diff --git a/.gitignore b/.gitignore
index cee10ae..f985abd 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,3 +1,10 @@
sftp-config.json
*.o
-*.ko
\ No newline at end of file
+*.ko
+.*.o.cmd
+.88x2bu.ko.cmd
+.88x2bu.mod.cmd
+88x2bu.mod
+88x2bu.mod.c
+Module.symvers
+modules.order
diff --git a/Makefile b/Makefile
index f7cbfa5..3f53ff1 100644
--- a/Makefile
+++ b/Makefile
@@ -7,16 +7,22 @@ EXTRA_CFLAGS += -O1
#EXTRA_CFLAGS += -pedantic
#EXTRA_CFLAGS += -Wshadow -Wpointer-arith -Wcast-qual -Wstrict-prototypes -Wmissing-prototypes
-PLATFORM = LINUX
EXTRA_CFLAGS += -Wno-unused-variable
EXTRA_CFLAGS += -Wno-unused-value
EXTRA_CFLAGS += -Wno-unused-label
EXTRA_CFLAGS += -Wno-unused-parameter
EXTRA_CFLAGS += -Wno-unused-function
EXTRA_CFLAGS += -Wno-unused
+#EXTRA_CFLAGS += -Wno-uninitialized
+
+GCC_VER_49 := $(shell echo `$(CC) -dumpversion | cut -f1-2 -d.` \>= 4.9 | bc )
+ifeq ($(GCC_VER_49),1)
+EXTRA_CFLAGS += -Wno-date-time # Fix compile error && warning on gcc 4.9 and later
+endif
+
+EXTRA_CFLAGS += -Wno-vla
EXTRA_CFLAGS += -I$(src)/include
-EXTRA_CFLAGS += -I$(src)/hal/phydm
EXTRA_LDFLAGS += --strip-debug
@@ -35,7 +41,6 @@ CONFIG_RTL8188F = n
CONFIG_RTL8822B = y
CONFIG_RTL8723D = n
CONFIG_RTL8821C = n
-
######################### Interface ###########################
CONFIG_USB_HCI = y
CONFIG_PCI_HCI = n
@@ -52,10 +57,11 @@ CONFIG_INTEL_WIDI = n
CONFIG_WAPI_SUPPORT = n
CONFIG_EFUSE_CONFIG_FILE = y
CONFIG_EXT_CLK = n
-CONFIG_TRAFFIC_PROTECT = y
+CONFIG_TRAFFIC_PROTECT = n
CONFIG_LOAD_PHY_PARA_FROM_FILE = y
-CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY = n
-CONFIG_CALIBRATE_TX_POWER_TO_MAX = n
+CONFIG_TXPWR_BY_RATE_EN = y
+CONFIG_TXPWR_LIMIT_EN = n
+CONFIG_RTW_CHPLAN = 0xFF
CONFIG_RTW_ADAPTIVITY_EN = disable
CONFIG_RTW_ADAPTIVITY_MODE = normal
CONFIG_SIGNAL_SCALE_MAPPING = n
@@ -66,15 +72,21 @@ CONFIG_TDLS = n
CONFIG_WIFI_MONITOR = n
CONFIG_MCC_MODE = n
CONFIG_APPEND_VENDOR_IE_ENABLE = n
+CONFIG_RTW_NAPI = y
+CONFIG_RTW_GRO = y
+CONFIG_RTW_NETIF_SG = n
+CONFIG_RTW_IPCAM_APPLICATION = n
+CONFIG_RTW_REPEATER_SON = n
+CONFIG_RTW_WIFI_HAL = y
########################## Debug ###########################
CONFIG_RTW_DEBUG = y
# default log level is _DRV_INFO_ = 4,
# please refer to "How_to_set_driver_debug_log_level.doc" to set the available level.
-CONFIG_RTW_LOG_LEVEL = 4
+CONFIG_RTW_LOG_LEVEL = 0
######################## Wake On Lan ##########################
CONFIG_WOWLAN = n
+CONFIG_WAKEUP_TYPE = 0x7 #bit2: deauth, bit1: unicast, bit0: magic pkt.
CONFIG_GPIO_WAKEUP = n
-CONFIG_DEFAULT_PATTERNS_EN = n
CONFIG_WAKEUP_GPIO_IDX = default
CONFIG_HIGH_ACTIVE = n
CONFIG_PNO_SUPPORT = n
@@ -85,8 +97,8 @@ CONFIG_RTW_SDIO_PM_KEEP_POWER = y
###################### MP HW TX MODE FOR VHT #######################
CONFIG_MP_VHT_HW_TX_MODE = n
###################### Platform Related #######################
-CONFIG_PLATFORM_ARM_RPI = n
CONFIG_PLATFORM_I386_PC = y
+CONFIG_PLATFORM_ARM_RPI = n
CONFIG_PLATFORM_ANDROID_X86 = n
CONFIG_PLATFORM_ANDROID_INTEL_X86 = n
CONFIG_PLATFORM_JB_X86 = n
@@ -131,9 +143,6 @@ CONFIG_PLATFORM_ARM_SUN50IW1P1 = n
CONFIG_PLATFORM_ARM_RTD299X = n
CONFIG_PLATFORM_ARM_SPREADTRUM_6820 = n
CONFIG_PLATFORM_ARM_SPREADTRUM_8810 = n
-
-# Setting to n
-CONFIG_PLATFORM_AML = y
CONFIG_PLATFORM_ARM_WMT = n
CONFIG_PLATFORM_TI_DM365 = n
CONFIG_PLATFORM_MOZART = n
@@ -141,20 +150,18 @@ CONFIG_PLATFORM_RTK119X = n
CONFIG_PLATFORM_RTK129X = n
CONFIG_PLATFORM_NOVATEK_NT72668 = n
CONFIG_PLATFORM_HISILICON = n
+CONFIG_PLATFORM_HISILICON_HI3798 = n
+CONFIG_PLATFORM_NV_TK1 = n
+CONFIG_PLATFORM_NV_TK1_UBUNTU = n
+CONFIG_PLATFORM_RTL8197D = n
+CONFIG_PLATFORM_AML_S905 = n
+CONFIG_PLATFORM_ZTE_ZX296716 = n
###############################################################
CONFIG_DRVEXT_MODULE = n
export TopDIR ?= $(shell pwd)
-ifeq ($(CONFIG_PLATFORM_AML), y)
-EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -fno-pic
-EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211
-EXTRA_CFLAGS += -DCONFIG_P2P_IPS -DRTW_USE_CFG80211_STA_EVENT
-EXTRA_CFLAGS += -DCONFIG_LPS_SLOW_TRANSITION
-EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
-endif
-
########### COMMON #################################
ifeq ($(CONFIG_GSPI_HCI), y)
HCI_NAME = gspi
@@ -185,7 +192,8 @@ _OS_INTFS_FILES := os_dep/osdep_service.o \
os_dep/linux/rtw_cfgvendor.o \
os_dep/linux/wifi_regd.o \
os_dep/linux/rtw_android.o \
- os_dep/linux/rtw_proc.o
+ os_dep/linux/rtw_proc.o \
+ os_dep/linux/rtw_rhashtable.o
ifeq ($(CONFIG_MP_INCLUDED), y)
_OS_INTFS_FILES += os_dep/linux/ioctl_mp.o
@@ -207,59 +215,20 @@ _HAL_INTFS_FILES := hal/hal_intf.o \
hal/hal_com_phycfg.o \
hal/hal_phy.o \
hal/hal_dm.o \
+ hal/hal_dm_acs.o \
+ hal/hal_btcoex_wifionly.o \
hal/hal_btcoex.o \
hal/hal_mp.o \
hal/hal_mcc.o \
hal/hal_hci/hal_$(HCI_NAME).o \
+ hal/led/hal_led.o \
hal/led/hal_$(HCI_NAME)_led.o
-
-_OUTSRC_FILES := hal/phydm/phydm_debug.o \
- hal/phydm/phydm_antdiv.o\
- hal/phydm/phydm_antdect.o\
- hal/phydm/phydm_interface.o\
- hal/phydm/phydm_hwconfig.o\
- hal/phydm/phydm.o\
- hal/phydm/halphyrf_ce.o\
- hal/phydm/phydm_edcaturbocheck.o\
- hal/phydm/phydm_dig.o\
- hal/phydm/phydm_pathdiv.o\
- hal/phydm/phydm_rainfo.o\
- hal/phydm/phydm_dynamicbbpowersaving.o\
- hal/phydm/phydm_powertracking_ce.o\
- hal/phydm/phydm_dynamictxpower.o\
- hal/phydm/phydm_adaptivity.o\
- hal/phydm/phydm_cfotracking.o\
- hal/phydm/phydm_noisemonitor.o\
- hal/phydm/phydm_acs.o\
- hal/phydm/phydm_beamforming.o\
- hal/phydm/phydm_dfs.o\
- hal/phydm/txbf/halcomtxbf.o\
- hal/phydm/txbf/haltxbfinterface.o\
- hal/phydm/phydm_kfree.o\
- hal/phydm/phydm_ccx.o
-
EXTRA_CFLAGS += -I$(src)/platform
_PLATFORM_FILES := platform/platform_ops.o
-ifeq ($(CONFIG_BT_COEXIST), y)
EXTRA_CFLAGS += -I$(src)/hal/btc
-_OUTSRC_FILES += hal/btc/HalBtc8192e1Ant.o \
- hal/btc/HalBtc8192e2Ant.o \
- hal/btc/HalBtc8723b1Ant.o \
- hal/btc/HalBtc8723b2Ant.o \
- hal/btc/HalBtc8812a1Ant.o \
- hal/btc/HalBtc8812a2Ant.o \
- hal/btc/HalBtc8821a1Ant.o \
- hal/btc/HalBtc8821a2Ant.o \
- hal/btc/HalBtc8821aCsr2Ant.o \
- hal/btc/HalBtc8703b1Ant.o \
- hal/btc/halbtc8723d1ant.o \
- hal/btc/halbtc8723d2ant.o \
- hal/btc/HalBtc8822b1Ant.o
-endif
-
########### HAL_RTL8188E #################################
ifeq ($(CONFIG_RTL8188E), y)
@@ -293,6 +262,8 @@ _HAL_INTFS_FILES += hal/$(RTL871X)/$(RTL871X)_hal_init.o \
hal/$(RTL871X)/$(RTL871X)_dm.o \
hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
hal/$(RTL871X)/$(RTL871X)_cmd.o \
+ hal/$(RTL871X)/hal8188e_s_fw.o \
+ hal/$(RTL871X)/hal8188e_t_fw.o \
hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \
hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \
@@ -318,17 +289,6 @@ ifeq ($(CONFIG_SDIO_HCI), y)
_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188E_SDIO.o
endif
-#hal/OUTSRC/$(RTL871X)/Hal8188EFWImg_CE.o
-_OUTSRC_FILES += hal/phydm/$(RTL871X)/halhwimg8188e_mac.o\
- hal/phydm/$(RTL871X)/halhwimg8188e_bb.o\
- hal/phydm/$(RTL871X)/halhwimg8188e_rf.o\
- hal/phydm/$(RTL871X)/halhwimg8188e_t_fw.o\
- hal/phydm/$(RTL871X)/halhwimg8188e_s_fw.o\
- hal/phydm/$(RTL871X)/halphyrf_8188e_ce.o\
- hal/phydm/$(RTL871X)/phydm_regconfig8188e.o\
- hal/phydm/$(RTL871X)/hal8188erateadaptive.o\
- hal/phydm/$(RTL871X)/phydm_rtl8188e.o
-
endif
########### HAL_RTL8192E #################################
@@ -358,6 +318,7 @@ _HAL_INTFS_FILES += hal/$(RTL871X)/$(RTL871X)_hal_init.o \
hal/$(RTL871X)/$(RTL871X)_dm.o \
hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
hal/$(RTL871X)/$(RTL871X)_cmd.o \
+ hal/$(RTL871X)/hal8192e_fw.o \
hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \
hal/$(RTL871X)/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \
@@ -379,15 +340,14 @@ endif
ifeq ($(CONFIG_PCI_HCI), y)
_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8192E_PCIE.o
endif
+ifeq ($(CONFIG_SDIO_HCI), y)
+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8192E_SDIO.o
+endif
-#hal/OUTSRC/$(RTL871X)/HalHWImg8188E_FW.o
-_OUTSRC_FILES += hal/phydm/$(RTL871X)/halhwimg8192e_mac.o\
- hal/phydm/$(RTL871X)/halhwimg8192e_bb.o\
- hal/phydm/$(RTL871X)/halhwimg8192e_rf.o\
- hal/phydm/$(RTL871X)/halhwimg8192e_fw.o\
- hal/phydm/$(RTL871X)/halphyrf_8192e_ce.o\
- hal/phydm/$(RTL871X)/phydm_regconfig8192e.o\
- hal/phydm/$(RTL871X)/phydm_rtl8192e.o
+ifeq ($(CONFIG_BT_COEXIST), y)
+_BTC_FILES += hal/btc/halbtc8192e1ant.o \
+ hal/btc/halbtc8192e2ant.o
+endif
endif
@@ -448,18 +408,14 @@ endif
ifeq ($(CONFIG_PCI_HCI), y)
_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8821A_PCIE.o
endif
+ifeq ($(CONFIG_SDIO_HCI), y)
+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8821A_SDIO.o
+endif
endif
ifeq ($(CONFIG_RTL8812A), y)
EXTRA_CFLAGS += -DCONFIG_RTL8812A
-_OUTSRC_FILES += hal/phydm/$(RTL871X)/halhwimg8812a_fw.o\
- hal/phydm/$(RTL871X)/halhwimg8812a_mac.o\
- hal/phydm/$(RTL871X)/halhwimg8812a_bb.o\
- hal/phydm/$(RTL871X)/halhwimg8812a_rf.o\
- hal/phydm/$(RTL871X)/halphyrf_8812a_ce.o\
- hal/phydm/$(RTL871X)/phydm_regconfig8812a.o\
- hal/phydm/$(RTL871X)/phydm_rtl8812a.o\
- hal/phydm/txbf/haltxbfjaguar.o
+_HAL_INTFS_FILES += hal/rtl8812a/hal8812a_fw.o
endif
ifeq ($(CONFIG_RTL8821A), y)
@@ -484,92 +440,23 @@ endif
endif
EXTRA_CFLAGS += -DCONFIG_RTL8821A
-_OUTSRC_FILES += hal/phydm/rtl8821a/halhwimg8821a_fw.o\
- hal/phydm/rtl8821a/halhwimg8821a_mac.o\
- hal/phydm/rtl8821a/halhwimg8821a_bb.o\
- hal/phydm/rtl8821a/halhwimg8821a_rf.o\
- hal/phydm/rtl8812a/halphyrf_8812a_ce.o\
- hal/phydm/rtl8821a/halphyrf_8821a_ce.o\
- hal/phydm/rtl8821a/phydm_regconfig8821a.o\
- hal/phydm/rtl8821a/phydm_rtl8821a.o\
- hal/phydm/rtl8821a/phydm_iqk_8821a_ce.o\
- hal/phydm/txbf/haltxbfjaguar.o
-
-endif
+_HAL_INTFS_FILES += hal/rtl8812a/hal8821a_fw.o
+
endif
-RTL871X := rtl8822b
-EXTRA_CFLAGS += -DCONFIG_RTL8822B
-
-ifeq ($(CONFIG_USB_HCI), y)
-MODULE_NAME = 8822bu
-endif
-ifeq ($(CONFIG_PCI_HCI), y)
-MODULE_NAME = 8822be
+ifeq ($(CONFIG_BT_COEXIST), y)
+ifeq ($(CONFIG_RTL8812A), y)
+_BTC_FILES += hal/btc/halbtc8812a1ant.o \
+ hal/btc/halbtc8812a2ant.o
endif
-ifeq ($(CONFIG_SDIO_HCI), y)
-MODULE_NAME = 8822bs
+ifeq ($(CONFIG_RTL8821A), y)
+_BTC_FILES += hal/btc/halbtc8821a1ant.o \
+ hal/btc/halbtc8821a2ant.o
endif
-
-ifeq ($(CONFIG_MP_INCLUDED), y)
-### 8822B Default Enable VHT MP HW TX MODE ###
-#EXTRA_CFLAGS += -DCONFIG_MP_VHT_HW_TX_MODE
-#CONFIG_MP_VHT_HW_TX_MODE = y
endif
-_HAL_HALMAC_FILES += hal/halmac/halmac_api.o
-
-_HAL_HALMAC_FILES += hal/halmac/halmac_88xx/halmac_api_88xx.o \
- hal/halmac/halmac_88xx/halmac_func_88xx.o \
- hal/halmac/halmac_88xx/halmac_api_88xx_usb.o \
- hal/halmac/halmac_88xx/halmac_api_88xx_sdio.o \
- hal/halmac/halmac_88xx/halmac_api_88xx_pcie.o
-
-_HAL_HALMAC_FILES += hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_pwr_seq.o \
- hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b.o \
- hal/halmac/halmac_88xx/halmac_8822b/halmac_func_8822b.o \
- hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_usb.o \
- hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_sdio.o \
- hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_pcie.o
-
-_HAL_INTFS_FILES += hal/hal_halmac.o
-
-_HAL_INTFS_FILES += hal/rtl8822b/rtl8822b_halinit.o \
- hal/rtl8822b/rtl8822b_mac.o \
- hal/rtl8822b/rtl8822b_cmd.o \
- hal/rtl8822b/rtl8822b_phy.o \
- hal/rtl8822b/rtl8822b_ops.o
-
-_HAL_INTFS_FILES += hal/rtl8822b/$(HCI_NAME)/rtl$(MODULE_NAME)_halinit.o \
- hal/rtl8822b/$(HCI_NAME)/rtl$(MODULE_NAME)_halmac.o \
- hal/rtl8822b/$(HCI_NAME)/rtl$(MODULE_NAME)_io.o \
- hal/rtl8822b/$(HCI_NAME)/rtl$(MODULE_NAME)_xmit.o \
- hal/rtl8822b/$(HCI_NAME)/rtl$(MODULE_NAME)_recv.o \
- hal/rtl8822b/$(HCI_NAME)/rtl$(MODULE_NAME)_led.o \
- hal/rtl8822b/$(HCI_NAME)/rtl$(MODULE_NAME)_ops.o
-
-ifeq ($(CONFIG_USB_HCI), y)
-_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8822B_USB.o
-endif
-ifeq ($(CONFIG_PCI_HCI), y)
-_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8822B_PCIE.o
endif
-ifeq ($(CONFIG_SDIO_HCI), y)
-#_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8822B_SDIO.o
-endif
-
-_OUTSRC_FILES += hal/phydm/rtl8822b/halhwimg8822b_bb.o \
- hal/phydm/rtl8822b/halhwimg8822b_fw.o \
- hal/phydm/rtl8822b/halhwimg8822b_mac.o \
- hal/phydm/rtl8822b/halhwimg8822b_rf.o \
- hal/phydm/rtl8822b/halphyrf_8822b.o \
- hal/phydm/rtl8822b/phydm_hal_api8822b.o \
- hal/phydm/rtl8822b/phydm_iqk_8822b.o \
- hal/phydm/rtl8822b/phydm_regconfig8822b.o \
- hal/phydm/rtl8822b/phydm_rtl8822b.o
-
-_HAL_INTFS_FILES += $(_HAL_HALMAC_FILES)
########### HAL_RTL8723B #################################
ifeq ($(CONFIG_RTL8723B), y)
@@ -597,7 +484,7 @@ _HAL_INTFS_FILES += hal/$(RTL871X)/$(RTL871X)_hal_init.o \
hal/$(RTL871X)/$(RTL871X)_dm.o \
hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
hal/$(RTL871X)/$(RTL871X)_cmd.o \
-
+ hal/$(RTL871X)/hal8723b_fw.o
_HAL_INTFS_FILES += \
hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
@@ -617,23 +504,23 @@ endif
ifeq ($(CONFIG_PCI_HCI), y)
_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8723B_PCIE.o
endif
+ifeq ($(CONFIG_SDIO_HCI), y)
+_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8723B_SDIO.o
+endif
-_OUTSRC_FILES += hal/phydm/$(RTL871X)/halhwimg8723b_bb.o\
- hal/phydm/$(RTL871X)/halhwimg8723b_mac.o\
- hal/phydm/$(RTL871X)/halhwimg8723b_rf.o\
- hal/phydm/$(RTL871X)/halhwimg8723b_fw.o\
- hal/phydm/$(RTL871X)/halhwimg8723b_mp.o\
- hal/phydm/$(RTL871X)/phydm_regconfig8723b.o\
- hal/phydm/$(RTL871X)/halphyrf_8723b_ce.o\
- hal/phydm/$(RTL871X)/phydm_rtl8723b.o
+_BTC_FILES += hal/btc/halbtc8723bwifionly.o
+ifeq ($(CONFIG_BT_COEXIST), y)
+_BTC_FILES += hal/btc/halbtc8723b1ant.o \
+ hal/btc/halbtc8723b2ant.o
+endif
endif
########### HAL_RTL8814A #################################
ifeq ($(CONFIG_RTL8814A), y)
## ADD NEW VHT MP HW TX MODE ##
-EXTRA_CFLAGS += -DCONFIG_MP_VHT_HW_TX_MODE
-CONFIG_MP_VHT_HW_TX_MODE = y
+#EXTRA_CFLAGS += -DCONFIG_MP_VHT_HW_TX_MODE
+#CONFIG_MP_VHT_HW_TX_MODE = y
##########################################
RTL871X = rtl8814a
ifeq ($(CONFIG_USB_HCI), y)
@@ -659,6 +546,7 @@ _HAL_INTFS_FILES += hal/$(RTL871X)/$(RTL871X)_hal_init.o \
hal/$(RTL871X)/$(RTL871X)_dm.o \
hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
hal/$(RTL871X)/$(RTL871X)_cmd.o \
+ hal/$(RTL871X)/hal8814a_fw.o
_HAL_INTFS_FILES += \
@@ -684,16 +572,6 @@ ifeq ($(CONFIG_PCI_HCI), y)
_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8814A_PCIE.o
endif
-_OUTSRC_FILES += hal/phydm/$(RTL871X)/halhwimg8814a_bb.o\
- hal/phydm/$(RTL871X)/halhwimg8814a_mac.o\
- hal/phydm/$(RTL871X)/halhwimg8814a_rf.o\
- hal/phydm/$(RTL871X)/halhwimg8814a_fw.o\
- hal/phydm/$(RTL871X)/phydm_iqk_8814a.o\
- hal/phydm/$(RTL871X)/phydm_regconfig8814a.o\
- hal/phydm/$(RTL871X)/halphyrf_8814a_ce.o\
- hal/phydm/$(RTL871X)/phydm_rtl8814a.o\
- hal/phydm/txbf/haltxbf8814a.o
-
endif
########### HAL_RTL8723C #################################
@@ -725,7 +603,7 @@ _HAL_INTFS_FILES += hal/$(RTL871X)/$(RTL871X)_hal_init.o \
hal/$(RTL871X)/$(RTL871X)_dm.o \
hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
hal/$(RTL871X)/$(RTL871X)_cmd.o \
-
+ hal/$(RTL871X)/hal8703b_fw.o
_HAL_INTFS_FILES += \
hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
@@ -746,12 +624,10 @@ ifeq ($(CONFIG_PCI_HCI), y)
_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8703B_PCIE.o
endif
-_OUTSRC_FILES += hal/phydm/$(RTL871X)/halhwimg8703b_bb.o\
- hal/phydm/$(RTL871X)/halhwimg8703b_mac.o\
- hal/phydm/$(RTL871X)/halhwimg8703b_rf.o\
- hal/phydm/$(RTL871X)/halhwimg8703b_fw.o\
- hal/phydm/$(RTL871X)/phydm_regconfig8703b.o\
- hal/phydm/$(RTL871X)/halphyrf_8703b.o
+ifeq ($(CONFIG_BT_COEXIST), y)
+_BTC_FILES += hal/btc/halbtc8703b1ant.o
+endif
+
endif
########### HAL_RTL8723D #################################
@@ -783,6 +659,7 @@ _HAL_INTFS_FILES += hal/$(RTL871X)/$(RTL871X)_hal_init.o \
hal/$(RTL871X)/$(RTL871X)_dm.o \
hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
hal/$(RTL871X)/$(RTL871X)_cmd.o \
+ hal/$(RTL871X)/hal8723d_fw.o \
hal/$(RTL871X)/$(RTL871X)_lps_poff.o
@@ -805,13 +682,11 @@ ifeq ($(CONFIG_PCI_HCI), y)
_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8723D_PCIE.o
endif
-_OUTSRC_FILES += hal/phydm/$(RTL871X)/halhwimg8723d_bb.o\
- hal/phydm/$(RTL871X)/halhwimg8723d_mac.o\
- hal/phydm/$(RTL871X)/halhwimg8723d_rf.o\
- hal/phydm/$(RTL871X)/halhwimg8723d_fw.o\
- hal/phydm/$(RTL871X)/phydm_regconfig8723d.o\
- hal/phydm/$(RTL871X)/phydm_rtl8723d.o\
- hal/phydm/$(RTL871X)/halphyrf_8723d.o
+ifeq ($(CONFIG_BT_COEXIST), y)
+_BTC_FILES += hal/btc/halbtc8723d1ant.o \
+ hal/btc/halbtc8723d2ant.o
+endif
+
endif
########### HAL_RTL8188F #################################
@@ -840,7 +715,7 @@ _HAL_INTFS_FILES += hal/$(RTL871X)/$(RTL871X)_hal_init.o \
hal/$(RTL871X)/$(RTL871X)_dm.o \
hal/$(RTL871X)/$(RTL871X)_rxdesc.o \
hal/$(RTL871X)/$(RTL871X)_cmd.o \
-
+ hal/$(RTL871X)/hal8188f_fw.o
_HAL_INTFS_FILES += \
hal/$(RTL871X)/$(HCI_NAME)/$(HCI_NAME)_halinit.o \
@@ -862,32 +737,40 @@ ifeq ($(CONFIG_SDIO_HCI), y)
_HAL_INTFS_FILES +=hal/efuse/$(RTL871X)/HalEfuseMask8188F_SDIO.o
endif
-_OUTSRC_FILES += hal/phydm/$(RTL871X)/halhwimg8188f_bb.o\
- hal/phydm/$(RTL871X)/halhwimg8188f_mac.o\
- hal/phydm/$(RTL871X)/halhwimg8188f_rf.o\
- hal/phydm/$(RTL871X)/halhwimg8188f_fw.o\
- hal/phydm/$(RTL871X)/phydm_regconfig8188f.o\
- hal/phydm/$(RTL871X)/halphyrf_8188f.o \
- hal/phydm/$(RTL871X)/phydm_rtl8188f.o
-
endif
########### HAL_RTL8822B #################################
-#ifeq ($(CONFIG_RTL8822B), y)
-#include $(TopDIR)/rtl8822b.mk
-#endif
+ifeq ($(CONFIG_RTL8822B), y)
+RTL871X := rtl8822b
+ifeq ($(CONFIG_USB_HCI), y)
+ifeq ($(CONFIG_BT_COEXIST), n)
+MODULE_NAME = 8812bu
+else
+MODULE_NAME = 88x2bu
+endif
+endif
+ifeq ($(CONFIG_PCI_HCI), y)
+MODULE_NAME = 88x2be
+endif
+ifeq ($(CONFIG_SDIO_HCI), y)
+MODULE_NAME = 88x2bs
+endif
+endif
########### HAL_RTL8821C #################################
ifeq ($(CONFIG_RTL8821C), y)
-include $(TopDIR)/rtl8821c.mk
-
-_OUTSRC_FILES += hal/phydm/rtl8821c/halhwimg8821c_testchip_bb.o \
- hal/phydm/rtl8821c/halhwimg8821c_testchip_mac.o \
- hal/phydm/rtl8821c/halhwimg8821c_testchip_rf.o \
- hal/phydm/rtl8821c/phydm_hal_api8821c.o \
- hal/phydm/rtl8821c/phydm_regconfig8821c.o
+RTL871X := rtl8821c
+ifeq ($(CONFIG_USB_HCI), y)
+MODULE_NAME = 8821cu
+endif
+ifeq ($(CONFIG_PCI_HCI), y)
+MODULE_NAME = 8821ce
+endif
+ifeq ($(CONFIG_SDIO_HCI), y)
+MODULE_NAME = 8821cs
endif
+endif
########### AUTO_CFG #################################
ifeq ($(CONFIG_AUTOCFG_CP), y)
@@ -981,8 +864,28 @@ endif
ifeq ($(CONFIG_LOAD_PHY_PARA_FROM_FILE), y)
EXTRA_CFLAGS += -DCONFIG_LOAD_PHY_PARA_FROM_FILE
-EXTRA_CFLAGS += -DREALTEK_CONFIG_PATH=\"/etc/firmware/\"
-#EXTRA_CFLAGS += -DREALTEK_CONFIG_PATH=\"$(TopDIR)/\"
+#EXTRA_CFLAGS += -DREALTEK_CONFIG_PATH_WITH_IC_NAME_FOLDER
+EXTRA_CFLAGS += -DREALTEK_CONFIG_PATH=\"/lib/firmware/\"
+endif
+
+ifeq ($(CONFIG_TXPWR_BY_RATE_EN), n)
+EXTRA_CFLAGS += -DCONFIG_TXPWR_BY_RATE_EN=0
+else ifeq ($(CONFIG_TXPWR_BY_RATE_EN), y)
+EXTRA_CFLAGS += -DCONFIG_TXPWR_BY_RATE_EN=1
+else ifeq ($(CONFIG_TXPWR_BY_RATE_EN), auto)
+EXTRA_CFLAGS += -DCONFIG_TXPWR_BY_RATE_EN=2
+endif
+
+ifeq ($(CONFIG_TXPWR_LIMIT_EN), n)
+EXTRA_CFLAGS += -DCONFIG_TXPWR_LIMIT_EN=0
+else ifeq ($(CONFIG_TXPWR_LIMIT_EN), y)
+EXTRA_CFLAGS += -DCONFIG_TXPWR_LIMIT_EN=1
+else ifeq ($(CONFIG_TXPWR_LIMIT_EN), auto)
+EXTRA_CFLAGS += -DCONFIG_TXPWR_LIMIT_EN=2
+endif
+
+ifneq ($(CONFIG_RTW_CHPLAN), 0xFF)
+EXTRA_CFLAGS += -DCONFIG_RTW_CHPLAN=$(CONFIG_RTW_CHPLAN)
endif
ifeq ($(CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY), y)
@@ -1014,13 +917,10 @@ EXTRA_CFLAGS += -DCONFIG_IEEE80211W
endif
ifeq ($(CONFIG_WOWLAN), y)
-EXTRA_CFLAGS += -DCONFIG_WOWLAN
+EXTRA_CFLAGS += -DCONFIG_WOWLAN -DRTW_WAKEUP_EVENT=$(CONFIG_WAKEUP_TYPE)
ifeq ($(CONFIG_SDIO_HCI), y)
EXTRA_CFLAGS += -DCONFIG_RTW_SDIO_PM_KEEP_POWER
endif
-ifeq ($(CONFIG_DEFAULT_PATTERNS_EN), y)
-EXTRA_CFLAGS += -DCONFIG_DEFAULT_PATTERNS_EN
-endif
endif
ifeq ($(CONFIG_AP_WOWLAN), y)
@@ -1066,9 +966,6 @@ EXTRA_CFLAGS += -DCONFIG_BR_EXT
EXTRA_CFLAGS += '-DCONFIG_BR_EXT_BRNAME="'$(BR_NAME)'"'
endif
-ifeq ($(CONFIG_ANTENNA_DIVERSITY), y)
-EXTRA_CFLAGS += -DCONFIG_ANTENNA_DIVERSITY
-endif
ifeq ($(CONFIG_TDLS), y)
EXTRA_CFLAGS += -DCONFIG_TDLS
@@ -1082,6 +979,35 @@ ifeq ($(CONFIG_MCC_MODE), y)
EXTRA_CFLAGS += -DCONFIG_MCC_MODE
endif
+ifeq ($(CONFIG_RTW_NAPI), y)
+EXTRA_CFLAGS += -DCONFIG_RTW_NAPI
+endif
+
+ifeq ($(CONFIG_RTW_GRO), y)
+EXTRA_CFLAGS += -DCONFIG_RTW_GRO
+endif
+
+ifeq ($(CONFIG_RTW_REPEATER_SON), y)
+EXTRA_CFLAGS += -DCONFIG_RTW_REPEATER_SON
+endif
+
+ifeq ($(CONFIG_RTW_IPCAM_APPLICATION), y)
+EXTRA_CFLAGS += -DCONFIG_RTW_IPCAM_APPLICATION
+ifeq ($(CONFIG_WIFI_MONITOR), n)
+EXTRA_CFLAGS += -DCONFIG_WIFI_MONITOR
+endif
+endif
+
+ifeq ($(CONFIG_RTW_NETIF_SG), y)
+EXTRA_CFLAGS += -DCONFIG_RTW_NETIF_SG
+endif
+
+ifeq ($(CONFIG_RTW_WIFI_HAL), y)
+#EXTRA_CFLAGS += -DCONFIG_RTW_WIFI_HAL_DEBUG
+EXTRA_CFLAGS += -DCONFIG_RTW_WIFI_HAL
+EXTRA_CFLAGS += -DCONFIG_RTW_CFGVEDNOR_LLSTATS
+endif
+
ifeq ($(CONFIG_MP_VHT_HW_TX_MODE), y)
EXTRA_CFLAGS += -DCONFIG_MP_VHT_HW_TX_MODE
ifeq ($(CONFIG_PLATFORM_I386_PC), y)
@@ -1107,14 +1033,14 @@ EXTRA_CFLAGS += -DDM_ODM_SUPPORT_TYPE=0x04
ifeq ($(CONFIG_PLATFORM_I386_PC), y)
EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-EXTRA_CFLAGS += -DPLATFORM_LINUX
SUBARCH := $(shell uname -m | sed -e s/i.86/i386/)
ARCH ?= $(SUBARCH)
CROSS_COMPILE ?=
KVER := $(shell uname -r)
-KSRC := /lib/modules/$(KVER)/build
+KSRC ?= /lib/modules/$(KVER)/build
MODDESTDIR := /lib/modules/$(KVER)/kernel/drivers/net/wireless/
INSTALL_PREFIX :=
+STAGINGMODDIR := /lib/modules/$(KVER)/kernel/drivers/staging
endif
ifeq ($(CONFIG_PLATFORM_ARM_RPI), y)
@@ -1124,7 +1050,39 @@ EXTRA_CFLAGS += -DPLATFORM_LINUX
ARCH ?= arm
CROSS_COMPILE ?=
KVER ?= $(shell uname -r)
-KSRC := /lib/modules/$(KVER)/build
+KSRC ?= /lib/modules/$(KVER)/build
+MODDESTDIR := /lib/modules/$(KVER)/kernel/drivers/net/wireless/
+INSTALL_PREFIX :=
+endif
+
+ifeq ($(CONFIG_PLATFORM_NV_TK1), y)
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_NV_TK1
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+# default setting for Android 4.1, 4.2
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_P2P_IPS -DCONFIG_PLATFORM_ANDROID
+# Enable this for Android 5.0
+EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
+EXTRA_CFLAGS += -DRTW_VENDOR_EXT_SUPPORT
+EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC
+ARCH ?= arm
+
+CROSS_COMPILE := /mnt/newdisk/android_sdk/nvidia_tk1/android_L/prebuilts/gcc/linux-x86/arm/arm-eabi-4.8/bin/arm-eabi-
+KSRC ?=/mnt/newdisk/android_sdk/nvidia_tk1/android_L/out/target/product/shieldtablet/obj/KERNEL/
+MODULE_NAME = wlan
+endif
+
+ifeq ($(CONFIG_PLATFORM_NV_TK1_UBUNTU), y)
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_NV_TK1
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+
+ARCH ?= arm
+
+CROSS_COMPILE ?=
+KVER := $(shell uname -r)
+KSRC ?= /lib/modules/$(KVER)/build
MODDESTDIR := /lib/modules/$(KVER)/kernel/drivers/net/wireless/
INSTALL_PREFIX :=
endif
@@ -1136,20 +1094,98 @@ ARCH := $(R_ARCH)
#CROSS_COMPILE := arm-none-linux-gnueabi-
CROSS_COMPILE := $(R_CROSS_COMPILE)
KVER:= 3.4.0
-#KSRC := ../../../../build/out/kernel
-KSRC := $(KERNEL_BUILD_PATH)
+#KSRC ?= ../../../../build/out/kernel
+KSRC ?= $(KERNEL_BUILD_PATH)
MODULE_NAME :=wlan
endif
+ifeq ($(CONFIG_PLATFORM_ACTIONS_ATM705X), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+#EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC
+# default setting for Android 4.1, 4.2, 4.3, 4.4
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ACTIONS_ATM705X
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+
+# Enable this for Android 5.0
+EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
+
+ifeq ($(CONFIG_SDIO_HCI), y)
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
+_PLATFORM_FILES += platform/platform_arm_act_sdio.o
+endif
+
+ARCH := arm
+CROSS_COMPILE := /opt/arm-2011.09/bin/arm-none-linux-gnueabi-
+KSRC ?= /home/android_sdk/Action-semi/705a_android_L/android/kernel
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_SUN50IW1P1), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN50IW1P1
+EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
+# default setting for Android 4.1, 4.2
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+EXTRA_CFLAGS += -DCONFIG_RESUME_IN_WORKQUEUE
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
+
+# Enable this for Android 5.0
+EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
+
+ifeq ($(CONFIG_USB_HCI), y)
+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
+_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o
+endif
+ifeq ($(CONFIG_SDIO_HCI), y)
+_PLATFORM_FILES += platform/platform_ARM_SUN50IW1P1_sdio.o
+endif
+
+ARCH := arm64
+# ===Cross compile setting for Android 5.1(64) SDK ===
+CROSS_COMPILE := /home/android_sdk/Allwinner/a64/android-51/lichee/out/sun50iw1p1/android/common/buildroot/external-toolchain/bin/aarch64-linux-gnu-
+KSRC ?=/home/android_sdk/Allwinner/a64/android-51/lichee/linux-3.10/
+endif
ifeq ($(CONFIG_PLATFORM_TI_AM3517), y)
EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_SHUTTLE
CROSS_COMPILE := arm-eabi-
-KSRC := $(shell pwd)/../../../Android/kernel
+KSRC ?= $(shell pwd)/../../../Android/kernel
ARCH := arm
endif
+ifeq ($(CONFIG_PLATFORM_MSTAR_TITANIA12), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MSTAR -DCONFIG_PLATFORM_MSTAR_TITANIA12
+ARCH:=mips
+CROSS_COMPILE:= /usr/src/Mstar_kernel/mips-4.3/bin/mips-linux-gnu-
+KVER:= 2.6.28.9
+KSRC:= /usr/src/Mstar_kernel/2.6.28.9/
+endif
+
+ifeq ($(CONFIG_PLATFORM_MSTAR), y)
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_MSTAR
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_MSTAR_HIGH
+ifeq ($(CONFIG_USB_HCI), y)
+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX -DCONFIG_FIX_NR_BULKIN_BUFFER
+endif
+ARCH:=arm
+CROSS_COMPILE:= /usr/src/bin/arm-none-linux-gnueabi-
+KVER:= 3.1.10
+KSRC:= /usr/src/Mstar_kernel/3.1.10/
+endif
+
+ifeq ($(CONFIG_PLATFORM_ANDROID_X86), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+SUBARCH := $(shell uname -m | sed -e s/i.86/i386/)
+ARCH := $(SUBARCH)
+CROSS_COMPILE := /media/DATA-2/android-x86/ics-x86_20120130/prebuilt/linux-x86/toolchain/i686-unknown-linux-gnu-4.2.1/bin/i686-unknown-linux-gnu-
+KSRC ?= /media/DATA-2/android-x86/ics-x86_20120130/out/target/product/generic_x86/obj/kernel
+MODULE_NAME :=wlan
+endif
ifeq ($(CONFIG_PLATFORM_ANDROID_INTEL_X86), y)
EXTRA_CFLAGS += -DCONFIG_PLATFORM_ANDROID_INTEL_X86
@@ -1163,10 +1199,490 @@ EXTRA_CFLAGS += -DCONFIG_RESUME_IN_WORKQUEUE
endif
endif
+ifeq ($(CONFIG_PLATFORM_JB_X86), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+SUBARCH := $(shell uname -m | sed -e s/i.86/i386/)
+ARCH := $(SUBARCH)
+CROSS_COMPILE := /home/android_sdk/android-x86_JB/prebuilts/gcc/linux-x86/x86/i686-linux-android-4.7/bin/i686-linux-android-
+KSRC ?= /home/android_sdk/android-x86_JB/out/target/product/x86/obj/kernel/
+MODULE_NAME :=wlan
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_PXA2XX), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+ARCH := arm
+CROSS_COMPILE := arm-none-linux-gnueabi-
+KVER := 2.6.34.1
+KSRC ?= /usr/src/linux-2.6.34.1
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_S3C2K4), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+ARCH := arm
+CROSS_COMPILE := arm-linux-
+KVER := 2.6.24.7_$(ARCH)
+KSRC ?= /usr/src/kernels/linux-$(KVER)
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_S3C6K4), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+ARCH := arm
+CROSS_COMPILE := arm-none-linux-gnueabi-
+KVER := 2.6.34.1
+KSRC ?= /usr/src/linux-2.6.34.1
+endif
+
+ifeq ($(CONFIG_PLATFORM_RTD2880B), y)
+EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN -DCONFIG_PLATFORM_RTD2880B
+ARCH:=
+CROSS_COMPILE:=
+KVER:=
+KSRC:=
+endif
+
+ifeq ($(CONFIG_PLATFORM_MIPS_RMI), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+ARCH:=mips
+CROSS_COMPILE:=mipsisa32r2-uclibc-
+KVER:=
+KSRC:= /root/work/kernel_realtek
+endif
+
+ifeq ($(CONFIG_PLATFORM_MIPS_PLM), y)
+EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN
+ARCH:=mips
+CROSS_COMPILE:=mipsisa32r2-uclibc-
+KVER:=
+KSRC:= /root/work/kernel_realtek
+endif
+
+ifeq ($(CONFIG_PLATFORM_MSTAR389), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MSTAR389
+ARCH:=mips
+CROSS_COMPILE:= mips-linux-gnu-
+KVER:= 2.6.28.10
+KSRC:= /home/mstar/mstar_linux/2.6.28.9/
+endif
+
+ifeq ($(CONFIG_PLATFORM_MIPS_AR9132), y)
+EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN
+ARCH := mips
+CROSS_COMPILE := mips-openwrt-linux-
+KSRC ?= /home/alex/test_openwrt/tmp/linux-2.6.30.9
+endif
+
+ifeq ($(CONFIG_PLATFORM_DMP_PHILIPS), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DRTK_DMP_PLATFORM
+ARCH := mips
+#CROSS_COMPILE:=/usr/local/msdk-4.3.6-mips-EL-2.6.12.6-0.9.30.3/bin/mipsel-linux-
+CROSS_COMPILE:=/usr/local/toolchain_mipsel/bin/mipsel-linux-
+KSRC ?=/usr/local/Jupiter/linux-2.6.12
+endif
+
+ifeq ($(CONFIG_PLATFORM_RTK_DMP), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DRTK_DMP_PLATFORM -DCONFIG_WIRELESS_EXT
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
+ifeq ($(CONFIG_USB_HCI), y)
+_PLATFORM_FILES += platform/platform_RTK_DMP_usb.o
+endif
+ARCH:=mips
+CROSS_COMPILE:=mipsel-linux-
+KVER:=
+KSRC ?= /usr/src/DMP_Kernel/jupiter/linux-2.6.12
+endif
+
+ifeq ($(CONFIG_PLATFORM_MT53XX), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MT53XX
+ARCH:= arm
+CROSS_COMPILE:= arm11_mtk_le-
+KVER:= 2.6.27
+KSRC?= /proj/mtk00802/BD_Compare/BDP/Dev/BDP_V301/BDP_Linux/linux-2.6.27
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_MX51_241H), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_WISTRON_PLATFORM
+ARCH := arm
+CROSS_COMPILE := /opt/freescale/usr/local/gcc-4.1.2-glibc-2.5-nptl-3/arm-none-linux-gnueabi/bin/arm-none-linux-gnueabi-
+KVER := 2.6.31
+KSRC ?= /lib/modules/2.6.31-770-g0e46b52/source
+endif
+
+ifeq ($(CONFIG_PLATFORM_FS_MX61), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+ARCH := arm
+CROSS_COMPILE := /home/share/CusEnv/FreeScale/arm-eabi-4.4.3/bin/arm-eabi-
+KSRC ?= /home/share/CusEnv/FreeScale/FS_kernel_env
+endif
+
+
+
+ifeq ($(CONFIG_PLATFORM_ACTIONS_ATJ227X), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ACTIONS_ATJ227X
+ARCH := mips
+CROSS_COMPILE := /home/cnsd4/project/actions/tools-2.6.27/bin/mipsel-linux-gnu-
+KVER := 2.6.27
+KSRC ?= /home/cnsd4/project/actions/linux-2.6.27.28
+endif
+
+ifeq ($(CONFIG_PLATFORM_TI_DM365), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_TI_DM365
+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_RX
+EXTRA_CFLAGS += -DCONFIG_SINGLE_XMIT_BUF -DCONFIG_SINGLE_RECV_BUF
+ARCH := arm
+#CROSS_COMPILE := /home/cnsd4/Appro/mv_pro_5.0/montavista/pro/devkit/arm/v5t_le/bin/arm_v5t_le-
+#KSRC ?= /home/cnsd4/Appro/mv_pro_5.0/montavista/pro/devkit/lsp/ti-davinci/linux-dm365
+CROSS_COMPILE := /opt/montavista/pro5.0/devkit/arm/v5t_le/bin/arm-linux-
+KSRC:= /home/vivotek/lsp/DM365/kernel_platform/kernel/linux-2.6.18
+KERNELOUTPUT := ${PRODUCTDIR}/tmp
+KVER := 2.6.18
+endif
+
+ifeq ($(CONFIG_PLATFORM_MOZART), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MOZART
+ARCH := arm
+CROSS_COMPILE := /home/vivotek/lsp/mozart3v2/Mozart3e_Toolchain/build_arm_nofpu/usr/bin/arm-linux-
+KVER := $(shell uname -r)
+KSRC:= /opt/Vivotek/lsp/mozart3v2/kernel_platform/kernel/mozart_kernel-1.17
+KERNELOUTPUT := /home/pink/sample/ODM/IP8136W-VINT/tmp/kernel
+endif
+
+ifeq ($(CONFIG_PLATFORM_TEGRA3_CARDHU), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+# default setting for Android 4.1, 4.2
+EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+ARCH := arm
+CROSS_COMPILE := /home/android_sdk/nvidia/tegra-16r3-partner-android-4.1_20120723/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-
+KSRC ?= /home/android_sdk/nvidia/tegra-16r3-partner-android-4.1_20120723/out/target/product/cardhu/obj/KERNEL
+MODULE_NAME := wlan
+endif
+
+ifeq ($(CONFIG_PLATFORM_TEGRA4_DALMORE), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+# default setting for Android 4.1, 4.2
+EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+ARCH := arm
+CROSS_COMPILE := /home/android_sdk/nvidia/tegra-17r9-partner-android-4.2-dalmore_20130131/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-
+KSRC ?= /home/android_sdk/nvidia/tegra-17r9-partner-android-4.2-dalmore_20130131/out/target/product/dalmore/obj/KERNEL
+MODULE_NAME := wlan
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_TCC8900), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+ARCH := arm
+CROSS_COMPILE := /home/android_sdk/Telechips/SDK_2304_20110613/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-
+KSRC ?= /home/android_sdk/Telechips/SDK_2304_20110613/kernel
+MODULE_NAME := wlan
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_TCC8920), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+ARCH := arm
+CROSS_COMPILE := /home/android_sdk/Telechips/v12.06_r1-tcc-android-4.0.4/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-
+KSRC ?= /home/android_sdk/Telechips/v12.06_r1-tcc-android-4.0.4/kernel
+MODULE_NAME := wlan
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_TCC8920_JB42), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+# default setting for Android 4.1, 4.2
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+ARCH := arm
+CROSS_COMPILE := /home/android_sdk/Telechips/v13.03_r1-tcc-android-4.2.2_ds_patched/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-
+KSRC ?= /home/android_sdk/Telechips/v13.03_r1-tcc-android-4.2.2_ds_patched/kernel
+MODULE_NAME := wlan
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_RK2818), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_ROCKCHIPS
+ARCH := arm
+CROSS_COMPILE := /usr/src/release_fae_version/toolchain/arm-eabi-4.4.0/bin/arm-eabi-
+KSRC ?= /usr/src/release_fae_version/kernel25_A7_281x
+MODULE_NAME := wlan
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_RK3188), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_ROCKCHIPS
+# default setting for Android 4.1, 4.2, 4.3, 4.4
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+# default setting for Power control
+EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC
+EXTRA_CFLAGS += -DRTW_SUPPORT_PLATFORM_SHUTDOWN
+# default setting for Special function
+ARCH := arm
+CROSS_COMPILE := /home/android_sdk/Rockchip/Rk3188/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-
+KSRC ?= /home/android_sdk/Rockchip/Rk3188/kernel
+MODULE_NAME := wlan
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_RK3066), y)
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_RK3066
+EXTRA_CFLAGS += -DRTW_ENABLE_WIFI_CONTROL_FUNC
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211
+ifeq ($(CONFIG_SDIO_HCI), y)
+EXTRA_CFLAGS += -DRTW_SUPPORT_PLATFORM_SHUTDOWN
+endif
+EXTRA_CFLAGS += -fno-pic
+ARCH := arm
+CROSS_COMPILE := /home/android_sdk/Rockchip/rk3066_20130607/prebuilts/gcc/linux-x86/arm/arm-linux-androideabi-4.6/bin/arm-linux-androideabi-
+#CROSS_COMPILE := /home/android_sdk/Rockchip/Rk3066sdk/prebuilts/gcc/linux-x86/arm/arm-linux-androideabi-4.6/bin/arm-linux-androideabi-
+KSRC ?= /home/android_sdk/Rockchip/Rk3066sdk/kernel
+MODULE_NAME :=wlan
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_URBETTER), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN #-DCONFIG_MINIMAL_MEMORY_USAGE
+ARCH := arm
+CROSS_COMPILE := /media/DATA-1/urbetter/arm-2009q3/bin/arm-none-linux-gnueabi-
+KSRC ?= /media/DATA-1/urbetter/ics-urbetter/kernel
+MODULE_NAME := wlan
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_TI_PANDA), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN #-DCONFIG_MINIMAL_MEMORY_USAGE
+ARCH := arm
+#CROSS_COMPILE := /media/DATA-1/aosp/ics-aosp_20111227/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-
+#KSRC ?= /media/DATA-1/aosp/android-omap-panda-3.0_20120104
+CROSS_COMPILE := /media/DATA-1/android-4.0/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi-
+KSRC ?= /media/DATA-1/android-4.0/panda_kernel/omap
+MODULE_NAME := wlan
+endif
+
+ifeq ($(CONFIG_PLATFORM_MIPS_JZ4760), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_MINIMAL_MEMORY_USAGE
+ARCH ?= mips
+CROSS_COMPILE ?= /mnt/sdb5/Ingenic/Umido/mips-4.3/bin/mips-linux-gnu-
+KSRC ?= /mnt/sdb5/Ingenic/Umido/kernel
+endif
+
+ifeq ($(CONFIG_PLATFORM_SZEBOOK), y)
+EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN
+ARCH:=arm
+CROSS_COMPILE:=/opt/crosstool2/bin/armeb-unknown-linux-gnueabi-
+KVER:= 2.6.31.6
+KSRC:= ../code/linux-2.6.31.6-2020/
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_SUNxI), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUNxI
+# default setting for Android 4.1, 4.2
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
+ifeq ($(CONFIG_USB_HCI), y)
+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
+_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o
+endif
+ifeq ($(CONFIG_SDIO_HCI), y)
+# default setting for A10-EVB mmc0
+#EXTRA_CFLAGS += -DCONFIG_WITS_EVB_V13
+_PLATFORM_FILES += platform/platform_ARM_SUNxI_sdio.o
+endif
+
+ARCH := arm
+#CROSS_COMPILE := arm-none-linux-gnueabi-
+CROSS_COMPILE=/home/android_sdk/Allwinner/a10/android-jb42/lichee-jb42/buildroot/output/external-toolchain/bin/arm-none-linux-gnueabi-
+KVER := 3.0.8
+#KSRC:= ../lichee/linux-3.0/
+KSRC=/home/android_sdk/Allwinner/a10/android-jb42/lichee-jb42/linux-3.0
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_SUN6I), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN6I
+EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
+# default setting for Android 4.1, 4.2, 4.3, 4.4
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+EXTRA_CFLAGS += -DCONFIG_QOS_OPTIMIZATION
+
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
+ifeq ($(CONFIG_USB_HCI), y)
+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
+_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o
+endif
+ifeq ($(CONFIG_SDIO_HCI), y)
+# default setting for A31-EVB mmc0
+EXTRA_CFLAGS += -DCONFIG_A31_EVB
+_PLATFORM_FILES += platform/platform_ARM_SUNnI_sdio.o
+endif
+
+ARCH := arm
+#Android-JB42
+#CROSS_COMPILE := /home/android_sdk/Allwinner/a31/android-jb42/lichee/buildroot/output/external-toolchain/bin/arm-linux-gnueabi-
+#KSRC ?=/home/android_sdk/Allwinner/a31/android-jb42/lichee/linux-3.3
+#ifeq ($(CONFIG_USB_HCI), y)
+#MODULE_NAME := 8188eu_sw
+#endif
+# ==== Cross compile setting for kitkat-a3x_v4.5 =====
+CROSS_COMPILE := /home/android_sdk/Allwinner/a31/kitkat-a3x_v4.5/lichee/buildroot/output/external-toolchain/bin/arm-linux-gnueabi-
+KSRC ?=/home/android_sdk/Allwinner/a31/kitkat-a3x_v4.5/lichee/linux-3.3
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_SUN7I), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN7I
+EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
+# default setting for Android 4.1, 4.2, 4.3, 4.4
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+EXTRA_CFLAGS += -DCONFIG_QOS_OPTIMIZATION
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
+ifeq ($(CONFIG_USB_HCI), y)
+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
+_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o
+endif
+ifeq ($(CONFIG_SDIO_HCI), y)
+_PLATFORM_FILES += platform/platform_ARM_SUNnI_sdio.o
+endif
+ARCH := arm
+# ===Cross compile setting for Android 4.2 SDK ===
+#CROSS_COMPILE := /home/android_sdk/Allwinner/a20_evb/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-
+#KSRC ?= /home/android_sdk/Allwinner/a20_evb/lichee/linux-3.3
+# ==== Cross compile setting for Android 4.3 SDK =====
+#CROSS_COMPILE := /home/android_sdk/Allwinner/a20/android-jb43/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-
+#KSRC ?= /home/android_sdk/Allwinner/a20/android-jb43/lichee/linux-3.4
+# ==== Cross compile setting for kitkat-a20_v4.4 =====
+CROSS_COMPILE := /home/android_sdk/Allwinner/a20/kitkat-a20_v4.4/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-
+KSRC ?= /home/android_sdk/Allwinner/a20/kitkat-a20_v4.4/lichee/linux-3.4
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_SUN8I_W3P1), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN8I
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN8I_W3P1
+EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
+# default setting for Android 4.1, 4.2
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
+ifeq ($(CONFIG_USB_HCI), y)
+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
+_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o
+endif
+ifeq ($(CONFIG_SDIO_HCI), y)
+_PLATFORM_FILES += platform/platform_ARM_SUNnI_sdio.o
+endif
+ARCH := arm
+# ===Cross compile setting for Android 4.2 SDK ===
+#CROSS_COMPILE := /home/android_sdk/Allwinner/a23/android-jb42/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-
+#KSRC ?=/home/android_sdk/Allwinner/a23/android-jb42/lichee/linux-3.4
+# ===Cross compile setting for Android 4.4 SDK ===
+CROSS_COMPILE := /home/android_sdk/Allwinner/a23/android-kk44/lichee/out/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-
+KSRC ?=/home/android_sdk/Allwinner/a23/android-kk44/lichee/linux-3.4
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_SUN8I_W5P1), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN8I
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN8I_W5P1
+EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
+# default setting for Android 4.1, 4.2
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+
+# Enable this for Android 5.0
+EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
+
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
+ifeq ($(CONFIG_USB_HCI), y)
+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
+_PLATFORM_FILES += platform/platform_ARM_SUNxI_usb.o
+endif
+ifeq ($(CONFIG_SDIO_HCI), y)
+_PLATFORM_FILES += platform/platform_ARM_SUNnI_sdio.o
+endif
+
+ARCH := arm
+# ===Cross compile setting for Android L SDK ===
+CROSS_COMPILE := /home/android_sdk/Allwinner/a33/android-L/lichee/out/sun8iw5p1/android/common/buildroot/external-toolchain/bin/arm-linux-gnueabi-
+KSRC ?=/home/android_sdk/Allwinner/a33/android-L/lichee/linux-3.4
+endif
+
+ifeq ($(CONFIG_PLATFORM_ACTIONS_ATV5201), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ACTIONS_ATV5201
+EXTRA_CFLAGS += -DCONFIG_SDIO_DISABLE_RXFIFO_POLLING_LOOP
+ARCH := mips
+CROSS_COMPILE := mipsel-linux-gnu-
+KVER := $(KERNEL_VER)
+KSRC:= $(CFGDIR)/../../kernel/linux-$(KERNEL_VER)
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_RTD299X), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+ifeq ($(CONFIG_ANDROID), y)
+# Enable this for Android 5.0
+EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
+endif
+#ARCH, CROSS_COMPILE, KSRC,and MODDESTDIR are provided by external makefile
+INSTALL_PREFIX :=
+endif
+
+ifeq ($(CONFIG_PLATFORM_HISILICON), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_HISILICON
+ifeq ($(SUPPORT_CONCURRENT),y)
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+endif
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+ARCH := arm
+ifeq ($(CROSS_COMPILE),)
+ CROSS_COMPILE = arm-hisiv200-linux-
+endif
+MODULE_NAME := rtl8192eu
+ifeq ($(KSRC),)
+ KSRC ?= ../../../../../../kernel/linux-3.4.y
+endif
+endif
+
+ifeq ($(CONFIG_PLATFORM_HISILICON_HI3798), y)
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_HISILICON
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_HISILICON_HI3798
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+# default setting for Android
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211
+EXTRA_CFLAGS += -DRTW_USE_CFG80211_STA_EVENT
+# default setting for Android 5.x and later
+#EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
+
+ifeq ($(CONFIG_SDIO_HCI), y)
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
+_PLATFORM_FILES += platform/platform_hisilicon_hi3798_sdio.o
+EXTRA_CFLAGS += -DCONFIG_HISI_SDIO_ID=1
+endif
+
+ARCH ?= arm
+CROSS_COMPILE ?= /HiSTBAndroidV600R003C00SPC021_git_0512/device/hisilicon/bigfish/sdk/tools/linux/toolchains/arm-histbv310-linux/bin/arm-histbv310-linux-
+ifndef KSRC
+KSRC ?= /HiSTBAndroidV600R003C00SPC021_git_0512/device/hisilicon/bigfish/sdk/source/kernel/linux-3.18.y
+KSRC += O=/HiSTBAndroidV600R003C00SPC021_git_0512/out/target/product/Hi3798MV200/obj/KERNEL_OBJ
+endif
+
+ifeq ($(CONFIG_RTL8822B), y)
+ifeq ($(CONFIG_SDIO_HCI), y)
+CONFIG_RTL8822BS ?= m
+USER_MODULE_NAME := rtl8822bs
+endif
+endif
+
+endif
# Platform setting
ifeq ($(CONFIG_PLATFORM_ARM_SPREADTRUM_6820), y)
@@ -1201,16 +1717,30 @@ _PLATFORM_FILES += platform/platform_sprd_sdio.o
endif
endif
-ifeq ($(CONFIG_PLATFORM_RTK129X), y)
+ifeq ($(CONFIG_PLATFORM_ARM_WMT), y)
EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
-EXTRA_CFLAGS += -DRTK_129X_PLATFORM
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
+ifeq ($(CONFIG_SDIO_HCI), y)
+_PLATFORM_FILES += platform/platform_ARM_WMT_sdio.o
+endif
+ARCH := arm
+CROSS_COMPILE := /home/android_sdk/WonderMedia/wm8880-android4.4/toolchain/arm_201103_gcc4.5.2/mybin/arm_1103_le-
+KSRC ?= /home/android_sdk/WonderMedia/wm8880-android4.4/kernel4.4/
+MODULE_NAME :=8189es_kk
+endif
+
+ifeq ($(CONFIG_PLATFORM_RTK119X), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+#EXTRA_CFLAGS += -DCONFIG_PLATFORM_ARM_SUN7I
EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
# default setting for Android 4.1, 4.2
-#EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IFACE_NUMBER=3
EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
-#EXTRA_CFLAGS += -DCONFIG_P2P_IPS -DCONFIG_QOS_OPTIMIZATION
+#EXTRA_CFLAGS += -DCONFIG_QOS_OPTIMIZATION
EXTRA_CFLAGS += -DCONFIG_QOS_OPTIMIZATION
-EXTRA_CFLAGS += -Wno-error=date-time
#EXTRA_CFLAGS += -DCONFIG_#PLATFORM_OPS
ifeq ($(CONFIG_USB_HCI), y)
@@ -1221,16 +1751,148 @@ ifeq ($(CONFIG_SDIO_HCI), y)
_PLATFORM_FILES += platform/platform_ARM_SUNnI_sdio.o
endif
+ARCH := arm
+
+# ==== Cross compile setting for Android 4.4 SDK =====
+#CROSS_COMPILE := arm-linux-gnueabihf-
+KVER := 3.10.24
+#KSRC ?=/home/android_sdk/Allwinner/a20/android-kitkat44/lichee/linux-3.4
+CROSS_COMPILE := /home/realtek/software_phoenix/phoenix/toolchain/usr/local/arm-2013.11/bin/arm-linux-gnueabihf-
+KSRC ?= /home/realtek/software_phoenix/linux-kernel
+MODULE_NAME := 8192eu
+
+endif
+
+ifeq ($(CONFIG_PLATFORM_RTK129X), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+EXTRA_CFLAGS += -DRTK_129X_PLATFORM
+EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT
+# default setting for Android 4.1, 4.2
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+#EXTRA_CFLAGS += -DCONFIG_P2P_IPS -DCONFIG_QOS_OPTIMIZATION
+EXTRA_CFLAGS += -DCONFIG_QOS_OPTIMIZATION
+# Enable this for Android 5.0
+EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
+ifeq ($(CONFIG_RTL8821C)$(CONFIG_SDIO_HCI),yy)
+EXTRA_CFLAGS += -DCONFIG_WAKEUP_GPIO_INPUT_MODE
+EXTRA_CFLAGS += -DCONFIG_BT_WAKE_HST_OPEN_DRAIN
+endif
+EXTRA_CFLAGS += -Wno-error=date-time
+# default setting for Android 7.0
+ifeq ($(RTK_ANDROID_VERSION), nougat)
+EXTRA_CFLAGS += -DRTW_P2P_GROUP_INTERFACE=1
+endif
+#EXTRA_CFLAGS += -DCONFIG_#PLATFORM_OPS
+ifeq ($(CONFIG_USB_HCI), y)
+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
+endif
+
ARCH := arm64
# ==== Cross compile setting for Android 4.4 SDK =====
#CROSS_COMPILE := arm-linux-gnueabihf-
-KVER := 4.1.10
-CROSS_COMPILE := $(CROSS)
-KSRC := $(LINUX_KERNEL_PATH)
-MODULE_NAME := 8822be
+#KVER := 4.1.10
+#CROSS_COMPILE := $(CROSS)
+#KSRC ?= $(LINUX_KERNEL_PATH)
+CROSS_COMPILE := /home/android_sdk/DHC/trunk-6.0.0_r1-QA160627/phoenix/toolchain/asdk64-4.9.4-a53-EL-3.10-g2.19-a64nt-160307/bin/asdk64-linux-
+KSRC ?= /home/android_sdk/DHC/trunk-6.0.0_r1-QA160627/linux-kernel
endif
+ifeq ($(CONFIG_PLATFORM_NOVATEK_NT72668), y)
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_NOVATEK_NT72668
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_RX
+EXTRA_CFLAGS += -DCONFIG_USE_USB_BUFFER_ALLOC_TX
+ARCH ?= arm
+CROSS_COMPILE := arm-linux-gnueabihf-
+KVER := 3.8.0
+KSRC ?= /Custom/Novatek/TCL/linux-3.8_header
+#KSRC ?= $(KERNELDIR)
+endif
+
+ifeq ($(CONFIG_PLATFORM_ARM_TCC8930_JB42), y)
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+# default setting for Android 4.1, 4.2
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
+ARCH := arm
+CROSS_COMPILE := /home/android_sdk/Telechips/v13.05_r1-tcc-android-4.2.2_tcc893x-evm_build/prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/bin/arm-eabi-
+KSRC ?= /home/android_sdk/Telechips/v13.05_r1-tcc-android-4.2.2_tcc893x-evm_build/kernel
+MODULE_NAME := wlan
+endif
+
+ifeq ($(CONFIG_PLATFORM_RTL8197D), y)
+EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN -DCONFIG_PLATFORM_RTL8197D
+export DIR_LINUX=$(shell pwd)/../SDK/rlxlinux-sdk321-v50/linux-2.6.30
+ARCH ?= rlx
+CROSS_COMPILE:= $(DIR_LINUX)/../toolchain/rsdk-1.5.5-5281-EB-2.6.30-0.9.30.3-110714/bin/rsdk-linux-
+KSRC ?= $(DIR_LINUX)
+endif
+
+ifeq ($(CONFIG_PLATFORM_AML_S905), y)
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_AML_S905
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -fno-pic
+# default setting for Android
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211
+EXTRA_CFLAGS += -DRTW_USE_CFG80211_STA_EVENT
+# default setting for Android 5.x and later
+EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
+
+ifeq ($(CONFIG_SDIO_HCI), y)
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
+_PLATFORM_FILES += platform/platform_aml_s905_sdio.o
+endif
+
+ARCH ?= arm64
+CROSS_COMPILE ?= /4.4_S905L_8822bs_compile/gcc-linaro-aarch64-linux-gnu-4.9-2014.09_linux/bin/aarch64-linux-gnu-
+ifndef KSRC
+KSRC ?= /4.4_S905L_8822bs_compile/common
+# To locate output files in a separate directory.
+KSRC += O=/4.4_S905L_8822bs_compile/KERNEL_OBJ
+endif
+
+ifeq ($(CONFIG_RTL8822B), y)
+ifeq ($(CONFIG_SDIO_HCI), y)
+CONFIG_RTL8822BS ?= m
+USER_MODULE_NAME := 8822bs
+endif
+endif
+
+endif
+
+ifeq ($(CONFIG_PLATFORM_ZTE_ZX296716), y)
+EXTRA_CFLAGS += -Wno-error=date-time
+EXTRA_CFLAGS += -DCONFIG_PLATFORM_ZTE_ZX296716
+EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN
+# default setting for Android
+EXTRA_CFLAGS += -DCONFIG_CONCURRENT_MODE
+EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211
+EXTRA_CFLAGS += -DRTW_USE_CFG80211_STA_EVENT
+# default setting for Android 5.x and later
+#EXTRA_CFLAGS += -DCONFIG_RADIO_WORK
+
+ifeq ($(CONFIG_SDIO_HCI), y)
+# mark this temporarily
+#EXTRA_CFLAGS += -DCONFIG_PLATFORM_OPS
+#_PLATFORM_FILES += platform/platform_zte_zx296716_sdio.o
+endif
+
+ARCH ?= arm64
+CROSS_COMPILE ?=
+KSRC ?=
+
+ifeq ($(CONFIG_RTL8822B), y)
+ifeq ($(CONFIG_SDIO_HCI), y)
+CONFIG_RTL8822BS ?= m
+USER_MODULE_NAME := 8822bs
+endif
+endif
+
+endif
ifeq ($(CONFIG_MULTIDRV), y)
@@ -1256,6 +1918,19 @@ endif
ifneq ($(KERNELRELEASE),)
+########### this part for *.mk ############################
+include $(src)/hal/phydm/phydm.mk
+
+########### HAL_RTL8822B #################################
+ifeq ($(CONFIG_RTL8822B), y)
+include $(src)/rtl8822b.mk
+endif
+
+########### HAL_RTL8821C #################################
+ifeq ($(CONFIG_RTL8821C), y)
+include $(src)/rtl8821c.mk
+endif
+
rtk_core := core/rtw_cmd.o \
core/rtw_security.o \
core/rtw_debug.o \
@@ -1273,15 +1948,22 @@ rtk_core := core/rtw_cmd.o \
core/rtw_recv.o \
core/rtw_sta_mgt.o \
core/rtw_ap.o \
+ core/mesh/rtw_mesh.o \
+ core/mesh/rtw_mesh_pathtbl.o \
+ core/mesh/rtw_mesh_hwmp.o \
core/rtw_xmit.o \
core/rtw_p2p.o \
+ core/rtw_rson.o \
core/rtw_tdls.o \
core/rtw_br_ext.o \
core/rtw_iol.o \
core/rtw_sreset.o \
+ core/rtw_btcoex_wifionly.o \
core/rtw_btcoex.o \
core/rtw_beamforming.o \
core/rtw_odm.o \
+ core/rtw_rm.o \
+ core/rtw_rm_fsm.o \
core/efuse/rtw_efuse.o
ifeq ($(CONFIG_SDIO_HCI), y)
@@ -1297,7 +1979,8 @@ $(MODULE_NAME)-$(CONFIG_WAPI_SUPPORT) += core/rtw_wapi.o \
$(MODULE_NAME)-y += $(_OS_INTFS_FILES)
$(MODULE_NAME)-y += $(_HAL_INTFS_FILES)
-$(MODULE_NAME)-y += $(_OUTSRC_FILES)
+$(MODULE_NAME)-y += $(_PHYDM_FILES)
+$(MODULE_NAME)-y += $(_BTC_FILES)
$(MODULE_NAME)-y += $(_PLATFORM_FILES)
$(MODULE_NAME)-$(CONFIG_MP_INCLUDED) += core/rtw_mp.o
@@ -1306,7 +1989,7 @@ ifeq ($(CONFIG_RTL8723B), y)
$(MODULE_NAME)-$(CONFIG_MP_INCLUDED)+= core/rtw_bt_mp.o
endif
-obj-m := $(MODULE_NAME).o
+obj-$(CONFIG_RTL8822BU) := $(MODULE_NAME).o
else
@@ -1315,19 +1998,56 @@ export CONFIG_RTL8822BU = m
all: modules
modules:
- $(MAKE) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) -C $(KSRC) M=$(shell pwd) modules
+ $(MAKE) ARCH="$(ARCH)" CROSS_COMPILE="$(CROSS_COMPILE)" -C $(KSRC) M="$(shell pwd)" modules
strip:
$(CROSS_COMPILE)strip $(MODULE_NAME).ko --strip-unneeded
install:
- install -p -m 644 $(MODULE_NAME).ko $(MODDESTDIR)
+ install -p -m 644 $(MODULE_NAME).ko $(MODDESTDIR)
+ if [ -n "$$(which selinuxenabled)" ] && selinuxenabled ; then \
+ restorecon $(MODDESTDIR)/$(MODULE_NAME).ko ; \
+ fi
/sbin/depmod -a ${KVER}
uninstall:
rm -f $(MODDESTDIR)/$(MODULE_NAME).ko
/sbin/depmod -a ${KVER}
+backup_rtlwifi:
+ @echo "Making backup rtlwifi drivers"
+ifneq (,$(wildcard $(STAGINGMODDIR)/rtl*))
+ @tar cPf $(wildcard $(STAGINGMODDIR))/backup_rtlwifi_driver.tar $(wildcard $(STAGINGMODDIR)/rtl*)
+ @rm -rf $(wildcard $(STAGINGMODDIR)/rtl*)
+endif
+ifneq (,$(wildcard $(MODDESTDIR)realtek))
+ @tar cPf $(MODDESTDIR)backup_rtlwifi_driver.tar $(MODDESTDIR)realtek
+ @rm -fr $(MODDESTDIR)realtek
+endif
+ifneq (,$(wildcard $(MODDESTDIR)rtl*))
+ @tar cPf $(MODDESTDIR)../backup_rtlwifi_driver.tar $(wildcard $(MODDESTDIR)rtl*)
+ @rm -fr $(wildcard $(MODDESTDIR)rtl*)
+endif
+ @/sbin/depmod -a ${KVER}
+ @echo "Please reboot your system"
+
+restore_rtlwifi:
+ @echo "Restoring backups"
+ifneq (,$(wildcard $(STAGINGMODDIR)/backup_rtlwifi_driver.tar))
+ @tar xPf $(STAGINGMODDIR)/backup_rtlwifi_driver.tar
+ @rm $(STAGINGMODDIR)/backup_rtlwifi_driver.tar
+endif
+ifneq (,$(wildcard $(MODDESTDIR)backup_rtlwifi_driver.tar))
+ @tar xPf $(MODDESTDIR)backup_rtlwifi_driver.tar
+ @rm $(MODDESTDIR)backup_rtlwifi_driver.tar
+endif
+ifneq (,$(wildcard $(MODDESTDIR)../backup_rtlwifi_driver.tar))
+ @tar xPf $(MODDESTDIR)../backup_rtlwifi_driver.tar
+ @rm $(MODDESTDIR)../backup_rtlwifi_driver.tar
+endif
+ @/sbin/depmod -a ${KVER}
+ @echo "Please reboot your system"
+
config_r:
@echo "make config"
/bin/bash script/Configure script/config.in
@@ -1336,14 +2056,12 @@ config_r:
.PHONY: modules clean
clean:
- $(MAKE) -C $(KSRC) M=$(shell pwd) clean
- cd hal/phydm/ ; rm -fr */*.mod.c */*.mod */*.o */.*.cmd */*.ko
- cd hal/phydm/ ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
- cd hal/led ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+ #$(MAKE) -C $(KSRC) M="$(shell pwd)" clean
+ cd hal ; rm -fr */*/*/*.mod.c */*/*/*.mod */*/*/*.o */*/*/.*.cmd */*/*/*.ko
cd hal ; rm -fr */*/*.mod.c */*/*.mod */*/*.o */*/.*.cmd */*/*.ko
cd hal ; rm -fr */*.mod.c */*.mod */*.o */.*.cmd */*.ko
cd hal ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
- cd core/efuse ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
+ cd core ; rm -fr */*.mod.c */*.mod */*.o */.*.cmd */*.ko
cd core ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
cd os_dep/linux ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
cd os_dep ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
diff --git a/README.md b/README.md
index 5c5baf6..0fe8f06 100644
--- a/README.md
+++ b/README.md
@@ -1,4 +1,8 @@
-**8822BU for Linux**
+# 8822BU for Linux
+
+This repo is obsolete. Try this instead (https://github.com/cilynx/rtl88x2bu)
+
+Note: I no longer have a device that requires this driver, thus no guarantees that it still works, only that it compiles on my machine.
Driver for 802.11ac USB Adapter with
RTL8822BU chipset
@@ -7,6 +11,9 @@ Only STA/Monitor Mode is supported, no AP.
A few known wireless cards that use this driver include
* [Edimax EW-7822ULC](http://us.edimax.com/edimax/merchandise/merchandise_detail/data/edimax/us/wireless_adapters_ac1200_dual-band/ew-7822ulc/)
* [ASUS AC-53 NANO](https://www.asus.com/Networking/USB-AC53-Nano/)
+* [D-Link DWA-182 (Revision D1 only)](http://ca.dlink.com/products/connect/wireless-ac1200-dual-band-usb-adapter/)
+* [tp-link Archer T4U (Revision V3 only)](https://www.tp-link.com/us/home-networking/usb-adapter/archer-t4u/)
+* [Linksys WUSB6400M](https://www.linksys.com/us/support-product?pid=01t340000042wpSAAQ)
> NOTE: At least v4.7 is needed to compile this module
@@ -16,12 +23,17 @@ A few known wireless cards that use this driver include
Currently tested on X86_64 and ARM platform(s) **only**,
cross compile possible.
+## Installing
For compiling type
-`make`
+```
+make
+```
in source dir
To install the firmware files
-`sudo make install`
+```
+sudo make install
+```
To Unload driver you may need to disconnect the device
@@ -29,18 +41,42 @@ To Unload driver you may need to disconnect the device
If the driver fails building consult your distro how to
install the kernel sources and build an external module.
+## DKMS
+Automatically rebuilds and installs on kernel updates. DKMS is in official sources of Ubuntu, for installation do:
+```
+sudo apt-get install build-essential dkms
+```
-**NOTES**
+Then install the module using dkms do in source dir:
+```
+sudo dkms add .
+sudo dkms install -m 88x2bu -v 1.1
+```
+In order to uninstall the module:
+```
+sudo dkms remove -m 88x2bu -v 1.1 --all
+sudo rm -rf /usr/src/88x2bu-1.1
+```
+
+## NOTES
This driver allows use of wpa_supplicant by using the nl80211 driver
`wpa_supplicant -Dnl80211`
If installing on Rasberry Pi or other "armv71" devices, edit the Makefile and set `CONFIG_PLATFORM_ARM_RPI = y` and `CONFIG_PLATFORM_I386_PC = n`
-**STATUS**
+On Debian with some wireless managers (KDE confirmed) you must append the following to /etc/NetworkManager/NetworkManager.conf:
+
+[device]
+wifi.scan-rand-mac-address=no
+
+Otherwise, you may get stuck in an infinte loop of failed connection and a prompt for password. Source page here:
+https://wiki.debian.org/WiFi
+
+## STATUS
Driver works fine (some sort of)
Most of the work is done is cleaning the driver and make this mess **readable** for conversion.
Updates for wireless-ext/cfg80211 are not accepted.
-**BUGS**
-
+## BUGS
+
diff --git a/RTL8822Bfw_NIC.bin b/RTL8822Bfw_NIC.bin
deleted file mode 100644
index ff8a12c..0000000
Binary files a/RTL8822Bfw_NIC.bin and /dev/null differ
diff --git a/core/efuse/rtw_efuse.c b/core/efuse/rtw_efuse.c
index 4efa64d..ba5c602 100644
--- a/core/efuse/rtw_efuse.c
+++ b/core/efuse/rtw_efuse.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,12 +11,7 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#define _RTW_EFUSE_C_
#include
@@ -41,7 +36,7 @@ u8 fakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE];
u8 fakeBTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN] = {0};
u8 fakeBTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN] = {0};
-u8 maskfileBuffer[32];
+u8 maskfileBuffer[64];
/*------------------------Define local variable------------------------------*/
BOOLEAN rtw_file_efuse_IsMasked(PADAPTER pAdapter, u16 Offset)
{
@@ -113,10 +108,10 @@ BOOLEAN efuse_IsMasked(PADAPTER pAdapter, u16 Offset)
return (IS_MASKED(8723D, _MUSB, Offset)) ? TRUE : FALSE;
#endif
- /*#if defined(CONFIG_RTL8821C)
- if (IS_HARDWARE_TYPE_8821C(pAdapter))
- return (IS_MASKED(8821C,_MUSB,Offset)) ? TRUE : FALSE;
- #endif*/
+#if defined(CONFIG_RTL8821C)
+ if (IS_HARDWARE_TYPE_8821CU(pAdapter))
+ return (IS_MASKED(8821C, _MUSB, Offset)) ? TRUE : FALSE;
+#endif
#elif DEV_BUS_TYPE == RT_PCI_INTERFACE
#if defined(CONFIG_RTL8188E)
@@ -147,16 +142,40 @@ BOOLEAN efuse_IsMasked(PADAPTER pAdapter, u16 Offset)
if (IS_HARDWARE_TYPE_8822B(pAdapter))
return (IS_MASKED(8822B, _MPCIE, Offset)) ? TRUE : FALSE;
#endif
+#if defined(CONFIG_RTL8821C)
+ if (IS_HARDWARE_TYPE_8821CE(pAdapter))
+ return (IS_MASKED(8821C, _MPCIE, Offset)) ? TRUE : FALSE;
+#endif
#elif DEV_BUS_TYPE == RT_SDIO_INTERFACE
#ifdef CONFIG_RTL8188E_SDIO
if (IS_HARDWARE_TYPE_8188E(pAdapter))
return (IS_MASKED(8188E, _MSDIO, Offset)) ? TRUE : FALSE;
#endif
+#ifdef CONFIG_RTL8723B
+ if (IS_HARDWARE_TYPE_8723BS(pAdapter))
+ return (IS_MASKED(8723B, _MSDIO, Offset)) ? TRUE : FALSE;
+#endif
#ifdef CONFIG_RTL8188F_SDIO
if (IS_HARDWARE_TYPE_8188F(pAdapter))
return (IS_MASKED(8188F, _MSDIO, Offset)) ? TRUE : FALSE;
#endif
+#ifdef CONFIG_RTL8192E
+ if (IS_HARDWARE_TYPE_8192ES(pAdapter))
+ return (IS_MASKED(8192E, _MSDIO, Offset)) ? TRUE : FALSE;
+#endif
+#if defined(CONFIG_RTL8821A)
+ if (IS_HARDWARE_TYPE_8821S(pAdapter))
+ return (IS_MASKED(8821A, _MSDIO, Offset)) ? TRUE : FALSE;
+#endif
+#if defined(CONFIG_RTL8821C)
+ if (IS_HARDWARE_TYPE_8821CS(pAdapter))
+ return (IS_MASKED(8821C, _MSDIO, Offset)) ? TRUE : FALSE;
+#endif
+#if defined(CONFIG_RTL8822B)
+ if (IS_HARDWARE_TYPE_8822B(pAdapter))
+ return (IS_MASKED(8822B, _MSDIO, Offset)) ? TRUE : FALSE;
+#endif
#endif
return FALSE;
@@ -203,10 +222,12 @@ void rtw_efuse_mask_array(PADAPTER pAdapter, u8 *pArray)
if (IS_HARDWARE_TYPE_8822B(pAdapter))
GET_MASK_ARRAY(8822B, _MUSB, pArray);
#endif
- /*#if defined(CONFIG_RTL8821C)
- if (IS_HARDWARE_TYPE_8821C(pAdapter))
- GET_MASK_ARRAY(8821C,_MUSB,pArray);
- #endif*/
+#if defined(CONFIG_RTL8821C)
+ if (IS_HARDWARE_TYPE_8821CU(pAdapter))
+ GET_MASK_ARRAY(8821C, _MUSB, pArray);
+#endif
+
+
#elif DEV_BUS_TYPE == RT_PCI_INTERFACE
#if defined(CONFIG_RTL8188E)
if (IS_HARDWARE_TYPE_8188E(pAdapter))
@@ -236,15 +257,41 @@ void rtw_efuse_mask_array(PADAPTER pAdapter, u8 *pArray)
if (IS_HARDWARE_TYPE_8822B(pAdapter))
GET_MASK_ARRAY(8822B, _MPCIE, pArray);
#endif
+#if defined(CONFIG_RTL8821C)
+ if (IS_HARDWARE_TYPE_8821CE(pAdapter))
+ GET_MASK_ARRAY(8821C, _MPCIE, pArray);
+#endif
+
+
#elif DEV_BUS_TYPE == RT_SDIO_INTERFACE
#if defined(CONFIG_RTL8188E)
if (IS_HARDWARE_TYPE_8188E(pAdapter))
GET_MASK_ARRAY(8188E, _MSDIO, pArray);
#endif
+#if defined(CONFIG_RTL8723B)
+ if (IS_HARDWARE_TYPE_8723BS(pAdapter))
+ GET_MASK_ARRAY(8723B, _MSDIO, pArray);
+#endif
#if defined(CONFIG_RTL8188F)
if (IS_HARDWARE_TYPE_8188F(pAdapter))
GET_MASK_ARRAY(8188F, _MSDIO, pArray);
#endif
+#if defined(CONFIG_RTL8192E)
+ if (IS_HARDWARE_TYPE_8192ES(pAdapter))
+ GET_MASK_ARRAY(8192E, _MSDIO, pArray);
+#endif
+#if defined(CONFIG_RTL8821A)
+ if (IS_HARDWARE_TYPE_8821S(pAdapter))
+ GET_MASK_ARRAY(8821A, _MSDIO, pArray);
+#endif
+#if defined(CONFIG_RTL8821C)
+ if (IS_HARDWARE_TYPE_8821CS(pAdapter))
+ GET_MASK_ARRAY(8821C , _MSDIO, pArray);
+#endif
+#if defined(CONFIG_RTL8822B)
+ if (IS_HARDWARE_TYPE_8822B(pAdapter))
+ GET_MASK_ARRAY(8822B , _MSDIO, pArray);
+#endif
#endif /*#elif DEV_BUS_TYPE == RT_SDIO_INTERFACE*/
}
@@ -289,10 +336,12 @@ u16 rtw_get_efuse_mask_arraylen(PADAPTER pAdapter)
if (IS_HARDWARE_TYPE_8822B(pAdapter))
return GET_MASK_ARRAY_LEN(8822B, _MUSB);
#endif
- /*#if defined(CONFIG_RTL8821C)
- if (IS_HARDWARE_TYPE_8821C(pAdapter))
- return GET_MASK_ARRAY_LEN(8821C,_MUSB);
- #endif*/
+#if defined(CONFIG_RTL8821C)
+ if (IS_HARDWARE_TYPE_8821CU(pAdapter))
+ return GET_MASK_ARRAY_LEN(8821C, _MUSB);
+#endif
+
+
#elif DEV_BUS_TYPE == RT_PCI_INTERFACE
#if defined(CONFIG_RTL8188E)
if (IS_HARDWARE_TYPE_8188E(pAdapter))
@@ -322,20 +371,403 @@ u16 rtw_get_efuse_mask_arraylen(PADAPTER pAdapter)
if (IS_HARDWARE_TYPE_8822B(pAdapter))
return GET_MASK_ARRAY_LEN(8822B, _MPCIE);
#endif
+#if defined(CONFIG_RTL8821C)
+ if (IS_HARDWARE_TYPE_8821CE(pAdapter))
+ return GET_MASK_ARRAY_LEN(8821C, _MPCIE);
+#endif
+
+
#elif DEV_BUS_TYPE == RT_SDIO_INTERFACE
#if defined(CONFIG_RTL8188E)
if (IS_HARDWARE_TYPE_8188E(pAdapter))
return GET_MASK_ARRAY_LEN(8188E, _MSDIO);
#endif
+#if defined(CONFIG_RTL8723B)
+ if (IS_HARDWARE_TYPE_8723BS(pAdapter))
+ return GET_MASK_ARRAY_LEN(8723B, _MSDIO);
+#endif
#if defined(CONFIG_RTL8188F)
if (IS_HARDWARE_TYPE_8188F(pAdapter))
return GET_MASK_ARRAY_LEN(8188F, _MSDIO);
#endif
-
+#if defined(CONFIG_RTL8192E)
+ if (IS_HARDWARE_TYPE_8192ES(pAdapter))
+ return GET_MASK_ARRAY_LEN(8192E, _MSDIO);
+#endif
+#if defined(CONFIG_RTL8821A)
+ if (IS_HARDWARE_TYPE_8821S(pAdapter))
+ return GET_MASK_ARRAY_LEN(8821A, _MSDIO);
+#endif
+#if defined(CONFIG_RTL8821C)
+ if (IS_HARDWARE_TYPE_8821CS(pAdapter))
+ return GET_MASK_ARRAY_LEN(8821C, _MSDIO);
+#endif
+#if defined(CONFIG_RTL8822B)
+ if (IS_HARDWARE_TYPE_8822B(pAdapter))
+ return GET_MASK_ARRAY_LEN(8822B, _MSDIO);
+#endif
#endif
return 0;
}
+static void rtw_mask_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
+{
+ u16 i = 0;
+
+ if (padapter->registrypriv.boffefusemask == 0) {
+
+ for (i = 0; i < cnts; i++) {
+ if (padapter->registrypriv.bFileMaskEfuse == _TRUE) {
+ if (rtw_file_efuse_IsMasked(padapter, addr + i)) /*use file efuse mask.*/
+ data[i] = 0xff;
+ } else {
+ /*RTW_INFO(" %s , data[%d] = %x\n", __func__, i, data[i]);*/
+ if (efuse_IsMasked(padapter, addr + i)) {
+ data[i] = 0xff;
+ /*RTW_INFO(" %s ,mask data[%d] = %x\n", __func__, i, data[i]);*/
+ }
+ }
+ }
+
+ }
+}
+
+u8 rtw_efuse_mask_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
+{
+ u8 ret = _SUCCESS;
+ u16 mapLen = 0;
+
+ EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, _FALSE);
+
+ ret = rtw_efuse_map_read(padapter, addr, cnts , data);
+
+ rtw_mask_map_read(padapter, addr, cnts , data);
+
+ return ret;
+
+}
+
+/* ***********************************************************
+ * Efuse related code
+ * *********************************************************** */
+static u8 hal_EfuseSwitchToBank(
+ PADAPTER padapter,
+ u8 bank,
+ u8 bPseudoTest)
+{
+ u8 bRet = _FALSE;
+ u32 value32 = 0;
+#ifdef HAL_EFUSE_MEMORY
+ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
+ PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal;
+#endif
+
+
+ RTW_INFO("%s: Efuse switch bank to %d\n", __FUNCTION__, bank);
+ if (bPseudoTest) {
+#ifdef HAL_EFUSE_MEMORY
+ pEfuseHal->fakeEfuseBank = bank;
+#else
+ fakeEfuseBank = bank;
+#endif
+ bRet = _TRUE;
+ } else {
+ value32 = rtw_read32(padapter, 0x34);
+ bRet = _TRUE;
+ switch (bank) {
+ case 0:
+ value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
+ break;
+ case 1:
+ value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_0);
+ break;
+ case 2:
+ value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_1);
+ break;
+ case 3:
+ value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_2);
+ break;
+ default:
+ value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
+ bRet = _FALSE;
+ break;
+ }
+ rtw_write32(padapter, 0x34, value32);
+ }
+
+ return bRet;
+}
+
+void rtw_efuse_analyze(PADAPTER padapter, u8 Type, u8 Fake)
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+ PEFUSE_HAL pEfuseHal = &(pHalData->EfuseHal);
+ u16 eFuse_Addr = 0;
+ u8 offset, wden;
+ u16 i, j;
+ u8 u1temp = 0;
+ u8 efuseHeader = 0, efuseExtHdr = 0, efuseData[EFUSE_MAX_WORD_UNIT*2] = {0}, dataCnt = 0;
+ u16 efuseHeader2Byte = 0;
+ u8 *eFuseWord = NULL;// [EFUSE_MAX_SECTION_NUM][EFUSE_MAX_WORD_UNIT];
+ u8 offset_2_0 = 0;
+ u8 pgSectionCnt = 0;
+ u8 wd_cnt = 0;
+ u8 max_section = 64;
+ u16 mapLen = 0, maprawlen = 0;
+ boolean bExtHeader = _FALSE;
+ u8 efuseType = EFUSE_WIFI;
+ boolean bPseudoTest = _FALSE;
+ u8 bank = 0, startBank = 0, endBank = 1-1;
+ boolean bCheckNextBank = FALSE;
+ u8 protectBytesBank = 0;
+ u16 efuse_max = 0;
+ u8 ParseEfuseExtHdr, ParseEfuseHeader, ParseOffset, ParseWDEN, ParseOffset2_0;
+
+ eFuseWord = rtw_zmalloc(EFUSE_MAX_SECTION_NUM * (EFUSE_MAX_WORD_UNIT * 2));
+
+ RTW_INFO("\n");
+ if (Type == 0) {
+ if (Fake == 0) {
+ RTW_INFO("\n\tEFUSE_Analyze Wifi Content\n");
+ efuseType = EFUSE_WIFI;
+ bPseudoTest = FALSE;
+ startBank = 0;
+ endBank = 0;
+ } else {
+ RTW_INFO("\n\tEFUSE_Analyze Wifi Pseudo Content\n");
+ efuseType = EFUSE_WIFI;
+ bPseudoTest = TRUE;
+ startBank = 0;
+ endBank = 0;
+ }
+ } else {
+ if (Fake == 0) {
+ RTW_INFO("\n\tEFUSE_Analyze BT Content\n");
+ efuseType = EFUSE_BT;
+ bPseudoTest = FALSE;
+ startBank = 1;
+ endBank = EFUSE_MAX_BANK - 1;
+ } else {
+ RTW_INFO("\n\tEFUSE_Analyze BT Pseudo Content\n");
+ efuseType = EFUSE_BT;
+ bPseudoTest = TRUE;
+ startBank = 1;
+ endBank = EFUSE_MAX_BANK - 1;
+ if (IS_HARDWARE_TYPE_8821(padapter))
+ endBank = 3 - 1;/*EFUSE_MAX_BANK_8821A - 1;*/
+ }
+ }
+
+ RTW_INFO("\n\r 1Byte header, [7:4]=offset, [3:0]=word enable\n");
+ RTW_INFO("\n\r 2Byte header, header[7:5]=offset[2:0], header[4:0]=0x0F\n");
+ RTW_INFO("\n\r 2Byte header, extHeader[7:4]=offset[6:3], extHeader[3:0]=word enable\n");
+
+ EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, bPseudoTest);
+ EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_EFUSE_MAX_SECTION, (PVOID)&max_section, bPseudoTest);
+ EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_EFUSE_PROTECT_BYTES_BANK, (PVOID)&protectBytesBank, bPseudoTest);
+ EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_EFUSE_CONTENT_LEN_BANK, (PVOID)&efuse_max, bPseudoTest);
+ EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_REAL_CONTENT_LEN, (PVOID)&maprawlen, _FALSE);
+
+ _rtw_memset(eFuseWord, 0xff, EFUSE_MAX_SECTION_NUM * (EFUSE_MAX_WORD_UNIT * 2));
+ _rtw_memset(pEfuseHal->fakeEfuseInitMap, 0xff, EFUSE_MAX_MAP_LEN);
+
+ if (IS_HARDWARE_TYPE_8821(padapter))
+ endBank = 3 - 1;/*EFUSE_MAX_BANK_8821A - 1;*/
+
+ for (bank = startBank; bank <= endBank; bank++) {
+ if (!hal_EfuseSwitchToBank(padapter, bank, bPseudoTest)) {
+ RTW_INFO("EFUSE_SwitchToBank() Fail!!\n");
+ return;
+ }
+
+ eFuse_Addr = bank * EFUSE_MAX_BANK_SIZE;
+
+ efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest);
+
+ if (efuseHeader == 0xFF && bank == startBank && Fake != TRUE) {
+ RTW_INFO("Non-PGed Efuse\n");
+ return;
+ }
+ RTW_INFO("EFUSE_REAL_CONTENT_LEN = %d\n", maprawlen);
+
+ while ((efuseHeader != 0xFF) && ((efuseType == EFUSE_WIFI && (eFuse_Addr < maprawlen)) || (efuseType == EFUSE_BT && (eFuse_Addr < (endBank + 1) * EFUSE_MAX_BANK_SIZE)))) {
+
+ RTW_INFO("Analyzing: Offset: 0x%X\n", eFuse_Addr);
+
+ /* Check PG header for section num.*/
+ if (EXT_HEADER(efuseHeader)) {
+ bExtHeader = TRUE;
+ offset_2_0 = GET_HDR_OFFSET_2_0(efuseHeader);
+ efuse_OneByteRead(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest);
+
+ if (efuseExtHdr != 0xff) {
+ if (ALL_WORDS_DISABLED(efuseExtHdr)) {
+ /* Read next pg header*/
+ efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest);
+ continue;
+ } else {
+ offset = ((efuseExtHdr & 0xF0) >> 1) | offset_2_0;
+ wden = (efuseExtHdr & 0x0F);
+ efuseHeader2Byte = (efuseExtHdr<<8)|efuseHeader;
+ RTW_INFO("Find efuseHeader2Byte = 0x%04X, offset=%d, wden=0x%x\n",
+ efuseHeader2Byte, offset, wden);
+ }
+ } else {
+ RTW_INFO("Error, efuse[%d]=0xff, efuseExtHdr=0xff\n", eFuse_Addr-1);
+ break;
+ }
+ } else {
+ offset = ((efuseHeader >> 4) & 0x0f);
+ wden = (efuseHeader & 0x0f);
+ }
+
+ _rtw_memset(efuseData, '\0', EFUSE_MAX_WORD_UNIT * 2);
+ dataCnt = 0;
+
+ if (offset < max_section) {
+ for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
+ /* Check word enable condition in the section */
+ if (!(wden & (0x01<> 8;
+ ParseEfuseHeader = (efuseHeader2Byte & 0xff);
+ ParseOffset2_0 = GET_HDR_OFFSET_2_0(ParseEfuseHeader);
+ ParseOffset = ((ParseEfuseExtHdr & 0xF0) >> 1) | ParseOffset2_0;
+ ParseWDEN = (ParseEfuseExtHdr & 0x0F);
+ RTW_INFO("Header=0x%x, ExtHeader=0x%x, ", ParseEfuseHeader, ParseEfuseExtHdr);
+ } else {
+ ParseEfuseHeader = efuseHeader;
+ ParseOffset = ((ParseEfuseHeader >> 4) & 0x0f);
+ ParseWDEN = (ParseEfuseHeader & 0x0f);
+ RTW_INFO("Header=0x%x, ", ParseEfuseHeader);
+ }
+ RTW_INFO("offset=0x%x(%d), word enable=0x%x\n", ParseOffset, ParseOffset, ParseWDEN);
+
+ wd_cnt = 0;
+ for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
+ if (!(wden & (0x01 << i))) {
+ RTW_INFO("Map[ %02X ] = %02X %02X\n", ((offset * EFUSE_MAX_WORD_UNIT * 2) + (i * 2)), efuseData[wd_cnt * 2 + 0], efuseData[wd_cnt * 2 + 1]);
+ wd_cnt++;
+ }
+ }
+
+ pgSectionCnt++;
+ bExtHeader = FALSE;
+ efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest);
+ if (efuseHeader == 0xFF) {
+ if ((eFuse_Addr + protectBytesBank) >= efuse_max)
+ bCheckNextBank = TRUE;
+ else
+ bCheckNextBank = FALSE;
+ }
+ }
+ if (!bCheckNextBank) {
+ RTW_INFO("Not need to check next bank, eFuse_Addr=%d, protectBytesBank=%d, efuse_max=%d\n",
+ eFuse_Addr, protectBytesBank, efuse_max);
+ break;
+ }
+ }
+ /* switch bank back to 0 for BT/wifi later use*/
+ hal_EfuseSwitchToBank(padapter, 0, bPseudoTest);
+
+ /* 3. Collect 16 sections and 4 word unit into Efuse map.*/
+ for (i = 0; i < max_section; i++) {
+ for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++) {
+ pEfuseHal->fakeEfuseInitMap[(i*8)+(j*2)] = (eFuseWord[(i*8)+(j*2)]);
+ pEfuseHal->fakeEfuseInitMap[(i*8)+((j*2)+1)] = (eFuseWord[(i*8)+((j*2)+1)]);
+ }
+ }
+
+ RTW_INFO("\n\tEFUSE Analyze Map\n");
+ i = 0;
+ j = 0;
+
+ for (i = 0; i < mapLen; i++) {
+ if (i % 16 == 0)
+ RTW_PRINT_SEL(RTW_DBGDUMP, "0x%03x: ", i);
+ _RTW_PRINT_SEL(RTW_DBGDUMP, "%02X%s"
+ , pEfuseHal->fakeEfuseInitMap[i]
+ , ((i + 1) % 16 == 0) ? "\n" : (((i + 1) % 8 == 0) ? " " : " ")
+ );
+ }
+ _RTW_PRINT_SEL(RTW_DBGDUMP, "\n");
+ if (eFuseWord)
+ rtw_mfree((u8 *)eFuseWord, EFUSE_MAX_SECTION_NUM * (EFUSE_MAX_WORD_UNIT * 2));
+}
+
+VOID efuse_PreUpdateAction(
+ PADAPTER pAdapter,
+ pu4Byte BackupRegs)
+{
+ if (IS_HARDWARE_TYPE_8812AU(pAdapter) || IS_HARDWARE_TYPE_8822BU(pAdapter)) {
+ /* <20131115, Kordan> Turn off Rx to prevent from being busy when writing the EFUSE. (Asked by Chunchu.)*/
+ BackupRegs[0] = phy_query_mac_reg(pAdapter, REG_RCR, bMaskDWord);
+ BackupRegs[1] = phy_query_mac_reg(pAdapter, REG_RXFLTMAP0, bMaskDWord);
+ BackupRegs[2] = phy_query_mac_reg(pAdapter, REG_RXFLTMAP0+4, bMaskDWord);
+#ifdef CONFIG_RTL8812A
+ BackupRegs[3] = phy_query_mac_reg(pAdapter, REG_AFE_MISC, bMaskDWord);
+#endif
+ PlatformEFIOWrite4Byte(pAdapter, REG_RCR, 0x1);
+ PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0, 0);
+ PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+1, 0);
+ PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+2, 0);
+ PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+3, 0);
+ PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+4, 0);
+ PlatformEFIOWrite1Byte(pAdapter, REG_RXFLTMAP0+5, 0);
+#ifdef CONFIG_RTL8812A
+ /* <20140410, Kordan> 0x11 = 0x4E, lower down LX_SPS0 voltage. (Asked by Chunchu)*/
+ phy_set_mac_reg(pAdapter, REG_AFE_MISC, bMaskByte1, 0x4E);
+#endif
+ RTW_INFO(" %s , done\n", __func__);
+
+ }
+}
+
+
+VOID efuse_PostUpdateAction(
+ PADAPTER pAdapter,
+ pu4Byte BackupRegs)
+{
+ if (IS_HARDWARE_TYPE_8812AU(pAdapter) || IS_HARDWARE_TYPE_8822BU(pAdapter)) {
+ /* <20131115, Kordan> Turn on Rx and restore the registers. (Asked by Chunchu.)*/
+ phy_set_mac_reg(pAdapter, REG_RCR, bMaskDWord, BackupRegs[0]);
+ phy_set_mac_reg(pAdapter, REG_RXFLTMAP0, bMaskDWord, BackupRegs[1]);
+ phy_set_mac_reg(pAdapter, REG_RXFLTMAP0+4, bMaskDWord, BackupRegs[2]);
+#ifdef CONFIG_RTL8812A
+ phy_set_mac_reg(pAdapter, REG_AFE_MISC, bMaskDWord, BackupRegs[3]);
+#endif
+ RTW_INFO(" %s , done\n", __func__);
+ }
+}
+
#ifdef RTW_HALMAC
#include "../../hal/hal_halmac.h"
@@ -369,16 +801,45 @@ u16 efuse_GetMaxSize(PADAPTER adapter)
return size;
}
-u8 efuse_bt_GetCurrentSize(PADAPTER adapter, u16 *size)
+u16 efuse_GetavailableSize(PADAPTER adapter)
{
- *size = 0;
+ struct dvobj_priv *d;
+ u32 size = 0;
+ int err;
- return _FAIL;
+ d = adapter_to_dvobj(adapter);
+ err = rtw_halmac_get_available_efuse_size(d, &size);
+ if (err)
+ return 0;
+
+ return size;
+}
+
+
+u8 efuse_bt_GetCurrentSize(PADAPTER adapter, u16 *usesize)
+{
+ u8 *efuse_map;
+
+ *usesize = 0;
+ efuse_map = rtw_malloc(EFUSE_BT_MAP_LEN);
+ if (efuse_map == NULL) {
+ RTW_DBG("%s: malloc FAIL\n", __FUNCTION__);
+ return _FAIL;
+ }
+
+ /* for get bt phy efuse last use byte */
+ hal_ReadEFuse_BT_logic_map(adapter, 0x00, EFUSE_BT_MAP_LEN, efuse_map);
+ *usesize = fakeBTEfuseUsedBytes;
+
+ if (efuse_map)
+ rtw_mfree(efuse_map, EFUSE_BT_MAP_LEN);
+
+ return _SUCCESS;
}
u16 efuse_bt_GetMaxSize(PADAPTER adapter)
{
- return 0;
+ return EFUSE_BT_REAL_CONTENT_LEN;
}
void EFUSE_GetEfuseDefinition(PADAPTER adapter, u8 efusetype, u8 type, void *out, BOOLEAN test)
@@ -389,8 +850,8 @@ void EFUSE_GetEfuseDefinition(PADAPTER adapter, u8 efusetype, u8 type, void *out
d = adapter_to_dvobj(adapter);
- if (adapter->HalFunc.EFUSEGetEfuseDefinition) {
- adapter->HalFunc.EFUSEGetEfuseDefinition(adapter, efusetype, type, out, test);
+ if (adapter->hal_func.EFUSEGetEfuseDefinition) {
+ adapter->hal_func.EFUSEGetEfuseDefinition(adapter, efusetype, type, out, test);
return;
}
@@ -400,6 +861,21 @@ void EFUSE_GetEfuseDefinition(PADAPTER adapter, u8 efusetype, u8 type, void *out
rtw_halmac_get_logical_efuse_size(d, &v32);
*(u16 *)out = (u16)v32;
return;
+
+ case TYPE_EFUSE_REAL_CONTENT_LEN:
+ rtw_halmac_get_physical_efuse_size(d, &v32);
+ *(u16 *)out = (u16)v32;
+ return;
+ }
+ } else if (EFUSE_BT == efusetype) {
+ switch (type) {
+ case TYPE_EFUSE_MAP_LEN:
+ *(u16 *)out = EFUSE_BT_MAP_LEN;
+ return;
+
+ case TYPE_EFUSE_REAL_CONTENT_LEN:
+ *(u16 *)out = EFUSE_BT_REAL_CONTENT_LEN;
+ return;
}
}
}
@@ -473,7 +949,7 @@ u8 rtw_efuse_bt_access(PADAPTER adapter, u8 write, u16 addr, u16 cnts, u8 *data)
d = adapter_to_dvobj(adapter);
- size = EFUSE_BT_REAL_BANK_CONTENT_LEN;
+ size = EFUSE_BT_REAL_CONTENT_LEN;
if ((addr + cnts) > size)
return _FAIL;
@@ -498,8 +974,9 @@ u8 rtw_efuse_bt_access(PADAPTER adapter, u8 write, u16 addr, u16 cnts, u8 *data)
}
dump_buf(efuse + addr, cnts);
- RTW_INFO("%s: rtw_halmac_read_bt_physical_efuse_map ok!\n", __FUNCTION__);
_rtw_memcpy(data, efuse + addr, cnts);
+
+ RTW_INFO("%s: rtw_halmac_read_bt_physical_efuse_map ok! data 0x%x\n", __FUNCTION__, *data);
rtw_mfree(efuse, size);
}
}
@@ -513,45 +990,52 @@ u8 rtw_efuse_map_read(PADAPTER adapter, u16 addr, u16 cnts, u8 *data)
u8 *efuse = NULL;
u32 size, i;
int err;
+ u32 backupRegs[4] = {0};
+ u8 status = _SUCCESS;
+ efuse_PreUpdateAction(adapter, backupRegs);
d = adapter_to_dvobj(adapter);
err = rtw_halmac_get_logical_efuse_size(d, &size);
- if (err)
- return _FAIL;
-
+ if (err) {
+ status = _FAIL;
+ goto exit;
+ }
/* size error handle */
if ((addr + cnts) > size) {
if (addr < size)
cnts = size - addr;
- else
- return _FAIL;
+ else {
+ status = _FAIL;
+ goto exit;
+ }
}
if (cnts > 16)
efuse = rtw_zmalloc(size);
if (efuse) {
- err = rtw_halmac_read_logical_efuse_map(d, efuse, size);
+ err = rtw_halmac_read_logical_efuse_map(d, efuse, size, NULL, 0);
if (err) {
rtw_mfree(efuse, size);
- return _FAIL;
+ status = _FAIL;
+ goto exit;
}
_rtw_memcpy(data, efuse + addr, cnts);
rtw_mfree(efuse, size);
} else {
err = rtw_halmac_read_logical_efuse(d, addr, cnts, data);
- if (err)
- return _FAIL;
+ if (err) {
+ status = _FAIL;
+ goto exit;
+ }
}
+ status = _SUCCESS;
+exit:
+ efuse_PostUpdateAction(adapter, backupRegs);
- return _SUCCESS;
-}
-
-u8 rtw_efuse_mask_map_read(PADAPTER adapter, u16 addr, u16 cnts, u8 *data)
-{
- return rtw_efuse_map_read(adapter, addr, cnts, data);
+ return status;
}
u8 rtw_efuse_map_write(PADAPTER adapter, u16 addr, u16 cnts, u8 *data)
@@ -562,23 +1046,34 @@ u8 rtw_efuse_map_write(PADAPTER adapter, u16 addr, u16 cnts, u8 *data)
int err;
u8 mask_buf[64] = "";
u16 mask_len = sizeof(u8) * rtw_get_efuse_mask_arraylen(adapter);
+ u32 backupRegs[4] = {0};
+ u8 status = _SUCCESS;;
+
+ efuse_PreUpdateAction(adapter, backupRegs);
d = adapter_to_dvobj(adapter);
err = rtw_halmac_get_logical_efuse_size(d, &size);
- if (err)
- return _FAIL;
+ if (err) {
+ status = _FAIL;
+ goto exit;
+ }
- if ((addr + cnts) > size)
- return _FAIL;
+ if ((addr + cnts) > size) {
+ status = _FAIL;
+ goto exit;
+ }
efuse = rtw_zmalloc(size);
- if (!efuse)
- return _FAIL;
+ if (!efuse) {
+ status = _FAIL;
+ goto exit;
+ }
- err = rtw_halmac_read_logical_efuse_map(d, efuse, size);
+ err = rtw_halmac_read_logical_efuse_map(d, efuse, size, NULL, 0);
if (err) {
rtw_mfree(efuse, size);
- return _FAIL;
+ status = _FAIL;
+ goto exit;
}
_rtw_memcpy(efuse + addr, data, cnts);
@@ -587,7 +1082,11 @@ u8 rtw_efuse_map_write(PADAPTER adapter, u16 addr, u16 cnts, u8 *data)
RTW_INFO("Use mask Array Len: %d\n", mask_len);
if (mask_len != 0) {
- rtw_efuse_mask_array(adapter, mask_buf);
+ if (adapter->registrypriv.bFileMaskEfuse == _TRUE)
+ _rtw_memcpy(mask_buf, maskfileBuffer, mask_len);
+ else
+ rtw_efuse_mask_array(adapter, mask_buf);
+
err = rtw_halmac_write_logical_efuse_map(d, efuse, size, mask_buf, mask_len);
} else
err = rtw_halmac_write_logical_efuse_map(d, efuse, size, NULL, 0);
@@ -599,12 +1098,16 @@ u8 rtw_efuse_map_write(PADAPTER adapter, u16 addr, u16 cnts, u8 *data)
if (err) {
rtw_mfree(efuse, size);
- return _FAIL;
+ status = _FAIL;
+ goto exit;
}
rtw_mfree(efuse, size);
+ status = _SUCCESS;
+exit :
+ efuse_PostUpdateAction(adapter, backupRegs);
- return _SUCCESS;
+ return status;
}
int Efuse_PgPacketRead(PADAPTER adapter, u8 offset, u8 *data, BOOLEAN test)
@@ -654,7 +1157,7 @@ u8 rtw_BT_efuse_map_write(PADAPTER adapter, u16 addr, u16 cnts, u8 *data)
if (ret == _FAIL)
goto exit;
RTW_INFO("OFFSET\tVALUE(hex)\n");
- for (i = 0; i < 1024; i += 16) { /* set 512 because the iwpriv's extra size have limit 0x7FF */
+ for (i = 0; i < mapLen; i += 16) { /* set 512 because the iwpriv's extra size have limit 0x7FF */
RTW_INFO("0x%03x\t", i);
for (j = 0; j < 8; j++)
RTW_INFO("%02X ", map[i + j]);
@@ -679,13 +1182,13 @@ u8 rtw_BT_efuse_map_write(PADAPTER adapter, u16 addr, u16 cnts, u8 *data)
}
if (word_en != 0xF) {
+ ret = EfusePgPacketWrite_BT(adapter, offset, word_en, newdata, _FALSE);
RTW_INFO("offset=%x\n", offset);
RTW_INFO("word_en=%x\n", word_en);
RTW_INFO("%s: data=", __FUNCTION__);
for (i = 0; i < PGPKT_DATA_SIZE; i++)
RTW_INFO("0x%02X ", newdata[i]);
RTW_INFO("\n");
- ret = EfusePgPacketWrite_BT(adapter, offset, word_en, newdata, _FALSE);
if (ret == _FAIL)
break;
}
@@ -725,17 +1228,17 @@ VOID hal_ReadEFuse_BT_logic_map(
}
efuseTbl = rtw_malloc(EFUSE_BT_MAP_LEN);
- phyefuse = rtw_malloc(EFUSE_BT_REAL_BANK_CONTENT_LEN);
-
+ phyefuse = rtw_malloc(EFUSE_BT_REAL_CONTENT_LEN);
if (efuseTbl == NULL || phyefuse == NULL) {
- RTW_INFO("%s: efuseTbl malloc fail!\n", __FUNCTION__);
- return;
+ RTW_INFO("%s: efuseTbl or phyefuse malloc fail!\n", __FUNCTION__);
+ goto exit;
}
+
/* 0xff will be efuse default value instead of 0x00. */
_rtw_memset(efuseTbl, 0xFF, EFUSE_BT_MAP_LEN);
- _rtw_memset(phyefuse, 0xFF, EFUSE_BT_REAL_BANK_CONTENT_LEN);
+ _rtw_memset(phyefuse, 0xFF, EFUSE_BT_REAL_CONTENT_LEN);
- if(rtw_efuse_bt_access(padapter, _FALSE, 0, EFUSE_BT_REAL_BANK_CONTENT_LEN, phyefuse))
+ if (rtw_efuse_bt_access(padapter, _FALSE, 0, EFUSE_BT_REAL_CONTENT_LEN, phyefuse))
dump_buf(phyefuse, EFUSE_BT_REAL_BANK_CONTENT_LEN);
total = BANK_NUM;
@@ -824,10 +1327,13 @@ VOID hal_ReadEFuse_BT_logic_map(
efuse_usage = 100;
fakeBTEfuseUsedBytes = used;
+ RTW_INFO("%s: BTEfuseUsed last Bytes = %#x\n", __FUNCTION__, fakeBTEfuseUsedBytes);
exit:
if (efuseTbl)
rtw_mfree(efuseTbl, EFUSE_BT_MAP_LEN);
+ if (phyefuse)
+ rtw_mfree(phyefuse, EFUSE_BT_REAL_BANK_CONTENT_LEN);
}
@@ -1085,15 +1591,136 @@ hal_EfusePgPacketWriteData(
if (badworden != 0x0F) {
RTW_INFO("%s: Fail!!\n", __FUNCTION__);
return _FALSE;
- }
+ } else
+ RTW_INFO("%s: OK!!\n", __FUNCTION__);
- /* RTW_INFO("%s: ok\n", __FUNCTION__); */
return _TRUE;
}
-u8 EfusePgPacketWrite_BT(
- PADAPTER pAdapter,
- u8 offset,
+u8 efuse_OneByteRead(struct _ADAPTER *a, u16 addr, u8 *data, u8 bPseudoTest)
+{
+ struct dvobj_priv *d;
+ int err;
+ u8 ret = _TRUE;
+
+ d = adapter_to_dvobj(a);
+ err = rtw_halmac_read_physical_efuse(d, addr, 1, data);
+ if (err) {
+ RTW_ERR("%s: addr=0x%x FAIL!!!\n", __FUNCTION__, addr);
+ ret = _FALSE;
+ }
+
+ return ret;
+
+}
+
+static u16
+hal_EfuseGetCurrentSize_BT(
+ PADAPTER padapter,
+ u8 bPseudoTest)
+{
+#ifdef HAL_EFUSE_MEMORY
+ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
+ PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal;
+#endif
+ u16 btusedbytes;
+ u16 efuse_addr;
+ u8 bank, startBank;
+ u8 hoffset = 0, hworden = 0;
+ u8 efuse_data, word_cnts = 0;
+ u16 retU2 = 0;
+ u8 bContinual = _TRUE;
+
+
+ btusedbytes = fakeBTEfuseUsedBytes;
+
+ efuse_addr = (u16)((btusedbytes % EFUSE_BT_REAL_BANK_CONTENT_LEN));
+ startBank = (u8)(1 + (btusedbytes / EFUSE_BT_REAL_BANK_CONTENT_LEN));
+
+ RTW_INFO("%s: start from bank=%d addr=0x%X\n", __FUNCTION__, startBank, efuse_addr);
+ retU2 = EFUSE_BT_REAL_CONTENT_LEN - EFUSE_PROTECT_BYTES_BANK;
+
+ for (bank = startBank; bank < 3; bank++) {
+ if (hal_EfuseSwitchToBank(padapter, bank, bPseudoTest) == _FALSE) {
+ RTW_ERR("%s: switch bank(%d) Fail!!\n", __FUNCTION__, bank);
+ /* bank = EFUSE_MAX_BANK; */
+ break;
+ }
+
+ /* only when bank is switched we have to reset the efuse_addr. */
+ if (bank != startBank)
+ efuse_addr = 0;
+
+
+ while (AVAILABLE_EFUSE_ADDR(efuse_addr)) {
+ if (rtw_efuse_bt_access(padapter, _FALSE, efuse_addr, 1, &efuse_data) == _FALSE) {
+ RTW_ERR("%s: efuse_OneByteRead Fail! addr=0x%X !!\n", __FUNCTION__, efuse_addr);
+ /* bank = EFUSE_MAX_BANK; */
+ break;
+ }
+ RTW_INFO("%s: efuse_OneByteRead ! addr=0x%X !efuse_data=0x%X! bank =%d\n", __FUNCTION__, efuse_addr, efuse_data, bank);
+
+ if (efuse_data == 0xFF)
+ break;
+
+ if (EXT_HEADER(efuse_data)) {
+ hoffset = GET_HDR_OFFSET_2_0(efuse_data);
+ efuse_addr++;
+ rtw_efuse_bt_access(padapter, _FALSE, efuse_addr, 1, &efuse_data);
+ RTW_INFO("%s: efuse_OneByteRead EXT_HEADER ! addr=0x%X !efuse_data=0x%X! bank =%d\n", __FUNCTION__, efuse_addr, efuse_data, bank);
+
+ if (ALL_WORDS_DISABLED(efuse_data)) {
+ efuse_addr++;
+ continue;
+ }
+
+ /* hoffset = ((hoffset & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1); */
+ hoffset |= ((efuse_data & 0xF0) >> 1);
+ hworden = efuse_data & 0x0F;
+ } else {
+ hoffset = (efuse_data >> 4) & 0x0F;
+ hworden = efuse_data & 0x0F;
+ }
+
+ RTW_INFO(FUNC_ADPT_FMT": Offset=%d Worden=%#X\n",
+ FUNC_ADPT_ARG(padapter), hoffset, hworden);
+
+ word_cnts = Efuse_CalculateWordCnts(hworden);
+ /* read next header */
+ efuse_addr += (word_cnts * 2) + 1;
+ }
+ /* Check if we need to check next bank efuse */
+ if (efuse_addr < retU2)
+ break;/* don't need to check next bank. */
+ }
+ retU2 = ((bank - 1) * EFUSE_BT_REAL_BANK_CONTENT_LEN) + efuse_addr;
+
+ fakeBTEfuseUsedBytes = retU2;
+ RTW_INFO("%s: CurrentSize=%d\n", __FUNCTION__, retU2);
+ return retU2;
+}
+
+
+static u8
+hal_BT_EfusePgCheckAvailableAddr(
+ PADAPTER pAdapter,
+ u8 bPseudoTest)
+{
+ u16 max_available = EFUSE_BT_REAL_CONTENT_LEN - EFUSE_PROTECT_BYTES_BANK;
+ u16 current_size = 0;
+
+ RTW_INFO("%s: max_available=%d\n", __FUNCTION__, max_available);
+ current_size = hal_EfuseGetCurrentSize_BT(pAdapter, bPseudoTest);
+ if (current_size >= max_available) {
+ RTW_INFO("%s: Error!! current_size(%d)>max_available(%d)\n", __FUNCTION__, current_size, max_available);
+ return _FALSE;
+ }
+ return _TRUE;
+}
+
+u8 EfusePgPacketWrite_BT(
+ PADAPTER pAdapter,
+ u8 offset,
u8 word_en,
u8 *pData,
u8 bPseudoTest)
@@ -1102,6 +1729,9 @@ u8 EfusePgPacketWrite_BT(
u16 startAddr = 0;
u8 efuseType = EFUSE_BT;
+ if (!hal_BT_EfusePgCheckAvailableAddr(pAdapter, bPseudoTest))
+ return _FALSE;
+
hal_EfuseConstructPGPkt(offset, word_en, pData, &targetPkt);
if (!hal_EfusePartialWriteCheck(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
@@ -1123,6 +1753,7 @@ u8 EfusePgPacketWrite_BT(
#define EFUSE_CTRL REG_EFUSE_CTRL /* E-Fuse Control. */
/* ------------------------------------------------------------------------------ */
+
BOOLEAN
Efuse_Read1ByteFromFakeContent(
IN PADAPTER pAdapter,
@@ -1188,7 +1819,7 @@ Efuse_PowerSwitch(
IN u8 bWrite,
IN u8 PwrState)
{
- pAdapter->HalFunc.EfusePowerSwitch(pAdapter, bWrite, PwrState);
+ pAdapter->hal_func.EfusePowerSwitch(pAdapter, bWrite, PwrState);
}
VOID
@@ -1197,8 +1828,8 @@ BTEfuse_PowerSwitch(
IN u8 bWrite,
IN u8 PwrState)
{
- if (pAdapter->HalFunc.BTEfusePowerSwitch)
- pAdapter->HalFunc.BTEfusePowerSwitch(pAdapter, bWrite, PwrState);
+ if (pAdapter->hal_func.BTEfusePowerSwitch)
+ pAdapter->hal_func.BTEfusePowerSwitch(pAdapter, bWrite, PwrState);
}
/*-----------------------------------------------------------------------------
@@ -1225,7 +1856,7 @@ Efuse_GetCurrentSize(
{
u16 ret = 0;
- ret = pAdapter->HalFunc.EfuseGetCurrentSize(pAdapter, efuseType, bPseudoTest);
+ ret = pAdapter->hal_func.EfuseGetCurrentSize(pAdapter, efuseType, bPseudoTest);
return ret;
}
@@ -1251,7 +1882,7 @@ ReadEFuseByte(
u32 value32;
u8 readbyte;
u16 retry;
- /* u32 start=rtw_get_current_time(); */
+ /* systime start=rtw_get_current_time(); */
if (bPseudoTest) {
Efuse_Read1ByteFromFakeContent(Adapter, _offset, pbuf);
@@ -1260,7 +1891,7 @@ ReadEFuseByte(
if (IS_HARDWARE_TYPE_8723B(Adapter)) {
/* <20130121, Kordan> For SMIC S55 EFUSE specificatoin. */
/* 0x34[11]: SW force PGMEN input of efuse to high. (for the bank selected by 0x34[9:8]) */
- PHY_SetMacReg(Adapter, EFUSE_TEST, BIT11, 0);
+ phy_set_mac_reg(Adapter, EFUSE_TEST, BIT11, 0);
}
/* Write Address */
rtw_write8(Adapter, EFUSE_CTRL + 1, (_offset & 0xff));
@@ -1329,7 +1960,7 @@ efuse_ReadEFuse(
IN BOOLEAN bPseudoTest
)
{
- Adapter->HalFunc.ReadEFuse(Adapter, efuseType, _offset, _size_byte, pbuf, bPseudoTest);
+ Adapter->hal_func.ReadEFuse(Adapter, efuseType, _offset, _size_byte, pbuf, bPseudoTest);
}
VOID
@@ -1341,135 +1972,9 @@ EFUSE_GetEfuseDefinition(
IN BOOLEAN bPseudoTest
)
{
- pAdapter->HalFunc.EFUSEGetEfuseDefinition(pAdapter, efuseType, type, pOut, bPseudoTest);
+ pAdapter->hal_func.EFUSEGetEfuseDefinition(pAdapter, efuseType, type, pOut, bPseudoTest);
}
-/*-----------------------------------------------------------------------------
- * Function: EFUSE_Read1Byte
- *
- * Overview: Copy from WMAC fot EFUSE read 1 byte.
- *
- * Input: NONE
- *
- * Output: NONE
- *
- * Return: NONE
- *
- * Revised History:
- * When Who Remark
- * 09/23/2008 MHC Copy from WMAC.
- *
- *---------------------------------------------------------------------------*/
-u8
-EFUSE_Read1Byte(
- IN PADAPTER Adapter,
- IN u16 Address)
-{
- u8 data;
- u8 Bytetemp = {0x00};
- u8 temp = {0x00};
- u32 k = 0;
- u16 contentLen = 0;
-
- EFUSE_GetEfuseDefinition(Adapter, EFUSE_WIFI , TYPE_EFUSE_REAL_CONTENT_LEN, (PVOID)&contentLen, _FALSE);
-
- if (Address < contentLen) { /* E-fuse 512Byte */
- /* Write E-fuse Register address bit0~7 */
- temp = Address & 0xFF;
- rtw_write8(Adapter, EFUSE_CTRL + 1, temp);
- Bytetemp = rtw_read8(Adapter, EFUSE_CTRL + 2);
- /* Write E-fuse Register address bit8~9 */
- temp = ((Address >> 8) & 0x03) | (Bytetemp & 0xFC);
- rtw_write8(Adapter, EFUSE_CTRL + 2, temp);
-
- /* Write 0x30[31]=0 */
- Bytetemp = rtw_read8(Adapter, EFUSE_CTRL + 3);
- temp = Bytetemp & 0x7F;
- rtw_write8(Adapter, EFUSE_CTRL + 3, temp);
-
- /* Wait Write-ready (0x30[31]=1) */
- Bytetemp = rtw_read8(Adapter, EFUSE_CTRL + 3);
- while (!(Bytetemp & 0x80)) {
- Bytetemp = rtw_read8(Adapter, EFUSE_CTRL + 3);
- k++;
- if (k == 1000) {
- k = 0;
- break;
- }
- }
- data = rtw_read8(Adapter, EFUSE_CTRL);
- return data;
- } else
- return 0xFF;
-
-} /* EFUSE_Read1Byte */
-
-/*-----------------------------------------------------------------------------
- * Function: EFUSE_Write1Byte
- *
- * Overview: Copy from WMAC fot EFUSE write 1 byte.
- *
- * Input: NONE
- *
- * Output: NONE
- *
- * Return: NONE
- *
- * Revised History:
- * When Who Remark
- * 09/23/2008 MHC Copy from WMAC.
- *
- *---------------------------------------------------------------------------*/
-
-void
-EFUSE_Write1Byte(
- IN PADAPTER Adapter,
- IN u16 Address,
- IN u8 Value);
-void
-EFUSE_Write1Byte(
- IN PADAPTER Adapter,
- IN u16 Address,
- IN u8 Value)
-{
- u8 Bytetemp = {0x00};
- u8 temp = {0x00};
- u32 k = 0;
- u16 contentLen = 0;
-
- /* RT_TRACE(COMP_EFUSE, DBG_LOUD, ("Addr=%x Data =%x\n", Address, Value)); */
- EFUSE_GetEfuseDefinition(Adapter, EFUSE_WIFI , TYPE_EFUSE_REAL_CONTENT_LEN, (PVOID)&contentLen, _FALSE);
-
- if (Address < contentLen) { /* E-fuse 512Byte */
- rtw_write8(Adapter, EFUSE_CTRL, Value);
-
- /* Write E-fuse Register address bit0~7 */
- temp = Address & 0xFF;
- rtw_write8(Adapter, EFUSE_CTRL + 1, temp);
- Bytetemp = rtw_read8(Adapter, EFUSE_CTRL + 2);
-
- /* Write E-fuse Register address bit8~9 */
- temp = ((Address >> 8) & 0x03) | (Bytetemp & 0xFC);
- rtw_write8(Adapter, EFUSE_CTRL + 2, temp);
-
- /* Write 0x30[31]=1 */
- Bytetemp = rtw_read8(Adapter, EFUSE_CTRL + 3);
- temp = Bytetemp | 0x80;
- rtw_write8(Adapter, EFUSE_CTRL + 3, temp);
-
- /* Wait Write-ready (0x30[31]=0) */
- Bytetemp = rtw_read8(Adapter, EFUSE_CTRL + 3);
- while (Bytetemp & 0x80) {
- Bytetemp = rtw_read8(Adapter, EFUSE_CTRL + 3);
- k++;
- if (k == 100) {
- k = 0;
- break;
- }
- }
- }
-} /* EFUSE_Write1Byte */
-
/* 11/16/2008 MH Read one byte from real Efuse. */
u8
@@ -1493,12 +1998,12 @@ efuse_OneByteRead(
}
if (IS_HARDWARE_TYPE_8723B(pAdapter) ||
- (IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->VersionID))) ||
- (IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->VersionID))
+ (IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->version_id))) ||
+ (IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->version_id))
) {
/* <20130121, Kordan> For SMIC EFUSE specificatoin. */
/* 0x34[11]: SW force PGMEN input of efuse to high. (for the bank selected by 0x34[9:8]) */
- /* PHY_SetMacReg(pAdapter, 0x34, BIT11, 0); */
+ /* phy_set_mac_reg(pAdapter, 0x34, BIT11, 0); */
rtw_write16(pAdapter, 0x34, rtw_read16(pAdapter, 0x34) & (~BIT11));
}
@@ -1551,6 +2056,7 @@ efuse_OneByteWrite(
return bResult;
}
+ Efuse_PowerSwitch(pAdapter, _TRUE, _TRUE);
/* -----------------e-fuse reg ctrl --------------------------------- */
/* address */
@@ -1563,17 +2069,19 @@ efuse_OneByteWrite(
/* <20130227, Kordan> 8192E MP chip A-cut had better not set 0x34[11] until B-Cut. */
if (IS_HARDWARE_TYPE_8723B(pAdapter) ||
- (IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->VersionID))) ||
- (IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->VersionID))
+ (IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->version_id))) ||
+ (IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->version_id))
) {
/* <20130121, Kordan> For SMIC EFUSE specificatoin. */
/* 0x34[11]: SW force PGMEN input of efuse to high. (for the bank selected by 0x34[9:8]) */
- /* PHY_SetMacReg(pAdapter, 0x34, BIT11, 1); */
+ /* phy_set_mac_reg(pAdapter, 0x34, BIT11, 1); */
rtw_write16(pAdapter, 0x34, rtw_read16(pAdapter, 0x34) | (BIT11));
rtw_write32(pAdapter, EFUSE_CTRL, 0x90600000 | ((addr << 8 | data)));
} else
rtw_write32(pAdapter, EFUSE_CTRL, efuseValue);
+ rtw_mdelay_os(1);
+
while ((0x80 & rtw_read8(pAdapter, EFUSE_CTRL + 3)) && (tmpidx < 100)) {
rtw_mdelay_os(1);
tmpidx++;
@@ -1590,10 +2098,12 @@ efuse_OneByteWrite(
/* disable Efuse program enable */
if (IS_HARDWARE_TYPE_8723B(pAdapter) ||
- (IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->VersionID))) ||
- (IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->VersionID))
+ (IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->version_id))) ||
+ (IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->version_id))
)
- PHY_SetMacReg(pAdapter, EFUSE_TEST, BIT(11), 0);
+ phy_set_mac_reg(pAdapter, EFUSE_TEST, BIT(11), 0);
+
+ Efuse_PowerSwitch(pAdapter, _TRUE, _FALSE);
return bResult;
}
@@ -1606,7 +2116,7 @@ Efuse_PgPacketRead(IN PADAPTER pAdapter,
{
int ret = 0;
- ret = pAdapter->HalFunc.Efuse_PgPacketRead(pAdapter, offset, data, bPseudoTest);
+ ret = pAdapter->hal_func.Efuse_PgPacketRead(pAdapter, offset, data, bPseudoTest);
return ret;
}
@@ -1620,7 +2130,7 @@ Efuse_PgPacketWrite(IN PADAPTER pAdapter,
{
int ret;
- ret = pAdapter->HalFunc.Efuse_PgPacketWrite(pAdapter, offset, word_en, data, bPseudoTest);
+ ret = pAdapter->hal_func.Efuse_PgPacketWrite(pAdapter, offset, word_en, data, bPseudoTest);
return ret;
}
@@ -1635,7 +2145,7 @@ Efuse_PgPacketWrite_BT(IN PADAPTER pAdapter,
{
int ret;
- ret = pAdapter->HalFunc.Efuse_PgPacketWrite_BT(pAdapter, offset, word_en, data, bPseudoTest);
+ ret = pAdapter->hal_func.Efuse_PgPacketWrite_BT(pAdapter, offset, word_en, data, bPseudoTest);
return ret;
}
@@ -1650,7 +2160,7 @@ Efuse_WordEnableDataWrite(IN PADAPTER pAdapter,
{
u8 ret = 0;
- ret = pAdapter->HalFunc.Efuse_WordEnableDataWrite(pAdapter, efuse_addr, word_en, data, bPseudoTest);
+ ret = pAdapter->hal_func.Efuse_WordEnableDataWrite(pAdapter, efuse_addr, word_en, data, bPseudoTest);
return ret;
}
@@ -1674,6 +2184,8 @@ u8 rtw_efuse_access(PADAPTER padapter, u8 bWrite, u16 start_addr, u16 cnts, u8 *
u16 real_content_len = 0, max_available_size = 0;
u8 res = _FAIL ;
u8(*rw8)(PADAPTER, u16, u8 *);
+ u32 backupRegs[4] = {0};
+
EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_REAL_CONTENT_LEN, (PVOID)&real_content_len, _FALSE);
EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE);
@@ -1688,6 +2200,8 @@ u8 rtw_efuse_access(PADAPTER padapter, u8 bWrite, u16 start_addr, u16 cnts, u8 *
} else
rw8 = &efuse_read8;
+ efuse_PreUpdateAction(padapter, backupRegs);
+
Efuse_PowerSwitch(padapter, bWrite, _TRUE);
/* e-fuse one byte read / write */
@@ -1704,6 +2218,8 @@ u8 rtw_efuse_access(PADAPTER padapter, u8 bWrite, u16 start_addr, u16 cnts, u8 *
Efuse_PowerSwitch(padapter, bWrite, _FALSE);
+ efuse_PostUpdateAction(padapter, backupRegs);
+
return res;
}
/* ------------------------------------------------------------------------------ */
@@ -1789,15 +2305,20 @@ u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
return _FAIL; \
}
+ u8 *efuse = NULL;
u8 offset, word_en;
- u8 *map;
+ u8 *map = NULL;
u8 newdata[PGPKT_DATA_SIZE];
- s32 i, j, idx;
+ s32 i, j, idx, chk_total_byte;
u8 ret = _SUCCESS;
- u16 mapLen = 0;
+ u16 mapLen = 0, startAddr = 0, efuse_max_available_len = 0;
+ u32 backupRegs[4] = {0};
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+ PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal;
+
EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, _FALSE);
+ EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &efuse_max_available_len, _FALSE);
if ((addr + cnts) > mapLen)
return _FAIL;
@@ -1805,9 +2326,15 @@ u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
RT_ASSERT_RET(PGPKT_DATA_SIZE == 8); /* have to be 8 byte alignment */
RT_ASSERT_RET((mapLen & 0x7) == 0); /* have to be PGPKT_DATA_SIZE alignment for memcpy */
+ efuse = rtw_zmalloc(mapLen);
+ if (!efuse)
+ return _FAIL;
+
map = rtw_zmalloc(mapLen);
- if (map == NULL)
+ if (map == NULL) {
+ rtw_mfree(efuse, mapLen);
return _FAIL;
+ }
_rtw_memset(map, 0xFF, mapLen);
@@ -1815,19 +2342,64 @@ u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
if (ret == _FAIL)
goto exit;
+ _rtw_memcpy(efuse , map, mapLen);
+ _rtw_memcpy(efuse + addr, data, cnts);
+
if (padapter->registrypriv.boffefusemask == 0) {
for (i = 0; i < cnts; i++) {
if (padapter->registrypriv.bFileMaskEfuse == _TRUE) {
if (rtw_file_efuse_IsMasked(padapter, addr + i)) /*use file efuse mask. */
- data[i] = map[addr + i];
+ efuse[addr + i] = map[addr + i];
} else {
if (efuse_IsMasked(padapter, addr + i))
- data[i] = map[addr + i];
+ efuse[addr + i] = map[addr + i];
}
- RTW_INFO("%s , data[%d] = %x, map[addr+i]= %x\n", __func__, i, data[i], map[addr + i]);
+ RTW_INFO("%s , data[%d] = %x, map[addr+i]= %x\n", __func__, addr + i, efuse[ addr + i], map[addr + i]);
}
}
- Efuse_PowerSwitch(padapter, _TRUE, _TRUE);
+ /*Efuse_PowerSwitch(padapter, _TRUE, _TRUE);*/
+
+ chk_total_byte = 0;
+ idx = 0;
+ offset = (addr >> 3);
+
+ while (idx < cnts) {
+ word_en = 0xF;
+ j = (addr + idx) & 0x7;
+ for (i = j; i < PGPKT_DATA_SIZE && idx < cnts; i++, idx++) {
+ if (efuse[addr + idx] != map[addr + idx])
+ word_en &= ~BIT(i >> 1);
+ }
+
+ if (word_en != 0xF) {
+ chk_total_byte += Efuse_CalculateWordCnts(word_en) * 2;
+
+ if (offset >= EFUSE_MAX_SECTION_BASE) /* Over EFUSE_MAX_SECTION 16 for 2 ByteHeader */
+ chk_total_byte += 2;
+ else
+ chk_total_byte += 1;
+ }
+
+ offset++;
+ }
+
+ RTW_INFO("Total PG bytes Count = %d\n", chk_total_byte);
+ rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&startAddr);
+
+ if (startAddr == 0) {
+ startAddr = Efuse_GetCurrentSize(padapter, EFUSE_WIFI, _FALSE);
+ RTW_INFO("%s: Efuse_GetCurrentSize startAddr=%#X\n", __func__, startAddr);
+ }
+ RTW_DBG("%s: startAddr=%#X\n", __func__, startAddr);
+
+ if ((startAddr + chk_total_byte) >= efuse_max_available_len) {
+ RTW_INFO("%s: startAddr(0x%X) + PG data len %d >= efuse_max_available_len(0x%X)\n",
+ __func__, startAddr, chk_total_byte, efuse_max_available_len);
+ ret = _FAIL;
+ goto exit;
+ }
+
+ efuse_PreUpdateAction(padapter, backupRegs);
idx = 0;
offset = (addr >> 3);
@@ -1836,12 +2408,12 @@ u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
j = (addr + idx) & 0x7;
_rtw_memcpy(newdata, &map[offset << 3], PGPKT_DATA_SIZE);
for (i = j; i < PGPKT_DATA_SIZE && idx < cnts; i++, idx++) {
- if (data[idx] != map[addr + idx]) {
+ if (efuse[addr + idx] != map[addr + idx]) {
word_en &= ~BIT(i >> 1);
- newdata[i] = data[idx];
+ newdata[i] = efuse[addr + idx];
#ifdef CONFIG_RTL8723B
if (addr + idx == 0x8) {
- if (IS_C_CUT(pHalData->VersionID) || IS_B_CUT(pHalData->VersionID)) {
+ if (IS_C_CUT(pHalData->version_id) || IS_B_CUT(pHalData->version_id)) {
if (pHalData->adjuseVoltageVal == 6) {
newdata[i] = map[addr + idx];
RTW_INFO(" %s ,\n adjuseVoltageVal = %d ,newdata[%d] = %x\n", __func__, pHalData->adjuseVoltageVal, i, newdata[i]);
@@ -1866,43 +2438,18 @@ u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
offset++;
}
- Efuse_PowerSwitch(padapter, _TRUE, _FALSE);
+ /*Efuse_PowerSwitch(padapter, _TRUE, _FALSE);*/
+
+ efuse_PostUpdateAction(padapter, backupRegs);
exit:
rtw_mfree(map, mapLen);
+ rtw_mfree(efuse, mapLen);
return ret;
}
-u8 rtw_efuse_mask_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
-{
- u8 ret = _SUCCESS;
- u16 mapLen = 0, i = 0;
-
- EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, _FALSE);
-
- ret = rtw_efuse_map_read(padapter, addr, cnts , data);
-
- if (padapter->registrypriv.boffefusemask == 0) {
-
- for (i = 0; i < cnts; i++) {
- if (padapter->registrypriv.bFileMaskEfuse == _TRUE) {
- if (rtw_file_efuse_IsMasked(padapter, addr + i)) /*use file efuse mask.*/
- data[i] = 0xff;
- } else {
- /*RTW_INFO(" %s , data[%d] = %x\n", __func__, i, data[i]);*/
- if (efuse_IsMasked(padapter, addr + i)) {
- data[i] = 0xff;
- /*RTW_INFO(" %s ,mask data[%d] = %x\n", __func__, i, data[i]);*/
- }
- }
- }
-
- }
- return ret;
-
-}
u8 rtw_BT_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data)
{
@@ -2025,67 +2572,6 @@ Efuse_ReadAllMap(
Efuse_PowerSwitch(pAdapter, _FALSE, _FALSE);
}
-/*-----------------------------------------------------------------------------
- * Function: efuse_ShadowRead1Byte
- * efuse_ShadowRead2Byte
- * efuse_ShadowRead4Byte
- *
- * Overview: Read from efuse init map by one/two/four bytes !!!!!
- *
- * Input: NONE
- *
- * Output: NONE
- *
- * Return: NONE
- *
- * Revised History:
- * When Who Remark
- * 11/12/2008 MHC Create Version 0.
- *
- *---------------------------------------------------------------------------*/
-static VOID
-efuse_ShadowRead1Byte(
- IN PADAPTER pAdapter,
- IN u16 Offset,
- IN OUT u8 *Value)
-{
- PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
-
- *Value = pHalData->efuse_eeprom_data[Offset];
-
-} /* EFUSE_ShadowRead1Byte */
-
-/* ---------------Read Two Bytes */
-static VOID
-efuse_ShadowRead2Byte(
- IN PADAPTER pAdapter,
- IN u16 Offset,
- IN OUT u16 *Value)
-{
- PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
-
- *Value = pHalData->efuse_eeprom_data[Offset];
- *Value |= pHalData->efuse_eeprom_data[Offset + 1] << 8;
-
-} /* EFUSE_ShadowRead2Byte */
-
-/* ---------------Read Four Bytes */
-static VOID
-efuse_ShadowRead4Byte(
- IN PADAPTER pAdapter,
- IN u16 Offset,
- IN OUT u32 *Value)
-{
- PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
-
- *Value = pHalData->efuse_eeprom_data[Offset];
- *Value |= pHalData->efuse_eeprom_data[Offset + 1] << 8;
- *Value |= pHalData->efuse_eeprom_data[Offset + 2] << 16;
- *Value |= pHalData->efuse_eeprom_data[Offset + 3] << 24;
-
-} /* efuse_ShadowRead4Byte */
-
-
/*-----------------------------------------------------------------------------
* Function: efuse_ShadowWrite1Byte
* efuse_ShadowWrite2Byte
@@ -2156,38 +2642,6 @@ efuse_ShadowWrite4Byte(
} /* efuse_ShadowWrite1Byte */
-/*-----------------------------------------------------------------------------
- * Function: EFUSE_ShadowRead
- *
- * Overview: Read from efuse init map !!!!!
- *
- * Input: NONE
- *
- * Output: NONE
- *
- * Return: NONE
- *
- * Revised History:
- * When Who Remark
- * 11/12/2008 MHC Create Version 0.
- *
- *---------------------------------------------------------------------------*/
-void
-EFUSE_ShadowRead(
- IN PADAPTER pAdapter,
- IN u8 Type,
- IN u16 Offset,
- IN OUT u32 *Value)
-{
- if (Type == 1)
- efuse_ShadowRead1Byte(pAdapter, Offset, (u8 *)Value);
- else if (Type == 2)
- efuse_ShadowRead2Byte(pAdapter, Offset, (u16 *)Value);
- else if (Type == 4)
- efuse_ShadowRead4Byte(pAdapter, Offset, (u32 *)Value);
-
-} /* EFUSE_ShadowRead */
-
/*-----------------------------------------------------------------------------
* Function: EFUSE_ShadowWrite
*
@@ -2259,6 +2713,87 @@ Efuse_InitSomeVar(
_rtw_memset((PVOID)&fakeBTEfuseModifiedMap[0], 0xff, EFUSE_BT_MAX_MAP_LEN);
}
#endif /* !RTW_HALMAC */
+/*-----------------------------------------------------------------------------
+ * Function: efuse_ShadowRead1Byte
+ * efuse_ShadowRead2Byte
+ * efuse_ShadowRead4Byte
+ *
+ * Overview: Read from efuse init map by one/two/four bytes !!!!!
+ *
+ * Input: NONE
+ *
+ * Output: NONE
+ *
+ * Return: NONE
+ *
+ * Revised History:
+ * When Who Remark
+ * 11/12/2008 MHC Create Version 0.
+ *
+ *---------------------------------------------------------------------------*/
+static VOID
+efuse_ShadowRead1Byte(
+ IN PADAPTER pAdapter,
+ IN u16 Offset,
+ IN OUT u8 *Value)
+{
+ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
+
+ *Value = pHalData->efuse_eeprom_data[Offset];
+
+} /* EFUSE_ShadowRead1Byte */
+
+/* ---------------Read Two Bytes */
+static VOID
+efuse_ShadowRead2Byte(
+ IN PADAPTER pAdapter,
+ IN u16 Offset,
+ IN OUT u16 *Value)
+{
+ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
+
+ *Value = pHalData->efuse_eeprom_data[Offset];
+ *Value |= pHalData->efuse_eeprom_data[Offset + 1] << 8;
+
+} /* EFUSE_ShadowRead2Byte */
+
+/* ---------------Read Four Bytes */
+static VOID
+efuse_ShadowRead4Byte(
+ IN PADAPTER pAdapter,
+ IN u16 Offset,
+ IN OUT u32 *Value)
+{
+ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
+
+ *Value = pHalData->efuse_eeprom_data[Offset];
+ *Value |= pHalData->efuse_eeprom_data[Offset + 1] << 8;
+ *Value |= pHalData->efuse_eeprom_data[Offset + 2] << 16;
+ *Value |= pHalData->efuse_eeprom_data[Offset + 3] << 24;
+
+} /* efuse_ShadowRead4Byte */
+
+/*-----------------------------------------------------------------------------
+ * Function: EFUSE_ShadowRead
+ *
+ * Overview: Read from pHalData->efuse_eeprom_data
+ *---------------------------------------------------------------------------*/
+void
+EFUSE_ShadowRead(
+ IN PADAPTER pAdapter,
+ IN u8 Type,
+ IN u16 Offset,
+ IN OUT u32 *Value)
+{
+ if (Type == 1)
+ efuse_ShadowRead1Byte(pAdapter, Offset, (u8 *)Value);
+ else if (Type == 2)
+ efuse_ShadowRead2Byte(pAdapter, Offset, (u16 *)Value);
+ else if (Type == 4)
+ efuse_ShadowRead4Byte(pAdapter, Offset, (u32 *)Value);
+
+} /* EFUSE_ShadowRead */
+
/* 11/16/2008 MH Add description. Get current efuse area enabled word!!. */
u8
Efuse_CalculateWordCnts(IN u8 word_en)
@@ -2360,7 +2895,7 @@ void EFUSE_ShadowMapUpdate(
}
if (pHalData->bautoload_fail_flag == _FALSE) {
- err = rtw_halmac_read_logical_efuse_map(adapter_to_dvobj(pAdapter), efuse_map, mapLen);
+ err = rtw_halmac_read_logical_efuse_map(adapter_to_dvobj(pAdapter), efuse_map, mapLen, NULL, 0);
if (err)
RTW_ERR("%s: fail to get efuse map!\n", __FUNCTION__);
}
@@ -2386,6 +2921,8 @@ void EFUSE_ShadowMapUpdate(
/* (PVOID)&pHalData->EfuseMap[EFUSE_INIT_MAP][0], mapLen); */
#endif /* !RTW_HALMAC */
+ rtw_mask_map_read(pAdapter, 0x00, mapLen, pHalData->efuse_eeprom_data);
+
rtw_dump_cur_efuse(pAdapter);
} /* EFUSE_ShadowMapUpdate */
@@ -2482,7 +3019,7 @@ int retriveAdaptorInfoFile(char *path, u8 *efuse_data)
u8 rtw_efuse_file_read(PADAPTER padapter, u8 *filepatch, u8 *buf, u32 len)
{
char *ptmpbuf = NULL, *ptr;
- unsigned long val16;
+ u8 val8;
u32 count, i, j;
int err;
u32 bufsize = 4096;
@@ -2492,7 +3029,7 @@ u8 rtw_efuse_file_read(PADAPTER padapter, u8 *filepatch, u8 *buf, u32 len)
return _FALSE;
count = rtw_retrieve_from_file(filepatch, ptmpbuf, bufsize);
- if (count <= 100) {
+ if (count <= 90) {
rtw_mfree(ptmpbuf, bufsize);
RTW_ERR("%s, filepatch %s, size=%d, FAIL!!\n", __FUNCTION__, filepatch, count);
return _FALSE;
@@ -2518,11 +3055,11 @@ u8 rtw_efuse_file_read(PADAPTER padapter, u8 *filepatch, u8 *buf, u32 len)
ptr = &ptmpbuf[count-1];
}
- err = kstrtoul(&ptmpbuf[i], 16, &val16);
- if (err) {
+ err = sscanf(&ptmpbuf[i], "%hhx", &val8);
+ if (err != 1) {
RTW_WARN("Something wrong to parse efuse file, string=%s\n", &ptmpbuf[i]);
} else {
- buf[j] = (u8)val16;
+ buf[j] = val8;
RTW_DBG("i=%d, j=%d, 0x%02x\n", i, j, buf[j]);
j++;
}
@@ -2536,126 +3073,143 @@ u8 rtw_efuse_file_read(PADAPTER padapter, u8 *filepatch, u8 *buf, u32 len)
}
#ifdef CONFIG_EFUSE_CONFIG_FILE
-u32 rtw_read_efuse_from_file(const char *path, u8 *buf)
+u32 rtw_read_efuse_from_file(const char *path, u8 *buf, int map_size)
{
u32 i;
+ u8 c;
u8 temp[3];
+ u8 temp_i;
+ u8 end = _FALSE;
u32 ret = _FAIL;
- struct file *fp;
- mm_segment_t fs;
- loff_t pos = 0;
-
- fp = filp_open(path, O_RDONLY, 0);
- if (fp == NULL || IS_ERR(fp)) {
- if (fp != NULL)
- RTW_PRINT("%s open %s fail, err:%ld\n"
- , __func__, path, PTR_ERR(fp));
- else
- RTW_PRINT("%s open %s fail, fp is NULL\n"
- , __func__, path);
+ u8 *file_data = NULL;
+ u32 file_size, read_size, pos = 0;
+ u8 *map = NULL;
+
+ if (rtw_is_file_readable_with_size(path, &file_size) != _TRUE) {
+ RTW_PRINT("%s %s is not readable\n", __func__, path);
+ goto exit;
+ }
+
+ file_data = rtw_vmalloc(file_size);
+ if (!file_data) {
+ RTW_ERR("%s rtw_vmalloc(%d) fail\n", __func__, file_size);
+ goto exit;
+ }
+
+ read_size = rtw_retrieve_from_file(path, file_data, file_size);
+ if (read_size == 0) {
+ RTW_ERR("%s read from %s fail\n", __func__, path);
+ goto exit;
+ }
+ map = rtw_vmalloc(map_size);
+ if (!map) {
+ RTW_ERR("%s rtw_vmalloc(%d) fail\n", __func__, map_size);
goto exit;
}
+ _rtw_memset(map, 0xff, map_size);
+
+ temp[2] = 0; /* end of string '\0' */
+
+ for (i = 0 ; i < map_size ; i++) {
+ temp_i = 0;
- temp[2] = 0; /* add end of string '\0' */
+ while (1) {
+ if (pos >= read_size) {
+ end = _TRUE;
+ break;
+ }
+ c = file_data[pos++];
+
+ /* bypass spece or eol or null before first hex digit */
+ if (temp_i == 0 && (is_eol(c) == _TRUE || is_space(c) == _TRUE || is_null(c) == _TRUE))
+ continue;
+
+ if (IsHexDigit(c) == _FALSE) {
+ RTW_ERR("%s invalid 8-bit hex format for offset:0x%03x\n", __func__, i);
+ goto exit;
+ }
- fs = get_fs();
- set_fs(KERNEL_DS);
+ temp[temp_i++] = c;
- for (i = 0 ; i < HWSET_MAX_SIZE ; i++) {
- vfs_read(fp, temp, 2, &pos);
- if (sscanf(temp, "%hhx", &buf[i]) != 1) {
- if (0)
- RTW_ERR("%s sscanf fail\n", __func__);
- buf[i] = 0xFF;
+ if (temp_i == 2) {
+ /* parse value */
+ if (sscanf(temp, "%hhx", &map[i]) != 1) {
+ RTW_ERR("%s sscanf fail for offset:0x%03x\n", __func__, i);
+ goto exit;
+ }
+ break;
+ }
}
- if ((i % EFUSE_FILE_COLUMN_NUM) == (EFUSE_FILE_COLUMN_NUM - 1)) {
- /* Filter the lates space char. */
- vfs_read(fp, temp, 1, &pos);
- if (strchr(temp, ' ') == NULL) {
- pos--;
- vfs_read(fp, temp, 2, &pos);
+
+ if (end == _TRUE) {
+ if (temp_i != 0) {
+ RTW_ERR("%s incomplete 8-bit hex format for offset:0x%03x\n", __func__, i);
+ goto exit;
}
- } else {
- pos += 1; /* Filter the space character */
+ break;
}
}
- set_fs(fs);
+ RTW_PRINT("efuse file:%s, 0x%03x byte content read\n", path, i);
- RTW_PRINT("efuse file: %s\n", path);
-#ifdef CONFIG_RTW_DEBUG
- for (i = 0; i < HWSET_MAX_SIZE; i++) {
- if (i % 16 == 0)
- RTW_PRINT_SEL(RTW_DBGDUMP, "0x%03x: ", i);
-
- _RTW_PRINT_SEL(RTW_DBGDUMP, "%02X%s"
- , buf[i]
- , ((i + 1) % 16 == 0) ? "\n" : (((i + 1) % 8 == 0) ? " " : " ")
- );
- }
- _RTW_PRINT_SEL(RTW_DBGDUMP, "\n");
-#endif
+ _rtw_memcpy(buf, map, map_size);
ret = _SUCCESS;
exit:
+ if (file_data)
+ rtw_vmfree(file_data, file_size);
+ if (map)
+ rtw_vmfree(map, map_size);
+
return ret;
}
u32 rtw_read_macaddr_from_file(const char *path, u8 *buf)
{
- struct file *fp;
- mm_segment_t fs;
- loff_t pos = 0;
-
- u8 source_addr[18];
- u8 *head, *end;
- int i;
+ u32 i;
+ u8 temp[3];
u32 ret = _FAIL;
- _rtw_memset(source_addr, 0, 18);
-
- fp = filp_open(path, O_RDONLY, 0);
- if (fp == NULL || IS_ERR(fp)) {
- if (fp != NULL)
- RTW_PRINT("%s open %s fail, err:%ld\n"
- , __func__, path, PTR_ERR(fp));
- else
- RTW_PRINT("%s open %s fail, fp is NULL\n"
- , __func__, path);
+ u8 file_data[17];
+ u32 read_size, pos = 0;
+ u8 addr[ETH_ALEN];
+ if (rtw_is_file_readable(path) != _TRUE) {
+ RTW_PRINT("%s %s is not readable\n", __func__, path);
goto exit;
}
- fs = get_fs();
- set_fs(KERNEL_DS);
-
- vfs_read(fp, source_addr, 18, &pos);
- source_addr[17] = ':';
+ read_size = rtw_retrieve_from_file(path, file_data, 17);
+ if (read_size != 17) {
+ RTW_ERR("%s read from %s fail\n", __func__, path);
+ goto exit;
+ }
- head = end = source_addr;
- for (i = 0; i < ETH_ALEN; i++) {
- while (end && (*end != ':'))
- end++;
+ temp[2] = 0; /* end of string '\0' */
- if (end && (*end == ':'))
- *end = '\0';
+ for (i = 0 ; i < ETH_ALEN ; i++) {
+ if (IsHexDigit(file_data[i * 3]) == _FALSE || IsHexDigit(file_data[i * 3 + 1]) == _FALSE) {
+ RTW_ERR("%s invalid 8-bit hex format for address offset:%u\n", __func__, i);
+ goto exit;
+ }
- if (sscanf(head, "%hhx", &buf[i]) != 1) {
- if (0)
- RTW_ERR("%s sscanf fail\n", __func__);
- buf[i] = 0xFF;
+ if (i < ETH_ALEN - 1 && file_data[i * 3 + 2] != ':') {
+ RTW_ERR("%s invalid separator after address offset:%u\n", __func__, i);
+ goto exit;
}
- if (end) {
- end++;
- head = end;
+ temp[0] = file_data[i * 3];
+ temp[1] = file_data[i * 3 + 1];
+ if (sscanf(temp, "%hhx", &addr[i]) != 1) {
+ RTW_ERR("%s sscanf fail for address offset:0x%03x\n", __func__, i);
+ goto exit;
}
}
- set_fs(fs);
+ _rtw_memcpy(buf, addr, ETH_ALEN);
RTW_PRINT("wifi_mac file: %s\n", path);
#ifdef CONFIG_RTW_DEBUG
diff --git a/core/mesh/rtw_mesh.c b/core/mesh/rtw_mesh.c
new file mode 100644
index 0000000..1c33616
--- /dev/null
+++ b/core/mesh/rtw_mesh.c
@@ -0,0 +1,3630 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTW_MESH_C_
+
+#ifdef CONFIG_RTW_MESH
+#include
+
+const char *_rtw_mesh_plink_str[] = {
+ "UNKNOWN",
+ "LISTEN",
+ "OPN_SNT",
+ "OPN_RCVD",
+ "CNF_RCVD",
+ "ESTAB",
+ "HOLDING",
+ "BLOCKED",
+};
+
+const char *_rtw_mesh_ps_str[] = {
+ "UNKNOWN",
+ "ACTIVE",
+ "LSLEEP",
+ "DSLEEP",
+};
+
+const char *_action_self_protected_str[] = {
+ "ACT_SELF_PROTECTED_RSVD",
+ "MESH_OPEN",
+ "MESH_CONF",
+ "MESH_CLOSE",
+ "MESH_GK_INFORM",
+ "MESH_GK_ACK",
+};
+
+inline u8 *rtw_set_ie_mesh_id(u8 *buf, u32 *buf_len, const char *mesh_id, u8 id_len)
+{
+ return rtw_set_ie(buf, WLAN_EID_MESH_ID, id_len, mesh_id, buf_len);
+}
+
+inline u8 *rtw_set_ie_mesh_config(u8 *buf, u32 *buf_len
+ , u8 path_sel_proto, u8 path_sel_metric, u8 congest_ctl_mode, u8 sync_method, u8 auth_proto
+ , u8 num_of_peerings, bool cto_mgate, bool cto_as
+ , bool accept_peerings, bool mcca_sup, bool mcca_en, bool forwarding
+ , bool mbca_en, bool tbtt_adj, bool ps_level)
+{
+
+ u8 conf[7] = {0};
+
+ SET_MESH_CONF_ELE_PATH_SEL_PROTO_ID(conf, path_sel_proto);
+ SET_MESH_CONF_ELE_PATH_SEL_METRIC_ID(conf, path_sel_metric);
+ SET_MESH_CONF_ELE_CONGEST_CTRL_MODE_ID(conf, congest_ctl_mode);
+ SET_MESH_CONF_ELE_SYNC_METHOD_ID(conf, sync_method);
+ SET_MESH_CONF_ELE_AUTH_PROTO_ID(conf, auth_proto);
+
+ SET_MESH_CONF_ELE_CTO_MGATE(conf, cto_mgate);
+ SET_MESH_CONF_ELE_NUM_OF_PEERINGS(conf, num_of_peerings);
+ SET_MESH_CONF_ELE_CTO_AS(conf, cto_as);
+
+ SET_MESH_CONF_ELE_ACCEPT_PEERINGS(conf, accept_peerings);
+ SET_MESH_CONF_ELE_MCCA_SUP(conf, mcca_sup);
+ SET_MESH_CONF_ELE_MCCA_EN(conf, mcca_en);
+ SET_MESH_CONF_ELE_FORWARDING(conf, forwarding);
+ SET_MESH_CONF_ELE_MBCA_EN(conf, mbca_en);
+ SET_MESH_CONF_ELE_TBTT_ADJ(conf, tbtt_adj);
+ SET_MESH_CONF_ELE_PS_LEVEL(conf, ps_level);
+
+ return rtw_set_ie(buf, WLAN_EID_MESH_CONFIG, 7, conf, buf_len);
+}
+
+inline u8 *rtw_set_ie_mpm(u8 *buf, u32 *buf_len
+ , u8 proto_id, u16 llid, u16 *plid, u16 *reason, u8 *chosen_pmk)
+{
+ u8 data[24] = {0};
+ u8 *pos = data;
+
+ RTW_PUT_LE16(pos, proto_id);
+ pos += 2;
+
+ RTW_PUT_LE16(pos, llid);
+ pos += 2;
+
+ if (plid) {
+ RTW_PUT_LE16(pos, *plid);
+ pos += 2;
+ }
+
+ if (reason) {
+ RTW_PUT_LE16(pos, *reason);
+ pos += 2;
+ }
+
+ if (chosen_pmk) {
+ _rtw_memcpy(pos, chosen_pmk, 16);
+ pos += 16;
+ }
+
+ return rtw_set_ie(buf, WLAN_EID_MPM, pos - data, data, buf_len);
+}
+
+bool rtw_bss_is_forwarding(WLAN_BSSID_EX *bss)
+{
+ u8 *ie;
+ int ie_len;
+ bool ret = 0;
+
+ ie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len,
+ BSS_EX_TLV_IES_LEN(bss));
+ if (!ie || ie_len != 7)
+ goto exit;
+
+ ret = GET_MESH_CONF_ELE_FORWARDING(ie + 2);
+
+exit:
+ return ret;
+}
+
+bool rtw_bss_is_cto_mgate(WLAN_BSSID_EX *bss)
+{
+ u8 *ie;
+ int ie_len;
+ bool ret = 0;
+
+ ie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len,
+ BSS_EX_TLV_IES_LEN(bss));
+ if (!ie || ie_len != 7)
+ goto exit;
+
+ ret = GET_MESH_CONF_ELE_CTO_MGATE(ie + 2);
+
+exit:
+ return ret;
+}
+
+int rtw_bss_is_same_mbss(WLAN_BSSID_EX *a, WLAN_BSSID_EX *b)
+{
+ int ret = 0;
+ u8 *a_mconf_ie, *b_mconf_ie;
+ sint a_mconf_ie_len, b_mconf_ie_len;
+
+ if (a->InfrastructureMode != Ndis802_11_mesh)
+ goto exit;
+ a_mconf_ie = rtw_get_ie(BSS_EX_TLV_IES(a), WLAN_EID_MESH_CONFIG, &a_mconf_ie_len, BSS_EX_TLV_IES_LEN(a));
+ if (!a_mconf_ie || a_mconf_ie_len != 7)
+ goto exit;
+ if (b->InfrastructureMode != Ndis802_11_mesh)
+ goto exit;
+ b_mconf_ie = rtw_get_ie(BSS_EX_TLV_IES(b), WLAN_EID_MESH_CONFIG, &b_mconf_ie_len, BSS_EX_TLV_IES_LEN(b));
+ if (!b_mconf_ie || b_mconf_ie_len != 7)
+ goto exit;
+
+ if (a->mesh_id.SsidLength != b->mesh_id.SsidLength
+ || _rtw_memcmp(a->mesh_id.Ssid, b->mesh_id.Ssid, a->mesh_id.SsidLength) == _FALSE)
+ goto exit;
+
+ if (_rtw_memcmp(a_mconf_ie + 2, b_mconf_ie + 2, 5) == _FALSE)
+ goto exit;
+
+ ret = 1;
+
+exit:
+ return ret;
+}
+
+int rtw_bss_is_candidate_mesh_peer(WLAN_BSSID_EX *self, WLAN_BSSID_EX *target, u8 ch, u8 add_peer)
+{
+ int ret = 0;
+ u8 *mconf_ie;
+ sint mconf_ie_len;
+ int i, j;
+
+ if (!rtw_bss_is_same_mbss(self, target))
+ goto exit;
+
+ if (ch && self->Configuration.DSConfig != target->Configuration.DSConfig)
+ goto exit;
+
+ if (add_peer) {
+ /* Accept additional mesh peerings */
+ mconf_ie = rtw_get_ie(BSS_EX_TLV_IES(target), WLAN_EID_MESH_CONFIG, &mconf_ie_len, BSS_EX_TLV_IES_LEN(target));
+ if (!mconf_ie || mconf_ie_len != 7)
+ goto exit;
+ if (GET_MESH_CONF_ELE_ACCEPT_PEERINGS(mconf_ie + 2) == 0)
+ goto exit;
+ }
+
+ /* BSSBasicRateSet */
+ for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {
+ if (target->SupportedRates[i] == 0)
+ break;
+ if (target->SupportedRates[i] & 0x80) {
+ u8 match = 0;
+
+ if (!ch) {
+ /* off-channel, check target with our hardcode capability */
+ if (target->Configuration.DSConfig > 14)
+ match = rtw_is_basic_rate_ofdm(target->SupportedRates[i]);
+ else
+ match = rtw_is_basic_rate_mix(target->SupportedRates[i]);
+ } else {
+ for (j = 0; j < NDIS_802_11_LENGTH_RATES_EX; j++) {
+ if (self->SupportedRates[j] == 0)
+ break;
+ if (self->SupportedRates[j] == target->SupportedRates[i]) {
+ match = 1;
+ break;
+ }
+ }
+ }
+ if (!match)
+ goto exit;
+ }
+ }
+
+
+ /* BSSBasicMCSSet */
+
+ /* 802.1X connected to AS ? */
+
+ ret = 1;
+
+exit:
+ return ret;
+}
+
+#if CONFIG_RTW_MESH_PEER_BLACKLIST
+int rtw_mesh_peer_blacklist_add(_adapter *adapter, const u8 *addr)
+{
+ struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+
+ return rtw_blacklist_add(&plink_ctl->peer_blacklist, addr
+ , mcfg->peer_sel_policy.peer_blacklist_timeout_ms);
+}
+
+int rtw_mesh_peer_blacklist_del(_adapter *adapter, const u8 *addr)
+{
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+
+ return rtw_blacklist_del(&plink_ctl->peer_blacklist, addr);
+}
+
+int rtw_mesh_peer_blacklist_search(_adapter *adapter, const u8 *addr)
+{
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+
+ return rtw_blacklist_search(&plink_ctl->peer_blacklist, addr);
+}
+
+void rtw_mesh_peer_blacklist_flush(_adapter *adapter)
+{
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+
+ rtw_blacklist_flush(&plink_ctl->peer_blacklist);
+}
+
+void dump_mesh_peer_blacklist(void *sel, _adapter *adapter)
+{
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+
+ dump_blacklist(sel, &plink_ctl->peer_blacklist, "blacklist");
+}
+
+void dump_mesh_peer_blacklist_settings(void *sel, _adapter *adapter)
+{
+ struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;
+
+ RTW_PRINT_SEL(sel, "%-12s %-17s\n"
+ , "conf_timeout", "blacklist_timeout");
+ RTW_PRINT_SEL(sel, "%12u %17u\n"
+ , peer_sel_policy->peer_conf_timeout_ms
+ , peer_sel_policy->peer_blacklist_timeout_ms);
+}
+#endif /* CONFIG_RTW_MESH_PEER_BLACKLIST */
+
+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+u8 rtw_mesh_cto_mgate_required(_adapter *adapter)
+{
+ struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+ struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
+
+ return mcfg->peer_sel_policy.cto_mgate_require
+ && !rtw_bss_is_cto_mgate(&(mlmeext->mlmext_info.network));
+}
+
+u8 rtw_mesh_cto_mgate_network_filter(_adapter *adapter, struct wlan_network *scanned)
+{
+ struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+ struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
+
+ return !rtw_mesh_cto_mgate_required(adapter)
+ || (rtw_bss_is_cto_mgate(&scanned->network)
+ && !rtw_mesh_cto_mgate_blacklist_search(adapter, scanned->network.MacAddress));
+}
+
+int rtw_mesh_cto_mgate_blacklist_add(_adapter *adapter, const u8 *addr)
+{
+ struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+
+ return rtw_blacklist_add(&plink_ctl->cto_mgate_blacklist, addr
+ , mcfg->peer_sel_policy.cto_mgate_blacklist_timeout_ms);
+}
+
+int rtw_mesh_cto_mgate_blacklist_del(_adapter *adapter, const u8 *addr)
+{
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+
+ return rtw_blacklist_del(&plink_ctl->cto_mgate_blacklist, addr);
+}
+
+int rtw_mesh_cto_mgate_blacklist_search(_adapter *adapter, const u8 *addr)
+{
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+
+ return rtw_blacklist_search(&plink_ctl->cto_mgate_blacklist, addr);
+}
+
+void rtw_mesh_cto_mgate_blacklist_flush(_adapter *adapter)
+{
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+
+ rtw_blacklist_flush(&plink_ctl->cto_mgate_blacklist);
+}
+
+void dump_mesh_cto_mgate_blacklist(void *sel, _adapter *adapter)
+{
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+
+ dump_blacklist(sel, &plink_ctl->cto_mgate_blacklist, "blacklist");
+}
+
+void dump_mesh_cto_mgate_blacklist_settings(void *sel, _adapter *adapter)
+{
+ struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;
+
+ RTW_PRINT_SEL(sel, "%-7s %-12s %-17s\n"
+ , "require", "conf_timeout", "blacklist_timeout");
+ RTW_PRINT_SEL(sel, "%7u %12u %17u\n"
+ , peer_sel_policy->cto_mgate_require
+ , peer_sel_policy->cto_mgate_conf_timeout_ms
+ , peer_sel_policy->cto_mgate_blacklist_timeout_ms);
+}
+
+static void rtw_mesh_cto_mgate_blacklist_chk(_adapter *adapter)
+{
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+ _queue *blist = &plink_ctl->cto_mgate_blacklist;
+ _list *list, *head;
+ struct blacklist_ent *ent = NULL;
+ struct wlan_network *scanned = NULL;
+
+ enter_critical_bh(&blist->lock);
+ head = &blist->queue;
+ list = get_next(head);
+ while (rtw_end_of_queue_search(head, list) == _FALSE) {
+ ent = LIST_CONTAINOR(list, struct blacklist_ent, list);
+ list = get_next(list);
+
+ if (rtw_time_after(rtw_get_current_time(), ent->exp_time)) {
+ rtw_list_delete(&ent->list);
+ rtw_mfree(ent, sizeof(struct blacklist_ent));
+ continue;
+ }
+
+ scanned = rtw_find_network(&adapter->mlmepriv.scanned_queue, ent->addr);
+ if (!scanned)
+ continue;
+
+ if (rtw_bss_is_forwarding(&scanned->network)) {
+ rtw_list_delete(&ent->list);
+ rtw_mfree(ent, sizeof(struct blacklist_ent));
+ }
+ }
+
+ exit_critical_bh(&blist->lock);
+}
+#endif /* CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST */
+
+void rtw_chk_candidate_peer_notify(_adapter *adapter, struct wlan_network *scanned)
+{
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+ struct mlme_priv *mlme = &adapter->mlmepriv;
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+ struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+
+ if (IS_CH_WAITING(rfctl) && !IS_UNDER_CAC(rfctl))
+ goto exit;
+
+ if (plink_ctl->num >= RTW_MESH_MAX_PEER_CANDIDATES)
+ goto exit;
+
+ /* wpa_supplicant's auto peer will initiate peering when candidate peer is reported without max_peer_links consideration */
+ if (plink_ctl->num >= mcfg->max_peer_links)
+ goto exit;
+
+ if (rtw_get_passing_time_ms(scanned->last_scanned) >= mcfg->peer_sel_policy.scanr_exp_ms
+ || (mcfg->rssi_threshold && mcfg->rssi_threshold > scanned->network.Rssi)
+ || !rtw_bss_is_candidate_mesh_peer(&mlme->cur_network.network, &scanned->network, 1, 1)
+ #if CONFIG_RTW_MACADDR_ACL
+ || rtw_access_ctrl(adapter, scanned->network.MacAddress) == _FALSE
+ #endif
+ || rtw_mesh_plink_get(adapter, scanned->network.MacAddress)
+ #if CONFIG_RTW_MESH_PEER_BLACKLIST
+ || rtw_mesh_peer_blacklist_search(adapter, scanned->network.MacAddress)
+ #endif
+ #if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+ || !rtw_mesh_cto_mgate_network_filter(adapter, scanned)
+ #endif
+ )
+ goto exit;
+
+#ifdef CONFIG_IOCTL_CFG80211
+ rtw_cfg80211_notify_new_peer_candidate(adapter->rtw_wdev
+ , scanned->network.MacAddress
+ , BSS_EX_TLV_IES(&scanned->network)
+ , BSS_EX_TLV_IES_LEN(&scanned->network)
+ , GFP_ATOMIC
+ );
+#endif
+
+exit:
+ return;
+}
+
+void rtw_mesh_peer_status_chk(_adapter *adapter)
+{
+ struct mlme_priv *mlme = &adapter->mlmepriv;
+ struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+ struct mesh_plink_ent *plink;
+ _list *head, *list;
+ struct sta_info *sta = NULL;
+ struct sta_priv *stapriv = &adapter->stapriv;
+ int stainfo_offset;
+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+ u8 cto_mgate, forwarding, mgate;
+#endif
+ u8 flush;
+ char flush_list[NUM_STA];
+ u8 flush_num = 0;
+ int i;
+
+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+ if (rtw_mesh_cto_mgate_required(adapter)) {
+ /* active scan on operating channel */
+ issue_probereq_ex(adapter, &adapter->mlmepriv.cur_network.network.mesh_id, NULL, 0, 0, 0, 0);
+ }
+#endif
+
+ enter_critical_bh(&(plink_ctl->lock));
+
+ /* check established peers */
+ enter_critical_bh(&stapriv->asoc_list_lock);
+
+ head = &stapriv->asoc_list;
+ list = get_next(head);
+ while (rtw_end_of_queue_search(head, list) == _FALSE) {
+ sta = LIST_CONTAINOR(list, struct sta_info, asoc_list);
+ list = get_next(list);
+
+ if (!sta->plink || !sta->plink->scanned) {
+ rtw_warn_on(1);
+ continue;
+ }
+ plink = sta->plink;
+ flush = 0;
+
+ /* remove unsuitable peer */
+ if (!rtw_bss_is_candidate_mesh_peer(&mlme->cur_network.network, &plink->scanned->network, 1, 0)
+ #if CONFIG_RTW_MACADDR_ACL
+ || rtw_access_ctrl(adapter, plink->addr) == _FALSE
+ #endif
+ ) {
+ flush = 1;
+ goto flush_add;
+ }
+
+ #if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+ cto_mgate = rtw_bss_is_cto_mgate(&(plink->scanned->network));
+ forwarding = rtw_bss_is_forwarding(&(plink->scanned->network));
+ mgate = rtw_mesh_gate_search(minfo->mesh_paths, sta->cmn.mac_addr);
+
+ /* CTO_MGATE required, remove peer without CTO_MGATE */
+ if (rtw_mesh_cto_mgate_required(adapter) && !cto_mgate) {
+ flush = 1;
+ goto flush_add;
+ }
+
+ /* cto_mgate_conf status update */
+ if (IS_CTO_MGATE_CONF_DISABLED(plink)) {
+ if (cto_mgate && !forwarding && !mgate)
+ SET_CTO_MGATE_CONF_END_TIME(plink, mcfg->peer_sel_policy.cto_mgate_conf_timeout_ms);
+ else
+ rtw_mesh_cto_mgate_blacklist_del(adapter, sta->cmn.mac_addr);
+ } else {
+ /* cto_mgate_conf ongoing */
+ if (cto_mgate && !forwarding && !mgate) {
+ if (IS_CTO_MGATE_CONF_TIMEOUT(plink)) {
+ rtw_mesh_cto_mgate_blacklist_add(adapter, sta->cmn.mac_addr);
+
+ /* CTO_MGATE required, remove peering can't achieve CTO_MGATE */
+ if (rtw_mesh_cto_mgate_required(adapter)) {
+ flush = 1;
+ goto flush_add;
+ }
+ }
+ } else {
+ SET_CTO_MGATE_CONF_DISABLED(plink);
+ rtw_mesh_cto_mgate_blacklist_del(adapter, sta->cmn.mac_addr);
+ }
+ }
+ #endif /* CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST */
+
+flush_add:
+ if (flush) {
+ rtw_list_delete(&sta->asoc_list);
+ stapriv->asoc_list_cnt--;
+ STA_SET_MESH_PLINK(sta, NULL);
+
+ stainfo_offset = rtw_stainfo_offset(stapriv, sta);
+ if (stainfo_offset_valid(stainfo_offset))
+ flush_list[flush_num++] = stainfo_offset;
+ else
+ rtw_warn_on(1);
+ }
+ }
+
+ exit_critical_bh(&stapriv->asoc_list_lock);
+
+ /* check non-established peers */
+ for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) {
+ plink = &plink_ctl->ent[i];
+ if (plink->valid != _TRUE || plink->plink_state == RTW_MESH_PLINK_ESTAB)
+ continue;
+
+ /* remove unsuitable peer */
+ if (!rtw_bss_is_candidate_mesh_peer(&mlme->cur_network.network, &plink->scanned->network, 1, 1)
+ #if CONFIG_RTW_MACADDR_ACL
+ || rtw_access_ctrl(adapter, plink->addr) == _FALSE
+ #endif
+ ) {
+ _rtw_mesh_expire_peer_ent(adapter, plink);
+ continue;
+ }
+
+ #if CONFIG_RTW_MESH_PEER_BLACKLIST
+ /* peer confirm check timeout, add to black list */
+ if (IS_PEER_CONF_TIMEOUT(plink)) {
+ rtw_mesh_peer_blacklist_add(adapter, plink->addr);
+ _rtw_mesh_expire_peer_ent(adapter, plink);
+ }
+ #endif
+ }
+
+ exit_critical_bh(&(plink_ctl->lock));
+
+ for (i = 0; i < flush_num; i++) {
+ u8 sta_addr[ETH_ALEN];
+
+ sta = rtw_get_stainfo_by_offset(stapriv, flush_list[i]);
+ _rtw_memcpy(sta_addr, sta->cmn.mac_addr, ETH_ALEN);
+
+ ap_free_sta(adapter, sta, _TRUE, WLAN_REASON_DEAUTH_LEAVING, _FALSE);
+ rtw_mesh_expire_peer(adapter, sta_addr);
+ }
+
+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+ /* loop cto_mgate_blacklist to remove ent according to scan_r */
+ rtw_mesh_cto_mgate_blacklist_chk(adapter);
+#endif
+
+ return;
+}
+
+#if CONFIG_RTW_MESH_OFFCH_CAND
+static u8 rtw_mesh_offch_cto_mgate_required(_adapter *adapter)
+{
+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+ struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+ struct mlme_priv *mlme = &adapter->mlmepriv;
+ _queue *queue = &(mlme->scanned_queue);
+ _list *head, *pos;
+ struct wlan_network *scanned = NULL;
+ u8 ret = 0;
+
+ if (!rtw_mesh_cto_mgate_required(adapter))
+ goto exit;
+
+ enter_critical_bh(&(mlme->scanned_queue.lock));
+
+ head = get_list_head(queue);
+ pos = get_next(head);
+ while (!rtw_end_of_queue_search(head, pos)) {
+ scanned = LIST_CONTAINOR(pos, struct wlan_network, list);
+
+ if (rtw_get_passing_time_ms(scanned->last_scanned) < mcfg->peer_sel_policy.scanr_exp_ms
+ && (!mcfg->rssi_threshold || mcfg->rssi_threshold <= scanned->network.Rssi)
+ #if CONFIG_RTW_MACADDR_ACL
+ && rtw_access_ctrl(adapter, scanned->network.MacAddress) == _TRUE
+ #endif
+ && rtw_bss_is_candidate_mesh_peer(&mlme->cur_network.network, &scanned->network, 1, 1)
+ && rtw_bss_is_cto_mgate(&scanned->network)
+ #if CONFIG_RTW_MESH_PEER_BLACKLIST
+ && !rtw_mesh_peer_blacklist_search(adapter, scanned->network.MacAddress)
+ #endif
+ && !rtw_mesh_cto_mgate_blacklist_search(adapter, scanned->network.MacAddress)
+ )
+ break;
+
+ pos = get_next(pos);
+ }
+
+ if (rtw_end_of_queue_search(head, pos))
+ ret = 1;
+
+ exit_critical_bh(&(mlme->scanned_queue.lock));
+
+exit:
+ return ret;
+#else
+ return 0;
+#endif /* CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST */
+}
+
+u8 rtw_mesh_offch_candidate_accepted(_adapter *adapter)
+{
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+ u8 ret;
+
+ ret = MLME_IS_MESH(adapter)
+ && check_fwstate(&adapter->mlmepriv, WIFI_ASOC_STATE) == _TRUE
+ && (!plink_ctl->num || rtw_mesh_offch_cto_mgate_required(adapter))
+ ;
+
+#ifdef CONFIG_CONCURRENT_MODE
+ if (ret) {
+ struct mi_state mstate_no_self;
+
+ rtw_mi_status_no_self(adapter, &mstate_no_self);
+ if (MSTATE_STA_LD_NUM(&mstate_no_self) || MSTATE_AP_LD_NUM(&mstate_no_self)
+ || MSTATE_ADHOC_LD_NUM(&mstate_no_self) || MSTATE_MESH_LD_NUM(&mstate_no_self))
+ ret = 0;
+ }
+#endif
+
+ return ret;
+}
+
+/*
+ * this function is called under off channel candidate is required
+ * the channel with maximum candidate count is selected
+*/
+u8 rtw_mesh_select_operating_ch(_adapter *adapter)
+{
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+ struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+ struct mlme_priv *mlme = &adapter->mlmepriv;
+ _queue *queue = &(mlme->scanned_queue);
+ _list *head, *pos;
+ _irqL irqL;
+ struct wlan_network *scanned = NULL;
+ int i;
+ u8 max_cand_ch = 0;
+ u8 max_cand_cnt = 0;
+
+ for (i = 0; i < rfctl->max_chan_nums; i++)
+ rfctl->channel_set[i].mesh_candidate_cnt = 0;
+
+ _enter_critical_bh(&(mlme->scanned_queue.lock), &irqL);
+
+ head = get_list_head(queue);
+ pos = get_next(head);
+ while (!rtw_end_of_queue_search(head, pos)) {
+ scanned = LIST_CONTAINOR(pos, struct wlan_network, list);
+ pos = get_next(pos);
+
+ if (rtw_get_passing_time_ms(scanned->last_scanned) < mcfg->peer_sel_policy.scanr_exp_ms
+ && (!mcfg->rssi_threshold || mcfg->rssi_threshold <= scanned->network.Rssi)
+ #if CONFIG_RTW_MACADDR_ACL
+ && rtw_access_ctrl(adapter, scanned->network.MacAddress) == _TRUE
+ #endif
+ && rtw_bss_is_candidate_mesh_peer(&mlme->cur_network.network, &scanned->network, 0, 1)
+ #if CONFIG_RTW_MESH_PEER_BLACKLIST
+ && !rtw_mesh_peer_blacklist_search(adapter, scanned->network.MacAddress)
+ #endif
+ #if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+ && rtw_mesh_cto_mgate_network_filter(adapter, scanned)
+ #endif
+ ) {
+ int ch_set_idx = rtw_chset_search_ch(rfctl->channel_set, scanned->network.Configuration.DSConfig);
+
+ if (ch_set_idx >= 0
+ && !CH_IS_NON_OCP(&rfctl->channel_set[ch_set_idx])
+ ) {
+ rfctl->channel_set[ch_set_idx].mesh_candidate_cnt++;
+ if (max_cand_cnt < rfctl->channel_set[ch_set_idx].mesh_candidate_cnt) {
+ max_cand_cnt = rfctl->channel_set[ch_set_idx].mesh_candidate_cnt;
+ max_cand_ch = rfctl->channel_set[ch_set_idx].ChannelNum;
+ }
+ }
+ }
+ }
+
+ _exit_critical_bh(&(mlme->scanned_queue.lock), &irqL);
+
+ return max_cand_ch;
+}
+#endif /* CONFIG_RTW_MESH_OFFCH_CAND */
+
+void dump_mesh_peer_sel_policy(void *sel, _adapter *adapter)
+{
+ struct mesh_peer_sel_policy *peer_sel_policy = &adapter->mesh_cfg.peer_sel_policy;
+
+#if CONFIG_RTW_MESH_OFFCH_CAND
+#define OFFCH_CAND_TITLE_FMT " %-17s"
+#define OFFCH_CAND_VALUE_FMT " %17u"
+#define OFFCH_CAND_TITLE_ARG , "offch_find_int_ms"
+#define OFFCH_CAND_VALUE_ARG , peer_sel_policy->offch_find_int_ms
+#else
+#define OFFCH_CAND_TITLE_FMT ""
+#define OFFCH_CAND_VALUE_FMT ""
+#define OFFCH_CAND_TITLE_ARG
+#define OFFCH_CAND_VALUE_ARG
+#endif
+
+ RTW_PRINT_SEL(sel,
+ "%-12s"
+ OFFCH_CAND_TITLE_FMT
+ "\n"
+ , "scanr_exp_ms"
+ OFFCH_CAND_TITLE_ARG
+ );
+ RTW_PRINT_SEL(sel,
+ "%12u"
+ OFFCH_CAND_VALUE_FMT
+ "\n"
+ , peer_sel_policy->scanr_exp_ms
+ OFFCH_CAND_VALUE_ARG
+ );
+}
+
+void dump_mesh_networks(void *sel, _adapter *adapter)
+{
+ struct mlme_priv *mlme = &(adapter->mlmepriv);
+ _queue *queue = &(mlme->scanned_queue);
+ struct wlan_network *network;
+ _list *list, *head;
+ u8 same_mbss;
+ u8 candidate;
+ struct mesh_plink_ent *plink;
+ u8 blocked;
+ u8 established;
+ s32 age_ms;
+ u8 *mesh_conf_ie;
+ sint mesh_conf_ie_len;
+ struct wlan_network **mesh_networks;
+ u8 mesh_network_cnt = 0;
+ int i;
+
+ mesh_networks = rtw_zvmalloc(MAX_BSS_CNT * sizeof(struct wlan_network *));
+ if (!mesh_networks)
+ return;
+
+ enter_critical_bh(&queue->lock);
+ head = get_list_head(queue);
+ list = get_next(head);
+
+ while (rtw_end_of_queue_search(head, list) == _FALSE) {
+ network = LIST_CONTAINOR(list, struct wlan_network, list);
+ list = get_next(list);
+
+ if (network->network.InfrastructureMode != Ndis802_11_mesh)
+ continue;
+
+ mesh_conf_ie = rtw_get_ie(BSS_EX_TLV_IES(&network->network), WLAN_EID_MESH_CONFIG
+ , &mesh_conf_ie_len, BSS_EX_TLV_IES_LEN(&network->network));
+ if (!mesh_conf_ie || mesh_conf_ie_len != 7)
+ continue;
+
+ mesh_networks[mesh_network_cnt++] = network;
+ }
+
+ exit_critical_bh(&queue->lock);
+
+ RTW_PRINT_SEL(sel, " %-17s %-3s %-4s %-5s %-32s %-3s %-3s %-3s\n"
+ , "bssid", "ch", "rssi", "age", "mesh_id", "nop", "fwd", "cto");
+
+
+ for (i = 0; i < mesh_network_cnt; i++) {
+ network = mesh_networks[i];
+
+ if (network->network.InfrastructureMode != Ndis802_11_mesh)
+ continue;
+
+ mesh_conf_ie = rtw_get_ie(BSS_EX_TLV_IES(&network->network), WLAN_EID_MESH_CONFIG
+ , &mesh_conf_ie_len, BSS_EX_TLV_IES_LEN(&network->network));
+ if (!mesh_conf_ie || mesh_conf_ie_len != 7)
+ continue;
+
+ age_ms = rtw_get_passing_time_ms(network->last_scanned);
+ same_mbss = 0;
+ candidate = 0;
+ plink = NULL;
+ blocked = 0;
+ established = 0;
+
+ if (MLME_IS_MESH(adapter) && MLME_IS_ASOC(adapter)) {
+ plink = rtw_mesh_plink_get(adapter, network->network.MacAddress);
+ if (plink && plink->plink_state == RTW_MESH_PLINK_ESTAB)
+ established = 1;
+ else if (plink && plink->plink_state == RTW_MESH_PLINK_BLOCKED)
+ blocked = 1;
+ else if (plink)
+ ;
+ else if (rtw_bss_is_candidate_mesh_peer(&mlme->cur_network.network, &network->network, 0, 1))
+ candidate = 1;
+ else if (rtw_bss_is_same_mbss(&mlme->cur_network.network, &network->network))
+ same_mbss = 1;
+ }
+
+ RTW_PRINT_SEL(sel, "%c "MAC_FMT" %3d %4ld %5d %-32s %c%2u %3u %c%c \n"
+ , established ? 'E' : (blocked ? 'B' : (plink ? 'N' : (candidate ? 'C' : (same_mbss ? 'S' : ' '))))
+ , MAC_ARG(network->network.MacAddress)
+ , network->network.Configuration.DSConfig
+ , network->network.Rssi
+ , age_ms < 99999 ? age_ms : 99999
+ , network->network.mesh_id.Ssid
+ , GET_MESH_CONF_ELE_ACCEPT_PEERINGS(mesh_conf_ie + 2) ? '+' : ' '
+ , GET_MESH_CONF_ELE_NUM_OF_PEERINGS(mesh_conf_ie + 2)
+ , GET_MESH_CONF_ELE_FORWARDING(mesh_conf_ie + 2)
+ , GET_MESH_CONF_ELE_CTO_MGATE(mesh_conf_ie + 2) ? 'G' : ' '
+ , GET_MESH_CONF_ELE_CTO_AS(mesh_conf_ie + 2) ? 'A' : ' '
+ );
+ }
+
+ rtw_vmfree(mesh_networks, MAX_BSS_CNT * sizeof(struct wlan_network *));
+}
+
+int rtw_sae_check_frames(_adapter *adapter, const u8 *buf, u32 len, u8 tx)
+{
+ const u8 *frame_body = buf + sizeof(struct rtw_ieee80211_hdr_3addr);
+ u16 alg;
+ u16 seq;
+ u16 status;
+ int ret = 0;
+
+ alg = RTW_GET_LE16(frame_body);
+ if (alg != 3)
+ goto exit;
+
+ seq = RTW_GET_LE16(frame_body + 2);
+ status = RTW_GET_LE16(frame_body + 4);
+
+ RTW_INFO("RTW_%s:AUTH alg:0x%04x, seq:0x%04x, status:0x%04x\n"
+ , (tx == _TRUE) ? "Tx" : "Rx", alg, seq, status);
+
+ ret = 1;
+
+#if CONFIG_RTW_MESH_PEER_BLACKLIST
+ if (tx && seq == 1)
+ rtw_mesh_plink_set_peer_conf_timeout(adapter, GetAddr1Ptr(buf));
+#endif
+
+exit:
+ return ret;
+}
+
+#if CONFIG_RTW_MPM_TX_IES_SYNC_BSS
+#ifdef CONFIG_RTW_MESH_AEK
+static int rtw_mpm_ampe_dec(_adapter *adapter, struct mesh_plink_ent *plink
+ , u8 *fhead, size_t flen, u8* fbody, u8 *mic_ie, u8 *ampe_buf)
+{
+ int ret = _FAIL, verify_ret;
+ const u8 *aad[] = {adapter_mac_addr(adapter), plink->addr, fbody};
+ const size_t aad_len[] = {ETH_ALEN, ETH_ALEN, mic_ie - fbody};
+ u8 *iv_crypt;
+ size_t iv_crypt_len = flen - (mic_ie + 2 - fhead);
+
+ iv_crypt = rtw_malloc(iv_crypt_len);
+ if (!iv_crypt)
+ goto exit;
+
+ _rtw_memcpy(iv_crypt, mic_ie + 2, iv_crypt_len);
+
+ verify_ret = aes_siv_decrypt(plink->aek, iv_crypt, iv_crypt_len
+ , 3, aad, aad_len, ampe_buf);
+
+ rtw_mfree(iv_crypt, iv_crypt_len);
+
+ if (verify_ret) {
+ RTW_WARN("verify error, aek_valid=%u\n", plink->aek_valid);
+ goto exit;
+ } else if (*ampe_buf != WLAN_EID_AMPE) {
+ RTW_WARN("plaintext is not AMPE IE\n");
+ goto exit;
+ } else if (AES_BLOCK_SIZE + 2 + *(ampe_buf + 1) > iv_crypt_len) {
+ RTW_WARN("plaintext AMPE IE length is not valid\n");
+ goto exit;
+ }
+
+ ret = _SUCCESS;
+
+exit:
+ return ret;
+}
+
+static int rtw_mpm_ampe_enc(_adapter *adapter, struct mesh_plink_ent *plink
+ , u8* fbody, u8 *mic_ie, u8 *ampe_buf, bool inverse)
+{
+ int ret = _FAIL, protect_ret;
+ const u8 *aad[3];
+ const size_t aad_len[3] = {ETH_ALEN, ETH_ALEN, mic_ie - fbody};
+ u8 *ampe_ie;
+ size_t ampe_ie_len = *(ampe_buf + 1) + 2; /* including id & len */
+
+ if (inverse) {
+ aad[0] = plink->addr;
+ aad[1] = adapter_mac_addr(adapter);
+ } else {
+ aad[0] = adapter_mac_addr(adapter);
+ aad[1] = plink->addr;
+ }
+ aad[2] = fbody;
+
+ ampe_ie = rtw_malloc(ampe_ie_len);
+ if (!ampe_ie)
+ goto exit;
+
+ _rtw_memcpy(ampe_ie, ampe_buf, ampe_ie_len);
+
+ protect_ret = aes_siv_encrypt(plink->aek, ampe_ie, ampe_ie_len
+ , 3, aad, aad_len, mic_ie + 2);
+
+ rtw_mfree(ampe_ie, ampe_ie_len);
+
+ if (protect_ret) {
+ RTW_WARN("protect error, aek_valid=%u\n", plink->aek_valid);
+ goto exit;
+ }
+
+ ret = _SUCCESS;
+
+exit:
+ return ret;
+}
+#endif /* CONFIG_RTW_MESH_AEK */
+
+static int rtw_mpm_tx_ies_sync_bss(_adapter *adapter, struct mesh_plink_ent *plink
+ , u8 *fhead, size_t flen, u8* fbody, u8 tlv_ies_offset, u8 *mpm_ie, u8 *mic_ie
+ , u8 **nbuf, size_t *nlen)
+{
+ int ret = _FAIL;
+ struct mlme_priv *mlme = &(adapter->mlmepriv);
+ struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
+ struct mlme_ext_info *mlmeinfo = &(mlmeext->mlmext_info);
+ WLAN_BSSID_EX *network = &(mlmeinfo->network);
+ uint left;
+ u8 *pos;
+
+ uint mpm_ielen = *(mpm_ie + 1);
+ u8 *fpos;
+ u8 *new_buf = NULL;
+ size_t new_len = 0;
+
+ u8 *new_fhead;
+ size_t new_flen;
+ u8 *new_fbody;
+ u8 *new_mic_ie;
+
+#ifdef CONFIG_RTW_MESH_AEK
+ u8 *ampe_buf = NULL;
+ size_t ampe_buf_len = 0;
+
+ /* decode */
+ if (mic_ie) {
+ ampe_buf_len = flen - (mic_ie + 2 + AES_BLOCK_SIZE - fhead);
+ ampe_buf = rtw_malloc(ampe_buf_len);
+ if (!ampe_buf)
+ goto exit;
+
+ if (rtw_mpm_ampe_dec(adapter, plink, fhead, flen, fbody, mic_ie, ampe_buf) != _SUCCESS)
+ goto exit;
+
+ if (*(ampe_buf + 1) >= 68) {
+ _rtw_memcpy(plink->sel_pcs, ampe_buf + 2, 4);
+ _rtw_memcpy(plink->l_nonce, ampe_buf + 6, 32);
+ _rtw_memcpy(plink->p_nonce, ampe_buf + 38, 32);
+ }
+ }
+#endif
+
+ /* count for new frame length */
+ new_len = sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset;
+ left = BSS_EX_TLV_IES_LEN(network);
+ pos = BSS_EX_TLV_IES(network);
+ while (left >= 2) {
+ u8 id, elen;
+
+ id = *pos++;
+ elen = *pos++;
+ left -= 2;
+
+ if (elen > left)
+ break;
+
+ switch (id) {
+ case WLAN_EID_SSID:
+ case WLAN_EID_DS_PARAMS:
+ case WLAN_EID_TIM:
+ break;
+ default:
+ new_len += 2 + elen;
+ }
+
+ left -= elen;
+ pos += elen;
+ }
+ new_len += mpm_ielen + 2;
+ if (mic_ie)
+ new_len += AES_BLOCK_SIZE + 2 + ampe_buf_len;
+
+ /* alloc new frame */
+ new_buf = rtw_malloc(new_len);
+ if (!new_buf) {
+ rtw_warn_on(1);
+ goto exit;
+ }
+
+ /* build new frame */
+ _rtw_memcpy(new_buf, fhead, sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset);
+ new_fhead = new_buf;
+ new_flen = new_len;
+ new_fbody = new_fhead + sizeof(struct rtw_ieee80211_hdr_3addr);
+
+ fpos = new_fbody + tlv_ies_offset;
+ left = BSS_EX_TLV_IES_LEN(network);
+ pos = BSS_EX_TLV_IES(network);
+ while (left >= 2) {
+ u8 id, elen;
+
+ id = *pos++;
+ elen = *pos++;
+ left -= 2;
+
+ if (elen > left)
+ break;
+
+ switch (id) {
+ case WLAN_EID_SSID:
+ case WLAN_EID_DS_PARAMS:
+ case WLAN_EID_TIM:
+ break;
+ default:
+ fpos = rtw_set_ie(fpos, id, elen, pos, NULL);
+ if (id == WLAN_EID_MESH_CONFIG)
+ fpos = rtw_set_ie(fpos, WLAN_EID_MPM, mpm_ielen, mpm_ie + 2, NULL);
+ }
+
+ left -= elen;
+ pos += elen;
+ }
+ if (mic_ie) {
+ new_mic_ie = fpos;
+ *fpos++ = WLAN_EID_MIC;
+ *fpos++ = AES_BLOCK_SIZE;
+ }
+
+#ifdef CONFIG_RTW_MESH_AEK
+ /* encode */
+ if (mic_ie) {
+ int enc_ret = rtw_mpm_ampe_enc(adapter, plink, new_fbody, new_mic_ie, ampe_buf, 0);
+ if (enc_ret != _SUCCESS)
+ goto exit;
+ }
+#endif
+
+ *nlen = new_len;
+ *nbuf = new_buf;
+
+ ret = _SUCCESS;
+
+exit:
+ if (ret != _SUCCESS && new_buf)
+ rtw_mfree(new_buf, new_len);
+
+#ifdef CONFIG_RTW_MESH_AEK
+ if (ampe_buf)
+ rtw_mfree(ampe_buf, ampe_buf_len);
+#endif
+
+ return ret;
+}
+#endif /* CONFIG_RTW_MPM_TX_IES_SYNC_BSS */
+
+struct mpm_frame_info {
+ u8 *aid;
+ u16 aid_v;
+ u8 *pid;
+ u16 pid_v;
+ u8 *llid;
+ u16 llid_v;
+ u8 *plid;
+ u16 plid_v;
+ u8 *reason;
+ u16 reason_v;
+ u8 *chosen_pmk;
+};
+
+/*
+* pid:0x0000 llid:0x0000 chosen_pmk:0x00000000000000000000000000000000
+* aid:0x0000 pid:0x0000 llid:0x0000 plid:0x0000 chosen_pmk:0x00000000000000000000000000000000
+* pid:0x0000 llid:0x0000 plid:0x0000 reason:0x0000 chosen_pmk:0x00000000000000000000000000000000
+*/
+#define MPM_LOG_BUF_LEN 96 /* this length is limited for legal combination */
+static void rtw_mpm_info_msg(struct mpm_frame_info *mpm_info, u8 *mpm_log_buf)
+{
+ int cnt = 0;
+
+ if (mpm_info->aid) {
+ cnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, "aid:0x%04x ", mpm_info->aid_v);
+ if (cnt >= MPM_LOG_BUF_LEN - 1)
+ goto exit;
+ }
+ if (mpm_info->pid) {
+ cnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, "pid:0x%04x ", mpm_info->pid_v);
+ if (cnt >= MPM_LOG_BUF_LEN - 1)
+ goto exit;
+ }
+ if (mpm_info->llid) {
+ cnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, "llid:0x%04x ", mpm_info->llid_v);
+ if (cnt >= MPM_LOG_BUF_LEN - 1)
+ goto exit;
+ }
+ if (mpm_info->plid) {
+ cnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, "plid:0x%04x ", mpm_info->plid_v);
+ if (cnt >= MPM_LOG_BUF_LEN - 1)
+ goto exit;
+ }
+ if (mpm_info->reason) {
+ cnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, "reason:0x%04x ", mpm_info->reason_v);
+ if (cnt >= MPM_LOG_BUF_LEN - 1)
+ goto exit;
+ }
+ if (mpm_info->chosen_pmk) {
+ cnt += snprintf(mpm_log_buf + cnt, MPM_LOG_BUF_LEN - cnt - 1, "chosen_pmk:0x"KEY_FMT, KEY_ARG(mpm_info->chosen_pmk));
+ if (cnt >= MPM_LOG_BUF_LEN - 1)
+ goto exit;
+ }
+
+exit:
+ return;
+}
+
+static int rtw_mpm_check_frames(_adapter *adapter, u8 action, const u8 **buf, size_t *len, u8 tx)
+{
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+ struct mesh_plink_ent *plink = NULL;
+ u8 *nbuf = NULL;
+ size_t nlen = 0;
+ u8 *fhead = (u8 *)*buf;
+ size_t flen = *len;
+ u8 *peer_addr = tx ? GetAddr1Ptr(fhead) : get_addr2_ptr(fhead);
+ u8 *frame_body = fhead + sizeof(struct rtw_ieee80211_hdr_3addr);
+ struct mpm_frame_info mpm_info;
+ u8 tlv_ies_offset;
+ u8 *mpm_ie = NULL;
+ uint mpm_ielen = 0;
+ u8 *mic_ie = NULL;
+ uint mic_ielen = 0;
+ int ret = 0;
+ u8 mpm_log_buf[MPM_LOG_BUF_LEN] = {0};
+
+ if (action == RTW_ACT_SELF_PROTECTED_MESH_OPEN)
+ tlv_ies_offset = 4;
+ else if (action == RTW_ACT_SELF_PROTECTED_MESH_CONF)
+ tlv_ies_offset = 6;
+ else if (action == RTW_ACT_SELF_PROTECTED_MESH_CLOSE)
+ tlv_ies_offset = 2;
+ else {
+ rtw_warn_on(1);
+ goto exit;
+ }
+
+ plink = rtw_mesh_plink_get(adapter, peer_addr);
+ if (!plink && (tx == _TRUE || action == RTW_ACT_SELF_PROTECTED_MESH_CONF)) {
+ /* warning message if no plink when: 1.TX all MPM or 2.RX CONF */
+ RTW_WARN("RTW_%s:%s without plink of "MAC_FMT"\n"
+ , (tx == _TRUE) ? "Tx" : "Rx", action_self_protected_str(action), MAC_ARG(peer_addr));
+ goto exit;
+ }
+
+ _rtw_memset(&mpm_info, 0, sizeof(struct mpm_frame_info));
+
+ if (action == RTW_ACT_SELF_PROTECTED_MESH_CONF) {
+ mpm_info.aid = (u8 *)frame_body + 4;
+ mpm_info.aid_v = RTW_GET_LE16(mpm_info.aid);
+ }
+
+ mpm_ie = rtw_get_ie(fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset
+ , WLAN_EID_MPM, &mpm_ielen
+ , flen - sizeof(struct rtw_ieee80211_hdr_3addr) - tlv_ies_offset);
+ if (!mpm_ie || mpm_ielen < 2 + 2)
+ goto exit;
+
+ mpm_info.pid = mpm_ie + 2;
+ mpm_info.pid_v = RTW_GET_LE16(mpm_info.pid);
+ mpm_info.llid = mpm_info.pid + 2;
+ mpm_info.llid_v = RTW_GET_LE16(mpm_info.llid);
+
+ switch (action) {
+ case RTW_ACT_SELF_PROTECTED_MESH_OPEN:
+ /* pid:2, llid:2, (chosen_pmk:16) */
+ if (mpm_info.pid_v == 0 && mpm_ielen == 4)
+ ;
+ else if (mpm_info.pid_v == 1 && mpm_ielen == 20)
+ mpm_info.chosen_pmk = mpm_info.llid + 2;
+ else
+ goto exit;
+ break;
+ case RTW_ACT_SELF_PROTECTED_MESH_CONF:
+ /* pid:2, llid:2, plid:2, (chosen_pmk:16) */
+ mpm_info.plid = mpm_info.llid + 2;
+ mpm_info.plid_v = RTW_GET_LE16(mpm_info.plid);
+ if (mpm_info.pid_v == 0 && mpm_ielen == 6)
+ ;
+ else if (mpm_info.pid_v == 1 && mpm_ielen == 22)
+ mpm_info.chosen_pmk = mpm_info.plid + 2;
+ else
+ goto exit;
+ break;
+ case RTW_ACT_SELF_PROTECTED_MESH_CLOSE:
+ /* pid:2, llid:2, (plid:2), reason:2, (chosen_pmk:16) */
+ if (mpm_info.pid_v == 0 && mpm_ielen == 6) {
+ /* MPM, without plid */
+ mpm_info.reason = mpm_info.llid + 2;
+ mpm_info.reason_v = RTW_GET_LE16(mpm_info.reason);
+ } else if (mpm_info.pid_v == 0 && mpm_ielen == 8) {
+ /* MPM, with plid */
+ mpm_info.plid = mpm_info.llid + 2;
+ mpm_info.plid_v = RTW_GET_LE16(mpm_info.plid);
+ mpm_info.reason = mpm_info.plid + 2;
+ mpm_info.reason_v = RTW_GET_LE16(mpm_info.reason);
+ } else if (mpm_info.pid_v == 1 && mpm_ielen == 22) {
+ /* AMPE, without plid */
+ mpm_info.reason = mpm_info.llid + 2;
+ mpm_info.reason_v = RTW_GET_LE16(mpm_info.reason);
+ mpm_info.chosen_pmk = mpm_info.reason + 2;
+ } else if (mpm_info.pid_v == 1 && mpm_ielen == 24) {
+ /* AMPE, with plid */
+ mpm_info.plid = mpm_info.llid + 2;
+ mpm_info.plid_v = RTW_GET_LE16(mpm_info.plid);
+ mpm_info.reason = mpm_info.plid + 2;
+ mpm_info.reason_v = RTW_GET_LE16(mpm_info.reason);
+ mpm_info.chosen_pmk = mpm_info.reason + 2;
+ } else
+ goto exit;
+ break;
+ };
+
+ if (mpm_info.pid_v == 1) {
+ mic_ie = rtw_get_ie(fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset
+ , WLAN_EID_MIC, &mic_ielen
+ , flen - sizeof(struct rtw_ieee80211_hdr_3addr) - tlv_ies_offset);
+ if (!mic_ie || mic_ielen != AES_BLOCK_SIZE)
+ goto exit;
+ }
+
+#if CONFIG_RTW_MPM_TX_IES_SYNC_BSS
+ if ((action == RTW_ACT_SELF_PROTECTED_MESH_OPEN || action == RTW_ACT_SELF_PROTECTED_MESH_CONF)
+ && tx == _TRUE
+ ) {
+#define DBG_RTW_MPM_TX_IES_SYNC_BSS 0
+
+ if (mpm_info.pid_v == 1 && (!plink || !MESH_PLINK_AEK_VALID(plink))) {
+ RTW_WARN("AEK not ready, IEs can't sync with BSS\n");
+ goto bypass_sync_bss;
+ }
+
+ if (DBG_RTW_MPM_TX_IES_SYNC_BSS) {
+ RTW_INFO(FUNC_ADPT_FMT" before:\n", FUNC_ADPT_ARG(adapter));
+ dump_ies(RTW_DBGDUMP
+ , fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset
+ , flen - sizeof(struct rtw_ieee80211_hdr_3addr) - tlv_ies_offset);
+ }
+
+ rtw_mpm_tx_ies_sync_bss(adapter, plink
+ , fhead, flen, frame_body, tlv_ies_offset, mpm_ie, mic_ie
+ , &nbuf, &nlen);
+ if (!nbuf)
+ goto exit;
+
+ /* update pointer & len for new frame */
+ fhead = nbuf;
+ flen = nlen;
+ frame_body = fhead + sizeof(struct rtw_ieee80211_hdr_3addr);
+ if (mpm_info.pid_v == 1) {
+ mic_ie = rtw_get_ie(fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset
+ , WLAN_EID_MIC, &mic_ielen
+ , flen - sizeof(struct rtw_ieee80211_hdr_3addr) - tlv_ies_offset);
+ }
+
+ if (DBG_RTW_MPM_TX_IES_SYNC_BSS) {
+ RTW_INFO(FUNC_ADPT_FMT" after:\n", FUNC_ADPT_ARG(adapter));
+ dump_ies(RTW_DBGDUMP
+ , fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + tlv_ies_offset
+ , flen - sizeof(struct rtw_ieee80211_hdr_3addr) - tlv_ies_offset);
+ }
+ }
+bypass_sync_bss:
+#endif /* CONFIG_RTW_MPM_TX_IES_SYNC_BSS */
+
+ if (!plink)
+ goto mpm_log;
+
+#if CONFIG_RTW_MESH_PEER_BLACKLIST
+ if (action == RTW_ACT_SELF_PROTECTED_MESH_OPEN) {
+ if (tx)
+ rtw_mesh_plink_set_peer_conf_timeout(adapter, peer_addr);
+
+ } else
+#endif
+ if (action == RTW_ACT_SELF_PROTECTED_MESH_CONF) {
+ _irqL irqL;
+ u8 *ies = NULL;
+ u16 ies_len = 0;
+
+ _enter_critical_bh(&(plink_ctl->lock), &irqL);
+
+ plink = _rtw_mesh_plink_get(adapter, peer_addr);
+ if (!plink)
+ goto release_plink_ctl;
+
+ if (tx == _FALSE) {
+ ies = plink->rx_conf_ies;
+ ies_len = plink->rx_conf_ies_len;
+ plink->rx_conf_ies = NULL;
+ plink->rx_conf_ies_len = 0;
+
+ plink->llid = mpm_info.plid_v;
+ plink->plid = mpm_info.llid_v;
+ plink->peer_aid = mpm_info.aid_v;
+ if (mpm_info.pid_v == 1)
+ _rtw_memcpy(plink->chosen_pmk, mpm_info.chosen_pmk, 16);
+ }
+ #ifdef CONFIG_RTW_MESH_DRIVER_AID
+ else {
+ ies = plink->tx_conf_ies;
+ ies_len = plink->tx_conf_ies_len;
+ plink->tx_conf_ies = NULL;
+ plink->tx_conf_ies_len = 0;
+ }
+ #endif
+
+ if (ies && ies_len)
+ rtw_mfree(ies, ies_len);
+
+ #ifndef CONFIG_RTW_MESH_DRIVER_AID
+ if (tx == _TRUE)
+ goto release_plink_ctl; /* no need to copy tx conf ies */
+ #endif
+
+ /* copy mesh confirm IEs */
+ if (mpm_info.pid_v == 1) /* not include MIC & encrypted AMPE */
+ ies_len = (mic_ie - fhead) - sizeof(struct rtw_ieee80211_hdr_3addr) - 2;
+ else
+ ies_len = flen - sizeof(struct rtw_ieee80211_hdr_3addr) - 2;
+
+ ies = rtw_zmalloc(ies_len);
+ if (ies) {
+ _rtw_memcpy(ies, fhead + sizeof(struct rtw_ieee80211_hdr_3addr) + 2, ies_len);
+ if (tx == _FALSE) {
+ plink->rx_conf_ies = ies;
+ plink->rx_conf_ies_len = ies_len;
+ }
+ #ifdef CONFIG_RTW_MESH_DRIVER_AID
+ else {
+ plink->tx_conf_ies = ies;
+ plink->tx_conf_ies_len = ies_len;
+ }
+ #endif
+ }
+
+release_plink_ctl:
+ _exit_critical_bh(&(plink_ctl->lock), &irqL);
+ }
+
+mpm_log:
+ rtw_mpm_info_msg(&mpm_info, mpm_log_buf);
+ RTW_INFO("RTW_%s:%s %s\n"
+ , (tx == _TRUE) ? "Tx" : "Rx"
+ , action_self_protected_str(action)
+ , mpm_log_buf
+ );
+
+ ret = 1;
+
+exit:
+ if (nbuf) {
+ if (ret == 1) {
+ *buf = nbuf;
+ *len = nlen;
+ } else
+ rtw_mfree(nbuf, nlen);
+ }
+
+ return ret;
+}
+
+static int rtw_mesh_check_frames(_adapter *adapter, const u8 **buf, size_t *len, u8 tx)
+{
+ int is_mesh_frame = -1;
+ const u8 *frame_body;
+ u8 category, action;
+
+ frame_body = *buf + sizeof(struct rtw_ieee80211_hdr_3addr);
+ category = frame_body[0];
+
+ if (category == RTW_WLAN_CATEGORY_SELF_PROTECTED) {
+ action = frame_body[1];
+ switch (action) {
+ case RTW_ACT_SELF_PROTECTED_MESH_OPEN:
+ case RTW_ACT_SELF_PROTECTED_MESH_CONF:
+ case RTW_ACT_SELF_PROTECTED_MESH_CLOSE:
+ rtw_mpm_check_frames(adapter, action, buf, len, tx);
+ is_mesh_frame = action;
+ break;
+ case RTW_ACT_SELF_PROTECTED_MESH_GK_INFORM:
+ case RTW_ACT_SELF_PROTECTED_MESH_GK_ACK:
+ RTW_INFO("RTW_%s:%s\n", (tx == _TRUE) ? "Tx" : "Rx", action_self_protected_str(action));
+ is_mesh_frame = action;
+ break;
+ default:
+ break;
+ };
+ }
+
+exit:
+ return is_mesh_frame;
+}
+
+int rtw_mesh_check_frames_tx(_adapter *adapter, const u8 **buf, size_t *len)
+{
+ return rtw_mesh_check_frames(adapter, buf, len, _TRUE);
+}
+
+int rtw_mesh_check_frames_rx(_adapter *adapter, const u8 *buf, size_t len)
+{
+ return rtw_mesh_check_frames(adapter, &buf, &len, _FALSE);
+}
+
+unsigned int on_action_self_protected(_adapter *adapter, union recv_frame *rframe)
+{
+ unsigned int ret = _FAIL;
+ struct sta_info *sta = NULL;
+ u8 *pframe = rframe->u.hdr.rx_data;
+ uint frame_len = rframe->u.hdr.len;
+ u8 *frame_body = (u8 *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
+ u8 category;
+ u8 action;
+
+ /* check RA matches or not */
+ if (!_rtw_memcmp(adapter_mac_addr(adapter), GetAddr1Ptr(pframe), ETH_ALEN))
+ goto exit;
+
+ category = frame_body[0];
+ if (category != RTW_WLAN_CATEGORY_SELF_PROTECTED)
+ goto exit;
+
+ action = frame_body[1];
+ switch (action) {
+ case RTW_ACT_SELF_PROTECTED_MESH_OPEN:
+ case RTW_ACT_SELF_PROTECTED_MESH_CONF:
+ case RTW_ACT_SELF_PROTECTED_MESH_CLOSE:
+ case RTW_ACT_SELF_PROTECTED_MESH_GK_INFORM:
+ case RTW_ACT_SELF_PROTECTED_MESH_GK_ACK:
+ if (!(MLME_IS_MESH(adapter) && MLME_IS_ASOC(adapter)))
+ goto exit;
+#ifdef CONFIG_IOCTL_CFG80211
+ #if CONFIG_RTW_MACADDR_ACL
+ if (rtw_access_ctrl(adapter, get_addr2_ptr(pframe)) == _FALSE)
+ goto exit;
+ #endif
+ #if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+ if (rtw_mesh_cto_mgate_required(adapter)
+ /* only peer being added (checked by notify conditions) is allowed */
+ && !rtw_mesh_plink_get(adapter, get_addr2_ptr(pframe)))
+ goto exit;
+ #endif
+ rtw_cfg80211_rx_action(adapter, rframe, NULL);
+ ret = _SUCCESS;
+#endif /* CONFIG_IOCTL_CFG80211 */
+ break;
+ default:
+ break;
+ }
+
+exit:
+ return ret;
+}
+
+const u8 ae_to_mesh_ctrl_len[] = {
+ 6,
+ 12, /* MESH_FLAGS_AE_A4 */
+ 18, /* MESH_FLAGS_AE_A5_A6 */
+ 0,
+};
+
+unsigned int on_action_mesh(_adapter *adapter, union recv_frame *rframe)
+{
+ unsigned int ret = _FAIL;
+ struct sta_info *sta = NULL;
+ struct sta_priv *stapriv = &adapter->stapriv;
+ u8 *pframe = rframe->u.hdr.rx_data;
+ uint frame_len = rframe->u.hdr.len;
+ u8 *frame_body = (u8 *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
+ u8 category;
+ u8 action;
+
+ if (!MLME_IS_MESH(adapter))
+ goto exit;
+
+ /* check stainfo exist? */
+
+ category = frame_body[0];
+ if (category != RTW_WLAN_CATEGORY_MESH)
+ goto exit;
+
+ action = frame_body[1];
+ switch (action) {
+ case RTW_ACT_MESH_HWMP_PATH_SELECTION:
+ rtw_mesh_rx_path_sel_frame(adapter, rframe);
+ ret = _SUCCESS;
+ break;
+ default:
+ break;
+ }
+
+exit:
+ return ret;
+}
+
+bool rtw_mesh_update_bss_peering_status(_adapter *adapter, WLAN_BSSID_EX *bss)
+{
+ struct sta_priv *stapriv = &adapter->stapriv;
+ struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+ u8 num_of_peerings = stapriv->asoc_list_cnt;
+ bool accept_peerings = stapriv->asoc_list_cnt < mcfg->max_peer_links;
+ u8 *ie;
+ int ie_len;
+ bool updated = 0;
+
+ ie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len, BSS_EX_TLV_IES_LEN(bss));
+ if (!ie || ie_len != 7) {
+ rtw_warn_on(1);
+ goto exit;
+ }
+
+ if (GET_MESH_CONF_ELE_NUM_OF_PEERINGS(ie + 2) != num_of_peerings) {
+ SET_MESH_CONF_ELE_NUM_OF_PEERINGS(ie + 2, num_of_peerings);
+ updated = 1;
+ }
+
+ if (GET_MESH_CONF_ELE_ACCEPT_PEERINGS(ie + 2) != accept_peerings) {
+ SET_MESH_CONF_ELE_ACCEPT_PEERINGS(ie + 2, accept_peerings);
+ updated = 1;
+ }
+
+exit:
+ return updated;
+}
+
+bool rtw_mesh_update_bss_formation_info(_adapter *adapter, WLAN_BSSID_EX *bss)
+{
+ struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ u8 cto_mgate = (minfo->num_gates || mcfg->dot11MeshGateAnnouncementProtocol);
+ u8 cto_as = 0;
+ u8 *ie;
+ int ie_len;
+ bool updated = 0;
+
+ ie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len,
+ BSS_EX_TLV_IES_LEN(bss));
+ if (!ie || ie_len != 7) {
+ rtw_warn_on(1);
+ goto exit;
+ }
+
+ if (GET_MESH_CONF_ELE_CTO_MGATE(ie + 2) != cto_mgate) {
+ SET_MESH_CONF_ELE_CTO_MGATE(ie + 2, cto_mgate);
+ updated = 1;
+ }
+
+ if (GET_MESH_CONF_ELE_CTO_AS(ie + 2) != cto_as) {
+ SET_MESH_CONF_ELE_CTO_AS(ie + 2, cto_as);
+ updated = 1;
+ }
+
+exit:
+ return updated;
+}
+
+bool rtw_mesh_update_bss_forwarding_state(_adapter *adapter, WLAN_BSSID_EX *bss)
+{
+ struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+ u8 forward = mcfg->dot11MeshForwarding;
+ u8 *ie;
+ int ie_len;
+ bool updated = 0;
+
+ ie = rtw_get_ie(BSS_EX_TLV_IES(bss), WLAN_EID_MESH_CONFIG, &ie_len,
+ BSS_EX_TLV_IES_LEN(bss));
+ if (!ie || ie_len != 7) {
+ rtw_warn_on(1);
+ goto exit;
+ }
+
+ if (GET_MESH_CONF_ELE_FORWARDING(ie + 2) != forward) {
+ SET_MESH_CONF_ELE_FORWARDING(ie + 2, forward);
+ updated = 1;
+ }
+
+exit:
+ return updated;
+}
+
+struct mesh_plink_ent *_rtw_mesh_plink_get(_adapter *adapter, const u8 *hwaddr)
+{
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+ struct mesh_plink_ent *ent = NULL;
+ int i;
+
+ for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) {
+ if (plink_ctl->ent[i].valid == _TRUE
+ && _rtw_memcmp(plink_ctl->ent[i].addr, hwaddr, ETH_ALEN) == _TRUE
+ ) {
+ ent = &plink_ctl->ent[i];
+ break;
+ }
+ }
+
+exit:
+ return ent;
+}
+
+struct mesh_plink_ent *rtw_mesh_plink_get(_adapter *adapter, const u8 *hwaddr)
+{
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+ struct mesh_plink_ent *ent = NULL;
+ _irqL irqL;
+
+ _enter_critical_bh(&(plink_ctl->lock), &irqL);
+ ent = _rtw_mesh_plink_get(adapter, hwaddr);
+ _exit_critical_bh(&(plink_ctl->lock), &irqL);
+
+exit:
+ return ent;
+}
+
+struct mesh_plink_ent *rtw_mesh_plink_get_no_estab_by_idx(_adapter *adapter, u8 idx)
+{
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+ struct mesh_plink_ent *ent = NULL;
+ int i, j = 0;
+ _irqL irqL;
+
+ _enter_critical_bh(&(plink_ctl->lock), &irqL);
+ for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) {
+ if (plink_ctl->ent[i].valid == _TRUE
+ && plink_ctl->ent[i].plink_state != RTW_MESH_PLINK_ESTAB
+ ) {
+ if (j == idx) {
+ ent = &plink_ctl->ent[i];
+ break;
+ }
+ j++;
+ }
+ }
+ _exit_critical_bh(&(plink_ctl->lock), &irqL);
+
+ return ent;
+}
+
+int _rtw_mesh_plink_add(_adapter *adapter, const u8 *hwaddr)
+{
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+ struct mesh_plink_ent *ent = NULL;
+ u8 exist = _FALSE;
+ int i;
+
+ for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) {
+ if (plink_ctl->ent[i].valid == _TRUE
+ && _rtw_memcmp(plink_ctl->ent[i].addr, hwaddr, ETH_ALEN) == _TRUE
+ ) {
+ ent = &plink_ctl->ent[i];
+ exist = _TRUE;
+ break;
+ }
+
+ if (ent == NULL && plink_ctl->ent[i].valid == _FALSE)
+ ent = &plink_ctl->ent[i];
+ }
+
+ if (exist == _FALSE && ent) {
+ _rtw_memcpy(ent->addr, hwaddr, ETH_ALEN);
+ ent->valid = _TRUE;
+ #ifdef CONFIG_RTW_MESH_AEK
+ ent->aek_valid = 0;
+ #endif
+ ent->llid = 0;
+ ent->plid = 0;
+ _rtw_memset(ent->chosen_pmk, 0, 16);
+ #ifdef CONFIG_RTW_MESH_AEK
+ _rtw_memset(ent->sel_pcs, 0, 4);
+ _rtw_memset(ent->l_nonce, 0, 32);
+ _rtw_memset(ent->p_nonce, 0, 32);
+ #endif
+ ent->plink_state = RTW_MESH_PLINK_LISTEN;
+ #ifndef CONFIG_RTW_MESH_DRIVER_AID
+ ent->aid = 0;
+ #endif
+ ent->peer_aid = 0;
+ SET_PEER_CONF_DISABLED(ent);
+ SET_CTO_MGATE_CONF_DISABLED(ent);
+ plink_ctl->num++;
+ }
+
+exit:
+ return exist == _TRUE ? RTW_ALREADY : (ent ? _SUCCESS : _FAIL);
+}
+
+int rtw_mesh_plink_add(_adapter *adapter, const u8 *hwaddr)
+{
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+ _irqL irqL;
+ int ret;
+
+ _enter_critical_bh(&(plink_ctl->lock), &irqL);
+ ret = _rtw_mesh_plink_add(adapter, hwaddr);
+ _exit_critical_bh(&(plink_ctl->lock), &irqL);
+
+ return ret;
+}
+
+int rtw_mesh_plink_set_state(_adapter *adapter, const u8 *hwaddr, u8 state)
+{
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+ struct mesh_plink_ent *ent = NULL;
+ _irqL irqL;
+
+ _enter_critical_bh(&(plink_ctl->lock), &irqL);
+ ent = _rtw_mesh_plink_get(adapter, hwaddr);
+ if (ent)
+ ent->plink_state = state;
+ _exit_critical_bh(&(plink_ctl->lock), &irqL);
+
+exit:
+ return ent ? _SUCCESS : _FAIL;
+}
+
+#ifdef CONFIG_RTW_MESH_AEK
+int rtw_mesh_plink_set_aek(_adapter *adapter, const u8 *hwaddr, const u8 *aek)
+{
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+ struct mesh_plink_ent *ent = NULL;
+ _irqL irqL;
+
+ _enter_critical_bh(&(plink_ctl->lock), &irqL);
+ ent = _rtw_mesh_plink_get(adapter, hwaddr);
+ if (ent) {
+ _rtw_memcpy(ent->aek, aek, 32);
+ ent->aek_valid = 1;
+ }
+ _exit_critical_bh(&(plink_ctl->lock), &irqL);
+
+exit:
+ return ent ? _SUCCESS : _FAIL;
+}
+#endif
+
+#if CONFIG_RTW_MESH_PEER_BLACKLIST
+int rtw_mesh_plink_set_peer_conf_timeout(_adapter *adapter, const u8 *hwaddr)
+{
+ struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+ struct mesh_plink_ent *ent = NULL;
+ _irqL irqL;
+
+ _enter_critical_bh(&(plink_ctl->lock), &irqL);
+ ent = _rtw_mesh_plink_get(adapter, hwaddr);
+ if (ent) {
+ if (IS_PEER_CONF_DISABLED(ent))
+ SET_PEER_CONF_END_TIME(ent, mcfg->peer_sel_policy.peer_conf_timeout_ms);
+ }
+ _exit_critical_bh(&(plink_ctl->lock), &irqL);
+
+exit:
+ return ent ? _SUCCESS : _FAIL;
+}
+#endif
+
+void _rtw_mesh_plink_del_ent(_adapter *adapter, struct mesh_plink_ent *ent)
+{
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+
+ ent->valid = _FALSE;
+ #ifdef CONFIG_RTW_MESH_DRIVER_AID
+ if (ent->tx_conf_ies && ent->tx_conf_ies_len)
+ rtw_mfree(ent->tx_conf_ies, ent->tx_conf_ies_len);
+ ent->tx_conf_ies = NULL;
+ ent->tx_conf_ies_len = 0;
+ #endif
+ if (ent->rx_conf_ies && ent->rx_conf_ies_len)
+ rtw_mfree(ent->rx_conf_ies, ent->rx_conf_ies_len);
+ ent->rx_conf_ies = NULL;
+ ent->rx_conf_ies_len = 0;
+ if (ent->scanned)
+ ent->scanned = NULL;
+ plink_ctl->num--;
+}
+
+int rtw_mesh_plink_del(_adapter *adapter, const u8 *hwaddr)
+{
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+ struct mesh_plink_ent *ent = NULL;
+ u8 exist = _FALSE;
+ int i;
+ _irqL irqL;
+
+ _enter_critical_bh(&(plink_ctl->lock), &irqL);
+ for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) {
+ if (plink_ctl->ent[i].valid == _TRUE
+ && _rtw_memcmp(plink_ctl->ent[i].addr, hwaddr, ETH_ALEN) == _TRUE
+ ) {
+ ent = &plink_ctl->ent[i];
+ exist = _TRUE;
+ break;
+ }
+ }
+
+ if (exist == _TRUE)
+ _rtw_mesh_plink_del_ent(adapter, ent);
+
+ _exit_critical_bh(&(plink_ctl->lock), &irqL);
+
+exit:
+ return exist == _TRUE ? _SUCCESS : RTW_ALREADY;
+}
+
+void rtw_mesh_plink_ctl_init(_adapter *adapter)
+{
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+ int i;
+
+ _rtw_spinlock_init(&plink_ctl->lock);
+ plink_ctl->num = 0;
+ for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++)
+ plink_ctl->ent[i].valid = _FALSE;
+
+#if CONFIG_RTW_MESH_PEER_BLACKLIST
+ _rtw_init_queue(&plink_ctl->peer_blacklist);
+#endif
+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+ _rtw_init_queue(&plink_ctl->cto_mgate_blacklist);
+#endif
+}
+
+void rtw_mesh_plink_ctl_deinit(_adapter *adapter)
+{
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+ struct mesh_plink_ent *ent;
+ int i;
+ _irqL irqL;
+
+ _enter_critical_bh(&(plink_ctl->lock), &irqL);
+ for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) {
+ ent = &plink_ctl->ent[i];
+ #ifdef CONFIG_RTW_MESH_DRIVER_AID
+ if (ent->tx_conf_ies && ent->tx_conf_ies_len)
+ rtw_mfree(ent->tx_conf_ies, ent->tx_conf_ies_len);
+ #endif
+ if (ent->rx_conf_ies && ent->rx_conf_ies_len)
+ rtw_mfree(ent->rx_conf_ies, ent->rx_conf_ies_len);
+ }
+ _exit_critical_bh(&(plink_ctl->lock), &irqL);
+
+ _rtw_spinlock_free(&plink_ctl->lock);
+
+#if CONFIG_RTW_MESH_PEER_BLACKLIST
+ rtw_mesh_peer_blacklist_flush(adapter);
+ _rtw_deinit_queue(&plink_ctl->peer_blacklist);
+#endif
+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+ rtw_mesh_cto_mgate_blacklist_flush(adapter);
+ _rtw_deinit_queue(&plink_ctl->cto_mgate_blacklist);
+#endif
+}
+
+void dump_mesh_plink_ctl(void *sel, _adapter *adapter)
+{
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+ struct mesh_plink_ent *ent;
+ int i;
+
+ RTW_PRINT_SEL(sel, "num:%u\n", plink_ctl->num);
+
+ for (i = 0; i < RTW_MESH_MAX_PEER_CANDIDATES; i++) {
+ ent = &plink_ctl->ent[i];
+ if (!ent->valid)
+ continue;
+
+ RTW_PRINT_SEL(sel, "\n");
+ RTW_PRINT_SEL(sel, "peer:"MAC_FMT"\n", MAC_ARG(ent->addr));
+ RTW_PRINT_SEL(sel, "plink_state:%s\n", rtw_mesh_plink_str(ent->plink_state));
+
+ #ifdef CONFIG_RTW_MESH_AEK
+ if (ent->aek_valid)
+ RTW_PRINT_SEL(sel, "aek:"KEY_FMT KEY_FMT"\n", KEY_ARG(ent->aek), KEY_ARG(ent->aek + 16));
+ #endif
+
+ RTW_PRINT_SEL(sel, "llid:%u, plid:%u\n", ent->llid, ent->plid);
+ #ifndef CONFIG_RTW_MESH_DRIVER_AID
+ RTW_PRINT_SEL(sel, "aid:%u\n", ent->aid);
+ #endif
+ RTW_PRINT_SEL(sel, "peer_aid:%u\n", ent->peer_aid);
+
+ RTW_PRINT_SEL(sel, "chosen_pmk:"KEY_FMT"\n", KEY_ARG(ent->chosen_pmk));
+
+ #ifdef CONFIG_RTW_MESH_AEK
+ RTW_PRINT_SEL(sel, "sel_pcs:%02x%02x%02x%02x\n"
+ , ent->sel_pcs[0], ent->sel_pcs[1], ent->sel_pcs[2], ent->sel_pcs[3]);
+ RTW_PRINT_SEL(sel, "l_nonce:"KEY_FMT KEY_FMT"\n", KEY_ARG(ent->l_nonce), KEY_ARG(ent->l_nonce + 16));
+ RTW_PRINT_SEL(sel, "p_nonce:"KEY_FMT KEY_FMT"\n", KEY_ARG(ent->p_nonce), KEY_ARG(ent->p_nonce + 16));
+ #endif
+
+ #ifdef CONFIG_RTW_MESH_DRIVER_AID
+ RTW_PRINT_SEL(sel, "tx_conf_ies:%p, len:%u\n", ent->tx_conf_ies, ent->tx_conf_ies_len);
+ #endif
+ RTW_PRINT_SEL(sel, "rx_conf_ies:%p, len:%u\n", ent->rx_conf_ies, ent->rx_conf_ies_len);
+ RTW_PRINT_SEL(sel, "scanned:%p\n", ent->scanned);
+
+ #if CONFIG_RTW_MESH_PEER_BLACKLIST
+ if (!IS_PEER_CONF_DISABLED(ent)) {
+ if (!IS_PEER_CONF_TIMEOUT(ent))
+ RTW_PRINT_SEL(sel, "peer_conf:%d\n", rtw_systime_to_ms(ent->peer_conf_end_time - rtw_get_current_time()));
+ else
+ RTW_PRINT_SEL(sel, "peer_conf:TIMEOUT\n");
+ }
+ #endif
+
+ #if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+ if (!IS_CTO_MGATE_CONF_DISABLED(ent)) {
+ if (!IS_CTO_MGATE_CONF_TIMEOUT(ent))
+ RTW_PRINT_SEL(sel, "cto_mgate_conf:%d\n", rtw_systime_to_ms(ent->cto_mgate_conf_end_time - rtw_get_current_time()));
+ else
+ RTW_PRINT_SEL(sel, "cto_mgate_conf:TIMEOUT\n");
+ }
+ #endif
+ }
+}
+
+/* this function is called with plink_ctl being locked */
+int rtw_mesh_peer_establish(_adapter *adapter, struct mesh_plink_ent *plink, struct sta_info *sta)
+{
+#ifndef DBG_RTW_MESH_PEER_ESTABLISH
+#define DBG_RTW_MESH_PEER_ESTABLISH 0
+#endif
+
+ struct sta_priv *stapriv = &adapter->stapriv;
+ struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+ u8 *tlv_ies;
+ u16 tlv_ieslen;
+ struct rtw_ieee802_11_elems elems;
+ _irqL irqL;
+ int i;
+ int ret = _FAIL;
+
+ if (!plink->rx_conf_ies || !plink->rx_conf_ies_len) {
+ RTW_INFO(FUNC_ADPT_FMT" no rx confirm from sta "MAC_FMT"\n"
+ , FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr));
+ goto exit;
+ }
+
+ if (plink->rx_conf_ies_len < 4) {
+ RTW_INFO(FUNC_ADPT_FMT" confirm from sta "MAC_FMT" too short\n"
+ , FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr));
+ goto exit;
+ }
+
+#ifdef CONFIG_RTW_MESH_DRIVER_AID
+ if (!plink->tx_conf_ies || !plink->tx_conf_ies_len) {
+ RTW_INFO(FUNC_ADPT_FMT" no tx confirm to sta "MAC_FMT"\n"
+ , FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr));
+ goto exit;
+ }
+
+ if (plink->tx_conf_ies_len < 4) {
+ RTW_INFO(FUNC_ADPT_FMT" confirm to sta "MAC_FMT" too short\n"
+ , FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr));
+ goto exit;
+ }
+#endif
+
+ tlv_ies = plink->rx_conf_ies + 4;
+ tlv_ieslen = plink->rx_conf_ies_len - 4;
+
+ if (DBG_RTW_MESH_PEER_ESTABLISH)
+ dump_ies(RTW_DBGDUMP, tlv_ies, tlv_ieslen);
+
+ if (rtw_ieee802_11_parse_elems(tlv_ies, tlv_ieslen, &elems, 1) == ParseFailed) {
+ RTW_INFO(FUNC_ADPT_FMT" sta "MAC_FMT" sent invalid confirm\n"
+ , FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr));
+ goto exit;
+ }
+
+ SET_PEER_CONF_DISABLED(plink);
+ if (rtw_bss_is_cto_mgate(&plink->scanned->network)
+ && !rtw_bss_is_forwarding(&plink->scanned->network))
+ SET_CTO_MGATE_CONF_END_TIME(plink, mcfg->peer_sel_policy.cto_mgate_conf_timeout_ms);
+ else
+ SET_CTO_MGATE_CONF_DISABLED(plink);
+
+ sta->state &= (~WIFI_FW_AUTH_SUCCESS);
+ sta->state |= WIFI_FW_ASSOC_STATE;
+
+ rtw_ap_parse_sta_capability(adapter, sta, plink->rx_conf_ies);
+
+ if (rtw_ap_parse_sta_supported_rates(adapter, sta, tlv_ies, tlv_ieslen) != _STATS_SUCCESSFUL_)
+ goto exit;
+
+ if (rtw_ap_parse_sta_security_ie(adapter, sta, &elems) != _STATS_SUCCESSFUL_)
+ goto exit;
+
+ rtw_ap_parse_sta_wmm_ie(adapter, sta, tlv_ies, tlv_ieslen);
+
+ rtw_ap_parse_sta_ht_ie(adapter, sta, &elems);
+ rtw_ap_parse_sta_vht_ie(adapter, sta, &elems);
+
+ /* AID */
+#ifdef CONFIG_RTW_MESH_DRIVER_AID
+ sta->cmn.aid = RTW_GET_LE16(plink->tx_conf_ies + 2);
+#else
+ sta->cmn.aid = plink->aid;
+#endif
+ stapriv->sta_aid[sta->cmn.aid - 1] = sta;
+ RTW_INFO(FUNC_ADPT_FMT" sta "MAC_FMT" aid:%u\n"
+ , FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr), sta->cmn.aid);
+
+ sta->state &= (~WIFI_FW_ASSOC_STATE);
+ sta->state |= WIFI_FW_ASSOC_SUCCESS;
+
+ sta->local_mps = RTW_MESH_PS_ACTIVE;
+
+ rtw_ewma_err_rate_init(&sta->metrics.err_rate);
+ rtw_ewma_err_rate_add(&sta->metrics.err_rate, 1);
+ /* init data_rate to 1M */
+ sta->metrics.data_rate = 10;
+
+ _enter_critical_bh(&stapriv->asoc_list_lock, &irqL);
+ if (rtw_is_list_empty(&sta->asoc_list)) {
+ STA_SET_MESH_PLINK(sta, plink);
+ sta->expire_to = mcfg->plink_timeout / 2;
+ rtw_list_insert_tail(&sta->asoc_list, &stapriv->asoc_list);
+ stapriv->asoc_list_cnt++;
+ }
+ _exit_critical_bh(&stapriv->asoc_list_lock, &irqL);
+
+ bss_cap_update_on_sta_join(adapter, sta);
+ sta_info_update(adapter, sta);
+ report_add_sta_event(adapter, sta->cmn.mac_addr);
+
+ ret = _SUCCESS;
+
+exit:
+ return ret;
+}
+
+void rtw_mesh_expire_peer_notify(_adapter *adapter, const u8 *peer_addr)
+{
+ u8 null_ssid[2] = {0, 0};
+
+#ifdef CONFIG_IOCTL_CFG80211
+ rtw_cfg80211_notify_new_peer_candidate(adapter->rtw_wdev
+ , peer_addr
+ , null_ssid
+ , 2
+ , GFP_ATOMIC
+ );
+#endif
+
+exit:
+ return;
+}
+
+static u8 *rtw_mesh_construct_peer_mesh_close(_adapter *adapter, struct mesh_plink_ent *plink, u16 reason, u32 *len)
+{
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ u8 *frame = NULL, *pos;
+ u32 flen;
+ struct rtw_ieee80211_hdr *whdr;
+
+ if (minfo->mesh_auth_id && !MESH_PLINK_AEK_VALID(plink))
+ goto exit;
+
+ flen = sizeof(struct rtw_ieee80211_hdr_3addr)
+ + 2 /* category, action */
+ + 2 + minfo->mesh_id_len /* mesh id */
+ + 2 + 8 + (minfo->mesh_auth_id ? 16 : 0) /* mpm */
+ + (minfo->mesh_auth_id ? 2 + AES_BLOCK_SIZE : 0) /* mic */
+ + (minfo->mesh_auth_id ? 70 : 0) /* ampe */
+ ;
+
+ pos = frame = rtw_zmalloc(flen);
+ if (!frame)
+ goto exit;
+
+ whdr = (struct rtw_ieee80211_hdr *)frame;
+ _rtw_memcpy(whdr->addr1, adapter_mac_addr(adapter), ETH_ALEN);
+ _rtw_memcpy(whdr->addr2, plink->addr, ETH_ALEN);
+ _rtw_memcpy(whdr->addr3, adapter_mac_addr(adapter), ETH_ALEN);
+
+ set_frame_sub_type(frame, WIFI_ACTION);
+
+ pos += sizeof(struct rtw_ieee80211_hdr_3addr);
+ *(pos++) = RTW_WLAN_CATEGORY_SELF_PROTECTED;
+ *(pos++) = RTW_ACT_SELF_PROTECTED_MESH_CLOSE;
+
+ pos = rtw_set_ie_mesh_id(pos, NULL, minfo->mesh_id, minfo->mesh_id_len);
+
+ pos = rtw_set_ie_mpm(pos, NULL
+ , minfo->mesh_auth_id ? 1 : 0
+ , plink->plid
+ , &plink->llid
+ , &reason
+ , minfo->mesh_auth_id ? plink->chosen_pmk : NULL);
+
+#ifdef CONFIG_RTW_MESH_AEK
+ if (minfo->mesh_auth_id) {
+ u8 ampe_buf[70];
+ int enc_ret;
+
+ *pos = WLAN_EID_MIC;
+ *(pos + 1) = AES_BLOCK_SIZE;
+
+ ampe_buf[0] = WLAN_EID_AMPE;
+ ampe_buf[1] = 68;
+ _rtw_memcpy(ampe_buf + 2, plink->sel_pcs, 4);
+ _rtw_memcpy(ampe_buf + 6, plink->p_nonce, 32);
+ _rtw_memcpy(ampe_buf + 38, plink->l_nonce, 32);
+
+ enc_ret = rtw_mpm_ampe_enc(adapter, plink
+ , frame + sizeof(struct rtw_ieee80211_hdr_3addr)
+ , pos, ampe_buf, 1);
+ if (enc_ret != _SUCCESS) {
+ rtw_mfree(frame, flen);
+ frame = NULL;
+ goto exit;
+ }
+ }
+#endif
+
+ *len = flen;
+
+exit:
+ return frame;
+}
+
+void _rtw_mesh_expire_peer_ent(_adapter *adapter, struct mesh_plink_ent *plink)
+{
+#if defined(CONFIG_RTW_MESH_STA_DEL_DISASOC)
+ _rtw_mesh_plink_del_ent(adapter, plink);
+ rtw_cfg80211_indicate_sta_disassoc(adapter, plink->addr, 0);
+#else
+ u8 *frame = NULL;
+ u32 flen;
+
+ if (plink->plink_state == RTW_MESH_PLINK_ESTAB)
+ frame = rtw_mesh_construct_peer_mesh_close(adapter, plink, WLAN_REASON_MESH_CLOSE, &flen);
+
+ if (frame) {
+ struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
+ struct wireless_dev *wdev = adapter->rtw_wdev;
+ s32 freq = rtw_ch2freq(mlmeext->cur_channel);
+
+ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
+ rtw_cfg80211_rx_mgmt(wdev, freq, 0, frame, flen, GFP_ATOMIC);
+ #else
+ cfg80211_rx_action(adapter->pnetdev, freq, frame, flen, GFP_ATOMIC);
+ #endif
+
+ rtw_mfree(frame, flen);
+ } else {
+ rtw_mesh_expire_peer_notify(adapter, plink->addr);
+ RTW_INFO(FUNC_ADPT_FMT" set "MAC_FMT" plink unknown\n"
+ , FUNC_ADPT_ARG(adapter), MAC_ARG(plink->addr));
+ plink->plink_state = RTW_MESH_PLINK_UNKNOWN;
+ }
+#endif
+}
+
+void rtw_mesh_expire_peer(_adapter *adapter, const u8 *peer_addr)
+{
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct mesh_plink_pool *plink_ctl = &minfo->plink_ctl;
+ struct mesh_plink_ent *plink;
+ _irqL irqL;
+
+ _enter_critical_bh(&(plink_ctl->lock), &irqL);
+
+ plink = _rtw_mesh_plink_get(adapter, peer_addr);
+ if (!plink)
+ goto exit;
+
+ _rtw_mesh_expire_peer_ent(adapter, plink);
+
+exit:
+ _exit_critical_bh(&(plink_ctl->lock), &irqL);
+}
+
+u8 rtw_mesh_ps_annc(_adapter *adapter, u8 ps)
+{
+ _irqL irqL;
+ _list *head, *list;
+ struct sta_info *sta;
+ struct sta_priv *stapriv = &adapter->stapriv;
+ u8 sta_alive_num = 0, i;
+ char sta_alive_list[NUM_STA];
+ u8 annc_cnt = 0;
+
+ if (rtw_linked_check(adapter) == _FALSE)
+ goto exit;
+
+ _enter_critical_bh(&stapriv->asoc_list_lock, &irqL);
+
+ head = &stapriv->asoc_list;
+ list = get_next(head);
+ while ((rtw_end_of_queue_search(head, list)) == _FALSE) {
+ int stainfo_offset;
+
+ sta = LIST_CONTAINOR(list, struct sta_info, asoc_list);
+ list = get_next(list);
+
+ stainfo_offset = rtw_stainfo_offset(stapriv, sta);
+ if (stainfo_offset_valid(stainfo_offset))
+ sta_alive_list[sta_alive_num++] = stainfo_offset;
+ }
+ _exit_critical_bh(&stapriv->asoc_list_lock, &irqL);
+
+ for (i = 0; i < sta_alive_num; i++) {
+ sta = rtw_get_stainfo_by_offset(stapriv, sta_alive_list[i]);
+ if (!sta)
+ continue;
+
+ issue_qos_nulldata(adapter, sta->cmn.mac_addr, 7, ps, 3, 500);
+ annc_cnt++;
+ }
+
+exit:
+ return annc_cnt;
+}
+
+static void mpath_tx_tasklet_hdl(void *priv)
+{
+ _adapter *adapter = (_adapter *)priv;
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct xmit_frame *xframe;
+ _list *list, *head;
+ _list tmp;
+ u32 tmp_len;
+ s32 res;
+
+ _rtw_init_listhead(&tmp);
+
+ while (1) {
+ tmp_len = 0;
+ enter_critical_bh(&minfo->mpath_tx_queue.lock);
+ if (minfo->mpath_tx_queue_len) {
+ rtw_list_splice_init(&minfo->mpath_tx_queue.queue, &tmp);
+ tmp_len = minfo->mpath_tx_queue_len;
+ minfo->mpath_tx_queue_len = 0;
+ }
+ exit_critical_bh(&minfo->mpath_tx_queue.lock);
+
+ if (!tmp_len)
+ break;
+
+ head = &tmp;
+ list = get_next(head);
+ while (rtw_end_of_queue_search(head, list) == _FALSE) {
+ xframe = LIST_CONTAINOR(list, struct xmit_frame, list);
+ list = get_next(list);
+ rtw_list_delete(&xframe->list);
+ res = rtw_xmit_posthandle(adapter, xframe, xframe->pkt);
+ if (res < 0) {
+ #ifdef DBG_TX_DROP_FRAME
+ RTW_INFO("DBG_TX_DROP_FRAME %s rtw_xmit fail\n", __FUNCTION__);
+ #endif
+ adapter->xmitpriv.tx_drop++;
+ }
+ }
+ }
+}
+
+static void rtw_mpath_tx_queue_flush(_adapter *adapter)
+{
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct xmit_frame *xframe;
+ _list *list, *head;
+ _list tmp;
+
+ _rtw_init_listhead(&tmp);
+
+ enter_critical_bh(&minfo->mpath_tx_queue.lock);
+ rtw_list_splice_init(&minfo->mpath_tx_queue.queue, &tmp);
+ minfo->mpath_tx_queue_len = 0;
+ exit_critical_bh(&minfo->mpath_tx_queue.lock);
+
+ head = &tmp;
+ list = get_next(head);
+ while (rtw_end_of_queue_search(head, list) == _FALSE) {
+ xframe = LIST_CONTAINOR(list, struct xmit_frame, list);
+ list = get_next(list);
+ rtw_list_delete(&xframe->list);
+ rtw_free_xmitframe(&adapter->xmitpriv, xframe);
+ }
+}
+
+#ifdef PLATFORM_LINUX /* 3.10 ~ 4.13 checked */
+#if defined(CONFIG_SLUB)
+#include
+#elif defined(CONFIG_SLAB)
+#include
+#endif
+typedef struct kmem_cache rtw_mcache;
+#endif
+
+rtw_mcache *rtw_mcache_create(const char *name, size_t size)
+{
+#ifdef PLATFORM_LINUX /* 3.10 ~ 4.13 checked */
+ return kmem_cache_create(name, size, 0, 0, NULL);
+#else
+ #error "TBD\n";
+#endif
+}
+
+void rtw_mcache_destroy(rtw_mcache *s)
+{
+#ifdef PLATFORM_LINUX /* 3.10 ~ 4.13 checked */
+ kmem_cache_destroy(s);
+#else
+ #error "TBD\n";
+#endif
+}
+
+void *_rtw_mcache_alloc(rtw_mcache *cachep)
+{
+#ifdef PLATFORM_LINUX /* 3.10 ~ 4.13 checked */
+ return kmem_cache_alloc(cachep, GFP_ATOMIC);
+#else
+ #error "TBD\n";
+#endif
+}
+
+void _rtw_mcache_free(rtw_mcache *cachep, void *objp)
+{
+#ifdef PLATFORM_LINUX /* 3.10 ~ 4.13 checked */
+ kmem_cache_free(cachep, objp);
+#else
+ #error "TBD\n";
+#endif
+}
+
+#ifdef DBG_MEM_ALLOC
+inline void *dbg_rtw_mcache_alloc(rtw_mcache *cachep, const enum mstat_f flags, const char *func, const int line)
+{
+ void *p;
+ u32 sz = cachep->size;
+
+ if (match_mstat_sniff_rules(flags, sz))
+ RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%u)\n", func, line, __func__, sz);
+
+ p = _rtw_mcache_alloc(cachep);
+
+ rtw_mstat_update(
+ flags
+ , p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL
+ , sz
+ );
+
+ return p;
+}
+
+inline void dbg_rtw_mcache_free(rtw_mcache *cachep, void *pbuf, const enum mstat_f flags, const char *func, const int line)
+{
+ u32 sz = cachep->size;
+
+ if (match_mstat_sniff_rules(flags, sz))
+ RTW_INFO("DBG_MEM_ALLOC %s:%d %s(%u)\n", func, line, __func__, sz);
+
+ _rtw_mcache_free(cachep, pbuf);
+
+ rtw_mstat_update(
+ flags
+ , MSTAT_FREE
+ , sz
+ );
+}
+
+#define rtw_mcache_alloc(cachep) dbg_rtw_mcache_alloc(cachep, MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
+#define rtw_mcache_free(cachep, objp) dbg_rtw_mcache_free(cachep, objp, MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
+#else
+#define rtw_mcache_alloc(cachep) _rtw_mcache_alloc(cachep)
+#define rtw_mcache_free(cachep, objp) _rtw_mcache_free(cachep, objp)
+#endif /* DBG_MEM_ALLOC */
+
+/* Mesh Received Cache */
+#define RTW_MRC_BUCKETS 256 /* must be a power of 2 */
+#define RTW_MRC_QUEUE_MAX_LEN 4
+#define RTW_MRC_TIMEOUT_MS (3 * 1000)
+
+/**
+ * struct rtw_mrc_entry - entry in the Mesh Received Cache
+ *
+ * @seqnum: mesh sequence number of the frame
+ * @exp_time: expiration time of the entry
+ * @msa: mesh source address of the frame
+ * @list: hashtable list pointer
+ *
+ * The Mesh Received Cache keeps track of the latest received frames that
+ * have been received by a mesh interface and discards received frames
+ * that are found in the cache.
+ */
+struct rtw_mrc_entry {
+ rtw_hlist_node list;
+ systime exp_time;
+ u32 seqnum;
+ u8 msa[ETH_ALEN];
+};
+
+struct rtw_mrc {
+ rtw_hlist_head bucket[RTW_MRC_BUCKETS];
+ u32 idx_mask;
+ rtw_mcache *cache;
+};
+
+static int rtw_mrc_init(_adapter *adapter)
+{
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ char cache_name[IFNAMSIZ + 8 + 1];
+ int i;
+
+ minfo->mrc = rtw_malloc(sizeof(struct rtw_mrc));
+ if (!minfo->mrc)
+ return -ENOMEM;
+ minfo->mrc->idx_mask = RTW_MRC_BUCKETS - 1;
+ for (i = 0; i < RTW_MRC_BUCKETS; i++)
+ rtw_hlist_head_init(&minfo->mrc->bucket[i]);
+
+ sprintf(cache_name, "rtw_mrc_%s", ADPT_ARG(adapter));
+ minfo->mrc->cache = rtw_mcache_create(cache_name, sizeof(struct rtw_mrc_entry));
+
+ return 0;
+}
+
+static void rtw_mrc_free(_adapter *adapter)
+{
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct rtw_mrc *mrc = minfo->mrc;
+ struct rtw_mrc_entry *p;
+ rtw_hlist_node *np, *n;
+ int i;
+
+ if (!mrc)
+ return;
+
+ for (i = 0; i < RTW_MRC_BUCKETS; i++) {
+ rtw_hlist_for_each_entry_safe(p, np, n, &mrc->bucket[i], list) {
+ rtw_hlist_del(&p->list);
+ rtw_mcache_free(mrc->cache, p);
+ }
+ }
+
+ rtw_mcache_destroy(mrc->cache);
+
+ rtw_mfree(mrc, sizeof(struct rtw_mrc));
+ minfo->mrc = NULL;
+}
+
+/**
+ * rtw_mrc_check - Check frame in mesh received cache and add if absent.
+ *
+ * @adapter: interface
+ * @msa: mesh source address
+ * @seq: mesh seq number
+ *
+ * Returns: 0 if the frame is not in the cache, nonzero otherwise.
+ *
+ * Checks using the mesh source address and the mesh sequence number if we have
+ * received this frame lately. If the frame is not in the cache, it is added to
+ * it.
+ */
+static int rtw_mrc_check(_adapter *adapter, const u8 *msa, u32 seq)
+{
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct rtw_mrc *mrc = minfo->mrc;
+ int entries = 0;
+ u8 idx;
+ struct rtw_mrc_entry *p;
+ rtw_hlist_node *np, *n;
+ u8 timeout;
+
+ if (!mrc)
+ return -1;
+
+ idx = seq & mrc->idx_mask;
+ rtw_hlist_for_each_entry_safe(p, np, n, &mrc->bucket[idx], list) {
+ ++entries;
+ timeout = rtw_time_after(rtw_get_current_time(), p->exp_time);
+ if (timeout || entries == RTW_MRC_QUEUE_MAX_LEN) {
+ if (!timeout)
+ minfo->mshstats.mrc_del_qlen++;
+
+ rtw_hlist_del(&p->list);
+ rtw_mcache_free(mrc->cache, p);
+ --entries;
+ } else if ((seq == p->seqnum) && _rtw_memcmp(msa, p->msa, ETH_ALEN) == _TRUE)
+ return -1;
+ }
+
+ p = rtw_mcache_alloc(mrc->cache);
+ if (!p)
+ return 0;
+
+ p->seqnum = seq;
+ p->exp_time = rtw_get_current_time() + rtw_ms_to_systime(RTW_MRC_TIMEOUT_MS);
+ _rtw_memcpy(p->msa, msa, ETH_ALEN);
+ rtw_hlist_add_head(&p->list, &mrc->bucket[idx]);
+ return 0;
+}
+
+static int rtw_mesh_decache(_adapter *adapter, const u8 *msa, u32 seq)
+{
+ return rtw_mrc_check(adapter, msa, seq);
+}
+
+void rtw_mesh_cfg_init_peer_sel_policy(struct rtw_mesh_cfg *mcfg)
+{
+ struct mesh_peer_sel_policy *sel_policy = &mcfg->peer_sel_policy;
+
+ sel_policy->scanr_exp_ms = RTW_MESH_SCAN_RESULT_EXP_MS;
+
+#if CONFIG_RTW_MESH_OFFCH_CAND
+ sel_policy->offch_find_int_ms = RTW_MESH_OFFCH_CAND_FIND_INT_MS;
+#endif
+
+#if CONFIG_RTW_MESH_PEER_BLACKLIST
+ sel_policy->peer_conf_timeout_ms = RTW_MESH_PEER_CONF_TIMEOUT_MS;
+ sel_policy->peer_blacklist_timeout_ms = RTW_MESH_PEER_BLACKLIST_TIMEOUT_MS;
+#endif
+
+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+ sel_policy->cto_mgate_require = 0;
+ sel_policy->cto_mgate_conf_timeout_ms = RTW_MESH_CTO_MGATE_CONF_TIMEOUT_MS;
+ sel_policy->cto_mgate_blacklist_timeout_ms = RTW_MESH_CTO_MGATE_BLACKLIST_TIMEOUT_MS;
+#endif
+}
+
+void rtw_mesh_cfg_init(_adapter *adapter)
+{
+ struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+
+ mcfg->max_peer_links = RTW_MESH_MAX_PEER_LINKS;
+ mcfg->plink_timeout = RTW_MESH_PEER_LINK_TIMEOUT;
+
+ mcfg->dot11MeshTTL = RTW_MESH_TTL;
+ mcfg->element_ttl = RTW_MESH_DEFAULT_ELEMENT_TTL;
+ mcfg->dot11MeshHWMPmaxPREQretries = RTW_MESH_MAX_PREQ_RETRIES;
+ mcfg->path_refresh_time = RTW_MESH_PATH_REFRESH_TIME;
+ mcfg->min_discovery_timeout = RTW_MESH_MIN_DISCOVERY_TIMEOUT;
+ mcfg->dot11MeshHWMPactivePathTimeout = RTW_MESH_PATH_TIMEOUT;
+ mcfg->dot11MeshHWMPpreqMinInterval = RTW_MESH_PREQ_MIN_INT;
+ mcfg->dot11MeshHWMPperrMinInterval = RTW_MESH_PERR_MIN_INT;
+ mcfg->dot11MeshHWMPnetDiameterTraversalTime = RTW_MESH_DIAM_TRAVERSAL_TIME;
+ mcfg->dot11MeshHWMPRootMode = RTW_IEEE80211_ROOTMODE_NO_ROOT;
+ mcfg->dot11MeshHWMPRannInterval = RTW_MESH_RANN_INTERVAL;
+ mcfg->dot11MeshGateAnnouncementProtocol = _FALSE;
+ mcfg->dot11MeshForwarding = _TRUE;
+ mcfg->rssi_threshold = 0;
+ mcfg->dot11MeshHWMPactivePathToRootTimeout = RTW_MESH_PATH_TO_ROOT_TIMEOUT;
+ mcfg->dot11MeshHWMProotInterval = RTW_MESH_ROOT_INTERVAL;
+ mcfg->dot11MeshHWMPconfirmationInterval = RTW_MESH_ROOT_CONFIRMATION_INTERVAL;
+ mcfg->path_gate_timeout_factor = 3;
+ rtw_mesh_cfg_init_peer_sel_policy(mcfg);
+
+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
+ mcfg->b2u_flags_msrc = 0;
+ mcfg->b2u_flags_mfwd = RTW_MESH_B2U_GA_UCAST;
+#endif
+}
+
+void rtw_mesh_cfg_init_max_peer_links(_adapter *adapter, u8 stack_conf)
+{
+ struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+
+ mcfg->max_peer_links = RTW_MESH_MAX_PEER_LINKS;
+
+ if (mcfg->max_peer_links > stack_conf)
+ mcfg->max_peer_links = stack_conf;
+}
+
+void rtw_mesh_cfg_init_plink_timeout(_adapter *adapter, u32 stack_conf)
+{
+ struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+
+ mcfg->plink_timeout = stack_conf;
+}
+
+void rtw_mesh_init_mesh_info(_adapter *adapter)
+{
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+
+ _rtw_memset(minfo, 0, sizeof(struct rtw_mesh_info));
+
+ rtw_mesh_plink_ctl_init(adapter);
+
+ minfo->last_preq = rtw_get_current_time();
+ /* minfo->last_sn_update = rtw_get_current_time(); */
+ minfo->next_perr = rtw_get_current_time();
+
+ ATOMIC_SET(&minfo->mpaths, 0);
+ rtw_mesh_pathtbl_init(adapter);
+
+ _rtw_init_queue(&minfo->mpath_tx_queue);
+ tasklet_init(&minfo->mpath_tx_tasklet
+ , (void(*)(unsigned long))mpath_tx_tasklet_hdl
+ , (unsigned long)adapter);
+
+ rtw_mrc_init(adapter);
+
+ _rtw_init_listhead(&minfo->preq_queue.list);
+ _rtw_spinlock_init(&minfo->mesh_preq_queue_lock);
+
+ rtw_init_timer(&adapter->mesh_path_timer, adapter, rtw_ieee80211_mesh_path_timer, adapter);
+ rtw_init_timer(&adapter->mesh_path_root_timer, adapter, rtw_ieee80211_mesh_path_root_timer, adapter);
+ rtw_init_timer(&adapter->mesh_atlm_param_req_timer, adapter, rtw_mesh_atlm_param_req_timer, adapter);
+ _init_workitem(&adapter->mesh_work, rtw_mesh_work_hdl, NULL);
+}
+
+void rtw_mesh_deinit_mesh_info(_adapter *adapter)
+{
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+
+ tasklet_kill(&minfo->mpath_tx_tasklet);
+ rtw_mpath_tx_queue_flush(adapter);
+ _rtw_deinit_queue(&adapter->mesh_info.mpath_tx_queue);
+
+ rtw_mrc_free(adapter);
+
+ rtw_mesh_pathtbl_unregister(adapter);
+
+ rtw_mesh_plink_ctl_deinit(adapter);
+
+ _cancel_workitem_sync(&adapter->mesh_work);
+ _cancel_timer_ex(&adapter->mesh_path_timer);
+ _cancel_timer_ex(&adapter->mesh_path_root_timer);
+ _cancel_timer_ex(&adapter->mesh_atlm_param_req_timer);
+}
+
+/**
+ * rtw_mesh_nexthop_resolve - lookup next hop; conditionally start path discovery
+ *
+ * @skb: 802.11 frame to be sent
+ * @sdata: network subif the frame will be sent through
+ *
+ * Lookup next hop for given skb and start path discovery if no
+ * forwarding information is found.
+ *
+ * Returns: 0 if the next hop was found and -ENOENT if the frame was queued.
+ * skb is freeed here if no mpath could be allocated.
+ */
+int rtw_mesh_nexthop_resolve(_adapter *adapter,
+ struct xmit_frame *xframe)
+{
+ struct pkt_attrib *attrib = &xframe->attrib;
+ struct rtw_mesh_path *mpath;
+ struct xmit_frame *xframe_to_free = NULL;
+ u8 *target_addr = attrib->mda;
+ int err = 0;
+ int ret = _SUCCESS;
+
+ rtw_rcu_read_lock();
+ err = rtw_mesh_nexthop_lookup(adapter, target_addr, attrib->msa, attrib->ra);
+ if (!err)
+ goto endlookup;
+
+ /* no nexthop found, start resolving */
+ mpath = rtw_mesh_path_lookup(adapter, target_addr);
+ if (!mpath) {
+ mpath = rtw_mesh_path_add(adapter, target_addr);
+ if (IS_ERR(mpath)) {
+ xframe->pkt = NULL; /* free pkt outside */
+ rtw_mesh_path_discard_frame(adapter, xframe);
+ err = PTR_ERR(mpath);
+ ret = _FAIL;
+ goto endlookup;
+ }
+ }
+
+ if (!(mpath->flags & RTW_MESH_PATH_RESOLVING))
+ rtw_mesh_queue_preq(mpath, RTW_PREQ_Q_F_START);
+
+ enter_critical_bh(&mpath->frame_queue.lock);
+
+ if (mpath->frame_queue_len >= RTW_MESH_FRAME_QUEUE_LEN) {
+ xframe_to_free = LIST_CONTAINOR(get_next(get_list_head(&mpath->frame_queue)), struct xmit_frame, list);
+ rtw_list_delete(&(xframe_to_free->list));
+ mpath->frame_queue_len--;
+ }
+
+ rtw_list_insert_tail(&xframe->list, get_list_head(&mpath->frame_queue));
+ mpath->frame_queue_len++;
+
+ exit_critical_bh(&mpath->frame_queue.lock);
+
+ ret = RTW_RA_RESOLVING;
+ if (xframe_to_free)
+ rtw_mesh_path_discard_frame(adapter, xframe_to_free);
+
+endlookup:
+ rtw_rcu_read_unlock();
+ return ret;
+}
+
+/**
+ * rtw_mesh_nexthop_lookup - put the appropriate next hop on a mesh frame. Calling
+ * this function is considered "using" the associated mpath, so preempt a path
+ * refresh if this mpath expires soon.
+ *
+ * @skb: 802.11 frame to be sent
+ * @sdata: network subif the frame will be sent through
+ *
+ * Returns: 0 if the next hop was found. Nonzero otherwise.
+ */
+int rtw_mesh_nexthop_lookup(_adapter *adapter,
+ const u8 *mda, const u8 *msa, u8 *ra)
+{
+ struct rtw_mesh_path *mpath;
+ struct sta_info *next_hop;
+ const u8 *target_addr = mda;
+ int err = -ENOENT;
+
+ rtw_rcu_read_lock();
+ mpath = rtw_mesh_path_lookup(adapter, target_addr);
+
+ if (!mpath || !(mpath->flags & RTW_MESH_PATH_ACTIVE))
+ goto endlookup;
+
+ if (rtw_time_after(rtw_get_current_time(),
+ mpath->exp_time -
+ rtw_ms_to_systime(adapter->mesh_cfg.path_refresh_time)) &&
+ _rtw_memcmp(adapter_mac_addr(adapter), msa, ETH_ALEN) == _TRUE &&
+ !(mpath->flags & RTW_MESH_PATH_RESOLVING) &&
+ !(mpath->flags & RTW_MESH_PATH_FIXED)) {
+ rtw_mesh_queue_preq(mpath, RTW_PREQ_Q_F_START | RTW_PREQ_Q_F_REFRESH);
+ }
+
+ next_hop = rtw_rcu_dereference(mpath->next_hop);
+ if (next_hop) {
+ _rtw_memcpy(ra, next_hop->cmn.mac_addr, ETH_ALEN);
+ err = 0;
+ }
+
+endlookup:
+ rtw_rcu_read_unlock();
+ return err;
+}
+
+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
+static bool rtw_mesh_data_bmc_to_uc(_adapter *adapter
+ , const u8 *da, const u8 *sa, const u8 *mda, const u8 *msa
+ , u8 ae_need, const u8 *ori_ta, u8 mfwd_ttl
+ , _list *b2u_list, u8 *b2u_num, u32 *b2u_mseq)
+{
+ struct sta_priv *stapriv = &adapter->stapriv;
+ struct xmit_priv *xmitpriv = &adapter->xmitpriv;
+ _irqL irqL;
+ _list *head, *list;
+ struct sta_info *sta;
+ char b2u_sta_id[NUM_STA];
+ u8 b2u_sta_num = 0;
+ bool bmc_need = _FALSE;
+ int i;
+
+ _enter_critical_bh(&stapriv->asoc_list_lock, &irqL);
+ head = &stapriv->asoc_list;
+ list = get_next(head);
+
+ while ((rtw_end_of_queue_search(head, list)) == _FALSE) {
+ int stainfo_offset;
+
+ sta = LIST_CONTAINOR(list, struct sta_info, asoc_list);
+ list = get_next(list);
+
+ stainfo_offset = rtw_stainfo_offset(stapriv, sta);
+ if (stainfo_offset_valid(stainfo_offset))
+ b2u_sta_id[b2u_sta_num++] = stainfo_offset;
+ }
+ _exit_critical_bh(&stapriv->asoc_list_lock, &irqL);
+
+ if (!b2u_sta_num)
+ goto exit;
+
+ for (i = 0; i < b2u_sta_num; i++) {
+ struct xmit_frame *b2uframe;
+ struct pkt_attrib *attrib;
+
+ sta = rtw_get_stainfo_by_offset(stapriv, b2u_sta_id[i]);
+ if (!(sta->state & _FW_LINKED)
+ || _rtw_memcmp(sta->cmn.mac_addr, msa, ETH_ALEN) == _TRUE
+ || (ori_ta && _rtw_memcmp(sta->cmn.mac_addr, ori_ta, ETH_ALEN) == _TRUE)
+ || is_broadcast_mac_addr(sta->cmn.mac_addr)
+ || is_zero_mac_addr(sta->cmn.mac_addr))
+ continue;
+
+ b2uframe = rtw_alloc_xmitframe(xmitpriv);
+ if (!b2uframe) {
+ bmc_need = _TRUE;
+ break;
+ }
+
+ if ((*b2u_num)++ == 0 && !ori_ta) {
+ *b2u_mseq = (cpu_to_le32(adapter->mesh_info.mesh_seqnum));
+ adapter->mesh_info.mesh_seqnum++;
+ }
+
+ attrib = &b2uframe->attrib;
+
+ attrib->mb2u = 1;
+ attrib->mseq = *b2u_mseq;
+ attrib->mfwd_ttl = ori_ta ? mfwd_ttl : 0;
+ _rtw_memcpy(attrib->ra, sta->cmn.mac_addr, ETH_ALEN);
+ _rtw_memcpy(attrib->ta, adapter_mac_addr(adapter), ETH_ALEN);
+ _rtw_memcpy(attrib->mda, mda, ETH_ALEN);
+ _rtw_memcpy(attrib->msa, msa, ETH_ALEN);
+ _rtw_memcpy(attrib->dst, da, ETH_ALEN);
+ _rtw_memcpy(attrib->src, sa, ETH_ALEN);
+ attrib->mesh_frame_mode = ae_need ? MESH_UCAST_PX_DATA : MESH_UCAST_DATA;
+
+ rtw_list_insert_tail(&b2uframe->list, b2u_list);
+ }
+
+exit:
+ return bmc_need;
+}
+
+void dump_mesh_b2u_flags(void *sel, _adapter *adapter)
+{
+ struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+
+ RTW_PRINT_SEL(sel, "%4s %4s\n", "msrc", "mfwd");
+ RTW_PRINT_SEL(sel, "0x%02x 0x%02x\n", mcfg->b2u_flags_msrc, mcfg->b2u_flags_mfwd);
+}
+#endif /* CONFIG_RTW_MESH_DATA_BMC_TO_UC */
+
+int rtw_mesh_addr_resolve(_adapter *adapter, struct xmit_frame *xframe, _pkt *pkt, _list *b2u_list)
+{
+ struct pkt_file pktfile;
+ struct ethhdr etherhdr;
+ struct pkt_attrib *attrib;
+ struct rtw_mesh_path *mpath = NULL, *mppath = NULL;
+ u8 is_da_mcast;
+ u8 ae_need;
+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
+ bool bmc_need = _TRUE;
+ u8 b2u_num = 0;
+ u32 b2u_mseq = 0;
+#endif
+ int res = _SUCCESS;
+
+ _rtw_open_pktfile(pkt, &pktfile);
+ if (_rtw_pktfile_read(&pktfile, (u8 *)ðerhdr, ETH_HLEN) != ETH_HLEN) {
+ res = _FAIL;
+ goto exit;
+ }
+
+ xframe->pkt = pkt;
+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
+ _rtw_init_listhead(b2u_list);
+#endif
+
+ is_da_mcast = IS_MCAST(etherhdr.h_dest);
+ if (!is_da_mcast) {
+ struct sta_info *next_hop;
+ bool mpp_lookup = 1;
+
+ mpath = rtw_mesh_path_lookup(adapter, etherhdr.h_dest);
+ if (mpath) {
+ mpp_lookup = 0;
+ next_hop = rtw_rcu_dereference(mpath->next_hop);
+ if (!next_hop
+ || !(mpath->flags & (RTW_MESH_PATH_ACTIVE | RTW_MESH_PATH_RESOLVING))
+ ) {
+ /* mpath is not valid, search mppath */
+ mpp_lookup = 1;
+ }
+ }
+
+ if (mpp_lookup) {
+ mppath = rtw_mpp_path_lookup(adapter, etherhdr.h_dest);
+ if (mppath)
+ mppath->exp_time = rtw_get_current_time();
+ }
+
+ if (mppath && mpath)
+ rtw_mesh_path_del(adapter, mpath->dst);
+
+ ae_need = _rtw_memcmp(adapter_mac_addr(adapter), etherhdr.h_source, ETH_ALEN) == _FALSE
+ || (mppath && _rtw_memcmp(mppath->mpp, etherhdr.h_dest, ETH_ALEN) == _FALSE);
+ } else {
+ ae_need = _rtw_memcmp(adapter_mac_addr(adapter), etherhdr.h_source, ETH_ALEN) == _FALSE;
+
+ #if CONFIG_RTW_MESH_DATA_BMC_TO_UC
+ if (rtw_msrc_b2u_policy_chk(adapter->mesh_cfg.b2u_flags_msrc, etherhdr.h_dest)) {
+ bmc_need = rtw_mesh_data_bmc_to_uc(adapter
+ , etherhdr.h_dest, etherhdr.h_source
+ , etherhdr.h_dest, adapter_mac_addr(adapter), ae_need, NULL, 0
+ , b2u_list, &b2u_num, &b2u_mseq);
+ if (bmc_need == _FALSE) {
+ res = RTW_BMC_NO_NEED;
+ goto exit;
+ }
+ }
+ #endif
+ }
+
+ attrib = &xframe->attrib;
+
+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
+ if (b2u_num) {
+ attrib->mb2u = 1;
+ attrib->mseq = b2u_mseq;
+ } else
+ attrib->mb2u = 0;
+#endif
+
+ attrib->mfwd_ttl = 0;
+ _rtw_memcpy(attrib->dst, etherhdr.h_dest, ETH_ALEN);
+ _rtw_memcpy(attrib->src, etherhdr.h_source, ETH_ALEN);
+ _rtw_memcpy(attrib->ta, adapter_mac_addr(adapter), ETH_ALEN);
+
+ if (is_da_mcast) {
+ attrib->mesh_frame_mode = ae_need ? MESH_BMCAST_PX_DATA : MESH_BMCAST_DATA;
+ _rtw_memcpy(attrib->ra, attrib->dst, ETH_ALEN);
+ _rtw_memcpy(attrib->msa, adapter_mac_addr(adapter), ETH_ALEN);
+ } else {
+ attrib->mesh_frame_mode = ae_need ? MESH_UCAST_PX_DATA : MESH_UCAST_DATA;
+ _rtw_memcpy(attrib->mda, (mppath && ae_need) ? mppath->mpp : attrib->dst, ETH_ALEN);
+ _rtw_memcpy(attrib->msa, adapter_mac_addr(adapter), ETH_ALEN);
+ /* RA needs to be resolved */
+ res = rtw_mesh_nexthop_resolve(adapter, xframe);
+ }
+
+exit:
+ return res;
+}
+
+s8 rtw_mesh_tx_set_whdr_mctrl_len(u8 mesh_frame_mode, struct pkt_attrib *attrib)
+{
+ u8 ret = 0;
+ switch (mesh_frame_mode) {
+ case MESH_UCAST_DATA:
+ attrib->hdrlen = WLAN_HDR_A4_QOS_LEN;
+ /* mesh flag + mesh TTL + Mesh SN. no ext addr. */
+ attrib->meshctrl_len = 6;
+ break;
+ case MESH_BMCAST_DATA:
+ attrib->hdrlen = WLAN_HDR_A3_QOS_LEN;
+ /* mesh flag + mesh TTL + Mesh SN. no ext addr. */
+ attrib->meshctrl_len = 6;
+ break;
+ case MESH_UCAST_PX_DATA:
+ attrib->hdrlen = WLAN_HDR_A4_QOS_LEN;
+ /* mesh flag + mesh TTL + Mesh SN + extaddr1 + extaddr2. */
+ attrib->meshctrl_len = 18;
+ break;
+ case MESH_BMCAST_PX_DATA:
+ attrib->hdrlen = WLAN_HDR_A3_QOS_LEN;
+ /* mesh flag + mesh TTL + Mesh SN + extaddr1 */
+ attrib->meshctrl_len = 12;
+ break;
+ default:
+ RTW_WARN("Invalid mesh frame mode:%u\n", mesh_frame_mode);
+ ret = -1;
+ break;
+ }
+
+ return ret;
+}
+
+void rtw_mesh_tx_build_mctrl(_adapter *adapter, struct pkt_attrib *attrib, u8 *buf)
+{
+ struct rtw_ieee80211s_hdr *mctrl = (struct rtw_ieee80211s_hdr *)buf;
+
+ _rtw_memset(mctrl, 0, XATTRIB_GET_MCTRL_LEN(attrib));
+
+ if (attrib->mfwd_ttl
+ #if CONFIG_RTW_MESH_DATA_BMC_TO_UC
+ || attrib->mb2u
+ #endif
+ ) {
+ #if CONFIG_RTW_MESH_DATA_BMC_TO_UC
+ if (!attrib->mfwd_ttl)
+ mctrl->ttl = adapter->mesh_cfg.dot11MeshTTL;
+ else
+ #endif
+ mctrl->ttl = attrib->mfwd_ttl;
+
+ mctrl->seqnum = (cpu_to_le32(attrib->mseq));
+ } else {
+ mctrl->ttl = adapter->mesh_cfg.dot11MeshTTL;
+ mctrl->seqnum = (cpu_to_le32(adapter->mesh_info.mesh_seqnum));
+ adapter->mesh_info.mesh_seqnum++;
+ }
+
+ switch (attrib->mesh_frame_mode){
+ case MESH_UCAST_DATA:
+ case MESH_BMCAST_DATA:
+ break;
+ case MESH_UCAST_PX_DATA:
+ mctrl->flags |= MESH_FLAGS_AE_A5_A6;
+ _rtw_memcpy(mctrl->eaddr1, attrib->dst, ETH_ALEN);
+ _rtw_memcpy(mctrl->eaddr2, attrib->src, ETH_ALEN);
+ break;
+ case MESH_BMCAST_PX_DATA:
+ mctrl->flags |= MESH_FLAGS_AE_A4;
+ _rtw_memcpy(mctrl->eaddr1, attrib->src, ETH_ALEN);
+ break;
+ case MESH_MHOP_UCAST_ACT:
+ /* TBD */
+ break;
+ case MESH_MHOP_BMCAST_ACT:
+ /* TBD */
+ break;
+ default:
+ break;
+ }
+}
+
+u8 rtw_mesh_tx_build_whdr(_adapter *adapter, struct pkt_attrib *attrib
+ , u16 *fctrl, struct rtw_ieee80211_hdr *whdr)
+{
+ switch (attrib->mesh_frame_mode) {
+ case MESH_UCAST_DATA: /* 1, 1, RA, TA, mDA(=DA), mSA(=SA) */
+ case MESH_UCAST_PX_DATA: /* 1, 1, RA, TA, mDA, mSA, [DA, SA] */
+ SetToDs(fctrl);
+ SetFrDs(fctrl);
+ _rtw_memcpy(whdr->addr1, attrib->ra, ETH_ALEN);
+ _rtw_memcpy(whdr->addr2, attrib->ta, ETH_ALEN);
+ _rtw_memcpy(whdr->addr3, attrib->mda, ETH_ALEN);
+ _rtw_memcpy(whdr->addr4, attrib->msa, ETH_ALEN);
+ break;
+ case MESH_BMCAST_DATA: /* 0, 1, RA(DA), TA, mSA(SA) */
+ case MESH_BMCAST_PX_DATA: /* 0, 1, RA(DA), TA, mSA, [SA] */
+ SetFrDs(fctrl);
+ _rtw_memcpy(whdr->addr1, attrib->ra, ETH_ALEN);
+ _rtw_memcpy(whdr->addr2, attrib->ta, ETH_ALEN);
+ _rtw_memcpy(whdr->addr3, attrib->msa, ETH_ALEN);
+ break;
+ case MESH_MHOP_UCAST_ACT:
+ /* TBD */
+ RTW_INFO("MESH_MHOP_UCAST_ACT\n");
+ break;
+ case MESH_MHOP_BMCAST_ACT:
+ /* TBD */
+ RTW_INFO("MESH_MHOP_BMCAST_ACT\n");
+ break;
+ default:
+ RTW_WARN("Invalid mesh frame mode\n");
+ break;
+ }
+
+ return 0;
+}
+
+int rtw_mesh_rx_data_validate_hdr(_adapter *adapter, union recv_frame *rframe, struct sta_info **sta)
+{
+ struct sta_priv *stapriv = &adapter->stapriv;
+ struct rx_pkt_attrib *rattrib = &rframe->u.hdr.attrib;
+ u8 *whdr = get_recvframe_data(rframe);
+ u8 is_ra_bmc = 0;
+ u8 a4_shift = 0;
+ u8 ps;
+ u8 *qc;
+ u8 mps_mode = RTW_MESH_PS_UNKNOWN;
+ sint ret = _FAIL;
+
+ if (!(MLME_STATE(adapter) & WIFI_ASOC_STATE))
+ goto exit;
+
+ if (!rattrib->qos)
+ goto exit;
+
+ switch (rattrib->to_fr_ds) {
+ case 1:
+ if (!IS_MCAST(GetAddr1Ptr(whdr)))
+ goto exit;
+ *sta = rtw_get_stainfo(stapriv, get_addr2_ptr(whdr));
+ if (*sta == NULL) {
+ ret = _SUCCESS; /* return _SUCCESS to drop at sta checking */
+ goto exit;
+ }
+ _rtw_memcpy(rattrib->ra, GetAddr1Ptr(whdr), ETH_ALEN);
+ _rtw_memcpy(rattrib->ta, get_addr2_ptr(whdr), ETH_ALEN);
+ _rtw_memcpy(rattrib->mda, GetAddr1Ptr(whdr), ETH_ALEN);
+ _rtw_memcpy(rattrib->msa, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking AMSDU subframe header */
+ _rtw_memcpy(rattrib->dst, GetAddr1Ptr(whdr), ETH_ALEN);
+ _rtw_memcpy(rattrib->src, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking mesh ctrl field */
+ _rtw_memcpy(rattrib->bssid, get_addr2_ptr(whdr), ETH_ALEN);
+ is_ra_bmc = 1;
+ break;
+ case 3:
+ if (IS_MCAST(GetAddr1Ptr(whdr)))
+ goto exit;
+ *sta = rtw_get_stainfo(stapriv, get_addr2_ptr(whdr));
+ if (*sta == NULL) {
+ ret = _SUCCESS; /* return _SUCCESS to drop at sta checking */
+ goto exit;
+ }
+ _rtw_memcpy(rattrib->ra, GetAddr1Ptr(whdr), ETH_ALEN);
+ _rtw_memcpy(rattrib->ta, get_addr2_ptr(whdr), ETH_ALEN);
+ _rtw_memcpy(rattrib->mda, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking AMSDU subframe header */
+ _rtw_memcpy(rattrib->msa, GetAddr4Ptr(whdr), ETH_ALEN); /* may change after checking AMSDU subframe header */
+ _rtw_memcpy(rattrib->dst, GetAddr3Ptr(whdr), ETH_ALEN); /* may change after checking mesh ctrl field */
+ _rtw_memcpy(rattrib->src, GetAddr4Ptr(whdr), ETH_ALEN); /* may change after checking mesh ctrl field */
+ _rtw_memcpy(rattrib->bssid, get_addr2_ptr(whdr), ETH_ALEN);
+ a4_shift = ETH_ALEN;
+ break;
+ default:
+ goto exit;
+ }
+
+ qc = whdr + WLAN_HDR_A3_LEN + a4_shift;
+ ps = GetPwrMgt(whdr);
+ mps_mode = ps ? (is_ra_bmc || (get_mps_lv(qc)) ? RTW_MESH_PS_DSLEEP : RTW_MESH_PS_LSLEEP) : RTW_MESH_PS_ACTIVE;
+
+ if (ps) {
+ if (!((*sta)->state & WIFI_SLEEP_STATE))
+ stop_sta_xmit(adapter, *sta);
+ } else {
+ if ((*sta)->state & WIFI_SLEEP_STATE)
+ wakeup_sta_to_xmit(adapter, *sta);
+ }
+
+ if (is_ra_bmc)
+ (*sta)->nonpeer_mps = mps_mode;
+ else {
+ (*sta)->peer_mps = mps_mode;
+ if (mps_mode != RTW_MESH_PS_ACTIVE && (*sta)->nonpeer_mps == RTW_MESH_PS_ACTIVE)
+ (*sta)->nonpeer_mps = RTW_MESH_PS_DSLEEP;
+ }
+
+ if (get_frame_sub_type(whdr) & BIT(6)) {
+ /* No data, will not indicate to upper layer, temporily count it here */
+ count_rx_stats(adapter, rframe, *sta);
+ ret = RTW_RX_HANDLED;
+ goto exit;
+ }
+
+ rattrib->mesh_ctrl_present = get_mctrl_present(qc) ? 1 : 0;
+ if (!rattrib->mesh_ctrl_present)
+ goto exit;
+
+ ret = _SUCCESS;
+
+exit:
+ return ret;
+}
+
+int rtw_mesh_rx_data_validate_mctrl(_adapter *adapter, union recv_frame *rframe
+ , const struct rtw_ieee80211s_hdr *mctrl, const u8 *mda, const u8 *msa
+ , u8 *mctrl_len
+ , const u8 **da, const u8 **sa)
+{
+ struct rx_pkt_attrib *rattrib = &rframe->u.hdr.attrib;
+ u8 mlen;
+ u8 ae;
+ int ret = _SUCCESS;
+
+ ae = mctrl->flags & MESH_FLAGS_AE;
+ mlen = ae_to_mesh_ctrl_len[ae];
+ switch (rattrib->to_fr_ds) {
+ case 1:
+ *da = mda;
+ if (ae == MESH_FLAGS_AE_A4)
+ *sa = mctrl->eaddr1;
+ else if (ae == 0)
+ *sa = msa;
+ else
+ ret = _FAIL;
+ break;
+ case 3:
+ if (ae == MESH_FLAGS_AE_A5_A6) {
+ *da = mctrl->eaddr1;
+ *sa = mctrl->eaddr2;
+ } else if (ae == 0) {
+ *da = mda;
+ *sa = msa;
+ } else
+ ret = _FAIL;
+ break;
+ default:
+ ret = _FAIL;
+ }
+
+ if (ret == _FAIL) {
+ #ifdef DBG_RX_DROP_FRAME
+ RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" invalid tfDS:%u AE:%u combination ra="MAC_FMT" ta="MAC_FMT"\n"
+ , FUNC_ADPT_ARG(adapter), rattrib->to_fr_ds, ae, MAC_ARG(rattrib->ra), MAC_ARG(rattrib->ta));
+ #endif
+ *mctrl_len = 0;
+ } else
+ *mctrl_len = mlen;
+
+ return ret;
+}
+
+inline int rtw_mesh_rx_validate_mctrl_non_amsdu(_adapter *adapter, union recv_frame *rframe)
+{
+ struct rx_pkt_attrib *rattrib = &rframe->u.hdr.attrib;
+ const u8 *da, *sa;
+ int ret;
+
+ ret = rtw_mesh_rx_data_validate_mctrl(adapter, rframe
+ , (struct rtw_ieee80211s_hdr *)(get_recvframe_data(rframe) + rattrib->hdrlen + rattrib->iv_len)
+ , rattrib->mda, rattrib->msa
+ , &rattrib->mesh_ctrl_len
+ , &da, &sa);
+
+ if (ret == _SUCCESS) {
+ _rtw_memcpy(rattrib->dst, da, ETH_ALEN);
+ _rtw_memcpy(rattrib->src, sa, ETH_ALEN);
+ }
+
+ return ret;
+}
+
+/**
+ * rtw_mesh_rx_nexthop_resolve - lookup next hop; conditionally start path discovery
+ *
+ * @skb: 802.11 frame to be sent
+ * @sdata: network subif the frame will be sent through
+ *
+ * Lookup next hop for given skb and start path discovery if no
+ * forwarding information is found.
+ *
+ * Returns: 0 if the next hop was found and -ENOENT if the frame was queued.
+ * skb is freeed here if no mpath could be allocated.
+ */
+static int rtw_mesh_rx_nexthop_resolve(_adapter *adapter,
+ const u8 *mda, const u8 *msa, u8 *ra)
+{
+ struct rtw_mesh_path *mpath;
+ struct xmit_frame *xframe_to_free = NULL;
+ int err = 0;
+ int ret = _SUCCESS;
+
+ rtw_rcu_read_lock();
+ err = rtw_mesh_nexthop_lookup(adapter, mda, msa, ra);
+ if (!err)
+ goto endlookup;
+
+ /* no nexthop found, start resolving */
+ mpath = rtw_mesh_path_lookup(adapter, mda);
+ if (!mpath) {
+ mpath = rtw_mesh_path_add(adapter, mda);
+ if (IS_ERR(mpath)) {
+ err = PTR_ERR(mpath);
+ ret = _FAIL;
+ goto endlookup;
+ }
+ }
+
+ if (!(mpath->flags & RTW_MESH_PATH_RESOLVING))
+ rtw_mesh_queue_preq(mpath, RTW_PREQ_Q_F_START);
+
+ ret = _FAIL;
+
+endlookup:
+ rtw_rcu_read_unlock();
+ return ret;
+}
+
+#define RTW_MESH_DECACHE_BMC 1
+#define RTW_MESH_DECACHE_UC 0
+
+#define RTW_MESH_FORWARD_MDA_SELF_COND 1
+int rtw_mesh_rx_msdu_act_check(union recv_frame *rframe
+ , const u8 *mda, const u8 *msa
+ , const u8 *da, const u8 *sa
+ , struct rtw_ieee80211s_hdr *mctrl
+ , struct xmit_frame **fwd_frame, _list *b2u_list)
+{
+ _adapter *adapter = rframe->u.hdr.adapter;
+ struct rtw_mesh_cfg *mcfg = &adapter->mesh_cfg;
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct rx_pkt_attrib *rattrib = &rframe->u.hdr.attrib;
+ struct rtw_mesh_path *mppath;
+ u8 is_mda_bmc = IS_MCAST(mda);
+ u8 is_mda_self = !is_mda_bmc && _rtw_memcmp(mda, adapter_mac_addr(adapter), ETH_ALEN);
+ struct xmit_frame *xframe;
+ struct pkt_attrib *xattrib;
+ u8 fwd_ra[ETH_ALEN] = {0};
+ u8 fwd_mpp[ETH_ALEN] = {0}; /* forward to other gate */
+ u32 fwd_mseq;
+ int act = 0;
+ u8 ae_need;
+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
+ bool bmc_need = _TRUE;
+ u8 b2u_num = 0;
+#endif
+
+ /* fwd info lifetime update */
+ #if 0
+ if (!is_mda_self)
+ mDA(A3) fwinfo.lifetime
+ mSA(A4) fwinfo.lifetime
+ Precursor-to-mDA(A2) fwinfo.lifetime
+ #endif
+
+ /* update/create pxoxy info for SA, mSA */
+ if ((mctrl->flags & MESH_FLAGS_AE)
+ && sa != msa && _rtw_memcmp(sa, msa, ETH_ALEN) == _FALSE
+ ) {
+ const u8 *proxied_addr = sa;
+ const u8 *mpp_addr = msa;
+
+ rtw_rcu_read_lock();
+ mppath = rtw_mpp_path_lookup(adapter, proxied_addr);
+ if (!mppath)
+ rtw_mpp_path_add(adapter, proxied_addr, mpp_addr);
+ else {
+ enter_critical_bh(&mppath->state_lock);
+ if (_rtw_memcmp(mppath->mpp, mpp_addr, ETH_ALEN) == _FALSE)
+ _rtw_memcpy(mppath->mpp, mpp_addr, ETH_ALEN);
+ mppath->exp_time = rtw_get_current_time();
+ exit_critical_bh(&mppath->state_lock);
+ }
+ rtw_rcu_read_unlock();
+ }
+
+ /* mSA is self, need no further process */
+ if (_rtw_memcmp(msa, adapter_mac_addr(adapter), ETH_ALEN) == _TRUE)
+ goto exit;
+
+ fwd_mseq = le32_to_cpu(mctrl->seqnum);
+
+ /* check duplicate MSDU from mSA */
+ if (((RTW_MESH_DECACHE_BMC && is_mda_bmc)
+ || (RTW_MESH_DECACHE_UC && !is_mda_bmc))
+ && rtw_mesh_decache(adapter, msa, fwd_mseq)
+ ) {
+ minfo->mshstats.dropped_frames_duplicate++;
+ goto exit;
+ }
+
+ if (is_mda_bmc) {
+ /* mDA is bmc addr */
+ act |= RTW_RX_MSDU_ACT_INDICATE;
+ if (!mcfg->dot11MeshForwarding)
+ goto exit;
+ goto fwd_chk;
+
+ } else if (!is_mda_self) {
+ /* mDA is unicast but not self */
+ if (!mcfg->dot11MeshForwarding) {
+ rtw_mesh_path_error_tx(adapter
+ , adapter->mesh_cfg.element_ttl
+ , mda, 0
+ , WLAN_REASON_MESH_PATH_NOFORWARD
+ , rattrib->ta
+ );
+ #ifdef DBG_RX_DROP_FRAME
+ RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" mDA("MAC_FMT") not self, !dot11MeshForwarding\n"
+ , FUNC_ADPT_ARG(adapter), MAC_ARG(mda));
+ #endif
+ goto exit;
+ }
+
+ if (rtw_mesh_rx_nexthop_resolve(adapter, mda, msa, fwd_ra) != _SUCCESS) {
+ /* mDA is unknown */
+ rtw_mesh_path_error_tx(adapter
+ , adapter->mesh_cfg.element_ttl
+ , mda, 0
+ , WLAN_REASON_MESH_PATH_NOFORWARD
+ , rattrib->ta
+ );
+ #ifdef DBG_RX_DROP_FRAME
+ RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" mDA("MAC_FMT") unknown\n"
+ , FUNC_ADPT_ARG(adapter), MAC_ARG(mda));
+ #endif
+ minfo->mshstats.dropped_frames_no_route++;
+ goto exit;
+
+ } else {
+ /* mDA is known in fwd info */
+ #if 0
+ if (TA is not in precursors)
+ goto exit;
+ #endif
+ goto fwd_chk;
+ }
+
+ } else {
+ /* mDA is self */
+ #if RTW_MESH_FORWARD_MDA_SELF_COND
+ u8 is_da_self = da == mda || _rtw_memcmp(da, adapter_mac_addr(adapter), ETH_ALEN);
+
+ if (is_da_self) {
+ /* DA is self, indicate */
+ act |= RTW_RX_MSDU_ACT_INDICATE;
+ goto exit;
+ }
+
+ /* DA is not self */
+ if (rtw_mesh_nexthop_lookup(adapter, da, msa, fwd_ra) == _SUCCESS) {
+ /* DA is known in fwd info */
+ if (!mcfg->dot11MeshForwarding) {
+ /* path error to? */
+ #ifdef DBG_RX_DROP_FRAME
+ RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" DA("MAC_FMT") not self, !dot11MeshForwarding\n"
+ , FUNC_ADPT_ARG(adapter), MAC_ARG(da));
+ #endif
+ goto exit;
+ }
+ mda = da;
+ goto fwd_chk;
+ }
+
+ rtw_rcu_read_lock();
+ mppath = rtw_mpp_path_lookup(adapter, da);
+ if (mppath && _rtw_memcmp(mppath->mpp, adapter_mac_addr(adapter), ETH_ALEN) == _FALSE) {
+ /* DA is reached by the other gate */
+ if (!mcfg->dot11MeshForwarding) {
+ /* path error to? */
+ #ifdef DBG_RX_DROP_FRAME
+ RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" DA("MAC_FMT") is reached by proxy("MAC_FMT"), !dot11MeshForwarding\n"
+ , FUNC_ADPT_ARG(adapter), MAC_ARG(da), MAC_ARG(mppath->mpp));
+ #endif
+ rtw_rcu_read_unlock();
+ goto exit;
+ }
+ _rtw_memcpy(fwd_mpp, mppath->mpp, ETH_ALEN);
+ mda = fwd_mpp;
+ msa = adapter_mac_addr(adapter);
+ rtw_rcu_read_unlock();
+
+ /* resolve RA */
+ if (rtw_mesh_nexthop_lookup(adapter, mda, msa, fwd_ra) != _SUCCESS) {
+ minfo->mshstats.dropped_frames_no_route++;
+ goto exit;
+ }
+ goto fwd_chk; /* forward to other gate */
+ }
+ rtw_rcu_read_unlock();
+
+ if (!mppath) {
+ /* DA is unknown */
+ #if 0 /* TODO: flags with AE bit */
+ rtw_mesh_path_error_tx(adapter
+ , adapter->mesh_cfg.element_ttl
+ , mda, adapter->mesh_info.last_sn_update
+ , WLAN_REASON_MESH_PATH_NOPROXY
+ , msa
+ );
+ #endif
+ }
+
+ /*
+ * indicate to DS for both cases:
+ * 1.) DA is reached by self
+ * 2.) DA is unknown
+ */
+ #endif /* RTW_MESH_FORWARD_MDA_SELF_COND */
+ act |= RTW_RX_MSDU_ACT_INDICATE;
+ goto exit;
+ }
+
+fwd_chk:
+
+ if (adapter->stapriv.asoc_list_cnt <= 1)
+ goto exit;
+
+ if (mctrl->ttl == 1) {
+ minfo->mshstats.dropped_frames_ttl++;
+ if (!act) {
+ #ifdef DBG_RX_DROP_FRAME
+ RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" ttl reaches 0, not forwarding\n"
+ , FUNC_ADPT_ARG(adapter));
+ #endif
+ }
+ goto exit;
+ }
+
+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
+ _rtw_init_listhead(b2u_list);
+#endif
+
+ ae_need = _rtw_memcmp(da , mda, ETH_ALEN) == _FALSE
+ || _rtw_memcmp(sa , msa, ETH_ALEN) == _FALSE;
+
+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
+ if (is_mda_bmc
+ && rtw_mfwd_b2u_policy_chk(mcfg->b2u_flags_mfwd, mda, rattrib->to_fr_ds == 3)
+ ) {
+ bmc_need = rtw_mesh_data_bmc_to_uc(adapter
+ , da, sa, mda, msa, ae_need, rframe->u.hdr.psta->cmn.mac_addr, mctrl->ttl - 1
+ , b2u_list, &b2u_num, &fwd_mseq);
+ }
+
+ if (bmc_need == _TRUE)
+#endif
+ {
+ xframe = rtw_alloc_xmitframe(&adapter->xmitpriv);
+ if (!xframe) {
+ #ifdef DBG_TX_DROP_FRAME
+ RTW_INFO("DBG_TX_DROP_FRAME "FUNC_ADPT_FMT" rtw_alloc_xmitframe fail\n"
+ , FUNC_ADPT_ARG(adapter));
+ #endif
+ goto exit;
+ }
+
+ xattrib = &xframe->attrib;
+
+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
+ if (b2u_num)
+ xattrib->mb2u = 1;
+ else
+ xattrib->mb2u = 0;
+#endif
+ xattrib->mfwd_ttl = mctrl->ttl - 1;
+ xattrib->mseq = fwd_mseq;
+ _rtw_memcpy(xattrib->dst, da, ETH_ALEN);
+ _rtw_memcpy(xattrib->src, sa, ETH_ALEN);
+ _rtw_memcpy(xattrib->mda, mda, ETH_ALEN);
+ _rtw_memcpy(xattrib->msa, msa, ETH_ALEN);
+ _rtw_memcpy(xattrib->ta, adapter_mac_addr(adapter), ETH_ALEN);
+
+ if (is_mda_bmc) {
+ xattrib->mesh_frame_mode = ae_need ? MESH_BMCAST_PX_DATA : MESH_BMCAST_DATA;
+ _rtw_memcpy(xattrib->ra, mda, ETH_ALEN);
+ } else {
+ xattrib->mesh_frame_mode = ae_need ? MESH_UCAST_PX_DATA : MESH_UCAST_DATA;
+ _rtw_memcpy(xattrib->ra, fwd_ra, ETH_ALEN);
+ }
+
+ *fwd_frame = xframe;
+ }
+
+ act |= RTW_RX_MSDU_ACT_FORWARD;
+ if (is_mda_bmc)
+ minfo->mshstats.fwded_mcast++;
+ else
+ minfo->mshstats.fwded_unicast++;
+ minfo->mshstats.fwded_frames++;
+
+exit:
+ return act;
+}
+
+void dump_mesh_stats(void *sel, _adapter *adapter)
+{
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct rtw_mesh_stats *stats = &minfo->mshstats;
+
+ RTW_PRINT_SEL(sel, "fwd_bmc:%u\n", stats->fwded_mcast);
+ RTW_PRINT_SEL(sel, "fwd_uc:%u\n", stats->fwded_unicast);
+
+ RTW_PRINT_SEL(sel, "drop_ttl:%u\n", stats->dropped_frames_ttl);
+ RTW_PRINT_SEL(sel, "drop_no_route:%u\n", stats->dropped_frames_no_route);
+ RTW_PRINT_SEL(sel, "drop_congestion:%u\n", stats->dropped_frames_congestion);
+ RTW_PRINT_SEL(sel, "drop_dup:%u\n", stats->dropped_frames_duplicate);
+
+ RTW_PRINT_SEL(sel, "mrc_del_qlen:%u\n", stats->mrc_del_qlen);
+}
+#endif /* CONFIG_RTW_MESH */
+
diff --git a/core/mesh/rtw_mesh.h b/core/mesh/rtw_mesh.h
new file mode 100644
index 0000000..3a8a6d7
--- /dev/null
+++ b/core/mesh/rtw_mesh.h
@@ -0,0 +1,506 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTW_MESH_H_
+#define __RTW_MESH_H_
+
+#ifndef CONFIG_AP_MODE
+ #error "CONFIG_RTW_MESH can't be enabled when CONFIG_AP_MODE is not defined\n"
+#endif
+
+#ifndef RTW_MESH_SCAN_RESULT_EXP_MS
+#define RTW_MESH_SCAN_RESULT_EXP_MS (10 * 1000)
+#endif
+#ifndef RTW_MESH_OFFCH_CAND_FIND_INT_MS
+#define RTW_MESH_OFFCH_CAND_FIND_INT_MS (10 * 1000)
+#endif
+#define RTW_MESH_TTL 31
+#define RTW_MESH_PERR_MIN_INT 100
+#define RTW_MESH_DEFAULT_ELEMENT_TTL 31
+#define RTW_MESH_RANN_INTERVAL 5000
+#define RTW_MESH_PATH_TO_ROOT_TIMEOUT 6000
+#define RTW_MESH_DIAM_TRAVERSAL_TIME 50
+#define RTW_MESH_PATH_TIMEOUT 5000
+#define RTW_MESH_PREQ_MIN_INT 10
+#define RTW_MESH_MAX_PREQ_RETRIES 4
+#define RTW_MESH_MIN_DISCOVERY_TIMEOUT (2 * RTW_MESH_DIAM_TRAVERSAL_TIME)
+#define RTW_MESH_ROOT_CONFIRMATION_INTERVAL 2000
+#define RTW_MESH_PATH_REFRESH_TIME 1000
+#define RTW_MESH_ROOT_INTERVAL 5000
+
+#define RTW_MESH_PLINK_UNKNOWN 0
+#define RTW_MESH_PLINK_LISTEN 1
+#define RTW_MESH_PLINK_OPN_SNT 2
+#define RTW_MESH_PLINK_OPN_RCVD 3
+#define RTW_MESH_PLINK_CNF_RCVD 4
+#define RTW_MESH_PLINK_ESTAB 5
+#define RTW_MESH_PLINK_HOLDING 6
+#define RTW_MESH_PLINK_BLOCKED 7
+
+extern const char *_rtw_mesh_plink_str[];
+#define rtw_mesh_plink_str(s) ((s <= RTW_MESH_PLINK_BLOCKED) ? _rtw_mesh_plink_str[s] : _rtw_mesh_plink_str[RTW_MESH_PLINK_UNKNOWN])
+
+#define RTW_MESH_PS_UNKNOWN 0
+#define RTW_MESH_PS_ACTIVE 1
+#define RTW_MESH_PS_LSLEEP 2
+#define RTW_MESH_PS_DSLEEP 3
+
+extern const char *_rtw_mesh_ps_str[];
+#define rtw_mesh_ps_str(mps) ((mps <= RTW_MESH_PS_DSLEEP) ? _rtw_mesh_ps_str[mps] : _rtw_mesh_ps_str[RTW_MESH_PS_UNKNOWN])
+
+#define GET_MESH_CONF_ELE_PATH_SEL_PROTO_ID(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 0, 0, 8)
+#define GET_MESH_CONF_ELE_PATH_SEL_METRIC_ID(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 1, 0, 8)
+#define GET_MESH_CONF_ELE_CONGEST_CTRL_MODE_ID(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 2, 0, 8)
+#define GET_MESH_CONF_ELE_SYNC_METHOD_ID(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 3, 0, 8)
+#define GET_MESH_CONF_ELE_AUTH_PROTO_ID(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 4, 0, 8)
+
+#define GET_MESH_CONF_ELE_MESH_FORMATION(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 5, 0, 8)
+#define GET_MESH_CONF_ELE_CTO_MGATE(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 5, 0, 1)
+#define GET_MESH_CONF_ELE_NUM_OF_PEERINGS(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 5, 1, 6)
+#define GET_MESH_CONF_ELE_CTO_AS(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 5, 7, 1)
+
+#define GET_MESH_CONF_ELE_MESH_CAP(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 0, 8)
+#define GET_MESH_CONF_ELE_ACCEPT_PEERINGS(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 0, 1)
+#define GET_MESH_CONF_ELE_MCCA_SUP(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 1, 1)
+#define GET_MESH_CONF_ELE_MCCA_EN(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 2, 1)
+#define GET_MESH_CONF_ELE_FORWARDING(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 3, 1)
+#define GET_MESH_CONF_ELE_MBCA_EN(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 4, 1)
+#define GET_MESH_CONF_ELE_TBTT_ADJ(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 5, 1)
+#define GET_MESH_CONF_ELE_PS_LEVEL(_iec) LE_BITS_TO_1BYTE(((u8 *)(_iec)) + 6, 6, 1)
+
+#define SET_MESH_CONF_ELE_PATH_SEL_PROTO_ID(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 0, 0, 8, _val)
+#define SET_MESH_CONF_ELE_PATH_SEL_METRIC_ID(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 1, 0, 8, _val)
+#define SET_MESH_CONF_ELE_CONGEST_CTRL_MODE_ID(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 2, 0, 8, _val)
+#define SET_MESH_CONF_ELE_SYNC_METHOD_ID(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 3, 0, 8, _val)
+#define SET_MESH_CONF_ELE_AUTH_PROTO_ID(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 4, 0, 8, _val)
+
+#define SET_MESH_CONF_ELE_CTO_MGATE(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 5, 0, 1, _val)
+#define SET_MESH_CONF_ELE_NUM_OF_PEERINGS(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 5, 1, 6, _val)
+#define SET_MESH_CONF_ELE_CTO_AS(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 5, 7, 1, _val)
+
+#define SET_MESH_CONF_ELE_ACCEPT_PEERINGS(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 0, 1, _val)
+#define SET_MESH_CONF_ELE_MCCA_SUP(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 1, 1, _val)
+#define SET_MESH_CONF_ELE_MCCA_EN(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 2, 1, _val)
+#define SET_MESH_CONF_ELE_FORWARDING(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 3, 1, _val)
+#define SET_MESH_CONF_ELE_MBCA_EN(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 4, 1, _val)
+#define SET_MESH_CONF_ELE_TBTT_ADJ(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 5, 1, _val)
+#define SET_MESH_CONF_ELE_PS_LEVEL(_iec, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_iec)) + 6, 6, 1, _val)
+
+/* Mesh flags */
+#define MESH_FLAGS_AE 0x3 /* mask */
+#define MESH_FLAGS_AE_A4 0x1
+#define MESH_FLAGS_AE_A5_A6 0x2
+
+/* Max number of paths */
+#define RTW_MESH_MAX_PATHS 1024
+
+#define RTW_PREQ_Q_F_START 0x1
+#define RTW_PREQ_Q_F_REFRESH 0x2
+struct rtw_mesh_preq_queue {
+ _list list;
+ u8 dst[ETH_ALEN];
+ u8 flags;
+};
+
+extern const u8 ae_to_mesh_ctrl_len[];
+
+enum mesh_frame_type {
+ MESH_UCAST_DATA = 0x0,
+ MESH_BMCAST_DATA = 0x1,
+ MESH_UCAST_PX_DATA = 0x2,
+ MESH_BMCAST_PX_DATA = 0x3,
+ MESH_MHOP_UCAST_ACT = 0x4,
+ MESH_MHOP_BMCAST_ACT = 0x5,
+};
+
+enum mpath_sel_frame_type {
+ MPATH_PREQ = 0,
+ MPATH_PREP,
+ MPATH_PERR,
+ MPATH_RANN
+};
+
+/**
+ * enum rtw_mesh_deferred_task_flags - mesh deferred tasks
+ *
+ *
+ *
+ * @RTW_MESH_WORK_HOUSEKEEPING: run the periodic mesh housekeeping tasks
+ * @RTW_MESH_WORK_ROOT: the mesh root station needs to send a frame
+ * @RTW_MESH_WORK_DRIFT_ADJUST: time to compensate for clock drift relative to other
+ * mesh nodes
+ * @RTW_MESH_WORK_MBSS_CHANGED: rebuild beacon and notify driver of BSS changes
+ */
+enum rtw_mesh_deferred_task_flags {
+ RTW_MESH_WORK_HOUSEKEEPING,
+ RTW_MESH_WORK_ROOT,
+ RTW_MESH_WORK_DRIFT_ADJUST,
+ RTW_MESH_WORK_MBSS_CHANGED,
+};
+
+#define RTW_MESH_MAX_PEER_CANDIDATES 15 /* aid consideration */
+#define RTW_MESH_MAX_PEER_LINKS 8
+#define RTW_MESH_PEER_LINK_TIMEOUT 20
+
+#define RTW_MESH_PEER_CONF_DISABLED 0 /* special time value means no confirmation ongoing */
+#if CONFIG_RTW_MESH_PEER_BLACKLIST
+#define IS_PEER_CONF_DISABLED(plink) ((plink)->peer_conf_end_time == RTW_MESH_PEER_CONF_DISABLED)
+#define IS_PEER_CONF_TIMEOUT(plink)(!IS_PEER_CONF_DISABLED(plink) && rtw_time_after(rtw_get_current_time(), (plink)->peer_conf_end_time))
+#define SET_PEER_CONF_DISABLED(plink) (plink)->peer_conf_end_time = RTW_MESH_PEER_CONF_DISABLED
+#define SET_PEER_CONF_END_TIME(plink, timeout_ms) \
+ do { \
+ (plink)->peer_conf_end_time = rtw_get_current_time() + rtw_ms_to_systime(timeout_ms); \
+ if ((plink)->peer_conf_end_time == RTW_MESH_PEER_CONF_DISABLED) \
+ (plink)->peer_conf_end_time++; \
+ } while (0)
+#else
+#define IS_PEER_CONF_DISABLED(plink) 1
+#define IS_PEER_CONF_TIMEOUT(plink) 0
+#define SET_PEER_CONF_DISABLED(plink) do {} while (0)
+#define SET_PEER_CONF_END_TIME(plink, timeout_ms) do {} while (0)
+#endif /* CONFIG_RTW_MESH_PEER_BLACKLIST */
+
+#define RTW_MESH_CTO_MGATE_CONF_DISABLED 0 /* special time value means no confirmation ongoing */
+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+#define IS_CTO_MGATE_CONF_DISABLED(plink) ((plink)->cto_mgate_conf_end_time == RTW_MESH_CTO_MGATE_CONF_DISABLED)
+#define IS_CTO_MGATE_CONF_TIMEOUT(plink)(!IS_CTO_MGATE_CONF_DISABLED(plink) && rtw_time_after(rtw_get_current_time(), (plink)->cto_mgate_conf_end_time))
+#define SET_CTO_MGATE_CONF_DISABLED(plink) (plink)->cto_mgate_conf_end_time = RTW_MESH_CTO_MGATE_CONF_DISABLED
+#define SET_CTO_MGATE_CONF_END_TIME(plink, timeout_ms) \
+ do { \
+ (plink)->cto_mgate_conf_end_time = rtw_get_current_time() + rtw_ms_to_systime(timeout_ms); \
+ if ((plink)->cto_mgate_conf_end_time == RTW_MESH_CTO_MGATE_CONF_DISABLED) \
+ (plink)->cto_mgate_conf_end_time++; \
+ } while (0)
+#else
+#define IS_CTO_MGATE_CONF_DISABLED(plink) 1
+#define IS_CTO_MGATE_CONF_TIMEOUT(plink) 0
+#define SET_CTO_MGATE_CONF_DISABLED(plink) do {} while (0)
+#define SET_CTO_MGATE_CONF_END_TIME(plink, timeout_ms) do {} while (0)
+#endif /* CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST */
+
+struct mesh_plink_ent {
+ u8 valid;
+ u8 addr[ETH_ALEN];
+ u8 plink_state;
+
+#ifdef CONFIG_RTW_MESH_AEK
+ u8 aek_valid;
+ u8 aek[32];
+#endif
+
+ u16 llid;
+ u16 plid;
+#ifndef CONFIG_RTW_MESH_DRIVER_AID
+ u16 aid; /* aid assigned from upper layer */
+#endif
+ u16 peer_aid; /* aid assigned from peer */
+
+ u8 chosen_pmk[16];
+
+#ifdef CONFIG_RTW_MESH_AEK
+ u8 sel_pcs[4];
+ u8 l_nonce[32];
+ u8 p_nonce[32];
+#endif
+
+#ifdef CONFIG_RTW_MESH_DRIVER_AID
+ u8 *tx_conf_ies;
+ u16 tx_conf_ies_len;
+#endif
+ u8 *rx_conf_ies;
+ u16 rx_conf_ies_len;
+
+ struct wlan_network *scanned;
+
+#if CONFIG_RTW_MESH_PEER_BLACKLIST
+ systime peer_conf_end_time;
+#endif
+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+ systime cto_mgate_conf_end_time;
+#endif
+};
+
+#ifdef CONFIG_RTW_MESH_AEK
+#define MESH_PLINK_AEK_VALID(ent) ent->aek_valid
+#else
+#define MESH_PLINK_AEK_VALID(ent) 0
+#endif
+
+struct mesh_plink_pool {
+ _lock lock;
+ u8 num; /* current ent being used */
+ struct mesh_plink_ent ent[RTW_MESH_MAX_PEER_CANDIDATES];
+
+#if CONFIG_RTW_MESH_PEER_BLACKLIST
+ _queue peer_blacklist;
+#endif
+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+ _queue cto_mgate_blacklist;
+#endif
+};
+
+#define RTW_MESH_PEER_CONF_TIMEOUT_MS (20 * 1000)
+#define RTW_MESH_PEER_BLACKLIST_TIMEOUT_MS (20 * 1000)
+#define RTW_MESH_CTO_MGATE_CONF_TIMEOUT_MS (20 * 1000)
+#define RTW_MESH_CTO_MGATE_BLACKLIST_TIMEOUT_MS (20 * 1000)
+
+struct mesh_peer_sel_policy {
+ u32 scanr_exp_ms;
+
+#if CONFIG_RTW_MESH_OFFCH_CAND
+ u32 offch_find_int_ms; /* 0 means no offch find by driver */
+#endif
+
+#if CONFIG_RTW_MESH_PEER_BLACKLIST
+ u32 peer_conf_timeout_ms;
+ u32 peer_blacklist_timeout_ms;
+#endif
+
+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+ u8 cto_mgate_require;
+ u32 cto_mgate_conf_timeout_ms;
+ u32 cto_mgate_blacklist_timeout_ms;
+#endif
+};
+
+/* b2u flags */
+#define RTW_MESH_B2U_ALL BIT0
+#define RTW_MESH_B2U_GA_UCAST BIT1 /* Group addressed unicast frame, forward only */
+#define RTW_MESH_B2U_BCAST BIT2
+#define RTW_MESH_B2U_IP_MCAST BIT3
+
+#define rtw_msrc_b2u_policy_chk(flags, mda) ( \
+ (flags & RTW_MESH_B2U_ALL) \
+ || ((flags & RTW_MESH_B2U_BCAST) && is_broadcast_mac_addr(mda)) \
+ || ((flags & RTW_MESH_B2U_IP_MCAST) && (IP_MCAST_MAC(mda) || ICMPV6_MCAST_MAC(mda))) \
+ )
+
+#define rtw_mfwd_b2u_policy_chk(flags, mda, ucst) ( \
+ (flags & RTW_MESH_B2U_ALL) \
+ || ((flags & RTW_MESH_B2U_GA_UCAST) && ucst) \
+ || ((flags & RTW_MESH_B2U_BCAST) && is_broadcast_mac_addr(mda)) \
+ || ((flags & RTW_MESH_B2U_IP_MCAST) && (IP_MCAST_MAC(mda) || ICMPV6_MCAST_MAC(mda))) \
+ )
+
+struct rtw_mesh_cfg {
+ u8 max_peer_links; /* peering limit */
+ u32 plink_timeout; /* seconds */
+
+ u8 dot11MeshTTL;
+ u8 element_ttl;
+ u32 path_refresh_time;
+ u16 dot11MeshHWMPpreqMinInterval;
+ u16 dot11MeshHWMPnetDiameterTraversalTime;
+ u32 dot11MeshHWMPactivePathTimeout;
+ u8 dot11MeshHWMPmaxPREQretries;
+ u16 min_discovery_timeout;
+ u16 dot11MeshHWMPconfirmationInterval;
+ u16 dot11MeshHWMPperrMinInterval;
+ u8 dot11MeshHWMPRootMode;
+ BOOLEAN dot11MeshForwarding;
+ s32 rssi_threshold; /* in dBm, 0: no specified */
+ u16 dot11MeshHWMPRannInterval;
+ BOOLEAN dot11MeshGateAnnouncementProtocol;
+ u32 dot11MeshHWMPactivePathToRootTimeout;
+ u16 dot11MeshHWMProotInterval;
+ u8 path_gate_timeout_factor;
+
+ struct mesh_peer_sel_policy peer_sel_policy;
+
+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
+ u8 b2u_flags_msrc;
+ u8 b2u_flags_mfwd;
+#endif
+};
+
+struct rtw_mesh_stats {
+ u32 fwded_mcast; /* Mesh forwarded multicast frames */
+ u32 fwded_unicast; /* Mesh forwarded unicast frames */
+ u32 fwded_frames; /* Mesh total forwarded frames */
+ u32 dropped_frames_ttl; /* Not transmitted since mesh_ttl == 0*/
+ u32 dropped_frames_no_route; /* Not transmitted, no route found */
+ u32 dropped_frames_congestion;/* Not forwarded due to congestion */
+ u32 dropped_frames_duplicate;
+
+ u32 mrc_del_qlen; /* MRC entry deleted cause by queue length limit */
+};
+
+struct rtw_mrc;
+
+struct rtw_mesh_info {
+ u8 mesh_id[NDIS_802_11_LENGTH_SSID];
+ size_t mesh_id_len;
+ /* Active Path Selection Protocol Identifier */
+ u8 mesh_pp_id;
+ /* Active Path Selection Metric Identifier */
+ u8 mesh_pm_id;
+ /* Congestion Control Mode Identifier */
+ u8 mesh_cc_id;
+ /* Synchronization Protocol Identifier */
+ u8 mesh_sp_id;
+ /* Authentication Protocol Identifier */
+ u8 mesh_auth_id;
+
+ struct mesh_plink_pool plink_ctl;
+
+ u32 mesh_seqnum;
+ /* MSTA's own hwmp sequence number */
+ u32 sn;
+ systime last_preq;
+ systime last_sn_update;
+ systime next_perr;
+ /* Last used Path Discovery ID */
+ u32 preq_id;
+
+ ATOMIC_T mpaths;
+ struct rtw_mesh_table *mesh_paths;
+ struct rtw_mesh_table *mpp_paths;
+ int mesh_paths_generation;
+ int mpp_paths_generation;
+
+ int num_gates;
+
+ struct rtw_mesh_stats mshstats;
+
+ _queue mpath_tx_queue;
+ u32 mpath_tx_queue_len;
+ struct tasklet_struct mpath_tx_tasklet;
+
+ struct rtw_mrc *mrc;
+
+ _lock mesh_preq_queue_lock;
+ struct rtw_mesh_preq_queue preq_queue;
+ int preq_queue_len;
+};
+
+extern const char *_action_self_protected_str[];
+#define action_self_protected_str(action) ((action < RTW_ACT_SELF_PROTECTED_NUM) ? _action_self_protected_str[action] : _action_self_protected_str[0])
+
+u8 *rtw_set_ie_mesh_id(u8 *buf, u32 *buf_len, const char *mesh_id, u8 id_len);
+u8 *rtw_set_ie_mesh_config(u8 *buf, u32 *buf_len
+ , u8 path_sel_proto, u8 path_sel_metric, u8 congest_ctl_mode, u8 sync_method, u8 auth_proto
+ , u8 num_of_peerings, bool cto_mgate, bool cto_as
+ , bool accept_peerings, bool mcca_sup, bool mcca_en, bool forwarding
+ , bool mbca_en, bool tbtt_adj, bool ps_level);
+
+int rtw_bss_is_same_mbss(WLAN_BSSID_EX *a, WLAN_BSSID_EX *b);
+int rtw_bss_is_candidate_mesh_peer(WLAN_BSSID_EX *self, WLAN_BSSID_EX *target, u8 ch, u8 add_peer);
+
+void rtw_chk_candidate_peer_notify(_adapter *adapter, struct wlan_network *scanned);
+
+void rtw_mesh_peer_status_chk(_adapter *adapter);
+
+#if CONFIG_RTW_MESH_OFFCH_CAND
+u8 rtw_mesh_offch_candidate_accepted(_adapter *adapter);
+u8 rtw_mesh_select_operating_ch(_adapter *adapter);
+#endif
+
+#if CONFIG_RTW_MESH_PEER_BLACKLIST
+int rtw_mesh_peer_blacklist_add(_adapter *adapter, const u8 *addr);
+int rtw_mesh_peer_blacklist_del(_adapter *adapter, const u8 *addr);
+int rtw_mesh_peer_blacklist_search(_adapter *adapter, const u8 *addr);
+void rtw_mesh_peer_blacklist_flush(_adapter *adapter);
+void dump_mesh_peer_blacklist(void *sel, _adapter *adapter);
+void dump_mesh_peer_blacklist_settings(void *sel, _adapter *adapter);
+#endif
+#if CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
+u8 rtw_mesh_cto_mgate_required(_adapter *adapter);
+u8 rtw_mesh_cto_mgate_network_filter(_adapter *adapter, struct wlan_network *scanned);
+int rtw_mesh_cto_mgate_blacklist_add(_adapter *adapter, const u8 *addr);
+int rtw_mesh_cto_mgate_blacklist_del(_adapter *adapter, const u8 *addr);
+int rtw_mesh_cto_mgate_blacklist_search(_adapter *adapter, const u8 *addr);
+void rtw_mesh_cto_mgate_blacklist_flush(_adapter *adapter);
+void dump_mesh_cto_mgate_blacklist(void *sel, _adapter *adapter);
+void dump_mesh_cto_mgate_blacklist_settings(void *sel, _adapter *adapter);
+#endif
+void dump_mesh_peer_sel_policy(void *sel, _adapter *adapter);
+void dump_mesh_networks(void *sel, _adapter *adapter);
+
+int rtw_sae_check_frames(_adapter *adapter, const u8 *buf, u32 len, u8 tx);
+int rtw_mesh_check_frames_tx(_adapter *adapter, const u8 **buf, size_t *len);
+int rtw_mesh_check_frames_rx(_adapter *adapter, const u8 *buf, size_t len);
+
+unsigned int on_action_self_protected(_adapter *adapter, union recv_frame *rframe);
+
+bool rtw_mesh_update_bss_peering_status(_adapter *adapter, WLAN_BSSID_EX *bss);
+bool rtw_mesh_update_bss_formation_info(_adapter *adapter, WLAN_BSSID_EX *bss);
+bool rtw_mesh_update_bss_forwarding_state(_adapter *adapter, WLAN_BSSID_EX *bss);
+
+struct mesh_plink_ent *_rtw_mesh_plink_get(_adapter *adapter, const u8 *hwaddr);
+struct mesh_plink_ent *rtw_mesh_plink_get(_adapter *adapter, const u8 *hwaddr);
+struct mesh_plink_ent *rtw_mesh_plink_get_no_estab_by_idx(_adapter *adapter, u8 idx);
+int _rtw_mesh_plink_add(_adapter *adapter, const u8 *hwaddr);
+int rtw_mesh_plink_add(_adapter *adapter, const u8 *hwaddr);
+int rtw_mesh_plink_set_state(_adapter *adapter, const u8 *hwaddr, u8 state);
+#ifdef CONFIG_RTW_MESH_AEK
+int rtw_mesh_plink_set_aek(_adapter *adapter, const u8 *hwaddr, const u8 *aek);
+#endif
+#if CONFIG_RTW_MESH_PEER_BLACKLIST
+int rtw_mesh_plink_set_peer_conf_timeout(_adapter *adapter, const u8 *hwaddr);
+#endif
+void _rtw_mesh_plink_del_ent(_adapter *adapter, struct mesh_plink_ent *ent);
+int rtw_mesh_plink_del(_adapter *adapter, const u8 *hwaddr);
+void rtw_mesh_plink_ctl_init(_adapter *adapter);
+void rtw_mesh_plink_ctl_deinit(_adapter *adapter);
+void dump_mesh_plink_ctl(void *sel, _adapter *adapter);
+
+int rtw_mesh_peer_establish(_adapter *adapter, struct mesh_plink_ent *plink, struct sta_info *sta);
+void _rtw_mesh_expire_peer_ent(_adapter *adapter, struct mesh_plink_ent *plink);
+void rtw_mesh_expire_peer(_adapter *adapter, const u8 *peer_addr);
+u8 rtw_mesh_ps_annc(_adapter *adapter, u8 ps);
+
+unsigned int on_action_mesh(_adapter *adapter, union recv_frame *rframe);
+
+void rtw_mesh_cfg_init(_adapter *adapter);
+void rtw_mesh_cfg_init_max_peer_links(_adapter *adapter, u8 stack_conf);
+void rtw_mesh_cfg_init_plink_timeout(_adapter *adapter, u32 stack_conf);
+void rtw_mesh_init_mesh_info(_adapter *adapter);
+void rtw_mesh_deinit_mesh_info(_adapter *adapter);
+
+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
+void dump_mesh_b2u_flags(void *sel, _adapter *adapter);
+#endif
+
+int rtw_mesh_addr_resolve(_adapter *adapter, struct xmit_frame *xframe, _pkt *pkt, _list *b2u_list);
+
+s8 rtw_mesh_tx_set_whdr_mctrl_len(u8 mesh_frame_mode, struct pkt_attrib *attrib);
+void rtw_mesh_tx_build_mctrl(_adapter *adapter, struct pkt_attrib *attrib, u8 *buf);
+u8 rtw_mesh_tx_build_whdr(_adapter *adapter, struct pkt_attrib *attrib
+ , u16 *fctrl, struct rtw_ieee80211_hdr *whdr);
+
+int rtw_mesh_rx_data_validate_hdr(_adapter *adapter, union recv_frame *rframe, struct sta_info **sta);
+int rtw_mesh_rx_data_validate_mctrl(_adapter *adapter, union recv_frame *rframe
+ , const struct rtw_ieee80211s_hdr *mctrl, const u8 *mda, const u8 *msa
+ , u8 *mctrl_len, const u8 **da, const u8 **sa);
+int rtw_mesh_rx_validate_mctrl_non_amsdu(_adapter *adapter, union recv_frame *rframe);
+
+int rtw_mesh_rx_msdu_act_check(union recv_frame *rframe
+ , const u8 *mda, const u8 *msa
+ , const u8 *da, const u8 *sa
+ , struct rtw_ieee80211s_hdr *mctrl
+ , struct xmit_frame **fwd_frame, _list *b2u_list);
+
+void dump_mesh_stats(void *sel, _adapter *adapter);
+
+#if defined(PLATFORM_LINUX) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 32))
+#define rtw_lockdep_assert_held(l) lockdep_assert_held(l)
+#define rtw_lockdep_is_held(l) lockdep_is_held(l)
+#else
+#error "TBD\n"
+#endif
+
+#include "rtw_mesh_pathtbl.h"
+#include "rtw_mesh_hwmp.h"
+#endif /* __RTW_MESH_H_ */
+
diff --git a/core/mesh/rtw_mesh_hwmp.c b/core/mesh/rtw_mesh_hwmp.c
new file mode 100644
index 0000000..bfde360
--- /dev/null
+++ b/core/mesh/rtw_mesh_hwmp.c
@@ -0,0 +1,1570 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTW_HWMP_C_
+
+#ifdef CONFIG_RTW_MESH
+#include
+#include
+
+#define RTW_TEST_FRAME_LEN 8192
+#define RTW_MAX_METRIC 0xffffffff
+#define RTW_ARITH_SHIFT 8
+#define RTW_LINK_FAIL_THRESH 95
+#define RTW_MAX_PREQ_QUEUE_LEN 64
+#define RTW_ATLM_REQ_CYCLE 1000
+
+#define rtw_ilog2(n) \
+( \
+ (n) < 2 ? 0 : \
+ (n) & (1ULL << 63) ? 63 : \
+ (n) & (1ULL << 62) ? 62 : \
+ (n) & (1ULL << 61) ? 61 : \
+ (n) & (1ULL << 60) ? 60 : \
+ (n) & (1ULL << 59) ? 59 : \
+ (n) & (1ULL << 58) ? 58 : \
+ (n) & (1ULL << 57) ? 57 : \
+ (n) & (1ULL << 56) ? 56 : \
+ (n) & (1ULL << 55) ? 55 : \
+ (n) & (1ULL << 54) ? 54 : \
+ (n) & (1ULL << 53) ? 53 : \
+ (n) & (1ULL << 52) ? 52 : \
+ (n) & (1ULL << 51) ? 51 : \
+ (n) & (1ULL << 50) ? 50 : \
+ (n) & (1ULL << 49) ? 49 : \
+ (n) & (1ULL << 48) ? 48 : \
+ (n) & (1ULL << 47) ? 47 : \
+ (n) & (1ULL << 46) ? 46 : \
+ (n) & (1ULL << 45) ? 45 : \
+ (n) & (1ULL << 44) ? 44 : \
+ (n) & (1ULL << 43) ? 43 : \
+ (n) & (1ULL << 42) ? 42 : \
+ (n) & (1ULL << 41) ? 41 : \
+ (n) & (1ULL << 40) ? 40 : \
+ (n) & (1ULL << 39) ? 39 : \
+ (n) & (1ULL << 38) ? 38 : \
+ (n) & (1ULL << 37) ? 37 : \
+ (n) & (1ULL << 36) ? 36 : \
+ (n) & (1ULL << 35) ? 35 : \
+ (n) & (1ULL << 34) ? 34 : \
+ (n) & (1ULL << 33) ? 33 : \
+ (n) & (1ULL << 32) ? 32 : \
+ (n) & (1ULL << 31) ? 31 : \
+ (n) & (1ULL << 30) ? 30 : \
+ (n) & (1ULL << 29) ? 29 : \
+ (n) & (1ULL << 28) ? 28 : \
+ (n) & (1ULL << 27) ? 27 : \
+ (n) & (1ULL << 26) ? 26 : \
+ (n) & (1ULL << 25) ? 25 : \
+ (n) & (1ULL << 24) ? 24 : \
+ (n) & (1ULL << 23) ? 23 : \
+ (n) & (1ULL << 22) ? 22 : \
+ (n) & (1ULL << 21) ? 21 : \
+ (n) & (1ULL << 20) ? 20 : \
+ (n) & (1ULL << 19) ? 19 : \
+ (n) & (1ULL << 18) ? 18 : \
+ (n) & (1ULL << 17) ? 17 : \
+ (n) & (1ULL << 16) ? 16 : \
+ (n) & (1ULL << 15) ? 15 : \
+ (n) & (1ULL << 14) ? 14 : \
+ (n) & (1ULL << 13) ? 13 : \
+ (n) & (1ULL << 12) ? 12 : \
+ (n) & (1ULL << 11) ? 11 : \
+ (n) & (1ULL << 10) ? 10 : \
+ (n) & (1ULL << 9) ? 9 : \
+ (n) & (1ULL << 8) ? 8 : \
+ (n) & (1ULL << 7) ? 7 : \
+ (n) & (1ULL << 6) ? 6 : \
+ (n) & (1ULL << 5) ? 5 : \
+ (n) & (1ULL << 4) ? 4 : \
+ (n) & (1ULL << 3) ? 3 : \
+ (n) & (1ULL << 2) ? 2 : \
+ 1 \
+)
+
+enum rtw_mpath_frame_type {
+ RTW_MPATH_PREQ = 0,
+ RTW_MPATH_PREP,
+ RTW_MPATH_PERR,
+ RTW_MPATH_RANN
+};
+
+static inline u32 rtw_u32_field_get(const u8 *preq_elem, int shift, BOOLEAN ae)
+{
+ if (ae)
+ shift += 6;
+ return LE_BITS_TO_4BYTE(preq_elem + shift, 0, 32);
+}
+
+static inline u16 rtw_u16_field_get(const u8 *preq_elem, int shift, BOOLEAN ae)
+{
+ if (ae)
+ shift += 6;
+ return LE_BITS_TO_2BYTE(preq_elem + shift, 0, 16);
+}
+
+/* HWMP IE processing macros */
+#define RTW_AE_F (1<<6)
+#define RTW_AE_F_SET(x) (*x & RTW_AE_F)
+#define RTW_PREQ_IE_FLAGS(x) (*(x))
+#define RTW_PREQ_IE_HOPCOUNT(x) (*(x + 1))
+#define RTW_PREQ_IE_TTL(x) (*(x + 2))
+#define RTW_PREQ_IE_PREQ_ID(x) rtw_u32_field_get(x, 3, 0)
+#define RTW_PREQ_IE_ORIG_ADDR(x) (x + 7)
+#define RTW_PREQ_IE_ORIG_SN(x) rtw_u32_field_get(x, 13, 0)
+#define RTW_PREQ_IE_LIFETIME(x) rtw_u32_field_get(x, 17, RTW_AE_F_SET(x))
+#define RTW_PREQ_IE_METRIC(x) rtw_u32_field_get(x, 21, RTW_AE_F_SET(x))
+#define RTW_PREQ_IE_TARGET_F(x) (*(RTW_AE_F_SET(x) ? x + 32 : x + 26))
+#define RTW_PREQ_IE_TARGET_ADDR(x) (RTW_AE_F_SET(x) ? x + 33 : x + 27)
+#define RTW_PREQ_IE_TARGET_SN(x) rtw_u32_field_get(x, 33, RTW_AE_F_SET(x))
+
+#define RTW_PREP_IE_FLAGS(x) RTW_PREQ_IE_FLAGS(x)
+#define RTW_PREP_IE_HOPCOUNT(x) RTW_PREQ_IE_HOPCOUNT(x)
+#define RTW_PREP_IE_TTL(x) RTW_PREQ_IE_TTL(x)
+#define RTW_PREP_IE_ORIG_ADDR(x) (RTW_AE_F_SET(x) ? x + 27 : x + 21)
+#define RTW_PREP_IE_ORIG_SN(x) rtw_u32_field_get(x, 27, RTW_AE_F_SET(x))
+#define RTW_PREP_IE_LIFETIME(x) rtw_u32_field_get(x, 13, RTW_AE_F_SET(x))
+#define RTW_PREP_IE_METRIC(x) rtw_u32_field_get(x, 17, RTW_AE_F_SET(x))
+#define RTW_PREP_IE_TARGET_ADDR(x) (x + 3)
+#define RTW_PREP_IE_TARGET_SN(x) rtw_u32_field_get(x, 9, 0)
+
+#define RTW_PERR_IE_TTL(x) (*(x))
+#define RTW_PERR_IE_TARGET_FLAGS(x) (*(x + 2))
+#define RTW_PERR_IE_TARGET_ADDR(x) (x + 3)
+#define RTW_PERR_IE_TARGET_SN(x) rtw_u32_field_get(x, 9, 0)
+#define RTW_PERR_IE_TARGET_RCODE(x) rtw_u16_field_get(x, 13, 0)
+
+#define RTW_TU_TO_SYSTIME(x) (rtw_us_to_systime((x) * 1024))
+#define RTW_TU_TO_EXP_TIME(x) (rtw_get_current_time() + RTW_TU_TO_SYSTIME(x))
+#define RTW_MSEC_TO_TU(x) (x*1000/1024)
+#define RTW_SN_GT(x, y) ((s32)(y - x) < 0)
+#define RTW_SN_LT(x, y) ((s32)(x - y) < 0)
+#define RTW_MAX_SANE_SN_DELTA 32
+
+static inline u32 RTW_SN_DELTA(u32 x, u32 y)
+{
+ return x >= y ? x - y : y - x;
+}
+
+#define rtw_net_traversal_jiffies(adapter) \
+ rtw_ms_to_systime(adapter->mesh_cfg.dot11MeshHWMPnetDiameterTraversalTime)
+#define rtw_default_lifetime(adapter) \
+ RTW_MSEC_TO_TU(adapter->mesh_cfg.dot11MeshHWMPactivePathTimeout)
+#define rtw_min_preq_int_jiff(adapter) \
+ (rtw_ms_to_systime(adapter->mesh_cfg.dot11MeshHWMPpreqMinInterval))
+#define rtw_max_preq_retries(adapter) (adapter->mesh_cfg.dot11MeshHWMPmaxPREQretries)
+#define rtw_disc_timeout_jiff(adapter) \
+ rtw_ms_to_systime(adapter->mesh_cfg.min_discovery_timeout)
+#define rtw_root_path_confirmation_jiffies(adapter) \
+ rtw_ms_to_systime(adapter->mesh_cfg.dot11MeshHWMPconfirmationInterval)
+
+static inline BOOLEAN rtw_ether_addr_equal(const u8 *addr1, const u8 *addr2)
+{
+ return _rtw_memcmp(addr1, addr2, ETH_ALEN);
+}
+
+#ifdef PLATFORM_LINUX
+#define rtw_print_ratelimit() printk_ratelimit()
+#define rtw_mod_timer(ptimer, expires) mod_timer(&(ptimer)->timer, expires)
+#else
+
+#endif
+
+#define RTW_MESH_EWMA_PRECISION 20
+#define RTW_MESH_EWMA_WEIGHT_RCP 8
+#define RTW_TOTAL_PKT_MIN_THRESHOLD 1
+inline void rtw_ewma_err_rate_init(struct rtw_ewma_err_rate *e)
+{
+ e->internal = 0;
+}
+inline unsigned long rtw_ewma_err_rate_read(struct rtw_ewma_err_rate *e)
+{
+ return e->internal >> (RTW_MESH_EWMA_PRECISION);
+}
+inline void rtw_ewma_err_rate_add(struct rtw_ewma_err_rate *e,
+ unsigned long val)
+{
+ unsigned long internal = e->internal;
+ unsigned long weight_rcp = rtw_ilog2(RTW_MESH_EWMA_WEIGHT_RCP);
+ unsigned long precision = RTW_MESH_EWMA_PRECISION;
+
+ (e->internal) = internal ? (((internal << weight_rcp) - internal) +
+ (val << precision)) >> weight_rcp :
+ (val << precision);
+}
+
+static const u8 bcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+
+static int rtw_mesh_path_sel_frame_tx(enum rtw_mpath_frame_type mpath_action, u8 flags,
+ const u8 *originator_addr, u32 originator_sn,
+ u8 target_flags, const u8 *target,
+ u32 target_sn, const u8 *da, u8 hopcount, u8 ttl,
+ u32 lifetime, u32 metric, u32 preq_id,
+ _adapter *adapter)
+{
+ struct xmit_priv *pxmitpriv = &(adapter->xmitpriv);
+ struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
+ struct xmit_frame *pmgntframe = NULL;
+ struct rtw_ieee80211_hdr *pwlanhdr = NULL;
+ struct pkt_attrib *pattrib = NULL;
+ u8 category = RTW_WLAN_CATEGORY_MESH;
+ u8 action = RTW_ACT_MESH_HWMP_PATH_SELECTION;
+ u16 *fctrl = NULL;
+ u8 *pos, ie_len;
+
+
+ pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+ if (pmgntframe == NULL)
+ return -1;
+
+ pattrib = &pmgntframe->attrib;
+ update_mgntframe_attrib(adapter, pattrib);
+ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+ pos = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+ pwlanhdr = (struct rtw_ieee80211_hdr *)pos;
+
+
+ fctrl = &(pwlanhdr->frame_ctl);
+ *(fctrl) = 0;
+
+ _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
+ _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN);
+ _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(adapter), ETH_ALEN);
+
+ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
+ pmlmeext->mgnt_seq++;
+ set_frame_sub_type(pos, WIFI_ACTION);
+
+ pos += sizeof(struct rtw_ieee80211_hdr_3addr);
+ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+ pos = rtw_set_fixed_ie(pos, 1, &(category), &(pattrib->pktlen));
+ pos = rtw_set_fixed_ie(pos, 1, &(action), &(pattrib->pktlen));
+
+ switch (mpath_action) {
+ case RTW_MPATH_PREQ:
+ RTW_HWMP_DBG("sending PREQ to "MAC_FMT"\n", MAC_ARG(target));
+ ie_len = 37;
+ pattrib->pktlen += (ie_len + 2);
+ *pos++ = WLAN_EID_PREQ;
+ break;
+ case RTW_MPATH_PREP:
+ RTW_HWMP_DBG("sending PREP to "MAC_FMT"\n", MAC_ARG(originator_addr));
+ ie_len = 31;
+ pattrib->pktlen += (ie_len + 2);
+ *pos++ = WLAN_EID_PREP;
+ break;
+ case RTW_MPATH_RANN:
+ RTW_HWMP_DBG("sending RANN from "MAC_FMT"\n", MAC_ARG(originator_addr));
+ ie_len = sizeof(struct rtw_ieee80211_rann_ie);
+ pattrib->pktlen += (ie_len + 2);
+ *pos++ = WLAN_EID_RANN;
+ break;
+ default:
+ rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf);
+ rtw_free_xmitframe(pxmitpriv, pmgntframe);
+ return _FAIL;
+ }
+ *pos++ = ie_len;
+ *pos++ = flags;
+ *pos++ = hopcount;
+ *pos++ = ttl;
+ if (mpath_action == RTW_MPATH_PREP) {
+ _rtw_memcpy(pos, target, ETH_ALEN);
+ pos += ETH_ALEN;
+ *(u32 *)pos = cpu_to_le32(target_sn);
+ pos += 4;
+ } else {
+ if (mpath_action == RTW_MPATH_PREQ) {
+ *(u32 *)pos = cpu_to_le32(preq_id);
+ pos += 4;
+ }
+ _rtw_memcpy(pos, originator_addr, ETH_ALEN);
+ pos += ETH_ALEN;
+ *(u32 *)pos = cpu_to_le32(originator_sn);
+ pos += 4;
+ }
+ *(u32 *)pos = cpu_to_le32(lifetime);
+ pos += 4;
+ *(u32 *)pos = cpu_to_le32(metric);
+ pos += 4;
+ if (mpath_action == RTW_MPATH_PREQ) {
+ *pos++ = 1; /* support only 1 destination now */
+ *pos++ = target_flags;
+ _rtw_memcpy(pos, target, ETH_ALEN);
+ pos += ETH_ALEN;
+ *(u32 *)pos = cpu_to_le32(target_sn);
+ pos += 4;
+ } else if (mpath_action == RTW_MPATH_PREP) {
+ _rtw_memcpy(pos, originator_addr, ETH_ALEN);
+ pos += ETH_ALEN;
+ *(u32 *)pos = cpu_to_le32(originator_sn);
+ pos += 4;
+ }
+
+ pattrib->last_txcmdsz = pattrib->pktlen;
+ dump_mgntframe(adapter, pmgntframe);
+ return 0;
+}
+
+int rtw_mesh_path_error_tx(_adapter *adapter,
+ u8 ttl, const u8 *target, u32 target_sn,
+ u16 perr_reason_code, const u8 *ra)
+{
+
+ struct xmit_priv *pxmitpriv = &(adapter->xmitpriv);
+ struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
+ struct xmit_frame *pmgntframe = NULL;
+ struct rtw_ieee80211_hdr *pwlanhdr = NULL;
+ struct pkt_attrib *pattrib = NULL;
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ u8 category = RTW_WLAN_CATEGORY_MESH;
+ u8 action = RTW_ACT_MESH_HWMP_PATH_SELECTION;
+ u8 *pos, ie_len;
+ u16 *fctrl = NULL;
+
+ if (rtw_time_before(rtw_get_current_time(), minfo->next_perr))
+ return -1;
+
+ pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+ if (pmgntframe == NULL)
+ return -1;
+
+ pattrib = &pmgntframe->attrib;
+ update_mgntframe_attrib(adapter, pattrib);
+ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+ pos = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+ pwlanhdr = (struct rtw_ieee80211_hdr *)pos;
+
+ fctrl = &(pwlanhdr->frame_ctl);
+ *(fctrl) = 0;
+
+ _rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN);
+ _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN);
+ _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(adapter), ETH_ALEN);
+
+ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
+ pmlmeext->mgnt_seq++;
+ set_frame_sub_type(pos, WIFI_ACTION);
+
+ pos += sizeof(struct rtw_ieee80211_hdr_3addr);
+ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+ pos = rtw_set_fixed_ie(pos, 1, &(category), &(pattrib->pktlen));
+ pos = rtw_set_fixed_ie(pos, 1, &(action), &(pattrib->pktlen));
+
+ ie_len = 15;
+ pattrib->pktlen += (2 + ie_len);
+ *pos++ = WLAN_EID_PERR;
+ *pos++ = ie_len;
+ /* ttl */
+ *pos++ = ttl;
+ /* The Number of Destinations N */
+ *pos++ = 1;
+ /* Flags format | B7 | B6 | B5:B0 | = | rsvd | AE | rsvd | */
+ *pos = 0;
+ pos++;
+ _rtw_memcpy(pos, target, ETH_ALEN);
+ pos += ETH_ALEN;
+ *(u32 *)pos = cpu_to_le32(target_sn);
+ pos += 4;
+ *(u16 *)pos = cpu_to_le16(perr_reason_code);
+
+ adapter->mesh_info.next_perr = RTW_TU_TO_EXP_TIME(
+ adapter->mesh_cfg.dot11MeshHWMPperrMinInterval);
+ pattrib->last_txcmdsz = pattrib->pktlen;
+ /* Send directly. Rewrite it if deferred tx is needed */
+ dump_mgntframe(adapter, pmgntframe);
+
+ RTW_HWMP_DBG("TX PERR toward "MAC_FMT", ra = "MAC_FMT"\n", MAC_ARG(target), MAC_ARG(ra));
+
+ return 0;
+}
+
+static u32 rtw_get_vht_bitrate(u8 mcs, u8 bw, u8 nss, u8 sgi)
+{
+ static const u32 base[4][10] = {
+ { 6500000,
+ 13000000,
+ 19500000,
+ 26000000,
+ 39000000,
+ 52000000,
+ 58500000,
+ 65000000,
+ 78000000,
+ /* not in the spec, but some devices use this: */
+ 86500000,
+ },
+ { 13500000,
+ 27000000,
+ 40500000,
+ 54000000,
+ 81000000,
+ 108000000,
+ 121500000,
+ 135000000,
+ 162000000,
+ 180000000,
+ },
+ { 29300000,
+ 58500000,
+ 87800000,
+ 117000000,
+ 175500000,
+ 234000000,
+ 263300000,
+ 292500000,
+ 351000000,
+ 390000000,
+ },
+ { 58500000,
+ 117000000,
+ 175500000,
+ 234000000,
+ 351000000,
+ 468000000,
+ 526500000,
+ 585000000,
+ 702000000,
+ 780000000,
+ },
+ };
+ u32 bitrate;
+ int bw_idx;
+
+ if (mcs > 9) {
+ RTW_HWMP_INFO("Invalid mcs = %d\n", mcs);
+ return 0;
+ }
+
+ if (nss > 4 || nss < 1) {
+ RTW_HWMP_INFO("Now only support nss = 1, 2, 3, 4\n");
+ }
+
+ switch (bw) {
+ case CHANNEL_WIDTH_160:
+ bw_idx = 3;
+ break;
+ case CHANNEL_WIDTH_80:
+ bw_idx = 2;
+ break;
+ case CHANNEL_WIDTH_40:
+ bw_idx = 1;
+ break;
+ case CHANNEL_WIDTH_20:
+ bw_idx = 0;
+ break;
+ default:
+ RTW_HWMP_INFO("bw = %d currently not supported\n", bw);
+ return 0;
+ }
+
+ bitrate = base[bw_idx][mcs];
+ bitrate *= nss;
+
+ if (sgi)
+ bitrate = (bitrate / 9) * 10;
+
+ /* do NOT round down here */
+ return (bitrate + 50000) / 100000;
+}
+
+static u32 rtw_get_ht_bitrate(u8 mcs, u8 bw, u8 sgi)
+{
+ int modulation, streams, bitrate;
+
+ /* the formula below does only work for MCS values smaller than 32 */
+ if (mcs >= 32) {
+ RTW_HWMP_INFO("Invalid mcs = %d\n", mcs);
+ return 0;
+ }
+
+ if (bw > 1) {
+ RTW_HWMP_INFO("Now HT only support bw = 0(20Mhz), 1(40Mhz)\n");
+ return 0;
+ }
+
+ modulation = mcs & 7;
+ streams = (mcs >> 3) + 1;
+
+ bitrate = (bw == 1) ? 13500000 : 6500000;
+
+ if (modulation < 4)
+ bitrate *= (modulation + 1);
+ else if (modulation == 4)
+ bitrate *= (modulation + 2);
+ else
+ bitrate *= (modulation + 3);
+
+ bitrate *= streams;
+
+ if (sgi)
+ bitrate = (bitrate / 9) * 10;
+
+ /* do NOT round down here */
+ return (bitrate + 50000) / 100000;
+}
+
+/**
+ * @bw: 0(20Mhz), 1(40Mhz), 2(80Mhz), 3(160Mhz)
+ * @rate_idx: DESC_RATEXXXX & 0x7f
+ * @sgi: DESC_RATEXXXX >> 7
+ * Returns: bitrate in 100kbps
+ */
+static u32 rtw_desc_rate_to_bitrate(u8 bw, u8 rate_idx, u8 sgi)
+{
+ u32 bitrate;
+
+ if (rate_idx <= DESC_RATE54M){
+ u16 ofdm_rate[12] = {10, 20, 55, 110,
+ 60, 90, 120, 180, 240, 360, 480, 540};
+ bitrate = ofdm_rate[rate_idx];
+ } else if ((DESC_RATEMCS0 <= rate_idx) &&
+ (rate_idx <= DESC_RATEMCS31)) {
+ u8 mcs = rate_idx - DESC_RATEMCS0;
+ bitrate = rtw_get_ht_bitrate(mcs, bw, sgi);
+ } else if ((DESC_RATEVHTSS1MCS0 <= rate_idx) &&
+ (rate_idx <= DESC_RATEVHTSS4MCS9)) {
+ u8 mcs = (rate_idx - DESC_RATEVHTSS1MCS0) % 10;
+ u8 nss = ((rate_idx - DESC_RATEVHTSS1MCS0) / 10) + 1;
+ bitrate = rtw_get_vht_bitrate(mcs, bw, nss, sgi);
+ } else {
+ /* 60Ghz ??? */
+ bitrate = 1;
+ }
+
+ return bitrate;
+}
+
+static u32 rtw_airtime_link_metric_get(_adapter *adapter, struct sta_info *sta)
+{
+ struct dm_struct *dm = adapter_to_phydm(adapter);
+ int device_constant = phydm_get_plcp(dm, sta->cmn.mac_id) << RTW_ARITH_SHIFT;
+ u32 test_frame_len = RTW_TEST_FRAME_LEN << RTW_ARITH_SHIFT;
+ u32 s_unit = 1 << RTW_ARITH_SHIFT;
+ u32 err;
+ u16 rate;
+ u32 tx_time, estimated_retx;
+ u64 result;
+ /* The fail_avg should <= 100 here */
+ u32 fail_avg = (u32)rtw_ewma_err_rate_read(&sta->metrics.err_rate);
+
+ if (fail_avg > RTW_LINK_FAIL_THRESH)
+ return RTW_MAX_METRIC;
+
+ rate = sta->metrics.data_rate;
+ /* rate unit is 100Kbps, min rate = 10 */
+ if (rate < 10) {
+ RTW_HWMP_INFO("rate = %d\n", rate);
+ return RTW_MAX_METRIC;
+ }
+
+ err = (fail_avg << RTW_ARITH_SHIFT) / 100;
+
+ /* test_frame_len*10 to adjust the unit of rate(100kbps/unit) */
+ tx_time = (device_constant + 10 * test_frame_len / rate);
+ estimated_retx = ((1 << (2 * RTW_ARITH_SHIFT)) / (s_unit - err));
+ result = (tx_time * estimated_retx) >> (2 * RTW_ARITH_SHIFT);
+ /* Convert us to 0.01 TU(10.24us). x/10.24 = x*100/1024 */
+ result = (result * 100) >> 10;
+
+ return (u32)result;
+}
+
+void rtw_ieee80211s_update_metric(_adapter *adapter, u8 mac_id,
+ u8 per, u8 rate,
+ u8 bw, u8 total_pkt)
+{
+ struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+ struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
+ struct sta_info *sta;
+ u8 rate_idx;
+ u8 sgi;
+
+ sta = macid_ctl->sta[mac_id];
+ if (!sta)
+ return;
+
+ /* if RA, use reported rate */
+ if (adapter->fix_rate == 0xff) {
+ rate_idx = rate & 0x7f;
+ sgi = rate >> 7;
+ } else {
+ rate_idx = adapter->fix_rate & 0x7f;
+ sgi = adapter->fix_rate >> 7;
+ }
+ sta->metrics.data_rate = rtw_desc_rate_to_bitrate(bw, rate_idx, sgi);
+
+ if (total_pkt < RTW_TOTAL_PKT_MIN_THRESHOLD)
+ return;
+
+ /* TBD: sta->metrics.overhead = phydm_get_plcp(void *dm_void, u16 macid); */
+ sta->metrics.total_pkt = total_pkt;
+
+ rtw_ewma_err_rate_add(&sta->metrics.err_rate, per);
+ if (rtw_ewma_err_rate_read(&sta->metrics.err_rate) >
+ RTW_LINK_FAIL_THRESH)
+ rtw_mesh_plink_broken(sta);
+}
+
+static void rtw_hwmp_preq_frame_process(_adapter *adapter,
+ struct rtw_ieee80211_hdr_3addr *mgmt,
+ const u8 *preq_elem, u32 originator_metric)
+{
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg;
+ struct rtw_mesh_path *path = NULL;
+ const u8 *target_addr, *originator_addr;
+ const u8 *da;
+ u8 target_flags, ttl, flags, to_gate_ask = 0;
+ u32 originator_sn, target_sn, lifetime, target_metric = 0;
+ BOOLEAN reply = _FALSE;
+ BOOLEAN forward = _TRUE;
+ BOOLEAN preq_is_gate;
+
+ /* Update target SN, if present */
+ target_addr = RTW_PREQ_IE_TARGET_ADDR(preq_elem);
+ originator_addr = RTW_PREQ_IE_ORIG_ADDR(preq_elem);
+ target_sn = RTW_PREQ_IE_TARGET_SN(preq_elem);
+ originator_sn = RTW_PREQ_IE_ORIG_SN(preq_elem);
+ target_flags = RTW_PREQ_IE_TARGET_F(preq_elem);
+ /* PREQ gate announcements */
+ flags = RTW_PREQ_IE_FLAGS(preq_elem);
+ preq_is_gate = !!(flags & RTW_IEEE80211_PREQ_IS_GATE_FLAG);
+
+ RTW_HWMP_DBG("received PREQ from "MAC_FMT"\n", MAC_ARG(originator_addr));
+
+ if (rtw_ether_addr_equal(target_addr, adapter_mac_addr(adapter))) {
+ RTW_HWMP_DBG("PREQ is for us\n");
+#ifdef CONFIG_RTW_MESH_ON_DMD_GANN
+ rtw_rcu_read_lock();
+ path = rtw_mesh_path_lookup(adapter, originator_addr);
+ if (path) {
+ if (preq_is_gate)
+ rtw_mesh_path_add_gate(path);
+ else if (path->is_gate) {
+ enter_critical_bh(&path->state_lock);
+ rtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path);
+ exit_critical_bh(&path->state_lock);
+ }
+ }
+ path = NULL;
+ rtw_rcu_read_unlock();
+#endif
+ forward = _FALSE;
+ reply = _TRUE;
+ to_gate_ask = 1;
+ target_metric = 0;
+ if (rtw_time_after(rtw_get_current_time(), minfo->last_sn_update +
+ rtw_net_traversal_jiffies(adapter)) ||
+ rtw_time_before(rtw_get_current_time(), minfo->last_sn_update)) {
+ ++minfo->sn;
+ minfo->last_sn_update = rtw_get_current_time();
+ }
+ target_sn = minfo->sn;
+ } else if (is_broadcast_mac_addr(target_addr) &&
+ (target_flags & RTW_IEEE80211_PREQ_TO_FLAG)) {
+ rtw_rcu_read_lock();
+ path = rtw_mesh_path_lookup(adapter, originator_addr);
+ if (path) {
+ if (flags & RTW_IEEE80211_PREQ_PROACTIVE_PREP_FLAG) {
+ reply = _TRUE;
+ target_addr = adapter_mac_addr(adapter);
+ target_sn = ++minfo->sn;
+ target_metric = 0;
+ minfo->last_sn_update = rtw_get_current_time();
+ }
+
+ if (preq_is_gate) {
+ lifetime = RTW_PREQ_IE_LIFETIME(preq_elem);
+ path->gate_ann_int = lifetime;
+ path->gate_asked = false;
+ rtw_mesh_path_add_gate(path);
+ } else if (path->is_gate) {
+ enter_critical_bh(&path->state_lock);
+ rtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path);
+ exit_critical_bh(&path->state_lock);
+ }
+ }
+ rtw_rcu_read_unlock();
+ } else {
+ rtw_rcu_read_lock();
+#ifdef CONFIG_RTW_MESH_ON_DMD_GANN
+ path = rtw_mesh_path_lookup(adapter, originator_addr);
+ if (path) {
+ if (preq_is_gate)
+ rtw_mesh_path_add_gate(path);
+ else if (path->is_gate) {
+ enter_critical_bh(&path->state_lock);
+ rtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path);
+ exit_critical_bh(&path->state_lock);
+ }
+ }
+ path = NULL;
+#endif
+ path = rtw_mesh_path_lookup(adapter, target_addr);
+ if (path) {
+ if ((!(path->flags & RTW_MESH_PATH_SN_VALID)) ||
+ RTW_SN_LT(path->sn, target_sn)) {
+ path->sn = target_sn;
+ path->flags |= RTW_MESH_PATH_SN_VALID;
+ } else if ((!(target_flags & RTW_IEEE80211_PREQ_TO_FLAG)) &&
+ (path->flags & RTW_MESH_PATH_ACTIVE)) {
+ reply = _TRUE;
+ target_metric = path->metric;
+ target_sn = path->sn;
+ /* Case E2 of sec 13.10.9.3 IEEE 802.11-2012*/
+ target_flags |= RTW_IEEE80211_PREQ_TO_FLAG;
+ }
+ }
+ rtw_rcu_read_unlock();
+ }
+
+ if (reply) {
+ lifetime = RTW_PREQ_IE_LIFETIME(preq_elem);
+ ttl = mshcfg->element_ttl;
+ if (ttl != 0 && !to_gate_ask) {
+ RTW_HWMP_DBG("replying to the PREQ\n");
+ rtw_mesh_path_sel_frame_tx(RTW_MPATH_PREP, 0, originator_addr,
+ originator_sn, 0, target_addr,
+ target_sn, mgmt->addr2, 0, ttl,
+ lifetime, target_metric, 0,
+ adapter);
+ } else if (ttl != 0 && to_gate_ask) {
+ RTW_HWMP_DBG("replying to the PREQ (PREQ for us)\n");
+ if (mshcfg->dot11MeshGateAnnouncementProtocol) {
+ /* BIT 7 is used to identify the prep is from mesh gate */
+ to_gate_ask = RTW_IEEE80211_PREQ_IS_GATE_FLAG | BIT(7);
+ } else {
+ to_gate_ask = 0;
+ }
+
+ rtw_mesh_path_sel_frame_tx(RTW_MPATH_PREP, to_gate_ask, originator_addr,
+ originator_sn, 0, target_addr,
+ target_sn, mgmt->addr2, 0, ttl,
+ lifetime, target_metric, 0,
+ adapter);
+ } else {
+ minfo->mshstats.dropped_frames_ttl++;
+ }
+ }
+
+ if (forward && mshcfg->dot11MeshForwarding) {
+ u32 preq_id;
+ u8 hopcount;
+
+ ttl = RTW_PREQ_IE_TTL(preq_elem);
+ lifetime = RTW_PREQ_IE_LIFETIME(preq_elem);
+ if (ttl <= 1) {
+ minfo->mshstats.dropped_frames_ttl++;
+ return;
+ }
+ RTW_HWMP_DBG("forwarding the PREQ from "MAC_FMT"\n", MAC_ARG(originator_addr));
+ --ttl;
+ preq_id = RTW_PREQ_IE_PREQ_ID(preq_elem);
+ hopcount = RTW_PREQ_IE_HOPCOUNT(preq_elem) + 1;
+ da = (path && path->is_root) ?
+ path->rann_snd_addr : bcast_addr;
+
+ if (flags & RTW_IEEE80211_PREQ_PROACTIVE_PREP_FLAG) {
+ target_addr = RTW_PREQ_IE_TARGET_ADDR(preq_elem);
+ target_sn = RTW_PREQ_IE_TARGET_SN(preq_elem);
+ }
+
+ rtw_mesh_path_sel_frame_tx(RTW_MPATH_PREQ, flags, originator_addr,
+ originator_sn, target_flags, target_addr,
+ target_sn, da, hopcount, ttl, lifetime,
+ originator_metric, preq_id, adapter);
+ if (!is_multicast_mac_addr(da))
+ minfo->mshstats.fwded_unicast++;
+ else
+ minfo->mshstats.fwded_mcast++;
+ minfo->mshstats.fwded_frames++;
+ }
+}
+
+static inline struct sta_info *
+rtw_next_hop_deref_protected(struct rtw_mesh_path *path)
+{
+ return rtw_rcu_dereference_protected(path->next_hop,
+ rtw_lockdep_is_held(&path->state_lock));
+}
+
+static void rtw_hwmp_prep_frame_process(_adapter *adapter,
+ struct rtw_ieee80211_hdr_3addr *mgmt,
+ const u8 *prep_elem, u32 metric)
+{
+ struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg;
+ struct rtw_mesh_stats *mshstats = &adapter->mesh_info.mshstats;
+ struct rtw_mesh_path *path;
+ const u8 *target_addr, *originator_addr;
+ u8 ttl, hopcount, flags;
+ u8 next_hop[ETH_ALEN];
+ u32 target_sn, originator_sn, lifetime;
+
+ RTW_HWMP_DBG("received PREP from "MAC_FMT"\n",
+ MAC_ARG(RTW_PREP_IE_TARGET_ADDR(prep_elem)));
+
+ originator_addr = RTW_PREP_IE_ORIG_ADDR(prep_elem);
+ if (rtw_ether_addr_equal(originator_addr, adapter_mac_addr(adapter))) {
+ /* destination, no forwarding required */
+ rtw_rcu_read_lock();
+ target_addr = RTW_PREP_IE_TARGET_ADDR(prep_elem);
+ path = rtw_mesh_path_lookup(adapter, target_addr);
+ if (path && path->gate_asked) {
+ enter_critical_bh(&path->state_lock);
+ path->gate_asked = false;
+ exit_critical_bh(&path->state_lock);
+ flags = RTW_PREP_IE_FLAGS(prep_elem);
+ if ((flags & BIT(7)) && !(flags & RTW_IEEE80211_PREQ_IS_GATE_FLAG)) {
+ enter_critical_bh(&path->state_lock);
+ rtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path);
+ exit_critical_bh(&path->state_lock);
+ }
+ }
+
+ rtw_rcu_read_unlock();
+ return;
+ }
+
+ if (!mshcfg->dot11MeshForwarding)
+ return;
+
+ ttl = RTW_PREP_IE_TTL(prep_elem);
+ if (ttl <= 1) {
+ mshstats->dropped_frames_ttl++;
+ return;
+ }
+
+ rtw_rcu_read_lock();
+ path = rtw_mesh_path_lookup(adapter, originator_addr);
+ if (path)
+ enter_critical_bh(&path->state_lock);
+ else
+ goto fail;
+ if (!(path->flags & RTW_MESH_PATH_ACTIVE)) {
+ exit_critical_bh(&path->state_lock);
+ goto fail;
+ }
+ _rtw_memcpy(next_hop, rtw_next_hop_deref_protected(path)->cmn.mac_addr, ETH_ALEN);
+ exit_critical_bh(&path->state_lock);
+ --ttl;
+ flags = RTW_PREP_IE_FLAGS(prep_elem);
+ lifetime = RTW_PREP_IE_LIFETIME(prep_elem);
+ hopcount = RTW_PREP_IE_HOPCOUNT(prep_elem) + 1;
+ target_addr = RTW_PREP_IE_TARGET_ADDR(prep_elem);
+ target_sn = RTW_PREP_IE_TARGET_SN(prep_elem);
+ originator_sn = RTW_PREP_IE_ORIG_SN(prep_elem);
+
+ rtw_mesh_path_sel_frame_tx(RTW_MPATH_PREP, flags, originator_addr, originator_sn, 0,
+ target_addr, target_sn, next_hop, hopcount,
+ ttl, lifetime, metric, 0, adapter);
+ rtw_rcu_read_unlock();
+
+ mshstats->fwded_unicast++;
+ mshstats->fwded_frames++;
+ return;
+
+fail:
+ rtw_rcu_read_unlock();
+ mshstats->dropped_frames_no_route++;
+}
+
+static void rtw_hwmp_perr_frame_process(_adapter *adapter,
+ struct rtw_ieee80211_hdr_3addr *mgmt,
+ const u8 *perr_elem)
+{
+ struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg;
+ struct rtw_mesh_stats *mshstats = &adapter->mesh_info.mshstats;
+ struct rtw_mesh_path *path;
+ u8 ttl;
+ const u8 *ta, *target_addr;
+ u32 target_sn;
+ u16 perr_reason_code;
+
+ ta = mgmt->addr2;
+ ttl = RTW_PERR_IE_TTL(perr_elem);
+ if (ttl <= 1) {
+ mshstats->dropped_frames_ttl++;
+ return;
+ }
+ ttl--;
+ target_addr = RTW_PERR_IE_TARGET_ADDR(perr_elem);
+ target_sn = RTW_PERR_IE_TARGET_SN(perr_elem);
+ perr_reason_code = RTW_PERR_IE_TARGET_RCODE(perr_elem);
+
+ RTW_HWMP_DBG("received PERR toward target "MAC_FMT"\n", MAC_ARG(target_addr));
+
+ rtw_rcu_read_lock();
+ path = rtw_mesh_path_lookup(adapter, target_addr);
+ if (path) {
+ struct sta_info *sta;
+
+ enter_critical_bh(&path->state_lock);
+ sta = rtw_next_hop_deref_protected(path);
+ if (path->flags & RTW_MESH_PATH_ACTIVE &&
+ rtw_ether_addr_equal(ta, sta->cmn.mac_addr) &&
+ !(path->flags & RTW_MESH_PATH_FIXED) &&
+ (!(path->flags & RTW_MESH_PATH_SN_VALID) ||
+ RTW_SN_GT(target_sn, path->sn) || target_sn == 0)) {
+ path->flags &= ~RTW_MESH_PATH_ACTIVE;
+ if (target_sn != 0)
+ path->sn = target_sn;
+ else
+ path->sn += 1;
+ exit_critical_bh(&path->state_lock);
+ if (!mshcfg->dot11MeshForwarding)
+ goto endperr;
+ rtw_mesh_path_error_tx(adapter, ttl, target_addr,
+ target_sn, perr_reason_code,
+ bcast_addr);
+ } else
+ exit_critical_bh(&path->state_lock);
+ }
+endperr:
+ rtw_rcu_read_unlock();
+}
+
+static void rtw_hwmp_rann_frame_process(_adapter *adapter,
+ struct rtw_ieee80211_hdr_3addr *mgmt,
+ const struct rtw_ieee80211_rann_ie *rann)
+{
+ struct sta_info *sta;
+ struct sta_priv *pstapriv = &adapter->stapriv;
+ struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg;
+ struct rtw_mesh_stats *mshstats = &adapter->mesh_info.mshstats;
+ struct rtw_mesh_path *path;
+ u8 ttl, flags, hopcount;
+ const u8 *originator_addr;
+ u32 originator_sn, metric, metric_txsta, interval;
+ BOOLEAN root_is_gate;
+
+ ttl = rann->rann_ttl;
+ flags = rann->rann_flags;
+ root_is_gate = !!(flags & RTW_RANN_FLAG_IS_GATE);
+ originator_addr = rann->rann_addr;
+ originator_sn = le32_to_cpu(rann->rann_seq);
+ interval = le32_to_cpu(rann->rann_interval);
+ hopcount = rann->rann_hopcount;
+ hopcount++;
+ metric = le32_to_cpu(rann->rann_metric);
+
+ /* Ignore our own RANNs */
+ if (rtw_ether_addr_equal(originator_addr, adapter_mac_addr(adapter)))
+ return;
+
+ RTW_HWMP_DBG("received RANN from "MAC_FMT" via neighbour "MAC_FMT" (is_gate=%d)\n",
+ MAC_ARG(originator_addr), MAC_ARG(mgmt->addr2), root_is_gate);
+
+ rtw_rcu_read_lock();
+ sta = rtw_get_stainfo(pstapriv, mgmt->addr2);
+ if (!sta) {
+ rtw_rcu_read_unlock();
+ return;
+ }
+
+ metric_txsta = rtw_airtime_link_metric_get(adapter, sta);
+
+ path = rtw_mesh_path_lookup(adapter, originator_addr);
+ if (!path) {
+ path = rtw_mesh_path_add(adapter, originator_addr);
+ if (IS_ERR(path)) {
+ rtw_rcu_read_unlock();
+ mshstats->dropped_frames_no_route++;
+ return;
+ }
+ }
+
+ if (!(RTW_SN_LT(path->sn, originator_sn)) &&
+ !(path->sn == originator_sn && metric < path->rann_metric)) {
+ rtw_rcu_read_unlock();
+ return;
+ }
+
+ if ((!(path->flags & (RTW_MESH_PATH_ACTIVE | RTW_MESH_PATH_RESOLVING)) ||
+ (rtw_time_after(rtw_get_current_time(), path->last_preq_to_root +
+ rtw_root_path_confirmation_jiffies(adapter)) ||
+ rtw_time_before(rtw_get_current_time(), path->last_preq_to_root))) &&
+ !(path->flags & RTW_MESH_PATH_FIXED) && (ttl != 0)) {
+ RTW_HWMP_DBG("time to refresh root path "MAC_FMT"\n",
+ MAC_ARG(originator_addr));
+ rtw_mesh_queue_preq(path, RTW_PREQ_Q_F_START | RTW_PREQ_Q_F_REFRESH);
+ path->last_preq_to_root = rtw_get_current_time();
+ }
+
+ path->sn = originator_sn;
+ path->rann_metric = metric + metric_txsta;
+ path->is_root = _TRUE;
+ /* Recording RANNs sender address to send individually
+ * addressed PREQs destined for root mesh STA */
+ _rtw_memcpy(path->rann_snd_addr, mgmt->addr2, ETH_ALEN);
+
+ if (root_is_gate) {
+ path->gate_ann_int = interval;
+ path->gate_asked = false;
+ rtw_mesh_path_add_gate(path);
+ } else if (path->is_gate) {
+ enter_critical_bh(&path->state_lock);
+ rtw_mesh_gate_del(adapter->mesh_info.mesh_paths, path);
+ exit_critical_bh(&path->state_lock);
+ }
+
+ if (ttl <= 1) {
+ mshstats->dropped_frames_ttl++;
+ rtw_rcu_read_unlock();
+ return;
+ }
+ ttl--;
+
+ if (mshcfg->dot11MeshForwarding) {
+ rtw_mesh_path_sel_frame_tx(RTW_MPATH_RANN, flags, originator_addr,
+ originator_sn, 0, NULL, 0, bcast_addr,
+ hopcount, ttl, interval,
+ metric + metric_txsta, 0, adapter);
+ }
+
+ rtw_rcu_read_unlock();
+}
+
+static u32 rtw_hwmp_route_info_get(_adapter *adapter,
+ struct rtw_ieee80211_hdr_3addr *mgmt,
+ const u8 *hwmp_ie, enum rtw_mpath_frame_type action)
+{
+ struct rtw_mesh_path *path;
+ struct sta_priv *pstapriv = &adapter->stapriv;
+ struct sta_info *sta;
+ BOOLEAN fresh_info;
+ const u8 *originator_addr, *ta;
+ u32 originator_sn, originator_metric;
+ unsigned long originator_lifetime, exp_time;
+ u32 last_hop_metric, new_metric;
+ BOOLEAN process = _TRUE;
+
+ rtw_rcu_read_lock();
+ sta = rtw_get_stainfo(pstapriv, mgmt->addr2);
+ if (!sta) {
+ rtw_rcu_read_unlock();
+ return 0;
+ }
+
+ last_hop_metric = rtw_airtime_link_metric_get(adapter, sta);
+ /* Update and check originator routing info */
+ fresh_info = _TRUE;
+
+ switch (action) {
+ case RTW_MPATH_PREQ:
+ originator_addr = RTW_PREQ_IE_ORIG_ADDR(hwmp_ie);
+ originator_sn = RTW_PREQ_IE_ORIG_SN(hwmp_ie);
+ originator_lifetime = RTW_PREQ_IE_LIFETIME(hwmp_ie);
+ originator_metric = RTW_PREQ_IE_METRIC(hwmp_ie);
+ break;
+ case RTW_MPATH_PREP:
+ /* Note: For coding, the naming is not consist with spec */
+ originator_addr = RTW_PREP_IE_TARGET_ADDR(hwmp_ie);
+ originator_sn = RTW_PREP_IE_TARGET_SN(hwmp_ie);
+ originator_lifetime = RTW_PREP_IE_LIFETIME(hwmp_ie);
+ originator_metric = RTW_PREP_IE_METRIC(hwmp_ie);
+ break;
+ default:
+ rtw_rcu_read_unlock();
+ return 0;
+ }
+ new_metric = originator_metric + last_hop_metric;
+ if (new_metric < originator_metric)
+ new_metric = RTW_MAX_METRIC;
+ exp_time = RTW_TU_TO_EXP_TIME(originator_lifetime);
+
+ if (rtw_ether_addr_equal(originator_addr, adapter_mac_addr(adapter))) {
+ process = _FALSE;
+ fresh_info = _FALSE;
+ } else {
+ path = rtw_mesh_path_lookup(adapter, originator_addr);
+ if (path) {
+ enter_critical_bh(&path->state_lock);
+ if (path->flags & RTW_MESH_PATH_FIXED)
+ fresh_info = _FALSE;
+ else if ((path->flags & RTW_MESH_PATH_ACTIVE) &&
+ (path->flags & RTW_MESH_PATH_SN_VALID)) {
+ if (RTW_SN_GT(path->sn, originator_sn) ||
+ (path->sn == originator_sn &&
+ new_metric >= path->metric)) {
+ process = _FALSE;
+ fresh_info = _FALSE;
+ }
+ } else if (!(path->flags & RTW_MESH_PATH_ACTIVE)) {
+ BOOLEAN have_sn, newer_sn, bounced;
+
+ have_sn = path->flags & RTW_MESH_PATH_SN_VALID;
+ newer_sn = have_sn && RTW_SN_GT(originator_sn, path->sn);
+ bounced = have_sn &&
+ (RTW_SN_DELTA(originator_sn, path->sn) >
+ RTW_MAX_SANE_SN_DELTA);
+
+ if (!have_sn || newer_sn) {
+ } else if (bounced) {
+ } else {
+ process = _FALSE;
+ fresh_info = _FALSE;
+ }
+ }
+ } else {
+ path = rtw_mesh_path_add(adapter, originator_addr);
+ if (IS_ERR(path)) {
+ rtw_rcu_read_unlock();
+ return 0;
+ }
+ enter_critical_bh(&path->state_lock);
+ }
+
+ if (fresh_info) {
+ rtw_mesh_path_assign_nexthop(path, sta);
+ path->flags |= RTW_MESH_PATH_SN_VALID;
+ path->metric = new_metric;
+ path->sn = originator_sn;
+ path->exp_time = rtw_time_after(path->exp_time, exp_time)
+ ? path->exp_time : exp_time;
+ rtw_mesh_path_activate(path);
+ exit_critical_bh(&path->state_lock);
+ rtw_mesh_path_tx_pending(path);
+ } else
+ exit_critical_bh(&path->state_lock);
+ }
+
+ /* Update and check transmitter routing info */
+ ta = mgmt->addr2;
+ if (rtw_ether_addr_equal(originator_addr, ta))
+ fresh_info = _FALSE;
+ else {
+ fresh_info = _TRUE;
+
+ path = rtw_mesh_path_lookup(adapter, ta);
+ if (path) {
+ enter_critical_bh(&path->state_lock);
+ if ((path->flags & RTW_MESH_PATH_FIXED) ||
+ ((path->flags & RTW_MESH_PATH_ACTIVE) &&
+ (last_hop_metric > path->metric)))
+ fresh_info = _FALSE;
+ } else {
+ path = rtw_mesh_path_add(adapter, ta);
+ if (IS_ERR(path)) {
+ rtw_rcu_read_unlock();
+ return 0;
+ }
+ enter_critical_bh(&path->state_lock);
+ }
+
+ if (fresh_info) {
+ rtw_mesh_path_assign_nexthop(path, sta);
+ path->metric = last_hop_metric;
+ path->exp_time = rtw_time_after(path->exp_time, exp_time)
+ ? path->exp_time : exp_time;
+ rtw_mesh_path_activate(path);
+ exit_critical_bh(&path->state_lock);
+ rtw_mesh_path_tx_pending(path);
+ } else
+ exit_critical_bh(&path->state_lock);
+ }
+
+ rtw_rcu_read_unlock();
+
+ return process ? new_metric : 0;
+}
+
+void rtw_mesh_rx_path_sel_frame(_adapter *adapter, union recv_frame *rframe)
+{
+ struct mesh_plink_ent *plink = NULL;
+ struct rtw_ieee802_11_elems elems;
+ u32 path_metric;
+ struct rx_pkt_attrib *attrib = &rframe->u.hdr.attrib;
+ u8 *pframe = rframe->u.hdr.rx_data, *start;
+ uint frame_len = rframe->u.hdr.len, left;
+ struct rtw_ieee80211_hdr_3addr *frame_hdr = (struct rtw_ieee80211_hdr_3addr *)pframe;
+ u8 *frame_body = (u8 *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
+ ParseRes parse_res;
+
+ plink = rtw_mesh_plink_get(adapter, get_addr2_ptr(pframe));
+ if (!plink || plink->plink_state != RTW_MESH_PLINK_ESTAB)
+ return;
+
+ /* Mesh action frame IE offset = 2 */
+ attrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+ left = frame_len - attrib->hdrlen - attrib->iv_len - attrib->icv_len - 2;
+ start = pframe + attrib->hdrlen + 2;
+
+ parse_res = rtw_ieee802_11_parse_elems(start, left, &elems, 1);
+ if (parse_res == ParseFailed)
+ RTW_HWMP_INFO(FUNC_ADPT_FMT" Path Select Frame ParseFailed\n"
+ , FUNC_ADPT_ARG(adapter));
+ else if (parse_res == ParseUnknown)
+ RTW_HWMP_INFO(FUNC_ADPT_FMT" Path Select Frame ParseUnknown\n"
+ , FUNC_ADPT_ARG(adapter));
+
+ if (elems.preq) {
+ if (elems.preq_len != 37)
+ /* Right now we support just 1 destination and no AE */
+ return;
+ path_metric = rtw_hwmp_route_info_get(adapter, frame_hdr, elems.preq,
+ MPATH_PREQ);
+ if (path_metric)
+ rtw_hwmp_preq_frame_process(adapter, frame_hdr, elems.preq,
+ path_metric);
+ }
+ if (elems.prep) {
+ if (elems.prep_len != 31)
+ /* Right now we support no AE */
+ return;
+ path_metric = rtw_hwmp_route_info_get(adapter, frame_hdr, elems.prep,
+ MPATH_PREP);
+ if (path_metric)
+ rtw_hwmp_prep_frame_process(adapter, frame_hdr, elems.prep,
+ path_metric);
+ }
+ if (elems.perr) {
+ if (elems.perr_len != 15)
+ /* Right now we support only one destination per PERR */
+ return;
+ rtw_hwmp_perr_frame_process(adapter, frame_hdr, elems.perr);
+ }
+ if (elems.rann)
+ rtw_hwmp_rann_frame_process(adapter, frame_hdr, (struct rtw_ieee80211_rann_ie *)elems.rann);
+}
+
+void rtw_mesh_queue_preq(struct rtw_mesh_path *path, u8 flags)
+{
+ _adapter *adapter = path->adapter;
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct rtw_mesh_preq_queue *preq_node;
+
+ preq_node = rtw_malloc(sizeof(struct rtw_mesh_preq_queue));
+ if (!preq_node) {
+ RTW_HWMP_INFO("could not allocate PREQ node\n");
+ return;
+ }
+
+ enter_critical_bh(&minfo->mesh_preq_queue_lock);
+ if (minfo->preq_queue_len == RTW_MAX_PREQ_QUEUE_LEN) {
+ exit_critical_bh(&minfo->mesh_preq_queue_lock);
+ rtw_mfree(preq_node, sizeof(struct rtw_mesh_preq_queue));
+ if (rtw_print_ratelimit())
+ RTW_HWMP_INFO("PREQ node queue full\n");
+ return;
+ }
+
+ _rtw_spinlock(&path->state_lock);
+ if (path->flags & RTW_MESH_PATH_REQ_QUEUED) {
+ _rtw_spinunlock(&path->state_lock);
+ exit_critical_bh(&minfo->mesh_preq_queue_lock);
+ rtw_mfree(preq_node, sizeof(struct rtw_mesh_preq_queue));
+ return;
+ }
+
+ _rtw_memcpy(preq_node->dst, path->dst, ETH_ALEN);
+ preq_node->flags = flags;
+
+ path->flags |= RTW_MESH_PATH_REQ_QUEUED;
+ _rtw_spinunlock(&path->state_lock);
+
+ rtw_list_insert_tail(&preq_node->list, &minfo->preq_queue.list);
+ ++minfo->preq_queue_len;
+ exit_critical_bh(&minfo->mesh_preq_queue_lock);
+
+ if (rtw_time_after(rtw_get_current_time(), minfo->last_preq + rtw_min_preq_int_jiff(adapter)))
+ rtw_mesh_work(&adapter->mesh_work);
+
+ else if (rtw_time_before(rtw_get_current_time(), minfo->last_preq)) {
+ /* systime wrapped around issue */
+ minfo->last_preq = rtw_get_current_time() - rtw_min_preq_int_jiff(adapter) - 1;
+ rtw_mesh_work(&adapter->mesh_work);
+ } else
+ rtw_mod_timer(&adapter->mesh_path_timer, minfo->last_preq +
+ rtw_min_preq_int_jiff(adapter));
+}
+
+void rtw_mesh_path_start_discovery(_adapter *adapter)
+{
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg;
+ struct rtw_mesh_preq_queue *preq_node;
+ struct rtw_mesh_path *path;
+ u8 ttl, target_flags = 0;
+ const u8 *da;
+ u32 lifetime;
+ u8 flags = 0;
+
+ enter_critical_bh(&minfo->mesh_preq_queue_lock);
+ if (!minfo->preq_queue_len ||
+ rtw_time_before(rtw_get_current_time(), minfo->last_preq +
+ rtw_min_preq_int_jiff(adapter))) {
+ exit_critical_bh(&minfo->mesh_preq_queue_lock);
+ return;
+ }
+
+ preq_node = rtw_list_first_entry(&minfo->preq_queue.list,
+ struct rtw_mesh_preq_queue, list);
+ rtw_list_delete(&preq_node->list); /* list_del_init(&preq_node->list); */
+ --minfo->preq_queue_len;
+ exit_critical_bh(&minfo->mesh_preq_queue_lock);
+
+ rtw_rcu_read_lock();
+ path = rtw_mesh_path_lookup(adapter, preq_node->dst);
+ if (!path)
+ goto enddiscovery;
+
+ enter_critical_bh(&path->state_lock);
+ if (path->flags & (RTW_MESH_PATH_DELETED | RTW_MESH_PATH_FIXED)) {
+ exit_critical_bh(&path->state_lock);
+ goto enddiscovery;
+ }
+ path->flags &= ~RTW_MESH_PATH_REQ_QUEUED;
+ if (preq_node->flags & RTW_PREQ_Q_F_START) {
+ if (path->flags & RTW_MESH_PATH_RESOLVING) {
+ exit_critical_bh(&path->state_lock);
+ goto enddiscovery;
+ } else {
+ path->flags &= ~RTW_MESH_PATH_RESOLVED;
+ path->flags |= RTW_MESH_PATH_RESOLVING;
+ path->discovery_retries = 0;
+ path->discovery_timeout = rtw_disc_timeout_jiff(adapter);
+ }
+ } else if (!(path->flags & RTW_MESH_PATH_RESOLVING) ||
+ path->flags & RTW_MESH_PATH_RESOLVED) {
+ path->flags &= ~RTW_MESH_PATH_RESOLVING;
+ exit_critical_bh(&path->state_lock);
+ goto enddiscovery;
+ }
+
+ minfo->last_preq = rtw_get_current_time();
+
+ if (rtw_time_after(rtw_get_current_time(), minfo->last_sn_update +
+ rtw_net_traversal_jiffies(adapter)) ||
+ rtw_time_before(rtw_get_current_time(), minfo->last_sn_update)) {
+ ++minfo->sn;
+ minfo->last_sn_update = rtw_get_current_time();
+ }
+ lifetime = rtw_default_lifetime(adapter);
+ ttl = mshcfg->element_ttl;
+ if (ttl == 0) {
+ minfo->mshstats.dropped_frames_ttl++;
+ exit_critical_bh(&path->state_lock);
+ goto enddiscovery;
+ }
+
+ if (preq_node->flags & RTW_PREQ_Q_F_REFRESH)
+ target_flags |= RTW_IEEE80211_PREQ_TO_FLAG;
+ else
+ target_flags &= ~RTW_IEEE80211_PREQ_TO_FLAG;
+
+ exit_critical_bh(&path->state_lock);
+ da = (path->is_root) ? path->rann_snd_addr : bcast_addr;
+#ifdef CONFIG_RTW_MESH_ON_DMD_GANN
+ flags = (mshcfg->dot11MeshGateAnnouncementProtocol)
+ ? RTW_IEEE80211_PREQ_IS_GATE_FLAG : 0;
+#endif
+ rtw_mesh_path_sel_frame_tx(RTW_MPATH_PREQ, flags, adapter_mac_addr(adapter), minfo->sn,
+ target_flags, path->dst, path->sn, da, 0,
+ ttl, lifetime, 0, minfo->preq_id++, adapter);
+ rtw_mod_timer(&path->timer, rtw_get_current_time() + path->discovery_timeout);
+
+enddiscovery:
+ rtw_rcu_read_unlock();
+ rtw_mfree(preq_node, sizeof(struct rtw_mesh_preq_queue));
+}
+
+void rtw_mesh_path_timer(void *ctx)
+{
+ struct rtw_mesh_path *path = (void *) ctx;
+ _adapter *adapter = path->adapter;
+ int ret;
+
+ /* TBD: Proctect for suspend */
+#if 0
+ if (suspending)
+ return;
+#endif
+ enter_critical_bh(&path->state_lock);
+ if (path->flags & RTW_MESH_PATH_RESOLVED ||
+ (!(path->flags & RTW_MESH_PATH_RESOLVING))) {
+ path->flags &= ~(RTW_MESH_PATH_RESOLVING | RTW_MESH_PATH_RESOLVED);
+ exit_critical_bh(&path->state_lock);
+ } else if (path->discovery_retries < rtw_max_preq_retries(adapter)) {
+ ++path->discovery_retries;
+ path->discovery_timeout *= 2;
+ path->flags &= ~RTW_MESH_PATH_REQ_QUEUED;
+ exit_critical_bh(&path->state_lock);
+ rtw_mesh_queue_preq(path, 0);
+ } else {
+ path->flags &= ~(RTW_MESH_PATH_RESOLVING |
+ RTW_MESH_PATH_RESOLVED |
+ RTW_MESH_PATH_REQ_QUEUED);
+ path->exp_time = rtw_get_current_time();
+ exit_critical_bh(&path->state_lock);
+ if (!path->is_gate && rtw_mesh_gate_num(adapter) > 0) {
+ ret = rtw_mesh_path_send_to_gates(path);
+ if (ret)
+ RTW_HWMP_DBG("no gate was reachable\n");
+ } else
+ rtw_mesh_path_flush_pending(path);
+ }
+}
+
+
+void rtw_mesh_path_tx_root_frame(_adapter *adapter)
+{
+ struct rtw_mesh_cfg *mshcfg = &adapter->mesh_cfg;
+ struct rtw_mesh_info *minfo = &adapter->mesh_info;
+ u32 interval = mshcfg->dot11MeshHWMPRannInterval;
+ u8 flags, target_flags = 0;
+
+ flags = (mshcfg->dot11MeshGateAnnouncementProtocol)
+ ? RTW_RANN_FLAG_IS_GATE : 0;
+
+ switch (mshcfg->dot11MeshHWMPRootMode) {
+ case RTW_IEEE80211_PROACTIVE_RANN:
+ rtw_mesh_path_sel_frame_tx(RTW_MPATH_RANN, flags, adapter_mac_addr(adapter),
+ ++minfo->sn, 0, NULL, 0, bcast_addr,
+ 0, mshcfg->element_ttl,
+ interval, 0, 0, adapter);
+ break;
+ case RTW_IEEE80211_PROACTIVE_PREQ_WITH_PREP:
+ flags |= RTW_IEEE80211_PREQ_PROACTIVE_PREP_FLAG;
+ case RTW_IEEE80211_PROACTIVE_PREQ_NO_PREP:
+ interval = mshcfg->dot11MeshHWMPactivePathToRootTimeout;
+ target_flags |= RTW_IEEE80211_PREQ_TO_FLAG |
+ RTW_IEEE80211_PREQ_USN_FLAG;
+ rtw_mesh_path_sel_frame_tx(RTW_MPATH_PREQ, flags, adapter_mac_addr(adapter),
+ ++minfo->sn, target_flags,
+ (u8 *) bcast_addr, 0, bcast_addr,
+ 0, mshcfg->element_ttl, interval,
+ 0, minfo->preq_id++, adapter);
+ break;
+ default:
+ RTW_HWMP_INFO("Proactive mechanism not supported\n");
+ return;
+ }
+}
+
+void rtw_mesh_work(_workitem *work)
+{
+ /* use kernel global workqueue */
+ _set_workitem(work);
+}
+
+void rtw_ieee80211_mesh_path_timer(void *ctx)
+{
+ _adapter *adapter = (_adapter *)ctx;
+ rtw_mesh_work(&adapter->mesh_work);
+}
+
+void rtw_ieee80211_mesh_path_root_timer(void *ctx)
+{
+ _adapter *adapter = (_adapter *)ctx;
+
+ rtw_set_bit(RTW_MESH_WORK_ROOT, &adapter->wrkq_flags);
+
+ rtw_mesh_work(&adapter->mesh_work);
+}
+
+static void rtw_ieee80211_mesh_rootpath(_adapter *adapter)
+{
+ u32 interval;
+
+ rtw_mesh_path_tx_root_frame(adapter);
+
+ if (adapter->mesh_cfg.dot11MeshHWMPRootMode == RTW_IEEE80211_PROACTIVE_RANN)
+ interval = adapter->mesh_cfg.dot11MeshHWMPRannInterval;
+ else
+ interval = adapter->mesh_cfg.dot11MeshHWMProotInterval;
+
+ rtw_mod_timer(&adapter->mesh_path_root_timer,
+ RTW_TU_TO_EXP_TIME(interval));
+}
+
+BOOLEAN rtw_ieee80211_mesh_root_setup(_adapter *adapter)
+{
+ BOOLEAN root_enabled = _FALSE;
+
+ if (adapter->mesh_cfg.dot11MeshHWMPRootMode > RTW_IEEE80211_ROOTMODE_ROOT) {
+ rtw_set_bit(RTW_MESH_WORK_ROOT, &adapter->wrkq_flags);
+ root_enabled = _TRUE;
+ }
+ else {
+ rtw_clear_bit(RTW_MESH_WORK_ROOT, &adapter->wrkq_flags);
+ /* stop running timer */
+ _cancel_timer_ex(&adapter->mesh_path_root_timer);
+ root_enabled = _FALSE;
+ }
+
+ return root_enabled;
+}
+
+void rtw_mesh_work_hdl(_workitem *work)
+{
+ _adapter *adapter = container_of(work, _adapter, mesh_work);
+
+ if (adapter->mesh_info.preq_queue_len &&
+ rtw_time_after(rtw_get_current_time(),
+ adapter->mesh_info.last_preq + rtw_ms_to_systime(adapter->mesh_cfg.dot11MeshHWMPpreqMinInterval)))
+ rtw_mesh_path_start_discovery(adapter);
+
+ if (rtw_test_and_clear_bit(RTW_MESH_WORK_ROOT, &adapter->wrkq_flags))
+ rtw_ieee80211_mesh_rootpath(adapter);
+}
+
+#ifndef RTW_PER_CMD_SUPPORT_FW
+static void rtw_update_metric_directly(_adapter *adapter)
+{
+ struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+ struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
+ u8 i;
+
+ for (i = 0; i < macid_ctl->num; i++) {
+ u8 role;
+ role = GET_H2CCMD_MSRRPT_PARM_ROLE(&macid_ctl->h2c_msr[i]);
+ if (role == H2C_MSR_ROLE_MESH) {
+ struct sta_info *sta = macid_ctl->sta[i];
+ u8 rate_idx, sgi, bw;
+ u32 rate;
+
+ if (!sta)
+ continue;
+ rate_idx = rtw_get_current_tx_rate(adapter, sta);
+ sgi = rtw_get_current_tx_sgi(adapter, sta);
+ bw = sta->cmn.bw_mode;
+ rate = rtw_desc_rate_to_bitrate(bw, rate_idx, sgi);
+ sta->metrics.data_rate = rate;
+ }
+ }
+}
+#endif
+
+void rtw_mesh_atlm_param_req_timer(void *ctx)
+{
+ _adapter *adapter = (_adapter *)ctx;
+ u8 ret = _FAIL;
+
+#ifdef RTW_PER_CMD_SUPPORT_FW
+ ret = rtw_req_per_cmd(adapter);
+ if (ret == _FAIL)
+ RTW_HWMP_INFO("rtw_req_per_cmd fail\n");
+#else
+ rtw_update_metric_directly(adapter);
+#endif
+ _set_timer(&adapter->mesh_atlm_param_req_timer, RTW_ATLM_REQ_CYCLE);
+}
+
+#endif /* CONFIG_RTW_MESH */
+
diff --git a/core/mesh/rtw_mesh_hwmp.h b/core/mesh/rtw_mesh_hwmp.h
new file mode 100644
index 0000000..9433417
--- /dev/null
+++ b/core/mesh/rtw_mesh_hwmp.h
@@ -0,0 +1,60 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTW_MESH_HWMP_H_
+#define __RTW_MESH_HWMP_H_
+
+#ifndef DBG_RTW_HWMP
+#define DBG_RTW_HWMP 0
+#endif
+#if DBG_RTW_HWMP
+#define RTW_HWMP_DBG(fmt, arg...) RTW_PRINT(fmt, ##arg)
+#else
+#define RTW_HWMP_DBG(fmt, arg...) RTW_DBG(fmt, ##arg)
+#endif
+
+#ifndef INFO_RTW_HWMP
+#define INFO_RTW_HWMP 0
+#endif
+#if INFO_RTW_HWMP
+#define RTW_HWMP_INFO(fmt, arg...) RTW_PRINT(fmt, ##arg)
+#else
+#define RTW_HWMP_INFO(fmt, arg...) RTW_INFO(fmt, ##arg)
+#endif
+
+
+void rtw_ewma_err_rate_init(struct rtw_ewma_err_rate *e);
+unsigned long rtw_ewma_err_rate_read(struct rtw_ewma_err_rate *e);
+void rtw_ewma_err_rate_add(struct rtw_ewma_err_rate *e, unsigned long val);
+int rtw_mesh_path_error_tx(_adapter *adapter,
+ u8 ttl, const u8 *target, u32 target_sn,
+ u16 target_rcode, const u8 *ra);
+void rtw_ieee80211s_update_metric(_adapter *adapter, u8 mac_id,
+ u8 per, u8 rate,
+ u8 bw, u8 total_pkt);
+void rtw_mesh_rx_path_sel_frame(_adapter *adapter, union recv_frame *rframe);
+void rtw_mesh_queue_preq(struct rtw_mesh_path *mpath, u8 flags);
+void rtw_mesh_path_start_discovery(_adapter *adapter);
+void rtw_mesh_path_timer(void *ctx);
+void rtw_mesh_path_tx_root_frame(_adapter *adapter);
+void rtw_mesh_work_hdl(_workitem *work);
+void rtw_ieee80211_mesh_path_timer(void *ctx);
+void rtw_ieee80211_mesh_path_root_timer(void *ctx);
+BOOLEAN rtw_ieee80211_mesh_root_setup(_adapter *adapter);
+void rtw_mesh_work(_workitem *work);
+void rtw_mesh_atlm_param_req_timer(void *ctx);
+
+#endif /* __RTW_MESH_HWMP_H_ */
+
+
diff --git a/core/mesh/rtw_mesh_pathtbl.c b/core/mesh/rtw_mesh_pathtbl.c
new file mode 100644
index 0000000..d1baaa8
--- /dev/null
+++ b/core/mesh/rtw_mesh_pathtbl.c
@@ -0,0 +1,1082 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#define _RTW_MESH_PATHTBL_C_
+
+#ifdef CONFIG_RTW_MESH
+#include
+#include
+
+#ifdef PLATFORM_LINUX
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
+static void rtw_mpath_free_rcu(struct rtw_mesh_path *mpath)
+{
+ kfree_rcu(mpath, rcu);
+ rtw_mstat_update(MSTAT_TYPE_PHY, MSTAT_FREE, sizeof(struct rtw_mesh_path));
+}
+#else
+static void rtw_mpath_free_rcu_callback(rtw_rcu_head *head)
+{
+ struct rtw_mesh_path *mpath;
+
+ mpath = container_of(head, struct rtw_mesh_path, rcu);
+ rtw_mfree(mpath, sizeof(struct rtw_mesh_path));
+}
+
+static void rtw_mpath_free_rcu(struct rtw_mesh_path *mpath)
+{
+ call_rcu(&mpath->rcu, rtw_mpath_free_rcu_callback);
+}
+#endif
+#endif /* PLATFORM_LINUX */
+
+static void rtw_mesh_path_free_rcu(struct rtw_mesh_table *tbl, struct rtw_mesh_path *mpath);
+
+static u32 rtw_mesh_table_hash(const void *addr, u32 len, u32 seed)
+{
+ /* Use last four bytes of hw addr as hash index */
+ return jhash_1word(*(u32 *)(addr+2), seed);
+}
+
+static const rtw_rhashtable_params rtw_mesh_rht_params = {
+ .nelem_hint = 2,
+ .automatic_shrinking = true,
+ .key_len = ETH_ALEN,
+ .key_offset = offsetof(struct rtw_mesh_path, dst),
+ .head_offset = offsetof(struct rtw_mesh_path, rhash),
+ .hashfn = rtw_mesh_table_hash,
+};
+
+static inline bool rtw_mpath_expired(struct rtw_mesh_path *mpath)
+{
+ return (mpath->flags & RTW_MESH_PATH_ACTIVE) &&
+ rtw_time_after(rtw_get_current_time(), mpath->exp_time) &&
+ !(mpath->flags & RTW_MESH_PATH_FIXED);
+}
+
+static void rtw_mesh_path_rht_free(void *ptr, void *tblptr)
+{
+ struct rtw_mesh_path *mpath = ptr;
+ struct rtw_mesh_table *tbl = tblptr;
+
+ rtw_mesh_path_free_rcu(tbl, mpath);
+}
+
+static struct rtw_mesh_table *rtw_mesh_table_alloc(void)
+{
+ struct rtw_mesh_table *newtbl;
+
+ newtbl = rtw_malloc(sizeof(struct rtw_mesh_table));
+ if (!newtbl)
+ return NULL;
+
+ rtw_hlist_head_init(&newtbl->known_gates);
+ ATOMIC_SET(&newtbl->entries, 0);
+ _rtw_spinlock_init(&newtbl->gates_lock);
+
+ return newtbl;
+}
+
+static void rtw_mesh_table_free(struct rtw_mesh_table *tbl)
+{
+ rtw_rhashtable_free_and_destroy(&tbl->rhead,
+ rtw_mesh_path_rht_free, tbl);
+ rtw_mfree(tbl, sizeof(struct rtw_mesh_table));
+}
+
+/**
+ *
+ * rtw_mesh_path_assign_nexthop - update mesh path next hop
+ *
+ * @mpath: mesh path to update
+ * @sta: next hop to assign
+ *
+ * Locking: mpath->state_lock must be held when calling this function
+ */
+void rtw_mesh_path_assign_nexthop(struct rtw_mesh_path *mpath, struct sta_info *sta)
+{
+ struct xmit_frame *xframe;
+ _list *list, *head;
+
+ rtw_rcu_assign_pointer(mpath->next_hop, sta);
+
+ enter_critical_bh(&mpath->frame_queue.lock);
+ head = &mpath->frame_queue.queue;
+ list = get_next(head);
+ while (rtw_end_of_queue_search(head, list) == _FALSE) {
+ xframe = LIST_CONTAINOR(list, struct xmit_frame, list);
+ list = get_next(list);
+ _rtw_memcpy(xframe->attrib.ra, sta->cmn.mac_addr, ETH_ALEN);
+ }
+
+ exit_critical_bh(&mpath->frame_queue.lock);
+}
+
+static void rtw_prepare_for_gate(struct xmit_frame *xframe, char *dst_addr,
+ struct rtw_mesh_path *gate_mpath)
+{
+ struct pkt_attrib *attrib = &xframe->attrib;
+ char *next_hop;
+
+ if (attrib->mesh_frame_mode == MESH_UCAST_DATA)
+ attrib->mesh_frame_mode = MESH_UCAST_PX_DATA;
+
+ /* update next hop */
+ rtw_rcu_read_lock();
+ next_hop = rtw_rcu_dereference(gate_mpath->next_hop)->cmn.mac_addr;
+ _rtw_memcpy(attrib->ra, next_hop, ETH_ALEN);
+ rtw_rcu_read_unlock();
+ _rtw_memcpy(attrib->mda, dst_addr, ETH_ALEN);
+}
+
+/**
+ *
+ * rtw_mesh_path_move_to_queue - Move or copy frames from one mpath queue to another
+ *
+ * This function is used to transfer or copy frames from an unresolved mpath to
+ * a gate mpath. The function also adds the Address Extension field and
+ * updates the next hop.
+ *
+ * If a frame already has an Address Extension field, only the next hop and
+ * destination addresses are updated.
+ *
+ * The gate mpath must be an active mpath with a valid mpath->next_hop.
+ *
+ * @mpath: An active mpath the frames will be sent to (i.e. the gate)
+ * @from_mpath: The failed mpath
+ * @copy: When true, copy all the frames to the new mpath queue. When false,
+ * move them.
+ */
+static void rtw_mesh_path_move_to_queue(struct rtw_mesh_path *gate_mpath,
+ struct rtw_mesh_path *from_mpath,
+ bool copy)
+{
+ struct xmit_frame *fskb;
+ _list *list, *head;
+ _list failq;
+ u32 failq_len;
+ _irqL flags;
+
+ if (rtw_warn_on(gate_mpath == from_mpath))
+ return;
+ if (rtw_warn_on(!gate_mpath->next_hop))
+ return;
+
+ _rtw_init_listhead(&failq);
+
+ _enter_critical_bh(&from_mpath->frame_queue.lock, &flags);
+ rtw_list_splice_init(&from_mpath->frame_queue.queue, &failq);
+ failq_len = from_mpath->frame_queue_len;
+ from_mpath->frame_queue_len = 0;
+ _exit_critical_bh(&from_mpath->frame_queue.lock, &flags);
+
+ head = &failq;
+ list = get_next(head);
+ while (rtw_end_of_queue_search(head, list) == _FALSE) {
+ if (gate_mpath->frame_queue_len >= RTW_MESH_FRAME_QUEUE_LEN) {
+ RTW_MPATH_DBG(FUNC_ADPT_FMT" mpath queue for gate %pM is full!\n"
+ , FUNC_ADPT_ARG(gate_mpath->adapter), gate_mpath->dst);
+ break;
+ }
+
+ fskb = LIST_CONTAINOR(list, struct xmit_frame, list);
+ list = get_next(list);
+
+ rtw_list_delete(&fskb->list);
+ failq_len--;
+ rtw_prepare_for_gate(fskb, gate_mpath->dst, gate_mpath);
+ _enter_critical_bh(&gate_mpath->frame_queue.lock, &flags);
+ rtw_list_insert_tail(&fskb->list, get_list_head(&gate_mpath->frame_queue));
+ gate_mpath->frame_queue_len++;
+ _exit_critical_bh(&gate_mpath->frame_queue.lock, &flags);
+
+ #if 0 /* TODO: copy */
+ skb = rtw_skb_copy(fskb);
+ if (rtw_warn_on(!skb))
+ break;
+
+ rtw_prepare_for_gate(skb, gate_mpath->dst, gate_mpath);
+ skb_queue_tail(&gate_mpath->frame_queue, skb);
+
+ if (copy)
+ continue;
+
+ __skb_unlink(fskb, &failq);
+ rtw_skb_free(fskb);
+ #endif
+ }
+
+ RTW_MPATH_DBG(FUNC_ADPT_FMT" mpath queue for gate %pM has %d frames\n"
+ , FUNC_ADPT_ARG(gate_mpath->adapter), gate_mpath->dst, gate_mpath->frame_queue_len);
+
+ if (!copy)
+ return;
+
+ _enter_critical_bh(&from_mpath->frame_queue.lock, &flags);
+ rtw_list_splice(&failq, &from_mpath->frame_queue.queue);
+ from_mpath->frame_queue_len += failq_len;
+ _exit_critical_bh(&from_mpath->frame_queue.lock, &flags);
+}
+
+
+static struct rtw_mesh_path *rtw_mpath_lookup(struct rtw_mesh_table *tbl, const u8 *dst)
+{
+ struct rtw_mesh_path *mpath;
+
+ if (!tbl)
+ return NULL;
+
+ mpath = rtw_rhashtable_lookup_fast(&tbl->rhead, dst, rtw_mesh_rht_params);
+
+ if (mpath && rtw_mpath_expired(mpath)) {
+ enter_critical_bh(&mpath->state_lock);
+ mpath->flags &= ~RTW_MESH_PATH_ACTIVE;
+ exit_critical_bh(&mpath->state_lock);
+ }
+ return mpath;
+}
+
+/**
+ * rtw_mesh_path_lookup - look up a path in the mesh path table
+ * @sdata: local subif
+ * @dst: hardware address (ETH_ALEN length) of destination
+ *
+ * Returns: pointer to the mesh path structure, or NULL if not found
+ *
+ * Locking: must be called within a read rcu section.
+ */
+struct rtw_mesh_path *
+rtw_mesh_path_lookup(_adapter *adapter, const u8 *dst)
+{
+ return rtw_mpath_lookup(adapter->mesh_info.mesh_paths, dst);
+}
+
+struct rtw_mesh_path *
+rtw_mpp_path_lookup(_adapter *adapter, const u8 *dst)
+{
+ return rtw_mpath_lookup(adapter->mesh_info.mpp_paths, dst);
+}
+
+static struct rtw_mesh_path *
+__rtw_mesh_path_lookup_by_idx(struct rtw_mesh_table *tbl, int idx)
+{
+ int i = 0, ret;
+ struct rtw_mesh_path *mpath = NULL;
+ rtw_rhashtable_iter iter;
+
+ if (!tbl)
+ return NULL;
+
+ ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);
+ if (ret)
+ return NULL;
+
+ ret = rtw_rhashtable_walk_start(&iter);
+ if (ret && ret != -EAGAIN)
+ goto err;
+
+ while ((mpath = rtw_rhashtable_walk_next(&iter))) {
+ if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN)
+ continue;
+ if (IS_ERR(mpath))
+ break;
+ if (i++ == idx)
+ break;
+ }
+err:
+ rtw_rhashtable_walk_stop(&iter);
+ rtw_rhashtable_walk_exit(&iter);
+
+ if (IS_ERR(mpath) || !mpath)
+ return NULL;
+
+ if (rtw_mpath_expired(mpath)) {
+ enter_critical_bh(&mpath->state_lock);
+ mpath->flags &= ~RTW_MESH_PATH_ACTIVE;
+ exit_critical_bh(&mpath->state_lock);
+ }
+ return mpath;
+}
+
+/**
+ * rtw_mesh_path_lookup_by_idx - look up a path in the mesh path table by its index
+ * @idx: index
+ * @sdata: local subif, or NULL for all entries
+ *
+ * Returns: pointer to the mesh path structure, or NULL if not found.
+ *
+ * Locking: must be called within a read rcu section.
+ */
+struct rtw_mesh_path *
+rtw_mesh_path_lookup_by_idx(_adapter *adapter, int idx)
+{
+ return __rtw_mesh_path_lookup_by_idx(adapter->mesh_info.mesh_paths, idx);
+}
+
+/**
+ * rtw_mpp_path_lookup_by_idx - look up a path in the proxy path table by its index
+ * @idx: index
+ * @sdata: local subif, or NULL for all entries
+ *
+ * Returns: pointer to the proxy path structure, or NULL if not found.
+ *
+ * Locking: must be called within a read rcu section.
+ */
+struct rtw_mesh_path *
+rtw_mpp_path_lookup_by_idx(_adapter *adapter, int idx)
+{
+ return __rtw_mesh_path_lookup_by_idx(adapter->mesh_info.mpp_paths, idx);
+}
+
+/**
+ * rtw_mesh_path_add_gate - add the given mpath to a mesh gate to our path table
+ * @mpath: gate path to add to table
+ */
+int rtw_mesh_path_add_gate(struct rtw_mesh_path *mpath)
+{
+ struct rtw_mesh_cfg *mcfg;
+ struct rtw_mesh_info *minfo;
+ struct rtw_mesh_table *tbl;
+ int err, ori_num_gates;
+
+ rtw_rcu_read_lock();
+ tbl = mpath->adapter->mesh_info.mesh_paths;
+ if (!tbl) {
+ err = -ENOENT;
+ goto err_rcu;
+ }
+
+ enter_critical_bh(&mpath->state_lock);
+ mcfg = &mpath->adapter->mesh_cfg;
+ mpath->gate_timeout = rtw_get_current_time() +
+ rtw_ms_to_systime(mcfg->path_gate_timeout_factor *
+ mpath->gate_ann_int);
+ if (mpath->is_gate) {
+ err = -EEXIST;
+ exit_critical_bh(&mpath->state_lock);
+ goto err_rcu;
+ }
+
+ minfo = &mpath->adapter->mesh_info;
+ mpath->is_gate = true;
+ _rtw_spinlock(&tbl->gates_lock);
+ ori_num_gates = minfo->num_gates;
+ minfo->num_gates++;
+ rtw_hlist_add_head_rcu(&mpath->gate_list, &tbl->known_gates);
+ _rtw_spinunlock(&tbl->gates_lock);
+
+ exit_critical_bh(&mpath->state_lock);
+
+ if (ori_num_gates == 0)
+ update_beacon(mpath->adapter, WLAN_EID_MESH_CONFIG, NULL, _TRUE);
+
+ RTW_MPATH_DBG(
+ FUNC_ADPT_FMT" Mesh path: Recorded new gate: %pM. %d known gates\n",
+ FUNC_ADPT_ARG(mpath->adapter),
+ mpath->dst, mpath->adapter->mesh_info.num_gates);
+ err = 0;
+err_rcu:
+ rtw_rcu_read_unlock();
+ return err;
+}
+
+/**
+ * rtw_mesh_gate_del - remove a mesh gate from the list of known gates
+ * @tbl: table which holds our list of known gates
+ * @mpath: gate mpath
+ */
+void rtw_mesh_gate_del(struct rtw_mesh_table *tbl, struct rtw_mesh_path *mpath)
+{
+ struct rtw_mesh_cfg *mcfg;
+ struct rtw_mesh_info *minfo;
+ int ori_num_gates;
+
+ rtw_lockdep_assert_held(&mpath->state_lock);
+ if (!mpath->is_gate)
+ return;
+
+ mcfg = &mpath->adapter->mesh_cfg;
+ minfo = &mpath->adapter->mesh_info;
+
+ mpath->is_gate = false;
+ enter_critical_bh(&tbl->gates_lock);
+ rtw_hlist_del_rcu(&mpath->gate_list);
+ ori_num_gates = minfo->num_gates;
+ minfo->num_gates--;
+ exit_critical_bh(&tbl->gates_lock);
+
+ if (ori_num_gates == 1)
+ update_beacon(mpath->adapter, WLAN_EID_MESH_CONFIG, NULL, _TRUE);
+
+ RTW_MPATH_DBG(
+ FUNC_ADPT_FMT" Mesh path: Deleted gate: %pM. %d known gates\n",
+ FUNC_ADPT_ARG(mpath->adapter),
+ mpath->dst, mpath->adapter->mesh_info.num_gates);
+}
+
+/**
+ * rtw_mesh_gate_search - search a mesh gate from the list of known gates
+ * @tbl: table which holds our list of known gates
+ * @addr: address of gate
+ */
+bool rtw_mesh_gate_search(struct rtw_mesh_table *tbl, const u8 *addr)
+{
+ struct rtw_mesh_path *gate;
+ rtw_hlist_node *node;
+ bool exist = 0;
+
+ rtw_rcu_read_lock();
+ rtw_hlist_for_each_entry_rcu(gate, node, &tbl->known_gates, gate_list) {
+ if (_rtw_memcmp(gate->dst, addr, ETH_ALEN) == _TRUE) {
+ exist = 1;
+ break;
+ }
+ }
+
+ rtw_rcu_read_unlock();
+
+ return exist;
+}
+
+/**
+ * rtw_mesh_gate_num - number of gates known to this interface
+ * @sdata: subif data
+ */
+int rtw_mesh_gate_num(_adapter *adapter)
+{
+ return adapter->mesh_info.num_gates;
+}
+
+static
+struct rtw_mesh_path *rtw_mesh_path_new(_adapter *adapter,
+ const u8 *dst)
+{
+ struct rtw_mesh_path *new_mpath;
+
+ new_mpath = rtw_zmalloc(sizeof(struct rtw_mesh_path));
+ if (!new_mpath)
+ return NULL;
+
+ _rtw_memcpy(new_mpath->dst, dst, ETH_ALEN);
+ _rtw_memset(new_mpath->rann_snd_addr, 0xFF, ETH_ALEN);
+ new_mpath->is_root = false;
+ new_mpath->adapter = adapter;
+ new_mpath->flags = 0;
+ new_mpath->gate_asked = false;
+ _rtw_init_queue(&new_mpath->frame_queue);
+ new_mpath->frame_queue_len = 0;
+ new_mpath->exp_time = rtw_get_current_time();
+ _rtw_spinlock_init(&new_mpath->state_lock);
+ rtw_init_timer(&new_mpath->timer, adapter, rtw_mesh_path_timer, new_mpath);
+
+ return new_mpath;
+}
+
+/**
+ * rtw_mesh_path_add - allocate and add a new path to the mesh path table
+ * @dst: destination address of the path (ETH_ALEN length)
+ * @sdata: local subif
+ *
+ * Returns: 0 on success
+ *
+ * State: the initial state of the new path is set to 0
+ */
+struct rtw_mesh_path *rtw_mesh_path_add(_adapter *adapter,
+ const u8 *dst)
+{
+ struct rtw_mesh_table *tbl = adapter->mesh_info.mesh_paths;
+ struct rtw_mesh_path *mpath, *new_mpath;
+ int ret;
+
+ if (!tbl)
+ return ERR_PTR(-ENOTSUPP);
+
+ if (_rtw_memcmp(dst, adapter_mac_addr(adapter), ETH_ALEN) == _TRUE)
+ /* never add ourselves as neighbours */
+ return ERR_PTR(-ENOTSUPP);
+
+ if (is_multicast_mac_addr(dst))
+ return ERR_PTR(-ENOTSUPP);
+
+ if (ATOMIC_INC_UNLESS(&adapter->mesh_info.mpaths, RTW_MESH_MAX_MPATHS) == 0)
+ return ERR_PTR(-ENOSPC);
+
+ new_mpath = rtw_mesh_path_new(adapter, dst);
+ if (!new_mpath)
+ return ERR_PTR(-ENOMEM);
+
+ do {
+ ret = rtw_rhashtable_lookup_insert_fast(&tbl->rhead,
+ &new_mpath->rhash,
+ rtw_mesh_rht_params);
+
+ if (ret == -EEXIST)
+ mpath = rtw_rhashtable_lookup_fast(&tbl->rhead,
+ dst,
+ rtw_mesh_rht_params);
+
+ } while (unlikely(ret == -EEXIST && !mpath));
+
+ if (ret && ret != -EEXIST)
+ return ERR_PTR(ret);
+
+ /* At this point either new_mpath was added, or we found a
+ * matching entry already in the table; in the latter case
+ * free the unnecessary new entry.
+ */
+ if (ret == -EEXIST) {
+ rtw_mfree(new_mpath, sizeof(struct rtw_mesh_path));
+ new_mpath = mpath;
+ }
+ adapter->mesh_info.mesh_paths_generation++;
+ return new_mpath;
+}
+
+int rtw_mpp_path_add(_adapter *adapter,
+ const u8 *dst, const u8 *mpp)
+{
+ struct rtw_mesh_table *tbl = adapter->mesh_info.mpp_paths;
+ struct rtw_mesh_path *new_mpath;
+ int ret;
+
+ if (!tbl)
+ return -ENOTSUPP;
+
+ if (_rtw_memcmp(dst, adapter_mac_addr(adapter), ETH_ALEN) == _TRUE)
+ /* never add ourselves as neighbours */
+ return -ENOTSUPP;
+
+ if (is_multicast_mac_addr(dst))
+ return -ENOTSUPP;
+
+ new_mpath = rtw_mesh_path_new(adapter, dst);
+
+ if (!new_mpath)
+ return -ENOMEM;
+
+ _rtw_memcpy(new_mpath->mpp, mpp, ETH_ALEN);
+ ret = rtw_rhashtable_lookup_insert_fast(&tbl->rhead,
+ &new_mpath->rhash,
+ rtw_mesh_rht_params);
+
+ adapter->mesh_info.mpp_paths_generation++;
+ return ret;
+}
+
+
+/**
+ * rtw_mesh_plink_broken - deactivates paths and sends perr when a link breaks
+ *
+ * @sta: broken peer link
+ *
+ * This function must be called from the rate control algorithm if enough
+ * delivery errors suggest that a peer link is no longer usable.
+ */
+void rtw_mesh_plink_broken(struct sta_info *sta)
+{
+ _adapter *adapter = sta->padapter;
+ struct rtw_mesh_table *tbl = adapter->mesh_info.mesh_paths;
+ static const u8 bcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+ struct rtw_mesh_path *mpath;
+ rtw_rhashtable_iter iter;
+ int ret;
+
+ if (!tbl)
+ return;
+
+ ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);
+ if (ret)
+ return;
+
+ ret = rtw_rhashtable_walk_start(&iter);
+ if (ret && ret != -EAGAIN)
+ goto out;
+
+ while ((mpath = rtw_rhashtable_walk_next(&iter))) {
+ if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN)
+ continue;
+ if (IS_ERR(mpath))
+ break;
+ if (rtw_rcu_access_pointer(mpath->next_hop) == sta &&
+ mpath->flags & RTW_MESH_PATH_ACTIVE &&
+ !(mpath->flags & RTW_MESH_PATH_FIXED)) {
+ enter_critical_bh(&mpath->state_lock);
+ mpath->flags &= ~RTW_MESH_PATH_ACTIVE;
+ ++mpath->sn;
+ exit_critical_bh(&mpath->state_lock);
+ rtw_mesh_path_error_tx(adapter,
+ adapter->mesh_cfg.element_ttl,
+ mpath->dst, mpath->sn,
+ WLAN_REASON_MESH_PATH_DEST_UNREACHABLE, bcast);
+ }
+ }
+out:
+ rtw_rhashtable_walk_stop(&iter);
+ rtw_rhashtable_walk_exit(&iter);
+}
+
+static void rtw_mesh_path_free_rcu(struct rtw_mesh_table *tbl,
+ struct rtw_mesh_path *mpath)
+{
+ _adapter *adapter = mpath->adapter;
+
+ enter_critical_bh(&mpath->state_lock);
+ mpath->flags |= RTW_MESH_PATH_RESOLVING | RTW_MESH_PATH_DELETED;
+ rtw_mesh_gate_del(tbl, mpath);
+ exit_critical_bh(&mpath->state_lock);
+ _cancel_timer_ex(&mpath->timer);
+ ATOMIC_DEC(&adapter->mesh_info.mpaths);
+ ATOMIC_DEC(&tbl->entries);
+ _rtw_spinlock_free(&mpath->state_lock);
+
+ rtw_mesh_path_flush_pending(mpath);
+
+ rtw_mpath_free_rcu(mpath);
+}
+
+static void __rtw_mesh_path_del(struct rtw_mesh_table *tbl, struct rtw_mesh_path *mpath)
+{
+ rtw_rhashtable_remove_fast(&tbl->rhead, &mpath->rhash, rtw_mesh_rht_params);
+ rtw_mesh_path_free_rcu(tbl, mpath);
+}
+
+/**
+ * rtw_mesh_path_flush_by_nexthop - Deletes mesh paths if their next hop matches
+ *
+ * @sta: mesh peer to match
+ *
+ * RCU notes: this function is called when a mesh plink transitions from
+ * PLINK_ESTAB to any other state, since PLINK_ESTAB state is the only one that
+ * allows path creation. This will happen before the sta can be freed (because
+ * sta_info_destroy() calls this) so any reader in a rcu read block will be
+ * protected against the plink disappearing.
+ */
+void rtw_mesh_path_flush_by_nexthop(struct sta_info *sta)
+{
+ _adapter *adapter = sta->padapter;
+ struct rtw_mesh_table *tbl = adapter->mesh_info.mesh_paths;
+ struct rtw_mesh_path *mpath;
+ rtw_rhashtable_iter iter;
+ int ret;
+
+ if (!tbl)
+ return;
+
+ ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);
+ if (ret)
+ return;
+
+ ret = rtw_rhashtable_walk_start(&iter);
+ if (ret && ret != -EAGAIN)
+ goto out;
+
+ while ((mpath = rtw_rhashtable_walk_next(&iter))) {
+ if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN)
+ continue;
+ if (IS_ERR(mpath))
+ break;
+
+ if (rtw_rcu_access_pointer(mpath->next_hop) == sta)
+ __rtw_mesh_path_del(tbl, mpath);
+ }
+out:
+ rtw_rhashtable_walk_stop(&iter);
+ rtw_rhashtable_walk_exit(&iter);
+}
+
+static void rtw_mpp_flush_by_proxy(_adapter *adapter,
+ const u8 *proxy)
+{
+ struct rtw_mesh_table *tbl = adapter->mesh_info.mpp_paths;
+ struct rtw_mesh_path *mpath;
+ rtw_rhashtable_iter iter;
+ int ret;
+
+ if (!tbl)
+ return;
+
+ ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);
+ if (ret)
+ return;
+
+ ret = rtw_rhashtable_walk_start(&iter);
+ if (ret && ret != -EAGAIN)
+ goto out;
+
+ while ((mpath = rtw_rhashtable_walk_next(&iter))) {
+ if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN)
+ continue;
+ if (IS_ERR(mpath))
+ break;
+
+ if (_rtw_memcmp(mpath->mpp, proxy, ETH_ALEN) == _TRUE)
+ __rtw_mesh_path_del(tbl, mpath);
+ }
+out:
+ rtw_rhashtable_walk_stop(&iter);
+ rtw_rhashtable_walk_exit(&iter);
+}
+
+static void rtw_table_flush_by_iface(struct rtw_mesh_table *tbl)
+{
+ struct rtw_mesh_path *mpath;
+ rtw_rhashtable_iter iter;
+ int ret;
+
+ if (!tbl)
+ return;
+
+ ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);
+ if (ret)
+ return;
+
+ ret = rtw_rhashtable_walk_start(&iter);
+ if (ret && ret != -EAGAIN)
+ goto out;
+
+ while ((mpath = rtw_rhashtable_walk_next(&iter))) {
+ if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN)
+ continue;
+ if (IS_ERR(mpath))
+ break;
+ __rtw_mesh_path_del(tbl, mpath);
+ }
+out:
+ rtw_rhashtable_walk_stop(&iter);
+ rtw_rhashtable_walk_exit(&iter);
+}
+
+/**
+ * rtw_mesh_path_flush_by_iface - Deletes all mesh paths associated with a given iface
+ *
+ * This function deletes both mesh paths as well as mesh portal paths.
+ *
+ * @sdata: interface data to match
+ *
+ */
+void rtw_mesh_path_flush_by_iface(_adapter *adapter)
+{
+ rtw_table_flush_by_iface(adapter->mesh_info.mesh_paths);
+ rtw_table_flush_by_iface(adapter->mesh_info.mpp_paths);
+}
+
+/**
+ * rtw_table_path_del - delete a path from the mesh or mpp table
+ *
+ * @tbl: mesh or mpp path table
+ * @sdata: local subif
+ * @addr: dst address (ETH_ALEN length)
+ *
+ * Returns: 0 if successful
+ */
+static int rtw_table_path_del(struct rtw_mesh_table *tbl,
+ const u8 *addr)
+{
+ struct rtw_mesh_path *mpath;
+
+ if (!tbl)
+ return -ENXIO;
+
+ rtw_rcu_read_lock();
+ mpath = rtw_rhashtable_lookup_fast(&tbl->rhead, addr, rtw_mesh_rht_params);
+ if (!mpath) {
+ rtw_rcu_read_unlock();
+ return -ENXIO;
+ }
+
+ __rtw_mesh_path_del(tbl, mpath);
+ rtw_rcu_read_unlock();
+ return 0;
+}
+
+
+/**
+ * rtw_mesh_path_del - delete a mesh path from the table
+ *
+ * @addr: dst address (ETH_ALEN length)
+ * @sdata: local subif
+ *
+ * Returns: 0 if successful
+ */
+int rtw_mesh_path_del(_adapter *adapter, const u8 *addr)
+{
+ int err;
+
+ /* flush relevant mpp entries first */
+ rtw_mpp_flush_by_proxy(adapter, addr);
+
+ err = rtw_table_path_del(adapter->mesh_info.mesh_paths, addr);
+ adapter->mesh_info.mesh_paths_generation++;
+ return err;
+}
+
+/**
+ * rtw_mesh_path_tx_pending - sends pending frames in a mesh path queue
+ *
+ * @mpath: mesh path to activate
+ *
+ * Locking: the state_lock of the mpath structure must NOT be held when calling
+ * this function.
+ */
+void rtw_mesh_path_tx_pending(struct rtw_mesh_path *mpath)
+{
+ if (mpath->flags & RTW_MESH_PATH_ACTIVE) {
+ struct rtw_mesh_info *minfo = &mpath->adapter->mesh_info;
+ _list q;
+ u32 q_len = 0;
+
+ _rtw_init_listhead(&q);
+
+ /* move to local queue */
+ enter_critical_bh(&mpath->frame_queue.lock);
+ if (mpath->frame_queue_len) {
+ rtw_list_splice_init(&mpath->frame_queue.queue, &q);
+ q_len = mpath->frame_queue_len;
+ mpath->frame_queue_len = 0;
+ }
+ exit_critical_bh(&mpath->frame_queue.lock);
+
+ if (q_len) {
+ /* move to mpath_tx_queue */
+ enter_critical_bh(&minfo->mpath_tx_queue.lock);
+ rtw_list_splice_tail(&q, &minfo->mpath_tx_queue.queue);
+ minfo->mpath_tx_queue_len += q_len;
+ exit_critical_bh(&minfo->mpath_tx_queue.lock);
+
+ /* schedule mpath_tx_tasklet */
+ tasklet_hi_schedule(&minfo->mpath_tx_tasklet);
+ }
+ }
+}
+
+/**
+ * rtw_mesh_path_send_to_gates - sends pending frames to all known mesh gates
+ *
+ * @mpath: mesh path whose queue will be emptied
+ *
+ * If there is only one gate, the frames are transferred from the failed mpath
+ * queue to that gate's queue. If there are more than one gates, the frames
+ * are copied from each gate to the next. After frames are copied, the
+ * mpath queues are emptied onto the transmission queue.
+ */
+int rtw_mesh_path_send_to_gates(struct rtw_mesh_path *mpath)
+{
+ _adapter *adapter = mpath->adapter;
+ struct rtw_mesh_table *tbl;
+ struct rtw_mesh_path *from_mpath = mpath;
+ struct rtw_mesh_path *gate;
+ bool copy = false;
+ rtw_hlist_node *node;
+
+ tbl = adapter->mesh_info.mesh_paths;
+ if (!tbl)
+ return 0;
+
+ rtw_rcu_read_lock();
+ rtw_hlist_for_each_entry_rcu(gate, node, &tbl->known_gates, gate_list) {
+ if (gate->flags & RTW_MESH_PATH_ACTIVE) {
+ RTW_MPATH_DBG(FUNC_ADPT_FMT" Forwarding to %pM\n",
+ FUNC_ADPT_ARG(adapter), gate->dst);
+ rtw_mesh_path_move_to_queue(gate, from_mpath, copy);
+ from_mpath = gate;
+ copy = true;
+ } else {
+ RTW_MPATH_DBG(
+ FUNC_ADPT_FMT" Not forwarding to %pM (flags %#x)\n",
+ FUNC_ADPT_ARG(adapter), gate->dst, gate->flags);
+ }
+ }
+
+ rtw_hlist_for_each_entry_rcu(gate, node, &tbl->known_gates, gate_list) {
+ RTW_MPATH_DBG(FUNC_ADPT_FMT" Sending to %pM\n",
+ FUNC_ADPT_ARG(adapter), gate->dst);
+ rtw_mesh_path_tx_pending(gate);
+ }
+ rtw_rcu_read_unlock();
+
+ return (from_mpath == mpath) ? -EHOSTUNREACH : 0;
+}
+
+/**
+ * rtw_mesh_path_discard_frame - discard a frame whose path could not be resolved
+ *
+ * @skb: frame to discard
+ * @sdata: network subif the frame was to be sent through
+ *
+ * Locking: the function must me called within a rcu_read_lock region
+ */
+void rtw_mesh_path_discard_frame(_adapter *adapter,
+ struct xmit_frame *xframe)
+{
+ rtw_free_xmitframe(&adapter->xmitpriv, xframe);
+ adapter->mesh_info.mshstats.dropped_frames_no_route++;
+}
+
+/**
+ * rtw_mesh_path_flush_pending - free the pending queue of a mesh path
+ *
+ * @mpath: mesh path whose queue has to be freed
+ *
+ * Locking: the function must me called within a rcu_read_lock region
+ */
+void rtw_mesh_path_flush_pending(struct rtw_mesh_path *mpath)
+{
+ struct xmit_frame *xframe;
+ _list *list, *head;
+ _list tmp;
+
+ _rtw_init_listhead(&tmp);
+
+ enter_critical_bh(&mpath->frame_queue.lock);
+ rtw_list_splice_init(&mpath->frame_queue.queue, &tmp);
+ mpath->frame_queue_len = 0;
+ exit_critical_bh(&mpath->frame_queue.lock);
+
+ head = &tmp;
+ list = get_next(head);
+ while (rtw_end_of_queue_search(head, list) == _FALSE) {
+ xframe = LIST_CONTAINOR(list, struct xmit_frame, list);
+ list = get_next(list);
+ rtw_list_delete(&xframe->list);
+ rtw_mesh_path_discard_frame(mpath->adapter, xframe);
+ }
+}
+
+/**
+ * rtw_mesh_path_fix_nexthop - force a specific next hop for a mesh path
+ *
+ * @mpath: the mesh path to modify
+ * @next_hop: the next hop to force
+ *
+ * Locking: this function must be called holding mpath->state_lock
+ */
+void rtw_mesh_path_fix_nexthop(struct rtw_mesh_path *mpath, struct sta_info *next_hop)
+{
+ enter_critical_bh(&mpath->state_lock);
+ rtw_mesh_path_assign_nexthop(mpath, next_hop);
+ mpath->sn = 0xffff;
+ mpath->metric = 0;
+ mpath->hop_count = 0;
+ mpath->exp_time = 0;
+ mpath->flags = RTW_MESH_PATH_FIXED | RTW_MESH_PATH_SN_VALID;
+ rtw_mesh_path_activate(mpath);
+ exit_critical_bh(&mpath->state_lock);
+ rtw_ewma_err_rate_init(&next_hop->metrics.err_rate);
+ /* init it at a low value - 0 start is tricky */
+ rtw_ewma_err_rate_add(&next_hop->metrics.err_rate, 1);
+ rtw_mesh_path_tx_pending(mpath);
+}
+
+int rtw_mesh_pathtbl_init(_adapter *adapter)
+{
+ struct rtw_mesh_table *tbl_path, *tbl_mpp;
+ int ret;
+
+ tbl_path = rtw_mesh_table_alloc();
+ if (!tbl_path)
+ return -ENOMEM;
+
+ tbl_mpp = rtw_mesh_table_alloc();
+ if (!tbl_mpp) {
+ ret = -ENOMEM;
+ goto free_path;
+ }
+
+ rtw_rhashtable_init(&tbl_path->rhead, &rtw_mesh_rht_params);
+ rtw_rhashtable_init(&tbl_mpp->rhead, &rtw_mesh_rht_params);
+
+ adapter->mesh_info.mesh_paths = tbl_path;
+ adapter->mesh_info.mpp_paths = tbl_mpp;
+
+ return 0;
+
+free_path:
+ rtw_mesh_table_free(tbl_path);
+ return ret;
+}
+
+static
+void rtw_mesh_path_tbl_expire(_adapter *adapter,
+ struct rtw_mesh_table *tbl)
+{
+ struct rtw_mesh_path *mpath;
+ rtw_rhashtable_iter iter;
+ int ret;
+
+ if (!tbl)
+ return;
+
+ ret = rtw_rhashtable_walk_enter(&tbl->rhead, &iter);
+ if (ret)
+ return;
+
+ ret = rtw_rhashtable_walk_start(&iter);
+ if (ret && ret != -EAGAIN)
+ goto out;
+
+ while ((mpath = rtw_rhashtable_walk_next(&iter))) {
+ if (IS_ERR(mpath) && PTR_ERR(mpath) == -EAGAIN)
+ continue;
+ if (IS_ERR(mpath))
+ break;
+ if ((!(mpath->flags & RTW_MESH_PATH_RESOLVING)) &&
+ (!(mpath->flags & RTW_MESH_PATH_FIXED)) &&
+ rtw_time_after(rtw_get_current_time(), mpath->exp_time + RTW_MESH_PATH_EXPIRE))
+ __rtw_mesh_path_del(tbl, mpath);
+
+ if (mpath->is_gate && /* need not to deal with non-gate case */
+ rtw_time_after(rtw_get_current_time(), mpath->gate_timeout)) {
+ RTW_MPATH_DBG(FUNC_ADPT_FMT"mpath [%pM] expired systime is %lu systime is %lu\n",
+ FUNC_ADPT_ARG(adapter), mpath->dst,
+ mpath->gate_timeout, rtw_get_current_time());
+ enter_critical_bh(&mpath->state_lock);
+ if (mpath->gate_asked) { /* asked gate before */
+ rtw_mesh_gate_del(tbl, mpath);
+ exit_critical_bh(&mpath->state_lock);
+ } else {
+ mpath->gate_asked = true;
+ mpath->gate_timeout = rtw_get_current_time() + rtw_ms_to_systime(mpath->gate_ann_int);
+ exit_critical_bh(&mpath->state_lock);
+ rtw_mesh_queue_preq(mpath, RTW_PREQ_Q_F_START | RTW_PREQ_Q_F_REFRESH);
+ RTW_MPATH_DBG(FUNC_ADPT_FMT"mpath [%pM] ask mesh gate existence (is_root=%d)\n",
+ FUNC_ADPT_ARG(adapter), mpath->dst, mpath->is_root);
+ }
+ }
+ }
+
+out:
+ rtw_rhashtable_walk_stop(&iter);
+ rtw_rhashtable_walk_exit(&iter);
+}
+
+void rtw_mesh_path_expire(_adapter *adapter)
+{
+ rtw_mesh_path_tbl_expire(adapter, adapter->mesh_info.mesh_paths);
+ rtw_mesh_path_tbl_expire(adapter, adapter->mesh_info.mpp_paths);
+}
+
+void rtw_mesh_pathtbl_unregister(_adapter *adapter)
+{
+ if (adapter->mesh_info.mesh_paths) {
+ rtw_mesh_table_free(adapter->mesh_info.mesh_paths);
+ adapter->mesh_info.mesh_paths = NULL;
+ }
+
+ if (adapter->mesh_info.mpp_paths) {
+ rtw_mesh_table_free(adapter->mesh_info.mpp_paths);
+ adapter->mesh_info.mpp_paths = NULL;
+ }
+}
+#endif /* CONFIG_RTW_MESH */
+
diff --git a/core/mesh/rtw_mesh_pathtbl.h b/core/mesh/rtw_mesh_pathtbl.h
new file mode 100644
index 0000000..c53477d
--- /dev/null
+++ b/core/mesh/rtw_mesh_pathtbl.h
@@ -0,0 +1,193 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __RTW_MESH_PATHTBL_H_
+#define __RTW_MESH_PATHTBL_H_
+
+#ifndef DBG_RTW_MPATH
+#define DBG_RTW_MPATH 1
+#endif
+#if DBG_RTW_MPATH
+#define RTW_MPATH_DBG(fmt, arg...) RTW_PRINT(fmt, ##arg)
+#else
+#define RTW_MPATH_DBG(fmt, arg...) do {} while (0)
+#endif
+
+/**
+ * enum rtw_mesh_path_flags - mesh path flags
+ *
+ * @RTW_MESH_PATH_ACTIVE: the mesh path can be used for forwarding
+ * @RTW_MESH_PATH_RESOLVING: the discovery process is running for this mesh path
+ * @RTW_MESH_PATH_SN_VALID: the mesh path contains a valid destination sequence
+ * number
+ * @RTW_MESH_PATH_FIXED: the mesh path has been manually set and should not be
+ * modified
+ * @RTW_MESH_PATH_RESOLVED: the mesh path can has been resolved
+ * @RTW_MESH_PATH_REQ_QUEUED: there is an unsent path request for this destination
+ * already queued up, waiting for the discovery process to start.
+ * @RTW_MESH_PATH_DELETED: the mesh path has been deleted and should no longer
+ * be used
+ *
+ * RTW_MESH_PATH_RESOLVED is used by the mesh path timer to
+ * decide when to stop or cancel the mesh path discovery.
+ */
+enum rtw_mesh_path_flags {
+ RTW_MESH_PATH_ACTIVE = BIT(0),
+ RTW_MESH_PATH_RESOLVING = BIT(1),
+ RTW_MESH_PATH_SN_VALID = BIT(2),
+ RTW_MESH_PATH_FIXED = BIT(3),
+ RTW_MESH_PATH_RESOLVED = BIT(4),
+ RTW_MESH_PATH_REQ_QUEUED = BIT(5),
+ RTW_MESH_PATH_DELETED = BIT(6),
+};
+
+/**
+ * struct rtw_mesh_path - mesh path structure
+ *
+ * @dst: mesh path destination mac address
+ * @mpp: mesh proxy mac address
+ * @rhash: rhashtable list pointer
+ * @gate_list: list pointer for known gates list
+ * @sdata: mesh subif
+ * @next_hop: mesh neighbor to which frames for this destination will be
+ * forwarded
+ * @timer: mesh path discovery timer
+ * @frame_queue: pending queue for frames sent to this destination while the
+ * path is unresolved
+ * @rcu: rcu head for freeing mesh path
+ * @sn: target sequence number
+ * @metric: current metric to this destination
+ * @hop_count: hops to destination
+ * @exp_time: in jiffies, when the path will expire or when it expired
+ * @discovery_timeout: timeout (lapse in jiffies) used for the last discovery
+ * retry
+ * @discovery_retries: number of discovery retries
+ * @flags: mesh path flags, as specified on &enum rtw_mesh_path_flags
+ * @state_lock: mesh path state lock used to protect changes to the
+ * mpath itself. No need to take this lock when adding or removing
+ * an mpath to a hash bucket on a path table.
+ * @rann_snd_addr: the RANN sender address
+ * @rann_metric: the aggregated path metric towards the root node
+ * @last_preq_to_root: Timestamp of last PREQ sent to root
+ * @is_root: the destination station of this path is a root node
+ * @is_gate: the destination station of this path is a mesh gate
+ *
+ *
+ * The dst address is unique in the mesh path table. Since the mesh_path is
+ * protected by RCU, deleting the next_hop STA must remove / substitute the
+ * mesh_path structure and wait until that is no longer reachable before
+ * destroying the STA completely.
+ */
+struct rtw_mesh_path {
+ u8 dst[ETH_ALEN];
+ u8 mpp[ETH_ALEN]; /* used for MPP or MAP */
+ rtw_rhash_head rhash;
+ rtw_hlist_node gate_list;
+ _adapter *adapter;
+ struct sta_info __rcu *next_hop;
+ _timer timer;
+ _queue frame_queue;
+ u32 frame_queue_len;
+ rtw_rcu_head rcu;
+ u32 sn;
+ u32 metric;
+ u8 hop_count;
+ systime exp_time;
+ systime discovery_timeout;
+ systime gate_timeout;
+ u32 gate_ann_int; /* gate announce interval */
+ u8 discovery_retries;
+ enum rtw_mesh_path_flags flags;
+ _lock state_lock;
+ u8 rann_snd_addr[ETH_ALEN];
+ u32 rann_metric;
+ unsigned long last_preq_to_root;
+ bool is_root;
+ bool is_gate;
+ bool gate_asked;
+};
+
+/**
+ * struct rtw_mesh_table
+ *
+ * @known_gates: list of known mesh gates and their mpaths by the station. The
+ * gate's mpath may or may not be resolved and active.
+ * @gates_lock: protects updates to known_gates
+ * @rhead: the rhashtable containing struct mesh_paths, keyed by dest addr
+ * @entries: number of entries in the table
+ */
+struct rtw_mesh_table {
+ rtw_hlist_head known_gates;
+ _lock gates_lock;
+ rtw_rhashtable rhead;
+ ATOMIC_T entries;
+};
+
+#define RTW_MESH_PATH_EXPIRE (600 * HZ)
+
+/* Maximum number of paths per interface */
+#define RTW_MESH_MAX_MPATHS 1024
+
+/* Number of frames buffered per destination for unresolved destinations */
+#define RTW_MESH_FRAME_QUEUE_LEN 10
+
+int rtw_mesh_nexthop_lookup(_adapter *adapter,
+ const u8 *mda, const u8 *msa, u8 *ra);
+int rtw_mesh_nexthop_resolve(_adapter *adapter,
+ struct xmit_frame *xframe);
+
+struct rtw_mesh_path *rtw_mesh_path_lookup(_adapter *adapter,
+ const u8 *dst);
+struct rtw_mesh_path *rtw_mpp_path_lookup(_adapter *adapter,
+ const u8 *dst);
+int rtw_mpp_path_add(_adapter *adapter,
+ const u8 *dst, const u8 *mpp);
+struct rtw_mesh_path *
+rtw_mesh_path_lookup_by_idx(_adapter *adapter, int idx);
+struct rtw_mesh_path *
+rtw_mpp_path_lookup_by_idx(_adapter *adapter, int idx);
+void rtw_mesh_path_fix_nexthop(struct rtw_mesh_path *mpath, struct sta_info *next_hop);
+void rtw_mesh_path_expire(_adapter *adapter);
+
+struct rtw_mesh_path *
+rtw_mesh_path_add(_adapter *adapter, const u8 *dst);
+
+int rtw_mesh_path_add_gate(struct rtw_mesh_path *mpath);
+void rtw_mesh_gate_del(struct rtw_mesh_table *tbl, struct rtw_mesh_path *mpath);
+bool rtw_mesh_gate_search(struct rtw_mesh_table *tbl, const u8 *addr);
+int rtw_mesh_path_send_to_gates(struct rtw_mesh_path *mpath);
+int rtw_mesh_gate_num(_adapter *adapter);
+
+void rtw_mesh_plink_broken(struct sta_info *sta);
+
+void rtw_mesh_path_assign_nexthop(struct rtw_mesh_path *mpath, struct sta_info *sta);
+void rtw_mesh_path_flush_pending(struct rtw_mesh_path *mpath);
+void rtw_mesh_path_tx_pending(struct rtw_mesh_path *mpath);
+int rtw_mesh_pathtbl_init(_adapter *adapter);
+void rtw_mesh_pathtbl_unregister(_adapter *adapter);
+int rtw_mesh_path_del(_adapter *adapter, const u8 *addr);
+
+void rtw_mesh_path_flush_by_nexthop(struct sta_info *sta);
+void rtw_mesh_path_discard_frame(_adapter *adapter,
+ struct xmit_frame *xframe);
+
+static inline void rtw_mesh_path_activate(struct rtw_mesh_path *mpath)
+{
+ mpath->flags |= RTW_MESH_PATH_ACTIVE | RTW_MESH_PATH_RESOLVED;
+}
+
+void rtw_mesh_path_flush_by_iface(_adapter *adapter);
+
+#endif /* __RTW_MESH_PATHTBL_H_ */
+
diff --git a/core/rtw_ap.c b/core/rtw_ap.c
index d697688..b110139 100644
--- a/core/rtw_ap.c
+++ b/core/rtw_ap.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,16 +11,11 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#define _RTW_AP_C_
#include
-
+#include
#ifdef CONFIG_AP_MODE
@@ -50,6 +45,49 @@ void free_mlme_ap_info(_adapter *padapter)
}
+/*
+* Set TIM IE
+* return length of total TIM IE
+*/
+u8 rtw_set_tim_ie(u8 dtim_cnt, u8 dtim_period
+ , const u8 *tim_bmp, u8 tim_bmp_len, u8 *tim_ie)
+{
+ u8 *p = tim_ie;
+ u8 i, n1, n2;
+ u8 bmp_len;
+
+ if (rtw_bmp_not_empty(tim_bmp, tim_bmp_len)) {
+ /* find the first nonzero octet in tim_bitmap */
+ for (i = 0; i < tim_bmp_len; i++)
+ if (tim_bmp[i])
+ break;
+ n1 = i & 0xFE;
+
+ /* find the last nonzero octet in tim_bitmap, except octet 0 */
+ for (i = tim_bmp_len - 1; i > 0; i--)
+ if (tim_bmp[i])
+ break;
+ n2 = i;
+ bmp_len = n2 - n1 + 1;
+ } else {
+ n1 = n2 = 0;
+ bmp_len = 1;
+ }
+
+ *p++ = WLAN_EID_TIM;
+ *p++ = 2 + 1 + bmp_len;
+ *p++ = dtim_cnt;
+ *p++ = dtim_period;
+ *p++ = (rtw_bmp_is_set(tim_bmp, tim_bmp_len, 0) ? BIT0 : 0) | n1;
+ _rtw_memcpy(p, tim_bmp + n1, bmp_len);
+
+#if 0
+ RTW_INFO("n1:%u, n2:%u, bmp_offset:%u, bmp_len:%u\n", n1, n2, n1 / 2, bmp_len);
+ RTW_INFO_DUMP("tim_ie: ", tim_ie + 2, 2 + 1 + bmp_len);
+#endif
+ return 2 + 2 + 1 + bmp_len;
+}
+
static void update_BCNTIM(_adapter *padapter)
{
struct sta_priv *pstapriv = &padapter->stapriv;
@@ -62,15 +100,12 @@ static void update_BCNTIM(_adapter *padapter)
/* update TIM IE */
- /* if(pstapriv->tim_bitmap) */
+ /* if(rtw_tim_map_anyone_be_set(padapter, pstapriv->tim_bitmap)) */
#endif
if (_TRUE) {
u8 *p, *dst_ie, *premainder_ie = NULL, *pbackup_remainder_ie = NULL;
- u16 tim_bitmap_le;
uint offset, tmp_len, tim_ielen, tim_ie_offset, remainder_ielen;
- tim_bitmap_le = cpu_to_le16(pstapriv->tim_bitmap);
-
p = rtw_get_ie(pie + _FIXED_IE_LENGTH_, _TIM_IE_, &tim_ielen, pnetwork_mlmeext->IELength - _FIXED_IE_LENGTH_);
if (p != NULL && tim_ielen > 0) {
tim_ielen += 2;
@@ -117,39 +152,8 @@ static void update_BCNTIM(_adapter *padapter)
_rtw_memcpy(pbackup_remainder_ie, premainder_ie, remainder_ielen);
}
- *dst_ie++ = _TIM_IE_;
-
- if ((pstapriv->tim_bitmap & 0xff00) && (pstapriv->tim_bitmap & 0x00fe))
- tim_ielen = 5;
- else
- tim_ielen = 4;
-
- *dst_ie++ = tim_ielen;
-
- *dst_ie++ = 0;/*DTIM count*/
- *dst_ie++ = 1;/*DTIM period*/
-
- if (pstapriv->tim_bitmap & BIT(0))/*for bc/mc frames*/
- *dst_ie++ = BIT(0);/*bitmap ctrl */
- else
- *dst_ie++ = 0;
-
- if (tim_ielen == 4) {
- u8 pvb = 0;
-
- if (pstapriv->tim_bitmap & 0x00fe)
- pvb = (u8)tim_bitmap_le;
- else if (pstapriv->tim_bitmap & 0xff00)
- pvb = (u8)(tim_bitmap_le >> 8);
- else
- pvb = (u8)tim_bitmap_le;
-
- *dst_ie++ = pvb;
-
- } else if (tim_ielen == 5) {
- _rtw_memcpy(dst_ie, &tim_bitmap_le, 2);
- dst_ie += 2;
- }
+ /* append TIM IE */
+ dst_ie += rtw_set_tim_ie(0, 1, pstapriv->tim_bitmap, pstapriv->aid_bmp_len, dst_ie);
/*copy remainder IE*/
if (pbackup_remainder_ie) {
@@ -274,8 +278,8 @@ u8 chk_sta_is_alive(struct sta_info *psta)
u8 ret = _FALSE;
#ifdef DBG_EXPIRATION_CHK
RTW_INFO("sta:"MAC_FMT", rssi:%d, rx:"STA_PKTS_FMT", expire_to:%u, %s%ssq_len:%u\n"
- , MAC_ARG(psta->hwaddr)
- , psta->rssi_stat.UndecoratedSmoothedPWDB
+ , MAC_ARG(psta->cmn.mac_addr)
+ , psta->cmn.rssi_stat.rssi
/* , STA_RX_PKTS_ARG(psta) */
, STA_RX_PKTS_DIFF_ARG(psta)
, psta->expire_to
@@ -310,6 +314,18 @@ void expire_timeout_chk(_adapter *padapter)
char chk_alive_list[NUM_STA];
int i;
+#ifdef CONFIG_RTW_MESH
+ if (MLME_IS_MESH(padapter)
+ && check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE)
+ ) {
+ struct rtw_mesh_cfg *mcfg = &padapter->mesh_cfg;
+
+ rtw_mesh_path_expire(padapter);
+
+ if (!mcfg->plink_timeout)
+ return;
+ }
+#endif
#ifdef CONFIG_MCC_MODE
/* then driver may check fail due to not recv client's frame under sitesurvey,
@@ -338,7 +354,7 @@ void expire_timeout_chk(_adapter *padapter)
#ifdef CONFIG_ATMEL_RC_PATCH
- if (_TRUE == _rtw_memcmp((void *)(pstapriv->atmel_rc_pattern), (void *)(psta->hwaddr), ETH_ALEN))
+ if (_rtw_memcmp((void *)(pstapriv->atmel_rc_pattern), (void *)(psta->cmn.mac_addr), ETH_ALEN) == _TRUE)
continue;
if (psta->flag_atmel_rc)
continue;
@@ -350,7 +366,8 @@ void expire_timeout_chk(_adapter *padapter)
pstapriv->auth_list_cnt--;
RTW_INFO("auth expire %02X%02X%02X%02X%02X%02X\n",
- psta->hwaddr[0], psta->hwaddr[1], psta->hwaddr[2], psta->hwaddr[3], psta->hwaddr[4], psta->hwaddr[5]);
+ psta->cmn.mac_addr[0], psta->cmn.mac_addr[1], psta->cmn.mac_addr[2],
+ psta->cmn.mac_addr[3], psta->cmn.mac_addr[4], psta->cmn.mac_addr[5]);
_exit_critical_bh(&pstapriv->auth_list_lock, &irqL);
@@ -385,8 +402,8 @@ void expire_timeout_chk(_adapter *padapter)
plist = get_next(plist);
#ifdef CONFIG_ATMEL_RC_PATCH
RTW_INFO("%s:%d psta=%p, %02x,%02x||%02x,%02x \n\n", __func__, __LINE__,
- psta, pstapriv->atmel_rc_pattern[0], pstapriv->atmel_rc_pattern[5], psta->hwaddr[0], psta->hwaddr[5]);
- if (_TRUE == _rtw_memcmp((void *)pstapriv->atmel_rc_pattern, (void *)(psta->hwaddr), ETH_ALEN))
+ psta, pstapriv->atmel_rc_pattern[0], pstapriv->atmel_rc_pattern[5], psta->cmn.mac_addr[0], psta->cmn.mac_addr[5]);
+ if (_rtw_memcmp((void *)pstapriv->atmel_rc_pattern, (void *)(psta->cmn.mac_addr), ETH_ALEN) == _TRUE)
continue;
if (psta->flag_atmel_rc)
continue;
@@ -421,7 +438,7 @@ void expire_timeout_chk(_adapter *padapter)
RTW_INFO("asoc check by DELBA/ADDBA! (%d s)\n", (pstapriv->expire_to - psta->expire_to) * 2);
psta->under_exist_checking = 1;
/* tear down TX AMPDU */
- send_delba(padapter, 1, psta->hwaddr);/* */ /* originator */
+ send_delba(padapter, 1, psta->cmn.mac_addr);/* */ /* originator */
psta->htpriv.agg_enable_bitmap = 0x0;/* reset */
psta->htpriv.candidate_tid_bitmap = 0x0;/* reset */
}
@@ -473,7 +490,7 @@ void expire_timeout_chk(_adapter *padapter)
RTW_INFO("issue addba_req to check if sta alive, keep_alive_trycnt=%d\n", psta->keep_alive_trycnt);
- issue_addba_req(padapter, psta->hwaddr, (u8)priority);
+ issue_addba_req(padapter, psta->cmn.mac_addr, (u8)priority);
_set_timer(&psta->addba_retry_timer, ADDBA_TO);
@@ -497,38 +514,32 @@ void expire_timeout_chk(_adapter *padapter)
psta->expire_to = pstapriv->expire_to;
psta->state |= WIFI_STA_ALIVE_CHK_STATE;
- /* RTW_INFO("alive chk, sta:" MAC_FMT " is at ps mode!\n", MAC_ARG(psta->hwaddr)); */
+ /* RTW_INFO("alive chk, sta:" MAC_FMT " is at ps mode!\n", MAC_ARG(psta->cmn.mac_addr)); */
/* to update bcn with tim_bitmap for this station */
- pstapriv->tim_bitmap |= BIT(psta->aid);
+ rtw_tim_map_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid);
update_beacon(padapter, _TIM_IE_, NULL, _TRUE);
if (!pmlmeext->active_keep_alive_check)
continue;
}
}
-#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
- if (pmlmeext->active_keep_alive_check) {
+
+ {
int stainfo_offset;
stainfo_offset = rtw_stainfo_offset(pstapriv, psta);
if (stainfo_offset_valid(stainfo_offset))
chk_alive_list[chk_alive_num++] = stainfo_offset;
-
continue;
}
-#endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */
- rtw_list_delete(&psta->asoc_list);
- pstapriv->asoc_list_cnt--;
- RTW_INFO("asoc expire "MAC_FMT", state=0x%x\n", MAC_ARG(psta->hwaddr), psta->state);
- updated = ap_free_sta(padapter, psta, _FALSE, WLAN_REASON_DEAUTH_LEAVING, _TRUE);
} else {
/* TODO: Aging mechanism to digest frames in sleep_q to avoid running out of xmitframe */
if (psta->sleepq_len > (NR_XMITFRAME / pstapriv->asoc_list_cnt)
&& padapter->xmitpriv.free_xmitframe_cnt < ((NR_XMITFRAME / pstapriv->asoc_list_cnt) / 2)
) {
RTW_INFO("%s sta:"MAC_FMT", sleepq_len:%u, free_xmitframe_cnt:%u, asoc_list_cnt:%u, clear sleep_q\n", __func__
- , MAC_ARG(psta->hwaddr)
+ , MAC_ARG(psta->cmn.mac_addr)
, psta->sleepq_len, padapter->xmitpriv.free_xmitframe_cnt, pstapriv->asoc_list_cnt);
wakeup_sta_to_xmit(padapter, psta);
}
@@ -537,210 +548,140 @@ void expire_timeout_chk(_adapter *padapter)
_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
if (chk_alive_num) {
-
- u8 backup_oper_channel = 0, switch_channel = _TRUE;
+ u8 backup_ch = 0, backup_bw = 0, backup_offset = 0;
+ u8 union_ch = 0, union_bw = 0, union_offset = 0;
+ u8 switch_channel_by_drv = _TRUE;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+ char del_asoc_list[NUM_STA];
-#ifdef CONFIG_MCC_MODE
- if (MCC_EN(padapter)) {
- /* driver doesn't switch channel under MCC */
- if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
- switch_channel = _FALSE;
- }
-#endif
- /* switch to correct channel of current network before issue keep-alive frames */
- if (switch_channel) {
- if (rtw_get_oper_ch(padapter) != pmlmeext->cur_channel) {
- backup_oper_channel = rtw_get_oper_ch(padapter);
- SelectChannel(padapter, pmlmeext->cur_channel);
+ _rtw_memset(del_asoc_list, NUM_STA, NUM_STA);
+
+ #ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
+ if (pmlmeext->active_keep_alive_check) {
+ #ifdef CONFIG_MCC_MODE
+ if (MCC_EN(padapter)) {
+ /* driver doesn't switch channel under MCC */
+ if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
+ switch_channel_by_drv = _FALSE;
+ }
+ #endif
+
+ if (!rtw_mi_get_ch_setting_union(padapter, &union_ch, &union_bw, &union_offset)
+ || pmlmeext->cur_channel != union_ch)
+ switch_channel_by_drv = _FALSE;
+
+ /* switch to correct channel of current network before issue keep-alive frames */
+ if (switch_channel_by_drv == _TRUE && rtw_get_oper_ch(padapter) != pmlmeext->cur_channel) {
+ backup_ch = rtw_get_oper_ch(padapter);
+ backup_bw = rtw_get_oper_bw(padapter);
+ backup_offset = rtw_get_oper_choffset(padapter);
+ set_channel_bwmode(padapter, union_ch, union_offset, union_bw);
}
}
+ #endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */
- /* issue null data to check sta alive*/
+ /* check loop */
for (i = 0; i < chk_alive_num; i++) {
int ret = _FAIL;
psta = rtw_get_stainfo_by_offset(pstapriv, chk_alive_list[i]);
-#ifdef CONFIG_ATMEL_RC_PATCH
- if (_TRUE == _rtw_memcmp(pstapriv->atmel_rc_pattern, psta->hwaddr, ETH_ALEN))
+
+ #ifdef CONFIG_ATMEL_RC_PATCH
+ if (_rtw_memcmp(pstapriv->atmel_rc_pattern, psta->cmn.mac_addr, ETH_ALEN) == _TRUE)
continue;
if (psta->flag_atmel_rc)
continue;
-#endif
+ #endif
+
if (!(psta->state & _FW_LINKED))
continue;
- if (psta->state & WIFI_SLEEP_STATE)
- ret = issue_nulldata(padapter, psta->hwaddr, 0, 1, 50);
- else
- ret = issue_nulldata(padapter, psta->hwaddr, 0, 3, 50);
+ #ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
+ if (pmlmeext->active_keep_alive_check) {
+ /* issue null data to check sta alive*/
+ if (psta->state & WIFI_SLEEP_STATE)
+ ret = issue_nulldata(padapter, psta->cmn.mac_addr, 0, 1, 50);
+ else
+ ret = issue_nulldata(padapter, psta->cmn.mac_addr, 0, 3, 50);
- psta->keep_alive_trycnt++;
- if (ret == _SUCCESS) {
- RTW_INFO("asoc check, sta(" MAC_FMT ") is alive\n", MAC_ARG(psta->hwaddr));
- psta->expire_to = pstapriv->expire_to;
- psta->keep_alive_trycnt = 0;
- continue;
- } else if (psta->keep_alive_trycnt <= 3) {
- RTW_INFO("ack check for asoc expire, keep_alive_trycnt=%d\n", psta->keep_alive_trycnt);
- psta->expire_to = 1;
- continue;
+ psta->keep_alive_trycnt++;
+ if (ret == _SUCCESS) {
+ RTW_INFO("asoc check, sta(" MAC_FMT ") is alive\n", MAC_ARG(psta->cmn.mac_addr));
+ psta->expire_to = pstapriv->expire_to;
+ psta->keep_alive_trycnt = 0;
+ continue;
+ } else if (psta->keep_alive_trycnt <= 3) {
+ RTW_INFO("ack check for asoc expire, keep_alive_trycnt=%d\n", psta->keep_alive_trycnt);
+ psta->expire_to = 1;
+ continue;
+ }
}
+ #endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */
psta->keep_alive_trycnt = 0;
- RTW_INFO("asoc expire "MAC_FMT", state=0x%x\n", MAC_ARG(psta->hwaddr), psta->state);
+ del_asoc_list[i] = chk_alive_list[i];
_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
if (rtw_is_list_empty(&psta->asoc_list) == _FALSE) {
rtw_list_delete(&psta->asoc_list);
pstapriv->asoc_list_cnt--;
- updated = ap_free_sta(padapter, psta, _FALSE, WLAN_REASON_DEAUTH_LEAVING, _TRUE);
+ STA_SET_MESH_PLINK(psta, NULL);
}
_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+ }
+
+ /* delete loop */
+ for (i = 0; i < chk_alive_num; i++) {
+ u8 sta_addr[ETH_ALEN];
+
+ if (del_asoc_list[i] >= NUM_STA)
+ continue;
+ psta = rtw_get_stainfo_by_offset(pstapriv, del_asoc_list[i]);
+ _rtw_memcpy(sta_addr, psta->cmn.mac_addr, ETH_ALEN);
+
+ RTW_INFO("asoc expire "MAC_FMT", state=0x%x\n", MAC_ARG(psta->cmn.mac_addr), psta->state);
+ updated = ap_free_sta(padapter, psta, _FALSE, WLAN_REASON_DEAUTH_LEAVING, _FALSE);
+ #ifdef CONFIG_RTW_MESH
+ if (MLME_IS_MESH(padapter))
+ rtw_mesh_expire_peer(padapter, sta_addr);
+ #endif
}
- if (switch_channel) {
- if (backup_oper_channel > 0) /* back to the original operation channel */
- SelectChannel(padapter, backup_oper_channel);
+ #ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
+ if (pmlmeext->active_keep_alive_check) {
+ /* back to the original operation channel */
+ if (switch_channel_by_drv == _TRUE && backup_ch > 0)
+ set_channel_bwmode(padapter, backup_ch, backup_offset, backup_bw);
}
+ #endif
}
-#endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */
associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL);
}
-void add_RATid(_adapter *padapter, struct sta_info *psta, u8 rssi_level)
+void rtw_ap_update_sta_ra_info(_adapter *padapter, struct sta_info *psta)
{
int i;
u8 rf_type;
- unsigned char sta_band = 0, shortGIrate = _FALSE;
+ unsigned char sta_band = 0;
u64 tx_ra_bitmap = 0;
- struct ht_priv *psta_ht = NULL;
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
WLAN_BSSID_EX *pcur_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network;
-#ifdef CONFIG_80211N_HT
- if (psta)
- psta_ht = &psta->htpriv;
- else
+ if (!psta)
return;
-#endif /* CONFIG_80211N_HT */
if (!(psta->state & _FW_LINKED))
return;
-#if 0/* gtest */
- if (get_rf_mimo_mode(padapter) == RTL8712_RF_2T2R) {
- /* is this a 2r STA? */
- if ((pstat->tx_ra_bitmap & 0x0ff00000) != 0 && !(priv->pshare->has_2r_sta & BIT(pstat->aid))) {
- priv->pshare->has_2r_sta |= BIT(pstat->aid);
- if (rtw_read16(padapter, 0x102501f6) != 0xffff) {
- rtw_write16(padapter, 0x102501f6, 0xffff);
- reset_1r_sta_RA(priv, 0xffff);
- Switch_1SS_Antenna(priv, 3);
- }
- } else { /* bg or 1R STA? */
- if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11N) && pstat->ht_cap_len && priv->pshare->has_2r_sta == 0) {
- if (rtw_read16(padapter, 0x102501f6) != 0x7777) {
- /* MCS7 SGI */
- rtw_write16(padapter, 0x102501f6, 0x7777);
- reset_1r_sta_RA(priv, 0x7777);
- Switch_1SS_Antenna(priv, 2);
- }
- }
- }
-
- }
-
- if ((pstat->rssi_level < 1) || (pstat->rssi_level > 3)) {
- if (pstat->rssi >= priv->pshare->rf_ft_var.raGoDownUpper)
- pstat->rssi_level = 1;
- else if ((pstat->rssi >= priv->pshare->rf_ft_var.raGoDown20MLower) ||
- ((priv->pshare->is_40m_bw) && (pstat->ht_cap_len) &&
- (pstat->rssi >= priv->pshare->rf_ft_var.raGoDown40MLower) &&
- (pstat->ht_cap_buf.ht_cap_info & cpu_to_le16(_HTCAP_SUPPORT_CH_WDTH_))))
- pstat->rssi_level = 2;
- else
- pstat->rssi_level = 3;
- }
-
- /* rate adaptive by rssi */
- if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11N) && pstat->ht_cap_len) {
- if ((get_rf_mimo_mode(priv) == MIMO_1T2R) || (get_rf_mimo_mode(priv) == MIMO_1T1R)) {
- switch (pstat->rssi_level) {
- case 1:
- pstat->tx_ra_bitmap &= 0x100f0000;
- break;
- case 2:
- pstat->tx_ra_bitmap &= 0x100ff000;
- break;
- case 3:
- if (priv->pshare->is_40m_bw)
- pstat->tx_ra_bitmap &= 0x100ff005;
- else
- pstat->tx_ra_bitmap &= 0x100ff001;
-
- break;
- }
- } else {
- switch (pstat->rssi_level) {
- case 1:
- pstat->tx_ra_bitmap &= 0x1f0f0000;
- break;
- case 2:
- pstat->tx_ra_bitmap &= 0x1f0ff000;
- break;
- case 3:
- if (priv->pshare->is_40m_bw)
- pstat->tx_ra_bitmap &= 0x000ff005;
- else
- pstat->tx_ra_bitmap &= 0x000ff001;
-
- break;
- }
-
- /* Don't need to mask high rates due to new rate adaptive parameters */
- /* if (pstat->is_broadcom_sta) */ /* use MCS12 as the highest rate vs. Broadcom sta */
- /* pstat->tx_ra_bitmap &= 0x81ffffff; */
-
- /* NIC driver will report not supporting MCS15 and MCS14 in asoc req */
- /* if (pstat->is_rtl8190_sta && !pstat->is_2t_mimo_sta) */
- /* pstat->tx_ra_bitmap &= 0x83ffffff; */ /* if Realtek 1x2 sta, don't use MCS15 and MCS14 */
- }
- } else if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11G) && isErpSta(pstat)) {
- switch (pstat->rssi_level) {
- case 1:
- pstat->tx_ra_bitmap &= 0x00000f00;
- break;
- case 2:
- pstat->tx_ra_bitmap &= 0x00000ff0;
- break;
- case 3:
- pstat->tx_ra_bitmap &= 0x00000ff5;
- break;
- }
- } else
- pstat->tx_ra_bitmap &= 0x0000000d;
-
- /* disable tx short GI when station cannot rx MCS15(AP is 2T2R) */
- /* disable tx short GI when station cannot rx MCS7 (AP is 1T2R or 1T1R) */
- /* if there is only 1r STA and we are 2T2R, DO NOT mask SGI rate */
- if ((!(pstat->tx_ra_bitmap & 0x8000000) && (priv->pshare->has_2r_sta > 0) && (get_rf_mimo_mode(padapter) == RTL8712_RF_2T2R)) ||
- (!(pstat->tx_ra_bitmap & 0x80000) && (get_rf_mimo_mode(padapter) != RTL8712_RF_2T2R)))
- pstat->tx_ra_bitmap &= ~BIT(28);
-#endif
-
- rtw_hal_update_sta_rate_mask(padapter, psta);
- tx_ra_bitmap = psta->ra_mask;
-
- shortGIrate = query_ra_short_GI(psta);
+ rtw_hal_update_sta_ra_info(padapter, psta);
+ tx_ra_bitmap = psta->cmn.ra_info.ramask;
if (pcur_network->Configuration.DSConfig > 14) {
if (tx_ra_bitmap & 0xffff000)
- sta_band |= WIRELESS_11_5N ;
+ sta_band |= WIRELESS_11_5N;
if (tx_ra_bitmap & 0xff0)
sta_band |= WIRELESS_11A;
@@ -750,7 +691,6 @@ void add_RATid(_adapter *padapter, struct sta_info *psta, u8 rssi_level)
if (psta->vhtpriv.vht_option)
sta_band = WIRELESS_11_5AC;
#endif
-
} else {
if (tx_ra_bitmap & 0xffff000)
sta_band |= WIRELESS_11_24N;
@@ -763,23 +703,180 @@ void add_RATid(_adapter *padapter, struct sta_info *psta, u8 rssi_level)
}
psta->wireless_mode = sta_band;
- psta->raid = rtw_hal_networktype_to_raid(padapter, psta);
+ rtw_hal_update_sta_wset(padapter, psta);
+ RTW_INFO("%s=> mac_id:%d , tx_ra_bitmap:0x%016llx, networkType:0x%02x\n",
+ __FUNCTION__, psta->cmn.mac_id, tx_ra_bitmap, psta->wireless_mode);
+}
+
+#ifdef CONFIG_BMC_TX_RATE_SELECT
+u8 rtw_ap_find_mini_tx_rate(_adapter *adapter)
+{
+ _irqL irqL;
+ _list *phead, *plist;
+ u8 miini_tx_rate = ODM_RATEVHTSS4MCS9, sta_tx_rate;
+ struct sta_info *psta = NULL;
+ struct sta_priv *pstapriv = &adapter->stapriv;
- if (psta->aid < NUM_STA) {
- u8 arg[4] = {0};
+ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+ phead = &pstapriv->asoc_list;
+ plist = get_next(phead);
+ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+ psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
+ plist = get_next(plist);
- arg[0] = psta->mac_id;
- arg[1] = psta->raid;
- arg[2] = shortGIrate;
- arg[3] = psta->init_rate;
+ sta_tx_rate = psta->cmn.ra_info.curr_tx_rate & 0x7F;
+ if (sta_tx_rate < miini_tx_rate)
+ miini_tx_rate = sta_tx_rate;
+ }
+ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
- RTW_INFO("%s=> mac_id:%d , raid:%d , shortGIrate=%d, tx_ra_bitmap:0x%016llx, networkType:0x%02x\n",
- __FUNCTION__, psta->mac_id, psta->raid, shortGIrate, tx_ra_bitmap, psta->wireless_mode);
+ return miini_tx_rate;
+}
- rtw_hal_add_ra_tid(padapter, tx_ra_bitmap, arg, rssi_level);
- } else
- RTW_INFO("station aid %d exceed the max number\n", psta->aid);
+u8 rtw_ap_find_bmc_rate(_adapter *adapter, u8 tx_rate)
+{
+ PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
+ u8 tx_ini_rate = ODM_RATE6M;
+
+ switch (tx_rate) {
+ case ODM_RATEVHTSS3MCS9:
+ case ODM_RATEVHTSS3MCS8:
+ case ODM_RATEVHTSS3MCS7:
+ case ODM_RATEVHTSS3MCS6:
+ case ODM_RATEVHTSS3MCS5:
+ case ODM_RATEVHTSS3MCS4:
+ case ODM_RATEVHTSS3MCS3:
+ case ODM_RATEVHTSS2MCS9:
+ case ODM_RATEVHTSS2MCS8:
+ case ODM_RATEVHTSS2MCS7:
+ case ODM_RATEVHTSS2MCS6:
+ case ODM_RATEVHTSS2MCS5:
+ case ODM_RATEVHTSS2MCS4:
+ case ODM_RATEVHTSS2MCS3:
+ case ODM_RATEVHTSS1MCS9:
+ case ODM_RATEVHTSS1MCS8:
+ case ODM_RATEVHTSS1MCS7:
+ case ODM_RATEVHTSS1MCS6:
+ case ODM_RATEVHTSS1MCS5:
+ case ODM_RATEVHTSS1MCS4:
+ case ODM_RATEVHTSS1MCS3:
+ case ODM_RATEMCS15:
+ case ODM_RATEMCS14:
+ case ODM_RATEMCS13:
+ case ODM_RATEMCS12:
+ case ODM_RATEMCS11:
+ case ODM_RATEMCS7:
+ case ODM_RATEMCS6:
+ case ODM_RATEMCS5:
+ case ODM_RATEMCS4:
+ case ODM_RATEMCS3:
+ case ODM_RATE54M:
+ case ODM_RATE48M:
+ case ODM_RATE36M:
+ case ODM_RATE24M:
+ tx_ini_rate = ODM_RATE24M;
+ break;
+ case ODM_RATEVHTSS3MCS2:
+ case ODM_RATEVHTSS3MCS1:
+ case ODM_RATEVHTSS2MCS2:
+ case ODM_RATEVHTSS2MCS1:
+ case ODM_RATEVHTSS1MCS2:
+ case ODM_RATEVHTSS1MCS1:
+ case ODM_RATEMCS10:
+ case ODM_RATEMCS9:
+ case ODM_RATEMCS2:
+ case ODM_RATEMCS1:
+ case ODM_RATE18M:
+ case ODM_RATE12M:
+ tx_ini_rate = ODM_RATE12M;
+ break;
+ case ODM_RATEVHTSS3MCS0:
+ case ODM_RATEVHTSS2MCS0:
+ case ODM_RATEVHTSS1MCS0:
+ case ODM_RATEMCS8:
+ case ODM_RATEMCS0:
+ case ODM_RATE9M:
+ case ODM_RATE6M:
+ tx_ini_rate = ODM_RATE6M;
+ break;
+ case ODM_RATE11M:
+ case ODM_RATE5_5M:
+ case ODM_RATE2M:
+ case ODM_RATE1M:
+ tx_ini_rate = ODM_RATE1M;
+ break;
+ default:
+ tx_ini_rate = ODM_RATE6M;
+ break;
+ }
+
+ if (hal_data->current_band_type == BAND_ON_5G)
+ if (tx_ini_rate < ODM_RATE6M)
+ tx_ini_rate = ODM_RATE6M;
+
+ return tx_ini_rate;
+}
+
+void rtw_update_bmc_sta_tx_rate(_adapter *adapter)
+{
+ struct sta_info *psta = NULL;
+ u8 tx_rate;
+
+ psta = rtw_get_bcmc_stainfo(adapter);
+ if (psta == NULL) {
+ RTW_ERR(ADPT_FMT "could not get bmc_sta !!\n", ADPT_ARG(adapter));
+ return;
+ }
+
+ if (adapter->bmc_tx_rate != MGN_UNKNOWN) {
+ psta->init_rate = adapter->bmc_tx_rate;
+ goto _exit;
+ }
+
+ if (adapter->stapriv.asoc_sta_count <= 2)
+ goto _exit;
+
+ tx_rate = rtw_ap_find_mini_tx_rate(adapter);
+ #ifdef CONFIG_BMC_TX_LOW_RATE
+ tx_rate = rtw_ap_find_bmc_rate(adapter, tx_rate);
+ #endif
+
+ psta->init_rate = hw_rate_to_m_rate(tx_rate);
+
+_exit:
+ RTW_INFO(ADPT_FMT" BMC Tx rate - %s\n", ADPT_ARG(adapter), MGN_RATE_STR(psta->init_rate));
+}
+#endif
+
+void rtw_init_bmc_sta_tx_rate(_adapter *padapter, struct sta_info *psta)
+{
+ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
+ u8 rate_idx = 0;
+ u8 brate_table[] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M,
+ MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M};
+
+ if (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter))
+ return;
+
+ if (padapter->bmc_tx_rate != MGN_UNKNOWN)
+ psta->init_rate = padapter->bmc_tx_rate;
+ else {
+ #ifdef CONFIG_BMC_TX_LOW_RATE
+ if (IsEnableHWOFDM(pmlmeext->cur_wireless_mode) && (psta->cmn.ra_info.ramask && 0xFF0))
+ rate_idx = get_lowest_rate_idx_ex(psta->cmn.ra_info.ramask, 4); /*from basic rate*/
+ else
+ rate_idx = get_lowest_rate_idx(psta->cmn.ra_info.ramask); /*from basic rate*/
+ #else
+ rate_idx = get_highest_rate_idx(psta->cmn.ra_info.ramask); /*from basic rate*/
+ #endif
+ if (rate_idx < 12)
+ psta->init_rate = brate_table[rate_idx];
+ else
+ psta->init_rate = MGN_1M;
+ }
+ RTW_INFO(ADPT_FMT" BMC Init Tx rate - %s\n", ADPT_ARG(padapter), MGN_RATE_STR(psta->init_rate));
}
void update_bmc_sta(_adapter *padapter)
@@ -787,14 +884,18 @@ void update_bmc_sta(_adapter *padapter)
_irqL irqL;
unsigned char network_type;
int supportRateNum = 0;
- u64 tx_ra_bitmap = 0;
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
WLAN_BSSID_EX *pcur_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network;
struct sta_info *psta = rtw_get_bcmc_stainfo(padapter);
if (psta) {
- psta->aid = 0;/* default set to 0 */
- psta->qos_option = 0;
+ psta->cmn.aid = 0;/* default set to 0 */
+#ifdef CONFIG_RTW_MESH
+ if (MLME_IS_MESH(padapter))
+ psta->qos_option = 1;
+ else
+#endif
+ psta->qos_option = 0;
#ifdef CONFIG_80211N_HT
psta->htpriv.ht_option = _FALSE;
#endif /* CONFIG_80211N_HT */
@@ -805,7 +906,6 @@ void update_bmc_sta(_adapter *padapter)
/* psta->dot118021XPrivacy = _NO_PRIVACY_; */ /* !!! remove it, because it has been set before this. */
- /* prepare for add_RATid */
supportRateNum = rtw_get_rateset_len((u8 *)&pcur_network->SupportedRates);
network_type = rtw_check_network_type((u8 *)&pcur_network->SupportedRates, supportRateNum, pcur_network->Configuration.DSConfig);
if (IsSupportedTxCCK(network_type))
@@ -819,22 +919,52 @@ void update_bmc_sta(_adapter *padapter)
update_sta_basic_rate(psta, network_type);
psta->wireless_mode = network_type;
- rtw_hal_update_sta_rate_mask(padapter, psta);
- tx_ra_bitmap = psta->ra_mask;
-
- psta->raid = rtw_hal_networktype_to_raid(padapter, psta);
-
- rtw_sta_media_status_rpt(padapter, psta, 1);
+ rtw_hal_update_sta_ra_info(padapter, psta);
_enter_critical_bh(&psta->lock, &irqL);
psta->state = _FW_LINKED;
_exit_critical_bh(&psta->lock, &irqL);
+ rtw_sta_media_status_rpt(padapter, psta, 1);
+ rtw_init_bmc_sta_tx_rate(padapter, psta);
+
} else
RTW_INFO("add_RATid_bmc_sta error!\n");
}
+#if defined(CONFIG_80211N_HT) && defined(CONFIG_BEAMFORMING)
+void update_sta_info_apmode_ht_bf_cap(_adapter *padapter, struct sta_info *psta)
+{
+ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+ struct ht_priv *phtpriv_ap = &pmlmepriv->htpriv;
+ struct ht_priv *phtpriv_sta = &psta->htpriv;
+
+ u8 cur_beamform_cap = 0;
+
+ /*Config Tx beamforming setting*/
+ if (TEST_FLAG(phtpriv_ap->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE) &&
+ GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP((u8 *)(&phtpriv_sta->ht_cap))) {
+ SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE);
+ /*Shift to BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP*/
+ SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS((u8 *)(&phtpriv_sta->ht_cap)) << 6);
+ }
+
+ if (TEST_FLAG(phtpriv_ap->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE) &&
+ GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP((u8 *)(&phtpriv_sta->ht_cap))) {
+ SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE);
+ /*Shift to BEAMFORMING_HT_BEAMFORMER_STEER_NUM*/
+ SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS((u8 *)(&phtpriv_sta->ht_cap)) << 4);
+ }
+ if (cur_beamform_cap)
+ RTW_INFO("Client STA(%d) HT Beamforming Cap = 0x%02X\n", psta->cmn.aid, cur_beamform_cap);
+
+ phtpriv_sta->beamform_cap = cur_beamform_cap;
+ psta->cmn.bf_info.ht_beamform_cap = cur_beamform_cap;
+
+}
+#endif /*CONFIG_80211N_HT && CONFIG_BEAMFORMING*/
+
/* notes:
* AID: 1~MAX for sta and 0 for bc/mc in ap/adhoc mode */
void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta)
@@ -847,7 +977,7 @@ void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta)
struct ht_priv *phtpriv_ap = &pmlmepriv->htpriv;
struct ht_priv *phtpriv_sta = &psta->htpriv;
#endif /* CONFIG_80211N_HT */
- u8 cur_ldpc_cap = 0, cur_stbc_cap = 0, cur_beamform_cap = 0;
+ u8 cur_ldpc_cap = 0, cur_stbc_cap = 0;
/* set intf_tag to if1 */
/* psta->intf_tag = 0; */
@@ -855,10 +985,7 @@ void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta)
/*alloc macid when call rtw_alloc_stainfo(),release macid when call rtw_free_stainfo()*/
- /* ap mode */
- rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _TRUE);
-
- if (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)
+ if (!MLME_IS_MESH(padapter) && psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)
psta->ieee8021x_blocked = _TRUE;
else
psta->ieee8021x_blocked = _FALSE;
@@ -878,15 +1005,19 @@ void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta)
/* bwmode */
if ((phtpriv_sta->ht_cap.cap_info & phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SUP_WIDTH))
- psta->bw_mode = CHANNEL_WIDTH_40;
+ psta->cmn.bw_mode = CHANNEL_WIDTH_40;
else
- psta->bw_mode = CHANNEL_WIDTH_20;
+ psta->cmn.bw_mode = CHANNEL_WIDTH_20;
+
+ if (phtpriv_sta->op_present
+ && !GET_HT_OP_ELE_STA_CHL_WIDTH(phtpriv_sta->ht_op))
+ psta->cmn.bw_mode = CHANNEL_WIDTH_20;
if (psta->ht_40mhz_intolerant)
- psta->bw_mode = CHANNEL_WIDTH_20;
+ psta->cmn.bw_mode = CHANNEL_WIDTH_20;
- if (pmlmeext->cur_bwmode < psta->bw_mode)
- psta->bw_mode = pmlmeext->cur_bwmode;
+ if (pmlmeext->cur_bwmode < psta->cmn.bw_mode)
+ psta->cmn.bw_mode = pmlmeext->cur_bwmode;
phtpriv_sta->ch_offset = pmlmeext->cur_ch_offset;
@@ -897,7 +1028,7 @@ void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta)
/* check if sta support s Short GI 40M */
if ((phtpriv_sta->ht_cap.cap_info & phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SGI_40)) {
- if (psta->bw_mode == CHANNEL_WIDTH_40) /* according to psta->bw_mode */
+ if (psta->cmn.bw_mode == CHANNEL_WIDTH_40) /* according to psta->bw_mode */
phtpriv_sta->sgi_40m = _TRUE;
else
phtpriv_sta->sgi_40m = _FALSE;
@@ -909,52 +1040,36 @@ void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta)
if (TEST_FLAG(phtpriv_ap->ldpc_cap, LDPC_HT_ENABLE_TX) &&
GET_HT_CAP_ELE_LDPC_CAP((u8 *)(&phtpriv_sta->ht_cap))) {
SET_FLAG(cur_ldpc_cap, (LDPC_HT_ENABLE_TX | LDPC_HT_CAP_TX));
- RTW_INFO("Enable HT Tx LDPC for STA(%d)\n", psta->aid);
+ RTW_INFO("Enable HT Tx LDPC for STA(%d)\n", psta->cmn.aid);
}
/* B7 B8 B9 Config STBC setting */
if (TEST_FLAG(phtpriv_ap->stbc_cap, STBC_HT_ENABLE_TX) &&
GET_HT_CAP_ELE_RX_STBC((u8 *)(&phtpriv_sta->ht_cap))) {
SET_FLAG(cur_stbc_cap, (STBC_HT_ENABLE_TX | STBC_HT_CAP_TX));
- RTW_INFO("Enable HT Tx STBC for STA(%d)\n", psta->aid);
- }
-
-#ifdef CONFIG_BEAMFORMING
- /*Config Tx beamforming setting*/
- if (TEST_FLAG(phtpriv_ap->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE) &&
- GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP((u8 *)(&phtpriv_sta->ht_cap))) {
- SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE);
- /*Shift to BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP*/
- SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS((u8 *)(&phtpriv_sta->ht_cap)) << 6);
+ RTW_INFO("Enable HT Tx STBC for STA(%d)\n", psta->cmn.aid);
}
- if (TEST_FLAG(phtpriv_ap->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE) &&
- GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP((u8 *)(&phtpriv_sta->ht_cap))) {
- SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE);
- /*Shift to BEAMFORMING_HT_BEAMFORMER_STEER_NUM*/
- SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS((u8 *)(&phtpriv_sta->ht_cap)) << 4);
- }
- if (cur_beamform_cap)
- RTW_INFO("Client STA(%d) HT Beamforming Cap = 0x%02X\n", psta->aid, cur_beamform_cap);
-#endif /*CONFIG_BEAMFORMING*/
+ #ifdef CONFIG_BEAMFORMING
+ update_sta_info_apmode_ht_bf_cap(padapter, psta);
+ #endif
} else {
phtpriv_sta->ampdu_enable = _FALSE;
phtpriv_sta->sgi_20m = _FALSE;
phtpriv_sta->sgi_40m = _FALSE;
- psta->bw_mode = CHANNEL_WIDTH_20;
+ psta->cmn.bw_mode = CHANNEL_WIDTH_20;
phtpriv_sta->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
}
phtpriv_sta->ldpc_cap = cur_ldpc_cap;
phtpriv_sta->stbc_cap = cur_stbc_cap;
- phtpriv_sta->beamform_cap = cur_beamform_cap;
/* Rx AMPDU */
- send_delba(padapter, 0, psta->hwaddr);/* recipient */
+ send_delba(padapter, 0, psta->cmn.mac_addr);/* recipient */
/* TX AMPDU */
- send_delba(padapter, 1, psta->hwaddr);/* */ /* originator */
+ send_delba(padapter, 1, psta->cmn.mac_addr);/* */ /* originator */
phtpriv_sta->agg_enable_bitmap = 0x0;/* reset */
phtpriv_sta->candidate_tid_bitmap = 0x0;/* reset */
#endif /* CONFIG_80211N_HT */
@@ -962,7 +1077,7 @@ void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta)
#ifdef CONFIG_80211AC_VHT
update_sta_vht_info_apmode(padapter, psta);
#endif
-
+ psta->cmn.ra_info.is_support_sgi = query_ra_short_GI(psta, rtw_get_tx_bw_mode(padapter, psta));
update_ldpc_stbc_cap(psta);
/* todo: init other variables */
@@ -973,6 +1088,8 @@ void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta)
/* add ratid */
/* add_RATid(padapter, psta); */ /* move to ap_sta_info_defer_update() */
+ /* ap mode */
+ rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _TRUE);
_enter_critical_bh(&psta->lock, &irqL);
psta->state |= _FW_LINKED;
@@ -1017,7 +1134,7 @@ static void update_ap_info(_adapter *padapter, struct sta_info *psta)
phtpriv_ap->sgi_40m = _FALSE;
}
- psta->bw_mode = pmlmeext->cur_bwmode;
+ psta->cmn.bw_mode = pmlmeext->cur_bwmode;
phtpriv_ap->ch_offset = pmlmeext->cur_ch_offset;
phtpriv_ap->agg_enable_bitmap = 0x0;/* reset */
@@ -1048,7 +1165,7 @@ static void rtw_set_hw_wmm_param(_adapter *padapter)
acm_mask = 0;
- if (IsSupported5G(pmlmeext->cur_wireless_mode) ||
+ if (is_supported_5g(pmlmeext->cur_wireless_mode) ||
(pmlmeext->cur_wireless_mode & WIRELESS_11_24N))
aSifsTime = 16;
else
@@ -1250,13 +1367,13 @@ static void rtw_ap_check_scan(_adapter *padapter)
}
_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
-#ifdef CONFIG_AUTO_CHNL_SEL_NHM
+#ifdef CONFIG_RTW_ACS
if (padapter->registrypriv.acs_auto_scan) {
do_scan = _TRUE;
reason |= RTW_AUTO_SCAN_REASON_ACS;
- rtw_acs_start(padapter, _TRUE);
+ rtw_acs_start(padapter);
}
-#endif
+#endif/*CONFIG_RTW_ACS*/
if (_TRUE == do_scan) {
RTW_INFO("%s : drv scans by itself and wait_completed\n", __func__);
@@ -1264,10 +1381,11 @@ static void rtw_ap_check_scan(_adapter *padapter)
rtw_scan_wait_completed(padapter);
}
-#ifdef CONFIG_AUTO_CHNL_SEL_NHM
+#ifdef CONFIG_RTW_ACS
if (padapter->registrypriv.acs_auto_scan)
- rtw_acs_start(padapter, _FALSE);
+ rtw_acs_stop(padapter);
#endif
+
_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
phead = get_list_head(queue);
@@ -1280,7 +1398,7 @@ static void rtw_ap_check_scan(_adapter *padapter)
pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
- if (rtw_ch_set_search_ch(padapter->mlmeextpriv.channel_set, pnetwork->network.Configuration.DSConfig) >= 0
+ if (rtw_chset_search_ch(adapter_to_chset(padapter), pnetwork->network.Configuration.DSConfig) >= 0
&& rtw_mlme_band_check(padapter, pnetwork->network.Configuration.DSConfig) == _TRUE
&& _TRUE == rtw_validate_ssid(&(pnetwork->network.Ssid))) {
delta_time = (u32) rtw_get_passing_time_ms(pnetwork->last_scanned);
@@ -1299,11 +1417,14 @@ static void rtw_ap_check_scan(_adapter *padapter)
if (pbuf == NULL) {
/* HT CAP INFO IE don't exist, it is b/g mode bss.*/
- if (pmlmepriv->olbc == _FALSE)
- pmlmepriv->olbc = _TRUE;
+ if (_FALSE == ATOMIC_READ(&pmlmepriv->olbc))
+ ATOMIC_SET(&pmlmepriv->olbc, _TRUE);
- if (pmlmepriv->olbc_ht == _FALSE)
- pmlmepriv->olbc_ht = _TRUE;
+ if (_FALSE == ATOMIC_READ(&pmlmepriv->olbc_ht))
+ ATOMIC_SET(&pmlmepriv->olbc_ht, _TRUE);
+
+ if (padapter->registrypriv.wifi_spec)
+ RTW_INFO("%s: %s is a/b/g ap\n", __func__, pnetwork->network.Ssid.Ssid);
}
}
}
@@ -1350,7 +1471,7 @@ void rtw_start_bss_hdl_after_chbw_decided(_adapter *adapter)
void start_bss_network(_adapter *padapter, struct createbss_parm *parm)
{
#define DUMP_ADAPTERS_STATUS 0
-
+ u8 self_action = MLME_ACTION_UNKNOWN;
u8 val8;
u16 bcn_interval;
u32 acparm;
@@ -1362,19 +1483,30 @@ void start_bss_network(_adapter *padapter, struct createbss_parm *parm)
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
WLAN_BSSID_EX *pnetwork_mlmeext = &(pmlmeinfo->network);
struct dvobj_priv *pdvobj = padapter->dvobj;
- s16 req_ch = -1, req_bw = -1, req_offset = -1;
+ s16 req_ch = REQ_CH_NONE, req_bw = REQ_BW_NONE, req_offset = REQ_OFFSET_NONE;
bool ch_setting_changed = _FALSE;
u8 ch_to_set = 0, bw_to_set, offset_to_set;
u8 doiqk = _FALSE;
/* use for check ch bw offset can be allowed or not */
u8 chbw_allow = _TRUE;
+ if (MLME_IS_AP(padapter))
+ self_action = MLME_AP_STARTED;
+ else if (MLME_IS_MESH(padapter))
+ self_action = MLME_MESH_STARTED;
+ else
+ rtw_warn_on(1);
+
if (parm->req_ch != 0) {
/* bypass other setting, go checking ch, bw, offset */
req_ch = parm->req_ch;
req_bw = parm->req_bw;
req_offset = parm->req_offset;
goto chbw_decision;
+ } else {
+ /* inform this request comes from upper layer */
+ req_ch = 0;
+ _rtw_memcpy(pnetwork_mlmeext, pnetwork, pnetwork->Length);
}
bcn_interval = (u16)pnetwork->Configuration.BeaconPeriod;
@@ -1410,7 +1542,9 @@ void start_bss_network(_adapter *padapter, struct createbss_parm *parm)
if (pmlmepriv->cur_network.join_res != _TRUE) { /* setting only at first time */
/* WEP Key will be set before this function, do not clear CAM. */
- if ((psecuritypriv->dot11PrivacyAlgrthm != _WEP40_) && (psecuritypriv->dot11PrivacyAlgrthm != _WEP104_))
+ if ((psecuritypriv->dot11PrivacyAlgrthm != _WEP40_) && (psecuritypriv->dot11PrivacyAlgrthm != _WEP104_)
+ && !MLME_IS_MESH(padapter) /* mesh group key is set before this function */
+ )
flush_all_cam_entry(padapter); /* clear CAM */
}
@@ -1446,22 +1580,40 @@ void start_bss_network(_adapter *padapter, struct createbss_parm *parm)
ch_setting_changed = rtw_ap_chbw_decision(padapter, req_ch, req_bw, req_offset
, &ch_to_set, &bw_to_set, &offset_to_set, &chbw_allow);
- /* let pnetwork_mlmeext == pnetwork_mlme. */
- _rtw_memcpy(pnetwork_mlmeext, pnetwork, pnetwork->Length);
+ /* let pnetwork_mlme == pnetwork_mlmeext */
+ _rtw_memcpy(pnetwork, pnetwork_mlmeext, pnetwork_mlmeext->Length);
rtw_start_bss_hdl_after_chbw_decided(padapter);
#if defined(CONFIG_DFS_MASTER)
- rtw_dfs_master_status_apply(padapter, MLME_AP_STARTED);
+ rtw_dfs_master_status_apply(padapter, self_action);
#endif
+ rtw_hal_rcr_set_chk_bssid(padapter, self_action);
#ifdef CONFIG_MCC_MODE
+ if (MCC_EN(padapter)) {
+ /*
+ * due to check under rtw_ap_chbw_decision
+ * if under MCC mode, means req channel setting is the same as current channel setting
+ * if not under MCC mode, mean req channel setting is not the same as current channel setting
+ */
+ if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
+ RTW_INFO(FUNC_ADPT_FMT": req channel setting is the same as current channel setting, go to update BCN\n"
+ , FUNC_ADPT_ARG(padapter));
+
+ goto update_beacon;
+
+ }
+ }
+
/* issue null data to AP for all interface connecting to AP before switch channel setting for softap */
rtw_hal_mcc_issue_null_data(padapter, chbw_allow, 1);
#endif /* CONFIG_MCC_MODE */
- doiqk = _TRUE;
- rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk);
+ if (!IS_CH_WAITING(adapter_to_rfctl(padapter))) {
+ doiqk = _TRUE;
+ rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk);
+ }
if (ch_to_set != 0) {
set_channel_bwmode(padapter, ch_to_set, offset_to_set, bw_to_set);
@@ -1476,18 +1628,28 @@ void start_bss_network(_adapter *padapter, struct createbss_parm *parm)
rtw_hal_set_mcc_setting_start_bss_network(padapter, chbw_allow);
#endif
+ if (ch_setting_changed == _TRUE
+ && (MLME_IS_GO(padapter) || MLME_IS_MESH(padapter)) /* pure AP is not needed*/
+ ) {
+ #if defined(CONFIG_IOCTL_CFG80211) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
+ rtw_cfg80211_ch_switch_notify(padapter
+ , pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset
+ , pmlmepriv->htpriv.ht_option);
+ #endif
+ }
+
if (DUMP_ADAPTERS_STATUS) {
RTW_INFO(FUNC_ADPT_FMT" done\n", FUNC_ADPT_ARG(padapter));
dump_adapters_status(RTW_DBGDUMP , adapter_to_dvobj(padapter));
}
+update_beacon:
/* update beacon content only if bstart_bss is _TRUE */
if (_TRUE == pmlmeext->bstart_bss) {
_irqL irqL;
- if ((pmlmepriv->olbc == _TRUE) || (pmlmepriv->olbc_ht == _TRUE)) {
-
+ if ((ATOMIC_READ(&pmlmepriv->olbc) == _TRUE) || (ATOMIC_READ(&pmlmepriv->olbc_ht) == _TRUE)) {
/* AP is not starting a 40 MHz BSS in presence of an 802.11g BSS. */
pmlmepriv->ht_op_mode &= (~HT_INFO_OPERATION_MODE_OP_MODE_MASK);
@@ -1515,9 +1677,7 @@ void start_bss_network(_adapter *padapter, struct createbss_parm *parm)
rtw_scan_wait_completed(padapter);
/* send beacon */
- if ((0 == rtw_mi_check_fwstate(padapter, _FW_UNDER_SURVEY))
- && (0 == rtw_mi_check_fwstate(padapter, WIFI_OP_CH_SWITCHING))
- ) {
+ if (!rtw_mi_check_fwstate(padapter, _FW_UNDER_SURVEY)) {
/*update_beacon(padapter, _TIM_IE_, NULL, _TRUE);*/
@@ -1553,11 +1713,13 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len)
u16 cap, ht_cap = _FALSE;
uint ie_len = 0;
int group_cipher, pairwise_cipher;
+ u8 mfp_opt = MFP_NO;
u8 channel, network_type, supportRate[NDIS_802_11_LENGTH_RATES_EX];
int supportRateNum = 0;
u8 OUI1[] = {0x00, 0x50, 0xf2, 0x01};
u8 wps_oui[4] = {0x0, 0x50, 0xf2, 0x04};
u8 WMM_PARA_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x01, 0x01};
+ HT_CAP_AMPDU_DENSITY best_ampdu_density;
struct registry_priv *pregistrypriv = &padapter->registrypriv;
struct security_priv *psecuritypriv = &padapter->securitypriv;
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
@@ -1567,6 +1729,7 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len)
u8 vht_cap = _FALSE;
struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
u8 rf_num = 0;
/* SSID */
@@ -1582,7 +1745,7 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len)
RTW_INFO("%s, len=%d\n", __FUNCTION__, len);
- if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
+ if (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter))
return _FAIL;
@@ -1596,8 +1759,12 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len)
_rtw_memcpy(ie, pbuf, pbss_network->IELength);
- if (pbss_network->InfrastructureMode != Ndis802_11APMode)
+ if (pbss_network->InfrastructureMode != Ndis802_11APMode
+ && pbss_network->InfrastructureMode != Ndis802_11_mesh
+ ) {
+ rtw_warn_on(1);
return _FAIL;
+ }
rtw_ap_check_scan(padapter);
@@ -1629,6 +1796,18 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len)
#endif
}
+#ifdef CONFIG_RTW_MESH
+ /* Mesh ID */
+ if (MLME_IS_MESH(padapter)) {
+ p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, WLAN_EID_MESH_ID, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));
+ if (p && ie_len > 0) {
+ _rtw_memset(&pbss_network->mesh_id, 0, sizeof(NDIS_802_11_SSID));
+ _rtw_memcpy(pbss_network->mesh_id.Ssid, (p + 2), ie_len);
+ pbss_network->mesh_id.SsidLength = ie_len;
+ }
+ }
+#endif
+
/* chnnel */
channel = 0;
pbss_network->Configuration.Length = 0;
@@ -1680,7 +1859,7 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len)
psecuritypriv->wpa2_pairwise_cipher = _NO_PRIVACY_;
p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _RSN_IE_2_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));
if (p && ie_len > 0) {
- if (rtw_parse_wpa2_ie(p, ie_len + 2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) {
+ if (rtw_parse_wpa2_ie(p, ie_len + 2, &group_cipher, &pairwise_cipher, NULL, &mfp_opt) == _SUCCESS) {
psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
psecuritypriv->dot8021xalg = 1;/* psk, todo:802.1x */
@@ -1796,9 +1975,26 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len)
}
+#ifdef CONFIG_RTW_MESH
+ if (MLME_IS_MESH(padapter)) {
+ /* MFP is mandatory for secure mesh */
+ if (padapter->mesh_info.mesh_auth_id)
+ mfp_opt = MFP_REQUIRED;
+ } else
+#endif
+ if (mfp_opt == MFP_INVALID) {
+ RTW_INFO(FUNC_ADPT_FMT" invalid MFP setting\n", FUNC_ADPT_ARG(padapter));
+ return _FAIL;
+ }
+ psecuritypriv->mfp_opt = mfp_opt;
+
/* wmm */
ie_len = 0;
pmlmepriv->qospriv.qos_option = 0;
+#ifdef CONFIG_RTW_MESH
+ if (MLME_IS_MESH(padapter))
+ pmlmepriv->qospriv.qos_option = 1;
+#endif
if (pregistrypriv->wmm_enable) {
for (p = ie + _BEACON_IE_OFFSET_; ; p += (ie_len + 2)) {
p = rtw_get_ie(p, _VENDOR_SPECIFIC_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_ - (ie_len + 2)));
@@ -1860,9 +2056,10 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len)
pht_cap->ampdu_params_info &= ~(IEEE80211_HT_CAP_AMPDU_FACTOR | IEEE80211_HT_CAP_AMPDU_DENSITY);
if ((psecuritypriv->wpa_pairwise_cipher & WPA_CIPHER_CCMP) ||
- (psecuritypriv->wpa2_pairwise_cipher & WPA_CIPHER_CCMP))
- pht_cap->ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY & (0x07 << 2));
- else
+ (psecuritypriv->wpa2_pairwise_cipher & WPA_CIPHER_CCMP)) {
+ rtw_hal_get_def_var(padapter, HW_VAR_BEST_AMPDU_DENSITY, &best_ampdu_density);
+ pht_cap->ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY & (best_ampdu_density << 2));
+ } else
pht_cap->ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY & 0x00);
rtw_hal_get_def_var(padapter, HW_VAR_MAX_RX_AMPDU_FACTOR, &max_rx_ampdu_factor);
@@ -1872,24 +2069,29 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len)
/* Update Supported MCS Set field */
{
+ struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
+ u8 rx_nss = 0;
int i;
rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
+ rx_nss = rtw_min(rf_type_to_rf_rx_cnt(rf_type), hal_spec->rx_nss_num);
/* RX MCS Bitmask */
- switch (rf_type) {
- case RF_1T1R:
- case RF_1T2R: /* ? */
+ switch (rx_nss) {
+ case 1:
set_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_1R);
break;
- case RF_2T2R:
+ case 2:
set_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_2R);
break;
- case RF_3T3R:
+ case 3:
set_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_3R);
break;
+ case 4:
+ set_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_4R);
+ break;
default:
- RTW_INFO("[warning] rf_type %d is not expected\n", rf_type);
+ RTW_WARN("rf_type:%d or rx_nss:%u is not expected\n", rf_type, hal_spec->rx_nss_num);
}
for (i = 0; i < 10; i++)
*(HT_CAP_ELE_RX_MCS_MAP(pht_cap) + i) &= padapter->mlmeextpriv.default_supported_mcs_set[i];
@@ -1933,9 +2135,17 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len)
/* parsing HT_INFO_IE */
p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_ADD_INFO_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));
- if (p && ie_len > 0)
+ if (p && ie_len > 0) {
pHT_info_ie = p;
+ if (channel == 0)
+ pbss_network->Configuration.DSConfig = GET_HT_OP_ELE_PRI_CHL(pHT_info_ie + 2);
+ else if (channel != GET_HT_OP_ELE_PRI_CHL(pHT_info_ie + 2)) {
+ RTW_INFO(FUNC_ADPT_FMT" ch inconsistent, DSSS:%u, HT primary:%u\n"
+ , FUNC_ADPT_ARG(padapter), channel, GET_HT_OP_ELE_PRI_CHL(pHT_info_ie + 2));
+ }
+ }
#endif /* CONFIG_80211N_HT */
+
switch (network_type) {
case WIRELESS_11B:
pbss_network->NetworkTypeInUse = Ndis802_11DS;
@@ -1970,8 +2180,7 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len)
pmlmepriv->htpriv.ht_option = _TRUE;
pmlmepriv->qospriv.qos_option = 1;
- if (pregistrypriv->ampdu_enable == 1)
- pmlmepriv->htpriv.ampdu_enable = _TRUE;
+ pmlmepriv->htpriv.ampdu_enable = pregistrypriv->ampdu_enable ? _TRUE : _FALSE;
HT_caps_handler(padapter, (PNDIS_802_11_VARIABLE_IEs)pHT_caps_ie);
@@ -1985,51 +2194,47 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len)
p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, EID_VHTCapability, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_));
if (p && ie_len > 0)
vht_cap = _TRUE;
- /* Parsing VHT OPERATION IE */
+ /* Parsing VHT OPERATION IE */
+ pmlmepriv->ori_vht_en = 0;
pmlmepriv->vhtpriv.vht_option = _FALSE;
/* if channel in 5G band, then add vht ie . */
if ((pbss_network->Configuration.DSConfig > 14)
- && (pmlmepriv->htpriv.ht_option == _TRUE)
- && REGSTY_IS_11AC_ENABLE(pregistrypriv)
- && hal_chk_proto_cap(padapter, PROTO_CAP_11AC)
- && (!pmlmepriv->country_ent || COUNTRY_CHPLAN_EN_11AC(pmlmepriv->country_ent))
- ) {
- if (vht_cap == _TRUE)
+ && (pmlmepriv->htpriv.ht_option == _TRUE)
+ && REGSTY_IS_11AC_ENABLE(pregistrypriv)
+ && hal_chk_proto_cap(padapter, PROTO_CAP_11AC)
+ && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent))
+ ) {
+ if (vht_cap == _TRUE
+ && MLME_IS_MESH(padapter) /* allow only mesh temporarily before VHT IE checking is ready */
+ ) {
+ rtw_check_for_vht20(padapter, ie + _BEACON_IE_OFFSET_, pbss_network->IELength - _BEACON_IE_OFFSET_);
+ pmlmepriv->ori_vht_en = 1;
pmlmepriv->vhtpriv.vht_option = _TRUE;
- else if (REGSTY_IS_11AC_AUTO(pregistrypriv)) {
- u8 cap_len, operation_len;
-
- rtw_vht_use_default_setting(padapter);
-
- {
- /* VHT Operation mode notifiy bit in Extended IE (127) */
- uint len = 0;
-
- SET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(pmlmepriv->ext_capab_ie_data, 1);
- pmlmepriv->ext_capab_ie_len = 10;
- rtw_set_ie(pbss_network->IEs + pbss_network->IELength, EID_EXTCapability, 8, pmlmepriv->ext_capab_ie_data, &len);
- pbss_network->IELength += pmlmepriv->ext_capab_ie_len;
- }
+ } else if (REGSTY_IS_11AC_AUTO(pregistrypriv)) {
+ rtw_vht_ies_detach(padapter, pbss_network);
+ rtw_vht_ies_attach(padapter, pbss_network);
+ }
+ }
- /* VHT Capabilities element */
- cap_len = rtw_build_vht_cap_ie(padapter, pbss_network->IEs + pbss_network->IELength);
- pbss_network->IELength += cap_len;
+ if (pmlmepriv->vhtpriv.vht_option == _FALSE)
+ rtw_vht_ies_detach(padapter, pbss_network);
+#endif /* CONFIG_80211AC_VHT */
- /* VHT Operation element */
- operation_len = rtw_build_vht_operation_ie(padapter, pbss_network->IEs + pbss_network->IELength, pbss_network->Configuration.DSConfig);
- pbss_network->IELength += operation_len;
+ if(pbss_network->Configuration.DSConfig <= 14 && padapter->registrypriv.wifi_spec == 1) {
+ uint len = 0;
- pmlmepriv->vhtpriv.vht_option = _TRUE;
- }
+ SET_EXT_CAPABILITY_ELE_BSS_COEXIST(pmlmepriv->ext_capab_ie_data, 1);
+ pmlmepriv->ext_capab_ie_len = 10;
+ rtw_set_ie(pbss_network->IEs + pbss_network->IELength, EID_EXTCapability, 8, pmlmepriv->ext_capab_ie_data, &len);
+ pbss_network->IELength += pmlmepriv->ext_capab_ie_len;
}
-#endif /* CONFIG_80211AC_VHT */
pbss_network->Length = get_WLAN_BSSID_EX_sz((WLAN_BSSID_EX *)pbss_network);
rtw_ies_get_chbw(pbss_network->IEs + _BEACON_IE_OFFSET_, pbss_network->IELength - _BEACON_IE_OFFSET_
- , &pmlmepriv->ori_ch, &pmlmepriv->ori_bw, &pmlmepriv->ori_offset);
+ , &pmlmepriv->ori_ch, &pmlmepriv->ori_bw, &pmlmepriv->ori_offset, 1, 1);
rtw_warn_on(pmlmepriv->ori_ch == 0);
{
@@ -2065,18 +2270,28 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len)
}
#if CONFIG_RTW_MACADDR_ACL
-void rtw_macaddr_acl_init(_adapter *adapter)
+void rtw_macaddr_acl_init(_adapter *adapter, u8 period)
{
struct sta_priv *stapriv = &adapter->stapriv;
- struct wlan_acl_pool *acl = &stapriv->acl_list;
- _queue *acl_node_q = &acl->acl_node_q;
+ struct wlan_acl_pool *acl;
+ _queue *acl_node_q;
int i;
_irqL irqL;
- _enter_critical_bh(&(acl_node_q->lock), &irqL);
- _rtw_init_listhead(&(acl_node_q->queue));
- acl->num = 0;
- acl->mode = RTW_ACL_MODE_DISABLED;
+ if (period >= RTW_ACL_PERIOD_NUM) {
+ rtw_warn_on(1);
+ return;
+ }
+
+ acl = &stapriv->acl_list[period];
+ acl_node_q = &acl->acl_node_q;
+
+ _rtw_spinlock_init(&(acl_node_q->lock));
+
+ _enter_critical_bh(&(acl_node_q->lock), &irqL);
+ _rtw_init_listhead(&(acl_node_q->queue));
+ acl->num = 0;
+ acl->mode = RTW_ACL_MODE_DISABLED;
for (i = 0; i < NUM_ACL; i++) {
_rtw_init_listhead(&acl->aclnode[i].list);
acl->aclnode[i].valid = _FALSE;
@@ -2084,15 +2299,23 @@ void rtw_macaddr_acl_init(_adapter *adapter)
_exit_critical_bh(&(acl_node_q->lock), &irqL);
}
-void rtw_macaddr_acl_deinit(_adapter *adapter)
+static void _rtw_macaddr_acl_deinit(_adapter *adapter, u8 period, bool clear_only)
{
struct sta_priv *stapriv = &adapter->stapriv;
- struct wlan_acl_pool *acl = &stapriv->acl_list;
- _queue *acl_node_q = &acl->acl_node_q;
+ struct wlan_acl_pool *acl;
+ _queue *acl_node_q;
_irqL irqL;
_list *head, *list;
struct rtw_wlan_acl_node *acl_node;
+ if (period >= RTW_ACL_PERIOD_NUM) {
+ rtw_warn_on(1);
+ return;
+ }
+
+ acl = &stapriv->acl_list[period];
+ acl_node_q = &acl->acl_node_q;
+
_enter_critical_bh(&(acl_node_q->lock), &irqL);
head = get_list_head(acl_node_q);
list = get_next(head);
@@ -2108,24 +2331,42 @@ void rtw_macaddr_acl_deinit(_adapter *adapter)
}
_exit_critical_bh(&(acl_node_q->lock), &irqL);
+ if (!clear_only)
+ _rtw_spinlock_free(&(acl_node_q->lock));
+
rtw_warn_on(acl->num);
acl->mode = RTW_ACL_MODE_DISABLED;
}
-void rtw_set_macaddr_acl(_adapter *adapter, int mode)
+void rtw_macaddr_acl_deinit(_adapter *adapter, u8 period)
+{
+ _rtw_macaddr_acl_deinit(adapter, period, 0);
+}
+
+void rtw_macaddr_acl_clear(_adapter *adapter, u8 period)
+{
+ _rtw_macaddr_acl_deinit(adapter, period, 1);
+}
+
+void rtw_set_macaddr_acl(_adapter *adapter, u8 period, int mode)
{
struct sta_priv *stapriv = &adapter->stapriv;
- struct wlan_acl_pool *acl = &stapriv->acl_list;
+ struct wlan_acl_pool *acl;
+
+ if (period >= RTW_ACL_PERIOD_NUM) {
+ rtw_warn_on(1);
+ return;
+ }
- RTW_INFO(FUNC_ADPT_FMT" mode=%d\n", FUNC_ADPT_ARG(adapter), mode);
+ acl = &stapriv->acl_list[period];
- acl->mode = mode;
+ RTW_INFO(FUNC_ADPT_FMT" p=%u, mode=%d\n"
+ , FUNC_ADPT_ARG(adapter), period, mode);
- if (mode == RTW_ACL_MODE_DISABLED)
- rtw_macaddr_acl_deinit(adapter);
+ acl->mode = mode;
}
-int rtw_acl_add_sta(_adapter *adapter, const u8 *addr)
+int rtw_acl_add_sta(_adapter *adapter, u8 period, const u8 *addr)
{
_irqL irqL;
_list *list, *head;
@@ -2133,8 +2374,17 @@ int rtw_acl_add_sta(_adapter *adapter, const u8 *addr)
int i = -1, ret = 0;
struct rtw_wlan_acl_node *acl_node;
struct sta_priv *stapriv = &adapter->stapriv;
- struct wlan_acl_pool *acl = &stapriv->acl_list;
- _queue *acl_node_q = &acl->acl_node_q;
+ struct wlan_acl_pool *acl;
+ _queue *acl_node_q;
+
+ if (period >= RTW_ACL_PERIOD_NUM) {
+ rtw_warn_on(1);
+ ret = -1;
+ goto exit;
+ }
+
+ acl = &stapriv->acl_list[period];
+ acl_node_q = &acl->acl_node_q;
_enter_critical_bh(&(acl_node_q->lock), &irqL);
@@ -2181,26 +2431,34 @@ int rtw_acl_add_sta(_adapter *adapter, const u8 *addr)
if (!existed && (i < 0 || i >= NUM_ACL))
ret = -1;
- RTW_INFO(FUNC_ADPT_FMT" "MAC_FMT" %s (acl_num=%d)\n"
- , FUNC_ADPT_ARG(adapter), MAC_ARG(addr)
+ RTW_INFO(FUNC_ADPT_FMT" p=%u "MAC_FMT" %s (acl_num=%d)\n"
+ , FUNC_ADPT_ARG(adapter), period, MAC_ARG(addr)
, (existed ? "existed" : ((i < 0 || i >= NUM_ACL) ? "no room" : "added"))
, acl->num);
-
+exit:
return ret;
}
-int rtw_acl_remove_sta(_adapter *adapter, const u8 *addr)
+int rtw_acl_remove_sta(_adapter *adapter, u8 period, const u8 *addr)
{
_irqL irqL;
_list *list, *head;
int ret = 0;
struct rtw_wlan_acl_node *acl_node;
struct sta_priv *stapriv = &adapter->stapriv;
- struct wlan_acl_pool *acl = &stapriv->acl_list;
- _queue *acl_node_q = &acl->acl_node_q;
+ struct wlan_acl_pool *acl;
+ _queue *acl_node_q;
u8 is_baddr = is_broadcast_mac_addr(addr);
u8 match = 0;
+ if (period >= RTW_ACL_PERIOD_NUM) {
+ rtw_warn_on(1);
+ goto exit;
+ }
+
+ acl = &stapriv->acl_list[period];
+ acl_node_q = &acl->acl_node_q;
+
_enter_critical_bh(&(acl_node_q->lock), &irqL);
head = get_list_head(acl_node_q);
@@ -2222,51 +2480,59 @@ int rtw_acl_remove_sta(_adapter *adapter, const u8 *addr)
_exit_critical_bh(&(acl_node_q->lock), &irqL);
- RTW_INFO(FUNC_ADPT_FMT" "MAC_FMT" %s (acl_num=%d)\n"
- , FUNC_ADPT_ARG(adapter), MAC_ARG(addr)
+ RTW_INFO(FUNC_ADPT_FMT" p=%u "MAC_FMT" %s (acl_num=%d)\n"
+ , FUNC_ADPT_ARG(adapter), period, MAC_ARG(addr)
, is_baddr ? "clear all" : (match ? "match" : "no found")
, acl->num);
+exit:
return ret;
}
#endif /* CONFIG_RTW_MACADDR_ACL */
-u8 rtw_ap_set_pairwise_key(_adapter *padapter, struct sta_info *psta)
+u8 rtw_ap_set_sta_key(_adapter *adapter, const u8 *addr, u8 alg, const u8 *key, u8 keyid, u8 gk)
{
- struct cmd_obj *ph2c;
- struct set_stakey_parm *psetstakey_para;
- struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
+ struct cmd_priv *cmdpriv = &adapter->cmdpriv;
+ struct cmd_obj *cmd;
+ struct set_stakey_parm *param;
u8 res = _SUCCESS;
- ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
- if (ph2c == NULL) {
+ cmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+ if (cmd == NULL) {
res = _FAIL;
goto exit;
}
- psetstakey_para = (struct set_stakey_parm *)rtw_zmalloc(sizeof(struct set_stakey_parm));
- if (psetstakey_para == NULL) {
- rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj));
+ param = (struct set_stakey_parm *)rtw_zmalloc(sizeof(struct set_stakey_parm));
+ if (param == NULL) {
+ rtw_mfree((u8 *) cmd, sizeof(struct cmd_obj));
res = _FAIL;
goto exit;
}
- init_h2fwcmd_w_parm_no_rsp(ph2c, psetstakey_para, _SetStaKey_CMD_);
-
-
- psetstakey_para->algorithm = (u8)psta->dot118021XPrivacy;
-
- _rtw_memcpy(psetstakey_para->addr, psta->hwaddr, ETH_ALEN);
-
- _rtw_memcpy(psetstakey_para->key, &psta->dot118021x_UncstKey, 16);
+ init_h2fwcmd_w_parm_no_rsp(cmd, param, _SetStaKey_CMD_);
+ _rtw_memcpy(param->addr, addr, ETH_ALEN);
+ param->algorithm = alg;
+ param->keyid = keyid;
+ _rtw_memcpy(param->key, key, 16);
+ param->gk = gk;
- res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+ res = rtw_enqueue_cmd(cmdpriv, cmd);
exit:
-
return res;
+}
+u8 rtw_ap_set_pairwise_key(_adapter *padapter, struct sta_info *psta)
+{
+ return rtw_ap_set_sta_key(padapter
+ , psta->cmn.mac_addr
+ , psta->dot118021XPrivacy
+ , psta->dot118021x_UncstKey.skey
+ , 0
+ , 0
+ );
}
static int rtw_ap_set_key(_adapter *padapter, u8 *key, u8 alg, int keyid, u8 set_tx)
@@ -2383,7 +2649,7 @@ u8 rtw_ap_bmc_frames_hdl(_adapter *padapter)
_enter_critical_bh(&pxmitpriv->lock, &irqL);
- if ((pstapriv->tim_bitmap & BIT(0)) && (psta_bmc->sleepq_len > 0)) {
+ if ((rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0)) && (psta_bmc->sleepq_len > 0)) {
int tx_counts = 0;
_update_beacon(padapter, _TIM_IE_, NULL, _FALSE, "update TIM with TIB=1");
@@ -2428,11 +2694,11 @@ u8 rtw_ap_bmc_frames_hdl(_adapter *padapter)
/*RTW_INFO("sleepq_len of bmc_sta = %d\n", psta_bmc->sleepq_len);*/
- if (pstapriv->tim_bitmap & BIT(0))
+ if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0))
update_tim = _TRUE;
- pstapriv->tim_bitmap &= ~BIT(0);
- pstapriv->sta_dz_bitmap &= ~BIT(0);
+ rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, 0);
+ rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, 0);
if (update_tim == _TRUE) {
RTW_INFO("clear TIB\n");
@@ -2465,13 +2731,13 @@ static void associated_stainfo_update(_adapter *padapter, struct sta_info *psta,
{
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
- RTW_INFO("%s: "MAC_FMT", updated_type=0x%x\n", __func__, MAC_ARG(psta->hwaddr), sta_info_type);
+ RTW_INFO("%s: "MAC_FMT", updated_type=0x%x\n", __func__, MAC_ARG(psta->cmn.mac_addr), sta_info_type);
if (sta_info_type & STA_INFO_UPDATE_BW) {
if ((psta->flags & WLAN_STA_HT) && !psta->ht_20mhz_set) {
if (pmlmepriv->sw_to_20mhz) {
- psta->bw_mode = CHANNEL_WIDTH_20;
+ psta->cmn.bw_mode = CHANNEL_WIDTH_20;
/*psta->htpriv.ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;*/
psta->htpriv.sgi_40m = _FALSE;
} else {
@@ -2526,12 +2792,6 @@ static void update_bcn_ext_capab_ie(_adapter *padapter)
}
-static void update_bcn_fixed_ie(_adapter *padapter)
-{
- RTW_INFO("%s\n", __FUNCTION__);
-
-}
-
static void update_bcn_erpinfo_ie(_adapter *padapter)
{
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
@@ -2596,7 +2856,7 @@ static void update_bcn_htinfo_ie(_adapter *padapter)
__FUNCTION__, pmlmepriv->ht_op_mode);
RTW_INFO("num_sta_40mhz_intolerant(%d), 20mhz_width_req(%d), intolerant_ch_rpt(%d), olbc(%d)\n",
- pmlmepriv->num_sta_40mhz_intolerant, pmlmepriv->ht_20mhz_width_req, pmlmepriv->ht_intolerant_ch_reported, pmlmepriv->olbc);
+ pmlmepriv->num_sta_40mhz_intolerant, pmlmepriv->ht_20mhz_width_req, pmlmepriv->ht_intolerant_ch_reported, ATOMIC_READ(&pmlmepriv->olbc));
/*parsing HT_INFO_IE, currently only update ht_op_mode - pht_info->infos[1] & pht_info->infos[2] for wifi logo test*/
p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_ADD_INFO_IE_, &len, (pnetwork->IELength - _BEACON_IE_OFFSET_));
@@ -2608,7 +2868,7 @@ static void update_bcn_htinfo_ie(_adapter *padapter)
/* for STA Channel Width/Secondary Channel Offset*/
if ((pmlmepriv->sw_to_20mhz == 0) && (pmlmeext->cur_channel <= 14)) {
if ((pmlmepriv->num_sta_40mhz_intolerant > 0) || (pmlmepriv->ht_20mhz_width_req == _TRUE)
- || (pmlmepriv->ht_intolerant_ch_reported == _TRUE) || (pmlmepriv->olbc == _TRUE)) {
+ || (pmlmepriv->ht_intolerant_ch_reported == _TRUE) || (ATOMIC_READ(&pmlmepriv->olbc) == _TRUE)) {
SET_HT_OP_ELE_2ND_CHL_OFFSET(pht_info, 0);
SET_HT_OP_ELE_STA_CHL_WIDTH(pht_info, 0);
@@ -2625,7 +2885,7 @@ static void update_bcn_htinfo_ie(_adapter *padapter)
} else {
if ((pmlmepriv->num_sta_40mhz_intolerant == 0) && (pmlmepriv->ht_20mhz_width_req == _FALSE)
- && (pmlmepriv->ht_intolerant_ch_reported == _FALSE) && (pmlmepriv->olbc == _FALSE)) {
+ && (pmlmepriv->ht_intolerant_ch_reported == _FALSE) && (ATOMIC_READ(&pmlmepriv->olbc) == _FALSE)) {
if (pmlmeext->cur_bwmode >= CHANNEL_WIDTH_40) {
@@ -2732,6 +2992,9 @@ static void update_bcn_wps_ie(_adapter *padapter)
if (sr) {
set_fwstate(pmlmepriv, WIFI_UNDER_WPS);
RTW_INFO("%s, set WIFI_UNDER_WPS\n", __func__);
+ } else {
+ clr_fwstate(pmlmepriv, WIFI_UNDER_WPS);
+ RTW_INFO("%s, clr WIFI_UNDER_WPS\n", __func__);
}
}
#endif
@@ -2764,83 +3027,70 @@ void _update_beacon(_adapter *padapter, u8 ie_id, u8 *oui, u8 tx, const char *ta
{
_irqL irqL;
struct mlme_priv *pmlmepriv;
- struct mlme_ext_priv *pmlmeext;
- /* struct mlme_ext_info *pmlmeinfo; */
-
- /* RTW_INFO("%s\n", __FUNCTION__); */
+ struct mlme_ext_priv *pmlmeext;
+ bool updated = 1; /* treat as upadated by default */
if (!padapter)
return;
pmlmepriv = &(padapter->mlmepriv);
pmlmeext = &(padapter->mlmeextpriv);
- /* pmlmeinfo = &(pmlmeext->mlmext_info); */
- if (_FALSE == pmlmeext->bstart_bss)
+ if (pmlmeext->bstart_bss == _FALSE)
return;
_enter_critical_bh(&pmlmepriv->bcn_update_lock, &irqL);
switch (ie_id) {
- case 0xFF:
-
- update_bcn_fixed_ie(padapter);/* 8: TimeStamp, 2: Beacon Interval 2:Capability */
-
- break;
-
case _TIM_IE_:
-
update_BCNTIM(padapter);
-
break;
case _ERPINFO_IE_:
-
update_bcn_erpinfo_ie(padapter);
-
break;
case _HT_CAPABILITY_IE_:
-
update_bcn_htcap_ie(padapter);
-
break;
case _RSN_IE_2_:
-
update_bcn_rsn_ie(padapter);
-
break;
case _HT_ADD_INFO_IE_:
-
update_bcn_htinfo_ie(padapter);
-
break;
case _EXT_CAP_IE_:
-
update_bcn_ext_capab_ie(padapter);
+ break;
+#ifdef CONFIG_RTW_MESH
+ case WLAN_EID_MESH_CONFIG:
+ updated = rtw_mesh_update_bss_peering_status(padapter, &(pmlmeext->mlmext_info.network));
+ updated |= rtw_mesh_update_bss_formation_info(padapter, &(pmlmeext->mlmext_info.network));
+ updated |= rtw_mesh_update_bss_forwarding_state(padapter, &(pmlmeext->mlmext_info.network));
break;
+#endif
case _VENDOR_SPECIFIC_IE_:
-
update_bcn_vendor_spec_ie(padapter, oui);
-
break;
+ case 0xFF:
default:
break;
}
- pmlmepriv->update_bcn = _TRUE;
+ if (updated)
+ pmlmepriv->update_bcn = _TRUE;
_exit_critical_bh(&pmlmepriv->bcn_update_lock, &irqL);
#ifndef CONFIG_INTERRUPT_BASED_TXBCN
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
- if (tx) {
+ if (tx && updated) {
/* send_beacon(padapter); */ /* send_beacon must execute on TSR level */
if (0)
RTW_INFO(FUNC_ADPT_FMT" ie_id:%u - %s\n", FUNC_ADPT_ARG(padapter), ie_id, tag);
@@ -2852,7 +3102,6 @@ void _update_beacon(_adapter *padapter, u8 ie_id, u8 *oui, u8 tx, const char *ta
}
#endif
#endif /* !CONFIG_INTERRUPT_BASED_TXBCN */
-
}
#ifdef CONFIG_80211N_HT
@@ -2867,7 +3116,7 @@ void rtw_process_public_act_bsscoex(_adapter *padapter, u8 *pframe, uint frame_l
uint frame_body_len = frame_len - sizeof(struct rtw_ieee80211_hdr_3addr);
u8 category, action;
- psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe));
+ psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
if (psta == NULL)
return;
@@ -2960,7 +3209,7 @@ Set to 2 if only HT STAs are associated in BSS,
Set to 3 (HT mixed mode) when one or more non-HT STAs are associated
(currently non-GF HT station is considered as non-HT STA also)
*/
-static int rtw_ht_operation_update(_adapter *padapter)
+int rtw_ht_operation_update(_adapter *padapter)
{
u16 cur_op_mode, new_op_mode;
int op_mode_changes = 0;
@@ -2990,12 +3239,12 @@ static int rtw_ht_operation_update(_adapter *padapter)
}
if (!(pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT) &&
- (pmlmepriv->num_sta_no_ht || pmlmepriv->olbc_ht)) {
+ (pmlmepriv->num_sta_no_ht || ATOMIC_READ(&pmlmepriv->olbc_ht))) {
pmlmepriv->ht_op_mode |= HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT;
op_mode_changes++;
} else if ((pmlmepriv->ht_op_mode &
HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT) &&
- (pmlmepriv->num_sta_no_ht == 0 && !pmlmepriv->olbc_ht)) {
+ (pmlmepriv->num_sta_no_ht == 0 && !ATOMIC_READ(&pmlmepriv->olbc_ht))) {
pmlmepriv->ht_op_mode &=
~HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT;
op_mode_changes++;
@@ -3012,7 +3261,7 @@ static int rtw_ht_operation_update(_adapter *padapter)
else if ((phtpriv_ap->ht_cap.cap_info & IEEE80211_HT_CAP_SUP_WIDTH)
&& pmlmepriv->num_sta_ht_20mhz)
new_op_mode = OP_MODE_20MHZ_HT_STA_ASSOCED;
- else if (pmlmepriv->olbc_ht)
+ else if (ATOMIC_READ(&pmlmepriv->olbc_ht))
new_op_mode = OP_MODE_MAY_BE_LEGACY_STAS;
else
new_op_mode = OP_MODE_PURE;
@@ -3089,11 +3338,8 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta)
pmlmepriv->num_sta_no_short_preamble++;
if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&
- (pmlmepriv->num_sta_no_short_preamble == 1)) {
+ (pmlmepriv->num_sta_no_short_preamble == 1))
beacon_updated = _TRUE;
- update_beacon(padapter, 0xFF, NULL, _TRUE);
- }
-
}
} else {
if (psta->no_short_preamble_set) {
@@ -3102,11 +3348,8 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta)
pmlmepriv->num_sta_no_short_preamble--;
if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&
- (pmlmepriv->num_sta_no_short_preamble == 0)) {
+ (pmlmepriv->num_sta_no_short_preamble == 0))
beacon_updated = _TRUE;
- update_beacon(padapter, 0xFF, NULL, _TRUE);
- }
-
}
}
@@ -3127,7 +3370,7 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta)
if (pmlmepriv->num_sta_non_erp == 1) {
beacon_updated = _TRUE;
- update_beacon(padapter, _ERPINFO_IE_, NULL, _TRUE);
+ update_beacon(padapter, _ERPINFO_IE_, NULL, _FALSE);
}
}
@@ -3139,7 +3382,7 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta)
if (pmlmepriv->num_sta_non_erp == 0) {
beacon_updated = _TRUE;
- update_beacon(padapter, _ERPINFO_IE_, NULL, _TRUE);
+ update_beacon(padapter, _ERPINFO_IE_, NULL, _FALSE);
}
}
@@ -3164,11 +3407,8 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta)
pmlmepriv->num_sta_no_short_slot_time++;
if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&
- (pmlmepriv->num_sta_no_short_slot_time == 1)) {
+ (pmlmepriv->num_sta_no_short_slot_time == 1))
beacon_updated = _TRUE;
- update_beacon(padapter, 0xFF, NULL, _TRUE);
- }
-
}
} else {
if (psta->no_short_slot_time_set) {
@@ -3177,20 +3417,17 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta)
pmlmepriv->num_sta_no_short_slot_time--;
if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) &&
- (pmlmepriv->num_sta_no_short_slot_time == 0)) {
+ (pmlmepriv->num_sta_no_short_slot_time == 0))
beacon_updated = _TRUE;
- update_beacon(padapter, 0xFF, NULL, _TRUE);
- }
}
}
#ifdef CONFIG_80211N_HT
-
if (psta->flags & WLAN_STA_HT) {
u16 ht_capab = le16_to_cpu(psta->htpriv.ht_cap.cap_info);
- RTW_INFO("HT: STA " MAC_FMT " HT Capabilities "
- "Info: 0x%04x\n", MAC_ARG(psta->hwaddr), ht_capab);
+ RTW_INFO("HT: STA " MAC_FMT " HT Capabilities Info: 0x%04x\n",
+ MAC_ARG(psta->cmn.mac_addr), ht_capab);
if (psta->no_ht_set) {
psta->no_ht_set = 0;
@@ -3204,7 +3441,7 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta)
}
RTW_INFO("%s STA " MAC_FMT " - no "
"greenfield, num of non-gf stations %d\n",
- __FUNCTION__, MAC_ARG(psta->hwaddr),
+ __FUNCTION__, MAC_ARG(psta->cmn.mac_addr),
pmlmepriv->num_sta_ht_no_gf);
}
@@ -3215,39 +3452,16 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta)
}
RTW_INFO("%s STA " MAC_FMT " - 20 MHz HT, "
"num of 20MHz HT STAs %d\n",
- __FUNCTION__, MAC_ARG(psta->hwaddr),
+ __FUNCTION__, MAC_ARG(psta->cmn.mac_addr),
pmlmepriv->num_sta_ht_20mhz);
}
-
- if (ht_capab & RTW_IEEE80211_HT_CAP_40MHZ_INTOLERANT) {
-
- if (!psta->ht_40mhz_intolerant) {
- psta->ht_40mhz_intolerant = 1;
- pmlmepriv->num_sta_40mhz_intolerant++;
- RTW_INFO("%s STA " MAC_FMT " - HT_CAP_40MHZ_INTOLERANT is set\n" ,
- __FUNCTION__, MAC_ARG(psta->hwaddr));
- beacon_updated = _TRUE;
- }
-
- /*
- if (pmlmepriv->ht_40mhz_intolerant == _FALSE) {
-
- pmlmepriv->ht_40mhz_intolerant = _TRUE;
-
- RTW_INFO("%s STA " MAC_FMT " - HT_CAP_40MHZ_INTOLERANT is set\n" ,
- __FUNCTION__, MAC_ARG(psta->hwaddr));
-
- beacon_updated = _TRUE;
- }
- */
-
- /*update ext_capab_ie_len & ext_capab_ie_data for beacon, probersp, assocrsp.*/
- if (pmlmepriv->ext_capab_ie_len == 0)
- pmlmepriv->ext_capab_ie_len = 1;
- SET_EXT_CAPABILITY_ELE_BSS_COEXIST(pmlmepriv->ext_capab_ie_data, 1);
-
- update_beacon(padapter, _EXT_CAP_IE_, NULL, _FALSE);
+ if (((ht_capab & RTW_IEEE80211_HT_CAP_40MHZ_INTOLERANT) != 0) &&
+ (psta->ht_40mhz_intolerant == 0)) {
+ psta->ht_40mhz_intolerant = 1;
+ pmlmepriv->num_sta_40mhz_intolerant++;
+ RTW_INFO("%s STA " MAC_FMT " - 40MHZ_INTOLERANT, ",
+ __FUNCTION__, MAC_ARG(psta->cmn.mac_addr));
}
} else {
@@ -3258,19 +3472,32 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta)
if (pmlmepriv->htpriv.ht_option == _TRUE) {
RTW_INFO("%s STA " MAC_FMT
" - no HT, num of non-HT stations %d\n",
- __FUNCTION__, MAC_ARG(psta->hwaddr),
+ __FUNCTION__, MAC_ARG(psta->cmn.mac_addr),
pmlmepriv->num_sta_no_ht);
}
}
if (rtw_ht_operation_update(padapter) > 0) {
update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE);
- update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE);
- /*beacon_updated = _TRUE;*/
+ update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _FALSE);
+ beacon_updated = _TRUE;
}
-
#endif /* CONFIG_80211N_HT */
+#ifdef CONFIG_RTW_MESH
+ if (MLME_IS_MESH(padapter)) {
+ struct sta_priv *pstapriv = &padapter->stapriv;
+
+ update_beacon(padapter, WLAN_EID_MESH_CONFIG, NULL, _FALSE);
+ if (pstapriv->asoc_list_cnt == 1)
+ _set_timer(&padapter->mesh_atlm_param_req_timer, 0);
+ beacon_updated = _TRUE;
+ }
+#endif
+
+ if (beacon_updated)
+ update_beacon(padapter, 0xFF, NULL, _TRUE);
+
/* update associcated stations cap. */
associated_clients_update(padapter, beacon_updated, STA_INFO_UPDATE_ALL);
@@ -3281,20 +3508,25 @@ void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta)
u8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta)
{
u8 beacon_updated = _FALSE;
+ struct sta_priv *pstapriv = &padapter->stapriv;
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
if (!psta)
return beacon_updated;
+ if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid)) {
+ rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid);
+ beacon_updated = _TRUE;
+ update_beacon(padapter, _TIM_IE_, NULL, _FALSE);
+ }
+
if (psta->no_short_preamble_set) {
psta->no_short_preamble_set = 0;
pmlmepriv->num_sta_no_short_preamble--;
if (pmlmeext->cur_wireless_mode > WIRELESS_11B
- && pmlmepriv->num_sta_no_short_preamble == 0) {
+ && pmlmepriv->num_sta_no_short_preamble == 0)
beacon_updated = _TRUE;
- update_beacon(padapter, 0xFF, NULL, _TRUE);
- }
}
if (psta->nonerp_set) {
@@ -3302,7 +3534,7 @@ u8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta)
pmlmepriv->num_sta_non_erp--;
if (pmlmepriv->num_sta_non_erp == 0) {
beacon_updated = _TRUE;
- update_beacon(padapter, _ERPINFO_IE_, NULL, _TRUE);
+ update_beacon(padapter, _ERPINFO_IE_, NULL, _FALSE);
}
}
@@ -3310,14 +3542,11 @@ u8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta)
psta->no_short_slot_time_set = 0;
pmlmepriv->num_sta_no_short_slot_time--;
if (pmlmeext->cur_wireless_mode > WIRELESS_11B
- && pmlmepriv->num_sta_no_short_slot_time == 0) {
+ && pmlmepriv->num_sta_no_short_slot_time == 0)
beacon_updated = _TRUE;
- update_beacon(padapter, 0xFF, NULL, _TRUE);
- }
}
#ifdef CONFIG_80211N_HT
-
if (psta->no_ht_gf_set) {
psta->no_ht_gf_set = 0;
pmlmepriv->num_sta_ht_no_gf--;
@@ -3335,26 +3564,30 @@ u8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta)
if (psta->ht_40mhz_intolerant) {
psta->ht_40mhz_intolerant = 0;
- pmlmepriv->num_sta_40mhz_intolerant--;
-
- /*update ext_capab_ie_len & ext_capab_ie_data for beacon, probersp, assocrsp.*/
- if ((pmlmepriv->ext_capab_ie_len > 0) && (pmlmepriv->num_sta_40mhz_intolerant == 0)) {
- SET_EXT_CAPABILITY_ELE_BSS_COEXIST(pmlmepriv->ext_capab_ie_data, 0);
- update_beacon(padapter, _EXT_CAP_IE_, NULL, _FALSE);
- }
-
- beacon_updated = _TRUE;
-
- update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _FALSE);
+ if (pmlmepriv->num_sta_40mhz_intolerant > 0)
+ pmlmepriv->num_sta_40mhz_intolerant--;
+ else
+ rtw_warn_on(1);
}
if (rtw_ht_operation_update(padapter) > 0) {
update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE);
- update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE);
+ update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _FALSE);
}
-
#endif /* CONFIG_80211N_HT */
+#ifdef CONFIG_RTW_MESH
+ if (MLME_IS_MESH(padapter)) {
+ update_beacon(padapter, WLAN_EID_MESH_CONFIG, NULL, _FALSE);
+ if (pstapriv->asoc_list_cnt == 0)
+ _cancel_timer_ex(&padapter->mesh_atlm_param_req_timer);
+ beacon_updated = _TRUE;
+ }
+#endif
+
+ if (beacon_updated == _TRUE)
+ update_beacon(padapter, 0xFF, NULL, _TRUE);
+
#if 0
/* update associated stations cap. */
associated_clients_update(padapter, beacon_updated, STA_INFO_UPDATE_ALL); /* move it to avoid deadlock */
@@ -3380,18 +3613,24 @@ u8 ap_free_sta(_adapter *padapter, struct sta_info *psta, bool active, u16 reaso
if (active == _TRUE) {
#ifdef CONFIG_80211N_HT
/* tear down Rx AMPDU */
- send_delba(padapter, 0, psta->hwaddr);/* recipient */
+ send_delba(padapter, 0, psta->cmn.mac_addr);/* recipient */
/* tear down TX AMPDU */
- send_delba(padapter, 1, psta->hwaddr);/* */ /* originator */
+ send_delba(padapter, 1, psta->cmn.mac_addr);/* */ /* originator */
#endif /* CONFIG_80211N_HT */
- issue_deauth(padapter, psta->hwaddr, reason);
+ if (!MLME_IS_MESH(padapter))
+ issue_deauth(padapter, psta->cmn.mac_addr, reason);
}
+#ifdef CONFIG_RTW_MESH
+ if (MLME_IS_MESH(padapter))
+ rtw_mesh_path_flush_by_nexthop(psta);
+#endif
+
#ifdef CONFIG_BEAMFORMING
- beamforming_wk_cmd(padapter, BEAMFORMING_CTRL_LEAVE, psta->hwaddr, ETH_ALEN, 1);
+ beamforming_wk_cmd(padapter, BEAMFORMING_CTRL_LEAVE, psta->cmn.mac_addr, ETH_ALEN, 1);
#endif
psta->htpriv.agg_enable_bitmap = 0x0;/* reset */
@@ -3405,22 +3644,21 @@ u8 ap_free_sta(_adapter *padapter, struct sta_info *psta, bool active, u16 reaso
psta->state &= ~_FW_LINKED;
_exit_critical_bh(&psta->lock, &irqL);
+ if (!MLME_IS_MESH(padapter)) {
#ifdef CONFIG_IOCTL_CFG80211
- if (1) {
-#ifdef COMPAT_KERNEL_RELEASE
- rtw_cfg80211_indicate_sta_disassoc(padapter, psta->hwaddr, reason);
-#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER)
- rtw_cfg80211_indicate_sta_disassoc(padapter, psta->hwaddr, reason);
-#else /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) */
+ #ifdef COMPAT_KERNEL_RELEASE
+ rtw_cfg80211_indicate_sta_disassoc(padapter, psta->cmn.mac_addr, reason);
+ #elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER)
+ rtw_cfg80211_indicate_sta_disassoc(padapter, psta->cmn.mac_addr, reason);
+ #else /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) */
/* will call rtw_cfg80211_indicate_sta_disassoc() in cmd_thread for old API context */
-#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) */
- } else
-#endif /* CONFIG_IOCTL_CFG80211 */
- {
+ #endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) */
+#else
rtw_indicate_sta_disassoc_event(padapter, psta);
+#endif
}
- report_del_sta_event(padapter, psta->hwaddr, reason, enqueue, _FALSE);
+ report_del_sta_event(padapter, psta->cmn.mac_addr, reason, enqueue, _FALSE);
beacon_updated = bss_cap_update_on_sta_leave(padapter, psta);
@@ -3459,7 +3697,7 @@ int rtw_ap_inform_ch_switch(_adapter *padapter, u8 new_ch, u8 ch_offset)
psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
plist = get_next(plist);
- issue_action_spct_ch_switch(padapter, psta->hwaddr, new_ch, ch_offset);
+ issue_action_spct_ch_switch(padapter, psta->cmn.mac_addr, new_ch, ch_offset);
psta->expire_to = ((pstapriv->expire_to * 2) > 5) ? 5 : (pstapriv->expire_to * 2);
}
_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
@@ -3483,7 +3721,7 @@ int rtw_sta_flush(_adapter *padapter, bool enqueue)
char flush_list[NUM_STA];
int i;
- if ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)
+ if (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter))
return ret;
RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(padapter->pnetdev));
@@ -3500,6 +3738,7 @@ int rtw_sta_flush(_adapter *padapter, bool enqueue)
rtw_list_delete(&psta->asoc_list);
pstapriv->asoc_list_cnt--;
+ STA_SET_MESH_PLINK(psta, NULL);
stainfo_offset = rtw_stainfo_offset(pstapriv, psta);
if (stainfo_offset_valid(stainfo_offset))
@@ -3511,11 +3750,20 @@ int rtw_sta_flush(_adapter *padapter, bool enqueue)
/* call ap_free_sta() for each sta picked */
for (i = 0; i < flush_num; i++) {
+ u8 sta_addr[ETH_ALEN];
+
psta = rtw_get_stainfo_by_offset(pstapriv, flush_list[i]);
+ _rtw_memcpy(sta_addr, psta->cmn.mac_addr, ETH_ALEN);
+
ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_DEAUTH_LEAVING, enqueue);
+ #ifdef CONFIG_RTW_MESH
+ if (MLME_IS_MESH(padapter))
+ rtw_mesh_expire_peer(padapter, sta_addr);
+ #endif
}
- issue_deauth(padapter, bc_addr, WLAN_REASON_DEAUTH_LEAVING);
+ if (!MLME_IS_MESH(padapter))
+ issue_deauth(padapter, bc_addr, WLAN_REASON_DEAUTH_LEAVING);
associated_clients_update(padapter, _TRUE, STA_INFO_UPDATE_ALL);
@@ -3564,19 +3812,14 @@ void sta_info_update(_adapter *padapter, struct sta_info *psta)
psta->vhtpriv.vht_option = _FALSE;
#endif
-
update_sta_info_apmode(padapter, psta);
-
-
}
/* called >= TSR LEVEL for USB or SDIO Interface*/
void ap_sta_info_defer_update(_adapter *padapter, struct sta_info *psta)
{
- if (psta->state & _FW_LINKED) {
- /* add ratid */
- add_RATid(padapter, psta, 0);/* DM_RATR_STA_INIT */
- }
+ if (psta->state & _FW_LINKED)
+ rtw_hal_update_ra_mask(psta); /* DM_RATR_STA_INIT */
}
/* restore hw setting from sw data structures */
void rtw_ap_restore_network(_adapter *padapter)
@@ -3593,7 +3836,10 @@ void rtw_ap_restore_network(_adapter *padapter)
char chk_alive_list[NUM_STA];
int i;
- rtw_setopmode_cmd(padapter, Ndis802_11APMode, _FALSE);
+ rtw_setopmode_cmd(padapter
+ , MLME_IS_AP(padapter) ? Ndis802_11APMode : Ndis802_11_mesh
+ , RTW_CMDF_DIRECTLY
+ );
set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
@@ -3673,8 +3919,8 @@ void start_ap_mode(_adapter *padapter)
pmlmepriv->num_sta_ht_20mhz = 0;
pmlmepriv->num_sta_40mhz_intolerant = 0;
- pmlmepriv->olbc = _FALSE;
- pmlmepriv->olbc_ht = _FALSE;
+ ATOMIC_SET(&pmlmepriv->olbc, _FALSE);
+ ATOMIC_SET(&pmlmepriv->olbc_ht, _FALSE);
#ifdef CONFIG_80211N_HT
pmlmepriv->ht_20mhz_width_req = _FALSE;
@@ -3690,13 +3936,9 @@ void start_ap_mode(_adapter *padapter)
psecuritypriv->dot118021x_bmc_cam_id = INVALID_SEC_MAC_CAM_ID;
#endif
- for (i = 0 ; i < NUM_STA ; i++)
+ for (i = 0 ; i < pstapriv->max_aid; i++)
pstapriv->sta_aid[i] = NULL;
-#if CONFIG_RTW_MACADDR_ACL
- rtw_macaddr_acl_init(padapter);
-#endif
-
psta = rtw_get_bcmc_stainfo(padapter);
/*_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);*/
if (psta)
@@ -3710,8 +3952,28 @@ void start_ap_mode(_adapter *padapter)
}
+void rtw_ap_bcmc_sta_flush(_adapter *padapter)
+{
+#ifdef CONFIG_CONCURRENT_MODE
+ int cam_id = -1;
+ u8 *addr = adapter_mac_addr(padapter);
+
+ cam_id = rtw_iface_bcmc_id_get(padapter);
+ if (cam_id != INVALID_SEC_MAC_CAM_ID) {
+ RTW_PRINT("clear group key for "ADPT_FMT" addr:"MAC_FMT", camid:%d\n",
+ ADPT_ARG(padapter), MAC_ARG(addr), cam_id);
+ clear_cam_entry(padapter, cam_id);
+ rtw_camid_free(padapter, cam_id);
+ rtw_iface_bcmc_id_set(padapter, INVALID_SEC_MAC_CAM_ID); /*init default value*/
+ }
+#else
+ invalidate_cam_all(padapter);
+#endif
+}
+
void stop_ap_mode(_adapter *padapter)
{
+ u8 self_action = MLME_ACTION_UNKNOWN;
_irqL irqL;
struct sta_info *psta = NULL;
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
@@ -3720,6 +3982,13 @@ void stop_ap_mode(_adapter *padapter)
RTW_INFO("%s -"ADPT_FMT"\n", __func__, ADPT_ARG(padapter));
+ if (MLME_IS_AP(padapter))
+ self_action = MLME_AP_STOPPED;
+ else if (MLME_IS_MESH(padapter))
+ self_action = MLME_MESH_STOPPED;
+ else
+ rtw_warn_on(1);
+
pmlmepriv->update_bcn = _FALSE;
/*pmlmeext->bstart_bss = _FALSE;*/
padapter->netif_up = _FALSE;
@@ -3731,25 +4000,29 @@ void stop_ap_mode(_adapter *padapter)
padapter->securitypriv.ndisencryptstatus = Ndis802_11WEPDisabled;
#ifdef CONFIG_DFS_MASTER
- rtw_dfs_master_status_apply(padapter, MLME_AP_STOPPED);
+ rtw_dfs_master_status_apply(padapter, self_action);
#endif
/* free scan queue */
rtw_free_network_queue(padapter, _TRUE);
#if CONFIG_RTW_MACADDR_ACL
- rtw_macaddr_acl_deinit(padapter);
+ rtw_macaddr_acl_clear(padapter, RTW_ACL_PERIOD_BSS);
#endif
rtw_sta_flush(padapter, _TRUE);
+ rtw_ap_bcmc_sta_flush(padapter);
/* free_assoc_sta_resources */
rtw_free_all_stainfo(padapter);
psta = rtw_get_bcmc_stainfo(padapter);
- /* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */
- rtw_free_stainfo(padapter, psta);
- /*_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);*/
+ if (psta) {
+ rtw_sta_mstatus_disc_rpt(padapter, psta->cmn.mac_id);
+ /* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */
+ rtw_free_stainfo(padapter, psta);
+ /*_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);*/
+ }
rtw_free_mlme_priv_ie_data(pmlmepriv);
@@ -3774,6 +4047,8 @@ void stop_ap_mode(_adapter *padapter)
pmlmeext->bstart_bss = _FALSE;
+ rtw_hal_rcr_set_chk_bssid(padapter, self_action);
+
#ifdef CONFIG_BT_COEXIST
rtw_btcoex_MediaStatusNotify(padapter, 0); /* disconnect */
#endif
@@ -3786,10 +4061,32 @@ void rtw_ap_update_bss_chbw(_adapter *adapter, WLAN_BSSID_EX *bss, u8 ch, u8 bw,
{
#define UPDATE_VHT_CAP 1
#define UPDATE_HT_CAP 1
-
#ifdef CONFIG_80211AC_VHT
+ struct vht_priv *vhtpriv = &adapter->mlmepriv.vhtpriv;
+#endif
{
- struct vht_priv *vhtpriv = &adapter->mlmepriv.vhtpriv;
+ u8 *p;
+ int ie_len;
+ u8 old_ch = bss->Configuration.DSConfig;
+ bool change_band = _FALSE;
+
+ if ((ch <= 14 && old_ch >= 36) || (ch >= 36 && old_ch <= 14))
+ change_band = _TRUE;
+
+ /* update channel in IE */
+ p = rtw_get_ie((bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)), _DSSET_IE_, &ie_len, (bss->IELength - sizeof(NDIS_802_11_FIXED_IEs)));
+ if (p && ie_len > 0)
+ *(p + 2) = ch;
+
+ bss->Configuration.DSConfig = ch;
+
+ /* band is changed, update ERP, support rate, ext support rate IE */
+ if (change_band == _TRUE)
+ change_band_update_ie(adapter, bss, ch);
+ }
+
+#ifdef CONFIG_80211AC_VHT
+ if (vhtpriv->vht_option == _TRUE) {
u8 *vht_cap_ie, *vht_op_ie;
int vht_cap_ielen, vht_op_ielen;
u8 center_freq;
@@ -3800,17 +4097,17 @@ void rtw_ap_update_bss_chbw(_adapter *adapter, WLAN_BSSID_EX *bss, u8 ch, u8 bw,
/* update vht cap ie */
if (vht_cap_ie && vht_cap_ielen) {
-#if UPDATE_VHT_CAP
+ #if UPDATE_VHT_CAP
/* if ((bw == CHANNEL_WIDTH_160 || bw == CHANNEL_WIDTH_80_80) && pvhtpriv->sgi_160m)
SET_VHT_CAPABILITY_ELE_SHORT_GI160M(pvht_cap_ie + 2, 1);
else */
- SET_VHT_CAPABILITY_ELE_SHORT_GI160M(vht_cap_ie + 2, 0);
+ SET_VHT_CAPABILITY_ELE_SHORT_GI160M(vht_cap_ie + 2, 0);
if (bw >= CHANNEL_WIDTH_80 && vhtpriv->sgi_80m)
SET_VHT_CAPABILITY_ELE_SHORT_GI80M(vht_cap_ie + 2, 1);
else
SET_VHT_CAPABILITY_ELE_SHORT_GI80M(vht_cap_ie + 2, 0);
-#endif
+ #endif
}
/* update vht op ie */
@@ -3841,7 +4138,7 @@ void rtw_ap_update_bss_chbw(_adapter *adapter, WLAN_BSSID_EX *bss, u8 ch, u8 bw,
/* update ht cap ie */
if (ht_cap_ie && ht_cap_ielen) {
-#if UPDATE_HT_CAP
+ #if UPDATE_HT_CAP
if (bw >= CHANNEL_WIDTH_40)
SET_HT_CAP_ELE_CHL_WIDTH(ht_cap_ie + 2, 1);
else
@@ -3856,7 +4153,7 @@ void rtw_ap_update_bss_chbw(_adapter *adapter, WLAN_BSSID_EX *bss, u8 ch, u8 bw,
SET_HT_CAP_ELE_SHORT_GI20M(ht_cap_ie + 2, 1);
else
SET_HT_CAP_ELE_SHORT_GI20M(ht_cap_ie + 2, 0);
-#endif
+ #endif
}
/* update ht op ie */
@@ -3882,61 +4179,74 @@ void rtw_ap_update_bss_chbw(_adapter *adapter, WLAN_BSSID_EX *bss, u8 ch, u8 bw,
}
}
#endif /* CONFIG_80211N_HT */
-
- {
- u8 *p;
- int ie_len;
- u8 old_ch = bss->Configuration.DSConfig;
- bool change_band = _FALSE;
-
- if ((ch <= 14 && old_ch >= 36) || (ch >= 36 && old_ch <= 14))
- change_band = _TRUE;
-
- /* update channel in IE */
- p = rtw_get_ie((bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)), _DSSET_IE_, &ie_len, (bss->IELength - sizeof(NDIS_802_11_FIXED_IEs)));
- if (p && ie_len > 0)
- *(p + 2) = ch;
-
- bss->Configuration.DSConfig = ch;
-
- /* band is changed, update ERP, support rate, ext support rate IE */
- if (change_band == _TRUE)
- change_band_update_ie(adapter, bss, ch);
- }
-
}
+/*
+* return _TRUE if ch setting differs from mlmeext.network
+*/
bool rtw_ap_chbw_decision(_adapter *adapter, s16 req_ch, s8 req_bw, s8 req_offset
, u8 *ch, u8 *bw, u8 *offset, u8 *chbw_allow)
{
+ RT_CHANNEL_INFO *chset = adapter_to_chset(adapter);
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+ bool ch_avail = _FALSE;
u8 cur_ie_ch, cur_ie_bw, cur_ie_offset;
u8 dec_ch, dec_bw, dec_offset;
u8 u_ch = 0, u_offset, u_bw;
bool changed = _FALSE;
struct mlme_ext_priv *mlmeext = &(adapter->mlmeextpriv);
- WLAN_BSSID_EX *network = &(adapter->mlmepriv.cur_network.network);
- u8 sta_num;
- u8 ld_sta_num;
- u8 lg_sta_num;
- u8 ap_num;
- u8 ld_ap_num;
+ WLAN_BSSID_EX *network = &(mlmeext->mlmext_info.network);
+ struct mi_state mstate;
bool set_u_ch = _FALSE, set_dec_ch = _FALSE;
- rtw_ies_get_chbw(network->IEs + sizeof(NDIS_802_11_FIXED_IEs)
- , network->IELength - sizeof(NDIS_802_11_FIXED_IEs)
- , &cur_ie_ch, &cur_ie_bw, &cur_ie_offset);
+ rtw_ies_get_chbw(BSS_EX_TLV_IES(network), BSS_EX_TLV_IES_LEN(network)
+ , &cur_ie_ch, &cur_ie_bw, &cur_ie_offset, 1, 1);
+
+#ifdef CONFIG_MCC_MODE
+ if (MCC_EN(adapter)) {
+ if (rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC)) {
+ /* check channel settings are the same */
+ if (cur_ie_ch == mlmeext->cur_channel
+ && cur_ie_bw == mlmeext->cur_bwmode
+ && cur_ie_offset == mlmeext->cur_ch_offset) {
+
+
+ RTW_INFO(FUNC_ADPT_FMT"req ch settings are the same as current ch setting, go to exit\n"
+ , FUNC_ADPT_ARG(adapter));
+
+ *chbw_allow = _FALSE;
+ goto exit;
+ } else {
+ RTW_INFO(FUNC_ADPT_FMT"request channel settings are not the same as current channel setting(%d,%d,%d,%d,%d,%d), restart MCC\n"
+ , FUNC_ADPT_ARG(adapter)
+ , cur_ie_ch, cur_ie_bw, cur_ie_bw
+ , mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset);
+
+ rtw_hal_set_mcc_setting_disconnect(adapter);
+ }
+ }
+ }
+#endif /* CONFIG_MCC_MODE */
- /* use chbw of cur_ie updated with specifying req as temporary decision */
- dec_ch = (req_ch <= 0) ? cur_ie_ch : req_ch;
- dec_bw = (req_bw < 0) ? cur_ie_bw : req_bw;
- dec_offset = (req_offset < 0) ? cur_ie_offset : req_offset;
+ if (req_ch == 0) {
+ /* request comes from upper layer, use cur_ie values */
+ dec_ch = cur_ie_ch;
+ dec_bw = cur_ie_bw;
+ dec_offset = cur_ie_offset;
+ } else {
+ /* use chbw of cur_ie updated with specifying req as temporary decision */
+ dec_ch = (req_ch <= REQ_CH_NONE) ? cur_ie_ch : req_ch;
+ dec_bw = (req_bw <= REQ_BW_NONE) ? cur_ie_bw : req_bw;
+ dec_offset = (req_offset <= REQ_OFFSET_NONE) ? cur_ie_offset : req_offset;
+ }
- rtw_mi_status_no_self(adapter, &sta_num, &ld_sta_num, &lg_sta_num, &ap_num, &ld_ap_num, NULL);
- RTW_INFO(FUNC_ADPT_FMT" ld_sta_num:%u, lg_sta_num%u, ap_num:%u\n"
- , FUNC_ADPT_ARG(adapter), ld_sta_num, lg_sta_num, ap_num);
+ rtw_mi_status_no_self(adapter, &mstate);
+ RTW_INFO(FUNC_ADPT_FMT" ld_sta_num:%u, lg_sta_num%u, ap_num:%u, mesh_num:%u\n"
+ , FUNC_ADPT_ARG(adapter), MSTATE_STA_LD_NUM(&mstate), MSTATE_STA_LG_NUM(&mstate)
+ , MSTATE_AP_NUM(&mstate), MSTATE_MESH_NUM(&mstate));
- if (ld_sta_num || ap_num) {
- /* has linked STA or AP mode, follow */
+ if (MSTATE_STA_LD_NUM(&mstate) || MSTATE_AP_NUM(&mstate) || MSTATE_MESH_NUM(&mstate)) {
+ /* has linked STA or AP/Mesh mode */
rtw_warn_on(!rtw_mi_get_ch_setting_union_no_self(adapter, &u_ch, &u_bw, &u_offset));
@@ -3944,12 +4254,13 @@ bool rtw_ap_chbw_decision(_adapter *adapter, s16 req_ch, s8 req_bw, s8 req_offse
RTW_INFO(FUNC_ADPT_FMT" req: %d,%d,%d\n", FUNC_ADPT_ARG(adapter), req_ch, req_bw, req_offset);
rtw_adjust_chbw(adapter, u_ch, &dec_bw, &dec_offset);
+
#ifdef CONFIG_MCC_MODE
if (MCC_EN(adapter)) {
if (!rtw_is_chbw_grouped(u_ch, u_bw, u_offset, dec_ch, dec_bw, dec_offset)) {
- mlmeext->cur_channel = *ch = dec_ch;
- mlmeext->cur_bwmode = *bw = dec_bw;
- mlmeext->cur_ch_offset = *offset = dec_offset;
+ mlmeext->cur_channel = *ch = dec_ch = cur_ie_ch;
+ mlmeext->cur_bwmode = *bw = dec_bw = cur_ie_bw;
+ mlmeext->cur_ch_offset = *offset = dec_offset = cur_ie_offset;
/* channel bw offset can not be allowed, need MCC */
*chbw_allow = _FALSE;
RTW_INFO(FUNC_ADPT_FMT" enable mcc: %u,%u,%u\n", FUNC_ADPT_ARG(adapter)
@@ -3960,14 +4271,14 @@ bool rtw_ap_chbw_decision(_adapter *adapter, s16 req_ch, s8 req_bw, s8 req_offse
*chbw_allow = _TRUE;
}
#endif /* CONFIG_MCC_MODE */
- rtw_sync_chbw(&dec_ch, &dec_bw, &dec_offset
- , &u_ch, &u_bw, &u_offset);
- rtw_ap_update_bss_chbw(adapter, &(adapter->mlmepriv.cur_network.network)
- , dec_ch, dec_bw, dec_offset);
+ /* follow */
+ rtw_chset_sync_chbw(chset
+ , &dec_ch, &dec_bw, &dec_offset
+ , &u_ch, &u_bw, &u_offset);
set_u_ch = _TRUE;
- } else if (lg_sta_num) {
+ } else if (MSTATE_STA_LG_NUM(&mstate)) {
/* has linking STA */
rtw_warn_on(!rtw_mi_get_ch_setting_union_no_self(adapter, &u_ch, &u_bw, &u_offset));
@@ -3979,11 +4290,9 @@ bool rtw_ap_chbw_decision(_adapter *adapter, s16 req_ch, s8 req_bw, s8 req_offse
if (rtw_is_chbw_grouped(u_ch, u_bw, u_offset, dec_ch, dec_bw, dec_offset)) {
- rtw_sync_chbw(&dec_ch, &dec_bw, &dec_offset
- , &u_ch, &u_bw, &u_offset);
-
- rtw_ap_update_bss_chbw(adapter, &(adapter->mlmepriv.cur_network.network)
- , dec_ch, dec_bw, dec_offset);
+ rtw_chset_sync_chbw(chset
+ , &dec_ch, &dec_bw, &dec_offset
+ , &u_ch, &u_bw, &u_offset);
set_u_ch = _TRUE;
@@ -4003,62 +4312,114 @@ bool rtw_ap_chbw_decision(_adapter *adapter, s16 req_ch, s8 req_bw, s8 req_offse
goto exit;
}
#endif /* CONFIG_MCC_MODE */
+
/* set this for possible ch change when join down*/
set_fwstate(&adapter->mlmepriv, WIFI_OP_CH_SWITCHING);
}
} else {
- /* single AP mode */
+ /* single AP/Mesh mode */
RTW_INFO(FUNC_ADPT_FMT" req: %d,%d,%d\n", FUNC_ADPT_ARG(adapter), req_ch, req_bw, req_offset);
+ if (req_ch <= REQ_CH_NONE) /* channel is not specified */
+ goto choose_chbw;
+
+ if (rtw_chset_search_ch(chset, dec_ch) < 0) {
+ RTW_WARN(FUNC_ADPT_FMT" ch:%u doesn't fit in chplan\n", FUNC_ADPT_ARG(adapter), req_ch);
+ *chbw_allow = _FALSE;
+ goto exit;
+ }
+
/* check temporary decision first */
rtw_adjust_chbw(adapter, dec_ch, &dec_bw, &dec_offset);
- if (!rtw_get_offset_by_chbw(dec_ch, dec_bw, &dec_offset)) {
-#if defined(CONFIG_DFS_MASTER)
- if (req_ch == -1 || req_bw == -1)
- goto choose_chbw;
-#endif
+ if (!rtw_get_offset_by_chbw(dec_ch, dec_bw, &dec_offset)
+ && req_bw > REQ_BW_NONE
+ ) {
RTW_WARN(FUNC_ADPT_FMT" req: %u,%u has no valid offset\n", FUNC_ADPT_ARG(adapter), dec_ch, dec_bw);
*chbw_allow = _FALSE;
goto exit;
}
- if (!rtw_chset_is_chbw_valid(mlmeext->channel_set, dec_ch, dec_bw, dec_offset)) {
-#if defined(CONFIG_DFS_MASTER)
- if (req_ch == -1 || req_bw == -1)
- goto choose_chbw;
-#endif
- RTW_WARN(FUNC_ADPT_FMT" req: %u,%u,%u doesn't fit in chplan\n", FUNC_ADPT_ARG(adapter), dec_ch, dec_bw, dec_offset);
- *chbw_allow = _FALSE;
- goto exit;
+ while (!rtw_chset_is_chbw_valid(chset, dec_ch, dec_bw, dec_offset)
+ || (rtw_odm_dfs_domain_unknown(adapter) && rtw_is_dfs_chbw(dec_ch, dec_bw, dec_offset))
+ || rtw_chset_is_ch_non_ocp(chset, dec_ch, dec_bw, dec_offset)
+ ) {
+ dec_bw--;
+ if (dec_bw == CHANNEL_WIDTH_20) {
+ dec_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+ break;
+ }
+ }
+
+ if (rtw_odm_dfs_domain_unknown(adapter) && rtw_is_dfs_chbw(dec_ch, dec_bw, dec_offset)) {
+ RTW_WARN(FUNC_ADPT_FMT" DFS channel %u can't be used\n", FUNC_ADPT_ARG(adapter), dec_ch);
+ if (req_ch > 0) {
+ /* specific channel and not from IE => don't change channel setting */
+ *chbw_allow = _FALSE;
+ goto exit;
+ }
+ goto choose_chbw;
}
- if (rtw_chset_is_ch_non_ocp(mlmeext->channel_set, dec_ch, dec_bw, dec_offset) == _FALSE)
+ if (rtw_chset_is_ch_non_ocp(chset, dec_ch, dec_bw, dec_offset) == _FALSE)
goto update_bss_chbw;
+ RTW_WARN(FUNC_ADPT_FMT" DFS channel %u under non ocp\n", FUNC_ADPT_ARG(adapter), dec_ch);
choose_chbw:
- if (req_bw < 0)
+ req_ch = req_ch >= 0 ? dec_ch : 0;
+ if (req_bw <= REQ_BW_NONE)
req_bw = cur_ie_bw;
#if defined(CONFIG_DFS_MASTER)
- /* choose 5G DFS channel for debug */
- if (adapter_to_rfctl(adapter)->dbg_dfs_master_choose_dfs_ch_first
- && rtw_choose_shortest_waiting_ch(adapter, req_bw, &dec_ch, &dec_bw, &dec_offset, RTW_CHF_2G | RTW_CHF_NON_DFS) == _TRUE)
- RTW_INFO(FUNC_ADPT_FMT" choose 5G DFS channel for debug\n", FUNC_ADPT_ARG(adapter));
- else if (adapter_to_rfctl(adapter)->dfs_ch_sel_d_flags
- && rtw_choose_shortest_waiting_ch(adapter, req_bw, &dec_ch, &dec_bw, &dec_offset, adapter_to_rfctl(adapter)->dfs_ch_sel_d_flags) == _TRUE)
- RTW_INFO(FUNC_ADPT_FMT" choose with dfs_ch_sel_d_flags:0x%02x for debug\n", FUNC_ADPT_ARG(adapter), adapter_to_rfctl(adapter)->dfs_ch_sel_d_flags);
- else if (rtw_choose_shortest_waiting_ch(adapter, req_bw, &dec_ch, &dec_bw, &dec_offset, 0) == _FALSE) {
- RTW_WARN(FUNC_ADPT_FMT" no available channel\n", FUNC_ADPT_ARG(adapter));
- *chbw_allow = _FALSE;
- goto exit;
- }
+ if (!rtw_odm_dfs_domain_unknown(adapter)) {
+ if (rfctl->dbg_dfs_master_choose_dfs_ch_first) {
+ ch_avail = rtw_choose_shortest_waiting_ch(adapter, req_ch, req_bw
+ , &dec_ch, &dec_bw, &dec_offset
+ , RTW_CHF_2G | RTW_CHF_NON_DFS, mlmeext->cur_channel
+ , rfctl->ch_sel_same_band_prefer);
+ if (ch_avail == _TRUE) {
+ RTW_INFO(FUNC_ADPT_FMT" choose 5G DFS channel for debug\n", FUNC_ADPT_ARG(adapter));
+ goto update_bss_chbw;
+ }
+ }
+
+ if (rfctl->dfs_ch_sel_d_flags) {
+ ch_avail = rtw_choose_shortest_waiting_ch(adapter, req_ch, req_bw
+ , &dec_ch, &dec_bw, &dec_offset
+ , rfctl->dfs_ch_sel_d_flags, mlmeext->cur_channel
+ , rfctl->ch_sel_same_band_prefer);
+ if (ch_avail == _TRUE) {
+ RTW_INFO(FUNC_ADPT_FMT" choose with dfs_ch_sel_d_flags:0x%02x for debug\n"
+ , FUNC_ADPT_ARG(adapter), rfctl->dfs_ch_sel_d_flags);
+ goto update_bss_chbw;
+ }
+ }
+
+ ch_avail = rtw_choose_shortest_waiting_ch(adapter, req_ch, req_bw
+ , &dec_ch, &dec_bw, &dec_offset
+ , 0, mlmeext->cur_channel
+ , rfctl->ch_sel_same_band_prefer);
+ if (ch_avail == _FALSE) {
+ RTW_WARN(FUNC_ADPT_FMT" no available channel\n", FUNC_ADPT_ARG(adapter));
+ *chbw_allow = _FALSE;
+ goto exit;
+ }
+
+ } else
#endif /* defined(CONFIG_DFS_MASTER) */
+ {
+ ch_avail = rtw_choose_shortest_waiting_ch(adapter, req_ch, req_bw
+ , &dec_ch, &dec_bw, &dec_offset
+ , RTW_CHF_DFS, MLME_IS_ASOC(adapter) ? mlmeext->cur_channel : cur_ie_ch
+ , rfctl->ch_sel_same_band_prefer);
+ if (ch_avail == _FALSE) {
+ RTW_WARN(FUNC_ADPT_FMT" no available channel\n", FUNC_ADPT_ARG(adapter));
+ *chbw_allow = _FALSE;
+ goto exit;
+ }
+ }
update_bss_chbw:
- rtw_ap_update_bss_chbw(adapter, &(adapter->mlmepriv.cur_network.network)
- , dec_ch, dec_bw, dec_offset);
-
/* channel bw offset can be allowed for single AP, not need MCC */
*chbw_allow = _TRUE;
set_dec_ch = _TRUE;
@@ -4069,24 +4430,34 @@ bool rtw_ap_chbw_decision(_adapter *adapter, s16 req_ch, s8 req_bw, s8 req_offse
set_u_ch = set_dec_ch = _FALSE;
}
- if (mlmeext->cur_channel != dec_ch
- || mlmeext->cur_bwmode != dec_bw
- || mlmeext->cur_ch_offset != dec_offset)
+ /* ch setting differs from mlmeext.network IE */
+ if (cur_ie_ch != dec_ch
+ || cur_ie_bw != dec_bw
+ || cur_ie_offset != dec_offset)
changed = _TRUE;
- if (changed == _TRUE && rtw_linked_check(adapter) == _TRUE) {
-#ifdef CONFIG_SPCT_CH_SWITCH
- if (1)
- rtw_ap_inform_ch_switch(adapter, dec_ch, dec_offset);
- else
-#endif
- rtw_sta_flush(adapter, _FALSE);
+ /* ch setting differs from existing one */
+ if (check_fwstate(&adapter->mlmepriv, WIFI_ASOC_STATE)
+ && (mlmeext->cur_channel != dec_ch
+ || mlmeext->cur_bwmode != dec_bw
+ || mlmeext->cur_ch_offset != dec_offset)
+ ) {
+ if (rtw_linked_check(adapter) == _TRUE) {
+ #ifdef CONFIG_SPCT_CH_SWITCH
+ if (1)
+ rtw_ap_inform_ch_switch(adapter, dec_ch, dec_offset);
+ else
+ #endif
+ rtw_sta_flush(adapter, _FALSE);
+ }
}
mlmeext->cur_channel = dec_ch;
mlmeext->cur_bwmode = dec_bw;
mlmeext->cur_ch_offset = dec_offset;
+ rtw_ap_update_bss_chbw(adapter, network, dec_ch, dec_bw, dec_offset);
+
if (u_ch != 0)
RTW_INFO(FUNC_ADPT_FMT" union: %u,%u,%u\n", FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset);
@@ -4105,8 +4476,38 @@ bool rtw_ap_chbw_decision(_adapter *adapter, s16 req_ch, s8 req_bw, s8 req_offse
return changed;
}
-/*#define DBG_SWTIMER_BASED_TXBCN*/
+u8 rtw_ap_sta_linking_state_check(_adapter *adapter)
+{
+ struct sta_info *psta;
+ struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
+ struct sta_priv *pstapriv = &adapter->stapriv;
+ int i;
+ _list *plist, *phead;
+ _irqL irqL;
+ u8 rst = _FALSE;
+
+ if (!MLME_IS_AP(adapter) && !MLME_IS_MESH(adapter))
+ return _FALSE;
+
+ if (pstapriv->auth_list_cnt !=0)
+ return _TRUE;
+
+ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+ phead = &pstapriv->asoc_list;
+ plist = get_next(phead);
+ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+ psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
+ plist = get_next(plist);
+ if (!(psta->state &_FW_LINKED)) {
+ rst = _TRUE;
+ break;
+ }
+ }
+ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+ return rst;
+}
+/*#define DBG_SWTIMER_BASED_TXBCN*/
#ifdef CONFIG_SWTIMER_BASED_TXBCN
void tx_beacon_handlder(struct dvobj_priv *pdvobj)
{
@@ -4118,6 +4519,7 @@ void tx_beacon_handlder(struct dvobj_priv *pdvobj)
u64 time;
u32 cur_tick, time_offset; /* unit : usec */
u32 inter_bcn_space_us; /* unit : usec */
+ u32 txbcn_timer_ms; /* unit : ms */
int nr_vap, idx, bcn_idx;
int i;
u8 val8, late = 0;
@@ -4217,14 +4619,29 @@ void tx_beacon_handlder(struct dvobj_priv *pdvobj)
#ifdef DBG_SWTIMER_BASED_TXBCN
RTW_INFO("set sw bcn timer %d us\n", time_offset);
#endif
- _set_timer(&pdvobj->txbcn_timer, time_offset / NET80211_TU_TO_US);
+ txbcn_timer_ms = time_offset / NET80211_TU_TO_US;
+ _set_timer(&pdvobj->txbcn_timer, txbcn_timer_ms);
if (padapter) {
+#ifdef CONFIG_BCN_RECOVERY
+ rtw_ap_bcn_recovery(padapter);
+#endif /*CONFIG_BCN_RECOVERY*/
+
+#ifdef CONFIG_BCN_XMIT_PROTECT
+ rtw_ap_bcn_queue_empty_check(padapter, txbcn_timer_ms);
+#endif /*CONFIG_BCN_XMIT_PROTECT*/
+
#ifdef DBG_SWTIMER_BASED_TXBCN
RTW_INFO("padapter=%p, PORT=%d\n", padapter, padapter->hw_port);
#endif
- /*update_beacon(padapter, _TIM_IE_, NULL, _FALSE);*/
- issue_beacon(padapter, 0);
+ /* bypass TX BCN queue if op ch is switching/waiting */
+ if (!check_fwstate(&padapter->mlmepriv, WIFI_OP_CH_SWITCHING)
+ && !IS_CH_WAITING(adapter_to_rfctl(padapter))
+ ) {
+ /*update_beacon(padapter, _TIM_IE_, NULL, _FALSE);*/
+ /*issue_beacon(padapter, 0);*/
+ send_beacon(padapter);
+ }
}
#if 0
@@ -4239,8 +4656,9 @@ void tx_beacon_handlder(struct dvobj_priv *pdvobj)
}
-void tx_beacon_timer_handlder(struct dvobj_priv *pdvobj)
+void tx_beacon_timer_handlder(void *ctx)
{
+ struct dvobj_priv *pdvobj = (struct dvobj_priv *)ctx;
_adapter *padapter = pdvobj->padapters[0];
if (padapter)
@@ -4248,4 +4666,318 @@ void tx_beacon_timer_handlder(struct dvobj_priv *pdvobj)
}
#endif
+void rtw_ap_parse_sta_capability(_adapter *adapter, struct sta_info *sta, u8 *cap)
+{
+ sta->capability = RTW_GET_LE16(cap);
+ if (sta->capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
+ sta->flags |= WLAN_STA_SHORT_PREAMBLE;
+ else
+ sta->flags &= ~WLAN_STA_SHORT_PREAMBLE;
+}
+
+u16 rtw_ap_parse_sta_supported_rates(_adapter *adapter, struct sta_info *sta, u8 *tlv_ies, u16 tlv_ies_len)
+{
+ u8 rate_set[16];
+ u8 rate_num;
+ int i;
+ u16 status = _STATS_SUCCESSFUL_;
+
+ rtw_ies_get_supported_rate(tlv_ies, tlv_ies_len, rate_set, &rate_num);
+ if (rate_num == 0) {
+ RTW_INFO(FUNC_ADPT_FMT" sta "MAC_FMT" with no supported rate\n"
+ , FUNC_ADPT_ARG(adapter), MAC_ARG(sta->cmn.mac_addr));
+ status = _STATS_FAILURE_;
+ goto exit;
+ }
+
+ _rtw_memcpy(sta->bssrateset, rate_set, rate_num);
+ sta->bssratelen = rate_num;
+
+ if (MLME_IS_AP(adapter)) {
+ /* this function force only CCK rates to be bassic rate... */
+ UpdateBrateTblForSoftAP(sta->bssrateset, sta->bssratelen);
+ }
+
+ /* if (hapd->iface->current_mode->mode == HOSTAPD_MODE_IEEE80211G) */ /* ? */
+ sta->flags |= WLAN_STA_NONERP;
+ for (i = 0; i < sta->bssratelen; i++) {
+ if ((sta->bssrateset[i] & 0x7f) > 22) {
+ sta->flags &= ~WLAN_STA_NONERP;
+ break;
+ }
+ }
+
+exit:
+ return status;
+}
+
+u16 rtw_ap_parse_sta_security_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems)
+{
+ struct security_priv *sec = &adapter->securitypriv;
+ u8 *wpa_ie;
+ int wpa_ie_len;
+ int group_cipher = 0, pairwise_cipher = 0;
+ u8 mfp_opt = MFP_NO;
+ u16 status = _STATS_SUCCESSFUL_;
+
+ sta->dot8021xalg = 0;
+ sta->wpa_psk = 0;
+ sta->wpa_group_cipher = 0;
+ sta->wpa2_group_cipher = 0;
+ sta->wpa_pairwise_cipher = 0;
+ sta->wpa2_pairwise_cipher = 0;
+ _rtw_memset(sta->wpa_ie, 0, sizeof(sta->wpa_ie));
+
+ if ((sec->wpa_psk & BIT(1)) && elems->rsn_ie) {
+ wpa_ie = elems->rsn_ie;
+ wpa_ie_len = elems->rsn_ie_len;
+
+ if (rtw_parse_wpa2_ie(wpa_ie - 2, wpa_ie_len + 2, &group_cipher, &pairwise_cipher, NULL, &mfp_opt) == _SUCCESS) {
+ sta->dot8021xalg = 1;/* psk, todo:802.1x */
+ sta->wpa_psk |= BIT(1);
+
+ sta->wpa2_group_cipher = group_cipher & sec->wpa2_group_cipher;
+ sta->wpa2_pairwise_cipher = pairwise_cipher & sec->wpa2_pairwise_cipher;
+
+ if (!sta->wpa2_group_cipher)
+ status = WLAN_STATUS_GROUP_CIPHER_NOT_VALID;
+
+ if (!sta->wpa2_pairwise_cipher)
+ status = WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID;
+ } else
+ status = WLAN_STATUS_INVALID_IE;
+
+ }
+ else if ((sec->wpa_psk & BIT(0)) && elems->wpa_ie) {
+ wpa_ie = elems->wpa_ie;
+ wpa_ie_len = elems->wpa_ie_len;
+
+ if (rtw_parse_wpa_ie(wpa_ie - 2, wpa_ie_len + 2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) {
+ sta->dot8021xalg = 1;/* psk, todo:802.1x */
+ sta->wpa_psk |= BIT(0);
+
+ sta->wpa_group_cipher = group_cipher & sec->wpa_group_cipher;
+ sta->wpa_pairwise_cipher = pairwise_cipher & sec->wpa_pairwise_cipher;
+
+ if (!sta->wpa_group_cipher)
+ status = WLAN_STATUS_GROUP_CIPHER_NOT_VALID;
+
+ if (!sta->wpa_pairwise_cipher)
+ status = WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID;
+ } else
+ status = WLAN_STATUS_INVALID_IE;
+
+ } else {
+ wpa_ie = NULL;
+ wpa_ie_len = 0;
+ }
+
+#ifdef CONFIG_RTW_MESH
+ if (MLME_IS_MESH(adapter)) {
+ /* MFP is mandatory for secure mesh */
+ if (adapter->mesh_info.mesh_auth_id)
+ sta->flags |= WLAN_STA_MFP;
+ } else
+#endif
+ if ((sec->mfp_opt == MFP_REQUIRED && mfp_opt == MFP_NO) || mfp_opt == MFP_INVALID)
+ status = WLAN_STATUS_ROBUST_MGMT_FRAME_POLICY_VIOLATION;
+ else if (sec->mfp_opt >= MFP_OPTIONAL && mfp_opt >= MFP_OPTIONAL)
+ sta->flags |= WLAN_STA_MFP;
+
+ if (status != _STATS_SUCCESSFUL_)
+ goto exit;
+
+ if (!MLME_IS_AP(adapter))
+ goto exit;
+
+ sta->flags &= ~(WLAN_STA_WPS | WLAN_STA_MAYBE_WPS);
+ /* if (hapd->conf->wps_state && wpa_ie == NULL) { */ /* todo: to check ap if supporting WPS */
+ if (wpa_ie == NULL) {
+ if (elems->wps_ie) {
+ RTW_INFO("STA included WPS IE in "
+ "(Re)Association Request - assume WPS is "
+ "used\n");
+ sta->flags |= WLAN_STA_WPS;
+ /* wpabuf_free(sta->wps_ie); */
+ /* sta->wps_ie = wpabuf_alloc_copy(elems.wps_ie + 4, */
+ /* elems.wps_ie_len - 4); */
+ } else {
+ RTW_INFO("STA did not include WPA/RSN IE "
+ "in (Re)Association Request - possible WPS "
+ "use\n");
+ sta->flags |= WLAN_STA_MAYBE_WPS;
+ }
+
+ /* AP support WPA/RSN, and sta is going to do WPS, but AP is not ready */
+ /* that the selected registrar of AP is _FLASE */
+ if ((sec->wpa_psk > 0)
+ && (sta->flags & (WLAN_STA_WPS | WLAN_STA_MAYBE_WPS))
+ ) {
+ struct mlme_priv *mlme = &adapter->mlmepriv;
+
+ if (mlme->wps_beacon_ie) {
+ u8 selected_registrar = 0;
+
+ rtw_get_wps_attr_content(mlme->wps_beacon_ie, mlme->wps_beacon_ie_len, WPS_ATTR_SELECTED_REGISTRAR, &selected_registrar, NULL);
+
+ if (!selected_registrar) {
+ RTW_INFO("selected_registrar is _FALSE , or AP is not ready to do WPS\n");
+ status = _STATS_UNABLE_HANDLE_STA_;
+ goto exit;
+ }
+ }
+ }
+
+ } else {
+ int copy_len;
+
+ if (sec->wpa_psk == 0) {
+ RTW_INFO("STA " MAC_FMT
+ ": WPA/RSN IE in association request, but AP don't support WPA/RSN\n",
+ MAC_ARG(sta->cmn.mac_addr));
+ status = WLAN_STATUS_INVALID_IE;
+ goto exit;
+ }
+
+ if (elems->wps_ie) {
+ RTW_INFO("STA included WPS IE in "
+ "(Re)Association Request - WPS is "
+ "used\n");
+ sta->flags |= WLAN_STA_WPS;
+ copy_len = 0;
+ } else
+ copy_len = ((wpa_ie_len + 2) > sizeof(sta->wpa_ie)) ? (sizeof(sta->wpa_ie)) : (wpa_ie_len + 2);
+
+ if (copy_len > 0)
+ _rtw_memcpy(sta->wpa_ie, wpa_ie - 2, copy_len);
+ }
+
+exit:
+ return status;
+}
+
+void rtw_ap_parse_sta_wmm_ie(_adapter *adapter, struct sta_info *sta, u8 *tlv_ies, u16 tlv_ies_len)
+{
+ struct mlme_priv *mlme = &adapter->mlmepriv;
+ unsigned char WMM_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01};
+ u8 *p;
+
+ sta->flags &= ~WLAN_STA_WME;
+ sta->qos_option = 0;
+ sta->qos_info = 0;
+ sta->has_legacy_ac = _TRUE;
+ sta->uapsd_vo = 0;
+ sta->uapsd_vi = 0;
+ sta->uapsd_be = 0;
+ sta->uapsd_bk = 0;
+
+ if (!mlme->qospriv.qos_option)
+ goto exit;
+
+#ifdef CONFIG_RTW_MESH
+ if (MLME_IS_MESH(adapter)) {
+ /* QoS is mandatory in mesh */
+ sta->flags |= WLAN_STA_WME;
+ }
+#endif
+
+ p = rtw_get_ie_ex(tlv_ies, tlv_ies_len, WLAN_EID_VENDOR_SPECIFIC, WMM_IE, 6, NULL, NULL);
+ if (!p)
+ goto exit;
+
+ sta->flags |= WLAN_STA_WME;
+ sta->qos_option = 1;
+ sta->qos_info = *(p + 8);
+ sta->max_sp_len = (sta->qos_info >> 5) & 0x3;
+
+ if ((sta->qos_info & 0xf) != 0xf)
+ sta->has_legacy_ac = _TRUE;
+ else
+ sta->has_legacy_ac = _FALSE;
+
+ if (sta->qos_info & 0xf) {
+ if (sta->qos_info & BIT(0))
+ sta->uapsd_vo = BIT(0) | BIT(1);
+ else
+ sta->uapsd_vo = 0;
+
+ if (sta->qos_info & BIT(1))
+ sta->uapsd_vi = BIT(0) | BIT(1);
+ else
+ sta->uapsd_vi = 0;
+
+ if (sta->qos_info & BIT(2))
+ sta->uapsd_bk = BIT(0) | BIT(1);
+ else
+ sta->uapsd_bk = 0;
+
+ if (sta->qos_info & BIT(3))
+ sta->uapsd_be = BIT(0) | BIT(1);
+ else
+ sta->uapsd_be = 0;
+ }
+
+exit:
+ return;
+}
+
+void rtw_ap_parse_sta_ht_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems)
+{
+ struct mlme_priv *mlme = &adapter->mlmepriv;
+
+ sta->flags &= ~WLAN_STA_HT;
+
+#ifdef CONFIG_80211N_HT
+ if (mlme->htpriv.ht_option == _FALSE)
+ goto exit;
+
+ /* save HT capabilities in the sta object */
+ _rtw_memset(&sta->htpriv.ht_cap, 0, sizeof(struct rtw_ieee80211_ht_cap));
+ if (elems->ht_capabilities && elems->ht_capabilities_len >= sizeof(struct rtw_ieee80211_ht_cap)) {
+ sta->flags |= WLAN_STA_HT;
+ sta->flags |= WLAN_STA_WME;
+ _rtw_memcpy(&sta->htpriv.ht_cap, elems->ht_capabilities, sizeof(struct rtw_ieee80211_ht_cap));
+
+ if (elems->ht_operation && elems->ht_operation_len == HT_OP_IE_LEN) {
+ _rtw_memcpy(sta->htpriv.ht_op, elems->ht_operation, HT_OP_IE_LEN);
+ sta->htpriv.op_present = 1;
+ }
+ }
+exit:
+#endif
+
+ return;
+}
+
+void rtw_ap_parse_sta_vht_ie(_adapter *adapter, struct sta_info *sta, struct rtw_ieee802_11_elems *elems)
+{
+ struct mlme_priv *mlme = &adapter->mlmepriv;
+
+ sta->flags &= ~WLAN_STA_VHT;
+
+#ifdef CONFIG_80211AC_VHT
+ if (mlme->vhtpriv.vht_option == _FALSE)
+ goto exit;
+
+ _rtw_memset(&sta->vhtpriv, 0, sizeof(struct vht_priv));
+ if (elems->vht_capabilities && elems->vht_capabilities_len == VHT_CAP_IE_LEN) {
+ sta->flags |= WLAN_STA_VHT;
+ _rtw_memcpy(sta->vhtpriv.vht_cap, elems->vht_capabilities, VHT_CAP_IE_LEN);
+
+ if (elems->vht_operation && elems->vht_operation_len== VHT_OP_IE_LEN) {
+ _rtw_memcpy(sta->vhtpriv.vht_op, elems->vht_operation, VHT_OP_IE_LEN);
+ sta->vhtpriv.op_present = 1;
+ }
+
+ if (elems->vht_op_mode_notify && elems->vht_op_mode_notify_len == 1) {
+ _rtw_memcpy(&sta->vhtpriv.vht_op_mode_notify, elems->vht_op_mode_notify, 1);
+ sta->vhtpriv.notify_present = 1;
+ }
+ }
+exit:
+#endif
+
+ return;
+}
#endif /* CONFIG_AP_MODE */
+
diff --git a/core/rtw_beamforming.c b/core/rtw_beamforming.c
index 4a55842..78a3986 100644
--- a/core/rtw_beamforming.c
+++ b/core/rtw_beamforming.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2016 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,12 +11,7 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#define _RTW_BEAMFORMING_C_
#include
@@ -24,110 +19,1132 @@
#ifdef CONFIG_BEAMFORMING
-#if (BEAMFORMING_SUPPORT == 0) /*for diver defined beamforming*/
#ifdef RTW_BEAMFORMING_VERSION_2
+
+struct ndpa_sta_info {
+ u16 aid:12;
+ u16 feedback_type:1;
+ u16 nc_index:3;
+};
+
+static void _get_txvector_parameter(PADAPTER adapter, struct sta_info *sta, u8 *g_id, u16 *p_aid)
+{
+ struct mlme_priv *mlme;
+ u16 aid;
+ u8 *bssid;
+ u16 val16;
+ u8 i;
+
+
+ mlme = &adapter->mlmepriv;
+
+ if (check_fwstate(mlme, WIFI_AP_STATE)) {
+ /*
+ * Sent by an AP and addressed to a STA associated with that AP
+ * or sent by a DLS or TDLS STA in a direct path to
+ * a DLS or TDLS peer STA
+ */
+
+ aid = sta->cmn.aid;
+ bssid = adapter_mac_addr(adapter);
+ RTW_INFO("%s: AID=0x%x BSSID=" MAC_FMT "\n",
+ __FUNCTION__, sta->cmn.aid, MAC_ARG(bssid));
+
+ /* AID[0:8] */
+ aid &= 0x1FF;
+ /* BSSID[44:47] xor BSSID[40:43] */
+ val16 = ((bssid[5] & 0xF0) >> 4) ^ (bssid[5] & 0xF);
+ /* (dec(AID[0:8]) + dec(BSSID)*2^5) mod 2^9 */
+ *p_aid = (aid + (val16 << 5)) & 0x1FF;
+ *g_id = 63;
+ } else if ((check_fwstate(mlme, WIFI_ADHOC_STATE) == _TRUE)
+ || (check_fwstate(mlme, WIFI_ADHOC_MASTER_STATE) == _TRUE)) {
+ /*
+ * Otherwise, includes
+ * 1. Sent to an IBSS STA
+ * 2. Sent by an AP to a non associated STA
+ * 3. Sent to a STA for which it is not known
+ * which condition is applicable
+ */
+ *p_aid = 0;
+ *g_id = 63;
+ } else {
+ /* Addressed to AP */
+ bssid = sta->cmn.mac_addr;
+ RTW_INFO("%s: BSSID=" MAC_FMT "\n", __FUNCTION__, MAC_ARG(bssid));
+
+ /* BSSID[39:47] */
+ *p_aid = (bssid[5] << 1) | (bssid[4] >> 7);
+ *g_id = 0;
+ }
+
+ RTW_INFO("%s: GROUP_ID=0x%02x PARTIAL_AID=0x%04x\n",
+ __FUNCTION__, *g_id, *p_aid);
+}
+
+/*
+ * Parameters
+ * adapter struct _adapter*
+ * sta struct sta_info*
+ * sta_bf_cap beamforming capabe of sta
+ * sounding_dim Number of Sounding Dimensions
+ * comp_steering Compressed Steering Number of Beamformer Antennas Supported
+ */
+static void _get_sta_beamform_cap(PADAPTER adapter, struct sta_info *sta,
+ u8 *sta_bf_cap, u8 *sounding_dim, u8 *comp_steering)
+{
+ struct beamforming_info *info;
+ struct ht_priv *ht;
+#ifdef CONFIG_80211AC_VHT
+ struct vht_priv *vht;
+#endif /* CONFIG_80211AC_VHT */
+ u16 bf_cap;
+
+
+ *sta_bf_cap = 0;
+ *sounding_dim = 0;
+ *comp_steering = 0;
+
+ info = GET_BEAMFORM_INFO(adapter);
+ ht = &adapter->mlmepriv.htpriv;
+#ifdef CONFIG_80211AC_VHT
+ vht = &adapter->mlmepriv.vhtpriv;
+#endif /* CONFIG_80211AC_VHT */
+
+ if (is_supported_ht(sta->wireless_mode) == _TRUE) {
+ /* HT */
+ bf_cap = ht->beamform_cap;
+
+ if (TEST_FLAG(bf_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) {
+ info->beamforming_cap |= BEAMFORMEE_CAP_HT_EXPLICIT;
+ *sta_bf_cap |= BEAMFORMER_CAP_HT_EXPLICIT;
+ *sounding_dim = (bf_cap & BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP) >> 6;
+ }
+ if (TEST_FLAG(bf_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) {
+ info->beamforming_cap |= BEAMFORMER_CAP_HT_EXPLICIT;
+ *sta_bf_cap |= BEAMFORMEE_CAP_HT_EXPLICIT;
+ *comp_steering = (bf_cap & BEAMFORMING_HT_BEAMFORMER_STEER_NUM) >> 4;
+ }
+ }
+
+#ifdef CONFIG_80211AC_VHT
+ if (is_supported_vht(sta->wireless_mode) == _TRUE) {
+ /* VHT */
+ bf_cap = vht->beamform_cap;
+
+ /* We are SU Beamformee because the STA is SU Beamformer */
+ if (TEST_FLAG(bf_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) {
+ info->beamforming_cap |= BEAMFORMEE_CAP_VHT_SU;
+ *sta_bf_cap |= BEAMFORMER_CAP_VHT_SU;
+
+ /* We are MU Beamformee because the STA is MU Beamformer */
+ if (TEST_FLAG(bf_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)) {
+ info->beamforming_cap |= BEAMFORMEE_CAP_VHT_MU;
+ *sta_bf_cap |= BEAMFORMER_CAP_VHT_MU;
+ }
+
+ *sounding_dim = (bf_cap & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM) >> 12;
+ }
+ /* We are SU Beamformer because the STA is SU Beamformee */
+ if (TEST_FLAG(bf_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) {
+ info->beamforming_cap |= BEAMFORMER_CAP_VHT_SU;
+ *sta_bf_cap |= BEAMFORMEE_CAP_VHT_SU;
+
+ /* We are MU Beamformer because the STA is MU Beamformee */
+ if (TEST_FLAG(bf_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) {
+ info->beamforming_cap |= BEAMFORMER_CAP_VHT_MU;
+ *sta_bf_cap |= BEAMFORMEE_CAP_VHT_MU;
+ }
+
+ *comp_steering = (bf_cap & BEAMFORMING_VHT_BEAMFORMER_STS_CAP) >> 8;
+ }
+ }
+#endif /* CONFIG_80211AC_VHT */
+}
+
+static u8 _send_ht_ndpa_packet(PADAPTER adapter, u8 *ra, enum channel_width bw)
+{
+ /* General */
+ struct xmit_priv *pxmitpriv;
+ struct mlme_ext_priv *pmlmeext;
+ struct mlme_ext_info *pmlmeinfo;
+ struct xmit_frame *pmgntframe;
+ /* Beamforming */
+ struct beamforming_info *info;
+ struct beamformee_entry *bfee;
+ struct ndpa_sta_info sta_info;
+ u8 ActionHdr[4] = {ACT_CAT_VENDOR, 0x00, 0xE0, 0x4C};
+ /* MISC */
+ struct pkt_attrib *attrib;
+ struct rtw_ieee80211_hdr *pwlanhdr;
+ enum MGN_RATE txrate;
+ u8 *pframe;
+ u16 duration = 0;
+ u8 aSifsTime = 0;
+
+
+ RTW_INFO("+%s: Send to " MAC_FMT "\n", __FUNCTION__, MAC_ARG(ra));
+
+ pxmitpriv = &adapter->xmitpriv;
+ pmlmeext = &adapter->mlmeextpriv;
+ pmlmeinfo = &pmlmeext->mlmext_info;
+ bfee = rtw_bf_bfee_get_entry_by_addr(adapter, ra);
+ if (!bfee) {
+ RTW_ERR("%s: Cann't find beamformee entry!\n", __FUNCTION__);
+ return _FALSE;
+ }
+
+ pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+ if (!pmgntframe) {
+ RTW_ERR("%s: alloc mgnt frame fail!\n", __FUNCTION__);
+ return _FALSE;
+ }
+
+ txrate = beamforming_get_htndp_tx_rate(GET_PDM_ODM(adapter), bfee->comp_steering_num_of_bfer);
+
+ /* update attribute */
+ attrib = &pmgntframe->attrib;
+ update_mgntframe_attrib(adapter, attrib);
+ /*attrib->type = WIFI_MGT_TYPE;*/ /* set in update_mgntframe_attrib() */
+ attrib->subtype = WIFI_ACTION_NOACK;
+ attrib->bwmode = bw;
+ /*attrib->qsel = QSLT_MGNT;*/ /* set in update_mgntframe_attrib() */
+ attrib->order = 1;
+ attrib->rate = (u8)txrate;
+ attrib->bf_pkt_type = 0;
+
+ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+ /* Frame control */
+ pwlanhdr->frame_ctl = 0;
+ set_frame_sub_type(pframe, attrib->subtype);
+ set_order_bit(pframe);
+
+ /* Duration */
+ if (pmlmeext->cur_wireless_mode == WIRELESS_11B)
+ aSifsTime = 10;
+ else
+ aSifsTime = 16;
+ duration = 2 * aSifsTime + 40;
+ if (bw == CHANNEL_WIDTH_40)
+ duration += 87;
+ else
+ duration += 180;
+ set_duration(pframe, duration);
+
+ /* DA */
+ _rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN);
+ /* SA */
+ _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN);
+ /* BSSID */
+ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
+
+ /* HT control field */
+ SET_HT_CTRL_CSI_STEERING(pframe + 24, 3);
+ SET_HT_CTRL_NDP_ANNOUNCEMENT(pframe + 24, 1);
+
+ /*
+ * Frame Body
+ * Category field: vender-specific value, 0x7F
+ * OUI: 0x00E04C
+ */
+ _rtw_memcpy(pframe + 28, ActionHdr, 4);
+
+ attrib->pktlen = 32;
+ attrib->last_txcmdsz = attrib->pktlen;
+
+ dump_mgntframe(adapter, pmgntframe);
+
+ return _TRUE;
+}
+
+static u8 _send_vht_ndpa_packet(PADAPTER adapter, u8 *ra, u16 aid, enum channel_width bw)
+{
+ /* General */
+ struct xmit_priv *pxmitpriv;
+ struct mlme_ext_priv *pmlmeext;
+ struct xmit_frame *pmgntframe;
+ /* Beamforming */
+ struct beamforming_info *info;
+ struct beamformee_entry *bfee;
+ struct ndpa_sta_info sta_info;
+ /* MISC */
+ struct pkt_attrib *attrib;
+ struct rtw_ieee80211_hdr *pwlanhdr;
+ u8 *pframe;
+ enum MGN_RATE txrate;
+ u16 duration = 0;
+ u8 sequence = 0, aSifsTime = 0;
+
+
+ RTW_INFO("+%s: Send to " MAC_FMT "\n", __FUNCTION__, MAC_ARG(ra));
+
+ pxmitpriv = &adapter->xmitpriv;
+ pmlmeext = &adapter->mlmeextpriv;
+ info = GET_BEAMFORM_INFO(adapter);
+ bfee = rtw_bf_bfee_get_entry_by_addr(adapter, ra);
+ if (!bfee) {
+ RTW_ERR("%s: Cann't find beamformee entry!\n", __FUNCTION__);
+ return _FALSE;
+ }
+
+ pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+ if (!pmgntframe) {
+ RTW_ERR("%s: alloc mgnt frame fail!\n", __FUNCTION__);
+ return _FALSE;
+ }
+
+ txrate = beamforming_get_vht_ndp_tx_rate(GET_PDM_ODM(adapter), bfee->comp_steering_num_of_bfer);
+
+ /* update attribute */
+ attrib = &pmgntframe->attrib;
+ update_mgntframe_attrib(adapter, attrib);
+ /*pattrib->type = WIFI_MGT_TYPE;*/ /* set in update_mgntframe_attrib() */
+ attrib->subtype = WIFI_NDPA;
+ attrib->bwmode = bw;
+ /*attrib->qsel = QSLT_MGNT;*/ /* set in update_mgntframe_attrib() */
+ attrib->rate = (u8)txrate;
+ attrib->bf_pkt_type = 0;
+
+ _rtw_memset(pmgntframe->buf_addr, 0, TXDESC_OFFSET + WLANHDR_OFFSET);
+ pframe = pmgntframe->buf_addr + TXDESC_OFFSET;
+ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+ /* Frame control */
+ pwlanhdr->frame_ctl = 0;
+ set_frame_sub_type(pframe, attrib->subtype);
+
+ /* Duration */
+ if (is_supported_5g(pmlmeext->cur_wireless_mode) || is_supported_ht(pmlmeext->cur_wireless_mode))
+ aSifsTime = 16;
+ else
+ aSifsTime = 10;
+ duration = 2 * aSifsTime + 44;
+ if (bw == CHANNEL_WIDTH_80)
+ duration += 40;
+ else if (bw == CHANNEL_WIDTH_40)
+ duration += 87;
+ else
+ duration += 180;
+ set_duration(pframe, duration);
+
+ /* RA */
+ _rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN);
+
+ /* TA */
+ _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN);
+
+ /* Sounding Sequence, bit0~1 is reserved */
+ sequence = info->sounding_sequence << 2;
+ if (info->sounding_sequence >= 0x3f)
+ info->sounding_sequence = 0;
+ else
+ info->sounding_sequence++;
+ _rtw_memcpy(pframe + 16, &sequence, 1);
+
+ /* STA Info */
+ /*
+ * "AID12" Equal to 0 if the STA is an AP, mesh STA or
+ * STA that is a member of an IBSS
+ */
+ if (check_fwstate(&adapter->mlmepriv, WIFI_AP_STATE) == _FALSE)
+ aid = 0;
+ sta_info.aid = aid;
+ /* "Feedback Type" set to 0 for SU */
+ sta_info.feedback_type = 0;
+ /* "Nc Index" reserved if the Feedback Type field indicates SU */
+ sta_info.nc_index = 0;
+ _rtw_memcpy(pframe + 17, (u8 *)&sta_info, 2);
+
+ attrib->pktlen = 19;
+ attrib->last_txcmdsz = attrib->pktlen;
+
+ dump_mgntframe(adapter, pmgntframe);
+
+ return _TRUE;
+}
+
+static u8 _send_vht_mu_ndpa_packet(PADAPTER adapter, enum channel_width bw)
+{
+ /* General */
+ struct xmit_priv *pxmitpriv;
+ struct mlme_ext_priv *pmlmeext;
+ struct xmit_frame *pmgntframe;
+ /* Beamforming */
+ struct beamforming_info *info;
+ struct sounding_info *sounding;
+ struct beamformee_entry *bfee;
+ struct ndpa_sta_info sta_info;
+ /* MISC */
+ struct pkt_attrib *attrib;
+ struct rtw_ieee80211_hdr *pwlanhdr;
+ enum MGN_RATE txrate;
+ u8 *pframe;
+ u8 *ra = NULL;
+ u16 duration = 0;
+ u8 sequence = 0, aSifsTime = 0;
+ u8 i;
+
+
+ RTW_INFO("+%s\n", __FUNCTION__);
+
+ pxmitpriv = &adapter->xmitpriv;
+ pmlmeext = &adapter->mlmeextpriv;
+ info = GET_BEAMFORM_INFO(adapter);
+ sounding = &info->sounding_info;
+
+ txrate = MGN_VHT2SS_MCS0;
+
+ /*
+ * Fill the first MU BFee entry (STA1) MAC addr to destination address then
+ * HW will change A1 to broadcast addr.
+ * 2015.05.28. Suggested by SD1 Chunchu.
+ */
+ bfee = &info->bfee_entry[sounding->mu_sounding_list[0]];
+ ra = bfee->mac_addr;
+
+ pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+ if (!pmgntframe) {
+ RTW_ERR("%s: alloc mgnt frame fail!\n", __FUNCTION__);
+ return _FALSE;
+ }
+
+ /* update attribute */
+ attrib = &pmgntframe->attrib;
+ update_mgntframe_attrib(adapter, attrib);
+ /*attrib->type = WIFI_MGT_TYPE;*/ /* set in update_mgntframe_attrib() */
+ attrib->subtype = WIFI_NDPA;
+ attrib->bwmode = bw;
+ /*attrib->qsel = QSLT_MGNT;*/ /* set in update_mgntframe_attrib() */
+ attrib->rate = (u8)txrate;
+ /* Set TxBFPktType of Tx desc to unicast type if there is only one MU STA for HW design */
+ if (info->sounding_info.candidate_mu_bfee_cnt > 1)
+ attrib->bf_pkt_type = 1;
+ else
+ attrib->bf_pkt_type = 0;
+
+ _rtw_memset(pmgntframe->buf_addr, 0, TXDESC_OFFSET + WLANHDR_OFFSET);
+ pframe = pmgntframe->buf_addr + TXDESC_OFFSET;
+ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+ /* Frame control */
+ pwlanhdr->frame_ctl = 0;
+ set_frame_sub_type(pframe, attrib->subtype);
+
+ /* Duration */
+ if (is_supported_5g(pmlmeext->cur_wireless_mode) || is_supported_ht(pmlmeext->cur_wireless_mode))
+ aSifsTime = 16;
+ else
+ aSifsTime = 10;
+ duration = 2 * aSifsTime + 44;
+ if (bw == CHANNEL_WIDTH_80)
+ duration += 40;
+ else if (bw == CHANNEL_WIDTH_40)
+ duration += 87;
+ else
+ duration += 180;
+ set_duration(pframe, duration);
+
+ /* RA */
+ _rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN);
+
+ /* TA */
+ _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN);
+
+ /* Sounding Sequence, bit0~1 is reserved */
+ sequence = info->sounding_sequence << 2;
+ if (info->sounding_sequence >= 0x3f)
+ info->sounding_sequence = 0;
+ else
+ info->sounding_sequence++;
+ _rtw_memcpy(pframe + 16, &sequence, 1);
+
+ attrib->pktlen = 17;
+
+ /*
+ * Construct STA info. for multiple STAs
+ * STA Info1, ..., STA Info n
+ */
+ for (i = 0; i < sounding->candidate_mu_bfee_cnt; i++) {
+ bfee = &info->bfee_entry[sounding->mu_sounding_list[i]];
+ sta_info.aid = bfee->aid;
+ sta_info.feedback_type = 1; /* 1'b1: MU */
+ sta_info.nc_index = 0;
+ _rtw_memcpy(pframe + attrib->pktlen, (u8 *)&sta_info, 2);
+ attrib->pktlen += 2;
+ }
+
+ attrib->last_txcmdsz = attrib->pktlen;
+
+ dump_mgntframe(adapter, pmgntframe);
+
+ return _TRUE;
+}
+
+static u8 _send_bf_report_poll(PADAPTER adapter, u8 *ra, u8 bFinalPoll)
+{
+ /* General */
+ struct xmit_priv *pxmitpriv;
+ struct xmit_frame *pmgntframe;
+ /* MISC */
+ struct pkt_attrib *attrib;
+ struct rtw_ieee80211_hdr *pwlanhdr;
+ u8 *pframe;
+
+
+ RTW_INFO("+%s: Send to " MAC_FMT "\n", __FUNCTION__, MAC_ARG(ra));
+
+ pxmitpriv = &adapter->xmitpriv;
+
+ pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+ if (!pmgntframe) {
+ RTW_ERR("%s: alloc mgnt frame fail!\n", __FUNCTION__);
+ return _FALSE;
+ }
+
+ /* update attribute */
+ attrib = &pmgntframe->attrib;
+ update_mgntframe_attrib(adapter, attrib);
+ /*attrib->type = WIFI_MGT_TYPE;*/ /* set in update_mgntframe_attrib() */
+ attrib->subtype = WIFI_BF_REPORT_POLL;
+ attrib->bwmode = CHANNEL_WIDTH_20;
+ /*attrib->qsel = QSLT_MGNT;*/ /* set in update_mgntframe_attrib() */
+ attrib->rate = MGN_6M;
+ if (bFinalPoll)
+ attrib->bf_pkt_type = 3;
+ else
+ attrib->bf_pkt_type = 2;
+
+ _rtw_memset(pmgntframe->buf_addr, 0, TXDESC_OFFSET + WLANHDR_OFFSET);
+ pframe = pmgntframe->buf_addr + TXDESC_OFFSET;
+ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+ /* Frame control */
+ pwlanhdr->frame_ctl = 0;
+ set_frame_sub_type(pframe, attrib->subtype);
+
+ /* Duration */
+ set_duration(pframe, 100);
+
+ /* RA */
+ _rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN);
+
+ /* TA */
+ _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN);
+
+ /* Feedback Segment Retransmission Bitmap */
+ pframe[16] = 0xFF;
+
+ attrib->pktlen = 17;
+ attrib->last_txcmdsz = attrib->pktlen;
+
+ dump_mgntframe(adapter, pmgntframe);
+
+ return _TRUE;
+}
+
+static void _sounding_update_min_period(PADAPTER adapter, u16 period, u8 leave)
+{
+ struct beamforming_info *info;
+ struct beamformee_entry *bfee;
+ u8 i = 0;
+ u16 min_val = 0xFFFF;
+
+
+ info = GET_BEAMFORM_INFO(adapter);
+
+ if (_TRUE == leave) {
+ /*
+ * When a BFee left,
+ * we need to find the latest min sounding period
+ * from the remaining BFees
+ */
+ for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {
+ bfee = &info->bfee_entry[i];
+ if ((bfee->used == _TRUE)
+ && (bfee->sound_period < min_val))
+ min_val = bfee->sound_period;
+ }
+
+ if (min_val == 0xFFFF)
+ info->sounding_info.min_sounding_period = 0;
+ else
+ info->sounding_info.min_sounding_period = min_val;
+ } else {
+ if ((info->sounding_info.min_sounding_period == 0)
+ || (period < info->sounding_info.min_sounding_period))
+ info->sounding_info.min_sounding_period = period;
+ }
+}
+
+static void _sounding_init(struct sounding_info *sounding)
+{
+ _rtw_memset(sounding->su_sounding_list, 0xFF, MAX_NUM_BEAMFORMEE_SU);
+ _rtw_memset(sounding->mu_sounding_list, 0xFF, MAX_NUM_BEAMFORMEE_MU);
+ sounding->state = SOUNDING_STATE_NONE;
+ sounding->su_bfee_curidx = 0xFF;
+ sounding->candidate_mu_bfee_cnt = 0;
+ sounding->min_sounding_period = 0;
+ sounding->sound_remain_cnt_per_period = 0;
+}
+
+static void _sounding_reset_vars(PADAPTER adapter)
+{
+ struct beamforming_info *info;
+ struct sounding_info *sounding;
+ u8 idx;
+
+
+ info = GET_BEAMFORM_INFO(adapter);
+ sounding = &info->sounding_info;
+
+ _rtw_memset(sounding->su_sounding_list, 0xFF, MAX_NUM_BEAMFORMEE_SU);
+ _rtw_memset(sounding->mu_sounding_list, 0xFF, MAX_NUM_BEAMFORMEE_MU);
+ sounding->su_bfee_curidx = 0xFF;
+ sounding->candidate_mu_bfee_cnt = 0;
+
+ /* Clear bSound flag for the new period */
+ for (idx = 0; idx < MAX_BEAMFORMEE_ENTRY_NUM; idx++) {
+ if ((info->bfee_entry[idx].used == _TRUE)
+ && (info->bfee_entry[idx].sounding == _TRUE)) {
+ info->bfee_entry[idx].sounding = _FALSE;
+ info->bfee_entry[idx].bCandidateSoundingPeer = _FALSE;
+ }
+ }
+}
+
/*
- * For phydm
+ * Return
+ * 0 Prepare sounding list OK
+ * -1 Fail to prepare sounding list, because no beamformee need to souding
+ * -2 Fail to prepare sounding list, because beamformee state not ready
+ *
*/
-BEAMFORMING_CAP beamforming_get_entry_beam_cap_by_mac_id(void *mlme, u8 mac_id)
+static int _sounding_get_list(PADAPTER adapter)
+{
+ struct beamforming_info *info;
+ struct sounding_info *sounding;
+ struct beamformee_entry *bfee;
+ u8 i, mu_idx = 0, su_idx = 0, not_ready = 0;
+ int ret = 0;
+
+
+ info = GET_BEAMFORM_INFO(adapter);
+ sounding = &info->sounding_info;
+
+ /* Add MU BFee list first because MU priority is higher than SU */
+ for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {
+ bfee = &info->bfee_entry[i];
+ if (bfee->used == _FALSE)
+ continue;
+
+ if (bfee->state != BEAMFORM_ENTRY_HW_STATE_ADDED) {
+ RTW_ERR("%s: Invalid BFee idx(%d) Hw state=%d\n", __FUNCTION__, i, bfee->state);
+ not_ready++;
+ continue;
+ }
+
+ /*
+ * Decrease BFee's SoundCnt per period
+ * If the remain count is 0,
+ * then it can be sounded at this time
+ */
+ if (bfee->SoundCnt) {
+ bfee->SoundCnt--;
+ if (bfee->SoundCnt)
+ continue;
+ }
+
+ /*
+ *
+ * If the STA supports MU BFee capability then we add it to MUSoundingList directly
+ * because we can only sound one STA by unicast NDPA with MU cap enabled to get correct channel info.
+ * Suggested by BB team Luke Lee. 2015.11.25.
+ */
+ if (bfee->cap & BEAMFORMEE_CAP_VHT_MU) {
+ /* MU BFee */
+ if (mu_idx >= MAX_NUM_BEAMFORMEE_MU) {
+ RTW_ERR("%s: Too much MU bfee entry(Limit:%d)\n", __FUNCTION__, MAX_NUM_BEAMFORMEE_MU);
+ continue;
+ }
+
+ if (bfee->bApplySounding == _TRUE) {
+ bfee->bCandidateSoundingPeer = _TRUE;
+ bfee->SoundCnt = GetInitSoundCnt(bfee->sound_period, sounding->min_sounding_period);
+ sounding->mu_sounding_list[mu_idx] = i;
+ mu_idx++;
+ }
+ } else if (bfee->cap & (BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT)) {
+ /* SU BFee (HT/VHT) */
+ if (su_idx >= MAX_NUM_BEAMFORMEE_SU) {
+ RTW_ERR("%s: Too much SU bfee entry(Limit:%d)\n", __FUNCTION__, MAX_NUM_BEAMFORMEE_SU);
+ continue;
+ }
+
+ if (bfee->bDeleteSounding == _TRUE) {
+ sounding->su_sounding_list[su_idx] = i;
+ su_idx++;
+ } else if ((bfee->bApplySounding == _TRUE)
+ && (bfee->bSuspendSUCap == _FALSE)) {
+ bfee->bCandidateSoundingPeer = _TRUE;
+ bfee->SoundCnt = GetInitSoundCnt(bfee->sound_period, sounding->min_sounding_period);
+ sounding->su_sounding_list[su_idx] = i;
+ su_idx++;
+ }
+ }
+ }
+
+ sounding->candidate_mu_bfee_cnt = mu_idx;
+
+ if (su_idx + mu_idx == 0) {
+ ret = -1;
+ if (not_ready)
+ ret = -2;
+ }
+
+ RTW_INFO("-%s: There are %d SU and %d MU BFees in this sounding period\n", __FUNCTION__, su_idx, mu_idx);
+
+ return ret;
+}
+
+static void _sounding_handler(PADAPTER adapter)
+{
+ struct beamforming_info *info;
+ struct sounding_info *sounding;
+ struct beamformee_entry *bfee;
+ u8 su_idx, i;
+ u32 timeout_period = 0;
+ u8 set_timer = _FALSE;
+ int ret = 0;
+ static u16 wait_cnt = 0;
+
+
+ info = GET_BEAMFORM_INFO(adapter);
+ sounding = &info->sounding_info;
+
+ RTW_DBG("+%s: state=%d\n", __FUNCTION__, sounding->state);
+ if ((sounding->state != SOUNDING_STATE_INIT)
+ && (sounding->state != SOUNDING_STATE_SU_SOUNDDOWN)
+ && (sounding->state != SOUNDING_STATE_MU_SOUNDDOWN)
+ && (sounding->state != SOUNDING_STATE_SOUNDING_TIMEOUT)) {
+ RTW_WARN("%s: Invalid State(%d) and return!\n", __FUNCTION__, sounding->state);
+ return;
+ }
+
+ if (sounding->state == SOUNDING_STATE_INIT) {
+ RTW_INFO("%s: Sounding start\n", __FUNCTION__);
+
+ /* Init Var */
+ _sounding_reset_vars(adapter);
+
+ /* Get the sounding list of this sounding period */
+ ret = _sounding_get_list(adapter);
+ if (ret == -1) {
+ wait_cnt = 0;
+ sounding->state = SOUNDING_STATE_NONE;
+ RTW_ERR("%s: No BFees found, set to SOUNDING_STATE_NONE\n", __FUNCTION__);
+ info->sounding_running--;
+ return;
+ }
+ if (ret == -2) {
+ RTW_WARN("%s: Temporarily cann't find BFee to sounding\n", __FUNCTION__);
+ if (wait_cnt < 5) {
+ wait_cnt++;
+ } else {
+ wait_cnt = 0;
+ sounding->state = SOUNDING_STATE_NONE;
+ RTW_ERR("%s: Wait changing state timeout!! Set to SOUNDING_STATE_NONE\n", __FUNCTION__);
+ }
+ info->sounding_running--;
+ return;
+ }
+ if (ret != 0) {
+ wait_cnt = 0;
+ RTW_ERR("%s: Unkown state(%d)!\n", __FUNCTION__, ret);
+ info->sounding_running--;
+ return;
+
+ }
+
+ wait_cnt = 0;
+
+ if (check_fwstate(&adapter->mlmepriv, WIFI_SITE_MONITOR) == _TRUE) {
+ RTW_INFO("%s: Sounding abort! scanning APs...\n", __FUNCTION__);
+ info->sounding_running--;
+ return;
+ }
+
+ rtw_ps_deny(adapter, PS_DENY_BEAMFORMING);
+ LeaveAllPowerSaveModeDirect(adapter);
+ }
+
+ /* Get non-sound SU BFee index */
+ for (i = 0; i < MAX_NUM_BEAMFORMEE_SU; i++) {
+ su_idx = sounding->su_sounding_list[i];
+ if (su_idx >= MAX_BEAMFORMEE_ENTRY_NUM)
+ continue;
+ bfee = &info->bfee_entry[su_idx];
+ if (_FALSE == bfee->sounding)
+ break;
+ }
+ if (i < MAX_NUM_BEAMFORMEE_SU) {
+ sounding->su_bfee_curidx = su_idx;
+ /* Set to sounding start state */
+ sounding->state = SOUNDING_STATE_SU_START;
+ RTW_DBG("%s: Set to SOUNDING_STATE_SU_START\n", __FUNCTION__);
+
+ bfee->sounding = _TRUE;
+ /* Reset sounding timeout flag for the new sounding */
+ bfee->bSoundingTimeout = _FALSE;
+
+ if (_TRUE == bfee->bDeleteSounding) {
+ u8 res = _FALSE;
+ rtw_bf_cmd(adapter, BEAMFORMING_CTRL_END_PERIOD, &res, 1, 0);
+ return;
+ }
+
+ /* Start SU sounding */
+ if (bfee->cap & BEAMFORMEE_CAP_VHT_SU)
+ _send_vht_ndpa_packet(adapter, bfee->mac_addr, bfee->aid, bfee->sound_bw);
+ else if (bfee->cap & BEAMFORMEE_CAP_HT_EXPLICIT)
+ _send_ht_ndpa_packet(adapter, bfee->mac_addr, bfee->sound_bw);
+
+ /* Set sounding timeout timer */
+ _set_timer(&info->sounding_timeout_timer, SU_SOUNDING_TIMEOUT);
+ return;
+ }
+
+ if (sounding->candidate_mu_bfee_cnt > 0) {
+ /*
+ * If there is no SU BFee then find MU BFee and perform MU sounding
+ *
+ * Need to check the MU starting condition. 2015.12.15.
+ */
+ sounding->state = SOUNDING_STATE_MU_START;
+ RTW_DBG("%s: Set to SOUNDING_STATE_MU_START\n", __FUNCTION__);
+
+ /* Update MU BFee info */
+ for (i = 0; i < sounding->candidate_mu_bfee_cnt; i++) {
+ bfee = &info->bfee_entry[sounding->mu_sounding_list[i]];
+ bfee->sounding = _TRUE;
+ }
+
+ /* Send MU NDPA */
+ bfee = &info->bfee_entry[sounding->mu_sounding_list[0]];
+ _send_vht_mu_ndpa_packet(adapter, bfee->sound_bw);
+
+ /* Send BF report poll if more than 1 MU STA */
+ for (i = 1; i < sounding->candidate_mu_bfee_cnt; i++) {
+ bfee = &info->bfee_entry[sounding->mu_sounding_list[i]];
+
+ if (i == (sounding->candidate_mu_bfee_cnt - 1))/* The last STA*/
+ _send_bf_report_poll(adapter, bfee->mac_addr, _TRUE);
+ else
+ _send_bf_report_poll(adapter, bfee->mac_addr, _FALSE);
+ }
+
+ sounding->candidate_mu_bfee_cnt = 0;
+
+ /* Set sounding timeout timer */
+ _set_timer(&info->sounding_timeout_timer, MU_SOUNDING_TIMEOUT);
+ return;
+ }
+
+ info->sounding_running--;
+ sounding->state = SOUNDING_STATE_INIT;
+ RTW_INFO("%s: Sounding finished!\n", __FUNCTION__);
+ rtw_ps_deny_cancel(adapter, PS_DENY_BEAMFORMING);
+}
+
+static void _sounding_force_stop(PADAPTER adapter)
+{
+ struct beamforming_info *info;
+ struct sounding_info *sounding;
+
+ info = GET_BEAMFORM_INFO(adapter);
+ sounding = &info->sounding_info;
+
+ if ((sounding->state == SOUNDING_STATE_SU_START)
+ || (sounding->state == SOUNDING_STATE_MU_START)) {
+ u8 res = _FALSE;
+ _cancel_timer_ex(&info->sounding_timeout_timer);
+ rtw_bf_cmd(adapter, BEAMFORMING_CTRL_END_PERIOD, &res, 1, 1);
+ return;
+ }
+
+ info->sounding_running--;
+ sounding->state = SOUNDING_STATE_INIT;
+ RTW_INFO("%s: Sounding finished!\n", __FUNCTION__);
+ rtw_ps_deny_cancel(adapter, PS_DENY_BEAMFORMING);
+}
+
+static void _sounding_timer_handler(void *FunctionContext)
+{
+ PADAPTER adapter;
+ struct beamforming_info *info;
+ struct sounding_info *sounding;
+ static u8 delay = 0;
+
+
+ RTW_DBG("+%s\n", __FUNCTION__);
+
+ adapter = (PADAPTER)FunctionContext;
+ info = GET_BEAMFORM_INFO(adapter);
+ sounding = &info->sounding_info;
+
+ if (SOUNDING_STATE_NONE == sounding->state) {
+ RTW_INFO("%s: Stop!\n", __FUNCTION__);
+ if (info->sounding_running)
+ RTW_WARN("%s: souding_running=%d when thread stop!\n",
+ __FUNCTION__, info->sounding_running);
+ return;
+ }
+
+ _set_timer(&info->sounding_timer, sounding->min_sounding_period);
+
+ if (!info->sounding_running) {
+ if (SOUNDING_STATE_INIT != sounding->state) {
+ RTW_WARN("%s: state(%d) != SOUNDING_STATE_INIT!!\n", __FUNCTION__, sounding->state);
+ sounding->state = SOUNDING_STATE_INIT;
+ }
+ delay = 0;
+ info->sounding_running++;
+ rtw_bf_cmd(adapter, BEAMFORMING_CTRL_START_PERIOD, NULL, 0, 1);
+ } else {
+ if (delay != 0xFF)
+ delay++;
+ RTW_WARN("%s: souding is still processing...(state:%d, running:%d, delay:%d)\n",
+ __FUNCTION__, sounding->state, info->sounding_running, delay);
+ if (delay > 3) {
+ RTW_WARN("%s: Stop sounding!!\n", __FUNCTION__);
+ _sounding_force_stop(adapter);
+ }
+ }
+}
+
+static void _sounding_timeout_timer_handler(void *FunctionContext)
{
PADAPTER adapter;
- struct beamforming_info *pBeamInfo;
+ struct beamforming_info *info;
+ struct sounding_info *sounding;
struct beamformee_entry *bfee;
- BEAMFORMING_CAP cap = BEAMFORMING_CAP_NONE;
+
+
+ RTW_WARN("+%s\n", __FUNCTION__);
+
+ adapter = (PADAPTER)FunctionContext;
+ info = GET_BEAMFORM_INFO(adapter);
+ sounding = &info->sounding_info;
+
+ if (SOUNDING_STATE_SU_START == sounding->state) {
+ sounding->state = SOUNDING_STATE_SOUNDING_TIMEOUT;
+ RTW_ERR("%s: Set to SU SOUNDING_STATE_SOUNDING_TIMEOUT\n", __FUNCTION__);
+ /* SU BFee */
+ bfee = &info->bfee_entry[sounding->su_bfee_curidx];
+ bfee->bSoundingTimeout = _TRUE;
+ RTW_WARN("%s: The BFee entry[%d] is Sounding Timeout!\n", __FUNCTION__, sounding->su_bfee_curidx);
+ } else if (SOUNDING_STATE_MU_START == sounding->state) {
+ sounding->state = SOUNDING_STATE_SOUNDING_TIMEOUT;
+ RTW_ERR("%s: Set to MU SOUNDING_STATE_SOUNDING_TIMEOUT\n", __FUNCTION__);
+ } else {
+ RTW_WARN("%s: unexpected sounding state:0x%02x\n", __FUNCTION__, sounding->state);
+ return;
+ }
+
+ rtw_bf_cmd(adapter, BEAMFORMING_CTRL_START_PERIOD, NULL, 0, 1);
+}
+
+static struct beamformer_entry *_bfer_get_free_entry(PADAPTER adapter)
+{
u8 i = 0;
+ struct beamforming_info *info;
+ struct beamformer_entry *bfer;
- adapter = mlme_to_adapter((struct mlme_priv *)mlme);
- pBeamInfo = GET_BEAMFORM_INFO(adapter);
+ info = GET_BEAMFORM_INFO(adapter);
for (i = 0; i < MAX_BEAMFORMER_ENTRY_NUM; i++) {
- bfee = &pBeamInfo->bfee_entry[i];
- if ((bfee->used == _TRUE)
- && (bfee->mac_id == mac_id)) {
- cap = bfee->cap;
- break;
+ bfer = &info->bfer_entry[i];
+ if (bfer->used == _FALSE)
+ return bfer;
+ }
+
+ return NULL;
+}
+
+static struct beamformer_entry *_bfer_get_entry_by_addr(PADAPTER adapter, u8 *ra)
+{
+ u8 i = 0;
+ struct beamforming_info *info;
+ struct beamformer_entry *bfer;
+
+
+ info = GET_BEAMFORM_INFO(adapter);
+
+ for (i = 0; i < MAX_BEAMFORMER_ENTRY_NUM; i++) {
+ bfer = &info->bfer_entry[i];
+ if (bfer->used == _FALSE)
+ continue;
+ if (_rtw_memcmp(ra, bfer->mac_addr, ETH_ALEN) == _TRUE)
+ return bfer;
+ }
+
+ return NULL;
+}
+
+static struct beamformer_entry *_bfer_add_entry(PADAPTER adapter,
+ struct sta_info *sta, u8 bf_cap, u8 sounding_dim, u8 comp_steering)
+{
+ struct mlme_priv *mlme;
+ struct beamforming_info *info;
+ struct beamformer_entry *bfer;
+ u8 *bssid;
+ u16 val16;
+ u8 i;
+
+
+ mlme = &adapter->mlmepriv;
+ info = GET_BEAMFORM_INFO(adapter);
+
+ bfer = _bfer_get_entry_by_addr(adapter, sta->cmn.mac_addr);
+ if (!bfer) {
+ bfer = _bfer_get_free_entry(adapter);
+ if (!bfer)
+ return NULL;
+ }
+
+ bfer->used = _TRUE;
+ _get_txvector_parameter(adapter, sta, &bfer->g_id, &bfer->p_aid);
+ _rtw_memcpy(bfer->mac_addr, sta->cmn.mac_addr, ETH_ALEN);
+ bfer->cap = bf_cap;
+ bfer->state = BEAMFORM_ENTRY_HW_STATE_ADD_INIT;
+ bfer->NumofSoundingDim = sounding_dim;
+
+ if (TEST_FLAG(bf_cap, BEAMFORMER_CAP_VHT_MU)) {
+ info->beamformer_mu_cnt += 1;
+ bfer->aid = sta->cmn.aid;
+ } else if (TEST_FLAG(bf_cap, BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT)) {
+ info->beamformer_su_cnt += 1;
+
+ /* Record HW idx info */
+ for (i = 0; i < MAX_NUM_BEAMFORMER_SU; i++) {
+ if ((info->beamformer_su_reg_maping & BIT(i)) == 0) {
+ info->beamformer_su_reg_maping |= BIT(i);
+ bfer->su_reg_index = i;
+ break;
+ }
}
+ RTW_INFO("%s: Add BFer entry beamformer_su_reg_maping=%#x, su_reg_index=%d\n",
+ __FUNCTION__, info->beamformer_su_reg_maping, bfer->su_reg_index);
+ }
+
+ return bfer;
+}
+
+static void _bfer_remove_entry(PADAPTER adapter, struct beamformer_entry *entry)
+{
+ struct beamforming_info *info;
+
+
+ info = GET_BEAMFORM_INFO(adapter);
+
+ entry->state = BEAMFORM_ENTRY_HW_STATE_DELETE_INIT;
+
+ if (TEST_FLAG(entry->cap, BEAMFORMER_CAP_VHT_MU)) {
+ info->beamformer_mu_cnt -= 1;
+ _rtw_memset(entry->gid_valid, 0, 8);
+ _rtw_memset(entry->user_position, 0, 16);
+ } else if (TEST_FLAG(entry->cap, BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT)) {
+ info->beamformer_su_cnt -= 1;
}
- return cap;
+ if (info->beamformer_mu_cnt == 0)
+ info->beamforming_cap &= ~BEAMFORMEE_CAP_VHT_MU;
+ if (info->beamformer_su_cnt == 0)
+ info->beamforming_cap &= ~(BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT);
}
-struct beamformer_entry *beamforming_get_bfer_entry_by_addr(PADAPTER adapter, u8 *ra)
+static u8 _bfer_set_entry_gid(PADAPTER adapter, u8 *addr, u8 *gid, u8 *position)
{
- u8 i = 0;
- struct beamforming_info *bf_info;
- struct beamformer_entry *entry;
+ struct beamformer_entry bfer;
+
+ memset(&bfer, 0, sizeof(bfer));
+ memcpy(bfer.mac_addr, addr, 6);
+ /* Parsing Membership Status Array */
+ memcpy(bfer.gid_valid, gid, 8);
- bf_info = GET_BEAMFORM_INFO(adapter);
+ /* Parsing User Position Array */
+ memcpy(bfer.user_position, position, 16);
- for (i = 0; i < MAX_BEAMFORMER_ENTRY_NUM; i++) {
- entry = &bf_info->bfer_entry[i];
- if (entry->used == _FALSE)
- continue;
- if (_rtw_memcmp(ra, entry->mac_addr, ETH_ALEN) == _TRUE) {
- return entry;
- }
- }
+ /* Config HW GID table */
+ rtw_bf_cmd(adapter, BEAMFORMING_CTRL_SET_GID_TABLE, (u8 *) &bfer,
+ sizeof(bfer), 1);
- return NULL;
+ return _SUCCESS;
}
-struct beamformee_entry *beamforming_get_bfee_entry_by_addr(PADAPTER adapter, u8 *ra)
+static struct beamformee_entry *_bfee_get_free_entry(PADAPTER adapter)
{
u8 i = 0;
- struct beamforming_info *bf_info;
- struct beamformee_entry *entry;
+ struct beamforming_info *info;
+ struct beamformee_entry *bfee;
- bf_info = GET_BEAMFORM_INFO(adapter);
+ info = GET_BEAMFORM_INFO(adapter);
for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {
- entry = &bf_info->bfee_entry[i];
- if (entry->used == _FALSE)
- continue;
- if (_rtw_memcmp(ra, entry->mac_addr, ETH_ALEN) == _TRUE)
- return entry;
+ bfee = &info->bfee_entry[i];
+ if (bfee->used == _FALSE)
+ return bfee;
}
return NULL;
}
-static struct beamformer_entry *_get_bfer_free_entry(PADAPTER adapter)
+static struct beamformee_entry *_bfee_get_entry_by_addr(PADAPTER adapter, u8 *ra)
{
u8 i = 0;
- struct beamforming_info *bf_info;
- struct beamformer_entry *entry;
+ struct beamforming_info *info;
+ struct beamformee_entry *bfee;
- bf_info = GET_BEAMFORM_INFO(adapter);
+ info = GET_BEAMFORM_INFO(adapter);
- for (i = 0; i < MAX_BEAMFORMER_ENTRY_NUM; i++) {
- entry = &bf_info->bfer_entry[i];
- if (entry->used == _FALSE)
- return entry;
+ for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {
+ bfee = &info->bfee_entry[i];
+ if (bfee->used == _FALSE)
+ continue;
+ if (_rtw_memcmp(ra, bfee->mac_addr, ETH_ALEN) == _TRUE)
+ return bfee;
}
return NULL;
}
-static struct beamformee_entry *_get_bfee_free_entry(PADAPTER adapter)
+static u8 _bfee_get_first_su_entry_idx(PADAPTER adapter, struct beamformee_entry *ignore)
{
- u8 i = 0;
- struct beamforming_info *bf_info;
- struct beamformee_entry *entry;
+ struct beamforming_info *info;
+ struct beamformee_entry *bfee;
+ u8 i;
- bf_info = GET_BEAMFORM_INFO(adapter);
+ info = GET_BEAMFORM_INFO(adapter);
for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {
- entry = &bf_info->bfee_entry[i];
- if (entry->used == _FALSE)
- return entry;
+ bfee = &info->bfee_entry[i];
+ if (ignore && (bfee == ignore))
+ continue;
+ if (bfee->used == _FALSE)
+ continue;
+ if ((!TEST_FLAG(bfee->cap, BEAMFORMEE_CAP_VHT_MU))
+ && TEST_FLAG(bfee->cap, BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT))
+ return i;
}
- return NULL;
+ return 0xFF;
}
/*
@@ -135,354 +1152,208 @@ static struct beamformee_entry *_get_bfee_free_entry(PADAPTER adapter)
* Get the first entry index of MU Beamformee.
*
* Return Value:
- * Index of the first MU sta.
+ * Index of the first MU sta, or 0xFF for invalid index.
*
* 2015.05.25. Created by tynli.
*
*/
-static u8 _get_first_mu_bfee_entry_idx(PADAPTER adapter, struct beamformee_entry *ignore)
+static u8 _bfee_get_first_mu_entry_idx(PADAPTER adapter, struct beamformee_entry *ignore)
{
- struct beamforming_info *bf_info;
- struct beamformee_entry *entry;
- u8 idx = 0xFF;
- u8 bFound = _FALSE;
+ struct beamforming_info *info;
+ struct beamformee_entry *bfee;
+ u8 i;
- bf_info = GET_BEAMFORM_INFO(adapter);
+ info = GET_BEAMFORM_INFO(adapter);
- for (idx = 0; idx < MAX_BEAMFORMEE_ENTRY_NUM; idx++) {
- entry = &bf_info->bfee_entry[idx];
- if (ignore && (entry == ignore))
+ for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {
+ bfee = &info->bfee_entry[i];
+ if (ignore && (bfee == ignore))
continue;
- if ((entry->used == _TRUE) &&
- TEST_FLAG(entry->cap, BEAMFORMEE_CAP_VHT_MU)) {
- bFound = _TRUE;
- break;
- }
+ if (bfee->used == _FALSE)
+ continue;
+ if (TEST_FLAG(bfee->cap, BEAMFORMEE_CAP_VHT_MU))
+ return i;
}
- if (bFound == _FALSE)
- idx = 0xFF;
-
- return idx;
-}
-
-static void _update_min_sounding_period(PADAPTER adapter, u16 period, u8 leave)
-{
- struct beamforming_info *bf_info;
- struct beamformee_entry *entry;
- u8 i = 0;
- u16 min_val = 0xFFFF;
-
-
- bf_info = GET_BEAMFORM_INFO(adapter);
-
- if (_TRUE == leave) {
- /*
- * When a BFee left,
- * we need to find the latest min sounding period
- * from the remaining BFees
- */
- for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {
- entry = &bf_info->bfee_entry[i];
- if ((entry->used == _TRUE)
- && (entry->sound_period < min_val))
- min_val = entry->sound_period;
- }
-
- if (min_val == 0xFFFF)
- bf_info->sounding_info.min_sounding_period = 0;
- else
- bf_info->sounding_info.min_sounding_period = min_val;
- } else {
- if ((bf_info->sounding_info.min_sounding_period == 0)
- || (period < bf_info->sounding_info.min_sounding_period))
- bf_info->sounding_info.min_sounding_period = period;
- }
+ return 0xFF;
}
-static struct beamformer_entry *_add_bfer_entry(PADAPTER adapter,
+static struct beamformee_entry *_bfee_add_entry(PADAPTER adapter,
struct sta_info *sta, u8 bf_cap, u8 sounding_dim, u8 comp_steering)
{
struct mlme_priv *mlme;
- struct beamforming_info *bf_info;
- struct beamformer_entry *entry;
+ struct beamforming_info *info;
+ struct beamformee_entry *bfee;
u8 *bssid;
u16 val16;
u8 i;
mlme = &adapter->mlmepriv;
- bf_info = GET_BEAMFORM_INFO(adapter);
+ info = GET_BEAMFORM_INFO(adapter);
- entry = beamforming_get_bfer_entry_by_addr(adapter, sta->hwaddr);
- if (!entry) {
- entry = _get_bfer_free_entry(adapter);
- if (!entry)
+ bfee = _bfee_get_entry_by_addr(adapter, sta->cmn.mac_addr);
+ if (!bfee) {
+ bfee = _bfee_get_free_entry(adapter);
+ if (!bfee)
return NULL;
}
- entry->used = _TRUE;
-
- if (check_fwstate(mlme, WIFI_AP_STATE)) {
- bssid = adapter_mac_addr(adapter);
- /* BSSID[44:47] xor BSSID[40:43] */
- val16 = ((bssid[5] & 0xF0) >> 4) ^ (bssid[5] & 0xF);
- /* (dec(A) + dec(B)*32) mod 512 */
- entry->p_aid = (sta->aid + val16 * 32) & 0x1FF;
- entry->g_id = 63;
- } else if ((check_fwstate(mlme, WIFI_ADHOC_STATE) == _TRUE)
- || (check_fwstate(mlme, WIFI_ADHOC_MASTER_STATE) == _TRUE)) {
- entry->p_aid = 0;
- entry->g_id = 63;
- } else {
- bssid = sta->hwaddr;
- /* BSSID[39:47] */
- entry->p_aid = (bssid[5] << 1) | (bssid[4] >> 7);
- entry->g_id = 0;
- }
- RTW_INFO("%s: p_aid=0x%04x g_id=0x%04x aid=0x%x\n",
- __FUNCTION__, entry->p_aid, entry->g_id, sta->aid);
-
- _rtw_memcpy(entry->mac_addr, sta->hwaddr, ETH_ALEN);
- entry->cap = bf_cap;
- entry->state = BEAMFORM_ENTRY_HW_STATE_ADD_INIT;
- entry->NumofSoundingDim = sounding_dim;
-
- if (TEST_FLAG(bf_cap, BEAMFORMER_CAP_VHT_MU)) {
- bf_info->beamformer_mu_cnt += 1;
- entry->aid = sta->aid;
- } else if (TEST_FLAG(bf_cap, BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT)) {
- bf_info->beamformer_su_cnt += 1;
+ bfee->used = _TRUE;
+ bfee->aid = sta->cmn.aid;
+ bfee->mac_id = sta->cmn.mac_id;
+ bfee->sound_bw = sta->cmn.bw_mode;
+
+ _get_txvector_parameter(adapter, sta, &bfee->g_id, &bfee->p_aid);
+ sta->cmn.bf_info.g_id = bfee->g_id;
+ sta->cmn.bf_info.p_aid = bfee->p_aid;
+
+ _rtw_memcpy(bfee->mac_addr, sta->cmn.mac_addr, ETH_ALEN);
+ bfee->txbf = _FALSE;
+ bfee->sounding = _FALSE;
+ bfee->sound_period = 40;
+ _sounding_update_min_period(adapter, bfee->sound_period, _FALSE);
+ bfee->SoundCnt = GetInitSoundCnt(bfee->sound_period, info->sounding_info.min_sounding_period);
+ bfee->cap = bf_cap;
+ bfee->state = BEAMFORM_ENTRY_HW_STATE_ADD_INIT;
+
+ bfee->bCandidateSoundingPeer = _FALSE;
+ bfee->bSoundingTimeout = _FALSE;
+ bfee->bDeleteSounding = _FALSE;
+ bfee->bApplySounding = _TRUE;
+
+ bfee->tx_timestamp = 0;
+ bfee->tx_bytes = 0;
+
+ bfee->LogStatusFailCnt = 0;
+ bfee->NumofSoundingDim = sounding_dim;
+ bfee->comp_steering_num_of_bfer = comp_steering;
+ bfee->bSuspendSUCap = _FALSE;
- /* Record HW idx info */
- for (i = 0; i < MAX_NUM_BEAMFORMER_SU; i++) {
- if ((bf_info->beamformer_su_reg_maping & BIT(i)) == 0) {
- bf_info->beamformer_su_reg_maping |= BIT(i);
- entry->su_reg_index = i;
- break;
+ if (TEST_FLAG(bf_cap, BEAMFORMEE_CAP_VHT_MU)) {
+ info->beamformee_mu_cnt += 1;
+ info->first_mu_bfee_index = _bfee_get_first_mu_entry_idx(adapter, NULL);
+
+ if (_TRUE == info->bEnableSUTxBFWorkAround) {
+ /* When the first MU BFee added, discard SU BFee bfee's capability */
+ if ((info->beamformee_mu_cnt == 1) && (info->beamformee_su_cnt > 0)) {
+ if (info->TargetSUBFee) {
+ info->TargetSUBFee->bSuspendSUCap = _TRUE;
+ info->TargetSUBFee->bDeleteSounding = _TRUE;
+ } else {
+ RTW_ERR("%s: UNEXPECTED!! info->TargetSUBFee is NULL!", __FUNCTION__);
+ }
+ info->TargetSUBFee = NULL;
+ _rtw_memset(&info->TargetCSIInfo, 0, sizeof(struct _RT_CSI_INFO));
+ rtw_bf_cmd(adapter, BEAMFORMING_CTRL_SET_CSI_REPORT, (u8*)&info->TargetCSIInfo, sizeof(struct _RT_CSI_INFO), 0);
}
}
- RTW_INFO("%s: Add BFer entry beamformer_su_reg_maping=%#X, su_reg_index=%d\n",
- __FUNCTION__, bf_info->beamformer_su_reg_maping, entry->su_reg_index);
- }
-
- return entry;
-}
-
-static struct beamformee_entry *_add_bfee_entry(PADAPTER adapter,
- struct sta_info *sta, u8 bf_cap, u8 sounding_dim, u8 comp_steering)
-{
- struct mlme_priv *mlme;
- struct beamforming_info *bf_info;
- struct beamformee_entry *entry;
- u8 *bssid;
- u16 val16;
- u8 i;
-
-
- mlme = &adapter->mlmepriv;
- bf_info = GET_BEAMFORM_INFO(adapter);
-
- entry = beamforming_get_bfee_entry_by_addr(adapter, sta->hwaddr);
- if (!entry) {
- entry = _get_bfee_free_entry(adapter);
- if (!entry)
- return NULL;
- }
-
- entry->used = _TRUE;
- entry->aid = sta->aid;
- entry->mac_id = sta->mac_id;
- entry->sound_bw = sta->bw_mode;
-
- if (check_fwstate(mlme, WIFI_AP_STATE)) {
- bssid = adapter_mac_addr(adapter);
- /* BSSID[44:47] xor BSSID[40:43] */
- val16 = ((bssid[5] & 0xF0) >> 4) ^ (bssid[5] & 0xF);
- /* (dec(A) + dec(B)*32) mod 512 */
- entry->p_aid = (sta->aid + val16 * 32) & 0x1FF;
- entry->g_id = 63;
- } else if (check_fwstate(mlme, WIFI_ADHOC_STATE) || check_fwstate(mlme, WIFI_ADHOC_MASTER_STATE)) {
- entry->p_aid = 0;
- entry->g_id = 63;
- } else {
- bssid = sta->hwaddr;
- /* BSSID[39:47] */
- entry->p_aid = (bssid[5] << 1) | (bssid[4] >> 7);
- entry->g_id = 0;
- }
-
- _rtw_memcpy(entry->mac_addr, sta->hwaddr, ETH_ALEN);
- entry->txbf = _FALSE;
- entry->sounding = _FALSE;
- entry->sound_period = 40;
- entry->cap = bf_cap;
-
- _update_min_sounding_period(adapter, entry->sound_period, _FALSE);
- entry->SoundCnt = GetInitSoundCnt(entry->sound_period, bf_info->sounding_info.min_sounding_period);
-
- entry->LogStatusFailCnt = 0;
-
- entry->NumofSoundingDim = sounding_dim;
- entry->CompSteeringNumofBFer = comp_steering;
- entry->state = BEAMFORM_ENTRY_HW_STATE_ADD_INIT;
-
- if (TEST_FLAG(bf_cap, BEAMFORMEE_CAP_VHT_MU)) {
- bf_info->beamformee_mu_cnt += 1;
- bf_info->first_mu_bfee_index = _get_first_mu_bfee_entry_idx(adapter, NULL);
/* Record HW idx info */
for (i = 0; i < MAX_NUM_BEAMFORMEE_MU; i++) {
- if ((bf_info->beamformee_mu_reg_maping & BIT(i)) == 0) {
- bf_info->beamformee_mu_reg_maping |= BIT(i);
- entry->mu_reg_index = i;
+ if ((info->beamformee_mu_reg_maping & BIT(i)) == 0) {
+ info->beamformee_mu_reg_maping |= BIT(i);
+ bfee->mu_reg_index = i;
break;
}
}
- RTW_INFO("%s: Add BFee entry beamformee_mu_reg_maping=%#X, mu_reg_index=%d\n",
- __FUNCTION__, bf_info->beamformee_mu_reg_maping, entry->mu_reg_index);
+ RTW_INFO("%s: Add BFee entry beamformee_mu_reg_maping=%#x, mu_reg_index=%d\n",
+ __FUNCTION__, info->beamformee_mu_reg_maping, bfee->mu_reg_index);
} else if (TEST_FLAG(bf_cap, BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT)) {
- bf_info->beamformee_su_cnt += 1;
+ info->beamformee_su_cnt += 1;
+
+ if (_TRUE == info->bEnableSUTxBFWorkAround) {
+ /* Record the first SU BFee index. We only allow the first SU BFee to be sound */
+ if ((info->beamformee_su_cnt == 1) && (info->beamformee_mu_cnt == 0)) {
+ info->TargetSUBFee = bfee;
+ _rtw_memset(&info->TargetCSIInfo, 0, sizeof(struct _RT_CSI_INFO));
+ bfee->bSuspendSUCap = _FALSE;
+ } else {
+ bfee->bSuspendSUCap = _TRUE;
+ }
+ }
/* Record HW idx info */
for (i = 0; i < MAX_NUM_BEAMFORMEE_SU; i++) {
- if ((bf_info->beamformee_su_reg_maping & BIT(i)) == 0) {
- bf_info->beamformee_su_reg_maping |= BIT(i);
- entry->su_reg_index = i;
+ if ((info->beamformee_su_reg_maping & BIT(i)) == 0) {
+ info->beamformee_su_reg_maping |= BIT(i);
+ bfee->su_reg_index = i;
break;
}
}
- RTW_INFO("%s: Add BFee entry beamformee_su_reg_maping=%#X, su_reg_index=%d\n",
- __FUNCTION__, bf_info->beamformee_su_reg_maping, entry->su_reg_index);
+ RTW_INFO("%s: Add BFee entry beamformee_su_reg_maping=%#x, su_reg_index=%d\n",
+ __FUNCTION__, info->beamformee_su_reg_maping, bfee->su_reg_index);
}
- return entry;
+ return bfee;
}
-static void _remove_bfer_entry(PADAPTER adapter, struct beamformer_entry *entry)
+static void _bfee_remove_entry(PADAPTER adapter, struct beamformee_entry *entry)
{
- struct beamforming_info *bf_info;
-
-
- bf_info = GET_BEAMFORM_INFO(adapter);
-
- entry->state = BEAMFORM_ENTRY_HW_STATE_DELETE_INIT;
-
- if (TEST_FLAG(entry->cap, BEAMFORMER_CAP_VHT_MU)) {
- bf_info->beamformer_mu_cnt -= 1;
- _rtw_memset(entry->gid_valid, 0, 8);
- _rtw_memset(entry->user_position, 0, 16);
- } else if (TEST_FLAG(entry->cap, BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT)) {
- bf_info->beamformer_su_cnt -= 1;
- }
-
- if (bf_info->beamformer_mu_cnt == 0)
- bf_info->beamforming_cap &= ~BEAMFORMEE_CAP_VHT_MU;
- if (bf_info->beamformer_su_cnt == 0)
- bf_info->beamforming_cap &= ~(BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT);
-}
-
-static void _remove_bfee_entry(PADAPTER adapter, struct beamformee_entry *entry)
-{
- struct beamforming_info *bf_info;
+ struct beamforming_info *info;
+ u8 idx;
- bf_info = GET_BEAMFORM_INFO(adapter);
+ info = GET_BEAMFORM_INFO(adapter);
entry->state = BEAMFORM_ENTRY_HW_STATE_DELETE_INIT;
if (TEST_FLAG(entry->cap, BEAMFORMEE_CAP_VHT_MU)) {
- bf_info->beamformee_mu_cnt -= 1;
- bf_info->first_mu_bfee_index = _get_first_mu_bfee_entry_idx(adapter, entry);
+ info->beamformee_mu_cnt -= 1;
+ info->first_mu_bfee_index = _bfee_get_first_mu_entry_idx(adapter, entry);
+
+ if (_TRUE == info->bEnableSUTxBFWorkAround) {
+ if ((info->beamformee_mu_cnt == 0) && (info->beamformee_su_cnt > 0)) {
+ idx = _bfee_get_first_su_entry_idx(adapter, NULL);
+ info->TargetSUBFee = &info->bfee_entry[idx];
+ _rtw_memset(&info->TargetCSIInfo, 0, sizeof(struct _RT_CSI_INFO));
+ info->TargetSUBFee->bSuspendSUCap = _FALSE;
+ }
+ }
} else if (TEST_FLAG(entry->cap, BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT)) {
- bf_info->beamformee_su_cnt -= 1;
+ info->beamformee_su_cnt -= 1;
+
+ /* When the target SU BFee leaves, disable workaround */
+ if ((_TRUE == info->bEnableSUTxBFWorkAround)
+ && (entry == info->TargetSUBFee)) {
+ entry->bSuspendSUCap = _TRUE;
+ info->TargetSUBFee = NULL;
+ _rtw_memset(&info->TargetCSIInfo, 0, sizeof(struct _RT_CSI_INFO));
+ rtw_bf_cmd(adapter, BEAMFORMING_CTRL_SET_CSI_REPORT, (u8*)&info->TargetCSIInfo, sizeof(struct _RT_CSI_INFO), 0);
+ }
}
- if (bf_info->beamformee_mu_cnt == 0)
- bf_info->beamforming_cap &= ~BEAMFORMER_CAP_VHT_MU;
- if (bf_info->beamformee_su_cnt == 0)
- bf_info->beamforming_cap &= ~(BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT);
+ if (info->beamformee_mu_cnt == 0)
+ info->beamforming_cap &= ~BEAMFORMER_CAP_VHT_MU;
+ if (info->beamformee_su_cnt == 0)
+ info->beamforming_cap &= ~(BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT);
- _update_min_sounding_period(adapter, 0, _TRUE);
+ _sounding_update_min_period(adapter, 0, _TRUE);
}
-/*
- * Parameters
- * adapter struct _adapter*
- * sta struct sta_info*
- * sta_bf_cap beamforming capabe of sta
- * sounding_dim Number of Sounding Dimensions
- * comp_steering Compressed Steering Number of Beamformer Antennas Supported
- */
-static void _get_sta_beamform_cap(PADAPTER adapter, struct sta_info *sta,
- u8 *sta_bf_cap, u8 *sounding_dim, u8 *comp_steering)
+static enum beamforming_cap _bfee_get_entry_cap_by_macid(PADAPTER adapter, u8 macid)
{
- struct ht_priv *ht;
-#ifdef CONFIG_80211AC_VHT
- struct vht_priv *vht;
-#endif /* CONFIG_80211AC_VHT */
- u16 bf_cap;
-
-
- *sta_bf_cap = 0;
- *sounding_dim = 0;
- *comp_steering = 0;
+ struct beamforming_info *info;
+ struct beamformee_entry *bfee;
+ u8 i;
- ht = &adapter->mlmepriv.htpriv;
-#ifdef CONFIG_80211AC_VHT
- vht = &adapter->mlmepriv.vhtpriv;
-#endif /* CONFIG_80211AC_VHT */
- if (IsSupportedHT(sta->wireless_mode) == _TRUE) {
- /* HT */
- bf_cap = ht->beamform_cap;
+ info = GET_BEAMFORM_INFO(adapter);
- if (TEST_FLAG(bf_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) {
- *sta_bf_cap |= BEAMFORMER_CAP_HT_EXPLICIT;
- *sounding_dim = (bf_cap & BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP) >> 6;
- }
- if (TEST_FLAG(bf_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) {
- *sta_bf_cap |= BEAMFORMEE_CAP_HT_EXPLICIT;
- *comp_steering = (bf_cap & BEAMFORMING_HT_BEAMFORMER_STEER_NUM) >> 4;
- }
+ for (i = 0; i < MAX_BEAMFORMER_ENTRY_NUM; i++) {
+ bfee = &info->bfee_entry[i];
+ if (bfee->used == _FALSE)
+ continue;
+ if (bfee->mac_id == macid)
+ return bfee->cap;
}
-#ifdef CONFIG_80211AC_VHT
- if (IsSupportedVHT(sta->wireless_mode) == _TRUE) {
- /* VHT */
- bf_cap = vht->beamform_cap;
-
- /* We are SU Beamformee because the STA is SU Beamformer */
- if (TEST_FLAG(bf_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) {
- *sta_bf_cap |= BEAMFORMER_CAP_VHT_SU;
-
- /* We are MU Beamformee because the STA is MU Beamformer */
- if (TEST_FLAG(bf_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE))
- *sta_bf_cap |= BEAMFORMER_CAP_VHT_MU;
-
- *sounding_dim = (bf_cap & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM) >> 12;
- }
- /* We are SU Beamformer because the STA is SU Beamformee */
- if (TEST_FLAG(bf_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) {
- *sta_bf_cap |= BEAMFORMEE_CAP_VHT_SU;
-
- /* We are MU Beamformer because the STA is MU Beamformee */
- if (TEST_FLAG(bf_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE))
- *sta_bf_cap |= BEAMFORMEE_CAP_VHT_MU;
-
- *comp_steering = (bf_cap & BEAMFORMING_VHT_BEAMFORMER_STS_CAP) >> 8;
- }
- }
-#endif /* CONFIG_80211AC_VHT */
+ return BEAMFORMING_CAP_NONE;
}
-/*
- * Return:
- * _TRUE success
- * _FALSE fail
- */
-static u8 _init_entry(PADAPTER adapter, struct sta_info *sta)
+
+static void _beamforming_enter(PADAPTER adapter, void *p)
{
struct mlme_priv *mlme;
struct ht_priv *htpriv;
@@ -490,10 +1361,10 @@ static u8 _init_entry(PADAPTER adapter, struct sta_info *sta)
struct vht_priv *vhtpriv;
#endif
struct mlme_ext_priv *mlme_ext;
- struct sta_info *sta_real;
+ struct sta_info *sta, *sta_copy;
+ struct beamforming_info *info;
struct beamformer_entry *bfer = NULL;
struct beamformee_entry *bfee = NULL;
- u8 *ra;
u8 wireless_mode;
u8 sta_bf_cap;
u8 sounding_dim = 0; /* number of sounding dimensions */
@@ -506,14 +1377,27 @@ static u8 _init_entry(PADAPTER adapter, struct sta_info *sta)
vhtpriv = &mlme->vhtpriv;
#endif
mlme_ext = &adapter->mlmeextpriv;
- ra = sta->hwaddr;
- wireless_mode = sta->wireless_mode;
- sta_real = rtw_get_stainfo(&adapter->stapriv, ra);
+ info = GET_BEAMFORM_INFO(adapter);
+
+ sta_copy = (struct sta_info *)p;
+ sta = rtw_get_stainfo(&adapter->stapriv, sta_copy->cmn.mac_addr);
+ if (!sta) {
+ RTW_ERR("%s: Cann't find STA info for " MAC_FMT "\n",
+ __FUNCTION__, MAC_ARG(sta_copy->cmn.mac_addr));
+ return;
+ }
+ if (sta != sta_copy) {
+ RTW_WARN("%s: Origin sta(fake)=%p realsta=%p for " MAC_FMT "\n",
+ __FUNCTION__, sta_copy, sta, MAC_ARG(sta_copy->cmn.mac_addr));
+ }
/* The current setting does not support Beaforming */
- if ((IsSupportedHT(wireless_mode) == _FALSE)
- && (IsSupportedVHT(wireless_mode) == _FALSE))
- return _FALSE;
+ wireless_mode = sta->wireless_mode;
+ if ((is_supported_ht(wireless_mode) == _FALSE)
+ && (is_supported_vht(wireless_mode) == _FALSE)) {
+ RTW_WARN("%s: Not support HT or VHT mode\n", __FUNCTION__);
+ return;
+ }
if ((0 == htpriv->beamform_cap)
#ifdef CONFIG_80211AC_VHT
@@ -521,51 +1405,59 @@ static u8 _init_entry(PADAPTER adapter, struct sta_info *sta)
#endif
) {
RTW_INFO("The configuration disabled Beamforming! Skip...\n");
- return _FALSE;
+ return;
}
_get_sta_beamform_cap(adapter, sta,
&sta_bf_cap, &sounding_dim, &comp_steering_num);
RTW_INFO("STA Beamforming Capability=0x%02X\n", sta_bf_cap);
-
if (sta_bf_cap == BEAMFORMING_CAP_NONE)
- return _FALSE;
-
+ return;
if ((sta_bf_cap & BEAMFORMEE_CAP_HT_EXPLICIT)
|| (sta_bf_cap & BEAMFORMEE_CAP_VHT_SU)
|| (sta_bf_cap & BEAMFORMEE_CAP_VHT_MU))
sta_bf_cap |= BEAMFORMEE_CAP;
- else
+ if ((sta_bf_cap & BEAMFORMER_CAP_HT_EXPLICIT)
+ || (sta_bf_cap & BEAMFORMER_CAP_VHT_SU)
+ || (sta_bf_cap & BEAMFORMER_CAP_VHT_MU))
sta_bf_cap |= BEAMFORMER_CAP;
if (sta_bf_cap & BEAMFORMER_CAP) {
/* The other side is beamformer */
- bfer = _add_bfer_entry(adapter, sta, sta_bf_cap, sounding_dim, comp_steering_num);
- if (bfer == NULL) {
+ bfer = _bfer_add_entry(adapter, sta, sta_bf_cap, sounding_dim, comp_steering_num);
+ if (!bfer)
RTW_ERR("%s: Fail to allocate bfer entry!\n", __FUNCTION__);
- return _FALSE;
- }
-
- sta_real->txbf_paid = bfer->p_aid;
- sta_real->txbf_gid = bfer->g_id;
- } else {
+ }
+ if (sta_bf_cap & BEAMFORMEE_CAP) {
/* The other side is beamformee */
- bfee = _add_bfee_entry(adapter, sta, sta_bf_cap, sounding_dim, comp_steering_num);
- if (bfee == NULL) {
+ bfee = _bfee_add_entry(adapter, sta, sta_bf_cap, sounding_dim, comp_steering_num);
+ if (!bfee)
RTW_ERR("%s: Fail to allocate bfee entry!\n", __FUNCTION__);
- return _FALSE;
- }
+ }
+ if (!bfer && !bfee)
+ return;
- sta_real->txbf_paid = bfee->p_aid;
- sta_real->txbf_gid = bfee->g_id;
+ rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_ENTER, (u8*)sta);
+
+ /* Perform sounding if there is BFee */
+ if ((info->beamformee_su_cnt != 0)
+ || (info->beamformee_mu_cnt != 0)) {
+ if (SOUNDING_STATE_NONE == info->sounding_info.state) {
+ info->sounding_info.state = SOUNDING_STATE_INIT;
+ /* Start sounding after 2 sec */
+ _set_timer(&info->sounding_timer, 2000);
+ }
}
+}
- return _TRUE;
+static void _beamforming_reset(PADAPTER adapter)
+{
+ RTW_ERR("%s: Not ready!!\n", __FUNCTION__);
}
-static void _deinit_entry(PADAPTER adapter, u8 *ra)
+static void _beamforming_leave(PADAPTER adapter, u8 *ra)
{
- struct beamforming_info *bf_info;
+ struct beamforming_info *info;
struct beamformer_entry *bfer = NULL;
struct beamformee_entry *bfee = NULL;
u8 bHwStateAddInit = _FALSE;
@@ -573,9 +1465,9 @@ static void _deinit_entry(PADAPTER adapter, u8 *ra)
RTW_INFO("+%s\n", __FUNCTION__);
- bf_info = GET_BEAMFORM_INFO(adapter);
- bfer = beamforming_get_bfer_entry_by_addr(adapter, ra);
- bfee = beamforming_get_bfee_entry_by_addr(adapter, ra);
+ info = GET_BEAMFORM_INFO(adapter);
+ bfer = _bfer_get_entry_by_addr(adapter, ra);
+ bfee = _bfee_get_entry_by_addr(adapter, ra);
if (!bfer && !bfee) {
RTW_WARN("%s: " MAC_FMT " is neither beamforming ee or er!!\n",
@@ -583,58 +1475,226 @@ static void _deinit_entry(PADAPTER adapter, u8 *ra)
return;
}
- if (bfer && bfee)
- RTW_ERR("%s: " MAC_FMT " is both beamforming ee & er!!\n",
- __FUNCTION__, MAC_ARG(ra));
+ if (bfer)
+ _bfer_remove_entry(adapter, bfer);
+
+ if (bfee)
+ _bfee_remove_entry(adapter, bfee);
+
+ rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_LEAVE, ra);
+
+ /* Stop sounding if there is no any BFee */
+ if ((info->beamformee_su_cnt == 0)
+ && (info->beamformee_mu_cnt == 0)) {
+ _cancel_timer_ex(&info->sounding_timer);
+ _sounding_init(&info->sounding_info);
+ }
+
+ RTW_INFO("-%s\n", __FUNCTION__);
+}
+
+static void _beamforming_sounding_down(PADAPTER adapter, u8 status)
+{
+ struct beamforming_info *info;
+ struct sounding_info *sounding;
+ struct beamformee_entry *bfee;
+
+
+ info = GET_BEAMFORM_INFO(adapter);
+ sounding = &info->sounding_info;
+
+ RTW_INFO("+%s: sounding=%d, status=0x%02x\n", __FUNCTION__, sounding->state, status);
+
+ if (sounding->state == SOUNDING_STATE_MU_START) {
+ RTW_INFO("%s: MU sounding done\n", __FUNCTION__);
+ sounding->state = SOUNDING_STATE_MU_SOUNDDOWN;
+ RTW_INFO("%s: Set to SOUNDING_STATE_MU_SOUNDDOWN\n", __FUNCTION__);
+ info->SetHalSoundownOnDemandCnt++;
+ rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_STATUS, &status);
+ } else if (sounding->state == SOUNDING_STATE_SU_START) {
+ RTW_INFO("%s: SU entry[%d] sounding down\n", __FUNCTION__, sounding->su_bfee_curidx);
+ bfee = &info->bfee_entry[sounding->su_bfee_curidx];
+ sounding->state = SOUNDING_STATE_SU_SOUNDDOWN;
+ RTW_INFO("%s: Set to SOUNDING_STATE_SU_SOUNDDOWN\n", __FUNCTION__);
+
+ /*
+ *
+ * bfee->bSoundingTimeout this flag still cannot avoid
+ * old sound down event happens in the new sounding period.
+ * 2015.12.10
+ */
+ if (_TRUE == bfee->bSoundingTimeout) {
+ RTW_WARN("%s: The entry[%d] is bSoundingTimeout!\n", __FUNCTION__, sounding->su_bfee_curidx);
+ bfee->bSoundingTimeout = _FALSE;
+ return;
+ }
+
+ if (_TRUE == status) {
+ /* success */
+ bfee->LogStatusFailCnt = 0;
+ info->SetHalSoundownOnDemandCnt++;
+ rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_STATUS, &status);
+ } else if (_TRUE == bfee->bDeleteSounding) {
+ RTW_WARN("%s: Delete entry[%d] sounding info!\n", __FUNCTION__, sounding->su_bfee_curidx);
+ rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_STATUS, &status);
+ bfee->bDeleteSounding = _FALSE;
+ } else {
+ bfee->LogStatusFailCnt++;
+ RTW_WARN("%s: LogStatusFailCnt=%d\n", __FUNCTION__, bfee->LogStatusFailCnt);
+ if (bfee->LogStatusFailCnt > 30) {
+ RTW_ERR("%s: LogStatusFailCnt > 30, Stop SOUNDING!!\n", __FUNCTION__);
+ rtw_bf_cmd(adapter, BEAMFORMING_CTRL_LEAVE, bfee->mac_addr, ETH_ALEN, 1);
+ }
+ }
+ } else {
+ RTW_WARN("%s: unexpected sounding state:0x%02x\n", __FUNCTION__, sounding->state);
+ return;
+ }
+
+ rtw_bf_cmd(adapter, BEAMFORMING_CTRL_START_PERIOD, NULL, 0, 0);
+}
+
+static void _c2h_snd_txbf(PADAPTER adapter, u8 *buf, u8 buf_len)
+{
+ struct beamforming_info *info;
+ u8 res;
- if (bfer)
- _remove_bfer_entry(adapter, bfer);
+ info = GET_BEAMFORM_INFO(adapter);
- if (bfee)
- _remove_bfee_entry(adapter, bfee);
+ _cancel_timer_ex(&info->sounding_timeout_timer);
- rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_LEAVE, ra);
+ res = C2H_SND_TXBF_GET_SND_RESULT(buf) ? _TRUE : _FALSE;
+ RTW_INFO("+%s: %s\n", __FUNCTION__, res==_TRUE?"Success":"Fail!");
- RTW_DBG("-%s\n", __FUNCTION__);
+ rtw_bf_cmd(adapter, BEAMFORMING_CTRL_END_PERIOD, &res, 1, 1);
}
-void _beamforming_reset(PADAPTER adapter)
+/*
+ * Description:
+ * This function is for phydm only
+ */
+enum beamforming_cap rtw_bf_bfee_get_entry_cap_by_macid(void *mlme, u8 macid)
{
- RTW_ERR("%s: Not ready!!\n", __FUNCTION__);
+ PADAPTER adapter;
+ enum beamforming_cap cap = BEAMFORMING_CAP_NONE;
+
+
+ adapter = mlme_to_adapter((struct mlme_priv *)mlme);
+ cap = _bfee_get_entry_cap_by_macid(adapter, macid);
+
+ return cap;
}
-void beamforming_enter(PADAPTER adapter, void *sta)
+struct beamformer_entry *rtw_bf_bfer_get_entry_by_addr(PADAPTER adapter, u8 *ra)
{
- u8 ret;
-
- ret = _init_entry(adapter, (struct sta_info *)sta);
- if (ret == _FALSE)
- return;
+ return _bfer_get_entry_by_addr(adapter, ra);
+}
- rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_ENTER, sta);
+struct beamformee_entry *rtw_bf_bfee_get_entry_by_addr(PADAPTER adapter, u8 *ra)
+{
+ return _bfee_get_entry_by_addr(adapter, ra);
}
-void beamforming_leave(PADAPTER adapter, u8 *ra)
+void rtw_bf_get_ndpa_packet(PADAPTER adapter, union recv_frame *precv_frame)
{
- if (ra == NULL)
- _beamforming_reset(adapter);
- else
- _deinit_entry(adapter, ra);
+ RTW_DBG("+%s\n", __FUNCTION__);
}
-void beamforming_sounding_fail(PADAPTER adapter)
+u32 rtw_bf_get_report_packet(PADAPTER adapter, union recv_frame *precv_frame)
{
- RTW_ERR("+%s: not implemented yet!\n", __FUNCTION__);
+ u32 ret = _SUCCESS;
+ struct beamforming_info *info;
+ struct beamformee_entry *bfee = NULL;
+ u8 *pframe;
+ u32 frame_len;
+ u8 *ta;
+ u8 *frame_body;
+ u8 category, action;
+ u8 *pMIMOCtrlField, *pCSIMatrix;
+ u8 Nc = 0, Nr = 0, CH_W = 0, Ng = 0, CodeBook = 0;
+ u16 CSIMatrixLen = 0;
+
+
+ RTW_INFO("+%s\n", __FUNCTION__);
+
+ info = GET_BEAMFORM_INFO(adapter);
+ pframe = precv_frame->u.hdr.rx_data;
+ frame_len = precv_frame->u.hdr.len;
+
+ /* Memory comparison to see if CSI report is the same with previous one */
+ ta = get_addr2_ptr(pframe);
+ bfee = _bfee_get_entry_by_addr(adapter, ta);
+ if (!bfee)
+ return _FAIL;
+
+ frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
+ category = frame_body[0];
+ action = frame_body[1];
+
+ if ((category == RTW_WLAN_CATEGORY_VHT)
+ && (action == RTW_WLAN_ACTION_VHT_COMPRESSED_BEAMFORMING)) {
+ pMIMOCtrlField = pframe + 26;
+ Nc = (*pMIMOCtrlField) & 0x7;
+ Nr = ((*pMIMOCtrlField) & 0x38) >> 3;
+ CH_W = (((*pMIMOCtrlField) & 0xC0) >> 6);
+ Ng = (*(pMIMOCtrlField+1)) & 0x3;
+ CodeBook = ((*(pMIMOCtrlField+1)) & 0x4) >> 2;
+ /*
+ * 24+(1+1+3)+2
+ * ==> MAC header+(Category+ActionCode+MIMOControlField)+SNR(Nc=2)
+ */
+ pCSIMatrix = pMIMOCtrlField + 3 + Nc;
+ CSIMatrixLen = frame_len - 26 - 3 - Nc;
+ info->TargetCSIInfo.bVHT = _TRUE;
+ } else if ((category == RTW_WLAN_CATEGORY_HT)
+ && (action == RTW_WLAN_ACTION_HT_COMPRESS_BEAMFORMING)) {
+ pMIMOCtrlField = pframe + 26;
+ Nc = (*pMIMOCtrlField) & 0x3;
+ Nr = ((*pMIMOCtrlField) & 0xC) >> 2;
+ CH_W = ((*pMIMOCtrlField) & 0x10) >> 4;
+ Ng = ((*pMIMOCtrlField) & 0x60) >> 5;
+ CodeBook = ((*(pMIMOCtrlField+1)) & 0x6) >> 1;
+ /*
+ * 24+(1+1+6)+2
+ * ==> MAC header+(Category+ActionCode+MIMOControlField)+SNR(Nc=2)
+ */
+ pCSIMatrix = pMIMOCtrlField + 6 + Nr;
+ CSIMatrixLen = frame_len - 26 - 6 - Nr;
+ info->TargetCSIInfo.bVHT = _FALSE;
+ }
+
+ /* Update current CSI report info */
+ if ((_TRUE == info->bEnableSUTxBFWorkAround)
+ && (info->TargetSUBFee == bfee)) {
+ if ((info->TargetCSIInfo.Nc != Nc) || (info->TargetCSIInfo.Nr != Nr) ||
+ (info->TargetCSIInfo.ChnlWidth != CH_W) || (info->TargetCSIInfo.Ng != Ng) ||
+ (info->TargetCSIInfo.CodeBook != CodeBook)) {
+ info->TargetCSIInfo.Nc = Nc;
+ info->TargetCSIInfo.Nr = Nr;
+ info->TargetCSIInfo.ChnlWidth = CH_W;
+ info->TargetCSIInfo.Ng = Ng;
+ info->TargetCSIInfo.CodeBook = CodeBook;
+
+ rtw_bf_cmd(adapter, BEAMFORMING_CTRL_SET_CSI_REPORT, (u8*)&info->TargetCSIInfo, sizeof(struct _RT_CSI_INFO), 1);
+ }
+ }
+
+ RTW_INFO("%s: pkt type=%d-%d, Nc=%d, Nr=%d, CH_W=%d, Ng=%d, CodeBook=%d\n",
+ __FUNCTION__, category, action, Nc, Nr, CH_W, Ng, CodeBook);
+
+ return ret;
}
-u8 beamforming_send_vht_gid_mgnt_packet(PADAPTER adapter, struct beamformee_entry *entry)
+u8 rtw_bf_send_vht_gid_mgnt_packet(PADAPTER adapter, u8 *ra, u8 *gid, u8 *position)
{
+ /* General */
struct xmit_priv *xmitpriv;
struct mlme_priv *mlmepriv;
struct xmit_frame *pmgntframe;
+ /* MISC */
struct pkt_attrib *attrib;
struct rtw_ieee80211_hdr *wlanhdr;
- u8 *pframe;
+ u8 *pframe, *ptr;
xmitpriv = &adapter->xmitpriv;
@@ -657,19 +1717,23 @@ u8 beamforming_send_vht_gid_mgnt_packet(PADAPTER adapter, struct beamformee_entr
wlanhdr = (struct rtw_ieee80211_hdr *)pframe;
wlanhdr->frame_ctl = 0;
- SetFrameSubType(pframe, attrib->subtype);
- SetDuration(pframe, 0);
+ set_frame_sub_type(pframe, attrib->subtype);
+ set_duration(pframe, 0);
SetFragNum(pframe, 0);
SetSeqNum(pframe, 0);
- _rtw_memcpy(wlanhdr->addr1, entry->mac_addr, ETH_ALEN);
+ _rtw_memcpy(wlanhdr->addr1, ra, ETH_ALEN);
_rtw_memcpy(wlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN);
_rtw_memcpy(wlanhdr->addr3, get_bssid(mlmepriv), ETH_ALEN);
pframe[24] = RTW_WLAN_CATEGORY_VHT;
pframe[25] = RTW_WLAN_ACTION_VHT_GROUPID_MANAGEMENT;
- _rtw_memcpy(&pframe[26], entry->gid_valid, 8);
- _rtw_memcpy(&pframe[34], entry->user_position, 16);
+ /* Set Membership Status Array */
+ ptr = pframe + 26;
+ _rtw_memcpy(ptr, gid, 8);
+ /* Set User Position Array */
+ ptr = pframe + 34;
+ _rtw_memcpy(ptr, position, 16);
attrib->pktlen = 54;
attrib->last_txcmdsz = attrib->pktlen;
@@ -679,11 +1743,268 @@ u8 beamforming_send_vht_gid_mgnt_packet(PADAPTER adapter, struct beamformee_entr
return _TRUE;
}
-void beamforming_watchdog(PADAPTER adapter)
+/*
+ * Description:
+ * On VHT GID management frame by an MU beamformee.
+ */
+void rtw_bf_get_vht_gid_mgnt_packet(PADAPTER adapter, union recv_frame *precv_frame)
+{
+ u8 *pframe;
+ u8 *ta, *gid, *position;
+
+
+ RTW_DBG("+%s\n", __FUNCTION__);
+
+ pframe = precv_frame->u.hdr.rx_data;
+
+ /* Get address by Addr2 */
+ ta = get_addr2_ptr(pframe);
+ /* Remove signaling TA */
+ ta[0] &= 0xFE;
+
+ /* Membership Status Array */
+ gid = pframe + 26;
+ /* User Position Array */
+ position= pframe + 34;
+
+ _bfer_set_entry_gid(adapter, ta, gid, position);
+}
+
+void rtw_bf_init(PADAPTER adapter)
+{
+ struct beamforming_info *info;
+
+
+ info = GET_BEAMFORM_INFO(adapter);
+ info->beamforming_cap = BEAMFORMING_CAP_NONE;
+ info->beamforming_state = BEAMFORMING_STATE_IDLE;
+/*
+ info->bfee_entry[MAX_BEAMFORMEE_ENTRY_NUM];
+ info->bfer_entry[MAX_BEAMFORMER_ENTRY_NUM];
+*/
+ info->sounding_sequence = 0;
+ info->beamformee_su_cnt = 0;
+ info->beamformer_su_cnt = 0;
+ info->beamformee_su_reg_maping = 0;
+ info->beamformer_su_reg_maping = 0;
+ info->beamformee_mu_cnt = 0;
+ info->beamformer_mu_cnt = 0;
+ info->beamformee_mu_reg_maping = 0;
+ info->first_mu_bfee_index = 0xFF;
+ info->mu_bfer_curidx = 0xFF;
+ info->cur_csi_rpt_rate = HALMAC_OFDM24;
+
+ _sounding_init(&info->sounding_info);
+ rtw_init_timer(&info->sounding_timer, adapter, _sounding_timer_handler, adapter);
+ rtw_init_timer(&info->sounding_timeout_timer, adapter, _sounding_timeout_timer_handler, adapter);
+
+ info->SetHalBFEnterOnDemandCnt = 0;
+ info->SetHalBFLeaveOnDemandCnt = 0;
+ info->SetHalSoundownOnDemandCnt = 0;
+
+ info->bEnableSUTxBFWorkAround = _TRUE;
+ info->TargetSUBFee = NULL;
+
+ info->sounding_running = 0;
+}
+
+void rtw_bf_cmd_hdl(PADAPTER adapter, u8 type, u8 *pbuf)
+{
+ switch (type) {
+ case BEAMFORMING_CTRL_ENTER:
+ _beamforming_enter(adapter, pbuf);
+ break;
+
+ case BEAMFORMING_CTRL_LEAVE:
+ if (pbuf == NULL)
+ _beamforming_reset(adapter);
+ else
+ _beamforming_leave(adapter, pbuf);
+ break;
+
+ case BEAMFORMING_CTRL_START_PERIOD:
+ _sounding_handler(adapter);
+ break;
+
+ case BEAMFORMING_CTRL_END_PERIOD:
+ _beamforming_sounding_down(adapter, *pbuf);
+ break;
+
+ case BEAMFORMING_CTRL_SET_GID_TABLE:
+ rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_SET_GID_TABLE, pbuf);
+ break;
+
+ case BEAMFORMING_CTRL_SET_CSI_REPORT:
+ rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_CSI_REPORT, pbuf);
+ break;
+
+ default:
+ break;
+ }
+}
+
+u8 rtw_bf_cmd(PADAPTER adapter, s32 type, u8 *pbuf, s32 size, u8 enqueue)
+{
+ struct cmd_obj *ph2c;
+ struct drvextra_cmd_parm *pdrvextra_cmd_parm;
+ struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
+ u8 *wk_buf;
+ u8 res = _SUCCESS;
+
+
+ if (!enqueue) {
+ rtw_bf_cmd_hdl(adapter, type, pbuf);
+ goto exit;
+ }
+
+ ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+ if (ph2c == NULL) {
+ res = _FAIL;
+ goto exit;
+ }
+
+ pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+ if (pdrvextra_cmd_parm == NULL) {
+ rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj));
+ res = _FAIL;
+ goto exit;
+ }
+
+ if (pbuf != NULL) {
+ wk_buf = rtw_zmalloc(size);
+ if (wk_buf == NULL) {
+ rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));
+ rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));
+ res = _FAIL;
+ goto exit;
+ }
+
+ _rtw_memcpy(wk_buf, pbuf, size);
+ } else {
+ wk_buf = NULL;
+ size = 0;
+ }
+
+ pdrvextra_cmd_parm->ec_id = BEAMFORMING_WK_CID;
+ pdrvextra_cmd_parm->type = type;
+ pdrvextra_cmd_parm->size = size;
+ pdrvextra_cmd_parm->pbuf = wk_buf;
+
+ init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
+
+ res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+
+exit:
+ return res;
+}
+
+void rtw_bf_update_attrib(PADAPTER adapter, struct pkt_attrib *attrib, struct sta_info *sta)
+{
+ if (sta) {
+ attrib->txbf_g_id = sta->cmn.bf_info.g_id;
+ attrib->txbf_p_aid = sta->cmn.bf_info.p_aid;
+ }
+}
+
+void rtw_bf_c2h_handler(PADAPTER adapter, u8 id, u8 *buf, u8 buf_len)
+{
+ switch (id) {
+ case CMD_ID_C2H_SND_TXBF:
+ _c2h_snd_txbf(adapter, buf, buf_len);
+ break;
+ }
+}
+
+#define toMbps(bytes, secs) (rtw_division64(bytes >> 17, secs))
+void rtw_bf_update_traffic(PADAPTER adapter)
{
+ struct beamforming_info *info;
+ struct sounding_info *sounding;
+ struct beamformee_entry *bfee;
+ struct sta_info *sta;
+ u8 bfee_cnt, sounding_idx, i;
+ u16 tp[MAX_BEAMFORMEE_ENTRY_NUM] = {0};
+ u8 tx_rate[MAX_BEAMFORMEE_ENTRY_NUM] = {0};
+ u64 tx_bytes, last_bytes;
+ u32 time;
+ systime last_timestamp;
+ u8 set_timer = _FALSE;
+
+
+ info = GET_BEAMFORM_INFO(adapter);
+ sounding = &info->sounding_info;
+
+ /* Check any bfee exist? */
+ bfee_cnt = info->beamformee_su_cnt + info->beamformee_mu_cnt;
+ if (bfee_cnt == 0)
+ return;
+
+ for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {
+ bfee = &info->bfee_entry[i];
+ if (_FALSE == bfee->used)
+ continue;
+
+ sta = rtw_get_stainfo(&adapter->stapriv, bfee->mac_addr);
+ if (!sta) {
+ RTW_ERR("%s: Cann't find sta_info for " MAC_FMT "!\n", __FUNCTION__, MAC_ARG(bfee->mac_addr));
+ continue;
+ }
+
+ last_timestamp = bfee->tx_timestamp;
+ last_bytes = bfee->tx_bytes;
+ bfee->tx_timestamp = rtw_get_current_time();
+ bfee->tx_bytes = sta->sta_stats.tx_bytes;
+ if (last_timestamp) {
+ if (bfee->tx_bytes >= last_bytes)
+ tx_bytes = bfee->tx_bytes - last_bytes;
+ else
+ tx_bytes = bfee->tx_bytes + (~last_bytes);
+ time = rtw_get_time_interval_ms(last_timestamp, bfee->tx_timestamp);
+ time = (time > 1000) ? time/1000 : 1;
+ tp[i] = toMbps(tx_bytes, time);
+ tx_rate[i] = rtw_get_current_tx_rate(adapter, sta);
+ RTW_INFO("%s: BFee idx(%d), MadId(%d), TxTP=%lld bytes (%d Mbps), txrate=%d\n",
+ __FUNCTION__, i, bfee->mac_id, tx_bytes, tp[i], tx_rate[i]);
+ }
+ }
+
+ sounding_idx = phydm_get_beamforming_sounding_info(GET_PDM_ODM(adapter), tp, MAX_BEAMFORMEE_ENTRY_NUM, tx_rate);
+
+ for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {
+ bfee = &info->bfee_entry[i];
+ if (_FALSE == bfee->used) {
+ if (sounding_idx & BIT(i))
+ RTW_WARN("%s: bfee(%d) not in used but need sounding?!\n", __FUNCTION__, i);
+ continue;
+ }
+
+ if (sounding_idx & BIT(i)) {
+ if (_FALSE == bfee->bApplySounding) {
+ bfee->bApplySounding = _TRUE;
+ bfee->SoundCnt = 0;
+ set_timer = _TRUE;
+ }
+ } else {
+ if (_TRUE == bfee->bApplySounding) {
+ bfee->bApplySounding = _FALSE;
+ bfee->bDeleteSounding = _TRUE;
+ bfee->SoundCnt = 0;
+ set_timer = _TRUE;
+ }
+ }
+ }
+
+ if (_TRUE == set_timer) {
+ if (SOUNDING_STATE_NONE == info->sounding_info.state) {
+ info->sounding_info.state = SOUNDING_STATE_INIT;
+ _set_timer(&info->sounding_timer, 0);
+ }
+ }
}
+
#else /* !RTW_BEAMFORMING_VERSION_2 */
+#if (BEAMFORMING_SUPPORT == 0) /*for diver defined beamforming*/
struct beamforming_entry *beamforming_get_entry_by_addr(struct mlme_priv *pmlmepriv, u8 *ra, u8 *idx)
{
u8 i = 0;
@@ -733,7 +2054,7 @@ struct beamforming_entry *beamforming_get_free_entry(struct mlme_priv *pmlmepriv
struct beamforming_entry *beamforming_add_entry(PADAPTER adapter, u8 *ra, u16 aid,
- u16 mac_id, CHANNEL_WIDTH bw, BEAMFORMING_CAP beamfrom_cap, u8 *idx)
+ u16 mac_id, enum channel_width bw, BEAMFORMING_CAP beamfrom_cap, u8 *idx)
{
struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
struct beamforming_entry *pEntry = beamforming_get_free_entry(pmlmepriv, idx);
@@ -795,8 +2116,10 @@ void beamforming_dym_ndpa_rate(PADAPTER adapter)
{
u16 NDPARate = MGN_6M;
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
+ s8 min_rssi = 0;
- if (pHalData->MinUndecoratedPWDBForDM > 30) /* link RSSI > 30% */
+ min_rssi = rtw_phydm_get_min_rssi(adapter);
+ if (min_rssi > 30) /* link RSSI > 30% */
NDPARate = MGN_24M;
else
NDPARate = MGN_6M;
@@ -849,7 +2172,7 @@ void beamforming_dym_period(PADAPTER Adapter)
rtw_hal_set_hwreg(Adapter, HW_VAR_SOUNDING_FW_NDPA, (u8 *)&Idx);
}
-BOOLEAN issue_ht_sw_ndpa_packet(PADAPTER Adapter, u8 *ra, CHANNEL_WIDTH bw, u8 qidx)
+BOOLEAN issue_ht_sw_ndpa_packet(PADAPTER Adapter, u8 *ra, enum channel_width bw, u8 qidx)
{
struct xmit_frame *pmgntframe;
struct pkt_attrib *pattrib;
@@ -891,8 +2214,8 @@ BOOLEAN issue_ht_sw_ndpa_packet(PADAPTER Adapter, u8 *ra, CHANNEL_WIDTH bw, u8 q
fctrl = &pwlanhdr->frame_ctl;
*(fctrl) = 0;
- SetOrderBit(pframe);
- SetFrameSubType(pframe, WIFI_ACTION_NOACK);
+ set_order_bit(pframe);
+ set_frame_sub_type(pframe, WIFI_ACTION_NOACK);
_rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN);
_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(Adapter), ETH_ALEN);
@@ -910,7 +2233,7 @@ BOOLEAN issue_ht_sw_ndpa_packet(PADAPTER Adapter, u8 *ra, CHANNEL_WIDTH bw, u8 q
else
duration += 180;
- SetDuration(pframe, duration);
+ set_duration(pframe, duration);
/*HT control field*/
SET_HT_CTRL_CSI_STEERING(pframe + 24, 3);
@@ -928,7 +2251,7 @@ BOOLEAN issue_ht_sw_ndpa_packet(PADAPTER Adapter, u8 *ra, CHANNEL_WIDTH bw, u8 q
}
-BOOLEAN issue_ht_ndpa_packet(PADAPTER Adapter, u8 *ra, CHANNEL_WIDTH bw, u8 qidx)
+BOOLEAN issue_ht_ndpa_packet(PADAPTER Adapter, u8 *ra, enum channel_width bw, u8 qidx)
{
struct xmit_frame *pmgntframe;
struct pkt_attrib *pattrib;
@@ -967,8 +2290,8 @@ BOOLEAN issue_ht_ndpa_packet(PADAPTER Adapter, u8 *ra, CHANNEL_WIDTH bw, u8 qidx
fctrl = &pwlanhdr->frame_ctl;
*(fctrl) = 0;
- SetOrderBit(pframe);
- SetFrameSubType(pframe, WIFI_ACTION_NOACK);
+ set_order_bit(pframe);
+ set_frame_sub_type(pframe, WIFI_ACTION_NOACK);
_rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN);
_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(Adapter), ETH_ALEN);
@@ -986,7 +2309,7 @@ BOOLEAN issue_ht_ndpa_packet(PADAPTER Adapter, u8 *ra, CHANNEL_WIDTH bw, u8 qidx
else
duration += 180;
- SetDuration(pframe, duration);
+ set_duration(pframe, duration);
/* HT control field */
SET_HT_CTRL_CSI_STEERING(pframe + 24, 3);
@@ -1003,11 +2326,11 @@ BOOLEAN issue_ht_ndpa_packet(PADAPTER Adapter, u8 *ra, CHANNEL_WIDTH bw, u8 qidx
return _TRUE;
}
-BOOLEAN beamforming_send_ht_ndpa_packet(PADAPTER Adapter, u8 *ra, CHANNEL_WIDTH bw, u8 qidx)
+BOOLEAN beamforming_send_ht_ndpa_packet(PADAPTER Adapter, u8 *ra, enum channel_width bw, u8 qidx)
{
return issue_ht_ndpa_packet(Adapter, ra, bw, qidx);
}
-BOOLEAN issue_vht_sw_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, CHANNEL_WIDTH bw, u8 qidx)
+BOOLEAN issue_vht_sw_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, enum channel_width bw, u8 qidx)
{
struct xmit_frame *pmgntframe;
struct pkt_attrib *pattrib;
@@ -1054,12 +2377,12 @@ BOOLEAN issue_vht_sw_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, CHANNEL_WIDT
fctrl = &pwlanhdr->frame_ctl;
*(fctrl) = 0;
- SetFrameSubType(pframe, WIFI_NDPA);
+ set_frame_sub_type(pframe, WIFI_NDPA);
_rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN);
_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(Adapter), ETH_ALEN);
- if (IsSupported5G(pmlmeext->cur_wireless_mode) || IsSupportedHT(pmlmeext->cur_wireless_mode))
+ if (is_supported_5g(pmlmeext->cur_wireless_mode) || is_supported_ht(pmlmeext->cur_wireless_mode))
aSifsTime = 16;
else
aSifsTime = 10;
@@ -1073,7 +2396,7 @@ BOOLEAN issue_vht_sw_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, CHANNEL_WIDT
else
duration += 180;
- SetDuration(pframe, duration);
+ set_duration(pframe, duration);
sequence = pBeamInfo->sounding_sequence << 2;
if (pBeamInfo->sounding_sequence >= 0x3f)
@@ -1101,7 +2424,7 @@ BOOLEAN issue_vht_sw_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, CHANNEL_WIDT
return _TRUE;
}
-BOOLEAN issue_vht_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, CHANNEL_WIDTH bw, u8 qidx)
+BOOLEAN issue_vht_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, enum channel_width bw, u8 qidx)
{
struct xmit_frame *pmgntframe;
struct pkt_attrib *pattrib;
@@ -1140,12 +2463,12 @@ BOOLEAN issue_vht_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, CHANNEL_WIDTH b
fctrl = &pwlanhdr->frame_ctl;
*(fctrl) = 0;
- SetFrameSubType(pframe, WIFI_NDPA);
+ set_frame_sub_type(pframe, WIFI_NDPA);
_rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN);
_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(Adapter), ETH_ALEN);
- if (IsSupported5G(pmlmeext->cur_wireless_mode) || IsSupportedHT(pmlmeext->cur_wireless_mode))
+ if (is_supported_5g(pmlmeext->cur_wireless_mode) || is_supported_ht(pmlmeext->cur_wireless_mode))
aSifsTime = 16;
else
aSifsTime = 10;
@@ -1159,7 +2482,7 @@ BOOLEAN issue_vht_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, CHANNEL_WIDTH b
else
duration += 180;
- SetDuration(pframe, duration);
+ set_duration(pframe, duration);
sequence = pBeamInfo->sounding_sequence << 2;
if (pBeamInfo->sounding_sequence >= 0x3f)
@@ -1187,7 +2510,7 @@ BOOLEAN issue_vht_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, CHANNEL_WIDTH b
return _TRUE;
}
-BOOLEAN beamforming_send_vht_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, CHANNEL_WIDTH bw, u8 qidx)
+BOOLEAN beamforming_send_vht_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, enum channel_width bw, u8 qidx)
{
return issue_vht_ndpa_packet(Adapter, ra, aid, bw, qidx);
}
@@ -1245,9 +2568,9 @@ u16 beamforming_sounding_time(struct beamforming_info *pBeamInfo, SOUNDING_MODE
return sounding_time;
}
-CHANNEL_WIDTH beamforming_sounding_bw(struct beamforming_info *pBeamInfo, SOUNDING_MODE mode, u8 idx)
+enum channel_width beamforming_sounding_bw(struct beamforming_info *pBeamInfo, SOUNDING_MODE mode, u8 idx)
{
- CHANNEL_WIDTH sounding_bw = CHANNEL_WIDTH_20;
+ enum channel_width sounding_bw = CHANNEL_WIDTH_20;
struct beamforming_entry BeamEntry = pBeamInfo->beamforming_entry[idx];
sounding_bw = BeamEntry.sound_bw;
@@ -1384,7 +2707,7 @@ BOOLEAN beamforming_init_entry(PADAPTER adapter, struct sta_info *psta, u8 *idx)
u8 *ra;
u16 aid, mac_id;
u8 wireless_mode;
- CHANNEL_WIDTH bw = CHANNEL_WIDTH_20;
+ enum channel_width bw = CHANNEL_WIDTH_20;
BEAMFORMING_CAP beamform_cap = BEAMFORMING_CAP_NONE;
/* The current setting does not support Beaforming */
@@ -1397,13 +2720,13 @@ BOOLEAN beamforming_init_entry(PADAPTER adapter, struct sta_info *psta, u8 *idx)
return _FALSE;
}
- aid = psta->aid;
- ra = psta->hwaddr;
- mac_id = psta->mac_id;
+ aid = psta->cmn.aid;
+ ra = psta->cmn.mac_addr;
+ mac_id = psta->cmn.mac_id;
wireless_mode = psta->wireless_mode;
- bw = psta->bw_mode;
+ bw = psta->cmn.bw_mode;
- if (IsSupportedHT(wireless_mode) || IsSupportedVHT(wireless_mode)) {
+ if (is_supported_ht(wireless_mode) || is_supported_vht(wireless_mode)) {
/* 3 */ /* HT */
u8 cur_beamform;
@@ -1417,7 +2740,7 @@ BOOLEAN beamforming_init_entry(PADAPTER adapter, struct sta_info *psta, u8 *idx)
if (TEST_FLAG(cur_beamform, BEAMFORMING_HT_BEAMFORMEE_ENABLE))
beamform_cap = (BEAMFORMING_CAP)(beamform_cap | BEAMFORMER_CAP_HT_EXPLICIT);
#ifdef CONFIG_80211AC_VHT
- if (IsSupportedVHT(wireless_mode)) {
+ if (is_supported_vht(wireless_mode)) {
/* 3 */ /* VHT */
cur_beamform = psta->vhtpriv.beamform_cap;
@@ -1453,8 +2776,8 @@ BOOLEAN beamforming_init_entry(PADAPTER adapter, struct sta_info *psta, u8 *idx)
}
pBeamformEntry->beamforming_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED;
- psta->txbf_paid = pBeamformEntry->p_aid;
- psta->txbf_gid = pBeamformEntry->g_id;
+ psta->cmn.bf_info.p_aid = pBeamformEntry->p_aid;
+ psta->cmn.bf_info.g_id = pBeamformEntry->g_id;
RTW_INFO("%s Idx %d\n", __FUNCTION__, *idx);
} else
@@ -1586,73 +2909,18 @@ void beamforming_watchdog(PADAPTER Adapter)
beamforming_dym_period(Adapter);
beamforming_dym_ndpa_rate(Adapter);
}
-#endif /* !RTW_BEAMFORMING_VERSION_2 */
#endif/* #if (BEAMFORMING_SUPPORT ==0) - for diver defined beamforming*/
-u32 beamforming_get_report_frame(PADAPTER Adapter, union recv_frame *precv_frame)
+u32 rtw_beamforming_get_report_frame(PADAPTER Adapter, union recv_frame *precv_frame)
{
u32 ret = _SUCCESS;
#if (BEAMFORMING_SUPPORT == 1)
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
- PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
+ struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
- ret = Beamforming_GetReportFrame(pDM_Odm, precv_frame);
+ ret = beamforming_get_report_frame(pDM_Odm, precv_frame);
#else /*(BEAMFORMING_SUPPORT == 0)- for drv beamfoming*/
-#ifdef RTW_BEAMFORMING_VERSION_2
- struct beamformee_entry *pBeamformEntry = NULL;
- struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
- u8 *pframe = precv_frame->u.hdr.rx_data;
- u32 frame_len = precv_frame->u.hdr.len;
- u8 *ta;
- u8 *frame_body;
- u8 category, action;
- u8 *pMIMOCtrlField, *pCSIMatrix;
- u8 Nc = 0, Nr = 0, CH_W = 0;
- u16 CSIMatrixLen = 0;
-
-
- RTW_DBG("+%s\n", __FUNCTION__);
-
- /* Memory comparison to see if CSI report is the same with previous one */
- ta = GetAddr2Ptr(pframe);
- pBeamformEntry = beamforming_get_bfee_entry_by_addr(Adapter, ta);
- if (!pBeamformEntry)
- return _FAIL;
-
- frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
- category = frame_body[0];
- action = frame_body[1];
-
- if ((category == RTW_WLAN_CATEGORY_VHT)
- && (action == RTW_WLAN_ACTION_VHT_COMPRESSED_BEAMFORMING)) {
- pMIMOCtrlField = pframe + 26;
- Nc = ((*pMIMOCtrlField) & 0x7) + 1;
- Nr = (((*pMIMOCtrlField) & 0x38) >> 3) + 1;
- CH_W = (((*pMIMOCtrlField) & 0xC0) >> 6);
- /*
- * 24+(1+1+3)+2
- * ==> MAC header+(Category+ActionCode+MIMOControlField)+SNR(Nc=2)
- */
- pCSIMatrix = pMIMOCtrlField + 3 + Nc;
- CSIMatrixLen = frame_len - 26 - 3 - Nc;
- } else if ((category == RTW_WLAN_CATEGORY_HT)
- && (action == RTW_WLAN_ACTION_HT_COMPRESS_BEAMFORMING)) {
- pMIMOCtrlField = pframe + 26;
- Nc = ((*pMIMOCtrlField) & 0x3) + 1;
- Nr = (((*pMIMOCtrlField) & 0xC) >> 2) + 1;
- CH_W = ((*pMIMOCtrlField) & 0x10) >> 4;
- /*
- * 24+(1+1+6)+2
- * ==> MAC header+(Category+ActionCode+MIMOControlField)+SNR(Nc=2)
- */
- pCSIMatrix = pMIMOCtrlField + 6 + Nr;
- CSIMatrixLen = frame_len - 26 - 6 - Nr;
- }
-
- RTW_INFO("%s: pkt type=%d-%d, Nc=%d, Nr=%d, CH_W=%d\n",
- __FUNCTION__, category, action, Nc, Nr, CH_W);
-#else /* !RTW_BEAMFORMING_VERSION_2 */
struct beamforming_entry *pBeamformEntry = NULL;
struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv);
u8 *pframe = precv_frame->u.hdr.rx_data;
@@ -1660,10 +2928,10 @@ u32 beamforming_get_report_frame(PADAPTER Adapter, union recv_frame *precv_fram
u8 *ta;
u8 idx, offset;
- /*RTW_INFO("beamforming_get_report_frame\n");*/
+ /*RTW_INFO("rtw_beamforming_get_report_frame\n");*/
/*Memory comparison to see if CSI report is the same with previous one*/
- ta = GetAddr2Ptr(pframe);
+ ta = get_addr2_ptr(pframe);
pBeamformEntry = beamforming_get_entry_by_addr(pmlmepriv, ta, &idx);
if (pBeamformEntry->beamforming_entry_cap & BEAMFORMER_CAP_VHT_SU)
offset = 31; /*24+(1+1+3)+2 MAC header+(Category+ActionCode+MIMOControlField)+SNR(Nc=2)*/
@@ -1687,37 +2955,33 @@ u32 beamforming_get_report_frame(PADAPTER Adapter, union recv_frame *precv_fram
pBeamformEntry->bDefaultCSI = _TRUE;
else
pBeamformEntry->bDefaultCSI = _FALSE;
-#endif /* !RTW_BEAMFORMING_VERSION_2 */
#endif
return ret;
}
-void beamforming_get_ndpa_frame(PADAPTER Adapter, union recv_frame *precv_frame)
+void rtw_beamforming_get_ndpa_frame(PADAPTER Adapter, union recv_frame *precv_frame)
{
#if (BEAMFORMING_SUPPORT == 1)
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
- PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
+ struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
- Beamforming_GetNDPAFrame(pDM_Odm, precv_frame);
+ beamforming_get_ndpa_frame(pDM_Odm, precv_frame);
#else /*(BEAMFORMING_SUPPORT == 0)- for drv beamfoming*/
-#ifdef RTW_BEAMFORMING_VERSION_2
- RTW_DBG("+%s\n", __FUNCTION__);
-#else /* !RTW_BEAMFORMING_VERSION_2 */
u8 *ta;
u8 idx, Sequence;
u8 *pframe = precv_frame->u.hdr.rx_data;
struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv);
struct beamforming_entry *pBeamformEntry = NULL;
- /*RTW_INFO("beamforming_get_ndpa_frame\n");*/
+ /*RTW_INFO("rtw_beamforming_get_ndpa_frame\n");*/
if (IS_HARDWARE_TYPE_8812(Adapter) == _FALSE)
return;
- else if (GetFrameSubType(pframe) != WIFI_NDPA)
+ else if (get_frame_sub_type(pframe) != WIFI_NDPA)
return;
- ta = GetAddr2Ptr(pframe);
+ ta = get_addr2_ptr(pframe);
/*Remove signaling TA. */
ta[0] = ta[0] & 0xFE;
@@ -1764,85 +3028,30 @@ void beamforming_get_ndpa_frame(PADAPTER Adapter, union recv_frame *precv_frame
/*Update LogSeq & PreLogSeq*/
pBeamformEntry->PreLogSeq = pBeamformEntry->LogSeq;
pBeamformEntry->LogSeq = Sequence;
-#endif /* !RTW_BEAMFORMING_VERSION_2 */
+
#endif
}
-/* octets in data header, no WEP */
-#define sMacHdrLng 24
-/* VHT Group ID (GID) Management Frame */
-#define FRAME_OFFSET_VHT_GID_MGNT_MEMBERSHIP_STATUS_ARRAY (sMacHdrLng + 2)
-#define FRAME_OFFSET_VHT_GID_MGNT_USER_POSITION_ARRAY (sMacHdrLng + 10)
-/* VHT GID Management Frame Info */
-#define GET_VHT_GID_MGNT_INFO_MEMBERSHIP_STATUS(_pStart) LE_BITS_TO_1BYTE((_pStart), 0, 8)
-#define GET_VHT_GID_MGNT_INFO_USER_POSITION(_pStart) LE_BITS_TO_1BYTE((_pStart), 0, 8)
-/*
- * Description:
- * On VHT GID management frame by an MU beamformee.
- *
- * 2015.05.20. Created by tynli.
- */
-u32 beamforming_get_vht_gid_mgnt_frame(PADAPTER adapter, union recv_frame *precv_frame)
-{
-#ifdef RTW_BEAMFORMING_VERSION_2
- u8 *ta;
- u8 idx;
- u8 *pframe;
- u8 *pBuffer = NULL;
- struct beamformer_entry *bfer = NULL;
-
-
- RTW_DBG("+%s\n", __FUNCTION__);
-
- pframe = precv_frame->u.hdr.rx_data;
- /* Get BFer entry by Addr2 */
- ta = GetAddr2Ptr(pframe);
- /* Remove signaling TA */
- ta[0] &= 0xFE;
-
- bfer = beamforming_get_bfer_entry_by_addr(adapter, ta);
- if (!bfer) {
- RTW_INFO("%s: Cannot find BFer entry!!\n", __FUNCTION__);
- return _FAIL;
- }
-
- /* Parsing Membership Status Array */
- pBuffer = pframe + FRAME_OFFSET_VHT_GID_MGNT_MEMBERSHIP_STATUS_ARRAY;
- for (idx = 0; idx < 8; idx++)
- bfer->gid_valid[idx] = GET_VHT_GID_MGNT_INFO_MEMBERSHIP_STATUS(pBuffer+idx);
-
- /* Parsing User Position Array */
- pBuffer = pframe + FRAME_OFFSET_VHT_GID_MGNT_USER_POSITION_ARRAY;
- for (idx = 0; idx < 16; idx++)
- bfer->user_position[idx] = GET_VHT_GID_MGNT_INFO_USER_POSITION(pBuffer+idx);
- /* Config HW GID table */
- beamforming_wk_cmd(adapter, BEAMFORMING_CTRL_SET_GID_TABLE, (u8*)&bfer, sizeof(struct beamformer_entry *), 1);
- return _SUCCESS;
-#else /* !RTW_BEAMFORMING_VERSION_2 */
- return _FAIL;
-#endif /* !RTW_BEAMFORMING_VERSION_2 */
-}
void beamforming_wk_hdl(_adapter *padapter, u8 type, u8 *pbuf)
{
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
- PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
- _func_enter_;
+ struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
#if (BEAMFORMING_SUPPORT == 1) /*(BEAMFORMING_SUPPORT == 1)- for PHYDM beamfoming*/
switch (type) {
case BEAMFORMING_CTRL_ENTER: {
struct sta_info *psta = (PVOID)pbuf;
- u16 staIdx = psta->mac_id;
+ u16 staIdx = psta->cmn.mac_id;
- Beamforming_Enter(pDM_Odm, staIdx);
+ beamforming_enter(pDM_Odm, staIdx);
break;
}
case BEAMFORMING_CTRL_LEAVE:
- Beamforming_Leave(pDM_Odm, pbuf);
+ beamforming_leave(pDM_Odm, pbuf);
break;
default:
break;
@@ -1866,15 +3075,10 @@ void beamforming_wk_hdl(_adapter *padapter, u8 type, u8 *pbuf)
rtw_hal_set_hwreg(padapter, HW_VAR_SOUNDING_CLK, NULL);
break;
- case BEAMFORMING_CTRL_SET_GID_TABLE:
- rtw_hal_set_hwreg(padapter, HW_VAR_SOUNDING_SET_GID_TABLE, *(void**)pbuf);
- break;
-
default:
break;
}
#endif
- _func_exit_;
}
u8 beamforming_wk_cmd(_adapter *padapter, s32 type, u8 *pbuf, s32 size, u8 enqueue)
@@ -1882,9 +3086,14 @@ u8 beamforming_wk_cmd(_adapter *padapter, s32 type, u8 *pbuf, s32 size, u8 enque
struct cmd_obj *ph2c;
struct drvextra_cmd_parm *pdrvextra_cmd_parm;
struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
+ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
u8 res = _SUCCESS;
- _func_enter_;
+ /*20170214 ad_hoc mode and mp_mode not support BF*/
+ if ((padapter->registrypriv.mp_mode == 1)
+ || (pmlmeinfo->state == WIFI_FW_ADHOC_STATE))
+ return res;
if (enqueue) {
u8 *wk_buf;
@@ -1930,7 +3139,6 @@ u8 beamforming_wk_cmd(_adapter *padapter, s32 type, u8 *pbuf, s32 size, u8 enque
exit:
- _func_exit_;
return res;
}
@@ -1938,9 +3146,10 @@ u8 beamforming_wk_cmd(_adapter *padapter, s32 type, u8 *pbuf, s32 size, u8 enque
void update_attrib_txbf_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta)
{
if (psta) {
- pattrib->txbf_g_id = psta->txbf_gid;
- pattrib->txbf_p_aid = psta->txbf_paid;
+ pattrib->txbf_g_id = psta->cmn.bf_info.g_id;
+ pattrib->txbf_p_aid = psta->cmn.bf_info.p_aid;
}
}
+#endif /* !RTW_BEAMFORMING_VERSION_2 */
-#endif
+#endif /* CONFIG_BEAMFORMING */
diff --git a/core/rtw_br_ext.c b/core/rtw_br_ext.c
index 8fe3ee4..6509df3 100644
--- a/core/rtw_br_ext.c
+++ b/core/rtw_br_ext.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,14 +11,8 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#define _RTW_BR_EXT_C_
-#include
#ifdef __KERNEL__
#include
diff --git a/core/rtw_bt_mp.c b/core/rtw_bt_mp.c
index ee6f328..9b4fc24 100644
--- a/core/rtw_bt_mp.c
+++ b/core/rtw_bt_mp.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,12 +11,7 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#include
@@ -36,7 +31,7 @@ void MPh2c_timeout_handle(void *FunctionContext)
RTW_INFO("[MPT], MPh2c_timeout_handle\n");
pAdapter = (PADAPTER)FunctionContext;
- pMptCtx = &pAdapter->mppriv.MptCtx;
+ pMptCtx = &pAdapter->mppriv.mpt_ctx;
pMptCtx->bMPh2c_timeout = _TRUE;
@@ -48,7 +43,7 @@ void MPh2c_timeout_handle(void *FunctionContext)
u32 WaitC2Hevent(PADAPTER pAdapter, u8 *C2H_event, u32 delay_time)
{
- PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
+ PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
pMptCtx->bMPh2c_timeout = _FALSE;
if (pAdapter->registrypriv.mp_mode == 0) {
@@ -107,7 +102,7 @@ mptbt_SendH2c(
{
/* KIRQL OldIrql = KeGetCurrentIrql(); */
BT_CTRL_STATUS h2cStatus = BT_STATUS_H2C_SUCCESS;
- PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx);
+ PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx);
u1Byte i;
RTW_INFO("[MPT], mptbt_SendH2c()=========>\n");
@@ -205,7 +200,7 @@ mptbt_BtFwOpCodeProcess(
{
u1Byte H2C_Parameter[6] = {0};
PBT_H2C pH2c = (PBT_H2C)&H2C_Parameter[0];
- PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx);
+ PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx);
PBT_EXT_C2H pExtC2h = (PBT_EXT_C2H)&pMptCtx->c2hBuf[0];
u2Byte paraLen = 0, i;
BT_CTRL_STATUS h2cStatus = BT_STATUS_H2C_SUCCESS, c2hStatus = BT_STATUS_C2H_SUCCESS;
@@ -266,7 +261,7 @@ mptbt_BtReady(
u1Byte retStatus = BT_STATUS_BT_OP_SUCCESS;
u1Byte btOpcode;
u1Byte btOpcodeVer = 0;
- PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx);
+ PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx);
PBT_EXT_C2H pExtC2h = (PBT_EXT_C2H)&pMptCtx->c2hBuf[0];
u1Byte i;
u1Byte btFwVer = 0, bdAddr[6] = {0};
@@ -353,16 +348,16 @@ mptbt_BtReady(
void mptbt_close_WiFiRF(PADAPTER Adapter)
{
- PHY_SetBBReg(Adapter, 0x824, 0xF, 0x0);
- PHY_SetBBReg(Adapter, 0x824, 0x700000, 0x0);
- PHY_SetRFReg(Adapter, RF_PATH_A, 0x0, 0xF0000, 0x0);
+ phy_set_bb_reg(Adapter, 0x824, 0xF, 0x0);
+ phy_set_bb_reg(Adapter, 0x824, 0x700000, 0x0);
+ phy_set_rf_reg(Adapter, RF_PATH_A, 0x0, 0xF0000, 0x0);
}
void mptbt_open_WiFiRF(PADAPTER Adapter)
{
- PHY_SetBBReg(Adapter, 0x824, 0x700000, 0x3);
- PHY_SetBBReg(Adapter, 0x824, 0xF, 0x2);
- PHY_SetRFReg(Adapter, RF_PATH_A, 0x0, 0xF0000, 0x3);
+ phy_set_bb_reg(Adapter, 0x824, 0x700000, 0x3);
+ phy_set_bb_reg(Adapter, 0x824, 0xF, 0x2);
+ phy_set_rf_reg(Adapter, RF_PATH_A, 0x0, 0xF0000, 0x3);
}
u4Byte mptbt_switch_RF(PADAPTER Adapter, u1Byte Enter)
@@ -468,10 +463,10 @@ MPTBT_FwC2hBtMpCtrl(
)
{
u32 i;
- PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx);
+ PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx);
PBT_EXT_C2H pExtC2h = (PBT_EXT_C2H)tmpBuf;
- if (Adapter->bBTFWReady == _FALSE || Adapter->registrypriv.mp_mode == 0) {
+ if (GET_HAL_DATA(Adapter)->bBTFWReady == _FALSE || Adapter->registrypriv.mp_mode == 0) {
/* RTW_INFO("Ignore C2H BT MP Info since not in MP mode\n"); */
return;
}
@@ -537,7 +532,7 @@ mptbt_BtGetGeneral(
IN PBT_RSP_CMD pBtRsp
)
{
- PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx);
+ PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx);
PBT_EXT_C2H pExtC2h = (PBT_EXT_C2H)&pMptCtx->c2hBuf[0];
u1Byte h2cParaBuf[6] = {0};
u1Byte h2cParaLen = 0;
@@ -1512,7 +1507,7 @@ mptbt_BtControlProcess(
{
u1Byte H2C_Parameter[6] = {0};
PBT_H2C pH2c = (PBT_H2C)&H2C_Parameter[0];
- PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx);
+ PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx);
PBT_REQ_CMD pBtReq = (PBT_REQ_CMD)pInBuf;
PBT_RSP_CMD pBtRsp;
u1Byte i;
diff --git a/core/rtw_btcoex.c b/core/rtw_btcoex.c
index 4046bd9..6b33e73 100644
--- a/core/rtw_btcoex.c
+++ b/core/rtw_btcoex.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2013 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2013 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,18 +11,11 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
-#ifdef CONFIG_BT_COEXIST
-
+ *****************************************************************************/
#include
-#include
#include
-
+#ifdef CONFIG_BT_COEXIST
+#include
void rtw_btcoex_Initialize(PADAPTER padapter)
{
@@ -34,6 +27,16 @@ void rtw_btcoex_PowerOnSetting(PADAPTER padapter)
hal_btcoex_PowerOnSetting(padapter);
}
+void rtw_btcoex_AntInfoSetting(PADAPTER padapter)
+{
+ hal_btcoex_AntInfoSetting(padapter);
+}
+
+void rtw_btcoex_PowerOffSetting(PADAPTER padapter)
+{
+ hal_btcoex_PowerOffSetting(padapter);
+}
+
void rtw_btcoex_PreLoadFirmware(PADAPTER padapter)
{
hal_btcoex_PreLoadFirmware(padapter);
@@ -78,12 +81,16 @@ void rtw_btcoex_ScanNotify(PADAPTER padapter, u8 type)
if (_FALSE == pHalData->EEPROMBluetoothCoexist)
return;
-#ifdef CONFIG_CONCURRENT_MODE
if (_FALSE == type) {
+ #ifdef CONFIG_CONCURRENT_MODE
if (rtw_mi_buddy_check_fwstate(padapter, WIFI_SITE_MONITOR))
return;
+ #endif
+
+ if (DEV_MGMT_TX_NUM(adapter_to_dvobj(padapter))
+ || DEV_ROCH_NUM(adapter_to_dvobj(padapter)))
+ return;
}
-#endif
#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
if (pBtMgnt->ExtConfig.bEnableWifiScanNotify)
@@ -210,42 +217,40 @@ void rtw_btcoex_SuspendNotify(PADAPTER padapter, u8 state)
void rtw_btcoex_HaltNotify(PADAPTER padapter)
{
PHAL_DATA_TYPE pHalData;
+ u8 do_halt = 1;
pHalData = GET_HAL_DATA(padapter);
if (_FALSE == pHalData->EEPROMBluetoothCoexist)
- return;
+ do_halt = 0;
if (_FALSE == padapter->bup) {
RTW_INFO(FUNC_ADPT_FMT ": bup=%d Skip!\n",
FUNC_ADPT_ARG(padapter), padapter->bup);
-
- return;
+ do_halt = 0;
}
if (rtw_is_surprise_removed(padapter)) {
RTW_INFO(FUNC_ADPT_FMT ": bSurpriseRemoved=%s Skip!\n",
FUNC_ADPT_ARG(padapter), rtw_is_surprise_removed(padapter) ? "True" : "False");
-
- return;
+ do_halt = 0;
}
- hal_btcoex_HaltNotify(padapter);
+ hal_btcoex_HaltNotify(padapter, do_halt);
}
-void rtw_btcoex_ScoreBoardStatusNotify(PADAPTER padapter, u8 length, u8 *tmpBuf)
+void rtw_btcoex_switchband_notify(u8 under_scan, u8 band_type)
{
- PHAL_DATA_TYPE pHalData;
-
- pHalData = GET_HAL_DATA(padapter);
- if (_FALSE == pHalData->EEPROMBluetoothCoexist)
- return;
+ hal_btcoex_switchband_notify(under_scan, band_type);
+}
- hal_btcoex_ScoreBoardStatusNotify(padapter, length, tmpBuf);
+void rtw_btcoex_WlFwDbgInfoNotify(PADAPTER padapter, u8* tmpBuf, u8 length)
+{
+ hal_btcoex_WlFwDbgInfoNotify(padapter, tmpBuf, length);
}
-void rtw_btcoex_switchband_notify(u8 under_scan, u8 band_type)
+void rtw_btcoex_rx_rate_change_notify(PADAPTER padapter, u8 is_data_frame, u8 rate_id)
{
- hal_btcoex_switchband_notify(under_scan, band_type);
+ hal_btcoex_rx_rate_change_notify(padapter, is_data_frame, rate_id);
}
void rtw_btcoex_SwitchBtTRxMask(PADAPTER padapter)
@@ -272,13 +277,6 @@ void rtw_btcoex_Handler(PADAPTER padapter)
if (_FALSE == pHalData->EEPROMBluetoothCoexist)
return;
-#if defined(CONFIG_CONCURRENT_MODE)
- if (padapter->adapter_type != PRIMARY_ADAPTER)
- return;
-#endif
-
-
-
hal_btcoex_Hanlder(padapter);
}
@@ -392,10 +390,22 @@ void rtw_btcoex_StackUpdateProfileInfo(void)
hal_btcoex_StackUpdateProfileInfo();
}
-void rtw_btcoex_BTOffOnNotify(PADAPTER padapter, u8 bBTON)
+void rtw_btcoex_pta_off_on_notify(PADAPTER padapter, u8 bBTON)
+{
+ hal_btcoex_pta_off_on_notify(padapter, bBTON);
+}
+
+#ifdef CONFIG_RF4CE_COEXIST
+void rtw_btcoex_SetRf4ceLinkState(PADAPTER padapter, u8 state)
+{
+ hal_btcoex_set_rf4ce_link_state(state);
+}
+
+u8 rtw_btcoex_GetRf4ceLinkState(PADAPTER padapter)
{
- hal_btcoex_BTOffOnNotify(padapter, bBTON);
+ return hal_btcoex_get_rf4ce_link_state();
}
+#endif
/* ==================================================
* Below Functions are called by BT-Coex
@@ -418,7 +428,7 @@ void rtw_btcoex_LPS_Enter(PADAPTER padapter)
rtw_set_ps_mode(padapter, PS_MODE_MIN, 0, lpsVal, "BTCOEX");
}
-void rtw_btcoex_LPS_Leave(PADAPTER padapter)
+u8 rtw_btcoex_LPS_Leave(PADAPTER padapter)
{
struct pwrctrl_priv *pwrpriv;
@@ -430,6 +440,8 @@ void rtw_btcoex_LPS_Leave(PADAPTER padapter)
LPS_RF_ON_check(padapter, 100);
pwrpriv->bpower_saving = _FALSE;
}
+
+ return _TRUE;
}
u16 rtw_btcoex_btreg_read(PADAPTER padapter, u8 type, u16 addr, u32 *data)
@@ -474,7 +486,7 @@ u8 rtw_btcoex_get_pg_rfe_type(PADAPTER padapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
- return pHalData->RFEType;
+ return pHalData->rfe_type;
}
u8 rtw_btcoex_is_tfbga_package_type(PADAPTER padapter)
@@ -1354,14 +1366,14 @@ void rtw_btcoex_recvmsgbysocket(void *data)
/* attend ack */
pcoex_info->BT_attend = _TRUE;
RTW_INFO("RX_ATTEND_ACK!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
- rtw_btcoex_BTOffOnNotify(pbtcoexadapter, pcoex_info->BT_attend);
+ rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);
break;
case RX_ATTEND_REQ:
pcoex_info->BT_attend = _TRUE;
RTW_INFO("RX_BT_ATTEND_REQ!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
rtw_btcoex_sendmsgbysocket(pbtcoexadapter, attend_ack, sizeof(attend_ack), _FALSE);
- rtw_btcoex_BTOffOnNotify(pbtcoexadapter, pcoex_info->BT_attend);
+ rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);
break;
case RX_INVITE_REQ:
@@ -1369,21 +1381,21 @@ void rtw_btcoex_recvmsgbysocket(void *data)
pcoex_info->BT_attend = _TRUE;
RTW_INFO("RX_INVITE_REQ!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
rtw_btcoex_sendmsgbysocket(pbtcoexadapter, invite_rsp, sizeof(invite_rsp), _FALSE);
- rtw_btcoex_BTOffOnNotify(pbtcoexadapter, pcoex_info->BT_attend);
+ rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);
break;
case RX_INVITE_RSP:
/*invite rsp*/
pcoex_info->BT_attend = _TRUE;
RTW_INFO("RX_INVITE_RSP!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
- rtw_btcoex_BTOffOnNotify(pbtcoexadapter, pcoex_info->BT_attend);
+ rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);
break;
case RX_LEAVE_ACK:
/* mean BT know wifi will leave */
pcoex_info->BT_attend = _FALSE;
RTW_INFO("RX_LEAVE_ACK!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
- rtw_btcoex_BTOffOnNotify(pbtcoexadapter, pcoex_info->BT_attend);
+ rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);
break;
case RX_BT_LEAVE:
@@ -1391,7 +1403,7 @@ void rtw_btcoex_recvmsgbysocket(void *data)
rtw_btcoex_sendmsgbysocket(pbtcoexadapter, leave_ack, sizeof(leave_ack), _FALSE); /* no ack */
pcoex_info->BT_attend = _FALSE;
RTW_INFO("RX_BT_LEAVE!sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend);
- rtw_btcoex_BTOffOnNotify(pbtcoexadapter, pcoex_info->BT_attend);
+ rtw_btcoex_pta_off_on_notify(pbtcoexadapter, pcoex_info->BT_attend);
break;
default:
@@ -1432,7 +1444,9 @@ u8 rtw_btcoex_sendmsgbysocket(_adapter *padapter, u8 *msg, u8 msg_size, bool for
{
u8 error;
struct msghdr udpmsg;
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0))
mm_segment_t oldfs;
+#endif
struct iovec iov;
struct bt_coex_info *pcoex_info = &padapter->coex_info;
@@ -1462,15 +1476,19 @@ u8 rtw_btcoex_sendmsgbysocket(_adapter *padapter, u8 *msg, u8 msg_size, bool for
udpmsg.msg_control = NULL;
udpmsg.msg_controllen = 0;
udpmsg.msg_flags = MSG_DONTWAIT | MSG_NOSIGNAL;
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0))
oldfs = get_fs();
set_fs(KERNEL_DS);
+#endif
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
error = sock_sendmsg(pcoex_info->udpsock, &udpmsg);
#else
error = sock_sendmsg(pcoex_info->udpsock, &udpmsg, msg_size);
#endif
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0))
set_fs(oldfs);
+#endif
if (error < 0) {
RTW_INFO("Error when sendimg msg, error:%d\n", error);
return _FAIL;
@@ -1560,7 +1578,7 @@ void rtw_btcoex_init_socket(_adapter *padapter)
pbtcoexadapter = padapter;
/* We expect BT is off if BT don't send ack to wifi */
RTW_INFO("We expect BT is off if BT send ack to wifi\n");
- rtw_btcoex_BTOffOnNotify(pbtcoexadapter, _FALSE);
+ rtw_btcoex_pta_off_on_notify(pbtcoexadapter, _FALSE);
if (rtw_btcoex_create_kernel_socket(padapter) == _SUCCESS)
pcoex_info->is_exist = _TRUE;
else {
@@ -1730,3 +1748,22 @@ void rtw_btcoex_SendScanNotify(PADAPTER padapter, u8 scanType)
}
#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
#endif /* CONFIG_BT_COEXIST */
+
+void rtw_btcoex_set_ant_info(PADAPTER padapter)
+{
+#ifdef CONFIG_BT_COEXIST
+ PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter);
+
+ if (hal->EEPROMBluetoothCoexist == _TRUE) {
+ u8 bMacPwrCtrlOn = _FALSE;
+
+ rtw_btcoex_AntInfoSetting(padapter);
+ rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
+ if (bMacPwrCtrlOn == _TRUE)
+ rtw_btcoex_PowerOnSetting(padapter);
+ }
+ else
+#endif
+ rtw_btcoex_wifionly_AntInfoSetting(padapter);
+}
+
diff --git a/core/rtw_btcoex_wifionly.c b/core/rtw_btcoex_wifionly.c
new file mode 100644
index 0000000..e26b3a0
--- /dev/null
+++ b/core/rtw_btcoex_wifionly.c
@@ -0,0 +1,42 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2013 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#include
+#include
+#include
+
+void rtw_btcoex_wifionly_switchband_notify(PADAPTER padapter)
+{
+ hal_btcoex_wifionly_switchband_notify(padapter);
+}
+
+void rtw_btcoex_wifionly_scan_notify(PADAPTER padapter)
+{
+ hal_btcoex_wifionly_scan_notify(padapter);
+}
+
+void rtw_btcoex_wifionly_hw_config(PADAPTER padapter)
+{
+ hal_btcoex_wifionly_hw_config(padapter);
+}
+
+void rtw_btcoex_wifionly_initialize(PADAPTER padapter)
+{
+ hal_btcoex_wifionly_initlizevariables(padapter);
+}
+
+void rtw_btcoex_wifionly_AntInfoSetting(PADAPTER padapter)
+{
+ hal_btcoex_wifionly_AntInfoSetting(padapter);
+}
diff --git a/core/rtw_cmd.c b/core/rtw_cmd.c
index 5dd2286..a783412 100644
--- a/core/rtw_cmd.c
+++ b/core/rtw_cmd.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,12 +11,7 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#define _RTW_CMD_C_
#include
@@ -35,12 +30,10 @@ sint _rtw_init_cmd_priv(struct cmd_priv *pcmdpriv)
{
sint res = _SUCCESS;
- _func_enter_;
_rtw_init_sema(&(pcmdpriv->cmd_queue_sema), 0);
/* _rtw_init_sema(&(pcmdpriv->cmd_done_sema), 0); */
- _rtw_init_sema(&(pcmdpriv->terminate_cmdthread_sema), 0);
-
+ _rtw_init_sema(&(pcmdpriv->start_cmdthread_sema), 0);
_rtw_init_queue(&(pcmdpriv->cmd_queue));
@@ -71,20 +64,72 @@ sint _rtw_init_cmd_priv(struct cmd_priv *pcmdpriv)
_rtw_mutex_init(&pcmdpriv->sctx_mutex);
exit:
- _func_exit_;
return res;
}
#ifdef CONFIG_C2H_WK
- static void c2h_wk_callback(_workitem *work);
-#endif
+static void c2h_wk_callback(_workitem *work)
+{
+ struct evt_priv *evtpriv = container_of(work, struct evt_priv, c2h_wk);
+ _adapter *adapter = container_of(evtpriv, _adapter, evtpriv);
+ u8 *c2h_evt;
+ c2h_id_filter direct_hdl_filter = rtw_hal_c2h_id_handle_directly;
+ u8 id, seq, plen;
+ u8 *payload;
+
+ evtpriv->c2h_wk_alive = _TRUE;
+
+ while (!rtw_cbuf_empty(evtpriv->c2h_queue)) {
+ c2h_evt = (u8 *)rtw_cbuf_pop(evtpriv->c2h_queue);
+ if (c2h_evt != NULL) {
+ /* This C2H event is read, clear it */
+ c2h_evt_clear(adapter);
+ } else {
+ c2h_evt = (u8 *)rtw_malloc(C2H_REG_LEN);
+ if (c2h_evt == NULL) {
+ rtw_warn_on(1);
+ continue;
+ }
+
+ /* This C2H event is not read, read & clear now */
+ if (rtw_hal_c2h_evt_read(adapter, c2h_evt) != _SUCCESS) {
+ rtw_mfree(c2h_evt, C2H_REG_LEN);
+ continue;
+ }
+ }
+
+ /* Special pointer to trigger c2h_evt_clear only */
+ if ((void *)c2h_evt == (void *)evtpriv)
+ continue;
+
+ if (!rtw_hal_c2h_valid(adapter, c2h_evt)
+ || rtw_hal_c2h_reg_hdr_parse(adapter, c2h_evt, &id, &seq, &plen, &payload) != _SUCCESS
+ ) {
+ rtw_mfree(c2h_evt, C2H_REG_LEN);
+ continue;
+ }
+
+ if (direct_hdl_filter(adapter, id, seq, plen, payload) == _TRUE) {
+ /* Handle directly */
+ rtw_hal_c2h_handler(adapter, id, seq, plen, payload);
+ rtw_mfree(c2h_evt, C2H_REG_LEN);
+ } else {
+ /* Enqueue into cmd_thread for others */
+ rtw_c2h_reg_wk_cmd(adapter, c2h_evt);
+ rtw_mfree(c2h_evt, C2H_REG_LEN);
+ }
+ }
+
+ evtpriv->c2h_wk_alive = _FALSE;
+}
+#endif /* CONFIG_C2H_WK */
+
sint _rtw_init_evt_priv(struct evt_priv *pevtpriv)
{
sint res = _SUCCESS;
- _func_enter_;
#ifdef CONFIG_H2CLBK
_rtw_init_sema(&(pevtpriv->lbkevt_done), 0);
@@ -100,7 +145,6 @@ sint _rtw_init_evt_priv(struct evt_priv *pevtpriv)
#ifdef CONFIG_EVENT_THREAD_MODE
_rtw_init_sema(&(pevtpriv->evt_notify), 0);
- _rtw_init_sema(&(pevtpriv->terminate_evtthread_sema), 0);
pevtpriv->evt_allocated_buf = rtw_zmalloc(MAX_EVTSZ + 4);
if (pevtpriv->evt_allocated_buf == NULL) {
@@ -143,21 +187,16 @@ sint _rtw_init_evt_priv(struct evt_priv *pevtpriv)
pevtpriv->c2h_queue = rtw_cbuf_alloc(C2H_QUEUE_MAX_LEN + 1);
#endif
- _func_exit_;
return res;
}
void _rtw_free_evt_priv(struct evt_priv *pevtpriv)
{
- _func_enter_;
- RT_TRACE(_module_rtl871x_cmd_c_, _drv_info_, ("+_rtw_free_evt_priv\n"));
#ifdef CONFIG_EVENT_THREAD_MODE
_rtw_free_sema(&(pevtpriv->evt_notify));
- _rtw_free_sema(&(pevtpriv->terminate_evtthread_sema));
-
if (pevtpriv->evt_allocated_buf)
rtw_mfree(pevtpriv->evt_allocated_buf, MAX_EVTSZ + 4);
@@ -171,28 +210,24 @@ void _rtw_free_evt_priv(struct evt_priv *pevtpriv)
while (!rtw_cbuf_empty(pevtpriv->c2h_queue)) {
void *c2h;
c2h = rtw_cbuf_pop(pevtpriv->c2h_queue);
- if (c2h != NULL
- && c2h != (void *)pevtpriv)
+ if (c2h != NULL && c2h != (void *)pevtpriv)
rtw_mfree(c2h, 16);
}
rtw_cbuf_free(pevtpriv->c2h_queue);
#endif
- RT_TRACE(_module_rtl871x_cmd_c_, _drv_info_, ("-_rtw_free_evt_priv\n"));
- _func_exit_;
}
void _rtw_free_cmd_priv(struct cmd_priv *pcmdpriv)
{
- _func_enter_;
if (pcmdpriv) {
_rtw_spinlock_free(&(pcmdpriv->cmd_queue.lock));
_rtw_free_sema(&(pcmdpriv->cmd_queue_sema));
/* _rtw_free_sema(&(pcmdpriv->cmd_done_sema)); */
- _rtw_free_sema(&(pcmdpriv->terminate_cmdthread_sema));
+ _rtw_free_sema(&(pcmdpriv->start_cmdthread_sema));
if (pcmdpriv->cmd_allocated_buf)
rtw_mfree(pcmdpriv->cmd_allocated_buf, MAX_CMDSZ + CMDBUFF_ALIGN_SZ);
@@ -202,7 +237,6 @@ void _rtw_free_cmd_priv(struct cmd_priv *pcmdpriv)
_rtw_mutex_free(&pcmdpriv->sctx_mutex);
}
- _func_exit_;
}
/*
@@ -215,14 +249,13 @@ ISR/Call-Back functions can't call this sub-function.
*/
#ifdef DBG_CMD_QUEUE
- extern u8 dump_cmd_id;
+extern u8 dump_cmd_id;
#endif
sint _rtw_enqueue_cmd(_queue *queue, struct cmd_obj *obj, bool to_head)
{
_irqL irqL;
- _func_enter_;
if (obj == NULL)
goto exit;
@@ -276,7 +309,6 @@ sint _rtw_enqueue_cmd(_queue *queue, struct cmd_obj *obj, bool to_head)
exit:
- _func_exit_;
return _SUCCESS;
}
@@ -286,7 +318,6 @@ struct cmd_obj *_rtw_dequeue_cmd(_queue *queue)
_irqL irqL;
struct cmd_obj *obj;
- _func_enter_;
/* _enter_critical_bh(&(queue->lock), &irqL); */
_enter_critical(&queue->lock, &irqL);
@@ -338,7 +369,6 @@ struct cmd_obj *_rtw_dequeue_cmd(_queue *queue)
/* _exit_critical_bh(&(queue->lock), &irqL); */
_exit_critical(&queue->lock, &irqL);
- _func_exit_;
return obj;
}
@@ -346,35 +376,25 @@ struct cmd_obj *_rtw_dequeue_cmd(_queue *queue)
u32 rtw_init_cmd_priv(struct cmd_priv *pcmdpriv)
{
u32 res;
- _func_enter_;
res = _rtw_init_cmd_priv(pcmdpriv);
- _func_exit_;
return res;
}
u32 rtw_init_evt_priv(struct evt_priv *pevtpriv)
{
int res;
- _func_enter_;
res = _rtw_init_evt_priv(pevtpriv);
- _func_exit_;
return res;
}
void rtw_free_evt_priv(struct evt_priv *pevtpriv)
{
- _func_enter_;
- RT_TRACE(_module_rtl871x_cmd_c_, _drv_info_, ("rtw_free_evt_priv\n"));
_rtw_free_evt_priv(pevtpriv);
- _func_exit_;
}
void rtw_free_cmd_priv(struct cmd_priv *pcmdpriv)
{
- _func_enter_;
- RT_TRACE(_module_rtl871x_cmd_c_, _drv_info_, ("rtw_free_cmd_priv\n"));
_rtw_free_cmd_priv(pcmdpriv);
- _func_exit_;
}
int rtw_cmd_filter(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj);
@@ -397,15 +417,6 @@ int rtw_cmd_filter(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj)
}
#endif
-#ifndef CONFIG_C2H_PACKET_EN
- /* C2H should be always allowed */
- if (cmd_obj->cmdcode == GEN_CMD_CODE(_Set_Drv_Extra)) {
- struct drvextra_cmd_parm *pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)cmd_obj->parmbuf;
- if (pdrvextra_cmd_parm->ec_id == C2H_WK_CID)
- bAllow = _TRUE;
- }
-#endif
-
if (cmd_obj->cmdcode == GEN_CMD_CODE(_SetChannelPlan))
bAllow = _TRUE;
@@ -433,7 +444,6 @@ u32 rtw_enqueue_cmd(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj)
int res = _FAIL;
PADAPTER padapter = pcmdpriv->padapter;
- _func_enter_;
if (cmd_obj == NULL)
goto exit;
@@ -442,7 +452,7 @@ u32 rtw_enqueue_cmd(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj)
#ifdef CONFIG_CONCURRENT_MODE
/* change pcmdpriv to primary's pcmdpriv */
- if (padapter->adapter_type != PRIMARY_ADAPTER)
+ if (!is_primary_adapter(padapter))
pcmdpriv = &(GET_PRIMARY_ADAPTER(padapter)->cmdpriv);
#endif
@@ -470,7 +480,6 @@ u32 rtw_enqueue_cmd(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj)
exit:
- _func_exit_;
return res;
}
@@ -479,26 +488,21 @@ struct cmd_obj *rtw_dequeue_cmd(struct cmd_priv *pcmdpriv)
{
struct cmd_obj *cmd_obj;
- _func_enter_;
cmd_obj = _rtw_dequeue_cmd(&pcmdpriv->cmd_queue);
- _func_exit_;
return cmd_obj;
}
void rtw_cmd_clr_isr(struct cmd_priv *pcmdpriv)
{
- _func_enter_;
pcmdpriv->cmd_done_cnt++;
/* _rtw_up_sema(&(pcmdpriv->cmd_done_sema)); */
- _func_exit_;
}
void rtw_free_cmd_obj(struct cmd_obj *pcmd)
{
struct drvextra_cmd_parm *extra_parm = NULL;
- _func_enter_;
if (pcmd->parmbuf != NULL) {
/* free parmbuf in cmd_obj */
@@ -514,18 +518,15 @@ void rtw_free_cmd_obj(struct cmd_obj *pcmd)
/* free cmd_obj */
rtw_mfree((unsigned char *)pcmd, sizeof(struct cmd_obj));
- _func_exit_;
}
void rtw_stop_cmd_thread(_adapter *adapter)
{
- if (adapter->cmdThread &&
- ATOMIC_READ(&(adapter->cmdpriv.cmdthd_running)) == _TRUE &&
- adapter->cmdpriv.stop_req == 0) {
- adapter->cmdpriv.stop_req = 1;
+ if (adapter->cmdThread) {
_rtw_up_sema(&adapter->cmdpriv.cmd_queue_sema);
- _rtw_down_sema(&adapter->cmdpriv.terminate_cmdthread_sema);
+ rtw_thread_stop(adapter->cmdThread);
+ adapter->cmdThread = NULL;
}
}
@@ -534,7 +535,7 @@ thread_return rtw_cmd_thread(thread_context context)
u8 ret;
struct cmd_obj *pcmd;
u8 *pcmdbuf, *prspbuf;
- u32 cmd_start_time;
+ systime cmd_start_time;
u32 cmd_process_time;
u8(*cmd_hdl)(_adapter *padapter, u8 *pbuf);
void (*pcmd_callback)(_adapter *dev, struct cmd_obj *pcmd);
@@ -542,18 +543,14 @@ thread_return rtw_cmd_thread(thread_context context)
struct cmd_priv *pcmdpriv = &(padapter->cmdpriv);
struct drvextra_cmd_parm *extra_parm = NULL;
_irqL irqL;
- _func_enter_;
thread_enter("RTW_CMD_THREAD");
pcmdbuf = pcmdpriv->cmd_buf;
prspbuf = pcmdpriv->rsp_buf;
-
- pcmdpriv->stop_req = 0;
ATOMIC_SET(&(pcmdpriv->cmdthd_running), _TRUE);
- _rtw_up_sema(&pcmdpriv->terminate_cmdthread_sema);
+ _rtw_up_sema(&pcmdpriv->start_cmdthread_sema);
- RT_TRACE(_module_rtl871x_cmd_c_, _drv_info_, ("start r871x rtw_cmd_thread !!!!\n"));
while (1) {
if (_rtw_down_sema(&pcmdpriv->cmd_queue_sema) == _FAIL) {
@@ -562,16 +559,10 @@ thread_return rtw_cmd_thread(thread_context context)
}
if (RTW_CANNOT_RUN(padapter)) {
- RTW_PRINT("%s: DriverStopped(%s) SurpriseRemoved(%s) break at line %d\n",
- __func__
- , rtw_is_drv_stopped(padapter) ? "True" : "False"
- , rtw_is_surprise_removed(padapter) ? "True" : "False"
- , __LINE__);
- break;
- }
-
- if (pcmdpriv->stop_req) {
- RTW_PRINT(FUNC_ADPT_FMT" stop_req:%u, break\n", FUNC_ADPT_ARG(padapter), pcmdpriv->stop_req);
+ RTW_DBG(FUNC_ADPT_FMT "- bDriverStopped(%s) bSurpriseRemoved(%s)\n",
+ FUNC_ADPT_ARG(padapter),
+ rtw_is_drv_stopped(padapter) ? "True" : "False",
+ rtw_is_surprise_removed(padapter) ? "True" : "False");
break;
}
@@ -671,8 +662,7 @@ thread_return rtw_cmd_thread(thread_context context)
_enter_critical_mutex(&(pcmd->padapter->cmdpriv.sctx_mutex), NULL);
if (pcmd->sctx) {
if (0)
- RTW_PRINT(FUNC_ADPT_FMT" pcmd->sctx\n",
- FUNC_ADPT_ARG(pcmd->padapter));
+ RTW_PRINT(FUNC_ADPT_FMT" pcmd->sctx\n", FUNC_ADPT_ARG(pcmd->padapter));
if (pcmd->res == H2C_SUCCESS)
rtw_sctx_done(&pcmd->sctx);
else
@@ -691,14 +681,12 @@ thread_return rtw_cmd_thread(thread_context context)
if (pcmd->cmdcode < (sizeof(rtw_cmd_callback) / sizeof(struct _cmd_callback))) {
pcmd_callback = rtw_cmd_callback[pcmd->cmdcode].callback;
if (pcmd_callback == NULL) {
- RT_TRACE(_module_rtl871x_cmd_c_, _drv_info_, ("mlme_cmd_hdl(): pcmd_callback=0x%p, cmdcode=0x%x\n", pcmd_callback, pcmd->cmdcode));
rtw_free_cmd_obj(pcmd);
} else {
/* todo: !!! fill rsp_buf to pcmd->rsp if (pcmd->rsp!=NULL) */
pcmd_callback(pcmd->padapter, pcmd);/* need conider that free cmd_obj in rtw_cmd_callback */
}
} else {
- RT_TRACE(_module_rtl871x_cmd_c_, _drv_err_, ("%s: cmdcode=0x%x callback not defined!\n", __FUNCTION__, pcmd->cmdcode));
rtw_free_cmd_obj(pcmd);
}
@@ -730,15 +718,22 @@ thread_return rtw_cmd_thread(thread_context context)
rtw_mfree(extra_parm->pbuf, extra_parm->size);
}
+ _enter_critical_mutex(&(pcmd->padapter->cmdpriv.sctx_mutex), NULL);
+ if (pcmd->sctx) {
+ if (0)
+ RTW_PRINT(FUNC_ADPT_FMT" pcmd->sctx\n", FUNC_ADPT_ARG(pcmd->padapter));
+ rtw_sctx_done_err(&pcmd->sctx, RTW_SCTX_DONE_CMD_DROP);
+ }
+ _exit_critical_mutex(&(pcmd->padapter->cmdpriv.sctx_mutex), NULL);
+
rtw_free_cmd_obj(pcmd);
} while (1);
- _rtw_up_sema(&pcmdpriv->terminate_cmdthread_sema);
-
- _func_exit_;
+ RTW_INFO(FUNC_ADPT_FMT " Exit\n", FUNC_ADPT_ARG(padapter));
- thread_exit();
+ rtw_thread_wait_stop();
+ return 0;
}
@@ -749,7 +744,6 @@ u32 rtw_enqueue_evt(struct evt_priv *pevtpriv, struct evt_obj *obj)
int res;
_queue *queue = &pevtpriv->evt_queue;
- _func_enter_;
res = _SUCCESS;
@@ -768,7 +762,6 @@ u32 rtw_enqueue_evt(struct evt_priv *pevtpriv, struct evt_obj *obj)
exit:
- _func_exit_;
return res;
}
@@ -778,7 +771,6 @@ struct evt_obj *rtw_dequeue_evt(_queue *queue)
_irqL irqL;
struct evt_obj *pevtobj;
- _func_enter_;
_enter_critical_bh(&queue->lock, &irqL);
@@ -791,29 +783,24 @@ struct evt_obj *rtw_dequeue_evt(_queue *queue)
_exit_critical_bh(&queue->lock, &irqL);
- _func_exit_;
return pevtobj;
}
void rtw_free_evt_obj(struct evt_obj *pevtobj)
{
- _func_enter_;
if (pevtobj->parmbuf)
rtw_mfree((unsigned char *)pevtobj->parmbuf, pevtobj->evtsz);
rtw_mfree((unsigned char *)pevtobj, sizeof(struct evt_obj));
- _func_exit_;
}
void rtw_evt_notify_isr(struct evt_priv *pevtpriv)
{
- _func_enter_;
pevtpriv->evt_done_cnt++;
_rtw_up_sema(&(pevtpriv->evt_notify));
- _func_exit_;
}
#endif
@@ -829,7 +816,6 @@ u8 rtw_setstandby_cmd(_adapter *padapter, uint action)
u8 ret = _SUCCESS;
- _func_enter_;
ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
if (ph2c == NULL) {
@@ -852,18 +838,25 @@ u8 rtw_setstandby_cmd(_adapter *padapter, uint action)
exit:
- _func_exit_;
return ret;
}
+void rtw_init_sitesurvey_parm(_adapter *padapter, struct sitesurvey_parm *pparm)
+{
+ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+
+
+ _rtw_memset(pparm, 0, sizeof(struct sitesurvey_parm));
+ pparm->scan_mode = pmlmepriv->scan_mode;
+}
+
/*
rtw_sitesurvey_cmd(~)
### NOTE:#### (!!!!)
MUST TAKE CARE THAT BEFORE CALLING THIS FUNC, YOU SHOULD HAVE LOCKED pmlmepriv->lock
*/
-u8 rtw_sitesurvey_cmd(_adapter *padapter, NDIS_802_11_SSID *ssid, int ssid_num,
- struct rtw_ieee80211_channel *ch, int ch_num)
+u8 rtw_sitesurvey_cmd(_adapter *padapter, struct sitesurvey_parm *pparm)
{
u8 res = _FAIL;
struct cmd_obj *ph2c;
@@ -874,8 +867,6 @@ u8 rtw_sitesurvey_cmd(_adapter *padapter, NDIS_802_11_SSID *ssid, int ssid_num,
struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
#endif /* CONFIG_P2P */
- _func_enter_;
-
#ifdef CONFIG_LPS
if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_SCAN, 1);
@@ -896,67 +887,30 @@ u8 rtw_sitesurvey_cmd(_adapter *padapter, NDIS_802_11_SSID *ssid, int ssid_num,
return _FAIL;
}
- rtw_free_network_queue(padapter, _FALSE);
+ if (pparm)
+ _rtw_memcpy(psurveyPara, pparm, sizeof(struct sitesurvey_parm));
+ else
+ psurveyPara->scan_mode = pmlmepriv->scan_mode;
- RT_TRACE(_module_rtl871x_cmd_c_, _drv_info_, ("%s: flush network queue\n", __FUNCTION__));
+ rtw_free_network_queue(padapter, _FALSE);
init_h2fwcmd_w_parm_no_rsp(ph2c, psurveyPara, GEN_CMD_CODE(_SiteSurvey));
- /* psurveyPara->bsslimit = 48; */
- psurveyPara->scan_mode = pmlmepriv->scan_mode;
-
- /* prepare ssid list */
- if (ssid) {
- int i;
- for (i = 0; i < ssid_num && i < RTW_SSID_SCAN_AMOUNT; i++) {
- if (ssid[i].SsidLength) {
- _rtw_memcpy(&psurveyPara->ssid[i], &ssid[i], sizeof(NDIS_802_11_SSID));
- psurveyPara->ssid_num++;
- if (0)
- RTW_INFO(FUNC_ADPT_FMT" ssid:(%s, %d)\n", FUNC_ADPT_ARG(padapter),
- psurveyPara->ssid[i].Ssid, psurveyPara->ssid[i].SsidLength);
- }
- }
- }
-
- /* prepare channel list */
- if (ch) {
- int i;
- for (i = 0; i < ch_num && i < RTW_CHANNEL_SCAN_AMOUNT; i++) {
- if (ch[i].hw_value && !(ch[i].flags & RTW_IEEE80211_CHAN_DISABLED)) {
- _rtw_memcpy(&psurveyPara->ch[i], &ch[i], sizeof(struct rtw_ieee80211_channel));
- psurveyPara->ch_num++;
- if (0)
- RTW_INFO(FUNC_ADPT_FMT" ch:%u\n", FUNC_ADPT_ARG(padapter),
- psurveyPara->ch[i].hw_value);
- }
- }
- }
-
set_fwstate(pmlmepriv, _FW_UNDER_SURVEY);
res = rtw_enqueue_cmd(pcmdpriv, ph2c);
if (res == _SUCCESS) {
+ u32 scan_timeout_ms;
pmlmepriv->scan_start_time = rtw_get_current_time();
-
-#ifdef CONFIG_SCAN_BACKOP
- if (rtw_mi_buddy_check_mlmeinfo_state(padapter, WIFI_FW_AP_STATE)) {
- if (IsSupported5G(padapter->registrypriv.wireless_mode)
- && IsSupported24G(padapter->registrypriv.wireless_mode)) /* dual band */
- mlme_set_scan_to_timer(pmlmepriv, CONC_SCANNING_TIMEOUT_DUAL_BAND);
- else /* single band */
- mlme_set_scan_to_timer(pmlmepriv, CONC_SCANNING_TIMEOUT_SINGLE_BAND);
- } else
-#endif /* CONFIG_SCAN_BACKOP */
- mlme_set_scan_to_timer(pmlmepriv, SCANNING_TIMEOUT);
+ scan_timeout_ms = rtw_scan_timeout_decision(padapter);
+ mlme_set_scan_to_timer(pmlmepriv,scan_timeout_ms);
rtw_led_control(padapter, LED_CTL_SITE_SURVEY);
} else
_clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY);
- _func_exit_;
return res;
}
@@ -968,7 +922,6 @@ u8 rtw_setdatarate_cmd(_adapter *padapter, u8 *rateset)
struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
u8 res = _SUCCESS;
- _func_enter_;
ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
if (ph2c == NULL) {
@@ -994,7 +947,6 @@ u8 rtw_setdatarate_cmd(_adapter *padapter, u8 *rateset)
res = rtw_enqueue_cmd(pcmdpriv, ph2c);
exit:
- _func_exit_;
return res;
}
@@ -1006,7 +958,6 @@ u8 rtw_setbasicrate_cmd(_adapter *padapter, u8 *rateset)
struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
u8 res = _SUCCESS;
- _func_enter_;
ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
if (ph2c == NULL) {
@@ -1028,7 +979,6 @@ u8 rtw_setbasicrate_cmd(_adapter *padapter, u8 *rateset)
res = rtw_enqueue_cmd(pcmdpriv, ph2c);
exit:
- _func_exit_;
return res;
}
@@ -1050,7 +1000,6 @@ u8 rtw_setphy_cmd(_adapter *padapter, u8 modem, u8 ch)
* struct registry_priv* pregistry_priv = &padapter->registrypriv; */
u8 res = _SUCCESS;
- _func_enter_;
ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
if (ph2c == NULL) {
@@ -1067,14 +1016,12 @@ u8 rtw_setphy_cmd(_adapter *padapter, u8 modem, u8 ch)
init_h2fwcmd_w_parm_no_rsp(ph2c, psetphypara, _SetPhy_CMD_);
- RT_TRACE(_module_rtl871x_cmd_c_, _drv_info_, ("CH=%d, modem=%d", ch, modem));
psetphypara->modem = modem;
psetphypara->rfchannel = ch;
res = rtw_enqueue_cmd(pcmdpriv, ph2c);
exit:
- _func_exit_;
return res;
}
@@ -1085,7 +1032,6 @@ u8 rtw_getmacreg_cmd(_adapter *padapter, u8 len, u32 addr)
struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
u8 res = _SUCCESS;
- _func_enter_;
ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
if (ph2c == NULL) {
res = _FAIL;
@@ -1107,7 +1053,6 @@ u8 rtw_getmacreg_cmd(_adapter *padapter, u8 len, u32 addr)
res = rtw_enqueue_cmd(pcmdpriv, ph2c);
exit:
- _func_exit_;
return res;
}
@@ -1123,7 +1068,6 @@ u8 rtw_setbbreg_cmd(_adapter *padapter, u8 offset, u8 val)
struct writeBB_parm *pwritebbparm;
struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
u8 res = _SUCCESS;
- _func_enter_;
ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
if (ph2c == NULL) {
res = _FAIL;
@@ -1144,7 +1088,6 @@ u8 rtw_setbbreg_cmd(_adapter *padapter, u8 offset, u8 val)
res = rtw_enqueue_cmd(pcmdpriv, ph2c);
exit:
- _func_exit_;
return res;
}
@@ -1155,7 +1098,6 @@ u8 rtw_getbbreg_cmd(_adapter *padapter, u8 offset, u8 *pval)
struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
u8 res = _SUCCESS;
- _func_enter_;
ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
if (ph2c == NULL) {
res = _FAIL;
@@ -1179,7 +1121,6 @@ u8 rtw_getbbreg_cmd(_adapter *padapter, u8 offset, u8 *pval)
res = rtw_enqueue_cmd(pcmdpriv, ph2c);
exit:
- _func_exit_;
return res;
}
@@ -1189,7 +1130,6 @@ u8 rtw_setrfreg_cmd(_adapter *padapter, u8 offset, u32 val)
struct writeRF_parm *pwriterfparm;
struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
u8 res = _SUCCESS;
- _func_enter_;
ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
if (ph2c == NULL) {
res = _FAIL;
@@ -1210,7 +1150,6 @@ u8 rtw_setrfreg_cmd(_adapter *padapter, u8 offset, u32 val)
res = rtw_enqueue_cmd(pcmdpriv, ph2c);
exit:
- _func_exit_;
return res;
}
@@ -1221,7 +1160,6 @@ u8 rtw_getrfreg_cmd(_adapter *padapter, u8 offset, u8 *pval)
struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
u8 res = _SUCCESS;
- _func_enter_;
ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
if (ph2c == NULL) {
@@ -1249,14 +1187,12 @@ u8 rtw_getrfreg_cmd(_adapter *padapter, u8 offset, u8 *pval)
exit:
- _func_exit_;
return res;
}
void rtw_getbbrfreg_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd)
{
- _func_enter_;
/* rtw_free_cmd_obj(pcmd); */
rtw_mfree((unsigned char *) pcmd->parmbuf, pcmd->cmdsz);
@@ -1266,12 +1202,10 @@ void rtw_getbbrfreg_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd)
if (padapter->registrypriv.mp_mode == 1)
padapter->mppriv.workparam.bcompleted = _TRUE;
#endif
- _func_exit_;
}
void rtw_readtssi_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd)
{
- _func_enter_;
rtw_mfree((unsigned char *) pcmd->parmbuf, pcmd->cmdsz);
rtw_mfree((unsigned char *) pcmd, sizeof(struct cmd_obj));
@@ -1281,7 +1215,6 @@ void rtw_readtssi_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd)
padapter->mppriv.workparam.bcompleted = _TRUE;
#endif
- _func_exit_;
}
static u8 rtw_createbss_cmd(_adapter *adapter, int flags, bool adhoc
@@ -1295,7 +1228,7 @@ static u8 rtw_createbss_cmd(_adapter *adapter, int flags, bool adhoc
u8 res = _SUCCESS;
if (req_ch > 0 && req_bw >= 0 && req_offset >= 0) {
- if (!rtw_chset_is_chbw_valid(adapter->mlmeextpriv.channel_set, req_ch, req_bw, req_offset)) {
+ if (!rtw_chset_is_chbw_valid(adapter_to_chset(adapter), req_ch, req_bw, req_offset)) {
res = _FAIL;
goto exit;
}
@@ -1357,26 +1290,62 @@ static u8 rtw_createbss_cmd(_adapter *adapter, int flags, bool adhoc
inline u8 rtw_create_ibss_cmd(_adapter *adapter, int flags)
{
return rtw_createbss_cmd(adapter, flags
- , 1
- , 0, -1, -1 /* for now, adhoc doesn't support ch,bw,offset request */
- );
+ , 1
+ , 0, REQ_BW_NONE, REQ_OFFSET_NONE /* for now, adhoc doesn't support ch,bw,offset request */
+ );
}
inline u8 rtw_startbss_cmd(_adapter *adapter, int flags)
{
return rtw_createbss_cmd(adapter, flags
- , 0
- , 0, -1, -1 /* excute entire AP setup cmd */
- );
+ , 0
+ , 0, REQ_BW_NONE, REQ_OFFSET_NONE /* excute entire AP setup cmd */
+ );
}
inline u8 rtw_change_bss_chbw_cmd(_adapter *adapter, int flags, s16 req_ch, s8 req_bw, s8 req_offset)
{
return rtw_createbss_cmd(adapter, flags
- , 0
- , req_ch, req_bw, req_offset
- );
+ , 0
+ , req_ch, req_bw, req_offset
+ );
+}
+
+#ifdef CONFIG_RTW_80211R
+static void rtw_ft_validate_akm_type(_adapter *padapter,
+ struct wlan_network *pnetwork)
+{
+ struct security_priv *psecuritypriv = &(padapter->securitypriv);
+ struct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam);
+ u32 tmp_len;
+ u8 *ptmp;
+
+ /*IEEE802.11-2012 Std. Table 8-101¡XAKM suite selectors*/
+ if (rtw_ft_valid_akm(padapter, psecuritypriv->rsn_akm_suite_type)) {
+ ptmp = rtw_get_ie(&pnetwork->network.IEs[12],
+ _MDIE_, &tmp_len, (pnetwork->network.IELength-12));
+ if (ptmp) {
+ pft_roam->mdid = *(u16 *)(ptmp+2);
+ pft_roam->ft_cap = *(ptmp+4);
+
+ RTW_INFO("FT: target " MAC_FMT " mdid=(0x%2x), capacity=(0x%2x)\n",
+ MAC_ARG(pnetwork->network.MacAddress), pft_roam->mdid, pft_roam->ft_cap);
+ rtw_ft_set_flags(padapter, RTW_FT_PEER_EN);
+
+ if (rtw_ft_otd_roam_en(padapter))
+ rtw_ft_set_flags(padapter, RTW_FT_PEER_OTD_EN);
+ } else {
+ /* Don't use FT roaming if target AP cannot support FT */
+ rtw_ft_clr_flags(padapter, (RTW_FT_PEER_EN|RTW_FT_PEER_OTD_EN));
+ rtw_ft_reset_status(padapter);
+ }
+ } else {
+ /* It could be a non-FT connection */
+ rtw_ft_clr_flags(padapter, (RTW_FT_PEER_EN|RTW_FT_PEER_OTD_EN));
+ rtw_ft_reset_status(padapter);
+ }
}
+#endif
u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork)
{
@@ -1398,21 +1367,15 @@ u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork)
NDIS_802_11_NETWORK_INFRASTRUCTURE ndis_network_mode = pnetwork->network.InfrastructureMode;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
u32 tmp_len;
u8 *ptmp = NULL;
- _func_enter_;
rtw_led_control(padapter, LED_CTL_START_TO_LINK);
- if (pmlmepriv->assoc_ssid.SsidLength == 0)
- RT_TRACE(_module_rtl871x_cmd_c_, _drv_info_, ("+Join cmd: Any SSid\n"));
- else
- RT_TRACE(_module_rtl871x_cmd_c_, _drv_notice_, ("+Join cmd: SSid=[%s]\n", pmlmepriv->assoc_ssid.Ssid));
-
pcmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
if (pcmd == NULL) {
res = _FAIL;
- RT_TRACE(_module_rtl871x_cmd_c_, _drv_err_, ("rtw_joinbss_cmd: memory allocate for cmd_obj fail!!!\n"));
goto exit;
}
#if 0
@@ -1439,12 +1402,9 @@ u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork)
set_fwstate(pmlmepriv, WIFI_STATION_STATE);
break;
- case Ndis802_11APMode:
- case Ndis802_11AutoUnknown:
- case Ndis802_11InfrastructureMax:
- case Ndis802_11Monitor:
+ default:
+ rtw_warn_on(1);
break;
-
}
}
@@ -1461,7 +1421,6 @@ u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork)
res = _FAIL;
- RT_TRACE(_module_rtl871x_cmd_c_, _drv_err_, ("rtw_joinbss_cmd :psecnetwork==NULL!!!\n"));
goto exit;
}
@@ -1487,12 +1446,19 @@ u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork)
if (pmlmepriv->assoc_by_bssid == _FALSE)
_rtw_memcpy(&pmlmepriv->assoc_bssid[0], &pnetwork->network.MacAddress[0], ETH_ALEN);
- psecnetwork->IELength = rtw_restruct_sec_ie(padapter, &pnetwork->network.IEs[0], &psecnetwork->IEs[0], pnetwork->network.IELength);
+ /* copy fixed ie */
+ _rtw_memcpy(psecnetwork->IEs, pnetwork->network.IEs, 12);
+ psecnetwork->IELength = 12;
+
+ psecnetwork->IELength += rtw_restruct_sec_ie(padapter, psecnetwork->IEs + psecnetwork->IELength);
pqospriv->qos_option = 0;
if (pregistrypriv->wmm_enable) {
+#ifdef CONFIG_WMMPS_STA
+ rtw_uapsd_use_default_setting(padapter);
+#endif /* CONFIG_WMMPS_STA */
tmp_len = rtw_restruct_wmm_ie(padapter, &pnetwork->network.IEs[0], &psecnetwork->IEs[0], pnetwork->network.IELength, psecnetwork->IELength);
if (psecnetwork->IELength != tmp_len) {
@@ -1515,12 +1481,10 @@ u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork)
(padapter->securitypriv.dot11PrivacyAlgrthm != _TKIP_)) {
rtw_ht_use_default_setting(padapter);
- rtw_build_wmm_ie_ht(padapter, &psecnetwork->IEs[0], &psecnetwork->IELength);
-
/* rtw_restructure_ht_ie */
rtw_restructure_ht_ie(padapter, &pnetwork->network.IEs[12], &psecnetwork->IEs[0],
pnetwork->network.IELength - 12, &psecnetwork->IELength,
- pnetwork->network.Configuration.DSConfig);
+ pnetwork->network.Configuration.DSConfig);
}
}
@@ -1529,7 +1493,7 @@ u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork)
if (phtpriv->ht_option
&& REGSTY_IS_11AC_ENABLE(pregistrypriv)
&& hal_chk_proto_cap(padapter, PROTO_CAP_11AC)
- && (!pmlmepriv->country_ent || COUNTRY_CHPLAN_EN_11AC(pmlmepriv->country_ent))
+ && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent))
) {
rtw_restructure_vht_ie(padapter, &pnetwork->network.IEs[0], &psecnetwork->IEs[0],
pnetwork->network.IELength, &psecnetwork->IELength);
@@ -1540,6 +1504,10 @@ u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork)
#endif /* CONFIG_80211N_HT */
+#ifdef CONFIG_RTW_80211R
+ rtw_ft_validate_akm_type(padapter, pnetwork);
+#endif
+
#if 0
psecuritypriv->supplicant_ie[0] = (u8)psecnetwork->IELength;
@@ -1580,21 +1548,20 @@ u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork)
exit:
- _func_exit_;
return res;
}
-u8 rtw_disassoc_cmd(_adapter *padapter, u32 deauth_timeout_ms, bool enqueue) /* for sta_mode */
+u8 rtw_disassoc_cmd(_adapter *padapter, u32 deauth_timeout_ms, int flags) /* for sta_mode */
{
struct cmd_obj *cmdobj = NULL;
struct disconnect_parm *param = NULL;
struct cmd_priv *cmdpriv = &padapter->cmdpriv;
+ struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
+ struct submit_ctx sctx;
u8 res = _SUCCESS;
- _func_enter_;
- RT_TRACE(_module_rtl871x_cmd_c_, _drv_notice_, ("+rtw_disassoc_cmd\n"));
/* prepare cmd parameter */
param = (struct disconnect_parm *)rtw_zmalloc(sizeof(*param));
@@ -1604,8 +1571,13 @@ u8 rtw_disassoc_cmd(_adapter *padapter, u32 deauth_timeout_ms, bool enqueue) /*
}
param->deauth_timeout_ms = deauth_timeout_ms;
- if (enqueue) {
- /* need enqueue, prepare cmd_obj and enqueue */
+ if (flags & RTW_CMDF_DIRECTLY) {
+ /* no need to enqueue, do the cmd hdl directly and free cmd parameter */
+ if (disconnect_hdl(padapter, (u8 *)param) != H2C_SUCCESS)
+ res = _FAIL;
+ rtw_mfree((u8 *)param, sizeof(*param));
+
+ } else {
cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));
if (cmdobj == NULL) {
res = _FAIL;
@@ -1613,56 +1585,75 @@ u8 rtw_disassoc_cmd(_adapter *padapter, u32 deauth_timeout_ms, bool enqueue) /*
goto exit;
}
init_h2fwcmd_w_parm_no_rsp(cmdobj, param, _DisConnect_CMD_);
+ if (flags & RTW_CMDF_WAIT_ACK) {
+ cmdobj->sctx = &sctx;
+ rtw_sctx_init(&sctx, 2000);
+ }
res = rtw_enqueue_cmd(cmdpriv, cmdobj);
- } else {
- /* no need to enqueue, do the cmd hdl directly and free cmd parameter */
- if (H2C_SUCCESS != disconnect_hdl(padapter, (u8 *)param))
- res = _FAIL;
- rtw_mfree((u8 *)param, sizeof(*param));
+ if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
+ rtw_sctx_wait(&sctx, __func__);
+ _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
+ if (sctx.status == RTW_SCTX_SUBMITTED)
+ cmdobj->sctx = NULL;
+ _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
+ }
}
exit:
- _func_exit_;
return res;
}
-u8 rtw_setopmode_cmd(_adapter *padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype, bool enqueue)
+u8 rtw_setopmode_cmd(_adapter *adapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype, u8 flags)
{
- struct cmd_obj *ph2c;
- struct setopmode_parm *psetop;
-
- struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
- u8 res = _SUCCESS;
-
- _func_enter_;
- psetop = (struct setopmode_parm *)rtw_zmalloc(sizeof(struct setopmode_parm));
+ struct cmd_obj *cmdobj;
+ struct setopmode_parm *parm;
+ struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
+ struct submit_ctx sctx;
+ u8 res = _SUCCESS;
- if (psetop == NULL) {
+ /* prepare cmd parameter */
+ parm = (struct setopmode_parm *)rtw_zmalloc(sizeof(*parm));
+ if (parm == NULL) {
res = _FAIL;
goto exit;
}
- psetop->mode = (u8)networktype;
+ parm->mode = (u8)networktype;
- if (enqueue) {
- ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
- if (ph2c == NULL) {
- rtw_mfree((u8 *)psetop, sizeof(*psetop));
+ if (flags & RTW_CMDF_DIRECTLY) {
+ /* no need to enqueue, do the cmd hdl directly and free cmd parameter */
+ if (H2C_SUCCESS != setopmode_hdl(adapter, (u8 *)parm))
+ res = _FAIL;
+ rtw_mfree((u8 *)parm, sizeof(*parm));
+ } else {
+ /* need enqueue, prepare cmd_obj and enqueue */
+ cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));
+ if (cmdobj == NULL) {
res = _FAIL;
+ rtw_mfree((u8 *)parm, sizeof(*parm));
goto exit;
}
- init_h2fwcmd_w_parm_no_rsp(ph2c, psetop, _SetOpMode_CMD_);
- res = rtw_enqueue_cmd(pcmdpriv, ph2c);
- } else {
- setopmode_hdl(padapter, (u8 *)psetop);
- rtw_mfree((u8 *)psetop, sizeof(*psetop));
- }
-exit:
+ init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, _SetOpMode_CMD_);
+
+ if (flags & RTW_CMDF_WAIT_ACK) {
+ cmdobj->sctx = &sctx;
+ rtw_sctx_init(&sctx, 2000);
+ }
+
+ res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
- _func_exit_;
+ if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
+ rtw_sctx_wait(&sctx, __func__);
+ _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
+ if (sctx.status == RTW_SCTX_SUBMITTED)
+ cmdobj->sctx = NULL;
+ _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
+ }
+ }
+exit:
return res;
}
@@ -1677,7 +1668,6 @@ u8 rtw_setstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 key_type, bool
struct security_priv *psecuritypriv = &padapter->securitypriv;
u8 res = _SUCCESS;
- _func_enter_;
psetstakey_para = (struct set_stakey_parm *)rtw_zmalloc(sizeof(struct set_stakey_parm));
if (psetstakey_para == NULL) {
@@ -1685,16 +1675,17 @@ u8 rtw_setstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 key_type, bool
goto exit;
}
- _rtw_memcpy(psetstakey_para->addr, sta->hwaddr, ETH_ALEN);
+ _rtw_memcpy(psetstakey_para->addr, sta->cmn.mac_addr, ETH_ALEN);
if (check_fwstate(pmlmepriv, WIFI_STATION_STATE))
psetstakey_para->algorithm = (unsigned char) psecuritypriv->dot11PrivacyAlgrthm;
else
GET_ENCRY_ALGO(psecuritypriv, sta, psetstakey_para->algorithm, _FALSE);
- if (key_type == GROUP_KEY)
+ if (key_type == GROUP_KEY) {
_rtw_memcpy(&psetstakey_para->key, &psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey, 16);
- else if (key_type == UNICAST_KEY)
+ psetstakey_para->gk = 1;
+ } else if (key_type == UNICAST_KEY)
_rtw_memcpy(&psetstakey_para->key, &sta->dot118021x_UncstKey, 16);
#ifdef CONFIG_TDLS
else if (key_type == TDLS_KEY) {
@@ -1732,7 +1723,6 @@ u8 rtw_setstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 key_type, bool
}
exit:
- _func_exit_;
return res;
}
@@ -1748,11 +1738,14 @@ u8 rtw_clearstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 enqueue)
s16 cam_id = 0;
u8 res = _SUCCESS;
- _func_enter_;
+ if (!sta) {
+ RTW_ERR("%s sta == NULL\n", __func__);
+ goto exit;
+ }
if (!enqueue) {
- while ((cam_id = rtw_camid_search(padapter, sta->hwaddr, -1, -1)) >= 0) {
- RTW_PRINT("clear key for addr:"MAC_FMT", camid:%d\n", MAC_ARG(sta->hwaddr), cam_id);
+ while ((cam_id = rtw_camid_search(padapter, sta->cmn.mac_addr, -1, -1)) >= 0) {
+ RTW_PRINT("clear key for addr:"MAC_FMT", camid:%d\n", MAC_ARG(sta->cmn.mac_addr), cam_id);
clear_cam_entry(padapter, cam_id);
rtw_camid_free(padapter, cam_id);
}
@@ -1782,7 +1775,7 @@ u8 rtw_clearstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 enqueue)
ph2c->rsp = (u8 *) psetstakey_rsp;
ph2c->rspsz = sizeof(struct set_stakey_rsp);
- _rtw_memcpy(psetstakey_para->addr, sta->hwaddr, ETH_ALEN);
+ _rtw_memcpy(psetstakey_para->addr, sta->cmn.mac_addr, ETH_ALEN);
psetstakey_para->algorithm = _NO_PRIVACY_;
@@ -1792,7 +1785,6 @@ u8 rtw_clearstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 enqueue)
exit:
- _func_exit_;
return res;
}
@@ -1803,7 +1795,6 @@ u8 rtw_setrttbl_cmd(_adapter *padapter, struct setratable_parm *prate_table)
struct setratable_parm *psetrttblparm;
struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
u8 res = _SUCCESS;
- _func_enter_;
ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
if (ph2c == NULL) {
@@ -1824,7 +1815,6 @@ u8 rtw_setrttbl_cmd(_adapter *padapter, struct setratable_parm *prate_table)
res = rtw_enqueue_cmd(pcmdpriv, ph2c);
exit:
- _func_exit_;
return res;
}
@@ -1835,7 +1825,6 @@ u8 rtw_getrttbl_cmd(_adapter *padapter, struct getratable_rsp *pval)
struct getratable_parm *pgetrttblparm;
struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
u8 res = _SUCCESS;
- _func_enter_;
ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
if (ph2c == NULL) {
@@ -1863,7 +1852,6 @@ u8 rtw_getrttbl_cmd(_adapter *padapter, struct getratable_rsp *pval)
res = rtw_enqueue_cmd(pcmdpriv, ph2c);
exit:
- _func_exit_;
return res;
}
@@ -1877,7 +1865,6 @@ u8 rtw_setassocsta_cmd(_adapter *padapter, u8 *mac_addr)
u8 res = _SUCCESS;
- _func_enter_;
ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
if (ph2c == NULL) {
@@ -1909,7 +1896,6 @@ u8 rtw_setassocsta_cmd(_adapter *padapter, u8 *mac_addr)
exit:
- _func_exit_;
return res;
}
@@ -1922,7 +1908,6 @@ u8 rtw_addbareq_cmd(_adapter *padapter, u8 tid, u8 *addr)
u8 res = _SUCCESS;
- _func_enter_;
ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
if (ph2c == NULL) {
@@ -1949,7 +1934,6 @@ u8 rtw_addbareq_cmd(_adapter *padapter, u8 tid, u8 *addr)
exit:
- _func_exit_;
return res;
}
@@ -1961,7 +1945,6 @@ u8 rtw_addbarsp_cmd(_adapter *padapter, u8 *addr, u16 tid, u8 status, u8 size, u
struct addBaRsp_parm *paddBaRsp_parm;
u8 res = _SUCCESS;
- _func_enter_;
ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
if (ph2c == NULL) {
@@ -1989,7 +1972,6 @@ u8 rtw_addbarsp_cmd(_adapter *padapter, u8 *addr, u16 tid, u8 status, u8 size, u
exit:
- _func_exit_;
return res;
}
@@ -2001,7 +1983,6 @@ u8 rtw_reset_securitypriv_cmd(_adapter *padapter)
struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
u8 res = _SUCCESS;
- _func_enter_;
ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
if (ph2c == NULL) {
@@ -2029,7 +2010,6 @@ u8 rtw_reset_securitypriv_cmd(_adapter *padapter)
exit:
- _func_exit_;
return res;
@@ -2042,7 +2022,6 @@ u8 rtw_free_assoc_resources_cmd(_adapter *padapter)
struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
u8 res = _SUCCESS;
- _func_enter_;
ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
if (ph2c == NULL) {
@@ -2070,7 +2049,6 @@ u8 rtw_free_assoc_resources_cmd(_adapter *padapter)
exit:
- _func_exit_;
return res;
@@ -2083,7 +2061,6 @@ u8 rtw_dynamic_chk_wk_cmd(_adapter *padapter)
struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
u8 res = _SUCCESS;
- _func_enter_;
/* only primary padapter does this cmd */
@@ -2112,21 +2089,19 @@ u8 rtw_dynamic_chk_wk_cmd(_adapter *padapter)
exit:
- _func_exit_;
return res;
}
-u8 rtw_set_ch_cmd(_adapter *padapter, u8 ch, u8 bw, u8 ch_offset, u8 enqueue)
+u8 rtw_set_chbw_cmd(_adapter *padapter, u8 ch, u8 bw, u8 ch_offset, u8 flags)
{
struct cmd_obj *pcmdobj;
struct set_ch_parm *set_ch_parm;
struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
-
+ struct submit_ctx sctx;
u8 res = _SUCCESS;
- _func_enter_;
RTW_INFO(FUNC_NDEV_FMT" ch:%u, bw:%u, ch_offset:%u\n",
FUNC_NDEV_ARG(padapter->pnetdev), ch, bw, ch_offset);
@@ -2143,7 +2118,13 @@ u8 rtw_set_ch_cmd(_adapter *padapter, u8 ch, u8 bw, u8 ch_offset, u8 enqueue)
set_ch_parm->bw = bw;
set_ch_parm->ch_offset = ch_offset;
- if (enqueue) {
+ if (flags & RTW_CMDF_DIRECTLY) {
+ /* no need to enqueue, do the cmd hdl directly and free cmd parameter */
+ if (H2C_SUCCESS != rtw_set_chbw_hdl(padapter, (u8 *)set_ch_parm))
+ res = _FAIL;
+
+ rtw_mfree((u8 *)set_ch_parm, sizeof(*set_ch_parm));
+ } else {
/* need enqueue, prepare cmd_obj and enqueue */
pcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
if (pcmdobj == NULL) {
@@ -2153,13 +2134,21 @@ u8 rtw_set_ch_cmd(_adapter *padapter, u8 ch, u8 bw, u8 ch_offset, u8 enqueue)
}
init_h2fwcmd_w_parm_no_rsp(pcmdobj, set_ch_parm, GEN_CMD_CODE(_SetChannel));
+
+ if (flags & RTW_CMDF_WAIT_ACK) {
+ pcmdobj->sctx = &sctx;
+ rtw_sctx_init(&sctx, 10 * 1000);
+ }
+
res = rtw_enqueue_cmd(pcmdpriv, pcmdobj);
- } else {
- /* no need to enqueue, do the cmd hdl directly and free cmd parameter */
- if (H2C_SUCCESS != set_ch_hdl(padapter, (u8 *)set_ch_parm))
- res = _FAIL;
- rtw_mfree((u8 *)set_ch_parm, sizeof(*set_ch_parm));
+ if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
+ rtw_sctx_wait(&sctx, __func__);
+ _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
+ if (sctx.status == RTW_SCTX_SUBMITTED)
+ pcmdobj->sctx = NULL;
+ _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
+ }
}
/* do something based on res... */
@@ -2168,7 +2157,6 @@ u8 rtw_set_ch_cmd(_adapter *padapter, u8 ch, u8 bw, u8 ch_offset, u8 enqueue)
RTW_INFO(FUNC_NDEV_FMT" res:%u\n", FUNC_NDEV_ARG(padapter->pnetdev), res);
- _func_exit_;
return res;
}
@@ -2182,7 +2170,6 @@ u8 _rtw_set_chplan_cmd(_adapter *adapter, int flags, u8 chplan, const struct cou
struct submit_ctx sctx;
u8 res = _SUCCESS;
- _func_enter_;
/* check if allow software config */
if (swconfig && rtw_hal_is_disable_sw_channel_plan(adapter) == _TRUE) {
@@ -2243,7 +2230,6 @@ u8 _rtw_set_chplan_cmd(_adapter *adapter, int flags, u8 chplan, const struct cou
exit:
- _func_exit_;
return res;
}
@@ -2273,7 +2259,7 @@ inline u8 rtw_set_country_cmd(_adapter *adapter, int flags, const char *country_
RTW_PRINT("%s country_code:\"%c%c\" mapping to chplan:0x%02x\n", __func__, country_code[0], country_code[1], ent->chplan);
- return _rtw_set_chplan_cmd(adapter, flags, RTW_CHPLAN_MAX, ent, swconfig);
+ return _rtw_set_chplan_cmd(adapter, flags, RTW_CHPLAN_UNSPECIFIED, ent, swconfig);
}
u8 rtw_led_blink_cmd(_adapter *padapter, PVOID pLed)
@@ -2284,9 +2270,7 @@ u8 rtw_led_blink_cmd(_adapter *padapter, PVOID pLed)
u8 res = _SUCCESS;
- _func_enter_;
- RT_TRACE(_module_rtl871x_cmd_c_, _drv_notice_, ("+rtw_led_blink_cmd\n"));
pcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
if (pcmdobj == NULL) {
@@ -2308,7 +2292,6 @@ u8 rtw_led_blink_cmd(_adapter *padapter, PVOID pLed)
exit:
- _func_exit_;
return res;
}
@@ -2322,9 +2305,7 @@ u8 rtw_set_csa_cmd(_adapter *padapter, u8 new_ch_no)
u8 res = _SUCCESS;
- _func_enter_;
- RT_TRACE(_module_rtl871x_cmd_c_, _drv_notice_, ("+rtw_set_csa_cmd\n"));
pcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
if (pcmdobj == NULL) {
@@ -2346,7 +2327,6 @@ u8 rtw_set_csa_cmd(_adapter *padapter, u8 new_ch_no)
exit:
- _func_exit_;
return res;
}
@@ -2360,11 +2340,9 @@ u8 rtw_tdls_cmd(_adapter *padapter, u8 *addr, u8 option)
u8 res = _SUCCESS;
- _func_enter_;
#ifdef CONFIG_TDLS
- RT_TRACE(_module_rtl871x_cmd_c_, _drv_notice_, ("+rtw_set_tdls_cmd\n"));
pcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
if (pcmdobj == NULL) {
@@ -2392,7 +2370,6 @@ u8 rtw_tdls_cmd(_adapter *padapter, u8 *addr, u8 option)
exit:
- _func_exit_;
return res;
}
@@ -2431,27 +2408,6 @@ u8 rtw_enable_hw_update_tsf_cmd(_adapter *padapter)
return res;
}
-static void collect_traffic_statistics(_adapter *padapter)
-{
- struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
-
-#ifdef CONFIG_CONCURRENT_MODE
- if (padapter->adapter_type != PRIMARY_ADAPTER)
- return;
-#endif
-
- rtw_mi_traffic_statistics(padapter);
-
- /* Calculate throughput in last interval */
- pdvobjpriv->traffic_stat.cur_tx_bytes = pdvobjpriv->traffic_stat.tx_bytes - pdvobjpriv->traffic_stat.last_tx_bytes;
- pdvobjpriv->traffic_stat.cur_rx_bytes = pdvobjpriv->traffic_stat.rx_bytes - pdvobjpriv->traffic_stat.last_rx_bytes;
- pdvobjpriv->traffic_stat.last_tx_bytes = pdvobjpriv->traffic_stat.tx_bytes;
- pdvobjpriv->traffic_stat.last_rx_bytes = pdvobjpriv->traffic_stat.rx_bytes;
-
- pdvobjpriv->traffic_stat.cur_tx_tp = (u32)(pdvobjpriv->traffic_stat.cur_tx_bytes * 8 / 2 / 1024 / 1024);
- pdvobjpriv->traffic_stat.cur_rx_tp = (u32)(pdvobjpriv->traffic_stat.cur_rx_bytes * 8 / 2 / 1024 / 1024);
-}
-
/* from_timer == 1 means driver is in LPS */
u8 traffic_status_watchdog(_adapter *padapter, u8 from_timer)
{
@@ -2483,7 +2439,6 @@ u8 traffic_status_watchdog(_adapter *padapter, u8 from_timer)
}
BusyThreshold = BusyThresholdHigh;
- collect_traffic_statistics(padapter);
/* */
/* Determine if our traffic is busy now */
@@ -2629,7 +2584,9 @@ u8 traffic_status_watchdog(_adapter *padapter, u8 from_timer)
LPS_Leave(padapter, "TRAFFIC_BUSY");
else {
#ifdef CONFIG_CONCURRENT_MODE
+ #ifndef CONFIG_FW_MULTI_PORT_SUPPORT
if (padapter->hw_port == HW_PORT0)
+ #endif
#endif
rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_TRAFFIC_BUSY, 1);
}
@@ -2654,6 +2611,12 @@ u8 traffic_status_watchdog(_adapter *padapter, u8 from_timer)
session_tracker_chk_cmd(padapter, NULL);
+#ifdef CONFIG_BEAMFORMING
+#ifdef RTW_BEAMFORMING_VERSION_2
+ rtw_bf_update_traffic(padapter);
+#endif /* RTW_BEAMFORMING_VERSION_2 */
+#endif /* CONFIG_BEAMFORMING */
+
pmlmepriv->LinkDetectInfo.NumRxOkInPeriod = 0;
pmlmepriv->LinkDetectInfo.NumTxOkInPeriod = 0;
pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod = 0;
@@ -2668,64 +2631,118 @@ u8 traffic_status_watchdog(_adapter *padapter, u8 from_timer)
}
-void dynamic_chk_wk_hdl(_adapter *padapter)
+
+/* for 11n Logo 4.2.31/4.2.32 */
+static void dynamic_update_bcn_check(_adapter *padapter)
{
- struct mlme_priv *pmlmepriv;
- pmlmepriv = &(padapter->mlmepriv);
+ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
-#ifdef CONFIG_AP_MODE
- if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
+ if (!padapter->registrypriv.wifi_spec)
+ return;
+
+ if (!MLME_IS_AP(padapter))
+ return;
+
+ if (pmlmeext->bstart_bss) {
+ /* In 10 * 2 = 20s, there are no legacy AP, update HT info */
+ static u8 count = 1;
+
+ if (count % 10 == 0) {
+ count = 1;
+
+ if (_FALSE == ATOMIC_READ(&pmlmepriv->olbc)
+ && _FALSE == ATOMIC_READ(&pmlmepriv->olbc_ht)) {
+
+ if (rtw_ht_operation_update(padapter) > 0) {
+ update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE);
+ update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE);
+ }
+ }
+ }
+
+ /* In 2s, there are any legacy AP, update HT info, and then reset count */
+
+ if (_FALSE != ATOMIC_READ(&pmlmepriv->olbc)
+ && _FALSE != ATOMIC_READ(&pmlmepriv->olbc_ht)) {
+
+ if (rtw_ht_operation_update(padapter) > 0) {
+ update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE);
+ update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE);
+
+ }
+ ATOMIC_SET(&pmlmepriv->olbc, _FALSE);
+ ATOMIC_SET(&pmlmepriv->olbc_ht, _FALSE);
+ count = 0;
+ }
+
+ count ++;
+ }
+}
+void rtw_iface_dynamic_chk_wk_hdl(_adapter *padapter)
+{
+ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+
+ #ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
+ #ifdef CONFIG_AP_MODE
+ if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {
expire_timeout_chk(padapter);
-#endif
-#endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */
+ #ifdef CONFIG_RTW_MESH
+ if (MLME_IS_MESH(padapter) && MLME_IS_ASOC(padapter))
+ rtw_mesh_peer_status_chk(padapter);
+ #endif
+ }
+ #endif
+ #endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */
+ dynamic_update_bcn_check(padapter);
-#ifdef DBG_CONFIG_ERROR_DETECT
- rtw_hal_sreset_xmit_status_check(padapter);
- rtw_hal_sreset_linked_status_check(padapter);
-#endif
+ linked_status_chk(padapter, 0);
+ traffic_status_watchdog(padapter, 0);
/* for debug purpose */
_linked_info_dump(padapter);
+ #ifdef CONFIG_BEAMFORMING
+ #ifndef RTW_BEAMFORMING_VERSION_2
+ #if (BEAMFORMING_SUPPORT == 0) /*for diver defined beamforming*/
+ beamforming_watchdog(padapter);
+ #endif
+ #endif /* !RTW_BEAMFORMING_VERSION_2 */
+ #endif
+
+}
+void rtw_dynamic_chk_wk_hdl(_adapter *padapter)
+{
+ rtw_mi_dynamic_chk_wk_hdl(padapter);
+
+#ifdef DBG_CONFIG_ERROR_DETECT
+ rtw_hal_sreset_xmit_status_check(padapter);
+ rtw_hal_sreset_linked_status_check(padapter);
+#endif
/* if(check_fwstate(pmlmepriv, _FW_UNDER_LINKING|_FW_UNDER_SURVEY)==_FALSE) */
{
- linked_status_chk(padapter, 0);
- traffic_status_watchdog(padapter, 0);
#ifdef DBG_RX_COUNTER_DUMP
rtw_dump_rx_counters(padapter);
#endif
dm_DynamicUsbTxAgg(padapter, 0);
}
-
-#ifdef CONFIG_BEAMFORMING
-#if (BEAMFORMING_SUPPORT == 0) /*for diver defined beamforming*/
- beamforming_watchdog(padapter);
-#endif
-#endif
-
rtw_hal_dm_watchdog(padapter);
/* check_hw_pbc(padapter, pdrvextra_cmd->pbuf, pdrvextra_cmd->type); */
#ifdef CONFIG_BT_COEXIST
- /* */
/* BT-Coexist */
- /* */
rtw_btcoex_Handler(padapter);
#endif
-
#ifdef CONFIG_IPS_CHECK_IN_WD
/* always call rtw_ps_processor() at last one. */
- if (is_primary_adapter(padapter))
- rtw_ps_processor(padapter);
+ rtw_ps_processor(padapter);
#endif
#ifdef CONFIG_MCC_MODE
- if (is_primary_adapter(padapter))
- rtw_hal_mcc_sw_status_check(padapter);
+ rtw_hal_mcc_sw_status_check(padapter);
#endif /* CONFIG_MCC_MODE */
}
@@ -2739,7 +2756,6 @@ void lps_ctrl_wk_hdl(_adapter *padapter, u8 lps_ctrl_type)
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
u8 mstatus;
- _func_enter_;
if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)
|| (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE))
@@ -2809,7 +2825,6 @@ void lps_ctrl_wk_hdl(_adapter *padapter, u8 lps_ctrl_type)
break;
}
- _func_exit_;
}
u8 rtw_lps_ctrl_wk_cmd(_adapter *padapter, u8 lps_ctrl_type, u8 enqueue)
@@ -2820,7 +2835,6 @@ u8 rtw_lps_ctrl_wk_cmd(_adapter *padapter, u8 lps_ctrl_type, u8 enqueue)
/* struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); */
u8 res = _SUCCESS;
- _func_enter_;
/* if(!pwrctrlpriv->bLeisurePs) */
/* return res; */
@@ -2852,7 +2866,6 @@ u8 rtw_lps_ctrl_wk_cmd(_adapter *padapter, u8 lps_ctrl_type, u8 enqueue)
exit:
- _func_exit_;
return res;
@@ -2860,7 +2873,7 @@ u8 rtw_lps_ctrl_wk_cmd(_adapter *padapter, u8 lps_ctrl_type, u8 enqueue)
void rtw_dm_in_lps_hdl(_adapter *padapter)
{
- rtw_hal_set_hwreg(padapter, HW_VAR_DM_IN_LPS, NULL);
+ rtw_hal_set_hwreg(padapter, HW_VAR_DM_IN_LPS_LCLK, NULL);
}
u8 rtw_dm_in_lps_wk_cmd(_adapter *padapter)
@@ -2994,7 +3007,6 @@ u8 rtw_rpt_timer_cfg_cmd(_adapter *padapter, u16 minRptTime)
u8 res = _SUCCESS;
- _func_enter_;
ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
if (ph2c == NULL) {
res = _FAIL;
@@ -3016,7 +3028,6 @@ u8 rtw_rpt_timer_cfg_cmd(_adapter *padapter, u16 minRptTime)
res = rtw_enqueue_cmd(pcmdpriv, ph2c);
exit:
- _func_exit_;
return res;
@@ -3040,7 +3051,6 @@ u8 rtw_antenna_select_cmd(_adapter *padapter, u8 antenna, u8 enqueue)
u8 res = _SUCCESS;
int i;
- _func_enter_;
rtw_hal_get_def_var(padapter, HAL_DEF_IS_SUPPORT_ANT_DIV, &(bSupportAntDiv));
if (_FALSE == bSupportAntDiv)
return _FAIL;
@@ -3075,7 +3085,6 @@ u8 rtw_antenna_select_cmd(_adapter *padapter, u8 antenna, u8 enqueue)
antenna_select_wk_hdl(padapter, antenna);
exit:
- _func_exit_;
return res;
@@ -3149,7 +3158,6 @@ u8 p2p_protocol_wk_cmd(_adapter *padapter, int intCmdType)
struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
u8 res = _SUCCESS;
- _func_enter_;
if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
return res;
@@ -3178,13 +3186,184 @@ u8 p2p_protocol_wk_cmd(_adapter *padapter, int intCmdType)
exit:
- _func_exit_;
return res;
}
+
+#ifdef CONFIG_IOCTL_CFG80211
+static u8 _p2p_roch_cmd(_adapter *adapter
+ , u64 cookie, struct wireless_dev *wdev
+ , struct ieee80211_channel *ch, enum nl80211_channel_type ch_type
+ , unsigned int duration
+ , u8 flags
+)
+{
+ struct cmd_obj *cmdobj;
+ struct drvextra_cmd_parm *parm;
+ struct p2p_roch_parm *roch_parm;
+ struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
+ struct submit_ctx sctx;
+ u8 cancel = duration ? 0 : 1;
+ u8 res = _SUCCESS;
+
+ roch_parm = (struct p2p_roch_parm *)rtw_zmalloc(sizeof(struct p2p_roch_parm));
+ if (roch_parm == NULL) {
+ res = _FAIL;
+ goto exit;
+ }
+
+ roch_parm->cookie = cookie;
+ roch_parm->wdev = wdev;
+ if (!cancel) {
+ _rtw_memcpy(&roch_parm->ch, ch, sizeof(struct ieee80211_channel));
+ roch_parm->ch_type = ch_type;
+ roch_parm->duration = duration;
+ }
+
+ if (flags & RTW_CMDF_DIRECTLY) {
+ /* no need to enqueue, do the cmd hdl directly and free cmd parameter */
+ if (H2C_SUCCESS != p2p_protocol_wk_hdl(adapter, cancel ? P2P_CANCEL_RO_CH_WK : P2P_RO_CH_WK, (u8 *)roch_parm))
+ res = _FAIL;
+ rtw_mfree((u8 *)roch_parm, sizeof(*roch_parm));
+ } else {
+ /* need enqueue, prepare cmd_obj and enqueue */
+ parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+ if (parm == NULL) {
+ rtw_mfree((u8 *)roch_parm, sizeof(*roch_parm));
+ res = _FAIL;
+ goto exit;
+ }
+
+ parm->ec_id = P2P_PROTO_WK_CID;
+ parm->type = cancel ? P2P_CANCEL_RO_CH_WK : P2P_RO_CH_WK;
+ parm->size = sizeof(*roch_parm);
+ parm->pbuf = (u8 *)roch_parm;
+
+ cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));
+ if (cmdobj == NULL) {
+ res = _FAIL;
+ rtw_mfree((u8 *)roch_parm, sizeof(*roch_parm));
+ rtw_mfree((u8 *)parm, sizeof(*parm));
+ goto exit;
+ }
+
+ init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_Set_Drv_Extra));
+
+ if (flags & RTW_CMDF_WAIT_ACK) {
+ cmdobj->sctx = &sctx;
+ rtw_sctx_init(&sctx, 10 * 1000);
+ }
+
+ res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
+
+ if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
+ rtw_sctx_wait(&sctx, __func__);
+ _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
+ if (sctx.status == RTW_SCTX_SUBMITTED)
+ cmdobj->sctx = NULL;
+ _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
+ if (sctx.status != RTW_SCTX_DONE_SUCCESS)
+ res = _FAIL;
+ }
+ }
+
+exit:
+ return res;
+}
+
+inline u8 p2p_roch_cmd(_adapter *adapter
+ , u64 cookie, struct wireless_dev *wdev
+ , struct ieee80211_channel *ch, enum nl80211_channel_type ch_type
+ , unsigned int duration
+ , u8 flags
+)
+{
+ return _p2p_roch_cmd(adapter, cookie, wdev, ch, ch_type, duration, flags);
+}
+
+inline u8 p2p_cancel_roch_cmd(_adapter *adapter, u64 cookie, struct wireless_dev *wdev, u8 flags)
+{
+ return _p2p_roch_cmd(adapter, cookie, wdev, NULL, 0, 0, flags);
+}
+
+#endif /* CONFIG_IOCTL_CFG80211 */
#endif /* CONFIG_P2P */
+#ifdef CONFIG_IOCTL_CFG80211
+inline u8 rtw_mgnt_tx_cmd(_adapter *adapter, u8 tx_ch, u8 no_cck, const u8 *buf, size_t len, int wait_ack, u8 flags)
+{
+ struct cmd_obj *cmdobj;
+ struct drvextra_cmd_parm *parm;
+ struct mgnt_tx_parm *mgnt_parm;
+ struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
+ struct submit_ctx sctx;
+ u8 res = _SUCCESS;
+
+ mgnt_parm = (struct mgnt_tx_parm *)rtw_zmalloc(sizeof(struct mgnt_tx_parm));
+ if (mgnt_parm == NULL) {
+ res = _FAIL;
+ goto exit;
+ }
+
+ mgnt_parm->tx_ch = tx_ch;
+ mgnt_parm->no_cck = no_cck;
+ mgnt_parm->buf = buf;
+ mgnt_parm->len = len;
+ mgnt_parm->wait_ack = wait_ack;
+
+ if (flags & RTW_CMDF_DIRECTLY) {
+ /* no need to enqueue, do the cmd hdl directly and free cmd parameter */
+ if (H2C_SUCCESS != rtw_mgnt_tx_handler(adapter, (u8 *)mgnt_parm))
+ res = _FAIL;
+ rtw_mfree((u8 *)mgnt_parm, sizeof(*mgnt_parm));
+ } else {
+ /* need enqueue, prepare cmd_obj and enqueue */
+ parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+ if (parm == NULL) {
+ rtw_mfree((u8 *)mgnt_parm, sizeof(*mgnt_parm));
+ res = _FAIL;
+ goto exit;
+ }
+
+ parm->ec_id = MGNT_TX_WK_CID;
+ parm->type = 0;
+ parm->size = sizeof(*mgnt_parm);
+ parm->pbuf = (u8 *)mgnt_parm;
+
+ cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));
+ if (cmdobj == NULL) {
+ res = _FAIL;
+ rtw_mfree((u8 *)mgnt_parm, sizeof(*mgnt_parm));
+ rtw_mfree((u8 *)parm, sizeof(*parm));
+ goto exit;
+ }
+
+ init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_Set_Drv_Extra));
+
+ if (flags & RTW_CMDF_WAIT_ACK) {
+ cmdobj->sctx = &sctx;
+ rtw_sctx_init(&sctx, 10 * 1000);
+ }
+
+ res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
+
+ if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
+ rtw_sctx_wait(&sctx, __func__);
+ _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
+ if (sctx.status == RTW_SCTX_SUBMITTED)
+ cmdobj->sctx = NULL;
+ _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
+ if (sctx.status != RTW_SCTX_DONE_SUCCESS)
+ res = _FAIL;
+ }
+ }
+
+exit:
+ return res;
+}
+#endif
+
u8 rtw_ps_cmd(_adapter *padapter)
{
struct cmd_obj *ppscmd;
@@ -3192,10 +3371,9 @@ u8 rtw_ps_cmd(_adapter *padapter)
struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
u8 res = _SUCCESS;
- _func_enter_;
#ifdef CONFIG_CONCURRENT_MODE
- if (padapter->adapter_type != PRIMARY_ADAPTER)
+ if (!is_primary_adapter(padapter))
goto exit;
#endif
@@ -3222,7 +3400,6 @@ u8 rtw_ps_cmd(_adapter *padapter)
exit:
- _func_exit_;
return res;
@@ -3234,7 +3411,7 @@ static void rtw_chk_hi_queue_hdl(_adapter *padapter)
{
struct sta_info *psta_bmc;
struct sta_priv *pstapriv = &padapter->stapriv;
- u32 start = rtw_get_current_time();
+ systime start = rtw_get_current_time();
u8 empty = _FALSE;
psta_bmc = rtw_get_bcmc_stainfo(padapter);
@@ -3252,11 +3429,11 @@ static void rtw_chk_hi_queue_hdl(_adapter *padapter)
if (empty == _SUCCESS) {
bool update_tim = _FALSE;
- if (pstapriv->tim_bitmap & BIT(0))
+ if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0))
update_tim = _TRUE;
- pstapriv->tim_bitmap &= ~BIT(0);
- pstapriv->sta_dz_bitmap &= ~BIT(0);
+ rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, 0);
+ rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, 0);
if (update_tim == _TRUE)
_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, "bmc sleepq and HIQ empty");
@@ -3305,15 +3482,30 @@ u8 rtw_chk_hi_queue_cmd(_adapter *padapter)
#ifdef CONFIG_DFS_MASTER
u8 rtw_dfs_master_hdl(_adapter *adapter)
{
+ struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
struct mlme_priv *mlme = &adapter->mlmepriv;
+ int i;
if (!rfctl->dfs_master_enabled)
goto exit;
+ for (i = 0; i < dvobj->iface_nums; i++) {
+ if (!dvobj->padapters[i])
+ continue;
+ if (check_fwstate(&dvobj->padapters[i]->mlmepriv, WIFI_AP_STATE | WIFI_MESH_STATE)
+ && check_fwstate(&dvobj->padapters[i]->mlmepriv, WIFI_ASOC_STATE))
+ break;
+ }
+
+ if (i >= dvobj->iface_nums)
+ goto cac_status_chk;
+ else
+ adapter = dvobj->padapters[i];
+
if (rtw_get_on_cur_ch_time(adapter) == 0
- || rtw_get_passing_time_ms(rtw_get_on_cur_ch_time(adapter)) < 300
- ) {
+ || rtw_get_passing_time_ms(rtw_get_on_cur_ch_time(adapter)) < 300
+ ) {
/* offchannel , bypass radar detect */
goto cac_status_chk;
}
@@ -3324,59 +3516,69 @@ u8 rtw_dfs_master_hdl(_adapter *adapter)
}
if (!rfctl->dbg_dfs_master_fake_radar_detect_cnt
- && rtw_odm_radar_detect(adapter) != _TRUE)
+ && rtw_odm_radar_detect(adapter) != _TRUE)
goto cac_status_chk;
- if (rfctl->dbg_dfs_master_fake_radar_detect_cnt != 0) {
- RTW_INFO(FUNC_ADPT_FMT" fake radar detect, cnt:%d\n", FUNC_ADPT_ARG(adapter)
- , rfctl->dbg_dfs_master_fake_radar_detect_cnt);
- rfctl->dbg_dfs_master_fake_radar_detect_cnt--;
+ if (!rfctl->dbg_dfs_master_fake_radar_detect_cnt
+ && rfctl->dbg_dfs_master_radar_detect_trigger_non
+ ) {
+ /* radar detect debug mode, trigger no mlme flow */
+ RTW_INFO(FUNC_ADPT_FMT" radar detected on test mode, trigger no mlme flow\n", FUNC_ADPT_ARG(adapter));
+ goto cac_status_chk;
}
- if (rfctl->dbg_dfs_master_radar_detect_trigger_non) {
- /* radar detect debug mode, trigger no mlme flow */
- if (0)
- RTW_INFO(FUNC_ADPT_FMT" radar detected, trigger no mlme flow for debug\n", FUNC_ADPT_ARG(adapter));
- } else {
- /* TODO: move timer to rfctl */
- struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
- int i;
- for (i = 0; i < dvobj->iface_nums; i++) {
- if (!dvobj->padapters[i])
- continue;
- if (check_fwstate(&dvobj->padapters[i]->mlmepriv, WIFI_AP_STATE)
- && check_fwstate(&dvobj->padapters[i]->mlmepriv, WIFI_ASOC_STATE))
- break;
- }
+ if (rfctl->dbg_dfs_master_fake_radar_detect_cnt != 0) {
+ RTW_INFO(FUNC_ADPT_FMT" fake radar detected, cnt:%d\n", FUNC_ADPT_ARG(adapter)
+ , rfctl->dbg_dfs_master_fake_radar_detect_cnt);
+ rfctl->dbg_dfs_master_fake_radar_detect_cnt--;
+ } else
+ RTW_INFO(FUNC_ADPT_FMT" radar detected\n", FUNC_ADPT_ARG(adapter));
- if (i >= dvobj->iface_nums) {
- /* what? */
- rtw_warn_on(1);
- } else {
- rtw_chset_update_non_ocp(dvobj->padapters[i]->mlmeextpriv.channel_set
- , rfctl->radar_detect_ch, rfctl->radar_detect_bw, rfctl->radar_detect_offset);
- rfctl->radar_detected = 1;
+ rtw_chset_update_non_ocp(rfctl->channel_set
+ , rfctl->radar_detect_ch, rfctl->radar_detect_bw, rfctl->radar_detect_offset);
+ rfctl->radar_detected = 1;
- /* trigger channel selection */
- rtw_change_bss_chbw_cmd(dvobj->padapters[i], RTW_CMDF_DIRECTLY, -1, dvobj->padapters[i]->mlmepriv.ori_bw, -1);
- }
+ /* trigger channel selection */
+ rtw_change_bss_chbw_cmd(adapter, RTW_CMDF_DIRECTLY, -1, adapter->mlmepriv.ori_bw, -1);
- if (rfctl->dfs_master_enabled)
- goto set_timer;
- goto exit;
- }
+ if (rfctl->dfs_master_enabled)
+ goto set_timer;
+ goto exit;
cac_status_chk:
- if (!IS_CH_WAITING(rfctl) && !IS_CAC_STOPPED(rfctl)) {
+ if (!IS_CAC_STOPPED(rfctl)
+ && ((IS_UNDER_CAC(rfctl) && rfctl->cac_force_stop)
+ || !IS_CH_WAITING(rfctl)
+ )
+ ) {
u8 pause = 0x00;
rtw_hal_set_hwreg(adapter, HW_VAR_TXPAUSE, &pause);
rfctl->cac_start_time = rfctl->cac_end_time = RTW_CAC_STOPPED;
+
+ if (rtw_mi_check_fwstate(adapter, WIFI_UNDER_LINKING|WIFI_SITE_MONITOR) == _FALSE) {
+ u8 doiqk = _TRUE;
+ u8 u_ch, u_bw, u_offset;
+
+ rtw_hal_set_hwreg(adapter , HW_VAR_DO_IQK , &doiqk);
+
+ if (rtw_mi_get_ch_setting_union(adapter, &u_ch, &u_bw, &u_offset))
+ set_channel_bwmode(adapter, u_ch, u_offset, u_bw);
+ else
+ rtw_warn_on(1);
+
+ doiqk = _FALSE;
+ rtw_hal_set_hwreg(adapter , HW_VAR_DO_IQK , &doiqk);
+
+ ResumeTxBeacon(adapter);
+ rtw_mi_tx_beacon_hdl(adapter);
+ }
}
set_timer:
+ /* TODO: move timer to rfctl */
_set_timer(&mlme->dfs_master_timer, DFS_MASTER_TIMER_MS);
exit:
@@ -3417,9 +3619,9 @@ u8 rtw_dfs_master_cmd(_adapter *adapter, bool enqueue)
return res;
}
-void rtw_dfs_master_timer_hdl(RTW_TIMER_HDL_ARGS)
+void rtw_dfs_master_timer_hdl(void *ctx)
{
- _adapter *adapter = (_adapter *)FunctionContext;
+ _adapter *adapter = (_adapter *)ctx;
rtw_dfs_master_cmd(adapter, _TRUE);
}
@@ -3443,6 +3645,9 @@ void rtw_dfs_master_enable(_adapter *adapter, u8 ch, u8 bw, u8 offset)
rfctl->radar_detected = 0;
+ if (IS_CH_WAITING(rfctl))
+ StopTxBeacon(adapter);
+
if (!rfctl->dfs_master_enabled) {
RTW_INFO(FUNC_ADPT_FMT" set dfs_master_enabled\n", FUNC_ADPT_ARG(adapter));
rfctl->dfs_master_enabled = 1;
@@ -3481,6 +3686,11 @@ void rtw_dfs_master_disable(_adapter *adapter, u8 ch, u8 bw, u8 offset, bool by_
rfctl->cac_start_time = rfctl->cac_end_time = RTW_CAC_STOPPED;
_cancel_timer_ex(&adapter->mlmepriv.dfs_master_timer);
+ if (rtw_mi_check_fwstate(adapter, WIFI_UNDER_LINKING|WIFI_SITE_MONITOR) == _FALSE) {
+ ResumeTxBeacon(adapter);
+ rtw_mi_tx_beacon_hdl(adapter);
+ }
+
if (overlap_radar_detect_ch) {
u8 pause = 0x00;
@@ -3499,30 +3709,45 @@ void rtw_dfs_master_disable(_adapter *adapter, u8 ch, u8 bw, u8 offset, bool by_
void rtw_dfs_master_status_apply(_adapter *adapter, u8 self_action)
{
struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
- u8 ld_sta_num, lg_sta_num, ap_num;
+ struct mi_state mstate;
u8 u_ch, u_bw, u_offset;
bool ld_sta_in_dfs = _FALSE;
bool sync_ch = _FALSE; /* _FALSE: asign channel directly */
bool needed = _FALSE;
- rtw_mi_status_no_self(adapter, NULL, &ld_sta_num, &lg_sta_num, &ap_num, NULL, NULL);
+ rtw_mi_status_no_self(adapter, &mstate);
rtw_mi_get_ch_setting_union_no_self(adapter, &u_ch, &u_bw, &u_offset);
if (u_ch != 0)
sync_ch = _TRUE;
switch (self_action) {
case MLME_STA_CONNECTING:
- lg_sta_num++;
+ MSTATE_STA_LG_NUM(&mstate)++;
break;
case MLME_STA_CONNECTED:
- ld_sta_num++;
+ MSTATE_STA_LD_NUM(&mstate)++;
+ break;
+ case MLME_STA_DISCONNECTED:
break;
+#ifdef CONFIG_AP_MODE
case MLME_AP_STARTED:
- ap_num++;
+ MSTATE_AP_NUM(&mstate)++;
break;
case MLME_AP_STOPPED:
- case MLME_STA_DISCONNECTED:
+ break;
+#endif
+#ifdef CONFIG_RTW_MESH
+ case MLME_MESH_STARTED:
+ MSTATE_MESH_NUM(&mstate)++;
+ break;
+ case MLME_MESH_STOPPED:
+ break;
+#endif
+ case MLME_ACTION_NONE:
+ /* caller without effect of decision */
+ break;
default:
+ rtw_warn_on(1);
break;
}
@@ -3534,39 +3759,41 @@ void rtw_dfs_master_status_apply(_adapter *adapter, u8 self_action)
}
rtw_sync_chbw(&mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset
- , &u_ch, &u_bw, &u_offset);
+ , &u_ch, &u_bw, &u_offset);
} else {
u_ch = mlmeext->cur_channel;
u_bw = mlmeext->cur_bwmode;
u_offset = mlmeext->cur_ch_offset;
}
- if (ld_sta_num > 0) {
+ if (MSTATE_STA_LD_NUM(&mstate) > 0) {
/* rely on AP on which STA mode connects */
- if (rtw_is_dfs_ch(u_ch, u_bw, u_offset))
+ if (rtw_is_dfs_chbw(u_ch, u_bw, u_offset))
ld_sta_in_dfs = _TRUE;
goto apply;
}
- if (lg_sta_num > 0) {
+ if (MSTATE_STA_LG_NUM(&mstate) > 0) {
/* STA mode is linking */
goto apply;
}
- if (ap_num == 0) {
- /* No working AP mode */
+ if (!MSTATE_AP_NUM(&mstate) && !MSTATE_MESH_NUM(&mstate)) {
+ /* No working AP/Mesh mode */
goto apply;
}
- if (rtw_is_dfs_ch(u_ch, u_bw, u_offset))
+ if (rtw_is_dfs_chbw(u_ch, u_bw, u_offset))
needed = _TRUE;
apply:
RTW_INFO(FUNC_ADPT_FMT" needed:%d, self_action:%u\n"
- , FUNC_ADPT_ARG(adapter), needed, self_action);
- RTW_INFO(FUNC_ADPT_FMT" ld_sta_num:%u, lg_sta_num:%u, ap_num:%u, %u,%u,%u\n"
- , FUNC_ADPT_ARG(adapter), ld_sta_num, lg_sta_num, ap_num, u_ch, u_bw, u_offset);
+ , FUNC_ADPT_ARG(adapter), needed, self_action);
+ RTW_INFO(FUNC_ADPT_FMT" ld_sta_num:%u, lg_sta_num:%u, ap_num:%u, mesh_num:%u, %u,%u,%u\n"
+ , FUNC_ADPT_ARG(adapter), MSTATE_STA_LD_NUM(&mstate), MSTATE_STA_LG_NUM(&mstate)
+ , MSTATE_AP_NUM(&mstate), MSTATE_MESH_NUM(&mstate)
+ , u_ch, u_bw, u_offset);
if (needed == _TRUE)
rtw_dfs_master_enable(adapter, u_ch, u_bw, u_offset);
@@ -3774,60 +4001,254 @@ u8 rtw_test_h2c_cmd(_adapter *adapter, u8 *buf, u8 len)
return res;
}
-/* #ifdef CONFIG_C2H_PACKET_EN */
-u8 rtw_c2h_packet_wk_cmd(PADAPTER padapter, u8 *pbuf, u16 length)
+#ifdef CONFIG_MP_INCLUDED
+static s32 rtw_mp_cmd_hdl(_adapter *padapter, u8 mp_cmd_id)
{
- struct cmd_obj *ph2c;
- struct drvextra_cmd_parm *pdrvextra_cmd_parm;
- struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
- u8 *extra_cmd_buf;
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+ int ret = H2C_SUCCESS;
+ uint status = _SUCCESS;
+ u8 rfreg0;
+
+ if (mp_cmd_id == MP_START) {
+ if (padapter->registrypriv.mp_mode == 0) {
+ rtw_intf_stop(padapter);
+ rtw_hal_deinit(padapter);
+ padapter->registrypriv.mp_mode = 1;
+#ifdef CONFIG_RF_POWER_TRIM
+ if (!IS_HARDWARE_TYPE_8814A(padapter) && !IS_HARDWARE_TYPE_8822B(padapter)) {
+ padapter->registrypriv.RegPwrTrimEnable = 1;
+ rtw_hal_read_chip_info(padapter);
+ }
+#endif /*CONFIG_RF_POWER_TRIM*/
+ rtw_reset_drv_sw(padapter);
+ status = rtw_hal_init(padapter);
+ if (status == _FAIL) {
+ ret = H2C_REJECTED;
+ goto exit;
+ }
+#ifndef RTW_HALMAC
+ rtw_intf_start(padapter);
+#endif /* !RTW_HALMAC */
+#ifdef RTW_HALMAC /*for New IC*/
+ MPT_InitializeAdapter(padapter, 1);
+#endif /* CONFIG_MP_INCLUDED */
+ }
+
+ if (padapter->registrypriv.mp_mode == 0) {
+ ret = H2C_REJECTED;
+ goto exit;
+ }
+
+ if (padapter->mppriv.mode == MP_OFF) {
+ if (mp_start_test(padapter) == _FAIL) {
+ ret = H2C_REJECTED;
+ goto exit;
+ }
+ padapter->mppriv.mode = MP_ON;
+ MPT_PwrCtlDM(padapter, 0);
+ }
+ padapter->mppriv.bmac_filter = _FALSE;
+#ifdef CONFIG_RTL8723B
+#ifdef CONFIG_USB_HCI
+ rtw_write32(padapter, 0x765, 0x0000);
+ rtw_write32(padapter, 0x948, 0x0280);
+#else
+ rtw_write32(padapter, 0x765, 0x0000);
+ rtw_write32(padapter, 0x948, 0x0000);
+#endif
+#ifdef CONFIG_FOR_RTL8723BS_VQ0
+ rtw_write32(padapter, 0x765, 0x0000);
+ rtw_write32(padapter, 0x948, 0x0280);
+#endif
+ rtw_write8(padapter, 0x66, 0x27); /*Open BT uart Log*/
+ rtw_write8(padapter, 0xc50, 0x20); /*for RX init Gain*/
+#endif
+ odm_write_dig(&pHalData->odmpriv, 0x20);
+
+ } else if (mp_cmd_id == MP_STOP) {
+ if (padapter->registrypriv.mp_mode == 1) {
+ MPT_DeInitAdapter(padapter);
+ rtw_intf_stop(padapter);
+ rtw_hal_deinit(padapter);
+ padapter->registrypriv.mp_mode = 0;
+ rtw_reset_drv_sw(padapter);
+ status = rtw_hal_init(padapter);
+ if (status == _FAIL) {
+ ret = H2C_REJECTED;
+ goto exit;
+ }
+#ifndef RTW_HALMAC
+ rtw_intf_start(padapter);
+#endif /* !RTW_HALMAC */
+ }
+
+ if (padapter->mppriv.mode != MP_OFF) {
+ mp_stop_test(padapter);
+ padapter->mppriv.mode = MP_OFF;
+ }
+
+ } else {
+ RTW_INFO(FUNC_ADPT_FMT"invalid id:%d\n", FUNC_ADPT_ARG(padapter), mp_cmd_id);
+ ret = H2C_PARAMETERS_ERROR;
+ rtw_warn_on(1);
+ }
+
+exit:
+ return ret;
+}
+
+u8 rtw_mp_cmd(_adapter *adapter, u8 mp_cmd_id, u8 flags)
+{
+ struct cmd_obj *cmdobj;
+ struct drvextra_cmd_parm *parm;
+ struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
+ struct submit_ctx sctx;
u8 res = _SUCCESS;
- ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
- if (ph2c == NULL) {
+ parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+ if (parm == NULL) {
res = _FAIL;
goto exit;
}
- pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
- if (pdrvextra_cmd_parm == NULL) {
- rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));
+ parm->ec_id = MP_CMD_WK_CID;
+ parm->type = mp_cmd_id;
+ parm->size = 0;
+ parm->pbuf = NULL;
+
+ if (flags & RTW_CMDF_DIRECTLY) {
+ /* no need to enqueue, do the cmd hdl directly and free cmd parameter */
+ if (H2C_SUCCESS != rtw_mp_cmd_hdl(adapter, mp_cmd_id))
+ res = _FAIL;
+ rtw_mfree((u8 *)parm, sizeof(*parm));
+ } else {
+ /* need enqueue, prepare cmd_obj and enqueue */
+ cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));
+ if (cmdobj == NULL) {
+ res = _FAIL;
+ rtw_mfree((u8 *)parm, sizeof(*parm));
+ goto exit;
+ }
+
+ init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_Set_Drv_Extra));
+
+ if (flags & RTW_CMDF_WAIT_ACK) {
+ cmdobj->sctx = &sctx;
+ rtw_sctx_init(&sctx, 10 * 1000);
+ }
+
+ res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
+
+ if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) {
+ rtw_sctx_wait(&sctx, __func__);
+ _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
+ if (sctx.status == RTW_SCTX_SUBMITTED)
+ cmdobj->sctx = NULL;
+ _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
+ if (sctx.status != RTW_SCTX_DONE_SUCCESS)
+ res = _FAIL;
+ }
+ }
+
+exit:
+ return res;
+}
+#endif /*CONFIG_MP_INCLUDED*/
+
+#ifdef CONFIG_RTW_CUSTOMER_STR
+static s32 rtw_customer_str_cmd_hdl(_adapter *adapter, u8 write, const u8 *cstr)
+{
+ int ret = H2C_SUCCESS;
+
+ if (write)
+ ret = rtw_hal_h2c_customer_str_write(adapter, cstr);
+ else
+ ret = rtw_hal_h2c_customer_str_req(adapter);
+
+ return ret == _SUCCESS ? H2C_SUCCESS : H2C_REJECTED;
+}
+
+static u8 rtw_customer_str_cmd(_adapter *adapter, u8 write, const u8 *cstr)
+{
+ struct cmd_obj *cmdobj;
+ struct drvextra_cmd_parm *parm;
+ u8 *str = NULL;
+ struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
+ struct submit_ctx sctx;
+ u8 res = _SUCCESS;
+
+ parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+ if (parm == NULL) {
res = _FAIL;
goto exit;
}
- extra_cmd_buf = rtw_zmalloc(length);
- if (extra_cmd_buf == NULL) {
- rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));
- rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));
+ if (write) {
+ str = rtw_zmalloc(RTW_CUSTOMER_STR_LEN);
+ if (str == NULL) {
+ rtw_mfree((u8 *)parm, sizeof(struct drvextra_cmd_parm));
+ res = _FAIL;
+ goto exit;
+ }
+ }
+
+ parm->ec_id = CUSTOMER_STR_WK_CID;
+ parm->type = write;
+ parm->size = write ? RTW_CUSTOMER_STR_LEN : 0;
+ parm->pbuf = write ? str : NULL;
+
+ if (write)
+ _rtw_memcpy(str, cstr, RTW_CUSTOMER_STR_LEN);
+
+ /* need enqueue, prepare cmd_obj and enqueue */
+ cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));
+ if (cmdobj == NULL) {
res = _FAIL;
+ rtw_mfree((u8 *)parm, sizeof(*parm));
+ if (write)
+ rtw_mfree(str, RTW_CUSTOMER_STR_LEN);
goto exit;
}
- _rtw_memcpy(extra_cmd_buf, pbuf, length);
- pdrvextra_cmd_parm->ec_id = C2H_WK_CID;
- pdrvextra_cmd_parm->type = 0;
- pdrvextra_cmd_parm->size = length;
- pdrvextra_cmd_parm->pbuf = extra_cmd_buf;
+ init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_Set_Drv_Extra));
- init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
+ cmdobj->sctx = &sctx;
+ rtw_sctx_init(&sctx, 2 * 1000);
- res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+ res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
+
+ if (res == _SUCCESS) {
+ rtw_sctx_wait(&sctx, __func__);
+ _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
+ if (sctx.status == RTW_SCTX_SUBMITTED)
+ cmdobj->sctx = NULL;
+ _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
+ if (sctx.status != RTW_SCTX_DONE_SUCCESS)
+ res = _FAIL;
+ }
exit:
return res;
}
-/* #else */ /* CONFIG_C2H_PACKET_EN */
-/* dont call R/W in this function, beucase SDIO interrupt have claim host
- * or deadlock will happen and cause special-systemserver-died in android */
+inline u8 rtw_customer_str_req_cmd(_adapter *adapter)
+{
+ return rtw_customer_str_cmd(adapter, 0, NULL);
+}
+
+inline u8 rtw_customer_str_write_cmd(_adapter *adapter, const u8 *cstr)
+{
+ return rtw_customer_str_cmd(adapter, 1, cstr);
+}
+#endif /* CONFIG_RTW_CUSTOMER_STR */
-u8 rtw_c2h_wk_cmd(PADAPTER padapter, u8 *c2h_evt)
+u8 rtw_c2h_wk_cmd(PADAPTER padapter, u8 *pbuf, u16 length, u8 type)
{
struct cmd_obj *ph2c;
struct drvextra_cmd_parm *pdrvextra_cmd_parm;
- struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
- u8 res = _SUCCESS;
+ struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
+ u8 *extra_cmd_buf;
+ u8 res = _SUCCESS;
ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
if (ph2c == NULL) {
@@ -3842,20 +4263,41 @@ u8 rtw_c2h_wk_cmd(PADAPTER padapter, u8 *c2h_evt)
goto exit;
}
+ extra_cmd_buf = rtw_zmalloc(length);
+ if (extra_cmd_buf == NULL) {
+ rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));
+ rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));
+ res = _FAIL;
+ goto exit;
+ }
+
+ _rtw_memcpy(extra_cmd_buf, pbuf, length);
pdrvextra_cmd_parm->ec_id = C2H_WK_CID;
- pdrvextra_cmd_parm->type = 0;
- pdrvextra_cmd_parm->size = c2h_evt ? 16 : 0;
- pdrvextra_cmd_parm->pbuf = c2h_evt;
+ pdrvextra_cmd_parm->type = type;
+ pdrvextra_cmd_parm->size = length;
+ pdrvextra_cmd_parm->pbuf = extra_cmd_buf;
init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
res = rtw_enqueue_cmd(pcmdpriv, ph2c);
exit:
-
return res;
}
-/* #endif */ /* CONFIG_C2H_PACKET_EN */
+
+#ifdef CONFIG_FW_C2H_REG
+inline u8 rtw_c2h_reg_wk_cmd(_adapter *adapter, u8 *c2h_evt)
+{
+ return rtw_c2h_wk_cmd(adapter, c2h_evt, c2h_evt ? C2H_REG_LEN : 0, C2H_TYPE_REG);
+}
+#endif
+
+#ifdef CONFIG_FW_C2H_PKT
+inline u8 rtw_c2h_packet_wk_cmd(_adapter *adapter, u8 *c2h_evt, u16 length)
+{
+ return rtw_c2h_wk_cmd(adapter, c2h_evt, length, C2H_TYPE_PKT);
+}
+#endif
u8 rtw_run_in_thread_cmd(PADAPTER padapter, void (*func)(void *), void *context)
{
@@ -3864,7 +4306,6 @@ u8 rtw_run_in_thread_cmd(PADAPTER padapter, void (*func)(void *), void *context)
struct RunInThread_param *parm;
s32 res = _SUCCESS;
- _func_enter_;
pcmdpriv = &padapter->cmdpriv;
@@ -3888,88 +4329,36 @@ u8 rtw_run_in_thread_cmd(PADAPTER padapter, void (*func)(void *), void *context)
res = rtw_enqueue_cmd(pcmdpriv, ph2c);
exit:
- _func_exit_;
return res;
}
+#ifdef CONFIG_FW_C2H_REG
s32 c2h_evt_hdl(_adapter *adapter, u8 *c2h_evt, c2h_id_filter filter)
{
s32 ret = _FAIL;
- u8 buf[16];
+ u8 buf[C2H_REG_LEN] = {0};
+ u8 id, seq, plen;
+ u8 *payload;
if (!c2h_evt) {
/* No c2h event in cmd_obj, read c2h event before handling*/
- if (rtw_hal_c2h_evt_read(adapter, buf) == _SUCCESS) {
- c2h_evt = buf;
-
- if (filter && filter(c2h_evt) == _FALSE)
- goto exit;
-
- ret = rtw_hal_c2h_handler(adapter, c2h_evt);
- }
- } else {
-
- if (filter && filter(c2h_evt) == _FALSE)
+ if (rtw_hal_c2h_evt_read(adapter, buf) != _SUCCESS)
goto exit;
-
- ret = rtw_hal_c2h_handler(adapter, c2h_evt);
+ c2h_evt = buf;
}
-exit:
- return ret;
-}
-#ifdef CONFIG_C2H_WK
-static void c2h_wk_callback(_workitem *work)
-{
- struct evt_priv *evtpriv = container_of(work, struct evt_priv, c2h_wk);
- _adapter *adapter = container_of(evtpriv, _adapter, evtpriv);
- u8 *c2h_evt;
- c2h_id_filter ccx_id_filter = rtw_hal_c2h_id_filter_ccx(adapter);
-
- evtpriv->c2h_wk_alive = _TRUE;
+ rtw_hal_c2h_reg_hdr_parse(adapter, c2h_evt, &id, &seq, &plen, &payload);
- while (!rtw_cbuf_empty(evtpriv->c2h_queue)) {
- c2h_evt = (u8 *)rtw_cbuf_pop(evtpriv->c2h_queue);
- if (c2h_evt != NULL) {
- /* This C2H event is read, clear it */
- c2h_evt_clear(adapter);
- } else {
- c2h_evt = (u8 *)rtw_malloc(16);
- if (c2h_evt == NULL) {
- rtw_warn_on(1);
- continue;
- }
-
- /* This C2H event is not read, read & clear now */
- if (rtw_hal_c2h_evt_read(adapter, c2h_evt) != _SUCCESS) {
- rtw_mfree(c2h_evt, 16);
- continue;
- }
- }
-
- /* Special pointer to trigger c2h_evt_clear only */
- if ((void *)c2h_evt == (void *)evtpriv)
- continue;
+ if (filter && filter(adapter, id, seq, plen, payload) == _FALSE)
+ goto exit;
- if (!rtw_hal_c2h_valid(adapter, c2h_evt)) {
- rtw_mfree(c2h_evt, 16);
- continue;
- }
+ ret = rtw_hal_c2h_handler(adapter, id, seq, plen, payload);
- if (ccx_id_filter(c2h_evt) == _TRUE) {
- /* Handle CCX report here */
- rtw_hal_c2h_handler(adapter, c2h_evt);
- rtw_mfree(c2h_evt, 16);
- } else {
- /* Enqueue into cmd_thread for others */
- rtw_c2h_wk_cmd(adapter, c2h_evt);
- }
- }
-
- evtpriv->c2h_wk_alive = _FALSE;
+exit:
+ return ret;
}
-#endif
+#endif /* CONFIG_FW_C2H_REG */
u8 session_tracker_cmd(_adapter *adapter, u8 cmd, struct sta_info *sta, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port)
{
@@ -4073,8 +4462,8 @@ void session_tracker_chk_for_sta(_adapter *adapter, struct sta_info *sta)
pnext = get_next(pnext);
if (st->status != ST_STATUS_ESTABLISH
- && rtw_get_passing_time_ms(st->set_time) > ST_EXPIRE_MS
- ) {
+ && rtw_get_passing_time_ms(st->set_time) > ST_EXPIRE_MS
+ ) {
rtw_list_delete(&st->list);
rtw_list_insert_tail(&st->list, &dlist);
}
@@ -4086,18 +4475,18 @@ void session_tracker_chk_for_sta(_adapter *adapter, struct sta_info *sta)
if (st->status != ST_STATUS_ESTABLISH)
continue;
-#ifdef CONFIG_WFD
+ #ifdef CONFIG_WFD
if (0)
RTW_INFO(FUNC_ADPT_FMT" local:%u, remote:%u, rtsp:%u, %u, %u\n", FUNC_ADPT_ARG(adapter)
, ntohs(st->local_port), ntohs(st->remote_port), adapter->wfd_info.rtsp_ctrlport, adapter->wfd_info.tdls_rtsp_ctrlport
- , adapter->wfd_info.peer_rtsp_ctrlport);
+ , adapter->wfd_info.peer_rtsp_ctrlport);
if (ntohs(st->local_port) == adapter->wfd_info.rtsp_ctrlport)
op_wfd_mode |= MIRACAST_SINK;
if (ntohs(st->local_port) == adapter->wfd_info.tdls_rtsp_ctrlport)
op_wfd_mode |= MIRACAST_SINK;
if (ntohs(st->remote_port) == adapter->wfd_info.peer_rtsp_ctrlport)
op_wfd_mode |= MIRACAST_SOURCE;
-#endif
+ #endif
}
_exit_critical_bh(&st_ctl->tracker_q.lock, &irqL);
@@ -4178,10 +4567,10 @@ void session_tracker_cmd_hdl(_adapter *adapter, struct st_cmd_parm *parm)
if (DBG_SESSION_TRACKER)
RTW_INFO(FUNC_ADPT_FMT" cmd:%u, sta:%p, local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT"\n"
- , FUNC_ADPT_ARG(adapter), cmd, sta
- , IP_ARG(&local_naddr), PORT_ARG(&local_port)
- , IP_ARG(&remote_naddr), PORT_ARG(&remote_port)
- );
+ , FUNC_ADPT_ARG(adapter), cmd, sta
+ , IP_ARG(&local_naddr), PORT_ARG(&local_port)
+ , IP_ARG(&remote_naddr), PORT_ARG(&remote_port)
+ );
if (!(sta->state & _FW_LINKED))
goto exit;
@@ -4196,9 +4585,9 @@ void session_tracker_cmd_hdl(_adapter *adapter, struct st_cmd_parm *parm)
st = LIST_CONTAINOR(plist, struct session_tracker, list);
if (st->local_naddr == local_naddr
- && st->local_port == local_port
- && st->remote_naddr == remote_naddr
- && st->remote_port == remote_port)
+ && st->local_port == local_port
+ && st->remote_naddr == remote_naddr
+ && st->remote_port == remote_port)
break;
plist = get_next(plist);
@@ -4249,8 +4638,72 @@ void session_tracker_cmd_hdl(_adapter *adapter, struct st_cmd_parm *parm)
return;
}
+#if defined(CONFIG_RTW_MESH) && defined(RTW_PER_CMD_SUPPORT_FW)
+static s32 rtw_req_per_cmd_hdl(_adapter *adapter)
+{
+ struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+ struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
+ struct macid_bmp req_macid_bmp, *macid_bmp;
+ u8 i, ret = _FAIL;
+
+ macid_bmp = &macid_ctl->if_g[adapter->iface_id];
+ _rtw_memcpy(&req_macid_bmp, macid_bmp, sizeof(struct macid_bmp));
+
+ /* Clear none mesh's macid */
+ for (i = 0; i < macid_ctl->num; i++) {
+ u8 role;
+ role = GET_H2CCMD_MSRRPT_PARM_ROLE(&macid_ctl->h2c_msr[i]);
+ if (role != H2C_MSR_ROLE_MESH)
+ rtw_macid_map_clr(&req_macid_bmp, i);
+ }
+
+ /* group_macid: always be 0 in NIC, so only pass macid_bitmap.m0
+ * rpt_type: 0 includes all info in 1, use 0 for now
+ * macid_bitmap: pass m0 only for NIC
+ */
+ ret = rtw_hal_set_req_per_rpt_cmd(adapter, 0, 0, req_macid_bmp.m0);
+
+ return ret;
+}
+
+u8 rtw_req_per_cmd(_adapter *adapter)
+{
+ struct cmd_obj *cmdobj;
+ struct drvextra_cmd_parm *parm;
+ struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
+ struct submit_ctx sctx;
+ u8 res = _SUCCESS;
+
+ parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+ if (parm == NULL) {
+ res = _FAIL;
+ goto exit;
+ }
+
+ parm->ec_id = REQ_PER_CMD_WK_CID;
+ parm->type = 0;
+ parm->size = 0;
+ parm->pbuf = NULL;
+
+ cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj));
+ if (cmdobj == NULL) {
+ res = _FAIL;
+ rtw_mfree((u8 *)parm, sizeof(*parm));
+ goto exit;
+ }
+
+ init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_Set_Drv_Extra));
+
+ res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
+
+exit:
+ return res;
+}
+#endif
+
u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf)
{
+ int ret = H2C_SUCCESS;
struct drvextra_cmd_parm *pdrvextra_cmd;
if (!pbuf)
@@ -4264,7 +4717,7 @@ u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf)
break;
case DYNAMIC_CHK_WK_CID:/*only primary padapter go to this cmd, but execute dynamic_chk_wk_hdl() for two interfaces */
- rtw_mi_dynamic_chk_wk_hdl(padapter);
+ rtw_dynamic_chk_wk_hdl(padapter);
break;
case POWER_SAVING_CTRL_WK_CID:
power_saving_wk_hdl(padapter);
@@ -4301,7 +4754,7 @@ u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf)
* Commented by Albert 2011/07/01
* I used the type_size as the type command
*/
- p2p_protocol_wk_hdl(padapter, pdrvextra_cmd->type);
+ ret = p2p_protocol_wk_hdl(padapter, pdrvextra_cmd->type, pdrvextra_cmd->pbuf);
break;
#endif
#ifdef CONFIG_AP_MODE
@@ -4322,11 +4775,22 @@ u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf)
free_assoc_resources_hdl(padapter);
break;
case C2H_WK_CID:
-#ifdef CONFIG_C2H_PACKET_EN
- rtw_hal_set_hwreg_with_buf(padapter, HW_VAR_C2H_HANDLE, pdrvextra_cmd->pbuf, pdrvextra_cmd->size);
-#else
- c2h_evt_hdl(padapter, pdrvextra_cmd->pbuf, NULL);
-#endif
+ switch (pdrvextra_cmd->type) {
+ #ifdef CONFIG_FW_C2H_REG
+ case C2H_TYPE_REG:
+ c2h_evt_hdl(padapter, pdrvextra_cmd->pbuf, NULL);
+ break;
+ #endif
+ #ifdef CONFIG_FW_C2H_PKT
+ case C2H_TYPE_PKT:
+ rtw_hal_c2h_pkt_hdl(padapter, pdrvextra_cmd->pbuf, pdrvextra_cmd->size);
+ break;
+ #endif
+ default:
+ RTW_ERR("unknown C2H type:%d\n", pdrvextra_cmd->type);
+ rtw_warn_on(1);
+ break;
+ }
break;
#ifdef CONFIG_BEAMFORMING
case BEAMFORMING_WK_CID:
@@ -4355,6 +4819,38 @@ u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf)
case TEST_H2C_CID:
rtw_hal_fill_h2c_cmd(padapter, pdrvextra_cmd->pbuf[0], pdrvextra_cmd->size - 1, &pdrvextra_cmd->pbuf[1]);
break;
+ case MP_CMD_WK_CID:
+#ifdef CONFIG_MP_INCLUDED
+ ret = rtw_mp_cmd_hdl(padapter, pdrvextra_cmd->type);
+#endif
+ break;
+#ifdef CONFIG_RTW_CUSTOMER_STR
+ case CUSTOMER_STR_WK_CID:
+ ret = rtw_customer_str_cmd_hdl(padapter, pdrvextra_cmd->type, pdrvextra_cmd->pbuf);
+ break;
+#endif
+
+#ifdef CONFIG_RTW_REPEATER_SON
+ case RSON_SCAN_WK_CID:
+ rtw_rson_scan_cmd_hdl(padapter, pdrvextra_cmd->type);
+ break;
+#endif
+
+#ifdef CONFIG_IOCTL_CFG80211
+ case MGNT_TX_WK_CID:
+ ret = rtw_mgnt_tx_handler(padapter, pdrvextra_cmd->pbuf);
+ break;
+#endif /* CONFIG_IOCTL_CFG80211 */
+#ifdef CONFIG_MCC_MODE
+ case MCC_SET_DURATION_WK_CID:
+ ret = rtw_set_mcc_duration_hdl(padapter, pdrvextra_cmd->type, pdrvextra_cmd->pbuf);
+ break;
+#endif /* CONFIG_MCC_MODE */
+#if defined(CONFIG_RTW_MESH) && defined(RTW_PER_CMD_SUPPORT_FW)
+ case REQ_PER_CMD_WK_CID:
+ ret = rtw_req_per_cmd_hdl(padapter);
+ break;
+#endif
default:
break;
}
@@ -4362,14 +4858,13 @@ u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf)
if (pdrvextra_cmd->pbuf && pdrvextra_cmd->size > 0)
rtw_mfree(pdrvextra_cmd->pbuf, pdrvextra_cmd->size);
- return H2C_SUCCESS;
+ return ret;
}
void rtw_survey_cmd_callback(_adapter *padapter , struct cmd_obj *pcmd)
{
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
- _func_enter_;
if (pcmd->res == H2C_DROPPED) {
/* TODO: cancel timer and do timeout handler directly... */
@@ -4377,28 +4872,22 @@ void rtw_survey_cmd_callback(_adapter *padapter , struct cmd_obj *pcmd)
mlme_set_scan_to_timer(pmlmepriv, 1);
} else if (pcmd->res != H2C_SUCCESS) {
mlme_set_scan_to_timer(pmlmepriv, 1);
- RT_TRACE(_module_rtl871x_cmd_c_, _drv_err_, ("\n ********Error: MgntActrtw_set_802_11_bssid_LIST_SCAN Fail ************\n\n."));
}
/* free cmd */
rtw_free_cmd_obj(pcmd);
- _func_exit_;
}
void rtw_disassoc_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd)
{
_irqL irqL;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
- _func_enter_;
if (pcmd->res != H2C_SUCCESS) {
_enter_critical_bh(&pmlmepriv->lock, &irqL);
set_fwstate(pmlmepriv, _FW_LINKED);
_exit_critical_bh(&pmlmepriv->lock, &irqL);
-
- RT_TRACE(_module_rtl871x_cmd_c_, _drv_err_, ("\n ***Error: disconnect_cmd_callback Fail ***\n."));
-
goto exit;
}
#ifdef CONFIG_BR_EXT
@@ -4410,26 +4899,22 @@ void rtw_disassoc_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd)
rtw_free_cmd_obj(pcmd);
exit:
-
- _func_exit_;
+ return;
}
void rtw_getmacreg_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd)
{
- _func_enter_;
rtw_free_cmd_obj(pcmd);
- _func_exit_;
}
void rtw_joinbss_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd)
{
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
- _func_enter_;
if (pcmd->res == H2C_DROPPED) {
/* TODO: cancel timer and do timeout handler directly... */
@@ -4440,13 +4925,11 @@ void rtw_joinbss_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd)
rtw_free_cmd_obj(pcmd);
- _func_exit_;
}
void rtw_create_ibss_post_hdl(_adapter *padapter, int status)
{
_irqL irqL;
- u8 timer_cancelled;
struct sta_info *psta = NULL;
struct wlan_network *pwlan = NULL;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
@@ -4456,7 +4939,7 @@ void rtw_create_ibss_post_hdl(_adapter *padapter, int status)
if (status != H2C_SUCCESS)
_set_timer(&pmlmepriv->assoc_timer, 1);
- _cancel_timer(&pmlmepriv->assoc_timer, &timer_cancelled);
+ _cancel_timer_ex(&pmlmepriv->assoc_timer);
_enter_critical_bh(&pmlmepriv->lock, &irqL);
@@ -4468,7 +4951,6 @@ void rtw_create_ibss_post_hdl(_adapter *padapter, int status)
if (pwlan == NULL) {
pwlan = rtw_get_oldest_wlan_network(&pmlmepriv->scanned_queue);
if (pwlan == NULL) {
- RT_TRACE(_module_rtl871x_cmd_c_, _drv_err_, ("Error: can't get pwlan in rtw_joinbss_event_callback\n"));
_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
goto createbss_cmd_fail;
}
@@ -4508,20 +4990,17 @@ void rtw_setstaKey_cmdrsp_callback(_adapter *padapter , struct cmd_obj *pcmd)
struct set_stakey_rsp *psetstakey_rsp = (struct set_stakey_rsp *)(pcmd->rsp);
struct sta_info *psta = rtw_get_stainfo(pstapriv, psetstakey_rsp->addr);
- _func_enter_;
if (psta == NULL) {
- RT_TRACE(_module_rtl871x_cmd_c_, _drv_err_, ("\nERROR: rtw_setstaKey_cmdrsp_callback => can't get sta_info \n\n"));
goto exit;
}
- /* psta->aid = psta->mac_id = psetstakey_rsp->keyid; */ /* CAM_ID(CAM_ENTRY) */
+ /* psta->cmn.aid = psta->cmn.mac_id = psetstakey_rsp->keyid; */ /* CAM_ID(CAM_ENTRY) */
exit:
rtw_free_cmd_obj(pcmd);
- _func_exit_;
}
void rtw_setassocsta_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd)
@@ -4533,14 +5012,12 @@ void rtw_setassocsta_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd)
struct set_assocsta_rsp *passocsta_rsp = (struct set_assocsta_rsp *)(pcmd->rsp);
struct sta_info *psta = rtw_get_stainfo(pstapriv, passocsta_parm->addr);
- _func_enter_;
if (psta == NULL) {
- RT_TRACE(_module_rtl871x_cmd_c_, _drv_err_, ("\nERROR: setassocsta_cmdrsp_callbac => can't get sta_info \n\n"));
goto exit;
}
- psta->aid = psta->mac_id = passocsta_rsp->cam_id;
+ psta->cmn.aid = psta->cmn.mac_id = passocsta_rsp->cam_id;
_enter_critical_bh(&pmlmepriv->lock, &irqL);
@@ -4553,13 +5030,11 @@ void rtw_setassocsta_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd)
exit:
rtw_free_cmd_obj(pcmd);
- _func_exit_;
}
void rtw_getrttbl_cmd_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd);
void rtw_getrttbl_cmd_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd)
{
- _func_enter_;
rtw_free_cmd_obj(pcmd);
#ifdef CONFIG_MP_INCLUDED
@@ -4567,6 +5042,5 @@ void rtw_getrttbl_cmd_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd)
padapter->mppriv.workparam.bcompleted = _TRUE;
#endif
- _func_exit_;
}
diff --git a/core/rtw_debug.c b/core/rtw_debug.c
index 97f1c9b..8b33a5f 100644
--- a/core/rtw_debug.c
+++ b/core/rtw_debug.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,12 +11,7 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#define _RTW_DEBUG_C_
#include
@@ -47,14 +42,17 @@ const char *rtw_log_level_str[] = {
void dump_drv_version(void *sel)
{
RTW_PRINT_SEL(sel, "%s %s\n", DRV_NAME, DRIVERVERSION);
- //RTW_PRINT_SEL(sel, "build time: %s %s\n", __DATE__, __TIME__);
+// RTW_PRINT_SEL(sel, "build time: %s %s\n", __DATE__, __TIME__); //EDX
}
void dump_drv_cfg(void *sel)
{
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))
char *kernel_version = utsname()->release;
RTW_PRINT_SEL(sel, "\nKernel Version: %s\n", kernel_version);
+#endif
+
RTW_PRINT_SEL(sel, "Driver Version: %s\n", DRIVERVERSION);
RTW_PRINT_SEL(sel, "------------------------------------------------\n");
#ifdef CONFIG_IOCTL_CFG80211
@@ -62,6 +60,9 @@ void dump_drv_cfg(void *sel)
#ifdef RTW_USE_CFG80211_STA_EVENT
RTW_PRINT_SEL(sel, "RTW_USE_CFG80211_STA_EVENT\n");
#endif
+ #ifdef CONFIG_RADIO_WORK
+ RTW_PRINT_SEL(sel, "CONFIG_RADIO_WORK\n");
+ #endif
#else
RTW_PRINT_SEL(sel, "WEXT\n");
#endif
@@ -81,6 +82,11 @@ void dump_drv_cfg(void *sel)
#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
RTW_PRINT_SEL(sel, "LOAD_PHY_PARA_FROM_FILE - REALTEK_CONFIG_PATH=%s\n", REALTEK_CONFIG_PATH);
+ #if defined(CONFIG_MULTIDRV) || defined(REALTEK_CONFIG_PATH_WITH_IC_NAME_FOLDER)
+ RTW_PRINT_SEL(sel, "LOAD_PHY_PARA_FROM_FILE - REALTEK_CONFIG_PATH_WITH_IC_NAME_FOLDER\n");
+ #endif
+
+/* configurations about TX power */
#ifdef CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY
RTW_PRINT_SEL(sel, "CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY\n");
#endif
@@ -88,6 +94,11 @@ void dump_drv_cfg(void *sel)
RTW_PRINT_SEL(sel, "CONFIG_CALIBRATE_TX_POWER_TO_MAX\n");
#endif
#endif
+ RTW_PRINT_SEL(sel, "RTW_DEF_MODULE_REGULATORY_CERT=0x%02x\n", RTW_DEF_MODULE_REGULATORY_CERT);
+
+ RTW_PRINT_SEL(sel, "CONFIG_TXPWR_BY_RATE_EN=%d\n", CONFIG_TXPWR_BY_RATE_EN);
+ RTW_PRINT_SEL(sel, "CONFIG_TXPWR_LIMIT_EN=%d\n", CONFIG_TXPWR_LIMIT_EN);
+
#ifdef CONFIG_DISABLE_ODM
RTW_PRINT_SEL(sel, "CONFIG_DISABLE_ODM\n");
@@ -114,6 +125,18 @@ void dump_drv_cfg(void *sel)
RTW_PRINT_SEL(sel, "CONFIG_TDLS\n");
#endif
+#ifdef CONFIG_RTW_80211R
+ RTW_PRINT_SEL(sel, "CONFIG_RTW_80211R\n");
+#endif
+
+#ifdef CONFIG_RTW_NETIF_SG
+ RTW_PRINT_SEL(sel, "CONFIG_RTW_NETIF_SG\n");
+#endif
+
+#ifdef CONFIG_RTW_WIFI_HAL
+ RTW_PRINT_SEL(sel, "CONFIG_RTW_WIFI_HAL\n");
+#endif
+
#ifdef CONFIG_USB_HCI
#ifdef CONFIG_SUPPORT_USB_INT
RTW_PRINT_SEL(sel, "CONFIG_SUPPORT_USB_INT\n");
@@ -153,7 +176,17 @@ void dump_drv_cfg(void *sel)
#ifdef CONFIG_PCI_HCI
#endif
+ RTW_PRINT_SEL(sel, "\n=== XMIT-INFO ===\n");
+ RTW_PRINT_SEL(sel, "NR_XMITFRAME = %d\n", NR_XMITFRAME);
+ RTW_PRINT_SEL(sel, "NR_XMITBUFF = %d\n", NR_XMITBUFF);
RTW_PRINT_SEL(sel, "MAX_XMITBUF_SZ = %d\n", MAX_XMITBUF_SZ);
+ RTW_PRINT_SEL(sel, "NR_XMIT_EXTBUFF = %d\n", NR_XMIT_EXTBUFF);
+ RTW_PRINT_SEL(sel, "MAX_XMIT_EXTBUF_SZ = %d\n", MAX_XMIT_EXTBUF_SZ);
+ RTW_PRINT_SEL(sel, "MAX_CMDBUF_SZ = %d\n", MAX_CMDBUF_SZ);
+
+ RTW_PRINT_SEL(sel, "\n=== RECV-INFO ===\n");
+ RTW_PRINT_SEL(sel, "NR_RECVFRAME = %d\n", NR_RECVFRAME);
+ RTW_PRINT_SEL(sel, "NR_RECVBUFF = %d\n", NR_RECVBUFF);
RTW_PRINT_SEL(sel, "MAX_RECVBUF_SZ = %d\n", MAX_RECVBUF_SZ);
}
@@ -214,7 +247,7 @@ void mac_reg_dump(void *sel, _adapter *adapter)
for (i = 0x0; i < 0x800; i += 4) {
if (j % 4 == 1)
- RTW_PRINT_SEL(sel, "0x%03x", i);
+ RTW_PRINT_SEL(sel, "0x%04x", i);
_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
if ((j++) % 4 == 0)
_RTW_PRINT_SEL(sel, "\n");
@@ -224,7 +257,7 @@ void mac_reg_dump(void *sel, _adapter *adapter)
{
for (i = 0x1000; i < 0x1650; i += 4) {
if (j % 4 == 1)
- RTW_PRINT_SEL(sel, "0x%03x", i);
+ RTW_PRINT_SEL(sel, "0x%04x", i);
_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
if ((j++) % 4 == 0)
_RTW_PRINT_SEL(sel, "\n");
@@ -232,10 +265,11 @@ void mac_reg_dump(void *sel, _adapter *adapter)
}
#endif /* CONFIG_RTL8814A */
-#ifdef CONFIG_RTL8822B
+
+#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
for (i = 0x1000; i < 0x1800; i += 4) {
if (j % 4 == 1)
- RTW_PRINT_SEL(sel, "0x%03x", i);
+ RTW_PRINT_SEL(sel, "0x%04x", i);
_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
if ((j++) % 4 == 0)
_RTW_PRINT_SEL(sel, "\n");
@@ -250,16 +284,16 @@ void bb_reg_dump(void *sel, _adapter *adapter)
RTW_PRINT_SEL(sel, "======= BB REG =======\n");
for (i = 0x800; i < 0x1000; i += 4) {
if (j % 4 == 1)
- RTW_PRINT_SEL(sel, "0x%03x", i);
+ RTW_PRINT_SEL(sel, "0x%04x", i);
_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
if ((j++) % 4 == 0)
_RTW_PRINT_SEL(sel, "\n");
}
-#ifdef CONFIG_RTL8822B
+#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
for (i = 0x1800; i < 0x2000; i += 4) {
if (j % 4 == 1)
- RTW_PRINT_SEL(sel, "0x%03x", i);
+ RTW_PRINT_SEL(sel, "0x%04x", i);
_RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
if ((j++) % 4 == 0)
_RTW_PRINT_SEL(sel, "\n");
@@ -267,6 +301,26 @@ void bb_reg_dump(void *sel, _adapter *adapter)
#endif /* CONFIG_RTL8822B */
}
+void bb_reg_dump_ex(void *sel, _adapter *adapter)
+{
+ int i, j = 1;
+
+ RTW_PRINT_SEL(sel, "======= BB REG =======\n");
+ for (i = 0x800; i < 0x1000; i += 4) {
+ RTW_PRINT_SEL(sel, "0x%04x", i);
+ _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
+ _RTW_PRINT_SEL(sel, "\n");
+ }
+
+#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
+ for (i = 0x1800; i < 0x2000; i += 4) {
+ RTW_PRINT_SEL(sel, "0x%04x", i);
+ _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i));
+ _RTW_PRINT_SEL(sel, "\n");
+ }
+#endif /* CONFIG_RTL8822B */
+}
+
void rf_reg_dump(void *sel, _adapter *adapter)
{
int i, j = 1, path;
@@ -295,55 +349,13 @@ void rf_reg_dump(void *sel, _adapter *adapter)
}
}
-static u8 fwdl_test_chksum_fail = 0;
-static u8 fwdl_test_wintint_rdy_fail = 0;
-
-bool rtw_fwdl_test_trigger_chksum_fail(void)
-{
- if (fwdl_test_chksum_fail) {
- RTW_PRINT("fwdl test case: trigger chksum_fail\n");
- fwdl_test_chksum_fail--;
- return _TRUE;
- }
- return _FALSE;
-}
-
-bool rtw_fwdl_test_trigger_wintint_rdy_fail(void)
-{
- if (fwdl_test_wintint_rdy_fail) {
- RTW_PRINT("fwdl test case: trigger wintint_rdy_fail\n");
- fwdl_test_wintint_rdy_fail--;
- return _TRUE;
- }
- return _FALSE;
-}
-
-static u32 g_wait_hiq_empty_ms = 0;
-
-u32 rtw_get_wait_hiq_empty_ms(void)
-{
- return g_wait_hiq_empty_ms;
-}
-
-static u8 del_rx_ampdu_test_no_tx_fail = 0;
-
-bool rtw_del_rx_ampdu_test_trigger_no_tx_fail(void)
-{
- if (del_rx_ampdu_test_no_tx_fail) {
- RTW_PRINT("del_rx_ampdu test case: trigger no_tx_fail\n");
- del_rx_ampdu_test_no_tx_fail--;
- return _TRUE;
- }
- return _FALSE;
-}
-
-void rtw_sink_rtp_seq_dbg(_adapter *adapter, _pkt *pkt)
+void rtw_sink_rtp_seq_dbg(_adapter *adapter, u8 *ehdr_pos)
{
struct recv_priv *precvpriv = &(adapter->recvpriv);
if (precvpriv->sink_udpport > 0) {
- if (*((u16 *)((pkt->data) + 0x24)) == cpu_to_be16(precvpriv->sink_udpport)) {
+ if (*((u16 *)(ehdr_pos + 0x24)) == cpu_to_be16(precvpriv->sink_udpport)) {
precvpriv->pre_rtp_rxseq = precvpriv->cur_rtp_rxseq;
- precvpriv->cur_rtp_rxseq = be16_to_cpu(*((u16 *)((pkt->data) + 0x2C)));
+ precvpriv->cur_rtp_rxseq = be16_to_cpu(*((u16 *)(ehdr_pos + 0x2C)));
if (precvpriv->pre_rtp_rxseq + 1 != precvpriv->cur_rtp_rxseq)
RTW_INFO("%s : RTP Seq num from %d to %d\n", __FUNCTION__, precvpriv->pre_rtp_rxseq, precvpriv->cur_rtp_rxseq);
}
@@ -365,6 +377,45 @@ void sta_rx_reorder_ctl_dump(void *sel, struct sta_info *sta)
}
}
+void dump_tx_rate_bmp(void *sel, struct dvobj_priv *dvobj)
+{
+ _adapter *adapter = dvobj_get_primary_adapter(dvobj);
+ struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj);
+ u8 bw;
+
+ RTW_PRINT_SEL(sel, "%-6s", "bw");
+ if (hal_chk_proto_cap(adapter, PROTO_CAP_11AC))
+ _RTW_PRINT_SEL(sel, " %-11s", "vht");
+
+ _RTW_PRINT_SEL(sel, " %-11s %-4s %-3s\n", "ht", "ofdm", "cck");
+
+ for (bw = CHANNEL_WIDTH_20; bw <= CHANNEL_WIDTH_160; bw++) {
+ if (!hal_is_bw_support(adapter, bw))
+ continue;
+
+ RTW_PRINT_SEL(sel, "%6s", ch_width_str(bw));
+ if (hal_chk_proto_cap(adapter, PROTO_CAP_11AC)) {
+ _RTW_PRINT_SEL(sel, " %03x %03x %03x"
+ , RATE_BMP_GET_VHT_3SS(rfctl->rate_bmp_vht_by_bw[bw])
+ , RATE_BMP_GET_VHT_2SS(rfctl->rate_bmp_vht_by_bw[bw])
+ , RATE_BMP_GET_VHT_1SS(rfctl->rate_bmp_vht_by_bw[bw])
+ );
+ }
+
+ _RTW_PRINT_SEL(sel, " %02x %02x %02x %02x"
+ , bw <= CHANNEL_WIDTH_40 ? RATE_BMP_GET_HT_4SS(rfctl->rate_bmp_ht_by_bw[bw]) : 0
+ , bw <= CHANNEL_WIDTH_40 ? RATE_BMP_GET_HT_3SS(rfctl->rate_bmp_ht_by_bw[bw]) : 0
+ , bw <= CHANNEL_WIDTH_40 ? RATE_BMP_GET_HT_2SS(rfctl->rate_bmp_ht_by_bw[bw]) : 0
+ , bw <= CHANNEL_WIDTH_40 ? RATE_BMP_GET_HT_1SS(rfctl->rate_bmp_ht_by_bw[bw]) : 0
+ );
+
+ _RTW_PRINT_SEL(sel, " %03x %01x\n"
+ , bw <= CHANNEL_WIDTH_20 ? RATE_BMP_GET_OFDM(rfctl->rate_bmp_cck_ofdm) : 0
+ , bw <= CHANNEL_WIDTH_20 ? RATE_BMP_GET_CCK(rfctl->rate_bmp_cck_ofdm) : 0
+ );
+ }
+}
+
void dump_adapters_status(void *sel, struct dvobj_priv *dvobj)
{
struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj);
@@ -374,118 +425,136 @@ void dump_adapters_status(void *sel, struct dvobj_priv *dvobj)
dump_mi_status(sel, dvobj);
- RTW_PRINT_SEL(sel, "%-2s %-8s %-17s %-4s %-7s %s\n"
- , "id", "ifname", "macaddr", "port", "ch", "status");
+#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
+ RTW_PRINT_SEL(sel, "default port id:%d\n\n", dvobj->default_port_id);
+#endif /* CONFIG_FW_MULTI_PORT_SUPPORT */
+
+ RTW_PRINT_SEL(sel, "dev status:%s%s\n\n"
+ , dev_is_surprise_removed(dvobj) ? " SR" : ""
+ , dev_is_drv_stopped(dvobj) ? " DS" : ""
+ );
+
+#ifdef CONFIG_P2P
+#define P2P_INFO_TITLE_FMT " %-3s %-4s"
+#define P2P_INFO_TITLE_ARG , "lch", "p2ps"
+#ifdef CONFIG_IOCTL_CFG80211
+#define P2P_INFO_VALUE_FMT " %3u %c%3u"
+#define P2P_INFO_VALUE_ARG , iface->wdinfo.listen_channel, iface->wdev_data.p2p_enabled ? 'e' : ' ', rtw_p2p_state(&iface->wdinfo)
+#else
+#define P2P_INFO_VALUE_FMT " %3u %4u"
+#define P2P_INFO_VALUE_ARG , iface->wdinfo.listen_channel, rtw_p2p_state(&iface->wdinfo)
+#endif
+#define P2P_INFO_DASH "---------"
+#else
+#define P2P_INFO_TITLE_FMT ""
+#define P2P_INFO_TITLE_ARG
+#define P2P_INFO_VALUE_FMT ""
+#define P2P_INFO_VALUE_ARG
+#define P2P_INFO_DASH
+#endif
+
+ RTW_PRINT_SEL(sel, "%-2s %-15s %c %-3s %-3s %-3s %-17s %-4s %-7s"
+ P2P_INFO_TITLE_FMT
+ " %s\n"
+ , "id", "ifname", ' ', "bup", "nup", "ncd", "macaddr", "port", "ch"
+ P2P_INFO_TITLE_ARG
+ , "status");
- RTW_PRINT_SEL(sel, "------------------------------------------\n");
+ RTW_PRINT_SEL(sel, "---------------------------------------------------------------"
+ P2P_INFO_DASH
+ "-------\n");
for (i = 0; i < dvobj->iface_nums; i++) {
iface = dvobj->padapters[i];
if (iface) {
- RTW_PRINT_SEL(sel, "%2d %-8s "MAC_FMT" %4hhu %3u,%u,%u "MLME_STATE_FMT" %s%s\n"
- , i, ADPT_ARG(iface)
- , MAC_ARG(adapter_mac_addr(iface))
- , get_hw_port(iface)
- , iface->mlmeextpriv.cur_channel
- , iface->mlmeextpriv.cur_bwmode
- , iface->mlmeextpriv.cur_ch_offset
- , MLME_STATE_ARG(iface)
- , rtw_is_surprise_removed(iface) ? " SR" : ""
- , rtw_is_drv_stopped(iface) ? " DS" : ""
- );
+ RTW_PRINT_SEL(sel, "%2d %-15s %c %3u %3u %3u "MAC_FMT" %4hhu %3u,%u,%u"
+ P2P_INFO_VALUE_FMT
+ " "MLME_STATE_FMT"\n"
+ , i, iface->registered ? ADPT_ARG(iface) : NULL
+ , iface->registered ? 'R' : ' '
+ , iface->bup
+ , iface->netif_up
+ , iface->net_closed
+ , MAC_ARG(adapter_mac_addr(iface))
+ , get_hw_port(iface)
+ , iface->mlmeextpriv.cur_channel
+ , iface->mlmeextpriv.cur_bwmode
+ , iface->mlmeextpriv.cur_ch_offset
+ P2P_INFO_VALUE_ARG
+ , MLME_STATE_ARG(iface)
+ );
}
}
- RTW_PRINT_SEL(sel, "------------------------------------------\n");
+ RTW_PRINT_SEL(sel, "---------------------------------------------------------------"
+ P2P_INFO_DASH
+ "-------\n");
- rtw_mi_get_ch_setting_union(dvobj->padapters[IFACE_ID0], &u_ch, &u_bw, &u_offset);
- RTW_PRINT_SEL(sel, "%34s %3u,%u,%u\n"
- , "union:"
- , u_ch, u_bw, u_offset
- );
+ rtw_mi_get_ch_setting_union(dvobj_get_primary_adapter(dvobj), &u_ch, &u_bw, &u_offset);
+ RTW_PRINT_SEL(sel, "%55s %3u,%u,%u\n"
+ , "union:"
+ , u_ch, u_bw, u_offset
+ );
- RTW_PRINT_SEL(sel, "%34s %3u,%u,%u\n"
- , "oper:"
- , dvobj->oper_channel
- , dvobj->oper_bwmode
- , dvobj->oper_ch_offset
- );
+ RTW_PRINT_SEL(sel, "%55s %3u,%u,%u offch_state:%d\n"
+ , "oper:"
+ , dvobj->oper_channel
+ , dvobj->oper_bwmode
+ , dvobj->oper_ch_offset
+ , rfctl->offch_state
+ );
#ifdef CONFIG_DFS_MASTER
if (rfctl->radar_detect_ch != 0) {
- u32 non_ocp_ms;
- u32 cac_ms;
+ RTW_PRINT_SEL(sel, "%55s %3u,%u,%u"
+ , "radar_detect:"
+ , rfctl->radar_detect_ch
+ , rfctl->radar_detect_bw
+ , rfctl->radar_detect_offset
+ );
+
+ if (rfctl->radar_detect_by_others)
+ _RTW_PRINT_SEL(sel, ", by AP of STA link");
+ else {
+ u32 non_ocp_ms;
+ u32 cac_ms;
+ u8 dfs_domain = rtw_odm_get_dfs_domain(dvobj_get_primary_adapter(dvobj));
+
+ _RTW_PRINT_SEL(sel, ", domain:%u", dfs_domain);
+
+ for (i = 0; i < dvobj->iface_nums; i++) {
+ if (!dvobj->padapters[i])
+ continue;
+ if (check_fwstate(&dvobj->padapters[i]->mlmepriv, WIFI_AP_STATE | WIFI_MESH_STATE)
+ && check_fwstate(&dvobj->padapters[i]->mlmepriv, WIFI_ASOC_STATE))
+ break;
+ }
- for (i = 0; i < dvobj->iface_nums; i++) {
- if (!dvobj->padapters[i])
- continue;
- if (check_fwstate(&dvobj->padapters[i]->mlmepriv, WIFI_AP_STATE)
- && check_fwstate(&dvobj->padapters[i]->mlmepriv, WIFI_ASOC_STATE))
- break;
- }
+ if (i >= dvobj->iface_nums) {
+ RTW_PRINT_SEL(sel, "DFS master enable without AP/Mesh mode???");
+ goto end_dfs_master;
+ }
- if (i >= dvobj->iface_nums) {
- RTW_PRINT_SEL(sel, "DFS master enable without AP mode???");
- goto end_dfs_master;
+ rtw_get_ch_waiting_ms(dvobj->padapters[i]
+ , rfctl->radar_detect_ch
+ , rfctl->radar_detect_bw
+ , rfctl->radar_detect_offset
+ , &non_ocp_ms
+ , &cac_ms
+ );
+
+ if (non_ocp_ms)
+ _RTW_PRINT_SEL(sel, ", non_ocp:%d", non_ocp_ms);
+ if (cac_ms)
+ _RTW_PRINT_SEL(sel, ", cac:%d", cac_ms);
}
- RTW_PRINT_SEL(sel, "%34s %3u,%u,%u"
- , "radar_detect:"
- , rfctl->radar_detect_ch
- , rfctl->radar_detect_bw
- , rfctl->radar_detect_offset
- );
-
- _RTW_PRINT_SEL(sel, ", domain:%u", rtw_odm_get_dfs_domain(dvobj->padapters[IFACE_ID0]));
-
- rtw_get_ch_waiting_ms(dvobj->padapters[i]
- , rfctl->radar_detect_ch
- , rfctl->radar_detect_bw
- , rfctl->radar_detect_offset
- , &non_ocp_ms
- , &cac_ms
- );
-
- if (non_ocp_ms)
- _RTW_PRINT_SEL(sel, ", non_ocp:%d", non_ocp_ms);
- if (cac_ms)
- _RTW_PRINT_SEL(sel, ", cac:%d", cac_ms);
end_dfs_master:
_RTW_PRINT_SEL(sel, "\n");
}
#endif /* CONFIG_DFS_MASTER */
}
-void dump_adapters_info(void *sel, struct dvobj_priv *dvobj)
-{
- int i;
- _adapter *iface;
- u8 u_ch, u_bw, u_offset;
-
- RTW_PRINT_SEL(sel, "%-8s %-8s %-4s %-4s %-8s %-8s\n"
- , "iface_id", "ifname", "port", "bup ", "netif_up", "net_closed");
-
- RTW_PRINT_SEL(sel, "------------------------\n");
-
- for (i = 0; i < dvobj->iface_nums; i++) {
- iface = dvobj->padapters[i];
- if (iface) {
- RTW_PRINT_SEL(sel, "%2d %-8s %u %s,%s,%s %s%s\n"
- , iface->iface_id
- , ADPT_ARG(iface)
- , get_hw_port(iface)
- , (iface->bup) ? " TRUE" : " FALSE"
- , (iface->netif_up) ? " TRUE" : " FALSE"
- , (iface->net_closed) ? " TRUE" : " FALSE"
- , rtw_is_surprise_removed(iface) ? " SR" : ""
- , rtw_is_drv_stopped(iface) ? " DS" : ""
- );
- }
- }
-
- RTW_PRINT_SEL(sel, "------------------------\n");
-}
-
#define SEC_CAM_ENT_ID_TITLE_FMT "%-2s"
#define SEC_CAM_ENT_ID_TITLE_ARG "id"
#define SEC_CAM_ENT_ID_VALUE_FMT "%2u"
@@ -537,6 +606,21 @@ void dump_sec_cam(void *sel, _adapter *adapter)
}
}
+void dump_sec_cam_cache(void *sel, _adapter *adapter)
+{
+ struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+ struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
+ int i;
+
+ RTW_PRINT_SEL(sel, "SW sec cam cache:\n");
+ dump_sec_cam_ent_title(sel, 1);
+ for (i = 0; i < cam_ctl->num; i++) {
+ if (dvobj->cam_cache[i].ctrl != 0)
+ dump_sec_cam_ent(sel, &dvobj->cam_cache[i], i);
+ }
+
+}
+
#ifdef CONFIG_PROC_DEBUG
ssize_t proc_set_write_reg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
@@ -650,6 +734,125 @@ ssize_t proc_set_read_reg(struct file *file, const char __user *buffer, size_t c
}
+int proc_get_rx_stat(struct seq_file *m, void *v)
+{
+ _irqL irqL;
+ _list *plist, *phead;
+ struct net_device *dev = m->private;
+ _adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+ struct sta_info *psta = NULL;
+ struct stainfo_stats *pstats = NULL;
+ struct sta_priv *pstapriv = &(adapter->stapriv);
+ u32 i, j;
+ u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+ u8 null_addr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
+
+ _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+ for (i = 0; i < NUM_STA; i++) {
+ phead = &(pstapriv->sta_hash[i]);
+ plist = get_next(phead);
+ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+ psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
+ plist = get_next(plist);
+ pstats = &psta->sta_stats;
+
+ if (pstats == NULL)
+ continue;
+ if ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, 6) != _TRUE)
+ && (_rtw_memcmp(psta->cmn.mac_addr, null_addr, 6) != _TRUE)
+ && (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(adapter), 6) != _TRUE)) {
+ RTW_PRINT_SEL(m, "MAC :\t\t"MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr));
+ RTW_PRINT_SEL(m, "data_rx_cnt :\t%llu\n", sta_rx_data_uc_pkts(psta) - pstats->last_rx_data_uc_pkts);
+ pstats->last_rx_data_uc_pkts = sta_rx_data_uc_pkts(psta);
+ RTW_PRINT_SEL(m, "duplicate_cnt :\t%u\n", pstats->duplicate_cnt);
+ pstats->duplicate_cnt = 0;
+ RTW_PRINT_SEL(m, "rx_per_rate_cnt :\n");
+
+ for (j = 0; j < 0x60; j++) {
+ RTW_PRINT_SEL(m, "%08u ", pstats->rxratecnt[j]);
+ pstats->rxratecnt[j] = 0;
+ if ((j%8) == 7)
+ RTW_PRINT_SEL(m, "\n");
+ }
+ RTW_PRINT_SEL(m, "\n");
+ }
+ }
+ }
+ _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+ return 0;
+}
+
+int proc_get_tx_stat(struct seq_file *m, void *v)
+{
+ _irqL irqL;
+ _list *plist, *phead;
+ struct net_device *dev = m->private;
+ _adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+ struct sta_info *psta = NULL;
+ u8 sta_mac[NUM_STA][ETH_ALEN] = {{0}};
+ uint mac_id[NUM_STA];
+ struct stainfo_stats *pstats = NULL;
+ struct sta_priv *pstapriv = &(adapter->stapriv);
+ struct sta_priv *pstapriv_primary = &(GET_PRIMARY_ADAPTER(adapter))->stapriv;
+ u32 i, macid_rec_idx = 0;
+ u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+ u8 null_addr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
+ struct submit_ctx gotc2h;
+
+ _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+ for (i = 0; i < NUM_STA; i++) {
+ phead = &(pstapriv->sta_hash[i]);
+ plist = get_next(phead);
+ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+ psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
+ plist = get_next(plist);
+ if ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, 6) != _TRUE)
+ && (_rtw_memcmp(psta->cmn.mac_addr, null_addr, 6) != _TRUE)
+ && (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(adapter), 6) != _TRUE)) {
+ _rtw_memcpy(&sta_mac[macid_rec_idx][0], psta->cmn.mac_addr, ETH_ALEN);
+ mac_id[macid_rec_idx] = psta->cmn.mac_id;
+ macid_rec_idx++;
+ }
+ }
+ }
+ _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+ for (i = 0; i < macid_rec_idx; i++) {
+ _rtw_memcpy(pstapriv_primary->c2h_sta_mac, &sta_mac[i][0], ETH_ALEN);
+ pstapriv_primary->c2h_adapter_id = adapter->iface_id;
+ rtw_sctx_init(&gotc2h, 60);
+ pstapriv_primary->gotc2h = &gotc2h;
+ rtw_hal_reqtxrpt(adapter, mac_id[i]);
+ if (rtw_sctx_wait(&gotc2h, __func__)) {
+ psta = rtw_get_stainfo(pstapriv, &sta_mac[i][0]);
+ if(psta) {
+ pstats = &psta->sta_stats;
+#ifndef ROKU_PRIVATE
+ RTW_PRINT_SEL(m, "data_sent_cnt :\t%u\n", pstats->tx_ok_cnt + pstats->tx_fail_cnt);
+ RTW_PRINT_SEL(m, "success_cnt :\t%u\n", pstats->tx_ok_cnt);
+ RTW_PRINT_SEL(m, "failure_cnt :\t%u\n", pstats->tx_fail_cnt);
+ RTW_PRINT_SEL(m, "retry_cnt :\t%u\n\n", pstats->tx_retry_cnt);
+#else
+ RTW_PRINT_SEL(m, "MAC: " MAC_FMT " sent: %u fail: %u retry: %u\n",
+ MAC_ARG(&sta_mac[i][0]), pstats->tx_ok_cnt, pstats->tx_fail_cnt, pstats->tx_retry_cnt);
+#endif /* ROKU_PRIVATE */
+
+ } else
+ RTW_PRINT_SEL(m, "STA is gone\n");
+ } else {
+ //to avoid c2h modify counters
+ pstapriv_primary->gotc2h = NULL;
+ _rtw_memset(pstapriv_primary->c2h_sta_mac, 0, ETH_ALEN);
+ pstapriv_primary->c2h_adapter_id = CONFIG_IFACE_NUMBER;
+ RTW_PRINT_SEL(m, "Warming : Query timeout, operation abort!!\n");
+ break;
+ }
+ pstapriv_primary->gotc2h = NULL;
+ _rtw_memset(pstapriv_primary->c2h_sta_mac, 0, ETH_ALEN);
+ pstapriv_primary->c2h_adapter_id = CONFIG_IFACE_NUMBER;
+ }
+ return 0;
+}
+
int proc_get_fwstate(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
@@ -668,8 +871,8 @@ int proc_get_sec_info(struct seq_file *m, void *v)
struct security_priv *sec = &padapter->securitypriv;
RTW_PRINT_SEL(m, "auth_alg=0x%x, enc_alg=0x%x, auth_type=0x%x, enc_type=0x%x\n",
- sec->dot11AuthAlgrthm, sec->dot11PrivacyAlgrthm,
- sec->ndisauthtype, sec->ndisencryptstatus);
+ sec->dot11AuthAlgrthm, sec->dot11PrivacyAlgrthm,
+ sec->ndisauthtype, sec->ndisencryptstatus);
RTW_PRINT_SEL(m, "hw_decrypted=%d\n", sec->hw_decrypted);
@@ -750,12 +953,13 @@ int proc_get_roam_param(struct seq_file *m, void *v)
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
struct mlme_priv *mlme = &adapter->mlmepriv;
- RTW_PRINT_SEL(m, "%12s %12s %11s\n", "rssi_diff_th", "scanr_exp_ms", "scan_int_ms");
- RTW_PRINT_SEL(m, "%-12u %-12u %-11u\n"
- , mlme->roam_rssi_diff_th
- , mlme->roam_scanr_exp_ms
- , mlme->roam_scan_int_ms
- );
+ RTW_PRINT_SEL(m, "%12s %12s %11s %14s\n", "rssi_diff_th", "scanr_exp_ms", "scan_int_ms", "rssi_threshold");
+ RTW_PRINT_SEL(m, "%-12u %-12u %-11u %-14u\n"
+ , mlme->roam_rssi_diff_th
+ , mlme->roam_scanr_exp_ms
+ , mlme->roam_scan_int_ms
+ , mlme->roam_rssi_threshold
+ );
return 0;
}
@@ -770,6 +974,7 @@ ssize_t proc_set_roam_param(struct file *file, const char __user *buffer, size_t
u8 rssi_diff_th;
u32 scanr_exp_ms;
u32 scan_int_ms;
+ u8 rssi_threshold;
if (count < 1)
return -EFAULT;
@@ -781,7 +986,7 @@ ssize_t proc_set_roam_param(struct file *file, const char __user *buffer, size_t
if (buffer && !copy_from_user(tmp, buffer, count)) {
- int num = sscanf(tmp, "%hhu %u %u", &rssi_diff_th, &scanr_exp_ms, &scan_int_ms);
+ int num = sscanf(tmp, "%hhu %u %u %hhu", &rssi_diff_th, &scanr_exp_ms, &scan_int_ms, &rssi_threshold);
if (num >= 1)
mlme->roam_rssi_diff_th = rssi_diff_th;
@@ -789,6 +994,8 @@ ssize_t proc_set_roam_param(struct file *file, const char __user *buffer, size_t
mlme->roam_scanr_exp_ms = scanr_exp_ms;
if (num >= 3)
mlme->roam_scan_int_ms = scan_int_ms;
+ if (num >= 4)
+ mlme->roam_rssi_threshold = rssi_threshold;
}
return count;
@@ -824,6 +1031,45 @@ ssize_t proc_set_roam_tgt_addr(struct file *file, const char __user *buffer, siz
}
#endif /* CONFIG_LAYER2_ROAMING */
+#ifdef CONFIG_RTW_80211R
+ssize_t proc_set_ft_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+ struct net_device *dev = data;
+ _adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+ char tmp[32];
+ u8 flags;
+
+ if (count < 1)
+ return -EFAULT;
+
+ if (count > sizeof(tmp)) {
+ rtw_warn_on(1);
+ return -EFAULT;
+ }
+
+ if (buffer && !copy_from_user(tmp, buffer, count)) {
+ int num = sscanf(tmp, "%hhx", &flags);
+
+ if (num == 1)
+ adapter->mlmepriv.ft_roam.ft_flags = flags;
+ }
+
+ return count;
+
+}
+
+int proc_get_ft_flags(struct seq_file *m, void *v)
+{
+ struct net_device *dev = m->private;
+ _adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+ RTW_PRINT_SEL(m, "0x%02x\n", adapter->mlmepriv.ft_roam.ft_flags);
+
+ return 0;
+}
+#endif
+
int proc_get_qos_option(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
@@ -898,24 +1144,24 @@ int proc_get_scan_param(struct seq_file *m, void *v)
#endif
RTW_PRINT_SEL(m,
- SCAN_PARAM_TITLE_FMT
- SCAN_PARAM_TITLE_FMT_HT
- SCAN_PARAM_TITLE_FMT_BACKOP
- "\n"
- SCAN_PARAM_TITLE_ARG
- SCAN_PARAM_TITLE_ARG_HT
- SCAN_PARAM_TITLE_ARG_BACKOP
- );
+ SCAN_PARAM_TITLE_FMT
+ SCAN_PARAM_TITLE_FMT_HT
+ SCAN_PARAM_TITLE_FMT_BACKOP
+ "\n"
+ SCAN_PARAM_TITLE_ARG
+ SCAN_PARAM_TITLE_ARG_HT
+ SCAN_PARAM_TITLE_ARG_BACKOP
+ );
RTW_PRINT_SEL(m,
- SCAN_PARAM_VALUE_FMT
- SCAN_PARAM_VALUE_FMT_HT
- SCAN_PARAM_VALUE_FMT_BACKOP
- "\n"
- SCAN_PARAM_VALUE_ARG
- SCAN_PARAM_VALUE_ARG_HT
- SCAN_PARAM_VALUE_ARG_BACKOP
- );
+ SCAN_PARAM_VALUE_FMT
+ SCAN_PARAM_VALUE_FMT_HT
+ SCAN_PARAM_VALUE_FMT_BACKOP
+ "\n"
+ SCAN_PARAM_VALUE_ARG
+ SCAN_PARAM_VALUE_ARG_HT
+ SCAN_PARAM_VALUE_ARG_BACKOP
+ );
return 0;
}
@@ -962,13 +1208,13 @@ ssize_t proc_set_scan_param(struct file *file, const char __user *buffer, size_t
if (buffer && !copy_from_user(tmp, buffer, count)) {
int num = sscanf(tmp,
- SCAN_PARAM_INPUT_FMT
- SCAN_PARAM_INPUT_FMT_HT
- SCAN_PARAM_INPUT_FMT_BACKOP
- SCAN_PARAM_INPUT_ARG
- SCAN_PARAM_INPUT_ARG_HT
- SCAN_PARAM_INPUT_ARG_BACKOP
- );
+ SCAN_PARAM_INPUT_FMT
+ SCAN_PARAM_INPUT_FMT_HT
+ SCAN_PARAM_INPUT_FMT_BACKOP
+ SCAN_PARAM_INPUT_ARG
+ SCAN_PARAM_INPUT_ARG_HT
+ SCAN_PARAM_INPUT_ARG_BACKOP
+ );
if (num-- > 0)
ss->scan_ch_ms = scan_ch_ms;
@@ -1083,6 +1329,52 @@ ssize_t proc_set_backop_flags_ap(struct file *file, const char __user *buffer, s
#endif /* CONFIG_SCAN_BACKOP */
+#ifdef CONFIG_RTW_REPEATER_SON
+int proc_get_rson_data(struct seq_file *m, void *v)
+{
+ struct net_device *dev = m->private;
+ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+ char rson_data_str[256];
+
+ rtw_rson_get_property_str(padapter, rson_data_str);
+ RTW_PRINT_SEL(m, "%s\n", rson_data_str);
+ return 0;
+}
+
+ssize_t proc_set_rson_data(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+ struct net_device *dev = data;
+ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+ struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);
+ char tmp[64] = {0};
+ int num;
+ u8 field[10], value[64];
+
+ if (count < 1)
+ return -EFAULT;
+
+ if (count > sizeof(tmp)) {
+ rtw_warn_on(1);
+ return -EFAULT;
+ }
+
+ if (buffer && !copy_from_user(tmp, buffer, count)) {
+ num = sscanf(tmp, "%s %s", field, value);
+ if (num != 2) {
+ RTW_INFO("Invalid format : echo > son_data\n");
+ return count;
+ }
+ RTW_INFO("field=%s value=%s\n", field, value);
+ num = rtw_rson_set_property(padapter, field, value);
+ if (num != 1) {
+ RTW_INFO("Invalid field(%s) or value(%s)\n", field, value);
+ return count;
+ }
+ }
+ return count;
+}
+#endif /*CONFIG_RTW_REPEATER_SON*/
+
int proc_get_survey_info(struct seq_file *m, void *v)
{
_irqL irqL;
@@ -1100,16 +1392,25 @@ int proc_get_survey_info(struct seq_file *m, void *v)
char flag_str[64];
int ielen = 0;
u32 wpsielen = 0;
+#ifdef CONFIG_RTW_MESH
+ const char *ssid_title_str = "ssid/mesh_id";
+#else
+ const char *ssid_title_str = "ssid";
+#endif
_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
phead = get_list_head(queue);
if (!phead)
- return 0;
+ goto _exit;
plist = get_next(phead);
if (!plist)
- return 0;
+ goto _exit;
+
+#ifdef CONFIG_RTW_REPEATER_SON
+ rtw_rson_show_survey_info(m, plist, phead);
+#else
- RTW_PRINT_SEL(m, "%5s %-17s %3s %-3s %-4s %-4s %5s %32s %32s\n", "index", "bssid", "ch", "RSSI", "SdBm", "Noise", "age", "flag", "ssid");
+ RTW_PRINT_SEL(m, "%5s %-17s %3s %-3s %-4s %-4s %5s %32s %32s\n", "index", "bssid", "ch", "RSSI", "SdBm", "Noise", "age", "flag", ssid_title_str);
while (1) {
if (rtw_end_of_queue_search(phead, plist) == _TRUE)
break;
@@ -1125,8 +1426,9 @@ int proc_get_survey_info(struct seq_file *m, void *v)
notify_signal = translate_percentage_to_dbm(pnetwork->network.PhyInfo.SignalStrength);/* dbm */
}
-#if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR)
- rtw_hal_get_odm_var(padapter, HAL_ODM_NOISE_MONITOR, &(pnetwork->network.Configuration.DSConfig), &(notify_noise));
+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
+ if (IS_NM_ENABLE(padapter))
+ notify_noise = rtw_noise_query_by_chan_num(padapter, pnetwork->network.Configuration.DSConfig);
#endif
ie_wpa = rtw_get_wpa_ie(&pnetwork->network.IEs[12], &ielen, pnetwork->network.IELength - 12);
@@ -1140,21 +1442,25 @@ int proc_get_survey_info(struct seq_file *m, void *v)
(ie_wpa2) ? "[WPA2]" : "",
(!ie_wpa && !ie_wpa && ie_cap & BIT(4)) ? "[WEP]" : "",
(ie_wps) ? "[WPS]" : "",
- (pnetwork->network.InfrastructureMode == Ndis802_11IBSS) ? "[IBSS]" : "",
+ (pnetwork->network.InfrastructureMode == Ndis802_11IBSS) ? "[IBSS]" :
+ (pnetwork->network.InfrastructureMode == Ndis802_11_mesh) ? "[MESH]" : "",
(ie_cap & BIT(0)) ? "[ESS]" : "",
(ie_p2p) ? "[P2P]" : "");
RTW_PRINT_SEL(m, "%5d "MAC_FMT" %3d %3d %4d %4d %5d %32s %32s\n",
- ++index,
- MAC_ARG(pnetwork->network.MacAddress),
- pnetwork->network.Configuration.DSConfig,
- (int)pnetwork->network.Rssi,
- notify_signal,
- notify_noise,
- rtw_get_passing_time_ms((u32)pnetwork->last_scanned),
- flag_str,
- pnetwork->network.Ssid.Ssid);
+ ++index,
+ MAC_ARG(pnetwork->network.MacAddress),
+ pnetwork->network.Configuration.DSConfig,
+ (int)pnetwork->network.Rssi,
+ notify_signal,
+ notify_noise,
+ rtw_get_passing_time_ms(pnetwork->last_scanned),
+ flag_str,
+ pnetwork->network.InfrastructureMode == Ndis802_11_mesh ? pnetwork->network.mesh_id.Ssid : pnetwork->network.Ssid.Ssid
+ );
plist = get_next(plist);
}
+#endif
+_exit:
_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
return 0;
@@ -1174,7 +1480,7 @@ ssize_t proc_set_survey_info(struct file *file, const char __user *buffer, size_
return -EFAULT;
#ifdef CONFIG_MP_INCLUDED
- if (rtw_mi_mp_mode_check(padapter)) {
+ if (rtw_mp_mode_check(padapter)) {
RTW_INFO("MP mode block Scan request\n");
goto exit;
}
@@ -1186,38 +1492,39 @@ ssize_t proc_set_survey_info(struct file *file, const char __user *buffer, size_
rtw_ps_deny(padapter, PS_DENY_SCAN);
if (_FAIL == rtw_pwr_wakeup(padapter))
- goto exit;
+ goto cancel_ps_deny;
if (!rtw_is_adapter_up(padapter)) {
RTW_INFO("scan abort!! adapter cannot use\n");
- goto exit;
+ goto cancel_ps_deny;
}
if (rtw_mi_busy_traffic_check(padapter, _FALSE)) {
RTW_INFO("scan abort!! BusyTraffic == _TRUE\n");
- goto exit;
+ goto cancel_ps_deny;
}
if (check_fwstate(pmlmepriv, WIFI_AP_STATE) && check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) {
RTW_INFO("scan abort!! AP mode process WPS\n");
- goto exit;
+ goto cancel_ps_deny;
}
if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY | _FW_UNDER_LINKING) == _TRUE) {
RTW_INFO("scan abort!! fwstate=0x%x\n", pmlmepriv->fw_state);
- goto exit;
+ goto cancel_ps_deny;
}
#ifdef CONFIG_CONCURRENT_MODE
if (rtw_mi_buddy_check_fwstate(padapter,
_FW_UNDER_SURVEY | _FW_UNDER_LINKING | WIFI_UNDER_WPS)) {
RTW_INFO("scan abort!! buddy_fwstate check failed\n");
- goto exit;
+ goto cancel_ps_deny;
}
#endif
- _status = rtw_set_802_11_bssid_list_scan(padapter, NULL, 0, NULL, 0);
+ _status = rtw_set_802_11_bssid_list_scan(padapter, NULL);
-exit:
+cancel_ps_deny:
rtw_ps_deny_cancel(padapter, PS_DENY_SCAN);
+exit:
return count;
}
@@ -1233,17 +1540,16 @@ int proc_get_ap_info(struct seq_file *m, void *v)
psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress);
if (psta) {
- int i;
- struct recv_reorder_ctrl *preorder_ctrl;
-
RTW_PRINT_SEL(m, "SSID=%s\n", cur_network->network.Ssid.Ssid);
- RTW_PRINT_SEL(m, "sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->hwaddr));
+ RTW_PRINT_SEL(m, "sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr));
RTW_PRINT_SEL(m, "cur_channel=%d, cur_bwmode=%d, cur_ch_offset=%d\n", pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset);
RTW_PRINT_SEL(m, "wireless_mode=0x%x, rtsen=%d, cts2slef=%d\n", psta->wireless_mode, psta->rtsen, psta->cts2self);
- RTW_PRINT_SEL(m, "state=0x%x, aid=%d, macid=%d, raid=%d\n", psta->state, psta->aid, psta->mac_id, psta->raid);
+ RTW_PRINT_SEL(m, "state=0x%x, aid=%d, macid=%d, raid=%d\n",
+ psta->state, psta->cmn.aid, psta->cmn.mac_id, psta->cmn.ra_info.rate_id);
#ifdef CONFIG_80211N_HT
RTW_PRINT_SEL(m, "qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate);
- RTW_PRINT_SEL(m, "bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n", psta->bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m);
+ RTW_PRINT_SEL(m, "bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n"
+ , psta->cmn.bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m);
RTW_PRINT_SEL(m, "ampdu_enable = %d\n", psta->htpriv.ampdu_enable);
RTW_PRINT_SEL(m, "agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap);
RTW_PRINT_SEL(m, "ldpc_cap=0x%x, stbc_cap=0x%x, beamform_cap=0x%x\n", psta->htpriv.ldpc_cap, psta->htpriv.stbc_cap, psta->htpriv.beamform_cap);
@@ -1253,7 +1559,6 @@ int proc_get_ap_info(struct seq_file *m, void *v)
RTW_PRINT_SEL(m, "vht_ldpc_cap=0x%x, vht_stbc_cap=0x%x, vht_beamform_cap=0x%x\n", psta->vhtpriv.ldpc_cap, psta->vhtpriv.stbc_cap, psta->vhtpriv.beamform_cap);
RTW_PRINT_SEL(m, "vht_mcs_map=0x%x, vht_highest_rate=0x%x, vht_ampdu_len=%d\n", *(u16 *)psta->vhtpriv.vht_mcs_map, psta->vhtpriv.vht_highest_rate, psta->vhtpriv.ampdu_len);
#endif
-
sta_rx_reorder_ctl_dump(m, psta);
} else
RTW_PRINT_SEL(m, "can't get sta's macaddr, cur_network's macaddr:" MAC_FMT "\n", MAC_ARG(cur_network->network.MacAddress));
@@ -1265,8 +1570,7 @@ ssize_t proc_reset_trx_info(struct file *file, const char __user *buffer, size_t
{
struct net_device *dev = data;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
- struct dvobj_priv *psdpriv = padapter->dvobj;
- struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
+ struct recv_priv *precvpriv = &padapter->recvpriv;
char cmd[32] = {0};
u8 cnt = 0;
@@ -1279,12 +1583,13 @@ ssize_t proc_reset_trx_info(struct file *file, const char __user *buffer, size_t
int num = sscanf(cmd, "%hhx", &cnt);
if (0 == cnt) {
- pdbgpriv->dbg_rx_ampdu_drop_count = 0;
- pdbgpriv->dbg_rx_ampdu_forced_indicate_count = 0;
- pdbgpriv->dbg_rx_ampdu_loss_count = 0;
- pdbgpriv->dbg_rx_dup_mgt_frame_drop_count = 0;
- pdbgpriv->dbg_rx_ampdu_window_shift_cnt = 0;
- pdbgpriv->dbg_rx_conflic_mac_addr_cnt = 0;
+ precvpriv->dbg_rx_ampdu_drop_count = 0;
+ precvpriv->dbg_rx_ampdu_forced_indicate_count = 0;
+ precvpriv->dbg_rx_ampdu_loss_count = 0;
+ precvpriv->dbg_rx_dup_mgt_frame_drop_count = 0;
+ precvpriv->dbg_rx_ampdu_window_shift_cnt = 0;
+ precvpriv->dbg_rx_conflic_mac_addr_cnt = 0;
+ precvpriv->dbg_rx_drop_count = 0;
}
}
@@ -1298,9 +1603,15 @@ int proc_get_trx_info(struct seq_file *m, void *v)
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
struct recv_priv *precvpriv = &padapter->recvpriv;
- struct dvobj_priv *psdpriv = padapter->dvobj;
- struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
struct hw_xmit *phwxmit;
+ u16 vo_params[4], vi_params[4], be_params[4], bk_params[4];
+
+ padapter->hal_func.read_wmmedca_reg(padapter, vo_params, vi_params, be_params, bk_params);
+
+ RTW_PRINT_SEL(m, "wmm_edca_vo, aifs = %u us, cw_min = %u, cw_max = %u, txop_limit = %u us\n", vo_params[0], vo_params[1], vo_params[2], vo_params[3]);
+ RTW_PRINT_SEL(m, "wmm_edca_vi, aifs = %u us, cw_min = %u, cw_max = %u, txop_limit = %u us\n", vi_params[0], vi_params[1], vi_params[2], vi_params[3]);
+ RTW_PRINT_SEL(m, "wmm_edca_be, aifs = %u us, cw_min = %u, cw_max = %u, txop_limit = %u us\n", be_params[0], be_params[1], be_params[2], be_params[3]);
+ RTW_PRINT_SEL(m, "wmm_edca_bk, aifs = %u us, cw_min = %u, cw_max = %u, txop_limit = %u us\n", bk_params[0], bk_params[1], bk_params[2], bk_params[3]);
dump_os_queue(m, padapter);
@@ -1316,39 +1627,59 @@ int proc_get_trx_info(struct seq_file *m, void *v)
RTW_PRINT_SEL(m, "%d, hwq.accnt=%d\n", i, phwxmit->accnt);
}
+ rtw_hal_get_hwreg(padapter, HW_VAR_DUMP_MAC_TXFIFO, (u8 *)m);
+
#ifdef CONFIG_USB_HCI
RTW_PRINT_SEL(m, "rx_urb_pending_cn=%d\n", ATOMIC_READ(&(precvpriv->rx_pending_cnt)));
#endif
+ dump_rx_bh_tk(m, &GET_PRIMARY_ADAPTER(padapter)->recvpriv);
+
/* Folowing are RX info */
+ RTW_PRINT_SEL(m, "RX: Count of Packets dropped by Driver: %llu\n", (unsigned long long)precvpriv->dbg_rx_drop_count);
/* Counts of packets whose seq_num is less than preorder_ctrl->indicate_seq, Ex delay, retransmission, redundant packets and so on */
- RTW_PRINT_SEL(m, "Rx: Counts of Packets Whose Seq_Num Less Than Reorder Control Seq_Num: %llu\n", (unsigned long long)pdbgpriv->dbg_rx_ampdu_drop_count);
+ RTW_PRINT_SEL(m, "Rx: Counts of Packets Whose Seq_Num Less Than Reorder Control Seq_Num: %llu\n", (unsigned long long)precvpriv->dbg_rx_ampdu_drop_count);
/* How many times the Rx Reorder Timer is triggered. */
- RTW_PRINT_SEL(m, "Rx: Reorder Time-out Trigger Counts: %llu\n", (unsigned long long)pdbgpriv->dbg_rx_ampdu_forced_indicate_count);
+ RTW_PRINT_SEL(m, "Rx: Reorder Time-out Trigger Counts: %llu\n", (unsigned long long)precvpriv->dbg_rx_ampdu_forced_indicate_count);
/* Total counts of packets loss */
- RTW_PRINT_SEL(m, "Rx: Packet Loss Counts: %llu\n", (unsigned long long)pdbgpriv->dbg_rx_ampdu_loss_count);
- RTW_PRINT_SEL(m, "Rx: Duplicate Management Frame Drop Count: %llu\n", (unsigned long long)pdbgpriv->dbg_rx_dup_mgt_frame_drop_count);
- RTW_PRINT_SEL(m, "Rx: AMPDU BA window shift Count: %llu\n", (unsigned long long)pdbgpriv->dbg_rx_ampdu_window_shift_cnt);
+ RTW_PRINT_SEL(m, "Rx: Packet Loss Counts: %llu\n", (unsigned long long)precvpriv->dbg_rx_ampdu_loss_count);
+ RTW_PRINT_SEL(m, "Rx: Duplicate Management Frame Drop Count: %llu\n", (unsigned long long)precvpriv->dbg_rx_dup_mgt_frame_drop_count);
+ RTW_PRINT_SEL(m, "Rx: AMPDU BA window shift Count: %llu\n", (unsigned long long)precvpriv->dbg_rx_ampdu_window_shift_cnt);
/*The same mac addr counts*/
- RTW_PRINT_SEL(m, "Rx: Conflict MAC Address Frames Count: %llu\n", (unsigned long long)pdbgpriv->dbg_rx_conflic_mac_addr_cnt);
+ RTW_PRINT_SEL(m, "Rx: Conflict MAC Address Frames Count: %llu\n", (unsigned long long)precvpriv->dbg_rx_conflic_mac_addr_cnt);
return 0;
}
-int proc_get_dis_pwt(struct seq_file *m, void *v)
+int proc_get_rate_ctl(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
- _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
- u8 dis_pwt = 0;
- rtw_hal_get_def_var(padapter, HAL_DEF_DBG_DIS_PWT, &(dis_pwt));
- RTW_PRINT_SEL(m, " Tx Power training mode:%s\n", (dis_pwt == _TRUE) ? "Disable" : "Enable");
+ _adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+ u8 data_rate = 0, sgi = 0, data_fb = 0;
+
+ if (adapter->fix_rate != 0xff) {
+ data_rate = adapter->fix_rate & 0x7F;
+ sgi = adapter->fix_rate >> 7;
+ data_fb = adapter->data_fb ? 1 : 0;
+ RTW_PRINT_SEL(m, "FIXED %s%s%s\n"
+ , HDATA_RATE(data_rate)
+ , data_rate > DESC_RATE54M ? (sgi ? " SGI" : " LGI") : ""
+ , data_fb ? " FB" : ""
+ );
+ RTW_PRINT_SEL(m, "0x%02x %u\n", adapter->fix_rate, adapter->data_fb);
+ } else
+ RTW_PRINT_SEL(m, "RA\n");
+
return 0;
}
-ssize_t proc_set_dis_pwt(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+
+ssize_t proc_set_rate_ctl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
- _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
- char tmp[4] = {0};
- u8 dis_pwt = 0;
+ _adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+ char tmp[32];
+ u8 fix_rate;
+ u8 data_fb;
if (count < 1)
return -EFAULT;
@@ -1360,47 +1691,51 @@ ssize_t proc_set_dis_pwt(struct file *file, const char __user *buffer, size_t co
if (buffer && !copy_from_user(tmp, buffer, count)) {
- int num = sscanf(tmp, "%hhx", &dis_pwt);
- RTW_INFO("Set Tx Power training mode:%s\n", (dis_pwt == _TRUE) ? "Disable" : "Enable");
+ int num = sscanf(tmp, "%hhx %hhu", &fix_rate, &data_fb);
- if (num >= 1)
- rtw_hal_set_def_var(padapter, HAL_DEF_DBG_DIS_PWT, &(dis_pwt));
+ if (num >= 1) {
+ u8 fix_rate_ori = adapter->fix_rate;
+
+ adapter->fix_rate = fix_rate;
+ if (fix_rate == 0xFF)
+ hal_data->ForcedDataRate = 0;
+ else
+ hal_data->ForcedDataRate = hw_rate_to_m_rate(fix_rate & 0x7F);
+
+ if (adapter->fix_bw != 0xFF && fix_rate_ori != fix_rate)
+ rtw_update_tx_rate_bmp(adapter_to_dvobj(adapter));
+ }
+ if (num >= 2)
+ adapter->data_fb = data_fb ? 1 : 0;
}
return count;
-
}
-int proc_get_rate_ctl(struct seq_file *m, void *v)
+#ifdef CONFIG_AP_MODE
+int proc_get_bmc_tx_rate(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
- int i;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
- u8 data_rate = 0, sgi = 0, data_fb = 0;
+ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
+ struct sta_info *psta = NULL;
- if (adapter->fix_rate != 0xff) {
- data_rate = adapter->fix_rate & 0x7F;
- sgi = adapter->fix_rate >> 7;
- data_fb = adapter->data_fb ? 1 : 0;
- RTW_PRINT_SEL(m, "FIXED %s%s%s\n"
- , HDATA_RATE(data_rate)
- , data_rate > DESC_RATE54M ? (sgi ? " SGI" : " LGI") : ""
- , data_fb ? " FB" : ""
- );
- RTW_PRINT_SEL(m, "0x%02x %u\n", adapter->fix_rate, adapter->data_fb);
- } else
- RTW_PRINT_SEL(m, "RA\n");
+ if (!MLME_IS_AP(adapter) && !MLME_IS_MESH(adapter)) {
+ RTW_PRINT_SEL(m, "[ERROR] Not in SoftAP/Mesh mode !!\n");
+ return 0;
+ }
+ RTW_PRINT_SEL(m, " BMC Tx rate - %s\n", MGN_RATE_STR(adapter->bmc_tx_rate));
return 0;
}
-ssize_t proc_set_rate_ctl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+ssize_t proc_set_bmc_tx_rate(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
char tmp[32];
- u8 fix_rate;
- u8 data_fb;
+ u8 bmc_tx_rate;
if (count < 1)
return -EFAULT;
@@ -1412,16 +1747,58 @@ ssize_t proc_set_rate_ctl(struct file *file, const char __user *buffer, size_t c
if (buffer && !copy_from_user(tmp, buffer, count)) {
- int num = sscanf(tmp, "%hhx %hhu", &fix_rate, &data_fb);
+ int num = sscanf(tmp, "%hhx", &bmc_tx_rate);
if (num >= 1)
- adapter->fix_rate = fix_rate;
- if (num >= 2)
- adapter->data_fb = data_fb ? 1 : 0;
+ /*adapter->bmc_tx_rate = hw_rate_to_m_rate(bmc_tx_rate);*/
+ adapter->bmc_tx_rate = bmc_tx_rate;
+ }
+
+ return count;
+}
+#endif /*CONFIG_AP_MODE*/
+
+
+int proc_get_tx_power_offset(struct seq_file *m, void *v)
+{
+ struct net_device *dev = m->private;
+ int i;
+ _adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+
+ RTW_PRINT_SEL(m, "Tx power offset - %u\n", adapter->power_offset);
+ return 0;
+}
+
+ssize_t proc_set_tx_power_offset(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+ struct net_device *dev = data;
+ _adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+ char tmp[32];
+ u8 power_offset = 0;
+
+ if (count < 1)
+ return -EFAULT;
+
+ if (count > sizeof(tmp)) {
+ rtw_warn_on(1);
+ return -EFAULT;
+ }
+
+ if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+ int num = sscanf(tmp, "%hhu", &power_offset);
+
+ if (num >= 1) {
+ if (power_offset > 5)
+ power_offset = 0;
+
+ adapter->power_offset = power_offset;
+ }
}
return count;
}
+
int proc_get_bw_ctl(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
@@ -1430,7 +1807,7 @@ int proc_get_bw_ctl(struct seq_file *m, void *v)
if (adapter->fix_bw != 0xff) {
data_bw = adapter->fix_bw;
- RTW_PRINT_SEL(m, "FIXED %s\n", HDATA_BW(data_bw));
+ RTW_PRINT_SEL(m, "FIXED %s\n", ch_width_str(data_bw));
} else
RTW_PRINT_SEL(m, "Auto\n");
@@ -1455,8 +1832,14 @@ ssize_t proc_set_bw_ctl(struct file *file, const char __user *buffer, size_t cou
if (buffer && !copy_from_user(tmp, buffer, count)) {
int num = sscanf(tmp, "%hhu", &fix_bw);
- if (num >= 1)
+ if (num >= 1) {
+ u8 fix_bw_ori = adapter->fix_bw;
+
adapter->fix_bw = fix_bw;
+
+ if (adapter->fix_rate != 0xFF && fix_bw_ori != fix_bw)
+ rtw_update_tx_rate_bmp(adapter_to_dvobj(adapter));
+ }
}
return count;
@@ -1504,6 +1887,30 @@ ssize_t proc_set_rx_cnt_dump(struct file *file, const char __user *buffer, size_
return count;
}
#endif
+
+static u8 fwdl_test_chksum_fail = 0;
+static u8 fwdl_test_wintint_rdy_fail = 0;
+
+bool rtw_fwdl_test_trigger_chksum_fail(void)
+{
+ if (fwdl_test_chksum_fail) {
+ RTW_PRINT("fwdl test case: trigger chksum_fail\n");
+ fwdl_test_chksum_fail--;
+ return _TRUE;
+ }
+ return _FALSE;
+}
+
+bool rtw_fwdl_test_trigger_wintint_rdy_fail(void)
+{
+ if (fwdl_test_wintint_rdy_fail) {
+ RTW_PRINT("fwdl test case: trigger wintint_rdy_fail\n");
+ fwdl_test_wintint_rdy_fail--;
+ return _TRUE;
+ }
+ return _FALSE;
+}
+
ssize_t proc_set_fwdl_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
@@ -1525,6 +1932,18 @@ ssize_t proc_set_fwdl_test_case(struct file *file, const char __user *buffer, si
return count;
}
+static u8 del_rx_ampdu_test_no_tx_fail = 0;
+
+bool rtw_del_rx_ampdu_test_trigger_no_tx_fail(void)
+{
+ if (del_rx_ampdu_test_no_tx_fail) {
+ RTW_PRINT("del_rx_ampdu test case: trigger no_tx_fail\n");
+ del_rx_ampdu_test_no_tx_fail--;
+ return _TRUE;
+ }
+ return _FALSE;
+}
+
ssize_t proc_set_del_rx_ampdu_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
@@ -1546,30 +1965,19 @@ ssize_t proc_set_del_rx_ampdu_test_case(struct file *file, const char __user *bu
return count;
}
-#ifdef CONFIG_DFS_MASTER
-int proc_get_dfs_master_test_case(struct seq_file *m, void *v)
-{
- struct net_device *dev = m->private;
- _adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
- struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
-
- RTW_PRINT_SEL(m, "%-24s %-19s\n", "radar_detect_trigger_non", "choose_dfs_ch_first");
- RTW_PRINT_SEL(m, "%24hhu %19hhu\n"
- , rfctl->dbg_dfs_master_radar_detect_trigger_non
- , rfctl->dbg_dfs_master_choose_dfs_ch_first
- );
+static u32 g_wait_hiq_empty_ms = 0;
- return 0;
+u32 rtw_get_wait_hiq_empty_ms(void)
+{
+ return g_wait_hiq_empty_ms;
}
-ssize_t proc_set_dfs_master_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+ssize_t proc_set_wait_hiq_empty(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
- _adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
- struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
char tmp[32];
- u8 radar_detect_trigger_non;
- u8 choose_dfs_ch_first;
+ int num;
if (count < 1)
return -EFAULT;
@@ -1579,25 +1987,36 @@ ssize_t proc_set_dfs_master_test_case(struct file *file, const char __user *buff
return -EFAULT;
}
- if (buffer && !copy_from_user(tmp, buffer, count)) {
- int num = sscanf(tmp, "%hhu %hhu", &radar_detect_trigger_non, &choose_dfs_ch_first);
-
- if (num >= 1)
- rfctl->dbg_dfs_master_radar_detect_trigger_non = radar_detect_trigger_non;
- if (num >= 2)
- rfctl->dbg_dfs_master_choose_dfs_ch_first = choose_dfs_ch_first;
- }
+ if (buffer && !copy_from_user(tmp, buffer, count))
+ num = sscanf(tmp, "%u", &g_wait_hiq_empty_ms);
return count;
}
-#endif /* CONFIG_DFS_MASTER */
-ssize_t proc_set_wait_hiq_empty(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+static systime sta_linking_test_start_time = 0;
+static u32 sta_linking_test_wait_ms = 0;
+static u8 sta_linking_test_force_fail = 0;
+
+void rtw_sta_linking_test_set_start(void)
+{
+ sta_linking_test_start_time = rtw_get_current_time();
+}
+
+bool rtw_sta_linking_test_wait_done(void)
+{
+ return rtw_get_passing_time_ms(sta_linking_test_start_time) >= sta_linking_test_wait_ms;
+}
+
+bool rtw_sta_linking_test_force_fail(void)
+{
+ return sta_linking_test_force_fail;
+}
+
+ssize_t proc_set_sta_linking_test(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
char tmp[32];
- int num;
if (count < 1)
return -EFAULT;
@@ -1607,13 +2026,21 @@ ssize_t proc_set_wait_hiq_empty(struct file *file, const char __user *buffer, si
return -EFAULT;
}
- if (buffer && !copy_from_user(tmp, buffer, count))
- num = sscanf(tmp, "%u", &g_wait_hiq_empty_ms);
+ if (buffer && !copy_from_user(tmp, buffer, count)) {
+ u32 wait_ms = 0;
+ u8 force_fail = 0;
+ int num = sscanf(tmp, "%u %hhu", &wait_ms, &force_fail);
+
+ if (num >= 1)
+ sta_linking_test_wait_ms = wait_ms;
+ if (num >= 2)
+ sta_linking_test_force_fail = force_fail;
+ }
return count;
}
-int proc_get_suspend_resume_info(struct seq_file *m, void *v)
+int proc_get_ps_dbg_info(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
@@ -1648,9 +2075,39 @@ int proc_get_suspend_resume_info(struct seq_file *m, void *v)
RTW_PRINT_SEL(m, "dbg_rpwm_toogle_cnt=%d\n", pdbgpriv->dbg_rpwm_toogle_cnt);
RTW_PRINT_SEL(m, "dbg_rpwm_timeout_fail_cnt=%d\n", pdbgpriv->dbg_rpwm_timeout_fail_cnt);
RTW_PRINT_SEL(m, "dbg_sreset_cnt=%d\n", pdbgpriv->dbg_sreset_cnt);
+ RTW_PRINT_SEL(m, "dbg_fw_mem_dl_error_cnt=%d\n", pdbgpriv->dbg_fw_mem_dl_error_cnt);
return 0;
}
+ssize_t proc_set_ps_dbg_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+ struct net_device *dev = data;
+ _adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+ struct dvobj_priv *dvobj = adapter->dvobj;
+ struct debug_priv *pdbgpriv = &dvobj->drv_dbg;
+ char tmp[32];
+ u8 ps_dbg_cmd_id;
+
+ if (count < 1)
+ return -EFAULT;
+
+ if (count > sizeof(tmp)) {
+ rtw_warn_on(1);
+ return -EFAULT;
+ }
+
+ if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+ int num = sscanf(tmp, "%hhx", &ps_dbg_cmd_id);
+
+ if (ps_dbg_cmd_id == 1) /*Clean all*/
+ _rtw_memset(pdbgpriv, 0, sizeof(struct debug_priv));
+
+ }
+
+ return count;
+}
+
#ifdef CONFIG_DBG_COUNTER
@@ -1921,8 +2378,11 @@ int proc_get_hw_status(struct seq_file *m, void *v)
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
struct dvobj_priv *dvobj = padapter->dvobj;
struct debug_priv *pdbgpriv = &dvobj->drv_dbg;
+ struct registry_priv *regsty = dvobj_to_regsty(dvobj);
- if (pdbgpriv->dbg_rx_fifo_last_overflow == 1
+ if (regsty->check_hw_status == 0)
+ RTW_PRINT_SEL(m, "RX FIFO full count: not check in watch dog\n");
+ else if (pdbgpriv->dbg_rx_fifo_last_overflow == 1
&& pdbgpriv->dbg_rx_fifo_curr_overflow == 1
&& pdbgpriv->dbg_rx_fifo_diff_overflow == 1
)
@@ -1934,6 +2394,37 @@ int proc_get_hw_status(struct seq_file *m, void *v)
return 0;
}
+
+ssize_t proc_set_hw_status(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+ struct net_device *dev = data;
+ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+ struct dvobj_priv *dvobj = padapter->dvobj;
+ struct registry_priv *regsty = dvobj_to_regsty(dvobj);
+ char tmp[32];
+ u32 enable;
+
+ if (count < 1)
+ return -EFAULT;
+
+ if (count > sizeof(tmp)) {
+ rtw_warn_on(1);
+ return -EFAULT;
+ }
+
+ if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+ int num = sscanf(tmp, "%d ", &enable);
+
+ if (regsty && enable <= 1) {
+ regsty->check_hw_status = enable;
+ RTW_INFO("check_hw_status=%d\n", regsty->check_hw_status);
+ }
+ }
+
+ return count;
+}
+
int proc_get_trx_info_debug(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
@@ -1963,9 +2454,27 @@ int proc_get_rx_signal(struct seq_file *m, void *v)
/* RTW_PRINT_SEL(m, "rxpwdb:%d\n", padapter->recvpriv.rxpwdb); */
RTW_PRINT_SEL(m, "signal_strength:%u\n", padapter->recvpriv.signal_strength);
RTW_PRINT_SEL(m, "signal_qual:%u\n", padapter->recvpriv.signal_qual);
-
- rtw_get_noise(padapter);
- RTW_PRINT_SEL(m, "noise:%d\n", padapter->recvpriv.noise);
+#ifdef CONFIG_MP_INCLUDED
+ if (padapter->registrypriv.mp_mode == 1) {
+ if (padapter->mppriv.antenna_rx == ANTENNA_A)
+ RTW_PRINT_SEL(m, "Antenna: A\n");
+ else if (padapter->mppriv.antenna_rx == ANTENNA_B)
+ RTW_PRINT_SEL(m, "Antenna: B\n");
+ else if (padapter->mppriv.antenna_rx == ANTENNA_C)
+ RTW_PRINT_SEL(m, "Antenna: C\n");
+ else if (padapter->mppriv.antenna_rx == ANTENNA_D)
+ RTW_PRINT_SEL(m, "Antenna: D\n");
+ else if (padapter->mppriv.antenna_rx == ANTENNA_AB)
+ RTW_PRINT_SEL(m, "Antenna: AB\n");
+ else if (padapter->mppriv.antenna_rx == ANTENNA_BC)
+ RTW_PRINT_SEL(m, "Antenna: BC\n");
+ else if (padapter->mppriv.antenna_rx == ANTENNA_CD)
+ RTW_PRINT_SEL(m, "Antenna: CD\n");
+ else
+ RTW_PRINT_SEL(m, "Antenna: __\n");
+ return 0;
+ }
+#endif
#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
rtw_odm_get_perpkt_rssi(m, padapter);
rtw_get_raw_rssi_info(m, padapter);
@@ -2075,6 +2584,8 @@ ssize_t proc_set_bw_mode(struct file *file, const char __user *buffer, size_t co
struct registry_priv *pregpriv = &padapter->registrypriv;
char tmp[32];
u32 mode;
+ u8 bw_2g;
+ u8 bw_5g;
if (count < 1)
return -EFAULT;
@@ -2086,12 +2597,14 @@ ssize_t proc_set_bw_mode(struct file *file, const char __user *buffer, size_t co
if (buffer && !copy_from_user(tmp, buffer, count)) {
- int num = sscanf(tmp, "%d ", &mode);
+ int num = sscanf(tmp, "%x ", &mode);
+ bw_5g = mode >> 4;
+ bw_2g = mode & 0x0f;
- if (pregpriv && mode < 2) {
+ if (pregpriv && bw_2g <= 4 && bw_5g <= 4) {
pregpriv->bw_mode = mode;
- printk("bw_mode=%d\n", mode);
+ printk("bw_mode=0x%x\n", mode);
}
}
@@ -2132,7 +2645,7 @@ ssize_t proc_set_ampdu_enable(struct file *file, const char __user *buffer, size
int num = sscanf(tmp, "%d ", &mode);
- if (pregpriv && mode < 3) {
+ if (pregpriv && mode < 2) {
pregpriv->ampdu_enable = mode;
printk("ampdu_enable=%d\n", mode);
}
@@ -2172,6 +2685,20 @@ int proc_get_mac_rptbuf(struct seq_file *m, void *v)
return 0;
}
+void dump_regsty_rx_ampdu_size_limit(void *sel, _adapter *adapter)
+{
+ struct registry_priv *regsty = adapter_to_regsty(adapter);
+ int i;
+
+ RTW_PRINT_SEL(sel, "%-3s %-3s %-3s %-3s %-4s\n"
+ , "", "20M", "40M", "80M", "160M");
+ for (i = 0; i < 4; i++)
+ RTW_PRINT_SEL(sel, "%dSS %3u %3u %3u %4u\n", i + 1
+ , regsty->rx_ampdu_sz_limit_by_nss_bw[i][0]
+ , regsty->rx_ampdu_sz_limit_by_nss_bw[i][1]
+ , regsty->rx_ampdu_sz_limit_by_nss_bw[i][2]
+ , regsty->rx_ampdu_sz_limit_by_nss_bw[i][3]);
+}
int proc_get_rx_ampdu(struct seq_file *m, void *v)
{
@@ -2185,16 +2712,18 @@ int proc_get_rx_ampdu(struct seq_file *m, void *v)
RTW_PRINT_SEL(m, "%u%s\n", padapter->fix_rx_ampdu_accept, "(fixed)");
_RTW_PRINT_SEL(m, "size: ");
- if (padapter->fix_rx_ampdu_size == RX_AMPDU_SIZE_INVALID)
- RTW_PRINT_SEL(m, "%u%s\n", rtw_rx_ampdu_size(padapter), "(auto)");
- else
+ if (padapter->fix_rx_ampdu_size == RX_AMPDU_SIZE_INVALID) {
+ RTW_PRINT_SEL(m, "%u%s\n", rtw_rx_ampdu_size(padapter), "(auto) with conditional limit:");
+ dump_regsty_rx_ampdu_size_limit(m, padapter);
+ } else
RTW_PRINT_SEL(m, "%u%s\n", padapter->fix_rx_ampdu_size, "(fixed)");
+ RTW_PRINT_SEL(m, "\n");
RTW_PRINT_SEL(m, "%19s %17s\n", "fix_rx_ampdu_accept", "fix_rx_ampdu_size");
_RTW_PRINT_SEL(m, "%-19d %-17u\n"
- , padapter->fix_rx_ampdu_accept
- , padapter->fix_rx_ampdu_size);
+ , padapter->fix_rx_ampdu_accept
+ , padapter->fix_rx_ampdu_size);
return 0;
}
@@ -2278,19 +2807,61 @@ ssize_t proc_set_rx_ampdu_factor(struct file *file, const char __user *buffer
return count;
}
-int proc_get_rx_ampdu_density(struct seq_file *m, void *v)
+int proc_get_tx_max_agg_num(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
if (padapter)
- RTW_PRINT_SEL(m, "rx ampdu densityg = %x\n", padapter->driver_rx_ampdu_spacing);
+ RTW_PRINT_SEL(m, "tx max AMPDU num = 0x%02x\n", padapter->driver_tx_max_agg_num);
return 0;
}
-ssize_t proc_set_rx_ampdu_density(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+ssize_t proc_set_tx_max_agg_num(struct file *file, const char __user *buffer
+ , size_t count, loff_t *pos, void *data)
+{
+ struct net_device *dev = data;
+ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+ char tmp[32];
+ u8 agg_num;
+
+ if (count < 1)
+ return -EFAULT;
+
+ if (count > sizeof(tmp)) {
+ rtw_warn_on(1);
+ return -EFAULT;
+ }
+
+ if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+ int num = sscanf(tmp, "%hhx ", &agg_num);
+
+ if (padapter && (num == 1)) {
+ RTW_INFO("padapter->driver_tx_max_agg_num = 0x%02x\n", agg_num);
+
+ padapter->driver_tx_max_agg_num = agg_num;
+ }
+ }
+
+ return count;
+}
+
+int proc_get_rx_ampdu_density(struct seq_file *m, void *v)
+{
+ struct net_device *dev = m->private;
+ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+
+ if (padapter)
+ RTW_PRINT_SEL(m, "rx ampdu densityg = %x\n", padapter->driver_rx_ampdu_spacing);
+
+ return 0;
+}
+
+ssize_t proc_set_rx_ampdu_density(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
@@ -2365,7 +2936,8 @@ ssize_t proc_set_tx_ampdu_density(struct file *file, const char __user *buffer,
return count;
}
-#ifdef TX_AMSDU
+
+#ifdef CONFIG_TX_AMSDU
int proc_get_tx_amsdu(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
@@ -2424,14 +2996,13 @@ ssize_t proc_set_tx_amsdu(struct file *file, const char __user *buffer, size_t c
return count;
}
-
int proc_get_tx_amsdu_rate(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
if (padapter)
- RTW_PRINT_SEL(m, "tx ampdu rate = %d Mbps\n", padapter->tx_amsdu_rate);
+ RTW_PRINT_SEL(m, "tx amsdu rate = %d Mbps\n", padapter->tx_amsdu_rate);
return 0;
}
@@ -2456,14 +3027,14 @@ ssize_t proc_set_tx_amsdu_rate(struct file *file, const char __user *buffer, siz
int num = sscanf(tmp, "%d ", &amsdu_rate);
if (padapter && (num == 1)) {
- RTW_INFO("padapter->tx_amsdu_rate = %d Mbps\n", amsdu_rate);
+ RTW_INFO("padapter->tx_amsdu_rate = %x\n", amsdu_rate);
padapter->tx_amsdu_rate = amsdu_rate;
}
}
return count;
}
-#endif
+#endif /* CONFIG_TX_AMSDU */
#endif /* CONFIG_80211N_HT */
int proc_get_en_fwps(struct seq_file *m, void *v)
@@ -2527,6 +3098,144 @@ int proc_get_two_path_rssi(struct seq_file *m, void *v)
}
*/
#ifdef CONFIG_80211N_HT
+void rtw_dump_dft_phy_cap(void *sel, _adapter *adapter)
+{
+ struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
+ struct ht_priv *phtpriv = &pmlmepriv->htpriv;
+ #ifdef CONFIG_80211AC_VHT
+ struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
+ #endif
+
+ #ifdef CONFIG_80211AC_VHT
+ RTW_PRINT_SEL(sel, "[DFT CAP] VHT STBC Tx : %s\n", (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX)) ? "V" : "X");
+ RTW_PRINT_SEL(sel, "[DFT CAP] VHT STBC Rx : %s\n", (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_RX)) ? "V" : "X");
+ #endif
+ RTW_PRINT_SEL(sel, "[DFT CAP] HT STBC Tx : %s\n", (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX)) ? "V" : "X");
+ RTW_PRINT_SEL(sel, "[DFT CAP] HT STBC Rx : %s\n\n", (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_RX)) ? "V" : "X");
+
+ #ifdef CONFIG_80211AC_VHT
+ RTW_PRINT_SEL(sel, "[DFT CAP] VHT LDPC Tx : %s\n", (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_TX)) ? "V" : "X");
+ RTW_PRINT_SEL(sel, "[DFT CAP] VHT LDPC Rx : %s\n", (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_RX)) ? "V" : "X");
+ #endif
+ RTW_PRINT_SEL(sel, "[DFT CAP] HT LDPC Tx : %s\n", (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_TX)) ? "V" : "X");
+ RTW_PRINT_SEL(sel, "[DFT CAP] HT LDPC Rx : %s\n\n", (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_RX)) ? "V" : "X");
+
+ #ifdef CONFIG_BEAMFORMING
+ #ifdef CONFIG_80211AC_VHT
+ RTW_PRINT_SEL(sel, "[DFT CAP] VHT MU Bfer : %s\n", (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) ? "V" : "X");
+ RTW_PRINT_SEL(sel, "[DFT CAP] VHT MU Bfee : %s\n", (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)) ? "V" : "X");
+ RTW_PRINT_SEL(sel, "[DFT CAP] VHT SU Bfer : %s\n", (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) ? "V" : "X");
+ RTW_PRINT_SEL(sel, "[DFT CAP] VHT SU Bfee : %s\n", (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) ? "V" : "X");
+ #endif
+ RTW_PRINT_SEL(sel, "[DFT CAP] HT Bfer : %s\n", (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) ? "V" : "X");
+ RTW_PRINT_SEL(sel, "[DFT CAP] HT Bfee : %s\n", (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) ? "V" : "X");
+ #endif
+}
+
+void rtw_get_dft_phy_cap(void *sel, _adapter *adapter)
+{
+ RTW_PRINT_SEL(sel, "\n ======== PHY CAP protocol ========\n");
+ rtw_ht_use_default_setting(adapter);
+ #ifdef CONFIG_80211AC_VHT
+ rtw_vht_use_default_setting(adapter);
+ #endif
+ rtw_dump_dft_phy_cap(sel, adapter);
+}
+
+void rtw_dump_drv_phy_cap(void *sel, _adapter *adapter)
+{
+ struct registry_priv *pregistry_priv = &adapter->registrypriv;
+
+ RTW_PRINT_SEL(sel, "\n ======== DRV's configuration ========\n");
+ #if 0
+ RTW_PRINT_SEL(sel, "[DRV CAP] TRx Capability : 0x%08x\n", phy_spec->trx_cap);
+ RTW_PRINT_SEL(sel, "[DRV CAP] Tx Stream Num Index : %d\n", (phy_spec->trx_cap >> 24) & 0xFF); /*Tx Stream Num Index [31:24]*/
+ RTW_PRINT_SEL(sel, "[DRV CAP] Rx Stream Num Index : %d\n", (phy_spec->trx_cap >> 16) & 0xFF); /*Rx Stream Num Index [23:16]*/
+ RTW_PRINT_SEL(sel, "[DRV CAP] Tx Path Num Index : %d\n", (phy_spec->trx_cap >> 8) & 0xFF);/*Tx Path Num Index [15:8]*/
+ RTW_PRINT_SEL(sel, "[DRV CAP] Rx Path Num Index : %d\n", (phy_spec->trx_cap & 0xFF));/*Rx Path Num Index [7:0]*/
+ #endif
+
+ RTW_PRINT_SEL(sel, "[DRV CAP] STBC Capability : 0x%02x\n", pregistry_priv->stbc_cap);
+ RTW_PRINT_SEL(sel, "[DRV CAP] VHT STBC Tx : %s\n", (TEST_FLAG(pregistry_priv->stbc_cap, BIT1)) ? "V" : "X"); /*BIT1: Enable VHT STBC Tx*/
+ RTW_PRINT_SEL(sel, "[DRV CAP] VHT STBC Rx : %s\n", (TEST_FLAG(pregistry_priv->stbc_cap, BIT0)) ? "V" : "X"); /*BIT0: Enable VHT STBC Rx*/
+ RTW_PRINT_SEL(sel, "[DRV CAP] HT STBC Tx : %s\n", (TEST_FLAG(pregistry_priv->stbc_cap, BIT5)) ? "V" : "X"); /*BIT5: Enable HT STBC Tx*/
+ RTW_PRINT_SEL(sel, "[DRV CAP] HT STBC Rx : %s\n\n", (TEST_FLAG(pregistry_priv->stbc_cap, BIT4)) ? "V" : "X"); /*BIT4: Enable HT STBC Rx*/
+
+ RTW_PRINT_SEL(sel, "[DRV CAP] LDPC Capability : 0x%02x\n", pregistry_priv->ldpc_cap);
+ RTW_PRINT_SEL(sel, "[DRV CAP] VHT LDPC Tx : %s\n", (TEST_FLAG(pregistry_priv->ldpc_cap, BIT1)) ? "V" : "X"); /*BIT1: Enable VHT LDPC Tx*/
+ RTW_PRINT_SEL(sel, "[DRV CAP] VHT LDPC Rx : %s\n", (TEST_FLAG(pregistry_priv->ldpc_cap, BIT0)) ? "V" : "X"); /*BIT0: Enable VHT LDPC Rx*/
+ RTW_PRINT_SEL(sel, "[DRV CAP] HT LDPC Tx : %s\n", (TEST_FLAG(pregistry_priv->ldpc_cap, BIT5)) ? "V" : "X"); /*BIT5: Enable HT LDPC Tx*/
+ RTW_PRINT_SEL(sel, "[DRV CAP] HT LDPC Rx : %s\n\n", (TEST_FLAG(pregistry_priv->ldpc_cap, BIT4)) ? "V" : "X"); /*BIT4: Enable HT LDPC Rx*/
+ #ifdef CONFIG_BEAMFORMING
+ #if 0
+ RTW_PRINT_SEL(sel, "[DRV CAP] TxBF parameter : 0x%08x\n", phy_spec->txbf_param);
+ RTW_PRINT_SEL(sel, "[DRV CAP] VHT Sounding Dim : %d\n", (phy_spec->txbf_param >> 24) & 0xFF); /*VHT Sounding Dim [31:24]*/
+ RTW_PRINT_SEL(sel, "[DRV CAP] VHT Steering Ant : %d\n", (phy_spec->txbf_param >> 16) & 0xFF); /*VHT Steering Ant [23:16]*/
+ RTW_PRINT_SEL(sel, "[DRV CAP] HT Sounding Dim : %d\n", (phy_spec->txbf_param >> 8) & 0xFF); /*HT Sounding Dim [15:8]*/
+ RTW_PRINT_SEL(sel, "[DRV CAP] HT Steering Ant : %d\n", phy_spec->txbf_param & 0xFF); /*HT Steering Ant [7:0]*/
+ #endif
+
+ /*
+ * BIT0: Enable VHT SU Beamformer
+ * BIT1: Enable VHT SU Beamformee
+ * BIT2: Enable VHT MU Beamformer, depend on VHT SU Beamformer
+ * BIT3: Enable VHT MU Beamformee, depend on VHT SU Beamformee
+ * BIT4: Enable HT Beamformer
+ * BIT5: Enable HT Beamformee
+ */
+ RTW_PRINT_SEL(sel, "[DRV CAP] TxBF Capability : 0x%02x\n", pregistry_priv->beamform_cap);
+ RTW_PRINT_SEL(sel, "[DRV CAP] VHT MU Bfer : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT2)) ? "V" : "X");
+ RTW_PRINT_SEL(sel, "[DRV CAP] VHT MU Bfee : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT3)) ? "V" : "X");
+ RTW_PRINT_SEL(sel, "[DRV CAP] VHT SU Bfer : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT0)) ? "V" : "X");
+ RTW_PRINT_SEL(sel, "[DRV CAP] VHT SU Bfee : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT1)) ? "V" : "X");
+ RTW_PRINT_SEL(sel, "[DRV CAP] HT Bfer : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT4)) ? "V" : "X");
+ RTW_PRINT_SEL(sel, "[DRV CAP] HT Bfee : %s\n", (TEST_FLAG(pregistry_priv->beamform_cap, BIT5)) ? "V" : "X");
+
+ RTW_PRINT_SEL(sel, "[DRV CAP] Tx Bfer rf_num : %d\n", pregistry_priv->beamformer_rf_num);
+ RTW_PRINT_SEL(sel, "[DRV CAP] Tx Bfee rf_num : %d\n", pregistry_priv->beamformee_rf_num);
+ #endif
+}
+
+int proc_get_stbc_cap(struct seq_file *m, void *v)
+{
+ struct net_device *dev = m->private;
+ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+ struct registry_priv *pregpriv = &padapter->registrypriv;
+
+ if (pregpriv)
+ RTW_PRINT_SEL(m, "0x%02x\n", pregpriv->stbc_cap);
+
+ return 0;
+}
+
+ssize_t proc_set_stbc_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+ struct net_device *dev = data;
+ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+ struct registry_priv *pregpriv = &padapter->registrypriv;
+ char tmp[32];
+ u32 mode;
+
+ if (count < 1)
+ return -EFAULT;
+
+ if (count > sizeof(tmp)) {
+ rtw_warn_on(1);
+ return -EFAULT;
+ }
+
+ if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+ int num = sscanf(tmp, "%d ", &mode);
+
+ if (pregpriv) {
+ pregpriv->stbc_cap = mode;
+ RTW_INFO("stbc_cap = 0x%02x\n", mode);
+ }
+ }
+
+ return count;
+}
int proc_get_rx_stbc(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
@@ -2568,6 +3277,88 @@ ssize_t proc_set_rx_stbc(struct file *file, const char __user *buffer, size_t co
return count;
}
+int proc_get_ldpc_cap(struct seq_file *m, void *v)
+{
+ struct net_device *dev = m->private;
+ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+ struct registry_priv *pregpriv = &padapter->registrypriv;
+
+ if (pregpriv)
+ RTW_PRINT_SEL(m, "0x%02x\n", pregpriv->ldpc_cap);
+
+ return 0;
+}
+
+ssize_t proc_set_ldpc_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+ struct net_device *dev = data;
+ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+ struct registry_priv *pregpriv = &padapter->registrypriv;
+ char tmp[32];
+ u32 mode;
+
+ if (count < 1)
+ return -EFAULT;
+
+ if (count > sizeof(tmp)) {
+ rtw_warn_on(1);
+ return -EFAULT;
+ }
+
+ if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+ int num = sscanf(tmp, "%d ", &mode);
+
+ if (pregpriv) {
+ pregpriv->ldpc_cap = mode;
+ RTW_INFO("ldpc_cap = 0x%02x\n", mode);
+ }
+ }
+
+ return count;
+}
+#ifdef CONFIG_BEAMFORMING
+int proc_get_txbf_cap(struct seq_file *m, void *v)
+{
+ struct net_device *dev = m->private;
+ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+ struct registry_priv *pregpriv = &padapter->registrypriv;
+
+ if (pregpriv)
+ RTW_PRINT_SEL(m, "0x%02x\n", pregpriv->beamform_cap);
+
+ return 0;
+}
+
+ssize_t proc_set_txbf_cap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+ struct net_device *dev = data;
+ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+ struct registry_priv *pregpriv = &padapter->registrypriv;
+ char tmp[32];
+ u32 mode;
+
+ if (count < 1)
+ return -EFAULT;
+
+ if (count > sizeof(tmp)) {
+ rtw_warn_on(1);
+ return -EFAULT;
+ }
+
+ if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+ int num = sscanf(tmp, "%d ", &mode);
+
+ if (pregpriv) {
+ pregpriv->beamform_cap = mode;
+ RTW_INFO("beamform_cap = 0x%02x\n", mode);
+ }
+ }
+
+ return count;
+}
+#endif
#endif /* CONFIG_80211N_HT */
/*int proc_get_rssi_disp(struct seq_file *m, void *v)
@@ -2634,7 +3425,8 @@ int proc_get_all_sta_info(struct seq_file *m, void *v)
int i;
_list *plist, *phead;
- RTW_PRINT_SEL(m, "sta_dz_bitmap=0x%x, tim_bitmap=0x%x\n", pstapriv->sta_dz_bitmap, pstapriv->tim_bitmap);
+ RTW_MAP_DUMP_SEL(m, "sta_dz_bitmap=", pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len);
+ RTW_MAP_DUMP_SEL(m, "tim_bitmap=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len);
_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
@@ -2647,19 +3439,26 @@ int proc_get_all_sta_info(struct seq_file *m, void *v)
plist = get_next(plist);
- /* if(extra_arg == psta->aid) */
+ /* if(extra_arg == psta->cmn.aid) */
{
RTW_PRINT_SEL(m, "==============================\n");
- RTW_PRINT_SEL(m, "sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->hwaddr));
+ RTW_PRINT_SEL(m, "sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr));
RTW_PRINT_SEL(m, "rtsen=%d, cts2slef=%d\n", psta->rtsen, psta->cts2self);
- RTW_PRINT_SEL(m, "state=0x%x, aid=%d, macid=%d, raid=%d\n", psta->state, psta->aid, psta->mac_id, psta->raid);
+ RTW_PRINT_SEL(m, "state=0x%x, aid=%d, macid=%d, raid=%d\n",
+ psta->state, psta->cmn.aid, psta->cmn.mac_id, psta->cmn.ra_info.rate_id);
#ifdef CONFIG_80211N_HT
RTW_PRINT_SEL(m, "qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate);
- RTW_PRINT_SEL(m, "bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n", psta->bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m);
+ RTW_PRINT_SEL(m, "bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n"
+ , psta->cmn.bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m);
RTW_PRINT_SEL(m, "ampdu_enable = %d\n", psta->htpriv.ampdu_enable);
RTW_PRINT_SEL(m, "tx_amsdu_enable = %d\n", psta->htpriv.tx_amsdu_enable);
RTW_PRINT_SEL(m, "agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap);
#endif /* CONFIG_80211N_HT */
+#ifdef CONFIG_80211AC_VHT
+ RTW_PRINT_SEL(m, "vht_en=%d, vht_sgi_80m=%d\n", psta->vhtpriv.vht_option, psta->vhtpriv.sgi_80m);
+ RTW_PRINT_SEL(m, "vht_ldpc_cap=0x%x, vht_stbc_cap=0x%x, vht_beamform_cap=0x%x\n", psta->vhtpriv.ldpc_cap, psta->vhtpriv.stbc_cap, psta->vhtpriv.beamform_cap);
+ RTW_PRINT_SEL(m, "vht_mcs_map=0x%x, vht_highest_rate=0x%x, vht_ampdu_len=%d\n", *(u16 *)psta->vhtpriv.vht_mcs_map, psta->vhtpriv.vht_highest_rate, psta->vhtpriv.ampdu_len);
+#endif
RTW_PRINT_SEL(m, "sleepq_len=%d\n", psta->sleepq_len);
RTW_PRINT_SEL(m, "sta_xmitpriv.vo_q_qcnt=%d\n", psta->sta_xmitpriv.vo_q.qcnt);
RTW_PRINT_SEL(m, "sta_xmitpriv.vi_q_qcnt=%d\n", psta->sta_xmitpriv.vi_q.qcnt);
@@ -2679,12 +3478,21 @@ int proc_get_all_sta_info(struct seq_file *m, void *v)
#ifdef CONFIG_TDLS
RTW_PRINT_SEL(m, "tdls_sta_state=0x%08x\n", psta->tdls_sta_state);
RTW_PRINT_SEL(m, "PeerKey_Lifetime=%d\n", psta->TDLS_PeerKey_Lifetime);
- RTW_PRINT_SEL(m, "rx_data_pkts=%llu\n", psta->sta_stats.rx_data_pkts);
- RTW_PRINT_SEL(m, "rx_bytes=%llu\n", psta->sta_stats.rx_bytes);
- RTW_PRINT_SEL(m, "tx_data_pkts=%llu\n", psta->sta_stats.tx_pkts);
- RTW_PRINT_SEL(m, "tx_bytes=%llu\n", psta->sta_stats.tx_bytes);
#endif /* CONFIG_TDLS */
+ RTW_PRINT_SEL(m, "rx_data_uc_pkts=%llu\n", sta_rx_data_uc_pkts(psta));
+ RTW_PRINT_SEL(m, "rx_data_mc_pkts=%llu\n", psta->sta_stats.rx_data_mc_pkts);
+ RTW_PRINT_SEL(m, "rx_data_bc_pkts=%llu\n", psta->sta_stats.rx_data_bc_pkts);
+ RTW_PRINT_SEL(m, "rx_uc_bytes=%llu\n", sta_rx_uc_bytes(psta));
+ RTW_PRINT_SEL(m, "rx_mc_bytes=%llu\n", psta->sta_stats.rx_mc_bytes);
+ RTW_PRINT_SEL(m, "rx_bc_bytes=%llu\n", psta->sta_stats.rx_bc_bytes);
+ RTW_PRINT_SEL(m, "rx_avg_tp =%d (Bps)\n", psta->cmn.rx_moving_average_tp);
+ RTW_PRINT_SEL(m, "tx_data_pkts=%llu\n", psta->sta_stats.tx_pkts);
+ RTW_PRINT_SEL(m, "tx_bytes=%llu\n", psta->sta_stats.tx_bytes);
+ RTW_PRINT_SEL(m, "tx_avg_tp =%d (MBps)\n", psta->cmn.tx_moving_average_tp);
+#ifdef CONFIG_RTW_80211K
+ RTW_PRINT_SEL(m, "rm_en_cap="RM_CAP_FMT"\n", RM_CAP_ARG(psta->rm_en_cap));
+#endif
dump_st_ctl(m, &psta->st_ctl);
if (STA_OP_WFD_MODE(psta))
@@ -2745,48 +3553,49 @@ int proc_get_best_channel(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
u32 i, best_channel_24G = 1, best_channel_5G = 36, index_24G = 0, index_5G = 0;
- for (i = 0; pmlmeext->channel_set[i].ChannelNum != 0; i++) {
- if (pmlmeext->channel_set[i].ChannelNum == 1)
+ for (i = 0; i < rfctl->max_chan_nums && rfctl->channel_set[i].ChannelNum != 0; i++) {
+ if (rfctl->channel_set[i].ChannelNum == 1)
index_24G = i;
- if (pmlmeext->channel_set[i].ChannelNum == 36)
+ if (rfctl->channel_set[i].ChannelNum == 36)
index_5G = i;
}
- for (i = 0; (i < MAX_CHANNEL_NUM) && (pmlmeext->channel_set[i].ChannelNum != 0) ; i++) {
+ for (i = 0; i < rfctl->max_chan_nums && rfctl->channel_set[i].ChannelNum != 0; i++) {
/* 2.4G */
- if (pmlmeext->channel_set[i].ChannelNum == 6) {
- if (pmlmeext->channel_set[i].rx_count < pmlmeext->channel_set[index_24G].rx_count) {
+ if (rfctl->channel_set[i].ChannelNum == 6) {
+ if (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_24G].rx_count) {
index_24G = i;
- best_channel_24G = pmlmeext->channel_set[i].ChannelNum;
+ best_channel_24G = rfctl->channel_set[i].ChannelNum;
}
}
/* 5G */
- if (pmlmeext->channel_set[i].ChannelNum >= 36
- && pmlmeext->channel_set[i].ChannelNum < 140) {
+ if (rfctl->channel_set[i].ChannelNum >= 36
+ && rfctl->channel_set[i].ChannelNum < 140) {
/* Find primary channel */
- if (((pmlmeext->channel_set[i].ChannelNum - 36) % 8 == 0)
- && (pmlmeext->channel_set[i].rx_count < pmlmeext->channel_set[index_5G].rx_count)) {
+ if (((rfctl->channel_set[i].ChannelNum - 36) % 8 == 0)
+ && (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_5G].rx_count)) {
index_5G = i;
- best_channel_5G = pmlmeext->channel_set[i].ChannelNum;
+ best_channel_5G = rfctl->channel_set[i].ChannelNum;
}
}
- if (pmlmeext->channel_set[i].ChannelNum >= 149
- && pmlmeext->channel_set[i].ChannelNum < 165) {
+ if (rfctl->channel_set[i].ChannelNum >= 149
+ && rfctl->channel_set[i].ChannelNum < 165) {
/* find primary channel */
- if (((pmlmeext->channel_set[i].ChannelNum - 149) % 8 == 0)
- && (pmlmeext->channel_set[i].rx_count < pmlmeext->channel_set[index_5G].rx_count)) {
+ if (((rfctl->channel_set[i].ChannelNum - 149) % 8 == 0)
+ && (rfctl->channel_set[i].rx_count < rfctl->channel_set[index_5G].rx_count)) {
index_5G = i;
- best_channel_5G = pmlmeext->channel_set[i].ChannelNum;
+ best_channel_5G = rfctl->channel_set[i].ChannelNum;
}
}
#if 1 /* debug */
RTW_PRINT_SEL(m, "The rx cnt of channel %3d = %d\n",
- pmlmeext->channel_set[i].ChannelNum, pmlmeext->channel_set[i].rx_count);
+ rfctl->channel_set[i].ChannelNum, rfctl->channel_set[i].rx_count);
#endif
}
@@ -2800,6 +3609,7 @@ ssize_t proc_set_best_channel(struct file *file, const char __user *buffer, size
{
struct net_device *dev = data;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
char tmp[32];
@@ -2813,8 +3623,8 @@ ssize_t proc_set_best_channel(struct file *file, const char __user *buffer, size
if (buffer && !copy_from_user(tmp, buffer, count)) {
int i;
- for (i = 0; pmlmeext->channel_set[i].ChannelNum != 0; i++)
- pmlmeext->channel_set[i].rx_count = 0;
+ for (i = 0; i < rfctl->max_chan_nums && rfctl->channel_set[i].ChannelNum != 0; i++)
+ rfctl->channel_set[i].rx_count = 0;
RTW_INFO("set %s\n", "Clean Best Channel Count");
}
@@ -2917,6 +3727,55 @@ int proc_get_btcoex_info(struct seq_file *m, void *v)
return 0;
}
+
+#ifdef CONFIG_RF4CE_COEXIST
+int proc_get_rf4ce_state(struct seq_file *m, void *v)
+{
+ struct net_device *dev = m->private;
+ _adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+ u8 state = 0, voice = 0;
+
+ state = rtw_btcoex_GetRf4ceLinkState(adapter);
+
+ RTW_PRINT_SEL(m, "RF4CE %s\n", state?"Connected":"Disconnect");
+
+ return 0;
+}
+
+/* This interface is designed for user space application to inform RF4CE state
+ * Initial define for DHC 1295 E387 project
+ *
+ * echo state voice > rf4ce_state
+ * state
+ * 0: RF4CE disconnected
+ * 1: RF4CE connected
+ */
+ssize_t proc_set_rf4ce_state(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+ struct net_device *dev = data;
+ _adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+ char tmp[32];
+ u8 state;
+
+ if (count < 1)
+ return -EFAULT;
+
+ if (count > sizeof(tmp)) {
+ rtw_warn_on(1);
+ return -EFAULT;
+ }
+
+ if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+ int num = sscanf(tmp, "%hhx", &state);
+
+ if (num >= 1)
+ rtw_btcoex_SetRf4ceLinkState(adapter, state);
+ }
+
+ return count;
+}
+#endif /* CONFIG_RF4CE_COEXIST */
#endif /* CONFIG_BT_COEXIST */
#if defined(DBG_CONFIG_ERROR_DETECT)
@@ -2924,8 +3783,21 @@ int proc_get_sreset(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+ struct dvobj_priv *psdpriv = padapter->dvobj;
+ struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+ struct sreset_priv *psrtpriv = &pHalData->srestpriv;
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+ if (psrtpriv->dbg_sreset_ctrl == _TRUE) {
+ RTW_PRINT_SEL(m, "self_dect_tx_cnt:%llu\n", psrtpriv->self_dect_tx_cnt);
+ RTW_PRINT_SEL(m, "self_dect_rx_cnt:%llu\n", psrtpriv->self_dect_rx_cnt);
+ RTW_PRINT_SEL(m, "self_dect_fw_cnt:%llu\n", psrtpriv->self_dect_fw_cnt);
+ RTW_PRINT_SEL(m, "tx_dma_status_cnt:%llu\n", psrtpriv->tx_dma_status_cnt);
+ RTW_PRINT_SEL(m, "rx_dma_status_cnt:%llu\n", psrtpriv->rx_dma_status_cnt);
+ RTW_PRINT_SEL(m, "self_dect_case:%d\n", psrtpriv->self_dect_case);
+ RTW_PRINT_SEL(m, "dbg_sreset_cnt:%d\n", pdbgpriv->dbg_sreset_cnt);
+ }
return 0;
}
@@ -2933,6 +3805,8 @@ ssize_t proc_set_sreset(struct file *file, const char __user *buffer, size_t cou
{
struct net_device *dev = data;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+ struct sreset_priv *psrtpriv = &pHalData->srestpriv;
char tmp[32];
s32 trigger_point;
@@ -2950,6 +3824,8 @@ ssize_t proc_set_sreset(struct file *file, const char __user *buffer, size_t cou
if (trigger_point == SRESET_TGP_NULL)
rtw_hal_sreset_reset(padapter);
+ else if (trigger_point == SRESET_TGP_INFO)
+ psrtpriv->dbg_sreset_ctrl = _TRUE;
else
sreset_set_trigger_point(padapter, trigger_point);
}
@@ -2961,6 +3837,63 @@ ssize_t proc_set_sreset(struct file *file, const char __user *buffer, size_t cou
#ifdef CONFIG_PCI_HCI
+int proc_get_pci_aspm(struct seq_file *m, void *v)
+{
+ struct net_device *dev = m->private;
+ _adapter *padapter = (_adapter *) rtw_netdev_priv(dev);
+ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+ struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv);
+ u8 tmp8 = 0;
+ u16 tmp16 = 0;
+ u32 tmp32 = 0;
+ u8 l1_idle = 0;
+
+
+ RTW_PRINT_SEL(m, "***** ASPM Capability *****\n");
+
+ pci_read_config_dword(pdvobjpriv->ppcidev, pcipriv->pciehdr_offset + PCI_EXP_LNKCAP, &tmp32);
+
+ RTW_PRINT_SEL(m, "CLK REQ: %s\n", (tmp32&PCI_EXP_LNKCAP_CLKPM) ? "Enable" : "Disable");
+ RTW_PRINT_SEL(m, "ASPM L0s: %s\n", (tmp32&BIT10) ? "Enable" : "Disable");
+ RTW_PRINT_SEL(m, "ASPM L1: %s\n", (tmp32&BIT11) ? "Enable" : "Disable");
+
+ tmp8 = rtw_hal_pci_l1off_capability(padapter);
+ RTW_PRINT_SEL(m, "ASPM L1OFF: %s\n", tmp8 ? "Enable" : "Disable");
+
+ RTW_PRINT_SEL(m, "***** ASPM CTRL Reg *****\n");
+
+ pci_read_config_word(pdvobjpriv->ppcidev, pcipriv->pciehdr_offset + PCI_EXP_LNKCTL, &tmp16);
+
+ RTW_PRINT_SEL(m, "CLK REQ: %s\n", (tmp16&PCI_EXP_LNKCTL_CLKREQ_EN) ? "Enable" : "Disable");
+ RTW_PRINT_SEL(m, "ASPM L0s: %s\n", (tmp16&BIT0) ? "Enable" : "Disable");
+ RTW_PRINT_SEL(m, "ASPM L1: %s\n", (tmp16&BIT1) ? "Enable" : "Disable");
+
+ tmp8 = rtw_hal_pci_l1off_nic_support(padapter);
+ RTW_PRINT_SEL(m, "ASPM L1OFF: %s\n", tmp8 ? "Enable" : "Disable");
+
+ RTW_PRINT_SEL(m, "***** ASPM Backdoor *****\n");
+
+ tmp8 = rtw_hal_pci_dbi_read(padapter, 0x719);
+ RTW_PRINT_SEL(m, "CLK REQ: %s\n", (tmp8 & BIT4) ? "Enable" : "Disable");
+
+ tmp8 = rtw_hal_pci_dbi_read(padapter, 0x70f);
+ l1_idle = tmp8 & 0x38;
+ RTW_PRINT_SEL(m, "ASPM L0s: %s\n", (tmp8&BIT7) ? "Enable" : "Disable");
+
+ tmp8 = rtw_hal_pci_dbi_read(padapter, 0x719);
+ RTW_PRINT_SEL(m, "ASPM L1: %s\n", (tmp8 & BIT3) ? "Enable" : "Disable");
+
+ tmp8 = rtw_hal_pci_dbi_read(padapter, 0x718);
+ RTW_PRINT_SEL(m, "ASPM L1OFF: %s\n", (tmp8 & BIT5) ? "Enable" : "Disable");
+
+ RTW_PRINT_SEL(m, "********* MISC **********\n");
+ RTW_PRINT_SEL(m, "ASPM L1 Idel Time: 0x%x\n", l1_idle>>3);
+ RTW_PRINT_SEL(m, "*************************\n");
+
+ return 0;
+}
+
int proc_get_rx_ring(struct seq_file *m, void *v)
{
_irqL irqL;
@@ -3025,11 +3958,12 @@ int proc_get_tx_ring(struct seq_file *m, void *v)
for (j = 0; j < pxmitpriv->txringcount[i]; j++) {
#ifdef CONFIG_TRX_BD_ARCH
struct tx_buf_desc *entry = &tx_ring->buf_desc[j];
+ RTW_PRINT_SEL(m, " buf_desc[%03d]: %p\n", j, entry);
#else
struct tx_desc *entry = &tx_ring->desc[j];
+ RTW_PRINT_SEL(m, " desc[%03d]: %p\n", j, entry);
#endif
- RTW_PRINT_SEL(m, " desc[%03d]: %p\n", j, entry);
for (k = 0; k < sizeof(*entry) / 4; k++) {
if ((k % 4) == 0)
RTW_PRINT_SEL(m, " 0x%03x", k);
@@ -3045,37 +3979,183 @@ int proc_get_tx_ring(struct seq_file *m, void *v)
return 0;
}
-#endif
-#ifdef CONFIG_WOWLAN
-int proc_get_pattern_info(struct seq_file *m, void *v)
+#ifdef DBG_TXBD_DESC_DUMP
+int proc_get_tx_ring_ext(struct seq_file *m, void *v)
{
+ _irqL irqL;
struct net_device *dev = m->private;
- _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
- struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
- struct registry_priv *pregistrypriv = &padapter->registrypriv;
- u8 pattern_num = 0, val8;
- char str_1[128];
- char *p_str;
- int i = 0 , j = 0, k = 0;
- int len = 0, max_len = 0, total = 0;
+ _adapter *padapter = (_adapter *) rtw_netdev_priv(dev);
+ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
+ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+ struct rtw_tx_desc_backup *pbuf;
+ int i, j, k, idx;
- p_str = str_1;
- max_len = sizeof(str_1);
+ RTW_PRINT_SEL(m, "<<<< tx ring ext dump settings >>>>\n");
+ RTW_PRINT_SEL(m, " - backup frame num: %d\n", TX_BAK_FRMAE_CNT);
+ RTW_PRINT_SEL(m, " - backup max. desc size: %d bytes\n", TX_BAK_DESC_LEN);
+ RTW_PRINT_SEL(m, " - backup data size: %d bytes\n\n", TX_BAK_DATA_LEN);
- total = pwrpriv->wowlan_pattern_idx;
+ if (!pxmitpriv->dump_txbd_desc) {
+ RTW_PRINT_SEL(m, "Dump function is disabled.\n");
+ return 0;
+ }
- rtw_set_default_pattern(padapter);
+ _enter_critical(&pdvobjpriv->irq_th_lock, &irqL);
+ for (i = 0; i < HW_QUEUE_ENTRY; i++) {
+ struct rtw_tx_ring *tx_ring = &pxmitpriv->tx_ring[i];
- /*show pattern*/
- RTW_PRINT_SEL(m, "\n======[Pattern Info.]======\n");
- RTW_PRINT_SEL(m, "pattern number: %d\n", total);
- RTW_PRINT_SEL(m, "support default patterns: %c\n",
- (pregistrypriv->default_patterns_en) ? 'Y' : 'N');
+ idx = rtw_get_tx_desc_backup(padapter, i, &pbuf);
- for (k = 0; k < total ; k++) {
- RTW_PRINT_SEL(m, "\npattern idx: %d\n", k);
- RTW_PRINT_SEL(m, "pattern content:\n");
+ RTW_PRINT_SEL(m, "Tx ring[%d]", i);
+ switch (i) {
+ case 0:
+ RTW_PRINT_SEL(m, " (VO)\n");
+ break;
+ case 1:
+ RTW_PRINT_SEL(m, " (VI)\n");
+ break;
+ case 2:
+ RTW_PRINT_SEL(m, " (BE)\n");
+ break;
+ case 3:
+ RTW_PRINT_SEL(m, " (BK)\n");
+ break;
+ case 4:
+ RTW_PRINT_SEL(m, " (BCN)\n");
+ break;
+ case 5:
+ RTW_PRINT_SEL(m, " (MGT)\n");
+ break;
+ case 6:
+ RTW_PRINT_SEL(m, " (HIGH)\n");
+ break;
+ case 7:
+ RTW_PRINT_SEL(m, " (TXCMD)\n");
+ break;
+ default:
+ RTW_PRINT_SEL(m, " (?)\n");
+ break;
+ }
+
+ RTW_PRINT_SEL(m, " Entries: %d\n", TX_BAK_FRMAE_CNT);
+ RTW_PRINT_SEL(m, " Last idx: %d\n", idx);
+
+ for (j = 0; j < TX_BAK_FRMAE_CNT; j++) {
+ RTW_PRINT_SEL(m, " desc[%03d]:\n", j);
+
+ for (k = 0; k < (pbuf->tx_desc_size) / 4; k++) {
+ if ((k % 4) == 0)
+ RTW_PRINT_SEL(m, " 0x%03x", k);
+
+ RTW_PRINT_SEL(m, " 0x%08x ", ((int *)pbuf->tx_bak_desc)[k]);
+
+ if ((k % 4) == 3)
+ RTW_PRINT_SEL(m, "\n");
+ }
+
+#if 1 /* data dump */
+ if (pbuf->tx_desc_size) {
+ RTW_PRINT_SEL(m, " data[%03d]:\n", j);
+
+ for (k = 0; k < (TX_BAK_DATA_LEN) / 4; k++) {
+ if ((k % 4) == 0)
+ RTW_PRINT_SEL(m, " 0x%03x", k);
+
+ RTW_PRINT_SEL(m, " 0x%08x ", ((int *)pbuf->tx_bak_data_hdr)[k]);
+
+ if ((k % 4) == 3)
+ RTW_PRINT_SEL(m, "\n");
+ }
+ RTW_PRINT_SEL(m, "\n");
+ }
+#endif
+
+ RTW_PRINT_SEL(m, " R/W pointer: %d/%d\n", pbuf->tx_bak_rp, pbuf->tx_bak_wp);
+
+ pbuf = pbuf + 1;
+ }
+ RTW_PRINT_SEL(m, "\n");
+ }
+ _exit_critical(&pdvobjpriv->irq_th_lock, &irqL);
+
+ return 0;
+}
+
+ssize_t proc_set_tx_ring_ext(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+ _irqL irqL;
+ struct net_device *dev = data;
+ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
+ char tmp[32];
+ u32 reset = 0;
+ u32 dump = 0;
+
+ if (count < 1)
+ return -EFAULT;
+
+ if (count > sizeof(tmp)) {
+ rtw_warn_on(1);
+ return -EFAULT;
+ }
+
+ if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+ int num = sscanf(tmp, "%u %u", &dump, &reset);
+
+ if (num != 2) {
+ RTW_INFO("invalid parameter!\n");
+ return count;
+ }
+
+ _enter_critical(&pdvobjpriv->irq_th_lock, &irqL);
+ pxmitpriv->dump_txbd_desc = (BOOLEAN) dump;
+
+ if (reset == 1)
+ rtw_tx_desc_backup_reset();
+
+ _exit_critical(&pdvobjpriv->irq_th_lock, &irqL);
+
+ }
+
+ return count;
+}
+
+#endif
+
+#endif
+
+#ifdef CONFIG_WOWLAN
+int proc_get_pattern_info(struct seq_file *m, void *v)
+{
+ struct net_device *dev = m->private;
+ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
+ struct registry_priv *pregistrypriv = &padapter->registrypriv;
+ u8 pattern_num = 0, val8;
+ char str_1[128];
+ char *p_str;
+ int i = 0 , j = 0, k = 0;
+ int len = 0, max_len = 0, total = 0;
+
+ p_str = str_1;
+ max_len = sizeof(str_1);
+
+ total = pwrpriv->wowlan_pattern_idx;
+
+ rtw_set_default_pattern(padapter);
+
+ /*show pattern*/
+ RTW_PRINT_SEL(m, "\n======[Pattern Info.]======\n");
+ RTW_PRINT_SEL(m, "pattern number: %d\n", total);
+ RTW_PRINT_SEL(m, "support default patterns: %c\n",
+ (pwrpriv->default_patterns_en) ? 'Y' : 'N');
+
+ for (k = 0; k < total ; k++) {
+ RTW_PRINT_SEL(m, "\npattern idx: %d\n", k);
+ RTW_PRINT_SEL(m, "pattern content:\n");
p_str = str_1;
max_len = sizeof(str_1);
@@ -3108,6 +4188,7 @@ int proc_get_pattern_info(struct seq_file *m, void *v)
return 0;
}
+
ssize_t proc_set_pattern_info(struct file *file, const char __user *buffer,
size_t count, loff_t *pos, void *data)
{
@@ -3129,7 +4210,7 @@ ssize_t proc_set_pattern_info(struct file *file, const char __user *buffer,
return -EFAULT;
}
- if (pwrpriv->wowlan_pattern_idx >= MAX_WKFM_NUM) {
+ if (pwrpriv->wowlan_pattern_idx >= MAX_WKFM_CAM_NUM) {
RTW_INFO("WARNING: priv-pattern is full(idx: %d)\n",
pwrpriv->wowlan_pattern_idx);
RTW_INFO("WARNING: please clean priv-pattern first\n");
@@ -3154,7 +4235,74 @@ ssize_t proc_set_pattern_info(struct file *file, const char __user *buffer,
return count;
}
-#endif
+
+int proc_get_wakeup_event(struct seq_file *m, void *v)
+{
+ struct net_device *dev = m->private;
+ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+ struct registry_priv *registry_par = &padapter->registrypriv;
+
+ RTW_PRINT_SEL(m, "wakeup event: %#02x\n", registry_par->wakeup_event);
+ return 0;
+}
+
+ssize_t proc_set_wakeup_event(struct file *file, const char __user *buffer,
+ size_t count, loff_t *pos, void *data)
+{
+ struct net_device *dev = data;
+ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+ struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
+ struct registry_priv *registry_par = &padapter->registrypriv;
+ u32 wakeup_event = 0;
+
+ u8 tmp[8] = {0};
+ int ret = 0, num = 0;
+ u8 index = 0;
+
+ if (count < 1)
+ return -EFAULT;
+
+ if (count > sizeof(tmp)) {
+ rtw_warn_on(1);
+ return -EFAULT;
+ }
+
+ if (buffer && !copy_from_user(tmp, buffer, count))
+ num = sscanf(tmp, "%u", &wakeup_event);
+ else
+ return -EFAULT;
+
+ if (wakeup_event <= 0x07) {
+ registry_par->wakeup_event = wakeup_event;
+
+ if (wakeup_event & BIT(1))
+ pwrctrlpriv->default_patterns_en = _TRUE;
+ else
+ pwrctrlpriv->default_patterns_en = _FALSE;
+
+ rtw_wow_pattern_sw_reset(padapter);
+
+ RTW_INFO("%s: wakeup_event: %#2x, default pattern: %d\n",
+ __func__, registry_par->wakeup_event,
+ pwrctrlpriv->default_patterns_en);
+ } else {
+ return -EINVAL;
+ }
+
+ return count;
+}
+
+int proc_get_wakeup_reason(struct seq_file *m, void *v)
+{
+ struct net_device *dev = m->private;
+ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
+ u8 val = pwrpriv->wowlan_last_wake_reason;
+
+ RTW_PRINT_SEL(m, "last wake reason: %#02x\n", val);
+ return 0;
+}
+#endif /*CONFIG_WOWLAN*/
#ifdef CONFIG_GPIO_WAKEUP
int proc_get_wowlan_gpio_info(struct seq_file *m, void *v)
@@ -3199,8 +4347,16 @@ ssize_t proc_set_wowlan_gpio_info(struct file *file, const char __user *buffer,
rtw_ps_deny(padapter, PS_DENY_IOCTL);
LeaveAllPowerSaveModeDirect(padapter);
+
+ #ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE
+ if (pwrpriv->is_high_active == 0)
+ rtw_hal_set_input_gpio(padapter, WAKEUP_GPIO_IDX);
+ else
+ rtw_hal_set_output_gpio(padapter, WAKEUP_GPIO_IDX, 0);
+ #else
val8 = (pwrpriv->is_high_active == 0) ? 1 : 0;
rtw_hal_set_output_gpio(padapter, WAKEUP_GPIO_IDX, val8);
+ #endif
rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL);
RTW_INFO("set %s %d\n", "gpio_high_active",
@@ -3280,6 +4436,7 @@ int proc_get_ps_info(struct seq_file *m, void *v)
struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
u8 ips_mode = pwrpriv->ips_mode;
u8 lps_mode = pwrpriv->power_mgnt;
+ u8 lps_level = pwrpriv->lps_level;
char *str = "";
RTW_PRINT_SEL(m, "======Power Saving Info:======\n");
@@ -3321,12 +4478,142 @@ int proc_get_ps_info(struct seq_file *m, void *v)
RTW_PRINT_SEL(m, " DTIM: %d\n", pwrpriv->dtim);
RTW_PRINT_SEL(m, " LPS enter count:%d, LPS leave count:%d\n",
pwrpriv->lps_enter_cnts, pwrpriv->lps_leave_cnts);
+
+ if (lps_level == LPS_LCLK)
+ str = "LPS_LCLK";
+ else if (lps_level == LPS_PG)
+ str = "LPS_PG";
+ else
+ str = "LPS_NORMAL";
+ RTW_PRINT_SEL(m, " LPS level: %s\n", str);
+
RTW_PRINT_SEL(m, "=============================\n");
return 0;
}
+
+#ifdef CONFIG_WMMPS_STA
+int proc_get_wmmps_info(struct seq_file *m, void *v)
+{
+ struct net_device *dev = m->private;
+ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+ struct registry_priv *pregpriv = &padapter->registrypriv;
+ char *uapsd_max_sp_str="";
+
+ if (pregpriv){
+ switch(pregpriv->uapsd_max_sp_len) {
+ case 0:
+ uapsd_max_sp_str = "NO_LIMIT";
+ break;
+ case 1:
+ uapsd_max_sp_str = "TWO_MSDU";
+ break;
+ case 2:
+ uapsd_max_sp_str = "FOUR_MSDU";
+ break;
+ case 3:
+ uapsd_max_sp_str = "SIX_MSDU";
+ break;
+ default:
+ uapsd_max_sp_str = "UNSPECIFIED";
+ break;
+ }
+
+ RTW_PRINT_SEL(m, "====== WMMPS_STA Info:======\n");
+ RTW_PRINT_SEL(m, "uapsd_max_sp_len=0x%02x (%s)\n", pregpriv->uapsd_max_sp_len, uapsd_max_sp_str);
+ RTW_PRINT_SEL(m, "uapsd_ac_enable=0x%02x\n", pregpriv->uapsd_ac_enable);
+ RTW_PRINT_SEL(m, "BIT0 - AC_VO UAPSD: %s\n", (pregpriv->uapsd_ac_enable & DRV_CFG_UAPSD_VO) ? "Enabled" : "Disabled");
+ RTW_PRINT_SEL(m, "BIT1 - AC_VI UAPSD: %s\n", (pregpriv->uapsd_ac_enable & DRV_CFG_UAPSD_VI) ? "Enabled" : "Disabled");
+ RTW_PRINT_SEL(m, "BIT2 - AC_BK UAPSD: %s\n", (pregpriv->uapsd_ac_enable & DRV_CFG_UAPSD_BK) ? "Enabled" : "Disabled");
+ RTW_PRINT_SEL(m, "BIT3 - AC_BE UAPSD: %s\n", (pregpriv->uapsd_ac_enable & DRV_CFG_UAPSD_BE) ? "Enabled" : "Disabled");
+ RTW_PRINT_SEL(m, "============================\n");
+ }
+
+ return 0;
+}
+
+ssize_t proc_set_wmmps_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+ struct net_device *dev = data;
+ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+ struct registry_priv *pregpriv = &padapter->registrypriv;
+ char tmp[32];
+ u8 uapsd_ac_setting;
+ u8 uapsd_max_sp_len_setting;
+
+ if (count < 1)
+ return -EFAULT;
+
+ if (count > sizeof(tmp)) {
+ rtw_warn_on(1);
+ return -EFAULT;
+ }
+
+ if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+ int num = sscanf(tmp, "%hhu %hhx", &uapsd_max_sp_len_setting, &uapsd_ac_setting);
+
+ if (pregpriv) {
+ if (num >= 1){
+ pregpriv->uapsd_max_sp_len = uapsd_max_sp_len_setting;
+ RTW_INFO("uapsd_max_sp_len = %d\n", pregpriv->uapsd_max_sp_len);
+ }
+
+ if (num >= 2){
+ pregpriv->uapsd_ac_enable = uapsd_ac_setting;
+ RTW_INFO("uapsd_ac_enable = 0x%02x\n", pregpriv->uapsd_ac_enable);
+ }
+ }
+ }
+
+ return count;
+}
+#endif /* CONFIG_WMMPS_STA */
#endif /* CONFIG_POWER_SAVING */
#ifdef CONFIG_TDLS
+int proc_get_tdls_enable(struct seq_file *m, void *v)
+{
+ struct net_device *dev = m->private;
+ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+ struct registry_priv *pregpriv = &padapter->registrypriv;
+
+ if (pregpriv)
+ RTW_PRINT_SEL(m, "TDLS is %s !\n", (rtw_is_tdls_enabled(padapter) == _TRUE) ? "enabled" : "disabled");
+
+ return 0;
+}
+
+ssize_t proc_set_tdls_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+ struct net_device *dev = data;
+ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+ struct registry_priv *pregpriv = &padapter->registrypriv;
+ char tmp[32];
+ u32 en_tdls = 0;
+
+ if (count < 1)
+ return -EFAULT;
+
+ if (count > sizeof(tmp)) {
+ rtw_warn_on(1);
+ return -EFAULT;
+ }
+
+ if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+ int num = sscanf(tmp, "%d ", &en_tdls);
+
+ if (pregpriv) {
+ if (en_tdls > 0)
+ rtw_enable_tdls_func(padapter);
+ else
+ rtw_disable_tdls_func(padapter, _TRUE);
+ }
+ }
+
+ return count;
+}
+
static int proc_tdls_display_tdls_function_info(struct seq_file *m)
{
struct net_device *dev = m->private;
@@ -3338,6 +4625,8 @@ static int proc_tdls_display_tdls_function_info(struct seq_file *m)
int j = 0;
RTW_PRINT_SEL(m, "============[TDLS Function Info]============\n");
+ RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Enable", (rtw_is_tdls_enabled(padapter) == _TRUE) ? "_TRUE" : "_FALSE");
+ RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Driver Setup", (ptdlsinfo->driver_setup == _TRUE) ? "_TRUE" : "_FALSE");
RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Prohibited", (ptdlsinfo->ap_prohibited == _TRUE) ? "_TRUE" : "_FALSE");
RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Channel Switch Prohibited", (ptdlsinfo->ch_switch_prohibited == _TRUE) ? "_TRUE" : "_FALSE");
RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Link Established", (ptdlsinfo->link_established == _TRUE) ? "_TRUE" : "_FALSE");
@@ -3401,8 +4690,6 @@ static int proc_tdls_display_tdls_function_info(struct seq_file *m)
#endif
RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Device Discovered", (ptdlsinfo->dev_discovered == _TRUE) ? "_TRUE" : "_FALSE");
- RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Enable", (ptdlsinfo->tdls_enable == _TRUE) ? "_TRUE" : "_FALSE");
- RTW_PRINT_SEL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Driver Setup", (ptdlsinfo->driver_setup == _TRUE) ? "_TRUE" : "_FALSE");
return 0;
}
@@ -3551,7 +4838,7 @@ static int proc_tdls_display_tdls_sta_info(struct seq_file *m)
if (psta->tdls_sta_state != TDLS_STATE_NONE) {
/* We got one TDLS sta info to show */
RTW_PRINT_SEL(m, "============[TDLS Peer STA Info: STA %d]============\n", ++NumOfTdlsStaToShow);
- RTW_PRINT_SEL(m, "%-*s = "MAC_FMT"\n", SpaceBtwnItemAndValue, "Mac Address", MAC_ARG(psta->hwaddr));
+ RTW_PRINT_SEL(m, "%-*s = "MAC_FMT"\n", SpaceBtwnItemAndValue, "Mac Address", MAC_ARG(psta->cmn.mac_addr));
RTW_PRINT_SEL(m, "%-*s =", SpaceBtwnItemAndValue, "TDLS STA State");
SpaceBtwnItemAndValueTmp = 0;
FirstMatchFound = _FALSE;
@@ -3628,7 +4915,7 @@ static int proc_tdls_display_tdls_sta_info(struct seq_file *m)
RTW_PRINT_SEL(m, "\n");
RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Bandwidth Mode");
- switch (psta->bw_mode) {
+ switch (psta->cmn.bw_mode) {
case CHANNEL_WIDTH_20:
RTW_PRINT_SEL(m, "%s\n", "20MHz");
break;
@@ -3644,6 +4931,15 @@ static int proc_tdls_display_tdls_sta_info(struct seq_file *m)
case CHANNEL_WIDTH_80_80:
RTW_PRINT_SEL(m, "%s\n", "80MHz + 80MHz");
break;
+ case CHANNEL_WIDTH_5:
+ RTW_PRINT_SEL(m, "%s\n", "5MHz");
+ break;
+ case CHANNEL_WIDTH_10:
+ RTW_PRINT_SEL(m, "%s\n", "10MHz");
+ break;
+ default:
+ RTW_PRINT_SEL(m, "(%d)%s\n", psta->cmn.bw_mode, "invalid");
+ break;
}
RTW_PRINT_SEL(m, "%-*s = ", SpaceBtwnItemAndValue, "Privacy");
@@ -3774,6 +5070,52 @@ ssize_t proc_set_monitor(struct file *file, const char __user *buffer, size_t co
return count;
}
+#ifdef DBG_XMIT_BLOCK
+int proc_get_xmit_block(struct seq_file *m, void *v)
+{
+ struct net_device *dev = m->private;
+ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+ dump_xmit_block(m, padapter);
+
+ return 0;
+}
+
+ssize_t proc_set_xmit_block(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+ struct net_device *dev = data;
+ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+ char tmp[32];
+ u8 xb_mode, xb_reason;
+
+ if (count < 1)
+ return -EFAULT;
+
+ if (count > sizeof(tmp)) {
+ rtw_warn_on(1);
+ return -EFAULT;
+ }
+
+ if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+ int num = sscanf(tmp, "%hhx %hhx", &xb_mode, &xb_reason);
+
+ if (num != 2) {
+ RTW_INFO("invalid parameter!\n");
+ return count;
+ }
+
+ if (xb_mode == 0)/*set*/
+ rtw_set_xmit_block(padapter, xb_reason);
+ else if (xb_mode == 1)/*clear*/
+ rtw_clr_xmit_block(padapter, xb_reason);
+ else
+ RTW_INFO("invalid parameter!\n");
+ }
+
+ return count;
+}
+#endif
#include
int proc_get_efuse_map(struct seq_file *m, void *v)
@@ -3793,24 +5135,49 @@ int proc_get_efuse_map(struct seq_file *m, void *v)
ips_mode = pwrctrlpriv->ips_mode;
rtw_pm_set_ips(padapter, IPS_NONE);
- if (rtw_efuse_map_read(padapter, 0, mapLen, pEfuseHal->fakeEfuseInitMap) == _FAIL)
+
+ if (pHalData->efuse_file_status == EFUSE_FILE_LOADED) {
+ RTW_PRINT_SEL(m, "File eFuse Map loaded! file path:%s\nDriver eFuse Map From File\n", EFUSE_MAP_PATH);
+ if (pHalData->bautoload_fail_flag)
+ RTW_PRINT_SEL(m, "File Autoload fail!!!\n");
+ } else if (pHalData->efuse_file_status == EFUSE_FILE_FAILED) {
+ RTW_PRINT_SEL(m, "Open File eFuse Map Fail ! file path:%s\nDriver eFuse Map From Default\n", EFUSE_MAP_PATH);
+ if (pHalData->bautoload_fail_flag)
+ RTW_PRINT_SEL(m, "HW Autoload fail!!!\n");
+ } else {
+ RTW_PRINT_SEL(m, "Driver eFuse Map From HW\n");
+ if (pHalData->bautoload_fail_flag)
+ RTW_PRINT_SEL(m, "HW Autoload fail!!!\n");
+ }
+ for (i = 0; i < mapLen; i += 16) {
+ RTW_PRINT_SEL(m, "0x%02x\t", i);
+ for (j = 0; j < 8; j++)
+ RTW_PRINT_SEL(m, "%02X ", pHalData->efuse_eeprom_data[i + j]);
+ RTW_PRINT_SEL(m, "\t");
+ for (; j < 16; j++)
+ RTW_PRINT_SEL(m, "%02X ", pHalData->efuse_eeprom_data[i + j]);
+ RTW_PRINT_SEL(m, "\n");
+ }
+
+ if (rtw_efuse_map_read(padapter, 0, mapLen, pEfuseHal->fakeEfuseInitMap) == _FAIL) {
RTW_PRINT_SEL(m, "WARN - Read Realmap Failed\n");
+ return 0;
+ }
RTW_PRINT_SEL(m, "\n");
+ RTW_PRINT_SEL(m, "HW eFuse Map\n");
for (i = 0; i < mapLen; i += 16) {
RTW_PRINT_SEL(m, "0x%02x\t", i);
for (j = 0; j < 8; j++)
RTW_PRINT_SEL(m, "%02X ", pEfuseHal->fakeEfuseInitMap[i + j]);
-
RTW_PRINT_SEL(m, "\t");
-
for (; j < 16; j++)
RTW_PRINT_SEL(m, "%02X ", pEfuseHal->fakeEfuseInitMap[i + j]);
-
RTW_PRINT_SEL(m, "\n");
-
}
+
rtw_pm_set_ips(padapter, ips_mode);
+
return 0;
}
@@ -3892,11 +5259,11 @@ ssize_t proc_set_tx_sa_query(struct file *file, const char __user *buffer, size_
}
if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
- && (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) && padapter->securitypriv.binstallBIPkey == _TRUE) {
+ && (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) && SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) == _TRUE) {
RTW_INFO("STA:"MAC_FMT"\n", MAC_ARG(get_my_bssid(&(pmlmeinfo->network))));
/* TX unicast sa_query to AP */
issue_action_SA_Query(padapter, get_my_bssid(&(pmlmeinfo->network)), 0, 0, (u8)key_type);
- } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE && padapter->securitypriv.binstallBIPkey == _TRUE) {
+ } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE && SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) == _TRUE) {
/* TX unicast sa_query to every client STA */
_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
for (index = 0; index < NUM_STA; index++) {
@@ -3908,7 +5275,7 @@ ssize_t proc_set_tx_sa_query(struct file *file, const char __user *buffer, size_
while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
plist = get_next(plist);
- _rtw_memcpy(&mac_addr[psta->mac_id][0], psta->hwaddr, ETH_ALEN);
+ _rtw_memcpy(&mac_addr[psta->cmn.mac_id][0], psta->cmn.mac_addr, ETH_ALEN);
}
}
_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
@@ -3996,7 +5363,7 @@ ssize_t proc_set_tx_deauth(struct file *file, const char __user *buffer, size_t
while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
plist = get_next(plist);
- _rtw_memcpy(&mac_addr[psta->mac_id][0], psta->hwaddr, ETH_ALEN);
+ _rtw_memcpy(&mac_addr[psta->cmn.mac_id][0], psta->cmn.mac_addr, ETH_ALEN);
}
}
_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
@@ -4101,58 +5468,23 @@ int proc_get_tx_auth(struct seq_file *m, void *v)
}
#endif /* CONFIG_IEEE80211W */
-#ifdef CONFIG_NAPI
-int proc_get_napi(struct seq_file *m, void *v)
+#ifdef CONFIG_MCC_MODE
+int proc_get_mcc_info(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
- _adapter *adapter = (_adapter *) rtw_netdev_priv(dev);
- struct registry_priv *reg = &adapter->registrypriv;
+ _adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
- RTW_PRINT_SEL(m, "debug weight\n");
- RTW_PRINT_SEL(m, "------------\n");
- RTW_PRINT_SEL(m, "%05d %06d\n", reg->napi_debug, reg->napi_weight);
+ dump_adapters_status(m, adapter_to_dvobj(adapter));
+ rtw_hal_dump_mcc_info(m, adapter_to_dvobj(adapter));
return 0;
}
-ssize_t proc_set_napi(struct file *file, const char __user *buffer,
- size_t count, loff_t *pos, void *data)
-{
- struct net_device *dev = data;
- _adapter *adapter = (_adapter *) rtw_netdev_priv(dev);
- struct registry_priv *reg = &adapter->registrypriv;
- char tmp[32];
-
- if (count < 1)
- return -EFAULT;
-
- if (count > sizeof(tmp)) {
- rtw_warn_on(1);
- return -EFAULT;
- }
-
- if (buffer && !copy_from_user(tmp, buffer, count)) {
- int num;
- u32 debug;
-
- num = sscanf(tmp, "%d ", &debug);
- if (num >= 1)
- reg->napi_debug = debug ? 1 : 0;
-
- /* we don't support run-time weight config */
- }
-
- return count;
-}
-#endif /* CONFIG_NAPI */
-
-#ifdef CONFIG_MCC_MODE
-int proc_get_mcc_info(struct seq_file *m, void *v)
+int proc_get_mcc_policy_table(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
- dump_adapters_status(m, adapter_to_dvobj(adapter));
- rtw_hal_dump_mcc_info(m, adapter_to_dvobj(adapter));
+ rtw_hal_dump_mcc_policy_table(m);
return 0;
}
@@ -4203,6 +5535,56 @@ ssize_t proc_set_mcc_enable(struct file *file, const char __user *buffer, size_t
return count;
}
+ssize_t proc_set_mcc_duration(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+ struct net_device *dev = data;
+ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+ char tmp[255];
+ u32 enable_runtime_duration = 0, mcc_duration = 0;
+
+ if (NULL == buffer) {
+ RTW_INFO(FUNC_ADPT_FMT ": input buffer is NULL!\n", FUNC_ADPT_ARG(padapter));
+ return -EFAULT;
+ }
+
+ if (count < 1) {
+ RTW_INFO(FUNC_ADPT_FMT ": input length is 0!\n", FUNC_ADPT_ARG(padapter));
+ return -EFAULT;
+ }
+
+ if (count > sizeof(tmp)) {
+ RTW_INFO(FUNC_ADPT_FMT ": input length is too large\n", FUNC_ADPT_ARG(padapter));
+ rtw_warn_on(1);
+ return -EFAULT;
+ }
+
+ if (buffer && !copy_from_user(tmp, buffer, count)) {
+ int num = sscanf(tmp, "%u %u", &enable_runtime_duration, &mcc_duration);
+
+ if (num < 1) {
+ RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter));
+ return -EINVAL;
+ }
+
+ if (num > 2) {
+ RTW_INFO(FUNC_ADPT_FMT ": input parameters > 2\n", FUNC_ADPT_ARG(padapter));
+ return -EINVAL;
+ }
+
+ if (num >= 1) {
+ SET_MCC_RUNTIME_DURATION(padapter, enable_runtime_duration);
+ RTW_INFO("runtime duration:%s\n", enable_runtime_duration ? "enable":"disable");
+ }
+
+ if (num == 2) {
+ RTW_INFO("mcc duration:%d\n", mcc_duration);
+ rtw_set_mcc_duration_cmd(padapter, MCC_DURATION_DIRECET, mcc_duration);
+ }
+ }
+
+ return count;
+}
+
ssize_t proc_set_mcc_single_tx_criteria(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
{
struct net_device *dev = data;
@@ -4500,4 +5882,308 @@ ssize_t proc_set_mcc_sta_bw80_target_tp(struct file *file, const char __user *bu
}
#endif /* CONFIG_MCC_MODE */
+int proc_get_ack_timeout(struct seq_file *m, void *v)
+{
+ struct net_device *dev = m->private;
+ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+ u8 ack_timeout_val, ack_timeout_val_cck;
+
+ ack_timeout_val = rtw_read8(padapter, REG_ACKTO);
+
+#ifdef CONFIG_RTL8821C
+ ack_timeout_val_cck = rtw_read8(padapter, REG_ACKTO_CCK_8821C);
+ RTW_PRINT_SEL(m, "Current CCK packet ACK Timeout = %d us (0x%x).\n", ack_timeout_val_cck, ack_timeout_val_cck);
+ RTW_PRINT_SEL(m, "Current non-CCK packet ACK Timeout = %d us (0x%x).\n", ack_timeout_val, ack_timeout_val);
+#else
+ RTW_PRINT_SEL(m, "Current ACK Timeout = %d us (0x%x).\n", ack_timeout_val, ack_timeout_val);
+#endif
+
+ return 0;
+}
+
+ssize_t proc_set_ack_timeout(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+ struct net_device *dev = data;
+ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+ char tmp[32];
+ u32 ack_timeout_ms, ack_timeout_ms_cck;
+
+ if (count > sizeof(tmp)) {
+ rtw_warn_on(1);
+ return -EFAULT;
+ }
+
+ if (buffer && !copy_from_user(tmp, buffer, count)) {
+ int num = sscanf(tmp, "%u %u", &ack_timeout_ms, &ack_timeout_ms_cck);
+
+#ifdef CONFIG_RTL8821C
+ if (num < 2) {
+ RTW_INFO(FUNC_ADPT_FMT ": input parameters < 2\n", FUNC_ADPT_ARG(padapter));
+ return -EINVAL;
+ }
+#else
+ if (num < 1) {
+ RTW_INFO(FUNC_ADPT_FMT ": input parameters < 1\n", FUNC_ADPT_ARG(padapter));
+ return -EINVAL;
+ }
+#endif
+ /* This register sets the Ack time out value after Tx unicast packet. It is in units of us. */
+ rtw_write8(padapter, REG_ACKTO, (u8)ack_timeout_ms);
+
+#ifdef CONFIG_RTL8821C
+ /* This register sets the Ack time out value after Tx unicast CCK packet. It is in units of us. */
+ rtw_write8(padapter, REG_ACKTO_CCK_8821C, (u8)ack_timeout_ms_cck);
+ RTW_INFO("Set CCK packet ACK Timeout to %d us.\n", ack_timeout_ms_cck);
+ RTW_INFO("Set non-CCK packet ACK Timeout to %d us.\n", ack_timeout_ms);
+#else
+ RTW_INFO("Set ACK Timeout to %d us.\n", ack_timeout_ms);
+#endif
+ }
+
+ return count;
+}
+
+ssize_t proc_set_fw_offload(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+ struct net_device *dev = data;
+ _adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+ _adapter *pri_adapter = GET_PRIMARY_ADAPTER(adapter);
+ HAL_DATA_TYPE *hal = GET_HAL_DATA(adapter);
+ char tmp[32];
+ u32 iqk_offload_enable = 0, ch_switch_offload_enable = 0;
+
+ if (buffer == NULL) {
+ RTW_INFO("input buffer is NULL!\n");
+ return -EFAULT;
+ }
+
+ if (count < 1) {
+ RTW_INFO("input length is 0!\n");
+ return -EFAULT;
+ }
+
+ if (count > sizeof(tmp)) {
+ RTW_INFO("input length is too large\n");
+ rtw_warn_on(1);
+ return -EFAULT;
+ }
+
+ if (buffer && !copy_from_user(tmp, buffer, count)) {
+ int num = sscanf(tmp, "%d %d", &iqk_offload_enable, &ch_switch_offload_enable);
+
+ if (num < 2) {
+ RTW_INFO("input parameters < 1\n");
+ return -EINVAL;
+ }
+
+ if (hal->RegIQKFWOffload != iqk_offload_enable) {
+ hal->RegIQKFWOffload = iqk_offload_enable;
+ rtw_hal_update_iqk_fw_offload_cap(pri_adapter);
+ }
+
+ if (hal->ch_switch_offload != ch_switch_offload_enable)
+ hal->ch_switch_offload = ch_switch_offload_enable;
+ }
+
+ return count;
+}
+
+int proc_get_fw_offload(struct seq_file *m, void *v)
+{
+ struct net_device *dev = m->private;
+ _adapter *adapter = (_adapter *)rtw_netdev_priv(dev);
+ HAL_DATA_TYPE *hal = GET_HAL_DATA(adapter);
+
+
+ RTW_PRINT_SEL(m, "IQK FW offload:%s\n", hal->RegIQKFWOffload?"enable":"disable");
+ RTW_PRINT_SEL(m, "Channel switch FW offload:%s\n", hal->ch_switch_offload?"enable":"disable");
+ return 0;
+}
+
+#ifdef CONFIG_DBG_RF_CAL
+int proc_get_iqk_info(struct seq_file *m, void *v)
+{
+ struct net_device *dev = m->private;
+ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+ return 0;
+}
+
+ssize_t proc_set_iqk(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+ struct net_device *dev = data;
+ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+ char tmp[32];
+ u32 recovery, clear, segment;
+
+ if (count < 1)
+ return -EFAULT;
+
+ if (count > sizeof(tmp)) {
+ rtw_warn_on(1);
+ return -EFAULT;
+ }
+
+ if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+ int num = sscanf(tmp, "%d %d %d", &recovery, &clear, &segment);
+
+ rtw_hal_iqk_test(padapter, recovery, clear, segment);
+ }
+
+ return count;
+
+}
+
+int proc_get_lck_info(struct seq_file *m, void *v)
+{
+ struct net_device *dev = m->private;
+ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+
+ return 0;
+}
+
+ssize_t proc_set_lck(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data)
+{
+ struct net_device *dev = data;
+ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
+ char tmp[32];
+ u32 trigger;
+
+ if (count < 1)
+ return -EFAULT;
+
+ if (count > sizeof(tmp)) {
+ rtw_warn_on(1);
+ return -EFAULT;
+ }
+
+ if (buffer && !copy_from_user(tmp, buffer, count)) {
+
+ int num = sscanf(tmp, "%d", &trigger);
+
+ rtw_hal_lck_test(padapter);
+ }
+
+ return count;
+}
+#endif /* CONFIG_DBG_RF_CAL */
+
#endif /* CONFIG_PROC_DEBUG */
+#define RTW_BUFDUMP_BSIZE 16
+#if 1
+inline void RTW_BUF_DUMP_SEL(uint _loglevel, void *sel, u8 *_titlestring,
+ bool _idx_show, const u8 *_hexdata, int _hexdatalen)
+{
+ int __i;
+ u8 *ptr = (u8 *)_hexdata;
+
+ if (_loglevel <= rtw_drv_log_level) {
+ if (_titlestring) {
+ if (sel == RTW_DBGDUMP)
+ RTW_PRINT("");
+ _RTW_PRINT_SEL(sel, "%s", _titlestring);
+ if (_hexdatalen >= RTW_BUFDUMP_BSIZE)
+ _RTW_PRINT_SEL(sel, "\n");
+ }
+
+ for (__i = 0; __i < _hexdatalen; __i++) {
+ if (((__i % RTW_BUFDUMP_BSIZE) == 0) && (_hexdatalen >= RTW_BUFDUMP_BSIZE)) {
+ if (sel == RTW_DBGDUMP)
+ RTW_PRINT("");
+ if (_idx_show)
+ _RTW_PRINT_SEL(sel, "0x%03X: ", __i);
+ }
+ _RTW_PRINT_SEL(sel, "%02X%s", ptr[__i], (((__i + 1) % 4) == 0) ? " " : " ");
+ if ((__i + 1 < _hexdatalen) && ((__i + 1) % RTW_BUFDUMP_BSIZE) == 0)
+ _RTW_PRINT_SEL(sel, "\n");
+ }
+ _RTW_PRINT_SEL(sel, "\n");
+ }
+}
+#else
+inline void _RTW_STR_DUMP_SEL(void *sel, char *str_out)
+{
+ if (sel == RTW_DBGDUMP)
+ _dbgdump("%s\n", str_out);
+ #if defined(_seqdump)
+ else
+ _seqdump(sel, "%s\n", str_out);
+ #endif /*_seqdump*/
+}
+inline void RTW_BUF_DUMP_SEL(uint _loglevel, void *sel, u8 *_titlestring,
+ bool _idx_show, u8 *_hexdata, int _hexdatalen)
+{
+ int __i, len;
+ int __j, idx;
+ int block_num, remain_byte;
+ char str_out[128] = {'\0'};
+ char str_val[32] = {'\0'};
+ char *p = NULL;
+ u8 *ptr = (u8 *)_hexdata;
+
+ if (_loglevel <= rtw_drv_log_level) {
+ /*dump title*/
+ p = &str_out[0];
+ if (_titlestring) {
+ if (sel == RTW_DBGDUMP) {
+ len = snprintf(str_val, sizeof(str_val), "%s", DRIVER_PREFIX);
+ strncpy(p, str_val, len);
+ p += len;
+ }
+ len = snprintf(str_val, sizeof(str_val), "%s", _titlestring);
+ strncpy(p, str_val, len);
+ p += len;
+ }
+ if (p != &str_out[0]) {
+ _RTW_STR_DUMP_SEL(sel, str_out);
+ _rtw_memset(&str_out, '\0', sizeof(str_out));
+ }
+
+ /*dump buffer*/
+ block_num = _hexdatalen / RTW_BUFDUMP_BSIZE;
+ remain_byte = _hexdatalen % RTW_BUFDUMP_BSIZE;
+ for (__i = 0; __i < block_num; __i++) {
+ p = &str_out[0];
+ if (sel == RTW_DBGDUMP) {
+ len = snprintf(str_val, sizeof(str_val), "%s", DRIVER_PREFIX);
+ strncpy(p, str_val, len);
+ p += len;
+ }
+ if (_idx_show) {
+ len = snprintf(str_val, sizeof(str_val), "0x%03X: ", __i * RTW_BUFDUMP_BSIZE);
+ strncpy(p, str_val, len);
+ p += len;
+ }
+ for (__j =0; __j < RTW_BUFDUMP_BSIZE; __j++) {
+ idx = __i * RTW_BUFDUMP_BSIZE + __j;
+ len = snprintf(str_val, sizeof(str_val), "%02X%s", ptr[idx], (((__j + 1) % 4) == 0) ? " " : " ");
+ strncpy(p, str_val, len);
+ p += len;
+ }
+ _RTW_STR_DUMP_SEL(sel, str_out);
+ _rtw_memset(&str_out, '\0', sizeof(str_out));
+ }
+
+ p = &str_out[0];
+ if ((sel == RTW_DBGDUMP) && remain_byte) {
+ len = snprintf(str_val, sizeof(str_val), "%s", DRIVER_PREFIX);
+ strncpy(p, str_val, len);
+ p += len;
+ }
+ if (_idx_show && remain_byte) {
+ len = snprintf(str_val, sizeof(str_val), "0x%03X: ", block_num * RTW_BUFDUMP_BSIZE);
+ strncpy(p, str_val, len);
+ p += len;
+ }
+ for (__i = 0; __i < remain_byte; __i++) {
+ idx = block_num * RTW_BUFDUMP_BSIZE + __i;
+ len = snprintf(str_val, sizeof(str_val), "%02X%s", ptr[idx], (((__i + 1) % 4) == 0) ? " " : " ");
+ strncpy(p, str_val, len);
+ p += len;
+ }
+ _RTW_STR_DUMP_SEL(sel, str_out);
+ }
+}
+
+#endif
diff --git a/core/rtw_eeprom.c b/core/rtw_eeprom.c
index 78d5758..d48996e 100644
--- a/core/rtw_eeprom.c
+++ b/core/rtw_eeprom.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,12 +11,7 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#define _RTW_EEPROM_C_
#include
@@ -25,31 +20,25 @@
void up_clk(_adapter *padapter, u16 *x)
{
- _func_enter_;
*x = *x | _EESK;
rtw_write8(padapter, EE_9346CR, (u8)*x);
rtw_udelay_os(CLOCK_RATE);
- _func_exit_;
}
void down_clk(_adapter *padapter, u16 *x)
{
- _func_enter_;
*x = *x & ~_EESK;
rtw_write8(padapter, EE_9346CR, (u8)*x);
rtw_udelay_os(CLOCK_RATE);
- _func_exit_;
}
void shift_out_bits(_adapter *padapter, u16 data, u16 count)
{
u16 x, mask;
- _func_enter_;
if (rtw_is_surprise_removed(padapter)) {
- RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
mask = 0x01 << (count - 1);
@@ -62,7 +51,6 @@ void shift_out_bits(_adapter *padapter, u16 data, u16 count)
if (data & mask)
x |= _EEDI;
if (rtw_is_surprise_removed(padapter)) {
- RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
rtw_write8(padapter, EE_9346CR, (u8)x);
@@ -72,21 +60,18 @@ void shift_out_bits(_adapter *padapter, u16 data, u16 count)
mask = mask >> 1;
} while (mask);
if (rtw_is_surprise_removed(padapter)) {
- RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
x &= ~_EEDI;
rtw_write8(padapter, EE_9346CR, (u8)x);
out:
- _func_exit_;
+ return;
}
u16 shift_in_bits(_adapter *padapter)
{
u16 x, d = 0, i;
- _func_enter_;
if (rtw_is_surprise_removed(padapter)) {
- RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
x = rtw_read8(padapter, EE_9346CR);
@@ -98,7 +83,6 @@ u16 shift_in_bits(_adapter *padapter)
d = d << 1;
up_clk(padapter, &x);
if (rtw_is_surprise_removed(padapter)) {
- RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
x = rtw_read8(padapter, EE_9346CR);
@@ -110,7 +94,6 @@ u16 shift_in_bits(_adapter *padapter)
down_clk(padapter, &x);
}
out:
- _func_exit_;
return d;
}
@@ -118,7 +101,6 @@ u16 shift_in_bits(_adapter *padapter)
void standby(_adapter *padapter)
{
u8 x;
- _func_enter_;
x = rtw_read8(padapter, EE_9346CR);
x &= ~(_EECS | _EESK);
@@ -128,14 +110,12 @@ void standby(_adapter *padapter)
x |= _EECS;
rtw_write8(padapter, EE_9346CR, x);
rtw_udelay_os(CLOCK_RATE);
- _func_exit_;
}
u16 wait_eeprom_cmd_done(_adapter *padapter)
{
u8 x;
u16 i, res = _FALSE;
- _func_enter_;
standby(padapter);
for (i = 0; i < 200; i++) {
x = rtw_read8(padapter, EE_9346CR);
@@ -146,37 +126,31 @@ u16 wait_eeprom_cmd_done(_adapter *padapter)
rtw_udelay_os(CLOCK_RATE);
}
exit:
- _func_exit_;
return res;
}
void eeprom_clean(_adapter *padapter)
{
u16 x;
- _func_enter_;
if (rtw_is_surprise_removed(padapter)) {
- RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
x = rtw_read8(padapter, EE_9346CR);
if (rtw_is_surprise_removed(padapter)) {
- RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
x &= ~(_EECS | _EEDI);
rtw_write8(padapter, EE_9346CR, (u8)x);
if (rtw_is_surprise_removed(padapter)) {
- RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
up_clk(padapter, &x);
if (rtw_is_surprise_removed(padapter)) {
- RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
down_clk(padapter, &x);
out:
- _func_exit_;
+ return;
}
void eeprom_write16(_adapter *padapter, u16 reg, u16 data)
@@ -188,16 +162,13 @@ void eeprom_write16(_adapter *padapter, u16 reg, u16 data)
tmp8_new = tmp8_ori & 0xf7;
if (tmp8_ori != tmp8_new) {
rtw_write8(padapter, 0x102502f1, tmp8_new);
- RT_TRACE(_module_rtl871x_mp_ioctl_c_, _drv_err_, ("====write 0x102502f1=====\n"));
}
tmp8_clk_ori = rtw_read8(padapter, 0x10250003);
tmp8_clk_new = tmp8_clk_ori | 0x20;
if (tmp8_clk_new != tmp8_clk_ori) {
- RT_TRACE(_module_rtl871x_mp_ioctl_c_, _drv_err_, ("====write 0x10250003=====\n"));
rtw_write8(padapter, 0x10250003, tmp8_clk_new);
}
#endif
- _func_enter_;
x = rtw_read8(padapter, EE_9346CR);
@@ -257,7 +228,6 @@ void eeprom_write16(_adapter *padapter, u16 reg, u16 data)
rtw_write8(padapter, 0x102502f1, tmp8_ori);
#endif
- _func_exit_;
return;
}
@@ -272,26 +242,21 @@ u16 eeprom_read16(_adapter *padapter, u16 reg) /* ReadEEprom */
tmp8_new = tmp8_ori & 0xf7;
if (tmp8_ori != tmp8_new) {
rtw_write8(padapter, 0x102502f1, tmp8_new);
- RT_TRACE(_module_rtl871x_mp_ioctl_c_, _drv_err_, ("====write 0x102502f1=====\n"));
}
tmp8_clk_ori = rtw_read8(padapter, 0x10250003);
tmp8_clk_new = tmp8_clk_ori | 0x20;
if (tmp8_clk_new != tmp8_clk_ori) {
- RT_TRACE(_module_rtl871x_mp_ioctl_c_, _drv_err_, ("====write 0x10250003=====\n"));
rtw_write8(padapter, 0x10250003, tmp8_clk_new);
}
#endif
- _func_enter_;
if (rtw_is_surprise_removed(padapter)) {
- RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
/* select EEPROM, reset bits, set _EECS */
x = rtw_read8(padapter, EE_9346CR);
if (rtw_is_surprise_removed(padapter)) {
- RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
@@ -316,7 +281,6 @@ u16 eeprom_read16(_adapter *padapter, u16 reg) /* ReadEEprom */
rtw_write8(padapter, 0x102502f1, tmp8_ori);
#endif
- _func_exit_;
return data;
@@ -331,16 +295,13 @@ void eeprom_read_sz(_adapter *padapter, u16 reg, u8 *data, u32 sz)
u16 x, data16;
u32 i;
- _func_enter_;
if (rtw_is_surprise_removed(padapter)) {
- RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
/* select EEPROM, reset bits, set _EECS */
x = rtw_read8(padapter, EE_9346CR);
if (rtw_is_surprise_removed(padapter)) {
- RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE"));
goto out;
}
@@ -362,10 +323,7 @@ void eeprom_read_sz(_adapter *padapter, u16 reg, u8 *data, u32 sz)
eeprom_clean(padapter);
out:
- _func_exit_;
-
-
-
+ return;
}
@@ -374,7 +332,6 @@ u8 eeprom_read(_adapter *padapter, u32 addr_off, u8 sz, u8 *rbuf)
{
u8 quotient, remainder, addr_2align_odd;
u16 reg, stmp , i = 0, idx = 0;
- _func_enter_;
reg = (u16)(addr_off >> 1);
addr_2align_odd = (u8)(addr_off & 0x1);
@@ -399,7 +356,6 @@ u8 eeprom_read(_adapter *padapter, u32 addr_off, u8 sz, u8 *rbuf)
stmp = eeprom_read16(padapter, reg);
rbuf[idx] = (u8)(stmp & 0xff);
}
- _func_exit_;
return _TRUE;
}
@@ -408,8 +364,6 @@ u8 eeprom_read(_adapter *padapter, u32 addr_off, u8 sz, u8 *rbuf)
VOID read_eeprom_content(_adapter *padapter)
{
- _func_enter_;
- _func_exit_;
}
diff --git a/core/rtw_ieee80211.c b/core/rtw_ieee80211.c
index eec9cab..c4a9bd2 100644
--- a/core/rtw_ieee80211.c
+++ b/core/rtw_ieee80211.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,12 +11,7 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#define _IEEE80211_C
#ifdef CONFIG_PLATFORM_INTEL_BYT
@@ -196,7 +191,7 @@ u8 *rtw_set_ie
u8 *pbuf,
sint index,
uint len,
- u8 *source,
+ const u8 *source,
uint *frlen /* frame length */
)
{
@@ -207,7 +202,8 @@ u8 *rtw_set_ie
if (len > 0)
_rtw_memcpy((void *)(pbuf + 2), (void *)source, len);
- *frlen = *frlen + (len + 2);
+ if (frlen)
+ *frlen = *frlen + (len + 2);
return pbuf + len + 2;
}
@@ -228,9 +224,9 @@ inline u8 secondary_ch_offset_to_hal_ch_offset(u8 ch_offset)
if (ch_offset == SCN)
return HAL_PRIME_CHNL_OFFSET_DONT_CARE;
else if (ch_offset == SCA)
- return HAL_PRIME_CHNL_OFFSET_UPPER;
- else if (ch_offset == SCB)
return HAL_PRIME_CHNL_OFFSET_LOWER;
+ else if (ch_offset == SCB)
+ return HAL_PRIME_CHNL_OFFSET_UPPER;
return HAL_PRIME_CHNL_OFFSET_DONT_CARE;
}
@@ -240,9 +236,9 @@ inline u8 hal_ch_offset_to_secondary_ch_offset(u8 ch_offset)
if (ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE)
return SCN;
else if (ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER)
- return SCB;
- else if (ch_offset == HAL_PRIME_CHNL_OFFSET_UPPER)
return SCA;
+ else if (ch_offset == HAL_PRIME_CHNL_OFFSET_UPPER)
+ return SCB;
return SCN;
}
@@ -268,13 +264,11 @@ inline u8 *rtw_set_ie_mesh_ch_switch_parm(u8 *buf, u32 *buf_len, u8 ttl,
/*----------------------------------------------------------------------------
index: the information element id index, limit is the limit for search
-----------------------------------------------------------------------------*/
-u8 *rtw_get_ie(u8 *pbuf, sint index, sint *len, sint limit)
+u8 *rtw_get_ie(const u8 *pbuf, sint index, sint *len, sint limit)
{
sint tmp, i;
- u8 *p;
- _func_enter_;
+ const u8 *p;
if (limit < 1) {
- _func_exit_;
return NULL;
}
@@ -284,7 +278,7 @@ u8 *rtw_get_ie(u8 *pbuf, sint index, sint *len, sint limit)
while (1) {
if (*p == index) {
*len = *(p + 1);
- return p;
+ return (u8 *)p;
} else {
tmp = *(p + 1);
p += (tmp + 2);
@@ -293,7 +287,6 @@ u8 *rtw_get_ie(u8 *pbuf, sint index, sint *len, sint limit)
if (i >= limit)
break;
}
- _func_exit_;
return NULL;
}
@@ -309,17 +302,17 @@ u8 *rtw_get_ie(u8 *pbuf, sint index, sint *len, sint limit)
*
* Returns: The address of the specific IE found, or NULL
*/
-u8 *rtw_get_ie_ex(u8 *in_ie, uint in_len, u8 eid, u8 *oui, u8 oui_len, u8 *ie, uint *ielen)
+u8 *rtw_get_ie_ex(const u8 *in_ie, uint in_len, u8 eid, const u8 *oui, u8 oui_len, u8 *ie, uint *ielen)
{
uint cnt;
- u8 *target_ie = NULL;
+ const u8 *target_ie = NULL;
if (ielen)
*ielen = 0;
if (!in_ie || in_len <= 0)
- return target_ie;
+ return (u8 *)target_ie;
cnt = 0;
@@ -341,7 +334,7 @@ u8 *rtw_get_ie_ex(u8 *in_ie, uint in_len, u8 eid, u8 *oui, u8 oui_len, u8 *ie, u
}
- return target_ie;
+ return (u8 *)target_ie;
}
/**
@@ -390,7 +383,6 @@ int rtw_ies_remove_ie(u8 *ies, uint *ies_len, uint offset, u8 eid, u8 *oui, u8 o
void rtw_set_supported_rate(u8 *SupportedRates, uint mode)
{
- _func_enter_;
_rtw_memset(SupportedRates, 0, NDIS_802_11_LENGTH_RATES_EX);
@@ -416,13 +408,11 @@ void rtw_set_supported_rate(u8 *SupportedRates, uint mode)
break;
}
- _func_exit_;
}
uint rtw_get_rateset_len(u8 *rateset)
{
uint i = 0;
- _func_enter_;
while (1) {
if ((rateset[i]) == 0)
break;
@@ -432,7 +422,6 @@ uint rtw_get_rateset_len(u8 *rateset)
i++;
}
- _func_exit_;
return i;
}
@@ -443,7 +432,6 @@ int rtw_generate_ie(struct registry_priv *pregistrypriv)
WLAN_BSSID_EX *pdev_network = &pregistrypriv->dev_network;
u8 *ie = pdev_network->IEs;
- _func_enter_;
/* timestamp will be inserted by hardware */
sz += 8;
@@ -516,7 +504,6 @@ int rtw_generate_ie(struct registry_priv *pregistrypriv)
/* pdev_network->IELength = sz; */ /* update IELength */
- _func_exit_;
/* return _SUCCESS; */
@@ -648,7 +635,6 @@ int rtw_parse_wpa_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwis
left -= WPA_SELECTOR_LEN;
} else if (left > 0) {
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("%s: ie length mismatch, %u too much", __FUNCTION__, left));
return _FAIL;
}
@@ -662,8 +648,6 @@ int rtw_parse_wpa_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwis
left -= 2;
if (count == 0 || left < count * WPA_SELECTOR_LEN) {
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("%s: ie count botch (pairwise), "
- "count %u left %u", __FUNCTION__, count, left));
return _FAIL;
}
@@ -675,7 +659,6 @@ int rtw_parse_wpa_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwis
}
} else if (left == 1) {
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("%s: ie too short (for key mgmt)", __FUNCTION__));
return _FAIL;
}
@@ -683,7 +666,6 @@ int rtw_parse_wpa_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwis
if (left >= 6) {
pos += 2;
if (_rtw_memcmp(pos, SUITE_1X, 4) == 1) {
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("%s : there has 802.1x auth\n", __FUNCTION__));
*is_8021x = 1;
}
}
@@ -693,77 +675,144 @@ int rtw_parse_wpa_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwis
}
-int rtw_parse_wpa2_ie(u8 *rsn_ie, int rsn_ie_len, int *group_cipher, int *pairwise_cipher, int *is_8021x)
+int rtw_rsne_info_parse(const u8 *ie, uint ie_len, struct rsne_info *info)
{
- int i, ret = _SUCCESS;
- int left, count;
- u8 *pos;
- u8 SUITE_1X[4] = {0x00, 0x0f, 0xac, 0x01};
+ int i;
+ const u8 *pos = ie;
+ u16 cnt;
- if (rsn_ie_len <= 0) {
- /* No RSN IE - fail silently */
- return _FAIL;
- }
+ _rtw_memset(info, 0, sizeof(struct rsne_info));
+ if (ie + ie_len < pos + 4)
+ goto err;
- if ((*rsn_ie != _WPA2_IE_ID_) || (*(rsn_ie + 1) != (u8)(rsn_ie_len - 2)))
- return _FAIL;
+ if (*ie != WLAN_EID_RSN || *(ie + 1) != ie_len - 2)
+ goto err;
+ pos += 2 + 2;
- pos = rsn_ie;
+ /* Group CS */
+ if (ie + ie_len < pos + 4) {
+ if (ie + ie_len != pos)
+ goto err;
+ goto exit;
+ }
+ info->gcs = (u8 *)pos;
pos += 4;
- left = rsn_ie_len - 4;
- /* group_cipher */
- if (left >= RSN_SELECTOR_LEN) {
+ /* Pairwise CS */
+ if (ie + ie_len < pos + 2) {
+ if (ie + ie_len != pos)
+ goto err;
+ goto exit;
+ }
+ cnt = RTW_GET_LE16(pos);
+ pos += 2;
+ if (ie + ie_len < pos + 4 * cnt) {
+ if (ie + ie_len != pos)
+ goto err;
+ goto exit;
+ }
+ info->pcs_cnt = cnt;
+ info->pcs_list = (u8 *)pos;
+ pos += 4 * cnt;
- *group_cipher = rtw_get_wpa2_cipher_suite(pos);
+ /* AKM */
+ if (ie + ie_len < pos + 2) {
+ if (ie + ie_len != pos)
+ goto err;
+ goto exit;
+ }
+ cnt = RTW_GET_LE16(pos);
+ pos += 2;
+ if (ie + ie_len < pos + 4 * cnt) {
+ if (ie + ie_len != pos)
+ goto err;
+ goto exit;
+ }
+ info->akm_cnt = cnt;
+ info->akm_list = (u8 *)pos;
+ pos += 4 * cnt;
- pos += RSN_SELECTOR_LEN;
- left -= RSN_SELECTOR_LEN;
+ /* RSN cap */
+ if (ie + ie_len < pos + 2) {
+ if (ie + ie_len != pos)
+ goto err;
+ goto exit;
+ }
+ info->cap = (u8 *)pos;
+ pos += 2;
- } else if (left > 0) {
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("%s: ie length mismatch, %u too much", __FUNCTION__, left));
- return _FAIL;
+ /* PMKID */
+ if (ie + ie_len < pos + 2) {
+ if (ie + ie_len != pos)
+ goto err;
+ goto exit;
+ }
+ cnt = RTW_GET_LE16(pos);
+ pos += 2;
+ if (ie + ie_len < pos + 16 * cnt) {
+ if (ie + ie_len != pos)
+ goto err;
+ goto exit;
}
+ info->pmkid_cnt = cnt;
+ info->pmkid_list = (u8 *)pos;
+ pos += 16 * cnt;
- /* pairwise_cipher */
- if (left >= 2) {
- /* count = le16_to_cpu(*(u16*)pos); */
- count = RTW_GET_LE16(pos);
- pos += 2;
- left -= 2;
+ /* Group Mgmt CS */
+ if (ie + ie_len < pos + 4) {
+ if (ie + ie_len != pos)
+ goto err;
+ goto exit;
+ }
+ info->gmcs = (u8 *)pos;
- if (count == 0 || left < count * RSN_SELECTOR_LEN) {
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("%s: ie count botch (pairwise), "
- "count %u left %u", __FUNCTION__, count, left));
- return _FAIL;
- }
+exit:
+ return _SUCCESS;
- for (i = 0; i < count; i++) {
- *pairwise_cipher |= rtw_get_wpa2_cipher_suite(pos);
+err:
+ info->err = 1;
+ return _FAIL;
+}
- pos += RSN_SELECTOR_LEN;
- left -= RSN_SELECTOR_LEN;
- }
+int rtw_parse_wpa2_ie(u8 *rsn_ie, int rsn_ie_len, int *group_cipher, int *pairwise_cipher, int *is_8021x, u8 *mfp_opt)
+{
+ struct rsne_info info;
+ int i, ret = _SUCCESS;
+ u8 SUITE_1X[4] = {0x00, 0x0f, 0xac, 0x01};
- } else if (left == 1) {
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("%s: ie too short (for key mgmt)", __FUNCTION__));
+ ret = rtw_rsne_info_parse(rsn_ie, rsn_ie_len, &info);
+ if (ret != _SUCCESS)
+ goto exit;
- return _FAIL;
+ if (group_cipher) {
+ if (info.gcs)
+ *group_cipher = rtw_get_wpa2_cipher_suite(info.gcs);
+ else
+ *group_cipher = 0;
+ }
+
+ if (pairwise_cipher) {
+ *pairwise_cipher = 0;
+ for (i = 0; i < info.pcs_cnt; i++)
+ *pairwise_cipher |= rtw_get_wpa2_cipher_suite(info.pcs_list + 4 * i);
}
if (is_8021x) {
- if (left >= 6) {
- pos += 2;
- if (_rtw_memcmp(pos, SUITE_1X, 4) == 1) {
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("%s (): there has 802.1x auth\n", __FUNCTION__));
- *is_8021x = 1;
- }
- }
+ *is_8021x = 0;
+ /* here only check the first AKM suite */
+ if (info.akm_cnt && _rtw_memcmp(SUITE_1X, info.akm_list, 4) == _TRUE)
+ *is_8021x = 1;
}
- return ret;
+ if (mfp_opt) {
+ *mfp_opt = MFP_NO;
+ if (info.cap)
+ *mfp_opt = GET_RSN_CAP_MFP_OPTION(info.cap);
+ }
+exit:
+ return ret;
}
/* #ifdef CONFIG_WAPI_SUPPORT */
@@ -775,7 +824,6 @@ int rtw_get_wapi_ie(u8 *in_ie, uint in_len, u8 *wapi_ie, u16 *wapi_len)
u8 wapi_oui1[4] = {0x0, 0x14, 0x72, 0x01};
u8 wapi_oui2[4] = {0x0, 0x14, 0x72, 0x02};
- _func_enter_;
if (wapi_len)
*wapi_len = 0;
@@ -791,16 +839,9 @@ int rtw_get_wapi_ie(u8 *in_ie, uint in_len, u8 *wapi_ie, u16 *wapi_len)
/* if(authmode==_WAPI_IE_) */
if (authmode == _WAPI_IE_ && (_rtw_memcmp(&in_ie[cnt + 6], wapi_oui1, 4) == _TRUE ||
_rtw_memcmp(&in_ie[cnt + 6], wapi_oui2, 4) == _TRUE)) {
- if (wapi_ie) {
+ if (wapi_ie)
_rtw_memcpy(wapi_ie, &in_ie[cnt], in_ie[cnt + 1] + 2);
- for (i = 0; i < (in_ie[cnt + 1] + 2); i = i + 8) {
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("\n %2x,%2x,%2x,%2x,%2x,%2x,%2x,%2x\n",
- wapi_ie[i], wapi_ie[i + 1], wapi_ie[i + 2], wapi_ie[i + 3], wapi_ie[i + 4],
- wapi_ie[i + 5], wapi_ie[i + 6], wapi_ie[i + 7]));
- }
- }
-
if (wapi_len)
*wapi_len = in_ie[cnt + 1] + 2;
@@ -813,7 +854,6 @@ int rtw_get_wapi_ie(u8 *in_ie, uint in_len, u8 *wapi_ie, u16 *wapi_len)
if (wapi_len)
len = *wapi_len;
- _func_exit_;
return len;
@@ -826,7 +866,6 @@ int rtw_get_sec_ie(u8 *in_ie, uint in_len, u8 *rsn_ie, u16 *rsn_len, u8 *wpa_ie,
u8 wpa_oui[4] = {0x0, 0x50, 0xf2, 0x01};
uint cnt;
- _func_enter_;
/* Search required WPA or WPA2 IE and copy to sec_ie[ ] */
@@ -838,34 +877,18 @@ int rtw_get_sec_ie(u8 *in_ie, uint in_len, u8 *rsn_ie, u16 *rsn_len, u8 *wpa_ie,
authmode = in_ie[cnt];
if ((authmode == _WPA_IE_ID_) && (_rtw_memcmp(&in_ie[cnt + 2], &wpa_oui[0], 4) == _TRUE)) {
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("\n rtw_get_wpa_ie: sec_idx=%d in_ie[cnt+1]+2=%d\n", sec_idx, in_ie[cnt + 1] + 2));
- if (wpa_ie) {
+ if (wpa_ie)
_rtw_memcpy(wpa_ie, &in_ie[cnt], in_ie[cnt + 1] + 2);
- for (i = 0; i < (in_ie[cnt + 1] + 2); i = i + 8) {
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("\n %2x,%2x,%2x,%2x,%2x,%2x,%2x,%2x\n",
- wpa_ie[i], wpa_ie[i + 1], wpa_ie[i + 2], wpa_ie[i + 3], wpa_ie[i + 4],
- wpa_ie[i + 5], wpa_ie[i + 6], wpa_ie[i + 7]));
- }
- }
-
*wpa_len = in_ie[cnt + 1] + 2;
cnt += in_ie[cnt + 1] + 2; /* get next */
} else {
if (authmode == _WPA2_IE_ID_) {
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("\n get_rsn_ie: sec_idx=%d in_ie[cnt+1]+2=%d\n", sec_idx, in_ie[cnt + 1] + 2));
- if (rsn_ie) {
+ if (rsn_ie)
_rtw_memcpy(rsn_ie, &in_ie[cnt], in_ie[cnt + 1] + 2);
- for (i = 0; i < (in_ie[cnt + 1] + 2); i = i + 8) {
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("\n %2x,%2x,%2x,%2x,%2x,%2x,%2x,%2x\n",
- rsn_ie[i], rsn_ie[i + 1], rsn_ie[i + 2], rsn_ie[i + 3], rsn_ie[i + 4],
- rsn_ie[i + 5], rsn_ie[i + 6], rsn_ie[i + 7]));
- }
- }
-
*rsn_len = in_ie[cnt + 1] + 2;
cnt += in_ie[cnt + 1] + 2; /* get next */
} else {
@@ -875,7 +898,6 @@ int rtw_get_sec_ie(u8 *in_ie, uint in_len, u8 *rsn_ie, u16 *rsn_len, u8 *wpa_ie,
}
- _func_exit_;
return *rsn_len + *wpa_len;
@@ -899,23 +921,26 @@ u8 rtw_is_wps_ie(u8 *ie_ptr, uint *wps_ielen)
return match;
}
-u8 *rtw_get_wps_ie_from_scan_queue(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen, u8 frame_type)
+u8 *rtw_get_wps_ie_from_scan_queue(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen, enum bss_type frame_type)
{
u8 *wps = NULL;
RTW_INFO("[%s] frame_type = %d\n", __FUNCTION__, frame_type);
switch (frame_type) {
- case 1:
- case 3: {
+ case BSS_TYPE_BCN:
+ case BSS_TYPE_PROB_RSP: {
/* Beacon or Probe Response */
wps = rtw_get_wps_ie(in_ie + _PROBERSP_IE_OFFSET_, in_len - _PROBERSP_IE_OFFSET_, wps_ie, wps_ielen);
break;
}
- case 2: {
+ case BSS_TYPE_PROB_REQ: {
/* Probe Request */
wps = rtw_get_wps_ie(in_ie + _PROBEREQ_IE_OFFSET_ , in_len - _PROBEREQ_IE_OFFSET_ , wps_ie, wps_ielen);
break;
}
+ default:
+ case BSS_TYPE_UNDEF:
+ break;
}
return wps;
}
@@ -929,10 +954,10 @@ u8 *rtw_get_wps_ie_from_scan_queue(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps
*
* Returns: The address of the WPS IE found, or NULL
*/
-u8 *rtw_get_wps_ie(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen)
+u8 *rtw_get_wps_ie(const u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen)
{
uint cnt;
- u8 *wpsie_ptr = NULL;
+ const u8 *wpsie_ptr = NULL;
u8 eid, wps_oui[4] = {0x00, 0x50, 0xf2, 0x04};
if (wps_ielen)
@@ -940,11 +965,11 @@ u8 *rtw_get_wps_ie(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen)
if (!in_ie) {
rtw_warn_on(1);
- return wpsie_ptr;
+ return (u8 *)wpsie_ptr;
}
if (in_len <= 0)
- return wpsie_ptr;
+ return (u8 *)wpsie_ptr;
cnt = 0;
@@ -971,7 +996,7 @@ u8 *rtw_get_wps_ie(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen)
}
- return wpsie_ptr;
+ return (u8 *)wpsie_ptr;
}
/**
@@ -1282,6 +1307,28 @@ ParseRes rtw_ieee802_11_parse_elems(u8 *start, uint len,
elems->vht_op_mode_notify = pos;
elems->vht_op_mode_notify_len = elen;
break;
+ case _EID_RRM_EN_CAP_IE_:
+ elems->rm_en_cap = pos;
+ elems->rm_en_cap_len = elen;
+ break;
+#ifdef CONFIG_RTW_MESH
+ case WLAN_EID_PREQ:
+ elems->preq = pos;
+ elems->preq_len = elen;
+ break;
+ case WLAN_EID_PREP:
+ elems->prep = pos;
+ elems->prep_len = elen;
+ break;
+ case WLAN_EID_PERR:
+ elems->perr = pos;
+ elems->perr_len = elen;
+ break;
+ case WLAN_EID_RANN:
+ elems->rann = pos;
+ elems->rann_len = elen;
+ break;
+#endif
default:
unknown++;
if (!show_errors)
@@ -1349,7 +1396,6 @@ int rtw_get_mac_addr_intel(unsigned char *buf)
int ret = 0;
int i;
struct file *fp = NULL;
- mm_segment_t oldfs;
unsigned char c_mac[MAC_ADDRESS_LEN];
char fname[] = "/config/wifi/mac.txt";
int jj, kk;
@@ -1479,40 +1525,78 @@ void rtw_macaddr_cfg(u8 *out, const u8 *hw_mac_addr)
}
#ifdef CONFIG_80211N_HT
-void dump_ht_cap_ie_content(void *sel, u8 *buf, u32 buf_len)
+void dump_ht_cap_ie_content(void *sel, const u8 *buf, u32 buf_len)
{
- if (buf_len != 26) {
- RTW_PRINT_SEL(sel, "Invalid HT capability IE len:%d != %d\n", buf_len, 26);
+ if (buf_len != HT_CAP_IE_LEN) {
+ RTW_PRINT_SEL(sel, "Invalid HT capability IE len:%d != %d\n", buf_len, HT_CAP_IE_LEN);
return;
}
- RTW_PRINT_SEL(sel, "HT Capabilities Info:%02x%02x\n", *(buf), *(buf + 1));
+ RTW_PRINT_SEL(sel, "cap_info:%02x%02x:%s\n", *(buf), *(buf + 1)
+ , GET_HT_CAP_ELE_CHL_WIDTH(buf) ? " 40MHz" : " 20MHz");
RTW_PRINT_SEL(sel, "A-MPDU Parameters:"HT_AMPDU_PARA_FMT"\n"
, HT_AMPDU_PARA_ARG(HT_CAP_ELE_AMPDU_PARA(buf)));
RTW_PRINT_SEL(sel, "Supported MCS Set:"HT_SUP_MCS_SET_FMT"\n"
, HT_SUP_MCS_SET_ARG(HT_CAP_ELE_SUP_MCS_SET(buf)));
}
-void dump_ht_cap_ie(void *sel, u8 *ie, u32 ie_len)
+void dump_ht_cap_ie(void *sel, const u8 *ie, u32 ie_len)
{
- u8 *pos = (u8 *)ie;
+ const u8 *pos = ie;
u16 id;
u16 len;
- u8 *ht_cap_ie;
+ const u8 *ht_cap_ie;
sint ht_cap_ielen;
- ht_cap_ie = rtw_get_ie(ie, _HT_CAPABILITY_IE_, &ht_cap_ielen, ie_len);
+ ht_cap_ie = rtw_get_ie(ie, WLAN_EID_HT_CAP, &ht_cap_ielen, ie_len);
if (!ie || ht_cap_ie != ie)
return;
dump_ht_cap_ie_content(sel, ht_cap_ie + 2, ht_cap_ielen);
}
+
+const char *const _ht_sc_offset_str[] = {
+ "SCN",
+ "SCA",
+ "SC-RSVD",
+ "SCB",
+};
+
+void dump_ht_op_ie_content(void *sel, const u8 *buf, u32 buf_len)
+{
+ if (buf_len != HT_OP_IE_LEN) {
+ RTW_PRINT_SEL(sel, "Invalid HT operation IE len:%d != %d\n", buf_len, HT_OP_IE_LEN);
+ return;
+ }
+
+ RTW_PRINT_SEL(sel, "ch:%u%s %s\n"
+ , GET_HT_OP_ELE_PRI_CHL(buf)
+ , GET_HT_OP_ELE_STA_CHL_WIDTH(buf) ? "" : " 20MHz only"
+ , ht_sc_offset_str(GET_HT_OP_ELE_2ND_CHL_OFFSET(buf))
+ );
+}
+
+void dump_ht_op_ie(void *sel, const u8 *ie, u32 ie_len)
+{
+ const u8 *pos = ie;
+ u16 id;
+ u16 len;
+
+ const u8 *ht_op_ie;
+ sint ht_op_ielen;
+
+ ht_op_ie = rtw_get_ie(ie, WLAN_EID_HT_OPERATION, &ht_op_ielen, ie_len);
+ if (!ie || ht_op_ie != ie)
+ return;
+
+ dump_ht_op_ie_content(sel, ht_op_ie + 2, ht_op_ielen);
+}
#endif /* CONFIG_80211N_HT */
-void dump_ies(void *sel, u8 *buf, u32 buf_len)
+void dump_ies(void *sel, const u8 *buf, u32 buf_len)
{
- u8 *pos = (u8 *)buf;
+ const u8 *pos = buf;
u8 id, len;
while (pos - buf + 1 < buf_len) {
@@ -1522,6 +1606,11 @@ void dump_ies(void *sel, u8 *buf, u32 buf_len)
RTW_PRINT_SEL(sel, "%s ID:%u, LEN:%u\n", __FUNCTION__, id, len);
#ifdef CONFIG_80211N_HT
dump_ht_cap_ie(sel, pos, len + 2);
+ dump_ht_op_ie(sel, pos, len + 2);
+#endif
+#ifdef CONFIG_80211AC_VHT
+ dump_vht_cap_ie(sel, pos, len + 2);
+ dump_vht_op_ie(sel, pos, len + 2);
#endif
dump_wps_ie(sel, pos, len + 2);
#ifdef CONFIG_P2P
@@ -1535,13 +1624,13 @@ void dump_ies(void *sel, u8 *buf, u32 buf_len)
}
}
-void dump_wps_ie(void *sel, u8 *ie, u32 ie_len)
+void dump_wps_ie(void *sel, const u8 *ie, u32 ie_len)
{
- u8 *pos = (u8 *)ie;
+ const u8 *pos = ie;
u16 id;
u16 len;
- u8 *wps_ie;
+ const u8 *wps_ie;
uint wps_ielen;
wps_ie = rtw_get_wps_ie(ie, ie_len, NULL, &wps_ielen);
@@ -1567,8 +1656,10 @@ void dump_wps_ie(void *sel, u8 *ie, u32 ie_len)
* @ch: pointer of ch, used as output
* @bw: pointer of bw, used as output
* @offset: pointer of offset, used as output
+ * @ht: check HT IEs
+ * @vht: check VHT IEs, if true imply ht is true
*/
-void rtw_ies_get_chbw(u8 *ies, int ies_len, u8 *ch, u8 *bw, u8 *offset)
+void rtw_ies_get_chbw(u8 *ies, int ies_len, u8 *ch, u8 *bw, u8 *offset, u8 ht, u8 vht)
{
u8 *p;
int ie_len;
@@ -1582,7 +1673,7 @@ void rtw_ies_get_chbw(u8 *ies, int ies_len, u8 *ch, u8 *bw, u8 *offset)
*ch = *(p + 2);
#ifdef CONFIG_80211N_HT
- {
+ if (ht || vht) {
u8 *ht_cap_ie, *ht_op_ie;
int ht_cap_ielen, ht_op_ielen;
@@ -1615,44 +1706,29 @@ void rtw_ies_get_chbw(u8 *ies, int ies_len, u8 *ch, u8 *bw, u8 *offset)
}
}
}
- }
-#endif /* CONFIG_80211N_HT */
+
#ifdef CONFIG_80211AC_VHT
- {
- u8 *vht_op_ie;
- int vht_op_ielen;
-
- vht_op_ie = rtw_get_ie(ies, EID_VHTOperation, &vht_op_ielen, ies_len);
- if (vht_op_ie && vht_op_ielen) {
- /* enable VHT 80 before check enable HT40 or not */
- if (GET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2) >= 1) {
- /* for HT40, enable VHT80 */
- if (*bw == CHANNEL_WIDTH_40)
+ if (vht) {
+ u8 *vht_op_ie;
+ int vht_op_ielen;
+
+ vht_op_ie = rtw_get_ie(ies, EID_VHTOperation, &vht_op_ielen, ies_len);
+ if (vht_op_ie && vht_op_ielen) {
+ if (GET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2) >= 1)
*bw = CHANNEL_WIDTH_80;
- /* for HT20, enable VHT20 */
- else if (*bw == CHANNEL_WIDTH_20) {
- /* modify VHT OP IE */
- SET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2, 0);
- /* reset to 0 for VHT20 */
- SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op_ie + 2, 0);
- SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op_ie + 2, 0);
- }
- } else {
- /*
- VHT OP WIDTH = 0 under HT20/HT40
- if REGSTY_BW_5G(pregistrypriv) < CHANNEL_WIDTH_80 in rtw_build_vht_operation_ie
- */
}
}
+#endif /* CONFIG_80211AC_VHT */
+
}
-#endif
+#endif /* CONFIG_80211N_HT */
}
-void rtw_bss_get_chbw(WLAN_BSSID_EX *bss, u8 *ch, u8 *bw, u8 *offset)
+void rtw_bss_get_chbw(WLAN_BSSID_EX *bss, u8 *ch, u8 *bw, u8 *offset, u8 ht, u8 vht)
{
rtw_ies_get_chbw(bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)
- , bss->IELength - sizeof(NDIS_802_11_FIXED_IEs)
- , ch, bw, offset);
+ , bss->IELength - sizeof(NDIS_802_11_FIXED_IEs)
+ , ch, bw, offset, ht, vht);
if (*ch == 0)
*ch = bss->Configuration.DSConfig;
@@ -1719,7 +1795,7 @@ void rtw_sync_chbw(u8 *req_ch, u8 *req_bw, u8 *req_offset
if (*g_bw == CHANNEL_WIDTH_40 || *g_bw == CHANNEL_WIDTH_80)
*req_offset = *g_offset;
else if (*g_bw == CHANNEL_WIDTH_20)
- *req_offset = rtw_get_offset_by_ch(*req_ch);
+ rtw_get_offset_by_chbw(*req_ch, *req_bw, req_offset);
if (*req_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) {
RTW_ERR("%s req 80MHz BW without offset, down to 20MHz\n", __func__);
@@ -1731,7 +1807,7 @@ void rtw_sync_chbw(u8 *req_ch, u8 *req_bw, u8 *req_offset
if (*g_bw == CHANNEL_WIDTH_40 || *g_bw == CHANNEL_WIDTH_80)
*req_offset = *g_offset;
else if (*g_bw == CHANNEL_WIDTH_20)
- *req_offset = rtw_get_offset_by_ch(*req_ch);
+ rtw_get_offset_by_chbw(*req_ch, *req_bw, req_offset);
if (*req_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) {
RTW_ERR("%s req 40MHz BW without offset, down to 20MHz\n", __func__);
@@ -1819,13 +1895,13 @@ int rtw_p2p_merge_ies(u8 *in_ie, u32 in_len, u8 *merge_ie)
return 0;
}
-void dump_p2p_ie(void *sel, u8 *ie, u32 ie_len)
+void dump_p2p_ie(void *sel, const u8 *ie, u32 ie_len)
{
- u8 *pos = (u8 *)ie;
+ const u8 *pos = ie;
u8 id;
u16 len;
- u8 *p2p_ie;
+ const u8 *p2p_ie;
uint p2p_ielen;
p2p_ie = rtw_get_p2p_ie(ie, ie_len, NULL, &p2p_ielen);
@@ -1853,10 +1929,10 @@ void dump_p2p_ie(void *sel, u8 *ie, u32 ie_len)
*
* Returns: The address of the P2P IE found, or NULL
*/
-u8 *rtw_get_p2p_ie(u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen)
+u8 *rtw_get_p2p_ie(const u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen)
{
uint cnt;
- u8 *p2p_ie_ptr = NULL;
+ const u8 *p2p_ie_ptr = NULL;
u8 eid, p2p_oui[4] = {0x50, 0x6F, 0x9A, 0x09};
if (p2p_ielen)
@@ -1864,11 +1940,11 @@ u8 *rtw_get_p2p_ie(u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen)
if (!in_ie || in_len < 0) {
rtw_warn_on(1);
- return p2p_ie_ptr;
+ return (u8 *)p2p_ie_ptr;
}
if (in_len <= 0)
- return p2p_ie_ptr;
+ return (u8 *)p2p_ie_ptr;
cnt = 0;
@@ -1895,7 +1971,7 @@ u8 *rtw_get_p2p_ie(u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen)
}
- return p2p_ie_ptr;
+ return (u8 *)p2p_ie_ptr;
}
/**
@@ -2163,13 +2239,13 @@ void rtw_bss_ex_del_p2p_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id)
}
}
-void dump_wfd_ie(void *sel, u8 *ie, u32 ie_len)
+void dump_wfd_ie(void *sel, const u8 *ie, u32 ie_len)
{
- u8 *pos = (u8 *)ie;
+ const u8 *pos = ie;
u8 id;
u16 len;
- u8 *wfd_ie;
+ const u8 *wfd_ie;
uint wfd_ielen;
wfd_ie = rtw_get_wfd_ie(ie, ie_len, NULL, &wfd_ielen);
@@ -2197,10 +2273,10 @@ void dump_wfd_ie(void *sel, u8 *ie, u32 ie_len)
*
* Returns: The address of the P2P IE found, or NULL
*/
-u8 *rtw_get_wfd_ie(u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen)
+u8 *rtw_get_wfd_ie(const u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen)
{
uint cnt;
- u8 *wfd_ie_ptr = NULL;
+ const u8 *wfd_ie_ptr = NULL;
u8 eid, wfd_oui[4] = {0x50, 0x6F, 0x9A, 0x0A};
if (wfd_ielen)
@@ -2208,11 +2284,11 @@ u8 *rtw_get_wfd_ie(u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen)
if (!in_ie || in_len < 0) {
rtw_warn_on(1);
- return wfd_ie_ptr;
+ return (u8 *)wfd_ie_ptr;
}
if (in_len <= 0)
- return wfd_ie_ptr;
+ return (u8 *)wfd_ie_ptr;
cnt = 0;
@@ -2239,7 +2315,7 @@ u8 *rtw_get_wfd_ie(u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen)
}
- return wfd_ie_ptr;
+ return (u8 *)wfd_ie_ptr;
}
/**
@@ -2542,14 +2618,11 @@ int rtw_get_cipher_info(struct wlan_network *pnetwork)
pbuf = rtw_get_wpa_ie(&pnetwork->network.IEs[12], &wpa_ielen, pnetwork->network.IELength - 12);
if (pbuf && (wpa_ielen > 0)) {
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("rtw_get_cipher_info: wpa_ielen: %d", wpa_ielen));
if (_SUCCESS == rtw_parse_wpa_ie(pbuf, wpa_ielen + 2, &group_cipher, &pairwise_cipher, &is8021x)) {
pnetwork->BcnInfo.pairwise_cipher = pairwise_cipher;
pnetwork->BcnInfo.group_cipher = group_cipher;
pnetwork->BcnInfo.is_8021x = is8021x;
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("%s: pnetwork->pairwise_cipher: %d, is_8021x is %d",
- __func__, pnetwork->BcnInfo.pairwise_cipher, pnetwork->BcnInfo.is_8021x));
ret = _SUCCESS;
}
} else {
@@ -2557,15 +2630,10 @@ int rtw_get_cipher_info(struct wlan_network *pnetwork)
pbuf = rtw_get_wpa2_ie(&pnetwork->network.IEs[12], &wpa_ielen, pnetwork->network.IELength - 12);
if (pbuf && (wpa_ielen > 0)) {
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("get RSN IE\n"));
- if (_SUCCESS == rtw_parse_wpa2_ie(pbuf, wpa_ielen + 2, &group_cipher, &pairwise_cipher, &is8021x)) {
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("get RSN IE OK!!!\n"));
+ if (_SUCCESS == rtw_parse_wpa2_ie(pbuf, wpa_ielen + 2, &group_cipher, &pairwise_cipher, &is8021x, NULL)) {
pnetwork->BcnInfo.pairwise_cipher = pairwise_cipher;
pnetwork->BcnInfo.group_cipher = group_cipher;
pnetwork->BcnInfo.is_8021x = is8021x;
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("%s: pnetwork->pairwise_cipher: %d,"
- "pnetwork->group_cipher is %d, is_8021x is %d", __func__, pnetwork->BcnInfo.pairwise_cipher,
- pnetwork->BcnInfo.group_cipher, pnetwork->BcnInfo.is_8021x));
ret = _SUCCESS;
}
}
@@ -2593,10 +2661,6 @@ void rtw_get_bcn_info(struct wlan_network *pnetwork)
} else
pnetwork->BcnInfo.encryp_protocol = ENCRYP_PROTOCOL_OPENSYS;
rtw_get_sec_ie(pnetwork->network.IEs , pnetwork->network.IELength, NULL, &rsn_len, NULL, &wpa_len);
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("rtw_get_bcn_info: ssid=%s\n", pnetwork->network.Ssid.Ssid));
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("rtw_get_bcn_info: wpa_len=%d rsn_len=%d\n", wpa_len, rsn_len));
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("rtw_get_bcn_info: ssid=%s\n", pnetwork->network.Ssid.Ssid));
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("rtw_get_bcn_info: wpa_len=%d rsn_len=%d\n", wpa_len, rsn_len));
if (rsn_len > 0)
pnetwork->BcnInfo.encryp_protocol = ENCRYP_PROTOCOL_WPA2;
@@ -2606,10 +2670,6 @@ void rtw_get_bcn_info(struct wlan_network *pnetwork)
if (bencrypt)
pnetwork->BcnInfo.encryp_protocol = ENCRYP_PROTOCOL_WEP;
}
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("rtw_get_bcn_info: pnetwork->encryp_protocol is %x\n",
- pnetwork->BcnInfo.encryp_protocol));
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("rtw_get_bcn_info: pnetwork->encryp_protocol is %x\n",
- pnetwork->BcnInfo.encryp_protocol));
rtw_get_cipher_info(pnetwork);
/* get bwmode and ch_offset */
@@ -2647,13 +2707,43 @@ u8 rtw_ht_mcsset_to_nss(u8 *supp_mcs_set)
return nss;
}
+u32 rtw_ht_mcs_set_to_bitmap(u8 *mcs_set, u8 nss)
+{
+ u8 i;
+ u32 bitmap = 0;
+
+ for (i = 0; i < nss; i++)
+ bitmap |= mcs_set[i] << (i * 8);
+
+ RTW_INFO("ht_mcs_set=%02x %02x %02x %02x, nss=%u, bitmap=%08x\n"
+ , mcs_set[0], mcs_set[1], mcs_set[2], mcs_set[3], nss, bitmap);
+
+ return bitmap;
+}
+
/* show MCS rate, unit: 100Kbps */
u16 rtw_mcs_rate(u8 rf_type, u8 bw_40MHz, u8 short_GI, unsigned char *MCS_rate)
{
u16 max_rate = 0;
- /*MCS_rate[2] = 3T3R , MCS_rate[1] = 2T2R , MCS_rate[0] = 1T1R*/
- if (MCS_rate[2]) {
+ if (MCS_rate[3]) {
+ if (MCS_rate[3] & BIT(7))
+ max_rate = (bw_40MHz) ? ((short_GI) ? 6000 : 5400) : ((short_GI) ? 2889 : 2600);
+ else if (MCS_rate[3] & BIT(6))
+ max_rate = (bw_40MHz) ? ((short_GI) ? 5400 : 4860) : ((short_GI) ? 2600 : 2340);
+ else if (MCS_rate[3] & BIT(5))
+ max_rate = (bw_40MHz) ? ((short_GI) ? 4800 : 4320) : ((short_GI) ? 2311 : 2080);
+ else if (MCS_rate[3] & BIT(4))
+ max_rate = (bw_40MHz) ? ((short_GI) ? 3600 : 3240) : ((short_GI) ? 1733 : 1560);
+ else if (MCS_rate[3] & BIT(3))
+ max_rate = (bw_40MHz) ? ((short_GI) ? 2400 : 2160) : ((short_GI) ? 1156 : 1040);
+ else if (MCS_rate[3] & BIT(2))
+ max_rate = (bw_40MHz) ? ((short_GI) ? 1800 : 1620) : ((short_GI) ? 867 : 780);
+ else if (MCS_rate[3] & BIT(1))
+ max_rate = (bw_40MHz) ? ((short_GI) ? 1200 : 1080) : ((short_GI) ? 578 : 520);
+ else if (MCS_rate[3] & BIT(0))
+ max_rate = (bw_40MHz) ? ((short_GI) ? 600 : 540) : ((short_GI) ? 289 : 260);
+ } else if (MCS_rate[2]) {
if (MCS_rate[2] & BIT(7))
max_rate = (bw_40MHz) ? ((short_GI) ? 4500 : 4050) : ((short_GI) ? 2167 : 1950);
else if (MCS_rate[2] & BIT(6))
@@ -2765,3 +2855,4 @@ const char *action_public_str(u8 action)
action = (action >= ACT_PUBLIC_MAX) ? ACT_PUBLIC_MAX : action;
return _action_public_str[action];
}
+
diff --git a/core/rtw_io.c b/core/rtw_io.c
index 10f929d..cb8e6b8 100644
--- a/core/rtw_io.c
+++ b/core/rtw_io.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,12 +11,7 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
/*
The purpose of rtw_io.c
@@ -56,7 +51,7 @@ jackson@realtek.com.tw
#error "Shall be Linux or Windows, but not both!\n"
#endif
-#ifdef CONFIG_SDIO_HCI
+#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_PLATFORM_RTL8197D)
#define rtw_le16_to_cpu(val) val
#define rtw_le32_to_cpu(val) val
#define rtw_cpu_to_le16(val) val
@@ -76,11 +71,9 @@ u8 _rtw_read8(_adapter *adapter, u32 addr)
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
u8(*_read8)(struct intf_hdl *pintfhdl, u32 addr);
- _func_enter_;
_read8 = pintfhdl->io_ops._read8;
r_val = _read8(pintfhdl, addr);
- _func_exit_;
return r_val;
}
@@ -91,11 +84,9 @@ u16 _rtw_read16(_adapter *adapter, u32 addr)
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
u16(*_read16)(struct intf_hdl *pintfhdl, u32 addr);
- _func_enter_;
_read16 = pintfhdl->io_ops._read16;
r_val = _read16(pintfhdl, addr);
- _func_exit_;
return rtw_le16_to_cpu(r_val);
}
@@ -106,11 +97,9 @@ u32 _rtw_read32(_adapter *adapter, u32 addr)
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
u32(*_read32)(struct intf_hdl *pintfhdl, u32 addr);
- _func_enter_;
_read32 = pintfhdl->io_ops._read32;
r_val = _read32(pintfhdl, addr);
- _func_exit_;
return rtw_le32_to_cpu(r_val);
}
@@ -122,11 +111,9 @@ int _rtw_write8(_adapter *adapter, u32 addr, u8 val)
struct intf_hdl *pintfhdl = &(pio_priv->intf);
int (*_write8)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
int ret;
- _func_enter_;
_write8 = pintfhdl->io_ops._write8;
ret = _write8(pintfhdl, addr, val);
- _func_exit_;
return RTW_STATUS_CODE(ret);
}
@@ -137,12 +124,10 @@ int _rtw_write16(_adapter *adapter, u32 addr, u16 val)
struct intf_hdl *pintfhdl = &(pio_priv->intf);
int (*_write16)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
int ret;
- _func_enter_;
_write16 = pintfhdl->io_ops._write16;
val = rtw_cpu_to_le16(val);
ret = _write16(pintfhdl, addr, val);
- _func_exit_;
return RTW_STATUS_CODE(ret);
}
@@ -153,12 +138,10 @@ int _rtw_write32(_adapter *adapter, u32 addr, u32 val)
struct intf_hdl *pintfhdl = &(pio_priv->intf);
int (*_write32)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
int ret;
- _func_enter_;
_write32 = pintfhdl->io_ops._write32;
val = rtw_cpu_to_le32(val);
ret = _write32(pintfhdl, addr, val);
- _func_exit_;
return RTW_STATUS_CODE(ret);
}
@@ -170,11 +153,9 @@ int _rtw_writeN(_adapter *adapter, u32 addr , u32 length , u8 *pdata)
struct intf_hdl *pintfhdl = (struct intf_hdl *)(&(pio_priv->intf));
int (*_writeN)(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata);
int ret;
- _func_enter_;
_writeN = pintfhdl->io_ops._writeN;
ret = _writeN(pintfhdl, addr, length, pdata);
- _func_exit_;
return RTW_STATUS_CODE(ret);
}
@@ -187,7 +168,6 @@ u8 _rtw_sd_f0_read8(_adapter *adapter, u32 addr)
struct intf_hdl *pintfhdl = &(pio_priv->intf);
u8(*_sd_f0_read8)(struct intf_hdl *pintfhdl, u32 addr);
- _func_enter_;
_sd_f0_read8 = pintfhdl->io_ops._sd_f0_read8;
if (_sd_f0_read8)
@@ -195,7 +175,6 @@ u8 _rtw_sd_f0_read8(_adapter *adapter, u32 addr)
else
RTW_WARN(FUNC_ADPT_FMT" _sd_f0_read8 callback is NULL\n", FUNC_ADPT_ARG(adapter));
- _func_exit_;
return r_val;
}
@@ -312,11 +291,9 @@ int _rtw_write8_async(_adapter *adapter, u32 addr, u8 val)
struct intf_hdl *pintfhdl = &(pio_priv->intf);
int (*_write8_async)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
int ret;
- _func_enter_;
_write8_async = pintfhdl->io_ops._write8_async;
ret = _write8_async(pintfhdl, addr, val);
- _func_exit_;
return RTW_STATUS_CODE(ret);
}
@@ -327,11 +304,9 @@ int _rtw_write16_async(_adapter *adapter, u32 addr, u16 val)
struct intf_hdl *pintfhdl = &(pio_priv->intf);
int (*_write16_async)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
int ret;
- _func_enter_;
_write16_async = pintfhdl->io_ops._write16_async;
val = rtw_cpu_to_le16(val);
ret = _write16_async(pintfhdl, addr, val);
- _func_exit_;
return RTW_STATUS_CODE(ret);
}
@@ -342,11 +317,9 @@ int _rtw_write32_async(_adapter *adapter, u32 addr, u32 val)
struct intf_hdl *pintfhdl = &(pio_priv->intf);
int (*_write32_async)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
int ret;
- _func_enter_;
_write32_async = pintfhdl->io_ops._write32_async;
val = rtw_cpu_to_le32(val);
ret = _write32_async(pintfhdl, addr, val);
- _func_exit_;
return RTW_STATUS_CODE(ret);
}
@@ -358,12 +331,8 @@ void _rtw_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
- _func_enter_;
if (RTW_CANNOT_RUN(adapter)) {
- RT_TRACE(_module_rtl871x_io_c_, _drv_info_, ("rtw_read_mem:bDriverStopped(%s) OR bSurpriseRemoved(%s)"
- , rtw_is_drv_stopped(adapter) ? "True" : "False"
- , rtw_is_surprise_removed(adapter) ? "True" : "False"));
return;
}
@@ -371,7 +340,6 @@ void _rtw_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
_read_mem(pintfhdl, addr, cnt, pmem);
- _func_exit_;
}
@@ -382,13 +350,11 @@ void _rtw_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
- _func_enter_;
_write_mem = pintfhdl->io_ops._write_mem;
_write_mem(pintfhdl, addr, cnt, pmem);
- _func_exit_;
}
@@ -399,12 +365,8 @@ void _rtw_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
struct io_priv *pio_priv = &adapter->iopriv;
struct intf_hdl *pintfhdl = &(pio_priv->intf);
- _func_enter_;
if (RTW_CANNOT_RUN(adapter)) {
- RT_TRACE(_module_rtl871x_io_c_, _drv_info_, ("rtw_read_port:bDriverStopped(%s) OR bSurpriseRemoved(%s)"
- , rtw_is_drv_stopped(adapter) ? "True" : "False"
- , rtw_is_surprise_removed(adapter) ? "True" : "False"));
return;
}
@@ -412,7 +374,6 @@ void _rtw_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
_read_port(pintfhdl, addr, cnt, pmem);
- _func_exit_;
}
@@ -438,13 +399,11 @@ u32 _rtw_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
struct intf_hdl *pintfhdl = &(pio_priv->intf);
u32 ret = _SUCCESS;
- _func_enter_;
_write_port = pintfhdl->io_ops._write_port;
ret = _write_port(pintfhdl, addr, cnt, pmem);
- _func_exit_;
return ret;
}
diff --git a/core/rtw_ioctl_query.c b/core/rtw_ioctl_query.c
index e9423ab..6f7613e 100644
--- a/core/rtw_ioctl_query.c
+++ b/core/rtw_ioctl_query.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,12 +11,7 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#define _RTW_IOCTL_QUERY_C_
#include
@@ -68,7 +63,6 @@ query_802_11_capability(
return _TRUE;
} else {
*pulOutLen = 0;
- RT_TRACE(_module_rtl871x_ioctl_query_c_, _drv_info_, ("_query_802_11_capability(): szAuthEnc size is too large.\n"));
return _FALSE;
}
}
@@ -106,13 +100,9 @@ u8 query_802_11_association_information(_adapter *padapter, PNDIS_802_11_ASSOCIA
else
pDest[0] = 221; /* WPA(SSN) Information Element */
- RT_TRACE(_module_rtl871x_ioctl_query_c_, _drv_info_, ("\n Adapter->ndisauthtype==Ndis802_11AuthModeWPA)?0xdd:0x30 [%d]", pDest[0]));
supp_ie = &psecuritypriv->supplicant_ie[0];
- for (i = 0; i < supp_ie[0]; i++)
- RT_TRACE(_module_rtl871x_ioctl_query_c_, _drv_info_, ("IEs [%d] = 0x%x \n\n", i, supp_ie[i]));
i = 13; /* 0~11 is fixed information element */
- RT_TRACE(_module_rtl871x_ioctl_query_c_, _drv_info_, ("i= %d tgt_network->network.IELength=%d\n\n", i, (int)psecnetwork->IELength));
while ((i < supp_ie[0]) && (i < 256)) {
if ((unsigned char)supp_ie[i] == pDest[0]) {
_rtw_memcpy((u8 *)(pDest),
@@ -125,7 +115,6 @@ u8 query_802_11_association_information(_adapter *padapter, PNDIS_802_11_ASSOCIA
i = i + supp_ie[i + 1] + 2;
if (supp_ie[1 + i] == 0)
i = i + 1;
- RT_TRACE(_module_rtl871x_ioctl_query_c_, _drv_info_, ("iteration i=%d IEs [%d] = 0x%x \n\n", i, i, supp_ie[i + 1]));
}
@@ -135,7 +124,6 @@ u8 query_802_11_association_information(_adapter *padapter, PNDIS_802_11_ASSOCIA
}
- RT_TRACE(_module_rtl871x_ioctl_query_c_, _drv_info_, ("\n psecnetwork != NULL,fwstate==_FW_UNDER_LINKING\n"));
}
@@ -159,8 +147,6 @@ u8 query_802_11_association_information(_adapter *padapter, PNDIS_802_11_ASSOCIA
pDest = (u8 *)pAssocInfo + sizeof(NDIS_802_11_ASSOCIATION_INFORMATION) + pAssocInfo->RequestIELength;
auth_ie = &psecuritypriv->authenticator_ie[0];
- for (i = 0; i < auth_ie[0]; i++)
- RT_TRACE(_module_rtl871x_ioctl_query_c_, _drv_info_, ("IEs [%d] = 0x%x \n\n", i, auth_ie[i]));
i = auth_ie[0] - 12;
if (i > 0) {
@@ -172,11 +158,8 @@ u8 query_802_11_association_information(_adapter *padapter, PNDIS_802_11_ASSOCIA
pAssocInfo->OffsetResponseIEs = sizeof(NDIS_802_11_ASSOCIATION_INFORMATION) + pAssocInfo->RequestIELength;
- RT_TRACE(_module_rtl871x_ioctl_query_c_, _drv_info_, ("\n tgt_network != NULL,fwstate==_FW_LINKED\n"));
}
}
- RT_TRACE(_module_rtl871x_ioctl_query_c_, _drv_info_, ("\n exit query_802_11_association_information\n"));
- _func_exit_;
return _TRUE;
}
diff --git a/core/rtw_ioctl_rtl.c b/core/rtw_ioctl_rtl.c
index 0459138..5d9e76b 100644
--- a/core/rtw_ioctl_rtl.c
+++ b/core/rtw_ioctl_rtl.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,12 +11,7 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#define _RTW_IOCTL_RTL_C_
#include
@@ -154,7 +149,6 @@ NDIS_STATUS oid_rt_pro_set_fw_dig_state_hdl(struct oid_par_priv *poid_par_priv)
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
_irqL oldirql;
- _func_enter_;
if (poid_par_priv->type_of_oid != SET_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
@@ -170,7 +164,6 @@ NDIS_STATUS oid_rt_pro_set_fw_dig_state_hdl(struct oid_par_priv *poid_par_priv)
} else
status = NDIS_STATUS_NOT_ACCEPTED;
_irqlevel_changed_(&oldirql, RAISE);
- _func_exit_;
#endif
return status;
}
@@ -183,7 +176,6 @@ NDIS_STATUS oid_rt_pro_set_fw_ra_state_hdl(struct oid_par_priv *poid_par_priv)
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
_irqL oldirql;
- _func_enter_;
if (poid_par_priv->type_of_oid != SET_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
@@ -200,7 +192,6 @@ NDIS_STATUS oid_rt_pro_set_fw_ra_state_hdl(struct oid_par_priv *poid_par_priv)
} else
status = NDIS_STATUS_NOT_ACCEPTED;
_irqlevel_changed_(&oldirql, RAISE);
- _func_exit_;
#endif
return status;
}
@@ -436,13 +427,14 @@ NDIS_STATUS oid_rt_get_channelplan_hdl(struct oid_par_priv *poid_par_priv)
{
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
if (poid_par_priv->type_of_oid != QUERY_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
- *(u16 *)poid_par_priv->information_buf = padapter->mlmepriv.ChannelPlan ;
+ *(u16 *)poid_par_priv->information_buf = rfctl->ChannelPlan;
return status;
}
@@ -450,13 +442,14 @@ NDIS_STATUS oid_rt_set_channelplan_hdl(struct oid_par_priv *poid_par_priv)
{
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
if (poid_par_priv->type_of_oid != SET_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
- padapter->mlmepriv.ChannelPlan = *(u16 *)poid_par_priv->information_buf ;
+ rfctl->ChannelPlan = *(u16 *)poid_par_priv->information_buf;
return status;
}
@@ -585,7 +578,6 @@ NDIS_STATUS oid_rt_get_channel_hdl(struct oid_par_priv *poid_par_priv)
ULONG channelnum;
- _func_enter_;
if (poid_par_priv->type_of_oid != QUERY_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
@@ -602,7 +594,6 @@ NDIS_STATUS oid_rt_get_channel_hdl(struct oid_par_priv *poid_par_priv)
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
- _func_exit_;
@@ -765,7 +756,6 @@ NDIS_STATUS oid_rt_pro_rf_write_registry_hdl(struct oid_par_priv *poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
_irqL oldirql;
- _func_enter_;
/* DEBUG_ERR(("<**********************oid_rt_pro_rf_write_registry_hdl\n")); */
if (poid_par_priv->type_of_oid != SET_OID) { /* QUERY_OID */
status = NDIS_STATUS_NOT_ACCEPTED;
@@ -788,7 +778,6 @@ NDIS_STATUS oid_rt_pro_rf_write_registry_hdl(struct oid_par_priv *poid_par_priv)
} else
status = NDIS_STATUS_INVALID_LENGTH;
_irqlevel_changed_(&oldirql, RAISE);
- _func_exit_;
return status;
}
@@ -800,7 +789,6 @@ NDIS_STATUS oid_rt_pro_rf_read_registry_hdl(struct oid_par_priv *poid_par_priv)
#if 0
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
_irqL oldirql;
- _func_enter_;
/* DEBUG_ERR(("<**********************oid_rt_pro_rf_read_registry_hdl\n")); */
if (poid_par_priv->type_of_oid != SET_OID) { /* QUERY_OID */
@@ -836,7 +824,6 @@ NDIS_STATUS oid_rt_pro_rf_read_registry_hdl(struct oid_par_priv *poid_par_priv)
} else
status = NDIS_STATUS_INVALID_LENGTH;
_irqlevel_changed_(&oldirql, RAISE);
- _func_exit_;
#endif
return status;
}
@@ -885,7 +872,6 @@ NDIS_STATUS oid_rt_get_connect_state_hdl(struct oid_par_priv *poid_par_priv)
#if 0
/* Rearrange the order to let the UI still shows connection when scan is in progress */
- RT_TRACE(COMP_OID_QUERY, DBG_LOUD, ("===> Query OID_RT_GET_CONNECT_STATE.\n"));
if (pMgntInfo->mAssoc)
ulInfo = 1;
else if (pMgntInfo->mIbss)
@@ -895,7 +881,6 @@ NDIS_STATUS oid_rt_get_connect_state_hdl(struct oid_par_priv *poid_par_priv)
else
ulInfo = 3;
ulInfoLen = sizeof(ULONG);
- RT_TRACE(COMP_OID_QUERY, DBG_LOUD, ("<=== Query OID_RT_GET_CONNECT_STATE: %d\n", ulInfo));
#endif
return status;
diff --git a/core/rtw_ioctl_set.c b/core/rtw_ioctl_set.c
index 6761aa4..e26f74a 100644
--- a/core/rtw_ioctl_set.c
+++ b/core/rtw_ioctl_set.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,12 +11,7 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#define _RTW_IOCTL_SET_C_
#include
@@ -50,10 +45,8 @@ u8 rtw_validate_ssid(NDIS_802_11_SSID *ssid)
u8 i;
u8 ret = _TRUE;
- _func_enter_;
if (ssid->SsidLength > 32) {
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("ssid length >32\n"));
ret = _FALSE;
goto exit;
}
@@ -62,7 +55,6 @@ u8 rtw_validate_ssid(NDIS_802_11_SSID *ssid)
for (i = 0; i < ssid->SsidLength; i++) {
/* wifi, printable ascii code must be supported */
if (!((ssid->Ssid[i] >= 0x20) && (ssid->Ssid[i] <= 0x7e))) {
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("ssid has nonprintabl ascii\n"));
ret = _FALSE;
break;
}
@@ -71,7 +63,6 @@ u8 rtw_validate_ssid(NDIS_802_11_SSID *ssid)
exit:
- _func_exit_;
return ret;
}
@@ -83,16 +74,15 @@ u8 rtw_do_join(_adapter *padapter)
_list *plist, *phead;
u8 *pibss = NULL;
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+ struct sitesurvey_parm parm;
_queue *queue = &(pmlmepriv->scanned_queue);
u8 ret = _SUCCESS;
- _func_enter_;
_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
phead = get_list_head(queue);
plist = get_next(phead);
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("\n rtw_do_join: phead = %p; plist = %p \n\n\n", phead, plist));
pmlmepriv->cur_network.join_res = -2;
@@ -102,6 +92,10 @@ u8 rtw_do_join(_adapter *padapter)
pmlmepriv->to_join = _TRUE;
+ rtw_init_sitesurvey_parm(padapter, &parm);
+ _rtw_memcpy(&parm.ssid[0], &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID));
+ parm.ssid_num = 1;
+
if (_rtw_queue_empty(queue) == _TRUE) {
_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
@@ -112,12 +106,10 @@ u8 rtw_do_join(_adapter *padapter)
if (pmlmepriv->LinkDetectInfo.bBusyTraffic == _FALSE
|| rtw_to_roam(padapter) > 0
) {
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("rtw_do_join(): site survey if scanned_queue is empty\n."));
/* submit site_survey_cmd */
- ret = rtw_sitesurvey_cmd(padapter, &pmlmepriv->assoc_ssid, 1, NULL, 0);
+ ret = rtw_sitesurvey_cmd(padapter, &parm);
if (_SUCCESS != ret) {
pmlmepriv->to_join = _FALSE;
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("rtw_do_join(): site survey return error\n."));
}
} else {
pmlmepriv->to_join = _FALSE;
@@ -152,14 +144,12 @@ u8 rtw_do_join(_adapter *padapter)
rtw_generate_random_ibss(pibss);
if (rtw_create_ibss_cmd(padapter, 0) != _SUCCESS) {
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("***Error=>do_goin: rtw_create_ibss_cmd status FAIL***\n"));
ret = _FALSE;
goto exit;
}
pmlmepriv->to_join = _FALSE;
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("***Error=> rtw_select_and_join_from_scanned_queue FAIL under STA_Mode***\n "));
} else {
/* can't associate ; reset under-linking */
@@ -170,9 +160,8 @@ u8 rtw_do_join(_adapter *padapter)
if (_rtw_memcmp(pmlmepriv->cur_network.network.Ssid.Ssid, pmlmepriv->assoc_ssid.Ssid, pmlmepriv->assoc_ssid.SsidLength)) {
/* for funk to do roaming */
/* funk will reconnect, but funk will not sitesurvey before reconnect */
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("for funk to do roaming"));
if (pmlmepriv->sitesurveyctrl.traffic_busy == _FALSE)
- rtw_sitesurvey_cmd(padapter, &pmlmepriv->assoc_ssid, 1, NULL, 0);
+ rtw_sitesurvey_cmd(padapter, &parm);
}
}
@@ -184,10 +173,9 @@ u8 rtw_do_join(_adapter *padapter)
|| rtw_to_roam(padapter) > 0
) {
/* RTW_INFO("rtw_do_join() when no desired bss in scanning queue\n"); */
- ret = rtw_sitesurvey_cmd(padapter, &pmlmepriv->assoc_ssid, 1, NULL, 0);
+ ret = rtw_sitesurvey_cmd(padapter, &parm);
if (_SUCCESS != ret) {
pmlmepriv->to_join = _FALSE;
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("do_join(): site survey return error\n."));
}
} else {
ret = _FAIL;
@@ -201,7 +189,6 @@ u8 rtw_do_join(_adapter *padapter)
exit:
- _func_exit_;
return ret;
}
@@ -210,15 +197,11 @@ u8 rtw_pnp_set_power_wakeup(_adapter *padapter)
{
u8 res = _SUCCESS;
- _func_enter_;
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("==>rtw_pnp_set_power_wakeup!!!\n"));
res = rtw_setstandby_cmd(padapter, 0);
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("<==rtw_pnp_set_power_wakeup!!!\n"));
- _func_exit_;
return res;
}
@@ -227,29 +210,20 @@ u8 rtw_pnp_set_power_sleep(_adapter *padapter)
{
u8 res = _SUCCESS;
- _func_enter_;
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("==>rtw_pnp_set_power_sleep!!!\n"));
/* DbgPrint("+rtw_pnp_set_power_sleep\n"); */
res = rtw_setstandby_cmd(padapter, 1);
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("<==rtw_pnp_set_power_sleep!!!\n"));
- _func_exit_;
return res;
}
u8 rtw_set_802_11_reload_defaults(_adapter *padapter, NDIS_802_11_RELOAD_DEFAULTS reloadDefaults)
{
- _func_enter_;
- switch (reloadDefaults) {
- case Ndis802_11ReloadWEPKeys:
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("SetInfo OID_802_11_RELOAD_DEFAULTS : Ndis802_11ReloadWEPKeys\n"));
- break;
- }
+
/* SecClearAllKeys(Adapter); */
/* 8711 CAM was not for En/Decrypt only */
@@ -258,7 +232,6 @@ u8 rtw_set_802_11_reload_defaults(_adapter *padapter, NDIS_802_11_RELOAD_DEFAULT
/* TO DO... */
- _func_exit_;
return _TRUE;
}
@@ -267,7 +240,6 @@ u8 set_802_11_test(_adapter *padapter, NDIS_802_11_TEST *test)
{
u8 ret = _TRUE;
- _func_enter_;
switch (test->Type) {
case 1:
@@ -285,7 +257,6 @@ u8 set_802_11_test(_adapter *padapter, NDIS_802_11_TEST *test)
break;
}
- _func_exit_;
return ret;
}
@@ -306,7 +277,6 @@ u8 rtw_set_802_11_bssid(_adapter *padapter, u8 *bssid)
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
- _func_enter_;
RTW_PRINT("set bssid:%pM\n", bssid);
@@ -326,17 +296,13 @@ u8 rtw_set_802_11_bssid(_adapter *padapter, u8 *bssid)
goto release_mlme_lock;
if (check_fwstate(pmlmepriv, _FW_LINKED | WIFI_ADHOC_MASTER_STATE) == _TRUE) {
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("set_bssid: _FW_LINKED||WIFI_ADHOC_MASTER_STATE\n"));
if (_rtw_memcmp(&pmlmepriv->cur_network.network.MacAddress, bssid, ETH_ALEN) == _TRUE) {
if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _FALSE)
goto release_mlme_lock;/* it means driver is in WIFI_ADHOC_MASTER_STATE, we needn't create bss again. */
} else {
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("Set BSSID not the same bssid\n"));
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("set_bssid="MAC_FMT"\n", MAC_ARG(bssid)));
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("cur_bssid="MAC_FMT"\n", MAC_ARG(pmlmepriv->cur_network.network.MacAddress)));
- rtw_disassoc_cmd(padapter, 0, _TRUE);
+ rtw_disassoc_cmd(padapter, 0, 0);
if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
rtw_indicate_disconnect(padapter, 0, _FALSE);
@@ -369,10 +335,7 @@ u8 rtw_set_802_11_bssid(_adapter *padapter, u8 *bssid)
_exit_critical_bh(&pmlmepriv->lock, &irqL);
exit:
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_,
- ("rtw_set_802_11_bssid: status=%d\n", status));
- _func_exit_;
return status;
}
@@ -386,14 +349,11 @@ u8 rtw_set_802_11_ssid(_adapter *padapter, NDIS_802_11_SSID *ssid)
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct wlan_network *pnetwork = &pmlmepriv->cur_network;
- _func_enter_;
RTW_PRINT("set ssid [%s] fw_state=0x%08x\n",
ssid->Ssid, get_fwstate(pmlmepriv));
if (!rtw_is_hw_init_completed(padapter)) {
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_,
- ("set_ssid: hw_init_completed==_FALSE=>exit!!!\n"));
status = _FAIL;
goto exit;
}
@@ -407,19 +367,14 @@ u8 rtw_set_802_11_ssid(_adapter *padapter, NDIS_802_11_SSID *ssid)
goto release_mlme_lock;
if (check_fwstate(pmlmepriv, _FW_LINKED | WIFI_ADHOC_MASTER_STATE) == _TRUE) {
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_,
- ("set_ssid: _FW_LINKED||WIFI_ADHOC_MASTER_STATE\n"));
if ((pmlmepriv->assoc_ssid.SsidLength == ssid->SsidLength) &&
(_rtw_memcmp(&pmlmepriv->assoc_ssid.Ssid, ssid->Ssid, ssid->SsidLength) == _TRUE)) {
if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _FALSE)) {
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_,
- ("Set SSID is the same ssid, fw_state=0x%08x\n",
- get_fwstate(pmlmepriv)));
if (rtw_is_same_ibss(padapter, pnetwork) == _FALSE) {
/* if in WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE, create bss or rejoin again */
- rtw_disassoc_cmd(padapter, 0, _TRUE);
+ rtw_disassoc_cmd(padapter, 0, 0);
if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
rtw_indicate_disconnect(padapter, 0, _FALSE);
@@ -439,11 +394,8 @@ u8 rtw_set_802_11_ssid(_adapter *padapter, NDIS_802_11_SSID *ssid)
rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_JOINBSS, 1);
#endif
} else {
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("Set SSID not the same ssid\n"));
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("set_ssid=[%s] len=0x%x\n", ssid->Ssid, (unsigned int)ssid->SsidLength));
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("assoc_ssid=[%s] len=0x%x\n", pmlmepriv->assoc_ssid.Ssid, (unsigned int)pmlmepriv->assoc_ssid.SsidLength));
- rtw_disassoc_cmd(padapter, 0, _TRUE);
+ rtw_disassoc_cmd(padapter, 0, 0);
if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
rtw_indicate_disconnect(padapter, 0, _FALSE);
@@ -480,10 +432,7 @@ u8 rtw_set_802_11_ssid(_adapter *padapter, NDIS_802_11_SSID *ssid)
_exit_critical_bh(&pmlmepriv->lock, &irqL);
exit:
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_,
- ("-rtw_set_802_11_ssid: status=%d\n", status));
- _func_exit_;
return status;
@@ -498,7 +447,6 @@ u8 rtw_set_802_11_connect(_adapter *padapter, u8 *bssid, NDIS_802_11_SSID *ssid)
bool ssid_valid = _TRUE;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
- _func_enter_;
if (!ssid || rtw_validate_ssid(ssid) == _FALSE)
ssid_valid = _FALSE;
@@ -514,8 +462,6 @@ u8 rtw_set_802_11_connect(_adapter *padapter, u8 *bssid, NDIS_802_11_SSID *ssid)
}
if (!rtw_is_hw_init_completed(padapter)) {
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_,
- ("set_ssid: hw_init_completed==_FALSE=>exit!!!\n"));
status = _FAIL;
goto exit;
}
@@ -557,7 +503,6 @@ u8 rtw_set_802_11_connect(_adapter *padapter, u8 *bssid, NDIS_802_11_SSID *ssid)
exit:
- _func_exit_;
return status;
}
@@ -569,21 +514,18 @@ u8 rtw_set_802_11_infrastructure_mode(_adapter *padapter,
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct wlan_network *cur_network = &pmlmepriv->cur_network;
NDIS_802_11_NETWORK_INFRASTRUCTURE *pold_state = &(cur_network->network.InfrastructureMode);
-
- _func_enter_;
-
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_notice_,
- ("+rtw_set_802_11_infrastructure_mode: old=%d new=%d fw_state=0x%08x\n",
- *pold_state, networktype, get_fwstate(pmlmepriv)));
+ u8 ap2sta_mode = _FALSE;
+ u8 ret = _TRUE;
if (*pold_state != networktype) {
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, (" change mode!"));
/* RTW_INFO("change mode, old_mode=%d, new_mode=%d, fw_state=0x%x\n", *pold_state, networktype, get_fwstate(pmlmepriv)); */
- if (*pold_state == Ndis802_11APMode) {
- /* change to other mode from Ndis802_11APMode */
+ if (*pold_state == Ndis802_11APMode
+ || *pold_state == Ndis802_11_mesh
+ ) {
+ /* change to other mode from Ndis802_11APMode/Ndis802_11_mesh */
cur_network->join_res = -1;
-
+ ap2sta_mode = _TRUE;
#ifdef CONFIG_NATIVEAP_MLME
stop_ap_mode(padapter);
#endif
@@ -592,7 +534,7 @@ u8 rtw_set_802_11_infrastructure_mode(_adapter *padapter,
_enter_critical_bh(&pmlmepriv->lock, &irqL);
if ((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) || (*pold_state == Ndis802_11IBSS))
- rtw_disassoc_cmd(padapter, 0, _TRUE);
+ rtw_disassoc_cmd(padapter, 0, 0);
if ((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ||
(check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE))
@@ -615,6 +557,9 @@ u8 rtw_set_802_11_infrastructure_mode(_adapter *padapter,
case Ndis802_11Infrastructure:
set_fwstate(pmlmepriv, WIFI_STATION_STATE);
+
+ if (ap2sta_mode)
+ rtw_init_bcmc_stainfo(padapter);
break;
case Ndis802_11APMode:
@@ -626,25 +571,31 @@ u8 rtw_set_802_11_infrastructure_mode(_adapter *padapter,
break;
+#ifdef CONFIG_RTW_MESH
+ case Ndis802_11_mesh:
+ set_fwstate(pmlmepriv, WIFI_MESH_STATE);
+ start_ap_mode(padapter);
+ break;
+#endif
+
case Ndis802_11AutoUnknown:
case Ndis802_11InfrastructureMax:
break;
case Ndis802_11Monitor:
set_fwstate(pmlmepriv, WIFI_MONITOR_STATE);
break;
+ default:
+ ret = _FALSE;
+ rtw_warn_on(1);
}
/* SecClearAllKeys(adapter); */
- /* RT_TRACE(COMP_OID_SET, DBG_LOUD, ("set_infrastructure: fw_state:%x after changing mode\n", */
- /* get_fwstate(pmlmepriv) )); */
_exit_critical_bh(&pmlmepriv->lock, &irqL);
}
- _func_exit_;
-
- return _TRUE;
+ return ret;
}
@@ -653,14 +604,12 @@ u8 rtw_set_802_11_disassociate(_adapter *padapter)
_irqL irqL;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
- _func_enter_;
_enter_critical_bh(&pmlmepriv->lock, &irqL);
if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("MgntActrtw_set_802_11_disassociate: rtw_indicate_disconnect\n"));
- rtw_disassoc_cmd(padapter, 0, _TRUE);
+ rtw_disassoc_cmd(padapter, 0, 0);
rtw_indicate_disconnect(padapter, 0, _FALSE);
/* modify for CONFIG_IEEE80211W, none 11w can use it */
rtw_free_assoc_resources_cmd(padapter);
@@ -670,35 +619,32 @@ u8 rtw_set_802_11_disassociate(_adapter *padapter)
_exit_critical_bh(&pmlmepriv->lock, &irqL);
- _func_exit_;
return _TRUE;
}
#if 1
-u8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, NDIS_802_11_SSID *pssid, int ssid_max_num, struct rtw_ieee80211_channel *ch, int ch_num)
+u8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, struct sitesurvey_parm *pparm)
{
_irqL irqL;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
u8 res = _TRUE;
_enter_critical_bh(&pmlmepriv->lock, &irqL);
- res = rtw_sitesurvey_cmd(padapter, pssid, ssid_max_num, ch, ch_num);
+ res = rtw_sitesurvey_cmd(padapter, pparm);
_exit_critical_bh(&pmlmepriv->lock, &irqL);
return res;
}
#else
-u8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, NDIS_802_11_SSID *pssid, int ssid_max_num, struct rtw_ieee80211_channel *ch, int ch_num)
+u8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, struct sitesurvey_parm *pparm)
{
_irqL irqL;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
u8 res = _TRUE;
- _func_enter_;
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("+%s, fw_state=%x\n", __func__, get_fwstate(pmlmepriv)));
if (padapter == NULL) {
res = _FALSE;
@@ -706,20 +652,15 @@ u8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, NDIS_802_11_SSID *pssid, i
}
if (!rtw_is_hw_init_completed(padapter)) {
res = _FALSE;
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("\n===%s:hw_init_completed==_FALSE===\n", __func__));
goto exit;
}
if ((check_fwstate(pmlmepriv, _FW_UNDER_SURVEY | _FW_UNDER_LINKING) == _TRUE) ||
(pmlmepriv->LinkDetectInfo.bBusyTraffic == _TRUE)) {
/* Scan or linking is in progress, do nothing. */
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("%s fail since fw_state = %x\n", __func__, get_fwstate(pmlmepriv)));
res = _TRUE;
- if (check_fwstate(pmlmepriv, (_FW_UNDER_SURVEY | _FW_UNDER_LINKING)) == _TRUE)
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("\n###_FW_UNDER_SURVEY | _FW_UNDER_LINKING\n\n"));
- else
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("\n###pmlmepriv->sitesurveyctrl.traffic_busy == _TRUE\n\n"));
+
} else {
if (rtw_is_scan_deny(padapter)) {
RTW_INFO(FUNC_ADPT_FMT": scan deny\n", FUNC_ADPT_ARG(padapter));
@@ -729,13 +670,12 @@ u8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, NDIS_802_11_SSID *pssid, i
_enter_critical_bh(&pmlmepriv->lock, &irqL);
- res = rtw_sitesurvey_cmd(padapter, pssid, ssid_max_num, NULL, 0, ch, ch_num);
+ res = rtw_sitesurvey_cmd(padapter, pparm);
_exit_critical_bh(&pmlmepriv->lock, &irqL);
}
exit:
- _func_exit_;
return res;
}
@@ -746,13 +686,10 @@ u8 rtw_set_802_11_authentication_mode(_adapter *padapter, NDIS_802_11_AUTHENTICA
int res;
u8 ret;
- _func_enter_;
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("set_802_11_auth.mode(): mode=%x\n", authmode));
psecuritypriv->ndisauthtype = authmode;
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("rtw_set_802_11_authentication_mode:psecuritypriv->ndisauthtype=%d", psecuritypriv->ndisauthtype));
if (psecuritypriv->ndisauthtype > 3)
psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
@@ -769,7 +706,6 @@ u8 rtw_set_802_11_authentication_mode(_adapter *padapter, NDIS_802_11_AUTHENTICA
else
ret = _FALSE;
- _func_exit_;
return ret;
}
@@ -783,14 +719,12 @@ u8 rtw_set_802_11_add_wep(_adapter *padapter, NDIS_802_11_WEP *wep)
struct security_priv *psecuritypriv = &(padapter->securitypriv);
u8 ret = _SUCCESS;
- _func_enter_;
bdefaultkey = (wep->KeyIndex & 0x40000000) > 0 ? _FALSE : _TRUE; /* for ??? */
btransmitkey = (wep->KeyIndex & 0x80000000) > 0 ? _TRUE : _FALSE; /* for ??? */
keyid = wep->KeyIndex & 0x3fffffff;
if (keyid >= 4) {
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("MgntActrtw_set_802_11_add_wep:keyid>4=>fail\n"));
ret = _FALSE;
goto exit;
}
@@ -798,19 +732,15 @@ u8 rtw_set_802_11_add_wep(_adapter *padapter, NDIS_802_11_WEP *wep)
switch (wep->KeyLength) {
case 5:
psecuritypriv->dot11PrivacyAlgrthm = _WEP40_;
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("MgntActrtw_set_802_11_add_wep:wep->KeyLength=5\n"));
break;
case 13:
psecuritypriv->dot11PrivacyAlgrthm = _WEP104_;
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("MgntActrtw_set_802_11_add_wep:wep->KeyLength=13\n"));
break;
default:
psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_;
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("MgntActrtw_set_802_11_add_wep:wep->KeyLength!=5 or 13\n"));
break;
}
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("rtw_set_802_11_add_wep:befor memcpy, wep->KeyLength=0x%x wep->KeyIndex=0x%x keyid =%x\n", wep->KeyLength, wep->KeyIndex, keyid));
_rtw_memcpy(&(psecuritypriv->dot11DefKey[keyid].skey[0]), &(wep->KeyMaterial), wep->KeyLength);
@@ -818,12 +748,6 @@ u8 rtw_set_802_11_add_wep(_adapter *padapter, NDIS_802_11_WEP *wep)
psecuritypriv->dot11PrivacyKeyIndex = keyid;
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("rtw_set_802_11_add_wep:security key material : %x %x %x %x %x %x %x %x %x %x %x %x %x\n",
- psecuritypriv->dot11DefKey[keyid].skey[0], psecuritypriv->dot11DefKey[keyid].skey[1], psecuritypriv->dot11DefKey[keyid].skey[2],
- psecuritypriv->dot11DefKey[keyid].skey[3], psecuritypriv->dot11DefKey[keyid].skey[4], psecuritypriv->dot11DefKey[keyid].skey[5],
- psecuritypriv->dot11DefKey[keyid].skey[6], psecuritypriv->dot11DefKey[keyid].skey[7], psecuritypriv->dot11DefKey[keyid].skey[8],
- psecuritypriv->dot11DefKey[keyid].skey[9], psecuritypriv->dot11DefKey[keyid].skey[10], psecuritypriv->dot11DefKey[keyid].skey[11],
- psecuritypriv->dot11DefKey[keyid].skey[12]));
res = rtw_set_key(padapter, psecuritypriv, keyid, 1, _TRUE);
@@ -831,457 +755,8 @@ u8 rtw_set_802_11_add_wep(_adapter *padapter, NDIS_802_11_WEP *wep)
ret = _FALSE;
exit:
- _func_exit_;
-
- return ret;
-
-}
-
-u8 rtw_set_802_11_remove_wep(_adapter *padapter, u32 keyindex)
-{
-
- u8 ret = _SUCCESS;
-
- _func_enter_;
-
- if (keyindex >= 0x80000000 || padapter == NULL) {
-
- ret = _FALSE;
- goto exit;
-
- } else {
- int res;
- struct security_priv *psecuritypriv = &(padapter->securitypriv);
- if (keyindex < 4) {
-
- _rtw_memset(&psecuritypriv->dot11DefKey[keyindex], 0, 16);
-
- res = rtw_set_key(padapter, psecuritypriv, keyindex, 0, _TRUE);
-
- psecuritypriv->dot11DefKeylen[keyindex] = 0;
-
- if (res == _FAIL)
- ret = _FAIL;
-
- } else
- ret = _FAIL;
-
- }
-
-exit:
-
- _func_exit_;
-
- return ret;
-
-}
-
-u8 rtw_set_802_11_add_key(_adapter *padapter, NDIS_802_11_KEY *key)
-{
-
- uint encryptionalgo;
- u8 *pbssid;
- struct sta_info *stainfo;
- u8 bgroup = _FALSE;
- u8 bgrouptkey = _FALSE;/* can be remove later */
- u8 ret = _SUCCESS;
-
- _func_enter_;
-
- if (((key->KeyIndex & 0x80000000) == 0) && ((key->KeyIndex & 0x40000000) > 0)) {
-
- /* It is invalid to clear bit 31 and set bit 30. If the miniport driver encounters this combination, */
- /* it must fail the request and return NDIS_STATUS_INVALID_DATA. */
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("rtw_set_802_11_add_key: ((key->KeyIndex & 0x80000000) == 0)[=%d] ", (int)(key->KeyIndex & 0x80000000) == 0));
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("rtw_set_802_11_add_key:((key->KeyIndex & 0x40000000) > 0)[=%d]" , (int)(key->KeyIndex & 0x40000000) > 0));
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("rtw_set_802_11_add_key: key->KeyIndex=%d\n" , (int)key->KeyIndex));
- ret = _FAIL;
- goto exit;
- }
-
- if (key->KeyIndex & 0x40000000) {
- /* Pairwise key */
-
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("OID_802_11_ADD_KEY: +++++ Pairwise key +++++\n"));
-
- pbssid = get_bssid(&padapter->mlmepriv);
- stainfo = rtw_get_stainfo(&padapter->stapriv, pbssid);
-
- if ((stainfo != NULL) && (padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)) {
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("OID_802_11_ADD_KEY:( stainfo!=NULL)&&(Adapter->securitypriv.dot11AuthAlgrthm==dot11AuthAlgrthm_8021X)\n"));
- encryptionalgo = stainfo->dot118021XPrivacy;
- } else {
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("OID_802_11_ADD_KEY: stainfo==NULL)||(Adapter->securitypriv.dot11AuthAlgrthm!=dot11AuthAlgrthm_8021X)\n"));
- encryptionalgo = padapter->securitypriv.dot11PrivacyAlgrthm;
- }
-
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("rtw_set_802_11_add_key: (encryptionalgo ==%d)!\n", encryptionalgo));
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("rtw_set_802_11_add_key: (Adapter->securitypriv.dot11PrivacyAlgrthm ==%d)!\n", padapter->securitypriv.dot11PrivacyAlgrthm));
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("rtw_set_802_11_add_key: (Adapter->securitypriv.dot11AuthAlgrthm ==%d)!\n", padapter->securitypriv.dot11AuthAlgrthm));
-
- if ((stainfo != NULL))
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("rtw_set_802_11_add_key: (stainfo->dot118021XPrivacy ==%d)!\n", stainfo->dot118021XPrivacy));
-
- if (key->KeyIndex & 0x000000FF) {
- /* The key index is specified in the lower 8 bits by values of zero to 255. */
- /* The key index should be set to zero for a Pairwise key, and the driver should fail with */
- /* NDIS_STATUS_INVALID_DATA if the lower 8 bits is not zero */
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, (" key->KeyIndex & 0x000000FF.\n"));
- ret = _FAIL;
- goto exit;
- }
-
- /* check BSSID */
- if (IS_MAC_ADDRESS_BROADCAST(key->BSSID) == _TRUE) {
-
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("MacAddr_isBcst(key->BSSID)\n"));
- ret = _FALSE;
- goto exit;
- }
-
- /* Check key length for TKIP. */
- /* if(encryptionAlgorithm == RT_ENC_TKIP_ENCRYPTION && key->KeyLength != 32) */
- if ((encryptionalgo == _TKIP_) && (key->KeyLength != 32)) {
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("TKIP KeyLength:0x%x != 32\n", key->KeyLength));
- ret = _FAIL;
- goto exit;
-
- }
-
- /* Check key length for AES. */
- if ((encryptionalgo == _AES_) && (key->KeyLength != 16)) {
- /* For our supplicant, EAPPkt9x.vxd, cannot differentiate TKIP and AES case. */
- if (key->KeyLength == 32)
- key->KeyLength = 16;
- else {
- ret = _FAIL;
- goto exit;
- }
- }
-
- /* Check key length for WEP. For NDTEST, 2005.01.27, by rcnjko. -> modify checking condition*/
- if (((encryptionalgo == _WEP40_) && (key->KeyLength != 5)) || ((encryptionalgo == _WEP104_) && (key->KeyLength != 13))) {
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("WEP KeyLength:0x%x != 5 or 13\n", key->KeyLength));
- ret = _FAIL;
- goto exit;
- }
-
- bgroup = _FALSE;
-
- /* Check the pairwise key. Added by Annie, 2005-07-06. */
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("------------------------------------------\n"));
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("[Pairwise Key set]\n"));
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("------------------------------------------\n"));
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("key index: 0x%8x(0x%8x)\n", key->KeyIndex, (key->KeyIndex & 0x3)));
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("key Length: %d\n", key->KeyLength));
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("------------------------------------------\n"));
-
- } else {
- /* Group key - KeyIndex(BIT30==0) */
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("OID_802_11_ADD_KEY: +++++ Group key +++++\n"));
-
-
- /* when add wep key through add key and didn't assigned encryption type before */
- if ((padapter->securitypriv.ndisauthtype <= 3) && (padapter->securitypriv.dot118021XGrpPrivacy == 0)) {
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("keylen=%d( Adapter->securitypriv.dot11PrivacyAlgrthm=%x )padapter->securitypriv.dot118021XGrpPrivacy(%x)\n",
- key->KeyLength, padapter->securitypriv.dot11PrivacyAlgrthm, padapter->securitypriv.dot118021XGrpPrivacy));
-
- switch (key->KeyLength) {
- case 5:
- padapter->securitypriv.dot11PrivacyAlgrthm = _WEP40_;
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("Adapter->securitypriv.dot11PrivacyAlgrthm= %x key->KeyLength=%u\n",
- padapter->securitypriv.dot11PrivacyAlgrthm, key->KeyLength));
- break;
- case 13:
- padapter->securitypriv.dot11PrivacyAlgrthm = _WEP104_;
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("Adapter->securitypriv.dot11PrivacyAlgrthm= %x key->KeyLength=%u\n",
- padapter->securitypriv.dot11PrivacyAlgrthm, key->KeyLength));
- break;
- default:
- padapter->securitypriv.dot11PrivacyAlgrthm = _NO_PRIVACY_;
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("Adapter->securitypriv.dot11PrivacyAlgrthm= %x key->KeyLength=%u\n",
- padapter->securitypriv.dot11PrivacyAlgrthm, key->KeyLength));
- break;
- }
-
- encryptionalgo = padapter->securitypriv.dot11PrivacyAlgrthm;
-
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, (" Adapter->securitypriv.dot11PrivacyAlgrthm=%x\n", padapter->securitypriv.dot11PrivacyAlgrthm));
-
- } else {
- encryptionalgo = padapter->securitypriv.dot118021XGrpPrivacy;
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_,
- ("( Adapter->securitypriv.dot11PrivacyAlgrthm=%x )encryptionalgo(%x)=padapter->securitypriv.dot118021XGrpPrivacy(%x)keylen=%d\n",
- padapter->securitypriv.dot11PrivacyAlgrthm, encryptionalgo, padapter->securitypriv.dot118021XGrpPrivacy, key->KeyLength));
-
- }
-
- if ((check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE) == _TRUE) && (IS_MAC_ADDRESS_BROADCAST(key->BSSID) == _FALSE)) {
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, (" IBSS but BSSID is not Broadcast Address.\n"));
- ret = _FAIL;
- goto exit;
- }
-
- /* Check key length for TKIP */
- if ((encryptionalgo == _TKIP_) && (key->KeyLength != 32)) {
-
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, (" TKIP GTK KeyLength:%u != 32\n", key->KeyLength));
- ret = _FAIL;
- goto exit;
-
- } else if (encryptionalgo == _AES_ && (key->KeyLength != 16 && key->KeyLength != 32)) {
-
- /* Check key length for AES */
- /* For NDTEST, we allow keylen=32 in this case. 2005.01.27, by rcnjko. */
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("<=== SetInfo, OID_802_11_ADD_KEY: AES GTK KeyLength:%u != 16 or 32\n", key->KeyLength));
- ret = _FAIL;
- goto exit;
- }
-
- /* Change the key length for EAPPkt9x.vxd. Added by Annie, 2005-11-03. */
- if ((encryptionalgo == _AES_) && (key->KeyLength == 32)) {
- key->KeyLength = 16;
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("AES key length changed: %u\n", key->KeyLength));
- }
-
- if (key->KeyIndex & 0x8000000) /* error ??? 0x8000_0000 */
- bgrouptkey = _TRUE;
-
- if ((check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE) == _TRUE) && (check_fwstate(&padapter->mlmepriv, _FW_LINKED) == _TRUE))
- bgrouptkey = _TRUE;
-
- bgroup = _TRUE;
-
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("------------------------------------------\n"));
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("[Group Key set]\n"));
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("------------------------------------------\n")) ;
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("key index: 0x%8x(0x%8x)\n", key->KeyIndex, (key->KeyIndex & 0x3)));
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("key Length: %d\n", key->KeyLength)) ;
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("------------------------------------------\n"));
-
- }
-
- /* If WEP encryption algorithm, just call rtw_set_802_11_add_wep(). */
- if ((padapter->securitypriv.dot11AuthAlgrthm != dot11AuthAlgrthm_8021X) && (encryptionalgo == _WEP40_ || encryptionalgo == _WEP104_)) {
- u8 ret;
- u32 keyindex;
- u32 len = FIELD_OFFSET(NDIS_802_11_KEY, KeyMaterial) + key->KeyLength;
- NDIS_802_11_WEP *wep = &padapter->securitypriv.ndiswep;
-
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("OID_802_11_ADD_KEY: +++++ WEP key +++++\n"));
-
- wep->Length = len;
- keyindex = key->KeyIndex & 0x7fffffff;
- wep->KeyIndex = keyindex ;
- wep->KeyLength = key->KeyLength;
-
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("OID_802_11_ADD_KEY:Before memcpy\n"));
-
- _rtw_memcpy(wep->KeyMaterial, key->KeyMaterial, key->KeyLength);
- _rtw_memcpy(&(padapter->securitypriv.dot11DefKey[keyindex].skey[0]), key->KeyMaterial, key->KeyLength);
-
- padapter->securitypriv.dot11DefKeylen[keyindex] = key->KeyLength;
- padapter->securitypriv.dot11PrivacyKeyIndex = keyindex;
-
- ret = rtw_set_802_11_add_wep(padapter, wep);
-
- goto exit;
-
- }
-
- if (key->KeyIndex & 0x20000000) {
- /* SetRSC */
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("OID_802_11_ADD_KEY: +++++ SetRSC+++++\n"));
- if (bgroup == _TRUE) {
- NDIS_802_11_KEY_RSC keysrc = key->KeyRSC & 0x00FFFFFFFFFFFFULL;
- _rtw_memcpy(&padapter->securitypriv.dot11Grprxpn, &keysrc, 8);
- } else {
- NDIS_802_11_KEY_RSC keysrc = key->KeyRSC & 0x00FFFFFFFFFFFFULL;
- _rtw_memcpy(&padapter->securitypriv.dot11Grptxpn, &keysrc, 8);
- }
-
- }
-
- /* Indicate this key idx is used for TX */
- /* Save the key in KeyMaterial */
- if (bgroup == _TRUE) { /* Group transmit key */
- int res;
-
- if (bgrouptkey == _TRUE)
- padapter->securitypriv.dot118021XGrpKeyid = (u8)key->KeyIndex;
-
- if ((key->KeyIndex & 0x3) == 0) {
- ret = _FAIL;
- goto exit;
- }
-
- _rtw_memset(&padapter->securitypriv.dot118021XGrpKey[(u8)((key->KeyIndex) & 0x03)], 0, 16);
- _rtw_memset(&padapter->securitypriv.dot118021XGrptxmickey[(u8)((key->KeyIndex) & 0x03)], 0, 16);
- _rtw_memset(&padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)], 0, 16);
-
- if ((key->KeyIndex & 0x10000000)) {
- _rtw_memcpy(&padapter->securitypriv.dot118021XGrptxmickey[(u8)((key->KeyIndex) & 0x03)], key->KeyMaterial + 16, 8);
- _rtw_memcpy(&padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)], key->KeyMaterial + 24, 8);
-
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("\n rtw_set_802_11_add_key:rx mic :0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x\n",
- padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[0],
- padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex - 1) & 0x03)].skey[1],
- padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[2],
- padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex - 1) & 0x03)].skey[3],
- padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[4],
- padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex - 1) & 0x03)].skey[5],
- padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[6],
- padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex - 1) & 0x03)].skey[7]));
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("\n rtw_set_802_11_add_key:set Group mic key!!!!!!!!\n"));
-
- } else {
- _rtw_memcpy(&padapter->securitypriv.dot118021XGrptxmickey[(u8)((key->KeyIndex) & 0x03)], key->KeyMaterial + 24, 8);
- _rtw_memcpy(&padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)], key->KeyMaterial + 16, 8);
-
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("\n rtw_set_802_11_add_key:rx mic :0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x\n",
- padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[0],
- padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex - 1) & 0x03)].skey[1],
- padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[2],
- padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex - 1) & 0x03)].skey[3],
- padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[4],
- padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex - 1) & 0x03)].skey[5],
- padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[6],
- padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex - 1) & 0x03)].skey[7]));
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("\n rtw_set_802_11_add_key:set Group mic key!!!!!!!!\n"));
-
- }
-
- /* set group key by index */
- _rtw_memcpy(&padapter->securitypriv.dot118021XGrpKey[(u8)((key->KeyIndex) & 0x03)], key->KeyMaterial, key->KeyLength);
-
- key->KeyIndex = key->KeyIndex & 0x03;
-
- padapter->securitypriv.binstallGrpkey = _TRUE;
-
- padapter->securitypriv.bcheck_grpkey = _FALSE;
-
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("reset group key"));
-
- res = rtw_set_key(padapter, &padapter->securitypriv, key->KeyIndex, 1, _TRUE);
-
- if (res == _FAIL)
- ret = _FAIL;
-
- goto exit;
-
- } else { /* Pairwise Key */
- u8 res;
-
- pbssid = get_bssid(&padapter->mlmepriv);
- stainfo = rtw_get_stainfo(&padapter->stapriv , pbssid);
-
- if (stainfo != NULL) {
- _rtw_memset(&stainfo->dot118021x_UncstKey, 0, 16); /* clear keybuffer */
-
- _rtw_memcpy(&stainfo->dot118021x_UncstKey, key->KeyMaterial, 16);
-
- if (encryptionalgo == _TKIP_) {
- padapter->securitypriv.busetkipkey = _FALSE;
-
- /* _set_timer(&padapter->securitypriv.tkip_timer, 50); */
-
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("\n ==========_set_timer\n"));
-
- /* if TKIP, save the Receive/Transmit MIC key in KeyMaterial[128-255] */
- if ((key->KeyIndex & 0x10000000)) {
- _rtw_memcpy(&stainfo->dot11tkiptxmickey, key->KeyMaterial + 16, 8);
- _rtw_memcpy(&stainfo->dot11tkiprxmickey, key->KeyMaterial + 24, 8);
-
- } else {
- _rtw_memcpy(&stainfo->dot11tkiptxmickey, key->KeyMaterial + 24, 8);
- _rtw_memcpy(&stainfo->dot11tkiprxmickey, key->KeyMaterial + 16, 8);
-
- }
-
- } else if (encryptionalgo == _AES_) {
-
- }
-
-
- /* Set key to CAM through H2C command */
-#if 0
- if (bgrouptkey) { /* never go to here */
- res = rtw_setstakey_cmd(padapter, stainfo, GROUP_KEY, _TRUE);
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("\n rtw_set_802_11_add_key:rtw_setstakey_cmd(group)\n"));
- } else {
- res = rtw_setstakey_cmd(padapter, stainfo, UNICAST_KEY, _TRUE);
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("\n rtw_set_802_11_add_key:rtw_setstakey_cmd(unicast)\n"));
- }
-#else
-
- res = rtw_setstakey_cmd(padapter, stainfo, UNICAST_KEY, _TRUE);
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("\n rtw_set_802_11_add_key:rtw_setstakey_cmd(unicast)\n"));
-#endif
-
- if (res == _FALSE)
- ret = _FAIL;
-
- }
-
- }
-
-exit:
-
- _func_exit_;
return ret;
-}
-
-u8 rtw_set_802_11_remove_key(_adapter *padapter, NDIS_802_11_REMOVE_KEY *key)
-{
-
- uint encryptionalgo;
- u8 *pbssid;
- struct sta_info *stainfo;
- u8 bgroup = (key->KeyIndex & 0x4000000) > 0 ? _FALSE : _TRUE;
- u8 keyIndex = (u8)key->KeyIndex & 0x03;
- u8 ret = _SUCCESS;
-
- _func_enter_;
-
- if ((key->KeyIndex & 0xbffffffc) > 0) {
- ret = _FAIL;
- goto exit;
- }
-
- if (bgroup == _TRUE) {
- encryptionalgo = padapter->securitypriv.dot118021XGrpPrivacy;
- /* clear group key by index */
- /* NdisZeroMemory(Adapter->MgntInfo.SecurityInfo.KeyBuf[keyIndex], MAX_WEP_KEY_LEN); */
- /* Adapter->MgntInfo.SecurityInfo.KeyLen[keyIndex] = 0; */
-
- _rtw_memset(&padapter->securitypriv.dot118021XGrpKey[keyIndex], 0, 16);
-
- /* ! \todo Send a H2C Command to Firmware for removing this Key in CAM Entry. */
-
- } else {
-
- pbssid = get_bssid(&padapter->mlmepriv);
- stainfo = rtw_get_stainfo(&padapter->stapriv , pbssid);
- if (stainfo != NULL) {
- encryptionalgo = stainfo->dot118021XPrivacy;
-
- /* clear key by BSSID */
- _rtw_memset(&stainfo->dot118021x_UncstKey, 0, 16);
-
- /* ! \todo Send a H2C Command to Firmware for disable this Key in CAM Entry. */
-
- } else {
- ret = _FAIL;
- goto exit;
- }
- }
-
-exit:
-
- _func_exit_;
-
- return _TRUE;
}
@@ -1318,22 +793,20 @@ u16 rtw_get_cur_max_rate(_adapter *adapter)
if (psta == NULL)
return 0;
- short_GI = query_ra_short_GI(psta);
+ short_GI = query_ra_short_GI(psta, rtw_get_tx_bw_mode(adapter, psta));
#ifdef CONFIG_80211N_HT
- if (IsSupportedHT(psta->wireless_mode)) {
+ if (is_supported_ht(psta->wireless_mode)) {
rtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
-
- max_rate = rtw_mcs_rate(
- rf_type,
- ((psta->bw_mode == CHANNEL_WIDTH_40) ? 1 : 0),
- short_GI,
- psta->htpriv.ht_cap.supp_mcs_set
- );
+ max_rate = rtw_mcs_rate(rf_type
+ , (psta->cmn.bw_mode == CHANNEL_WIDTH_40) ? 1 : 0
+ , short_GI
+ , psta->htpriv.ht_cap.supp_mcs_set
+ );
}
#ifdef CONFIG_80211AC_VHT
- else if (IsSupportedVHT(psta->wireless_mode))
- max_rate = ((rtw_vht_mcs_to_data_rate(psta->bw_mode, short_GI, pmlmepriv->vhtpriv.vht_highest_rate) + 1) >> 1) * 10;
+ else if (is_supported_vht(psta->wireless_mode))
+ max_rate = ((rtw_vht_mcs_to_data_rate(psta->cmn.bw_mode, short_GI, pmlmepriv->vhtpriv.vht_highest_rate) + 1) >> 1) * 10;
#endif /* CONFIG_80211AC_VHT */
else
#endif /* CONFIG_80211N_HT */
@@ -1396,7 +869,8 @@ int rtw_set_country(_adapter *adapter, const char *country_code)
#ifdef CONFIG_RTW_IOCTL_SET_COUNTRY
return rtw_set_country_cmd(adapter, RTW_CMDF_WAIT_ACK, country_code, 1);
#else
- return _FAIL;
+ RTW_INFO("%s(): not applied\n", __func__);
+ return _SUCCESS;
#endif
}
diff --git a/core/rtw_iol.c b/core/rtw_iol.c
index 42d0b6b..aafac3f 100644
--- a/core/rtw_iol.c
+++ b/core/rtw_iol.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,12 +11,7 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#include
diff --git a/core/rtw_mem.c b/core/rtw_mem.c
index d82fa7f..d9f5652 100644
--- a/core/rtw_mem.c
+++ b/core/rtw_mem.c
@@ -1,31 +1,49 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
#include
#include
MODULE_LICENSE("GPL");
-MODULE_DESCRIPTION("Realtek Wireless Lan Driver 802.11 AC");
-MODULE_AUTHOR("Brandon Bailey ");
+MODULE_DESCRIPTION("Realtek Wireless Lan Driver");
+MODULE_AUTHOR("Realtek Semiconductor Corp.");
MODULE_VERSION("DRIVERVERSION");
struct sk_buff_head rtk_skb_mem_q;
struct u8 *rtk_buf_mem[NR_RECVBUFF];
-struct u8 *rtw_get_buf_premem(int index) {
+struct u8 *rtw_get_buf_premem(int index)
+{
printk("%s, rtk_buf_mem index : %d\n", __func__, index);
return rtk_buf_mem[index];
}
-u16 rtw_rtkm_get_buff_size(void) {
+u16 rtw_rtkm_get_buff_size(void)
+{
return MAX_RTKM_RECVBUF_SZ;
}
EXPORT_SYMBOL(rtw_rtkm_get_buff_size);
-u8 rtw_rtkm_get_nr_recv_skb(void) {
+u8 rtw_rtkm_get_nr_recv_skb(void)
+{
return MAX_RTKM_NR_PREALLOC_RECV_SKB;
}
EXPORT_SYMBOL(rtw_rtkm_get_nr_recv_skb);
-struct sk_buff *rtw_alloc_skb_premem(u16 in_size) {
+struct sk_buff *rtw_alloc_skb_premem(u16 in_size)
+{
struct sk_buff *skb = NULL;
if (in_size > MAX_RTKM_RECVBUF_SZ) {
@@ -42,7 +60,8 @@ struct sk_buff *rtw_alloc_skb_premem(u16 in_size) {
}
EXPORT_SYMBOL(rtw_alloc_skb_premem);
-int rtw_free_skb_premem(struct sk_buff *pskb) {
+int rtw_free_skb_premem(struct sk_buff *pskb)
+{
if (!pskb)
return -1;
@@ -57,7 +76,8 @@ int rtw_free_skb_premem(struct sk_buff *pskb) {
}
EXPORT_SYMBOL(rtw_free_skb_premem);
-static int __init rtw_mem_init(void) {
+static int __init rtw_mem_init(void)
+{
int i;
SIZE_PTR tmpaddr = 0;
SIZE_PTR alignment = 0;
@@ -94,7 +114,8 @@ static int __init rtw_mem_init(void) {
}
-static void __exit rtw_mem_exit(void) {
+static void __exit rtw_mem_exit(void)
+{
if (skb_queue_len(&rtk_skb_mem_q))
printk("%s, rtk_skb_mem_q len : %d\n", __func__, skb_queue_len(&rtk_skb_mem_q));
diff --git a/core/rtw_mi.c b/core/rtw_mi.c
index 2532848..bef596b 100644
--- a/core/rtw_mi.c
+++ b/core/rtw_mi.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2015 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,12 +11,7 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#define _RTW_MI_C_
#include
@@ -32,6 +27,82 @@ void rtw_mi_update_union_chan_inf(_adapter *adapter, u8 ch, u8 offset , u8 bw)
iface_state->union_offset = offset;
}
+#ifdef CONFIG_P2P
+static u8 _rtw_mi_p2p_listen_scan_chk(_adapter *adapter)
+{
+ int i;
+ _adapter *iface;
+ struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+ u8 p2p_listen_scan_state = _FALSE;
+
+ for (i = 0; i < dvobj->iface_nums; i++) {
+ iface = dvobj->padapters[i];
+ if (rtw_p2p_chk_state(&iface->wdinfo, P2P_STATE_LISTEN) ||
+ rtw_p2p_chk_state(&iface->wdinfo, P2P_STATE_SCAN)) {
+ p2p_listen_scan_state = _TRUE;
+ break;
+ }
+ }
+ return p2p_listen_scan_state;
+}
+#endif
+u8 rtw_mi_stayin_union_ch_chk(_adapter *adapter)
+{
+ u8 rst = _TRUE;
+ u8 u_ch, u_bw, u_offset;
+ u8 o_ch, o_bw, o_offset;
+
+ u_ch = rtw_mi_get_union_chan(adapter);
+ u_bw = rtw_mi_get_union_bw(adapter);
+ u_offset = rtw_mi_get_union_offset(adapter);
+
+ o_ch = rtw_get_oper_ch(adapter);
+ o_bw = rtw_get_oper_bw(adapter);
+ o_offset = rtw_get_oper_choffset(adapter);
+
+ if ((u_ch != o_ch) || (u_bw != o_bw) || (u_offset != o_offset))
+ rst = _FALSE;
+
+ #ifdef DBG_IFACE_STATUS
+ if (rst == _FALSE) {
+ RTW_ERR("%s Not stay in union channel\n", __func__);
+ if (GET_HAL_DATA(adapter)->bScanInProcess == _TRUE)
+ RTW_ERR("ScanInProcess\n");
+ #ifdef CONFIG_P2P
+ if (_rtw_mi_p2p_listen_scan_chk(adapter))
+ RTW_ERR("P2P in listen or scan state\n");
+ #endif
+ RTW_ERR("union ch, bw, offset: %u,%u,%u\n", u_ch, u_bw, u_offset);
+ RTW_ERR("oper ch, bw, offset: %u,%u,%u\n", o_ch, o_bw, o_offset);
+ RTW_ERR("=========================\n");
+ }
+ #endif
+ return rst;
+}
+
+u8 rtw_mi_stayin_union_band_chk(_adapter *adapter)
+{
+ u8 rst = _TRUE;
+ u8 u_ch, o_ch;
+ u8 u_band, o_band;
+
+ u_ch = rtw_mi_get_union_chan(adapter);
+ o_ch = rtw_get_oper_ch(adapter);
+ u_band = (u_ch > 14) ? BAND_ON_5G : BAND_ON_2_4G;
+ o_band = (o_ch > 14) ? BAND_ON_5G : BAND_ON_2_4G;
+
+ if (u_ch != o_ch)
+ if(u_band != o_band)
+ rst = _FALSE;
+
+ #ifdef DBG_IFACE_STATUS
+ if (rst == _FALSE)
+ RTW_ERR("%s Not stay in union band\n", __func__);
+ #endif
+
+ return rst;
+}
+
/* Find union about ch, bw, ch_offset of all linked/linking interfaces */
int _rtw_mi_get_ch_setting_union(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset, bool include_self)
{
@@ -110,106 +181,170 @@ inline int rtw_mi_get_ch_setting_union_no_self(_adapter *adapter, u8 *ch, u8 *bw
return _rtw_mi_get_ch_setting_union(adapter, ch, bw, offset, 0);
}
-void _rtw_mi_status(_adapter *adapter, u8 *sta_num, u8 *ld_sta_num, u8 *lg_sta_num
- , u8 *ap_num, u8 *ld_ap_num, u8 *uw_num, bool include_self)
+#define MI_STATUS_SELF_ONLY 0
+#define MI_STATUS_OTHERS_ONLY 1
+#define MI_STATUS_ALL 2
+
+/* For now, not return union_ch/bw/offset */
+void _rtw_mi_status(_adapter *adapter, struct mi_state *mstate, u8 target_sel)
{
struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
_adapter *iface;
- struct mlme_ext_priv *mlmeext;
-
int i;
- u8 sta_num_ret = 0;
- u8 ld_sta_num_ret = 0;
- u8 lg_sta_num_ret = 0;
- u8 ap_num_ret = 0;
- u8 ld_ap_num_ret = 0;
- u8 uw_num_ret = 0;
-
- if (sta_num)
- *sta_num = 0;
- if (ld_sta_num)
- *ld_sta_num = 0;
- if (lg_sta_num)
- *lg_sta_num = 0;
- if (ap_num)
- *ap_num = 0;
- if (ld_ap_num)
- *ld_ap_num = 0;
- if (uw_num)
- *uw_num = 0;
+
+ _rtw_memset(mstate, 0, sizeof(struct mi_state));
for (i = 0; i < dvobj->iface_nums; i++) {
iface = dvobj->padapters[i];
- if (include_self == _FALSE && iface == adapter)
+ if (target_sel == MI_STATUS_SELF_ONLY && iface != adapter)
+ continue;
+ if (target_sel == MI_STATUS_OTHERS_ONLY && iface == adapter)
continue;
- /*mlmeext = &iface->mlmeextpriv;
-
- if (mlmeext_msr(mlmeext) == WIFI_FW_STATION_STATE) {*/
- if (check_fwstate(&iface->mlmepriv, WIFI_STATION_STATE)) {
- sta_num_ret++;
- if (check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE)
- ld_sta_num_ret++;
+ if (check_fwstate(&iface->mlmepriv, WIFI_STATION_STATE) == _TRUE) {
+ MSTATE_STA_NUM(mstate)++;
+ if (check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE) {
+ MSTATE_STA_LD_NUM(mstate)++;
+
+ #ifdef CONFIG_TDLS
+ if (iface->tdlsinfo.link_established == _TRUE)
+ MSTATE_TDLS_LD_NUM(mstate)++;
+ #endif
+ }
if (check_fwstate(&iface->mlmepriv, _FW_UNDER_LINKING) == _TRUE)
- lg_sta_num_ret++;
- }
+ MSTATE_STA_LG_NUM(mstate)++;
+
+#ifdef CONFIG_AP_MODE
+ } else if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) == _TRUE ) {
+ if (check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE) {
+ MSTATE_AP_NUM(mstate)++;
+ if (iface->stapriv.asoc_sta_count > 2)
+ MSTATE_AP_LD_NUM(mstate)++;
+ } else
+ MSTATE_AP_STARTING_NUM(mstate)++;
+#endif
- /*if (mlmeext_msr(mlmeext) == WIFI_FW_AP_STATE*/
- if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE)
- && check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE
- ) {
- ap_num_ret++;
+ } else if (check_fwstate(&iface->mlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) == _TRUE
+ && check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE
+ ) {
+ MSTATE_ADHOC_NUM(mstate)++;
if (iface->stapriv.asoc_sta_count > 2)
- ld_ap_num_ret++;
+ MSTATE_ADHOC_LD_NUM(mstate)++;
+
+#ifdef CONFIG_RTW_MESH
+ } else if (check_fwstate(&iface->mlmepriv, WIFI_MESH_STATE) == _TRUE
+ && check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE
+ ) {
+ MSTATE_MESH_NUM(mstate)++;
+ if (iface->stapriv.asoc_sta_count > 2)
+ MSTATE_MESH_LD_NUM(mstate)++;
+#endif
+
}
if (check_fwstate(&iface->mlmepriv, WIFI_UNDER_WPS) == _TRUE)
- uw_num_ret++;
+ MSTATE_WPS_NUM(mstate)++;
+
+ if (check_fwstate(&iface->mlmepriv, WIFI_SITE_MONITOR) == _TRUE) {
+ MSTATE_SCAN_NUM(mstate)++;
+
+ if (mlmeext_scan_state(&iface->mlmeextpriv) != SCAN_DISABLE
+ && mlmeext_scan_state(&iface->mlmeextpriv) != SCAN_BACK_OP)
+ MSTATE_SCAN_ENTER_NUM(mstate)++;
+ }
+
+#ifdef CONFIG_IOCTL_CFG80211
+ if (rtw_cfg80211_get_is_mgmt_tx(iface))
+ MSTATE_MGMT_TX_NUM(mstate)++;
+ #ifdef CONFIG_P2P
+ if (rtw_cfg80211_get_is_roch(iface) == _TRUE)
+ MSTATE_ROCH_NUM(mstate)++;
+ #endif
+#endif /* CONFIG_IOCTL_CFG80211 */
}
+}
+
+inline void rtw_mi_status(_adapter *adapter, struct mi_state *mstate)
+{
+ return _rtw_mi_status(adapter, mstate, MI_STATUS_ALL);
+}
- if (sta_num)
- *sta_num = sta_num_ret;
- if (ld_sta_num)
- *ld_sta_num = ld_sta_num_ret;
- if (lg_sta_num)
- *lg_sta_num = lg_sta_num_ret;
- if (ap_num)
- *ap_num = ap_num_ret;
- if (ld_ap_num)
- *ld_ap_num = ld_ap_num_ret;
- if (uw_num)
- *uw_num = uw_num_ret;
+inline void rtw_mi_status_no_self(_adapter *adapter, struct mi_state *mstate)
+{
+ return _rtw_mi_status(adapter, mstate, MI_STATUS_OTHERS_ONLY);
}
-inline void rtw_mi_status(_adapter *adapter, u8 *sta_num, u8 *ld_sta_num, u8 *lg_sta_num
- , u8 *ap_num, u8 *ld_ap_num, u8 *uw_num)
+inline void rtw_mi_status_no_others(_adapter *adapter, struct mi_state *mstate)
{
- return _rtw_mi_status(adapter, sta_num, ld_sta_num, lg_sta_num, ap_num, ld_ap_num, uw_num, 1);
+ return _rtw_mi_status(adapter, mstate, MI_STATUS_SELF_ONLY);
}
-inline void rtw_mi_status_no_self(_adapter *adapter, u8 *sta_num, u8 *ld_sta_num, u8 *lg_sta_num
- , u8 *ap_num, u8 *ld_ap_num, u8 *uw_num)
+
+/* For now, not handle union_ch/bw/offset */
+inline void rtw_mi_status_merge(struct mi_state *d, struct mi_state *a)
{
- return _rtw_mi_status(adapter, sta_num, ld_sta_num, lg_sta_num, ap_num, ld_ap_num, uw_num, 0);
+ d->sta_num += a->sta_num;
+ d->ld_sta_num += a->ld_sta_num;
+ d->lg_sta_num += a->lg_sta_num;
+#ifdef CONFIG_TDLS
+ d->ld_tdls_num += a->ld_tdls_num;
+#endif
+#ifdef CONFIG_AP_MODE
+ d->ap_num += a->ap_num;
+ d->ld_ap_num += a->ld_ap_num;
+#endif
+ d->adhoc_num += a->adhoc_num;
+ d->ld_adhoc_num += a->ld_adhoc_num;
+#ifdef CONFIG_RTW_MESH
+ d->mesh_num += a->mesh_num;
+ d->ld_mesh_num += a->ld_mesh_num;
+#endif
+ d->scan_num += a->scan_num;
+ d->scan_enter_num += a->scan_enter_num;
+ d->uwps_num += a->uwps_num;
+#ifdef CONFIG_IOCTL_CFG80211
+ #ifdef CONFIG_P2P
+ d->roch_num += a->roch_num;
+ #endif
+ d->mgmt_tx_num += a->mgmt_tx_num;
+#endif
}
+
void dump_mi_status(void *sel, struct dvobj_priv *dvobj)
{
RTW_PRINT_SEL(sel, "== dvobj-iface_state ==\n");
- RTW_PRINT_SEL(sel, "sta_num:%d\n", dvobj->iface_state.sta_num);
- RTW_PRINT_SEL(sel, "linking_sta_num:%d\n", dvobj->iface_state.lg_sta_num);
- RTW_PRINT_SEL(sel, "linked_sta_num:%d\n", dvobj->iface_state.ld_sta_num);
- RTW_PRINT_SEL(sel, "ap_num:%d\n", dvobj->iface_state.ap_num);
- RTW_PRINT_SEL(sel, "linked_ap_num:%d\n", dvobj->iface_state.ld_ap_num);
- RTW_PRINT_SEL(sel, "adhoc_num:%d\n", dvobj->iface_state.adhoc_num);
- RTW_PRINT_SEL(sel, "linked_adhoc_num:%d\n", dvobj->iface_state.ld_adhoc_num);
+ RTW_PRINT_SEL(sel, "sta_num:%d\n", DEV_STA_NUM(dvobj));
+ RTW_PRINT_SEL(sel, "linking_sta_num:%d\n", DEV_STA_LG_NUM(dvobj));
+ RTW_PRINT_SEL(sel, "linked_sta_num:%d\n", DEV_STA_LD_NUM(dvobj));
+#ifdef CONFIG_TDLS
+ RTW_PRINT_SEL(sel, "linked_tdls_num:%d\n", DEV_TDLS_LD_NUM(dvobj));
+#endif
+#ifdef CONFIG_AP_MODE
+ RTW_PRINT_SEL(sel, "ap_num:%d\n", DEV_AP_NUM(dvobj));
+ RTW_PRINT_SEL(sel, "starting_ap_num:%d\n", DEV_AP_STARTING_NUM(dvobj));
+ RTW_PRINT_SEL(sel, "linked_ap_num:%d\n", DEV_AP_LD_NUM(dvobj));
+#endif
+ RTW_PRINT_SEL(sel, "adhoc_num:%d\n", DEV_ADHOC_NUM(dvobj));
+ RTW_PRINT_SEL(sel, "linked_adhoc_num:%d\n", DEV_ADHOC_LD_NUM(dvobj));
+#ifdef CONFIG_RTW_MESH
+ RTW_PRINT_SEL(sel, "mesh_num:%d\n", DEV_MESH_NUM(dvobj));
+ RTW_PRINT_SEL(sel, "linked_mesh_num:%d\n", DEV_MESH_LD_NUM(dvobj));
+#endif
#ifdef CONFIG_P2P
- RTW_PRINT_SEL(sel, "p2p_device_num:%d\n", rtw_mi_stay_in_p2p_mode(dvobj->padapters[IFACE_ID0]));
+ RTW_PRINT_SEL(sel, "p2p_device_num:%d\n", rtw_mi_stay_in_p2p_mode(dvobj_get_primary_adapter(dvobj)));
+#endif
+ RTW_PRINT_SEL(sel, "scan_num:%d\n", DEV_SCAN_NUM(dvobj));
+ RTW_PRINT_SEL(sel, "under_wps_num:%d\n", DEV_WPS_NUM(dvobj));
+#if defined(CONFIG_IOCTL_CFG80211)
+ #if defined(CONFIG_P2P)
+ RTW_PRINT_SEL(sel, "roch_num:%d\n", DEV_ROCH_NUM(dvobj));
+ #endif
+ RTW_PRINT_SEL(sel, "mgmt_tx_num:%d\n", DEV_MGMT_TX_NUM(dvobj));
#endif
- RTW_PRINT_SEL(sel, "under_wps_num:%d\n", dvobj->iface_state.uwps_num);
- RTW_PRINT_SEL(sel, "union_ch:%d\n", dvobj->iface_state.union_ch);
- RTW_PRINT_SEL(sel, "union_bw:%d\n", dvobj->iface_state.union_bw);
- RTW_PRINT_SEL(sel, "union_offset:%d\n", dvobj->iface_state.union_offset);
+ RTW_PRINT_SEL(sel, "union_ch:%d\n", DEV_U_CH(dvobj));
+ RTW_PRINT_SEL(sel, "union_bw:%d\n", DEV_U_BW(dvobj));
+ RTW_PRINT_SEL(sel, "union_offset:%d\n", DEV_U_OFFSET(dvobj));
RTW_PRINT_SEL(sel, "================\n\n");
}
@@ -224,51 +359,21 @@ inline void rtw_mi_update_iface_status(struct mlme_priv *pmlmepriv, sint state)
_adapter *adapter = container_of(pmlmepriv, _adapter, mlmepriv);
struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
struct mi_state *iface_state = &dvobj->iface_state;
+ struct mi_state tmp_mstate;
u8 i;
u8 u_ch, u_offset, u_bw;
_adapter *iface;
- struct mlme_ext_priv *mlmeext;
- if ((state == WIFI_MONITOR_STATE) || /* (state == WIFI_OP_CH_SWITCHING) || */
- (state == WIFI_ADHOC_MASTER_STATE) || (state == WIFI_ADHOC_STATE) ||
- (state == WIFI_SITE_MONITOR) || (state == 0xFFFFFFFF) ||
- (state == WIFI_UNDER_WPS)
- )
+ if (state == WIFI_MONITOR_STATE
+ || state == 0xFFFFFFFF
+ )
return;
if (0)
RTW_INFO("%s => will change or clean state to 0x%08x\n", __func__, state);
- _rtw_memset(iface_state, 0, sizeof(struct mi_state));
- for (i = 0; i < dvobj->iface_nums; i++) {
- iface = dvobj->padapters[i];
- mlmeext = &iface->mlmeextpriv;
-
- if (check_fwstate(&iface->mlmepriv, WIFI_STATION_STATE) == _TRUE) {
- iface_state->sta_num++;
- if (check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE)
- iface_state->ld_sta_num++;
-
- if (check_fwstate(&iface->mlmepriv, _FW_UNDER_LINKING) == _TRUE)
- iface_state->lg_sta_num++;
- } else if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) == _TRUE
- && check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE
- ) {
- iface_state->ap_num++;
- if (iface->stapriv.asoc_sta_count > 2)
- iface_state->ld_ap_num++;
- } else if (check_fwstate(&iface->mlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) == _TRUE
- && check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE
- ) {
- iface_state->adhoc_num++;
- if (iface->stapriv.asoc_sta_count > 2)
- iface_state->ld_adhoc_num++;
- }
-
- if (check_fwstate(&iface->mlmepriv, WIFI_UNDER_WPS) == _TRUE)
- iface_state->uwps_num++;
-
- }
+ rtw_mi_status(adapter, &tmp_mstate);
+ _rtw_memcpy(iface_state, &tmp_mstate, sizeof(struct mi_state));
if (rtw_mi_get_ch_setting_union(adapter, &u_ch, &u_bw, &u_offset))
rtw_mi_update_union_chan_inf(adapter , u_ch, u_offset , u_bw);
@@ -297,46 +402,57 @@ u8 rtw_mi_check_status(_adapter *adapter, u8 type)
switch (type) {
case MI_LINKED:
- if (iface_state->ld_sta_num || iface_state->ap_num || iface_state->adhoc_num) /*check_fwstate(&iface->mlmepriv, _FW_LINKED)*/
+ if (MSTATE_STA_LD_NUM(iface_state) || MSTATE_AP_NUM(iface_state) || MSTATE_ADHOC_NUM(iface_state) || MSTATE_MESH_NUM(iface_state)) /*check_fwstate(&iface->mlmepriv, _FW_LINKED)*/
ret = _TRUE;
break;
case MI_ASSOC:
- if (iface_state->ld_sta_num || iface_state->ld_ap_num || iface_state->ld_adhoc_num)
+ if (MSTATE_STA_LD_NUM(iface_state) || MSTATE_AP_LD_NUM(iface_state) || MSTATE_ADHOC_LD_NUM(iface_state) || MSTATE_MESH_LD_NUM(iface_state))
ret = _TRUE;
break;
case MI_UNDER_WPS:
- if (iface_state->uwps_num)
+ if (MSTATE_WPS_NUM(iface_state))
ret = _TRUE;
break;
case MI_AP_MODE:
- if (iface_state->ap_num)
+ if (MSTATE_AP_NUM(iface_state))
ret = _TRUE;
break;
case MI_AP_ASSOC:
- if (iface_state->ld_ap_num)
+ if (MSTATE_AP_LD_NUM(iface_state))
ret = _TRUE;
break;
case MI_ADHOC:
- if (iface_state->adhoc_num)
+ if (MSTATE_ADHOC_NUM(iface_state))
ret = _TRUE;
break;
case MI_ADHOC_ASSOC:
- if (iface_state->ld_adhoc_num)
+ if (MSTATE_ADHOC_LD_NUM(iface_state))
+ ret = _TRUE;
+ break;
+
+#ifdef CONFIG_RTW_MESH
+ case MI_MESH:
+ if (MSTATE_MESH_NUM(iface_state))
ret = _TRUE;
break;
+ case MI_MESH_ASSOC:
+ if (MSTATE_MESH_LD_NUM(iface_state))
+ ret = _TRUE;
+ break;
+#endif
case MI_STA_NOLINK: /* this is misleading, but not used now */
- if (iface_state->sta_num && (!(iface_state->ld_sta_num || iface_state->lg_sta_num)))
+ if (MSTATE_STA_NUM(iface_state) && (!(MSTATE_STA_LD_NUM(iface_state) || MSTATE_STA_LG_NUM(iface_state))))
ret = _TRUE;
break;
case MI_STA_LINKED:
- if (iface_state->ld_sta_num)
+ if (MSTATE_STA_LD_NUM(iface_state))
ret = _TRUE;
break;
case MI_STA_LINKING:
- if (iface_state->lg_sta_num)
+ if (MSTATE_STA_LG_NUM(iface_state))
ret = _TRUE;
break;
@@ -346,170 +462,35 @@ u8 rtw_mi_check_status(_adapter *adapter, u8 type)
return ret;
}
-#if 0
-inline void rtw_mi_update_fwstate(struct mlme_priv *pmlmepriv, sint state, u8 bset)
-{
- _adapter *adapter = container_of(pmlmepriv, _adapter, mlmepriv);
-
- struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
- struct mi_state *iface_state = &dvobj->iface_state;
- struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
-
- if (!(state & (_FW_LINKED | _FW_UNDER_LINKING | WIFI_UNDER_WPS)))
- return;
-
- if (mlmeext_msr(mlmeext) == WIFI_FW_STATION_STATE) {
- /*ATOMIC_INC(&(iface_state->sta_num_ret));*/
-
- if (state & _FW_LINKED)
- (bset) ? ATOMIC_INC(&(iface_state->ld_sta_num_ret))
- : ATOMIC_DEC(&(iface_state->ld_sta_num_ret));
-
- if (state & _FW_UNDER_LINKING)
- (bset) ? ATOMIC_INC(&(iface_state->lg_sta_num_ret))
- : ATOMIC_DEC(&(iface_state->lg_sta_num_ret));
- }
-
- if (mlmeext_msr(mlmeext) == WIFI_FW_AP_STATE
- && check_fwstate(&adapter->mlmepriv, _FW_LINKED) == _TRUE
- ) {
- /*ATOMIC_INC(&(iface_state->ap_num_ret));*/
- if (adapter->stapriv.asoc_sta_count > 2)
- ld_ap_num_ret++;
- }
-
- if (state & WIFI_UNDER_WPS)
- (bset) ? ATOMIC_INC(&(iface_state->uw_num_ret))
- : ATOMIC_DEC(&(iface_state->uw_num_ret));
-
- _rtw_mi_status(adapter, &iface_state->sta_num, &iface_state->ld_sta_num, &iface_state->lg_sta_num
- , &iface_state->ap_num, &iface_state->ld_ap_num, &iface_state->uwps_num, 1);
-}
-#endif
-
-#ifdef CONFIG_MP_INCLUDED
-u8 rtw_mi_mp_mode_check(_adapter *padapter)
+/*
+* return value : 0 is failed or have not interface meet condition
+* return value : !0 is success or interface numbers which meet condition
+* return value of ops_func must be _TRUE or _FALSE
+*/
+static u8 _rtw_mi_process(_adapter *padapter, bool exclude_self,
+ void *data, u8(*ops_func)(_adapter *padapter, void *data))
{
-#ifdef CONFIG_CONCURRENT_MODE
int i;
+ _adapter *iface;
struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
- _adapter *iface = NULL;
-
- for (i = 0; i < dvobj->iface_nums; i++) {
- iface = dvobj->padapters[i];
- if ((iface) && (iface->registrypriv.mp_mode == 1)) {
- RTW_INFO(ADPT_FMT "-MP mode enable\n", ADPT_ARG(iface));
- return _TRUE;
- }
- }
-#else
- if (padapter->registrypriv.mp_mode == 1)
- return _TRUE;
-#endif
- return _FALSE;
-}
-#endif
-
-#ifdef CONFIG_CONCURRENT_MODE
-u8 rtw_mi_buddy_under_survey(_adapter *padapter)
-{
- int i;
u8 ret = 0;
- _adapter *iface = NULL;
- _irqL irqL;
- struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
-
-#ifdef CONFIG_IOCTL_CFG80211
- struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
-#endif
-
- struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-
- struct mlme_priv *buddy_mlmepriv;
- struct rtw_wdev_priv *buddy_wdev_priv;
for (i = 0; i < dvobj->iface_nums; i++) {
iface = dvobj->padapters[i];
if ((iface) && rtw_is_adapter_up(iface)) {
- if (iface == padapter)
+ if ((exclude_self) && (iface == padapter))
continue;
- buddy_mlmepriv = &iface->mlmepriv;
- if (check_fwstate(buddy_mlmepriv, _FW_UNDER_SURVEY)) {
- ret = UNDER_SURVEY_T1;
-
-#ifdef CONFIG_IOCTL_CFG80211
- buddy_wdev_priv = adapter_wdev_data(iface);
- _enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL);
- _enter_critical_bh(&buddy_wdev_priv->scan_req_lock, &irqL);
- if (buddy_wdev_priv->scan_request) {
- pmlmepriv->scanning_via_buddy_intf = _TRUE;
- _enter_critical_bh(&pmlmepriv->lock, &irqL);
- set_fwstate(pmlmepriv, _FW_UNDER_SURVEY);
- _exit_critical_bh(&pmlmepriv->lock, &irqL);
- ret = UNDER_SURVEY_T2;
- }
- _exit_critical_bh(&buddy_wdev_priv->scan_req_lock, &irqL);
- _exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL);
-#endif
-
- RTW_INFO(ADPT_FMT"_FW_UNDER_SURVEY\n", ADPT_ARG(iface));
- return ret;
- }
+ if (ops_func)
+ if (_TRUE == ops_func(iface, data))
+ ret++;
}
}
return ret;
}
-void rtw_mi_buddy_indicate_scan_done(_adapter *padapter, bool bscan_aborted)
-{
-#if defined(CONFIG_IOCTL_CFG80211)
- int i;
- u8 ret = 0;
- _adapter *iface = NULL;
- _irqL irqL;
- struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
- struct mlme_priv *mlmepriv;
- struct rtw_wdev_priv *wdev_priv;
- bool indicate_buddy_scan = _FALSE;
-
- for (i = 0; i < dvobj->iface_nums; i++) {
- iface = dvobj->padapters[i];
- if ((iface) && rtw_is_adapter_up(iface)) {
-
- if (iface == padapter)
- continue;
-
- mlmepriv = &(iface->mlmepriv);
- wdev_priv = adapter_wdev_data(iface);
-
- _enter_critical_bh(&wdev_priv->scan_req_lock, &irqL);
- if (wdev_priv->scan_request && mlmepriv->scanning_via_buddy_intf == _TRUE) {
- mlmepriv->scanning_via_buddy_intf = _FALSE;
- clr_fwstate(mlmepriv, _FW_UNDER_SURVEY);
- indicate_buddy_scan = _TRUE;
- }
- _exit_critical_bh(&wdev_priv->scan_req_lock, &irqL);
-
- if (indicate_buddy_scan == _TRUE) {
- rtw_cfg80211_surveydone_event_callback(iface);
- rtw_indicate_scan_done(iface, bscan_aborted);
- }
-
- }
- }
-#endif
-
-}
-#endif
-
-/*
-* return value : 0 is failed or have not interface meet condition
-* return value : !0 is success or interface numbers which meet condition
-* return value of ops_func must be _TRUE or _FALSE
-*/
-static u8 _rtw_mi_process(_adapter *padapter, bool exclude_self,
+static u8 _rtw_mi_process_without_schk(_adapter *padapter, bool exclude_self,
void *data, u8(*ops_func)(_adapter *padapter, void *data))
{
int i;
@@ -520,39 +501,66 @@ static u8 _rtw_mi_process(_adapter *padapter, bool exclude_self,
for (i = 0; i < dvobj->iface_nums; i++) {
iface = dvobj->padapters[i];
- if ((iface) && rtw_is_adapter_up(iface)) {
-
+ if (iface) {
if ((exclude_self) && (iface == padapter))
continue;
if (ops_func)
- if (_TRUE == ops_func(iface, data))
+ if (ops_func(iface, data) == _TRUE)
ret++;
}
}
return ret;
}
-static u8 _rtw_mi_netif_stop_queue(_adapter *padapter, void *data)
+
+static u8 _rtw_mi_netif_caroff_qstop(_adapter *padapter, void *data)
{
- bool carrier_off = *(bool *)data;
struct net_device *pnetdev = padapter->pnetdev;
- if (carrier_off)
- netif_carrier_off(pnetdev);
+ rtw_netif_carrier_off(pnetdev);
rtw_netif_stop_queue(pnetdev);
return _TRUE;
}
-u8 rtw_mi_netif_stop_queue(_adapter *padapter, bool carrier_off)
+u8 rtw_mi_netif_caroff_qstop(_adapter *padapter)
{
- bool in_data = carrier_off;
+ return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_netif_caroff_qstop);
+}
+u8 rtw_mi_buddy_netif_caroff_qstop(_adapter *padapter)
+{
+ return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_caroff_qstop);
+}
+
+static u8 _rtw_mi_netif_caron_qstart(_adapter *padapter, void *data)
+{
+ struct net_device *pnetdev = padapter->pnetdev;
- return _rtw_mi_process(padapter, _FALSE, &in_data, _rtw_mi_netif_stop_queue);
+ rtw_netif_carrier_on(pnetdev);
+ rtw_netif_start_queue(pnetdev);
+ return _TRUE;
+}
+u8 rtw_mi_netif_caron_qstart(_adapter *padapter)
+{
+ return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_netif_caron_qstart);
}
-u8 rtw_mi_buddy_netif_stop_queue(_adapter *padapter, bool carrier_off)
+u8 rtw_mi_buddy_netif_caron_qstart(_adapter *padapter)
{
- bool in_data = carrier_off;
+ return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_caron_qstart);
+}
+
+static u8 _rtw_mi_netif_stop_queue(_adapter *padapter, void *data)
+{
+ struct net_device *pnetdev = padapter->pnetdev;
- return _rtw_mi_process(padapter, _TRUE, &in_data, _rtw_mi_netif_stop_queue);
+ rtw_netif_stop_queue(pnetdev);
+ return _TRUE;
+}
+u8 rtw_mi_netif_stop_queue(_adapter *padapter)
+{
+ return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_netif_stop_queue);
+}
+u8 rtw_mi_buddy_netif_stop_queue(_adapter *padapter)
+{
+ return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_stop_queue);
}
static u8 _rtw_mi_netif_wake_queue(_adapter *padapter, void *data)
@@ -589,6 +597,23 @@ u8 rtw_mi_buddy_netif_carrier_on(_adapter *padapter)
return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_carrier_on);
}
+static u8 _rtw_mi_netif_carrier_off(_adapter *padapter, void *data)
+{
+ struct net_device *pnetdev = padapter->pnetdev;
+
+ if (pnetdev)
+ rtw_netif_carrier_off(pnetdev);
+ return _TRUE;
+}
+u8 rtw_mi_netif_carrier_off(_adapter *padapter)
+{
+ return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_netif_carrier_off);
+}
+u8 rtw_mi_buddy_netif_carrier_off(_adapter *padapter)
+{
+ return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_carrier_off);
+}
+
static u8 _rtw_mi_scan_abort(_adapter *adapter, void *data)
{
bool bwait = *(bool *)data;
@@ -614,32 +639,57 @@ void rtw_mi_buddy_scan_abort(_adapter *adapter, bool bwait)
_rtw_mi_process(adapter, _TRUE, &in_data, _rtw_mi_scan_abort);
}
-static u8 _rtw_mi_start_drv_threads(_adapter *adapter, void *data)
+static u32 _rtw_mi_start_drv_threads(_adapter *adapter, bool exclude_self)
{
- rtw_start_drv_threads(adapter);
- return _TRUE;
+ int i;
+ _adapter *iface = NULL;
+ struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+ u32 _status = _SUCCESS;
+
+ for (i = 0; i < dvobj->iface_nums; i++) {
+ iface = dvobj->padapters[i];
+ if (iface) {
+ if ((exclude_self) && (iface == adapter))
+ continue;
+ if (rtw_start_drv_threads(iface) == _FAIL) {
+ _status = _FAIL;
+ break;
+ }
+ }
+ }
+ return _status;
}
-void rtw_mi_start_drv_threads(_adapter *adapter)
+u32 rtw_mi_start_drv_threads(_adapter *adapter)
{
- _rtw_mi_process(adapter, _FALSE, NULL, _rtw_mi_start_drv_threads);
+ return _rtw_mi_start_drv_threads(adapter, _FALSE);
}
-void rtw_mi_buddy_start_drv_threads(_adapter *adapter)
+u32 rtw_mi_buddy_start_drv_threads(_adapter *adapter)
{
- _rtw_mi_process(adapter, _TRUE, NULL, _rtw_mi_start_drv_threads);
+ return _rtw_mi_start_drv_threads(adapter, _TRUE);
}
-static u8 _rtw_mi_stop_drv_threads(_adapter *adapter, void *data)
+static void _rtw_mi_stop_drv_threads(_adapter *adapter, bool exclude_self)
{
- rtw_stop_drv_threads(adapter);
- return _TRUE;
+ int i;
+ _adapter *iface = NULL;
+ struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+
+ for (i = 0; i < dvobj->iface_nums; i++) {
+ iface = dvobj->padapters[i];
+ if (iface) {
+ if ((exclude_self) && (iface == adapter))
+ continue;
+ rtw_stop_drv_threads(iface);
+ }
+ }
}
void rtw_mi_stop_drv_threads(_adapter *adapter)
{
- _rtw_mi_process(adapter, _FALSE, NULL, _rtw_mi_stop_drv_threads);
+ _rtw_mi_stop_drv_threads(adapter, _FALSE);
}
void rtw_mi_buddy_stop_drv_threads(_adapter *adapter)
{
- _rtw_mi_process(adapter, _TRUE, NULL, _rtw_mi_stop_drv_threads);
+ _rtw_mi_stop_drv_threads(adapter, _TRUE);
}
static u8 _rtw_mi_cancel_all_timer(_adapter *adapter, void *data)
@@ -663,11 +713,11 @@ static u8 _rtw_mi_reset_drv_sw(_adapter *adapter, void *data)
}
void rtw_mi_reset_drv_sw(_adapter *adapter)
{
- _rtw_mi_process(adapter, _FALSE, NULL, _rtw_mi_reset_drv_sw);
+ _rtw_mi_process_without_schk(adapter, _FALSE, NULL, _rtw_mi_reset_drv_sw);
}
void rtw_mi_buddy_reset_drv_sw(_adapter *adapter)
{
- _rtw_mi_process(adapter, _TRUE, NULL, _rtw_mi_reset_drv_sw);
+ _rtw_mi_process_without_schk(adapter, _TRUE, NULL, _rtw_mi_reset_drv_sw);
}
static u8 _rtw_mi_intf_start(_adapter *adapter, void *data)
@@ -746,58 +796,14 @@ void rtw_mi_buddy_set_scan_deny(_adapter *adapter, u32 ms)
_rtw_mi_process(adapter, _TRUE, &in_data, _rtw_mi_set_scan_deny);
}
-#endif
-
-struct nulldata_param {
- unsigned char *da;
- unsigned int power_mode;
- int try_cnt;
- int wait_ms;
-};
-
-static u8 _rtw_mi_issue_nulldata(_adapter *padapter, void *data)
-{
- struct nulldata_param *pnulldata_param = (struct nulldata_param *)data;
-
- if (is_client_associated_to_ap(padapter) == _TRUE) {
- /* TODO: TDLS peers */
- issue_nulldata(padapter, pnulldata_param->da, pnulldata_param->power_mode, pnulldata_param->try_cnt, pnulldata_param->wait_ms);
- return _TRUE;
- }
- return _FALSE;
-}
-
-u8 rtw_mi_issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms)
-{
- struct nulldata_param nparam;
-
- nparam.da = da;
- nparam.power_mode = power_mode;/*0 or 1*/
- nparam.try_cnt = try_cnt;
- nparam.wait_ms = wait_ms;
-
- return _rtw_mi_process(padapter, _FALSE, &nparam, _rtw_mi_issue_nulldata);
-}
-u8 rtw_mi_buddy_issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms)
-{
- struct nulldata_param nparam;
-
- nparam.da = da;
- nparam.power_mode = power_mode;
- nparam.try_cnt = try_cnt;
- nparam.wait_ms = wait_ms;
-
- return _rtw_mi_process(padapter, _TRUE, &nparam, _rtw_mi_issue_nulldata);
-}
+#endif /*CONFIG_SET_SCAN_DENY_TIMER*/
static u8 _rtw_mi_beacon_update(_adapter *padapter, void *data)
{
- struct mlme_ext_priv *mlmeext = &padapter->mlmeextpriv;
-
- if (mlmeext_msr(mlmeext) == WIFI_FW_AP_STATE
+ if (!MLME_IS_STA(padapter)
&& check_fwstate(&padapter->mlmepriv, _FW_LINKED) == _TRUE) {
- RTW_INFO(ADPT_FMT"-WIFI_FW_AP_STATE - update_beacon\n", ADPT_ARG(padapter));
- update_beacon(padapter, 0, NULL, _TRUE);
+ RTW_INFO(ADPT_FMT" - update_beacon\n", ADPT_ARG(padapter));
+ update_beacon(padapter, 0xFF, NULL, _TRUE);
}
return _TRUE;
}
@@ -816,7 +822,7 @@ static u8 _rtw_mi_hal_dump_macaddr(_adapter *padapter, void *data)
{
u8 mac_addr[ETH_ALEN] = {0};
- rtw_hal_get_macaddr_port(padapter, mac_addr);
+ rtw_hal_get_hwreg(padapter, HW_VAR_MAC_ADDR, mac_addr);
RTW_INFO(ADPT_FMT"MAC Address ="MAC_FMT"\n", ADPT_ARG(padapter), MAC_ARG(mac_addr));
return _TRUE;
}
@@ -987,20 +993,6 @@ static u8 _rtw_mi_traffic_statistics(_adapter *padapter , void *data)
}
u8 rtw_mi_traffic_statistics(_adapter *padapter)
{
- struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
-
- /*_rtw_memset(&pdvobjpriv->traffic_stat, 0, sizeof(struct rtw_traffic_statistics));*/
-
- /* Tx bytes reset*/
- pdvobjpriv->traffic_stat.tx_bytes = 0;
- pdvobjpriv->traffic_stat.tx_pkts = 0;
- pdvobjpriv->traffic_stat.tx_drop = 0;
-
- /* Rx bytes reset*/
- pdvobjpriv->traffic_stat.rx_bytes = 0;
- pdvobjpriv->traffic_stat.rx_pkts = 0;
- pdvobjpriv->traffic_stat.rx_drop = 0;
-
return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_traffic_statistics);
}
@@ -1085,7 +1077,7 @@ void rtw_mi_buddy_adapter_reset(_adapter *padapter)
static u8 _rtw_mi_dynamic_check_timer_handlder(_adapter *adapter, void *data)
{
- rtw_dynamic_check_timer_handlder(adapter);
+ rtw_iface_dynamic_check_timer_handlder(adapter);
return _TRUE;
}
u8 rtw_mi_dynamic_check_timer_handlder(_adapter *padapter)
@@ -1113,7 +1105,7 @@ u8 rtw_mi_buddy_dev_unload(_adapter *padapter)
static u8 _rtw_mi_dynamic_chk_wk_hdl(_adapter *adapter, void *data)
{
- dynamic_chk_wk_hdl(adapter);
+ rtw_iface_dynamic_chk_wk_hdl(adapter);
return _TRUE;
}
u8 rtw_mi_dynamic_chk_wk_hdl(_adapter *padapter)
@@ -1179,9 +1171,9 @@ u8 rtw_mi_buddy_sreset_adapter_hdl(_adapter *padapter, u8 bstart)
}
static u8 _rtw_mi_tx_beacon_hdl(_adapter *adapter, void *data)
{
- if (check_fwstate(&adapter->mlmepriv, WIFI_AP_STATE) == _TRUE
- && check_fwstate(&adapter->mlmepriv, WIFI_ASOC_STATE) == _TRUE
- ) {
+ if ((MLME_IS_AP(adapter) || MLME_IS_MESH(adapter))
+ && check_fwstate(&adapter->mlmepriv, WIFI_ASOC_STATE) == _TRUE
+ ) {
adapter->mlmepriv.update_bcn = _TRUE;
#ifndef CONFIG_INTERRUPT_BASED_TXBCN
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
@@ -1204,7 +1196,7 @@ static u8 _rtw_mi_set_tx_beacon_cmd(_adapter *adapter, void *data)
{
struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
- if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) {
+ if (MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)) {
if (pmlmepriv->update_bcn == _TRUE)
set_tx_beacon_cmd(adapter);
}
@@ -1390,7 +1382,7 @@ static s32 _rtw_mi_buddy_clone_bcmc_packet(_adapter *adapter, union recv_frame *
rtw_dbg_skb_process(adapter, precvframe, pcloneframe);
#endif
- if (pattrib->physt && pphy_status)
+ if (pphy_status)
rx_query_phy_status(pcloneframe, pphy_status);
ret = rtw_recv_entry(pcloneframe);
@@ -1412,20 +1404,25 @@ void rtw_mi_buddy_clone_bcmc_packet(_adapter *padapter, union recv_frame *precvf
struct recv_priv *precvpriv = &padapter->recvpriv;/*primary_padapter*/
_queue *pfree_recv_queue = &precvpriv->free_recv_queue;
struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+ u8 *fhead = get_recvframe_data(precvframe);
+ u8 type = GetFrameType(fhead);
for (i = 0; i < dvobj->iface_nums; i++) {
iface = dvobj->padapters[i];
- if ((iface) && rtw_is_adapter_up(iface)) {
- if (iface == padapter)
- continue;
- pcloneframe = rtw_alloc_recvframe(pfree_recv_queue);
- if (pcloneframe) {
- ret = _rtw_mi_buddy_clone_bcmc_packet(iface, precvframe, pphy_status, pcloneframe);
- if (_SUCCESS != ret) {
- if (ret == -1)
- rtw_free_recvframe(pcloneframe, pfree_recv_queue);
- /*RTW_INFO(ADPT_FMT"-clone BC/MC frame failed\n", ADPT_ARG(iface));*/
- }
+ if (!iface || iface == padapter)
+ continue;
+ if (rtw_is_adapter_up(iface) == _FALSE || iface->registered == 0)
+ continue;
+ if (type == WIFI_DATA_TYPE && !adapter_allow_bmc_data_rx(iface))
+ continue;
+
+ pcloneframe = rtw_alloc_recvframe(pfree_recv_queue);
+ if (pcloneframe) {
+ ret = _rtw_mi_buddy_clone_bcmc_packet(iface, precvframe, pphy_status, pcloneframe);
+ if (_SUCCESS != ret) {
+ if (ret == -1)
+ rtw_free_recvframe(pcloneframe, pfree_recv_queue);
+ /*RTW_INFO(ADPT_FMT"-clone BC/MC frame failed\n", ADPT_ARG(iface));*/
}
}
}
@@ -1478,3 +1475,4 @@ void rtw_mi_update_ap_bmc_camid(_adapter *padapter, u8 camid_a, u8 camid_b)
}
#endif
}
+
diff --git a/core/rtw_mlme.c b/core/rtw_mlme.c
index 04e0d9a..baee8e4 100644
--- a/core/rtw_mlme.c
+++ b/core/rtw_mlme.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,12 +11,7 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#define _RTW_MLME_C_
#include
@@ -25,6 +20,27 @@ extern void indicate_wx_scan_complete_event(_adapter *padapter);
extern u8 rtw_do_join(_adapter *padapter);
+void rtw_init_mlme_timer(_adapter *padapter)
+{
+ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+
+ rtw_init_timer(&(pmlmepriv->assoc_timer), padapter, rtw_join_timeout_handler, padapter);
+ rtw_init_timer(&(pmlmepriv->scan_to_timer), padapter, rtw_scan_timeout_handler, padapter);
+
+#ifdef CONFIG_DFS_MASTER
+ rtw_init_timer(&(pmlmepriv->dfs_master_timer), padapter, rtw_dfs_master_timer_hdl, padapter);
+#endif
+
+#ifdef CONFIG_SET_SCAN_DENY_TIMER
+ rtw_init_timer(&(pmlmepriv->set_scan_deny_timer), padapter, rtw_set_scan_deny_timer_hdl, padapter);
+#endif
+
+#ifdef RTK_DMP_PLATFORM
+ _init_workitem(&(pmlmepriv->Linkup_workitem), Linkup_workitem_callback, padapter);
+ _init_workitem(&(pmlmepriv->Linkdown_workitem), Linkdown_workitem_callback, padapter);
+#endif
+}
+
sint _rtw_init_mlme_priv(_adapter *padapter)
{
sint i;
@@ -33,7 +49,6 @@ sint _rtw_init_mlme_priv(_adapter *padapter)
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
sint res = _SUCCESS;
- _func_enter_;
/* We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). */
/* _rtw_memset((u8 *)pmlmepriv, 0, sizeof(struct mlme_priv)); */
@@ -89,12 +104,14 @@ sint _rtw_init_mlme_priv(_adapter *padapter)
rtw_clear_scan_deny(padapter);
#ifdef CONFIG_ARP_KEEP_ALIVE
pmlmepriv->bGetGateway = 0;
+ pmlmepriv->GetGatewayTryCnt = 0;
#endif
#ifdef CONFIG_LAYER2_ROAMING
#define RTW_ROAM_SCAN_RESULT_EXP_MS (5*1000)
#define RTW_ROAM_RSSI_DIFF_TH 10
#define RTW_ROAM_SCAN_INTERVAL_MS (10*1000)
+#define RTW_ROAM_RSSI_THRESHOLD 70
pmlmepriv->roam_flags = 0
| RTW_ROAM_ON_EXPIRED
@@ -109,13 +126,23 @@ sint _rtw_init_mlme_priv(_adapter *padapter)
pmlmepriv->roam_scanr_exp_ms = RTW_ROAM_SCAN_RESULT_EXP_MS;
pmlmepriv->roam_rssi_diff_th = RTW_ROAM_RSSI_DIFF_TH;
pmlmepriv->roam_scan_int_ms = RTW_ROAM_SCAN_INTERVAL_MS;
+ pmlmepriv->roam_rssi_threshold = RTW_ROAM_RSSI_THRESHOLD;
+ pmlmepriv->need_to_roam = _FALSE;
#endif /* CONFIG_LAYER2_ROAMING */
+#ifdef CONFIG_RTW_80211R
+ rtw_ft_info_init(&pmlmepriv->ft_roam);
+#endif
+#ifdef CONFIG_LAYER2_ROAMING
+#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K)
+ rtw_roam_nb_info_init(padapter);
+ pmlmepriv->ch_cnt = 0;
+#endif
+#endif
rtw_init_mlme_timer(padapter);
exit:
- _func_exit_;
return res;
}
@@ -164,6 +191,9 @@ void rtw_free_mlme_priv_ie_data(struct mlme_priv *pmlmepriv)
rtw_free_mlme_ie_data(&pmlmepriv->wfd_assoc_resp_ie, &pmlmepriv->wfd_assoc_resp_ie_len);
#endif
+#ifdef CONFIG_RTW_80211R
+ rtw_free_mlme_ie_data(&pmlmepriv->auth_rsp, &pmlmepriv->auth_rsp_len);
+#endif
}
#if defined(CONFIG_WFD) && defined(CONFIG_IOCTL_CFG80211)
@@ -265,7 +295,6 @@ int rtw_mlme_update_wfd_ie_data(struct mlme_priv *mlme, u8 type, u8 *ie, u32 ie_
void _rtw_free_mlme_priv(struct mlme_priv *pmlmepriv)
{
- _func_enter_;
if (NULL == pmlmepriv) {
rtw_warn_on(1);
goto exit;
@@ -279,14 +308,13 @@ void _rtw_free_mlme_priv(struct mlme_priv *pmlmepriv)
rtw_vmfree(pmlmepriv->free_bss_buf, MAX_BSS_CNT * sizeof(struct wlan_network));
}
exit:
- _func_exit_;
+ return;
}
sint _rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork)
{
_irqL irqL;
- _func_enter_;
if (pnetwork == NULL)
goto exit;
@@ -299,7 +327,6 @@ sint _rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork)
exit:
- _func_exit_;
return _SUCCESS;
}
@@ -311,7 +338,6 @@ struct wlan_network *_rtw_dequeue_network(_queue *queue)
struct wlan_network *pnetwork;
-_func_enter_;
_enter_critical_bh(&queue->lock, &irqL);
@@ -328,7 +354,6 @@ _func_enter_;
_exit_critical_bh(&queue->lock, &irqL);
-_func_exit_;
return pnetwork;
}
@@ -341,7 +366,6 @@ struct wlan_network *_rtw_alloc_network(struct mlme_priv *pmlmepriv) /* (_queue
_queue *free_queue = &pmlmepriv->free_bss_pool;
_list *plist = NULL;
- _func_enter_;
_enter_critical_bh(&free_queue->lock, &irqL);
@@ -355,7 +379,6 @@ struct wlan_network *_rtw_alloc_network(struct mlme_priv *pmlmepriv) /* (_queue
rtw_list_delete(&pnetwork->list);
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("_rtw_alloc_network: ptr=%p\n", plist));
pnetwork->network_type = 0;
pnetwork->fixed = _FALSE;
pnetwork->last_scanned = rtw_get_current_time();
@@ -367,7 +390,6 @@ struct wlan_network *_rtw_alloc_network(struct mlme_priv *pmlmepriv) /* (_queue
exit:
_exit_critical_bh(&free_queue->lock, &irqL);
- _func_exit_;
return pnetwork;
}
@@ -379,7 +401,6 @@ void _rtw_free_network(struct mlme_priv *pmlmepriv , struct wlan_network *pnetwo
_irqL irqL;
_queue *free_queue = &(pmlmepriv->free_bss_pool);
- _func_enter_;
if (pnetwork == NULL)
goto exit;
@@ -411,9 +432,7 @@ void _rtw_free_network(struct mlme_priv *pmlmepriv , struct wlan_network *pnetwo
_exit_critical_bh(&free_queue->lock, &irqL);
exit:
-
- _func_exit_;
-
+ return;
}
void _rtw_free_network_nolock(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork)
@@ -421,7 +440,6 @@ void _rtw_free_network_nolock(struct mlme_priv *pmlmepriv, struct wlan_network *
_queue *free_queue = &(pmlmepriv->free_bss_pool);
- _func_enter_;
if (pnetwork == NULL)
goto exit;
@@ -440,60 +458,9 @@ void _rtw_free_network_nolock(struct mlme_priv *pmlmepriv, struct wlan_network *
/* _exit_critical(&free_queue->lock, &irqL); */
exit:
-
- _func_exit_;
-
-}
-
-
-/*
- return the wlan_network with the matching addr
-
- Shall be calle under atomic context... to avoid possible racing condition...
-*/
-struct wlan_network *_rtw_find_network(_queue *scanned_queue, u8 *addr)
-{
-
- /* _irqL irqL; */
- _list *phead, *plist;
- struct wlan_network *pnetwork = NULL;
- u8 zero_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
-
- _func_enter_;
-
- if (_rtw_memcmp(zero_addr, addr, ETH_ALEN)) {
- pnetwork = NULL;
- goto exit;
- }
-
- /* _enter_critical_bh(&scanned_queue->lock, &irqL); */
-
- phead = get_list_head(scanned_queue);
- plist = get_next(phead);
-
- while (plist != phead) {
- pnetwork = LIST_CONTAINOR(plist, struct wlan_network , list);
-
- if (_rtw_memcmp(addr, pnetwork->network.MacAddress, ETH_ALEN) == _TRUE)
- break;
-
- plist = get_next(plist);
- }
-
- if (plist == phead)
- pnetwork = NULL;
-
- /* _exit_critical_bh(&scanned_queue->lock, &irqL); */
-
-exit:
-
- _func_exit_;
-
- return pnetwork;
-
+ return;
}
-
void _rtw_free_network_queue(_adapter *padapter, u8 isfreeall)
{
_irqL irqL;
@@ -502,7 +469,6 @@ void _rtw_free_network_queue(_adapter *padapter, u8 isfreeall)
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
_queue *scanned_queue = &pmlmepriv->scanned_queue;
- _func_enter_;
_enter_critical_bh(&scanned_queue->lock, &irqL);
@@ -522,7 +488,6 @@ void _rtw_free_network_queue(_adapter *padapter, u8 isfreeall)
_exit_critical_bh(&scanned_queue->lock, &irqL);
- _func_exit_;
}
@@ -533,18 +498,13 @@ sint rtw_if_up(_adapter *padapter)
{
sint res;
- _func_enter_;
if (RTW_CANNOT_RUN(padapter) ||
(check_fwstate(&padapter->mlmepriv, _FW_LINKED) == _FALSE)) {
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("rtw_if_up:bDriverStopped(%s) OR bSurpriseRemoved(%s)"
- , rtw_is_drv_stopped(padapter) ? "True" : "False"
- , rtw_is_surprise_removed(padapter) ? "True" : "False"));
res = _FALSE;
} else
res = _TRUE;
- _func_exit_;
return res;
}
@@ -566,11 +526,9 @@ u8 *rtw_get_capability_from_ie(u8 *ie)
u16 rtw_get_capability(WLAN_BSSID_EX *bss)
{
u16 val;
- _func_enter_;
_rtw_memcpy((u8 *)&val, rtw_get_capability_from_ie(bss->IEs), 2);
- _func_exit_;
return le16_to_cpu(val);
}
@@ -588,27 +546,20 @@ u8 *rtw_get_beacon_interval_from_ie(u8 *ie)
int rtw_init_mlme_priv(_adapter *padapter) /* (struct mlme_priv *pmlmepriv) */
{
int res;
- _func_enter_;
res = _rtw_init_mlme_priv(padapter);/* (pmlmepriv); */
- _func_exit_;
return res;
}
void rtw_free_mlme_priv(struct mlme_priv *pmlmepriv)
{
- _func_enter_;
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("rtw_free_mlme_priv\n"));
_rtw_free_mlme_priv(pmlmepriv);
- _func_exit_;
}
int rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork);
int rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork)
{
int res;
- _func_enter_;
res = _rtw_enqueue_network(queue, pnetwork);
- _func_exit_;
return res;
}
@@ -616,9 +567,7 @@ int rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork)
static struct wlan_network *rtw_dequeue_network(_queue *queue)
{
struct wlan_network *pnetwork;
-_func_enter_;
pnetwork = _rtw_dequeue_network(queue);
-_func_exit_;
return pnetwork;
}
*/
@@ -627,49 +576,69 @@ struct wlan_network *rtw_alloc_network(struct mlme_priv *pmlmepriv);
struct wlan_network *rtw_alloc_network(struct mlme_priv *pmlmepriv) /* (_queue *free_queue) */
{
struct wlan_network *pnetwork;
- _func_enter_;
pnetwork = _rtw_alloc_network(pmlmepriv);
- _func_exit_;
return pnetwork;
}
void rtw_free_network(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork, u8 is_freeall);
void rtw_free_network(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork, u8 is_freeall)/* (struct wlan_network *pnetwork, _queue *free_queue) */
{
- _func_enter_;
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("rtw_free_network==> ssid = %s \n\n" , pnetwork->network.Ssid.Ssid));
_rtw_free_network(pmlmepriv, pnetwork, is_freeall);
- _func_exit_;
}
void rtw_free_network_nolock(_adapter *padapter, struct wlan_network *pnetwork);
void rtw_free_network_nolock(_adapter *padapter, struct wlan_network *pnetwork)
{
- _func_enter_;
- /* RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("rtw_free_network==> ssid = %s \n\n" , pnetwork->network.Ssid.Ssid)); */
_rtw_free_network_nolock(&(padapter->mlmepriv), pnetwork);
#ifdef CONFIG_IOCTL_CFG80211
rtw_cfg80211_unlink_bss(padapter, pnetwork);
#endif /* CONFIG_IOCTL_CFG80211 */
- _func_exit_;
}
void rtw_free_network_queue(_adapter *dev, u8 isfreeall)
{
- _func_enter_;
_rtw_free_network_queue(dev, isfreeall);
- _func_exit_;
}
-/*
- return the wlan_network with the matching addr
+struct wlan_network *_rtw_find_network(_queue *scanned_queue, const u8 *addr)
+{
+ _list *phead, *plist;
+ struct wlan_network *pnetwork = NULL;
+ u8 zero_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
- Shall be calle under atomic context... to avoid possible racing condition...
-*/
-struct wlan_network *rtw_find_network(_queue *scanned_queue, u8 *addr)
+ if (_rtw_memcmp(zero_addr, addr, ETH_ALEN)) {
+ pnetwork = NULL;
+ goto exit;
+ }
+
+ phead = get_list_head(scanned_queue);
+ plist = get_next(phead);
+
+ while (plist != phead) {
+ pnetwork = LIST_CONTAINOR(plist, struct wlan_network , list);
+
+ if (_rtw_memcmp(addr, pnetwork->network.MacAddress, ETH_ALEN) == _TRUE)
+ break;
+
+ plist = get_next(plist);
+ }
+
+ if (plist == phead)
+ pnetwork = NULL;
+
+exit:
+ return pnetwork;
+}
+
+struct wlan_network *rtw_find_network(_queue *scanned_queue, const u8 *addr)
{
- struct wlan_network *pnetwork = _rtw_find_network(scanned_queue, addr);
+ struct wlan_network *pnetwork;
+ _irqL irqL;
+
+ _enter_critical_bh(&scanned_queue->lock, &irqL);
+ pnetwork = _rtw_find_network(scanned_queue, addr);
+ _exit_critical_bh(&scanned_queue->lock, &irqL);
return pnetwork;
}
@@ -694,8 +663,6 @@ int rtw_is_same_ibss(_adapter *adapter, struct wlan_network *pnetwork)
inline int is_same_ess(WLAN_BSSID_EX *a, WLAN_BSSID_EX *b)
{
- /* RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("(%s,%d)(%s,%d)\n", */
- /* a->Ssid.Ssid,a->Ssid.SsidLength,b->Ssid.Ssid,b->Ssid.SsidLength)); */
return (a->Ssid.SsidLength == b->Ssid.SsidLength)
&& _rtw_memcmp(a->Ssid.Ssid, b->Ssid.Ssid, a->Ssid.SsidLength) == _TRUE;
}
@@ -704,7 +671,6 @@ int is_same_network(WLAN_BSSID_EX *src, WLAN_BSSID_EX *dst, u8 feature)
{
u16 s_cap, d_cap;
- _func_enter_;
if (rtw_bug_check(dst, src, &s_cap, &d_cap) == _FALSE)
return _FALSE;
@@ -716,7 +682,6 @@ int is_same_network(WLAN_BSSID_EX *src, WLAN_BSSID_EX *dst, u8 feature)
s_cap = le16_to_cpu(s_cap);
d_cap = le16_to_cpu(d_cap);
- _func_exit_;
#ifdef CONFIG_P2P
if ((feature == 1) && /* 1: P2P supported */
@@ -725,15 +690,35 @@ int is_same_network(WLAN_BSSID_EX *src, WLAN_BSSID_EX *dst, u8 feature)
return _TRUE;
#endif
- return ((src->Ssid.SsidLength == dst->Ssid.SsidLength) &&
- /* (src->Configuration.DSConfig == dst->Configuration.DSConfig) && */
- ((_rtw_memcmp(src->MacAddress, dst->MacAddress, ETH_ALEN)) == _TRUE) &&
- ((_rtw_memcmp(src->Ssid.Ssid, dst->Ssid.Ssid, src->Ssid.SsidLength)) == _TRUE) &&
- ((s_cap & WLAN_CAPABILITY_IBSS) ==
- (d_cap & WLAN_CAPABILITY_IBSS)) &&
- ((s_cap & WLAN_CAPABILITY_BSS) ==
- (d_cap & WLAN_CAPABILITY_BSS)));
-
+ /* Wi-Fi driver doesn't consider the situation of BCN and ProbRsp sent from the same hidden AP,
+ * it considers these two packets are sent from different AP.
+ * Therefore, the scan queue may store two scan results of the same hidden AP, likes below.
+ *
+ * index bssid ch RSSI SdBm Noise age flag ssid
+ * 1 00:e0:4c:55:50:01 153 -73 -73 0 7044 [WPS][ESS] RTK5G
+ * 3 00:e0:4c:55:50:01 153 -73 -73 0 7044 [WPS][ESS]
+ *
+ * Original rules will compare Ssid, SsidLength, MacAddress, s_cap, d_cap at the same time.
+ * Wi-Fi driver will assume that the BCN and ProbRsp sent from the same hidden AP are the same network
+ * after we add an additional rule to compare SsidLength and Ssid.
+ * It means the scan queue will not store two scan results of the same hidden AP, it only store ProbRsp.
+ * For customer request.
+ */
+
+ if (((_rtw_memcmp(src->MacAddress, dst->MacAddress, ETH_ALEN)) == _TRUE) &&
+ ((s_cap & WLAN_CAPABILITY_IBSS) == (d_cap & WLAN_CAPABILITY_IBSS)) &&
+ ((s_cap & WLAN_CAPABILITY_BSS) == (d_cap & WLAN_CAPABILITY_BSS))) {
+ if ((src->Ssid.SsidLength == dst->Ssid.SsidLength) &&
+ (((_rtw_memcmp(src->Ssid.Ssid, dst->Ssid.Ssid, src->Ssid.SsidLength)) == _TRUE) || //Case of normal AP
+ (is_all_null(src->Ssid.Ssid, src->Ssid.SsidLength) == _TRUE || is_all_null(dst->Ssid.Ssid, dst->Ssid.SsidLength) == _TRUE))) //Case of hidden AP
+ return _TRUE;
+ else if ((src->Ssid.SsidLength == 0 || dst->Ssid.SsidLength == 0)) //Case of hidden AP
+ return _TRUE;
+ else
+ return _FALSE;
+ } else {
+ return _FALSE;
+ }
}
struct wlan_network *_rtw_find_same_network(_queue *scanned_queue, struct wlan_network *network)
@@ -782,7 +767,6 @@ struct wlan_network *rtw_get_oldest_wlan_network(_queue *scanned_queue)
struct wlan_network *pwlan = NULL;
struct wlan_network *oldest = NULL;
- _func_enter_;
phead = get_list_head(scanned_queue);
plist = get_next(phead);
@@ -795,13 +779,12 @@ struct wlan_network *rtw_get_oldest_wlan_network(_queue *scanned_queue)
pwlan = LIST_CONTAINOR(plist, struct wlan_network, list);
if (pwlan->fixed != _TRUE) {
- if (oldest == NULL || time_after(oldest->last_scanned, pwlan->last_scanned))
+ if (oldest == NULL || rtw_time_after(oldest->last_scanned, pwlan->last_scanned))
oldest = pwlan;
}
plist = get_next(plist);
}
- _func_exit_;
return oldest;
}
@@ -821,7 +804,6 @@ void update_network(WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src,
u8 sq_final;
long rssi_final;
- _func_enter_;
#ifdef CONFIG_ANTENNA_DIVERSITY
rtw_hal_antdiv_rssi_compared(padapter, dst, src); /* this will update src.Rssi, need consider again */
@@ -912,14 +894,12 @@ void update_network(WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src,
#endif
- _func_exit_;
}
static void update_current_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork)
{
struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
- _func_enter_;
rtw_bug_check(&(pmlmepriv->cur_network.network),
&(pmlmepriv->cur_network.network),
@@ -927,7 +907,6 @@ static void update_current_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork)
&(pmlmepriv->cur_network.network));
if ((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) && (is_same_network(&(pmlmepriv->cur_network.network), pnetwork, 0))) {
- /* RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,"Same Network\n"); */
/* if(pmlmepriv->cur_network.network.IELength<= pnetwork->IELength) */
{
@@ -937,7 +916,6 @@ static void update_current_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork)
}
}
- _func_exit_;
}
@@ -948,7 +926,7 @@ Caller must hold pmlmepriv->lock first.
*/
-void rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target)
+bool rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target)
{
_irqL irqL;
_list *plist, *phead;
@@ -963,13 +941,17 @@ void rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target)
struct wlan_network *oldest = NULL;
int target_find = 0;
u8 feature = 0;
-
- _func_enter_;
+ bool update_ie = _FALSE;
_enter_critical_bh(&queue->lock, &irqL);
phead = get_list_head(queue);
plist = get_next(phead);
+#if 0
+ RTW_INFO("%s => ssid:%s , rssi:%ld , ss:%d\n",
+ __func__, target->Ssid.Ssid, target->Rssi, target->PhyInfo.SignalStrength);
+#endif
+
#ifdef CONFIG_P2P
if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
feature = 1; /* p2p enable */
@@ -999,10 +981,21 @@ void rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target)
if (rtw_roam_flags(adapter)) {
/* TODO: don't select netowrk in the same ess as oldest if it's new enough*/
}
-
- if (oldest == NULL || time_after(oldest->last_scanned, pnetwork->last_scanned))
- oldest = pnetwork;
-
+#ifdef CONFIG_RSSI_PRIORITY
+ if ((oldest == NULL) || (pnetwork->network.PhyInfo.SignalStrength < oldest->network.PhyInfo.SignalStrength))
+ #ifdef CONFIG_RTW_MESH
+ if (!MLME_IS_MESH(adapter) || check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _FALSE
+ || !rtw_bss_is_same_mbss(&pmlmepriv->cur_network.network, &pnetwork->network))
+ #endif
+ oldest = pnetwork;
+#else
+ if (oldest == NULL || rtw_time_after(oldest->last_scanned, pnetwork->last_scanned))
+ #ifdef CONFIG_RTW_MESH
+ if (!MLME_IS_MESH(adapter) || check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _FALSE
+ || !rtw_bss_is_same_mbss(&pmlmepriv->cur_network.network, &pnetwork->network))
+ #endif
+ oldest = pnetwork;
+#endif
plist = get_next(plist);
}
@@ -1016,10 +1009,17 @@ void rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target)
/* If there are no more slots, expire the oldest */
/* list_del_init(&oldest->list); */
pnetwork = oldest;
- if (pnetwork == NULL) {
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("\n\n\nsomething wrong here\n\n\n"));
- goto exit;
- }
+ if (pnetwork == NULL)
+ goto unlock_scan_queue;
+
+#ifdef CONFIG_RSSI_PRIORITY
+ RTW_DBG("%s => ssid:%s ,bssid:"MAC_FMT" will be deleted from scanned_queue (rssi:%ld , ss:%d)\n",
+ __func__, pnetwork->network.Ssid.Ssid, MAC_ARG(pnetwork->network.MacAddress), pnetwork->network.Rssi, pnetwork->network.PhyInfo.SignalStrength);
+#else
+ RTW_DBG("%s => ssid:%s ,bssid:"MAC_FMT" will be deleted from scanned_queue\n",
+ __func__, pnetwork->network.Ssid.Ssid, MAC_ARG(pnetwork->network.MacAddress));
+#endif
+
#ifdef CONFIG_ANTENNA_DIVERSITY
rtw_hal_get_odm_var(adapter, HAL_ODM_ANTDIV_SELECT, &(target->PhyInfo.Optimum_antenna), NULL);
#endif
@@ -1040,11 +1040,8 @@ void rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target)
/* Otherwise just pull from the free list */
pnetwork = rtw_alloc_network(pmlmepriv); /* will update scan_time */
-
- if (pnetwork == NULL) {
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("\n\n\nsomething wrong here\n\n\n"));
- goto exit;
- }
+ if (pnetwork == NULL)
+ goto unlock_scan_queue;
bssid_ex_sz = get_WLAN_BSSID_EX_sz(target);
target->Length = bssid_ex_sz;
@@ -1067,39 +1064,56 @@ void rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target)
* be already expired. In this case we do the same as we found a new
* net and call the new_net handler
*/
- bool update_ie = _TRUE;
pnetwork->last_scanned = rtw_get_current_time();
- /* target.Reserved[0]==1, means that scaned network is a bcn frame. */
- if ((pnetwork->network.IELength > target->IELength) && (target->Reserved[0] == 1))
+ /* target.Reserved[0]==BSS_TYPE_BCN, means that scanned network is a bcn frame. */
+ if ((pnetwork->network.IELength > target->IELength) && (target->Reserved[0] == BSS_TYPE_BCN))
update_ie = _FALSE;
- /* probe resp(3) > beacon(1) > probe req(2) */
- if ((target->Reserved[0] != 2) &&
- (target->Reserved[0] >= pnetwork->network.Reserved[0])
- )
+ if (MLME_IS_MESH(adapter)
+ /* probe resp(3) > beacon(1) > probe req(2) */
+ || (target->Reserved[0] != BSS_TYPE_PROB_REQ
+ && target->Reserved[0] >= pnetwork->network.Reserved[0])
+ )
update_ie = _TRUE;
else
update_ie = _FALSE;
update_network(&(pnetwork->network), target, adapter, update_ie);
}
-
-exit:
+ /*
+ * report network only if the current channel set contains the channel
+ * to which this network belongs. Report early so that we have a valid
+ * scan timestamp, finish up in scan-done callback.
+ */
+ if (rtw_chset_search_ch(adapter_to_chset(adapter),
+ pnetwork->network.Configuration.DSConfig) >= 0
+ && rtw_mlme_band_check(adapter, pnetwork->network.Configuration.DSConfig) == _TRUE
+ && _TRUE == rtw_validate_ssid(&(pnetwork->network.Ssid)))
+ rtw_cfg80211_inform_bss(adapter, pnetwork);
+
+unlock_scan_queue:
_exit_critical_bh(&queue->lock, &irqL);
- _func_exit_;
+#ifdef CONFIG_RTW_MESH
+ if (pnetwork && MLME_IS_MESH(adapter)
+ && check_fwstate(pmlmepriv, WIFI_ASOC_STATE)
+ && !check_fwstate(pmlmepriv, WIFI_SITE_MONITOR)
+ )
+ rtw_chk_candidate_peer_notify(adapter, pnetwork);
+#endif
+
+ return update_ie;
}
-void rtw_add_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork);
void rtw_add_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork)
{
_irqL irqL;
struct mlme_priv *pmlmepriv = &(((_adapter *)adapter)->mlmepriv);
+ bool update_ie;
/* _queue *queue = &(pmlmepriv->scanned_queue); */
- _func_enter_;
/* _enter_critical_bh(&queue->lock, &irqL); */
@@ -1111,13 +1125,14 @@ void rtw_add_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork)
if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST))
rtw_bss_ex_del_wfd_ie(pnetwork);
- update_current_network(adapter, pnetwork);
+ /* Wi-Fi driver will update the current network if the scan result of the connected AP be updated by scan. */
+ update_ie = rtw_update_scanned_network(adapter, pnetwork);
- rtw_update_scanned_network(adapter, pnetwork);
+ if (update_ie)
+ update_current_network(adapter, pnetwork);
/* _exit_critical_bh(&queue->lock, &irqL); */
- _func_exit_;
}
/* select the desired network based on the capability of the (i)bss.
@@ -1126,7 +1141,6 @@ void rtw_add_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork)
* (3) WMM
* (4) HT
* (5) others */
-int rtw_is_desired_network(_adapter *adapter, struct wlan_network *pnetwork);
int rtw_is_desired_network(_adapter *adapter, struct wlan_network *pnetwork)
{
struct security_priv *psecuritypriv = &adapter->securitypriv;
@@ -1183,9 +1197,6 @@ int rtw_is_desired_network(_adapter *adapter, struct wlan_network *pnetwork)
void rtw_atimdone_event_callback(_adapter *adapter , u8 *pbuf)
{
- _func_enter_;
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("receive atimdone_evet\n"));
- _func_exit_;
return;
}
@@ -1197,11 +1208,9 @@ void rtw_survey_event_callback(_adapter *adapter, u8 *pbuf)
WLAN_BSSID_EX *pnetwork;
struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
- _func_enter_;
pnetwork = (WLAN_BSSID_EX *)pbuf;
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("rtw_survey_event_callback, ssid=%s\n", pnetwork->Ssid.Ssid));
#ifdef CONFIG_RTL8712
/* endian_convert */
@@ -1224,7 +1233,6 @@ void rtw_survey_event_callback(_adapter *adapter, u8 *pbuf)
len = get_WLAN_BSSID_EX_sz(pnetwork);
if (len > (sizeof(WLAN_BSSID_EX))) {
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("\n ****rtw_survey_event_callback: return a wrong bss ***\n"));
return;
}
@@ -1233,14 +1241,13 @@ void rtw_survey_event_callback(_adapter *adapter, u8 *pbuf)
/* update IBSS_network 's timestamp */
if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) == _TRUE) {
- /* RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,"rtw_survey_event_callback : WIFI_ADHOC_MASTER_STATE \n\n"); */
if (_rtw_memcmp(&(pmlmepriv->cur_network.network.MacAddress), pnetwork->MacAddress, ETH_ALEN)) {
struct wlan_network *ibss_wlan = NULL;
_irqL irqL;
_rtw_memcpy(pmlmepriv->cur_network.network.IEs, pnetwork->IEs, 8);
_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
- ibss_wlan = rtw_find_network(&pmlmepriv->scanned_queue, pnetwork->MacAddress);
+ ibss_wlan = _rtw_find_network(&pmlmepriv->scanned_queue, pnetwork->MacAddress);
if (ibss_wlan) {
_rtw_memcpy(ibss_wlan->network.IEs , pnetwork->IEs, 8);
_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
@@ -1261,7 +1268,6 @@ void rtw_survey_event_callback(_adapter *adapter, u8 *pbuf)
_exit_critical_bh(&pmlmepriv->lock, &irqL);
- _func_exit_;
return;
}
@@ -1269,14 +1275,16 @@ void rtw_survey_event_callback(_adapter *adapter, u8 *pbuf)
void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf)
{
_irqL irqL;
- u8 timer_cancelled;
+ struct sitesurvey_parm parm;
struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
+#ifdef CONFIG_RTW_80211R
+ struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
+#endif
#ifdef CONFIG_MLME_EXT
mlmeext_surveydone_event_callback(adapter);
#endif
- _func_enter_;
_enter_critical_bh(&pmlmepriv->lock, &irqL);
if (pmlmepriv->wps_probe_req_ie) {
@@ -1286,7 +1294,6 @@ void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf)
pmlmepriv->wps_probe_req_ie = NULL;
}
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("rtw_surveydone_event_callback: fw_state:%x\n\n", get_fwstate(pmlmepriv)));
if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _FALSE) {
RTW_INFO(FUNC_ADPT_FMT" fw_state:0x%x\n", FUNC_ADPT_ARG(adapter), get_fwstate(pmlmepriv));
@@ -1296,7 +1303,7 @@ void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf)
_clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY);
_exit_critical_bh(&pmlmepriv->lock, &irqL);
- _cancel_timer(&pmlmepriv->scan_to_timer, &timer_cancelled);
+ _cancel_timer_ex(&pmlmepriv->scan_to_timer);
_enter_critical_bh(&pmlmepriv->lock, &irqL);
@@ -1318,7 +1325,6 @@ void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf)
/* pmlmepriv->fw_state ^= _FW_UNDER_SURVEY; */ /* because don't set assoc_timer */
_clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY);
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("switching to adhoc master\n"));
_rtw_memset(&pdev_network->Ssid, 0, sizeof(NDIS_802_11_SSID));
_rtw_memcpy(&pdev_network->Ssid, &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID));
@@ -1330,7 +1336,7 @@ void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf)
init_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
if (rtw_create_ibss_cmd(adapter, 0) != _SUCCESS)
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("Error=>rtw_create_ibss_cmd status FAIL\n"));
+ RTW_ERR("rtw_create_ibss_cmd FAIL\n");
pmlmepriv->to_join = _FALSE;
}
@@ -1349,8 +1355,13 @@ void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf)
RTW_INFO("try_to_join, but select scanning queue fail, to_roam:%d\n", rtw_to_roam(adapter));
if (rtw_to_roam(adapter) != 0) {
+
+ rtw_init_sitesurvey_parm(adapter, &parm);
+ _rtw_memcpy(&parm.ssid[0], &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID));
+ parm.ssid_num = 1;
+
if (rtw_dec_to_roam(adapter) == 0
- || _SUCCESS != rtw_sitesurvey_cmd(adapter, &pmlmepriv->assoc_ssid, 1, NULL, 0)
+ || _SUCCESS != rtw_sitesurvey_cmd(adapter, &parm)
) {
rtw_set_to_roam(adapter, 0);
#ifdef CONFIG_INTEL_WIDI
@@ -1374,8 +1385,13 @@ void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf)
if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)
&& check_fwstate(pmlmepriv, _FW_LINKED)) {
if (rtw_select_roaming_candidate(pmlmepriv) == _SUCCESS) {
+#ifdef CONFIG_RTW_80211R
+ rtw_ft_start_roam(adapter,
+ (u8 *)pmlmepriv->roam_network->network.MacAddress);
+#else
receive_disconnect(adapter, pmlmepriv->cur_network.network.MacAddress
, WLAN_REASON_ACTIVE_ROAM, _FALSE);
+#endif
}
}
}
@@ -1410,11 +1426,25 @@ void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf)
#endif /* CONFIG_IOCTL_CFG80211 */
rtw_indicate_scan_done(adapter, _FALSE);
-#ifdef CONFIG_CONCURRENT_MODE
- rtw_mi_buddy_indicate_scan_done(adapter, _FALSE);/*scanning_via_buddy_intf*/
+
+#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_IOCTL_CFG80211)
+ rtw_cfg80211_indicate_scan_done_for_buddy(adapter, _FALSE);
#endif
- _func_exit_;
+#ifdef CONFIG_RTW_MESH
+ #if CONFIG_RTW_MESH_OFFCH_CAND
+ if (rtw_mesh_offch_candidate_accepted(adapter)) {
+ u8 ch;
+
+ ch = rtw_mesh_select_operating_ch(adapter);
+ if (ch && pmlmepriv->cur_network.network.Configuration.DSConfig != ch) {
+ /* trigger channel switch with bw specified by upper layer */
+ rtw_change_bss_chbw_cmd(adapter, RTW_CMDF_DIRECTLY, ch, adapter->mlmepriv.ori_bw, -1);
+ issue_probereq_ex(adapter, &pmlmepriv->cur_network.network.mesh_id, NULL, 0, 0, 0, 0);
+ }
+ }
+ #endif
+#endif /* CONFIG_RTW_MESH */
}
void rtw_dummy_event_callback(_adapter *adapter , u8 *pbuf)
@@ -1434,9 +1464,7 @@ static void free_scanqueue(struct mlme_priv *pmlmepriv)
_queue *scan_queue = &pmlmepriv->scanned_queue;
_list *plist, *phead, *ptemp;
- _func_enter_;
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_notice_, ("+free_scanqueue\n"));
_enter_critical_bh(&scan_queue->lock, &irqL0);
_enter_critical_bh(&free_queue->lock, &irqL);
@@ -1454,16 +1482,19 @@ static void free_scanqueue(struct mlme_priv *pmlmepriv)
_exit_critical_bh(&free_queue->lock, &irqL);
_exit_critical_bh(&scan_queue->lock, &irqL0);
- _func_exit_;
}
-void rtw_reset_rx_info(struct debug_priv *pdbgpriv)
+void rtw_reset_rx_info(_adapter *adapter)
{
- pdbgpriv->dbg_rx_ampdu_drop_count = 0;
- pdbgpriv->dbg_rx_ampdu_forced_indicate_count = 0;
- pdbgpriv->dbg_rx_ampdu_loss_count = 0;
- pdbgpriv->dbg_rx_dup_mgt_frame_drop_count = 0;
- pdbgpriv->dbg_rx_ampdu_window_shift_cnt = 0;
+ struct recv_priv *precvpriv = &adapter->recvpriv;
+
+ precvpriv->dbg_rx_ampdu_drop_count = 0;
+ precvpriv->dbg_rx_ampdu_forced_indicate_count = 0;
+ precvpriv->dbg_rx_ampdu_loss_count = 0;
+ precvpriv->dbg_rx_dup_mgt_frame_drop_count = 0;
+ precvpriv->dbg_rx_ampdu_window_shift_cnt = 0;
+ precvpriv->dbg_rx_drop_count = 0;
+ precvpriv->dbg_rx_conflic_mac_addr_cnt = 0;
}
/*
@@ -1476,18 +1507,14 @@ void rtw_free_assoc_resources(_adapter *adapter, int lock_scanned_queue)
struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
struct sta_priv *pstapriv = &adapter->stapriv;
struct wlan_network *tgt_network = &pmlmepriv->cur_network;
- struct dvobj_priv *psdpriv = adapter->dvobj;
- struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
#ifdef CONFIG_TDLS
struct tdls_info *ptdlsinfo = &adapter->tdlsinfo;
#endif /* CONFIG_TDLS */
- _func_enter_;
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_notice_, ("+rtw_free_assoc_resources\n"));
- RTW_INFO("%s-"ADPT_FMT" tgt_network MacAddress=" MAC_FMT"ssid=%s\n",
+ RTW_INFO("%s-"ADPT_FMT" tgt_network MacAddress=" MAC_FMT" ssid=%s\n",
__func__, ADPT_ARG(adapter), MAC_ARG(tgt_network->network.MacAddress), tgt_network->network.Ssid.Ssid);
if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
@@ -1496,18 +1523,15 @@ void rtw_free_assoc_resources(_adapter *adapter, int lock_scanned_queue)
psta = rtw_get_stainfo(&adapter->stapriv, tgt_network->network.MacAddress);
#ifdef CONFIG_TDLS
- if (ptdlsinfo->link_established == _TRUE) {
+ rtw_free_all_tdls_sta(adapter, _TRUE);
+ rtw_reset_tdls_info(adapter);
+
+ if (ptdlsinfo->link_established == _TRUE)
rtw_tdls_cmd(adapter, NULL, TDLS_RS_RCR);
- rtw_reset_tdls_info(adapter);
- rtw_free_all_stainfo(adapter);
- /* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */
- } else
#endif /* CONFIG_TDLS */
- {
- /* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */
- rtw_free_stainfo(adapter, psta);
- }
+ /* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */
+ rtw_free_stainfo(adapter, psta);
/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */
}
@@ -1559,9 +1583,8 @@ void rtw_free_assoc_resources(_adapter *adapter, int lock_scanned_queue)
adapter->securitypriv.key_mask = 0;
- rtw_reset_rx_info(pdbgpriv);
+ rtw_reset_rx_info(adapter);
- _func_exit_;
}
@@ -1573,9 +1596,7 @@ void rtw_indicate_connect(_adapter *padapter)
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
- _func_enter_;
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("+rtw_indicate_connect\n"));
pmlmepriv->to_join = _FALSE;
@@ -1585,16 +1606,7 @@ void rtw_indicate_connect(_adapter *padapter)
rtw_led_control(padapter, LED_CTL_LINK);
-
-#ifdef CONFIG_DRVEXT_MODULE
- if (padapter->drvextpriv.enable_wpa)
- indicate_l2_connect(padapter);
- else
-#endif
- {
- rtw_os_indicate_connect(padapter);
- }
-
+ rtw_os_indicate_connect(padapter);
}
rtw_set_to_roam(padapter, 0);
@@ -1605,12 +1617,10 @@ void rtw_indicate_connect(_adapter *padapter)
RTW_INFO("change to widi listen\n");
}
#endif /* CONFIG_INTEL_WIDI */
- if (!check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE))
+ if (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter))
rtw_mi_set_scan_deny(padapter, 3000);
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("-rtw_indicate_connect: fw_state=0x%08x\n", get_fwstate(pmlmepriv)));
- _func_exit_;
}
@@ -1628,9 +1638,7 @@ void rtw_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally_generate
u8 *wps_ie = NULL;
uint wpsie_len = 0;
- _func_enter_;
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("+rtw_indicate_disconnect\n"));
_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING | WIFI_UNDER_WPS);
@@ -1658,7 +1666,7 @@ void rtw_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally_generate
#ifdef CONFIG_WAPI_SUPPORT
psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress);
if (check_fwstate(pmlmepriv, WIFI_STATION_STATE))
- rtw_wapi_return_one_sta_info(padapter, psta->hwaddr);
+ rtw_wapi_return_one_sta_info(padapter, psta->cmn.mac_addr);
else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) ||
check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE))
rtw_wapi_return_all_sta_info(padapter);
@@ -1692,7 +1700,6 @@ void rtw_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally_generate
beamforming_wk_cmd(padapter, BEAMFORMING_CTRL_LEAVE, cur_network->MacAddress, ETH_ALEN, 1);
#endif /*CONFIG_BEAMFORMING*/
- _func_exit_;
}
inline void rtw_indicate_scan_done(_adapter *padapter, bool aborted)
@@ -1710,7 +1717,7 @@ inline void rtw_indicate_scan_done(_adapter *padapter, bool aborted)
pwrpriv = adapter_to_pwrctl(padapter);
rtw_set_ips_deny(padapter, 0);
#ifdef CONFIG_IPS_CHECK_IN_WD
- _set_timer(&padapter->mlmepriv.dynamic_chk_timer, 1);
+ _set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 1);
#else /* !CONFIG_IPS_CHECK_IN_WD */
_rtw_set_pwr_state_check_timer(pwrpriv, 1);
#endif /* !CONFIG_IPS_CHECK_IN_WD */
@@ -1720,7 +1727,7 @@ inline void rtw_indicate_scan_done(_adapter *padapter, bool aborted)
static u32 _rtw_wait_scan_done(_adapter *adapter, u8 abort, u32 timeout_ms)
{
- u32 start;
+ systime start;
u32 pass_ms;
struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
@@ -1761,17 +1768,11 @@ static u32 _rtw_wait_scan_done(_adapter *adapter, u8 abort, u32 timeout_ms)
void rtw_scan_wait_completed(_adapter *adapter)
{
- u32 scan_to = SCANNING_TIMEOUT;
-
-#ifdef CONFIG_SCAN_BACKOP
- if (IsSupported5G(adapter->registrypriv.wireless_mode)
- && IsSupported24G(adapter->registrypriv.wireless_mode)) /*dual band*/
- scan_to = CONC_SCANNING_TIMEOUT_DUAL_BAND;
- else /*single band*/
- scan_to = CONC_SCANNING_TIMEOUT_SINGLE_BAND;
-#endif /* CONFIG_SCAN_BACKOP */
+ struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
+ struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
+ struct ss_res *ss = &pmlmeext->sitesurvey_res;
- _rtw_wait_scan_done(adapter, _FALSE, scan_to);
+ _rtw_wait_scan_done(adapter, _FALSE, ss->scan_timeout_ms);
}
u32 rtw_scan_abort_timeout(_adapter *adapter, u32 timeout_ms)
@@ -1793,10 +1794,59 @@ void rtw_scan_abort(_adapter *adapter)
rtw_scan_abort_timeout(adapter, 200);
}
+static u32 _rtw_wait_join_done(_adapter *adapter, u8 abort, u32 timeout_ms)
+{
+ systime start;
+ u32 pass_ms;
+ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
+ struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
+
+ start = rtw_get_current_time();
+
+ pmlmeext->join_abort = abort;
+ if (abort)
+ set_link_timer(pmlmeext, 1);
+
+ while (rtw_get_passing_time_ms(start) <= timeout_ms
+ && (check_fwstate(pmlmepriv, _FW_UNDER_LINKING)
+ #ifdef CONFIG_IOCTL_CFG80211
+ || rtw_cfg80211_is_connect_requested(adapter)
+ #endif
+ )
+ ) {
+ if (RTW_CANNOT_RUN(adapter))
+ break;
+
+ RTW_INFO(FUNC_ADPT_FMT" linking...\n", FUNC_ADPT_ARG(adapter));
+ rtw_msleep_os(20);
+ }
+
+ if (abort) {
+ if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING)
+ #ifdef CONFIG_IOCTL_CFG80211
+ || rtw_cfg80211_is_connect_requested(adapter)
+ #endif
+ ) {
+ if (!RTW_CANNOT_RUN(adapter))
+ RTW_INFO(FUNC_ADPT_FMT" waiting for join_abort time out!\n", FUNC_ADPT_ARG(adapter));
+ }
+ }
+
+ pmlmeext->join_abort = 0;
+ pass_ms = rtw_get_passing_time_ms(start);
+
+ return pass_ms;
+}
+
+u32 rtw_join_abort_timeout(_adapter *adapter, u32 timeout_ms)
+{
+ return _rtw_wait_join_done(adapter, _TRUE, timeout_ms);
+}
+
static struct sta_info *rtw_joinbss_update_stainfo(_adapter *padapter, struct wlan_network *pnetwork)
{
int i;
- struct sta_info *bmc_sta, *psta = NULL;
+ struct sta_info *psta = NULL;
struct recv_reorder_ctrl *preorder_ctrl;
struct sta_priv *pstapriv = &padapter->stapriv;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
@@ -1808,54 +1858,51 @@ static struct sta_info *rtw_joinbss_update_stainfo(_adapter *padapter, struct wl
if (psta) { /* update ptarget_sta */
RTW_INFO("%s\n", __FUNCTION__);
- psta->aid = pnetwork->join_res;
-
-#if 0 /* alloc macid when call rtw_alloc_stainfo(), and release macid when call rtw_free_stainfo() */
-#ifdef CONFIG_CONCURRENT_MODE
-
- if (PRIMARY_ADAPTER == padapter->adapter_type)
- psta->mac_id = 0;
- else
- psta->mac_id = 2;
-#else
- psta->mac_id = 0;
-#endif
-#endif /* removed */
+ psta->cmn.aid = pnetwork->join_res;
update_sta_info(padapter, psta);
/* update station supportRate */
psta->bssratelen = rtw_get_rateset_len(pnetwork->network.SupportedRates);
_rtw_memcpy(psta->bssrateset, pnetwork->network.SupportedRates, psta->bssratelen);
- rtw_hal_update_sta_rate_mask(padapter, psta);
+ rtw_hal_update_sta_ra_info(padapter, psta);
psta->wireless_mode = pmlmeext->cur_wireless_mode;
- psta->raid = rtw_hal_networktype_to_raid(padapter, psta);
-
+ rtw_hal_update_sta_wset(padapter, psta);
/* sta mode */
rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _TRUE);
/* security related */
+#ifdef CONFIG_RTW_80211R
+ if ((padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)
+ && (psta->ft_pairwise_key_installed == _FALSE)) {
+#else
if (padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) {
+#endif
+ u8 *ie;
+ sint ie_len;
+ u8 mfp_opt = MFP_NO;
+
padapter->securitypriv.binstallGrpkey = _FALSE;
padapter->securitypriv.busetkipkey = _FALSE;
padapter->securitypriv.bgrpkey_handshake = _FALSE;
+ ie = rtw_get_ie(pnetwork->network.IEs + _BEACON_IE_OFFSET_, WLAN_EID_RSN
+ , &ie_len, (pnetwork->network.IELength - _BEACON_IE_OFFSET_));
+ if (ie && ie_len > 0
+ && rtw_parse_wpa2_ie(ie, ie_len + 2, NULL, NULL, NULL, &mfp_opt) == _SUCCESS
+ ) {
+ if (padapter->securitypriv.mfp_opt >= MFP_OPTIONAL && mfp_opt >= MFP_OPTIONAL)
+ psta->flags |= WLAN_STA_MFP;
+ }
+
psta->ieee8021x_blocked = _TRUE;
psta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm;
_rtw_memset((u8 *)&psta->dot118021x_UncstKey, 0, sizeof(union Keytype));
-
_rtw_memset((u8 *)&psta->dot11tkiprxmickey, 0, sizeof(union Keytype));
_rtw_memset((u8 *)&psta->dot11tkiptxmickey, 0, sizeof(union Keytype));
-
- _rtw_memset((u8 *)&psta->dot11txpn, 0, sizeof(union pn48));
- psta->dot11txpn.val = psta->dot11txpn.val + 1;
-#ifdef CONFIG_IEEE80211W
- _rtw_memset((u8 *)&psta->dot11wtxpn, 0, sizeof(union pn48));
-#endif /* CONFIG_IEEE80211W */
- _rtw_memset((u8 *)&psta->dot11rxpn, 0, sizeof(union pn48));
}
/* Commented by Albert 2012/07/21 */
@@ -1867,7 +1914,7 @@ static struct sta_info *rtw_joinbss_update_stainfo(_adapter *padapter, struct wl
}
- /* for A-MPDU Rx reordering buffer control for bmc_sta & sta_info */
+ /* for A-MPDU Rx reordering buffer control for sta_info */
/* if A-MPDU Rx is enabled, reseting rx_ordering_ctrl wstart_b(indicate_seq) to default value=0xffff */
/* todo: check if AP can send A-MPDU packets */
for (i = 0; i < 16 ; i++) {
@@ -1875,33 +1922,19 @@ static struct sta_info *rtw_joinbss_update_stainfo(_adapter *padapter, struct wl
preorder_ctrl = &psta->recvreorder_ctrl[i];
preorder_ctrl->enable = _FALSE;
preorder_ctrl->indicate_seq = 0xffff;
-#ifdef DBG_RX_SEQ
- RTW_INFO("DBG_RX_SEQ %s:%d indicate_seq:%u\n", __FUNCTION__, __LINE__,
- preorder_ctrl->indicate_seq);
-#endif
+ #ifdef DBG_RX_SEQ
+ RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_CLEAR indicate_seq:%u\n"
+ , FUNC_ADPT_ARG(padapter), i, preorder_ctrl->indicate_seq);
+ #endif
preorder_ctrl->wend_b = 0xffff;
preorder_ctrl->wsize_b = 64;/* max_ampdu_sz; */ /* ex. 32(kbytes) -> wsize_b=32 */
preorder_ctrl->ampdu_size = RX_AMPDU_SIZE_INVALID;
}
+ }
-
- bmc_sta = rtw_get_bcmc_stainfo(padapter);
- if (bmc_sta) {
- for (i = 0; i < 16 ; i++) {
- /* preorder_ctrl = &precvpriv->recvreorder_ctrl[i]; */
- preorder_ctrl = &bmc_sta->recvreorder_ctrl[i];
- preorder_ctrl->enable = _FALSE;
- preorder_ctrl->indicate_seq = 0xffff;
-#ifdef DBG_RX_SEQ
- RTW_INFO("DBG_RX_SEQ %s:%d indicate_seq:%u\n", __FUNCTION__, __LINE__,
- preorder_ctrl->indicate_seq);
+#ifdef CONFIG_RTW_80211K
+ _rtw_memcpy(&psta->rm_en_cap, pnetwork->network.PhyInfo.rm_en_cap, 5);
#endif
- preorder_ctrl->wend_b = 0xffff;
- preorder_ctrl->wsize_b = 64;/* max_ampdu_sz; */ /* ex. 32(kbytes) -> wsize_b=32 */
- preorder_ctrl->ampdu_size = RX_AMPDU_SIZE_INVALID;
- }
- }
- }
return psta;
@@ -1916,8 +1949,6 @@ static void rtw_joinbss_update_network(_adapter *padapter, struct wlan_network *
RTW_INFO("%s\n", __FUNCTION__);
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("\nfw_state:%x, BSSID:"MAC_FMT"\n"
- , get_fwstate(pmlmepriv), MAC_ARG(pnetwork->network.MacAddress)));
/* why not use ptarget_wlan?? */
@@ -1968,7 +1999,6 @@ static void rtw_joinbss_update_network(_adapter *padapter, struct wlan_network *
default:
/*pmlmepriv->fw_state = WIFI_NULL_STATE;*/
init_fwstate(pmlmepriv, WIFI_NULL_STATE);
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("Invalid network_mode\n"));
break;
}
@@ -1992,7 +2022,6 @@ void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf)
{
_irqL irqL, irqL2;
static u8 retry = 0;
- u8 timer_cancelled;
struct sta_info *ptarget_sta = NULL, *pcur_sta = NULL;
struct sta_priv *pstapriv = &adapter->stapriv;
struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
@@ -2001,7 +2030,6 @@ void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf)
struct wlan_network *pcur_wlan = NULL, *ptarget_wlan = NULL;
unsigned int the_same_macaddr = _FALSE;
- _func_enter_;
#ifdef CONFIG_RTL8712
/* endian_convert */
@@ -2024,21 +2052,15 @@ void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf)
pnetwork->network.IELength = le32_to_cpu(pnetwork->network.IELength);
#endif
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("joinbss event call back received with res=%d\n", pnetwork->join_res));
rtw_get_encrypt_decrypt_from_registrypriv(adapter);
- if (pmlmepriv->assoc_ssid.SsidLength == 0)
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("@@@@@ joinbss event call back for Any SSid\n"));
- else
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("@@@@@ rtw_joinbss_event_callback for SSid:%s\n", pmlmepriv->assoc_ssid.Ssid));
the_same_macaddr = _rtw_memcmp(pnetwork->network.MacAddress, cur_network->network.MacAddress, ETH_ALEN);
pnetwork->network.Length = get_WLAN_BSSID_EX_sz(&pnetwork->network);
if (pnetwork->network.Length > sizeof(WLAN_BSSID_EX)) {
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("\n\n ***joinbss_evt_callback return a wrong bss ***\n\n"));
goto ignore_joinbss_callback;
}
@@ -2047,7 +2069,6 @@ void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf)
pmlmepriv->LinkDetectInfo.TrafficTransitionCount = 0;
pmlmepriv->LinkDetectInfo.LowPowerTransitionCount = 0;
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("\n rtw_joinbss_event_callback !! _enter_critical\n"));
if (pnetwork->join_res > 0) {
_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
@@ -2056,9 +2077,9 @@ void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf)
/* s1. find ptarget_wlan */
if (check_fwstate(pmlmepriv, _FW_LINKED)) {
if (the_same_macaddr == _TRUE)
- ptarget_wlan = rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress);
+ ptarget_wlan = _rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress);
else {
- pcur_wlan = rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress);
+ pcur_wlan = _rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress);
if (pcur_wlan)
pcur_wlan->fixed = _FALSE;
@@ -2069,7 +2090,7 @@ void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf)
/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); */
}
- ptarget_wlan = rtw_find_network(&pmlmepriv->scanned_queue, pnetwork->network.MacAddress);
+ ptarget_wlan = _rtw_find_network(&pmlmepriv->scanned_queue, pnetwork->network.MacAddress);
if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) {
if (ptarget_wlan)
ptarget_wlan->fixed = _TRUE;
@@ -2111,12 +2132,10 @@ void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf)
}
/* s5. Cancle assoc_timer */
- _cancel_timer(&pmlmepriv->assoc_timer, &timer_cancelled);
+ _cancel_timer_ex(&pmlmepriv->assoc_timer);
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("Cancle assoc_timer\n"));
} else {
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("rtw_joinbss_event_callback err: fw_state:%x", get_fwstate(pmlmepriv)));
_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
goto ignore_joinbss_callback;
}
@@ -2130,7 +2149,6 @@ void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf)
/* rtw_free_assoc_resources(adapter, 1); */
if ((check_fwstate(pmlmepriv, _FW_UNDER_LINKING)) == _TRUE) {
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("fail! clear _FW_UNDER_LINKING ^^^fw_state=%x\n", get_fwstate(pmlmepriv)));
_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
}
@@ -2140,7 +2158,6 @@ void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf)
res = _FAIL;
if (retry < 2) {
res = rtw_select_and_join_from_scanned_queue(pmlmepriv);
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("rtw_select_and_join_from_scanned_queue again! res:%d\n", res));
}
if (res == _SUCCESS) {
@@ -2151,7 +2168,6 @@ void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf)
_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
rtw_indicate_connect(adapter);
} else {
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("Set Assoc_Timer = 1; can't find match ssid in scanned_q\n"));
#endif
_set_timer(&pmlmepriv->assoc_timer, 1);
@@ -2166,20 +2182,17 @@ void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf)
ignore_joinbss_callback:
_exit_critical_bh(&pmlmepriv->lock, &irqL);
- _func_exit_;
}
void rtw_joinbss_event_callback(_adapter *adapter, u8 *pbuf)
{
struct wlan_network *pnetwork = (struct wlan_network *)pbuf;
- _func_enter_;
mlmeext_joinbss_event_callback(adapter, pnetwork->join_res);
rtw_mi_os_xmit_schedule(adapter);
- _func_exit_;
}
void rtw_sta_media_status_rpt(_adapter *adapter, struct sta_info *sta, bool connected)
@@ -2196,21 +2209,21 @@ void rtw_sta_media_status_rpt(_adapter *adapter, struct sta_info *sta, bool conn
return;
}
- if (sta->mac_id >= macid_ctl->num) {
+ if (sta->cmn.mac_id >= macid_ctl->num) {
RTW_PRINT(FUNC_ADPT_FMT" invalid macid:%u\n"
- , FUNC_ADPT_ARG(adapter), sta->mac_id);
+ , FUNC_ADPT_ARG(adapter), sta->cmn.mac_id);
rtw_warn_on(1);
return;
}
- if (!rtw_macid_is_used(macid_ctl, sta->mac_id)) {
+ if (!rtw_macid_is_used(macid_ctl, sta->cmn.mac_id)) {
RTW_PRINT(FUNC_ADPT_FMT" macid:%u not is used, set connected to 0\n"
- , FUNC_ADPT_ARG(adapter), sta->mac_id);
+ , FUNC_ADPT_ARG(adapter), sta->cmn.mac_id);
connected = 0;
rtw_warn_on(1);
}
- if (connected && !rtw_macid_is_bmc(macid_ctl, sta->mac_id)) {
+ if (connected && !rtw_macid_is_bmc(macid_ctl, sta->cmn.mac_id)) {
miracast_enabled = STA_OP_WFD_MODE(sta) != 0 && is_miracast_enabled(adapter);
miracast_sink = miracast_enabled && (STA_OP_WFD_MODE(sta) & MIRACAST_SINK);
@@ -2219,39 +2232,41 @@ void rtw_sta_media_status_rpt(_adapter *adapter, struct sta_info *sta, bool conn
role = H2C_MSR_ROLE_TDLS;
else
#endif
- if (MLME_IS_STA(adapter)) {
- if (MLME_IS_GC(adapter))
- role = H2C_MSR_ROLE_GO;
- else
- role = H2C_MSR_ROLE_AP;
- } else if (MLME_IS_AP(adapter)) {
- if (MLME_IS_GO(adapter))
- role = H2C_MSR_ROLE_GC;
- else
- role = H2C_MSR_ROLE_STA;
- } else if (MLME_IS_ADHOC(adapter) || MLME_IS_ADHOC_MASTER(adapter))
- role = H2C_MSR_ROLE_ADHOC;
+ if (MLME_IS_STA(adapter)) {
+ if (MLME_IS_GC(adapter))
+ role = H2C_MSR_ROLE_GO;
+ else
+ role = H2C_MSR_ROLE_AP;
+ } else if (MLME_IS_AP(adapter)) {
+ if (MLME_IS_GO(adapter))
+ role = H2C_MSR_ROLE_GC;
+ else
+ role = H2C_MSR_ROLE_STA;
+ } else if (MLME_IS_ADHOC(adapter) || MLME_IS_ADHOC_MASTER(adapter))
+ role = H2C_MSR_ROLE_ADHOC;
+ else if (MLME_IS_MESH(adapter))
+ role = H2C_MSR_ROLE_MESH;
#ifdef CONFIG_WFD
if (role == H2C_MSR_ROLE_GC
- || role == H2C_MSR_ROLE_GO
- || role == H2C_MSR_ROLE_TDLS
- ) {
+ || role == H2C_MSR_ROLE_GO
+ || role == H2C_MSR_ROLE_TDLS
+ ) {
if (adapter->wfd_info.rtsp_ctrlport
- || adapter->wfd_info.tdls_rtsp_ctrlport
- || adapter->wfd_info.peer_rtsp_ctrlport)
+ || adapter->wfd_info.tdls_rtsp_ctrlport
+ || adapter->wfd_info.peer_rtsp_ctrlport)
rtw_wfd_st_switch(sta, 1);
}
#endif
}
rtw_hal_set_FwMediaStatusRpt_single_cmd(adapter
- , connected
- , miracast_enabled
- , miracast_sink
- , role
- , sta->mac_id
- );
+ , connected
+ , miracast_enabled
+ , miracast_sink
+ , role
+ , sta->cmn.mac_id
+ );
}
u8 rtw_sta_media_status_rpt_cmd(_adapter *adapter, struct sta_info *sta, bool connected)
@@ -2312,7 +2327,6 @@ void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf)
struct wlan_network *cur_network = &(pmlmepriv->cur_network);
struct wlan_network *ptarget_wlan = NULL;
- _func_enter_;
#if CONFIG_RTW_MACADDR_ACL
if (rtw_access_ctrl(adapter, pstassoc->macaddr) == _FALSE)
@@ -2320,7 +2334,7 @@ void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf)
#endif
#if defined(CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME)
- if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) {
+ if (MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)) {
psta = rtw_get_stainfo(&adapter->stapriv, pstassoc->macaddr);
if (psta) {
u8 *passoc_req = NULL;
@@ -2328,35 +2342,39 @@ void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf)
rtw_sta_media_status_rpt(adapter, psta, 1);
-#ifndef CONFIG_AUTO_AP_MODE
+#ifdef CONFIG_MCC_MODE
+ rtw_hal_mcc_update_macid_bitmap(adapter, psta->cmn.mac_id, _TRUE);
+#endif /* CONFIG_MCC_MODE */
+#ifndef CONFIG_AUTO_AP_MODE
ap_sta_info_defer_update(adapter, psta);
- /* report to upper layer */
- RTW_INFO("indicate_sta_assoc_event to upper layer - hostapd\n");
-#ifdef CONFIG_IOCTL_CFG80211
- _enter_critical_bh(&psta->lock, &irqL);
- if (psta->passoc_req && psta->assoc_req_len > 0) {
- passoc_req = rtw_zmalloc(psta->assoc_req_len);
- if (passoc_req) {
- assoc_req_len = psta->assoc_req_len;
- _rtw_memcpy(passoc_req, psta->passoc_req, assoc_req_len);
-
- rtw_mfree(psta->passoc_req , psta->assoc_req_len);
- psta->passoc_req = NULL;
- psta->assoc_req_len = 0;
+ if (!MLME_IS_MESH(adapter)) {
+ /* report to upper layer */
+ RTW_INFO("indicate_sta_assoc_event to upper layer - hostapd\n");
+ #ifdef CONFIG_IOCTL_CFG80211
+ _enter_critical_bh(&psta->lock, &irqL);
+ if (psta->passoc_req && psta->assoc_req_len > 0) {
+ passoc_req = rtw_zmalloc(psta->assoc_req_len);
+ if (passoc_req) {
+ assoc_req_len = psta->assoc_req_len;
+ _rtw_memcpy(passoc_req, psta->passoc_req, assoc_req_len);
+
+ rtw_mfree(psta->passoc_req , psta->assoc_req_len);
+ psta->passoc_req = NULL;
+ psta->assoc_req_len = 0;
+ }
}
- }
- _exit_critical_bh(&psta->lock, &irqL);
+ _exit_critical_bh(&psta->lock, &irqL);
- if (passoc_req && assoc_req_len > 0) {
- rtw_cfg80211_indicate_sta_assoc(adapter, passoc_req, assoc_req_len);
-
- rtw_mfree(passoc_req, assoc_req_len);
+ if (passoc_req && assoc_req_len > 0) {
+ rtw_cfg80211_indicate_sta_assoc(adapter, passoc_req, assoc_req_len);
+ rtw_mfree(passoc_req, assoc_req_len);
+ }
+ #else /* !CONFIG_IOCTL_CFG80211 */
+ rtw_indicate_sta_assoc_event(adapter, psta);
+ #endif /* !CONFIG_IOCTL_CFG80211 */
}
-#else /* !CONFIG_IOCTL_CFG80211 */
- rtw_indicate_sta_assoc_event(adapter, psta);
-#endif /* !CONFIG_IOCTL_CFG80211 */
#endif /* !CONFIG_AUTO_AP_MODE */
#ifdef CONFIG_BEAMFORMING
@@ -2364,8 +2382,6 @@ void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf)
#endif/*CONFIG_BEAMFORMING*/
if (is_wep_enc(adapter->securitypriv.dot11PrivacyAlgrthm))
rtw_ap_wep_pk_setting(adapter, psta);
-
- rtw_mi_update_iface_status(pmlmepriv, WIFI_AP_STATE);
}
goto exit;
}
@@ -2380,8 +2396,6 @@ void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf)
goto exit;
}
- rtw_hal_set_odm_var(adapter, HAL_ODM_STA_INFO, psta, _TRUE);
-
rtw_sta_media_status_rpt(adapter, psta, 1);
if (adapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)
@@ -2396,7 +2410,7 @@ void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf)
(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)) {
if (adapter->stapriv.asoc_sta_count == 2) {
_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
- ptarget_wlan = rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress);
+ ptarget_wlan = _rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress);
pmlmepriv->cur_network_scanned = ptarget_wlan;
if (ptarget_wlan)
ptarget_wlan->fixed = _TRUE;
@@ -2417,9 +2431,7 @@ void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf)
#endif
exit:
-
- _func_exit_;
-
+ return;
}
#ifdef CONFIG_IEEE80211W
@@ -2430,7 +2442,6 @@ void rtw_sta_timeout_event_callback(_adapter *adapter, u8 *pbuf)
struct stadel_event *pstadel = (struct stadel_event *)pbuf;
struct sta_priv *pstapriv = &adapter->stapriv;
- _func_enter_;
psta = rtw_get_stainfo(&adapter->stapriv, pstadel->macaddr);
@@ -2449,54 +2460,235 @@ void rtw_sta_timeout_event_callback(_adapter *adapter, u8 *pbuf)
}
- _func_exit_;
}
#endif /* CONFIG_IEEE80211W */
-void rtw_sta_mstatus_disc_rpt(_adapter *adapter, u8 mac_id)
+#ifdef CONFIG_RTW_80211R
+void rtw_ft_info_init(struct ft_roam_info *pft)
{
- struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl;
+ _rtw_memset(pft, 0, sizeof(struct ft_roam_info));
+ pft->ft_flags = 0
+ | RTW_FT_EN
+ | RTW_FT_OTD_EN
+#ifdef CONFIG_RTW_BTM_ROAM
+ | RTW_FT_BTM_ROAM
+#endif
+ ;
+ pft->ft_updated_bcn = _FALSE;
+}
+
+u8 rtw_ft_chk_roaming_candidate(
+ _adapter *padapter, struct wlan_network *competitor)
+{
+ u8 *pmdie;
+ u32 mdie_len = 0;
+ struct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam);
- RTW_INFO("%s "ADPT_FMT" - mac_id=%d\n", __func__, ADPT_ARG(adapter), mac_id);
+ if (!(pmdie = rtw_get_ie(&competitor->network.IEs[12],
+ _MDIE_, &mdie_len, competitor->network.IELength-12)))
+ return _FALSE;
- if (mac_id >= 0 && mac_id < macid_ctl->num) {
- rtw_hal_set_FwMediaStatusRpt_single_cmd(adapter, 0, 0, 0, 0, mac_id);
- /*
- * For safety, prevent from keeping macid sleep.
- * If we can sure all power mode enter/leave are paired,
- * this check can be removed.
- * Lucas@20131113
- */
- /* wakeup macid after disconnect. */
- /*if (MLME_IS_STA(adapter))*/
- rtw_hal_macid_wakeup(adapter, mac_id);
- } else {
- RTW_PRINT(FUNC_ADPT_FMT" invalid macid:%u\n"
- , FUNC_ADPT_ARG(adapter), mac_id);
- rtw_warn_on(1);
+ if (!_rtw_memcmp(&pft_roam->mdid, (pmdie+2), 2))
+ return _FALSE;
+
+ /*The candidate don't support over-the-DS*/
+ if (rtw_ft_valid_otd_candidate(padapter, pmdie)) {
+ RTW_INFO("FT: ignore the candidate("
+ MAC_FMT ") for over-the-DS\n",
+ MAC_ARG(competitor->network.MacAddress));
+ rtw_ft_clr_flags(padapter, RTW_FT_PEER_OTD_EN);
+ return _FALSE;
}
+
+ return _TRUE;
}
-void rtw_sta_mstatus_report(_adapter *adapter)
+
+void rtw_ft_update_stainfo(_adapter *padapter, WLAN_BSSID_EX *pnetwork)
{
- struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
- struct wlan_network *tgt_network = &pmlmepriv->cur_network;
- struct sta_info *psta = NULL;
+ struct sta_priv *pstapriv = &padapter->stapriv;
+ struct sta_info *psta = NULL;
- if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
- psta = rtw_get_stainfo(&adapter->stapriv, tgt_network->network.MacAddress);
- if (psta)
- rtw_sta_mstatus_disc_rpt(adapter, psta->mac_id);
- else {
- RTW_INFO("%s "ADPT_FMT" - mac_addr: "MAC_FMT" psta == NULL\n", __func__, ADPT_ARG(adapter), MAC_ARG(tgt_network->network.MacAddress));
- rtw_warn_on(1);
- }
+ psta = rtw_get_stainfo(pstapriv, pnetwork->MacAddress);
+ if (psta == NULL)
+ psta = rtw_alloc_stainfo(pstapriv, pnetwork->MacAddress);
+
+ if (padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) {
+
+ padapter->securitypriv.binstallGrpkey = _FALSE;
+ padapter->securitypriv.busetkipkey = _FALSE;
+ padapter->securitypriv.bgrpkey_handshake = _FALSE;
+
+ psta->ieee8021x_blocked = _TRUE;
+ psta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm;
+
+ _rtw_memset((u8 *)&psta->dot118021x_UncstKey, 0, sizeof(union Keytype));
+ _rtw_memset((u8 *)&psta->dot11tkiprxmickey, 0, sizeof(union Keytype));
+ _rtw_memset((u8 *)&psta->dot11tkiptxmickey, 0, sizeof(union Keytype));
}
+
}
-void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf)
+void rtw_ft_reassoc_event_callback(_adapter *padapter, u8 *pbuf)
{
- _irqL irqL, irqL2;
+ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+ struct stassoc_event *pstassoc = (struct stassoc_event *)pbuf;
+ struct ft_roam_info *pft_roam = &(pmlmepriv->ft_roam);
+ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
+ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+ WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)&(pmlmeinfo->network);
+ struct cfg80211_ft_event_params ft_evt_parms;
+ _irqL irqL;
+
+ _rtw_memset(&ft_evt_parms, 0, sizeof(ft_evt_parms));
+ rtw_ft_update_stainfo(padapter, pnetwork);
+ ft_evt_parms.ies_len = pft_roam->ft_event.ies_len;
+ ft_evt_parms.ies = rtw_zmalloc(ft_evt_parms.ies_len);
+ if (ft_evt_parms.ies)
+ _rtw_memcpy((void *)ft_evt_parms.ies, pft_roam->ft_event.ies, ft_evt_parms.ies_len);
+ else
+ goto err_2;
+
+ ft_evt_parms.target_ap = rtw_zmalloc(ETH_ALEN);
+ if (ft_evt_parms.target_ap)
+ _rtw_memcpy((void *)ft_evt_parms.target_ap, pstassoc->macaddr, ETH_ALEN);
+ else
+ goto err_1;
+
+ ft_evt_parms.ric_ies = pft_roam->ft_event.ric_ies;
+ ft_evt_parms.ric_ies_len = pft_roam->ft_event.ric_ies_len;
+
+ rtw_ft_lock_set_status(padapter, RTW_FT_AUTHENTICATED_STA, &irqL);
+ rtw_cfg80211_ft_event(padapter, &ft_evt_parms);
+ RTW_INFO("%s: to "MAC_FMT"\n", __func__, MAC_ARG(ft_evt_parms.target_ap));
+
+ rtw_mfree((u8 *)pft_roam->ft_event.target_ap, ETH_ALEN);
+err_1:
+ rtw_mfree((u8 *)ft_evt_parms.ies, ft_evt_parms.ies_len);
+err_2:
+ return;
+}
+#endif
+
+#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K)
+void rtw_roam_nb_info_init(_adapter *padapter)
+{
+ struct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info);
+
+ _rtw_memset(&pnb->nb_rpt, 0, sizeof(pnb->nb_rpt));
+ _rtw_memset(&pnb->nb_rpt_ch_list, 0, sizeof(pnb->nb_rpt_ch_list));
+ _rtw_memset(&pnb->roam_target_addr, 0, ETH_ALEN);
+ pnb->nb_rpt_valid = _FALSE;
+ pnb->nb_rpt_ch_list_num = 0;
+ pnb->preference_en = _FALSE;
+ pnb->nb_rpt_is_same = _TRUE;
+ pnb->last_nb_rpt_entries = 0;
+#ifdef CONFIG_RTW_WNM
+ rtw_init_timer(&pnb->roam_scan_timer,
+ padapter, rtw_wnm_roam_scan_hdl,
+ padapter);
+#endif
+}
+
+u8 rtw_roam_nb_scan_list_set(
+ _adapter *padapter, struct sitesurvey_parm *pparm)
+{
+ u8 ret = _FALSE;
+ u32 i;
+ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+ struct roam_nb_info *pnb = &(pmlmepriv->nb_info);
+
+ if (!rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE))
+ return ret;
+
+ if (!pmlmepriv->need_to_roam)
+ return ret;
+
+ if ((!pmlmepriv->nb_info.nb_rpt_valid) || (!pnb->nb_rpt_ch_list_num))
+ return ret;
+
+ if (!pparm)
+ return ret;
+
+ rtw_init_sitesurvey_parm(padapter, pparm);
+ if (rtw_roam_busy_scan(padapter, pnb)) {
+ pparm->ch_num = 1;
+ pparm->ch[pmlmepriv->ch_cnt].hw_value =
+ pnb->nb_rpt_ch_list[pmlmepriv->ch_cnt].hw_value;
+ pmlmepriv->ch_cnt++;
+ ret = _TRUE;
+ if (pmlmepriv->ch_cnt == pnb->nb_rpt_ch_list_num) {
+ pmlmepriv->nb_info.nb_rpt_valid = _FALSE;
+ pmlmepriv->ch_cnt = 0;
+ }
+ goto set_bssid_list;
+ }
+
+ pparm->ch_num = (pnb->nb_rpt_ch_list_num > RTW_CHANNEL_SCAN_AMOUNT)?
+ (RTW_CHANNEL_SCAN_AMOUNT):(pnb->nb_rpt_ch_list_num);
+ for (i=0; ich_num; i++) {
+ pparm->ch[i].hw_value = pnb->nb_rpt_ch_list[i].hw_value;
+ pparm->ch[i].flags = RTW_IEEE80211_CHAN_PASSIVE_SCAN;
+ }
+
+ pmlmepriv->nb_info.nb_rpt_valid = _FALSE;
+ pmlmepriv->ch_cnt = 0;
+ ret = _TRUE;
+
+set_bssid_list:
+ rtw_set_802_11_bssid_list_scan(padapter, pparm);
+ return ret;
+}
+#endif
+
+void rtw_sta_mstatus_disc_rpt(_adapter *adapter, u8 mac_id)
+{
+ struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl;
+
+ if (mac_id >= 0 && mac_id < macid_ctl->num) {
+ u8 id_is_shared = mac_id == RTW_DEFAULT_MGMT_MACID; /* TODO: real shared macid judgment */
+
+ RTW_INFO(FUNC_ADPT_FMT" - mac_id=%d%s\n", FUNC_ADPT_ARG(adapter)
+ , mac_id, id_is_shared ? " shared" : "");
+
+ if (!id_is_shared) {
+ rtw_hal_set_FwMediaStatusRpt_single_cmd(adapter, 0, 0, 0, 0, mac_id);
+ /*
+ * For safety, prevent from keeping macid sleep.
+ * If we can sure all power mode enter/leave are paired,
+ * this check can be removed.
+ * Lucas@20131113
+ */
+ /* wakeup macid after disconnect. */
+ /*if (MLME_IS_STA(adapter))*/
+ rtw_hal_macid_wakeup(adapter, mac_id);
+ }
+ } else {
+ RTW_PRINT(FUNC_ADPT_FMT" invalid macid:%u\n"
+ , FUNC_ADPT_ARG(adapter), mac_id);
+ rtw_warn_on(1);
+ }
+}
+void rtw_sta_mstatus_report(_adapter *adapter)
+{
+ struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
+ struct wlan_network *tgt_network = &pmlmepriv->cur_network;
+ struct sta_info *psta = NULL;
+
+ if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) && check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) {
+ psta = rtw_get_stainfo(&adapter->stapriv, tgt_network->network.MacAddress);
+ if (psta)
+ rtw_sta_mstatus_disc_rpt(adapter, psta->cmn.mac_id);
+ else {
+ RTW_INFO("%s "ADPT_FMT" - mac_addr: "MAC_FMT" psta == NULL\n", __func__, ADPT_ARG(adapter), MAC_ARG(tgt_network->network.MacAddress));
+ rtw_warn_on(1);
+ }
+ }
+}
+
+void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf)
+{
+ _irqL irqL, irqL2;
struct sta_info *psta;
struct wlan_network *pwlan = NULL;
@@ -2509,11 +2701,14 @@ void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf)
struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
- _func_enter_;
RTW_INFO("%s(mac_id=%d)=" MAC_FMT "\n", __func__, pstadel->mac_id, MAC_ARG(pstadel->macaddr));
rtw_sta_mstatus_disc_rpt(adapter, pstadel->mac_id);
+#ifdef CONFIG_MCC_MODE
+ rtw_hal_mcc_update_macid_bitmap(adapter, pstadel->mac_id, _FALSE);
+#endif /* CONFIG_MCC_MODE */
+
psta = rtw_get_stainfo(&adapter->stapriv, pstadel->macaddr);
if (psta == NULL) {
@@ -2524,8 +2719,10 @@ void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf)
if (psta)
rtw_wfd_st_switch(psta, 0);
- /* if(check_fwstate(pmlmepriv, WIFI_AP_STATE)) */
- if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {
+ if (MLME_IS_MESH(adapter))
+ return;
+
+ if (MLME_IS_AP(adapter)) {
#ifdef CONFIG_IOCTL_CFG80211
#ifdef COMPAT_KERNEL_RELEASE
@@ -2547,6 +2744,12 @@ void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf)
struct wlan_network *roam_target = NULL;
#ifdef CONFIG_LAYER2_ROAMING
+#ifdef CONFIG_RTW_80211R
+ if (rtw_ft_roam_expired(adapter, reason))
+ pmlmepriv->ft_roam.ft_roam_on_expired = _TRUE;
+ else
+ pmlmepriv->ft_roam.ft_roam_on_expired = _FALSE;
+#endif
if (adapter->registrypriv.wifi_spec == 1)
roam = _FALSE;
else if (reason == WLAN_REASON_EXPIRATION_CHK && rtw_chk_roam_flags(adapter, RTW_ROAM_ON_EXPIRED))
@@ -2576,7 +2779,7 @@ void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf)
_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
/* remove the network entry in scanned_queue */
- pwlan = rtw_find_network(&pmlmepriv->scanned_queue, tgt_network->network.MacAddress);
+ pwlan = _rtw_find_network(&pmlmepriv->scanned_queue, tgt_network->network.MacAddress);
if ((pwlan) && (!check_fwstate(pmlmepriv, WIFI_UNDER_WPS))) {
pwlan->fixed = _FALSE;
rtw_free_network_nolock(adapter, pwlan);
@@ -2603,8 +2806,8 @@ void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf)
/* rtw_indicate_disconnect(adapter); */ /* removed@20091105 */
_enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
/* free old ibss network */
- /* pwlan = rtw_find_network(&pmlmepriv->scanned_queue, pstadel->macaddr); */
- pwlan = rtw_find_network(&pmlmepriv->scanned_queue, tgt_network->network.MacAddress);
+ /* pwlan = _rtw_find_network(&pmlmepriv->scanned_queue, pstadel->macaddr); */
+ pwlan = _rtw_find_network(&pmlmepriv->scanned_queue, tgt_network->network.MacAddress);
if (pwlan) {
pwlan->fixed = _FALSE;
rtw_free_network_nolock(adapter, pwlan);
@@ -2629,7 +2832,7 @@ void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf)
}
if (rtw_create_ibss_cmd(adapter, 0) != _SUCCESS)
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("***Error=>stadel_event_callback: rtw_create_ibss_cmd status FAIL***\n"));
+ RTW_ERR("rtw_create_ibss_cmd FAIL\n");
}
@@ -2637,7 +2840,6 @@ void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf)
_exit_critical_bh(&pmlmepriv->lock, &irqL2);
- _func_exit_;
}
@@ -2648,36 +2850,31 @@ void rtw_cpwm_event_callback(PADAPTER padapter, u8 *pbuf)
struct reportpwrstate_parm *preportpwrstate;
#endif
- _func_enter_;
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("+rtw_cpwm_event_callback !!!\n"));
#ifdef CONFIG_LPS_LCLK
preportpwrstate = (struct reportpwrstate_parm *)pbuf;
preportpwrstate->state |= (u8)(adapter_to_pwrctl(padapter)->cpwm_tog + 0x80);
cpwm_int_hdl(padapter, preportpwrstate);
#endif
- _func_exit_;
}
void rtw_wmm_event_callback(PADAPTER padapter, u8 *pbuf)
{
- _func_enter_;
WMMOnAssocRsp(padapter);
- _func_exit_;
}
/*
-* _rtw_join_timeout_handler - Timeout/faliure handler for CMD JoinBss
-* @adapter: pointer to _adapter structure
+* rtw_join_timeout_handler - Timeout/failure handler for CMD JoinBss
*/
-void _rtw_join_timeout_handler(_adapter *adapter)
+void rtw_join_timeout_handler(void *ctx)
{
+ _adapter *adapter = (_adapter *)ctx;
_irqL irqL;
struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
@@ -2688,7 +2885,6 @@ void _rtw_join_timeout_handler(_adapter *adapter)
}
#endif
- _func_enter_;
RTW_INFO("%s, fw_state=%x\n", __FUNCTION__, get_fwstate(pmlmepriv));
@@ -2721,6 +2917,10 @@ void _rtw_join_timeout_handler(_adapter *adapter)
}
#endif /* CONFIG_INTEL_WIDI */
RTW_INFO("%s We've try roaming but fail\n", __FUNCTION__);
+#ifdef CONFIG_RTW_80211R
+ rtw_ft_clr_flags(adapter, RTW_FT_PEER_EN|RTW_FT_PEER_OTD_EN);
+ rtw_ft_reset_status(adapter);
+#endif
rtw_indicate_disconnect(adapter, 0, _FALSE);
break;
}
@@ -2747,7 +2947,6 @@ void _rtw_join_timeout_handler(_adapter *adapter)
#endif
- _func_exit_;
}
@@ -2755,8 +2954,9 @@ void _rtw_join_timeout_handler(_adapter *adapter)
* rtw_scan_timeout_handler - Timeout/Faliure handler for CMD SiteSurvey
* @adapter: pointer to _adapter structure
*/
-void rtw_scan_timeout_handler(_adapter *adapter)
+void rtw_scan_timeout_handler(void *ctx)
{
+ _adapter *adapter = (_adapter *)ctx;
_irqL irqL;
struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
RTW_INFO(FUNC_ADPT_FMT" fw_state=%x\n", FUNC_ADPT_ARG(adapter), get_fwstate(pmlmepriv));
@@ -2772,13 +2972,15 @@ void rtw_scan_timeout_handler(_adapter *adapter)
#endif /* CONFIG_IOCTL_CFG80211 */
rtw_indicate_scan_done(adapter, _TRUE);
-#ifdef CONFIG_CONCURRENT_MODE
- rtw_mi_buddy_indicate_scan_done(adapter, _TRUE);/*scanning_via_buddy_intf */
+
+#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_IOCTL_CFG80211)
+ rtw_cfg80211_indicate_scan_done_for_buddy(adapter, _TRUE);
#endif
}
void rtw_mlme_reset_auto_scan_int(_adapter *adapter, u8 *reason)
{
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
struct mlme_priv *mlme = &adapter->mlmepriv;
struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
@@ -2789,22 +2991,28 @@ void rtw_mlme_reset_auto_scan_int(_adapter *adapter, u8 *reason)
rtw_mi_get_ch_setting_union(adapter, &u_ch, NULL, NULL);
if (hal_chk_bw_cap(adapter, BW_CAP_40M)
- && is_client_associated_to_ap(adapter) == _TRUE
- && u_ch >= 1 && u_ch <= 14
- && adapter->registrypriv.wifi_spec
- /* TODO: AP Connected is 40MHz capability? */
- ) {
+ && is_client_associated_to_ap(adapter) == _TRUE
+ && u_ch >= 1 && u_ch <= 14
+ && adapter->registrypriv.wifi_spec
+ /* TODO: AP Connected is 40MHz capability? */
+ ) {
interval_ms = rtw_min(interval_ms, 60 * 1000);
*reason |= RTW_AUTO_SCAN_REASON_2040_BSS;
}
-#ifdef CONFIG_LAYER2_ROAMING
- if (rtw_chk_roam_flags(adapter, RTW_ROAM_ACTIVE)
- && is_client_associated_to_ap(adapter) == _TRUE
- ) {
- interval_ms = rtw_min(interval_ms, mlme->roam_scan_int_ms);
- *reason |= RTW_AUTO_SCAN_REASON_ROAM;
+
+#ifdef CONFIG_RTW_MESH
+ #if CONFIG_RTW_MESH_OFFCH_CAND
+ if (adapter->mesh_cfg.peer_sel_policy.offch_find_int_ms
+ && rtw_mesh_offch_candidate_accepted(adapter)
+ #ifdef CONFIG_DFS_MASTER
+ && (!rfctl->radar_detect_ch || (IS_CH_WAITING(rfctl) && !IS_UNDER_CAC(rfctl)))
+ #endif
+ ) {
+ interval_ms = rtw_min(interval_ms, adapter->mesh_cfg.peer_sel_policy.offch_find_int_ms);
+ *reason |= RTW_AUTO_SCAN_REASON_MESH_OFFCH_CAND;
}
-#endif
+ #endif
+#endif /* CONFIG_RTW_MESH */
exit:
if (interval_ms == 0xffffffff)
@@ -2816,25 +3024,10 @@ void rtw_mlme_reset_auto_scan_int(_adapter *adapter, u8 *reason)
void rtw_drv_scan_by_self(_adapter *padapter, u8 reason)
{
+ struct sitesurvey_parm parm;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
- struct rtw_ieee80211_channel ch_for_2040_bss[14] = {
- {1, RTW_IEEE80211_CHAN_PASSIVE_SCAN},
- {2, RTW_IEEE80211_CHAN_PASSIVE_SCAN},
- {3, RTW_IEEE80211_CHAN_PASSIVE_SCAN},
- {4, RTW_IEEE80211_CHAN_PASSIVE_SCAN},
- {5, RTW_IEEE80211_CHAN_PASSIVE_SCAN},
- {6, RTW_IEEE80211_CHAN_PASSIVE_SCAN},
- {7, RTW_IEEE80211_CHAN_PASSIVE_SCAN},
- {8, RTW_IEEE80211_CHAN_PASSIVE_SCAN},
- {9, RTW_IEEE80211_CHAN_PASSIVE_SCAN},
- {10, RTW_IEEE80211_CHAN_PASSIVE_SCAN},
- {11, RTW_IEEE80211_CHAN_PASSIVE_SCAN},
- {12, RTW_IEEE80211_CHAN_PASSIVE_SCAN},
- {13, RTW_IEEE80211_CHAN_PASSIVE_SCAN},
- {14, RTW_IEEE80211_CHAN_PASSIVE_SCAN},
- };
- struct rtw_ieee80211_channel *ch_sel = NULL;
- int ch_num = 0;
+ int i;
+
if (rtw_is_scan_deny(padapter))
goto exit;
@@ -2843,8 +3036,15 @@ void rtw_drv_scan_by_self(_adapter *padapter, u8 reason)
goto exit;
if (rtw_mi_busy_traffic_check(padapter, _FALSE)) {
- RTW_INFO(FUNC_ADPT_FMT" exit due to BusyTraffic\n", FUNC_ADPT_ARG(padapter));
- goto exit;
+#ifdef CONFIG_LAYER2_ROAMING
+ if (rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE) && pmlmepriv->need_to_roam == _TRUE) {
+ RTW_INFO("need to roam, don't care BusyTraffic\n");
+ } else
+#endif
+ {
+ RTW_INFO(FUNC_ADPT_FMT" exit BusyTraffic\n", FUNC_ADPT_ARG(padapter));
+ goto exit;
+ }
}
if (check_fwstate(pmlmepriv, WIFI_AP_STATE) && check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) {
RTW_INFO(FUNC_ADPT_FMT" WIFI_AP_STATE && WIFI_UNDER_WPS\n", FUNC_ADPT_ARG(padapter));
@@ -2866,11 +3066,23 @@ void rtw_drv_scan_by_self(_adapter *padapter, u8 reason)
/* only for 20/40 BSS */
if (reason == RTW_AUTO_SCAN_REASON_2040_BSS) {
- ch_sel = ch_for_2040_bss;
- ch_num = 14;
+ rtw_init_sitesurvey_parm(padapter, &parm);
+ for (i=0;i<14;i++) {
+ parm.ch[i].hw_value = i + 1;
+ parm.ch[i].flags = RTW_IEEE80211_CHAN_PASSIVE_SCAN;
+ }
+ parm.ch_num = 14;
+ rtw_set_802_11_bssid_list_scan(padapter, &parm);
+ goto exit;
}
- rtw_set_802_11_bssid_list_scan(padapter, NULL, 0, ch_sel, ch_num);
+#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K)
+ if ((reason == RTW_AUTO_SCAN_REASON_ROAM)
+ && (rtw_roam_nb_scan_list_set(padapter, &parm)))
+ goto exit;
+#endif
+
+ rtw_set_802_11_bssid_list_scan(padapter, NULL);
exit:
return;
}
@@ -2901,32 +3113,30 @@ static void rtw_auto_scan_handler(_adapter *padapter)
exit:
return;
}
+static u8 is_drv_in_lps(_adapter *adapter)
+{
+ u8 is_in_lps = _FALSE;
-void rtw_dynamic_check_timer_handlder(_adapter *adapter)
+ #ifdef CONFIG_LPS_LCLK_WD_TIMER /* to avoid leaving lps 32k frequently*/
+ if ((adapter_to_pwrctl(adapter)->bFwCurrentInPSMode == _TRUE)
+ #ifdef CONFIG_BT_COEXIST
+ && (rtw_btcoex_IsBtControlLps(adapter) == _FALSE)
+ #endif
+ )
+ is_in_lps = _TRUE;
+ #endif /* CONFIG_LPS_LCLK_WD_TIMER*/
+ return is_in_lps;
+}
+void rtw_iface_dynamic_check_timer_handlder(_adapter *adapter)
{
#ifdef CONFIG_AP_MODE
struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
#endif /* CONFIG_AP_MODE */
- struct registry_priv *pregistrypriv = &adapter->registrypriv;
-
- if (!adapter)
- return;
-
- if (!rtw_is_hw_init_completed(adapter))
- return;
-
- if (RTW_CANNOT_RUN(adapter))
- return;
if (adapter->net_closed == _TRUE)
return;
-
-#ifdef CONFIG_LPS_LCLK_WD_TIMER /* to avoid leaving lps 32k frequently*/
- if ((adapter_to_pwrctl(adapter)->bFwCurrentInPSMode == _TRUE)
-#ifdef CONFIG_BT_COEXIST
- && (rtw_btcoex_IsBtControlLps(adapter) == _FALSE)
-#endif
- ) {
+ #ifdef CONFIG_LPS_LCLK_WD_TIMER /* to avoid leaving lps 32k frequently*/
+ if (is_drv_in_lps(adapter)) {
u8 bEnterPS;
linked_status_chk(adapter, 1);
@@ -2938,23 +3148,24 @@ void rtw_dynamic_check_timer_handlder(_adapter *adapter)
} else {
/* call rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE, 1) in traffic_status_watchdog() */
}
-
- } else
-#endif /* CONFIG_LPS_LCLK_WD_TIMER */
- {
- if (is_primary_adapter(adapter))
- rtw_dynamic_chk_wk_cmd(adapter);
}
+ #endif /* CONFIG_LPS_LCLK_WD_TIMER */
/* auto site survey */
rtw_auto_scan_handler(adapter);
-#ifndef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
#ifdef CONFIG_AP_MODE
- if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
+ if (MLME_IS_AP(adapter)|| MLME_IS_MESH(adapter)) {
+ #ifndef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
expire_timeout_chk(adapter);
-#endif
-#endif /* !CONFIG_ACTIVE_KEEP_ALIVE_CHECK */
+ #endif /* !CONFIG_ACTIVE_KEEP_ALIVE_CHECK */
+
+ #ifdef CONFIG_BMC_TX_RATE_SELECT
+ rtw_update_bmc_sta_tx_rate(adapter);
+ #endif /*CONFIG_BMC_TX_RATE_SELECT*/
+ }
+#endif /*CONFIG_AP_MODE*/
+
#ifdef CONFIG_BR_EXT
@@ -2967,14 +3178,13 @@ void rtw_dynamic_check_timer_handlder(_adapter *adapter)
#else /* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */
if (rcu_dereference(adapter->pnetdev->rx_handler_data)
#endif /* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */
- && (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE) == _TRUE)) {
+ && (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE) == _TRUE)) {
/* expire NAT2.5 entry */
void nat25_db_expire(_adapter *priv);
nat25_db_expire(adapter);
if (adapter->pppoe_connection_in_progress > 0)
adapter->pppoe_connection_in_progress--;
-
/* due to rtw_dynamic_check_timer_handlder() is called every 2 seconds */
if (adapter->pppoe_connection_in_progress > 0)
adapter->pppoe_connection_in_progress--;
@@ -2988,6 +3198,141 @@ void rtw_dynamic_check_timer_handlder(_adapter *adapter)
}
+/*TP_avg(t) = (1/10) * TP_avg(t-1) + (9/10) * TP(t) MBps*/
+static void collect_sta_traffic_statistics(_adapter *adapter)
+{
+ struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl;
+ struct sta_info *sta;
+ u16 curr_tx_mbytes = 0, curr_rx_mbytes = 0;
+ int i;
+
+ for (i = 0; i < MACID_NUM_SW_LIMIT; i++) {
+ sta = macid_ctl->sta[i];
+ if (sta && !is_broadcast_mac_addr(sta->cmn.mac_addr)) {
+ if (sta->sta_stats.last_tx_bytes > sta->sta_stats.tx_bytes)
+ sta->sta_stats.last_tx_bytes = sta->sta_stats.tx_bytes;
+ if (sta->sta_stats.last_rx_bytes > sta->sta_stats.rx_bytes)
+ sta->sta_stats.last_rx_bytes = sta->sta_stats.rx_bytes;
+ if (sta->sta_stats.last_rx_bc_bytes > sta->sta_stats.rx_bc_bytes)
+ sta->sta_stats.last_rx_bc_bytes = sta->sta_stats.rx_bc_bytes;
+ if (sta->sta_stats.last_rx_mc_bytes > sta->sta_stats.rx_mc_bytes)
+ sta->sta_stats.last_rx_mc_bytes = sta->sta_stats.rx_mc_bytes;
+
+ curr_tx_mbytes = ((sta->sta_stats.tx_bytes - sta->sta_stats.last_tx_bytes) >> 20) / 2; /*MBps*/
+ curr_rx_mbytes = ((sta->sta_stats.rx_bytes - sta->sta_stats.last_rx_bytes) >> 20) / 2; /*MBps*/
+ sta->sta_stats.tx_tp_mbytes = curr_tx_mbytes;
+ sta->sta_stats.rx_tp_mbytes = curr_rx_mbytes;
+
+ sta->cmn.tx_moving_average_tp =
+ (sta->cmn.tx_moving_average_tp / 10) + (curr_tx_mbytes * 9 / 10);
+
+ sta->cmn.rx_moving_average_tp =
+ (sta->cmn.rx_moving_average_tp / 10) + (curr_rx_mbytes * 9 /10);
+
+ if (adapter->bsta_tp_dump)
+ dump_sta_traffic(RTW_DBGDUMP, adapter, sta);
+
+ sta->sta_stats.last_tx_bytes = sta->sta_stats.tx_bytes;
+ sta->sta_stats.last_rx_bytes = sta->sta_stats.rx_bytes;
+ sta->sta_stats.last_rx_bc_bytes = sta->sta_stats.rx_bc_bytes;
+ sta->sta_stats.last_rx_mc_bytes = sta->sta_stats.rx_mc_bytes;
+ }
+ }
+}
+
+void rtw_sta_traffic_info(void *sel, _adapter *adapter)
+{
+ struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl;
+ struct sta_info *sta;
+ int i;
+
+ for (i = 0; i < MACID_NUM_SW_LIMIT; i++) {
+ sta = macid_ctl->sta[i];
+ if (sta && !is_broadcast_mac_addr(sta->cmn.mac_addr))
+ dump_sta_traffic(sel, adapter, sta);
+ }
+}
+
+/*#define DBG_TRAFFIC_STATISTIC*/
+static void collect_traffic_statistics(_adapter *padapter)
+{
+ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
+
+ /*_rtw_memset(&pdvobjpriv->traffic_stat, 0, sizeof(struct rtw_traffic_statistics));*/
+
+ /* Tx bytes reset*/
+ pdvobjpriv->traffic_stat.tx_bytes = 0;
+ pdvobjpriv->traffic_stat.tx_pkts = 0;
+ pdvobjpriv->traffic_stat.tx_drop = 0;
+
+ /* Rx bytes reset*/
+ pdvobjpriv->traffic_stat.rx_bytes = 0;
+ pdvobjpriv->traffic_stat.rx_pkts = 0;
+ pdvobjpriv->traffic_stat.rx_drop = 0;
+
+ rtw_mi_traffic_statistics(padapter);
+
+ /* Calculate throughput in last interval */
+ pdvobjpriv->traffic_stat.cur_tx_bytes = pdvobjpriv->traffic_stat.tx_bytes - pdvobjpriv->traffic_stat.last_tx_bytes;
+ pdvobjpriv->traffic_stat.cur_rx_bytes = pdvobjpriv->traffic_stat.rx_bytes - pdvobjpriv->traffic_stat.last_rx_bytes;
+ pdvobjpriv->traffic_stat.last_tx_bytes = pdvobjpriv->traffic_stat.tx_bytes;
+ pdvobjpriv->traffic_stat.last_rx_bytes = pdvobjpriv->traffic_stat.rx_bytes;
+
+ pdvobjpriv->traffic_stat.cur_tx_tp = (u32)(pdvobjpriv->traffic_stat.cur_tx_bytes * 8 / 2 / 1024 / 1024);
+ pdvobjpriv->traffic_stat.cur_rx_tp = (u32)(pdvobjpriv->traffic_stat.cur_rx_bytes * 8 / 2 / 1024 / 1024);
+
+ #ifdef DBG_TRAFFIC_STATISTIC
+ RTW_INFO("\n========================\n");
+ RTW_INFO("cur_tx_bytes:%lld\n", pdvobjpriv->traffic_stat.cur_tx_bytes);
+ RTW_INFO("cur_rx_bytes:%lld\n", pdvobjpriv->traffic_stat.cur_rx_bytes);
+
+ RTW_INFO("last_tx_bytes:%lld\n", pdvobjpriv->traffic_stat.last_tx_bytes);
+ RTW_INFO("last_rx_bytes:%lld\n", pdvobjpriv->traffic_stat.last_rx_bytes);
+
+ RTW_INFO("cur_tx_tp:%d\n", pdvobjpriv->traffic_stat.cur_tx_tp);
+ RTW_INFO("cur_rx_tp:%d\n", pdvobjpriv->traffic_stat.cur_rx_tp);
+ #endif
+
+#ifdef CONFIG_RTW_NAPI
+#ifdef CONFIG_RTW_NAPI_DYNAMIC
+ dynamic_napi_th_chk (padapter);
+#endif /* CONFIG_RTW_NAPI_DYNAMIC */
+#endif
+
+}
+
+void rtw_dynamic_check_timer_handlder(void *ctx)
+{
+ struct dvobj_priv *pdvobj = (struct dvobj_priv *)ctx;
+ _adapter *adapter = dvobj_get_primary_adapter(pdvobj);
+
+#if (MP_DRIVER == 1)
+ if (adapter->registrypriv.mp_mode == 1 && adapter->mppriv.mp_dm == 0) { /* for MP ODM dynamic Tx power tracking */
+ /* RTW_INFO("%s mp_dm =0 return\n", __func__); */
+ goto exit;
+ }
+#endif
+
+ if (!adapter)
+ goto exit;
+
+ if (!rtw_is_hw_init_completed(adapter))
+ goto exit;
+
+ if (RTW_CANNOT_RUN(adapter))
+ goto exit;
+
+ collect_traffic_statistics(adapter);
+ collect_sta_traffic_statistics(adapter);
+ rtw_mi_dynamic_check_timer_handlder(adapter);
+
+ if (!is_drv_in_lps(adapter))
+ rtw_dynamic_chk_wk_cmd(adapter);
+
+exit:
+ _set_timer(&pdvobj->dynamic_chk_timer, 2000);
+}
+
#ifdef CONFIG_SET_SCAN_DENY_TIMER
inline bool rtw_is_scan_deny(_adapter *adapter)
@@ -3004,8 +3349,10 @@ inline void rtw_clear_scan_deny(_adapter *adapter)
RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter));
}
-void rtw_set_scan_deny_timer_hdl(_adapter *adapter)
+void rtw_set_scan_deny_timer_hdl(void *ctx)
{
+ _adapter *adapter = (_adapter *)ctx;
+
rtw_clear_scan_deny(adapter);
}
void rtw_set_scan_deny(_adapter *adapter, u32 ms)
@@ -3030,12 +3377,33 @@ static int rtw_check_roaming_candidate(struct mlme_priv *mlme
int updated = _FALSE;
_adapter *adapter = container_of(mlme, _adapter, mlmepriv);
+ if (rtw_chset_search_ch(adapter_to_chset(adapter), competitor->network.Configuration.DSConfig) < 0)
+ goto exit;
+
+#if defined(CONFIG_RTW_REPEATER_SON) && (!defined(CONFIG_RTW_REPEATER_SON_ROOT))
+ if (rtw_rson_isupdate_roamcan(mlme, candidate, competitor))
+ goto update;
+ goto exit;
+#endif
+
if (is_same_ess(&competitor->network, &mlme->cur_network.network) == _FALSE)
goto exit;
if (rtw_is_desired_network(adapter, competitor) == _FALSE)
goto exit;
+#ifdef CONFIG_LAYER2_ROAMING
+ if (mlme->need_to_roam == _FALSE)
+ goto exit;
+#endif
+
+#ifdef CONFIG_RTW_80211R
+ if (rtw_ft_chk_flags(adapter, RTW_FT_PEER_EN)) {
+ if (rtw_ft_chk_roaming_candidate(adapter, competitor) == _FALSE)
+ goto exit;
+ }
+#endif
+
RTW_INFO("roam candidate:%s %s("MAC_FMT", ch%3u) rssi:%d, age:%5d\n",
(competitor == mlme->cur_network_scanned) ? "*" : " " ,
competitor->network.Ssid.Ssid,
@@ -3053,9 +3421,16 @@ static int rtw_check_roaming_candidate(struct mlme_priv *mlme
goto exit;
}
#if 1
- if (rtw_get_passing_time_ms((u32)competitor->last_scanned) >= mlme->roam_scanr_exp_ms)
+ if (rtw_get_passing_time_ms(competitor->last_scanned) >= mlme->roam_scanr_exp_ms)
goto exit;
+#if defined(CONFIG_RTW_80211R) && defined(CONFIG_RTW_WNM)
+ if (rtw_wnm_btm_diff_bss(adapter) &&
+ rtw_wnm_btm_roam_candidate(adapter, competitor)) {
+ goto update;
+ }
+#endif
+
if (competitor->network.Rssi - mlme->cur_network_scanned->network.Rssi < mlme->roam_rssi_diff_th)
goto exit;
@@ -3084,7 +3459,6 @@ int rtw_select_roaming_candidate(struct mlme_priv *mlme)
struct wlan_network *candidate = NULL;
u8 bSupportAntDiv = _FALSE;
- _func_enter_;
if (mlme->cur_network_scanned == NULL) {
rtw_warn_on(1);
@@ -3101,7 +3475,6 @@ int rtw_select_roaming_candidate(struct mlme_priv *mlme)
pnetwork = LIST_CONTAINOR(mlme->pscanned, struct wlan_network, list);
if (pnetwork == NULL) {
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("%s return _FAIL:(pnetwork==NULL)\n", __FUNCTION__));
ret = _FAIL;
goto exit;
}
@@ -3120,14 +3493,37 @@ int rtw_select_roaming_candidate(struct mlme_priv *mlme)
}
if (candidate == NULL) {
+ /* if parent note lost the path to root and there is no other cadidate, report disconnection */
+#if defined(CONFIG_RTW_REPEATER_SON) && (!defined(CONFIG_RTW_REPEATER_SON_ROOT))
+ struct rtw_rson_struct rson_curr;
+ u8 rson_score;
+
+ rtw_get_rson_struct(&(mlme->cur_network_scanned->network), &rson_curr);
+ rson_score = rtw_cal_rson_score(&rson_curr, mlme->cur_network_scanned->network.Rssi);
+ if (check_fwstate(mlme, _FW_LINKED)
+ && ((rson_score == RTW_RSON_SCORE_NOTCNNT)
+ || (rson_score == RTW_RSON_SCORE_NOTSUP)))
+ receive_disconnect(adapter, mlme->cur_network_scanned->network.MacAddress
+ , WLAN_REASON_EXPIRATION_CHK, _FALSE);
+#endif
RTW_INFO("%s: return _FAIL(candidate == NULL)\n", __FUNCTION__);
ret = _FAIL;
goto exit;
} else {
+#if defined(CONFIG_RTW_REPEATER_SON) && (!defined(CONFIG_RTW_REPEATER_SON_ROOT))
+ struct rtw_rson_struct rson_curr;
+ u8 rson_score;
+
+ rtw_get_rson_struct(&(candidate->network), &rson_curr);
+ rson_score = rtw_cal_rson_score(&rson_curr, candidate->network.Rssi);
+ RTW_INFO("%s: candidate: %s("MAC_FMT", ch:%u) rson_score:%d\n", __FUNCTION__,
+ candidate->network.Ssid.Ssid, MAC_ARG(candidate->network.MacAddress),
+ candidate->network.Configuration.DSConfig, rson_score);
+#else
RTW_INFO("%s: candidate: %s("MAC_FMT", ch:%u)\n", __FUNCTION__,
candidate->network.Ssid.Ssid, MAC_ARG(candidate->network.MacAddress),
candidate->network.Configuration.DSConfig);
-
+#endif
mlme->roam_network = candidate;
if (_rtw_memcmp(candidate->network.MacAddress, mlme->roam_tgt_addr, ETH_ALEN) == _TRUE)
@@ -3153,6 +3549,27 @@ static int rtw_check_join_candidate(struct mlme_priv *mlme
int updated = _FALSE;
_adapter *adapter = container_of(mlme, _adapter, mlmepriv);
+ if (rtw_chset_search_ch(adapter_to_chset(adapter), competitor->network.Configuration.DSConfig) < 0)
+ goto exit;
+
+#if defined(CONFIG_RTW_REPEATER_SON) && (!defined(CONFIG_RTW_REPEATER_SON_ROOT))
+ s16 rson_score;
+ struct rtw_rson_struct rson_data;
+
+ if (rtw_rson_choose(candidate, competitor)) {
+ *candidate = competitor;
+ rtw_get_rson_struct(&((*candidate)->network), &rson_data);
+ rson_score = rtw_cal_rson_score(&rson_data, (*candidate)->network.Rssi);
+ RTW_INFO("[assoc_ssid:%s] new candidate: %s("MAC_FMT", ch%u) rson_score:%d\n",
+ mlme->assoc_ssid.Ssid,
+ (*candidate)->network.Ssid.Ssid,
+ MAC_ARG((*candidate)->network.MacAddress),
+ (*candidate)->network.Configuration.DSConfig,
+ rson_score);
+ return _TRUE;
+ }
+ return _FALSE;
+#endif
/* check bssid, if needed */
if (mlme->assoc_by_bssid == _TRUE) {
@@ -3173,7 +3590,7 @@ static int rtw_check_join_candidate(struct mlme_priv *mlme
#ifdef CONFIG_LAYER2_ROAMING
if (rtw_to_roam(adapter) > 0) {
- if (rtw_get_passing_time_ms((u32)competitor->last_scanned) >= mlme->roam_scanr_exp_ms
+ if (rtw_get_passing_time_ms(competitor->last_scanned) >= mlme->roam_scanr_exp_ms
|| is_same_ess(&competitor->network, &mlme->cur_network.network) == _FALSE
)
goto exit;
@@ -3224,7 +3641,6 @@ int rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv)
struct wlan_network *candidate = NULL;
u8 bSupportAntDiv = _FALSE;
- _func_enter_;
adapter = (_adapter *)pmlmepriv->nic_hdl;
@@ -3245,7 +3661,6 @@ int rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv)
pnetwork = LIST_CONTAINOR(pmlmepriv->pscanned, struct wlan_network, list);
if (pnetwork == NULL) {
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("%s return _FAIL:(pnetwork==NULL)\n", __FUNCTION__));
ret = _FAIL;
goto exit;
}
@@ -3294,7 +3709,7 @@ int rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv)
} else
#endif
{
- rtw_disassoc_cmd(adapter, 0, _TRUE);
+ rtw_disassoc_cmd(adapter, 0, 0);
rtw_indicate_disconnect(adapter, 0, _FALSE);
rtw_free_assoc_resources(adapter, 0);
}
@@ -3317,7 +3732,6 @@ int rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv)
exit:
_exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
- _func_exit_;
return ret;
}
@@ -3329,7 +3743,6 @@ sint rtw_set_auth(_adapter *adapter, struct security_priv *psecuritypriv)
struct cmd_priv *pcmdpriv = &(adapter->cmdpriv);
sint res = _SUCCESS;
- _func_enter_;
pcmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
if (pcmd == NULL) {
@@ -3356,13 +3769,11 @@ sint rtw_set_auth(_adapter *adapter, struct security_priv *psecuritypriv)
_rtw_init_listhead(&pcmd->list);
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("after enqueue set_auth_cmd, auth_mode=%x\n", psecuritypriv->dot11AuthAlgrthm));
res = rtw_enqueue_cmd(pcmdpriv, pcmd);
exit:
- _func_exit_;
return res;
@@ -3378,7 +3789,6 @@ sint rtw_set_key(_adapter *adapter, struct security_priv *psecuritypriv, sint ke
struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
sint res = _SUCCESS;
- _func_enter_;
psetkeyparm = (struct setkey_parm *)rtw_zmalloc(sizeof(struct setkey_parm));
if (psetkeyparm == NULL) {
@@ -3389,10 +3799,8 @@ sint rtw_set_key(_adapter *adapter, struct security_priv *psecuritypriv, sint ke
if (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) {
psetkeyparm->algorithm = (unsigned char)psecuritypriv->dot118021XGrpPrivacy;
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("\n rtw_set_key: psetkeyparm->algorithm=(unsigned char)psecuritypriv->dot118021XGrpPrivacy=%d\n", psetkeyparm->algorithm));
} else {
psetkeyparm->algorithm = (u8)psecuritypriv->dot11PrivacyAlgrthm;
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("\n rtw_set_key: psetkeyparm->algorithm=(u8)psecuritypriv->dot11PrivacyAlgrthm=%d\n", psetkeyparm->algorithm));
}
psetkeyparm->keyid = (u8)keyid;/* 0~3 */
@@ -3401,7 +3809,6 @@ sint rtw_set_key(_adapter *adapter, struct security_priv *psecuritypriv, sint ke
adapter->securitypriv.key_mask |= BIT(psetkeyparm->keyid);
RTW_INFO("==> rtw_set_key algorithm(%x),keyid(%x),key_mask(%x)\n", psetkeyparm->algorithm, psetkeyparm->keyid, adapter->securitypriv.key_mask);
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("\n rtw_set_key: psetkeyparm->algorithm=%d psetkeyparm->keyid=(u8)keyid=%d\n", psetkeyparm->algorithm, keyid));
switch (psetkeyparm->algorithm) {
@@ -3416,15 +3823,12 @@ sint rtw_set_key(_adapter *adapter, struct security_priv *psecuritypriv, sint ke
case _TKIP_:
keylen = 16;
_rtw_memcpy(&psetkeyparm->key, &psecuritypriv->dot118021XGrpKey[keyid], keylen);
- psetkeyparm->grpkey = 1;
break;
case _AES_:
keylen = 16;
_rtw_memcpy(&psetkeyparm->key, &psecuritypriv->dot118021XGrpKey[keyid], keylen);
- psetkeyparm->grpkey = 1;
break;
default:
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("\n rtw_set_key:psecuritypriv->dot11PrivacyAlgrthm = %x (must be 1 or 2 or 4 or 5)\n", psecuritypriv->dot11PrivacyAlgrthm));
res = _FAIL;
rtw_mfree((unsigned char *)psetkeyparm, sizeof(struct setkey_parm));
goto exit;
@@ -3455,17 +3859,115 @@ sint rtw_set_key(_adapter *adapter, struct security_priv *psecuritypriv, sint ke
rtw_mfree((u8 *) psetkeyparm, sizeof(struct setkey_parm));
}
exit:
- _func_exit_;
return res;
}
+#ifdef CONFIG_WMMPS_STA
+/*
+ * rtw_uapsd_use_default_setting
+ * This function is used for setting default uapsd max sp length to uapsd_max_sp_len
+ * in qos_priv data structure from registry. In additional, it will also map default uapsd
+ * ac to each uapsd TID, delivery-enabled and trigger-enabled of corresponding TID.
+ *
+ * Arguments:
+ * @padapter: _adapter pointer.
+ *
+ * Auther: Arvin Liu
+ * Date: 2017/05/03
+ */
+void rtw_uapsd_use_default_setting(_adapter *padapter)
+{
+ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+ struct qos_priv *pqospriv = &pmlmepriv->qospriv;
+ struct registry_priv *pregistrypriv = &padapter->registrypriv;
+
+ if (pregistrypriv->uapsd_ac_enable != 0) {
+ pqospriv->uapsd_max_sp_len = pregistrypriv->uapsd_max_sp_len;
+
+ CLEAR_FLAGS(pqospriv->uapsd_tid);
+ CLEAR_FLAGS(pqospriv->uapsd_tid_delivery_enabled);
+ CLEAR_FLAGS(pqospriv->uapsd_tid_trigger_enabled);
+
+ /* check the uapsd setting of AC_VO from registry then map these setting to each TID if necessary */
+ if(TEST_FLAG(pregistrypriv->uapsd_ac_enable, DRV_CFG_UAPSD_VO)) {
+ SET_FLAG(pqospriv->uapsd_tid, WMM_TID7);
+ SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID7);
+ SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID7);
+ SET_FLAG(pqospriv->uapsd_tid, WMM_TID6);
+ SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID6);
+ SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID6);
+ }
+
+ /* check the uapsd setting of AC_VI from registry then map these setting to each TID if necessary */
+ if(TEST_FLAG(pregistrypriv->uapsd_ac_enable, DRV_CFG_UAPSD_VI)) {
+ SET_FLAG(pqospriv->uapsd_tid, WMM_TID5);
+ SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID5);
+ SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID5);
+ SET_FLAG(pqospriv->uapsd_tid, WMM_TID4);
+ SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID4);
+ SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID4);
+ }
+
+ /* check the uapsd setting of AC_BK from registry then map these setting to each TID if necessary */
+ if(TEST_FLAG(pregistrypriv->uapsd_ac_enable, DRV_CFG_UAPSD_BK)) {
+ SET_FLAG(pqospriv->uapsd_tid, WMM_TID2);
+ SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID2);
+ SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID2);
+ SET_FLAG(pqospriv->uapsd_tid, WMM_TID1);
+ SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID1);
+ SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID1);
+ }
+
+ /* check the uapsd setting of AC_BE from registry then map these setting to each TID if necessary */
+ if(TEST_FLAG(pregistrypriv->uapsd_ac_enable, DRV_CFG_UAPSD_BE)) {
+ SET_FLAG(pqospriv->uapsd_tid, WMM_TID3);
+ SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID3);
+ SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID3);
+ SET_FLAG(pqospriv->uapsd_tid, WMM_TID0);
+ SET_FLAG(pqospriv->uapsd_tid_delivery_enabled, WMM_TID0);
+ SET_FLAG(pqospriv->uapsd_tid_trigger_enabled, WMM_TID0);
+ }
+
+ RTW_INFO("[WMMPS] UAPSD MAX SP Len = 0x%02x, UAPSD TID enabled = 0x%02x\n",
+ pqospriv->uapsd_max_sp_len, (u8)pqospriv->uapsd_tid);
+ }
+
+}
+
+/*
+ * rtw_is_wmmps_mode
+ * This function is used for checking whether Driver and an AP support uapsd function or not.
+ * If both of them support uapsd function, it will return true. Otherwise returns false.
+ *
+ * Arguments:
+ * @padapter: _adapter pointer.
+ *
+ * Auther: Arvin Liu
+ * Date: 2017/06/12
+ */
+bool rtw_is_wmmps_mode(_adapter *padapter)
+{
+ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+ struct qos_priv *pqospriv = &pmlmepriv->qospriv;
+
+ if ((pqospriv->uapsd_ap_supported) && ((pqospriv->uapsd_tid & BIT_MASK_TID_TC) != 0))
+ return _TRUE;
+
+ return _FALSE;
+}
+#endif /* CONFIG_WMMPS_STA */
/* adjust IEs for rtw_joinbss_cmd in WMM */
int rtw_restruct_wmm_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len, uint initial_out_len)
{
+#ifdef CONFIG_WMMPS_STA
+ struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
+ struct qos_priv *pqospriv = &pmlmepriv->qospriv;
+#endif /* CONFIG_WMMPS_STA */
unsigned int ielength = 0;
unsigned int i, j;
+ u8 qos_info = 0;
i = 12; /* after the fixed IE */
while (i < in_len) {
@@ -3488,7 +3990,42 @@ int rtw_restruct_wmm_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len, u
}
out_ie[initial_out_len + 1] = 0x07;
out_ie[initial_out_len + 6] = 0x00;
- out_ie[initial_out_len + 8] = 0x00;
+
+#ifdef CONFIG_WMMPS_STA
+ switch(pqospriv->uapsd_max_sp_len) {
+ case NO_LIMIT:
+ /* do nothing */
+ break;
+ case TWO_MSDU:
+ SET_FLAG(qos_info, BIT5);
+ break;
+ case FOUR_MSDU:
+ SET_FLAG(qos_info, BIT6);
+ break;
+ case SIX_MSDU:
+ SET_FLAG(qos_info, BIT5);
+ SET_FLAG(qos_info, BIT6);
+ break;
+ default:
+ /* do nothing */
+ break;
+ };
+
+ /* check TID7 and TID6 for AC_VO to set corresponding Qos_info bit in WMM IE */
+ if((TEST_FLAG(pqospriv->uapsd_tid, WMM_TID7)) && (TEST_FLAG(pqospriv->uapsd_tid, WMM_TID6)))
+ SET_FLAG(qos_info, WMM_IE_UAPSD_VO);
+ /* check TID5 and TID4 for AC_VI to set corresponding Qos_info bit in WMM IE */
+ if((TEST_FLAG(pqospriv->uapsd_tid, WMM_TID5)) && (TEST_FLAG(pqospriv->uapsd_tid, WMM_TID4)))
+ SET_FLAG(qos_info, WMM_IE_UAPSD_VI);
+ /* check TID2 and TID1 for AC_BK to set corresponding Qos_info bit in WMM IE */
+ if((TEST_FLAG(pqospriv->uapsd_tid, WMM_TID2)) && (TEST_FLAG(pqospriv->uapsd_tid, WMM_TID1)))
+ SET_FLAG(qos_info, WMM_IE_UAPSD_BK);
+ /* check TID3 and TID0 for AC_BE to set corresponding Qos_info bit in WMM IE */
+ if((TEST_FLAG(pqospriv->uapsd_tid, WMM_TID3)) && (TEST_FLAG(pqospriv->uapsd_tid, WMM_TID0)))
+ SET_FLAG(qos_info, WMM_IE_UAPSD_BE);
+#endif /* CONFIG_WMMPS_STA */
+
+ out_ie[initial_out_len + 8] = qos_info;
break;
}
@@ -3538,84 +4075,74 @@ static int SecIsInPMKIDList(_adapter *Adapter, u8 *bssid)
}
-/*
- * Check the RSN IE length
- * If the RSN IE length <= 20, the RSN IE didn't include the PMKID information
- * 0-11th element in the array are the fixed IE
- * 12th element in the array is the IE
- * 13th element in the array is the IE length
- * */
-
-static int rtw_append_pmkid(_adapter *adapter, int iEntry, u8 *ie, uint ie_len)
+static int rtw_rsn_sync_pmkid(_adapter *adapter, u8 *ie, uint ie_len, int i_ent)
{
struct security_priv *sec = &adapter->securitypriv;
+ struct rsne_info info;
+ u8 gm_cs[4];
+ int i;
- if (ie[13] > 20) {
- int i;
- u16 pmkid_cnt = RTW_GET_LE16(ie + 14 + 20);
- if (pmkid_cnt == 1 && _rtw_memcmp(ie + 14 + 20 + 2, &sec->PMKIDList[iEntry].PMKID, 16)) {
- RTW_INFO(FUNC_ADPT_FMT" has carried the same PMKID:"KEY_FMT"\n"
- , FUNC_ADPT_ARG(adapter), KEY_ARG(&sec->PMKIDList[iEntry].PMKID));
- goto exit;
- }
-
- RTW_INFO(FUNC_ADPT_FMT" remove original PMKID, count:%u\n"
- , FUNC_ADPT_ARG(adapter), pmkid_cnt);
-
- for (i = 0; i < pmkid_cnt; i++)
- RTW_INFO(" "KEY_FMT"\n", KEY_ARG(ie + 14 + 20 + 2 + i * 16));
+ rtw_rsne_info_parse(ie, ie_len, &info);
- ie_len -= 2 + pmkid_cnt * 16;
- ie[13] = 20;
+ if (info.err) {
+ RTW_WARN(FUNC_ADPT_FMT" rtw_rsne_info_parse error\n"
+ , FUNC_ADPT_ARG(adapter));
+ return 0;
}
- if (ie[13] <= 20) {
- /* The RSN IE didn't include the PMK ID, append the PMK information */
-
- RTW_INFO(FUNC_ADPT_FMT" append PMKID:"KEY_FMT"\n"
- , FUNC_ADPT_ARG(adapter), KEY_ARG(&sec->PMKIDList[iEntry].PMKID));
-
- RTW_PUT_LE16(&ie[ie_len], 1);
- ie_len += 2;
-
- _rtw_memcpy(&ie[ie_len], &sec->PMKIDList[iEntry].PMKID, 16);
- ie_len += 16;
+ if (i_ent < 0 && info.pmkid_cnt == 0)
+ goto exit;
- ie[13] += 18;/* PMKID length = 2+16 */
+ if (i_ent >= 0 && info.pmkid_cnt == 1 && _rtw_memcmp(info.pmkid_list, sec->PMKIDList[i_ent].PMKID, 16)) {
+ RTW_INFO(FUNC_ADPT_FMT" has carried the same PMKID:"KEY_FMT"\n"
+ , FUNC_ADPT_ARG(adapter), KEY_ARG(&sec->PMKIDList[i_ent].PMKID));
+ goto exit;
}
-exit:
- return ie_len;
-}
-
-static int rtw_remove_pmkid(_adapter *adapter, u8 *ie, uint ie_len)
-{
- struct security_priv *sec = &adapter->securitypriv;
- int i;
- u16 pmkid_cnt = RTW_GET_LE16(ie + 14 + 20);
-
- if (ie[13] <= 20)
- goto exit;
+ /* bakcup group mgmt cs */
+ if (info.gmcs)
+ _rtw_memcpy(gm_cs, info.gmcs, 4);
- RTW_INFO(FUNC_ADPT_FMT" remove original PMKID, count:%u\n"
- , FUNC_ADPT_ARG(adapter), pmkid_cnt);
+ if (info.pmkid_cnt) {
+ RTW_INFO(FUNC_ADPT_FMT" remove original PMKID, count:%u\n"
+ , FUNC_ADPT_ARG(adapter), info.pmkid_cnt);
+ for (i = 0; i < info.pmkid_cnt; i++)
+ RTW_INFO(" "KEY_FMT"\n", KEY_ARG(info.pmkid_list + i * 16));
+ }
- for (i = 0; i < pmkid_cnt; i++)
- RTW_INFO(" "KEY_FMT"\n", KEY_ARG(ie + 14 + 20 + 2 + i * 16));
+ if (i_ent >= 0) {
+ RTW_INFO(FUNC_ADPT_FMT" append PMKID:"KEY_FMT"\n"
+ , FUNC_ADPT_ARG(adapter), KEY_ARG(sec->PMKIDList[i_ent].PMKID));
- ie_len -= 2 + pmkid_cnt * 16;
- ie[13] = 20;
+ info.pmkid_cnt = 1; /* update new pmkid_cnt */
+ _rtw_memcpy(info.pmkid_list, sec->PMKIDList[i_ent].PMKID, 16);
+ } else
+ info.pmkid_cnt = 0; /* update new pmkid_cnt */
+
+ RTW_PUT_LE16(info.pmkid_list - 2, info.pmkid_cnt);
+ if (info.gmcs)
+ _rtw_memcpy(info.pmkid_list + 16 * info.pmkid_cnt, gm_cs, 4);
+
+ ie_len = 1 + 1 + 2 + 4
+ + 2 + 4 * info.pcs_cnt
+ + 2 + 4 * info.akm_cnt
+ + 2
+ + 2 + 16 * info.pmkid_cnt
+ + (info.gmcs ? 4 : 0)
+ ;
+
+ ie[1] = (u8)(ie_len - 2);
exit:
return ie_len;
}
-sint rtw_restruct_sec_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len)
+sint rtw_restruct_sec_ie(_adapter *adapter, u8 *out_ie)
{
u8 authmode = 0x0, securitytype, match;
u8 sec_ie[255], uncst_oui[4], bkup_ie[255];
u8 wpa_oui[4] = {0x0, 0x50, 0xf2, 0x01};
- uint ielength, cnt, remove_cnt;
+ uint ielength = 0, cnt, remove_cnt;
int iEntry;
struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
@@ -3623,27 +4150,18 @@ sint rtw_restruct_sec_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len)
uint ndisauthmode = psecuritypriv->ndisauthtype;
uint ndissecuritytype = psecuritypriv->ndisencryptstatus;
- _func_enter_;
-
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_notice_,
- ("+rtw_restruct_sec_ie: ndisauthmode=%d ndissecuritytype=%d\n",
- ndisauthmode, ndissecuritytype));
-
- /* copy fixed ie only */
- _rtw_memcpy(out_ie, in_ie, 12);
- ielength = 12;
if ((ndisauthmode == Ndis802_11AuthModeWPA) || (ndisauthmode == Ndis802_11AuthModeWPAPSK))
authmode = _WPA_IE_ID_;
if ((ndisauthmode == Ndis802_11AuthModeWPA2) || (ndisauthmode == Ndis802_11AuthModeWPA2PSK))
authmode = _WPA2_IE_ID_;
if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) {
- _rtw_memcpy(out_ie + ielength, psecuritypriv->wps_ie, psecuritypriv->wps_ie_len);
+ _rtw_memcpy(out_ie, psecuritypriv->wps_ie, psecuritypriv->wps_ie_len);
+ ielength = psecuritypriv->wps_ie_len;
- ielength += psecuritypriv->wps_ie_len;
} else if ((authmode == _WPA_IE_ID_) || (authmode == _WPA2_IE_ID_)) {
/* copy RSN or SSN */
- _rtw_memcpy(&out_ie[ielength], &psecuritypriv->supplicant_ie[0], psecuritypriv->supplicant_ie[1] + 2);
+ _rtw_memcpy(out_ie, psecuritypriv->supplicant_ie, psecuritypriv->supplicant_ie[1] + 2);
/* debug for CONFIG_IEEE80211W
{
int jj;
@@ -3652,25 +4170,15 @@ sint rtw_restruct_sec_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len)
printk(" %02x ", psecuritypriv->supplicant_ie[jj]);
printk("\n");
}*/
- ielength += psecuritypriv->supplicant_ie[1] + 2;
+ ielength = psecuritypriv->supplicant_ie[1] + 2;
rtw_report_sec_ie(adapter, authmode, psecuritypriv->supplicant_ie);
-
-#ifdef CONFIG_DRVEXT_MODULE
- drvext_report_sec_ie(&adapter->drvextpriv, authmode, sec_ie);
-#endif
}
- iEntry = SecIsInPMKIDList(adapter, pmlmepriv->assoc_bssid);
- if (iEntry < 0) {
- if (authmode == _WPA2_IE_ID_)
- ielength = rtw_remove_pmkid(adapter, out_ie, ielength);
- } else {
- if (authmode == _WPA2_IE_ID_)
- ielength = rtw_append_pmkid(adapter, iEntry, out_ie, ielength);
+ if (authmode == WLAN_EID_RSN) {
+ iEntry = SecIsInPMKIDList(adapter, pmlmepriv->assoc_bssid);
+ ielength = rtw_rsn_sync_pmkid(adapter, out_ie, ielength, iEntry);
}
- _func_exit_;
-
return ielength;
}
@@ -3680,7 +4188,6 @@ void rtw_init_registrypriv_dev_network(_adapter *adapter)
WLAN_BSSID_EX *pdev_network = &pregistrypriv->dev_network;
u8 *myhwaddr = adapter_mac_addr(adapter);
- _func_enter_;
_rtw_memcpy(pdev_network->MacAddress, myhwaddr, ETH_ALEN);
@@ -3694,7 +4201,6 @@ void rtw_init_registrypriv_dev_network(_adapter *adapter)
pdev_network->Configuration.FHConfig.DwellTime = 0;
- _func_exit_;
}
@@ -3708,7 +4214,6 @@ void rtw_update_registrypriv_dev_network(_adapter *adapter)
/* struct xmit_priv *pxmitpriv = &adapter->xmitpriv; */
struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
- _func_enter_;
#if 0
pxmitpriv->vcs_setting = pregistrypriv->vrtl_carrier_sense;
@@ -3751,7 +4256,6 @@ void rtw_update_registrypriv_dev_network(_adapter *adapter)
}
pdev_network->Configuration.DSConfig = (pregistrypriv->channel);
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("pregistrypriv->channel=%d, pdev_network->Configuration.DSConfig=0x%x\n", pregistrypriv->channel, pdev_network->Configuration.DSConfig));
if (cur_network->network.InfrastructureMode == Ndis802_11IBSS) {
pdev_network->Configuration.ATIMWindow = (0);
@@ -3777,16 +4281,13 @@ void rtw_update_registrypriv_dev_network(_adapter *adapter)
/* notes: translate IELength & Length after assign the Length to cmdsz in createbss_cmd(); */
/* pdev_network->IELength = cpu_to_le32(sz); */
- _func_exit_;
}
void rtw_get_encrypt_decrypt_from_registrypriv(_adapter *adapter)
{
- _func_enter_;
- _func_exit_;
}
@@ -3878,15 +4379,23 @@ void rtw_ht_use_default_setting(_adapter *padapter)
/* Beamforming setting */
CLEAR_FLAGS(phtpriv->beamform_cap);
#ifdef CONFIG_BEAMFORMING
- rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMER, (u8 *)&bHwSupportBeamformer);
- rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMEE, (u8 *)&bHwSupportBeamformee);
- if (TEST_FLAG(pregistrypriv->beamform_cap, BIT4) && bHwSupportBeamformer) {
- SET_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE);
- RTW_INFO("[HT] HAL Support Beamformer\n");
- }
- if (TEST_FLAG(pregistrypriv->beamform_cap, BIT5) && bHwSupportBeamformee) {
- SET_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE);
- RTW_INFO("[HT] HAL Support Beamformee\n");
+#ifdef RTW_BEAMFORMING_VERSION_2
+ /* only enable beamforming in STA client mode */
+ if (MLME_IS_STA(padapter) && !MLME_IS_GC(padapter)
+ && !MLME_IS_ADHOC(padapter)
+ && !MLME_IS_MESH(padapter))
+#endif
+ {
+ rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMER, (u8 *)&bHwSupportBeamformer);
+ rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMEE, (u8 *)&bHwSupportBeamformee);
+ if (TEST_FLAG(pregistrypriv->beamform_cap, BIT4) && bHwSupportBeamformer) {
+ SET_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE);
+ RTW_INFO("[HT] HAL Support Beamformer\n");
+ }
+ if (TEST_FLAG(pregistrypriv->beamform_cap, BIT5) && bHwSupportBeamformee) {
+ SET_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE);
+ RTW_INFO("[HT] HAL Support Beamformee\n");
+ }
}
#endif /* CONFIG_BEAMFORMING */
}
@@ -3914,11 +4423,16 @@ unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, ui
HT_CAP_AMPDU_DENSITY best_ampdu_density;
unsigned char *p, *pframe;
struct rtw_ieee80211_ht_cap ht_capie;
- u8 cbw40_enable = 0, rf_type = 0, operation_bw = 0, rf_num = 0, rx_stbc_nss = 0;
+ u8 cbw40_enable = 0, rf_type = 0, rf_num = 0, rx_stbc_nss = 0, rx_nss = 0;
struct registry_priv *pregistrypriv = &padapter->registrypriv;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct ht_priv *phtpriv = &pmlmepriv->htpriv;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+ struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
+#ifdef CONFIG_80211AC_VHT
+ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+ struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
+#endif /* CONFIG_80211AC_VHT */
phtpriv->ht_option = _FALSE;
@@ -3931,36 +4445,7 @@ unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, ui
if (phtpriv->sgi_20m)
ht_capie.cap_info |= IEEE80211_HT_CAP_SGI_20;
- /* Get HT BW */
- if (in_ie == NULL) {
- /* TDLS: TODO 20/40 issue */
- if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
- operation_bw = padapter->mlmeextpriv.cur_bwmode;
- if (operation_bw > CHANNEL_WIDTH_40)
- operation_bw = CHANNEL_WIDTH_40;
- } else
- /* TDLS: TODO 40? */
- operation_bw = CHANNEL_WIDTH_40;
- } else {
- p = rtw_get_ie(in_ie, _HT_ADD_INFO_IE_, &ielen, in_len);
- if (p && (ielen == sizeof(struct ieee80211_ht_addt_info))) {
- struct HT_info_element *pht_info = (struct HT_info_element *)(p + 2);
- if (pht_info->infos[0] & BIT(2)) {
- switch (pht_info->infos[0] & 0x3) {
- case 1:
- case 3:
- operation_bw = CHANNEL_WIDTH_40;
- break;
- default:
- operation_bw = CHANNEL_WIDTH_20;
- break;
- }
- } else
- operation_bw = CHANNEL_WIDTH_20;
- }
- }
-
- /* to disable 40M Hz support while gd_bw_40MHz_en = 0 */
+ /* check if 40MHz is allowed according to hal cap and registry */
if (hal_chk_bw_cap(padapter, BW_CAP_40M)) {
if (channel > 14) {
if (REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40))
@@ -3971,10 +4456,53 @@ unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, ui
}
}
- if ((cbw40_enable == 1) && (operation_bw == CHANNEL_WIDTH_40)) {
- ht_capie.cap_info |= IEEE80211_HT_CAP_SUP_WIDTH;
- if (phtpriv->sgi_40m)
- ht_capie.cap_info |= IEEE80211_HT_CAP_SGI_40;
+ if (cbw40_enable) {
+ u8 oper_bw = CHANNEL_WIDTH_20, oper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+
+ if (in_ie == NULL) {
+ /* TDLS: TODO 20/40 issue */
+ if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
+ oper_bw = padapter->mlmeextpriv.cur_bwmode;
+ if (oper_bw > CHANNEL_WIDTH_40)
+ oper_bw = CHANNEL_WIDTH_40;
+ } else
+ /* TDLS: TODO 40? */
+ oper_bw = CHANNEL_WIDTH_40;
+ } else {
+ p = rtw_get_ie(in_ie, WLAN_EID_HT_OPERATION, &ielen, in_len);
+ if (p && ielen == HT_OP_IE_LEN) {
+ if (GET_HT_OP_ELE_STA_CHL_WIDTH(p + 2)) {
+ switch (GET_HT_OP_ELE_2ND_CHL_OFFSET(p + 2)) {
+ case SCA:
+ oper_bw = CHANNEL_WIDTH_40;
+ oper_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
+ break;
+ case SCB:
+ oper_bw = CHANNEL_WIDTH_40;
+ oper_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
+ break;
+ }
+ }
+ }
+ }
+
+ /* adjust bw to fit in channel plan setting */
+ if (oper_bw == CHANNEL_WIDTH_40
+ && oper_offset != HAL_PRIME_CHNL_OFFSET_DONT_CARE /* check this because TDLS has no info to set offset */
+ && !rtw_chset_is_chbw_valid(adapter_to_chset(padapter), channel, oper_bw, oper_offset)
+ ) {
+ oper_bw = CHANNEL_WIDTH_20;
+ oper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+ rtw_warn_on(!rtw_chset_is_chbw_valid(adapter_to_chset(padapter), channel, oper_bw, oper_offset));
+ }
+
+ if (oper_bw == CHANNEL_WIDTH_40) {
+ ht_capie.cap_info |= IEEE80211_HT_CAP_SUP_WIDTH;
+ if (phtpriv->sgi_40m)
+ ht_capie.cap_info |= IEEE80211_HT_CAP_SGI_40;
+ }
+
+ cbw40_enable = oper_bw == CHANNEL_WIDTH_40 ? 1 : 0;
}
/* todo: disable SM power save mode */
@@ -4010,28 +4538,28 @@ unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, ui
/* update default supported_mcs_set */
rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
+ rx_nss = rtw_min(rf_type_to_rf_rx_cnt(rf_type), hal_spec->rx_nss_num);
- switch (rf_type) {
- case RF_1T1R:
+ switch (rx_nss) {
+ case 1:
set_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_1R);
break;
-
- case RF_2T2R:
- case RF_1T2R:
-#ifdef CONFIG_DISABLE_MCS13TO15
- if (((cbw40_enable == 1) && (operation_bw == CHANNEL_WIDTH_40)) && (pregistrypriv->wifi_spec != 1))
+ case 2:
+ #ifdef CONFIG_DISABLE_MCS13TO15
+ if (cbw40_enable && pregistrypriv->wifi_spec != 1)
set_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_2R_13TO15_OFF);
else
+ #endif
set_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_2R);
-#else /* CONFIG_DISABLE_MCS13TO15 */
- set_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_2R);
-#endif /* CONFIG_DISABLE_MCS13TO15 */
break;
- case RF_3T3R:
+ case 3:
set_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_3R);
break;
+ case 4:
+ set_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_4R);
+ break;
default:
- RTW_INFO("[warning] rf_type %d is not expected\n", rf_type);
+ RTW_WARN("rf_type:%d or rx_nss:%u is not expected\n", rf_type, hal_spec->rx_nss_num);
}
{
@@ -4099,7 +4627,14 @@ unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, ui
SET_HT_CAP_TXBF_RECEIVE_NDP_CAP(&ht_capie, 1);
/* Explicit Compressed Beamforming Feedback Capable */
SET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(&ht_capie, 2);
+
rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMEE_CAP, (u8 *)&rf_num);
+#ifdef CONFIG_80211AC_VHT
+ /* IOT action suggested by Yu Chen 2017/3/3 */
+ if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM) &&
+ !GET_VHT_CAPABILITY_ELE_MU_BFER(&pvhtpriv->beamform_cap))
+ rf_num = (rf_num >= 2 ? 2 : rf_num);
+#endif
SET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(&ht_capie, rf_num);
}
#endif/*CONFIG_BEAMFORMING*/
@@ -4156,10 +4691,7 @@ void rtw_update_ht_cap(_adapter *padapter, u8 *pie, uint ie_len, u8 channel)
phtpriv->ampdu_enable = _TRUE;
} else
phtpriv->ampdu_enable = _TRUE;
- } else if (pregistrypriv->ampdu_enable == 2) {
- /* remove this part because testbed AP should disable RX AMPDU */
- /* phtpriv->ampdu_enable = _TRUE; */
- }
+ }
/* check Max Rx A-MPDU Size */
@@ -4197,36 +4729,39 @@ void rtw_update_ht_cap(_adapter *padapter, u8 *pie, uint ie_len, u8 channel)
if ((cbw40_enable) &&
(pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & BIT(1)) &&
(pmlmeinfo->HT_info.infos[0] & BIT(2))) {
+ struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
int i;
u8 rf_type = RF_1T1R;
+ u8 tx_nss = 0;
rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
+ tx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num);
/* update the MCS set */
for (i = 0; i < 16; i++)
pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate[i] &= pmlmeext->default_supported_mcs_set[i];
/* update the MCS rates */
- switch (rf_type) {
- case RF_1T1R:
- case RF_1T2R:
+ switch (tx_nss) {
+ case 1:
set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_1R);
break;
- case RF_2T2R:
-#ifdef CONFIG_DISABLE_MCS13TO15
+ case 2:
+ #ifdef CONFIG_DISABLE_MCS13TO15
if (pmlmeext->cur_bwmode == CHANNEL_WIDTH_40 && pregistrypriv->wifi_spec != 1)
set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R_13TO15_OFF);
else
+ #endif
set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R);
-#else /* CONFIG_DISABLE_MCS13TO15 */
- set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R);
-#endif /* CONFIG_DISABLE_MCS13TO15 */
break;
- case RF_3T3R:
+ case 3:
set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_3R);
break;
+ case 4:
+ set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_4R);
+ break;
default:
- RTW_INFO("[warning] rf_type %d is not expected\n", rf_type);
+ RTW_WARN("rf_type:%d or tx_nss_num:%u is not expected\n", rf_type, hal_spec->tx_nss_num);
}
/* switch to the 40M Hz mode accoring to the AP */
@@ -4264,46 +4799,6 @@ void rtw_update_ht_cap(_adapter *padapter, u8 *pie, uint ie_len, u8 channel)
/* Config current HT Protection mode. */
/* */
pmlmeinfo->HT_protection = pmlmeinfo->HT_info.infos[1] & 0x3;
-
-
-
-#if 0 /* move to rtw_update_sta_info_client() */
- /* for A-MPDU Rx reordering buffer control for bmc_sta & sta_info */
- /* if A-MPDU Rx is enabled, reseting rx_ordering_ctrl wstart_b(indicate_seq) to default value=0xffff */
- /* todo: check if AP can send A-MPDU packets */
- bmc_sta = rtw_get_bcmc_stainfo(padapter);
- if (bmc_sta) {
- for (i = 0; i < 16 ; i++) {
- /* preorder_ctrl = &precvpriv->recvreorder_ctrl[i]; */
- preorder_ctrl = &bmc_sta->recvreorder_ctrl[i];
- preorder_ctrl->enable = _FALSE;
- preorder_ctrl->indicate_seq = 0xffff;
-#ifdef DBG_RX_SEQ
- RTW_INFO("DBG_RX_SEQ %s:%d indicate_seq:%u\n", __FUNCTION__, __LINE__,
- preorder_ctrl->indicate_seq);
-#endif
- preorder_ctrl->wend_b = 0xffff;
- preorder_ctrl->wsize_b = 64;/* max_ampdu_sz; */ /* ex. 32(kbytes) -> wsize_b=32 */
- }
- }
-
- psta = rtw_get_stainfo(&padapter->stapriv, pcur_network->network.MacAddress);
- if (psta) {
- for (i = 0; i < 16 ; i++) {
- /* preorder_ctrl = &precvpriv->recvreorder_ctrl[i]; */
- preorder_ctrl = &psta->recvreorder_ctrl[i];
- preorder_ctrl->enable = _FALSE;
- preorder_ctrl->indicate_seq = 0xffff;
-#ifdef DBG_RX_SEQ
- RTW_INFO("DBG_RX_SEQ %s:%d indicate_seq:%u\n", __FUNCTION__, __LINE__,
- preorder_ctrl->indicate_seq);
-#endif
- preorder_ctrl->wend_b = 0xffff;
- preorder_ctrl->wsize_b = 64;/* max_ampdu_sz; */ /* ex. 32(kbytes) -> wsize_b=32 */
- }
- }
-#endif
-
}
#ifdef CONFIG_TDLS
@@ -4406,6 +4901,9 @@ void rtw_append_exented_cap(_adapter *padapter, u8 *out_ie, uint *pout_len)
if (pvhtpriv->vht_option)
SET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(cap_content, 1);
#endif /* CONFIG_80211AC_VHT */
+#ifdef CONFIG_RTW_WNM
+ rtw_wnm_set_ext_cap_btm(cap_content, 1);
+#endif
/*
From 802.11 specification,if a STA does not support any of capabilities defined
in the Extended Capabilities element, then the STA is not required to
@@ -4474,6 +4972,10 @@ void _rtw_roaming(_adapter *padapter, struct wlan_network *tgt_network)
continue;
else {
RTW_INFO("%s(%d) -to roaming fail, indicate_disconnect\n", __FUNCTION__, __LINE__);
+#ifdef CONFIG_RTW_80211R
+ rtw_ft_clr_flags(padapter, RTW_FT_PEER_EN|RTW_FT_PEER_OTD_EN);
+ rtw_ft_reset_status(padapter);
+#endif
rtw_indicate_disconnect(padapter, 0, _FALSE);
break;
}
@@ -4489,9 +4991,14 @@ bool rtw_adjust_chbw(_adapter *adapter, u8 req_ch, u8 *req_bw, u8 *req_offset)
struct registry_priv *regsty = adapter_to_regsty(adapter);
u8 allowed_bw;
- if (req_ch <= 14)
+ if (req_ch <= 14) {
allowed_bw = REGSTY_BW_2G(regsty);
- else
+ if (MLME_IS_MESH(adapter)) {
+ /* prevent secondary channel offset mismatch */
+ if (req_ch >= 5 && req_ch <= 9)
+ allowed_bw = CHANNEL_WIDTH_20;
+ }
+ } else
allowed_bw = REGSTY_BW_5G(regsty);
allowed_bw = hal_largest_bw(adapter, allowed_bw);
@@ -4511,8 +5018,9 @@ bool rtw_adjust_chbw(_adapter *adapter, u8 req_ch, u8 *req_bw, u8 *req_offset)
sint rtw_linked_check(_adapter *padapter)
{
- if ((check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) ||
- (check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) == _TRUE)) {
+ if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)
+ || MLME_IS_ADHOC(padapter) || MLME_IS_ADHOC_MASTER(padapter)
+ ) {
if (padapter->stapriv.asoc_sta_count > 2)
return _TRUE;
} else {
@@ -4522,23 +5030,33 @@ sint rtw_linked_check(_adapter *padapter)
}
return _FALSE;
}
+/*#define DBG_ADAPTER_STATE_CHK*/
u8 rtw_is_adapter_up(_adapter *padapter)
{
if (padapter == NULL)
return _FALSE;
if (RTW_CANNOT_RUN(padapter)) {
- RTW_INFO(FUNC_ADPT_FMT "-(bSurpriseRemoved == _TRUE) || ( bDriverStopped == _TRUE)\n", FUNC_ADPT_ARG(padapter));
+ #ifdef DBG_ADAPTER_STATE_CHK
+ RTW_INFO(FUNC_ADPT_FMT " FALSE -bDriverStopped(%s) bSurpriseRemoved(%s)\n"
+ , FUNC_ADPT_ARG(padapter)
+ , rtw_is_drv_stopped(padapter) ? "True" : "False"
+ , rtw_is_surprise_removed(padapter) ? "True" : "False");
+ #endif
return _FALSE;
}
if (!rtw_is_hw_init_completed(padapter)) {
- /*RTW_INFO(FUNC_ADPT_FMT "-(hw_init_completed == _FALSE)\n", FUNC_ADPT_ARG(padapter));*/
+ #ifdef DBG_ADAPTER_STATE_CHK
+ RTW_INFO(FUNC_ADPT_FMT " FALSE -(hw_init_completed == _FALSE)\n", FUNC_ADPT_ARG(padapter));
+ #endif
return _FALSE;
}
if (padapter->bup == _FALSE) {
- /*RTW_INFO(FUNC_ADPT_FMT "-(bup == _FALSE)\n", FUNC_ADPT_ARG(padapter));*/
+ #ifdef DBG_ADAPTER_STATE_CHK
+ RTW_INFO(FUNC_ADPT_FMT " FALSE -(bup == _FALSE)\n", FUNC_ADPT_ARG(padapter));
+ #endif
return _FALSE;
}
diff --git a/core/rtw_mlme_ext.c b/core/rtw_mlme_ext.c
index c256193..427cfd8 100644
--- a/core/rtw_mlme_ext.c
+++ b/core/rtw_mlme_ext.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,12 +11,7 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#define _RTW_MLME_EXT_C_
#include
@@ -78,17 +73,22 @@ struct action_handler OnAction_tbl[] = {
{RTW_WLAN_CATEGORY_DLS, "ACTION_DLS", &OnAction_dls},
{RTW_WLAN_CATEGORY_BACK, "ACTION_BACK", &OnAction_back},
{RTW_WLAN_CATEGORY_PUBLIC, "ACTION_PUBLIC", on_action_public},
- {RTW_WLAN_CATEGORY_RADIO_MEASUREMENT, "ACTION_RADIO_MEASUREMENT", &DoReserved},
- {RTW_WLAN_CATEGORY_FT, "ACTION_FT", &DoReserved},
+ {RTW_WLAN_CATEGORY_RADIO_MEAS, "ACTION_RADIO_MEAS", &on_action_rm},
+ {RTW_WLAN_CATEGORY_FT, "ACTION_FT", &OnAction_ft},
{RTW_WLAN_CATEGORY_HT, "ACTION_HT", &OnAction_ht},
#ifdef CONFIG_IEEE80211W
{RTW_WLAN_CATEGORY_SA_QUERY, "ACTION_SA_QUERY", &OnAction_sa_query},
#else
{RTW_WLAN_CATEGORY_SA_QUERY, "ACTION_SA_QUERY", &DoReserved},
#endif /* CONFIG_IEEE80211W */
- /* add for CONFIG_IEEE80211W */
+#ifdef CONFIG_RTW_WNM
+ {RTW_WLAN_CATEGORY_WNM, "ACTION_WNM", &on_action_wnm},
+#endif
{RTW_WLAN_CATEGORY_UNPROTECTED_WNM, "ACTION_UNPROTECTED_WNM", &DoReserved},
- {RTW_WLAN_CATEGORY_SELF_PROTECTED, "ACTION_SELF_PROTECTED", &DoReserved},
+#ifdef CONFIG_RTW_MESH
+ {RTW_WLAN_CATEGORY_MESH, "ACTION_MESH", &on_action_mesh},
+ {RTW_WLAN_CATEGORY_SELF_PROTECTED, "ACTION_SELF_PROTECTED", &on_action_self_protected},
+#endif
{RTW_WLAN_CATEGORY_WMM, "ACTION_WMM", &OnAction_wmm},
{RTW_WLAN_CATEGORY_VHT, "ACTION_VHT", &OnAction_vht},
{RTW_WLAN_CATEGORY_P2P, "ACTION_P2P", &OnAction_p2p},
@@ -143,166 +143,300 @@ static RT_CHANNEL_PLAN legacy_channel_plan[] = {
};
#endif
-static RT_CHANNEL_PLAN_2G RTW_ChannelPlan2G[] = {
- /* 0, RTW_RD_2G_NULL */ {{}, 0},
- /* 1, RTW_RD_2G_WORLD */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13},
- /* 2, RTW_RD_2G_ETSI1 */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13},
- /* 3, RTW_RD_2G_FCC1 */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11}, 11},
- /* 4, RTW_RD_2G_MKK1 */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14}, 14},
- /* 5, RTW_RD_2G_ETSI2 */ {{10, 11, 12, 13}, 4},
- /* 6, RTW_RD_2G_GLOBAL */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14}, 14},
- /* 7, RTW_RD_2G_MKK2 */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13},
- /* 8, RTW_RD_2G_FCC2 */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13},
+enum rtw_rd_2g {
+ RTW_RD_2G_NULL = 0,
+ RTW_RD_2G_WORLD = 1, /* Worldwird 13 */
+ RTW_RD_2G_ETSI1 = 2, /* Europe */
+ RTW_RD_2G_FCC1 = 3, /* US */
+ RTW_RD_2G_MKK1 = 4, /* Japan */
+ RTW_RD_2G_ETSI2 = 5, /* France */
+ RTW_RD_2G_GLOBAL = 6, /* Global domain */
+ RTW_RD_2G_MKK2 = 7, /* Japan */
+ RTW_RD_2G_FCC2 = 8, /* US */
+ RTW_RD_2G_IC1 = 9, /* Canada */
+ RTW_RD_2G_WORLD1 = 10, /* Worldwide 11 */
+
+ RTW_RD_2G_MAX,
+};
+
+enum rtw_rd_5g {
+ RTW_RD_5G_NULL = 0, /* */
+ RTW_RD_5G_ETSI1 = 1, /* Europe */
+ RTW_RD_5G_ETSI2 = 2, /* Australia, New Zealand */
+ RTW_RD_5G_ETSI3 = 3, /* Russia */
+ RTW_RD_5G_FCC1 = 4, /* US */
+ RTW_RD_5G_FCC2 = 5, /* FCC w/o DFS Channels */
+ RTW_RD_5G_FCC3 = 6, /* Bolivia, Chile, El Salvador, Venezuela */
+ RTW_RD_5G_FCC4 = 7, /* Venezuela */
+ RTW_RD_5G_FCC5 = 8, /* China */
+ RTW_RD_5G_FCC6 = 9, /* */
+ RTW_RD_5G_FCC7 = 10, /* US(w/o Weather radar) */
+ RTW_RD_5G_IC1 = 11, /* Canada(w/o Weather radar) */
+ RTW_RD_5G_KCC1 = 12, /* Korea */
+ RTW_RD_5G_MKK1 = 13, /* Japan */
+ RTW_RD_5G_MKK2 = 14, /* Japan (W52, W53) */
+ RTW_RD_5G_MKK3 = 15, /* Japan (W56) */
+ RTW_RD_5G_NCC1 = 16, /* Taiwan, (w/o Weather radar) */
+ RTW_RD_5G_NCC2 = 17, /* Taiwan, Band2, Band4 */
+ RTW_RD_5G_NCC3 = 18, /* Taiwan w/o DFS, Band4 only */
+ RTW_RD_5G_ETSI4 = 19, /* Europe w/o DFS, Band1 only */
+ RTW_RD_5G_ETSI5 = 20, /* Australia, New Zealand(w/o Weather radar) */
+ RTW_RD_5G_FCC8 = 21, /* Latin America */
+ RTW_RD_5G_ETSI6 = 22, /* Israel, Bahrain, Egypt, India, China, Malaysia */
+ RTW_RD_5G_ETSI7 = 23, /* China */
+ RTW_RD_5G_ETSI8 = 24, /* Jordan */
+ RTW_RD_5G_ETSI9 = 25, /* Lebanon */
+ RTW_RD_5G_ETSI10 = 26, /* Qatar */
+ RTW_RD_5G_ETSI11 = 27, /* Russia */
+ RTW_RD_5G_NCC4 = 28, /* Taiwan, (w/o Weather radar) */
+ RTW_RD_5G_ETSI12 = 29, /* Indonesia */
+ RTW_RD_5G_FCC9 = 30, /* (w/o Weather radar) */
+ RTW_RD_5G_ETSI13 = 31, /* (w/o Weather radar) */
+ RTW_RD_5G_FCC10 = 32, /* Argentina(w/o Weather radar) */
+ RTW_RD_5G_MKK4 = 33, /* Japan (W52) */
+ RTW_RD_5G_ETSI14 = 34, /* Russia */
+ RTW_RD_5G_FCC11 = 35, /* US(include CH144) */
+ RTW_RD_5G_ETSI15 = 36, /* Malaysia */
+ RTW_RD_5G_MKK5 = 37, /* Japan */
+ RTW_RD_5G_ETSI16 = 38, /* Europe */
+ RTW_RD_5G_ETSI17 = 39, /* Europe */
+ RTW_RD_5G_FCC12 = 40, /* FCC */
+ RTW_RD_5G_FCC13 = 41, /* FCC */
+ RTW_RD_5G_FCC14 = 42, /* FCC w/o Weather radar(w/o 5600~5650MHz) */
+ RTW_RD_5G_FCC15 = 43, /* FCC w/o Band3 */
+ RTW_RD_5G_FCC16 = 44, /* FCC w/o Band3 */
+ RTW_RD_5G_ETSI18 = 45, /* ETSI w/o DFS Band2&3 */
+ RTW_RD_5G_ETSI19 = 46, /* Europe */
+ RTW_RD_5G_FCC17 = 47, /* FCC w/o Weather radar(w/o 5600~5650MHz) */
+ RTW_RD_5G_ETSI20 = 48, /* Europe */
+ RTW_RD_5G_IC2 = 49, /* Canada(w/o Weather radar), include ch144 */
+ RTW_RD_5G_ETSI21 = 50, /* Australia, New Zealand(w/o Weather radar) */
+ RTW_RD_5G_FCC18 = 51, /* */
+ RTW_RD_5G_WORLD = 52, /* Worldwide */
+ RTW_RD_5G_CHILE1 = 53, /* Chile */
+ RTW_RD_5G_ACMA1 = 54, /* Australia, New Zealand (w/o Weather radar) (w/o Ch120~Ch128) */
+ RTW_RD_5G_WORLD1 = 55, /* 5G Worldwide Band1&2 */
+ RTW_RD_5G_CHILE2 = 56, /* Chile (Band2,Band3) */
+
+ /* === Below are driver defined for legacy channel plan compatible, DON'T assign index ==== */
+ RTW_RD_5G_OLD_FCC1,
+ RTW_RD_5G_OLD_NCC1,
+ RTW_RD_5G_OLD_KCC1,
+
+ RTW_RD_5G_MAX,
+};
+
+static struct ch_list_t RTW_ChannelPlan2G[] = {
+ /* 0, RTW_RD_2G_NULL */ CH_LIST_ENT(0),
+ /* 1, RTW_RD_2G_WORLD */ CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13),
+ /* 2, RTW_RD_2G_ETSI1 */ CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13),
+ /* 3, RTW_RD_2G_FCC1 */ CH_LIST_ENT(11, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11),
+ /* 4, RTW_RD_2G_MKK1 */ CH_LIST_ENT(14, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14),
+ /* 5, RTW_RD_2G_ETSI2 */ CH_LIST_ENT(4, 10, 11, 12, 13),
+ /* 6, RTW_RD_2G_GLOBAL */ CH_LIST_ENT(14, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14),
+ /* 7, RTW_RD_2G_MKK2 */ CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13),
+ /* 8, RTW_RD_2G_FCC2 */ CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13),
+ /* 9, RTW_RD_2G_IC1 */ CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13),
+ /* 10, RTW_RD_2G_WORLD1 */ CH_LIST_ENT(11, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11),
};
-static RT_CHANNEL_PLAN_5G RTW_ChannelPlan5G[] = {
- /* 0, RTW_RD_5G_NULL */ {{}, 0},
- /* 1, RTW_RD_5G_ETSI1 */ {{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 19},
- /* 2, RTW_RD_5G_ETSI2 */ {{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165}, 24},
- /* 3, RTW_RD_5G_ETSI3 */ {{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 149, 153, 157, 161, 165}, 22},
- /* 4, RTW_RD_5G_FCC1 */ {{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165}, 24},
- /* 5, RTW_RD_5G_FCC2 */ {{36, 40, 44, 48, 149, 153, 157, 161, 165}, 9},
- /* 6, RTW_RD_5G_FCC3 */ {{36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165}, 13},
- /* 7, RTW_RD_5G_FCC4 */ {{36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161}, 12},
- /* 8, RTW_RD_5G_FCC5 */ {{149, 153, 157, 161, 165}, 5},
- /* 9, RTW_RD_5G_FCC6 */ {{36, 40, 44, 48, 52, 56, 60, 64}, 8},
- /* 10, RTW_RD_5G_FCC7 */ {{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165}, 21},
- /* 11, RTW_RD_5G_KCC1 */ {{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 149, 153, 157, 161}, 19},
- /* 12, RTW_RD_5G_MKK1 */ {{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 19},
- /* 13, RTW_RD_5G_MKK2 */ {{36, 40, 44, 48, 52, 56, 60, 64}, 8},
- /* 14, RTW_RD_5G_MKK3 */ {{100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 11},
- /* 15, RTW_RD_5G_NCC1 */ {{56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165}, 16},
- /* 16, RTW_RD_5G_NCC2 */ {{56, 60, 64, 149, 153, 157, 161, 165}, 8},
- /* 17, RTW_RD_5G_NCC3 */ {{149, 153, 157, 161, 165}, 5},
- /* 18, RTW_RD_5G_ETSI4 */ {{36, 40, 44, 48}, 4},
- /* 19, RTW_RD_5G_ETSI5 */ {{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165}, 21},
- /* 20, RTW_RD_5G_FCC8 */ {{149, 153, 157, 161}, 4},
- /* 21, RTW_RD_5G_ETSI6 */ {{36, 40, 44, 48, 52, 56, 60, 64}, 8},
- /* 22, RTW_RD_5G_ETSI7 */ {{36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165}, 13},
- /* 23, RTW_RD_5G_ETSI8 */ {{36, 40, 44, 48, 149, 153, 157, 161, 165}, 9},
- /* 24, RTW_RD_5G_ETSI9 */ {{100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 11},
- /* 25, RTW_RD_5G_ETSI10 */ {{149, 153, 157, 161, 165}, 5},
- /* 26, RTW_RD_5G_ETSI11 */ {{36, 40, 44, 48, 52, 56, 60, 64, 132, 136, 140, 149, 153, 157, 161, 165}, 16},
- /* 27, RTW_RD_5G_NCC4 */ {{52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165}, 17},
- /* 28, RTW_RD_5G_ETSI12 */ {{149, 153, 157, 161}, 4},
- /* 29, RTW_RD_5G_FCC9 */ {{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165}, 21},
- /* 30, RTW_RD_5G_ETSI13 */ {{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140}, 16},
- /* 31, RTW_RD_5G_FCC10 */ {{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161}, 20},
- /* 32, RTW_RD_5G_MKK4 */ {{36, 40, 44, 48}, 4},
- /* 33, RTW_RD_5G_ETSI14 */ {{36, 40, 44, 48, 52, 56, 60, 64, 132, 136, 140}, 11},
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+static struct ch_list_t RTW_ChannelPlan5G[] = {
+ /* 0, RTW_RD_5G_NULL */ CH_LIST_ENT(0),
+ /* 1, RTW_RD_5G_ETSI1 */ CH_LIST_ENT(19, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140),
+ /* 2, RTW_RD_5G_ETSI2 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165),
+ /* 3, RTW_RD_5G_ETSI3 */ CH_LIST_ENT(22, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 149, 153, 157, 161, 165),
+ /* 4, RTW_RD_5G_FCC1 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165),
+ /* 5, RTW_RD_5G_FCC2 */ CH_LIST_ENT(9, 36, 40, 44, 48, 149, 153, 157, 161, 165),
+ /* 6, RTW_RD_5G_FCC3 */ CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165),
+ /* 7, RTW_RD_5G_FCC4 */ CH_LIST_ENT(12, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161),
+ /* 8, RTW_RD_5G_FCC5 */ CH_LIST_ENT(5, 149, 153, 157, 161, 165),
+ /* 9, RTW_RD_5G_FCC6 */ CH_LIST_ENT(8, 36, 40, 44, 48, 52, 56, 60, 64),
+ /* 10, RTW_RD_5G_FCC7 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165),
+ /* 11, RTW_RD_5G_IC1 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165),
+ /* 12, RTW_RD_5G_KCC1 */ CH_LIST_ENT(19, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 149, 153, 157, 161),
+ /* 13, RTW_RD_5G_MKK1 */ CH_LIST_ENT(19, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140),
+ /* 14, RTW_RD_5G_MKK2 */ CH_LIST_ENT(8, 36, 40, 44, 48, 52, 56, 60, 64),
+ /* 15, RTW_RD_5G_MKK3 */ CH_LIST_ENT(11, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140),
+ /* 16, RTW_RD_5G_NCC1 */ CH_LIST_ENT(16, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165),
+ /* 17, RTW_RD_5G_NCC2 */ CH_LIST_ENT(8, 56, 60, 64, 149, 153, 157, 161, 165),
+ /* 18, RTW_RD_5G_NCC3 */ CH_LIST_ENT(5, 149, 153, 157, 161, 165),
+ /* 19, RTW_RD_5G_ETSI4 */ CH_LIST_ENT(4, 36, 40, 44, 48),
+ /* 20, RTW_RD_5G_ETSI5 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165),
+ /* 21, RTW_RD_5G_FCC8 */ CH_LIST_ENT(4, 149, 153, 157, 161),
+ /* 22, RTW_RD_5G_ETSI6 */ CH_LIST_ENT(8, 36, 40, 44, 48, 52, 56, 60, 64),
+ /* 23, RTW_RD_5G_ETSI7 */ CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165),
+ /* 24, RTW_RD_5G_ETSI8 */ CH_LIST_ENT(9, 36, 40, 44, 48, 149, 153, 157, 161, 165),
+ /* 25, RTW_RD_5G_ETSI9 */ CH_LIST_ENT(11, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140),
+ /* 26, RTW_RD_5G_ETSI10 */ CH_LIST_ENT(5, 149, 153, 157, 161, 165),
+ /* 27, RTW_RD_5G_ETSI11 */ CH_LIST_ENT(16, 36, 40, 44, 48, 52, 56, 60, 64, 132, 136, 140, 149, 153, 157, 161, 165),
+ /* 28, RTW_RD_5G_NCC4 */ CH_LIST_ENT(17, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165),
+ /* 29, RTW_RD_5G_ETSI12 */ CH_LIST_ENT(4, 149, 153, 157, 161),
+ /* 30, RTW_RD_5G_FCC9 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165),
+ /* 31, RTW_RD_5G_ETSI13 */ CH_LIST_ENT(16, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140),
+ /* 32, RTW_RD_5G_FCC10 */ CH_LIST_ENT(20, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161),
+ /* 33, RTW_RD_5G_MKK4 */ CH_LIST_ENT(4, 36, 40, 44, 48),
+ /* 34, RTW_RD_5G_ETSI14 */ CH_LIST_ENT(11, 36, 40, 44, 48, 52, 56, 60, 64, 132, 136, 140),
+ /* 35, RTW_RD_5G_FCC11 */ CH_LIST_ENT(25, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 149, 153, 157, 161, 165),
+ /* 36, RTW_RD_5G_ETSI15 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 149, 153, 157, 161, 165),
+ /* 37, RTW_RD_5G_MKK5 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165),
+ /* 38, RTW_RD_5G_ETSI16 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165),
+ /* 39, RTW_RD_5G_ETSI17 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165),
+ /* 40, RTW_RD_5G_FCC12*/ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165),
+ /* 41, RTW_RD_5G_FCC13 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165),
+ /* 42, RTW_RD_5G_FCC14 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165),
+ /* 43, RTW_RD_5G_FCC15 */ CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165),
+ /* 44, RTW_RD_5G_FCC16 */ CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165),
+ /* 45, RTW_RD_5G_ETSI18 */ CH_LIST_ENT(9, 36, 40, 44, 48, 149, 153, 157, 161, 165),
+ /* 46, RTW_RD_5G_ETSI19 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165),
+ /* 47, RTW_RD_5G_FCC17 */ CH_LIST_ENT(16, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140),
+ /* 48, RTW_RD_5G_ETSI20 */ CH_LIST_ENT(9, 52, 56, 60, 64, 149, 153, 157, 161, 165),
+ /* 49, RTW_RD_5G_IC2 */ CH_LIST_ENT(22, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 144, 149, 153, 157, 161, 165),
+ /* 50, RTW_RD_5G_ETSI21 */ CH_LIST_ENT(13, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165),
+ /* 51, RTW_RD_5G_FCC18 */ CH_LIST_ENT(8, 100, 104, 108, 112, 116, 132, 136, 140),
+ /* 52, RTW_RD_5G_WORLD */ CH_LIST_ENT(25, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 149, 153, 157, 161, 165),
+ /* 53, RTW_RD_5G_CHILE1 */ CH_LIST_ENT(25, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 149, 153, 157, 161, 165),
+ /* 54, RTW_RD_5G_ACMA1 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165),
+ /* 55, RTW_RD_5G_WORLD1 */ CH_LIST_ENT(8, 36, 40, 44, 48, 52, 56, 60, 64),
+ /* 56, RTW_RD_5G_CHILE2 */ CH_LIST_ENT(16, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144),
/* === Below are driver defined for legacy channel plan compatible, NO static index assigned ==== */
- /* RTW_RD_5G_OLD_FCC1 */ {{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 20},
- /* RTW_RD_5G_OLD_NCC1 */ {{56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 15},
- /* RTW_RD_5G_OLD_KCC1 */ {{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 149, 153, 157, 161, 165}, 20},
+ /* RTW_RD_5G_OLD_FCC1 */ CH_LIST_ENT(20, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165),
+ /* RTW_RD_5G_OLD_NCC1 */ CH_LIST_ENT(15, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165),
+ /* RTW_RD_5G_OLD_KCC1 */ CH_LIST_ENT(20, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 149, 153, 157, 161, 165),
};
+#endif /* CONFIG_IEEE80211_BAND_5GHZ */
-static RT_CHANNEL_PLAN_MAP RTW_ChannelPlanMap[] = {
+static RT_CHANNEL_PLAN_MAP RTW_ChannelPlanMap[RTW_CHPLAN_MAX] = {
/* ===== 0x00 ~ 0x1F, legacy channel plan ===== */
- {RTW_RD_2G_FCC1, RTW_RD_5G_KCC1, TXPWR_LMT_FCC}, /* 0x00, RTW_CHPLAN_FCC */
- {RTW_RD_2G_FCC1, RTW_RD_5G_OLD_FCC1, TXPWR_LMT_FCC}, /* 0x01, RTW_CHPLAN_IC */
- {RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI1, TXPWR_LMT_ETSI}, /* 0x02, RTW_CHPLAN_ETSI */
- {RTW_RD_2G_ETSI1, RTW_RD_5G_NULL, TXPWR_LMT_ETSI}, /* 0x03, RTW_CHPLAN_SPAIN */
- {RTW_RD_2G_ETSI1, RTW_RD_5G_NULL, TXPWR_LMT_ETSI}, /* 0x04, RTW_CHPLAN_FRANCE */
- {RTW_RD_2G_MKK1, RTW_RD_5G_NULL, TXPWR_LMT_MKK}, /* 0x05, RTW_CHPLAN_MKK */
- {RTW_RD_2G_MKK1, RTW_RD_5G_NULL, TXPWR_LMT_MKK}, /* 0x06, RTW_CHPLAN_MKK1 */
- {RTW_RD_2G_ETSI1, RTW_RD_5G_FCC6, TXPWR_LMT_ETSI}, /* 0x07, RTW_CHPLAN_ISRAEL */
- {RTW_RD_2G_MKK1, RTW_RD_5G_FCC6, TXPWR_LMT_MKK}, /* 0x08, RTW_CHPLAN_TELEC */
- {RTW_RD_2G_MKK1, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x09, RTW_CHPLAN_GLOBAL_DOAMIN */
- {RTW_RD_2G_WORLD, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x0A, RTW_CHPLAN_WORLD_WIDE_13 */
- {RTW_RD_2G_FCC1, RTW_RD_5G_OLD_NCC1, TXPWR_LMT_FCC}, /* 0x0B, RTW_CHPLAN_TAIWAN */
- {RTW_RD_2G_ETSI1, RTW_RD_5G_FCC5, TXPWR_LMT_ETSI}, /* 0x0C, RTW_CHPLAN_CHINA */
- {RTW_RD_2G_FCC1, RTW_RD_5G_FCC3, TXPWR_LMT_WW}, /* 0x0D, RTW_CHPLAN_SINGAPORE_INDIA_MEXICO */ /* ETSI:Singapore, India. FCC:Mexico => WW */
- {RTW_RD_2G_FCC1, RTW_RD_5G_OLD_KCC1, TXPWR_LMT_ETSI}, /* 0x0E, RTW_CHPLAN_KOREA */
- {RTW_RD_2G_FCC1, RTW_RD_5G_FCC6, TXPWR_LMT_ETSI}, /* 0x0F, RTW_CHPLAN_TURKEY */
- {RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI1, TXPWR_LMT_MKK}, /* 0x10, RTW_CHPLAN_JAPAN */
- {RTW_RD_2G_FCC1, RTW_RD_5G_FCC2, TXPWR_LMT_FCC}, /* 0x11, RTW_CHPLAN_FCC_NO_DFS */
- {RTW_RD_2G_ETSI1, RTW_RD_5G_FCC7, TXPWR_LMT_MKK}, /* 0x12, RTW_CHPLAN_JAPAN_NO_DFS */
- {RTW_RD_2G_WORLD, RTW_RD_5G_FCC1, TXPWR_LMT_WW}, /* 0x13, RTW_CHPLAN_WORLD_WIDE_5G */
- {RTW_RD_2G_FCC1, RTW_RD_5G_NCC2, TXPWR_LMT_FCC}, /* 0x14, RTW_CHPLAN_TAIWAN_NO_DFS */
- {RTW_RD_2G_WORLD, RTW_RD_5G_FCC7, TXPWR_LMT_ETSI}, /* 0x15, RTW_CHPLAN_ETSI_NO_DFS */
- {RTW_RD_2G_WORLD, RTW_RD_5G_NCC1, TXPWR_LMT_ETSI}, /* 0x16, RTW_CHPLAN_KOREA_NO_DFS */
- {RTW_RD_2G_MKK1, RTW_RD_5G_FCC7, TXPWR_LMT_MKK}, /* 0x17, RTW_CHPLAN_JAPAN_NO_DFS */
- {RTW_RD_2G_NULL, RTW_RD_5G_FCC5, TXPWR_LMT_ETSI}, /* 0x18, RTW_CHPLAN_PAKISTAN_NO_DFS */
- {RTW_RD_2G_FCC1, RTW_RD_5G_FCC5, TXPWR_LMT_FCC}, /* 0x19, RTW_CHPLAN_TAIWAN2_NO_DFS */
- {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x1A, */
- {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x1B, */
- {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x1C, */
- {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x1D, */
- {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x1E, */
- {RTW_RD_2G_NULL, RTW_RD_5G_FCC1, TXPWR_LMT_WW}, /* 0x1F, RTW_CHPLAN_WORLD_WIDE_ONLY_5G */
+ CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_KCC1, TXPWR_LMT_FCC), /* 0x00, RTW_CHPLAN_FCC */
+ CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_OLD_FCC1, TXPWR_LMT_FCC), /* 0x01, RTW_CHPLAN_IC */
+ CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI1, TXPWR_LMT_ETSI), /* 0x02, RTW_CHPLAN_ETSI */
+ CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_NULL, TXPWR_LMT_ETSI), /* 0x03, RTW_CHPLAN_SPAIN */
+ CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_NULL, TXPWR_LMT_ETSI), /* 0x04, RTW_CHPLAN_FRANCE */
+ CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_NULL, TXPWR_LMT_MKK), /* 0x05, RTW_CHPLAN_MKK */
+ CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_NULL, TXPWR_LMT_MKK), /* 0x06, RTW_CHPLAN_MKK1 */
+ CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_FCC6, TXPWR_LMT_ETSI), /* 0x07, RTW_CHPLAN_ISRAEL */
+ CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_FCC6, TXPWR_LMT_MKK), /* 0x08, RTW_CHPLAN_TELEC */
+ CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x09, RTW_CHPLAN_GLOBAL_DOAMIN */
+ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x0A, RTW_CHPLAN_WORLD_WIDE_13 */
+ CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_OLD_NCC1, TXPWR_LMT_FCC), /* 0x0B, RTW_CHPLAN_TAIWAN */
+ CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_FCC5, TXPWR_LMT_ETSI), /* 0x0C, RTW_CHPLAN_CHINA */
+ CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC3, TXPWR_LMT_WW), /* 0x0D, RTW_CHPLAN_SINGAPORE_INDIA_MEXICO */ /* ETSI:Singapore, India. FCC:Mexico => WW */
+ CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_OLD_KCC1, TXPWR_LMT_ETSI), /* 0x0E, RTW_CHPLAN_KOREA */
+ CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC6, TXPWR_LMT_ETSI), /* 0x0F, RTW_CHPLAN_TURKEY */
+ CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI1, TXPWR_LMT_MKK), /* 0x10, RTW_CHPLAN_JAPAN */
+ CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC2, TXPWR_LMT_FCC), /* 0x11, RTW_CHPLAN_FCC_NO_DFS */
+ CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_FCC7, TXPWR_LMT_MKK), /* 0x12, RTW_CHPLAN_JAPAN_NO_DFS */
+ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC1, TXPWR_LMT_WW), /* 0x13, RTW_CHPLAN_WORLD_WIDE_5G */
+ CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_NCC2, TXPWR_LMT_FCC), /* 0x14, RTW_CHPLAN_TAIWAN_NO_DFS */
+ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC7, TXPWR_LMT_ETSI), /* 0x15, RTW_CHPLAN_ETSI_NO_DFS */
+ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_NCC1, TXPWR_LMT_ETSI), /* 0x16, RTW_CHPLAN_KOREA_NO_DFS */
+ CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_FCC7, TXPWR_LMT_MKK), /* 0x17, RTW_CHPLAN_JAPAN_NO_DFS */
+ CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_FCC5, TXPWR_LMT_ETSI), /* 0x18, RTW_CHPLAN_PAKISTAN_NO_DFS */
+ CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC5, TXPWR_LMT_FCC), /* 0x19, RTW_CHPLAN_TAIWAN2_NO_DFS */
+ CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x1A, */
+ CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x1B, */
+ CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x1C, */
+ CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x1D, */
+ CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x1E, */
+ CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_FCC1, TXPWR_LMT_WW), /* 0x1F, RTW_CHPLAN_WORLD_WIDE_ONLY_5G */
/* ===== 0x20 ~ 0x7F, new channel plan ===== */
- {RTW_RD_2G_WORLD, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x20, RTW_CHPLAN_WORLD_NULL */
- {RTW_RD_2G_ETSI1, RTW_RD_5G_NULL, TXPWR_LMT_ETSI}, /* 0x21, RTW_CHPLAN_ETSI1_NULL */
- {RTW_RD_2G_FCC1, RTW_RD_5G_NULL, TXPWR_LMT_FCC}, /* 0x22, RTW_CHPLAN_FCC1_NULL */
- {RTW_RD_2G_MKK1, RTW_RD_5G_NULL, TXPWR_LMT_MKK}, /* 0x23, RTW_CHPLAN_MKK1_NULL */
- {RTW_RD_2G_ETSI2, RTW_RD_5G_NULL, TXPWR_LMT_ETSI}, /* 0x24, RTW_CHPLAN_ETSI2_NULL */
- {RTW_RD_2G_FCC1, RTW_RD_5G_FCC1, TXPWR_LMT_FCC}, /* 0x25, RTW_CHPLAN_FCC1_FCC1 */
- {RTW_RD_2G_WORLD, RTW_RD_5G_ETSI1, TXPWR_LMT_ETSI}, /* 0x26, RTW_CHPLAN_WORLD_ETSI1 */
- {RTW_RD_2G_MKK1, RTW_RD_5G_MKK1, TXPWR_LMT_MKK}, /* 0x27, RTW_CHPLAN_MKK1_MKK1 */
- {RTW_RD_2G_WORLD, RTW_RD_5G_KCC1, TXPWR_LMT_ETSI}, /* 0x28, RTW_CHPLAN_WORLD_KCC1 */
- {RTW_RD_2G_WORLD, RTW_RD_5G_FCC2, TXPWR_LMT_FCC}, /* 0x29, RTW_CHPLAN_WORLD_FCC2 */
- {RTW_RD_2G_FCC2, RTW_RD_5G_NULL, TXPWR_LMT_FCC}, /* 0x2A, RTW_CHPLAN_FCC2_NULL */
- {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x2B, */
- {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x2C, */
- {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x2D, */
- {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x2E, */
- {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x2F, */
- {RTW_RD_2G_WORLD, RTW_RD_5G_FCC3, TXPWR_LMT_FCC}, /* 0x30, RTW_CHPLAN_WORLD_FCC3 */
- {RTW_RD_2G_WORLD, RTW_RD_5G_FCC4, TXPWR_LMT_FCC}, /* 0x31, RTW_CHPLAN_WORLD_FCC4 */
- {RTW_RD_2G_WORLD, RTW_RD_5G_FCC5, TXPWR_LMT_FCC}, /* 0x32, RTW_CHPLAN_WORLD_FCC5 */
- {RTW_RD_2G_WORLD, RTW_RD_5G_FCC6, TXPWR_LMT_FCC}, /* 0x33, RTW_CHPLAN_WORLD_FCC6 */
- {RTW_RD_2G_FCC1, RTW_RD_5G_FCC7, TXPWR_LMT_FCC}, /* 0x34, RTW_CHPLAN_FCC1_FCC7 */
- {RTW_RD_2G_WORLD, RTW_RD_5G_ETSI2, TXPWR_LMT_ETSI}, /* 0x35, RTW_CHPLAN_WORLD_ETSI2 */
- {RTW_RD_2G_WORLD, RTW_RD_5G_ETSI3, TXPWR_LMT_ETSI}, /* 0x36, RTW_CHPLAN_WORLD_ETSI3 */
- {RTW_RD_2G_MKK1, RTW_RD_5G_MKK2, TXPWR_LMT_MKK}, /* 0x37, RTW_CHPLAN_MKK1_MKK2 */
- {RTW_RD_2G_MKK1, RTW_RD_5G_MKK3, TXPWR_LMT_MKK}, /* 0x38, RTW_CHPLAN_MKK1_MKK3 */
- {RTW_RD_2G_FCC1, RTW_RD_5G_NCC1, TXPWR_LMT_FCC}, /* 0x39, RTW_CHPLAN_FCC1_NCC1 */
- {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x3A, */
- {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x3B, */
- {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x3C, */
- {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x3D, */
- {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x3E, */
- {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x3F, */
- {RTW_RD_2G_FCC1, RTW_RD_5G_NCC2, TXPWR_LMT_FCC}, /* 0x40, RTW_CHPLAN_FCC1_NCC2 */
- {RTW_RD_2G_GLOBAL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x41, RTW_CHPLAN_GLOBAL_NULL */
- {RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI4, TXPWR_LMT_ETSI}, /* 0x42, RTW_CHPLAN_ETSI1_ETSI4 */
- {RTW_RD_2G_FCC1, RTW_RD_5G_FCC2, TXPWR_LMT_FCC}, /* 0x43, RTW_CHPLAN_FCC1_FCC2 */
- {RTW_RD_2G_FCC1, RTW_RD_5G_NCC3, TXPWR_LMT_FCC}, /* 0x44, RTW_CHPLAN_FCC1_NCC3 */
- {RTW_RD_2G_WORLD, RTW_RD_5G_ETSI5, TXPWR_LMT_ETSI}, /* 0x45, RTW_CHPLAN_WORLD_ETSI5 */
- {RTW_RD_2G_FCC1, RTW_RD_5G_FCC8, TXPWR_LMT_FCC}, /* 0x46, RTW_CHPLAN_FCC1_FCC8 */
- {RTW_RD_2G_WORLD, RTW_RD_5G_ETSI6, TXPWR_LMT_ETSI}, /* 0x47, RTW_CHPLAN_WORLD_ETSI6 */
- {RTW_RD_2G_WORLD, RTW_RD_5G_ETSI7, TXPWR_LMT_ETSI}, /* 0x48, RTW_CHPLAN_WORLD_ETSI7 */
- {RTW_RD_2G_WORLD, RTW_RD_5G_ETSI8, TXPWR_LMT_ETSI}, /* 0x49, RTW_CHPLAN_WORLD_ETSI8 */
- {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x4A, */
- {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x4B, */
- {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x4C, */
- {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x4D, */
- {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x4E, */
- {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x4F, */
- {RTW_RD_2G_WORLD, RTW_RD_5G_ETSI9, TXPWR_LMT_ETSI}, /* 0x50, RTW_CHPLAN_WORLD_ETSI9 */
- {RTW_RD_2G_WORLD, RTW_RD_5G_ETSI10, TXPWR_LMT_ETSI}, /* 0x51, RTW_CHPLAN_WORLD_ETSI10 */
- {RTW_RD_2G_WORLD, RTW_RD_5G_ETSI11, TXPWR_LMT_ETSI}, /* 0x52, RTW_CHPLAN_WORLD_ETSI11 */
- {RTW_RD_2G_FCC1, RTW_RD_5G_NCC4, TXPWR_LMT_FCC}, /* 0x53, RTW_CHPLAN_FCC1_NCC4 */
- {RTW_RD_2G_WORLD, RTW_RD_5G_ETSI12, TXPWR_LMT_ETSI}, /* 0x54, RTW_CHPLAN_WORLD_ETSI12 */
- {RTW_RD_2G_FCC1, RTW_RD_5G_FCC9, TXPWR_LMT_FCC}, /* 0x55, RTW_CHPLAN_FCC1_FCC9 */
- {RTW_RD_2G_WORLD, RTW_RD_5G_ETSI13, TXPWR_LMT_ETSI}, /* 0x56, RTW_CHPLAN_WORLD_ETSI13 */
- {RTW_RD_2G_FCC1, RTW_RD_5G_FCC10, TXPWR_LMT_FCC}, /* 0x57, RTW_CHPLAN_FCC1_FCC10 */
- {RTW_RD_2G_MKK2, RTW_RD_5G_MKK4, TXPWR_LMT_MKK}, /* 0x58, RTW_CHPLAN_MKK2_MKK4 */
- {RTW_RD_2G_WORLD, RTW_RD_5G_ETSI14, TXPWR_LMT_ETSI}, /* 0x59, RTW_CHPLAN_WORLD_ETSI14 */
- {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x5A, */
- {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x5B, */
- {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x5C, */
- {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x5D, */
- {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x5E, */
- {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x5F, */
- {RTW_RD_2G_FCC1, RTW_RD_5G_FCC5, TXPWR_LMT_FCC}, /* 0x60, RTW_CHPLAN_FCC1_FCC5 */
+ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x20, RTW_CHPLAN_WORLD_NULL */
+ CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_NULL, TXPWR_LMT_ETSI), /* 0x21, RTW_CHPLAN_ETSI1_NULL */
+ CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_NULL, TXPWR_LMT_FCC), /* 0x22, RTW_CHPLAN_FCC1_NULL */
+ CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_NULL, TXPWR_LMT_MKK), /* 0x23, RTW_CHPLAN_MKK1_NULL */
+ CHPLAN_ENT(RTW_RD_2G_ETSI2, RTW_RD_5G_NULL, TXPWR_LMT_ETSI), /* 0x24, RTW_CHPLAN_ETSI2_NULL */
+ CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC1, TXPWR_LMT_FCC), /* 0x25, RTW_CHPLAN_FCC1_FCC1 */
+ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI1, TXPWR_LMT_ETSI), /* 0x26, RTW_CHPLAN_WORLD_ETSI1 */
+ CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_MKK1, TXPWR_LMT_MKK), /* 0x27, RTW_CHPLAN_MKK1_MKK1 */
+ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_KCC1, TXPWR_LMT_KCC), /* 0x28, RTW_CHPLAN_WORLD_KCC1 */
+ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC2, TXPWR_LMT_FCC), /* 0x29, RTW_CHPLAN_WORLD_FCC2 */
+ CHPLAN_ENT(RTW_RD_2G_FCC2, RTW_RD_5G_NULL, TXPWR_LMT_FCC), /* 0x2A, RTW_CHPLAN_FCC2_NULL */
+ CHPLAN_ENT(RTW_RD_2G_IC1, RTW_RD_5G_IC2, TXPWR_LMT_IC), /* 0x2B, RTW_CHPLAN_IC1_IC2 */
+ CHPLAN_ENT(RTW_RD_2G_MKK2, RTW_RD_5G_NULL, TXPWR_LMT_MKK), /* 0x2C, RTW_CHPLAN_MKK2_NULL */
+ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_CHILE1, TXPWR_LMT_CHILE), /* 0x2D, RTW_CHPLAN_WORLD_CHILE1 */
+ CHPLAN_ENT(RTW_RD_2G_WORLD1, RTW_RD_5G_WORLD1, TXPWR_LMT_WW), /* 0x2E, RTW_CHPLAN_WORLD1_WORLD1 */
+ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_CHILE2, TXPWR_LMT_CHILE), /* 0x2F, RTW_CHPLAN_WORLD_CHILE2 */
+ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC3, TXPWR_LMT_FCC), /* 0x30, RTW_CHPLAN_WORLD_FCC3 */
+ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC4, TXPWR_LMT_FCC), /* 0x31, RTW_CHPLAN_WORLD_FCC4 */
+ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC5, TXPWR_LMT_FCC), /* 0x32, RTW_CHPLAN_WORLD_FCC5 */
+ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC6, TXPWR_LMT_FCC), /* 0x33, RTW_CHPLAN_WORLD_FCC6 */
+ CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC7, TXPWR_LMT_FCC), /* 0x34, RTW_CHPLAN_FCC1_FCC7 */
+ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI2, TXPWR_LMT_ETSI), /* 0x35, RTW_CHPLAN_WORLD_ETSI2 */
+ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI3, TXPWR_LMT_ETSI), /* 0x36, RTW_CHPLAN_WORLD_ETSI3 */
+ CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_MKK2, TXPWR_LMT_MKK), /* 0x37, RTW_CHPLAN_MKK1_MKK2 */
+ CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_MKK3, TXPWR_LMT_MKK), /* 0x38, RTW_CHPLAN_MKK1_MKK3 */
+ CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_NCC1, TXPWR_LMT_FCC), /* 0x39, RTW_CHPLAN_FCC1_NCC1 */
+ CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI1, TXPWR_LMT_ETSI), /* 0x3A, RTW_CHPLAN_ETSI1_ETSI1 */
+ CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_ACMA1, TXPWR_LMT_ACMA), /* 0x3B, RTW_CHPLAN_ETSI1_ACMA1 */
+ CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI6, TXPWR_LMT_ETSI), /* 0x3C, RTW_CHPLAN_ETSI1_ETSI6 */
+ CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI12, TXPWR_LMT_ETSI), /* 0x3D, RTW_CHPLAN_ETSI1_ETSI12 */
+ CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x3E, */
+ CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x3F, */
+ CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_NCC2, TXPWR_LMT_FCC), /* 0x40, RTW_CHPLAN_FCC1_NCC2 */
+ CHPLAN_ENT(RTW_RD_2G_GLOBAL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x41, RTW_CHPLAN_GLOBAL_NULL */
+ CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI4, TXPWR_LMT_ETSI), /* 0x42, RTW_CHPLAN_ETSI1_ETSI4 */
+ CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC2, TXPWR_LMT_FCC), /* 0x43, RTW_CHPLAN_FCC1_FCC2 */
+ CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_NCC3, TXPWR_LMT_FCC), /* 0x44, RTW_CHPLAN_FCC1_NCC3 */
+ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ACMA1, TXPWR_LMT_ACMA), /* 0x45, RTW_CHPLAN_WORLD_ACMA1 */
+ CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC8, TXPWR_LMT_FCC), /* 0x46, RTW_CHPLAN_FCC1_FCC8 */
+ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI6, TXPWR_LMT_ETSI), /* 0x47, RTW_CHPLAN_WORLD_ETSI6 */
+ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI7, TXPWR_LMT_ETSI), /* 0x48, RTW_CHPLAN_WORLD_ETSI7 */
+ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI8, TXPWR_LMT_ETSI), /* 0x49, RTW_CHPLAN_WORLD_ETSI8 */
+ CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x4A, */
+ CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x4B, */
+ CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x4C, */
+ CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x4D, */
+ CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x4E, */
+ CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x4F, */
+ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI9, TXPWR_LMT_ETSI), /* 0x50, RTW_CHPLAN_WORLD_ETSI9 */
+ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI10, TXPWR_LMT_ETSI), /* 0x51, RTW_CHPLAN_WORLD_ETSI10 */
+ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI11, TXPWR_LMT_ETSI), /* 0x52, RTW_CHPLAN_WORLD_ETSI11 */
+ CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_NCC4, TXPWR_LMT_FCC), /* 0x53, RTW_CHPLAN_FCC1_NCC4 */
+ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI12, TXPWR_LMT_ETSI), /* 0x54, RTW_CHPLAN_WORLD_ETSI12 */
+ CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC9, TXPWR_LMT_FCC), /* 0x55, RTW_CHPLAN_FCC1_FCC9 */
+ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI13, TXPWR_LMT_ETSI), /* 0x56, RTW_CHPLAN_WORLD_ETSI13 */
+ CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC10, TXPWR_LMT_FCC), /* 0x57, RTW_CHPLAN_FCC1_FCC10 */
+ CHPLAN_ENT(RTW_RD_2G_MKK2, RTW_RD_5G_MKK4, TXPWR_LMT_MKK), /* 0x58, RTW_CHPLAN_MKK2_MKK4 */
+ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI14, TXPWR_LMT_ETSI), /* 0x59, RTW_CHPLAN_WORLD_ETSI14 */
+ CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x5A, */
+ CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x5B, */
+ CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x5C, */
+ CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x5D, */
+ CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x5E, */
+ CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x5F, */
+ CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC5, TXPWR_LMT_FCC), /* 0x60, RTW_CHPLAN_FCC1_FCC5 */
+ CHPLAN_ENT(RTW_RD_2G_FCC2, RTW_RD_5G_FCC7, TXPWR_LMT_FCC), /* 0x61, RTW_CHPLAN_FCC2_FCC7 */
+ CHPLAN_ENT(RTW_RD_2G_FCC2, RTW_RD_5G_FCC1, TXPWR_LMT_FCC), /* 0x62, RTW_CHPLAN_FCC2_FCC1 */
+ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI15, TXPWR_LMT_ETSI), /* 0x63, RTW_CHPLAN_WORLD_ETSI15 */
+ CHPLAN_ENT(RTW_RD_2G_MKK2, RTW_RD_5G_MKK5, TXPWR_LMT_MKK), /* 0x64, RTW_CHPLAN_MKK2_MKK5 */
+ CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI16, TXPWR_LMT_ETSI), /* 0x65, RTW_CHPLAN_ETSI1_ETSI16 */
+ CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC14, TXPWR_LMT_FCC), /* 0x66, RTW_CHPLAN_FCC1_FCC14 */
+ CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC12, TXPWR_LMT_FCC), /* 0x67, RTW_CHPLAN_FCC1_FCC12 */
+ CHPLAN_ENT(RTW_RD_2G_FCC2, RTW_RD_5G_FCC14, TXPWR_LMT_FCC), /* 0x68, RTW_CHPLAN_FCC2_FCC14 */
+ CHPLAN_ENT(RTW_RD_2G_FCC2, RTW_RD_5G_FCC12, TXPWR_LMT_FCC), /* 0x69, RTW_CHPLAN_FCC2_FCC12 */
+ CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI17, TXPWR_LMT_ETSI), /* 0x6A, RTW_CHPLAN_ETSI1_ETSI17 */
+ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC16, TXPWR_LMT_FCC), /* 0x6B, RTW_CHPLAN_WORLD_FCC16 */
+ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC13, TXPWR_LMT_FCC), /* 0x6C, RTW_CHPLAN_WORLD_FCC13 */
+ CHPLAN_ENT(RTW_RD_2G_FCC2, RTW_RD_5G_FCC15, TXPWR_LMT_FCC), /* 0x6D, RTW_CHPLAN_FCC2_FCC15 */
+ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC12, TXPWR_LMT_FCC), /* 0x6E, RTW_CHPLAN_WORLD_FCC12 */
+ CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_ETSI8, TXPWR_LMT_ETSI), /* 0x6F, RTW_CHPLAN_NULL_ETSI8 */
+ CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_ETSI18, TXPWR_LMT_ETSI), /* 0x70, RTW_CHPLAN_NULL_ETSI18 */
+ CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_ETSI17, TXPWR_LMT_ETSI), /* 0x71, RTW_CHPLAN_NULL_ETSI17 */
+ CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_ETSI19, TXPWR_LMT_ETSI), /* 0x72, RTW_CHPLAN_NULL_ETSI19 */
+ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC7, TXPWR_LMT_FCC), /* 0x73, RTW_CHPLAN_WORLD_FCC7 */
+ CHPLAN_ENT(RTW_RD_2G_FCC2, RTW_RD_5G_FCC17, TXPWR_LMT_FCC), /* 0x74, RTW_CHPLAN_FCC2_FCC17 */
+ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI20, TXPWR_LMT_ETSI), /* 0x75, RTW_CHPLAN_WORLD_ETSI20 */
+ CHPLAN_ENT(RTW_RD_2G_FCC2, RTW_RD_5G_FCC11, TXPWR_LMT_FCC), /* 0x76, RTW_CHPLAN_FCC2_FCC11 */
+ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI21, TXPWR_LMT_ETSI), /* 0x77, RTW_CHPLAN_WORLD_ETSI21 */
+ CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC18, TXPWR_LMT_FCC), /* 0x78, RTW_CHPLAN_FCC1_FCC18 */
+ CHPLAN_ENT(RTW_RD_2G_MKK2, RTW_RD_5G_MKK1, TXPWR_LMT_MKK), /* 0x79, RTW_CHPLAN_MKK2_MKK1 */
};
-static RT_CHANNEL_PLAN_MAP RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE = {
- RTW_RD_2G_WORLD, RTW_RD_5G_FCC1, TXPWR_LMT_FCC /* 0x7F, Realtek Define */
-};
+static RT_CHANNEL_PLAN_MAP RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE =
+ CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC1, TXPWR_LMT_FCC); /* 0x7F, Realtek Define */
bool rtw_chplan_is_empty(u8 id)
{
@@ -314,17 +448,358 @@ bool rtw_chplan_is_empty(u8 id)
chplan_map = &RTW_ChannelPlanMap[id];
if (chplan_map->Index2G == RTW_RD_2G_NULL
- && chplan_map->Index5G == RTW_RD_5G_NULL)
+ #ifdef CONFIG_IEEE80211_BAND_5GHZ
+ && chplan_map->Index5G == RTW_RD_5G_NULL
+ #endif
+ )
return _TRUE;
return _FALSE;
}
+bool rtw_regsty_is_excl_chs(struct registry_priv *regsty, u8 ch)
+{
+ int i;
+
+ for (i = 0; i < MAX_CHANNEL_NUM; i++) {
+ if (regsty->excl_chs[i] == 0)
+ break;
+ if (regsty->excl_chs[i] == ch)
+ return _TRUE;
+ }
+ return _FALSE;
+}
+
+inline u8 rtw_rd_5g_band1_passive(u8 rtw_rd_5g)
+{
+ u8 passive = 0;
+
+ switch (rtw_rd_5g) {
+ case RTW_RD_5G_FCC13:
+ case RTW_RD_5G_FCC16:
+ case RTW_RD_5G_ETSI18:
+ case RTW_RD_5G_ETSI19:
+ case RTW_RD_5G_WORLD:
+ case RTW_RD_5G_WORLD1:
+ passive = 1;
+ };
+
+ return passive;
+}
+
+inline u8 rtw_rd_5g_band4_passive(u8 rtw_rd_5g)
+{
+ u8 passive = 0;
+
+ switch (rtw_rd_5g) {
+ case RTW_RD_5G_MKK5:
+ case RTW_RD_5G_ETSI16:
+ case RTW_RD_5G_ETSI18:
+ case RTW_RD_5G_ETSI19:
+ case RTW_RD_5G_WORLD:
+ passive = 1;
+ };
+
+ return passive;
+}
+
+static void init_channel_list(_adapter *padapter, RT_CHANNEL_INFO *channel_set
+ , struct p2p_channels *channel_list)
+{
+ struct registry_priv *regsty = adapter_to_regsty(padapter);
+
+ struct p2p_oper_class_map op_class[] = {
+ { IEEE80211G, 81, 1, 13, 1, BW20 },
+ { IEEE80211G, 82, 14, 14, 1, BW20 },
+#if 0 /* Do not enable HT40 on 2 GHz */
+ { IEEE80211G, 83, 1, 9, 1, BW40PLUS },
+ { IEEE80211G, 84, 5, 13, 1, BW40MINUS },
+#endif
+ { IEEE80211A, 115, 36, 48, 4, BW20 },
+ { IEEE80211A, 116, 36, 44, 8, BW40PLUS },
+ { IEEE80211A, 117, 40, 48, 8, BW40MINUS },
+ { IEEE80211A, 124, 149, 161, 4, BW20 },
+ { IEEE80211A, 125, 149, 169, 4, BW20 },
+ { IEEE80211A, 126, 149, 157, 8, BW40PLUS },
+ { IEEE80211A, 127, 153, 161, 8, BW40MINUS },
+ { -1, 0, 0, 0, 0, BW20 }
+ };
+
+ int cla, op;
+
+ cla = 0;
+
+ for (op = 0; op_class[op].op_class; op++) {
+ u8 ch;
+ struct p2p_oper_class_map *o = &op_class[op];
+ struct p2p_reg_class *reg = NULL;
+
+ for (ch = o->min_chan; ch <= o->max_chan; ch += o->inc) {
+ if (rtw_chset_search_ch(channel_set, ch) == -1)
+ continue;
+
+ if ((padapter->registrypriv.ht_enable == 0) && (o->inc == 8))
+ continue;
+
+ if ((REGSTY_IS_BW_5G_SUPPORT(regsty, CHANNEL_WIDTH_40)) &&
+ ((o->bw == BW40MINUS) || (o->bw == BW40PLUS)))
+ continue;
+
+ if (reg == NULL) {
+ reg = &channel_list->reg_class[cla];
+ cla++;
+ reg->reg_class = o->op_class;
+ reg->channels = 0;
+ }
+ reg->channel[reg->channels] = ch;
+ reg->channels++;
+ }
+ }
+ channel_list->reg_classes = cla;
+
+}
+
+static u8 init_channel_set(_adapter *padapter, u8 ChannelPlan, RT_CHANNEL_INFO *channel_set)
+{
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
+ struct registry_priv *regsty = adapter_to_regsty(padapter);
+ u8 index, chanset_size = 0;
+ u8 b5GBand = _FALSE, b2_4GBand = _FALSE;
+ u8 Index2G = 0, Index5G = 0;
+ int i;
+
+ if (!rtw_is_channel_plan_valid(ChannelPlan)) {
+ RTW_ERR("ChannelPlan ID 0x%02X error !!!!!\n", ChannelPlan);
+ return chanset_size;
+ }
+
+ _rtw_memset(channel_set, 0, sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM);
+
+ if (IsSupported24G(regsty->wireless_mode) && hal_chk_band_cap(padapter, BAND_CAP_2G))
+ b2_4GBand = _TRUE;
+
+ if (is_supported_5g(regsty->wireless_mode) && hal_chk_band_cap(padapter, BAND_CAP_5G))
+ b5GBand = _TRUE;
+
+ if (b2_4GBand == _FALSE && b5GBand == _FALSE) {
+ RTW_WARN("HW band_cap has no intersection with SW wireless_mode setting\n");
+ return chanset_size;
+ }
+
+ if (b2_4GBand) {
+ if (ChannelPlan == RTW_CHPLAN_REALTEK_DEFINE)
+ Index2G = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.Index2G;
+ else
+ Index2G = RTW_ChannelPlanMap[ChannelPlan].Index2G;
+
+ for (index = 0; index < CH_LIST_LEN(RTW_ChannelPlan2G[Index2G]); index++) {
+ if (rtw_regsty_is_excl_chs(regsty, CH_LIST_CH(RTW_ChannelPlan2G[Index2G], index)) == _TRUE)
+ continue;
+
+ if (chanset_size >= MAX_CHANNEL_NUM) {
+ RTW_WARN("chset size can't exceed MAX_CHANNEL_NUM(%u)\n", MAX_CHANNEL_NUM);
+ break;
+ }
+
+ channel_set[chanset_size].ChannelNum = CH_LIST_CH(RTW_ChannelPlan2G[Index2G], index);
+
+ if (ChannelPlan == RTW_CHPLAN_GLOBAL_DOAMIN
+ || Index2G == RTW_RD_2G_GLOBAL
+ ) {
+ /* Channel 1~11 is active, and 12~14 is passive */
+ if (channel_set[chanset_size].ChannelNum >= 1 && channel_set[chanset_size].ChannelNum <= 11)
+ channel_set[chanset_size].ScanType = SCAN_ACTIVE;
+ else if ((channel_set[chanset_size].ChannelNum >= 12 && channel_set[chanset_size].ChannelNum <= 14))
+ channel_set[chanset_size].ScanType = SCAN_PASSIVE;
+ } else if (ChannelPlan == RTW_CHPLAN_WORLD_WIDE_13
+ || ChannelPlan == RTW_CHPLAN_WORLD_WIDE_5G
+ || Index2G == RTW_RD_2G_WORLD
+ ) {
+ /* channel 12~13, passive scan */
+ if (channel_set[chanset_size].ChannelNum <= 11)
+ channel_set[chanset_size].ScanType = SCAN_ACTIVE;
+ else
+ channel_set[chanset_size].ScanType = SCAN_PASSIVE;
+ } else
+ channel_set[chanset_size].ScanType = SCAN_ACTIVE;
+
+ chanset_size++;
+ }
+ }
+
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+ if (b5GBand) {
+ if (ChannelPlan == RTW_CHPLAN_REALTEK_DEFINE)
+ Index5G = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.Index5G;
+ else
+ Index5G = RTW_ChannelPlanMap[ChannelPlan].Index5G;
+
+ for (index = 0; index < CH_LIST_LEN(RTW_ChannelPlan5G[Index5G]); index++) {
+ if (rtw_regsty_is_excl_chs(regsty, CH_LIST_CH(RTW_ChannelPlan5G[Index5G], index)) == _TRUE)
+ continue;
+ #ifndef CONFIG_DFS
+ if (rtw_is_dfs_ch(CH_LIST_CH(RTW_ChannelPlan5G[Index5G], index)))
+ continue;
+ #endif
+
+ if (chanset_size >= MAX_CHANNEL_NUM) {
+ RTW_WARN("chset size can't exceed MAX_CHANNEL_NUM(%u)\n", MAX_CHANNEL_NUM);
+ break;
+ }
+
+ channel_set[chanset_size].ChannelNum = CH_LIST_CH(RTW_ChannelPlan5G[Index5G], index);
+
+ if ((ChannelPlan == RTW_CHPLAN_WORLD_WIDE_5G) /* all channels passive */
+ || (rtw_is_5g_band1(channel_set[chanset_size].ChannelNum)
+ && rtw_rd_5g_band1_passive(Index5G)) /* band1 passive */
+ || (rtw_is_5g_band4(channel_set[chanset_size].ChannelNum)
+ && rtw_rd_5g_band4_passive(Index5G)) /* band4 passive */
+ || (rtw_is_dfs_ch(channel_set[chanset_size].ChannelNum)) /* DFS channel(band2, 3) passive */
+ )
+ channel_set[chanset_size].ScanType = SCAN_PASSIVE;
+ else
+ channel_set[chanset_size].ScanType = SCAN_ACTIVE;
+
+ chanset_size++;
+ }
+ }
+
+ #ifdef CONFIG_DFS_MASTER
+ for (i = 0; i < chanset_size; i++)
+ channel_set[i].non_ocp_end_time = rtw_get_current_time();
+ #endif
+#endif /* CONFIG_IEEE80211_BAND_5GHZ */
+
+ if (chanset_size)
+ RTW_INFO(FUNC_ADPT_FMT" ChannelPlan ID:0x%02x, ch num:%d\n"
+ , FUNC_ADPT_ARG(padapter), ChannelPlan, chanset_size);
+ else
+ RTW_WARN(FUNC_ADPT_FMT" ChannelPlan ID:0x%02x, final chset has no channel\n"
+ , FUNC_ADPT_ARG(padapter), ChannelPlan);
+
+ return chanset_size;
+}
+
+#ifdef CONFIG_TXPWR_LIMIT
+void rtw_txpwr_init_regd(struct rf_ctl_t *rfctl)
+{
+ u8 regd;
+ u8 regd_name;
+ struct regd_exc_ent *exc;
+ struct txpwr_lmt_ent *ent;
+ _irqL irqL;
+
+ _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+
+ rfctl->regd_name = NULL;
+
+ if (rfctl->txpwr_regd_num == 0) {
+ RTW_PRINT("there is no any txpwr_regd\n");
+ goto release_lock;
+ }
+
+ /* search from exception mapping */
+ exc = _rtw_regd_exc_search(rfctl
+ , rfctl->country_ent ? rfctl->country_ent->alpha2 : NULL
+ , rfctl->ChannelPlan);
+ if (exc) {
+ u8 has_country = (exc->country[0] == '\0' && exc->country[1] == '\0') ? 0 : 1;
+
+ if (strcmp(exc->regd_name, regd_str(TXPWR_LMT_NONE)) == 0)
+ rfctl->regd_name = regd_str(TXPWR_LMT_NONE);
+ else if (strcmp(exc->regd_name, regd_str(TXPWR_LMT_WW)) == 0)
+ rfctl->regd_name = regd_str(TXPWR_LMT_WW);
+ else {
+ ent = _rtw_txpwr_lmt_get_by_name(rfctl, exc->regd_name);
+ if (ent)
+ rfctl->regd_name = ent->regd_name;
+ }
+
+ RTW_PRINT("exception mapping country:%c%c domain:0x%02x to%s regd_name:%s\n"
+ , has_country ? exc->country[0] : '0'
+ , has_country ? exc->country[1] : '0'
+ , exc->domain
+ , rfctl->regd_name ? "" : " unknown"
+ , exc->regd_name
+ );
+ if (rfctl->regd_name)
+ goto release_lock;
+ }
+
+ /* follow default channel plan mapping */
+ if (rfctl->ChannelPlan == RTW_CHPLAN_REALTEK_DEFINE)
+ regd = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.regd;
+ else
+ regd = RTW_ChannelPlanMap[rfctl->ChannelPlan].regd;
+
+ if (regd == TXPWR_LMT_NONE)
+ rfctl->regd_name = regd_str(TXPWR_LMT_NONE);
+ else if (regd == TXPWR_LMT_WW)
+ rfctl->regd_name = regd_str(TXPWR_LMT_WW);
+ else {
+ ent = _rtw_txpwr_lmt_get_by_name(rfctl, regd_str(regd));
+ if (ent)
+ rfctl->regd_name = ent->regd_name;
+ }
+
+ RTW_PRINT("default mapping domain:0x%02x to%s regd_name:%s\n"
+ , rfctl->ChannelPlan
+ , rfctl->regd_name ? "" : " unknown"
+ , regd_str(regd)
+ );
+ if (rfctl->regd_name)
+ goto release_lock;
+
+ switch (regd) {
+ /*
+ * To support older chips without new predefined regd:
+ * - use FCC if IC or CHILE not found
+ * - use ETSI if KCC or ACMA not found
+ */
+ case TXPWR_LMT_IC:
+ case TXPWR_LMT_KCC:
+ case TXPWR_LMT_ACMA:
+ case TXPWR_LMT_CHILE:
+ if (regd == TXPWR_LMT_IC || regd == TXPWR_LMT_CHILE)
+ regd = TXPWR_LMT_FCC;
+ else if (regd == TXPWR_LMT_KCC || regd == TXPWR_LMT_ACMA)
+ regd = TXPWR_LMT_ETSI;
+ ent = _rtw_txpwr_lmt_get_by_name(rfctl, regd_str(regd));
+ if (ent)
+ rfctl->regd_name = ent->regd_name;
+ RTW_PRINT("alternate regd_name:%s %s\n"
+ , regd_str(regd)
+ , rfctl->regd_name ? "is used" : "not found"
+ );
+ if (rfctl->regd_name)
+ break;
+ default:
+ rfctl->regd_name = regd_str(TXPWR_LMT_WW);
+ RTW_PRINT("assign %s for default case\n", regd_str(TXPWR_LMT_WW));
+ break;
+ };
+
+release_lock:
+ _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+}
+#endif /* CONFIG_TXPWR_LIMIT */
+
void rtw_rfctl_init(_adapter *adapter)
{
struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
- _rtw_memset(rfctl, 0, sizeof(*rfctl));
+ rfctl->max_chan_nums = init_channel_set(adapter, rfctl->ChannelPlan, rfctl->channel_set);
+ init_channel_list(adapter, rfctl->channel_set, &rfctl->channel_list);
+
+ _rtw_mutex_init(&rfctl->offch_mutex);
+
+#ifdef CONFIG_TXPWR_LIMIT
+ _rtw_mutex_init(&rfctl->txpwr_lmt_mutex);
+ _rtw_init_listhead(&rfctl->reg_exc_list);
+ _rtw_init_listhead(&rfctl->txpwr_lmt_list);
+#endif
+
+ rfctl->ch_sel_same_band_prefer = 1;
#ifdef CONFIG_DFS_MASTER
rfctl->cac_start_time = rfctl->cac_end_time = RTW_CAC_STOPPED;
@@ -333,6 +808,23 @@ void rtw_rfctl_init(_adapter *adapter)
#endif
}
+void rtw_rfctl_deinit(_adapter *adapter)
+{
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+
+ _rtw_mutex_free(&rfctl->offch_mutex);
+
+#ifdef CONFIG_TXPWR_LIMIT
+ rtw_regd_exc_list_free(rfctl);
+ rtw_txpwr_lmt_list_free(rfctl);
+ _rtw_mutex_free(&rfctl->txpwr_lmt_mutex);
+#endif
+
+#ifdef CONFIG_DFS_MASTER
+ /* TODO: dfs_master_timer */
+#endif
+}
+
#ifdef CONFIG_DFS_MASTER
/*
* called in rtw_dfs_master_enable()
@@ -412,8 +904,8 @@ bool _rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8
}
if (rtw_chbw_to_freq_range(rfctl->radar_detect_ch
- , rfctl->radar_detect_bw, rfctl->radar_detect_offset
- , &r_hi, &r_lo) == _FALSE) {
+ , rfctl->radar_detect_bw, rfctl->radar_detect_offset
+ , &r_hi, &r_lo) == _FALSE) {
rtw_warn_on(1);
goto exit;
}
@@ -428,9 +920,9 @@ bool _rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8
bool rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl)
{
return _rtw_rfctl_overlap_radar_detect_ch(rfctl
- , rfctl_to_dvobj(rfctl)->oper_channel
- , rfctl_to_dvobj(rfctl)->oper_bwmode
- , rfctl_to_dvobj(rfctl)->oper_ch_offset);
+ , rfctl_to_dvobj(rfctl)->oper_channel
+ , rfctl_to_dvobj(rfctl)->oper_bwmode
+ , rfctl_to_dvobj(rfctl)->oper_ch_offset);
}
bool rtw_rfctl_is_tx_blocked_by_ch_waiting(struct rf_ctl_t *rfctl)
@@ -447,7 +939,7 @@ bool rtw_chset_is_ch_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset)
if (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE)
goto exit;
- for (i = 0; ch_set[i].ChannelNum != 0; i++) {
+ for (i = 0; i < MAX_CHANNEL_NUM && ch_set[i].ChannelNum != 0; i++) {
if (!rtw_ch2freq(ch_set[i].ChannelNum)) {
rtw_warn_on(1);
continue;
@@ -457,8 +949,8 @@ bool rtw_chset_is_ch_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset)
continue;
if (lo <= rtw_ch2freq(ch_set[i].ChannelNum)
- && rtw_ch2freq(ch_set[i].ChannelNum) <= hi
- ) {
+ && rtw_ch2freq(ch_set[i].ChannelNum) <= hi
+ ) {
ret = _TRUE;
break;
}
@@ -471,7 +963,7 @@ bool rtw_chset_is_ch_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset)
u32 rtw_chset_get_ch_non_ocp_ms(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset)
{
int ms = 0;
- u32 current_time;
+ systime current_time;
u32 hi = 0, lo = 0;
int i;
@@ -480,7 +972,7 @@ u32 rtw_chset_get_ch_non_ocp_ms(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset
current_time = rtw_get_current_time();
- for (i = 0; ch_set[i].ChannelNum != 0; i++) {
+ for (i = 0; i < MAX_CHANNEL_NUM && ch_set[i].ChannelNum != 0; i++) {
if (!rtw_ch2freq(ch_set[i].ChannelNum)) {
rtw_warn_on(1);
continue;
@@ -490,8 +982,8 @@ u32 rtw_chset_get_ch_non_ocp_ms(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset
continue;
if (lo <= rtw_ch2freq(ch_set[i].ChannelNum)
- && rtw_ch2freq(ch_set[i].ChannelNum) <= hi
- ) {
+ && rtw_ch2freq(ch_set[i].ChannelNum) <= hi
+ ) {
if (rtw_systime_to_ms(ch_set[i].non_ocp_end_time - current_time) > ms)
ms = rtw_systime_to_ms(ch_set[i].non_ocp_end_time - current_time);
}
@@ -517,15 +1009,15 @@ static void _rtw_chset_update_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8
if (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE)
goto exit;
- for (i = 0; ch_set[i].ChannelNum != 0; i++) {
+ for (i = 0; i < MAX_CHANNEL_NUM && ch_set[i].ChannelNum != 0; i++) {
if (!rtw_ch2freq(ch_set[i].ChannelNum)) {
rtw_warn_on(1);
continue;
}
if (lo <= rtw_ch2freq(ch_set[i].ChannelNum)
- && rtw_ch2freq(ch_set[i].ChannelNum) <= hi
- ) {
+ && rtw_ch2freq(ch_set[i].ChannelNum) <= hi
+ ) {
if (ms >= 0)
ch_set[i].non_ocp_end_time = rtw_get_current_time() + rtw_ms_to_systime(ms);
else
@@ -550,13 +1042,12 @@ inline void rtw_chset_update_non_ocp_ms(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u
u32 rtw_get_ch_waiting_ms(_adapter *adapter, u8 ch, u8 bw, u8 offset, u32 *r_non_ocp_ms, u32 *r_cac_ms)
{
struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
- struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
u32 non_ocp_ms;
u32 cac_ms;
u8 in_rd_range = 0; /* if in current radar detection range*/
- if (rtw_chset_is_ch_non_ocp(mlmeext->channel_set, ch, bw, offset))
- non_ocp_ms = rtw_chset_get_ch_non_ocp_ms(mlmeext->channel_set, ch, bw, offset);
+ if (rtw_chset_is_ch_non_ocp(rfctl->channel_set, ch, bw, offset))
+ non_ocp_ms = rtw_chset_get_ch_non_ocp_ms(rfctl->channel_set, ch, bw, offset);
else
non_ocp_ms = 0;
@@ -577,7 +1068,7 @@ u32 rtw_get_ch_waiting_ms(_adapter *adapter, u8 ch, u8 bw, u8 offset, u32 *r_non
in_rd_range = 1;
}
- if (!rtw_is_dfs_ch(ch, bw, offset))
+ if (!rtw_is_dfs_chbw(ch, bw, offset))
cac_ms = 0;
else if (in_rd_range && !non_ocp_ms) {
if (IS_CH_WAITING(rfctl))
@@ -604,12 +1095,12 @@ void rtw_reset_cac(_adapter *adapter, u8 ch, u8 bw, u8 offset)
u32 cac_ms;
rtw_get_ch_waiting_ms(adapter
- , ch
- , bw
- , offset
- , &non_ocp_ms
- , &cac_ms
- );
+ , ch
+ , bw
+ , offset
+ , &non_ocp_ms
+ , &cac_ms
+ );
rfctl->cac_start_time = rtw_get_current_time() + rtw_ms_to_systime(non_ocp_ms);
rfctl->cac_end_time = rfctl->cac_start_time + rtw_ms_to_systime(cac_ms);
@@ -623,14 +1114,46 @@ void rtw_reset_cac(_adapter *adapter, u8 ch, u8 bw, u8 offset)
rfctl->cac_end_time++;
}
+u32 rtw_force_stop_cac(_adapter *adapter, u32 timeout_ms)
+{
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+ systime start;
+ u32 pass_ms;
+
+ start = rtw_get_current_time();
+
+ rfctl->cac_force_stop = 1;
+
+ while (rtw_get_passing_time_ms(start) <= timeout_ms
+ && IS_UNDER_CAC(rfctl)
+ ) {
+ if (RTW_CANNOT_RUN(adapter))
+ break;
+ rtw_msleep_os(20);
+ }
+
+ if (IS_UNDER_CAC(rfctl)) {
+ if (!RTW_CANNOT_RUN(adapter))
+ RTW_INFO(FUNC_ADPT_FMT" waiting for cac stop timeout!\n", FUNC_ADPT_ARG(adapter));
+ }
+
+ rfctl->cac_force_stop = 0;
+
+ pass_ms = rtw_get_passing_time_ms(start);
+
+ return pass_ms;
+}
+#endif /* CONFIG_DFS_MASTER */
+
/* choose channel with shortest waiting (non ocp + cac) time */
-bool rtw_choose_shortest_waiting_ch(_adapter *adapter, u8 req_bw, u8 *dec_ch, u8 *dec_bw, u8 *dec_offset, u8 d_flags)
+bool rtw_choose_shortest_waiting_ch(_adapter *adapter, u8 sel_ch, u8 max_bw
+ , u8 *dec_ch, u8 *dec_bw, u8 *dec_offset
+ , u8 d_flags, u8 cur_ch, u8 same_band_prefer)
{
#ifndef DBG_CHOOSE_SHORTEST_WAITING_CH
#define DBG_CHOOSE_SHORTEST_WAITING_CH 0
#endif
- struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
struct registry_priv *regsty = adapter_to_regsty(adapter);
u8 ch, bw, offset;
@@ -644,16 +1167,18 @@ bool rtw_choose_shortest_waiting_ch(_adapter *adapter, u8 req_bw, u8 *dec_ch, u8
}
/* full search and narrow bw judegement first to avoid potetial judegement timing issue */
- for (bw = CHANNEL_WIDTH_20; bw <= req_bw; bw++) {
+ for (bw = CHANNEL_WIDTH_20; bw <= max_bw; bw++) {
if (!hal_is_bw_support(adapter, bw))
continue;
- for (i = 0; i < mlmeext->max_chan_nums; i++) {
- u32 non_ocp_ms;
- u32 cac_ms;
- u32 waiting_ms;
+ for (i = 0; i < rfctl->max_chan_nums; i++) {
+ u32 non_ocp_ms = 0;
+ u32 cac_ms = 0;
+ u32 waiting_ms = 0;
- ch = mlmeext->channel_set[i].ChannelNum;
+ ch = rfctl->channel_set[i].ChannelNum;
+ if (sel_ch > 0 && ch != sel_ch)
+ continue;
if ((d_flags & RTW_CHF_2G) && ch <= 14)
continue;
@@ -672,34 +1197,41 @@ bool rtw_choose_shortest_waiting_ch(_adapter *adapter, u8 req_bw, u8 *dec_ch, u8
if (!rtw_get_offset_by_chbw(ch, bw, &offset))
continue;
- if (!rtw_chset_is_chbw_valid(mlmeext->channel_set, ch, bw, offset))
+ if (!rtw_chset_is_chbw_valid(rfctl->channel_set, ch, bw, offset))
continue;
- if ((d_flags & RTW_CHF_NON_OCP) && rtw_chset_is_ch_non_ocp(mlmeext->channel_set, ch, bw, offset))
+ if ((d_flags & RTW_CHF_NON_OCP) && rtw_chset_is_ch_non_ocp(rfctl->channel_set, ch, bw, offset))
continue;
- if ((d_flags & RTW_CHF_DFS) && rtw_is_dfs_ch(ch, bw, offset))
+ if ((d_flags & RTW_CHF_DFS) && rtw_is_dfs_chbw(ch, bw, offset))
continue;
if ((d_flags & RTW_CHF_LONG_CAC) && rtw_is_long_cac_ch(ch, bw, offset, rtw_odm_get_dfs_domain(adapter)))
continue;
- if ((d_flags & RTW_CHF_NON_DFS) && !rtw_is_dfs_ch(ch, bw, offset))
+ if ((d_flags & RTW_CHF_NON_DFS) && !rtw_is_dfs_chbw(ch, bw, offset))
continue;
if ((d_flags & RTW_CHF_NON_LONG_CAC) && !rtw_is_long_cac_ch(ch, bw, offset, rtw_odm_get_dfs_domain(adapter)))
continue;
+ #ifdef CONFIG_DFS_MASTER
waiting_ms = rtw_get_ch_waiting_ms(adapter, ch, bw, offset, &non_ocp_ms, &cac_ms);
+ #endif
if (DBG_CHOOSE_SHORTEST_WAITING_CH)
RTW_INFO(FUNC_ADPT_FMT":%u,%u,%u %u(non_ocp:%u, cac:%u)\n"
, FUNC_ADPT_ARG(adapter), ch, bw, offset, waiting_ms, non_ocp_ms, cac_ms);
if (ch_c == 0
- || min_waiting_ms > waiting_ms
- || (min_waiting_ms == waiting_ms && bw > bw_c) /* wider bw first */
- ) {
+ /* first: smaller wating time */
+ || min_waiting_ms > waiting_ms
+ /* then: wider bw */
+ || (min_waiting_ms == waiting_ms && bw > bw_c)
+ /* then: same band if requested */
+ || (same_band_prefer && min_waiting_ms == waiting_ms && bw == bw_c
+ && !rtw_is_same_band(cur_ch, ch_c) && rtw_is_same_band(cur_ch, ch))
+ ) {
ch_c = ch;
bw_c = bw;
offset_c = offset;
@@ -709,8 +1241,9 @@ bool rtw_choose_shortest_waiting_ch(_adapter *adapter, u8 req_bw, u8 *dec_ch, u8
}
if (ch_c != 0) {
- RTW_INFO(FUNC_ADPT_FMT": d_flags:0x%02x %u,%u,%u waiting_ms:%u\n"
- , FUNC_ADPT_ARG(adapter), d_flags, ch_c, bw_c, offset_c, min_waiting_ms);
+ RTW_INFO(FUNC_ADPT_FMT": d_flags:0x%02x cur_ch:%u sb_prefer:%u %u,%u,%u waiting_ms:%u\n"
+ , FUNC_ADPT_ARG(adapter), d_flags, cur_ch, same_band_prefer
+ , ch_c, bw_c, offset_c, min_waiting_ms);
*dec_ch = ch_c;
*dec_bw = bw_c;
@@ -723,14 +1256,13 @@ bool rtw_choose_shortest_waiting_ch(_adapter *adapter, u8 req_bw, u8 *dec_ch, u8
return _FALSE;
}
-#endif /* CONFIG_DFS_MASTER */
void dump_country_chplan(void *sel, const struct country_chplan *ent)
{
- _RTW_PRINT_SEL(sel, "\"%c%c\", 0x%02X%s\n"
- , ent->alpha2[0], ent->alpha2[1], ent->chplan
- , COUNTRY_CHPLAN_EN_11AC(ent) ? " ac" : ""
- );
+ RTW_PRINT_SEL(sel, "\"%c%c\", 0x%02X%s\n"
+ , ent->alpha2[0], ent->alpha2[1], ent->chplan
+ , COUNTRY_CHPLAN_EN_11AC(ent) ? " ac" : ""
+ );
}
void dump_country_chplan_map(void *sel)
@@ -739,10 +1271,10 @@ void dump_country_chplan_map(void *sel)
u8 code[2];
#if RTW_DEF_MODULE_REGULATORY_CERT
- _RTW_PRINT_SEL(sel, "RTW_DEF_MODULE_REGULATORY_CERT:0x%x\n", RTW_DEF_MODULE_REGULATORY_CERT);
+ RTW_PRINT_SEL(sel, "RTW_DEF_MODULE_REGULATORY_CERT:0x%x\n", RTW_DEF_MODULE_REGULATORY_CERT);
#endif
#ifdef CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP
- _RTW_PRINT_SEL(sel, "CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP\n");
+ RTW_PRINT_SEL(sel, "CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP\n");
#endif
for (code[0] = 'A'; code[0] <= 'Z'; code[0]++) {
@@ -758,16 +1290,21 @@ void dump_country_chplan_map(void *sel)
void dump_chplan_id_list(void *sel)
{
+ u8 first = 1;
int i;
for (i = 0; i < RTW_CHPLAN_MAX; i++) {
if (!rtw_is_channel_plan_valid(i))
continue;
- _RTW_PRINT_SEL(sel, "0x%02X ", i);
+ if (first) {
+ RTW_PRINT_SEL(sel, "0x%02X ", i);
+ first = 0;
+ } else
+ _RTW_PRINT_SEL(sel, "0x%02X ", i);
}
- RTW_PRINT_SEL(sel, "0x7F\n");
+ _RTW_PRINT_SEL(sel, "0x7F\n");
}
void dump_chplan_test(void *sel)
@@ -776,25 +1313,27 @@ void dump_chplan_test(void *sel)
/* check invalid channel */
for (i = 0; i < RTW_RD_2G_MAX; i++) {
- for (j = 0; j < RTW_ChannelPlan2G[i].Len; j++) {
- if (rtw_ch2freq(RTW_ChannelPlan2G[i].Channel[j]) == 0)
- RTW_PRINT_SEL(sel, "invalid ch:%u at (%d,%d)\n", RTW_ChannelPlan2G[i].Channel[j], i, j);
+ for (j = 0; j < CH_LIST_LEN(RTW_ChannelPlan2G[i]); j++) {
+ if (rtw_ch2freq(CH_LIST_CH(RTW_ChannelPlan2G[i], j)) == 0)
+ RTW_PRINT_SEL(sel, "invalid ch:%u at (%d,%d)\n", CH_LIST_CH(RTW_ChannelPlan2G[i], j), i, j);
}
}
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
for (i = 0; i < RTW_RD_5G_MAX; i++) {
- for (j = 0; j < RTW_ChannelPlan5G[i].Len; j++) {
- if (rtw_ch2freq(RTW_ChannelPlan5G[i].Channel[j]) == 0)
- RTW_PRINT_SEL(sel, "invalid ch:%u at (%d,%d)\n", RTW_ChannelPlan5G[i].Channel[j], i, j);
+ for (j = 0; j < CH_LIST_LEN(RTW_ChannelPlan5G[i]); j++) {
+ if (rtw_ch2freq(CH_LIST_CH(RTW_ChannelPlan5G[i], j)) == 0)
+ RTW_PRINT_SEL(sel, "invalid ch:%u at (%d,%d)\n", CH_LIST_CH(RTW_ChannelPlan5G[i], j), i, j);
}
}
+#endif
}
void dump_chset(void *sel, RT_CHANNEL_INFO *ch_set)
{
u8 i;
- for (i = 0; ch_set[i].ChannelNum != 0; i++) {
+ for (i = 0; i < MAX_CHANNEL_NUM && ch_set[i].ChannelNum != 0; i++) {
RTW_PRINT_SEL(sel, "ch:%3u, freq:%u, scan_type:%d"
, ch_set[i].ChannelNum, rtw_ch2freq(ch_set[i].ChannelNum), ch_set[i].ScanType);
@@ -803,7 +1342,7 @@ void dump_chset(void *sel, RT_CHANNEL_INFO *ch_set)
#endif
#ifdef CONFIG_DFS_MASTER
- if (rtw_is_dfs_ch(ch_set[i].ChannelNum, CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE)) {
+ if (rtw_is_dfs_ch(ch_set[i].ChannelNum)) {
if (CH_IS_NON_OCP(&ch_set[i]))
_RTW_PRINT_SEL(sel, ", non_ocp:%d"
, rtw_systime_to_ms(ch_set[i].non_ocp_end_time - rtw_get_current_time()));
@@ -820,35 +1359,39 @@ void dump_chset(void *sel, RT_CHANNEL_INFO *ch_set)
void dump_cur_chset(void *sel, _adapter *adapter)
{
- struct mlme_priv *mlme = &adapter->mlmepriv;
- struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
struct registry_priv *regsty = adapter_to_regsty(adapter);
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
int i;
- if (mlme->country_ent)
- dump_country_chplan(sel, mlme->country_ent);
+ if (rfctl->country_ent)
+ dump_country_chplan(sel, rfctl->country_ent);
else
- RTW_PRINT_SEL(sel, "chplan:0x%02X\n", mlme->ChannelPlan);
+ RTW_PRINT_SEL(sel, "chplan:0x%02X\n", rfctl->ChannelPlan);
+
+#ifdef CONFIG_TXPWR_LIMIT
+ RTW_PRINT_SEL(sel, "PLS regd:%s\n", rfctl->regd_name);
+#endif
- RTW_PRINT_SEL(sel, "2G_PLS:%u, 5G_PLS:%u\n"
- , hal_data->Regulation2_4G, hal_data->Regulation5G);
+#ifdef CONFIG_DFS_MASTER
+ RTW_PRINT_SEL(sel, "dfs_domain:%u\n", rtw_odm_get_dfs_domain(adapter));
+#endif
for (i = 0; i < MAX_CHANNEL_NUM; i++)
if (regsty->excl_chs[i] != 0)
break;
if (i < MAX_CHANNEL_NUM) {
- _RTW_PRINT_SEL(sel, "excl_chs:");
+ RTW_PRINT_SEL(sel, "excl_chs:");
for (i = 0; i < MAX_CHANNEL_NUM; i++) {
if (regsty->excl_chs[i] == 0)
break;
_RTW_PRINT_SEL(sel, "%u ", regsty->excl_chs[i]);
}
- RTW_PRINT_SEL(sel, "\n");
+ _RTW_PRINT_SEL(sel, "\n");
}
- dump_chset(sel, mlmeext->channel_set);
+ dump_chset(sel, rfctl->channel_set);
}
/*
@@ -858,17 +1401,19 @@ void dump_cur_chset(void *sel, _adapter *adapter)
*
* return the index of channel_num in channel_set, -1 if not found
*/
-int rtw_ch_set_search_ch(RT_CHANNEL_INFO *ch_set, const u32 ch)
+int rtw_chset_search_ch(RT_CHANNEL_INFO *ch_set, const u32 ch)
{
int i;
- for (i = 0; ch_set[i].ChannelNum != 0; i++) {
+
+ if (ch == 0)
+ return -1;
+
+ for (i = 0; i < MAX_CHANNEL_NUM && ch_set[i].ChannelNum != 0; i++) {
if (ch == ch_set[i].ChannelNum)
- break;
+ return i;
}
- if (i >= ch_set[i].ChannelNum)
- return -1;
- return i;
+ return -1;
}
/*
@@ -896,7 +1441,7 @@ u8 rtw_chset_is_chbw_valid(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset)
for (i = 0; i < op_ch_num; i++) {
if (0)
RTW_INFO("%u,%u,%u - cch:%u, bw:%u, op_ch:%u\n", ch, bw, offset, cch, bw, *(op_chs + i));
- if (rtw_ch_set_search_ch(ch_set, *(op_chs + i)) == -1)
+ if (rtw_chset_search_ch(ch_set, *(op_chs + i)) == -1)
break;
}
@@ -907,21 +1452,65 @@ u8 rtw_chset_is_chbw_valid(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset)
return valid;
}
-/*
- * Check the @param ch is fit with setband setting of @param adapter
- * @adapter: the given adapter
- * @ch: the given channel number
- *
- * return _TRUE when check valid, _FALSE not valid
+/**
+ * rtw_chset_sync_chbw - obey g_ch, adjust g_bw, g_offset, bw, offset to fit in channel plan
+ * @ch_set: channel plan to check
+ * @req_ch: pointer of the request ch, may be modified further
+ * @req_bw: pointer of the request bw, may be modified further
+ * @req_offset: pointer of the request offset, may be modified further
+ * @g_ch: pointer of the ongoing group ch
+ * @g_bw: pointer of the ongoing group bw, may be modified further
+ * @g_offset: pointer of the ongoing group offset, may be modified further
*/
-bool rtw_mlme_band_check(_adapter *adapter, const u32 ch)
+void rtw_chset_sync_chbw(RT_CHANNEL_INFO *ch_set, u8 *req_ch, u8 *req_bw, u8 *req_offset
+ , u8 *g_ch, u8 *g_bw, u8 *g_offset)
{
- if (adapter->setband == WIFI_FREQUENCY_BAND_AUTO /* 2.4G and 5G */
- || (adapter->setband == WIFI_FREQUENCY_BAND_2GHZ && ch < 35) /* 2.4G only */
- || (adapter->setband == WIFI_FREQUENCY_BAND_5GHZ && ch > 35) /* 5G only */
- )
- return _TRUE;
- return _FALSE;
+ u8 r_ch, r_bw, r_offset;
+ u8 u_ch, u_bw, u_offset;
+ u8 cur_bw = *req_bw;
+
+ while (1) {
+ r_ch = *req_ch;
+ r_bw = cur_bw;
+ r_offset = *req_offset;
+ u_ch = *g_ch;
+ u_bw = *g_bw;
+ u_offset = *g_offset;
+
+ rtw_sync_chbw(&r_ch, &r_bw, &r_offset, &u_ch, &u_bw, &u_offset);
+
+ if (rtw_chset_is_chbw_valid(ch_set, r_ch, r_bw, r_offset))
+ break;
+ if (cur_bw == CHANNEL_WIDTH_20) {
+ rtw_warn_on(1);
+ break;
+ }
+ cur_bw--;
+ };
+
+ *req_ch = r_ch;
+ *req_bw = r_bw;
+ *req_offset = r_offset;
+ *g_ch = u_ch;
+ *g_bw = u_bw;
+ *g_offset = u_offset;
+}
+
+/*
+ * Check the @param ch is fit with setband setting of @param adapter
+ * @adapter: the given adapter
+ * @ch: the given channel number
+ *
+ * return _TRUE when check valid, _FALSE not valid
+ */
+bool rtw_mlme_band_check(_adapter *adapter, const u32 ch)
+{
+ if (adapter->setband == WIFI_FREQUENCY_BAND_AUTO /* 2.4G and 5G */
+ || (adapter->setband == WIFI_FREQUENCY_BAND_2GHZ && ch < 35) /* 2.4G only */
+ || (adapter->setband == WIFI_FREQUENCY_BAND_5GHZ && ch > 35) /* 5G only */
+ )
+ return _TRUE;
+ return _FALSE;
}
inline void RTW_SET_SCAN_BAND_SKIP(_adapter *padapter, int skip_band)
{
@@ -965,9 +1554,10 @@ Following are the initialization functions for WiFi MLME
int init_hw_mlme_ext(_adapter *padapter)
{
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+ u8 rx_bar_enble = _TRUE;
/* set_opmode_cmd(padapter, infra_client_with_mlme); */ /* removed */
-
+ rtw_hal_set_hwreg(padapter, HW_VAR_ENABLE_RX_BAR, &rx_bar_enble);
set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
return _SUCCESS;
@@ -996,9 +1586,7 @@ static void init_mlme_ext_priv_value(_adapter *padapter)
pmlmeext->mgnt_seq = 0;/* reset to zero when disconnect at client mode */
#ifdef CONFIG_IEEE80211W
pmlmeext->sa_query_seq = 0;
- pmlmeext->mgnt_80211w_IPN = 0;
- pmlmeext->mgnt_80211w_IPN_rx = 0;
-#endif /* CONFIG_IEEE80211W */
+#endif
pmlmeext->cur_channel = padapter->registrypriv.channel;
pmlmeext->cur_bwmode = CHANNEL_WIDTH_20;
pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
@@ -1055,201 +1643,20 @@ static void init_mlme_ext_priv_value(_adapter *padapter)
pmlmeext->action_public_dialog_token = 0xff;
}
-static int has_channel(RT_CHANNEL_INFO *channel_set,
- u8 chanset_size,
- u8 chan)
-{
- int i;
-
- for (i = 0; i < chanset_size; i++) {
- if (channel_set[i].ChannelNum == chan)
- return 1;
- }
-
- return 0;
-}
-
-static void init_channel_list(_adapter *padapter, RT_CHANNEL_INFO *channel_set,
- u8 chanset_size,
- struct p2p_channels *channel_list)
+void init_mlme_ext_timer(_adapter *padapter)
{
- struct registry_priv *regsty = adapter_to_regsty(padapter);
+ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
- struct p2p_oper_class_map op_class[] = {
- { IEEE80211G, 81, 1, 13, 1, BW20 },
- { IEEE80211G, 82, 14, 14, 1, BW20 },
-#if 0 /* Do not enable HT40 on 2 GHz */
- { IEEE80211G, 83, 1, 9, 1, BW40PLUS },
- { IEEE80211G, 84, 5, 13, 1, BW40MINUS },
+ rtw_init_timer(&pmlmeext->survey_timer, padapter, survey_timer_hdl, padapter);
+ rtw_init_timer(&pmlmeext->link_timer, padapter, link_timer_hdl, padapter);
+#ifdef CONFIG_RTW_80211R
+ rtw_init_timer(&pmlmeext->ft_link_timer, padapter, rtw_ft_link_timer_hdl, padapter);
+ rtw_init_timer(&pmlmeext->ft_roam_timer, padapter, rtw_ft_roam_timer_hdl, padapter);
#endif
- { IEEE80211A, 115, 36, 48, 4, BW20 },
- { IEEE80211A, 116, 36, 44, 8, BW40PLUS },
- { IEEE80211A, 117, 40, 48, 8, BW40MINUS },
- { IEEE80211A, 124, 149, 161, 4, BW20 },
- { IEEE80211A, 125, 149, 169, 4, BW20 },
- { IEEE80211A, 126, 149, 157, 8, BW40PLUS },
- { IEEE80211A, 127, 153, 161, 8, BW40MINUS },
- { -1, 0, 0, 0, 0, BW20 }
- };
-
- int cla, op;
-
- cla = 0;
-
- for (op = 0; op_class[op].op_class; op++) {
- u8 ch;
- struct p2p_oper_class_map *o = &op_class[op];
- struct p2p_reg_class *reg = NULL;
-
- for (ch = o->min_chan; ch <= o->max_chan; ch += o->inc) {
- if (!has_channel(channel_set, chanset_size, ch))
- continue;
-
- if ((0 == padapter->registrypriv.ht_enable) && (8 == o->inc))
- continue;
-
- if ((REGSTY_IS_BW_5G_SUPPORT(regsty, CHANNEL_WIDTH_40)) &&
- ((BW40MINUS == o->bw) || (BW40PLUS == o->bw)))
- continue;
-
- if (reg == NULL) {
- reg = &channel_list->reg_class[cla];
- cla++;
- reg->reg_class = o->op_class;
- reg->channels = 0;
- }
- reg->channel[reg->channels] = ch;
- reg->channels++;
- }
- }
- channel_list->reg_classes = cla;
-
-}
-
-bool rtw_regsty_is_excl_chs(struct registry_priv *regsty, u8 ch)
-{
- int i;
-
- for (i = 0; i < MAX_CHANNEL_NUM; i++) {
- if (regsty->excl_chs[i] == 0)
- break;
- if (regsty->excl_chs[i] == ch)
- return _TRUE;
- }
- return _FALSE;
-}
-
-static u8 init_channel_set(_adapter *padapter, u8 ChannelPlan, RT_CHANNEL_INFO *channel_set)
-{
- struct registry_priv *regsty = adapter_to_regsty(padapter);
- u8 index, chanset_size = 0;
- u8 b5GBand = _FALSE, b2_4GBand = _FALSE;
- u8 Index2G = 0, Index5G = 0;
- HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
- int i;
-
- if (!rtw_is_channel_plan_valid(ChannelPlan)) {
- RTW_ERR("ChannelPlan ID 0x%02X error !!!!!\n", ChannelPlan);
- return chanset_size;
- }
-
- _rtw_memset(channel_set, 0, sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM);
-
- if (IsSupported24G(padapter->registrypriv.wireless_mode))
- b2_4GBand = _TRUE;
-
- if (IsSupported5G(padapter->registrypriv.wireless_mode))
- b5GBand = _TRUE;
-
- if (b2_4GBand) {
- if (RTW_CHPLAN_REALTEK_DEFINE == ChannelPlan)
- Index2G = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.Index2G;
- else
- Index2G = RTW_ChannelPlanMap[ChannelPlan].Index2G;
-
- for (index = 0; index < RTW_ChannelPlan2G[Index2G].Len; index++) {
- if (rtw_regsty_is_excl_chs(regsty, RTW_ChannelPlan2G[Index2G].Channel[index]) == _TRUE)
- continue;
-
- channel_set[chanset_size].ChannelNum = RTW_ChannelPlan2G[Index2G].Channel[index];
-
- if (RTW_CHPLAN_GLOBAL_DOAMIN == ChannelPlan
- || RTW_CHPLAN_GLOBAL_NULL == ChannelPlan
- ) {
- /* Channel 1~11 is active, and 12~14 is passive */
- if (channel_set[chanset_size].ChannelNum >= 1 && channel_set[chanset_size].ChannelNum <= 11)
- channel_set[chanset_size].ScanType = SCAN_ACTIVE;
- else if ((channel_set[chanset_size].ChannelNum >= 12 && channel_set[chanset_size].ChannelNum <= 14))
- channel_set[chanset_size].ScanType = SCAN_PASSIVE;
- } else if (RTW_CHPLAN_WORLD_WIDE_13 == ChannelPlan
- || RTW_CHPLAN_WORLD_WIDE_5G == ChannelPlan
- || RTW_RD_2G_WORLD == Index2G
- ) {
- /* channel 12~13, passive scan */
- if (channel_set[chanset_size].ChannelNum <= 11)
- channel_set[chanset_size].ScanType = SCAN_ACTIVE;
- else
- channel_set[chanset_size].ScanType = SCAN_PASSIVE;
- } else
- channel_set[chanset_size].ScanType = SCAN_ACTIVE;
-
- chanset_size++;
- }
- }
-
- if (b5GBand) {
- if (RTW_CHPLAN_REALTEK_DEFINE == ChannelPlan)
- Index5G = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.Index5G;
- else
- Index5G = RTW_ChannelPlanMap[ChannelPlan].Index5G;
-
- for (index = 0; index < RTW_ChannelPlan5G[Index5G].Len; index++) {
- if (rtw_regsty_is_excl_chs(regsty, RTW_ChannelPlan5G[Index5G].Channel[index]) == _TRUE)
- continue;
-#ifdef CONFIG_DFS
- channel_set[chanset_size].ChannelNum = RTW_ChannelPlan5G[Index5G].Channel[index];
- if (channel_set[chanset_size].ChannelNum <= 48
- || channel_set[chanset_size].ChannelNum >= 149) {
- if (RTW_CHPLAN_WORLD_WIDE_5G == ChannelPlan) /* passive scan for all 5G channels */
- channel_set[chanset_size].ScanType = SCAN_PASSIVE;
- else
- channel_set[chanset_size].ScanType = SCAN_ACTIVE;
- } else
- channel_set[chanset_size].ScanType = SCAN_PASSIVE;
- chanset_size++;
-#else /* CONFIG_DFS */
- if (RTW_ChannelPlan5G[Index5G].Channel[index] <= 48
- || RTW_ChannelPlan5G[Index5G].Channel[index] >= 149
- ) {
- channel_set[chanset_size].ChannelNum = RTW_ChannelPlan5G[Index5G].Channel[index];
- if (RTW_CHPLAN_WORLD_WIDE_5G == ChannelPlan) /* passive scan for all 5G channels */
- channel_set[chanset_size].ScanType = SCAN_PASSIVE;
- else
- channel_set[chanset_size].ScanType = SCAN_ACTIVE;
- RTW_INFO("%s(): channel_set[%d].ChannelNum = %d\n", __FUNCTION__, chanset_size, channel_set[chanset_size].ChannelNum);
- chanset_size++;
- }
-#endif /* CONFIG_DFS */
- }
- }
-
- if (RTW_CHPLAN_REALTEK_DEFINE == ChannelPlan) {
- hal_data->Regulation2_4G = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.regd;
- hal_data->Regulation5G = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.regd;
- } else {
- hal_data->Regulation2_4G = RTW_ChannelPlanMap[ChannelPlan].regd;
- hal_data->Regulation5G = RTW_ChannelPlanMap[ChannelPlan].regd;
- }
-#ifdef CONFIG_DFS_MASTER
- for (i = 0; i < chanset_size; i++)
- channel_set[i].non_ocp_end_time = rtw_get_current_time();
+#ifdef CONFIG_RTW_REPEATER_SON
+ rtw_init_timer(&pmlmeext->rson_scan_timer, padapter, rson_timer_hdl, padapter);
#endif
-
- RTW_INFO(FUNC_ADPT_FMT" ChannelPlan ID:0x%02x, ch num:%d\n"
- , FUNC_ADPT_ARG(padapter), ChannelPlan, chanset_size);
-
- return chanset_size;
}
int init_mlme_ext_priv(_adapter *padapter)
@@ -1276,8 +1683,6 @@ int init_mlme_ext_priv(_adapter *padapter)
init_mlme_ap_info(padapter);
#endif
- pmlmeext->max_chan_nums = init_channel_set(padapter, pmlmepriv->ChannelPlan, pmlmeext->channel_set);
- init_channel_list(padapter, pmlmeext->channel_set, pmlmeext->max_chan_nums, &pmlmeext->channel_list);
pmlmeext->last_scan_time = 0;
pmlmeext->mlmeext_init = _TRUE;
@@ -1306,7 +1711,6 @@ void free_mlme_ext_priv(struct mlme_ext_priv *pmlmeext)
if (rtw_is_drv_stopped(padapter)) {
_cancel_timer_ex(&pmlmeext->survey_timer);
_cancel_timer_ex(&pmlmeext->link_timer);
- /* _cancel_timer_ex(&pmlmeext->ADDBA_timer); */
}
}
@@ -1352,20 +1756,16 @@ void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame)
#endif /* CONFIG_AP_MODE */
u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
u8 *pframe = precv_frame->u.hdr.rx_data;
- struct sta_info *psta = rtw_get_stainfo(&padapter->stapriv, GetAddr2Ptr(pframe));
- struct dvobj_priv *psdpriv = padapter->dvobj;
- struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
+ struct sta_info *psta = rtw_get_stainfo(&padapter->stapriv, get_addr2_ptr(pframe));
+ struct recv_priv *precvpriv = &padapter->recvpriv;
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_,
- ("+mgt_dispatcher: type(0x%x) subtype(0x%x)\n",
- GetFrameType(pframe), GetFrameSubType(pframe)));
#if 0
{
u8 *pbuf;
pbuf = GetAddr1Ptr(pframe);
RTW_INFO("A1-%x:%x:%x:%x:%x:%x\n", *pbuf, *(pbuf + 1), *(pbuf + 2), *(pbuf + 3), *(pbuf + 4), *(pbuf + 5));
- pbuf = GetAddr2Ptr(pframe);
+ pbuf = get_addr2_ptr(pframe);
RTW_INFO("A2-%x:%x:%x:%x:%x:%x\n", *pbuf, *(pbuf + 1), *(pbuf + 2), *(pbuf + 3), *(pbuf + 4), *(pbuf + 5));
pbuf = GetAddr3Ptr(pframe);
RTW_INFO("A3-%x:%x:%x:%x:%x:%x\n", *pbuf, *(pbuf + 1), *(pbuf + 2), *(pbuf + 3), *(pbuf + 4), *(pbuf + 5));
@@ -1373,7 +1773,6 @@ void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame)
#endif
if (GetFrameType(pframe) != WIFI_MGT_TYPE) {
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("mgt_dispatcher: type(0x%x) error!\n", GetFrameType(pframe)));
return;
}
@@ -1384,20 +1783,19 @@ void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame)
ptable = mlme_sta_tbl;
- index = GetFrameSubType(pframe) >> 4;
+ index = get_frame_sub_type(pframe) >> 4;
#ifdef CONFIG_TDLS
if ((index << 4) == WIFI_ACTION) {
/* category==public (4), action==TDLS_DISCOVERY_RESPONSE */
if (*(pframe + 24) == RTW_WLAN_CATEGORY_PUBLIC && *(pframe + 25) == TDLS_DISCOVERY_RESPONSE) {
- RTW_INFO("[TDLS] Recv %s from "MAC_FMT"\n", rtw_tdls_action_txt(TDLS_DISCOVERY_RESPONSE), MAC_ARG(GetAddr2Ptr(pframe)));
+ RTW_INFO("[TDLS] Recv %s from "MAC_FMT"\n", rtw_tdls_action_txt(TDLS_DISCOVERY_RESPONSE), MAC_ARG(get_addr2_ptr(pframe)));
On_TDLS_Dis_Rsp(padapter, precv_frame);
}
}
#endif /* CONFIG_TDLS */
if (index >= (sizeof(mlme_sta_tbl) / sizeof(struct mlme_handler))) {
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("Currently we do not support reserved sub-fr-type=%d\n", index));
return;
}
ptable += index;
@@ -1407,7 +1805,7 @@ void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame)
if (GetRetry(pframe)) {
if (precv_frame->u.hdr.attrib.seq_num == psta->RxMgmtFrameSeqNum) {
/* drop the duplicate management frame */
- pdbgpriv->dbg_rx_dup_mgt_frame_drop_count++;
+ precvpriv->dbg_rx_dup_mgt_frame_drop_count++;
RTW_INFO("Drop duplicate management frame with seq_num = %d.\n", precv_frame->u.hdr.attrib.seq_num);
return;
}
@@ -1417,48 +1815,46 @@ void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame)
#else
if (GetRetry(pframe)) {
- /* RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("drop due to decache!\n")); */
/* return; */
}
#endif
#ifdef CONFIG_AP_MODE
- switch (GetFrameSubType(pframe)) {
+ switch (get_frame_sub_type(pframe)) {
case WIFI_AUTH:
- if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
+ if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter))
ptable->func = &OnAuth;
else
ptable->func = &OnAuthClient;
- /* pass through */
+ // fallthrough
+
case WIFI_ASSOCREQ:
case WIFI_REASSOCREQ:
_mgt_dispatcher(padapter, ptable, precv_frame);
-#ifdef CONFIG_HOSTAPD_MLME
- if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
+ #ifdef CONFIG_HOSTAPD_MLME
+ if (MLME_IS_AP(padapter))
rtw_hostapd_mlme_rx(padapter, precv_frame);
-#endif
+ #endif
break;
case WIFI_PROBEREQ:
- if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) {
-#ifdef CONFIG_HOSTAPD_MLME
+ _mgt_dispatcher(padapter, ptable, precv_frame);
+ #ifdef CONFIG_HOSTAPD_MLME
+ if (MLME_IS_AP(padapter))
rtw_hostapd_mlme_rx(padapter, precv_frame);
-#else
- _mgt_dispatcher(padapter, ptable, precv_frame);
-#endif
- } else
- _mgt_dispatcher(padapter, ptable, precv_frame);
+ #endif
break;
case WIFI_BEACON:
_mgt_dispatcher(padapter, ptable, precv_frame);
break;
case WIFI_ACTION:
- /* if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) */
_mgt_dispatcher(padapter, ptable, precv_frame);
break;
default:
_mgt_dispatcher(padapter, ptable, precv_frame);
- if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
+ #ifdef CONFIG_HOSTAPD_MLME
+ if (MLME_IS_AP(padapter))
rtw_hostapd_mlme_rx(padapter, precv_frame);
+ #endif
break;
}
#else
@@ -1476,21 +1872,23 @@ u32 p2p_listen_state_process(_adapter *padapter, unsigned char *da)
#ifdef CONFIG_IOCTL_CFG80211
if (padapter->wdinfo.driver_interface == DRIVER_CFG80211) {
- if (padapter->cfg80211_wdinfo.is_ro_ch == _FALSE
- || rtw_get_oper_ch(padapter) != padapter->wdinfo.listen_channel
- || adapter_wdev_data(padapter)->p2p_enabled == _FALSE
- || padapter->mlmepriv.wps_probe_resp_ie == NULL
- || padapter->mlmepriv.p2p_probe_resp_ie == NULL
- ) {
+ if (rtw_cfg80211_get_is_roch(padapter) == _FALSE
+ || rtw_get_oper_ch(padapter) != padapter->wdinfo.listen_channel
+ || adapter_wdev_data(padapter)->p2p_enabled == _FALSE
+ || padapter->mlmepriv.wps_probe_resp_ie == NULL
+ || padapter->mlmepriv.p2p_probe_resp_ie == NULL
+ ) {
#ifdef CONFIG_DEBUG_CFG80211
- RTW_INFO("DON'T issue_probersp_p2p: p2p_enabled:%d, wps_probe_resp_ie:%p, p2p_probe_resp_ie:%p, ",
- adapter_wdev_data(padapter)->p2p_enabled,
- padapter->mlmepriv.wps_probe_resp_ie,
- padapter->mlmepriv.p2p_probe_resp_ie);
- RTW_INFO("is_ro_ch:%d, op_ch:%d, p2p_listen_channel:%d\n",
- padapter->cfg80211_wdinfo.is_ro_ch,
- rtw_get_oper_ch(padapter),
- padapter->wdinfo.listen_channel);
+ RTW_INFO(ADPT_FMT" DON'T issue_probersp_p2p: p2p_enabled:%d, wps_probe_resp_ie:%p, p2p_probe_resp_ie:%p\n"
+ , ADPT_ARG(padapter)
+ , adapter_wdev_data(padapter)->p2p_enabled
+ , padapter->mlmepriv.wps_probe_resp_ie
+ , padapter->mlmepriv.p2p_probe_resp_ie);
+ RTW_INFO(ADPT_FMT" DON'T issue_probersp_p2p: is_ro_ch:%d, op_ch:%d, p2p_listen_channel:%d\n"
+ , ADPT_ARG(padapter)
+ , rtw_cfg80211_get_is_roch(padapter)
+ , rtw_get_oper_ch(padapter)
+ , padapter->wdinfo.listen_channel);
#endif
response = _FALSE;
}
@@ -1546,8 +1944,8 @@ unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame)
if ((pwdinfo->driver_interface == DRIVER_CFG80211)
&& !rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)
&& (GET_CFG80211_REPORT_MGMT(adapter_wdev_data(padapter), IEEE80211_STYPE_PROBE_REQ) == _TRUE)
- ) {
- rtw_cfg80211_rx_probe_request(padapter, pframe, len);
+ ) {
+ rtw_cfg80211_rx_probe_request(padapter, precv_frame);
return _SUCCESS;
}
#endif /* CONFIG_IOCTL_CFG80211 */
@@ -1598,7 +1996,7 @@ unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame)
return _SUCCESS;
if (check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE &&
- check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE | WIFI_AP_STATE) == _FALSE)
+ check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE | WIFI_AP_STATE | WIFI_MESH_STATE) == _FALSE)
return _SUCCESS;
@@ -1672,32 +2070,25 @@ unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame)
/* generate pairing ID */
mac_addr = adapter_mac_addr(padapter);
- peer_addr = psta->hwaddr;
+ peer_addr = psta->cmn.mac_addr;
psta->pid = (u16)(((mac_addr[4] << 8) + mac_addr[5]) + ((peer_addr[4] << 8) + peer_addr[5]));
/* update peer stainfo */
psta->isrc = _TRUE;
- /* get a unique AID */
- if (psta->aid > 0)
- RTW_INFO("old AID %d\n", psta->aid);
+ /* AID assignment */
+ if (psta->cmn.aid > 0)
+ RTW_INFO(FUNC_ADPT_FMT" old AID=%d\n", FUNC_ADPT_ARG(padapter), psta->cmn.aid);
else {
- for (psta->aid = 1; psta->aid <= NUM_STA; psta->aid++)
- if (pstapriv->sta_aid[psta->aid - 1] == NULL)
- break;
-
- if (psta->aid > pstapriv->max_num_sta) {
- psta->aid = 0;
- RTW_INFO("no room for more AIDs\n");
+ if (!rtw_aid_alloc(padapter, psta)) {
+ RTW_INFO(FUNC_ADPT_FMT" no room for more AIDs\n", FUNC_ADPT_ARG(padapter));
return _SUCCESS;
- } else {
- pstapriv->sta_aid[psta->aid - 1] = psta;
- RTW_INFO("allocate new AID = (%d)\n", psta->aid);
}
+ RTW_INFO(FUNC_ADPT_FMT" allocate new AID=%d\n", FUNC_ADPT_ARG(padapter), psta->cmn.aid);
}
psta->qos_option = 1;
- psta->bw_mode = CHANNEL_WIDTH_20;
+ psta->cmn.bw_mode = CHANNEL_WIDTH_20;
psta->ieee8021x_blocked = _FALSE;
#ifdef CONFIG_80211N_HT
psta->htpriv.ht_option = _TRUE;
@@ -1717,7 +2108,7 @@ unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame)
psta->state |= _FW_LINKED;
_exit_critical_bh(&psta->lock, &irqL);
- report_add_sta_event(padapter, psta->hwaddr);
+ report_add_sta_event(padapter, psta->cmn.mac_addr);
}
@@ -1752,9 +2143,20 @@ unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame)
goto _issue_probersp;
if ((ielen != 0 && _FALSE == _rtw_memcmp((void *)(p + 2), (void *)cur->Ssid.Ssid, cur->Ssid.SsidLength))
- || (ielen == 0 && pmlmeinfo->hidden_ssid_mode)
- )
- return _SUCCESS;
+ || (ielen == 0 && pmlmeinfo->hidden_ssid_mode))
+ goto exit;
+
+ #ifdef CONFIG_RTW_MESH
+ if (MLME_IS_MESH(padapter)) {
+ p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, WLAN_EID_MESH_ID, (int *)&ielen,
+ len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_);
+
+ if (!p)
+ goto exit;
+ if (ielen != 0 && _rtw_memcmp((void *)(p + 2), (void *)cur->mesh_id.Ssid, cur->mesh_id.SsidLength) == _FALSE)
+ goto exit;
+ }
+ #endif
_issue_probersp:
if (((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE &&
@@ -1765,6 +2167,7 @@ unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame)
}
+exit:
return _SUCCESS;
}
@@ -1784,7 +2187,7 @@ unsigned int OnProbeRsp(_adapter *padapter, union recv_frame *precv_frame)
#ifdef CONFIG_P2P
if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ)) {
if (_TRUE == pwdinfo->tx_prov_disc_info.benable) {
- if (_rtw_memcmp(pwdinfo->tx_prov_disc_info.peerIFAddr, GetAddr2Ptr(pframe), ETH_ALEN)) {
+ if (_rtw_memcmp(pwdinfo->tx_prov_disc_info.peerIFAddr, get_addr2_ptr(pframe), ETH_ALEN)) {
if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) {
pwdinfo->tx_prov_disc_info.benable = _FALSE;
issue_p2p_provision_request(padapter,
@@ -1804,7 +2207,7 @@ unsigned int OnProbeRsp(_adapter *padapter, union recv_frame *precv_frame)
} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING)) {
if (_TRUE == pwdinfo->nego_req_info.benable) {
RTW_INFO("[%s] P2P State is GONEGO ING!\n", __FUNCTION__);
- if (_rtw_memcmp(pwdinfo->nego_req_info.peerDevAddr, GetAddr2Ptr(pframe), ETH_ALEN)) {
+ if (_rtw_memcmp(pwdinfo->nego_req_info.peerDevAddr, get_addr2_ptr(pframe), ETH_ALEN)) {
pwdinfo->nego_req_info.benable = _FALSE;
issue_p2p_GO_request(padapter, pwdinfo->nego_req_info.peerDevAddr);
}
@@ -1812,7 +2215,7 @@ unsigned int OnProbeRsp(_adapter *padapter, union recv_frame *precv_frame)
} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_INVITE_REQ)) {
if (_TRUE == pwdinfo->invitereq_info.benable) {
RTW_INFO("[%s] P2P_STATE_TX_INVITE_REQ!\n", __FUNCTION__);
- if (_rtw_memcmp(pwdinfo->invitereq_info.peer_macaddr, GetAddr2Ptr(pframe), ETH_ALEN)) {
+ if (_rtw_memcmp(pwdinfo->invitereq_info.peer_macaddr, get_addr2_ptr(pframe), ETH_ALEN)) {
pwdinfo->invitereq_info.benable = _FALSE;
issue_p2p_invitation_request(padapter, pwdinfo->invitereq_info.peer_macaddr);
}
@@ -1821,7 +2224,12 @@ unsigned int OnProbeRsp(_adapter *padapter, union recv_frame *precv_frame)
#endif
- if (mlmeext_chk_scan_state(pmlmeext, SCAN_PROCESS)) {
+ if ((mlmeext_chk_scan_state(pmlmeext, SCAN_PROCESS))
+ || (MLME_IS_MESH(padapter) && check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE))
+ #ifdef CONFIG_RTW_REPEATER_SON
+ || (padapter->rtw_rson_scanstage == RSON_SCAN_PROCESS)
+ #endif
+ ) {
rtw_mi_report_survey_event(padapter, precv_frame);
return _SUCCESS;
}
@@ -1829,7 +2237,7 @@ unsigned int OnProbeRsp(_adapter *padapter, union recv_frame *precv_frame)
#if 0 /* move to validate_recv_mgnt_frame */
if (_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN)) {
if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) {
- psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe));
+ psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
if (psta != NULL)
psta->sta_stats.rx_mgnt_pkts++;
}
@@ -1840,6 +2248,51 @@ unsigned int OnProbeRsp(_adapter *padapter, union recv_frame *precv_frame)
}
+/* for 11n Logo 4.2.31/4.2.32 */
+static void rtw_check_legacy_ap(_adapter *padapter, u8 *pframe, u32 len)
+{
+
+ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+
+ if (!padapter->registrypriv.wifi_spec)
+ return;
+
+ if(!MLME_IS_AP(padapter))
+ return;
+
+
+ if (pmlmeext->bstart_bss == _TRUE) {
+ int left;
+ u16 capability;
+ unsigned char *pos;
+ struct rtw_ieee802_11_elems elems;
+ struct HT_info_element *pht_info = NULL;
+ u16 cur_op_mode;
+
+ /* checking IEs */
+ left = len - sizeof(struct rtw_ieee80211_hdr_3addr) - _BEACON_IE_OFFSET_;
+ pos = pframe + sizeof(struct rtw_ieee80211_hdr_3addr) + _BEACON_IE_OFFSET_;
+ if (rtw_ieee802_11_parse_elems(pos, left, &elems, 1) == ParseFailed) {
+ RTW_INFO("%s: parse fail for "MAC_FMT"\n", __func__, MAC_ARG(GetAddr3Ptr(pframe)));
+ return;
+ }
+
+ cur_op_mode = pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_OP_MODE_MASK;
+
+ /* for legacy ap */
+ if (elems.ht_capabilities == NULL && elems.ht_capabilities_len == 0) {
+
+ if (0)
+ RTW_INFO("%s: "MAC_FMT" is legacy ap\n", __func__, MAC_ARG(GetAddr3Ptr(pframe)));
+
+ ATOMIC_SET(&pmlmepriv->olbc, _TRUE);
+ ATOMIC_SET(&pmlmepriv->olbc_ht, _TRUE);
+ }
+
+ }
+}
+
unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame)
{
struct sta_info *psta;
@@ -1861,6 +2314,8 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame)
#endif
#endif /* CONFIG_TDLS */
+ if (validate_beacon_len(pframe, len) == _FALSE)
+ return _SUCCESS;
#ifdef CONFIG_ATTEMPT_TO_FIX_AP_BEACON_ERROR
p = rtw_get_ie(pframe + sizeof(struct rtw_ieee80211_hdr_3addr) + _BEACON_IE_OFFSET_, _EXT_SUPPORTEDRATES_IE_, &ielen,
precv_frame->u.hdr.len - sizeof(struct rtw_ieee80211_hdr_3addr) - _BEACON_IE_OFFSET_);
@@ -1873,13 +2328,28 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame)
}
#endif
- if (mlmeext_chk_scan_state(pmlmeext, SCAN_PROCESS)) {
+ if (mlmeext_chk_scan_state(pmlmeext, SCAN_PROCESS)
+ || (MLME_IS_MESH(padapter) && check_fwstate(pmlmepriv, WIFI_ASOC_STATE))
+ ) {
rtw_mi_report_survey_event(padapter, precv_frame);
return _SUCCESS;
}
+#ifdef CONFIG_RTW_REPEATER_SON
+ if (padapter->rtw_rson_scanstage == RSON_SCAN_PROCESS)
+ rtw_mi_report_survey_event(padapter, precv_frame);
+#endif
+
+ rtw_check_legacy_ap(padapter, pframe, len);
if (_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN)) {
- if (pmlmeinfo->state & WIFI_FW_AUTH_NULL) {
+ if ((pmlmeinfo->state & WIFI_FW_AUTH_NULL)
+ && (rtw_sta_linking_test_wait_done() || pmlmeext->join_abort)
+ ) {
+ if (rtw_sta_linking_test_force_fail() || pmlmeext->join_abort) {
+ set_link_timer(pmlmeext, 1);
+ return _SUCCESS;
+ }
+
/* we should update current network before auth, or some IE is wrong */
pbss = (WLAN_BSSID_EX *)rtw_malloc(sizeof(WLAN_BSSID_EX));
if (pbss) {
@@ -1919,7 +2389,8 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame)
_rtw_memset(pmlmeext->bcn_delay_ratio, 0, sizeof(pmlmeext->bcn_delay_ratio));
#ifdef CONFIG_P2P_PS
- process_p2p_ps_ie(padapter, (pframe + WLAN_HDR_A3_LEN), (len - WLAN_HDR_A3_LEN));
+ /* Comment by YiWei , in wifi p2p spec the "3.3 P2P Power Management" , "These mechanisms are available in a P2P Group in which only P2P Devices are associated." */
+ /* process_p2p_ps_ie(padapter, (pframe + WLAN_HDR_A3_LEN), (len - WLAN_HDR_A3_LEN)); */
#endif /* CONFIG_P2P_PS */
#if defined(CONFIG_P2P) && defined(CONFIG_CONCURRENT_MODE)
@@ -1940,7 +2411,7 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame)
}
if (((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) && (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) {
- psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe));
+ psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
if (psta != NULL) {
#ifdef CONFIG_PATCH_JOIN_WRONG_CHANNEL
/* Merge from 8712 FW code */
@@ -1953,7 +2424,9 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame)
return _SUCCESS;
}
#endif /* CONFIG_PATCH_JOIN_WRONG_CHANNEL */
-
+#ifdef CONFIG_RTW_80211R
+ rtw_ft_update_bcn(padapter, precv_frame);
+#endif
ret = rtw_check_bcn_info(padapter, pframe, len);
if (!ret) {
RTW_PRINT("ap has changed, disconnect now\n ");
@@ -1967,6 +2440,8 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame)
update_beacon_info(padapter, pframe, len, psta);
}
+ pmlmepriv->cur_network_scanned->network.Rssi = precv_frame->u.hdr.attrib.phy_info.recv_signal_power;
+
adaptive_early_32k(pmlmeext, pframe, len);
#ifdef CONFIG_TDLS
@@ -1985,9 +2460,11 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame)
#endif
#endif /* CONFIG_TDLS */
-#ifdef CONFIG_DFS
- process_csa_ie(padapter, pframe, len); /* channel switch announcement */
-#endif /* CONFIG_DFS */
+ #ifdef CONFIG_DFS
+ process_csa_ie(padapter
+ , pframe + WLAN_HDR_A3_LEN + _BEACON_IE_OFFSET_
+ , len - (WLAN_HDR_A3_LEN + _BEACON_IE_OFFSET_));
+ #endif
#ifdef CONFIG_P2P_PS
process_p2p_ps_ie(padapter, (pframe + WLAN_HDR_A3_LEN), (len - WLAN_HDR_A3_LEN));
@@ -2006,7 +2483,7 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame)
u8 rate_set[16];
u8 rate_num = 0;
- psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe));
+ psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
if (psta != NULL) {
/*
* update WMM, ERP in the beacon
@@ -2024,7 +2501,7 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame)
goto _END_ONBEACON_;
}
- psta = rtw_alloc_stainfo(pstapriv, GetAddr2Ptr(pframe));
+ psta = rtw_alloc_stainfo(pstapriv, get_addr2_ptr(pframe));
if (psta == NULL) {
RTW_INFO(FUNC_ADPT_FMT" Exceed the upper limit of supported clients\n", FUNC_ADPT_ARG(padapter));
goto _END_ONBEACON_;
@@ -2039,7 +2516,7 @@ unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame)
update_TSF(pmlmeext, pframe, len);
/* report sta add event */
- report_add_sta_event(padapter, GetAddr2Ptr(pframe));
+ report_add_sta_event(padapter, get_addr2_ptr(pframe));
}
}
}
@@ -2080,9 +2557,32 @@ unsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame)
if ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)
return _FAIL;
+#if defined(CONFIG_IOCTL_CFG80211) && defined(CONFIG_RTW_MESH)
+ if (MLME_IS_MESH(padapter)) {
+ if (!MLME_IS_ASOC(padapter))
+ return _SUCCESS;
+
+ #if CONFIG_RTW_MACADDR_ACL
+ if (rtw_access_ctrl(padapter, get_addr2_ptr(pframe)) == _FALSE)
+ return _SUCCESS;
+ #endif
+
+ if (!rtw_mesh_plink_get(padapter, get_addr2_ptr(pframe))) {
+ if (adapter_to_rfctl(padapter)->offch_state == OFFCHS_NONE)
+ issue_probereq(padapter, &padapter->mlmepriv.cur_network.network.mesh_id, get_addr2_ptr(pframe));
+
+ /* only peer being added (checked by notify conditions) is allowed */
+ return _SUCCESS;
+ }
+
+ rtw_cfg80211_rx_mframe(padapter, precv_frame, NULL);
+ return _SUCCESS;
+ }
+#endif
+
RTW_INFO("+OnAuth\n");
- sa = GetAddr2Ptr(pframe);
+ sa = get_addr2_ptr(pframe);
auth_mode = psecuritypriv->dot11AuthAlgrthm;
@@ -2283,7 +2783,7 @@ unsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame)
pstat = &stat;
_rtw_memset((char *)pstat, '\0', sizeof(stat));
pstat->auth_seq = 2;
- _rtw_memcpy(pstat->hwaddr, sa, 6);
+ _rtw_memcpy(pstat->cmn.mac_addr, sa, 6);
#ifdef CONFIG_NATIVEAP_MLME
issue_auth(padapter, pstat, (unsigned short)status);
@@ -2310,7 +2810,7 @@ unsigned int OnAuthClient(_adapter *padapter, union recv_frame *precv_frame)
if (!_rtw_memcmp(adapter_mac_addr(padapter), get_da(pframe), ETH_ALEN))
return _SUCCESS;
- if (!(pmlmeinfo->state & WIFI_FW_AUTH_STATE))
+ if (!(pmlmeinfo->state & WIFI_FW_AUTH_STATE) || pmlmeext->join_abort)
return _SUCCESS;
offset = (GetPrivacy(pframe)) ? 4 : 0;
@@ -2351,7 +2851,7 @@ unsigned int OnAuthClient(_adapter *padapter, union recv_frame *precv_frame)
return _SUCCESS;
} else {
- /* open system */
+ /* open, or 802.11r FTAA system */
go2asoc = 1;
}
} else if (seq == 4) {
@@ -2366,6 +2866,10 @@ unsigned int OnAuthClient(_adapter *padapter, union recv_frame *precv_frame)
}
if (go2asoc) {
+#ifdef CONFIG_RTW_80211R
+ if (rtw_ft_update_auth_rsp_ies(padapter, pframe, pkt_len))
+ return _SUCCESS;
+#endif
RTW_PRINT("auth success, start assoc\n");
start_clnt_assoc(padapter);
return _SUCCESS;
@@ -2386,15 +2890,11 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame)
u16 capab_info, listen_interval;
struct rtw_ieee802_11_elems elems;
struct sta_info *pstat;
- unsigned char reassoc, *p, *pos, *wpa_ie;
- unsigned char WMM_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01};
- int i, ie_len, wpa_ie_len, left;
- u8 rate_set[16];
- u8 rate_num;
+ unsigned char reassoc, *p, *pos;
+ int i, ie_len, left;
unsigned short status = _STATS_SUCCESSFUL_;
unsigned short frame_type, ie_offset = 0;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
- struct security_priv *psecuritypriv = &padapter->securitypriv;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
WLAN_BSSID_EX *cur = &(pmlmeinfo->network);
@@ -2419,7 +2919,7 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame)
if ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)
return _FAIL;
- frame_type = GetFrameSubType(pframe);
+ frame_type = get_frame_sub_type(pframe);
if (frame_type == WIFI_ASSOCREQ) {
reassoc = 0;
ie_offset = _ASOCREQ_IE_OFFSET_;
@@ -2435,21 +2935,12 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame)
return _FAIL;
}
- pstat = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe));
+ pstat = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
if (pstat == (struct sta_info *)NULL) {
status = _RSON_CLS2_;
goto asoc_class2_error;
}
- capab_info = RTW_GET_LE16(pframe + WLAN_HDR_A3_LEN);
- /* capab_info = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN)); */
- /* listen_interval = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN+2)); */
- listen_interval = RTW_GET_LE16(pframe + WLAN_HDR_A3_LEN + 2);
-
- left = pkt_len - (IEEE80211_3ADDR_LEN + ie_offset);
- pos = pframe + (IEEE80211_3ADDR_LEN + ie_offset);
-
-
RTW_INFO("%s\n", __FUNCTION__);
/* check if this stat has been successfully authenticated/assocated */
@@ -2466,7 +2957,6 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame)
pstat->state |= WIFI_FW_ASSOC_STATE;
}
-
#if 0/* todo:tkip_countermeasures */
if (hapd->tkip_countermeasures) {
resp = WLAN_REASON_MICHAEL_MIC_FAILURE;
@@ -2474,8 +2964,19 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame)
}
#endif
- pstat->capability = capab_info;
+ /* now parse all ieee802_11 ie to point to elems */
+ left = pkt_len - (IEEE80211_3ADDR_LEN + ie_offset);
+ pos = pframe + (IEEE80211_3ADDR_LEN + ie_offset);
+ if (rtw_ieee802_11_parse_elems(pos, left, &elems, 1) == ParseFailed) {
+ RTW_INFO("STA " MAC_FMT " sent invalid association request\n",
+ MAC_ARG(pstat->cmn.mac_addr));
+ status = _STATS_FAILURE_;
+ goto OnAssocReqFail;
+ }
+
+ rtw_ap_parse_sta_capability(padapter, pstat, pframe + WLAN_HDR_A3_LEN);
+ listen_interval = RTW_GET_LE16(pframe + WLAN_HDR_A3_LEN + 2);
#if 0/* todo: */
/* check listen_interval */
if (listen_interval > hapd->conf->max_listen_interval) {
@@ -2490,290 +2991,40 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame)
pstat->listen_interval = listen_interval;
#endif
- /* now parse all ieee802_11 ie to point to elems */
- if (rtw_ieee802_11_parse_elems(pos, left, &elems, 1) == ParseFailed ||
- !elems.ssid) {
- RTW_INFO("STA " MAC_FMT " sent invalid association request\n",
- MAC_ARG(pstat->hwaddr));
+ /* now we should check all the fields... */
+ /* checking SSID */
+ if (elems.ssid == NULL
+ || elems.ssid_len == 0
+ || elems.ssid_len != cur->Ssid.SsidLength
+ || _rtw_memcmp(elems.ssid, cur->Ssid.Ssid, cur->Ssid.SsidLength) == _FALSE
+ ) {
status = _STATS_FAILURE_;
goto OnAssocReqFail;
}
-
- /* now we should check all the fields... */
- /* checking SSID */
- p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + ie_offset, _SSID_IE_, &ie_len,
- pkt_len - WLAN_HDR_A3_LEN - ie_offset);
- if (p == NULL)
- status = _STATS_FAILURE_;
-
- if (ie_len == 0) /* broadcast ssid, however it is not allowed in assocreq */
- status = _STATS_FAILURE_;
- else {
- /* check if ssid match */
- if (!_rtw_memcmp((void *)(p + 2), cur->Ssid.Ssid, cur->Ssid.SsidLength))
- status = _STATS_FAILURE_;
-
- if (ie_len != cur->Ssid.SsidLength)
- status = _STATS_FAILURE_;
- }
-
- if (_STATS_SUCCESSFUL_ != status)
- goto OnAssocReqFail;
-
- rtw_ies_get_supported_rate(pframe + WLAN_HDR_A3_LEN + ie_offset, pkt_len - WLAN_HDR_A3_LEN - ie_offset, rate_set, &rate_num);
- if (rate_num == 0) {
- RTW_INFO(FUNC_ADPT_FMT" RX assoc-req with no supported rate\n", FUNC_ADPT_ARG(padapter));
- status = _STATS_FAILURE_;
- goto OnAssocReqFail;
- }
- _rtw_memcpy(pstat->bssrateset, rate_set, rate_num);
- pstat->bssratelen = rate_num;
- UpdateBrateTblForSoftAP(pstat->bssrateset, pstat->bssratelen);
+ /* (Extended) Supported rates */
+ status = rtw_ap_parse_sta_supported_rates(padapter, pstat
+ , pframe + WLAN_HDR_A3_LEN + ie_offset, pkt_len - WLAN_HDR_A3_LEN - ie_offset);
+ if (status != _STATS_SUCCESSFUL_)
+ goto OnAssocReqFail;
/* check RSN/WPA/WPS */
- pstat->dot8021xalg = 0;
- pstat->wpa_psk = 0;
- pstat->wpa_group_cipher = 0;
- pstat->wpa2_group_cipher = 0;
- pstat->wpa_pairwise_cipher = 0;
- pstat->wpa2_pairwise_cipher = 0;
- _rtw_memset(pstat->wpa_ie, 0, sizeof(pstat->wpa_ie));
- if ((psecuritypriv->wpa_psk & BIT(1)) && elems.rsn_ie) {
-
- int group_cipher = 0, pairwise_cipher = 0;
-
- wpa_ie = elems.rsn_ie;
- wpa_ie_len = elems.rsn_ie_len;
-
- if (rtw_parse_wpa2_ie(wpa_ie - 2, wpa_ie_len + 2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) {
- pstat->dot8021xalg = 1;/* psk, todo:802.1x */
- pstat->wpa_psk |= BIT(1);
-
- pstat->wpa2_group_cipher = group_cipher & psecuritypriv->wpa2_group_cipher;
- pstat->wpa2_pairwise_cipher = pairwise_cipher & psecuritypriv->wpa2_pairwise_cipher;
-
- if (!pstat->wpa2_group_cipher)
- status = WLAN_STATUS_GROUP_CIPHER_NOT_VALID;
-
- if (!pstat->wpa2_pairwise_cipher)
- status = WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID;
- } else
- status = WLAN_STATUS_INVALID_IE;
-
- } else if ((psecuritypriv->wpa_psk & BIT(0)) && elems.wpa_ie) {
-
- int group_cipher = 0, pairwise_cipher = 0;
-
- wpa_ie = elems.wpa_ie;
- wpa_ie_len = elems.wpa_ie_len;
-
- if (rtw_parse_wpa_ie(wpa_ie - 2, wpa_ie_len + 2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) {
- pstat->dot8021xalg = 1;/* psk, todo:802.1x */
- pstat->wpa_psk |= BIT(0);
-
- pstat->wpa_group_cipher = group_cipher & psecuritypriv->wpa_group_cipher;
- pstat->wpa_pairwise_cipher = pairwise_cipher & psecuritypriv->wpa_pairwise_cipher;
-
- if (!pstat->wpa_group_cipher)
- status = WLAN_STATUS_GROUP_CIPHER_NOT_VALID;
-
- if (!pstat->wpa_pairwise_cipher)
- status = WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID;
-
- } else
- status = WLAN_STATUS_INVALID_IE;
-
- } else {
- wpa_ie = NULL;
- wpa_ie_len = 0;
- }
-
- if (_STATS_SUCCESSFUL_ != status)
+ status = rtw_ap_parse_sta_security_ie(padapter, pstat, &elems);
+ if (status != _STATS_SUCCESSFUL_)
goto OnAssocReqFail;
- pstat->flags &= ~(WLAN_STA_WPS | WLAN_STA_MAYBE_WPS);
- /* if (hapd->conf->wps_state && wpa_ie == NULL) { */ /* todo: to check ap if supporting WPS */
- if (wpa_ie == NULL) {
- if (elems.wps_ie) {
- RTW_INFO("STA included WPS IE in "
- "(Re)Association Request - assume WPS is "
- "used\n");
- pstat->flags |= WLAN_STA_WPS;
- /* wpabuf_free(sta->wps_ie); */
- /* sta->wps_ie = wpabuf_alloc_copy(elems.wps_ie + 4, */
- /* elems.wps_ie_len - 4); */
- } else {
- RTW_INFO("STA did not include WPA/RSN IE "
- "in (Re)Association Request - possible WPS "
- "use\n");
- pstat->flags |= WLAN_STA_MAYBE_WPS;
- }
-
-
- /* AP support WPA/RSN, and sta is going to do WPS, but AP is not ready */
- /* that the selected registrar of AP is _FLASE */
- if ((psecuritypriv->wpa_psk > 0)
- && (pstat->flags & (WLAN_STA_WPS | WLAN_STA_MAYBE_WPS))) {
- if (pmlmepriv->wps_beacon_ie) {
- u8 selected_registrar = 0;
-
- rtw_get_wps_attr_content(pmlmepriv->wps_beacon_ie, pmlmepriv->wps_beacon_ie_len, WPS_ATTR_SELECTED_REGISTRAR , &selected_registrar, NULL);
-
- if (!selected_registrar) {
- RTW_INFO("selected_registrar is _FALSE , or AP is not ready to do WPS\n");
-
- status = _STATS_UNABLE_HANDLE_STA_;
-
- goto OnAssocReqFail;
- }
- }
- }
-
- } else {
- int copy_len;
-
- if (psecuritypriv->wpa_psk == 0) {
- RTW_INFO("STA " MAC_FMT ": WPA/RSN IE in association "
- "request, but AP don't support WPA/RSN\n", MAC_ARG(pstat->hwaddr));
-
- status = WLAN_STATUS_INVALID_IE;
-
- goto OnAssocReqFail;
-
- }
-
- if (elems.wps_ie) {
- RTW_INFO("STA included WPS IE in "
- "(Re)Association Request - WPS is "
- "used\n");
- pstat->flags |= WLAN_STA_WPS;
- copy_len = 0;
- } else
- copy_len = ((wpa_ie_len + 2) > sizeof(pstat->wpa_ie)) ? (sizeof(pstat->wpa_ie)) : (wpa_ie_len + 2);
-
-
- if (copy_len > 0)
- _rtw_memcpy(pstat->wpa_ie, wpa_ie - 2, copy_len);
-
- }
-
-
/* check if there is WMM IE & support WWM-PS */
- pstat->flags &= ~WLAN_STA_WME;
- pstat->qos_option = 0;
- pstat->qos_info = 0;
- pstat->has_legacy_ac = _TRUE;
- pstat->uapsd_vo = 0;
- pstat->uapsd_vi = 0;
- pstat->uapsd_be = 0;
- pstat->uapsd_bk = 0;
- if (pmlmepriv->qospriv.qos_option) {
- p = pframe + WLAN_HDR_A3_LEN + ie_offset;
- ie_len = 0;
- for (;;) {
- p = rtw_get_ie(p, _VENDOR_SPECIFIC_IE_, &ie_len, pkt_len - WLAN_HDR_A3_LEN - ie_offset);
- if (p != NULL) {
- if (_rtw_memcmp(p + 2, WMM_IE, 6)) {
-
- pstat->flags |= WLAN_STA_WME;
-
- pstat->qos_option = 1;
- pstat->qos_info = *(p + 8);
-
- pstat->max_sp_len = (pstat->qos_info >> 5) & 0x3;
-
- if ((pstat->qos_info & 0xf) != 0xf)
- pstat->has_legacy_ac = _TRUE;
- else
- pstat->has_legacy_ac = _FALSE;
-
- if (pstat->qos_info & 0xf) {
- if (pstat->qos_info & BIT(0))
- pstat->uapsd_vo = BIT(0) | BIT(1);
- else
- pstat->uapsd_vo = 0;
+ rtw_ap_parse_sta_wmm_ie(padapter, pstat
+ , pframe + WLAN_HDR_A3_LEN + ie_offset, pkt_len - WLAN_HDR_A3_LEN - ie_offset);
- if (pstat->qos_info & BIT(1))
- pstat->uapsd_vi = BIT(0) | BIT(1);
- else
- pstat->uapsd_vi = 0;
-
- if (pstat->qos_info & BIT(2))
- pstat->uapsd_bk = BIT(0) | BIT(1);
- else
- pstat->uapsd_bk = 0;
-
- if (pstat->qos_info & BIT(3))
- pstat->uapsd_be = BIT(0) | BIT(1);
- else
- pstat->uapsd_be = 0;
-
- }
-
- break;
- }
- } else
- break;
- p = p + ie_len + 2;
- }
- }
-
-
-#ifdef CONFIG_80211N_HT
- if (pmlmepriv->htpriv.ht_option == _FALSE)
- goto bypass_ht_chk;
-
- /* save HT capabilities in the sta object */
- _rtw_memset(&pstat->htpriv.ht_cap, 0, sizeof(struct rtw_ieee80211_ht_cap));
- if (elems.ht_capabilities && elems.ht_capabilities_len >= sizeof(struct rtw_ieee80211_ht_cap)) {
- pstat->flags |= WLAN_STA_HT;
-
- pstat->flags |= WLAN_STA_WME;
-
- _rtw_memcpy(&pstat->htpriv.ht_cap, elems.ht_capabilities, sizeof(struct rtw_ieee80211_ht_cap));
-
- } else
- pstat->flags &= ~WLAN_STA_HT;
-bypass_ht_chk:
-
- if ((pmlmepriv->htpriv.ht_option == _FALSE) && (pstat->flags & WLAN_STA_HT)) {
- rtw_warn_on(1);
- status = _STATS_FAILURE_;
- goto OnAssocReqFail;
- }
-#endif /* CONFIG_80211N_HT */
-
-#ifdef CONFIG_80211AC_VHT
- if (pmlmepriv->vhtpriv.vht_option == _FALSE)
- goto bypass_vht_chk;
-
- _rtw_memset(&pstat->vhtpriv, 0, sizeof(struct vht_priv));
- if (elems.vht_capabilities && elems.vht_capabilities_len == 12) {
- pstat->flags |= WLAN_STA_VHT;
-
- _rtw_memcpy(pstat->vhtpriv.vht_cap, elems.vht_capabilities, 12);
-
- if (elems.vht_op_mode_notify && elems.vht_op_mode_notify_len == 1)
- _rtw_memcpy(&pstat->vhtpriv.vht_op_mode_notify, elems.vht_op_mode_notify, 1);
- else /* for Frame without Operating Mode notify ie; default: 80M */
- pstat->vhtpriv.vht_op_mode_notify = CHANNEL_WIDTH_80;
- } else
- pstat->flags &= ~WLAN_STA_VHT;
-bypass_vht_chk:
-
- if ((pmlmepriv->vhtpriv.vht_option == _FALSE) && (pstat->flags & WLAN_STA_VHT)) {
- rtw_warn_on(1);
- status = _STATS_FAILURE_;
- goto OnAssocReqFail;
- }
-#endif /* CONFIG_80211AC_VHT */
+ rtw_ap_parse_sta_ht_ie(padapter, pstat, &elems);
+ rtw_ap_parse_sta_vht_ie(padapter, pstat, &elems);
if (((pstat->flags & WLAN_STA_HT) || (pstat->flags & WLAN_STA_VHT)) &&
((pstat->wpa2_pairwise_cipher & WPA_CIPHER_TKIP) ||
(pstat->wpa_pairwise_cipher & WPA_CIPHER_TKIP))) {
- RTW_INFO("(V)HT: " MAC_FMT " tried to use TKIP with (V)HT association\n", MAC_ARG(pstat->hwaddr));
+ RTW_INFO("(V)HT: " MAC_FMT " tried to use TKIP with (V)HT association\n", MAC_ARG(pstat->cmn.mac_addr));
pstat->flags &= ~WLAN_STA_HT;
pstat->flags &= ~WLAN_STA_VHT;
@@ -2782,24 +3033,6 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame)
*/
}
-
- /*
- * if (hapd->iface->current_mode->mode == HOSTAPD_MODE_IEEE80211G) */ /* ? */
- pstat->flags |= WLAN_STA_NONERP;
- for (i = 0; i < pstat->bssratelen; i++) {
- if ((pstat->bssrateset[i] & 0x7f) > 22) {
- pstat->flags &= ~WLAN_STA_NONERP;
- break;
- }
- }
-
- if (pstat->capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
- pstat->flags |= WLAN_STA_SHORT_PREAMBLE;
- else
- pstat->flags &= ~WLAN_STA_SHORT_PREAMBLE;
-
-
-
if (status != _STATS_SUCCESSFUL_)
goto OnAssocReqFail;
@@ -2823,44 +3056,37 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame)
pstat->p2p_status_code = p2p_status_code;
#endif /* CONFIG_P2P */
+#ifdef CONFIG_RTW_REPEATER_SON
+ if (rtw_rson_ap_check_sta(padapter, pframe, pkt_len, ie_offset))
+ goto OnAssocReqFail;
+#endif
+
/* TODO: identify_proprietary_vendor_ie(); */
/* Realtek proprietary IE */
/* identify if this is Broadcom sta */
/* identify if this is ralink sta */
/* Customer proprietary IE */
+#ifdef CONFIG_RTW_80211K
+ rtw_ap_parse_sta_rm_en_cap(padapter, pstat, &elems);
+#endif
-
- /* get a unique AID */
- if (pstat->aid > 0)
- RTW_INFO(" old AID %d\n", pstat->aid);
+ /* AID assignment */
+ if (pstat->cmn.aid > 0)
+ RTW_INFO(FUNC_ADPT_FMT" old AID=%d\n", FUNC_ADPT_ARG(padapter), pstat->cmn.aid);
else {
- for (pstat->aid = 1; pstat->aid <= NUM_STA; pstat->aid++) {
- if (pstapriv->sta_aid[pstat->aid - 1] == NULL) {
- if (pstat->aid > pstapriv->max_num_sta) {
- pstat->aid = 0;
-
- RTW_INFO(" no room for more AIDs\n");
-
- status = WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA;
-
- goto OnAssocReqFail;
-
-
- } else {
- pstapriv->sta_aid[pstat->aid - 1] = pstat;
- RTW_INFO("allocate new AID = (%d)\n", pstat->aid);
- break;
- }
- }
+ if (!rtw_aid_alloc(padapter, pstat)) {
+ RTW_INFO(FUNC_ADPT_FMT" no room for more AIDs\n", FUNC_ADPT_ARG(padapter));
+ status = WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA;
+ goto OnAssocReqFail;
}
+ RTW_INFO(FUNC_ADPT_FMT" allocate new AID=%d\n", FUNC_ADPT_ARG(padapter), pstat->cmn.aid);
}
-
pstat->state &= (~WIFI_FW_ASSOC_STATE);
pstat->state |= WIFI_FW_ASSOC_SUCCESS;
/* RTW_INFO("==================%s, %d, (%x), bpairwise_key_installed=%d, MAC:"MAC_FMT"\n"
- , __func__, __LINE__, pstat->state, pstat->bpairwise_key_installed, MAC_ARG(pstat->hwaddr)); */
+ , __func__, __LINE__, pstat->state, pstat->bpairwise_key_installed, MAC_ARG(pstat->cmn.mac_addr)); */
#ifdef CONFIG_IEEE80211W
if (pstat->bpairwise_key_installed != _TRUE)
#endif /* CONFIG_IEEE80211W */
@@ -2922,12 +3148,12 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame)
#endif /* CONFIG_IEEE80211W */
{
/* .3-(1) report sta add event */
- report_add_sta_event(padapter, pstat->hwaddr);
+ report_add_sta_event(padapter, pstat->cmn.mac_addr);
}
#ifdef CONFIG_IEEE80211W
- if (pstat->bpairwise_key_installed == _TRUE && padapter->securitypriv.binstallBIPkey == _TRUE) {
- RTW_INFO(MAC_FMT"\n", MAC_ARG(pstat->hwaddr));
- issue_action_SA_Query(padapter, pstat->hwaddr, 0, 0, IEEE80211W_RIGHT_KEY);
+ if (pstat->bpairwise_key_installed == _TRUE && SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) == _TRUE) {
+ RTW_INFO(MAC_FMT"\n", MAC_ARG(pstat->cmn.mac_addr));
+ issue_action_SA_Query(padapter, pstat->cmn.mac_addr, 0, 0, IEEE80211W_RIGHT_KEY);
}
#endif /* CONFIG_IEEE80211W */
#endif /* CONFIG_NATIVEAP_MLME */
@@ -2938,7 +3164,7 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame)
asoc_class2_error:
#ifdef CONFIG_NATIVEAP_MLME
- issue_deauth(padapter, (void *)GetAddr2Ptr(pframe), status);
+ issue_deauth(padapter, (void *)get_addr2_ptr(pframe), status);
#endif
return _FAIL;
@@ -2947,7 +3173,7 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame)
#ifdef CONFIG_NATIVEAP_MLME
- pstat->aid = 0;
+ pstat->cmn.aid = 0;
if (frame_type == WIFI_ASSOCREQ)
issue_asocrsp(padapter, status, pstat, WIFI_ASSOCRSP);
else
@@ -2961,6 +3187,34 @@ unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame)
}
+#if defined(CONFIG_LAYER2_ROAMING) && defined(CONFIG_RTW_80211K)
+void rtw_roam_nb_discover(_adapter *padapter, u8 bfroce)
+{
+ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+ struct sta_priv *pstapriv = &padapter->stapriv;
+ struct sta_info *psta;
+ u8 nb_req_issue = _FALSE;
+
+ if (!check_fwstate(pmlmepriv, _FW_LINKED))
+ return;
+
+ if (!rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE))
+ return;
+
+ psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress);
+ if (!psta)
+ return;
+
+ if (bfroce || (!pmlmepriv->nb_info.nb_rpt_is_same))
+ nb_req_issue = _TRUE;
+
+ if (nb_req_issue && (psta->rm_en_cap[0] & RTW_RRM_NB_RPT_EN))
+ rm_add_nb_req(padapter, psta);
+}
+#endif
+
unsigned int OnAssocRsp(_adapter *padapter, union recv_frame *precv_frame)
{
uint i;
@@ -2981,7 +3235,7 @@ unsigned int OnAssocRsp(_adapter *padapter, union recv_frame *precv_frame)
if (!_rtw_memcmp(adapter_mac_addr(padapter), get_da(pframe), ETH_ALEN))
return _SUCCESS;
- if (!(pmlmeinfo->state & (WIFI_FW_AUTH_SUCCESS | WIFI_FW_ASSOC_STATE)))
+ if (!(pmlmeinfo->state & (WIFI_FW_AUTH_SUCCESS | WIFI_FW_ASSOC_STATE)) || pmlmeext->join_abort)
return _SUCCESS;
if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)
@@ -3058,6 +3312,12 @@ unsigned int OnAssocRsp(_adapter *padapter, union recv_frame *precv_frame)
padapter->tdlsinfo.ch_switch_prohibited = _TRUE;
break;
#endif /* CONFIG_TDLS */
+
+#ifdef CONFIG_RTW_80211K
+ case _EID_RRM_EN_CAP_IE_:
+ RM_IE_handler(padapter, pIE);
+ break;
+#endif
default:
break;
}
@@ -3083,6 +3343,9 @@ unsigned int OnAssocRsp(_adapter *padapter, union recv_frame *precv_frame)
report_join_res(padapter, res);
+#if defined(CONFIG_LAYER2_ROAMING) && defined(CONFIG_RTW_80211K)
+ rtw_roam_nb_discover(padapter, _TRUE);
+#endif
return _SUCCESS;
}
@@ -3112,10 +3375,8 @@ unsigned int OnDeAuth(_adapter *padapter, union recv_frame *precv_frame)
reason = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN));
- rtw_lock_rx_suspend_timeout(8000);
-
#ifdef CONFIG_AP_MODE
- if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) {
+ if (MLME_IS_AP(padapter)) {
_irqL irqL;
struct sta_info *psta;
struct sta_priv *pstapriv = &padapter->stapriv;
@@ -3125,9 +3386,9 @@ unsigned int OnDeAuth(_adapter *padapter, union recv_frame *precv_frame)
/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */
RTW_PRINT(FUNC_ADPT_FMT" reason=%u, ta=%pM\n"
- , FUNC_ADPT_ARG(padapter), reason, GetAddr2Ptr(pframe));
+ , FUNC_ADPT_ARG(padapter), reason, get_addr2_ptr(pframe));
- psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe));
+ psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
if (psta) {
u8 updated = _FALSE;
@@ -3147,7 +3408,7 @@ unsigned int OnDeAuth(_adapter *padapter, union recv_frame *precv_frame)
return _SUCCESS;
} else
#endif
- {
+ if (!MLME_IS_MESH(padapter)) {
int ignore_received_deauth = 0;
/* Commented by Albert 20130604 */
@@ -3166,10 +3427,10 @@ unsigned int OnDeAuth(_adapter *padapter, union recv_frame *precv_frame)
}
RTW_PRINT(FUNC_ADPT_FMT" reason=%u, ta=%pM, ignore=%d\n"
- , FUNC_ADPT_ARG(padapter), reason, GetAddr2Ptr(pframe), ignore_received_deauth);
+ , FUNC_ADPT_ARG(padapter), reason, get_addr2_ptr(pframe), ignore_received_deauth);
if (0 == ignore_received_deauth)
- receive_disconnect(padapter, GetAddr2Ptr(pframe), reason, _FALSE);
+ receive_disconnect(padapter, get_addr2_ptr(pframe), reason, _FALSE);
}
pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE;
return _SUCCESS;
@@ -3202,10 +3463,8 @@ unsigned int OnDisassoc(_adapter *padapter, union recv_frame *precv_frame)
reason = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN));
- rtw_lock_rx_suspend_timeout(8000);
-
#ifdef CONFIG_AP_MODE
- if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) {
+ if (MLME_IS_AP(padapter)) {
_irqL irqL;
struct sta_info *psta;
struct sta_priv *pstapriv = &padapter->stapriv;
@@ -3215,9 +3474,9 @@ unsigned int OnDisassoc(_adapter *padapter, union recv_frame *precv_frame)
/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */
RTW_PRINT(FUNC_ADPT_FMT" reason=%u, ta=%pM\n"
- , FUNC_ADPT_ARG(padapter), reason, GetAddr2Ptr(pframe));
+ , FUNC_ADPT_ARG(padapter), reason, get_addr2_ptr(pframe));
- psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe));
+ psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
if (psta) {
u8 updated = _FALSE;
@@ -3236,11 +3495,11 @@ unsigned int OnDisassoc(_adapter *padapter, union recv_frame *precv_frame)
return _SUCCESS;
} else
#endif
- {
+ if (!MLME_IS_MESH(padapter)) {
RTW_PRINT(FUNC_ADPT_FMT" reason=%u, ta=%pM\n"
- , FUNC_ADPT_ARG(padapter), reason, GetAddr2Ptr(pframe));
+ , FUNC_ADPT_ARG(padapter), reason, get_addr2_ptr(pframe));
- receive_disconnect(padapter, GetAddr2Ptr(pframe), reason, _FALSE);
+ receive_disconnect(padapter, get_addr2_ptr(pframe), reason, _FALSE);
}
pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE;
return _SUCCESS;
@@ -3272,7 +3531,7 @@ unsigned int on_action_spct_ch_switch(_adapter *padapter, struct sta_info *psta,
struct ieee80211_info_element *ie;
RTW_INFO(FUNC_NDEV_FMT" from "MAC_FMT"\n",
- FUNC_NDEV_ARG(padapter->pnetdev), MAC_ARG(psta->hwaddr));
+ FUNC_NDEV_ARG(padapter->pnetdev), MAC_ARG(psta->cmn.mac_addr));
for_each_ie(ie, ies, ies_len) {
if (ie->id == WLAN_EID_CHANNEL_SWITCH) {
@@ -3303,7 +3562,7 @@ unsigned int on_action_spct_ch_switch(_adapter *padapter, struct sta_info *psta,
* 2. things after channel switching
*/
- ret = rtw_set_ch_cmd(padapter, ch, bwmode, ch_offset, _TRUE);
+ ret = rtw_set_chbw_cmd(padapter, ch, bwmode, ch_offset, 0);
}
exit:
@@ -3321,9 +3580,7 @@ unsigned int on_action_spct(_adapter *padapter, union recv_frame *precv_frame)
u8 category;
u8 action;
- RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(padapter->pnetdev));
-
- psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe));
+ psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
if (!psta)
goto exit;
@@ -3333,6 +3590,9 @@ unsigned int on_action_spct(_adapter *padapter, union recv_frame *precv_frame)
goto exit;
action = frame_body[1];
+
+ RTW_INFO(FUNC_ADPT_FMT" action:%u\n", FUNC_ADPT_ARG(padapter), action);
+
switch (action) {
case RTW_WLAN_ACTION_SPCT_MSR_REQ:
case RTW_WLAN_ACTION_SPCT_MSR_RPRT:
@@ -3341,8 +3601,13 @@ unsigned int on_action_spct(_adapter *padapter, union recv_frame *precv_frame)
break;
case RTW_WLAN_ACTION_SPCT_CHL_SWITCH:
#ifdef CONFIG_SPCT_CH_SWITCH
- ret = on_action_spct_ch_switch(padapter, psta, &frame_body[2],
- frame_len - (frame_body - pframe) - 2);
+ ret = on_action_spct_ch_switch(padapter, psta
+ , frame_body + 2, frame_len - (frame_body - pframe) - 2);
+#elif defined(CONFIG_DFS)
+ if (MLME_IS_STA(padapter) && MLME_IS_ASOC(padapter)) {
+ process_csa_ie(padapter
+ , frame_body + 2, frame_len - (frame_body - pframe) - 2);
+ }
#endif
break;
default:
@@ -3363,6 +3628,55 @@ unsigned int OnAction_dls(_adapter *padapter, union recv_frame *precv_frame)
return _SUCCESS;
}
+#ifdef CONFIG_RTW_WNM
+unsigned int on_action_wnm(_adapter *adapter, union recv_frame *rframe)
+{
+ unsigned int ret = _FAIL;
+ struct sta_info *sta = NULL;
+ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
+ struct sta_priv *stapriv = &(adapter->stapriv);
+ u8 *frame = rframe->u.hdr.rx_data;
+ u32 frame_len = rframe->u.hdr.len;
+ u8 *frame_body = (u8 *)(frame + sizeof(struct rtw_ieee80211_hdr_3addr));
+ u32 frame_body_len = frame_len - sizeof(struct rtw_ieee80211_hdr_3addr);
+ u8 category, action;
+ int cnt = 0;
+ char msg[16];
+
+ sta = rtw_get_stainfo(stapriv, get_addr2_ptr(frame));
+ if (!sta)
+ goto exit;
+
+ category = frame_body[0];
+ if (category != RTW_WLAN_CATEGORY_WNM)
+ goto exit;
+
+ action = frame_body[1];
+
+ switch (action) {
+#ifdef CONFIG_RTW_80211R
+ case RTW_WLAN_ACTION_WNM_BTM_REQ:
+ if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) {
+ RTW_INFO("WNM: RTW_WLAN_ACTION_WNM_BTM_REQ recv.\n");
+ rtw_wnm_process_btm_req(adapter, frame_body, frame_body_len);
+ }
+ ret = _SUCCESS;
+ break;
+#endif
+ default:
+ #ifdef CONFIG_IOCTL_CFG80211
+ cnt += sprintf((msg + cnt), "ACT_WNM %u", action);
+ rtw_cfg80211_rx_action(adapter, rframe, msg);
+ #endif
+ ret = _SUCCESS;
+ break;
+ }
+
+exit:
+ return ret;
+}
+#endif /* CONFIG_RTW_WNM */
+
/**
* rtw_rx_ampdu_size - Get the target RX AMPDU buffer size for the specific @adapter
* @adapter: the adapter to get target RX AMPDU buffer size
@@ -3374,11 +3688,6 @@ u8 rtw_rx_ampdu_size(_adapter *adapter)
u8 size;
HT_CAP_AMPDU_FACTOR max_rx_ampdu_factor;
- if (adapter->fix_rx_ampdu_size != RX_AMPDU_SIZE_INVALID) {
- size = adapter->fix_rx_ampdu_size;
- goto exit;
- }
-
#ifdef CONFIG_BT_COEXIST
if (rtw_btcoex_IsBTCoexCtrlAMPDUSize(adapter) == _TRUE) {
size = rtw_btcoex_GetAMPDUSize(adapter);
@@ -3400,7 +3709,14 @@ u8 rtw_rx_ampdu_size(_adapter *adapter)
max_rx_ampdu_factor = (HT_CAP_AMPDU_FACTOR)adapter->driver_rx_ampdu_factor;
else
rtw_hal_get_def_var(adapter, HW_VAR_MAX_RX_AMPDU_FACTOR, &max_rx_ampdu_factor);
-
+
+ /* In Maximum A-MPDU Length Exponent subfield of A-MPDU Parameters field of HT Capabilities element,
+ the unit of max_rx_ampdu_factor are octets. 8K, 16K, 32K, 64K is right.
+ But the buffer size subfield of Block Ack Parameter Set field in ADDBA action frame indicates
+ the number of buffers available for this particular TID. Each buffer is equal to max. size of
+ MSDU or AMSDU.
+ The size variable means how many MSDUs or AMSDUs, it's not Kbytes.
+ */
if (MAX_AMPDU_FACTOR_64K == max_rx_ampdu_factor)
size = 64;
else if (MAX_AMPDU_FACTOR_32K == max_rx_ampdu_factor)
@@ -3569,6 +3885,35 @@ u8 rx_ampdu_apply_sta_tid(_adapter *adapter, struct sta_info *sta, u8 tid, u8 ac
return ret;
}
+u8 rx_ampdu_size_sta_limit(_adapter *adapter, struct sta_info *sta)
+{
+ u8 sz_limit = 0xFF;
+
+#ifdef CONFIG_80211N_HT
+ struct registry_priv *regsty = adapter_to_regsty(adapter);
+ struct mlme_priv *mlme = &adapter->mlmepriv;
+ struct mlme_ext_info *mlmeinfo = &adapter->mlmeextpriv.mlmext_info;
+ s8 nss = -1;
+ u8 bw = rtw_min(sta->cmn.bw_mode, adapter->mlmeextpriv.cur_bwmode);
+
+ #ifdef CONFIG_80211AC_VHT
+ if (is_supported_vht(sta->wireless_mode)) {
+ nss = rtw_min(rtw_vht_mcsmap_to_nss(mlme->vhtpriv.vht_mcs_map)
+ , rtw_vht_mcsmap_to_nss(sta->vhtpriv.vht_mcs_map));
+ } else
+ #endif
+ if (is_supported_ht(sta->wireless_mode)) {
+ nss = rtw_min(rtw_ht_mcsset_to_nss(mlmeinfo->HT_caps.u.HT_cap_element.MCS_rate)
+ , rtw_ht_mcsset_to_nss(sta->htpriv.ht_cap.supp_mcs_set));
+ }
+
+ if (nss >= 1)
+ sz_limit = regsty->rx_ampdu_sz_limit_by_nss_bw[nss - 1][bw];
+#endif /* CONFIG_80211N_HT */
+
+ return sz_limit;
+}
+
/**
* rx_ampdu_apply_sta - Apply RX AMPDU setting to the specific @sta
* @adapter: the adapter to which @sta belongs
@@ -3602,19 +3947,28 @@ u8 rx_ampdu_apply_sta(_adapter *adapter, struct sta_info *sta, u8 accept, u8 siz
u16 rtw_rx_ampdu_apply(_adapter *adapter)
{
u16 adj_cnt = 0;
- struct mlme_ext_priv *mlmeext;
+ struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
struct sta_info *sta;
u8 accept = rtw_rx_ampdu_is_accept(adapter);
- u8 size = rtw_rx_ampdu_size(adapter);
+ u8 size;
- mlmeext = &adapter->mlmeextpriv;
+ if (adapter->fix_rx_ampdu_size != RX_AMPDU_SIZE_INVALID)
+ size = adapter->fix_rx_ampdu_size;
+ else
+ size = rtw_rx_ampdu_size(adapter);
- if (mlmeext_msr(mlmeext) == WIFI_FW_STATION_STATE) {
+ if (MLME_IS_STA(adapter)) {
sta = rtw_get_stainfo(&adapter->stapriv, get_bssid(&adapter->mlmepriv));
- if (sta)
- adj_cnt += rx_ampdu_apply_sta(adapter, sta, accept, size);
+ if (sta) {
+ u8 sta_size = size;
+
+ if (adapter->fix_rx_ampdu_size == RX_AMPDU_SIZE_INVALID)
+ sta_size = rtw_min(size, rx_ampdu_size_sta_limit(adapter, sta));
+ adj_cnt += rx_ampdu_apply_sta(adapter, sta, accept, sta_size);
+ }
+ /* TODO: TDLS peer */
- } else if (mlmeext_msr(mlmeext) == WIFI_FW_AP_STATE) {
+ } else if (MLME_IS_AP(adapter) || MLME_IS_MESH(adapter)) {
_irqL irqL;
_list *phead, *plist;
u8 peer_num = 0;
@@ -3642,11 +3996,18 @@ u16 rtw_rx_ampdu_apply(_adapter *adapter)
for (i = 0; i < peer_num; i++) {
sta = rtw_get_stainfo_by_offset(pstapriv, peers[i]);
- if (sta)
- adj_cnt += rx_ampdu_apply_sta(adapter, sta, accept, size);
+ if (sta) {
+ u8 sta_size = size;
+
+ if (adapter->fix_rx_ampdu_size == RX_AMPDU_SIZE_INVALID)
+ sta_size = rtw_min(size, rx_ampdu_size_sta_limit(adapter, sta));
+ adj_cnt += rx_ampdu_apply_sta(adapter, sta, accept, sta_size);
+ }
}
}
+ /* TODO: ADHOC */
+
return adj_cnt;
}
@@ -3662,6 +4023,7 @@ unsigned int OnAction_back(_adapter *padapter, union recv_frame *precv_frame)
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
u8 *pframe = precv_frame->u.hdr.rx_data;
struct sta_priv *pstapriv = &padapter->stapriv;
+ struct registry_priv *pregpriv = &padapter->registrypriv;
#ifdef CONFIG_80211N_HT
@@ -3681,7 +4043,7 @@ unsigned int OnAction_back(_adapter *padapter, union recv_frame *precv_frame)
if (!(pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS))
return _SUCCESS;
- addr = GetAddr2Ptr(pframe);
+ addr = get_addr2_ptr(pframe);
psta = rtw_get_stainfo(pstapriv, addr);
if (psta == NULL)
@@ -3723,8 +4085,14 @@ unsigned int OnAction_back(_adapter *padapter, union recv_frame *precv_frame)
psta->htpriv.agg_enable_bitmap |= 1 << tid;
psta->htpriv.candidate_tid_bitmap &= ~BIT(tid);
/* amsdu in ampdu */
- if (frame_body[5] & 1)
+ if (pregpriv->tx_ampdu_amsdu == 0)
+ psta->htpriv.tx_amsdu_enable = _FALSE;
+ else if (pregpriv->tx_ampdu_amsdu == 1)
psta->htpriv.tx_amsdu_enable = _TRUE;
+ else {
+ if (frame_body[5] & 1)
+ psta->htpriv.tx_amsdu_enable = _TRUE;
+ }
} else
psta->htpriv.agg_enable_bitmap &= ~BIT(tid);
@@ -3766,42 +4134,20 @@ unsigned int OnAction_back(_adapter *padapter, union recv_frame *precv_frame)
}
#ifdef CONFIG_P2P
-
-static int get_reg_classes_full_count(struct p2p_channels channel_list)
+int get_reg_classes_full_count(struct p2p_channels *channel_list)
{
int cnt = 0;
int i;
- for (i = 0; i < channel_list.reg_classes; i++)
- cnt += channel_list.reg_class[i].channels;
+ for (i = 0; i < channel_list->reg_classes; i++)
+ cnt += channel_list->reg_class[i].channels;
return cnt;
}
-static void get_channel_cnt_24g_5gl_5gh(struct mlme_ext_priv *pmlmeext, u8 *p24g_cnt, u8 *p5gl_cnt, u8 *p5gh_cnt)
-{
- int i = 0;
-
- *p24g_cnt = 0;
- *p5gl_cnt = 0;
- *p5gh_cnt = 0;
-
- for (i = 0; i < pmlmeext->max_chan_nums; i++) {
- if (pmlmeext->channel_set[i].ChannelNum <= 14)
- (*p24g_cnt)++;
- else if ((pmlmeext->channel_set[i].ChannelNum > 14) && (pmlmeext->channel_set[i].ChannelNum <= 48)) {
- /* Just include the channel 36, 40, 44, 48 channels for 5G low */
- (*p5gl_cnt)++;
- } else if ((pmlmeext->channel_set[i].ChannelNum >= 149) && (pmlmeext->channel_set[i].ChannelNum <= 161)) {
- /* Just include the channel 149, 153, 157, 161 channels for 5G high */
- (*p5gh_cnt)++;
- }
- }
-}
-
void issue_p2p_GO_request(_adapter *padapter, u8 *raddr)
{
-
+ struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list);
unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
u8 action = P2P_PUB_ACTION_ACTION;
u32 p2poui = cpu_to_be32(P2POUI);
@@ -3848,7 +4194,7 @@ void issue_p2p_GO_request(_adapter *padapter, u8 *raddr)
SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
pmlmeext->mgnt_seq++;
- SetFrameSubType(pframe, WIFI_ACTION);
+ set_frame_sub_type(pframe, WIFI_ACTION);
pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
@@ -4013,7 +4359,7 @@ void issue_p2p_GO_request(_adapter *padapter, u8 *raddr)
/* Intended P2P Interface Address */
/* Type: */
- p2pie[p2pielen++] = P2P_ATTR_INTENTED_IF_ADDR;
+ p2pie[p2pielen++] = P2P_ATTR_INTENDED_IF_ADDR;
/* Length: */
*(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN);
@@ -4033,8 +4379,8 @@ void issue_p2p_GO_request(_adapter *padapter, u8 *raddr)
/* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */
/* + number of channels in all classes */
len_channellist_attr = 3
- + (1 + 1) * (u16)(pmlmeext->channel_list.reg_classes)
- + get_reg_classes_full_count(pmlmeext->channel_list);
+ + (1 + 1) * (u16)(ch_list->reg_classes)
+ + get_reg_classes_full_count(ch_list);
#ifdef CONFIG_CONCURRENT_MODE
if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)
@@ -4079,36 +4425,22 @@ void issue_p2p_GO_request(_adapter *padapter, u8 *raddr)
/* Channel List */
p2pie[p2pielen++] = union_ch;
- } else {
- int i, j;
- for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) {
- /* Operating Class */
- p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class;
-
- /* Number of Channels */
- p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels;
-
- /* Channel List */
- for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++)
- p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i];
- }
- }
-#else /* CONFIG_CONCURRENT_MODE */
+ } else
+#endif /* CONFIG_CONCURRENT_MODE */
{
int i, j;
- for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) {
+ for (j = 0; j < ch_list->reg_classes; j++) {
/* Operating Class */
- p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class;
+ p2pie[p2pielen++] = ch_list->reg_class[j].reg_class;
/* Number of Channels */
- p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels;
+ p2pie[p2pielen++] = ch_list->reg_class[j].channels;
/* Channel List */
- for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++)
- p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i];
+ for (i = 0; i < ch_list->reg_class[j].channels; i++)
+ p2pie[p2pielen++] = ch_list->reg_class[j].channel[i];
}
}
-#endif /* CONFIG_CONCURRENT_MODE */
/* Device Info */
/* Type: */
@@ -4213,7 +4545,7 @@ void issue_p2p_GO_request(_adapter *padapter, u8 *raddr)
void issue_p2p_GO_response(_adapter *padapter, u8 *raddr, u8 *frame_body, uint len, u8 result)
{
-
+ struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list);
unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
u8 action = P2P_PUB_ACTION_ACTION;
u32 p2poui = cpu_to_be32(P2POUI);
@@ -4263,7 +4595,7 @@ void issue_p2p_GO_response(_adapter *padapter, u8 *raddr, u8 *frame_body, uint l
SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
pmlmeext->mgnt_seq++;
- SetFrameSubType(pframe, WIFI_ACTION);
+ set_frame_sub_type(pframe, WIFI_ACTION);
pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
@@ -4462,7 +4794,7 @@ void issue_p2p_GO_response(_adapter *padapter, u8 *raddr, u8 *frame_body, uint l
/* Intended P2P Interface Address */
/* Type: */
- p2pie[p2pielen++] = P2P_ATTR_INTENTED_IF_ADDR;
+ p2pie[p2pielen++] = P2P_ATTR_INTENDED_IF_ADDR;
/* Length: */
*(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN);
@@ -4480,8 +4812,8 @@ void issue_p2p_GO_response(_adapter *padapter, u8 *raddr, u8 *frame_body, uint l
/* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */
/* + number of channels in all classes */
len_channellist_attr = 3
- + (1 + 1) * (u16)pmlmeext->channel_list.reg_classes
- + get_reg_classes_full_count(pmlmeext->channel_list);
+ + (1 + 1) * (u16)ch_list->reg_classes
+ + get_reg_classes_full_count(ch_list);
#ifdef CONFIG_CONCURRENT_MODE
if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)
@@ -4526,37 +4858,22 @@ void issue_p2p_GO_response(_adapter *padapter, u8 *raddr, u8 *frame_body, uint l
/*Channel List*/
p2pie[p2pielen++] = union_chan;
- } else {
- int i, j;
- for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) {
- /* Operating Class */
- p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class;
-
- /* Number of Channels */
- p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels;
-
- /* Channel List */
- for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++)
- p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i];
- }
- }
-#else /* CONFIG_CONCURRENT_MODE */
+ } else
+#endif /* CONFIG_CONCURRENT_MODE */
{
int i, j;
- for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) {
+ for (j = 0; j < ch_list->reg_classes; j++) {
/* Operating Class */
- p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class;
+ p2pie[p2pielen++] = ch_list->reg_class[j].reg_class;
/* Number of Channels */
- p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels;
+ p2pie[p2pielen++] = ch_list->reg_class[j].channels;
/* Channel List */
- for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++)
- p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i];
+ for (i = 0; i < ch_list->reg_class[j].channels; i++)
+ p2pie[p2pielen++] = ch_list->reg_class[j].channel[i];
}
}
-#endif /* CONFIG_CONCURRENT_MODE */
-
/* Device Info */
/* Type: */
@@ -4691,7 +5008,7 @@ void issue_p2p_GO_confirm(_adapter *padapter, u8 *raddr, u8 result)
SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
pmlmeext->mgnt_seq++;
- SetFrameSubType(pframe, WIFI_ACTION);
+ set_frame_sub_type(pframe, WIFI_ACTION);
pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
@@ -4882,7 +5199,7 @@ void issue_p2p_GO_confirm(_adapter *padapter, u8 *raddr, u8 result)
void issue_p2p_invitation_request(_adapter *padapter, u8 *raddr)
{
-
+ struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list);
unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
u8 action = P2P_PUB_ACTION_ACTION;
u32 p2poui = cpu_to_be32(P2POUI);
@@ -4929,7 +5246,7 @@ void issue_p2p_invitation_request(_adapter *padapter, u8 *raddr)
SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
pmlmeext->mgnt_seq++;
- SetFrameSubType(pframe, WIFI_ACTION);
+ set_frame_sub_type(pframe, WIFI_ACTION);
pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
@@ -5036,8 +5353,8 @@ void issue_p2p_invitation_request(_adapter *padapter, u8 *raddr)
/* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */
/* + number of channels in all classes */
len_channellist_attr = 3
- + (1 + 1) * (u16)pmlmeext->channel_list.reg_classes
- + get_reg_classes_full_count(pmlmeext->channel_list);
+ + (1 + 1) * (u16)ch_list->reg_classes
+ + get_reg_classes_full_count(ch_list);
#ifdef CONFIG_CONCURRENT_MODE
if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)
@@ -5079,36 +5396,22 @@ void issue_p2p_invitation_request(_adapter *padapter, u8 *raddr)
/* Channel List */
p2pie[p2pielen++] = union_ch;
- } else {
- int i, j;
- for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) {
- /* Operating Class */
- p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class;
-
- /* Number of Channels */
- p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels;
-
- /* Channel List */
- for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++)
- p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i];
- }
- }
-#else /* CONFIG_CONCURRENT_MODE */
+ } else
+#endif /* CONFIG_CONCURRENT_MODE */
{
int i, j;
- for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) {
+ for (j = 0; j < ch_list->reg_classes; j++) {
/* Operating Class */
- p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class;
+ p2pie[p2pielen++] = ch_list->reg_class[j].reg_class;
/* Number of Channels */
- p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels;
+ p2pie[p2pielen++] = ch_list->reg_class[j].channels;
/* Channel List */
- for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++)
- p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i];
+ for (i = 0; i < ch_list->reg_class[j].channels; i++)
+ p2pie[p2pielen++] = ch_list->reg_class[j].channel[i];
}
}
-#endif /* CONFIG_CONCURRENT_MODE */
/* P2P Group ID */
@@ -5196,7 +5499,7 @@ void issue_p2p_invitation_request(_adapter *padapter, u8 *raddr)
void issue_p2p_invitation_response(_adapter *padapter, u8 *raddr, u8 dialogToken, u8 status_code)
{
-
+ struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list);
unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
u8 action = P2P_PUB_ACTION_ACTION;
u32 p2poui = cpu_to_be32(P2POUI);
@@ -5242,7 +5545,7 @@ void issue_p2p_invitation_response(_adapter *padapter, u8 *raddr, u8 dialogToken
SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
pmlmeext->mgnt_seq++;
- SetFrameSubType(pframe, WIFI_ACTION);
+ set_frame_sub_type(pframe, WIFI_ACTION);
pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
@@ -5354,8 +5657,8 @@ void issue_p2p_invitation_response(_adapter *padapter, u8 *raddr, u8 dialogToken
/* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */
/* + number of channels in all classes */
len_channellist_attr = 3
- + (1 + 1) * (u16)pmlmeext->channel_list.reg_classes
- + get_reg_classes_full_count(pmlmeext->channel_list);
+ + (1 + 1) * (u16)ch_list->reg_classes
+ + get_reg_classes_full_count(ch_list);
#ifdef CONFIG_CONCURRENT_MODE
if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)
@@ -5397,36 +5700,22 @@ void issue_p2p_invitation_response(_adapter *padapter, u8 *raddr, u8 dialogToken
/* Channel List */
p2pie[p2pielen++] = union_ch;
- } else {
- int i, j;
- for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) {
- /* Operating Class */
- p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class;
-
- /* Number of Channels */
- p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels;
-
- /* Channel List */
- for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++)
- p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i];
- }
- }
-#else /* CONFIG_CONCURRENT_MODE */
+ } else
+#endif /* CONFIG_CONCURRENT_MODE */
{
int i, j;
- for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) {
+ for (j = 0; j < ch_list->reg_classes; j++) {
/* Operating Class */
- p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class;
+ p2pie[p2pielen++] = ch_list->reg_class[j].reg_class;
/* Number of Channels */
- p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels;
+ p2pie[p2pielen++] = ch_list->reg_class[j].channels;
/* Channel List */
- for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++)
- p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i];
+ for (i = 0; i < ch_list->reg_class[j].channels; i++)
+ p2pie[p2pielen++] = ch_list->reg_class[j].channel[i];
}
}
-#endif /* CONFIG_CONCURRENT_MODE */
}
pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen);
@@ -5493,7 +5782,7 @@ void issue_p2p_provision_request(_adapter *padapter, u8 *pssid, u8 ussidlen, u8
SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
pmlmeext->mgnt_seq++;
- SetFrameSubType(pframe, WIFI_ACTION);
+ set_frame_sub_type(pframe, WIFI_ACTION);
pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
@@ -5612,6 +5901,12 @@ void issue_probersp_p2p(_adapter *padapter, unsigned char *da)
pattrib = &pmgntframe->attrib;
update_mgntframe_attrib(padapter, pattrib);
+ if (IS_CCK_RATE(pattrib->rate)) {
+ /* force OFDM 6M rate */
+ pattrib->rate = MGN_6M;
+ pattrib->raid = rtw_get_mgntframe_raid(padapter, WIRELESS_11G);
+ }
+
_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
@@ -5629,7 +5924,7 @@ void issue_probersp_p2p(_adapter *padapter, unsigned char *da)
SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
pmlmeext->mgnt_seq++;
- SetFrameSubType(fctrl, WIFI_PROBERSP);
+ set_frame_sub_type(fctrl, WIFI_PROBERSP);
pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr);
pattrib->pktlen = pattrib->hdrlen;
@@ -5932,6 +6227,11 @@ int _issue_probereq_p2p(_adapter *padapter, u8 *da, int wait_ack)
pattrib = &pmgntframe->attrib;
update_mgntframe_attrib(padapter, pattrib);
+ if (IS_CCK_RATE(pattrib->rate)) {
+ /* force OFDM 6M rate */
+ pattrib->rate = MGN_6M;
+ pattrib->raid = rtw_get_mgntframe_raid(padapter, WIRELESS_11G);
+ }
_rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
@@ -5961,7 +6261,7 @@ int _issue_probereq_p2p(_adapter *padapter, u8 *da, int wait_ack)
SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
pmlmeext->mgnt_seq++;
- SetFrameSubType(pframe, WIFI_PROBEREQ);
+ set_frame_sub_type(pframe, WIFI_PROBEREQ);
pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
@@ -6205,7 +6505,6 @@ int _issue_probereq_p2p(_adapter *padapter, u8 *da, int wait_ack)
pattrib->last_txcmdsz = pattrib->pktlen;
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("issuing probe_req, tx_len=%d\n", pattrib->last_txcmdsz));
if (wait_ack)
ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);
@@ -6232,7 +6531,7 @@ int issue_probereq_p2p_ex(_adapter *adapter, u8 *da, int try_cnt, int wait_ms)
{
int ret;
int i = 0;
- u32 start = rtw_get_current_time();
+ systime start = rtw_get_current_time();
do {
ret = _issue_probereq_p2p(adapter, da, wait_ms > 0 ? _TRUE : _FALSE);
@@ -6317,7 +6616,7 @@ unsigned int on_action_public_p2p(union recv_frame *precv_frame)
_cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey);
#ifdef CONFIG_IOCTL_CFG80211
if (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211)
- rtw_cfg80211_rx_p2p_action_public(padapter, pframe, len);
+ rtw_cfg80211_rx_p2p_action_public(padapter, precv_frame);
else
#endif /* CONFIG_IOCTL_CFG80211 */
{
@@ -6356,10 +6655,10 @@ unsigned int on_action_public_p2p(union recv_frame *precv_frame)
/* Commented by Kurt 20120113 */
/* Get peer_dev_addr here if peer doesn't issue prov_disc frame. */
if (_rtw_memcmp(pwdinfo->rx_prov_disc_info.peerDevAddr, empty_addr, ETH_ALEN))
- _rtw_memcpy(pwdinfo->rx_prov_disc_info.peerDevAddr, GetAddr2Ptr(pframe), ETH_ALEN);
+ _rtw_memcpy(pwdinfo->rx_prov_disc_info.peerDevAddr, get_addr2_ptr(pframe), ETH_ALEN);
result = process_p2p_group_negotation_req(pwdinfo, frame_body, len);
- issue_p2p_GO_response(padapter, GetAddr2Ptr(pframe), frame_body, len, result);
+ issue_p2p_GO_response(padapter, get_addr2_ptr(pframe), frame_body, len, result);
#ifdef CONFIG_INTEL_WIDI
if (padapter->mlmepriv.widi_state == INTEL_WIDI_STATE_LISTEN) {
padapter->mlmepriv.widi_state = INTEL_WIDI_STATE_WFD_CONNECTION;
@@ -6387,7 +6686,7 @@ unsigned int on_action_public_p2p(union recv_frame *precv_frame)
_cancel_timer_ex(&pwdinfo->restore_p2p_state_timer);
pwdinfo->nego_req_info.benable = _FALSE;
result = process_p2p_group_negotation_resp(pwdinfo, frame_body, len);
- issue_p2p_GO_confirm(pwdinfo->padapter, GetAddr2Ptr(pframe), result);
+ issue_p2p_GO_confirm(pwdinfo->padapter, get_addr2_ptr(pframe), result);
if (P2P_STATUS_SUCCESS == result) {
if (rtw_p2p_role(pwdinfo) == P2P_ROLE_CLIENT) {
pwdinfo->p2p_info.operation_ch[0] = pwdinfo->peer_operating_ch;
@@ -6488,7 +6787,7 @@ unsigned int on_action_public_p2p(union recv_frame *precv_frame)
u8 operatingch_info[5] = { 0x00 };
if (rtw_get_p2p_attr_content(merged_p2pie, merged_p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info,
&attr_contentlen)) {
- if (rtw_ch_set_search_ch(padapter->mlmeextpriv.channel_set, (u32)operatingch_info[4]) >= 0) {
+ if (rtw_chset_search_ch(adapter_to_chset(padapter), (u32)operatingch_info[4]) >= 0) {
/* The operating channel is acceptable for this device. */
pwdinfo->rx_invitereq_info.operation_ch[0] = operatingch_info[4];
#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH
@@ -6565,7 +6864,7 @@ unsigned int on_action_public_p2p(union recv_frame *precv_frame)
RTW_INFO("[%s] status_code = %d\n", __FUNCTION__, status_code);
pwdinfo->inviteresp_info.token = frame_body[7];
- issue_p2p_invitation_response(padapter, GetAddr2Ptr(pframe), pwdinfo->inviteresp_info.token, status_code);
+ issue_p2p_invitation_response(padapter, get_addr2_ptr(pframe), pwdinfo->inviteresp_info.token, status_code);
_set_timer(&pwdinfo->restore_p2p_state_timer, 3000);
}
#ifdef CONFIG_INTEL_WIDI
@@ -6630,7 +6929,7 @@ unsigned int on_action_public_p2p(union recv_frame *precv_frame)
case P2P_PROVISION_DISC_REQ:
RTW_INFO("[%s] Got Provisioning Discovery Request Frame\n", __FUNCTION__);
process_p2p_provdisc_req(pwdinfo, pframe, len);
- _rtw_memcpy(pwdinfo->rx_prov_disc_info.peerDevAddr, GetAddr2Ptr(pframe), ETH_ALEN);
+ _rtw_memcpy(pwdinfo->rx_prov_disc_info.peerDevAddr, get_addr2_ptr(pframe), ETH_ALEN);
/* 20110902 Kurt */
/* Add the following statement to avoid receiving duplicate prov disc req. such that pre_p2p_state would be covered. */
@@ -6711,7 +7010,7 @@ unsigned int on_action_public_default(union recv_frame *precv_frame, u8 action)
#ifdef CONFIG_IOCTL_CFG80211
cnt += sprintf((msg + cnt), "%s(token:%u)", action_public_str(action), token);
- rtw_cfg80211_rx_action(adapter, pframe, frame_len, msg);
+ rtw_cfg80211_rx_action(adapter, precv_frame, msg);
#endif
ret = _SUCCESS;
@@ -6759,6 +7058,566 @@ unsigned int on_action_public(_adapter *padapter, union recv_frame *precv_frame)
return ret;
}
+#if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K)
+static u8 rtw_wnm_nb_elem_parsing(
+ u8* pdata, u32 data_len, u8 from_btm,
+ u32 *nb_rpt_num, u8 *nb_rpt_is_same,
+ struct roam_nb_info *pnb, struct wnm_btm_cant *pcandidates)
+{
+ u8 bfound = _FALSE, ret = _SUCCESS;
+ u8 *ptr, *pend, *op;
+ u32 elem_len, subelem_len, op_len;
+ u32 i, nb_rpt_entries = 0;
+ struct nb_rpt_hdr *pie;
+ struct wnm_btm_cant *pcandidate;
+
+ if ((!pdata) || (!pnb))
+ return _FAIL;
+
+ if ((from_btm) && (!pcandidates))
+ return _FAIL;
+
+ ptr = pdata;
+ pend = ptr + data_len;
+ elem_len = data_len;
+ subelem_len = (u32)*(pdata+1);
+
+ for (i=0; i < RTW_MAX_NB_RPT_NUM; i++) {
+ if (((ptr + 7) > pend) || (elem_len < subelem_len))
+ break;
+
+ if (*ptr != 0x34) {
+ RTW_ERR("WNM: invalid data(0x%2x)!\n", *ptr);
+ ret = _FAIL;
+ break;
+ }
+
+ pie = (struct nb_rpt_hdr *)ptr;
+ if (from_btm) {
+ op = rtw_get_ie((u8 *)(ptr+15),
+ WNM_BTM_CAND_PREF_SUBEID,
+ &op_len, (subelem_len - 15));
+ }
+
+ ptr = (u8 *)(ptr + subelem_len + 2);
+ elem_len -= (subelem_len +2);
+ subelem_len = *(ptr+1);
+ if (from_btm) {
+ pcandidate = (pcandidates + i);
+ _rtw_memcpy(&pcandidate->nb_rpt, pie, sizeof(struct nb_rpt_hdr));
+ if (op && (op_len !=0)) {
+ pcandidate->preference = *(op + 2);
+ bfound = _TRUE;
+ } else
+ pcandidate->preference = 0;
+
+ RTW_DBG("WNM: preference check bssid("MAC_FMT
+ ") ,bss_info(0x%04X), reg_class(0x%02X), ch(%d),"
+ " phy_type(0x%02X), preference(0x%02X)\n",
+ MAC_ARG(pcandidate->nb_rpt.bssid), pcandidate->nb_rpt.bss_info,
+ pcandidate->nb_rpt.reg_class, pcandidate->nb_rpt.ch_num,
+ pcandidate->nb_rpt.phy_type, pcandidate->preference);
+ } else {
+ if (_rtw_memcmp(&pnb->nb_rpt[i], pie, sizeof(struct nb_rpt_hdr)) == _FALSE)
+ *nb_rpt_is_same = _FALSE;
+ _rtw_memcpy(&pnb->nb_rpt[i], pie, sizeof(struct nb_rpt_hdr));
+ }
+ nb_rpt_entries++;
+ }
+
+ if (from_btm)
+ pnb->preference_en = (bfound)?_TRUE:_FALSE;
+
+ *nb_rpt_num = nb_rpt_entries;
+ return ret;
+}
+
+/* selection sorting based on preference value
+ * IN : nb_rpt_entries - candidate num
+ * IN/OUT : pcandidates - candidate list
+ * return : TRUE - means pcandidates is updated.
+ */
+static u8 rtw_wnm_candidates_sorting(
+ u32 nb_rpt_entries, struct wnm_btm_cant *pcandidates)
+{
+ u8 updated = _FALSE;
+ u32 i, j, pos;
+ struct wnm_btm_cant swap;
+ struct wnm_btm_cant *pcant_1, *pcant_2;
+
+ if ((!nb_rpt_entries) || (!pcandidates))
+ return updated;
+
+ for (i=0; i < (nb_rpt_entries - 1); i++) {
+ pos = i;
+ for (j=(i + 1); j < nb_rpt_entries; j++) {
+ pcant_1 = pcandidates+pos;
+ pcant_2 = pcandidates+j;
+ if ((pcant_1->preference) < (pcant_2->preference))
+ pos = j;
+ }
+
+ if (pos != i) {
+ updated = _TRUE;
+ _rtw_memcpy(&swap, (pcandidates+i), sizeof(struct wnm_btm_cant));
+ _rtw_memcpy((pcandidates+i), (pcandidates+pos), sizeof(struct wnm_btm_cant));
+ _rtw_memcpy((pcandidates+pos), &swap, sizeof(struct wnm_btm_cant));
+ }
+ }
+ return updated;
+}
+
+static void rtw_wnm_nb_info_update(
+ u32 nb_rpt_entries, u8 from_btm,
+ struct roam_nb_info *pnb, struct wnm_btm_cant *pcandidates,
+ u8 *nb_rpt_is_same)
+{
+ u8 is_found;
+ u32 i, j;
+ struct wnm_btm_cant *pcand;
+
+ if (!pnb)
+ return;
+
+ pnb->nb_rpt_ch_list_num = 0;
+ for (i=0; inb_rpt[i], &pcand->nb_rpt,
+ sizeof(struct nb_rpt_hdr)) == _FALSE)
+ *nb_rpt_is_same = _FALSE;
+ _rtw_memcpy(&pnb->nb_rpt[i], &pcand->nb_rpt, sizeof(struct nb_rpt_hdr));
+ }
+
+ RTW_DBG("WNM: bssid(" MAC_FMT
+ ") , bss_info(0x%04X), reg_class(0x%02X), ch_num(%d), phy_type(0x%02X)\n",
+ MAC_ARG(pnb->nb_rpt[i].bssid), pnb->nb_rpt[i].bss_info,
+ pnb->nb_rpt[i].reg_class, pnb->nb_rpt[i].ch_num,
+ pnb->nb_rpt[i].phy_type);
+
+ if (pnb->nb_rpt[i].ch_num == 0)
+ continue;
+
+ for (j=0; jnb_rpt[i].ch_num == pnb->nb_rpt_ch_list[j].hw_value) {
+ is_found = _TRUE;
+ break;
+ }
+ }
+
+ if (!is_found) {
+ pnb->nb_rpt_ch_list[pnb->nb_rpt_ch_list_num].hw_value = pnb->nb_rpt[i].ch_num;
+ pnb->nb_rpt_ch_list_num++;
+ }
+ }
+}
+
+static void rtw_wnm_btm_candidate_select(_adapter *padapter)
+{
+ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+ struct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info);
+ struct wlan_network *pnetwork;
+ u8 bfound = _FALSE;
+ u32 i;
+
+ for (i = 0; i < pnb->last_nb_rpt_entries; i++) {
+ pnetwork = rtw_find_network(
+ &(pmlmepriv->scanned_queue),
+ pnb->nb_rpt[i].bssid);
+
+ if (pnetwork) {
+ bfound = _TRUE;
+ break;
+ }
+ }
+
+ if (bfound) {
+ _rtw_memcpy(pnb->roam_target_addr, pnb->nb_rpt[i].bssid, ETH_ALEN);
+ RTW_INFO("WNM : select btm entry(%d) - %s("MAC_FMT", ch%u) rssi:%d\n"
+ , i
+ , pnetwork->network.Ssid.Ssid
+ , MAC_ARG(pnetwork->network.MacAddress)
+ , pnetwork->network.Configuration.DSConfig
+ , (int)pnetwork->network.Rssi);
+ } else
+ _rtw_memset(pnb->roam_target_addr,0, ETH_ALEN);
+}
+
+u32 rtw_wnm_btm_candidates_survey(
+ _adapter *padapter, u8* pframe, u32 elem_len, u8 from_btm)
+{
+ struct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info);
+ struct wnm_btm_cant *pcandidate_list = NULL;
+ u8 nb_rpt_is_same = _TRUE;
+ u32 ret = _FAIL;
+ u32 nb_rpt_entries = 0;
+
+ if (from_btm) {
+ u32 mlen = sizeof(struct wnm_btm_cant) * RTW_MAX_NB_RPT_NUM;
+ pcandidate_list = (struct wnm_btm_cant *)rtw_malloc(mlen);
+ if (pcandidate_list == NULL)
+ goto exit;
+ }
+
+ /*clean the status set last time*/
+ _rtw_memset(&pnb->nb_rpt_ch_list, 0, sizeof(pnb->nb_rpt_ch_list));
+ pnb->nb_rpt_valid = _FALSE;
+ if (!rtw_wnm_nb_elem_parsing(
+ pframe, elem_len, from_btm,
+ &nb_rpt_entries, &nb_rpt_is_same,
+ pnb, pcandidate_list))
+ goto exit;
+
+ if (nb_rpt_entries != 0) {
+ if ((from_btm) && (rtw_wnm_btm_preference_cap(padapter)))
+ rtw_wnm_candidates_sorting(nb_rpt_entries, pcandidate_list);
+
+ rtw_wnm_nb_info_update(
+ nb_rpt_entries, from_btm,
+ pnb, pcandidate_list, &nb_rpt_is_same);
+ }
+
+ RTW_INFO("nb_rpt_is_same = %d, nb_rpt_entries = %d, last_nb_rpt_entries = %d\n",
+ nb_rpt_is_same, nb_rpt_entries, pnb->last_nb_rpt_entries);
+ if ((nb_rpt_is_same == _TRUE) && (nb_rpt_entries == pnb->last_nb_rpt_entries))
+ pnb->nb_rpt_is_same = _TRUE;
+ else {
+ pnb->nb_rpt_is_same = _FALSE;
+ pnb->last_nb_rpt_entries = nb_rpt_entries;
+ }
+
+ if ((from_btm) && (nb_rpt_entries != 0))
+ rtw_wnm_btm_candidate_select(padapter);
+
+ pnb->nb_rpt_valid = _TRUE;
+ ret = _SUCCESS;
+
+exit:
+ if (from_btm && pcandidate_list)
+ rtw_mfree((u8 *)pcandidate_list, sizeof(struct wnm_btm_cant) * RTW_MAX_NB_RPT_NUM);
+
+ return ret;
+}
+#endif
+
+unsigned int OnAction_ft(_adapter *padapter, union recv_frame *precv_frame)
+{
+#ifdef CONFIG_RTW_80211R
+ u32 ret = _FAIL;
+ u32 frame_len = 0;
+ u8 action_code = 0;
+ u8 category = 0;
+ u8 *pframe = NULL;
+ u8 *pframe_body = NULL;
+ u8 sta_addr[ETH_ALEN] = {0};
+ u8 *pie = NULL;
+ u32 ft_ie_len = 0;
+ u32 status_code = 0;
+ struct mlme_ext_priv *pmlmeext = NULL;
+ struct mlme_ext_info *pmlmeinfo = NULL;
+ struct mlme_priv *pmlmepriv = NULL;
+ struct wlan_network *proam_target = NULL;
+ struct ft_roam_info *pft_roam = NULL;
+ _irqL irqL;
+
+ pmlmeext = &(padapter->mlmeextpriv);
+ pmlmeinfo = &(pmlmeext->mlmext_info);
+ pmlmepriv = &(padapter->mlmepriv);
+ pft_roam = &(pmlmepriv->ft_roam);
+ pframe = precv_frame->u.hdr.rx_data;
+ frame_len = precv_frame->u.hdr.len;
+ pframe_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
+ category = pframe_body[0];
+
+ if (category != RTW_WLAN_CATEGORY_FT)
+ goto exit;
+
+ action_code = pframe_body[1];
+ switch (action_code) {
+ case RTW_WLAN_ACTION_FT_RSP:
+ RTW_INFO("FT: RTW_WLAN_ACTION_FT_RSP recv.\n");
+ if (!_rtw_memcmp(adapter_mac_addr(padapter), &pframe_body[2], ETH_ALEN)) {
+ RTW_ERR("FT: Unmatched STA MAC Address "MAC_FMT"\n", MAC_ARG(&pframe_body[2]));
+ goto exit;
+ }
+
+ status_code = le16_to_cpu(*(u16 *)((SIZE_PTR)pframe + sizeof(struct rtw_ieee80211_hdr_3addr) + 14));
+ if (status_code != 0) {
+ RTW_ERR("FT: WLAN ACTION FT RESPONSE fail, status: %d\n", status_code);
+ goto exit;
+ }
+
+ if (is_zero_mac_addr(&pframe_body[8]) || is_broadcast_mac_addr(&pframe_body[8])) {
+ RTW_ERR("FT: Invalid Target MAC Address "MAC_FMT"\n", MAC_ARG(padapter->mlmepriv.roam_tgt_addr));
+ goto exit;
+ }
+
+ pie = rtw_get_ie(pframe_body, _MDIE_, &ft_ie_len, frame_len);
+ if (pie) {
+ if (!_rtw_memcmp(&pft_roam->mdid, pie+2, 2)) {
+ RTW_ERR("FT: Invalid MDID\n");
+ goto exit;
+ }
+ }
+
+ rtw_ft_set_status(padapter, RTW_FT_REQUESTED_STA);
+ _cancel_timer_ex(&pmlmeext->ft_link_timer);
+
+ /*Disconnect current AP*/
+ receive_disconnect(padapter, pmlmepriv->cur_network.network.MacAddress, WLAN_REASON_ACTIVE_ROAM, _FALSE);
+
+ pft_roam->ft_action_len = frame_len;
+ _rtw_memcpy(pft_roam->ft_action, pframe, rtw_min(frame_len, RTW_FT_MAX_IE_SZ));
+ ret = _SUCCESS;
+ break;
+ case RTW_WLAN_ACTION_FT_REQ:
+ case RTW_WLAN_ACTION_FT_CONF:
+ case RTW_WLAN_ACTION_FT_ACK:
+ default:
+ RTW_ERR("FT: Unsupported FT Action!\n");
+ break;
+ }
+
+exit:
+ return ret;
+#else
+ return _SUCCESS;
+#endif
+}
+
+#ifdef CONFIG_RTW_WNM
+u8 rtw_wmn_btm_rsp_reason_decision(_adapter *padapter, u8* req_mode)
+{
+ struct recv_priv *precvpriv = &padapter->recvpriv;
+ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+ u8 reason = 0;
+
+ if (!rtw_wnm_btm_diff_bss(padapter)) {
+ /* Reject - No suitable BSS transition candidates */
+ reason = 7;
+ goto candidate_remove;
+ }
+
+#ifdef CONFIG_RTW_80211R
+ if (rtw_ft_chk_flags(padapter, RTW_FT_BTM_ROAM)) {
+ /* Accept */
+ reason = 0;
+ goto under_survey;
+ }
+#endif
+
+ if (((*req_mode) & DISASSOC_IMMINENT) == 0) {
+ /* Reject - Unspecified reject reason */
+ reason = 1;
+ goto candidate_remove;
+ }
+
+ if (precvpriv->signal_strength_data.avg_val >= pmlmepriv->roam_rssi_threshold) {
+ reason = 1;
+ goto candidate_remove;
+ }
+
+under_survey:
+ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)) {
+ RTW_INFO("%s reject due to _FW_UNDER_SURVEY\n", __func__);
+ reason = 1;
+ }
+
+candidate_remove:
+ if (reason !=0)
+ rtw_wnm_reset_btm_candidate(&padapter->mlmepriv.nb_info);
+
+ return reason;
+}
+
+static u32 rtw_wnm_btm_candidates_offset_get(u8* pframe)
+{
+ u8 *pos = pframe;
+ u32 offset = 0;
+
+ if (!pframe)
+ return 0;
+
+ offset += 7;
+ pos += offset;
+
+ /* BSS Termination Duration check */
+ if (wnm_btm_bss_term_inc(pframe)) {
+ offset += 12;
+ pos += offset;
+ }
+
+ /* Session Information URL check*/
+ if (wnm_btm_ess_disassoc_im(pframe)) {
+ /*URL length field + URL variable length*/
+ offset = 1 + *(pframe + offset);
+ pos += offset;
+ }
+
+ offset = (pos - pframe);
+ return offset;
+}
+
+static void rtw_wnm_btm_req_hdr_parsing(u8* pframe, struct btm_req_hdr *phdr)
+{
+ u8 *pos = pframe;
+ u32 offset = 0;
+
+ if (!pframe || !phdr)
+ return;
+
+ _rtw_memset(phdr, 0, sizeof(struct btm_req_hdr));
+ phdr->req_mode = wnm_btm_req_mode(pframe);
+ phdr->disassoc_timer = wnm_btm_disassoc_timer(pframe);
+ phdr->validity_interval = wnm_btm_valid_interval(pframe);
+ if (wnm_btm_bss_term_inc(pframe)) {
+ _rtw_memcpy(&phdr->term_duration,
+ wnm_btm_term_duration_offset(pframe),
+ sizeof(struct btm_term_duration));
+ }
+
+ RTW_DBG("WNM: req_mode(%1x), disassoc_timer(%02x), interval(%x)\n",
+ phdr->req_mode, phdr->disassoc_timer, phdr->validity_interval);
+ if (wnm_btm_bss_term_inc(pframe))
+ RTW_INFO("WNM: tsf(%llx), duration(%2x)\n",
+ phdr->term_duration.tsf, phdr->term_duration.duration);
+}
+
+void rtw_wnm_roam_scan_hdl(void *ctx)
+{
+ _adapter *padapter = (_adapter *)ctx;
+ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+
+ if (rtw_is_scan_deny(padapter))
+ RTW_INFO("WNM: roam scan would abort by scan_deny!\n");
+
+ pmlmepriv->need_to_roam = _TRUE;
+ rtw_drv_scan_by_self(padapter, RTW_AUTO_SCAN_REASON_ROAM);
+}
+
+static void rtw_wnm_roam_scan(_adapter *padapter)
+{
+ struct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info);
+
+ if (rtw_is_scan_deny(padapter)) {
+ _cancel_timer_ex(&pnb->roam_scan_timer);
+ _set_timer(&pnb->roam_scan_timer, 1000);
+ } else
+ rtw_wnm_roam_scan_hdl((void *)padapter);
+}
+
+void rtw_wnm_process_btm_req(_adapter *padapter, u8* pframe, u32 frame_len)
+{
+ struct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info);
+ struct btm_req_hdr req_hdr;
+ u8 *ptr, reason;
+ u32 elem_len, offset;
+
+ rtw_wnm_btm_req_hdr_parsing(pframe, &req_hdr);
+ offset = rtw_wnm_btm_candidates_offset_get(pframe);
+ if ((offset == 0) || ((frame_len - offset) <= 15))
+ return;
+
+ ptr = (pframe + offset);
+ elem_len = (frame_len - offset);
+ rtw_wnm_btm_candidates_survey(padapter, ptr, elem_len, _TRUE);
+ reason = rtw_wmn_btm_rsp_reason_decision(padapter, &pframe[3]);
+ rtw_wnm_issue_action(padapter,
+ RTW_WLAN_ACTION_WNM_BTM_RSP, reason);
+
+ if (reason == 0)
+ rtw_wnm_roam_scan(padapter);
+}
+
+void rtw_wnm_reset_btm_candidate(struct roam_nb_info *pnb)
+{
+ pnb->preference_en = _FALSE;
+ _rtw_memset(pnb->roam_target_addr, 0, ETH_ALEN);
+}
+
+void rtw_wnm_reset_btm_state(_adapter *padapter)
+{
+ struct roam_nb_info *pnb = &(padapter->mlmepriv.nb_info);
+
+ pnb->last_nb_rpt_entries = 0;
+ pnb->nb_rpt_is_same = _TRUE;
+ pnb->nb_rpt_valid = _FALSE;
+ pnb->nb_rpt_ch_list_num = 0;
+ rtw_wnm_reset_btm_candidate(pnb);
+ _rtw_memset(&pnb->nb_rpt, 0, sizeof(pnb->nb_rpt));
+ _rtw_memset(&pnb->nb_rpt_ch_list, 0, sizeof(pnb->nb_rpt_ch_list));
+}
+
+void rtw_wnm_issue_action(_adapter *padapter, u8 action, u8 reason)
+{
+ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
+ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
+ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+ struct xmit_frame *pmgntframe;
+ struct rtw_ieee80211_hdr *pwlanhdr;
+ struct pkt_attrib *pattrib;
+ u8 category, dialog_token, termination_delay, *pframe;
+ u16 *fctrl;
+
+ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL)
+ return ;
+
+ pattrib = &(pmgntframe->attrib);
+ update_mgntframe_attrib(padapter, pattrib);
+ _rtw_memset(pmgntframe->buf_addr, 0, (WLANHDR_OFFSET + TXDESC_OFFSET));
+
+ pframe = (u8 *)(pmgntframe->buf_addr + TXDESC_OFFSET);
+ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+ fctrl = &(pwlanhdr->frame_ctl);
+ *(fctrl) = 0;
+
+ _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
+ _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
+
+ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
+ pmlmeext->mgnt_seq++;
+ set_frame_sub_type(pframe, WIFI_ACTION);
+
+ pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
+ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+ category = RTW_WLAN_CATEGORY_WNM;
+ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
+ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
+
+ switch (action) {
+ case RTW_WLAN_ACTION_WNM_BTM_QUERY:
+ pframe = rtw_set_fixed_ie(pframe, 1, &(dialog_token), &(pattrib->pktlen));
+ pframe = rtw_set_fixed_ie(pframe, 1, &(reason), &(pattrib->pktlen));
+ RTW_INFO("WNM: RTW_WLAN_ACTION_WNM_BTM_QUERY sent.\n");
+ break;
+ case RTW_WLAN_ACTION_WNM_BTM_RSP:
+ termination_delay = 0;
+ pframe = rtw_set_fixed_ie(pframe, 1, &(dialog_token), &(pattrib->pktlen));
+ pframe = rtw_set_fixed_ie(pframe, 1, &(reason), &(pattrib->pktlen));
+ pframe = rtw_set_fixed_ie(pframe, 1, &(termination_delay), &(pattrib->pktlen));
+ if (!is_zero_mac_addr(pmlmepriv->nb_info.roam_target_addr)) {
+ pframe = rtw_set_fixed_ie(pframe, 6,
+ pmlmepriv->nb_info.roam_target_addr, &(pattrib->pktlen));
+ }
+ RTW_INFO("WNM: RTW_WLAN_ACTION_WNM_BTM_RSP sent. reason = %d\n", reason);
+ break;
+ default:
+ goto exit;
+ }
+
+ pattrib->last_txcmdsz = pattrib->pktlen;
+ dump_mgntframe(padapter, pmgntframe);
+
+exit:
+ return;
+}
+#endif
+
unsigned int OnAction_ht(_adapter *padapter, union recv_frame *precv_frame)
{
u8 *pframe = precv_frame->u.hdr.rx_data;
@@ -6780,14 +7639,14 @@ unsigned int OnAction_ht(_adapter *padapter, union recv_frame *precv_frame)
#ifdef CONFIG_80211N_HT
#ifdef CONFIG_AP_MODE
if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE)
- rtw_process_ht_action_smps(padapter, GetAddr2Ptr(pframe), frame_body[2]);
+ rtw_process_ht_action_smps(padapter, get_addr2_ptr(pframe), frame_body[2]);
#endif /*CONFIG_AP_MODE*/
#endif /*CONFIG_80211N_HT*/
break;
case RTW_WLAN_ACTION_HT_COMPRESS_BEAMFORMING:
#ifdef CONFIG_BEAMFORMING
/*RTW_INFO("RTW_WLAN_ACTION_HT_COMPRESS_BEAMFORMING\n");*/
- beamforming_get_report_frame(padapter, precv_frame);
+ rtw_beamforming_get_report_frame(padapter, precv_frame);
#endif /*CONFIG_BEAMFORMING*/
break;
default:
@@ -6818,11 +7677,11 @@ unsigned int OnAction_sa_query(_adapter *padapter, union recv_frame *precv_frame
_rtw_memcpy(&tid, &pframe[WLAN_HDR_A3_LEN + 2], sizeof(u16));
RTW_INFO("OnAction_sa_query request,action=%d, tid=%04x, pframe=%02x-%02x\n"
, pframe[WLAN_HDR_A3_LEN + 1], tid, pframe[WLAN_HDR_A3_LEN + 2], pframe[WLAN_HDR_A3_LEN + 3]);
- issue_action_SA_Query(padapter, GetAddr2Ptr(pframe), 1, tid, IEEE80211W_RIGHT_KEY);
+ issue_action_SA_Query(padapter, get_addr2_ptr(pframe), 1, tid, IEEE80211W_RIGHT_KEY);
break;
case 1: /* SA Query rsp */
- psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe));
+ psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
if (psta != NULL)
_cancel_timer_ex(&psta->dot11w_expire_timer);
@@ -6844,6 +7703,15 @@ unsigned int OnAction_sa_query(_adapter *padapter, union recv_frame *precv_frame
}
#endif /* CONFIG_IEEE80211W */
+unsigned int on_action_rm(_adapter *padapter, union recv_frame *precv_frame)
+{
+#ifdef CONFIG_RTW_80211K
+ return rm_on_action(padapter, precv_frame);
+#else
+ return _SUCCESS;
+#endif /* CONFIG_RTW_80211K */
+}
+
unsigned int OnAction_wmm(_adapter *padapter, union recv_frame *precv_frame)
{
return _SUCCESS;
@@ -6873,7 +7741,7 @@ unsigned int OnAction_vht(_adapter *padapter, union recv_frame *precv_frame)
case RTW_WLAN_ACTION_VHT_COMPRESSED_BEAMFORMING:
#ifdef CONFIG_BEAMFORMING
/*RTW_INFO("RTW_WLAN_ACTION_VHT_COMPRESSED_BEAMFORMING\n");*/
- beamforming_get_report_frame(padapter, precv_frame);
+ rtw_beamforming_get_report_frame(padapter, precv_frame);
#endif /*CONFIG_BEAMFORMING*/
break;
case RTW_WLAN_ACTION_VHT_OPMODE_NOTIFICATION:
@@ -6885,7 +7753,9 @@ unsigned int OnAction_vht(_adapter *padapter, union recv_frame *precv_frame)
break;
case RTW_WLAN_ACTION_VHT_GROUPID_MANAGEMENT:
#ifdef CONFIG_BEAMFORMING
- beamforming_get_vht_gid_mgnt_frame(padapter, precv_frame);
+#ifdef RTW_BEAMFORMING_VERSION_2
+ rtw_beamforming_get_vht_gid_mgnt_frame(padapter, precv_frame);
+#endif /* RTW_BEAMFORMING_VERSION_2 */
#endif /* CONFIG_BEAMFORMING */
break;
default:
@@ -6922,9 +7792,9 @@ unsigned int OnAction_p2p(_adapter *padapter, union recv_frame *precv_frame)
#ifdef CONFIG_IOCTL_CFG80211
if (adapter_wdev_data(padapter)->p2p_enabled
- && pwdinfo->driver_interface == DRIVER_CFG80211
- ) {
- rtw_cfg80211_rx_action_p2p(padapter, pframe, len);
+ && pwdinfo->driver_interface == DRIVER_CFG80211
+ ) {
+ rtw_cfg80211_rx_action_p2p(padapter, precv_frame);
return _SUCCESS;
} else
#endif /* CONFIG_IOCTL_CFG80211 */
@@ -6990,7 +7860,7 @@ unsigned int OnAction(_adapter *padapter, union recv_frame *precv_frame)
unsigned int DoReserved(_adapter *padapter, union recv_frame *precv_frame)
{
- /* RTW_INFO("rcvd mgt frame(%x, %x)\n", (GetFrameSubType(pframe) >> 4), *(unsigned int *)GetAddr1Ptr(pframe)); */
+ /* RTW_INFO("rcvd mgt frame(%x, %x)\n", (get_frame_sub_type(pframe) >> 4), *(unsigned int *)GetAddr1Ptr(pframe)); */
return _SUCCESS;
}
@@ -7061,21 +7931,13 @@ void update_monitor_frame_attrib(_adapter *padapter, struct pkt_attrib *pattrib)
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
struct sta_info *psta = NULL;
struct sta_priv *pstapriv = &padapter->stapriv;
- struct sta_info *pbcmc_sta = NULL;
psta = rtw_get_stainfo(pstapriv, pattrib->ra);
- pbcmc_sta = rtw_get_bcmc_stainfo(padapter);
pattrib->hdrlen = 24;
pattrib->nr_frags = 1;
pattrib->priority = 7;
-
- if (pbcmc_sta)
- pattrib->mac_id = pbcmc_sta->mac_id;
- else {
- pattrib->mac_id = 0;
- RTW_INFO("mgmt use mac_id 0 will affect RA\n");
- }
+ pattrib->mac_id = RTW_DEFAULT_MGMT_MACID;
pattrib->qsel = QSLT_MGNT;
pattrib->pktlen = 0;
@@ -7127,25 +7989,12 @@ void update_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib)
u8 wireless_mode;
struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
- struct sta_info *psta = NULL;
- struct sta_priv *pstapriv = &padapter->stapriv;
- struct sta_info *pbcmc_sta = NULL;
/* _rtw_memset((u8 *)(pattrib), 0, sizeof(struct pkt_attrib)); */
- pbcmc_sta = rtw_get_bcmc_stainfo(padapter);
-
pattrib->hdrlen = 24;
pattrib->nr_frags = 1;
pattrib->priority = 7;
-
- if (pbcmc_sta)
- pattrib->mac_id = pbcmc_sta->mac_id;
- else {
- pattrib->mac_id = 1; /* use STA's BCMC sta-info macid */
-
- if (MLME_IS_AP(padapter) || MLME_IS_GO(padapter))
- RTW_INFO("%s-"ADPT_FMT" get bcmc sta_info fail,use MACID=1\n", __func__, ADPT_ARG(padapter));
- }
+ pattrib->mac_id = RTW_DEFAULT_MGMT_MACID;
pattrib->qsel = QSLT_MGNT;
#ifdef CONFIG_MCC_MODE
@@ -7154,7 +8003,7 @@ void update_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib)
pattrib->pktlen = 0;
- if (pmlmeext->tx_rate == IEEE80211_CCK_RATE_1MB)
+ if (IS_CCK_RATE(pmlmeext->tx_rate))
wireless_mode = WIRELESS_11B;
else
wireless_mode = WIRELESS_11G;
@@ -7176,24 +8025,32 @@ void update_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib)
pattrib->mbssid = 0;
pattrib->hw_ssn_sel = pxmitpriv->hw_ssn_seq_no;
-
-#ifdef CONFIG_BEAMFORMING
- psta = rtw_get_stainfo(pstapriv, pattrib->ra);
- if (psta)
- update_attrib_txbf_info(padapter, pattrib, psta);
-#endif
-
}
void update_mgntframe_attrib_addr(_adapter *padapter, struct xmit_frame *pmgntframe)
{
u8 *pframe;
struct pkt_attrib *pattrib = &pmgntframe->attrib;
+#if defined(CONFIG_BEAMFORMING) || defined(CONFIG_ANTENNA_DIVERSITY)
+ struct sta_info *sta = NULL;
+#endif
pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
_rtw_memcpy(pattrib->ra, GetAddr1Ptr(pframe), ETH_ALEN);
- _rtw_memcpy(pattrib->ta, GetAddr2Ptr(pframe), ETH_ALEN);
+ _rtw_memcpy(pattrib->ta, get_addr2_ptr(pframe), ETH_ALEN);
+
+#if defined(CONFIG_BEAMFORMING) || defined(CONFIG_ANTENNA_DIVERSITY)
+ sta = pattrib->psta;
+ if (!sta) {
+ sta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
+ pattrib->psta = sta;
+ }
+ #ifdef CONFIG_BEAMFORMING
+ if (sta)
+ update_attrib_txbf_info(padapter, pattrib, sta);
+ #endif
+#endif /* defined(CONFIG_BEAMFORMING) || defined(CONFIG_ANTENNA_DIVERSITY) */
}
void dump_mgntframe(_adapter *padapter, struct xmit_frame *pmgntframe)
@@ -7254,13 +8111,8 @@ s32 dump_mgntframe_and_wait_ack_timeout(_adapter *padapter, struct xmit_frame *p
pxmitpriv->seq_no = seq_no++;
pmgntframe->ack_report = 1;
rtw_sctx_init(&(pxmitpriv->ack_tx_ops), timeout_ms);
- if (rtw_hal_mgnt_xmit(padapter, pmgntframe) == _SUCCESS) {
-#ifdef CONFIG_XMIT_ACK_POLLING
- ret = rtw_ack_tx_polling(pxmitpriv, timeout_ms);
-#else
+ if (rtw_hal_mgnt_xmit(padapter, pmgntframe) == _SUCCESS)
ret = rtw_sctx_wait(&(pxmitpriv->ack_tx_ops), __func__);
-#endif
- }
pxmitpriv->ack_tx = _FALSE;
_exit_critical_mutex(&pxmitpriv->ack_tx_mutex, NULL);
@@ -7398,12 +8250,12 @@ void issue_beacon(_adapter *padapter, int timeout_ms)
SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/);
/* pmlmeext->mgnt_seq++; */
- SetFrameSubType(pframe, WIFI_BEACON);
+ set_frame_sub_type(pframe, WIFI_BEACON);
pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
- if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {
+ if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {
/* RTW_INFO("ie len=%d\n", cur_network->IELength); */
#ifdef CONFIG_P2P
/* for P2P : Primary Device Type & Device Name */
@@ -7527,6 +8379,12 @@ void issue_beacon(_adapter *padapter, int timeout_ms)
_clr_fwstate_(pmlmepriv, WIFI_UNDER_WPS);
}
+#ifdef CONFIG_RTW_80211K
+ pframe = rtw_set_ie(pframe, _EID_RRM_EN_CAP_IE_,
+ sizeof(padapter->rmpriv.rm_en_cap_def),
+ padapter->rmpriv.rm_en_cap_def, &pattrib->pktlen);
+#endif
+
#ifdef CONFIG_P2P
if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
u32 len;
@@ -7544,6 +8402,10 @@ void issue_beacon(_adapter *padapter, int timeout_ms)
pframe += len;
pattrib->pktlen += len;
+#ifdef CONFIG_MCC_MODE
+ pframe = rtw_hal_mcc_append_go_p2p_ie(padapter, pframe, &pattrib->pktlen);
+#endif /* CONFIG_MCC_MODE*/
+
#ifdef CONFIG_WFD
len = rtw_append_beacon_wfd_ie(padapter, pframe);
pframe += len;
@@ -7551,7 +8413,9 @@ void issue_beacon(_adapter *padapter, int timeout_ms)
#endif
}
#endif /* CONFIG_P2P */
-
+#ifdef CONFIG_RTW_REPEATER_SON
+ rtw_rson_append_ie(padapter, pframe, &pattrib->pktlen);
+#endif
#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
pattrib->pktlen += rtw_build_vendor_ie(padapter , pframe , WIFI_BEACON_VENDOR_IE_BIT);
#endif
@@ -7693,7 +8557,7 @@ void issue_probersp(_adapter *padapter, unsigned char *da, u8 is_valid_p2p_probe
SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
pmlmeext->mgnt_seq++;
- SetFrameSubType(fctrl, WIFI_PROBERSP);
+ set_frame_sub_type(fctrl, WIFI_PROBERSP);
pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr);
pattrib->pktlen = pattrib->hdrlen;
@@ -7773,6 +8637,9 @@ void issue_probersp(_adapter *padapter, unsigned char *da, u8 is_valid_p2p_probe
pattrib->pktlen += ssid_ielen_diff;
}
}
+#ifdef CONFIG_RTW_REPEATER_SON
+ rtw_rson_append_ie(padapter, pframe, &pattrib->pktlen);
+#endif
#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
pattrib->pktlen += rtw_build_vendor_ie(padapter , pframe , WIFI_PROBERESP_VENDOR_IE_BIT);
#endif
@@ -7832,6 +8699,12 @@ void issue_probersp(_adapter *padapter, unsigned char *da, u8 is_valid_p2p_probe
}
+#ifdef CONFIG_RTW_80211K
+ pframe = rtw_set_ie(pframe, _EID_RRM_EN_CAP_IE_,
+ sizeof(padapter->rmpriv.rm_en_cap_def),
+ padapter->rmpriv.rm_en_cap_def, &pattrib->pktlen);
+#endif
+
#ifdef CONFIG_P2P
if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)
/* IOT issue, When wifi_spec is not set, send probe_resp with P2P IE even if probe_req has no P2P IE */
@@ -7852,6 +8725,10 @@ void issue_probersp(_adapter *padapter, unsigned char *da, u8 is_valid_p2p_probe
pframe += len;
pattrib->pktlen += len;
+#ifdef CONFIG_MCC_MODE
+ pframe = rtw_hal_mcc_append_go_p2p_ie(padapter, pframe, &pattrib->pktlen);
+#endif /* CONFIG_MCC_MODE*/
+
#ifdef CONFIG_WFD
len = rtw_append_probe_resp_wfd_ie(padapter, pframe);
pframe += len;
@@ -7877,7 +8754,7 @@ void issue_probersp(_adapter *padapter, unsigned char *da, u8 is_valid_p2p_probe
u16 cu_ch = (u16)cur_network->Configuration.DSConfig;
RTW_INFO("%s, reply rc(pid=0x%x) device "MAC_FMT" in ch=%d\n", __FUNCTION__,
- psta->pid, MAC_ARG(psta->hwaddr), cu_ch);
+ psta->pid, MAC_ARG(psta->cmn.mac_addr), cu_ch);
/* append vendor specific ie */
_rtw_memcpy(RC_INFO, RC_OUI, sizeof(RC_OUI));
@@ -7900,7 +8777,7 @@ void issue_probersp(_adapter *padapter, unsigned char *da, u8 is_valid_p2p_probe
}
-int _issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da, u8 ch, bool append_wps, int wait_ack)
+int _issue_probereq(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da, u8 ch, bool append_wps, int wait_ack)
{
int ret = _FAIL;
struct xmit_frame *pmgntframe;
@@ -7953,12 +8830,12 @@ int _issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da, u8 ch,
SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
pmlmeext->mgnt_seq++;
- SetFrameSubType(pframe, WIFI_PROBEREQ);
+ set_frame_sub_type(pframe, WIFI_PROBEREQ);
pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
- if (pssid)
+ if (pssid && !MLME_IS_MESH(padapter))
pframe = rtw_set_ie(pframe, _SSID_IE_, pssid->SsidLength, pssid->Ssid, &(pattrib->pktlen));
else
pframe = rtw_set_ie(pframe, _SSID_IE_, 0, NULL, &(pattrib->pktlen));
@@ -7974,6 +8851,15 @@ int _issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da, u8 ch,
if (ch)
pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, &ch, &pattrib->pktlen);
+#ifdef CONFIG_RTW_MESH
+ if (MLME_IS_MESH(padapter)) {
+ if (pssid)
+ pframe = rtw_set_ie_mesh_id(pframe, &pattrib->pktlen, pssid->Ssid, pssid->SsidLength);
+ else
+ pframe = rtw_set_ie_mesh_id(pframe, &pattrib->pktlen, NULL, 0);
+ }
+#endif
+
if (append_wps) {
/* add wps_ie for wps2.0 */
if (pmlmepriv->wps_probe_req_ie_len > 0 && pmlmepriv->wps_probe_req_ie) {
@@ -7989,7 +8875,6 @@ int _issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da, u8 ch,
pattrib->last_txcmdsz = pattrib->pktlen;
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_notice_, ("issuing probe_req, tx_len=%d\n", pattrib->last_txcmdsz));
if (wait_ack)
ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);
@@ -8002,7 +8887,7 @@ int _issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da, u8 ch,
return ret;
}
-inline void issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da)
+inline void issue_probereq(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da)
{
_issue_probereq(padapter, pssid, da, 0, 1, _FALSE);
}
@@ -8012,12 +8897,12 @@ inline void issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da)
* wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX
* try_cnt means the maximal TX count to try
*/
-int issue_probereq_ex(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da, u8 ch, bool append_wps,
+int issue_probereq_ex(_adapter *padapter, const NDIS_802_11_SSID *pssid, const u8 *da, u8 ch, bool append_wps,
int try_cnt, int wait_ms)
{
int ret = _FAIL;
int i = 0;
- u32 start = rtw_get_current_time();
+ systime start = rtw_get_current_time();
if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
goto exit;
@@ -8092,7 +8977,7 @@ void issue_auth(_adapter *padapter, struct sta_info *psta, unsigned short status
SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
pmlmeext->mgnt_seq++;
- SetFrameSubType(pframe, WIFI_AUTH);
+ set_frame_sub_type(pframe, WIFI_AUTH);
pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
@@ -8101,7 +8986,7 @@ void issue_auth(_adapter *padapter, struct sta_info *psta, unsigned short status
if (psta) { /* for AP mode */
#ifdef CONFIG_NATIVEAP_MLME
- _rtw_memcpy(pwlanhdr->addr1, psta->hwaddr, ETH_ALEN);
+ _rtw_memcpy(pwlanhdr->addr1, psta->cmn.mac_addr, ETH_ALEN);
_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN);
@@ -8138,12 +9023,21 @@ void issue_auth(_adapter *padapter, struct sta_info *psta, unsigned short status
_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
- /* setting auth algo number */
- val16 = (pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared) ? 1 : 0; /* 0:OPEN System, 1:Shared key */
- if (val16) {
- val16 = cpu_to_le16(val16);
- use_shared_key = 1;
+#ifdef CONFIG_RTW_80211R
+ if (rtw_ft_roam(padapter)) {
+ /* 2: 802.11R FTAA */
+ val16 = cpu_to_le16(2);
+ } else
+#endif
+ {
+ /* setting auth algo number */
+ val16 = (pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared) ? 1 : 0; /* 0:OPEN System, 1:Shared key */
+ if (val16) {
+ val16 = cpu_to_le16(val16);
+ use_shared_key = 1;
+ }
}
+
/* RTW_INFO("%s auth_algo= %s auth_seq=%d\n",__FUNCTION__,(pmlmeinfo->auth_algo==0)?"OPEN":"SHARED",pmlmeinfo->auth_seq); */
/* setting IV for auth seq #3 */
@@ -8169,6 +9063,10 @@ void issue_auth(_adapter *padapter, struct sta_info *psta, unsigned short status
val16 = cpu_to_le16(val16);
pframe = rtw_set_fixed_ie(pframe, _STATUS_CODE_, (unsigned char *)&val16, &(pattrib->pktlen));
+#ifdef CONFIG_RTW_80211R
+ rtw_ft_build_auth_req_ies(padapter, pattrib, &pframe);
+#endif
+
/* then checking to see if sending challenging text... */
if ((pmlmeinfo->auth_seq == 3) && (pmlmeinfo->state & WIFI_FW_AUTH_STATE) && (use_shared_key == 1)) {
pframe = rtw_set_ie(pframe, _CHLGETXT_IE_, 128, pmlmeinfo->chg_txt, &(pattrib->pktlen));
@@ -8242,15 +9140,15 @@ void issue_asocrsp(_adapter *padapter, unsigned short status, struct sta_info *p
fctrl = &(pwlanhdr->frame_ctl);
*(fctrl) = 0;
- _rtw_memcpy((void *)GetAddr1Ptr(pwlanhdr), pstat->hwaddr, ETH_ALEN);
- _rtw_memcpy((void *)GetAddr2Ptr(pwlanhdr), adapter_mac_addr(padapter), ETH_ALEN);
+ _rtw_memcpy((void *)GetAddr1Ptr(pwlanhdr), pstat->cmn.mac_addr, ETH_ALEN);
+ _rtw_memcpy((void *)get_addr2_ptr(pwlanhdr), adapter_mac_addr(padapter), ETH_ALEN);
_rtw_memcpy((void *)GetAddr3Ptr(pwlanhdr), get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
pmlmeext->mgnt_seq++;
if ((pkt_type == WIFI_ASSOCRSP) || (pkt_type == WIFI_REASSOCRSP))
- SetFrameSubType(pwlanhdr, pkt_type);
+ set_frame_sub_type(pwlanhdr, pkt_type);
else
return;
@@ -8266,7 +9164,7 @@ void issue_asocrsp(_adapter *padapter, unsigned short status, struct sta_info *p
ie_status = cpu_to_le16(status);
pframe = rtw_set_fixed_ie(pframe , _STATUS_CODE_ , (unsigned char *)&ie_status, &(pattrib->pktlen));
- val = cpu_to_le16(pstat->aid | BIT(14) | BIT(15));
+ val = cpu_to_le16(pstat->cmn.aid | BIT(14) | BIT(15));
pframe = rtw_set_fixed_ie(pframe, _ASOC_ID_ , (unsigned char *)&val, &(pattrib->pktlen));
if (pstat->bssratelen <= 8)
@@ -8417,7 +9315,7 @@ void issue_asocrsp(_adapter *padapter, unsigned short status, struct sta_info *p
#endif
}
-void issue_assocreq(_adapter *padapter)
+void _issue_assocreq(_adapter *padapter, u8 is_reassoc)
{
int ret = _FAIL;
struct xmit_frame *pmgntframe;
@@ -8446,6 +9344,7 @@ void issue_assocreq(_adapter *padapter)
#endif /* CONFIG_P2P */
#ifdef CONFIG_DFS
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
u16 cap;
/* Dot H */
@@ -8478,7 +9377,10 @@ void issue_assocreq(_adapter *padapter)
SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
pmlmeext->mgnt_seq++;
- SetFrameSubType(pframe, WIFI_ASSOCREQ);
+ if (is_reassoc == _TRUE)
+ set_frame_sub_type(pframe, WIFI_REASSOCREQ);
+ else
+ set_frame_sub_type(pframe, WIFI_ASSOCREQ);
pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
@@ -8503,6 +9405,13 @@ void issue_assocreq(_adapter *padapter)
pframe += 2;
pattrib->pktlen += 2;
+ /*Construct Current AP Field for Reassoc-Req only*/
+ if (is_reassoc == _TRUE) {
+ _rtw_memcpy(pframe, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
+ pframe += ETH_ALEN;
+ pattrib->pktlen += ETH_ALEN;
+ }
+
/* SSID */
pframe = rtw_set_ie(pframe, _SSID_IE_, pmlmeinfo->network.Ssid.SsidLength, pmlmeinfo->network.Ssid.Ssid, &(pattrib->pktlen));
@@ -8514,16 +9423,17 @@ void issue_assocreq(_adapter *padapter)
pframe = rtw_set_ie(pframe, EID_PowerCap, 2, pow_cap_ele, &(pattrib->pktlen));
/* supported channels */
- do {
- if (pmlmeext->channel_set[sup_ch_idx].ChannelNum <= 14) {
+ while (sup_ch_idx < rfctl->max_chan_nums && rfctl->channel_set[sup_ch_idx].ChannelNum != 0) {
+ if (rfctl->channel_set[sup_ch_idx].ChannelNum <= 14) {
+ /* TODO: fix 2.4G supported channel when channel doesn't start from 1 and continuous */
sup_ch[0] = 1; /* First channel number */
- sup_ch[1] = pmlmeext->channel_set[sup_ch_idx].ChannelNum; /* Number of channel */
+ sup_ch[1] = rfctl->channel_set[sup_ch_idx].ChannelNum; /* Number of channel */
} else {
- sup_ch[idx_5g++] = pmlmeext->channel_set[sup_ch_idx].ChannelNum;
+ sup_ch[idx_5g++] = rfctl->channel_set[sup_ch_idx].ChannelNum;
sup_ch[idx_5g++] = 1;
}
sup_ch_idx++;
- } while (pmlmeext->channel_set[sup_ch_idx].ChannelNum != 0);
+ }
pframe = rtw_set_ie(pframe, EID_SupportedChannels, idx_5g, sup_ch, &(pattrib->pktlen));
}
#endif /* CONFIG_DFS */
@@ -8609,6 +9519,16 @@ void issue_assocreq(_adapter *padapter)
else
RTW_INFO("%s: Connect to AP without 11b and 11g data rate!\n", __FUNCTION__);
+#ifdef CONFIG_RTW_80211K
+ if (pmlmeinfo->network.PhyInfo.rm_en_cap[0] /* RM Enabled Capabilities */
+ | pmlmeinfo->network.PhyInfo.rm_en_cap[1]
+ | pmlmeinfo->network.PhyInfo.rm_en_cap[2]
+ | pmlmeinfo->network.PhyInfo.rm_en_cap[3]
+ | pmlmeinfo->network.PhyInfo.rm_en_cap[4])
+ pframe = rtw_set_ie(pframe, _EID_RRM_EN_CAP_IE_, 5,
+ (u8 *)padapter->rmpriv.rm_en_cap_def, &(pattrib->pktlen));
+#endif /* CONFIG_RTW_80211K */
+
/* vendor specific IE, such as WPA, WMM, WPS */
for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pmlmeinfo->network.IELength;) {
pIE = (PNDIS_802_11_VARIABLE_IEs)(pmlmeinfo->network.IEs + i);
@@ -8632,7 +9552,12 @@ void issue_assocreq(_adapter *padapter)
break;
case EID_WPA2:
- pframe = rtw_set_ie(pframe, EID_WPA2, pIE->Length, pIE->data, &(pattrib->pktlen));
+#ifdef CONFIG_RTW_80211R
+ if ((is_reassoc) && (rtw_ft_roam(padapter))) {
+ rtw_ft_update_rsnie(padapter, _TRUE, pattrib, &pframe);
+ } else
+#endif
+ pframe = rtw_set_ie(pframe, EID_WPA2, pIE->Length, pIE->data, &(pattrib->pktlen));
break;
#ifdef CONFIG_80211N_HT
case EID_HTCapability:
@@ -8826,9 +9751,16 @@ void issue_assocreq(_adapter *padapter)
pframe += wfdielen;
pattrib->pktlen += wfdielen;
#endif
+#ifdef CONFIG_RTW_REPEATER_SON
+ rtw_rson_append_ie(padapter, pframe, &pattrib->pktlen);
+#endif
#ifdef CONFIG_APPEND_VENDOR_IE_ENABLE
pattrib->pktlen += rtw_build_vendor_ie(padapter , pframe , WIFI_ASSOCREQ_VENDOR_IE_BIT);
#endif
+#ifdef CONFIG_RTW_80211R
+ rtw_ft_build_assoc_req_ies(padapter, is_reassoc, pattrib, &pframe);
+#endif
+
pattrib->last_txcmdsz = pattrib->pktlen;
dump_mgntframe(padapter, pmgntframe);
@@ -8843,6 +9775,16 @@ void issue_assocreq(_adapter *padapter)
return;
}
+void issue_assocreq(_adapter *padapter)
+{
+ _issue_assocreq(padapter, _FALSE);
+}
+
+void issue_reassocreq(_adapter *padapter)
+{
+ _issue_assocreq(padapter, _TRUE);
+}
+
/* when wait_ack is ture, this function shoule be called at process context */
static int _issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int wait_ack)
{
@@ -8855,6 +9797,7 @@ static int _issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int p
struct xmit_priv *pxmitpriv;
struct mlme_ext_priv *pmlmeext;
struct mlme_ext_info *pmlmeinfo;
+ u8 a4_shift;
/* RTW_INFO("%s:%d\n", __FUNCTION__, power_mode); */
@@ -8885,24 +9828,38 @@ static int _issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int p
fctrl = &(pwlanhdr->frame_ctl);
*(fctrl) = 0;
- if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)
+ if (MLME_IS_AP(padapter))
SetFrDs(fctrl);
- else if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE)
+ else if (MLME_IS_STA(padapter))
SetToDs(fctrl);
+ else if (MLME_IS_MESH(padapter)) {
+ SetToDs(fctrl);
+ SetFrDs(fctrl);
+ }
if (power_mode)
SetPwrMgt(fctrl);
- _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
- _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
- _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
+ if (get_tofr_ds(fctrl) == 3) {
+ _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
+ _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+ _rtw_memcpy(pwlanhdr->addr3, da, ETH_ALEN);
+ _rtw_memcpy(pwlanhdr->addr4, adapter_mac_addr(padapter), ETH_ALEN);
+ a4_shift = ETH_ALEN;
+ pattrib->hdrlen += ETH_ALEN;
+ } else {
+ _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
+ _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
+ a4_shift = 0;
+ }
SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
pmlmeext->mgnt_seq++;
- SetFrameSubType(pframe, WIFI_DATA_NULL);
+ set_frame_sub_type(pframe, WIFI_DATA_NULL);
- pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
- pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+ pframe += sizeof(struct rtw_ieee80211_hdr_3addr) + a4_shift;
+ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr) + a4_shift;
pattrib->last_txcmdsz = pattrib->pktlen;
@@ -8918,8 +9875,6 @@ static int _issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int p
}
/*
- * [IMPORTANT] Don't call this function in interrupt context
- *
* When wait_ms > 0, this function should be called at process context
* wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT
* wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX
@@ -8930,48 +9885,17 @@ int issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mod
{
int ret = _FAIL;
int i = 0;
- u32 start = rtw_get_current_time();
+ systime start = rtw_get_current_time();
struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
- struct sta_info *psta;
- u8 macid_sleep_reg_access = _TRUE;
-
-#ifdef CONFIG_MCC_MODE
- if (MCC_EN(padapter)) {
- /* driver doesn't access macid sleep reg under MCC */
- if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
- macid_sleep_reg_access = _FALSE;
-
- if (da == NULL) {
- RTW_INFO("Warning: Do not tx null data to AP under MCC mode\n");
- rtw_warn_on(1);
- }
-
- }
- }
-#endif
if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
goto exit;
- /* da == NULL, assum it's null data for sta to ap*/
+ /* da == NULL, assum it's null data for sta to ap */
if (da == NULL)
da = get_my_bssid(&(pmlmeinfo->network));
- psta = rtw_get_stainfo(&padapter->stapriv, da);
- if (psta) {
- if (macid_sleep_reg_access) {
- if (power_mode)
- rtw_hal_macid_sleep(padapter, psta->mac_id);
- else
- rtw_hal_macid_wakeup(padapter, psta->mac_id);
- }
- } else {
- RTW_INFO(FUNC_ADPT_FMT ": Can't find sta info for " MAC_FMT ", skip macid %s!!\n",
- FUNC_ADPT_ARG(padapter), MAC_ARG(da), power_mode ? "sleep" : "wakeup");
- rtw_warn_on(1);
- }
-
do {
ret = _issue_nulldata(padapter, da, power_mode, wait_ms > 0 ? _TRUE : _FALSE);
@@ -9006,33 +9930,8 @@ int issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mod
return ret;
}
-/*
- * [IMPORTANT] This function run in interrupt context
- *
- * The null data packet would be sent without power bit,
- * and not guarantee success.
- */
-s32 issue_nulldata_in_interrupt(PADAPTER padapter, u8 *da, unsigned int power_mode)
-{
- int ret;
- struct mlme_ext_priv *pmlmeext;
- struct mlme_ext_info *pmlmeinfo;
-
-
- pmlmeext = &padapter->mlmeextpriv;
- pmlmeinfo = &pmlmeext->mlmext_info;
-
- /* da == NULL, assum it's null data for sta to ap*/
- if (da == NULL)
- da = get_my_bssid(&(pmlmeinfo->network));
-
- ret = _issue_nulldata(padapter, da, power_mode, _FALSE);
-
- return ret;
-}
-
/* when wait_ack is ture, this function shoule be called at process context */
-static int _issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, int wait_ack)
+static int _issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, u8 ps, int wait_ack)
{
int ret = _FAIL;
struct xmit_frame *pmgntframe;
@@ -9043,11 +9942,12 @@ static int _issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, i
struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+ u8 a4_shift;
if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
goto exit;
- RTW_INFO("%s\n", __FUNCTION__);
+ /* RTW_INFO("%s\n", __FUNCTION__); */
pmgntframe = alloc_mgtxmitframe(pxmitpriv);
if (pmgntframe == NULL)
@@ -9071,14 +9971,35 @@ static int _issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, i
fctrl = &(pwlanhdr->frame_ctl);
*(fctrl) = 0;
- if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)
+ if (MLME_IS_AP(padapter))
SetFrDs(fctrl);
- else if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE)
+ else if (MLME_IS_STA(padapter))
+ SetToDs(fctrl);
+ else if (MLME_IS_MESH(padapter)) {
SetToDs(fctrl);
+ SetFrDs(fctrl);
+ }
+
+ if (ps)
+ SetPwrMgt(fctrl);
if (pattrib->mdata)
SetMData(fctrl);
+ if (get_tofr_ds(fctrl) == 3) {
+ _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
+ _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+ _rtw_memcpy(pwlanhdr->addr3, da, ETH_ALEN);
+ _rtw_memcpy(pwlanhdr->addr4, adapter_mac_addr(padapter), ETH_ALEN);
+ a4_shift = ETH_ALEN;
+ pattrib->hdrlen += ETH_ALEN;
+ } else {
+ _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
+ _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
+ a4_shift = 0;
+ }
+
qc = (unsigned short *)(pframe + pattrib->hdrlen - 2);
SetPriority(qc, tid);
@@ -9087,16 +10008,12 @@ static int _issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, i
SetAckpolicy(qc, pattrib->ack_policy);
- _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN);
- _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
- _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
-
SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
pmlmeext->mgnt_seq++;
- SetFrameSubType(pframe, WIFI_QOS_DATA_NULL);
+ set_frame_sub_type(pframe, WIFI_QOS_DATA_NULL);
- pframe += sizeof(struct rtw_ieee80211_hdr_3addr_qos);
- pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos);
+ pframe += sizeof(struct rtw_ieee80211_hdr_3addr_qos) + a4_shift;
+ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos) + a4_shift;
pattrib->last_txcmdsz = pattrib->pktlen;
@@ -9118,11 +10035,11 @@ static int _issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, i
* try_cnt means the maximal TX count to try
* da == NULL for station mode
*/
-int issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, int try_cnt, int wait_ms)
+int issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, u8 ps, int try_cnt, int wait_ms)
{
int ret = _FAIL;
int i = 0;
- u32 start = rtw_get_current_time();
+ systime start = rtw_get_current_time();
struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
@@ -9134,7 +10051,7 @@ int issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, int try_c
da = get_my_bssid(&(pmlmeinfo->network));
do {
- ret = _issue_qos_nulldata(padapter, da, tid, wait_ms > 0 ? _TRUE : _FALSE);
+ ret = _issue_qos_nulldata(padapter, da, tid, ps, wait_ms > 0 ? _TRUE : _FALSE);
i++;
@@ -9217,7 +10134,7 @@ static int _issue_deauth(_adapter *padapter, unsigned char *da, unsigned short r
SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
pmlmeext->mgnt_seq++;
- SetFrameSubType(pframe, WIFI_DEAUTH);
+ set_frame_sub_type(pframe, WIFI_DEAUTH);
pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
@@ -9263,7 +10180,7 @@ int issue_deauth_ex(_adapter *padapter, u8 *da, unsigned short reason, int try_c
{
int ret = _FAIL;
int i = 0;
- u32 start = rtw_get_current_time();
+ systime start = rtw_get_current_time();
if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
goto exit;
@@ -9344,7 +10261,7 @@ void issue_action_spct_ch_switch(_adapter *padapter, u8 *ra, u8 new_ch, u8 ch_of
SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
pmlmeext->mgnt_seq++;
- SetFrameSubType(pframe, WIFI_ACTION);
+ set_frame_sub_type(pframe, WIFI_ACTION);
pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
@@ -9419,7 +10336,7 @@ void issue_action_SA_Query(_adapter *padapter, unsigned char *raddr, unsigned ch
SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
pmlmeext->mgnt_seq++;
- SetFrameSubType(pframe, WIFI_ACTION);
+ set_frame_sub_type(pframe, WIFI_ACTION);
pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
@@ -9433,7 +10350,7 @@ void issue_action_SA_Query(_adapter *padapter, unsigned char *raddr, unsigned ch
pmlmeext->sa_query_seq++;
/* send sa query request to AP, AP should reply sa query response in 1 second */
if (pattrib->key_type == IEEE80211W_RIGHT_KEY) {
- psta = rtw_get_stainfo(pstapriv, raddr);
+ psta = rtw_get_stainfo(pstapriv, pwlanhdr->addr1);
if (psta != NULL) {
/* RTW_INFO("%s, %d, set dot11w_expire_timer\n", __func__, __LINE__); */
_set_timer(&psta->dot11w_expire_timer, 1000);
@@ -9520,7 +10437,7 @@ static int issue_action_ba(_adapter *padapter, unsigned char *raddr, unsigned ch
SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
pmlmeext->mgnt_seq++;
- SetFrameSubType(pframe, WIFI_ACTION);
+ set_frame_sub_type(pframe, WIFI_ACTION);
pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
@@ -9542,6 +10459,12 @@ static int issue_action_ba(_adapter *padapter, unsigned char *raddr, unsigned ch
BA_para_set = (0x1002 | ((tid & 0xf) << 2)); /* immediate ack & 64 buffer size */
#endif
+#ifdef CONFIG_TX_AMSDU
+ if (padapter->tx_amsdu >= 1) /* TX AMSDU enabled */
+ BA_para_set |= BIT(0);
+ else /* TX AMSDU disabled */
+ BA_para_set &= ~BIT(0);
+#endif
BA_para_set = cpu_to_le16(BA_para_set);
pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_para_set)), &(pattrib->pktlen));
@@ -9580,9 +10503,9 @@ static int issue_action_ba(_adapter *padapter, unsigned char *raddr, unsigned ch
BA_para_set |= (size << 6) & RTW_IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK;
if (!padapter->registrypriv.wifi_spec) {
- if (pregpriv->ampdu_amsdu == 0) /* disabled */
+ if (pregpriv->rx_ampdu_amsdu == 0) /* disabled */
BA_para_set &= ~BIT(0);
- else if (pregpriv->ampdu_amsdu == 1) /* enabled */
+ else if (pregpriv->rx_ampdu_amsdu == 1) /* enabled */
BA_para_set |= BIT(0);
}
@@ -9677,7 +10600,7 @@ inline u8 issue_addba_rsp_wait_ack(_adapter *adapter, unsigned char *ra, u8 tid,
{
int ret = _FAIL;
int i = 0;
- u32 start = rtw_get_current_time();
+ systime start = rtw_get_current_time();
if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(adapter)))
goto exit;
@@ -9709,8 +10632,8 @@ inline u8 issue_addba_rsp_wait_ack(_adapter *adapter, unsigned char *ra, u8 tid,
}
if (try_cnt && wait_ms) {
- RTW_INFO(FUNC_ADPT_FMT" ra="MAC_FMT" tid=%u%s, %d/%d in %u ms\n"
- , FUNC_ADPT_ARG(adapter), MAC_ARG(ra), tid
+ RTW_INFO(FUNC_ADPT_FMT" ra="MAC_FMT" status:=%u tid=%u size:%u%s, %d/%d in %u ms\n"
+ , FUNC_ADPT_ARG(adapter), MAC_ARG(ra), status, tid, size
, ret == _SUCCESS ? ", acked" : "", i, try_cnt, rtw_get_passing_time_ms(start));
}
@@ -9755,7 +10678,7 @@ int issue_del_ba_ex(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8
{
int ret = _FAIL;
int i = 0;
- u32 start = rtw_get_current_time();
+ systime start = rtw_get_current_time();
if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(adapter)))
goto exit;
@@ -9795,7 +10718,7 @@ int issue_del_ba_ex(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8
return ret;
}
-static void issue_action_BSSCoexistPacket(_adapter *padapter)
+void issue_action_BSSCoexistPacket(_adapter *padapter)
{
_irqL irqL;
_list *plist, *phead;
@@ -9851,7 +10774,7 @@ static void issue_action_BSSCoexistPacket(_adapter *padapter)
SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
pmlmeext->mgnt_seq++;
- SetFrameSubType(pframe, WIFI_ACTION);
+ set_frame_sub_type(pframe, WIFI_ACTION);
pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
@@ -10001,7 +10924,7 @@ int _issue_action_SM_PS(_adapter *padapter , unsigned char *raddr , u8 NewMimoP
SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
pmlmeext->mgnt_seq++;
- SetFrameSubType(pframe, WIFI_ACTION);
+ set_frame_sub_type(pframe, WIFI_ACTION);
pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
@@ -10036,7 +10959,7 @@ int issue_action_SM_PS_wait_ack(_adapter *padapter, unsigned char *raddr, u8 New
{
int ret = _FAIL;
int i = 0;
- u32 start = rtw_get_current_time();
+ systime start = rtw_get_current_time();
if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter)))
goto exit;
@@ -10117,9 +11040,9 @@ static unsigned int _send_delba_sta_tid(_adapter *adapter, u8 initiator, struct
if (rtw_del_rx_ampdu_test_trigger_no_tx_fail())
ret = _FAIL;
else if (wait_ack)
- ret = issue_del_ba_ex(adapter, sta->hwaddr, tid, 37, initiator, 3, 1);
+ ret = issue_del_ba_ex(adapter, sta->cmn.mac_addr, tid, 37, initiator, 3, 1);
else
- issue_del_ba(adapter, sta->hwaddr, tid, 37, initiator);
+ issue_del_ba(adapter, sta->cmn.mac_addr, tid, 37, initiator);
if (ret == _FAIL && sta->recvreorder_ctrl[tid].enable == _FALSE)
sta->recvreorder_ctrl[tid].ampdu_size = ampdu_size_bak;
@@ -10130,7 +11053,7 @@ static unsigned int _send_delba_sta_tid(_adapter *adapter, u8 initiator, struct
if (force || sta->htpriv.agg_enable_bitmap & BIT(tid)) {
sta->htpriv.agg_enable_bitmap &= ~BIT(tid);
sta->htpriv.candidate_tid_bitmap &= ~BIT(tid);
- issue_del_ba(adapter, sta->hwaddr, tid, 37, initiator);
+ issue_del_ba(adapter, sta->cmn.mac_addr, tid, 37, initiator);
}
#endif
}
@@ -10189,6 +11112,12 @@ unsigned int send_beacon(_adapter *padapter)
#endif
#ifdef CONFIG_PCI_HCI
+ /* bypass TX BCN queue because op ch is switching/waiting */
+ if (check_fwstate(&padapter->mlmepriv, WIFI_OP_CH_SWITCHING)
+ || IS_CH_WAITING(adapter_to_rfctl(padapter))
+ )
+ return _SUCCESS;
+
/* RTW_INFO("%s\n", __FUNCTION__); */
rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL);
@@ -10208,35 +11137,53 @@ unsigned int send_beacon(_adapter *padapter)
#endif
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
- u32 start = rtw_get_current_time();
+ systime start = rtw_get_current_time();
- rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL);
- rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL);
- do {
- issue_beacon(padapter, 100);
- issue++;
- do {
- rtw_yield_os();
- rtw_hal_get_hwreg(padapter, HW_VAR_BCN_VALID, (u8 *)(&bxmitok));
- poll++;
- } while ((poll % 10) != 0 && _FALSE == bxmitok && !RTW_CANNOT_RUN(padapter));
+ /* bypass TX BCN queue because op ch is switching/waiting */
+ if (check_fwstate(&padapter->mlmepriv, WIFI_OP_CH_SWITCHING)
+ || IS_CH_WAITING(adapter_to_rfctl(padapter))
+ )
+ return _SUCCESS;
- } while (_FALSE == bxmitok && issue < 100 && !RTW_CANNOT_RUN(padapter));
+#if defined(CONFIG_USB_HCI)
+#if defined(CONFIG_RTL8812A)
+ if (IS_FULL_SPEED_USB(padapter)) {
+ issue_beacon(padapter, 300);
+ bxmitok = _TRUE;
+ } else
+#endif
+#endif
+ {
+ rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL);
+ rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL);
+ do {
+ issue_beacon(padapter, 100);
+ issue++;
+ do {
+ rtw_yield_os();
+ rtw_hal_get_hwreg(padapter, HW_VAR_BCN_VALID, (u8 *)(&bxmitok));
+ poll++;
+ } while ((poll % 10) != 0 && _FALSE == bxmitok && !RTW_CANNOT_RUN(padapter));
+ } while (bxmitok == _FALSE && (issue < 100) && !RTW_CANNOT_RUN(padapter));
+ }
if (RTW_CANNOT_RUN(padapter))
return _FAIL;
if (_FALSE == bxmitok) {
RTW_INFO("%s fail! %u ms\n", __FUNCTION__, rtw_get_passing_time_ms(start));
+ #ifdef CONFIG_BCN_RECOVERY
+ GET_HAL_DATA(padapter)->issue_bcn_fail++;
+ #endif /*CONFIG_BCN_RECOVERY*/
return _FAIL;
} else {
u32 passing_time = rtw_get_passing_time_ms(start);
if (passing_time > 100 || issue > 3)
RTW_INFO("%s success, issue:%d, poll:%d, %u ms\n", __FUNCTION__, issue, poll, rtw_get_passing_time_ms(start));
- /* else */
- /* RTW_INFO("%s success, issue:%d, poll:%d, %u ms\n", __FUNCTION__, issue, poll, rtw_get_passing_time_ms(start)); */
+ else if (0)
+ RTW_INFO("%s success, issue:%d, poll:%d, %u ms\n", __FUNCTION__, issue, poll, rtw_get_passing_time_ms(start));
rtw_hal_fw_correct_bcn(padapter);
@@ -10274,16 +11221,20 @@ BOOLEAN IsLegal5GChannel(
u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSID_EX *bssid)
{
int i;
- u32 len;
+ sint len;
u8 *p;
+ u8 rf_path;
u16 val16, subtype;
u8 *pframe = precv_frame->u.hdr.rx_data;
u32 packet_len = precv_frame->u.hdr.len;
u8 ie_offset;
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct registry_priv *pregistrypriv = &padapter->registrypriv;
+ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+
len = packet_len - sizeof(struct rtw_ieee80211_hdr_3addr);
if (len > MAX_IE_SZ) {
@@ -10293,21 +11244,21 @@ u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSI
_rtw_memset(bssid, 0, sizeof(WLAN_BSSID_EX));
- subtype = GetFrameSubType(pframe);
+ subtype = get_frame_sub_type(pframe);
if (subtype == WIFI_BEACON) {
- bssid->Reserved[0] = 1;
+ bssid->Reserved[0] = BSS_TYPE_BCN;
ie_offset = _BEACON_IE_OFFSET_;
} else {
/* FIXME : more type */
if (subtype == WIFI_PROBERSP) {
ie_offset = _PROBERSP_IE_OFFSET_;
- bssid->Reserved[0] = 3;
+ bssid->Reserved[0] = BSS_TYPE_PROB_RSP;
} else if (subtype == WIFI_PROBEREQ) {
ie_offset = _PROBEREQ_IE_OFFSET_;
- bssid->Reserved[0] = 2;
+ bssid->Reserved[0] = BSS_TYPE_PROB_REQ;
} else {
- bssid->Reserved[0] = 0;
+ bssid->Reserved[0] = BSS_TYPE_UNDEF;
ie_offset = _FIXED_IE_LENGTH_;
}
}
@@ -10320,9 +11271,19 @@ u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSI
/* get the signal strength */
/* bssid->Rssi = precv_frame->u.hdr.attrib.SignalStrength; */ /* 0-100 index. */
- bssid->Rssi = precv_frame->u.hdr.attrib.phy_info.RecvSignalPower; /* in dBM.raw data */
- bssid->PhyInfo.SignalQuality = precv_frame->u.hdr.attrib.phy_info.SignalQuality;/* in percentage */
- bssid->PhyInfo.SignalStrength = precv_frame->u.hdr.attrib.phy_info.SignalStrength;/* in percentage */
+ bssid->Rssi = precv_frame->u.hdr.attrib.phy_info.recv_signal_power; /* in dBM.raw data */
+ bssid->PhyInfo.SignalQuality = precv_frame->u.hdr.attrib.phy_info.signal_quality;/* in percentage */
+ bssid->PhyInfo.SignalStrength = precv_frame->u.hdr.attrib.phy_info.signal_strength;/* in percentage */
+
+ /* get rx_snr */
+ if (precv_frame->u.hdr.attrib.data_rate >= DESC_RATE11M) {
+ bssid->PhyInfo.is_cck_rate = 0;
+ for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++)
+ bssid->PhyInfo.rx_snr[rf_path] =
+ precv_frame->u.hdr.attrib.phy_info.rx_snr[rf_path];
+ } else
+ bssid->PhyInfo.is_cck_rate = 1;
+
#ifdef CONFIG_ANTENNA_DIVERSITY
rtw_hal_get_odm_var(padapter, HAL_ODM_ANTDIV_SELECT, &(bssid->PhyInfo.Optimum_antenna), NULL);
#endif
@@ -10397,7 +11358,7 @@ u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSI
/* FIXME */
bssid->InfrastructureMode = Ndis802_11Infrastructure;
- _rtw_memcpy(bssid->MacAddress, GetAddr2Ptr(pframe), ETH_ALEN);
+ _rtw_memcpy(bssid->MacAddress, get_addr2_ptr(pframe), ETH_ALEN);
bssid->Privacy = 1;
return _SUCCESS;
}
@@ -10432,12 +11393,49 @@ u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSI
val16 = rtw_get_capability((WLAN_BSSID_EX *)bssid);
- if (val16 & BIT(0)) {
+ if ((val16 & 0x03) == cap_ESS) {
bssid->InfrastructureMode = Ndis802_11Infrastructure;
- _rtw_memcpy(bssid->MacAddress, GetAddr2Ptr(pframe), ETH_ALEN);
- } else {
+ _rtw_memcpy(bssid->MacAddress, get_addr2_ptr(pframe), ETH_ALEN);
+ } else if ((val16 & 0x03) == cap_IBSS){
bssid->InfrastructureMode = Ndis802_11IBSS;
_rtw_memcpy(bssid->MacAddress, GetAddr3Ptr(pframe), ETH_ALEN);
+ } else if ((val16 & 0x03) == 0x00){
+ u8 *mesh_id_ie, *mesh_conf_ie;
+ sint mesh_id_ie_len, mesh_conf_ie_len;
+
+ mesh_id_ie = rtw_get_ie(bssid->IEs + ie_offset, WLAN_EID_MESH_ID, &mesh_id_ie_len, bssid->IELength - ie_offset);
+ mesh_conf_ie = rtw_get_ie(bssid->IEs + ie_offset, WLAN_EID_MESH_CONFIG, &mesh_conf_ie_len, bssid->IELength - ie_offset);
+ if (mesh_id_ie || mesh_conf_ie) {
+ if (!mesh_id_ie) {
+ RTW_INFO("cannot find Mesh ID for survey event\n");
+ return _FAIL;
+ }
+ if (mesh_id_ie_len) {
+ if (mesh_id_ie_len > NDIS_802_11_LENGTH_SSID) {
+ RTW_INFO("Mesh ID too long (%d) for survey event\n", mesh_id_ie_len);
+ return _FAIL;
+ }
+ _rtw_memcpy(bssid->mesh_id.Ssid, (mesh_id_ie + 2), mesh_id_ie_len);
+ bssid->mesh_id.SsidLength = mesh_id_ie_len;
+ } else
+ bssid->mesh_id.SsidLength = 0;
+
+ if (!mesh_conf_ie) {
+ RTW_INFO("cannot find Mesh config for survey event\n");
+ return _FAIL;
+ }
+ if (mesh_conf_ie_len != 7) {
+ RTW_INFO("invalid Mesh conf IE len (%d) for survey event\n", mesh_conf_ie_len);
+ return _FAIL;
+ }
+
+ bssid->InfrastructureMode = Ndis802_11_mesh;
+ _rtw_memcpy(bssid->MacAddress, GetAddr3Ptr(pframe), ETH_ALEN);
+ } else {
+ /* default cases */
+ bssid->InfrastructureMode = Ndis802_11IBSS;
+ _rtw_memcpy(bssid->MacAddress, GetAddr3Ptr(pframe), ETH_ALEN);
+ }
}
if (val16 & BIT(4))
@@ -10484,6 +11482,14 @@ u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSI
if (bssid->Configuration.DSConfig != rtw_get_oper_ch(padapter))
bssid->PhyInfo.SignalQuality = 101;
+#ifdef CONFIG_RTW_80211K
+ p = rtw_get_ie(bssid->IEs + ie_offset, _EID_RRM_EN_CAP_IE_, &len, bssid->IELength - ie_offset);
+ if (p)
+ _rtw_memcpy(bssid->PhyInfo.rm_en_cap, (p + 2), *(p + 1));
+
+ /* save freerun counter */
+ bssid->PhyInfo.free_cnt = precv_frame->u.hdr.attrib.free_cnt;
+#endif
return _SUCCESS;
}
@@ -10515,7 +11521,6 @@ void start_create_ibss(_adapter *padapter)
rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk);
/* switch channel */
- /* SelectChannel(padapter, pmlmeext->cur_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE); */
set_channel_bwmode(padapter, pmlmeext->cur_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
doiqk = _FALSE;
@@ -10529,7 +11534,6 @@ void start_create_ibss(_adapter *padapter)
/* issue beacon */
if (send_beacon(padapter) == _FAIL) {
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("issuing beacon frame fail....\n"));
report_join_res(padapter, -1);
pmlmeinfo->state = WIFI_FW_NULL_STATE;
@@ -10537,6 +11541,7 @@ void start_create_ibss(_adapter *padapter)
rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, padapter->registrypriv.dev_network.MacAddress);
join_type = 0;
rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));
+ rtw_hal_rcr_set_chk_bssid(padapter, MLME_ADHOC_STARTED);
report_join_res(padapter, 1);
pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS;
@@ -10613,7 +11618,7 @@ void start_clnt_join(_adapter *padapter)
if (_rtw_memcmp(&(scanned->network.Ssid), &(pnetwork->Ssid), sizeof(NDIS_802_11_SSID)) == _TRUE
&& _rtw_memcmp(scanned->network.MacAddress, pnetwork->MacAddress, sizeof(NDIS_802_11_MAC_ADDRESS)) == _TRUE
) {
- ie_offset = (scanned->network.Reserved[0] == 2 ? 0 : 12);
+ ie_offset = (scanned->network.Reserved[0] == BSS_TYPE_PROB_REQ ? 0 : 12);
if (rtw_get_p2p_ie(scanned->network.IEs + ie_offset, scanned->network.IELength - ie_offset, NULL, NULL))
has_p2p_ie = _TRUE;
break;
@@ -10636,9 +11641,18 @@ void start_clnt_join(_adapter *padapter)
_set_timer(&padapter->mlmepriv.assoc_timer,
(REAUTH_TO * REAUTH_LIMIT) + (REASSOC_TO * REASSOC_LIMIT) + beacon_timeout);
- pmlmeinfo->state = WIFI_FW_AUTH_NULL | WIFI_FW_STATION_STATE;
+#ifdef CONFIG_RTW_80211R
+ if (rtw_ft_roam(padapter)) {
+ rtw_ft_start_clnt_join(padapter);
+ } else
+#endif
+ {
+ rtw_sta_linking_test_set_start();
+ pmlmeinfo->state = WIFI_FW_AUTH_NULL | WIFI_FW_STATION_STATE;
+ }
} else if (caps & cap_IBSS) { /* adhoc client */
Set_MSR(padapter, WIFI_FW_ADHOC_STATE);
+ rtw_hal_rcr_set_chk_bssid(padapter, MLME_ADHOC_STARTED);
val8 = 0xcf;
rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8));
@@ -10671,8 +11685,13 @@ void start_clnt_auth(_adapter *padapter)
pmlmeinfo->link_count = 0;
pmlmeext->retry = 0;
-
- RTW_PRINT("start auth\n");
+#ifdef CONFIG_RTW_80211R
+ if (rtw_ft_roam(padapter)) {
+ rtw_ft_set_status(padapter, RTW_FT_AUTHENTICATING_STA);
+ RTW_PRINT("start ft auth\n");
+ } else
+#endif
+ RTW_PRINT("start auth\n");
issue_auth(padapter, NULL, 0);
set_link_timer(pmlmeext, REAUTH_TO);
@@ -10690,7 +11709,12 @@ void start_clnt_assoc(_adapter *padapter)
pmlmeinfo->state &= (~(WIFI_FW_AUTH_NULL | WIFI_FW_AUTH_STATE));
pmlmeinfo->state |= (WIFI_FW_AUTH_SUCCESS | WIFI_FW_ASSOC_STATE);
- issue_assocreq(padapter);
+#ifdef CONFIG_RTW_80211R
+ if (rtw_ft_roam(padapter))
+ issue_reassocreq(padapter);
+ else
+#endif
+ issue_assocreq(padapter);
set_link_timer(pmlmeext, REASSOC_TO);
}
@@ -10705,6 +11729,9 @@ unsigned int receive_disconnect(_adapter *padapter, unsigned char *MacAddr, unsi
RTW_INFO("%s\n", __FUNCTION__);
+#ifdef CONFIG_RTW_REPEATER_SON
+ rtw_rson_do_disconnect(padapter);
+#endif
if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) {
if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) {
if (report_del_sta_event(padapter, MacAddr, reason, _TRUE, locally_generated) != _FAIL)
@@ -10714,6 +11741,12 @@ unsigned int receive_disconnect(_adapter *padapter, unsigned char *MacAddr, unsi
pmlmeinfo->state = WIFI_FW_NULL_STATE;
} else
RTW_INFO(FUNC_ADPT_FMT" - End to Disconnect\n", FUNC_ADPT_ARG(padapter));
+#ifdef CONFIG_RTW_80211R
+ rtw_ft_roam_status_reset(padapter);
+#endif
+#ifdef CONFIG_RTW_WNM
+ rtw_wnm_reset_btm_state(padapter);
+#endif
}
return _SUCCESS;
@@ -10722,6 +11755,7 @@ unsigned int receive_disconnect(_adapter *padapter, unsigned char *MacAddr, unsi
#ifdef CONFIG_80211D
static void process_80211d(PADAPTER padapter, WLAN_BSSID_EX *bssid)
{
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
struct registry_priv *pregistrypriv;
struct mlme_ext_priv *pmlmeext;
RT_CHANNEL_INFO *chplan_new;
@@ -10738,7 +11772,7 @@ static void process_80211d(PADAPTER padapter, WLAN_BSSID_EX *bssid)
u8 *ie, *p;
u32 len;
RT_CHANNEL_PLAN chplan_ap;
- RT_CHANNEL_INFO chplan_sta[MAX_CHANNEL_NUM];
+ RT_CHANNEL_INFO *chplan_sta = NULL;
u8 country[4];
u8 fcn; /* first channel number */
u8 noc; /* number of channel */
@@ -10786,7 +11820,11 @@ static void process_80211d(PADAPTER padapter, WLAN_BSSID_EX *bssid)
_RTW_INFO("}\n");
#endif
- _rtw_memcpy(chplan_sta, pmlmeext->channel_set, sizeof(chplan_sta));
+ chplan_sta = rtw_malloc(sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM);
+ if (!chplan_sta)
+ goto done_update_chplan_from_ap;
+
+ _rtw_memcpy(chplan_sta, rfctl->channel_set, sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM);
#ifdef CONFIG_RTW_DEBUG
i = 0;
RTW_INFO("%s: STA channel plan {", __FUNCTION__);
@@ -10797,8 +11835,8 @@ static void process_80211d(PADAPTER padapter, WLAN_BSSID_EX *bssid)
_RTW_INFO("}\n");
#endif
- _rtw_memset(pmlmeext->channel_set, 0, sizeof(pmlmeext->channel_set));
- chplan_new = pmlmeext->channel_set;
+ _rtw_memset(rfctl->channel_set, 0, sizeof(rfctl->channel_set));
+ chplan_new = rfctl->channel_set;
i = j = k = 0;
if (pregistrypriv->wireless_mode & WIRELESS_11G) {
@@ -10958,26 +11996,10 @@ static void process_80211d(PADAPTER padapter, WLAN_BSSID_EX *bssid)
k++;
}
#endif
- }
- /* If channel is used by AP, set channel scan type to active */
- channel = bssid->Configuration.DSConfig;
- chplan_new = pmlmeext->channel_set;
- i = 0;
- while ((i < MAX_CHANNEL_NUM) && (chplan_new[i].ChannelNum != 0)) {
- if (chplan_new[i].ChannelNum == channel) {
- if (chplan_new[i].ScanType == SCAN_PASSIVE) {
- /* 5G Bnad 2, 3 (DFS) doesn't change to active scan */
- if (channel >= 52 && channel <= 144)
- break;
-
- chplan_new[i].ScanType = SCAN_ACTIVE;
- RTW_INFO("%s: change channel %d scan type from passive to active\n",
- __FUNCTION__, channel);
- }
- break;
- }
- i++;
+done_update_chplan_from_ap:
+ if (chplan_sta)
+ rtw_mfree(chplan_sta, sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM);
}
}
#endif
@@ -10999,6 +12021,8 @@ void report_survey_event(_adapter *padapter, union recv_frame *precv_frame)
struct cmd_priv *pcmdpriv;
/* u8 *pframe = precv_frame->u.hdr.rx_data; */
/* uint len = precv_frame->u.hdr.len; */
+ RT_CHANNEL_INFO *chset = adapter_to_chset(padapter);
+ int ch_set_idx = -1;
if (!padapter)
return;
@@ -11044,6 +12068,23 @@ void report_survey_event(_adapter *padapter, union recv_frame *precv_frame)
process_80211d(padapter, &psurvey_evt->bss);
#endif
+ ch_set_idx = rtw_chset_search_ch(chset, psurvey_evt->bss.Configuration.DSConfig);
+ if (ch_set_idx >= 0) {
+ if (psurvey_evt->bss.InfrastructureMode == Ndis802_11Infrastructure) {
+ if (chset[ch_set_idx].ScanType == SCAN_PASSIVE
+ && !rtw_is_dfs_ch(psurvey_evt->bss.Configuration.DSConfig)
+ ) {
+ RTW_INFO("%s: change ch:%d to active\n", __func__, psurvey_evt->bss.Configuration.DSConfig);
+ chset[ch_set_idx].ScanType = SCAN_ACTIVE;
+ }
+ #ifdef CONFIG_DFS
+ if (psurvey_evt->bss.Ssid.SsidLength == 0
+ || is_all_null(psurvey_evt->bss.Ssid.Ssid, psurvey_evt->bss.Ssid.SsidLength) == _TRUE)
+ chset[ch_set_idx].hidden_bss_cnt++;
+ #endif
+ }
+ }
+
rtw_enqueue_cmd(pcmdpriv, pcmd_obj);
pmlmeext->sitesurvey_res.bss_cnt++;
@@ -11227,7 +12268,7 @@ u32 report_del_sta_event(_adapter *padapter, unsigned char *MacAddr, unsigned sh
_rtw_memcpy((unsigned char *)(pdel_sta_evt->rsvd), (unsigned char *)(&reason), 2);
psta = rtw_get_stainfo(&padapter->stapriv, MacAddr);
if (psta)
- mac_id = (int)psta->mac_id;
+ mac_id = (int)psta->cmn.mac_id;
else
mac_id = (-1);
pdel_sta_evt->mac_id = mac_id;
@@ -11363,9 +12404,9 @@ bool rtw_port_switch_chk(_adapter *adapter)
}
#endif /* CONFIG_WOWLAN */
- /* AP should use port0 for ctl frame's ack */
+ /* AP/Mesh should use port0 for ctl frame's ack */
if ((if_port1_mlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {
- RTW_INFO("%s "ADPT_FMT" is AP/GO\n", __func__, ADPT_ARG(if_port1));
+ RTW_INFO("%s "ADPT_FMT" is AP/GO/Mesh\n", __func__, ADPT_ARG(if_port1));
switch_needed = _TRUE;
goto exit;
}
@@ -11373,7 +12414,9 @@ bool rtw_port_switch_chk(_adapter *adapter)
/* GC should use port0 for p2p ps */
if (((if_port1_mlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE)
&& (if_port1_mlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)
+#ifdef CONFIG_P2P
&& !rtw_p2p_chk_state(&if_port1->wdinfo, P2P_STATE_NONE)
+#endif
&& !check_fwstate(&if_port1->mlmepriv, WIFI_UNDER_WPS)
) {
RTW_INFO("%s "ADPT_FMT" is GC\n", __func__, ADPT_ARG(if_port1));
@@ -11439,6 +12482,10 @@ void update_sta_info(_adapter *padapter, struct sta_info *psta)
psta->htpriv.beamform_cap = pmlmepriv->htpriv.beamform_cap;
_rtw_memcpy(&psta->htpriv.ht_cap, &pmlmeinfo->HT_caps, sizeof(struct rtw_ieee80211_ht_cap));
+ #ifdef CONFIG_BEAMFORMING
+ psta->htpriv.beamform_cap = pmlmepriv->htpriv.beamform_cap;
+ psta->cmn.bf_info.ht_beamform_cap = pmlmepriv->htpriv.beamform_cap;
+ #endif
} else
#endif /* CONFIG_80211N_HT */
{
@@ -11460,7 +12507,7 @@ void update_sta_info(_adapter *padapter, struct sta_info *psta)
psta->htpriv.candidate_tid_bitmap = 0x0;/* reset */
#endif /* CONFIG_80211N_HT */
- psta->bw_mode = pmlmeext->cur_bwmode;
+ psta->cmn.bw_mode = pmlmeext->cur_bwmode;
/* QoS */
if (pmlmepriv->qospriv.qos_option)
@@ -11468,8 +12515,15 @@ void update_sta_info(_adapter *padapter, struct sta_info *psta)
#ifdef CONFIG_80211AC_VHT
_rtw_memcpy(&psta->vhtpriv, &pmlmepriv->vhtpriv, sizeof(struct vht_priv));
+ if (psta->vhtpriv.vht_option) {
+ psta->cmn.ra_info.is_vht_enable = _TRUE;
+ #ifdef CONFIG_BEAMFORMING
+ psta->vhtpriv.beamform_cap = pmlmepriv->vhtpriv.beamform_cap;
+ psta->cmn.bf_info.vht_beamform_cap = pmlmepriv->vhtpriv.beamform_cap;
+ #endif /*CONFIG_BEAMFORMING*/
+ }
#endif /* CONFIG_80211AC_VHT */
-
+ psta->cmn.ra_info.is_support_sgi = query_ra_short_GI(psta, rtw_get_tx_bw_mode(padapter, psta));
update_ldpc_stbc_cap(psta);
_enter_critical_bh(&psta->lock, &irqL);
@@ -11484,9 +12538,25 @@ static void rtw_mlmeext_disconnect(_adapter *padapter)
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network));
+ u8 self_action = MLME_ACTION_UNKNOWN;
u8 state_backup = (pmlmeinfo->state & 0x03);
u8 ASIX_ID[] = {0x00, 0x0E, 0xC6};
+ if (MLME_IS_AP(padapter))
+ self_action = MLME_AP_STOPPED;
+ else if (MLME_IS_MESH(padapter))
+ self_action = MLME_MESH_STOPPED;
+ else if (MLME_IS_STA(padapter))
+ self_action = MLME_STA_DISCONNECTED;
+ else if (MLME_IS_ADHOC(padapter) || MLME_IS_ADHOC_MASTER(padapter))
+ self_action = MLME_ADHOC_STOPPED;
+ else if (MLME_IS_NULL(padapter))
+ self_action = MLME_ACTION_NONE;
+ else {
+ RTW_INFO("state:0x%x\n", MLME_STATE(padapter));
+ rtw_warn_on(1);
+ }
+
/* set_opmode_cmd(padapter, infra_client_with_mlme); */
rtw_hal_set_hwreg(padapter, HW_VAR_MLME_DISCONNECT, 0);
@@ -11530,10 +12600,7 @@ static void rtw_mlmeext_disconnect(_adapter *padapter)
#endif
#ifdef CONFIG_DFS_MASTER
- if (check_fwstate(pmlmepriv, WIFI_AP_STATE))
- rtw_dfs_master_status_apply(padapter, MLME_AP_STOPPED);
- else if (check_fwstate(pmlmepriv, WIFI_STATION_STATE))
- rtw_dfs_master_status_apply(padapter, MLME_STA_DISCONNECTED);
+ rtw_dfs_master_status_apply(padapter, self_action);
#endif
{
@@ -11561,6 +12628,17 @@ static void rtw_mlmeext_disconnect(_adapter *padapter)
padapter->tdlsinfo.ch_switch_prohibited = _FALSE;
#endif /* CONFIG_TDLS */
+#ifdef CONFIG_WMMPS_STA
+ if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) {
+ /* reset currently related uapsd setting when the connection has broken */
+ pmlmepriv->qospriv.uapsd_max_sp_len = 0;
+ pmlmepriv->qospriv.uapsd_tid = 0;
+ pmlmepriv->qospriv.uapsd_tid_delivery_enabled = 0;
+ pmlmepriv->qospriv.uapsd_tid_trigger_enabled = 0;
+ pmlmepriv->qospriv.uapsd_ap_supported = 0;
+ }
+#endif /* CONFIG_WMMPS_STA */
+
}
void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res)
@@ -11585,6 +12663,7 @@ void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res)
}
#ifdef CONFIG_ARP_KEEP_ALIVE
pmlmepriv->bGetGateway = 1;
+ pmlmepriv->GetGatewayTryCnt = 0;
#endif
if ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) {
@@ -11620,10 +12699,12 @@ void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res)
psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress);
if (psta) { /* only for infra. mode */
- /* RTW_INFO("set_sta_rate\n"); */
-
psta->wireless_mode = pmlmeext->cur_wireless_mode;
+#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
+ rtw_hal_set_default_port_id_cmd(padapter, psta->cmn.mac_id);
+#endif
+
/* set per sta rate after updating HT cap. */
set_sta_rate(padapter, psta);
@@ -11631,7 +12712,7 @@ void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res)
/* wakeup macid after join bss successfully to ensure
the subsequent data frames can be sent out normally */
- rtw_hal_macid_wakeup(padapter, psta->mac_id);
+ rtw_hal_macid_wakeup(padapter, psta->cmn.mac_id);
}
#ifndef CONFIG_IOCTL_CFG80211
@@ -11653,7 +12734,9 @@ void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res)
}
#ifdef CONFIG_LPS
+ #ifndef CONFIG_FW_MULTI_PORT_SUPPORT
if (get_hw_port(padapter) == HW_PORT0)
+ #endif
rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_CONNECT, 0);
#endif
@@ -11665,7 +12748,9 @@ void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res)
exit_mlmeext_joinbss_event_callback:
rtw_join_done_chk_ch(padapter, join_res);
-
+#ifdef CONFIG_RTW_REPEATER_SON
+ rtw_rson_join_done(padapter);
+#endif
RTW_INFO("=>%s - End to Connection without 4-way\n", __FUNCTION__);
}
@@ -11702,11 +12787,11 @@ void mlmeext_sta_add_event_callback(_adapter *padapter, struct sta_info *psta)
/* update adhoc sta_info */
update_sta_info(padapter, psta);
- rtw_hal_update_sta_rate_mask(padapter, psta);
+ rtw_hal_update_sta_ra_info(padapter, psta);
/* ToDo: HT for Ad-hoc */
psta->wireless_mode = rtw_check_network_type(psta->bssrateset, psta->bssratelen, pmlmeext->cur_channel);
- psta->raid = rtw_hal_networktype_to_raid(padapter, psta);
+ rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _TRUE);
/* rate radaptive */
Update_RA_Entry(padapter, psta);
@@ -11729,51 +12814,17 @@ Following are the functions for the timer handlers
*****************************************************************************/
void _linked_info_dump(_adapter *padapter)
{
- int i;
- struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
- struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
- HAL_DATA_TYPE *HalData = GET_HAL_DATA(padapter);
- int UndecoratedSmoothedPWDB = 0;
-
if (padapter->bLinkInfoDump) {
-
- RTW_INFO("\n============["ADPT_FMT"] linked status check ===================\n", ADPT_ARG(padapter));
-
- if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) {
- rtw_hal_get_def_var(padapter, HAL_DEF_UNDERCORATEDSMOOTHEDPWDB, &UndecoratedSmoothedPWDB);
-
- RTW_INFO("AP[" MAC_FMT "] - UndecoratedSmoothedPWDB:%d\n",
- MAC_ARG(padapter->mlmepriv.cur_network.network.MacAddress), UndecoratedSmoothedPWDB);
- } else if ((pmlmeinfo->state & 0x03) == _HW_STATE_AP_) {
- _irqL irqL;
- _list *phead, *plist;
-
- struct sta_info *psta = NULL;
- struct sta_priv *pstapriv = &padapter->stapriv;
-
- _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
- phead = &pstapriv->asoc_list;
- plist = get_next(phead);
- while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
- psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
- plist = get_next(plist);
-
- RTW_INFO("STA[" MAC_FMT "]:UndecoratedSmoothedPWDB:%d\n",
- MAC_ARG(psta->hwaddr), psta->rssi_stat.UndecoratedSmoothedPWDB);
- }
- _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
-
- }
-
- /*============ tx info ============ */
rtw_hal_get_def_var(padapter, HW_DEF_RA_INFO_DUMP, RTW_DBGDUMP);
-
rtw_hal_set_odm_var(padapter, HAL_ODM_RX_INFO_DUMP, RTW_DBGDUMP, _FALSE);
-
}
+}
+/********************************************************************
+When station does not receive any packet in MAX_CONTINUAL_NORXPACKET_COUNT*2 seconds,
+recipient station will teardown the block ack by issuing DELBA frame.
-}
+*********************************************************************/
void rtw_delba_check(_adapter *padapter, struct sta_info *psta, u8 from_timer)
{
int i = 0;
@@ -11791,20 +12842,19 @@ void rtw_delba_check(_adapter *padapter, struct sta_info *psta, u8 from_timer)
*/
if (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM) {
for (i = 0; i < TID_NUM ; i++) {
- if (sta_rx_data_qos_pkts(psta, i) == sta_last_rx_data_qos_pkts(psta, i)) {
- if (_TRUE == rtw_inc_and_chk_continual_no_rx_packet(psta, i)) {
- if (psta->recvreorder_ctrl[i].enable) {
+ if ((psta->recvreorder_ctrl[i].enable) &&
+ (sta_rx_data_qos_pkts(psta, i) == sta_last_rx_data_qos_pkts(psta, i)) ) {
+ if (_TRUE == rtw_inc_and_chk_continual_no_rx_packet(psta, i)) {
/* send a DELBA frame to the peer STA with the Reason Code field set to TIMEOUT */
if (!from_timer)
- ret = issue_del_ba_ex(padapter, psta->hwaddr, i, 39, 0, 3, 1);
+ ret = issue_del_ba_ex(padapter, psta->cmn.mac_addr, i, 39, 0, 3, 1);
else
- issue_del_ba(padapter, psta->hwaddr, i, 39, 0);
+ issue_del_ba(padapter, psta->cmn.mac_addr, i, 39, 0);
psta->recvreorder_ctrl[i].enable = _FALSE;
if (ret != _FAIL)
psta->recvreorder_ctrl[i].ampdu_size = RX_AMPDU_SIZE_INVALID;
rtw_reset_continual_no_rx_packet(psta, i);
- }
- }
+ }
} else {
/* The inactivity timer is reset when MPDUs to the TID is received. */
rtw_reset_continual_no_rx_packet(psta, i);
@@ -11816,7 +12866,6 @@ void rtw_delba_check(_adapter *padapter, struct sta_info *psta, u8 from_timer)
u8 chk_ap_is_alive(_adapter *padapter, struct sta_info *psta)
{
u8 ret = _FALSE;
- int i = 0;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
@@ -11836,7 +12885,7 @@ u8 chk_ap_is_alive(_adapter *padapter, struct sta_info *psta)
);
RTW_INFO(FUNC_ADPT_FMT" tx_pkts:%llu, link_count:%u\n", FUNC_ADPT_ARG(padapter)
- , padapter->xmitpriv.tx_pkts
+ , sta_tx_pkts(psta)
, pmlmeinfo->link_count
);
#endif
@@ -11851,12 +12900,6 @@ u8 chk_ap_is_alive(_adapter *padapter, struct sta_info *psta)
sta_update_last_rx_pkts(psta);
- /*
- record last rx data packets for every tid.
- */
- for (i = 0; i < TID_NUM; i++)
- psta->sta_stats.last_rx_data_qos_pkts[i] = psta->sta_stats.rx_data_qos_pkts[i];
-
return ret;
}
@@ -11868,8 +12911,8 @@ u8 chk_adhoc_peer_is_alive(struct sta_info *psta)
RTW_INFO("sta:"MAC_FMT", rssi:%d, rx:"STA_PKTS_FMT", beacon:%llu, probersp_to_self:%llu"
/*", probersp_bm:%llu, probersp_uo:%llu, probereq:%llu, BI:%u"*/
", expire_to:%u\n"
- , MAC_ARG(psta->hwaddr)
- , psta->rssi_stat.UndecoratedSmoothedPWDB
+ , MAC_ARG(psta->cmn.mac_addr)
+ , psta->cmn.rssi_stat.rssi
, STA_RX_PKTS_DIFF_ARG(psta)
, psta->sta_stats.rx_beacon_pkts - psta->sta_stats.last_rx_beacon_pkts
, psta->sta_stats.rx_probersp_pkts - psta->sta_stats.last_rx_probersp_pkts
@@ -11940,11 +12983,11 @@ void linked_status_chk_tdls(_adapter *padapter)
if (psta->alive_count >= ALIVE_MIN) {
if (chk_tdls_peer_sta_is_alive(padapter, psta) == _FALSE) {
if (psta->alive_count < ALIVE_MAX) {
- _rtw_memcpy(checkalive[num_checkalive].addr, psta->hwaddr, ETH_ALEN);
+ _rtw_memcpy(checkalive[num_checkalive].addr, psta->cmn.mac_addr, ETH_ALEN);
checkalive[num_checkalive].psta = psta;
num_checkalive++;
} else {
- _rtw_memcpy(teardown[num_teardown].addr, psta->hwaddr, ETH_ALEN);
+ _rtw_memcpy(teardown[num_teardown].addr, psta->cmn.mac_addr, ETH_ALEN);
teardown[num_teardown].psta = psta;
num_teardown++;
}
@@ -11997,10 +13040,15 @@ void linked_status_chk(_adapter *padapter, u8 from_timer)
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
struct sta_priv *pstapriv = &padapter->stapriv;
-#ifdef CONFIG_ARP_KEEP_ALIVE
+#if defined(CONFIG_ARP_KEEP_ALIVE) || defined(CONFIG_LAYER2_ROAMING)
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
#endif
+#ifdef CONFIG_LAYER2_ROAMING
+ struct recv_priv *precvpriv = &padapter->recvpriv;
+#endif
+ if (padapter->registrypriv.mp_mode == _TRUE)
+ return;
if (is_client_associated_to_ap(padapter)) {
/* linked infrastructure client mode */
@@ -12009,6 +13057,21 @@ void linked_status_chk(_adapter *padapter, u8 from_timer)
int rx_chk_limit;
int link_count_limit;
+#if defined(CONFIG_RTW_REPEATER_SON)
+ rtw_rson_scan_wk_cmd(padapter, RSON_SCAN_PROCESS);
+#elif defined(CONFIG_LAYER2_ROAMING)
+ if (rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE)) {
+ RTW_INFO("signal_strength_data.avg_val = %d\n", precvpriv->signal_strength_data.avg_val);
+ if (precvpriv->signal_strength_data.avg_val < pmlmepriv->roam_rssi_threshold) {
+#ifdef CONFIG_RTW_80211K
+ rtw_roam_nb_discover(padapter, _FALSE);
+#endif
+ pmlmepriv->need_to_roam = _TRUE;
+ rtw_drv_scan_by_self(padapter, RTW_AUTO_SCAN_REASON_ROAM);
+ } else
+ pmlmepriv->need_to_roam = _FALSE;
+ }
+#endif
#ifdef CONFIG_MCC_MODE
/*
* due to tx ps null date to ao, so ap doest not tx pkt to driver
@@ -12019,7 +13082,7 @@ void linked_status_chk(_adapter *padapter, u8 from_timer)
return;
#endif
-#if defined(DBG_ROAMING_TEST)
+#if defined(DBG_ROAMING_TEST) || defined(CONFIG_RTW_REPEATER_SON)
rx_chk_limit = 1;
#elif defined(CONFIG_ACTIVE_KEEP_ALIVE_CHECK) && !defined(CONFIG_LPS_LCLK_WD_TIMER)
rx_chk_limit = 4;
@@ -12027,8 +13090,9 @@ void linked_status_chk(_adapter *padapter, u8 from_timer)
rx_chk_limit = 8;
#endif
#ifdef CONFIG_ARP_KEEP_ALIVE
- if (!from_timer && pmlmepriv->bGetGateway == 1) {
- RTW_INFO("do rtw_gw_addr_query()");
+ if (!from_timer && pmlmepriv->bGetGateway == 1 && pmlmepriv->GetGatewayTryCnt < 3) {
+ RTW_INFO("do rtw_gw_addr_query() : %d\n", pmlmepriv->GetGatewayTryCnt);
+ pmlmepriv->GetGatewayTryCnt++;
if (rtw_gw_addr_query(padapter) == 0)
pmlmepriv->bGetGateway = 0;
else {
@@ -12070,45 +13134,61 @@ void linked_status_chk(_adapter *padapter, u8 from_timer)
is_p2p_enable = !rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE);
#endif
+#ifdef CONFIG_ISSUE_DELBA_WHEN_NO_TRAFFIC
/*issue delba when ap does not tx data packet that is Broadcom ap */
rtw_delba_check(padapter, psta, from_timer);
-
+#endif
if (chk_ap_is_alive(padapter, psta) == _FALSE)
rx_chk = _FAIL;
- if (pxmitpriv->last_tx_pkts == pxmitpriv->tx_pkts)
+ if (sta_last_tx_pkts(psta) == sta_tx_pkts(psta))
tx_chk = _FAIL;
#if defined(CONFIG_ACTIVE_KEEP_ALIVE_CHECK) && !defined(CONFIG_LPS_LCLK_WD_TIMER)
if (pmlmeext->active_keep_alive_check && (rx_chk == _FAIL || tx_chk == _FAIL)
+ ) {
+ u8 backup_ch = 0, backup_bw = 0, backup_offset = 0;
+ u8 union_ch = 0, union_bw = 0, union_offset = 0;
+ u8 switch_channel_by_drv = _TRUE;
+
+
#ifdef CONFIG_MCC_MODE
- /* Driver don't know operation channel under MCC*/
- /* So driver don't do KEEP_ALIVE_CHECK */
- && (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC))
+ if (MCC_EN(padapter)) {
+ /* driver doesn't switch channel under MCC */
+ if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
+ switch_channel_by_drv = _FALSE;
+ }
#endif
- ) {
- u8 backup_oper_channel = 0;
-
- /* switch to correct channel of current network before issue keep-alive frames */
- if (rtw_get_oper_ch(padapter) != pmlmeext->cur_channel) {
- backup_oper_channel = rtw_get_oper_ch(padapter);
- SelectChannel(padapter, pmlmeext->cur_channel);
+ if (switch_channel_by_drv) {
+ if (!rtw_mi_get_ch_setting_union(padapter, &union_ch, &union_bw, &union_offset)
+ || pmlmeext->cur_channel != union_ch)
+ goto bypass_active_keep_alive;
+
+ /* switch to correct channel of current network before issue keep-alive frames */
+ if (rtw_get_oper_ch(padapter) != pmlmeext->cur_channel) {
+ backup_ch = rtw_get_oper_ch(padapter);
+ backup_bw = rtw_get_oper_bw(padapter);
+ backup_offset = rtw_get_oper_choffset(padapter);
+ set_channel_bwmode(padapter, union_ch, union_offset, union_bw);
+ }
}
if (rx_chk != _SUCCESS)
- issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, psta->hwaddr, 0, 0, 3, 1);
+ issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, psta->cmn.mac_addr, 0, 0, 3, 1);
if ((tx_chk != _SUCCESS && pmlmeinfo->link_count++ == link_count_limit) || rx_chk != _SUCCESS) {
- tx_chk = issue_nulldata(padapter, psta->hwaddr, 0, 3, 1);
+ tx_chk = issue_nulldata(padapter, psta->cmn.mac_addr, 0, 3, 1);
/* if tx acked and p2p disabled, set rx_chk _SUCCESS to reset retry count */
if (tx_chk == _SUCCESS && !is_p2p_enable)
rx_chk = _SUCCESS;
}
/* back to the original operation channel */
- if (backup_oper_channel > 0)
- SelectChannel(padapter, backup_oper_channel);
+ if (backup_ch > 0 && switch_channel_by_drv)
+ set_channel_bwmode(padapter, backup_ch, backup_offset, backup_bw);
+bypass_active_keep_alive:
+ ;
} else
#endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */
{
@@ -12117,9 +13197,9 @@ void linked_status_chk(_adapter *padapter, u8 from_timer)
#ifdef DBG_EXPIRATION_CHK
RTW_INFO("issue_probereq to trigger probersp, retry=%d\n", pmlmeext->retry);
#endif
- issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, 0);
- issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, 0);
- issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, 0);
+ issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, (from_timer ? 0 : 1));
+ issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, (from_timer ? 0 : 1));
+ issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, (from_timer ? 0 : 1));
}
}
@@ -12128,11 +13208,14 @@ void linked_status_chk(_adapter *padapter, u8 from_timer)
/* FW tx nulldata under MCC mode, we just check ap is alive */
&& (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC))
#endif /* CONFIG_MCC_MODE */
- ) {
-#ifdef DBG_EXPIRATION_CHK
+ ) {
+ #ifdef DBG_EXPIRATION_CHK
RTW_INFO("%s issue_nulldata(%d)\n", __FUNCTION__, from_timer ? 1 : 0);
-#endif
- tx_chk = issue_nulldata_in_interrupt(padapter, NULL, from_timer ? 1 : 0);
+ #endif
+ if (from_timer)
+ tx_chk = issue_nulldata(padapter, NULL, 1, 0, 0);
+ else
+ tx_chk = issue_nulldata(padapter, NULL, 0, 1, 1);
}
}
@@ -12151,7 +13234,7 @@ void linked_status_chk(_adapter *padapter, u8 from_timer)
if (tx_chk == _FAIL)
pmlmeinfo->link_count %= (link_count_limit + 1);
else {
- pxmitpriv->last_tx_pkts = pxmitpriv->tx_pkts;
+ psta->sta_stats.last_tx_pkts = psta->sta_stats.tx_pkts;
pmlmeinfo->link_count = 0;
}
@@ -12173,7 +13256,7 @@ void linked_status_chk(_adapter *padapter, u8 from_timer)
psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
plist = get_next(plist);
- if (is_broadcast_mac_addr(psta->hwaddr))
+ if (is_broadcast_mac_addr(psta->cmn.mac_addr))
continue;
if (chk_adhoc_peer_is_alive(psta) || !psta->expire_to)
@@ -12196,15 +13279,16 @@ void linked_status_chk(_adapter *padapter, u8 from_timer)
plist = get_next(plist);
rtw_list_delete(&psta->list);
RTW_INFO(FUNC_ADPT_FMT" ibss expire "MAC_FMT"\n"
- , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->hwaddr));
- report_del_sta_event(padapter, psta->hwaddr, WLAN_REASON_EXPIRATION_CHK, from_timer ? _TRUE : _FALSE, _FALSE);
+ , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr));
+ report_del_sta_event(padapter, psta->cmn.mac_addr, WLAN_REASON_EXPIRATION_CHK, from_timer ? _TRUE : _FALSE, _FALSE);
}
}
}
-void survey_timer_hdl(_adapter *padapter)
+void survey_timer_hdl(void *ctx)
{
+ _adapter *padapter = (_adapter *)ctx;
struct cmd_obj *cmd;
struct sitesurvey_parm *psurveyPara;
struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
@@ -12235,15 +13319,41 @@ void survey_timer_hdl(_adapter *padapter)
return;
}
-void link_timer_hdl(_adapter *padapter)
+#ifdef CONFIG_RTW_REPEATER_SON
+/* 100ms pass, stop rson_scan */
+void rson_timer_hdl(void *ctx)
+{
+ _adapter *padapter = (_adapter *)ctx;
+
+ rtw_rson_scan_wk_cmd(padapter, RSON_SCAN_DISABLE);
+}
+
+#endif
+
+void link_timer_hdl(void *ctx)
{
+ _adapter *padapter = (_adapter *)ctx;
/* static unsigned int rx_pkt = 0; */
/* static u64 tx_cnt = 0; */
/* struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); */
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
/* struct sta_priv *pstapriv = &padapter->stapriv; */
+#ifdef CONFIG_RTW_80211R
+ struct sta_priv *pstapriv = &padapter->stapriv;
+ struct sta_info *psta = NULL;
+ WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network));
+#endif
+ if (rtw_sta_linking_test_force_fail())
+ RTW_INFO("rtw_sta_linking_test_force_fail\n");
+
+ if (pmlmeext->join_abort && pmlmeinfo->state != WIFI_FW_NULL_STATE) {
+ RTW_INFO(FUNC_ADPT_FMT" join abort\n", FUNC_ADPT_ARG(padapter));
+ pmlmeinfo->state = WIFI_FW_NULL_STATE;
+ report_join_res(padapter, -4);
+ goto exit;
+ }
if (pmlmeinfo->state & WIFI_FW_AUTH_NULL) {
RTW_INFO("link_timer_hdl:no beacon while connecting\n");
@@ -12273,20 +13383,39 @@ void link_timer_hdl(_adapter *padapter)
/* re-assoc timer */
if (++pmlmeinfo->reassoc_count > REASSOC_LIMIT) {
pmlmeinfo->state = WIFI_FW_NULL_STATE;
+#ifdef CONFIG_RTW_80211R
+ if (rtw_ft_roam(padapter)) {
+ psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress);
+ if (psta)
+ rtw_free_stainfo(padapter, psta);
+ }
+#endif
report_join_res(padapter, -2);
return;
}
- RTW_INFO("link_timer_hdl: assoc timeout and try again\n");
- issue_assocreq(padapter);
+#ifdef CONFIG_RTW_80211R
+ if (rtw_ft_roam(padapter)) {
+ RTW_INFO("link_timer_hdl: reassoc timeout and try again\n");
+ issue_reassocreq(padapter);
+ } else
+#endif
+ {
+ RTW_INFO("link_timer_hdl: assoc timeout and try again\n");
+ issue_assocreq(padapter);
+ }
+
set_link_timer(pmlmeext, REASSOC_TO);
}
+exit:
return;
}
-void addba_timer_hdl(struct sta_info *psta)
+void addba_timer_hdl(void *ctx)
{
+ struct sta_info *psta = (struct sta_info *)ctx;
+
#ifdef CONFIG_80211N_HT
struct ht_priv *phtpriv;
@@ -12348,7 +13477,7 @@ void report_sta_timeout_event(_adapter *padapter, u8 *MacAddr, unsigned short re
psta = rtw_get_stainfo(&padapter->stapriv, MacAddr);
if (psta)
- mac_id = (int)psta->mac_id;
+ mac_id = (int)psta->cmn.mac_id;
else
mac_id = (-1);
@@ -12363,16 +13492,16 @@ void report_sta_timeout_event(_adapter *padapter, u8 *MacAddr, unsigned short re
void clnt_sa_query_timeout(_adapter *padapter)
{
+ struct mlme_ext_priv *mlmeext = &(padapter->mlmeextpriv);
+ struct mlme_ext_info *mlmeinfo = &(mlmeext->mlmext_info);
- rtw_disassoc_cmd(padapter, 0, _TRUE);
- rtw_indicate_disconnect(padapter, 0, _FALSE);
- rtw_free_assoc_resources(padapter, 1);
-
- RTW_INFO("SA query timeout client disconnect\n");
+ RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
+ receive_disconnect(padapter, get_my_bssid(&(mlmeinfo->network)), WLAN_REASON_SA_QUERY_TIMEOUT, _FALSE);
}
-void sa_query_timer_hdl(struct sta_info *psta)
+void sa_query_timer_hdl(void *ctx)
{
+ struct sta_info *psta = (struct sta_info *)ctx;
_adapter *padapter = psta->padapter;
_irqL irqL;
struct sta_priv *pstapriv = &padapter->stapriv;
@@ -12382,24 +13511,469 @@ void sa_query_timer_hdl(struct sta_info *psta)
check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
clnt_sa_query_timeout(padapter);
else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
- report_sta_timeout_event(padapter, psta->hwaddr, WLAN_REASON_PREV_AUTH_NOT_VALID);
+ report_sta_timeout_event(padapter, psta->cmn.mac_addr, WLAN_REASON_PREV_AUTH_NOT_VALID);
+}
+
+#endif /* CONFIG_IEEE80211W */
+
+#ifdef CONFIG_RTW_80211R
+void rtw_ft_update_bcn(_adapter *padapter, union recv_frame *precv_frame)
+{
+ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+ u8 *pframe = precv_frame->u.hdr.rx_data;
+ uint len = precv_frame->u.hdr.len;
+ WLAN_BSSID_EX *pbss;
+
+ if (rtw_ft_chk_status(padapter,RTW_FT_ASSOCIATED_STA)
+ && (pmlmepriv->ft_roam.ft_updated_bcn == _FALSE)) {
+ pbss = (WLAN_BSSID_EX*)rtw_malloc(sizeof(WLAN_BSSID_EX));
+ if (pbss) {
+ if (collect_bss_info(padapter, precv_frame, pbss) == _SUCCESS) {
+ struct beacon_keys recv_beacon;
+
+ update_network(&(pmlmepriv->cur_network.network), pbss, padapter, _TRUE);
+ rtw_get_bcn_info(&(pmlmepriv->cur_network));
+
+ /* update bcn keys */
+ if (rtw_get_bcn_keys(padapter, pframe, len, &recv_beacon) == _TRUE) {
+ RTW_INFO("%s: beacon keys ready\n", __func__);
+ _rtw_memcpy(&pmlmepriv->cur_beacon_keys,
+ &recv_beacon, sizeof(recv_beacon));
+ pmlmepriv->new_beacon_cnts = 0;
+ } else {
+ RTW_ERR("%s: get beacon keys failed\n", __func__);
+ _rtw_memset(&pmlmepriv->cur_beacon_keys, 0, sizeof(recv_beacon));
+ pmlmepriv->new_beacon_cnts = 0;
+ }
+ }
+ rtw_mfree((u8*)pbss, sizeof(WLAN_BSSID_EX));
+ }
+
+ /* check the vendor of the assoc AP */
+ pmlmeinfo->assoc_AP_vendor =
+ check_assoc_AP(pframe+sizeof(struct rtw_ieee80211_hdr_3addr),
+ (len - sizeof(struct rtw_ieee80211_hdr_3addr)));
+
+ /* update TSF Value */
+ update_TSF(pmlmeext, pframe, len);
+
+ /* reset for adaptive_early_32k */
+ pmlmeext->adaptive_tsf_done = _FALSE;
+ pmlmeext->DrvBcnEarly = 0xff;
+ pmlmeext->DrvBcnTimeOut = 0xff;
+ pmlmeext->bcn_cnt = 0;
+ _rtw_memset(pmlmeext->bcn_delay_cnt, 0, sizeof(pmlmeext->bcn_delay_cnt));
+ _rtw_memset(pmlmeext->bcn_delay_ratio, 0, sizeof(pmlmeext->bcn_delay_ratio));
+
+ pmlmepriv->ft_roam.ft_updated_bcn = _TRUE;
+ }
+}
+
+void rtw_ft_start_clnt_join(_adapter *padapter)
+{
+ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
+ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+ struct ft_roam_info *pft_roam = &(pmlmepriv->ft_roam);
+
+ if (rtw_ft_otd_roam(padapter)) {
+ pmlmeinfo->state = WIFI_FW_AUTH_SUCCESS | WIFI_FW_STATION_STATE;
+ pft_roam->ft_event.ies =
+ (pft_roam->ft_action + sizeof(struct rtw_ieee80211_hdr_3addr) + 16);
+ pft_roam->ft_event.ies_len =
+ (pft_roam->ft_action_len - sizeof(struct rtw_ieee80211_hdr_3addr));
+
+ /*Not support RIC*/
+ pft_roam->ft_event.ric_ies = NULL;
+ pft_roam->ft_event.ric_ies_len = 0;
+ rtw_ft_report_evt(padapter);
+ return;
+ }
+
+ pmlmeinfo->state = WIFI_FW_AUTH_NULL | WIFI_FW_STATION_STATE;
+ start_clnt_auth(padapter);
}
-#endif /* CONFIG_IEEE80211W */
+u8 rtw_ft_update_rsnie(
+ _adapter *padapter, u8 bwrite,
+ struct pkt_attrib *pattrib, u8 **pframe)
+{
+ struct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam);
+ u8 *pie;
+ u32 len;
+
+ pie = rtw_get_ie(pft_roam->updated_ft_ies, EID_WPA2, &len,
+ pft_roam->updated_ft_ies_len);
+
+ if (!bwrite)
+ return (pie)?_SUCCESS:_FAIL;
+
+ if (pie) {
+ *pframe = rtw_set_ie(((u8 *)*pframe), EID_WPA2, len,
+ pie+2, &(pattrib->pktlen));
+ } else
+ return _FAIL;
+
+ return _SUCCESS;
+}
+
+static u8 rtw_ft_update_mdie(
+ _adapter *padapter, struct pkt_attrib *pattrib, u8 **pframe)
+{
+ struct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam);
+ u8 *pie, mdie[3];
+ u32 len = 3;
+
+ if (rtw_ft_roam(padapter)) {
+ if ((pie = rtw_get_ie(pft_roam->updated_ft_ies, _MDIE_,
+ &len, pft_roam->updated_ft_ies_len))) {
+ pie = (pie + 2); /* ignore md-id & length */
+ } else
+ return _FAIL;
+ } else {
+ *((u16 *)&mdie[0]) = pft_roam->mdid;
+ mdie[2] = pft_roam->ft_cap;
+ pie = &mdie[0];
+ }
+
+ *pframe = rtw_set_ie(((u8 *)*pframe), _MDIE_, len , pie, &(pattrib->pktlen));
+ return _SUCCESS;
+}
+
+static u8 rtw_ft_update_ftie(
+ _adapter *padapter, struct pkt_attrib *pattrib, u8 **pframe)
+{
+ struct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam);
+ u8 *pie;
+ u32 len;
+
+ if ((pie = rtw_get_ie(pft_roam->updated_ft_ies, _FTIE_, &len,
+ pft_roam->updated_ft_ies_len)) != NULL) {
+ *pframe = rtw_set_ie(*pframe, _FTIE_, len ,
+ (pie+2), &(pattrib->pktlen));
+ } else
+ return _FAIL;
+
+ return _SUCCESS;
+}
+
+void rtw_ft_build_auth_req_ies(_adapter *padapter,
+ struct pkt_attrib *pattrib, u8 **pframe)
+{
+ u8 ftie_append = _TRUE;
+
+ if (!pattrib || !(*pframe))
+ return;
+
+ if (!rtw_ft_roam(padapter))
+ return;
+
+ ftie_append = rtw_ft_update_rsnie(padapter, _TRUE, pattrib, pframe);
+ rtw_ft_update_mdie(padapter, pattrib, pframe);
+ if (ftie_append)
+ rtw_ft_update_ftie(padapter, pattrib, pframe);
+}
+
+void rtw_ft_build_assoc_req_ies(_adapter *padapter,
+ u8 is_reassoc, struct pkt_attrib *pattrib, u8 **pframe)
+{
+ if (!pattrib || !(*pframe))
+ return;
+
+ if (rtw_ft_chk_flags(padapter, RTW_FT_PEER_EN))
+ rtw_ft_update_mdie(padapter, pattrib, pframe);
+
+ if ((!is_reassoc) || (!rtw_ft_roam(padapter)))
+ return;
+
+ if (rtw_ft_update_rsnie(padapter, _FALSE, pattrib, pframe))
+ rtw_ft_update_ftie(padapter, pattrib, pframe);
+}
+
+u8 rtw_ft_update_auth_rsp_ies(_adapter *padapter, u8 *pframe, u32 len)
+{
+ u8 ret = _SUCCESS;
+ u8 target_ap_addr[ETH_ALEN] = {0};
+ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+ struct ft_roam_info *pft_roam = &(pmlmepriv->ft_roam);
+
+ if (!rtw_ft_roam(padapter))
+ return _FAIL;
+
+ /*rtw_ft_report_reassoc_evt already,
+ * and waiting for cfg80211_rtw_update_ft_ies */
+ if (rtw_ft_authed_sta(padapter))
+ return ret;
+
+ if (!pframe || !len)
+ return _FAIL;
+
+ rtw_buf_update(&pmlmepriv->auth_rsp,
+ &pmlmepriv->auth_rsp_len, pframe, len);
+ pft_roam->ft_event.ies =
+ (pmlmepriv->auth_rsp + sizeof(struct rtw_ieee80211_hdr_3addr) + 6);
+ pft_roam->ft_event.ies_len =
+ (pmlmepriv->auth_rsp_len - sizeof(struct rtw_ieee80211_hdr_3addr) - 6);
+
+ /*Not support RIC*/
+ pft_roam->ft_event.ric_ies = NULL;
+ pft_roam->ft_event.ric_ies_len = 0;
+ _rtw_memcpy(target_ap_addr, pmlmepriv->assoc_bssid, ETH_ALEN);
+ rtw_ft_report_reassoc_evt(padapter, target_ap_addr);
+
+ return ret;
+}
+
+static void rtw_ft_start_clnt_action(_adapter *padapter, u8 *pTargetAddr)
+{
+ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+
+ rtw_ft_set_status(padapter, RTW_FT_REQUESTING_STA);
+ rtw_ft_issue_action_req(padapter, pTargetAddr);
+ _set_timer(&pmlmeext->ft_link_timer, REASSOC_TO);
+}
+
+void rtw_ft_start_roam(_adapter *padapter, u8 *pTargetAddr)
+{
+ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+
+ if (rtw_ft_otd_roam(padapter)) {
+ rtw_ft_start_clnt_action(padapter, pTargetAddr);
+ } else {
+ /*wait a little time to retrieve packets buffered in the current ap while scan*/
+ _set_timer(&pmlmeext->ft_roam_timer, 30);
+ }
+}
+
+void rtw_ft_issue_action_req(_adapter *padapter, u8 *pTargetAddr)
+{
+ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
+ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
+ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+ struct xmit_frame *pmgntframe;
+ struct rtw_ieee80211_hdr *pwlanhdr;
+ struct pkt_attrib *pattrib;
+ u8 *pframe;
+ u8 category = RTW_WLAN_CATEGORY_FT;
+ u8 action = RTW_WLAN_ACTION_FT_REQ;
+
+ pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+ if (pmgntframe == NULL)
+ return;
+
+ pattrib = &pmgntframe->attrib;
+ update_mgntframe_attrib(padapter, pattrib);
+ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+ pwlanhdr->frame_ctl = 0;
+
+ _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
+ _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
+
+ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
+ pmlmeext->mgnt_seq++;
+ set_frame_sub_type(pframe, WIFI_ACTION);
+
+ pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
+ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen));
+ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen));
+
+ _rtw_memcpy(pframe, adapter_mac_addr(padapter), ETH_ALEN);
+ pframe += ETH_ALEN;
+ pattrib->pktlen += ETH_ALEN;
+
+ _rtw_memcpy(pframe, pTargetAddr, ETH_ALEN);
+ pframe += ETH_ALEN;
+ pattrib->pktlen += ETH_ALEN;
+
+ rtw_ft_update_mdie(padapter, pattrib, &pframe);
+ if (rtw_ft_update_rsnie(padapter, _TRUE, pattrib, &pframe))
+ rtw_ft_update_ftie(padapter, pattrib, &pframe);
+
+ pattrib->last_txcmdsz = pattrib->pktlen;
+ dump_mgntframe(padapter, pmgntframe);
+}
+
+void rtw_ft_report_evt(_adapter *padapter)
+{
+ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+ struct ft_roam_info *pft_roam = &(pmlmepriv->ft_roam);
+ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
+ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+ WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)&(pmlmeinfo->network);
+ struct cfg80211_ft_event_params ft_evt_parms;
+ _irqL irqL;
+
+ _rtw_memset(&ft_evt_parms, 0, sizeof(ft_evt_parms));
+ rtw_ft_update_stainfo(padapter, pnetwork);
+
+ if (!pnetwork)
+ goto err_2;
+
+ ft_evt_parms.ies_len = pft_roam->ft_event.ies_len;
+ ft_evt_parms.ies = rtw_zmalloc(ft_evt_parms.ies_len);
+ if (ft_evt_parms.ies)
+ _rtw_memcpy((void *)ft_evt_parms.ies, pft_roam->ft_event.ies, ft_evt_parms.ies_len);
+ else
+ goto err_2;
+
+ ft_evt_parms.target_ap = rtw_zmalloc(ETH_ALEN);
+ if (ft_evt_parms.target_ap)
+ _rtw_memcpy((void *)ft_evt_parms.target_ap, pnetwork->MacAddress, ETH_ALEN);
+ else
+ goto err_1;
+
+ ft_evt_parms.ric_ies = pft_roam->ft_event.ric_ies;
+ ft_evt_parms.ric_ies_len = pft_roam->ft_event.ric_ies_len;
+
+ rtw_ft_lock_set_status(padapter, RTW_FT_AUTHENTICATED_STA, &irqL);
+ rtw_cfg80211_ft_event(padapter, &ft_evt_parms);
+ RTW_INFO("FT: rtw_ft_report_evt\n");
+ rtw_mfree((u8 *)pft_roam->ft_event.target_ap, ETH_ALEN);
+err_1:
+ rtw_mfree((u8 *)ft_evt_parms.ies, ft_evt_parms.ies_len);
+err_2:
+ return;
+}
+
+void rtw_ft_report_reassoc_evt(_adapter *padapter, u8 *pMacAddr)
+{
+ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
+ struct cmd_priv *pcmdpriv = &(padapter->cmdpriv);
+ struct cmd_obj *pcmd_obj = NULL;
+ struct stassoc_event *passoc_sta_evt = NULL;
+ struct C2HEvent_Header *pc2h_evt_hdr = NULL;
+ u8 *pevtcmd = NULL;
+ u32 cmdsz = 0;
+
+ pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+ if (pcmd_obj == NULL)
+ return;
+
+ cmdsz = (sizeof(struct stassoc_event) + sizeof(struct C2HEvent_Header));
+ pevtcmd = (u8 *)rtw_zmalloc(cmdsz);
+ if (pevtcmd == NULL) {
+ rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj));
+ return;
+ }
+
+ _rtw_init_listhead(&pcmd_obj->list);
+ pcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT);
+ pcmd_obj->cmdsz = cmdsz;
+ pcmd_obj->parmbuf = pevtcmd;
+ pcmd_obj->rsp = NULL;
+ pcmd_obj->rspsz = 0;
+
+ pc2h_evt_hdr = (struct C2HEvent_Header *)(pevtcmd);
+ pc2h_evt_hdr->len = sizeof(struct stassoc_event);
+ pc2h_evt_hdr->ID = GEN_EVT_CODE(_FT_REASSOC);
+ pc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq);
+
+ passoc_sta_evt = (struct stassoc_event *)(pevtcmd + sizeof(struct C2HEvent_Header));
+ _rtw_memcpy((unsigned char *)(&(passoc_sta_evt->macaddr)), pMacAddr, ETH_ALEN);
+ rtw_enqueue_cmd(pcmdpriv, pcmd_obj);
+}
+
+void rtw_ft_link_timer_hdl(void *ctx)
+{
+ _adapter *padapter = (_adapter *)ctx;
+ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
+ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+ struct ft_roam_info *pft_roam = &(pmlmepriv->ft_roam);
+
+ if (rtw_ft_chk_status(padapter, RTW_FT_REQUESTING_STA)) {
+ if (pft_roam->ft_req_retry_cnt < RTW_FT_ACTION_REQ_LMT) {
+ pft_roam->ft_req_retry_cnt++;
+ rtw_ft_issue_action_req(padapter, (u8 *)pmlmepriv->roam_network->network.MacAddress);
+ _set_timer(&pmlmeext->ft_link_timer, REASSOC_TO);
+ } else {
+ pft_roam->ft_req_retry_cnt = 0;
+ if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)
+ rtw_ft_set_status(padapter, RTW_FT_ASSOCIATED_STA);
+ else
+ rtw_ft_reset_status(padapter);
+ }
+ }
+}
+
+void rtw_ft_roam_timer_hdl(void *ctx)
+{
+ _adapter *padapter = (_adapter *)ctx;
+ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+
+ receive_disconnect(padapter, pmlmepriv->cur_network.network.MacAddress
+ , WLAN_REASON_ACTIVE_ROAM, _FALSE);
+}
+
+void rtw_ft_roam_status_reset(_adapter *padapter)
+{
+ struct ft_roam_info *pft_roam = &(padapter->mlmepriv.ft_roam);
+
+ if ((rtw_to_roam(padapter) > 0) &&
+ (!rtw_ft_chk_status(padapter, RTW_FT_REQUESTED_STA))) {
+ rtw_ft_reset_status(padapter);
+ }
+
+ padapter->mlmepriv.ft_roam.ft_updated_bcn = _FALSE;
+}
+#endif
+
+u8 NULL_hdl(_adapter *padapter, u8 *pbuf)
+{
+ return H2C_SUCCESS;
+}
+
+#ifdef CONFIG_AUTO_AP_MODE
+void rtw_auto_ap_rx_msg_dump(_adapter *padapter, union recv_frame *precv_frame, u8 *ehdr_pos)
+{
+ struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
+ struct sta_info *psta = precv_frame->u.hdr.psta;
+ struct ethhdr *ehdr = (struct ethhdr *)ehdr_pos;
+
+ RTW_INFO("eth rx: got eth_type=0x%x\n", ntohs(ehdr->h_proto));
+
+ if (psta && psta->isrc && psta->pid > 0) {
+ u16 rx_pid;
+
+ rx_pid = *(u16 *)(ehdr_pos + ETH_HLEN);
+
+ RTW_INFO("eth rx(pid=0x%x): sta("MAC_FMT") pid=0x%x\n",
+ rx_pid, MAC_ARG(psta->cmn.mac_addr), psta->pid);
+
+ if (rx_pid == psta->pid) {
+ int i;
+ u16 len = *(u16 *)(ehdr_pos + ETH_HLEN + 2);
+ /* u16 ctrl_type = *(u16 *)(ehdr_pos + ETH_HLEN + 4); */
+
+ /* RTW_INFO("eth, RC: len=0x%x, ctrl_type=0x%x\n", len, ctrl_type); */
+ RTW_INFO("eth, RC: len=0x%x\n", len);
+
+ for (i = 0; i < len; i++)
+ RTW_INFO("0x%x\n", *(ehdr_pos + ETH_HLEN + 4 + i));
+ /* RTW_INFO("0x%x\n", *(ehdr_pos + ETH_HLEN + 6 + i)); */
+
+ RTW_INFO("eth, RC-end\n");
+ }
+ }
-u8 NULL_hdl(_adapter *padapter, u8 *pbuf)
-{
- return H2C_SUCCESS;
}
-#ifdef CONFIG_AUTO_AP_MODE
void rtw_start_auto_ap(_adapter *adapter)
{
RTW_INFO("%s\n", __FUNCTION__);
rtw_set_802_11_infrastructure_mode(adapter, Ndis802_11APMode);
- rtw_setopmode_cmd(adapter, Ndis802_11APMode, _TRUE);
+ rtw_setopmode_cmd(adapter, Ndis802_11APMode, RTW_CMDF_WAIT_ACK);
}
static int rtw_auto_ap_start_beacon(_adapter *adapter)
@@ -12494,12 +14068,11 @@ u8 setopmode_hdl(_adapter *padapter, u8 *pbuf)
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
struct setopmode_parm *psetop = (struct setopmode_parm *)pbuf;
- if (psetop->mode == Ndis802_11APMode) {
+ if (psetop->mode == Ndis802_11APMode
+ || psetop->mode == Ndis802_11_mesh
+ ) {
pmlmeinfo->state = WIFI_FW_AP_STATE;
type = _HW_STATE_AP_;
-#ifdef CONFIG_NATIVEAP_MLME
- /* start_ap_mode(padapter); */
-#endif
} else if (psetop->mode == Ndis802_11Infrastructure) {
pmlmeinfo->state &= ~(BIT(0) | BIT(1)); /* clear state */
pmlmeinfo->state |= WIFI_FW_STATION_STATE;/* set to STATION_STATE */
@@ -12511,6 +14084,10 @@ u8 setopmode_hdl(_adapter *padapter, u8 *pbuf)
else
type = _HW_STATE_NOLINK_;
+#ifdef CONFIG_AP_PORT_SWAP
+ rtw_hal_set_hwreg(padapter, HW_VAR_PORT_SWITCH, (u8 *)(&type));
+#endif
+
rtw_hal_set_hwreg(padapter, HW_VAR_SET_OPMODE, (u8 *)(&type));
#ifdef CONFIG_AUTO_AP_MODE
@@ -12533,7 +14110,10 @@ u8 setopmode_hdl(_adapter *padapter, u8 *pbuf)
}
#ifdef CONFIG_BT_COEXIST
- if (psetop->mode == Ndis802_11APMode) {
+ if (psetop->mode == Ndis802_11APMode
+ || psetop->mode == Ndis802_11_mesh
+ || psetop->mode == Ndis802_11Monitor
+ ) {
/* Do this after port switch to */
/* prevent from downloading rsvd page to wrong port */
rtw_btcoex_MediaStatusNotify(padapter, 1); /* connect */
@@ -12576,14 +14156,6 @@ u8 createbss_hdl(_adapter *padapter, u8 *pbuf)
pmlmeinfo->agg_enable_bitmap = 0;
pmlmeinfo->candidate_tid_bitmap = 0;
- /* config the initial gain under linking, need to write the BB registers */
- /* initialgain = 0x1E; */
- /*rtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &initialgain, _FALSE);*/
-
- /* disable dynamic functions, such as high power, DIG */
- rtw_phydm_ability_backup(padapter);
- rtw_phydm_func_disable_all(padapter);
-
/* cancel link timer */
_cancel_timer_ex(&pmlmeext->link_timer);
@@ -12723,7 +14295,7 @@ u8 join_cmd_hdl(_adapter *padapter, u8 *pbuf)
}
rtw_bss_get_chbw(pnetwork
- , &pmlmeext->cur_channel, &pmlmeext->cur_bwmode, &pmlmeext->cur_ch_offset);
+ , &pmlmeext->cur_channel, &pmlmeext->cur_bwmode, &pmlmeext->cur_ch_offset, 1, 1);
rtw_adjust_chbw(padapter, pmlmeext->cur_channel, &pmlmeext->cur_bwmode, &pmlmeext->cur_ch_offset);
@@ -12772,6 +14344,8 @@ u8 join_cmd_hdl(_adapter *padapter, u8 *pbuf)
rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmlmeinfo->network.MacAddress);
join_type = 0;
rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));
+ if (MLME_IS_STA(padapter))
+ rtw_hal_rcr_set_chk_bssid(padapter, MLME_STA_CONNECTING);
doiqk = _TRUE;
rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk);
@@ -12825,6 +14399,8 @@ u8 disconnect_hdl(_adapter *padapter, unsigned char *pbuf)
rtw_free_uc_swdec_pending_queue(padapter);
+ rtw_sta_mstatus_report(padapter);
+
return H2C_SUCCESS;
}
@@ -12898,6 +14474,11 @@ u8 rtw_scan_sparse(_adapter *adapter, struct rtw_ieee80211_channel *ch, u8 ch_nu
#ifndef RTW_SCAN_SPARSE_CH_NUM_BG
#define RTW_SCAN_SPARSE_CH_NUM_BG 4
#endif
+#ifdef CONFIG_LAYER2_ROAMING
+#ifndef RTW_SCAN_SPARSE_CH_NUM_ROAMING_ACTIVE
+#define RTW_SCAN_SPARSE_CH_NUM_ROAMING_ACTIVE 1
+#endif
+#endif
#define SCAN_SPARSE_CH_NUM_INVALID 255
@@ -12946,6 +14527,13 @@ u8 rtw_scan_sparse(_adapter *adapter, struct rtw_ieee80211_channel *ch, u8 ch_nu
max_allow_ch = rtw_min(max_allow_ch, RTW_SCAN_SPARSE_CH_NUM_BG);
#endif
+#if defined(CONFIG_LAYER2_ROAMING) && defined(RTW_SCAN_SPARSE_ROAMING_ACTIVE)
+ if (rtw_chk_roam_flags(adapter, RTW_ROAM_ACTIVE)) {
+ if (busy_traffic == _TRUE && adapter->mlmepriv.need_to_roam == _TRUE)
+ max_allow_ch = rtw_min(max_allow_ch, RTW_SCAN_SPARSE_CH_NUM_ROAMING_ACTIVE);
+ }
+#endif
+
if (max_allow_ch != SCAN_SPARSE_CH_NUM_INVALID) {
int i;
@@ -12976,6 +14564,44 @@ u8 rtw_scan_sparse(_adapter *adapter, struct rtw_ieee80211_channel *ch, u8 ch_nu
return ret_num;
}
+#define SCANNING_TIMEOUT_EX 2000
+u32 rtw_scan_timeout_decision(_adapter *padapter)
+{
+ u32 back_op_times= 0;
+ u8 max_chan_num;
+ u16 scan_ms;
+ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+ struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
+ struct ss_res *ss = &pmlmeext->sitesurvey_res;
+
+ if (is_supported_5g(padapter->registrypriv.wireless_mode)
+ && IsSupported24G(padapter->registrypriv.wireless_mode))
+ max_chan_num = MAX_CHANNEL_NUM;/* dual band */
+ else
+ max_chan_num = MAX_CHANNEL_NUM_2G;/*single band*/
+
+ #ifdef CONFIG_SCAN_BACKOP
+ if (rtw_mi_buddy_check_mlmeinfo_state(padapter, WIFI_FW_AP_STATE))
+ back_op_times = (max_chan_num / ss->scan_cnt_max) * ss->backop_ms;
+ #endif
+
+ if (ss->duration)
+ scan_ms = ss->duration;
+ else
+ #if defined(CONFIG_RTW_ACS) && defined(CONFIG_RTW_ACS_DBG)
+ if (IS_ACS_ENABLE(padapter) && rtw_is_acs_st_valid(padapter))
+ scan_ms = rtw_acs_get_adv_st(padapter);
+ else
+ #endif /*CONFIG_RTW_ACS*/
+ scan_ms = ss->scan_ch_ms;
+
+ ss->scan_timeout_ms = (scan_ms * max_chan_num) + back_op_times + SCANNING_TIMEOUT_EX;
+ #ifdef DBG_SITESURVEY
+ RTW_INFO("%s , scan_timeout_ms = %d (ms)\n", __func__, ss->scan_timeout_ms);
+ #endif /*DBG_SITESURVEY*/
+ return ss->scan_timeout_ms;
+}
+
static int rtw_scan_ch_decision(_adapter *padapter, struct rtw_ieee80211_channel *out,
u32 out_num, struct rtw_ieee80211_channel *in, u32 in_num)
{
@@ -12983,7 +14609,7 @@ static int rtw_scan_ch_decision(_adapter *padapter, struct rtw_ieee80211_channel
int scan_ch_num = 0;
int set_idx;
u8 chan;
- struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
/* clear first */
_rtw_memset(out, 0, sizeof(struct rtw_ieee80211_channel) * out_num);
@@ -12995,11 +14621,13 @@ static int rtw_scan_ch_decision(_adapter *padapter, struct rtw_ieee80211_channel
if (0)
RTW_INFO(FUNC_ADPT_FMT" "CHAN_FMT"\n", FUNC_ADPT_ARG(padapter), CHAN_ARG(&in[i]));
- set_idx = rtw_ch_set_search_ch(pmlmeext->channel_set, in[i].hw_value);
- if (in[i].hw_value && !(in[i].flags & RTW_IEEE80211_CHAN_DISABLED)
- && set_idx >= 0
- && rtw_mlme_band_check(padapter, in[i].hw_value) == _TRUE
- ) {
+ if (!in[i].hw_value || (in[i].flags & RTW_IEEE80211_CHAN_DISABLED))
+ continue;
+ if (rtw_mlme_band_check(padapter, in[i].hw_value) == _FALSE)
+ continue;
+
+ set_idx = rtw_chset_search_ch(rfctl->channel_set, in[i].hw_value);
+ if (set_idx >= 0) {
if (j >= out_num) {
RTW_PRINT(FUNC_ADPT_FMT" out_num:%u not enough\n",
FUNC_ADPT_ARG(padapter), out_num);
@@ -13008,7 +14636,7 @@ static int rtw_scan_ch_decision(_adapter *padapter, struct rtw_ieee80211_channel
_rtw_memcpy(&out[j], &in[i], sizeof(struct rtw_ieee80211_channel));
- if (pmlmeext->channel_set[set_idx].ScanType == SCAN_PASSIVE)
+ if (rfctl->channel_set[set_idx].ScanType == SCAN_PASSIVE)
out[j].flags |= RTW_IEEE80211_CHAN_PASSIVE_SCAN;
j++;
@@ -13019,8 +14647,8 @@ static int rtw_scan_ch_decision(_adapter *padapter, struct rtw_ieee80211_channel
/* if out is empty, use channel_set as default */
if (j == 0) {
- for (i = 0; i < pmlmeext->max_chan_nums; i++) {
- chan = pmlmeext->channel_set[i].ChannelNum;
+ for (i = 0; i < rfctl->max_chan_nums; i++) {
+ chan = rfctl->channel_set[i].ChannelNum;
if (rtw_mlme_band_check(padapter, chan) == _TRUE) {
if (rtw_mlme_ignore_chan(padapter, chan) == _TRUE)
continue;
@@ -13036,7 +14664,7 @@ static int rtw_scan_ch_decision(_adapter *padapter, struct rtw_ieee80211_channel
out[j].hw_value = chan;
- if (pmlmeext->channel_set[i].ScanType == SCAN_PASSIVE)
+ if (rfctl->channel_set[i].ScanType == SCAN_PASSIVE)
out[j].flags |= RTW_IEEE80211_CHAN_PASSIVE_SCAN;
j++;
@@ -13053,21 +14681,28 @@ static int rtw_scan_ch_decision(_adapter *padapter, struct rtw_ieee80211_channel
static void sitesurvey_res_reset(_adapter *adapter, struct sitesurvey_parm *parm)
{
struct ss_res *ss = &adapter->mlmeextpriv.sitesurvey_res;
+ RT_CHANNEL_INFO *chset = adapter_to_chset(adapter);
int i;
ss->bss_cnt = 0;
ss->channel_idx = 0;
+#ifdef CONFIG_DFS
+ ss->dfs_ch_ssid_scan = 0;
+#endif
+ ss->igi_scan = 0;
+ ss->igi_before_scan = 0;
#ifdef CONFIG_SCAN_BACKOP
ss->scan_cnt = 0;
#endif
#if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL)
ss->is_sw_antdiv_bl_scan = 0;
#endif
-
+ ss->ssid_num = 0;
for (i = 0; i < RTW_SSID_SCAN_AMOUNT; i++) {
if (parm->ssid[i].SsidLength) {
_rtw_memcpy(ss->ssid[i].Ssid, parm->ssid[i].Ssid, IW_ESSID_MAX_SIZE);
ss->ssid[i].SsidLength = parm->ssid[i].SsidLength;
+ ss->ssid_num++;
} else
ss->ssid[i].SsidLength = 0;
}
@@ -13077,7 +14712,17 @@ static void sitesurvey_res_reset(_adapter *adapter, struct sitesurvey_parm *parm
, parm->ch, parm->ch_num
);
+#ifdef CONFIG_DFS
+ for (i = 0; i < MAX_CHANNEL_NUM; i++)
+ chset[i].hidden_bss_cnt = 0;
+#endif
+
+ ss->bw = parm->bw;
+ ss->igi = parm->igi;
+ ss->token = parm->token;
+ ss->duration = parm->duration;
ss->scan_mode = parm->scan_mode;
+ ss->token = parm->token;
}
static u8 sitesurvey_pick_ch_behavior(_adapter *padapter, u8 *ch, RT_SCAN_TYPE *type)
@@ -13088,7 +14733,8 @@ static u8 sitesurvey_pick_ch_behavior(_adapter *padapter, u8 *ch, RT_SCAN_TYPE *
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
struct ss_res *ss = &pmlmeext->sitesurvey_res;
-
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
+ int ch_set_idx;
#ifdef CONFIG_P2P
struct wifidirect_info *pwdinfo = &padapter->wdinfo;
#endif
@@ -13108,12 +14754,10 @@ static u8 sitesurvey_pick_ch_behavior(_adapter *padapter, u8 *ch, RT_SCAN_TYPE *
* Commented by Albert 2011/06/03
* The driver is in the find phase, it should go through the social channel.
*/
- int ch_set_idx;
-
scan_ch = pwdinfo->social_chan[ss->channel_idx];
- ch_set_idx = rtw_ch_set_search_ch(pmlmeext->channel_set, scan_ch);
+ ch_set_idx = rtw_chset_search_ch(rfctl->channel_set, scan_ch);
if (ch_set_idx >= 0)
- scan_type = pmlmeext->channel_set[ch_set_idx].ScanType;
+ scan_type = rfctl->channel_set[ch_set_idx].ScanType;
else
scan_type = SCAN_ACTIVE;
} else
@@ -13121,10 +14765,30 @@ static u8 sitesurvey_pick_ch_behavior(_adapter *padapter, u8 *ch, RT_SCAN_TYPE *
{
struct rtw_ieee80211_channel *ch;
+#ifdef CONFIG_DFS
+ if (ss->channel_idx != 0 && ss->dfs_ch_ssid_scan == 0
+ && pmlmeext->sitesurvey_res.ssid_num
+ && rtw_is_dfs_ch(ss->ch[ss->channel_idx - 1].hw_value)
+ ) {
+ ch_set_idx = rtw_chset_search_ch(rfctl->channel_set, ss->ch[ss->channel_idx - 1].hw_value);
+ if (ch_set_idx != -1 && rfctl->channel_set[ch_set_idx].hidden_bss_cnt) {
+ ss->channel_idx--;
+ ss->dfs_ch_ssid_scan = 1;
+ }
+ } else
+ ss->dfs_ch_ssid_scan = 0;
+#endif /* CONFIG_DFS */
+
if (ss->channel_idx < ss->ch_num) {
ch = &ss->ch[ss->channel_idx];
scan_ch = ch->hw_value;
- scan_type = (ch->flags & RTW_IEEE80211_CHAN_PASSIVE_SCAN) ? SCAN_PASSIVE : SCAN_ACTIVE;
+
+ #if defined(CONFIG_RTW_ACS) && defined(CONFIG_RTW_ACS_DBG)
+ if (IS_ACS_ENABLE(padapter) && rtw_is_acs_passiv_scan(padapter))
+ scan_type = SCAN_PASSIVE;
+ else
+ #endif /*CONFIG_RTW_ACS*/
+ scan_type = (ch->flags & RTW_IEEE80211_CHAN_PASSIVE_SCAN) ? SCAN_PASSIVE : SCAN_ACTIVE;
}
}
@@ -13132,22 +14796,17 @@ static u8 sitesurvey_pick_ch_behavior(_adapter *padapter, u8 *ch, RT_SCAN_TYPE *
next_state = SCAN_PROCESS;
#ifdef CONFIG_SCAN_BACKOP
{
- u8 sta_num;
- u8 ld_sta_num;
- u8 ap_num;
- u8 ld_ap_num;
+ struct mi_state mstate;
u8 backop_flags = 0;
- rtw_mi_status(padapter, &sta_num, &ld_sta_num, NULL, &ap_num, &ld_ap_num, NULL);
+ rtw_mi_status(padapter, &mstate);
- if ((ld_sta_num > 0 && mlmeext_chk_scan_backop_flags_sta(pmlmeext, SS_BACKOP_EN))
- || (sta_num > 0 && mlmeext_chk_scan_backop_flags_sta(pmlmeext, SS_BACKOP_EN_NL))
- )
+ if ((MSTATE_STA_LD_NUM(&mstate) && mlmeext_chk_scan_backop_flags_sta(pmlmeext, SS_BACKOP_EN))
+ || (MSTATE_STA_NUM(&mstate) && mlmeext_chk_scan_backop_flags_sta(pmlmeext, SS_BACKOP_EN_NL)))
backop_flags |= mlmeext_scan_backop_flags_sta(pmlmeext);
- if ((ld_ap_num > 0 && mlmeext_chk_scan_backop_flags_ap(pmlmeext, SS_BACKOP_EN))
- || (ap_num > 0 && mlmeext_chk_scan_backop_flags_ap(pmlmeext, SS_BACKOP_EN_NL))
- )
+ if ((MSTATE_AP_LD_NUM(&mstate) && mlmeext_chk_scan_backop_flags_ap(pmlmeext, SS_BACKOP_EN))
+ || (MSTATE_AP_NUM(&mstate) && mlmeext_chk_scan_backop_flags_ap(pmlmeext, SS_BACKOP_EN_NL)))
backop_flags |= mlmeext_scan_backop_flags_ap(pmlmeext);
if (backop_flags) {
@@ -13220,6 +14879,8 @@ void site_survey(_adapter *padapter, u8 survey_channel, RT_SCAN_TYPE ScanType)
{
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+ struct ss_res *ss = &pmlmeext->sitesurvey_res;
+ u8 ssid_scan = 0;
#ifdef CONFIG_P2P
struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
@@ -13228,43 +14889,26 @@ void site_survey(_adapter *padapter, u8 survey_channel, RT_SCAN_TYPE ScanType)
if (survey_channel != 0) {
set_channel_bwmode(padapter, survey_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
-#ifdef CONFIG_AUTO_CHNL_SEL_NHM
- if (ACS_ENABLE == GET_ACS_STATE(padapter)) {
- ACS_OP acs_op = ACS_RESET;
-
- rtw_hal_set_odm_var(padapter, HAL_ODM_AUTO_CHNL_SEL, &acs_op, _TRUE);
- rtw_set_acs_channel(padapter, survey_channel);
-#ifdef DBG_AUTO_CHNL_SEL_NHM
- RTW_INFO("[ACS-"ADPT_FMT"]-set ch:%u\n",
- ADPT_ARG(padapter), rtw_get_acs_channel(padapter));
-#endif
- }
+#ifdef CONFIG_DFS
+ if (ScanType == SCAN_PASSIVE && ss->dfs_ch_ssid_scan)
+ ssid_scan = 1;
+ else
#endif
-
if (ScanType == SCAN_ACTIVE) {
#ifdef CONFIG_P2P
- if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN) ||
- rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH)
- ) {
+ #ifdef CONFIG_IOCTL_CFG80211
+ if (rtw_cfg80211_is_p2p_scan(padapter))
+ #else
+ if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN)
+ || rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH))
+ #endif
+ {
issue_probereq_p2p(padapter, NULL);
issue_probereq_p2p(padapter, NULL);
issue_probereq_p2p(padapter, NULL);
} else
#endif /* CONFIG_P2P */
{
- int i;
-
- for (i = 0; i < RTW_SSID_SCAN_AMOUNT; i++) {
- if (pmlmeext->sitesurvey_res.ssid[i].SsidLength) {
- /* IOT issue, When wifi_spec is not set, send one probe req without WPS IE. */
- if (padapter->registrypriv.wifi_spec)
- issue_probereq(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL);
- else
- issue_probereq_ex(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL, 0, 0, 0, 0);
- issue_probereq(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL);
- }
- }
-
if (pmlmeext->sitesurvey_res.scan_mode == SCAN_ACTIVE) {
/* IOT issue, When wifi_spec is not set, send one probe req without WPS IE. */
if (padapter->registrypriv.wifi_spec)
@@ -13273,6 +14917,23 @@ void site_survey(_adapter *padapter, u8 survey_channel, RT_SCAN_TYPE ScanType)
issue_probereq_ex(padapter, NULL, NULL, 0, 0, 0, 0);
issue_probereq(padapter, NULL, NULL);
}
+
+ ssid_scan = 1;
+ }
+ }
+
+ if (ssid_scan) {
+ int i;
+
+ for (i = 0; i < RTW_SSID_SCAN_AMOUNT; i++) {
+ if (pmlmeext->sitesurvey_res.ssid[i].SsidLength) {
+ /* IOT issue, When wifi_spec is not set, send one probe req without WPS IE. */
+ if (padapter->registrypriv.wifi_spec)
+ issue_probereq(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL);
+ else
+ issue_probereq_ex(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL, 0, 0, 0, 0);
+ issue_probereq(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL);
+ }
}
}
} else {
@@ -13344,85 +15005,161 @@ void survey_done_set_ch_bw(_adapter *padapter)
set_channel_bwmode(padapter, cur_channel, cur_ch_offset, cur_bwmode);
}
-#if 1
-/**
- * sitesurvey_ps_annc - check and doing ps announcement for all the adapters of given @dvobj
- * @padapter
- * @ps: power saving or not
- *
- * Returns: 0: no ps announcement is doing. 1: ps announcement is doing
- */
-
-u8 sitesurvey_ps_annc(_adapter *padapter, bool ps)
-{
- u8 ps_anc = 0;
-
- if (rtw_mi_issue_nulldata(padapter, NULL, ps, 3, 500))
- ps_anc = 1;
- return ps_anc;
-}
-#else
/**
- * sitesurvey_ps_annc - check and doing ps announcement for all the adapters of given @dvobj
- * @dvobj: the dvobj to check
+ * rtw_ps_annc - check and doing ps announcement for all the adapters
+ * @adapter: the requesting adapter
* @ps: power saving or not
*
* Returns: 0: no ps announcement is doing. 1: ps announcement is doing
*/
-
-u8 sitesurvey_ps_annc(struct dvobj_priv *dvobj, bool ps)
+u8 rtw_ps_annc(_adapter *adapter, bool ps)
{
- _adapter *adapter;
+ struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+ _adapter *iface;
int i;
u8 ps_anc = 0;
for (i = 0; i < dvobj->iface_nums; i++) {
- adapter = dvobj->padapters[i];
- if (!adapter)
+ iface = dvobj->padapters[i];
+ if (!iface)
continue;
- if (ps) {
- if (is_client_associated_to_ap(adapter) == _TRUE) {
+ if (MLME_IS_STA(iface)) {
+ if (is_client_associated_to_ap(iface) == _TRUE) {
/* TODO: TDLS peers */
- issue_nulldata(adapter, NULL, 1, 3, 500);
+ #ifdef CONFIG_MCC_MODE
+ /* for two station case */
+ if (MCC_EN(adapter) && rtw_hal_check_mcc_status(adapter, MCC_STATUS_NEED_MCC)) {
+ u8 ch = iface->mlmeextpriv.cur_channel;
+ u8 offset = iface->mlmeextpriv.cur_ch_offset;
+ u8 bw = iface->mlmeextpriv.cur_bwmode;
+
+ set_channel_bwmode(iface, ch, offset, bw);
+ }
+ #endif /* CONFIG_MCC_MODE */
+ issue_nulldata(iface, NULL, ps, 3, 500);
ps_anc = 1;
}
- } else {
- if (is_client_associated_to_ap(adapter) == _TRUE) {
- /* TODO: TDLS peers */
- issue_nulldata(adapter, NULL, 0, 3, 500);
+ #ifdef CONFIG_RTW_MESH
+ } else if (MLME_IS_MESH(iface)) {
+ if (rtw_mesh_ps_annc(iface, ps))
ps_anc = 1;
- }
+ #endif
}
}
return ps_anc;
}
+
+void rtw_leave_opch(_adapter *adapter)
+{
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+
+#ifdef CONFIG_MCC_MODE
+ if (MCC_EN(adapter) && rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC))
+ return;
+#endif
+
+ _enter_critical_mutex(&rfctl->offch_mutex, NULL);
+
+ if (rfctl->offch_state == OFFCHS_NONE) {
+ /* prepare to leave operating channel */
+ rfctl->offch_state = OFFCHS_LEAVING_OP;
+
+ /* clear HW TX queue */
+ rtw_hal_set_hwreg(adapter, HW_VAR_CHECK_TXBUF, 0);
+
+ rtw_hal_macid_sleep_all_used(adapter);
+
+ rtw_ps_annc(adapter, 1);
+
+ rfctl->offch_state = OFFCHS_LEAVE_OP;
+ }
+
+ _exit_critical_mutex(&rfctl->offch_mutex, NULL);
+}
+
+void rtw_back_opch(_adapter *adapter)
+{
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+
+#ifdef CONFIG_MCC_MODE
+ if (MCC_EN(adapter) && rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC))
+ return;
#endif
-void sitesurvey_set_igi(_adapter *adapter, bool enter)
+ _enter_critical_mutex(&rfctl->offch_mutex, NULL);
+
+ if (rfctl->offch_state != OFFCHS_NONE) {
+ rfctl->offch_state = OFFCHS_BACKING_OP;
+ rtw_hal_macid_wakeup_all_used(adapter);
+ rtw_ps_annc(adapter, 0);
+
+ rfctl->offch_state = OFFCHS_NONE;
+ rtw_mi_os_xmit_schedule(adapter);
+ }
+
+ _exit_critical_mutex(&rfctl->offch_mutex, NULL);
+}
+
+void sitesurvey_set_igi(_adapter *adapter)
{
+ struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
+ struct ss_res *ss = &mlmeext->sitesurvey_res;
u8 igi;
#ifdef CONFIG_P2P
struct wifidirect_info *pwdinfo = &adapter->wdinfo;
#endif
- if (enter) {
-#ifdef CONFIG_P2P
-#ifdef CONFIG_IOCTL_CFG80211
- if (adapter_wdev_data(adapter)->p2p_enabled == _TRUE && pwdinfo->driver_interface == DRIVER_CFG80211)
+ switch (mlmeext_scan_state(mlmeext)) {
+ case SCAN_ENTER:
+ #ifdef CONFIG_P2P
+ #ifdef CONFIG_IOCTL_CFG80211
+ if (pwdinfo->driver_interface == DRIVER_CFG80211 && rtw_cfg80211_is_p2p_scan(adapter))
igi = 0x30;
else
-#endif /* CONFIG_IOCTL_CFG80211 */
- if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
- igi = 0x28;
- else
-#endif /* CONFIG_P2P */
- igi = 0x1e;
- } else {
- igi = 0xff; /* restore RX GAIN */
- }
+ #endif /* CONFIG_IOCTL_CFG80211 */
+ if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
+ igi = 0x28;
+ else
+ #endif /* CONFIG_P2P */
+
+ if (ss->igi)
+ igi = ss->igi;
+ else
+ #if defined(CONFIG_RTW_ACS) && defined(CONFIG_RTW_ACS_DBG)
+ if (IS_ACS_ENABLE(adapter) && rtw_is_acs_igi_valid(adapter))
+ igi = rtw_acs_get_adv_igi(adapter);
+ else
+ #endif /*CONFIG_RTW_ACS*/
+ igi = 0x1e;
- rtw_hal_set_odm_var(adapter, HAL_ODM_INITIAL_GAIN, &igi, _FALSE);
+ /* record IGI status */
+ ss->igi_scan = igi;
+ rtw_hal_get_odm_var(adapter, HAL_ODM_INITIAL_GAIN, &ss->igi_before_scan, NULL);
+
+ /* disable DIG and set IGI for scan */
+ rtw_hal_set_odm_var(adapter, HAL_ODM_INITIAL_GAIN, &igi, _FALSE);
+ break;
+ case SCAN_COMPLETE:
+ case SCAN_TO_P2P_LISTEN:
+ /* enable DIG and restore IGI */
+ igi = 0xff;
+ rtw_hal_set_odm_var(adapter, HAL_ODM_INITIAL_GAIN, &igi, _FALSE);
+ break;
+#ifdef CONFIG_SCAN_BACKOP
+ case SCAN_BACKING_OP:
+ /* write IGI for op channel when DIG is not enabled */
+ odm_write_dig(adapter_to_phydm(adapter), ss->igi_before_scan);
+ break;
+ case SCAN_LEAVE_OP:
+ /* write IGI for scan when DIG is not enabled */
+ odm_write_dig(adapter_to_phydm(adapter), ss->igi_scan);
+ break;
+#endif /* CONFIG_SCAN_BACKOP */
+ default:
+ rtw_warn_on(1);
+ break;
+ }
}
void sitesurvey_set_msr(_adapter *adapter, bool enter)
{
@@ -13445,6 +15182,37 @@ void sitesurvey_set_msr(_adapter *adapter, bool enter)
}
Set_MSR(adapter, network_type);
}
+
+void sitesurvey_set_offch_state(_adapter *adapter, u8 scan_state)
+{
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+
+ _enter_critical_mutex(&rfctl->offch_mutex, NULL);
+
+ switch (scan_state) {
+ case SCAN_DISABLE:
+ case SCAN_BACK_OP:
+ rfctl->offch_state = OFFCHS_NONE;
+ break;
+ case SCAN_START:
+ case SCAN_LEAVING_OP:
+ rfctl->offch_state = OFFCHS_LEAVING_OP;
+ break;
+ case SCAN_ENTER:
+ case SCAN_LEAVE_OP:
+ rfctl->offch_state = OFFCHS_LEAVE_OP;
+ break;
+ case SCAN_COMPLETE:
+ case SCAN_BACKING_OP:
+ rfctl->offch_state = OFFCHS_BACKING_OP;
+ break;
+ default:
+ break;
+ }
+
+ _exit_critical_mutex(&rfctl->offch_mutex, NULL);
+}
+
u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf)
{
struct sitesurvey_parm *pparm = (struct sitesurvey_parm *)pbuf;
@@ -13497,15 +15265,16 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf)
/* apply rx ampdu setting */
if (ss->rx_ampdu_accept != RX_AMPDU_ACCEPT_INVALID
- || ss->rx_ampdu_size != RX_AMPDU_SIZE_INVALID
- )
+ || ss->rx_ampdu_size != RX_AMPDU_SIZE_INVALID)
rtw_rx_ampdu_apply(padapter);
/* clear HW TX queue before scan */
rtw_hal_set_hwreg(padapter, HW_VAR_CHECK_TXBUF, 0);
+ rtw_hal_macid_sleep_all_used(padapter);
+
/* power save state announcement */
- if (sitesurvey_ps_annc(padapter, 1)) {
+ if (rtw_ps_annc(padapter, 1)) {
mlmeext_set_scan_state(pmlmeext, SCAN_PS_ANNC_WAIT);
mlmeext_set_scan_next_state(pmlmeext, SCAN_ENTER);
set_survey_timer(pmlmeext, 50); /* delay 50ms to protect nulldata(1) */
@@ -13521,11 +15290,11 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf)
* HW register and DM setting for enter scan
*/
- /* config the initial gain under scanning */
- sitesurvey_set_igi(padapter, 1);
-
- /* disable dynamic functions, such as high power, DIG */
rtw_phydm_ability_backup(padapter);
+
+ sitesurvey_set_igi(padapter);
+
+ /* config dynamic functions for off channel */
rtw_phydm_func_for_offchannel(padapter);
/* set MSR to no link state */
sitesurvey_set_msr(padapter, _TRUE);
@@ -13542,32 +15311,21 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf)
u8 next_state;
u32 scan_ms;
-#ifdef CONFIG_AUTO_CHNL_SEL_NHM
- if ((ACS_ENABLE == GET_ACS_STATE(padapter)) && (0 != rtw_get_acs_channel(padapter))) {
- ACS_OP acs_op = ACS_SELECT;
-
- rtw_hal_set_odm_var(padapter, HAL_ODM_AUTO_CHNL_SEL, &acs_op, _TRUE);
- }
+#ifdef CONFIG_RTW_ACS
+ if (IS_ACS_ENABLE(padapter))
+ rtw_acs_get_rst(padapter);
#endif
next_state = sitesurvey_pick_ch_behavior(padapter, &scan_ch, &scan_type);
- if (next_state != SCAN_PROCESS) {
-#ifdef CONFIG_AUTO_CHNL_SEL_NHM
- if (ACS_ENABLE == GET_ACS_STATE(padapter)) {
- rtw_set_acs_channel(padapter, 0);
-#ifdef DBG_AUTO_CHNL_SEL_NHM
- RTW_INFO("[ACS-"ADPT_FMT"]-set ch:%u\n", ADPT_ARG(padapter), rtw_get_acs_channel(padapter));
-#endif
- }
-#endif
+ if (next_state != SCAN_PROCESS) {
mlmeext_set_scan_state(pmlmeext, next_state);
goto operation_by_state;
}
/* still SCAN_PROCESS state */
- if (0)
-#ifdef CONFIG_P2P
+ #ifdef DBG_SITESURVEY
+ #ifdef CONFIG_P2P
RTW_INFO(FUNC_ADPT_FMT" %s ch:%u (cnt:%u,idx:%d) at %dms, %c%c%c\n"
, FUNC_ADPT_ARG(padapter)
, mlmeext_scan_state_str(pmlmeext)
@@ -13577,7 +15335,7 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf)
, scan_type ? 'A' : 'P', ss->scan_mode ? 'A' : 'P'
, ss->ssid[0].SsidLength ? 'S' : ' '
);
-#else
+ #else
RTW_INFO(FUNC_ADPT_FMT" %s ch:%u (idx:%d) at %dms, %c%c%c\n"
, FUNC_ADPT_ARG(padapter)
, mlmeext_scan_state_str(pmlmeext)
@@ -13587,8 +15345,8 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf)
, scan_type ? 'A' : 'P', ss->scan_mode ? 'A' : 'P'
, ss->ssid[0].SsidLength ? 'S' : ' '
);
-#endif /* CONFIG_P2P */
-
+ #endif /* CONFIG_P2P */
+ #endif /*DBG_SITESURVEY*/
#ifdef DBG_FIXED_CHAN
if (pmlmeext->fixed_chan != 0xff)
RTW_INFO(FUNC_ADPT_FMT" fixed_chan:%u\n", pmlmeext->fixed_chan);
@@ -13602,7 +15360,12 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf)
else
scan_ms = 40;
#else
- scan_ms = ss->scan_ch_ms;
+ #if defined(CONFIG_RTW_ACS) && defined(CONFIG_RTW_ACS_DBG)
+ if (IS_ACS_ENABLE(padapter) && rtw_is_acs_st_valid(padapter))
+ scan_ms = rtw_acs_get_adv_st(padapter);
+ else
+ #endif /*CONFIG_RTW_ACS*/
+ scan_ms = ss->scan_ch_ms;
#endif
#if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL)
@@ -13610,18 +15373,19 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf)
scan_ms = scan_ms / 2;
#endif
-#if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR)
- {
- struct noise_info info;
-
- info.bPauseDIG = _FALSE;
- info.IGIValue = 0;
- info.max_time = scan_ms / 2;
- info.chan = scan_ch;
- rtw_hal_set_odm_var(padapter, HAL_ODM_NOISE_MONITOR, &info, _FALSE);
+#ifdef CONFIG_RTW_ACS
+ if (IS_ACS_ENABLE(padapter)) {
+ if (pparm->token)
+ rtw_acs_trigger(padapter, scan_ms, scan_ch, NHM_PID_IEEE_11K_HIGH);
+ else
+ rtw_acs_trigger(padapter, scan_ms, scan_ch, NHM_PID_ACS);
}
#endif
+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
+ if (IS_NM_ENABLE(padapter))
+ rtw_noise_measure(padapter, scan_ch, _FALSE, 0, scan_ms / 2);
+#endif
set_survey_timer(pmlmeext, scan_ms);
break;
}
@@ -13641,14 +15405,14 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf)
rtw_warn_on(1);
}
- if (0)
+ #ifdef DBG_SITESURVEY
RTW_INFO(FUNC_ADPT_FMT" %s ch:%u, bw:%u, offset:%u at %dms\n"
, FUNC_ADPT_ARG(padapter)
, mlmeext_scan_state_str(pmlmeext)
, back_ch, back_bw, back_ch_offset
, rtw_get_passing_time_ms(padapter->mlmepriv.scan_start_time)
);
-
+ #endif /*DBG_SITESURVEY*/
set_channel_bwmode(padapter, back_ch, back_ch_offset, back_bw);
sitesurvey_set_msr(padapter, _FALSE);
@@ -13657,8 +15421,9 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf)
rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
if (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_PS_ANNC)) {
- sitesurvey_set_igi(padapter, 0);
- sitesurvey_ps_annc(padapter, 0);
+ sitesurvey_set_igi(padapter);
+ rtw_hal_macid_wakeup_all_used(padapter);
+ rtw_ps_annc(padapter, 0);
}
mlmeext_set_scan_state(pmlmeext, SCAN_BACK_OP);
@@ -13683,15 +15448,16 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf)
case SCAN_LEAVING_OP:
/*
- * prepare to leave operating channel
- */
+ * prepare to leave operating channel
+ */
/* clear HW TX queue before scan */
rtw_hal_set_hwreg(padapter, HW_VAR_CHECK_TXBUF, 0);
+ rtw_hal_macid_sleep_all_used(padapter);
if (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_PS_ANNC)
- && sitesurvey_ps_annc(padapter, 1)
- ) {
+ && rtw_ps_annc(padapter, 1)
+ ) {
mlmeext_set_scan_state(pmlmeext, SCAN_PS_ANNC_WAIT);
mlmeext_set_scan_next_state(pmlmeext, SCAN_LEAVE_OP);
set_survey_timer(pmlmeext, 50); /* delay 50ms to protect nulldata(1) */
@@ -13707,10 +15473,8 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf)
* HW register and DM setting for enter scan
*/
- if (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_PS_ANNC)) {
- /* config the initial gain under scanning */
- sitesurvey_set_igi(padapter, 1);
- }
+ if (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_PS_ANNC))
+ sitesurvey_set_igi(padapter);
sitesurvey_set_msr(padapter, _TRUE);
@@ -13750,7 +15514,7 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf)
/* turn on phy-dynamic functions */
rtw_phydm_ability_restore(padapter);
- sitesurvey_set_igi(padapter, 0);
+ sitesurvey_set_igi(padapter);
mlmeext_set_scan_state(pmlmeext, SCAN_P2P_LISTEN);
_set_timer(&pwdinfo->find_phase_timer, (u32)((u32)pwdinfo->listen_dwell * 100));
@@ -13790,13 +15554,16 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf)
/* turn on phy-dynamic functions */
rtw_phydm_ability_restore(padapter);
- sitesurvey_set_igi(padapter, 0);
+ sitesurvey_set_igi(padapter);
#ifdef CONFIG_MCC_MODE
/* start MCC fail, then tx null data */
if (!rtw_hal_set_mcc_setting_scan_complete(padapter))
-#endif /* CONFIG_MCC_MODE */
- sitesurvey_ps_annc(padapter, 0);
+#endif
+ {
+ rtw_hal_macid_wakeup_all_used(padapter);
+ rtw_ps_annc(padapter, 0);
+ }
/* apply rx ampdu setting */
rtw_rx_ampdu_apply(padapter);
@@ -13804,10 +15571,25 @@ u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf)
mlmeext_set_scan_state(pmlmeext, SCAN_DISABLE);
report_surveydone_event(padapter);
+#ifdef CONFIG_RTW_ACS
+ if (IS_ACS_ENABLE(padapter))
+ rtw_acs_select_best_chan(padapter);
+#endif
+#if defined(CONFIG_BACKGROUND_NOISE_MONITOR) && defined(DBG_NOISE_MONITOR)
+ if (IS_NM_ENABLE(padapter))
+ rtw_noise_info_dump(RTW_DBGDUMP, padapter);
+#endif
issue_action_BSSCoexistPacket(padapter);
issue_action_BSSCoexistPacket(padapter);
issue_action_BSSCoexistPacket(padapter);
+
+#ifdef CONFIG_RTW_80211K
+ if (ss->token)
+ rm_post_event(padapter, ss->token, RM_EV_survey_done);
+#endif /* CONFIG_RTW_80211K */
+
+ break;
}
return H2C_SUCCESS;
@@ -13859,23 +15641,26 @@ u8 setkey_hdl(_adapter *padapter, u8 *pbuf)
cam_id = rtw_iface_bcmc_id_get(padapter);
else
#endif
- cam_id = rtw_camid_alloc(padapter, NULL, pparm->keyid, &used);
+ cam_id = rtw_camid_alloc(padapter, NULL, pparm->keyid, 1, &used);
if (cam_id < 0)
goto enable_mc;
#ifndef CONFIG_CONCURRENT_MODE
- if (cam_id >= 0 && cam_id <= 3)
+ if (cam_id >= 0 && cam_id <= 3) {
+ /* default key camid */
addr = null_addr;
- else
+ } else
#endif
{
- if (((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE))
- /* for AP mode ,we will force sec cam entry_id so hw dont search cam when tx*/
+ /* not default key camid */
+ if (((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE)) {
+ /* group TX, force sec cam entry_id */
addr = adapter_mac_addr(padapter);
- else
- /* not default key, searched by A2 */
+ } else {
+ /* group RX, searched by A2 (TA) */
addr = get_bssid(&padapter->mlmepriv);
+ }
}
/* cam entry searched is pairwise key */
@@ -13942,6 +15727,7 @@ u8 setkey_hdl(_adapter *padapter, u8 *pbuf)
_rtw_camctl_chk_cap(padapter, SEC_CAP_CHK_BMC)) {
struct set_stakey_parm sta_pparm;
+ _rtw_memset(&sta_pparm, 0, sizeof(struct set_stakey_parm));
sta_pparm.algorithm = pparm->algorithm;
sta_pparm.keyid = pparm->keyid;
_rtw_memcpy(sta_pparm.key, pparm->key, 16);
@@ -13969,11 +15755,12 @@ void rtw_ap_wep_pk_setting(_adapter *adapter, struct sta_info *psta)
if ((psecuritypriv->key_mask & BIT(keyid)) && (keyid == psecuritypriv->dot11PrivacyKeyIndex)) {
sta_pparm.algorithm = psecuritypriv->dot11PrivacyAlgrthm;
sta_pparm.keyid = keyid;
+ sta_pparm.gk = 0;
_rtw_memcpy(sta_pparm.key, &(psecuritypriv->dot11DefKey[keyid].skey[0]), 16);
- _rtw_memcpy(sta_pparm.addr, psta->hwaddr, ETH_ALEN);
+ _rtw_memcpy(sta_pparm.addr, psta->cmn.mac_addr, ETH_ALEN);
RTW_PRINT(FUNC_ADPT_FMT"set WEP - PK with "MAC_FMT" keyid:%u\n"
- , FUNC_ADPT_ARG(adapter), MAC_ARG(psta->hwaddr), keyid);
+ , FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr), keyid);
set_stakey_hdl(adapter, (u8 *)&sta_pparm);
}
@@ -13985,7 +15772,6 @@ u8 set_stakey_hdl(_adapter *padapter, u8 *pbuf)
u16 ctrl = 0;
s16 cam_id = 0;
bool used;
- u8 kid = 0;
u8 ret = H2C_SUCCESS;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
@@ -14004,14 +15790,13 @@ u8 set_stakey_hdl(_adapter *padapter, u8 *pbuf)
}
pmlmeinfo->enc_algo = pparm->algorithm;
- if (is_wep_enc(pparm->algorithm))
- kid = pparm->keyid;
- cam_id = rtw_camid_alloc(padapter, psta, kid, &used);
+
+ cam_id = rtw_camid_alloc(padapter, psta, pparm->keyid, pparm->gk, &used);
if (cam_id < 0)
goto exit;
- /* cam entry searched is group key */
- if (used == _TRUE && rtw_camid_is_gk(padapter, cam_id) == _TRUE) {
+ /* cam entry searched is group key when setting pariwise key */
+ if (!pparm->gk && used == _TRUE && rtw_camid_is_gk(padapter, cam_id) == _TRUE) {
s16 camid_clr;
RTW_PRINT(FUNC_ADPT_FMT" pairwise key with "MAC_FMT" id:%u the same key id as group key\n"
@@ -14037,9 +15822,12 @@ u8 set_stakey_hdl(_adapter *padapter, u8 *pbuf)
rtw_camid_free(padapter, cam_id);
}
} else {
- RTW_PRINT("set pairwise key camid:%d, addr:"MAC_FMT", kid:%d, type:%s\n",
- cam_id, MAC_ARG(pparm->addr), pparm->keyid, security_type_str(pparm->algorithm));
+ RTW_PRINT("set %s key camid:%d, addr:"MAC_FMT", kid:%d, type:%s\n"
+ , pparm->gk ? "group" : "pairwise"
+ , cam_id, MAC_ARG(pparm->addr), pparm->keyid, security_type_str(pparm->algorithm));
ctrl = BIT(15) | ((pparm->algorithm) << 2) | pparm->keyid;
+ if (pparm->gk)
+ ctrl |= BIT(6);
write_cam(padapter, cam_id, ctrl, pparm->addr, pparm->key);
}
ret = H2C_SUCCESS_RSP;
@@ -14066,7 +15854,6 @@ u8 add_ba_hdl(_adapter *padapter, unsigned char *pbuf)
/* pmlmeinfo->candidate_tid_bitmap |= (0x1 << pparm->tid); */
/* psta->htpriv.candidate_tid_bitmap |= BIT(pparm->tid); */
issue_addba_req(padapter, pparm->addr, (u8)pparm->tid);
- /* _set_timer(&pmlmeext->ADDBA_timer, ADDBA_TO); */
_set_timer(&psta->addba_retry_timer, ADDBA_TO);
}
#ifdef CONFIG_TDLS
@@ -14103,13 +15890,17 @@ u8 add_ba_rsp_hdl(_adapter *padapter, unsigned char *pbuf)
/* status = 0 means accept this addba req, so update indicate seq = start_seq under this compile flag */
if (pparm->status == 0) {
preorder_ctrl->indicate_seq = pparm->start_seq;
-#ifdef DBG_RX_SEQ
- RTW_INFO("DBG_RX_SEQ %s:%d IndicateSeq: %d, start_seq: %d\n", __func__, __LINE__,
- preorder_ctrl->indicate_seq, pparm->start_seq);
-#endif
+ #ifdef DBG_RX_SEQ
+ RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_UPDATE indicate_seq:%d, start_seq:%d\n"
+ , FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, pparm->start_seq);
+ #endif
}
#else
preorder_ctrl->indicate_seq = 0xffff;
+ #ifdef DBG_RX_SEQ
+ RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_CLEAR indicate_seq:%d, start_seq:%d\n"
+ , FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, pparm->start_seq);
+ #endif
#endif
/*
@@ -14132,7 +15923,6 @@ u8 chk_bmc_sleepq_cmd(_adapter *padapter)
struct cmd_priv *pcmdpriv = &(padapter->cmdpriv);
u8 res = _SUCCESS;
- _func_enter_;
ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
if (ph2c == NULL) {
@@ -14146,7 +15936,6 @@ u8 chk_bmc_sleepq_cmd(_adapter *padapter)
exit:
- _func_exit_;
return res;
}
@@ -14161,7 +15950,6 @@ u8 set_tx_beacon_cmd(_adapter *padapter)
u8 res = _SUCCESS;
int len_diff = 0;
- _func_enter_;
ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
if (ph2c == NULL) {
@@ -14192,7 +15980,6 @@ u8 set_tx_beacon_cmd(_adapter *padapter)
exit:
- _func_exit_;
return res;
}
@@ -14218,7 +16005,6 @@ u8 mlme_evt_hdl(_adapter *padapter, unsigned char *pbuf)
#ifdef CHECK_EVENT_SEQ
/* checking event sequence... */
if (evt_seq != (ATOMIC_READ(&pevt_priv->event_seq) & 0x7f)) {
- RT_TRACE(_module_rtl871x_cmd_c_, _drv_info_, ("Evetn Seq Error! %d vs %d\n", (evt_seq & 0x7f), (ATOMIC_READ(&pevt_priv->event_seq) & 0x7f)));
pevt_priv->event_seq = (evt_seq + 1) & 0x7f;
@@ -14228,7 +16014,6 @@ u8 mlme_evt_hdl(_adapter *padapter, unsigned char *pbuf)
/* checking if event code is valid */
if (evt_code >= MAX_C2HEVT) {
- RT_TRACE(_module_rtl871x_cmd_c_, _drv_err_, ("\nEvent Code(%d) mismatch!\n", evt_code));
goto _abort_event_;
}
@@ -14236,8 +16021,6 @@ u8 mlme_evt_hdl(_adapter *padapter, unsigned char *pbuf)
if ((wlanevents[evt_code].parmsize != 0) &&
(wlanevents[evt_code].parmsize != evt_sz)) {
- RT_TRACE(_module_rtl871x_cmd_c_, _drv_err_, ("\nEvent(%d) Parm Size mismatch (%d vs %d)!\n",
- evt_code, wlanevents[evt_code].parmsize, evt_sz));
goto _abort_event_;
}
@@ -14284,7 +16067,7 @@ u8 chk_bmc_sleepq_hdl(_adapter *padapter, unsigned char *pbuf)
if (!psta_bmc)
return H2C_SUCCESS;
- if ((pstapriv->tim_bitmap & BIT(0)) && (psta_bmc->sleepq_len > 0)) {
+ if ((rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0)) && (psta_bmc->sleepq_len > 0)) {
#ifndef CONFIG_PCI_HCI
rtw_msleep_os(10);/* 10ms, ATIM(HIQ) Windows */
#endif
@@ -14366,16 +16149,33 @@ void change_band_update_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 ch)
u8 network_type, rate_len, total_rate_len, remainder_rate_len;
struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
u8 erpinfo = 0x4;
if (ch >= 36) {
network_type = WIRELESS_11A;
total_rate_len = IEEE80211_NUM_OFDM_RATESLEN;
rtw_remove_bcn_ie(padapter, pnetwork, _ERPINFO_IE_);
+ #ifdef CONFIG_80211AC_VHT
+ /* if channel in 5G band, then add vht ie . */
+ if ((pmlmepriv->htpriv.ht_option == _TRUE)
+ && REGSTY_IS_11AC_ENABLE(&padapter->registrypriv)
+ && hal_chk_proto_cap(padapter, PROTO_CAP_11AC)
+ && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent))
+ ) {
+ if (REGSTY_IS_11AC_AUTO(&padapter->registrypriv)
+ || pmlmepriv->ori_vht_en)
+ rtw_vht_ies_attach(padapter, pnetwork);
+ }
+ #endif
} else {
network_type = WIRELESS_11BG;
total_rate_len = IEEE80211_CCK_RATE_LEN + IEEE80211_NUM_OFDM_RATESLEN;
rtw_add_bcn_ie(padapter, pnetwork, _ERPINFO_IE_, &erpinfo, 1);
+ #ifdef CONFIG_80211AC_VHT
+ rtw_vht_ies_detach(padapter, pnetwork);
+ #endif
}
rtw_set_supported_rate(pnetwork->SupportedRates, network_type);
@@ -14439,9 +16239,9 @@ void rtw_join_done_chk_ch(_adapter *adapter, int join_res)
if (!iface || iface == adapter)
continue;
- if (check_fwstate(mlme, WIFI_AP_STATE)
- && check_fwstate(mlme, WIFI_ASOC_STATE)
- ) {
+ if ((MLME_IS_AP(iface) || MLME_IS_MESH(iface))
+ && check_fwstate(mlme, WIFI_ASOC_STATE)
+ ) {
bool is_grouped = rtw_is_chbw_grouped(u_ch, u_bw, u_offset
, mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset);
@@ -14454,7 +16254,8 @@ void rtw_join_done_chk_ch(_adapter *adapter, int join_res)
rtw_adjust_chbw(iface
, mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset);
- rtw_sync_chbw(&mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset
+ rtw_chset_sync_chbw(adapter_to_chset(adapter)
+ , &mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset
, &u_ch, &u_bw, &u_offset);
rtw_ap_update_bss_chbw(iface, &(mlmeext->mlmext_info.network)
@@ -14463,12 +16264,19 @@ void rtw_join_done_chk_ch(_adapter *adapter, int join_res)
_rtw_memcpy(&(mlme->cur_network.network), &(mlmeext->mlmext_info.network), sizeof(WLAN_BSSID_EX));
rtw_start_bss_hdl_after_chbw_decided(iface);
+
+ if (MLME_IS_GO(iface) || MLME_IS_MESH(iface)) { /* pure AP is not needed*/
+ #if defined(CONFIG_IOCTL_CFG80211) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0))
+ rtw_cfg80211_ch_switch_notify(iface
+ , mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset
+ , mlme->htpriv.ht_option);
+ #endif
+ }
}
- update_beacon(iface, 0, NULL, _TRUE);
+ clr_fwstate(mlme, WIFI_OP_CH_SWITCHING);
+ update_beacon(iface, 0xFF, NULL, _TRUE);
}
-
- clr_fwstate(mlme, WIFI_OP_CH_SWITCHING);
}
#ifdef CONFIG_DFS_MASTER
@@ -14483,11 +16291,12 @@ void rtw_join_done_chk_ch(_adapter *adapter, int join_res)
if (!iface || iface == adapter)
continue;
- if (check_fwstate(mlme, WIFI_AP_STATE)
- && check_fwstate(mlme, WIFI_ASOC_STATE))
- update_beacon(iface, 0, NULL, _TRUE);
-
- clr_fwstate(mlme, WIFI_OP_CH_SWITCHING);
+ if ((MLME_IS_AP(iface) || MLME_IS_MESH(iface))
+ && check_fwstate(mlme, WIFI_ASOC_STATE)
+ ) {
+ clr_fwstate(mlme, WIFI_OP_CH_SWITCHING);
+ update_beacon(iface, 0xFF, NULL, _TRUE);
+ }
}
#ifdef CONFIG_DFS_MASTER
rtw_dfs_master_status_apply(adapter, MLME_STA_DISCONNECTED);
@@ -14538,20 +16347,17 @@ int rtw_chk_start_clnt_join(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset)
_adapter *iface;
struct mlme_priv *mlme;
struct mlme_ext_priv *mlmeext;
- u8 sta_num;
- u8 ld_sta_num;
- u8 lg_sta_num;
- u8 ap_num;
- u8 ld_ap_num;
+ struct mi_state mstate;
int i;
dvobj = adapter_to_dvobj(adapter);
- rtw_mi_status_no_self(adapter, &sta_num, &ld_sta_num, &lg_sta_num, &ap_num, &ld_ap_num, NULL);
- RTW_INFO(FUNC_ADPT_FMT" ld_sta_num:%u, ap_num:%u\n"
- , FUNC_ADPT_ARG(adapter), ld_sta_num, ap_num);
+ rtw_mi_status_no_self(adapter, &mstate);
+ RTW_INFO(FUNC_ADPT_FMT" ld_sta_num:%u, ap_num:%u, mesh_num:%u\n"
+ , FUNC_ADPT_ARG(adapter), MSTATE_STA_LD_NUM(&mstate)
+ , MSTATE_AP_NUM(&mstate), MSTATE_MESH_NUM(&mstate));
- if (!ld_sta_num && !ap_num) {
+ if (!MSTATE_STA_LD_NUM(&mstate) && !MSTATE_AP_NUM(&mstate) && !MSTATE_MESH_NUM(&mstate)) {
/* consider linking STA? */
goto connect_allow_hdl;
}
@@ -14603,7 +16409,7 @@ int rtw_chk_start_clnt_join(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset)
}
#endif /* CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT */
- if ((ld_sta_num + ld_ap_num) >= 2)
+ if (MSTATE_STA_LD_NUM(&mstate) + MSTATE_AP_LD_NUM(&mstate) + MSTATE_MESH_LD_NUM(&mstate) >= 2)
connect_allow = _FALSE;
RTW_INFO(FUNC_ADPT_FMT" connect_allow:%d\n"
@@ -14632,22 +16438,23 @@ int rtw_chk_start_clnt_join(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset)
if (!iface || iface == adapter)
continue;
- if (check_fwstate(mlme, WIFI_AP_STATE)
- && check_fwstate(mlme, WIFI_ASOC_STATE)
- ) {
-#ifdef CONFIG_SPCT_CH_SWITCH
+ if ((MLME_IS_AP(iface) || MLME_IS_MESH(iface))
+ && check_fwstate(mlme, WIFI_ASOC_STATE)
+ ) {
+ #ifdef CONFIG_SPCT_CH_SWITCH
if (1)
rtw_ap_inform_ch_switch(iface, pmlmeext->cur_channel , pmlmeext->cur_ch_offset);
else
-#endif
+ #endif
rtw_sta_flush(iface, _FALSE);
rtw_hal_set_hwreg(iface, HW_VAR_CHECK_TXBUF, 0);
set_fwstate(mlme, WIFI_OP_CH_SWITCHING);
+
} else if (check_fwstate(mlme, WIFI_STATION_STATE)
&& check_fwstate(mlme, WIFI_ASOC_STATE)
- ) {
- rtw_disassoc_cmd(iface, 500, _FALSE);
+ ) {
+ rtw_disassoc_cmd(iface, 500, RTW_CMDF_DIRECTLY);
rtw_indicate_disconnect(iface, 0, _FALSE);
rtw_free_assoc_resources(iface, 1);
}
@@ -14669,7 +16476,7 @@ int rtw_chk_start_clnt_join(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset)
}
-u8 set_ch_hdl(_adapter *padapter, u8 *pbuf)
+u8 rtw_set_chbw_hdl(_adapter *padapter, u8 *pbuf)
{
struct set_ch_parm *set_ch_parm;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
@@ -14696,7 +16503,7 @@ u8 set_ch_hdl(_adapter *padapter, u8 *pbuf)
u8 set_chplan_hdl(_adapter *padapter, unsigned char *pbuf)
{
struct SetChannelPlan_param *setChannelPlan_param;
- struct mlme_priv *mlme = &padapter->mlmepriv;
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
if (!pbuf)
@@ -14707,11 +16514,14 @@ u8 set_chplan_hdl(_adapter *padapter, unsigned char *pbuf)
if (!rtw_is_channel_plan_valid(setChannelPlan_param->channel_plan))
return H2C_PARAMETERS_ERROR;
- mlme->country_ent = setChannelPlan_param->country_ent;
- mlme->ChannelPlan = setChannelPlan_param->channel_plan;
+ rfctl->country_ent = setChannelPlan_param->country_ent;
+ rfctl->ChannelPlan = setChannelPlan_param->channel_plan;
- pmlmeext->max_chan_nums = init_channel_set(padapter, setChannelPlan_param->channel_plan, pmlmeext->channel_set);
- init_channel_list(padapter, pmlmeext->channel_set, pmlmeext->max_chan_nums, &pmlmeext->channel_list);
+ rfctl->max_chan_nums = init_channel_set(padapter, rfctl->ChannelPlan, rfctl->channel_set);
+ init_channel_list(padapter, rfctl->channel_set, &rfctl->channel_list);
+#ifdef CONFIG_TXPWR_LIMIT
+ rtw_txpwr_init_regd(rfctl);
+#endif
rtw_hal_set_odm_var(padapter, HAL_ODM_REGULATION, NULL, _TRUE);
@@ -14731,7 +16541,7 @@ u8 led_blink_hdl(_adapter *padapter, unsigned char *pbuf)
ledBlink_param = (struct LedBlink_param *)pbuf;
-#ifdef CONFIG_LED_HANDLED_BY_CMD_THREAD
+#ifdef CONFIG_RTW_LED_HANDLED_BY_CMD_THREAD
BlinkHandler((PLED_DATA)ledBlink_param->pLed);
#endif
@@ -14756,17 +16566,17 @@ u8 set_csa_hdl(_adapter *padapter, unsigned char *pbuf)
rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, &sval8);
RTW_INFO("DFS detected! Swiching channel to %d!\n", new_ch_no);
- SelectChannel(padapter, new_ch_no);
+ set_channel_bwmode(padapter, new_ch_no, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, &gval8);
- rtw_disassoc_cmd(padapter, 0, _FALSE);
+ rtw_disassoc_cmd(padapter, 0, RTW_CMDF_DIRECTLY);
rtw_indicate_disconnect(padapter, 0, _FALSE);
rtw_free_assoc_resources(padapter, 1);
rtw_free_network_queue(padapter, _TRUE);
- if (((new_ch_no >= 52) && (new_ch_no <= 64)) || ((new_ch_no >= 100) && (new_ch_no <= 140)))
- RTW_INFO("Switched to DFS band (ch %02x) again!!\n", new_ch_no);
+ if (rtw_is_dfs_ch(new_ch_no))
+ RTW_INFO("Switched to DFS band (ch %u) again!!\n", new_ch_no);
return H2C_SUCCESS;
#else
@@ -14788,12 +16598,14 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf)
struct sta_info *ptdls_sta = NULL;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
+ struct sta_info *ap_sta = rtw_get_stainfo(&padapter->stapriv, get_my_bssid(&(pmlmeinfo->network)));
u8 survey_channel, i, min, option;
struct tdls_txmgmt txmgmt;
u32 setchtime, resp_sleep = 0, wait_time;
u8 zaddr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
u8 ret;
u8 doiqk;
+ u64 tx_ra_bitmap = 0;
if (!pbuf)
return H2C_PARAMETERS_ERROR;
@@ -14822,17 +16634,19 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf)
/* leave ALL PS when TDLS is established */
rtw_pwr_wakeup(padapter);
- rtw_hal_set_hwreg(padapter, HW_VAR_TDLS_WRCR, 0);
- RTW_INFO("Created Direct Link with "MAC_FMT"\n", MAC_ARG(ptdls_sta->hwaddr));
+ rtw_hal_rcr_set_chk_bssid(padapter, MLME_TDLS_LINKED);
+ RTW_INFO("Created Direct Link with "MAC_FMT"\n", MAC_ARG(ptdls_sta->cmn.mac_addr));
/* Set TDLS sta rate. */
/* Update station supportRate */
- rtw_hal_update_sta_rate_mask(padapter, ptdls_sta);
+ rtw_hal_update_sta_ra_info(padapter, ptdls_sta);
+ tx_ra_bitmap = ptdls_sta->cmn.ra_info.ramask;
+
if (pmlmeext->cur_channel > 14) {
- if (ptdls_sta->ra_mask & 0xffff000)
+ if (tx_ra_bitmap & 0xffff000)
sta_band |= WIRELESS_11_5N ;
- if (ptdls_sta->ra_mask & 0xff0)
+ if (tx_ra_bitmap & 0xff0)
sta_band |= WIRELESS_11A;
/* 5G band */
@@ -14842,21 +16656,22 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf)
#endif
} else {
- if (ptdls_sta->ra_mask & 0xffff000)
+ if (tx_ra_bitmap & 0xffff000)
sta_band |= WIRELESS_11_24N;
- if (ptdls_sta->ra_mask & 0xff0)
+ if (tx_ra_bitmap & 0xff0)
sta_band |= WIRELESS_11G;
- if (ptdls_sta->ra_mask & 0x0f)
+ if (tx_ra_bitmap & 0x0f)
sta_band |= WIRELESS_11B;
}
ptdls_sta->wireless_mode = sta_band;
- ptdls_sta->raid = rtw_hal_networktype_to_raid(padapter, ptdls_sta);
- set_sta_rate(padapter, ptdls_sta);
- rtw_sta_media_status_rpt(padapter, ptdls_sta, 1);
+ rtw_hal_update_sta_wset(padapter, ptdls_sta);
/* Sta mode */
rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, ptdls_sta, _TRUE);
+
+ set_sta_rate(padapter, ptdls_sta);
+ rtw_sta_media_status_rpt(padapter, ptdls_sta, 1);
break;
}
case TDLS_ISSUE_PTI:
@@ -14868,22 +16683,24 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf)
case TDLS_CH_SW_RESP:
_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
txmgmt.status_code = 0;
- _rtw_memcpy(txmgmt.peer, ptdls_sta->hwaddr, ETH_ALEN);
+ _rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN);
+ if (ap_sta)
+ rtw_hal_macid_sleep(padapter, ap_sta->cmn.mac_id);
issue_nulldata(padapter, NULL, 1, 3, 3);
RTW_INFO("[TDLS ] issue tdls channel switch response\n");
ret = issue_tdls_ch_switch_rsp(padapter, &txmgmt, _TRUE);
/* If we receive TDLS_CH_SW_REQ at off channel which it's target is AP's channel */
- /* then we just SelectChannel to AP's channel*/
+ /* then we just switch to AP's channel*/
if (padapter->mlmeextpriv.cur_channel == pchsw_info->off_ch_num) {
- rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_END_TO_BASE_CHNL);
+ rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_END_TO_BASE_CHNL);
break;
}
if (ret == _SUCCESS)
- rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_TO_OFF_CHNL);
+ rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_OFF_CHNL);
else
RTW_INFO("[TDLS] issue_tdls_ch_switch_rsp wait ack fail !!!!!!!!!!\n");
@@ -14901,7 +16718,7 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf)
/* switch back to base-chnl */
set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
- rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_START);
+ rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_START);
pchsw_info->ch_sw_state &= ~(TDLS_CH_SWITCH_PREPARE_STATE);
@@ -14910,23 +16727,26 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf)
rtw_tdls_set_ch_sw_oper_control(padapter, _TRUE);
break;
case TDLS_CH_SW_TO_OFF_CHNL:
+ if (ap_sta)
+ rtw_hal_macid_sleep(padapter, ap_sta->cmn.mac_id);
issue_nulldata(padapter, NULL, 1, 3, 3);
+ if (padapter->registrypriv.wifi_spec == 0) {
if (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE))
_set_timer(&ptdls_sta->ch_sw_timer, (u32)(ptdls_sta->ch_switch_timeout) / 1000);
+ }
if (rtw_tdls_do_ch_sw(padapter, ptdls_sta, TDLS_CH_SW_OFF_CHNL, pchsw_info->off_ch_num,
pchsw_info->ch_offset, (pchsw_info->ch_offset) ? CHANNEL_WIDTH_40 : CHANNEL_WIDTH_20, ptdls_sta->ch_switch_time) == _SUCCESS) {
pchsw_info->ch_sw_state &= ~(TDLS_PEER_AT_OFF_STATE);
if (pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE) {
- if (issue_nulldata_to_TDLS_peer_STA(ptdls_sta->padapter, ptdls_sta->hwaddr, 0, 1, 3) == _FAIL)
- rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_TO_BASE_CHNL);
+ if (issue_nulldata_to_TDLS_peer_STA(ptdls_sta->padapter, ptdls_sta->cmn.mac_addr, 0, 1,
+ (padapter->registrypriv.wifi_spec == 0) ? 3 : 0) == _FAIL)
+ rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_BASE_CHNL);
}
} else {
- u8 bcancelled;
-
if (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE))
- _cancel_timer(&ptdls_sta->ch_sw_timer, &bcancelled);
+ _cancel_timer_ex(&ptdls_sta->ch_sw_timer);
}
@@ -14943,7 +16763,7 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf)
#endif
if (option == TDLS_CH_SW_END_TO_BASE_CHNL)
- rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_TO_BASE_CHNL);
+ rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_BASE_CHNL);
break;
case TDLS_CH_SW_TO_BASE_CHNL_UNSOLICITED:
@@ -14955,13 +16775,15 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf)
/* Send unsolicited channel switch rsp. to peer */
_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
txmgmt.status_code = 0;
- _rtw_memcpy(txmgmt.peer, ptdls_sta->hwaddr, ETH_ALEN);
+ _rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN);
issue_tdls_ch_switch_rsp(padapter, &txmgmt, _FALSE);
}
}
if (rtw_tdls_do_ch_sw(padapter, ptdls_sta, TDLS_CH_SW_BASE_CHNL, pmlmeext->cur_channel,
pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode, ptdls_sta->ch_switch_time) == _SUCCESS) {
+ if (ap_sta)
+ rtw_hal_macid_wakeup(padapter, ap_sta->cmn.mac_id);
issue_nulldata(padapter, NULL, 0, 3, 3);
/* set ch sw monitor timer for responder */
if (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE))
@@ -14971,17 +16793,19 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf)
break;
#endif
case TDLS_RS_RCR:
- rtw_hal_set_hwreg(padapter, HW_VAR_TDLS_RS_RCR, 0);
- RTW_INFO("[TDLS] write REG_RCR, set bit6 on\n");
+ rtw_hal_rcr_set_chk_bssid(padapter, MLME_TDLS_NOLINK);
break;
case TDLS_TEARDOWN_STA:
+ case TDLS_TEARDOWN_STA_NO_WAIT:
_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
- txmgmt.status_code = 0;
- _rtw_memcpy(txmgmt.peer, ptdls_sta->hwaddr, ETH_ALEN);
+ txmgmt.status_code = _RSON_TDLS_TEAR_UN_RSN_;
+ _rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN);
+
+ issue_tdls_teardown(padapter, &txmgmt, (option == TDLS_TEARDOWN_STA) ? _TRUE : _FALSE);
- issue_tdls_teardown(padapter, &txmgmt, _TRUE);
break;
case TDLS_TEARDOWN_STA_LOCALLY:
+ case TDLS_TEARDOWN_STA_LOCALLY_POST:
#ifdef CONFIG_TDLS_CH_SW
if (_rtw_memcmp(TDLSoption->addr, pchsw_info->addr, ETH_ALEN) == _TRUE) {
pchsw_info->ch_sw_state &= ~(TDLS_CH_SW_INITIATOR_STATE |
@@ -14991,8 +16815,15 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf)
_rtw_memset(pchsw_info->addr, 0x00, ETH_ALEN);
}
#endif
- rtw_sta_media_status_rpt(padapter, ptdls_sta, 0);
- free_tdls_sta(padapter, ptdls_sta);
+
+ if (option == TDLS_TEARDOWN_STA_LOCALLY)
+ rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);
+
+ rtw_tdls_teardown_post_hdl(padapter, ptdls_sta, _FALSE);
+
+ if (ptdlsinfo->tdls_sctx != NULL)
+ rtw_sctx_done(&(ptdlsinfo->tdls_sctx));
+
break;
}
diff --git a/core/rtw_mp.c b/core/rtw_mp.c
index 98054d1..ad9755b 100644
--- a/core/rtw_mp.c
+++ b/core/rtw_mp.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,12 +11,7 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#define _RTW_MP_C_
#include
#ifdef PLATFORM_FREEBSD
@@ -125,7 +120,7 @@ static void _init_mp_priv_(struct mp_priv *pmp_priv)
pmp_priv->channel = 1;
pmp_priv->bandwidth = CHANNEL_WIDTH_20;
- pmp_priv->prime_channel_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+ pmp_priv->prime_channel_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
pmp_priv->rateidx = RATE_1M;
pmp_priv->txpoweridx = 0x2A;
@@ -151,6 +146,8 @@ static void _init_mp_priv_(struct mp_priv *pmp_priv)
pmp_priv->bRTWSmbCfg = _FALSE;
pmp_priv->bloopback = _FALSE;
+ pmp_priv->bloadefusemap = _FALSE;
+
pnetwork = &pmp_priv->mp_network.network;
_rtw_memcpy(pnetwork->MacAddress, pmp_priv->network_macaddr, ETH_ALEN);
@@ -162,6 +159,8 @@ static void _init_mp_priv_(struct mp_priv *pmp_priv)
pmp_priv->tx.attrib.ht_en = 1;
#endif
+ pmp_priv->mpt_ctx.mpt_rate_index = 1;
+
}
#ifdef PLATFORM_WINDOWS
@@ -187,9 +186,6 @@ void mp_wi_callback(
NdisGetCurrentSystemTime(&cur_time); /* driver version */
end_time = cur_time.QuadPart / 10; /* The return value is in microsecond */
- RT_TRACE(_module_mp_, _drv_info_,
- ("WorkItemActType: %d, time spent: %I64d us\n",
- pmp_wi_cntx->param.act_type, (end_time - start_time)));
}
NdisAcquireSpinLock(&(pmp_wi_cntx->mp_wi_lock));
@@ -343,7 +339,6 @@ s32 init_mp_priv(PADAPTER padapter)
pmppriv->antenna_rx = ANTENNA_AB;
break;
case RF_2T2R:
- case RF_2T2R_GREEN:
pmppriv->antenna_tx = ANTENNA_AB;
pmppriv->antenna_rx = ANTENNA_AB;
break;
@@ -354,7 +349,7 @@ s32 init_mp_priv(PADAPTER padapter)
}
pHalData->AntennaRxPath = pmppriv->antenna_rx;
- pHalData->AntennaTxPath = pmppriv->antenna_tx;
+ pHalData->antenna_tx_path = pmppriv->antenna_tx;
return _SUCCESS;
}
@@ -395,209 +390,225 @@ static VOID PHY_SetRFPathSwitch_default(
void mpt_InitHWConfig(PADAPTER Adapter)
{
+ PHAL_DATA_TYPE hal;
+
+ hal = GET_HAL_DATA(Adapter);
+
if (IS_HARDWARE_TYPE_8723B(Adapter)) {
/* TODO: <20130114, Kordan> The following setting is only for DPDT and Fixed board type. */
/* TODO: A better solution is configure it according EFUSE during the run-time. */
- PHY_SetMacReg(Adapter, 0x64, BIT20, 0x0); /* 0x66[4]=0 */
- PHY_SetMacReg(Adapter, 0x64, BIT24, 0x0); /* 0x66[8]=0 */
- PHY_SetMacReg(Adapter, 0x40, BIT4, 0x0); /* 0x40[4]=0 */
- PHY_SetMacReg(Adapter, 0x40, BIT3, 0x1); /* 0x40[3]=1 */
- PHY_SetMacReg(Adapter, 0x4C, BIT24, 0x1); /* 0x4C[24:23]=10 */
- PHY_SetMacReg(Adapter, 0x4C, BIT23, 0x0); /* 0x4C[24:23]=10 */
- PHY_SetBBReg(Adapter, 0x944, BIT1 | BIT0, 0x3); /* 0x944[1:0]=11 */
- PHY_SetBBReg(Adapter, 0x930, bMaskByte0, 0x77); /* 0x930[7:0]=77 */
- PHY_SetMacReg(Adapter, 0x38, BIT11, 0x1); /* 0x38[11]=1 */
+ phy_set_mac_reg(Adapter, 0x64, BIT20, 0x0); /* 0x66[4]=0 */
+ phy_set_mac_reg(Adapter, 0x64, BIT24, 0x0); /* 0x66[8]=0 */
+ phy_set_mac_reg(Adapter, 0x40, BIT4, 0x0); /* 0x40[4]=0 */
+ phy_set_mac_reg(Adapter, 0x40, BIT3, 0x1); /* 0x40[3]=1 */
+ phy_set_mac_reg(Adapter, 0x4C, BIT24, 0x1); /* 0x4C[24:23]=10 */
+ phy_set_mac_reg(Adapter, 0x4C, BIT23, 0x0); /* 0x4C[24:23]=10 */
+ phy_set_bb_reg(Adapter, 0x944, BIT1 | BIT0, 0x3); /* 0x944[1:0]=11 */
+ phy_set_bb_reg(Adapter, 0x930, bMaskByte0, 0x77);/* 0x930[7:0]=77 */
+ phy_set_mac_reg(Adapter, 0x38, BIT11, 0x1);/* 0x38[11]=1 */
/* TODO: <20130206, Kordan> The default setting is wrong, hard-coded here. */
- PHY_SetMacReg(Adapter, 0x778, 0x3, 0x3); /* Turn off hardware PTA control (Asked by Scott) */
- PHY_SetMacReg(Adapter, 0x64, bMaskDWord, 0x36000000); /* Fix BT S0/S1 */
- PHY_SetMacReg(Adapter, 0x948, bMaskDWord, 0x0); /* Fix BT can't Tx */
+ phy_set_mac_reg(Adapter, 0x778, 0x3, 0x3); /* Turn off hardware PTA control (Asked by Scott) */
+ phy_set_mac_reg(Adapter, 0x64, bMaskDWord, 0x36000000);/* Fix BT S0/S1 */
+ phy_set_mac_reg(Adapter, 0x948, bMaskDWord, 0x0); /* Fix BT can't Tx */
/* <20130522, Kordan> Turn off equalizer to improve Rx sensitivity. (Asked by EEChou) */
- PHY_SetBBReg(Adapter, 0xA00, BIT8, 0x0); /*0xA01[0] = 0*/
+ phy_set_bb_reg(Adapter, 0xA00, BIT8, 0x0); /*0xA01[0] = 0*/
} else if (IS_HARDWARE_TYPE_8821(Adapter)) {
/* <20131121, VincentL> Add for 8821AU DPDT setting and fix switching antenna issue (Asked by Rock)
<20131122, VincentL> Enable for all 8821A/8811AU (Asked by Alex)*/
- PHY_SetMacReg(Adapter, 0x4C, BIT23, 0x0); /*0x4C[23:22]=01*/
- PHY_SetMacReg(Adapter, 0x4C, BIT22, 0x1); /*0x4C[23:22]=01*/
+ phy_set_mac_reg(Adapter, 0x4C, BIT23, 0x0); /*0x4C[23:22]=01*/
+ phy_set_mac_reg(Adapter, 0x4C, BIT22, 0x1); /*0x4C[23:22]=01*/
} else if (IS_HARDWARE_TYPE_8188ES(Adapter))
- PHY_SetMacReg(Adapter, 0x4C , BIT23, 0); /*select DPDT_P and DPDT_N as output pin*/
+ phy_set_mac_reg(Adapter, 0x4C , BIT23, 0); /*select DPDT_P and DPDT_N as output pin*/
#ifdef CONFIG_RTL8814A
else if (IS_HARDWARE_TYPE_8814A(Adapter))
PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8814A, 0x2000);
#endif
+
+#ifdef CONFIG_RTL8812A
+ else if (IS_HARDWARE_TYPE_8812(Adapter)) {
+ rtw_write32(Adapter, 0x520, rtw_read32(Adapter, 0x520) | 0x8000);
+ rtw_write32(Adapter, 0x524, rtw_read32(Adapter, 0x524) & (~0x800));
+ }
+#endif
+
+
#ifdef CONFIG_RTL8822B
else if (IS_HARDWARE_TYPE_8822B(Adapter)) {
u32 tmp_reg = 0;
PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8822B, 0x2000);
/* fixed wifi can't 2.4g tx suggest by Szuyitasi 20160504 */
- PHY_SetBBReg(Adapter, 0x70, bMaskByte3, 0x0e);
- RTW_INFO(" 0x73 = 0x%x\n",PHY_QueryBBReg(Adapter, 0x70, bMaskByte3));
- PHY_SetBBReg(Adapter, 0x1704, bMaskDWord, 0x0000ff00);
- RTW_INFO(" 0x1704 = 0x%x\n",PHY_QueryBBReg(Adapter, 0x1704, bMaskDWord));
- PHY_SetBBReg(Adapter, 0x1700, bMaskDWord, 0xc00f0038);
- RTW_INFO(" 0x1700 = 0x%x\n",PHY_QueryBBReg(Adapter, 0x1700, bMaskDWord));
+ phy_set_bb_reg(Adapter, 0x70, bMaskByte3, 0x0e);
+ RTW_INFO(" 0x73 = 0x%x\n", phy_query_bb_reg(Adapter, 0x70, bMaskByte3));
+ phy_set_bb_reg(Adapter, 0x1704, bMaskDWord, 0x0000ff00);
+ RTW_INFO(" 0x1704 = 0x%x\n", phy_query_bb_reg(Adapter, 0x1704, bMaskDWord));
+ phy_set_bb_reg(Adapter, 0x1700, bMaskDWord, 0xc00f0038);
+ RTW_INFO(" 0x1700 = 0x%x\n", phy_query_bb_reg(Adapter, 0x1700, bMaskDWord));
}
#endif /* CONFIG_RTL8822B */
#ifdef CONFIG_RTL8821C
else if (IS_HARDWARE_TYPE_8821C(Adapter))
PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8821C, 0x2000);
#endif /* CONFIG_RTL8821C */
+#ifdef CONFIG_RTL8188F
+ else if (IS_HARDWARE_TYPE_8188F(Adapter)) {
+ if (IS_A_CUT(hal->version_id) || IS_B_CUT(hal->version_id)) {
+ RTW_INFO("%s() Active large power detection\n", __func__);
+ phy_active_large_power_detection_8188f(&(GET_HAL_DATA(Adapter)->odmpriv));
+ }
+ }
+#endif
}
static void PHY_IQCalibrate(PADAPTER padapter, u8 bReCovery)
{
- PHAL_DATA_TYPE pHalData;
- u8 b2ant; /* false:1ant, true:2-ant */
- u8 RF_Path; /* 0:S1, 1:S0 */
-
- if (IS_HARDWARE_TYPE_8723B(padapter)) {
-#ifdef CONFIG_RTL8723B
- pHalData = GET_HAL_DATA(padapter);
- b2ant = pHalData->EEPROMBluetoothAntNum == Ant_x2 ? _TRUE : _FALSE;
- PHY_IQCalibrate_8723B(padapter, bReCovery, _FALSE, b2ant, pHalData->ant_path);
-#endif
- } else if (IS_HARDWARE_TYPE_8188E(padapter)) {
-#ifdef CONFIG_RTL8188E
- PHY_IQCalibrate_8188E(padapter, bReCovery);
-#endif
- } else if (IS_HARDWARE_TYPE_8814A(padapter)) {
-#ifdef CONFIG_RTL8814A
- PHY_IQCalibrate_8814A(&(GET_HAL_DATA(padapter)->odmpriv), bReCovery);
-#endif
- } else if (IS_HARDWARE_TYPE_8812(padapter)) {
-#ifdef CONFIG_RTL8812A
- PHY_IQCalibrate_8812A(padapter, bReCovery);
-#endif
- } else if (IS_HARDWARE_TYPE_8821(padapter)) {
-#ifdef CONFIG_RTL8821A
- PHY_IQCalibrate_8821A(&(GET_HAL_DATA(padapter)->odmpriv), bReCovery);
-#endif
- } else if (IS_HARDWARE_TYPE_8192E(padapter)) {
-#ifdef CONFIG_RTL8192E
- PHY_IQCalibrate_8192E(padapter, bReCovery);
-#endif
- } else if (IS_HARDWARE_TYPE_8703B(padapter)) {
-#ifdef CONFIG_RTL8703B
- PHY_IQCalibrate_8703B(padapter, bReCovery);
-#endif
- } else if (IS_HARDWARE_TYPE_8188F(padapter)) {
-#ifdef CONFIG_RTL8188F
- PHY_IQCalibrate_8188F(padapter, bReCovery, _FALSE);
-#endif
- } else if (IS_HARDWARE_TYPE_8822B(padapter)) {
-#ifdef CONFIG_RTL8822B
- PHY_IQCalibrate_8822B(&(GET_HAL_DATA(padapter)->odmpriv), bReCovery);
-#endif
- } else if (IS_HARDWARE_TYPE_8723D(padapter)) {
-#ifdef CONFIG_RTL8723D
- PHY_IQCalibrate_8723D(padapter, bReCovery);
-#endif
- } else if (IS_HARDWARE_TYPE_8821C(padapter)) {
-#ifdef CONFIG_RTL8821C
- /*PHY_IQCalibrate_8821C(padapter, bReCovery);*/
-#endif
- }
-
+ halrf_iqk_trigger(&(GET_HAL_DATA(padapter)->odmpriv), bReCovery);
}
static void PHY_LCCalibrate(PADAPTER padapter)
{
+ halrf_lck_trigger(&(GET_HAL_DATA(padapter)->odmpriv));
+}
+
+static u8 PHY_QueryRFPathSwitch(PADAPTER padapter)
+{
+ u8 bmain = 0;
+/*
if (IS_HARDWARE_TYPE_8723B(padapter)) {
#ifdef CONFIG_RTL8723B
- PHY_LCCalibrate_8723B(&(GET_HAL_DATA(padapter)->odmpriv));
+ bmain = PHY_QueryRFPathSwitch_8723B(padapter);
#endif
} else if (IS_HARDWARE_TYPE_8188E(padapter)) {
#ifdef CONFIG_RTL8188E
- PHY_LCCalibrate_8188E(&(GET_HAL_DATA(padapter)->odmpriv));
+ bmain = PHY_QueryRFPathSwitch_8188E(padapter);
#endif
- } else if (IS_HARDWARE_TYPE_8814A(padapter)) {
+ } else if (IS_HARDWARE_TYPE_8814A(padapter)) {
#ifdef CONFIG_RTL8814A
- PHY_LCCalibrate_8814A(&(GET_HAL_DATA(padapter)->odmpriv));
+ bmain = PHY_QueryRFPathSwitch_8814A(padapter);
#endif
- } else if (IS_HARDWARE_TYPE_8812(padapter)) {
-#ifdef CONFIG_RTL8812A
- PHY_LCCalibrate_8812A(&(GET_HAL_DATA(padapter)->odmpriv));
-#endif
- } else if (IS_HARDWARE_TYPE_8821(padapter)) {
-#ifdef CONFIG_RTL8821A
- PHY_LCCalibrate_8821A(&(GET_HAL_DATA(padapter)->odmpriv));
+ } else if (IS_HARDWARE_TYPE_8812(padapter) || IS_HARDWARE_TYPE_8821(padapter)) {
+#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
+ bmain = PHY_QueryRFPathSwitch_8812A(padapter);
#endif
} else if (IS_HARDWARE_TYPE_8192E(padapter)) {
#ifdef CONFIG_RTL8192E
- PHY_LCCalibrate_8192E(&(GET_HAL_DATA(padapter)->odmpriv));
+ bmain = PHY_QueryRFPathSwitch_8192E(padapter);
#endif
} else if (IS_HARDWARE_TYPE_8703B(padapter)) {
#ifdef CONFIG_RTL8703B
- PHY_LCCalibrate_8703B(&(GET_HAL_DATA(padapter)->odmpriv));
+ bmain = PHY_QueryRFPathSwitch_8703B(padapter);
#endif
} else if (IS_HARDWARE_TYPE_8188F(padapter)) {
#ifdef CONFIG_RTL8188F
- PHY_LCCalibrate_8188F(&(GET_HAL_DATA(padapter)->odmpriv));
+ bmain = PHY_QueryRFPathSwitch_8188F(padapter);
#endif
} else if (IS_HARDWARE_TYPE_8822B(padapter)) {
#ifdef CONFIG_RTL8822B
- PHY_LCCalibrate_8822B(&(GET_HAL_DATA(padapter)->odmpriv));
+ bmain = PHY_QueryRFPathSwitch_8822B(padapter);
#endif
} else if (IS_HARDWARE_TYPE_8723D(padapter)) {
#ifdef CONFIG_RTL8723D
- PHY_LCCalibrate_8723D(&(GET_HAL_DATA(padapter)->odmpriv));
+ bmain = PHY_QueryRFPathSwitch_8723D(padapter);
#endif
- } else if (IS_HARDWARE_TYPE_8821C(padapter)) {
+ } else
+*/
+
+ if (IS_HARDWARE_TYPE_8821C(padapter)) {
#ifdef CONFIG_RTL8821C
- /*PHY_IQCalibrate_8821C(&(GET_HAL_DATA(padapter)->odmpriv));*/
+ bmain = phy_query_rf_path_switch_8821c(padapter);
#endif
}
+ return bmain;
}
static void PHY_SetRFPathSwitch(PADAPTER padapter , BOOLEAN bMain) {
+ PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter);
+ struct dm_struct *phydm = &hal->odmpriv;
+
if (IS_HARDWARE_TYPE_8723B(padapter)) {
#ifdef CONFIG_RTL8723B
- PHY_SetRFPathSwitch_8723B(padapter, bMain);
+ phy_set_rf_path_switch_8723b(phydm, bMain);
#endif
} else if (IS_HARDWARE_TYPE_8188E(padapter)) {
#ifdef CONFIG_RTL8188E
- PHY_SetRFPathSwitch_8188E(padapter, bMain);
+ phy_set_rf_path_switch_8188e(phydm, bMain);
#endif
} else if (IS_HARDWARE_TYPE_8814A(padapter)) {
#ifdef CONFIG_RTL8814A
- PHY_SetRFPathSwitch_8814A(padapter, bMain);
+ phy_set_rf_path_switch_8814a(phydm, bMain);
#endif
} else if (IS_HARDWARE_TYPE_8812(padapter) || IS_HARDWARE_TYPE_8821(padapter)) {
#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
- PHY_SetRFPathSwitch_8812A(padapter, bMain);
+ phy_set_rf_path_switch_8812a(phydm, bMain);
#endif
} else if (IS_HARDWARE_TYPE_8192E(padapter)) {
#ifdef CONFIG_RTL8192E
- PHY_SetRFPathSwitch_8192E(padapter, bMain);
+ phy_set_rf_path_switch_8192e(phydm, bMain);
#endif
} else if (IS_HARDWARE_TYPE_8703B(padapter)) {
#ifdef CONFIG_RTL8703B
- PHY_SetRFPathSwitch_8703B(padapter, bMain);
+ phy_set_rf_path_switch_8703b(phydm, bMain);
#endif
} else if (IS_HARDWARE_TYPE_8188F(padapter)) {
#ifdef CONFIG_RTL8188F
- PHY_SetRFPathSwitch_8188F(padapter, bMain);
+ phy_set_rf_path_switch_8188f(phydm, bMain);
#endif
} else if (IS_HARDWARE_TYPE_8822B(padapter)) {
#ifdef CONFIG_RTL8822B
- PHY_SetRFPathSwitch_8822B(padapter, bMain);
+ phy_set_rf_path_switch_8822b(phydm, bMain);
#endif
} else if (IS_HARDWARE_TYPE_8723D(padapter)) {
#ifdef CONFIG_RTL8723D
- PHY_SetRFPathSwitch_8723D(padapter, bMain);
+ phy_set_rf_path_switch_8723d(phydm, bMain);
#endif
} else if (IS_HARDWARE_TYPE_8821C(padapter)) {
#ifdef CONFIG_RTL8821C
- /*PHY_SetRFPathSwitch_8821C(&(GET_HAL_DATA(padapter)->odmpriv));*/
+ phy_set_rf_path_switch_8821c(phydm, bMain);
#endif
}
}
+
+static void phy_switch_rf_path_set(PADAPTER padapter , u8 *prf_set_State) {
+
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+ struct dm_struct *p_dm = &pHalData->odmpriv;
+
+#ifdef CONFIG_RTL8821C
+ if (IS_HARDWARE_TYPE_8821C(padapter)) {
+ config_phydm_set_ant_path(p_dm, *prf_set_State, p_dm->current_ant_num_8821c);
+ /* Do IQK when switching to BTG/WLG, requested by RF Binson */
+ if (*prf_set_State == SWITCH_TO_BTG || *prf_set_State == SWITCH_TO_WLG)
+ PHY_IQCalibrate(padapter, FALSE);
+ }
+#endif
+
+}
+
+
+#ifdef CONFIG_ANTENNA_DIVERSITY
+u8 rtw_mp_set_antdiv(PADAPTER padapter, BOOLEAN bMain)
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+ u8 cur_ant, change_ant;
+
+ if (!pHalData->AntDivCfg)
+ return _FALSE;
+ /*rtw_hal_get_odm_var(padapter, HAL_ODM_ANTDIV_SELECT, &cur_ant, NULL);*/
+ change_ant = (bMain == MAIN_ANT) ? MAIN_ANT : AUX_ANT;
+
+ RTW_INFO("%s: config %s\n", __func__, (bMain == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
+ rtw_antenna_select_cmd(padapter, change_ant, _FALSE);
+
+ return _TRUE;
+}
+#endif
+
s32
MPT_InitializeAdapter(
IN PADAPTER pAdapter,
@@ -606,7 +617,7 @@ MPT_InitializeAdapter(
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
s32 rtStatus = _SUCCESS;
- PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx;
+ PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.mpt_ctx;
u32 ledsetting;
struct mlme_priv *pmlmepriv = &pAdapter->mlmepriv;
@@ -620,7 +631,7 @@ MPT_InitializeAdapter(
pMptCtx->MptH2cRspEvent = _FALSE;
pMptCtx->MptBtC2hEvent = _FALSE;
_rtw_init_sema(&pMptCtx->MPh2c_Sema, 0);
- _init_timer(&pMptCtx->MPh2c_timeout_timer, pAdapter->pnetdev, MPh2c_timeout_handle, pAdapter);
+ rtw_init_timer(&pMptCtx->MPh2c_timeout_timer, pAdapter, MPh2c_timeout_handle, pAdapter);
#endif
mpt_InitHWConfig(pAdapter);
@@ -630,13 +641,14 @@ MPT_InitializeAdapter(
if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
/* <20130522, Kordan> Turn off equalizer to improve Rx sensitivity. (Asked by EEChou)*/
- PHY_SetBBReg(pAdapter, 0xA00, BIT8, 0x0);
+ phy_set_bb_reg(pAdapter, 0xA00, BIT8, 0x0);
PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); /*default use Main*/
- /*<20130522, Kordan> 0x51 and 0x71 should be set immediately after path switched, or they might be overwritten. */
- if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90))
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E);
- else
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E);
+
+ if (pHalData->PackageType == PACKAGE_DEFAULT)
+ phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E);
+ else
+ phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6F10E);
+
}
/*set ant to wifi side in mp mode*/
rtw_write16(pAdapter, 0x870, 0x300);
@@ -645,7 +657,7 @@ MPT_InitializeAdapter(
pMptCtx->bMptWorkItemInProgress = _FALSE;
pMptCtx->CurrMptAct = NULL;
- pMptCtx->MptRfPath = ODM_RF_PATH_A;
+ pMptCtx->mpt_rf_path = RF_PATH_A;
/* ------------------------------------------------------------------------- */
/* Don't accept any packets */
rtw_write32(pAdapter, REG_RCR, 0);
@@ -659,25 +671,25 @@ MPT_InitializeAdapter(
PHY_LCCalibrate(pAdapter);
PHY_IQCalibrate(pAdapter, _FALSE);
- /* dm_CheckTXPowerTracking(&pHalData->odmpriv); */ /* trigger thermal meter */
+ /* dm_check_txpowertracking(&pHalData->odmpriv); */ /* trigger thermal meter */
PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); /* default use Main */
- pMptCtx->backup0xc50 = (u1Byte)PHY_QueryBBReg(pAdapter, rOFDM0_XAAGCCore1, bMaskByte0);
- pMptCtx->backup0xc58 = (u1Byte)PHY_QueryBBReg(pAdapter, rOFDM0_XBAGCCore1, bMaskByte0);
- pMptCtx->backup0xc30 = (u1Byte)PHY_QueryBBReg(pAdapter, rOFDM0_RxDetector1, bMaskByte0);
- pMptCtx->backup0x52_RF_A = (u1Byte)PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
- pMptCtx->backup0x52_RF_B = (u1Byte)PHY_QueryRFReg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0);
+ pMptCtx->backup0xc50 = (u1Byte)phy_query_bb_reg(pAdapter, rOFDM0_XAAGCCore1, bMaskByte0);
+ pMptCtx->backup0xc58 = (u1Byte)phy_query_bb_reg(pAdapter, rOFDM0_XBAGCCore1, bMaskByte0);
+ pMptCtx->backup0xc30 = (u1Byte)phy_query_bb_reg(pAdapter, rOFDM0_RxDetector1, bMaskByte0);
+ pMptCtx->backup0x52_RF_A = (u1Byte)phy_query_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
+ pMptCtx->backup0x52_RF_B = (u1Byte)phy_query_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0);
#ifdef CONFIG_RTL8188E
rtw_write32(pAdapter, REG_MACID_NO_LINK_0, 0x0);
rtw_write32(pAdapter, REG_MACID_NO_LINK_1, 0x0);
#endif
#ifdef CONFIG_RTL8814A
if (IS_HARDWARE_TYPE_8814A(pAdapter)) {
- pHalData->BackUp_IG_REG_4_Chnl_Section[0] = (u1Byte)PHY_QueryBBReg(pAdapter, rA_IGI_Jaguar, bMaskByte0);
- pHalData->BackUp_IG_REG_4_Chnl_Section[1] = (u1Byte)PHY_QueryBBReg(pAdapter, rB_IGI_Jaguar, bMaskByte0);
- pHalData->BackUp_IG_REG_4_Chnl_Section[2] = (u1Byte)PHY_QueryBBReg(pAdapter, rC_IGI_Jaguar2, bMaskByte0);
- pHalData->BackUp_IG_REG_4_Chnl_Section[3] = (u1Byte)PHY_QueryBBReg(pAdapter, rD_IGI_Jaguar2, bMaskByte0);
+ pHalData->BackUp_IG_REG_4_Chnl_Section[0] = (u1Byte)phy_query_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0);
+ pHalData->BackUp_IG_REG_4_Chnl_Section[1] = (u1Byte)phy_query_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0);
+ pHalData->BackUp_IG_REG_4_Chnl_Section[2] = (u1Byte)phy_query_bb_reg(pAdapter, rC_IGI_Jaguar2, bMaskByte0);
+ pHalData->BackUp_IG_REG_4_Chnl_Section[3] = (u1Byte)phy_query_bb_reg(pAdapter, rD_IGI_Jaguar2, bMaskByte0);
}
#endif
return rtStatus;
@@ -705,7 +717,7 @@ MPT_DeInitAdapter(
IN PADAPTER pAdapter
)
{
- PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx;
+ PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.mpt_ctx;
pMptCtx->bMptDrvUnload = _TRUE;
#if defined(CONFIG_RTL8723B)
@@ -713,7 +725,7 @@ MPT_DeInitAdapter(
_cancel_timer_ex(&pMptCtx->MPh2c_timeout_timer);
#endif
#if defined(CONFIG_RTL8723B)
- PHY_SetBBReg(pAdapter, 0xA01, BIT0, 1); /* /suggestion by jerry for MP Rx. */
+ phy_set_bb_reg(pAdapter, 0xA01, BIT0, 1); /* /suggestion by jerry for MP Rx. */
#endif
#if 0 /* for Windows */
PlatformFreeWorkItem(&(pMptCtx->MptWorkItem));
@@ -728,15 +740,15 @@ MPT_DeInitAdapter(
static u8 mpt_ProStartTest(PADAPTER padapter)
{
- PMPT_CONTEXT pMptCtx = &padapter->mppriv.MptCtx;
+ PMPT_CONTEXT pMptCtx = &padapter->mppriv.mpt_ctx;
pMptCtx->bMassProdTest = _TRUE;
- pMptCtx->bStartContTx = _FALSE;
+ pMptCtx->is_start_cont_tx = _FALSE;
pMptCtx->bCckContTx = _FALSE;
pMptCtx->bOfdmContTx = _FALSE;
pMptCtx->bSingleCarrier = _FALSE;
- pMptCtx->bCarrierSuppression = _FALSE;
- pMptCtx->bSingleTone = _FALSE;
+ pMptCtx->is_carrier_suppression = _FALSE;
+ pMptCtx->is_single_tone = _FALSE;
pMptCtx->HWTxmode = PACKETS_TX;
return _SUCCESS;
@@ -757,63 +769,66 @@ void GetPowerTracking(PADAPTER padapter, u8 *enable)
hal_mpt_GetPowerTracking(padapter, enable);
}
-static void disable_dm(PADAPTER padapter)
+void rtw_mp_trigger_iqk(PADAPTER padapter)
+{
+ PHY_IQCalibrate(padapter, _FALSE);
+}
+
+void rtw_mp_trigger_lck(PADAPTER padapter)
+{
+ PHY_LCCalibrate(padapter);
+}
+
+static void init_mp_data(PADAPTER padapter)
{
u8 v8;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
- PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
+ struct dm_struct *pDM_Odm = &pHalData->odmpriv;
- /* 3 1. disable firmware dynamic mechanism */
- /* disable Power Training, Rate Adaptive */
+ /*disable BCN*/
v8 = rtw_read8(padapter, REG_BCN_CTRL);
v8 &= ~EN_BCN_FUNCTION;
rtw_write8(padapter, REG_BCN_CTRL, v8);
- /* 3 2. disable driver dynamic mechanism */
- rtw_phydm_func_disable_all(padapter);
-
- /* enable APK, LCK and IQK but disable power tracking */
- pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _FALSE;
- rtw_phydm_func_set(padapter, ODM_RF_CALIBRATION);
-
- /* #ifdef CONFIG_BT_COEXIST */
- /* rtw_btcoex_Switch(padapter, 0); */ /* remove for BT MP Down. */
- /* #endif */
+ pDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE;
}
-
void MPT_PwrCtlDM(PADAPTER padapter, u32 bstart)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
- PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
+ struct dm_struct *pDM_Odm = &pHalData->odmpriv;
+ u32 rf_ability;
if (bstart == 1) {
RTW_INFO("in MPT_PwrCtlDM start\n");
- rtw_phydm_func_set(padapter, ODM_RF_TX_PWR_TRACK | ODM_RF_CALIBRATION);
- pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _TRUE;
+ rf_ability = ((u32)halrf_cmn_info_get(pDM_Odm, HALRF_CMNINFO_ABILITY)) | HAL_RF_TX_PWR_TRACK;
+ halrf_cmn_info_set(pDM_Odm, HALRF_CMNINFO_ABILITY, rf_ability);
+
+ pDM_Odm->rf_calibrate_info.txpowertrack_control = _TRUE;
padapter->mppriv.mp_dm = 1;
} else {
RTW_INFO("in MPT_PwrCtlDM stop\n");
- disable_dm(padapter);
- pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _FALSE;
+ rf_ability = ((u32)halrf_cmn_info_get(pDM_Odm, HALRF_CMNINFO_ABILITY)) & ~HAL_RF_TX_PWR_TRACK;
+ halrf_cmn_info_set(pDM_Odm, HALRF_CMNINFO_ABILITY, rf_ability);
+ pDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE;
padapter->mppriv.mp_dm = 0;
{
- TXPWRTRACK_CFG c;
+ struct txpwrtrack_cfg c;
u1Byte chnl = 0 ;
- _rtw_memset(&c, 0, sizeof(TXPWRTRACK_CFG));
- ConfigureTxpowerTrack(pDM_Odm, &c);
- ODM_ClearTxPowerTrackingState(pDM_Odm);
- if (*c.ODM_TxPwrTrackSetPwr) {
- if (pDM_Odm->SupportICType == ODM_RTL8188F)
- (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, chnl);
- else if (pDM_Odm->SupportICType == ODM_RTL8723D) {
- (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, ODM_RF_PATH_A, chnl);
+ _rtw_memset(&c, 0, sizeof(struct txpwrtrack_cfg));
+ configure_txpower_track(pDM_Odm, &c);
+ odm_clear_txpowertracking_state(pDM_Odm);
+ if (*c.odm_tx_pwr_track_set_pwr) {
+ if (pDM_Odm->support_ic_type == ODM_RTL8188F)
+ (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, MIX_MODE, RF_PATH_A, chnl);
+ else if (pDM_Odm->support_ic_type == ODM_RTL8723D) {
+ (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, RF_PATH_A, chnl);
SetTxPower(padapter);
} else {
- (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, ODM_RF_PATH_A, chnl);
- (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, ODM_RF_PATH_B, chnl);
+ (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, RF_PATH_A, chnl);
+ (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, RF_PATH_B, chnl);
}
}
}
@@ -827,7 +842,7 @@ u32 mp_join(PADAPTER padapter, u8 mode)
WLAN_BSSID_EX bssid;
struct sta_info *psta;
u32 length;
- u8 val8;
+ u8 val8, join_type;
_irqL irqL;
s32 res = _SUCCESS;
@@ -877,7 +892,7 @@ u32 mp_join(PADAPTER padapter, u8 mode)
/* init mp_start_test status */
if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {
- rtw_disassoc_cmd(padapter, 500, _TRUE);
+ rtw_disassoc_cmd(padapter, 500, 0);
rtw_indicate_disconnect(padapter, 0, _FALSE);
rtw_free_assoc_resources(padapter, 1);
}
@@ -895,16 +910,18 @@ u32 mp_join(PADAPTER padapter, u8 mode)
psta = rtw_alloc_stainfo(&padapter->stapriv, bssid.MacAddress);
if (psta == NULL) {
- RT_TRACE(_module_mp_, _drv_err_, ("mp_start_test: Can't alloc sta_info!\n"));
/*pmlmepriv->fw_state = pmppriv->prev_fw_state;*/
init_fwstate(pmlmepriv, pmppriv->prev_fw_state);
res = _FAIL;
goto end_of_mp_start_test;
}
+ if (mode == WIFI_FW_ADHOC_STATE)
set_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
+ else
+ set_fwstate(pmlmepriv, WIFI_STATION_STATE);
/* 3 3. join psudo AdHoc */
tgt_network->join_res = 1;
- tgt_network->aid = psta->aid = 1;
+ tgt_network->aid = psta->cmn.aid = 1;
_rtw_memcpy(&padapter->registrypriv.dev_network, &bssid, length);
rtw_update_registrypriv_dev_network(padapter);
@@ -922,10 +939,12 @@ u32 mp_join(PADAPTER padapter, u8 mode)
if (1) { /* (res == _SUCCESS) */
/* set MSR to WIFI_FW_ADHOC_STATE */
if (mode == WIFI_FW_ADHOC_STATE) {
-
- val8 = rtw_read8(padapter, MSR) & 0xFC; /* 0x0102 */
- val8 |= WIFI_FW_ADHOC_STATE;
- rtw_write8(padapter, MSR, val8); /* Link in ad hoc network */
+ /* set msr to WIFI_FW_ADHOC_STATE */
+ pmlmeinfo->state = WIFI_FW_ADHOC_STATE;
+ Set_MSR(padapter, (pmlmeinfo->state & 0x3));
+ rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, padapter->registrypriv.dev_network.MacAddress);
+ rtw_hal_rcr_set_chk_bssid(padapter, MLME_ADHOC_STARTED);
+ pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS;
} else {
Set_MSR(padapter, WIFI_FW_STATION_STATE);
@@ -947,17 +966,10 @@ s32 mp_start_test(PADAPTER padapter)
padapter->registrypriv.mp_mode = 1;
- /* 3 disable dynamic mechanism */
- disable_dm(padapter);
+ init_mp_data(padapter);
#ifdef CONFIG_RTL8814A
rtl8814_InitHalDm(padapter);
#endif /* CONFIG_RTL8814A */
-#ifdef CONFIG_RTL8822B
- rtl8822b_phy_init_haldm(padapter);
-#endif /* CONFIG_RTL8822B */
-#ifdef CONFIG_RTL8821C
- rtl8821c_phy_init_haldm(padapter);
-#endif /* CONFIG_RTL8821C */
#ifdef CONFIG_RTL8812A
rtl8812_InitHalDm(padapter);
#endif /* CONFIG_RTL8812A */
@@ -973,13 +985,16 @@ s32 mp_start_test(PADAPTER padapter)
#ifdef CONFIG_RTL8188F
rtl8188f_InitHalDm(padapter);
#endif
+#ifdef CONFIG_RTL8188E
+ rtl8188e_InitHalDm(padapter);
+#endif
#ifdef CONFIG_RTL8723D
rtl8723d_InitHalDm(padapter);
#endif /* CONFIG_RTL8723D */
/* 3 0. update mp_priv */
- if (padapter->registrypriv.rf_config == RF_MAX_TYPE) {
+ if (!RF_TYPE_VALID(padapter->registrypriv.rf_config)) {
/* switch (phal->rf_type) { */
switch (GET_RF_TYPE(padapter)) {
case RF_1T1R:
@@ -992,7 +1007,6 @@ s32 mp_start_test(PADAPTER padapter)
pmppriv->antenna_rx = ANTENNA_AB;
break;
case RF_2T2R:
- case RF_2T2R_GREEN:
pmppriv->antenna_tx = ANTENNA_AB;
pmppriv->antenna_rx = ANTENNA_AB;
break;
@@ -1107,7 +1121,6 @@ static VOID mpt_AdjustRFRegByRateByChan92CU(PADAPTER pAdapter, u8 RateIdx, u8 Ch
}
}
- /* RT_TRACE(COMP_CMD, DBG_LOUD, ("\n mpt_AdjustRFRegByRateByChan92CU():Chan:%d Rate=%d rfReg0x26:0x%08x\n",Channel, RateIdx,rfReg0x26)); */
for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++)
write_rfreg(pAdapter, eRFPath, RF_SYN_G2, rfReg0x26);
}
@@ -1141,11 +1154,6 @@ static void MPT_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
hal_mpt_CCKTxPowerAdjust(Adapter, bInCH14);
}
-static void MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, BOOLEAN beven)
-{
- hal_mpt_CCKTxPowerAdjustbyIndex(pAdapter, beven);
-}
-
/*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/
/*
@@ -1206,6 +1214,17 @@ void MP_PHY_SetRFPathSwitch(PADAPTER pAdapter , BOOLEAN bMain)
}
+void mp_phy_switch_rf_path_set(PADAPTER pAdapter , u8 *pstate)
+{
+
+ phy_switch_rf_path_set(pAdapter, pstate);
+
+}
+
+u8 MP_PHY_QueryRFPathSwitch(PADAPTER pAdapter)
+{
+ return PHY_QueryRFPathSwitch(pAdapter);
+}
s32 SetThermalMeter(PADAPTER pAdapter, u8 target_ther)
{
@@ -1245,18 +1264,6 @@ void SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
hal_mpt_SetCarrierSuppressionTx(pAdapter, bStart);
}
-void SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart)
-{
- PhySetTxPowerLevel(pAdapter);
- hal_mpt_SetCCKContinuousTx(pAdapter, bStart);
-}
-
-void SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart)
-{
- PhySetTxPowerLevel(pAdapter);
- hal_mpt_SetOFDMContinuousTx(pAdapter, bStart);
-} /* mpt_StartOfdmContTx */
-
void SetContinuousTx(PADAPTER pAdapter, u8 bStart)
{
PhySetTxPowerLevel(pAdapter);
@@ -1268,25 +1275,9 @@ void PhySetTxPowerLevel(PADAPTER pAdapter)
{
struct mp_priv *pmp_priv = &pAdapter->mppriv;
- if (pmp_priv->bSetTxPower == 0) { /* for NO manually set power index */
-#ifdef CONFIG_RTL8188E
- PHY_SetTxPowerLevel8188E(pAdapter, pmp_priv->channel);
-#endif
-#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
- PHY_SetTxPowerLevel8812(pAdapter, pmp_priv->channel);
-#endif
-#if defined(CONFIG_RTL8192E)
- PHY_SetTxPowerLevel8192E(pAdapter, pmp_priv->channel);
-#endif
-#if defined(CONFIG_RTL8723B)
- PHY_SetTxPowerLevel8723B(pAdapter, pmp_priv->channel);
-#endif
-#if defined(CONFIG_RTL8188F)
- PHY_SetTxPowerLevel8188F(pAdapter, pmp_priv->channel);
-#endif
- mpt_ProQueryCalTxPower(pAdapter, pmp_priv->antenna_tx);
- }
+ if (pmp_priv->bSetTxPower == 0) /* for NO manually set power index */
+ rtw_hal_set_tx_power_level(pAdapter, pmp_priv->channel);
}
/* ------------------------------------------------------------------------------ */
@@ -1322,6 +1313,48 @@ static struct xmit_frame *alloc_mp_xmitframe(struct xmit_priv *pxmitpriv)
}
+#ifdef CONFIG_PCIE_HCI
+static u8 check_nic_enough_desc(_adapter *padapter, struct pkt_attrib *pattrib)
+{
+ u32 prio;
+ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+ struct rtw_tx_ring *ring;
+
+ switch (pattrib->qsel) {
+ case 0:
+ case 3:
+ prio = BE_QUEUE_INX;
+ break;
+ case 1:
+ case 2:
+ prio = BK_QUEUE_INX;
+ break;
+ case 4:
+ case 5:
+ prio = VI_QUEUE_INX;
+ break;
+ case 6:
+ case 7:
+ prio = VO_QUEUE_INX;
+ break;
+ default:
+ prio = BE_QUEUE_INX;
+ break;
+ }
+
+ ring = &pxmitpriv->tx_ring[prio];
+
+ /*
+ * for now we reserve two free descriptor as a safety boundary
+ * between the tail and the head
+ */
+ if ((ring->entries - ring->qlen) >= 2)
+ return _TRUE;
+ else
+ return _FALSE;
+}
+#endif
+
static thread_return mp_xmit_packet_thread(thread_context context)
{
struct xmit_frame *pxmitframe;
@@ -1340,6 +1373,12 @@ static thread_return mp_xmit_packet_thread(thread_context context)
RTW_INFO("%s:pkTx Start\n", __func__);
while (1) {
pxmitframe = alloc_mp_xmitframe(pxmitpriv);
+#ifdef CONFIG_PCIE_HCI
+ if(check_nic_enough_desc(padapter, &pmptx->attrib) == _FALSE) {
+ rtw_usleep_os(1000);
+ continue;
+ }
+#endif
if (pxmitframe == NULL) {
if (pmptx->stop ||
RTW_CANNOT_RUN(padapter))
@@ -1375,7 +1414,8 @@ static thread_return mp_xmit_packet_thread(thread_context context)
pmptx->pallocated_buf = NULL;
pmptx->stop = 1;
- thread_exit();
+ thread_exit(NULL);
+ return 0;
}
void fill_txdesc_for_mp(PADAPTER padapter, u8 *ptxdesc)
@@ -1738,13 +1778,13 @@ static void Rtw_MPSetMacTxEDCA(PADAPTER padapter)
rtw_write32(padapter, 0x508 , 0x00a422); /* Disable EDCA BE Txop for MP pkt tx adjust Packet interval */
/* RTW_INFO("%s:write 0x508~~~~~~ 0x%x\n", __func__,rtw_read32(padapter, 0x508)); */
- PHY_SetMacReg(padapter, 0x458 , bMaskDWord , 0x0);
- /* RTW_INFO("%s()!!!!! 0x460 = 0x%x\n" ,__func__,PHY_QueryBBReg(padapter, 0x460, bMaskDWord)); */
- PHY_SetMacReg(padapter, 0x460 , bMaskLWord , 0x0); /* fast EDCA queue packet interval & time out vaule */
- /* PHY_SetMacReg(padapter, ODM_EDCA_VO_PARAM ,bMaskLWord , 0x431C); */
- /* PHY_SetMacReg(padapter, ODM_EDCA_BE_PARAM ,bMaskLWord , 0x431C); */
- /* PHY_SetMacReg(padapter, ODM_EDCA_BK_PARAM ,bMaskLWord , 0x431C); */
- RTW_INFO("%s()!!!!! 0x460 = 0x%x\n" , __func__, PHY_QueryBBReg(padapter, 0x460, bMaskDWord));
+ phy_set_mac_reg(padapter, 0x458 , bMaskDWord , 0x0);
+ /*RTW_INFO("%s()!!!!! 0x460 = 0x%x\n" ,__func__, phy_query_bb_reg(padapter, 0x460, bMaskDWord));*/
+ phy_set_mac_reg(padapter, 0x460 , bMaskLWord , 0x0); /* fast EDCA queue packet interval & time out value*/
+ /*phy_set_mac_reg(padapter, ODM_EDCA_VO_PARAM ,bMaskLWord , 0x431C);*/
+ /*phy_set_mac_reg(padapter, ODM_EDCA_BE_PARAM ,bMaskLWord , 0x431C);*/
+ /*phy_set_mac_reg(padapter, ODM_EDCA_BK_PARAM ,bMaskLWord , 0x431C);*/
+ RTW_INFO("%s()!!!!! 0x460 = 0x%x\n" , __func__, phy_query_bb_reg(padapter, 0x460, bMaskDWord));
}
@@ -1772,13 +1812,12 @@ void SetPacketTx(PADAPTER padapter)
_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
_rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);
bmcast = IS_MCAST(pattrib->ra);
- if (bmcast) {
- pattrib->mac_id = 1;
+ if (bmcast)
pattrib->psta = rtw_get_bcmc_stainfo(padapter);
- } else {
- pattrib->mac_id = 0;
+ else
pattrib->psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv));
- }
+
+ pattrib->mac_id = pattrib->psta->cmn.mac_id;
pattrib->mbssid = 0;
pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->pktlen;
@@ -1853,9 +1892,8 @@ void SetPacketTx(PADAPTER padapter)
/* 3 4. make wlan header, make_wlanhdr() */
hdr = (struct rtw_ieee80211_hdr *)pkt_start;
- SetFrameSubType(&hdr->frame_ctl, pattrib->subtype);
- /* */
- SetFrDs(&hdr->frame_ctl);
+ set_frame_sub_type(&hdr->frame_ctl, pattrib->subtype);
+
_rtw_memcpy(hdr->addr1, pattrib->dst, ETH_ALEN); /* DA */
_rtw_memcpy(hdr->addr2, pattrib->src, ETH_ALEN); /* SA */
_rtw_memcpy(hdr->addr3, get_bssid(&padapter->mlmepriv), ETH_ALEN); /* RA, BSSID */
@@ -1898,8 +1936,10 @@ void SetPacketTx(PADAPTER padapter)
/* 3 6. start thread */
#ifdef PLATFORM_LINUX
pmp_priv->tx.PktTxThread = kthread_run(mp_xmit_packet_thread, pmp_priv, "RTW_MP_THREAD");
- if (IS_ERR(pmp_priv->tx.PktTxThread))
- RTW_INFO("Create PktTx Thread Fail !!!!!\n");
+ if (IS_ERR(pmp_priv->tx.PktTxThread)) {
+ RTW_ERR("Create PktTx Thread Fail !!!!!\n");
+ pmp_priv->tx.PktTxThread = NULL;
+ }
#endif
#ifdef PLATFORM_FREEBSD
{
@@ -1926,7 +1966,7 @@ void SetPacketRx(PADAPTER pAdapter, u8 bStartRx, u8 bAB)
if (bStartRx) {
#ifdef CONFIG_RTL8723B
- PHY_SetMacReg(pAdapter, 0xe70, BIT23 | BIT22, 0x3); /* Power on adc (in RX_WAIT_CCA state) */
+ phy_set_mac_reg(pAdapter, 0xe70, BIT23 | BIT22, 0x3); /* Power on adc (in RX_WAIT_CCA state) */
write_bbreg(pAdapter, 0xa01, BIT0, bDisable);/* improve Rx performance by jerry */
#endif
pHalData->ReceiveConfig = RCR_AAP | RCR_APM | RCR_AM | RCR_AMF | RCR_HTC_LOC_CTRL;
@@ -1936,13 +1976,17 @@ void SetPacketRx(PADAPTER pAdapter, u8 bStartRx, u8 bAB)
if (pmppriv->bSetRxBssid == _TRUE) {
RTW_INFO("%s: pmppriv->network_macaddr=" MAC_FMT "\n", __func__,
MAC_ARG(pmppriv->network_macaddr));
+ pHalData->ReceiveConfig = 0;
+ pHalData->ReceiveConfig |= RCR_CBSSID_DATA | RCR_CBSSID_BCN |RCR_APM | RCR_AM | RCR_AB |RCR_AMF;
+ pHalData->ReceiveConfig |= RCR_APP_PHYST_RXFF;
+
+#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
+ write_bbreg(pAdapter, 0x550, BIT3, bEnable);
+#endif
+ rtw_write16(pAdapter, REG_RXFLTMAP0, 0xFFEF); /* REG_RXFLTMAP0 (RX Filter Map Group 0) */
- /* Set_MSR(pAdapter, WIFI_FW_AP_STATE); */
- /* rtw_hal_set_hwreg(pAdapter, HW_VAR_BSSID, pmppriv->network_macaddr); */
- /* rtw_hal_set_hwreg(pAdapter, HW_VAR_SET_OPMODE, (u8 *)(&type)); */
} else {
pHalData->ReceiveConfig |= RCR_ADF;
-
/* Accept all data frames */
rtw_write16(pAdapter, REG_RXFLTMAP2, 0xFFFF);
}
@@ -1951,10 +1995,11 @@ void SetPacketRx(PADAPTER pAdapter, u8 bStartRx, u8 bAB)
pHalData->ReceiveConfig |= RCR_AB;
} else {
#ifdef CONFIG_RTL8723B
- PHY_SetMacReg(pAdapter, 0xe70, BIT23 | BIT22, 0x00); /* Power off adc (in RX_WAIT_CCA state) */
+ phy_set_mac_reg(pAdapter, 0xe70, BIT23 | BIT22, 0x00); /* Power off adc (in RX_WAIT_CCA state)*/
write_bbreg(pAdapter, 0xa01, BIT0, bEnable);/* improve Rx performance by jerry */
#endif
pHalData->ReceiveConfig = 0;
+ rtw_write16(pAdapter, REG_RXFLTMAP0, 0xFFFF); /* REG_RXFLTMAP0 (RX Filter Map Group 0) */
}
rtw_write32(pAdapter, REG_RCR, pHalData->ReceiveConfig);
@@ -2036,7 +2081,11 @@ static u32 rtw_GetPSDData(PADAPTER pAdapter, u32 point)
rtw_mdelay_os(1);
psd_val = rtw_read32(pAdapter, psd_regL);
+#if defined(CONFIG_RTL8821C)
+ psd_val = (psd_val & 0x00FFFFFF) / 32;
+#else
psd_val &= 0x0000FFFF;
+#endif
return psd_val;
}
@@ -2057,13 +2106,11 @@ u32 mp_query_psd(PADAPTER pAdapter, u8 *data)
#ifdef PLATFORM_LINUX
if (!netif_running(pAdapter->pnetdev)) {
- RT_TRACE(_module_mp_, _drv_warning_, ("mp_query_psd: Fail! interface not opened!\n"));
return 0;
}
#endif
if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
- RT_TRACE(_module_mp_, _drv_warning_, ("mp_query_psd: Fail! not in MP mode!\n"));
return 0;
}
@@ -2138,7 +2185,6 @@ void _rtw_mp_xmit_priv(struct xmit_priv *pxmitpriv)
pxmitpriv->pallocated_xmit_extbuf = rtw_zvmalloc(num_xmit_extbuf * sizeof(struct xmit_buf) + 4);
if (pxmitpriv->pallocated_xmit_extbuf == NULL) {
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("alloc xmit_extbuf fail!\n"));
res = _FAIL;
goto exit;
}
@@ -2182,284 +2228,8 @@ void _rtw_mp_xmit_priv(struct xmit_priv *pxmitpriv)
}
#endif
-
-ULONG getPowerDiffByRate8188E(
- IN PADAPTER pAdapter,
- IN u1Byte CurrChannel,
- IN ULONG RfPath
-)
-{
- PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
- ULONG PwrGroup = 0;
- ULONG TxPower = 0, Limit = 0;
- ULONG Pathmapping = (RfPath == ODM_RF_PATH_A ? 0 : 8);
-
- switch (pHalData->EEPROMRegulatory) {
- case 0: /* driver-defined maximum power offset for longer communication range */
- /* refer to power by rate table */
- PwrGroup = 0;
- Limit = 0xff;
- break;
- case 1: /* Power-limit table-defined maximum power offset range */
- /* choosed by min(power by rate, power limit). */
- {
- if (pHalData->pwrGroupCnt == 1)
- PwrGroup = 0;
- if (pHalData->pwrGroupCnt >= 3) {
- if (CurrChannel <= 3)
- PwrGroup = 0;
- else if (CurrChannel >= 4 && CurrChannel <= 9)
- PwrGroup = 1;
- else if (CurrChannel > 9)
- PwrGroup = 2;
-
- if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_20)
- PwrGroup++;
- else
- PwrGroup += 4;
- }
- Limit = 0xff;
- }
- break;
- case 2: /* not support power offset by rate. */
- /* don't increase any power diff */
- PwrGroup = 0;
- Limit = 0;
- break;
- default:
- PwrGroup = 0;
- Limit = 0xff;
- break;
- }
-
-
- {
- switch (pMptCtx->MptRateIndex) {
- case MPT_RATE_1M:
- case MPT_RATE_2M:
- case MPT_RATE_55M:
- case MPT_RATE_11M:
- /* CCK rates, don't add any tx power index. */
- /* RT_DISP(FPHY, PHY_TXPWR,("CCK rates!\n")); */
- break;
- case MPT_RATE_6M: /* 0xe00 [31:0] = 18M,12M,09M,06M */
- TxPower += ((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][0 + Pathmapping]) & 0xff);
- /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x, OFDM 6M, TxPower = %d\n", */
- /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][0], TxPower)); */
- break;
- case MPT_RATE_9M:
- TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][0 + Pathmapping]) & 0xff00) >> 8);
- /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x, OFDM 9M, TxPower = %d\n", */
- /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][0], TxPower)); */
- break;
- case MPT_RATE_12M:
- TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][0 + Pathmapping]) & 0xff0000) >> 16);
- /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x, OFDM 12M, TxPower = %d\n", */
- /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][0], TxPower)); */
- break;
- case MPT_RATE_18M:
- TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][0 + Pathmapping]) & 0xff000000) >> 24);
- /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x, OFDM 24M, TxPower = %d\n", */
- /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][0], TxPower)); */
- break;
- case MPT_RATE_24M: /* 0xe04[31:0] = 54M,48M,36M,24M */
- TxPower += ((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][1 + Pathmapping]) & 0xff);
- /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x, OFDM 24M, TxPower = %d\n", */
- /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][1], TxPower)); */
- break;
- case MPT_RATE_36M:
- TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][1 + Pathmapping]) & 0xff00) >> 8);
- /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x, OFDM 36M, TxPower = %d\n", */
- /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][1], TxPower)); */
- break;
- case MPT_RATE_48M:
- TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][1 + Pathmapping]) & 0xff0000) >> 16);
- /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x, OFDM 48M, TxPower = %d\n", */
- /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][1], TxPower)); */
- break;
- case MPT_RATE_54M:
- TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][1 + Pathmapping]) & 0xff000000) >> 24);
- /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x, OFDM 54M, TxPower = %d\n", */
- /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][1], TxPower)); */
- break;
- case MPT_RATE_MCS0: /* 0xe10[31:0]= MCS=03,02,01,00 */
- TxPower += ((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][2 + Pathmapping]) & 0xff);
- /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x, MCS0, TxPower = %d\n", */
- /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][2], TxPower)); */
- break;
- case MPT_RATE_MCS1:
- TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][2 + Pathmapping]) & 0xff00) >> 8);
- /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x, MCS1, TxPower = %d\n", */
- /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][2], TxPower)); */
- break;
- case MPT_RATE_MCS2:
- TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][2 + Pathmapping]) & 0xff0000) >> 16);
- /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x, MCS2, TxPower = %d\n", */
- /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][2], TxPower)); */
- break;
- case MPT_RATE_MCS3:
- TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][2 + Pathmapping]) & 0xff000000) >> 24);
- /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x, MCS3, TxPower = %d\n", */
- /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][2], TxPower)); */
- break;
- case MPT_RATE_MCS4: /* 0xe14[31:0]= MCS=07,06,05,04 */
- TxPower += ((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][3 + Pathmapping]) & 0xff);
- /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x, MCS4, TxPower = %d\n", */
- /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][3], TxPower)); */
- break;
- case MPT_RATE_MCS5:
- TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][3 + Pathmapping]) & 0xff00) >> 8);
- /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x, MCS5, TxPower = %d\n", */
- /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][3], TxPower)); */
- break;
- case MPT_RATE_MCS6:
- TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][3 + Pathmapping]) & 0xff0000) >> 16);
- /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x, MCS6, TxPower = %d\n", */
- /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][3], TxPower)); */
- break;
- case MPT_RATE_MCS7:
- TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][3 + Pathmapping]) & 0xff000000) >> 24);
- /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x, MCS7, TxPower = %d\n", */
- /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][3], TxPower)); */
- break;
-
- case MPT_RATE_MCS8: /* 0xe18[31:0]= MCS=11,10,09,08 */
- TxPower += ((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][4 + Pathmapping]) & 0xff);
- /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x, MCS8, TxPower = %d\n", */
- /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][4], TxPower)); */
- break;
- case MPT_RATE_MCS9:
- TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][4 + Pathmapping]) & 0xff00) >> 8);
- /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x, MCS9, TxPower = %d\n", */
- /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][4], TxPower)); */
- break;
- case MPT_RATE_MCS10:
- TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][4 + Pathmapping]) & 0xff0000) >> 16);
- /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x, MCS10, TxPower = %d\n", */
- /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][4], TxPower)); */
- break;
- case MPT_RATE_MCS11:
- TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][4 + Pathmapping]) & 0xff000000) >> 24);
- /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x, MCS11, TxPower = %d\n", */
- /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][4], TxPower)); */
- break;
- case MPT_RATE_MCS12: /* 0xe1c[31:0]= MCS=15,14,13,12 */
- TxPower += ((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][5 + Pathmapping]) & 0xff);
- /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x, MCS12, TxPower = %d\n", */
- /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][5], TxPower)); */
- break;
- case MPT_RATE_MCS13:
- TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][5 + Pathmapping]) & 0xff00) >> 8);
- /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x, MCS13, TxPower = %d\n", */
- /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][5], TxPower)); */
- break;
- case MPT_RATE_MCS14:
- TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][5 + Pathmapping]) & 0xff0000) >> 16);
- /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x, MCS14, TxPower = %d\n", */
- /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][5], TxPower)); */
- break;
- case MPT_RATE_MCS15:
- TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][5 + Pathmapping]) & 0xff000000) >> 24);
- /* RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x, MCS15, TxPower = %d\n", */
- /* PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][5], TxPower)); */
- break;
- default:
- break;
- }
- }
-
- if (TxPower > Limit)
- TxPower = Limit;
-
- return TxPower;
-}
-
-
-
-static ULONG
-mpt_ProQueryCalTxPower_8188E(
- IN PADAPTER pAdapter,
- IN u1Byte RfPath
-)
-{
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
- u1Byte TxCount = TX_1S, i = 0; /* default set to 1S */
- /* PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo); */
- ULONG TxPower = 1, PwrGroup = 0, PowerDiffByRate = 0;
- ULONG TxPowerCCK = 1, TxPowerOFDM = 1, TxPowerBW20 = 1, TxPowerBW40 = 1 ;
- PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
- u1Byte CurrChannel = pHalData->CurrentChannel;
- u1Byte index = (CurrChannel - 1);
- u1Byte rf_path = (RfPath), rfPath;
- u1Byte limit = 0, rate = 0;
-
- if (HAL_IsLegalChannel(pAdapter, CurrChannel) == FALSE)
- CurrChannel = 1;
-
- if (pMptCtx->MptRateIndex <= MPT_RATE_11M)
- TxPower = pHalData->Index24G_CCK_Base[rf_path][index];
- else if (pMptCtx->MptRateIndex >= MPT_RATE_6M &&
- pMptCtx->MptRateIndex <= MPT_RATE_54M)
- TxPower = pHalData->Index24G_BW40_Base[rf_path][index];
- else if (pMptCtx->MptRateIndex >= MPT_RATE_MCS0 &&
- pMptCtx->MptRateIndex <= MPT_RATE_MCS7)
- TxPower = pHalData->Index24G_BW40_Base[rf_path][index];
-
- /* RT_DISP(FPHY, PHY_TXPWR, ("HT40 rate(%d) Tx power(RF-%c) = 0x%x\n", pMptCtx->MptRateIndex, ((rf_path==0)?'A':'B'), TxPower)); */
-
-
- if (pMptCtx->MptRateIndex >= MPT_RATE_6M &&
- pMptCtx->MptRateIndex <= MPT_RATE_54M) {
- TxPower += pHalData->OFDM_24G_Diff[rf_path][TxCount];
- /* /RT_DISP(FPHY, PHY_TXPWR, ("+OFDM_PowerDiff(RF-%c) = 0x%x\n", ((rf_path==0)?'A':'B'), */
- /* pHalData->OFDM_24G_Diff[rf_path][TxCount])); */
- }
-
- if (pMptCtx->MptRateIndex >= MPT_RATE_MCS0) {
- if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_20) {
- TxPower += pHalData->BW20_24G_Diff[rf_path][TxCount];
- /* RT_DISP(FPHY, PHY_TXPWR, ("+HT20_PowerDiff(RF-%c) = 0x%x\n", ((rf_path==0)?'A':'B'), */
- /* pHalData->BW20_24G_Diff[rf_path][TxCount])); */
- }
- }
-
-
-#ifdef ENABLE_POWER_BY_RATE
- PowerDiffByRate = getPowerDiffByRate8188E(pAdapter, CurrChannel, RfPath);
-#else
- PowerDiffByRate = 0;
-#endif
-
- /* 2012/11/02 Awk: add power limit mechansim */
- if (pMptCtx->MptRateIndex <= MPT_RATE_11M)
- rate = MGN_1M;
- else if (pMptCtx->MptRateIndex >= MPT_RATE_6M &&
- pMptCtx->MptRateIndex <= MPT_RATE_54M)
- rate = MGN_54M;
- else if (pMptCtx->MptRateIndex >= MPT_RATE_MCS0 &&
- pMptCtx->MptRateIndex <= MPT_RATE_MCS7)
- rate = MGN_MCS7;
-
- limit = (u8)PHY_GetTxPowerLimit(pAdapter, pMptCtx->RegTxPwrLimit,
- pHalData->CurrentBandType,
- pHalData->CurrentChannelBW, RfPath,
- rate, CurrChannel);
-
- /* RT_DISP(FPHY, PHY_TXPWR, ("+PowerDiffByRate(RF-%c) = 0x%x\n", ((rf_path==0)?'A':'B'), */
- /* PowerDiffByRate)); */
- TxPower += PowerDiffByRate;
- /* RT_DISP(FPHY, PHY_TXPWR, ("PowerDiffByRate limit value(RF-%c) = %d\n", ((rf_path==0)?'A':'B'), */
- /* limit)); */
-
- TxPower += limit > (s8) PowerDiffByRate ? PowerDiffByRate : limit;
-
- return TxPower;
-}
-
-
u8
-MptToMgntRate(
+mpt_to_mgnt_rate(
IN ULONG MptRateIdx
)
{
@@ -2643,7 +2413,7 @@ MptToMgntRate(
case MPT_RATE_LAST: /* fully automatiMGN_VHT2SS_MCS1; */
default:
- RTW_INFO("<===MptToMgntRate(), Invalid Rate: %d!!\n", MptRateIdx);
+ RTW_INFO("<===mpt_to_mgnt_rate(), Invalid Rate: %d!!\n", MptRateIdx);
return 0x0;
}
}
@@ -2908,7 +2678,7 @@ u8 HwRateToMPTRate(u8 rate)
break;
default:
- RTW_INFO("HwRateToMRate(): Non supported Rate [%x]!!!\n", rate);
+ RTW_INFO("hw_rate_to_m_rate(): Non supported Rate [%x]!!!\n", rate);
break;
}
return ret_rate;
@@ -2944,6 +2714,17 @@ u8 rtw_mpRateParseFunc(PADAPTER pAdapter, u8 *targetStr)
return _FAIL;
}
+u8 rtw_mp_mode_check(PADAPTER pAdapter)
+{
+ PADAPTER primary_adapter = GET_PRIMARY_ADAPTER(pAdapter);
+
+ if (primary_adapter->registrypriv.mp_mode == 1)
+ return _TRUE;
+ else
+ return _FALSE;
+}
+
+
ULONG mpt_ProQueryCalTxPower(
PADAPTER pAdapter,
u8 RfPath
@@ -2951,65 +2732,24 @@ ULONG mpt_ProQueryCalTxPower(
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
- PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
+ PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
- ULONG TxPower = 1, PwrGroup = 0, PowerDiffByRate = 0;
- u1Byte limit = 0, rate = 0;
- u8 mgn_rate = MptToMgntRate(pMptCtx->MptRateIndex);
+ ULONG TxPower = 1;
+ u1Byte rate = 0;
+ struct txpwr_idx_comp tic;
+ u8 mgn_rate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
-#if defined(CONFIG_RTL8188E)
- if (IS_HARDWARE_TYPE_8188E(pAdapter))
- TxPower = PHY_GetTxPowerIndex_8188E(pAdapter, RfPath, mgn_rate, pHalData->CurrentChannelBW, pHalData->CurrentChannel);
-#endif
-
-#if defined(CONFIG_RTL8723B)
- if (IS_HARDWARE_TYPE_8723B(pAdapter))
- TxPower = PHY_GetTxPowerIndex_8723B(pAdapter, RfPath, mgn_rate, pHalData->CurrentChannelBW, pHalData->CurrentChannel);
-#endif
-
-#if defined(CONFIG_RTL8192E)
- if (IS_HARDWARE_TYPE_8192E(pAdapter))
- TxPower = PHY_GetTxPowerIndex_8192E(pAdapter, RfPath, mgn_rate, pHalData->CurrentChannelBW, pHalData->CurrentChannel);
-#endif
-
-#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
- if (IS_HARDWARE_TYPE_JAGUAR(pAdapter))
- TxPower = PHY_GetTxPowerIndex_8812A(pAdapter, RfPath, mgn_rate, pHalData->CurrentChannelBW, pHalData->CurrentChannel);
-#endif
-
-#if defined(CONFIG_RTL8814A)
- if (IS_HARDWARE_TYPE_8814A(pAdapter))
- TxPower = PHY_GetTxPowerIndex_8814A(pAdapter, RfPath, mgn_rate, pHalData->CurrentChannelBW, pHalData->CurrentChannel);
-#endif
-
-#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
- if (IS_HARDWARE_TYPE_8822B(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter))
- TxPower = rtw_hal_get_tx_power_index(pAdapter, RfPath, mgn_rate, pHalData->CurrentChannelBW, pHalData->CurrentChannel);
-#endif
-
-#if defined(CONFIG_RTL8703B)
- if (IS_HARDWARE_TYPE_8703B(pAdapter))
- TxPower = PHY_GetTxPowerIndex_8703B(pAdapter, RfPath, mgn_rate, pHalData->CurrentChannelBW, pHalData->CurrentChannel);
-#endif
-
-#if defined(CONFIG_RTL8188F)
- if (IS_HARDWARE_TYPE_8188F(pAdapter))
- TxPower = PHY_GetTxPowerIndex_8188F(pAdapter, RfPath, mgn_rate, pHalData->CurrentChannelBW, pHalData->CurrentChannel);
-#endif
-
-#if defined(CONFIG_RTL8723D)
- if (IS_HARDWARE_TYPE_8723D(pAdapter))
- TxPower = PHY_GetTxPowerIndex_8723D(pAdapter, RfPath, mgn_rate, pHalData->CurrentChannelBW, pHalData->CurrentChannel);
-#endif
+ TxPower = rtw_hal_get_tx_power_index(pAdapter, RfPath, mgn_rate, pHalData->current_channel_bw, pHalData->current_channel, &tic);
- RTW_INFO("txPower=%d ,CurrentChannelBW=%d ,CurrentChannel=%d ,rate =%d\n",
- TxPower, pHalData->CurrentChannelBW, pHalData->CurrentChannel, mgn_rate);
+ RTW_INFO("bw=%d, ch=%d, rate=%d, txPower:%u = %u + (%d=%d:%d) + (%d) + (%d)\n",
+ pHalData->current_channel_bw, pHalData->current_channel, mgn_rate
+ , TxPower, tic.base, (tic.by_rate > tic.limit ? tic.limit : tic.by_rate), tic.by_rate, tic.limit, tic.tpt, tic.ebias);
pAdapter->mppriv.txpoweridx = (u8)TxPower;
- pMptCtx->TxPwrLevel[ODM_RF_PATH_A] = (u8)TxPower;
- pMptCtx->TxPwrLevel[ODM_RF_PATH_B] = (u8)TxPower;
- pMptCtx->TxPwrLevel[ODM_RF_PATH_C] = (u8)TxPower;
- pMptCtx->TxPwrLevel[ODM_RF_PATH_D] = (u8)TxPower;
+ pMptCtx->TxPwrLevel[RF_PATH_A] = (u8)TxPower;
+ pMptCtx->TxPwrLevel[RF_PATH_B] = (u8)TxPower;
+ pMptCtx->TxPwrLevel[RF_PATH_C] = (u8)TxPower;
+ pMptCtx->TxPwrLevel[RF_PATH_D] = (u8)TxPower;
hal_mpt_SetTxPower(pAdapter);
return TxPower;
diff --git a/core/rtw_mp_ioctl.c b/core/rtw_mp_ioctl.c
index 0e7fee6..035d281 100644
--- a/core/rtw_mp_ioctl.c
+++ b/core/rtw_mp_ioctl.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,12 +11,7 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#define _RTW_MP_IOCTL_C_
#include
@@ -29,7 +24,6 @@ NDIS_STATUS oid_rt_wireless_mode_hdl(struct oid_par_priv *poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
- _func_enter_;
if (poid_par_priv->information_buf_len < sizeof(u8))
return NDIS_STATUS_INVALID_LENGTH;
@@ -39,11 +33,9 @@ NDIS_STATUS oid_rt_wireless_mode_hdl(struct oid_par_priv *poid_par_priv)
else if (poid_par_priv->type_of_oid == QUERY_OID) {
*(u8 *)poid_par_priv->information_buf = Adapter->registrypriv.wireless_mode;
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
- RT_TRACE(_module_mp_, _drv_info_, ("-query Wireless Mode=%d\n", Adapter->registrypriv.wireless_mode));
} else
status = NDIS_STATUS_NOT_ACCEPTED;
- _func_exit_;
return status;
}
@@ -59,9 +51,7 @@ NDIS_STATUS oid_rt_pro_write_bb_reg_hdl(struct oid_par_priv *poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
- _func_enter_;
- RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_write_bb_reg_hdl\n"));
if (poid_par_priv->type_of_oid != SET_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -77,15 +67,11 @@ NDIS_STATUS oid_rt_pro_write_bb_reg_hdl(struct oid_par_priv *poid_par_priv)
value = pbbreg->value;
- RT_TRACE(_module_mp_, _drv_notice_,
- ("oid_rt_pro_write_bb_reg_hdl: offset=0x%03X value=0x%08X\n",
- offset, value));
_irqlevel_changed_(&oldirql, LOWER);
write_bbreg(Adapter, offset, 0xFFFFFFFF, value);
_irqlevel_changed_(&oldirql, RAISE);
- _func_exit_;
return status;
}
@@ -101,9 +87,7 @@ NDIS_STATUS oid_rt_pro_read_bb_reg_hdl(struct oid_par_priv *poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
- _func_enter_;
- RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_read_bb_reg_hdl\n"));
if (poid_par_priv->type_of_oid != QUERY_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -124,10 +108,6 @@ NDIS_STATUS oid_rt_pro_read_bb_reg_hdl(struct oid_par_priv *poid_par_priv)
pbbreg->value = value;
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
- RT_TRACE(_module_mp_, _drv_notice_,
- ("-oid_rt_pro_read_bb_reg_hdl: offset=0x%03X value:0x%08X\n",
- offset, value));
- _func_exit_;
return status;
}
@@ -144,9 +124,7 @@ NDIS_STATUS oid_rt_pro_write_rf_reg_hdl(struct oid_par_priv *poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
- _func_enter_;
- RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_write_rf_reg_hdl\n"));
if (poid_par_priv->type_of_oid != SET_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -167,15 +145,11 @@ NDIS_STATUS oid_rt_pro_write_rf_reg_hdl(struct oid_par_priv *poid_par_priv)
offset = (u8)pbbreg->offset;
value = pbbreg->value;
- RT_TRACE(_module_mp_, _drv_notice_,
- ("oid_rt_pro_write_rf_reg_hdl: path=%d offset=0x%02X value=0x%05X\n",
- path, offset, value));
_irqlevel_changed_(&oldirql, LOWER);
write_rfreg(Adapter, path, offset, value);
_irqlevel_changed_(&oldirql, RAISE);
- _func_exit_;
return status;
}
@@ -192,9 +166,7 @@ NDIS_STATUS oid_rt_pro_read_rf_reg_hdl(struct oid_par_priv *poid_par_priv)
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
- _func_enter_;
- RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_read_rf_reg_hdl\n"));
if (poid_par_priv->type_of_oid != QUERY_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -220,11 +192,7 @@ NDIS_STATUS oid_rt_pro_read_rf_reg_hdl(struct oid_par_priv *poid_par_priv)
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
- RT_TRACE(_module_mp_, _drv_notice_,
- ("-oid_rt_pro_read_rf_reg_hdl: path=%d offset=0x%02X value=0x%05X\n",
- path, offset, value));
- _func_exit_;
return status;
}
@@ -242,10 +210,7 @@ NDIS_STATUS oid_rt_pro_set_data_rate_hdl(struct oid_par_priv *poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
- _func_enter_;
- RT_TRACE(_module_mp_, _drv_notice_,
- ("+oid_rt_pro_set_data_rate_hdl\n"));
if (poid_par_priv->type_of_oid != SET_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -254,8 +219,6 @@ NDIS_STATUS oid_rt_pro_set_data_rate_hdl(struct oid_par_priv *poid_par_priv)
return NDIS_STATUS_INVALID_LENGTH;
ratevalue = *((u32 *)poid_par_priv->information_buf); /* 4 */
- RT_TRACE(_module_mp_, _drv_notice_,
- ("oid_rt_pro_set_data_rate_hdl: data rate idx=%d\n", ratevalue));
if (ratevalue >= MPT_RATE_LAST)
return NDIS_STATUS_INVALID_DATA;
@@ -265,7 +228,6 @@ NDIS_STATUS oid_rt_pro_set_data_rate_hdl(struct oid_par_priv *poid_par_priv)
SetDataRate(Adapter);
_irqlevel_changed_(&oldirql, RAISE);
- _func_exit_;
return status;
}
@@ -279,9 +241,7 @@ NDIS_STATUS oid_rt_pro_start_test_hdl(struct oid_par_priv *poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
- _func_enter_;
- RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_start_test_hdl\n"));
if (Adapter->registrypriv.mp_mode == 0)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -304,9 +264,7 @@ NDIS_STATUS oid_rt_pro_start_test_hdl(struct oid_par_priv *poid_par_priv)
exit:
_irqlevel_changed_(&oldirql, RAISE);
- RT_TRACE(_module_mp_, _drv_notice_, ("-oid_rt_pro_start_test_hdl: mp_mode=%d\n", Adapter->mppriv.mode));
- _func_exit_;
return status;
}
@@ -319,9 +277,7 @@ NDIS_STATUS oid_rt_pro_stop_test_hdl(struct oid_par_priv *poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
- _func_enter_;
- RT_TRACE(_module_mp_, _drv_notice_, ("+Set OID_RT_PRO_STOP_TEST\n"));
if (poid_par_priv->type_of_oid != SET_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -330,9 +286,7 @@ NDIS_STATUS oid_rt_pro_stop_test_hdl(struct oid_par_priv *poid_par_priv)
mp_stop_test(Adapter);
_irqlevel_changed_(&oldirql, RAISE);
- RT_TRACE(_module_mp_, _drv_notice_, ("-Set OID_RT_PRO_STOP_TEST\n"));
- _func_exit_;
return status;
}
@@ -346,9 +300,7 @@ NDIS_STATUS oid_rt_pro_set_channel_direct_call_hdl(struct oid_par_priv *poid_par
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
- _func_enter_;
- RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_set_channel_direct_call_hdl\n"));
if (poid_par_priv->information_buf_len != sizeof(u32))
return NDIS_STATUS_INVALID_LENGTH;
@@ -362,7 +314,6 @@ NDIS_STATUS oid_rt_pro_set_channel_direct_call_hdl(struct oid_par_priv *poid_par
return NDIS_STATUS_NOT_ACCEPTED;
Channel = *((u32 *)poid_par_priv->information_buf);
- RT_TRACE(_module_mp_, _drv_notice_, ("oid_rt_pro_set_channel_direct_call_hdl: Channel=%d\n", Channel));
if (Channel > 14)
return NDIS_STATUS_NOT_ACCEPTED;
Adapter->mppriv.channel = Channel;
@@ -371,7 +322,6 @@ NDIS_STATUS oid_rt_pro_set_channel_direct_call_hdl(struct oid_par_priv *poid_par
SetChannel(Adapter);
_irqlevel_changed_(&oldirql, RAISE);
- _func_exit_;
return status;
}
@@ -386,10 +336,7 @@ NDIS_STATUS oid_rt_set_bandwidth_hdl(struct oid_par_priv *poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
- _func_enter_;
- RT_TRACE(_module_mp_, _drv_info_,
- ("+oid_rt_set_bandwidth_hdl\n"));
if (poid_par_priv->type_of_oid != SET_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -409,11 +356,7 @@ NDIS_STATUS oid_rt_set_bandwidth_hdl(struct oid_par_priv *poid_par_priv)
SetBandwidth(padapter);
_irqlevel_changed_(&oldirql, RAISE);
- RT_TRACE(_module_mp_, _drv_notice_,
- ("-oid_rt_set_bandwidth_hdl: bandwidth=%d channel_offset=%d\n",
- bandwidth, channel_offset));
- _func_exit_;
return status;
}
@@ -427,9 +370,7 @@ NDIS_STATUS oid_rt_pro_set_antenna_bb_hdl(struct oid_par_priv *poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
- _func_enter_;
- RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_set_antenna_bb_hdl\n"));
if (poid_par_priv->information_buf_len != sizeof(u32))
return NDIS_STATUS_INVALID_LENGTH;
@@ -439,9 +380,6 @@ NDIS_STATUS oid_rt_pro_set_antenna_bb_hdl(struct oid_par_priv *poid_par_priv)
Adapter->mppriv.antenna_tx = (u16)((antenna & 0xFFFF0000) >> 16);
Adapter->mppriv.antenna_rx = (u16)(antenna & 0x0000FFFF);
- RT_TRACE(_module_mp_, _drv_notice_,
- ("oid_rt_pro_set_antenna_bb_hdl: tx_ant=0x%04x rx_ant=0x%04x\n",
- Adapter->mppriv.antenna_tx, Adapter->mppriv.antenna_rx));
_irqlevel_changed_(&oldirql, LOWER);
SetAntenna(Adapter);
@@ -451,7 +389,6 @@ NDIS_STATUS oid_rt_pro_set_antenna_bb_hdl(struct oid_par_priv *poid_par_priv)
*(u32 *)poid_par_priv->information_buf = antenna;
}
- _func_exit_;
return status;
}
@@ -465,9 +402,7 @@ NDIS_STATUS oid_rt_pro_set_tx_power_control_hdl(struct oid_par_priv *poid_par_pr
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
- _func_enter_;
- RT_TRACE(_module_mp_, _drv_info_, ("+oid_rt_pro_set_tx_power_control_hdl\n"));
if (poid_par_priv->type_of_oid != SET_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -481,15 +416,11 @@ NDIS_STATUS oid_rt_pro_set_tx_power_control_hdl(struct oid_par_priv *poid_par_pr
Adapter->mppriv.txpoweridx = (u8)tx_pwr_idx;
- RT_TRACE(_module_mp_, _drv_notice_,
- ("oid_rt_pro_set_tx_power_control_hdl: idx=0x%2x\n",
- Adapter->mppriv.txpoweridx));
_irqlevel_changed_(&oldirql, LOWER);
SetTxPower(Adapter);
_irqlevel_changed_(&oldirql, RAISE);
- _func_exit_;
return status;
}
@@ -502,7 +433,6 @@ NDIS_STATUS oid_rt_pro_query_tx_packet_sent_hdl(struct oid_par_priv *poid_par_pr
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
- _func_enter_;
if (poid_par_priv->type_of_oid != QUERY_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
@@ -515,7 +445,6 @@ NDIS_STATUS oid_rt_pro_query_tx_packet_sent_hdl(struct oid_par_priv *poid_par_pr
} else
status = NDIS_STATUS_INVALID_LENGTH;
- _func_exit_;
return status;
}
@@ -525,21 +454,17 @@ NDIS_STATUS oid_rt_pro_query_rx_packet_received_hdl(struct oid_par_priv *poid_pa
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
- _func_enter_;
if (poid_par_priv->type_of_oid != QUERY_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
- RT_TRACE(_module_mp_, _drv_alert_, ("===> oid_rt_pro_query_rx_packet_received_hdl.\n"));
if (poid_par_priv->information_buf_len == sizeof(ULONG)) {
*(ULONG *)poid_par_priv->information_buf = Adapter->mppriv.rx_pktcount;
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
- RT_TRACE(_module_mp_, _drv_alert_, ("recv_ok:%d\n", Adapter->mppriv.rx_pktcount));
} else
status = NDIS_STATUS_INVALID_LENGTH;
- _func_exit_;
return status;
}
@@ -549,21 +474,17 @@ NDIS_STATUS oid_rt_pro_query_rx_packet_crc32_error_hdl(struct oid_par_priv *poid
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
- _func_enter_;
if (poid_par_priv->type_of_oid != QUERY_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
- RT_TRACE(_module_mp_, _drv_alert_, ("===> oid_rt_pro_query_rx_packet_crc32_error_hdl.\n"));
if (poid_par_priv->information_buf_len == sizeof(ULONG)) {
*(ULONG *)poid_par_priv->information_buf = Adapter->mppriv.rx_crcerrpktcount;
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
- RT_TRACE(_module_mp_, _drv_alert_, ("recv_err:%d\n", Adapter->mppriv.rx_crcerrpktcount));
} else
status = NDIS_STATUS_INVALID_LENGTH;
- _func_exit_;
return status;
}
@@ -574,17 +495,14 @@ NDIS_STATUS oid_rt_pro_reset_tx_packet_sent_hdl(struct oid_par_priv *poid_par_pr
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
- _func_enter_;
if (poid_par_priv->type_of_oid != SET_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
- RT_TRACE(_module_mp_, _drv_alert_, ("===> oid_rt_pro_reset_tx_packet_sent_hdl.\n"));
Adapter->mppriv.tx_pktcount = 0;
- _func_exit_;
return status;
}
@@ -594,7 +512,6 @@ NDIS_STATUS oid_rt_pro_reset_rx_packet_received_hdl(struct oid_par_priv *poid_pa
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
- _func_enter_;
if (poid_par_priv->type_of_oid != SET_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
@@ -607,7 +524,6 @@ NDIS_STATUS oid_rt_pro_reset_rx_packet_received_hdl(struct oid_par_priv *poid_pa
} else
status = NDIS_STATUS_INVALID_LENGTH;
- _func_exit_;
return status;
}
@@ -620,7 +536,6 @@ NDIS_STATUS oid_rt_reset_phy_rx_packet_count_hdl(struct oid_par_priv *poid_par_p
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
- _func_enter_;
if (poid_par_priv->type_of_oid != SET_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
@@ -631,7 +546,6 @@ NDIS_STATUS oid_rt_reset_phy_rx_packet_count_hdl(struct oid_par_priv *poid_par_p
ResetPhyRxPktCount(Adapter);
_irqlevel_changed_(&oldirql, RAISE);
- _func_exit_;
return status;
}
@@ -644,9 +558,7 @@ NDIS_STATUS oid_rt_get_phy_rx_packet_received_hdl(struct oid_par_priv *poid_par_
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
- _func_enter_;
- RT_TRACE(_module_mp_, _drv_info_, ("+oid_rt_get_phy_rx_packet_received_hdl\n"));
if (poid_par_priv->type_of_oid != QUERY_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -660,9 +572,7 @@ NDIS_STATUS oid_rt_get_phy_rx_packet_received_hdl(struct oid_par_priv *poid_par_
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
- RT_TRACE(_module_mp_, _drv_notice_, ("-oid_rt_get_phy_rx_packet_received_hdl: recv_ok=%d\n", *(ULONG *)poid_par_priv->information_buf));
- _func_exit_;
return status;
}
@@ -675,9 +585,7 @@ NDIS_STATUS oid_rt_get_phy_rx_packet_crc32_error_hdl(struct oid_par_priv *poid_p
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
- _func_enter_;
- RT_TRACE(_module_mp_, _drv_info_, ("+oid_rt_get_phy_rx_packet_crc32_error_hdl\n"));
if (poid_par_priv->type_of_oid != QUERY_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -692,9 +600,7 @@ NDIS_STATUS oid_rt_get_phy_rx_packet_crc32_error_hdl(struct oid_par_priv *poid_p
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
- RT_TRACE(_module_mp_, _drv_info_, ("-oid_rt_get_phy_rx_packet_crc32_error_hdl: recv_err=%d\n", *(ULONG *)poid_par_priv->information_buf));
- _func_exit_;
return status;
}
@@ -708,9 +614,7 @@ NDIS_STATUS oid_rt_pro_set_continuous_tx_hdl(struct oid_par_priv *poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
- _func_enter_;
- RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_set_continuous_tx_hdl\n"));
if (poid_par_priv->type_of_oid != SET_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -732,7 +636,6 @@ NDIS_STATUS oid_rt_pro_set_continuous_tx_hdl(struct oid_par_priv *poid_par_priv)
}
_irqlevel_changed_(&oldirql, RAISE);
- _func_exit_;
return status;
}
@@ -746,9 +649,7 @@ NDIS_STATUS oid_rt_pro_set_single_carrier_tx_hdl(struct oid_par_priv *poid_par_p
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
- _func_enter_;
- RT_TRACE(_module_mp_, _drv_alert_, ("+oid_rt_pro_set_single_carrier_tx_hdl\n"));
if (poid_par_priv->type_of_oid != SET_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -770,7 +671,6 @@ NDIS_STATUS oid_rt_pro_set_single_carrier_tx_hdl(struct oid_par_priv *poid_par_p
}
_irqlevel_changed_(&oldirql, RAISE);
- _func_exit_;
return status;
}
@@ -784,9 +684,7 @@ NDIS_STATUS oid_rt_pro_set_carrier_suppression_tx_hdl(struct oid_par_priv *poid_
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
- _func_enter_;
- RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_set_carrier_suppression_tx_hdl\n"));
if (poid_par_priv->type_of_oid != SET_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -808,7 +706,6 @@ NDIS_STATUS oid_rt_pro_set_carrier_suppression_tx_hdl(struct oid_par_priv *poid_
}
_irqlevel_changed_(&oldirql, RAISE);
- _func_exit_;
return status;
}
@@ -822,9 +719,7 @@ NDIS_STATUS oid_rt_pro_set_single_tone_tx_hdl(struct oid_par_priv *poid_par_priv
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
- _func_enter_;
- RT_TRACE(_module_mp_, _drv_alert_, ("+oid_rt_pro_set_single_tone_tx_hdl\n"));
if (poid_par_priv->type_of_oid != SET_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -835,7 +730,6 @@ NDIS_STATUS oid_rt_pro_set_single_tone_tx_hdl(struct oid_par_priv *poid_par_priv
SetSingleToneTx(Adapter, (u8)bStartTest);
_irqlevel_changed_(&oldirql, RAISE);
- _func_exit_;
return status;
}
@@ -853,7 +747,6 @@ NDIS_STATUS oid_rt_pro_trigger_gpio_hdl(struct oid_par_priv *poid_par_priv)
_irqL oldirql;
#endif
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
- _func_enter_;
if (poid_par_priv->type_of_oid != SET_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -862,7 +755,6 @@ NDIS_STATUS oid_rt_pro_trigger_gpio_hdl(struct oid_par_priv *poid_par_priv)
rtw_hal_set_hwreg(Adapter, HW_VAR_TRIGGER_GPIO_0, 0);
_irqlevel_changed_(&oldirql, RAISE);
- _func_exit_;
return status;
}
@@ -880,7 +772,6 @@ NDIS_STATUS oid_rt_pro8711_join_bss_hdl(struct oid_par_priv *poid_par_priv)
PNDIS_802_11_SSID pssid;
- _func_enter_;
if (poid_par_priv->type_of_oid != SET_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -901,7 +792,6 @@ NDIS_STATUS oid_rt_pro8711_join_bss_hdl(struct oid_par_priv *poid_par_priv)
*poid_par_priv->bytes_rw = sizeof(NDIS_802_11_SSID);
- _func_exit_;
return status;
#else
@@ -919,10 +809,7 @@ NDIS_STATUS oid_rt_pro_read_register_hdl(struct oid_par_priv *poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
- _func_enter_;
- RT_TRACE(_module_mp_, _drv_info_,
- ("+oid_rt_pro_read_register_hdl\n"));
if (poid_par_priv->type_of_oid != QUERY_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -948,15 +835,11 @@ NDIS_STATUS oid_rt_pro_read_register_hdl(struct oid_par_priv *poid_par_priv)
RegRWStruct->value = rtw_read32(Adapter, offset);
break;
}
- RT_TRACE(_module_mp_, _drv_notice_,
- ("oid_rt_pro_read_register_hdl: offset:0x%04X value:0x%X\n",
- offset, RegRWStruct->value));
_irqlevel_changed_(&oldirql, RAISE);
*poid_par_priv->bytes_rw = width;
- _func_exit_;
return status;
}
@@ -971,10 +854,7 @@ NDIS_STATUS oid_rt_pro_write_register_hdl(struct oid_par_priv *poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
- _func_enter_;
- RT_TRACE(_module_mp_, _drv_info_,
- ("+oid_rt_pro_write_register_hdl\n"));
if (poid_par_priv->type_of_oid != SET_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -1014,11 +894,7 @@ NDIS_STATUS oid_rt_pro_write_register_hdl(struct oid_par_priv *poid_par_priv)
_irqlevel_changed_(&oldirql, RAISE);
- RT_TRACE(_module_mp_, _drv_info_,
- ("-oid_rt_pro_write_register_hdl: offset=0x%08X width=%d value=0x%X\n",
- offset, width, value));
- _func_exit_;
return status;
}
@@ -1033,9 +909,7 @@ NDIS_STATUS oid_rt_pro_burst_read_register_hdl(struct oid_par_priv *poid_par_pri
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
- _func_enter_;
- RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_burst_read_register_hdl\n"));
if (poid_par_priv->type_of_oid != QUERY_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -1048,9 +922,7 @@ NDIS_STATUS oid_rt_pro_burst_read_register_hdl(struct oid_par_priv *poid_par_pri
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
- RT_TRACE(_module_mp_, _drv_info_, ("-oid_rt_pro_burst_read_register_hdl\n"));
- _func_exit_;
return status;
#else
@@ -1068,9 +940,7 @@ NDIS_STATUS oid_rt_pro_burst_write_register_hdl(struct oid_par_priv *poid_par_pr
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
- _func_enter_;
- RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_burst_write_register_hdl\n"));
if (poid_par_priv->type_of_oid != SET_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -1081,9 +951,7 @@ NDIS_STATUS oid_rt_pro_burst_write_register_hdl(struct oid_par_priv *poid_par_pr
rtw_write_mem(padapter, pBstRwReg->offset, (u32)pBstRwReg->len, pBstRwReg->Data);
_irqlevel_changed_(&oldirql, RAISE);
- RT_TRACE(_module_mp_, _drv_info_, ("-oid_rt_pro_burst_write_register_hdl\n"));
- _func_exit_;
return status;
#else
@@ -1104,20 +972,13 @@ NDIS_STATUS oid_rt_pro_write_txcmd_hdl(struct oid_par_priv *poid_par_priv)
TX_CMD_Desc *TxCmd_Info;
- _func_enter_;
if (poid_par_priv->type_of_oid != SET_OID)
return NDIS_STATUS_NOT_ACCEPTED;
- RT_TRACE(_module_mp_, _drv_info_, ("+Set OID_RT_PRO_WRITE_TXCMD\n"));
TxCmd_Info = (TX_CMD_Desc *)poid_par_priv->information_buf;
- RT_TRACE(_module_mp_, _drv_info_, ("WRITE_TXCMD:Addr=%.8X\n", TxCmd_Info->offset));
- RT_TRACE(_module_mp_, _drv_info_, ("WRITE_TXCMD:1.)%.8X\n", (ULONG)TxCmd_Info->TxCMD.value[0]));
- RT_TRACE(_module_mp_, _drv_info_, ("WRITE_TXCMD:2.)%.8X\n", (ULONG)TxCmd_Info->TxCMD.value[1]));
- RT_TRACE(_module_mp_, _drv_info_, (("WRITE_TXCMD:3.)%.8X\n", (ULONG)TxCmd_Info->TxCMD.value[2]));
- RT_TRACE(_module_mp_, _drv_info_, ("WRITE_TXCMD:4.)%.8X\n", (ULONG)TxCmd_Info->TxCMD.value[3]));
_irqlevel_changed_(&oldirql, LOWER);
@@ -1126,10 +987,7 @@ NDIS_STATUS oid_rt_pro_write_txcmd_hdl(struct oid_par_priv *poid_par_priv)
_irqlevel_changed_(&oldirql, RAISE);
- RT_TRACE(_module_mp_, _drv_notice_,
- ("-Set OID_RT_PRO_WRITE_TXCMD: status=0x%08X\n", status));
- _func_exit_;
return status;
#else
@@ -1148,9 +1006,7 @@ NDIS_STATUS oid_rt_pro_read16_eeprom_hdl(struct oid_par_priv *poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
- _func_enter_;
- RT_TRACE(_module_mp_, _drv_info_, ("+Query OID_RT_PRO_READ16_EEPROM\n"));
if (poid_par_priv->type_of_oid != QUERY_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -1163,11 +1019,7 @@ NDIS_STATUS oid_rt_pro_read16_eeprom_hdl(struct oid_par_priv *poid_par_priv)
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
- RT_TRACE(_module_mp_, _drv_notice_,
- ("-Query OID_RT_PRO_READ16_EEPROM: offset=0x%x value=0x%x\n",
- pEEPROM->offset, pEEPROM->value));
- _func_exit_;
return status;
#else
@@ -1186,9 +1038,7 @@ NDIS_STATUS oid_rt_pro_write16_eeprom_hdl(struct oid_par_priv *poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
- _func_enter_;
- RT_TRACE(_module_mp_, _drv_notice_, ("+Set OID_RT_PRO_WRITE16_EEPROM\n"));
if (poid_par_priv->type_of_oid != SET_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -1201,7 +1051,6 @@ NDIS_STATUS oid_rt_pro_write16_eeprom_hdl(struct oid_par_priv *poid_par_priv)
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
- _func_exit_;
return status;
#else
@@ -1218,7 +1067,6 @@ NDIS_STATUS oid_rt_pro8711_wi_poll_hdl(struct oid_par_priv *poid_par_priv)
struct mp_wiparam *pwi_param;
- _func_enter_;
if (poid_par_priv->type_of_oid != QUERY_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -1233,10 +1081,8 @@ NDIS_STATUS oid_rt_pro8711_wi_poll_hdl(struct oid_par_priv *poid_par_priv)
_rtw_memcpy(pwi_param, &Adapter->mppriv.workparam, sizeof(struct mp_wiparam));
Adapter->mppriv.act_in_progress = _FALSE;
- /* RT_TRACE(_module_mp_, _drv_info_, ("rf:%x\n", pwiparam->IoValue)); */
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
- _func_exit_;
return status;
#else
@@ -1251,15 +1097,12 @@ NDIS_STATUS oid_rt_pro8711_pkt_loss_hdl(struct oid_par_priv *poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
- _func_enter_;
- RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro8711_pkt_loss_hdl\n"));
if (poid_par_priv->type_of_oid != QUERY_OID)
return NDIS_STATUS_NOT_ACCEPTED;
if (poid_par_priv->information_buf_len < sizeof(uint) * 2) {
- RT_TRACE(_module_mp_, _drv_err_, ("-oid_rt_pro8711_pkt_loss_hdl: buf_len=%d\n", (int)poid_par_priv->information_buf_len));
return NDIS_STATUS_INVALID_LENGTH;
}
@@ -1269,7 +1112,6 @@ NDIS_STATUS oid_rt_pro8711_pkt_loss_hdl(struct oid_par_priv *poid_par_priv)
*((uint *)poid_par_priv->information_buf + 1) = Adapter->mppriv.rx_pktloss;
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
- _func_exit_;
return status;
#else
@@ -1293,9 +1135,7 @@ NDIS_STATUS oid_rt_rd_attrib_mem_hdl(struct oid_par_priv *poid_par_priv)
void (*_attrib_read)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
#endif
- _func_enter_;
- RT_TRACE(_module_mp_, _drv_notice_, ("+Query OID_RT_RD_ATTRIB_MEM\n"));
if (poid_par_priv->type_of_oid != QUERY_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -1312,7 +1152,6 @@ NDIS_STATUS oid_rt_rd_attrib_mem_hdl(struct oid_par_priv *poid_par_priv)
_irqlevel_changed_(&oldirql, RAISE);
#endif
- _func_exit_;
return status;
#else
@@ -1336,7 +1175,6 @@ NDIS_STATUS oid_rt_wr_attrib_mem_hdl(struct oid_par_priv *poid_par_priv)
void (*_attrib_write)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
#endif
- _func_enter_;
if (poid_par_priv->type_of_oid != SET_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -1352,7 +1190,6 @@ NDIS_STATUS oid_rt_wr_attrib_mem_hdl(struct oid_par_priv *poid_par_priv)
_irqlevel_changed_(&oldirql, RAISE);
#endif
- _func_exit_;
return status;
#else
@@ -1370,9 +1207,7 @@ NDIS_STATUS oid_rt_pro_set_rf_intfs_hdl(struct oid_par_priv *poid_par_priv)
#endif
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
- _func_enter_;
- RT_TRACE(_module_mp_, _drv_notice_, ("+OID_RT_PRO_SET_RF_INTFS\n"));
if (poid_par_priv->type_of_oid != SET_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -1384,7 +1219,6 @@ NDIS_STATUS oid_rt_pro_set_rf_intfs_hdl(struct oid_par_priv *poid_par_priv)
_irqlevel_changed_(&oldirql, RAISE);
- _func_exit_;
return status;
#else
@@ -1399,7 +1233,6 @@ NDIS_STATUS oid_rt_poll_rx_status_hdl(struct oid_par_priv *poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
- _func_enter_;
if (poid_par_priv->type_of_oid != QUERY_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -1407,7 +1240,6 @@ NDIS_STATUS oid_rt_poll_rx_status_hdl(struct oid_par_priv *poid_par_priv)
_rtw_memcpy(poid_par_priv->information_buf, (unsigned char *)&Adapter->mppriv.rxstat, sizeof(struct recv_stat));
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
- _func_exit_;
return status;
#else
@@ -1424,38 +1256,26 @@ NDIS_STATUS oid_rt_pro_cfg_debug_message_hdl(struct oid_par_priv *poid_par_priv)
PCFG_DBG_MSG_STRUCT pdbg_msg;
- _func_enter_;
- /* RT_TRACE(0xffffffffff,_drv_alert_,("===> oid_rt_pro_cfg_debug_message_hdl.\n")); */
#if 0/*#ifdef CONFIG_DEBUG_RTL871X*/
pdbg_msg = (PCFG_DBG_MSG_STRUCT)(poid_par_priv->information_buf);
if (poid_par_priv->type_of_oid == SET_OID) {
- RT_TRACE(0xffffffffff, _drv_alert_,
- ("===>Set level :0x%08x, H32:0x%08x L32:0x%08x\n",
- pdbg_msg->DebugLevel, pdbg_msg->DebugComponent_H32, pdbg_msg->DebugComponent_L32));
GlobalDebugLevel = pdbg_msg->DebugLevel;
GlobalDebugComponents = (pdbg_msg->DebugComponent_H32 << 32) | pdbg_msg->DebugComponent_L32;
- RT_TRACE(0xffffffffff, _drv_alert_,
- ("===> Set level :0x%08x, component:0x%016x\n",
- GlobalDebugLevel, (u32)GlobalDebugComponents));
} else {
pdbg_msg->DebugLevel = GlobalDebugLevel;
pdbg_msg->DebugComponent_H32 = (u32)(GlobalDebugComponents >> 32);
pdbg_msg->DebugComponent_L32 = (u32)GlobalDebugComponents;
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
- RT_TRACE(0xffffffffff, _drv_alert_,
- ("===>Query level:0x%08x H32:0x%08x L32:0x%08x\n",
- (u32)pdbg_msg->DebugLevel, (u32)pdbg_msg->DebugComponent_H32, (u32)pdbg_msg->DebugComponent_L32));
}
#endif
- _func_exit_;
return status;
#else
@@ -1472,9 +1292,7 @@ NDIS_STATUS oid_rt_pro_set_data_rate_ex_hdl(struct oid_par_priv *poid_par_priv)
#endif
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
- _func_enter_;
- RT_TRACE(_module_mp_, _drv_notice_, ("+OID_RT_PRO_SET_DATA_RATE_EX\n"));
if (poid_par_priv->type_of_oid != SET_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -1486,7 +1304,6 @@ NDIS_STATUS oid_rt_pro_set_data_rate_ex_hdl(struct oid_par_priv *poid_par_priv)
_irqlevel_changed_(&oldirql, RAISE);
- _func_exit_;
return status;
}
@@ -1500,9 +1317,7 @@ NDIS_STATUS oid_rt_get_thermal_meter_hdl(struct oid_par_priv *poid_par_priv)
u8 thermal = 0;
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
- _func_enter_;
- RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_get_thermal_meter_hdl\n"));
if (poid_par_priv->type_of_oid != QUERY_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -1517,7 +1332,6 @@ NDIS_STATUS oid_rt_get_thermal_meter_hdl(struct oid_par_priv *poid_par_priv)
*(u32 *)poid_par_priv->information_buf = (u32)thermal;
*poid_par_priv->bytes_rw = sizeof(u32);
- _func_exit_;
return status;
}
@@ -1532,9 +1346,7 @@ NDIS_STATUS oid_rt_pro_read_tssi_hdl(struct oid_par_priv *poid_par_priv)
#endif
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
- _func_enter_;
- RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_read_tssi_hdl\n"));
if (poid_par_priv->type_of_oid != SET_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -1559,7 +1371,6 @@ NDIS_STATUS oid_rt_pro_read_tssi_hdl(struct oid_par_priv *poid_par_priv)
_irqlevel_changed_(&oldirql, RAISE);
- _func_exit_;
return status;
#else
@@ -1576,7 +1387,6 @@ NDIS_STATUS oid_rt_pro_set_power_tracking_hdl(struct oid_par_priv *poid_par_priv
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
- _func_enter_;
/* if (poid_par_priv->type_of_oid != SET_OID)
* return NDIS_STATUS_NOT_ACCEPTED; */
@@ -1589,15 +1399,12 @@ NDIS_STATUS oid_rt_pro_set_power_tracking_hdl(struct oid_par_priv *poid_par_priv
u8 enable;
enable = *(u8 *)poid_par_priv->information_buf;
- RT_TRACE(_module_mp_, _drv_notice_,
- ("+oid_rt_pro_set_power_tracking_hdl: enable=%d\n", enable));
SetPowerTracking(Adapter, enable);
} else
GetPowerTracking(Adapter, (u8 *)poid_par_priv->information_buf);
_irqlevel_changed_(&oldirql, RAISE);
- _func_exit_;
return status;
}
@@ -1614,9 +1421,7 @@ NDIS_STATUS oid_rt_pro_set_basic_rate_hdl(struct oid_par_priv *poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context);
- _func_enter_;
- RT_TRACE(_module_mp_, _drv_info_, ("+OID_RT_PRO_SET_BASIC_RATE\n"));
if (poid_par_priv->type_of_oid != SET_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -1628,7 +1433,6 @@ NDIS_STATUS oid_rt_pro_set_basic_rate_hdl(struct oid_par_priv *poid_par_priv)
datarates[i] = mpdatarate[i];
else
datarates[i] = 0xff;
- RT_TRACE(_module_rtl871x_ioctl_c_, _drv_info_, ("basicrate_inx=%d\n", datarates[i]));
}
_irqlevel_changed_(&oldirql, LOWER);
@@ -1638,10 +1442,7 @@ NDIS_STATUS oid_rt_pro_set_basic_rate_hdl(struct oid_par_priv *poid_par_priv)
_irqlevel_changed_(&oldirql, RAISE);
#endif
- RT_TRACE(_module_mp_, _drv_notice_,
- ("-OID_RT_PRO_SET_BASIC_RATE: status=0x%08X\n", status));
- _func_exit_;
return status;
#else
@@ -1656,7 +1457,6 @@ NDIS_STATUS oid_rt_pro_qry_pwrstate_hdl(struct oid_par_priv *poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
- _func_enter_;
if (poid_par_priv->type_of_oid != QUERY_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -1668,11 +1468,7 @@ NDIS_STATUS oid_rt_pro_qry_pwrstate_hdl(struct oid_par_priv *poid_par_priv)
_rtw_memcpy(poid_par_priv->information_buf, &(adapter_to_pwrctl(Adapter)->pwr_mode), 8);
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
- RT_TRACE(_module_mp_, _drv_notice_,
- ("-oid_rt_pro_qry_pwrstate_hdl: pwr_mode=%d smart_ps=%d\n",
- adapter_to_pwrctl(Adapter)->pwr_mode, adapter_to_pwrctl(Adapter)->smart_ps));
- _func_exit_;
return status;
#else
@@ -1689,9 +1485,7 @@ NDIS_STATUS oid_rt_pro_set_pwrstate_hdl(struct oid_par_priv *poid_par_priv)
uint pwr_mode, smart_ps;
- _func_enter_;
- RT_TRACE(_module_mp_, _drv_notice_, ("+Set OID_RT_PRO_SET_PWRSTATE\n"));
if (poid_par_priv->type_of_oid != SET_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -1707,7 +1501,6 @@ NDIS_STATUS oid_rt_pro_set_pwrstate_hdl(struct oid_par_priv *poid_par_priv)
*poid_par_priv->bytes_rw = 8;
- _func_exit_;
return status;
#else
@@ -1728,7 +1521,6 @@ NDIS_STATUS oid_rt_pro_h2c_set_rate_table_hdl(struct oid_par_priv *poid_par_priv
struct setratable_parm *prate_table;
u8 res;
- _func_enter_;
if (poid_par_priv->type_of_oid != SET_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -1746,7 +1538,6 @@ NDIS_STATUS oid_rt_pro_h2c_set_rate_table_hdl(struct oid_par_priv *poid_par_priv
if (res == _FAIL)
status = NDIS_STATUS_FAILURE;
- _func_exit_;
return status;
#else
@@ -1761,7 +1552,6 @@ NDIS_STATUS oid_rt_pro_h2c_get_rate_table_hdl(struct oid_par_priv *poid_par_priv
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
- _func_enter_;
if (poid_par_priv->type_of_oid != QUERY_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -1791,7 +1581,6 @@ NDIS_STATUS oid_rt_pro_h2c_get_rate_table_hdl(struct oid_par_priv *poid_par_priv
DEBUG_INFO(("\n <=== Set OID_RT_PRO_H2C_GET_RATE_TABLE.\n"));
#endif
- _func_exit_;
return status;
#else
@@ -1856,9 +1645,6 @@ NDIS_STATUS oid_rt_pro_encryption_ctrl_hdl(struct oid_par_priv *poid_par_priv)
break;
}
- RT_TRACE(_module_rtl871x_ioctl_c_, _drv_notice_,
- ("-oid_rt_pro_encryption_ctrl_hdl: SET encry_mode=0x%x sw_encrypt=0x%x sw_decrypt=0x%x\n",
- encry_mode, psecuritypriv->sw_encrypt, psecuritypriv->sw_decrypt));
} else {
#if 0
if (Adapter->registrypriv.software_encrypt == _FALSE) {
@@ -1888,9 +1674,6 @@ NDIS_STATUS oid_rt_pro_encryption_ctrl_hdl(struct oid_par_priv *poid_par_priv)
*(u8 *)poid_par_priv->information_buf = encry_mode;
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
- RT_TRACE(_module_mp_, _drv_notice_,
- ("-oid_rt_pro_encryption_ctrl_hdl: QUERY encry_mode=0x%x\n",
- encry_mode));
}
return status;
@@ -1922,8 +1705,6 @@ NDIS_STATUS oid_rt_pro_add_sta_info_hdl(struct oid_par_priv *poid_par_priv)
macaddr = (UCHAR *) poid_par_priv->information_buf ;
- RT_TRACE(_module_rtl871x_ioctl_c_, _drv_notice_,
- ("OID_RT_PRO_ADD_STA_INFO: addr="MAC_FMT"\n", MAC_ARG(macaddr)));
_irqlevel_changed_(&oldirql, LOWER);
@@ -1933,12 +1714,8 @@ NDIS_STATUS oid_rt_pro_add_sta_info_hdl(struct oid_par_priv *poid_par_priv)
psta = rtw_alloc_stainfo(&Adapter->stapriv, macaddr);
if (psta == NULL) {
- RT_TRACE(_module_rtl871x_ioctl_c_, _drv_err_, ("Can't alloc sta_info when OID_RT_PRO_ADD_STA_INFO\n"));
status = NDIS_STATUS_FAILURE;
}
- } else { /* (between drv has received this event before and fw have not yet to set key to CAM_ENTRY) */
- RT_TRACE(_module_rtl871x_ioctl_c_, _drv_err_,
- ("Error: OID_RT_PRO_ADD_STA_INFO: sta has been in sta_hash_queue\n"));
}
_irqlevel_changed_(&oldirql, RAISE);
@@ -1971,8 +1748,6 @@ NDIS_STATUS oid_rt_pro_dele_sta_info_hdl(struct oid_par_priv *poid_par_priv)
return NDIS_STATUS_INVALID_LENGTH;
macaddr = (UCHAR *) poid_par_priv->information_buf ;
- RT_TRACE(_module_rtl871x_ioctl_c_, _drv_notice_,
- ("+OID_RT_PRO_ADD_STA_INFO: addr="MAC_FMT"\n", MAC_ARG(macaddr)));
psta = rtw_get_stainfo(&Adapter->stapriv, macaddr);
if (psta != NULL) {
@@ -1995,9 +1770,7 @@ static u32 mp_query_drv_var(_adapter *padapter, u8 offset, u32 var)
if (offset == 1) {
u16 tmp_blk_num;
tmp_blk_num = rtw_read16(padapter, SDIO_RX0_RDYBLK_NUM);
- RT_TRACE(_module_mp_, _drv_err_, ("Query Information, mp_query_drv_var SDIO_RX0_RDYBLK_NUM=0x%x dvobj.rxblknum=0x%x\n", tmp_blk_num, adapter_to_dvobj(padapter)->rxblknum));
if (adapter_to_dvobj(padapter)->rxblknum != tmp_blk_num) {
- RT_TRACE(_module_mp_, _drv_err_, ("Query Information, mp_query_drv_var call recv rx\n"));
/* sd_recv_rxfifo(padapter); */
}
}
@@ -2005,72 +1778,43 @@ static u32 mp_query_drv_var(_adapter *padapter, u8 offset, u32 var)
#if 0
if (offset <= 100) { /* For setting data rate and query data rate */
if (offset == 100) { /* For query data rate */
- RT_TRACE(_module_mp_, _drv_emerg_, ("\n mp_query_drv_var: offset(%d): query rate=0x%.2x\n", offset, padapter->registrypriv.tx_rate));
var = padapter->registrypriv.tx_rate;
} else if (offset < 0x1d) { /* For setting data rate */
padapter->registrypriv.tx_rate = offset;
var = padapter->registrypriv.tx_rate;
padapter->registrypriv.use_rate = _TRUE;
- RT_TRACE(_module_mp_, _drv_emerg_, ("\n mp_query_drv_var: offset(%d): set rate=0x%.2x\n", offset, padapter->registrypriv.tx_rate));
} else { /* not use the data rate */
padapter->registrypriv.use_rate = _FALSE;
- RT_TRACE(_module_mp_, _drv_emerg_, ("\n mp_query_drv_var: offset(%d) out of rate range\n", offset));
}
} else if (offset <= 110) { /* for setting debug level */
- RT_TRACE(_module_mp_, _drv_emerg_, (" mp_query_drv_var: offset(%d) for set debug level\n", offset));
if (offset == 110) { /* For query data rate */
- RT_TRACE(_module_mp_, _drv_emerg_, (" mp_query_drv_var: offset(%d): query dbg level=0x%.2x\n", offset, padapter->registrypriv.dbg_level));
padapter->registrypriv.dbg_level = GlobalDebugLevel;
var = padapter->registrypriv.dbg_level;
} else if (offset < 110 && offset > 100) {
- RT_TRACE(_module_mp_, _drv_emerg_, (" mp_query_drv_var: offset(%d): set dbg level=0x%.2x\n", offset, offset - 100));
padapter->registrypriv.dbg_level = GlobalDebugLevel = offset - 100;
var = padapter->registrypriv.dbg_level;
- RT_TRACE(_module_mp_, _drv_emerg_, (" mp_query_drv_var(_drv_emerg_): offset(%d): set dbg level=0x%.2x\n", offset, GlobalDebugLevel));
- RT_TRACE(_module_mp_, _drv_alert_, (" mp_query_drv_var(_drv_alert_): offset(%d): set dbg level=0x%.2x\n", offset, GlobalDebugLevel));
- RT_TRACE(_module_mp_, _drv_crit_, (" mp_query_drv_var(_drv_crit_): offset(%d): set dbg level=0x%.2x\n", offset, GlobalDebugLevel));
- RT_TRACE(_module_mp_, _drv_err_, (" mp_query_drv_var(_drv_err_): offset(%d): set dbg level=0x%.2x\n", offset, GlobalDebugLevel));
- RT_TRACE(_module_mp_, _drv_warning_, (" mp_query_drv_var(_drv_warning_): offset(%d): set dbg level=0x%.2x\n", offset, GlobalDebugLevel));
- RT_TRACE(_module_mp_, _drv_notice_, (" mp_query_drv_var(_drv_notice_): offset(%d): set dbg level=0x%.2x\n", offset, GlobalDebugLevel));
- RT_TRACE(_module_mp_, _drv_info_, (" mp_query_drv_var(_drv_info_): offset(%d): set dbg level=0x%.2x\n", offset, GlobalDebugLevel));
- RT_TRACE(_module_mp_, _drv_debug_, (" mp_query_drv_var(_drv_debug_): offset(%d): set dbg level=0x%.2x\n", offset, GlobalDebugLevel));
}
} else if (offset > 110 && offset < 116) {
if (115 == offset) {
- RT_TRACE(_module_mp_, _drv_emerg_, (" mp_query_drv_var(_drv_emerg_): offset(%d): query TRX access type: [tx_block_mode=%x,rx_block_mode=%x]\n", \
- offset, adapter_to_dvobj(padapter)->tx_block_mode, adapter_to_dvobj(
- padapter)->rx_block_mode));
} else {
switch (offset) {
case 111:
adapter_to_dvobj(padapter)->tx_block_mode = 1;
adapter_to_dvobj(padapter)->rx_block_mode = 1;
- RT_TRACE(_module_mp_, _drv_emerg_, \
- (" mp_query_drv_var(_drv_emerg_): offset(%d): SET TRX access type:(TX block/RX block) [tx_block_mode=%x,rx_block_mode=%x]\n", \
- offset, adapter_to_dvobj(padapter)->tx_block_mode, adapter_to_dvobj(padapter)->rx_block_mode));
break;
case 112:
adapter_to_dvobj(padapter)->tx_block_mode = 1;
adapter_to_dvobj(padapter)->rx_block_mode = 0;
- RT_TRACE(_module_mp_, _drv_emerg_, \
- (" mp_query_drv_var(_drv_emerg_): offset(%d): SET TRX access type:(TX block/RX byte) [tx_block_mode=%x,rx_block_mode=%x]\n", \
- offset, adapter_to_dvobj(padapter)->tx_block_mode, adapter_to_dvobj(padapter)->rx_block_mode));
break;
case 113:
adapter_to_dvobj(padapter)->tx_block_mode = 0;
adapter_to_dvobj(padapter)->rx_block_mode = 1;
- RT_TRACE(_module_mp_, _drv_emerg_, \
- (" mp_query_drv_var(_drv_emerg_): offset(%d): SET TRX access type:(TX byte/RX block) [tx_block_mode=%x,rx_block_mode=%x]\n", \
- offset, adapter_to_dvobj(padapter)->tx_block_mode, adapter_to_dvobj(padapter)->rx_block_mode));
break;
case 114:
adapter_to_dvobj(padapter)->tx_block_mode = 0;
adapter_to_dvobj(padapter)->rx_block_mode = 0;
- RT_TRACE(_module_mp_, _drv_emerg_, \
- (" mp_query_drv_var(_drv_emerg_): offset(%d): SET TRX access type:(TX byte/RX byte) [tx_block_mode=%x,rx_block_mode=%x]\n", \
- offset, adapter_to_dvobj(padapter)->tx_block_mode, adapter_to_dvobj(padapter)->rx_block_mode));
break;
default:
break;
@@ -2086,31 +1830,15 @@ static u32 mp_query_drv_var(_adapter *padapter, u8 offset, u32 var)
chg_idx = offset - 0x80;
tmp_dbg_comp = BIT(chg_idx);
prnt_dbg_comp = padapter->registrypriv.dbg_component = GlobalDebugComponents;
- RT_TRACE(_module_mp_, _drv_emerg_,
- (" 1: mp_query_drv_var: offset(%d;0x%x):for dbg conpoment prnt_dbg_comp=0x%.16x GlobalDebugComponents=0x%.16x padapter->registrypriv.dbg_component=0x%.16x\n", offset, offset,
- prnt_dbg_comp, GlobalDebugComponents, padapter->registrypriv.dbg_component));
if (offset == 127) {
/* prnt_dbg_comp=padapter->registrypriv.dbg_component= GlobalDebugComponents; */
var = (u32)(padapter->registrypriv.dbg_component);
- RT_TRACE(0xffffffff, _drv_emerg_, ("2: mp_query_drv_var: offset(%d;0x%x):for query dbg conpoment=0x%x(l) 0x%x(h) GlobalDebugComponents=0x%x(l) 0x%x(h)\n", offset, offset,
- padapter->registrypriv.dbg_component, prnt_dbg_comp));
prnt_dbg_comp = GlobalDebugComponents;
- RT_TRACE(0xffffffff, _drv_emerg_, ("2-1: mp_query_drv_var: offset(%d;0x%x):for query dbg conpoment=0x%x(l) 0x%x(h) GlobalDebugComponents=0x%x(l) 0x%x(h)\n", offset, offset,
- padapter->registrypriv.dbg_component, prnt_dbg_comp));
prnt_dbg_comp = GlobalDebugComponents = padapter->registrypriv.dbg_component;
- RT_TRACE(0xffffffff, _drv_emerg_, ("2-2: mp_query_drv_var: offset(%d;0x%x):for query dbg conpoment=0x%x(l) 0x%x(h) GlobalDebugComponents=0x%x(l) 0x%x(h)\n", offset, offset,
- padapter->registrypriv.dbg_component, prnt_dbg_comp));
} else {
- RT_TRACE(0xffffffff, _drv_emerg_, ("3: mp_query_drv_var: offset(%d;0x%x):for query dbg conpoment=0x%x(l) 0x%x(h) GlobalDebugComponents=0x%x(l) 0x%x(h) chg_idx=%d\n", offset,
- offset, padapter->registrypriv.dbg_component, prnt_dbg_comp, chg_idx));
prnt_dbg_comp = GlobalDebugComponents;
- RT_TRACE(0xffffffff, _drv_emerg_, ("3-1: mp_query_drv_var: offset(%d;0x%x):for query dbg conpoment=0x%x(l) 0x%x(h) GlobalDebugComponents=0x%x(l) 0x%x(h) chg_idx=%d\n", offset,
- offset, padapter->registrypriv.dbg_component, prnt_dbg_comp,
- chg_idx)); /* ("3-1: mp_query_drv_var: offset(%d;0x%x):before set dbg conpoment=0x%x chg_idx=%d or0x%x BIT(chg_idx[%d]=0x%x)\n",offset,offset,prnt_dbg_comp,chg_idx,chg_idx,(chg_idx),tmp_dbg_comp) */
prnt_dbg_comp = GlobalDebugComponents = padapter->registrypriv.dbg_component;
- RT_TRACE(0xffffffff, _drv_emerg_, ("3-2: mp_query_drv_var: offset(%d;0x%x):for query dbg conpoment=0x%x(l) 0x%x(h) GlobalDebugComponents=0x%x(l) 0x%x(h)\n", offset, offset,
- padapter->registrypriv.dbg_component, prnt_dbg_comp));
if (GlobalDebugComponents & tmp_dbg_comp) {
/* this bit is already set, now clear it */
@@ -2119,68 +1847,13 @@ static u32 mp_query_drv_var(_adapter *padapter, u8 offset, u32 var)
/* this bit is not set, now set it. */
GlobalDebugComponents = GlobalDebugComponents | tmp_dbg_comp;
}
- RT_TRACE(0xffffffff, _drv_emerg_, ("4: mp_query_drv_var: offset(%d;0x%x):before set dbg conpoment tmp_dbg_comp=0x%x GlobalDebugComponents=0x%x(l) 0x%x(h)", offset, offset,
- tmp_dbg_comp, prnt_dbg_comp));
prnt_dbg_comp = GlobalDebugComponents;
- RT_TRACE(0xffffffff, _drv_emerg_, ("4-1: mp_query_drv_var: offset(%d;0x%x):before set dbg conpoment tmp_dbg_comp=0x%x GlobalDebugComponents=0x%x(l) 0x%x(h)", offset, offset,
- tmp_dbg_comp, prnt_dbg_comp));
-
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_emerg_, ("0: mp_query_drv_var(_module_rtl871x_xmit_c_:0): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, offset,
- prnt_dbg_comp));
- RT_TRACE(_module_xmit_osdep_c_, _drv_emerg_, ("1: mp_query_drv_var(_module_xmit_osdep_c_:1): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, offset,
- GlobalDebugComponents));
- RT_TRACE(_module_rtl871x_recv_c_, _drv_emerg_, ("2: mp_query_drv_var(_module_rtl871x_recv_c_:2): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, offset,
- GlobalDebugComponents));
- RT_TRACE(_module_recv_osdep_c_, _drv_emerg_, ("3: mp_query_drv_var(_module_recv_osdep_c_:3): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, offset,
- GlobalDebugComponents));
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_emerg_, ("4: mp_query_drv_var(_module_rtl871x_mlme_c_:4): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, offset,
- GlobalDebugComponents));
- RT_TRACE(_module_mlme_osdep_c_, _drv_emerg_, (" 5:mp_query_drv_var(_module_mlme_osdep_c_:5): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, offset,
- GlobalDebugComponents));
- RT_TRACE(_module_rtl871x_sta_mgt_c_, _drv_emerg_, ("6: mp_query_drv_var(_module_rtl871x_sta_mgt_c_:6): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset,
- offset, GlobalDebugComponents));
- RT_TRACE(_module_rtl871x_cmd_c_, _drv_emerg_, ("7: mp_query_drv_var(_module_rtl871x_cmd_c_:7): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, offset,
- GlobalDebugComponents));
- RT_TRACE(_module_cmd_osdep_c_, _drv_emerg_, ("8: mp_query_drv_var(_module_cmd_osdep_c_:8): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, offset,
- GlobalDebugComponents));
- RT_TRACE(_module_rtl871x_io_c_, _drv_emerg_, ("9: mp_query_drv_var(_module_rtl871x_io_c_:9): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, offset,
- GlobalDebugComponents));
- RT_TRACE(_module_io_osdep_c_, _drv_emerg_, ("10: mp_query_drv_var(_module_io_osdep_c_:10): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, offset,
- GlobalDebugComponents));
- RT_TRACE(_module_os_intfs_c_, _drv_emerg_, ("11: mp_query_drv_var(_module_os_intfs_c_:11): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, offset,
- GlobalDebugComponents));
- RT_TRACE(_module_rtl871x_security_c_, _drv_emerg_, ("12: mp_query_drv_var(_module_rtl871x_security_c_:12): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset,
- offset, GlobalDebugComponents));
- RT_TRACE(_module_rtl871x_eeprom_c_, _drv_emerg_, ("13: mp_query_drv_var(_module_rtl871x_eeprom_c_:13): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset,
- offset, GlobalDebugComponents));
- RT_TRACE(_module_hal_init_c_, _drv_emerg_, ("14: mp_query_drv_var(_module_hal_init_c_:14): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, offset,
- GlobalDebugComponents));
- RT_TRACE(_module_hci_hal_init_c_, _drv_emerg_, ("15: mp_query_drv_var(_module_hci_hal_init_c_:15): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, offset,
- GlobalDebugComponents));
- RT_TRACE(_module_rtl871x_ioctl_c_, _drv_emerg_, ("16: mp_query_drv_var(_module_rtl871x_ioctl_c_:16): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset,
- offset, GlobalDebugComponents));
- RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_emerg_, ("17: mp_query_drv_var(_module_rtl871x_ioctl_set_c_:17): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",
- offset, offset, GlobalDebugComponents));
- RT_TRACE(_module_rtl871x_ioctl_query_c_, _drv_emerg_, ("18: mp_query_drv_var(_module_rtl871x_ioctl_query_c_:18): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",
- offset, offset, GlobalDebugComponents));
- RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_emerg_, ("19: mp_query_drv_var(_module_rtl871x_pwrctrl_c_:19): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset,
- offset, GlobalDebugComponents));
- RT_TRACE(_module_hci_intfs_c_, _drv_emerg_, ("20: mp_query_drv_var(_module_hci_intfs_c_:20): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, offset,
- GlobalDebugComponents));
- RT_TRACE(_module_hci_ops_c_, _drv_emerg_, ("21: mp_query_drv_var(_module_hci_ops_c_:21): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, offset,
- GlobalDebugComponents));
- RT_TRACE(_module_osdep_service_c_, _drv_emerg_, ("22: mp_query_drv_var(_module_osdep_service_c_:22): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset,
- offset, GlobalDebugComponents));
- RT_TRACE(_module_mp_, _drv_emerg_, ("23: mp_query_drv_var(_module_mp_:23): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, offset, GlobalDebugComponents));
- RT_TRACE(_module_hci_ops_os_c_, _drv_emerg_, ("24: mp_query_drv_var(_module_hci_ops_os_c_:24): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, offset,
- GlobalDebugComponents));
+
var = (u32)(GlobalDebugComponents);
/* GlobalDebugComponents=padapter->registrypriv.dbg_component; */
- RT_TRACE(0xffffffff, _drv_emerg_, (" ==mp_query_drv_var(_module_mp_): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n", offset, offset, GlobalDebugComponents));
}
- } else
- RT_TRACE(_module_mp_, _drv_emerg_, ("\n mp_query_drv_var: offset(%d) >110\n", offset));
+ }
#endif
#endif
@@ -2208,7 +1881,6 @@ NDIS_STATUS oid_rt_pro_query_dr_variable_hdl(struct oid_par_priv *poid_par_priv)
if (poid_par_priv->information_buf_len < *poid_par_priv->bytes_needed)
return NDIS_STATUS_INVALID_LENGTH;
- RT_TRACE(_module_mp_, _drv_notice_, ("+Query Information, OID_RT_PRO_QUERY_DR_VARIABLE\n"));
pdrv_var = (struct _DR_VARIABLE_STRUCT_ *)poid_par_priv->information_buf;
@@ -2218,9 +1890,6 @@ NDIS_STATUS oid_rt_pro_query_dr_variable_hdl(struct oid_par_priv *poid_par_priv)
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
- RT_TRACE(_module_mp_, _drv_notice_,
- ("-oid_rt_pro_query_dr_variable_hdl: offset=0x%x valule=0x%x\n",
- pdrv_var->offset, pdrv_var->variable));
return status;
#else
@@ -2235,7 +1904,6 @@ NDIS_STATUS oid_rt_pro_rx_packet_type_hdl(struct oid_par_priv *poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
- RT_TRACE(_module_mp_, _drv_err_, ("oid_rt_pro_rx_packet_type_hdl...................\n"));
if (poid_par_priv->information_buf_len < sizeof(UCHAR)) {
status = NDIS_STATUS_INVALID_LENGTH;
@@ -2245,25 +1913,15 @@ NDIS_STATUS oid_rt_pro_rx_packet_type_hdl(struct oid_par_priv *poid_par_priv)
if (poid_par_priv->type_of_oid == SET_OID) {
Adapter->mppriv.rx_with_status = *(UCHAR *) poid_par_priv->information_buf;
- RT_TRACE(_module_rtl871x_ioctl_c_, _drv_err_, ("Query Information, OID_RT_PRO_RX_PACKET_TYPE:%d\n", \
- Adapter->mppriv.rx_with_status));
- RT_TRACE(_module_rtl871x_ioctl_c_, _drv_err_, ("MAC addr=0x%x:0x%x:0x%x:0x%x:0x%x:0x%x\n",
- Adapter->eeprompriv.mac_addr[0], Adapter->eeprompriv.mac_addr[1], Adapter->eeprompriv.mac_addr[2], \
- Adapter->eeprompriv.mac_addr[3], Adapter->eeprompriv.mac_addr[4], Adapter->eeprompriv.mac_addr[5]));
} else {
*(UCHAR *) poid_par_priv->information_buf = Adapter->mppriv.rx_with_status;
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
- RT_TRACE(_module_rtl871x_ioctl_c_, _drv_err_, ("Query Information, OID_RT_PRO_RX_PACKET_TYPE:%d\n", \
- Adapter->mppriv.rx_with_status));
/* *(u32 *)&Adapter->eeprompriv.mac_addr[0]=rtw_read32(Adapter, 0x10250050); */
/* *(u16 *)&Adapter->eeprompriv.mac_addr[4]=rtw_read16(Adapter, 0x10250054); */
- RT_TRACE(_module_rtl871x_ioctl_c_, _drv_err_, ("MAC addr=0x%x:0x%x:0x%x:0x%x:0x%x:0x%x\n",
- Adapter->eeprompriv.mac_addr[0], Adapter->eeprompriv.mac_addr[1], Adapter->eeprompriv.mac_addr[2], \
- Adapter->eeprompriv.mac_addr[3], Adapter->eeprompriv.mac_addr[4], Adapter->eeprompriv.mac_addr[5]));
}
#endif
@@ -2281,7 +1939,6 @@ NDIS_STATUS oid_rt_pro_read_efuse_hdl(struct oid_par_priv *poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
- _func_enter_;
if (poid_par_priv->type_of_oid != QUERY_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -2294,26 +1951,20 @@ NDIS_STATUS oid_rt_pro_read_efuse_hdl(struct oid_par_priv *poid_par_priv)
cnts = pefuse->cnts;
data = pefuse->data;
- RT_TRACE(_module_mp_, _drv_notice_,
- ("+oid_rt_pro_read_efuse_hd: buf_len=%d addr=%d cnts=%d\n",
- poid_par_priv->information_buf_len, addr, cnts));
EFUSE_GetEfuseDefinition(Adapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE);
if ((addr + cnts) > max_available_size) {
- RT_TRACE(_module_mp_, _drv_err_, ("!oid_rt_pro_read_efuse_hdl: parameter error!\n"));
return NDIS_STATUS_NOT_ACCEPTED;
}
_irqlevel_changed_(&oldirql, LOWER);
if (rtw_efuse_access(Adapter, _FALSE, addr, cnts, data) == _FAIL) {
- RT_TRACE(_module_mp_, _drv_err_, ("!oid_rt_pro_read_efuse_hdl: rtw_efuse_access FAIL!\n"));
status = NDIS_STATUS_FAILURE;
} else
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
_irqlevel_changed_(&oldirql, RAISE);
- _func_exit_;
return status;
}
@@ -2330,7 +1981,6 @@ NDIS_STATUS oid_rt_pro_write_efuse_hdl(struct oid_par_priv *poid_par_priv)
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
- _func_enter_;
if (poid_par_priv->type_of_oid != SET_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -2340,14 +1990,10 @@ NDIS_STATUS oid_rt_pro_write_efuse_hdl(struct oid_par_priv *poid_par_priv)
cnts = pefuse->cnts;
data = pefuse->data;
- RT_TRACE(_module_mp_, _drv_notice_,
- ("+oid_rt_pro_write_efuse_hdl: buf_len=%d addr=0x%04x cnts=%d\n",
- poid_par_priv->information_buf_len, addr, cnts));
EFUSE_GetEfuseDefinition(Adapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE);
if ((addr + cnts) > max_available_size) {
- RT_TRACE(_module_mp_, _drv_err_, ("!oid_rt_pro_write_efuse_hdl: parameter error"));
return NDIS_STATUS_NOT_ACCEPTED;
}
@@ -2356,7 +2002,6 @@ NDIS_STATUS oid_rt_pro_write_efuse_hdl(struct oid_par_priv *poid_par_priv)
status = NDIS_STATUS_FAILURE;
_irqlevel_changed_(&oldirql, RAISE);
- _func_exit_;
return status;
}
@@ -2370,9 +2015,7 @@ NDIS_STATUS oid_rt_pro_rw_efuse_pgpkt_hdl(struct oid_par_priv *poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
- _func_enter_;
- /* RT_TRACE(_module_mp_, _drv_info_, ("+oid_rt_pro_rw_efuse_pgpkt_hdl\n")); */
*poid_par_priv->bytes_rw = 0;
@@ -2384,9 +2027,6 @@ NDIS_STATUS oid_rt_pro_rw_efuse_pgpkt_hdl(struct oid_par_priv *poid_par_priv)
_irqlevel_changed_(&oldirql, LOWER);
if (poid_par_priv->type_of_oid == QUERY_OID) {
- RT_TRACE(_module_mp_, _drv_notice_,
- ("oid_rt_pro_rw_efuse_pgpkt_hdl: Read offset=0x%x\n", \
- ppgpkt->offset));
Efuse_PowerSwitch(Adapter, _FALSE, _TRUE);
if (Efuse_PgPacketRead(Adapter, ppgpkt->offset, ppgpkt->data, _FALSE) == _TRUE)
@@ -2395,9 +2035,6 @@ NDIS_STATUS oid_rt_pro_rw_efuse_pgpkt_hdl(struct oid_par_priv *poid_par_priv)
status = NDIS_STATUS_FAILURE;
Efuse_PowerSwitch(Adapter, _FALSE, _FALSE);
} else {
- RT_TRACE(_module_mp_, _drv_notice_,
- ("oid_rt_pro_rw_efuse_pgpkt_hdl: Write offset=0x%x word_en=0x%x\n", \
- ppgpkt->offset, ppgpkt->word_en));
Efuse_PowerSwitch(Adapter, _TRUE, _TRUE);
if (Efuse_PgPacketWrite(Adapter, ppgpkt->offset, ppgpkt->word_en, ppgpkt->data, _FALSE) == _TRUE)
@@ -2409,10 +2046,7 @@ NDIS_STATUS oid_rt_pro_rw_efuse_pgpkt_hdl(struct oid_par_priv *poid_par_priv)
_irqlevel_changed_(&oldirql, RAISE);
- RT_TRACE(_module_mp_, _drv_info_,
- ("-oid_rt_pro_rw_efuse_pgpkt_hdl: status=0x%08X\n", status));
- _func_exit_;
return status;
}
@@ -2427,7 +2061,6 @@ NDIS_STATUS oid_rt_get_efuse_current_size_hdl(struct oid_par_priv *poid_par_priv
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
- _func_enter_;
if (poid_par_priv->type_of_oid != QUERY_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -2444,7 +2077,6 @@ NDIS_STATUS oid_rt_get_efuse_current_size_hdl(struct oid_par_priv *poid_par_priv
} else
status = NDIS_STATUS_FAILURE;
- _func_exit_;
return status;
}
@@ -2454,7 +2086,6 @@ NDIS_STATUS oid_rt_get_efuse_max_size_hdl(struct oid_par_priv *poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
- _func_enter_;
if (poid_par_priv->type_of_oid != QUERY_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -2465,11 +2096,7 @@ NDIS_STATUS oid_rt_get_efuse_max_size_hdl(struct oid_par_priv *poid_par_priv)
*(u32 *)poid_par_priv->information_buf = efuse_GetMaxSize(Adapter);
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
- RT_TRACE(_module_mp_, _drv_info_,
- ("-oid_rt_get_efuse_max_size_hdl: size=%d status=0x%08X\n",
- *(int *)poid_par_priv->information_buf, status));
- _func_exit_;
return status;
}
@@ -2478,18 +2105,14 @@ NDIS_STATUS oid_rt_pro_efuse_hdl(struct oid_par_priv *poid_par_priv)
{
NDIS_STATUS status;
- _func_enter_;
- RT_TRACE(_module_mp_, _drv_info_, ("+oid_rt_pro_efuse_hdl\n"));
if (poid_par_priv->type_of_oid == QUERY_OID)
status = oid_rt_pro_read_efuse_hdl(poid_par_priv);
else
status = oid_rt_pro_write_efuse_hdl(poid_par_priv);
- RT_TRACE(_module_mp_, _drv_info_, ("-oid_rt_pro_efuse_hdl: status=0x%08X\n", status));
- _func_exit_;
return status;
}
@@ -2504,9 +2127,7 @@ NDIS_STATUS oid_rt_pro_efuse_map_hdl(struct oid_par_priv *poid_par_priv)
PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context);
u16 mapLen = 0;
- _func_enter_;
- RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_efuse_map_hdl\n"));
EFUSE_GetEfuseDefinition(Adapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, _FALSE);
@@ -2520,36 +2141,25 @@ NDIS_STATUS oid_rt_pro_efuse_map_hdl(struct oid_par_priv *poid_par_priv)
_irqlevel_changed_(&oldirql, LOWER);
if (poid_par_priv->type_of_oid == QUERY_OID) {
- RT_TRACE(_module_mp_, _drv_info_,
- ("oid_rt_pro_efuse_map_hdl: READ\n"));
if (rtw_efuse_map_read(Adapter, 0, mapLen, data) == _SUCCESS)
*poid_par_priv->bytes_rw = mapLen;
else {
- RT_TRACE(_module_mp_, _drv_err_,
- ("oid_rt_pro_efuse_map_hdl: READ fail\n"));
status = NDIS_STATUS_FAILURE;
}
} else {
/* SET_OID */
- RT_TRACE(_module_mp_, _drv_info_,
- ("oid_rt_pro_efuse_map_hdl: WRITE\n"));
if (rtw_efuse_map_write(Adapter, 0, mapLen, data) == _SUCCESS)
*poid_par_priv->bytes_rw = mapLen;
else {
- RT_TRACE(_module_mp_, _drv_err_,
- ("oid_rt_pro_efuse_map_hdl: WRITE fail\n"));
status = NDIS_STATUS_FAILURE;
}
}
_irqlevel_changed_(&oldirql, RAISE);
- RT_TRACE(_module_mp_, _drv_info_,
- ("-oid_rt_pro_efuse_map_hdl: status=0x%08X\n", status));
- _func_exit_;
return status;
}
@@ -2566,7 +2176,6 @@ NDIS_STATUS oid_rt_set_crystal_cap_hdl(struct oid_par_priv *poid_par_priv)
u32 crystal_cap = 0;
- _func_enter_;
if (poid_par_priv->type_of_oid != SET_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -2584,7 +2193,6 @@ NDIS_STATUS oid_rt_set_crystal_cap_hdl(struct oid_par_priv *poid_par_priv)
SetCrystalCap(Adapter);
_irqlevel_changed_(&oldirql, RAISE);
- _func_exit_;
#endif
return status;
@@ -2600,9 +2208,7 @@ NDIS_STATUS oid_rt_set_rx_packet_type_hdl(struct oid_par_priv *poid_par_priv)
NDIS_STATUS status = NDIS_STATUS_SUCCESS;
/* PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); */
- _func_enter_;
- RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_set_rx_packet_type_hdl\n"));
if (poid_par_priv->type_of_oid != SET_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -2612,7 +2218,6 @@ NDIS_STATUS oid_rt_set_rx_packet_type_hdl(struct oid_par_priv *poid_par_priv)
rx_pkt_type = *((u8 *)poid_par_priv->information_buf); /* 4 */
- RT_TRACE(_module_mp_, _drv_info_, ("rx_pkt_type: %x\n", rx_pkt_type));
#if 0
_irqlevel_changed_(&oldirql, LOWER);
#if 0
@@ -2668,7 +2273,6 @@ NDIS_STATUS oid_rt_set_rx_packet_type_hdl(struct oid_par_priv *poid_par_priv)
#endif
_irqlevel_changed_(&oldirql, RAISE);
#endif
- _func_exit_;
return status;
}
@@ -2685,7 +2289,6 @@ NDIS_STATUS oid_rt_pro_set_tx_agc_offset_hdl(struct oid_par_priv *poid_par_priv)
u32 txagc;
- _func_enter_;
if (poid_par_priv->type_of_oid != SET_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -2694,14 +2297,11 @@ NDIS_STATUS oid_rt_pro_set_tx_agc_offset_hdl(struct oid_par_priv *poid_par_priv)
return NDIS_STATUS_INVALID_LENGTH;
txagc = *(u32 *)poid_par_priv->information_buf;
- RT_TRACE(_module_mp_, _drv_info_,
- ("oid_rt_pro_set_tx_agc_offset_hdl: 0x%08x\n", txagc));
_irqlevel_changed_(&oldirql, LOWER);
SetTxAGCOffset(Adapter, txagc);
_irqlevel_changed_(&oldirql, RAISE);
- _func_exit_;
return status;
#else
@@ -2720,7 +2320,6 @@ NDIS_STATUS oid_rt_pro_set_pkt_test_mode_hdl(struct oid_par_priv *poid_par_priv)
struct mp_priv *pmppriv = &Adapter->mppriv;
u32 type;
- _func_enter_;
if (poid_par_priv->type_of_oid != SET_OID)
return NDIS_STATUS_NOT_ACCEPTED;
@@ -2733,15 +2332,12 @@ NDIS_STATUS oid_rt_pro_set_pkt_test_mode_hdl(struct oid_par_priv *poid_par_priv)
if (_LOOPBOOK_MODE_ == type) {
pmppriv->mode = type;
set_fwstate(pmlmepriv, WIFI_MP_LPBK_STATE); /* append txdesc */
- RT_TRACE(_module_mp_, _drv_info_, ("test mode change to loopback mode:0x%08x.\n", get_fwstate(pmlmepriv)));
} else if (_2MAC_MODE_ == type) {
pmppriv->mode = type;
_clr_fwstate_(pmlmepriv, WIFI_MP_LPBK_STATE);
- RT_TRACE(_module_mp_, _drv_info_, ("test mode change to 2mac mode:0x%08x.\n", get_fwstate(pmlmepriv)));
} else
status = NDIS_STATUS_NOT_ACCEPTED;
- _func_exit_;
return status;
#else
@@ -2756,7 +2352,6 @@ unsigned int mp_ioctl_xmit_packet_hdl(struct oid_par_priv *poid_par_priv)
struct mp_priv *pmp_priv;
struct pkt_attrib *pattrib;
- RT_TRACE(_module_mp_, _drv_notice_, ("+%s\n", __func__));
pparm = (PMP_XMIT_PARM)poid_par_priv->information_buf;
padapter = (PADAPTER)poid_par_priv->adapter_context;
@@ -2839,7 +2434,7 @@ unsigned int mp_ioctl_xmit_packet_hdl(struct oid_par_priv *poid_par_priv)
fctrl = &(pwlanhdr->frame_ctl);
*(fctrl) = 0;
- SetFrameSubType(pframe, WIFI_DATA);
+ set_frame_sub_type(pframe, WIFI_DATA);
_rtw_memcpy(pwlanhdr->addr1, pethhdr->h_dest, ETH_ALEN);
_rtw_memcpy(pwlanhdr->addr2, pethhdr->h_source, ETH_ALEN);
@@ -2876,15 +2471,12 @@ NDIS_STATUS oid_rt_set_power_down_hdl(struct oid_par_priv *poid_par_priv)
#endif
#endif
- _func_enter_;
if (poid_par_priv->type_of_oid != SET_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
return status;
}
- RT_TRACE(_module_mp_, _drv_info_,
- ("\n ===> Setoid_rt_set_power_down_hdl.\n"));
_irqlevel_changed_(&oldirql, LOWER);
@@ -2900,7 +2492,6 @@ NDIS_STATUS oid_rt_set_power_down_hdl(struct oid_par_priv *poid_par_priv)
/* DEBUG_ERR(("\n <=== Query OID_RT_PRO_READ_REGISTER. */
/* Add:0x%08x Width:%d Value:0x%08x\n",RegRWStruct->offset,RegRWStruct->width,RegRWStruct->value)); */
- _func_exit_;
return status;
}
@@ -2914,7 +2505,6 @@ NDIS_STATUS oid_rt_get_power_mode_hdl(struct oid_par_priv *poid_par_priv)
/* _irqL oldirql;
* #endif */
- _func_enter_;
if (poid_par_priv->type_of_oid != QUERY_OID) {
status = NDIS_STATUS_NOT_ACCEPTED;
@@ -2925,15 +2515,12 @@ NDIS_STATUS oid_rt_get_power_mode_hdl(struct oid_par_priv *poid_par_priv)
return status;
}
- RT_TRACE(_module_mp_, _drv_info_,
- ("\n ===> oid_rt_get_power_mode_hdl.\n"));
/* _irqlevel_changed_(&oldirql, LOWER); */
*(int *)poid_par_priv->information_buf = Adapter->registrypriv.low_power ? POWER_LOW : POWER_NORMAL;
*poid_par_priv->bytes_rw = poid_par_priv->information_buf_len;
/* _irqlevel_changed_(&oldirql, RAISE); */
- _func_exit_;
return status;
#else
diff --git a/core/rtw_odm.c b/core/rtw_odm.c
index 780cc39..83e6cfc 100644
--- a/core/rtw_odm.c
+++ b/core/rtw_odm.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2013 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2013 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,188 +11,57 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#include
#include
-const char *odm_comp_str[] = {
- /* BIT0 */"ODM_COMP_DIG",
- /* BIT1 */"ODM_COMP_RA_MASK",
- /* BIT2 */"ODM_COMP_DYNAMIC_TXPWR",
- /* BIT3 */"ODM_COMP_FA_CNT",
- /* BIT4 */"ODM_COMP_RSSI_MONITOR",
- /* BIT5 */"ODM_COMP_CCK_PD",
- /* BIT6 */"ODM_COMP_ANT_DIV",
- /* BIT7 */"ODM_COMP_PWR_SAVE",
- /* BIT8 */"ODM_COMP_PWR_TRAIN",
- /* BIT9 */"ODM_COMP_RATE_ADAPTIVE",
- /* BIT10 */"ODM_COMP_PATH_DIV",
- /* BIT11 */"ODM_COMP_PSD",
- /* BIT12 */"ODM_COMP_DYNAMIC_PRICCA",
- /* BIT13 */"ODM_COMP_RXHP",
- /* BIT14 */"ODM_COMP_MP",
- /* BIT15 */"ODM_COMP_CFO_TRACKING",
- /* BIT16 */"ODM_COMP_ACS",
- /* BIT17 */"PHYDM_COMP_ADAPTIVITY",
- /* BIT18 */"PHYDM_COMP_RA_DBG",
- /* BIT19 */"PHYDM_COMP_TXBF",
- /* BIT20 */"ODM_COMP_EDCA_TURBO",
- /* BIT21 */"ODM_COMP_EARLY_MODE",
- /* BIT22 */"ODM_FW_DEBUG_TRACE",
- /* BIT23 */NULL,
- /* BIT24 */"ODM_COMP_TX_PWR_TRACK",
- /* BIT25 */"ODM_COMP_RX_GAIN_TRACK",
- /* BIT26 */"ODM_COMP_CALIBRATION",
- /* BIT27 */NULL,
- /* BIT28 */"ODM_PHY_CONFIG",
- /* BIT29 */"BEAMFORMING_DEBUG",
- /* BIT30 */"ODM_COMP_COMMON",
- /* BIT31 */"ODM_COMP_INIT",
- /* BIT32 */"ODM_COMP_NOISY_DETECT",
- /* BIT33 */"ODM_COMP_DFS",
-};
-
-#define RTW_ODM_COMP_MAX 34
-
-const char *odm_ability_str[] = {
- /* BIT0 */"ODM_BB_DIG",
- /* BIT1 */"ODM_BB_RA_MASK",
- /* BIT2 */"ODM_BB_DYNAMIC_TXPWR",
- /* BIT3 */"ODM_BB_FA_CNT",
- /* BIT4 */"ODM_BB_RSSI_MONITOR",
- /* BIT5 */"ODM_BB_CCK_PD",
- /* BIT6 */"ODM_BB_ANT_DIV",
- /* BIT7 */"ODM_BB_PWR_SAVE",
- /* BIT8 */"ODM_BB_PWR_TRAIN",
- /* BIT9 */"ODM_BB_RATE_ADAPTIVE",
- /* BIT10 */"ODM_BB_PATH_DIV",
- /* BIT11 */"ODM_BB_PSD",
- /* BIT12 */"ODM_BB_RXHP",
- /* BIT13 */"ODM_BB_ADAPTIVITY",
- /* BIT14 */"ODM_BB_CFO_TRACKING",
- /* BIT15 */"ODM_BB_NHM_CNT",
- /* BIT16 */"ODM_BB_PRIMARY_CCA",
- /* BIT17 */"ODM_BB_TXBF",
- /* BIT18 */NULL,
- /* BIT19 */NULL,
- /* BIT20 */"ODM_MAC_EDCA_TURBO",
- /* BIT21 */"ODM_MAC_EARLY_MODE",
- /* BIT22 */NULL,
- /* BIT23 */NULL,
- /* BIT24 */"ODM_RF_TX_PWR_TRACK",
- /* BIT25 */"ODM_RF_RX_GAIN_TRACK",
- /* BIT26 */"ODM_RF_CALIBRATION",
-};
-
-#define RTW_ODM_ABILITY_MAX 27
-
-const char *odm_dbg_level_str[] = {
- NULL,
- "ODM_DBG_OFF",
- "ODM_DBG_SERIOUS",
- "ODM_DBG_WARNING",
- "ODM_DBG_LOUD",
- "ODM_DBG_TRACE",
-};
-
-#define RTW_ODM_DBG_LEVEL_NUM 6
-
-void rtw_odm_dbg_comp_msg(void *sel, _adapter *adapter)
+u32 rtw_phydm_ability_ops(_adapter *adapter, HAL_PHYDM_OPS ops, u32 ability)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
- DM_ODM_T *odm = &pHalData->odmpriv;
- int cnt = 0;
- u64 dbg_comp = 0;
- int i;
-
- rtw_hal_get_odm_var(adapter, HAL_ODM_DBG_FLAG, &dbg_comp, NULL);
-
- RTW_PRINT_SEL(sel, "odm.DebugComponents = 0x%016llx\n", dbg_comp);
- for (i = 0; i < RTW_ODM_COMP_MAX; i++) {
- if (odm_comp_str[i])
- RTW_PRINT_SEL(sel, "%cBIT%-2d %s\n",
- (BIT0 & (dbg_comp >> i)) ? '+' : ' ', i, odm_comp_str[i]);
- }
-}
-
-inline void rtw_odm_dbg_comp_set(_adapter *adapter, u64 comps)
-{
- rtw_hal_set_odm_var(adapter, HAL_ODM_DBG_FLAG, &comps, _FALSE);
-}
-
-void rtw_odm_dbg_level_msg(void *sel, _adapter *adapter)
-{
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
- DM_ODM_T *odm = &pHalData->odmpriv;
- int cnt = 0;
- u32 dbg_level = 0;
- int i;
-
- rtw_hal_get_odm_var(adapter, HAL_ODM_DBG_LEVEL, &dbg_level, NULL);
- RTW_PRINT_SEL(sel, "odm.DebugLevel = %u\n", dbg_level);
- for (i = 0; i < RTW_ODM_DBG_LEVEL_NUM; i++) {
- if (odm_dbg_level_str[i])
- RTW_PRINT_SEL(sel, "%u %s\n", i, odm_dbg_level_str[i]);
- }
-}
-
-inline void rtw_odm_dbg_level_set(_adapter *adapter, u32 level)
-{
- rtw_hal_set_odm_var(adapter, HAL_ODM_DBG_LEVEL, &level, _FALSE);
-}
+ struct dm_struct *podmpriv = &pHalData->odmpriv;
+ u32 result = 0;
-void rtw_odm_ability_msg(void *sel, _adapter *adapter)
-{
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
- DM_ODM_T *odm = &pHalData->odmpriv;
- int cnt = 0;
- u32 ability = 0;
- int i;
-
- ability = rtw_phydm_ability_get(adapter);
- RTW_PRINT_SEL(sel, "odm.SupportAbility = 0x%08x\n", ability);
- for (i = 0; i < RTW_ODM_ABILITY_MAX; i++) {
- if (odm_ability_str[i])
- RTW_PRINT_SEL(sel, "%cBIT%-2d %s\n",
- (BIT0 << i) & ability ? '+' : ' ', i, odm_ability_str[i]);
+ switch (ops) {
+ case HAL_PHYDM_DIS_ALL_FUNC:
+ podmpriv->support_ability = DYNAMIC_FUNC_DISABLE;
+ halrf_cmn_info_set(podmpriv, HALRF_CMNINFO_ABILITY, DYNAMIC_FUNC_DISABLE);
+ break;
+ case HAL_PHYDM_FUNC_SET:
+ podmpriv->support_ability |= ability;
+ break;
+ case HAL_PHYDM_FUNC_CLR:
+ podmpriv->support_ability &= ~(ability);
+ break;
+ case HAL_PHYDM_ABILITY_BK:
+ /* dm flag backup*/
+ podmpriv->bk_support_ability = podmpriv->support_ability;
+ pHalData->bk_rf_ability = halrf_cmn_info_get(podmpriv, HALRF_CMNINFO_ABILITY);
+ break;
+ case HAL_PHYDM_ABILITY_RESTORE:
+ /* restore dm flag */
+ podmpriv->support_ability = podmpriv->bk_support_ability;
+ halrf_cmn_info_set(podmpriv, HALRF_CMNINFO_ABILITY, pHalData->bk_rf_ability);
+ break;
+ case HAL_PHYDM_ABILITY_SET:
+ podmpriv->support_ability = ability;
+ break;
+ case HAL_PHYDM_ABILITY_GET:
+ result = podmpriv->support_ability;
+ break;
}
-}
-
-inline void rtw_odm_ability_set(_adapter *adapter, u32 ability)
-{
- rtw_phydm_ability_set(adapter, ability);
+ return result;
}
/* set ODM_CMNINFO_IC_TYPE based on chip_type */
void rtw_odm_init_ic_type(_adapter *adapter)
{
- HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
- DM_ODM_T *odm = &hal_data->odmpriv;
+ struct dm_struct *odm = adapter_to_phydm(adapter);
u4Byte ic_type = chip_type_to_odm_ic_type(rtw_get_chip_type(adapter));
rtw_warn_on(!ic_type);
- ODM_CmnInfoInit(odm, ODM_CMNINFO_IC_TYPE, ic_type);
-}
-
-inline void rtw_odm_set_force_igi_lb(_adapter *adapter, u8 lb)
-{
- HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-
- hal_data->u1ForcedIgiLb = lb;
-}
-
-inline u8 rtw_odm_get_force_igi_lb(_adapter *adapter)
-{
- HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
-
- return hal_data->u1ForcedIgiLb;
+ odm_cmn_info_init(odm, ODM_CMNINFO_IC_TYPE, ic_type);
}
void rtw_odm_adaptivity_ver_msg(void *sel, _adapter *adapter)
@@ -206,9 +75,6 @@ void rtw_odm_adaptivity_ver_msg(void *sel, _adapter *adapter)
void rtw_odm_adaptivity_en_msg(void *sel, _adapter *adapter)
{
struct registry_priv *regsty = &adapter->registrypriv;
- struct mlme_priv *mlme = &adapter->mlmepriv;
- HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
- DM_ODM_T *odm = &hal_data->odmpriv;
RTW_PRINT_SEL(sel, "RTW_ADAPTIVITY_EN_");
@@ -284,51 +150,48 @@ bool rtw_odm_adaptivity_needed(_adapter *adapter)
void rtw_odm_adaptivity_parm_msg(void *sel, _adapter *adapter)
{
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
- DM_ODM_T *odm = &pHalData->odmpriv;
+ struct dm_struct *odm = adapter_to_phydm(adapter);
rtw_odm_adaptivity_config_msg(sel, adapter);
RTW_PRINT_SEL(sel, "%10s %16s %16s %22s %12s\n"
- , "TH_L2H_ini", "TH_EDCCA_HL_diff", "TH_L2H_ini_mode2", "TH_EDCCA_HL_diff_mode2", "EDCCA_enable");
+ , "th_l2h_ini", "th_edcca_hl_diff", "th_l2h_ini_mode2", "th_edcca_hl_diff_mode2", "edcca_enable");
RTW_PRINT_SEL(sel, "0x%-8x %-16d 0x%-14x %-22d %-12d\n"
- , (u8)odm->TH_L2H_ini
- , odm->TH_EDCCA_HL_diff
- , (u8)odm->TH_L2H_ini_mode2
- , odm->TH_EDCCA_HL_diff_mode2
- , odm->EDCCA_enable
- );
+ , (u8)odm->th_l2h_ini
+ , odm->th_edcca_hl_diff
+ , (u8)odm->th_l2h_ini_mode2
+ , odm->th_edcca_hl_diff_mode2
+ , odm->edcca_enable
+ );
RTW_PRINT_SEL(sel, "%15s %9s\n", "AdapEnableState", "Adap_Flag");
RTW_PRINT_SEL(sel, "%-15x %-9x\n"
- , odm->Adaptivity_enable
- , odm->adaptivity_flag
- );
+ , odm->adaptivity_enable
+ , odm->adaptivity_flag
+ );
}
-void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 TH_L2H_ini, s8 TH_EDCCA_HL_diff, s8 TH_L2H_ini_mode2, s8 TH_EDCCA_HL_diff_mode2, u8 EDCCA_enable)
+void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 th_l2h_ini, s8 th_edcca_hl_diff, s8 th_l2h_ini_mode2, s8 th_edcca_hl_diff_mode2, u8 edcca_enable)
{
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
- DM_ODM_T *odm = &pHalData->odmpriv;
+ struct dm_struct *odm = adapter_to_phydm(adapter);
- odm->TH_L2H_ini = TH_L2H_ini;
- odm->TH_EDCCA_HL_diff = TH_EDCCA_HL_diff;
- odm->TH_L2H_ini_mode2 = TH_L2H_ini_mode2;
- odm->TH_EDCCA_HL_diff_mode2 = TH_EDCCA_HL_diff_mode2;
- odm->EDCCA_enable = EDCCA_enable;
+ odm->th_l2h_ini = th_l2h_ini;
+ odm->th_edcca_hl_diff = th_edcca_hl_diff;
+ odm->th_l2h_ini_mode2 = th_l2h_ini_mode2;
+ odm->th_edcca_hl_diff_mode2 = th_edcca_hl_diff_mode2;
+ odm->edcca_enable = edcca_enable;
}
void rtw_odm_get_perpkt_rssi(void *sel, _adapter *adapter)
{
- HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
- DM_ODM_T *odm = &(hal_data->odmpriv);
+ struct dm_struct *odm = adapter_to_phydm(adapter);
- RTW_PRINT_SEL(sel, "RxRate = %s, RSSI_A = %d(%%), RSSI_B = %d(%%)\n",
- HDATA_RATE(odm->RxRate), odm->RSSI_A, odm->RSSI_B);
+ RTW_PRINT_SEL(sel, "rx_rate = %s, rssi_a = %d(%%), rssi_b = %d(%%)\n",
+ HDATA_RATE(odm->rx_rate), odm->rssi_a, odm->rssi_b);
}
-void rtw_odm_acquirespinlock(_adapter *adapter, RT_SPINLOCK_TYPE type)
+void rtw_odm_acquirespinlock(_adapter *adapter, enum rt_spinlock_type type)
{
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
_irqL irqL;
@@ -341,7 +204,7 @@ void rtw_odm_acquirespinlock(_adapter *adapter, RT_SPINLOCK_TYPE type)
}
}
-void rtw_odm_releasespinlock(_adapter *adapter, RT_SPINLOCK_TYPE type)
+void rtw_odm_releasespinlock(_adapter *adapter, enum rt_spinlock_type type)
{
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
_irqL irqL;
@@ -354,33 +217,238 @@ void rtw_odm_releasespinlock(_adapter *adapter, RT_SPINLOCK_TYPE type)
}
}
-#ifdef CONFIG_DFS_MASTER
inline u8 rtw_odm_get_dfs_domain(_adapter *adapter)
{
- HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
- PDM_ODM_T pDM_Odm = &(hal_data->odmpriv);
+#ifdef CONFIG_DFS_MASTER
+ struct dm_struct *pDM_Odm = adapter_to_phydm(adapter);
+
+ return pDM_Odm->dfs_region_domain;
+#else
+ return PHYDM_DFS_DOMAIN_UNKNOWN;
+#endif
+}
- return pDM_Odm->DFS_RegionDomain;
+inline u8 rtw_odm_dfs_domain_unknown(_adapter *adapter)
+{
+#ifdef CONFIG_DFS_MASTER
+ return rtw_odm_get_dfs_domain(adapter) == PHYDM_DFS_DOMAIN_UNKNOWN;
+#else
+ return 1;
+#endif
}
+#ifdef CONFIG_DFS_MASTER
inline VOID rtw_odm_radar_detect_reset(_adapter *adapter)
{
- phydm_radar_detect_reset(GET_ODM(adapter));
+ phydm_radar_detect_reset(adapter_to_phydm(adapter));
}
inline VOID rtw_odm_radar_detect_disable(_adapter *adapter)
{
- phydm_radar_detect_disable(GET_ODM(adapter));
+ phydm_radar_detect_disable(adapter_to_phydm(adapter));
}
/* called after ch, bw is set */
inline VOID rtw_odm_radar_detect_enable(_adapter *adapter)
{
- phydm_radar_detect_enable(GET_ODM(adapter));
+ phydm_radar_detect_enable(adapter_to_phydm(adapter));
}
inline BOOLEAN rtw_odm_radar_detect(_adapter *adapter)
{
- return phydm_radar_detect(GET_ODM(adapter));
+ return phydm_radar_detect(adapter_to_phydm(adapter));
}
#endif /* CONFIG_DFS_MASTER */
+
+void rtw_odm_parse_rx_phy_status_chinfo(union recv_frame *rframe, u8 *phys)
+{
+#ifndef DBG_RX_PHYSTATUS_CHINFO
+#define DBG_RX_PHYSTATUS_CHINFO 0
+#endif
+
+#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
+ _adapter *adapter = rframe->u.hdr.adapter;
+ struct dm_struct *phydm = adapter_to_phydm(adapter);
+ struct rx_pkt_attrib *attrib = &rframe->u.hdr.attrib;
+ u8 *wlanhdr = get_recvframe_data(rframe);
+
+ if (phydm->support_ic_type & PHYSTS_2ND_TYPE_IC) {
+ /*
+ * 8723D:
+ * type_0(CCK)
+ * l_rxsc
+ * is filled with primary channel SC, not real rxsc.
+ * 0:LSC, 1:USC
+ * type_1(OFDM)
+ * rf_mode
+ * RF bandwidth when RX
+ * l_rxsc(legacy), ht_rxsc
+ * see below RXSC N-series
+ * type_2(Not used)
+ */
+ /*
+ * 8821C, 8822B:
+ * type_0(CCK)
+ * l_rxsc
+ * is filled with primary channel SC, not real rxsc.
+ * 0:LSC, 1:USC
+ * type_1(OFDM)
+ * rf_mode
+ * RF bandwidth when RX
+ * l_rxsc(legacy), ht_rxsc
+ * see below RXSC AC-series
+ * type_2(Not used)
+ */
+
+ if ((*phys & 0xf) == 0) {
+ struct phy_status_rpt_jaguar2_type0 *phys_t0 = (struct phy_status_rpt_jaguar2_type0 *)phys;
+
+ if (DBG_RX_PHYSTATUS_CHINFO) {
+ RTW_PRINT("phys_t%u ta="MAC_FMT" %s, %s(band:%u, ch:%u, l_rxsc:%u)\n"
+ , *phys & 0xf
+ , MAC_ARG(get_ta(wlanhdr))
+ , is_broadcast_mac_addr(get_ra(wlanhdr)) ? "BC" : is_multicast_mac_addr(get_ra(wlanhdr)) ? "MC" : "UC"
+ , HDATA_RATE(attrib->data_rate)
+ , phys_t0->band, phys_t0->channel, phys_t0->rxsc
+ );
+ }
+
+ } else if ((*phys & 0xf) == 1) {
+ struct phy_status_rpt_jaguar2_type1 *phys_t1 = (struct phy_status_rpt_jaguar2_type1 *)phys;
+ u8 rxsc = (attrib->data_rate > DESC_RATE11M && attrib->data_rate < DESC_RATEMCS0) ? phys_t1->l_rxsc : phys_t1->ht_rxsc;
+ u8 pkt_cch = 0;
+ u8 pkt_bw = CHANNEL_WIDTH_20;
+
+ #if ODM_IC_11N_SERIES_SUPPORT
+ if (phydm->support_ic_type & ODM_IC_11N_SERIES) {
+ /* RXSC N-series */
+ #define RXSC_DUP 0
+ #define RXSC_LSC 1
+ #define RXSC_USC 2
+ #define RXSC_40M 3
+
+ static const s8 cch_offset_by_rxsc[4] = {0, -2, 2, 0};
+
+ if (phys_t1->rf_mode == 0) {
+ pkt_cch = phys_t1->channel;
+ pkt_bw = CHANNEL_WIDTH_20;
+ } else if (phys_t1->rf_mode == 1) {
+ if (rxsc == RXSC_LSC || rxsc == RXSC_USC) {
+ pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];
+ pkt_bw = CHANNEL_WIDTH_20;
+ } else if (rxsc == RXSC_40M) {
+ pkt_cch = phys_t1->channel;
+ pkt_bw = CHANNEL_WIDTH_40;
+ }
+ } else
+ rtw_warn_on(1);
+
+ goto type1_end;
+ }
+ #endif /* ODM_IC_11N_SERIES_SUPPORT */
+
+ #if ODM_IC_11AC_SERIES_SUPPORT
+ if (phydm->support_ic_type & ODM_IC_11AC_SERIES) {
+ /* RXSC AC-series */
+ #define RXSC_DUP 0 /* 0: RX from all SC of current rf_mode */
+
+ #define RXSC_LL20M_OF_160M 8 /* 1~8: RX from 20MHz SC */
+ #define RXSC_L20M_OF_160M 6
+ #define RXSC_L20M_OF_80M 4
+ #define RXSC_L20M_OF_40M 2
+ #define RXSC_U20M_OF_40M 1
+ #define RXSC_U20M_OF_80M 3
+ #define RXSC_U20M_OF_160M 5
+ #define RXSC_UU20M_OF_160M 7
+
+ #define RXSC_L40M_OF_160M 12 /* 9~12: RX from 40MHz SC */
+ #define RXSC_L40M_OF_80M 10
+ #define RXSC_U40M_OF_80M 9
+ #define RXSC_U40M_OF_160M 11
+
+ #define RXSC_L80M_OF_160M 14 /* 13~14: RX from 80MHz SC */
+ #define RXSC_U80M_OF_160M 13
+
+ static const s8 cch_offset_by_rxsc[15] = {0, 2, -2, 6, -6, 10, -10, 14, -14, 4, -4, 12, -12, 8, -8};
+
+ if (phys_t1->rf_mode > 3) {
+ /* invalid rf_mode */
+ rtw_warn_on(1);
+ goto type1_end;
+ }
+
+ if (phys_t1->rf_mode == 0) {
+ /* RF 20MHz */
+ pkt_cch = phys_t1->channel;
+ pkt_bw = CHANNEL_WIDTH_20;
+ goto type1_end;
+ }
+
+ if (rxsc == 0) {
+ /* RF and RX with same BW */
+ if (attrib->data_rate >= DESC_RATEMCS0) {
+ pkt_cch = phys_t1->channel;
+ pkt_bw = phys_t1->rf_mode;
+ }
+ goto type1_end;
+ }
+
+ if ((phys_t1->rf_mode == 1 && rxsc >= 1 && rxsc <= 2) /* RF 40MHz, RX 20MHz */
+ || (phys_t1->rf_mode == 2 && rxsc >= 1 && rxsc <= 4) /* RF 80MHz, RX 20MHz */
+ || (phys_t1->rf_mode == 3 && rxsc >= 1 && rxsc <= 8) /* RF 160MHz, RX 20MHz */
+ ) {
+ pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];
+ pkt_bw = CHANNEL_WIDTH_20;
+ } else if ((phys_t1->rf_mode == 2 && rxsc >= 9 && rxsc <= 10) /* RF 80MHz, RX 40MHz */
+ || (phys_t1->rf_mode == 3 && rxsc >= 9 && rxsc <= 12) /* RF 160MHz, RX 40MHz */
+ ) {
+ if (attrib->data_rate >= DESC_RATEMCS0) {
+ pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];
+ pkt_bw = CHANNEL_WIDTH_40;
+ }
+ } else if ((phys_t1->rf_mode == 3 && rxsc >= 13 && rxsc <= 14) /* RF 160MHz, RX 80MHz */
+ ) {
+ if (attrib->data_rate >= DESC_RATEMCS0) {
+ pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc];
+ pkt_bw = CHANNEL_WIDTH_80;
+ }
+ } else
+ rtw_warn_on(1);
+
+ }
+ #endif /* ODM_IC_11AC_SERIES_SUPPORT */
+
+type1_end:
+ if (DBG_RX_PHYSTATUS_CHINFO) {
+ RTW_PRINT("phys_t%u ta="MAC_FMT" %s, %s(band:%u, ch:%u, rf_mode:%u, l_rxsc:%u, ht_rxsc:%u) => %u,%u\n"
+ , *phys & 0xf
+ , MAC_ARG(get_ta(wlanhdr))
+ , is_broadcast_mac_addr(get_ra(wlanhdr)) ? "BC" : is_multicast_mac_addr(get_ra(wlanhdr)) ? "MC" : "UC"
+ , HDATA_RATE(attrib->data_rate)
+ , phys_t1->band, phys_t1->channel, phys_t1->rf_mode, phys_t1->l_rxsc, phys_t1->ht_rxsc
+ , pkt_cch, pkt_bw
+ );
+ }
+
+ /* for now, only return cneter channel of 20MHz packet */
+ if (pkt_cch && pkt_bw == CHANNEL_WIDTH_20)
+ attrib->ch = pkt_cch;
+
+ } else {
+ struct phy_status_rpt_jaguar2_type2 *phys_t2 = (struct phy_status_rpt_jaguar2_type2 *)phys;
+
+ if (DBG_RX_PHYSTATUS_CHINFO) {
+ RTW_PRINT("phys_t%u ta="MAC_FMT" %s, %s(band:%u, ch:%u, l_rxsc:%u, ht_rxsc:%u)\n"
+ , *phys & 0xf
+ , MAC_ARG(get_ta(wlanhdr))
+ , is_broadcast_mac_addr(get_ra(wlanhdr)) ? "BC" : is_multicast_mac_addr(get_ra(wlanhdr)) ? "MC" : "UC"
+ , HDATA_RATE(attrib->data_rate)
+ , phys_t2->band, phys_t2->channel, phys_t2->l_rxsc, phys_t2->ht_rxsc
+ );
+ }
+ }
+ }
+#endif /* (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) */
+
+}
+
diff --git a/core/rtw_p2p.c b/core/rtw_p2p.c
index 02f6a31..964f1c7 100644
--- a/core/rtw_p2p.c
+++ b/core/rtw_p2p.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,12 +11,7 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#define _RTW_P2P_C_
#include
@@ -52,7 +47,7 @@ static u32 go_add_group_info_attr(struct wifidirect_info *pwdinfo, u8 *pbuf)
_adapter *padapter = pwdinfo->padapter;
struct sta_priv *pstapriv = &padapter->stapriv;
- RTW_INFO("%s\n", __FUNCTION__);
+ RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
pdata_attr = rtw_zmalloc(MAX_P2P_IE_LEN);
@@ -85,7 +80,7 @@ static u32 go_add_group_info_attr(struct wifidirect_info *pwdinfo, u8 *pbuf)
pcur += ETH_ALEN;
/* P2P interface address */
- _rtw_memcpy(pcur, psta->hwaddr, ETH_ALEN);
+ _rtw_memcpy(pcur, psta->cmn.mac_addr, ETH_ALEN);
pcur += ETH_ALEN;
*pcur = psta->dev_cap;
@@ -182,7 +177,7 @@ static void issue_group_disc_req(struct wifidirect_info *pwdinfo, u8 *da)
SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
pmlmeext->mgnt_seq++;
- SetFrameSubType(pframe, WIFI_ACTION);
+ set_frame_sub_type(pframe, WIFI_ACTION);
pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
@@ -242,7 +237,7 @@ static void issue_p2p_devdisc_resp(struct wifidirect_info *pwdinfo, u8 *da, u8 s
SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
pmlmeext->mgnt_seq++;
- SetFrameSubType(pframe, WIFI_ACTION);
+ set_frame_sub_type(pframe, WIFI_ACTION);
pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
@@ -320,7 +315,7 @@ static void issue_p2p_provision_resp(struct wifidirect_info *pwdinfo, u8 *raddr,
SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
pmlmeext->mgnt_seq++;
- SetFrameSubType(pframe, WIFI_ACTION);
+ set_frame_sub_type(pframe, WIFI_ACTION);
pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
@@ -424,7 +419,7 @@ static void issue_p2p_presence_resp(struct wifidirect_info *pwdinfo, u8 *da, u8
SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
pmlmeext->mgnt_seq++;
- SetFrameSubType(pframe, WIFI_ACTION);
+ set_frame_sub_type(pframe, WIFI_ACTION);
pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
@@ -757,6 +752,7 @@ u32 build_probe_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 tunnel
_adapter *padapter = pwdinfo->padapter;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct wifi_display_info *pwfd_info = padapter->wdinfo.wfd_info;
+ u16 v16 = 0;
if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
goto exit;
@@ -794,36 +790,43 @@ u32 build_probe_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 tunnel
if (is_any_client_associated(pwdinfo->padapter)) {
if (pwdinfo->wfd_tdls_enable) {
/* TDLS mode + WSD ( WFD Service Discovery ) */
- RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT);
+ v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT;
+ RTW_PUT_BE16(wfdie + wfdielen, v16);
} else {
/* WiFi Direct mode + WSD ( WFD Service Discovery ) */
- RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT);
+ v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT;
+ RTW_PUT_BE16(wfdie + wfdielen, v16);
}
} else {
if (pwdinfo->wfd_tdls_enable) {
/* available for WFD session + TDLS mode + WSD ( WFD Service Discovery ) */
- RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT);
+ v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT;
+ RTW_PUT_BE16(wfdie + wfdielen, v16);
} else {
/* available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */
- RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT);
+ v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT;
+ RTW_PUT_BE16(wfdie + wfdielen, v16);
}
}
} else {
if (pwdinfo->wfd_tdls_enable) {
/* available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */
- RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT);
+ v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT;
+ RTW_PUT_BE16(wfdie + wfdielen, v16);
} else {
-
/* available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */
- RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT);
+ v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT;
+ RTW_PUT_BE16(wfdie + wfdielen, v16);
}
}
} else {
- if (pwdinfo->wfd_tdls_enable)
- RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT);
- else
- RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT);
-
+ if (pwdinfo->wfd_tdls_enable) {
+ v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT;
+ RTW_PUT_BE16(wfdie + wfdielen, v16);
+ } else {
+ v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT;
+ RTW_PUT_BE16(wfdie + wfdielen, v16);
+ }
}
wfdielen += 2;
@@ -2328,7 +2331,7 @@ u32 process_assoc_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint l
if (!rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO))
return P2P_STATUS_FAIL_REQUEST_UNABLE;
- frame_type = GetFrameSubType(pframe);
+ frame_type = get_frame_sub_type(pframe);
if (frame_type == WIFI_ASSOCREQ)
ie_offset = _ASOCREQ_IE_OFFSET_;
else /* WIFI_REASSOCREQ */
@@ -2467,7 +2470,7 @@ u32 process_p2p_devdisc_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint le
/* _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); */
/* issue GO Discoverability Request */
- issue_group_disc_req(pwdinfo, psta->hwaddr);
+ issue_group_disc_req(pwdinfo, psta->cmn.mac_addr);
/* _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); */
status = P2P_STATUS_SUCCESS;
@@ -2491,7 +2494,7 @@ u32 process_p2p_devdisc_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint le
/* issue Device Discoverability Response */
- issue_p2p_devdisc_resp(pwdinfo, GetAddr2Ptr(pframe), status, dialogToken);
+ issue_p2p_devdisc_resp(pwdinfo, get_addr2_ptr(pframe), status, dialogToken);
return (status == P2P_STATUS_SUCCESS) ? _TRUE : _FALSE;
@@ -2535,7 +2538,7 @@ u8 process_p2p_provdisc_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint l
break;
}
}
- issue_p2p_provision_resp(pwdinfo, GetAddr2Ptr(pframe), frame_body, uconfig_method);
+ issue_p2p_provision_resp(pwdinfo, get_addr2_ptr(pframe), frame_body, uconfig_method);
}
}
RTW_INFO("[%s] config method = %s\n", __FUNCTION__, pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req);
@@ -2571,26 +2574,15 @@ u8 rtw_p2p_get_peer_ch_list(struct wifidirect_info *pwdinfo, u8 *ch_content, u8
return ch_no;
}
-u8 rtw_p2p_check_peer_oper_ch(struct mlme_ext_priv *pmlmeext, u8 ch)
-{
- u8 i = 0;
-
- for (i = 0; i < pmlmeext->max_chan_nums; i++) {
- if (pmlmeext->channel_set[i].ChannelNum == ch)
- return _SUCCESS;
- }
-
- return _FAIL;
-}
-
-u8 rtw_p2p_ch_inclusion(struct mlme_ext_priv *pmlmeext, u8 *peer_ch_list, u8 peer_ch_num, u8 *ch_list_inclusioned)
+u8 rtw_p2p_ch_inclusion(_adapter *adapter, u8 *peer_ch_list, u8 peer_ch_num, u8 *ch_list_inclusioned)
{
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
int i = 0, j = 0, temp = 0;
u8 ch_no = 0;
for (i = 0; i < peer_ch_num; i++) {
- for (j = temp; j < pmlmeext->max_chan_nums; j++) {
- if (*(peer_ch_list + i) == pmlmeext->channel_set[j].ChannelNum) {
+ for (j = temp; j < rfctl->max_chan_nums; j++) {
+ if (*(peer_ch_list + i) == rfctl->channel_set[j].ChannelNum) {
ch_list_inclusioned[ch_no++] = *(peer_ch_list + i);
temp = j;
break;
@@ -2708,14 +2700,14 @@ u8 process_p2p_group_negotation_req(struct wifidirect_info *pwdinfo, u8 *pframe,
RTW_INFO(FUNC_ADPT_FMT" listen channel :%u\n", FUNC_ADPT_ARG(padapter), pwdinfo->nego_req_info.peer_ch);
attr_contentlen = 0;
- if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INTENTED_IF_ADDR, pwdinfo->p2p_peer_interface_addr, &attr_contentlen)) {
+ if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INTENDED_IF_ADDR, pwdinfo->p2p_peer_interface_addr, &attr_contentlen)) {
if (attr_contentlen != ETH_ALEN)
_rtw_memset(pwdinfo->p2p_peer_interface_addr, 0x00, ETH_ALEN);
}
if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, ch_content, &ch_cnt)) {
peer_ch_num = rtw_p2p_get_peer_ch_list(pwdinfo, ch_content, ch_cnt, peer_ch_list);
- ch_num_inclusioned = rtw_p2p_ch_inclusion(&padapter->mlmeextpriv, peer_ch_list, peer_ch_num, ch_list_inclusioned);
+ ch_num_inclusioned = rtw_p2p_ch_inclusion(padapter, peer_ch_list, peer_ch_num, ch_list_inclusioned);
if (ch_num_inclusioned == 0) {
RTW_INFO("[%s] No common channel in channel list!\n", __FUNCTION__);
@@ -2853,7 +2845,7 @@ u8 process_p2p_group_negotation_resp(struct wifidirect_info *pwdinfo, u8 *pframe
/* Try to get the peer's interface address */
attr_contentlen = 0;
- if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INTENTED_IF_ADDR, pwdinfo->p2p_peer_interface_addr, &attr_contentlen)) {
+ if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INTENDED_IF_ADDR, pwdinfo->p2p_peer_interface_addr, &attr_contentlen)) {
if (attr_contentlen != ETH_ALEN)
_rtw_memset(pwdinfo->p2p_peer_interface_addr, 0x00, ETH_ALEN);
}
@@ -2910,7 +2902,7 @@ u8 process_p2p_group_negotation_resp(struct wifidirect_info *pwdinfo, u8 *pframe
RTW_INFO("[%s] channel list attribute found, len = %d\n", __FUNCTION__, pwdinfo->channel_list_attr_len);
peer_ch_num = rtw_p2p_get_peer_ch_list(pwdinfo, pwdinfo->channel_list_attr, pwdinfo->channel_list_attr_len, peer_ch_list);
- ch_num_inclusioned = rtw_p2p_ch_inclusion(&padapter->mlmeextpriv, peer_ch_list, peer_ch_num, ch_list_inclusioned);
+ ch_num_inclusioned = rtw_p2p_ch_inclusion(padapter, peer_ch_list, peer_ch_num, ch_list_inclusioned);
if (ch_num_inclusioned == 0) {
RTW_INFO("[%s] No common channel in channel list!\n", __FUNCTION__);
@@ -3004,9 +2996,8 @@ u8 process_p2p_group_negotation_confirm(struct wifidirect_info *pwdinfo, u8 *pfr
result = attr_content;
if (attr_content == P2P_STATUS_SUCCESS) {
- u8 bcancelled = 0;
- _cancel_timer(&pwdinfo->restore_p2p_state_timer, &bcancelled);
+ _cancel_timer_ex(&pwdinfo->restore_p2p_state_timer);
/* Commented by Albert 20100911 */
/* Todo: Need to handle the case which both Intents are the same. */
@@ -3073,7 +3064,7 @@ u8 process_p2p_presence_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint le
/* todo: check NoA attribute */
- issue_p2p_presence_resp(pwdinfo, GetAddr2Ptr(pframe), status, dialogToken);
+ issue_p2p_presence_resp(pwdinfo, get_addr2_ptr(pframe), status, dialogToken);
return _TRUE;
}
@@ -3082,24 +3073,23 @@ void find_phase_handler(_adapter *padapter)
{
struct wifidirect_info *pwdinfo = &padapter->wdinfo;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
- NDIS_802_11_SSID ssid;
+ struct sitesurvey_parm parm;
_irqL irqL;
u8 _status = 0;
- _func_enter_;
- _rtw_memset((unsigned char *)&ssid, 0, sizeof(NDIS_802_11_SSID));
- _rtw_memcpy(ssid.Ssid, pwdinfo->p2p_wildcard_ssid, P2P_WILDCARD_SSID_LEN);
- ssid.SsidLength = P2P_WILDCARD_SSID_LEN;
+ rtw_init_sitesurvey_parm(padapter, &parm);
+ _rtw_memcpy(&parm.ssid[0].Ssid, pwdinfo->p2p_wildcard_ssid, P2P_WILDCARD_SSID_LEN);
+ parm.ssid[0].SsidLength = P2P_WILDCARD_SSID_LEN;
+ parm.ssid_num = 1;
rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH);
_enter_critical_bh(&pmlmepriv->lock, &irqL);
- _status = rtw_sitesurvey_cmd(padapter, &ssid, 1, NULL, 0);
+ _status = rtw_sitesurvey_cmd(padapter, &parm);
_exit_critical_bh(&pmlmepriv->lock, &irqL);
- _func_exit_;
}
void p2p_concurrent_handler(_adapter *padapter);
@@ -3109,7 +3099,6 @@ void restore_p2p_state_handler(_adapter *padapter)
struct wifidirect_info *pwdinfo = &padapter->wdinfo;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
- _func_enter_;
if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL))
rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE);
@@ -3122,7 +3111,7 @@ void restore_p2p_state_handler(_adapter *padapter)
if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_RSP)) {
set_channel_bwmode(padapter, union_ch, union_offset, union_bw);
- rtw_mi_buddy_issue_nulldata(padapter, NULL, 0, 3, 500);
+ rtw_back_opch(padapter);
}
}
#endif
@@ -3138,42 +3127,36 @@ void restore_p2p_state_handler(_adapter *padapter)
set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
#endif
}
- _func_exit_;
}
void pre_tx_invitereq_handler(_adapter *padapter)
{
struct wifidirect_info *pwdinfo = &padapter->wdinfo;
u8 val8 = 1;
- _func_enter_;
set_channel_bwmode(padapter, pwdinfo->invitereq_info.peer_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
issue_probereq_p2p(padapter, NULL);
_set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT);
- _func_exit_;
}
void pre_tx_provdisc_handler(_adapter *padapter)
{
struct wifidirect_info *pwdinfo = &padapter->wdinfo;
u8 val8 = 1;
- _func_enter_;
set_channel_bwmode(padapter, pwdinfo->tx_prov_disc_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
issue_probereq_p2p(padapter, NULL);
_set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT);
- _func_exit_;
}
void pre_tx_negoreq_handler(_adapter *padapter)
{
struct wifidirect_info *pwdinfo = &padapter->wdinfo;
u8 val8 = 1;
- _func_enter_;
set_channel_bwmode(padapter, pwdinfo->nego_req_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
@@ -3182,7 +3165,6 @@ void pre_tx_negoreq_handler(_adapter *padapter)
issue_probereq_p2p(padapter , pwdinfo->nego_req_info.peerDevAddr);
_set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT);
- _func_exit_;
}
#ifdef CONFIG_CONCURRENT_MODE
@@ -3192,7 +3174,12 @@ void p2p_concurrent_handler(_adapter *padapter)
struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
u8 val8;
- _func_enter_;
+
+#ifdef CONFIG_IOCTL_CFG80211
+ if (pwdinfo->driver_interface == DRIVER_CFG80211
+ && !rtw_cfg80211_get_is_roch(padapter))
+ return;
+#endif
if (rtw_mi_check_status(padapter, MI_LINKED)) {
u8 union_ch = rtw_mi_get_union_chan(padapter);
@@ -3202,10 +3189,10 @@ void p2p_concurrent_handler(_adapter *padapter)
pwdinfo->operating_channel = union_ch;
if (pwdinfo->driver_interface == DRIVER_CFG80211) {
- RTW_INFO("%s, switch ch back to union_ch=%d\n", __func__, union_ch);
+ RTW_INFO("%s, switch ch back to union=%u,%u, %u\n"
+ , __func__, union_ch, union_bw, union_offset);
set_channel_bwmode(padapter, union_ch, union_offset, union_bw);
-
- rtw_mi_buddy_issue_nulldata(padapter, NULL, 0, 3, 500);
+ rtw_back_opch(padapter);
} else if (pwdinfo->driver_interface == DRIVER_WEXT) {
if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) {
@@ -3215,8 +3202,7 @@ void p2p_concurrent_handler(_adapter *padapter)
RTW_INFO("[%s] P2P_STATE_IDLE, ext_listen_period = %d\n", __FUNCTION__, pwdinfo->ext_listen_period);
if (union_ch != pwdinfo->listen_channel) {
- /* Will switch to listen channel so that need to send the NULL data with PW bit to AP. */
- rtw_mi_buddy_issue_nulldata(padapter, NULL, 1, 3, 500);
+ rtw_leave_opch(padapter);
set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
}
@@ -3229,6 +3215,7 @@ void p2p_concurrent_handler(_adapter *padapter)
/* Todo: To check the value of pwdinfo->ext_listen_period is equal to 0 or not. */
_set_timer(&pwdinfo->ap_p2p_switch_timer, pwdinfo->ext_listen_period);
}
+
} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_LISTEN) ||
rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL) ||
(rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING) && pwdinfo->nego_req_info.benable == _FALSE) ||
@@ -3248,17 +3235,19 @@ void p2p_concurrent_handler(_adapter *padapter)
rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
}
rtw_p2p_set_state(pwdinfo, P2P_STATE_IDLE);
- rtw_mi_buddy_issue_nulldata(padapter, NULL, 0, 3, 500);
+ rtw_back_opch(padapter);
}
/* Todo: To check the value of pwdinfo->ext_listen_interval is equal to 0 or not. */
_set_timer(&pwdinfo->ap_p2p_switch_timer, pwdinfo->ext_listen_interval);
+
} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_OK)) {
/* The driver had finished the P2P handshake successfully. */
val8 = 0;
rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
set_channel_bwmode(padapter, union_ch, union_offset, union_bw);
- rtw_mi_buddy_issue_nulldata(padapter, NULL, 0, 3, 500);
+ rtw_back_opch(padapter);
+
} else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ)) {
val8 = 1;
set_channel_bwmode(padapter, pwdinfo->tx_prov_disc_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
@@ -3289,18 +3278,171 @@ void p2p_concurrent_handler(_adapter *padapter)
RTW_INFO("%s, buddy not linked, go nego ok, not back to listen channel\n", __func__);
}
- _func_exit_;
}
#endif
#ifdef CONFIG_IOCTL_CFG80211
-static void ro_ch_handler(_adapter *padapter)
+u8 roch_stay_in_cur_chan(_adapter *padapter)
{
+ int i;
+ _adapter *iface;
+ struct mlme_priv *pmlmepriv;
+ struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+ u8 rst = _FALSE;
+
+ for (i = 0; i < dvobj->iface_nums; i++) {
+ iface = dvobj->padapters[i];
+ if (iface) {
+ pmlmepriv = &iface->mlmepriv;
+
+ if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING | WIFI_UNDER_WPS) == _TRUE) {
+ RTW_ERR(ADPT_FMT"- _FW_UNDER_LINKING |WIFI_UNDER_WPS (mlme state:0x%x)\n",
+ ADPT_ARG(iface), get_fwstate(&iface->mlmepriv));
+ rst = _TRUE;
+ break;
+ }
+ #ifdef CONFIG_AP_MODE
+ if (MLME_IS_AP(iface) || MLME_IS_MESH(iface)) {
+ if (rtw_ap_sta_linking_state_check(iface) == _TRUE) {
+ RTW_ERR(ADPT_FMT"- SoftAP/Mesh -have sta under linking\n", ADPT_ARG(iface));
+ rst = _TRUE;
+ break;
+ }
+ }
+ #endif
+ }
+ }
+
+ return rst;
+}
+
+static int ro_ch_handler(_adapter *adapter, u8 *buf)
+{
+ int ret = H2C_SUCCESS;
+ struct p2p_roch_parm *roch_parm = (struct p2p_roch_parm *)buf;
+ struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter);
+ struct cfg80211_wifidirect_info *pcfg80211_wdinfo = &adapter->cfg80211_wdinfo;
+ struct wifidirect_info *pwdinfo = &adapter->wdinfo;
+ struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
+ u8 ready_on_channel = _FALSE;
+ u8 remain_ch;
+ unsigned int duration;
+
+ _enter_critical_mutex(&pwdev_priv->roch_mutex, NULL);
+
+ if (rtw_cfg80211_get_is_roch(adapter) != _TRUE)
+ goto exit;
+
+ remain_ch = (u8)ieee80211_frequency_to_channel(roch_parm->ch.center_freq);
+ duration = roch_parm->duration;
+
+ RTW_INFO(FUNC_ADPT_FMT" ch:%u duration:%d, cookie:0x%llx\n"
+ , FUNC_ADPT_ARG(adapter), remain_ch, roch_parm->duration, roch_parm->cookie);
+
+ if (roch_parm->wdev && roch_parm->cookie) {
+ if (pcfg80211_wdinfo->ro_ch_wdev != roch_parm->wdev) {
+ RTW_WARN(FUNC_ADPT_FMT" ongoing wdev:%p, wdev:%p\n"
+ , FUNC_ADPT_ARG(adapter), pcfg80211_wdinfo->ro_ch_wdev, roch_parm->wdev);
+ rtw_warn_on(1);
+ }
+
+ if (pcfg80211_wdinfo->remain_on_ch_cookie != roch_parm->cookie) {
+ RTW_WARN(FUNC_ADPT_FMT" ongoing cookie:0x%llx, cookie:0x%llx\n"
+ , FUNC_ADPT_ARG(adapter), pcfg80211_wdinfo->remain_on_ch_cookie, roch_parm->cookie);
+ rtw_warn_on(1);
+ }
+ }
+
+ if (roch_stay_in_cur_chan(adapter) == _TRUE) {
+ remain_ch = rtw_mi_get_union_chan(adapter);
+ RTW_INFO(FUNC_ADPT_FMT" stay in union ch:%d\n", FUNC_ADPT_ARG(adapter), remain_ch);
+ }
+
+ #ifdef CONFIG_CONCURRENT_MODE
+ if (rtw_mi_check_status(adapter, MI_LINKED) && (0 != rtw_mi_get_union_chan(adapter))) {
+ if ((remain_ch != rtw_mi_get_union_chan(adapter)) && !check_fwstate(&adapter->mlmepriv, _FW_LINKED)) {
+ if (remain_ch != pmlmeext->cur_channel
+ #ifdef RTW_ROCH_BACK_OP
+ || ATOMIC_READ(&pwdev_priv->switch_ch_to) == 1
+ #endif
+ ) {
+ rtw_leave_opch(adapter);
+
+ #ifdef RTW_ROCH_BACK_OP
+ RTW_INFO("%s, set switch ch timer, duration=%d\n", __func__, duration - pwdinfo->ext_listen_interval);
+ ATOMIC_SET(&pwdev_priv->switch_ch_to, 0);
+ _set_timer(&pwdinfo->ap_p2p_switch_timer, duration - pwdinfo->ext_listen_interval);
+ #endif
+ }
+ }
+ ready_on_channel = _TRUE;
+ } else
+ #endif /* CONFIG_CONCURRENT_MODE */
+ {
+ if (remain_ch != rtw_get_oper_ch(adapter))
+ ready_on_channel = _TRUE;
+ }
+
+ if (ready_on_channel == _TRUE) {
+ #ifndef RTW_SINGLE_WIPHY
+ if (!check_fwstate(&adapter->mlmepriv, _FW_LINKED))
+ #endif
+ {
+ #ifdef CONFIG_CONCURRENT_MODE
+ if (rtw_get_oper_ch(adapter) != remain_ch)
+ #endif
+ {
+ /* if (!padapter->mlmepriv.LinkDetectInfo.bBusyTraffic) */
+ set_channel_bwmode(adapter, remain_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20);
+ }
+ }
+ }
+
+ #ifdef CONFIG_BT_COEXIST
+ rtw_btcoex_ScanNotify(adapter, _TRUE);
+ #endif
+
+ RTW_INFO("%s, set ro ch timer, duration=%d\n", __func__, duration);
+ _set_timer(&pcfg80211_wdinfo->remain_on_ch_timer, duration);
+
+exit:
+ _exit_critical_mutex(&pwdev_priv->roch_mutex, NULL);
+
+ return ret;
+}
+
+static int cancel_ro_ch_handler(_adapter *padapter, u8 *buf)
+{
+ int ret = H2C_SUCCESS;
+ struct p2p_roch_parm *roch_parm = (struct p2p_roch_parm *)buf;
+ struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter);
struct cfg80211_wifidirect_info *pcfg80211_wdinfo = &padapter->cfg80211_wdinfo;
+ struct wireless_dev *wdev;
struct wifidirect_info *pwdinfo = &padapter->wdinfo;
- struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
u8 ch, bw, offset;
- _func_enter_;
+
+ _enter_critical_mutex(&pwdev_priv->roch_mutex, NULL);
+
+ if (rtw_cfg80211_get_is_roch(padapter) != _TRUE)
+ goto exit;
+
+ if (roch_parm->wdev && roch_parm->cookie) {
+ if (pcfg80211_wdinfo->ro_ch_wdev != roch_parm->wdev) {
+ RTW_WARN(FUNC_ADPT_FMT" ongoing wdev:%p, wdev:%p\n"
+ , FUNC_ADPT_ARG(padapter), pcfg80211_wdinfo->ro_ch_wdev, roch_parm->wdev);
+ rtw_warn_on(1);
+ }
+
+ if (pcfg80211_wdinfo->remain_on_ch_cookie != roch_parm->cookie) {
+ RTW_WARN(FUNC_ADPT_FMT" ongoing cookie:0x%llx, cookie:0x%llx\n"
+ , FUNC_ADPT_ARG(padapter), pcfg80211_wdinfo->remain_on_ch_cookie, roch_parm->cookie);
+ rtw_warn_on(1);
+ }
+ }
+
+#if defined(RTW_ROCH_BACK_OP) && defined(CONFIG_CONCURRENT_MODE)
+ _cancel_timer_ex(&pwdinfo->ap_p2p_switch_timer);
+#endif
if (rtw_mi_get_ch_setting_union(padapter, &ch, &bw, &offset) != 0) {
if (0)
@@ -3323,39 +3465,42 @@ static void ro_ch_handler(_adapter *padapter)
}
set_channel_bwmode(padapter, ch, offset, bw);
+ rtw_back_opch(padapter);
rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo));
#ifdef CONFIG_DEBUG_CFG80211
RTW_INFO("%s, role=%d, p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo));
#endif
- pcfg80211_wdinfo->is_ro_ch = _FALSE;
- pcfg80211_wdinfo->last_ro_ch_time = rtw_get_current_time();
+ wdev = pcfg80211_wdinfo->ro_ch_wdev;
+
+ rtw_cfg80211_set_is_roch(padapter, _FALSE);
+ pcfg80211_wdinfo->ro_ch_wdev = NULL;
+ rtw_cfg80211_set_last_ro_ch_time(padapter);
- RTW_INFO("cfg80211_remain_on_channel_expired cookie:0x%llx, ch=%d, bw=%d, offset=%d\n"
- , pcfg80211_wdinfo->remain_on_ch_cookie
- , rtw_get_oper_ch(padapter), rtw_get_oper_bw(padapter), rtw_get_oper_choffset(padapter));
+ rtw_cfg80211_remain_on_channel_expired(wdev
+ , pcfg80211_wdinfo->remain_on_ch_cookie
+ , &pcfg80211_wdinfo->remain_on_ch_channel
+ , pcfg80211_wdinfo->remain_on_ch_type, GFP_KERNEL);
- rtw_cfg80211_remain_on_channel_expired(padapter,
- pcfg80211_wdinfo->remain_on_ch_cookie,
- &pcfg80211_wdinfo->remain_on_ch_channel,
- pcfg80211_wdinfo->remain_on_ch_type, GFP_KERNEL);
+ RTW_INFO("cfg80211_remain_on_channel_expired cookie:0x%llx\n"
+ , pcfg80211_wdinfo->remain_on_ch_cookie);
- _func_exit_;
+#ifdef CONFIG_BT_COEXIST
+ rtw_btcoex_ScanNotify(padapter, _FALSE);
+#endif
+
+exit:
+ _exit_critical_mutex(&pwdev_priv->roch_mutex, NULL);
+
+ return ret;
}
static void ro_ch_timer_process(void *FunctionContext)
{
_adapter *adapter = (_adapter *)FunctionContext;
- struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter);
-
- /* printk("%s\n", __FUNCTION__); */
-
-#ifdef CONFIG_CONCURRENT_MODE
- ATOMIC_SET(&pwdev_priv->ro_ch_to, 1);
-#endif
- p2p_protocol_wk_cmd(adapter, P2P_RO_CH_WK);
+ p2p_cancel_roch_cmd(adapter, 0, NULL, 0);
}
static void rtw_change_p2pie_op_ch(_adapter *padapter, const u8 *frame_body, u32 len, u8 ch)
@@ -3363,6 +3508,11 @@ static void rtw_change_p2pie_op_ch(_adapter *padapter, const u8 *frame_body, u32
u8 *ies, *p2p_ie;
u32 ies_len, p2p_ielen;
+#ifdef CONFIG_MCC_MODE
+ if (MCC_EN(padapter))
+ return;
+#endif /* CONFIG_MCC_MODE */
+
ies = (u8 *)(frame_body + _PUBLIC_ACTION_IE_OFFSET_);
ies_len = len - _PUBLIC_ACTION_IE_OFFSET_;
@@ -3389,6 +3539,11 @@ static void rtw_change_p2pie_ch_list(_adapter *padapter, const u8 *frame_body, u
u8 *ies, *p2p_ie;
u32 ies_len, p2p_ielen;
+#ifdef CONFIG_MCC_MODE
+ if (MCC_EN(padapter))
+ return;
+#endif /* CONFIG_MCC_MODE */
+
ies = (u8 *)(frame_body + _PUBLIC_ACTION_IE_OFFSET_);
ies_len = len - _PUBLIC_ACTION_IE_OFFSET_;
@@ -3515,6 +3670,11 @@ static void rtw_cfg80211_adjust_p2pie_channel(_adapter *padapter, const u8 *fram
u32 ies_len, p2p_ielen;
u8 union_ch = rtw_mi_get_union_chan(padapter);
+#ifdef CONFIG_MCC_MODE
+ if (MCC_EN(padapter))
+ return;
+#endif /* CONFIG_MCC_MODE */
+
ies = (u8 *)(frame_body + _PUBLIC_ACTION_IE_OFFSET_);
ies_len = len - _PUBLIC_ACTION_IE_OFFSET_;
@@ -3536,8 +3696,14 @@ static void rtw_cfg80211_adjust_p2pie_channel(_adapter *padapter, const u8 *fram
while (attr_contentlen > 0) {
num_of_ch = *(pattr_temp + 1);
- for (i = 0; i < num_of_ch; i++)
- *(pattr_temp + 2 + i) = union_ch; /*forcing to the same channel*/
+ for (i = 0; i < num_of_ch; i++) {
+ if (*(pattr_temp + 2 + i) && *(pattr_temp + 2 + i) != union_ch) {
+ #ifdef RTW_SINGLE_WIPHY
+ RTW_ERR("replace ch_list:%u with:%u\n", *(pattr_temp + 2 + i), union_ch);
+ #endif
+ *(pattr_temp + 2 + i) = union_ch; /*forcing to the same channel*/
+ }
+ }
pattr_temp += (2 + num_of_ch);
attr_contentlen -= (2 + num_of_ch);
@@ -3549,7 +3715,12 @@ static void rtw_cfg80211_adjust_p2pie_channel(_adapter *padapter, const u8 *fram
pattr = NULL;
pattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, (uint *)&attr_contentlen);
if (pattr != NULL) {
- *(pattr + 4) = union_ch; /*forcing to the same channel */
+ if (*(pattr + 4) && *(pattr + 4) != union_ch) {
+ #ifdef RTW_SINGLE_WIPHY
+ RTW_ERR("replace op_ch:%u with:%u\n", *(pattr + 4), union_ch);
+ #endif
+ *(pattr + 4) = union_ch; /*forcing to the same channel */
+ }
}
/* Get the next P2P IE */
@@ -3792,6 +3963,8 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx)
int op_ch = -1;
int listen_ch = -1;
u8 intent = 0;
+ u8 *iaddr = NULL;
+ u8 *gbssid = NULL;
frame_body = (unsigned char *)(buf + sizeof(struct rtw_ieee80211_hdr_3addr));
category = frame_body[0];
@@ -3799,20 +3972,21 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx)
if (category == RTW_WLAN_CATEGORY_PUBLIC) {
action = frame_body[1];
if (action == ACT_PUBLIC_VENDOR
- && _rtw_memcmp(frame_body + 2, P2P_OUI, 4) == _TRUE
- ) {
+ && _rtw_memcmp(frame_body + 2, P2P_OUI, 4) == _TRUE
+ ) {
OUI_Subtype = frame_body[6];
dialogToken = frame_body[7];
is_p2p_frame = OUI_Subtype;
-#ifdef CONFIG_DEBUG_CFG80211
+
+ #ifdef CONFIG_DEBUG_CFG80211
RTW_INFO("ACTION_CATEGORY_PUBLIC: ACT_PUBLIC_VENDOR, OUI=0x%x, OUI_Subtype=%d, dialogToken=%d\n",
cpu_to_be32(*((u32 *)(frame_body + 2))), OUI_Subtype, dialogToken);
-#endif
+ #endif
p2p_ie = rtw_get_p2p_ie(
- (u8 *)buf + sizeof(struct rtw_ieee80211_hdr_3addr) + _PUBLIC_ACTION_IE_OFFSET_,
- len - sizeof(struct rtw_ieee80211_hdr_3addr) - _PUBLIC_ACTION_IE_OFFSET_,
- NULL, &p2p_ielen);
+ (u8 *)buf + sizeof(struct rtw_ieee80211_hdr_3addr) + _PUBLIC_ACTION_IE_OFFSET_
+ , len - sizeof(struct rtw_ieee80211_hdr_3addr) - _PUBLIC_ACTION_IE_OFFSET_
+ , NULL, &p2p_ielen);
switch (OUI_Subtype) { /* OUI Subtype */
u8 *cont;
@@ -3821,17 +3995,17 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx)
struct rtw_wdev_nego_info *nego_info = &pwdev_priv->nego_info;
if (tx) {
-#ifdef CONFIG_DRV_ISSUE_PROV_REQ /* IOT FOR S2 */
+ #ifdef CONFIG_DRV_ISSUE_PROV_REQ /* IOT FOR S2 */
if (pwdev_priv->provdisc_req_issued == _FALSE)
rtw_cfg80211_issue_p2p_provision_request(padapter, buf, len);
-#endif /* CONFIG_DRV_ISSUE_PROV_REQ */
+ #endif /* CONFIG_DRV_ISSUE_PROV_REQ */
/* pwdev_priv->provdisc_req_issued = _FALSE; */
-#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
+ #if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)
rtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr));
-#endif
+ #endif
}
cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len);
@@ -3843,11 +4017,16 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx)
cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GO_INTENT, NULL, &cont_len);
if (cont)
intent = *cont;
+ cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INTENDED_IF_ADDR, NULL, &cont_len);
+ if (cont && cont_len == 6)
+ iaddr = cont;
if (nego_info->token != dialogToken)
rtw_wdev_nego_info_init(nego_info);
- _rtw_memcpy(nego_info->peer_mac, tx ? GetAddr1Ptr(buf) : GetAddr2Ptr(buf), ETH_ALEN);
+ _rtw_memcpy(nego_info->peer_mac, tx ? GetAddr1Ptr(buf) : get_addr2_ptr(buf), ETH_ALEN);
+ if (iaddr)
+ _rtw_memcpy(tx ? nego_info->iface_addr : nego_info->peer_iface_addr, iaddr, ETH_ALEN);
nego_info->active = tx ? 1 : 0;
nego_info->token = dialogToken;
nego_info->req_op_ch = op_ch;
@@ -3856,19 +4035,21 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx)
nego_info->state = 0;
dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128);
- RTW_INFO("RTW_%s:P2P_GO_NEGO_REQ, dialogToken=%d, intent:%u%s, listen_ch:%d, op_ch:%d, ch_list:%s, full_ch_in_p2p_handshake:%d\n" ,
- (tx == _TRUE) ? "Tx" : "Rx" , dialogToken , (intent >> 1) , intent & 0x1 ? "+" : "-" , listen_ch , op_ch , ch_list_buf ,
- padapter->registrypriv.full_ch_in_p2p_handshake);
+ RTW_INFO("RTW_%s:P2P_GO_NEGO_REQ, dialogToken=%d, intent:%u%s, listen_ch:%d, op_ch:%d, ch_list:%s"
+ , (tx == _TRUE) ? "Tx" : "Rx" , dialogToken , (intent >> 1) , intent & 0x1 ? "+" : "-" , listen_ch , op_ch , ch_list_buf);
+ if (iaddr)
+ _RTW_INFO(", iaddr:"MAC_FMT, MAC_ARG(iaddr));
+ _RTW_INFO("\n");
if (!tx) {
-#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
+ #if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
if (rtw_mi_check_status(padapter, MI_LINKED)
&& rtw_chk_p2pie_ch_list_with_buddy(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE
&& padapter->registrypriv.full_ch_in_p2p_handshake == 0) {
RTW_INFO(FUNC_ADPT_FMT" ch_list has no intersect with buddy\n", FUNC_ADPT_ARG(padapter));
rtw_change_p2pie_ch_list(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr), 0);
}
-#endif
+ #endif
}
break;
@@ -3877,10 +4058,10 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx)
struct rtw_wdev_nego_info *nego_info = &pwdev_priv->nego_info;
if (tx) {
-#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
+ #if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)
rtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr));
-#endif
+ #endif
}
cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len);
@@ -3892,10 +4073,15 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx)
cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, NULL, &cont_len);
if (cont)
status = *cont;
+ cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INTENDED_IF_ADDR, NULL, &cont_len);
+ if (cont && cont_len == 6)
+ iaddr = cont;
if (nego_info->token == dialogToken && nego_info->state == 0
- && _rtw_memcmp(nego_info->peer_mac, tx ? GetAddr1Ptr(buf) : GetAddr2Ptr(buf), ETH_ALEN) == _TRUE
- ) {
+ && _rtw_memcmp(nego_info->peer_mac, tx ? GetAddr1Ptr(buf) : get_addr2_ptr(buf), ETH_ALEN) == _TRUE
+ ) {
+ if (iaddr)
+ _rtw_memcpy(tx ? nego_info->iface_addr : nego_info->peer_iface_addr, iaddr, ETH_ALEN);
nego_info->status = (status == -1) ? 0xff : status;
nego_info->rsp_op_ch = op_ch;
nego_info->rsp_intent = intent;
@@ -3905,19 +4091,22 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx)
}
dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128);
- RTW_INFO("RTW_%s:P2P_GO_NEGO_RESP, dialogToken=%d, intent:%u%s, status:%d, op_ch:%d, ch_list:%s\n",
- (tx == _TRUE) ? "Tx" : "Rx", dialogToken, (intent >> 1), intent & 0x1 ? "+" : "-", status, op_ch, ch_list_buf);
+ RTW_INFO("RTW_%s:P2P_GO_NEGO_RESP, dialogToken=%d, intent:%u%s, status:%d, op_ch:%d, ch_list:%s"
+ , (tx == _TRUE) ? "Tx" : "Rx", dialogToken, (intent >> 1), intent & 0x1 ? "+" : "-", status, op_ch, ch_list_buf);
+ if (iaddr)
+ _RTW_INFO(", iaddr:"MAC_FMT, MAC_ARG(iaddr));
+ _RTW_INFO("\n");
if (!tx) {
pwdev_priv->provdisc_req_issued = _FALSE;
-#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
+ #if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
if (rtw_mi_check_status(padapter, MI_LINKED)
&& rtw_chk_p2pie_ch_list_with_buddy(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE
&& padapter->registrypriv.full_ch_in_p2p_handshake == 0) {
RTW_INFO(FUNC_ADPT_FMT" ch_list has no intersect with buddy\n", FUNC_ADPT_ARG(padapter));
rtw_change_p2pie_ch_list(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr), 0);
}
-#endif
+ #endif
}
break;
@@ -3927,10 +4116,10 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx)
bool is_go = _FALSE;
if (tx) {
-#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
+ #if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)
rtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr));
-#endif
+ #endif
}
cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len);
@@ -3941,7 +4130,7 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx)
status = *cont;
if (nego_info->token == dialogToken && nego_info->state == 1
- && _rtw_memcmp(nego_info->peer_mac, tx ? GetAddr1Ptr(buf) : GetAddr2Ptr(buf), ETH_ALEN) == _TRUE
+ && _rtw_memcmp(nego_info->peer_mac, tx ? GetAddr1Ptr(buf) : get_addr2_ptr(buf), ETH_ALEN) == _TRUE
) {
nego_info->status = (status == -1) ? 0xff : status;
nego_info->conf_op_ch = (op_ch == -1) ? 0 : op_ch;
@@ -3956,8 +4145,8 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx)
}
dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128);
- RTW_INFO("RTW_%s:P2P_GO_NEGO_CONF, dialogToken=%d, status:%d, op_ch:%d, ch_list:%s\n",
- (tx == _TRUE) ? "Tx" : "Rx", dialogToken, status, op_ch, ch_list_buf);
+ RTW_INFO("RTW_%s:P2P_GO_NEGO_CONF, dialogToken=%d, status:%d, op_ch:%d, ch_list:%s\n"
+ , (tx == _TRUE) ? "Tx" : "Rx", dialogToken, status, op_ch, ch_list_buf);
if (!tx) {
}
@@ -3969,11 +4158,11 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx)
int flags = -1;
if (tx) {
-#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
+ #if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
if (rtw_mi_check_status(padapter, MI_LINKED)
&& padapter->registrypriv.full_ch_in_p2p_handshake == 0)
rtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr));
-#endif
+ #endif
}
cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INVITATION_FLAGS, NULL, &cont_len);
@@ -3982,11 +4171,16 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx)
cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len);
if (cont)
op_ch = *(cont + 4);
+ cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_BSSID, NULL, &cont_len);
+ if (cont && cont_len == 6)
+ gbssid = cont;
if (invit_info->token != dialogToken)
rtw_wdev_invit_info_init(invit_info);
- _rtw_memcpy(invit_info->peer_mac, tx ? GetAddr1Ptr(buf) : GetAddr2Ptr(buf), ETH_ALEN);
+ _rtw_memcpy(invit_info->peer_mac, tx ? GetAddr1Ptr(buf) : get_addr2_ptr(buf), ETH_ALEN);
+ if (gbssid)
+ _rtw_memcpy(invit_info->group_bssid, gbssid, ETH_ALEN);
invit_info->active = tx ? 1 : 0;
invit_info->token = dialogToken;
invit_info->flags = (flags == -1) ? 0x0 : flags;
@@ -3994,21 +4188,27 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx)
invit_info->state = 0;
dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128);
- RTW_INFO("RTW_%s:P2P_INVIT_REQ, dialogToken=%d, flags:0x%02x, op_ch:%d, ch_list:%s\n",
- (tx == _TRUE) ? "Tx" : "Rx", dialogToken, flags, op_ch, ch_list_buf);
+ RTW_INFO("RTW_%s:P2P_INVIT_REQ, dialogToken=%d, flags:0x%02x, op_ch:%d, ch_list:%s"
+ , (tx == _TRUE) ? "Tx" : "Rx", dialogToken, flags, op_ch, ch_list_buf);
+ if (gbssid)
+ _RTW_INFO(", gbssid:"MAC_FMT, MAC_ARG(gbssid));
+ _RTW_INFO("\n");
if (!tx) {
-#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
+ #if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) {
+ #if defined(CONFIG_P2P_INVITE_IOT)
if (op_ch != -1 && rtw_chk_p2pie_op_ch_with_buddy(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE) {
RTW_INFO(FUNC_ADPT_FMT" op_ch:%u has no intersect with buddy\n", FUNC_ADPT_ARG(padapter), op_ch);
rtw_change_p2pie_ch_list(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr), 0);
- } else if (rtw_chk_p2pie_ch_list_with_buddy(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE) {
+ } else
+ #endif
+ if (rtw_chk_p2pie_ch_list_with_buddy(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE) {
RTW_INFO(FUNC_ADPT_FMT" ch_list has no intersect with buddy\n", FUNC_ADPT_ARG(padapter));
rtw_change_p2pie_ch_list(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr), 0);
}
}
-#endif
+ #endif
}
break;
@@ -4017,28 +4217,31 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx)
struct rtw_wdev_invit_info *invit_info = &pwdev_priv->invit_info;
if (tx) {
-#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
+ #if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT)
if (rtw_mi_check_status(padapter, MI_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0)
rtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len - sizeof(struct rtw_ieee80211_hdr_3addr));
-#endif
+ #endif
}
cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, NULL, &cont_len);
if (cont) {
-#ifdef CONFIG_P2P_INVITE_IOT
+ #ifdef CONFIG_P2P_INVITE_IOT
if (tx && *cont == 7) {
RTW_INFO("TX_P2P_INVITE_RESP, status is no common channel, change to unknown group\n");
*cont = 8; /* unknow group status */
}
-#endif /* CONFIG_P2P_INVITE_IOT */
+ #endif /* CONFIG_P2P_INVITE_IOT */
status = *cont;
}
cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len);
if (cont)
op_ch = *(cont + 4);
+ cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_BSSID, NULL, &cont_len);
+ if (cont && cont_len == 6)
+ gbssid = cont;
if (invit_info->token == dialogToken && invit_info->state == 0
- && _rtw_memcmp(invit_info->peer_mac, tx ? GetAddr1Ptr(buf) : GetAddr2Ptr(buf), ETH_ALEN) == _TRUE
+ && _rtw_memcmp(invit_info->peer_mac, tx ? GetAddr1Ptr(buf) : get_addr2_ptr(buf), ETH_ALEN) == _TRUE
) {
invit_info->status = (status == -1) ? 0xff : status;
invit_info->rsp_op_ch = op_ch;
@@ -4047,8 +4250,11 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx)
}
dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128);
- RTW_INFO("RTW_%s:P2P_INVIT_RESP, dialogToken=%d, status:%d, op_ch:%d, ch_list:%s\n",
- (tx == _TRUE) ? "Tx" : "Rx", dialogToken, status, op_ch, ch_list_buf);
+ RTW_INFO("RTW_%s:P2P_INVIT_RESP, dialogToken=%d, status:%d, op_ch:%d, ch_list:%s"
+ , (tx == _TRUE) ? "Tx" : "Rx", dialogToken, status, op_ch, ch_list_buf);
+ if (gbssid)
+ _RTW_INFO(", gbssid:"MAC_FMT, MAC_ARG(gbssid));
+ _RTW_INFO("\n");
if (!tx) {
}
@@ -4080,9 +4286,9 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx)
if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, NULL, &contentlen)) {
pwdev_priv->provdisc_req_issued = _FALSE;/* case: p2p_client join p2p GO */
} else {
-#ifdef CONFIG_DEBUG_CFG80211
+ #ifdef CONFIG_DEBUG_CFG80211
RTW_INFO("provdisc_req_issued is _TRUE\n");
-#endif /*CONFIG_DEBUG_CFG80211*/
+ #endif /*CONFIG_DEBUG_CFG80211*/
pwdev_priv->provdisc_req_issued = _TRUE;/* case: p2p_devices connection before Nego req. */
}
@@ -4104,33 +4310,32 @@ int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx)
OUI_Subtype = frame_body[5];
dialogToken = frame_body[6];
-#ifdef CONFIG_DEBUG_CFG80211
+ #ifdef CONFIG_DEBUG_CFG80211
RTW_INFO("ACTION_CATEGORY_P2P: OUI=0x%x, OUI_Subtype=%d, dialogToken=%d\n",
cpu_to_be32(*((u32 *)(frame_body + 1))), OUI_Subtype, dialogToken);
-#endif
+ #endif
is_p2p_frame = OUI_Subtype;
switch (OUI_Subtype) {
case P2P_NOTICE_OF_ABSENCE:
- RTW_INFO("RTW_%s:P2P_NOTICE_OF_ABSENCE, dialogToken=%d\n", (tx == _TRUE) ? "TX" : "RX", dialogToken);
+ RTW_INFO("RTW_%s:P2P_NOTICE_OF_ABSENCE, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", dialogToken);
break;
case P2P_PRESENCE_REQUEST:
- RTW_INFO("RTW_%s:P2P_PRESENCE_REQUEST, dialogToken=%d\n", (tx == _TRUE) ? "TX" : "RX", dialogToken);
+ RTW_INFO("RTW_%s:P2P_PRESENCE_REQUEST, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", dialogToken);
break;
case P2P_PRESENCE_RESPONSE:
- RTW_INFO("RTW_%s:P2P_PRESENCE_RESPONSE, dialogToken=%d\n", (tx == _TRUE) ? "TX" : "RX", dialogToken);
+ RTW_INFO("RTW_%s:P2P_PRESENCE_RESPONSE, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", dialogToken);
break;
case P2P_GO_DISC_REQUEST:
- RTW_INFO("RTW_%s:P2P_GO_DISC_REQUEST, dialogToken=%d\n", (tx == _TRUE) ? "TX" : "RX", dialogToken);
+ RTW_INFO("RTW_%s:P2P_GO_DISC_REQUEST, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", dialogToken);
break;
default:
- RTW_INFO("RTW_%s:OUI_Subtype=%d, dialogToken=%d\n", (tx == _TRUE) ? "TX" : "RX", OUI_Subtype, dialogToken);
+ RTW_INFO("RTW_%s:OUI_Subtype=%d, dialogToken=%d\n", (tx == _TRUE) ? "Tx" : "Rx", OUI_Subtype, dialogToken);
break;
}
- } else
- RTW_INFO("RTW_%s:action frame category=%d\n", (tx == _TRUE) ? "TX" : "RX", category);
+ }
return is_p2p_frame;
}
@@ -4141,26 +4346,25 @@ void rtw_init_cfg80211_wifidirect_info(_adapter *padapter)
_rtw_memset(pcfg80211_wdinfo, 0x00, sizeof(struct cfg80211_wifidirect_info));
- _init_timer(&pcfg80211_wdinfo->remain_on_ch_timer, padapter->pnetdev, ro_ch_timer_process, padapter);
+ rtw_init_timer(&pcfg80211_wdinfo->remain_on_ch_timer, padapter, ro_ch_timer_process, padapter);
}
#endif /* CONFIG_IOCTL_CFG80211 */
-void p2p_protocol_wk_hdl(_adapter *padapter, int intCmdType)
+s32 p2p_protocol_wk_hdl(_adapter *padapter, int intCmdType, u8 *buf)
{
+ int ret = H2C_SUCCESS;
struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
- _func_enter_;
-
switch (intCmdType) {
- case P2P_FIND_PHASE_WK: {
+ case P2P_FIND_PHASE_WK:
find_phase_handler(padapter);
break;
- }
- case P2P_RESTORE_STATE_WK: {
+
+ case P2P_RESTORE_STATE_WK:
restore_p2p_state_handler(padapter);
break;
- }
- case P2P_PRE_TX_PROVDISC_PROCESS_WK: {
+
+ case P2P_PRE_TX_PROVDISC_PROCESS_WK:
#ifdef CONFIG_CONCURRENT_MODE
if (rtw_mi_check_status(padapter, MI_LINKED))
p2p_concurrent_handler(padapter);
@@ -4170,8 +4374,8 @@ void p2p_protocol_wk_hdl(_adapter *padapter, int intCmdType)
pre_tx_provdisc_handler(padapter);
#endif
break;
- }
- case P2P_PRE_TX_INVITEREQ_PROCESS_WK: {
+
+ case P2P_PRE_TX_INVITEREQ_PROCESS_WK:
#ifdef CONFIG_CONCURRENT_MODE
if (rtw_mi_check_status(padapter, MI_LINKED))
p2p_concurrent_handler(padapter);
@@ -4181,8 +4385,8 @@ void p2p_protocol_wk_hdl(_adapter *padapter, int intCmdType)
pre_tx_invitereq_handler(padapter);
#endif
break;
- }
- case P2P_PRE_TX_NEGOREQ_PROCESS_WK: {
+
+ case P2P_PRE_TX_NEGOREQ_PROCESS_WK:
#ifdef CONFIG_CONCURRENT_MODE
if (rtw_mi_check_status(padapter, MI_LINKED))
p2p_concurrent_handler(padapter);
@@ -4192,25 +4396,28 @@ void p2p_protocol_wk_hdl(_adapter *padapter, int intCmdType)
pre_tx_negoreq_handler(padapter);
#endif
break;
- }
-#ifdef CONFIG_P2P
+
#ifdef CONFIG_CONCURRENT_MODE
- case P2P_AP_P2P_CH_SWITCH_PROCESS_WK: {
+ case P2P_AP_P2P_CH_SWITCH_PROCESS_WK:
p2p_concurrent_handler(padapter);
break;
- }
-#endif
#endif
+
#ifdef CONFIG_IOCTL_CFG80211
- case P2P_RO_CH_WK: {
- ro_ch_handler(padapter);
+ case P2P_RO_CH_WK:
+ ret = ro_ch_handler(padapter, buf);
break;
- }
-#endif /* CONFIG_IOCTL_CFG80211 */
+ case P2P_CANCEL_RO_CH_WK:
+ ret = cancel_ro_ch_handler(padapter, buf);
+ break;
+#endif
+ default:
+ rtw_warn_on(1);
+ break;
}
- _func_exit_;
+ return ret;
}
int process_p2p_cross_connect_ie(PADAPTER padapter, u8 *IEs, u32 IELength)
@@ -4225,7 +4432,6 @@ int process_p2p_cross_connect_ie(PADAPTER padapter, u8 *IEs, u32 IELength)
struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
- _func_enter_;
if (IELength <= _BEACON_IE_OFFSET_)
return ret;
@@ -4246,7 +4452,6 @@ int process_p2p_cross_connect_ie(PADAPTER padapter, u8 *IEs, u32 IELength)
p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen);
}
- _func_exit_;
return ret;
}
@@ -4264,13 +4469,14 @@ void process_p2p_ps_ie(PADAPTER padapter, u8 *IEs, u32 IELength)
u8 find_p2p = _FALSE, find_p2p_ps = _FALSE;
u8 noa_offset, noa_num, noa_index;
- _func_enter_;
if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE))
return;
#ifdef CONFIG_CONCURRENT_MODE
+#ifndef CONFIG_FW_MULTI_PORT_SUPPORT
if (padapter->hw_port != HW_PORT0)
return;
+#endif
#endif
if (IELength <= _BEACON_IE_OFFSET_)
return;
@@ -4341,15 +4547,14 @@ void process_p2p_ps_ie(PADAPTER padapter, u8 *IEs, u32 IELength)
p2p_ps_wk_cmd(padapter, P2P_PS_DISABLE, 1);
}
- _func_exit_;
}
void p2p_ps_wk_hdl(_adapter *padapter, u8 p2p_ps_state)
{
struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
-
- _func_enter_;
+ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+ u32 ps_deny = 0;
/* Pre action for p2p state */
switch (p2p_ps_state) {
@@ -4371,6 +4576,16 @@ void p2p_ps_wk_hdl(_adapter *padapter, u8 p2p_ps_state)
}
break;
case P2P_PS_ENABLE:
+ _enter_pwrlock(&adapter_to_pwrctl(padapter)->lock);
+ ps_deny = rtw_ps_deny_get(padapter);
+ _exit_pwrlock(&adapter_to_pwrctl(padapter)->lock);
+
+ if ((ps_deny & (PS_DENY_SCAN | PS_DENY_JOIN))
+ || rtw_mi_check_fwstate(padapter, (_FW_UNDER_SURVEY | _FW_UNDER_LINKING))) {
+ pwdinfo->p2p_ps_mode = P2P_PS_NONE;
+ RTW_DBG(FUNC_ADPT_FMT" Block P2P PS under site survey or LINKING\n", FUNC_ADPT_ARG(padapter));
+ return;
+ }
if (pwdinfo->p2p_ps_mode > P2P_PS_NONE) {
#ifdef CONFIG_MCC_MODE
if (MCC_EN(padapter)) {
@@ -4405,7 +4620,9 @@ void p2p_ps_wk_hdl(_adapter *padapter, u8 p2p_ps_state)
break;
}
- _func_exit_;
+#ifdef CONFIG_MCC_MODE
+ rtw_hal_mcc_process_noa(padapter);
+#endif /* CONFIG_MCC_MODE */
}
u8 p2p_ps_wk_cmd(_adapter *padapter, u8 p2p_ps_state, u8 enqueue)
@@ -4416,11 +4633,12 @@ u8 p2p_ps_wk_cmd(_adapter *padapter, u8 p2p_ps_state, u8 enqueue)
struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
u8 res = _SUCCESS;
- _func_enter_;
if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)
#ifdef CONFIG_CONCURRENT_MODE
+#ifndef CONFIG_FW_MULTI_PORT_SUPPORT
|| (padapter->hw_port != HW_PORT0)
+#endif
#endif
)
return res;
@@ -4452,7 +4670,6 @@ u8 p2p_ps_wk_cmd(_adapter *padapter, u8 p2p_ps_state, u8 enqueue)
exit:
- _func_exit_;
return res;
@@ -4799,13 +5016,13 @@ void rtw_init_wifidirect_timers(_adapter *padapter)
{
struct wifidirect_info *pwdinfo = &padapter->wdinfo;
- _init_timer(&pwdinfo->find_phase_timer, padapter->pnetdev, find_phase_timer_process, padapter);
- _init_timer(&pwdinfo->restore_p2p_state_timer, padapter->pnetdev, restore_p2p_state_timer_process, padapter);
- _init_timer(&pwdinfo->pre_tx_scan_timer, padapter->pnetdev, pre_tx_scan_timer_process, padapter);
- _init_timer(&pwdinfo->reset_ch_sitesurvey, padapter->pnetdev, reset_ch_sitesurvey_timer_process, padapter);
- _init_timer(&pwdinfo->reset_ch_sitesurvey2, padapter->pnetdev, reset_ch_sitesurvey_timer_process2, padapter);
+ rtw_init_timer(&pwdinfo->find_phase_timer, padapter, find_phase_timer_process, padapter);
+ rtw_init_timer(&pwdinfo->restore_p2p_state_timer, padapter, restore_p2p_state_timer_process, padapter);
+ rtw_init_timer(&pwdinfo->pre_tx_scan_timer, padapter, pre_tx_scan_timer_process, padapter);
+ rtw_init_timer(&pwdinfo->reset_ch_sitesurvey, padapter, reset_ch_sitesurvey_timer_process, padapter);
+ rtw_init_timer(&pwdinfo->reset_ch_sitesurvey2, padapter, reset_ch_sitesurvey_timer_process2, padapter);
#ifdef CONFIG_CONCURRENT_MODE
- _init_timer(&pwdinfo->ap_p2p_switch_timer, padapter->pnetdev, ap_p2p_switch_timer_process, padapter);
+ rtw_init_timer(&pwdinfo->ap_p2p_switch_timer, padapter, ap_p2p_switch_timer_process, padapter);
#endif
}
@@ -4839,21 +5056,25 @@ void init_wifidirect_info(_adapter *padapter, enum P2P_ROLE role)
pwdinfo->social_chan[2] = 11;
pwdinfo->social_chan[3] = 0; /* channel 0 for scanning ending in site survey function. */
-#ifdef CONFIG_CONCURRENT_MODE
- if (rtw_mi_check_status(padapter, MI_LINKED))
- union_ch = rtw_mi_get_union_chan(padapter);
-
- if ((union_ch != 0) &&
- ((union_ch == 1) || (union_ch == 6) || (union_ch == 11))
- ) {
- /* Use the AP's channel as the listen channel */
- /* This will avoid the channel switch between AP's channel and listen channel. */
- pwdinfo->listen_channel = union_ch;
- } else
-#endif /* CONFIG_CONCURRENT_MODE */
- {
- /* Use the channel 11 as the listen channel */
- pwdinfo->listen_channel = 11;
+ if (role != P2P_ROLE_DISABLE
+ && pwdinfo->driver_interface != DRIVER_CFG80211
+ ) {
+ #ifdef CONFIG_CONCURRENT_MODE
+ if (rtw_mi_check_status(padapter, MI_LINKED))
+ union_ch = rtw_mi_get_union_chan(padapter);
+
+ if (union_ch != 0 &&
+ (union_ch == 1 || union_ch == 6 || union_ch == 11)
+ ) {
+ /* Use the AP's channel as the listen channel */
+ /* This will avoid the channel switch between AP's channel and listen channel */
+ pwdinfo->listen_channel = union_ch;
+ } else
+ #endif /* CONFIG_CONCURRENT_MODE */
+ {
+ /* Use the channel 11 as the listen channel */
+ pwdinfo->listen_channel = 11;
+ }
}
if (role == P2P_ROLE_DEVICE) {
@@ -5125,7 +5346,7 @@ int rtw_p2p_enable(_adapter *padapter, enum P2P_ROLE role)
u8 channel, ch_offset;
u16 bwmode;
-#ifdef CONFIG_CONCURRENT_MODE
+#if defined(CONFIG_CONCURRENT_MODE) && (!defined(RTW_P2P_GROUP_INTERFACE) || !RTW_P2P_GROUP_INTERFACE)
/* Commented by Albert 2011/12/30 */
/* The driver just supports 1 P2P group operation. */
/* So, this function will do nothing if the buddy adapter had enabled the P2P function. */
@@ -5145,11 +5366,19 @@ int rtw_p2p_enable(_adapter *padapter, enum P2P_ROLE role)
/* Added by Albert 2011/03/22 */
/* In the P2P mode, the driver should not support the b mode. */
/* So, the Tx packet shouldn't use the CCK rate */
- update_tx_basic_rate(padapter, WIRELESS_11AGN);
+ #ifdef CONFIG_IOCTL_CFG80211
+ if (rtw_cfg80211_iface_has_p2p_group_cap(padapter))
+ #endif
+ update_tx_basic_rate(padapter, WIRELESS_11AGN);
/* Enable P2P function */
init_wifidirect_info(padapter, role);
+ #ifdef CONFIG_IOCTL_CFG80211
+ if (padapter->wdinfo.driver_interface == DRIVER_CFG80211)
+ adapter_wdev_data(padapter)->p2p_enabled = _TRUE;
+ #endif
+
rtw_hal_set_odm_var(padapter, HAL_ODM_P2P_STATE, NULL, _TRUE);
#ifdef CONFIG_WFD
if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
@@ -5162,11 +5391,12 @@ int rtw_p2p_enable(_adapter *padapter, enum P2P_ROLE role)
return ret;
#endif /* CONFIG_INTEL_WIDI */
-#ifdef CONFIG_IOCTL_CFG80211
+ #ifdef CONFIG_IOCTL_CFG80211
if (padapter->wdinfo.driver_interface == DRIVER_CFG80211)
adapter_wdev_data(padapter)->p2p_enabled = _FALSE;
-#endif /* CONFIG_IOCTL_CFG80211 */
+ #endif
+ pwdinfo->listen_channel = 0;
/* Disable P2P function */
if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) {
diff --git a/core/rtw_pwrctrl.c b/core/rtw_pwrctrl.c
index 2f3a8ad..671fba4 100644
--- a/core/rtw_pwrctrl.c
+++ b/core/rtw_pwrctrl.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,12 +11,7 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#define _RTW_PWRCTRL_C_
#include
@@ -90,6 +85,10 @@ void _ips_enter(_adapter *padapter)
if (pwrpriv->ips_mode == IPS_LEVEL_2)
pwrpriv->bkeepfwalive = _TRUE;
+#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS
+ pwrpriv->pwr_saving_start_time = rtw_get_current_time();
+#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */
+
rtw_ips_pwr_down(padapter);
pwrpriv->rf_pwrstate = rf_off;
}
@@ -125,6 +124,11 @@ int _ips_leave(_adapter *padapter)
result = rtw_ips_pwr_up(padapter);
if (result == _SUCCESS)
pwrpriv->rf_pwrstate = rf_on;
+
+#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS
+ pwrpriv->pwr_saving_time += rtw_get_passing_time_ms(pwrpriv->pwr_saving_start_time);
+#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */
+
RTW_PRINT("nolinked power save leave\n");
RTW_INFO("==> ips_leave.....LED(0x%08x)...\n", rtw_read32(padapter, 0x4c));
@@ -158,7 +162,7 @@ int ips_leave(_adapter *padapter)
_exit_pwrlock(&pwrpriv->lock);
if (_SUCCESS == ret)
- ODM_DMReset(&GET_HAL_DATA(padapter)->odmpriv);
+ odm_dm_reset(&GET_HAL_DATA(padapter)->odmpriv);
#ifdef CONFIG_BT_COEXIST
if (_SUCCESS == ret)
@@ -188,9 +192,6 @@ bool rtw_pwr_unassociated_idle(_adapter *adapter)
struct mlme_priv *pmlmepriv;
#ifdef CONFIG_P2P
struct wifidirect_info *pwdinfo;
-#ifdef CONFIG_IOCTL_CFG80211
- struct cfg80211_wifidirect_info *pcfg80211_wdinfo;
-#endif
#endif
bool ret = _FALSE;
@@ -200,7 +201,7 @@ bool rtw_pwr_unassociated_idle(_adapter *adapter)
goto exit;
}
- if (adapter_to_pwrctl(adapter)->ips_deny_time >= rtw_get_current_time()) {
+ if (rtw_time_after(adapter_to_pwrctl(adapter)->ips_deny_time, rtw_get_current_time())) {
/* RTW_INFO("%s ips_deny_time\n", __func__); */
goto exit;
}
@@ -211,24 +212,21 @@ bool rtw_pwr_unassociated_idle(_adapter *adapter)
pmlmepriv = &(iface->mlmepriv);
#ifdef CONFIG_P2P
pwdinfo = &(iface->wdinfo);
-#ifdef CONFIG_IOCTL_CFG80211
- pcfg80211_wdinfo = &iface->cfg80211_wdinfo;
-#endif
#endif
if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE | WIFI_SITE_MONITOR)
- || check_fwstate(pmlmepriv, WIFI_UNDER_LINKING | WIFI_UNDER_WPS)
- || check_fwstate(pmlmepriv, WIFI_AP_STATE)
- || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE)
-#if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211)
- || pcfg80211_wdinfo->is_ro_ch
-#elif defined(CONFIG_P2P)
- || rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)
- || rtw_p2p_chk_state(pwdinfo, P2P_STATE_LISTEN)
-#endif
-#if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211)
- || rtw_get_passing_time_ms(pcfg80211_wdinfo->last_ro_ch_time) < 3000
-#endif
- )
+ || check_fwstate(pmlmepriv, WIFI_UNDER_LINKING | WIFI_UNDER_WPS)
+ || MLME_IS_AP(iface)
+ || MLME_IS_MESH(iface)
+ || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE)
+ #if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211)
+ || rtw_cfg80211_get_is_roch(iface) == _TRUE
+ || (rtw_cfg80211_is_ro_ch_once(adapter)
+ && rtw_cfg80211_get_last_ro_ch_passing_ms(adapter) < 3000)
+ #elif defined(CONFIG_P2P)
+ || rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)
+ || rtw_p2p_chk_state(pwdinfo, P2P_STATE_LISTEN)
+ #endif
+ )
goto exit;
}
@@ -393,10 +391,9 @@ void rtw_ps_processor(_adapter *padapter)
return;
}
-void pwr_state_check_handler(RTW_TIMER_HDL_ARGS);
-void pwr_state_check_handler(RTW_TIMER_HDL_ARGS)
+void pwr_state_check_handler(void *ctx)
{
- _adapter *padapter = (_adapter *)FunctionContext;
+ _adapter *padapter = (_adapter *)ctx;
rtw_ps_cmd(padapter);
}
@@ -404,7 +401,7 @@ void pwr_state_check_handler(RTW_TIMER_HDL_ARGS)
void traffic_check_for_leave_lps(PADAPTER padapter, u8 tx, u32 tx_packets)
{
#ifdef CONFIG_CHECK_LEAVE_LPS
- static u32 start_time = 0;
+ static systime start_time = 0;
static u32 xmit_cnt = 0;
u8 bLeaveLPS = _FALSE;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
@@ -456,6 +453,61 @@ void traffic_check_for_leave_lps(PADAPTER padapter, u8 tx, u32 tx_packets)
#endif /* CONFIG_CHECK_LEAVE_LPS */
}
+#ifdef CONFIG_LPS_LCLK
+u8 rtw_cpwm_polling(_adapter *adapter, u8 cpwm_orig)
+{
+ u8 result = _FAIL;
+ u8 cpwm_now;
+ u8 poll_cnt = 0;
+ systime start_time;
+ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
+ struct debug_priv *pdbgpriv = &(adapter_to_dvobj(adapter)->drv_dbg);
+
+ /*RTW_INFO("%s.....\n", __func__);*/
+
+ start_time = rtw_get_current_time();
+
+ /* polling cpwm */
+ do {
+ rtw_msleep_os(1);
+ poll_cnt++;
+ cpwm_now = 0;
+ rtw_hal_get_hwreg(adapter, HW_VAR_CPWM, &cpwm_now);
+
+ if ((cpwm_orig ^ cpwm_now) & 0x80) {
+ pwrpriv->cpwm = PS_STATE_S4;
+ pwrpriv->cpwm_tog = cpwm_now & PS_TOGGLE;
+ #ifdef DBG_CHECK_FW_PS_STATE
+ RTW_INFO("%s: polling cpwm OK! poll_cnt=%d, cpwm_orig=%02x, cpwm_now=%02x , 0x100=0x%x\n"
+ , __func__, poll_cnt, cpwm_orig, cpwm_now, rtw_read8(adapter, REG_CR));
+ if (rtw_fw_ps_state(adapter) == _FAIL) {
+ RTW_INFO("leave 32k but fw state in 32k\n");
+ pdbgpriv->dbg_rpwm_toogle_cnt++;
+ }
+ #endif /* DBG_CHECK_FW_PS_STATE */
+ result = _SUCCESS;
+ break;
+ }
+
+ if (rtw_get_passing_time_ms(start_time) > LPS_RPWM_WAIT_MS) {
+ RTW_ERR("%s: polling cpwm timeout! poll_cnt=%d, cpwm_orig=%02x, cpwm_now=%02x\n"
+ , __func__, poll_cnt, cpwm_orig, cpwm_now);
+ #ifdef DBG_CHECK_FW_PS_STATE
+ if (rtw_fw_ps_state(adapter) == _FAIL) {
+ RTW_INFO("rpwm timeout and fw ps state in 32k\n");
+ pdbgpriv->dbg_rpwm_timeout_fail_cnt++;
+ }
+ #endif /* DBG_CHECK_FW_PS_STATE */
+
+ #ifdef CONFIG_LPS_RPWM_TIMER
+ _set_timer(&pwrpriv->pwr_rpwm_timer, 1);
+ #endif /* CONFIG_LPS_RPWM_TIMER */
+ break;
+ }
+ } while (1);
+ return result;
+}
+#endif
/*
* Description:
* This function MUST be called under power lock protect
@@ -469,12 +521,11 @@ void rtw_set_rpwm(PADAPTER padapter, u8 pslv)
{
u8 rpwm;
struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
-#ifdef CONFIG_DETECT_CPWM_BY_POLLING
+#ifdef CONFIG_LPS_LCLK
u8 cpwm_orig;
-#endif /* CONFIG_DETECT_CPWM_BY_POLLING */
+#endif
struct dvobj_priv *psdpriv = padapter->dvobj;
struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
- _func_enter_;
pslv = PS_STATE(pslv);
@@ -488,36 +539,23 @@ void rtw_set_rpwm(PADAPTER padapter, u8 pslv)
#ifdef CONFIG_LPS_LCLK
|| ((pwrpriv->rpwm >= PS_STATE_S2) && (pslv >= PS_STATE_S2))
#endif
+ || (pwrpriv->lps_level == LPS_NORMAL)
) {
- RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_err_,
- ("%s: Already set rpwm[0x%02X], new=0x%02X!\n", __FUNCTION__, pwrpriv->rpwm, pslv));
return;
}
}
if (rtw_is_surprise_removed(padapter) ||
(!rtw_is_hw_init_completed(padapter))) {
- RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_err_,
- ("%s: SurpriseRemoved(%s) hw_init_completed(%s)\n"
- , __func__
- , rtw_is_surprise_removed(padapter) ? "True" : "False"
- , rtw_is_hw_init_completed(padapter) ? "True" : "False"));
pwrpriv->cpwm = PS_STATE_S4;
return;
}
- if (rtw_is_drv_stopped(padapter)) {
- RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_err_,
- ("%s: change power state(0x%02X) when DriverStopped\n", __FUNCTION__, pslv));
-
- if (pslv < PS_STATE_S2) {
- RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_err_,
- ("%s: Reject to enter PS_STATE(0x%02X) lower than S2 when DriverStopped!!\n", __FUNCTION__, pslv));
+ if (rtw_is_drv_stopped(padapter))
+ if (pslv < PS_STATE_S2)
return;
- }
- }
rpwm = pslv | pwrpriv->tog;
#ifdef CONFIG_LPS_LCLK
@@ -525,12 +563,10 @@ void rtw_set_rpwm(PADAPTER padapter, u8 pslv)
if ((pwrpriv->cpwm < PS_STATE_S2) && (pslv >= PS_STATE_S2))
rpwm |= PS_ACK;
#endif
- RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_,
- ("rtw_set_rpwm: rpwm=0x%02x cpwm=0x%02x\n", rpwm, pwrpriv->cpwm));
pwrpriv->rpwm = pslv;
-#ifdef CONFIG_DETECT_CPWM_BY_POLLING
+#ifdef CONFIG_LPS_LCLK
cpwm_orig = 0;
if (rpwm & PS_ACK)
rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_orig);
@@ -548,59 +584,26 @@ void rtw_set_rpwm(PADAPTER padapter, u8 pslv)
/* No LPS 32K, No Ack */
if (rpwm & PS_ACK) {
#ifdef CONFIG_DETECT_CPWM_BY_POLLING
- u32 start_time;
- u8 cpwm_now;
- u8 poll_cnt = 0;
-
- start_time = rtw_get_current_time();
-
- /* polling cpwm */
- do {
- rtw_msleep_os(1);
- poll_cnt++;
- cpwm_now = 0;
- rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_now);
- if ((cpwm_orig ^ cpwm_now) & 0x80) {
- pwrpriv->cpwm = PS_STATE_S4;
- pwrpriv->cpwm_tog = cpwm_now & PS_TOGGLE;
-#ifdef DBG_CHECK_FW_PS_STATE
- RTW_INFO("%s: polling cpwm OK! poll_cnt=%d, cpwm_orig=%02x, cpwm_now=%02x , 0x100=0x%x\n"
- , __FUNCTION__, poll_cnt, cpwm_orig, cpwm_now, rtw_read8(padapter, REG_CR));
- if (rtw_fw_ps_state(padapter) == _FAIL) {
- RTW_INFO("leave 32k but fw state in 32k\n");
- pdbgpriv->dbg_rpwm_toogle_cnt++;
- }
-#endif /* DBG_CHECK_FW_PS_STATE */
- break;
- }
-
- if (rtw_get_passing_time_ms(start_time) > LPS_RPWM_WAIT_MS) {
- RTW_INFO("%s: polling cpwm timeout! poll_cnt=%d, cpwm_orig=%02x, cpwm_now=%02x\n", __FUNCTION__, poll_cnt, cpwm_orig, cpwm_now);
-#ifdef DBG_CHECK_FW_PS_STATE
- if (rtw_fw_ps_state(padapter) == _FAIL) {
- RTW_INFO("rpwm timeout and fw ps state in 32k\n");
- pdbgpriv->dbg_rpwm_timeout_fail_cnt++;
- }
-#endif /* DBG_CHECK_FW_PS_STATE */
-#ifdef CONFIG_LPS_RPWM_TIMER
- _set_timer(&pwrpriv->pwr_rpwm_timer, 1);
-#endif /* CONFIG_LPS_RPWM_TIMER */
- break;
- }
- } while (1);
-#endif /* CONFIG_DETECT_CPWM_BY_POLLING */
+ rtw_cpwm_polling(padapter, cpwm_orig);
+ #else
+ #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_P2P_WOWLAN)
+ if (pwrpriv->wowlan_mode == _TRUE ||
+ pwrpriv->wowlan_ap_mode == _TRUE ||
+ pwrpriv->wowlan_p2p_mode == _TRUE)
+ rtw_cpwm_polling(padapter, cpwm_orig);
+ #endif /*#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_P2P_WOWLAN)*/
+ #endif /*#ifdef CONFIG_DETECT_CPWM_BY_POLLING*/
} else
#endif /* CONFIG_LPS_LCLK */
{
pwrpriv->cpwm = pslv;
}
- _func_exit_;
}
u8 PS_RDY_CHECK(_adapter *padapter)
{
- u32 curr_time, delta_time;
+ u32 delta_ms;
struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
#ifdef CONFIG_P2P
@@ -622,26 +625,24 @@ u8 PS_RDY_CHECK(_adapter *padapter)
return _FALSE;
#endif
- curr_time = rtw_get_current_time();
-
- delta_time = curr_time - pwrpriv->DelayLPSLastTimeStamp;
-
- if (delta_time < LPS_DELAY_TIME)
+ delta_ms = rtw_get_passing_time_ms(pwrpriv->DelayLPSLastTimeStamp);
+ if (delta_ms < LPS_DELAY_MS)
return _FALSE;
if (check_fwstate(pmlmepriv, WIFI_SITE_MONITOR)
- || check_fwstate(pmlmepriv, WIFI_UNDER_LINKING | WIFI_UNDER_WPS)
- || check_fwstate(pmlmepriv, WIFI_AP_STATE)
- || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE)
-#if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211)
- || pcfg80211_wdinfo->is_ro_ch
-#endif
- || rtw_is_scan_deny(padapter)
-#ifdef CONFIG_TDLS
- /* TDLS link is established. */
- || (padapter->tdlsinfo.link_established == _TRUE)
-#endif /* CONFIG_TDLS */
- )
+ || check_fwstate(pmlmepriv, WIFI_UNDER_LINKING | WIFI_UNDER_WPS)
+ || MLME_IS_AP(padapter)
+ || MLME_IS_MESH(padapter)
+ || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE)
+ #if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211)
+ || rtw_cfg80211_get_is_roch(padapter) == _TRUE
+ #endif
+ || rtw_is_scan_deny(padapter)
+ #ifdef CONFIG_TDLS
+ /* TDLS link is established. */
+ || (padapter->tdlsinfo.link_established == _TRUE)
+ #endif /* CONFIG_TDLS */
+ )
return _FALSE;
if ((padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) && (padapter->securitypriv.binstallGrpkey == _FALSE)) {
@@ -662,7 +663,7 @@ void rtw_set_fw_in_ips_mode(PADAPTER padapter, u8 enable)
{
struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
int cnt = 0;
- u32 start_time;
+ systime start_time;
u8 val8 = 0;
u8 cpwm_orig = 0, cpwm_now = 0;
u8 parm[H2C_INACTIVE_PS_LEN] = {0};
@@ -704,11 +705,11 @@ void rtw_set_fw_in_ips_mode(PADAPTER padapter, u8 enable)
/* H2C done, enter 32k */
if (val8 == 0) {
/* ser rpwm to enter 32k */
- val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1);
+ rtw_hal_get_hwreg(padapter, HW_VAR_RPWM_TOG, &val8);
RTW_INFO("%s: read rpwm=%02x\n", __FUNCTION__, val8);
val8 += 0x80;
val8 |= BIT(0);
- rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
+ rtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&val8));
RTW_INFO("%s: write rpwm=%02x\n", __FUNCTION__, val8);
adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
cnt = val8 = 0;
@@ -737,11 +738,10 @@ void rtw_set_fw_in_ips_mode(PADAPTER padapter, u8 enable)
rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_orig);
/* ser rpwm */
- val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1);
- val8 &= 0x80;
+ rtw_hal_get_hwreg(padapter, HW_VAR_RPWM_TOG, &val8);
val8 += 0x80;
val8 |= BIT(6);
- rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
+ rtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&val8));
RTW_INFO("%s: write rpwm=%02x\n", __FUNCTION__, val8);
adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
@@ -779,6 +779,7 @@ void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode
struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
struct dvobj_priv *psdpriv = padapter->dvobj;
struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
+ struct registry_priv *pregistrypriv = &padapter->registrypriv;
#ifdef CONFIG_P2P
struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
#endif /* CONFIG_P2P */
@@ -789,15 +790,13 @@ void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode
_list *plist, *phead;
struct sta_info *ptdls_sta;
#endif /* CONFIG_TDLS */
+#ifdef CONFIG_LPS_PG
+ u8 lps_pg_hdl_id = 0;
+#endif
- _func_enter_;
- RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_,
- ("%s: PowerMode=%d Smart_PS=%d\n",
- __FUNCTION__, ps_mode, smart_ps));
if (ps_mode > PM_Card_Disable) {
- RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_err_, ("ps_mode:%d error\n", ps_mode));
return;
}
@@ -806,12 +805,30 @@ void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode
return;
#ifndef CONFIG_BT_COEXIST
- if ((pwrpriv->smart_ps == smart_ps) &&
- (pwrpriv->bcn_ant_mode == bcn_ant_mode))
- return;
+#ifdef CONFIG_WMMPS_STA
+ if (!rtw_is_wmmps_mode(padapter))
+#endif /* CONFIG_WMMPS_STA */
+ if ((pwrpriv->smart_ps == smart_ps) &&
+ (pwrpriv->bcn_ant_mode == bcn_ant_mode))
+ return;
#endif /* !CONFIG_BT_COEXIST */
}
+#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
+ if (PS_MODE_ACTIVE != ps_mode) {
+ rtw_set_ps_rsvd_page(padapter);
+ rtw_set_default_port_id(padapter);
+ }
+#endif
+
+#ifdef CONFIG_LPS_PG
+ if ((PS_MODE_ACTIVE != ps_mode) && (pwrpriv->blpspg_info_up)) {
+ /*rtw_hal_set_lps_pg_info(padapter);*/
+ lps_pg_hdl_id = LPS_PG_INFO_CFG;
+ rtw_hal_set_hwreg(padapter, HW_VAR_LPS_PG_HANDLE, (u8 *)(&lps_pg_hdl_id));
+ }
+#endif
+
#ifdef CONFIG_LPS_LCLK
_enter_pwrlock(&pwrpriv->lock);
#endif
@@ -850,7 +867,7 @@ void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode
ptdls_sta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)
- issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->hwaddr, 0, 0, 0);
+ issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->cmn.mac_addr, 0, 0, 0);
plist = get_next(plist);
}
}
@@ -863,7 +880,8 @@ void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode
if (pwrpriv->wowlan_mode == _TRUE ||
pwrpriv->wowlan_ap_mode == _TRUE ||
pwrpriv->wowlan_p2p_mode == _TRUE) {
- u32 start_time, delay_ms;
+ systime start_time;
+ u32 delay_ms;
u8 val8;
delay_ms = 20;
start_time = rtw_get_current_time();
@@ -882,8 +900,22 @@ void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode
rtw_usleep_os(100);
} while (1);
}
+#endif
+#ifdef CONFIG_LPS_PG
+ if (pwrpriv->lps_level == LPS_PG) {
+ lps_pg_hdl_id = LPS_PG_REDLEMEM;
+ rtw_hal_set_hwreg(padapter, HW_VAR_LPS_PG_HANDLE, (u8 *)(&lps_pg_hdl_id));
+ }
#endif
rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&ps_mode));
+
+#ifdef CONFIG_LPS_PG
+ if (pwrpriv->lps_level == LPS_PG) {
+ lps_pg_hdl_id = LPS_PG_RESEND_H2C;
+ rtw_hal_set_hwreg(padapter, HW_VAR_LPS_PG_HANDLE, (u8 *)(&lps_pg_hdl_id));
+ }
+#endif
+
#ifdef CONFIG_LPS_POFF
rtw_hal_set_hwreg(padapter, HW_VAR_LPS_POFF_SET_MODE,
(u8 *)(&ps_mode));
@@ -923,7 +955,7 @@ void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode
ptdls_sta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)
- issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->hwaddr, 1, 0, 0);
+ issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->cmn.mac_addr, 1, 0, 0);
plist = get_next(plist);
}
}
@@ -942,6 +974,11 @@ void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode
pwrpriv->pwr_mode = ps_mode;
pwrpriv->smart_ps = smart_ps;
pwrpriv->bcn_ant_mode = bcn_ant_mode;
+
+#ifdef CONFIG_WMMPS_STA
+ pwrpriv->wmm_smart_ps = pregistrypriv->wmm_smart_ps;
+#endif /* CONFIG_WMMPS_STA */
+
rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&ps_mode));
#ifdef CONFIG_P2P_PS
@@ -976,7 +1013,6 @@ void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode
_exit_pwrlock(&pwrpriv->lock);
#endif
- _func_exit_;
}
/*
@@ -987,7 +1023,7 @@ void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode
*/
s32 LPS_RF_ON_check(PADAPTER padapter, u32 delay_ms)
{
- u32 start_time;
+ systime start_time;
u8 bAwake = _FALSE;
s32 err = 0;
@@ -1028,9 +1064,10 @@ void LPS_Enter(PADAPTER padapter, const char *msg)
int i;
char buf[32] = {0};
- _func_enter_;
/* RTW_INFO("+LeisurePSEnter\n"); */
+ if (GET_HAL_DATA(padapter)->bFWReady == _FALSE)
+ return;
#ifdef CONFIG_BT_COEXIST
if (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)
@@ -1045,9 +1082,11 @@ void LPS_Enter(PADAPTER padapter, const char *msg)
if (n_assoc_iface != 1)
return;
+#ifndef CONFIG_FW_MULTI_PORT_SUPPORT
/* Skip lps enter request for adapter not port0 */
if (get_hw_port(padapter) != HW_PORT0)
return;
+#endif
for (i = 0; i < dvobj->iface_nums; i++) {
if (PS_RDY_CHECK(dvobj->padapters[i]) == _FALSE)
@@ -1062,15 +1101,21 @@ void LPS_Enter(PADAPTER padapter, const char *msg)
if (pwrpriv->bLeisurePs) {
/* Idle for a while if we connect to AP a while ago. */
-#ifdef CONFIG_LPS_PG
- if (pwrpriv->LpsIdleCount == 2)
- rtw_hal_set_lps_pg_info(padapter);
-#endif
-
if (pwrpriv->LpsIdleCount >= 2) { /* 4 Sec */
if (pwrpriv->pwr_mode == PS_MODE_ACTIVE) {
+
+#ifdef CONFIG_WMMPS_STA
+ if (rtw_is_wmmps_mode(padapter))
+ msg = "WMMPS_IDLE";
+#endif /* CONFIG_WMMPS_STA */
+
sprintf(buf, "WIFI-%s", msg);
pwrpriv->bpower_saving = _TRUE;
+
+#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS
+ pwrpriv->pwr_saving_start_time = rtw_get_current_time();
+#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */
+
rtw_set_ps_mode(padapter, pwrpriv->power_mgnt, padapter->registrypriv.smart_ps, 0, buf);
}
} else
@@ -1079,7 +1124,6 @@ void LPS_Enter(PADAPTER padapter, const char *msg)
/* RTW_INFO("-LeisurePSEnter\n"); */
- _func_exit_;
}
/*
@@ -1097,7 +1141,6 @@ void LPS_Leave(PADAPTER padapter, const char *msg)
char buf[32] = {0};
struct debug_priv *pdbgpriv = &dvobj->drv_dbg;
- _func_enter_;
/* RTW_INFO("+LeisurePSLeave\n"); */
@@ -1108,9 +1151,19 @@ void LPS_Leave(PADAPTER padapter, const char *msg)
if (pwrpriv->bLeisurePs) {
if (pwrpriv->pwr_mode != PS_MODE_ACTIVE) {
+
+#ifdef CONFIG_WMMPS_STA
+ if (rtw_is_wmmps_mode(padapter))
+ msg = "WMMPS_BUSY";
+#endif /* CONFIG_WMMPS_STA */
+
sprintf(buf, "WIFI-%s", msg);
rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, buf);
+#ifdef CONFIG_RTW_CFGVEDNOR_LLSTATS
+ pwrpriv->pwr_saving_time += rtw_get_passing_time_ms(pwrpriv->pwr_saving_start_time);
+#endif /* CONFIG_RTW_CFGVEDNOR_LLSTATS */
+
if (pwrpriv->pwr_mode == PS_MODE_ACTIVE)
LPS_RF_ON_check(padapter, LPS_LEAVE_TIMEOUT_MS);
}
@@ -1125,7 +1178,20 @@ void LPS_Leave(PADAPTER padapter, const char *msg)
#endif /* DBG_CHECK_FW_PS_STATE
* RTW_INFO("-LeisurePSLeave\n"); */
- _func_exit_;
+}
+
+void rtw_wow_lps_level_decide(_adapter *adapter, u8 wow_en)
+{
+#if defined(CONFIG_USB_HCI) && defined(CONFIG_LPS_LCLK)
+ struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+ struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
+
+ if (wow_en) {
+ pwrpriv->lps_level_bk = pwrpriv->lps_level;
+ pwrpriv->lps_level = LPS_LCLK;
+ } else
+ pwrpriv->lps_level = pwrpriv->lps_level_bk;
+#endif
}
#endif
@@ -1138,10 +1204,9 @@ void LeaveAllPowerSaveModeDirect(PADAPTER Adapter)
struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
#ifndef CONFIG_DETECT_CPWM_BY_POLLING
u8 cpwm_orig, cpwm_now;
- u32 start_time;
+ systime start_time;
#endif /* CONFIG_DETECT_CPWM_BY_POLLING */
- _func_enter_;
RTW_INFO("%s.....\n", __FUNCTION__);
@@ -1234,7 +1299,6 @@ void LeaveAllPowerSaveModeDirect(PADAPTER Adapter)
}
}
- _func_exit_;
}
/*
@@ -1249,7 +1313,6 @@ void LeaveAllPowerSaveMode(IN PADAPTER Adapter)
int n_assoc_iface = 0;
int i;
- _func_enter_;
/* RTW_INFO("%s.....\n",__FUNCTION__); */
@@ -1276,7 +1339,13 @@ void LeaveAllPowerSaveMode(IN PADAPTER Adapter)
#endif
#ifdef CONFIG_P2P_PS
- p2p_ps_wk_cmd(Adapter, P2P_PS_DISABLE, enqueue);
+ for (i = 0; i < dvobj->iface_nums; i++) {
+ _adapter *iface = dvobj->padapters[i];
+ struct wifidirect_info *pwdinfo = &(iface->wdinfo);
+
+ if (pwdinfo->p2p_ps_mode > P2P_PS_NONE)
+ p2p_ps_wk_cmd(iface, P2P_PS_DISABLE, enqueue);
+ }
#endif /* CONFIG_P2P_PS */
#ifdef CONFIG_LPS
@@ -1308,7 +1377,6 @@ void LeaveAllPowerSaveMode(IN PADAPTER Adapter)
}
}
- _func_exit_;
}
#ifdef CONFIG_LPS_LCLK
@@ -1316,10 +1384,9 @@ void LPS_Leave_check(
PADAPTER padapter)
{
struct pwrctrl_priv *pwrpriv;
- u32 start_time;
+ systime start_time;
u8 bReady;
- _func_enter_;
pwrpriv = adapter_to_pwrctl(padapter);
@@ -1352,7 +1419,6 @@ void LPS_Leave_check(
rtw_msleep_os(1);
}
- _func_exit_;
}
/*
@@ -1368,14 +1434,15 @@ void cpwm_int_hdl(
{
struct pwrctrl_priv *pwrpriv;
- _func_enter_;
+ if (!padapter)
+ goto exit;
+
+ if (RTW_CANNOT_RUN(padapter))
+ goto exit;
pwrpriv = adapter_to_pwrctl(padapter);
#if 0
if (pwrpriv->cpwm_tog == (preportpwrstate->state & PS_TOGGLE)) {
- RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_err_,
- ("cpwm_int_hdl: tog(old)=0x%02x cpwm(new)=0x%02x toggle bit didn't change!?\n",
- pwrpriv->cpwm_tog, preportpwrstate->state));
goto exit;
}
#endif
@@ -1404,17 +1471,14 @@ void cpwm_int_hdl(
_exit_pwrlock(&pwrpriv->lock);
exit:
- RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_,
- ("cpwm_int_hdl: cpwm=0x%02x\n", pwrpriv->cpwm));
-
- _func_exit_;
+ return;
}
static void cpwm_event_callback(struct work_struct *work)
{
struct pwrctrl_priv *pwrpriv = container_of(work, struct pwrctrl_priv, cpwm_event);
struct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv);
- _adapter *adapter = dvobj->padapters[IFACE_ID0];
+ _adapter *adapter = dvobj_get_primary_adapter(dvobj);
struct reportpwrstate_parm report;
/* RTW_INFO("%s\n",__FUNCTION__); */
@@ -1423,7 +1487,40 @@ static void cpwm_event_callback(struct work_struct *work)
cpwm_int_hdl(adapter, &report);
}
+static void dma_event_callback(struct work_struct *work)
+{
+ struct pwrctrl_priv *pwrpriv = container_of(work, struct pwrctrl_priv, dma_event);
+ struct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv);
+ _adapter *adapter = dvobj_get_primary_adapter(dvobj);
+
+ rtw_unregister_tx_alive(adapter);
+}
+
#ifdef CONFIG_LPS_RPWM_TIMER
+
+#define DBG_CPWM_CHK_FAIL
+#if defined(DBG_CPWM_CHK_FAIL) && (defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C))
+#define CPU_EXCEPTION_CODE 0xFAFAFAFA
+static void rtw_cpwm_chk_fail_debug(_adapter *padapter)
+{
+ u32 cpu_state;
+
+ cpu_state = rtw_read32(padapter, 0x10FC);
+
+ RTW_INFO("[PS-DBG] Reg_10FC =0x%08x\n", cpu_state);
+ RTW_INFO("[PS-DBG] Reg_10F8 =0x%08x\n", rtw_read32(padapter, 0x10F8));
+
+ if (cpu_state == CPU_EXCEPTION_CODE) {
+ RTW_INFO("[PS-DBG] Reg_48C =0x%08x\n", rtw_read32(padapter, 0x48C));
+ RTW_INFO("[PS-DBG] Reg_490 =0x%08x\n", rtw_read32(padapter, 0x490));
+ RTW_INFO("[PS-DBG] Reg_494 =0x%08x\n", rtw_read32(padapter, 0x494));
+ RTW_INFO("[PS-DBG] Reg_498 =0x%08x\n", rtw_read32(padapter, 0x498));
+ RTW_INFO("[PS-DBG] Reg_49C =0x%08x\n", rtw_read32(padapter, 0x49C));
+ RTW_INFO("[PS-DBG] Reg_4A0 =0x%08x\n", rtw_read32(padapter, 0x4A0));
+ RTW_INFO("[PS-DBG] Reg_1BC =0x%08x\n", rtw_read32(padapter, 0x1BC));
+ }
+}
+#endif
static void rpwmtimeout_workitem_callback(struct work_struct *work)
{
PADAPTER padapter;
@@ -1433,8 +1530,13 @@ static void rpwmtimeout_workitem_callback(struct work_struct *work)
pwrpriv = container_of(work, struct pwrctrl_priv, rpwmtimeoutwi);
dvobj = pwrctl_to_dvobj(pwrpriv);
- padapter = dvobj->padapters[IFACE_ID0];
- /* RTW_INFO("+%s: rpwm=0x%02X cpwm=0x%02X\n", __func__, pwrpriv->rpwm, pwrpriv->cpwm); */
+ padapter = dvobj_get_primary_adapter(dvobj);
+
+ if (!padapter)
+ return;
+
+ if (RTW_CANNOT_RUN(padapter))
+ return;
_enter_pwrlock(&pwrpriv->lock);
if ((pwrpriv->rpwm == pwrpriv->cpwm) || (pwrpriv->cpwm >= PS_STATE_S2)) {
@@ -1443,6 +1545,11 @@ static void rpwmtimeout_workitem_callback(struct work_struct *work)
}
_exit_pwrlock(&pwrpriv->lock);
+#if defined(DBG_CPWM_CHK_FAIL) && (defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C))
+ RTW_INFO("+%s: rpwm=0x%02X cpwm=0x%02X\n", __func__, pwrpriv->rpwm, pwrpriv->cpwm);
+ rtw_cpwm_chk_fail_debug(padapter);
+#endif
+
if (rtw_read8(padapter, 0x100) != 0xEA) {
#if 1
struct reportpwrstate_parm report;
@@ -1482,6 +1589,12 @@ static void pwr_rpwm_timeout_handler(void *FunctionContext)
padapter = (PADAPTER)FunctionContext;
pwrpriv = adapter_to_pwrctl(padapter);
+ if (!padapter)
+ return;
+
+ if (RTW_CANNOT_RUN(padapter))
+ return;
+
RTW_INFO("+%s: rpwm=0x%02X cpwm=0x%02X\n", __func__, pwrpriv->rpwm, pwrpriv->cpwm);
if ((pwrpriv->rpwm == pwrpriv->cpwm) || (pwrpriv->cpwm >= PS_STATE_S2)) {
@@ -1525,7 +1638,6 @@ s32 rtw_register_task_alive(PADAPTER padapter, u32 task)
struct pwrctrl_priv *pwrctrl;
u8 pslv;
- _func_enter_;
res = _SUCCESS;
pwrctrl = adapter_to_pwrctl(padapter);
@@ -1536,9 +1648,6 @@ s32 rtw_register_task_alive(PADAPTER padapter, u32 task)
register_task_alive(pwrctrl, task);
if (pwrctrl->bFwCurrentInPSMode == _TRUE) {
- RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_,
- ("%s: task=0x%x cpwm=0x%02x alives=0x%08x\n",
- __FUNCTION__, task, pwrctrl->cpwm, pwrctrl->alives));
if (pwrctrl->cpwm < pslv) {
if (pwrctrl->cpwm < PS_STATE_S2)
@@ -1557,7 +1666,6 @@ s32 rtw_register_task_alive(PADAPTER padapter, u32 task)
}
#endif /* CONFIG_DETECT_CPWM_BY_POLLING */
- _func_exit_;
return res;
}
@@ -1577,7 +1685,6 @@ void rtw_unregister_task_alive(PADAPTER padapter, u32 task)
struct pwrctrl_priv *pwrctrl;
u8 pslv;
- _func_enter_;
pwrctrl = adapter_to_pwrctl(padapter);
pslv = PS_STATE_S0;
@@ -1600,9 +1707,6 @@ void rtw_unregister_task_alive(PADAPTER padapter, u32 task)
if ((pwrctrl->pwr_mode != PS_MODE_ACTIVE)
&& (pwrctrl->bFwCurrentInPSMode == _TRUE)) {
- RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_,
- ("%s: cpwm=0x%02x alives=0x%08x\n",
- __FUNCTION__, pwrctrl->cpwm, pwrctrl->alives));
if (pwrctrl->cpwm > pslv) {
if ((pslv >= PS_STATE_S2) || (pwrctrl->alives == 0))
@@ -1612,7 +1716,6 @@ void rtw_unregister_task_alive(PADAPTER padapter, u32 task)
_exit_pwrlock(&pwrctrl->lock);
- _func_exit_;
}
/*
@@ -1634,7 +1737,6 @@ s32 rtw_register_tx_alive(PADAPTER padapter)
struct pwrctrl_priv *pwrctrl;
u8 pslv;
- _func_enter_;
res = _SUCCESS;
pwrctrl = adapter_to_pwrctl(padapter);
@@ -1645,9 +1747,6 @@ s32 rtw_register_tx_alive(PADAPTER padapter)
register_task_alive(pwrctrl, XMIT_ALIVE);
if (pwrctrl->bFwCurrentInPSMode == _TRUE) {
- RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_,
- ("rtw_register_tx_alive: cpwm=0x%02x alives=0x%08x\n",
- pwrctrl->cpwm, pwrctrl->alives));
if (pwrctrl->cpwm < pslv) {
if (pwrctrl->cpwm < PS_STATE_S2)
@@ -1666,7 +1765,6 @@ s32 rtw_register_tx_alive(PADAPTER padapter)
}
#endif /* CONFIG_DETECT_CPWM_BY_POLLING */
- _func_exit_;
return res;
}
@@ -1690,7 +1788,6 @@ s32 rtw_register_cmd_alive(PADAPTER padapter)
struct pwrctrl_priv *pwrctrl;
u8 pslv;
- _func_enter_;
res = _SUCCESS;
pwrctrl = adapter_to_pwrctl(padapter);
@@ -1701,9 +1798,6 @@ s32 rtw_register_cmd_alive(PADAPTER padapter)
register_task_alive(pwrctrl, CMD_ALIVE);
if (pwrctrl->bFwCurrentInPSMode == _TRUE) {
- RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_info_,
- ("rtw_register_cmd_alive: cpwm=0x%02x alives=0x%08x\n",
- pwrctrl->cpwm, pwrctrl->alives));
if (pwrctrl->cpwm < pslv) {
if (pwrctrl->cpwm < PS_STATE_S2)
@@ -1722,7 +1816,6 @@ s32 rtw_register_cmd_alive(PADAPTER padapter)
}
#endif /* CONFIG_DETECT_CPWM_BY_POLLING */
- _func_exit_;
return res;
}
@@ -1740,20 +1833,15 @@ s32 rtw_register_rx_alive(PADAPTER padapter)
{
struct pwrctrl_priv *pwrctrl;
- _func_enter_;
pwrctrl = adapter_to_pwrctl(padapter);
_enter_pwrlock(&pwrctrl->lock);
register_task_alive(pwrctrl, RECV_ALIVE);
- RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_,
- ("rtw_register_rx_alive: cpwm=0x%02x alives=0x%08x\n",
- pwrctrl->cpwm, pwrctrl->alives));
_exit_pwrlock(&pwrctrl->lock);
- _func_exit_;
return _SUCCESS;
}
@@ -1771,20 +1859,15 @@ s32 rtw_register_evt_alive(PADAPTER padapter)
{
struct pwrctrl_priv *pwrctrl;
- _func_enter_;
pwrctrl = adapter_to_pwrctl(padapter);
_enter_pwrlock(&pwrctrl->lock);
register_task_alive(pwrctrl, EVT_ALIVE);
- RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_,
- ("rtw_register_evt_alive: cpwm=0x%02x alives=0x%08x\n",
- pwrctrl->cpwm, pwrctrl->alives));
_exit_pwrlock(&pwrctrl->lock);
- _func_exit_;
return _SUCCESS;
}
@@ -1803,7 +1886,6 @@ void rtw_unregister_tx_alive(PADAPTER padapter)
struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
u8 pslv, i;
- _func_enter_;
pwrctrl = adapter_to_pwrctl(padapter);
pslv = PS_STATE_S0;
@@ -1837,9 +1919,6 @@ void rtw_unregister_tx_alive(PADAPTER padapter)
if ((pwrctrl->pwr_mode != PS_MODE_ACTIVE)
&& (pwrctrl->bFwCurrentInPSMode == _TRUE)) {
- RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_,
- ("%s: cpwm=0x%02x alives=0x%08x\n",
- __FUNCTION__, pwrctrl->cpwm, pwrctrl->alives));
if (pwrctrl->cpwm > pslv) {
if ((pslv >= PS_STATE_S2) || (pwrctrl->alives == 0))
@@ -1849,7 +1928,6 @@ void rtw_unregister_tx_alive(PADAPTER padapter)
_exit_pwrlock(&pwrctrl->lock);
- _func_exit_;
}
/*
@@ -1866,7 +1944,6 @@ void rtw_unregister_cmd_alive(PADAPTER padapter)
struct pwrctrl_priv *pwrctrl;
u8 pslv, i;
- _func_enter_;
pwrctrl = adapter_to_pwrctl(padapter);
pslv = PS_STATE_S0;
@@ -1901,9 +1978,6 @@ void rtw_unregister_cmd_alive(PADAPTER padapter)
if ((pwrctrl->pwr_mode != PS_MODE_ACTIVE)
&& (pwrctrl->bFwCurrentInPSMode == _TRUE)) {
- RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_info_,
- ("%s: cpwm=0x%02x alives=0x%08x\n",
- __FUNCTION__, pwrctrl->cpwm, pwrctrl->alives));
if (pwrctrl->cpwm > pslv) {
if ((pslv >= PS_STATE_S2) || (pwrctrl->alives == 0))
@@ -1913,7 +1987,6 @@ void rtw_unregister_cmd_alive(PADAPTER padapter)
_exit_pwrlock(&pwrctrl->lock);
- _func_exit_;
}
/*
@@ -1923,7 +1996,6 @@ void rtw_unregister_rx_alive(PADAPTER padapter)
{
struct pwrctrl_priv *pwrctrl;
- _func_enter_;
pwrctrl = adapter_to_pwrctl(padapter);
@@ -1931,32 +2003,23 @@ void rtw_unregister_rx_alive(PADAPTER padapter)
unregister_task_alive(pwrctrl, RECV_ALIVE);
- RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_,
- ("rtw_unregister_rx_alive: cpwm=0x%02x alives=0x%08x\n",
- pwrctrl->cpwm, pwrctrl->alives));
_exit_pwrlock(&pwrctrl->lock);
- _func_exit_;
}
void rtw_unregister_evt_alive(PADAPTER padapter)
{
struct pwrctrl_priv *pwrctrl;
- _func_enter_;
pwrctrl = adapter_to_pwrctl(padapter);
unregister_task_alive(pwrctrl, EVT_ALIVE);
- RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_,
- ("rtw_unregister_evt_alive: cpwm=0x%02x alives=0x%08x\n",
- pwrctrl->cpwm, pwrctrl->alives));
_exit_pwrlock(&pwrctrl->lock);
- _func_exit_;
}
#endif /* CONFIG_LPS_LCLK */
@@ -1967,15 +2030,15 @@ void rtw_unregister_evt_alive(PADAPTER padapter)
void rtw_init_pwrctrl_priv(PADAPTER padapter)
{
struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
- int i = 0;
+ struct registry_priv *registry_par = &padapter->registrypriv;
+
u8 val8 = 0;
#if defined(CONFIG_CONCURRENT_MODE)
- if (padapter->adapter_type != PRIMARY_ADAPTER)
+ if (!is_primary_adapter(padapter))
return;
#endif
- _func_enter_;
#ifdef PLATFORM_WINDOWS
pwrctrlpriv->pnp_current_pwr_state = NdisDeviceStateD0;
@@ -1992,10 +2055,14 @@ void rtw_init_pwrctrl_priv(PADAPTER padapter)
pwrctrlpriv->ips_mode = padapter->registrypriv.ips_mode;
pwrctrlpriv->ips_mode_req = padapter->registrypriv.ips_mode;
+ pwrctrlpriv->ips_deny_time = rtw_get_current_time();
+ pwrctrlpriv->lps_level = padapter->registrypriv.lps_level;
pwrctrlpriv->pwr_state_check_interval = RTW_PWR_STATE_CHK_INTERVAL;
pwrctrlpriv->pwr_state_check_cnts = 0;
+ #ifdef CONFIG_AUTOSUSPEND
pwrctrlpriv->bInternalAutoSuspend = _FALSE;
+ #endif
pwrctrlpriv->bInSuspend = _FALSE;
pwrctrlpriv->bkeepfwalive = _FALSE;
@@ -2006,6 +2073,11 @@ void rtw_init_pwrctrl_priv(PADAPTER padapter)
#endif
pwrctrlpriv->LpsIdleCount = 0;
+
+#ifdef CONFIG_LPS_PG
+ pwrctrlpriv->lpspg_rsvd_page_locate = 0;
+#endif
+
/* pwrctrlpriv->FWCtrlPSMode =padapter->registrypriv.power_mgnt; */ /* PS_MODE_MIN; */
if (padapter->registrypriv.mp_mode == 1)
pwrctrlpriv->power_mgnt = PS_MODE_ACTIVE ;
@@ -2030,18 +2102,22 @@ void rtw_init_pwrctrl_priv(PADAPTER padapter)
_init_workitem(&pwrctrlpriv->cpwm_event, cpwm_event_callback, NULL);
+ _init_workitem(&pwrctrlpriv->dma_event, dma_event_callback, NULL);
+
#ifdef CONFIG_LPS_RPWM_TIMER
pwrctrlpriv->brpwmtimeout = _FALSE;
_init_workitem(&pwrctrlpriv->rpwmtimeoutwi, rpwmtimeout_workitem_callback, NULL);
- _init_timer(&pwrctrlpriv->pwr_rpwm_timer, padapter->pnetdev, pwr_rpwm_timeout_handler, padapter);
+ rtw_init_timer(&pwrctrlpriv->pwr_rpwm_timer, padapter, pwr_rpwm_timeout_handler, padapter);
#endif /* CONFIG_LPS_RPWM_TIMER */
#endif /* CONFIG_LPS_LCLK */
- rtw_init_timer(&pwrctrlpriv->pwr_state_check_timer, padapter, pwr_state_check_handler);
+ rtw_init_timer(&pwrctrlpriv->pwr_state_check_timer, padapter, pwr_state_check_handler, padapter);
pwrctrlpriv->wowlan_mode = _FALSE;
pwrctrlpriv->wowlan_ap_mode = _FALSE;
pwrctrlpriv->wowlan_p2p_mode = _FALSE;
+ pwrctrlpriv->wowlan_in_resume = _FALSE;
+ pwrctrlpriv->wowlan_last_wake_reason = 0;
#ifdef CONFIG_RESUME_IN_WORKQUEUE
_init_workitem(&pwrctrlpriv->resume_work, resume_workitem_callback, NULL);
@@ -2056,38 +2132,45 @@ void rtw_init_pwrctrl_priv(PADAPTER padapter)
#ifdef CONFIG_GPIO_WAKEUP
/*default low active*/
pwrctrlpriv->is_high_active = HIGH_ACTIVE;
+
+ #ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE
+ if (pwrctrlpriv->is_high_active == 0)
+ rtw_hal_set_input_gpio(padapter, WAKEUP_GPIO_IDX);
+ else
+ rtw_hal_set_output_gpio(padapter, WAKEUP_GPIO_IDX, 0);
+ #else
val8 = (pwrctrlpriv->is_high_active == 0) ? 1 : 0;
rtw_hal_switch_gpio_wl_ctrl(padapter, WAKEUP_GPIO_IDX, _TRUE);
rtw_hal_set_output_gpio(padapter, WAKEUP_GPIO_IDX, val8);
RTW_INFO("%s: set GPIO_%d %d as default.\n",
__func__, WAKEUP_GPIO_IDX, val8);
+ #endif /*CONFIG_WAKEUP_GPIO_INPUT_MODE*/
#endif /* CONFIG_GPIO_WAKEUP */
#ifdef CONFIG_WOWLAN
- pwrctrlpriv->wowlan_pattern_idx = DEFAULT_PATTERN_NUM;
- for (i = 0 ; i < MAX_WKFM_NUM; i++) {
- _rtw_memset(pwrctrlpriv->patterns[i].content, '\0',
- sizeof(pwrctrlpriv->patterns[i].content));
- _rtw_memset(pwrctrlpriv->patterns[i].mask, '\0',
- sizeof(pwrctrlpriv->patterns[i].mask));
- pwrctrlpriv->patterns[i].len = 0;
- }
+ if (registry_par->wakeup_event & BIT(1))
+ pwrctrlpriv->default_patterns_en = _TRUE;
+ else
+ pwrctrlpriv->default_patterns_en = _FALSE;
+ rtw_wow_pattern_sw_reset(padapter);
#ifdef CONFIG_PNO_SUPPORT
pwrctrlpriv->pno_inited = _FALSE;
pwrctrlpriv->pnlo_info = NULL;
pwrctrlpriv->pscan_info = NULL;
pwrctrlpriv->pno_ssid_list = NULL;
- pwrctrlpriv->pno_in_resume = _TRUE;
#endif /* CONFIG_PNO_SUPPORT */
+#ifdef CONFIG_WOW_PATTERN_HW_CAM
+ _rtw_mutex_init(&pwrctrlpriv->wowlan_pattern_cam_mutex);
+#endif
+ pwrctrlpriv->wowlan_aoac_rpt_loc = 0;
#endif /* CONFIG_WOWLAN */
#ifdef CONFIG_LPS_POFF
rtw_hal_set_hwreg(padapter, HW_VAR_LPS_POFF_INIT, 0);
#endif
- _func_exit_;
}
@@ -2097,11 +2180,10 @@ void rtw_free_pwrctrl_priv(PADAPTER adapter)
struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(adapter);
#if defined(CONFIG_CONCURRENT_MODE)
- if (adapter->adapter_type != PRIMARY_ADAPTER)
+ if (!is_primary_adapter(adapter))
return;
#endif
- _func_enter_;
/* _rtw_memset((unsigned char *)pwrctrlpriv, 0, sizeof(struct pwrctrl_priv)); */
@@ -2117,6 +2199,14 @@ void rtw_free_pwrctrl_priv(PADAPTER adapter)
rtw_hal_set_hwreg(adapter, HW_VAR_LPS_POFF_DEINIT, 0);
#endif
+#ifdef CONFIG_LPS_LCLK
+ _cancel_workitem_sync(&pwrctrlpriv->cpwm_event);
+ _cancel_workitem_sync(&pwrctrlpriv->dma_event);
+ #ifdef CONFIG_LPS_RPWM_TIMER
+ _cancel_workitem_sync(&pwrctrlpriv->rpwmtimeoutwi);
+ #endif
+#endif /* CONFIG_LPS_LCLK */
+
#ifdef CONFIG_WOWLAN
#ifdef CONFIG_PNO_SUPPORT
if (pwrctrlpriv->pnlo_info != NULL)
@@ -2128,6 +2218,10 @@ void rtw_free_pwrctrl_priv(PADAPTER adapter)
if (pwrctrlpriv->pno_ssid_list != NULL)
printk("****** pno_ssid_list memory leak********\n");
#endif
+#ifdef CONFIG_WOW_PATTERN_HW_CAM
+ _rtw_mutex_free(&pwrctrlpriv->wowlan_pattern_cam_mutex);
+#endif
+
#endif /* CONFIG_WOWLAN */
#if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER)
@@ -2137,7 +2231,6 @@ void rtw_free_pwrctrl_priv(PADAPTER adapter)
_free_pwrlock(&pwrctrlpriv->lock);
_free_pwrlock(&pwrctrlpriv->check_32k_lock);
- _func_exit_;
}
#ifdef CONFIG_RESUME_IN_WORKQUEUE
@@ -2147,7 +2240,7 @@ static void resume_workitem_callback(struct work_struct *work)
{
struct pwrctrl_priv *pwrpriv = container_of(work, struct pwrctrl_priv, resume_work);
struct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv);
- _adapter *adapter = dvobj->padapters[IFACE_ID0];
+ _adapter *adapter = dvobj_get_primary_adapter(dvobj);
RTW_INFO("%s\n", __FUNCTION__);
@@ -2202,7 +2295,7 @@ static void rtw_late_resume(struct early_suspend *h)
{
struct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend);
struct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv);
- _adapter *adapter = dvobj->padapters[IFACE_ID0];
+ _adapter *adapter = dvobj_get_primary_adapter(dvobj);
RTW_INFO("%s\n", __FUNCTION__);
@@ -2255,7 +2348,7 @@ static void rtw_late_resume(android_early_suspend_t *h)
{
struct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend);
struct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv);
- _adapter *adapter = dvobj->padapters[IFACE_ID0];
+ _adapter *adapter = dvobj_get_primary_adapter(dvobj);
RTW_INFO("%s\n", __FUNCTION__);
if (pwrpriv->do_late_resume) {
@@ -2320,7 +2413,7 @@ int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller)
struct mlme_priv *pmlmepriv;
int ret = _SUCCESS;
int i;
- u32 start = rtw_get_current_time();
+ systime start = rtw_get_current_time();
/* for LPS */
LeaveAllPowerSaveMode(padapter);
@@ -2329,7 +2422,7 @@ int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller)
padapter = GET_PRIMARY_ADAPTER(padapter);
pmlmepriv = &padapter->mlmepriv;
- if (pwrpriv->ips_deny_time < rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms))
+ if (rtw_time_after(rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms), pwrpriv->ips_deny_time))
pwrpriv->ips_deny_time = rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms);
@@ -2355,7 +2448,11 @@ int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller)
}
#endif
- if (pwrpriv->bInternalAutoSuspend == _FALSE && pwrpriv->bInSuspend) {
+ if (pwrpriv->bInSuspend
+ #ifdef CONFIG_AUTOSUSPEND
+ && pwrpriv->bInternalAutoSuspend == _FALSE
+ #endif
+ ) {
RTW_INFO("%s wait bInSuspend...\n", __func__);
while (pwrpriv->bInSuspend
&& ((rtw_get_passing_time_ms(start) <= 3000 && !rtw_is_do_late_resume(pwrpriv))
@@ -2369,17 +2466,21 @@ int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller)
}
/* System suspend is not allowed to wakeup */
- if ((pwrpriv->bInternalAutoSuspend == _FALSE) && (_TRUE == pwrpriv->bInSuspend)) {
+ if ((_TRUE == pwrpriv->bInSuspend)
+ #ifdef CONFIG_AUTOSUSPEND
+ && (pwrpriv->bInternalAutoSuspend == _FALSE)
+ #endif
+ ) {
ret = _FAIL;
goto exit;
}
-
- /* block??? */
+#ifdef CONFIG_AUTOSUSPEND
+ /* usb autosuspend block??? */
if ((pwrpriv->bInternalAutoSuspend == _TRUE) && (padapter->net_closed == _TRUE)) {
ret = _FAIL;
goto exit;
}
-
+#endif
/* I think this should be check in IPS, LPS, autosuspend functions... */
if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {
#if defined(CONFIG_BT_COEXIST) && defined (CONFIG_AUTOSUSPEND)
@@ -2447,7 +2548,7 @@ int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller)
}
exit:
- if (pwrpriv->ips_deny_time < rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms))
+ if (rtw_time_after(rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms), pwrpriv->ips_deny_time))
pwrpriv->ips_deny_time = rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms);
return ret;
@@ -2473,6 +2574,19 @@ int rtw_pm_set_lps(_adapter *padapter, u8 mode)
return ret;
}
+int rtw_pm_set_lps_level(_adapter *padapter, u8 level)
+{
+ int ret = 0;
+ struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
+
+ if (level < LPS_LEVEL_MAX)
+ pwrctrlpriv->lps_level = level;
+ else
+ ret = -EINVAL;
+
+ return ret;
+}
+
int rtw_pm_set_ips(_adapter *padapter, u8 mode)
{
struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
diff --git a/core/rtw_recv.c b/core/rtw_recv.c
index 2e46bfe..4da9bc4 100644
--- a/core/rtw_recv.c
+++ b/core/rtw_recv.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,12 +11,7 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#define _RTW_RECV_C_
#include
@@ -30,7 +25,7 @@
#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
-void rtw_signal_stat_timer_hdl(RTW_TIMER_HDL_ARGS);
+static void rtw_signal_stat_timer_hdl(void *ctx);
enum {
SIGNAL_STAT_CALC_PROFILE_0 = 0,
@@ -53,7 +48,6 @@ void _rtw_init_sta_recv_priv(struct sta_recv_priv *psta_recvpriv)
{
- _func_enter_;
_rtw_memset((u8 *)psta_recvpriv, 0, sizeof(struct sta_recv_priv));
@@ -64,7 +58,6 @@ void _rtw_init_sta_recv_priv(struct sta_recv_priv *psta_recvpriv)
_rtw_init_queue(&psta_recvpriv->defrag_q);
- _func_exit_;
}
@@ -75,13 +68,17 @@ sint _rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter)
union recv_frame *precvframe;
sint res = _SUCCESS;
- _func_enter_;
/* We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). */
/* _rtw_memset((unsigned char *)precvpriv, 0, sizeof (struct recv_priv)); */
_rtw_spinlock_init(&precvpriv->lock);
+#ifdef CONFIG_RECV_THREAD_MODE
+ _rtw_init_sema(&precvpriv->recv_sema, 0);
+
+#endif
+
_rtw_init_queue(&precvpriv->free_recv_queue);
_rtw_init_queue(&precvpriv->recv_pending_queue);
_rtw_init_queue(&precvpriv->uc_swdec_pending_queue);
@@ -142,7 +139,7 @@ sint _rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter)
res = rtw_hal_init_recv_priv(padapter);
#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
- rtw_init_timer(&precvpriv->signal_stat_timer, padapter, RTW_TIMER_HDL_NAME(signal_stat));
+ rtw_init_timer(&precvpriv->signal_stat_timer, padapter, rtw_signal_stat_timer_hdl, padapter);
precvpriv->signal_stat_sampling_interval = 2000; /* ms */
/* precvpriv->signal_stat_converging_constant = 5000; */ /* ms */
@@ -152,7 +149,6 @@ sint _rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter)
exit:
- _func_exit_;
return res;
@@ -164,7 +160,6 @@ void rtw_mfree_recv_priv_lock(struct recv_priv *precvpriv)
_rtw_spinlock_free(&precvpriv->lock);
#ifdef CONFIG_RECV_THREAD_MODE
_rtw_free_sema(&precvpriv->recv_sema);
- _rtw_free_sema(&precvpriv->terminate_recvthread_sema);
#endif
_rtw_spinlock_free(&precvpriv->free_recv_queue.lock);
@@ -181,7 +176,6 @@ void _rtw_free_recv_priv(struct recv_priv *precvpriv)
{
_adapter *padapter = precvpriv->adapter;
- _func_enter_;
rtw_free_uc_swdec_pending_queue(padapter);
@@ -194,7 +188,6 @@ void _rtw_free_recv_priv(struct recv_priv *precvpriv)
rtw_hal_free_recv_priv(padapter);
- _func_exit_;
}
@@ -218,7 +211,6 @@ union recv_frame *_rtw_alloc_recvframe(_queue *pfree_recv_queue)
_list *plist, *phead;
_adapter *padapter;
struct recv_priv *precvpriv;
- _func_enter_;
if (_rtw_queue_empty(pfree_recv_queue) == _TRUE)
precvframe = NULL;
@@ -238,7 +230,6 @@ union recv_frame *_rtw_alloc_recvframe(_queue *pfree_recv_queue)
}
}
- _func_exit_;
return precvframe;
@@ -272,7 +263,6 @@ int rtw_free_recvframe(union recv_frame *precvframe, _queue *pfree_recv_queue)
_adapter *padapter = precvframe->u.hdr.adapter;
struct recv_priv *precvpriv = &padapter->recvpriv;
- _func_enter_;
#ifdef CONFIG_CONCURRENT_MODE
padapter = GET_PRIMARY_ADAPTER(padapter);
@@ -300,7 +290,6 @@ int rtw_free_recvframe(union recv_frame *precvframe, _queue *pfree_recv_queue)
_exit_critical_bh(&pfree_recv_queue->lock, &irqL);
- _func_exit_;
return _SUCCESS;
@@ -315,7 +304,6 @@ sint _rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue)
_adapter *padapter = precvframe->u.hdr.adapter;
struct recv_priv *precvpriv = &padapter->recvpriv;
- _func_enter_;
/* _rtw_init_listhead(&(precvframe->u.hdr.list)); */
rtw_list_delete(&(precvframe->u.hdr.list));
@@ -328,7 +316,6 @@ sint _rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue)
precvpriv->free_recvframe_cnt++;
}
- _func_exit_;
return _SUCCESS;
}
@@ -370,7 +357,6 @@ void rtw_free_recvframe_queue(_queue *pframequeue, _queue *pfree_recv_queue)
union recv_frame *precvframe;
_list *plist, *phead;
- _func_enter_;
_rtw_spinlock(&pframequeue->lock);
phead = get_list_head(pframequeue);
@@ -388,7 +374,6 @@ void rtw_free_recvframe_queue(_queue *pframequeue, _queue *pfree_recv_queue)
_rtw_spinunlock(&pframequeue->lock);
- _func_exit_;
}
@@ -495,14 +480,10 @@ sint recvframe_chkmic(_adapter *adapter, union recv_frame *precvframe)
struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
- _func_enter_;
stainfo = rtw_get_stainfo(&adapter->stapriv , &prxattrib->ta[0]);
if (prxattrib->encrypt == _TKIP_) {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("\n recvframe_chkmic:prxattrib->encrypt ==_TKIP_\n"));
- RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("\n recvframe_chkmic:da=0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x\n",
- prxattrib->ra[0], prxattrib->ra[1], prxattrib->ra[2], prxattrib->ra[3], prxattrib->ra[4], prxattrib->ra[5]));
/* calculate mic code */
if (stainfo != NULL) {
@@ -512,26 +493,22 @@ sint recvframe_chkmic(_adapter *adapter, union recv_frame *precvframe)
/* rxdata_key_idx =( ((iv[3])>>6)&0x3) ; */
mickey = &psecuritypriv->dot118021XGrprxmickey[prxattrib->key_index].skey[0];
- RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("\n recvframe_chkmic: bcmc key\n"));
/* RTW_INFO("\n recvframe_chkmic: bcmc key psecuritypriv->dot118021XGrpKeyid(%d),pmlmeinfo->key_index(%d) ,recv key_id(%d)\n", */
/* psecuritypriv->dot118021XGrpKeyid,pmlmeinfo->key_index,rxdata_key_idx); */
if (psecuritypriv->binstallGrpkey == _FALSE) {
res = _FAIL;
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("\n recvframe_chkmic:didn't install group key!!!!!!!!!!\n"));
RTW_INFO("\n recvframe_chkmic:didn't install group key!!!!!!!!!!\n");
goto exit;
}
} else {
mickey = &stainfo->dot11tkiprxmickey.skey[0];
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("\n recvframe_chkmic: unicast key\n"));
}
datalen = precvframe->u.hdr.len - prxattrib->hdrlen - prxattrib->iv_len - prxattrib->icv_len - 8; /* icv_len included the mic code */
pframe = precvframe->u.hdr.rx_data;
payload = pframe + prxattrib->hdrlen + prxattrib->iv_len;
- RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("\n prxattrib->iv_len=%d prxattrib->icv_len=%d\n", prxattrib->iv_len, prxattrib->icv_len));
/* rtw_seccalctkipmic(&stainfo->dot11tkiprxmickey.skey[0],pframe,payload, datalen ,&miccode[0],(unsigned char)prxattrib->priority); */ /* care the length of the data */
@@ -543,7 +520,6 @@ sint recvframe_chkmic(_adapter *adapter, union recv_frame *precvframe)
for (i = 0; i < 8; i++) {
if (miccode[i] != *(pframemic + i)) {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("recvframe_chkmic:miccode[%d](%02x) != *(pframemic+%d)(%02x) ", i, miccode[i], i, *(pframemic + i)));
bmic_err = _TRUE;
}
}
@@ -551,28 +527,7 @@ sint recvframe_chkmic(_adapter *adapter, union recv_frame *precvframe)
if (bmic_err == _TRUE) {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("\n *(pframemic-8)-*(pframemic-1)=0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x\n",
- *(pframemic - 8), *(pframemic - 7), *(pframemic - 6), *(pframemic - 5), *(pframemic - 4), *(pframemic - 3), *(pframemic - 2), *(pframemic - 1)));
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("\n *(pframemic-16)-*(pframemic-9)=0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x\n",
- *(pframemic - 16), *(pframemic - 15), *(pframemic - 14), *(pframemic - 13), *(pframemic - 12), *(pframemic - 11), *(pframemic - 10), *(pframemic - 9)));
-
- {
- uint i;
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("\n ======demp packet (len=%d)======\n", precvframe->u.hdr.len));
- for (i = 0; i < precvframe->u.hdr.len; i = i + 8) {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x",
- *(precvframe->u.hdr.rx_data + i), *(precvframe->u.hdr.rx_data + i + 1),
- *(precvframe->u.hdr.rx_data + i + 2), *(precvframe->u.hdr.rx_data + i + 3),
- *(precvframe->u.hdr.rx_data + i + 4), *(precvframe->u.hdr.rx_data + i + 5),
- *(precvframe->u.hdr.rx_data + i + 6), *(precvframe->u.hdr.rx_data + i + 7)));
- }
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("\n ======demp packet end [len=%d]======\n", precvframe->u.hdr.len));
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("\n hrdlen=%d,\n", prxattrib->hdrlen));
- }
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("ra=0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x psecuritypriv->binstallGrpkey=%d ",
- prxattrib->ra[0], prxattrib->ra[1], prxattrib->ra[2],
- prxattrib->ra[3], prxattrib->ra[4], prxattrib->ra[5], psecuritypriv->binstallGrpkey));
/* double check key_index for some timing issue , */
/* cannot compare with psecuritypriv->dot118021XGrpKeyid also cause timing issue */
@@ -581,10 +536,8 @@ sint recvframe_chkmic(_adapter *adapter, union recv_frame *precvframe)
if ((prxattrib->bdecrypted == _TRUE) && (brpt_micerror == _TRUE)) {
rtw_handle_tkip_mic_err(adapter, stainfo, (u8)IS_MCAST(prxattrib->ra));
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, (" mic error :prxattrib->bdecrypted=%d ", prxattrib->bdecrypted));
RTW_INFO(" mic error :prxattrib->bdecrypted=%d\n", prxattrib->bdecrypted);
} else {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, (" mic error :prxattrib->bdecrypted=%d ", prxattrib->bdecrypted));
RTW_INFO(" mic error :prxattrib->bdecrypted=%d\n", prxattrib->bdecrypted);
}
@@ -594,12 +547,10 @@ sint recvframe_chkmic(_adapter *adapter, union recv_frame *precvframe)
/* mic checked ok */
if ((psecuritypriv->bcheck_grpkey == _FALSE) && (IS_MCAST(prxattrib->ra) == _TRUE)) {
psecuritypriv->bcheck_grpkey = _TRUE;
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("psecuritypriv->bcheck_grpkey =_TRUE"));
}
}
- } else
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("recvframe_chkmic: rtw_get_stainfo==NULL!!!\n"));
+ }
recvframe_pull_tail(precvframe, 8);
@@ -607,7 +558,6 @@ sint recvframe_chkmic(_adapter *adapter, union recv_frame *precvframe)
exit:
- _func_exit_;
return res;
@@ -625,11 +575,9 @@ union recv_frame *decryptor(_adapter *padapter, union recv_frame *precv_frame)
union recv_frame *return_packet = precv_frame;
u32 res = _SUCCESS;
- _func_enter_;
DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt);
- RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("prxstat->decrypted=%x prxattrib->encrypt = 0x%03x\n", prxattrib->bdecrypted, prxattrib->encrypt));
if (prxattrib->encrypt > 0) {
u8 *iv = precv_frame->u.hdr.rx_data + prxattrib->hdrlen;
@@ -652,11 +600,12 @@ union recv_frame *decryptor(_adapter *padapter, union recv_frame *precv_frame)
}
}
- if ((prxattrib->encrypt > 0) && ((prxattrib->bdecrypted == 0) || (psecuritypriv->sw_decrypt == _TRUE))) {
-
-#ifdef CONFIG_CONCURRENT_MODE
- if (!IS_MCAST(prxattrib->ra)) /* bc/mc packets use sw decryption for concurrent mode */
-#endif
+ if (prxattrib->encrypt && !prxattrib->bdecrypted) {
+ if (GetFrameType(get_recvframe_data(precv_frame)) == WIFI_DATA
+ #ifdef CONFIG_CONCURRENT_MODE
+ && !IS_MCAST(prxattrib->ra) /* bc/mc packets may use sw decryption for concurrent mode */
+ #endif
+ )
psecuritypriv->hw_decrypted = _FALSE;
#ifdef DBG_RX_SW_DECRYPTOR
@@ -704,7 +653,6 @@ union recv_frame *decryptor(_adapter *padapter, union recv_frame *precv_frame)
if ((prxstat->icv == 1) && (prxattrib->encrypt != _AES_)) {
psecuritypriv->hw_decrypted = _FALSE;
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("psecuritypriv->hw_decrypted=_FALSE"));
rtw_free_recvframe(precv_frame, &padapter->recvpriv.free_recv_queue);
@@ -738,6 +686,13 @@ union recv_frame *decryptor(_adapter *padapter, union recv_frame *precv_frame)
#endif
}
+ #ifdef CONFIG_RTW_MESH
+ if (res != _FAIL
+ && !prxattrib->amsdu
+ && prxattrib->mesh_ctrl_present)
+ res = rtw_mesh_rx_validate_mctrl_non_amsdu(padapter, precv_frame);
+ #endif
+
if (res == _FAIL) {
rtw_free_recvframe(return_packet, &padapter->recvpriv.free_recv_queue);
return_packet = NULL;
@@ -745,7 +700,6 @@ union recv_frame *decryptor(_adapter *padapter, union recv_frame *precv_frame)
prxattrib->bdecrypted = _TRUE;
/* recvframe_chkmic(adapter, precv_frame); */ /* move to recvframme_defrag function */
- _func_exit_;
return return_packet;
@@ -765,7 +719,6 @@ union recv_frame *portctrl(_adapter *adapter, union recv_frame *precv_frame)
u16 eapol_type = 0x888e;/* for Funia BD's WPA issue */
struct rx_pkt_attrib *pattrib;
- _func_enter_;
pstapriv = &adapter->stapriv;
@@ -780,13 +733,11 @@ union recv_frame *portctrl(_adapter *adapter, union recv_frame *precv_frame)
psta = rtw_get_stainfo(pstapriv, psta_addr);
- RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("########portctrl:adapter->securitypriv.dot11AuthAlgrthm=%d\n", adapter->securitypriv.dot11AuthAlgrthm));
if (auth_alg == dot11AuthAlgrthm_8021X) {
if ((psta != NULL) && (psta->ieee8021x_blocked)) {
/* blocked */
/* only accept EAPOL frame */
- RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("########portctrl:psta->ieee8021x_blocked==1\n"));
prtnframe = precv_frame;
@@ -805,117 +756,163 @@ union recv_frame *portctrl(_adapter *adapter, union recv_frame *precv_frame)
} else {
/* allowed */
/* check decryption status, and decrypt the frame if needed */
- RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("########portctrl:psta->ieee8021x_blocked==0\n"));
- RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("portctrl:precv_frame->hdr.attrib.privacy=%x\n", precv_frame->u.hdr.attrib.privacy));
- if (pattrib->bdecrypted == 0)
- RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("portctrl:prxstat->decrypted=%x\n", pattrib->bdecrypted));
prtnframe = precv_frame;
/* check is the EAPOL frame or not (Rekey) */
/* if(ether_type == eapol_type){ */
- /* RT_TRACE(_module_rtl871x_recv_c_,_drv_notice_,("########portctrl:ether_type == 0x888e\n")); */
/* check Rekey */
/* prtnframe=precv_frame; */
/* } */
- /* else{ */
- /* RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("########portctrl:ether_type=0x%04x\n", ether_type)); */
- /* } */
}
} else
prtnframe = precv_frame;
- _func_exit_;
return prtnframe;
}
-sint recv_decache(union recv_frame *precv_frame, u8 bretry, struct stainfo_rxcache *prxcache);
-sint recv_decache(union recv_frame *precv_frame, u8 bretry, struct stainfo_rxcache *prxcache)
+sint recv_decache(union recv_frame *precv_frame, u16 *tid_rxseq)
{
- sint tid = precv_frame->u.hdr.attrib.priority;
+ struct sta_info *sta = precv_frame->u.hdr.psta;
+ sint tid = precv_frame->u.hdr.attrib.priority;
u16 seq_ctrl = ((precv_frame->u.hdr.attrib.seq_num & 0xffff) << 4) |
(precv_frame->u.hdr.attrib.frag_num & 0xf);
- _func_enter_;
+ if (tid > 15)
+ return _FAIL;
+
+ if (seq_ctrl == tid_rxseq[tid]) {
+ /* for non-AMPDU case */
+ sta->sta_stats.duplicate_cnt++;
- if (tid > 15) {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ("recv_decache, (tid>15)! seq_ctrl=0x%x, tid=0x%x\n", seq_ctrl, tid));
+ if (sta->sta_stats.duplicate_cnt % 100 == 0)
+ RTW_INFO("%s: tid=%u seq=%d frag=%d\n", __func__
+ , tid, precv_frame->u.hdr.attrib.seq_num
+ , precv_frame->u.hdr.attrib.frag_num);
return _FAIL;
}
- if (1) { /* if(bretry) */
- if (seq_ctrl == prxcache->tid_rxseq[tid]) {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ("recv_decache, seq_ctrl=0x%x, tid=0x%x, tid_rxseq=0x%x\n", seq_ctrl, tid, prxcache->tid_rxseq[tid]));
+ tid_rxseq[tid] = seq_ctrl;
- return _FAIL;
+ return _SUCCESS;
+}
+
+/* VALID_PN_CHK
+ * Return true when PN is legal, otherwise false.
+ * Legal PN:
+ * 1. If old PN is 0, any PN is legal
+ * 2. PN > old PN
+ */
+#define PN_LESS_CHK(a, b) (((a-b) & 0x800000000000) != 0)
+#define VALID_PN_CHK(new, old) (((old) == 0) || PN_LESS_CHK(old, new))
+#define CCMPH_2_KEYID(ch) (((ch) & 0x00000000c0000000) >> 30)
+sint recv_ucast_pn_decache(union recv_frame *precv_frame);
+sint recv_ucast_pn_decache(union recv_frame *precv_frame)
+{
+ _adapter *padapter = precv_frame->u.hdr.adapter;
+ struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
+ struct sta_info *sta = precv_frame->u.hdr.psta;
+ struct stainfo_rxcache *prxcache = &sta->sta_recvpriv.rxcache;
+ u8 *pdata = precv_frame->u.hdr.rx_data;
+ u32 data_len = precv_frame->u.hdr.len;
+ sint tid = precv_frame->u.hdr.attrib.priority;
+ u64 tmp_iv_hdr = 0;
+ u64 curr_pn = 0, pkt_pn = 0;
+
+ if (tid > 15)
+ return _FAIL;
+
+ if (pattrib->encrypt == _AES_) {
+ tmp_iv_hdr = le64_to_cpu(*(u64*)(pdata + pattrib->hdrlen));
+ pkt_pn = CCMPH_2_PN(tmp_iv_hdr);
+ tmp_iv_hdr = le64_to_cpu(*(u64*)prxcache->iv[tid]);
+ curr_pn = CCMPH_2_PN(tmp_iv_hdr);
+
+ if (!VALID_PN_CHK(pkt_pn, curr_pn)) {
+ /* return _FAIL; */
+ } else {
+ prxcache->last_tid = tid;
+ _rtw_memcpy(prxcache->iv[tid],
+ (pdata + pattrib->hdrlen),
+ sizeof(prxcache->iv[tid]));
}
}
- prxcache->tid_rxseq[tid] = seq_ctrl;
+ return _SUCCESS;
+}
+
+sint recv_bcast_pn_decache(union recv_frame *precv_frame);
+sint recv_bcast_pn_decache(union recv_frame *precv_frame)
+{
+ _adapter *padapter = precv_frame->u.hdr.adapter;
+ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+ struct security_priv *psecuritypriv = &padapter->securitypriv;
+ struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
+ u8 *pdata = precv_frame->u.hdr.rx_data;
+ u32 data_len = precv_frame->u.hdr.len;
+ u64 tmp_iv_hdr = 0;
+ u64 curr_pn = 0, pkt_pn = 0;
+ u8 key_id;
+
+ if ((pattrib->encrypt == _AES_) &&
+ (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)) {
+
+ tmp_iv_hdr = le64_to_cpu(*(u64*)(pdata + pattrib->hdrlen));
+ key_id = CCMPH_2_KEYID(tmp_iv_hdr);
+ pkt_pn = CCMPH_2_PN(tmp_iv_hdr);
+
+ curr_pn = le64_to_cpu(*(u64*)psecuritypriv->iv_seq[key_id]);
+ curr_pn &= 0x0000ffffffffffff;
+
+ if (!VALID_PN_CHK(pkt_pn, curr_pn))
+ return _FAIL;
- _func_exit_;
+ *(u64*)psecuritypriv->iv_seq[key_id] = cpu_to_le64(pkt_pn);
+ }
return _SUCCESS;
-
}
-void process_pwrbit_data(_adapter *padapter, union recv_frame *precv_frame);
-void process_pwrbit_data(_adapter *padapter, union recv_frame *precv_frame)
+void process_pwrbit_data(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *psta)
{
#ifdef CONFIG_AP_MODE
unsigned char pwrbit;
u8 *ptr = precv_frame->u.hdr.rx_data;
struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
struct sta_priv *pstapriv = &padapter->stapriv;
- struct sta_info *psta = NULL;
-
- psta = rtw_get_stainfo(pstapriv, pattrib->src);
pwrbit = GetPwrMgt(ptr);
- if (psta) {
- if (pwrbit) {
- if (!(psta->state & WIFI_SLEEP_STATE)) {
- /* psta->state |= WIFI_SLEEP_STATE; */
- /* pstapriv->sta_dz_bitmap |= BIT(psta->aid); */
-
- stop_sta_xmit(padapter, psta);
-
- /* RTW_INFO("to sleep, sta_dz_bitmap=%x\n", pstapriv->sta_dz_bitmap); */
- }
- } else {
- if (psta->state & WIFI_SLEEP_STATE) {
- /* psta->state ^= WIFI_SLEEP_STATE; */
- /* pstapriv->sta_dz_bitmap &= ~BIT(psta->aid); */
-
- wakeup_sta_to_xmit(padapter, psta);
+ if (pwrbit) {
+ if (!(psta->state & WIFI_SLEEP_STATE)) {
+ /* psta->state |= WIFI_SLEEP_STATE; */
+ /* rtw_tim_map_set(padapter, pstapriv->sta_dz_bitmap, BIT(psta->cmn.aid)); */
- /* RTW_INFO("to wakeup, sta_dz_bitmap=%x\n", pstapriv->sta_dz_bitmap); */
- }
+ stop_sta_xmit(padapter, psta);
+ /* RTW_INFO_DUMP("to sleep, sta_dz_bitmap=", pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len); */
}
+ } else {
+ if (psta->state & WIFI_SLEEP_STATE) {
+ /* psta->state ^= WIFI_SLEEP_STATE; */
+ /* rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, BIT(psta->cmn.aid)); */
+ wakeup_sta_to_xmit(padapter, psta);
+ /* RTW_INFO_DUMP("to wakeup, sta_dz_bitmap=", pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len); */
+ }
}
-
#endif
}
-void process_wmmps_data(_adapter *padapter, union recv_frame *precv_frame);
-void process_wmmps_data(_adapter *padapter, union recv_frame *precv_frame)
+void process_wmmps_data(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *psta)
{
#ifdef CONFIG_AP_MODE
struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
struct sta_priv *pstapriv = &padapter->stapriv;
- struct sta_info *psta = NULL;
-
- psta = rtw_get_stainfo(pstapriv, pattrib->src);
-
- if (!psta)
- return;
#ifdef CONFIG_TDLS
if (!(psta->tdls_sta_state & TDLS_LINKED_STATE)) {
@@ -960,7 +957,7 @@ void process_wmmps_data(_adapter *padapter, union recv_frame *precv_frame)
xmit_delivery_enabled_frames(padapter, psta);
} else {
/* issue one qos null frame with More data bit = 0 and the EOSP bit set (=1) */
- issue_qos_nulldata(padapter, psta->hwaddr, (u16)pattrib->priority, 0, 0);
+ issue_qos_nulldata(padapter, psta->cmn.mac_addr, (u16)pattrib->priority, 0, 0, 0);
}
}
@@ -982,6 +979,9 @@ sint OnTDLS(_adapter *adapter, union recv_frame *precv_frame)
u8 WFA_OUI[3] = { 0x50, 0x6f, 0x9a };
#endif /* CONFIG_WFD */
struct tdls_info *ptdlsinfo = &(adapter->tdlsinfo);
+ u8 *ptr = precv_frame->u.hdr.rx_data;
+ struct sta_priv *pstapriv = &(adapter->stapriv);
+ struct sta_info *ptdls_sta = NULL;
/* point to action field */
paction += pattrib->hdrlen
@@ -999,41 +999,54 @@ sint OnTDLS(_adapter *adapter, union recv_frame *precv_frame)
return ret;
}
- if (ptdlsinfo->tdls_enable == _FALSE) {
+ if (rtw_is_tdls_enabled(adapter) == _FALSE) {
RTW_INFO("recv tdls frame, "
"but tdls haven't enabled\n");
ret = _FAIL;
return ret;
}
+ ptdls_sta = rtw_get_stainfo(pstapriv, get_sa(ptr));
+ if (ptdls_sta == NULL) {
+ switch (*paction) {
+ case TDLS_SETUP_REQUEST:
+ case TDLS_DISCOVERY_REQUEST:
+ break;
+ default:
+ RTW_INFO("[TDLS] %s - Direct Link Peer = "MAC_FMT" not found for action = %d\n", __func__, MAC_ARG(get_sa(ptr)), *paction);
+ ret = _FAIL;
+ goto exit;
+ }
+ }
+
switch (*paction) {
case TDLS_SETUP_REQUEST:
- ret = On_TDLS_Setup_Req(adapter, precv_frame);
+ ret = On_TDLS_Setup_Req(adapter, precv_frame, ptdls_sta);
break;
case TDLS_SETUP_RESPONSE:
- ret = On_TDLS_Setup_Rsp(adapter, precv_frame);
+ ret = On_TDLS_Setup_Rsp(adapter, precv_frame, ptdls_sta);
break;
case TDLS_SETUP_CONFIRM:
- ret = On_TDLS_Setup_Cfm(adapter, precv_frame);
+ ret = On_TDLS_Setup_Cfm(adapter, precv_frame, ptdls_sta);
break;
case TDLS_TEARDOWN:
- ret = On_TDLS_Teardown(adapter, precv_frame);
+ ret = On_TDLS_Teardown(adapter, precv_frame, ptdls_sta);
break;
case TDLS_DISCOVERY_REQUEST:
ret = On_TDLS_Dis_Req(adapter, precv_frame);
break;
case TDLS_PEER_TRAFFIC_INDICATION:
- ret = On_TDLS_Peer_Traffic_Indication(adapter, precv_frame);
+ ret = On_TDLS_Peer_Traffic_Indication(adapter, precv_frame, ptdls_sta);
break;
case TDLS_PEER_TRAFFIC_RESPONSE:
- ret = On_TDLS_Peer_Traffic_Rsp(adapter, precv_frame);
+ ret = On_TDLS_Peer_Traffic_Rsp(adapter, precv_frame, ptdls_sta);
break;
#ifdef CONFIG_TDLS_CH_SW
case TDLS_CHANNEL_SWITCH_REQUEST:
- ret = On_TDLS_Ch_Switch_Req(adapter, precv_frame);
+ ret = On_TDLS_Ch_Switch_Req(adapter, precv_frame, ptdls_sta);
break;
case TDLS_CHANNEL_SWITCH_RESPONSE:
- ret = On_TDLS_Ch_Switch_Rsp(adapter, precv_frame);
+ ret = On_TDLS_Ch_Switch_Rsp(adapter, precv_frame, ptdls_sta);
break;
#endif
#ifdef CONFIG_WFD
@@ -1068,7 +1081,6 @@ sint OnTDLS(_adapter *adapter, union recv_frame *precv_frame)
}
#endif /* CONFIG_TDLS */
-void count_rx_stats(_adapter *padapter, union recv_frame *prframe, struct sta_info *sta);
void count_rx_stats(_adapter *padapter, union recv_frame *prframe, struct sta_info *sta)
{
int sz;
@@ -1093,25 +1105,29 @@ void count_rx_stats(_adapter *padapter, union recv_frame *prframe, struct sta_in
psta = prframe->u.hdr.psta;
if (psta) {
+ u8 is_ra_bmc = IS_MCAST(pattrib->ra);
+
pstats = &psta->sta_stats;
+ pstats->last_rx_time = rtw_get_current_time();
pstats->rx_data_pkts++;
pstats->rx_bytes += sz;
+ if (is_broadcast_mac_addr(pattrib->ra)) {
+ pstats->rx_data_bc_pkts++;
+ pstats->rx_bc_bytes += sz;
+ } else if (is_ra_bmc) {
+ pstats->rx_data_mc_pkts++;
+ pstats->rx_mc_bytes += sz;
+ }
- /*record rx packets for every tid*/
- pstats->rx_data_qos_pkts[pattrib->priority]++;
-
-#ifdef CONFIG_TDLS
- if (psta->tdls_sta_state & TDLS_LINKED_STATE) {
- struct sta_info *pap_sta = NULL;
- pap_sta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv));
- if (pap_sta) {
- pstats = &pap_sta->sta_stats;
- pstats->rx_data_pkts++;
- pstats->rx_bytes += sz;
- }
+ if (!is_ra_bmc) {
+ pstats->rxratecnt[pattrib->data_rate]++;
+ /*record rx packets for every tid*/
+ pstats->rx_data_qos_pkts[pattrib->priority]++;
}
-#endif /* CONFIG_TDLS */
+#ifdef CONFIG_DYNAMIC_SOML
+ rtw_dyn_soml_byte_update(padapter, pattrib->data_rate, sz);
+#endif
}
#ifdef CONFIG_CHECK_LEAVE_LPS
@@ -1120,11 +1136,6 @@ void count_rx_stats(_adapter *padapter, union recv_frame *prframe, struct sta_in
}
-sint sta2sta_data_frame(
- _adapter *adapter,
- union recv_frame *precv_frame,
- struct sta_info **psta
-);
sint sta2sta_data_frame(
_adapter *adapter,
union recv_frame *precv_frame,
@@ -1138,7 +1149,7 @@ sint sta2sta_data_frame(
struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
u8 *mybssid = get_bssid(pmlmepriv);
u8 *myhwaddr = adapter_mac_addr(adapter);
- u8 *sta_addr = NULL;
+ u8 *sta_addr = pattrib->ta;
sint bmcast = IS_MCAST(pattrib->dst);
#ifdef CONFIG_TDLS
@@ -1152,7 +1163,6 @@ sint sta2sta_data_frame(
u8 *pframe_body = psnap_type + 2 + 1;
#endif
- _func_enter_;
/* RTW_INFO("[%s] %d, seqnum:%d\n", __FUNCTION__, __LINE__, pattrib->seq_num); */
@@ -1161,7 +1171,6 @@ sint sta2sta_data_frame(
/* filter packets that SA is myself or multicast or broadcast */
if (_rtw_memcmp(myhwaddr, pattrib->src, ETH_ALEN)) {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, (" SA==myself\n"));
ret = _FAIL;
goto exit;
}
@@ -1178,14 +1187,12 @@ sint sta2sta_data_frame(
goto exit;
}
- sta_addr = pattrib->src;
-
} else if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) {
#ifdef CONFIG_TDLS
/* direct link data transfer */
if (ptdlsinfo->link_established == _TRUE) {
- ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->src);
+ *psta = ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->ta);
if (ptdls_sta == NULL) {
ret = _FAIL;
goto exit;
@@ -1220,10 +1227,10 @@ sint sta2sta_data_frame(
#endif
/* process UAPSD tdls sta */
- process_pwrbit_data(adapter, precv_frame);
+ process_pwrbit_data(adapter, precv_frame, ptdls_sta);
/* if NULL-frame, check pwrbit */
- if ((GetFrameSubType(ptr) & WIFI_DATA_NULL) == WIFI_DATA_NULL) {
+ if ((get_frame_sub_type(ptr) & WIFI_DATA_NULL) == WIFI_DATA_NULL) {
/* NULL-frame with pwrbit=1, buffer_STA should buffer frames for sleep_STA */
if (GetPwrMgt(ptr)) {
/* it would be triggered when we are off channel and receiving NULL DATA */
@@ -1245,26 +1252,20 @@ sint sta2sta_data_frame(
goto exit;
}
- if ((GetFrameSubType(ptr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE)
- process_wmmps_data(adapter, precv_frame);
+ if ((get_frame_sub_type(ptr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE)
+ process_wmmps_data(adapter, precv_frame, ptdls_sta);
ptdls_sta->tdls_sta_state &= ~(TDLS_WAIT_PTR_STATE);
}
-
- sta_addr = pattrib->src;
-
} else
#endif /* CONFIG_TDLS */
{
/* For Station mode, sa and bssid should always be BSSID, and DA is my mac-address */
if (!_rtw_memcmp(pattrib->bssid, pattrib->src, ETH_ALEN)) {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("bssid != TA under STATION_MODE; drop pkt\n"));
ret = _FAIL;
goto exit;
}
-
- sta_addr = pattrib->bssid;
}
} else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) {
@@ -1280,13 +1281,11 @@ sint sta2sta_data_frame(
ret = _FAIL;
goto exit;
}
-
- sta_addr = pattrib->src;
}
} else if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) {
_rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN);
- _rtw_memcpy(pattrib->src, GetAddr2Ptr(ptr), ETH_ALEN);
+ _rtw_memcpy(pattrib->src, get_addr2_ptr(ptr), ETH_ALEN);
_rtw_memcpy(pattrib->bssid, GetAddr3Ptr(ptr), ETH_ALEN);
_rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);
_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
@@ -1295,20 +1294,12 @@ sint sta2sta_data_frame(
} else
ret = _FAIL;
-
-
- if (bmcast)
- *psta = rtw_get_bcmc_stainfo(adapter);
- else
- *psta = rtw_get_stainfo(pstapriv, sta_addr); /* get ap_info */
-
#ifdef CONFIG_TDLS
- if (ptdls_sta != NULL)
- *psta = ptdls_sta;
-#endif /* CONFIG_TDLS */
+ if (ptdls_sta == NULL)
+#endif
+ *psta = rtw_get_stainfo(pstapriv, sta_addr);
if (*psta == NULL) {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("can't get psta under sta2sta_data_frame ; drop pkt\n"));
#ifdef CONFIG_MP_INCLUDED
if (adapter->registrypriv.mp_mode == 1) {
if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE)
@@ -1320,15 +1311,10 @@ sint sta2sta_data_frame(
}
exit:
- _func_exit_;
return ret;
}
-sint ap2sta_data_frame(
- _adapter *adapter,
- union recv_frame *precv_frame,
- struct sta_info **psta);
sint ap2sta_data_frame(
_adapter *adapter,
union recv_frame *precv_frame,
@@ -1343,7 +1329,6 @@ sint ap2sta_data_frame(
u8 *myhwaddr = adapter_mac_addr(adapter);
sint bmcast = IS_MCAST(pattrib->dst);
- _func_enter_;
if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
&& (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE
@@ -1352,22 +1337,20 @@ sint ap2sta_data_frame(
/* filter packets that SA is myself or multicast or broadcast */
if (_rtw_memcmp(myhwaddr, pattrib->src, ETH_ALEN)) {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, (" SA==myself\n"));
-#ifdef DBG_RX_DROP_FRAME
- RTW_INFO("DBG_RX_DROP_FRAME %s SA="MAC_FMT", myhwaddr="MAC_FMT"\n",
- __FUNCTION__, MAC_ARG(pattrib->src), MAC_ARG(myhwaddr));
-#endif
+ #ifdef DBG_RX_DROP_FRAME
+ RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" SA="MAC_FMT", myhwaddr="MAC_FMT"\n"
+ , FUNC_ADPT_ARG(adapter), MAC_ARG(pattrib->src), MAC_ARG(myhwaddr));
+ #endif
ret = _FAIL;
goto exit;
}
/* da should be for me */
if ((!_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN)) && (!bmcast)) {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_info_,
- (" ap2sta_data_frame: compare DA fail; DA="MAC_FMT"\n", MAC_ARG(pattrib->dst)));
-#ifdef DBG_RX_DROP_FRAME
- RTW_INFO("DBG_RX_DROP_FRAME %s DA="MAC_FMT"\n", __func__, MAC_ARG(pattrib->dst));
-#endif
+ #ifdef DBG_RX_DROP_FRAME
+ RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" DA="MAC_FMT"\n"
+ , FUNC_ADPT_ARG(adapter), MAC_ARG(pattrib->dst));
+ #endif
ret = _FAIL;
goto exit;
}
@@ -1377,13 +1360,10 @@ sint ap2sta_data_frame(
if (_rtw_memcmp(pattrib->bssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) ||
_rtw_memcmp(mybssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) ||
(!_rtw_memcmp(pattrib->bssid, mybssid, ETH_ALEN))) {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_info_,
- (" ap2sta_data_frame: compare BSSID fail ; BSSID="MAC_FMT"\n", MAC_ARG(pattrib->bssid)));
- RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("mybssid="MAC_FMT"\n", MAC_ARG(mybssid)));
-#ifdef DBG_RX_DROP_FRAME
- RTW_INFO("DBG_RX_DROP_FRAME %s BSSID="MAC_FMT", mybssid="MAC_FMT"\n",
- __func__, MAC_ARG(pattrib->bssid), MAC_ARG(mybssid));
-#endif
+ #ifdef DBG_RX_DROP_FRAME
+ RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" BSSID="MAC_FMT", mybssid="MAC_FMT"\n"
+ , FUNC_ADPT_ARG(adapter), MAC_ARG(pattrib->bssid), MAC_ARG(mybssid));
+ #endif
if (!bmcast) {
RTW_INFO(ADPT_FMT" -issue_deauth to the nonassociated ap=" MAC_FMT " for the reason(7)\n", ADPT_ARG(adapter), MAC_ARG(pattrib->bssid));
@@ -1394,24 +1374,21 @@ sint ap2sta_data_frame(
goto exit;
}
- if (bmcast)
- *psta = rtw_get_bcmc_stainfo(adapter);
- else
- *psta = rtw_get_stainfo(pstapriv, pattrib->bssid); /* get ap_info */
-
+ *psta = rtw_get_stainfo(pstapriv, pattrib->ta);
if (*psta == NULL) {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("ap2sta: can't get psta under STATION_MODE ; drop pkt\n"));
-#ifdef DBG_RX_DROP_FRAME
- RTW_INFO("DBG_RX_DROP_FRAME %s can't get psta under STATION_MODE ; drop pkt\n", __FUNCTION__);
-#endif
+ #ifdef DBG_RX_DROP_FRAME
+ RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" can't get psta under STATION_MODE ; drop pkt\n"
+ , FUNC_ADPT_ARG(adapter));
+ #endif
ret = _FAIL;
goto exit;
}
- if ((GetFrameSubType(ptr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE) {
+ /*if ((get_frame_sub_type(ptr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE) {
}
+ */
- if (GetFrameSubType(ptr) & BIT(6)) {
+ if (get_frame_sub_type(ptr) & BIT(6)) {
/* No data, will not indicate to upper layer, temporily count it here */
count_rx_stats(adapter, precv_frame, *psta);
ret = RTW_RX_HANDLED;
@@ -1421,22 +1398,18 @@ sint ap2sta_data_frame(
} else if ((check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) &&
(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)) {
_rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN);
- _rtw_memcpy(pattrib->src, GetAddr2Ptr(ptr), ETH_ALEN);
+ _rtw_memcpy(pattrib->src, get_addr2_ptr(ptr), ETH_ALEN);
_rtw_memcpy(pattrib->bssid, GetAddr3Ptr(ptr), ETH_ALEN);
_rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);
_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
- /* */
- if (adapter->mppriv.bRTWSmbCfg == _FALSE)
- _rtw_memcpy(pattrib->bssid, mybssid, ETH_ALEN);
-
*psta = rtw_get_stainfo(pstapriv, pattrib->bssid); /* get sta_info */
if (*psta == NULL) {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("can't get psta under MP_MODE ; drop pkt\n"));
-#ifdef DBG_RX_DROP_FRAME
- RTW_INFO("DBG_RX_DROP_FRAME %s can't get psta under WIFI_MP_STATE ; drop pkt\n", __FUNCTION__);
-#endif
+ #ifdef DBG_RX_DROP_FRAME
+ RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" can't get psta under WIFI_MP_STATE ; drop pkt\n"
+ , FUNC_ADPT_ARG(adapter));
+ #endif
ret = _FAIL;
goto exit;
}
@@ -1448,11 +1421,11 @@ sint ap2sta_data_frame(
goto exit;
} else {
if (_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN) && (!bmcast)) {
- *psta = rtw_get_stainfo(pstapriv, pattrib->bssid); /* get sta_info */
+ *psta = rtw_get_stainfo(pstapriv, pattrib->ta);
if (*psta == NULL) {
/* for AP multicast issue , modify by yiwei */
- static u32 send_issue_deauth_time = 0;
+ static systime send_issue_deauth_time = 0;
/* RTW_INFO("After send deauth , %u ms has elapsed.\n", rtw_get_passing_time_ms(send_issue_deauth_time)); */
@@ -1467,23 +1440,19 @@ sint ap2sta_data_frame(
}
ret = _FAIL;
-#ifdef DBG_RX_DROP_FRAME
- RTW_INFO("DBG_RX_DROP_FRAME %s fw_state:0x%x\n", __FUNCTION__, get_fwstate(pmlmepriv));
-#endif
+ #ifdef DBG_RX_DROP_FRAME
+ RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" fw_state:0x%x\n"
+ , FUNC_ADPT_ARG(adapter), get_fwstate(pmlmepriv));
+ #endif
}
exit:
- _func_exit_;
return ret;
}
-sint sta2ap_data_frame(
- _adapter *adapter,
- union recv_frame *precv_frame,
- struct sta_info **psta);
sint sta2ap_data_frame(
_adapter *adapter,
union recv_frame *precv_frame,
@@ -1496,7 +1465,6 @@ sint sta2ap_data_frame(
unsigned char *mybssid = get_bssid(pmlmepriv);
sint ret = _SUCCESS;
- _func_enter_;
if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) {
/* For AP mode, RA=BSSID, TX=STA(SRC_ADDR), A3=DST_ADDR */
@@ -1505,17 +1473,16 @@ sint sta2ap_data_frame(
goto exit;
}
- *psta = rtw_get_stainfo(pstapriv, pattrib->src);
+ *psta = rtw_get_stainfo(pstapriv, pattrib->ta);
if (*psta == NULL) {
-#ifdef CONFIG_DFS_MASTER
+ #ifdef CONFIG_DFS_MASTER
struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
/* prevent RX tasklet blocks cmd_thread */
if (rfctl->radar_detected == 1)
goto bypass_deauth7;
-#endif
+ #endif
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("can't get psta under AP_MODE; drop pkt\n"));
RTW_INFO("issue_deauth to sta=" MAC_FMT " for the reason(7)\n", MAC_ARG(pattrib->src));
issue_deauth(adapter, pattrib->src, WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA);
@@ -1527,12 +1494,12 @@ sint sta2ap_data_frame(
goto exit;
}
- process_pwrbit_data(adapter, precv_frame);
+ process_pwrbit_data(adapter, precv_frame, *psta);
- if ((GetFrameSubType(ptr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE)
- process_wmmps_data(adapter, precv_frame);
+ if ((get_frame_sub_type(ptr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE)
+ process_wmmps_data(adapter, precv_frame, *psta);
- if (GetFrameSubType(ptr) & BIT(6)) {
+ if (get_frame_sub_type(ptr) & BIT(6)) {
/* No data, will not indicate to upper layer, temporily count it here */
count_rx_stats(adapter, precv_frame, *psta);
ret = RTW_RX_HANDLED;
@@ -1542,20 +1509,18 @@ sint sta2ap_data_frame(
(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)) {
/* RTW_INFO("%s ,in WIFI_MP_STATE\n",__func__); */
_rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN);
- _rtw_memcpy(pattrib->src, GetAddr2Ptr(ptr), ETH_ALEN);
+ _rtw_memcpy(pattrib->src, get_addr2_ptr(ptr), ETH_ALEN);
_rtw_memcpy(pattrib->bssid, GetAddr3Ptr(ptr), ETH_ALEN);
_rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);
_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
- /* */
- if (adapter->mppriv.bRTWSmbCfg == _FALSE)
- _rtw_memcpy(pattrib->bssid, mybssid, ETH_ALEN);
+
*psta = rtw_get_stainfo(pstapriv, pattrib->bssid); /* get sta_info */
if (*psta == NULL) {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("can't get psta under MP_MODE ; drop pkt\n"));
-#ifdef DBG_RX_DROP_FRAME
- RTW_INFO("DBG_RX_DROP_FRAME %s can't get psta under WIFI_MP_STATE ; drop pkt\n", __FUNCTION__);
-#endif
+ #ifdef DBG_RX_DROP_FRAME
+ RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" can't get psta under WIFI_MP_STATE ; drop pkt\n"
+ , FUNC_ADPT_ARG(adapter));
+ #endif
ret = _FAIL;
goto exit;
}
@@ -1574,7 +1539,6 @@ sint sta2ap_data_frame(
exit:
- _func_exit_;
return ret;
@@ -1598,21 +1562,22 @@ sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame)
if (!_rtw_memcmp(GetAddr1Ptr(pframe), adapter_mac_addr(padapter), ETH_ALEN))
return _FAIL;
- psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe));
+ psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
if (psta == NULL)
return _FAIL;
/* for rx pkt statistics */
+ psta->sta_stats.last_rx_time = rtw_get_current_time();
psta->sta_stats.rx_ctrl_pkts++;
/* only handle ps-poll */
- if (GetFrameSubType(pframe) == WIFI_PSPOLL) {
+ if (get_frame_sub_type(pframe) == WIFI_PSPOLL) {
#ifdef CONFIG_AP_MODE
u16 aid;
u8 wmmps_ac = 0;
aid = GetAid(pframe);
- if (psta->aid != aid)
+ if (psta->cmn.aid != aid)
return _FAIL;
switch (pattrib->priority) {
@@ -1644,7 +1609,7 @@ sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame)
psta->state ^= WIFI_STA_ALIVE_CHK_STATE;
}
- if ((psta->state & WIFI_SLEEP_STATE) && (pstapriv->sta_dz_bitmap & BIT(psta->aid))) {
+ if ((psta->state & WIFI_SLEEP_STATE) && (rtw_tim_map_is_set(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid))) {
_irqL irqL;
_list *xmitframe_plist, *xmitframe_phead;
struct xmit_frame *pxmitframe = NULL;
@@ -1672,7 +1637,8 @@ sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame)
pxmitframe->attrib.triggered = 1;
- /* RTW_INFO("handling ps-poll, q_len=%d, tim=%x\n", psta->sleepq_len, pstapriv->tim_bitmap); */
+ /* RTW_INFO("handling ps-poll, q_len=%d\n", psta->sleepq_len); */
+ /* RTW_INFO_DUMP("handling, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */
#if 0
_exit_critical_bh(&psta->sleep_q.lock, &irqL);
@@ -1683,9 +1649,10 @@ sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame)
rtw_hal_xmitframe_enqueue(padapter, pxmitframe);
if (psta->sleepq_len == 0) {
- pstapriv->tim_bitmap &= ~BIT(psta->aid);
+ rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid);
- /* RTW_INFO("after handling ps-poll, tim=%x\n", pstapriv->tim_bitmap); */
+ /* RTW_INFO("after handling ps-poll\n"); */
+ /* RTW_INFO_DUMP("after handling, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */
/* upate BCN for TIM IE */
/* update_BCNTIM(padapter); */
@@ -1700,18 +1667,18 @@ sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame)
_exit_critical_bh(&pxmitpriv->lock, &irqL);
/* RTW_INFO("no buffered packets to xmit\n"); */
- if (pstapriv->tim_bitmap & BIT(psta->aid)) {
+ if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid)) {
if (psta->sleepq_len == 0) {
RTW_INFO("no buffered packets to xmit\n");
/* issue nulldata with More data bit = 0 to indicate we have no buffered packets */
- issue_nulldata_in_interrupt(padapter, psta->hwaddr, 0);
+ issue_nulldata(padapter, psta->cmn.mac_addr, 0, 0, 0);
} else {
RTW_INFO("error!psta->sleepq_len=%d\n", psta->sleepq_len);
psta->sleepq_len = 0;
}
- pstapriv->tim_bitmap &= ~BIT(psta->aid);
+ rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid);
/* upate BCN for TIM IE */
/* update_BCNTIM(padapter); */
@@ -1720,59 +1687,284 @@ sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame)
}
}
#endif /* CONFIG_AP_MODE */
- } else if (GetFrameSubType(pframe) == WIFI_NDPA) {
+ } else if (get_frame_sub_type(pframe) == WIFI_NDPA) {
#ifdef CONFIG_BEAMFORMING
- beamforming_get_ndpa_frame(padapter, precv_frame);
+ rtw_beamforming_get_ndpa_frame(padapter, precv_frame);
#endif/*CONFIG_BEAMFORMING*/
+ } else if (get_frame_sub_type(pframe) == WIFI_BAR) {
+ rtw_process_bar_frame(padapter, precv_frame);
}
return _FAIL;
}
-union recv_frame *recvframe_chk_defrag(PADAPTER padapter, union recv_frame *precv_frame);
-sint validate_recv_mgnt_frame(PADAPTER padapter, union recv_frame *precv_frame);
-sint validate_recv_mgnt_frame(PADAPTER padapter, union recv_frame *precv_frame)
+#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)
+static sint validate_mgmt_protect(_adapter *adapter, union recv_frame *precv_frame)
{
- /* struct mlme_priv *pmlmepriv = &adapter->mlmepriv; */
+#define DBG_VALIDATE_MGMT_PROTECT 0
+#define DBG_VALIDATE_MGMT_DEC 0
- RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("+validate_recv_mgnt_frame\n"));
+ struct security_priv *sec = &adapter->securitypriv;
+ struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
+ struct sta_info *psta = precv_frame->u.hdr.psta;
+ u8 *ptr;
+ u8 type;
+ u8 subtype;
+ u8 is_bmc;
+ u8 category = 0xFF;
-#if 0
- if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) {
-#ifdef CONFIG_NATIVEAP_MLME
- mgt_dispatcher(padapter, precv_frame);
-#else
- rtw_hostapd_mlme_rx(padapter, precv_frame);
+#ifdef CONFIG_IEEE80211W
+ const u8 *igtk;
+ u16 igtk_id;
+ u64* ipn;
#endif
+
+ u8 *mgmt_DATA;
+ u32 data_len = 0;
+
+ sint ret;
+
+#ifdef CONFIG_RTW_MESH
+ if (MLME_IS_MESH(adapter)) {
+ if (!adapter->mesh_info.mesh_auth_id)
+ return pattrib->privacy ? _FAIL : _SUCCESS;
} else
- mgt_dispatcher(padapter, precv_frame);
#endif
-
- precv_frame = recvframe_chk_defrag(padapter, precv_frame);
- if (precv_frame == NULL) {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ("%s: fragment packet\n", __FUNCTION__));
+ if (SEC_IS_BIP_KEY_INSTALLED(sec) == _FALSE)
return _SUCCESS;
+
+ ptr = precv_frame->u.hdr.rx_data;
+ type = GetFrameType(ptr);
+ subtype = get_frame_sub_type(ptr); /* bit(7)~bit(2) */
+ is_bmc = IS_MCAST(GetAddr1Ptr(ptr));
+
+#if DBG_VALIDATE_MGMT_PROTECT
+ if (subtype == WIFI_DEAUTH) {
+ RTW_INFO(FUNC_ADPT_FMT" bmc:%u, deauth, privacy:%u, encrypt:%u, bdecrypted:%u\n"
+ , FUNC_ADPT_ARG(adapter)
+ , is_bmc, pattrib->privacy, pattrib->encrypt, pattrib->bdecrypted);
+ } else if (subtype == WIFI_DISASSOC) {
+ RTW_INFO(FUNC_ADPT_FMT" bmc:%u, disassoc, privacy:%u, encrypt:%u, bdecrypted:%u\n"
+ , FUNC_ADPT_ARG(adapter)
+ , is_bmc, pattrib->privacy, pattrib->encrypt, pattrib->bdecrypted);
+ } if (subtype == WIFI_ACTION) {
+ if (pattrib->privacy) {
+ RTW_INFO(FUNC_ADPT_FMT" bmc:%u, action(?), privacy:%u, encrypt:%u, bdecrypted:%u\n"
+ , FUNC_ADPT_ARG(adapter)
+ , is_bmc, pattrib->privacy, pattrib->encrypt, pattrib->bdecrypted);
+ } else {
+ RTW_INFO(FUNC_ADPT_FMT" bmc:%u, action(%u), privacy:%u, encrypt:%u, bdecrypted:%u\n"
+ , FUNC_ADPT_ARG(adapter), is_bmc
+ , *(ptr + sizeof(struct rtw_ieee80211_hdr_3addr))
+ , pattrib->privacy, pattrib->encrypt, pattrib->bdecrypted);
+ }
}
+#endif
- {
- /* for rx pkt statistics */
- struct sta_info *psta = rtw_get_stainfo(&padapter->stapriv, GetAddr2Ptr(precv_frame->u.hdr.rx_data));
- if (psta) {
- psta->sta_stats.rx_mgnt_pkts++;
- if (GetFrameSubType(precv_frame->u.hdr.rx_data) == WIFI_BEACON)
- psta->sta_stats.rx_beacon_pkts++;
- else if (GetFrameSubType(precv_frame->u.hdr.rx_data) == WIFI_PROBEREQ)
- psta->sta_stats.rx_probereq_pkts++;
- else if (GetFrameSubType(precv_frame->u.hdr.rx_data) == WIFI_PROBERSP) {
- if (_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(precv_frame->u.hdr.rx_data), ETH_ALEN) == _TRUE)
- psta->sta_stats.rx_probersp_pkts++;
- else if (is_broadcast_mac_addr(GetAddr1Ptr(precv_frame->u.hdr.rx_data))
- || is_multicast_mac_addr(GetAddr1Ptr(precv_frame->u.hdr.rx_data)))
- psta->sta_stats.rx_probersp_bm_pkts++;
- else
- psta->sta_stats.rx_probersp_uo_pkts++;
+ if (!pattrib->privacy) {
+ if (!psta || !(psta->flags & WLAN_STA_MFP)) {
+ /* peer is not MFP capable, no need to check */
+ goto exit;
+ }
+
+ if (subtype == WIFI_ACTION)
+ category = *(ptr + sizeof(struct rtw_ieee80211_hdr_3addr));
+
+ if (is_bmc) {
+ /* broadcast cases */
+ if (subtype == WIFI_ACTION) {
+ if (CATEGORY_IS_GROUP_PRIVACY(category)) {
+ /* drop broadcast group privacy action frame without encryption */
+ #if DBG_VALIDATE_MGMT_PROTECT
+ RTW_INFO(FUNC_ADPT_FMT" broadcast gp action(%u) w/o encrypt\n"
+ , FUNC_ADPT_ARG(adapter), category);
+ #endif
+ goto fail;
+ }
+ if (CATEGORY_IS_ROBUST(category)) {
+ /* broadcast robust action frame need BIP check */
+ goto bip_verify;
+ }
+ }
+ if (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC) {
+ /* broadcast deauth or disassoc frame need BIP check */
+ goto bip_verify;
+ }
+ goto exit;
+
+ } else {
+ /* unicast cases */
+ #ifdef CONFIG_IEEE80211W
+ if (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC) {
+ if (!MLME_IS_MESH(adapter)) {
+ unsigned short reason = le16_to_cpu(*(unsigned short *)(ptr + WLAN_HDR_A3_LEN));
+
+ #if DBG_VALIDATE_MGMT_PROTECT
+ RTW_INFO(FUNC_ADPT_FMT" unicast %s, reason=%d w/o encrypt\n"
+ , FUNC_ADPT_ARG(adapter), subtype == WIFI_DEAUTH ? "deauth" : "disassoc", reason);
+ #endif
+ if (reason == 6 || reason == 7) {
+ /* issue sa query request */
+ issue_action_SA_Query(adapter, psta->cmn.mac_addr, 0, 0, IEEE80211W_RIGHT_KEY);
+ }
+ }
+ goto fail;
+ }
+ #endif
+
+ if (subtype == WIFI_ACTION && CATEGORY_IS_ROBUST(category)) {
+ if (psta->bpairwise_key_installed == _TRUE) {
+ #if DBG_VALIDATE_MGMT_PROTECT
+ RTW_INFO(FUNC_ADPT_FMT" unicast robust action(%d) w/o encrypt\n"
+ , FUNC_ADPT_ARG(adapter), category);
+ #endif
+ goto fail;
+ }
+ }
+ goto exit;
+ }
+
+bip_verify:
+#ifdef CONFIG_IEEE80211W
+ #ifdef CONFIG_RTW_MESH
+ if (MLME_IS_MESH(adapter)) {
+ if (psta->igtk_bmp) {
+ igtk = psta->igtk.skey;
+ igtk_id = psta->igtk_id;
+ ipn = &psta->igtk_pn.val;
+ } else {
+ /* mesh MFP without IGTK */
+ goto exit;
}
+ } else
+ #endif
+ {
+ igtk = sec->dot11wBIPKey[sec->dot11wBIPKeyid].skey;
+ igtk_id = sec->dot11wBIPKeyid;
+ ipn = &sec->dot11wBIPrxpn.val;
+ }
+
+ /* verify BIP MME IE */
+ ret = rtw_BIP_verify(adapter
+ , get_recvframe_data(precv_frame)
+ , get_recvframe_len(precv_frame)
+ , igtk, igtk_id, ipn);
+ if (ret == _FAIL) {
+ /* RTW_INFO("802.11w BIP verify fail\n"); */
+ goto fail;
+
+ } else if (ret == RTW_RX_HANDLED) {
+ #if DBG_VALIDATE_MGMT_PROTECT
+ RTW_INFO(FUNC_ADPT_FMT" none protected packet\n", FUNC_ADPT_ARG(adapter));
+ #endif
+ goto fail;
+ }
+#endif /* CONFIG_IEEE80211W */
+ goto exit;
+ }
+
+ /* cases to decrypt mgmt frame */
+ pattrib->bdecrypted = 0;
+ pattrib->encrypt = _AES_;
+ pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+ /* set iv and icv length */
+ SET_ICE_IV_LEN(pattrib->iv_len, pattrib->icv_len, pattrib->encrypt);
+ _rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN);
+ _rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN);
+
+ /* actual management data frame body */
+ data_len = pattrib->pkt_len - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len;
+ mgmt_DATA = rtw_zmalloc(data_len);
+ if (mgmt_DATA == NULL) {
+ RTW_INFO(FUNC_ADPT_FMT" mgmt allocate fail !!!!!!!!!\n", FUNC_ADPT_ARG(adapter));
+ goto fail;
+ }
+
+#if DBG_VALIDATE_MGMT_DEC
+ /* dump the packet content before decrypt */
+ {
+ int pp;
+
+ printk("pattrib->pktlen = %d =>", pattrib->pkt_len);
+ for (pp = 0; pp < pattrib->pkt_len; pp++)
+ printk(" %02x ", ptr[pp]);
+ printk("\n");
+ }
+#endif
+
+ precv_frame = decryptor(adapter, precv_frame);
+ /* save actual management data frame body */
+ _rtw_memcpy(mgmt_DATA, ptr + pattrib->hdrlen + pattrib->iv_len, data_len);
+ /* overwrite the iv field */
+ _rtw_memcpy(ptr + pattrib->hdrlen, mgmt_DATA, data_len);
+ /* remove the iv and icv length */
+ pattrib->pkt_len = pattrib->pkt_len - pattrib->iv_len - pattrib->icv_len;
+ rtw_mfree(mgmt_DATA, data_len);
+
+#if DBG_VALIDATE_MGMT_DEC
+ /* print packet content after decryption */
+ {
+ int pp;
+
+ printk("after decryption pattrib->pktlen = %d @@=>", pattrib->pkt_len);
+ for (pp = 0; pp < pattrib->pkt_len; pp++)
+ printk(" %02x ", ptr[pp]);
+ printk("\n");
+ }
+#endif
+
+ if (!precv_frame) {
+ #if DBG_VALIDATE_MGMT_PROTECT
+ RTW_INFO(FUNC_ADPT_FMT" mgmt descrypt fail !!!!!!!!!\n", FUNC_ADPT_ARG(adapter));
+ #endif
+ goto fail;
+ }
+
+exit:
+ return _SUCCESS;
+
+fail:
+ return _FAIL;
+
+}
+#endif /* defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) */
+
+union recv_frame *recvframe_chk_defrag(PADAPTER padapter, union recv_frame *precv_frame);
+
+sint validate_recv_mgnt_frame(PADAPTER padapter, union recv_frame *precv_frame)
+{
+ struct sta_info *psta = precv_frame->u.hdr.psta
+ = rtw_get_stainfo(&padapter->stapriv, get_addr2_ptr(precv_frame->u.hdr.rx_data));
+
+#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)
+ if (validate_mgmt_protect(padapter, precv_frame) == _FAIL) {
+ DBG_COUNTER(padapter->rx_logs.core_rx_pre_mgmt_err_80211w);
+ goto exit;
+ }
+#endif
+
+ precv_frame = recvframe_chk_defrag(padapter, precv_frame);
+ if (precv_frame == NULL)
+ return _SUCCESS;
+
+ /* for rx pkt statistics */
+ if (psta) {
+ psta->sta_stats.last_rx_time = rtw_get_current_time();
+ psta->sta_stats.rx_mgnt_pkts++;
+ if (get_frame_sub_type(precv_frame->u.hdr.rx_data) == WIFI_BEACON)
+ psta->sta_stats.rx_beacon_pkts++;
+ else if (get_frame_sub_type(precv_frame->u.hdr.rx_data) == WIFI_PROBEREQ)
+ psta->sta_stats.rx_probereq_pkts++;
+ else if (get_frame_sub_type(precv_frame->u.hdr.rx_data) == WIFI_PROBERSP) {
+ if (_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(precv_frame->u.hdr.rx_data), ETH_ALEN) == _TRUE)
+ psta->sta_stats.rx_probersp_pkts++;
+ else if (is_broadcast_mac_addr(GetAddr1Ptr(precv_frame->u.hdr.rx_data))
+ || is_multicast_mac_addr(GetAddr1Ptr(precv_frame->u.hdr.rx_data)))
+ psta->sta_stats.rx_probersp_bm_pkts++;
+ else
+ psta->sta_stats.rx_probersp_uo_pkts++;
}
}
@@ -1810,8 +2002,7 @@ sint validate_recv_mgnt_frame(PADAPTER padapter, union recv_frame *precv_frame)
case 3:
_rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN);
- _rtw_memcpy(pattrib->ta, GetAddr2Ptr(ptr), ETH_ALEN);
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, (" case 3\n"));
+ _rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN);
break;
default:
@@ -1826,15 +2017,14 @@ sint validate_recv_mgnt_frame(PADAPTER padapter, union recv_frame *precv_frame)
#endif
mgt_dispatcher(padapter, precv_frame);
+exit:
return _SUCCESS;
}
-sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame);
sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame)
{
- u8 bretry;
- u8 *psa, *pda, *pbssid;
+ u8 bretry, a4_shift;
struct sta_info *psta = NULL;
u8 *ptr = precv_frame->u.hdr.rx_data;
struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
@@ -1842,120 +2032,139 @@ sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame)
struct security_priv *psecuritypriv = &adapter->securitypriv;
sint ret = _SUCCESS;
- _func_enter_;
-
bretry = GetRetry(ptr);
- pda = get_da(ptr);
- psa = get_sa(ptr);
- pbssid = get_hdr_bssid(ptr);
+ a4_shift = (pattrib->to_fr_ds == 3) ? ETH_ALEN : 0;
- if (pbssid == NULL) {
-#ifdef DBG_RX_DROP_FRAME
- RTW_INFO("DBG_RX_DROP_FRAME %s pbssid == NULL\n", __func__);
-#endif
- ret = _FAIL;
- goto exit;
- }
-
- _rtw_memcpy(pattrib->dst, pda, ETH_ALEN);
- _rtw_memcpy(pattrib->src, psa, ETH_ALEN);
+ /* some address fields are different when using AMSDU */
+ if (pattrib->qos)
+ pattrib->amsdu = GetAMsdu(ptr + WLAN_HDR_A3_LEN + a4_shift);
+ else
+ pattrib->amsdu = 0;
- _rtw_memcpy(pattrib->bssid, pbssid, ETH_ALEN);
+#ifdef CONFIG_RTW_MESH
+ if (MLME_IS_MESH(adapter)) {
+ ret = rtw_mesh_rx_data_validate_hdr(adapter, precv_frame, &psta);
+ goto pre_validate_status_chk;
+ }
+#endif
switch (pattrib->to_fr_ds) {
case 0:
- _rtw_memcpy(pattrib->ra, pda, ETH_ALEN);
- _rtw_memcpy(pattrib->ta, psa, ETH_ALEN);
+ _rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN);
+ _rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN);
+ _rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN);
+ _rtw_memcpy(pattrib->src, get_addr2_ptr(ptr), ETH_ALEN);
+ _rtw_memcpy(pattrib->bssid, GetAddr3Ptr(ptr), ETH_ALEN);
ret = sta2sta_data_frame(adapter, precv_frame, &psta);
break;
case 1:
- _rtw_memcpy(pattrib->ra, pda, ETH_ALEN);
- _rtw_memcpy(pattrib->ta, pbssid, ETH_ALEN);
+ _rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN);
+ _rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN);
+ _rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN);
+ _rtw_memcpy(pattrib->src, GetAddr3Ptr(ptr), ETH_ALEN);
+ _rtw_memcpy(pattrib->bssid, get_addr2_ptr(ptr), ETH_ALEN);
ret = ap2sta_data_frame(adapter, precv_frame, &psta);
break;
case 2:
- _rtw_memcpy(pattrib->ra, pbssid, ETH_ALEN);
- _rtw_memcpy(pattrib->ta, psa, ETH_ALEN);
+ _rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN);
+ _rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN);
+ _rtw_memcpy(pattrib->dst, GetAddr3Ptr(ptr), ETH_ALEN);
+ _rtw_memcpy(pattrib->src, get_addr2_ptr(ptr), ETH_ALEN);
+ _rtw_memcpy(pattrib->bssid, GetAddr1Ptr(ptr), ETH_ALEN);
ret = sta2ap_data_frame(adapter, precv_frame, &psta);
break;
case 3:
- _rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN);
- _rtw_memcpy(pattrib->ta, GetAddr2Ptr(ptr), ETH_ALEN);
- ret = _FAIL;
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, (" case 3\n"));
- break;
-
default:
+ /* WDS is not supported */
ret = _FAIL;
break;
-
}
+pre_validate_status_chk:
if (ret == _FAIL) {
-#ifdef DBG_RX_DROP_FRAME
- RTW_INFO("DBG_RX_DROP_FRAME %s case:%d, res:%d\n", __FUNCTION__, pattrib->to_fr_ds, ret);
-#endif
+ #ifdef DBG_RX_DROP_FRAME
+ RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" case:%d, res:%d, ra="MAC_FMT", ta="MAC_FMT"\n"
+ , FUNC_ADPT_ARG(adapter), pattrib->to_fr_ds, ret, MAC_ARG(GetAddr1Ptr(ptr)), MAC_ARG(get_addr2_ptr(ptr)));
+ #endif
goto exit;
} else if (ret == RTW_RX_HANDLED)
goto exit;
if (psta == NULL) {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, (" after to_fr_ds_chk; psta==NULL\n"));
-#ifdef DBG_RX_DROP_FRAME
- RTW_INFO("DBG_RX_DROP_FRAME %s psta == NULL\n", __func__);
-#endif
+ #ifdef DBG_RX_DROP_FRAME
+ RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" psta == NULL, ra="MAC_FMT", ta="MAC_FMT"\n"
+ , FUNC_ADPT_ARG(adapter), MAC_ARG(GetAddr1Ptr(ptr)), MAC_ARG(get_addr2_ptr(ptr)));
+ #endif
ret = _FAIL;
goto exit;
}
- /* psta->rssi = prxcmd->rssi; */
- /* psta->signal_quality= prxcmd->sq; */
precv_frame->u.hdr.psta = psta;
-
- pattrib->amsdu = 0;
pattrib->ack_policy = 0;
+
/* parsing QC field */
if (pattrib->qos == 1) {
- pattrib->priority = GetPriority((ptr + 24));
- pattrib->ack_policy = GetAckpolicy((ptr + 24));
- pattrib->amsdu = GetAMsdu((ptr + 24));
- pattrib->hdrlen = pattrib->to_fr_ds == 3 ? 32 : 26;
-
+ pattrib->priority = GetPriority((ptr + WLAN_HDR_A3_LEN + a4_shift)); /* point to Qos field*/
+ pattrib->ack_policy = GetAckpolicy((ptr + WLAN_HDR_A3_LEN + a4_shift));
+ pattrib->hdrlen = WLAN_HDR_A3_QOS_LEN + a4_shift;
if (pattrib->priority != 0 && pattrib->priority != 3)
- adapter->recvpriv.bIsAnyNonBEPkts = _TRUE;
+ adapter->recvpriv.is_any_non_be_pkts = _TRUE;
else
- adapter->recvpriv.bIsAnyNonBEPkts = _FALSE;
+ adapter->recvpriv.is_any_non_be_pkts = _FALSE;
} else {
pattrib->priority = 0;
- pattrib->hdrlen = pattrib->to_fr_ds == 3 ? 30 : 24;
+ pattrib->hdrlen = WLAN_HDR_A3_LEN + a4_shift;
}
if (pattrib->order) /* HT-CTRL 11n */
pattrib->hdrlen += 4;
- precv_frame->u.hdr.preorder_ctrl = &psta->recvreorder_ctrl[pattrib->priority];
-
/* decache, drop duplicate recv packets */
- if (recv_decache(precv_frame, bretry, &psta->sta_recvpriv.rxcache) == _FAIL) {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("decache : drop pkt\n"));
-#ifdef DBG_RX_DROP_FRAME
- RTW_INFO("DBG_RX_DROP_FRAME %s recv_decache return _FAIL\n", __func__);
-#endif
- ret = _FAIL;
- goto exit;
+ if (!IS_MCAST(pattrib->ra)) {
+ precv_frame->u.hdr.preorder_ctrl = &psta->recvreorder_ctrl[pattrib->priority];
+ if (recv_decache(precv_frame, psta->sta_recvpriv.rxcache.tid_rxseq) == _FAIL) {
+ #ifdef DBG_RX_DROP_FRAME
+ RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" recv_decache uc return _FAIL for sta="MAC_FMT"\n"
+ , FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr));
+ #endif
+ ret = _FAIL;
+ goto exit;
+ }
+ if (recv_ucast_pn_decache(precv_frame) == _FAIL) {
+ #ifdef DBG_RX_DROP_FRAME
+ RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" recv_ucast_pn_decache return _FAIL for sta="MAC_FMT"\n"
+ , FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr));
+ #endif
+ ret = _FAIL;
+ goto exit;
+ }
+ } else {
+ precv_frame->u.hdr.preorder_ctrl = NULL;
+ if (recv_decache(precv_frame, psta->sta_recvpriv.bmc_tid_rxseq) == _FAIL) {
+ #ifdef DBG_RX_DROP_FRAME
+ RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" recv_decache bmc return _FAIL for sta="MAC_FMT"\n"
+ , FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr));
+ #endif
+ ret = _FAIL;
+ goto exit;
+ }
+ if (recv_bcast_pn_decache(precv_frame) == _FAIL) {
+ #ifdef DBG_RX_DROP_FRAME
+ RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" recv_bcast_pn_decache return _FAIL for sta="MAC_FMT"\n"
+ , FUNC_ADPT_ARG(adapter), MAC_ARG(psta->cmn.mac_addr));
+ #endif
+ ret = _FAIL;
+ goto exit;
+ }
}
if (pattrib->privacy) {
-
- RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("validate_recv_data_frame:pattrib->privacy=%x\n", pattrib->privacy));
- RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("\n ^^^^^^^^^^^IS_MCAST(pattrib->ra(0x%02x))=%d^^^^^^^^^^^^^^^6\n", pattrib->ra[0], IS_MCAST(pattrib->ra)));
-
#ifdef CONFIG_TDLS
if ((psta->tdls_sta_state & TDLS_LINKED_STATE) && (psta->dot118021XPrivacy == _AES_))
pattrib->encrypt = psta->dot118021XPrivacy;
@@ -1963,7 +2172,6 @@ sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame)
#endif /* CONFIG_TDLS */
GET_ENCRY_ALGO(psecuritypriv, psta, pattrib->encrypt, IS_MCAST(pattrib->ra));
- RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("\n pattrib->encrypt=%d\n", pattrib->encrypt));
SET_ICE_IV_LEN(pattrib->iv_len, pattrib->icv_len, pattrib->encrypt);
} else {
@@ -1971,133 +2179,20 @@ sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame)
pattrib->iv_len = pattrib->icv_len = 0;
}
-exit:
-
- _func_exit_;
+#ifdef CONFIG_RTW_MESH
+ if (!pattrib->amsdu
+ && pattrib->mesh_ctrl_present
+ && (!pattrib->encrypt || pattrib->bdecrypted))
+ ret = rtw_mesh_rx_validate_mctrl_non_amsdu(adapter, precv_frame);
+#endif
+exit:
return ret;
}
-#ifdef CONFIG_IEEE80211W
-static sint validate_80211w_mgmt(_adapter *adapter, union recv_frame *precv_frame)
+static inline void dump_rx_packet(u8 *ptr)
{
- struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
- struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
- u8 *ptr = precv_frame->u.hdr.rx_data;
- struct sta_info *psta;
- struct sta_priv *pstapriv = &adapter->stapriv;
- u8 type;
- u8 subtype;
-
- type = GetFrameType(ptr);
- subtype = GetFrameSubType(ptr); /* bit(7)~bit(2) */
-
- if (adapter->securitypriv.binstallBIPkey == _TRUE) {
- /* unicast management frame decrypt */
- if (pattrib->privacy && !(IS_MCAST(GetAddr1Ptr(ptr))) &&
- (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC || subtype == WIFI_ACTION)) {
- u8 *ppp, *mgmt_DATA;
- u32 data_len = 0;
- ppp = GetAddr2Ptr(ptr);
-
- pattrib->bdecrypted = 0;
- pattrib->encrypt = _AES_;
- pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr);
- /* set iv and icv length */
- SET_ICE_IV_LEN(pattrib->iv_len, pattrib->icv_len, pattrib->encrypt);
- _rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN);
- _rtw_memcpy(pattrib->ta, GetAddr2Ptr(ptr), ETH_ALEN);
- /* actual management data frame body */
- data_len = pattrib->pkt_len - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len;
- mgmt_DATA = rtw_zmalloc(data_len);
- if (mgmt_DATA == NULL) {
- RTW_INFO("%s mgmt allocate fail !!!!!!!!!\n", __FUNCTION__);
- goto validate_80211w_fail;
- }
-#if 0
- /* dump the packet content before decrypt */
- {
- int pp;
- printk("pattrib->pktlen = %d =>", pattrib->pkt_len);
- for (pp = 0; pp < pattrib->pkt_len; pp++)
- printk(" %02x ", ptr[pp]);
- printk("\n");
- }
-#endif
-
- precv_frame = decryptor(adapter, precv_frame);
- /* save actual management data frame body */
- _rtw_memcpy(mgmt_DATA, ptr + pattrib->hdrlen + pattrib->iv_len, data_len);
- /* overwrite the iv field */
- _rtw_memcpy(ptr + pattrib->hdrlen, mgmt_DATA, data_len);
- /* remove the iv and icv length */
- pattrib->pkt_len = pattrib->pkt_len - pattrib->iv_len - pattrib->icv_len;
- rtw_mfree(mgmt_DATA, data_len);
-#if 0
- /* print packet content after decryption */
- {
- int pp;
- printk("after decryption pattrib->pktlen = %d @@=>", pattrib->pkt_len);
- for (pp = 0; pp < pattrib->pkt_len; pp++)
- printk(" %02x ", ptr[pp]);
- printk("\n");
- }
-#endif
- if (!precv_frame) {
- RTW_INFO("%s mgmt descrypt fail !!!!!!!!!\n", __FUNCTION__);
- goto validate_80211w_fail;
- }
- } else if (IS_MCAST(GetAddr1Ptr(ptr)) &&
- (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC)) {
- sint BIP_ret = _SUCCESS;
- /* verify BIP MME IE of broadcast/multicast de-auth/disassoc packet */
- BIP_ret = rtw_BIP_verify(adapter, (u8 *)precv_frame);
- if (BIP_ret == _FAIL) {
- /* RTW_INFO("802.11w BIP verify fail\n"); */
- goto validate_80211w_fail;
- } else if (BIP_ret == RTW_RX_HANDLED) {
- RTW_INFO("802.11w recv none protected packet\n");
- /* drop pkt, don't issue sa query request */
- /* issue_action_SA_Query(adapter, NULL, 0, 0, 0); */
- goto validate_80211w_fail;
- }
- } /* 802.11w protect */
- else {
- psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(ptr));
-
- if (subtype == WIFI_ACTION && psta && psta->bpairwise_key_installed == _TRUE) {
- /* according 802.11-2012 standard, these five types are not robust types */
- if (ptr[WLAN_HDR_A3_LEN] != RTW_WLAN_CATEGORY_PUBLIC &&
- ptr[WLAN_HDR_A3_LEN] != RTW_WLAN_CATEGORY_HT &&
- ptr[WLAN_HDR_A3_LEN] != RTW_WLAN_CATEGORY_UNPROTECTED_WNM &&
- ptr[WLAN_HDR_A3_LEN] != RTW_WLAN_CATEGORY_SELF_PROTECTED &&
- ptr[WLAN_HDR_A3_LEN] != RTW_WLAN_CATEGORY_P2P) {
- RTW_INFO("action frame category=%d should robust\n", ptr[WLAN_HDR_A3_LEN]);
- goto validate_80211w_fail;
- }
- } else if (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC) {
- unsigned short reason;
- reason = le16_to_cpu(*(unsigned short *)(ptr + WLAN_HDR_A3_LEN));
- RTW_INFO("802.11w recv none protected packet, reason=%d\n", reason);
- if (reason == 6 || reason == 7) {
- /* issue sa query request */
- issue_action_SA_Query(adapter, NULL, 0, 0, IEEE80211W_RIGHT_KEY);
- }
- goto validate_80211w_fail;
- }
- }
- }
- return _SUCCESS;
-
-validate_80211w_fail:
- return _FAIL;
-
-}
-#endif /* CONFIG_IEEE80211W */
-
-static inline void dump_rx_packet(u8 *ptr)
-{
- int i;
+ int i;
RTW_INFO("#############################\n");
for (i = 0; i < 64; i = i + 8)
@@ -2118,10 +2213,12 @@ sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame)
sint retval = _SUCCESS;
struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
+ struct recv_priv *precvpriv = &adapter->recvpriv;
u8 *ptr = precv_frame->u.hdr.rx_data;
u8 ver = (unsigned char)(*ptr) & 0x3 ;
#ifdef CONFIG_FIND_BEST_CHANNEL
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
#endif
@@ -2136,13 +2233,12 @@ sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame)
u8 external_len = 0;
#endif
- _func_enter_;
#ifdef CONFIG_FIND_BEST_CHANNEL
if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS) {
- int ch_set_idx = rtw_ch_set_search_ch(pmlmeext->channel_set, rtw_get_oper_ch(adapter));
+ int ch_set_idx = rtw_chset_search_ch(rfctl->channel_set, rtw_get_oper_ch(adapter));
if (ch_set_idx >= 0)
- pmlmeext->channel_set[ch_set_idx].rx_count++;
+ rfctl->channel_set[ch_set_idx].rx_count++;
}
#endif
@@ -2167,14 +2263,13 @@ sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame)
/* add version chk */
if (ver != 0) {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("validate_recv_data_frame fail! (ver!=0)\n"));
retval = _FAIL;
DBG_COUNTER(adapter->rx_logs.core_rx_pre_ver_err);
goto exit;
}
type = GetFrameType(ptr);
- subtype = GetFrameSubType(ptr); /* bit(7)~bit(2) */
+ subtype = get_frame_sub_type(ptr); /* bit(7)~bit(2) */
pattrib->to_fr_ds = get_tofr_ds(ptr);
@@ -2206,17 +2301,8 @@ sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame)
switch (type) {
case WIFI_MGT_TYPE: /* mgnt */
DBG_COUNTER(adapter->rx_logs.core_rx_pre_mgmt);
-#ifdef CONFIG_IEEE80211W
- if (validate_80211w_mgmt(adapter, precv_frame) == _FAIL) {
- retval = _FAIL;
- DBG_COUNTER(adapter->rx_logs.core_rx_pre_mgmt_err_80211w);
- break;
- }
-#endif /* CONFIG_IEEE80211W */
-
retval = validate_recv_mgnt_frame(adapter, precv_frame);
if (retval == _FAIL) {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("validate_recv_mgnt_frame fail\n"));
DBG_COUNTER(adapter->rx_logs.core_rx_pre_mgmt_err);
}
retval = _FAIL; /* only data frame return _SUCCESS */
@@ -2225,7 +2311,6 @@ sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame)
DBG_COUNTER(adapter->rx_logs.core_rx_pre_ctrl);
retval = validate_recv_ctrl_frame(adapter, precv_frame);
if (retval == _FAIL) {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("validate_recv_ctrl_frame fail\n"));
DBG_COUNTER(adapter->rx_logs.core_rx_pre_ctrl_err);
}
retval = _FAIL; /* only data frame return _SUCCESS */
@@ -2252,7 +2337,7 @@ sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame)
}
} else {
- if (rtw_wapi_drop_for_key_absent(adapter, GetAddr2Ptr(ptr))) {
+ if (rtw_wapi_drop_for_key_absent(adapter, get_addr2_ptr(ptr))) {
retval = _FAIL;
WAPI_TRACE(WAPI_RX, "drop for key absent for rx\n");
DBG_COUNTER(adapter->rx_logs.core_rx_pre_data_wapi_key_err);
@@ -2265,39 +2350,38 @@ sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame)
pattrib->qos = (subtype & BIT(7)) ? 1 : 0;
retval = validate_recv_data_frame(adapter, precv_frame);
if (retval == _FAIL) {
- struct recv_priv *precvpriv = &adapter->recvpriv;
- /* RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("validate_recv_data_frame fail\n")); */
- precvpriv->rx_drop++;
+ precvpriv->dbg_rx_drop_count++;
DBG_COUNTER(adapter->rx_logs.core_rx_pre_data_err);
} else if (retval == _SUCCESS) {
-#ifdef DBG_RX_DUMP_EAP
- u8 bDumpRxPkt;
- u16 eth_type;
-
- /* dump eapol */
- rtw_hal_get_def_var(adapter, HAL_DEF_DBG_DUMP_RXPKT, &(bDumpRxPkt));
- /* get ether_type */
- _rtw_memcpy(ð_type, ptr + pattrib->hdrlen + pattrib->iv_len + LLC_HEADER_SIZE, 2);
- eth_type = ntohs((unsigned short) eth_type);
- if ((bDumpRxPkt == 4) && (eth_type == 0x888e))
- dump_rx_packet(ptr);
-#endif
+ #ifdef DBG_RX_DUMP_EAP
+ if (!pattrib->encrypt || pattrib->bdecrypted) {
+ u8 bDumpRxPkt;
+ u16 eth_type;
+
+ /* dump eapol */
+ rtw_hal_get_def_var(adapter, HAL_DEF_DBG_DUMP_RXPKT, &(bDumpRxPkt));
+ /* get ether_type */
+ _rtw_memcpy(ð_type, ptr + pattrib->hdrlen + pattrib->iv_len + RATTRIB_GET_MCTRL_LEN(pattrib) + LLC_HEADER_SIZE, 2);
+ eth_type = ntohs((unsigned short) eth_type);
+ if ((bDumpRxPkt == 4) && (eth_type == 0x888e))
+ dump_rx_packet(ptr);
+ }
+ #endif
} else
DBG_COUNTER(adapter->rx_logs.core_rx_pre_data_handled);
break;
default:
DBG_COUNTER(adapter->rx_logs.core_rx_pre_unknown);
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("validate_recv_data_frame fail! type=0x%x\n", type));
-#ifdef DBG_RX_DROP_FRAME
- RTW_INFO("DBG_RX_DROP_FRAME validate_recv_data_frame fail! type=0x%x\n", type);
-#endif
+ #ifdef DBG_RX_DROP_FRAME
+ RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" fail! type=0x%x\n"
+ , FUNC_ADPT_ARG(adapter), type);
+ #endif
retval = _FAIL;
break;
}
exit:
- _func_exit_;
return retval;
}
@@ -2305,8 +2389,6 @@ sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame)
/* remove the wlanhdr and add the eth_hdr */
#if 1
-
-sint wlanhdr_to_ethhdr(union recv_frame *precvframe);
sint wlanhdr_to_ethhdr(union recv_frame *precvframe)
{
sint rmv_len;
@@ -2322,13 +2404,12 @@ sint wlanhdr_to_ethhdr(union recv_frame *precvframe)
u8 *ptr = get_recvframe_data(precvframe) ; /* point to frame_ctrl field */
struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib;
- _func_enter_;
if (pattrib->encrypt)
recvframe_pull_tail(precvframe, pattrib->icv_len);
- psnap = (struct ieee80211_snap_hdr *)(ptr + pattrib->hdrlen + pattrib->iv_len);
- psnap_type = ptr + pattrib->hdrlen + pattrib->iv_len + SNAP_SIZE;
+ psnap = (struct ieee80211_snap_hdr *)(ptr + pattrib->hdrlen + pattrib->iv_len + RATTRIB_GET_MCTRL_LEN(pattrib));
+ psnap_type = ptr + pattrib->hdrlen + pattrib->iv_len + RATTRIB_GET_MCTRL_LEN(pattrib) + SNAP_SIZE;
/* convert hdr + possible LLC headers into Ethernet header */
/* eth_type = (psnap_type[0] << 8) | psnap_type[1]; */
if ((_rtw_memcmp(psnap, rtw_rfc1042_header, SNAP_SIZE) &&
@@ -2343,46 +2424,14 @@ sint wlanhdr_to_ethhdr(union recv_frame *precvframe)
bsnaphdr = _FALSE;
}
- rmv_len = pattrib->hdrlen + pattrib->iv_len + (bsnaphdr ? SNAP_SIZE : 0);
+ rmv_len = pattrib->hdrlen + pattrib->iv_len + RATTRIB_GET_MCTRL_LEN(pattrib) + (bsnaphdr ? SNAP_SIZE : 0);
len = precvframe->u.hdr.len - rmv_len;
- RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("\n===pattrib->hdrlen: %x, pattrib->iv_len:%x ===\n\n", pattrib->hdrlen, pattrib->iv_len));
_rtw_memcpy(ð_type, ptr + rmv_len, 2);
eth_type = ntohs((unsigned short)eth_type); /* pattrib->ether_type */
pattrib->eth_type = eth_type;
-#ifdef CONFIG_AUTO_AP_MODE
- if (0x8899 == pattrib->eth_type) {
- struct sta_info *psta = precvframe->u.hdr.psta;
-
- RTW_INFO("wlan rx: got eth_type=0x%x\n", pattrib->eth_type);
-
- if (psta && psta->isrc && psta->pid > 0) {
- u16 rx_pid;
-
- rx_pid = *(u16 *)(ptr + rmv_len + 2);
-
- RTW_INFO("wlan rx(pid=0x%x): sta("MAC_FMT") pid=0x%x\n",
- rx_pid, MAC_ARG(psta->hwaddr), psta->pid);
-
- if (rx_pid == psta->pid) {
- int i;
- u16 len = *(u16 *)(ptr + rmv_len + 4);
- /* u16 ctrl_type = *(u16*)(ptr+rmv_len+6); */
-
- /* RTW_INFO("RC: len=0x%x, ctrl_type=0x%x\n", len, ctrl_type); */
- RTW_INFO("RC: len=0x%x\n", len);
-
- for (i = 0; i < len; i++)
- RTW_INFO("0x%x\n", *(ptr + rmv_len + 6 + i));
- /* RTW_INFO("0x%x\n", *(ptr+rmv_len+8+i)); */
-
- RTW_INFO("RC-end\n");
- }
- }
- }
-#endif /* CONFIG_AUTO_AP_MODE */
if ((check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE)) {
ptr += rmv_len ;
@@ -2414,10 +2463,11 @@ sint wlanhdr_to_ethhdr(union recv_frame *precvframe)
len = htons(len);
_rtw_memcpy(ptr + 12, &len, 2);
}
+
+ rtw_rframe_set_os_pkt(precvframe);
}
exiting:
- _func_exit_;
return ret;
}
@@ -2440,7 +2490,6 @@ sint wlanhdr_to_ethhdr(union recv_frame *precvframe)
struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib;
struct _vlan *pvlan = NULL;
- _func_enter_;
psnap = (struct ieee80211_snap_hdr *)(ptr + pattrib->hdrlen + pattrib->iv_len);
psnap_type = ptr + pattrib->hdrlen + pattrib->iv_len + SNAP_SIZE;
@@ -2453,7 +2502,6 @@ sint wlanhdr_to_ethhdr(union recv_frame *precvframe)
else if (_rtw_memcmp(psnap->oui, oui_8021h, WLAN_IEEE_OUI_LEN))
bsnaphdr = _TRUE; /* wlan_pkt_format = WLAN_PKT_FORMAT_SNAP_TUNNEL; */
else {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("drop pkt due to invalid frame format!\n"));
ret = _FAIL;
goto exit;
}
@@ -2462,7 +2510,6 @@ sint wlanhdr_to_ethhdr(union recv_frame *precvframe)
bsnaphdr = _FALSE; /* wlan_pkt_format = WLAN_PKT_FORMAT_OTHERS; */
rmv_len = pattrib->hdrlen + pattrib->iv_len + (bsnaphdr ? SNAP_SIZE : 0);
- RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("===pattrib->hdrlen: %x, pattrib->iv_len:%x ===\n", pattrib->hdrlen, pattrib->iv_len));
if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) {
ptr += rmv_len ;
@@ -2497,10 +2544,6 @@ sint wlanhdr_to_ethhdr(union recv_frame *precvframe)
/* piphdr->tos = tos; */
- /* if (piphdr->protocol == 0x06) */
- /* { */
- /* RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("@@@===recv tcp len:%d @@@===\n", precvframe->u.hdr.len)); */
- /* } */
} else if (eth_type == 0x8712) { /* append rx status for mp test packets */
/* ptr -= 16; */
/* _rtw_memcpy(ptr, get_rxmem(precvframe), 16); */
@@ -2537,7 +2580,6 @@ sint wlanhdr_to_ethhdr(union recv_frame *precvframe)
exit:
- _func_exit_;
return ret;
}
@@ -2614,7 +2656,6 @@ union recv_frame *recvframe_defrag(_adapter *adapter, _queue *defrag_q)
union recv_frame *prframe, *pnextrframe;
_queue *pfree_recv_queue;
- _func_enter_;
curfragnum = 0;
pfree_recv_queue = &adapter->recvpriv.free_recv_queue;
@@ -2688,9 +2729,7 @@ union recv_frame *recvframe_defrag(_adapter *adapter, _queue *defrag_q)
/* free the defrag_q queue and return the prframe */
rtw_free_recvframe_queue(defrag_q, pfree_recv_queue);
- RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("Performance defrag!!!!!\n"));
- _func_exit_;
return prframe;
}
@@ -2708,7 +2747,6 @@ union recv_frame *recvframe_chk_defrag(PADAPTER padapter, union recv_frame *prec
union recv_frame *prtnframe = NULL;
_queue *pfree_recv_queue, *pdefrag_q;
- _func_enter_;
pstapriv = &padapter->stapriv;
@@ -2756,7 +2794,6 @@ union recv_frame *recvframe_chk_defrag(PADAPTER padapter, union recv_frame *prec
rtw_list_insert_tail(&pfhdr->list, phead);
/* _rtw_spinunlock(&pdefrag_q->lock); */
- RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("Enqueuq: ismfrag = %d, fragnum= %d\n", ismfrag, fragnum));
prtnframe = NULL;
@@ -2764,7 +2801,6 @@ union recv_frame *recvframe_chk_defrag(PADAPTER padapter, union recv_frame *prec
/* can't find this ta's defrag_queue, so free this recv_frame */
rtw_free_recvframe(precv_frame, pfree_recv_queue);
prtnframe = NULL;
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("Free because pdefrag_q ==NULL: ismfrag = %d, fragnum= %d\n", ismfrag, fragnum));
}
}
@@ -2779,7 +2815,6 @@ union recv_frame *recvframe_chk_defrag(PADAPTER padapter, union recv_frame *prec
/* _rtw_spinunlock(&pdefrag_q->lock); */
/* call recvframe_defrag to defrag */
- RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("defrag: ismfrag = %d, fragnum= %d\n", ismfrag, fragnum));
precv_frame = recvframe_defrag(padapter, pdefrag_q);
prtnframe = precv_frame;
@@ -2787,7 +2822,6 @@ union recv_frame *recvframe_chk_defrag(PADAPTER padapter, union recv_frame *prec
/* can't find this ta's defrag_queue, so free this recv_frame */
rtw_free_recvframe(precv_frame, pfree_recv_queue);
prtnframe = NULL;
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("Free because pdefrag_q ==NULL: ismfrag = %d, fragnum= %d\n", ismfrag, fragnum));
}
}
@@ -2796,20 +2830,154 @@ union recv_frame *recvframe_chk_defrag(PADAPTER padapter, union recv_frame *prec
if ((prtnframe != NULL) && (prtnframe->u.hdr.attrib.privacy)) {
/* after defrag we must check tkip mic code */
if (recvframe_chkmic(padapter, prtnframe) == _FAIL) {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("recvframe_chkmic(padapter, prtnframe)==_FAIL\n"));
rtw_free_recvframe(prtnframe, pfree_recv_queue);
prtnframe = NULL;
}
}
- _func_exit_;
return prtnframe;
}
+static int rtw_recv_indicatepkt_check(union recv_frame *rframe, u8 *ehdr_pos, u32 pkt_len)
+{
+ _adapter *adapter = rframe->u.hdr.adapter;
+ struct recv_priv *recvpriv = &adapter->recvpriv;
+ struct ethhdr *ehdr = (struct ethhdr *)ehdr_pos;
+ int ret = _FAIL;
+
+#ifdef CONFIG_WAPI_SUPPORT
+ if (rtw_wapi_check_for_drop(adapter, rframe, ehdr_pos)) {
+ #ifdef DBG_RX_DROP_FRAME
+ RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" rtw_wapi_check_for_drop\n"
+ , FUNC_ADPT_ARG(adapter));
+ #endif
+ goto exit;
+ }
+#endif
+
+ if (rframe->u.hdr.psta)
+ rtw_st_ctl_rx(rframe->u.hdr.psta, ehdr_pos);
+
+ if (ntohs(ehdr->h_proto) == 0x888e)
+ RTW_PRINT("recv eapol packet\n");
+
+ if (recvpriv->sink_udpport > 0)
+ rtw_sink_rtp_seq_dbg(adapter, ehdr_pos);
+
+#ifdef DBG_UDP_PKT_LOSE_11AC
+ #define PAYLOAD_LEN_LOC_OF_IP_HDR 0x10 /*ethernet payload length location of ip header (DA + SA+eth_type+(version&hdr_len)) */
+
+ if (ntohs(ehdr->h_proto) == ETH_P_ARP) {
+ /* ARP Payload length will be 42bytes or 42+18(tailer)=60bytes*/
+ if (pkt_len != 42 && pkt_len != 60)
+ RTW_INFO("Error !!%s,ARP Payload length %u not correct\n" , __func__ , pkt_len);
+ } else if (ntohs(ehdr->h_proto) == ETH_P_IP) {
+ if (be16_to_cpu(*((u16 *)(ehdr_pos + PAYLOAD_LEN_LOC_OF_IP_HDR))) != (pkt_len) - ETH_HLEN) {
+ RTW_INFO("Error !!%s,Payload length not correct\n" , __func__);
+ RTW_INFO("%s, IP header describe Total length=%u\n" , __func__ , be16_to_cpu(*((u16 *)(ehdr_pos + PAYLOAD_LEN_LOC_OF_IP_HDR))));
+ RTW_INFO("%s, Pkt real length=%u\n" , __func__ , (pkt_len) - ETH_HLEN);
+ }
+ }
+#endif
+
+#ifdef CONFIG_AUTO_AP_MODE
+ if (ntohs(ehdr->h_proto) == 0x8899)
+ rtw_auto_ap_rx_msg_dump(adapter, rframe, ehdr_pos);
+#endif
+
+ ret = _SUCCESS;
+
+exit:
+ return ret;
+}
+
+static void recv_free_fwd_resource(_adapter *adapter, struct xmit_frame *fwd_frame, _list *b2u_list)
+{
+ struct xmit_priv *xmitpriv = &adapter->xmitpriv;
+
+ if (fwd_frame)
+ rtw_free_xmitframe(xmitpriv, fwd_frame);
+
+#ifdef CONFIG_RTW_MESH
+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
+ if (!rtw_is_list_empty(b2u_list)) {
+ struct xmit_frame *b2uframe;
+ _list *list;
+
+ list = get_next(b2u_list);
+ while (rtw_end_of_queue_search(b2u_list, list) == _FALSE) {
+ b2uframe = LIST_CONTAINOR(list, struct xmit_frame, list);
+ list = get_next(list);
+ rtw_list_delete(&b2uframe->list);
+ rtw_free_xmitframe(xmitpriv, b2uframe);
+ }
+ }
+#endif
+#endif /* CONFIG_RTW_MESH */
+}
+
+static void recv_fwd_pkt_hdl(_adapter *adapter, _pkt *pkt
+ , u8 act, struct xmit_frame *fwd_frame, _list *b2u_list)
+{
+ struct xmit_priv *xmitpriv = &adapter->xmitpriv;
+ _pkt *fwd_pkt = pkt;
+
+ if (act & RTW_RX_MSDU_ACT_INDICATE) {
+ fwd_pkt = rtw_os_pkt_copy(pkt);
+ if (!fwd_pkt) {
+ #ifdef DBG_TX_DROP_FRAME
+ RTW_INFO("DBG_TX_DROP_FRAME %s rtw_os_pkt_copy fail\n", __func__);
+ #endif
+ recv_free_fwd_resource(adapter, fwd_frame, b2u_list);
+ goto exit;
+ }
+ }
+
+#ifdef CONFIG_RTW_MESH
+#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
+ if (!rtw_is_list_empty(b2u_list)) {
+ _list *list = get_next(b2u_list);
+ struct xmit_frame *b2uframe;
+
+ while (rtw_end_of_queue_search(b2u_list, list) == _FALSE) {
+ b2uframe = LIST_CONTAINOR(list, struct xmit_frame, list);
+ list = get_next(list);
+ rtw_list_delete(&b2uframe->list);
+
+ if (!fwd_frame && rtw_is_list_empty(b2u_list)) /* the last fwd_pkt */
+ b2uframe->pkt = fwd_pkt;
+ else
+ b2uframe->pkt = rtw_os_pkt_copy(fwd_pkt);
+ if (!b2uframe->pkt) {
+ rtw_free_xmitframe(xmitpriv, b2uframe);
+ continue;
+ }
+
+ rtw_xmit_posthandle(adapter, b2uframe, b2uframe->pkt);
+ }
+ }
+#endif
+#endif /* CONFIG_RTW_MESH */
+
+ if (fwd_frame) {
+ fwd_frame->pkt = fwd_pkt;
+ if (rtw_xmit_posthandle(adapter, fwd_frame, fwd_pkt) < 0) {
+ #ifdef DBG_TX_DROP_FRAME
+ RTW_INFO("DBG_TX_DROP_FRAME %s rtw_xmit_posthandle fail\n", __func__);
+ #endif
+ xmitpriv->tx_drop++;
+ }
+ }
+
+exit:
+ return;
+}
+
int amsdu_to_msdu(_adapter *padapter, union recv_frame *prframe)
{
+ struct rx_pkt_attrib *rattrib = &prframe->u.hdr.attrib;
int a_len, padding_len;
u16 nSubframe_Length;
u8 nr_subframes, i;
@@ -2817,43 +2985,96 @@ int amsdu_to_msdu(_adapter *padapter, union recv_frame *prframe)
_pkt *sub_pkt, *subframes[MAX_SUBFRAME_COUNT];
struct recv_priv *precvpriv = &padapter->recvpriv;
_queue *pfree_recv_queue = &(precvpriv->free_recv_queue);
+ const u8 *da, *sa;
+ int act;
+ struct xmit_frame *fwd_frame;
+ _list b2u_list;
+ u8 mctrl_len = 0;
int ret = _SUCCESS;
nr_subframes = 0;
- recvframe_pull(prframe, prframe->u.hdr.attrib.hdrlen);
+ recvframe_pull(prframe, rattrib->hdrlen);
- if (prframe->u.hdr.attrib.iv_len > 0)
- recvframe_pull(prframe, prframe->u.hdr.attrib.iv_len);
+ if (rattrib->iv_len > 0)
+ recvframe_pull(prframe, rattrib->iv_len);
a_len = prframe->u.hdr.len;
-
pdata = prframe->u.hdr.rx_data;
while (a_len > ETH_HLEN) {
-
/* Offset 12 denote 2 mac address */
nSubframe_Length = RTW_GET_BE16(pdata + 12);
-
if (a_len < (ETHERNET_HEADER_SIZE + nSubframe_Length)) {
RTW_INFO("nRemain_Length is %d and nSubframe_Length is : %d\n", a_len, nSubframe_Length);
break;
}
- sub_pkt = rtw_os_alloc_msdu_pkt(prframe, nSubframe_Length, pdata);
+ act = RTW_RX_MSDU_ACT_INDICATE;
+ fwd_frame = NULL;
+
+ #ifdef CONFIG_RTW_MESH
+ if (MLME_IS_MESH(padapter)) {
+ u8 *mda = pdata, *msa = pdata + ETH_ALEN;
+ struct rtw_ieee80211s_hdr *mctrl = (struct rtw_ieee80211s_hdr *)(pdata + ETH_HLEN);
+ int v_ret;
+
+ v_ret = rtw_mesh_rx_data_validate_mctrl(padapter, prframe
+ , mctrl, mda, msa, &mctrl_len, &da, &sa);
+ if (v_ret != _SUCCESS)
+ goto move_to_next;
+
+ act = rtw_mesh_rx_msdu_act_check(prframe
+ , mda, msa, da, sa, mctrl, &fwd_frame, &b2u_list);
+ } else
+ #endif
+ {
+ da = pdata;
+ sa = pdata + ETH_ALEN;
+ }
+
+ if (!act)
+ goto move_to_next;
+
+ rtw_led_rx_control(padapter, da);
+
+ sub_pkt = rtw_os_alloc_msdu_pkt(prframe, da, sa
+ , pdata + ETH_HLEN + mctrl_len, nSubframe_Length - mctrl_len);
if (sub_pkt == NULL) {
- RTW_INFO("%s(): allocate sub packet fail !!!\n", __FUNCTION__);
+ if (act & RTW_RX_MSDU_ACT_INDICATE) {
+ #ifdef DBG_RX_DROP_FRAME
+ RTW_INFO("DBG_RX_DROP_FRAME %s rtw_os_alloc_msdu_pkt fail\n", __func__);
+ #endif
+ }
+ if (act & RTW_RX_MSDU_ACT_FORWARD) {
+ #ifdef DBG_TX_DROP_FRAME
+ RTW_INFO("DBG_TX_DROP_FRAME %s rtw_os_alloc_msdu_pkt fail\n", __func__);
+ #endif
+ recv_free_fwd_resource(padapter, fwd_frame, &b2u_list);
+ }
break;
}
+ #ifdef CONFIG_RTW_MESH
+ if (act & RTW_RX_MSDU_ACT_FORWARD) {
+ recv_fwd_pkt_hdl(padapter, sub_pkt, act, fwd_frame, &b2u_list);
+ if (!(act & RTW_RX_MSDU_ACT_INDICATE))
+ goto move_to_next;
+ }
+ #endif
+
+ if (rtw_recv_indicatepkt_check(prframe, rtw_os_pkt_data(sub_pkt), rtw_os_pkt_len(sub_pkt)) == _SUCCESS)
+ subframes[nr_subframes++] = sub_pkt;
+ else
+ rtw_os_pkt_free(sub_pkt);
+
+move_to_next:
/* move the data point to data content */
pdata += ETH_HLEN;
a_len -= ETH_HLEN;
- subframes[nr_subframes++] = sub_pkt;
-
if (nr_subframes >= MAX_SUBFRAME_COUNT) {
- RTW_INFO("ParseSubframe(): Too many Subframes! Packets dropped!\n");
+ RTW_WARN("ParseSubframe(): Too many Subframes! Packets dropped!\n");
break;
}
@@ -2878,7 +3099,7 @@ int amsdu_to_msdu(_adapter *padapter, union recv_frame *prframe)
/* Indicat the packets to upper layer */
if (sub_pkt)
- rtw_os_recv_indicate_pkt(padapter, sub_pkt, &prframe->u.hdr.attrib);
+ rtw_os_recv_indicate_pkt(padapter, sub_pkt, prframe);
}
prframe->u.hdr.len = 0;
@@ -2887,77 +3108,164 @@ int amsdu_to_msdu(_adapter *padapter, union recv_frame *prframe)
return ret;
}
-int check_indicate_seq(struct recv_reorder_ctrl *preorder_ctrl, u16 seq_num);
-int check_indicate_seq(struct recv_reorder_ctrl *preorder_ctrl, u16 seq_num)
+static int recv_process_mpdu(_adapter *padapter, union recv_frame *prframe)
+{
+ struct recv_priv *precvpriv = &padapter->recvpriv;
+ _queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue;
+ struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
+ int ret;
+
+ if (pattrib->amsdu) {
+ ret = amsdu_to_msdu(padapter, prframe);
+ if (ret != _SUCCESS) {
+ #ifdef DBG_RX_DROP_FRAME
+ RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" amsdu_to_msdu fail\n"
+ , FUNC_ADPT_ARG(padapter));
+ #endif
+ rtw_free_recvframe(prframe, pfree_recv_queue);
+ goto exit;
+ }
+ } else {
+ int act = RTW_RX_MSDU_ACT_INDICATE;
+ struct xmit_frame *fwd_frame = NULL;
+ _list b2u_list;
+
+ #ifdef CONFIG_RTW_MESH
+ if (MLME_IS_MESH(padapter) && pattrib->mesh_ctrl_present) {
+ act = rtw_mesh_rx_msdu_act_check(prframe
+ , pattrib->mda, pattrib->msa
+ , pattrib->dst, pattrib->src
+ , (struct rtw_ieee80211s_hdr *)(get_recvframe_data(prframe) + pattrib->hdrlen + pattrib->iv_len)
+ , &fwd_frame, &b2u_list);
+ }
+ #endif
+
+ if (!act) {
+ rtw_free_recvframe(prframe, pfree_recv_queue);
+ ret = _FAIL;
+ goto exit;
+ }
+
+ rtw_led_rx_control(padapter, pattrib->dst);
+
+ ret = wlanhdr_to_ethhdr(prframe);
+ if (ret != _SUCCESS) {
+ if (act & RTW_RX_MSDU_ACT_INDICATE) {
+ #ifdef DBG_RX_DROP_FRAME
+ RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" wlanhdr_to_ethhdr: drop pkt\n"
+ , FUNC_ADPT_ARG(padapter));
+ #endif
+ }
+ if (act & RTW_RX_MSDU_ACT_FORWARD) {
+ #ifdef DBG_TX_DROP_FRAME
+ RTW_INFO("DBG_TX_DROP_FRAME %s wlanhdr_to_ethhdr fail\n", __func__);
+ #endif
+ recv_free_fwd_resource(padapter, fwd_frame, &b2u_list);
+ }
+ rtw_free_recvframe(prframe, pfree_recv_queue);
+ goto exit;
+ }
+
+ #ifdef CONFIG_RTW_MESH
+ if (act & RTW_RX_MSDU_ACT_FORWARD) {
+ recv_fwd_pkt_hdl(padapter, prframe->u.hdr.pkt, act, fwd_frame, &b2u_list);
+ if (!(act & RTW_RX_MSDU_ACT_INDICATE)) {
+ prframe->u.hdr.pkt = NULL;
+ rtw_free_recvframe(prframe, pfree_recv_queue);
+ goto exit;
+ }
+ }
+ #endif
+
+ if (!RTW_CANNOT_RUN(padapter)) {
+ ret = rtw_recv_indicatepkt_check(prframe
+ , get_recvframe_data(prframe), get_recvframe_len(prframe));
+ if (ret != _SUCCESS) {
+ rtw_free_recvframe(prframe, pfree_recv_queue);
+ goto exit;
+ }
+
+ /* indicate this recv_frame */
+ ret = rtw_recv_indicatepkt(padapter, prframe);
+ if (ret != _SUCCESS) {
+ #ifdef DBG_RX_DROP_FRAME
+ RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" rtw_recv_indicatepkt fail!\n"
+ , FUNC_ADPT_ARG(padapter));
+ #endif
+ goto exit;
+ }
+ } else {
+ #ifdef DBG_RX_DROP_FRAME
+ RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" DS:%u SR:%u\n"
+ , FUNC_ADPT_ARG(padapter)
+ , rtw_is_drv_stopped(padapter)
+ , rtw_is_surprise_removed(padapter));
+ #endif
+ ret = _SUCCESS; /* don't count as packet drop */
+ rtw_free_recvframe(prframe, pfree_recv_queue);
+ }
+ }
+
+exit:
+ return ret;
+}
+
+#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL)
+static int check_indicate_seq(struct recv_reorder_ctrl *preorder_ctrl, u16 seq_num)
{
PADAPTER padapter = preorder_ctrl->padapter;
- struct dvobj_priv *psdpriv = padapter->dvobj;
- struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
+ struct recv_priv *precvpriv = &padapter->recvpriv;
u8 wsize = preorder_ctrl->wsize_b;
u16 wend = (preorder_ctrl->indicate_seq + wsize - 1) & 0xFFF; /* % 4096; */
/* Rx Reorder initialize condition. */
if (preorder_ctrl->indicate_seq == 0xFFFF) {
preorder_ctrl->indicate_seq = seq_num;
-#ifdef DBG_RX_SEQ
- RTW_INFO("DBG_RX_SEQ %s:%d init IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__,
- preorder_ctrl->indicate_seq, seq_num);
-#endif
-
- /* DbgPrint("check_indicate_seq, 1st->indicate_seq=%d\n", precvpriv->indicate_seq); */
+ #ifdef DBG_RX_SEQ
+ RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_INIT indicate_seq:%d, seq_num:%d\n"
+ , FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, seq_num);
+ #endif
}
- /* DbgPrint("enter->check_indicate_seq(): IndicateSeq: %d, NewSeq: %d\n", precvpriv->indicate_seq, seq_num); */
-
/* Drop out the packet which SeqNum is smaller than WinStart */
if (SN_LESS(seq_num, preorder_ctrl->indicate_seq)) {
- /* RT_TRACE(COMP_RX_REORDER, DBG_LOUD, ("CheckRxTsIndicateSeq(): Packet Drop! IndicateSeq: %d, NewSeq: %d\n", pTS->RxIndicateSeq, NewSeqNum)); */
- /* DbgPrint("CheckRxTsIndicateSeq(): Packet Drop! IndicateSeq: %d, NewSeq: %d\n", precvpriv->indicate_seq, seq_num); */
-
-#ifdef DBG_RX_DROP_FRAME
- RTW_INFO("%s IndicateSeq: %d > NewSeq: %d\n", __FUNCTION__,
- preorder_ctrl->indicate_seq, seq_num);
-#endif
-
-
+ #ifdef DBG_RX_DROP_FRAME
+ RTW_INFO(FUNC_ADPT_FMT" tid:%u indicate_seq:%d > seq_num:%d\n"
+ , FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, seq_num);
+ #endif
return _FALSE;
}
- /* */
- /* Sliding window manipulation. Conditions includes: */
- /* 1. Incoming SeqNum is equal to WinStart =>Window shift 1 */
- /* 2. Incoming SeqNum is larger than the WinEnd => Window shift N */
- /* */
+ /*
+ * Sliding window manipulation. Conditions includes:
+ * 1. Incoming SeqNum is equal to WinStart =>Window shift 1
+ * 2. Incoming SeqNum is larger than the WinEnd => Window shift N
+ */
if (SN_EQUAL(seq_num, preorder_ctrl->indicate_seq)) {
preorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1) & 0xFFF;
+ #ifdef DBG_RX_SEQ
+ RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_EQUAL indicate_seq:%d, seq_num:%d\n"
+ , FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, seq_num);
+ #endif
-#ifdef DBG_RX_SEQ
- RTW_INFO("DBG_RX_SEQ %s:%d SN_EQUAL IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__,
- preorder_ctrl->indicate_seq, seq_num);
-#endif
} else if (SN_LESS(wend, seq_num)) {
- /* RT_TRACE(COMP_RX_REORDER, DBG_LOUD, ("CheckRxTsIndicateSeq(): Window Shift! IndicateSeq: %d, NewSeq: %d\n", pTS->RxIndicateSeq, NewSeqNum)); */
- /* DbgPrint("CheckRxTsIndicateSeq(): Window Shift! IndicateSeq: %d, NewSeq: %d\n", precvpriv->indicate_seq, seq_num); */
-
/* boundary situation, when seq_num cross 0xFFF */
if (seq_num >= (wsize - 1))
preorder_ctrl->indicate_seq = seq_num + 1 - wsize;
else
preorder_ctrl->indicate_seq = 0xFFF - (wsize - (seq_num + 1)) + 1;
- pdbgpriv->dbg_rx_ampdu_window_shift_cnt++;
-#ifdef DBG_RX_SEQ
- RTW_INFO("DBG_RX_SEQ %s:%d SN_LESS(wend, seq_num) IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__,
- preorder_ctrl->indicate_seq, seq_num);
-#endif
- }
- /* DbgPrint("exit->check_indicate_seq(): IndicateSeq: %d, NewSeq: %d\n", precvpriv->indicate_seq, seq_num); */
+ precvpriv->dbg_rx_ampdu_window_shift_cnt++;
+ #ifdef DBG_RX_SEQ
+ RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_LESS(wend, seq_num) indicate_seq:%d, seq_num:%d\n"
+ , FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, seq_num);
+ #endif
+ }
return _TRUE;
}
-int enqueue_reorder_recvframe(struct recv_reorder_ctrl *preorder_ctrl, union recv_frame *prframe);
-int enqueue_reorder_recvframe(struct recv_reorder_ctrl *preorder_ctrl, union recv_frame *prframe)
+static int enqueue_reorder_recvframe(struct recv_reorder_ctrl *preorder_ctrl, union recv_frame *prframe)
{
struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
_queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue;
@@ -2982,7 +3290,6 @@ int enqueue_reorder_recvframe(struct recv_reorder_ctrl *preorder_ctrl, union rec
plist = get_next(plist);
else if (SN_EQUAL(pnextattrib->seq_num, pattrib->seq_num)) {
/* Duplicate entry is found!! Do not insert current entry. */
- /* RT_TRACE(COMP_RX_REORDER, DBG_TRACE, ("InsertRxReorderList(): Duplicate packet is dropped!! IndicateSeq: %d, NewSeq: %d\n", pTS->RxIndicateSeq, SeqNum)); */
/* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */
@@ -3006,25 +3313,26 @@ int enqueue_reorder_recvframe(struct recv_reorder_ctrl *preorder_ctrl, union rec
/* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */
- /* RT_TRACE(COMP_RX_REORDER, DBG_TRACE, ("InsertRxReorderList(): Pkt insert into buffer!! IndicateSeq: %d, NewSeq: %d\n", pTS->RxIndicateSeq, SeqNum)); */
return _TRUE;
}
-void recv_indicatepkts_pkt_loss_cnt(struct debug_priv *pdbgpriv, u64 prev_seq, u64 current_seq);
-void recv_indicatepkts_pkt_loss_cnt(struct debug_priv *pdbgpriv, u64 prev_seq, u64 current_seq)
+static void recv_indicatepkts_pkt_loss_cnt(_adapter *padapter, u64 prev_seq, u64 current_seq)
{
- if (current_seq < prev_seq)
- pdbgpriv->dbg_rx_ampdu_loss_count += (4096 + current_seq - prev_seq);
+ struct recv_priv *precvpriv = &padapter->recvpriv;
- else
- pdbgpriv->dbg_rx_ampdu_loss_count += (current_seq - prev_seq);
+ if (current_seq < prev_seq) {
+ precvpriv->dbg_rx_ampdu_loss_count += (4096 + current_seq - prev_seq);
+ precvpriv->rx_drop += (4096 + current_seq - prev_seq);
+ } else {
+ precvpriv->dbg_rx_ampdu_loss_count += (current_seq - prev_seq);
+ precvpriv->rx_drop += (current_seq - prev_seq);
+ }
}
-int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *preorder_ctrl, int bforced);
-int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *preorder_ctrl, int bforced)
+
+static int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *preorder_ctrl, int bforced)
{
/* _irqL irql; */
- /* u8 bcancelled; */
_list *phead, *plist;
union recv_frame *prframe;
struct rx_pkt_attrib *pattrib;
@@ -3032,8 +3340,6 @@ int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *pre
int bPktInBuf = _FALSE;
struct recv_priv *precvpriv = &padapter->recvpriv;
_queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue;
- struct dvobj_priv *psdpriv = padapter->dvobj;
- struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
DBG_COUNTER(padapter->rx_logs.core_rx_post_indicate_in_oder);
@@ -3053,7 +3359,7 @@ int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *pre
/* Handling some condition for forced indicate case. */
if (bforced == _TRUE) {
- pdbgpriv->dbg_rx_ampdu_forced_indicate_count++;
+ precvpriv->dbg_rx_ampdu_forced_indicate_count++;
if (rtw_is_list_empty(phead)) {
/* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */
/* _rtw_spinunlock_ex(&ppending_recvframe_queue->lock); */
@@ -3063,13 +3369,12 @@ int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *pre
prframe = LIST_CONTAINOR(plist, union recv_frame, u);
pattrib = &prframe->u.hdr.attrib;
-#ifdef DBG_RX_SEQ
- RTW_INFO("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__,
- preorder_ctrl->indicate_seq, pattrib->seq_num);
-#endif
- recv_indicatepkts_pkt_loss_cnt(pdbgpriv, preorder_ctrl->indicate_seq, pattrib->seq_num);
+ #ifdef DBG_RX_SEQ
+ RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u FORCE indicate_seq:%d, seq_num:%d\n"
+ , FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, pattrib->seq_num);
+ #endif
+ recv_indicatepkts_pkt_loss_cnt(padapter, preorder_ctrl->indicate_seq, pattrib->seq_num);
preorder_ctrl->indicate_seq = pattrib->seq_num;
-
}
/* Prepare indication list and indication. */
@@ -3080,9 +3385,6 @@ int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *pre
pattrib = &prframe->u.hdr.attrib;
if (!SN_LESS(preorder_ctrl->indicate_seq, pattrib->seq_num)) {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_,
- ("recv_indicatepkts_in_order: indicate=%d seq=%d amsdu=%d\n",
- preorder_ctrl->indicate_seq, pattrib->seq_num, pattrib->amsdu));
#if 0
/* This protect buffer from overflow. */
@@ -3098,10 +3400,10 @@ int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *pre
if (SN_EQUAL(preorder_ctrl->indicate_seq, pattrib->seq_num)) {
preorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1) & 0xFFF;
-#ifdef DBG_RX_SEQ
- RTW_INFO("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__,
- preorder_ctrl->indicate_seq, pattrib->seq_num);
-#endif
+ #ifdef DBG_RX_SEQ
+ RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_EQUAL indicate_seq:%d, seq_num:%d\n"
+ , FUNC_ADPT_ARG(padapter), preorder_ctrl->tid, preorder_ctrl->indicate_seq, pattrib->seq_num);
+ #endif
}
#if 0
@@ -3110,8 +3412,8 @@ int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *pre
/* Cancel previous pending timer. */
/* PlatformCancelTimer(Adapter, &pTS->RxPktPendingTimer); */
if (bforced != _TRUE) {
- /* RTW_INFO("_cancel_timer(&preorder_ctrl->reordering_ctrl_timer, &bcancelled);\n"); */
- _cancel_timer(&preorder_ctrl->reordering_ctrl_timer, &bcancelled);
+ /* RTW_INFO("_cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer);\n"); */
+ _cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer);
}
}
#endif
@@ -3125,19 +3427,8 @@ int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *pre
/* indicate this recv_frame */
/* DbgPrint("recv_indicatepkts_in_order, indicate_seq=%d, seq_num=%d\n", precvpriv->indicate_seq, pattrib->seq_num); */
- if (!pattrib->amsdu) {
- /* RTW_INFO("recv_indicatepkts_in_order, amsdu!=1, indicate_seq=%d, seq_num=%d\n", preorder_ctrl->indicate_seq, pattrib->seq_num); */
-
- if (!RTW_CANNOT_RUN(padapter))
- rtw_recv_indicatepkt(padapter, prframe);/*indicate this recv_frame*/
-
- } else if (pattrib->amsdu == 1) {
- if (amsdu_to_msdu(padapter, prframe) != _SUCCESS)
- rtw_free_recvframe(prframe, &precvpriv->free_recv_queue);
- } else {
- /* error condition; */
- }
-
+ if (recv_process_mpdu(padapter, prframe) != _SUCCESS)
+ precvpriv->dbg_rx_drop_count++;
/* Update local variables. */
bPktInBuf = _FALSE;
@@ -3173,120 +3464,34 @@ int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *pre
}
-int recv_indicatepkt_reorder(_adapter *padapter, union recv_frame *prframe);
-int recv_indicatepkt_reorder(_adapter *padapter, union recv_frame *prframe)
+static int recv_indicatepkt_reorder(_adapter *padapter, union recv_frame *prframe)
{
_irqL irql;
int retval = _SUCCESS;
struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
struct recv_reorder_ctrl *preorder_ctrl = prframe->u.hdr.preorder_ctrl;
- _queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue;
- struct dvobj_priv *psdpriv = padapter->dvobj;
- struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
-
- DBG_COUNTER(padapter->rx_logs.core_rx_post_indicate_reoder);
-
- if (!pattrib->amsdu) {
- /* s1. */
- retval = wlanhdr_to_ethhdr(prframe);
- if (retval != _SUCCESS) {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("wlanhdr_to_ethhdr: drop pkt\n"));
-#ifdef DBG_RX_DROP_FRAME
- RTW_INFO("DBG_RX_DROP_FRAME %s wlanhdr_to_ethhdr error!\n", __FUNCTION__);
-#endif
- return retval;
- }
-
- /* if ((pattrib->qos!=1) || pattrib->priority!=0 || IS_MCAST(pattrib->ra) */
- /* || (pattrib->eth_type==0x0806) || (pattrib->ack_policy!=0)) */
- if (pattrib->qos != 1) {
- if (!RTW_CANNOT_RUN(padapter)) {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ("@@@@ recv_indicatepkt_reorder -recv_func recv_indicatepkt\n"));
-
- rtw_recv_indicatepkt(padapter, prframe);
- return _SUCCESS;
-
- }
-
-#ifdef DBG_RX_DROP_FRAME
- RTW_INFO("DBG_RX_DROP_FRAME %s pattrib->qos !=1\n", __FUNCTION__);
-#endif
-
- return _FAIL;
-
- }
-
- if (preorder_ctrl->enable == _FALSE) {
- /* indicate this recv_frame */
- preorder_ctrl->indicate_seq = pattrib->seq_num;
-#ifdef DBG_RX_SEQ
- RTW_INFO("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__,
- preorder_ctrl->indicate_seq, pattrib->seq_num);
-#endif
-
- rtw_recv_indicatepkt(padapter, prframe);
-
- preorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1) % 4096;
-#ifdef DBG_RX_SEQ
- RTW_INFO("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__,
- preorder_ctrl->indicate_seq, pattrib->seq_num);
-#endif
-
- return _SUCCESS;
- }
+ _queue *ppending_recvframe_queue = preorder_ctrl ? &preorder_ctrl->pending_recvframe_queue : NULL;
+ struct recv_priv *precvpriv = &padapter->recvpriv;
-#ifndef CONFIG_RECV_REORDERING_CTRL
- /* indicate this recv_frame */
- rtw_recv_indicatepkt(padapter, prframe);
- return _SUCCESS;
-#endif
-
- } else if (pattrib->amsdu == 1) { /* temp filter->means didn't support A-MSDUs in a A-MPDU */
- if (preorder_ctrl->enable == _FALSE) {
- preorder_ctrl->indicate_seq = pattrib->seq_num;
-#ifdef DBG_RX_SEQ
- RTW_INFO("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__,
- preorder_ctrl->indicate_seq, pattrib->seq_num);
-#endif
-
- retval = amsdu_to_msdu(padapter, prframe);
-
- preorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1) % 4096;
-#ifdef DBG_RX_SEQ
- RTW_INFO("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__,
- preorder_ctrl->indicate_seq, pattrib->seq_num);
-#endif
-
- if (retval != _SUCCESS) {
-#ifdef DBG_RX_DROP_FRAME
- RTW_INFO("DBG_RX_DROP_FRAME %s amsdu_to_msdu fail\n", __FUNCTION__);
-#endif
- }
-
- return retval;
- }
- } else {
+ if (!pattrib->qos || !preorder_ctrl || preorder_ctrl->enable == _FALSE)
+ goto _success_exit;
- }
+ DBG_COUNTER(padapter->rx_logs.core_rx_post_indicate_reoder);
_enter_critical_bh(&ppending_recvframe_queue->lock, &irql);
- RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_,
- ("recv_indicatepkt_reorder: indicate=%d seq=%d\n",
- preorder_ctrl->indicate_seq, pattrib->seq_num));
-
/* s2. check if winstart_b(indicate_seq) needs to been updated */
if (!check_indicate_seq(preorder_ctrl, pattrib->seq_num)) {
- pdbgpriv->dbg_rx_ampdu_drop_count++;
+ precvpriv->dbg_rx_ampdu_drop_count++;
/* pHTInfo->RxReorderDropCounter++; */
/* ReturnRFDList(Adapter, pRfd); */
- /* RT_TRACE(COMP_RX_REORDER, DBG_TRACE, ("RxReorderIndicatePacket() ==> Packet Drop!!\n")); */
/* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */
/* return _FAIL; */
-#ifdef DBG_RX_DROP_FRAME
- RTW_INFO("DBG_RX_DROP_FRAME %s check_indicate_seq fail\n", __FUNCTION__);
-#endif
+ #ifdef DBG_RX_DROP_FRAME
+ RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" check_indicate_seq fail\n"
+ , FUNC_ADPT_ARG(padapter));
+ #endif
#if 0
rtw_recv_indicatepkt(padapter, prframe);
@@ -3304,9 +3509,10 @@ int recv_indicatepkt_reorder(_adapter *padapter, union recv_frame *prframe)
/* DbgPrint("recv_indicatepkt_reorder, enqueue_reorder_recvframe fail!\n"); */
/* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */
/* return _FAIL; */
-#ifdef DBG_RX_DROP_FRAME
- RTW_INFO("DBG_RX_DROP_FRAME %s enqueue_reorder_recvframe fail\n", __FUNCTION__);
-#endif
+ #ifdef DBG_RX_DROP_FRAME
+ RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" enqueue_reorder_recvframe fail\n"
+ , FUNC_ADPT_ARG(padapter));
+ #endif
goto _err_exit;
}
@@ -3334,6 +3540,7 @@ int recv_indicatepkt_reorder(_adapter *padapter, union recv_frame *prframe)
_cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer);
}
+ return RTW_RX_HANDLED;
_success_exit:
@@ -3371,75 +3578,38 @@ void rtw_reordering_ctrl_timeout_handler(void *pcontext)
_exit_critical_bh(&ppending_recvframe_queue->lock, &irql);
}
+#endif /* defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL) */
-int process_recv_indicatepkts(_adapter *padapter, union recv_frame *prframe);
-int process_recv_indicatepkts(_adapter *padapter, union recv_frame *prframe)
+static void recv_set_iseq_before_mpdu_process(union recv_frame *rframe, u16 seq_num, const char *caller)
{
- int retval = _SUCCESS;
- /* struct recv_priv *precvpriv = &padapter->recvpriv; */
- /* struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; */
- struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
-#ifdef CONFIG_TDLS
- struct sta_info *psta = prframe->u.hdr.psta;
-#endif /* CONFIG_TDLS */
-
-#ifdef CONFIG_80211N_HT
-
- struct ht_priv *phtpriv = &pmlmepriv->htpriv;
-
- DBG_COUNTER(padapter->rx_logs.core_rx_post_indicate);
-
-#ifdef CONFIG_TDLS
- if ((phtpriv->ht_option == _TRUE) ||
- ((psta->tdls_sta_state & TDLS_LINKED_STATE) &&
- (psta->htpriv.ht_option == _TRUE) &&
- (psta->htpriv.ampdu_enable == _TRUE))) /* B/G/N Mode */
-#else
- if (phtpriv->ht_option == _TRUE) /* B/G/N Mode */
-#endif /* CONFIG_TDLS */
- {
- /* prframe->u.hdr.preorder_ctrl = &precvpriv->recvreorder_ctrl[pattrib->priority]; */
-
- if (recv_indicatepkt_reorder(padapter, prframe) != _SUCCESS) { /* including perform A-MPDU Rx Ordering Buffer Control */
-#ifdef DBG_RX_DROP_FRAME
- RTW_INFO("DBG_RX_DROP_FRAME %s recv_indicatepkt_reorder error!\n", __FUNCTION__);
-#endif
-
- if (!RTW_CANNOT_RUN(padapter)) {
- retval = _FAIL;
- return retval;
- }
- }
- } else /* B/G mode */
-#endif
- {
- retval = wlanhdr_to_ethhdr(prframe);
- if (retval != _SUCCESS) {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("wlanhdr_to_ethhdr: drop pkt\n"));
-#ifdef DBG_RX_DROP_FRAME
- RTW_INFO("DBG_RX_DROP_FRAME %s wlanhdr_to_ethhdr error!\n", __FUNCTION__);
+#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL)
+ struct recv_reorder_ctrl *reorder_ctrl = rframe->u.hdr.preorder_ctrl;
+
+ if (reorder_ctrl) {
+ reorder_ctrl->indicate_seq = seq_num;
+ #ifdef DBG_RX_SEQ
+ RTW_INFO("DBG_RX_SEQ %s("ADPT_FMT")-B tid:%u indicate_seq:%d, seq_num:%d\n"
+ , caller, ADPT_ARG(reorder_ctrl->padapter)
+ , reorder_ctrl->tid, reorder_ctrl->indicate_seq, seq_num);
+ #endif
+ }
#endif
- return retval;
- }
-
- if (!RTW_CANNOT_RUN(padapter)) {
- /* indicate this recv_frame */
- RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ("@@@@ process_recv_indicatepkts- recv_func recv_indicatepkt\n"));
- rtw_recv_indicatepkt(padapter, prframe);
- } else {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ("@@@@ process_recv_indicatepkts- recv_func free_indicatepkt\n"));
-
- RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ("recv_func:bDriverStopped(%s) OR bSurpriseRemoved(%s)"
- , rtw_is_drv_stopped(padapter) ? "True" : "False"
- , rtw_is_surprise_removed(padapter) ? "True" : "False"));
- retval = _FAIL;
- return retval;
- }
+}
+static void recv_set_iseq_after_mpdu_process(union recv_frame *rframe, u16 seq_num, const char *caller)
+{
+#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL)
+ struct recv_reorder_ctrl *reorder_ctrl = rframe->u.hdr.preorder_ctrl;
+
+ if (reorder_ctrl) {
+ reorder_ctrl->indicate_seq = (reorder_ctrl->indicate_seq + 1) % 4096;
+ #ifdef DBG_RX_SEQ
+ RTW_INFO("DBG_RX_SEQ %s("ADPT_FMT")-A tid:%u indicate_seq:%d, seq_num:%d\n"
+ , caller, ADPT_ARG(reorder_ctrl->padapter)
+ , reorder_ctrl->tid, reorder_ctrl->indicate_seq, seq_num);
+ #endif
}
-
- return retval;
-
+#endif
}
#ifdef CONFIG_MP_INCLUDED
@@ -3450,6 +3620,7 @@ int validate_mp_recv_frame(_adapter *adapter, union recv_frame *precv_frame)
u8 type, subtype;
struct mp_priv *pmppriv = &adapter->mppriv;
struct mp_tx *pmptx;
+ unsigned char *sa , *da, *bs;
pmptx = &pmppriv->tx;
@@ -3457,7 +3628,7 @@ int validate_mp_recv_frame(_adapter *adapter, union recv_frame *precv_frame)
if (1) {
u8 bDumpRxPkt;
type = GetFrameType(ptr);
- subtype = GetFrameSubType(ptr); /* bit(7)~bit(2) */
+ subtype = get_frame_sub_type(ptr); /* bit(7)~bit(2) */
rtw_hal_get_def_var(adapter, HAL_DEF_DBG_DUMP_RXPKT, &(bDumpRxPkt));
if (bDumpRxPkt == 1) { /* dump all rx packets */
@@ -3477,16 +3648,31 @@ int validate_mp_recv_frame(_adapter *adapter, union recv_frame *precv_frame)
ret = _FAIL;
}
}
+ if (pmppriv->bSetRxBssid == _TRUE) {
+
+ sa = get_addr2_ptr(ptr);
+ da = GetAddr1Ptr(ptr);
+ bs = GetAddr3Ptr(ptr);
+ type = GetFrameType(ptr);
+ subtype = get_frame_sub_type(ptr); /* bit(7)~bit(2) */
+
+ if (_rtw_memcmp(bs, adapter->mppriv.network_macaddr, ETH_ALEN) == _FALSE)
+ ret = _FAIL;
+
+ RTW_DBG("############ type:0x%02x subtype:0x%02x #################\n", type, subtype);
+ RTW_DBG("A2 sa %02X:%02X:%02X:%02X:%02X:%02X \n", *(sa) , *(sa + 1), *(sa+ 2), *(sa + 3), *(sa + 4), *(sa + 5));
+ RTW_DBG("A1 da %02X:%02X:%02X:%02X:%02X:%02X \n", *(da) , *(da + 1), *(da+ 2), *(da + 3), *(da + 4), *(da + 5));
+ RTW_DBG("A3 bs %02X:%02X:%02X:%02X:%02X:%02X \n --------------------------\n", *(bs) , *(bs + 1), *(bs+ 2), *(bs + 3), *(bs + 4), *(bs + 5));
+ }
if (!adapter->mppriv.bmac_filter)
return ret;
- if (_rtw_memcmp(GetAddr2Ptr(ptr), adapter->mppriv.mac_filter, ETH_ALEN) == _FALSE)
+ if (_rtw_memcmp(get_addr2_ptr(ptr), adapter->mppriv.mac_filter, ETH_ALEN) == _FALSE)
ret = _FAIL;
return ret;
}
-#endif
static sint MPwlanhdr_to_ethhdr(union recv_frame *precvframe)
{
@@ -3505,7 +3691,6 @@ static sint MPwlanhdr_to_ethhdr(union recv_frame *precvframe)
u8 *ptr = get_recvframe_data(precvframe) ; /* point to frame_ctrl field */
struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib;
- _func_enter_;
if (pattrib->encrypt)
recvframe_pull_tail(precvframe, pattrib->icv_len);
@@ -3529,7 +3714,6 @@ static sint MPwlanhdr_to_ethhdr(union recv_frame *precvframe)
rmv_len = pattrib->hdrlen + pattrib->iv_len + (bsnaphdr ? SNAP_SIZE : 0);
len = precvframe->u.hdr.len - rmv_len;
- RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("\n===pattrib->hdrlen: %x, pattrib->iv_len:%x ===\n\n", pattrib->hdrlen, pattrib->iv_len));
_rtw_memcpy(ð_type, ptr + rmv_len, 2);
eth_type = ntohs((unsigned short)eth_type); /* pattrib->ether_type */
@@ -3561,7 +3745,6 @@ static sint MPwlanhdr_to_ethhdr(union recv_frame *precvframe)
}
- _func_exit_;
return ret;
}
@@ -3594,7 +3777,6 @@ int mp_recv_frame(_adapter *padapter, union recv_frame *rframe)
}
if (pmppriv->rx_bindicatePkt == _FALSE) {
- /* RT_TRACE(_module_rtl871x_recv_c_, _drv_alert_, ("MP - Not in loopback mode , drop pkt\n")); */
ret = _FAIL;
rtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */
goto exit;
@@ -3641,9 +3823,8 @@ int mp_recv_frame(_adapter *padapter, union recv_frame *rframe)
case 3:
_rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN);
- _rtw_memcpy(pattrib->ta, GetAddr2Ptr(ptr), ETH_ALEN);
+ _rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN);
ret = _FAIL;
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, (" case 3\n"));
break;
default:
@@ -3654,37 +3835,34 @@ int mp_recv_frame(_adapter *padapter, union recv_frame *rframe)
ret = MPwlanhdr_to_ethhdr(rframe);
if (ret != _SUCCESS) {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("wlanhdr_to_ethhdr: drop pkt\n"));
-#ifdef DBG_RX_DROP_FRAME
- RTW_INFO("DBG_RX_DROP_FRAME %s wlanhdr_to_ethhdr: drop pkt\n", __FUNCTION__);
-#endif
+ #ifdef DBG_RX_DROP_FRAME
+ RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" wlanhdr_to_ethhdr: drop pkt\n"
+ , FUNC_ADPT_ARG(padapter));
+ #endif
rtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */
ret = _FAIL;
goto exit;
}
if (!RTW_CANNOT_RUN(padapter)) {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_alert_, ("@@@@ recv_func: recv_func rtw_recv_indicatepkt\n"));
/* indicate this recv_frame */
ret = rtw_recv_indicatepkt(padapter, rframe);
if (ret != _SUCCESS) {
-#ifdef DBG_RX_DROP_FRAME
- RTW_INFO("DBG_RX_DROP_FRAME %s rtw_recv_indicatepkt fail!\n", __FUNCTION__);
-#endif
+ #ifdef DBG_RX_DROP_FRAME
+ RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" rtw_recv_indicatepkt fail!\n"
+ , FUNC_ADPT_ARG(padapter));
+ #endif
rtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */
ret = _FAIL;
goto exit;
}
} else {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_alert_, ("@@@@ recv_func: rtw_free_recvframe\n"));
- RT_TRACE(_module_rtl871x_recv_c_, _drv_debug_, ("recv_func:bDriverStopped(%s) OR bSurpriseRemoved(%s)"
+ #ifdef DBG_RX_DROP_FRAME
+ RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" bDriverStopped(%s) OR bSurpriseRemoved(%s)\n"
+ , FUNC_ADPT_ARG(padapter)
, rtw_is_drv_stopped(padapter) ? "True" : "False"
- , rtw_is_surprise_removed(padapter) ? "True" : "False"));
-#ifdef DBG_RX_DROP_FRAME
- RTW_INFO("DBG_RX_DROP_FRAME %s ecv_func:bDriverStopped(%s) OR bSurpriseRemoved(%s)\n", __func__,
- rtw_is_drv_stopped(padapter) ? "True" : "False",
- rtw_is_surprise_removed(padapter) ? "True" : "False");
-#endif
+ , rtw_is_surprise_removed(padapter) ? "True" : "False");
+ #endif
ret = _FAIL;
rtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */
goto exit;
@@ -3695,7 +3873,6 @@ int mp_recv_frame(_adapter *padapter, union recv_frame *rframe)
}
- RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("recv_func: validate_recv_frame fail! drop pkt\n"));
rtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */
ret = _FAIL;
@@ -3703,6 +3880,7 @@ int mp_recv_frame(_adapter *padapter, union recv_frame *rframe)
return ret;
}
+#endif
static sint fill_radiotap_hdr(_adapter *padapter, union recv_frame *precvframe, u8 *buf)
{
@@ -3737,6 +3915,11 @@ static sint fill_radiotap_hdr(_adapter *padapter, union recv_frame *precvframe,
/* (0 << IEEE80211_RADIOTAP_AMPDU_STATUS) | \ */
/* (0 << IEEE80211_RADIOTAP_VHT) | \ */
#endif
+
+#ifndef IEEE80211_RADIOTAP_RX_FLAGS
+#define IEEE80211_RADIOTAP_RX_FLAGS 14
+#endif
+
#ifndef IEEE80211_RADIOTAP_MCS
#define IEEE80211_RADIOTAP_MCS 19
#endif
@@ -3837,13 +4020,13 @@ static sint fill_radiotap_hdr(_adapter *padapter, union recv_frame *precvframe,
tmp_16bit = 0;
rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_CHANNEL);
tmp_16bit = CHAN2FREQ(rtw_get_oper_ch(padapter));
- /*tmp_16bit = CHAN2FREQ(pHalData->CurrentChannel);*/
+ /*tmp_16bit = CHAN2FREQ(pHalData->current_channel);*/
memcpy(&hdr_buf[rt_len], &tmp_16bit, 2);
rt_len += 2;
/* channel flags */
tmp_16bit = 0;
- if (pHalData->CurrentBandType == 0)
+ if (pHalData->current_band_type == 0)
tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_2GHZ);
else
tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_5GHZ);
@@ -3863,7 +4046,7 @@ static sint fill_radiotap_hdr(_adapter *padapter, union recv_frame *precvframe,
/* dBm Antenna Signal */
rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL);
- hdr_buf[rt_len] = pattrib->phy_info.RecvSignalPower;
+ hdr_buf[rt_len] = pattrib->phy_info.recv_signal_power;
rt_len += 1;
#if 0
@@ -3874,7 +4057,7 @@ static sint fill_radiotap_hdr(_adapter *padapter, union recv_frame *precvframe,
/* Signal Quality */
rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_LOCK_QUALITY);
- hdr_buf[rt_len] = pattrib->phy_info.SignalQuality;
+ hdr_buf[rt_len] = pattrib->phy_info.signal_quality;
rt_len += 1;
#endif
@@ -4006,7 +4189,7 @@ static sint fill_radiotap_hdr(_adapter *padapter, union recv_frame *precvframe,
return ret;
}
-
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))
int recv_frame_monitor(_adapter *padapter, union recv_frame *rframe)
{
int ret = _SUCCESS;
@@ -4053,7 +4236,7 @@ int recv_frame_monitor(_adapter *padapter, union recv_frame *rframe)
exit:
return ret;
}
-
+#endif
int recv_func_prehandle(_adapter *padapter, union recv_frame *rframe)
{
int ret = _SUCCESS;
@@ -4081,7 +4264,6 @@ int recv_func_prehandle(_adapter *padapter, union recv_frame *rframe)
/* check the frame crtl field and decache */
ret = validate_recv_frame(padapter, rframe);
if (ret != _SUCCESS) {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("recv_func: validate_recv_frame fail! drop pkt\n"));
rtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */
goto exit;
}
@@ -4104,31 +4286,24 @@ int recv_func_posthandle(_adapter *padapter, union recv_frame *prframe)
DBG_COUNTER(padapter->rx_logs.core_rx_post);
- /* DATA FRAME */
- rtw_led_control(padapter, LED_CTL_RX);
-
prframe = decryptor(padapter, prframe);
if (prframe == NULL) {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("decryptor: drop pkt\n"));
-#ifdef DBG_RX_DROP_FRAME
- RTW_INFO("DBG_RX_DROP_FRAME %s decryptor: drop pkt\n", __FUNCTION__);
-#endif
+ #ifdef DBG_RX_DROP_FRAME
+ RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" decryptor: drop pkt\n"
+ , FUNC_ADPT_ARG(padapter));
+ #endif
ret = _FAIL;
DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_err);
goto _recv_data_drop;
}
#ifdef DBG_RX_BMC_FRAME
- if (IS_MCAST(pattrib->ra)) {
- u8 *pbuf = prframe->u.hdr.rx_data;
- u8 *sa_addr = get_sa(pbuf);
-
- RTW_INFO("%s =>"ADPT_FMT" Rx BC/MC from MAC: "MAC_FMT"\n", __func__, ADPT_ARG(padapter), MAC_ARG(sa_addr));
- }
+ if (IS_MCAST(pattrib->ra))
+ RTW_INFO("%s =>"ADPT_FMT" Rx BC/MC from "MAC_FMT"\n", __func__, ADPT_ARG(padapter), MAC_ARG(pattrib->ta));
#endif
#if 0
- if (padapter->adapter_type == PRIMARY_ADAPTER) {
+ if (is_primary_adapter(padapter)) {
RTW_INFO("+++\n");
{
int i;
@@ -4157,20 +4332,20 @@ int recv_func_posthandle(_adapter *padapter, union recv_frame *prframe)
prframe = recvframe_chk_defrag(padapter, prframe);
if (prframe == NULL) {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("recvframe_chk_defrag: drop pkt\n"));
-#ifdef DBG_RX_DROP_FRAME
- RTW_INFO("DBG_RX_DROP_FRAME %s recvframe_chk_defrag: drop pkt\n", __FUNCTION__);
-#endif
+ #ifdef DBG_RX_DROP_FRAME
+ RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" recvframe_chk_defrag: drop pkt\n"
+ , FUNC_ADPT_ARG(padapter));
+ #endif
DBG_COUNTER(padapter->rx_logs.core_rx_post_defrag_err);
goto _recv_data_drop;
}
prframe = portctrl(padapter, prframe);
if (prframe == NULL) {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("portctrl: drop pkt\n"));
-#ifdef DBG_RX_DROP_FRAME
- RTW_INFO("DBG_RX_DROP_FRAME %s portctrl: drop pkt\n", __FUNCTION__);
-#endif
+ #ifdef DBG_RX_DROP_FRAME
+ RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" portctrl: drop pkt\n"
+ , FUNC_ADPT_ARG(padapter));
+ #endif
ret = _FAIL;
DBG_COUNTER(padapter->rx_logs.core_rx_post_portctrl_err);
goto _recv_data_drop;
@@ -4182,82 +4357,30 @@ int recv_func_posthandle(_adapter *padapter, union recv_frame *prframe)
rtw_wapi_update_info(padapter, prframe);
#endif
-#ifdef CONFIG_80211N_HT
- ret = process_recv_indicatepkts(padapter, prframe);
- if (ret != _SUCCESS) {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("recv_func: process_recv_indicatepkts fail!\n"));
-#ifdef DBG_RX_DROP_FRAME
- RTW_INFO("DBG_RX_DROP_FRAME %s process_recv_indicatepkts fail!\n", __FUNCTION__);
-#endif
- rtw_free_recvframe(orig_prframe, pfree_recv_queue);/* free this recv_frame */
- DBG_COUNTER(padapter->rx_logs.core_rx_post_indicate_err);
+#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL)
+ /* including perform A-MPDU Rx Ordering Buffer Control */
+ ret = recv_indicatepkt_reorder(padapter, prframe);
+ if (ret == _FAIL) {
+ rtw_free_recvframe(orig_prframe, pfree_recv_queue);
goto _recv_data_drop;
- }
-#else /* CONFIG_80211N_HT */
- if (!pattrib->amsdu) {
- ret = wlanhdr_to_ethhdr(prframe);
- if (ret != _SUCCESS) {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("wlanhdr_to_ethhdr: drop pkt\n"));
-#ifdef DBG_RX_DROP_FRAME
- RTW_INFO("DBG_RX_DROP_FRAME %s wlanhdr_to_ethhdr: drop pkt\n", __FUNCTION__);
+ } else if (ret == RTW_RX_HANDLED) /* queued OR indicated in order */
+ goto _exit_recv_func;
#endif
- rtw_free_recvframe(orig_prframe, pfree_recv_queue);/* free this recv_frame */
- goto _recv_data_drop;
- }
- if (!RTW_CANNOT_RUN(padapter)) {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_alert_, ("@@@@ recv_func: recv_func rtw_recv_indicatepkt\n"));
- /* indicate this recv_frame */
- ret = rtw_recv_indicatepkt(padapter, prframe);
- if (ret != _SUCCESS) {
-#ifdef DBG_RX_DROP_FRAME
- RTW_INFO("DBG_RX_DROP_FRAME %s rtw_recv_indicatepkt fail!\n", __FUNCTION__);
-#endif
- goto _recv_data_drop;
- }
- } else {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_alert_, ("@@@@ recv_func: rtw_free_recvframe\n"));
- RT_TRACE(_module_rtl871x_recv_c_, _drv_debug_, ("recv_func:bDriverStopped(%s) OR bSurpriseRemoved(%s)"
- , rtw_is_drv_stopped(padapter) ? "True" : "False"
- , rtw_is_surprise_removed(padapter) ? "True" : "False"));
-
-#ifdef DBG_RX_DROP_FRAME
- RTW_INFO("DBG_RX_DROP_FRAME %s recv_func:bDriverStopped(%s) OR bSurpriseRemoved(%s)\n", __func__
- , rtw_is_drv_stopped(padapter) ? "True" : "False"
- , rtw_is_surprise_removed(padapter) ? "True" : "False");
-#endif
- ret = _FAIL;
- rtw_free_recvframe(orig_prframe, pfree_recv_queue); /* free this recv_frame */
- }
-
- } else if (pattrib->amsdu == 1) {
-
- ret = amsdu_to_msdu(padapter, prframe);
- if (ret != _SUCCESS) {
-#ifdef DBG_RX_DROP_FRAME
- RTW_INFO("DBG_RX_DROP_FRAME %s amsdu_to_msdu fail\n", __FUNCTION__);
-#endif
- rtw_free_recvframe(orig_prframe, pfree_recv_queue);
- goto _recv_data_drop;
- }
- } else {
-#ifdef DBG_RX_DROP_FRAME
- RTW_INFO("DBG_RX_DROP_FRAME %s what is this condition??\n", __FUNCTION__);
-#endif
+ recv_set_iseq_before_mpdu_process(prframe, pattrib->seq_num, __func__);
+ ret = recv_process_mpdu(padapter, prframe);
+ recv_set_iseq_after_mpdu_process(prframe, pattrib->seq_num, __func__);
+ if (ret == _FAIL)
goto _recv_data_drop;
- }
-#endif /* CONFIG_80211N_HT */
_exit_recv_func:
return ret;
_recv_data_drop:
- precvpriv->rx_drop++;
+ precvpriv->dbg_rx_drop_count++;
return ret;
}
-
-int recv_func(_adapter *padapter, union recv_frame *rframe);
int recv_func(_adapter *padapter, union recv_frame *rframe)
{
int ret;
@@ -4268,7 +4391,9 @@ int recv_func(_adapter *padapter, union recv_frame *rframe)
if (check_fwstate(mlmepriv, WIFI_MONITOR_STATE)) {
/* monitor mode */
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))
recv_frame_monitor(padapter, rframe);
+#endif
ret = _SUCCESS;
goto exit;
} else
@@ -4328,9 +4453,7 @@ s32 rtw_recv_entry(union recv_frame *precvframe)
struct recv_priv *precvpriv;
s32 ret = _SUCCESS;
- _func_enter_;
- /* RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("+rtw_recv_entry\n")); */
padapter = precvframe->u.hdr.adapter;
@@ -4339,14 +4462,12 @@ s32 rtw_recv_entry(union recv_frame *precvframe)
ret = recv_func(padapter, precvframe);
if (ret == _FAIL) {
- RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("rtw_recv_entry: recv_func return fail!!!\n"));
goto _recv_entry_drop;
}
precvpriv->rx_pkts++;
- _func_exit_;
return ret;
@@ -4357,17 +4478,15 @@ s32 rtw_recv_entry(union recv_frame *precvframe)
padapter->mppriv.rx_pktloss = precvpriv->rx_drop;
#endif
- /* RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("_recv_entry_drop\n")); */
- _func_exit_;
return ret;
}
#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
-void rtw_signal_stat_timer_hdl(RTW_TIMER_HDL_ARGS)
+static void rtw_signal_stat_timer_hdl(void *ctx)
{
- _adapter *adapter = (_adapter *)FunctionContext;
+ _adapter *adapter = (_adapter *)ctx;
struct recv_priv *recvpriv = &adapter->recvpriv;
u32 tmp_s, tmp_q;
@@ -4471,7 +4590,7 @@ static void rx_process_rssi(_adapter *padapter, union recv_frame *prframe)
struct signal_stat *signal_stat = &padapter->recvpriv.signal_strength_data;
#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
- /* RTW_INFO("process_rssi=> pattrib->rssil(%d) signal_strength(%d)\n ",pattrib->RecvSignalPower,pattrib->signal_strength); */
+ /* RTW_INFO("process_rssi=> pattrib->rssil(%d) signal_strength(%d)\n ",pattrib->recv_signal_power,pattrib->signal_strength); */
/* if(pRfd->Status.bPacketToSelf || pRfd->Status.bPacketBeacon) */
{
#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
@@ -4482,7 +4601,7 @@ static void rx_process_rssi(_adapter *padapter, union recv_frame *prframe)
}
signal_stat->total_num++;
- signal_stat->total_val += pattrib->phy_info.SignalStrength;
+ signal_stat->total_val += pattrib->phy_info.signal_strength;
signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num;
#else /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
@@ -4492,9 +4611,9 @@ static void rx_process_rssi(_adapter *padapter, union recv_frame *prframe)
last_rssi = padapter->recvpriv.signal_strength_data.elements[padapter->recvpriv.signal_strength_data.index];
padapter->recvpriv.signal_strength_data.total_val -= last_rssi;
}
- padapter->recvpriv.signal_strength_data.total_val += pattrib->phy_info.SignalStrength;
+ padapter->recvpriv.signal_strength_data.total_val += pattrib->phy_info.signal_strength;
- padapter->recvpriv.signal_strength_data.elements[padapter->recvpriv.signal_strength_data.index++] = pattrib->phy_info.SignalStrength;
+ padapter->recvpriv.signal_strength_data.elements[padapter->recvpriv.signal_strength_data.index++] = pattrib->phy_info.signal_strength;
if (padapter->recvpriv.signal_strength_data.index >= PHY_RSSI_SLID_WIN_MAX)
padapter->recvpriv.signal_strength_data.index = 0;
@@ -4509,8 +4628,6 @@ static void rx_process_rssi(_adapter *padapter, union recv_frame *prframe)
padapter->recvpriv.rssi = (s8)translate_percentage_to_dbm(tmp_val);
}
- RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("UI RSSI = %d, ui_rssi.TotalVal = %d, ui_rssi.TotalNum = %d\n", tmp_val, padapter->recvpriv.signal_strength_data.total_val,
- padapter->recvpriv.signal_strength_data.total_num));
#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
}
}
@@ -4541,11 +4658,11 @@ static void rx_process_link_qual(_adapter *padapter, union recv_frame *prframe)
}
signal_stat->total_num++;
- signal_stat->total_val += pattrib->phy_info.SignalQuality;
+ signal_stat->total_val += pattrib->phy_info.signal_quality;
signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num;
#else /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
- if (pattrib->phy_info.SignalQuality != 0) {
+ if (pattrib->phy_info.signal_quality != 0) {
/* */
/* 1. Record the general EVM to the sliding window. */
/* */
@@ -4554,20 +4671,18 @@ static void rx_process_link_qual(_adapter *padapter, union recv_frame *prframe)
last_evm = padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index];
padapter->recvpriv.signal_qual_data.total_val -= last_evm;
}
- padapter->recvpriv.signal_qual_data.total_val += pattrib->phy_info.SignalQuality;
+ padapter->recvpriv.signal_qual_data.total_val += pattrib->phy_info.signal_quality;
- padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index++] = pattrib->phy_info.SignalQuality;
+ padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index++] = pattrib->phy_info.signal_quality;
if (padapter->recvpriv.signal_qual_data.index >= PHY_LINKQUALITY_SLID_WIN_MAX)
padapter->recvpriv.signal_qual_data.index = 0;
- RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("Total SQ=%d pattrib->signal_qual= %d\n", padapter->recvpriv.signal_qual_data.total_val, pattrib->phy_info.SignalQuality));
/* <1> Showed on UI for user, in percentage. */
tmpVal = padapter->recvpriv.signal_qual_data.total_val / padapter->recvpriv.signal_qual_data.total_num;
padapter->recvpriv.signal_qual = (u8)tmpVal;
- } else
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, (" pattrib->signal_qual =%d\n", pattrib->phy_info.SignalQuality));
+ }
#endif /* CONFIG_NEW_SIGNAL_STAT_PROCESS */
}
@@ -4593,47 +4708,36 @@ void rx_query_phy_status(
PADAPTER padapter = precvframe->u.hdr.adapter;
struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
- PODM_PHY_INFO_T pPHYInfo = (PODM_PHY_INFO_T)(&pattrib->phy_info);
+ struct phydm_phyinfo_struct *p_phy_info = &pattrib->phy_info;
u8 *wlanhdr;
- ODM_PACKET_INFO_T pkt_info;
- u8 *sa;
+ struct phydm_perpkt_info_struct pkt_info;
+ u8 *ta, *ra;
+ u8 is_ra_bmc;
struct sta_priv *pstapriv;
struct sta_info *psta = NULL;
- struct dvobj_priv *psdpriv = padapter->dvobj;
- struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
+ struct recv_priv *precvpriv = &padapter->recvpriv;
/* _irqL irqL; */
- pkt_info.bPacketMatchBSSID = _FALSE;
- pkt_info.bPacketToSelf = _FALSE;
- pkt_info.bPacketBeacon = _FALSE;
+ pkt_info.is_packet_match_bssid = _FALSE;
+ pkt_info.is_packet_to_self = _FALSE;
+ pkt_info.is_packet_beacon = _FALSE;
+ pkt_info.ppdu_cnt = pattrib->ppdu_cnt;
+ pkt_info.station_id = 0xFF;
wlanhdr = get_recvframe_data(precvframe);
- pkt_info.bPacketMatchBSSID = (!IsFrameTypeCtrl(wlanhdr))
- && (!pattrib->icv_err) && (!pattrib->crc_err)
- && _rtw_memcmp(get_hdr_bssid(wlanhdr), get_bssid(&padapter->mlmepriv), ETH_ALEN);
-
- pkt_info.bToSelf = (!pattrib->icv_err) && (!pattrib->crc_err)
- && _rtw_memcmp(get_ra(wlanhdr), adapter_mac_addr(padapter), ETH_ALEN);
-
- pkt_info.bPacketToSelf = pkt_info.bPacketMatchBSSID
- && _rtw_memcmp(get_ra(wlanhdr), adapter_mac_addr(padapter), ETH_ALEN);
+ ta = get_ta(wlanhdr);
+ ra = get_ra(wlanhdr);
+ is_ra_bmc = IS_MCAST(ra);
- pkt_info.bPacketBeacon = pkt_info.bPacketMatchBSSID
- && (GetFrameSubType(wlanhdr) == WIFI_BEACON);
-
- sa = get_ta(wlanhdr);
-
- pkt_info.StationID = 0xFF;
-
- if (_rtw_memcmp(adapter_mac_addr(padapter), sa, ETH_ALEN) == _TRUE) {
- static u32 start_time = 0;
+ if (_rtw_memcmp(adapter_mac_addr(padapter), ta, ETH_ALEN) == _TRUE) {
+ static systime start_time = 0;
#if 0 /*For debug */
if (IsFrameTypeCtrl(wlanhdr)) {
RTW_INFO("-->Control frame: Y\n");
RTW_INFO("-->pkt_len: %d\n", pattrib->pkt_len);
- RTW_INFO("-->Sub Type = 0x%X\n", GetFrameSubType(wlanhdr));
+ RTW_INFO("-->Sub Type = 0x%X\n", get_frame_sub_type(wlanhdr));
}
/* Dump first 40 bytes of header */
@@ -4649,38 +4753,61 @@ void rx_query_phy_status(
RTW_PRINT("Warning!!! %s: Confilc mac addr!!\n", __func__);
start_time = rtw_get_current_time();
}
- pdbgpriv->dbg_rx_conflic_mac_addr_cnt++;
+ precvpriv->dbg_rx_conflic_mac_addr_cnt++;
} else {
pstapriv = &padapter->stapriv;
- psta = rtw_get_stainfo(pstapriv, sa);
+ psta = rtw_get_stainfo(pstapriv, ta);
if (psta)
- pkt_info.StationID = psta->mac_id;
+ pkt_info.station_id = psta->cmn.mac_id;
}
- pkt_info.DataRate = pattrib->data_rate;
+ pkt_info.is_packet_match_bssid = (!IsFrameTypeCtrl(wlanhdr))
+ && (!pattrib->icv_err) && (!pattrib->crc_err)
+ && ((!MLME_IS_MESH(padapter) && _rtw_memcmp(get_hdr_bssid(wlanhdr), get_bssid(&padapter->mlmepriv), ETH_ALEN))
+ || (MLME_IS_MESH(padapter) && psta));
- /* _enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */
- ODM_PhyStatusQuery(&pHalData->odmpriv, pPHYInfo, pphy_status, &pkt_info);
- if (psta)
- psta->rssi = pattrib->phy_info.RecvSignalPower;
- /* _exit_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */
+ pkt_info.is_to_self = (!pattrib->icv_err) && (!pattrib->crc_err)
+ && _rtw_memcmp(ra, adapter_mac_addr(padapter), ETH_ALEN);
+
+ pkt_info.is_packet_to_self = pkt_info.is_packet_match_bssid
+ && _rtw_memcmp(ra, adapter_mac_addr(padapter), ETH_ALEN);
+
+ pkt_info.is_packet_beacon = pkt_info.is_packet_match_bssid
+ && (get_frame_sub_type(wlanhdr) == WIFI_BEACON);
+
+ if (psta && IsFrameTypeData(wlanhdr)) {
+ if (is_ra_bmc)
+ psta->curr_rx_rate_bmc = pattrib->data_rate;
+ else
+ psta->curr_rx_rate = pattrib->data_rate;
+ }
+ pkt_info.data_rate = pattrib->data_rate;
+
+ odm_phy_status_query(&pHalData->odmpriv, p_phy_info, pphy_status, &pkt_info);
+
+ /* If bw is initial value, get from phy status */
+ if (pattrib->bw == CHANNEL_WIDTH_MAX)
+ pattrib->bw = p_phy_info->band_width;
{
precvframe->u.hdr.psta = NULL;
- if (pkt_info.bPacketMatchBSSID
- && (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE)
- ) {
+ if ((!MLME_IS_MESH(padapter) && pkt_info.is_packet_match_bssid)
+ || (MLME_IS_MESH(padapter) && psta)
+ || padapter->registrypriv.mp_mode == 1
+ ) {
if (psta) {
precvframe->u.hdr.psta = psta;
rx_process_phy_info(padapter, precvframe);
}
- } else if (pkt_info.bPacketToSelf || pkt_info.bPacketBeacon) {
+ } else if (pkt_info.is_packet_to_self || pkt_info.is_packet_beacon) {
if (psta)
precvframe->u.hdr.psta = psta;
rx_process_phy_info(padapter, precvframe);
}
}
+
+ rtw_odm_parse_rx_phy_status_chinfo(precvframe, pphy_status);
}
/*
* Increase and check if the continual_no_rx_packet of this @param pmlmepriv is larger than MAX_CONTINUAL_NORXPACKET_COUNT
@@ -4707,19 +4834,36 @@ void rtw_reset_continual_no_rx_packet(struct sta_info *sta, int tid_index)
ATOMIC_SET(&sta->continual_no_rx_packet[tid_index], 0);
}
+u8 adapter_allow_bmc_data_rx(_adapter *adapter)
+{
+ if (check_fwstate(&adapter->mlmepriv, WIFI_MONITOR_STATE | WIFI_MP_STATE) == _TRUE)
+ return 1;
+
+ if (MLME_IS_AP(adapter))
+ return 0;
+
+ if (rtw_linked_check(adapter) == _FALSE)
+ return 0;
+
+ return 1;
+}
s32 pre_recv_entry(union recv_frame *precvframe, u8 *pphy_status)
{
s32 ret = _SUCCESS;
-#ifdef CONFIG_CONCURRENT_MODE
- u8 *pda;
u8 *pbuf = precvframe->u.hdr.rx_data;
+ u8 *pda = get_ra(pbuf);
+ u8 ra_is_bmc = IS_MCAST(pda);
+#ifdef CONFIG_CONCURRENT_MODE
_adapter *iface = NULL;
_adapter *primary_padapter = precvframe->u.hdr.adapter;
- pda = get_ra(pbuf);
+ #ifdef CONFIG_MP_INCLUDED
+ if (rtw_mp_mode_check(primary_padapter))
+ goto bypass_concurrent_hdl;
+ #endif
- if (IS_MCAST(pda) == _FALSE) { /*unicast packets*/
+ if (ra_is_bmc == _FALSE) { /*unicast packets*/
iface = rtw_get_iface_by_macddr(primary_padapter , pda);
if (NULL == iface) {
RTW_INFO("%s [WARN] Cannot find appropriate adapter - mac_addr : "MAC_FMT"\n", __func__, MAC_ARG(pda));
@@ -4728,7 +4872,125 @@ s32 pre_recv_entry(union recv_frame *precvframe, u8 *pphy_status)
precvframe->u.hdr.adapter = iface;
} else /* Handle BC/MC Packets */
rtw_mi_buddy_clone_bcmc_packet(primary_padapter, precvframe, pphy_status);
-#endif
+bypass_concurrent_hdl:
+#endif /* CONFIG_CONCURRENT_MODE */
+
+ /* skip unnecessary bmc data frame for primary adapter */
+ if (ra_is_bmc == _TRUE && GetFrameType(pbuf) == WIFI_DATA_TYPE
+ && !adapter_allow_bmc_data_rx(precvframe->u.hdr.adapter)
+ ) {
+ rtw_free_recvframe(precvframe, &precvframe->u.hdr.adapter->recvpriv.free_recv_queue);
+ goto exit;
+ }
+
+ if (pphy_status)
+ rx_query_phy_status(precvframe, pphy_status);
+ ret = rtw_recv_entry(precvframe);
+exit:
return ret;
}
+
+#ifdef CONFIG_RECV_THREAD_MODE
+thread_return rtw_recv_thread(thread_context context)
+{
+ _adapter *adapter = (_adapter *)context;
+ struct recv_priv *recvpriv = &adapter->recvpriv;
+ s32 err = _SUCCESS;
+#ifdef PLATFORM_LINUX
+ struct sched_param param = { .sched_priority = 1 };
+
+ sched_setscheduler(current, SCHED_FIFO, ¶m);
+#endif /* PLATFORM_LINUX */
+ thread_enter("RTW_RECV_THREAD");
+
+ RTW_INFO(FUNC_ADPT_FMT" enter\n", FUNC_ADPT_ARG(adapter));
+
+ do {
+ err = _rtw_down_sema(&recvpriv->recv_sema);
+ if (_FAIL == err) {
+ RTW_ERR(FUNC_ADPT_FMT" down recv_sema fail!\n", FUNC_ADPT_ARG(adapter));
+ goto exit;
+ }
+
+ if (RTW_CANNOT_RUN(adapter)) {
+ RTW_DBG(FUNC_ADPT_FMT "- bDriverStopped(%s) bSurpriseRemoved(%s)\n",
+ FUNC_ADPT_ARG(adapter),
+ rtw_is_drv_stopped(adapter) ? "True" : "False",
+ rtw_is_surprise_removed(adapter) ? "True" : "False");
+ goto exit;
+ }
+
+ err = rtw_hal_recv_hdl(adapter);
+
+ if (err == RTW_RFRAME_UNAVAIL
+ || err == RTW_RFRAME_PKT_UNAVAIL
+ ) {
+ rtw_msleep_os(1);
+ _rtw_up_sema(&recvpriv->recv_sema);
+ }
+
+ flush_signals_thread();
+
+ } while (err != _FAIL);
+
+exit:
+
+ RTW_INFO(FUNC_ADPT_FMT " Exit\n", FUNC_ADPT_ARG(adapter));
+
+ rtw_thread_wait_stop();
+
+ return 0;
+}
+#endif /* CONFIG_RECV_THREAD_MODE */
+
+#if DBG_RX_BH_TRACKING
+void rx_bh_tk_set_stage(struct recv_priv *recv, u32 s)
+{
+ recv->rx_bh_stage = s;
+}
+
+void rx_bh_tk_set_buf(struct recv_priv *recv, void *buf, void *data, u32 dlen)
+{
+ if (recv->rx_bh_cbuf)
+ recv->rx_bh_lbuf = recv->rx_bh_cbuf;
+ recv->rx_bh_cbuf = buf;
+ if (buf) {
+ recv->rx_bh_cbuf_data = data;
+ recv->rx_bh_cbuf_dlen = dlen;
+ recv->rx_bh_buf_dq_cnt++;
+ } else {
+ recv->rx_bh_cbuf_data = NULL;
+ recv->rx_bh_cbuf_dlen = 0;
+ }
+}
+
+void rx_bh_tk_set_buf_pos(struct recv_priv *recv, void *pos)
+{
+ if (recv->rx_bh_cbuf) {
+ recv->rx_bh_cbuf_pos = pos - recv->rx_bh_cbuf_data;
+ } else {
+ rtw_warn_on(1);
+ recv->rx_bh_cbuf_pos = 0;
+ }
+}
+
+void rx_bh_tk_set_frame(struct recv_priv *recv, void *frame)
+{
+ recv->rx_bh_cframe = frame;
+}
+
+void dump_rx_bh_tk(void *sel, struct recv_priv *recv)
+{
+ RTW_PRINT_SEL(sel, "[RXBHTK]s:%u, buf_dqc:%u, lbuf:%p, cbuf:%p, dlen:%u, pos:%u, cframe:%p\n"
+ , recv->rx_bh_stage
+ , recv->rx_bh_buf_dq_cnt
+ , recv->rx_bh_lbuf
+ , recv->rx_bh_cbuf
+ , recv->rx_bh_cbuf_dlen
+ , recv->rx_bh_cbuf_pos
+ , recv->rx_bh_cframe
+ );
+}
+#endif /* DBG_RX_BH_TRACKING */
+
diff --git a/core/rtw_rf.c b/core/rtw_rf.c
index 667383a..1c57c91 100644
--- a/core/rtw_rf.c
+++ b/core/rtw_rf.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,24 +11,19 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#define _RTW_RF_C_
#include
#include
u8 center_ch_2g[CENTER_CH_2G_NUM] = {
- /* G00 */1, 2,
- /* G01 */3, 4, 5,
- /* G02 */6, 7, 8,
- /* G03 */9, 10, 11,
- /* G04 */12, 13,
- /* G05 */14
+/* G00 */1, 2,
+/* G01 */3, 4, 5,
+/* G02 */6, 7, 8,
+/* G03 */9, 10, 11,
+/* G04 */12, 13,
+/* G05 */14
};
u8 center_ch_2g_40m[CENTER_CH_2G_40M_NUM] = {
@@ -56,64 +51,81 @@ u8 op_chs_of_cch_2g_40m[CENTER_CH_2G_40M_NUM][2] = {
};
u8 center_ch_5g_all[CENTER_CH_5G_ALL_NUM] = {
- /* G00 */36, 38, 40,
+/* G00 */36, 38, 40,
42,
- /* G01 */44, 46, 48,
+/* G01 */44, 46, 48,
/* 50, */
- /* G02 */52, 54, 56,
+/* G02 */52, 54, 56,
58,
- /* G03 */60, 62, 64,
- /* G04 */100, 102, 104,
+/* G03 */60, 62, 64,
+/* G04 */100, 102, 104,
106,
- /* G05 */108, 110, 112,
+/* G05 */108, 110, 112,
/* 114, */
- /* G06 */116, 118, 120,
+/* G06 */116, 118, 120,
122,
- /* G07 */124, 126, 128,
- /* G08 */132, 134, 136,
+/* G07 */124, 126, 128,
+/* G08 */132, 134, 136,
138,
- /* G09 */140, 142, 144,
- /* G10 */149, 151, 153,
+/* G09 */140, 142, 144,
+/* G10 */149, 151, 153,
155,
- /* G11 */157, 159, 161,
+/* G11 */157, 159, 161,
/* 163, */
- /* G12 */165, 167, 169,
+/* G12 */165, 167, 169,
171,
- /* G13 */173, 175, 177
+/* G13 */173, 175, 177
};
u8 center_ch_5g_20m[CENTER_CH_5G_20M_NUM] = {
- /* G00 */36, 40,
- /* G01 */44, 48,
- /* G02 */52, 56,
- /* G03 */60, 64,
- /* G04 */100, 104,
- /* G05 */108, 112,
- /* G06 */116, 120,
- /* G07 */124, 128,
- /* G08 */132, 136,
- /* G09 */140, 144,
- /* G10 */149, 153,
- /* G11 */157, 161,
- /* G12 */165, 169,
- /* G13 */173, 177
+/* G00 */36, 40,
+/* G01 */44, 48,
+/* G02 */52, 56,
+/* G03 */60, 64,
+/* G04 */100, 104,
+/* G05 */108, 112,
+/* G06 */116, 120,
+/* G07 */124, 128,
+/* G08 */132, 136,
+/* G09 */140, 144,
+/* G10 */149, 153,
+/* G11 */157, 161,
+/* G12 */165, 169,
+/* G13 */173, 177
};
u8 center_ch_5g_40m[CENTER_CH_5G_40M_NUM] = {
- /* G00 */38,
- /* G01 */46,
- /* G02 */54,
- /* G03 */62,
- /* G04 */102,
- /* G05 */110,
- /* G06 */118,
- /* G07 */126,
- /* G08 */134,
- /* G09 */142,
- /* G10 */151,
- /* G11 */159,
- /* G12 */167,
- /* G13 */175
+/* G00 */38,
+/* G01 */46,
+/* G02 */54,
+/* G03 */62,
+/* G04 */102,
+/* G05 */110,
+/* G06 */118,
+/* G07 */126,
+/* G08 */134,
+/* G09 */142,
+/* G10 */151,
+/* G11 */159,
+/* G12 */167,
+/* G13 */175
+};
+
+u8 center_ch_5g_20m_40m[CENTER_CH_5G_20M_NUM + CENTER_CH_5G_40M_NUM] = {
+/* G00 */36, 38, 40,
+/* G01 */44, 46, 48,
+/* G02 */52, 54, 56,
+/* G03 */60, 62, 64,
+/* G04 */100, 102, 104,
+/* G05 */108, 110, 112,
+/* G06 */116, 118, 120,
+/* G07 */124, 126, 128,
+/* G08 */132, 134, 136,
+/* G09 */140, 142, 144,
+/* G10 */149, 151, 153,
+/* G11 */157, 159, 161,
+/* G12 */165, 167, 169,
+/* G13 */173, 175, 177
};
u8 op_chs_of_cch_5g_40m[CENTER_CH_5G_40M_NUM][2] = {
@@ -134,13 +146,13 @@ u8 op_chs_of_cch_5g_40m[CENTER_CH_5G_40M_NUM][2] = {
};
u8 center_ch_5g_80m[CENTER_CH_5G_80M_NUM] = {
- /* G00 ~ G01*/42,
- /* G02 ~ G03*/58,
- /* G04 ~ G05*/106,
- /* G06 ~ G07*/122,
- /* G08 ~ G09*/138,
- /* G10 ~ G11*/155,
- /* G12 ~ G13*/171
+/* G00 ~ G01*/42,
+/* G02 ~ G03*/58,
+/* G04 ~ G05*/106,
+/* G06 ~ G07*/122,
+/* G08 ~ G09*/138,
+/* G10 ~ G11*/155,
+/* G12 ~ G13*/171
};
u8 op_chs_of_cch_5g_80m[CENTER_CH_5G_80M_NUM][4] = {
@@ -154,9 +166,9 @@ u8 op_chs_of_cch_5g_80m[CENTER_CH_5G_80M_NUM][4] = {
};
u8 center_ch_5g_160m[CENTER_CH_5G_160M_NUM] = {
- /* G00 ~ G03*/50,
- /* G04 ~ G07*/114,
- /* G10 ~ G13*/163
+/* G00 ~ G03*/50,
+/* G04 ~ G07*/114,
+/* G10 ~ G13*/163
};
u8 op_chs_of_cch_5g_160m[CENTER_CH_5G_160M_NUM][8] = {
@@ -182,6 +194,59 @@ struct center_chs_ent_t center_chs_5g_by_bw[] = {
{CENTER_CH_5G_160M_NUM, center_ch_5g_160m},
};
+/*
+ * Get center channel of smaller bandwidth by @param cch, @param bw, @param offset
+ * @cch: the given center channel
+ * @bw: the given bandwidth
+ * @offset: the given primary SC offset of the given bandwidth
+ *
+ * return center channel of smaller bandiwdth if valid, or 0
+ */
+u8 rtw_get_scch_by_cch_offset(u8 cch, u8 bw, u8 offset)
+{
+ int i;
+ u8 t_cch = 0;
+
+ if (bw == CHANNEL_WIDTH_20) {
+ t_cch = cch;
+ goto exit;
+ }
+
+ if (offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) {
+ rtw_warn_on(1);
+ goto exit;
+ }
+
+ /* 2.4G, 40MHz */
+ if (cch >= 3 && cch <= 11 && bw == CHANNEL_WIDTH_40) {
+ t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 2 : cch - 2;
+ goto exit;
+ }
+
+ /* 5G, 160MHz */
+ if (cch >= 50 && cch <= 163 && bw == CHANNEL_WIDTH_160) {
+ t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 8 : cch - 8;
+ goto exit;
+
+ /* 5G, 80MHz */
+ } else if (cch >= 42 && cch <= 171 && bw == CHANNEL_WIDTH_80) {
+ t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 4 : cch - 4;
+ goto exit;
+
+ /* 5G, 40MHz */
+ } else if (cch >= 38 && cch <= 175 && bw == CHANNEL_WIDTH_40) {
+ t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 2 : cch - 2;
+ goto exit;
+
+ } else {
+ rtw_warn_on(1);
+ goto exit;
+ }
+
+exit:
+ return t_cch;
+}
+
struct op_chs_ent_t {
u8 ch_num;
u8 *chs;
@@ -199,15 +264,36 @@ struct op_chs_ent_t op_chs_of_cch_5g_by_bw[] = {
{8, (u8 *)op_chs_of_cch_5g_160m},
};
-inline u8 center_chs_5g_num(u8 bw) {
- if (bw >= CHANNEL_WIDTH_160)
+inline u8 center_chs_2g_num(u8 bw)
+{
+ if (bw > CHANNEL_WIDTH_40)
+ return 0;
+
+ return center_chs_2g_by_bw[bw].ch_num;
+}
+
+inline u8 center_chs_2g(u8 bw, u8 id)
+{
+ if (bw > CHANNEL_WIDTH_40)
+ return 0;
+
+ if (id >= center_chs_2g_num(bw))
+ return 0;
+
+ return center_chs_2g_by_bw[bw].chs[id];
+}
+
+inline u8 center_chs_5g_num(u8 bw)
+{
+ if (bw > CHANNEL_WIDTH_80)
return 0;
return center_chs_5g_by_bw[bw].ch_num;
}
-inline u8 center_chs_5g(u8 bw, u8 id) {
- if (bw >= CHANNEL_WIDTH_160)
+inline u8 center_chs_5g(u8 bw, u8 id)
+{
+ if (bw > CHANNEL_WIDTH_80)
return 0;
if (id >= center_chs_5g_num(bw))
@@ -225,20 +311,21 @@ inline u8 center_chs_5g(u8 bw, u8 id) {
*
* return valid (1) or not (0)
*/
-u8 rtw_get_op_chs_by_cch_bw(u8 cch, u8 bw, u8 **op_chs, u8 *op_ch_num) {
+u8 rtw_get_op_chs_by_cch_bw(u8 cch, u8 bw, u8 **op_chs, u8 *op_ch_num)
+{
int i;
struct center_chs_ent_t *c_chs_ent = NULL;
struct op_chs_ent_t *op_chs_ent = NULL;
u8 valid = 1;
if (cch <= 14
- && bw >= CHANNEL_WIDTH_20 && bw <= CHANNEL_WIDTH_40
- ) {
+ && bw >= CHANNEL_WIDTH_20 && bw <= CHANNEL_WIDTH_40
+ ) {
c_chs_ent = ¢er_chs_2g_by_bw[bw];
op_chs_ent = &op_chs_of_cch_2g_by_bw[bw];
} else if (cch >= 36 && cch <= 177
- && bw >= CHANNEL_WIDTH_20 && bw <= CHANNEL_WIDTH_160
- ) {
+ && bw >= CHANNEL_WIDTH_20 && bw <= CHANNEL_WIDTH_160
+ ) {
c_chs_ent = ¢er_chs_5g_by_bw[bw];
op_chs_ent = &op_chs_of_cch_5g_by_bw[bw];
} else {
@@ -262,7 +349,86 @@ u8 rtw_get_op_chs_by_cch_bw(u8 cch, u8 bw, u8 **op_chs, u8 *op_ch_num) {
return valid;
}
-int rtw_ch2freq(int chan) {
+u8 rtw_get_ch_group(u8 ch, u8 *group, u8 *cck_group)
+{
+ BAND_TYPE band = BAND_MAX;
+ s8 gp = -1, cck_gp = -1;
+
+ if (ch <= 14) {
+ band = BAND_ON_2_4G;
+
+ if (1 <= ch && ch <= 2)
+ gp = 0;
+ else if (3 <= ch && ch <= 5)
+ gp = 1;
+ else if (6 <= ch && ch <= 8)
+ gp = 2;
+ else if (9 <= ch && ch <= 11)
+ gp = 3;
+ else if (12 <= ch && ch <= 14)
+ gp = 4;
+ else
+ band = BAND_MAX;
+
+ if (ch == 14)
+ cck_gp = 5;
+ else
+ cck_gp = gp;
+ } else {
+ band = BAND_ON_5G;
+
+ if (36 <= ch && ch <= 42)
+ gp = 0;
+ else if (44 <= ch && ch <= 48)
+ gp = 1;
+ else if (50 <= ch && ch <= 58)
+ gp = 2;
+ else if (60 <= ch && ch <= 64)
+ gp = 3;
+ else if (100 <= ch && ch <= 106)
+ gp = 4;
+ else if (108 <= ch && ch <= 114)
+ gp = 5;
+ else if (116 <= ch && ch <= 122)
+ gp = 6;
+ else if (124 <= ch && ch <= 130)
+ gp = 7;
+ else if (132 <= ch && ch <= 138)
+ gp = 8;
+ else if (140 <= ch && ch <= 144)
+ gp = 9;
+ else if (149 <= ch && ch <= 155)
+ gp = 10;
+ else if (157 <= ch && ch <= 161)
+ gp = 11;
+ else if (165 <= ch && ch <= 171)
+ gp = 12;
+ else if (173 <= ch && ch <= 177)
+ gp = 13;
+ else
+ band = BAND_MAX;
+ }
+
+ if (band == BAND_MAX
+ || (band == BAND_ON_2_4G && cck_gp == -1)
+ || gp == -1
+ ) {
+ RTW_WARN("%s invalid channel:%u", __func__, ch);
+ rtw_warn_on(1);
+ goto exit;
+ }
+
+ if (group)
+ *group = gp;
+ if (cck_group && band == BAND_ON_2_4G)
+ *cck_group = cck_gp;
+
+exit:
+ return band;
+}
+
+int rtw_ch2freq(int chan)
+{
/* see 802.11 17.3.8.3.2 and Annex J
* there are overlapping channel numbers in 5GHz and 2GHz bands */
@@ -282,7 +448,8 @@ int rtw_ch2freq(int chan) {
return 0; /* not supported */
}
-int rtw_freq2ch(int freq) {
+int rtw_freq2ch(int freq)
+{
/* see 802.11 17.3.8.3.2 and Annex J */
if (freq == 2484)
return 14;
@@ -298,7 +465,8 @@ int rtw_freq2ch(int freq) {
return 0;
}
-bool rtw_chbw_to_freq_range(u8 ch, u8 bw, u8 offset, u32 *hi, u32 *lo) {
+bool rtw_chbw_to_freq_range(u8 ch, u8 bw, u8 offset, u32 *hi, u32 *lo)
+{
u8 c_ch;
u32 freq;
u32 hi_ret = 0, lo_ret = 0;
@@ -341,22 +509,24 @@ bool rtw_chbw_to_freq_range(u8 ch, u8 bw, u8 offset, u32 *hi, u32 *lo) {
return valid;
}
-const char *const _ch_width_str[] = {
+const char *const _ch_width_str[CHANNEL_WIDTH_MAX] = {
"20MHz",
"40MHz",
"80MHz",
"160MHz",
"80_80MHz",
- "CHANNEL_WIDTH_MAX",
+ "5MHz",
+ "10MHz",
};
-const u8 _ch_width_to_bw_cap[] = {
+const u8 _ch_width_to_bw_cap[CHANNEL_WIDTH_MAX] = {
BW_CAP_20M,
BW_CAP_40M,
BW_CAP_80M,
BW_CAP_160M,
BW_CAP_80_80M,
- 0,
+ BW_CAP_5M,
+ BW_CAP_10M,
};
const char *const _band_str[] = {
@@ -373,6 +543,30 @@ const u8 _band_to_band_cap[] = {
0,
};
+const u8 _rf_type_to_rf_tx_cnt[] = {
+ 1, /*RF_1T1R*/
+ 1, /*RF_1T2R*/
+ 2, /*RF_2T2R*/
+ 2, /*RF_2T3R*/
+ 2, /*RF_2T4R*/
+ 3, /*RF_3T3R*/
+ 3, /*RF_3T4R*/
+ 4, /*RF_4T4R*/
+ 1, /*RF_TYPE_MAX*/
+};
+
+const u8 _rf_type_to_rf_rx_cnt[] = {
+ 1, /*RF_1T1R*/
+ 2, /*RF_1T2R*/
+ 2, /*RF_2T2R*/
+ 3, /*RF_2T3R*/
+ 4, /*RF_2T4R*/
+ 3, /*RF_3T3R*/
+ 4, /*RF_3T4R*/
+ 4, /*RF_4T4R*/
+ 1, /*RF_TYPE_MAX*/
+};
+
#ifdef CONFIG_80211AC_VHT
#define COUNTRY_CHPLAN_ASSIGN_EN_11AC(_val) , .en_11ac = (_val)
#else
@@ -388,8 +582,8 @@ const u8 _band_to_band_cap[] = {
/* has def_module_flags specified, used by common map and HAL dfference map */
#define COUNTRY_CHPLAN_ENT(_alpha2, _chplan, _en_11ac, _def_module_flags) \
{.alpha2 = (_alpha2), .chplan = (_chplan) \
- COUNTRY_CHPLAN_ASSIGN_EN_11AC(_en_11ac) \
- COUNTRY_CHPLAN_ASSIGN_DEF_MODULE_FLAGS(_def_module_flags) \
+ COUNTRY_CHPLAN_ASSIGN_EN_11AC(_en_11ac) \
+ COUNTRY_CHPLAN_ASSIGN_DEF_MODULE_FLAGS(_def_module_flags) \
}
#ifdef CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP
@@ -398,57 +592,98 @@ const u8 _band_to_band_cap[] = {
#elif RTW_DEF_MODULE_REGULATORY_CERT
-#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8821AE_HMC_M2)
-static const struct country_chplan RTL8821AE_HMC_M2_country_chplan_map[] = {
- COUNTRY_CHPLAN_ENT("CN", 0x51, 1, 0xFB), /* China */
- COUNTRY_CHPLAN_ENT("RU", 0x59, 0, 0xFB), /* Russia(fac/gost), Kaliningrad */
- COUNTRY_CHPLAN_ENT("UA", 0x26, 0, 0xFB), /* Ukraine */
+/* leave def_module_flags empty, def_module_flags check is done on country_chplan_map */
+#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8821AE_HMC_M2) /* 2013 certify */
+static const struct country_chplan RTL8821AE_HMC_M2_country_chplan_exc_map[] = {
+ COUNTRY_CHPLAN_ENT("CA", 0x34, 1, 0), /* Canada */
+ COUNTRY_CHPLAN_ENT("CL", 0x30, 1, 0), /* Chile */
+ COUNTRY_CHPLAN_ENT("CN", 0x51, 1, 0), /* China */
+ COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0), /* Mexico */
+ COUNTRY_CHPLAN_ENT("MY", 0x47, 1, 0), /* Malaysia */
+ COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */
+ COUNTRY_CHPLAN_ENT("UA", 0x36, 0, 0), /* Ukraine */
+ COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */
};
-static const u16 RTL8821AE_HMC_M2_country_chplan_map_sz = sizeof(RTL8821AE_HMC_M2_country_chplan_map) / sizeof(struct country_chplan);
#endif
-#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8821AU)
-static const struct country_chplan RTL8821AU_country_chplan_map[] = {
- COUNTRY_CHPLAN_ENT("RU", 0x59, 0, 0xFB), /* Russia(fac/gost), Kaliningrad */
- COUNTRY_CHPLAN_ENT("UA", 0x26, 0, 0xFB), /* Ukraine */
+#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8821AU) /* 2014 certify */
+static const struct country_chplan RTL8821AU_country_chplan_exc_map[] = {
+ COUNTRY_CHPLAN_ENT("CA", 0x34, 1, 0), /* Canada */
+ COUNTRY_CHPLAN_ENT("RU", 0x59, 0, 0), /* Russia(fac/gost), Kaliningrad */
+ COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */
+ COUNTRY_CHPLAN_ENT("UA", 0x36, 0, 0), /* Ukraine */
+ COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */
};
-static const u16 RTL8821AU_country_chplan_map_sz = sizeof(RTL8821AU_country_chplan_map) / sizeof(struct country_chplan);
#endif
-#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8812AENF_NGFF)
-static const struct country_chplan RTL8812AENF_NGFF_country_chplan_map[] = {
+#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8812AENF_NGFF) /* 2014 certify */
+static const struct country_chplan RTL8812AENF_NGFF_country_chplan_exc_map[] = {
+ COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */
+ COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */
};
-static const u16 RTL8812AENF_NGFF_country_chplan_map_sz = sizeof(RTL8812AENF_NGFF_country_chplan_map) / sizeof(struct country_chplan);
#endif
-#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8812AEBT_HMC)
-static const struct country_chplan RTL8812AEBT_HMC_country_chplan_map[] = {
+#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8812AEBT_HMC) /* 2013 certify */
+static const struct country_chplan RTL8812AEBT_HMC_country_chplan_exc_map[] = {
+ COUNTRY_CHPLAN_ENT("CA", 0x34, 1, 0), /* Canada */
+ COUNTRY_CHPLAN_ENT("RU", 0x59, 0, 0), /* Russia(fac/gost), Kaliningrad */
+ COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */
+ COUNTRY_CHPLAN_ENT("UA", 0x36, 0, 0), /* Ukraine */
+ COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */
};
-static const u16 RTL8812AEBT_HMC_country_chplan_map_sz = sizeof(RTL8812AEBT_HMC_country_chplan_map) / sizeof(struct country_chplan);
#endif
-#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8188EE_HMC_M2)
-static const struct country_chplan RTL8188EE_HMC_M2_country_chplan_map[] = {
+#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8188EE_HMC_M2) /* 2012 certify */
+static const struct country_chplan RTL8188EE_HMC_M2_country_chplan_exc_map[] = {
+ COUNTRY_CHPLAN_ENT("CA", 0x20, 1, 0), /* Canada */
+ COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0), /* Mexico */
+ COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */
+ COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */
};
-static const u16 RTL8188EE_HMC_M2_country_chplan_map_sz = sizeof(RTL8188EE_HMC_M2_country_chplan_map) / sizeof(struct country_chplan);
#endif
-#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8723BE_HMC_M2)
-static const struct country_chplan RTL8723BE_HMC_M2_country_chplan_map[] = {
+#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8723BE_HMC_M2) /* 2013 certify */
+static const struct country_chplan RTL8723BE_HMC_M2_country_chplan_exc_map[] = {
+ COUNTRY_CHPLAN_ENT("CA", 0x20, 1, 0), /* Canada */
+ COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0), /* Mexico */
+ COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */
+ COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */
};
-static const u16 RTL8723BE_HMC_M2_country_chplan_map_sz = sizeof(RTL8723BE_HMC_M2_country_chplan_map) / sizeof(struct country_chplan);
#endif
-#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8723BS_NGFF1216)
-static const struct country_chplan RTL8723BS_NGFF1216_country_chplan_map[] = {
+#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8723BS_NGFF1216) /* 2014 certify */
+static const struct country_chplan RTL8723BS_NGFF1216_country_chplan_exc_map[] = {
+ COUNTRY_CHPLAN_ENT("CA", 0x20, 1, 0), /* Canada */
+ COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0), /* Mexico */
+ COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */
+ COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */
};
-static const u16 RTL8723BS_NGFF1216_country_chplan_map_sz = sizeof(RTL8723BS_NGFF1216_country_chplan_map) / sizeof(struct country_chplan);
#endif
-#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8192EEBT_HMC_M2)
-static const struct country_chplan RTL8192EEBT_HMC_M2_country_chplan_map[] = {
+#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8192EEBT_HMC_M2) /* 2013 certify */
+static const struct country_chplan RTL8192EEBT_HMC_M2_country_chplan_exc_map[] = {
+ COUNTRY_CHPLAN_ENT("CA", 0x20, 1, 0), /* Canada */
+ COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0), /* Mexico */
+ COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0), /* Taiwan */
+ COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0), /* United States of America (USA) */
+};
+#endif
+
+#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8723DE_NGFF1630) /* 2016 certify */
+static const struct country_chplan RTL8723DE_NGFF1630_country_chplan_exc_map[] = {
+ COUNTRY_CHPLAN_ENT("CA", 0x2A, 1, 0), /* Canada */
+ COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0), /* Mexico */
+};
+#endif
+
+#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8822BE) /* 2016 certify */
+static const struct country_chplan RTL8822BE_country_chplan_exc_map[] = {
+};
+#endif
+
+#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8821CE) /* 2016 certify */
+static const struct country_chplan RTL8821CE_country_chplan_exc_map[] = {
};
-static const u16 RTL8192EEBT_HMC_M2_country_chplan_map_sz = sizeof(RTL8192EEBT_HMC_M2_country_chplan_map) / sizeof(struct country_chplan);
#endif
/**
@@ -457,7 +692,8 @@ static const u16 RTL8192EEBT_HMC_M2_country_chplan_map_sz = sizeof(RTL8192EEBT_H
* @return:
* Return NULL for case referring to common map
*/
-static const struct country_chplan *rtw_def_module_get_chplan_from_country(const char *country_code) {
+static const struct country_chplan *rtw_def_module_get_chplan_from_country(const char *country_code)
+{
const struct country_chplan *ent = NULL;
const struct country_chplan *hal_map = NULL;
u16 hal_map_sz = 0;
@@ -465,29 +701,38 @@ static const struct country_chplan *rtw_def_module_get_chplan_from_country(const
/* TODO: runtime selection for multi driver */
#if (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8821AE_HMC_M2)
- hal_map = RTL8821AE_HMC_M2_country_chplan_map;
- hal_map_sz = RTL8821AE_HMC_M2_country_chplan_map_sz;
+ hal_map = RTL8821AE_HMC_M2_country_chplan_exc_map;
+ hal_map_sz = sizeof(RTL8821AE_HMC_M2_country_chplan_exc_map) / sizeof(struct country_chplan);
#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8821AU)
- hal_map = RTL8821AU_country_chplan_map;
- hal_map_sz = RTL8821AU_country_chplan_map_sz;
+ hal_map = RTL8821AU_country_chplan_exc_map;
+ hal_map_sz = sizeof(RTL8821AU_country_chplan_exc_map) / sizeof(struct country_chplan);
#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8812AENF_NGFF)
- hal_map = RTL8812AENF_NGFF_country_chplan_map;
- hal_map_sz = RTL8812AENF_NGFF_country_chplan_map_sz;
+ hal_map = RTL8812AENF_NGFF_country_chplan_exc_map;
+ hal_map_sz = sizeof(RTL8812AENF_NGFF_country_chplan_exc_map) / sizeof(struct country_chplan);
#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8812AEBT_HMC)
- hal_map = RTL8812AEBT_HMC_country_chplan_map;
- hal_map_sz = RTL8812AEBT_HMC_country_chplan_map_sz;
+ hal_map = RTL8812AEBT_HMC_country_chplan_exc_map;
+ hal_map_sz = sizeof(RTL8812AEBT_HMC_country_chplan_exc_map) / sizeof(struct country_chplan);
#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8188EE_HMC_M2)
- hal_map = RTL8188EE_HMC_M2_country_chplan_map;
- hal_map_sz = RTL8188EE_HMC_M2_country_chplan_map_sz;
+ hal_map = RTL8188EE_HMC_M2_country_chplan_exc_map;
+ hal_map_sz = sizeof(RTL8188EE_HMC_M2_country_chplan_exc_map) / sizeof(struct country_chplan);
#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8723BE_HMC_M2)
- hal_map = RTL8723BE_HMC_M2_country_chplan_map;
- hal_map_sz = RTL8723BE_HMC_M2_country_chplan_map_sz;
+ hal_map = RTL8723BE_HMC_M2_country_chplan_exc_map;
+ hal_map_sz = sizeof(RTL8723BE_HMC_M2_country_chplan_exc_map) / sizeof(struct country_chplan);
#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8723BS_NGFF1216)
- hal_map = RTL8723BS_NGFF1216_country_chplan_map;
- hal_map_sz = RTL8723BS_NGFF1216_country_chplan_map_sz;
+ hal_map = RTL8723BS_NGFF1216_country_chplan_exc_map;
+ hal_map_sz = sizeof(RTL8723BS_NGFF1216_country_chplan_exc_map) / sizeof(struct country_chplan);
#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8192EEBT_HMC_M2)
- hal_map = RTL8192EEBT_HMC_M2_country_chplan_map;
- hal_map_sz = RTL8192EEBT_HMC_M2_country_chplan_map_sz;
+ hal_map = RTL8192EEBT_HMC_M2_country_chplan_exc_map;
+ hal_map_sz = sizeof(RTL8192EEBT_HMC_M2_country_chplan_exc_map) / sizeof(struct country_chplan);
+#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8723DE_NGFF1630)
+ hal_map = RTL8723DE_NGFF1630_country_chplan_exc_map;
+ hal_map_sz = sizeof(RTL8723DE_NGFF1630_country_chplan_exc_map) / sizeof(struct country_chplan);
+#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8822BE)
+ hal_map = RTL8822BE_country_chplan_exc_map;
+ hal_map_sz = sizeof(RTL8822BE_country_chplan_exc_map) / sizeof(struct country_chplan);
+#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8821CE)
+ hal_map = RTL8821CE_country_chplan_exc_map;
+ hal_map_sz = sizeof(RTL8821CE_country_chplan_exc_map) / sizeof(struct country_chplan);
#endif
if (hal_map == NULL || hal_map_sz == 0)
@@ -506,238 +751,237 @@ static const struct country_chplan *rtw_def_module_get_chplan_from_country(const
#endif /* CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP or RTW_DEF_MODULE_REGULATORY_CERT */
static const struct country_chplan country_chplan_map[] = {
- COUNTRY_CHPLAN_ENT("AD", 0x26, 1, 0x00), /* Andorra */
- COUNTRY_CHPLAN_ENT("AE", 0x26, 1, 0xFB), /* United Arab Emirates */
- COUNTRY_CHPLAN_ENT("AF", 0x42, 1, 0x00), /* Afghanistan */
- COUNTRY_CHPLAN_ENT("AG", 0x30, 1, 0x00), /* Antigua & Barbuda */
- COUNTRY_CHPLAN_ENT("AI", 0x26, 1, 0x00), /* Anguilla(UK) */
- COUNTRY_CHPLAN_ENT("AL", 0x26, 1, 0xF1), /* Albania */
- COUNTRY_CHPLAN_ENT("AM", 0x26, 1, 0xB0), /* Armenia */
- COUNTRY_CHPLAN_ENT("AO", 0x26, 1, 0xE0), /* Angola */
- COUNTRY_CHPLAN_ENT("AQ", 0x26, 1, 0x00), /* Antarctica */
- COUNTRY_CHPLAN_ENT("AR", 0x57, 1, 0xF3), /* Argentina */
- COUNTRY_CHPLAN_ENT("AS", 0x34, 1, 0x00), /* American Samoa */
- COUNTRY_CHPLAN_ENT("AT", 0x26, 1, 0xFB), /* Austria */
- COUNTRY_CHPLAN_ENT("AU", 0x45, 1, 0xFB), /* Australia */
- COUNTRY_CHPLAN_ENT("AW", 0x34, 1, 0xB0), /* Aruba */
- COUNTRY_CHPLAN_ENT("AZ", 0x26, 1, 0xF1), /* Azerbaijan */
- COUNTRY_CHPLAN_ENT("BA", 0x26, 1, 0xF1), /* Bosnia & Herzegovina */
- COUNTRY_CHPLAN_ENT("BB", 0x34, 1, 0x50), /* Barbados */
- COUNTRY_CHPLAN_ENT("BD", 0x26, 1, 0xF1), /* Bangladesh */
- COUNTRY_CHPLAN_ENT("BE", 0x26, 1, 0xFB), /* Belgium */
- COUNTRY_CHPLAN_ENT("BF", 0x26, 1, 0xB0), /* Burkina Faso */
- COUNTRY_CHPLAN_ENT("BG", 0x26, 1, 0xF1), /* Bulgaria */
- COUNTRY_CHPLAN_ENT("BH", 0x47, 1, 0xF1), /* Bahrain */
- COUNTRY_CHPLAN_ENT("BI", 0x26, 1, 0xB0), /* Burundi */
- COUNTRY_CHPLAN_ENT("BJ", 0x26, 1, 0xB0), /* Benin */
- COUNTRY_CHPLAN_ENT("BN", 0x47, 1, 0x10), /* Brunei */
- COUNTRY_CHPLAN_ENT("BO", 0x30, 1, 0xF1), /* Bolivia */
- COUNTRY_CHPLAN_ENT("BR", 0x34, 1, 0xF1), /* Brazil */
- COUNTRY_CHPLAN_ENT("BS", 0x34, 1, 0x20), /* Bahamas */
- COUNTRY_CHPLAN_ENT("BW", 0x26, 1, 0xF1), /* Botswana */
- COUNTRY_CHPLAN_ENT("BY", 0x26, 1, 0xF1), /* Belarus */
- COUNTRY_CHPLAN_ENT("BZ", 0x34, 1, 0x00), /* Belize */
- COUNTRY_CHPLAN_ENT("CA", 0x34, 1, 0xFB), /* Canada */
- COUNTRY_CHPLAN_ENT("CC", 0x26, 1, 0x00), /* Cocos (Keeling) Islands (Australia) */
- COUNTRY_CHPLAN_ENT("CD", 0x26, 1, 0xB0), /* Congo, Republic of the */
- COUNTRY_CHPLAN_ENT("CF", 0x26, 1, 0xB0), /* Central African Republic */
- COUNTRY_CHPLAN_ENT("CG", 0x26, 1, 0xB0), /* Congo, Democratic Republic of the. Zaire */
- COUNTRY_CHPLAN_ENT("CH", 0x26, 1, 0xFB), /* Switzerland */
- COUNTRY_CHPLAN_ENT("CI", 0x26, 1, 0xF1), /* Cote d'Ivoire */
- COUNTRY_CHPLAN_ENT("CK", 0x26, 1, 0x00), /* Cook Islands */
- COUNTRY_CHPLAN_ENT("CL", 0x30, 1, 0xF1), /* Chile */
- COUNTRY_CHPLAN_ENT("CM", 0x26, 1, 0xB0), /* Cameroon */
- COUNTRY_CHPLAN_ENT("CN", 0x48, 1, 0xFB), /* China */
- COUNTRY_CHPLAN_ENT("CO", 0x34, 1, 0xF1), /* Colombia */
- COUNTRY_CHPLAN_ENT("CR", 0x34, 1, 0xF1), /* Costa Rica */
- COUNTRY_CHPLAN_ENT("CV", 0x26, 1, 0xB0), /* Cape Verde */
- COUNTRY_CHPLAN_ENT("CX", 0x45, 1, 0x00), /* Christmas Island (Australia) */
- COUNTRY_CHPLAN_ENT("CY", 0x26, 1, 0xFB), /* Cyprus */
- COUNTRY_CHPLAN_ENT("CZ", 0x26, 1, 0xFB), /* Czech Republic */
- COUNTRY_CHPLAN_ENT("DE", 0x26, 1, 0xFB), /* Germany */
- COUNTRY_CHPLAN_ENT("DJ", 0x26, 1, 0x80), /* Djibouti */
- COUNTRY_CHPLAN_ENT("DK", 0x26, 1, 0xFB), /* Denmark */
- COUNTRY_CHPLAN_ENT("DM", 0x34, 1, 0x00), /* Dominica */
- COUNTRY_CHPLAN_ENT("DO", 0x34, 1, 0xF1), /* Dominican Republic */
- COUNTRY_CHPLAN_ENT("DZ", 0x26, 1, 0xF1), /* Algeria */
- COUNTRY_CHPLAN_ENT("EC", 0x34, 1, 0xF1), /* Ecuador */
- COUNTRY_CHPLAN_ENT("EE", 0x26, 1, 0xFB), /* Estonia */
- COUNTRY_CHPLAN_ENT("EG", 0x47, 0, 0xF1), /* Egypt */
- COUNTRY_CHPLAN_ENT("EH", 0x47, 1, 0x80), /* Western Sahara */
- COUNTRY_CHPLAN_ENT("ER", 0x26, 1, 0x00), /* Eritrea */
- COUNTRY_CHPLAN_ENT("ES", 0x26, 1, 0xFB), /* Spain, Canary Islands, Ceuta, Melilla */
- COUNTRY_CHPLAN_ENT("ET", 0x26, 1, 0xB0), /* Ethiopia */
- COUNTRY_CHPLAN_ENT("FI", 0x26, 1, 0xFB), /* Finland */
- COUNTRY_CHPLAN_ENT("FJ", 0x34, 1, 0x00), /* Fiji */
- COUNTRY_CHPLAN_ENT("FK", 0x26, 1, 0x00), /* Falkland Islands (Islas Malvinas) (UK) */
- COUNTRY_CHPLAN_ENT("FM", 0x34, 1, 0x00), /* Micronesia, Federated States of (USA) */
- COUNTRY_CHPLAN_ENT("FO", 0x26, 1, 0x00), /* Faroe Islands (Denmark) */
- COUNTRY_CHPLAN_ENT("FR", 0x26, 1, 0xFB), /* France */
- COUNTRY_CHPLAN_ENT("GA", 0x26, 1, 0xB0), /* Gabon */
- COUNTRY_CHPLAN_ENT("GB", 0x26, 1, 0xFB), /* Great Britain (United Kingdom; England) */
- COUNTRY_CHPLAN_ENT("GD", 0x34, 1, 0xB0), /* Grenada */
- COUNTRY_CHPLAN_ENT("GE", 0x26, 1, 0x00), /* Georgia */
- COUNTRY_CHPLAN_ENT("GF", 0x26, 1, 0x80), /* French Guiana */
- COUNTRY_CHPLAN_ENT("GG", 0x26, 1, 0x00), /* Guernsey (UK) */
- COUNTRY_CHPLAN_ENT("GH", 0x26, 1, 0xF1), /* Ghana */
- COUNTRY_CHPLAN_ENT("GI", 0x26, 1, 0x00), /* Gibraltar (UK) */
- COUNTRY_CHPLAN_ENT("GL", 0x26, 1, 0x00), /* Greenland (Denmark) */
- COUNTRY_CHPLAN_ENT("GM", 0x26, 1, 0xB0), /* Gambia */
- COUNTRY_CHPLAN_ENT("GN", 0x26, 1, 0x10), /* Guinea */
- COUNTRY_CHPLAN_ENT("GP", 0x26, 1, 0x00), /* Guadeloupe (France) */
- COUNTRY_CHPLAN_ENT("GQ", 0x26, 1, 0xB0), /* Equatorial Guinea */
- COUNTRY_CHPLAN_ENT("GR", 0x26, 1, 0xFB), /* Greece */
- COUNTRY_CHPLAN_ENT("GS", 0x26, 1, 0x00), /* South Georgia and the Sandwich Islands (UK) */
- COUNTRY_CHPLAN_ENT("GT", 0x34, 1, 0xF1), /* Guatemala */
- COUNTRY_CHPLAN_ENT("GU", 0x34, 1, 0x00), /* Guam (USA) */
- COUNTRY_CHPLAN_ENT("GW", 0x26, 1, 0xB0), /* Guinea-Bissau */
- COUNTRY_CHPLAN_ENT("GY", 0x44, 1, 0x00), /* Guyana */
- COUNTRY_CHPLAN_ENT("HK", 0x26, 1, 0xFB), /* Hong Kong */
- COUNTRY_CHPLAN_ENT("HM", 0x45, 1, 0x00), /* Heard and McDonald Islands (Australia) */
- COUNTRY_CHPLAN_ENT("HN", 0x32, 1, 0xF1), /* Honduras */
- COUNTRY_CHPLAN_ENT("HR", 0x26, 1, 0xF9), /* Croatia */
- COUNTRY_CHPLAN_ENT("HT", 0x34, 1, 0x50), /* Haiti */
- COUNTRY_CHPLAN_ENT("HU", 0x26, 1, 0xFB), /* Hungary */
- COUNTRY_CHPLAN_ENT("ID", 0x54, 0, 0xF3), /* Indonesia */
- COUNTRY_CHPLAN_ENT("IE", 0x26, 1, 0xFB), /* Ireland */
- COUNTRY_CHPLAN_ENT("IL", 0x47, 1, 0xF1), /* Israel */
- COUNTRY_CHPLAN_ENT("IM", 0x26, 1, 0x00), /* Isle of Man (UK) */
- COUNTRY_CHPLAN_ENT("IN", 0x47, 1, 0xF1), /* India */
- COUNTRY_CHPLAN_ENT("IQ", 0x26, 1, 0x00), /* Iraq */
- COUNTRY_CHPLAN_ENT("IR", 0x26, 0, 0x00), /* Iran */
- COUNTRY_CHPLAN_ENT("IS", 0x26, 1, 0xFB), /* Iceland */
- COUNTRY_CHPLAN_ENT("IT", 0x26, 1, 0xFB), /* Italy */
- COUNTRY_CHPLAN_ENT("JE", 0x26, 1, 0x00), /* Jersey (UK) */
- COUNTRY_CHPLAN_ENT("JM", 0x51, 1, 0xF1), /* Jamaica */
- COUNTRY_CHPLAN_ENT("JO", 0x49, 1, 0xFB), /* Jordan */
- COUNTRY_CHPLAN_ENT("JP", 0x27, 1, 0xFF), /* Japan- Telec */
- COUNTRY_CHPLAN_ENT("KE", 0x47, 1, 0xF9), /* Kenya */
- COUNTRY_CHPLAN_ENT("KG", 0x26, 1, 0xF1), /* Kyrgyzstan */
- COUNTRY_CHPLAN_ENT("KH", 0x26, 1, 0xF1), /* Cambodia */
- COUNTRY_CHPLAN_ENT("KI", 0x26, 1, 0x00), /* Kiribati */
- COUNTRY_CHPLAN_ENT("KN", 0x34, 1, 0x00), /* Saint Kitts and Nevis */
- COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0xFB), /* South Korea */
- COUNTRY_CHPLAN_ENT("KW", 0x47, 1, 0xFB), /* Kuwait */
- COUNTRY_CHPLAN_ENT("KY", 0x34, 1, 0x00), /* Cayman Islands (UK) */
- COUNTRY_CHPLAN_ENT("KZ", 0x26, 1, 0x00), /* Kazakhstan */
- COUNTRY_CHPLAN_ENT("LA", 0x26, 1, 0x00), /* Laos */
- COUNTRY_CHPLAN_ENT("LB", 0x26, 1, 0xF1), /* Lebanon */
- COUNTRY_CHPLAN_ENT("LC", 0x34, 1, 0x00), /* Saint Lucia */
- COUNTRY_CHPLAN_ENT("LI", 0x26, 1, 0xFB), /* Liechtenstein */
- COUNTRY_CHPLAN_ENT("LK", 0x26, 1, 0xF1), /* Sri Lanka */
- COUNTRY_CHPLAN_ENT("LR", 0x26, 1, 0xB0), /* Liberia */
- COUNTRY_CHPLAN_ENT("LS", 0x26, 1, 0xF1), /* Lesotho */
- COUNTRY_CHPLAN_ENT("LT", 0x26, 1, 0xFB), /* Lithuania */
- COUNTRY_CHPLAN_ENT("LU", 0x26, 1, 0xFB), /* Luxembourg */
- COUNTRY_CHPLAN_ENT("LV", 0x26, 1, 0xFB), /* Latvia */
- COUNTRY_CHPLAN_ENT("LY", 0x26, 1, 0x00), /* Libya */
- COUNTRY_CHPLAN_ENT("MA", 0x47, 1, 0xF1), /* Morocco */
- COUNTRY_CHPLAN_ENT("MC", 0x26, 1, 0xFB), /* Monaco */
- COUNTRY_CHPLAN_ENT("MD", 0x26, 1, 0xF1), /* Moldova */
- COUNTRY_CHPLAN_ENT("ME", 0x26, 1, 0xF1), /* Montenegro */
- COUNTRY_CHPLAN_ENT("MF", 0x34, 1, 0x00), /* Saint Martin */
- COUNTRY_CHPLAN_ENT("MG", 0x26, 1, 0x20), /* Madagascar */
- COUNTRY_CHPLAN_ENT("MH", 0x34, 1, 0x00), /* Marshall Islands (USA) */
- COUNTRY_CHPLAN_ENT("MK", 0x26, 1, 0xF1), /* Republic of Macedonia (FYROM) */
- COUNTRY_CHPLAN_ENT("ML", 0x26, 1, 0xB0), /* Mali */
- COUNTRY_CHPLAN_ENT("MM", 0x26, 1, 0x00), /* Burma (Myanmar) */
- COUNTRY_CHPLAN_ENT("MN", 0x26, 1, 0x00), /* Mongolia */
- COUNTRY_CHPLAN_ENT("MO", 0x26, 1, 0x00), /* Macau */
- COUNTRY_CHPLAN_ENT("MP", 0x34, 1, 0x00), /* Northern Mariana Islands (USA) */
- COUNTRY_CHPLAN_ENT("MQ", 0x26, 1, 0x40), /* Martinique (France) */
- COUNTRY_CHPLAN_ENT("MR", 0x26, 1, 0xA0), /* Mauritania */
- COUNTRY_CHPLAN_ENT("MS", 0x26, 1, 0x00), /* Montserrat (UK) */
- COUNTRY_CHPLAN_ENT("MT", 0x26, 1, 0xFB), /* Malta */
- COUNTRY_CHPLAN_ENT("MU", 0x26, 1, 0xB0), /* Mauritius */
- COUNTRY_CHPLAN_ENT("MV", 0x26, 1, 0x00), /* Maldives */
- COUNTRY_CHPLAN_ENT("MW", 0x26, 1, 0xB0), /* Malawi */
- COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0xF1), /* Mexico */
- COUNTRY_CHPLAN_ENT("MY", 0x47, 1, 0xF1), /* Malaysia */
- COUNTRY_CHPLAN_ENT("MZ", 0x26, 1, 0xF1), /* Mozambique */
- COUNTRY_CHPLAN_ENT("NA", 0x26, 0, 0x00), /* Namibia */
- COUNTRY_CHPLAN_ENT("NC", 0x26, 1, 0x00), /* New Caledonia */
- COUNTRY_CHPLAN_ENT("NE", 0x26, 1, 0xB0), /* Niger */
- COUNTRY_CHPLAN_ENT("NF", 0x45, 1, 0x00), /* Norfolk Island (Australia) */
- COUNTRY_CHPLAN_ENT("NG", 0x50, 1, 0xF9), /* Nigeria */
- COUNTRY_CHPLAN_ENT("NI", 0x34, 1, 0xF1), /* Nicaragua */
- COUNTRY_CHPLAN_ENT("NL", 0x26, 1, 0xFB), /* Netherlands */
- COUNTRY_CHPLAN_ENT("NO", 0x26, 1, 0xFB), /* Norway */
- COUNTRY_CHPLAN_ENT("NP", 0x47, 1, 0xF0), /* Nepal */
- COUNTRY_CHPLAN_ENT("NR", 0x26, 1, 0x00), /* Nauru */
- COUNTRY_CHPLAN_ENT("NU", 0x45, 1, 0x00), /* Niue */
- COUNTRY_CHPLAN_ENT("NZ", 0x45, 1, 0xFB), /* New Zealand */
- COUNTRY_CHPLAN_ENT("OM", 0x26, 1, 0xF9), /* Oman */
- COUNTRY_CHPLAN_ENT("PA", 0x34, 1, 0xF1), /* Panama */
- COUNTRY_CHPLAN_ENT("PE", 0x34, 1, 0xF1), /* Peru */
- COUNTRY_CHPLAN_ENT("PF", 0x26, 1, 0x00), /* French Polynesia (France) */
- COUNTRY_CHPLAN_ENT("PG", 0x26, 1, 0xF1), /* Papua New Guinea */
- COUNTRY_CHPLAN_ENT("PH", 0x26, 1, 0xF1), /* Philippines */
- COUNTRY_CHPLAN_ENT("PK", 0x51, 1, 0xF1), /* Pakistan */
- COUNTRY_CHPLAN_ENT("PL", 0x26, 1, 0xFB), /* Poland */
- COUNTRY_CHPLAN_ENT("PM", 0x26, 1, 0x00), /* Saint Pierre and Miquelon (France) */
- COUNTRY_CHPLAN_ENT("PR", 0x34, 1, 0xF1), /* Puerto Rico */
- COUNTRY_CHPLAN_ENT("PT", 0x26, 1, 0xFB), /* Portugal */
- COUNTRY_CHPLAN_ENT("PW", 0x34, 1, 0x00), /* Palau */
- COUNTRY_CHPLAN_ENT("PY", 0x34, 1, 0xF1), /* Paraguay */
- COUNTRY_CHPLAN_ENT("QA", 0x51, 1, 0xF9), /* Qatar */
- COUNTRY_CHPLAN_ENT("RE", 0x26, 1, 0x00), /* Reunion (France) */
- COUNTRY_CHPLAN_ENT("RO", 0x26, 1, 0xF1), /* Romania */
- COUNTRY_CHPLAN_ENT("RS", 0x26, 1, 0xF1), /* Serbia, Kosovo */
- COUNTRY_CHPLAN_ENT("RU", 0x59, 1, 0xFB), /* Russia(fac/gost), Kaliningrad */
- COUNTRY_CHPLAN_ENT("RW", 0x26, 1, 0xB0), /* Rwanda */
- COUNTRY_CHPLAN_ENT("SA", 0x26, 1, 0xFB), /* Saudi Arabia */
- COUNTRY_CHPLAN_ENT("SB", 0x26, 1, 0x00), /* Solomon Islands */
- COUNTRY_CHPLAN_ENT("SC", 0x34, 1, 0x90), /* Seychelles */
- COUNTRY_CHPLAN_ENT("SE", 0x26, 1, 0xFB), /* Sweden */
- COUNTRY_CHPLAN_ENT("SG", 0x47, 1, 0xFB), /* Singapore */
- COUNTRY_CHPLAN_ENT("SH", 0x26, 1, 0x00), /* Saint Helena (UK) */
- COUNTRY_CHPLAN_ENT("SI", 0x26, 1, 0xFB), /* Slovenia */
- COUNTRY_CHPLAN_ENT("SJ", 0x26, 1, 0x00), /* Svalbard (Norway) */
- COUNTRY_CHPLAN_ENT("SK", 0x26, 1, 0xFB), /* Slovakia */
- COUNTRY_CHPLAN_ENT("SL", 0x26, 1, 0xB0), /* Sierra Leone */
- COUNTRY_CHPLAN_ENT("SM", 0x26, 1, 0x00), /* San Marino */
- COUNTRY_CHPLAN_ENT("SN", 0x26, 1, 0xF1), /* Senegal */
- COUNTRY_CHPLAN_ENT("SO", 0x26, 1, 0x00), /* Somalia */
- COUNTRY_CHPLAN_ENT("SR", 0x34, 1, 0x00), /* Suriname */
- COUNTRY_CHPLAN_ENT("ST", 0x34, 1, 0x80), /* Sao Tome and Principe */
- COUNTRY_CHPLAN_ENT("SV", 0x30, 1, 0xF1), /* El Salvador */
- COUNTRY_CHPLAN_ENT("SX", 0x34, 1, 0x00), /* Sint Marteen */
- COUNTRY_CHPLAN_ENT("SZ", 0x26, 1, 0x20), /* Swaziland */
- COUNTRY_CHPLAN_ENT("TC", 0x26, 1, 0x00), /* Turks and Caicos Islands (UK) */
- COUNTRY_CHPLAN_ENT("TD", 0x26, 1, 0xB0), /* Chad */
- COUNTRY_CHPLAN_ENT("TF", 0x26, 1, 0x80), /* French Southern and Antarctic Lands (FR Southern Territories) */
- COUNTRY_CHPLAN_ENT("TG", 0x26, 1, 0xB0), /* Togo */
- COUNTRY_CHPLAN_ENT("TH", 0x26, 1, 0xF1), /* Thailand */
- COUNTRY_CHPLAN_ENT("TJ", 0x26, 1, 0x40), /* Tajikistan */
- COUNTRY_CHPLAN_ENT("TK", 0x45, 1, 0x00), /* Tokelau */
- COUNTRY_CHPLAN_ENT("TM", 0x26, 1, 0x00), /* Turkmenistan */
- COUNTRY_CHPLAN_ENT("TN", 0x47, 1, 0xF1), /* Tunisia */
- COUNTRY_CHPLAN_ENT("TO", 0x26, 1, 0x00), /* Tonga */
- COUNTRY_CHPLAN_ENT("TR", 0x26, 1, 0xF1), /* Turkey, Northern Cyprus */
- COUNTRY_CHPLAN_ENT("TT", 0x42, 1, 0xF1), /* Trinidad & Tobago */
- COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0xFF), /* Taiwan */
- COUNTRY_CHPLAN_ENT("TZ", 0x26, 1, 0xF0), /* Tanzania */
- COUNTRY_CHPLAN_ENT("UA", 0x26, 1, 0xFB), /* Ukraine */
- COUNTRY_CHPLAN_ENT("UG", 0x26, 1, 0xF1), /* Uganda */
- COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0xFF), /* United States of America (USA) */
- COUNTRY_CHPLAN_ENT("UY", 0x34, 1, 0xF1), /* Uruguay */
- COUNTRY_CHPLAN_ENT("UZ", 0x47, 1, 0xF0), /* Uzbekistan */
- COUNTRY_CHPLAN_ENT("VA", 0x26, 1, 0x00), /* Holy See (Vatican City) */
- COUNTRY_CHPLAN_ENT("VC", 0x34, 1, 0x10), /* Saint Vincent and the Grenadines */
- COUNTRY_CHPLAN_ENT("VE", 0x30, 1, 0xF1), /* Venezuela */
- COUNTRY_CHPLAN_ENT("VI", 0x34, 1, 0x00), /* United States Virgin Islands (USA) */
- COUNTRY_CHPLAN_ENT("VN", 0x26, 1, 0xF1), /* Vietnam */
- COUNTRY_CHPLAN_ENT("VU", 0x26, 1, 0x00), /* Vanuatu */
- COUNTRY_CHPLAN_ENT("WF", 0x26, 1, 0x00), /* Wallis and Futuna (France) */
- COUNTRY_CHPLAN_ENT("WS", 0x34, 1, 0x00), /* Samoa */
- COUNTRY_CHPLAN_ENT("YE", 0x26, 1, 0x40), /* Yemen */
- COUNTRY_CHPLAN_ENT("YT", 0x26, 1, 0x80), /* Mayotte (France) */
- COUNTRY_CHPLAN_ENT("ZA", 0x26, 1, 0xF1), /* South Africa */
- COUNTRY_CHPLAN_ENT("ZM", 0x26, 1, 0xB0), /* Zambia */
- COUNTRY_CHPLAN_ENT("ZW", 0x26, 1, 0xF1), /* Zimbabwe */
-};
-
-u16 const country_chplan_map_sz = sizeof(country_chplan_map) / sizeof(struct country_chplan);
+ COUNTRY_CHPLAN_ENT("AD", 0x26, 1, 0x000), /* Andorra */
+ COUNTRY_CHPLAN_ENT("AE", 0x26, 1, 0x7FB), /* United Arab Emirates */
+ COUNTRY_CHPLAN_ENT("AF", 0x42, 1, 0x000), /* Afghanistan */
+ COUNTRY_CHPLAN_ENT("AG", 0x26, 1, 0x000), /* Antigua & Barbuda */
+ COUNTRY_CHPLAN_ENT("AI", 0x26, 1, 0x000), /* Anguilla(UK) */
+ COUNTRY_CHPLAN_ENT("AL", 0x26, 1, 0x7F1), /* Albania */
+ COUNTRY_CHPLAN_ENT("AM", 0x26, 1, 0x6B0), /* Armenia */
+ COUNTRY_CHPLAN_ENT("AN", 0x26, 1, 0x7F1), /* Netherlands Antilles */
+ COUNTRY_CHPLAN_ENT("AO", 0x47, 1, 0x6E0), /* Angola */
+ COUNTRY_CHPLAN_ENT("AQ", 0x26, 1, 0x000), /* Antarctica */
+ COUNTRY_CHPLAN_ENT("AR", 0x61, 1, 0x7F3), /* Argentina */
+ COUNTRY_CHPLAN_ENT("AS", 0x34, 1, 0x000), /* American Samoa */
+ COUNTRY_CHPLAN_ENT("AT", 0x26, 1, 0x7FB), /* Austria */
+ COUNTRY_CHPLAN_ENT("AU", 0x45, 1, 0x7FB), /* Australia */
+ COUNTRY_CHPLAN_ENT("AW", 0x34, 1, 0x0B0), /* Aruba */
+ COUNTRY_CHPLAN_ENT("AZ", 0x26, 1, 0x7F1), /* Azerbaijan */
+ COUNTRY_CHPLAN_ENT("BA", 0x26, 1, 0x7F1), /* Bosnia & Herzegovina */
+ COUNTRY_CHPLAN_ENT("BB", 0x34, 1, 0x650), /* Barbados */
+ COUNTRY_CHPLAN_ENT("BD", 0x26, 1, 0x7F1), /* Bangladesh */
+ COUNTRY_CHPLAN_ENT("BE", 0x26, 1, 0x7FB), /* Belgium */
+ COUNTRY_CHPLAN_ENT("BF", 0x26, 1, 0x6B0), /* Burkina Faso */
+ COUNTRY_CHPLAN_ENT("BG", 0x26, 1, 0x7F1), /* Bulgaria */
+ COUNTRY_CHPLAN_ENT("BH", 0x47, 1, 0x7F1), /* Bahrain */
+ COUNTRY_CHPLAN_ENT("BI", 0x26, 1, 0x6B0), /* Burundi */
+ COUNTRY_CHPLAN_ENT("BJ", 0x26, 1, 0x6B0), /* Benin */
+ COUNTRY_CHPLAN_ENT("BN", 0x47, 1, 0x610), /* Brunei */
+ COUNTRY_CHPLAN_ENT("BO", 0x73, 1, 0x7F1), /* Bolivia */
+ COUNTRY_CHPLAN_ENT("BR", 0x62, 1, 0x7F1), /* Brazil */
+ COUNTRY_CHPLAN_ENT("BS", 0x34, 1, 0x620), /* Bahamas */
+ COUNTRY_CHPLAN_ENT("BW", 0x26, 1, 0x6F1), /* Botswana */
+ COUNTRY_CHPLAN_ENT("BY", 0x26, 1, 0x7F1), /* Belarus */
+ COUNTRY_CHPLAN_ENT("BZ", 0x34, 1, 0x000), /* Belize */
+ COUNTRY_CHPLAN_ENT("CA", 0x2B, 1, 0x7FB), /* Canada */
+ COUNTRY_CHPLAN_ENT("CC", 0x26, 1, 0x000), /* Cocos (Keeling) Islands (Australia) */
+ COUNTRY_CHPLAN_ENT("CD", 0x26, 1, 0x6B0), /* Congo, Republic of the */
+ COUNTRY_CHPLAN_ENT("CF", 0x26, 1, 0x6B0), /* Central African Republic */
+ COUNTRY_CHPLAN_ENT("CG", 0x26, 1, 0x6B0), /* Congo, Democratic Republic of the. Zaire */
+ COUNTRY_CHPLAN_ENT("CH", 0x26, 1, 0x7FB), /* Switzerland */
+ COUNTRY_CHPLAN_ENT("CI", 0x26, 1, 0x7F1), /* Cote d'Ivoire */
+ COUNTRY_CHPLAN_ENT("CK", 0x26, 1, 0x000), /* Cook Islands */
+ COUNTRY_CHPLAN_ENT("CL", 0x2D, 1, 0x7F1), /* Chile */
+ COUNTRY_CHPLAN_ENT("CM", 0x26, 1, 0x6B0), /* Cameroon */
+ COUNTRY_CHPLAN_ENT("CN", 0x48, 1, 0x7FB), /* China */
+ COUNTRY_CHPLAN_ENT("CO", 0x34, 1, 0x7F1), /* Colombia */
+ COUNTRY_CHPLAN_ENT("CR", 0x34, 1, 0x7F1), /* Costa Rica */
+ COUNTRY_CHPLAN_ENT("CV", 0x26, 1, 0x6B0), /* Cape Verde */
+ COUNTRY_CHPLAN_ENT("CX", 0x45, 1, 0x000), /* Christmas Island (Australia) */
+ COUNTRY_CHPLAN_ENT("CY", 0x26, 1, 0x7FB), /* Cyprus */
+ COUNTRY_CHPLAN_ENT("CZ", 0x26, 1, 0x7FB), /* Czech Republic */
+ COUNTRY_CHPLAN_ENT("DE", 0x26, 1, 0x7FB), /* Germany */
+ COUNTRY_CHPLAN_ENT("DJ", 0x26, 1, 0x680), /* Djibouti */
+ COUNTRY_CHPLAN_ENT("DK", 0x26, 1, 0x7FB), /* Denmark */
+ COUNTRY_CHPLAN_ENT("DM", 0x34, 1, 0x000), /* Dominica */
+ COUNTRY_CHPLAN_ENT("DO", 0x34, 1, 0x7F1), /* Dominican Republic */
+ COUNTRY_CHPLAN_ENT("DZ", 0x26, 1, 0x7F1), /* Algeria */
+ COUNTRY_CHPLAN_ENT("EC", 0x34, 1, 0x7F1), /* Ecuador */
+ COUNTRY_CHPLAN_ENT("EE", 0x26, 1, 0x7FB), /* Estonia */
+ COUNTRY_CHPLAN_ENT("EG", 0x47, 1, 0x7F1), /* Egypt */
+ COUNTRY_CHPLAN_ENT("EH", 0x47, 1, 0x680), /* Western Sahara */
+ COUNTRY_CHPLAN_ENT("ER", 0x26, 1, 0x000), /* Eritrea */
+ COUNTRY_CHPLAN_ENT("ES", 0x26, 1, 0x7FB), /* Spain, Canary Islands, Ceuta, Melilla */
+ COUNTRY_CHPLAN_ENT("ET", 0x26, 1, 0x4B0), /* Ethiopia */
+ COUNTRY_CHPLAN_ENT("FI", 0x26, 1, 0x7FB), /* Finland */
+ COUNTRY_CHPLAN_ENT("FJ", 0x34, 1, 0x600), /* Fiji */
+ COUNTRY_CHPLAN_ENT("FK", 0x26, 1, 0x000), /* Falkland Islands (Islas Malvinas) (UK) */
+ COUNTRY_CHPLAN_ENT("FM", 0x34, 1, 0x000), /* Micronesia, Federated States of (USA) */
+ COUNTRY_CHPLAN_ENT("FO", 0x26, 1, 0x000), /* Faroe Islands (Denmark) */
+ COUNTRY_CHPLAN_ENT("FR", 0x26, 1, 0x7FB), /* France */
+ COUNTRY_CHPLAN_ENT("GA", 0x26, 1, 0x6B0), /* Gabon */
+ COUNTRY_CHPLAN_ENT("GB", 0x26, 1, 0x7FB), /* Great Britain (United Kingdom; England) */
+ COUNTRY_CHPLAN_ENT("GD", 0x34, 1, 0x0B0), /* Grenada */
+ COUNTRY_CHPLAN_ENT("GE", 0x26, 1, 0x600), /* Georgia */
+ COUNTRY_CHPLAN_ENT("GF", 0x26, 1, 0x080), /* French Guiana */
+ COUNTRY_CHPLAN_ENT("GG", 0x26, 1, 0x000), /* Guernsey (UK) */
+ COUNTRY_CHPLAN_ENT("GH", 0x26, 1, 0x7F1), /* Ghana */
+ COUNTRY_CHPLAN_ENT("GI", 0x26, 1, 0x600), /* Gibraltar (UK) */
+ COUNTRY_CHPLAN_ENT("GL", 0x26, 1, 0x600), /* Greenland (Denmark) */
+ COUNTRY_CHPLAN_ENT("GM", 0x26, 1, 0x6B0), /* Gambia */
+ COUNTRY_CHPLAN_ENT("GN", 0x26, 1, 0x610), /* Guinea */
+ COUNTRY_CHPLAN_ENT("GP", 0x26, 1, 0x600), /* Guadeloupe (France) */
+ COUNTRY_CHPLAN_ENT("GQ", 0x26, 1, 0x6B0), /* Equatorial Guinea */
+ COUNTRY_CHPLAN_ENT("GR", 0x26, 1, 0x7FB), /* Greece */
+ COUNTRY_CHPLAN_ENT("GS", 0x26, 1, 0x000), /* South Georgia and the Sandwich Islands (UK) */
+ COUNTRY_CHPLAN_ENT("GT", 0x34, 1, 0x7F1), /* Guatemala */
+ COUNTRY_CHPLAN_ENT("GU", 0x34, 1, 0x600), /* Guam (USA) */
+ COUNTRY_CHPLAN_ENT("GW", 0x26, 1, 0x6B0), /* Guinea-Bissau */
+ COUNTRY_CHPLAN_ENT("GY", 0x44, 1, 0x000), /* Guyana */
+ COUNTRY_CHPLAN_ENT("HK", 0x26, 1, 0x7FB), /* Hong Kong */
+ COUNTRY_CHPLAN_ENT("HM", 0x45, 1, 0x000), /* Heard and McDonald Islands (Australia) */
+ COUNTRY_CHPLAN_ENT("HN", 0x32, 1, 0x7F1), /* Honduras */
+ COUNTRY_CHPLAN_ENT("HR", 0x26, 1, 0x7F9), /* Croatia */
+ COUNTRY_CHPLAN_ENT("HT", 0x34, 1, 0x650), /* Haiti */
+ COUNTRY_CHPLAN_ENT("HU", 0x26, 1, 0x7FB), /* Hungary */
+ COUNTRY_CHPLAN_ENT("ID", 0x3D, 0, 0x7F3), /* Indonesia */
+ COUNTRY_CHPLAN_ENT("IE", 0x26, 1, 0x7FB), /* Ireland */
+ COUNTRY_CHPLAN_ENT("IL", 0x47, 1, 0x7F1), /* Israel */
+ COUNTRY_CHPLAN_ENT("IM", 0x26, 1, 0x000), /* Isle of Man (UK) */
+ COUNTRY_CHPLAN_ENT("IN", 0x48, 1, 0x7F1), /* India */
+ COUNTRY_CHPLAN_ENT("IQ", 0x26, 1, 0x000), /* Iraq */
+ COUNTRY_CHPLAN_ENT("IR", 0x26, 0, 0x000), /* Iran */
+ COUNTRY_CHPLAN_ENT("IS", 0x26, 1, 0x7FB), /* Iceland */
+ COUNTRY_CHPLAN_ENT("IT", 0x26, 1, 0x7FB), /* Italy */
+ COUNTRY_CHPLAN_ENT("JE", 0x26, 1, 0x000), /* Jersey (UK) */
+ COUNTRY_CHPLAN_ENT("JM", 0x51, 1, 0x7F1), /* Jamaica */
+ COUNTRY_CHPLAN_ENT("JO", 0x49, 1, 0x7FB), /* Jordan */
+ COUNTRY_CHPLAN_ENT("JP", 0x27, 1, 0x7FF), /* Japan- Telec */
+ COUNTRY_CHPLAN_ENT("KE", 0x47, 1, 0x7F9), /* Kenya */
+ COUNTRY_CHPLAN_ENT("KG", 0x26, 1, 0x7F1), /* Kyrgyzstan */
+ COUNTRY_CHPLAN_ENT("KH", 0x26, 1, 0x7F1), /* Cambodia */
+ COUNTRY_CHPLAN_ENT("KI", 0x26, 1, 0x000), /* Kiribati */
+ COUNTRY_CHPLAN_ENT("KN", 0x34, 1, 0x000), /* Saint Kitts and Nevis */
+ COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0x7FB), /* South Korea */
+ COUNTRY_CHPLAN_ENT("KW", 0x47, 1, 0x7FB), /* Kuwait */
+ COUNTRY_CHPLAN_ENT("KY", 0x34, 1, 0x000), /* Cayman Islands (UK) */
+ COUNTRY_CHPLAN_ENT("KZ", 0x26, 1, 0x700), /* Kazakhstan */
+ COUNTRY_CHPLAN_ENT("LA", 0x26, 1, 0x000), /* Laos */
+ COUNTRY_CHPLAN_ENT("LB", 0x26, 1, 0x7F1), /* Lebanon */
+ COUNTRY_CHPLAN_ENT("LC", 0x34, 1, 0x000), /* Saint Lucia */
+ COUNTRY_CHPLAN_ENT("LI", 0x26, 1, 0x7FB), /* Liechtenstein */
+ COUNTRY_CHPLAN_ENT("LK", 0x26, 1, 0x7F1), /* Sri Lanka */
+ COUNTRY_CHPLAN_ENT("LR", 0x26, 1, 0x6B0), /* Liberia */
+ COUNTRY_CHPLAN_ENT("LS", 0x26, 1, 0x7F1), /* Lesotho */
+ COUNTRY_CHPLAN_ENT("LT", 0x26, 1, 0x7FB), /* Lithuania */
+ COUNTRY_CHPLAN_ENT("LU", 0x26, 1, 0x7FB), /* Luxembourg */
+ COUNTRY_CHPLAN_ENT("LV", 0x26, 1, 0x7FB), /* Latvia */
+ COUNTRY_CHPLAN_ENT("LY", 0x26, 1, 0x000), /* Libya */
+ COUNTRY_CHPLAN_ENT("MA", 0x47, 1, 0x7F1), /* Morocco */
+ COUNTRY_CHPLAN_ENT("MC", 0x26, 1, 0x7FB), /* Monaco */
+ COUNTRY_CHPLAN_ENT("MD", 0x26, 1, 0x7F1), /* Moldova */
+ COUNTRY_CHPLAN_ENT("ME", 0x26, 1, 0x7F1), /* Montenegro */
+ COUNTRY_CHPLAN_ENT("MF", 0x34, 1, 0x000), /* Saint Martin */
+ COUNTRY_CHPLAN_ENT("MG", 0x26, 1, 0x620), /* Madagascar */
+ COUNTRY_CHPLAN_ENT("MH", 0x34, 1, 0x000), /* Marshall Islands (USA) */
+ COUNTRY_CHPLAN_ENT("MK", 0x26, 1, 0x7F1), /* Republic of Macedonia (FYROM) */
+ COUNTRY_CHPLAN_ENT("ML", 0x26, 1, 0x6B0), /* Mali */
+ COUNTRY_CHPLAN_ENT("MM", 0x26, 1, 0x000), /* Burma (Myanmar) */
+ COUNTRY_CHPLAN_ENT("MN", 0x26, 1, 0x000), /* Mongolia */
+ COUNTRY_CHPLAN_ENT("MO", 0x26, 1, 0x600), /* Macau */
+ COUNTRY_CHPLAN_ENT("MP", 0x34, 1, 0x000), /* Northern Mariana Islands (USA) */
+ COUNTRY_CHPLAN_ENT("MQ", 0x26, 1, 0x640), /* Martinique (France) */
+ COUNTRY_CHPLAN_ENT("MR", 0x26, 1, 0x6A0), /* Mauritania */
+ COUNTRY_CHPLAN_ENT("MS", 0x26, 1, 0x000), /* Montserrat (UK) */
+ COUNTRY_CHPLAN_ENT("MT", 0x26, 1, 0x7FB), /* Malta */
+ COUNTRY_CHPLAN_ENT("MU", 0x26, 1, 0x6B0), /* Mauritius */
+ COUNTRY_CHPLAN_ENT("MV", 0x47, 1, 0x000), /* Maldives */
+ COUNTRY_CHPLAN_ENT("MW", 0x26, 1, 0x6B0), /* Malawi */
+ COUNTRY_CHPLAN_ENT("MX", 0x61, 1, 0x7F1), /* Mexico */
+ COUNTRY_CHPLAN_ENT("MY", 0x63, 1, 0x7F1), /* Malaysia */
+ COUNTRY_CHPLAN_ENT("MZ", 0x26, 1, 0x7F1), /* Mozambique */
+ COUNTRY_CHPLAN_ENT("NA", 0x26, 1, 0x700), /* Namibia */
+ COUNTRY_CHPLAN_ENT("NC", 0x26, 1, 0x000), /* New Caledonia */
+ COUNTRY_CHPLAN_ENT("NE", 0x26, 1, 0x6B0), /* Niger */
+ COUNTRY_CHPLAN_ENT("NF", 0x45, 1, 0x000), /* Norfolk Island (Australia) */
+ COUNTRY_CHPLAN_ENT("NG", 0x75, 1, 0x7F9), /* Nigeria */
+ COUNTRY_CHPLAN_ENT("NI", 0x34, 1, 0x7F1), /* Nicaragua */
+ COUNTRY_CHPLAN_ENT("NL", 0x26, 1, 0x7FB), /* Netherlands */
+ COUNTRY_CHPLAN_ENT("NO", 0x26, 1, 0x7FB), /* Norway */
+ COUNTRY_CHPLAN_ENT("NP", 0x47, 1, 0x6F0), /* Nepal */
+ COUNTRY_CHPLAN_ENT("NR", 0x26, 1, 0x000), /* Nauru */
+ COUNTRY_CHPLAN_ENT("NU", 0x45, 1, 0x000), /* Niue */
+ COUNTRY_CHPLAN_ENT("NZ", 0x45, 1, 0x7FB), /* New Zealand */
+ COUNTRY_CHPLAN_ENT("OM", 0x26, 1, 0x7F9), /* Oman */
+ COUNTRY_CHPLAN_ENT("PA", 0x34, 1, 0x7F1), /* Panama */
+ COUNTRY_CHPLAN_ENT("PE", 0x34, 1, 0x7F1), /* Peru */
+ COUNTRY_CHPLAN_ENT("PF", 0x26, 1, 0x000), /* French Polynesia (France) */
+ COUNTRY_CHPLAN_ENT("PG", 0x26, 1, 0x7F1), /* Papua New Guinea */
+ COUNTRY_CHPLAN_ENT("PH", 0x26, 1, 0x7F1), /* Philippines */
+ COUNTRY_CHPLAN_ENT("PK", 0x51, 1, 0x7F1), /* Pakistan */
+ COUNTRY_CHPLAN_ENT("PL", 0x26, 1, 0x7FB), /* Poland */
+ COUNTRY_CHPLAN_ENT("PM", 0x26, 1, 0x000), /* Saint Pierre and Miquelon (France) */
+ COUNTRY_CHPLAN_ENT("PR", 0x34, 1, 0x7F1), /* Puerto Rico */
+ COUNTRY_CHPLAN_ENT("PT", 0x26, 1, 0x7FB), /* Portugal */
+ COUNTRY_CHPLAN_ENT("PW", 0x34, 1, 0x000), /* Palau */
+ COUNTRY_CHPLAN_ENT("PY", 0x34, 1, 0x7F1), /* Paraguay */
+ COUNTRY_CHPLAN_ENT("QA", 0x51, 1, 0x7F9), /* Qatar */
+ COUNTRY_CHPLAN_ENT("RE", 0x26, 1, 0x000), /* Reunion (France) */
+ COUNTRY_CHPLAN_ENT("RO", 0x26, 1, 0x7F1), /* Romania */
+ COUNTRY_CHPLAN_ENT("RS", 0x26, 1, 0x7F1), /* Serbia, Kosovo */
+ COUNTRY_CHPLAN_ENT("RU", 0x59, 1, 0x7FB), /* Russia(fac/gost), Kaliningrad */
+ COUNTRY_CHPLAN_ENT("RW", 0x26, 1, 0x0B0), /* Rwanda */
+ COUNTRY_CHPLAN_ENT("SA", 0x26, 1, 0x7FB), /* Saudi Arabia */
+ COUNTRY_CHPLAN_ENT("SB", 0x26, 1, 0x000), /* Solomon Islands */
+ COUNTRY_CHPLAN_ENT("SC", 0x34, 1, 0x690), /* Seychelles */
+ COUNTRY_CHPLAN_ENT("SE", 0x26, 1, 0x7FB), /* Sweden */
+ COUNTRY_CHPLAN_ENT("SG", 0x26, 1, 0x7FB), /* Singapore */
+ COUNTRY_CHPLAN_ENT("SH", 0x26, 1, 0x000), /* Saint Helena (UK) */
+ COUNTRY_CHPLAN_ENT("SI", 0x26, 1, 0x7FB), /* Slovenia */
+ COUNTRY_CHPLAN_ENT("SJ", 0x26, 1, 0x000), /* Svalbard (Norway) */
+ COUNTRY_CHPLAN_ENT("SK", 0x26, 1, 0x7FB), /* Slovakia */
+ COUNTRY_CHPLAN_ENT("SL", 0x26, 1, 0x6B0), /* Sierra Leone */
+ COUNTRY_CHPLAN_ENT("SM", 0x26, 1, 0x000), /* San Marino */
+ COUNTRY_CHPLAN_ENT("SN", 0x26, 1, 0x7F1), /* Senegal */
+ COUNTRY_CHPLAN_ENT("SO", 0x26, 1, 0x000), /* Somalia */
+ COUNTRY_CHPLAN_ENT("SR", 0x74, 1, 0x000), /* Suriname */
+ COUNTRY_CHPLAN_ENT("ST", 0x34, 1, 0x680), /* Sao Tome and Principe */
+ COUNTRY_CHPLAN_ENT("SV", 0x30, 1, 0x7F1), /* El Salvador */
+ COUNTRY_CHPLAN_ENT("SX", 0x34, 1, 0x000), /* Sint Marteen */
+ COUNTRY_CHPLAN_ENT("SZ", 0x26, 1, 0x020), /* Swaziland */
+ COUNTRY_CHPLAN_ENT("TC", 0x26, 1, 0x000), /* Turks and Caicos Islands (UK) */
+ COUNTRY_CHPLAN_ENT("TD", 0x26, 1, 0x6B0), /* Chad */
+ COUNTRY_CHPLAN_ENT("TF", 0x26, 1, 0x680), /* French Southern and Antarctic Lands (FR Southern Territories) */
+ COUNTRY_CHPLAN_ENT("TG", 0x26, 1, 0x6B0), /* Togo */
+ COUNTRY_CHPLAN_ENT("TH", 0x26, 1, 0x7F1), /* Thailand */
+ COUNTRY_CHPLAN_ENT("TJ", 0x26, 1, 0x640), /* Tajikistan */
+ COUNTRY_CHPLAN_ENT("TK", 0x45, 1, 0x000), /* Tokelau */
+ COUNTRY_CHPLAN_ENT("TM", 0x26, 1, 0x000), /* Turkmenistan */
+ COUNTRY_CHPLAN_ENT("TN", 0x47, 1, 0x7F1), /* Tunisia */
+ COUNTRY_CHPLAN_ENT("TO", 0x26, 1, 0x000), /* Tonga */
+ COUNTRY_CHPLAN_ENT("TR", 0x26, 1, 0x7F1), /* Turkey, Northern Cyprus */
+ COUNTRY_CHPLAN_ENT("TT", 0x42, 1, 0x3F1), /* Trinidad & Tobago */
+ COUNTRY_CHPLAN_ENT("TW", 0x76, 1, 0x7FF), /* Taiwan */
+ COUNTRY_CHPLAN_ENT("TZ", 0x26, 1, 0x6F0), /* Tanzania */
+ COUNTRY_CHPLAN_ENT("UA", 0x36, 1, 0x7FB), /* Ukraine */
+ COUNTRY_CHPLAN_ENT("UG", 0x26, 1, 0x6F1), /* Uganda */
+ COUNTRY_CHPLAN_ENT("US", 0x76, 1, 0x7FF), /* United States of America (USA) */
+ COUNTRY_CHPLAN_ENT("UY", 0x30, 1, 0x7F1), /* Uruguay */
+ COUNTRY_CHPLAN_ENT("UZ", 0x47, 1, 0x6F0), /* Uzbekistan */
+ COUNTRY_CHPLAN_ENT("VA", 0x26, 1, 0x000), /* Holy See (Vatican City) */
+ COUNTRY_CHPLAN_ENT("VC", 0x34, 1, 0x010), /* Saint Vincent and the Grenadines */
+ COUNTRY_CHPLAN_ENT("VE", 0x30, 1, 0x7F1), /* Venezuela */
+ COUNTRY_CHPLAN_ENT("VI", 0x34, 1, 0x000), /* United States Virgin Islands (USA) */
+ COUNTRY_CHPLAN_ENT("VN", 0x26, 1, 0x7F1), /* Vietnam */
+ COUNTRY_CHPLAN_ENT("VU", 0x26, 1, 0x000), /* Vanuatu */
+ COUNTRY_CHPLAN_ENT("WF", 0x26, 1, 0x000), /* Wallis and Futuna (France) */
+ COUNTRY_CHPLAN_ENT("WS", 0x34, 1, 0x000), /* Samoa */
+ COUNTRY_CHPLAN_ENT("YE", 0x26, 1, 0x040), /* Yemen */
+ COUNTRY_CHPLAN_ENT("YT", 0x26, 1, 0x680), /* Mayotte (France) */
+ COUNTRY_CHPLAN_ENT("ZA", 0x26, 1, 0x7F1), /* South Africa */
+ COUNTRY_CHPLAN_ENT("ZM", 0x26, 1, 0x6B0), /* Zambia */
+ COUNTRY_CHPLAN_ENT("ZW", 0x26, 1, 0x7F1), /* Zimbabwe */
+};
/*
* rtw_get_chplan_from_country -
@@ -745,7 +989,11 @@ u16 const country_chplan_map_sz = sizeof(country_chplan_map) / sizeof(struct cou
*
* Return pointer of struct country_chplan entry or NULL when unsupported country_code is given
*/
-const struct country_chplan *rtw_get_chplan_from_country(const char *country_code) {
+const struct country_chplan *rtw_get_chplan_from_country(const char *country_code)
+{
+#if RTW_DEF_MODULE_REGULATORY_CERT
+ const struct country_chplan *exc_ent = NULL;
+#endif
const struct country_chplan *ent = NULL;
const struct country_chplan *map = NULL;
u16 map_sz = 0;
@@ -755,18 +1003,15 @@ const struct country_chplan *rtw_get_chplan_from_country(const char *country_cod
code[0] = alpha_to_upper(country_code[0]);
code[1] = alpha_to_upper(country_code[1]);
-#if !defined(CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP) && RTW_DEF_MODULE_REGULATORY_CERT
- ent = rtw_def_module_get_chplan_from_country(code);
- if (ent != NULL)
- goto exit;
-#endif
-
#ifdef CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP
map = CUSTOMIZED_country_chplan_map;
- map_sz = CUSTOMIZED_country_chplan_map_sz;
+ map_sz = sizeof(CUSTOMIZED_country_chplan_map) / sizeof(struct country_chplan);
#else
+ #if RTW_DEF_MODULE_REGULATORY_CERT
+ exc_ent = rtw_def_module_get_chplan_from_country(code);
+ #endif
map = country_chplan_map;
- map_sz = country_chplan_map_sz;
+ map_sz = sizeof(country_chplan_map) / sizeof(struct country_chplan);
#endif
for (i = 0; i < map_sz; i++) {
@@ -777,20 +1022,648 @@ const struct country_chplan *rtw_get_chplan_from_country(const char *country_cod
}
exit:
-#if RTW_DEF_MODULE_REGULATORY_CERT
- if (ent && !(COUNTRY_CHPLAN_DEF_MODULE_FALGS(ent) & RTW_DEF_MODULE_REGULATORY_CERT))
- ent = NULL;
-#endif
+ #if RTW_DEF_MODULE_REGULATORY_CERT
+ if (!ent || !(COUNTRY_CHPLAN_DEF_MODULE_FALGS(ent) & RTW_DEF_MODULE_REGULATORY_CERT))
+ exc_ent = ent = NULL;
+ if (exc_ent)
+ ent = exc_ent;
+ #endif
return ent;
}
-int rtw_ch_to_bb_gain_sel(int ch) {
+const char *const _regd_str[] = {
+ "NONE",
+ "FCC",
+ "MKK",
+ "ETSI",
+ "IC",
+ "KCC",
+ "ACMA",
+ "CHILE",
+ "WW",
+};
+
+#ifdef CONFIG_TXPWR_LIMIT
+void _dump_regd_exc_list(void *sel, struct rf_ctl_t *rfctl)
+{
+ struct regd_exc_ent *ent;
+ _list *cur, *head;
+
+ RTW_PRINT_SEL(sel, "regd_exc_num:%u\n", rfctl->regd_exc_num);
+
+ if (!rfctl->regd_exc_num)
+ goto exit;
+
+ RTW_PRINT_SEL(sel, "%-7s %-6s %-9s\n", "country", "domain", "regd_name");
+
+ head = &rfctl->reg_exc_list;
+ cur = get_next(head);
+
+ while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
+ u8 has_country;
+
+ ent = LIST_CONTAINOR(cur, struct regd_exc_ent, list);
+ cur = get_next(cur);
+ has_country = (ent->country[0] == '\0' && ent->country[1] == '\0') ? 0 : 1;
+
+ RTW_PRINT_SEL(sel, " %c%c 0x%02x %s\n"
+ , has_country ? ent->country[0] : '0'
+ , has_country ? ent->country[1] : '0'
+ , ent->domain
+ , ent->regd_name
+ );
+ }
+
+exit:
+ return;
+}
+
+inline void dump_regd_exc_list(void *sel, struct rf_ctl_t *rfctl)
+{
+ _irqL irqL;
+
+ _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+ _dump_regd_exc_list(sel, rfctl);
+ _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+}
+
+void rtw_regd_exc_add_with_nlen(struct rf_ctl_t *rfctl, const char *country, u8 domain, const char *regd_name, u32 nlen)
+{
+ struct regd_exc_ent *ent;
+ _irqL irqL;
+
+ if (!regd_name || !nlen) {
+ rtw_warn_on(1);
+ goto exit;
+ }
+
+ ent = (struct regd_exc_ent *)rtw_zmalloc(sizeof(struct regd_exc_ent) + nlen + 1);
+ if (!ent)
+ goto exit;
+
+ _rtw_init_listhead(&ent->list);
+ if (country)
+ _rtw_memcpy(ent->country, country, 2);
+ ent->domain = domain;
+ _rtw_memcpy(ent->regd_name, regd_name, nlen);
+
+ _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+
+ rtw_list_insert_tail(&ent->list, &rfctl->reg_exc_list);
+ rfctl->regd_exc_num++;
+
+ _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+
+exit:
+ return;
+}
+
+inline void rtw_regd_exc_add(struct rf_ctl_t *rfctl, const char *country, u8 domain, const char *regd_name)
+{
+ rtw_regd_exc_add_with_nlen(rfctl, country, domain, regd_name, strlen(regd_name));
+}
+
+struct regd_exc_ent *_rtw_regd_exc_search(struct rf_ctl_t *rfctl, const char *country, u8 domain)
+{
+ struct regd_exc_ent *ent;
+ _list *cur, *head;
+ u8 match = 0;
+
+ head = &rfctl->reg_exc_list;
+ cur = get_next(head);
+
+ while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
+ u8 has_country;
+
+ ent = LIST_CONTAINOR(cur, struct regd_exc_ent, list);
+ cur = get_next(cur);
+ has_country = (ent->country[0] == '\0' && ent->country[1] == '\0') ? 0 : 1;
+
+ /* entry has country condition to match */
+ if (has_country) {
+ if (!country)
+ continue;
+ if (ent->country[0] != country[0]
+ || ent->country[1] != country[1])
+ continue;
+ }
+
+ /* entry has domain condition to match */
+ if (ent->domain != 0xFF) {
+ if (domain == 0xFF)
+ continue;
+ if (ent->domain != domain)
+ continue;
+ }
+
+ match = 1;
+ break;
+ }
+
+exit:
+ if (match)
+ return ent;
+ else
+ return NULL;
+}
+
+inline struct regd_exc_ent *rtw_regd_exc_search(struct rf_ctl_t *rfctl, const char *country, u8 domain)
+{
+ struct regd_exc_ent *ent;
+ _irqL irqL;
+
+ _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+ ent = _rtw_regd_exc_search(rfctl, country, domain);
+ _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+
+ return ent;
+}
+
+void rtw_regd_exc_list_free(struct rf_ctl_t *rfctl)
+{
+ struct regd_exc_ent *ent;
+ _irqL irqL;
+ _list *cur, *head;
+
+ _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+
+ head = &rfctl->reg_exc_list;
+ cur = get_next(head);
+
+ while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
+ ent = LIST_CONTAINOR(cur, struct regd_exc_ent, list);
+ cur = get_next(cur);
+ rtw_list_delete(&ent->list);
+ rtw_mfree((u8 *)ent, sizeof(struct regd_exc_ent) + strlen(ent->regd_name) + 1);
+ }
+ rfctl->regd_exc_num = 0;
+
+ _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+}
+
+void dump_txpwr_lmt(void *sel, _adapter *adapter)
+{
+#define TMP_STR_LEN 16
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+ struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+ _irqL irqL;
+ char fmt[16];
+ char tmp_str[TMP_STR_LEN];
+ s8 *lmt_idx = NULL;
+ int bw, band, ch_num, tlrs, ntx_idx, rs, i, path;
+ u8 ch, n, rfpath_num;
+
+ _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+
+ _dump_regd_exc_list(sel, rfctl);
+ RTW_PRINT_SEL(sel, "\n");
+
+ if (!rfctl->txpwr_regd_num)
+ goto release_lock;
+
+ lmt_idx = rtw_malloc(sizeof(s8) * RF_PATH_MAX * rfctl->txpwr_regd_num);
+ if (!lmt_idx) {
+ RTW_ERR("%s alloc fail\n", __func__);
+ goto release_lock;
+ }
+
+ RTW_PRINT_SEL(sel, "txpwr_lmt_2g_cck_ofdm_state:0x%02x\n", rfctl->txpwr_lmt_2g_cck_ofdm_state);
+ #ifdef CONFIG_IEEE80211_BAND_5GHZ
+ if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter))
+ RTW_PRINT_SEL(sel, "txpwr_lmt_5g_cck_ofdm_state:0x%02x\n", rfctl->txpwr_lmt_5g_cck_ofdm_state);
+ RTW_PRINT_SEL(sel, "txpwr_lmt_5g_20_40_ref:0x%02x\n", rfctl->txpwr_lmt_5g_20_40_ref);
+ #endif
+ RTW_PRINT_SEL(sel, "\n");
+
+ for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
+ if (!hal_is_band_support(adapter, band))
+ continue;
+
+ rfpath_num = (band == BAND_ON_2_4G ? hal_spec->rfpath_num_2g : hal_spec->rfpath_num_5g);
+
+ for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; bw++) {
+
+ if (bw >= CHANNEL_WIDTH_160)
+ break;
+ if (band == BAND_ON_2_4G && bw >= CHANNEL_WIDTH_80)
+ break;
+
+ if (band == BAND_ON_2_4G)
+ ch_num = CENTER_CH_2G_NUM;
+ else
+ ch_num = center_chs_5g_num(bw);
+
+ if (ch_num == 0) {
+ rtw_warn_on(1);
+ break;
+ }
+
+ for (tlrs = TXPWR_LMT_RS_CCK; tlrs < TXPWR_LMT_RS_NUM; tlrs++) {
+
+ if (band == BAND_ON_2_4G && tlrs == TXPWR_LMT_RS_VHT)
+ continue;
+ if (band == BAND_ON_5G && tlrs == TXPWR_LMT_RS_CCK)
+ continue;
+ if (bw > CHANNEL_WIDTH_20 && (tlrs == TXPWR_LMT_RS_CCK || tlrs == TXPWR_LMT_RS_OFDM))
+ continue;
+ if (bw > CHANNEL_WIDTH_40 && tlrs == TXPWR_LMT_RS_HT)
+ continue;
+ if (tlrs == TXPWR_LMT_RS_VHT && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter))
+ continue;
+
+ for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
+ struct txpwr_lmt_ent *ent;
+ _list *cur, *head;
+
+ if (ntx_idx >= hal_spec->tx_nss_num)
+ continue;
+
+ /* bypass CCK multi-TX is not defined */
+ if (tlrs == TXPWR_LMT_RS_CCK && ntx_idx > RF_1TX) {
+ if (band == BAND_ON_2_4G
+ && !(rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_CCK_1T << ntx_idx)))
+ continue;
+ }
+
+ /* bypass OFDM multi-TX is not defined */
+ if (tlrs == TXPWR_LMT_RS_OFDM && ntx_idx > RF_1TX) {
+ if (band == BAND_ON_2_4G
+ && !(rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx)))
+ continue;
+ #ifdef CONFIG_IEEE80211_BAND_5GHZ
+ if (band == BAND_ON_5G
+ && !(rfctl->txpwr_lmt_5g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx)))
+ continue;
+ #endif
+ }
+
+ /* bypass 5G 20M, 40M pure reference */
+ #ifdef CONFIG_IEEE80211_BAND_5GHZ
+ if (band == BAND_ON_5G && (bw == CHANNEL_WIDTH_20 || bw == CHANNEL_WIDTH_40)) {
+ if (rfctl->txpwr_lmt_5g_20_40_ref == TXPWR_LMT_REF_HT_FROM_VHT) {
+ if (tlrs == TXPWR_LMT_RS_HT)
+ continue;
+ } else if (rfctl->txpwr_lmt_5g_20_40_ref == TXPWR_LMT_REF_VHT_FROM_HT) {
+ if (tlrs == TXPWR_LMT_RS_VHT && bw <= CHANNEL_WIDTH_40)
+ continue;
+ }
+ }
+ #endif
+
+ /* choose n-SS mapping rate section to get lmt diff value */
+ if (tlrs == TXPWR_LMT_RS_CCK)
+ rs = CCK;
+ else if (tlrs == TXPWR_LMT_RS_OFDM)
+ rs = OFDM;
+ else if (tlrs == TXPWR_LMT_RS_HT)
+ rs = HT_1SS + ntx_idx;
+ else if (tlrs == TXPWR_LMT_RS_VHT)
+ rs = VHT_1SS + ntx_idx;
+ else {
+ RTW_ERR("%s invalid tlrs %u\n", __func__, tlrs);
+ continue;
+ }
+
+ RTW_PRINT_SEL(sel, "[%s][%s][%s][%uT]\n"
+ , band_str(band)
+ , ch_width_str(bw)
+ , txpwr_lmt_rs_str(tlrs)
+ , ntx_idx + 1
+ );
+
+ /* header for limit in db */
+ RTW_PRINT_SEL(sel, "%3s ", "ch");
+
+ head = &rfctl->txpwr_lmt_list;
+ cur = get_next(head);
+ while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
+ ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
+ cur = get_next(cur);
+
+ sprintf(fmt, "%%%zus%%s ", strlen(ent->regd_name) < 4 ? 5 - strlen(ent->regd_name) : 1);
+ snprintf(tmp_str, TMP_STR_LEN, fmt
+ , strcmp(ent->regd_name, rfctl->regd_name) == 0 ? "*" : ""
+ , ent->regd_name);
+ _RTW_PRINT_SEL(sel, "%s", tmp_str);
+ }
+ sprintf(fmt, "%%%zus%%s ", strlen(regd_str(TXPWR_LMT_WW)) < 4 ? 5 - strlen(regd_str(TXPWR_LMT_WW)) : 1);
+ snprintf(tmp_str, TMP_STR_LEN, fmt
+ , strcmp(rfctl->regd_name, regd_str(TXPWR_LMT_WW)) == 0 ? "*" : ""
+ , regd_str(TXPWR_LMT_WW));
+ _RTW_PRINT_SEL(sel, "%s", tmp_str);
+
+ /* header for limit offset */
+ for (path = 0; path < RF_PATH_MAX; path++) {
+ if (path >= rfpath_num)
+ break;
+ _RTW_PRINT_SEL(sel, "|");
+ head = &rfctl->txpwr_lmt_list;
+ cur = get_next(head);
+ while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
+ ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
+ cur = get_next(cur);
+ _RTW_PRINT_SEL(sel, "%3c "
+ , strcmp(ent->regd_name, rfctl->regd_name) == 0 ? rf_path_char(path) : ' ');
+ }
+ _RTW_PRINT_SEL(sel, "%3c "
+ , strcmp(rfctl->regd_name, regd_str(TXPWR_LMT_WW)) == 0 ? rf_path_char(path) : ' ');
+ }
+ _RTW_PRINT_SEL(sel, "\n");
+
+ for (n = 0; n < ch_num; n++) {
+ s8 lmt;
+ s8 lmt_offset;
+ u8 base;
+
+ if (band == BAND_ON_2_4G)
+ ch = n + 1;
+ else
+ ch = center_chs_5g(bw, n);
+
+ if (ch == 0) {
+ rtw_warn_on(1);
+ break;
+ }
+
+ /* dump limit in db */
+ RTW_PRINT_SEL(sel, "%3u ", ch);
+ head = &rfctl->txpwr_lmt_list;
+ cur = get_next(head);
+ while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
+ ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
+ cur = get_next(cur);
+ lmt = phy_get_txpwr_lmt_abs(adapter, ent->regd_name, band, bw, tlrs, ntx_idx, ch, 0);
+ if (lmt == MAX_POWER_INDEX) {
+ sprintf(fmt, "%%%zus ", strlen(ent->regd_name) >= 5 ? strlen(ent->regd_name) + 1 : 5);
+ snprintf(tmp_str, TMP_STR_LEN, fmt, "NA");
+ _RTW_PRINT_SEL(sel, "%s", tmp_str);
+ } else {
+ if (lmt == -1) { /* -0.5 */
+ sprintf(fmt, "%%%zus ", strlen(ent->regd_name) >= 5 ? strlen(ent->regd_name) + 1 : 5);
+ snprintf(tmp_str, TMP_STR_LEN, fmt, "-0.5");
+ _RTW_PRINT_SEL(sel, "%s", tmp_str);
+ } else if (lmt % 2) { /* n.5 */
+ sprintf(fmt, "%%%zud.5 ", strlen(ent->regd_name) >= 5 ? strlen(ent->regd_name) - 1 : 3);
+ snprintf(tmp_str, TMP_STR_LEN, fmt, lmt / 2);
+ _RTW_PRINT_SEL(sel, "%s", tmp_str);
+ } else { /* n */
+ sprintf(fmt, "%%%zud ", strlen(ent->regd_name) >= 5 ? strlen(ent->regd_name) + 1 : 5);
+ snprintf(tmp_str, TMP_STR_LEN, fmt, lmt / 2);
+ _RTW_PRINT_SEL(sel, "%s", tmp_str);
+ }
+ }
+ }
+ lmt = phy_get_txpwr_lmt_abs(adapter, regd_str(TXPWR_LMT_WW), band, bw, tlrs, ntx_idx, ch, 0);
+ if (lmt == MAX_POWER_INDEX) {
+ sprintf(fmt, "%%%zus ", strlen(regd_str(TXPWR_LMT_WW)) >= 5 ? strlen(regd_str(TXPWR_LMT_WW)) + 1 : 5);
+ snprintf(tmp_str, TMP_STR_LEN, fmt, "NA");
+ _RTW_PRINT_SEL(sel, "%s", tmp_str);
+ } else {
+ if (lmt == -1) { /* -0.5 */
+ sprintf(fmt, "%%%zus ", strlen(regd_str(TXPWR_LMT_WW)) >= 5 ? strlen(regd_str(TXPWR_LMT_WW)) + 1 : 5);
+ snprintf(tmp_str, TMP_STR_LEN, fmt, "-0.5");
+ _RTW_PRINT_SEL(sel, "%s", tmp_str);
+ } else if (lmt % 2) { /* n.5 */
+ sprintf(fmt, "%%%zud.5 ", strlen(regd_str(TXPWR_LMT_WW)) >= 5 ? strlen(regd_str(TXPWR_LMT_WW)) - 1 : 3);
+ snprintf(tmp_str, TMP_STR_LEN, fmt, lmt / 2);
+ _RTW_PRINT_SEL(sel, "%s", tmp_str);
+ } else { /* n */
+ sprintf(fmt, "%%%zud ", strlen(regd_str(TXPWR_LMT_WW)) >= 5 ? strlen(regd_str(TXPWR_LMT_WW)) + 1 : 5);
+ snprintf(tmp_str, TMP_STR_LEN, fmt, lmt / 2);
+ _RTW_PRINT_SEL(sel, "%s", tmp_str);
+ }
+ }
+
+ /* dump limit offset of each path */
+ for (path = RF_PATH_A; path < RF_PATH_MAX; path++) {
+ if (path >= rfpath_num)
+ break;
+
+ base = PHY_GetTxPowerByRateBase(adapter, band, path, rs);
+
+ _RTW_PRINT_SEL(sel, "|");
+ head = &rfctl->txpwr_lmt_list;
+ cur = get_next(head);
+ i = 0;
+ while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
+ ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
+ cur = get_next(cur);
+ lmt_offset = phy_get_txpwr_lmt(adapter, ent->regd_name, band, bw, path, rs, ntx_idx, ch, 0);
+ if (lmt_offset == MAX_POWER_INDEX) {
+ *(lmt_idx + i * RF_PATH_MAX + path) = MAX_POWER_INDEX;
+ _RTW_PRINT_SEL(sel, "%3s ", "NA");
+ } else {
+ *(lmt_idx + i * RF_PATH_MAX + path) = lmt_offset + base;
+ _RTW_PRINT_SEL(sel, "%3d ", lmt_offset);
+ }
+ i++;
+ }
+ lmt_offset = phy_get_txpwr_lmt(adapter, regd_str(TXPWR_LMT_WW), band, bw, path, rs, ntx_idx, ch, 0);
+ if (lmt_offset == MAX_POWER_INDEX)
+ _RTW_PRINT_SEL(sel, "%3s ", "NA");
+ else
+ _RTW_PRINT_SEL(sel, "%3d ", lmt_offset);
+
+ }
+
+ /* compare limit_idx of each path, print 'x' when mismatch */
+ if (rfpath_num > 1) {
+ for (i = 0; i < rfctl->txpwr_regd_num; i++) {
+ for (path = 0; path < RF_PATH_MAX; path++) {
+ if (path >= rfpath_num)
+ break;
+ if (*(lmt_idx + i * RF_PATH_MAX + path) != *(lmt_idx + i * RF_PATH_MAX + ((path + 1) % rfpath_num)))
+ break;
+ }
+ if (path >= rfpath_num)
+ _RTW_PRINT_SEL(sel, " ");
+ else
+ _RTW_PRINT_SEL(sel, "x");
+ }
+ }
+ _RTW_PRINT_SEL(sel, "\n");
+
+ }
+ RTW_PRINT_SEL(sel, "\n");
+ }
+ } /* loop for rate sections */
+ } /* loop for bandwidths */
+ } /* loop for bands */
+
+ if (lmt_idx)
+ rtw_mfree(lmt_idx, sizeof(s8) * RF_PATH_MAX * rfctl->txpwr_regd_num);
+
+release_lock:
+ _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+}
+
+/* search matcing first, if not found, alloc one */
+void rtw_txpwr_lmt_add_with_nlen(struct rf_ctl_t *rfctl, const char *regd_name, u32 nlen
+ , u8 band, u8 bw, u8 tlrs, u8 ntx_idx, u8 ch_idx, s8 lmt)
+{
+ struct txpwr_lmt_ent *ent;
+ _irqL irqL;
+ _list *cur, *head;
+ s8 pre_lmt;
+
+ if (!regd_name || !nlen) {
+ rtw_warn_on(1);
+ goto exit;
+ }
+
+ _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+
+ /* search for existed entry */
+ head = &rfctl->txpwr_lmt_list;
+ cur = get_next(head);
+ while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
+ ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
+ cur = get_next(cur);
+
+ if (strlen(ent->regd_name) == nlen
+ && _rtw_memcmp(ent->regd_name, regd_name, nlen) == _TRUE)
+ goto chk_lmt_val;
+ }
+
+ /* alloc new one */
+ ent = (struct txpwr_lmt_ent *)rtw_zvmalloc(sizeof(struct txpwr_lmt_ent) + nlen + 1);
+ if (!ent)
+ goto release_lock;
+
+ _rtw_init_listhead(&ent->list);
+ _rtw_memcpy(ent->regd_name, regd_name, nlen);
+ {
+ u8 j, k, l, m;
+
+ for (j = 0; j < MAX_2_4G_BANDWIDTH_NUM; ++j)
+ for (k = 0; k < TXPWR_LMT_RS_NUM_2G; ++k)
+ for (m = 0; m < CENTER_CH_2G_NUM; ++m)
+ for (l = 0; l < MAX_TX_COUNT; ++l)
+ ent->lmt_2g[j][k][m][l] = MAX_POWER_INDEX;
+ #ifdef CONFIG_IEEE80211_BAND_5GHZ
+ for (j = 0; j < MAX_5G_BANDWIDTH_NUM; ++j)
+ for (k = 0; k < TXPWR_LMT_RS_NUM_5G; ++k)
+ for (m = 0; m < CENTER_CH_5G_ALL_NUM; ++m)
+ for (l = 0; l < MAX_TX_COUNT; ++l)
+ ent->lmt_5g[j][k][m][l] = MAX_POWER_INDEX;
+ #endif
+ }
+
+ rtw_list_insert_tail(&ent->list, &rfctl->txpwr_lmt_list);
+ rfctl->txpwr_regd_num++;
+
+chk_lmt_val:
+ if (band == BAND_ON_2_4G)
+ pre_lmt = ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx];
+ #ifdef CONFIG_IEEE80211_BAND_5GHZ
+ else if (band == BAND_ON_5G)
+ pre_lmt = ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx];
+ #endif
+ else
+ goto release_lock;
+
+ if (pre_lmt != MAX_POWER_INDEX)
+ RTW_PRINT("duplicate txpwr_lmt for [%s][%s][%s][%s][%uT][%d]\n"
+ , regd_name, band_str(band), ch_width_str(bw), txpwr_lmt_rs_str(tlrs), ntx_idx + 1
+ , band == BAND_ON_2_4G ? ch_idx + 1 : center_ch_5g_all[ch_idx]);
+
+ lmt = rtw_min(pre_lmt, lmt);
+ if (band == BAND_ON_2_4G)
+ ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx] = lmt;
+ #ifdef CONFIG_IEEE80211_BAND_5GHZ
+ else if (band == BAND_ON_5G)
+ ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx] = lmt;
+ #endif
+
+ if (0)
+ RTW_PRINT("%s, %4s, %6s, %7s, %uT, ch%3d = %d\n"
+ , regd_name, band_str(band), ch_width_str(bw), txpwr_lmt_rs_str(tlrs), ntx_idx + 1
+ , band == BAND_ON_2_4G ? ch_idx + 1 : center_ch_5g_all[ch_idx]
+ , lmt);
+
+release_lock:
+ _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+
+exit:
+ return;
+}
+
+inline void rtw_txpwr_lmt_add(struct rf_ctl_t *rfctl, const char *regd_name
+ , u8 band, u8 bw, u8 tlrs, u8 ntx_idx, u8 ch_idx, s8 lmt)
+{
+ rtw_txpwr_lmt_add_with_nlen(rfctl, regd_name, strlen(regd_name)
+ , band, bw, tlrs, ntx_idx, ch_idx, lmt);
+}
+
+struct txpwr_lmt_ent *_rtw_txpwr_lmt_get_by_name(struct rf_ctl_t *rfctl, const char *regd_name)
+{
+ struct txpwr_lmt_ent *ent;
+ _list *cur, *head;
+ u8 found = 0;
+
+ head = &rfctl->txpwr_lmt_list;
+ cur = get_next(head);
+
+ while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
+ ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
+ cur = get_next(cur);
+
+ if (strcmp(ent->regd_name, regd_name) == 0) {
+ found = 1;
+ break;
+ }
+ }
+
+ if (found)
+ return ent;
+ return NULL;
+}
+
+inline struct txpwr_lmt_ent *rtw_txpwr_lmt_get_by_name(struct rf_ctl_t *rfctl, const char *regd_name)
+{
+ struct txpwr_lmt_ent *ent;
+ _irqL irqL;
+
+ _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+ ent = _rtw_txpwr_lmt_get_by_name(rfctl, regd_name);
+ _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+
+ return ent;
+}
+
+void rtw_txpwr_lmt_list_free(struct rf_ctl_t *rfctl)
+{
+ struct txpwr_lmt_ent *ent;
+ _irqL irqL;
+ _list *cur, *head;
+
+ _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+
+ head = &rfctl->txpwr_lmt_list;
+ cur = get_next(head);
+
+ while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
+ ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
+ cur = get_next(cur);
+ if (ent->regd_name == rfctl->regd_name)
+ rfctl->regd_name = regd_str(TXPWR_LMT_NONE);
+ rtw_list_delete(&ent->list);
+ rtw_vmfree((u8 *)ent, sizeof(struct txpwr_lmt_ent) + strlen(ent->regd_name) + 1);
+ }
+ rfctl->txpwr_regd_num = 0;
+
+ _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+}
+#endif /* CONFIG_TXPWR_LIMIT */
+
+int rtw_ch_to_bb_gain_sel(int ch)
+{
int sel = -1;
if (ch >= 1 && ch <= 14)
sel = BB_GAIN_2G;
-#ifdef CONFIG_NL80211_BAND_5GHZ
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
else if (ch >= 36 && ch < 48)
sel = BB_GAIN_5GLB1;
else if (ch >= 52 && ch <= 64)
@@ -806,7 +1679,8 @@ int rtw_ch_to_bb_gain_sel(int ch) {
return sel;
}
-s8 rtw_rf_get_kfree_tx_gain_offset(_adapter *padapter, u8 path, u8 ch) {
+s8 rtw_rf_get_kfree_tx_gain_offset(_adapter *padapter, u8 path, u8 ch)
+{
s8 kfree_offset = 0;
#ifdef CONFIG_RF_POWER_TRIM
@@ -821,49 +1695,71 @@ s8 rtw_rf_get_kfree_tx_gain_offset(_adapter *padapter, u8 path, u8 ch) {
if (kfree_data->flag & KFREE_FLAG_ON) {
kfree_offset = kfree_data->bb_gain[bb_gain_sel][path];
- if (1)
+ if (IS_HARDWARE_TYPE_8723D(padapter))
+ RTW_INFO("%s path:%s, ch:%u, bb_gain_sel:%d, kfree_offset:%d\n"
+ , __func__, (path == 0)?"S1":"S0",
+ ch, bb_gain_sel, kfree_offset);
+ else
RTW_INFO("%s path:%u, ch:%u, bb_gain_sel:%d, kfree_offset:%d\n"
- , __func__, path, ch, bb_gain_sel, kfree_offset);
+ , __func__, path, ch, bb_gain_sel, kfree_offset);
}
exit:
#endif /* CONFIG_RF_POWER_TRIM */
return kfree_offset;
}
-void rtw_rf_set_tx_gain_offset(_adapter *adapter, u8 path, s8 offset) {
+void rtw_rf_set_tx_gain_offset(_adapter *adapter, u8 path, s8 offset)
+{
u8 write_value;
-
- RTW_INFO("kfree gain_offset 0x55:0x%x ", rtw_hal_read_rfreg(adapter, path, 0x55, 0xffffffff));
+ u8 target_path = 0;
+ u32 val32 = 0;
+
+ if (IS_HARDWARE_TYPE_8723D(adapter)) {
+ target_path = RF_PATH_A; /*in 8723D case path means S0/S1*/
+ if (path == PPG_8723D_S1)
+ RTW_INFO("kfree gain_offset 0x55:0x%x ",
+ rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff));
+ else if (path == PPG_8723D_S0)
+ RTW_INFO("kfree gain_offset 0x65:0x%x ",
+ rtw_hal_read_rfreg(adapter, target_path, 0x65, 0xffffffff));
+ } else {
+ target_path = path;
+ RTW_INFO("kfree gain_offset 0x55:0x%x ", rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff));
+ }
+
switch (rtw_get_chip_type(adapter)) {
#ifdef CONFIG_RTL8723D
case RTL8723D:
write_value = RF_TX_GAIN_OFFSET_8723D(offset);
- rtw_hal_write_rfreg(adapter, path, 0x55, 0x0fc000, write_value);
+ if (path == PPG_8723D_S1)
+ rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0f8000, write_value);
+ else if (path == PPG_8723D_S0)
+ rtw_hal_write_rfreg(adapter, target_path, 0x65, 0x0f8000, write_value);
break;
#endif /* CONFIG_RTL8723D */
#ifdef CONFIG_RTL8703B
case RTL8703B:
write_value = RF_TX_GAIN_OFFSET_8703B(offset);
- rtw_hal_write_rfreg(adapter, path, 0x55, 0x0fc000, write_value);
+ rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0fc000, write_value);
break;
#endif /* CONFIG_RTL8703B */
#ifdef CONFIG_RTL8188F
case RTL8188F:
write_value = RF_TX_GAIN_OFFSET_8188F(offset);
- rtw_hal_write_rfreg(adapter, path, 0x55, 0x0fc000, write_value);
+ rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0fc000, write_value);
break;
#endif /* CONFIG_RTL8188F */
#ifdef CONFIG_RTL8192E
case RTL8192E:
write_value = RF_TX_GAIN_OFFSET_8192E(offset);
- rtw_hal_write_rfreg(adapter, path, 0x55, 0x0f8000, write_value);
+ rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0f8000, write_value);
break;
#endif /* CONFIG_RTL8188F */
#ifdef CONFIG_RTL8821A
case RTL8821:
write_value = RF_TX_GAIN_OFFSET_8821A(offset);
- rtw_hal_write_rfreg(adapter, path, 0x55, 0x0f8000, write_value);
+ rtw_hal_write_rfreg(adapter, target_path, 0x55, 0x0f8000, write_value);
break;
#endif /* CONFIG_RTL8821A */
#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
@@ -878,42 +1774,70 @@ void rtw_rf_set_tx_gain_offset(_adapter *adapter, u8 path, s8 offset) {
rtw_warn_on(1);
break;
}
-
- RTW_INFO(" after :0x%x\n", rtw_hal_read_rfreg(adapter, path, 0x55, 0xffffffff));
+
+ if (IS_HARDWARE_TYPE_8723D(adapter)) {
+ if (path == PPG_8723D_S1)
+ val32 = rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff);
+ else if (path == PPG_8723D_S0)
+ val32 = rtw_hal_read_rfreg(adapter, target_path, 0x65, 0xffffffff);
+ } else {
+ val32 = rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff);
+ }
+ RTW_INFO(" after :0x%x\n", val32);
}
-void rtw_rf_apply_tx_gain_offset(_adapter *adapter, u8 ch) {
+void rtw_rf_apply_tx_gain_offset(_adapter *adapter, u8 ch)
+{
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
s8 kfree_offset = 0;
s8 tx_pwr_track_offset = 0; /* TODO: 8814A should consider tx pwr track when setting tx gain offset */
s8 total_offset;
- int i;
+ int i, total = 0;
+
+ if (IS_HARDWARE_TYPE_8723D(adapter))
+ total = 2; /* S1 and S0 */
+ else
+ total = hal_data->NumTotalRFPath;
- for (i = 0; i < hal_data->NumTotalRFPath; i++) {
+ for (i = 0; i < total; i++) {
kfree_offset = rtw_rf_get_kfree_tx_gain_offset(adapter, i, ch);
total_offset = kfree_offset + tx_pwr_track_offset;
rtw_rf_set_tx_gain_offset(adapter, i, total_offset);
}
}
-bool rtw_is_dfs_range(u32 hi, u32 lo) {
- return rtw_is_range_overlap(hi, lo, 5720 + 10, 5260 - 10) ? _TRUE : _FALSE;
+inline u8 rtw_is_dfs_range(u32 hi, u32 lo)
+{
+ return rtw_is_range_overlap(hi, lo, 5720 + 10, 5260 - 10);
}
-bool rtw_is_dfs_ch(u8 ch, u8 bw, u8 offset) {
+u8 rtw_is_dfs_ch(u8 ch)
+{
u32 hi, lo;
- if (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE)
- return _FALSE;
+ if (!rtw_chbw_to_freq_range(ch, CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE, &hi, &lo))
+ return 0;
+
+ return rtw_is_dfs_range(hi, lo);
+}
+
+u8 rtw_is_dfs_chbw(u8 ch, u8 bw, u8 offset)
+{
+ u32 hi, lo;
+
+ if (!rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo))
+ return 0;
- return rtw_is_dfs_range(hi, lo) ? _TRUE : _FALSE;
+ return rtw_is_dfs_range(hi, lo);
}
-bool rtw_is_long_cac_range(u32 hi, u32 lo, u8 dfs_region) {
- return (dfs_region == PHYDM_DFS_DOMAIN_ETSI && rtw_is_range_overlap(hi, lo, 5660 + 10, 5600 - 10)) ? _TRUE : _FALSE;
+bool rtw_is_long_cac_range(u32 hi, u32 lo, u8 dfs_region)
+{
+ return (dfs_region == PHYDM_DFS_DOMAIN_ETSI && rtw_is_range_overlap(hi, lo, 5650, 5600)) ? _TRUE : _FALSE;
}
-bool rtw_is_long_cac_ch(u8 ch, u8 bw, u8 offset, u8 dfs_region) {
+bool rtw_is_long_cac_ch(u8 ch, u8 bw, u8 offset, u8 dfs_region)
+{
u32 hi, lo;
if (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE)
diff --git a/core/rtw_rm.c b/core/rtw_rm.c
new file mode 100644
index 0000000..0e76b08
--- /dev/null
+++ b/core/rtw_rm.c
@@ -0,0 +1,2493 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#include
+#include
+#include "rtw_rm_fsm.h"
+
+#define pstr(s) s+strlen(s)
+
+u8 rm_post_event_hdl(_adapter *padapter, u8 *pbuf)
+{
+#ifdef CONFIG_RTW_80211K
+ struct rm_event *pev = (struct rm_event *)pbuf;
+
+ _rm_post_event(padapter, pev->rmid, pev->evid);
+ rm_handler(padapter, pev);
+#endif
+ return H2C_SUCCESS;
+}
+
+#ifdef CONFIG_RTW_80211K
+
+/* 802.11-2012 Table E-1 Operationg classes in United States */
+static RT_OPERATING_CLASS RTW_OP_CLASS_US[] = {
+ /* 0, OP_CLASS_NULL */ { 0, 0, {}},
+ /* 1, OP_CLASS_1 */ {115, 4, {36, 40, 44, 48}},
+ /* 2, OP_CLASS_2 */ {118, 4, {52, 56, 60, 64}},
+ /* 3, OP_CLASS_3 */ {124, 4, {149, 153, 157, 161}},
+ /* 4, OP_CLASS_4 */ {121, 11, {100, 104, 108, 112, 116, 120, 124,
+ 128, 132, 136, 140}},
+ /* 5, OP_CLASS_5 */ {125, 5, {149, 153, 157, 161, 165}},
+ /* 6, OP_CLASS_12 */ { 81, 11, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11}}
+};
+
+struct cmd_meas_type_ {
+ u8 id;
+ char *name;
+};
+
+char *rm_type_req_name(u8 meas_type) {
+
+ switch (meas_type) {
+ case basic_req:
+ return "basic_req";
+ case cca_req:
+ return "cca_req";
+ case rpi_histo_req:
+ return "rpi_histo_req";
+ case ch_load_req:
+ return "ch_load_req";
+ case noise_histo_req:
+ return "noise_histo_req";
+ case bcn_req:
+ return "bcn_req";
+ case frame_req:
+ return "frame_req";
+ case sta_statis_req:
+ return "sta_statis_req";
+ }
+ return "unknown_req";
+};
+
+char *rm_type_rep_name(u8 meas_type) {
+
+ switch (meas_type) {
+ case basic_rep:
+ return "basic_rep";
+ case cca_rep:
+ return "cca_rep";
+ case rpi_histo_rep:
+ return "rpi_histo_rep";
+ case ch_load_rep:
+ return "ch_load_rep";
+ case noise_histo_rep:
+ return "noise_histo_rep";
+ case bcn_rep:
+ return "bcn_rep";
+ case frame_rep:
+ return "frame_rep";
+ case sta_statis_rep:
+ return "sta_statis_rep";
+ }
+ return "unknown_rep";
+};
+
+char *rm_en_cap_name(enum rm_cap_en en)
+{
+ switch (en) {
+ case RM_LINK_MEAS_CAP_EN:
+ return "RM_LINK_MEAS_CAP_EN";
+ case RM_NB_REP_CAP_EN:
+ return "RM_NB_REP_CAP_EN";
+ case RM_PARAL_MEAS_CAP_EN:
+ return "RM_PARAL_MEAS_CAP_EN";
+ case RM_REPEAT_MEAS_CAP_EN:
+ return "RM_REPEAT_MEAS_CAP_EN";
+ case RM_BCN_PASSIVE_MEAS_CAP_EN:
+ return "RM_BCN_PASSIVE_MEAS_CAP_EN";
+ case RM_BCN_ACTIVE_MEAS_CAP_EN:
+ return "RM_BCN_ACTIVE_MEAS_CAP_EN";
+ case RM_BCN_TABLE_MEAS_CAP_EN:
+ return "RM_BCN_TABLE_MEAS_CAP_EN";
+ case RM_BCN_MEAS_REP_COND_CAP_EN:
+ return "RM_BCN_MEAS_REP_COND_CAP_EN";
+
+ case RM_FRAME_MEAS_CAP_EN:
+ return "RM_FRAME_MEAS_CAP_EN";
+ case RM_CH_LOAD_CAP_EN:
+ return "RM_CH_LOAD_CAP_EN";
+ case RM_NOISE_HISTO_CAP_EN:
+ return "RM_NOISE_HISTO_CAP_EN";
+ case RM_STATIS_MEAS_CAP_EN:
+ return "RM_STATIS_MEAS_CAP_EN";
+ case RM_LCI_MEAS_CAP_EN:
+ return "RM_LCI_MEAS_CAP_EN";
+ case RM_LCI_AMIMUTH_CAP_EN:
+ return "RM_LCI_AMIMUTH_CAP_EN";
+ case RM_TRANS_STREAM_CAT_MEAS_CAP_EN:
+ return "RM_TRANS_STREAM_CAT_MEAS_CAP_EN";
+ case RM_TRIG_TRANS_STREAM_CAT_MEAS_CAP_EN:
+ return "RM_TRIG_TRANS_STREAM_CAT_MEAS_CAP_EN";
+
+ case RM_AP_CH_REP_CAP_EN:
+ return "RM_AP_CH_REP_CAP_EN";
+ case RM_RM_MIB_CAP_EN:
+ return "RM_RM_MIB_CAP_EN";
+ case RM_OP_CH_MAX_MEAS_DUR0:
+ return "RM_OP_CH_MAX_MEAS_DUR0";
+ case RM_OP_CH_MAX_MEAS_DUR1:
+ return "RM_OP_CH_MAX_MEAS_DUR1";
+ case RM_OP_CH_MAX_MEAS_DUR2:
+ return "RM_OP_CH_MAX_MEAS_DUR2";
+ case RM_NONOP_CH_MAX_MEAS_DUR0:
+ return "RM_NONOP_CH_MAX_MEAS_DUR0";
+ case RM_NONOP_CH_MAX_MEAS_DUR1:
+ return "RM_NONOP_CH_MAX_MEAS_DUR1";
+ case RM_NONOP_CH_MAX_MEAS_DUR2:
+ return "RM_NONOP_CH_MAX_MEAS_DUR2";
+
+ case RM_MEAS_PILOT_CAP0:
+ return "RM_MEAS_PILOT_CAP0"; /* 24-26 */
+ case RM_MEAS_PILOT_CAP1:
+ return "RM_MEAS_PILOT_CAP1";
+ case RM_MEAS_PILOT_CAP2:
+ return "RM_MEAS_PILOT_CAP2";
+ case RM_MEAS_PILOT_TRANS_INFO_CAP_EN:
+ return "RM_MEAS_PILOT_TRANS_INFO_CAP_EN";
+ case RM_NB_REP_TSF_OFFSET_CAP_EN:
+ return "RM_NB_REP_TSF_OFFSET_CAP_EN";
+ case RM_RCPI_MEAS_CAP_EN:
+ return "RM_RCPI_MEAS_CAP_EN"; /* 29 */
+ case RM_RSNI_MEAS_CAP_EN:
+ return "RM_RSNI_MEAS_CAP_EN";
+ case RM_BSS_AVG_ACCESS_DELAY_CAP_EN:
+ return "RM_BSS_AVG_ACCESS_DELAY_CAP_EN";
+
+ case RM_AVALB_ADMIS_CAPACITY_CAP_EN:
+ return "RM_AVALB_ADMIS_CAPACITY_CAP_EN";
+ case RM_ANT_CAP_EN:
+ return "RM_ANT_CAP_EN";
+ case RM_RSVD:
+ case RM_MAX:
+ default:
+ break;
+ }
+ return "unknown";
+}
+
+int rm_en_cap_chk_and_set(struct rm_obj *prm, enum rm_cap_en en)
+{
+ int idx;
+ u8 cap;
+
+
+ if (en >= RM_MAX)
+ return _FALSE;
+
+ idx = en / 8;
+ cap = prm->psta->padapter->rmpriv.rm_en_cap_def[idx];
+
+ if (!(cap & BIT(en - (idx*8)))) {
+ RTW_INFO("RM: %s incapable\n",rm_en_cap_name(en));
+ rm_set_rep_mode(prm, MEAS_REP_MOD_INCAP);
+ return _FALSE;
+ }
+ return _SUCCESS;
+}
+
+static u8 rm_get_oper_class_via_ch(u8 ch)
+{
+ int i,j,sz;
+
+
+ sz = sizeof(RTW_OP_CLASS_US)/sizeof(struct _RT_OPERATING_CLASS);
+
+ for (i = 0; i < sz; i++) {
+ for (j = 0; j < RTW_OP_CLASS_US[i].Len; j++) {
+ if ( ch == RTW_OP_CLASS_US[i].Channel[j]) {
+ RTW_INFO("RM: ch %u in oper_calss %u\n",
+ ch, RTW_OP_CLASS_US[i].global_op_class);
+ return RTW_OP_CLASS_US[i].global_op_class;
+ break;
+ }
+ }
+ }
+ return 0;
+}
+
+static u8 rm_get_ch_set(
+ struct rtw_ieee80211_channel *pch_set, u8 op_class, u8 ch_num)
+{
+ int i,j,sz;
+ u8 ch_amount = 0;
+
+
+ sz = sizeof(RTW_OP_CLASS_US)/sizeof(struct _RT_OPERATING_CLASS);
+
+ if (ch_num != 0) {
+ pch_set[0].hw_value = ch_num;
+ ch_amount = 1;
+ RTW_INFO("RM: meas_ch->hw_value = %u\n", pch_set->hw_value);
+ goto done;
+ }
+
+ for (i = 0; i < sz; i++) {
+
+ if (RTW_OP_CLASS_US[i].global_op_class == op_class) {
+
+ for (j = 0; j < RTW_OP_CLASS_US[i].Len; j++) {
+ pch_set[j].hw_value =
+ RTW_OP_CLASS_US[i].Channel[j];
+ RTW_INFO("RM: meas_ch[%d].hw_value = %u\n",
+ j, pch_set[j].hw_value);
+ }
+ ch_amount = RTW_OP_CLASS_US[i].Len;
+ break;
+ }
+ }
+done:
+ return ch_amount;
+}
+
+static int is_wildcard_bssid(u8 *bssid)
+{
+ int i;
+ u8 val8 = 0xff;
+
+
+ for (i=0;i<6;i++)
+ val8 &= bssid[i];
+
+ if (val8 == 0xff)
+ return _SUCCESS;
+ return _FALSE;
+}
+
+/* for caller outside rm */
+u8 rm_add_nb_req(_adapter *padapter, struct sta_info *psta)
+{
+ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+ struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
+ struct rm_obj *prm;
+
+
+ prm = rm_alloc_rmobj(padapter);
+
+ if (prm == NULL) {
+ RTW_ERR("RM: unable to alloc rm obj for requeset\n");
+ return _FALSE;
+ }
+
+ prm->psta = psta;
+ prm->q.category = RTW_WLAN_CATEGORY_RADIO_MEAS;
+ prm->q.diag_token = pmlmeinfo->dialogToken++;
+ prm->q.m_token = 1;
+
+ prm->rmid = psta->cmn.aid << 16
+ | prm->q.diag_token << 8
+ | RM_MASTER;
+
+ prm->q.action_code = RM_ACT_NB_REP_REQ;
+
+ #if 0
+ if (pmac) { /* find sta_info according to bssid */
+ pmac += 4; /* skip mac= */
+ if (hwaddr_parse(pmac, bssid) == NULL) {
+ sprintf(pstr(s), "Err: \nincorrect mac format\n");
+ return _FAIL;
+ }
+ psta = rm_get_sta(padapter, 0xff, bssid);
+ }
+ #endif
+
+ /* enquee rmobj */
+ rm_enqueue_rmobj(padapter, prm, _FALSE);
+
+ RTW_INFO("RM: rmid=%x add req to " MAC_FMT "\n",
+ prm->rmid, MAC_ARG(psta->cmn.mac_addr));
+
+ return _SUCCESS;
+}
+
+
+static u8 *build_wlan_hdr(_adapter *padapter, struct xmit_frame *pmgntframe,
+ struct sta_info *psta, u16 frame_type)
+{
+ u8 *pframe;
+ u16 *fctrl;
+ struct pkt_attrib *pattr;
+ struct rtw_ieee80211_hdr *pwlanhdr;
+ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+ struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
+
+
+ /* update attribute */
+ pattr = &pmgntframe->attrib;
+ update_mgntframe_attrib(padapter, pattr);
+
+ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+
+ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+ fctrl = &(pwlanhdr->frame_ctl);
+ *(fctrl) = 0;
+
+ _rtw_memcpy(pwlanhdr->addr1, psta->cmn.mac_addr, ETH_ALEN);
+ _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+ _rtw_memcpy(pwlanhdr->addr3,
+ get_my_bssid(&(pmlmeinfo->network)),ETH_ALEN);
+
+ RTW_INFO("RM: dst = " MAC_FMT "\n", MAC_ARG(pwlanhdr->addr1));
+
+ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
+ pmlmeext->mgnt_seq++;
+ SetFragNum(pframe, 0);
+
+ set_frame_sub_type(pframe, WIFI_ACTION);
+
+ pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
+ pattr->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+ return pframe;
+}
+
+void rm_set_rep_mode(struct rm_obj *prm, u8 mode)
+{
+
+ RTW_INFO("RM: rmid=%x set %s\n",
+ prm->rmid,
+ mode|MEAS_REP_MOD_INCAP?"INCAP":
+ mode|MEAS_REP_MOD_REFUSE?"REFUSE":
+ mode|MEAS_REP_MOD_LATE?"LATE":"");
+
+ prm->p.m_mode |= mode;
+}
+
+int issue_null_reply(struct rm_obj *prm)
+{
+ int len=0, my_len;
+ u8 *pframe, m_mode;
+ _adapter *padapter = prm->psta->padapter;
+ struct pkt_attrib *pattr;
+ struct xmit_frame *pmgntframe;
+ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
+
+
+ m_mode = prm->p.m_mode;
+ if (m_mode || prm->p.rpt == 0) {
+ RTW_INFO("RM: rmid=%x reply (%s repeat=%d)\n",
+ prm->rmid,
+ m_mode&MEAS_REP_MOD_INCAP?"INCAP":
+ m_mode&MEAS_REP_MOD_REFUSE?"REFUSE":
+ m_mode&MEAS_REP_MOD_LATE?"LATE":"no content",
+ prm->p.rpt);
+ }
+
+ switch (prm->p.action_code) {
+ case RM_ACT_RADIO_MEAS_REQ:
+ len = 8;
+ break;
+ case RM_ACT_NB_REP_REQ:
+ len = 3;
+ break;
+ case RM_ACT_LINK_MEAS_REQ:
+ len = 3;
+ break;
+ default:
+ break;
+ }
+
+ if (len==0)
+ return _FALSE;
+
+ pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+ if (pmgntframe == NULL) {
+ RTW_ERR("RM: %s alloc xmit_frame fail\n",__func__);
+ return _FALSE;
+ }
+ pattr = &pmgntframe->attrib;
+ pframe = build_wlan_hdr(padapter, pmgntframe, prm->psta, WIFI_ACTION);
+ pframe = rtw_set_fixed_ie(pframe, 3, &prm->p.category, &pattr->pktlen);
+
+ my_len = 0;
+ if (len>5) {
+ prm->p.len = len - 3 - 2;
+ pframe = rtw_set_fixed_ie(pframe, len - 3,
+ &prm->p.e_id, &my_len);
+ }
+
+ pattr->pktlen += my_len;
+ pattr->last_txcmdsz = pattr->pktlen;
+ dump_mgntframe(padapter, pmgntframe);
+
+ return _SUCCESS;
+}
+
+int ready_for_scan(struct rm_obj *prm)
+{
+ _adapter *padapter = prm->psta->padapter;
+ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+
+
+ if (rtw_is_scan_deny(padapter))
+ return _FALSE;
+
+ if (!rtw_is_adapter_up(padapter))
+ return _FALSE;
+
+ if (rtw_mi_busy_traffic_check(padapter, _FALSE))
+ return _FALSE;
+
+ if (check_fwstate(pmlmepriv, WIFI_AP_STATE)
+ && check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) {
+ RTW_INFO(FUNC_ADPT_FMT" WIFI_AP_STATE && WIFI_UNDER_WPS\n",
+ FUNC_ADPT_ARG(padapter));
+ return _FALSE;
+ }
+ if (check_fwstate(pmlmepriv,
+ (_FW_UNDER_SURVEY | _FW_UNDER_LINKING)) == _TRUE) {
+ RTW_INFO(FUNC_ADPT_FMT" _FW_UNDER_SURVEY|_FW_UNDER_LINKING\n",
+ FUNC_ADPT_ARG(padapter));
+ return _FALSE;
+ }
+
+#ifdef CONFIG_CONCURRENT_MODE
+ if (rtw_mi_buddy_check_fwstate(padapter,
+ (_FW_UNDER_SURVEY | _FW_UNDER_LINKING | WIFI_UNDER_WPS))) {
+ RTW_INFO(FUNC_ADPT_FMT", but buddy_intf is under scanning or linking or wps_phase\n",
+ FUNC_ADPT_ARG(padapter));
+ return _FALSE;
+ }
+#endif
+ return _SUCCESS;
+}
+
+int rm_sitesurvey(struct rm_obj *prm)
+{
+ int meas_ch_num=0;
+ u8 ch_num=0, op_class=0, val8;
+ struct rtw_ieee80211_channel *pch_set;
+ struct sitesurvey_parm parm;
+
+
+ RTW_INFO("RM: rmid=%x %s\n",prm->rmid, __func__);
+
+ pch_set = &prm->q.ch_set[0];
+
+ _rtw_memset(pch_set, 0,
+ sizeof(struct rtw_ieee80211_channel) * MAX_OP_CHANNEL_SET_NUM);
+
+ if (prm->q.ch_num == 0) {
+ /* ch_num=0 : scan all ch in operating class */
+ op_class = prm->q.op_class;
+
+ } else if (prm->q.ch_num == 255) {
+ /* 802.11 p.499 */
+ /* ch_num=255 : scan all ch in current operating class */
+ op_class = rm_get_oper_class_via_ch(
+ (u8)prm->psta->padapter->mlmeextpriv.cur_channel);
+ } else
+ ch_num = prm->q.ch_num;
+
+ /* get means channel */
+ meas_ch_num = rm_get_ch_set(pch_set, op_class, ch_num);
+ prm->q.ch_set_ch_amount = meas_ch_num;
+
+ _rtw_memset(&parm, 0, sizeof(struct sitesurvey_parm));
+ _rtw_memcpy(parm.ch, pch_set,
+ sizeof(struct rtw_ieee80211_channel) * MAX_OP_CHANNEL_SET_NUM);
+
+ _rtw_memcpy(&parm.ssid[0], &prm->q.opt.bcn.ssid, IW_ESSID_MAX_SIZE);
+
+ parm.ssid_num = 1;
+ parm.scan_mode = prm->q.m_mode;
+ parm.ch_num = meas_ch_num;
+ parm.igi = 0;
+ parm.token = prm->rmid;
+ parm.duration = prm->q.meas_dur;
+ /* parm.bw = BW_20M; */
+
+ rtw_sitesurvey_cmd(prm->psta->padapter, &parm);
+
+ return _SUCCESS;
+}
+
+static u8 translate_percentage_to_rcpi(u32 SignalStrengthIndex)
+{
+ s32 SignalPower; /* in dBm. */
+ u8 rcpi;
+
+ /* Translate to dBm (x=y-100) */
+ SignalPower = SignalStrengthIndex - 100;
+
+ /* RCPI = Int{(Power in dBm + 110)*2} for 0dBm > Power > -110dBm
+ * 0 : power <= -110.0 dBm
+ * 1 : power = -109.5 dBm
+ * 2 : power = -109.0 dBm
+ */
+
+ rcpi = (SignalPower + 110)*2;
+ return rcpi;
+}
+
+static int rm_parse_ch_load_s_elem(struct rm_obj *prm, u8 *pbody, int req_len)
+{
+ u8 *popt_id;
+ int i, p=0; /* position */
+ int len = req_len;
+
+
+ prm->q.opt_s_elem_len = len;
+#if (RM_MORE_DBG_MSG)
+ RTW_INFO("RM: opt_s_elem_len=%d\n", len);
+#endif
+ while (len) {
+
+ switch (pbody[p]) {
+ case ch_load_rep_info:
+ /* check RM_EN */
+ rm_en_cap_chk_and_set(prm, RM_CH_LOAD_CAP_EN);
+
+ _rtw_memcpy(&(prm->q.opt.clm.rep_cond),
+ &pbody[p+2], sizeof(prm->q.opt.clm.rep_cond));
+
+ RTW_INFO("RM: ch_load_rep_info=%u:%u\n",
+ prm->q.opt.clm.rep_cond.cond,
+ prm->q.opt.clm.rep_cond.threshold);
+ break;
+ default:
+ break;
+
+ }
+ len = len - (int)pbody[p+1] - 2;
+ p = p + (int)pbody[p+1] + 2;
+#if (RM_MORE_DBG_MSG)
+ RTW_INFO("RM: opt_s_elem_len=%d\n",len);
+#endif
+ }
+ return _SUCCESS;
+}
+
+static int rm_parse_noise_histo_s_elem(struct rm_obj *prm,
+ u8 *pbody, int req_len)
+{
+ u8 *popt_id;
+ int i, p=0; /* position */
+ int len = req_len;
+
+
+ prm->q.opt_s_elem_len = len;
+#if (RM_MORE_DBG_MSG)
+ RTW_INFO("RM: opt_s_elem_len=%d\n", len);
+#endif
+
+ while (len) {
+
+ switch (pbody[p]) {
+ case noise_histo_rep_info:
+ /* check RM_EN */
+ rm_en_cap_chk_and_set(prm, RM_NOISE_HISTO_CAP_EN);
+
+ _rtw_memcpy(&(prm->q.opt.nhm.rep_cond),
+ &pbody[p+2], sizeof(prm->q.opt.nhm.rep_cond));
+
+ RTW_INFO("RM: noise_histo_rep_info=%u:%u\n",
+ prm->q.opt.nhm.rep_cond.cond,
+ prm->q.opt.nhm.rep_cond.threshold);
+ break;
+ default:
+ break;
+
+ }
+ len = len - (int)pbody[p+1] - 2;
+ p = p + (int)pbody[p+1] + 2;
+#if (RM_MORE_DBG_MSG)
+ RTW_INFO("RM: opt_s_elem_len=%d\n",len);
+#endif
+ }
+ return _SUCCESS;
+}
+
+static int rm_parse_bcn_req_s_elem(struct rm_obj *prm, u8 *pbody, int req_len)
+{
+ u8 *popt_id;
+ int i, p=0; /* position */
+ int len = req_len;
+
+
+ /* opt length,2:pbody[0]+ pbody[1] */
+ /* first opt id : pbody[18] */
+
+ prm->q.opt_s_elem_len = len;
+#if (RM_MORE_DBG_MSG)
+ RTW_INFO("RM: opt_s_elem_len=%d\n", len);
+#endif
+
+ popt_id = prm->q.opt.bcn.opt_id;
+ while (len && prm->q.opt.bcn.opt_id_num < BCN_REQ_OPT_MAX_NUM) {
+
+ switch (pbody[p]) {
+ case bcn_req_ssid:
+ RTW_INFO("bcn_req_ssid\n");
+
+#if (DBG_BCN_REQ_WILDCARD)
+ RTW_INFO("DBG set ssid to WILDCARD\n");
+#else
+#if (DBG_BCN_REQ_SSID)
+ RTW_INFO("DBG set ssid to %s\n",DBG_BCN_REQ_SSID_NAME);
+ i = strlen(DBG_BCN_REQ_SSID_NAME);
+ prm->q.opt.bcn.ssid.SsidLength = i;
+ _rtw_memcpy(&(prm->q.opt.bcn.ssid.Ssid),
+ DBG_BCN_REQ_SSID_NAME, i);
+
+#else /* original */
+ prm->q.opt.bcn.ssid.SsidLength = pbody[p+1];
+ _rtw_memcpy(&(prm->q.opt.bcn.ssid.Ssid),
+ &pbody[p+2], pbody[p+1]);
+#endif
+#endif
+
+ RTW_INFO("RM: bcn_req_ssid=%s\n",
+ prm->q.opt.bcn.ssid.Ssid);
+
+ popt_id[prm->q.opt.bcn.opt_id_num++] = pbody[p];
+ break;
+
+ case bcn_req_rep_info:
+ /* check RM_EN */
+ rm_en_cap_chk_and_set(prm, RM_BCN_MEAS_REP_COND_CAP_EN);
+
+ _rtw_memcpy(&(prm->q.opt.bcn.rep_cond),
+ &pbody[p+2], sizeof(prm->q.opt.bcn.rep_cond));
+
+ RTW_INFO("bcn_req_rep_info=%u:%u\n",
+ prm->q.opt.bcn.rep_cond.cond,
+ prm->q.opt.bcn.rep_cond.threshold);
+
+ /*popt_id[prm->q.opt.bcn.opt_id_num++] = pbody[p];*/
+ break;
+
+ case bcn_req_rep_detail:
+#if DBG_BCN_REQ_DETAIL
+ prm->q.opt.bcn.rep_detail = 2; /* all IE in beacon */
+#else
+ prm->q.opt.bcn.rep_detail = pbody[p+2];
+#endif
+ popt_id[prm->q.opt.bcn.opt_id_num++] = pbody[p];
+
+#if (RM_MORE_DBG_MSG)
+ RTW_INFO("RM: report_detail=%d\n",
+ prm->q.opt.bcn.rep_detail);
+#endif
+ break;
+
+ case bcn_req_req:
+ RTW_INFO("RM: bcn_req_req\n");
+
+ prm->q.opt.bcn.req_start = rtw_malloc(pbody[p+1]);
+
+ if (prm->q.opt.bcn.req_start == NULL) {
+ RTW_ERR("RM: req_start malloc fail!!\n");
+ break;
+ }
+
+ for (i = 0; i < pbody[p+1]; i++)
+ *((prm->q.opt.bcn.req_start)+i) =
+ pbody[p+2+i];
+
+ prm->q.opt.bcn.req_len = pbody[p+1];
+ popt_id[prm->q.opt.bcn.opt_id_num++] = pbody[p];
+ break;
+
+ case bcn_req_ac_ch_rep:
+#if (RM_MORE_DBG_MSG)
+ RTW_INFO("RM: bcn_req_ac_ch_rep\n");
+#endif
+ popt_id[prm->q.opt.bcn.opt_id_num++] = pbody[p];
+ break;
+
+ default:
+ break;
+
+ }
+ len = len - (int)pbody[p+1] - 2;
+ p = p + (int)pbody[p+1] + 2;
+#if (RM_MORE_DBG_MSG)
+ RTW_INFO("RM: opt_s_elem_len=%d\n",len);
+#endif
+ }
+
+ return _SUCCESS;
+}
+
+static int rm_parse_meas_req(struct rm_obj *prm, u8 *pbody)
+{
+ int p; /* position */
+ int req_len;
+
+
+ req_len = (int)pbody[1];
+ p = 5;
+
+ prm->q.op_class = pbody[p++];
+ prm->q.ch_num = pbody[p++];
+ prm->q.rand_intvl = le16_to_cpu(*(u16*)(&pbody[p]));
+ p+=2;
+ prm->q.meas_dur = le16_to_cpu(*(u16*)(&pbody[p]));
+ p+=2;
+
+ if (prm->q.m_type == bcn_req) {
+ /*
+ * 0: passive
+ * 1: active
+ * 2: bcn_table
+ */
+ prm->q.m_mode = pbody[p++];
+
+ /* BSSID */
+ _rtw_memcpy(&(prm->q.bssid), &pbody[p], 6);
+ p+=6;
+
+ /*
+ * default, used when Reporting detail subelement
+ * is not included in Beacon Request
+ */
+ prm->q.opt.bcn.rep_detail = 2;
+ }
+
+ if (req_len-(p-2) <= 0) /* without sub-element */
+ return _SUCCESS;
+
+ switch (prm->q.m_type) {
+ case bcn_req:
+ rm_parse_bcn_req_s_elem(prm, &pbody[p], req_len-(p-2));
+ break;
+ case ch_load_req:
+ rm_parse_ch_load_s_elem(prm, &pbody[p], req_len-(p-2));
+ break;
+ case noise_histo_req:
+ rm_parse_noise_histo_s_elem(prm, &pbody[p], req_len-(p-2));
+ break;
+ default:
+ break;
+ }
+
+ return _SUCCESS;
+}
+
+/* receive measurement request */
+int rm_recv_radio_mens_req(_adapter *padapter,
+ union recv_frame *precv_frame, struct sta_info *psta)
+{
+ struct rm_obj *prm;
+ struct rm_priv *prmpriv = &padapter->rmpriv;
+ u8 *pdiag_body = (u8 *)(precv_frame->u.hdr.rx_data +
+ sizeof(struct rtw_ieee80211_hdr_3addr));
+ u8 *pmeas_body = &pdiag_body[5];
+ u8 rmid, update = 0;
+
+
+#if 0
+ /* search existing rm_obj */
+ rmid = psta->cmn.aid << 16
+ | pdiag_body[2] << 8
+ | RM_SLAVE;
+
+ prm = rm_get_rmobj(padapter, rmid);
+ if (prm) {
+ RTW_INFO("RM: Found an exist meas rmid=%u\n", rmid);
+ update = 1;
+ } else
+#endif
+ prm = rm_alloc_rmobj(padapter);
+
+ if (prm == NULL) {
+ RTW_ERR("RM: unable to alloc rm obj for requeset\n");
+ return _FALSE;
+ }
+
+ prm->psta = psta;
+ prm->q.diag_token = pdiag_body[2];
+ prm->q.rpt = le16_to_cpu(*(u16*)(&pdiag_body[3]));
+
+ /* Figure 8-104 Measurement Requested format */
+ prm->q.e_id = pmeas_body[0];
+ prm->q.m_token = pmeas_body[2];
+ prm->q.m_mode = pmeas_body[3];
+ prm->q.m_type = pmeas_body[4];
+
+ prm->rmid = psta->cmn.aid << 16
+ | prm->q.diag_token << 8
+ | RM_SLAVE;
+
+ RTW_INFO("RM: rmid=%x, bssid " MAC_FMT "\n", prm->rmid,
+ MAC_ARG(prm->psta->cmn.mac_addr));
+
+#if (RM_MORE_DBG_MSG)
+ RTW_INFO("RM: element_id = %d\n", prm->q.e_id);
+ RTW_INFO("RM: length = %d\n", (int)pmeas_body[1]);
+ RTW_INFO("RM: meas_token = %d\n", prm->q.m_token);
+ RTW_INFO("RM: meas_mode = %d\n", prm->q.m_mode);
+ RTW_INFO("RM: meas_type = %d\n", prm->q.m_type);
+#endif
+
+ if (prm->q.e_id != _MEAS_REQ_IE_) /* 38 */
+ return _FALSE;
+
+ switch (prm->q.m_type) {
+ case bcn_req:
+ RTW_INFO("RM: recv beacon_request\n");
+ switch (prm->q.m_mode) {
+ case bcn_req_passive:
+ rm_en_cap_chk_and_set(prm, RM_BCN_PASSIVE_MEAS_CAP_EN);
+ break;
+ case bcn_req_active:
+ rm_en_cap_chk_and_set(prm, RM_BCN_ACTIVE_MEAS_CAP_EN);
+ break;
+ case bcn_req_bcn_table:
+ rm_en_cap_chk_and_set(prm, RM_BCN_TABLE_MEAS_CAP_EN);
+ break;
+ default:
+ rm_set_rep_mode(prm, MEAS_REP_MOD_INCAP);
+ break;
+ }
+ break;
+ case ch_load_req:
+ RTW_INFO("RM: recv ch_load_request\n");
+ rm_en_cap_chk_and_set(prm, RM_CH_LOAD_CAP_EN);
+ break;
+ case noise_histo_req:
+ RTW_INFO("RM: recv noise_histogram_request\n");
+ rm_en_cap_chk_and_set(prm, RM_NOISE_HISTO_CAP_EN);
+ break;
+ default:
+ RTW_INFO("RM: recv unknown request type 0x%02x\n",
+ prm->q.m_type);
+ rm_set_rep_mode(prm, MEAS_REP_MOD_INCAP);
+ goto done;
+ }
+ rm_parse_meas_req(prm, pmeas_body);
+done:
+ if (!update)
+ rm_enqueue_rmobj(padapter, prm, _FALSE);
+
+ return _SUCCESS;
+}
+
+/* receive measurement report */
+int rm_recv_radio_mens_rep(_adapter *padapter,
+ union recv_frame *precv_frame, struct sta_info *psta)
+{
+ int ret = _FALSE;
+ struct rm_obj *prm;
+ u32 rmid;
+ u8 *pdiag_body = (u8 *)(precv_frame->u.hdr.rx_data +
+ sizeof(struct rtw_ieee80211_hdr_3addr));
+ u8 *pmeas_body = &pdiag_body[3];
+
+
+ rmid = psta->cmn.aid << 16
+ | pdiag_body[2] << 8
+ | RM_MASTER;
+
+ prm = rm_get_rmobj(padapter, rmid);
+ if (prm == NULL)
+ return _FALSE;
+
+ prm->p.action_code = pdiag_body[1];
+ prm->p.diag_token = pdiag_body[2];
+
+ /* Figure 8-140 Measuremnt Report format */
+ prm->p.e_id = pmeas_body[0];
+ prm->p.m_token = pmeas_body[2];
+ prm->p.m_mode = pmeas_body[3];
+ prm->p.m_type = pmeas_body[4];
+
+ RTW_INFO("RM: rmid=%x, bssid " MAC_FMT "\n", prm->rmid,
+ MAC_ARG(prm->psta->cmn.mac_addr));
+
+#if (RM_MORE_DBG_MSG)
+ RTW_INFO("RM: element_id = %d\n", prm->p.e_id);
+ RTW_INFO("RM: length = %d\n", (int)pmeas_body[1]);
+ RTW_INFO("RM: meas_token = %d\n", prm->p.m_token);
+ RTW_INFO("RM: meas_mode = %d\n", prm->p.m_mode);
+ RTW_INFO("RM: meas_type = %d\n", prm->p.m_type);
+#endif
+ if (prm->p.e_id != _MEAS_RSP_IE_) /* 39 */
+ return _FALSE;
+
+ RTW_INFO("RM: recv %s\n", rm_type_rep_name(prm->p.m_type));
+ rm_post_event(padapter, prm->rmid, RM_EV_recv_rep);
+
+ return ret;
+}
+
+int rm_radio_mens_nb_rep(_adapter *padapter,
+ union recv_frame *precv_frame, struct sta_info *psta)
+{
+ u8 *pdiag_body = (u8 *)(precv_frame->u.hdr.rx_data +
+ sizeof(struct rtw_ieee80211_hdr_3addr));
+ u8 *pmeas_body = &pdiag_body[3];
+ u32 len = precv_frame->u.hdr.len;
+ u32 rmid;
+ struct rm_obj *prm;
+
+
+ rmid = psta->cmn.aid << 16
+ | pdiag_body[2] << 8
+ | RM_MASTER;
+
+ prm = rm_get_rmobj(padapter, rmid);
+ if (prm == NULL)
+ return _FALSE;
+
+ prm->p.action_code = pdiag_body[1];
+ prm->p.diag_token = pdiag_body[2];
+ prm->p.e_id = pmeas_body[0];
+
+ RTW_INFO("RM: rmid=%x, bssid " MAC_FMT "\n", prm->rmid,
+ MAC_ARG(prm->psta->cmn.mac_addr));
+
+#if (RM_MORE_DBG_MSG)
+ RTW_INFO("RM: element_id = %d\n", prm->p.e_id);
+ RTW_INFO("RM: length = %d\n", (int)pmeas_body[1]);
+#endif
+ rm_post_event(padapter, prm->rmid, RM_EV_recv_rep);
+
+#ifdef CONFIG_LAYER2_ROAMING
+ if (rtw_wnm_btm_candidates_survey(padapter
+ ,(pdiag_body + 3)
+ ,(len - sizeof(struct rtw_ieee80211_hdr_3addr))
+ ,_FALSE) == _FAIL)
+ return _FALSE;
+#endif
+ rtw_cfg80211_rx_rrm_action(padapter, precv_frame);
+
+ return _TRUE;
+}
+
+unsigned int rm_on_action(_adapter *padapter, union recv_frame *precv_frame)
+{
+ u32 ret = _FAIL;
+ u8 *pframe = NULL;
+ u8 *pframe_body = NULL;
+ u8 action_code = 0;
+ u8 diag_token = 0;
+ struct rtw_ieee80211_hdr_3addr *whdr;
+ struct sta_info *psta;
+
+
+ pframe = precv_frame->u.hdr.rx_data;
+
+ /* check RA matches or not */
+ if (!_rtw_memcmp(adapter_mac_addr(padapter),
+ GetAddr1Ptr(pframe), ETH_ALEN))
+ goto exit;
+
+ whdr = (struct rtw_ieee80211_hdr_3addr *)pframe;
+ RTW_INFO("RM: %s bssid = " MAC_FMT "\n",
+ __func__, MAC_ARG(whdr->addr2));
+
+ psta = rtw_get_stainfo(&padapter->stapriv, whdr->addr2);
+
+ if (!psta) {
+ RTW_ERR("RM: psta not found\n");
+ goto exit;
+ }
+
+ pframe_body = (unsigned char *)(pframe +
+ sizeof(struct rtw_ieee80211_hdr_3addr));
+
+ /* Figure 8-438 radio measurement request frame Action field format */
+ /* Category = pframe_body[0] = 5 (Radio Measurement) */
+ action_code = pframe_body[1];
+ diag_token = pframe_body[2];
+
+#if (RM_MORE_DBG_MSG)
+ RTW_INFO("RM: %s radio_action=%x, diag_token=%x\n", __func__,
+ action_code, diag_token);
+#endif
+
+ switch (action_code) {
+
+ case RM_ACT_RADIO_MEAS_REQ:
+ RTW_INFO("RM: RM_ACT_RADIO_MEAS_REQ\n");
+ ret = rm_recv_radio_mens_req(padapter, precv_frame, psta);
+ break;
+
+ case RM_ACT_RADIO_MEAS_REP:
+ RTW_INFO("RM: RM_ACT_RADIO_MEAS_REP\n");
+ ret = rm_recv_radio_mens_rep(padapter, precv_frame, psta);
+ break;
+
+ case RM_ACT_LINK_MEAS_REQ:
+ RTW_INFO("RM: RM_ACT_LINK_MEAS_REQ\n");
+ break;
+
+ case RM_ACT_LINK_MEAS_REP:
+ RTW_INFO("RM: RM_ACT_LINK_MEAS_REP\n");
+ break;
+
+ case RM_ACT_NB_REP_REQ:
+ RTW_INFO("RM: RM_ACT_NB_REP_REQ\n");
+ break;
+
+ case RM_ACT_NB_REP_RESP:
+ RTW_INFO("RM: RM_ACT_NB_REP_RESP\n");
+ ret = rm_radio_mens_nb_rep(padapter, precv_frame, psta);
+ break;
+
+ default:
+ /* TODO reply incabable */
+ RTW_ERR("RM: unknown specturm management action %2x\n",
+ action_code);
+ break;
+ }
+exit:
+ return ret;
+}
+
+static u8 *rm_gen_bcn_detail_elem(_adapter *padapter, u8 *pframe,
+ struct rm_obj *prm, struct wlan_network *pnetwork,
+ unsigned int *fr_len)
+{
+ WLAN_BSSID_EX *pbss = &pnetwork->network;
+ unsigned int my_len;
+ int j, k, len;
+ u8 *plen;
+ u8 *ptr;
+ u8 val8, eid;
+
+
+ my_len = 0;
+ /* Reporting Detail values
+ * 0: No fixed length fields or elements
+ * 1: All fixed length fields and any requested elements
+ * in the Request info element if present
+ * 2: All fixed length fields and elements
+ * 3-255: Reserved
+ */
+
+ /* report_detail = 0 */
+ if (prm->q.opt.bcn.rep_detail == 0
+ || prm->q.opt.bcn.rep_detail > 2) {
+ return pframe;
+ }
+
+ /* ID */
+ val8 = 1; /* 1:reported frame body */
+ pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+ plen = pframe;
+ val8 = 0;
+ pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+ /* report_detail = 2 */
+ if (prm->q.opt.bcn.rep_detail == 2) {
+ pframe = rtw_set_fixed_ie(pframe, pbss->IELength - 4,
+ pbss->IEs, &my_len); /* -4 remove FCS */
+ goto done;
+ }
+
+ /* report_detail = 1 */
+ /* all fixed lenght fields */
+ pframe = rtw_set_fixed_ie(pframe,
+ _FIXED_IE_LENGTH_, pbss->IEs, &my_len);
+
+ for (j = 0; j < prm->q.opt.bcn.opt_id_num; j++) {
+ switch (prm->q.opt.bcn.opt_id[j]) {
+ case bcn_req_ssid:
+ /* SSID */
+#if (RM_MORE_DBG_MSG)
+ RTW_INFO("RM: bcn_req_ssid\n");
+#endif
+ pframe = rtw_set_ie(pframe, _SSID_IE_,
+ pbss->Ssid.SsidLength,
+ pbss->Ssid.Ssid, &my_len);
+ break;
+ case bcn_req_req:
+ if (prm->q.opt.bcn.req_start == NULL)
+ break;
+#if (RM_MORE_DBG_MSG)
+ RTW_INFO("RM: bcn_req_req");
+#endif
+ for (k=0; kq.opt.bcn.req_len; k++) {
+ eid = prm->q.opt.bcn.req_start[k];
+
+ val8 = pbss->IELength - _FIXED_IE_LENGTH_;
+ ptr = rtw_get_ie(pbss->IEs + _FIXED_IE_LENGTH_,
+ eid, &len, val8);
+
+ if (!ptr)
+ continue;
+#if (RM_MORE_DBG_MSG)
+ switch (eid) {
+ case EID_QBSSLoad:
+ RTW_INFO("RM: EID_QBSSLoad\n");
+ break;
+ case EID_HTCapability:
+ RTW_INFO("RM: EID_HTCapability\n");
+ break;
+ case _MDIE_:
+ RTW_INFO("RM: EID_MobilityDomain\n");
+ break;
+ default:
+ RTW_INFO("RM: EID %d todo\n",eid);
+ break;
+ }
+#endif
+ pframe = rtw_set_ie(pframe, eid,
+ len,ptr+2, &my_len);
+ } /* for() */
+ break;
+ case bcn_req_ac_ch_rep:
+ default:
+ RTW_INFO("RM: OPT %d TODO\n",prm->q.opt.bcn.opt_id[j]);
+ break;
+ }
+ }
+done:
+ /*
+ * update my length
+ * content length does NOT include ID and LEN
+ */
+ val8 = my_len - 2;
+ rtw_set_fixed_ie(plen, 1, &val8, &j);
+
+ /* update length to caller */
+ *fr_len += my_len;
+
+ return pframe;
+}
+
+static u8 rm_get_rcpi(struct rm_obj *prm, struct wlan_network *pnetwork)
+{
+ return translate_percentage_to_rcpi(
+ pnetwork->network.PhyInfo.SignalStrength);
+}
+
+static u8 rm_get_rsni(struct rm_obj *prm, struct wlan_network *pnetwork)
+{
+ int i;
+ u8 val8, snr;
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(prm->psta->padapter);
+
+
+ if (pnetwork->network.PhyInfo.is_cck_rate) {
+ /* current HW doesn't have CCK RSNI */
+ /* 255 indicates RSNI is unavailable */
+ val8 = 255;
+ } else {
+ snr = 0;
+ for (i = 0; i < pHalData->NumTotalRFPath; i++) {
+ snr += pnetwork->network.PhyInfo.rx_snr[i];
+ }
+ snr = snr / pHalData->NumTotalRFPath;
+ val8 = (u8)(snr + 10)*2;
+ }
+ return val8;
+}
+
+u8 rm_bcn_req_cond_mach(struct rm_obj *prm, struct wlan_network *pnetwork)
+{
+ u8 val8;
+
+
+ switch(prm->q.opt.bcn.rep_cond.cond) {
+ case bcn_rep_cond_immediately:
+ return _SUCCESS;
+ case bcn_req_cond_rcpi_greater:
+ val8 = rm_get_rcpi(prm, pnetwork);
+ if (val8 > prm->q.opt.bcn.rep_cond.threshold)
+ return _SUCCESS;
+ break;
+ case bcn_req_cond_rcpi_less:
+ val8 = rm_get_rcpi(prm, pnetwork);
+ if (val8 < prm->q.opt.bcn.rep_cond.threshold)
+ return _SUCCESS;
+ break;
+ case bcn_req_cond_rsni_greater:
+ val8 = rm_get_rsni(prm, pnetwork);
+ if (val8 != 255 && val8 > prm->q.opt.bcn.rep_cond.threshold)
+ return _SUCCESS;
+ break;
+ case bcn_req_cond_rsni_less:
+ val8 = rm_get_rsni(prm, pnetwork);
+ if (val8 != 255 && val8 < prm->q.opt.bcn.rep_cond.threshold)
+ return _SUCCESS;
+ break;
+ default:
+ RTW_ERR("RM: bcn_req cond %u not support\n",
+ prm->q.opt.bcn.rep_cond.cond);
+ break;
+ }
+ return _FALSE;
+}
+
+static u8 *rm_bcn_rep_fill_scan_resule (struct rm_obj *prm,
+ u8 *pframe, struct wlan_network *pnetwork, unsigned int *fr_len)
+{
+ int snr, i;
+ u8 val8, *plen;
+ u16 val16;
+ u32 val32;
+ u64 val64;
+ PWLAN_BSSID_EX pbss;
+ unsigned int my_len;
+ _adapter *padapter = prm->psta->padapter;
+
+
+ my_len = 0;
+ /* meas ID */
+ val8 = EID_MeasureReport;
+ pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+ /* remember position form elelment length */
+ plen = pframe;
+
+ /* meas_rpt_len */
+ /* default 3 = mode + token + type but no beacon content */
+ val8 = 3;
+ pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+ /* meas_token */
+ val8 = prm->q.m_token;
+ pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+ /* meas_rpt_mode F8-141 */
+ val8 = prm->p.m_mode;
+ pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+ /* meas_type T8-81 */
+ val8 = bcn_rep;
+ pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+ if (pnetwork == NULL)
+ goto done;
+
+ pframe = rtw_set_fixed_ie(pframe, 1, &prm->q.op_class, &my_len);
+
+ /* channel */
+ pbss = &pnetwork->network;
+ val8 = pbss->Configuration.DSConfig;
+ pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+ /* Actual Measurement StartTime */
+ val64 = cpu_to_le64(prm->meas_start_time);
+ pframe = rtw_set_fixed_ie(pframe, 8, (u8 *)&val64, &my_len);
+
+ /* Measurement Duration */
+ val16 = prm->meas_end_time - prm->meas_start_time;
+ val16 = cpu_to_le16(val16);
+ pframe = rtw_set_fixed_ie(pframe, 2, (u8 *)&val16, &my_len);
+
+ /* TODO
+ * ReportedFrameInformation:
+ * 0 :beacon or probe rsp
+ * 1 :pilot frame
+ */
+ val8 = 0; /* report frame info */
+ pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+ /* RCPI */
+ val8 = rm_get_rcpi(prm, pnetwork);
+ pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+ /* RSNI */
+ val8 = rm_get_rsni(prm, pnetwork);
+ pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+ /* BSSID */
+ pframe = rtw_set_fixed_ie(pframe, 6, (u8 *)&pbss->MacAddress, &my_len);
+
+ /*
+ * AntennaID
+ * 0: unknown
+ * 255: multiple antenna (Diversity)
+ */
+ val8 = 0;
+ pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+ /* ParentTSF */
+ val32 = prm->meas_start_time + pnetwork->network.PhyInfo.free_cnt;
+ pframe = rtw_set_fixed_ie(pframe, 4, (u8 *)&val32, &my_len);
+
+ /*
+ * Generate Beacon detail
+ */
+ pframe = rm_gen_bcn_detail_elem(padapter, pframe,
+ prm, pnetwork, &my_len);
+done:
+ /*
+ * update my length
+ * content length does NOT include ID and LEN
+ */
+ val8 = my_len - 2;
+ rtw_set_fixed_ie(plen, 1, &val8, &i);
+
+ /* update length to caller */
+ *fr_len += my_len;
+
+ return pframe;
+}
+
+static u8 *rm_gen_bcn_rep_ie (struct rm_obj *prm,
+ u8 *pframe, struct wlan_network *pnetwork, unsigned int *fr_len)
+{
+ int snr, i;
+ u8 val8, *plen;
+ u16 val16;
+ u32 val32;
+ u64 val64;
+ unsigned int my_len;
+ _adapter *padapter = prm->psta->padapter;
+
+
+ my_len = 0;
+ plen = pframe + 1;
+ pframe = rtw_set_fixed_ie(pframe, 7, &prm->p.e_id, &my_len);
+
+ /* Actual Measurement StartTime */
+ val64 = cpu_to_le64(prm->meas_start_time);
+ pframe = rtw_set_fixed_ie(pframe, 8, (u8 *)&val64, &my_len);
+
+ /* Measurement Duration */
+ val16 = prm->meas_end_time - prm->meas_start_time;
+ val16 = cpu_to_le16(val16);
+ pframe = rtw_set_fixed_ie(pframe, 2, (u8*)&val16, &my_len);
+
+ /* TODO
+ * ReportedFrameInformation:
+ * 0 :beacon or probe rsp
+ * 1 :pilot frame
+ */
+ val8 = 0; /* report frame info */
+ pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+ /* RCPI */
+ val8 = rm_get_rcpi(prm, pnetwork);
+ pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+ /* RSNI */
+ val8 = rm_get_rsni(prm, pnetwork);
+ pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+ /* BSSID */
+ pframe = rtw_set_fixed_ie(pframe, 6,
+ (u8 *)&pnetwork->network.MacAddress, &my_len);
+
+ /*
+ * AntennaID
+ * 0: unknown
+ * 255: multiple antenna (Diversity)
+ */
+ val8 = 0;
+ pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+ /* ParentTSF */
+ val32 = prm->meas_start_time + pnetwork->network.PhyInfo.free_cnt;
+ pframe = rtw_set_fixed_ie(pframe, 4, (u8 *)&val32, &my_len);
+
+ /* Generate Beacon detail */
+ pframe = rm_gen_bcn_detail_elem(padapter, pframe,
+ prm, pnetwork, &my_len);
+done:
+ /*
+ * update my length
+ * content length does NOT include ID and LEN
+ */
+ val8 = my_len - 2;
+ rtw_set_fixed_ie(plen, 1, &val8, &i);
+
+ /* update length to caller */
+ *fr_len += my_len;
+
+ return pframe;
+}
+
+static int retrieve_scan_result(struct rm_obj *prm)
+{
+ _irqL irqL;
+ _list *plist, *phead;
+ _queue *queue;
+ _adapter *padapter = prm->psta->padapter;
+ struct rtw_ieee80211_channel *pch_set;
+ struct wlan_network *pnetwork = NULL;
+ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+ int i, meas_ch_num=0;
+ PWLAN_BSSID_EX pbss;
+ unsigned int matched_network;
+ int len, my_len;
+ u8 buf_idx, *pbuf = NULL, *tmp_buf = NULL;
+
+
+ tmp_buf = rtw_malloc(MAX_XMIT_EXTBUF_SZ);
+ if (tmp_buf == NULL)
+ return 0;
+
+ my_len = 0;
+ buf_idx = 0;
+ matched_network = 0;
+ queue = &(pmlmepriv->scanned_queue);
+
+ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+
+ phead = get_list_head(queue);
+ plist = get_next(phead);
+
+ /* get requested measurement channel set */
+ pch_set = prm->q.ch_set;
+ meas_ch_num = prm->q.ch_set_ch_amount;
+
+ /* search scan queue to find requested SSID */
+ while (1) {
+
+ if (rtw_end_of_queue_search(phead, plist) == _TRUE)
+ break;
+
+ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
+ pbss = &pnetwork->network;
+
+ /*
+ * report network if requested channel set contains
+ * the channel matchs selected network
+ */
+ if (rtw_chset_search_ch(adapter_to_chset(padapter),
+ pbss->Configuration.DSConfig) == 0)
+ goto next;
+
+ if (rtw_mlme_band_check(padapter, pbss->Configuration.DSConfig)
+ == _FALSE)
+ goto next;
+
+ if (rtw_validate_ssid(&(pbss->Ssid)) == _FALSE)
+ goto next;
+
+ /* go through measurement requested channels */
+ for (i = 0; i < meas_ch_num; i++) {
+
+ /* match channel */
+ if (pch_set[i].hw_value != pbss->Configuration.DSConfig)
+ continue;
+
+ /* match bssid */
+ if (is_wildcard_bssid(prm->q.bssid) == FALSE)
+ if (_rtw_memcmp(prm->q.bssid,
+ pbss->MacAddress, 6) == _FALSE) {
+ continue;
+ }
+ /*
+ * default wildcard SSID. wildcard SSID:
+ * A SSID value (null) used to represent all SSIDs
+ */
+
+ /* match ssid */
+ if ((prm->q.opt.bcn.ssid.SsidLength > 0) &&
+ _rtw_memcmp(prm->q.opt.bcn.ssid.Ssid,
+ pbss->Ssid.Ssid,
+ prm->q.opt.bcn.ssid.SsidLength) == _FALSE)
+ continue;
+
+ /* match condition */
+ if (rm_bcn_req_cond_mach(prm, pnetwork) == _FALSE) {
+ RTW_INFO("RM: condition mismatch ch %u ssid %s bssid "MAC_FMT"\n",
+ pch_set[i].hw_value, pbss->Ssid.Ssid,
+ MAC_ARG(pbss->MacAddress));
+ RTW_INFO("RM: condition %u:%u\n",
+ prm->q.opt.bcn.rep_cond.cond,
+ prm->q.opt.bcn.rep_cond.threshold);
+ continue;
+ }
+
+ /* Found a matched SSID */
+ matched_network++;
+
+ RTW_INFO("RM: ch %u Found %s bssid "MAC_FMT"\n",
+ pch_set[i].hw_value, pbss->Ssid.Ssid,
+ MAC_ARG(pbss->MacAddress));
+
+ len = 0;
+ _rtw_memset(tmp_buf, 0, MAX_XMIT_EXTBUF_SZ);
+ rm_gen_bcn_rep_ie(prm, tmp_buf, pnetwork, &len);
+new_packet:
+ if (my_len == 0) {
+ pbuf = rtw_malloc(MAX_XMIT_EXTBUF_SZ);
+ if (pbuf == NULL)
+ goto fail;
+ prm->buf[buf_idx].pbuf = pbuf;
+ }
+
+ if ((MAX_XMIT_EXTBUF_SZ - (my_len+len+24+4)) > 0) {
+ pbuf = rtw_set_fixed_ie(pbuf,
+ len, tmp_buf, &my_len);
+ prm->buf[buf_idx].len = my_len;
+ } else {
+ if (my_len == 0) /* not enough space */
+ goto fail;
+
+ my_len = 0;
+ buf_idx++;
+ goto new_packet;
+ }
+ } /* for() */
+next:
+ plist = get_next(plist);
+ } /* while() */
+fail:
+ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+
+ if (tmp_buf)
+ rtw_mfree(tmp_buf, MAX_XMIT_EXTBUF_SZ);
+
+ RTW_INFO("RM: Found %d matched %s\n", matched_network,
+ prm->q.opt.bcn.ssid.Ssid);
+
+ if (prm->buf[buf_idx].pbuf)
+ return buf_idx+1;
+
+ return 0;
+}
+
+int issue_beacon_rep(struct rm_obj *prm)
+{
+ int i, my_len;
+ u8 *pframe;
+ _adapter *padapter = prm->psta->padapter;
+ struct pkt_attrib *pattr;
+ struct xmit_frame *pmgntframe;
+ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
+ int pkt_num;
+
+
+ pkt_num = retrieve_scan_result(prm);
+
+ if (pkt_num == 0) {
+ issue_null_reply(prm);
+ return _SUCCESS;
+ }
+
+ for (i=0;iattrib;
+ pframe = build_wlan_hdr(padapter,
+ pmgntframe, prm->psta, WIFI_ACTION);
+ pframe = rtw_set_fixed_ie(pframe,
+ 3, &prm->p.category, &pattr->pktlen);
+
+ my_len = 0;
+ pframe = rtw_set_fixed_ie(pframe,
+ prm->buf[i].len, prm->buf[i].pbuf, &my_len);
+
+ pattr->pktlen += my_len;
+ pattr->last_txcmdsz = pattr->pktlen;
+ dump_mgntframe(padapter, pmgntframe);
+ }
+fail:
+ for (i=0;ibuf[i].pbuf) {
+ rtw_mfree(prm->buf[i].pbuf, MAX_XMIT_EXTBUF_SZ);
+ prm->buf[i].pbuf = NULL;
+ prm->buf[i].len = 0;
+ }
+ }
+ return _SUCCESS;
+}
+
+/* neighbor request */
+int issue_nb_req(struct rm_obj *prm)
+{
+ _adapter *padapter = prm->psta->padapter;
+ struct sta_info *psta = prm->psta;
+ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+ struct xmit_frame *pmgntframe = NULL;
+ struct pkt_attrib *pattr = NULL;
+ u8 val8;
+ u8 *pframe = NULL;
+
+
+ RTW_INFO("RM: %s\n", __func__);
+
+ pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+ if (pmgntframe == NULL) {
+ RTW_ERR("RM: %s alloc xmit_frame fail\n",__func__);
+ return _FALSE;
+ }
+ pattr = &pmgntframe->attrib;
+ pframe = build_wlan_hdr(padapter, pmgntframe, psta, WIFI_ACTION);
+ pframe = rtw_set_fixed_ie(pframe,
+ 3, &prm->q.category, &pattr->pktlen);
+
+ if (prm->q.pssid) {
+
+ u8 sub_ie[64] = {0};
+ u8 *pie = &sub_ie[2];
+
+ RTW_INFO("RM: Send NB Req to "MAC_FMT" for(SSID) %s searching\n",
+ MAC_ARG(pmlmepriv->cur_network.network.MacAddress),
+ pmlmepriv->cur_network.network.Ssid.Ssid);
+
+ val8 = strlen(prm->q.pssid);
+ sub_ie[0] = 0; /*SSID*/
+ sub_ie[1] = val8;
+
+ _rtw_memcpy(pie, prm->q.pssid, val8);
+
+ pframe = rtw_set_fixed_ie(pframe, val8 + 2,
+ sub_ie, &pattr->pktlen);
+ } else {
+
+ if (!pmlmepriv->cur_network.network.Ssid.SsidLength)
+ RTW_INFO("RM: Send NB Req to "MAC_FMT"\n",
+ MAC_ARG(pmlmepriv->cur_network.network.MacAddress));
+ else {
+ u8 sub_ie[64] = {0};
+ u8 *pie = &sub_ie[2];
+
+ RTW_INFO("RM: Send NB Req to "MAC_FMT" for(SSID) %s searching\n",
+ MAC_ARG(pmlmepriv->cur_network.network.MacAddress),
+ pmlmepriv->cur_network.network.Ssid.Ssid);
+
+ sub_ie[0] = 0; /*SSID*/
+ sub_ie[1] = pmlmepriv->cur_network.network.Ssid.SsidLength;
+
+ _rtw_memcpy(pie, pmlmepriv->cur_network.network.Ssid.Ssid,
+ pmlmepriv->cur_network.network.Ssid.SsidLength);
+
+ pframe = rtw_set_fixed_ie(pframe,
+ pmlmepriv->cur_network.network.Ssid.SsidLength + 2,
+ sub_ie, &pattr->pktlen);
+ }
+ }
+
+ pattr->last_txcmdsz = pattr->pktlen;
+ dump_mgntframe(padapter, pmgntframe);
+
+ return _SUCCESS;
+}
+
+static u8 *rm_gen_bcn_req_s_elem(_adapter *padapter,
+ u8 *pframe, unsigned int *fr_len)
+{
+ u8 val8;
+ unsigned int my_len = 0;
+ u8 bssid[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+
+
+ val8 = bcn_req_active; /* measurement mode T8-64 */
+ pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+ pframe = rtw_set_fixed_ie(pframe, 6, bssid, &my_len);
+
+ /* update length to caller */
+ *fr_len += my_len;
+
+ /* optional subelements */
+ return pframe;
+}
+
+static u8 *rm_gen_ch_load_req_s_elem(_adapter *padapter,
+ u8 *pframe, unsigned int *fr_len)
+{
+ u8 val8;
+ unsigned int my_len = 0;
+
+
+ val8 = 1; /* 1: channel load T8-60 */
+ pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+ val8 = 2; /* channel load length = 2 (extensible) */
+ pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+ val8 = 0; /* channel load condition : 0 (issue when meas done) T8-61 */
+ pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+ val8 = 0; /* channel load reference value : 0 */
+ pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+ /* update length to caller */
+ *fr_len += my_len;
+
+ return pframe;
+}
+
+static u8 *rm_gen_noise_histo_req_s_elem(_adapter *padapter,
+ u8 *pframe, unsigned int *fr_len)
+{
+ u8 val8;
+ unsigned int my_len = 0;
+
+
+ val8 = 1; /* 1: noise histogram T8-62 */
+ pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+ val8 = 2; /* noise histogram length = 2 (extensible) */
+ pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+ val8 = 0; /* noise histogram condition : 0 (issue when meas done) T8-63 */
+ pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+ val8 = 0; /* noise histogram reference value : 0 */
+ pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+
+ /* update length to caller */
+ *fr_len += my_len;
+
+ return pframe;
+}
+
+int issue_radio_meas_req(struct rm_obj *prm)
+{
+ u8 val8;
+ u8 *pframe;
+ u8 *plen;
+ u16 val16;
+ int my_len, i;
+ struct xmit_frame *pmgntframe;
+ struct pkt_attrib *pattr;
+ _adapter *padapter = prm->psta->padapter;
+ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+
+
+ RTW_INFO("RM: %s - %s\n", __func__, rm_type_req_name(prm->q.m_type));
+
+ pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+ if (pmgntframe == NULL) {
+ RTW_ERR("RM: %s alloc xmit_frame fail\n",__func__);
+ return _FALSE;
+ }
+ pattr = &pmgntframe->attrib;
+ pframe = build_wlan_hdr(padapter, pmgntframe, prm->psta, WIFI_ACTION);
+ pframe = rtw_set_fixed_ie(pframe, 3, &prm->q.category, &pattr->pktlen);
+
+ /* repeat */
+ val16 = cpu_to_le16(prm->q.rpt);
+ pframe = rtw_set_fixed_ie(pframe, 2,
+ (unsigned char *)&(val16), &pattr->pktlen);
+
+ my_len = 0;
+ plen = pframe + 1;
+ pframe = rtw_set_fixed_ie(pframe, 7, &prm->q.e_id, &my_len);
+
+ /* random interval */
+ val16 = 100; /* 100 TU */
+ val16 = cpu_to_le16(val16);
+ pframe = rtw_set_fixed_ie(pframe, 2, (u8 *)&val16, &my_len);
+
+ /* measurement duration */
+ val16 = 100;
+ val16 = cpu_to_le16(val16);
+ pframe = rtw_set_fixed_ie(pframe, 2, (u8 *)&val16, &my_len);
+
+ /* optional subelement */
+ switch (prm->q.m_type) {
+ case bcn_req:
+ pframe = rm_gen_bcn_req_s_elem(padapter, pframe, &my_len);
+ break;
+ case ch_load_req:
+ pframe = rm_gen_ch_load_req_s_elem(padapter, pframe, &my_len);
+ break;
+ case noise_histo_req:
+ pframe = rm_gen_noise_histo_req_s_elem(padapter,
+ pframe, &my_len);
+ break;
+ case basic_req:
+ default:
+ break;
+ }
+
+ /* length */
+ val8 = (u8)my_len - 2;
+ rtw_set_fixed_ie(plen, 1, &val8, &i);
+
+ pattr->pktlen += my_len;
+
+ pattr->last_txcmdsz = pattr->pktlen;
+ dump_mgntframe(padapter, pmgntframe);
+
+ return _SUCCESS;
+}
+
+/* noise histogram */
+static u8 rm_get_anpi(struct rm_obj *prm, struct wlan_network *pnetwork)
+{
+ return translate_percentage_to_rcpi(
+ pnetwork->network.PhyInfo.SignalStrength);
+}
+
+int rm_radio_meas_report_cond(struct rm_obj *prm)
+{
+ u8 val8;
+ int i;
+
+
+ switch (prm->q.m_type) {
+ case ch_load_req:
+
+ val8 = prm->p.ch_load;
+ switch (prm->q.opt.clm.rep_cond.cond) {
+ case ch_load_cond_immediately:
+ return _SUCCESS;
+ case ch_load_cond_anpi_equal_greater:
+ if (val8 >= prm->q.opt.clm.rep_cond.threshold)
+ return _SUCCESS;
+ case ch_load_cond_anpi_equal_less:
+ if (val8 <= prm->q.opt.clm.rep_cond.threshold)
+ return _SUCCESS;
+ default:
+ break;
+ }
+ break;
+ case noise_histo_req:
+ val8 = prm->p.anpi;
+ switch (prm->q.opt.nhm.rep_cond.cond) {
+ case noise_histo_cond_immediately:
+ return _SUCCESS;
+ case noise_histo_cond_anpi_equal_greater:
+ if (val8 >= prm->q.opt.nhm.rep_cond.threshold)
+ return _SUCCESS;
+ break;
+ case noise_histo_cond_anpi_equal_less:
+ if (val8 <= prm->q.opt.nhm.rep_cond.threshold)
+ return _SUCCESS;
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+ return _FAIL;
+}
+
+int retrieve_radio_meas_result(struct rm_obj *prm)
+{
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(prm->psta->padapter);
+ int i, ch = -1;
+ u8 val8;
+
+
+ ch = rtw_chset_search_ch(adapter_to_chset(prm->psta->padapter),
+ prm->q.ch_num);
+
+ if ((ch == -1) || (ch >= MAX_CHANNEL_NUM)) {
+ RTW_ERR("RM: get ch(CH:%d) fail\n", prm->q.ch_num);
+ ch = 0;
+ }
+
+ switch (prm->q.m_type) {
+ case ch_load_req:
+#ifdef CONFIG_RTW_ACS
+ val8 = hal_data->acs.clm_ratio[ch];
+#else
+ val8 = 0;
+#endif
+ prm->p.ch_load = val8;
+ break;
+ case noise_histo_req:
+#ifdef CONFIG_RTW_ACS
+ /* ANPI */
+ prm->p.anpi = hal_data->acs.nhm_ratio[ch];
+
+ /* IPI 0~10 */
+ for (i=0;i<11;i++)
+ prm->p.ipi[i] = hal_data->acs.nhm[ch][i];
+
+#else
+ val8 = 0;
+ prm->p.anpi = val8;
+ for (i=0;i<11;i++)
+ prm->p.ipi[i] = val8;
+#endif
+ break;
+ default:
+ break;
+ }
+ return _SUCCESS;
+}
+
+int issue_radio_meas_rep(struct rm_obj *prm)
+{
+ u8 val8;
+ u8 *pframe;
+ u8 *plen;
+ u16 val16;
+ u64 val64;
+ unsigned int my_len;
+ _adapter *padapter = prm->psta->padapter;
+ struct xmit_frame *pmgntframe;
+ struct pkt_attrib *pattr;
+ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
+ struct sta_info *psta = prm->psta;
+ int i;
+
+
+ RTW_INFO("RM: %s\n", __func__);
+
+ pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+ if (pmgntframe == NULL) {
+ RTW_ERR("RM: ERR %s alloc xmit_frame fail\n",__func__);
+ return _FALSE;
+ }
+ pattr = &pmgntframe->attrib;
+ pframe = build_wlan_hdr(padapter, pmgntframe, psta, WIFI_ACTION);
+ pframe = rtw_set_fixed_ie(pframe, 3,
+ &prm->p.category, &pattr->pktlen);
+
+ my_len = 0;
+ plen = pframe + 1;
+ pframe = rtw_set_fixed_ie(pframe, 7, &prm->p.e_id, &my_len);
+
+ /* Actual Meas start time - 8 bytes */
+ val64 = cpu_to_le64(prm->meas_start_time);
+ pframe = rtw_set_fixed_ie(pframe, 8, (u8 *)&val64, &my_len);
+
+ /* measurement duration */
+ val16 = prm->meas_end_time - prm->meas_start_time;
+ val16 = cpu_to_le16(val16);
+ pframe = rtw_set_fixed_ie(pframe, 2, (u8 *)&val16, &my_len);
+
+ /* optional subelement */
+ switch (prm->q.m_type) {
+ case ch_load_req:
+ val8 = prm->p.ch_load;
+ pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+ break;
+ case noise_histo_req:
+ /*
+ * AntennaID
+ * 0: unknown
+ * 255: multiple antenna (Diversity)
+ */
+ val8 = 0;
+ pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+ /* ANPI */
+ val8 = prm->p.anpi;
+ pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+ /* IPI 0~10 */
+ for (i=0;i<11;i++) {
+ val8 = prm->p.ipi[i];
+ pframe = rtw_set_fixed_ie(pframe, 1, &val8, &my_len);
+ }
+ break;
+ default:
+ break;
+ }
+done:
+ /* length */
+ val8 = (u8)my_len-2;
+ rtw_set_fixed_ie(plen, 1, &val8, &i); /* use variable i to ignore it */
+
+ pattr->pktlen += my_len;
+ pattr->last_txcmdsz = pattr->pktlen;
+ dump_mgntframe(padapter, pmgntframe);
+
+ return _SUCCESS;
+}
+
+void rtw_ap_parse_sta_rm_en_cap(_adapter *padapter,
+ struct sta_info *psta, struct rtw_ieee802_11_elems *elem)
+{
+ if (elem->rm_en_cap) {
+ RTW_INFO("assoc.rm_en_cap="RM_CAP_FMT"\n",
+ RM_CAP_ARG(elem->rm_en_cap));
+ _rtw_memcpy(psta->rm_en_cap,
+ (elem->rm_en_cap), elem->rm_en_cap_len);
+ }
+}
+
+void RM_IE_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
+{
+ int i;
+
+ _rtw_memcpy(&padapter->rmpriv.rm_en_cap_assoc, pIE->data, pIE->Length);
+ RTW_INFO("assoc.rm_en_cap="RM_CAP_FMT"\n", RM_CAP_ARG(pIE->data));
+}
+
+/* Debug command */
+
+#if (RM_SUPPORT_IWPRIV_DBG)
+static int hex2num(char c)
+{
+ if (c >= '0' && c <= '9')
+ return c - '0';
+ if (c >= 'a' && c <= 'f')
+ return c - 'a' + 10;
+ if (c >= 'A' && c <= 'F')
+ return c - 'A' + 10;
+ return -1;
+}
+
+int hex2byte(const char *hex)
+{
+ int a, b;
+ a = hex2num(*hex++);
+ if (a < 0)
+ return -1;
+ b = hex2num(*hex++);
+ if (b < 0)
+ return -1;
+ return (a << 4) | b;
+}
+
+static char * hwaddr_parse(char *txt, u8 *addr)
+{
+ size_t i;
+
+ for (i = 0; i < ETH_ALEN; i++) {
+ int a;
+
+ a = hex2byte(txt);
+ if (a < 0)
+ return NULL;
+ txt += 2;
+ addr[i] = a;
+ if (i < ETH_ALEN - 1 && *txt++ != ':')
+ return NULL;
+ }
+ return txt;
+}
+
+void rm_dbg_list_sta(_adapter *padapter, char *s)
+{
+ int i;
+ _irqL irqL;
+ struct sta_info *psta;
+ struct sta_priv *pstapriv = &padapter->stapriv;
+ _list *plist, *phead;
+
+
+ sprintf(pstr(s), "\n");
+ _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+ for (i = 0; i < NUM_STA; i++) {
+ phead = &(pstapriv->sta_hash[i]);
+ plist = get_next(phead);
+
+ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+ psta = LIST_CONTAINOR(plist,
+ struct sta_info, hash_list);
+
+ plist = get_next(plist);
+
+ sprintf(pstr(s), "=========================================\n");
+ sprintf(pstr(s), "mac=" MAC_FMT "\n",
+ MAC_ARG(psta->cmn.mac_addr));
+ sprintf(pstr(s), "state=0x%x, aid=%d, macid=%d\n",
+ psta->state, psta->cmn.aid, psta->cmn.mac_id);
+ sprintf(pstr(s), "rm_cap="RM_CAP_FMT"\n",
+ RM_CAP_ARG(psta->rm_en_cap));
+ }
+
+ }
+ _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+ sprintf(pstr(s), "=========================================\n");
+}
+
+void rm_dbg_help(_adapter *padapter, char *s)
+{
+ int i;
+
+
+ sprintf(pstr(s), "\n");
+ sprintf(pstr(s), "rrm list_sta\n");
+ sprintf(pstr(s), "rrm list_meas\n");
+
+ sprintf(pstr(s), "rrm add_meas ,m=,rpt=\n");
+ sprintf(pstr(s), "rrm run_meas \n");
+ sprintf(pstr(s), "rrm del_meas\n");
+
+ sprintf(pstr(s), "rrm run_meas rmid=xxxx,ev=xx\n");
+ sprintf(pstr(s), "rrm activate\n");
+
+ for (i=0;istapriv;
+ _list *plist, *phead;
+
+
+ _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+
+ for (i = 0; i < NUM_STA; i++) {
+ phead = &(pstapriv->sta_hash[i]);
+ plist = get_next(phead);
+
+ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+ psta = LIST_CONTAINOR(plist,
+ struct sta_info, hash_list);
+
+ plist = get_next(plist);
+
+ if (psta->cmn.aid == aid)
+ goto done;
+
+ if (pbssid && _rtw_memcmp(psta->cmn.mac_addr,
+ pbssid, 6))
+ goto done;
+ }
+
+ }
+ psta = NULL;
+done:
+ _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+ return psta;
+}
+
+static int rm_dbg_modify_meas(_adapter *padapter, char *s)
+{
+ struct rm_priv *prmpriv = &padapter->rmpriv;
+ struct mlme_ext_info *pmlmeinfo = &padapter->mlmeextpriv.mlmext_info;
+ struct rm_obj *prm;
+ struct sta_info *psta;
+ char *pmac, *ptr, *paid, *prpt, *pnbp, *pclm, *pnhm, *pbcn;
+ unsigned val;
+ u8 bssid[ETH_ALEN];
+
+
+ /* example :
+ * rrm add_meas ,m=,
+ * rrm run_meas
+ */
+ paid = strstr(s, "aid=");
+ pmac = strstr(s, "mac=");
+ pbcn = strstr(s, "m=bcn");
+ pclm = strstr(s, "m=clm");
+ pnhm = strstr(s, "m=nhm");
+ pnbp = strstr(s, "m=nb");
+ prpt = strstr(s, "rpt=");
+
+ /* set all ',' to NULL (end of line) */
+ ptr = s;
+ while (ptr) {
+ ptr = strchr(ptr, ',');
+ if (ptr) {
+ *(ptr) = 0x0;
+ ptr++;
+ }
+ }
+ prm = (struct rm_obj *)prmpriv->prm_sel;
+ prm->q.m_token = 1;
+ psta = prm->psta;
+
+ if (paid) { /* find sta_info according to aid */
+ paid += 4; /* skip aid= */
+ sscanf(paid, "%u", &val); /* aid=x */
+ psta = rm_get_sta(padapter, val, NULL);
+
+ } else if (pmac) { /* find sta_info according to bssid */
+ pmac += 4; /* skip mac= */
+ if (hwaddr_parse(pmac, bssid) == NULL) {
+ sprintf(pstr(s), "Err: \nincorrect mac format\n");
+ return _FAIL;
+ }
+ psta = rm_get_sta(padapter, 0xff, bssid);
+ }
+
+ if (psta) {
+ prm->psta = psta;
+
+#if 0
+ prm->q.diag_token = psta->rm_diag_token++;
+#else
+ /* TODO dialog should base on sta_info */
+ prm->q.diag_token = pmlmeinfo->dialogToken++;
+#endif
+ prm->rmid = psta->cmn.aid << 16
+ | prm->q.diag_token << 8
+ | RM_MASTER;
+ } else
+ return _FAIL;
+
+ prm->q.action_code = RM_ACT_RADIO_MEAS_REQ;
+ if (pbcn) {
+ prm->q.m_type = bcn_req;
+ } else if (pnhm) {
+ prm->q.m_type = noise_histo_req;
+ } else if (pclm) {
+ prm->q.m_type = ch_load_req;
+ } else if (pnbp) {
+ prm->q.action_code = RM_ACT_NB_REP_REQ;
+ } else
+ return _FAIL;
+
+ if (prpt) {
+ prpt += 4; /* skip rpt= */
+ sscanf(prpt, "%u", &val);
+ prm->q.rpt = (u8)val;
+ }
+
+ return _SUCCESS;
+}
+
+static void rm_dbg_activate_meas(_adapter *padapter, char *s)
+{
+ struct rm_priv *prmpriv = &(padapter->rmpriv);
+ struct rm_obj *prm;
+
+
+ if (prmpriv->prm_sel == NULL) {
+ sprintf(pstr(s), "\nErr: No inActivate measurement\n");
+ return;
+ }
+ prm = (struct rm_obj *)prmpriv->prm_sel;
+
+ /* verify attributes */
+ if (prm->psta == NULL) {
+ sprintf(pstr(s), "\nErr: inActivate meas has no psta\n");
+ return;
+ }
+
+ /* measure current channel */
+ prm->q.ch_num = padapter->mlmeextpriv.cur_channel;
+ prm->q.op_class = rm_get_oper_class_via_ch(prm->q.ch_num);
+
+ /* enquee rmobj */
+ rm_enqueue_rmobj(padapter, prm, _FALSE);
+
+ sprintf(pstr(s), "\nActivate rmid=%x, state=%s, meas_type=%s\n",
+ prm->rmid, rm_state_name(prm->state),
+ rm_type_req_name(prm->q.m_type));
+
+ sprintf(pstr(s), "aid=%d, mac=" MAC_FMT "\n",
+ prm->psta->cmn.aid, MAC_ARG(prm->psta->cmn.mac_addr));
+
+ /* clearn inActivate prm info */
+ prmpriv->prm_sel = NULL;
+}
+
+static void rm_dbg_add_meas(_adapter *padapter, char *s)
+{
+ struct rm_priv *prmpriv = &(padapter->rmpriv);
+ struct rm_obj *prm;
+ char *pact;
+
+
+ /* example :
+ * rrm add_meas ,m=
+ * rrm run_meas
+ */
+ prm = (struct rm_obj *)prmpriv->prm_sel;
+ if (prm == NULL)
+ prm = rm_alloc_rmobj(padapter);
+
+ if (prm == NULL) {
+ sprintf(pstr(s), "\nErr: alloc meas fail\n");
+ return;
+ }
+
+ prmpriv->prm_sel = prm;
+
+ pact = strstr(s, "act");
+ if (rm_dbg_modify_meas(padapter, s) == _FAIL) {
+
+ sprintf(pstr(s), "\nErr: add meas fail\n");
+ rm_free_rmobj(prm);
+ prmpriv->prm_sel = NULL;
+ return;
+ }
+ prm->q.category = RTW_WLAN_CATEGORY_RADIO_MEAS;
+ prm->q.e_id = _MEAS_REQ_IE_; /* 38 */
+
+ if (prm->q.action_code == RM_ACT_RADIO_MEAS_REQ)
+ sprintf(pstr(s), "\nAdd rmid=%x, meas_type=%s ok\n",
+ prm->rmid, rm_type_req_name(prm->q.m_type));
+ else if (prm->q.action_code == RM_ACT_NB_REP_REQ)
+ sprintf(pstr(s), "\nAdd rmid=%x, meas_type=bcn_req ok\n",
+ prm->rmid);
+
+ if (prm->psta)
+ sprintf(pstr(s), "mac="MAC_FMT"\n",
+ MAC_ARG(prm->psta->cmn.mac_addr));
+
+ if (pact)
+ rm_dbg_activate_meas(padapter, pstr(s));
+}
+
+static void rm_dbg_del_meas(_adapter *padapter, char *s)
+{
+ struct rm_priv *prmpriv = &padapter->rmpriv;
+ struct rm_obj *prm = (struct rm_obj *)prmpriv->prm_sel;
+
+
+ if (prm) {
+ sprintf(pstr(s), "\ndelete rmid=%x\n",prm->rmid);
+
+ /* free inActivate meas - enqueue yet */
+ prmpriv->prm_sel = NULL;
+ rtw_mfree(prmpriv->prm_sel, sizeof(struct rm_obj));
+ } else
+ sprintf(pstr(s), "Err: no inActivate measurement\n");
+}
+
+static void rm_dbg_run_meas(_adapter *padapter, char *s)
+{
+ struct rm_obj *prm;
+ char *pevid, *prmid;
+ u32 rmid, evid;
+
+
+ prmid = strstr(s, "rmid="); /* hex */
+ pevid = strstr(s, "evid="); /* dec */
+
+ if (prmid && pevid) {
+ prmid += 5; /* rmid= */
+ sscanf(prmid, "%x", &rmid);
+
+ pevid += 5; /* evid= */
+ sscanf(pevid, "%u", &evid);
+ } else {
+ sprintf(pstr(s), "\nErr: incorrect attribute\n");
+ return;
+ }
+
+ prm = rm_get_rmobj(padapter, rmid);
+
+ if (!prm) {
+ sprintf(pstr(s), "\nErr: measurement not found\n");
+ return;
+ }
+
+ if (evid >= RM_EV_max) {
+ sprintf(pstr(s), "\nErr: wrong event id\n");
+ return;
+ }
+
+ rm_post_event(padapter, prm->rmid, evid);
+ sprintf(pstr(s), "\npost %s to rmid=%x\n",rm_event_name(evid), rmid);
+}
+
+static void rm_dbg_show_meas(struct rm_obj *prm, char *s)
+{
+ struct sta_info *psta;
+
+ psta = prm->psta;
+
+ if (prm->q.action_code == RM_ACT_RADIO_MEAS_REQ) {
+
+ sprintf(pstr(s), "\nrmid=%x, meas_type=%s\n",
+ prm->rmid, rm_type_req_name(prm->q.m_type));
+
+ } else if (prm->q.action_code == RM_ACT_NB_REP_REQ) {
+
+ sprintf(pstr(s), "\nrmid=%x, action=neighbor_req\n",
+ prm->rmid);
+ } else
+ sprintf(pstr(s), "\nrmid=%x, action=unknown\n",
+ prm->rmid);
+
+ if (psta)
+ sprintf(pstr(s), "aid=%d, mac="MAC_FMT"\n",
+ psta->cmn.aid, MAC_ARG(psta->cmn.mac_addr));
+
+ sprintf(pstr(s), "clock=%d, state=%s, rpt=%u/%u\n",
+ (int)ATOMIC_READ(&prm->pclock->counter),
+ rm_state_name(prm->state), prm->p.rpt, prm->q.rpt);
+}
+
+static void rm_dbg_list_meas(_adapter *padapter, char *s)
+{
+ int meas_amount;
+ _irqL irqL;
+ struct rm_obj *prm;
+ struct sta_info *psta;
+ struct rm_priv *prmpriv = &padapter->rmpriv;
+ _queue *queue = &prmpriv->rm_queue;
+ _list *plist, *phead;
+
+
+ sprintf(pstr(s), "\n");
+ _enter_critical(&queue->lock, &irqL);
+ phead = get_list_head(queue);
+ plist = get_next(phead);
+ meas_amount = 0;
+
+ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+ prm = LIST_CONTAINOR(plist, struct rm_obj, list);
+ meas_amount++;
+ plist = get_next(plist);
+ psta = prm->psta;
+ sprintf(pstr(s), "=========================================\n");
+
+ rm_dbg_show_meas(prm, s);
+ }
+ _exit_critical(&queue->lock, &irqL);
+
+ sprintf(pstr(s), "=========================================\n");
+
+ if (meas_amount==0) {
+ sprintf(pstr(s), "No Activate measurement\n");
+ sprintf(pstr(s), "=========================================\n");
+ }
+
+ if (prmpriv->prm_sel == NULL)
+ sprintf(pstr(s), "\nNo inActivate measurement\n");
+ else {
+ sprintf(pstr(s), "\ninActivate measurement\n");
+ rm_dbg_show_meas((struct rm_obj *)prmpriv->prm_sel, s);
+ }
+}
+#endif /* RM_SUPPORT_IWPRIV_DBG */
+
+void rm_dbg_cmd(_adapter *padapter, char *s)
+{
+ unsigned val;
+ char *paid;
+ struct sta_info *psta=NULL;
+
+#if (RM_SUPPORT_IWPRIV_DBG)
+ if (_rtw_memcmp(s, "help", 4)) {
+ rm_dbg_help(padapter, s);
+
+ } else if (_rtw_memcmp(s, "list_sta", 8)) {
+ rm_dbg_list_sta(padapter, s);
+
+ } else if (_rtw_memcmp(s, "list_meas", 9)) {
+ rm_dbg_list_meas(padapter, s);
+
+ } else if (_rtw_memcmp(s, "add_meas", 8)) {
+ rm_dbg_add_meas(padapter, s);
+
+ } else if (_rtw_memcmp(s, "del_meas", 8)) {
+ rm_dbg_del_meas(padapter, s);
+
+ } else if (_rtw_memcmp(s, "activate", 8)) {
+ rm_dbg_activate_meas(padapter, s);
+
+ } else if (_rtw_memcmp(s, "run_meas", 8)) {
+ rm_dbg_run_meas(padapter, s);
+ } else if (_rtw_memcmp(s, "nb", 2)) {
+
+ paid = strstr(s, "aid=");
+
+ if (paid) { /* find sta_info according to aid */
+ paid += 4; /* skip aid= */
+ sscanf(paid, "%u", &val); /* aid=x */
+ psta = rm_get_sta(padapter, val, NULL);
+
+ if (psta)
+ rm_add_nb_req(padapter, psta);
+ }
+ }
+#else
+ sprintf(pstr(s), "\n");
+ sprintf(pstr(s), "rrm debug command was disabled\n");
+#endif
+}
+#endif /* CONFIG_RTW_80211K */
diff --git a/core/rtw_rm_fsm.c b/core/rtw_rm_fsm.c
new file mode 100644
index 0000000..1ed3c9d
--- /dev/null
+++ b/core/rtw_rm_fsm.c
@@ -0,0 +1,998 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#include
+#include
+#include "rtw_rm_fsm.h"
+
+#ifdef CONFIG_RTW_80211K
+
+struct fsm_state {
+ u8 *name;
+ int(*fsm_func)(struct rm_obj *prm, enum RM_EV_ID evid);
+};
+
+static void rm_state_initial(struct rm_obj *prm);
+static void rm_state_goto(struct rm_obj *prm, enum RM_STATE rm_state);
+static void rm_state_run(struct rm_obj *prm, enum RM_EV_ID evid);
+static struct rm_event *rm_dequeue_ev(_queue *queue);
+static struct rm_obj *rm_dequeue_rm(_queue *queue);
+
+void rm_timer_callback(void *data)
+{
+ int i;
+ _adapter *padapter = (_adapter *)data;
+ struct rm_priv *prmpriv = &padapter->rmpriv;
+ struct rm_clock *pclock;
+
+
+ /* deal with clock */
+ for (i=0;iclock[i];
+ if (pclock->prm == NULL
+ ||(ATOMIC_READ(&(pclock->counter)) == 0))
+ continue;
+
+ ATOMIC_DEC(&(pclock->counter));
+
+ if (ATOMIC_READ(&(pclock->counter)) == 0)
+ rm_post_event(pclock->prm->psta->padapter,
+ pclock->prm->rmid, prmpriv->clock[i].evid);
+ }
+ _set_timer(&prmpriv->rm_timer, CLOCK_UNIT);
+}
+
+int rtw_init_rm(_adapter *padapter)
+{
+ struct rm_priv *prmpriv = &padapter->rmpriv;
+
+
+ RTW_INFO("RM: %s\n",__func__);
+ _rtw_init_queue(&(prmpriv->rm_queue));
+ _rtw_init_queue(&(prmpriv->ev_queue));
+
+ /* bit 0-7 */
+ prmpriv->rm_en_cap_def[0] = 0
+ /*| BIT(RM_LINK_MEAS_CAP_EN)*/
+ | BIT(RM_NB_REP_CAP_EN)
+ /*| BIT(RM_PARAL_MEAS_CAP_EN)*/
+ | BIT(RM_REPEAT_MEAS_CAP_EN)
+ | BIT(RM_BCN_PASSIVE_MEAS_CAP_EN)
+ | BIT(RM_BCN_ACTIVE_MEAS_CAP_EN)
+ | BIT(RM_BCN_TABLE_MEAS_CAP_EN)
+ /*| BIT(RM_BCN_MEAS_REP_COND_CAP_EN)*/;
+
+ /* bit 8-15 */
+ prmpriv->rm_en_cap_def[1] = 0
+ /*| BIT(RM_FRAME_MEAS_CAP_EN - 8)*/
+#ifdef CONFIG_RTW_ACS
+ | BIT(RM_CH_LOAD_CAP_EN - 8)
+ | BIT(RM_NOISE_HISTO_CAP_EN - 8)
+#endif
+ /*| BIT(RM_STATIS_MEAS_CAP_EN - 8)*/
+ /*| BIT(RM_LCI_MEAS_CAP_EN - 8)*/
+ /*| BIT(RM_LCI_AMIMUTH_CAP_EN - 8)*/
+ /*| BIT(RM_TRANS_STREAM_CAT_MEAS_CAP_EN - 8)*/
+ /*| BIT(RM_TRIG_TRANS_STREAM_CAT_MEAS_CAP_EN - 8)*/;
+
+ /* bit 16-23 */
+ prmpriv->rm_en_cap_def[2] = 0
+ /*| BIT(RM_AP_CH_REP_CAP_EN - 16)*/
+ /*| BIT(RM_RM_MIB_CAP_EN - 16)*/
+ /*| BIT(RM_OP_CH_MAX_MEAS_DUR0 - 16)*/
+ /*| BIT(RM_OP_CH_MAX_MEAS_DUR1 - 16)*/
+ /*| BIT(RM_OP_CH_MAX_MEAS_DUR2 - 16)*/
+ /*| BIT(RM_NONOP_CH_MAX_MEAS_DUR0 - 16)*/
+ /*| BIT(RM_NONOP_CH_MAX_MEAS_DUR1 - 16)*/
+ /*| BIT(RM_NONOP_CH_MAX_MEAS_DUR2 - 16)*/;
+
+ /* bit 24-31 */
+ prmpriv->rm_en_cap_def[3] = 0
+ /*| BIT(RM_MEAS_PILOT_CAP0 - 24)*/
+ /*| BIT(RM_MEAS_PILOT_CAP1 - 24)*/
+ /*| BIT(RM_MEAS_PILOT_CAP2 - 24)*/
+ /*| BIT(RM_MEAS_PILOT_TRANS_INFO_CAP_EN - 24)*/
+ /*| BIT(RM_NB_REP_TSF_OFFSET_CAP_EN - 24)*/
+ | BIT(RM_RCPI_MEAS_CAP_EN - 24)
+ | BIT(RM_RSNI_MEAS_CAP_EN - 24)
+ /*| BIT(RM_BSS_AVG_ACCESS_DELAY_CAP_EN - 24)*/;
+
+ /* bit 32-39 */
+ prmpriv->rm_en_cap_def[4] = 0
+ /*| BIT(RM_BSS_AVG_ACCESS_DELAY_CAP_EN - 32)*/
+ /*| BIT(RM_AVALB_ADMIS_CAPACITY_CAP_EN - 32)*/
+ /*| BIT(RM_ANT_CAP_EN - 32)*/;
+
+ prmpriv->enable = _TRUE;
+
+ /* clock timer */
+ rtw_init_timer(&prmpriv->rm_timer,
+ padapter, rm_timer_callback, padapter);
+ _set_timer(&prmpriv->rm_timer, CLOCK_UNIT);
+
+ return _SUCCESS;
+}
+
+int rtw_deinit_rm(_adapter *padapter)
+{
+ struct rm_priv *prmpriv = &padapter->rmpriv;
+ struct rm_obj *prm;
+ struct rm_event *pev;
+
+
+ RTW_INFO("RM: %s\n",__func__);
+ prmpriv->enable = _FALSE;
+ _cancel_timer_ex(&prmpriv->rm_timer);
+
+ /* free all events and measurements */
+ while((pev = rm_dequeue_ev(&prmpriv->ev_queue)) != NULL)
+ rtw_mfree((void *)pev, sizeof(struct rm_event));
+
+ while((prm = rm_dequeue_rm(&prmpriv->rm_queue)) != NULL)
+ rm_state_run(prm, RM_EV_cancel);
+
+ _rtw_deinit_queue(&(prmpriv->rm_queue));
+ _rtw_deinit_queue(&(prmpriv->ev_queue));
+
+ return _SUCCESS;
+}
+
+int rtw_free_rm_priv(_adapter *padapter)
+{
+ return rtw_deinit_rm(padapter);
+}
+
+static int rm_enqueue_ev(_queue *queue, struct rm_event *obj, bool to_head)
+{
+ _irqL irqL;
+
+
+ if (obj == NULL)
+ return _FAIL;
+
+ _enter_critical(&queue->lock, &irqL);
+
+ if (to_head)
+ rtw_list_insert_head(&obj->list, &queue->queue);
+ else
+ rtw_list_insert_tail(&obj->list, &queue->queue);
+
+ _exit_critical(&queue->lock, &irqL);
+
+ return _SUCCESS;
+}
+
+static void rm_set_clock(struct rm_obj *prm, u32 ms, enum RM_EV_ID evid)
+{
+ ATOMIC_SET(&(prm->pclock->counter), (ms/CLOCK_UNIT));
+ prm->pclock->evid = evid;
+}
+
+static struct rm_clock *rm_alloc_clock(_adapter *padapter, struct rm_obj *prm)
+{
+ int i;
+ struct rm_priv *prmpriv = &padapter->rmpriv;
+ struct rm_clock *pclock = NULL;
+
+
+ for (i=0;iclock[i];
+
+ if (pclock->prm == NULL) {
+ pclock->prm = prm;
+ ATOMIC_SET(&(pclock->counter), 0);
+ pclock->evid = RM_EV_max;
+ break;
+ }
+ }
+ return pclock;
+}
+
+static void rm_cancel_clock(struct rm_obj *prm)
+{
+ ATOMIC_SET(&(prm->pclock->counter), 0);
+ prm->pclock->evid = RM_EV_max;
+}
+
+static void rm_free_clock(struct rm_clock *pclock)
+{
+ pclock->prm = NULL;
+ ATOMIC_SET(&(pclock->counter), 0);
+ pclock->evid = RM_EV_max;
+}
+
+static int is_list_linked(const struct list_head *head)
+{
+ return head->prev != NULL;
+}
+
+void rm_free_rmobj(struct rm_obj *prm)
+{
+ if (is_list_linked(&prm->list))
+ rtw_list_delete(&prm->list);
+
+ if (prm->q.pssid)
+ rtw_mfree(prm->q.pssid, strlen(prm->q.pssid)+1);
+
+ if (prm->q.opt.bcn.req_start)
+ rtw_mfree(prm->q.opt.bcn.req_start,
+ prm->q.opt.bcn.req_len);
+
+ if (prm->pclock)
+ rm_free_clock(prm->pclock);
+
+ rtw_mfree((void *)prm, sizeof(struct rm_obj));
+}
+
+struct rm_obj *rm_alloc_rmobj(_adapter *padapter)
+{
+ struct rm_obj *prm;
+
+
+ prm = (struct rm_obj *)rtw_malloc(sizeof(struct rm_obj));
+ if (prm == NULL)
+ return NULL;
+
+ _rtw_memset(prm, 0, sizeof(struct rm_obj));
+
+ /* alloc timer */
+ if ((prm->pclock = rm_alloc_clock(padapter, prm)) == NULL) {
+ rm_free_rmobj(prm);
+ return NULL;
+ }
+ return prm;
+}
+
+int rm_enqueue_rmobj(_adapter *padapter, struct rm_obj *prm, bool to_head)
+{
+ _irqL irqL;
+ struct rm_priv *prmpriv = &padapter->rmpriv;
+ _queue *queue = &prmpriv->rm_queue;
+
+
+ if (prm == NULL)
+ return _FAIL;
+
+ _enter_critical(&queue->lock, &irqL);
+ if (to_head)
+ rtw_list_insert_head(&prm->list, &queue->queue);
+ else
+ rtw_list_insert_tail(&prm->list, &queue->queue);
+ _exit_critical(&queue->lock, &irqL);
+
+ rm_state_initial(prm);
+
+ return _SUCCESS;
+}
+
+static struct rm_obj *rm_dequeue_rm(_queue *queue)
+{
+ _irqL irqL;
+ struct rm_obj *prm;
+
+
+ _enter_critical(&queue->lock, &irqL);
+ if (rtw_is_list_empty(&(queue->queue)))
+ prm = NULL;
+ else {
+ prm = LIST_CONTAINOR(get_next(&(queue->queue)),
+ struct rm_obj, list);
+ /* rtw_list_delete(&prm->list); */
+ }
+ _exit_critical(&queue->lock, &irqL);
+
+ return prm;
+}
+
+static struct rm_event *rm_dequeue_ev(_queue *queue)
+{
+ _irqL irqL;
+ struct rm_event *ev;
+
+
+ _enter_critical(&queue->lock, &irqL);
+ if (rtw_is_list_empty(&(queue->queue)))
+ ev = NULL;
+ else {
+ ev = LIST_CONTAINOR(get_next(&(queue->queue)),
+ struct rm_event, list);
+ rtw_list_delete(&ev->list);
+ }
+ _exit_critical(&queue->lock, &irqL);
+
+ return ev;
+}
+
+static struct rm_obj *_rm_get_rmobj(_queue *queue, u32 rmid)
+{
+ _irqL irqL;
+ _list *phead, *plist;
+ struct rm_obj *prm = NULL;
+
+
+ if (rmid == 0)
+ return NULL;
+
+ _enter_critical(&queue->lock, &irqL);
+
+ phead = get_list_head(queue);
+ plist = get_next(phead);
+ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+
+ prm = LIST_CONTAINOR(plist, struct rm_obj, list);
+ if (rmid == (prm->rmid)) {
+ _exit_critical(&queue->lock, &irqL);
+ return prm;
+ }
+ plist = get_next(plist);
+ }
+ _exit_critical(&queue->lock, &irqL);
+
+ return NULL;
+}
+
+struct sta_info *rm_get_psta(_adapter *padapter, u32 rmid)
+{
+ struct rm_priv *prmpriv = &padapter->rmpriv;
+ struct rm_obj *prm;
+
+
+ prm = _rm_get_rmobj(&prmpriv->rm_queue, rmid);
+
+ if (prm)
+ return prm->psta;
+
+ return NULL;
+}
+
+struct rm_obj *rm_get_rmobj(_adapter *padapter, u32 rmid)
+{
+ struct rm_priv *prmpriv = &padapter->rmpriv;
+
+ return _rm_get_rmobj(&prmpriv->rm_queue, rmid);
+}
+
+u8 rtw_rm_post_envent_cmd(_adapter *padapter, u32 rmid, u8 evid)
+{
+ struct cmd_obj *pcmd;
+ struct rm_event *pev;
+ struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
+ u8 res = _SUCCESS;
+
+
+ pcmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+ if (pcmd == NULL) {
+ res = _FAIL;
+ goto exit;
+ }
+ pev = (struct rm_event*)rtw_zmalloc(sizeof(struct rm_event));
+
+ if (pev == NULL) {
+ rtw_mfree((u8 *) pcmd, sizeof(struct cmd_obj));
+ res = _FAIL;
+ goto exit;
+ }
+ pev->rmid = rmid;
+ pev->evid = evid;
+
+ init_h2fwcmd_w_parm_no_rsp(pcmd, pev, GEN_CMD_CODE(_RM_POST_EVENT));
+ res = rtw_enqueue_cmd(pcmdpriv, pcmd);
+exit:
+ return res;
+}
+
+int rm_post_event(_adapter *padapter, u32 rmid, enum RM_EV_ID evid)
+{
+ if (padapter->rmpriv.enable == _FALSE)
+ return _FALSE;
+
+ RTW_INFO("RM: post asyn %s to rmid=%x\n", rm_event_name(evid), rmid);
+ rtw_rm_post_envent_cmd(padapter, rmid, evid);
+ return _SUCCESS;
+}
+
+int _rm_post_event(_adapter *padapter, u32 rmid, enum RM_EV_ID evid)
+{
+ struct rm_priv *prmpriv = &padapter->rmpriv;
+ struct rm_event *pev;
+
+ if (evid >= RM_EV_max || rmid == 0)
+ return _FALSE;
+
+ pev = (struct rm_event *)rtw_malloc(sizeof(struct rm_event));
+ if (pev == NULL)
+ return _FALSE;
+
+ pev->rmid = rmid;
+ pev->evid = evid;
+
+ RTW_INFO("RM: post sync %s to rmid=%x\n", rm_event_name(evid), rmid);
+ rm_enqueue_ev(&prmpriv->ev_queue, pev, FALSE);
+
+ return _SUCCESS;
+}
+
+static void rm_bcast_aid_handler(_adapter *padapter, struct rm_event *pev)
+{
+ _irqL irqL;
+ _list *phead, *plist;
+ _queue *queue = &padapter->rmpriv.rm_queue;
+ struct rm_obj *prm;
+
+
+ _enter_critical(&queue->lock, &irqL);
+ phead = get_list_head(queue);
+ plist = get_next(phead);
+ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+
+ prm = LIST_CONTAINOR(plist, struct rm_obj, list);
+ plist = get_next(plist);
+ if (RM_GET_AID(pev->rmid) == RM_GET_AID(prm->rmid)) {
+ _exit_critical(&queue->lock, &irqL);
+ rm_state_run(prm, pev->evid);
+ _enter_critical(&queue->lock, &irqL);
+ }
+ }
+ _exit_critical(&queue->lock, &irqL);
+ return;
+}
+
+/* main handler of RM (Resource Management) */
+void rm_handler(_adapter *padapter, struct rm_event *pe)
+{
+ int i;
+ struct rm_priv *prmpriv = &padapter->rmpriv;
+ struct rm_obj *prm;
+ struct rm_event *pev;
+
+
+ /* dequeue event */
+ while((pev = rm_dequeue_ev(&prmpriv->ev_queue)) != NULL)
+ {
+ if (RM_IS_ID_FOR_ALL(pev->rmid)) {
+ /* apply to all aid mateched measurement */
+ rm_bcast_aid_handler(padapter, pev);
+ rtw_mfree((void *)pev, sizeof(struct rm_event));
+ continue;
+ }
+
+ /* retrieve rmobj */
+ prm = _rm_get_rmobj(&prmpriv->rm_queue, pev->rmid);
+ if (prm == NULL) {
+ RTW_ERR("RM: rmid=%x event=%s doesn't find rm obj\n",
+ pev->rmid, rm_event_name(pev->evid));
+ rtw_mfree((void *)pev, sizeof(struct rm_event));
+ return;
+ }
+ /* run state machine */
+ rm_state_run(prm, pev->evid);
+ rtw_mfree((void *)pev, sizeof(struct rm_event));
+ }
+}
+
+static int rm_issue_meas_req(struct rm_obj *prm)
+{
+ switch (prm->q.action_code) {
+ case RM_ACT_RADIO_MEAS_REQ:
+ switch (prm->q.m_type) {
+ case bcn_req:
+ case ch_load_req:
+ case noise_histo_req:
+ issue_radio_meas_req(prm);
+ break;
+ default:
+ break;
+ } /* meas_type */
+ break;
+ case RM_ACT_NB_REP_REQ:
+ /* issue neighbor request */
+ issue_nb_req(prm);
+ break;
+ case RM_ACT_LINK_MEAS_REQ:
+ default:
+ return _FALSE;
+ } /* action_code */
+
+ return _SUCCESS;
+}
+
+/*
+* RM state machine
+*/
+
+static int rm_state_idle(struct rm_obj *prm, enum RM_EV_ID evid)
+{
+ _adapter *padapter = prm->psta->padapter;
+ u8 val8;
+ u32 val32;
+
+
+ prm->p.category = RTW_WLAN_CATEGORY_RADIO_MEAS;
+
+ switch (evid) {
+ case RM_EV_state_in:
+ switch (prm->q.action_code) {
+ case RM_ACT_RADIO_MEAS_REQ:
+ /* copy attrib from meas_req to meas_rep */
+ prm->p.action_code = RM_ACT_RADIO_MEAS_REP;
+ prm->p.diag_token = prm->q.diag_token;
+ prm->p.e_id = _MEAS_RSP_IE_;
+ prm->p.m_token = prm->q.m_token;
+ prm->p.m_type = prm->q.m_type;
+ prm->p.rpt = prm->q.rpt;
+ prm->p.ch_num = prm->q.ch_num;
+ prm->p.op_class = prm->q.op_class;
+
+ if (prm->q.m_type == ch_load_req
+ || prm->q.m_type == noise_histo_req) {
+ /*
+ * phydm measure current ch periodically
+ * scan current ch is not necessary
+ */
+ val8 = padapter->mlmeextpriv.cur_channel;
+ if (prm->q.ch_num == val8)
+ prm->poll_mode = 1;
+ }
+ RTW_INFO("RM: rmid=%x %s switch in repeat=%u\n",
+ prm->rmid, rm_type_req_name(prm->q.m_type),
+ prm->q.rpt);
+ break;
+ case RM_ACT_NB_REP_REQ:
+ prm->p.action_code = RM_ACT_NB_REP_RESP;
+ RTW_INFO("RM: rmid=%x Neighbor request switch in\n",
+ prm->rmid);
+ break;
+ case RM_ACT_LINK_MEAS_REQ:
+ prm->p.action_code = RM_ACT_LINK_MEAS_REP;
+ rm_set_rep_mode(prm, MEAS_REP_MOD_INCAP);
+ RTW_INFO("RM: rmid=%x Link meas switch in\n",
+ prm->rmid);
+ break;
+ default:
+ prm->p.action_code = prm->q.action_code;
+ rm_set_rep_mode(prm, MEAS_REP_MOD_INCAP);
+ RTW_INFO("RM: rmid=%x recv unknown action %d\n",
+ prm->rmid,prm->p.action_code);
+ break;
+ } /* switch() */
+
+ if (prm->rmid & RM_MASTER) {
+ if (rm_issue_meas_req(prm) == _SUCCESS)
+ rm_state_goto(prm, RM_ST_WAIT_MEAS);
+ else
+ rm_state_goto(prm, RM_ST_END);
+ return _SUCCESS;
+ } else {
+ rm_state_goto(prm, RM_ST_DO_MEAS);
+ return _SUCCESS;
+ }
+
+ if (prm->p.m_mode) {
+ issue_null_reply(prm);
+ rm_state_goto(prm, RM_ST_END);
+ return _SUCCESS;
+ }
+ if (prm->q.rand_intvl) {
+ /* get low tsf to generate random interval */
+ val32 = rtw_read32(padapter, REG_TSFTR);
+ val32 = val32 % prm->q.rand_intvl;
+ RTW_INFO("RM: rmid=%x rand_intval=%d, rand=%d\n",
+ prm->rmid, (int)prm->q.rand_intvl,val32);
+ rm_set_clock(prm, prm->q.rand_intvl,
+ RM_EV_delay_timer_expire);
+ return _SUCCESS;
+ }
+ break;
+ case RM_EV_delay_timer_expire:
+ rm_state_goto(prm, RM_ST_DO_MEAS);
+ break;
+ case RM_EV_cancel:
+ rm_state_goto(prm, RM_ST_END);
+ break;
+ case RM_EV_state_out:
+ rm_cancel_clock(prm);
+ break;
+ default:
+ break;
+ }
+ return _SUCCESS;
+}
+
+/* we do the measuring */
+static int rm_state_do_meas(struct rm_obj *prm, enum RM_EV_ID evid)
+{
+ _adapter *padapter = prm->psta->padapter;
+ u8 val8;
+ u64 val64;
+
+
+ switch (evid) {
+ case RM_EV_state_in:
+ if (prm->q.action_code == RM_ACT_RADIO_MEAS_REQ) {
+ switch (prm->q.m_type) {
+ case bcn_req:
+ if (prm->q.m_mode == bcn_req_bcn_table) {
+ RTW_INFO("RM: rmid=%x Beacon table\n",
+ prm->rmid);
+ _rm_post_event(padapter, prm->rmid,
+ RM_EV_survey_done);
+ return _SUCCESS;
+ }
+ break;
+ case ch_load_req:
+ case noise_histo_req:
+ if (prm->poll_mode)
+ _rm_post_event(padapter, prm->rmid,
+ RM_EV_survey_done);
+ return _SUCCESS;
+ default:
+ rm_state_goto(prm, RM_ST_END);
+ return _SUCCESS;
+ }
+
+ if (!ready_for_scan(prm)) {
+ prm->wait_busy = RM_BUSY_TRAFFIC_TIMES;
+ RTW_INFO("RM: wait busy traffic - %d\n",
+ prm->wait_busy);
+ rm_set_clock(prm, RM_WAIT_BUSY_TIMEOUT,
+ RM_EV_busy_timer_expire);
+ return _SUCCESS;
+ }
+ }
+ _rm_post_event(padapter, prm->rmid, RM_EV_start_meas);
+ break;
+ case RM_EV_start_meas:
+ if (prm->q.action_code == RM_ACT_RADIO_MEAS_REQ) {
+ /* resotre measurement start time */
+ rtw_hal_get_hwreg(padapter, HW_VAR_TSF, (u8 *)&val64);
+ prm->meas_start_time = val64;
+
+ switch (prm->q.m_type) {
+ case bcn_req:
+ val8 = 1; /* Enable free run counter */
+ rtw_hal_set_hwreg(padapter,
+ HW_VAR_FREECNT, &val8);
+ rm_sitesurvey(prm);
+ break;
+ case ch_load_req:
+ case noise_histo_req:
+ rm_sitesurvey(prm);
+ break;
+ default:
+ rm_state_goto(prm, RM_ST_END);
+ return _SUCCESS;
+ break;
+ }
+ }
+ /* handle measurement timeout */
+ rm_set_clock(prm, RM_MEAS_TIMEOUT, RM_EV_meas_timer_expire);
+ break;
+ case RM_EV_survey_done:
+ if (prm->q.action_code == RM_ACT_RADIO_MEAS_REQ) {
+ switch (prm->q.m_type) {
+ case bcn_req:
+ rm_cancel_clock(prm);
+ rm_state_goto(prm, RM_ST_SEND_REPORT);
+ return _SUCCESS;
+ case ch_load_req:
+ case noise_histo_req:
+ retrieve_radio_meas_result(prm);
+
+ if (rm_radio_meas_report_cond(prm) == _SUCCESS)
+ rm_state_goto(prm, RM_ST_SEND_REPORT);
+ else
+ rm_set_clock(prm, RM_COND_INTVL,
+ RM_EV_retry_timer_expire);
+ break;
+ default:
+ rm_state_goto(prm, RM_ST_END);
+ return _SUCCESS;
+ }
+ }
+ break;
+ case RM_EV_meas_timer_expire:
+ RTW_INFO("RM: rmid=%x measurement timeount\n",prm->rmid);
+ rm_set_rep_mode(prm, MEAS_REP_MOD_REFUSE);
+ issue_null_reply(prm);
+ rm_state_goto(prm, RM_ST_END);
+ break;
+ case RM_EV_busy_timer_expire:
+ if (!ready_for_scan(prm) && prm->wait_busy--) {
+ RTW_INFO("RM: wait busy - %d\n",prm->wait_busy);
+ rm_set_clock(prm, RM_WAIT_BUSY_TIMEOUT,
+ RM_EV_busy_timer_expire);
+ break;
+ }
+ else if (prm->wait_busy <= 0) {
+ RTW_INFO("RM: wait busy timeout\n");
+ rm_set_rep_mode(prm, MEAS_REP_MOD_REFUSE);
+ issue_null_reply(prm);
+ rm_state_goto(prm, RM_ST_END);
+ return _SUCCESS;
+ }
+ _rm_post_event(padapter, prm->rmid, RM_EV_start_meas);
+ break;
+ case RM_EV_request_timer_expire:
+ rm_set_rep_mode(prm, MEAS_REP_MOD_REFUSE);
+ issue_null_reply(prm);
+ rm_state_goto(prm, RM_ST_END);
+ break;
+ case RM_EV_retry_timer_expire:
+ /* expired due to meas condition mismatch, meas again */
+ _rm_post_event(padapter, prm->rmid, RM_EV_start_meas);
+ break;
+ case RM_EV_cancel:
+ rm_set_rep_mode(prm, MEAS_REP_MOD_REFUSE);
+ issue_null_reply(prm);
+ rm_state_goto(prm, RM_ST_END);
+ break;
+ case RM_EV_state_out:
+ rm_cancel_clock(prm);
+ /* resotre measurement end time */
+ rtw_hal_get_hwreg(padapter, HW_VAR_TSF, (u8 *)&val64);
+ _rtw_memcpy(&prm->meas_end_time, (char *)&val64, sizeof(u64));
+
+ val8 = 0; /* Disable free run counter */
+ rtw_hal_set_hwreg(padapter, HW_VAR_FREECNT, &val8);
+ break;
+ default:
+ break;
+ }
+
+ return _SUCCESS;
+}
+
+static int rm_state_wait_meas(struct rm_obj *prm, enum RM_EV_ID evid)
+{
+ u8 val8;
+ u64 val64;
+
+
+ switch (evid) {
+ case RM_EV_state_in:
+ /* we create meas_req, waiting for peer report */
+ rm_set_clock(prm, RM_REQ_TIMEOUT,
+ RM_EV_request_timer_expire);
+ break;
+ case RM_EV_recv_rep:
+ rm_state_goto(prm, RM_ST_RECV_REPORT);
+ break;
+ case RM_EV_request_timer_expire:
+ case RM_EV_cancel:
+ rm_state_goto(prm, RM_ST_END);
+ break;
+ case RM_EV_state_out:
+ rm_cancel_clock(prm);
+ break;
+ default:
+ break;
+ }
+ return _SUCCESS;
+}
+
+static int rm_state_send_report(struct rm_obj *prm, enum RM_EV_ID evid)
+{
+ u8 val8;
+
+
+ switch (evid) {
+ case RM_EV_state_in:
+ /* we have to issue report */
+ switch (prm->q.m_type) {
+ case bcn_req:
+ issue_beacon_rep(prm);
+ break;
+ case ch_load_req:
+ case noise_histo_req:
+ issue_radio_meas_rep(prm);
+ break;
+ default:
+ rm_state_goto(prm, RM_ST_END);
+ return _SUCCESS;
+ }
+
+ /* check repeat */
+ if (prm->p.rpt) {
+ RTW_INFO("RM: rmid=%x repeat=%u/%u\n",
+ prm->rmid, prm->p.rpt,
+ prm->q.rpt);
+ prm->p.rpt--;
+ /*
+ * we recv meas_req,
+ * delay for a wihile and than meas again
+ */
+ if (prm->poll_mode)
+ rm_set_clock(prm, RM_REPT_POLL_INTVL,
+ RM_EV_repeat_delay_expire);
+ else
+ rm_set_clock(prm, RM_REPT_SCAN_INTVL,
+ RM_EV_repeat_delay_expire);
+ return _SUCCESS;
+ }
+ /* we are done */
+ rm_state_goto(prm, RM_ST_END);
+ break;
+ case RM_EV_repeat_delay_expire:
+ rm_state_goto(prm, RM_ST_DO_MEAS);
+ break;
+ case RM_EV_cancel:
+ rm_state_goto(prm, RM_ST_END);
+ break;
+ case RM_EV_state_out:
+ rm_cancel_clock(prm);
+ break;
+ default:
+ break;
+ }
+ return _SUCCESS;
+}
+
+static int rm_state_recv_report(struct rm_obj *prm, enum RM_EV_ID evid)
+{
+ u8 val8;
+
+
+ switch (evid) {
+ case RM_EV_state_in:
+ /* we issue meas_req, got peer's meas report */
+ switch (prm->p.action_code) {
+ case RM_ACT_RADIO_MEAS_REP:
+ /* check refuse, incapable and repeat */
+ val8 = prm->p.m_mode;
+ if (val8) {
+ RTW_INFO("RM: rmid=%x peer reject (%s repeat=%d)\n",
+ prm->rmid,
+ val8|MEAS_REP_MOD_INCAP?"INCAP":
+ val8|MEAS_REP_MOD_REFUSE?"REFUSE":
+ val8|MEAS_REP_MOD_LATE?"LATE":"",
+ prm->p.rpt);
+ rm_state_goto(prm, RM_ST_END);
+ return _SUCCESS;
+ }
+ break;
+ case RM_ACT_NB_REP_RESP:
+ /* report to upper layer if needing */
+ rm_state_goto(prm, RM_ST_END);
+ return _SUCCESS;
+ default:
+ rm_state_goto(prm, RM_ST_END);
+ return _SUCCESS;
+ }
+ /* check repeat */
+ if (prm->p.rpt) {
+ RTW_INFO("RM: rmid=%x repeat=%u/%u\n",
+ prm->rmid, prm->p.rpt,
+ prm->q.rpt);
+ prm->p.rpt--;
+ /* waitting more report */
+ rm_state_goto(prm, RM_ST_WAIT_MEAS);
+ break;
+ }
+ /* we are done */
+ rm_state_goto(prm, RM_ST_END);
+ break;
+ case RM_EV_cancel:
+ rm_state_goto(prm, RM_ST_END);
+ break;
+ case RM_EV_state_out:
+ rm_cancel_clock(prm);
+ break;
+ default:
+ break;
+ }
+ return _SUCCESS;
+}
+
+static int rm_state_end(struct rm_obj *prm, enum RM_EV_ID evid)
+{
+ switch (evid) {
+ case RM_EV_state_in:
+ _rm_post_event(prm->psta->padapter, prm->rmid, RM_EV_state_out);
+ break;
+
+ case RM_EV_cancel:
+ case RM_EV_state_out:
+ default:
+ rm_free_rmobj(prm);
+ break;
+ }
+ return _SUCCESS;
+}
+
+struct fsm_state rm_fsm[] = {
+ {"RM_ST_IDLE", rm_state_idle},
+ {"RM_ST_DO_MEAS", rm_state_do_meas},
+ {"RM_ST_WAIT_MEAS", rm_state_wait_meas},
+ {"RM_ST_SEND_REPORT", rm_state_send_report},
+ {"RM_ST_RECV_REPORT", rm_state_recv_report},
+ {"RM_ST_END", rm_state_end}
+};
+
+char *rm_state_name(enum RM_STATE state)
+{
+ return rm_fsm[state].name;
+}
+
+char *rm_event_name(enum RM_EV_ID evid)
+{
+ switch(evid) {
+ case RM_EV_state_in:
+ return "RM_EV_state_in";
+ case RM_EV_busy_timer_expire:
+ return "RM_EV_busy_timer_expire";
+ case RM_EV_delay_timer_expire:
+ return "RM_EV_delay_timer_expire";
+ case RM_EV_meas_timer_expire:
+ return "RM_EV_meas_timer_expire";
+ case RM_EV_repeat_delay_expire:
+ return "RM_EV_repeat_delay_expire";
+ case RM_EV_retry_timer_expire:
+ return "RM_EV_retry_timer_expire";
+ case RM_EV_request_timer_expire:
+ return "RM_EV_request_timer_expire";
+ case RM_EV_wait_report:
+ return "RM_EV_wait_report";
+ case RM_EV_start_meas:
+ return "RM_EV_start_meas";
+ case RM_EV_survey_done:
+ return "RM_EV_survey_done";
+ case RM_EV_recv_rep:
+ return "RM_EV_recv_report";
+ case RM_EV_cancel:
+ return "RM_EV_cancel";
+ case RM_EV_state_out:
+ return "RM_EV_state_out";
+ case RM_EV_max:
+ return "RM_EV_max";
+ default:
+ return "RM_EV_unknown";
+ }
+ return "UNKNOWN";
+}
+
+static void rm_state_initial(struct rm_obj *prm)
+{
+ prm->state = RM_ST_IDLE;
+
+ RTW_INFO("\n");
+ RTW_INFO("RM: rmid=%x %-18s -> %s\n",prm->rmid,
+ "new measurement", rm_fsm[prm->state].name);
+
+ rm_post_event(prm->psta->padapter, prm->rmid, RM_EV_state_in);
+}
+
+static void rm_state_run(struct rm_obj *prm, enum RM_EV_ID evid)
+{
+ RTW_INFO("RM: rmid=%x %-18s %s\n",prm->rmid,
+ rm_fsm[prm->state].name,rm_event_name(evid));
+
+ rm_fsm[prm->state].fsm_func(prm, evid);
+}
+
+static void rm_state_goto(struct rm_obj *prm, enum RM_STATE rm_state)
+{
+ if (prm->state == rm_state)
+ return;
+
+ rm_state_run(prm, RM_EV_state_out);
+
+ RTW_INFO("\n");
+ RTW_INFO("RM: rmid=%x %-18s -> %s\n",prm->rmid,
+ rm_fsm[prm->state].name, rm_fsm[rm_state].name);
+
+ prm->state = rm_state;
+ rm_state_run(prm, RM_EV_state_in);
+}
+#endif /* CONFIG_RTW_80211K */
diff --git a/core/rtw_rson.c b/core/rtw_rson.c
new file mode 100644
index 0000000..0aa5850
--- /dev/null
+++ b/core/rtw_rson.c
@@ -0,0 +1,595 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#define _RTW_RSON_C_
+
+#include
+
+#ifdef CONFIG_RTW_REPEATER_SON
+
+/******** Custommize Part ***********************/
+
+unsigned char RTW_RSON_OUI[] = {0xFA, 0xFA, 0xFA};
+#define RSON_SCORE_DIFF_TH 8
+
+/*
+ Calculate the corresponding score.
+*/
+inline u8 rtw_cal_rson_score(struct rtw_rson_struct *cand_rson_data, NDIS_802_11_RSSI Rssi)
+{
+ if ((cand_rson_data->hopcnt == RTW_RSON_HC_NOTREADY)
+ || (cand_rson_data->connectible == RTW_RSON_DENYCONNECT))
+ return RTW_RSON_SCORE_NOTCNNT;
+
+ return RTW_RSON_SCORE_MAX - (cand_rson_data->hopcnt * 10) + (Rssi/10);
+}
+
+/*************************************************/
+
+
+static u8 rtw_rson_block_bssid_idx = 0;
+u8 rtw_rson_block_bssid[10][6] = {
+ /*{0x02, 0xE0, 0x4C, 0x07, 0xC3, 0xF6}*/
+};
+
+/* fake root, regard a real AP as a SO root */
+static u8 rtw_rson_root_bssid_idx = 0;
+u8 rtw_rson_root_bssid[10][6] = {
+ /*{0x1c, 0x5f, 0x2b, 0x5a, 0x60, 0x24}*/
+};
+
+int is_match_bssid(u8 *mac, u8 bssid_array[][6], int num)
+{
+ int i;
+
+ for (i = 0; i < num; i++)
+ if (_rtw_memcmp(mac, bssid_array[i], 6) == _TRUE)
+ return _TRUE;
+ return _FALSE;
+}
+
+void init_rtw_rson_data(struct dvobj_priv *dvobj)
+{
+ /*Aries todo. if pdvobj->rson_data.ver == 1 */
+ dvobj->rson_data.ver = RTW_RSON_VER;
+ dvobj->rson_data.id = CONFIG_RTW_REPEATER_SON_ID;
+#ifdef CONFIG_RTW_REPEATER_SON_ROOT
+ dvobj->rson_data.hopcnt = RTW_RSON_HC_ROOT;
+ dvobj->rson_data.connectible = RTW_RSON_ALLOWCONNECT;
+#else
+ dvobj->rson_data.hopcnt = RTW_RSON_HC_NOTREADY;
+ dvobj->rson_data.connectible = RTW_RSON_DENYCONNECT;
+#endif
+ dvobj->rson_data.loading = 0;
+ _rtw_memset(dvobj->rson_data.res, 0xAA, sizeof(dvobj->rson_data.res));
+}
+
+void rtw_rson_get_property_str(_adapter *padapter, char *rson_data_str)
+{
+ struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);
+
+ sprintf(rson_data_str, "version : \t%d\nid : \t\t%08x\nhop count : \t%d\nconnectible : \t%s\nloading : \t%d\nreserve : \t%16ph\n",
+ pdvobj->rson_data.ver,
+ pdvobj->rson_data.id,
+ pdvobj->rson_data.hopcnt,
+ pdvobj->rson_data.connectible ? "connectable":"unconnectable",
+ pdvobj->rson_data.loading,
+ pdvobj->rson_data.res);
+}
+
+int str2hexbuf(char *str, u8 *hexbuf, int len)
+{
+ u8 *p;
+ int i, slen, idx = 0;
+
+ p = (unsigned char *)str;
+ if ((*p != '0') || (*(p+1) != 'x'))
+ return _FALSE;
+ slen = strlen(str);
+ if (slen > (len*2) + 2)
+ return _FALSE;
+ p += 2;
+ for (i = 0 ; i < len; i++, idx = idx+2) {
+ hexbuf[i] = key_2char2num(p[idx], p[idx + 1]);
+ if (slen <= idx+2)
+ break;
+ }
+ return _TRUE;
+}
+
+int rtw_rson_set_property(_adapter *padapter, char *field, char *value)
+{
+ struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);
+ int num = 0;
+
+ if (_rtw_memcmp(field, (u8 *)"ver", 3) == _TRUE)
+ pdvobj->rson_data.ver = rtw_atoi(value);
+ else if (_rtw_memcmp(field, (u8 *)"id", 2) == _TRUE)
+ num = sscanf(value, "%08x", &(pdvobj->rson_data.id));
+ else if (_rtw_memcmp(field, (u8 *)"hc", 2) == _TRUE)
+ num = sscanf(value, "%hhu", &(pdvobj->rson_data.hopcnt));
+ else if (_rtw_memcmp(field, (u8 *)"cnt", 3) == _TRUE)
+ num = sscanf(value, "%hhu", &(pdvobj->rson_data.connectible));
+ else if (_rtw_memcmp(field, (u8 *)"loading", 2) == _TRUE)
+ num = sscanf(value, "%hhu", &(pdvobj->rson_data.loading));
+ else if (_rtw_memcmp(field, (u8 *)"res", 2) == _TRUE) {
+ str2hexbuf(value, pdvobj->rson_data.res, 16);
+ return 1;
+ } else
+ return _FALSE;
+ return num;
+}
+
+/*
+ return : TRUE -- competitor is taking advantage than condidate
+ FALSE -- we should continue keeping candidate
+*/
+int rtw_rson_choose(struct wlan_network **candidate, struct wlan_network *competitor)
+{
+ s16 comp_score = 0, cand_score = 0;
+ struct rtw_rson_struct rson_cand, rson_comp;
+
+ if (is_match_bssid(competitor->network.MacAddress, rtw_rson_block_bssid, rtw_rson_block_bssid_idx) == _TRUE)
+ return _FALSE;
+
+ if ((competitor == NULL)
+ || (rtw_get_rson_struct(&(competitor->network), &rson_comp) != _TRUE)
+ || (rson_comp.id != CONFIG_RTW_REPEATER_SON_ID))
+ return _FALSE;
+
+ comp_score = rtw_cal_rson_score(&rson_comp, competitor->network.Rssi);
+ if (comp_score == RTW_RSON_SCORE_NOTCNNT)
+ return _FALSE;
+
+ if (*candidate == NULL)
+ return _TRUE;
+ if (rtw_get_rson_struct(&((*candidate)->network), &rson_cand) != _TRUE)
+ return _FALSE;
+
+ cand_score = rtw_cal_rson_score(&rson_cand, (*candidate)->network.Rssi);
+ RTW_INFO("%s: competitor_score=%d, candidate_score=%d\n", __func__, comp_score, cand_score);
+ if (comp_score - cand_score > RSON_SCORE_DIFF_TH)
+ return _TRUE;
+
+ return _FALSE;
+}
+
+inline u8 rtw_rson_varify_ie(u8 *p)
+{
+ u8 *ptr = NULL;
+ u8 ver;
+ u32 id;
+ u8 hopcnt;
+ u8 allcnnt;
+
+ ptr = p + 2 + sizeof(RTW_RSON_OUI);
+ ver = *ptr;
+
+ /* for (ver == 1) */
+ if (ver != 1)
+ return _FALSE;
+
+ return _TRUE;
+}
+
+/*
+ Parsing RTK self-organization vendor IE
+*/
+int rtw_get_rson_struct(WLAN_BSSID_EX *bssid, struct rtw_rson_struct *rson_data)
+{
+ sint limit = 0;
+ u32 len;
+ u8 *p;
+
+ if ((rson_data == NULL) || (bssid == NULL))
+ return -EINVAL;
+
+ /* Default */
+ rson_data->id = 0;
+ rson_data->ver = 0;
+ rson_data->hopcnt = 0;
+ rson_data->connectible = 0;
+ rson_data->loading = 0;
+ /* fake root */
+ if (is_match_bssid(bssid->MacAddress, rtw_rson_root_bssid, rtw_rson_root_bssid_idx) == _TRUE) {
+ rson_data->id = CONFIG_RTW_REPEATER_SON_ID;
+ rson_data->ver = RTW_RSON_VER;
+ rson_data->hopcnt = RTW_RSON_HC_ROOT;
+ rson_data->connectible = RTW_RSON_ALLOWCONNECT;
+ rson_data->loading = 0;
+ return _TRUE;
+ }
+ limit = bssid->IELength - _BEACON_IE_OFFSET_;
+
+ for (p = bssid->IEs + _BEACON_IE_OFFSET_; ; p += (len + 2)) {
+ p = rtw_get_ie(p, _VENDOR_SPECIFIC_IE_, &len, limit);
+ limit -= len;
+ if ((p == NULL) || (len == 0))
+ break;
+ if (p && (_rtw_memcmp(p + 2, RTW_RSON_OUI, sizeof(RTW_RSON_OUI)) == _TRUE)
+ && rtw_rson_varify_ie(p)) {
+ p = p + 2 + sizeof(RTW_RSON_OUI);
+ rson_data->ver = *p;
+ /* for (ver == 1) */
+ p = p + 1;
+ rson_data->id = le32_to_cpup((__le32 *)p);
+ p = p + 4;
+ rson_data->hopcnt = *p;
+ p = p + 1;
+ rson_data->connectible = *p;
+ p = p + 1;
+ rson_data->loading = *p;
+
+ return _TRUE;
+ }
+ }
+ return -EBADMSG;
+}
+
+u32 rtw_rson_append_ie(_adapter *padapter, unsigned char *pframe, u32 *len)
+{
+ u8 *ptr, *ori, ie_len = 0;
+ struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);
+ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+/* static int iii = 0;*/
+
+ if ((!pdvobj) || (!pframe))
+ return 0;
+ ptr = ori = pframe;
+ *ptr++ = _VENDOR_SPECIFIC_IE_;
+ *ptr++ = ie_len = sizeof(RTW_RSON_OUI)+sizeof(pdvobj->rson_data);
+ _rtw_memcpy(ptr, RTW_RSON_OUI, sizeof(RTW_RSON_OUI));
+ ptr = ptr + sizeof(RTW_RSON_OUI);
+ *ptr++ = pdvobj->rson_data.ver;
+ *(s32 *)ptr = cpu_to_le32(pdvobj->rson_data.id);
+ ptr = ptr + sizeof(pdvobj->rson_data.id);
+ *ptr++ = pdvobj->rson_data.hopcnt;
+ *ptr++ = pdvobj->rson_data.connectible;
+ *ptr++ = pdvobj->rson_data.loading;
+ _rtw_memcpy(ptr, pdvobj->rson_data.res, sizeof(pdvobj->rson_data.res));
+ pframe = ptr;
+/*
+ iii = iii % 20;
+ if (iii++ == 0)
+ RTW_INFO("%s : RTW RSON IE : %20ph\n", __func__, ori);
+*/
+ *len += (ie_len+2);
+ return ie_len;
+
+}
+
+void rtw_rson_do_disconnect(_adapter *padapter)
+{
+ struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);
+
+ RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
+#ifndef CONFIG_RTW_REPEATER_SON_ROOT
+ pdvobj->rson_data.ver = RTW_RSON_VER;
+ pdvobj->rson_data.id = CONFIG_RTW_REPEATER_SON_ID;
+ pdvobj->rson_data.hopcnt = RTW_RSON_HC_NOTREADY;
+ pdvobj->rson_data.connectible = RTW_RSON_DENYCONNECT;
+ pdvobj->rson_data.loading = 0;
+ rtw_mi_tx_beacon_hdl(padapter);
+#endif
+}
+
+void rtw_rson_join_done(_adapter *padapter)
+{
+ struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);
+ WLAN_BSSID_EX *cur_network = NULL;
+ struct rtw_rson_struct rson_data;
+
+ RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
+ if (!padapter->mlmepriv.cur_network_scanned)
+ return;
+ cur_network = &(padapter->mlmepriv.cur_network_scanned->network);
+ if (rtw_get_rson_struct(cur_network, &rson_data) != _TRUE) {
+ RTW_ERR("%s: try to join a improper network(%s)\n", __func__, cur_network->Ssid.Ssid);
+ return;
+ }
+
+#ifndef CONFIG_RTW_REPEATER_SON_ROOT
+ /* update rson_data */
+ pdvobj->rson_data.ver = RTW_RSON_VER;
+ pdvobj->rson_data.id = rson_data.id;
+ pdvobj->rson_data.hopcnt = rson_data.hopcnt + 1;
+ pdvobj->rson_data.connectible = RTW_RSON_ALLOWCONNECT;
+ pdvobj->rson_data.loading = 0;
+ rtw_mi_tx_beacon_hdl(padapter);
+#endif
+}
+
+int rtw_rson_isupdate_roamcan(struct mlme_priv *mlme
+ , struct wlan_network **candidate, struct wlan_network *competitor)
+{
+ struct rtw_rson_struct rson_cand, rson_comp, rson_curr;
+ s16 comp_score, cand_score, curr_score;
+
+ if ((competitor == NULL)
+ || (rtw_get_rson_struct(&(competitor->network), &rson_comp) != _TRUE)
+ || (rson_comp.id != CONFIG_RTW_REPEATER_SON_ID))
+ return _FALSE;
+
+ if (is_match_bssid(competitor->network.MacAddress, rtw_rson_block_bssid, rtw_rson_block_bssid_idx) == _TRUE)
+ return _FALSE;
+
+ if ((!mlme->cur_network_scanned)
+ || (mlme->cur_network_scanned == competitor)
+ || (rtw_get_rson_struct(&(mlme->cur_network_scanned->network), &rson_curr)) != _TRUE)
+ return _FALSE;
+
+ if (rtw_get_passing_time_ms((u32)competitor->last_scanned) >= mlme->roam_scanr_exp_ms)
+ return _FALSE;
+
+ comp_score = rtw_cal_rson_score(&rson_comp, competitor->network.Rssi);
+ curr_score = rtw_cal_rson_score(&rson_curr, mlme->cur_network_scanned->network.Rssi);
+ if (comp_score - curr_score < RSON_SCORE_DIFF_TH)
+ return _FALSE;
+
+ if (*candidate == NULL)
+ return _TRUE;
+
+ if (rtw_get_rson_struct(&((*candidate)->network), &rson_cand) != _TRUE) {
+ RTW_ERR("%s : Unable to get rson_struct from candidate(%s -- " MAC_FMT")\n",
+ __func__, (*candidate)->network.Ssid.Ssid, MAC_ARG((*candidate)->network.MacAddress));
+ return _FALSE;
+ }
+ cand_score = rtw_cal_rson_score(&rson_cand, (*candidate)->network.Rssi);
+ RTW_DBG("comp_score=%d , cand_score=%d , curr_score=%d\n", comp_score, cand_score, curr_score);
+ if (cand_score < comp_score)
+ return _TRUE;
+
+#if 0 /* Handle 11R protocol */
+#ifdef CONFIG_RTW_80211R
+ if (rtw_chk_ft_flags(adapter, RTW_FT_SUPPORTED)) {
+ ptmp = rtw_get_ie(&competitor->network.IEs[12], _MDIE_, &mdie_len, competitor->network.IELength-12);
+ if (ptmp) {
+ if (!_rtw_memcmp(&pftpriv->mdid, ptmp+2, 2))
+ goto exit;
+
+ /*The candidate don't support over-the-DS*/
+ if (rtw_chk_ft_flags(adapter, RTW_FT_STA_OVER_DS_SUPPORTED)) {
+ if ((rtw_chk_ft_flags(adapter, RTW_FT_OVER_DS_SUPPORTED) && !(*(ptmp+4) & 0x01)) ||
+ (!rtw_chk_ft_flags(adapter, RTW_FT_OVER_DS_SUPPORTED) && (*(ptmp+4) & 0x01))) {
+ RTW_INFO("FT: ignore the candidate(" MAC_FMT ") for over-the-DS\n", MAC_ARG(competitor->network.MacAddress));
+ rtw_clr_ft_flags(adapter, RTW_FT_OVER_DS_SUPPORTED);
+ goto exit;
+ }
+ }
+ } else
+ goto exit;
+ }
+#endif
+#endif
+ return _FALSE;
+}
+
+void rtw_rson_show_survey_info(struct seq_file *m, _list *plist, _list *phead)
+{
+ struct wlan_network *pnetwork = NULL;
+ struct rtw_rson_struct rson_data;
+ s16 rson_score;
+ u16 index = 0;
+
+ RTW_PRINT_SEL(m, "%5s %-17s %3s %5s %14s %10s %-3s %5s %32s\n", "index", "bssid", "ch", "id", "hop_cnt", "loading", "RSSI", "score", "ssid");
+ while (1) {
+ if (rtw_end_of_queue_search(phead, plist) == _TRUE)
+ break;
+
+ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
+ if (!pnetwork)
+ break;
+
+ _rtw_memset(&rson_data, 0, sizeof(rson_data));
+ rson_score = 0;
+ if (rtw_get_rson_struct(&(pnetwork->network), &rson_data) == _TRUE)
+ rson_score = rtw_cal_rson_score(&rson_data, pnetwork->network.Rssi);
+ RTW_PRINT_SEL(m, "%5d "MAC_FMT" %3d 0x%08x %6d %10d %6d %6d %32s\n",
+ ++index,
+ MAC_ARG(pnetwork->network.MacAddress),
+ pnetwork->network.Configuration.DSConfig,
+ rson_data.id,
+ rson_data.hopcnt,
+ rson_data.loading,
+ (int)pnetwork->network.Rssi,
+ rson_score,
+ pnetwork->network.Ssid.Ssid);
+ plist = get_next(plist);
+ }
+
+}
+
+/*
+ Description : As a AP role, We need to check the qualify of associating STA.
+ We also need to check if we are ready to be associated.
+
+ return : TRUE -- AP REJECT this STA
+ FALSE -- AP ACCEPT this STA
+*/
+u8 rtw_rson_ap_check_sta(_adapter *padapter, u8 *pframe, uint pkt_len, unsigned short ie_offset)
+{
+ struct wlan_network *pnetwork = NULL;
+ struct rtw_rson_struct rson_target;
+ struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter);
+ int len = 0;
+ u8 ret = _FALSE;
+ u8 *p;
+
+#ifndef CONFIG_RTW_REPEATER_SON_ROOT
+ _rtw_memset(&rson_target, 0, sizeof(rson_target));
+ for (p = pframe + WLAN_HDR_A3_LEN + ie_offset; ; p += (len + 2)) {
+ p = rtw_get_ie(p, _VENDOR_SPECIFIC_IE_, &len, pkt_len - WLAN_HDR_A3_LEN - ie_offset);
+
+ if ((p == NULL) || (len == 0))
+ break;
+
+ if (p && (_rtw_memcmp(p + 2, RTW_RSON_OUI, sizeof(RTW_RSON_OUI)) == _TRUE)
+ && rtw_rson_varify_ie(p)) {
+ p = p + 2 + sizeof(RTW_RSON_OUI);
+ rson_target.ver = *p;
+ /* for (ver == 1) */
+ p = p + 1;
+ rson_target.id = le32_to_cpup((__le32 *)p);
+ p = p + 4;
+ rson_target.hopcnt = *p;
+ p = p + 1;
+ rson_target.connectible = *p;
+ p = p + 1;
+ rson_target.loading = *p;
+ break;
+ }
+ }
+
+ if (rson_target.id == 0) /* Normal STA, not a RSON STA */
+ ret = _FALSE;
+ else if (rson_target.id != pdvobj->rson_data.id) {
+ ret = _TRUE;
+ RTW_INFO("%s : Reject AssoReq because RSON ID not match, STA=%08x, our=%08x\n",
+ __func__, rson_target.id, pdvobj->rson_data.id);
+ } else if ((pdvobj->rson_data.hopcnt == RTW_RSON_HC_NOTREADY)
+ || (pdvobj->rson_data.connectible == RTW_RSON_DENYCONNECT)) {
+ ret = _TRUE;
+ RTW_INFO("%s : Reject AssoReq becuase our hopcnt=%d or connectbile=%d\n",
+ __func__, pdvobj->rson_data.hopcnt, pdvobj->rson_data.connectible);
+ }
+#endif
+ return ret;
+}
+
+u8 rtw_rson_scan_wk_cmd(_adapter *padapter, int op)
+{
+ struct cmd_obj *ph2c;
+ struct drvextra_cmd_parm *pdrvextra_cmd_parm;
+ struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
+ u8 *extra_cmd_buf;
+ u8 res = _SUCCESS;
+
+ ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+ if (ph2c == NULL) {
+ res = _FAIL;
+ goto exit;
+ }
+
+ pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+ if (pdrvextra_cmd_parm == NULL) {
+ rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj));
+ res = _FAIL;
+ goto exit;
+ }
+ pdrvextra_cmd_parm->ec_id = RSON_SCAN_WK_CID;
+ pdrvextra_cmd_parm->type = op;
+ pdrvextra_cmd_parm->size = 0;
+ pdrvextra_cmd_parm->pbuf = NULL;
+
+ init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
+
+ res = rtw_enqueue_cmd(pcmdpriv, ph2c);
+
+exit:
+ return res;
+
+}
+
+void rtw_rson_scan_cmd_hdl(_adapter *padapter, int op)
+{
+ struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
+ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+ u8 val8;
+
+ if (mlmeext_chk_scan_state(pmlmeext, SCAN_DISABLE) != _TRUE)
+ return;
+ if (op == RSON_SCAN_PROCESS) {
+ padapter->rtw_rson_scanstage = RSON_SCAN_PROCESS;
+ val8 = 0x1e;
+ rtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &val8, _FALSE);
+ val8 = 1;
+ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
+ issue_probereq(padapter, NULL, NULL);
+ /* stop rson_scan after 100ms */
+ _set_timer(&(pmlmeext->rson_scan_timer), 100);
+ } else if (op == RSON_SCAN_DISABLE) {
+ padapter->rtw_rson_scanstage = RSON_SCAN_DISABLE;
+ val8 = 0;
+ rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8));
+ val8 = 0xff;
+ rtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &val8, _FALSE);
+ /* report_surveydone_event(padapter);*/
+ if (pmlmepriv->to_join == _TRUE) {
+ if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) != _TRUE) {
+ int s_ret;
+
+ set_fwstate(pmlmepriv, _FW_UNDER_LINKING);
+ pmlmepriv->to_join = _FALSE;
+ s_ret = rtw_select_and_join_from_scanned_queue(pmlmepriv);
+ if (s_ret == _SUCCESS)
+ _set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT);
+ else if (s_ret == 2) {
+ _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
+ rtw_indicate_connect(padapter);
+ } else {
+ RTW_INFO("try_to_join, but select scanning queue fail, to_roam:%d\n", rtw_to_roam(padapter));
+ if (rtw_to_roam(padapter) != 0) {
+ if (rtw_dec_to_roam(padapter) == 0) {
+ rtw_set_to_roam(padapter, 0);
+#ifdef CONFIG_INTEL_WIDI
+ if (padapter->mlmepriv.widi_state == INTEL_WIDI_STATE_ROAMING) {
+ _rtw_memset(pmlmepriv->sa_ext, 0x00, L2SDTA_SERVICE_VE_LEN);
+ intel_widi_wk_cmd(padapter, INTEL_WIDI_LISTEN_WK, NULL, 0);
+ RTW_INFO("change to widi listen\n");
+ }
+#endif /* CONFIG_INTEL_WIDI */
+ rtw_free_assoc_resources(padapter, 1);
+ rtw_indicate_disconnect(padapter, 0, _FALSE);
+ } else
+ pmlmepriv->to_join = _TRUE;
+ } else
+ rtw_indicate_disconnect(padapter, 0, _FALSE);
+ _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
+ }
+ }
+ } else {
+ if (rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE)) {
+ if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)
+ && check_fwstate(pmlmepriv, _FW_LINKED)) {
+ if (rtw_select_roaming_candidate(pmlmepriv) == _SUCCESS) {
+#ifdef CONFIG_RTW_80211R
+ if (rtw_chk_ft_flags(padapter, RTW_FT_OVER_DS_SUPPORTED)) {
+ start_clnt_ft_action(adapter, (u8 *)pmlmepriv->roam_network->network.MacAddress);
+ } else {
+ /*wait a little time to retrieve packets buffered in the current ap while scan*/
+ _set_timer(&pmlmeext->ft_roam_timer, 30);
+ }
+#else
+ receive_disconnect(padapter, pmlmepriv->cur_network.network.MacAddress
+ , WLAN_REASON_ACTIVE_ROAM, _FALSE);
+#endif
+ }
+ }
+ }
+ issue_action_BSSCoexistPacket(padapter);
+ issue_action_BSSCoexistPacket(padapter);
+ issue_action_BSSCoexistPacket(padapter);
+ }
+ } else {
+ RTW_ERR("%s : improper parameter -- op = %d\n", __func__, op);
+ }
+}
+
+#endif /* CONFIG_RTW_REPEATER_SON */
diff --git a/core/rtw_sdio.c b/core/rtw_sdio.c
index 63467bc..e8f49bf 100644
--- a/core/rtw_sdio.c
+++ b/core/rtw_sdio.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2015 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,11 +11,7 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- ******************************************************************************/
+ *****************************************************************************/
#define _RTW_SDIO_C_
#include /* struct dvobj_priv and etc. */
@@ -39,22 +35,61 @@
*/
static u8 sdio_io(struct dvobj_priv *d, u32 addr, void *buf, size_t len, u8 write, u8 cmd52)
{
+ u32 addr_drv; /* address with driver defined bit */
int err;
+ u8 retry = 0;
+ u8 stop_retry = _FALSE; /* flag for stopping retry or not */
- if (cmd52)
- addr = RTW_SDIO_ADDR_CMD52_GEN(addr);
-
- if (write)
- err = d->intf_ops->write(d, addr, buf, len, 0);
- else
- err = d->intf_ops->read(d, addr, buf, len, 0);
- if (err) {
- RTW_INFO("%s: [ERROR] %s FAIL! error(%d)\n",
- __FUNCTION__, write ? "write" : "read", err);
+ if (rtw_is_surprise_removed(dvobj_get_primary_adapter(d))) {
+ RTW_ERR("%s: bSurpriseRemoved, skip %s 0x%05x, %zu bytes\n",
+ __FUNCTION__, write?"write":"read", addr, len);
return _FAIL;
}
+ addr_drv = addr;
+ if (cmd52)
+ addr_drv = RTW_SDIO_ADDR_CMD52_GEN(addr_drv);
+
+ do {
+ if (write)
+ err = d->intf_ops->write(d, addr_drv, buf, len, 0);
+ else
+ err = d->intf_ops->read(d, addr_drv, buf, len, 0);
+ if (!err) {
+ if (retry) {
+ RTW_INFO("%s: Retry %s OK! addr=0x%05x %zu bytes, retry=%u,%u\n",
+ __FUNCTION__, write?"write":"read",
+ addr, len, retry, ATOMIC_READ(&d->continual_io_error));
+ RTW_INFO_DUMP("Data: ", buf, len);
+ }
+ rtw_reset_continual_io_error(d);
+ break;
+ }
+ RTW_ERR("%s: %s FAIL! error(%d) addr=0x%05x %zu bytes, retry=%u,%u\n",
+ __FUNCTION__, write?"write":"read", err, addr, len,
+ retry, ATOMIC_READ(&d->continual_io_error));
+
+ retry++;
+ stop_retry = rtw_inc_and_chk_continual_io_error(d);
+ if ((err == -1) || (stop_retry == _TRUE) || (retry > SD_IO_TRY_CNT)) {
+ /* critical error, unrecoverable */
+ RTW_ERR("%s: Fatal error! Set surprise remove flag ON! (retry=%u,%u)\n",
+ __FUNCTION__, retry, ATOMIC_READ(&d->continual_io_error));
+ rtw_set_surprise_removed(dvobj_get_primary_adapter(d));
+ return _FAIL;
+ }
+
+ /* WLAN IOREG or SDIO Local */
+ if ((addr & 0x10000) || !(addr & 0xE000)) {
+ RTW_WARN("%s: Retry %s addr=0x%05x %zu bytes, retry=%u,%u\n",
+ __FUNCTION__, write?"write":"read", addr, len,
+ retry, ATOMIC_READ(&d->continual_io_error));
+ continue;
+ }
+ return _FAIL;
+ } while (1);
+
return _SUCCESS;
}
@@ -83,18 +118,13 @@ u8 rtw_sdio_f0_read(struct dvobj_priv *d, u32 addr, void *buf, size_t len)
int err;
u8 ret;
- _func_enter_;
ret = _SUCCESS;
addr = RTW_SDIO_ADDR_F0_GEN(addr);
err = d->intf_ops->read(d, addr, buf, len, 0);
- if (err) {
- RTW_INFO("%s: [ERROR] Read f0 register FAIL!\n", __FUNCTION__);
+ if (err)
ret = _FAIL;
- }
-
- _func_exit_;
return ret;
}
diff --git a/core/rtw_security.c b/core/rtw_security.c
index 5a1d0cd..318dc52 100644
--- a/core/rtw_security.c
+++ b/core/rtw_security.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,12 +11,7 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#define _RTW_SECURITY_C_
#include
@@ -125,7 +120,6 @@ static void arcfour_init(struct arc4context *parc4ctx, u8 *key, u32 key_len)
u32 stateindex;
u8 *state;
u32 counter;
- _func_enter_;
state = parc4ctx->state;
parc4ctx->x = 0;
parc4ctx->y = 0;
@@ -142,7 +136,6 @@ static void arcfour_init(struct arc4context *parc4ctx, u8 *key, u32 key_len)
if (++keyindex >= key_len)
keyindex = 0;
}
- _func_exit_;
}
static u32 arcfour_byte(struct arc4context *parc4ctx)
{
@@ -150,7 +143,6 @@ static u32 arcfour_byte(struct arc4context *parc4ctx)
u32 y;
u32 sx, sy;
u8 *state;
- _func_enter_;
state = parc4ctx->state;
x = (parc4ctx->x + 1) & 0xff;
sx = state[x];
@@ -160,7 +152,6 @@ static u32 arcfour_byte(struct arc4context *parc4ctx)
parc4ctx->y = y;
state[y] = (u8)sx;
state[x] = (u8)sy;
- _func_exit_;
return state[(sx + sy) & 0xff];
}
@@ -171,10 +162,8 @@ static void arcfour_encrypt(struct arc4context *parc4ctx,
u32 len)
{
u32 i;
- _func_enter_;
for (i = 0; i < len; i++)
dest[i] = src[i] ^ (unsigned char)arcfour_byte(parc4ctx);
- _func_exit_;
}
static sint bcrc32initialized = 0;
@@ -189,7 +178,6 @@ static u8 crc32_reverseBit(u8 data)
static void crc32_init(void)
{
- _func_enter_;
if (bcrc32initialized == 1)
goto exit;
else {
@@ -214,14 +202,13 @@ static void crc32_init(void)
bcrc32initialized = 1;
}
exit:
- _func_exit_;
+ return;
}
static u32 getcrc32(u8 *buf, sint len)
{
u8 *p;
u32 crc;
- _func_enter_;
if (bcrc32initialized == 0)
crc32_init();
@@ -229,7 +216,6 @@ static u32 getcrc32(u8 *buf, sint len)
for (p = buf; len > 0; ++p, --len)
crc = crc32_table[(crc ^ *p) & 0xff] ^ (crc >> 8);
- _func_exit_;
return ~crc; /* transmit complement, per CRC-32 spec */
}
@@ -254,7 +240,6 @@ void rtw_wep_encrypt(_adapter *padapter, u8 *pxmitframe)
struct security_priv *psecuritypriv = &padapter->securitypriv;
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
- _func_enter_;
if (((struct xmit_frame *)pxmitframe)->buf_addr == NULL)
@@ -311,7 +296,6 @@ void rtw_wep_encrypt(_adapter *padapter, u8 *pxmitframe)
WEP_SW_ENC_CNT_INC(psecuritypriv, pattrib->ra);
}
- _func_exit_;
}
@@ -327,7 +311,6 @@ void rtw_wep_decrypt(_adapter *padapter, u8 *precvframe)
struct rx_pkt_attrib *prxattrib = &(((union recv_frame *)precvframe)->u.hdr.attrib);
struct security_priv *psecuritypriv = &padapter->securitypriv;
- _func_enter_;
pframe = (unsigned char *)((union recv_frame *)precvframe)->u.hdr.rx_data;
@@ -351,16 +334,10 @@ void rtw_wep_decrypt(_adapter *padapter, u8 *precvframe)
/* calculate icv and compare the icv */
*((u32 *)crc) = le32_to_cpu(getcrc32(payload, length - 4));
- if (crc[3] != payload[length - 1] || crc[2] != payload[length - 2] || crc[1] != payload[length - 3] || crc[0] != payload[length - 4]) {
- RT_TRACE(_module_rtl871x_security_c_, _drv_err_,
- ("rtw_wep_decrypt:icv error crc[3](%x)!=payload[length-1](%x) || crc[2](%x)!=payload[length-2](%x) || crc[1](%x)!=payload[length-3](%x) || crc[0](%x)!=payload[length-4](%x)\n",
- crc[3], payload[length - 1], crc[2], payload[length - 2], crc[1], payload[length - 3], crc[0], payload[length - 4]));
- }
WEP_SW_DEC_CNT_INC(psecuritypriv, prxattrib->ra);
}
- _func_exit_;
return;
@@ -373,10 +350,8 @@ static u32 secmicgetuint32(u8 *p)
{
s32 i;
u32 res = 0;
- _func_enter_;
for (i = 0; i < 4; i++)
res |= ((u32)(*p++)) << (8 * i);
- _func_exit_;
return res;
}
@@ -384,39 +359,32 @@ static void secmicputuint32(u8 *p, u32 val)
/* Convert from Us4Byte32 to Byte[] in a portable way */
{
long i;
- _func_enter_;
for (i = 0; i < 4; i++) {
*p++ = (u8)(val & 0xff);
val >>= 8;
}
- _func_exit_;
}
static void secmicclear(struct mic_data *pmicdata)
{
/* Reset the state to the empty message. */
- _func_enter_;
pmicdata->L = pmicdata->K0;
pmicdata->R = pmicdata->K1;
pmicdata->nBytesInM = 0;
pmicdata->M = 0;
- _func_exit_;
}
void rtw_secmicsetkey(struct mic_data *pmicdata, u8 *key)
{
/* Set the key */
- _func_enter_;
pmicdata->K0 = secmicgetuint32(key);
pmicdata->K1 = secmicgetuint32(key + 4);
/* and reset the message */
secmicclear(pmicdata);
- _func_exit_;
}
void rtw_secmicappendbyte(struct mic_data *pmicdata, u8 b)
{
- _func_enter_;
/* Append the byte to our word-sized buffer */
pmicdata->M |= ((unsigned long)b) << (8 * pmicdata->nBytesInM);
pmicdata->nBytesInM++;
@@ -435,23 +403,19 @@ void rtw_secmicappendbyte(struct mic_data *pmicdata, u8 b)
pmicdata->M = 0;
pmicdata->nBytesInM = 0;
}
- _func_exit_;
}
void rtw_secmicappend(struct mic_data *pmicdata, u8 *src, u32 nbytes)
{
- _func_enter_;
/* This is simple */
while (nbytes > 0) {
rtw_secmicappendbyte(pmicdata, *src++);
nbytes--;
}
- _func_exit_;
}
void rtw_secgetmic(struct mic_data *pmicdata, u8 *dst)
{
- _func_enter_;
/* Append the minimum padding */
rtw_secmicappendbyte(pmicdata, 0x5a);
rtw_secmicappendbyte(pmicdata, 0);
@@ -466,7 +430,6 @@ void rtw_secgetmic(struct mic_data *pmicdata, u8 *dst)
secmicputuint32(dst + 4, pmicdata->R);
/* Reset to the empty message. */
secmicclear(pmicdata);
- _func_exit_;
}
@@ -475,7 +438,6 @@ void rtw_seccalctkipmic(u8 *key, u8 *header, u8 *data, u32 data_len, u8 *mic_cod
struct mic_data micdata;
u8 priority[4] = {0x0, 0x0, 0x0, 0x0};
- _func_enter_;
rtw_secmicsetkey(&micdata, key);
priority[0] = pri;
@@ -500,7 +462,6 @@ void rtw_seccalctkipmic(u8 *key, u8 *header, u8 *data, u32 data_len, u8 *mic_cod
rtw_secmicappend(&micdata, data, data_len);
rtw_secgetmic(&micdata, mic_code);
- _func_exit_;
}
@@ -622,7 +583,6 @@ static const unsigned short Sbox1[2][256] = /* Sbox for hash (can be in ROM
static void phase1(u16 *p1k, const u8 *tk, const u8 *ta, u32 iv32)
{
sint i;
- _func_enter_;
/* Initialize the 80 bits of P1K[] from IV32 and TA[0..5] */
p1k[0] = Lo16(iv32);
p1k[1] = Hi16(iv32);
@@ -641,7 +601,6 @@ static void phase1(u16 *p1k, const u8 *tk, const u8 *ta, u32 iv32)
p1k[4] += _S_(p1k[3] ^ TK16((i & 1) + 0));
p1k[4] += (unsigned short)i; /* avoid "slide attacks" */
}
- _func_exit_;
}
@@ -672,7 +631,6 @@ static void phase2(u8 *rc4key, const u8 *tk, const u16 *p1k, u16 iv16)
{
sint i;
u16 PPK[6]; /* temporary key for mixing */
- _func_enter_;
/* Note: all adds in the PPK[] equations below are mod 2**16 */
for (i = 0; i < 5; i++)
PPK[i] = p1k[i]; /* first, copy P1K to PPK */
@@ -710,7 +668,6 @@ static void phase2(u8 *rc4key, const u8 *tk, const u16 *p1k, u16 iv16)
rc4key[4 + 2 * i] = Lo8(PPK[i]);
rc4key[5 + 2 * i] = Hi8(PPK[i]);
}
- _func_exit_;
}
@@ -735,7 +692,6 @@ u32 rtw_tkip_encrypt(_adapter *padapter, u8 *pxmitframe)
struct security_priv *psecuritypriv = &padapter->securitypriv;
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
u32 res = _SUCCESS;
- _func_enter_;
if (((struct xmit_frame *)pxmitframe)->buf_addr == NULL)
return _FAIL;
@@ -775,7 +731,6 @@ u32 rtw_tkip_encrypt(_adapter *padapter, u8 *pxmitframe)
return _FAIL;
}
*/
- RT_TRACE(_module_rtl871x_security_c_, _drv_err_, ("rtw_tkip_encrypt: stainfo!=NULL!!!\n"));
if (IS_MCAST(pattrib->ra))
prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey;
@@ -801,7 +756,6 @@ u32 rtw_tkip_encrypt(_adapter *padapter, u8 *pxmitframe)
if ((curfragnum + 1) == pattrib->nr_frags) { /* 4 the last fragment */
length = pattrib->last_txcmdsz - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len;
- RT_TRACE(_module_rtl871x_security_c_, _drv_info_, ("pattrib->iv_len =%x, pattrib->icv_len =%x\n", pattrib->iv_len, pattrib->icv_len));
*((u32 *)crc) = cpu_to_le32(getcrc32(payload, length)); /* modified by Amy*/
arcfour_init(&mycontext, rc4key, 16);
@@ -825,14 +779,12 @@ u32 rtw_tkip_encrypt(_adapter *padapter, u8 *pxmitframe)
}
/*
else{
- RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_tkip_encrypt: stainfo==NULL!!!\n"));
RTW_INFO("%s, psta==NUL\n", __func__);
res=_FAIL;
}
*/
}
- _func_exit_;
return res;
}
@@ -859,7 +811,6 @@ u32 rtw_tkip_decrypt(_adapter *padapter, u8 *precvframe)
/* struct recv_priv *precvpriv=&padapter->recvpriv; */
u32 res = _SUCCESS;
- _func_enter_;
pframe = (unsigned char *)((union recv_frame *)precvframe)->u.hdr.rx_data;
@@ -870,7 +821,7 @@ u32 rtw_tkip_decrypt(_adapter *padapter, u8 *precvframe)
if (stainfo != NULL) {
if (IS_MCAST(prxattrib->ra)) {
- static u32 start = 0;
+ static systime start = 0;
static u32 no_gkey_bc_cnt = 0;
static u32 no_gkey_mc_cnt = 0;
@@ -934,20 +885,15 @@ u32 rtw_tkip_decrypt(_adapter *padapter, u8 *precvframe)
*((u32 *)crc) = le32_to_cpu(getcrc32(payload, length - 4));
if (crc[3] != payload[length - 1] || crc[2] != payload[length - 2] || crc[1] != payload[length - 3] || crc[0] != payload[length - 4]) {
- RT_TRACE(_module_rtl871x_security_c_, _drv_err_,
- ("rtw_wep_decrypt:icv error crc[3](%x)!=payload[length-1](%x) || crc[2](%x)!=payload[length-2](%x) || crc[1](%x)!=payload[length-3](%x) || crc[0](%x)!=payload[length-4](%x)\n",
- crc[3], payload[length - 1], crc[2], payload[length - 2], crc[1], payload[length - 3], crc[0], payload[length - 4]));
res = _FAIL;
}
TKIP_SW_DEC_CNT_INC(psecuritypriv, prxattrib->ra);
} else {
- RT_TRACE(_module_rtl871x_security_c_, _drv_err_, ("rtw_tkip_decrypt: stainfo==NULL!!!\n"));
res = _FAIL;
}
}
- _func_exit_;
exit:
return res;
@@ -1054,20 +1000,16 @@ static void aes128k128d(u8 *key, u8 *data, u8 *ciphertext);
static void xor_128(u8 *a, u8 *b, u8 *out)
{
sint i;
- _func_enter_;
for (i = 0; i < 16; i++)
out[i] = a[i] ^ b[i];
- _func_exit_;
}
static void xor_32(u8 *a, u8 *b, u8 *out)
{
sint i;
- _func_enter_;
for (i = 0; i < 4; i++)
out[i] = a[i] ^ b[i];
- _func_exit_;
}
@@ -1085,7 +1027,6 @@ static void next_key(u8 *key, sint round)
0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80,
0x1b, 0x36, 0x36, 0x36
};
- _func_enter_;
sbox_key[0] = sbox(key[13]);
sbox_key[1] = sbox(key[14]);
sbox_key[2] = sbox(key[15]);
@@ -1099,23 +1040,19 @@ static void next_key(u8 *key, sint round)
xor_32(&key[4], &key[0], &key[4]);
xor_32(&key[8], &key[4], &key[8]);
xor_32(&key[12], &key[8], &key[12]);
- _func_exit_;
}
static void byte_sub(u8 *in, u8 *out)
{
sint i;
- _func_enter_;
for (i = 0; i < 16; i++)
out[i] = sbox(in[i]);
- _func_exit_;
}
static void shift_row(u8 *in, u8 *out)
{
- _func_enter_;
out[0] = in[0];
out[1] = in[5];
out[2] = in[10];
@@ -1132,7 +1069,6 @@ static void shift_row(u8 *in, u8 *out)
out[13] = in[1];
out[14] = in[6];
out[15] = in[11];
- _func_exit_;
}
@@ -1147,7 +1083,6 @@ static void mix_column(u8 *in, u8 *out)
u8 rotr[4];
u8 temp[4];
u8 tempb[4];
- _func_enter_;
for (i = 0 ; i < 4; i++) {
if ((in[i] & 0x80) == 0x80)
add1b[i] = 0x1b;
@@ -1191,7 +1126,6 @@ static void mix_column(u8 *in, u8 *out)
xor_32(add1bf7, rotr, temp);
xor_32(swap_halfs, rotl, tempb);
xor_32(temp, tempb, out);
- _func_exit_;
}
@@ -1202,7 +1136,6 @@ static void aes128k128d(u8 *key, u8 *data, u8 *ciphertext)
u8 intermediatea[16];
u8 intermediateb[16];
u8 round_key[16];
- _func_enter_;
for (i = 0; i < 16; i++)
round_key[i] = key[i];
@@ -1225,7 +1158,6 @@ static void aes128k128d(u8 *key, u8 *data, u8 *ciphertext)
next_key(round_key, round);
}
}
- _func_exit_;
}
@@ -1246,7 +1178,6 @@ static void construct_mic_iv(
)
{
sint i;
- _func_enter_;
mic_iv[0] = 0x59;
if (qc_exists && a4_exists)
mic_iv[1] = mpdu[30] & 0x0f; /* QoS_TC */
@@ -1254,11 +1185,11 @@ static void construct_mic_iv(
mic_iv[1] = mpdu[24] & 0x0f; /* mute bits 7-4 */
if (!qc_exists)
mic_iv[1] = 0x00;
-#ifdef CONFIG_IEEE80211W
+#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)
/* 802.11w management frame should set management bit(4) */
if (frtype == WIFI_MGT_TYPE)
mic_iv[1] |= BIT(4);
-#endif /* CONFIG_IEEE80211W */
+#endif
for (i = 2; i < 8; i++)
mic_iv[i] = mpdu[i + 8]; /* mic_iv[2:7] = A2[0:5] = mpdu[10:15] */
#ifdef CONSISTENT_PN_ORDER
@@ -1270,7 +1201,6 @@ static void construct_mic_iv(
#endif
mic_iv[14] = (unsigned char)(payload_length / 256);
mic_iv[15] = (unsigned char)(payload_length % 256);
- _func_exit_;
}
@@ -1287,15 +1217,14 @@ static void construct_mic_header1(
uint frtype/* add for CONFIG_IEEE80211W, none 11w also can use */
)
{
- _func_enter_;
mic_header1[0] = (u8)((header_length - 2) / 256);
mic_header1[1] = (u8)((header_length - 2) % 256);
-#ifdef CONFIG_IEEE80211W
+#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)
/* 802.11w management frame don't AND subtype bits 4,5,6 of frame control field */
if (frtype == WIFI_MGT_TYPE)
mic_header1[2] = mpdu[0];
else
-#endif /* CONFIG_IEEE80211W */
+#endif
mic_header1[2] = mpdu[0] & 0xcf; /* Mute CF poll & CF ack bits */
mic_header1[3] = mpdu[1] & 0xc7; /* Mute retry, more data and pwr mgt bits */
@@ -1311,7 +1240,6 @@ static void construct_mic_header1(
mic_header1[13] = mpdu[13];
mic_header1[14] = mpdu[14];
mic_header1[15] = mpdu[15];
- _func_exit_;
}
@@ -1328,7 +1256,6 @@ static void construct_mic_header2(
)
{
sint i;
- _func_enter_;
for (i = 0; i < 16; i++)
mic_header2[i] = 0x00;
@@ -1363,7 +1290,6 @@ static void construct_mic_header2(
mic_header2[15] = mpdu[31] & 0x00;
}
- _func_exit_;
}
@@ -1385,7 +1311,6 @@ static void construct_ctr_preload(
)
{
sint i = 0;
- _func_enter_;
for (i = 0; i < 16; i++)
ctr_preload[i] = 0x00;
i = 0;
@@ -1395,11 +1320,11 @@ static void construct_ctr_preload(
ctr_preload[1] = mpdu[30] & 0x0f; /* QoC_Control */
if (qc_exists && !a4_exists)
ctr_preload[1] = mpdu[24] & 0x0f;
-#ifdef CONFIG_IEEE80211W
+#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)
/* 802.11w management frame should set management bit(4) */
if (frtype == WIFI_MGT_TYPE)
ctr_preload[1] |= BIT(4);
-#endif /* CONFIG_IEEE80211W */
+#endif
for (i = 2; i < 8; i++)
ctr_preload[i] = mpdu[i + 8]; /* ctr_preload[2:7] = A2[0:5] = mpdu[10:15] */
#ifdef CONSISTENT_PN_ORDER
@@ -1411,7 +1336,6 @@ static void construct_ctr_preload(
#endif
ctr_preload[14] = (unsigned char)(c / 256); /* Ctr */
ctr_preload[15] = (unsigned char)(c % 256);
- _func_exit_;
}
@@ -1422,10 +1346,8 @@ static void construct_ctr_preload(
static void bitwise_xor(u8 *ina, u8 *inb, u8 *out)
{
sint i;
- _func_enter_;
for (i = 0; i < 16; i++)
out[i] = ina[i] ^ inb[i];
- _func_exit_;
}
@@ -1449,9 +1371,8 @@ static sint aes_cipher(u8 *key, uint hdrlen,
u8 mic[8];
/* uint offset = 0; */
uint frtype = GetFrameType(pframe);
- uint frsubtype = GetFrameSubType(pframe);
+ uint frsubtype = get_frame_sub_type(pframe);
- _func_enter_;
frsubtype = frsubtype >> 4;
@@ -1473,8 +1394,7 @@ static sint aes_cipher(u8 *key, uint hdrlen,
((frtype | frsubtype) == WIFI_DATA_CFPOLL) ||
((frtype | frsubtype) == WIFI_DATA_CFACKPOLL)) {
qc_exists = 1;
- if (hdrlen != WLAN_HDR_A3_QOS_LEN)
-
+ if (hdrlen != WLAN_HDR_A3_QOS_LEN && hdrlen != WLAN_HDR_A4_QOS_LEN)
hdrlen += 2;
}
/* add for CONFIG_IEEE80211W, none 11w also can use */
@@ -1483,8 +1403,7 @@ static sint aes_cipher(u8 *key, uint hdrlen,
(frsubtype == 0x09) ||
(frsubtype == 0x0a) ||
(frsubtype == 0x0b))) {
- if (hdrlen != WLAN_HDR_A3_QOS_LEN)
-
+ if (hdrlen != WLAN_HDR_A3_QOS_LEN && hdrlen != WLAN_HDR_A4_QOS_LEN)
hdrlen += 2;
qc_exists = 1;
} else
@@ -1618,7 +1537,6 @@ static sint aes_cipher(u8 *key, uint hdrlen,
bitwise_xor(aes_out, padded_buffer, chain_buffer);
for (j = 0; j < 8; j++)
pframe[payload_index++] = chain_buffer[j];/* for (j=0; j<8;j++) message[payload_index++] = chain_buffer[j]; */
- _func_exit_;
return _SUCCESS;
}
@@ -1646,7 +1564,6 @@ u32 rtw_aes_encrypt(_adapter *padapter, u8 *pxmitframe)
/* uint offset = 0; */
u32 res = _SUCCESS;
- _func_enter_;
if (((struct xmit_frame *)pxmitframe)->buf_addr == NULL)
return _FAIL;
@@ -1686,7 +1603,6 @@ u32 rtw_aes_encrypt(_adapter *padapter, u8 *pxmitframe)
return _FAIL;
}
*/
- RT_TRACE(_module_rtl871x_security_c_, _drv_err_, ("rtw_aes_encrypt: stainfo!=NULL!!!\n"));
if (IS_MCAST(pattrib->ra))
prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey;
@@ -1729,7 +1645,6 @@ u32 rtw_aes_encrypt(_adapter *padapter, u8 *pxmitframe)
}
/*
else{
- RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_aes_encrypt: stainfo==NULL!!!\n"));
RTW_INFO("%s, psta==NUL\n", __func__);
res=_FAIL;
}
@@ -1738,7 +1653,6 @@ u32 rtw_aes_encrypt(_adapter *padapter, u8 *pxmitframe)
- _func_exit_;
return res;
}
@@ -1764,8 +1678,7 @@ static sint aes_decipher(u8 *key, uint hdrlen,
/* uint offset = 0; */
uint frtype = GetFrameType(pframe);
- uint frsubtype = GetFrameSubType(pframe);
- _func_enter_;
+ uint frsubtype = get_frame_sub_type(pframe);
frsubtype = frsubtype >> 4;
@@ -1800,8 +1713,7 @@ static sint aes_decipher(u8 *key, uint hdrlen,
((frtype | frsubtype) == WIFI_DATA_CFPOLL) ||
((frtype | frsubtype) == WIFI_DATA_CFACKPOLL)) {
qc_exists = 1;
- if (hdrlen != WLAN_HDR_A3_QOS_LEN)
-
+ if (hdrlen != WLAN_HDR_A3_QOS_LEN && hdrlen != WLAN_HDR_A4_QOS_LEN)
hdrlen += 2;
} /* only for data packet . add for CONFIG_IEEE80211W, none 11w also can use */
else if ((frtype == WIFI_DATA) &&
@@ -1809,8 +1721,7 @@ static sint aes_decipher(u8 *key, uint hdrlen,
(frsubtype == 0x09) ||
(frsubtype == 0x0a) ||
(frsubtype == 0x0b))) {
- if (hdrlen != WLAN_HDR_A3_QOS_LEN)
-
+ if (hdrlen != WLAN_HDR_A3_QOS_LEN && hdrlen != WLAN_HDR_A4_QOS_LEN)
hdrlen += 2;
qc_exists = 1;
} else
@@ -1997,14 +1908,11 @@ static sint aes_decipher(u8 *key, uint hdrlen,
/* compare the mic */
for (i = 0; i < 8; i++) {
if (pframe[hdrlen + 8 + plen - 8 + i] != message[hdrlen + 8 + plen - 8 + i]) {
- RT_TRACE(_module_rtl871x_security_c_, _drv_err_, ("aes_decipher:mic check error mic[%d]: pframe(%x) != message(%x)\n",
- i, pframe[hdrlen + 8 + plen - 8 + i], message[hdrlen + 8 + plen - 8 + i]));
RTW_INFO("aes_decipher:mic check error mic[%d]: pframe(%x) != message(%x)\n",
i, pframe[hdrlen + 8 + plen - 8 + i], message[hdrlen + 8 + plen - 8 + i]);
res = _FAIL;
}
}
- _func_exit_;
return res;
}
@@ -2028,23 +1936,25 @@ u32 rtw_aes_decrypt(_adapter *padapter, u8 *precvframe)
struct security_priv *psecuritypriv = &padapter->securitypriv;
/* struct recv_priv *precvpriv=&padapter->recvpriv; */
u32 res = _SUCCESS;
- _func_enter_;
pframe = (unsigned char *)((union recv_frame *)precvframe)->u.hdr.rx_data;
/* 4 start to encrypt each fragment */
if ((prxattrib->encrypt == _AES_)) {
stainfo = rtw_get_stainfo(&padapter->stapriv , &prxattrib->ta[0]);
if (stainfo != NULL) {
- RT_TRACE(_module_rtl871x_security_c_, _drv_err_, ("rtw_aes_decrypt: stainfo!=NULL!!!\n"));
if (IS_MCAST(prxattrib->ra)) {
- static u32 start = 0;
+ static systime start = 0;
static u32 no_gkey_bc_cnt = 0;
static u32 no_gkey_mc_cnt = 0;
/* RTW_INFO("rx bc/mc packets, to perform sw rtw_aes_decrypt\n"); */
/* prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey; */
- if (psecuritypriv->binstallGrpkey == _FALSE) {
+ if ((!MLME_IS_MESH(padapter) && psecuritypriv->binstallGrpkey == _FALSE)
+ #ifdef CONFIG_RTW_MESH
+ || !(stainfo->gtk_bmp | BIT(prxattrib->key_index))
+ #endif
+ ) {
res = _FAIL;
if (start == 0)
@@ -2076,12 +1986,20 @@ u32 rtw_aes_decrypt(_adapter *padapter, u8 *precvframe)
no_gkey_bc_cnt = 0;
no_gkey_mc_cnt = 0;
- prwskey = psecuritypriv->dot118021XGrpKey[prxattrib->key_index].skey;
- if (psecuritypriv->dot118021XGrpKeyid != prxattrib->key_index) {
- RTW_INFO("not match packet_index=%d, install_index=%d\n"
- , prxattrib->key_index, psecuritypriv->dot118021XGrpKeyid);
- res = _FAIL;
- goto exit;
+ #ifdef CONFIG_RTW_MESH
+ if (MLME_IS_MESH(padapter)) {
+ /* TODO: multiple GK? */
+ prwskey = &stainfo->gtk.skey[0];
+ } else
+ #endif
+ {
+ prwskey = psecuritypriv->dot118021XGrpKey[prxattrib->key_index].skey;
+ if (psecuritypriv->dot118021XGrpKeyid != prxattrib->key_index) {
+ RTW_DBG("not match packet_index=%d, install_index=%d\n"
+ , prxattrib->key_index, psecuritypriv->dot118021XGrpKeyid);
+ res = _FAIL;
+ goto exit;
+ }
}
} else
prwskey = &stainfo->dot118021x_UncstKey.skey[0];
@@ -2114,105 +2032,105 @@ u32 rtw_aes_decrypt(_adapter *padapter, u8 *precvframe)
AES_SW_DEC_CNT_INC(psecuritypriv, prxattrib->ra);
} else {
- RT_TRACE(_module_rtl871x_security_c_, _drv_err_, ("rtw_aes_decrypt: stainfo==NULL!!!\n"));
res = _FAIL;
}
}
- _func_exit_;
exit:
return res;
}
#ifdef CONFIG_IEEE80211W
-u32 rtw_BIP_verify(_adapter *padapter, u8 *precvframe)
+u32 rtw_BIP_verify(_adapter *padapter, u8 *whdr_pos, sint flen
+ , const u8 *key, u16 keyid, u64* ipn)
{
- struct rx_pkt_attrib *pattrib = &((union recv_frame *)precvframe)->u.hdr.attrib;
- u8 *pframe;
- u8 *BIP_AAD, *p;
+ u8 *BIP_AAD, *mme;
u32 res = _FAIL;
uint len, ori_len;
+ u16 pkt_keyid = 0;
+ u64 pkt_ipn = 0;
struct rtw_ieee80211_hdr *pwlanhdr;
u8 mic[16];
- struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
- ori_len = pattrib->pkt_len - WLAN_HDR_A3_LEN + BIP_AAD_SIZE;
- BIP_AAD = rtw_zmalloc(ori_len);
+ mme = whdr_pos + flen - 18;
+ if (*mme != _MME_IE_)
+ return RTW_RX_HANDLED;
+
+ /* copy key index */
+ _rtw_memcpy(&pkt_keyid, mme + 2, 2);
+ pkt_keyid = le16_to_cpu(pkt_keyid);
+ if (pkt_keyid != keyid) {
+ RTW_INFO("BIP key index error!\n");
+ return _FAIL;
+ }
+
+ /* save packet number */
+ _rtw_memcpy(&pkt_ipn, mme + 4, 6);
+ pkt_ipn = le64_to_cpu(pkt_ipn);
+ /* BIP packet number should bigger than previous BIP packet */
+ if (pkt_ipn <= *ipn) { /* wrap around? */
+ RTW_INFO("replay BIP packet\n");
+ return _FAIL;
+ }
+
+ ori_len = flen - WLAN_HDR_A3_LEN + BIP_AAD_SIZE;
+ BIP_AAD = rtw_zmalloc(ori_len);
if (BIP_AAD == NULL) {
RTW_INFO("BIP AAD allocate fail\n");
return _FAIL;
}
- /* PKT start */
- pframe = (unsigned char *)((union recv_frame *)precvframe)->u.hdr.rx_data;
+
/* mapping to wlan header */
- pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+ pwlanhdr = (struct rtw_ieee80211_hdr *)whdr_pos;
+
/* save the frame body + MME */
- _rtw_memcpy(BIP_AAD + BIP_AAD_SIZE, pframe + WLAN_HDR_A3_LEN, pattrib->pkt_len - WLAN_HDR_A3_LEN);
- /* find MME IE pointer */
- p = rtw_get_ie(BIP_AAD + BIP_AAD_SIZE, _MME_IE_, &len, pattrib->pkt_len - WLAN_HDR_A3_LEN);
- /* Baron */
- if (p) {
- u16 keyid = 0;
- u64 temp_ipn = 0;
- /* save packet number */
- _rtw_memcpy(&temp_ipn, p + 4, 6);
- temp_ipn = le64_to_cpu(temp_ipn);
- /* BIP packet number should bigger than previous BIP packet */
- if (temp_ipn < pmlmeext->mgnt_80211w_IPN_rx) {
- RTW_INFO("replay BIP packet\n");
- goto BIP_exit;
- }
- /* copy key index */
- _rtw_memcpy(&keyid, p + 2, 2);
- keyid = le16_to_cpu(keyid);
- if (keyid != padapter->securitypriv.dot11wBIPKeyid) {
- RTW_INFO("BIP key index error!\n");
- goto BIP_exit;
- }
- /* clear the MIC field of MME to zero */
- _rtw_memset(p + 2 + len - 8, 0, 8);
+ _rtw_memcpy(BIP_AAD + BIP_AAD_SIZE, whdr_pos + WLAN_HDR_A3_LEN, flen - WLAN_HDR_A3_LEN);
+
+ /* point mme to the copy */
+ mme = BIP_AAD + ori_len - 18;
- /* conscruct AAD, copy frame control field */
- _rtw_memcpy(BIP_AAD, &pwlanhdr->frame_ctl, 2);
- ClearRetry(BIP_AAD);
- ClearPwrMgt(BIP_AAD);
- ClearMData(BIP_AAD);
- /* conscruct AAD, copy address 1 to address 3 */
- _rtw_memcpy(BIP_AAD + 2, pwlanhdr->addr1, 18);
+ /* clear the MIC field of MME to zero */
+ _rtw_memset(mme + 10, 0, 8);
- if (omac1_aes_128(padapter->securitypriv.dot11wBIPKey[padapter->securitypriv.dot11wBIPKeyid].skey
- , BIP_AAD, ori_len, mic))
- goto BIP_exit;
+ /* conscruct AAD, copy frame control field */
+ _rtw_memcpy(BIP_AAD, &pwlanhdr->frame_ctl, 2);
+ ClearRetry(BIP_AAD);
+ ClearPwrMgt(BIP_AAD);
+ ClearMData(BIP_AAD);
+ /* conscruct AAD, copy address 1 to address 3 */
+ _rtw_memcpy(BIP_AAD + 2, pwlanhdr->addr1, 18);
+
+ if (omac1_aes_128(key, BIP_AAD, ori_len, mic))
+ goto BIP_exit;
#if 0
- /* management packet content */
- {
- int pp;
- RTW_INFO("pkt: ");
- for (pp = 0; pp < pattrib->pkt_len; pp++)
- printk(" %02x ", pframe[pp]);
- RTW_INFO("\n");
- /* BIP AAD + management frame body + MME(MIC is zero) */
- RTW_INFO("AAD+PKT: ");
- for (pp = 0; pp < ori_len; pp++)
- RTW_INFO(" %02x ", BIP_AAD[pp]);
- RTW_INFO("\n");
- /* show the MIC result */
- RTW_INFO("mic: ");
- for (pp = 0; pp < 16; pp++)
- RTW_INFO(" %02x ", mic[pp]);
- RTW_INFO("\n");
- }
+ /* management packet content */
+ {
+ int pp;
+ RTW_INFO("pkt: ");
+ for (pp = 0; pp < flen; pp++)
+ printk(" %02x ", whdr_pos[pp]);
+ RTW_INFO("\n");
+ /* BIP AAD + management frame body + MME(MIC is zero) */
+ RTW_INFO("AAD+PKT: ");
+ for (pp = 0; pp < ori_len; pp++)
+ RTW_INFO(" %02x ", BIP_AAD[pp]);
+ RTW_INFO("\n");
+ /* show the MIC result */
+ RTW_INFO("mic: ");
+ for (pp = 0; pp < 16; pp++)
+ RTW_INFO(" %02x ", mic[pp]);
+ RTW_INFO("\n");
+ }
#endif
- /* MIC field should be last 8 bytes of packet (packet without FCS) */
- if (_rtw_memcmp(mic, pframe + pattrib->pkt_len - 8, 8)) {
- pmlmeext->mgnt_80211w_IPN_rx = temp_ipn;
- res = _SUCCESS;
- } else
- RTW_INFO("BIP MIC error!\n");
+ /* MIC field should be last 8 bytes of packet (packet without FCS) */
+ if (_rtw_memcmp(mic, whdr_pos + flen - 8, 8)) {
+ *ipn = pkt_ipn;
+ res = _SUCCESS;
} else
- res = RTW_RX_HANDLED;
+ RTW_INFO("BIP MIC error!\n");
+
BIP_exit:
rtw_mfree(BIP_AAD, ori_len);
@@ -2222,6 +2140,7 @@ u32 rtw_BIP_verify(_adapter *padapter, u8 *precvframe)
#ifndef PLATFORM_FREEBSD
/* compress 512-bits */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0))
static int sha256_compress(struct sha256_state *md, unsigned char *buf)
{
u32 S[8], W[64], t0, t1;
@@ -2268,8 +2187,10 @@ static int sha256_compress(struct sha256_state *md, unsigned char *buf)
md->state[i] = md->state[i] + S[i];
return 0;
}
+#endif
/* Initialize the hash state */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0))
static void sha256_init(struct sha256_state *md)
{
md->curlen = 0;
@@ -2283,6 +2204,7 @@ static void sha256_init(struct sha256_state *md)
md->state[6] = 0x1F83D9ABUL;
md->state[7] = 0x5BE0CD19UL;
}
+#endif
/**
Process a block of memory though the hash
@@ -2291,13 +2213,14 @@ static void sha256_init(struct sha256_state *md)
@param inlen The length of the data (octets)
@return CRYPT_OK if successful
*/
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0))
static int sha256_process(struct sha256_state *md, unsigned char *in,
unsigned long inlen)
{
unsigned long n;
#define block_size 64
- if (md->curlen > sizeof(md->buf))
+ if (md->curlen >= sizeof(md->buf))
return -1;
while (inlen > 0) {
@@ -2324,6 +2247,7 @@ static int sha256_process(struct sha256_state *md, unsigned char *in,
return 0;
}
+#endif
/**
@@ -2332,6 +2256,7 @@ static int sha256_process(struct sha256_state *md, unsigned char *in,
@param out [out] The destination of the hash (32 bytes)
@return CRYPT_OK if successful
*/
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0))
static int sha256_done(struct sha256_state *md, unsigned char *out)
{
int i;
@@ -2370,6 +2295,7 @@ static int sha256_done(struct sha256_state *md, unsigned char *out)
return 0;
}
+#endif
/**
* sha256_vector - SHA256 hash for data vector
@@ -2379,6 +2305,7 @@ static int sha256_done(struct sha256_state *md, unsigned char *out)
* @mac: Buffer for the hash
* Returns: 0 on success, -1 of failure
*/
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0))
static int sha256_vector(size_t num_elem, u8 *addr[], size_t *len,
u8 *mac)
{
@@ -2393,6 +2320,7 @@ static int sha256_vector(size_t num_elem, u8 *addr[], size_t *len,
return -1;
return 0;
}
+#endif
static u8 os_strlen(const char *s)
{
@@ -2402,9 +2330,9 @@ static u8 os_strlen(const char *s)
return p - s;
}
-static int os_memcmp(void *s1, void *s2, u8 n)
+static int os_memcmp(const void *s1, const void *s2, u8 n)
{
- unsigned char *p1 = s1, *p2 = s2;
+ const unsigned char *p1 = s1, *p2 = s2;
if (n == 0)
return 0;
@@ -2429,6 +2357,7 @@ static int os_memcmp(void *s1, void *s2, u8 n)
* @len: Lengths of the data blocks
* @mac: Buffer for the hash (32 bytes)
*/
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0))
static void hmac_sha256_vector(u8 *key, size_t key_len, size_t num_elem,
u8 *addr[], size_t *len, u8 *mac)
{
@@ -2505,6 +2434,7 @@ static void hmac_sha256_vector(u8 *key, size_t key_len, size_t num_elem,
* given key.
*/
#ifndef PLATFORM_FREEBSD /* Baron */
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0))
static void sha256_prf(u8 *key, size_t key_len, char *label,
u8 *data, size_t data_len, u8 *buf, size_t buf_len)
{
@@ -2541,6 +2471,7 @@ static void sha256_prf(u8 *key, size_t key_len, char *label,
counter++;
}
}
+#endif
#endif /* PLATFORM_FREEBSD Baron */
/* AES tables*/
@@ -2810,7 +2741,7 @@ static void rijndaelEncrypt(u32 rk[/*44*/], u8 pt[16], u8 ct[16])
PUTU32(ct + 12, s3);
}
-static void *aes_encrypt_init(u8 *key, size_t len)
+static void *aes_encrypt_init(const u8 *key, size_t len)
{
u32 *rk;
if (len != 16)
@@ -2860,12 +2791,12 @@ static void aes_encrypt_deinit(void *ctx)
* OMAC1 was standardized with the name CMAC by NIST in a Special Publication
* (SP) 800-38B.
*/
-static int omac1_aes_128_vector(u8 *key, size_t num_elem,
- u8 *addr[], size_t *len, u8 *mac)
+static int omac1_aes_128_vector(const u8 *key, size_t num_elem,
+ const u8 *addr[], const size_t *len, u8 *mac)
{
void *ctx;
u8 cbc[AES_BLOCK_SIZE], pad[AES_BLOCK_SIZE];
- u8 *pos, *end;
+ const u8 *pos, *end;
size_t i, e, left, total_len;
ctx = aes_encrypt_init(key, 16);
@@ -2933,12 +2864,237 @@ static int omac1_aes_128_vector(u8 *key, size_t num_elem,
* OMAC1 was standardized with the name CMAC by NIST in a Special Publication
* (SP) 800-38B.
*/ /* modify for CONFIG_IEEE80211W */
-int omac1_aes_128(u8 *key, u8 *data, size_t data_len, u8 *mac)
+int omac1_aes_128(const u8 *key, const u8 *data, size_t data_len, u8 *mac)
{
return omac1_aes_128_vector(key, 1, &data, &data_len, mac);
}
#endif /* PLATFORM_FREEBSD Baron */
+#ifdef CONFIG_RTW_MESH_AEK
+/* for AES-SIV */
+#define os_memset _rtw_memset
+#define os_memcpy _rtw_memcpy
+#define os_malloc rtw_malloc
+#define bin_clear_free(bin, len) \
+ do { \
+ if (bin) { \
+ os_memset(bin, 0, len); \
+ rtw_mfree(bin, len); \
+ } \
+ } while (0)
+
+static const u8 zero[AES_BLOCK_SIZE];
+
+static void dbl(u8 *pad)
+{
+ int i, carry;
+
+ carry = pad[0] & 0x80;
+ for (i = 0; i < AES_BLOCK_SIZE - 1; i++)
+ pad[i] = (pad[i] << 1) | (pad[i + 1] >> 7);
+ pad[AES_BLOCK_SIZE - 1] <<= 1;
+ if (carry)
+ pad[AES_BLOCK_SIZE - 1] ^= 0x87;
+}
+
+static void xor(u8 *a, const u8 *b)
+{
+ int i;
+
+ for (i = 0; i < AES_BLOCK_SIZE; i++)
+ *a++ ^= *b++;
+}
+
+static void xorend(u8 *a, int alen, const u8 *b, int blen)
+{
+ int i;
+
+ if (alen < blen)
+ return;
+
+ for (i = 0; i < blen; i++)
+ a[alen - blen + i] ^= b[i];
+}
+
+static void pad_block(u8 *pad, const u8 *addr, size_t len)
+{
+ os_memset(pad, 0, AES_BLOCK_SIZE);
+ os_memcpy(pad, addr, len);
+
+ if (len < AES_BLOCK_SIZE)
+ pad[len] = 0x80;
+}
+
+static int aes_s2v(const u8 *key, size_t num_elem, const u8 *addr[],
+ size_t *len, u8 *mac)
+{
+ u8 tmp[AES_BLOCK_SIZE], tmp2[AES_BLOCK_SIZE];
+ u8 *buf = NULL;
+ int ret;
+ size_t i;
+
+ if (!num_elem) {
+ os_memcpy(tmp, zero, sizeof(zero));
+ tmp[AES_BLOCK_SIZE - 1] = 1;
+ return omac1_aes_128(key, tmp, sizeof(tmp), mac);
+ }
+
+ ret = omac1_aes_128(key, zero, sizeof(zero), tmp);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < num_elem - 1; i++) {
+ ret = omac1_aes_128(key, addr[i], len[i], tmp2);
+ if (ret)
+ return ret;
+
+ dbl(tmp);
+ xor(tmp, tmp2);
+ }
+ if (len[i] >= AES_BLOCK_SIZE) {
+ buf = os_malloc(len[i]);
+ if (!buf)
+ return -ENOMEM;
+
+ os_memcpy(buf, addr[i], len[i]);
+ xorend(buf, len[i], tmp, AES_BLOCK_SIZE);
+ ret = omac1_aes_128(key, buf, len[i], mac);
+ bin_clear_free(buf, len[i]);
+ return ret;
+ }
+
+ dbl(tmp);
+ pad_block(tmp2, addr[i], len[i]);
+ xor(tmp, tmp2);
+
+ return omac1_aes_128(key, tmp, sizeof(tmp), mac);
+}
+
+/**
+ * aes_128_ctr_encrypt - AES-128 CTR mode encryption
+ * @key: Key for encryption (16 bytes)
+ * @nonce: Nonce for counter mode (16 bytes)
+ * @data: Data to encrypt in-place
+ * @data_len: Length of data in bytes
+ * Returns: 0 on success, -1 on failure
+ */
+int aes_128_ctr_encrypt(const u8 *key, const u8 *nonce,
+ u8 *data, size_t data_len)
+{
+ void *ctx;
+ size_t j, len, left = data_len;
+ int i;
+ u8 *pos = data;
+ u8 counter[AES_BLOCK_SIZE], buf[AES_BLOCK_SIZE];
+
+ ctx = aes_encrypt_init(key, 16);
+ if (ctx == NULL)
+ return -1;
+ os_memcpy(counter, nonce, AES_BLOCK_SIZE);
+
+ while (left > 0) {
+ #if 0
+ aes_encrypt(ctx, counter, buf);
+ #else
+ aes_128_encrypt(ctx, counter, buf);
+ #endif
+
+ len = (left < AES_BLOCK_SIZE) ? left : AES_BLOCK_SIZE;
+ for (j = 0; j < len; j++)
+ pos[j] ^= buf[j];
+ pos += len;
+ left -= len;
+
+ for (i = AES_BLOCK_SIZE - 1; i >= 0; i--) {
+ counter[i]++;
+ if (counter[i])
+ break;
+ }
+ }
+ aes_encrypt_deinit(ctx);
+ return 0;
+}
+
+int aes_siv_encrypt(const u8 *key, const u8 *pw,
+ size_t pwlen, size_t num_elem,
+ const u8 *addr[], const size_t *len, u8 *out)
+{
+ const u8 *_addr[6];
+ size_t _len[6];
+ const u8 *k1 = key, *k2 = key + 16;
+ u8 v[AES_BLOCK_SIZE];
+ size_t i;
+ u8 *iv, *crypt_pw;
+
+ if (num_elem > ARRAY_SIZE(_addr) - 1)
+ return -1;
+
+ for (i = 0; i < num_elem; i++) {
+ _addr[i] = addr[i];
+ _len[i] = len[i];
+ }
+ _addr[num_elem] = pw;
+ _len[num_elem] = pwlen;
+
+ if (aes_s2v(k1, num_elem + 1, _addr, _len, v))
+ return -1;
+
+ iv = out;
+ crypt_pw = out + AES_BLOCK_SIZE;
+
+ os_memcpy(iv, v, AES_BLOCK_SIZE);
+ os_memcpy(crypt_pw, pw, pwlen);
+
+ /* zero out 63rd and 31st bits of ctr (from right) */
+ v[8] &= 0x7f;
+ v[12] &= 0x7f;
+ return aes_128_ctr_encrypt(k2, v, crypt_pw, pwlen);
+}
+
+int aes_siv_decrypt(const u8 *key, const u8 *iv_crypt, size_t iv_c_len,
+ size_t num_elem, const u8 *addr[], const size_t *len,
+ u8 *out)
+{
+ const u8 *_addr[6];
+ size_t _len[6];
+ const u8 *k1 = key, *k2 = key + 16;
+ size_t crypt_len;
+ size_t i;
+ int ret;
+ u8 iv[AES_BLOCK_SIZE];
+ u8 check[AES_BLOCK_SIZE];
+
+ if (iv_c_len < AES_BLOCK_SIZE || num_elem > ARRAY_SIZE(_addr) - 1)
+ return -1;
+ crypt_len = iv_c_len - AES_BLOCK_SIZE;
+
+ for (i = 0; i < num_elem; i++) {
+ _addr[i] = addr[i];
+ _len[i] = len[i];
+ }
+ _addr[num_elem] = out;
+ _len[num_elem] = crypt_len;
+
+ os_memcpy(iv, iv_crypt, AES_BLOCK_SIZE);
+ os_memcpy(out, iv_crypt + AES_BLOCK_SIZE, crypt_len);
+
+ iv[8] &= 0x7f;
+ iv[12] &= 0x7f;
+
+ ret = aes_128_ctr_encrypt(k2, iv, out, crypt_len);
+ if (ret)
+ return ret;
+
+ ret = aes_s2v(k1, num_elem + 1, _addr, _len, check);
+ if (ret)
+ return ret;
+ if (os_memcmp(check, iv_crypt, AES_BLOCK_SIZE) == 0)
+ return 0;
+
+ return -1;
+}
+#endif /* CONFIG_RTW_MESH_AEK */
+
#ifdef CONFIG_TDLS
void wpa_tdls_generate_tpk(_adapter *padapter, PVOID sta)
{
@@ -2975,11 +3131,11 @@ void wpa_tdls_generate_tpk(_adapter *padapter, PVOID sta)
* added by the KDF anyway..
*/
- if (os_memcmp(adapter_mac_addr(padapter), psta->hwaddr, ETH_ALEN) < 0) {
+ if (os_memcmp(adapter_mac_addr(padapter), psta->cmn.mac_addr, ETH_ALEN) < 0) {
_rtw_memcpy(data, adapter_mac_addr(padapter), ETH_ALEN);
- _rtw_memcpy(data + ETH_ALEN, psta->hwaddr, ETH_ALEN);
+ _rtw_memcpy(data + ETH_ALEN, psta->cmn.mac_addr, ETH_ALEN);
} else {
- _rtw_memcpy(data, psta->hwaddr, ETH_ALEN);
+ _rtw_memcpy(data, psta->cmn.mac_addr, ETH_ALEN);
_rtw_memcpy(data + ETH_ALEN, adapter_mac_addr(padapter), ETH_ALEN);
}
_rtw_memcpy(data + 2 * ETH_ALEN, get_bssid(pmlmepriv), ETH_ALEN);
@@ -3156,34 +3312,9 @@ int tdls_verify_mic(u8 *kck, u8 trans_seq,
return _FAIL;
}
+#endif
#endif /* CONFIG_TDLS */
-void rtw_use_tkipkey_handler(RTW_TIMER_HDL_ARGS)
-{
- _adapter *padapter = (_adapter *)FunctionContext;
-
- _func_enter_;
-
- RT_TRACE(_module_rtl871x_security_c_, _drv_err_, ("^^^rtw_use_tkipkey_handler ^^^\n"));
-
- /*
- if (RTW_CANNOT_RUN(padapter)) {
- RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("^^^rtw_use_tkipkey_handler (padapter->bDriverStopped %s)(padapter->bSurpriseRemoved %s)^^^\n"
- , rtw_is_drv_stopped(padapter)?"True":"False"
- , rtw_is_surprise_removed(padapter)?"True":"False"));
-
- return;
- }
- */
-
- padapter->securitypriv.busetkipkey = _TRUE;
-
- RT_TRACE(_module_rtl871x_security_c_, _drv_err_, ("^^^rtw_use_tkipkey_handler padapter->securitypriv.busetkipkey=%d^^^\n", padapter->securitypriv.busetkipkey));
-
- _func_exit_;
-
-}
-
/* Restore HW wep key setting according to key_mask */
void rtw_sec_restore_wep_key(_adapter *adapter)
{
diff --git a/core/rtw_sreset.c b/core/rtw_sreset.c
index 00f81d9..09558ed 100644
--- a/core/rtw_sreset.c
+++ b/core/rtw_sreset.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,12 +11,7 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#include
#include
@@ -131,31 +126,18 @@ void sreset_restore_security_station(_adapter *padapter)
rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8));
}
-#if 0
- if ((padapter->securitypriv.dot11PrivacyAlgrthm == _WEP40_) ||
- (padapter->securitypriv.dot11PrivacyAlgrthm == _WEP104_)) {
-
- for (EntryId = 0; EntryId < 4; EntryId++) {
- if (EntryId == psecuritypriv->dot11PrivacyKeyIndex)
- rtw_set_key(padapter, &padapter->securitypriv, EntryId, 1, _FALSE);
- else
- rtw_set_key(padapter, &padapter->securitypriv, EntryId, 0, _FALSE);
- }
-
- } else
-#endif
- if ((padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_) ||
- (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)) {
- psta = rtw_get_stainfo(pstapriv, get_bssid(mlmepriv));
- if (psta == NULL) {
- /* DEBUG_ERR( ("Set wpa_set_encryption: Obtain Sta_info fail\n")); */
- } else {
- /* pairwise key */
- rtw_setstakey_cmd(padapter, psta, UNICAST_KEY, _FALSE);
- /* group key */
- rtw_set_key(padapter, &padapter->securitypriv, padapter->securitypriv.dot118021XGrpKeyid, 0, _FALSE);
- }
+ if ((padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_) ||
+ (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)) {
+ psta = rtw_get_stainfo(pstapriv, get_bssid(mlmepriv));
+ if (psta == NULL) {
+ /* DEBUG_ERR( ("Set wpa_set_encryption: Obtain Sta_info fail\n")); */
+ } else {
+ /* pairwise key */
+ rtw_setstakey_cmd(padapter, psta, UNICAST_KEY, _FALSE);
+ /* group key */
+ rtw_set_key(padapter, &padapter->securitypriv, padapter->securitypriv.dot118021XGrpKeyid, 0, _FALSE);
}
+ }
}
void sreset_restore_network_station(_adapter *padapter)
@@ -184,7 +166,7 @@ void sreset_restore_network_station(_adapter *padapter)
}
#endif
- rtw_setopmode_cmd(padapter, Ndis802_11Infrastructure, _FALSE);
+ rtw_setopmode_cmd(padapter, Ndis802_11Infrastructure, RTW_CMDF_DIRECTLY);
{
u8 threshold;
@@ -219,6 +201,7 @@ void sreset_restore_network_station(_adapter *padapter)
{
u8 join_type = 0;
rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));
+ rtw_hal_rcr_set_chk_bssid(padapter, MLME_STA_CONNECTING);
}
Set_MSR(padapter, (pmlmeinfo->state & 0x3));
@@ -240,8 +223,8 @@ void sreset_restore_network_status(_adapter *padapter)
if (check_fwstate(mlmepriv, WIFI_STATION_STATE)) {
RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_STATION_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
sreset_restore_network_station(padapter);
- } else if (check_fwstate(mlmepriv, WIFI_AP_STATE)) {
- RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_AP_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
+ } else if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {
+ RTW_INFO(FUNC_ADPT_FMT" %s\n", FUNC_ADPT_ARG(padapter), MLME_IS_AP(padapter) ? "AP" : "MESH");
rtw_ap_restore_network(padapter);
} else if (check_fwstate(mlmepriv, WIFI_ADHOC_STATE))
RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_ADHOC_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv));
@@ -273,7 +256,7 @@ void sreset_stop_adapter(_adapter *padapter)
if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING)) {
rtw_set_to_roam(padapter, 0);
- _rtw_join_timeout_handler(padapter);
+ rtw_join_timeout_handler(padapter);
}
}
@@ -297,7 +280,7 @@ void sreset_start_adapter(_adapter *padapter)
#endif
if (is_primary_adapter(padapter))
- _set_timer(&padapter->mlmepriv.dynamic_chk_timer, 2000);
+ _set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000);
rtw_netif_wake_queue(padapter->pnetdev);
}
@@ -311,7 +294,7 @@ void sreset_reset(_adapter *padapter)
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
_irqL irqL;
- u32 start = rtw_get_current_time();
+ systime start = rtw_get_current_time();
struct dvobj_priv *psdpriv = padapter->dvobj;
struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
@@ -342,5 +325,8 @@ void sreset_reset(_adapter *padapter)
RTW_INFO("%s done in %d ms\n", __FUNCTION__, rtw_get_passing_time_ms(start));
pdbgpriv->dbg_sreset_cnt++;
+
+ psrtpriv->self_dect_fw = _FALSE;
+ psrtpriv->rx_cnt = 0;
#endif
}
diff --git a/core/rtw_sta_mgt.c b/core/rtw_sta_mgt.c
index dd9978a..17c0257 100644
--- a/core/rtw_sta_mgt.c
+++ b/core/rtw_sta_mgt.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,12 +11,7 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#define _RTW_STA_MGT_C_
#include
@@ -133,6 +128,46 @@ inline bool rtw_st_ctl_chk_reg_rule(struct st_ctl_t *st_ctl, _adapter *adapter,
return ret;
}
+void rtw_st_ctl_rx(struct sta_info *sta, u8 *ehdr_pos)
+{
+ _adapter *adapter = sta->padapter;
+ struct ethhdr *etherhdr = (struct ethhdr *)ehdr_pos;
+
+ if (ntohs(etherhdr->h_proto) == ETH_P_IP) {
+ u8 *ip = ehdr_pos + ETH_HLEN;
+
+ if (GET_IPV4_PROTOCOL(ip) == 0x06 /* TCP */
+ && rtw_st_ctl_chk_reg_s_proto(&sta->st_ctl, 0x06) == _TRUE
+ ) {
+ u8 *tcp = ip + GET_IPV4_IHL(ip) * 4;
+
+ if (rtw_st_ctl_chk_reg_rule(&sta->st_ctl, adapter, IPV4_DST(ip), TCP_DST(tcp), IPV4_SRC(ip), TCP_SRC(tcp)) == _TRUE) {
+ if (GET_TCP_SYN(tcp) && GET_TCP_ACK(tcp)) {
+ session_tracker_add_cmd(adapter, sta
+ , IPV4_DST(ip), TCP_DST(tcp)
+ , IPV4_SRC(ip), TCP_SRC(tcp));
+ if (DBG_SESSION_TRACKER)
+ RTW_INFO(FUNC_ADPT_FMT" local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT" SYN-ACK\n"
+ , FUNC_ADPT_ARG(adapter)
+ , IP_ARG(IPV4_DST(ip)), PORT_ARG(TCP_DST(tcp))
+ , IP_ARG(IPV4_SRC(ip)), PORT_ARG(TCP_SRC(tcp)));
+ }
+ if (GET_TCP_FIN(tcp)) {
+ session_tracker_del_cmd(adapter, sta
+ , IPV4_DST(ip), TCP_DST(tcp)
+ , IPV4_SRC(ip), TCP_SRC(tcp));
+ if (DBG_SESSION_TRACKER)
+ RTW_INFO(FUNC_ADPT_FMT" local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT" FIN\n"
+ , FUNC_ADPT_ARG(adapter)
+ , IP_ARG(IPV4_DST(ip)), PORT_ARG(TCP_DST(tcp))
+ , IP_ARG(IPV4_SRC(ip)), PORT_ARG(TCP_SRC(tcp)));
+ }
+ }
+
+ }
+ }
+}
+
#define SESSION_TRACKER_FMT IP_FMT":"PORT_FMT" "IP_FMT":"PORT_FMT" %u %d"
#define SESSION_TRACKER_ARG(st) IP_ARG(&(st)->local_naddr), PORT_ARG(&(st)->local_port), IP_ARG(&(st)->remote_naddr), PORT_ARG(&(st)->remote_port), (st)->status, rtw_get_passing_time_ms((st)->set_time)
@@ -165,9 +200,6 @@ void dump_st_ctl(void *sel, struct st_ctl_t *st_ctl)
void _rtw_init_stainfo(struct sta_info *psta);
void _rtw_init_stainfo(struct sta_info *psta)
{
-
- _func_enter_;
-
_rtw_memset((u8 *)psta, 0, sizeof(struct sta_info));
_rtw_spinlock_init(&psta->lock);
@@ -178,61 +210,36 @@ void _rtw_init_stainfo(struct sta_info *psta)
/* _rtw_init_listhead(&psta->wakeup_list); */
_rtw_init_queue(&psta->sleep_q);
- psta->sleepq_len = 0;
_rtw_init_sta_xmit_priv(&psta->sta_xmitpriv);
_rtw_init_sta_recv_priv(&psta->sta_recvpriv);
#ifdef CONFIG_AP_MODE
-
_rtw_init_listhead(&psta->asoc_list);
-
_rtw_init_listhead(&psta->auth_list);
-
- psta->expire_to = 0;
-
- psta->flags = 0;
-
- psta->capability = 0;
-
psta->bpairwise_key_installed = _FALSE;
-
-#ifdef CONFIG_NATIVEAP_MLME
- psta->nonerp_set = 0;
- psta->no_short_slot_time_set = 0;
- psta->no_short_preamble_set = 0;
- psta->no_ht_gf_set = 0;
- psta->no_ht_set = 0;
- psta->ht_20mhz_set = 0;
- psta->ht_40mhz_intolerant = 0;
+#ifdef CONFIG_RTW_80211R
+ psta->ft_pairwise_key_installed = _FALSE;
#endif
-
-#ifdef CONFIG_TX_MCAST2UNI
- psta->under_exist_checking = 0;
-#endif /* CONFIG_TX_MCAST2UNI */
-
- psta->keep_alive_trycnt = 0;
-
#endif /* CONFIG_AP_MODE */
rtw_st_ctl_init(&psta->st_ctl);
-
- _func_exit_;
-
}
u32 _rtw_init_sta_priv(struct sta_priv *pstapriv)
{
+ _adapter *adapter = container_of(pstapriv, _adapter, stapriv);
+ struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
struct sta_info *psta;
s32 i;
+ u32 ret = _FAIL;
- _func_enter_;
+ pstapriv->padapter = adapter;
pstapriv->pallocated_stainfo_buf = rtw_zvmalloc(sizeof(struct sta_info) * NUM_STA + 4);
-
if (!pstapriv->pallocated_stainfo_buf)
- return _FAIL;
+ goto exit;
pstapriv->pstainfo_buf = pstapriv->pallocated_stainfo_buf + 4 -
((SIZE_PTR)(pstapriv->pallocated_stainfo_buf) & 3);
@@ -262,9 +269,19 @@ u32 _rtw_init_sta_priv(struct sta_priv *pstapriv)
pstapriv->adhoc_expire_to = 4; /* 4 * 2 = 8 sec */
#ifdef CONFIG_AP_MODE
-
- pstapriv->sta_dz_bitmap = 0;
- pstapriv->tim_bitmap = 0;
+ pstapriv->max_aid = macid_ctl->num;
+ pstapriv->rr_aid = 0;
+ pstapriv->started_aid = 1;
+ pstapriv->sta_aid = rtw_zmalloc(pstapriv->max_aid * sizeof(struct sta_info *));
+ if (!pstapriv->sta_aid)
+ goto exit;
+ pstapriv->aid_bmp_len = AID_BMP_LEN(pstapriv->max_aid);
+ pstapriv->sta_dz_bitmap = rtw_zmalloc(pstapriv->aid_bmp_len);
+ if (!pstapriv->sta_dz_bitmap)
+ goto exit;
+ pstapriv->tim_bitmap = rtw_zmalloc(pstapriv->aid_bmp_len);
+ if (!pstapriv->tim_bitmap)
+ goto exit;
_rtw_init_listhead(&pstapriv->asoc_list);
_rtw_init_listhead(&pstapriv->auth_list);
@@ -290,13 +307,29 @@ u32 _rtw_init_sta_priv(struct sta_priv *pstapriv)
#endif
#if CONFIG_RTW_MACADDR_ACL
- _rtw_init_queue(&(pstapriv->acl_list.acl_node_q));
+ for (i = 0; i < RTW_ACL_PERIOD_NUM; i++)
+ rtw_macaddr_acl_init(adapter, i);
#endif
- _func_exit_;
+#if CONFIG_RTW_PRE_LINK_STA
+ rtw_pre_link_sta_ctl_init(pstapriv);
+#endif
- return _SUCCESS;
+ ret = _SUCCESS;
+exit:
+ if (ret != _SUCCESS) {
+ if (pstapriv->pallocated_stainfo_buf)
+ rtw_vmfree(pstapriv->pallocated_stainfo_buf, sizeof(struct sta_info) * NUM_STA + 4);
+ #ifdef CONFIG_AP_MODE
+ if (pstapriv->sta_aid)
+ rtw_mfree(pstapriv->sta_aid, pstapriv->max_aid * sizeof(struct sta_info *));
+ if (pstapriv->sta_dz_bitmap)
+ rtw_mfree(pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len);
+ #endif
+ }
+
+ return ret;
}
inline int rtw_stainfo_offset(struct sta_priv *stapriv, struct sta_info *sta)
@@ -320,7 +353,6 @@ inline struct sta_info *rtw_get_stainfo_by_offset(struct sta_priv *stapriv, int
void _rtw_free_sta_xmit_priv_lock(struct sta_xmit_priv *psta_xmitpriv);
void _rtw_free_sta_xmit_priv_lock(struct sta_xmit_priv *psta_xmitpriv)
{
- _func_enter_;
_rtw_spinlock_free(&psta_xmitpriv->lock);
@@ -328,25 +360,21 @@ void _rtw_free_sta_xmit_priv_lock(struct sta_xmit_priv *psta_xmitpriv)
_rtw_spinlock_free(&(psta_xmitpriv->bk_q.sta_pending.lock));
_rtw_spinlock_free(&(psta_xmitpriv->vi_q.sta_pending.lock));
_rtw_spinlock_free(&(psta_xmitpriv->vo_q.sta_pending.lock));
- _func_exit_;
}
static void _rtw_free_sta_recv_priv_lock(struct sta_recv_priv *psta_recvpriv)
{
- _func_enter_;
_rtw_spinlock_free(&psta_recvpriv->lock);
_rtw_spinlock_free(&(psta_recvpriv->defrag_q.lock));
- _func_exit_;
}
void rtw_mfree_stainfo(struct sta_info *psta);
void rtw_mfree_stainfo(struct sta_info *psta)
{
- _func_enter_;
if (&psta->lock != NULL)
_rtw_spinlock_free(&psta->lock);
@@ -354,7 +382,6 @@ void rtw_mfree_stainfo(struct sta_info *psta)
_rtw_free_sta_xmit_priv_lock(&psta->sta_xmitpriv);
_rtw_free_sta_recv_priv_lock(&psta->sta_recvpriv);
- _func_exit_;
}
@@ -366,7 +393,6 @@ void rtw_mfree_all_stainfo(struct sta_priv *pstapriv)
_list *plist, *phead;
struct sta_info *psta = NULL;
- _func_enter_;
_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
@@ -382,7 +408,6 @@ void rtw_mfree_all_stainfo(struct sta_priv *pstapriv)
_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
- _func_exit_;
}
@@ -412,7 +437,6 @@ u32 _rtw_free_sta_priv(struct sta_priv *pstapriv)
struct recv_reorder_ctrl *preorder_ctrl;
int index;
- _func_enter_;
if (pstapriv) {
/* delete all reordering_ctrl_timer */
@@ -438,23 +462,43 @@ u32 _rtw_free_sta_priv(struct sta_priv *pstapriv)
rtw_mfree_sta_priv_lock(pstapriv);
#if CONFIG_RTW_MACADDR_ACL
- _rtw_deinit_queue(&(pstapriv->acl_list.acl_node_q));
+ for (index = 0; index < RTW_ACL_PERIOD_NUM; index++)
+ rtw_macaddr_acl_deinit(pstapriv->padapter, index);
+#endif
+
+#if CONFIG_RTW_PRE_LINK_STA
+ rtw_pre_link_sta_ctl_deinit(pstapriv);
#endif
if (pstapriv->pallocated_stainfo_buf)
rtw_vmfree(pstapriv->pallocated_stainfo_buf, sizeof(struct sta_info) * NUM_STA + 4);
+ #ifdef CONFIG_AP_MODE
+ if (pstapriv->sta_aid)
+ rtw_mfree(pstapriv->sta_aid, pstapriv->max_aid * sizeof(struct sta_info *));
+ if (pstapriv->sta_dz_bitmap)
+ rtw_mfree(pstapriv->sta_dz_bitmap, pstapriv->aid_bmp_len);
+ if (pstapriv->tim_bitmap)
+ rtw_mfree(pstapriv->tim_bitmap, pstapriv->aid_bmp_len);
+ #endif
}
- _func_exit_;
return _SUCCESS;
}
+static void rtw_init_recv_timer(struct recv_reorder_ctrl *preorder_ctrl)
+{
+ _adapter *padapter = preorder_ctrl->padapter;
+
+#if defined(CONFIG_80211N_HT) && defined(CONFIG_RECV_REORDERING_CTRL)
+ rtw_init_timer(&(preorder_ctrl->reordering_ctrl_timer), padapter, rtw_reordering_ctrl_timeout_handler, preorder_ctrl);
+#endif
+}
+
/* struct sta_info *rtw_alloc_stainfo(_queue *pfree_sta_queue, unsigned char *hwaddr) */
-struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr)
+struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, const u8 *hwaddr)
{
_irqL irqL, irqL2;
- uint tmp_aid;
s32 index;
_list *phash_list;
struct sta_info *psta;
@@ -463,7 +507,6 @@ struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr)
int i = 0;
u16 wRxSeqInitialValue = 0xffff;
- _func_enter_;
pfree_sta_queue = &pstapriv->free_sta_queue;
@@ -479,21 +522,16 @@ struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr)
rtw_list_delete(&(psta->list));
/* _exit_critical_bh(&(pfree_sta_queue->lock), &irqL); */
-
- tmp_aid = psta->aid;
-
_rtw_init_stainfo(psta);
psta->padapter = pstapriv->padapter;
- _rtw_memcpy(psta->hwaddr, hwaddr, ETH_ALEN);
+ _rtw_memcpy(psta->cmn.mac_addr, hwaddr, ETH_ALEN);
index = wifi_mac_hash(hwaddr);
- RT_TRACE(_module_rtl871x_sta_mgt_c_, _drv_info_, ("rtw_alloc_stainfo: index = %x", index));
if (index >= NUM_STA) {
- RT_TRACE(_module_rtl871x_sta_mgt_c_, _drv_err_, ("ERROR=> rtw_alloc_stainfo: index >= NUM_STA"));
psta = NULL;
goto exit;
}
@@ -512,15 +550,15 @@ struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr)
* In this case, this packet will be dropped by recv_decache function if we use the 0x00 as the default value for tid_rxseq variable.
* So, we initialize the tid_rxseq variable as the 0xffff. */
- for (i = 0; i < 16; i++)
+ for (i = 0; i < 16; i++) {
_rtw_memcpy(&psta->sta_recvpriv.rxcache.tid_rxseq[i], &wRxSeqInitialValue, 2);
+ _rtw_memcpy(&psta->sta_recvpriv.bmc_tid_rxseq[i], &wRxSeqInitialValue, 2);
+ _rtw_memset(&psta->sta_recvpriv.rxcache.iv[i], 0, sizeof(psta->sta_recvpriv.rxcache.iv[i]));
+ }
- RT_TRACE(_module_rtl871x_sta_mgt_c_, _drv_info_, ("alloc number_%d stainfo with hwaddr = %x %x %x %x %x %x\n",
- pstapriv->asoc_sta_count , hwaddr[0], hwaddr[1], hwaddr[2], hwaddr[3], hwaddr[4], hwaddr[5]));
-
- init_addba_retry_timer(pstapriv->padapter, psta);
+ rtw_init_timer(&psta->addba_retry_timer, psta->padapter, addba_timer_hdl, psta);
#ifdef CONFIG_IEEE80211W
- init_dot11w_expire_timer(pstapriv->padapter, psta);
+ rtw_init_timer(&psta->dot11w_expire_timer, psta->padapter, sa_query_timer_hdl, psta);
#endif /* CONFIG_IEEE80211W */
#ifdef CONFIG_TDLS
rtw_init_tdls_timer(pstapriv->padapter, psta);
@@ -529,16 +567,14 @@ struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr)
/* for A-MPDU Rx reordering buffer control */
for (i = 0; i < 16 ; i++) {
preorder_ctrl = &psta->recvreorder_ctrl[i];
-
preorder_ctrl->padapter = pstapriv->padapter;
-
+ preorder_ctrl->tid = i;
preorder_ctrl->enable = _FALSE;
-
preorder_ctrl->indicate_seq = 0xffff;
-#ifdef DBG_RX_SEQ
- RTW_INFO("DBG_RX_SEQ %s:%d IndicateSeq: %d\n", __FUNCTION__, __LINE__,
- preorder_ctrl->indicate_seq);
-#endif
+ #ifdef DBG_RX_SEQ
+ RTW_INFO("DBG_RX_SEQ "FUNC_ADPT_FMT" tid:%u SN_CLEAR indicate_seq:%d\n"
+ , FUNC_ADPT_ARG(pstapriv->padapter), i, preorder_ctrl->indicate_seq);
+ #endif
preorder_ctrl->wend_b = 0xffff;
/* preorder_ctrl->wsize_b = (NR_RECVBUFF-2); */
preorder_ctrl->wsize_b = 64;/* 64; */
@@ -551,14 +587,14 @@ struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr)
/* init for DM */
- psta->rssi_stat.UndecoratedSmoothedPWDB = (-1);
- psta->rssi_stat.UndecoratedSmoothedCCK = (-1);
+ psta->cmn.rssi_stat.rssi = (-1);
+ psta->cmn.rssi_stat.rssi_cck = (-1);
+ psta->cmn.rssi_stat.rssi_ofdm = (-1);
#ifdef CONFIG_ATMEL_RC_PATCH
psta->flag_atmel_rc = 0;
#endif
/* init for the sequence number of received management frame */
psta->RxMgmtFrameSeqNum = 0xffff;
- psta->ra_rpt_linked = _FALSE;
rtw_alloc_macid(pstapriv->padapter, psta);
@@ -568,11 +604,11 @@ struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr)
_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2);
- _func_exit_;
-
- return psta;
+ if (psta)
+ rtw_mi_update_iface_status(&(pstapriv->padapter->mlmepriv), 0);
+ return psta;
}
@@ -587,20 +623,32 @@ u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta)
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
struct sta_priv *pstapriv = &padapter->stapriv;
struct hw_xmit *phwxmit;
- int pending_qcnt[4];
+ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
- _func_enter_;
+ int pending_qcnt[4];
+ u8 is_pre_link_sta = _FALSE;
if (psta == NULL)
goto exit;
- _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL0);
- rtw_list_delete(&psta->hash_list);
- RT_TRACE(_module_rtl871x_sta_mgt_c_, _drv_err_, ("\n free number_%d stainfo with hwaddr = 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x\n", pstapriv->asoc_sta_count , psta->hwaddr[0],
- psta->hwaddr[1], psta->hwaddr[2], psta->hwaddr[3], psta->hwaddr[4], psta->hwaddr[5]));
- pstapriv->asoc_sta_count--;
- _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL0);
+#ifdef CONFIG_RTW_80211K
+ rm_post_event(padapter, RM_ID_FOR_ALL(psta->cmn.aid), RM_EV_cancel);
+#endif
+ is_pre_link_sta = rtw_is_pre_link_sta(pstapriv, psta->cmn.mac_addr);
+
+ if (is_pre_link_sta == _FALSE) {
+ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL0);
+ rtw_list_delete(&psta->hash_list);
+ pstapriv->asoc_sta_count--;
+ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL0);
+ rtw_mi_update_iface_status(&(padapter->mlmepriv), 0);
+ } else {
+ _enter_critical_bh(&psta->lock, &irqL0);
+ psta->state = WIFI_FW_PRE_LINK;
+ _exit_critical_bh(&psta->lock, &irqL0);
+ }
_enter_critical_bh(&psta->lock, &irqL0);
psta->state &= ~_FW_LINKED;
@@ -675,7 +723,6 @@ u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta)
#ifdef CONFIG_TDLS
psta->tdls_sta_state = TDLS_STATE_NONE;
- rtw_free_tdls_timer(psta);
#endif /* CONFIG_TDLS */
/* for A-MPDU Rx reordering buffer control, cancel reordering_ctrl_timer */
@@ -712,12 +759,13 @@ u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta)
}
- if (!((psta->state & WIFI_AP_STATE) || MacAddr_isBcst(psta->hwaddr)))
+ if (!((psta->state & WIFI_AP_STATE) || MacAddr_isBcst(psta->cmn.mac_addr)) && is_pre_link_sta == _FALSE)
rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _FALSE);
/* release mac id for non-bc/mc station, */
- rtw_release_macid(pstapriv->padapter, psta);
+ if (is_pre_link_sta == _FALSE)
+ rtw_release_macid(pstapriv->padapter, psta);
#ifdef CONFIG_AP_MODE
@@ -750,14 +798,16 @@ u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta)
#ifdef CONFIG_NATIVEAP_MLME
- pstapriv->sta_dz_bitmap &= ~BIT(psta->aid);
- pstapriv->tim_bitmap &= ~BIT(psta->aid);
+ if (pmlmeinfo->state == _HW_STATE_AP_) {
+ rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid);
+ rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid);
- /* rtw_indicate_sta_disassoc_event(padapter, psta); */
+ /* rtw_indicate_sta_disassoc_event(padapter, psta); */
- if ((psta->aid > 0) && (pstapriv->sta_aid[psta->aid - 1] == psta)) {
- pstapriv->sta_aid[psta->aid - 1] = NULL;
- psta->aid = 0;
+ if ((psta->cmn.aid > 0) && (pstapriv->sta_aid[psta->cmn.aid - 1] == psta)) {
+ pstapriv->sta_aid[psta->cmn.aid - 1] = NULL;
+ psta->cmn.aid = 0;
+ }
}
#endif /* CONFIG_NATIVEAP_MLME */
@@ -770,20 +820,18 @@ u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta)
rtw_st_ctl_deinit(&psta->st_ctl);
- _rtw_spinlock_free(&psta->lock);
+ if (is_pre_link_sta == _FALSE) {
+ _rtw_spinlock_free(&psta->lock);
- /* _enter_critical_bh(&(pfree_sta_queue->lock), &irqL0); */
- _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL0);
- rtw_list_insert_tail(&psta->list, get_list_head(pfree_sta_queue));
- _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL0);
- /* _exit_critical_bh(&(pfree_sta_queue->lock), &irqL0); */
+ /* _enter_critical_bh(&(pfree_sta_queue->lock), &irqL0); */
+ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL0);
+ rtw_list_insert_tail(&psta->list, get_list_head(pfree_sta_queue));
+ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL0);
+ /* _exit_critical_bh(&(pfree_sta_queue->lock), &irqL0); */
+ }
exit:
-
- _func_exit_;
-
return _SUCCESS;
-
}
/* free all stainfo which in sta_hash[all] */
@@ -799,7 +847,6 @@ void rtw_free_all_stainfo(_adapter *padapter)
char free_sta_list[NUM_STA];
int stainfo_offset;
- _func_enter_;
if (pstapriv->asoc_sta_count == 1)
goto exit;
@@ -816,8 +863,9 @@ void rtw_free_all_stainfo(_adapter *padapter)
plist = get_next(plist);
if (pbcmc_stainfo != psta) {
- rtw_list_delete(&psta->hash_list);
- /* rtw_free_stainfo(padapter , psta); */
+ if (rtw_is_pre_link_sta(pstapriv, psta->cmn.mac_addr) == _FALSE)
+ rtw_list_delete(&psta->hash_list);
+
stainfo_offset = rtw_stainfo_offset(pstapriv, psta);
if (stainfo_offset_valid(stainfo_offset))
free_sta_list[free_sta_num++] = stainfo_offset;
@@ -835,13 +883,11 @@ void rtw_free_all_stainfo(_adapter *padapter)
}
exit:
-
- _func_exit_;
-
+ return;
}
/* any station allocated can be searched by hash list */
-struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, u8 *hwaddr)
+struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, const u8 *hwaddr)
{
_irqL irqL;
@@ -852,11 +898,10 @@ struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, u8 *hwaddr)
u32 index;
- u8 *addr;
+ const u8 *addr;
u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
- _func_enter_;
if (hwaddr == NULL)
return NULL;
@@ -878,7 +923,7 @@ struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, u8 *hwaddr)
psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
- if ((_rtw_memcmp(psta->hwaddr, addr, ETH_ALEN)) == _TRUE) {
+ if ((_rtw_memcmp(psta->cmn.mac_addr, addr, ETH_ALEN)) == _TRUE) {
/* if found the matched address */
break;
}
@@ -887,7 +932,6 @@ struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, u8 *hwaddr)
}
_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
- _func_exit_;
return psta;
}
@@ -903,19 +947,18 @@ u32 rtw_init_bcmc_stainfo(_adapter *padapter)
struct sta_priv *pstapriv = &padapter->stapriv;
/* _queue *pstapending = &padapter->xmitpriv.bm_pending; */
- _func_enter_;
psta = rtw_alloc_stainfo(pstapriv, bcast_addr);
if (psta == NULL) {
res = _FAIL;
- RT_TRACE(_module_rtl871x_sta_mgt_c_, _drv_err_, ("rtw_alloc_stainfo fail"));
goto exit;
}
#ifdef CONFIG_BEAMFORMING
- psta->txbf_gid = 63;
- psta->txbf_paid = 0;
+ psta->cmn.bf_info.g_id = 63;
+ psta->cmn.bf_info.p_aid = 0;
#endif
+
ptxservq = &(psta->sta_xmitpriv.be_q);
/*
@@ -928,7 +971,6 @@ u32 rtw_init_bcmc_stainfo(_adapter *padapter)
*/
exit:
- _func_exit_;
return _SUCCESS;
}
@@ -939,15 +981,80 @@ struct sta_info *rtw_get_bcmc_stainfo(_adapter *padapter)
struct sta_info *psta;
struct sta_priv *pstapriv = &padapter->stapriv;
u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
- _func_enter_;
psta = rtw_get_stainfo(pstapriv, bc_addr);
- _func_exit_;
return psta;
}
+#ifdef CONFIG_AP_MODE
+u16 rtw_aid_alloc(_adapter *adapter, struct sta_info *sta)
+{
+ struct sta_priv *stapriv = &adapter->stapriv;
+ u16 aid, i, used_cnt = 0;
+
+ for (i = 0; i < stapriv->max_aid; i++) {
+ aid = ((i + stapriv->started_aid - 1) % stapriv->max_aid) + 1;
+ if (stapriv->sta_aid[aid - 1] == NULL)
+ break;
+ if (++used_cnt >= stapriv->max_num_sta)
+ break;
+ }
+
+ /* check for aid limit and assoc limit */
+ if (i >= stapriv->max_aid || used_cnt >= stapriv->max_num_sta)
+ aid = 0;
+
+ sta->cmn.aid = aid;
+ if (aid) {
+ stapriv->sta_aid[aid - 1] = sta;
+ if (stapriv->rr_aid)
+ stapriv->started_aid = (aid % stapriv->max_aid) + 1;
+ }
+
+ return aid;
+}
+
+void dump_aid_status(void *sel, _adapter *adapter)
+{
+ struct sta_priv *stapriv = &adapter->stapriv;
+ u8 *aid_bmp;
+ u16 i, used_cnt = 0;
+
+ aid_bmp = rtw_zmalloc(stapriv->aid_bmp_len);
+ if (!aid_bmp)
+ return;
+
+ for (i = 1; i <= stapriv->max_aid; i++) {
+ if (stapriv->sta_aid[i - 1]) {
+ aid_bmp[i / 8] |= BIT(i % 8);
+ ++used_cnt;
+ }
+ }
+
+ RTW_PRINT_SEL(sel, "used_cnt:%u/%u\n", used_cnt, stapriv->max_aid);
+ RTW_MAP_DUMP_SEL(sel, "aid_map:", aid_bmp, stapriv->aid_bmp_len);
+ RTW_PRINT_SEL(sel, "\n");
+
+ RTW_PRINT_SEL(sel, "%-2s %-11s\n", "rr", "started_aid");
+ RTW_PRINT_SEL(sel, "%2d %11d\n", stapriv->rr_aid, stapriv->started_aid);
+
+ rtw_mfree(aid_bmp, stapriv->aid_bmp_len);
+}
+#endif /* CONFIG_AP_MODE */
+
#if CONFIG_RTW_MACADDR_ACL
-u8 rtw_access_ctrl(_adapter *adapter, u8 *mac_addr)
+const char *const _acl_period_str[RTW_ACL_PERIOD_NUM] = {
+ "DEV",
+ "BSS",
+};
+
+const char *const _acl_mode_str[RTW_ACL_MODE_MAX] = {
+ "DISABLED",
+ "ACCEPT_UNLESS_LISTED",
+ "DENY_UNLESS_LISTED",
+};
+
+u8 _rtw_access_ctrl(_adapter *adapter, u8 period, const u8 *mac_addr)
{
u8 res = _TRUE;
_irqL irqL;
@@ -955,8 +1062,20 @@ u8 rtw_access_ctrl(_adapter *adapter, u8 *mac_addr)
struct rtw_wlan_acl_node *acl_node;
u8 match = _FALSE;
struct sta_priv *stapriv = &adapter->stapriv;
- struct wlan_acl_pool *acl = &stapriv->acl_list;
- _queue *acl_node_q = &acl->acl_node_q;
+ struct wlan_acl_pool *acl;
+ _queue *acl_node_q;
+
+ if (period >= RTW_ACL_PERIOD_NUM) {
+ rtw_warn_on(1);
+ goto exit;
+ }
+
+ acl = &stapriv->acl_list[period];
+ acl_node_q = &acl->acl_node_q;
+
+ if (acl->mode != RTW_ACL_MODE_ACCEPT_UNLESS_LISTED
+ && acl->mode != RTW_ACL_MODE_DENY_UNLESS_LISTED)
+ goto exit;
_enter_critical_bh(&(acl_node_q->lock), &irqL);
head = get_list_head(acl_node_q);
@@ -976,11 +1095,235 @@ u8 rtw_access_ctrl(_adapter *adapter, u8 *mac_addr)
if (acl->mode == RTW_ACL_MODE_ACCEPT_UNLESS_LISTED)
res = (match == _TRUE) ? _FALSE : _TRUE;
- else if (acl->mode == RTW_ACL_MODE_DENY_UNLESS_LISTED)
+ else /* RTW_ACL_MODE_DENY_UNLESS_LISTED */
res = (match == _TRUE) ? _TRUE : _FALSE;
- else
- res = _TRUE;
+exit:
return res;
}
+
+u8 rtw_access_ctrl(_adapter *adapter, const u8 *mac_addr)
+{
+ int i;
+
+ for (i = 0; i < RTW_ACL_PERIOD_NUM; i++)
+ if (_rtw_access_ctrl(adapter, i, mac_addr) == _FALSE)
+ return _FALSE;
+
+ return _TRUE;
+}
+
+void dump_macaddr_acl(void *sel, _adapter *adapter)
+{
+ struct sta_priv *stapriv = &adapter->stapriv;
+ struct wlan_acl_pool *acl;
+ int i, j;
+
+ for (j = 0; j < RTW_ACL_PERIOD_NUM; j++) {
+ RTW_PRINT_SEL(sel, "period:%s(%d)\n", acl_period_str(j), j);
+
+ acl = &stapriv->acl_list[j];
+ RTW_PRINT_SEL(sel, "mode:%s(%d)\n", acl_mode_str(acl->mode), acl->mode);
+ RTW_PRINT_SEL(sel, "num:%d/%d\n", acl->num, NUM_ACL);
+ for (i = 0; i < NUM_ACL; i++) {
+ if (acl->aclnode[i].valid == _FALSE)
+ continue;
+ RTW_PRINT_SEL(sel, MAC_FMT"\n", MAC_ARG(acl->aclnode[i].addr));
+ }
+ RTW_PRINT_SEL(sel, "\n");
+ }
+}
#endif /* CONFIG_RTW_MACADDR_ACL */
+
+bool rtw_is_pre_link_sta(struct sta_priv *stapriv, u8 *addr)
+{
+#if CONFIG_RTW_PRE_LINK_STA
+ struct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl;
+ struct sta_info *sta = NULL;
+ u8 exist = _FALSE;
+ int i;
+ _irqL irqL;
+
+ _enter_critical_bh(&(pre_link_sta_ctl->lock), &irqL);
+ for (i = 0; i < RTW_PRE_LINK_STA_NUM; i++) {
+ if (pre_link_sta_ctl->node[i].valid == _TRUE
+ && _rtw_memcmp(pre_link_sta_ctl->node[i].addr, addr, ETH_ALEN) == _TRUE
+ ) {
+ exist = _TRUE;
+ break;
+ }
+ }
+ _exit_critical_bh(&(pre_link_sta_ctl->lock), &irqL);
+
+ return exist;
+#else
+ return _FALSE;
+#endif
+}
+
+#if CONFIG_RTW_PRE_LINK_STA
+struct sta_info *rtw_pre_link_sta_add(struct sta_priv *stapriv, u8 *hwaddr)
+{
+ struct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl;
+ struct pre_link_sta_node_t *node = NULL;
+ struct sta_info *sta = NULL;
+ u8 exist = _FALSE;
+ int i;
+ _irqL irqL;
+
+ if (rtw_check_invalid_mac_address(hwaddr, _FALSE) == _TRUE)
+ goto exit;
+
+ _enter_critical_bh(&(pre_link_sta_ctl->lock), &irqL);
+ for (i = 0; i < RTW_PRE_LINK_STA_NUM; i++) {
+ if (pre_link_sta_ctl->node[i].valid == _TRUE
+ && _rtw_memcmp(pre_link_sta_ctl->node[i].addr, hwaddr, ETH_ALEN) == _TRUE
+ ) {
+ node = &pre_link_sta_ctl->node[i];
+ exist = _TRUE;
+ break;
+ }
+
+ if (node == NULL && pre_link_sta_ctl->node[i].valid == _FALSE)
+ node = &pre_link_sta_ctl->node[i];
+ }
+
+ if (exist == _FALSE && node) {
+ _rtw_memcpy(node->addr, hwaddr, ETH_ALEN);
+ node->valid = _TRUE;
+ pre_link_sta_ctl->num++;
+ }
+ _exit_critical_bh(&(pre_link_sta_ctl->lock), &irqL);
+
+ if (node == NULL)
+ goto exit;
+
+ sta = rtw_get_stainfo(stapriv, hwaddr);
+ if (sta)
+ goto odm_hook;
+
+ sta = rtw_alloc_stainfo(stapriv, hwaddr);
+ if (!sta)
+ goto exit;
+
+ sta->state = WIFI_FW_PRE_LINK;
+
+odm_hook:
+ rtw_hal_set_odm_var(stapriv->padapter, HAL_ODM_STA_INFO, sta, _TRUE);
+
+exit:
+ return sta;
+}
+
+void rtw_pre_link_sta_del(struct sta_priv *stapriv, u8 *hwaddr)
+{
+ struct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl;
+ struct pre_link_sta_node_t *node = NULL;
+ struct sta_info *sta = NULL;
+ u8 exist = _FALSE;
+ int i;
+ _irqL irqL;
+
+ if (rtw_check_invalid_mac_address(hwaddr, _FALSE) == _TRUE)
+ goto exit;
+
+ _enter_critical_bh(&(pre_link_sta_ctl->lock), &irqL);
+ for (i = 0; i < RTW_PRE_LINK_STA_NUM; i++) {
+ if (pre_link_sta_ctl->node[i].valid == _TRUE
+ && _rtw_memcmp(pre_link_sta_ctl->node[i].addr, hwaddr, ETH_ALEN) == _TRUE
+ ) {
+ node = &pre_link_sta_ctl->node[i];
+ exist = _TRUE;
+ break;
+ }
+ }
+
+ if (exist == _TRUE && node) {
+ node->valid = _FALSE;
+ pre_link_sta_ctl->num--;
+ }
+ _exit_critical_bh(&(pre_link_sta_ctl->lock), &irqL);
+
+ if (exist == _FALSE)
+ goto exit;
+
+ sta = rtw_get_stainfo(stapriv, hwaddr);
+ if (!sta)
+ goto exit;
+
+ if (sta->state == WIFI_FW_PRE_LINK)
+ rtw_free_stainfo(stapriv->padapter, sta);
+
+exit:
+ return;
+}
+
+void rtw_pre_link_sta_ctl_reset(struct sta_priv *stapriv)
+{
+ struct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl;
+ struct pre_link_sta_node_t *node = NULL;
+ struct sta_info *sta = NULL;
+ int i, j = 0;
+ _irqL irqL;
+
+ u8 addrs[RTW_PRE_LINK_STA_NUM][ETH_ALEN];
+
+ _rtw_memset(addrs, 0, RTW_PRE_LINK_STA_NUM * ETH_ALEN);
+
+ _enter_critical_bh(&(pre_link_sta_ctl->lock), &irqL);
+ for (i = 0; i < RTW_PRE_LINK_STA_NUM; i++) {
+ if (pre_link_sta_ctl->node[i].valid == _FALSE)
+ continue;
+ _rtw_memcpy(&(addrs[j][0]), pre_link_sta_ctl->node[i].addr, ETH_ALEN);
+ pre_link_sta_ctl->node[i].valid = _FALSE;
+ pre_link_sta_ctl->num--;
+ j++;
+ }
+ _exit_critical_bh(&(pre_link_sta_ctl->lock), &irqL);
+
+ for (i = 0; i < j; i++) {
+ sta = rtw_get_stainfo(stapriv, &(addrs[i][0]));
+ if (!sta)
+ continue;
+
+ if (sta->state == WIFI_FW_PRE_LINK)
+ rtw_free_stainfo(stapriv->padapter, sta);
+ }
+}
+
+void rtw_pre_link_sta_ctl_init(struct sta_priv *stapriv)
+{
+ struct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl;
+ int i;
+
+ _rtw_spinlock_init(&pre_link_sta_ctl->lock);
+ pre_link_sta_ctl->num = 0;
+ for (i = 0; i < RTW_PRE_LINK_STA_NUM; i++)
+ pre_link_sta_ctl->node[i].valid = _FALSE;
+}
+
+void rtw_pre_link_sta_ctl_deinit(struct sta_priv *stapriv)
+{
+ struct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl;
+ int i;
+
+ rtw_pre_link_sta_ctl_reset(stapriv);
+
+ _rtw_spinlock_free(&pre_link_sta_ctl->lock);
+}
+
+void dump_pre_link_sta_ctl(void *sel, struct sta_priv *stapriv)
+{
+ struct pre_link_sta_ctl_t *pre_link_sta_ctl = &stapriv->pre_link_sta_ctl;
+ int i;
+
+ RTW_PRINT_SEL(sel, "num:%d/%d\n", pre_link_sta_ctl->num, RTW_PRE_LINK_STA_NUM);
+
+ for (i = 0; i < RTW_PRE_LINK_STA_NUM; i++) {
+ if (pre_link_sta_ctl->node[i].valid == _FALSE)
+ continue;
+ RTW_PRINT_SEL(sel, MAC_FMT"\n", MAC_ARG(pre_link_sta_ctl->node[i].addr));
+ }
+}
+#endif /* CONFIG_RTW_PRE_LINK_STA */
+
diff --git a/core/rtw_tdls.c b/core/rtw_tdls.c
index 5b172b9..07395fc 100644
--- a/core/rtw_tdls.c
+++ b/core/rtw_tdls.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,12 +11,7 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#define _RTW_TDLS_C_
#include
@@ -27,7 +22,12 @@
extern unsigned char MCS_rate_2R[16];
extern unsigned char MCS_rate_1R[16];
-extern void process_wmmps_data(_adapter *padapter, union recv_frame *precv_frame);
+
+inline void rtw_tdls_set_link_established(_adapter *adapter, bool en)
+{
+ adapter->tdlsinfo.link_established = en;
+ rtw_mi_update_iface_status(&(adapter->mlmepriv), 0);
+}
void rtw_reset_tdls_info(_adapter *padapter)
{
@@ -41,7 +41,7 @@ void rtw_reset_tdls_info(_adapter *padapter)
else
ptdlsinfo->ch_switch_prohibited = _TRUE;
- ptdlsinfo->link_established = _FALSE;
+ rtw_tdls_set_link_established(padapter, _FALSE);
ptdlsinfo->sta_cnt = 0;
ptdlsinfo->sta_maximum = _FALSE;
@@ -62,6 +62,8 @@ void rtw_reset_tdls_info(_adapter *padapter)
#ifdef CONFIG_WFD
ptdlsinfo->wfd_info = &padapter->wfd_info;
#endif
+
+ ptdlsinfo->tdls_sctx = NULL;
}
int rtw_init_tdls_info(_adapter *padapter)
@@ -71,7 +73,6 @@ int rtw_init_tdls_info(_adapter *padapter)
rtw_reset_tdls_info(padapter);
- ptdlsinfo->tdls_enable = _TRUE;
#ifdef CONFIG_TDLS_DRIVER_SETUP
ptdlsinfo->driver_setup = _TRUE;
#else
@@ -94,6 +95,60 @@ void rtw_free_tdls_info(struct tdls_info *ptdlsinfo)
}
+void rtw_free_all_tdls_sta(_adapter *padapter, u8 enqueue_cmd)
+{
+ struct sta_priv *pstapriv = &padapter->stapriv;
+ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
+ _irqL irqL;
+ _list *plist, *phead;
+ s32 index;
+ struct sta_info *psta = NULL;
+ struct sta_info *ptdls_sta[NUM_STA];
+ u8 empty_hwaddr[ETH_ALEN] = { 0x00 };
+
+ _rtw_memset(ptdls_sta, 0x00, sizeof(ptdls_sta));
+
+ _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+ for (index = 0; index < NUM_STA; index++) {
+ phead = &(pstapriv->sta_hash[index]);
+ plist = get_next(phead);
+
+ while (rtw_end_of_queue_search(phead, plist) == _FALSE) {
+ psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
+
+ plist = get_next(plist);
+
+ if (psta->tdls_sta_state != TDLS_STATE_NONE)
+ ptdls_sta[index] = psta;
+ }
+ }
+ _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+
+ for (index = 0; index < NUM_STA; index++) {
+ if (ptdls_sta[index]) {
+ struct TDLSoption_param tdls_param;
+
+ psta = ptdls_sta[index];
+
+ RTW_INFO("Do tear down to "MAC_FMT" by enqueue_cmd = %d\n", MAC_ARG(psta->cmn.mac_addr), enqueue_cmd);
+
+ _rtw_memcpy(&(tdls_param.addr), psta->cmn.mac_addr, ETH_ALEN);
+ tdls_param.option = TDLS_TEARDOWN_STA_NO_WAIT;
+ tdls_hdl(padapter, (unsigned char *)&(tdls_param));
+
+ rtw_tdls_teardown_pre_hdl(padapter, psta);
+
+ if (enqueue_cmd == _TRUE)
+ rtw_tdls_cmd(padapter, psta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST);
+ else
+ {
+ tdls_param.option = TDLS_TEARDOWN_STA_LOCALLY_POST;
+ tdls_hdl(padapter, (unsigned char *)&(tdls_param));
+ }
+ }
+ }
+}
+
int check_ap_tdls_prohibited(u8 *pframe, u8 pkt_len)
{
u8 tdls_prohibited_bit = 0x40; /* bit(38); TDLS_prohibited */
@@ -122,10 +177,86 @@ int check_ap_tdls_ch_switching_prohibited(u8 *pframe, u8 pkt_len)
return _FALSE;
}
+u8 rtw_is_tdls_enabled(_adapter *padapter)
+{
+ return padapter->registrypriv.en_tdls;
+}
+
+void rtw_set_tdls_enable(_adapter *padapter, u8 enable)
+{
+ padapter->registrypriv.en_tdls = enable;
+ RTW_INFO("%s: en_tdls = %d\n", __func__, rtw_is_tdls_enabled(padapter));
+}
+
+void rtw_enable_tdls_func(_adapter *padapter)
+{
+ if (rtw_is_tdls_enabled(padapter) == _TRUE)
+ return;
+
+#if 0
+#ifdef CONFIG_MCC_MODE
+ if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC) == _TRUE) {
+ RTW_INFO("[TDLS] MCC is running, can't enable TDLS !\n");
+ return;
+ }
+#endif
+#endif
+ rtw_set_tdls_enable(padapter, _TRUE);
+}
+
+void rtw_disable_tdls_func(_adapter *padapter, u8 enqueue_cmd)
+{
+ if (rtw_is_tdls_enabled(padapter) == _FALSE)
+ return;
+
+ rtw_free_all_tdls_sta(padapter, enqueue_cmd);
+ rtw_tdls_cmd(padapter, NULL, TDLS_RS_RCR);
+ rtw_reset_tdls_info(padapter);
+
+ rtw_set_tdls_enable(padapter, _FALSE);
+}
+
+u8 rtw_is_tdls_sta_existed(_adapter *padapter)
+{
+ struct sta_priv *pstapriv = &padapter->stapriv;
+ struct sta_info *psta;
+ int i = 0;
+ _irqL irqL;
+ _list *plist, *phead;
+ u8 ret = _FALSE;
+
+ if (rtw_is_tdls_enabled(padapter) == _FALSE)
+ return _FALSE;
+
+ _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+
+ for (i = 0; i < NUM_STA; i++) {
+ phead = &(pstapriv->sta_hash[i]);
+ plist = get_next(phead);
+ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+ psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
+ plist = get_next(plist);
+ if (psta->tdls_sta_state != TDLS_STATE_NONE) {
+ ret = _TRUE;
+ goto Exit;
+ }
+ }
+ }
+
+Exit:
+
+ _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
+
+ return ret;
+}
+
u8 rtw_tdls_is_setup_allowed(_adapter *padapter)
{
struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
+ if (is_client_associated_to_ap(padapter) == _FALSE)
+ return _FALSE;
+
if (ptdlsinfo->ap_prohibited == _TRUE)
return _FALSE;
@@ -147,7 +278,7 @@ u8 rtw_tdls_is_chsw_allowed(_adapter *padapter)
}
#endif
-int _issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsigned int power_mode, int wait_ack)
+int _issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsigned int power_mode, int wait_ms)
{
int ret = _FAIL;
struct xmit_frame *pmgntframe;
@@ -198,15 +329,15 @@ int _issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsi
SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
pmlmeext->mgnt_seq++;
- SetFrameSubType(pframe, WIFI_QOS_DATA_NULL);
+ set_frame_sub_type(pframe, WIFI_QOS_DATA_NULL);
pframe += sizeof(struct rtw_ieee80211_hdr_3addr_qos);
pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos);
pattrib->last_txcmdsz = pattrib->pktlen;
- if (wait_ack)
- ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe);
+ if (wait_ms)
+ ret = dump_mgntframe_and_wait_ack_timeout(padapter, pmgntframe, wait_ms);
else {
dump_mgntframe(padapter, pmgntframe);
ret = _SUCCESS;
@@ -226,7 +357,7 @@ int issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsig
{
int ret;
int i = 0;
- u32 start = rtw_get_current_time();
+ systime start = rtw_get_current_time();
struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
@@ -234,9 +365,9 @@ int issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsig
psta = rtw_get_stainfo(&padapter->stapriv, da);
if (psta) {
if (power_mode)
- rtw_hal_macid_sleep(padapter, psta->mac_id);
+ rtw_hal_macid_sleep(padapter, psta->cmn.mac_id);
else
- rtw_hal_macid_wakeup(padapter, psta->mac_id);
+ rtw_hal_macid_wakeup(padapter, psta->cmn.mac_id);
} else {
RTW_INFO(FUNC_ADPT_FMT ": Can't find sta info for " MAC_FMT ", skip macid %s!!\n",
FUNC_ADPT_ARG(padapter), MAC_ARG(da), power_mode ? "sleep" : "wakeup");
@@ -245,7 +376,7 @@ int issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsig
#endif
do {
- ret = _issue_nulldata_to_TDLS_peer_STA(padapter, da, power_mode, wait_ms > 0 ? _TRUE : _FALSE);
+ ret = _issue_nulldata_to_TDLS_peer_STA(padapter, da, power_mode, wait_ms);
i++;
@@ -278,37 +409,6 @@ int issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsig
return ret;
}
-void free_tdls_sta(_adapter *padapter, struct sta_info *ptdls_sta)
-{
- struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
- struct sta_priv *pstapriv = &padapter->stapriv;
- _irqL irqL;
-
- /* free peer sta_info */
- _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
- if (ptdlsinfo->sta_cnt != 0)
- ptdlsinfo->sta_cnt--;
- _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
- /* -2: AP + BC/MC sta, -4: default key */
- if (ptdlsinfo->sta_cnt < MAX_ALLOWED_TDLS_STA_NUM) {
- ptdlsinfo->sta_maximum = _FALSE;
- _rtw_memset(&ptdlsinfo->ss_record, 0x00, sizeof(struct tdls_ss_record));
- }
-
- /* clear cam */
- rtw_clearstakey_cmd(padapter, ptdls_sta, _TRUE);
-
- if (ptdlsinfo->sta_cnt == 0) {
- rtw_tdls_cmd(padapter, NULL, TDLS_RS_RCR);
- ptdlsinfo->link_established = _FALSE;
- } else
- RTW_INFO("Remain tdls sta:%02x\n", ptdlsinfo->sta_cnt);
-
- rtw_free_stainfo(padapter, ptdls_sta);
-
-}
-
-
/* TDLS encryption(if needed) will always be CCMP */
void rtw_tdls_set_key(_adapter *padapter, struct sta_info *ptdls_sta)
{
@@ -333,8 +433,10 @@ void rtw_tdls_process_ht_cap(_adapter *padapter, struct sta_info *ptdls_sta, u8
ptdls_sta->flags |= WLAN_STA_WME;
_rtw_memcpy(&ptdls_sta->htpriv.ht_cap, data, sizeof(struct rtw_ieee80211_ht_cap));
- } else
+ } else {
ptdls_sta->flags &= ~WLAN_STA_HT;
+ return;
+ }
if (ptdls_sta->flags & WLAN_STA_HT) {
if (padapter->registrypriv.ht_enable == _TRUE) {
@@ -366,17 +468,17 @@ void rtw_tdls_process_ht_cap(_adapter *padapter, struct sta_info *ptdls_sta, u8
ptdls_sta->htpriv.rx_ampdu_min_spacing = max_AMPDU_len | min_MPDU_spacing;
/* Check if sta support s Short GI 20M */
- if (ptdls_sta->htpriv.ht_cap.cap_info & cpu_to_le16(IEEE80211_HT_CAP_SGI_20))
+ if ((phtpriv->sgi_20m == _TRUE) && (ptdls_sta->htpriv.ht_cap.cap_info & cpu_to_le16(IEEE80211_HT_CAP_SGI_20)))
ptdls_sta->htpriv.sgi_20m = _TRUE;
/* Check if sta support s Short GI 40M */
- if (ptdls_sta->htpriv.ht_cap.cap_info & cpu_to_le16(IEEE80211_HT_CAP_SGI_40))
+ if ((phtpriv->sgi_40m == _TRUE) && (ptdls_sta->htpriv.ht_cap.cap_info & cpu_to_le16(IEEE80211_HT_CAP_SGI_40)))
ptdls_sta->htpriv.sgi_40m = _TRUE;
/* Bwmode would still followed AP's setting */
if (ptdls_sta->htpriv.ht_cap.cap_info & cpu_to_le16(IEEE80211_HT_CAP_SUP_WIDTH)) {
if (padapter->mlmeextpriv.cur_bwmode >= CHANNEL_WIDTH_40)
- ptdls_sta->bw_mode = CHANNEL_WIDTH_40;
+ ptdls_sta->cmn.bw_mode = CHANNEL_WIDTH_40;
ptdls_sta->htpriv.ch_offset = padapter->mlmeextpriv.cur_ch_offset;
}
@@ -415,6 +517,11 @@ u8 *rtw_tdls_set_ht_cap(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattr
{
rtw_ht_use_default_setting(padapter);
+ if (padapter->registrypriv.wifi_spec == 1) {
+ padapter->mlmepriv.htpriv.sgi_20m = _FALSE;
+ padapter->mlmepriv.htpriv.sgi_40m = _FALSE;
+ }
+
rtw_restructure_ht_ie(padapter, NULL, pframe, 0, &(pattrib->pktlen), padapter->mlmeextpriv.cur_channel);
return pframe + pattrib->pktlen;
@@ -424,11 +531,12 @@ u8 *rtw_tdls_set_ht_cap(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattr
#ifdef CONFIG_80211AC_VHT
void rtw_tdls_process_vht_cap(_adapter *padapter, struct sta_info *ptdls_sta, u8 *data, u8 Length)
{
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
+ struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
- u8 cur_ldpc_cap = 0, cur_stbc_cap = 0, cur_beamform_cap = 0, rf_type = RF_1T1R;
+ u8 cur_ldpc_cap = 0, cur_stbc_cap = 0, cur_beamform_cap = 0, rf_type = RF_1T1R, tx_nss = 0;
u8 *pcap_mcs;
- u8 vht_mcs[2];
_rtw_memset(&ptdls_sta->vhtpriv, 0, sizeof(struct vht_priv));
if (data && Length == 12) {
@@ -444,13 +552,15 @@ void rtw_tdls_process_vht_cap(_adapter *padapter, struct sta_info *ptdls_sta, u8
#else
ptdls_sta->vhtpriv.vht_op_mode_notify = CHANNEL_WIDTH_80;
#endif
- } else
+ } else {
ptdls_sta->flags &= ~WLAN_STA_VHT;
+ return;
+ }
if (ptdls_sta->flags & WLAN_STA_VHT) {
if (REGSTY_IS_11AC_ENABLE(&padapter->registrypriv)
&& hal_chk_proto_cap(padapter, PROTO_CAP_11AC)
- && (!pmlmepriv->country_ent || COUNTRY_CHPLAN_EN_11AC(pmlmepriv->country_ent)))
+ && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent)))
ptdls_sta->vhtpriv.vht_option = _TRUE;
else
ptdls_sta->vhtpriv.vht_option = _FALSE;
@@ -475,6 +585,7 @@ void rtw_tdls_process_vht_cap(_adapter *padapter, struct sta_info *ptdls_sta, u8
}
ptdls_sta->vhtpriv.stbc_cap = cur_stbc_cap;
+ #ifdef CONFIG_BEAMFORMING
/* B11 SU Beamformer Capable, the target supports Beamformer and we are Beamformee */
if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE) &&
GET_VHT_CAPABILITY_ELE_SU_BFEE(data))
@@ -487,24 +598,66 @@ void rtw_tdls_process_vht_cap(_adapter *padapter, struct sta_info *ptdls_sta, u8
ptdls_sta->vhtpriv.beamform_cap = cur_beamform_cap;
if (cur_beamform_cap)
RTW_INFO("Current VHT Beamforming Setting = %02X\n", cur_beamform_cap);
+ #endif /*CONFIG_BEAMFORMING*/
/* B23 B24 B25 Maximum A-MPDU Length Exponent */
ptdls_sta->vhtpriv.ampdu_len = GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(data);
pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(data);
- _rtw_memcpy(vht_mcs, pcap_mcs, 2);
-
rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
- if ((rf_type == RF_1T1R) || (rf_type == RF_1T2R))
- vht_mcs[0] |= 0xfc;
- else if (rf_type == RF_2T2R)
- vht_mcs[0] |= 0xf0;
- else if (rf_type == RF_3T3R)
- vht_mcs[0] |= 0xc0;
+ tx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num);
+ rtw_vht_nss_to_mcsmap(tx_nss, ptdls_sta->vhtpriv.vht_mcs_map, pcap_mcs);
+ ptdls_sta->vhtpriv.vht_highest_rate = rtw_get_vht_highest_rate(ptdls_sta->vhtpriv.vht_mcs_map);
+}
- _rtw_memcpy(ptdls_sta->vhtpriv.vht_mcs_map, vht_mcs, 2);
+void rtw_tdls_process_vht_operation(_adapter *padapter, struct sta_info *ptdls_sta, u8 *data, u8 Length)
+{
+ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+ struct registry_priv *regsty = adapter_to_regsty(padapter);
+ u8 operation_bw = 0;
- ptdls_sta->vhtpriv.vht_highest_rate = rtw_get_vht_highest_rate(ptdls_sta->vhtpriv.vht_mcs_map);
+ if (GET_VHT_OPERATION_ELE_CHL_WIDTH(data) >= 1) {
+
+ operation_bw = CHANNEL_WIDTH_80;
+
+ if (hal_is_bw_support(padapter, operation_bw) && REGSTY_IS_BW_5G_SUPPORT(regsty, operation_bw)
+ && (operation_bw <= pmlmeext->cur_bwmode))
+ ptdls_sta->cmn.bw_mode = operation_bw;
+ else
+ ptdls_sta->cmn.bw_mode = pmlmeext->cur_bwmode;
+ } else
+ ptdls_sta->cmn.bw_mode = pmlmeext->cur_bwmode;
+}
+
+void rtw_tdls_process_vht_op_mode_notify(_adapter *padapter, struct sta_info *ptdls_sta, u8 *data, u8 Length)
+{
+ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+ struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
+ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+ struct registry_priv *regsty = adapter_to_regsty(padapter);
+ u8 target_bw;
+ u8 target_rxss, current_rxss;
+
+ if (pvhtpriv->vht_option == _FALSE)
+ return;
+
+ target_bw = GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(data);
+ target_rxss = (GET_VHT_OPERATING_MODE_FIELD_RX_NSS(data) + 1);
+
+ if (hal_is_bw_support(padapter, target_bw) && REGSTY_IS_BW_5G_SUPPORT(regsty, target_bw)
+ && (target_bw <= pmlmeext->cur_bwmode))
+ ptdls_sta->cmn.bw_mode = target_bw;
+ else
+ ptdls_sta->cmn.bw_mode = pmlmeext->cur_bwmode;
+
+ current_rxss = rtw_vht_mcsmap_to_nss(ptdls_sta->vhtpriv.vht_mcs_map);
+ if (target_rxss != current_rxss) {
+ u8 vht_mcs_map[2] = {};
+
+ rtw_vht_nss_to_mcsmap(target_rxss, vht_mcs_map, ptdls_sta->vhtpriv.vht_mcs_map);
+ _rtw_memcpy(ptdls_sta->vhtpriv.vht_mcs_map, vht_mcs_map, 2);
+ }
}
u8 *rtw_tdls_set_aid(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib)
@@ -546,20 +699,22 @@ u8 *rtw_tdls_set_vht_op_mode_notify(_adapter *padapter, u8 *pframe, struct pkt_a
#endif
-u8 *rtw_tdls_set_sup_ch(struct mlme_ext_priv *pmlmeext, u8 *pframe, struct pkt_attrib *pattrib)
+u8 *rtw_tdls_set_sup_ch(_adapter *adapter, u8 *pframe, struct pkt_attrib *pattrib)
{
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
u8 sup_ch[30 * 2] = {0x00}, ch_set_idx = 0, sup_ch_idx = 2;
- do {
- if (pmlmeext->channel_set[ch_set_idx].ChannelNum <= 14) {
+ while (ch_set_idx < rfctl->max_chan_nums && rfctl->channel_set[ch_set_idx].ChannelNum != 0) {
+ if (rfctl->channel_set[ch_set_idx].ChannelNum <= 14) {
+ /* TODO: fix 2.4G supported channel when channel doesn't start from 1 and continuous */
sup_ch[0] = 1; /* First channel number */
- sup_ch[1] = pmlmeext->channel_set[ch_set_idx].ChannelNum; /* Number of channel */
+ sup_ch[1] = rfctl->channel_set[ch_set_idx].ChannelNum; /* Number of channel */
} else {
- sup_ch[sup_ch_idx++] = pmlmeext->channel_set[ch_set_idx].ChannelNum;
+ sup_ch[sup_ch_idx++] = rfctl->channel_set[ch_set_idx].ChannelNum;
sup_ch[sup_ch_idx++] = 1;
}
ch_set_idx++;
- } while (pmlmeext->channel_set[ch_set_idx].ChannelNum != 0 && ch_set_idx < MAX_CHANNEL_NUM);
+ }
return rtw_set_ie(pframe, _SUPPORTED_CH_IE_, sup_ch_idx, sup_ch, &(pattrib->pktlen));
}
@@ -606,7 +761,9 @@ u8 *rtw_tdls_set_ftie(struct tdls_txmgmt *ptxmgmt, u8 *pframe, struct pkt_attrib
_rtw_memcpy(FTIE.Anonce, ANonce, WPA_NONCE_LEN);
if (SNonce != NULL)
_rtw_memcpy(FTIE.Snonce, SNonce, WPA_NONCE_LEN);
- return rtw_set_ie(pframe, _FTIE_ , 82, (u8 *)FTIE.mic_ctrl, &(pattrib->pktlen));
+
+ return rtw_set_ie(pframe, _FTIE_, TDLS_FTIE_DATA_LEN,
+ (u8 *)FTIE.data, &(pattrib->pktlen));
}
}
@@ -725,15 +882,19 @@ u8 *rtw_tdls_set_sup_reg_class(u8 *pframe, struct pkt_attrib *pattrib)
return rtw_set_ie(pframe, _SRC_IE_ , sizeof(TDLS_SRC), TDLS_SRC, &(pattrib->pktlen));
}
-u8 *rtw_tdls_set_linkid(u8 *pframe, struct pkt_attrib *pattrib, u8 init)
+u8 *rtw_tdls_set_linkid(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib, u8 init)
{
+ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
+ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+
u8 link_id_addr[18] = {0};
+
+ _rtw_memcpy(link_id_addr, get_my_bssid(&(pmlmeinfo->network)), 6);
+
if (init == _TRUE) {
- _rtw_memcpy(link_id_addr, pattrib->ra, 6);
_rtw_memcpy((link_id_addr + 6), pattrib->src, 6);
_rtw_memcpy((link_id_addr + 12), pattrib->dst, 6);
} else {
- _rtw_memcpy(link_id_addr, pattrib->ra, 6);
_rtw_memcpy((link_id_addr + 6), pattrib->dst, 6);
_rtw_memcpy((link_id_addr + 12), pattrib->src, 6);
}
@@ -766,6 +927,20 @@ u8 *rtw_tdls_set_ch_sw(u8 *pframe, struct pkt_attrib *pattrib, struct sta_info *
void rtw_tdls_set_ch_sw_oper_control(_adapter *padapter, u8 enable)
{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+
+ if (enable == _TRUE) {
+#ifdef CONFIG_TDLS_CH_SW_V2
+ pHalData->ch_switch_offload = _TRUE;
+#endif
+
+#ifdef CONFIG_TDLS_CH_SW_BY_DRV
+ pHalData->ch_switch_offload = _FALSE;
+#endif
+ }
+ else
+ pHalData->ch_switch_offload = _FALSE;
+
if (ATOMIC_READ(&padapter->tdlsinfo.chsw_info.chsw_on) != enable)
ATOMIC_SET(&padapter->tdlsinfo.chsw_info.chsw_on, enable);
@@ -816,10 +991,14 @@ s32 rtw_tdls_do_ch_sw(_adapter *padapter, struct sta_info *ptdls_sta, u8 chnl_ty
ch_sw_time_start = rtw_systime_to_ms(rtw_get_current_time());
- rtw_tdls_chsw_oper_init(padapter, TDLS_CH_SWITCH_OPER_OFFLOAD_TIMEOUT);
-
/* set mac_id sleep before channel switch */
- rtw_hal_macid_sleep(padapter, ptdls_sta->mac_id);
+ rtw_hal_macid_sleep(padapter, ptdls_sta->cmn.mac_id);
+
+#if defined(CONFIG_TDLS_CH_SW_BY_DRV) || defined(CONFIG_TDLS_CH_SW_V2)
+ set_channel_bwmode(padapter, channel, channel_offset, bwmode);
+ ret = _SUCCESS;
+#else
+ rtw_tdls_chsw_oper_init(padapter, TDLS_CH_SWITCH_OPER_OFFLOAD_TIMEOUT);
/* channel switch IOs offload to FW */
if (rtw_hal_ch_sw_oper_offload(padapter, channel, channel_offset, bwmode) == _SUCCESS) {
@@ -832,9 +1011,9 @@ s32 rtw_tdls_do_ch_sw(_adapter *padapter, struct sta_info *ptdls_sta, u8 chnl_ty
rtw_set_oper_bw(padapter, bwmode);
center_ch = rtw_get_center_ch(channel, bwmode, channel_offset);
- pHalData->CurrentChannel = center_ch;
+ pHalData->current_channel = center_ch;
pHalData->CurrentCenterFrequencyIndex1 = center_ch;
- pHalData->CurrentChannelBW = bwmode;
+ pHalData->current_channel_bw = bwmode;
pHalData->nCur40MhzPrimeSC = channel_offset;
if (bwmode == CHANNEL_WIDTH_80) {
@@ -855,25 +1034,27 @@ s32 rtw_tdls_do_ch_sw(_adapter *padapter, struct sta_info *ptdls_sta, u8 chnl_ty
if (take_care_iqk == _TRUE)
rtw_hal_ch_sw_iqk_info_restore(padapter, CH_SW_USE_CASE_TDLS);
- ch_sw_time_spent = rtw_systime_to_ms(rtw_get_current_time()) - ch_sw_time_start;
-
- if (chnl_type == TDLS_CH_SW_OFF_CHNL) {
- if ((u32)ch_switch_time / 1000 > ch_sw_time_spent)
- wait_time = (u32)ch_switch_time / 1000 - ch_sw_time_spent;
- else
- wait_time = 0;
-
- if (wait_time > 0)
- rtw_msleep_os(wait_time);
- }
-
ret = _SUCCESS;
} else
RTW_INFO("[TDLS] chsw oper wait fail !!\n");
}
+#endif
+
+ if (ret == _SUCCESS) {
+ ch_sw_time_spent = rtw_systime_to_ms(rtw_get_current_time()) - ch_sw_time_start;
+ if (chnl_type == TDLS_CH_SW_OFF_CHNL) {
+ if ((u32)ch_switch_time / 1000 > ch_sw_time_spent)
+ wait_time = (u32)ch_switch_time / 1000 - ch_sw_time_spent;
+ else
+ wait_time = 0;
+
+ if (wait_time > 0)
+ rtw_msleep_os(wait_time);
+ }
+ }
/* set mac_id wakeup after channel switch */
- rtw_hal_macid_wakeup(padapter, ptdls_sta->mac_id);
+ rtw_hal_macid_wakeup(padapter, ptdls_sta->cmn.mac_id);
return ret;
}
@@ -1035,27 +1216,24 @@ int issue_tdls_setup_req(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, int wa
RTW_INFO("[TDLS] %s\n", __FUNCTION__);
- ptxmgmt->action_code = TDLS_SETUP_REQUEST;
if (rtw_tdls_is_setup_allowed(padapter) == _FALSE)
goto exit;
- pmgntframe = alloc_mgtxmitframe(pxmitpriv);
- if (pmgntframe == NULL)
+ if (IS_MCAST(ptxmgmt->peer))
goto exit;
- pattrib = &pmgntframe->attrib;
- pmgntframe->frame_tag = DATA_FRAMETAG;
- pattrib->ether_type = 0x890d;
-
- _rtw_memcpy(pattrib->dst, ptxmgmt->peer, ETH_ALEN);
- _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
- _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);
- _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
+ ptdls_sta = rtw_get_stainfo(pstapriv, ptxmgmt->peer);
+ if (ptdlsinfo->sta_maximum == _TRUE) {
+ if (ptdls_sta == NULL)
+ goto exit;
+ else if (!(ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE))
+ goto exit;
+ }
- update_tdls_attrib(padapter, pattrib);
+ pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+ if (pmgntframe == NULL)
+ goto exit;
- /* init peer sta_info */
- ptdls_sta = rtw_get_stainfo(pstapriv, ptxmgmt->peer);
if (ptdls_sta == NULL) {
ptdls_sta = rtw_alloc_stainfo(pstapriv, ptxmgmt->peer);
if (ptdls_sta == NULL) {
@@ -1064,10 +1242,21 @@ int issue_tdls_setup_req(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, int wa
rtw_free_xmitframe(pxmitpriv, pmgntframe);
goto exit;
}
+ ptdlsinfo->sta_cnt++;
}
- if (!(ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE))
- ptdlsinfo->sta_cnt++;
+ ptxmgmt->action_code = TDLS_SETUP_REQUEST;
+
+ pattrib = &pmgntframe->attrib;
+ pmgntframe->frame_tag = DATA_FRAMETAG;
+ pattrib->ether_type = 0x890d;
+
+ _rtw_memcpy(pattrib->dst, ptxmgmt->peer, ETH_ALEN);
+ _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
+ _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);
+ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
+
+ update_tdls_attrib(padapter, pattrib);
if (ptdlsinfo->sta_cnt == MAX_ALLOWED_TDLS_STA_NUM)
ptdlsinfo->sta_maximum = _TRUE;
@@ -1099,25 +1288,19 @@ int issue_tdls_setup_req(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, int wa
return ret;
}
-int _issue_tdls_teardown(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, u8 wait_ack)
+int _issue_tdls_teardown(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta, u8 wait_ack)
{
struct xmit_frame *pmgntframe;
struct pkt_attrib *pattrib;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
struct sta_priv *pstapriv = &padapter->stapriv;
- struct sta_info *ptdls_sta = NULL;
_irqL irqL;
int ret = _FAIL;
RTW_INFO("[TDLS] %s\n", __FUNCTION__);
ptxmgmt->action_code = TDLS_TEARDOWN;
- ptdls_sta = rtw_get_stainfo(pstapriv, ptxmgmt->peer);
- if (ptdls_sta == NULL) {
- RTW_INFO("Np tdls_sta for tearing down\n");
- goto exit;
- }
pmgntframe = alloc_mgtxmitframe(pxmitpriv);
if (pmgntframe == NULL)
@@ -1133,7 +1316,12 @@ int _issue_tdls_teardown(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, u8 wai
_rtw_memcpy(pattrib->dst, ptxmgmt->peer, ETH_ALEN);
_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
- _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);
+
+ if (ptxmgmt->status_code == _RSON_TDLS_TEAR_UN_RSN_)
+ _rtw_memcpy(pattrib->ra, ptxmgmt->peer, ETH_ALEN);
+ else
+ _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);
+
_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
update_tdls_attrib(padapter, pattrib);
@@ -1156,9 +1344,6 @@ int _issue_tdls_teardown(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, u8 wai
ret = _SUCCESS;
}
- if (rtw_tdls_is_driver_setup(padapter))
- rtw_tdls_cmd(padapter, ptxmgmt->peer, TDLS_TEARDOWN_STA_LOCALLY);
-
exit:
return ret;
@@ -1166,15 +1351,28 @@ int _issue_tdls_teardown(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, u8 wai
int issue_tdls_teardown(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, u8 wait_ack)
{
+ struct sta_info *ptdls_sta = NULL;
int ret = _FAIL;
- ret = _issue_tdls_teardown(padapter, ptxmgmt, wait_ack);
+ ptdls_sta = rtw_get_stainfo(&(padapter->stapriv), ptxmgmt->peer);
+ if (ptdls_sta == NULL) {
+ RTW_INFO("No tdls_sta for tearing down\n");
+ goto exit;
+ }
+
+ ret = _issue_tdls_teardown(padapter, ptxmgmt, ptdls_sta, wait_ack);
if ((ptxmgmt->status_code == _RSON_TDLS_TEAR_UN_RSN_) && (ret == _FAIL)) {
/* Change status code and send teardown again via AP */
ptxmgmt->status_code = _RSON_TDLS_TEAR_TOOFAR_;
- ret = _issue_tdls_teardown(padapter, ptxmgmt, wait_ack);
+ ret = _issue_tdls_teardown(padapter, ptxmgmt, ptdls_sta, wait_ack);
}
+ if (rtw_tdls_is_driver_setup(padapter)) {
+ rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);
+ rtw_tdls_cmd(padapter, ptxmgmt->peer, TDLS_TEARDOWN_STA_LOCALLY_POST);
+ }
+
+exit:
return ret;
}
@@ -1338,7 +1536,7 @@ int issue_tdls_dis_rsp(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, u8 priva
SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq);
pmlmeext->mgnt_seq++;
- SetFrameSubType(pframe, WIFI_ACTION);
+ set_frame_sub_type(pframe, WIFI_ACTION);
pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
@@ -1376,9 +1574,9 @@ int issue_tdls_peer_traffic_rsp(_adapter *padapter, struct sta_info *ptdls_sta,
pmgntframe->frame_tag = DATA_FRAMETAG;
pattrib->ether_type = 0x890d;
- _rtw_memcpy(pattrib->dst, ptdls_sta->hwaddr, ETH_ALEN);
+ _rtw_memcpy(pattrib->dst, ptdls_sta->cmn.mac_addr, ETH_ALEN);
_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
- _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);
+ _rtw_memcpy(pattrib->ra, ptdls_sta->cmn.mac_addr, ETH_ALEN);
_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
update_tdls_attrib(padapter, pattrib);
@@ -1421,7 +1619,7 @@ int issue_tdls_peer_traffic_indication(_adapter *padapter, struct sta_info *ptdl
pmgntframe->frame_tag = DATA_FRAMETAG;
pattrib->ether_type = 0x890d;
- _rtw_memcpy(pattrib->dst, ptdls_sta->hwaddr, ETH_ALEN);
+ _rtw_memcpy(pattrib->dst, ptdls_sta->cmn.mac_addr, ETH_ALEN);
_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
_rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);
_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
@@ -1474,9 +1672,9 @@ int issue_tdls_ch_switch_req(_adapter *padapter, struct sta_info *ptdls_sta)
pmgntframe->frame_tag = DATA_FRAMETAG;
pattrib->ether_type = 0x890d;
- _rtw_memcpy(pattrib->dst, ptdls_sta->hwaddr, ETH_ALEN);
+ _rtw_memcpy(pattrib->dst, ptdls_sta->cmn.mac_addr, ETH_ALEN);
_rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
- _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN);
+ _rtw_memcpy(pattrib->ra, ptdls_sta->cmn.mac_addr, ETH_ALEN);
_rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
update_tdls_attrib(padapter, pattrib);
@@ -1560,10 +1758,13 @@ int On_TDLS_Dis_Rsp(_adapter *padapter, union recv_frame *precv_frame)
struct rx_pkt_attrib *pattrib = &(precv_frame->u.hdr.attrib);
struct tdls_info *ptdlsinfo = &(padapter->tdlsinfo);
u8 empty_addr[ETH_ALEN] = { 0x00 };
- int UndecoratedSmoothedPWDB;
+ int rssi = 0;
struct tdls_txmgmt txmgmt;
int ret = _SUCCESS;
+ if (psta)
+ rssi = psta->cmn.rssi_stat.rssi;
+
_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
/* WFDTDLS: for sigma test, not to setup direct link automatically */
ptdlsinfo->dev_discovered = _TRUE;
@@ -1579,11 +1780,11 @@ int On_TDLS_Dis_Rsp(_adapter *padapter, union recv_frame *precv_frame)
if (ptdlsinfo->sta_maximum == _TRUE && ptdls_sta->alive_count >= 1) {
if (_rtw_memcmp(ptdlsinfo->ss_record.macaddr, empty_addr, ETH_ALEN)) {
_rtw_memcpy(ptdlsinfo->ss_record.macaddr, psa, ETH_ALEN);
- ptdlsinfo->ss_record.RxPWDBAll = pattrib->phy_info.RxPWDBAll;
+ ptdlsinfo->ss_record.RxPWDBAll = pattrib->phy_info.rx_pwdb_all;
} else {
- if (ptdlsinfo->ss_record.RxPWDBAll < pattrib->phy_info.RxPWDBAll) {
+ if (ptdlsinfo->ss_record.RxPWDBAll < pattrib->phy_info.rx_pwdb_all) {
_rtw_memcpy(ptdlsinfo->ss_record.macaddr, psa, ETH_ALEN);
- ptdlsinfo->ss_record.RxPWDBAll = pattrib->phy_info.RxPWDBAll;
+ ptdlsinfo->ss_record.RxPWDBAll = pattrib->phy_info.rx_pwdb_all;
}
}
}
@@ -1594,7 +1795,7 @@ int On_TDLS_Dis_Rsp(_adapter *padapter, union recv_frame *precv_frame)
ret = _FAIL;
goto exit;
} else {
- if (pattrib->phy_info.RxPWDBAll > ptdlsinfo->ss_record.RxPWDBAll) {
+ if (pattrib->phy_info.rx_pwdb_all > ptdlsinfo->ss_record.RxPWDBAll) {
_rtw_memcpy(txmgmt.peer, ptdlsinfo->ss_record.macaddr, ETH_ALEN);
/* issue_tdls_teardown(padapter, ptdlsinfo->ss_record.macaddr, _FALSE); */
} else {
@@ -1604,10 +1805,9 @@ int On_TDLS_Dis_Rsp(_adapter *padapter, union recv_frame *precv_frame)
}
}
- rtw_hal_get_def_var(padapter, HAL_DEF_UNDERCORATEDSMOOTHEDPWDB, &UndecoratedSmoothedPWDB);
- if (pattrib->phy_info.RxPWDBAll + TDLS_SIGNAL_THRESH >= UndecoratedSmoothedPWDB) {
- RTW_INFO("pattrib->RxPWDBAll=%d, pdmpriv->UndecoratedSmoothedPWDB=%d\n", pattrib->phy_info.RxPWDBAll, UndecoratedSmoothedPWDB);
+ if (pattrib->phy_info.rx_pwdb_all + TDLS_SIGNAL_THRESH >= rssi) {
+ RTW_INFO("pattrib->RxPWDBAll=%d, pdmpriv->undecorated_smoothed_pwdb=%d\n", pattrib->phy_info.rx_pwdb_all, rssi);
_rtw_memcpy(txmgmt.peer, psa, ETH_ALEN);
issue_tdls_setup_req(padapter, &txmgmt, _FALSE);
}
@@ -1619,11 +1819,10 @@ int On_TDLS_Dis_Rsp(_adapter *padapter, union recv_frame *precv_frame)
}
-sint On_TDLS_Setup_Req(_adapter *padapter, union recv_frame *precv_frame)
+sint On_TDLS_Setup_Req(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)
{
struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
u8 *psa, *pmyid;
- struct sta_info *ptdls_sta = NULL;
struct sta_priv *pstapriv = &padapter->stapriv;
u8 *ptr = precv_frame->u.hdr.rx_data;
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
@@ -1648,7 +1847,13 @@ sint On_TDLS_Setup_Req(_adapter *padapter, union recv_frame *precv_frame)
_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
psa = get_sa(ptr);
- ptdls_sta = rtw_get_stainfo(pstapriv, psa);
+
+ if (ptdlsinfo->sta_maximum == _TRUE) {
+ if (ptdls_sta == NULL)
+ goto exit;
+ else if (!(ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE))
+ goto exit;
+ }
pmyid = adapter_mac_addr(padapter);
ptr += prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN;
@@ -1658,11 +1863,15 @@ sint On_TDLS_Setup_Req(_adapter *padapter, union recv_frame *precv_frame)
- prx_pkt_attrib->icv_len
- LLC_HEADER_SIZE
- ETH_TYPE_LEN
- - PAYLOAD_TYPE_LEN
- - FIXED_IE;
+ - PAYLOAD_TYPE_LEN;
- if (ptdls_sta == NULL)
+ if (ptdls_sta == NULL) {
ptdls_sta = rtw_alloc_stainfo(pstapriv, psa);
+ if (ptdls_sta == NULL)
+ goto exit;
+
+ ptdlsinfo->sta_cnt++;
+ }
else {
if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) {
/* If the direct link is already set up */
@@ -1706,7 +1915,7 @@ sint On_TDLS_Setup_Req(_adapter *padapter, union recv_frame *precv_frame)
case _COUNTRY_IE_:
break;
case _EXT_SUPPORTEDRATES_IE_:
- if (supportRateNum <= sizeof(supportRate)) {
+ if (supportRateNum < sizeof(supportRate)) {
_rtw_memcpy(supportRate + supportRateNum, pIE->data, pIE->Length);
supportRateNum += pIE->Length;
}
@@ -1800,8 +2009,6 @@ sint On_TDLS_Setup_Req(_adapter *padapter, union recv_frame *precv_frame)
ptdls_sta->bssratelen = supportRateNum;
_rtw_memcpy(ptdls_sta->bssrateset, supportRate, supportRateNum);
- if (!(ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE))
- ptdlsinfo->sta_cnt++;
/* -2: AP + BC/MC sta, -4: default key */
if (ptdlsinfo->sta_cnt == MAX_ALLOWED_TDLS_STA_NUM)
ptdlsinfo->sta_maximum = _TRUE;
@@ -1820,8 +2027,10 @@ sint On_TDLS_Setup_Req(_adapter *padapter, union recv_frame *precv_frame)
if (txmgmt.status_code == _STATS_SUCCESSFUL_)
_set_timer(&ptdls_sta->handshake_timer, TDLS_HANDSHAKE_TIME);
- else
- free_tdls_sta(padapter, ptdls_sta);
+ else {
+ rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);
+ rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST);
+ }
}
exit:
@@ -1829,11 +2038,10 @@ sint On_TDLS_Setup_Req(_adapter *padapter, union recv_frame *precv_frame)
return _SUCCESS;
}
-int On_TDLS_Setup_Rsp(_adapter *padapter, union recv_frame *precv_frame)
+int On_TDLS_Setup_Rsp(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)
{
struct registry_priv *pregistrypriv = &padapter->registrypriv;
struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
- struct sta_info *ptdls_sta = NULL;
struct sta_priv *pstapriv = &padapter->stapriv;
u8 *ptr = precv_frame->u.hdr.rx_data;
_irqL irqL;
@@ -1855,13 +2063,6 @@ int On_TDLS_Setup_Rsp(_adapter *padapter, union recv_frame *precv_frame)
_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
psa = get_sa(ptr);
- ptdls_sta = rtw_get_stainfo(pstapriv, psa);
-
- if (ptdls_sta == NULL) {
- RTW_INFO("[%s] Direct Link Peer = "MAC_FMT" not found\n", __func__, MAC_ARG(psa));
- ret = _FAIL;
- goto exit;
- }
ptr += prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN;
parsing_length = ((union recv_frame *)precv_frame)->u.hdr.len
@@ -1870,14 +2071,14 @@ int On_TDLS_Setup_Rsp(_adapter *padapter, union recv_frame *precv_frame)
- prx_pkt_attrib->icv_len
- LLC_HEADER_SIZE
- ETH_TYPE_LEN
- - PAYLOAD_TYPE_LEN
- - FIXED_IE;
+ - PAYLOAD_TYPE_LEN;
_rtw_memcpy(&status_code, ptr + 2, 2);
if (status_code != 0) {
RTW_INFO("[TDLS] %s status_code = %d, free_tdls_sta\n", __FUNCTION__, status_code);
- free_tdls_sta(padapter, ptdls_sta);
+ rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);
+ rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST);
ret = _FAIL;
goto exit;
}
@@ -1896,7 +2097,7 @@ int On_TDLS_Setup_Rsp(_adapter *padapter, union recv_frame *precv_frame)
case _COUNTRY_IE_:
break;
case _EXT_SUPPORTEDRATES_IE_:
- if (supportRateNum <= sizeof(supportRate)) {
+ if (supportRateNum < sizeof(supportRate)) {
_rtw_memcpy(supportRate + supportRateNum, pIE->data, pIE->Length);
supportRateNum += pIE->Length;
}
@@ -1944,7 +2145,7 @@ int On_TDLS_Setup_Rsp(_adapter *padapter, union recv_frame *precv_frame)
rtw_tdls_process_vht_cap(padapter, ptdls_sta, pIE->data, pIE->Length);
break;
case EID_OpModeNotification:
- rtw_process_vht_op_mode_notify(padapter, pIE->data, ptdls_sta);
+ rtw_tdls_process_vht_op_mode_notify(padapter, ptdls_sta, pIE->data, pIE->Length);
break;
#endif
case EID_BSSCoexistence:
@@ -1968,35 +2169,31 @@ int On_TDLS_Setup_Rsp(_adapter *padapter, union recv_frame *precv_frame)
rtw_tdls_process_wfd_ie(ptdlsinfo, ptr + FIXED_IE, parsing_length);
#endif
- if (status_code != _STATS_SUCCESSFUL_)
- txmgmt.status_code = status_code;
- else {
- if (prx_pkt_attrib->encrypt) {
- if (verify_ccmp == 1) {
- txmgmt.status_code = _STATS_SUCCESSFUL_;
- if (rtw_tdls_is_driver_setup(padapter) == _TRUE) {
- wpa_tdls_generate_tpk(padapter, ptdls_sta);
- if (tdls_verify_mic(ptdls_sta->tpk.kck, 2, plinkid_ie, prsnie, ptimeout_ie, pftie) == _FAIL) {
- RTW_INFO("[TDLS] %s tdls_verify_mic fail, free_tdls_sta\n", __FUNCTION__);
- free_tdls_sta(padapter, ptdls_sta);
- ret = _FAIL;
- goto exit;
- }
- ptdls_sta->TDLS_PeerKey_Lifetime = timeout_interval;
+ if (prx_pkt_attrib->encrypt) {
+ if (verify_ccmp == 1) {
+ txmgmt.status_code = _STATS_SUCCESSFUL_;
+ if (rtw_tdls_is_driver_setup(padapter) == _TRUE) {
+ wpa_tdls_generate_tpk(padapter, ptdls_sta);
+ if (tdls_verify_mic(ptdls_sta->tpk.kck, 2, plinkid_ie, prsnie, ptimeout_ie, pftie) == _FAIL) {
+ RTW_INFO("[TDLS] %s tdls_verify_mic fail, free_tdls_sta\n", __FUNCTION__);
+ rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);
+ rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST);
+ ret = _FAIL;
+ goto exit;
}
- } else
- txmgmt.status_code = _STATS_INVALID_RSNIE_;
-
+ ptdls_sta->TDLS_PeerKey_Lifetime = timeout_interval;
+ }
} else
- txmgmt.status_code = _STATS_SUCCESSFUL_;
- }
+ txmgmt.status_code = _STATS_INVALID_RSNIE_;
+ } else
+ txmgmt.status_code = _STATS_SUCCESSFUL_;
if (rtw_tdls_is_driver_setup(padapter) == _TRUE) {
_rtw_memcpy(txmgmt.peer, prx_pkt_attrib->src, ETH_ALEN);
issue_tdls_setup_cfm(padapter, &txmgmt);
if (txmgmt.status_code == _STATS_SUCCESSFUL_) {
- ptdlsinfo->link_established = _TRUE;
+ rtw_tdls_set_link_established(padapter, _TRUE);
if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE) {
ptdls_sta->tdls_sta_state |= TDLS_LINKED_STATE;
@@ -2007,7 +2204,7 @@ int On_TDLS_Setup_Rsp(_adapter *padapter, union recv_frame *precv_frame)
if (prx_pkt_attrib->encrypt)
rtw_tdls_set_key(padapter, ptdls_sta);
- rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_ESTABLISHED);
+ rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_ESTABLISHED);
}
}
@@ -2020,10 +2217,9 @@ int On_TDLS_Setup_Rsp(_adapter *padapter, union recv_frame *precv_frame)
}
-int On_TDLS_Setup_Cfm(_adapter *padapter, union recv_frame *precv_frame)
+int On_TDLS_Setup_Cfm(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)
{
struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
- struct sta_info *ptdls_sta = NULL;
struct sta_priv *pstapriv = &padapter->stapriv;
u8 *ptr = precv_frame->u.hdr.rx_data;
_irqL irqL;
@@ -2038,13 +2234,6 @@ int On_TDLS_Setup_Cfm(_adapter *padapter, union recv_frame *precv_frame)
int ret = _SUCCESS;
psa = get_sa(ptr);
- ptdls_sta = rtw_get_stainfo(pstapriv, psa);
-
- if (ptdls_sta == NULL) {
- RTW_INFO("[%s] Direct Link Peer = "MAC_FMT" not found\n", __FUNCTION__, MAC_ARG(psa));
- ret = _FAIL;
- goto exit;
- }
ptr += prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN;
parsing_length = ((union recv_frame *)precv_frame)->u.hdr.len
@@ -2053,14 +2242,14 @@ int On_TDLS_Setup_Cfm(_adapter *padapter, union recv_frame *precv_frame)
- prx_pkt_attrib->icv_len
- LLC_HEADER_SIZE
- ETH_TYPE_LEN
- - PAYLOAD_TYPE_LEN
- - FIXED_IE;
+ - PAYLOAD_TYPE_LEN;
_rtw_memcpy(&status_code, ptr + 2, 2);
if (status_code != 0) {
RTW_INFO("[%s] status_code = %d\n, free_tdls_sta", __FUNCTION__, status_code);
- free_tdls_sta(padapter, ptdls_sta);
+ rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);
+ rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST);
ret = _FAIL;
goto exit;
}
@@ -2092,9 +2281,10 @@ int On_TDLS_Setup_Cfm(_adapter *padapter, union recv_frame *precv_frame)
#endif
#ifdef CONFIG_80211AC_VHT
case EID_VHTOperation:
+ rtw_tdls_process_vht_operation(padapter, ptdls_sta, pIE->data, pIE->Length);
break;
case EID_OpModeNotification:
- rtw_process_vht_op_mode_notify(padapter, pIE->data, ptdls_sta);
+ rtw_tdls_process_vht_op_mode_notify(padapter, ptdls_sta, pIE->data, pIE->Length);
break;
#endif
case _LINK_ID_IE_:
@@ -2112,14 +2302,15 @@ int On_TDLS_Setup_Cfm(_adapter *padapter, union recv_frame *precv_frame)
/* Verify mic in FTIE MIC field */
if (rtw_tdls_is_driver_setup(padapter) &&
(tdls_verify_mic(ptdls_sta->tpk.kck, 3, plinkid_ie, prsnie, ptimeout_ie, pftie) == _FAIL)) {
- free_tdls_sta(padapter, ptdls_sta);
+ rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);
+ rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST);
ret = _FAIL;
goto exit;
}
}
if (rtw_tdls_is_driver_setup(padapter)) {
- ptdlsinfo->link_established = _TRUE;
+ rtw_tdls_set_link_established(padapter, _TRUE);
if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE) {
ptdls_sta->tdls_sta_state |= TDLS_LINKED_STATE;
@@ -2135,7 +2326,7 @@ int On_TDLS_Setup_Cfm(_adapter *padapter, union recv_frame *precv_frame)
_set_timer(&ptdls_sta->TPK_timer, ONE_SEC);
}
- rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_ESTABLISHED);
+ rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_ESTABLISHED);
}
exit:
@@ -2170,8 +2361,7 @@ int On_TDLS_Dis_Req(_adapter *padapter, union recv_frame *precv_frame)
- prx_pkt_attrib->icv_len
- LLC_HEADER_SIZE
- ETH_TYPE_LEN
- - PAYLOAD_TYPE_LEN
- - FIXED_IE;
+ - PAYLOAD_TYPE_LEN;
/* Parsing information element */
for (j = FIXED_IE; j < parsing_length;) {
@@ -2202,27 +2392,22 @@ int On_TDLS_Dis_Req(_adapter *padapter, union recv_frame *precv_frame)
}
-int On_TDLS_Teardown(_adapter *padapter, union recv_frame *precv_frame)
+int On_TDLS_Teardown(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)
{
- u8 *psa;
u8 *ptr = precv_frame->u.hdr.rx_data;
struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib;
struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
struct sta_priv *pstapriv = &padapter->stapriv;
- struct sta_info *ptdls_sta = NULL;
_irqL irqL;
u8 reason;
reason = *(ptr + prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN + 2);
RTW_INFO("[TDLS] %s Reason code(%d)\n", __FUNCTION__, reason);
- psa = get_sa(ptr);
-
- ptdls_sta = rtw_get_stainfo(pstapriv, psa);
- if (ptdls_sta != NULL) {
- if (rtw_tdls_is_driver_setup(padapter))
- rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_TEARDOWN_STA_LOCALLY);
+ if (rtw_tdls_is_driver_setup(padapter)) {
+ rtw_tdls_teardown_pre_hdl(padapter, ptdls_sta);
+ rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY_POST);
}
return _SUCCESS;
@@ -2243,36 +2428,29 @@ u8 TDLS_check_ch_state(uint state)
}
#endif
-int On_TDLS_Peer_Traffic_Indication(_adapter *padapter, union recv_frame *precv_frame)
+int On_TDLS_Peer_Traffic_Indication(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)
{
struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
- struct sta_info *ptdls_sta = rtw_get_stainfo(&padapter->stapriv, pattrib->src);
u8 *ptr = precv_frame->u.hdr.rx_data;
struct tdls_txmgmt txmgmt;
ptr += pattrib->hdrlen + pattrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN;
_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
- if (ptdls_sta != NULL) {
txmgmt.dialog_token = *(ptr + 2);
issue_tdls_peer_traffic_rsp(padapter, ptdls_sta, &txmgmt);
- /* issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->hwaddr, 0, 0, 0); */
- } else {
- RTW_INFO("from unknown sta:"MAC_FMT"\n", MAC_ARG(pattrib->src));
- return _FAIL;
- }
+ /* issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->cmn.mac_addr, 0, 0, 0); */
return _SUCCESS;
}
/* We process buffered data for 1. U-APSD, 2. ch. switch, 3. U-APSD + ch. switch here */
-int On_TDLS_Peer_Traffic_Rsp(_adapter *padapter, union recv_frame *precv_frame)
+int On_TDLS_Peer_Traffic_Rsp(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)
{
struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
struct sta_priv *pstapriv = &padapter->stapriv;
- struct sta_info *ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->src);
u8 wmmps_ac = 0;
/* u8 state=TDLS_check_ch_state(ptdls_sta->tdls_sta_state); */
int i;
@@ -2334,20 +2512,17 @@ int On_TDLS_Peer_Traffic_Rsp(_adapter *padapter, union recv_frame *precv_frame)
}
#ifdef CONFIG_TDLS_CH_SW
-sint On_TDLS_Ch_Switch_Req(_adapter *padapter, union recv_frame *precv_frame)
+sint On_TDLS_Ch_Switch_Req(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)
{
struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;
- struct sta_info *ptdls_sta = NULL;
struct sta_priv *pstapriv = &padapter->stapriv;
u8 *ptr = precv_frame->u.hdr.rx_data;
struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib;
- u8 *psa;
sint parsing_length;
PNDIS_802_11_VARIABLE_IEs pIE;
u8 FIXED_IE = 4;
u16 j;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
- struct tdls_txmgmt txmgmt;
u8 zaddr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
u16 switch_time = TDLS_CH_SWITCH_TIME * 1000, switch_timeout = TDLS_CH_SWITCH_TIMEOUT * 1000;
u8 take_care_iqk;
@@ -2357,15 +2532,6 @@ sint On_TDLS_Ch_Switch_Req(_adapter *padapter, union recv_frame *precv_frame)
return _FAIL;
}
- _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
- psa = get_sa(ptr);
- ptdls_sta = rtw_get_stainfo(pstapriv, psa);
-
- if (ptdls_sta == NULL) {
- RTW_INFO("[%s] Direct Link Peer = "MAC_FMT" not found\n", __func__, MAC_ARG(psa));
- return _FAIL;
- }
-
ptdls_sta->ch_switch_time = switch_time;
ptdls_sta->ch_switch_timeout = switch_timeout;
@@ -2376,8 +2542,7 @@ sint On_TDLS_Ch_Switch_Req(_adapter *padapter, union recv_frame *precv_frame)
- prx_pkt_attrib->icv_len
- LLC_HEADER_SIZE
- ETH_TYPE_LEN
- - PAYLOAD_TYPE_LEN
- - FIXED_IE;
+ - PAYLOAD_TYPE_LEN;
pchsw_info->off_ch_num = *(ptr + 2);
@@ -2432,7 +2597,7 @@ sint On_TDLS_Ch_Switch_Req(_adapter *padapter, union recv_frame *precv_frame)
central_chnl = rtw_get_center_ch(pchsw_info->off_ch_num, bw_mode, pchsw_info->ch_offset);
if (rtw_hal_ch_sw_iqk_info_search(padapter, central_chnl, bw_mode) < 0) {
if (!(pchsw_info->ch_sw_state & TDLS_CH_SWITCH_PREPARE_STATE))
- rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_PREPARE);
+ rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_PREPARE);
return _FAIL;
}
@@ -2442,29 +2607,23 @@ sint On_TDLS_Ch_Switch_Req(_adapter *padapter, union recv_frame *precv_frame)
if (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE))
_cancel_timer_ex(&ptdls_sta->ch_sw_monitor_timer);
- /* Todo: check status */
- txmgmt.status_code = 0;
- _rtw_memcpy(txmgmt.peer, psa, ETH_ALEN);
-
if (_rtw_memcmp(pchsw_info->addr, zaddr, ETH_ALEN) == _TRUE)
- _rtw_memcpy(pchsw_info->addr, ptdls_sta->hwaddr, ETH_ALEN);
+ _rtw_memcpy(pchsw_info->addr, ptdls_sta->cmn.mac_addr, ETH_ALEN);
if (ATOMIC_READ(&pchsw_info->chsw_on) == _FALSE)
- rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_START);
+ rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_START);
- rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_RESP);
+ rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_RESP);
return _SUCCESS;
}
-sint On_TDLS_Ch_Switch_Rsp(_adapter *padapter, union recv_frame *precv_frame)
+sint On_TDLS_Ch_Switch_Rsp(_adapter *padapter, union recv_frame *precv_frame, struct sta_info *ptdls_sta)
{
struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;
- struct sta_info *ptdls_sta = NULL;
struct sta_priv *pstapriv = &padapter->stapriv;
u8 *ptr = precv_frame->u.hdr.rx_data;
struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib;
- u8 *psa;
sint parsing_length;
PNDIS_802_11_VARIABLE_IEs pIE;
u8 FIXED_IE = 4;
@@ -2477,20 +2636,12 @@ sint On_TDLS_Ch_Switch_Rsp(_adapter *padapter, union recv_frame *precv_frame)
return _SUCCESS;
}
- psa = get_sa(ptr);
- ptdls_sta = rtw_get_stainfo(pstapriv, psa);
-
- if (ptdls_sta == NULL) {
- RTW_INFO("[%s] Direct Link Peer = "MAC_FMT" not found\n", __func__, MAC_ARG(psa));
- return _FAIL;
- }
-
/* If we receive Unsolicited TDLS Channel Switch Response when channel switch is running, */
/* we will go back to base channel and terminate this channel switch procedure */
if (ATOMIC_READ(&pchsw_info->chsw_on) == _TRUE) {
if (pmlmeext->cur_channel != rtw_get_oper_ch(padapter)) {
RTW_INFO("[TDLS] Rx unsolicited channel switch response\n");
- rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_TO_BASE_CHNL);
+ rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_BASE_CHNL);
goto exit;
}
}
@@ -2502,15 +2653,14 @@ sint On_TDLS_Ch_Switch_Rsp(_adapter *padapter, union recv_frame *precv_frame)
- prx_pkt_attrib->icv_len
- LLC_HEADER_SIZE
- ETH_TYPE_LEN
- - PAYLOAD_TYPE_LEN
- - FIXED_IE;
+ - PAYLOAD_TYPE_LEN;
_rtw_memcpy(&status_code, ptr + 2, 2);
if (status_code != 0) {
RTW_INFO("[TDLS] %s status_code:%d\n", __func__, status_code);
pchsw_info->ch_sw_state &= ~(TDLS_CH_SW_INITIATOR_STATE);
- rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_END);
+ rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_END);
ret = _FAIL;
goto exit;
}
@@ -2541,7 +2691,7 @@ sint On_TDLS_Ch_Switch_Rsp(_adapter *padapter, union recv_frame *precv_frame)
if ((pmlmeext->cur_channel == rtw_get_oper_ch(padapter)) &&
(pchsw_info->ch_sw_state & TDLS_WAIT_CH_RSP_STATE)) {
if (ATOMIC_READ(&pchsw_info->chsw_on) == _TRUE)
- rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_TO_OFF_CHNL);
+ rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_TO_OFF_CHNL);
}
exit:
@@ -2556,6 +2706,7 @@ void wfd_ie_tdls(_adapter *padapter, u8 *pframe, u32 *pktlen)
struct wifi_display_info *pwfd_info = padapter->tdlsinfo.wfd_info;
u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 };
u32 wfdielen = 0;
+ u16 v16 = 0;
if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST))
return;
@@ -2587,8 +2738,9 @@ void wfd_ie_tdls(_adapter *padapter, u8 *pframe, u32 *pktlen)
/* Value1: */
/* WFD device information */
/* available for WFD session + Preferred TDLS + WSD ( WFD Service Discovery ) */
- RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL
- | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_WSD);
+ v16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL
+ | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_WSD;
+ RTW_PUT_BE16(wfdie + wfdielen, v16);
wfdielen += 2;
/* Value2: */
@@ -2640,13 +2792,12 @@ void wfd_ie_tdls(_adapter *padapter, u8 *pframe, u32 *pktlen)
}
#endif /* CONFIG_WFD */
-void rtw_build_tdls_setup_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt)
+void rtw_build_tdls_setup_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)
{
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
struct registry_priv *pregistrypriv = &padapter->registrypriv;
struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
struct pkt_attrib *pattrib = &pxmitframe->attrib;
- struct sta_info *ptdls_sta = rtw_get_stainfo((&padapter->stapriv) , pattrib->dst);
-
int i = 0 ;
u32 time;
u8 *pframe_head;
@@ -2668,7 +2819,7 @@ void rtw_build_tdls_setup_req_ies(_adapter *padapter, struct xmit_frame *pxmitfr
pframe = rtw_tdls_set_capability(padapter, pframe, pattrib);
pframe = rtw_tdls_set_supported_rate(padapter, pframe, pattrib);
- pframe = rtw_tdls_set_sup_ch(&(padapter->mlmeextpriv), pframe, pattrib);
+ pframe = rtw_tdls_set_sup_ch(padapter, pframe, pattrib);
pframe = rtw_tdls_set_sup_reg_class(pframe, pattrib);
if (pattrib->encrypt)
@@ -2694,7 +2845,7 @@ void rtw_build_tdls_setup_req_ies(_adapter *padapter, struct xmit_frame *pxmitfr
pframe = rtw_tdls_set_bss_coexist(padapter, pframe, pattrib);
- pframe = rtw_tdls_set_linkid(pframe, pattrib, _TRUE);
+ pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);
if ((pregistrypriv->wmm_enable == _TRUE) || (padapter->mlmepriv.htpriv.ht_option == _TRUE))
pframe = rtw_tdls_set_qos_cap(pframe, pattrib);
@@ -2703,7 +2854,7 @@ void rtw_build_tdls_setup_req_ies(_adapter *padapter, struct xmit_frame *pxmitfr
if ((padapter->mlmepriv.htpriv.ht_option == _TRUE) && (pmlmeext->cur_channel > 14)
&& REGSTY_IS_11AC_ENABLE(pregistrypriv)
&& hal_chk_proto_cap(padapter, PROTO_CAP_11AC)
- && (!padapter->mlmepriv.country_ent || COUNTRY_CHPLAN_EN_11AC(padapter->mlmepriv.country_ent))
+ && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent))
) {
pframe = rtw_tdls_set_aid(padapter, pframe, pattrib);
pframe = rtw_tdls_set_vht_cap(padapter, pframe, pattrib);
@@ -2717,23 +2868,18 @@ void rtw_build_tdls_setup_req_ies(_adapter *padapter, struct xmit_frame *pxmitfr
}
-void rtw_build_tdls_setup_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt)
+void rtw_build_tdls_setup_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)
{
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
struct registry_priv *pregistrypriv = &padapter->registrypriv;
struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
struct pkt_attrib *pattrib = &pxmitframe->attrib;
- struct sta_info *ptdls_sta;
u8 k; /* for random ANonce */
u8 *pftie = NULL, *ptimeout_ie = NULL, *plinkid_ie = NULL, *prsnie = NULL, *pftie_mic = NULL;
u32 time;
u8 *pframe_head;
- ptdls_sta = rtw_get_stainfo(&(padapter->stapriv) , pattrib->dst);
-
- if (ptdls_sta == NULL)
- RTW_INFO("[%s] %d ptdls_sta is NULL\n", __FUNCTION__, __LINE__);
-
- if (pattrib->encrypt && ptdls_sta != NULL) {
+ if (pattrib->encrypt) {
for (k = 0; k < 8; k++) {
time = rtw_get_current_time();
_rtw_memcpy(&ptdls_sta->ANonce[4 * k], (u8 *)&time, 4);
@@ -2755,7 +2901,7 @@ void rtw_build_tdls_setup_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitfr
pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt);
pframe = rtw_tdls_set_capability(padapter, pframe, pattrib);
pframe = rtw_tdls_set_supported_rate(padapter, pframe, pattrib);
- pframe = rtw_tdls_set_sup_ch(&(padapter->mlmeextpriv), pframe, pattrib);
+ pframe = rtw_tdls_set_sup_ch(padapter, pframe, pattrib);
pframe = rtw_tdls_set_sup_reg_class(pframe, pattrib);
if (pattrib->encrypt) {
@@ -2790,7 +2936,7 @@ void rtw_build_tdls_setup_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitfr
pframe = rtw_tdls_set_bss_coexist(padapter, pframe, pattrib);
plinkid_ie = pframe;
- pframe = rtw_tdls_set_linkid(pframe, pattrib, _FALSE);
+ pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE);
/* Fill FTIE mic */
if (pattrib->encrypt && rtw_tdls_is_driver_setup(padapter) == _TRUE)
@@ -2803,7 +2949,7 @@ void rtw_build_tdls_setup_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitfr
if ((padapter->mlmepriv.htpriv.ht_option == _TRUE) && (pmlmeext->cur_channel > 14)
&& REGSTY_IS_11AC_ENABLE(pregistrypriv)
&& hal_chk_proto_cap(padapter, PROTO_CAP_11AC)
- && (!padapter->mlmepriv.country_ent || COUNTRY_CHPLAN_EN_11AC(padapter->mlmepriv.country_ent))
+ && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent))
) {
pframe = rtw_tdls_set_aid(padapter, pframe, pattrib);
pframe = rtw_tdls_set_vht_cap(padapter, pframe, pattrib);
@@ -2818,13 +2964,13 @@ void rtw_build_tdls_setup_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitfr
}
-void rtw_build_tdls_setup_cfm_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt)
+void rtw_build_tdls_setup_cfm_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)
{
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
struct registry_priv *pregistrypriv = &padapter->registrypriv;
struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
struct pkt_attrib *pattrib = &pxmitframe->attrib;
- struct sta_info *ptdls_sta = rtw_get_stainfo((&padapter->stapriv) , pattrib->dst);
unsigned int ie_len;
unsigned char *p;
@@ -2867,7 +3013,7 @@ void rtw_build_tdls_setup_cfm_ies(_adapter *padapter, struct xmit_frame *pxmitfr
/* HT operation; todo */
plinkid_ie = pframe;
- pframe = rtw_tdls_set_linkid(pframe, pattrib, _TRUE);
+ pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);
if (pattrib->encrypt && (rtw_tdls_is_driver_setup(padapter) == _TRUE))
wpa_tdls_ftie_mic(ptdls_sta->tpk.kck, 3, plinkid_ie, prsnie, ptimeout_ie, pftie, pftie_mic);
@@ -2880,7 +3026,7 @@ void rtw_build_tdls_setup_cfm_ies(_adapter *padapter, struct xmit_frame *pxmitfr
&& (ptdls_sta->vhtpriv.vht_option == _TRUE) && (pmlmeext->cur_channel > 14)
&& REGSTY_IS_11AC_ENABLE(pregistrypriv)
&& hal_chk_proto_cap(padapter, PROTO_CAP_11AC)
- && (!padapter->mlmepriv.country_ent || COUNTRY_CHPLAN_EN_11AC(padapter->mlmepriv.country_ent))
+ && (!rfctl->country_ent || COUNTRY_CHPLAN_EN_11AC(rfctl->country_ent))
) {
pframe = rtw_tdls_set_vht_operation(padapter, pframe, pattrib, pmlmeext->cur_channel);
pframe = rtw_tdls_set_vht_op_mode_notify(padapter, pframe, pattrib, pmlmeext->cur_bwmode);
@@ -2888,10 +3034,9 @@ void rtw_build_tdls_setup_cfm_ies(_adapter *padapter, struct xmit_frame *pxmitfr
#endif
}
-void rtw_build_tdls_teardown_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt)
+void rtw_build_tdls_teardown_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)
{
struct pkt_attrib *pattrib = &pxmitframe->attrib;
- struct sta_info *ptdls_sta = rtw_get_stainfo(&(padapter->stapriv) , pattrib->dst);
u8 *pftie = NULL, *pftie_mic = NULL, *plinkid_ie = NULL;
pframe = rtw_tdls_set_payload_type(pframe, pattrib);
@@ -2911,9 +3056,9 @@ void rtw_build_tdls_teardown_ies(_adapter *padapter, struct xmit_frame *pxmitfra
plinkid_ie = pframe;
if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE)
- pframe = rtw_tdls_set_linkid(pframe, pattrib, _FALSE);
+ pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE);
else if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE)
- pframe = rtw_tdls_set_linkid(pframe, pattrib, _TRUE);
+ pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);
if (pattrib->encrypt && (rtw_tdls_is_driver_setup(padapter) == _TRUE))
wpa_tdls_teardown_ftie_mic(ptdls_sta->tpk.kck, plinkid_ie, ptxmgmt->status_code, 1, 4, pftie, pftie_mic);
@@ -2927,7 +3072,7 @@ void rtw_build_tdls_dis_req_ies(_adapter *padapter, struct xmit_frame *pxmitfram
pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);
pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt);
pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt);
- pframe = rtw_tdls_set_linkid(pframe, pattrib, _TRUE);
+ pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);
}
@@ -2948,7 +3093,7 @@ void rtw_build_tdls_dis_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitfram
pframe = rtw_tdls_set_supported_rate(padapter, pframe, pattrib);
- pframe = rtw_tdls_set_sup_ch(pmlmeext, pframe, pattrib);
+ pframe = rtw_tdls_set_sup_ch(padapter, pframe, pattrib);
if (privacy)
pframe = rtw_tdls_set_rsnie(ptxmgmt, pframe, pattrib, _TRUE, NULL);
@@ -2966,17 +3111,16 @@ void rtw_build_tdls_dis_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitfram
#endif
pframe = rtw_tdls_set_bss_coexist(padapter, pframe, pattrib);
- pframe = rtw_tdls_set_linkid(pframe, pattrib, _FALSE);
+ pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE);
}
-void rtw_build_tdls_peer_traffic_indication_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt)
+void rtw_build_tdls_peer_traffic_indication_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)
{
struct pkt_attrib *pattrib = &pxmitframe->attrib;
u8 AC_queue = 0;
- struct sta_info *ptdls_sta = rtw_get_stainfo(&padapter->stapriv, pattrib->dst);
pframe = rtw_tdls_set_payload_type(pframe, pattrib);
pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);
@@ -2984,9 +3128,9 @@ void rtw_build_tdls_peer_traffic_indication_ies(_adapter *padapter, struct xmit_
pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt);
if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE)
- pframe = rtw_tdls_set_linkid(pframe, pattrib, _FALSE);
+ pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE);
else if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE)
- pframe = rtw_tdls_set_linkid(pframe, pattrib, _TRUE);
+ pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);
/* PTI control */
/* PU buffer status */
@@ -3002,11 +3146,10 @@ void rtw_build_tdls_peer_traffic_indication_ies(_adapter *padapter, struct xmit_
}
-void rtw_build_tdls_peer_traffic_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt)
+void rtw_build_tdls_peer_traffic_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)
{
struct pkt_attrib *pattrib = &pxmitframe->attrib;
- struct sta_info *ptdls_sta = rtw_get_stainfo(&padapter->stapriv, pattrib->dst);
pframe = rtw_tdls_set_payload_type(pframe, pattrib);
pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);
@@ -3014,18 +3157,17 @@ void rtw_build_tdls_peer_traffic_rsp_ies(_adapter *padapter, struct xmit_frame *
pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt);
if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE)
- pframe = rtw_tdls_set_linkid(pframe, pattrib, _FALSE);
+ pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE);
else if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE)
- pframe = rtw_tdls_set_linkid(pframe, pattrib, _TRUE);
+ pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);
}
#ifdef CONFIG_TDLS_CH_SW
-void rtw_build_tdls_ch_switch_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt)
+void rtw_build_tdls_ch_switch_req_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)
{
struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
struct pkt_attrib *pattrib = &pxmitframe->attrib;
struct sta_priv *pstapriv = &padapter->stapriv;
- struct sta_info *ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->dst);
u16 switch_time = TDLS_CH_SWITCH_TIME * 1000, switch_timeout = TDLS_CH_SWITCH_TIMEOUT * 1000;
ptdls_sta->ch_switch_time = switch_time;
@@ -3049,20 +3191,19 @@ void rtw_build_tdls_ch_switch_req_ies(_adapter *padapter, struct xmit_frame *pxm
}
if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE)
- pframe = rtw_tdls_set_linkid(pframe, pattrib, _FALSE);
+ pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE);
else if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE)
- pframe = rtw_tdls_set_linkid(pframe, pattrib, _TRUE);
+ pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);
pframe = rtw_tdls_set_ch_sw(pframe, pattrib, ptdls_sta);
}
-void rtw_build_tdls_ch_switch_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt)
+void rtw_build_tdls_ch_switch_rsp_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, struct sta_info *ptdls_sta)
{
struct pkt_attrib *pattrib = &pxmitframe->attrib;
struct sta_priv *pstapriv = &padapter->stapriv;
- struct sta_info *ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->dst);
pframe = rtw_tdls_set_payload_type(pframe, pattrib);
pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS);
@@ -3070,9 +3211,9 @@ void rtw_build_tdls_ch_switch_rsp_ies(_adapter *padapter, struct xmit_frame *pxm
pframe = rtw_tdls_set_status_code(pframe, pattrib, ptxmgmt);
if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE)
- pframe = rtw_tdls_set_linkid(pframe, pattrib, _FALSE);
+ pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _FALSE);
else if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE)
- pframe = rtw_tdls_set_linkid(pframe, pattrib, _TRUE);
+ pframe = rtw_tdls_set_linkid(padapter, pframe, pattrib, _TRUE);
pframe = rtw_tdls_set_ch_sw(pframe, pattrib, ptdls_sta);
}
@@ -3151,9 +3292,10 @@ void _tdls_tpk_timer_hdl(void *FunctionContext)
/* TPK_timer expired in a second */
/* Retry timer should set at least 301 sec. */
if (ptdls_sta->TPK_count >= (ptdls_sta->TDLS_PeerKey_Lifetime - 3)) {
- RTW_INFO("[TDLS] %s, Re-Setup TDLS link with "MAC_FMT" since TPK lifetime expires!\n", __FUNCTION__, MAC_ARG(ptdls_sta->hwaddr));
+ RTW_INFO("[TDLS] %s, Re-Setup TDLS link with "MAC_FMT" since TPK lifetime expires!\n",
+ __FUNCTION__, MAC_ARG(ptdls_sta->cmn.mac_addr));
ptdls_sta->TPK_count = 0;
- _rtw_memcpy(txmgmt.peer, ptdls_sta->hwaddr, ETH_ALEN);
+ _rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN);
issue_tdls_setup_req(ptdls_sta->padapter, &txmgmt, _FALSE);
}
@@ -3167,7 +3309,7 @@ void _tdls_ch_switch_timer_hdl(void *FunctionContext)
_adapter *padapter = ptdls_sta->padapter;
struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;
- rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_END_TO_BASE_CHNL);
+ rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_END_TO_BASE_CHNL);
RTW_INFO("[TDLS] %s, can't get traffic from op_ch:%d\n", __func__, rtw_get_oper_ch(padapter));
}
@@ -3199,7 +3341,7 @@ void _tdls_ch_switch_monitor_timer_hdl(void *FunctionContext)
_adapter *padapter = ptdls_sta->padapter;
struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info;
- rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_END);
+ rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_CH_SW_END);
RTW_INFO("[TDLS] %s, does not receive ch sw req\n", __func__);
}
@@ -3208,37 +3350,41 @@ void _tdls_ch_switch_monitor_timer_hdl(void *FunctionContext)
void _tdls_handshake_timer_hdl(void *FunctionContext)
{
struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext;
- _adapter *padapter = ptdls_sta->padapter;
+ _adapter *padapter = NULL;
struct tdls_txmgmt txmgmt;
_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
- _rtw_memcpy(txmgmt.peer, ptdls_sta->hwaddr, ETH_ALEN);
+ _rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN);
txmgmt.status_code = _RSON_TDLS_TEAR_UN_RSN_;
if (ptdls_sta != NULL) {
+ padapter = ptdls_sta->padapter;
+
RTW_INFO("[TDLS] Handshake time out\n");
if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)
- rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_TEARDOWN_STA);
+ rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA);
else
- rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_TEARDOWN_STA_LOCALLY);
+ rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA_LOCALLY);
}
}
void _tdls_pti_timer_hdl(void *FunctionContext)
{
struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext;
- _adapter *padapter = ptdls_sta->padapter;
+ _adapter *padapter = NULL;
struct tdls_txmgmt txmgmt;
_rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt));
- _rtw_memcpy(txmgmt.peer, ptdls_sta->hwaddr, ETH_ALEN);
+ _rtw_memcpy(txmgmt.peer, ptdls_sta->cmn.mac_addr, ETH_ALEN);
txmgmt.status_code = _RSON_TDLS_TEAR_TOOFAR_;
if (ptdls_sta != NULL) {
+ padapter = ptdls_sta->padapter;
+
if (ptdls_sta->tdls_sta_state & TDLS_WAIT_PTR_STATE) {
RTW_INFO("[TDLS] Doesn't receive PTR from peer dev:"MAC_FMT"; "
- "Send TDLS Tear Down\n", MAC_ARG(ptdls_sta->hwaddr));
- issue_tdls_teardown(padapter, &txmgmt, _FALSE);
+ "Send TDLS Tear Down\n", MAC_ARG(ptdls_sta->cmn.mac_addr));
+ rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_TEARDOWN_STA);
}
}
}
@@ -3246,18 +3392,18 @@ void _tdls_pti_timer_hdl(void *FunctionContext)
void rtw_init_tdls_timer(_adapter *padapter, struct sta_info *psta)
{
psta->padapter = padapter;
- _init_timer(&psta->TPK_timer, padapter->pnetdev, _tdls_tpk_timer_hdl, psta);
+ rtw_init_timer(&psta->TPK_timer, padapter, _tdls_tpk_timer_hdl, psta);
#ifdef CONFIG_TDLS_CH_SW
- _init_timer(&psta->ch_sw_timer, padapter->pnetdev, _tdls_ch_switch_timer_hdl, psta);
- _init_timer(&psta->delay_timer, padapter->pnetdev, _tdls_delay_timer_hdl, psta);
- _init_timer(&psta->stay_on_base_chnl_timer, padapter->pnetdev, _tdls_stay_on_base_chnl_timer_hdl, psta);
- _init_timer(&psta->ch_sw_monitor_timer, padapter->pnetdev, _tdls_ch_switch_monitor_timer_hdl, psta);
+ rtw_init_timer(&psta->ch_sw_timer, padapter, _tdls_ch_switch_timer_hdl, psta);
+ rtw_init_timer(&psta->delay_timer, padapter, _tdls_delay_timer_hdl, psta);
+ rtw_init_timer(&psta->stay_on_base_chnl_timer, padapter, _tdls_stay_on_base_chnl_timer_hdl, psta);
+ rtw_init_timer(&psta->ch_sw_monitor_timer, padapter, _tdls_ch_switch_monitor_timer_hdl, psta);
#endif
- _init_timer(&psta->handshake_timer, padapter->pnetdev, _tdls_handshake_timer_hdl, psta);
- _init_timer(&psta->pti_timer, padapter->pnetdev, _tdls_pti_timer_hdl, psta);
+ rtw_init_timer(&psta->handshake_timer, padapter, _tdls_handshake_timer_hdl, psta);
+ rtw_init_timer(&psta->pti_timer, padapter, _tdls_pti_timer_hdl, psta);
}
-void rtw_free_tdls_timer(struct sta_info *psta)
+void rtw_cancel_tdls_timer(struct sta_info *psta)
{
_cancel_timer_ex(&psta->TPK_timer);
#ifdef CONFIG_TDLS_CH_SW
@@ -3270,40 +3416,53 @@ void rtw_free_tdls_timer(struct sta_info *psta)
_cancel_timer_ex(&psta->pti_timer);
}
-u8 update_sgi_tdls(_adapter *padapter, struct sta_info *psta)
+void rtw_tdls_teardown_pre_hdl(_adapter *padapter, struct sta_info *psta)
{
- return query_ra_short_GI(psta);
+ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
+ struct sta_priv *pstapriv = &padapter->stapriv;
+ _irqL irqL;
+
+ rtw_cancel_tdls_timer(psta);
+
+ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
+ if (ptdlsinfo->sta_cnt != 0)
+ ptdlsinfo->sta_cnt--;
+ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);
+
+ if (ptdlsinfo->sta_cnt < MAX_ALLOWED_TDLS_STA_NUM) {
+ ptdlsinfo->sta_maximum = _FALSE;
+ _rtw_memset(&ptdlsinfo->ss_record, 0x00, sizeof(struct tdls_ss_record));
+ }
+
+ if (ptdlsinfo->sta_cnt == 0)
+ rtw_tdls_set_link_established(padapter, _FALSE);
+ else
+ RTW_INFO("Remain tdls sta:%02x\n", ptdlsinfo->sta_cnt);
}
-u32 update_mask_tdls(_adapter *padapter, struct sta_info *psta)
+void rtw_tdls_teardown_post_hdl(_adapter *padapter, struct sta_info *psta, u8 enqueue_cmd)
{
- unsigned char sta_band = 0;
- unsigned int tx_ra_bitmap = 0;
- struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
- WLAN_BSSID_EX *pcur_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network;
+ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
- rtw_hal_update_sta_rate_mask(padapter, psta);
- tx_ra_bitmap = psta->ra_mask;
+ /* Clear cam */
+ rtw_clearstakey_cmd(padapter, psta, enqueue_cmd);
- if (pcur_network->Configuration.DSConfig > 14) {
- if (tx_ra_bitmap & 0xffff000)
- sta_band |= WIRELESS_11_5N | WIRELESS_11A;
- else
- sta_band |= WIRELESS_11A;
- } else {
- if (tx_ra_bitmap & 0xffff000)
- sta_band |= WIRELESS_11_24N | WIRELESS_11G | WIRELESS_11B;
- else if (tx_ra_bitmap & 0xff0)
- sta_band |= WIRELESS_11G | WIRELESS_11B;
+ /* Update sta media status */
+ if (enqueue_cmd)
+ rtw_sta_media_status_rpt_cmd(padapter, psta, 0);
+ else
+ rtw_sta_media_status_rpt(padapter, psta, 0);
+
+ /* Set RCR if necessary */
+ if (ptdlsinfo->sta_cnt == 0) {
+ if (enqueue_cmd)
+ rtw_tdls_cmd(padapter, NULL, TDLS_RS_RCR);
else
- sta_band |= WIRELESS_11B;
+ rtw_hal_rcr_set_chk_bssid(padapter, MLME_TDLS_NOLINK);
}
- psta->wireless_mode = sta_band;
-
- psta->raid = rtw_hal_networktype_to_raid(padapter, psta);
- tx_ra_bitmap |= ((psta->raid << 28) & 0xf0000000);
- return tx_ra_bitmap;
+ /* Free tdls sta info */
+ rtw_free_stainfo(padapter, psta);
}
int rtw_tdls_is_driver_setup(_adapter *padapter)
diff --git a/core/rtw_vht.c b/core/rtw_vht.c
index 496a300..dd2e7e5 100644
--- a/core/rtw_vht.c
+++ b/core/rtw_vht.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,17 +11,108 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#define _RTW_VHT_C
#include
+#include
#ifdef CONFIG_80211AC_VHT
+const u16 _vht_max_mpdu_len[] = {
+ 3895,
+ 7991,
+ 11454,
+ 0,
+};
+
+const u8 _vht_sup_ch_width_set_to_bw_cap[] = {
+ BW_CAP_80M,
+ BW_CAP_80M | BW_CAP_160M,
+ BW_CAP_80M | BW_CAP_160M | BW_CAP_80_80M,
+ 0,
+};
+
+const char *const _vht_sup_ch_width_set_str[] = {
+ "80MHz",
+ "160MHz",
+ "160MHz & 80+80MHz",
+ "BW-RSVD",
+};
+
+void dump_vht_cap_ie_content(void *sel, const u8 *buf, u32 buf_len)
+{
+ if (buf_len != VHT_CAP_IE_LEN) {
+ RTW_PRINT_SEL(sel, "Invalid VHT capability IE len:%d != %d\n", buf_len, VHT_CAP_IE_LEN);
+ return;
+ }
+
+ RTW_PRINT_SEL(sel, "cap_info:%02x %02x %02x %02x: MAX_MPDU_LEN:%u %s%s%s%s%s RX-STBC:%u MAX_AMPDU_LEN:%u\n"
+ , *(buf), *(buf + 1), *(buf + 2), *(buf + 3)
+ , vht_max_mpdu_len(GET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(buf))
+ , vht_sup_ch_width_set_str(GET_VHT_CAPABILITY_ELE_CHL_WIDTH(buf))
+ , GET_VHT_CAPABILITY_ELE_RX_LDPC(buf) ? " RX-LDPC" : ""
+ , GET_VHT_CAPABILITY_ELE_SHORT_GI80M(buf) ? " SGI-80" : ""
+ , GET_VHT_CAPABILITY_ELE_SHORT_GI160M(buf) ? " SGI-160" : ""
+ , GET_VHT_CAPABILITY_ELE_TX_STBC(buf) ? " TX-STBC" : ""
+ , GET_VHT_CAPABILITY_ELE_RX_STBC(buf)
+ , VHT_MAX_AMPDU_LEN(GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(buf))
+ );
+}
+
+void dump_vht_cap_ie(void *sel, const u8 *ie, u32 ie_len)
+{
+ const u8 *pos = ie;
+ u16 id;
+ u16 len;
+
+ const u8 *vht_cap_ie;
+ sint vht_cap_ielen;
+
+ vht_cap_ie = rtw_get_ie(ie, WLAN_EID_VHT_CAPABILITY, &vht_cap_ielen, ie_len);
+ if (!ie || vht_cap_ie != ie)
+ return;
+
+ dump_vht_cap_ie_content(sel, vht_cap_ie + 2, vht_cap_ielen);
+}
+
+const char *const _vht_op_ch_width_str[] = {
+ "20 or 40MHz",
+ "80MHz",
+ "160MHz",
+ "80+80MHz",
+ "BW-RSVD",
+};
+
+void dump_vht_op_ie_content(void *sel, const u8 *buf, u32 buf_len)
+{
+ if (buf_len != VHT_OP_IE_LEN) {
+ RTW_PRINT_SEL(sel, "Invalid VHT operation IE len:%d != %d\n", buf_len, VHT_OP_IE_LEN);
+ return;
+ }
+
+ RTW_PRINT_SEL(sel, "%s, ch0:%u, ch1:%u\n"
+ , vht_op_ch_width_str(GET_VHT_OPERATION_ELE_CHL_WIDTH(buf))
+ , GET_VHT_OPERATION_ELE_CENTER_FREQ1(buf)
+ , GET_VHT_OPERATION_ELE_CENTER_FREQ2(buf)
+ );
+}
+
+void dump_vht_op_ie(void *sel, const u8 *ie, u32 ie_len)
+{
+ const u8 *pos = ie;
+ u16 id;
+ u16 len;
+
+ const u8 *vht_op_ie;
+ sint vht_op_ielen;
+
+ vht_op_ie = rtw_get_ie(ie, WLAN_EID_VHT_OPERATION, &vht_op_ielen, ie_len);
+ if (!ie || vht_op_ie != ie)
+ return;
+
+ dump_vht_op_ie_content(sel, vht_op_ie + 2, vht_op_ielen);
+}
+
/* 20/40/80, ShortGI, MCS Rate */
const u16 VHT_MCS_DATA_RATE[3][2][30] = {
{ {
@@ -101,7 +192,7 @@ u8 rtw_vht_mcsmap_to_nss(u8 *pvht_mcs_map)
return nss;
}
-void rtw_vht_nss_to_mcsmap(u8 nss, u8 *target_mcs_map, u8 *cur_mcs_map)
+void rtw_vht_nss_to_mcsmap(u8 nss, u8 *target_mcs_map, u8 *cur_mcs_map)
{
u8 i, j;
u8 cur_rate, target_rate;
@@ -143,6 +234,8 @@ void rtw_vht_use_default_setting(_adapter *padapter)
u8 mu_bfer, mu_bfee;
#endif /* CONFIG_BEAMFORMING */
u8 rf_type = 0;
+ u8 tx_nss, rx_nss;
+ struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
pvhtpriv->sgi_80m = TEST_FLAG(pregistrypriv->short_gi, BIT2) ? _TRUE : _FALSE;
@@ -180,43 +273,53 @@ void rtw_vht_use_default_setting(_adapter *padapter)
/* Beamforming setting */
CLEAR_FLAGS(pvhtpriv->beamform_cap);
#ifdef CONFIG_BEAMFORMING
- rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMER, (u8 *)&bHwSupportBeamformer);
- rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMEE, (u8 *)&bHwSupportBeamformee);
- mu_bfer = _FALSE;
- mu_bfee = _FALSE;
- rtw_hal_get_def_var(padapter, HAL_DEF_VHT_MU_BEAMFORMER, &mu_bfer);
- rtw_hal_get_def_var(padapter, HAL_DEF_VHT_MU_BEAMFORMEE, &mu_bfee);
- if (TEST_FLAG(pregistrypriv->beamform_cap, BIT0) && bHwSupportBeamformer) {
+#ifdef RTW_BEAMFORMING_VERSION_2
+ /* only enable beamforming in STA client mode */
+ if (MLME_IS_STA(padapter) && !MLME_IS_GC(padapter)
+ && !MLME_IS_ADHOC(padapter)
+ && !MLME_IS_MESH(padapter))
+#endif
+ {
+ rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMER,
+ (u8 *)&bHwSupportBeamformer);
+ rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMEE,
+ (u8 *)&bHwSupportBeamformee);
+ mu_bfer = _FALSE;
+ mu_bfee = _FALSE;
+ rtw_hal_get_def_var(padapter, HAL_DEF_VHT_MU_BEAMFORMER, &mu_bfer);
+ rtw_hal_get_def_var(padapter, HAL_DEF_VHT_MU_BEAMFORMEE, &mu_bfee);
+ if (TEST_FLAG(pregistrypriv->beamform_cap, BIT0) && bHwSupportBeamformer) {
#ifdef CONFIG_CONCURRENT_MODE
- if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {
+ if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) {
+ SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
+ RTW_INFO("[VHT] CONCURRENT AP Support Beamformer\n");
+ if (TEST_FLAG(pregistrypriv->beamform_cap, BIT(2))
+ && (_TRUE == mu_bfer)) {
+ SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE);
+ RTW_INFO("[VHT] Support MU-MIMO AP\n");
+ }
+ } else
+ RTW_INFO("[VHT] CONCURRENT not AP ;not allow Support Beamformer\n");
+#else
SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
- RTW_INFO("[VHT] CONCURRENT AP Support Beamformer\n");
+ RTW_INFO("[VHT] Support Beamformer\n");
if (TEST_FLAG(pregistrypriv->beamform_cap, BIT(2))
- && (_TRUE == mu_bfer)) {
+ && (_TRUE == mu_bfer)
+ && ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) {
SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE);
RTW_INFO("[VHT] Support MU-MIMO AP\n");
}
- } else
- RTW_INFO("[VHT] CONCURRENT not AP ;not allow Support Beamformer\n");
-#else
- SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
- RTW_INFO("[VHT] Support Beamformer\n");
- if (TEST_FLAG(pregistrypriv->beamform_cap, BIT(2))
- && (_TRUE == mu_bfer)
- && ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) {
- SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE);
- RTW_INFO("[VHT] Support MU-MIMO AP\n");
- }
#endif
- }
- if (TEST_FLAG(pregistrypriv->beamform_cap, BIT1) && bHwSupportBeamformee) {
- SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
- RTW_INFO("[VHT] Support Beamformee\n");
- if (TEST_FLAG(pregistrypriv->beamform_cap, BIT(3))
- && (_TRUE == mu_bfee)
- && ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)) {
- SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE);
- RTW_INFO("[VHT] Support MU-MIMO STA\n");
+ }
+ if (TEST_FLAG(pregistrypriv->beamform_cap, BIT1) && bHwSupportBeamformee) {
+ SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
+ RTW_INFO("[VHT] Support Beamformee\n");
+ if (TEST_FLAG(pregistrypriv->beamform_cap, BIT(3))
+ && (_TRUE == mu_bfee)
+ && ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE)) {
+ SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE);
+ RTW_INFO("[VHT] Support MU-MIMO STA\n");
+ }
}
}
#endif /* CONFIG_BEAMFORMING */
@@ -224,69 +327,77 @@ void rtw_vht_use_default_setting(_adapter *padapter)
pvhtpriv->ampdu_len = pregistrypriv->ampdu_factor;
rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
+ tx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num);
+ rx_nss = rtw_min(rf_type_to_rf_rx_cnt(rf_type), hal_spec->rx_nss_num);
- if (rf_type == RF_3T3R)
- pvhtpriv->vht_mcs_map[0] = 0xea; /* support 1SS MCS 0~9 2SS MCS 0~9 3SS MCS 0~9 */
- else if (rf_type == RF_2T2R)
- pvhtpriv->vht_mcs_map[0] = 0xfa; /* support 1SS MCS 0~9 2SS MCS 0~9 */
- else
- pvhtpriv->vht_mcs_map[0] = 0xfe; /* Only support 1SS MCS 0~9; */
- pvhtpriv->vht_mcs_map[1] = 0xff;
-
- if (pregistrypriv->vht_rate_sel == 1) {
- pvhtpriv->vht_mcs_map[0] = 0xfc; /* support 1SS MCS 0~7 */
- } else if (pregistrypriv->vht_rate_sel == 2) {
- pvhtpriv->vht_mcs_map[0] = 0xfd; /* Support 1SS MCS 0~8 */
- } else if (pregistrypriv->vht_rate_sel == 3) {
- pvhtpriv->vht_mcs_map[0] = 0xfe; /* Support 1SS MCS 0~9 */
- } else if (pregistrypriv->vht_rate_sel == 4) {
- pvhtpriv->vht_mcs_map[0] = 0xf0; /* support 1SS MCS 0~7 2SS MCS 0~7 */
- } else if (pregistrypriv->vht_rate_sel == 5) {
- pvhtpriv->vht_mcs_map[0] = 0xf5; /* support 1SS MCS 0~8 2SS MCS 0~8 */
- } else if (pregistrypriv->vht_rate_sel == 6) {
- pvhtpriv->vht_mcs_map[0] = 0xfa; /* support 1SS MCS 0~9 2SS MCS 0~9 */
- } else if (pregistrypriv->vht_rate_sel == 7) {
- pvhtpriv->vht_mcs_map[0] = 0xf8; /* support 1SS MCS 0-7 2SS MCS 0~9 */
- } else if (pregistrypriv->vht_rate_sel == 8) {
- pvhtpriv->vht_mcs_map[0] = 0xf9; /* support 1SS MCS 0-8 2SS MCS 0~9 */
- } else if (pregistrypriv->vht_rate_sel == 9) {
- pvhtpriv->vht_mcs_map[0] = 0xf4; /* support 1SS MCS 0-7 2SS MCS 0~8 */
- }
-
+ /* for now, vhtpriv.vht_mcs_map comes from RX NSS */
+ rtw_vht_nss_to_mcsmap(rx_nss, pvhtpriv->vht_mcs_map, pregistrypriv->vht_rx_mcs_map);
pvhtpriv->vht_highest_rate = rtw_get_vht_highest_rate(pvhtpriv->vht_mcs_map);
}
-u64 rtw_vht_rate_to_bitmap(u8 *pVHTRate)
+u64 rtw_vht_mcs_map_to_bitmap(u8 *mcs_map, u8 nss)
{
+ u8 i, j, tmp;
+ u64 bitmap = 0;
+ u8 bits_nss = nss * 2;
- u8 i, j , tmpRate;
- u64 RateBitmap = 0;
- u8 Bits_3ss = 6;
-
- for (i = j = 0; i < Bits_3ss; i += 2, j += 10) {
+ for (i = j = 0; i < bits_nss; i += 2, j += 10) {
/* every two bits means single sptial stream */
- tmpRate = (pVHTRate[0] >> i) & 3;
+ tmp = (mcs_map[i / 8] >> i) & 3;
- switch (tmpRate) {
+ switch (tmp) {
case 2:
- RateBitmap = RateBitmap | (0x03ff << j);
+ bitmap = bitmap | (0x03ff << j);
break;
case 1:
- RateBitmap = RateBitmap | (0x01ff << j);
+ bitmap = bitmap | (0x01ff << j);
break;
-
case 0:
- RateBitmap = RateBitmap | (0x00ff << j);
+ bitmap = bitmap | (0x00ff << j);
break;
-
default:
break;
}
}
- RTW_INFO("RateBitmap=%016llx , pVHTRate[0]=%02x, pVHTRate[1]=%02x\n", RateBitmap, pVHTRate[0], pVHTRate[1]);
- return RateBitmap;
+
+ RTW_INFO("vht_mcs_map=%02x %02x, nss=%u => bitmap=%016llx\n"
+ , mcs_map[0], mcs_map[1], nss, bitmap);
+
+ return bitmap;
}
+#ifdef CONFIG_BEAMFORMING
+void update_sta_vht_info_apmode_bf_cap(_adapter *padapter, struct sta_info *psta)
+{
+ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+ struct vht_priv *pvhtpriv_ap = &pmlmepriv->vhtpriv;
+ struct vht_priv *pvhtpriv_sta = &psta->vhtpriv;
+ u16 cur_beamform_cap = 0;
+
+ /* B11 SU Beamformer Capable, the target supports Beamformer and we are Beamformee */
+ if (TEST_FLAG(pvhtpriv_ap->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE) &&
+ GET_VHT_CAPABILITY_ELE_SU_BFEE(pvhtpriv_sta->vht_cap)) {
+ SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
+ /*Shift to BEAMFORMING_VHT_BEAMFORMER_STS_CAP*/
+ SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(pvhtpriv_sta->vht_cap) << 8);
+ }
+
+ /* B12 SU Beamformee Capable, the target supports Beamformee and we are Beamformer */
+ if (TEST_FLAG(pvhtpriv_ap->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) &&
+ GET_VHT_CAPABILITY_ELE_SU_BFER(pvhtpriv_sta->vht_cap)) {
+ SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
+ /*Shit to BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM*/
+ SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(pvhtpriv_sta->vht_cap) << 12);
+ }
+
+ if (cur_beamform_cap)
+ RTW_INFO("Current STA(%d) VHT Beamforming Setting = %02X\n", psta->cmn.aid, cur_beamform_cap);
+
+ pvhtpriv_sta->beamform_cap = cur_beamform_cap;
+ psta->cmn.bf_info.vht_beamform_cap = cur_beamform_cap;
+}
+#endif
+
void update_sta_vht_info_apmode(_adapter *padapter, PVOID sta)
{
struct sta_info *psta = (struct sta_info *)sta;
@@ -294,35 +405,52 @@ void update_sta_vht_info_apmode(_adapter *padapter, PVOID sta)
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct vht_priv *pvhtpriv_ap = &pmlmepriv->vhtpriv;
struct vht_priv *pvhtpriv_sta = &psta->vhtpriv;
- struct ht_priv *phtpriv_sta = &psta->htpriv;
- u8 cur_ldpc_cap = 0, cur_stbc_cap = 0, bw_mode = 0;
- u16 cur_beamform_cap = 0;
+ u8 cur_ldpc_cap = 0, cur_stbc_cap = 0;
+ s8 bw_mode = -1;
u8 *pcap_mcs;
if (pvhtpriv_sta->vht_option == _FALSE)
return;
- bw_mode = GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(&pvhtpriv_sta->vht_op_mode_notify);
+ if (pvhtpriv_sta->op_present) {
+ switch (GET_VHT_OPERATION_ELE_CHL_WIDTH(pvhtpriv_sta->vht_op)) {
+ case 1: /* 80MHz */
+ case 2: /* 160MHz */
+ case 3: /* 80+80 */
+ bw_mode = CHANNEL_WIDTH_80; /* only support up to 80MHz for now */
+ break;
+ }
+ }
+
+ if (pvhtpriv_sta->notify_present)
+ bw_mode = GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(&pvhtpriv_sta->vht_op_mode_notify);
+ else if (MLME_IS_AP(padapter)) {
+ /* for VHT client without Operating Mode Notify IE; minimal 80MHz */
+ if (bw_mode < CHANNEL_WIDTH_80)
+ bw_mode = CHANNEL_WIDTH_80;
+ }
+
+ if (bw_mode != -1)
+ psta->cmn.bw_mode = bw_mode; /* update bw_mode only if get value from VHT IEs */
- /* if (bw_mode > psta->bw_mode) */
- psta->bw_mode = bw_mode;
+ psta->cmn.ra_info.is_vht_enable = _TRUE;
/* B4 Rx LDPC */
if (TEST_FLAG(pvhtpriv_ap->ldpc_cap, LDPC_VHT_ENABLE_TX) &&
GET_VHT_CAPABILITY_ELE_RX_LDPC(pvhtpriv_sta->vht_cap)) {
SET_FLAG(cur_ldpc_cap, (LDPC_VHT_ENABLE_TX | LDPC_VHT_CAP_TX));
- RTW_INFO("Current STA(%d) VHT LDPC = %02X\n", psta->aid, cur_ldpc_cap);
+ RTW_INFO("Current STA(%d) VHT LDPC = %02X\n", psta->cmn.aid, cur_ldpc_cap);
}
pvhtpriv_sta->ldpc_cap = cur_ldpc_cap;
- if (psta->bw_mode > pmlmeext->cur_bwmode)
- psta->bw_mode = pmlmeext->cur_bwmode;
+ if (psta->cmn.bw_mode > pmlmeext->cur_bwmode)
+ psta->cmn.bw_mode = pmlmeext->cur_bwmode;
- if (psta->bw_mode == CHANNEL_WIDTH_80) {
+ if (psta->cmn.bw_mode == CHANNEL_WIDTH_80) {
/* B5 Short GI for 80 MHz */
pvhtpriv_sta->sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI80M(pvhtpriv_sta->vht_cap) & pvhtpriv_ap->sgi_80m) ? _TRUE : _FALSE;
/* RTW_INFO("Current STA ShortGI80MHz = %d\n", pvhtpriv_sta->sgi_80m); */
- } else if (psta->bw_mode >= CHANNEL_WIDTH_160) {
+ } else if (psta->cmn.bw_mode >= CHANNEL_WIDTH_160) {
/* B5 Short GI for 80 MHz */
pvhtpriv_sta->sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI160M(pvhtpriv_sta->vht_cap) & pvhtpriv_ap->sgi_80m) ? _TRUE : _FALSE;
/* RTW_INFO("Current STA ShortGI160MHz = %d\n", pvhtpriv_sta->sgi_80m); */
@@ -332,29 +460,12 @@ void update_sta_vht_info_apmode(_adapter *padapter, PVOID sta)
if (TEST_FLAG(pvhtpriv_ap->stbc_cap, STBC_VHT_ENABLE_TX) &&
GET_VHT_CAPABILITY_ELE_RX_STBC(pvhtpriv_sta->vht_cap)) {
SET_FLAG(cur_stbc_cap, (STBC_VHT_ENABLE_TX | STBC_VHT_CAP_TX));
- RTW_INFO("Current STA(%d) VHT STBC = %02X\n", psta->aid, cur_stbc_cap);
+ RTW_INFO("Current STA(%d) VHT STBC = %02X\n", psta->cmn.aid, cur_stbc_cap);
}
pvhtpriv_sta->stbc_cap = cur_stbc_cap;
#ifdef CONFIG_BEAMFORMING
- /* B11 SU Beamformer Capable, the target supports Beamformer and we are Beamformee */
- if (TEST_FLAG(pvhtpriv_ap->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE) &&
- GET_VHT_CAPABILITY_ELE_SU_BFEE(pvhtpriv_sta->vht_cap)) {
- SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE);
- /*Shift to BEAMFORMING_VHT_BEAMFORMER_STS_CAP*/
- SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(pvhtpriv_sta->vht_cap) << 8);
- }
-
- /* B12 SU Beamformee Capable, the target supports Beamformee and we are Beamformer */
- if (TEST_FLAG(pvhtpriv_ap->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) &&
- GET_VHT_CAPABILITY_ELE_SU_BFER(pvhtpriv_sta->vht_cap)) {
- SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE);
- /*Shit to BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM*/
- SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(pvhtpriv_sta->vht_cap) << 12);
- }
- pvhtpriv_sta->beamform_cap = cur_beamform_cap;
- if (cur_beamform_cap)
- RTW_INFO("Current STA(%d) VHT Beamforming Setting = %02X\n", psta->aid, cur_beamform_cap);
+ update_sta_vht_info_apmode_bf_cap(padapter, psta);
#endif
/* B23 B24 B25 Maximum A-MPDU Length Exponent */
@@ -362,9 +473,7 @@ void update_sta_vht_info_apmode(_adapter *padapter, PVOID sta)
pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pvhtpriv_sta->vht_cap);
_rtw_memcpy(pvhtpriv_sta->vht_mcs_map, pcap_mcs, 2);
-
pvhtpriv_sta->vht_highest_rate = rtw_get_vht_highest_rate(pvhtpriv_sta->vht_mcs_map);
-
}
void update_hw_vht_param(_adapter *padapter)
@@ -383,14 +492,14 @@ void update_hw_vht_param(_adapter *padapter)
void VHT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
{
+ struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
- u8 cur_ldpc_cap = 0, cur_stbc_cap = 0, rf_type = RF_1T1R;
+ u8 cur_ldpc_cap = 0, cur_stbc_cap = 0, rf_type = RF_1T1R, tx_nss = 0;
u16 cur_beamform_cap = 0;
u8 *pcap_mcs;
- u8 vht_mcs[2];
if (pIE == NULL)
return;
@@ -489,18 +598,9 @@ void VHT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
pvhtpriv->ampdu_len = GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pIE->data);
pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pIE->data);
- _rtw_memcpy(vht_mcs, pcap_mcs, 2);
-
rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
- if ((rf_type == RF_1T1R) || (rf_type == RF_1T2R))
- vht_mcs[0] |= 0xfc;
- else if (rf_type == RF_2T2R)
- vht_mcs[0] |= 0xf0;
- else if (rf_type == RF_3T3R)
- vht_mcs[0] |= 0xc0;
-
- _rtw_memcpy(pvhtpriv->vht_mcs_map, vht_mcs, 2);
-
+ tx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num);
+ rtw_vht_nss_to_mcsmap(tx_nss, pvhtpriv->vht_mcs_map, pcap_mcs);
pvhtpriv->vht_highest_rate = rtw_get_vht_highest_rate(pvhtpriv->vht_mcs_map);
}
@@ -526,7 +626,6 @@ void rtw_process_vht_op_mode_notify(_adapter *padapter, u8 *pframe, PVOID sta)
u8 target_bw;
u8 target_rxss, current_rxss;
u8 update_ra = _FALSE;
- u8 vht_mcs_map[2] = {};
if (pvhtpriv->vht_option == _FALSE)
return;
@@ -534,23 +633,25 @@ void rtw_process_vht_op_mode_notify(_adapter *padapter, u8 *pframe, PVOID sta)
target_bw = GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(pframe);
target_rxss = (GET_VHT_OPERATING_MODE_FIELD_RX_NSS(pframe) + 1);
- if (target_bw != psta->bw_mode) {
+ if (target_bw != psta->cmn.bw_mode) {
if (hal_is_bw_support(padapter, target_bw)
&& REGSTY_IS_BW_5G_SUPPORT(regsty, target_bw)
) {
update_ra = _TRUE;
- psta->bw_mode = target_bw;
+ psta->cmn.bw_mode = target_bw;
}
}
current_rxss = rtw_vht_mcsmap_to_nss(psta->vhtpriv.vht_mcs_map);
if (target_rxss != current_rxss) {
+ u8 vht_mcs_map[2] = {};
+
update_ra = _TRUE;
rtw_vht_nss_to_mcsmap(target_rxss, vht_mcs_map, psta->vhtpriv.vht_mcs_map);
_rtw_memcpy(psta->vhtpriv.vht_mcs_map, vht_mcs_map, 2);
- rtw_hal_update_sta_rate_mask(padapter, psta);
+ rtw_hal_update_sta_ra_info(padapter, psta);
}
if (update_ra)
@@ -563,12 +664,10 @@ u32 rtw_build_vht_operation_ie(_adapter *padapter, u8 *pbuf, u8 channel)
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
/* struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; */
- u8 ChnlWidth, center_freq, bw_mode, rf_type = 0;
+ u8 ChnlWidth, center_freq, bw_mode;
u32 len = 0;
u8 operation[5];
- rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
-
_rtw_memset(operation, 0, 5);
bw_mode = REGSTY_BW_5G(pregistrypriv); /* TODO: control op bw with other info */
@@ -589,34 +688,7 @@ u32 rtw_build_vht_operation_ie(_adapter *padapter, u8 *pbuf, u8 channel)
SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(operation, center_freq);/* Todo: need to set correct center channel */
SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(operation, 0);
- if (padapter->registrypriv.rf_config != RF_MAX_TYPE)
- rf_type = padapter->registrypriv.rf_config;
-
- switch (rf_type) {
- case RF_1T1R:
- operation[3] = 0xfe;
- operation[4] = 0xff;
- break;
- case RF_1T2R:
- case RF_2T2R:
- case RF_2T2R_GREEN:
- operation[3] = 0xfa;
- operation[4] = 0xff;
- break;
- case RF_2T3R:
- case RF_2T4R:
- case RF_3T3R:
- case RF_3T4R:
- operation[3] = 0xea;
- operation[4] = 0xff;
- break;
- case RF_4T4R:
- operation[3] = 0xaa;
- operation[4] = 0xff;
- break;
- default:
- RTW_INFO("%s, %d, unknown rf type\n", __func__, __LINE__);
- }
+ _rtw_memcpy(operation + 3, pvhtpriv->vht_mcs_map, 2);
rtw_set_ie(pbuf, EID_VHTOperation, 5, operation, &len);
@@ -629,18 +701,11 @@ u32 rtw_build_vht_op_mode_notify_ie(_adapter *padapter, u8 *pbuf, u8 bw)
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
u32 len = 0;
- u8 opmode = 0, rf_type = 0;
+ u8 opmode = 0;
u8 chnl_width, rx_nss;
chnl_width = bw;
-
- rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
- if (rf_type == RF_3T3R)
- rx_nss = 3;
- else if (rf_type == RF_2T2R)
- rx_nss = 2;
- else
- rx_nss = 1;
+ rx_nss = rtw_vht_mcsmap_to_nss(pvhtpriv->vht_mcs_map);
SET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(&opmode, chnl_width);
SET_VHT_OPERATING_MODE_FIELD_RX_NSS(&opmode, (rx_nss - 1));
@@ -663,6 +728,8 @@ u32 rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf)
struct registry_priv *pregistrypriv = &padapter->registrypriv;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
+ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
pcap = pvhtpriv->vht_cap;
_rtw_memset(pcap, 0, 32);
@@ -695,47 +762,68 @@ u32 rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf)
SET_VHT_CAPABILITY_ELE_CHL_WIDTH(pcap, 0);
/* B4 Rx LDPC */
- if (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_RX))
+ if (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_RX)) {
SET_VHT_CAPABILITY_ELE_RX_LDPC(pcap, 1);
+ RTW_INFO("[VHT] Declare supporting RX LDPC\n");
+ }
/* B5 ShortGI for 80MHz */
SET_VHT_CAPABILITY_ELE_SHORT_GI80M(pcap, pvhtpriv->sgi_80m ? 1 : 0); /* We can receive Short GI of 80M */
+ if (pvhtpriv->sgi_80m)
+ RTW_INFO("[VHT] Declare supporting SGI 80MHz\n");
/* B6 ShortGI for 160MHz */
/* SET_VHT_CAPABILITY_ELE_SHORT_GI160M(pcap, pvhtpriv->sgi_80m? 1 : 0); */
/* B7 Tx STBC */
- if (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX))
+ if (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX)) {
SET_VHT_CAPABILITY_ELE_TX_STBC(pcap, 1);
+ RTW_INFO("[VHT] Declare supporting TX STBC\n");
+ }
/* B8 B9 B10 Rx STBC */
if (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_RX)) {
rtw_hal_get_def_var(padapter, HAL_DEF_RX_STBC, (u8 *)(&rx_stbc_nss));
SET_VHT_CAPABILITY_ELE_RX_STBC(pcap, rx_stbc_nss);
+ RTW_INFO("[VHT] Declare supporting RX STBC = %d\n", rx_stbc_nss);
}
-
+ #ifdef CONFIG_BEAMFORMING
/* B11 SU Beamformer Capable */
if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) {
SET_VHT_CAPABILITY_ELE_SU_BFER(pcap, 1);
+ RTW_INFO("[VHT] Declare supporting SU Bfer\n");
/* B16 17 18 Number of Sounding Dimensions */
rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMER_CAP, (u8 *)&rf_num);
SET_VHT_CAPABILITY_ELE_SOUNDING_DIMENSIONS(pcap, rf_num);
/* B19 MU Beamformer Capable */
- if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE))
+ if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) {
SET_VHT_CAPABILITY_ELE_MU_BFER(pcap, 1);
+ RTW_INFO("[VHT] Declare supporting MU Bfer\n");
+ }
}
/* B12 SU Beamformee Capable */
if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) {
SET_VHT_CAPABILITY_ELE_SU_BFEE(pcap, 1);
- /* B13 14 15 Compressed Steering Number of Beamformer Antennas Supported */
+ RTW_INFO("[VHT] Declare supporting SU Bfee\n");
+
rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMEE_CAP, (u8 *)&rf_num);
+
+ /* IOT action suggested by Yu Chen 2017/3/3 */
+ if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM) &&
+ !GET_VHT_CAPABILITY_ELE_MU_BFER(&pvhtpriv->beamform_cap))
+ rf_num = (rf_num >= 2 ? 2 : rf_num);
+
+ /* B13 14 15 Compressed Steering Number of Beamformer Antennas Supported */
SET_VHT_CAPABILITY_ELE_BFER_ANT_SUPP(pcap, rf_num);
/* B20 SU Beamformee Capable */
- if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE))
+ if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)) {
SET_VHT_CAPABILITY_ELE_MU_BFEE(pcap, 1);
+ RTW_INFO("[VHT] Declare supporting MU Bfee\n");
+ }
}
+ #endif/*CONFIG_BEAMFORMING*/
/* B21 VHT TXOP PS */
SET_VHT_CAPABILITY_ELE_TXOP_PS(pcap, 0);
@@ -771,61 +859,101 @@ u32 rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf)
u32 rtw_restructure_vht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len)
{
- u32 ielen = 0, out_len = 0;
- u8 cap_len = 0, notify_len = 0, notify_bw = 0, operation_bw = 0, supported_chnl_width = 0;
- u8 *p, *pframe;
+ u32 ielen;
+ u8 max_bw;
+ u8 oper_ch, oper_bw = CHANNEL_WIDTH_20, oper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+ u8 *out_vht_op_ie, *ht_op_ie, *vht_cap_ie, *vht_op_ie;
struct registry_priv *pregistrypriv = &padapter->registrypriv;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
rtw_vht_use_default_setting(padapter);
- p = rtw_get_ie(in_ie + 12, EID_VHTCapability, &ielen, in_len - 12);
- if (p && ielen > 0) {
- supported_chnl_width = GET_VHT_CAPABILITY_ELE_CHL_WIDTH(p + 2);
+ ht_op_ie = rtw_get_ie(in_ie + 12, WLAN_EID_HT_OPERATION, &ielen, in_len - 12);
+ if (!ht_op_ie || ielen != HT_OP_IE_LEN)
+ goto exit;
+ vht_cap_ie = rtw_get_ie(in_ie + 12, EID_VHTCapability, &ielen, in_len - 12);
+ if (!vht_cap_ie || ielen != VHT_CAP_IE_LEN)
+ goto exit;
+ vht_op_ie = rtw_get_ie(in_ie + 12, EID_VHTOperation, &ielen, in_len - 12);
+ if (!vht_op_ie || ielen != VHT_OP_IE_LEN)
+ goto exit;
- /* VHT Capabilities element */
- cap_len = rtw_build_vht_cap_ie(padapter, out_ie + *pout_len);
- *pout_len += cap_len;
+ /* VHT Capabilities element */
+ *pout_len += rtw_build_vht_cap_ie(padapter, out_ie + *pout_len);
- /* Get HT BW */
- p = rtw_get_ie(in_ie + 12, _HT_EXTRA_INFO_IE_, &ielen, in_len - 12);
- if (p && ielen > 0) {
- struct HT_info_element *pht_info = (struct HT_info_element *)(p + 2);
- if (pht_info->infos[0] & BIT(2))
- operation_bw = CHANNEL_WIDTH_40;
- else
- operation_bw = CHANNEL_WIDTH_20;
- }
- /* VHT Operation element */
- p = rtw_get_ie(in_ie + 12, EID_VHTOperation, &ielen, in_len - 12);
- if (p && ielen > 0) {
- out_len = *pout_len;
- if (GET_VHT_OPERATION_ELE_CHL_WIDTH(p + 2) >= 1) {
- if (supported_chnl_width == 2)
- operation_bw = CHANNEL_WIDTH_80_80;
- else if (supported_chnl_width == 1)
- operation_bw = CHANNEL_WIDTH_160;
- else
- operation_bw = CHANNEL_WIDTH_80;
+ /* VHT Operation element */
+ out_vht_op_ie = out_ie + *pout_len;
+ rtw_set_ie(out_vht_op_ie, EID_VHTOperation, VHT_OP_IE_LEN, vht_op_ie + 2 , pout_len);
+
+ /* get primary channel from HT_OP_IE */
+ oper_ch = GET_HT_OP_ELE_PRI_CHL(ht_op_ie + 2);
+
+ /* find the largest bw supported by both registry and hal */
+ max_bw = hal_largest_bw(padapter, REGSTY_BW_5G(pregistrypriv));
+
+ if (max_bw >= CHANNEL_WIDTH_40) {
+ /* get bw offset form HT_OP_IE */
+ if (GET_HT_OP_ELE_STA_CHL_WIDTH(ht_op_ie + 2)) {
+ switch (GET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2)) {
+ case SCA:
+ oper_bw = CHANNEL_WIDTH_40;
+ oper_offset = HAL_PRIME_CHNL_OFFSET_LOWER;
+ break;
+ case SCB:
+ oper_bw = CHANNEL_WIDTH_40;
+ oper_offset = HAL_PRIME_CHNL_OFFSET_UPPER;
+ break;
}
- pframe = rtw_set_ie(out_ie + out_len, EID_VHTOperation, ielen, p + 2 , pout_len);
}
- /* find the largest bw supported by both registry and hal */
- notify_bw = hal_largest_bw(padapter, REGSTY_BW_5G(pregistrypriv));
+ if (oper_bw == CHANNEL_WIDTH_40) {
+ switch (GET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2)) {
+ case 1: /* 80MHz */
+ case 2: /* 160MHz */
+ case 3: /* 80+80 */
+ oper_bw = CHANNEL_WIDTH_80; /* only support up to 80MHz for now */
+ break;
+ }
+
+ oper_bw = rtw_min(oper_bw, max_bw);
+
+ /* try downgrage bw to fit in channel plan setting */
+ while (!rtw_chset_is_chbw_valid(adapter_to_chset(padapter), oper_ch, oper_bw, oper_offset)) {
+ oper_bw--;
+ if (oper_bw == CHANNEL_WIDTH_20) {
+ oper_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+ break;
+ }
+ }
+ }
+ }
- if (notify_bw > operation_bw)
- notify_bw = operation_bw;
+ rtw_warn_on(!rtw_chset_is_chbw_valid(adapter_to_chset(padapter), oper_ch, oper_bw, oper_offset));
- /* Operating Mode Notification element */
- notify_len = rtw_build_vht_op_mode_notify_ie(padapter, out_ie + *pout_len, notify_bw);
- *pout_len += notify_len;
+ /* update VHT_OP_IE */
+ if (oper_bw < CHANNEL_WIDTH_80) {
+ SET_VHT_OPERATION_ELE_CHL_WIDTH(out_vht_op_ie + 2, 0);
+ SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(out_vht_op_ie + 2, 0);
+ SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(out_vht_op_ie + 2, 0);
+ } else if (oper_bw == CHANNEL_WIDTH_80) {
+ u8 cch = rtw_get_center_ch(oper_ch, oper_bw, oper_offset);
- pvhtpriv->vht_option = _TRUE;
+ SET_VHT_OPERATION_ELE_CHL_WIDTH(out_vht_op_ie + 2, 1);
+ SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(out_vht_op_ie + 2, cch);
+ SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(out_vht_op_ie + 2, 0);
+ } else {
+ RTW_ERR(FUNC_ADPT_FMT" unsupported BW:%u\n", FUNC_ADPT_ARG(padapter), oper_bw);
+ rtw_warn_on(1);
}
+ /* Operating Mode Notification element */
+ *pout_len += rtw_build_vht_op_mode_notify_ie(padapter, out_ie + *pout_len, oper_bw);
+
+ pvhtpriv->vht_option = _TRUE;
+
+exit:
return pvhtpriv->vht_option;
}
@@ -854,4 +982,72 @@ void VHTOnAssocRsp(_adapter *padapter)
rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_MAX_TIME, (u8 *)(&pvhtpriv->vht_highest_rate));
}
+void rtw_vht_ies_attach(_adapter *padapter, WLAN_BSSID_EX *pnetwork)
+{
+ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+ u8 cap_len, operation_len;
+ uint len = 0;
+ sint ie_len = 0;
+ u8 *p = NULL;
+
+ p = rtw_get_ie(pnetwork->IEs + _BEACON_IE_OFFSET_, EID_VHTCapability, &ie_len,
+ (pnetwork->IELength - _BEACON_IE_OFFSET_));
+ if (p && ie_len > 0)
+ return;
+
+ rtw_vht_use_default_setting(padapter);
+
+ /* VHT Operation mode notifiy bit in Extended IE (127) */
+ SET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(pmlmepriv->ext_capab_ie_data, 1);
+ pmlmepriv->ext_capab_ie_len = 10;
+ rtw_set_ie(pnetwork->IEs + pnetwork->IELength, EID_EXTCapability, 8, pmlmepriv->ext_capab_ie_data, &len);
+ pnetwork->IELength += pmlmepriv->ext_capab_ie_len;
+
+ /* VHT Capabilities element */
+ cap_len = rtw_build_vht_cap_ie(padapter, pnetwork->IEs + pnetwork->IELength);
+ pnetwork->IELength += cap_len;
+
+ /* VHT Operation element */
+ operation_len = rtw_build_vht_operation_ie(padapter, pnetwork->IEs + pnetwork->IELength,
+ pnetwork->Configuration.DSConfig);
+ pnetwork->IELength += operation_len;
+
+ rtw_check_for_vht20(padapter, pnetwork->IEs + _BEACON_IE_OFFSET_, pnetwork->IELength - _BEACON_IE_OFFSET_);
+
+ pmlmepriv->vhtpriv.vht_option = _TRUE;
+}
+
+void rtw_vht_ies_detach(_adapter *padapter, WLAN_BSSID_EX *pnetwork)
+{
+ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+
+ rtw_remove_bcn_ie(padapter, pnetwork, EID_EXTCapability);
+ rtw_remove_bcn_ie(padapter, pnetwork, EID_VHTCapability);
+ rtw_remove_bcn_ie(padapter, pnetwork, EID_VHTOperation);
+
+ pmlmepriv->vhtpriv.vht_option = _FALSE;
+}
+
+void rtw_check_for_vht20(_adapter *adapter, u8 *ies, int ies_len)
+{
+ u8 ht_ch, ht_bw, ht_offset;
+ u8 vht_ch, vht_bw, vht_offset;
+
+ rtw_ies_get_chbw(ies, ies_len, &ht_ch, &ht_bw, &ht_offset, 1, 0);
+ rtw_ies_get_chbw(ies, ies_len, &vht_ch, &vht_bw, &vht_offset, 1, 1);
+
+ if (ht_bw == CHANNEL_WIDTH_20 && vht_bw >= CHANNEL_WIDTH_80) {
+ u8 *vht_op_ie;
+ int vht_op_ielen;
+
+ RTW_INFO(FUNC_ADPT_FMT" vht80 is not allowed without ht40\n", FUNC_ADPT_ARG(adapter));
+ vht_op_ie = rtw_get_ie(ies, EID_VHTOperation, &vht_op_ielen, ies_len);
+ if (vht_op_ie && vht_op_ielen) {
+ RTW_INFO(FUNC_ADPT_FMT" switch to vht20\n", FUNC_ADPT_ARG(adapter));
+ SET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2, 0);
+ SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op_ie + 2, 0);
+ SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op_ie + 2, 0);
+ }
+ }
+}
#endif /* CONFIG_80211AC_VHT */
diff --git a/core/rtw_wapi.c b/core/rtw_wapi.c
index eb1605e..e065b3d 100644
--- a/core/rtw_wapi.c
+++ b/core/rtw_wapi.c
@@ -1,3 +1,17 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
#ifdef CONFIG_WAPI_SUPPORT
#include
@@ -161,14 +175,12 @@ WapiGetEntryForCamWrite(_adapter *padapter, u8 *pMacAddr, u8 KID, BOOLEAN IsMsk)
/*
if(RTIsListEmpty(&pWapiInfo->wapiCamIdleList)) {
- RT_TRACE(COMP_SEC,DBG_LOUD,("No Entry for wapi!!!\n"));
return 0;
}
pEntry = (PRT_WAPI_CAM_ENTRY)RTRemoveHeadList(&pWapiInfo->wapiCamIdleList);
RTInsertTailList(&pWapiInfo->wapiCamUsedList, &pEntry->list);
- RT_TRACE(COMP_SEC,DBG_LOUD,("<====WapiGetCamEntry(),Get Entry Idx:%d.but we just return 4 for test\n",pEntry->entry_idx));
return pEntry->entry_idx;*/
}
@@ -200,7 +212,6 @@ u8 WapiGetEntryForCamClear(_adapter *padapter, u8 *pPeerMac, u8 keyid, u8 IsMsk)
return 0xff;
/*
if(RTIsListEmpty(&pWapiInfo->wapiCamUsedList)) {
- RT_TRACE(COMP_SEC,DBG_LOUD,("No Entry for wapi!!!\n"));
return FALSE;
}
@@ -371,7 +382,7 @@ u8 rtw_wapi_is_wai_packet(_adapter *padapter, u8 *pkt_data)
return 0;
}
- pTaddr = GetAddr2Ptr(pkt_data);
+ pTaddr = get_addr2_ptr(pkt_data);
if (list_empty(&pWapiInfo->wapiSTAUsedList))
bFind = false;
else {
@@ -426,7 +437,7 @@ void rtw_wapi_update_info(_adapter *padapter, union recv_frame *precv_frame)
else
precv_hdr->UserPriority = 0;
- pTA = GetAddr2Ptr(ptr);
+ pTA = get_addr2_ptr(ptr);
_rtw_memcpy((u8 *)precv_hdr->WapiSrcAddr, pTA, 6);
pRecvPN = ptr + precv_hdr->attrib.hdrlen + 2;
_rtw_memcpy((u8 *)precv_hdr->WapiTempPN, pRecvPN, 16);
@@ -441,7 +452,8 @@ add to support WAPI to N-mode
*****************************************************************************/
u8 rtw_wapi_check_for_drop(
_adapter *padapter,
- union recv_frame *precv_frame
+ union recv_frame *precv_frame,
+ u8 *ehdr_ops
)
{
PRT_WAPI_T pWapiInfo = &(padapter->wapiInfo);
@@ -452,7 +464,7 @@ u8 rtw_wapi_check_for_drop(
struct recv_frame_hdr *precv_hdr = &precv_frame->u.hdr;
u8 WapiAEPNInitialValueSrc[16] = {0x37, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;
u8 WapiAEMultiCastPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;
- u8 *ptr = precv_frame->u.hdr.rx_data;
+ u8 *ptr = ehdr_ops;
int i;
WAPI_TRACE(WAPI_RX, "===========> %s\n", __FUNCTION__);
@@ -1240,4 +1252,61 @@ bool rtw_wapi_drop_for_key_absent(_adapter *padapter, u8 *pRA)
return bDrop;
}
+void rtw_wapi_set_set_encryption(_adapter *padapter, struct ieee_param *param)
+{
+ struct security_priv *psecuritypriv = &padapter->securitypriv;
+ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+ PRT_WAPI_T pWapiInfo = &padapter->wapiInfo;
+ PRT_WAPI_STA_INFO pWapiSta;
+ u8 WapiASUEPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;
+ u8 WapiAEPNInitialValueSrc[16] = {0x37, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;
+ u8 WapiAEMultiCastPNInitialValueSrc[16] = {0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C, 0x36, 0x5C} ;
+
+ if (param->u.crypt.set_tx == 1) {
+ list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {
+ if (_rtw_memcmp(pWapiSta->PeerMacAddr, param->sta_addr, 6)) {
+ _rtw_memcpy(pWapiSta->lastTxUnicastPN, WapiASUEPNInitialValueSrc, 16);
+
+ pWapiSta->wapiUsk.bSet = true;
+ _rtw_memcpy(pWapiSta->wapiUsk.dataKey, param->u.crypt.key, 16);
+ _rtw_memcpy(pWapiSta->wapiUsk.micKey, param->u.crypt.key + 16, 16);
+ pWapiSta->wapiUsk.keyId = param->u.crypt.idx ;
+ pWapiSta->wapiUsk.bTxEnable = true;
+
+ _rtw_memcpy(pWapiSta->lastRxUnicastPNBEQueue, WapiAEPNInitialValueSrc, 16);
+ _rtw_memcpy(pWapiSta->lastRxUnicastPNBKQueue, WapiAEPNInitialValueSrc, 16);
+ _rtw_memcpy(pWapiSta->lastRxUnicastPNVIQueue, WapiAEPNInitialValueSrc, 16);
+ _rtw_memcpy(pWapiSta->lastRxUnicastPNVOQueue, WapiAEPNInitialValueSrc, 16);
+ _rtw_memcpy(pWapiSta->lastRxUnicastPN, WapiAEPNInitialValueSrc, 16);
+ pWapiSta->wapiUskUpdate.bTxEnable = false;
+ pWapiSta->wapiUskUpdate.bSet = false;
+
+ if (psecuritypriv->sw_encrypt == false || psecuritypriv->sw_decrypt == false) {
+ /* set unicast key for ASUE */
+ rtw_wapi_set_key(padapter, &pWapiSta->wapiUsk, pWapiSta, false, false);
+ }
+ }
+ }
+ } else {
+ list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) {
+ if (_rtw_memcmp(pWapiSta->PeerMacAddr, get_bssid(pmlmepriv), 6)) {
+ pWapiSta->wapiMsk.bSet = true;
+ _rtw_memcpy(pWapiSta->wapiMsk.dataKey, param->u.crypt.key, 16);
+ _rtw_memcpy(pWapiSta->wapiMsk.micKey, param->u.crypt.key + 16, 16);
+ pWapiSta->wapiMsk.keyId = param->u.crypt.idx ;
+ pWapiSta->wapiMsk.bTxEnable = false;
+ if (!pWapiSta->bSetkeyOk)
+ pWapiSta->bSetkeyOk = true;
+ pWapiSta->bAuthenticateInProgress = false;
+
+ _rtw_memcpy(pWapiSta->lastRxMulticastPN, WapiAEMultiCastPNInitialValueSrc, 16);
+
+ if (psecuritypriv->sw_decrypt == false) {
+ /* set rx broadcast key for ASUE */
+ rtw_wapi_set_key(padapter, &pWapiSta->wapiMsk, pWapiSta, true, false);
+ }
+ }
+ }
+ }
+}
#endif
diff --git a/core/rtw_wapi_sms4.c b/core/rtw_wapi_sms4.c
index fc01212..4b7cf95 100644
--- a/core/rtw_wapi_sms4.c
+++ b/core/rtw_wapi_sms4.c
@@ -1,3 +1,17 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
#ifdef CONFIG_WAPI_SUPPORT
#include
diff --git a/core/rtw_wlan_util.c b/core/rtw_wlan_util.c
index a9b4a6f..f9e4bb8 100644
--- a/core/rtw_wlan_util.c
+++ b/core/rtw_wlan_util.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,21 +11,19 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#define _RTW_WLAN_UTIL_C_
#include
+#include
#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
#include
#define ETH_TYPE_OFFSET 12
#define PROTOCOL_OFFSET 23
#define IP_OFFSET 30
+ #define IPv6_OFFSET 38
+ #define IPv6_PROTOCOL_OFFSET 20
#endif
unsigned char ARTHEROS_OUI1[] = {0x00, 0x03, 0x7f};
@@ -74,6 +72,39 @@ static u8 rtw_basic_rate_mix[7] = {
IEEE80211_OFDM_RATE_24MB | IEEE80211_BASIC_RATE_MASK
};
+/* test if rate is defined in rtw_basic_rate_cck */
+bool rtw_is_basic_rate_cck(u8 rate)
+{
+ int i;
+
+ for (i = 0; i < 4; i++)
+ if ((rtw_basic_rate_cck[i] & 0x7F) == (rate & 0x7F))
+ return 1;
+ return 0;
+}
+
+/* test if rate is defined in rtw_basic_rate_ofdm */
+bool rtw_is_basic_rate_ofdm(u8 rate)
+{
+ int i;
+
+ for (i = 0; i < 3; i++)
+ if ((rtw_basic_rate_ofdm[i] & 0x7F) == (rate & 0x7F))
+ return 1;
+ return 0;
+}
+
+/* test if rate is defined in rtw_basic_rate_mix */
+bool rtw_is_basic_rate_mix(u8 rate)
+{
+ int i;
+
+ for (i = 0; i < 7; i++)
+ if ((rtw_basic_rate_mix[i] & 0x7F) == (rate & 0x7F))
+ return 1;
+ return 0;
+}
+
int new_bcn_max = 3;
int cckrates_included(unsigned char *rate, int ratelen)
@@ -103,214 +134,62 @@ int cckratesonly_included(unsigned char *rate, int ratelen)
return _TRUE;
}
-s8 rtw_get_tx_nss(_adapter *adapter, struct sta_info *psta)
+s8 rtw_get_sta_rx_nss(_adapter *adapter, struct sta_info *psta)
{
- u8 rf_type = RF_1T1R, custom_rf_type, vht_mcs[2];
+ struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+ u8 rf_type = RF_1T1R, custom_rf_type;
s8 nss = 1;
- custom_rf_type = adapter->registrypriv.rf_config;
- rtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
-
if (!psta)
return nss;
- /* rf_config is dependent on efuse or sw config */
- if (custom_rf_type != RF_MAX_TYPE)
+ custom_rf_type = adapter->registrypriv.rf_config;
+ rtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
+ if (RF_TYPE_VALID(custom_rf_type))
rf_type = custom_rf_type;
-#ifdef CONFIG_80211AC_VHT
- if (psta->vhtpriv.vht_option) {
- u8 vht_mcs[2];
- struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
- struct vht_priv *pvhtpriv_ap = &pmlmepriv->vhtpriv;
-
- _rtw_memcpy(vht_mcs, psta->vhtpriv.vht_mcs_map, 2);
- /* doesn't support 5~8 SS so far */
- vht_mcs[1] = 0xff;
- switch (rf_type) {
- case RF_1T1R:
- case RF_1T2R:
- vht_mcs[0] |= 0xfc;
- break;
- case RF_2T2R:
- case RF_2T4R:
- case RF_2T2R_GREEN:
- case RF_2T3R:
- vht_mcs[0] |= 0xf0;
- break;
- case RF_3T3R:
- case RF_3T4R:
- vht_mcs[0] |= 0xc0;
- break;
- default:
- RTW_INFO("%s,%d, unknown rf type\n", __func__, __LINE__);
- break;
- }
- nss = rtw_vht_mcsmap_to_nss(vht_mcs);
- } else
-#endif /* CONFIG_80211AC_VHT */
- if (psta->htpriv.ht_option) {
- u8 supp_mcs_set[4];
-
- _rtw_memcpy(supp_mcs_set, psta->htpriv.ht_cap.supp_mcs_set, 4);
-
- switch (rf_type) {
- case RF_1T1R:
- case RF_1T2R:
- supp_mcs_set[1] = supp_mcs_set[2] = supp_mcs_set[3] = 0;
- break;
- case RF_2T2R:
- case RF_2T4R:
- case RF_2T2R_GREEN:
- case RF_2T3R:
- supp_mcs_set[2] = supp_mcs_set[3] = 0;
- break;
- case RF_3T3R:
- case RF_3T4R:
- supp_mcs_set[3] = 0;
- break;
- default:
- RTW_INFO("%s,%d, unknown rf type\n", __func__, __LINE__);
- break;
- }
- nss = rtw_ht_mcsset_to_nss(supp_mcs_set);
- }
+ nss = rtw_min(rf_type_to_rf_rx_cnt(rf_type), hal_spec->rx_nss_num);
- RTW_INFO("%s: %d SS, rf_type=%d\n", __func__, nss, rf_type);
+#ifdef CONFIG_80211N_HT
+ #ifdef CONFIG_80211AC_VHT
+ if (psta->vhtpriv.vht_option)
+ nss = rtw_min(nss, rtw_vht_mcsmap_to_nss(psta->vhtpriv.vht_mcs_map));
+ else
+ #endif /* CONFIG_80211AC_VHT */
+ if (psta->htpriv.ht_option)
+ nss = rtw_min(nss, rtw_ht_mcsset_to_nss(psta->htpriv.ht_cap.supp_mcs_set));
+#endif /*CONFIG_80211N_HT*/
+ RTW_INFO("%s: %d SS\n", __func__, nss);
return nss;
}
-u8 networktype_to_raid(_adapter *adapter, struct sta_info *psta)
-{
- unsigned char raid;
- switch (psta->wireless_mode) {
- case WIRELESS_11B:
- raid = RATR_INX_WIRELESS_B;
- break;
- case WIRELESS_11A:
- case WIRELESS_11G:
- raid = RATR_INX_WIRELESS_G;
- break;
- case WIRELESS_11BG:
- raid = RATR_INX_WIRELESS_GB;
- break;
- case WIRELESS_11_24N:
- case WIRELESS_11_5N:
- raid = RATR_INX_WIRELESS_N;
- break;
- case WIRELESS_11A_5N:
- case WIRELESS_11G_24N:
- raid = RATR_INX_WIRELESS_NG;
- break;
- case WIRELESS_11BG_24N:
- raid = RATR_INX_WIRELESS_NGB;
- break;
- default:
- raid = RATR_INX_WIRELESS_GB;
- break;
-
- }
- return raid;
-
-}
-
-u8 networktype_to_raid_ex(_adapter *adapter, struct sta_info *psta)
+s8 rtw_get_sta_tx_nss(_adapter *adapter, struct sta_info *psta)
{
- struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
- u8 raid = RATEID_IDX_BGN_40M_1SS, cur_rf_type, rf_type, custom_rf_type;
- s8 tx_nss;
-
- tx_nss = rtw_get_tx_nss(adapter, psta);
-
- switch (psta->wireless_mode) {
- case WIRELESS_11B:
- raid = RATEID_IDX_B;
- break;
- case WIRELESS_11A:
- case WIRELESS_11G:
- raid = RATEID_IDX_G;
- break;
- case WIRELESS_11BG:
- raid = RATEID_IDX_BG;
- break;
- case WIRELESS_11_24N:
- case WIRELESS_11_5N:
- case WIRELESS_11A_5N:
- case WIRELESS_11G_24N:
- if (tx_nss == 1)
- raid = RATEID_IDX_GN_N1SS;
- else if (tx_nss == 2)
- raid = RATEID_IDX_GN_N2SS;
- else if (tx_nss == 3)
- raid = RATEID_IDX_BGN_3SS;
- else
- RTW_INFO("tx_nss error!(tx_nss=%d)\n", tx_nss);
- break;
- case WIRELESS_11B_24N:
- case WIRELESS_11BG_24N:
- if (psta->bw_mode == CHANNEL_WIDTH_20) {
- if (tx_nss == 1)
- raid = RATEID_IDX_BGN_20M_1SS_BN;
- else if (tx_nss == 2)
- raid = RATEID_IDX_BGN_20M_2SS_BN;
- else if (tx_nss == 3)
- raid = RATEID_IDX_BGN_3SS;
- else
- RTW_INFO("tx_nss error!(tx_nss=%d)\n", tx_nss);
- } else {
- if (tx_nss == 1)
- raid = RATEID_IDX_BGN_40M_1SS;
- else if (tx_nss == 2)
- raid = RATEID_IDX_BGN_40M_2SS;
- else if (tx_nss == 3)
- raid = RATEID_IDX_BGN_3SS;
- else
- RTW_INFO("tx_nss error!(tx_nss=%d)\n", tx_nss);
- }
- break;
-#ifdef CONFIG_80211AC_VHT
- case WIRELESS_11_5AC:
- if (tx_nss == 1)
- raid = RATEID_IDX_VHT_1SS;
- else if (tx_nss == 2)
- raid = RATEID_IDX_VHT_2SS;
- else if (tx_nss == 3)
- raid = RATEID_IDX_VHT_3SS;
- else
- RTW_INFO("tx_nss error!(tx_nss=%d)\n", tx_nss);
- break;
- case WIRELESS_11_24AC:
- if (psta->bw_mode >= CHANNEL_WIDTH_80) {
- if (tx_nss == 1)
- raid = RATEID_IDX_VHT_1SS;
- else if (tx_nss == 2)
- raid = RATEID_IDX_VHT_2SS;
- else if (tx_nss == 3)
- raid = RATEID_IDX_VHT_3SS;
- else
- RTW_INFO("tx_nss error!(tx_nss=%d)\n", tx_nss);
- } else {
- if (tx_nss == 1)
- raid = RATEID_IDX_MIX1;
- else if (tx_nss == 2)
- raid = RATEID_IDX_MIX2;
- else if (tx_nss == 3)
- raid = RATEID_IDX_VHT_3SS;
- else
- RTW_INFO("tx_nss error!(tx_nss=%d)\n", tx_nss);
- }
- break;
-#endif
- default:
- RTW_INFO("unexpected wireless mode!(psta->wireless_mode=%x)\n", psta->wireless_mode);
- break;
+ struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+ u8 rf_type = RF_1T1R, custom_rf_type;
+ s8 nss = 1;
- }
+ if (!psta)
+ return nss;
- /* RTW_INFO("psta->wireless_mode=%x, tx_nss=%d\n", psta->wireless_mode, tx_nss); */
+ custom_rf_type = adapter->registrypriv.rf_config;
+ rtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
+ if (RF_TYPE_VALID(custom_rf_type))
+ rf_type = custom_rf_type;
- return raid;
+ nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num);
+#ifdef CONFIG_80211N_HT
+ #ifdef CONFIG_80211AC_VHT
+ if (psta->vhtpriv.vht_option)
+ nss = rtw_min(nss, rtw_vht_mcsmap_to_nss(psta->vhtpriv.vht_mcs_map));
+ else
+ #endif /* CONFIG_80211AC_VHT */
+ if (psta->htpriv.ht_option)
+ nss = rtw_min(nss, rtw_ht_mcsset_to_nss(psta->htpriv.ht_cap.supp_mcs_set));
+#endif /*CONFIG_80211N_HT*/
+ RTW_INFO("%s: %d SS\n", __func__, nss);
+ return nss;
}
u8 judge_network_type(_adapter *padapter, unsigned char *rate, int ratelen)
@@ -432,6 +311,9 @@ unsigned int ratetbl2rateset(_adapter *padapter, unsigned char *rateset)
for (i = 0; i < NumRates; i++) {
rate = pmlmeext->datarate[i];
+ if (rtw_get_oper_ch(padapter) > 14 && rate < _6M_RATE_) /*5G no support CCK rate*/
+ continue;
+
switch (rate) {
case 0xff:
return len;
@@ -599,13 +481,19 @@ u8 rtw_get_offset_by_chbw(u8 ch, u8 bw, u8 *r_offset)
goto exit;
}
- /* TODO: 2.4G 40MHz offset choise */
-
if (ch >= 1 && ch <= 4)
offset = HAL_PRIME_CHNL_OFFSET_LOWER;
- else if (ch >= 5 && ch <= 14)
+ else if (ch >= 5 && ch <= 9) {
+ if (*r_offset == HAL_PRIME_CHNL_OFFSET_LOWER || *r_offset == HAL_PRIME_CHNL_OFFSET_UPPER)
+ offset = *r_offset; /* both lower and upper is valid, obey input value */
+ else
+ offset = HAL_PRIME_CHNL_OFFSET_UPPER; /* default use upper */
+ } else if (ch >= 10 && ch <= 13)
offset = HAL_PRIME_CHNL_OFFSET_UPPER;
- else if (ch >= 36 && ch <= 177) {
+ else if (ch == 14) {
+ valid = 0; /* ch14 doesn't support 40MHz bandwidth */
+ goto exit;
+ } else if (ch >= 36 && ch <= 177) {
switch (ch) {
case 36:
case 44:
@@ -652,53 +540,6 @@ u8 rtw_get_offset_by_chbw(u8 ch, u8 bw, u8 *r_offset)
return valid;
}
-u8 rtw_get_offset_by_ch(u8 channel)
-{
- u8 offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
-
- if (channel >= 1 && channel <= 4)
- offset = HAL_PRIME_CHNL_OFFSET_LOWER;
- else if (channel >= 5 && channel <= 14)
- offset = HAL_PRIME_CHNL_OFFSET_UPPER;
- else {
- switch (channel) {
- case 36:
- case 44:
- case 52:
- case 60:
- case 100:
- case 108:
- case 116:
- case 124:
- case 132:
- case 149:
- case 157:
- offset = HAL_PRIME_CHNL_OFFSET_LOWER;
- break;
- case 40:
- case 48:
- case 56:
- case 64:
- case 104:
- case 112:
- case 120:
- case 128:
- case 136:
- case 153:
- case 161:
- offset = HAL_PRIME_CHNL_OFFSET_UPPER;
- break;
- default:
- offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
- break;
- }
-
- }
-
- return offset;
-
-}
-
u8 rtw_get_center_ch(u8 channel, u8 chnl_bw, u8 chnl_offset)
{
u8 center_ch = channel;
@@ -733,12 +574,12 @@ u8 rtw_get_center_ch(u8 channel, u8 chnl_bw, u8 chnl_offset)
return center_ch;
}
-inline u32 rtw_get_on_oper_ch_time(_adapter *adapter)
+inline systime rtw_get_on_oper_ch_time(_adapter *adapter)
{
return adapter_to_dvobj(adapter)->on_oper_ch_time;
}
-inline u32 rtw_get_on_cur_ch_time(_adapter *adapter)
+inline systime rtw_get_on_cur_ch_time(_adapter *adapter)
{
if (adapter->mlmeextpriv.cur_channel == adapter_to_dvobj(adapter)->oper_channel)
return adapter_to_dvobj(adapter)->on_oper_ch_time;
@@ -746,110 +587,6 @@ inline u32 rtw_get_on_cur_ch_time(_adapter *adapter)
return 0;
}
-void SelectChannel(_adapter *padapter, unsigned char channel)
-{
- struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-
- _enter_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL);
-
-#ifdef CONFIG_MCC_MODE
- if (MCC_EN(padapter)) {
- /* driver doesn't set channel reg under MCC */
- if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
- RTW_INFO("Warning: Do not set channel reg MCC mode\n");
- rtw_warn_on(1);
- }
- }
-#endif
-
-#ifdef CONFIG_DFS_MASTER
- {
- struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
- bool ori_overlap_radar_detect_ch = rtw_rfctl_overlap_radar_detect_ch(rfctl);
- bool new_overlap_radar_detect_ch = _rtw_rfctl_overlap_radar_detect_ch(rfctl, channel
- , adapter_to_dvobj(padapter)->oper_bwmode, adapter_to_dvobj(padapter)->oper_ch_offset);
-
- if (new_overlap_radar_detect_ch)
- rtw_odm_radar_detect_enable(padapter);
-
- if (new_overlap_radar_detect_ch && IS_CH_WAITING(rfctl)) {
- u8 pause = 0xFF;
-
- rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, &pause);
- }
-#endif /* CONFIG_DFS_MASTER */
-
- /* saved channel info */
- rtw_set_oper_ch(padapter, channel);
-
- rtw_hal_set_chan(padapter, channel);
-
-#ifdef CONFIG_DFS_MASTER
- if (ori_overlap_radar_detect_ch && !new_overlap_radar_detect_ch) {
- u8 pause = 0x00;
-
- rtw_odm_radar_detect_disable(padapter);
- rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, &pause);
- }
- }
-#endif /* CONFIG_DFS_MASTER */
-
- _exit_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL);
-
-}
-
-void SetBWMode(_adapter *padapter, unsigned short bwmode, unsigned char channel_offset)
-{
- struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
-
- _enter_critical_mutex(&(adapter_to_dvobj(padapter)->setbw_mutex), NULL);
-
-#ifdef CONFIG_MCC_MODE
- if (MCC_EN(padapter)) {
- /* driver doesn't set bw reg under MCC */
- if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
- RTW_INFO("Warning: Do not set bw reg MCC mode\n");
- rtw_warn_on(1);
- }
- }
-#endif
-
-#ifdef CONFIG_DFS_MASTER
- {
- struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
- bool ori_overlap_radar_detect_ch = rtw_rfctl_overlap_radar_detect_ch(rfctl);
- bool new_overlap_radar_detect_ch = _rtw_rfctl_overlap_radar_detect_ch(rfctl
- , adapter_to_dvobj(padapter)->oper_channel, bwmode, channel_offset);
-
- if (new_overlap_radar_detect_ch)
- rtw_odm_radar_detect_enable(padapter);
-
- if (new_overlap_radar_detect_ch && IS_CH_WAITING(rfctl)) {
- u8 pause = 0xFF;
-
- rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, &pause);
- }
-#endif /* CONFIG_DFS_MASTER */
-
- /* saved bw info */
- rtw_set_oper_bw(padapter, bwmode);
- rtw_set_oper_choffset(padapter, channel_offset);
-
- rtw_hal_set_bwmode(padapter, (CHANNEL_WIDTH)bwmode, channel_offset);
-
-#ifdef CONFIG_DFS_MASTER
- if (ori_overlap_radar_detect_ch && !new_overlap_radar_detect_ch) {
- u8 pause = 0x00;
-
- rtw_odm_radar_detect_disable(padapter);
- rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, &pause);
- }
- }
-#endif /* CONFIG_DFS_MASTER */
-
- _exit_critical_mutex(&(adapter_to_dvobj(padapter)->setbw_mutex), NULL);
-}
-
void set_channel_bwmode(_adapter *padapter, unsigned char channel, unsigned char channel_offset, unsigned short bwmode)
{
u8 center_ch, chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
@@ -876,10 +613,8 @@ void set_channel_bwmode(_adapter *padapter, unsigned char channel, unsigned char
#ifdef CONFIG_MCC_MODE
if (MCC_EN(padapter)) {
/* driver doesn't set channel setting reg under MCC */
- if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
+ if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
RTW_INFO("Warning: Do not set channel setting reg MCC mode\n");
- rtw_warn_on(1);
- }
}
#endif
@@ -889,9 +624,6 @@ void set_channel_bwmode(_adapter *padapter, unsigned char channel, unsigned char
bool ori_overlap_radar_detect_ch = rtw_rfctl_overlap_radar_detect_ch(rfctl);
bool new_overlap_radar_detect_ch = _rtw_rfctl_overlap_radar_detect_ch(rfctl, channel, bwmode, channel_offset);
- if (new_overlap_radar_detect_ch)
- rtw_odm_radar_detect_enable(padapter);
-
if (new_overlap_radar_detect_ch && IS_CH_WAITING(rfctl)) {
u8 pause = 0xFF;
@@ -925,7 +657,9 @@ void set_channel_bwmode(_adapter *padapter, unsigned char channel, unsigned char
#endif
#ifdef CONFIG_DFS_MASTER
- if (ori_overlap_radar_detect_ch && !new_overlap_radar_detect_ch) {
+ if (new_overlap_radar_detect_ch)
+ rtw_odm_radar_detect_enable(padapter);
+ else if (ori_overlap_radar_detect_ch) {
u8 pause = 0x00;
rtw_odm_radar_detect_disable(padapter);
@@ -937,16 +671,6 @@ void set_channel_bwmode(_adapter *padapter, unsigned char channel, unsigned char
_exit_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL);
}
-int get_bsstype(unsigned short capability)
-{
- if (capability & BIT(0))
- return WIFI_FW_AP_STATE;
- else if (capability & BIT(1))
- return WIFI_FW_ADHOC_STATE;
- else
- return 0;
-}
-
__inline u8 *get_my_bssid(WLAN_BSSID_EX *pnetwork)
{
return pnetwork->MacAddress;
@@ -997,7 +721,7 @@ int is_IBSS_empty(_adapter *padapter)
for (i = 0; i < macid_ctl->num; i++) {
if (!rtw_macid_is_used(macid_ctl, i))
continue;
- if (rtw_macid_get_if_g(macid_ctl, i) != padapter->iface_id)
+ if (!rtw_macid_is_iface_specific(macid_ctl, i, padapter))
continue;
if (!GET_H2CCMD_MSRRPT_PARM_OPMODE(&macid_ctl->h2c_msr[i]))
continue;
@@ -1438,7 +1162,7 @@ s16 rtw_camid_search(_adapter *adapter, u8 *addr, s16 kid, s8 gk)
return cam_id;
}
-s16 rtw_get_camid(_adapter *adapter, struct sta_info *sta, u8 *addr, s16 kid)
+s16 rtw_get_camid(_adapter *adapter, u8 *addr, s16 kid, u8 gk)
{
struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
@@ -1459,7 +1183,7 @@ s16 rtw_get_camid(_adapter *adapter, struct sta_info *sta, u8 *addr, s16 kid)
/* find cam entry which has the same addr, kid (, gk bit) */
if (_rtw_camctl_chk_cap(adapter, SEC_CAP_CHK_BMC) == _TRUE)
- i = _rtw_camid_search(adapter, addr, kid, sta ? _FALSE : _TRUE);
+ i = _rtw_camid_search(adapter, addr, kid, gk);
else
i = _rtw_camid_search(adapter, addr, kid, -1);
@@ -1479,12 +1203,8 @@ s16 rtw_get_camid(_adapter *adapter, struct sta_info *sta, u8 *addr, s16 kid)
}
if (i == cam_ctl->num) {
- if (sta)
- RTW_PRINT(FUNC_ADPT_FMT" pairwise key with "MAC_FMT" id:%u no room\n"
- , FUNC_ADPT_ARG(adapter), MAC_ARG(addr), kid);
- else
- RTW_PRINT(FUNC_ADPT_FMT" group key with "MAC_FMT" id:%u no room\n"
- , FUNC_ADPT_ARG(adapter), MAC_ARG(addr), kid);
+ RTW_PRINT(FUNC_ADPT_FMT" %s key with "MAC_FMT" id:%u no room\n"
+ , FUNC_ADPT_ARG(adapter), gk ? "group" : "pairwise", MAC_ARG(addr), kid);
rtw_warn_on(1);
goto _exit;
}
@@ -1496,7 +1216,7 @@ s16 rtw_get_camid(_adapter *adapter, struct sta_info *sta, u8 *addr, s16 kid)
return cam_id;
}
-s16 rtw_camid_alloc(_adapter *adapter, struct sta_info *sta, u8 kid, bool *used)
+s16 rtw_camid_alloc(_adapter *adapter, struct sta_info *sta, u8 kid, u8 gk, bool *used)
{
struct mlme_ext_info *mlmeinfo = &adapter->mlmeextpriv.mlmext_info;
struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
@@ -1510,8 +1230,12 @@ s16 rtw_camid_alloc(_adapter *adapter, struct sta_info *sta, u8 kid, bool *used)
if ((((mlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) || ((mlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE))
&& !sta) {
+ /*
+ * 1. non-STA mode WEP key
+ * 2. group TX key
+ */
#ifndef CONFIG_CONCURRENT_MODE
- /* AP/Ad-hoc mode group key static alloction to default key by key ID on Non-concurrent*/
+ /* static alloction to default key by key ID when concurrent is not defined */
if (kid > 3) {
RTW_PRINT(FUNC_ADPT_FMT" group key with invalid key id:%u\n"
, FUNC_ADPT_ARG(adapter), kid);
@@ -1522,13 +1246,18 @@ s16 rtw_camid_alloc(_adapter *adapter, struct sta_info *sta, u8 kid, bool *used)
#else
u8 *addr = adapter_mac_addr(adapter);
- cam_id = rtw_get_camid(adapter, sta, addr, kid);
+ cam_id = rtw_get_camid(adapter, addr, kid, gk);
if (1)
RTW_PRINT(FUNC_ADPT_FMT" group key with "MAC_FMT" assigned cam_id:%u\n"
, FUNC_ADPT_ARG(adapter), MAC_ARG(addr), cam_id);
#endif
} else {
- u8 *addr = sta ? sta->hwaddr : NULL;
+ /*
+ * 1. STA mode WEP key
+ * 2. STA mode group RX key
+ * 3. sta key (pairwise, group RX)
+ */
+ u8 *addr = sta ? sta->cmn.mac_addr : NULL;
if (!sta) {
if (!(mlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) {
@@ -1537,7 +1266,7 @@ s16 rtw_camid_alloc(_adapter *adapter, struct sta_info *sta, u8 kid, bool *used)
}
addr = get_bssid(&adapter->mlmepriv);/*A2*/
}
- cam_id = rtw_get_camid(adapter, sta, addr, kid);
+ cam_id = rtw_get_camid(adapter, addr, kid, gk);
}
@@ -1669,6 +1398,14 @@ void rtw_clean_dk_section(_adapter *adapter)
}
}
}
+void rtw_clean_hw_dk_cam(_adapter *adapter)
+{
+ int i;
+
+ for (i = 0; i < 4; i++)
+ rtw_sec_clr_cam_ent(adapter, i);
+ /*_clear_cam_entry(adapter, i);*/
+}
void flush_all_cam_entry(_adapter *padapter)
{
@@ -1689,7 +1426,7 @@ void flush_all_cam_entry(_adapter *padapter)
} else
rtw_clearstakey_cmd(padapter, psta, _FALSE);
}
- } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) {
+ } else if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {
#if 1
int cam_id = -1;
u8 *addr = adapter_mac_addr(padapter);
@@ -1807,10 +1544,14 @@ void WMMOnAssocRsp(_adapter *padapter)
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
struct registry_priv *pregpriv = &padapter->registrypriv;
+#ifdef CONFIG_WMMPS_STA
+ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+ struct qos_priv *pqospriv = &pmlmepriv->qospriv;
+#endif /* CONFIG_WMMPS_STA */
acm_mask = 0;
- if (IsSupported5G(pmlmeext->cur_wireless_mode) ||
+ if (is_supported_5g(pmlmeext->cur_wireless_mode) ||
(pmlmeext->cur_wireless_mode & WIRELESS_11_24N))
aSifsTime = 16;
else
@@ -1932,6 +1673,14 @@ void WMMOnAssocRsp(_adapter *padapter)
pxmitpriv->wmm_para_seq[i] = inx[i];
RTW_INFO("wmm_para_seq(%d): %d\n", i, pxmitpriv->wmm_para_seq[i]);
}
+
+#ifdef CONFIG_WMMPS_STA
+ /* if AP supports UAPSD function, driver must set each uapsd TID to coresponding mac register 0x693 */
+ if (pmlmeinfo->WMM_param.QoS_info & AP_SUPPORTED_UAPSD) {
+ pqospriv->uapsd_ap_supported = 1;
+ rtw_hal_set_hwreg(padapter, HW_VAR_UAPSD_TID, NULL);
+ }
+#endif /* CONFIG_WMMPS_STA */
}
}
@@ -2024,10 +1773,10 @@ static void bwmode_update_check(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pI
if (phtpriv_sta->ht_option) {
/* bwmode */
- psta->bw_mode = pmlmeext->cur_bwmode;
+ psta->cmn.bw_mode = pmlmeext->cur_bwmode;
phtpriv_sta->ch_offset = pmlmeext->cur_ch_offset;
} else {
- psta->bw_mode = CHANNEL_WIDTH_20;
+ psta->cmn.bw_mode = CHANNEL_WIDTH_20;
phtpriv_sta->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
}
@@ -2045,12 +1794,13 @@ void HT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
unsigned int i;
u8 rf_type = RF_1T1R;
u8 max_AMPDU_len, min_MPDU_spacing;
- u8 cur_ldpc_cap = 0, cur_stbc_cap = 0, cur_beamform_cap = 0;
+ u8 cur_ldpc_cap = 0, cur_stbc_cap = 0, cur_beamform_cap = 0, tx_nss = 0;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct ht_priv *phtpriv = &pmlmepriv->htpriv;
struct registry_priv *pregistrypriv = &padapter->registrypriv;
+ struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
if (pIE == NULL)
return;
@@ -2090,39 +1840,38 @@ void HT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info = le16_to_cpu(pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info);
pmlmeinfo->HT_caps.u.HT_cap_element.HT_ext_caps = le16_to_cpu(pmlmeinfo->HT_caps.u.HT_cap_element.HT_ext_caps);
- rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
-
-
/* update the MCS set */
for (i = 0; i < 16; i++)
pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate[i] &= pmlmeext->default_supported_mcs_set[i];
- /* update the MCS rates */
- switch (rf_type) {
- case RF_1T1R:
- case RF_1T2R:
+ rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
+ tx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num);
+
+ switch (tx_nss) {
+ case 1:
set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_1R);
break;
- case RF_2T2R:
-#ifdef CONFIG_DISABLE_MCS13TO15
+ case 2:
+ #ifdef CONFIG_DISABLE_MCS13TO15
if (pmlmeext->cur_bwmode == CHANNEL_WIDTH_40 && pregistrypriv->wifi_spec != 1)
set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R_13TO15_OFF);
else
+ #endif
set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R);
-#else /* CONFIG_DISABLE_MCS13TO15 */
- set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R);
-#endif /* CONFIG_DISABLE_MCS13TO15 */
break;
- case RF_3T3R:
+ case 3:
set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_3R);
break;
+ case 4:
+ set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_4R);
+ break;
default:
- RTW_INFO("[warning] rf_type %d is not expected\n", rf_type);
+ RTW_WARN("rf_type:%d or tx_nss:%u is not expected\n", rf_type, hal_spec->tx_nss_num);
}
if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) {
/* Config STBC setting */
- if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX) && GET_HT_CAP_ELE_TX_STBC(pIE->data)) {
+ if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX) && GET_HT_CAP_ELE_RX_STBC(pIE->data)) {
SET_FLAG(cur_stbc_cap, STBC_HT_ENABLE_TX);
RTW_INFO("Enable HT Tx STBC !\n");
}
@@ -2164,6 +1913,22 @@ void HT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
phtpriv->stbc_cap = cur_stbc_cap;
#ifdef CONFIG_BEAMFORMING
+#ifdef RTW_BEAMFORMING_VERSION_2
+ /* Config beamforming setting */
+ if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE) &&
+ GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(pIE->data)) {
+ SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE);
+ /* Shift to BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP*/
+ SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(pIE->data) << 6);
+ }
+
+ if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE) &&
+ GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(pIE->data)) {
+ SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE);
+ /* Shift to BEAMFORMING_HT_BEAMFORMER_STEER_NUM*/
+ SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(pIE->data) << 4);
+ }
+#else /* !RTW_BEAMFORMING_VERSION_2 */
/* Config Tx beamforming setting */
if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE) &&
GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(pIE->data)) {
@@ -2178,6 +1943,7 @@ void HT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE)
/* Shift to BEAMFORMING_HT_BEAMFORMER_STEER_NUM*/
SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(pIE->data) << 4);
}
+#endif /* !RTW_BEAMFORMING_VERSION_2 */
phtpriv->beamform_cap = cur_beamform_cap;
if (cur_beamform_cap)
RTW_INFO("Client HT Beamforming Cap = 0x%02X\n", cur_beamform_cap);
@@ -2261,8 +2027,6 @@ void HTOnAssocRsp(_adapter *padapter)
pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
break;
}
-
- /* SelectChannel(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset); */
}
#endif
@@ -2329,8 +2093,8 @@ void VCS_update(_adapter *padapter, struct sta_info *psta)
case 2: /* auto */
default:
if (((pmlmeinfo->ERP_enable) && (pmlmeinfo->ERP_IE & BIT(1)))
- /*||(pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT)*/
- ) {
+ /*||(pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT)*/
+ ) {
if (pregpriv->vcs_type == 1) {
psta->rtsen = 1;
psta->cts2self = 0;
@@ -2353,26 +2117,77 @@ void update_ldpc_stbc_cap(struct sta_info *psta)
#ifdef CONFIG_80211AC_VHT
if (psta->vhtpriv.vht_option) {
if (TEST_FLAG(psta->vhtpriv.ldpc_cap, LDPC_VHT_ENABLE_TX))
- psta->ldpc = 1;
+ psta->cmn.ldpc_en = VHT_LDPC_EN;
+ else
+ psta->cmn.ldpc_en = 0;
if (TEST_FLAG(psta->vhtpriv.stbc_cap, STBC_VHT_ENABLE_TX))
- psta->stbc = 1;
+ psta->cmn.stbc_en = VHT_STBC_EN;
+ else
+ psta->cmn.stbc_en = 0;
} else
#endif /* CONFIG_80211AC_VHT */
if (psta->htpriv.ht_option) {
if (TEST_FLAG(psta->htpriv.ldpc_cap, LDPC_HT_ENABLE_TX))
- psta->ldpc = 1;
+ psta->cmn.ldpc_en = HT_LDPC_EN;
+ else
+ psta->cmn.ldpc_en = 0;
if (TEST_FLAG(psta->htpriv.stbc_cap, STBC_HT_ENABLE_TX))
- psta->stbc = 1;
+ psta->cmn.stbc_en = HT_STBC_EN;
+ else
+ psta->cmn.stbc_en = 0;
} else {
- psta->ldpc = 0;
- psta->stbc = 0;
+ psta->cmn.ldpc_en = 0;
+ psta->cmn.stbc_en = 0;
}
#endif /* CONFIG_80211N_HT */
}
+int check_ielen(u8 *start, uint len)
+{
+ int left = len;
+ u8 *pos = start;
+ int unknown = 0;
+ u8 id, elen;
+
+ while (left >= 2) {
+ id = *pos++;
+ elen = *pos++;
+ left -= 2;
+
+ if (elen > left) {
+ RTW_INFO("IEEE 802.11 element parse failed (id=%d elen=%d left=%lu)\n",
+ id, elen, (unsigned long) left);
+ return _FALSE;
+ }
+ if ((id == WLAN_EID_VENDOR_SPECIFIC) && (elen < 4))
+ return _FALSE;
+
+ left -= elen;
+ pos += elen;
+ }
+ if (left)
+ return _FALSE;
+
+ return _TRUE;
+}
+
+int validate_beacon_len(u8 *pframe, u32 len)
+{
+ u8 ie_offset = _BEACON_IE_OFFSET_ + sizeof(struct rtw_ieee80211_hdr_3addr);
+
+ if (len < ie_offset) {
+ RTW_INFO("%s: incorrect beacon length(%d)\n", __func__, len);
+ return _FALSE;
+ }
+
+ if (check_ielen(pframe + ie_offset, len - ie_offset) == _FALSE)
+ return _FALSE;
+
+ return _TRUE;
+}
/*
* rtw_get_bcn_keys: get beacon keys from recv frame
@@ -2449,7 +2264,7 @@ int rtw_get_bcn_keys(ADAPTER *Adapter, u8 *pframe, u32 packet_len,
recv_beacon->encryp_protocol = ENCRYP_PROTOCOL_WPA2;
rtw_parse_wpa2_ie(elems.rsn_ie - 2, elems.rsn_ie_len + 2,
&recv_beacon->group_cipher, &recv_beacon->pairwise_cipher,
- &recv_beacon->is_8021x);
+ &recv_beacon->is_8021x, NULL);
}
/* checking WPA secon */
else if (elems.wpa_ie && elems.wpa_ie_len) {
@@ -2516,12 +2331,12 @@ int rtw_check_bcn_info(ADAPTER *Adapter, u8 *pframe, u32 packet_len)
len = packet_len - sizeof(struct rtw_ieee80211_hdr_3addr);
if (len > MAX_IE_SZ) {
- RTW_INFO("%s IE too long for survey event\n", __func__);
+ RTW_WARN("%s IE too long for survey event\n", __func__);
return _FAIL;
}
if (_rtw_memcmp(cur_network->network.MacAddress, pbssid, 6) == _FALSE) {
- RTW_INFO("Oops: rtw_check_network_encrypt linked but recv other bssid bcn\n" MAC_FMT MAC_FMT,
+ RTW_WARN("Oops: rtw_check_network_encrypt linked but recv other bssid bcn\n" MAC_FMT MAC_FMT,
MAC_ARG(pbssid), MAC_ARG(cur_network->network.MacAddress));
return _TRUE;
}
@@ -2540,34 +2355,32 @@ int rtw_check_bcn_info(ADAPTER *Adapter, u8 *pframe, u32 packet_len)
pmlmepriv->new_beacon_cnts = 0;
else if ((pmlmepriv->new_beacon_cnts == 0) ||
_rtw_memcmp(&recv_beacon, &pmlmepriv->new_beacon_keys, sizeof(recv_beacon)) == _FALSE) {
- RTW_ERR("%s: start new beacon (seq=%d)\n", __func__, GetSequence(pframe));
+ RTW_DBG("%s: start new beacon (seq=%d)\n", __func__, GetSequence(pframe));
if (pmlmepriv->new_beacon_cnts == 0) {
RTW_ERR("%s: cur beacon key\n", __func__);
RTW_DBG_EXPR(rtw_dump_bcn_keys(&pmlmepriv->cur_beacon_keys));
}
- RTW_ERR("%s: new beacon key\n", __func__);
+ RTW_DBG("%s: new beacon key\n", __func__);
RTW_DBG_EXPR(rtw_dump_bcn_keys(&recv_beacon));
memcpy(&pmlmepriv->new_beacon_keys, &recv_beacon, sizeof(recv_beacon));
pmlmepriv->new_beacon_cnts = 1;
} else {
- RTW_ERR("%s: new beacon again (seq=%d)\n", __func__, GetSequence(pframe));
+ RTW_DBG("%s: new beacon again (seq=%d)\n", __func__, GetSequence(pframe));
pmlmepriv->new_beacon_cnts++;
}
/* if counter >= max, it means beacon is changed really */
if (pmlmepriv->new_beacon_cnts >= new_bcn_max) {
- RTW_ERR("%s: new beacon occur!!\n", __func__);
-
/* check bw mode change only? */
pmlmepriv->cur_beacon_keys.ht_cap_info = recv_beacon.ht_cap_info;
pmlmepriv->cur_beacon_keys.ht_info_infos_0_sco = recv_beacon.ht_info_infos_0_sco;
-
if (_rtw_memcmp(&recv_beacon, &pmlmepriv->cur_beacon_keys,
sizeof(recv_beacon)) == _FALSE) {
/* beacon is changed, have to do disconnect/connect */
+ RTW_WARN("%s: new beacon occur!!\n", __func__);
return _FAIL;
}
@@ -2603,7 +2416,7 @@ int rtw_check_bcn_info(ADAPTER *Adapter, u8 *pframe, u32 packet_len)
pmlmepriv->NumOfBcnInfoChkFail = 0;
}
- subtype = GetFrameSubType(pframe) >> 4;
+ subtype = get_frame_sub_type(pframe) >> 4;
if (subtype == WIFI_BEACON)
bssid->Reserved[0] = 1;
@@ -2680,10 +2493,6 @@ int rtw_check_bcn_info(ADAPTER *Adapter, u8 *pframe, u32 packet_len)
bssid->Ssid.Ssid[0] = '\0';
}
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("%s bssid.Ssid.Ssid:%s bssid.Ssid.SsidLength:%d "
- "cur_network->network.Ssid.Ssid:%s len:%d\n", __func__, bssid->Ssid.Ssid,
- bssid->Ssid.SsidLength, cur_network->network.Ssid.Ssid,
- cur_network->network.Ssid.SsidLength));
if (_rtw_memcmp(bssid->Ssid.Ssid, cur_network->network.Ssid.Ssid, 32) == _FALSE ||
bssid->Ssid.SsidLength != cur_network->network.Ssid.SsidLength) {
@@ -2701,9 +2510,6 @@ int rtw_check_bcn_info(ADAPTER *Adapter, u8 *pframe, u32 packet_len)
else
bssid->Privacy = 0;
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_,
- ("%s(): cur_network->network.Privacy is %d, bssid.Privacy is %d\n",
- __func__, cur_network->network.Privacy, bssid->Privacy));
if (cur_network->network.Privacy != bssid->Privacy) {
RTW_INFO("%s(), privacy is not match\n", __func__);
goto _mismatch;
@@ -2728,25 +2534,15 @@ int rtw_check_bcn_info(ADAPTER *Adapter, u8 *pframe, u32 packet_len)
if (encryp_protocol == ENCRYP_PROTOCOL_WPA || encryp_protocol == ENCRYP_PROTOCOL_WPA2) {
pbuf = rtw_get_wpa_ie(&bssid->IEs[12], &wpa_ielen, bssid->IELength - 12);
if (pbuf && (wpa_ielen > 0)) {
- if (_SUCCESS == rtw_parse_wpa_ie(pbuf, wpa_ielen + 2, &group_cipher, &pairwise_cipher, &is_8021x)) {
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_,
- ("%s pnetwork->pairwise_cipher: %d, group_cipher is %d, is_8021x is %d\n", __func__,
- pairwise_cipher, group_cipher, is_8021x));
- }
+ rtw_parse_wpa_ie(pbuf, wpa_ielen + 2, &group_cipher, &pairwise_cipher, &is_8021x);
} else {
pbuf = rtw_get_wpa2_ie(&bssid->IEs[12], &wpa_ielen, bssid->IELength - 12);
if (pbuf && (wpa_ielen > 0)) {
- if (_SUCCESS == rtw_parse_wpa2_ie(pbuf, wpa_ielen + 2, &group_cipher, &pairwise_cipher, &is_8021x)) {
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_,
- ("%s pnetwork->pairwise_cipher: %d, pnetwork->group_cipher is %d, is_802x is %d\n",
- __func__, pairwise_cipher, group_cipher, is_8021x));
- }
+ rtw_parse_wpa2_ie(pbuf, wpa_ielen + 2, &group_cipher, &pairwise_cipher, &is_8021x, NULL);
}
}
- RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_,
- ("%s cur_network->group_cipher is %d: %d\n", __func__, cur_network->BcnInfo.group_cipher, group_cipher));
if (pairwise_cipher != cur_network->BcnInfo.pairwise_cipher || group_cipher != cur_network->BcnInfo.group_cipher) {
RTW_INFO("%s pairwise_cipher(%x:%x) or group_cipher(%x:%x) is not match\n", __func__,
pairwise_cipher, cur_network->BcnInfo.pairwise_cipher,
@@ -2809,7 +2605,7 @@ void update_beacon_info(_adapter *padapter, u8 *pframe, uint pkt_len, struct sta
break;
- case _HT_EXTRA_INFO_IE_: /* HT info */
+ case _HT_EXTRA_INFO_IE_: /* HT info */
/* HT_info_handler(padapter, pIE); */
bwmode_update_check(padapter, pIE);
break;
@@ -2840,20 +2636,17 @@ void update_beacon_info(_adapter *padapter, u8 *pframe, uint pkt_len, struct sta
}
#ifdef CONFIG_DFS
-void process_csa_ie(_adapter *padapter, u8 *pframe, uint pkt_len)
+void process_csa_ie(_adapter *padapter, u8 *ies, uint ies_len)
{
unsigned int i;
- unsigned int len;
PNDIS_802_11_VARIABLE_IEs pIE;
u8 new_ch_no = 0;
if (padapter->mlmepriv.handle_dfs == _TRUE)
return;
- len = pkt_len - (_BEACON_IE_OFFSET_ + WLAN_HDR_A3_LEN);
-
- for (i = 0; i < len;) {
- pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + (_BEACON_IE_OFFSET_ + WLAN_HDR_A3_LEN) + i);
+ for (i = 0; i + 1 < ies_len;) {
+ pIE = (PNDIS_802_11_VARIABLE_IEs)(ies + i);
switch (pIE->ElementID) {
case _CH_SWTICH_ANNOUNCE_:
@@ -3062,15 +2855,6 @@ unsigned int update_supported_rate(unsigned char *ptn, unsigned int ptn_sz)
return mask;
}
-unsigned int update_MCS_rate(struct HT_caps_element *pHT_caps)
-{
- unsigned int mask = 0;
-
- mask = ((pHT_caps->u.HT_cap_element.MCS_rate[0] << 12) | (pHT_caps->u.HT_cap_element.MCS_rate[1] << 20));
-
- return mask;
-}
-
int support_short_GI(_adapter *padapter, struct HT_caps_element *pHT_caps, u8 bwmode)
{
unsigned char bit_offset;
@@ -3088,13 +2872,13 @@ int support_short_GI(_adapter *padapter, struct HT_caps_element *pHT_caps, u8 bw
return _FAIL;
}
-unsigned char get_highest_rate_idx(u32 mask)
+unsigned char get_highest_rate_idx(u64 mask)
{
int i;
unsigned char rate_idx = 0;
- for (i = 31; i >= 0; i--) {
- if (mask & BIT(i)) {
+ for (i = 63; i >= 0; i--) {
+ if ((mask >> i) & 0x01) {
rate_idx = i;
break;
}
@@ -3102,37 +2886,30 @@ unsigned char get_highest_rate_idx(u32 mask)
return rate_idx;
}
-
-unsigned char get_highest_mcs_rate(struct HT_caps_element *pHT_caps);
-unsigned char get_highest_mcs_rate(struct HT_caps_element *pHT_caps)
+unsigned char get_lowest_rate_idx_ex(u64 mask, int start_bit)
{
- int i, mcs_rate;
-
- mcs_rate = (pHT_caps->u.HT_cap_element.MCS_rate[0] | (pHT_caps->u.HT_cap_element.MCS_rate[1] << 8));
+ int i;
+ unsigned char rate_idx = 0;
- for (i = 15; i >= 0; i--) {
- if (mcs_rate & (0x1 << i))
+ for (i = start_bit; i < 64; i++) {
+ if ((mask >> i) & 0x01) {
+ rate_idx = i;
break;
+ }
}
- return i;
+ return rate_idx;
}
void Update_RA_Entry(_adapter *padapter, struct sta_info *psta)
{
- rtw_hal_update_ra_mask(psta, psta->rssi_level);
-}
-
-void enable_rate_adaptive(_adapter *padapter, struct sta_info *psta);
-void enable_rate_adaptive(_adapter *padapter, struct sta_info *psta)
-{
- Update_RA_Entry(padapter, psta);
+ rtw_hal_update_ra_mask(psta);
}
void set_sta_rate(_adapter *padapter, struct sta_info *psta)
{
/* rate adaptive */
- enable_rate_adaptive(padapter, psta);
+ rtw_hal_update_ra_mask(psta);
}
/* Update RRSR and Rate for USERATE */
@@ -3365,10 +3142,14 @@ void update_wireless_mode(_adapter *padapter)
rtw_hal_set_hwreg(padapter, HW_VAR_WIRELESS_MODE, (u8 *)&(pmlmeext->cur_wireless_mode));
if ((pmlmeext->cur_wireless_mode & WIRELESS_11B)
-#ifdef CONFIG_P2P
- && rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)
-#endif /* CONFIG_P2P */
- )
+ #ifdef CONFIG_P2P
+ && (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)
+ #ifdef CONFIG_IOCTL_CFG80211
+ || !rtw_cfg80211_iface_has_p2p_group_cap(padapter)
+ #endif
+ )
+ #endif
+ )
update_mgnt_tx_rate(padapter, IEEE80211_CCK_RATE_1MB);
else
update_mgnt_tx_rate(padapter, IEEE80211_OFDM_RATE_6MB);
@@ -3471,7 +3252,12 @@ void process_addba_req(_adapter *padapter, u8 *paddba_req, u8 *addr)
accept = rtw_rx_ampdu_is_accept(padapter);
- size = rtw_rx_ampdu_size(padapter);
+ if (padapter->fix_rx_ampdu_size != RX_AMPDU_SIZE_INVALID)
+ size = padapter->fix_rx_ampdu_size;
+ else {
+ size = rtw_rx_ampdu_size(padapter);
+ size = rtw_min(size, rx_ampdu_size_sta_limit(padapter, psta));
+ }
if (accept == _TRUE)
rtw_addbarsp_cmd(padapter, addr, tid, 0, size, start_seq);
@@ -3482,6 +3268,33 @@ void process_addba_req(_adapter *padapter, u8 *paddba_req, u8 *addr)
return;
}
+void rtw_process_bar_frame(_adapter *padapter, union recv_frame *precv_frame)
+{
+ struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
+ struct sta_priv *pstapriv = &padapter->stapriv;
+ u8 *pframe = precv_frame->u.hdr.rx_data;
+ struct sta_info *psta = NULL;
+ struct recv_reorder_ctrl *preorder_ctrl = NULL;
+ u8 tid = 0;
+ u16 start_seq=0;
+
+ psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe));
+ if (psta == NULL)
+ goto exit;
+
+ tid = ((cpu_to_le16((*(u16 *)(pframe + 16))) & 0xf000) >> 12);
+ preorder_ctrl = &psta->recvreorder_ctrl[tid];
+ start_seq = ((cpu_to_le16(*(u16 *)(pframe + 18))) >> 4);
+ preorder_ctrl->indicate_seq = start_seq;
+
+ /* for Debug use */
+ if (0)
+ RTW_INFO(FUNC_ADPT_FMT" tid=%d, start_seq=%d\n", FUNC_ADPT_ARG(padapter), tid, start_seq);
+
+exit:
+ return;
+}
+
void update_TSF(struct mlme_ext_priv *pmlmeext, u8 *pframe, uint len)
{
u8 *pIE;
@@ -3598,8 +3411,6 @@ void beacon_timing_control(_adapter *padapter)
rtw_hal_bcn_related_reg_setting(padapter);
}
-#define CONFIG_SHARED_BMC_MACID
-
void dump_macid_map(void *sel, struct macid_bmp *map, u8 max_num)
{
RTW_PRINT_SEL(sel, "0x%08x\n", map->m0);
@@ -3659,22 +3470,6 @@ inline void rtw_macid_map_set(struct macid_bmp *map, u8 id)
rtw_warn_on(1);
}
-/*Record bc's mac-id and sec-cam-id*/
-inline void rtw_iface_bcmc_id_set(_adapter *padapter, u8 mac_id)
-{
- struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
- struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
-
- macid_ctl->iface_bmc[padapter->iface_id] = mac_id;
-}
-inline u8 rtw_iface_bcmc_id_get(_adapter *padapter)
-{
- struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
- struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
-
- return macid_ctl->iface_bmc[padapter->iface_id];
-}
-
inline void rtw_macid_map_clr(struct macid_bmp *map, u8 id)
{
if (id < 32)
@@ -3705,24 +3500,48 @@ inline bool rtw_macid_is_bmc(struct macid_ctl_t *macid_ctl, u8 id)
return rtw_macid_is_set(&macid_ctl->bmc, id);
}
-inline s8 rtw_macid_get_if_g(struct macid_ctl_t *macid_ctl, u8 id)
+inline u8 rtw_macid_get_iface_bmp(struct macid_ctl_t *macid_ctl, u8 id)
{
int i;
+ u8 iface_bmp = 0;
-#ifdef CONFIG_SHARED_BMC_MACID
- if (rtw_macid_is_bmc(macid_ctl, id)) {
- for (i = 0; i < CONFIG_IFACE_NUMBER; i++)
- if (macid_ctl->iface_bmc[i] == id)
- return i;
- return -1;
+ for (i = 0; i < CONFIG_IFACE_NUMBER; i++) {
+ if (rtw_macid_is_set(&macid_ctl->if_g[i], id))
+ iface_bmp |= BIT(i);
}
-#endif
+ return iface_bmp;
+}
+
+inline bool rtw_macid_is_iface_shared(struct macid_ctl_t *macid_ctl, u8 id)
+{
+ int i;
+ u8 iface_bmp = 0;
for (i = 0; i < CONFIG_IFACE_NUMBER; i++) {
- if (rtw_macid_is_set(&macid_ctl->if_g[i], id))
- return i;
+ if (rtw_macid_is_set(&macid_ctl->if_g[i], id)) {
+ if (iface_bmp)
+ return 1;
+ iface_bmp |= BIT(i);
+ }
}
- return -1;
+
+ return 0;
+}
+
+inline bool rtw_macid_is_iface_specific(struct macid_ctl_t *macid_ctl, u8 id, _adapter *adapter)
+{
+ int i;
+ u8 iface_bmp = 0;
+
+ for (i = 0; i < CONFIG_IFACE_NUMBER; i++) {
+ if (rtw_macid_is_set(&macid_ctl->if_g[i], id)) {
+ if (iface_bmp || i != adapter->iface_id)
+ return 0;
+ iface_bmp |= BIT(i);
+ }
+ }
+
+ return iface_bmp ? 1 : 0;
}
inline s8 rtw_macid_get_ch_g(struct macid_ctl_t *macid_ctl, u8 id)
@@ -3736,6 +3555,22 @@ inline s8 rtw_macid_get_ch_g(struct macid_ctl_t *macid_ctl, u8 id)
return -1;
}
+/*Record bc's mac-id and sec-cam-id*/
+inline void rtw_iface_bcmc_id_set(_adapter *padapter, u8 mac_id)
+{
+ struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+ struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
+
+ macid_ctl->iface_bmc[padapter->iface_id] = mac_id;
+}
+inline u8 rtw_iface_bcmc_id_get(_adapter *padapter)
+{
+ struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+ struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
+
+ return macid_ctl->iface_bmc[padapter->iface_id];
+}
+
void rtw_alloc_macid(_adapter *padapter, struct sta_info *psta)
{
int i;
@@ -3748,51 +3583,31 @@ void rtw_alloc_macid(_adapter *padapter, struct sta_info *psta)
u8 last_id = 0;
u8 is_bc_sta = _FALSE;
- if (_rtw_memcmp(psta->hwaddr, adapter_mac_addr(padapter), ETH_ALEN)) {
- psta->mac_id = macid_ctl->num;
+ if (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(padapter), ETH_ALEN)) {
+ psta->cmn.mac_id = macid_ctl->num;
return;
}
- if (_rtw_memcmp(psta->hwaddr, bc_addr, ETH_ALEN)) {
+ if (_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN)) {
is_bc_sta = _TRUE;
rtw_iface_bcmc_id_set(padapter, INVALID_SEC_MAC_CAM_ID); /*init default value*/
}
-#ifdef CONFIG_SHARED_BMC_MACID
if (is_bc_sta
-#ifdef CONFIG_CONCURRENT_MODE
- && (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) || check_fwstate(&padapter->mlmepriv, WIFI_NULL_STATE))
-#endif
- ) {
- /* use shared broadcast & multicast macid 1 for all ifaces which configure to station mode*/
- _enter_critical_bh(&macid_ctl->lock, &irqL);
- rtw_macid_map_set(used_map, 1);
- rtw_macid_map_set(&macid_ctl->bmc, 1);
- rtw_macid_map_set(&macid_ctl->if_g[padapter->iface_id], 1);
- macid_ctl->sta[1] = psta;
- /* TODO ch_g? */
- _exit_critical_bh(&macid_ctl->lock, &irqL);
- i = 1;
+ #ifdef CONFIG_CONCURRENT_MODE
+ && (MLME_IS_STA(padapter) || MLME_IS_NULL(padapter))
+ #endif
+ ) {
+ /* STA mode have no BMC data TX, shared with this macid */
+ /* When non-concurrent, only one BMC data TX is used, shared with this macid */
+ /* TODO: When concurrent, non-security BMC data TX may use this, but will not control by specific macid sleep */
+ i = RTW_DEFAULT_MGMT_MACID;
goto assigned;
}
-#endif
-
-#ifdef CONFIG_MCC_MODE
- if (MCC_EN(padapter)) {
- if (MLME_IS_AP(padapter) || MLME_IS_GO(padapter))
- /* GO/AP assign client macid from 8 */
- last_id = 8;
- }
-#endif /* CONFIG_MCC_MODE */
_enter_critical_bh(&macid_ctl->lock, &irqL);
for (i = last_id; i < macid_ctl->num; i++) {
-#ifdef CONFIG_SHARED_BMC_MACID
- if (i == 1)
- continue;
-#endif
-
#ifdef CONFIG_MCC_MODE
/* macid 0/1 reserve for mcc for mgnt queue macid */
if (MCC_EN(padapter)) {
@@ -3803,8 +3618,7 @@ void rtw_alloc_macid(_adapter *padapter, struct sta_info *psta)
}
#endif /* CONFIG_MCC_MODE */
- if (is_bc_sta) {/*for SoftAP's Broadcast sta-info*/
- /*TODO:non-security AP may allociated macid = 1*/
+ if (is_bc_sta) {
struct cam_ctl_t *cam_ctl = dvobj_to_sec_camctl(dvobj);
if ((!rtw_macid_is_used(macid_ctl, i)) && (!rtw_sec_camid_is_used(cam_ctl, i)))
@@ -3839,18 +3653,18 @@ void rtw_alloc_macid(_adapter *padapter, struct sta_info *psta)
_exit_critical_bh(&macid_ctl->lock, &irqL);
if (i >= macid_ctl->num) {
- psta->mac_id = macid_ctl->num;
- RTW_ERR(FUNC_ADPT_FMT" if%u, hwaddr:"MAC_FMT" no available macid\n"
- , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1, MAC_ARG(psta->hwaddr));
+ psta->cmn.mac_id = macid_ctl->num;
+ RTW_ERR(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" no available macid\n"
+ , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1, MAC_ARG(psta->cmn.mac_addr));
rtw_warn_on(1);
goto exit;
} else
goto assigned;
assigned:
- psta->mac_id = i;
- RTW_INFO(FUNC_ADPT_FMT" if%u, hwaddr:"MAC_FMT" macid:%u\n"
- , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1, MAC_ARG(psta->hwaddr), psta->mac_id);
+ psta->cmn.mac_id = i;
+ RTW_INFO(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" macid:%u\n"
+ , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1, MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id);
exit:
return;
@@ -3862,65 +3676,75 @@ void rtw_release_macid(_adapter *padapter, struct sta_info *psta)
u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
- u8 is_bc_sta = _FALSE;
-
- if (_rtw_memcmp(psta->hwaddr, adapter_mac_addr(padapter), ETH_ALEN))
- return;
-
- if (_rtw_memcmp(psta->hwaddr, bc_addr, ETH_ALEN))
- is_bc_sta = _TRUE;
+ u8 ifbmp;
+ int i;
-#ifdef CONFIG_SHARED_BMC_MACID
- if (is_bc_sta
-#ifdef CONFIG_CONCURRENT_MODE
- && (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) || check_fwstate(&padapter->mlmepriv, WIFI_NULL_STATE))
-#endif
- )
- return;
+ if (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(padapter), ETH_ALEN))
+ goto exit;
- if (psta->mac_id == 1) {
- RTW_ERR(FUNC_ADPT_FMT" if%u, hwaddr:"MAC_FMT" with macid:%u\n"
- , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1, MAC_ARG(psta->hwaddr), psta->mac_id);
- if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) || check_fwstate(&padapter->mlmepriv, WIFI_NULL_STATE))
- rtw_warn_on(1);
- return;
+ if (psta->cmn.mac_id >= macid_ctl->num) {
+ RTW_WARN(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" macid:%u not valid\n"
+ , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1
+ , MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id);
+ rtw_warn_on(1);
+ goto exit;
}
-#endif
+
+ if (psta->cmn.mac_id == RTW_DEFAULT_MGMT_MACID)
+ goto msg;
_enter_critical_bh(&macid_ctl->lock, &irqL);
- if (psta->mac_id < macid_ctl->num) {
- int i;
+ if (!rtw_macid_is_used(macid_ctl, psta->cmn.mac_id)) {
+ RTW_WARN(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" macid:%u not used\n"
+ , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1
+ , MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id);
+ _exit_critical_bh(&macid_ctl->lock, &irqL);
+ rtw_warn_on(1);
+ goto exit;
+ }
- if (!rtw_macid_is_used(macid_ctl, psta->mac_id)) {
- RTW_ERR(FUNC_ADPT_FMT" if%u, hwaddr:"MAC_FMT" macid:%u not used\n"
- , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1, MAC_ARG(psta->hwaddr), psta->mac_id);
- rtw_warn_on(1);
- }
+ ifbmp = rtw_macid_get_iface_bmp(macid_ctl, psta->cmn.mac_id);
+ if (!(ifbmp & BIT(padapter->iface_id))) {
+ RTW_WARN(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" macid:%u not used by self\n"
+ , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1
+ , MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id);
+ _exit_critical_bh(&macid_ctl->lock, &irqL);
+ rtw_warn_on(1);
+ goto exit;
+ }
- rtw_macid_map_clr(&macid_ctl->used, psta->mac_id);
- rtw_macid_map_clr(&macid_ctl->bmc, psta->mac_id);
+ if (_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN)) {
+ struct cam_ctl_t *cam_ctl = dvobj_to_sec_camctl(dvobj);
+ u8 id = rtw_iface_bcmc_id_get(padapter);
- if (is_bc_sta) {
- struct cam_ctl_t *cam_ctl = dvobj_to_sec_camctl(dvobj);
- u8 id = rtw_iface_bcmc_id_get(padapter);
+ if ((id != INVALID_SEC_MAC_CAM_ID) && (id < cam_ctl->num))
+ rtw_sec_cam_map_clr(&cam_ctl->used, id);
- if ((id != INVALID_SEC_MAC_CAM_ID) && (id < cam_ctl->num))
- rtw_sec_cam_map_clr(&cam_ctl->used, id);
+ rtw_iface_bcmc_id_set(padapter, INVALID_SEC_MAC_CAM_ID);
+ }
- rtw_iface_bcmc_id_set(padapter, INVALID_SEC_MAC_CAM_ID);
- }
+ rtw_macid_map_clr(&macid_ctl->if_g[padapter->iface_id], psta->cmn.mac_id);
- for (i = 0; i < CONFIG_IFACE_NUMBER; i++)
- rtw_macid_map_clr(&macid_ctl->if_g[i], psta->mac_id);
+ ifbmp &= ~BIT(padapter->iface_id);
+ if (!ifbmp) { /* only used by self */
+ rtw_macid_map_clr(&macid_ctl->used, psta->cmn.mac_id);
+ rtw_macid_map_clr(&macid_ctl->bmc, psta->cmn.mac_id);
for (i = 0; i < 2; i++)
- rtw_macid_map_clr(&macid_ctl->ch_g[i], psta->mac_id);
- macid_ctl->sta[psta->mac_id] = NULL;
+ rtw_macid_map_clr(&macid_ctl->ch_g[i], psta->cmn.mac_id);
+ macid_ctl->sta[psta->cmn.mac_id] = NULL;
}
_exit_critical_bh(&macid_ctl->lock, &irqL);
- psta->mac_id = macid_ctl->num;
+msg:
+ RTW_INFO(FUNC_ADPT_FMT" if%u, mac_addr:"MAC_FMT" macid:%u\n"
+ , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1
+ , MAC_ARG(psta->cmn.mac_addr), psta->cmn.mac_id
+ );
+
+exit:
+ psta->cmn.mac_id = macid_ctl->num;
}
/* For 8188E RA */
@@ -3957,8 +3781,79 @@ inline void rtw_macid_ctl_set_h2c_msr(struct macid_ctl_t *macid_ctl, u8 id, u8 h
RTW_INFO("macid:%u, h2c_msr:"H2C_MSR_FMT"\n", id, H2C_MSR_ARG(&macid_ctl->h2c_msr[id]));
}
+inline void rtw_macid_ctl_set_bw(struct macid_ctl_t *macid_ctl, u8 id, u8 bw)
+{
+ if (id >= macid_ctl->num) {
+ rtw_warn_on(1);
+ return;
+ }
+
+ macid_ctl->bw[id] = bw;
+ if (0)
+ RTW_INFO("macid:%u, bw:%s\n", id, ch_width_str(macid_ctl->bw[id]));
+}
+
+inline void rtw_macid_ctl_set_vht_en(struct macid_ctl_t *macid_ctl, u8 id, u8 en)
+{
+ if (id >= macid_ctl->num) {
+ rtw_warn_on(1);
+ return;
+ }
+
+ macid_ctl->vht_en[id] = en;
+ if (0)
+ RTW_INFO("macid:%u, vht_en:%u\n", id, macid_ctl->vht_en[id]);
+}
+
+inline void rtw_macid_ctl_set_rate_bmp0(struct macid_ctl_t *macid_ctl, u8 id, u32 bmp)
+{
+ if (id >= macid_ctl->num) {
+ rtw_warn_on(1);
+ return;
+ }
+
+ macid_ctl->rate_bmp0[id] = bmp;
+ if (0)
+ RTW_INFO("macid:%u, rate_bmp0:0x%08X\n", id, macid_ctl->rate_bmp0[id]);
+}
+
+inline void rtw_macid_ctl_set_rate_bmp1(struct macid_ctl_t *macid_ctl, u8 id, u32 bmp)
+{
+ if (id >= macid_ctl->num) {
+ rtw_warn_on(1);
+ return;
+ }
+
+ macid_ctl->rate_bmp1[id] = bmp;
+ if (0)
+ RTW_INFO("macid:%u, rate_bmp1:0x%08X\n", id, macid_ctl->rate_bmp1[id]);
+}
+
+inline void rtw_macid_ctl_init_sleep_reg(struct macid_ctl_t *macid_ctl, u16 m0, u16 m1, u16 m2, u16 m3)
+{
+ macid_ctl->reg_sleep_m0 = m0;
+#if (MACID_NUM_SW_LIMIT > 32)
+ macid_ctl->reg_sleep_m1 = m1;
+#endif
+#if (MACID_NUM_SW_LIMIT > 64)
+ macid_ctl->reg_sleep_m2 = m2;
+#endif
+#if (MACID_NUM_SW_LIMIT > 96)
+ macid_ctl->reg_sleep_m3 = m3;
+#endif
+}
+
inline void rtw_macid_ctl_init(struct macid_ctl_t *macid_ctl)
{
+ int i;
+ u8 id = RTW_DEFAULT_MGMT_MACID;
+
+ rtw_macid_map_set(&macid_ctl->used, id);
+ rtw_macid_map_set(&macid_ctl->bmc, id);
+ for (i = 0; i < CONFIG_IFACE_NUMBER; i++)
+ rtw_macid_map_set(&macid_ctl->if_g[i], id);
+ macid_ctl->sta[id] = NULL;
+
_rtw_spinlock_init(&macid_ctl->lock);
}
@@ -3967,6 +3862,87 @@ inline void rtw_macid_ctl_deinit(struct macid_ctl_t *macid_ctl)
_rtw_spinlock_free(&macid_ctl->lock);
}
+inline bool rtw_bmp_is_set(const u8 *bmp, u8 bmp_len, u8 id)
+{
+ if (id / 8 >= bmp_len)
+ return 0;
+
+ return bmp[id / 8] & BIT(id % 8);
+}
+
+inline void rtw_bmp_set(u8 *bmp, u8 bmp_len, u8 id)
+{
+ if (id / 8 < bmp_len)
+ bmp[id / 8] |= BIT(id % 8);
+}
+
+inline void rtw_bmp_clear(u8 *bmp, u8 bmp_len, u8 id)
+{
+ if (id / 8 < bmp_len)
+ bmp[id / 8] &= ~BIT(id % 8);
+}
+
+inline bool rtw_bmp_not_empty(const u8 *bmp, u8 bmp_len)
+{
+ int i;
+
+ for (i = 0; i < bmp_len; i++) {
+ if (bmp[i])
+ return 1;
+ }
+
+ return 0;
+}
+
+inline bool rtw_bmp_not_empty_exclude_bit0(const u8 *bmp, u8 bmp_len)
+{
+ int i;
+
+ for (i = 0; i < bmp_len; i++) {
+ if (i == 0) {
+ if (bmp[i] & 0xFE)
+ return 1;
+ } else {
+ if (bmp[i])
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_AP_MODE
+/* Check the id be set or not in map , if yes , return a none zero value*/
+bool rtw_tim_map_is_set(_adapter *padapter, const u8 *map, u8 id)
+{
+ return rtw_bmp_is_set(map, padapter->stapriv.aid_bmp_len, id);
+}
+
+/* Set the id into map array*/
+void rtw_tim_map_set(_adapter *padapter, u8 *map, u8 id)
+{
+ rtw_bmp_set(map, padapter->stapriv.aid_bmp_len, id);
+}
+
+/* Clear the id from map array*/
+void rtw_tim_map_clear(_adapter *padapter, u8 *map, u8 id)
+{
+ rtw_bmp_clear(map, padapter->stapriv.aid_bmp_len, id);
+}
+
+/* Check have anyone bit be set , if yes return true*/
+bool rtw_tim_map_anyone_be_set(_adapter *padapter, const u8 *map)
+{
+ return rtw_bmp_not_empty(map, padapter->stapriv.aid_bmp_len);
+}
+
+/* Check have anyone bit be set exclude bit0 , if yes return true*/
+bool rtw_tim_map_anyone_be_set_exclude_aid0(_adapter *padapter, const u8 *map)
+{
+ return rtw_bmp_not_empty_exclude_bit0(map, padapter->stapriv.aid_bmp_len);
+}
+#endif /* CONFIG_AP_MODE */
+
#if 0
unsigned int setup_beacon_frame(_adapter *padapter, unsigned char *beacon_frame)
{
@@ -3995,7 +3971,7 @@ unsigned int setup_beacon_frame(_adapter *padapter, unsigned char *beacon_frame)
_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN);
- SetFrameSubType(pframe, WIFI_BEACON);
+ set_frame_sub_type(pframe, WIFI_BEACON);
pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
len = sizeof(struct rtw_ieee80211_hdr_3addr);
@@ -4083,31 +4059,38 @@ _adapter *dvobj_get_port0_adapter(struct dvobj_priv *dvobj)
return port0_iface;
}
-#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
-void rtw_get_current_ip_address(PADAPTER padapter, u8 *pcurrentip)
+_adapter *dvobj_get_unregisterd_adapter(struct dvobj_priv *dvobj)
{
- struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
- struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
- struct in_device *my_ip_ptr = padapter->pnetdev->ip_ptr;
- u8 ipaddress[4];
-
- if ((pmlmeinfo->state & WIFI_FW_LINKING_STATE) ||
- pmlmeinfo->state & WIFI_FW_AP_STATE) {
- if (my_ip_ptr != NULL) {
- struct in_ifaddr *my_ifa_list = my_ip_ptr->ifa_list ;
- if (my_ifa_list != NULL) {
- ipaddress[0] = my_ifa_list->ifa_address & 0xFF;
- ipaddress[1] = (my_ifa_list->ifa_address >> 8) & 0xFF;
- ipaddress[2] = (my_ifa_list->ifa_address >> 16) & 0xFF;
- ipaddress[3] = my_ifa_list->ifa_address >> 24;
- RTW_INFO("%s: %d.%d.%d.%d ==========\n", __func__,
- ipaddress[0], ipaddress[1], ipaddress[2], ipaddress[3]);
- _rtw_memcpy(pcurrentip, ipaddress, 4);
- }
- }
+ _adapter *adapter = NULL;
+ int i;
+
+ for (i = 0; i < dvobj->iface_nums; i++) {
+ if (dvobj->padapters[i]->registered == 0)
+ break;
}
+
+ if (i < dvobj->iface_nums)
+ adapter = dvobj->padapters[i];
+
+ return adapter;
}
-#endif
+
+_adapter *dvobj_get_adapter_by_addr(struct dvobj_priv *dvobj, u8 *addr)
+{
+ _adapter *adapter = NULL;
+ int i;
+
+ for (i = 0; i < dvobj->iface_nums; i++) {
+ if (_rtw_memcmp(dvobj->padapters[i]->mac_addr, addr, ETH_ALEN) == _TRUE)
+ break;
+ }
+
+ if (i < dvobj->iface_nums)
+ adapter = dvobj->padapters[i];
+
+ return adapter;
+}
+
#ifdef CONFIG_WOWLAN
bool rtw_wowlan_parser_pattern_cmd(u8 *input, char *pattern,
int *pattern_len, char *bit_mask)
@@ -4185,23 +4168,42 @@ bool rtw_check_pattern_valid(u8 *input, u8 len)
exit:
return res;
}
+void rtw_wow_pattern_sw_reset(_adapter *adapter)
+{
+ int i;
+ struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(adapter);
+
+ if (pwrctrlpriv->default_patterns_en == _TRUE)
+ pwrctrlpriv->wowlan_pattern_idx = DEFAULT_PATTERN_NUM;
+ else
+ pwrctrlpriv->wowlan_pattern_idx = 0;
+
+ for (i = 0 ; i < MAX_WKFM_CAM_NUM; i++) {
+ _rtw_memset(pwrctrlpriv->patterns[i].content, '\0', sizeof(pwrctrlpriv->patterns[i].content));
+ _rtw_memset(pwrctrlpriv->patterns[i].mask, '\0', sizeof(pwrctrlpriv->patterns[i].mask));
+ pwrctrlpriv->patterns[i].len = 0;
+ }
+}
u8 rtw_set_default_pattern(_adapter *adapter)
{
struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
- struct registry_priv *pregistrypriv = &adapter->registrypriv;
+ struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
+ struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
u8 index = 0;
- u8 currentip[4];
u8 multicast_addr[3] = {0x01, 0x00, 0x5e};
u8 multicast_ip[4] = {0xe0, 0x28, 0x28, 0x2a};
+
u8 unicast_mask[5] = {0x3f, 0x70, 0x80, 0xc0, 0x03};
+ u8 icmpv6_mask[7] = {0x00, 0x70, 0x10, 0x00, 0xc0, 0xc0, 0x3f};
u8 multicast_mask[5] = {0x07, 0x70, 0x80, 0xc0, 0x03};
+
u8 ip_protocol[3] = {0x08, 0x00, 0x45};
- u8 icmp_protocol[1] = {0x01};
- u8 tcp_protocol[1] = {0x06};
- u8 udp_protocol[1] = {0x11};
+ u8 ipv6_protocol[3] = {0x86, 0xdd, 0x60};
- if (pregistrypriv->default_patterns_en == _FALSE)
+ u8 *target = NULL;
+
+ if (pwrpriv->default_patterns_en == _FALSE)
return 0;
for (index = 0 ; index < DEFAULT_PATTERN_NUM ; index++) {
@@ -4212,253 +4214,109 @@ u8 rtw_set_default_pattern(_adapter *adapter)
pwrpriv->patterns[index].len = 0;
}
- rtw_get_current_ip_address(adapter, currentip);
-
/*TCP/ICMP unicast*/
for (index = 0 ; index < DEFAULT_PATTERN_NUM ; index++) {
switch (index) {
case 0:
- _rtw_memcpy(pwrpriv->patterns[index].content,
- adapter_mac_addr(adapter),
+ target = pwrpriv->patterns[index].content;
+ _rtw_memcpy(target, adapter_mac_addr(adapter),
ETH_ALEN);
- _rtw_memcpy(pwrpriv->patterns[index].content + ETH_TYPE_OFFSET,
- &ip_protocol, sizeof(ip_protocol));
- _rtw_memcpy(pwrpriv->patterns[index].content + PROTOCOL_OFFSET,
- &tcp_protocol, sizeof(tcp_protocol));
- _rtw_memcpy(pwrpriv->patterns[index].content + IP_OFFSET,
- ¤tip, sizeof(currentip));
- _rtw_memcpy(pwrpriv->patterns[index].mask,
- &unicast_mask, sizeof(unicast_mask));
- pwrpriv->patterns[index].len = IP_OFFSET + sizeof(currentip);
- break;
- case 1:
- _rtw_memcpy(pwrpriv->patterns[index].content,
- adapter_mac_addr(adapter),
- ETH_ALEN);
- _rtw_memcpy(pwrpriv->patterns[index].content + ETH_TYPE_OFFSET,
- &ip_protocol, sizeof(ip_protocol));
- _rtw_memcpy(pwrpriv->patterns[index].content + PROTOCOL_OFFSET,
- &icmp_protocol, sizeof(icmp_protocol));
- _rtw_memcpy(pwrpriv->patterns[index].content + IP_OFFSET,
- ¤tip, sizeof(currentip));
- _rtw_memcpy(pwrpriv->patterns[index].mask,
- &unicast_mask, sizeof(unicast_mask));
- pwrpriv->patterns[index].len = IP_OFFSET + sizeof(currentip);
- break;
- case 2:
- _rtw_memcpy(pwrpriv->patterns[index].content, &multicast_addr,
- sizeof(multicast_addr));
- _rtw_memcpy(pwrpriv->patterns[index].content + ETH_TYPE_OFFSET,
- &ip_protocol, sizeof(ip_protocol));
- _rtw_memcpy(pwrpriv->patterns[index].content + PROTOCOL_OFFSET,
- &udp_protocol, sizeof(udp_protocol));
- _rtw_memcpy(pwrpriv->patterns[index].content + IP_OFFSET,
- &multicast_ip, sizeof(multicast_ip));
- _rtw_memcpy(pwrpriv->patterns[index].mask,
- &multicast_mask, sizeof(multicast_mask));
- pwrpriv->patterns[index].len =
- IP_OFFSET + sizeof(multicast_ip);
- break;
- }
- }
-
- return index;
-}
-
-bool rtw_read_from_frame_mask(_adapter *adapter, u8 idx)
-{
- u32 data_l = 0, data_h = 0, rx_dma_buff_sz = 0, page_sz = 0;
- u16 offset, rx_buf_ptr = 0;
- u16 cam_start_offset = 0;
- u16 ctrl_l = 0, ctrl_h = 0;
- u8 count = 0, tmp = 0;
- int i = 0;
- bool res = _TRUE;
-
- if (idx > MAX_WKFM_NUM) {
- RTW_INFO("[Error]: %s, pattern index is out of range\n",
- __func__);
- return _FALSE;
- }
-
- rtw_hal_get_def_var(adapter, HAL_DEF_RX_DMA_SZ_WOW,
- (u8 *)&rx_dma_buff_sz);
-
- if (rx_dma_buff_sz == 0) {
- RTW_INFO("[Error]: %s, rx_dma_buff_sz is 0!!\n", __func__);
- return _FALSE;
- }
-
- rtw_hal_get_def_var(adapter, HAL_DEF_RX_PAGE_SIZE, (u8 *)&page_sz);
-
- if (page_sz == 0) {
- RTW_INFO("[Error]: %s, page_sz is 0!!\n", __func__);
- return _FALSE;
- }
-
- offset = (u16)PageNum(rx_dma_buff_sz, page_sz);
- cam_start_offset = offset * page_sz;
- ctrl_l = 0x0;
- ctrl_h = 0x0;
+ target += ETH_TYPE_OFFSET;
+ _rtw_memcpy(target, &ip_protocol,
+ sizeof(ip_protocol));
- /* Enable RX packet buffer access */
- rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT);
+ /* TCP */
+ target += (PROTOCOL_OFFSET - ETH_TYPE_OFFSET);
+ _rtw_memset(target, 0x06, 1);
- /* Read the WKFM CAM */
- for (i = 0; i < (WKFMCAM_ADDR_NUM / 2); i++) {
- /*
- * Set Rx packet buffer offset.
- * RxBufer pointer increases 1, we can access 8 bytes in Rx packet buffer.
- * CAM start offset (unit: 1 byte) = Index*WKFMCAM_SIZE
- * RxBufer pointer addr = (CAM start offset + per entry offset of a WKFMCAM)/8
- * * Index: The index of the wake up frame mask
- * * WKFMCAM_SIZE: the total size of one WKFM CAM
- * * per entry offset of a WKFM CAM: Addr i * 4 bytes
- */
- rx_buf_ptr =
- (cam_start_offset + idx * WKFMCAM_SIZE + i * 8) >> 3;
- rtw_write16(adapter, REG_PKTBUF_DBG_CTRL, rx_buf_ptr);
-
- rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_l);
- data_l = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_L);
- data_h = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H);
-
- RTW_INFO("[%d]: %08x %08x\n", i, data_h, data_l);
-
- count = 0;
-
- do {
- tmp = rtw_read8(adapter, REG_RXPKTBUF_CTRL);
- rtw_udelay_os(2);
- count++;
- } while (!tmp && count < 100);
-
- if (count >= 100) {
- RTW_INFO("%s count:%d\n", __func__, count);
- res = _FALSE;
- }
- }
+ target += (IP_OFFSET - PROTOCOL_OFFSET);
- /* Disable RX packet buffer access */
- rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL,
- DISABLE_TRXPKT_BUF_ACCESS);
- return res;
-}
+ _rtw_memcpy(target, pmlmeinfo->ip_addr,
+ RTW_IP_ADDR_LEN);
-bool rtw_write_to_frame_mask(_adapter *adapter, u8 idx,
- struct rtl_wow_pattern *context)
-{
- u32 data = 0, rx_dma_buff_sz = 0, page_sz = 0;
- u16 offset, rx_buf_ptr = 0;
- u16 cam_start_offset = 0;
- u16 ctrl_l = 0, ctrl_h = 0;
- u8 count = 0, tmp = 0;
- int res = 0, i = 0;
+ _rtw_memcpy(pwrpriv->patterns[index].mask,
+ &unicast_mask, sizeof(unicast_mask));
- if (idx > MAX_WKFM_NUM) {
- RTW_INFO("[Error]: %s, pattern index is out of range\n",
- __func__);
- return _FALSE;
- }
+ pwrpriv->patterns[index].len =
+ IP_OFFSET + RTW_IP_ADDR_LEN;
+ break;
+ case 1:
+ target = pwrpriv->patterns[index].content;
+ _rtw_memcpy(target, adapter_mac_addr(adapter),
+ ETH_ALEN);
- rtw_hal_get_def_var(adapter, HAL_DEF_RX_DMA_SZ_WOW,
- (u8 *)&rx_dma_buff_sz);
+ target += ETH_TYPE_OFFSET;
+ _rtw_memcpy(target, &ip_protocol, sizeof(ip_protocol));
- if (rx_dma_buff_sz == 0) {
- RTW_INFO("[Error]: %s, rx_dma_buff_sz is 0!!\n", __func__);
- return _FALSE;
- }
+ /* ICMP */
+ target += (PROTOCOL_OFFSET - ETH_TYPE_OFFSET);
+ _rtw_memset(target, 0x01, 1);
- rtw_hal_get_def_var(adapter, HAL_DEF_RX_PAGE_SIZE, (u8 *)&page_sz);
+ target += (IP_OFFSET - PROTOCOL_OFFSET);
+ _rtw_memcpy(target, pmlmeinfo->ip_addr,
+ RTW_IP_ADDR_LEN);
- if (page_sz == 0) {
- RTW_INFO("[Error]: %s, page_sz is 0!!\n", __func__);
- return _FALSE;
- }
+ _rtw_memcpy(pwrpriv->patterns[index].mask,
+ &unicast_mask, sizeof(unicast_mask));
+ pwrpriv->patterns[index].len =
- offset = (u16)PageNum(rx_dma_buff_sz, page_sz);
+ IP_OFFSET + RTW_IP_ADDR_LEN;
+ break;
+#ifdef CONFIG_IPV6
+ case 2:
+ if (pwrpriv->wowlan_ns_offload_en == _TRUE) {
+ target = pwrpriv->patterns[index].content;
+ target += ETH_TYPE_OFFSET;
+
+ _rtw_memcpy(target, &ipv6_protocol,
+ sizeof(ipv6_protocol));
+
+ /* ICMPv6 */
+ target += (IPv6_PROTOCOL_OFFSET -
+ ETH_TYPE_OFFSET);
+ _rtw_memset(target, 0x3a, 1);
+
+ target += (IPv6_OFFSET - IPv6_PROTOCOL_OFFSET);
+ _rtw_memcpy(target, pmlmeinfo->ip6_addr,
+ RTW_IPv6_ADDR_LEN);
+
+ _rtw_memcpy(pwrpriv->patterns[index].mask,
+ &icmpv6_mask, sizeof(icmpv6_mask));
+ pwrpriv->patterns[index].len =
+ IPv6_OFFSET + RTW_IPv6_ADDR_LEN;
+ }
+ break;
+#endif /*CONFIG_IPV6*/
+ case 3:
+ target = pwrpriv->patterns[index].content;
+ _rtw_memcpy(target, &multicast_addr,
+ sizeof(multicast_addr));
- cam_start_offset = offset * page_sz;
+ target += ETH_TYPE_OFFSET;
+ _rtw_memcpy(target, &ip_protocol, sizeof(ip_protocol));
- if (IS_HARDWARE_TYPE_8188E(adapter)) {
- ctrl_l = 0x0001;
- ctrl_h = 0x0001;
- } else {
- ctrl_l = 0x0f01;
- ctrl_h = 0xf001;
- }
+ /* UDP */
+ target += (PROTOCOL_OFFSET - ETH_TYPE_OFFSET);
+ _rtw_memset(target, 0x11, 1);
- /* Enable RX packet buffer access */
- rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT);
+ target += (IP_OFFSET - PROTOCOL_OFFSET);
+ _rtw_memcpy(target, &multicast_ip,
+ sizeof(multicast_ip));
- /* Write the WKFM CAM */
- for (i = 0; i < WKFMCAM_ADDR_NUM; i++) {
- /*
- * Set Rx packet buffer offset.
- * RxBufer pointer increases 1, we can access 8 bytes in Rx packet buffer.
- * CAM start offset (unit: 1 byte) = Index*WKFMCAM_SIZE
- * RxBufer pointer addr = (CAM start offset + per entry offset of a WKFMCAM)/8
- * * Index: The index of the wake up frame mask
- * * WKFMCAM_SIZE: the total size of one WKFM CAM
- * * per entry offset of a WKFM CAM: Addr i * 4 bytes
- */
- rx_buf_ptr =
- (cam_start_offset + idx * WKFMCAM_SIZE + i * 4) >> 3;
- rtw_write16(adapter, REG_PKTBUF_DBG_CTRL, rx_buf_ptr);
+ _rtw_memcpy(pwrpriv->patterns[index].mask,
+ &multicast_mask, sizeof(multicast_mask));
- if (i == 0) {
- if (context->type == PATTERN_VALID)
- data = BIT(31);
- else if (context->type == PATTERN_BROADCAST)
- data = BIT(31) | BIT(26);
- else if (context->type == PATTERN_MULTICAST)
- data = BIT(31) | BIT(25);
- else if (context->type == PATTERN_UNICAST)
- data = BIT(31) | BIT(24);
-
- if (context->crc != 0)
- data |= context->crc;
-
- rtw_write32(adapter, REG_PKTBUF_DBG_DATA_L, data);
- rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_l);
- } else if (i == 1) {
- data = 0;
- rtw_write32(adapter, REG_PKTBUF_DBG_DATA_H, data);
- rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_h);
- } else if (i == 2 || i == 4) {
- data = context->mask[i - 2];
- rtw_write32(adapter, REG_PKTBUF_DBG_DATA_L, data);
- /* write to RX packet buffer*/
- rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_l);
- } else if (i == 3 || i == 5) {
- data = context->mask[i - 2];
- rtw_write32(adapter, REG_PKTBUF_DBG_DATA_H, data);
- /* write to RX packet buffer*/
- rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_h);
+ pwrpriv->patterns[index].len =
+ IP_OFFSET + sizeof(multicast_ip);
+ break;
+ default:
+ break;
}
-
- count = 0;
- do {
- tmp = rtw_read8(adapter, REG_RXPKTBUF_CTRL);
- rtw_udelay_os(2);
- count++;
- } while (tmp && count < 100);
-
- if (count >= 100)
- res = _FALSE;
- else
- res = _TRUE;
}
-
- /* Disable RX packet buffer access */
- rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL,
- DISABLE_TRXPKT_BUF_ACCESS);
-
- return res;
+ return index;
}
-
void rtw_dump_priv_pattern(_adapter *adapter, u8 idx)
{
struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
@@ -4499,20 +4357,13 @@ void rtw_dump_priv_pattern(_adapter *adapter, u8 idx)
RTW_INFO("%s: len: %d\n", __func__, pwrctl->patterns[idx].len);
}
-void rtw_clean_pattern(_adapter *adapter)
+void rtw_wow_pattern_sw_dump(_adapter *adapter)
{
- struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
- struct rtl_wow_pattern zero_pattern;
- int i = 0;
-
- _rtw_memset(&zero_pattern, 0, sizeof(struct rtl_wow_pattern));
-
- zero_pattern.type = PATTERN_INVALID;
-
- for (i = 0; i < MAX_WKFM_NUM; i++)
- rtw_write_to_frame_mask(adapter, i, &zero_pattern);
+ int i;
- rtw_write8(adapter, REG_WKFMCAM_NUM, 0);
+ RTW_INFO("********[RTK priv-patterns]*********\n");
+ for (i = 0 ; i < MAX_WKFM_CAM_NUM; i++)
+ rtw_dump_priv_pattern(adapter, i);
}
void rtw_get_sec_iv(PADAPTER padapter, u8 *pcur_dot11txpn, u8 *StaAddr)
@@ -4529,9 +4380,10 @@ void rtw_get_sec_iv(PADAPTER padapter, u8 *pcur_dot11txpn, u8 *StaAddr)
StaAddr[3], StaAddr[4], StaAddr[5]);
if (psta) {
- if (psecpriv->dot11PrivacyAlgrthm != _NO_PRIVACY_ && psta->dot11txpn.val > 0)
- psta->dot11txpn.val--;
- AES_IV(pcur_dot11txpn, psta->dot11txpn, 0);
+ if (psecpriv->dot11PrivacyAlgrthm == _AES_)
+ AES_IV(pcur_dot11txpn, psta->dot11txpn, 0);
+ else if (psecpriv->dot11PrivacyAlgrthm == _TKIP_)
+ TKIP_IV(pcur_dot11txpn, psta->dot11txpn, 0);
RTW_INFO("%s(): CurrentIV: %02x %02x %02x %02x %02x %02x %02x %02x\n"
, __func__, pcur_dot11txpn[0], pcur_dot11txpn[1],
@@ -4539,28 +4391,6 @@ void rtw_get_sec_iv(PADAPTER padapter, u8 *pcur_dot11txpn, u8 *StaAddr)
pcur_dot11txpn[5], pcur_dot11txpn[6], pcur_dot11txpn[7]);
}
}
-void rtw_set_sec_pn(PADAPTER padapter)
-{
- struct sta_info *psta;
- struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
- struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
- struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
- struct security_priv *psecpriv = &padapter->securitypriv;
-
- psta = rtw_get_stainfo(&padapter->stapriv,
- get_my_bssid(&pmlmeinfo->network));
-
- if (psta) {
- if (pwrpriv->wowlan_fw_iv > psta->dot11txpn.val) {
- if (psecpriv->dot11PrivacyAlgrthm != _NO_PRIVACY_)
- psta->dot11txpn.val = pwrpriv->wowlan_fw_iv + 2;
- } else {
- RTW_INFO("%s(): FW IV is smaller than driver\n", __func__);
- psta->dot11txpn.val += 2;
- }
- RTW_INFO("%s: dot11txpn: 0x%016llx\n", __func__ , psta->dot11txpn.val);
- }
-}
#endif /* CONFIG_WOWLAN */
#ifdef CONFIG_PNO_SUPPORT
@@ -4681,7 +4511,9 @@ int rtw_dev_nlo_info_set(struct pno_nlo_info *nlo_info, pno_ssid_t *ssid,
int i = 0;
struct file *fp;
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0))
mm_segment_t fs;
+#endif
loff_t pos = 0;
u8 *source = NULL;
long len = 0;
@@ -4704,7 +4536,7 @@ int rtw_dev_nlo_info_set(struct pno_nlo_info *nlo_info, pno_ssid_t *ssid,
}
/* cipher array */
- fp = filp_open("/home/timlee/wpa_kk/wpa.conf", O_RDONLY, 0644);
+ fp = filp_open("/data/misc/wifi/wpa_supplicant.conf", O_RDONLY, 0644);
if (IS_ERR(fp)) {
RTW_INFO("Error, wpa_supplicant.conf doesn't exist.\n");
RTW_INFO("Error, cipher array using default value.\n");
@@ -4718,8 +4550,10 @@ int rtw_dev_nlo_info_set(struct pno_nlo_info *nlo_info, pno_ssid_t *ssid,
return 0;
}
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0))
fs = get_fs();
set_fs(KERNEL_DS);
+#endif
source = rtw_zmalloc(2048);
@@ -4729,7 +4563,9 @@ int rtw_dev_nlo_info_set(struct pno_nlo_info *nlo_info, pno_ssid_t *ssid,
rtw_mfree(source, 2048);
}
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0))
set_fs(fs);
+#endif
filp_close(fp, NULL);
RTW_INFO("-%s-\n", __func__);
@@ -4774,7 +4610,7 @@ int rtw_dev_scan_info_set(_adapter *padapter, pno_ssid_t *ssid,
scan_info->ssid_channel_info[i].timeout = 100;
scan_info->ssid_channel_info[i].tx_power =
- PHY_GetTxPowerIndex(padapter, 0, 0x02, bw_mode, i + 1);
+ phy_get_tx_power_index(padapter, 0, 0x02, bw_mode, i + 1);
scan_info->ssid_channel_info[i].channel = i + 1;
}
@@ -4819,7 +4655,7 @@ int rtw_dev_pno_set(struct net_device *net, pno_ssid_t *ssid, int num,
goto failing;
}
- pwrctl->pno_in_resume = _FALSE;
+ pwrctl->wowlan_in_resume = _FALSE;
pwrctl->pno_inited = _TRUE;
/* NLO Info */
diff --git a/core/rtw_xmit.c b/core/rtw_xmit.c
index cb91217..b480319 100644
--- a/core/rtw_xmit.c
+++ b/core/rtw_xmit.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,15 +11,11 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#define _RTW_XMIT_C_
#include
+#include
#if defined(PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
#error "Shall be Linux or Windows, but not both!\n"
@@ -31,18 +27,15 @@ static u8 RFC1042_OUI[P80211_OUI_LEN] = { 0x00, 0x00, 0x00 };
static void _init_txservq(struct tx_servq *ptxservq)
{
- _func_enter_;
_rtw_init_listhead(&ptxservq->tx_pending);
_rtw_init_queue(&ptxservq->sta_pending);
ptxservq->qcnt = 0;
- _func_exit_;
}
void _rtw_init_sta_xmit_priv(struct sta_xmit_priv *psta_xmitpriv)
{
- _func_enter_;
_rtw_memset((unsigned char *)psta_xmitpriv, 0, sizeof(struct sta_xmit_priv));
@@ -58,10 +51,24 @@ void _rtw_init_sta_xmit_priv(struct sta_xmit_priv *psta_xmitpriv)
_rtw_init_listhead(&psta_xmitpriv->legacy_dz);
_rtw_init_listhead(&psta_xmitpriv->apsd);
- _func_exit_;
}
+void rtw_init_xmit_block(_adapter *padapter)
+{
+ struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+
+ _rtw_spinlock_init(&dvobj->xmit_block_lock);
+ dvobj->xmit_block = XMIT_BLOCK_NONE;
+
+}
+void rtw_free_xmit_block(_adapter *padapter)
+{
+ struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+
+ _rtw_spinlock_free(&dvobj->xmit_block_lock);
+}
+
s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter)
{
int i;
@@ -69,7 +76,6 @@ s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter)
struct xmit_frame *pxframe;
sint res = _SUCCESS;
- _func_enter_;
/* We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). */
/* _rtw_memset((unsigned char *)pxmitpriv, 0, sizeof(struct xmit_priv)); */
@@ -77,7 +83,6 @@ s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter)
_rtw_spinlock_init(&pxmitpriv->lock);
_rtw_spinlock_init(&pxmitpriv->lock_sctx);
_rtw_init_sema(&pxmitpriv->xmit_sema, 0);
- _rtw_init_sema(&pxmitpriv->terminate_xmitthread_sema, 0);
/*
Please insert all the queue initializaiton using _rtw_init_queue below
@@ -109,7 +114,6 @@ s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter)
if (pxmitpriv->pallocated_frame_buf == NULL) {
pxmitpriv->pxmit_frame_buf = NULL;
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("alloc xmit_frame fail!\n"));
res = _FAIL;
goto exit;
}
@@ -147,7 +151,6 @@ s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter)
pxmitpriv->pallocated_xmitbuf = rtw_zvmalloc(NR_XMITBUFF * sizeof(struct xmit_buf) + 4);
if (pxmitpriv->pallocated_xmitbuf == NULL) {
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("alloc xmit_buf fail!\n"));
res = _FAIL;
goto exit;
}
@@ -201,7 +204,6 @@ s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter)
if (pxmitpriv->xframe_ext_alloc_addr == NULL) {
pxmitpriv->xframe_ext = NULL;
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("alloc xframe_ext fail!\n"));
res = _FAIL;
goto exit;
}
@@ -233,7 +235,6 @@ s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter)
pxmitpriv->pallocated_xmit_extbuf = rtw_zvmalloc(NR_XMIT_EXTBUFF * sizeof(struct xmit_buf) + 4);
if (pxmitpriv->pallocated_xmit_extbuf == NULL) {
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("alloc xmit_extbuf fail!\n"));
res = _FAIL;
goto exit;
}
@@ -322,17 +323,21 @@ s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter)
rtw_sctx_init(&pxmitpriv->ack_tx_ops, 0);
#endif
-#ifdef TX_AMSDU
- _init_timer(&(pxmitpriv->amsdu_vo_timer), padapter->pnetdev, rtw_amsdu_vo_timeout_handler, padapter);
+#ifdef CONFIG_TX_AMSDU
+ rtw_init_timer(&(pxmitpriv->amsdu_vo_timer), padapter,
+ rtw_amsdu_vo_timeout_handler, padapter);
pxmitpriv->amsdu_vo_timeout = RTW_AMSDU_TIMER_UNSET;
- _init_timer(&(pxmitpriv->amsdu_vi_timer), padapter->pnetdev, rtw_amsdu_vi_timeout_handler, padapter);
+ rtw_init_timer(&(pxmitpriv->amsdu_vi_timer), padapter,
+ rtw_amsdu_vi_timeout_handler, padapter);
pxmitpriv->amsdu_vi_timeout = RTW_AMSDU_TIMER_UNSET;
- _init_timer(&(pxmitpriv->amsdu_be_timer), padapter->pnetdev, rtw_amsdu_be_timeout_handler, padapter);
+ rtw_init_timer(&(pxmitpriv->amsdu_be_timer), padapter,
+ rtw_amsdu_be_timeout_handler, padapter);
pxmitpriv->amsdu_be_timeout = RTW_AMSDU_TIMER_UNSET;
- _init_timer(&(pxmitpriv->amsdu_bk_timer), padapter->pnetdev, rtw_amsdu_bk_timeout_handler, padapter);
+ rtw_init_timer(&(pxmitpriv->amsdu_bk_timer), padapter,
+ rtw_amsdu_bk_timeout_handler, padapter);
pxmitpriv->amsdu_bk_timeout = RTW_AMSDU_TIMER_UNSET;
pxmitpriv->amsdu_debug_set_timer = 0;
@@ -340,11 +345,14 @@ s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter)
pxmitpriv->amsdu_debug_coalesce_one = 0;
pxmitpriv->amsdu_debug_coalesce_two = 0;
#endif
-
+#ifdef DBG_TXBD_DESC_DUMP
+ pxmitpriv->dump_txbd_desc = 0;
+#endif
+ rtw_init_xmit_block(padapter);
rtw_hal_init_xmit_priv(padapter);
+
exit:
- _func_exit_;
return res;
}
@@ -354,7 +362,6 @@ void rtw_mfree_xmit_priv_lock(struct xmit_priv *pxmitpriv)
{
_rtw_spinlock_free(&pxmitpriv->lock);
_rtw_free_sema(&pxmitpriv->xmit_sema);
- _rtw_free_sema(&pxmitpriv->terminate_xmitthread_sema);
_rtw_spinlock_free(&pxmitpriv->be_pending.lock);
_rtw_spinlock_free(&pxmitpriv->bk_pending.lock);
@@ -378,7 +385,6 @@ void _rtw_free_xmit_priv(struct xmit_priv *pxmitpriv)
struct xmit_frame *pxmitframe = (struct xmit_frame *) pxmitpriv->pxmit_frame_buf;
struct xmit_buf *pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmitbuf;
- _func_enter_;
rtw_hal_free_xmit_priv(padapter);
@@ -441,14 +447,288 @@ void _rtw_free_xmit_priv(struct xmit_priv *pxmitpriv)
#ifdef CONFIG_XMIT_ACK
_rtw_mutex_free(&pxmitpriv->ack_tx_mutex);
#endif
-
+ rtw_free_xmit_block(padapter);
out:
+ return;
+}
+
+u8 rtw_get_tx_bw_mode(_adapter *adapter, struct sta_info *sta)
+{
+ u8 bw;
+
+ bw = sta->cmn.bw_mode;
+ if (MLME_STATE(adapter) & WIFI_ASOC_STATE) {
+ if (adapter->mlmeextpriv.cur_channel <= 14)
+ bw = rtw_min(bw, ADAPTER_TX_BW_2G(adapter));
+ else
+ bw = rtw_min(bw, ADAPTER_TX_BW_5G(adapter));
+ }
+
+ return bw;
+}
+
+void rtw_get_adapter_tx_rate_bmp_by_bw(_adapter *adapter, u8 bw, u16 *r_bmp_cck_ofdm, u32 *r_bmp_ht, u32 *r_bmp_vht)
+{
+ struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+ struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
+ struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
+ u8 fix_bw = 0xFF;
+ u16 bmp_cck_ofdm = 0;
+ u32 bmp_ht = 0;
+ u32 bmp_vht = 0;
+ int i;
+
+ if (adapter->fix_rate != 0xFF && adapter->fix_bw != 0xFF)
+ fix_bw = adapter->fix_bw;
+
+ /* TODO: adapter->fix_rate */
+
+ for (i = 0; i < macid_ctl->num; i++) {
+ if (!rtw_macid_is_used(macid_ctl, i))
+ continue;
+ if (!rtw_macid_is_iface_specific(macid_ctl, i, adapter))
+ continue;
+
+ if (bw == CHANNEL_WIDTH_20) /* CCK, OFDM always 20MHz */
+ bmp_cck_ofdm |= macid_ctl->rate_bmp0[i] & 0x00000FFF;
+
+ /* bypass mismatch bandwidth for HT, VHT */
+ if ((fix_bw != 0xFF && fix_bw != bw) || (fix_bw == 0xFF && macid_ctl->bw[i] != bw))
+ continue;
+
+ if (macid_ctl->vht_en[i])
+ bmp_vht |= (macid_ctl->rate_bmp0[i] >> 12) | (macid_ctl->rate_bmp1[i] << 20);
+ else
+ bmp_ht |= (macid_ctl->rate_bmp0[i] >> 12) | (macid_ctl->rate_bmp1[i] << 20);
+ }
+
+ /* TODO: mlmeext->tx_rate*/
+
+exit:
+ if (r_bmp_cck_ofdm)
+ *r_bmp_cck_ofdm = bmp_cck_ofdm;
+ if (r_bmp_ht)
+ *r_bmp_ht = bmp_ht;
+ if (r_bmp_vht)
+ *r_bmp_vht = bmp_vht;
+}
+
+void rtw_get_shared_macid_tx_rate_bmp_by_bw(struct dvobj_priv *dvobj, u8 bw, u16 *r_bmp_cck_ofdm, u32 *r_bmp_ht, u32 *r_bmp_vht)
+{
+ struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
+ u16 bmp_cck_ofdm = 0;
+ u32 bmp_ht = 0;
+ u32 bmp_vht = 0;
+ int i;
+
+ for (i = 0; i < macid_ctl->num; i++) {
+ if (!rtw_macid_is_used(macid_ctl, i))
+ continue;
+ if (!rtw_macid_is_iface_shared(macid_ctl, i))
+ continue;
+
+ if (bw == CHANNEL_WIDTH_20) /* CCK, OFDM always 20MHz */
+ bmp_cck_ofdm |= macid_ctl->rate_bmp0[i] & 0x00000FFF;
+
+ /* bypass mismatch bandwidth for HT, VHT */
+ if (macid_ctl->bw[i] != bw)
+ continue;
+
+ if (macid_ctl->vht_en[i])
+ bmp_vht |= (macid_ctl->rate_bmp0[i] >> 12) | (macid_ctl->rate_bmp1[i] << 20);
+ else
+ bmp_ht |= (macid_ctl->rate_bmp0[i] >> 12) | (macid_ctl->rate_bmp1[i] << 20);
+ }
+
+ if (r_bmp_cck_ofdm)
+ *r_bmp_cck_ofdm = bmp_cck_ofdm;
+ if (r_bmp_ht)
+ *r_bmp_ht = bmp_ht;
+ if (r_bmp_vht)
+ *r_bmp_vht = bmp_vht;
+}
+
+void rtw_update_tx_rate_bmp(struct dvobj_priv *dvobj)
+{
+ struct rf_ctl_t *rf_ctl = dvobj_to_rfctl(dvobj);
+ _adapter *adapter = dvobj_get_primary_adapter(dvobj);
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+ u8 bw;
+ u16 bmp_cck_ofdm, tmp_cck_ofdm;
+ u32 bmp_ht, tmp_ht, ori_bmp_ht[2];
+ u8 ori_highest_ht_rate_bw_bmp;
+ u32 bmp_vht, tmp_vht, ori_bmp_vht[4];
+ u8 ori_highest_vht_rate_bw_bmp;
+ int i;
+
+ /* backup the original ht & vht highest bw bmp */
+ ori_highest_ht_rate_bw_bmp = rf_ctl->highest_ht_rate_bw_bmp;
+ ori_highest_vht_rate_bw_bmp = rf_ctl->highest_vht_rate_bw_bmp;
+
+ for (bw = CHANNEL_WIDTH_20; bw <= CHANNEL_WIDTH_160; bw++) {
+ /* backup the original ht & vht bmp */
+ if (bw <= CHANNEL_WIDTH_40)
+ ori_bmp_ht[bw] = rf_ctl->rate_bmp_ht_by_bw[bw];
+ if (bw <= CHANNEL_WIDTH_160)
+ ori_bmp_vht[bw] = rf_ctl->rate_bmp_vht_by_bw[bw];
+
+ bmp_cck_ofdm = bmp_ht = bmp_vht = 0;
+ if (hal_is_bw_support(dvobj_get_primary_adapter(dvobj), bw)) {
+ for (i = 0; i < dvobj->iface_nums; i++) {
+ if (!dvobj->padapters[i])
+ continue;
+ rtw_get_adapter_tx_rate_bmp_by_bw(dvobj->padapters[i], bw, &tmp_cck_ofdm, &tmp_ht, &tmp_vht);
+ bmp_cck_ofdm |= tmp_cck_ofdm;
+ bmp_ht |= tmp_ht;
+ bmp_vht |= tmp_vht;
+ }
+ rtw_get_shared_macid_tx_rate_bmp_by_bw(dvobj, bw, &tmp_cck_ofdm, &tmp_ht, &tmp_vht);
+ bmp_cck_ofdm |= tmp_cck_ofdm;
+ bmp_ht |= tmp_ht;
+ bmp_vht |= tmp_vht;
+ }
+ if (bw == CHANNEL_WIDTH_20)
+ rf_ctl->rate_bmp_cck_ofdm = bmp_cck_ofdm;
+ if (bw <= CHANNEL_WIDTH_40)
+ rf_ctl->rate_bmp_ht_by_bw[bw] = bmp_ht;
+ if (bw <= CHANNEL_WIDTH_160)
+ rf_ctl->rate_bmp_vht_by_bw[bw] = bmp_vht;
+ }
+
+#ifndef DBG_HIGHEST_RATE_BMP_BW_CHANGE
+#define DBG_HIGHEST_RATE_BMP_BW_CHANGE 0
+#endif
+
+ {
+ u8 highest_rate_bw;
+ u8 highest_rate_bw_bmp;
+ u8 update_ht_rs = _FALSE;
+ u8 update_vht_rs = _FALSE;
+
+ highest_rate_bw_bmp = BW_CAP_20M;
+ highest_rate_bw = CHANNEL_WIDTH_20;
+ for (bw = CHANNEL_WIDTH_20; bw <= CHANNEL_WIDTH_40; bw++) {
+ if (rf_ctl->rate_bmp_ht_by_bw[highest_rate_bw] < rf_ctl->rate_bmp_ht_by_bw[bw]) {
+ highest_rate_bw_bmp = ch_width_to_bw_cap(bw);
+ highest_rate_bw = bw;
+ } else if (rf_ctl->rate_bmp_ht_by_bw[highest_rate_bw] == rf_ctl->rate_bmp_ht_by_bw[bw])
+ highest_rate_bw_bmp |= ch_width_to_bw_cap(bw);
+ }
+ rf_ctl->highest_ht_rate_bw_bmp = highest_rate_bw_bmp;
+
+ if (ori_highest_ht_rate_bw_bmp != rf_ctl->highest_ht_rate_bw_bmp
+ || largest_bit(ori_bmp_ht[highest_rate_bw]) != largest_bit(rf_ctl->rate_bmp_ht_by_bw[highest_rate_bw])
+ ) {
+ if (DBG_HIGHEST_RATE_BMP_BW_CHANGE) {
+ RTW_INFO("highest_ht_rate_bw_bmp:0x%02x=>0x%02x\n", ori_highest_ht_rate_bw_bmp, rf_ctl->highest_ht_rate_bw_bmp);
+ RTW_INFO("rate_bmp_ht_by_bw[%u]:0x%08x=>0x%08x\n", highest_rate_bw, ori_bmp_ht[highest_rate_bw], rf_ctl->rate_bmp_ht_by_bw[highest_rate_bw]);
+ }
+ update_ht_rs = _TRUE;
+ }
+
+ highest_rate_bw_bmp = BW_CAP_20M;
+ highest_rate_bw = CHANNEL_WIDTH_20;
+ for (bw = CHANNEL_WIDTH_20; bw <= CHANNEL_WIDTH_160; bw++) {
+ if (rf_ctl->rate_bmp_vht_by_bw[highest_rate_bw] < rf_ctl->rate_bmp_vht_by_bw[bw]) {
+ highest_rate_bw_bmp = ch_width_to_bw_cap(bw);
+ highest_rate_bw = bw;
+ } else if (rf_ctl->rate_bmp_vht_by_bw[highest_rate_bw] == rf_ctl->rate_bmp_vht_by_bw[bw])
+ highest_rate_bw_bmp |= ch_width_to_bw_cap(bw);
+ }
+ rf_ctl->highest_vht_rate_bw_bmp = highest_rate_bw_bmp;
+
+ if (ori_highest_vht_rate_bw_bmp != rf_ctl->highest_vht_rate_bw_bmp
+ || largest_bit(ori_bmp_vht[highest_rate_bw]) != largest_bit(rf_ctl->rate_bmp_vht_by_bw[highest_rate_bw])
+ ) {
+ if (DBG_HIGHEST_RATE_BMP_BW_CHANGE) {
+ RTW_INFO("highest_vht_rate_bw_bmp:0x%02x=>0x%02x\n", ori_highest_vht_rate_bw_bmp, rf_ctl->highest_vht_rate_bw_bmp);
+ RTW_INFO("rate_bmp_vht_by_bw[%u]:0x%08x=>0x%08x\n", highest_rate_bw, ori_bmp_vht[highest_rate_bw], rf_ctl->rate_bmp_vht_by_bw[highest_rate_bw]);
+ }
+ update_vht_rs = _TRUE;
+ }
+
+ /* TODO: per rfpath and rate section handling? */
+ if (update_ht_rs == _TRUE || update_vht_rs == _TRUE)
+ rtw_hal_set_tx_power_level(dvobj_get_primary_adapter(dvobj), hal_data->current_channel);
+ }
+}
+
+inline u16 rtw_get_tx_rate_bmp_cck_ofdm(struct dvobj_priv *dvobj)
+{
+ struct rf_ctl_t *rf_ctl = dvobj_to_rfctl(dvobj);
+
+ return rf_ctl->rate_bmp_cck_ofdm;
+}
+
+inline u32 rtw_get_tx_rate_bmp_ht_by_bw(struct dvobj_priv *dvobj, u8 bw)
+{
+ struct rf_ctl_t *rf_ctl = dvobj_to_rfctl(dvobj);
+
+ return rf_ctl->rate_bmp_ht_by_bw[bw];
+}
+
+inline u32 rtw_get_tx_rate_bmp_vht_by_bw(struct dvobj_priv *dvobj, u8 bw)
+{
+ struct rf_ctl_t *rf_ctl = dvobj_to_rfctl(dvobj);
+
+ return rf_ctl->rate_bmp_vht_by_bw[bw];
+}
+
+u8 rtw_get_tx_bw_bmp_of_ht_rate(struct dvobj_priv *dvobj, u8 rate, u8 max_bw)
+{
+ struct rf_ctl_t *rf_ctl = dvobj_to_rfctl(dvobj);
+ u8 bw;
+ u8 bw_bmp = 0;
+ u32 rate_bmp;
+
+ if (!IS_HT_RATE(rate)) {
+ rtw_warn_on(1);
+ goto exit;
+ }
+
+ rate_bmp = 1 << (rate - MGN_MCS0);
- _func_exit_;
+ if (max_bw > CHANNEL_WIDTH_40)
+ max_bw = CHANNEL_WIDTH_40;
+ for (bw = CHANNEL_WIDTH_20; bw <= max_bw; bw++) {
+ /* RA may use lower rate for retry */
+ if (rf_ctl->rate_bmp_ht_by_bw[bw] >= rate_bmp)
+ bw_bmp |= ch_width_to_bw_cap(bw);
+ }
+
+exit:
+ return bw_bmp;
+}
+
+u8 rtw_get_tx_bw_bmp_of_vht_rate(struct dvobj_priv *dvobj, u8 rate, u8 max_bw)
+{
+ struct rf_ctl_t *rf_ctl = dvobj_to_rfctl(dvobj);
+ u8 bw;
+ u8 bw_bmp = 0;
+ u32 rate_bmp;
+
+ if (!IS_VHT_RATE(rate)) {
+ rtw_warn_on(1);
+ goto exit;
+ }
+
+ rate_bmp = 1 << (rate - MGN_VHT1SS_MCS0);
+
+ if (max_bw > CHANNEL_WIDTH_160)
+ max_bw = CHANNEL_WIDTH_160;
+
+ for (bw = CHANNEL_WIDTH_20; bw <= max_bw; bw++) {
+ /* RA may use lower rate for retry */
+ if (rf_ctl->rate_bmp_vht_by_bw[bw] >= rate_bmp)
+ bw_bmp |= ch_width_to_bw_cap(bw);
+ }
+
+exit:
+ return bw_bmp;
}
-u8 query_ra_short_GI(struct sta_info *psta)
+u8 query_ra_short_GI(struct sta_info *psta, u8 bw)
{
u8 sgi = _FALSE, sgi_20m = _FALSE, sgi_40m = _FALSE, sgi_80m = _FALSE;
@@ -456,14 +736,12 @@ u8 query_ra_short_GI(struct sta_info *psta)
#ifdef CONFIG_80211AC_VHT
if (psta->vhtpriv.vht_option)
sgi_80m = psta->vhtpriv.sgi_80m;
-#endif /* CONFIG_80211AC_VHT */
- {
- sgi_20m = psta->htpriv.sgi_20m;
- sgi_40m = psta->htpriv.sgi_40m;
- }
+#endif
+ sgi_20m = psta->htpriv.sgi_20m;
+ sgi_40m = psta->htpriv.sgi_40m;
#endif
- switch (psta->bw_mode) {
+ switch (bw) {
case CHANNEL_WIDTH_80:
sgi = sgi_80m;
break;
@@ -602,9 +880,42 @@ static void update_attrib_vcs_info(_adapter *padapter, struct xmit_frame *pxmitf
}
+#ifdef CONFIG_WMMPS_STA
+/*
+ * update_attrib_trigger_frame_info
+ * For Station mode, if a specific TID of driver setting and an AP support uapsd function, the data
+ * frame with corresponding TID will be a trigger frame when driver is in wmm power saving mode.
+ *
+ * Arguments:
+ * @padapter: _adapter pointer.
+ * @pattrib: pkt_attrib pointer.
+ *
+ * Auther: Arvin Liu
+ * Date: 2017/06/05
+ */
+static void update_attrib_trigger_frame_info(_adapter *padapter, struct pkt_attrib *pattrib) {
+ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
+ struct qos_priv *pqospriv = &pmlmepriv->qospriv;
+ u8 trigger_frame_en = 0;
+
+ if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) {
+ if ((pwrpriv->pwr_mode == PS_MODE_MIN) || (pwrpriv->pwr_mode == PS_MODE_MAX)) {
+ if((pqospriv->uapsd_ap_supported) && ((pqospriv->uapsd_tid & BIT(pattrib->priority)) == _TRUE)) {
+ trigger_frame_en = 1;
+ RTW_INFO("[WMMPS]"FUNC_ADPT_FMT": This is a Trigger Frame\n", FUNC_ADPT_ARG(padapter));
+ }
+ }
+ }
+
+ pattrib->trigger_frame = trigger_frame_en;
+}
+#endif /* CONFIG_WMMPS_STA */
+
static void update_attrib_phy_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta)
{
struct mlme_ext_priv *mlmeext = &padapter->mlmeextpriv;
+ u8 bw;
pattrib->rtsen = psta->rtsen;
pattrib->cts2self = psta->cts2self;
@@ -617,17 +928,14 @@ static void update_attrib_phy_info(_adapter *padapter, struct pkt_attrib *pattri
/* qos_en, ht_en, init rate, ,bw, ch_offset, sgi */
pattrib->qos_en = psta->qos_option;
- pattrib->raid = psta->raid;
-
- if (mlmeext->cur_bwmode < psta->bw_mode)
- pattrib->bwmode = mlmeext->cur_bwmode;
- else
- pattrib->bwmode = psta->bw_mode;
+ pattrib->raid = psta->cmn.ra_info.rate_id;
- pattrib->sgi = query_ra_short_GI(psta);
+ bw = rtw_get_tx_bw_mode(padapter, psta);
+ pattrib->bwmode = rtw_min(bw, mlmeext->cur_bwmode);
+ pattrib->sgi = query_ra_short_GI(psta, pattrib->bwmode);
- pattrib->ldpc = psta->ldpc;
- pattrib->stbc = psta->stbc;
+ pattrib->ldpc = psta->cmn.ldpc_en;
+ pattrib->stbc = psta->cmn.stbc_en;
#ifdef CONFIG_80211N_HT
pattrib->ht_en = psta->htpriv.ht_option;
@@ -638,6 +946,17 @@ static void update_attrib_phy_info(_adapter *padapter, struct pkt_attrib *pattri
pattrib->ampdu_spacing = padapter->driver_ampdu_spacing;
else
pattrib->ampdu_spacing = psta->htpriv.rx_ampdu_min_spacing;
+
+ /* check if enable ampdu */
+ if (pattrib->ht_en && psta->htpriv.ampdu_enable) {
+ if (psta->htpriv.agg_enable_bitmap & BIT(pattrib->priority)) {
+ pattrib->ampdu_en = _TRUE;
+ if (psta->htpriv.tx_amsdu_enable == _TRUE)
+ pattrib->amsdu_ampdu_en = _TRUE;
+ else
+ pattrib->amsdu_ampdu_en = _FALSE;
+ }
+ }
#endif /* CONFIG_80211N_HT */
/* if(pattrib->ht_en && psta->htpriv.ampdu_enable) */
/* { */
@@ -649,12 +968,12 @@ static void update_attrib_phy_info(_adapter *padapter, struct pkt_attrib *pattri
if (pattrib->direct_link == _TRUE) {
psta = pattrib->ptdls_sta;
- pattrib->raid = psta->raid;
+ pattrib->raid = psta->cmn.ra_info.rate_id;
#ifdef CONFIG_80211N_HT
- pattrib->bwmode = psta->bw_mode;
+ pattrib->bwmode = rtw_get_tx_bw_mode(padapter, psta);
pattrib->ht_en = psta->htpriv.ht_option;
pattrib->ch_offset = psta->htpriv.ch_offset;
- pattrib->sgi = query_ra_short_GI(psta);
+ pattrib->sgi = query_ra_short_GI(psta, pattrib->bwmode);
#endif /* CONFIG_80211N_HT */
}
#endif /* CONFIG_TDLS */
@@ -677,15 +996,13 @@ static s32 update_attrib_sec_info(_adapter *padapter, struct pkt_attrib *pattrib
_rtw_memset(pattrib->dot118021x_UncstKey.skey, 0, 16);
_rtw_memset(pattrib->dot11tkiptxmickey.skey, 0, 16);
- pattrib->mac_id = psta->mac_id;
+ pattrib->mac_id = psta->cmn.mac_id;
if (psta->ieee8021x_blocked == _TRUE) {
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("\n psta->ieee8021x_blocked == _TRUE\n"));
pattrib->encrypt = 0;
if ((pattrib->ether_type != 0x888e) && (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _FALSE)) {
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("\npsta->ieee8021x_blocked == _TRUE, pattrib->ether_type(%.4x) != 0x888e\n", pattrib->ether_type));
#ifdef DBG_TX_DROP_FRAME
RTW_INFO("DBG_TX_DROP_FRAME %s psta->ieee8021x_blocked == _TRUE, pattrib->ether_type(%04x) != 0x888e\n", __FUNCTION__, pattrib->ether_type);
#endif
@@ -788,19 +1105,12 @@ static s32 update_attrib_sec_info(_adapter *padapter, struct pkt_attrib *pattrib
if (pattrib->encrypt > 0)
_rtw_memcpy(pattrib->dot118021x_UncstKey.skey, psta->dot118021x_UncstKey.skey, 16);
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_,
- ("update_attrib: encrypt=%d securitypriv.sw_encrypt=%d\n",
- pattrib->encrypt, padapter->securitypriv.sw_encrypt));
if (pattrib->encrypt &&
((padapter->securitypriv.sw_encrypt == _TRUE) || (psecuritypriv->hw_decrypted == _FALSE))) {
pattrib->bswenc = _TRUE;
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_,
- ("update_attrib: encrypt=%d securitypriv.hw_decrypted=%d bswenc=_TRUE\n",
- pattrib->encrypt, padapter->securitypriv.sw_encrypt));
} else {
pattrib->bswenc = _FALSE;
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("update_attrib: bswenc=_FALSE\n"));
}
#if defined(CONFIG_CONCURRENT_MODE)
@@ -930,7 +1240,7 @@ s32 update_tdls_attrib(_adapter *padapter, struct pkt_attrib *pattrib)
goto exit;
}
- pattrib->mac_id = psta->mac_id;
+ pattrib->mac_id = psta->cmn.mac_id;
pattrib->psta = psta;
pattrib->ack_policy = 0;
/* get ether_hdr_len */
@@ -968,13 +1278,14 @@ inline u8 rtw_get_hwseq_no(_adapter *padapter)
{
u8 hwseq_num = 0;
#ifdef CONFIG_CONCURRENT_MODE
- if (padapter->adapter_type != PRIMARY_ADAPTER)
+ if (!is_primary_adapter(padapter))
hwseq_num = 1;
/* else */
/* hwseq_num = 2; */
#endif /* CONFIG_CONCURRENT_MODE */
return hwseq_num;
}
+
static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattrib)
{
uint i;
@@ -990,7 +1301,6 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
sint res = _SUCCESS;
- _func_enter_;
DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib);
@@ -999,11 +1309,12 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr
pattrib->ether_type = ntohs(etherhdr.h_proto);
+ if (MLME_IS_MESH(padapter)) /* address resolve is done for mesh */
+ goto get_sta_info;
_rtw_memcpy(pattrib->dst, ðerhdr.h_dest, ETH_ALEN);
_rtw_memcpy(pattrib->src, ðerhdr.h_source, ETH_ALEN);
-
if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) ||
(check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) {
_rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);
@@ -1025,15 +1336,15 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr
} else
DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_unknown);
+get_sta_info:
bmcast = IS_MCAST(pattrib->ra);
if (bmcast) {
psta = rtw_get_bcmc_stainfo(padapter);
if (psta == NULL) { /* if we cannot get psta => drop the pkt */
DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_sta);
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_alert_, ("\nupdate_attrib => get sta_info fail, ra:" MAC_FMT "\n", MAC_ARG(pattrib->ra)));
-#ifdef DBG_TX_DROP_FRAME
+ #ifdef DBG_TX_DROP_FRAME
RTW_INFO("DBG_TX_DROP_FRAME %s get sta_info fail, ra:" MAC_FMT"\n", __func__, MAC_ARG(pattrib->ra));
-#endif
+ #endif
res = _FAIL;
goto exit;
}
@@ -1041,10 +1352,9 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr
psta = rtw_get_stainfo(pstapriv, pattrib->ra);
if (psta == NULL) { /* if we cannot get psta => drop the pkt */
DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_ucast_sta);
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_alert_, ("\nupdate_attrib => get sta_info fail, ra:" MAC_FMT"\n", MAC_ARG(pattrib->ra)));
-#ifdef DBG_TX_DROP_FRAME
+ #ifdef DBG_TX_DROP_FRAME
RTW_INFO("DBG_TX_DROP_FRAME %s get sta_info fail, ra:" MAC_FMT"\n", __func__, MAC_ARG(pattrib->ra));
-#endif
+ #endif
res = _FAIL;
goto exit;
} else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE && !(psta->state & _FW_LINKED)) {
@@ -1056,7 +1366,8 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr
if (!(psta->state & _FW_LINKED)) {
DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_link);
- RTW_INFO("%s-"ADPT_FMT" psta("MAC_FMT")->state(0x%x) != _FW_LINKED\n", __func__, ADPT_ARG(padapter), MAC_ARG(psta->hwaddr), psta->state);
+ RTW_INFO("%s-"ADPT_FMT" psta("MAC_FMT")->state(0x%x) != _FW_LINKED\n",
+ __func__, ADPT_ARG(padapter), MAC_ARG(psta->cmn.mac_addr), psta->state);
res = _FAIL;
goto exit;
}
@@ -1087,8 +1398,8 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr
_rtw_pktfile_read(&pktfile, udp, 8);
if ((GET_UDP_SRC(udp) == 68 && GET_UDP_DST(udp) == 67)
- || (GET_UDP_SRC(udp) == 67 && GET_UDP_DST(udp) == 68)
- ) {
+ || (GET_UDP_SRC(udp) == 67 && GET_UDP_DST(udp) == 68)
+ ) {
/* 67 : UDP BOOTP server, 68 : UDP BOOTP client */
if (pattrib->pktlen > 282) { /* MINIMUM_DHCP_PACKET_SIZE */
pattrib->dhcp_pkt = 1;
@@ -1100,7 +1411,7 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr
} else if (GET_IPV4_PROTOCOL(ip) == 0x06 /* TCP */
&& rtw_st_ctl_chk_reg_s_proto(&psta->st_ctl, 0x06) == _TRUE
- ) {
+ ) {
u8 tcp[20];
_rtw_pktfile_read(&pktfile, tcp, 20);
@@ -1183,9 +1494,19 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr
pattrib->subtype = WIFI_DATA_TYPE;
pattrib->priority = 0;
- if (check_fwstate(pmlmepriv, WIFI_AP_STATE | WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) {
- if (pattrib->qos_en)
+ if (bmcast)
+ pattrib->rate = psta->init_rate;
+
+ if (check_fwstate(pmlmepriv, WIFI_AP_STATE | WIFI_MESH_STATE
+ | WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)
+ ) {
+ if (pattrib->qos_en) {
set_qos(&pktfile, pattrib);
+ #ifdef CONFIG_RTW_MESH
+ if (MLME_IS_MESH(padapter))
+ rtw_mesh_tx_set_whdr_mctrl_len(pattrib->mesh_frame_mode, pattrib);
+ #endif
+ }
} else {
#ifdef CONFIG_TDLS
if (pattrib->direct_link == _TRUE) {
@@ -1203,13 +1524,16 @@ static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattr
}
}
+#ifdef CONFIG_WMMPS_STA
+ update_attrib_trigger_frame_info(padapter, pattrib);
+#endif /* CONFIG_WMMPS_STA */
+
/* pattrib->priority = 5; */ /* force to used VI queue, for testing */
pattrib->hw_ssn_sel = pxmitpriv->hw_ssn_seq_no;
rtw_set_tx_chksum_offload(pkt, pattrib);
exit:
- _func_exit_;
return res;
}
@@ -1252,7 +1576,6 @@ static s32 xmitframe_addmic(_adapter *padapter, struct xmit_frame *pxmitframe)
}
*/
- _func_enter_;
#ifdef CONFIG_USB_TX_AGGREGATION
hw_hdr_offset = TXDESC_SIZE + (pxmitframe->pkt_offset * PACKET_OFFSET_SZ);;
@@ -1316,11 +1639,8 @@ static s32 xmitframe_addmic(_adapter *padapter, struct xmit_frame *pxmitframe)
for (curfragnum = 0; curfragnum < pattrib->nr_frags; curfragnum++) {
payload = (u8 *)RND4((SIZE_PTR)(payload));
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("===curfragnum=%d, pframe= 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x,!!!\n",
- curfragnum, *payload, *(payload + 1), *(payload + 2), *(payload + 3), *(payload + 4), *(payload + 5), *(payload + 6), *(payload + 7)));
payload = payload + pattrib->hdrlen + pattrib->iv_len;
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("curfragnum=%d pattrib->hdrlen=%d pattrib->iv_len=%d", curfragnum, pattrib->hdrlen, pattrib->iv_len));
if ((curfragnum + 1) == pattrib->nr_frags) {
length = pattrib->last_txcmdsz - pattrib->hdrlen - pattrib->iv_len - ((pattrib->bswenc) ? pattrib->icv_len : 0);
rtw_secmicappend(&micdata, payload, length);
@@ -1329,35 +1649,18 @@ static s32 xmitframe_addmic(_adapter *padapter, struct xmit_frame *pxmitframe)
length = pxmitpriv->frag_len - pattrib->hdrlen - pattrib->iv_len - ((pattrib->bswenc) ? pattrib->icv_len : 0);
rtw_secmicappend(&micdata, payload, length);
payload = payload + length + pattrib->icv_len;
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("curfragnum=%d length=%d pattrib->icv_len=%d", curfragnum, length, pattrib->icv_len));
}
}
rtw_secgetmic(&micdata, &(mic[0]));
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("xmitframe_addmic: before add mic code!!!\n"));
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("xmitframe_addmic: pattrib->last_txcmdsz=%d!!!\n", pattrib->last_txcmdsz));
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("xmitframe_addmic: mic[0]=0x%.2x ,mic[1]=0x%.2x ,mic[2]=0x%.2x ,mic[3]=0x%.2x \n\
- mic[4]=0x%.2x ,mic[5]=0x%.2x ,mic[6]=0x%.2x ,mic[7]=0x%.2x !!!!\n",
- mic[0], mic[1], mic[2], mic[3], mic[4], mic[5], mic[6], mic[7]));
/* add mic code and add the mic code length in last_txcmdsz */
_rtw_memcpy(payload, &(mic[0]), 8);
pattrib->last_txcmdsz += 8;
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("\n ========last pkt========\n"));
payload = payload - pattrib->last_txcmdsz + 8;
- for (curfragnum = 0; curfragnum < pattrib->last_txcmdsz; curfragnum = curfragnum + 8)
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, (" %.2x, %.2x, %.2x, %.2x, %.2x, %.2x, %.2x, %.2x ",
- *(payload + curfragnum), *(payload + curfragnum + 1), *(payload + curfragnum + 2), *(payload + curfragnum + 3),
- *(payload + curfragnum + 4), *(payload + curfragnum + 5), *(payload + curfragnum + 6), *(payload + curfragnum + 7)));
}
- /*
- else{
- RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("xmitframe_addmic: rtw_get_stainfo==NULL!!!\n"));
- }
- */
}
- _func_exit_;
return _SUCCESS;
}
@@ -1370,7 +1673,6 @@ static s32 xmitframe_swencrypt(_adapter *padapter, struct xmit_frame *pxmitframe
struct pkt_attrib *pattrib = &pxmitframe->attrib;
/* struct security_priv *psecuritypriv=&padapter->securitypriv; */
- _func_enter_;
/* if((psecuritypriv->sw_encrypt)||(pattrib->bswenc)) */
if (pattrib->bswenc) {
@@ -1379,7 +1681,6 @@ static s32 xmitframe_swencrypt(_adapter *padapter, struct xmit_frame *pxmitframe
ADPT_ARG(padapter), security_type_str(pattrib->encrypt));
#endif
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_alert_, ("### xmitframe_swencrypt\n"));
switch (pattrib->encrypt) {
case _WEP40_:
case _WEP104_:
@@ -1399,10 +1700,8 @@ static s32 xmitframe_swencrypt(_adapter *padapter, struct xmit_frame *pxmitframe
break;
}
- } else
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_notice_, ("### xmitframe_hwencrypt\n"));
+ }
- _func_exit_;
return _SUCCESS;
}
@@ -1422,7 +1721,6 @@ s32 rtw_make_wlanhdr(_adapter *padapter , u8 *hdr, struct pkt_attrib *pattrib)
/* sint bmcst = IS_MCAST(pattrib->ra); */
- _func_enter_;
/*
psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
@@ -1447,7 +1745,7 @@ s32 rtw_make_wlanhdr(_adapter *padapter , u8 *hdr, struct pkt_attrib *pattrib)
_rtw_memset(hdr, 0, WLANHDR_OFFSET);
- SetFrameSubType(fctrl, pattrib->subtype);
+ set_frame_sub_type(fctrl, pattrib->subtype);
if (pattrib->subtype & WIFI_DATA_TYPE) {
if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)) {
@@ -1491,8 +1789,18 @@ s32 rtw_make_wlanhdr(_adapter *padapter , u8 *hdr, struct pkt_attrib *pattrib)
if (pattrib->qos_en)
qos_option = _TRUE;
+#ifdef CONFIG_RTW_MESH
+ } else if (check_fwstate(pmlmepriv, WIFI_MESH_STATE) == _TRUE) {
+ rtw_mesh_tx_build_whdr(padapter, pattrib, fctrl, pwlanhdr);
+ if (pattrib->qos_en)
+ qos_option = _TRUE;
+ else {
+ RTW_WARN("[%s] !qos_en in Mesh\n", __FUNCTION__);
+ res = _FAIL;
+ goto exit;
+ }
+#endif
} else {
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("fw_state:%x is not allowed to xmit frame\n", get_fwstate(pmlmepriv)));
res = _FAIL;
goto exit;
}
@@ -1515,6 +1823,18 @@ s32 rtw_make_wlanhdr(_adapter *padapter , u8 *hdr, struct pkt_attrib *pattrib)
if(pattrib->amsdu)
SetAMsdu(qc, pattrib->amsdu);
+#ifdef CONFIG_RTW_MESH
+ if (MLME_IS_MESH(padapter)) {
+ /* active: don't care, light sleep: 0, deep sleep: 1*/
+ set_mps_lv(qc, 0); //TBD
+
+ /* TBD: temporary set (rspi, eosp) = (0, 1) which means End MPSP */
+ set_rspi(qc, 0);
+ SetEOSP(qc, 1);
+
+ set_mctrl_present(qc, 1);
+ }
+#endif
}
/* TODO: fill HT Control Field */
@@ -1547,12 +1867,13 @@ s32 rtw_make_wlanhdr(_adapter *padapter , u8 *hdr, struct pkt_attrib *pattrib)
SetSeqNum(hdr, pattrib->seqnum);
#ifdef CONFIG_80211N_HT
+#if 0 /* move into update_attrib_phy_info(). */
/* check if enable ampdu */
if (pattrib->ht_en && psta->htpriv.ampdu_enable) {
if (psta->htpriv.agg_enable_bitmap & BIT(pattrib->priority))
pattrib->ampdu_en = _TRUE;
}
-
+#endif
/* re-check if enable ampdu by BA_starting_seqctrl */
if (pattrib->ampdu_en == _TRUE) {
u16 tx_seq;
@@ -1584,7 +1905,6 @@ s32 rtw_make_wlanhdr(_adapter *padapter , u8 *hdr, struct pkt_attrib *pattrib)
exit:
- _func_exit_;
return res;
}
@@ -1659,37 +1979,53 @@ s32 rtw_txframes_sta_ac_pending(_adapter *padapter, struct pkt_attrib *pattrib)
int rtw_build_tdls_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt)
{
+ struct pkt_attrib *pattrib = &pxmitframe->attrib;
+ struct sta_info *ptdls_sta = NULL;
int res = _SUCCESS;
+ ptdls_sta = rtw_get_stainfo((&padapter->stapriv), pattrib->dst);
+ if (ptdls_sta == NULL) {
+ switch (ptxmgmt->action_code) {
+ case TDLS_DISCOVERY_REQUEST:
+ case TUNNELED_PROBE_REQ:
+ case TUNNELED_PROBE_RSP:
+ break;
+ default:
+ RTW_INFO("[TDLS] %s - Direct Link Peer = "MAC_FMT" not found for action = %d\n", __func__, MAC_ARG(pattrib->dst), ptxmgmt->action_code);
+ res = _FAIL;
+ goto exit;
+ }
+ }
+
switch (ptxmgmt->action_code) {
case TDLS_SETUP_REQUEST:
- rtw_build_tdls_setup_req_ies(padapter, pxmitframe, pframe, ptxmgmt);
+ rtw_build_tdls_setup_req_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);
break;
case TDLS_SETUP_RESPONSE:
- rtw_build_tdls_setup_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt);
+ rtw_build_tdls_setup_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);
break;
case TDLS_SETUP_CONFIRM:
- rtw_build_tdls_setup_cfm_ies(padapter, pxmitframe, pframe, ptxmgmt);
+ rtw_build_tdls_setup_cfm_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);
break;
case TDLS_TEARDOWN:
- rtw_build_tdls_teardown_ies(padapter, pxmitframe, pframe, ptxmgmt);
+ rtw_build_tdls_teardown_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);
break;
case TDLS_DISCOVERY_REQUEST:
rtw_build_tdls_dis_req_ies(padapter, pxmitframe, pframe, ptxmgmt);
break;
case TDLS_PEER_TRAFFIC_INDICATION:
- rtw_build_tdls_peer_traffic_indication_ies(padapter, pxmitframe, pframe, ptxmgmt);
+ rtw_build_tdls_peer_traffic_indication_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);
break;
#ifdef CONFIG_TDLS_CH_SW
case TDLS_CHANNEL_SWITCH_REQUEST:
- rtw_build_tdls_ch_switch_req_ies(padapter, pxmitframe, pframe, ptxmgmt);
+ rtw_build_tdls_ch_switch_req_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);
break;
case TDLS_CHANNEL_SWITCH_RESPONSE:
- rtw_build_tdls_ch_switch_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt);
+ rtw_build_tdls_ch_switch_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);
break;
#endif
case TDLS_PEER_TRAFFIC_RESPONSE:
- rtw_build_tdls_peer_traffic_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt);
+ rtw_build_tdls_peer_traffic_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt, ptdls_sta);
break;
#ifdef CONFIG_WFD
case TUNNELED_PROBE_REQ:
@@ -1704,6 +2040,7 @@ int rtw_build_tdls_ies(_adapter *padapter, struct xmit_frame *pxmitframe, u8 *pf
break;
}
+exit:
return res;
}
@@ -1720,11 +2057,10 @@ s32 rtw_make_tdls_wlanhdr(_adapter *padapter , u8 *hdr, struct pkt_attrib *pattr
sint res = _SUCCESS;
u16 *fctrl = &pwlanhdr->frame_ctl;
- _func_enter_;
_rtw_memset(hdr, 0, WLANHDR_OFFSET);
- SetFrameSubType(fctrl, pattrib->subtype);
+ set_frame_sub_type(fctrl, pattrib->subtype);
switch (ptxmgmt->action_code) {
case TDLS_SETUP_REQUEST:
@@ -1795,7 +2131,7 @@ s32 rtw_make_tdls_wlanhdr(_adapter *padapter , u8 *hdr, struct pkt_attrib *pattr
pattrib->icv_len = 8;
pattrib->bswenc = _FALSE;
}
- pattrib->mac_id = ptdls_sta->mac_id;
+ pattrib->mac_id = ptdls_sta->cmn.mac_id;
} else {
res = _FAIL;
goto exit;
@@ -1810,7 +2146,6 @@ s32 rtw_make_tdls_wlanhdr(_adapter *padapter , u8 *hdr, struct pkt_attrib *pattr
exit:
- _func_exit_;
return res;
}
@@ -1829,7 +2164,6 @@ s32 rtw_xmit_tdls_coalesce(_adapter *padapter, struct xmit_frame *pxmitframe, st
s32 bmcst = IS_MCAST(pattrib->ra);
s32 res = _SUCCESS;
- _func_enter_;
if (pattrib->psta)
psta = pattrib->psta;
@@ -1918,7 +2252,6 @@ s32 rtw_xmit_tdls_coalesce(_adapter *padapter, struct xmit_frame *pxmitframe, st
exit:
- _func_exit_;
return res;
}
@@ -1932,22 +2265,23 @@ u32 rtw_calculate_wlan_pkt_size_by_attribue(struct pkt_attrib *pattrib)
{
u32 len = 0;
- len = pattrib->hdrlen + pattrib->iv_len; /* WLAN Header and IV */
- len += SNAP_SIZE + sizeof(u16); /* LLC */
- len += pattrib->pktlen;
- if (pattrib->encrypt == _TKIP_)
- len += 8; /* MIC */
- len += ((pattrib->bswenc) ? pattrib->icv_len : 0); /* ICV */
+ len = pattrib->hdrlen /* WLAN Header */
+ + pattrib->iv_len /* IV */
+ + XATTRIB_GET_MCTRL_LEN(pattrib)
+ + SNAP_SIZE + sizeof(u16) /* LLC */
+ + pattrib->pktlen
+ + (pattrib->encrypt == _TKIP_ ? 8 : 0) /* MIC */
+ + (pattrib->bswenc ? pattrib->icv_len : 0) /* ICV */
+ ;
return len;
}
-#ifdef TX_AMSDU
-
+#ifdef CONFIG_TX_AMSDU
s32 check_amsdu(struct xmit_frame *pxmitframe)
{
struct pkt_attrib *pattrib;
- int ret = _TRUE;
+ s32 ret = _TRUE;
if (!pxmitframe)
ret = _FALSE;
@@ -1971,9 +2305,34 @@ s32 check_amsdu(struct xmit_frame *pxmitframe)
if (!pattrib->qos_en)
ret = _FALSE;
+ if (IS_AMSDU_AMPDU_NOT_VALID(pattrib))
+ ret = _FALSE;
+
return ret;
}
+s32 check_amsdu_tx_support(_adapter *padapter)
+{
+ struct dvobj_priv *pdvobjpriv;
+ int tx_amsdu;
+ int tx_amsdu_rate;
+ int current_tx_rate;
+ s32 ret = _FALSE;
+
+ pdvobjpriv = adapter_to_dvobj(padapter);
+ tx_amsdu = padapter->tx_amsdu;
+ tx_amsdu_rate = padapter->tx_amsdu_rate;
+ current_tx_rate = pdvobjpriv->traffic_stat.cur_tx_tp;
+
+ if (tx_amsdu == 1)
+ ret = _TRUE;
+ else if (tx_amsdu == 2 && (tx_amsdu_rate == 0 || current_tx_rate > tx_amsdu_rate))
+ ret = _TRUE;
+ else
+ ret = _FALSE;
+
+ return ret;
+}
s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitframe, struct xmit_frame *pxmitframe_queue)
{
@@ -1997,9 +2356,6 @@ s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitfra
u8 *pbuf_start;
s32 res = _SUCCESS;
- _func_enter_;
-
-
if (pxmitframe->buf_addr == NULL) {
RTW_INFO("==> %s buf_addr==NULL\n", __FUNCTION__);
return _FAIL;
@@ -2025,7 +2381,6 @@ s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitfra
pattrib->amsdu = 1;
if (rtw_make_wlanhdr(padapter, mem_start, pattrib) == _FAIL) {
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("rtw_xmitframe_coalesce: rtw_make_wlanhdr fail; drop pkt\n"));
RTW_INFO("rtw_xmitframe_coalesce: rtw_make_wlanhdr fail; drop pkt\n");
res = _FAIL;
goto exit;
@@ -2044,9 +2399,8 @@ s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitfra
if (pattrib->iv_len) {
_rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len); // queue or new?
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_notice_,
- ("rtw_xmitframe_coalesce: keyid=%d pattrib->iv[3]=%.2x pframe=%.2x %.2x %.2x %.2x\n",
- padapter->securitypriv.dot11PrivacyKeyIndex, pattrib->iv[3], *pframe, *(pframe + 1), *(pframe + 2), *(pframe + 3)));
+ RTW_DBG("rtw_xmitframe_coalesce: keyid=%d pattrib->iv[3]=%.2x pframe=%.2x %.2x %.2x %.2x\n",
+ padapter->securitypriv.dot11PrivacyKeyIndex, pattrib->iv[3], *pframe, *(pframe + 1), *(pframe + 2), *(pframe + 3));
pframe += pattrib->iv_len;
}
@@ -2061,16 +2415,28 @@ s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitfra
_rtw_open_pktfile(pkt_queue, &pktfile_queue);
_rtw_pktfile_read(&pktfile_queue, NULL, pattrib_queue->pkt_hdrlen);
- /* 802.3 MAC Header DA(6) SA(6) Len(2)*/
-
- _rtw_memcpy(pframe, pattrib_queue->dst, ETH_ALEN);
- pframe += ETH_ALEN;
-
- _rtw_memcpy(pframe, pattrib_queue->src, ETH_ALEN);
- pframe += ETH_ALEN;
-
- len = (u16*) pframe;
- pframe += 2;
+ #ifdef CONFIG_RTW_MESH
+ if (MLME_IS_MESH(padapter)) {
+ /* mDA(6), mSA(6), len(2), mctrl */
+ _rtw_memcpy(pframe, pattrib_queue->mda, ETH_ALEN);
+ pframe += ETH_ALEN;
+ _rtw_memcpy(pframe, pattrib_queue->msa, ETH_ALEN);
+ pframe += ETH_ALEN;
+ len = (u16*)pframe;
+ pframe += 2;
+ rtw_mesh_tx_build_mctrl(padapter, pattrib_queue, pframe);
+ pframe += XATTRIB_GET_MCTRL_LEN(pattrib_queue);
+ } else
+ #endif
+ {
+ /* 802.3 MAC Header DA(6) SA(6) Len(2)*/
+ _rtw_memcpy(pframe, pattrib_queue->dst, ETH_ALEN);
+ pframe += ETH_ALEN;
+ _rtw_memcpy(pframe, pattrib_queue->src, ETH_ALEN);
+ pframe += ETH_ALEN;
+ len = (u16*)pframe;
+ pframe += 2;
+ }
llc_sz = rtw_put_snap(pframe, pattrib_queue->ether_type);
pframe += llc_sz;
@@ -2078,17 +2444,17 @@ s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitfra
mem_sz = _rtw_pktfile_read(&pktfile_queue, pframe, pattrib_queue->pktlen);
pframe += mem_sz;
- *len = htons(llc_sz + mem_sz);
+ *len = htons(XATTRIB_GET_MCTRL_LEN(pattrib_queue) + llc_sz + mem_sz);
//calc padding
- padding = 4 - ((ETH_HLEN + llc_sz + mem_sz) & (4-1));
+ padding = 4 - ((ETH_HLEN + XATTRIB_GET_MCTRL_LEN(pattrib_queue) + llc_sz + mem_sz) & (4-1));
if(padding == 4)
padding = 0;
//_rtw_memset(pframe,0xaa, padding);
pframe += padding;
- pattrib->last_txcmdsz += ETH_HLEN + llc_sz + mem_sz + padding ;
+ pattrib->last_txcmdsz += ETH_HLEN + XATTRIB_GET_MCTRL_LEN(pattrib_queue) + llc_sz + mem_sz + padding ;
}
//2nd mpdu
@@ -2097,16 +2463,28 @@ s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitfra
_rtw_open_pktfile(pkt, &pktfile);
_rtw_pktfile_read(&pktfile, NULL, pattrib->pkt_hdrlen);
- /* 802.3 MAC Header DA(6) SA(6) Len(2) */
-
- _rtw_memcpy(pframe, pattrib->dst, ETH_ALEN);
- pframe += ETH_ALEN;
-
- _rtw_memcpy(pframe, pattrib->src, ETH_ALEN);
- pframe += ETH_ALEN;
-
- len = (u16*) pframe;
- pframe += 2;
+#ifdef CONFIG_RTW_MESH
+ if (MLME_IS_MESH(padapter)) {
+ /* mDA(6), mSA(6), len(2), mctrl */
+ _rtw_memcpy(pframe, pattrib->mda, ETH_ALEN);
+ pframe += ETH_ALEN;
+ _rtw_memcpy(pframe, pattrib->msa, ETH_ALEN);
+ pframe += ETH_ALEN;
+ len = (u16*)pframe;
+ pframe += 2;
+ rtw_mesh_tx_build_mctrl(padapter, pattrib, pframe);
+ pframe += XATTRIB_GET_MCTRL_LEN(pattrib);
+ } else
+#endif
+ {
+ /* 802.3 MAC Header DA(6) SA(6) Len(2) */
+ _rtw_memcpy(pframe, pattrib->dst, ETH_ALEN);
+ pframe += ETH_ALEN;
+ _rtw_memcpy(pframe, pattrib->src, ETH_ALEN);
+ pframe += ETH_ALEN;
+ len = (u16*)pframe;
+ pframe += 2;
+ }
llc_sz = rtw_put_snap(pframe, pattrib->ether_type);
pframe += llc_sz;
@@ -2115,14 +2493,14 @@ s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitfra
pframe += mem_sz;
- *len = htons(llc_sz + mem_sz);
+ *len = htons(XATTRIB_GET_MCTRL_LEN(pattrib) + llc_sz + mem_sz);
//the last ampdu has no padding
padding = 0;
pattrib->nr_frags = 1;
- pattrib->last_txcmdsz += ETH_HLEN + llc_sz + mem_sz + padding +
+ pattrib->last_txcmdsz += ETH_HLEN + XATTRIB_GET_MCTRL_LEN(pattrib) + llc_sz + mem_sz + padding +
((pattrib->bswenc) ? pattrib->icv_len : 0) ;
if ((pattrib->icv_len > 0) && (pattrib->bswenc)) {
@@ -2131,7 +2509,6 @@ s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitfra
}
if (xmitframe_addmic(padapter, pxmitframe) == _FAIL) {
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("xmitframe_addmic(padapter, pxmitframe)==_FAIL\n"));
RTW_INFO("xmitframe_addmic(padapter, pxmitframe)==_FAIL\n");
res = _FAIL;
goto exit;
@@ -2142,12 +2519,10 @@ s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitfra
pattrib->vcs_mode = NONE_VCS;
exit:
-
- _func_exit_;
-
return res;
}
-#endif
+#endif /* CONFIG_TX_AMSDU */
+
/*
This sub-routine will perform all the following:
@@ -2183,7 +2558,6 @@ s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxm
s32 bmcst = IS_MCAST(pattrib->ra);
s32 res = _SUCCESS;
- _func_enter_;
/*
if (pattrib->psta)
@@ -2229,7 +2603,6 @@ s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxm
mem_start = pbuf_start + hw_hdr_offset;
if (rtw_make_wlanhdr(padapter, mem_start, pattrib) == _FAIL) {
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("rtw_xmitframe_coalesce: rtw_make_wlanhdr fail; drop pkt\n"));
RTW_INFO("rtw_xmitframe_coalesce: rtw_make_wlanhdr fail; drop pkt\n");
res = _FAIL;
goto exit;
@@ -2289,9 +2662,6 @@ s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxm
#endif
_rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len);
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_notice_,
- ("rtw_xmitframe_coalesce: keyid=%d pattrib->iv[3]=%.2x pframe=%.2x %.2x %.2x %.2x\n",
- padapter->securitypriv.dot11PrivacyKeyIndex, pattrib->iv[3], *pframe, *(pframe + 1), *(pframe + 2), *(pframe + 3)));
pframe += pattrib->iv_len;
@@ -2299,6 +2669,14 @@ s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxm
}
if (frg_inx == 0) {
+ #ifdef CONFIG_RTW_MESH
+ if (MLME_IS_MESH(padapter)) {
+ rtw_mesh_tx_build_mctrl(padapter, pattrib, pframe);
+ pframe += XATTRIB_GET_MCTRL_LEN(pattrib);
+ mpdu_len -= XATTRIB_GET_MCTRL_LEN(pattrib);
+ }
+ #endif
+
llc_sz = rtw_put_snap(pframe, pattrib->ether_type);
pframe += llc_sz;
mpdu_len -= llc_sz;
@@ -2326,14 +2704,14 @@ s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxm
if (bmcst || (rtw_endofpktfile(&pktfile) == _TRUE)) {
pattrib->nr_frags = frg_inx;
- pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->iv_len + ((pattrib->nr_frags == 1) ? llc_sz : 0) +
+ pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->iv_len +
+ ((pattrib->nr_frags == 1) ? (XATTRIB_GET_MCTRL_LEN(pattrib) + llc_sz) : 0) +
((pattrib->bswenc) ? pattrib->icv_len : 0) + mem_sz;
ClearMFrag(mem_start);
break;
- } else
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("%s: There're still something in packet!\n", __FUNCTION__));
+ }
addr = (SIZE_PTR)(pframe);
@@ -2343,7 +2721,6 @@ s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxm
}
if (xmitframe_addmic(padapter, pxmitframe) == _FAIL) {
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("xmitframe_addmic(padapter, pxmitframe)==_FAIL\n"));
RTW_INFO("xmitframe_addmic(padapter, pxmitframe)==_FAIL\n");
res = _FAIL;
goto exit;
@@ -2358,20 +2735,27 @@ s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxm
exit:
- _func_exit_;
return res;
}
-#ifdef CONFIG_IEEE80211W
-/* broadcast or multicast management pkt use BIP, unicast management pkt use CCMP encryption */
+#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)
+/*
+ * CCMP encryption for unicast robust mgmt frame and broadcast group privicy action
+ * BIP for broadcast robust mgmt frame
+ */
s32 rtw_mgmt_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe)
{
+#define DBG_MGMT_XMIT_COALESEC_DUMP 0
+#define DBG_MGMT_XMIT_BIP_DUMP 0
+#define DBG_MGMT_XMIT_ENC_DUMP 0
+
struct pkt_file pktfile;
s32 frg_inx, frg_len, mpdu_len, llc_sz, mem_sz;
SIZE_PTR addr;
u8 *pframe, *mem_start = NULL, *tmp_buf = NULL;
u8 hw_hdr_offset, subtype ;
+ u8 category = 0xFF;
struct sta_info *psta = NULL;
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
struct pkt_attrib *pattrib = &pxmitframe->attrib;
@@ -2388,220 +2772,294 @@ s32 rtw_mgmt_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame
_irqL irqL;
u32 ori_len;
+ union pn48 *pn = NULL;
+ u8 kid;
+
+ if (pxmitframe->buf_addr == NULL) {
+ RTW_WARN(FUNC_ADPT_FMT" pxmitframe->buf_addr\n"
+ , FUNC_ADPT_ARG(padapter));
+ return _FAIL;
+ }
+
mem_start = pframe = (u8 *)(pxmitframe->buf_addr) + TXDESC_OFFSET;
pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+ subtype = get_frame_sub_type(pframe); /* bit(7)~bit(2) */
+
+ /* check if robust mgmt frame */
+ if (subtype != WIFI_DEAUTH && subtype != WIFI_DISASSOC && subtype != WIFI_ACTION)
+ return _SUCCESS;
+ if (subtype == WIFI_ACTION) {
+ category = *(pframe + sizeof(struct rtw_ieee80211_hdr_3addr));
+ if (CATEGORY_IS_NON_ROBUST(category))
+ return _SUCCESS;
+ }
+ if (!bmcst) {
+ if (pattrib->psta)
+ psta = pattrib->psta;
+ else
+ pattrib->psta = psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
+ if (psta == NULL) {
+ RTW_INFO(FUNC_ADPT_FMT" unicast sta == NULL\n", FUNC_ADPT_ARG(padapter));
+ return _FAIL;
+ }
+ if (!(psta->flags & WLAN_STA_MFP)) {
+ /* peer is not MFP capable, no need to encrypt */
+ return _SUCCESS;
+ }
+ if (psta->bpairwise_key_installed != _TRUE) {
+ RTW_INFO(FUNC_ADPT_FMT" PTK is not installed\n"
+ , FUNC_ADPT_ARG(padapter));
+ return _FAIL;
+ }
+ }
- _func_enter_;
ori_len = BIP_AAD_SIZE + pattrib->pktlen;
tmp_buf = BIP_AAD = rtw_zmalloc(ori_len);
- subtype = GetFrameSubType(pframe); /* bit(7)~bit(2) */
-
if (BIP_AAD == NULL)
return _FAIL;
_enter_critical_bh(&padapter->security_key_mutex, &irqL);
-
- /* IGTK key is not install, it may not support 802.11w */
- if (padapter->securitypriv.binstallBIPkey != _TRUE) {
- RTW_INFO("no instll BIP key\n");
- goto xmitframe_coalesce_success;
- }
- /* station mode doesn't need TX BIP, just ready the code */
if (bmcst) {
- int frame_body_len;
- u8 mic[16];
-
- _rtw_memset(MME, 0, _MME_IE_LENGTH_);
-
- /* other types doesn't need the BIP */
- if (GetFrameSubType(pframe) != WIFI_DEAUTH && GetFrameSubType(pframe) != WIFI_DISASSOC)
- goto xmitframe_coalesce_fail;
-
- MGMT_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
- pframe += pattrib->pktlen;
-
- /* octent 0 and 1 is key index ,BIP keyid is 4 or 5, LSB only need octent 0 */
- MME[0] = padapter->securitypriv.dot11wBIPKeyid;
- /* copy packet number */
- _rtw_memcpy(&MME[2], &pmlmeext->mgnt_80211w_IPN, 6);
- /* increase the packet number */
- pmlmeext->mgnt_80211w_IPN++;
-
- /* add MME IE with MIC all zero, MME string doesn't include element id and length */
- pframe = rtw_set_ie(pframe, _MME_IE_ , 16 , MME, &(pattrib->pktlen));
- pattrib->last_txcmdsz = pattrib->pktlen;
- /* total frame length - header length */
- frame_body_len = pattrib->pktlen - sizeof(struct rtw_ieee80211_hdr_3addr);
-
- /* conscruct AAD, copy frame control field */
- _rtw_memcpy(BIP_AAD, &pwlanhdr->frame_ctl, 2);
- ClearRetry(BIP_AAD);
- ClearPwrMgt(BIP_AAD);
- ClearMData(BIP_AAD);
- /* conscruct AAD, copy address 1 to address 3 */
- _rtw_memcpy(BIP_AAD + 2, pwlanhdr->addr1, 18);
- /* copy management fram body */
- _rtw_memcpy(BIP_AAD + BIP_AAD_SIZE, MGMT_body, frame_body_len);
-#if 0
- /* dump total packet include MME with zero MIC */
- {
- int i;
- printk("Total packet: ");
- for (i = 0; i < BIP_AAD_SIZE + frame_body_len; i++)
- printk(" %02x ", BIP_AAD[i]);
- printk("\n");
- }
-#endif
- /* calculate mic */
- if (omac1_aes_128(padapter->securitypriv.dot11wBIPKey[padapter->securitypriv.dot11wBIPKeyid].skey
- , BIP_AAD, BIP_AAD_SIZE + frame_body_len, mic))
- goto xmitframe_coalesce_fail;
+ if (subtype == WIFI_ACTION && CATEGORY_IS_GROUP_PRIVACY(category)) {
+ /* broadcast group privacy action frame */
+ #if DBG_MGMT_XMIT_COALESEC_DUMP
+ RTW_INFO(FUNC_ADPT_FMT" broadcast gp action(%u)\n"
+ , FUNC_ADPT_ARG(padapter), category);
+ #endif
-#if 0
- /* dump calculated mic result */
- {
- int i;
- printk("Calculated mic result: ");
- for (i = 0; i < 16; i++)
- printk(" %02x ", mic[i]);
- printk("\n");
- }
-#endif
- /* copy right BIP mic value, total is 128bits, we use the 0~63 bits */
- _rtw_memcpy(pframe - 8, mic, 8);
- /*/dump all packet after mic ok
- {
- int pp;
- printk("pattrib->pktlen = %d\n", pattrib->pktlen);
- for(pp=0;pp< pattrib->pktlen; pp++)
- printk(" %02x ", mem_start[pp]);
- printk("\n");
- }*/
- } else { /* unicast mgmt frame TX */
- /* start to encrypt mgmt frame */
- if (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC ||
- subtype == WIFI_REASSOCREQ || subtype == WIFI_ACTION) {
if (pattrib->psta)
psta = pattrib->psta;
else
- psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra);
-
+ pattrib->psta = psta = rtw_get_bcmc_stainfo(padapter);
if (psta == NULL) {
-
- RTW_INFO("%s, psta==NUL\n", __func__);
+ RTW_INFO(FUNC_ADPT_FMT" broadcast sta == NULL\n"
+ , FUNC_ADPT_ARG(padapter));
goto xmitframe_coalesce_fail;
}
-
- if (pxmitframe->buf_addr == NULL) {
- RTW_INFO("%s, pxmitframe->buf_addr\n", __func__);
+ if (padapter->securitypriv.binstallGrpkey != _TRUE) {
+ RTW_INFO(FUNC_ADPT_FMT" GTK is not installed\n"
+ , FUNC_ADPT_ARG(padapter));
goto xmitframe_coalesce_fail;
}
- /* RTW_INFO("%s, action frame category=%d\n", __func__, pframe[WLAN_HDR_A3_LEN]); */
- /* according 802.11-2012 standard, these five types are not robust types */
- if (subtype == WIFI_ACTION &&
- (pframe[WLAN_HDR_A3_LEN] == RTW_WLAN_CATEGORY_PUBLIC ||
- pframe[WLAN_HDR_A3_LEN] == RTW_WLAN_CATEGORY_HT ||
- pframe[WLAN_HDR_A3_LEN] == RTW_WLAN_CATEGORY_UNPROTECTED_WNM ||
- pframe[WLAN_HDR_A3_LEN] == RTW_WLAN_CATEGORY_SELF_PROTECTED ||
- pframe[WLAN_HDR_A3_LEN] == RTW_WLAN_CATEGORY_P2P))
- goto xmitframe_coalesce_fail;
- /* before encrypt dump the management packet content */
- /*{
- int i;
- printk("Management pkt: ");
- for(i=0; ipktlen; i++)
- printk(" %02x ", pframe[i]);
- printk("=======\n");
- }*/
- if (pattrib->encrypt > 0)
- _rtw_memcpy(pattrib->dot118021x_UncstKey.skey, psta->dot118021x_UncstKey.skey, 16);
-
- /* To use wrong key */
- if (pattrib->key_type == IEEE80211W_WRONG_KEY) {
- RTW_INFO("use wrong key\n");
- pattrib->dot118021x_UncstKey.skey[0] = 0xff;
+ pn = &psta->dot11txpn;
+ kid = padapter->securitypriv.dot118021XGrpKeyid;
+ } else {
+ #ifdef CONFIG_IEEE80211W
+ /* broadcast robust mgmt frame, using BIP */
+ int frame_body_len;
+ u8 mic[16];
+
+ /* IGTK key is not install ex: mesh MFP without IGTK */
+ if (SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) != _TRUE)
+ goto xmitframe_coalesce_success;
+
+ #if DBG_MGMT_XMIT_COALESEC_DUMP
+ if (subtype == WIFI_DEAUTH)
+ RTW_INFO(FUNC_ADPT_FMT" braodcast deauth\n", FUNC_ADPT_ARG(padapter));
+ else if (subtype == WIFI_DISASSOC)
+ RTW_INFO(FUNC_ADPT_FMT" braodcast disassoc\n", FUNC_ADPT_ARG(padapter));
+ else if (subtype == WIFI_ACTION) {
+ RTW_INFO(FUNC_ADPT_FMT" braodcast action(%u)\n"
+ , FUNC_ADPT_ARG(padapter), category);
}
+ #endif
- /* bakeup original management packet */
- _rtw_memcpy(tmp_buf, pframe, pattrib->pktlen);
- /* move to data portion */
- pframe += pattrib->hdrlen;
+ _rtw_memset(MME, 0, _MME_IE_LENGTH_);
- /* 802.11w unicast management packet must be _AES_ */
- pattrib->iv_len = 8;
- /* it's MIC of AES */
- pattrib->icv_len = 8;
+ MGMT_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr);
+ pframe += pattrib->pktlen;
- switch (pattrib->encrypt) {
- case _AES_:
- /* set AES IV header */
- AES_IV(pattrib->iv, psta->dot11wtxpn, 0);
- break;
- default:
- goto xmitframe_coalesce_fail;
- }
- /* insert iv header into management frame */
- _rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len);
- pframe += pattrib->iv_len;
- /* copy mgmt data portion after CCMP header */
- _rtw_memcpy(pframe, tmp_buf + pattrib->hdrlen, pattrib->pktlen - pattrib->hdrlen);
- /* move pframe to end of mgmt pkt */
- pframe += pattrib->pktlen - pattrib->hdrlen;
- /* add 8 bytes CCMP IV header to length */
- pattrib->pktlen += pattrib->iv_len;
-#if 0
- /* dump management packet include AES IV header */
+ /* octent 0 and 1 is key index ,BIP keyid is 4 or 5, LSB only need octent 0 */
+ MME[0] = padapter->securitypriv.dot11wBIPKeyid;
+ /* increase PN and apply to packet */
+ padapter->securitypriv.dot11wBIPtxpn.val++;
+ RTW_PUT_LE64(&MME[2], padapter->securitypriv.dot11wBIPtxpn.val);
+
+ /* add MME IE with MIC all zero, MME string doesn't include element id and length */
+ pframe = rtw_set_ie(pframe, _MME_IE_ , 16 , MME, &(pattrib->pktlen));
+ pattrib->last_txcmdsz = pattrib->pktlen;
+ /* total frame length - header length */
+ frame_body_len = pattrib->pktlen - sizeof(struct rtw_ieee80211_hdr_3addr);
+
+ /* conscruct AAD, copy frame control field */
+ _rtw_memcpy(BIP_AAD, &pwlanhdr->frame_ctl, 2);
+ ClearRetry(BIP_AAD);
+ ClearPwrMgt(BIP_AAD);
+ ClearMData(BIP_AAD);
+ /* conscruct AAD, copy address 1 to address 3 */
+ _rtw_memcpy(BIP_AAD + 2, pwlanhdr->addr1, 18);
+ /* copy management fram body */
+ _rtw_memcpy(BIP_AAD + BIP_AAD_SIZE, MGMT_body, frame_body_len);
+
+ #if DBG_MGMT_XMIT_BIP_DUMP
+ /* dump total packet include MME with zero MIC */
{
int i;
- printk("Management pkt + IV: ");
- /* for(i=0; ipktlen; i++) */
-
- printk("@@@@@@@@@@@@@\n");
+ printk("Total packet: ");
+ for (i = 0; i < BIP_AAD_SIZE + frame_body_len; i++)
+ printk(" %02x ", BIP_AAD[i]);
+ printk("\n");
}
-#endif
+ #endif
- if ((pattrib->icv_len > 0) && (pattrib->bswenc)) {
- _rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len);
- pframe += pattrib->icv_len;
- }
- /* add 8 bytes MIC */
- pattrib->pktlen += pattrib->icv_len;
- /* set final tx command size */
- pattrib->last_txcmdsz = pattrib->pktlen;
+ /* calculate mic */
+ if (omac1_aes_128(padapter->securitypriv.dot11wBIPKey[padapter->securitypriv.dot11wBIPKeyid].skey
+ , BIP_AAD, BIP_AAD_SIZE + frame_body_len, mic))
+ goto xmitframe_coalesce_fail;
- /* set protected bit must be beofre SW encrypt */
- SetPrivacy(mem_start);
-#if 0
- /* dump management packet include AES header */
+ #if DBG_MGMT_XMIT_BIP_DUMP
+ /* dump calculated mic result */
{
int i;
- printk("prepare to enc Management pkt + IV: ");
- for (i = 0; i < pattrib->pktlen; i++)
- printk(" %02x ", mem_start[i]);
- printk("@@@@@@@@@@@@@\n");
+ printk("Calculated mic result: ");
+ for (i = 0; i < 16; i++)
+ printk(" %02x ", mic[i]);
+ printk("\n");
}
-#endif
- /* software encrypt */
- xmitframe_swencrypt(padapter, pxmitframe);
+ #endif
+
+ /* copy right BIP mic value, total is 128bits, we use the 0~63 bits */
+ _rtw_memcpy(pframe - 8, mic, 8);
+
+ #if DBG_MGMT_XMIT_BIP_DUMP
+ /*dump all packet after mic ok */
+ {
+ int pp;
+ printk("pattrib->pktlen = %d\n", pattrib->pktlen);
+ for(pp=0;pp< pattrib->pktlen; pp++)
+ printk(" %02x ", mem_start[pp]);
+ printk("\n");
+ }
+ #endif
+
+ #endif /* CONFIG_IEEE80211W */
+
+ goto xmitframe_coalesce_success;
+ }
+ }
+ else {
+ /* unicast robust mgmt frame */
+ #if DBG_MGMT_XMIT_COALESEC_DUMP
+ if (subtype == WIFI_DEAUTH) {
+ RTW_INFO(FUNC_ADPT_FMT" unicast deauth to "MAC_FMT"\n"
+ , FUNC_ADPT_ARG(padapter), MAC_ARG(pattrib->ra));
+ } else if (subtype == WIFI_DISASSOC) {
+ RTW_INFO(FUNC_ADPT_FMT" unicast disassoc to "MAC_FMT"\n"
+ , FUNC_ADPT_ARG(padapter), MAC_ARG(pattrib->ra));
+ } else if (subtype == WIFI_ACTION) {
+ RTW_INFO(FUNC_ADPT_FMT" unicast action(%u) to "MAC_FMT"\n"
+ , FUNC_ADPT_ARG(padapter), category, MAC_ARG(pattrib->ra));
}
+ #endif
+
+ _rtw_memcpy(pattrib->dot118021x_UncstKey.skey, psta->dot118021x_UncstKey.skey, 16);
+
+ /* To use wrong key */
+ if (pattrib->key_type == IEEE80211W_WRONG_KEY) {
+ RTW_INFO("use wrong key\n");
+ pattrib->dot118021x_UncstKey.skey[0] = 0xff;
+ }
+
+ pn = &psta->dot11txpn;
+ kid = 0;
+ }
+
+ #if DBG_MGMT_XMIT_ENC_DUMP
+ /* before encrypt dump the management packet content */
+ {
+ int i;
+ printk("Management pkt: ");
+ for(i=0; ipktlen; i++)
+ printk(" %02x ", pframe[i]);
+ printk("=======\n");
+ }
+ #endif
+
+ /* bakeup original management packet */
+ _rtw_memcpy(tmp_buf, pframe, pattrib->pktlen);
+ /* move to data portion */
+ pframe += pattrib->hdrlen;
+
+ /* 802.11w encrypted management packet must be _AES_ */
+ if (pattrib->key_type != IEEE80211W_NO_KEY) {
+ pattrib->encrypt = _AES_;
+ pattrib->bswenc = _TRUE;
+ }
+
+ pattrib->iv_len = 8;
+ /* it's MIC of AES */
+ pattrib->icv_len = 8;
+
+ switch (pattrib->encrypt) {
+ case _AES_:
+ /* set AES IV header */
+ AES_IV(pattrib->iv, (*pn), kid);
+ break;
+ default:
+ goto xmitframe_coalesce_fail;
}
+ /* insert iv header into management frame */
+ _rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len);
+ pframe += pattrib->iv_len;
+ /* copy mgmt data portion after CCMP header */
+ _rtw_memcpy(pframe, tmp_buf + pattrib->hdrlen, pattrib->pktlen - pattrib->hdrlen);
+ /* move pframe to end of mgmt pkt */
+ pframe += pattrib->pktlen - pattrib->hdrlen;
+ /* add 8 bytes CCMP IV header to length */
+ pattrib->pktlen += pattrib->iv_len;
+
+ #if DBG_MGMT_XMIT_ENC_DUMP
+ /* dump management packet include AES IV header */
+ {
+ int i;
+ printk("Management pkt + IV: ");
+ /* for(i=0; ipktlen; i++) */
+
+ printk("@@@@@@@@@@@@@\n");
+ }
+ #endif
+
+ if ((pattrib->icv_len > 0) && (pattrib->bswenc)) {
+ _rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len);
+ pframe += pattrib->icv_len;
+ }
+ /* add 8 bytes MIC */
+ pattrib->pktlen += pattrib->icv_len;
+ /* set final tx command size */
+ pattrib->last_txcmdsz = pattrib->pktlen;
+
+ /* set protected bit must be beofre SW encrypt */
+ SetPrivacy(mem_start);
+
+ #if DBG_MGMT_XMIT_ENC_DUMP
+ /* dump management packet include AES header */
+ {
+ int i;
+ printk("prepare to enc Management pkt + IV: ");
+ for (i = 0; i < pattrib->pktlen; i++)
+ printk(" %02x ", mem_start[i]);
+ printk("@@@@@@@@@@@@@\n");
+ }
+ #endif
+
+ /* software encrypt */
+ xmitframe_swencrypt(padapter, pxmitframe);
+
xmitframe_coalesce_success:
_exit_critical_bh(&padapter->security_key_mutex, &irqL);
rtw_mfree(BIP_AAD, ori_len);
- _func_exit_;
return _SUCCESS;
xmitframe_coalesce_fail:
_exit_critical_bh(&padapter->security_key_mutex, &irqL);
rtw_mfree(BIP_AAD, ori_len);
- _func_exit_;
return _FAIL;
}
-#endif /* CONFIG_IEEE80211W */
+#endif /* defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH) */
/* Logical Link Control(LLC) SubNetwork Attachment Point(SNAP) header
* IEEE LLC/SNAP header contains 8 octets
@@ -2615,7 +3073,6 @@ s32 rtw_put_snap(u8 *data, u16 h_proto)
struct ieee80211_snap_hdr *snap;
u8 *oui;
- _func_enter_;
snap = (struct ieee80211_snap_hdr *)data;
snap->dsap = 0xaa;
@@ -2633,7 +3090,6 @@ s32 rtw_put_snap(u8 *data, u16 h_proto)
*(u16 *)(data + SNAP_SIZE) = htons(h_proto);
- _func_exit_;
return SNAP_SIZE + sizeof(u16);
}
@@ -2647,7 +3103,6 @@ void rtw_update_protection(_adapter *padapter, u8 *ie, uint ie_len)
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
struct registry_priv *pregistrypriv = &padapter->registrypriv;
- _func_enter_;
switch (pxmitpriv->vcs_setting) {
case DISABLE_VCS:
@@ -2677,7 +3132,6 @@ void rtw_update_protection(_adapter *padapter, u8 *ie, uint ie_len)
}
- _func_exit_;
}
@@ -2706,13 +3160,6 @@ void rtw_count_tx_stats(PADAPTER padapter, struct xmit_frame *pxmitframe, int sz
pstats->tx_pkts += pkt_num;
pstats->tx_bytes += sz;
-#ifdef CONFIG_TDLS
- if (pxmitframe->attrib.ptdls_sta != NULL) {
- pstats = &(pxmitframe->attrib.ptdls_sta->sta_stats);
- pstats->tx_pkts += pkt_num;
- pstats->tx_bytes += sz;
- }
-#endif /* CONFIG_TDLS */
}
#ifdef CONFIG_CHECK_LEAVE_LPS
@@ -2727,7 +3174,6 @@ static struct xmit_buf *__rtw_alloc_cmd_xmitbuf(struct xmit_priv *pxmitpriv,
{
struct xmit_buf *pxmitbuf = NULL;
- _func_enter_;
pxmitbuf = &pxmitpriv->pcmd_xmitbuf[buf_type];
if (pxmitbuf != NULL) {
@@ -2757,7 +3203,6 @@ static struct xmit_buf *__rtw_alloc_cmd_xmitbuf(struct xmit_priv *pxmitpriv,
exit:
- _func_exit_;
return pxmitbuf;
}
@@ -2787,6 +3232,9 @@ struct xmit_frame *__rtw_alloc_cmdxmitframe(struct xmit_priv *pxmitpriv,
pcmdframe->buf_addr = pxmitbuf->pbuf;
+ /* initial memory to zero */
+ _rtw_memset(pcmdframe->buf_addr, 0, MAX_CMDBUF_SZ);
+
pxmitbuf->priv_data = pcmdframe;
return pcmdframe;
@@ -2800,7 +3248,6 @@ struct xmit_buf *rtw_alloc_xmitbuf_ext(struct xmit_priv *pxmitpriv)
_list *plist, *phead;
_queue *pfree_queue = &pxmitpriv->free_xmit_extbuf_queue;
- _func_enter_;
_enter_critical(&pfree_queue->lock, &irqL);
@@ -2849,7 +3296,6 @@ struct xmit_buf *rtw_alloc_xmitbuf_ext(struct xmit_priv *pxmitpriv)
_exit_critical(&pfree_queue->lock, &irqL);
- _func_exit_;
return pxmitbuf;
}
@@ -2859,7 +3305,6 @@ s32 rtw_free_xmitbuf_ext(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf)
_irqL irqL;
_queue *pfree_queue = &pxmitpriv->free_xmit_extbuf_queue;
- _func_enter_;
if (pxmitbuf == NULL)
return _FAIL;
@@ -2876,7 +3321,6 @@ s32 rtw_free_xmitbuf_ext(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf)
_exit_critical(&pfree_queue->lock, &irqL);
- _func_exit_;
return _SUCCESS;
}
@@ -2888,7 +3332,6 @@ struct xmit_buf *rtw_alloc_xmitbuf(struct xmit_priv *pxmitpriv)
_list *plist, *phead;
_queue *pfree_xmitbuf_queue = &pxmitpriv->free_xmitbuf_queue;
- _func_enter_;
/* RTW_INFO("+rtw_alloc_xmitbuf\n"); */
@@ -2943,7 +3386,6 @@ struct xmit_buf *rtw_alloc_xmitbuf(struct xmit_priv *pxmitpriv)
_exit_critical(&pfree_xmitbuf_queue->lock, &irqL);
- _func_exit_;
return pxmitbuf;
}
@@ -2953,7 +3395,6 @@ s32 rtw_free_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf)
_irqL irqL;
_queue *pfree_xmitbuf_queue = &pxmitpriv->free_xmitbuf_queue;
- _func_enter_;
/* RTW_INFO("+rtw_free_xmitbuf\n"); */
@@ -2983,7 +3424,6 @@ s32 rtw_free_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf)
_exit_critical(&pfree_xmitbuf_queue->lock, &irqL);
}
- _func_exit_;
return _SUCCESS;
}
@@ -3049,12 +3489,10 @@ struct xmit_frame *rtw_alloc_xmitframe(struct xmit_priv *pxmitpriv)/* (_queue *p
_list *plist, *phead;
_queue *pfree_xmit_queue = &pxmitpriv->free_xmit_queue;
- _func_enter_;
_enter_critical_bh(&pfree_xmit_queue->lock, &irqL);
if (_rtw_queue_empty(pfree_xmit_queue) == _TRUE) {
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("rtw_alloc_xmitframe:%d\n", pxmitpriv->free_xmitframe_cnt));
pxframe = NULL;
} else {
phead = get_list_head(pfree_xmit_queue);
@@ -3065,14 +3503,12 @@ struct xmit_frame *rtw_alloc_xmitframe(struct xmit_priv *pxmitpriv)/* (_queue *p
rtw_list_delete(&(pxframe->list));
pxmitpriv->free_xmitframe_cnt--;
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("rtw_alloc_xmitframe():free_xmitframe_cnt=%d\n", pxmitpriv->free_xmitframe_cnt));
}
_exit_critical_bh(&pfree_xmit_queue->lock, &irqL);
rtw_init_xmitframe(pxframe);
- _func_exit_;
return pxframe;
}
@@ -3084,12 +3520,10 @@ struct xmit_frame *rtw_alloc_xmitframe_ext(struct xmit_priv *pxmitpriv)
_list *plist, *phead;
_queue *queue = &pxmitpriv->free_xframe_ext_queue;
- _func_enter_;
_enter_critical_bh(&queue->lock, &irqL);
if (_rtw_queue_empty(queue) == _TRUE) {
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("rtw_alloc_xmitframe_ext:%d\n", pxmitpriv->free_xframe_ext_cnt));
pxframe = NULL;
} else {
phead = get_list_head(queue);
@@ -3098,14 +3532,12 @@ struct xmit_frame *rtw_alloc_xmitframe_ext(struct xmit_priv *pxmitpriv)
rtw_list_delete(&(pxframe->list));
pxmitpriv->free_xframe_ext_cnt--;
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("rtw_alloc_xmitframe_ext():free_xmitframe_cnt=%d\n", pxmitpriv->free_xframe_ext_cnt));
}
_exit_critical_bh(&queue->lock, &irqL);
rtw_init_xmitframe(pxframe);
- _func_exit_;
return pxframe;
}
@@ -3146,10 +3578,8 @@ s32 rtw_free_xmitframe(struct xmit_priv *pxmitpriv, struct xmit_frame *pxmitfram
_adapter *padapter = pxmitpriv->adapter;
_pkt *pndis_pkt = NULL;
- _func_enter_;
if (pxmitframe == NULL) {
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("======rtw_free_xmitframe():pxmitframe==NULL!!!!!!!!!!\n"));
goto exit;
}
@@ -3177,10 +3607,8 @@ s32 rtw_free_xmitframe(struct xmit_priv *pxmitpriv, struct xmit_frame *pxmitfram
rtw_list_insert_tail(&pxmitframe->list, get_list_head(queue));
if (pxmitframe->ext_tag == 0) {
pxmitpriv->free_xmitframe_cnt++;
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_debug_, ("rtw_free_xmitframe():free_xmitframe_cnt=%d\n", pxmitpriv->free_xmitframe_cnt));
} else if (pxmitframe->ext_tag == 1) {
pxmitpriv->free_xframe_ext_cnt++;
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_debug_, ("rtw_free_xmitframe():free_xframe_ext_cnt=%d\n", pxmitpriv->free_xframe_ext_cnt));
} else {
}
@@ -3193,7 +3621,6 @@ s32 rtw_free_xmitframe(struct xmit_priv *pxmitpriv, struct xmit_frame *pxmitfram
exit:
- _func_exit_;
return _SUCCESS;
}
@@ -3204,7 +3631,6 @@ void rtw_free_xmitframe_queue(struct xmit_priv *pxmitpriv, _queue *pframequeue)
_list *plist, *phead;
struct xmit_frame *pxmitframe;
- _func_enter_;
_enter_critical_bh(&(pframequeue->lock), &irqL);
@@ -3222,15 +3648,12 @@ void rtw_free_xmitframe_queue(struct xmit_priv *pxmitpriv, _queue *pframequeue)
}
_exit_critical_bh(&(pframequeue->lock), &irqL);
- _func_exit_;
}
s32 rtw_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe)
{
DBG_COUNTER(padapter->tx_logs.core_tx_enqueue);
if (rtw_xmit_classifier(padapter, pxmitframe) == _FAIL) {
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_,
- ("rtw_xmitframe_enqueue: drop xmit pkt for classifier fail\n"));
/* pxmitframe->pkt = NULL; */
return _FAIL;
}
@@ -3315,8 +3738,6 @@ struct xmit_frame *rtw_get_xframe(struct xmit_priv *pxmitpriv, int *num_frame)
/* int j, tmp, acirp_cnt[4]; */
#endif
- _func_enter_;
-
inx[0] = 0;
inx[1] = 1;
inx[2] = 2;
@@ -3356,8 +3777,6 @@ struct xmit_frame *rtw_get_xframe(struct xmit_priv *pxmitpriv, int *num_frame)
_exit_critical_bh(&pxmitpriv->lock, &irqL0);
- _func_exit_;
-
return pxmitframe;
}
@@ -3377,7 +3796,6 @@ struct xmit_frame *rtw_dequeue_xframe(struct xmit_priv *pxmitpriv, struct hw_xmi
/* int j, tmp, acirp_cnt[4]; */
#endif
- _func_enter_;
inx[0] = 0;
inx[1] = 1;
@@ -3442,8 +3860,6 @@ struct xmit_frame *rtw_dequeue_xframe(struct xmit_priv *pxmitpriv, struct hw_xmi
_exit_critical_bh(&pxmitpriv->lock, &irqL0);
- _func_exit_;
-
return pxmitframe;
}
@@ -3452,28 +3868,24 @@ struct tx_servq *rtw_get_sta_pending(_adapter *padapter, struct sta_info *psta,
{
struct tx_servq *ptxservq = NULL;
- _func_enter_;
switch (up) {
case 1:
case 2:
ptxservq = &(psta->sta_xmitpriv.bk_q);
*(ac) = 3;
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("rtw_get_sta_pending : BK\n"));
break;
case 4:
case 5:
ptxservq = &(psta->sta_xmitpriv.vi_q);
*(ac) = 1;
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("rtw_get_sta_pending : VI\n"));
break;
case 6:
case 7:
ptxservq = &(psta->sta_xmitpriv.vo_q);
*(ac) = 0;
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("rtw_get_sta_pending : VO\n"));
break;
case 0:
@@ -3481,12 +3893,10 @@ struct tx_servq *rtw_get_sta_pending(_adapter *padapter, struct sta_info *psta,
default:
ptxservq = &(psta->sta_xmitpriv.be_q);
*(ac) = 2;
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("rtw_get_sta_pending : BE\n"));
break;
}
- _func_exit_;
return ptxservq;
}
@@ -3497,11 +3907,10 @@ __inline static struct tx_servq *rtw_get_sta_pending
struct tx_servq *ptxservq;
struct hw_xmit *phwxmits = padapter->xmitpriv.hwxmits;
- _func_enter_;
#ifdef CONFIG_RTL8711
- if (IS_MCAST(psta->hwaddr)) {
+ if (IS_MCAST(psta->cmn.mac_addr)) {
ptxservq = &(psta->sta_xmitpriv.be_q); /* we will use be_q to queue bc/mc frames in BCMC_stainfo */
*ppstapending = &padapter->xmitpriv.bm_pending;
} else
@@ -3513,7 +3922,6 @@ __inline static struct tx_servq *rtw_get_sta_pending
ptxservq = &(psta->sta_xmitpriv.bk_q);
*ppstapending = &padapter->xmitpriv.bk_pending;
(phwxmits + 3)->accnt++;
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("rtw_get_sta_pending : BK\n"));
break;
case 4:
@@ -3521,7 +3929,6 @@ __inline static struct tx_servq *rtw_get_sta_pending
ptxservq = &(psta->sta_xmitpriv.vi_q);
*ppstapending = &padapter->xmitpriv.vi_pending;
(phwxmits + 1)->accnt++;
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("rtw_get_sta_pending : VI\n"));
break;
case 6:
@@ -3529,7 +3936,6 @@ __inline static struct tx_servq *rtw_get_sta_pending
ptxservq = &(psta->sta_xmitpriv.vo_q);
*ppstapending = &padapter->xmitpriv.vo_pending;
(phwxmits + 0)->accnt++;
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("rtw_get_sta_pending : VO\n"));
break;
case 0:
@@ -3538,14 +3944,12 @@ __inline static struct tx_servq *rtw_get_sta_pending
ptxservq = &(psta->sta_xmitpriv.be_q);
*ppstapending = &padapter->xmitpriv.be_pending;
(phwxmits + 2)->accnt++;
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("rtw_get_sta_pending : BE\n"));
break;
}
}
- _func_exit_;
return ptxservq;
}
@@ -3566,7 +3970,6 @@ s32 rtw_xmit_classifier(_adapter *padapter, struct xmit_frame *pxmitframe)
struct hw_xmit *phwxmits = padapter->xmitpriv.hwxmits;
sint res = _SUCCESS;
- _func_enter_;
DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class);
@@ -3590,7 +3993,6 @@ s32 rtw_xmit_classifier(_adapter *padapter, struct xmit_frame *pxmitframe)
DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class_err_nosta);
res = _FAIL;
RTW_INFO("rtw_xmit_classifier: psta == NULL\n");
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("rtw_xmit_classifier: psta == NULL\n"));
goto exit;
}
@@ -3619,7 +4021,6 @@ s32 rtw_xmit_classifier(_adapter *padapter, struct xmit_frame *pxmitframe)
exit:
- _func_exit_;
return res;
}
@@ -3701,14 +4102,12 @@ void rtw_free_hwxmits(_adapter *padapter)
void rtw_init_hwxmits(struct hw_xmit *phwxmit, sint entry)
{
sint i;
- _func_enter_;
for (i = 0; i < entry; i++, phwxmit++) {
/* _rtw_spinlock_init(&phwxmit->xmit_lock); */
/* _rtw_init_listhead(&phwxmit->pending); */
/* phwxmit->txcmdcnt = 0; */
phwxmit->accnt = 0;
}
- _func_exit_;
}
#ifdef CONFIG_BR_EXT
@@ -3934,12 +4333,6 @@ static void do_queue_select(_adapter *padapter, struct pkt_attrib *pattrib)
u8 qsel;
qsel = pattrib->priority;
- RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("### do_queue_select priority=%d ,qsel = %d\n", pattrib->priority , qsel));
-
-#ifdef CONFIG_CONCURRENT_MODE
- /* if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE)
- * qsel = 7; */
-#endif
#ifdef CONFIG_MCC_MODE
if (MCC_EN(padapter)) {
@@ -3970,20 +4363,21 @@ static void do_queue_select(_adapter *padapter, struct pkt_attrib *pattrib)
* 0 success, hardware will handle this xmit frame(packet)
* <0 fail
*/
+ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))
s32 rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev)
{
- int ret = 0;
- int rtap_len;
- int qos_len = 0;
- int dot11_hdr_len = 24;
- int snap_len = 6;
- unsigned char *pdata;
u16 frame_ctl;
- unsigned char src_mac_addr[6];
- unsigned char dst_mac_addr[6];
- struct rtw_ieee80211_hdr *dot11_hdr;
- struct ieee80211_radiotap_header *rtap_hdr;
+ struct ieee80211_radiotap_header rtap_hdr;
_adapter *padapter = (_adapter *)rtw_netdev_priv(ndev);
+ struct pkt_file pktfile;
+ struct rtw_ieee80211_hdr *pwlanhdr;
+ struct pkt_attrib *pattrib;
+ struct xmit_frame *pmgntframe;
+ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
+ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
+ unsigned char *pframe;
+ u8 dummybuf[32];
+ int len = skb->len, rtap_len;
if (skb)
rtw_mstat_update(MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, skb->truesize);
@@ -3991,11 +4385,12 @@ s32 rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev)
if (unlikely(skb->len < sizeof(struct ieee80211_radiotap_header)))
goto fail;
- rtap_hdr = (struct ieee80211_radiotap_header *)skb->data;
- if (unlikely(rtap_hdr->it_version))
+ _rtw_open_pktfile((_pkt *)skb, &pktfile);
+ _rtw_pktfile_read(&pktfile, (u8 *)(&rtap_hdr), sizeof(struct ieee80211_radiotap_header));
+ rtap_len = ieee80211_get_radiotap_len((u8 *)(&rtap_hdr));
+ if (unlikely(rtap_hdr.it_version))
goto fail;
- rtap_len = ieee80211_get_radiotap_len(skb->data);
if (unlikely(skb->len < rtap_len))
goto fail;
@@ -4003,102 +4398,112 @@ s32 rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev)
RTW_INFO("radiotap len (should be 14): %d\n", rtap_len);
goto fail;
}
+ _rtw_pktfile_read(&pktfile, dummybuf, rtap_len-sizeof(struct ieee80211_radiotap_header));
+ len = len - rtap_len;
- /* Skip the ratio tap header */
- skb_pull(skb, rtap_len);
+ pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+ if (pmgntframe == NULL) {
+ rtw_udelay_os(500);
+ goto fail;
+ }
+
+ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+// _rtw_memcpy(pframe, (void *)checking, len);
+ _rtw_pktfile_read(&pktfile, pframe, len);
- dot11_hdr = (struct rtw_ieee80211_hdr *)skb->data;
- frame_ctl = le16_to_cpu(dot11_hdr->frame_ctl);
- /* Check if the QoS bit is set */
+ /* Check DATA/MGNT frames */
+ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+ frame_ctl = le16_to_cpu(pwlanhdr->frame_ctl);
if ((frame_ctl & RTW_IEEE80211_FCTL_FTYPE) == RTW_IEEE80211_FTYPE_DATA) {
- struct xmit_frame *pmgntframe;
- struct pkt_attrib *pattrib;
- unsigned char *pframe;
- struct rtw_ieee80211_hdr *pwlanhdr;
- struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
- struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
- u8 *buf = skb->data;
- u32 len = skb->len;
- u8 category, action;
- int type = -1;
-
- pmgntframe = alloc_mgtxmitframe(pxmitpriv);
- if (pmgntframe == NULL) {
- rtw_udelay_os(500);
- goto fail;
- }
pattrib = &pmgntframe->attrib;
-
update_monitor_frame_attrib(padapter, pattrib);
- pattrib->retry_ctrl = _FALSE;
-
- _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
-
- pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
-
- _rtw_memcpy(pframe, (void *)buf, len);
-
- pattrib->pktlen = len;
-
- pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
-
if (is_broadcast_mac_addr(pwlanhdr->addr3) || is_broadcast_mac_addr(pwlanhdr->addr1))
pattrib->rate = MGN_24M;
- pmlmeext->mgnt_seq = GetSequence(pwlanhdr);
- pattrib->seqnum = pmlmeext->mgnt_seq;
- pmlmeext->mgnt_seq++;
-
- pattrib->last_txcmdsz = pattrib->pktlen;
-
- dump_mgntframe(padapter, pmgntframe);
-
} else {
- struct xmit_frame *pmgntframe;
- struct pkt_attrib *pattrib;
- unsigned char *pframe;
- struct rtw_ieee80211_hdr *pwlanhdr;
- struct xmit_priv *pxmitpriv = &(padapter->xmitpriv);
- struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
- u8 *buf = skb->data;
- u32 len = skb->len;
- u8 category, action;
- int type = -1;
-
- pmgntframe = alloc_mgtxmitframe(pxmitpriv);
- if (pmgntframe == NULL)
- goto fail;
pattrib = &pmgntframe->attrib;
update_mgntframe_attrib(padapter, pattrib);
- pattrib->retry_ctrl = _FALSE;
- _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET);
+ }
+ pattrib->retry_ctrl = _FALSE;
+ pattrib->pktlen = len;
+ pmlmeext->mgnt_seq = GetSequence(pwlanhdr);
+ pattrib->seqnum = pmlmeext->mgnt_seq;
+ pmlmeext->mgnt_seq++;
+ pattrib->last_txcmdsz = pattrib->pktlen;
- pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
+ dump_mgntframe(padapter, pmgntframe);
- _rtw_memcpy(pframe, (void *)buf, len);
+fail:
+ rtw_endofpktfile(&pktfile);
+ rtw_skb_free(skb);
+ return 0;
+}
+#endif
- pattrib->pktlen = len;
+/*
+ * The main transmit(tx) entry post handle
+ *
+ * Return
+ * 1 enqueue
+ * 0 success, hardware will handle this xmit frame(packet)
+ * <0 fail
+ */
+s32 rtw_xmit_posthandle(_adapter *padapter, struct xmit_frame *pxmitframe, _pkt *pkt)
+{
+#ifdef CONFIG_AP_MODE
+ _irqL irqL0;
+#endif
+ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+ s32 res;
- pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+ res = update_attrib(padapter, pkt, &pxmitframe->attrib);
- pmlmeext->mgnt_seq = GetSequence(pwlanhdr);
- pattrib->seqnum = pmlmeext->mgnt_seq;
- pmlmeext->mgnt_seq++;
+#ifdef CONFIG_MCC_MODE
+ /* record data kernel TX to driver to check MCC concurrent TX */
+ rtw_hal_mcc_calc_tx_bytes_from_kernel(padapter, pxmitframe->attrib.pktlen);
+#endif /* CONFIG_MCC_MODE */
- pattrib->last_txcmdsz = pattrib->pktlen;
+#ifdef CONFIG_WAPI_SUPPORT
+ if (pxmitframe->attrib.ether_type != 0x88B4) {
+ if (rtw_wapi_drop_for_key_absent(padapter, pxmitframe->attrib.ra)) {
+ WAPI_TRACE(WAPI_RX, "drop for key absend when tx\n");
+ res = _FAIL;
+ }
+ }
+#endif
+ if (res == _FAIL) {
+ /*RTW_INFO("%s-"ADPT_FMT" update attrib fail\n", __func__, ADPT_ARG(padapter));*/
+#ifdef DBG_TX_DROP_FRAME
+ RTW_INFO("DBG_TX_DROP_FRAME %s update attrib fail\n", __FUNCTION__);
+#endif
+ rtw_free_xmitframe(pxmitpriv, pxmitframe);
+ return -1;
+ }
+ pxmitframe->pkt = pkt;
- dump_mgntframe(padapter, pmgntframe);
+ rtw_led_tx_control(padapter, pxmitframe->attrib.dst);
- }
+ do_queue_select(padapter, &pxmitframe->attrib);
-fail:
+#ifdef CONFIG_AP_MODE
+ _enter_critical_bh(&pxmitpriv->lock, &irqL0);
+ if (xmitframe_enqueue_for_sleeping_sta(padapter, pxmitframe) == _TRUE) {
+ _exit_critical_bh(&pxmitpriv->lock, &irqL0);
+ DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue);
+ return 1;
+ }
+ _exit_critical_bh(&pxmitpriv->lock, &irqL0);
+#endif
- rtw_skb_free(skb);
+ /* pre_xmitframe */
+ if (rtw_hal_xmit(padapter, pxmitframe) == _FALSE)
+ return 1;
return 0;
}
@@ -4113,22 +4518,20 @@ s32 rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev)
*/
s32 rtw_xmit(_adapter *padapter, _pkt **ppkt)
{
- static u32 start = 0;
+ static systime start = 0;
static u32 drop_cnt = 0;
-#ifdef CONFIG_AP_MODE
- _irqL irqL0;
-#endif
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
struct xmit_frame *pxmitframe = NULL;
-#ifdef CONFIG_BR_EXT
- struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
- void *br_port = NULL;
-#endif /* CONFIG_BR_EXT */
-
s32 res;
DBG_COUNTER(padapter->tx_logs.core_tx);
+ if (IS_CH_WAITING(adapter_to_rfctl(padapter)))
+ return -1;
+
+ if (rtw_linked_check(padapter) == _FALSE)
+ return -1;
+
if (start == 0)
start = rtw_get_current_time();
@@ -4149,70 +4552,72 @@ s32 rtw_xmit(_adapter *padapter, _pkt **ppkt)
}
#ifdef CONFIG_BR_EXT
+ if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE) == _TRUE) {
+ void *br_port = NULL;
-#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
- br_port = padapter->pnetdev->br_port;
-#else /* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */
- rcu_read_lock();
- br_port = rcu_dereference(padapter->pnetdev->rx_handler_data);
- rcu_read_unlock();
-#endif /* (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) */
+ #if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
+ br_port = padapter->pnetdev->br_port;
+ #else
+ rcu_read_lock();
+ br_port = rcu_dereference(padapter->pnetdev->rx_handler_data);
+ rcu_read_unlock();
+ #endif
- if (br_port && check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE) == _TRUE) {
- res = rtw_br_client_tx(padapter, ppkt);
- if (res == -1) {
- rtw_free_xmitframe(pxmitpriv, pxmitframe);
- DBG_COUNTER(padapter->tx_logs.core_tx_err_brtx);
- return -1;
+ if (br_port) {
+ res = rtw_br_client_tx(padapter, ppkt);
+ if (res == -1) {
+ rtw_free_xmitframe(pxmitpriv, pxmitframe);
+ DBG_COUNTER(padapter->tx_logs.core_tx_err_brtx);
+ return -1;
+ }
}
}
-
#endif /* CONFIG_BR_EXT */
- res = update_attrib(padapter, *ppkt, &pxmitframe->attrib);
+#ifdef CONFIG_RTW_MESH
+ if (MLME_IS_MESH(padapter)) {
+ _list b2u_list;
-#ifdef CONFIG_MCC_MODE
- /* record data kernel TX to driver to check MCC concurrent TX */
- rtw_hal_mcc_calc_tx_bytes_from_kernel(padapter, pxmitframe->attrib.pktlen);
-#endif /* CONFIG_MCC_MODE */
-
-#ifdef CONFIG_WAPI_SUPPORT
- if (pxmitframe->attrib.ether_type != 0x88B4) {
- if (rtw_wapi_drop_for_key_absent(padapter, pxmitframe->attrib.ra)) {
- WAPI_TRACE(WAPI_RX, "drop for key absend when tx\n");
- res = _FAIL;
- }
- }
-#endif
- if (res == _FAIL) {
- /*RTW_INFO("%s-"ADPT_FMT" update attrib fail\n", __func__, ADPT_ARG(padapter));*/
-#ifdef DBG_TX_DROP_FRAME
- RTW_INFO("DBG_TX_DROP_FRAME %s update attrib fail\n", __FUNCTION__);
-#endif
- rtw_free_xmitframe(pxmitpriv, pxmitframe);
- return -1;
- }
- pxmitframe->pkt = *ppkt;
+ res = rtw_mesh_addr_resolve(padapter, pxmitframe, *ppkt, &b2u_list);
+ if (res == RTW_RA_RESOLVING)
+ return 1;
+ if (res == _FAIL)
+ return -1;
- rtw_led_control(padapter, LED_CTL_TX);
+ #if CONFIG_RTW_MESH_DATA_BMC_TO_UC
+ if (!rtw_is_list_empty(&b2u_list)) {
+ _list *list = get_next(&b2u_list);
+ struct xmit_frame *b2uframe;
+
+ while ((rtw_end_of_queue_search(&b2u_list, list)) == _FALSE) {
+ b2uframe = LIST_CONTAINOR(list, struct xmit_frame, list);
+ list = get_next(list);
+ rtw_list_delete(&b2uframe->list);
+
+ b2uframe->pkt = rtw_os_pkt_copy(*ppkt);
+ if (!b2uframe->pkt) {
+ if (res == RTW_BMC_NO_NEED)
+ res = _SUCCESS;
+ rtw_free_xmitframe(pxmitpriv, b2uframe);
+ continue;
+ }
- do_queue_select(padapter, &pxmitframe->attrib);
+ rtw_xmit_posthandle(padapter, b2uframe, b2uframe->pkt);
+ }
+ }
+ #endif /* CONFIG_RTW_MESH_DATA_BMC_TO_UC */
-#ifdef CONFIG_AP_MODE
- _enter_critical_bh(&pxmitpriv->lock, &irqL0);
- if (xmitframe_enqueue_for_sleeping_sta(padapter, pxmitframe) == _TRUE) {
- _exit_critical_bh(&pxmitpriv->lock, &irqL0);
- DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue);
- return 1;
+ if (res == RTW_BMC_NO_NEED) {
+ rtw_free_xmitframe(&padapter->xmitpriv, pxmitframe);
+ return 0;
+ }
}
- _exit_critical_bh(&pxmitpriv->lock, &irqL0);
-#endif
+#endif /* CONFIG_RTW_MESH */
- /* pre_xmitframe */
- if (rtw_hal_xmit(padapter, pxmitframe) == _FALSE)
- return 1;
+ pxmitframe->pkt = NULL; /* let rtw_xmit_posthandle not to free pkt inside */
+ res = rtw_xmit_posthandle(padapter, pxmitframe, *ppkt);
- return 0;
+ return res;
}
#ifdef CONFIG_TDLS
@@ -4272,7 +4677,7 @@ sint xmitframe_enqueue_for_tdls_sleeping_sta(_adapter *padapter, struct xmit_fra
/* Transmit TDLS PTI via AP */
if (ptdls_sta->sleepq_len == 1)
- rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_ISSUE_PTI);
+ rtw_tdls_cmd(padapter, ptdls_sta->cmn.mac_addr, TDLS_ISSUE_PTI);
ret = _TRUE;
}
@@ -4295,32 +4700,31 @@ inline bool xmitframe_hiq_filter(struct xmit_frame *xmitframe)
_adapter *adapter = xmitframe->padapter;
struct registry_priv *registry = &adapter->registrypriv;
- if (rtw_get_intf_type(adapter) != RTW_PCIE) {
-
- if (adapter->registrypriv.wifi_spec == 1)
- allow = _TRUE;
- else if (registry->hiq_filter == RTW_HIQ_FILTER_ALLOW_SPECIAL) {
+ if (adapter->registrypriv.wifi_spec == 1)
+ allow = _TRUE;
+ else if (registry->hiq_filter == RTW_HIQ_FILTER_ALLOW_SPECIAL) {
- struct pkt_attrib *attrib = &xmitframe->attrib;
+ struct pkt_attrib *attrib = &xmitframe->attrib;
- if (attrib->ether_type == 0x0806
- || attrib->ether_type == 0x888e
+ if (attrib->ether_type == 0x0806
+ || attrib->ether_type == 0x888e
#ifdef CONFIG_WAPI_SUPPORT
- || attrib->ether_type == 0x88B4
+ || attrib->ether_type == 0x88B4
#endif
- || attrib->dhcp_pkt
- ) {
- if (0)
- RTW_INFO(FUNC_ADPT_FMT" ether_type:0x%04x%s\n", FUNC_ADPT_ARG(xmitframe->padapter)
- , attrib->ether_type, attrib->dhcp_pkt ? " DHCP" : "");
- allow = _TRUE;
- }
- } else if (registry->hiq_filter == RTW_HIQ_FILTER_ALLOW_ALL)
+ || attrib->dhcp_pkt
+ ) {
+ if (0)
+ RTW_INFO(FUNC_ADPT_FMT" ether_type:0x%04x%s\n", FUNC_ADPT_ARG(xmitframe->padapter)
+ , attrib->ether_type, attrib->dhcp_pkt ? " DHCP" : "");
allow = _TRUE;
- else if (registry->hiq_filter == RTW_HIQ_FILTER_DENY_ALL) {
- } else
- rtw_warn_on(1);
- }
+ }
+ } else if (registry->hiq_filter == RTW_HIQ_FILTER_ALLOW_ALL)
+ allow = _TRUE;
+ else if (registry->hiq_filter == RTW_HIQ_FILTER_DENY_ALL)
+ allow = _FALSE;
+ else
+ rtw_warn_on(1);
+
return allow;
}
@@ -4342,7 +4746,7 @@ sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *p
ret = xmitframe_enqueue_for_tdls_sleeping_sta(padapter, pxmitframe);
#endif /* CONFIG_TDLS */
- if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _FALSE) {
+ if (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter)) {
DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_warn_fwstate);
return ret;
}
@@ -4391,7 +4795,7 @@ sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *p
if (bmcst) {
_enter_critical_bh(&psta->sleep_q.lock, &irqL);
- if (pstapriv->sta_dz_bitmap) { /* if anyone sta is in ps mode */
+ if (rtw_tim_map_anyone_be_set(padapter, pstapriv->sta_dz_bitmap)) { /* if anyone sta is in ps mode */
/* pattrib->qsel = QSLT_HIGH; */ /* HIQ */
rtw_list_delete(&pxmitframe->list);
@@ -4402,13 +4806,14 @@ sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *p
psta->sleepq_len++;
- if (!(pstapriv->tim_bitmap & BIT(0)))
+ if (!(rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0)))
update_tim = _TRUE;
- pstapriv->tim_bitmap |= BIT(0);
- pstapriv->sta_dz_bitmap |= BIT(0);
+ rtw_tim_map_set(padapter, pstapriv->tim_bitmap, 0);
+ rtw_tim_map_set(padapter, pstapriv->sta_dz_bitmap, 0);
- /* RTW_INFO("enqueue, sq_len=%d, tim=%x\n", psta->sleepq_len, pstapriv->tim_bitmap); */
+ /* RTW_INFO("enqueue, sq_len=%d\n", psta->sleepq_len); */
+ /* RTW_INFO_DUMP("enqueue, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */
if (update_tim == _TRUE) {
if (is_broadcast_mac_addr(pattrib->ra))
_update_beacon(padapter, _TIM_IE_, NULL, _TRUE, "buffer BC");
@@ -4422,7 +4827,6 @@ sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *p
ret = _TRUE;
DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_mcast);
-
}
_exit_critical_bh(&psta->sleep_q.lock, &irqL);
@@ -4437,7 +4841,7 @@ sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *p
if (psta->state & WIFI_SLEEP_STATE) {
u8 wmmps_ac = 0;
- if (pstapriv->sta_dz_bitmap & BIT(psta->aid)) {
+ if (rtw_tim_map_is_set(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid)) {
rtw_list_delete(&pxmitframe->list);
/* _enter_critical_bh(&psta->sleep_q.lock, &irqL); */
@@ -4470,12 +4874,13 @@ sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *p
psta->sleepq_ac_len++;
if (((psta->has_legacy_ac) && (!wmmps_ac)) || ((!psta->has_legacy_ac) && (wmmps_ac))) {
- if (!(pstapriv->tim_bitmap & BIT(psta->aid)))
+ if (!(rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid)))
update_tim = _TRUE;
- pstapriv->tim_bitmap |= BIT(psta->aid);
+ rtw_tim_map_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid);
- /* RTW_INFO("enqueue, sq_len=%d, tim=%x\n", psta->sleepq_len, pstapriv->tim_bitmap); */
+ /* RTW_INFO("enqueue, sq_len=%d\n", psta->sleepq_len); */
+ /* RTW_INFO_DUMP("enqueue, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */
if (update_tim == _TRUE) {
/* RTW_INFO("sleepq_len==1, update BCNTIM\n"); */
@@ -4562,22 +4967,14 @@ void stop_sta_xmit(_adapter *padapter, struct sta_info *psta)
#ifdef CONFIG_TDLS
if (!(psta->tdls_sta_state & TDLS_LINKED_STATE))
#endif /* CONFIG_TDLS */
- pstapriv->sta_dz_bitmap |= BIT(psta->aid);
-
-
+ rtw_tim_map_set(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid);
dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->vo_q.sta_pending);
rtw_list_delete(&(pstaxmitpriv->vo_q.tx_pending));
-
-
dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->vi_q.sta_pending);
rtw_list_delete(&(pstaxmitpriv->vi_q.tx_pending));
-
-
dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->be_q.sta_pending);
rtw_list_delete(&(pstaxmitpriv->be_q.tx_pending));
-
-
dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->bk_q.sta_pending);
rtw_list_delete(&(pstaxmitpriv->bk_q.tx_pending));
@@ -4585,12 +4982,16 @@ void stop_sta_xmit(_adapter *padapter, struct sta_info *psta)
if (!(psta->tdls_sta_state & TDLS_LINKED_STATE) && (psta_bmc != NULL)) {
#endif /* CONFIG_TDLS */
-
/* for BC/MC Frames */
pstaxmitpriv = &psta_bmc->sta_xmitpriv;
+ dequeue_xmitframes_to_sleeping_queue(padapter, psta_bmc, &pstaxmitpriv->vo_q.sta_pending);
+ rtw_list_delete(&(pstaxmitpriv->vo_q.tx_pending));
+ dequeue_xmitframes_to_sleeping_queue(padapter, psta_bmc, &pstaxmitpriv->vi_q.sta_pending);
+ rtw_list_delete(&(pstaxmitpriv->vi_q.tx_pending));
dequeue_xmitframes_to_sleeping_queue(padapter, psta_bmc, &pstaxmitpriv->be_q.sta_pending);
rtw_list_delete(&(pstaxmitpriv->be_q.tx_pending));
-
+ dequeue_xmitframes_to_sleeping_queue(padapter, psta_bmc, &pstaxmitpriv->bk_q.sta_pending);
+ rtw_list_delete(&(pstaxmitpriv->bk_q.tx_pending));
#ifdef CONFIG_TDLS
}
@@ -4689,14 +5090,15 @@ void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta)
}
#endif /* CONFIG_TDLS */
- if (pstapriv->tim_bitmap & BIT(psta->aid)) {
- /* RTW_INFO("wakeup to xmit, qlen==0, update_BCNTIM, tim=%x\n", pstapriv->tim_bitmap); */
+ if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, psta->cmn.aid)) {
+ /* RTW_INFO("wakeup to xmit, qlen==0\n"); */
+ /* RTW_INFO_DUMP("update_BCNTIM, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */
/* upate BCN for TIM IE */
/* update_BCNTIM(padapter); */
update_mask = BIT(0);
}
- pstapriv->tim_bitmap &= ~BIT(psta->aid);
+ rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid);
if (psta->state & WIFI_SLEEP_STATE)
psta->state ^= WIFI_SLEEP_STATE;
@@ -4707,14 +5109,14 @@ void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta)
psta->state ^= WIFI_STA_ALIVE_CHK_STATE;
}
- pstapriv->sta_dz_bitmap &= ~BIT(psta->aid);
+ rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, psta->cmn.aid);
}
/* for BC/MC Frames */
if (!psta_bmc)
goto _exit;
- if ((pstapriv->sta_dz_bitmap & 0xfffe) == 0x0) { /* no any sta in ps mode */
+ if (!(rtw_tim_map_anyone_be_set_exclude_aid0(padapter, pstapriv->sta_dz_bitmap))) { /* no any sta in ps mode */
xmitframe_phead = get_list_head(&psta_bmc->sleep_q);
xmitframe_plist = get_next(xmitframe_phead);
@@ -4747,14 +5149,15 @@ void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta)
}
if (psta_bmc->sleepq_len == 0) {
- if (pstapriv->tim_bitmap & BIT(0)) {
- /* RTW_INFO("wakeup to xmit, qlen==0, update_BCNTIM, tim=%x\n", pstapriv->tim_bitmap); */
+ if (rtw_tim_map_is_set(padapter, pstapriv->tim_bitmap, 0)) {
+ /* RTW_INFO("wakeup to xmit, qlen==0\n"); */
+ /* RTW_INFO_DUMP("update_BCNTIM, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */
/* upate BCN for TIM IE */
/* update_BCNTIM(padapter); */
update_mask |= BIT(1);
}
- pstapriv->tim_bitmap &= ~BIT(0);
- pstapriv->sta_dz_bitmap &= ~BIT(0);
+ rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, 0);
+ rtw_tim_map_clear(padapter, pstapriv->sta_dz_bitmap, 0);
}
}
@@ -4843,9 +5246,10 @@ void xmit_delivery_enabled_frames(_adapter *padapter, struct sta_info *psta)
goto exit;
}
#endif /* CONFIG_TDLS */
- pstapriv->tim_bitmap &= ~BIT(psta->aid);
+ rtw_tim_map_clear(padapter, pstapriv->tim_bitmap, psta->cmn.aid);
- /* RTW_INFO("wakeup to xmit, qlen==0, update_BCNTIM, tim=%x\n", pstapriv->tim_bitmap); */
+ /* RTW_INFO("wakeup to xmit, qlen==0\n"); */
+ /* RTW_INFO_DUMP("update_BCNTIM, tim=", pstapriv->tim_bitmap, pstapriv->aid_bmp_len); */
/* upate BCN for TIM IE */
/* update_BCNTIM(padapter); */
update_beacon(padapter, _TIM_IE_, NULL, _TRUE);
@@ -4925,17 +5329,13 @@ struct xmit_buf *dequeue_pending_xmitbuf(
return pxmitbuf;
}
-struct xmit_buf *dequeue_pending_xmitbuf_under_survey(
+static struct xmit_buf *dequeue_pending_xmitbuf_ext(
struct xmit_priv *pxmitpriv)
{
_irqL irql;
struct xmit_buf *pxmitbuf;
-#ifdef CONFIG_USB_HCI
- struct xmit_frame *pxmitframe;
-#endif
_queue *pqueue;
-
pxmitbuf = NULL;
pqueue = &pxmitpriv->pending_xmitbuf_queue;
@@ -4943,7 +5343,7 @@ struct xmit_buf *dequeue_pending_xmitbuf_under_survey(
if (_rtw_queue_empty(pqueue) == _FALSE) {
_list *plist, *phead;
- u8 type;
+ u8 type = 0;
phead = get_list_head(pqueue);
plist = phead;
@@ -4954,19 +5354,7 @@ struct xmit_buf *dequeue_pending_xmitbuf_under_survey(
pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list);
-#ifdef CONFIG_USB_HCI
- pxmitframe = (struct xmit_frame *)pxmitbuf->priv_data;
- if (pxmitframe)
- type = GetFrameSubType(pxmitbuf->pbuf + TXDESC_SIZE + pxmitframe->pkt_offset * PACKET_OFFSET_SZ);
- else
- RTW_INFO("%s, !!!ERROR!!! For USB, TODO ITEM\n", __FUNCTION__);
-#else
- type = GetFrameSubType(pxmitbuf->pbuf + TXDESC_OFFSET);
-#endif
-
- if ((type == WIFI_PROBEREQ) ||
- (type == WIFI_DATA_NULL) ||
- (type == WIFI_QOS_DATA_NULL)) {
+ if (pxmitbuf->buf_tag == XMITBUF_MGNT) {
rtw_list_delete(&pxmitbuf->list);
break;
}
@@ -4979,6 +5367,21 @@ struct xmit_buf *dequeue_pending_xmitbuf_under_survey(
return pxmitbuf;
}
+struct xmit_buf *select_and_dequeue_pending_xmitbuf(_adapter *padapter)
+{
+ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+ struct xmit_buf *pxmitbuf = NULL;
+
+ if (_TRUE == rtw_is_xmit_blocked(padapter))
+ return pxmitbuf;
+
+ pxmitbuf = dequeue_pending_xmitbuf_ext(pxmitpriv);
+ if (pxmitbuf == NULL && rtw_xmit_ac_blocked(padapter) != _TRUE)
+ pxmitbuf = dequeue_pending_xmitbuf(pxmitpriv);
+
+ return pxmitbuf;
+}
+
sint check_pending_xmitbuf(
struct xmit_priv *pxmitpriv)
{
@@ -5014,20 +5417,96 @@ thread_return rtw_xmit_thread(thread_context context)
flush_signals_thread();
} while (_SUCCESS == err);
- _rtw_up_sema(&padapter->xmitpriv.terminate_xmitthread_sema);
+ RTW_INFO(FUNC_ADPT_FMT " Exit\n", FUNC_ADPT_ARG(padapter));
+
+ rtw_thread_wait_stop();
+
+ return 0;
+}
+#endif
+
+#ifdef DBG_XMIT_BLOCK
+void dump_xmit_block(void *sel, _adapter *padapter)
+{
+ struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+
+ RTW_PRINT_SEL(sel, "[XMIT-BLOCK] xmit_block :0x%02x\n", dvobj->xmit_block);
+ if (dvobj->xmit_block & XMIT_BLOCK_REDLMEM)
+ RTW_PRINT_SEL(sel, "Reason:%s\n", "XMIT_BLOCK_REDLMEM");
+ if (dvobj->xmit_block & XMIT_BLOCK_SUSPEND)
+ RTW_PRINT_SEL(sel, "Reason:%s\n", "XMIT_BLOCK_SUSPEND");
+ if (dvobj->xmit_block == XMIT_BLOCK_NONE)
+ RTW_PRINT_SEL(sel, "Reason:%s\n", "XMIT_BLOCK_NONE");
+}
+void dump_xmit_block_info(void *sel, const char *fun_name, _adapter *padapter)
+{
+ struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
- thread_exit();
+ RTW_INFO("\n"ADPT_FMT" call %s\n", ADPT_ARG(padapter), fun_name);
+ dump_xmit_block(sel, padapter);
}
+#define DBG_XMIT_BLOCK_DUMP(adapter) dump_xmit_block_info(RTW_DBGDUMP, __func__, adapter)
#endif
+void rtw_set_xmit_block(_adapter *padapter, enum XMIT_BLOCK_REASON reason)
+{
+ _irqL irqL;
+ struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+
+ _enter_critical_bh(&dvobj->xmit_block_lock, &irqL);
+ dvobj->xmit_block |= reason;
+ _exit_critical_bh(&dvobj->xmit_block_lock, &irqL);
+
+ #ifdef DBG_XMIT_BLOCK
+ DBG_XMIT_BLOCK_DUMP(padapter);
+ #endif
+}
+
+void rtw_clr_xmit_block(_adapter *padapter, enum XMIT_BLOCK_REASON reason)
+{
+ _irqL irqL;
+ struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+
+ _enter_critical_bh(&dvobj->xmit_block_lock, &irqL);
+ dvobj->xmit_block &= ~reason;
+ _exit_critical_bh(&dvobj->xmit_block_lock, &irqL);
+
+ #ifdef DBG_XMIT_BLOCK
+ DBG_XMIT_BLOCK_DUMP(padapter);
+ #endif
+}
+bool rtw_is_xmit_blocked(_adapter *padapter)
+{
+ struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+
+ #ifdef DBG_XMIT_BLOCK
+ DBG_XMIT_BLOCK_DUMP(padapter);
+ #endif
+ return ((dvobj->xmit_block) ? _TRUE : _FALSE);
+}
+
bool rtw_xmit_ac_blocked(_adapter *adapter)
{
struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
_adapter *iface;
struct mlme_ext_priv *mlmeext;
struct mlme_ext_info *mlmeextinfo;
bool blocked = _FALSE;
int i;
+#ifdef DBG_CONFIG_ERROR_DETECT
+#ifdef DBG_CONFIG_ERROR_RESET
+#ifdef CONFIG_USB_HCI
+ if (rtw_hal_sreset_inprogress(adapter) == _TRUE) {
+ blocked = _TRUE;
+ goto exit;
+ }
+#endif/* #ifdef CONFIG_USB_HCI */
+#endif/* #ifdef DBG_CONFIG_ERROR_RESET */
+#endif/* #ifdef DBG_CONFIG_ERROR_DETECT */
+
+ if (rfctl->offch_state != OFFCHS_NONE)
+ blocked = _TRUE;
for (i = 0; i < dvobj->iface_nums; i++) {
iface = dvobj->padapters[i];
@@ -5035,15 +5514,15 @@ bool rtw_xmit_ac_blocked(_adapter *adapter)
/* check scan state */
if (mlmeext_scan_state(mlmeext) != SCAN_DISABLE
- && mlmeext_scan_state(mlmeext) != SCAN_BACK_OP
- ) {
+ && mlmeext_scan_state(mlmeext) != SCAN_BACK_OP
+ ) {
blocked = _TRUE;
goto exit;
}
if (mlmeext_scan_state(mlmeext) == SCAN_BACK_OP
- && !mlmeext_chk_scan_backop_flags(mlmeext, SS_BACKOP_TX_RESUME)
- ) {
+ && !mlmeext_chk_scan_backop_flags(mlmeext, SS_BACKOP_TX_RESUME)
+ ) {
blocked = _TRUE;
goto exit;
}
@@ -5064,7 +5543,7 @@ bool rtw_xmit_ac_blocked(_adapter *adapter)
return blocked;
}
-#ifdef TX_AMSDU
+#ifdef CONFIG_TX_AMSDU
void rtw_amsdu_vo_timeout_handler(void *FunctionContext)
{
_adapter *adapter = (_adapter *)FunctionContext;
@@ -5073,6 +5552,7 @@ void rtw_amsdu_vo_timeout_handler(void *FunctionContext)
tasklet_hi_schedule(&adapter->xmitpriv.xmit_tasklet);
}
+
void rtw_amsdu_vi_timeout_handler(void *FunctionContext)
{
_adapter *adapter = (_adapter *)FunctionContext;
@@ -5081,6 +5561,7 @@ void rtw_amsdu_vi_timeout_handler(void *FunctionContext)
tasklet_hi_schedule(&adapter->xmitpriv.xmit_tasklet);
}
+
void rtw_amsdu_be_timeout_handler(void *FunctionContext)
{
_adapter *adapter = (_adapter *)FunctionContext;
@@ -5092,6 +5573,7 @@ void rtw_amsdu_be_timeout_handler(void *FunctionContext)
tasklet_hi_schedule(&adapter->xmitpriv.xmit_tasklet);
}
+
void rtw_amsdu_bk_timeout_handler(void *FunctionContext)
{
_adapter *adapter = (_adapter *)FunctionContext;
@@ -5129,6 +5611,7 @@ u8 rtw_amsdu_get_timer_status(_adapter *padapter, u8 priority)
}
return status;
}
+
void rtw_amsdu_set_timer_status(_adapter *padapter, u8 priority, u8 status)
{
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
@@ -5154,6 +5637,7 @@ void rtw_amsdu_set_timer_status(_adapter *padapter, u8 priority, u8 status)
break;
}
}
+
void rtw_amsdu_set_timer(_adapter *padapter, u8 priority)
{
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
@@ -5182,11 +5666,11 @@ void rtw_amsdu_set_timer(_adapter *padapter, u8 priority)
}
_set_timer(amsdu_timer, 1);
}
+
void rtw_amsdu_cancel_timer(_adapter *padapter, u8 priority)
{
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
_timer* amsdu_timer = NULL;
- u8 cancel;
switch(priority)
{
@@ -5208,7 +5692,56 @@ void rtw_amsdu_cancel_timer(_adapter *padapter, u8 priority)
amsdu_timer = &pxmitpriv->amsdu_be_timer;
break;
}
- _cancel_timer(amsdu_timer, &cancel);
+ _cancel_timer_ex(amsdu_timer);
+}
+#endif /* CONFIG_TX_AMSDU */
+
+#ifdef DBG_TXBD_DESC_DUMP
+static struct rtw_tx_desc_backup tx_backup[HW_QUEUE_ENTRY][TX_BAK_FRMAE_CNT];
+static u8 backup_idx[HW_QUEUE_ENTRY];
+
+void rtw_tx_desc_backup(_adapter *padapter, struct xmit_frame *pxmitframe, u8 desc_size, u8 hwq)
+{
+ u16 reg_rp;
+ u16 reg_wp;
+ u32 tmp32;
+ u8 *pxmit_buf;
+
+ if (rtw_get_hw_init_completed(padapter) == _FALSE)
+ return;
+
+ pxmit_buf = pxmitframe->pxmitbuf->pbuf;
+
+ _rtw_memcpy(tx_backup[hwq][backup_idx[hwq]].tx_bak_desc, pxmit_buf, desc_size);
+ _rtw_memcpy(tx_backup[hwq][backup_idx[hwq]].tx_bak_data_hdr, pxmit_buf+desc_size, TX_BAK_DATA_LEN);
+
+ tmp32 = rtw_read32(padapter, get_txbd_rw_reg(hwq));
+
+ tx_backup[hwq][backup_idx[hwq]].tx_bak_rp = (tmp32>>16)&0xfff;
+ tx_backup[hwq][backup_idx[hwq]].tx_bak_wp = tmp32&0xfff;
+
+ tx_backup[hwq][backup_idx[hwq]].tx_desc_size = desc_size;
+
+ backup_idx[hwq] = (backup_idx[hwq] + 1) % TX_BAK_FRMAE_CNT;
+}
+
+void rtw_tx_desc_backup_reset(void)
+{
+ int i, j;
+
+ for (i = 0; i < HW_QUEUE_ENTRY; i++) {
+ for (j = 0; j < TX_BAK_FRMAE_CNT; j++)
+ _rtw_memset(&tx_backup[i][j], 0, sizeof(struct rtw_tx_desc_backup));
+
+ backup_idx[i] = 0;
+ }
+}
+
+u8 rtw_get_tx_desc_backup(_adapter *padapter, u8 hwq, struct rtw_tx_desc_backup **pbak)
+{
+ *pbak = &tx_backup[hwq][0];
+
+ return backup_idx[hwq];
}
#endif
@@ -5278,63 +5811,8 @@ void rtw_sctx_done(struct submit_ctx **sctx)
}
#ifdef CONFIG_XMIT_ACK
-
-#ifdef CONFIG_XMIT_ACK_POLLING
-s32 c2h_evt_hdl(_adapter *adapter, u8 *c2h_evt, c2h_id_filter filter);
-
-/**
- * rtw_ack_tx_polling -
- * @pxmitpriv: xmit_priv to address ack_tx_ops
- * @timeout_ms: timeout msec
- *
- * Init ack_tx_ops and then do c2h_evt_hdl() and polling ack_tx_ops repeatedly
- * till tx report or timeout
- * Returns: _SUCCESS if TX report ok, _FAIL for others
- */
-int rtw_ack_tx_polling(struct xmit_priv *pxmitpriv, u32 timeout_ms)
-{
- int ret = _FAIL;
- struct submit_ctx *pack_tx_ops = &pxmitpriv->ack_tx_ops;
- _adapter *adapter = container_of(pxmitpriv, _adapter, xmitpriv);
-
- pack_tx_ops->submit_time = rtw_get_current_time();
- pack_tx_ops->timeout_ms = timeout_ms;
- pack_tx_ops->status = RTW_SCTX_SUBMITTED;
-
- do {
- c2h_evt_hdl(adapter, NULL, rtw_hal_c2h_id_filter_ccx(adapter));
- if (pack_tx_ops->status != RTW_SCTX_SUBMITTED)
- break;
-
- if (rtw_is_drv_stopped(adapter)) {
- pack_tx_ops->status = RTW_SCTX_DONE_DRV_STOP;
- break;
- }
- if (rtw_is_surprise_removed(adapter)) {
- pack_tx_ops->status = RTW_SCTX_DONE_DEV_REMOVE;
- break;
- }
-
- rtw_msleep_os(10);
- } while (rtw_get_passing_time_ms(pack_tx_ops->submit_time) < timeout_ms);
-
- if (pack_tx_ops->status == RTW_SCTX_SUBMITTED) {
- pack_tx_ops->status = RTW_SCTX_DONE_TIMEOUT;
- RTW_INFO("%s timeout\n", __func__);
- }
-
- if (pack_tx_ops->status == RTW_SCTX_DONE_SUCCESS)
- ret = _SUCCESS;
-
- return ret;
-}
-#endif
-
int rtw_ack_tx_wait(struct xmit_priv *pxmitpriv, u32 timeout_ms)
{
-#ifdef CONFIG_XMIT_ACK_POLLING
- return rtw_ack_tx_polling(pxmitpriv, timeout_ms);
-#else
struct submit_ctx *pack_tx_ops = &pxmitpriv->ack_tx_ops;
pack_tx_ops->submit_time = rtw_get_current_time();
@@ -5342,7 +5820,6 @@ int rtw_ack_tx_wait(struct xmit_priv *pxmitpriv, u32 timeout_ms)
pack_tx_ops->status = RTW_SCTX_SUBMITTED;
return rtw_sctx_wait(pack_tx_ops, __func__);
-#endif
}
void rtw_ack_tx_done(struct xmit_priv *pxmitpriv, int status)
diff --git a/dkms.conf b/dkms.conf
new file mode 100644
index 0000000..8b081d0
--- /dev/null
+++ b/dkms.conf
@@ -0,0 +1,9 @@
+PACKAGE_NAME=88x2bu
+PACKAGE_VERSION=1.1
+
+DEST_MODULE_LOCATION=/kernel/drivers/net/wireless
+BUILT_MODULE_NAME=88x2bu
+
+MAKE="'make' all KVER=${kernelver}"
+CLEAN="'make' clean"
+AUTOINSTALL="yes"
diff --git a/hal/HalPwrSeqCmd.c b/hal/HalPwrSeqCmd.c
index 411b3c6..389785c 100644
--- a/hal/HalPwrSeqCmd.c
+++ b/hal/HalPwrSeqCmd.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,12 +11,7 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
/*++
Copyright (c) Realtek Semiconductor Corp. All rights reserved.
@@ -54,25 +49,17 @@ u8 HalPwrSeqCmdParsing(
{
WLAN_PWR_CFG PwrCfgCmd = {0};
u8 bPollingBit = _FALSE;
+ u8 bHWICSupport = _FALSE;
u32 AryIdx = 0;
u8 value = 0;
u32 offset = 0;
+ u8 flag = 0;
u32 pollingCount = 0; /* polling autoload done. */
u32 maxPollingCnt = 5000;
do {
PwrCfgCmd = PwrSeqCmd[AryIdx];
- RT_TRACE(_module_hal_init_c_ , _drv_info_,
- ("HalPwrSeqCmdParsing: offset(%#x) cut_msk(%#x) fab_msk(%#x) interface_msk(%#x) base(%#x) cmd(%#x) msk(%#x) value(%#x)\n",
- GET_PWR_CFG_OFFSET(PwrCfgCmd),
- GET_PWR_CFG_CUT_MASK(PwrCfgCmd),
- GET_PWR_CFG_FAB_MASK(PwrCfgCmd),
- GET_PWR_CFG_INTF_MASK(PwrCfgCmd),
- GET_PWR_CFG_BASE(PwrCfgCmd),
- GET_PWR_CFG_CMD(PwrCfgCmd),
- GET_PWR_CFG_MASK(PwrCfgCmd),
- GET_PWR_CFG_VALUE(PwrCfgCmd)));
/* 2 Only Handle the command whose FAB, CUT, and Interface are matched */
if ((GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) &&
@@ -80,11 +67,9 @@ u8 HalPwrSeqCmdParsing(
(GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType)) {
switch (GET_PWR_CFG_CMD(PwrCfgCmd)) {
case PWR_CMD_READ:
- RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_READ\n"));
break;
case PWR_CMD_WRITE:
- RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_WRITE\n"));
offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
#ifdef CONFIG_SDIO_HCI
@@ -120,10 +105,17 @@ u8 HalPwrSeqCmdParsing(
break;
case PWR_CMD_POLLING:
- RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_POLLING\n"));
bPollingBit = _FALSE;
offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
+
+ rtw_hal_get_hwreg(padapter, HW_VAR_PWR_CMD, &bHWICSupport);
+ if (bHWICSupport && offset == 0x06) {
+ flag = 0;
+ maxPollingCnt = 100000;
+ } else
+ maxPollingCnt = 5000;
+
#ifdef CONFIG_GSPI_HCI
if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
offset = SPI_LOCAL_OFFSET | offset;
@@ -144,14 +136,32 @@ u8 HalPwrSeqCmdParsing(
if (pollingCount++ > maxPollingCnt) {
RTW_ERR("HalPwrSeqCmdParsing: Fail to polling Offset[%#x]=%02x\n", offset, value);
- return _FALSE;
+
+ /* For PCIE + USB package poll power bit timeout issue only modify 8821AE and 8723BE */
+ if (bHWICSupport && offset == 0x06 && flag == 0) {
+
+ RTW_ERR("[WARNING] PCIE polling(0x%X) timeout(%d), Toggle 0x04[3] and try again.\n", offset, maxPollingCnt);
+ if (IS_HARDWARE_TYPE_8723DE(padapter))
+ PlatformEFIOWrite1Byte(padapter, 0x40, (PlatformEFIORead1Byte(padapter, 0x40)) & (~BIT3));
+
+ PlatformEFIOWrite1Byte(padapter, 0x04, PlatformEFIORead1Byte(padapter, 0x04) | BIT3);
+ PlatformEFIOWrite1Byte(padapter, 0x04, PlatformEFIORead1Byte(padapter, 0x04) & ~BIT3);
+
+ if (IS_HARDWARE_TYPE_8723DE(padapter))
+ PlatformEFIOWrite1Byte(padapter, 0x40, PlatformEFIORead1Byte(padapter, 0x40)|BIT3);
+
+ /* Retry Polling Process one more time */
+ pollingCount = 0;
+ flag = 1;
+ } else {
+ return _FALSE;
+ }
}
} while (!bPollingBit);
break;
case PWR_CMD_DELAY:
- RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_DELAY\n"));
if (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US)
rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd));
else
@@ -160,12 +170,10 @@ u8 HalPwrSeqCmdParsing(
case PWR_CMD_END:
/* When this command is parsed, end the process */
- RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_END\n"));
return _TRUE;
break;
default:
- RT_TRACE(_module_hal_init_c_ , _drv_err_, ("HalPwrSeqCmdParsing: Unknown CMD!!\n"));
break;
}
}
diff --git a/hal/btc/HalBtc8188c2Ant.c b/hal/btc/HalBtc8188c2Ant.c
deleted file mode 100644
index 59c2d4c..0000000
--- a/hal/btc/HalBtc8188c2Ant.c
+++ /dev/null
@@ -1,1987 +0,0 @@
-//============================================================
-// Description:
-//
-// This file is for 92CE/92CU BT 1 Antenna Co-exist mechanism
-//
-// By cosa 02/11/2011
-//
-//============================================================
-
-//============================================================
-// include files
-//============================================================
-#include "Mp_Precomp.h"
-
-#if WPP_SOFTWARE_TRACE
-#include "HalBtc8188c2Ant.tmh"
-#endif
-
-#if(BT_30_SUPPORT == 1)
-//============================================================
-// Global variables, these are static variables
-//============================================================
-static COEX_DM_8188C_2ANT GLCoexDm8188c2Ant;
-static PCOEX_DM_8188C_2ANT pCoexDm=&GLCoexDm8188c2Ant;
-static COEX_STA_8188C_2ANT GLCoexSta8188c2Ant;
-static PCOEX_STA_8188C_2ANT pCoexSta=&GLCoexSta8188c2Ant;
-
-//============================================================
-// local function start with btdm_
-//============================================================
-u1Byte
-halbtc8188c2ant_WifiRssiState(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte index,
- IN u1Byte levelNum,
- IN u1Byte rssiThresh,
- IN u1Byte rssiThresh1
- )
-{
- s4Byte wifiRssi=0;
- u1Byte wifiRssiState=pCoexSta->preWifiRssiState[index];
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi);
-
- if(levelNum == 2)
- {
- if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) ||
- (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW))
- {
- if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8188C_2ANT))
- {
- wifiRssiState = BTC_RSSI_STATE_HIGH;
- }
- else
- {
- wifiRssiState = BTC_RSSI_STATE_STAY_LOW;
- }
- }
- else
- {
- if(wifiRssi < rssiThresh)
- {
- wifiRssiState = BTC_RSSI_STATE_LOW;
- }
- else
- {
- wifiRssiState = BTC_RSSI_STATE_STAY_HIGH;
- }
- }
- }
- else if(levelNum == 3)
- {
- if(rssiThresh > rssiThresh1)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi RSSI thresh error!!\n"));
- return pCoexSta->preWifiRssiState[index];
- }
-
- if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) ||
- (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW))
- {
- if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8188C_2ANT))
- {
- wifiRssiState = BTC_RSSI_STATE_MEDIUM;
- }
- else
- {
- wifiRssiState = BTC_RSSI_STATE_STAY_LOW;
- }
- }
- else if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_MEDIUM) ||
- (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_MEDIUM))
- {
- if(wifiRssi >= (rssiThresh1+BTC_RSSI_COEX_THRESH_TOL_8188C_2ANT))
- {
- wifiRssiState = BTC_RSSI_STATE_HIGH;
- }
- else if(wifiRssi < rssiThresh)
- {
- wifiRssiState = BTC_RSSI_STATE_LOW;
- }
- else
- {
- wifiRssiState = BTC_RSSI_STATE_STAY_MEDIUM;
- }
- }
- else
- {
- if(wifiRssi < rssiThresh1)
- {
- wifiRssiState = BTC_RSSI_STATE_MEDIUM;
- }
- else
- {
- wifiRssiState = BTC_RSSI_STATE_STAY_HIGH;
- }
- }
- }
-
- pCoexSta->preWifiRssiState[index] = wifiRssiState;
-
- return wifiRssiState;
-}
-
-u1Byte
-halbtc8188c2ant_ActionAlgorithm(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo;
- u1Byte algorithm=BT_8188C_2ANT_COEX_ALGO_UNDEFINED;
- u1Byte numOfDiffProfile=0;
-
- if(!pStackInfo->bBtLinkExist)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], No profile exists!!!\n"));
- return algorithm;
- }
-
- if(pStackInfo->bScoExist)
- numOfDiffProfile++;
- if(pStackInfo->bHidExist)
- numOfDiffProfile++;
- if(pStackInfo->bPanExist)
- numOfDiffProfile++;
- if(pStackInfo->bA2dpExist)
- numOfDiffProfile++;
-
- if(pStackInfo->bScoExist)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO algorithm\n"));
- algorithm = BT_8188C_2ANT_COEX_ALGO_SCO;
- }
- else
- {
- if(numOfDiffProfile == 1)
- {
- if(pStackInfo->bHidExist)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID only\n"));
- algorithm = BT_8188C_2ANT_COEX_ALGO_HID;
- }
- else if(pStackInfo->bA2dpExist)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP only\n"));
- algorithm = BT_8188C_2ANT_COEX_ALGO_A2DP;
- }
- else if(pStackInfo->bPanExist)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN only\n"));
- algorithm = BT_8188C_2ANT_COEX_ALGO_PAN;
- }
- }
- else
- {
- if( pStackInfo->bHidExist &&
- pStackInfo->bA2dpExist )
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + A2DP\n"));
- algorithm = BT_8188C_2ANT_COEX_ALGO_HID_A2DP;
- }
- else if( pStackInfo->bHidExist &&
- pStackInfo->bPanExist )
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + PAN\n"));
- algorithm = BT_8188C_2ANT_COEX_ALGO_HID_PAN;
- }
- else if( pStackInfo->bPanExist &&
- pStackInfo->bA2dpExist )
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN + A2DP\n"));
- algorithm = BT_8188C_2ANT_COEX_ALGO_PAN_A2DP;
- }
- }
- }
- return algorithm;
-}
-
-VOID
-halbtc8188c2ant_SetFwBalance(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bBalanceOn,
- IN u1Byte ms0,
- IN u1Byte ms1
- )
-{
- u1Byte H2C_Parameter[3] ={0};
-
- if(bBalanceOn)
- {
- H2C_Parameter[2] = 1;
- H2C_Parameter[1] = ms1;
- H2C_Parameter[0] = ms0;
- }
- else
- {
- H2C_Parameter[2] = 0;
- H2C_Parameter[1] = 0;
- H2C_Parameter[0] = 0;
- }
-
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Balance=[%s:%dms:%dms], write 0xc=0x%x\n",
- bBalanceOn?"ON":"OFF", ms0, ms1,
- H2C_Parameter[0]<<16|H2C_Parameter[1]<<8|H2C_Parameter[2]));
-
- pBtCoexist->fBtcFillH2c(pBtCoexist, 0xc, 3, H2C_Parameter);
-}
-
-VOID
-halbtc8188c2ant_Balance(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bForceExec,
- IN BOOLEAN bBalanceOn,
- IN u1Byte ms0,
- IN u1Byte ms1
- )
-{
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Balance %s\n",
- (bForceExec? "force to":""), (bBalanceOn? "ON":"OFF")));
- pCoexDm->bCurBalanceOn = bBalanceOn;
-
- if(!bForceExec)
- {
- if(pCoexDm->bPreBalanceOn == pCoexDm->bCurBalanceOn)
- return;
- }
- halbtc8188c2ant_SetFwBalance(pBtCoexist, bBalanceOn, ms0, ms1);
-
- pCoexDm->bPreBalanceOn = pCoexDm->bCurBalanceOn;
-}
-
-VOID
-halbtc8188c2ant_SetFwDiminishWifi(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bDacOn,
- IN BOOLEAN bInterruptOn,
- IN u1Byte fwDacSwingLvl,
- IN BOOLEAN bNavOn
- )
-{
- u1Byte H2C_Parameter[3] ={0};
-
- if((pBtCoexist->stackInfo.minBtRssi <= -5) && (fwDacSwingLvl == 0x20))
- {
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], DiminishWiFi 0x20 original, but set 0x18 for Low RSSI!\n"));
- fwDacSwingLvl = 0x18;
- }
-
- H2C_Parameter[2] = 0;
- H2C_Parameter[1] = fwDacSwingLvl;
- H2C_Parameter[0] = 0;
- if(bDacOn)
- {
- H2C_Parameter[2] |= 0x01; //BIT0
- if(bInterruptOn)
- {
- H2C_Parameter[2] |= 0x02; //BIT1
- }
- }
- if(bNavOn)
- {
- H2C_Parameter[2] |= 0x08; //BIT3
- }
-
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], bDacOn=%s, bInterruptOn=%s, bNavOn=%s, write 0xe=0x%x\n",
- (bDacOn?"ON":"OFF"), (bInterruptOn?"ON":"OFF"), (bNavOn?"ON":"OFF"),
- (H2C_Parameter[0]<<16|H2C_Parameter[1]<<8|H2C_Parameter[2])));
- pBtCoexist->fBtcFillH2c(pBtCoexist, 0xe, 3, H2C_Parameter);
-}
-
-VOID
-halbtc8188c2ant_DiminishWifi(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bForceExec,
- IN BOOLEAN bDacOn,
- IN BOOLEAN bInterruptOn,
- IN u1Byte fwDacSwingLvl,
- IN BOOLEAN bNavOn
- )
-{
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s set Diminish Wifi, bDacOn=%s, bInterruptOn=%s, fwDacSwingLvl=%d, bNavOn=%s\n",
- (bForceExec? "force to":""), (bDacOn? "ON":"OFF"), (bInterruptOn? "ON":"OFF"), fwDacSwingLvl, (bNavOn? "ON":"OFF")));
-
- pCoexDm->bCurDacOn = bDacOn;
- pCoexDm->bCurInterruptOn = bInterruptOn;
- pCoexDm->curFwDacSwingLvl = fwDacSwingLvl;
- pCoexDm->bCurNavOn = bNavOn;
-
- if(!bForceExec)
- {
- if( (pCoexDm->bPreDacOn==pCoexDm->bCurDacOn) &&
- (pCoexDm->bPreInterruptOn==pCoexDm->bCurInterruptOn) &&
- (pCoexDm->preFwDacSwingLvl==pCoexDm->curFwDacSwingLvl) &&
- (pCoexDm->bPreNavOn==pCoexDm->bCurNavOn) )
- return;
- }
- halbtc8188c2ant_SetFwDiminishWifi(pBtCoexist, bDacOn, bInterruptOn, fwDacSwingLvl, bNavOn);
-
- pCoexDm->bPreDacOn = pCoexDm->bCurDacOn;
- pCoexDm->bPreInterruptOn = pCoexDm->bCurInterruptOn;
- pCoexDm->preFwDacSwingLvl = pCoexDm->curFwDacSwingLvl;
- pCoexDm->bPreNavOn = pCoexDm->bCurNavOn;
-}
-
-VOID
-halbtc8188c2ant_SetSwRfRxLpfCorner(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bRxRfShrinkOn
- )
-{
- if(bRxRfShrinkOn)
- {
- //Shrink RF Rx LPF corner
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Shrink RF Rx LPF corner!!\n"));
- pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xf0, 0xf);
- }
- else
- {
- //Resume RF Rx LPF corner
- // After initialized, we can use pCoexDm->btRf0x1eBackup
- if(pBtCoexist->bInitilized)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Resume RF Rx LPF corner!!\n"));
- pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xf0, pCoexDm->btRf0x1eBackup);
- }
- }
-}
-
-VOID
-halbtc8188c2ant_RfShrink(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bForceExec,
- IN BOOLEAN bRxRfShrinkOn
- )
-{
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Rx RF Shrink = %s\n",
- (bForceExec? "force to":""), ((bRxRfShrinkOn)? "ON":"OFF")));
- pCoexDm->bCurRfRxLpfShrink = bRxRfShrinkOn;
-
- if(!bForceExec)
- {
- if(pCoexDm->bPreRfRxLpfShrink == pCoexDm->bCurRfRxLpfShrink)
- return;
- }
- halbtc8188c2ant_SetSwRfRxLpfCorner(pBtCoexist, pCoexDm->bCurRfRxLpfShrink);
-
- pCoexDm->bPreRfRxLpfShrink = pCoexDm->bCurRfRxLpfShrink;
-}
-
-VOID
-halbtc8188c2ant_SetSwPenaltyTxRateAdaptive(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bLowPenaltyRa
- )
-{
- u1Byte tmpU1;
-
- tmpU1 = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x4fd);
- if(bLowPenaltyRa)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Tx rate adaptive, set low penalty!!\n"));
- tmpU1 &= ~BIT2;
- }
- else
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Tx rate adaptive, set normal!!\n"));
- tmpU1 |= BIT2;
- }
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x4fd, tmpU1);
-}
-
-VOID
-halbtc8188c2ant_LowPenaltyRa(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bForceExec,
- IN BOOLEAN bLowPenaltyRa
- )
-{
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn LowPenaltyRA = %s\n",
- (bForceExec? "force to":""), ((bLowPenaltyRa)? "ON":"OFF")));
- pCoexDm->bCurLowPenaltyRa = bLowPenaltyRa;
-
- if(!bForceExec)
- {
- if(pCoexDm->bPreLowPenaltyRa == pCoexDm->bCurLowPenaltyRa)
- return;
- }
- halbtc8188c2ant_SetSwPenaltyTxRateAdaptive(pBtCoexist, pCoexDm->bCurLowPenaltyRa);
-
- pCoexDm->bPreLowPenaltyRa = pCoexDm->bCurLowPenaltyRa;
-}
-
-VOID
-halbtc8188c2ant_SetSwFullTimeDacSwing(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bSwDacSwingOn,
- IN u4Byte swDacSwingLvl
- )
-{
- u4Byte dacSwingLvl;
-
- if(bSwDacSwingOn)
- {
- if((pBtCoexist->stackInfo.minBtRssi <= -5) && (swDacSwingLvl == 0x20))
- {
- dacSwingLvl = 0x18;
- }
- else
- {
- dacSwingLvl = swDacSwingLvl;
- }
- pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x880, 0xfc000000, dacSwingLvl);
- }
- else
- {
- pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x880, 0xfc000000, 0x30);
- }
-}
-
-VOID
-halbtc8188c2ant_DacSwing(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bForceExec,
- IN BOOLEAN bDacSwingOn,
- IN u4Byte dacSwingLvl
- )
-{
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn DacSwing=%s, dacSwingLvl=0x%x\n",
- (bForceExec? "force to":""), ((bDacSwingOn)? "ON":"OFF"), dacSwingLvl));
- pCoexDm->bCurDacSwingOn = bDacSwingOn;
- pCoexDm->curDacSwingLvl = dacSwingLvl;
-
- if(!bForceExec)
- {
- if( (pCoexDm->bPreDacSwingOn == pCoexDm->bCurDacSwingOn) &&
- (pCoexDm->preDacSwingLvl == pCoexDm->curDacSwingLvl) )
- return;
- }
- delay_ms(30);
- halbtc8188c2ant_SetSwFullTimeDacSwing(pBtCoexist, bDacSwingOn, dacSwingLvl);
-
- pCoexDm->bPreDacSwingOn = pCoexDm->bCurDacSwingOn;
- pCoexDm->preDacSwingLvl = pCoexDm->curDacSwingLvl;
-}
-
-VOID
-halbtc8188c2ant_SetAdcBackOff(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bAdcBackOff
- )
-{
- if(bAdcBackOff)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB BackOff Level On!\n"));
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc04,0x3a07611);
- }
- else
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB BackOff Level Off!\n"));
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc04,0x3a05611);
- }
-}
-
-VOID
-halbtc8188c2ant_AdcBackOff(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bForceExec,
- IN BOOLEAN bAdcBackOff
- )
-{
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn AdcBackOff = %s\n",
- (bForceExec? "force to":""), ((bAdcBackOff)? "ON":"OFF")));
- pCoexDm->bCurAdcBackOff = bAdcBackOff;
-
- if(!bForceExec)
- {
- if(pCoexDm->bPreAdcBackOff == pCoexDm->bCurAdcBackOff)
- return;
- }
- halbtc8188c2ant_SetAdcBackOff(pBtCoexist, pCoexDm->bCurAdcBackOff);
-
- pCoexDm->bPreAdcBackOff = pCoexDm->bCurAdcBackOff;
-}
-
-VOID
-halbtc8188c2ant_SetAgcTable(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bAgcTableEn
- )
-{
- u1Byte rssiAdjustVal=0;
-
- if(bAgcTableEn)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table On!\n"));
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x4e1c0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x4d1d0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x4c1e0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x4b1f0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x4a200001);
-
- pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0xdc000);
- pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0x90000);
- pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0x51000);
- pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0x12000);
- pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1a, 0xfffff, 0x00255);
- }
- else
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table Off!\n"));
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x641c0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x631d0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x621e0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x611f0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x60200001);
-
- pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0x32000);
- pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0x71000);
- pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0xb0000);
- pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0xfc000);
- pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1a, 0xfffff, 0x10255);
- }
-
- // set rssiAdjustVal for wifi module.
- pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON, &rssiAdjustVal);
-}
-
-
-VOID
-halbtc8188c2ant_AgcTable(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bForceExec,
- IN BOOLEAN bAgcTableEn
- )
-{
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s %s Agc Table\n",
- (bForceExec? "force to":""), ((bAgcTableEn)? "Enable":"Disable")));
- pCoexDm->bCurAgcTableEn = bAgcTableEn;
-
- if(!bForceExec)
- {
- if(pCoexDm->bPreAgcTableEn == pCoexDm->bCurAgcTableEn)
- return;
- }
- halbtc8188c2ant_SetAgcTable(pBtCoexist, bAgcTableEn);
-
- pCoexDm->bPreAgcTableEn = pCoexDm->bCurAgcTableEn;
-}
-
-VOID
-halbtc8188c2ant_SetCoexTable(
- IN PBTC_COEXIST pBtCoexist,
- IN u4Byte val0x6c4,
- IN u4Byte val0x6c8,
- IN u4Byte val0x6cc
- )
-{
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], set coex table, set 0x6c4=0x%x\n", val0x6c4));
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c4, val0x6c4);
-
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], set coex table, set 0x6c8=0x%x\n", val0x6c8));
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c8, val0x6c8);
-
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], set coex table, set 0x6cc=0x%x\n", val0x6cc));
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6cc, val0x6cc);
-}
-
-VOID
-halbtc8188c2ant_CoexTable(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bForceExec,
- IN u4Byte val0x6c4,
- IN u4Byte val0x6c8,
- IN u4Byte val0x6cc
- )
-{
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s write Coex Table 0x6c4=0x%x, 0x6c8=0x%x, 0x6cc=0x%x\n",
- (bForceExec? "force to":""), val0x6c4, val0x6c8, val0x6cc));
- pCoexDm->curVal0x6c4 = val0x6c4;
- pCoexDm->curVal0x6c8 = val0x6c8;
- pCoexDm->curVal0x6cc = val0x6cc;
-
- if(!bForceExec)
- {
- if( (pCoexDm->preVal0x6c4 == pCoexDm->curVal0x6c4) &&
- (pCoexDm->preVal0x6c8 == pCoexDm->curVal0x6c8) &&
- (pCoexDm->preVal0x6cc == pCoexDm->curVal0x6cc) )
- return;
- }
- halbtc8188c2ant_SetCoexTable(pBtCoexist, val0x6c4, val0x6c8, val0x6cc);
-
- pCoexDm->preVal0x6c4 = pCoexDm->curVal0x6c4;
- pCoexDm->preVal0x6c8 = pCoexDm->curVal0x6c8;
- pCoexDm->preVal0x6cc = pCoexDm->curVal0x6cc;
-}
-
-VOID
-halbtc8188c2ant_CoexAllOff(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- // fw mechanism
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE);
-
- // sw mechanism
- halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
-}
-VOID
-halbtc8188c2ant_InitCoexDm(
- IN PBTC_COEXIST pBtCoexist
- )
-{
-}
-
-
-VOID
-halbtc8188c2ant_MonitorBtState(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- BOOLEAN stateChange=FALSE;
- u4Byte BT_Polling, Ratio_Act, Ratio_STA;
- u4Byte BT_Active, BT_State;
- u4Byte regBTActive=0, regBTState=0, regBTPolling=0;
- u4Byte btBusyThresh=0;
- u4Byte fwVer=0;
- static BOOLEAN bBtBusyTraffic=FALSE;
- BOOLEAN bRejApAggPkt=FALSE;
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer);
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], FirmwareVersion = 0x%x(%d)\n", fwVer, fwVer));
- if(fwVer < 62)
- {
- regBTActive = 0x488;
- regBTState = 0x48c;
- regBTPolling = 0x490;
- }
- else
- {
- regBTActive = 0x444;
- regBTState = 0x448;
- if(fwVer >= 74)
- regBTPolling = 0x44c;
- else
- regBTPolling = 0x700;
- }
- btBusyThresh = 60;
-
- BT_Active = pBtCoexist->fBtcRead4Byte(pBtCoexist, regBTActive);
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT_Active(0x%x)=0x%x\n", regBTActive, BT_Active));
- BT_Active = BT_Active & 0x00ffffff;
-
- BT_State = pBtCoexist->fBtcRead4Byte(pBtCoexist, regBTState);
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT_State(0x%x)=0x%x\n", regBTState, BT_State));
- BT_State = BT_State & 0x00ffffff;
-
- BT_Polling = pBtCoexist->fBtcRead4Byte(pBtCoexist, regBTPolling);
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT_Polling(0x%x)=0x%x\n", regBTPolling, BT_Polling));
-
- if(BT_Active==0xffffffff && BT_State==0xffffffff && BT_Polling==0xffffffff )
- return;
-
- // 2011/05/04 MH For Slim combo test meet a problem. Surprise remove and WLAN is running
- // DHCP process. At the same time, the register read value might be zero. And cause BSOD 0x7f
- // EXCEPTION_DIVIDED_BY_ZERO. In This case, the stack content may always be wrong due to
- // HW divide trap.
- if (BT_Polling==0)
- return;
-
- Ratio_Act = BT_Active*1000/BT_Polling;
- Ratio_STA = BT_State*1000/BT_Polling;
-
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Ratio_Act=%d\n", Ratio_Act));
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Ratio_STA=%d\n", Ratio_STA));
-
- if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType)
- {
- if(Ratio_STA < 60) // BT PAN idle
- {
- }
- else
- {
- // Check if BT PAN (under BT 2.1) is uplink or downlink
- if((Ratio_Act/Ratio_STA) < 2)
- { // BT PAN Uplink
- pCoexSta->bBtUplink = TRUE;
- }
- else
- { // BT PAN downlink
- pCoexSta->bBtUplink = FALSE;
- }
- }
- }
-
- // Check BT is idle or not
- if(!pBtCoexist->stackInfo.bBtLinkExist)
- {
- pCoexSta->bBtBusy = FALSE;
- }
- else
- {
- if(BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType)
- {
- if(Ratio_Act<20)
- {
- pCoexSta->bBtBusy = FALSE;
- }
- else
- {
- pCoexSta->bBtBusy = TRUE;
- }
- }
- else if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType)
- {
- if(Ratio_STA < btBusyThresh)
- {
- pCoexSta->bBtBusy = FALSE;
- }
- else
- {
- pCoexSta->bBtBusy = TRUE;
- }
-
- if( (Ratio_STA < btBusyThresh) ||
- (Ratio_Act<180 && Ratio_STA<130) )
- {
- pCoexSta->bA2dpBusy = FALSE;
- }
- else
- {
- pCoexSta->bA2dpBusy = TRUE;
- }
- }
- }
-
- pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &pCoexSta->bBtBusy);
- pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_LIMITED_DIG, &pCoexSta->bBtBusy);
-
- if(bBtBusyTraffic != pCoexSta->bBtBusy)
- { // BT idle or BT non-idle
- bBtBusyTraffic = pCoexSta->bBtBusy;
- stateChange = TRUE;
- }
-
- if(stateChange)
- {
- if(!pCoexSta->bBtBusy)
- {
- halbtc8188c2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_RfShrink(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_CoexAllOff(pBtCoexist);
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0);
- }
- else
- {
- halbtc8188c2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8188c2ant_RfShrink(pBtCoexist, NORMAL_EXEC, TRUE);
- }
- }
-
- if(stateChange)
- {
- bRejApAggPkt = pCoexSta->bBtBusy;
- pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, &bRejApAggPkt);
- pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
- }
-}
-
-VOID
-halbtc8188c2ant_ActionA2dpBc4(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- u1Byte wifiRssiState;
- u4Byte wifiBw, wifiTrafficDir;
-
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0);
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir);
-
- if(pCoexSta->bBtBusy)
- {
- if(BTC_WIFI_BW_HT40 == wifiBw)
- {
- // fw mechanism first
- if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir)
- {
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0xc, 0x18);
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x20, FALSE);
- }
- else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir)
- {
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE);
- }
-
- // sw mechanism
- halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20);
- }
- else
- {
- wifiRssiState = halbtc8188c2ant_WifiRssiState(pBtCoexist, 0, 2, 47, 0);
-
- if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir)
- {
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0xc, 0x18);
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x20, FALSE);
- }
- else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir)
- {
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE);
- }
-
- // sw mechanism
- if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20);
- }
- else
- {
- halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20);
- }
- }
- }
- else
- {
- halbtc8188c2ant_CoexAllOff(pBtCoexist);
- }
-}
-
-VOID
-halbtc8188c2ant_ActionA2dpBc8(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- u1Byte wifiRssiState;
- u4Byte wifiBw, wifiTrafficDir;
- BOOLEAN bWifiBusy=FALSE;
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy);
- if(pCoexSta->bA2dpBusy && bWifiBusy)
- {
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir);
- wifiRssiState = halbtc8188c2ant_WifiRssiState(pBtCoexist, 0, 2, 47, 0);
-
- // fw mechanism first
- if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir)
- {
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0xc, 0x18);
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
- }
- else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir)
- {
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x10, 0x18);
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
- }
-
- // sw mechanism
- if(BTC_WIFI_BW_HT40 == wifiBw)
- {
- halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- else
- {
- if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- else
- {
- halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- }
- }
- else if(pCoexSta->bA2dpBusy)
- {
- // fw mechanism first
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, TRUE, 0x18, FALSE);
-
- // sw mechanism
- halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- else
- {
- halbtc8188c2ant_CoexAllOff(pBtCoexist);
- }
-}
-
-VOID
-halbtc8188c2ant_ActionA2dp(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- if(BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType)
- {
- halbtc8188c2ant_ActionA2dpBc4(pBtCoexist);
- }
- else if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType)
- {
- halbtc8188c2ant_ActionA2dpBc8(pBtCoexist);
- }
-}
-
-VOID
-halbtc8188c2ant_ActionPanBc4(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE;
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn);
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy);
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0);
- if(bBtHsOn)
- {
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE);
- }
- else
- {
- if(pCoexSta->bBtBusy && bWifiBusy)
- {
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x20, 0x10);
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
- }
- else
- {
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE);
- }
- }
- // sw mechanism
- halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
-}
-
-VOID
-halbtc8188c2ant_ActionPanBc8(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE;
- u1Byte wifiRssiState;
- u4Byte wifiBw, wifiTrafficDir;
- s4Byte wifiRssi;
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn);
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy);
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir);
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi);
-
- if(bBtHsOn)
- {
- halbtc8188c2ant_CoexAllOff(pBtCoexist);
- }
- else
- {
- wifiRssiState = halbtc8188c2ant_WifiRssiState(pBtCoexist, 0, 3, 25, 50);
-
- if(pCoexSta->bBtBusy && bWifiBusy)
- {
- if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
- {
- // fw mechanism first
- if(pCoexSta->bBtUplink)
- {
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x20, 0x20);
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
- }
- else
- {
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE);
- }
- // sw mechanism
- if(BTC_WIFI_BW_HT40 == wifiBw)
- {
- halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- }
- else
- {
- halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE);
- }
- halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- if(pCoexSta->bBtUplink)
- {
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- else
- {
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20);
- }
- }
- else if( (wifiRssiState == BTC_RSSI_STATE_MEDIUM) ||
- (wifiRssiState == BTC_RSSI_STATE_STAY_MEDIUM) )
- {
- // fw mechanism first
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x20, 0x20);
-
- if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir)
- {
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
- }
- else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir)
- {
- if(BTC_WIFI_BW_HT40 == wifiBw)
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);//BT_FW_NAV_ON);
- else
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
- }
- // sw mechanism
- if(BTC_WIFI_BW_HT40 == wifiBw)
- {
- halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- }
- else
- {
- halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE);
- }
- halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- else
- {
- // fw mechanism first
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x20, 0x20);
-
- if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir)
- {
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
- }
- else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir)
- {
- if(pCoexSta->bBtUplink)
- {
- if(BTC_WIFI_BW_HT40 == wifiBw)
- {
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);//BT_FW_NAV_ON);
- }
- else
- {
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
- }
- }
- else
- {
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
- }
- }
- // sw mechanism
- halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- }
- else if(pCoexSta->bBtBusy && !bWifiBusy && (wifiRssi < 30))
- {
- // fw mechanism first
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x0a, 0x20);
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
- // sw mechanism
- halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- else
- {
- halbtc8188c2ant_CoexAllOff(pBtCoexist);
- }
- }
-}
-
-VOID
-halbtc8188c2ant_ActionPan(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- if(BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType)
- {
- halbtc8188c2ant_ActionPanBc4(pBtCoexist);
- }
- else if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType)
- {
- halbtc8188c2ant_ActionPanBc8(pBtCoexist);
- }
-}
-
-VOID
-halbtc8188c2ant_ActionHid(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- u4Byte wifiBw, wifiTrafficDir;
- BOOLEAN bWifiBusy=FALSE;
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy);
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir);
- if(BTC_WIFI_BW_LEGACY == wifiBw)
- {
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE);
-
- halbtc8188c2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0x000000f0, 0x40000010);
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0xa0);
- }
- else if(!bWifiBusy)
- {
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0);
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE);
- }
- else if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir)
- {
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE);
-
- halbtc8188c2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0x000000f0, 0x40000010);
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0xa0);
- }
- else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir)
- {
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0);
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE);
- }
- // sw mechanism
- halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
-}
-
-
-VOID
-halbtc8188c2ant_ActionSco(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- u1Byte wifiRssiState;
- u4Byte wifiBw;
-
- if(BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType)
- {
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0);
-
- // fw mechanism
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE);
-
- // sw mechanism
- halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- else if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType)
- {
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
- if(BTC_WIFI_BW_HT40 == wifiBw)
- {
- // fw mechanism first
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE);
-
- // sw mechanism
- halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- else
- {
- wifiRssiState = halbtc8188c2ant_WifiRssiState(pBtCoexist, 0, 2, 47, 0);
- // fw mechanism first
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE);
-
- // sw mechanism
- if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- else
- {
- halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- }
- }
-}
-
-VOID
-halbtc8188c2ant_ActionHidA2dpBc4(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- u1Byte wifiRssiState;
- u4Byte wifiBw, wifiTrafficDir;
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir);
-
- if(pCoexSta->bBtBusy)
- {
- if(BTC_WIFI_BW_HT40 == wifiBw)
- {
- // fw mechanism first
- if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir)
- {
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x7, 0x20);
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x20, FALSE);
- }
- else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir)
- {
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE);
- }
-
- // sw mechanism
- halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18);
- }
- else
- {
- wifiRssiState = halbtc8188c2ant_WifiRssiState(pBtCoexist, 0, 2, 47, 0);
- // fw mechanism first
- if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir)
- {
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x7, 0x20);
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x20, FALSE);
- }
- else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir)
- {
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE);
- }
-
- // sw mechanism
- if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18);
- }
- else
- {
- halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18);
- }
- }
- }
- else
- {
- halbtc8188c2ant_CoexAllOff(pBtCoexist);
- }
-}
-VOID
-halbtc8188c2ant_ActionHidA2dpBc8(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- u1Byte wifiRssiState;
- u4Byte wifiBw;
-
- if(pCoexSta->bBtBusy)
- {
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
- if(BTC_WIFI_BW_HT40 == wifiBw)
- {
- // fw mechanism first
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE);
-
- // sw mechanism
- halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18);
- }
- else
- {
- wifiRssiState = halbtc8188c2ant_WifiRssiState(pBtCoexist, 0, 2, 47, 0);
- // fw mechanism
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE);
-
- // sw mechanism
- if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18);
- }
- else
- {
- halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18);
- }
- }
- }
- else
- {
- halbtc8188c2ant_CoexAllOff(pBtCoexist);
- }
-}
-
-VOID
-halbtc8188c2ant_ActionHidA2dp(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- if(BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType)
- {
- halbtc8188c2ant_ActionHidA2dpBc4(pBtCoexist);
- }
- else if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType)
- {
- halbtc8188c2ant_ActionHidA2dpBc8(pBtCoexist);
- }
-}
-
-VOID
-halbtc8188c2ant_ActionHidPanBc4(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE;
- u4Byte wifiBw, wifiTrafficDir;
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn);
-
- if(bBtHsOn)
- {
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE);
-
- halbtc8188c2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0x000000f0, 0x40000010);
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0xa0);
- }
- else
- {
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy);
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir);
- if(BTC_WIFI_BW_LEGACY == wifiBw)
- {
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE);
-
- halbtc8188c2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0x000000f0, 0x40000010);
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0xa0);
- }
- else if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir)
- {
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE);
-
- halbtc8188c2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0x000000f0, 0x40000010);
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0xa0);
- }
- else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir)
- {
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0);
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x20, 0x10);
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
- }
- else if(!bWifiBusy)
- {
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0);
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE);
- }
- }
- halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
-}
-VOID
-halbtc8188c2ant_ActionHidPanBc8(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE;
- u1Byte wifiRssiState;
- u4Byte wifiBw, wifiTrafficDir;
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn);
-
- if(!bBtHsOn)
- {
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy);
- wifiRssiState = halbtc8188c2ant_WifiRssiState(pBtCoexist, 0, 2, 25, 0);
- if((pCoexSta->bBtBusy && bWifiBusy))
- {
- // fw mechanism first
- if(pCoexSta->bBtUplink)
- {
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x15, 0x20);
- }
- else
- {
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x10, 0x20);
- }
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
-
- // sw mechanism
- if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
- {
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
- if(BTC_WIFI_BW_HT40 == wifiBw)
- {
- halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- else
- {
- halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- }
- else
- {
- halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- }
- else
- {
- halbtc8188c2ant_CoexAllOff(pBtCoexist);
- }
- }
- else
- {
- if(BTC_INTF_USB == pBtCoexist->chipInterface)
- {
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir);
- if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir)
- {
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE);
-
- halbtc8188c2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0x000000f0, 0x40000010);
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0xa0);
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18);
- }
- else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir)
- {
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18);
- }
- }
- else
- {
- if(pCoexSta->bBtBusy)
- {
- // fw mechanism
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE);
-
- // sw mechanism
- halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20);
- }
- else
- {
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- }
- }
-}
-
-VOID
-halbtc8188c2ant_ActionHidPan(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- if(BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType)
- {
- halbtc8188c2ant_ActionHidPanBc4(pBtCoexist);
- }
- else if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType)
- {
- halbtc8188c2ant_ActionHidPanBc8(pBtCoexist);
- }
-}
-
-VOID
-halbtc8188c2ant_ActionPanA2dpBc4(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE;
- u1Byte wifiRssiState;
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn);
-
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0);
- if(bBtHsOn)
- {
- if(pCoexSta->bBtBusy)
- {
- // fw mechanism
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE);
-
- // sw mechanism
- halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20);
- }
- else
- {
- halbtc8188c2ant_CoexAllOff(pBtCoexist);
- }
- }
- else
- {
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy);
- if(pCoexSta->bBtBusy && bWifiBusy)
- {
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x20, 0x10);
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
- }
- else
- {
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE);
- }
- // sw mechanism
- halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
-}
-VOID
-halbtc8188c2ant_ActionPanA2dpBc8(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE;
- u1Byte wifiRssiState;
- u4Byte wifiBw;
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn);
-
- if(!bBtHsOn)
- {
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy);
- wifiRssiState = halbtc8188c2ant_WifiRssiState(pBtCoexist, 0, 2, 25, 0);
- if((pCoexSta->bBtBusy && bWifiBusy))
- {
- // fw mechanism first
- if(pCoexSta->bBtUplink)
- {
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x15, 0x20);
- }
- else
- {
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x10, 0x20);
- }
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
-
- // sw mechanism
- if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
- {
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
- if(BTC_WIFI_BW_HT40 == wifiBw)
- {
- halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- else
- {
- halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- }
- else
- {
- halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- }
- else
- {
- halbtc8188c2ant_CoexAllOff(pBtCoexist);
- }
- }
- else
- {
- if(pCoexSta->bBtBusy)
- {
- // fw mechanism
- halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE);
-
- // sw mechanism
- halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20);
- }
- else
- {
- halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- }
-}
-
-VOID
-halbtc8188c2ant_ActionPanA2dp(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- if(BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType)
- {
- halbtc8188c2ant_ActionPanA2dpBc4(pBtCoexist);
- }
- else if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType)
- {
- halbtc8188c2ant_ActionPanA2dpBc8(pBtCoexist);
- }
-}
-
-//============================================================
-// extern function start with EXhalbtc8188c2ant_
-//============================================================
-VOID
-EXhalbtc8188c2ant_PowerOnSetting(
- IN PBTC_COEXIST pBtCoexist
- )
-{
-}
-
-VOID
-EXhalbtc8188c2ant_InitHwConfig(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bWifiOnly
- )
-{
- u1Byte u1Tmp=0;
-
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 2Ant Init HW Config!!\n"));
-
- // backup rf 0x1e value
- pCoexDm->btRf0x1eBackup =
- pBtCoexist->fBtcGetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xf0);
-
- if( (BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType) ||
- (BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType) )
- {
- u1Tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x4fd) & BIT0;
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x4fd, u1Tmp);
-
- halbtc8188c2ant_CoexTable(pBtCoexist, FORCE_EXEC, 0xaaaa9aaa, 0xffbd0040, 0x40000010);
- }
-}
-
-VOID
-EXhalbtc8188c2ant_InitCoexDm(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Coex Mechanism Init!!\n"));
-
- halbtc8188c2ant_InitCoexDm(pBtCoexist);
-}
-
-VOID
-EXhalbtc8188c2ant_DisplayCoexInfo(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo;
- PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo;
- pu1Byte cliBuf=pBtCoexist->cliBuf;
- u1Byte u1Tmp[4], i, btInfoExt, psTdmaCase=0;
- u4Byte u4Tmp[4];
-
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[BT Coexist info]============");
- CL_PRINTF(cliBuf);
-
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", "Ant PG number/ Ant mechanism:", \
- pBoardInfo->pgAntNum, pBoardInfo->btdmAntNum);
- CL_PRINTF(cliBuf);
-
- if(pBtCoexist->bManualControl)
- {
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "[Action Manual control]!!");
- CL_PRINTF(cliBuf);
- }
-
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d", "BT stack/ hci ext ver", \
- ((pStackInfo->bProfileNotified)? "Yes":"No"), pStackInfo->hciVersion);
- CL_PRINTF(cliBuf);
-
- // wifi status
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Wifi Status]============");
- CL_PRINTF(cliBuf);
- pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_WIFI_STATUS);
-
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[BT Status]============");
- CL_PRINTF(cliBuf);
-
- if(pStackInfo->bProfileNotified)
- {
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", "SCO/HID/PAN/A2DP", \
- pStackInfo->bScoExist, pStackInfo->bHidExist, pStackInfo->bPanExist, pStackInfo->bA2dpExist);
- CL_PRINTF(cliBuf);
-
- pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_BT_LINK_INFO);
- }
-
- // Sw mechanism
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Sw mechanism]============");
- CL_PRINTF(cliBuf);
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ", "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]", \
- pCoexDm->bCurAgcTableEn, pCoexDm->bCurAdcBackOff, pCoexDm->bCurDacSwingOn, pCoexDm->curDacSwingLvl);
- CL_PRINTF(cliBuf);
-
- // Fw mechanism
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Fw mechanism]============");
- CL_PRINTF(cliBuf);
-
- // Hw setting
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Hw setting]============");
- CL_PRINTF(cliBuf);
-
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "RF-A, 0x1e initVal", \
- pCoexDm->btRf0x1eBackup);
- CL_PRINTF(cliBuf);
-
- u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x40);
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x40", \
- u1Tmp[0]);
- CL_PRINTF(cliBuf);
-
- u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xc50);
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)", \
- u4Tmp[0]);
- CL_PRINTF(cliBuf);
-
- u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c4);
- u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c8);
- u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6cc);
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "0x6c4/0x6c8/0x6cc(coexTable)", \
- u4Tmp[0], u4Tmp[1], u4Tmp[2]);
- CL_PRINTF(cliBuf);
-
- pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_COEX_STATISTICS);
-}
-
-
-VOID
-EXhalbtc8188c2ant_IpsNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- )
-{
- if(BTC_IPS_ENTER == type)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS ENTER notify\n"));
- halbtc8188c2ant_CoexAllOff(pBtCoexist);
- }
- else if(BTC_IPS_LEAVE == type)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS LEAVE notify\n"));
- //halbtc8188c2ant_InitCoexDm(pBtCoexist);
- }
-}
-
-VOID
-EXhalbtc8188c2ant_LpsNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- )
-{
- if(BTC_LPS_ENABLE == type)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS ENABLE notify\n"));
- halbtc8188c2ant_CoexAllOff(pBtCoexist);
- }
- else if(BTC_LPS_DISABLE == type)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS DISABLE notify\n"));
- halbtc8188c2ant_InitCoexDm(pBtCoexist);
- }
-}
-
-VOID
-EXhalbtc8188c2ant_ScanNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- )
-{
- if(BTC_SCAN_START == type)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN START notify\n"));
- }
- else if(BTC_SCAN_FINISH == type)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN FINISH notify\n"));
- }
-}
-
-VOID
-EXhalbtc8188c2ant_ConnectNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- )
-{
- if(BTC_ASSOCIATE_START == type)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT START notify\n"));
- }
- else if(BTC_ASSOCIATE_FINISH == type)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT FINISH notify\n"));
- }
-}
-
-VOID
-EXhalbtc8188c2ant_MediaStatusNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- )
-{
- if(BTC_MEDIA_CONNECT == type)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA connect notify\n"));
- }
- else
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA disconnect notify\n"));
- }
-
-}
-
-VOID
-EXhalbtc8188c2ant_SpecialPacketNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- )
-{
- if(type == BTC_PACKET_DHCP)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], DHCP Packet notify\n"));
- }
-}
-
-VOID
-EXhalbtc8188c2ant_BtInfoNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN pu1Byte tmpBuf,
- IN u1Byte length
- )
-{
-}
-
-VOID
-EXhalbtc8188c2ant_HaltNotify(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Halt notify\n"));
-
- EXhalbtc8188c2ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT);
-}
-
-VOID
-EXhalbtc8188c2ant_Periodical(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- u1Byte algorithm;
-
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 2Ant Periodical!!\n"));
-
- // NOTE:
- // sw mechanism must be done after fw mechanism
- //
-
- if((BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType) ||
- (BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType) )
- {
- pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_GET_BT_RSSI, NULL);
-
- halbtc8188c2ant_MonitorBtState(pBtCoexist);
- algorithm = halbtc8188c2ant_ActionAlgorithm(pBtCoexist);
- pCoexDm->curAlgorithm = algorithm;
- switch(pCoexDm->curAlgorithm)
- {
- case BT_8188C_2ANT_COEX_ALGO_SCO:
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = SCO\n"));
- halbtc8188c2ant_ActionSco(pBtCoexist);
- break;
- case BT_8188C_2ANT_COEX_ALGO_HID:
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID\n"));
- halbtc8188c2ant_ActionHid(pBtCoexist);
- break;
- case BT_8188C_2ANT_COEX_ALGO_A2DP:
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = A2DP\n"));
- halbtc8188c2ant_ActionA2dp(pBtCoexist);
- break;
- case BT_8188C_2ANT_COEX_ALGO_PAN:
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN\n"));
- halbtc8188c2ant_ActionPan(pBtCoexist);
- break;
- case BT_8188C_2ANT_COEX_ALGO_HID_A2DP:
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID+A2DP\n"));
- halbtc8188c2ant_ActionHidA2dp(pBtCoexist);
- break;
- case BT_8188C_2ANT_COEX_ALGO_HID_PAN:
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN+HID\n"));
- halbtc8188c2ant_ActionHidPan(pBtCoexist);
- break;
- case BT_8188C_2ANT_COEX_ALGO_PAN_A2DP:
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN+A2DP\n"));
- halbtc8188c2ant_ActionPanA2dp(pBtCoexist);
- break;
- default:
- break;
- }
- }
-}
-
-
-#endif
-
diff --git a/hal/btc/HalBtc8188c2Ant.h b/hal/btc/HalBtc8188c2Ant.h
deleted file mode 100644
index e4aa715..0000000
--- a/hal/btc/HalBtc8188c2Ant.h
+++ /dev/null
@@ -1,149 +0,0 @@
-//===========================================
-// The following is for 8188C 2Ant BT Co-exist definition
-//===========================================
-#define BTC_RSSI_COEX_THRESH_TOL_8188C_2ANT 6
-
-typedef enum _BT_INFO_SRC_8188C_2ANT{
- BT_INFO_SRC_8188C_2ANT_WIFI_FW = 0x0,
- BT_INFO_SRC_8188C_2ANT_BT_RSP = 0x1,
- BT_INFO_SRC_8188C_2ANT_BT_ACTIVE_SEND = 0x2,
- BT_INFO_SRC_8188C_2ANT_MAX
-}BT_INFO_SRC_8188C_2ANT,*PBT_INFO_SRC_8188C_2ANT;
-
-typedef enum _BT_8188C_2ANT_BT_STATUS{
- BT_8188C_2ANT_BT_STATUS_IDLE = 0x0,
- BT_8188C_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
- BT_8188C_2ANT_BT_STATUS_NON_IDLE = 0x2,
- BT_8188C_2ANT_BT_STATUS_MAX
-}BT_8188C_2ANT_BT_STATUS,*PBT_8188C_2ANT_BT_STATUS;
-
-typedef enum _BT_8188C_2ANT_COEX_ALGO{
- BT_8188C_2ANT_COEX_ALGO_UNDEFINED = 0x0,
- BT_8188C_2ANT_COEX_ALGO_SCO = 0x1,
- BT_8188C_2ANT_COEX_ALGO_HID = 0x2,
- BT_8188C_2ANT_COEX_ALGO_A2DP = 0x3,
- BT_8188C_2ANT_COEX_ALGO_PAN = 0x4,
- BT_8188C_2ANT_COEX_ALGO_HID_A2DP = 0x5,
- BT_8188C_2ANT_COEX_ALGO_HID_PAN = 0x6,
- BT_8188C_2ANT_COEX_ALGO_PAN_A2DP = 0x7,
- BT_8188C_2ANT_COEX_ALGO_MAX
-}BT_8188C_2ANT_COEX_ALGO,*PBT_8188C_2ANT_COEX_ALGO;
-
-typedef struct _COEX_DM_8188C_2ANT{
- // fw mechanism
- BOOLEAN bPreBalanceOn;
- BOOLEAN bCurBalanceOn;
-
- // diminishWifi
- BOOLEAN bPreDacOn;
- BOOLEAN bCurDacOn;
- BOOLEAN bPreInterruptOn;
- BOOLEAN bCurInterruptOn;
- u1Byte preFwDacSwingLvl;
- u1Byte curFwDacSwingLvl;
- BOOLEAN bPreNavOn;
- BOOLEAN bCurNavOn;
-
- // sw mechanism
- BOOLEAN bPreRfRxLpfShrink;
- BOOLEAN bCurRfRxLpfShrink;
- u4Byte btRf0x1eBackup;
- BOOLEAN bPreLowPenaltyRa;
- BOOLEAN bCurLowPenaltyRa;
- BOOLEAN bPreDacSwingOn;
- u4Byte preDacSwingLvl;
- BOOLEAN bCurDacSwingOn;
- u4Byte curDacSwingLvl;
- BOOLEAN bPreAdcBackOff;
- BOOLEAN bCurAdcBackOff;
- BOOLEAN bPreAgcTableEn;
- BOOLEAN bCurAgcTableEn;
- //u4Byte preVal0x6c0;
- //u4Byte curVal0x6c0;
- u4Byte preVal0x6c4;
- u4Byte curVal0x6c4;
- u4Byte preVal0x6c8;
- u4Byte curVal0x6c8;
- u4Byte preVal0x6cc;
- u4Byte curVal0x6cc;
- //BOOLEAN bLimitedDig;
-
- // algorithm related
- u1Byte preAlgorithm;
- u1Byte curAlgorithm;
- //u1Byte btStatus;
- //u1Byte wifiChnlInfo[3];
-} COEX_DM_8188C_2ANT, *PCOEX_DM_8188C_2ANT;
-
-typedef struct _COEX_STA_8188C_2ANT{
- u1Byte preWifiRssiState[4];
- BOOLEAN bBtBusy;
- BOOLEAN bBtUplink;
- BOOLEAN bBtDownLink;
- BOOLEAN bA2dpBusy;
-}COEX_STA_8188C_2ANT, *PCOEX_STA_8188C_2ANT;
-
-//===========================================
-// The following is interface which will notify coex module.
-//===========================================
-VOID
-EXhalbtc8188c2ant_PowerOnSetting(
- IN PBTC_COEXIST pBtCoexist
- );
-VOID
-EXhalbtc8188c2ant_InitHwConfig(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bWifiOnly
- );
-VOID
-EXhalbtc8188c2ant_InitCoexDm(
- IN PBTC_COEXIST pBtCoexist
- );
-VOID
-EXhalbtc8188c2ant_IpsNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- );
-VOID
-EXhalbtc8188c2ant_LpsNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- );
-VOID
-EXhalbtc8188c2ant_ScanNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- );
-VOID
-EXhalbtc8188c2ant_ConnectNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- );
-VOID
-EXhalbtc8188c2ant_MediaStatusNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- );
-VOID
-EXhalbtc8188c2ant_SpecialPacketNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- );
-VOID
-EXhalbtc8188c2ant_HaltNotify(
- IN PBTC_COEXIST pBtCoexist
- );
-VOID
-EXhalbtc8188c2ant_Periodical(
- IN PBTC_COEXIST pBtCoexist
- );
-VOID
-EXhalbtc8188c2ant_BtInfoNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN pu1Byte tmpBuf,
- IN u1Byte length
- );
-VOID
-EXhalbtc8188c2ant_DisplayCoexInfo(
- IN PBTC_COEXIST pBtCoexist
- );
diff --git a/hal/btc/HalBtc8192d2Ant.c b/hal/btc/HalBtc8192d2Ant.c
deleted file mode 100644
index 0cb38ee..0000000
--- a/hal/btc/HalBtc8192d2Ant.c
+++ /dev/null
@@ -1,1992 +0,0 @@
-//============================================================
-// Description:
-//
-// This file is for 92D BT 2 Antenna Co-exist mechanism
-//
-// By cosa 02/11/2011
-//
-//============================================================
-
-//============================================================
-// include files
-//============================================================
-#include "Mp_Precomp.h"
-
-#if WPP_SOFTWARE_TRACE
-#include "HalBtc8192d2Ant.tmh"
-#endif
-
-#if(BT_30_SUPPORT == 1)
-//============================================================
-// Global variables, these are static variables
-//============================================================
-static COEX_DM_8192D_2ANT GLCoexDm8192d2Ant;
-static PCOEX_DM_8192D_2ANT pCoexDm=&GLCoexDm8192d2Ant;
-static COEX_STA_8192D_2ANT GLCoexSta8192d2Ant;
-static PCOEX_STA_8192D_2ANT pCoexSta=&GLCoexSta8192d2Ant;
-
-//============================================================
-// local function start with btdm_
-//============================================================
-u1Byte
-halbtc8192d2ant_WifiRssiState(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte index,
- IN u1Byte levelNum,
- IN u1Byte rssiThresh,
- IN u1Byte rssiThresh1
- )
-{
- s4Byte wifiRssi=0;
- u1Byte wifiRssiState=pCoexSta->preWifiRssiState[index];
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi);
-
- if(levelNum == 2)
- {
- if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) ||
- (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW))
- {
- if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8192D_2ANT))
- {
- wifiRssiState = BTC_RSSI_STATE_HIGH;
- }
- else
- {
- wifiRssiState = BTC_RSSI_STATE_STAY_LOW;
- }
- }
- else
- {
- if(wifiRssi < rssiThresh)
- {
- wifiRssiState = BTC_RSSI_STATE_LOW;
- }
- else
- {
- wifiRssiState = BTC_RSSI_STATE_STAY_HIGH;
- }
- }
- }
- else if(levelNum == 3)
- {
- if(rssiThresh > rssiThresh1)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi RSSI thresh error!!\n"));
- return pCoexSta->preWifiRssiState[index];
- }
-
- if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) ||
- (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW))
- {
- if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8192D_2ANT))
- {
- wifiRssiState = BTC_RSSI_STATE_MEDIUM;
- }
- else
- {
- wifiRssiState = BTC_RSSI_STATE_STAY_LOW;
- }
- }
- else if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_MEDIUM) ||
- (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_MEDIUM))
- {
- if(wifiRssi >= (rssiThresh1+BTC_RSSI_COEX_THRESH_TOL_8192D_2ANT))
- {
- wifiRssiState = BTC_RSSI_STATE_HIGH;
- }
- else if(wifiRssi < rssiThresh)
- {
- wifiRssiState = BTC_RSSI_STATE_LOW;
- }
- else
- {
- wifiRssiState = BTC_RSSI_STATE_STAY_MEDIUM;
- }
- }
- else
- {
- if(wifiRssi < rssiThresh1)
- {
- wifiRssiState = BTC_RSSI_STATE_MEDIUM;
- }
- else
- {
- wifiRssiState = BTC_RSSI_STATE_STAY_HIGH;
- }
- }
- }
-
- pCoexSta->preWifiRssiState[index] = wifiRssiState;
-
- return wifiRssiState;
-}
-
-u1Byte
-halbtc8192d2ant_ActionAlgorithm(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo;
- BOOLEAN bBtHsOn=FALSE;
- u1Byte algorithm=BT_8192D_2ANT_COEX_ALGO_UNDEFINED;
- u1Byte numOfDiffProfile=0;
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn);
-
- if(!pStackInfo->bBtLinkExist)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], No profile exists!!!\n"));
- return algorithm;
- }
-
- if(pStackInfo->bScoExist)
- numOfDiffProfile++;
- if(pStackInfo->bHidExist)
- numOfDiffProfile++;
- if(pStackInfo->bPanExist)
- numOfDiffProfile++;
- if(pStackInfo->bA2dpExist)
- numOfDiffProfile++;
-
- if(pStackInfo->bScoExist)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO algorithm\n"));
- algorithm = BT_8192D_2ANT_COEX_ALGO_SCO;
- }
- else
- {
- if(numOfDiffProfile == 1)
- {
- if(pStackInfo->bHidExist)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID only\n"));
- algorithm = BT_8192D_2ANT_COEX_ALGO_HID;
- }
- else if(pStackInfo->bA2dpExist)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP only\n"));
- algorithm = BT_8192D_2ANT_COEX_ALGO_A2DP;
- }
- else if(pStackInfo->bPanExist)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN only\n"));
- algorithm = BT_8192D_2ANT_COEX_ALGO_PAN;
- }
- }
- else
- {
- if( pStackInfo->bHidExist &&
- pStackInfo->bA2dpExist )
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + A2DP\n"));
- algorithm = BT_8192D_2ANT_COEX_ALGO_HID_A2DP;
- }
- else if( pStackInfo->bHidExist &&
- pStackInfo->bPanExist )
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + PAN\n"));
- algorithm = BT_8192D_2ANT_COEX_ALGO_HID_PAN;
- }
- else if( pStackInfo->bPanExist &&
- pStackInfo->bA2dpExist )
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN + A2DP\n"));
- algorithm = BT_8192D_2ANT_COEX_ALGO_PAN_A2DP;
- }
- }
- }
- return algorithm;
-}
-
-VOID
-halbtc8192d2ant_SetFwBalance(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bBalanceOn,
- IN u1Byte ms0,
- IN u1Byte ms1
- )
-{
- u1Byte H2C_Parameter[3] ={0};
-
- if(bBalanceOn)
- {
- H2C_Parameter[2] = 1;
- H2C_Parameter[1] = ms1;
- H2C_Parameter[0] = ms0;
- }
- else
- {
- H2C_Parameter[2] = 0;
- H2C_Parameter[1] = 0;
- H2C_Parameter[0] = 0;
- }
-
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Balance=[%s:%dms:%dms], write 0xc=0x%x\n",
- bBalanceOn?"ON":"OFF", ms0, ms1,
- H2C_Parameter[0]<<16|H2C_Parameter[1]<<8|H2C_Parameter[2]));
-
- pBtCoexist->fBtcFillH2c(pBtCoexist, 0xc, 3, H2C_Parameter);
-}
-
-VOID
-halbtc8192d2ant_Balance(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bForceExec,
- IN BOOLEAN bBalanceOn,
- IN u1Byte ms0,
- IN u1Byte ms1
- )
-{
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Balance %s\n",
- (bForceExec? "force to":""), (bBalanceOn? "ON":"OFF")));
- pCoexDm->bCurBalanceOn = bBalanceOn;
-
- if(!bForceExec)
- {
- if(pCoexDm->bPreBalanceOn == pCoexDm->bCurBalanceOn)
- return;
- }
- halbtc8192d2ant_SetFwBalance(pBtCoexist, bBalanceOn, ms0, ms1);
-
- pCoexDm->bPreBalanceOn = pCoexDm->bCurBalanceOn;
-}
-
-VOID
-halbtc8192d2ant_SetFwDiminishWifi(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bDacOn,
- IN BOOLEAN bInterruptOn,
- IN u1Byte fwDacSwingLvl,
- IN BOOLEAN bNavOn
- )
-{
- u1Byte H2C_Parameter[3] ={0};
-
- if((pBtCoexist->stackInfo.minBtRssi <= -5) && (fwDacSwingLvl == 0x20))
- {
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], DiminishWiFi 0x20 original, but set 0x18 for Low RSSI!\n"));
- fwDacSwingLvl = 0x18;
- }
-
- H2C_Parameter[2] = 0;
- H2C_Parameter[1] = fwDacSwingLvl;
- H2C_Parameter[0] = 0;
- if(bDacOn)
- {
- H2C_Parameter[2] |= 0x01; //BIT0
- if(bInterruptOn)
- {
- H2C_Parameter[2] |= 0x02; //BIT1
- }
- }
- if(bNavOn)
- {
- H2C_Parameter[2] |= 0x08; //BIT3
- }
-
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], bDacOn=%s, bInterruptOn=%s, bNavOn=%s, write 0x12=0x%x\n",
- (bDacOn?"ON":"OFF"), (bInterruptOn?"ON":"OFF"), (bNavOn?"ON":"OFF"),
- (H2C_Parameter[0]<<16|H2C_Parameter[1]<<8|H2C_Parameter[2])));
- pBtCoexist->fBtcFillH2c(pBtCoexist, 0x12, 3, H2C_Parameter);
-}
-
-
-VOID
-halbtc8192d2ant_DiminishWifi(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bForceExec,
- IN BOOLEAN bDacOn,
- IN BOOLEAN bInterruptOn,
- IN u1Byte fwDacSwingLvl,
- IN BOOLEAN bNavOn
- )
-{
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s set Diminish Wifi, bDacOn=%s, bInterruptOn=%s, fwDacSwingLvl=%d, bNavOn=%s\n",
- (bForceExec? "force to":""), (bDacOn? "ON":"OFF"), (bInterruptOn? "ON":"OFF"), fwDacSwingLvl, (bNavOn? "ON":"OFF")));
-
- pCoexDm->bCurDacOn = bDacOn;
- pCoexDm->bCurInterruptOn = bInterruptOn;
- pCoexDm->curFwDacSwingLvl = fwDacSwingLvl;
- pCoexDm->bCurNavOn = bNavOn;
-
- if(!bForceExec)
- {
- if( (pCoexDm->bPreDacOn==pCoexDm->bCurDacOn) &&
- (pCoexDm->bPreInterruptOn==pCoexDm->bCurInterruptOn) &&
- (pCoexDm->preFwDacSwingLvl==pCoexDm->curFwDacSwingLvl) &&
- (pCoexDm->bPreNavOn==pCoexDm->bCurNavOn) )
- return;
- }
- halbtc8192d2ant_SetFwDiminishWifi(pBtCoexist, bDacOn, bInterruptOn, fwDacSwingLvl, bNavOn);
-
- pCoexDm->bPreDacOn = pCoexDm->bCurDacOn;
- pCoexDm->bPreInterruptOn = pCoexDm->bCurInterruptOn;
- pCoexDm->preFwDacSwingLvl = pCoexDm->curFwDacSwingLvl;
- pCoexDm->bPreNavOn = pCoexDm->bCurNavOn;
-}
-
-VOID
-halbtc8192d2ant_SetSwRfRxLpfCorner(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bRxRfShrinkOn
- )
-{
- if(bRxRfShrinkOn)
- {
- //Shrink RF Rx LPF corner
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Shrink RF Rx LPF corner!!\n"));
- pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, 0xf2ff7);
- }
- else
- {
- //Resume RF Rx LPF corner
- // After initialized, we can use pCoexDm->btRf0x1eBackup
- if(pBtCoexist->bInitilized)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Resume RF Rx LPF corner!!\n"));
- pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, pCoexDm->btRf0x1eBackup);
- }
- }
-}
-
-
-VOID
-halbtc8192d2ant_RfShrink(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bForceExec,
- IN BOOLEAN bRxRfShrinkOn
- )
-{
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Rx RF Shrink = %s\n",
- (bForceExec? "force to":""), ((bRxRfShrinkOn)? "ON":"OFF")));
- pCoexDm->bCurRfRxLpfShrink = bRxRfShrinkOn;
-
- if(!bForceExec)
- {
- if(pCoexDm->bPreRfRxLpfShrink == pCoexDm->bCurRfRxLpfShrink)
- return;
- }
- halbtc8192d2ant_SetSwRfRxLpfCorner(pBtCoexist, pCoexDm->bCurRfRxLpfShrink);
-
- pCoexDm->bPreRfRxLpfShrink = pCoexDm->bCurRfRxLpfShrink;
-}
-
-VOID
-halbtc8192d2ant_SetSwPenaltyTxRateAdaptive(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bLowPenaltyRa
- )
-{
- u1Byte tmpU1;
-
- tmpU1 = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x4fd);
- if(bLowPenaltyRa)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Tx rate adaptive, set low penalty!!\n"));
- tmpU1 &= ~BIT2;
- }
- else
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Tx rate adaptive, set normal!!\n"));
- tmpU1 |= BIT2;
- }
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x4fd, tmpU1);
-}
-
-VOID
-halbtc8192d2ant_LowPenaltyRa(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bForceExec,
- IN BOOLEAN bLowPenaltyRa
- )
-{
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn LowPenaltyRA = %s\n",
- (bForceExec? "force to":""), ((bLowPenaltyRa)? "ON":"OFF")));
- pCoexDm->bCurLowPenaltyRa = bLowPenaltyRa;
-
- if(!bForceExec)
- {
- if(pCoexDm->bPreLowPenaltyRa == pCoexDm->bCurLowPenaltyRa)
- return;
- }
- halbtc8192d2ant_SetSwPenaltyTxRateAdaptive(pBtCoexist, pCoexDm->bCurLowPenaltyRa);
-
- pCoexDm->bPreLowPenaltyRa = pCoexDm->bCurLowPenaltyRa;
-}
-
-VOID
-halbtc8192d2ant_SetSwFullTimeDacSwing(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bSwDacSwingOn,
- IN u4Byte swDacSwingLvl
- )
-{
- u4Byte dacSwingLvl;
-
- if(bSwDacSwingOn)
- {
- if((pBtCoexist->stackInfo.minBtRssi <= -5) && (swDacSwingLvl == 0x20))
- {
- dacSwingLvl = 0x18;
- }
- else
- {
- dacSwingLvl = swDacSwingLvl;
- }
- pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x880, 0xfc000000, dacSwingLvl);
- }
- else
- {
- pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x880, 0xfc000000, 0x30);
- }
-}
-
-VOID
-halbtc8192d2ant_DacSwing(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bForceExec,
- IN BOOLEAN bDacSwingOn,
- IN u4Byte dacSwingLvl
- )
-{
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn DacSwing=%s, dacSwingLvl=0x%x\n",
- (bForceExec? "force to":""), ((bDacSwingOn)? "ON":"OFF"), dacSwingLvl));
- pCoexDm->bCurDacSwingOn = bDacSwingOn;
- pCoexDm->curDacSwingLvl = dacSwingLvl;
-
- if(!bForceExec)
- {
- if( (pCoexDm->bPreDacSwingOn == pCoexDm->bCurDacSwingOn) &&
- (pCoexDm->preDacSwingLvl == pCoexDm->curDacSwingLvl) )
- return;
- }
- delay_ms(30);
- halbtc8192d2ant_SetSwFullTimeDacSwing(pBtCoexist, bDacSwingOn, dacSwingLvl);
-
- pCoexDm->bPreDacSwingOn = pCoexDm->bCurDacSwingOn;
- pCoexDm->preDacSwingLvl = pCoexDm->curDacSwingLvl;
-}
-
-VOID
-halbtc8192d2ant_SetAdcBackOff(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bAdcBackOff
- )
-{
- if(bAdcBackOff)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB BackOff Level On!\n"));
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc04,0x3a07611);
- }
- else
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB BackOff Level Off!\n"));
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc04,0x3a05611);
- }
-}
-
-VOID
-halbtc8192d2ant_AdcBackOff(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bForceExec,
- IN BOOLEAN bAdcBackOff
- )
-{
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn AdcBackOff = %s\n",
- (bForceExec? "force to":""), ((bAdcBackOff)? "ON":"OFF")));
- pCoexDm->bCurAdcBackOff = bAdcBackOff;
-
- if(!bForceExec)
- {
- if(pCoexDm->bPreAdcBackOff == pCoexDm->bCurAdcBackOff)
- return;
- }
- halbtc8192d2ant_SetAdcBackOff(pBtCoexist, pCoexDm->bCurAdcBackOff);
-
- pCoexDm->bPreAdcBackOff = pCoexDm->bCurAdcBackOff;
-}
-
-VOID
-halbtc8192d2ant_SetAgcTable(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bAgcTableEn
- )
-{
- u1Byte rssiAdjustVal=0;
-
- if(bAgcTableEn)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table On!\n"));
- pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1a, 0xfffff, 0xa99);
- pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0xd4000);
-
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b000001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b010001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b020001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b030001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b040001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b050001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b060001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b070001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b080001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b090001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b0A0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b0B0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7a0C0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x790D0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x780E0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x770F0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x76100001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x75110001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x74120001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x73130001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x72140001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x71150001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x70160001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6f170001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6e180001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6d190001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6c1A0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6b1B0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6a1C0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x691D0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x4f1E0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x4e1F0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x4d200001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x4c210001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x4b220001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x4a230001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x49240001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x48250001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x47260001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x46270001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x45280001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x44290001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x432A0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x422B0001);
-
- rssiAdjustVal = 12;
- }
- else
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table Off!\n"));
- pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1a, 0xfffff, 0x30a99);
- pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0xdc000);
-
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7B000001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7B010001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7B020001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7B030001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7B040001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7B050001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7B060001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7A070001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x79080001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x78090001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x770A0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x760B0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x750C0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x740D0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x730E0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x720F0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x71100001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x70110001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6F120001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6E130001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6D140001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6C150001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6B160001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6A170001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x69180001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x68190001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x671A0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x661B0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x651C0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x641D0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x631E0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x621F0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x61200001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x60210001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x49220001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x48230001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x47240001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x46250001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x45260001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x44270001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x43280001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x42290001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x412A0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x402B0001);
- }
-
- // set rssiAdjustVal for wifi module.
- pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON, &rssiAdjustVal);
-}
-
-
-
-VOID
-halbtc8192d2ant_AgcTable(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bForceExec,
- IN BOOLEAN bAgcTableEn
- )
-{
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s %s Agc Table\n",
- (bForceExec? "force to":""), ((bAgcTableEn)? "Enable":"Disable")));
- pCoexDm->bCurAgcTableEn = bAgcTableEn;
-
- if(!bForceExec)
- {
- if(pCoexDm->bPreAgcTableEn == pCoexDm->bCurAgcTableEn)
- return;
- }
- halbtc8192d2ant_SetAgcTable(pBtCoexist, bAgcTableEn);
-
- pCoexDm->bPreAgcTableEn = pCoexDm->bCurAgcTableEn;
-}
-
-VOID
-halbtc8192d2ant_SetCoexTable(
- IN PBTC_COEXIST pBtCoexist,
- IN u4Byte val0x6c4,
- IN u4Byte val0x6c8,
- IN u4Byte val0x6cc
- )
-{
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], set coex table, set 0x6c4=0x%x\n", val0x6c4));
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c4, val0x6c4);
-
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], set coex table, set 0x6c8=0x%x\n", val0x6c8));
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c8, val0x6c8);
-
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], set coex table, set 0x6cc=0x%x\n", val0x6cc));
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6cc, val0x6cc);
-}
-
-VOID
-halbtc8192d2ant_CoexTable(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bForceExec,
- IN u4Byte val0x6c4,
- IN u4Byte val0x6c8,
- IN u4Byte val0x6cc
- )
-{
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s write Coex Table 0x6c4=0x%x, 0x6c8=0x%x, 0x6cc=0x%x\n",
- (bForceExec? "force to":""), val0x6c4, val0x6c8, val0x6cc));
- pCoexDm->curVal0x6c4 = val0x6c4;
- pCoexDm->curVal0x6c8 = val0x6c8;
- pCoexDm->curVal0x6cc = val0x6cc;
-
- if(!bForceExec)
- {
- if( (pCoexDm->preVal0x6c4 == pCoexDm->curVal0x6c4) &&
- (pCoexDm->preVal0x6c8 == pCoexDm->curVal0x6c8) &&
- (pCoexDm->preVal0x6cc == pCoexDm->curVal0x6cc) )
- return;
- }
- halbtc8192d2ant_SetCoexTable(pBtCoexist, val0x6c4, val0x6c8, val0x6cc);
-
- pCoexDm->preVal0x6c4 = pCoexDm->curVal0x6c4;
- pCoexDm->preVal0x6c8 = pCoexDm->curVal0x6c8;
- pCoexDm->preVal0x6cc = pCoexDm->curVal0x6cc;
-}
-
-VOID
-halbtc8192d2ant_CoexAllOff(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- // fw mechanism
- halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE);
-
- // sw mechanism
- halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
-}
-VOID
-halbtc8192d2ant_InitCoexDm(
- IN PBTC_COEXIST pBtCoexist
- )
-{
-}
-
-VOID
-halbtc8192d2ant_MonitorBtEnableDisable(
- IN PBTC_COEXIST pBtCoexist,
- IN u4Byte btActive
- )
-{
- static BOOLEAN bPreBtDisabled=FALSE;
- static u4Byte btDisableCnt=0;
- BOOLEAN bBtDisabled=FALSE, bForceToRoam=FALSE;
- u4Byte u4Tmp=0;
-
- // This function check if bt is disabled
- if(btActive)
- {
- btDisableCnt = 0;
- bBtDisabled = FALSE;
- pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled);
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is enabled !!\n"));
- }
- else
- {
- btDisableCnt++;
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], bt all counters=0, %d times!!\n",
- btDisableCnt));
- if(btDisableCnt >= 2)
- {
- bBtDisabled = TRUE;
- pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled);
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is disabled !!\n"));
- }
- }
- if(bPreBtDisabled != bBtDisabled)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is from %s to %s!!\n",
- (bPreBtDisabled ? "disabled":"enabled"),
- (bBtDisabled ? "disabled":"enabled")));
-
- bForceToRoam = TRUE;
- pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_FORCE_TO_ROAM, &bForceToRoam);
-
- bPreBtDisabled = bBtDisabled;
- }
-}
-
-VOID
-halbtc8192d2ant_MonitorBtState(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- BOOLEAN stateChange=FALSE;
- u4Byte BT_Polling, Ratio_Act, Ratio_STA;
- u4Byte BT_Active, BT_State;
- u4Byte regBTActive=0, regBTState=0, regBTPolling=0;
- u4Byte btBusyThresh=0;
- u4Byte fwVer=0;
- static BOOLEAN bBtBusyTraffic=FALSE;
- BOOLEAN bRejApAggPkt=FALSE;
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer);
-
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], FirmwareVersion = 0x%x(%d)\n", fwVer, fwVer));
-
- regBTActive = 0x444;
- regBTState = 0x448;
- regBTPolling = 0x44c;
-
- btBusyThresh = 40;
-
- BT_Active = pBtCoexist->fBtcRead4Byte(pBtCoexist, regBTActive);
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT_Active(0x%x)=0x%x\n", regBTActive, BT_Active));
- BT_Active = BT_Active & 0x00ffffff;
-
- BT_State = pBtCoexist->fBtcRead4Byte(pBtCoexist, regBTState);
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT_State(0x%x)=0x%x\n", regBTState, BT_State));
- BT_State = BT_State & 0x00ffffff;
-
- BT_Polling = pBtCoexist->fBtcRead4Byte(pBtCoexist, regBTPolling);
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT_Polling(0x%x)=0x%x\n", regBTPolling, BT_Polling));
-
- if(BT_Active==0xffffffff && BT_State==0xffffffff && BT_Polling==0xffffffff )
- return;
-
- // 2011/05/04 MH For Slim combo test meet a problem. Surprise remove and WLAN is running
- // DHCP process. At the same time, the register read value might be zero. And cause BSOD 0x7f
- // EXCEPTION_DIVIDED_BY_ZERO. In This case, the stack content may always be wrong due to
- // HW divide trap.
- if (BT_Polling==0)
- return;
-
- halbtc8192d2ant_MonitorBtEnableDisable(pBtCoexist, BT_Active);
-
- Ratio_Act = BT_Active*1000/BT_Polling;
- Ratio_STA = BT_State*1000/BT_Polling;
-
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Ratio_Act=%d\n", Ratio_Act));
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Ratio_STA=%d\n", Ratio_STA));
-
- if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType)
- {
- if(Ratio_STA < 60) // BT PAN idle
- {
- }
- else
- {
- // Check if BT PAN (under BT 2.1) is uplink or downlink
- if((Ratio_Act/Ratio_STA) < 2)
- { // BT PAN Uplink
- pCoexSta->bBtUplink = TRUE;
- }
- else
- { // BT PAN downlink
- pCoexSta->bBtUplink = FALSE;
- }
- }
- }
-
- // Check BT is idle or not
- if(!pBtCoexist->stackInfo.bBtLinkExist)
- {
- pCoexSta->bBtBusy = FALSE;
- }
- else
- {
- if(BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType)
- {
- if(Ratio_Act<20)
- {
- pCoexSta->bBtBusy = FALSE;
- }
- else
- {
- pCoexSta->bBtBusy = TRUE;
- }
- }
- else if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType)
- {
- if(Ratio_STA < btBusyThresh)
- {
- pCoexSta->bBtBusy = FALSE;
- }
- else
- {
- pCoexSta->bBtBusy = TRUE;
- }
-
- if( (Ratio_STA < btBusyThresh) ||
- (Ratio_Act<180 && Ratio_STA<130) )
- {
- pCoexSta->bA2dpBusy = FALSE;
- }
- else
- {
- pCoexSta->bA2dpBusy = TRUE;
- }
- }
- }
-
- pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &pCoexSta->bBtBusy);
- pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_LIMITED_DIG, &pCoexSta->bBtBusy);
-
- if(bBtBusyTraffic != pCoexSta->bBtBusy)
- { // BT idle or BT non-idle
- bBtBusyTraffic = pCoexSta->bBtBusy;
- stateChange = TRUE;
- }
-
- if(stateChange)
- {
- if(!pCoexSta->bBtBusy)
- {
- halbtc8192d2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8192d2ant_RfShrink(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8192d2ant_CoexAllOff(pBtCoexist);
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0);
- }
- else
- {
- halbtc8192d2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8192d2ant_RfShrink(pBtCoexist, NORMAL_EXEC, TRUE);
- }
- }
-
- if(stateChange)
- {
- bRejApAggPkt = pCoexSta->bBtBusy;
- pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, &bRejApAggPkt);
- pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
- }
-}
-
-VOID
-halbtc8192d2ant_ActionA2dp(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- u1Byte wifiRssiState, wifiRssiState1=BTC_RSSI_STATE_HIGH;
- u4Byte wifiBw, wifiTrafficDir;
- BOOLEAN bWifiBusy=FALSE;
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy);
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir);
-
- wifiRssiState = halbtc8192d2ant_WifiRssiState(pBtCoexist, 0, 2, 47, 0);
- if(pCoexSta->bA2dpBusy && bWifiBusy)
- {
- if(BTC_WIFI_BW_HT40 == wifiBw)
- {
- wifiRssiState1 = halbtc8192d2ant_WifiRssiState(pBtCoexist, 1, 2, 47, 0);
- }
- else
- {
- if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir)
- {
- wifiRssiState1 = halbtc8192d2ant_WifiRssiState(pBtCoexist, 1, 2, 25, 0);
- }
- else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir)
- {
- wifiRssiState1 = halbtc8192d2ant_WifiRssiState(pBtCoexist, 1, 2, 40, 0);
- }
- }
-
- // fw mechanism first
- if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir)
- {
- halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0xc, 0x18);
- halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
- }
- else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir)
- {
- halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x10, 0x18);
- halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
- }
-
- // sw mechanism
- if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE);
- }
- else
- {
- halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- }
-
- if(BTC_WIFI_BW_HT40 == wifiBw)
- {
- halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- else
- {
- if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- else
- {
- halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- }
- }
- else if(pCoexSta->bA2dpBusy)
- {
- // fw mechanism first
- halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, TRUE, 0x18, FALSE);
-
- // sw mechanism
- halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- else
- {
- halbtc8192d2ant_CoexAllOff(pBtCoexist);
- }
-}
-
-VOID
-halbtc8192d2ant_ActionPan(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE;
- u1Byte wifiRssiState, wifiRssiState1;
- u4Byte wifiBw, wifiTrafficDir;
- s4Byte wifiRssi;
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn);
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy);
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir);
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi);
-
- if(bBtHsOn)
- {
- halbtc8192d2ant_CoexAllOff(pBtCoexist);
- }
- else
- {
- wifiRssiState = halbtc8192d2ant_WifiRssiState(pBtCoexist, 0, 3, 25, 50);
- if(BTC_WIFI_BW_HT40 == wifiBw)
- {
- wifiRssiState1 = halbtc8192d2ant_WifiRssiState(pBtCoexist, 1, 2, 47, 0);
- }
- else
- {
- wifiRssiState1 = halbtc8192d2ant_WifiRssiState(pBtCoexist, 1, 2, 25, 0);
- }
-
- if(pCoexSta->bBtBusy && bWifiBusy)
- {
- if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
- {
- // fw mechanism first
- if(pCoexSta->bBtUplink)
- {
- halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x20, 0x20);
- halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
- }
- else
- {
- halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE);
- }
- // sw mechanism
- if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE);
- }
- else
- {
- halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- }
- halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- if(pCoexSta->bBtUplink)
- {
- halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- else
- {
- halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20);
- }
- }
- else if( (wifiRssiState == BTC_RSSI_STATE_MEDIUM) ||
- (wifiRssiState == BTC_RSSI_STATE_STAY_MEDIUM) )
- {
- // fw mechanism first
- halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x20, 0x20);
-
- if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir)
- {
- halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
- }
- else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir)
- {
- if(BTC_WIFI_BW_HT40 == wifiBw)
- halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);//BT_FW_NAV_ON);
- else
- halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
- }
- // sw mechanism
- if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE);
- }
- else
- {
- halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- }
- halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- else
- {
- // fw mechanism first
- halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x20, 0x20);
-
- if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir)
- {
- halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
- }
- else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir)
- {
- if(pCoexSta->bBtUplink)
- {
- if(BTC_WIFI_BW_HT40 == wifiBw)
- {
- halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);//BT_FW_NAV_ON);
- }
- else
- {
- halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
- }
- }
- else
- {
- halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
- }
- }
- // sw mechanism
- if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE);
- }
- else
- {
- halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- }
- halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- }
- else if(pCoexSta->bBtBusy &&
- !bWifiBusy &&
- (wifiRssi < 30))
- {
- // fw mechanism first
- halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x0a, 0x20);
- halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
- // sw mechanism
- halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- else
- {
- halbtc8192d2ant_CoexAllOff(pBtCoexist);
- }
- }
-}
-
-
-VOID
-halbtc8192d2ant_ActionHid(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH;
- u4Byte wifiTrafficDir;
- BOOLEAN bWifiBusy=FALSE;
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy);
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir);
- if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir)
- {
- wifiRssiState = halbtc8192d2ant_WifiRssiState(pBtCoexist, 0, 2, 45, 0);
- }
- else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir)
- {
- wifiRssiState = halbtc8192d2ant_WifiRssiState(pBtCoexist, 0, 2, 20, 0);
- }
-
- if(pCoexSta->bBtBusy && bWifiBusy)
- {
- if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
- {
- // fw mechanism first
- halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE);
-
- // sw mechanism
- halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20);
- }
- else
- {
- // fw mechanism first
- if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir)
- {
- halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, TRUE, 0x18, FALSE);
- }
- else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir)
- {
- halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x15, 0x15);
- halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x30, FALSE);
- }
- // sw mechanism
- halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- }
- else
- {
- halbtc8192d2ant_CoexAllOff(pBtCoexist);
- }
-}
-
-
-
-VOID
-halbtc8192d2ant_ActionSco(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- u1Byte wifiRssiState;
- u4Byte wifiBw;
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
- wifiRssiState = halbtc8192d2ant_WifiRssiState(pBtCoexist, 0, 2, 47, 0);
-
- if(BTC_WIFI_BW_HT40 == wifiBw)
- {
- // fw mechanism first
- halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE);
-
- // sw mechanism
- halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- else
- {
- // fw mechanism first
- halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE);
-
- // sw mechanism
- if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- else
- {
- halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- }
-}
-
-VOID
-halbtc8192d2ant_ActionHidA2dp(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- u1Byte wifiRssiState, wifiRssiState1;
- u4Byte wifiBw;
-
- if(pCoexSta->bBtBusy)
- {
- wifiRssiState1 = halbtc8192d2ant_WifiRssiState(pBtCoexist, 1, 2, 35, 0);
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
- if(BTC_WIFI_BW_HT40 == wifiBw)
- {
- // fw mechanism first
- halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE);
-
-
- // sw mechanism
- if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE);
- }
- else
- {
- halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- }
- halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18);
- }
- else
- {
- wifiRssiState = halbtc8192d2ant_WifiRssiState(pBtCoexist, 0, 2, 47, 0);
- // fw mechanism
- halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE);
-
- // sw mechanism
- if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE);
- }
- else
- {
- halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- }
- if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18);
- }
- else
- {
- halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18);
- }
- }
- }
- else
- {
- halbtc8192d2ant_CoexAllOff(pBtCoexist);
- }
-}
-
-
-VOID
-halbtc8192d2ant_ActionHidPanBc4(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE;
- u4Byte wifiBw, wifiTrafficDir;
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn);
-
- if(bBtHsOn)
- {
- halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE);
-
- halbtc8192d2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0x000000f0, 0x40000010);
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0xa0);
- }
- else
- {
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy);
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir);
- if(BTC_WIFI_BW_LEGACY == wifiBw)
- {
- halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE);
-
- halbtc8192d2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0x000000f0, 0x40000010);
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0xa0);
- }
- else if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir)
- {
- halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE);
-
- halbtc8192d2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0x000000f0, 0x40000010);
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0xa0);
- }
- else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir)
- {
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0);
- halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x20, 0x10);
- halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
- }
- else if(!bWifiBusy)
- {
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0);
- halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE);
- }
- }
- halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
-}
-VOID
-halbtc8192d2ant_ActionHidPanBc8(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE;
- u1Byte wifiRssiState;
- u4Byte wifiBw, wifiTrafficDir;
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn);
-
- if(!bBtHsOn)
- {
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy);
- wifiRssiState = halbtc8192d2ant_WifiRssiState(pBtCoexist, 0, 2, 25, 0);
- if((pCoexSta->bBtBusy && bWifiBusy))
- {
- // fw mechanism first
- if(pCoexSta->bBtUplink)
- {
- halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x15, 0x20);
- }
- else
- {
- halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x10, 0x20);
- }
- halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
-
- // sw mechanism
- if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
- {
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
- if(BTC_WIFI_BW_HT40 == wifiBw)
- {
- halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- else
- {
- halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- }
- else
- {
- halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- }
- else
- {
- halbtc8192d2ant_CoexAllOff(pBtCoexist);
- }
- }
- else
- {
- if(BTC_INTF_USB == pBtCoexist->chipInterface)
- {
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir);
- if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir)
- {
- halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE);
-
- halbtc8192d2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0x000000f0, 0x40000010);
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0xa0);
- halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18);
- }
- else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir)
- {
- halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18);
- }
- }
- else
- {
- if(pCoexSta->bBtBusy)
- {
- // fw mechanism
- halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE);
-
- // sw mechanism
- halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20);
- }
- else
- {
- halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- }
- }
-}
-
-VOID
-halbtc8192d2ant_ActionHidPan(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- if(BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType)
- {
- halbtc8192d2ant_ActionHidPanBc4(pBtCoexist);
- }
- else if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType)
- {
- halbtc8192d2ant_ActionHidPanBc8(pBtCoexist);
- }
-}
-
-VOID
-halbtc8192d2ant_ActionPanA2dpBc4(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE;
- u1Byte wifiRssiState;
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn);
-
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0);
- if(bBtHsOn)
- {
- if(pCoexSta->bBtBusy)
- {
- // fw mechanism
- halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE);
-
- // sw mechanism
- halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20);
- }
- else
- {
- halbtc8192d2ant_CoexAllOff(pBtCoexist);
- }
- }
- else
- {
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy);
- if(pCoexSta->bBtBusy && bWifiBusy)
- {
- halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x20, 0x10);
- halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
- }
- else
- {
- halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE);
- }
- // sw mechanism
- halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
-}
-VOID
-halbtc8192d2ant_ActionPanA2dpBc8(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE;
- u1Byte wifiRssiState;
- u4Byte wifiBw;
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn);
-
- if(!bBtHsOn)
- {
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy);
- wifiRssiState = halbtc8192d2ant_WifiRssiState(pBtCoexist, 0, 2, 25, 0);
- if((pCoexSta->bBtBusy && bWifiBusy))
- {
- // fw mechanism first
- if(pCoexSta->bBtUplink)
- {
- halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x15, 0x20);
- }
- else
- {
- halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x10, 0x20);
- }
- halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);
-
- // sw mechanism
- if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
- {
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
- if(BTC_WIFI_BW_HT40 == wifiBw)
- {
- halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- else
- {
- halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- }
- else
- {
- halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- }
- else
- {
- halbtc8192d2ant_CoexAllOff(pBtCoexist);
- }
- }
- else
- {
- if(pCoexSta->bBtBusy)
- {
- // fw mechanism
- halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0);
- halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE);
-
- // sw mechanism
- halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20);
- }
- else
- {
- halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30);
- }
- }
-}
-
-VOID
-halbtc8192d2ant_ActionPanA2dp(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- if(BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType)
- {
- halbtc8192d2ant_ActionPanA2dpBc4(pBtCoexist);
- }
- else if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType)
- {
- halbtc8192d2ant_ActionPanA2dpBc8(pBtCoexist);
- }
-}
-
-BOOLEAN
-halbtc8192d2ant_IsBtCoexistEnter(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- u1Byte macPhyMode;
- BOOLEAN bRet=TRUE;
- BOOLEAN bWifiUnder5G=FALSE;
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_MAC_PHY_MODE, &macPhyMode);
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_UNDER_5G, &bWifiUnder5G);
-
- if(BTC_SMSP != macPhyMode)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Only support single mac single phy!!\n"));
- bRet = FALSE;
- }
-
- if(bWifiUnder5G)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi is under 5G or A band\n"));
- halbtc8192d2ant_CoexAllOff(pBtCoexist);
- bRet = FALSE;
- }
-
- return bRet;
-}
-
-//============================================================
-// extern function start with EXhalbtc8192d2ant_
-//============================================================
-VOID
-EXhalbtc8192d2ant_PowerOnSetting(
- IN PBTC_COEXIST pBtCoexist
- )
-{
-}
-
-VOID
-EXhalbtc8192d2ant_InitHwConfig(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bWifiOnly
- )
-{
- u1Byte u1Tmp=0;
-
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 2Ant Init HW Config!!\n"));
-
- // backup rf 0x1e value
- pCoexDm->btRf0x1eBackup =
- pBtCoexist->fBtcGetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff);
-
- if( (BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType) ||
- (BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType) )
- {
- u1Tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x4fd) & BIT0;
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x4fd, u1Tmp);
-
- halbtc8192d2ant_CoexTable(pBtCoexist, FORCE_EXEC, 0xaaaa9aaa, 0xffbd0040, 0x40000010);
-
- // switch control, here we set pathA to control
- // 0x878[13] = 1, 0:pathB, 1:pathA(default)
- pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x878, BIT13, 0x1);
-
- // antsel control, here we use phy0 and enable antsel.
- // 0x87c[16:15] = b'11, enable antsel, antsel output pin
- // 0x87c[30] = 0, 0: phy0, 1:phy 1
- pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x87c, bMaskDWord, 0x1fff8);
-
- // antsel to Bt or Wifi, it depends Bt on/off.
- // 0x860[9:8] = 'b10, b10:Bt On, WL2G off(default), b01:Bt off, WL2G on.
- pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x860, BIT9|BIT8, 0x2);
-
- // sw/hw control switch, here we set sw control
- // 0x870[9:8] = 'b11 sw control, 'b00 hw control
- pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x870, BIT9|BIT8, 0x3);
- }
-}
-
-VOID
-EXhalbtc8192d2ant_InitCoexDm(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Coex Mechanism Init!!\n"));
-
- halbtc8192d2ant_InitCoexDm(pBtCoexist);
-}
-
-VOID
-EXhalbtc8192d2ant_DisplayCoexInfo(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo;
- PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo;
- pu1Byte cliBuf=pBtCoexist->cliBuf;
- u1Byte u1Tmp[4], i, btInfoExt, psTdmaCase=0;
- u4Byte u4Tmp[4];
-
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[BT Coexist info]============");
- CL_PRINTF(cliBuf);
-
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", "Ant PG number/ Ant mechanism:", \
- pBoardInfo->pgAntNum, pBoardInfo->btdmAntNum);
- CL_PRINTF(cliBuf);
-
- if(pBtCoexist->bManualControl)
- {
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "[Action Manual control]!!");
- CL_PRINTF(cliBuf);
- }
-
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d", "BT stack/ hci ext ver", \
- ((pStackInfo->bProfileNotified)? "Yes":"No"), pStackInfo->hciVersion);
- CL_PRINTF(cliBuf);
-
- // wifi status
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Wifi Status]============");
- CL_PRINTF(cliBuf);
- pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_WIFI_STATUS);
-
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[BT Status]============");
- CL_PRINTF(cliBuf);
-
- if(pStackInfo->bProfileNotified)
- {
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", "SCO/HID/PAN/A2DP", \
- pStackInfo->bScoExist, pStackInfo->bHidExist, pStackInfo->bPanExist, pStackInfo->bA2dpExist);
- CL_PRINTF(cliBuf);
-
- pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_BT_LINK_INFO);
- }
-
- // Sw mechanism
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Sw mechanism]============");
- CL_PRINTF(cliBuf);
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ", "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]", \
- pCoexDm->bCurAgcTableEn, pCoexDm->bCurAdcBackOff, pCoexDm->bCurDacSwingOn, pCoexDm->curDacSwingLvl);
- CL_PRINTF(cliBuf);
-
- // Fw mechanism
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Fw mechanism]============");
- CL_PRINTF(cliBuf);
-
- // Hw setting
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Hw setting]============");
- CL_PRINTF(cliBuf);
-
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "RF-A, 0x1e initVal", \
- pCoexDm->btRf0x1eBackup);
- CL_PRINTF(cliBuf);
-
- u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x40);
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x40", \
- u1Tmp[0]);
- CL_PRINTF(cliBuf);
-
- u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xc50);
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)", \
- u4Tmp[0]);
- CL_PRINTF(cliBuf);
-
- u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c4);
- u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c8);
- u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6cc);
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "0x6c4/0x6c8/0x6cc(coexTable)", \
- u4Tmp[0], u4Tmp[1], u4Tmp[2]);
- CL_PRINTF(cliBuf);
-
- pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_COEX_STATISTICS);
-}
-
-
-VOID
-EXhalbtc8192d2ant_IpsNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- )
-{
- if(BTC_IPS_ENTER == type)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS ENTER notify\n"));
- halbtc8192d2ant_CoexAllOff(pBtCoexist);
- }
- else if(BTC_IPS_LEAVE == type)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS LEAVE notify\n"));
- //halbtc8192d2ant_InitCoexDm(pBtCoexist);
- }
-}
-
-VOID
-EXhalbtc8192d2ant_LpsNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- )
-{
- if(BTC_LPS_ENABLE == type)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS ENABLE notify\n"));
- halbtc8192d2ant_CoexAllOff(pBtCoexist);
- }
- else if(BTC_LPS_DISABLE == type)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS DISABLE notify\n"));
- halbtc8192d2ant_InitCoexDm(pBtCoexist);
- }
-}
-
-VOID
-EXhalbtc8192d2ant_ScanNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- )
-{
- if(BTC_SCAN_START == type)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN START notify\n"));
- }
- else if(BTC_SCAN_FINISH == type)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN FINISH notify\n"));
- }
-}
-
-VOID
-EXhalbtc8192d2ant_ConnectNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- )
-{
- if(BTC_ASSOCIATE_START == type)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT START notify\n"));
- }
- else if(BTC_ASSOCIATE_FINISH == type)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT FINISH notify\n"));
- }
-}
-
-VOID
-EXhalbtc8192d2ant_MediaStatusNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- )
-{
- if(BTC_MEDIA_CONNECT == type)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA connect notify\n"));
- }
- else
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA disconnect notify\n"));
- }
-}
-
-VOID
-EXhalbtc8192d2ant_SpecialPacketNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- )
-{
- if(type == BTC_PACKET_DHCP)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], DHCP Packet notify\n"));
- }
-}
-
-VOID
-EXhalbtc8192d2ant_BtInfoNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN pu1Byte tmpBuf,
- IN u1Byte length
- )
-{
-}
-
-VOID
-EXhalbtc8192d2ant_HaltNotify(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Halt notify\n"));
-
- EXhalbtc8192d2ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT);
-}
-
-VOID
-EXhalbtc8192d2ant_Periodical(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- u1Byte algorithm;
-
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 2Ant Periodical!!\n"));
-
- // NOTE:
- // sw mechanism must be done after fw mechanism
- //
- if(!halbtc8192d2ant_IsBtCoexistEnter(pBtCoexist))
- return;
-
- if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType)
- {
- pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_GET_BT_RSSI, NULL);
-
- halbtc8192d2ant_MonitorBtState(pBtCoexist);
- algorithm = halbtc8192d2ant_ActionAlgorithm(pBtCoexist);
- pCoexDm->curAlgorithm = algorithm;
- switch(pCoexDm->curAlgorithm)
- {
- case BT_8192D_2ANT_COEX_ALGO_SCO:
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = SCO\n"));
- halbtc8192d2ant_ActionSco(pBtCoexist);
- break;
- case BT_8192D_2ANT_COEX_ALGO_HID:
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID\n"));
- halbtc8192d2ant_ActionHid(pBtCoexist);
- break;
- case BT_8192D_2ANT_COEX_ALGO_A2DP:
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = A2DP\n"));
- halbtc8192d2ant_ActionA2dp(pBtCoexist);
- break;
- case BT_8192D_2ANT_COEX_ALGO_PAN:
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN\n"));
- halbtc8192d2ant_ActionPan(pBtCoexist);
- break;
- case BT_8192D_2ANT_COEX_ALGO_HID_A2DP:
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID+A2DP\n"));
- halbtc8192d2ant_ActionHidA2dp(pBtCoexist);
- break;
- case BT_8192D_2ANT_COEX_ALGO_HID_PAN:
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN+HID\n"));
- halbtc8192d2ant_ActionHidPan(pBtCoexist);
- break;
- case BT_8192D_2ANT_COEX_ALGO_PAN_A2DP:
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN+A2DP\n"));
- halbtc8192d2ant_ActionPanA2dp(pBtCoexist);
- break;
- default:
- break;
- }
- }
-}
-
-#endif
-
diff --git a/hal/btc/HalBtc8192d2Ant.h b/hal/btc/HalBtc8192d2Ant.h
deleted file mode 100644
index f3862b3..0000000
--- a/hal/btc/HalBtc8192d2Ant.h
+++ /dev/null
@@ -1,170 +0,0 @@
-//===========================================
-// The following is for 8192D 2Ant BT Co-exist definition
-//===========================================
-#define BTC_RSSI_COEX_THRESH_TOL_8192D_2ANT 6
-
-typedef enum _BT_INFO_SRC_8192D_2ANT{
- BT_INFO_SRC_8192D_2ANT_WIFI_FW = 0x0,
- BT_INFO_SRC_8192D_2ANT_BT_RSP = 0x1,
- BT_INFO_SRC_8192D_2ANT_BT_ACTIVE_SEND = 0x2,
- BT_INFO_SRC_8192D_2ANT_MAX
-}BT_INFO_SRC_8192D_2ANT,*PBT_INFO_SRC_8192D_2ANT;
-
-typedef enum _BT_8192D_2ANT_BT_STATUS{
- BT_8192D_2ANT_BT_STATUS_IDLE = 0x0,
- BT_8192D_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
- BT_8192D_2ANT_BT_STATUS_NON_IDLE = 0x2,
- BT_8192D_2ANT_BT_STATUS_MAX
-}BT_8192D_2ANT_BT_STATUS,*PBT_8192D_2ANT_BT_STATUS;
-
-typedef enum _BT_8192D_2ANT_COEX_ALGO{
- BT_8192D_2ANT_COEX_ALGO_UNDEFINED = 0x0,
- BT_8192D_2ANT_COEX_ALGO_SCO = 0x1,
- BT_8192D_2ANT_COEX_ALGO_HID = 0x2,
- BT_8192D_2ANT_COEX_ALGO_A2DP = 0x3,
- BT_8192D_2ANT_COEX_ALGO_PAN = 0x4,
- BT_8192D_2ANT_COEX_ALGO_HID_A2DP = 0x5,
- BT_8192D_2ANT_COEX_ALGO_HID_PAN = 0x6,
- BT_8192D_2ANT_COEX_ALGO_PAN_A2DP = 0x7,
- BT_8192D_2ANT_COEX_ALGO_MAX
-}BT_8192D_2ANT_COEX_ALGO,*PBT_8192D_2ANT_COEX_ALGO;
-
-typedef struct _COEX_DM_8192D_2ANT{
- // fw mechanism
- BOOLEAN bPreBalanceOn;
- BOOLEAN bCurBalanceOn;
-
- // diminishWifi
- BOOLEAN bPreDacOn;
- BOOLEAN bCurDacOn;
- BOOLEAN bPreInterruptOn;
- BOOLEAN bCurInterruptOn;
- u1Byte preFwDacSwingLvl;
- u1Byte curFwDacSwingLvl;
- BOOLEAN bPreNavOn;
- BOOLEAN bCurNavOn;
-
-
-
-
-
- //BOOLEAN bPreDecBtPwr;
- //BOOLEAN bCurDecBtPwr;
-
- //u1Byte preFwDacSwingLvl;
- //u1Byte curFwDacSwingLvl;
- //BOOLEAN bCurIgnoreWlanAct;
- //BOOLEAN bPreIgnoreWlanAct;
- //u1Byte prePsTdma;
- //u1Byte curPsTdma;
- //u1Byte psTdmaPara[5];
- //u1Byte psTdmaDuAdjType;
- //BOOLEAN bResetTdmaAdjust;
- //BOOLEAN bPrePsTdmaOn;
- //BOOLEAN bCurPsTdmaOn;
- //BOOLEAN bPreBtAutoReport;
- //BOOLEAN bCurBtAutoReport;
-
- // sw mechanism
- BOOLEAN bPreRfRxLpfShrink;
- BOOLEAN bCurRfRxLpfShrink;
- u4Byte btRf0x1eBackup;
- BOOLEAN bPreLowPenaltyRa;
- BOOLEAN bCurLowPenaltyRa;
- BOOLEAN bPreDacSwingOn;
- u4Byte preDacSwingLvl;
- BOOLEAN bCurDacSwingOn;
- u4Byte curDacSwingLvl;
- BOOLEAN bPreAdcBackOff;
- BOOLEAN bCurAdcBackOff;
- BOOLEAN bPreAgcTableEn;
- BOOLEAN bCurAgcTableEn;
- //u4Byte preVal0x6c0;
- //u4Byte curVal0x6c0;
- u4Byte preVal0x6c4;
- u4Byte curVal0x6c4;
- u4Byte preVal0x6c8;
- u4Byte curVal0x6c8;
- u4Byte preVal0x6cc;
- u4Byte curVal0x6cc;
- //BOOLEAN bLimitedDig;
-
- // algorithm related
- u1Byte preAlgorithm;
- u1Byte curAlgorithm;
- //u1Byte btStatus;
- //u1Byte wifiChnlInfo[3];
-} COEX_DM_8192D_2ANT, *PCOEX_DM_8192D_2ANT;
-
-typedef struct _COEX_STA_8192D_2ANT{
- u1Byte preWifiRssiState[4];
- BOOLEAN bBtBusy;
- BOOLEAN bBtUplink;
- BOOLEAN bBtDownLink;
- BOOLEAN bA2dpBusy;
-}COEX_STA_8192D_2ANT, *PCOEX_STA_8192D_2ANT;
-
-//===========================================
-// The following is interface which will notify coex module.
-//===========================================
-VOID
-EXhalbtc8192d2ant_PowerOnSetting(
- IN PBTC_COEXIST pBtCoexist
- );
-VOID
-EXhalbtc8192d2ant_InitHwConfig(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bWifiOnly
- );
-VOID
-EXhalbtc8192d2ant_InitCoexDm(
- IN PBTC_COEXIST pBtCoexist
- );
-VOID
-EXhalbtc8192d2ant_IpsNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- );
-VOID
-EXhalbtc8192d2ant_LpsNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- );
-VOID
-EXhalbtc8192d2ant_ScanNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- );
-VOID
-EXhalbtc8192d2ant_ConnectNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- );
-VOID
-EXhalbtc8192d2ant_MediaStatusNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- );
-VOID
-EXhalbtc8192d2ant_SpecialPacketNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- );
-VOID
-EXhalbtc8192d2ant_HaltNotify(
- IN PBTC_COEXIST pBtCoexist
- );
-VOID
-EXhalbtc8192d2ant_Periodical(
- IN PBTC_COEXIST pBtCoexist
- );
-VOID
-EXhalbtc8192d2ant_BtInfoNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN pu1Byte tmpBuf,
- IN u1Byte length
- );
-VOID
-EXhalbtc8192d2ant_DisplayCoexInfo(
- IN PBTC_COEXIST pBtCoexist
- );
diff --git a/hal/btc/HalBtc8192e1Ant.c b/hal/btc/HalBtc8192e1Ant.c
deleted file mode 100644
index 8a4d977..0000000
--- a/hal/btc/HalBtc8192e1Ant.c
+++ /dev/null
@@ -1,3417 +0,0 @@
-/* ************************************************************
- * Description:
- *
- * This file is for RTL8192E Co-exist mechanism
- *
- * History
- * 2012/11/15 Cosa first check in.
- *
- * ************************************************************ */
-
-/* ************************************************************
- * include files
- * ************************************************************ */
-#include "Mp_Precomp.h"
-
-#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
-
-#if (RTL8192E_SUPPORT == 1)
-/* ************************************************************
- * Global variables, these are static variables
- * ************************************************************ */
-static u8 *trace_buf = &gl_btc_trace_buf[0];
-static struct coex_dm_8192e_1ant glcoex_dm_8192e_1ant;
-static struct coex_dm_8192e_1ant *coex_dm = &glcoex_dm_8192e_1ant;
-static struct coex_sta_8192e_1ant glcoex_sta_8192e_1ant;
-static struct coex_sta_8192e_1ant *coex_sta = &glcoex_sta_8192e_1ant;
-
-const char *const glbt_info_src_8192e_1ant[] = {
- "BT Info[wifi fw]",
- "BT Info[bt rsp]",
- "BT Info[bt auto report]",
-};
-
-u32 glcoex_ver_date_8192e_1ant = 20140527;
-u32 glcoex_ver_8192e_1ant = 0x4f;
-
-/* ************************************************************
- * local function proto type if needed
- * ************************************************************
- * ************************************************************
- * local function start with halbtc8192e1ant_
- * ************************************************************ */
-u8 halbtc8192e1ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1)
-{
- s32 bt_rssi = 0;
- u8 bt_rssi_state = coex_sta->pre_bt_rssi_state;
-
- bt_rssi = coex_sta->bt_rssi;
-
- if (level_num == 2) {
- if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
- (coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (bt_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT))
- bt_rssi_state = BTC_RSSI_STATE_HIGH;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else {
- if (bt_rssi < rssi_thresh)
- bt_rssi_state = BTC_RSSI_STATE_LOW;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- } else if (level_num == 3) {
- if (rssi_thresh > rssi_thresh1) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Rssi thresh error!!\n");
- BTC_TRACE(trace_buf);
- return coex_sta->pre_bt_rssi_state;
- }
-
- if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
- (coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (bt_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT))
- bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else if ((coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_MEDIUM) ||
- (coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_STAY_MEDIUM)) {
- if (bt_rssi >= (rssi_thresh1 +
- BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT))
- bt_rssi_state = BTC_RSSI_STATE_HIGH;
- else if (bt_rssi < rssi_thresh)
- bt_rssi_state = BTC_RSSI_STATE_LOW;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
- } else {
- if (bt_rssi < rssi_thresh1)
- bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- }
-
- coex_sta->pre_bt_rssi_state = bt_rssi_state;
-
- return bt_rssi_state;
-}
-
-u8 halbtc8192e1ant_wifi_rssi_state(IN struct btc_coexist *btcoexist,
- IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1)
-{
- s32 wifi_rssi = 0;
- u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index];
-
- btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
-
- if (level_num == 2) {
- if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
- ||
- (coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (wifi_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT))
- wifi_rssi_state = BTC_RSSI_STATE_HIGH;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else {
- if (wifi_rssi < rssi_thresh)
- wifi_rssi_state = BTC_RSSI_STATE_LOW;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- } else if (level_num == 3) {
- if (rssi_thresh > rssi_thresh1) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], wifi RSSI thresh error!!\n");
- BTC_TRACE(trace_buf);
- return coex_sta->pre_wifi_rssi_state[index];
- }
-
- if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
- ||
- (coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (wifi_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT))
- wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else if ((coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_MEDIUM) ||
- (coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_STAY_MEDIUM)) {
- if (wifi_rssi >= (rssi_thresh1 +
- BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT))
- wifi_rssi_state = BTC_RSSI_STATE_HIGH;
- else if (wifi_rssi < rssi_thresh)
- wifi_rssi_state = BTC_RSSI_STATE_LOW;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
- } else {
- if (wifi_rssi < rssi_thresh1)
- wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- }
-
- coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state;
-
- return wifi_rssi_state;
-}
-
-void halbtc8192e1ant_update_ra_mask(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u32 dis_rate_mask)
-{
- coex_dm->cur_ra_mask = dis_rate_mask;
-
- if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask))
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK,
- &coex_dm->cur_ra_mask);
- coex_dm->pre_ra_mask = coex_dm->cur_ra_mask;
-}
-
-void halbtc8192e1ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- boolean wifi_under_b_mode = false;
-
- coex_dm->cur_arfr_type = type;
-
- if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) {
- switch (coex_dm->cur_arfr_type) {
- case 0: /* normal mode */
- btcoexist->btc_write_4byte(btcoexist, 0x430,
- coex_dm->backup_arfr_cnt1);
- btcoexist->btc_write_4byte(btcoexist, 0x434,
- coex_dm->backup_arfr_cnt2);
- break;
- case 1:
- btcoexist->btc_get(btcoexist,
- BTC_GET_BL_WIFI_UNDER_B_MODE,
- &wifi_under_b_mode);
- if (wifi_under_b_mode) {
- btcoexist->btc_write_4byte(btcoexist,
- 0x430, 0x0);
- btcoexist->btc_write_4byte(btcoexist,
- 0x434, 0x01010101);
- } else {
- btcoexist->btc_write_4byte(btcoexist,
- 0x430, 0x0);
- btcoexist->btc_write_4byte(btcoexist,
- 0x434, 0x04030201);
- }
- break;
- default:
- break;
- }
- }
-
- coex_dm->pre_arfr_type = coex_dm->cur_arfr_type;
-}
-
-void halbtc8192e1ant_retry_limit(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- coex_dm->cur_retry_limit_type = type;
-
- if (force_exec ||
- (coex_dm->pre_retry_limit_type !=
- coex_dm->cur_retry_limit_type)) {
- switch (coex_dm->cur_retry_limit_type) {
- case 0: /* normal mode */
- btcoexist->btc_write_2byte(btcoexist, 0x42a,
- coex_dm->backup_retry_limit);
- break;
- case 1: /* retry limit=8 */
- btcoexist->btc_write_2byte(btcoexist, 0x42a,
- 0x0808);
- break;
- default:
- break;
- }
- }
-
- coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type;
-}
-
-void halbtc8192e1ant_ampdu_max_time(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- coex_dm->cur_ampdu_time_type = type;
-
- if (force_exec ||
- (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) {
- switch (coex_dm->cur_ampdu_time_type) {
- case 0: /* normal mode */
- btcoexist->btc_write_1byte(btcoexist, 0x456,
- coex_dm->backup_ampdu_max_time);
- break;
- case 1: /* AMPDU timw = 0x38 * 32us */
- btcoexist->btc_write_1byte(btcoexist, 0x456,
- 0x38);
- break;
- default:
- break;
- }
- }
-
- coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type;
-}
-
-void halbtc8192e1ant_limited_tx(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type,
- IN u8 retry_limit_type, IN u8 ampdu_time_type)
-{
- switch (ra_mask_type) {
- case 0: /* normal mode */
- halbtc8192e1ant_update_ra_mask(btcoexist, force_exec,
- 0x0);
- break;
- case 1: /* disable cck 1/2 */
- halbtc8192e1ant_update_ra_mask(btcoexist, force_exec,
- 0x00000003);
- break;
- case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */
- halbtc8192e1ant_update_ra_mask(btcoexist, force_exec,
- 0x0001f1f7);
- break;
- default:
- break;
- }
-
- halbtc8192e1ant_auto_rate_fallback_retry(btcoexist, force_exec,
- arfr_type);
- halbtc8192e1ant_retry_limit(btcoexist, force_exec, retry_limit_type);
- halbtc8192e1ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type);
-}
-
-void halbtc8192e1ant_limited_rx(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean rej_ap_agg_pkt,
- IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size)
-{
- boolean reject_rx_agg = rej_ap_agg_pkt;
- boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size;
- u8 rx_agg_size = agg_buf_size;
-
- /* ============================================ */
- /* Rx Aggregation related setting */
- /* ============================================ */
- btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT,
- &reject_rx_agg);
- /* decide BT control aggregation buf size or not */
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE,
- &bt_ctrl_rx_agg_size);
- /* aggregation buf size, only work when BT control Rx aggregation size. */
- btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size);
- /* real update aggregation setting */
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
-
-
-}
-
-void halbtc8192e1ant_query_bt_info(IN struct btc_coexist *btcoexist)
-{
- u8 h2c_parameter[1] = {0};
-
- coex_sta->c2h_bt_info_req_sent = true;
-
- h2c_parameter[0] |= BIT(0); /* trigger */
-
- btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter);
-}
-
-void halbtc8192e1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist)
-{
- u32 reg_hp_txrx, reg_lp_txrx, u32tmp;
- u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
- static u8 num_of_bt_counter_chk = 0;
-
- /* to avoid 0x76e[3] = 1 (WLAN_Act control by PTA) during IPS */
- /* if (! (btcoexist->btc_read_1byte(btcoexist, 0x76e) & 0x8) ) */
-
- if (coex_sta->under_ips) {
- coex_sta->high_priority_tx = 65535;
- coex_sta->high_priority_rx = 65535;
- coex_sta->low_priority_tx = 65535;
- coex_sta->low_priority_rx = 65535;
- return;
- }
-
- reg_hp_txrx = 0x770;
- reg_lp_txrx = 0x774;
-
- u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
- reg_hp_tx = u32tmp & MASKLWORD;
- reg_hp_rx = (u32tmp & MASKHWORD) >> 16;
-
- u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
- reg_lp_tx = u32tmp & MASKLWORD;
- reg_lp_rx = (u32tmp & MASKHWORD) >> 16;
-
- coex_sta->high_priority_tx = reg_hp_tx;
- coex_sta->high_priority_rx = reg_hp_rx;
- coex_sta->low_priority_tx = reg_lp_tx;
- coex_sta->low_priority_rx = reg_lp_rx;
-
- if ((coex_sta->low_priority_tx >= 1050) &&
- (!coex_sta->c2h_bt_inquiry_page))
- coex_sta->pop_event_cnt++;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n",
- reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx);
- BTC_TRACE(trace_buf);
-
- /* reset counter */
- btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
-
- if ((reg_hp_tx == 0) && (reg_hp_rx == 0) && (reg_lp_tx == 0) &&
- (reg_lp_rx == 0)) {
- num_of_bt_counter_chk++;
- if (num_of_bt_counter_chk >= 3) {
- halbtc8192e1ant_query_bt_info(btcoexist);
- num_of_bt_counter_chk = 0;
- }
- }
-}
-
-
-void halbtc8192e1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist)
-{
- s32 wifi_rssi = 0;
- boolean wifi_busy = false, wifi_under_b_mode = false;
- static u8 cck_lock_counter = 0;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
- &wifi_under_b_mode);
-
- if (coex_sta->under_ips) {
- coex_sta->crc_ok_cck = 0;
- coex_sta->crc_ok_11g = 0;
- coex_sta->crc_ok_11n = 0;
- coex_sta->crc_ok_11n_agg = 0;
-
- coex_sta->crc_err_cck = 0;
- coex_sta->crc_err_11g = 0;
- coex_sta->crc_err_11n = 0;
- coex_sta->crc_err_11n_agg = 0;
- } else {
- coex_sta->crc_ok_cck = btcoexist->btc_read_4byte(btcoexist,
- 0xf88);
- coex_sta->crc_ok_11g = btcoexist->btc_read_2byte(btcoexist,
- 0xf94);
- coex_sta->crc_ok_11n = btcoexist->btc_read_2byte(btcoexist,
- 0xf90);
- coex_sta->crc_ok_11n_agg = btcoexist->btc_read_2byte(btcoexist,
- 0xfb8);
-
- coex_sta->crc_err_cck = btcoexist->btc_read_4byte(btcoexist,
- 0xf84);
- coex_sta->crc_err_11g = btcoexist->btc_read_2byte(btcoexist,
- 0xf96);
- coex_sta->crc_err_11n = btcoexist->btc_read_2byte(btcoexist,
- 0xf92);
- coex_sta->crc_err_11n_agg = btcoexist->btc_read_2byte(btcoexist,
- 0xfba);
- }
-
-
- /* reset counter */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xf16, 0x1, 0x1);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xf16, 0x1, 0x0);
-
- if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) {
- if ((coex_dm->bt_status == BT_8192E_1ANT_BT_STATUS_ACL_BUSY) ||
- (coex_dm->bt_status ==
- BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY) ||
- (coex_dm->bt_status ==
- BT_8192E_1ANT_BT_STATUS_SCO_BUSY)) {
- if (coex_sta->crc_ok_cck > (coex_sta->crc_ok_11g +
- coex_sta->crc_ok_11n +
- coex_sta->crc_ok_11n_agg)) {
- if (cck_lock_counter < 5)
- cck_lock_counter++;
- } else {
- if (cck_lock_counter > 0)
- cck_lock_counter--;
- }
-
- } else {
- if (cck_lock_counter > 0)
- cck_lock_counter--;
- }
- } else {
- if (cck_lock_counter > 0)
- cck_lock_counter--;
- }
-
- if (!coex_sta->pre_ccklock) {
-
- if (cck_lock_counter >= 5)
- coex_sta->cck_lock = true;
- else
- coex_sta->cck_lock = false;
- } else {
- if (cck_lock_counter == 0)
- coex_sta->cck_lock = false;
- else
- coex_sta->cck_lock = true;
- }
-
- coex_sta->pre_ccklock = coex_sta->cck_lock;
-
-
-}
-
-boolean halbtc8192e1ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist)
-{
- static boolean pre_wifi_busy = false, pre_under_4way = false,
- pre_bt_hs_on = false;
- boolean wifi_busy = false, under_4way = false, bt_hs_on = false;
- boolean wifi_connected = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
- &under_4way);
-
- if (wifi_connected) {
- if (wifi_busy != pre_wifi_busy) {
- pre_wifi_busy = wifi_busy;
- return true;
- }
- if (under_4way != pre_under_4way) {
- pre_under_4way = under_4way;
- return true;
- }
- if (bt_hs_on != pre_bt_hs_on) {
- pre_bt_hs_on = bt_hs_on;
- return true;
- }
- }
-
- return false;
-}
-
-void halbtc8192e1ant_update_bt_link_info(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean bt_hs_on = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
-
- bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
- bt_link_info->sco_exist = coex_sta->sco_exist;
- bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
- bt_link_info->pan_exist = coex_sta->pan_exist;
- bt_link_info->hid_exist = coex_sta->hid_exist;
-
- /* work around for HS mode. */
- if (bt_hs_on) {
- bt_link_info->pan_exist = true;
- bt_link_info->bt_link_exist = true;
- }
-
- /* check if Sco only */
- if (bt_link_info->sco_exist &&
- !bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist &&
- !bt_link_info->hid_exist)
- bt_link_info->sco_only = true;
- else
- bt_link_info->sco_only = false;
-
- /* check if A2dp only */
- if (!bt_link_info->sco_exist &&
- bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist &&
- !bt_link_info->hid_exist)
- bt_link_info->a2dp_only = true;
- else
- bt_link_info->a2dp_only = false;
-
- /* check if Pan only */
- if (!bt_link_info->sco_exist &&
- !bt_link_info->a2dp_exist &&
- bt_link_info->pan_exist &&
- !bt_link_info->hid_exist)
- bt_link_info->pan_only = true;
- else
- bt_link_info->pan_only = false;
-
- /* check if Hid only */
- if (!bt_link_info->sco_exist &&
- !bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist &&
- bt_link_info->hid_exist)
- bt_link_info->hid_only = true;
- else
- bt_link_info->hid_only = false;
-}
-
-u8 halbtc8192e1ant_action_algorithm(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean bt_hs_on = false;
- u8 algorithm = BT_8192E_1ANT_COEX_ALGO_UNDEFINED;
- u8 num_of_diff_profile = 0;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
-
- if (!bt_link_info->bt_link_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], No BT link exists!!!\n");
- BTC_TRACE(trace_buf);
- return algorithm;
- }
-
- if (bt_link_info->sco_exist)
- num_of_diff_profile++;
- if (bt_link_info->hid_exist)
- num_of_diff_profile++;
- if (bt_link_info->pan_exist)
- num_of_diff_profile++;
- if (bt_link_info->a2dp_exist)
- num_of_diff_profile++;
-
- if (num_of_diff_profile == 1) {
- if (bt_link_info->sco_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO only\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8192E_1ANT_COEX_ALGO_SCO;
- } else {
- if (bt_link_info->hid_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = HID only\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8192E_1ANT_COEX_ALGO_HID;
- } else if (bt_link_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = A2DP only\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8192E_1ANT_COEX_ALGO_A2DP;
- } else if (bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = PAN(HS) only\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8192E_1ANT_COEX_ALGO_PANHS;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = PAN(EDR) only\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8192E_1ANT_COEX_ALGO_PANEDR;
- }
- }
- }
- } else if (num_of_diff_profile == 2) {
- if (bt_link_info->sco_exist) {
- if (bt_link_info->hid_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + HID\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8192E_1ANT_COEX_ALGO_HID;
- } else if (bt_link_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + A2DP ==> SCO\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8192E_1ANT_COEX_ALGO_SCO;
- } else if (bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8192E_1ANT_COEX_ALGO_SCO;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8192E_1ANT_COEX_ALGO_PANEDR_HID;
- }
- }
- } else {
- if (bt_link_info->hid_exist &&
- bt_link_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = HID + A2DP\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8192E_1ANT_COEX_ALGO_HID_A2DP;
- } else if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = HID + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8192E_1ANT_COEX_ALGO_HID_A2DP;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = HID + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8192E_1ANT_COEX_ALGO_PANEDR_HID;
- }
- } else if (bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8192E_1ANT_COEX_ALGO_A2DP_PANHS;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = A2DP + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8192E_1ANT_COEX_ALGO_PANEDR_A2DP;
- }
- }
- }
- } else if (num_of_diff_profile == 3) {
- if (bt_link_info->sco_exist) {
- if (bt_link_info->hid_exist &&
- bt_link_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8192E_1ANT_COEX_ALGO_HID;
- } else if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + HID + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8192E_1ANT_COEX_ALGO_HID_A2DP;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8192E_1ANT_COEX_ALGO_PANEDR_HID;
- }
- } else if (bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8192E_1ANT_COEX_ALGO_SCO;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8192E_1ANT_COEX_ALGO_PANEDR_HID;
- }
- }
- } else {
- if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8192E_1ANT_COEX_ALGO_HID_A2DP;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8192E_1ANT_COEX_ALGO_HID_A2DP_PANEDR;
- }
- }
- }
- } else if (num_of_diff_profile >= 3) {
- if (bt_link_info->sco_exist) {
- if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
-
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8192E_1ANT_COEX_ALGO_PANEDR_HID;
- }
- }
- }
- }
-
- return algorithm;
-}
-
-void halbtc8192e1ant_set_bt_auto_report(IN struct btc_coexist *btcoexist,
- IN boolean enable_auto_report)
-{
- u8 h2c_parameter[1] = {0};
-
- h2c_parameter[0] = 0;
-
- if (enable_auto_report)
- h2c_parameter[0] |= BIT(0);
-
- btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter);
-}
-
-void halbtc8192e1ant_bt_auto_report(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean enable_auto_report)
-{
- coex_dm->cur_bt_auto_report = enable_auto_report;
-
- if (!force_exec) {
- if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report)
- return;
- }
- halbtc8192e1ant_set_bt_auto_report(btcoexist,
- coex_dm->cur_bt_auto_report);
-
- coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report;
-}
-
-void halbtc8192e1ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist
- *btcoexist, IN boolean low_penalty_ra)
-{
- u8 h2c_parameter[6] = {0};
-
- h2c_parameter[0] = 0x6; /* op_code, 0x6= Retry_Penalty */
-
- if (low_penalty_ra) {
- h2c_parameter[1] |= BIT(0);
- h2c_parameter[2] =
- 0x00; /* normal rate except MCS7/6/5, OFDM54/48/36 */
- h2c_parameter[3] = 0xf7; /* MCS7 or OFDM54 */
- h2c_parameter[4] = 0xf8; /* MCS6 or OFDM48 */
- h2c_parameter[5] = 0xf9; /* MCS5 or OFDM36 */
- }
-
- btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter);
-}
-
-void halbtc8192e1ant_low_penalty_ra(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean low_penalty_ra)
-{
- coex_dm->cur_low_penalty_ra = low_penalty_ra;
-
- if (!force_exec) {
- if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra)
- return;
- }
- halbtc8192e1ant_set_sw_penalty_tx_rate_adaptive(btcoexist,
- coex_dm->cur_low_penalty_ra);
-
- coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra;
-}
-
-void halbtc8192e1ant_set_coex_table(IN struct btc_coexist *btcoexist,
- IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc)
-{
- btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
-
- btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
-
- btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
-
- btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
-}
-
-void halbtc8192e1ant_coex_table(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4,
- IN u32 val0x6c8, IN u8 val0x6cc)
-{
- coex_dm->cur_val0x6c0 = val0x6c0;
- coex_dm->cur_val0x6c4 = val0x6c4;
- coex_dm->cur_val0x6c8 = val0x6c8;
- coex_dm->cur_val0x6cc = val0x6cc;
-
- if (!force_exec) {
- if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) &&
- (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) &&
- (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) &&
- (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc))
- return;
- }
- halbtc8192e1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8,
- val0x6cc);
-
- coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0;
- coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4;
- coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8;
- coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc;
-}
-
-void halbtc8192e1ant_coex_table_with_type(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** CoexTable(%d) **********\n", type);
- BTC_TRACE(trace_buf);
-
- coex_sta->coex_table_type = type;
-
- switch (type) {
- case 0:
- halbtc8192e1ant_coex_table(btcoexist, force_exec,
- 0x55555555, 0x55555555, 0xffffff, 0x3);
- break;
- case 1:
- halbtc8192e1ant_coex_table(btcoexist, force_exec,
- 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3);
- break;
- case 2:
- halbtc8192e1ant_coex_table(btcoexist, force_exec,
- 0x5a5a5a5a, 0x5a5a5a5a, 0xffffff, 0x3);
- break;
- case 3:
- halbtc8192e1ant_coex_table(btcoexist, force_exec,
- 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3);
- break;
- case 4:
- halbtc8192e1ant_coex_table(btcoexist, force_exec,
- 0x55555555, 0xaaaa5a5a, 0xffffff, 0x3);
- break;
- case 5:
- halbtc8192e1ant_coex_table(btcoexist, force_exec,
- 0x5a5a5a5a, 0xaa5a5a5a, 0xffffff, 0x3);
- break;
- case 6:
- halbtc8192e1ant_coex_table(btcoexist, force_exec,
- 0x55555555, 0xaaaaaaaa, 0xffffff, 0x3);
- break;
- case 7:
- halbtc8192e1ant_coex_table(btcoexist, force_exec,
- 0xaaaaaaaa, 0xaaaaaaaa, 0xffffff, 0x3);
- break;
- default:
- break;
- }
-}
-
-void halbtc8192e1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist,
- IN boolean enable)
-{
- u8 h2c_parameter[1] = {0};
-
- if (enable) {
- h2c_parameter[0] |= BIT(0); /* function enable */
- }
-
- btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter);
-}
-
-void halbtc8192e1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean enable)
-{
- coex_dm->cur_ignore_wlan_act = enable;
-
- if (!force_exec) {
- if (coex_dm->pre_ignore_wlan_act ==
- coex_dm->cur_ignore_wlan_act)
- return;
- }
- halbtc8192e1ant_set_fw_ignore_wlan_act(btcoexist, enable);
-
- coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
-}
-
-void halbtc8192e1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist,
- IN u8 lps_val, IN u8 rpwm_val)
-{
- u8 lps = lps_val;
- u8 rpwm = rpwm_val;
-
- btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps);
- btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm);
-}
-
-void halbtc8192e1ant_lps_rpwm(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val)
-{
- coex_dm->cur_lps = lps_val;
- coex_dm->cur_rpwm = rpwm_val;
-
- if (!force_exec) {
- if ((coex_dm->pre_lps == coex_dm->cur_lps) &&
- (coex_dm->pre_rpwm == coex_dm->cur_rpwm))
- return;
- }
- halbtc8192e1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val);
-
- coex_dm->pre_lps = coex_dm->cur_lps;
- coex_dm->pre_rpwm = coex_dm->cur_rpwm;
-}
-
-void halbtc8192e1ant_sw_mechanism(IN struct btc_coexist *btcoexist,
- IN boolean low_penalty_ra)
-{
- halbtc8192e1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra);
-}
-
-void halbtc8192e1ant_set_ant_path(IN struct btc_coexist *btcoexist,
- IN u8 ant_pos_type, IN boolean init_hwcfg, IN boolean wifi_off)
-{
- u32 u32tmp = 0;
-
- if (init_hwcfg) {
- btcoexist->btc_write_1byte(btcoexist, 0x944, 0x24);
- btcoexist->btc_write_4byte(btcoexist, 0x930, 0x700700);
- if (btcoexist->chip_interface == BTC_INTF_USB)
- btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30430004);
- else
- btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30030004);
-
- /* 0x4c[27][24]='00', Set Antenna to BB */
- u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c);
- u32tmp &= ~BIT(24);
- u32tmp &= ~BIT(27);
- btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp);
- } else if (wifi_off) {
- if (btcoexist->chip_interface == BTC_INTF_USB)
- btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30430004);
- else
- btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30030004);
-
- /* 0x4c[27][24]='11', Set Antenna to BT, 0x64[8:7]=0, 0x64[2]=1 */
- u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c);
- u32tmp |= BIT(24);
- u32tmp |= BIT(27);
- btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp);
- }
-
- /* ext switch setting */
- switch (ant_pos_type) {
- case BTC_ANT_PATH_WIFI:
- btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x4);
- break;
- case BTC_ANT_PATH_BT:
- btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x20);
- break;
- default:
- case BTC_ANT_PATH_PTA:
- btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x4);
- break;
- }
-}
-
-void halbtc8192e1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist,
- IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5)
-{
- u8 h2c_parameter[5] = {0};
- u8 real_byte1 = byte1, real_byte5 = byte5;
- boolean ap_enable = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
- &ap_enable);
-
- if (ap_enable) {
- if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], FW for 1Ant AP mode\n");
- BTC_TRACE(trace_buf);
- real_byte1 &= ~BIT(4);
- real_byte1 |= BIT(5);
-
- real_byte5 |= BIT(5);
- real_byte5 &= ~BIT(6);
- }
- }
-
- h2c_parameter[0] = real_byte1;
- h2c_parameter[1] = byte2;
- h2c_parameter[2] = byte3;
- h2c_parameter[3] = byte4;
- h2c_parameter[4] = real_byte5;
-
- coex_dm->ps_tdma_para[0] = real_byte1;
- coex_dm->ps_tdma_para[1] = byte2;
- coex_dm->ps_tdma_para[2] = byte3;
- coex_dm->ps_tdma_para[3] = byte4;
- coex_dm->ps_tdma_para[4] = real_byte5;
-
- btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
-}
-
-
-void halbtc8192e1ant_ps_tdma(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean turn_on, IN u8 type)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_busy = false;
- u8 rssi_adjust_val = 0;
- u8 ps_tdma_byte4_val = 0x50, ps_tdma_byte0_val = 0x51,
- ps_tdma_byte3_val = 0x10;
- s8 wifi_duration_adjust = 0x0;
-
- coex_dm->cur_ps_tdma_on = turn_on;
- coex_dm->cur_ps_tdma = type;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- if (coex_dm->cur_ps_tdma_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** TDMA(on, %d) **********\n",
- coex_dm->cur_ps_tdma);
- BTC_TRACE(trace_buf);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** TDMA(off, %d) **********\n",
- coex_dm->cur_ps_tdma);
- BTC_TRACE(trace_buf);
- }
-
- if (!force_exec) {
- if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) &&
- (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma))
- return;
- }
-
- if (coex_sta->scan_ap_num <= 5)
- wifi_duration_adjust = 5;
- else if (coex_sta->scan_ap_num >= 40)
- wifi_duration_adjust = -15;
- else if (coex_sta->scan_ap_num >= 20)
- wifi_duration_adjust = -10;
-
- if (!coex_sta->force_lps_on) { /* only for A2DP-only case 1/2/9/11 while wifi noisy threshold > 30 */
- ps_tdma_byte0_val = 0x61; /* no null-pkt */
- ps_tdma_byte3_val = 0x11; /* no tx-pause at BT-slot */
- ps_tdma_byte4_val = 0x10; /* 0x778 = d/1 toggle */
- }
-
- if ((type == 3) || (type == 13) || (type == 14))
- ps_tdma_byte4_val = ps_tdma_byte4_val &
- 0xbf; /* no dynamic slot for multi-profile */
-
- if (bt_link_info->slave_role == true)
- ps_tdma_byte4_val = ps_tdma_byte4_val |
- 0x1; /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */
-
- if (turn_on) {
- switch (type) {
- default:
- halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x51,
- 0x1a, 0x1a, 0x0, ps_tdma_byte4_val);
- break;
- case 1:
- halbtc8192e1ant_set_fw_pstdma(btcoexist,
- ps_tdma_byte0_val, 0x3a +
- wifi_duration_adjust, 0x03,
- ps_tdma_byte3_val, ps_tdma_byte4_val);
- break;
- case 2:
- halbtc8192e1ant_set_fw_pstdma(btcoexist,
- ps_tdma_byte0_val, 0x2d +
- wifi_duration_adjust, 0x03,
- ps_tdma_byte3_val, ps_tdma_byte4_val);
- break;
- case 3:
- halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x51,
- 0x1d, 0x1d, 0x0, ps_tdma_byte4_val);
- break;
- case 4:
- halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x93,
- 0x15, 0x3, 0x14, 0x0);
- break;
- case 5:
- halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x61,
- 0x15, 0x3, 0x11, 0x11);
- break;
- case 6:
- halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x61,
- 0x20, 0x3, 0x11, 0x11);
- break;
- case 7:
- halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x13,
- 0xc, 0x5, 0x0, 0x0);
- break;
- case 8:
- halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x93,
- 0x25, 0x3, 0x10, 0x0);
- break;
- case 9:
- halbtc8192e1ant_set_fw_pstdma(btcoexist,
- ps_tdma_byte0_val, 0x21, 0x3,
- ps_tdma_byte3_val, ps_tdma_byte4_val);
- break;
- case 10:
- halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x13,
- 0xa, 0xa, 0x0, 0x40);
- break;
- case 11:
- halbtc8192e1ant_set_fw_pstdma(btcoexist,
- ps_tdma_byte0_val, 0x21, 0x03,
- ps_tdma_byte3_val, ps_tdma_byte4_val);
- break;
- case 12:
- halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x51,
- 0x0a, 0x0a, 0x0, 0x50);
- break;
- case 13:
- halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x51,
- 0x12, 0x12, 0x0, ps_tdma_byte4_val);
- break;
- case 14:
- halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x51,
- 0x21, 0x3, 0x10, ps_tdma_byte4_val);
- break;
- case 15:
- halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x13,
- 0xa, 0x3, 0x8, 0x0);
- break;
- case 16:
- halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x93,
- 0x15, 0x3, 0x10, 0x0);
- break;
- case 18:
- halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x93,
- 0x25, 0x3, 0x10, 0x0);
- break;
- case 20:
- halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x61,
- 0x3f, 0x03, 0x11, 0x10);
- break;
- case 21:
- halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x61,
- 0x25, 0x03, 0x11, 0x11);
- break;
- case 22:
- halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x61,
- 0x25, 0x03, 0x11, 0x10);
- break;
- case 23:
- halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x25, 0x3, 0x31, 0x18);
- break;
- case 24:
- halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x15, 0x3, 0x31, 0x18);
- break;
- case 25:
- halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xe3,
- 0xa, 0x3, 0x31, 0x18);
- break;
- case 26:
- halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xe3,
- 0xa, 0x3, 0x31, 0x18);
- break;
- case 27:
- halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x25, 0x3, 0x31, 0x98);
- break;
- case 28:
- halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x69,
- 0x25, 0x3, 0x31, 0x0);
- break;
- case 29:
- halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xab,
- 0x1a, 0x1a, 0x1, 0x10);
- break;
- case 30:
- halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x51,
- 0x30, 0x3, 0x10, 0x10);
- break;
- case 31:
- halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xd3,
- 0x1a, 0x1a, 0, 0x58);
- break;
- case 32:
- halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x61,
- 0x35, 0x3, 0x11, 0x11);
- break;
- case 33:
- halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xa3,
- 0x25, 0x3, 0x30, 0x90);
- break;
- case 34:
- halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x53,
- 0x1a, 0x1a, 0x0, 0x10);
- break;
- case 35:
- halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x63,
- 0x1a, 0x1a, 0x0, 0x10);
- break;
- case 36:
- halbtc8192e1ant_set_fw_pstdma(btcoexist, 0xd3,
- 0x12, 0x3, 0x14, 0x50);
- break;
- case 40: /* SoftAP only with no sta associated,BT disable ,TDMA mode for power saving */
- /* here softap mode screen off will cost 70-80mA for phone */
- halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x23,
- 0x18, 0x00, 0x10, 0x24);
- break;
- }
- } else {
-
- /* disable PS tdma */
- switch (type) {
- case 8: /* PTA Control */
- halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x8,
- 0x0, 0x0, 0x0, 0x0);
- halbtc8192e1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_PTA, false, false);
- break;
- case 0:
- default: /* Software control, Antenna at BT side */
- halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x0,
- 0x0, 0x0, 0x0, 0x0);
- halbtc8192e1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_BT, false, false);
- break;
- case 9: /* Software control, Antenna at WiFi side */
- halbtc8192e1ant_set_fw_pstdma(btcoexist, 0x0,
- 0x0, 0x0, 0x0, 0x0);
- halbtc8192e1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_WIFI, false, false);
- break;
- }
- }
- rssi_adjust_val = 0;
- btcoexist->btc_set(btcoexist,
- BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE, &rssi_adjust_val);
-
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x\n",
- btcoexist->btc_read_4byte(btcoexist, 0x948),
- btcoexist->btc_read_1byte(btcoexist, 0x765),
- btcoexist->btc_read_1byte(btcoexist, 0x67));
- BTC_TRACE(trace_buf);
- /* update pre state */
- coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on;
- coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
-}
-
-void halbtc8192e1ant_coex_all_off(IN struct btc_coexist *btcoexist)
-{
- /* sw all off */
- halbtc8192e1ant_sw_mechanism(btcoexist, false);
-
- /* hw all off */
- halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-}
-
-boolean halbtc8192e1ant_is_common_action(IN struct btc_coexist *btcoexist)
-{
- boolean common = false, wifi_connected = false, wifi_busy = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- if (!wifi_connected &&
- BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
- coex_dm->bt_status) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n");
- BTC_TRACE(trace_buf);
- /* halbtc8192e1ant_sw_mechanism(btcoexist, false); */
-
- common = true;
- } else if (wifi_connected &&
- (BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
- coex_dm->bt_status)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi connected + BT non connected-idle!!\n");
- BTC_TRACE(trace_buf);
- /* halbtc8192e1ant_sw_mechanism(btcoexist, false); */
-
- common = true;
- } else if (!wifi_connected &&
- (BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi non connected-idle + BT connected-idle!!\n");
- BTC_TRACE(trace_buf);
- /* halbtc8192e1ant_sw_mechanism(btcoexist, false); */
-
- common = true;
- } else if (wifi_connected &&
- (BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi connected + BT connected-idle!!\n");
- BTC_TRACE(trace_buf);
- /* halbtc8192e1ant_sw_mechanism(btcoexist, false); */
-
- common = true;
- } else if (!wifi_connected &&
- (BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE != coex_dm->bt_status)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi non connected-idle + BT Busy!!\n");
- BTC_TRACE(trace_buf);
- /* halbtc8192e1ant_sw_mechanism(btcoexist, false); */
-
- common = true;
- } else {
- if (wifi_busy) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi Connected-Busy + BT Busy!!\n");
- BTC_TRACE(trace_buf);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi Connected-Idle + BT Busy!!\n");
- BTC_TRACE(trace_buf);
- }
-
- common = false;
- }
-
- return common;
-}
-
-
-void halbtc8192e1ant_tdma_duration_adjust_for_acl(IN struct btc_coexist
- *btcoexist, IN u8 wifi_status)
-{
- static s32 up, dn, m, n, wait_count;
- s32 result; /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */
- u8 retry_count = 0, bt_info_ext;
- boolean wifi_busy = false;
- /*static boolean pre_wifi_busy = false;*/
-
- if (BT_8192E_1ANT_WIFI_STATUS_CONNECTED_BUSY == wifi_status)
- wifi_busy = true;
- else
- wifi_busy = false;
-
- if ((BT_8192E_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN ==
- wifi_status) ||
- (BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SCAN == wifi_status) ||
- (BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT ==
- wifi_status)) {
- if (coex_dm->cur_ps_tdma != 1 &&
- coex_dm->cur_ps_tdma != 2 &&
- coex_dm->cur_ps_tdma != 3 &&
- coex_dm->cur_ps_tdma != 9) {
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 9);
- coex_dm->ps_tdma_du_adj_type = 9;
-
- up = 0;
- dn = 0;
- m = 1;
- n = 3;
- result = 0;
- wait_count = 0;
- }
- return;
- }
-
- if (!coex_dm->auto_tdma_adjust) {
- coex_dm->auto_tdma_adjust = true;
-
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 2);
- coex_dm->ps_tdma_du_adj_type = 2;
- /* ============ */
- up = 0;
- dn = 0;
- m = 1;
- n = 3;
- result = 0;
- wait_count = 0;
- } else {
- /* accquire the BT TRx retry count from BT_Info byte2 */
- retry_count = coex_sta->bt_retry_cnt;
- bt_info_ext = coex_sta->bt_info_ext;
-
- if ((coex_sta->low_priority_tx) > 1050 ||
- (coex_sta->low_priority_rx) > 1250)
- retry_count++;
-
- result = 0;
- wait_count++;
-
- if (retry_count ==
- 0) { /* no retry in the last 2-second duration */
- up++;
- dn--;
-
- if (dn <= 0)
- dn = 0;
-
- if (up >= n) { /* if retry count during continuous n*2 seconds is 0, enlarge WiFi duration */
- wait_count = 0;
- n = 3;
- up = 0;
- dn = 0;
- result = 1;
- }
- } else if (retry_count <=
- 3) { /* <=3 retry in the last 2-second duration */
- up--;
- dn++;
-
- if (up <= 0)
- up = 0;
-
- if (dn == 2) { /* if continuous 2 retry count(every 2 seconds) >0 and < 3, reduce WiFi duration */
- if (wait_count <= 2)
- m++; /* to avoid loop between the two levels */
- else
- m = 1;
-
- if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */
- m = 20;
-
- n = 3 * m;
- up = 0;
- dn = 0;
- wait_count = 0;
- result = -1;
- }
- } else { /* retry count > 3, once retry count > 3, to reduce WiFi duration */
- if (wait_count == 1)
- m++; /* to avoid loop between the two levels */
- else
- m = 1;
-
- if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */
- m = 20;
-
- n = 3 * m;
- up = 0;
- dn = 0;
- wait_count = 0;
- result = -1;
- }
-
- if (result == -1) {
- if ((BT_INFO_8192E_1ANT_A2DP_BASIC_RATE(bt_info_ext)) &&
- ((coex_dm->cur_ps_tdma == 1) ||
- (coex_dm->cur_ps_tdma == 2))) {
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 9);
- coex_dm->ps_tdma_du_adj_type = 9;
- } else if (coex_dm->cur_ps_tdma == 1) {
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 2);
- coex_dm->ps_tdma_du_adj_type = 2;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 9);
- coex_dm->ps_tdma_du_adj_type = 9;
- } else if (coex_dm->cur_ps_tdma == 9) {
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type = 11;
- }
- } else if (result == 1) {
- if ((BT_INFO_8192E_1ANT_A2DP_BASIC_RATE(bt_info_ext)) &&
- ((coex_dm->cur_ps_tdma == 1) ||
- (coex_dm->cur_ps_tdma == 2))) {
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 9);
- coex_dm->ps_tdma_du_adj_type = 9;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 9);
- coex_dm->ps_tdma_du_adj_type = 9;
- } else if (coex_dm->cur_ps_tdma == 9) {
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 2);
- coex_dm->ps_tdma_du_adj_type = 2;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 1);
- coex_dm->ps_tdma_du_adj_type = 1;
- }
- } else { /* no change */
- /* Bryant Modify
- if(wifi_busy != pre_wifi_busy)
- {
- pre_wifi_busy = wifi_busy;
- halbtc8192e1ant_ps_tdma(btcoexist, FORCE_EXEC, true, coex_dm->cur_ps_tdma);
- }
- */
- }
-
- if (coex_dm->cur_ps_tdma != 1 &&
- coex_dm->cur_ps_tdma != 2 &&
- coex_dm->cur_ps_tdma != 9 &&
- coex_dm->cur_ps_tdma != 11) {
- /* recover to previous adjust type */
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- coex_dm->ps_tdma_du_adj_type);
- }
- }
-}
-
-void halbtc8192e1ant_ps_tdma_check_for_power_save_state(
- IN struct btc_coexist *btcoexist, IN boolean new_ps_state)
-{
- u8 lps_mode = 0x0;
-
- btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode);
-
- if (lps_mode) { /* already under LPS state */
- if (new_ps_state) {
- /* keep state under LPS, do nothing. */
- } else {
- /* will leave LPS state, turn off psTdma first */
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 0);
- }
- } else { /* NO PS state */
- if (new_ps_state) {
- /* will enter LPS state, turn off psTdma first */
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 0);
- } else {
- /* keep state under NO PS state, do nothing. */
- }
- }
-}
-
-void halbtc8192e1ant_power_save_state(IN struct btc_coexist *btcoexist,
- IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val)
-{
- boolean low_pwr_disable = false;
-
- switch (ps_type) {
- case BTC_PS_WIFI_NATIVE:
- /* recover to original 32k low power setting */
- low_pwr_disable = false;
- btcoexist->btc_set(btcoexist,
- BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS,
- NULL);
- coex_sta->force_lps_on = false;
- break;
- case BTC_PS_LPS_ON:
- halbtc8192e1ant_ps_tdma_check_for_power_save_state(
- btcoexist, true);
- halbtc8192e1ant_lps_rpwm(btcoexist, NORMAL_EXEC,
- lps_val, rpwm_val);
- /* when coex force to enter LPS, do not enter 32k low power. */
- low_pwr_disable = true;
- btcoexist->btc_set(btcoexist,
- BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
- /* power save must executed before psTdma. */
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS,
- NULL);
- coex_sta->force_lps_on = true;
- break;
- case BTC_PS_LPS_OFF:
- halbtc8192e1ant_ps_tdma_check_for_power_save_state(
- btcoexist, false);
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS,
- NULL);
- coex_sta->force_lps_on = false;
- break;
- default:
- break;
- }
-}
-
-void halbtc8192e1ant_action_wifi_only(IN struct btc_coexist *btcoexist)
-{
- halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 9);
-}
-
-void halbtc8192e1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist)
-{
- static u32 bt_disable_cnt = 0;
- boolean bt_active = true, bt_disabled = false;
-
- /* This function check if bt is disabled */
-
- if (coex_sta->high_priority_tx == 0 &&
- coex_sta->high_priority_rx == 0 &&
- coex_sta->low_priority_tx == 0 &&
- coex_sta->low_priority_rx == 0)
- bt_active = false;
- if (coex_sta->high_priority_tx == 0xffff &&
- coex_sta->high_priority_rx == 0xffff &&
- coex_sta->low_priority_tx == 0xffff &&
- coex_sta->low_priority_rx == 0xffff)
- bt_active = false;
- if (bt_active) {
- bt_disable_cnt = 0;
- bt_disabled = false;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
- &bt_disabled);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is enabled !!\n");
- BTC_TRACE(trace_buf);
- } else {
- bt_disable_cnt++;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], bt all counters=0, %d times!!\n",
- bt_disable_cnt);
- BTC_TRACE(trace_buf);
- if (bt_disable_cnt >= 2) {
- bt_disabled = true;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
- &bt_disabled);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is disabled !!\n");
- BTC_TRACE(trace_buf);
- halbtc8192e1ant_action_wifi_only(btcoexist);
- }
- }
- if (coex_sta->bt_disabled != bt_disabled) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is from %s to %s!!\n",
- (coex_sta->bt_disabled ? "disabled" : "enabled"),
- (bt_disabled ? "disabled" : "enabled"));
- BTC_TRACE(trace_buf);
- coex_sta->bt_disabled = bt_disabled;
- if (!bt_disabled) {
- } else {
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS,
- NULL);
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS,
- NULL);
- }
- }
-}
-
-/* *********************************************
- *
- * Software Coex Mechanism start
- *
- * ********************************************* */
-
-/* SCO only or SCO+PAN(HS) */
-
-/*
-void halbtc8192e1ant_action_sco(IN struct btc_coexist* btcoexist)
-{
- halbtc8192e1ant_sw_mechanism(btcoexist, true);
-}
-
-
-void halbtc8192e1ant_action_hid(IN struct btc_coexist* btcoexist)
-{
- halbtc8192e1ant_sw_mechanism(btcoexist, true);
-}
-
-
-void halbtc8192e1ant_action_a2dp(IN struct btc_coexist* btcoexist)
-{
- halbtc8192e1ant_sw_mechanism(btcoexist, false);
-}
-
-void halbtc8192e1ant_action_a2dp_pan_hs(IN struct btc_coexist* btcoexist)
-{
- halbtc8192e1ant_sw_mechanism(btcoexist, false);
-}
-
-void halbtc8192e1ant_action_pan_edr(IN struct btc_coexist* btcoexist)
-{
- halbtc8192e1ant_sw_mechanism(btcoexist, false);
-}
-
-
-void halbtc8192e1ant_action_pan_hs(IN struct btc_coexist* btcoexist)
-{
- halbtc8192e1ant_sw_mechanism(btcoexist, false);
-}
-
-
-void halbtc8192e1ant_action_pan_edr_a2dp(IN struct btc_coexist* btcoexist)
-{
- halbtc8192e1ant_sw_mechanism(btcoexist, false);
-}
-
-void halbtc8192e1ant_action_pan_edr_hid(IN struct btc_coexist* btcoexist)
-{
- halbtc8192e1ant_sw_mechanism(btcoexist, true);
-}
-
-
-void halbtc8192e1ant_action_hid_a2dp_pan_edr(IN struct btc_coexist* btcoexist)
-{
- halbtc8192e1ant_sw_mechanism(btcoexist, true);
-}
-
-void halbtc8192e1ant_action_hid_a2dp(IN struct btc_coexist* btcoexist)
-{
- halbtc8192e1ant_sw_mechanism(btcoexist, true);
-}
-
-*/
-
-/* *********************************************
- *
- * Non-Software Coex Mechanism start
- *
- * ********************************************* */
-void halbtc8192e1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist)
-{
- halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
-
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
-}
-
-void halbtc8192e1ant_action_hs(IN struct btc_coexist *btcoexist)
-{
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
- halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
-}
-
-void halbtc8192e1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_connected = false, ap_enable = false, wifi_busy = false,
- bt_busy = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
- &ap_enable);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
-
- if ((!wifi_connected) && (!coex_sta->wifi_is_high_pri_task)) {
- halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
-
- halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
- } else if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) ||
- (bt_link_info->a2dp_exist)) {
- /* SCO/HID/A2DP busy */
- halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
-
- halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- } else if ((bt_link_info->pan_exist) || (wifi_busy)) {
- halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
-
- halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- } else {
- halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
-
- halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
- }
-}
-
-void halbtc8192e1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist
- *btcoexist, IN u8 wifi_status)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_connected = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
-
- /* tdma and coex table */
-
- if (bt_link_info->sco_exist) {
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
- halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
- } else { /* HID */
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 6);
- halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
- }
-}
-
-void halbtc8192e1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist
- *btcoexist, IN u8 wifi_status)
-{
- u8 bt_rssi_state;
-
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- bt_rssi_state = halbtc8192e1ant_bt_rssi_state(2, 28, 0);
-
- if ((coex_sta->low_priority_rx >= 1000) &&
- (coex_sta->low_priority_rx != 65535))
- bt_link_info->slave_role = true;
- else
- bt_link_info->slave_role = false;
-
- if (bt_link_info->hid_only) { /* HID */
- halbtc8192e1ant_action_bt_sco_hid_only_busy(btcoexist,
- wifi_status);
- coex_dm->auto_tdma_adjust = false;
- return;
- } else if (bt_link_info->a2dp_only) { /* A2DP */
- if (BT_8192E_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifi_status) {
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 32);
- halbtc8192e1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- coex_dm->auto_tdma_adjust = false;
- } else {
- halbtc8192e1ant_tdma_duration_adjust_for_acl(btcoexist,
- wifi_status);
-#if 0
- if (coex_sta->cck_lock)
- halbtc8192e1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 3);
- else
-#endif
- halbtc8192e1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- coex_dm->auto_tdma_adjust = true;
- }
- } else if (((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) ||
- (bt_link_info->hid_exist && bt_link_info->a2dp_exist &&
- bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13);
- halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- coex_dm->auto_tdma_adjust = false;
- } else if (bt_link_info->hid_exist &&
- bt_link_info->a2dp_exist) { /* HID+A2DP */
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14);
- coex_dm->auto_tdma_adjust = false;
-
- halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
- } else if ((bt_link_info->pan_only) || (bt_link_info->hid_exist &&
- bt_link_info->pan_exist)) { /* PAN(OPP,FTP), HID+PAN(OPP,FTP) */
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3);
- halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- coex_dm->auto_tdma_adjust = false;
- } else {
- /* BT no-profile busy (0x9) */
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
- halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- coex_dm->auto_tdma_adjust = false;
- }
-}
-
-void halbtc8192e1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist)
-{
- /* power save state */
- halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
-
- /* tdma and coex table */
- halbtc8192e1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8);
- halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-}
-
-void halbtc8192e1ant_action_wifi_not_connected_scan(IN struct btc_coexist
- *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
- halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
-
- /* tdma and coex table */
- if (BT_8192E_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
- if (bt_link_info->a2dp_exist) {
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 32);
- halbtc8192e1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- } else if (bt_link_info->a2dp_exist &&
- bt_link_info->pan_exist) {
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 22);
- halbtc8192e1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- } else {
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 20);
- halbtc8192e1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- }
- } else if ((BT_8192E_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
- (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY ==
- coex_dm->bt_status)) {
- halbtc8192e1ant_action_bt_sco_hid_only_busy(btcoexist,
- BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SCAN);
- } else {
- /* Bryant Add */
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
- }
-}
-
-void halbtc8192e1ant_action_wifi_not_connected_asso_auth(
- IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
- halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
-
- /* tdma and coex table */
- if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) ||
- (bt_link_info->a2dp_exist)) {
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
- halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- } else if (bt_link_info->pan_exist) {
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
- halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- } else {
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
- }
-}
-
-void halbtc8192e1ant_action_wifi_connected_scan(IN struct btc_coexist
- *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
- halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
-
- /* tdma and coex table */
- if (BT_8192E_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
- if (bt_link_info->a2dp_exist) {
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 32);
- halbtc8192e1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- } else if (bt_link_info->a2dp_exist &&
- bt_link_info->pan_exist) {
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 22);
- halbtc8192e1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- } else {
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 20);
- halbtc8192e1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- }
- } else if ((BT_8192E_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
- (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY ==
- coex_dm->bt_status)) {
- halbtc8192e1ant_action_bt_sco_hid_only_busy(btcoexist,
- BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SCAN);
- } else {
- /* Bryant Add */
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
- }
-}
-
-void halbtc8192e1ant_action_wifi_connected_specific_packet(
- IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
- halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
-
- /* tdma and coex table */
- if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) ||
- (bt_link_info->a2dp_exist)) {
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
- halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- } else if (bt_link_info->pan_exist) {
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
- halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- } else {
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
- }
-}
-
-void halbtc8192e1ant_action_wifi_connected(IN struct btc_coexist *btcoexist)
-{
- boolean wifi_busy = false;
- boolean scan = false, link = false, roam = false;
- boolean under_4way = false, ap_enable = false;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CoexForWifiConnect()===>\n");
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
- &under_4way);
- if (under_4way) {
- halbtc8192e1ant_action_wifi_connected_specific_packet(btcoexist);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CoexForWifiConnect(), return for wifi is under 4way<===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
- if (scan || link || roam) {
- if (scan)
- halbtc8192e1ant_action_wifi_connected_scan(btcoexist);
- else
- halbtc8192e1ant_action_wifi_connected_specific_packet(
- btcoexist);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CoexForWifiConnect(), return for wifi is under scan<===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
- &ap_enable);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- /* power save state */
- if (!ap_enable &&
- BT_8192E_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status &&
- !btcoexist->bt_link_info.hid_only) {
- if (btcoexist->bt_link_info.a2dp_only) { /* A2DP */
- if (!wifi_busy)
- halbtc8192e1ant_power_save_state(btcoexist,
- BTC_PS_WIFI_NATIVE, 0x0, 0x0);
- else { /* busy */
- if (coex_sta->scan_ap_num >=
- BT_8192E_1ANT_WIFI_NOISY_THRESH) /* no force LPS, no PS-TDMA, use pure TDMA */
- halbtc8192e1ant_power_save_state(
- btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- else
- halbtc8192e1ant_power_save_state(
- btcoexist, BTC_PS_LPS_ON, 0x50,
- 0x4);
- }
- } else if ((coex_sta->pan_exist == false) &&
- (coex_sta->a2dp_exist == false) &&
- (coex_sta->hid_exist == false))
- halbtc8192e1ant_power_save_state(btcoexist,
- BTC_PS_WIFI_NATIVE, 0x0, 0x0);
- else
- halbtc8192e1ant_power_save_state(btcoexist,
- BTC_PS_LPS_ON, 0x50, 0x4);
- } else
- halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
-
- /* tdma and coex table */
- if (!wifi_busy) {
- if (BT_8192E_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
- halbtc8192e1ant_action_wifi_connected_bt_acl_busy(
- btcoexist,
- BT_8192E_1ANT_WIFI_STATUS_CONNECTED_IDLE);
- } else if ((BT_8192E_1ANT_BT_STATUS_SCO_BUSY ==
- coex_dm->bt_status) ||
- (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY ==
- coex_dm->bt_status)) {
- halbtc8192e1ant_action_bt_sco_hid_only_busy(btcoexist,
- BT_8192E_1ANT_WIFI_STATUS_CONNECTED_IDLE);
- } else {
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 8);
-
- if ((coex_sta->high_priority_tx) +
- (coex_sta->high_priority_rx) <= 60)
- halbtc8192e1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 2);
- else
- halbtc8192e1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 7);
- }
- } else {
- if (BT_8192E_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
- halbtc8192e1ant_action_wifi_connected_bt_acl_busy(
- btcoexist,
- BT_8192E_1ANT_WIFI_STATUS_CONNECTED_BUSY);
- } else if ((BT_8192E_1ANT_BT_STATUS_SCO_BUSY ==
- coex_dm->bt_status) ||
- (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY ==
- coex_dm->bt_status)) {
- halbtc8192e1ant_action_bt_sco_hid_only_busy(btcoexist,
- BT_8192E_1ANT_WIFI_STATUS_CONNECTED_BUSY);
- } else {
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 8);
-
- if ((coex_sta->high_priority_tx) +
- (coex_sta->high_priority_rx) <= 60)
- halbtc8192e1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 2);
- else
- halbtc8192e1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 7);
- }
- }
-}
-
-void halbtc8192e1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist)
-{
- u8 algorithm = 0;
-
- algorithm = halbtc8192e1ant_action_algorithm(btcoexist);
- coex_dm->cur_algorithm = algorithm;
-
- if (halbtc8192e1ant_is_common_action(btcoexist)) {
-
- } else {
- switch (coex_dm->cur_algorithm) {
- case BT_8192E_1ANT_COEX_ALGO_SCO:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = SCO.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8192e1ant_action_sco(btcoexist); */
- break;
- case BT_8192E_1ANT_COEX_ALGO_HID:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = HID.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8192e1ant_action_hid(btcoexist); */
- break;
- case BT_8192E_1ANT_COEX_ALGO_A2DP:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = A2DP.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8192e1ant_action_a2dp(btcoexist); */
- break;
- case BT_8192E_1ANT_COEX_ALGO_A2DP_PANHS:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = A2DP+PAN(HS).\n");
- BTC_TRACE(trace_buf);
- /* halbtc8192e1ant_action_a2dp_pan_hs(btcoexist); */
- break;
- case BT_8192E_1ANT_COEX_ALGO_PANEDR:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = PAN(EDR).\n");
- BTC_TRACE(trace_buf);
- /* halbtc8192e1ant_action_pan_edr(btcoexist); */
- break;
- case BT_8192E_1ANT_COEX_ALGO_PANHS:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = HS mode.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8192e1ant_action_pan_hs(btcoexist); */
- break;
- case BT_8192E_1ANT_COEX_ALGO_PANEDR_A2DP:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = PAN+A2DP.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8192e1ant_action_pan_edr_a2dp(btcoexist); */
- break;
- case BT_8192E_1ANT_COEX_ALGO_PANEDR_HID:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = PAN(EDR)+HID.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8192e1ant_action_pan_edr_hid(btcoexist); */
- break;
- case BT_8192E_1ANT_COEX_ALGO_HID_A2DP_PANEDR:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = HID+A2DP+PAN.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8192e1ant_action_hid_a2dp_pan_edr(btcoexist); */
- break;
- case BT_8192E_1ANT_COEX_ALGO_HID_A2DP:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = HID+A2DP.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8192e1ant_action_hid_a2dp(btcoexist); */
- break;
- default:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = coexist All Off!!\n");
- BTC_TRACE(trace_buf);
- /* halbtc8192e1ant_coex_all_off(btcoexist); */
- break;
- }
- coex_dm->pre_algorithm = coex_dm->cur_algorithm;
- }
-}
-
-void halbtc8192e1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_connected = false, bt_hs_on = false;
- boolean increase_scan_dev_num = false;
- boolean bt_ctrl_agg_buf_size = false;
- boolean miracast_plus_bt = false;
- u8 agg_buf_size = 5;
- u32 wifi_link_status = 0;
- u32 num_of_wifi_link = 0;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism()===>\n");
- BTC_TRACE(trace_buf);
-
- if (btcoexist->manual_control) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- if (btcoexist->stop_coex_dm) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- if (coex_sta->under_ips) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], wifi is under IPS !!!\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- if ((BT_8192E_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
- (BT_8192E_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
- (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status))
- increase_scan_dev_num = true;
-
- btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM,
- &increase_scan_dev_num);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
- num_of_wifi_link = wifi_link_status >> 16;
-
- if ((num_of_wifi_link >= 2) ||
- (wifi_link_status & WIFI_P2P_GO_CONNECTED)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n",
- num_of_wifi_link, wifi_link_status);
- BTC_TRACE(trace_buf);
-
- if (bt_link_info->bt_link_exist) {
- halbtc8192e1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1,
- 0, 1);
- miracast_plus_bt = true;
- } else {
- halbtc8192e1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0,
- 0, 0);
- miracast_plus_bt = false;
- }
- btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
- &miracast_plus_bt);
- halbtc8192e1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
- bt_ctrl_agg_buf_size, agg_buf_size);
-
- if ((bt_link_info->a2dp_exist) &&
- (coex_sta->c2h_bt_inquiry_page)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], BT Is Inquirying\n");
- BTC_TRACE(trace_buf);
- halbtc8192e1ant_action_bt_inquiry(btcoexist);
- } else
- halbtc8192e1ant_action_wifi_multi_port(btcoexist);
-
- return;
- } else {
- miracast_plus_bt = false;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
- &miracast_plus_bt);
- }
-
- if ((bt_link_info->bt_link_exist) && (wifi_connected)) {
- halbtc8192e1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, 0, 1);
-
- if (bt_link_info->sco_exist)
- halbtc8192e1ant_limited_rx(btcoexist, NORMAL_EXEC,
- false, true, 0x5);
- else
- halbtc8192e1ant_limited_rx(btcoexist, NORMAL_EXEC,
- false, true, 0x8);
-
- halbtc8192e1ant_sw_mechanism(btcoexist, true);
- halbtc8192e1ant_run_sw_coexist_mechanism(
- btcoexist); /* just print debug message */
- } else {
- halbtc8192e1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
-
- halbtc8192e1ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
- 0x5);
-
- halbtc8192e1ant_sw_mechanism(btcoexist, false);
- halbtc8192e1ant_run_sw_coexist_mechanism(
- btcoexist); /* just print debug message */
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- if (coex_sta->c2h_bt_inquiry_page) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], BT Is Inquirying\n");
- BTC_TRACE(trace_buf);
- halbtc8192e1ant_action_bt_inquiry(btcoexist);
- return;
- } else if (bt_hs_on) {
- halbtc8192e1ant_action_hs(btcoexist);
- return;
- }
-
-
- if (!wifi_connected) {
- boolean scan = false, link = false, roam = false;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], wifi is non connected-idle !!!\n");
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
-
- if (scan || link || roam) {
- if (scan)
- halbtc8192e1ant_action_wifi_not_connected_scan(
- btcoexist);
- else
- halbtc8192e1ant_action_wifi_not_connected_asso_auth(
- btcoexist);
- } else
- halbtc8192e1ant_action_wifi_not_connected(btcoexist);
- } else /* wifi LPS/Busy */
- halbtc8192e1ant_action_wifi_connected(btcoexist);
-}
-
-void halbtc8192e1ant_init_coex_dm(IN struct btc_coexist *btcoexist)
-{
- /* force to reset coex mechanism */
-
- /* sw all off */
- halbtc8192e1ant_sw_mechanism(btcoexist, false);
-
- /* halbtc8192e1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); */
- halbtc8192e1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
-
- coex_sta->pop_event_cnt = 0;
-}
-
-void halbtc8192e1ant_init_hw_config(IN struct btc_coexist *btcoexist,
- IN boolean wifi_only)
-{
- u16 u16tmp = 0;
- u8 u8tmp = 0;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], 1Ant Init HW Config!!\n");
- BTC_TRACE(trace_buf);
-
- /* antenna sw ctrl to bt */
- halbtc8192e1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, true, false);
-
- halbtc8192e1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
-
- /* antenna switch control parameter */
- btcoexist->btc_write_4byte(btcoexist, 0x858, 0x55555555);
-
- /* coex parameters */
- btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1);
- /* 0x790[5:0]=0x5 */
- u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790);
- u8tmp &= 0xc0;
- u8tmp |= 0x5;
- btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp);
-
- /* enable counter statistics */
- btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4);
-
- /* enable PTA */
- btcoexist->btc_write_1byte(btcoexist, 0x40, 0x20);
- /* enable mailbox interface */
- u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x40);
- u16tmp |= BIT(9);
- btcoexist->btc_write_2byte(btcoexist, 0x40, u16tmp);
-
- /* enable PTA I2C mailbox */
- u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x101);
- u8tmp |= BIT(4);
- btcoexist->btc_write_1byte(btcoexist, 0x101, u8tmp);
-
- /* enable bt clock when wifi is disabled. */
- u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x93);
- u8tmp |= BIT(0);
- btcoexist->btc_write_1byte(btcoexist, 0x93, u8tmp);
- /* enable bt clock when suspend. */
- u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x7);
- u8tmp |= BIT(0);
- btcoexist->btc_write_1byte(btcoexist, 0x7, u8tmp);
-}
-
-
-/*
-void halbtc8192e1ant_wifi_off_hw_cfg(IN struct btc_coexist* btcoexist)
-{
-
-
-}
-*/
-
-/* ************************************************************
- * work around function start with wa_halbtc8192e1ant_
- * ************************************************************
- * ************************************************************
- * extern function start with ex_halbtc8192e1ant_
- * ************************************************************ */
-void ex_halbtc8192e1ant_power_on_setting(IN struct btc_coexist *btcoexist)
-{
-#if 0
- struct btc_board_info *board_info = &btcoexist->board_info;
- u8 u8tmp = 0x0;
- u16 u16tmp = 0x0;
-
- btcoexist->stop_coex_dm = true;
-
- btcoexist->btc_write_1byte(btcoexist, 0x67, 0x20);
-
- /* enable BB, REG_SYS_FUNC_EN such that we can write 0x948 correctly. */
- u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2);
- btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1));
-
- /* set GRAN_BT = 1 */
- btcoexist->btc_write_1byte(btcoexist, 0x765, 0x18);
- /* set WLAN_ACT = 0 */
- btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4);
-
- /* */
- /* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */
- /* Local setting bit define */
- /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */
- /* BIT1: "0" for internal switch; "1" for external switch */
- /* BIT2: "0" for one antenna; "1" for two antenna */
- /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */
- if (btcoexist->chip_interface == BTC_INTF_USB) {
- /* fixed at S0 for USB interface */
- btcoexist->btc_write_4byte(btcoexist, 0x948, 0x0);
-
- u8tmp |= 0x1; /* antenna inverse */
- btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp);
-
- board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT;
- } else {
- /* for PCIE and SDIO interface, we check efuse 0xc3[6] */
- if (board_info->single_ant_path == 0) {
- /* set to S1 */
- btcoexist->btc_write_4byte(btcoexist, 0x948, 0x280);
- board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;
- } else if (board_info->single_ant_path == 1) {
- /* set to S0 */
- btcoexist->btc_write_4byte(btcoexist, 0x948, 0x0);
- u8tmp |= 0x1; /* antenna inverse */
- board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT;
- }
-
- if (btcoexist->chip_interface == BTC_INTF_PCI)
- btcoexist->btc_write_local_reg_1byte(btcoexist, 0x384,
- u8tmp);
- else if (btcoexist->chip_interface == BTC_INTF_SDIO)
- btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60,
- u8tmp);
- }
-#endif
-}
-
-void ex_halbtc8192e1ant_pre_load_firmware(IN struct btc_coexist *btcoexist)
-{
-}
-
-void ex_halbtc8192e1ant_init_hw_config(IN struct btc_coexist *btcoexist,
- IN boolean wifi_only)
-{
- halbtc8192e1ant_init_hw_config(btcoexist, wifi_only);
- btcoexist->stop_coex_dm = false;
-}
-
-void ex_halbtc8192e1ant_init_coex_dm(IN struct btc_coexist *btcoexist)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Coex Mechanism Init!!\n");
- BTC_TRACE(trace_buf);
-
- btcoexist->stop_coex_dm = false;
-
- halbtc8192e1ant_init_coex_dm(btcoexist);
-
- halbtc8192e1ant_query_bt_info(btcoexist);
-}
-
-void ex_halbtc8192e1ant_display_coex_info(IN struct btc_coexist *btcoexist)
-{
- struct btc_board_info *board_info = &btcoexist->board_info;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- u8 *cli_buf = btcoexist->cli_buf;
- u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0;
- u32 u32tmp[4];
- u32 fw_ver = 0, bt_patch_ver = 0;
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ============[BT Coexist info]============");
- CL_PRINTF(cli_buf);
-
- if (btcoexist->manual_control) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ============[Under Manual Control]============");
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ==========================================");
- CL_PRINTF(cli_buf);
- }
- if (btcoexist->stop_coex_dm) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ============[Coex is STOPPED]============");
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ==========================================");
- CL_PRINTF(cli_buf);
- }
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ",
- "Ant PG number/ Ant mechanism:",
- board_info->pg_ant_num, board_info->btdm_ant_num);
- CL_PRINTF(cli_buf);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %d_%d/ 0x%x/ 0x%x(%d)",
- "CoexVer/ FwVer/ PatchVer",
- glcoex_ver_date_8192e_1ant, glcoex_ver_8192e_1ant, fw_ver,
- bt_patch_ver, bt_patch_ver);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ",
- "Wifi channel informed to BT",
- coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
- coex_dm->wifi_chnl_info[2]);
- CL_PRINTF(cli_buf);
-
- /* wifi status */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Wifi Status]============");
- CL_PRINTF(cli_buf);
- btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[BT Status]============");
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ",
- "BT [status/ rssi/ retryCnt]",
- ((coex_sta->bt_disabled) ? ("disabled") : ((
- coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan")
- : ((BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
- coex_dm->bt_status) ? "non-connected idle" :
- ((BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)
- ? "connected-idle" : "busy")))),
- coex_sta->bt_rssi, coex_sta->bt_retry_cnt);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d",
- "SCO/HID/PAN/A2DP",
- bt_link_info->sco_exist, bt_link_info->hid_exist,
- bt_link_info->pan_exist, bt_link_info->a2dp_exist);
- CL_PRINTF(cli_buf);
- btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_BT_LINK_INFO);
-
- bt_info_ext = coex_sta->bt_info_ext;
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
- "BT Info A2DP rate",
- (bt_info_ext & BIT(0)) ? "Basic rate" : "EDR rate");
- CL_PRINTF(cli_buf);
-
- for (i = 0; i < BT_INFO_SRC_8192E_1ANT_MAX; i++) {
- if (coex_sta->bt_info_c2h_cnt[i]) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)",
- glbt_info_src_8192e_1ant[i],
- coex_sta->bt_info_c2h[i][0],
- coex_sta->bt_info_c2h[i][1],
- coex_sta->bt_info_c2h[i][2],
- coex_sta->bt_info_c2h[i][3],
- coex_sta->bt_info_c2h[i][4],
- coex_sta->bt_info_c2h[i][5],
- coex_sta->bt_info_c2h[i][6],
- coex_sta->bt_info_c2h_cnt[i]);
- CL_PRINTF(cli_buf);
- }
- }
-
- if (!btcoexist->manual_control) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[mechanisms]============");
- CL_PRINTF(cli_buf);
-
- ps_tdma_case = coex_dm->cur_ps_tdma;
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (auto:%d)",
- "PS TDMA",
- coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],
- coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],
- coex_dm->ps_tdma_para[4], ps_tdma_case,
- coex_dm->auto_tdma_adjust);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ",
- "Latest error condition(should be 0)",
- coex_dm->error_condition);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ",
- "IgnWlanAct",
- coex_dm->cur_ignore_wlan_act);
- CL_PRINTF(cli_buf);
- }
-
- /* Hw setting */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Hw setting]============");
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc04);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xd04);
- u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x90c);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
- "0xc04/ 0xd04/ 0x90c",
- u32tmp[0], u32tmp[1], u32tmp[2]);
- CL_PRINTF(cli_buf);
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x778",
- u8tmp[0]);
- CL_PRINTF(cli_buf);
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x92c);
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x930);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
- "0x92c/ 0x930",
- (u8tmp[0]), u32tmp[0]);
- CL_PRINTF(cli_buf);
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x40);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x4f);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
- "0x40/ 0x4f",
- u8tmp[0], u8tmp[1]);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
- "0x550(bcn ctrl)/0x522",
- u32tmp[0], u8tmp[0]);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)",
- u32tmp[0]);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
- u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x6cc);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
- "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)",
- u32tmp[0], u32tmp[1], u32tmp[2], u8tmp[0]);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
- "0x770(hp rx[31:16]/tx[15:0])",
- coex_sta->high_priority_rx, coex_sta->high_priority_tx);
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
- "0x774(lp rx[31:16]/tx[15:0])",
- coex_sta->low_priority_rx, coex_sta->low_priority_tx);
- CL_PRINTF(cli_buf);
-#if (BT_AUTO_REPORT_ONLY_8192E_1ANT == 1)
- halbtc8192e1ant_monitor_bt_ctr(btcoexist);
-#endif
-
- btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
-}
-
-void ex_halbtc8192e1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type)
-{
- if (btcoexist->manual_control || btcoexist->stop_coex_dm)
- return;
-
- if (BTC_IPS_ENTER == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], IPS ENTER notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_ips = true;
-
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
- halbtc8192e1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false,
- true);
- } else if (BTC_IPS_LEAVE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], IPS LEAVE notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_ips = false;
-
- halbtc8192e1ant_init_hw_config(btcoexist, false);
- halbtc8192e1ant_init_coex_dm(btcoexist);
- halbtc8192e1ant_query_bt_info(btcoexist);
- }
-}
-
-void ex_halbtc8192e1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type)
-{
- if (btcoexist->manual_control || btcoexist->stop_coex_dm)
- return;
-
- if (BTC_LPS_ENABLE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], LPS ENABLE notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_lps = true;
- } else if (BTC_LPS_DISABLE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], LPS DISABLE notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_lps = false;
- }
-}
-
-void ex_halbtc8192e1ant_scan_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- boolean wifi_connected = false, bt_hs_on = false;
- u32 wifi_link_status = 0;
- u32 num_of_wifi_link = 0;
- boolean bt_ctrl_agg_buf_size = false;
- u8 agg_buf_size = 5;
-
- u8 u8tmpa, u8tmpb;
- u32 u32tmp;
-
- if (btcoexist->manual_control ||
- btcoexist->stop_coex_dm)
- return;
-
- if (BTC_SCAN_START == type) {
- coex_sta->wifi_is_high_pri_task = true;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCAN START notify\n");
- BTC_TRACE(trace_buf);
-
- halbtc8192e1ant_ps_tdma(btcoexist, FORCE_EXEC, false,
- 8); /* Force antenna setup for no scan result issue */
- u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x948);
- u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765);
- u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x67);
-
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x\n",
- u32tmp, u8tmpa, u8tmpb);
- BTC_TRACE(trace_buf);
- } else {
- coex_sta->wifi_is_high_pri_task = false;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCAN FINISH notify\n");
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
- &coex_sta->scan_ap_num);
- }
-
- if (coex_sta->bt_disabled)
- return;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
-
- halbtc8192e1ant_query_bt_info(btcoexist);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
- num_of_wifi_link = wifi_link_status >> 16;
- if (num_of_wifi_link >= 2) {
- halbtc8192e1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
- halbtc8192e1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
- bt_ctrl_agg_buf_size, agg_buf_size);
- halbtc8192e1ant_action_wifi_multi_port(btcoexist);
- return;
- }
-
- if (coex_sta->c2h_bt_inquiry_page) {
- halbtc8192e1ant_action_bt_inquiry(btcoexist);
- return;
- } else if (bt_hs_on) {
- halbtc8192e1ant_action_hs(btcoexist);
- return;
- }
-
- if (BTC_SCAN_START == type) {
- if (!wifi_connected) /* non-connected scan */
- halbtc8192e1ant_action_wifi_not_connected_scan(
- btcoexist);
- else /* wifi is connected */
- halbtc8192e1ant_action_wifi_connected_scan(btcoexist);
- } else if (BTC_SCAN_FINISH == type) {
- if (!wifi_connected) /* non-connected scan */
- halbtc8192e1ant_action_wifi_not_connected(btcoexist);
- else
- halbtc8192e1ant_action_wifi_connected(btcoexist);
- }
-}
-
-void ex_halbtc8192e1ant_connect_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- boolean wifi_connected = false, bt_hs_on = false;
- u32 wifi_link_status = 0;
- u32 num_of_wifi_link = 0;
- boolean bt_ctrl_agg_buf_size = false;
- u8 agg_buf_size = 5;
-
- if (btcoexist->manual_control ||
- btcoexist->stop_coex_dm ||
- coex_sta->bt_disabled)
- return;
-
- if (BTC_ASSOCIATE_START == type) {
- coex_sta->wifi_is_high_pri_task = true;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CONNECT START notify\n");
- BTC_TRACE(trace_buf);
- coex_dm->arp_cnt = 0;
- } else {
- coex_sta->wifi_is_high_pri_task = false;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CONNECT FINISH notify\n");
- BTC_TRACE(trace_buf);
- /* coex_dm->arp_cnt = 0; */
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
- num_of_wifi_link = wifi_link_status >> 16;
- if (num_of_wifi_link >= 2) {
- halbtc8192e1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
- halbtc8192e1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
- bt_ctrl_agg_buf_size, agg_buf_size);
- halbtc8192e1ant_action_wifi_multi_port(btcoexist);
- return;
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- if (coex_sta->c2h_bt_inquiry_page) {
- halbtc8192e1ant_action_bt_inquiry(btcoexist);
- return;
- } else if (bt_hs_on) {
- halbtc8192e1ant_action_hs(btcoexist);
- return;
- }
-
- if (BTC_ASSOCIATE_START == type)
- halbtc8192e1ant_action_wifi_not_connected_asso_auth(btcoexist);
- else if (BTC_ASSOCIATE_FINISH == type) {
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- if (!wifi_connected) /* non-connected scan */
- halbtc8192e1ant_action_wifi_not_connected(btcoexist);
- else
- halbtc8192e1ant_action_wifi_connected(btcoexist);
- }
-}
-
-void ex_halbtc8192e1ant_media_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- u8 h2c_parameter[3] = {0};
- u32 wifi_bw;
- u8 wifi_central_chnl;
- boolean wifi_under_b_mode = false;
-
- if (btcoexist->manual_control ||
- btcoexist->stop_coex_dm ||
- coex_sta->bt_disabled)
- return;
-
- if (BTC_MEDIA_CONNECT == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], MEDIA connect notify\n");
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
- &wifi_under_b_mode);
-
- /* Set CCK Tx/Rx high Pri except 11b mode */
- if (wifi_under_b_mode) {
- btcoexist->btc_write_1byte(btcoexist, 0x6cd,
- 0x00); /* CCK Tx */
- btcoexist->btc_write_1byte(btcoexist, 0x6cf,
- 0x00); /* CCK Rx */
- } else {
- btcoexist->btc_write_1byte(btcoexist, 0x6cd,
- 0x10); /* CCK Tx */
- btcoexist->btc_write_1byte(btcoexist, 0x6cf,
- 0x10); /* CCK Rx */
- }
-
- coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist,
- 0x430);
- coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist,
- 0x434);
- coex_dm->backup_retry_limit = btcoexist->btc_read_2byte(
- btcoexist, 0x42a);
- coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte(
- btcoexist, 0x456);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], MEDIA disconnect notify\n");
- BTC_TRACE(trace_buf);
- coex_dm->arp_cnt = 0;
-
- btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */
- btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */
- }
-
- /* only 2.4G we need to inform bt the chnl mask */
- btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
- &wifi_central_chnl);
- if ((BTC_MEDIA_CONNECT == type) &&
- (wifi_central_chnl <= 14)) {
- /* h2c_parameter[0] = 0x1; */
- h2c_parameter[0] = 0x0;
- h2c_parameter[1] = wifi_central_chnl;
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- if (BTC_WIFI_BW_HT40 == wifi_bw)
- h2c_parameter[2] = 0x30;
- else
- h2c_parameter[2] = 0x20;
- }
-
- coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
- coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
- coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
-
- btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter);
-}
-
-void ex_halbtc8192e1ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- boolean bt_hs_on = false;
- u32 wifi_link_status = 0;
- u32 num_of_wifi_link = 0;
- boolean bt_ctrl_agg_buf_size = false;
- u8 agg_buf_size = 5;
-
- if (btcoexist->manual_control ||
- btcoexist->stop_coex_dm ||
- coex_sta->bt_disabled)
- return;
-
- if (BTC_PACKET_DHCP == type ||
- BTC_PACKET_EAPOL == type ||
- BTC_PACKET_ARP == type) {
- if (BTC_PACKET_ARP == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], specific Packet ARP notify\n");
- BTC_TRACE(trace_buf);
-
- coex_dm->arp_cnt++;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ARP Packet Count = %d\n",
- coex_dm->arp_cnt);
- BTC_TRACE(trace_buf);
-
- if (coex_dm->arp_cnt >=
- 10) /* if APR PKT > 10 after connect, do not go to ActionWifiConnectedSpecificPacket(btcoexist) */
- coex_sta->wifi_is_high_pri_task = false;
- else
- coex_sta->wifi_is_high_pri_task = true;
- } else {
- coex_sta->wifi_is_high_pri_task = true;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], specific Packet DHCP or EAPOL notify\n");
- BTC_TRACE(trace_buf);
- }
- } else {
- coex_sta->wifi_is_high_pri_task = false;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], specific Packet [Type = %d] notify\n", type);
- BTC_TRACE(trace_buf);
- }
-
- coex_sta->specific_pkt_period_cnt = 0;
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
- num_of_wifi_link = wifi_link_status >> 16;
- if (num_of_wifi_link >= 2) {
- halbtc8192e1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
- halbtc8192e1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
- bt_ctrl_agg_buf_size, agg_buf_size);
- halbtc8192e1ant_action_wifi_multi_port(btcoexist);
- return;
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- if (coex_sta->c2h_bt_inquiry_page) {
- halbtc8192e1ant_action_bt_inquiry(btcoexist);
- return;
- } else if (bt_hs_on) {
- halbtc8192e1ant_action_hs(btcoexist);
- return;
- }
-
- if (BTC_PACKET_DHCP == type ||
- BTC_PACKET_EAPOL == type ||
- ((BTC_PACKET_ARP == type) && (coex_sta->wifi_is_high_pri_task)))
- halbtc8192e1ant_action_wifi_connected_specific_packet(btcoexist);
-}
-
-void ex_halbtc8192e1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
- IN u8 *tmp_buf, IN u8 length)
-{
- u8 bt_info = 0;
- u8 i, rsp_source = 0;
- boolean wifi_connected = false;
- boolean bt_busy = false;
-
- coex_sta->c2h_bt_info_req_sent = false;
-
- rsp_source = tmp_buf[0] & 0xf;
- if (rsp_source >= BT_INFO_SRC_8192E_1ANT_MAX)
- rsp_source = BT_INFO_SRC_8192E_1ANT_WIFI_FW;
- coex_sta->bt_info_c2h_cnt[rsp_source]++;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source,
- length);
- BTC_TRACE(trace_buf);
- for (i = 0; i < length; i++) {
- coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
- if (i == 1)
- bt_info = tmp_buf[i];
- if (i == length - 1) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n",
- tmp_buf[i]);
- BTC_TRACE(trace_buf);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ",
- tmp_buf[i]);
- BTC_TRACE(trace_buf);
- }
- }
-
- if (BT_INFO_SRC_8192E_1ANT_WIFI_FW != rsp_source) {
- coex_sta->bt_retry_cnt = /* [3:0] */
- coex_sta->bt_info_c2h[rsp_source][2] & 0xf;
-
- if (coex_sta->bt_retry_cnt >= 1)
- coex_sta->pop_event_cnt++;
-
- if (coex_sta->bt_info_c2h[rsp_source][2] & 0x20)
- coex_sta->c2h_bt_page = true;
- else
- coex_sta->c2h_bt_page = false;
-
- coex_sta->bt_rssi =
- coex_sta->bt_info_c2h[rsp_source][3] * 2 - 90;
- /* coex_sta->bt_info_c2h[rsp_source][3]*2+10; */
-
- coex_sta->bt_info_ext =
- coex_sta->bt_info_c2h[rsp_source][4];
-
- coex_sta->bt_tx_rx_mask = (coex_sta->bt_info_c2h[rsp_source][2]
- & 0x40);
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TX_RX_MASK,
- &coex_sta->bt_tx_rx_mask);
- if (!coex_sta->bt_tx_rx_mask) {
- /* BT into is responded by BT FW and BT RF REG 0x3C != 0x15 => Need to switch BT TRx Mask */
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x15\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF,
- 0x3c, 0x15);
- }
-
- /* Here we need to resend some wifi info to BT */
- /* because bt is reset and loss of the info. */
- if (coex_sta->bt_info_ext & BIT(1)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- if (wifi_connected)
- ex_halbtc8192e1ant_media_status_notify(
- btcoexist, BTC_MEDIA_CONNECT);
- else
- ex_halbtc8192e1ant_media_status_notify(
- btcoexist, BTC_MEDIA_DISCONNECT);
- }
-
- if (coex_sta->bt_info_ext & BIT(3)) {
- if (!btcoexist->manual_control &&
- !btcoexist->stop_coex_dm) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n");
- BTC_TRACE(trace_buf);
- halbtc8192e1ant_ignore_wlan_act(btcoexist,
- FORCE_EXEC, false);
- }
- } else {
- /* BT already NOT ignore Wlan active, do nothing here. */
- }
-#if (BT_AUTO_REPORT_ONLY_8192E_1ANT == 0)
- if ((coex_sta->bt_info_ext & BIT(4))) {
- /* BT auto report already enabled, do nothing */
- } else
- halbtc8192e1ant_bt_auto_report(btcoexist, FORCE_EXEC,
- true);
-#endif
- }
-
- /* check BIT2 first ==> check if bt is under inquiry or page scan */
- if (bt_info & BT_INFO_8192E_1ANT_B_INQ_PAGE)
- coex_sta->c2h_bt_inquiry_page = true;
- else
- coex_sta->c2h_bt_inquiry_page = false;
-
- /* set link exist status */
- if (!(bt_info & BT_INFO_8192E_1ANT_B_CONNECTION)) {
- coex_sta->bt_link_exist = false;
- coex_sta->pan_exist = false;
- coex_sta->a2dp_exist = false;
- coex_sta->hid_exist = false;
- coex_sta->sco_exist = false;
- } else { /* connection exists */
- coex_sta->bt_link_exist = true;
- if (bt_info & BT_INFO_8192E_1ANT_B_FTP)
- coex_sta->pan_exist = true;
- else
- coex_sta->pan_exist = false;
- if (bt_info & BT_INFO_8192E_1ANT_B_A2DP)
- coex_sta->a2dp_exist = true;
- else
- coex_sta->a2dp_exist = false;
- if (bt_info & BT_INFO_8192E_1ANT_B_HID)
- coex_sta->hid_exist = true;
- else
- coex_sta->hid_exist = false;
- if (bt_info & BT_INFO_8192E_1ANT_B_SCO_ESCO)
- coex_sta->sco_exist = true;
- else
- coex_sta->sco_exist = false;
- }
-
- halbtc8192e1ant_update_bt_link_info(btcoexist);
-
- bt_info = bt_info &
- 0x1f; /* mask profile bit for connect-ilde identification ( for CSR case: A2DP idle --> 0x41) */
-
- if (!(bt_info & BT_INFO_8192E_1ANT_B_CONNECTION)) {
- coex_dm->bt_status = BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n");
- BTC_TRACE(trace_buf);
- } else if (bt_info ==
- BT_INFO_8192E_1ANT_B_CONNECTION) { /* connection exists but no busy */
- coex_dm->bt_status = BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n");
- BTC_TRACE(trace_buf);
- } else if ((bt_info & BT_INFO_8192E_1ANT_B_SCO_ESCO) ||
- (bt_info & BT_INFO_8192E_1ANT_B_SCO_BUSY)) {
- coex_dm->bt_status = BT_8192E_1ANT_BT_STATUS_SCO_BUSY;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n");
- BTC_TRACE(trace_buf);
- } else if (bt_info & BT_INFO_8192E_1ANT_B_ACL_BUSY) {
- if (BT_8192E_1ANT_BT_STATUS_ACL_BUSY != coex_dm->bt_status)
- coex_dm->auto_tdma_adjust = false;
- coex_dm->bt_status = BT_8192E_1ANT_BT_STATUS_ACL_BUSY;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n");
- BTC_TRACE(trace_buf);
- } else {
- coex_dm->bt_status = BT_8192E_1ANT_BT_STATUS_MAX;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n");
- BTC_TRACE(trace_buf);
- }
-
- if ((BT_8192E_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
- (BT_8192E_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
- (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status))
- bt_busy = true;
- else
- bt_busy = false;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
-
- halbtc8192e1ant_run_coexist_mechanism(btcoexist);
-}
-
-void ex_halbtc8192e1ant_rf_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- u32 u32tmp;
- u8 u8tmpa, u8tmpb, u8tmpc;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n");
- BTC_TRACE(trace_buf);
-
- if (BTC_RF_ON == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RF is turned ON!!\n");
- BTC_TRACE(trace_buf);
- btcoexist->stop_coex_dm = false;
- } else if (BTC_RF_OFF == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RF is turned OFF!!\n");
- BTC_TRACE(trace_buf);
-
- halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- halbtc8192e1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
- halbtc8192e1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false,
- true);
-
- halbtc8192e1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
- btcoexist->stop_coex_dm = true;
-
- u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x948);
- u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765);
- u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x67);
- u8tmpc = btcoexist->btc_read_1byte(btcoexist, 0x76e);
-
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x, 0x76e=0x%x\n",
- u32tmp, u8tmpa, u8tmpb, u8tmpc);
- BTC_TRACE(trace_buf);
-
- }
-}
-
-void ex_halbtc8192e1ant_halt_notify(IN struct btc_coexist *btcoexist)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n");
- BTC_TRACE(trace_buf);
-
- halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
- halbtc8192e1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
- halbtc8192e1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false, true);
-
- halbtc8192e1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
-
- ex_halbtc8192e1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
-
- btcoexist->stop_coex_dm = true;
-}
-
-void ex_halbtc8192e1ant_pnp_notify(IN struct btc_coexist *btcoexist,
- IN u8 pnp_state)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n");
- BTC_TRACE(trace_buf);
-
- if (BTC_WIFI_PNP_SLEEP == pnp_state) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Pnp notify to SLEEP\n");
- BTC_TRACE(trace_buf);
-
- halbtc8192e1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- halbtc8192e1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
- halbtc8192e1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false,
- true);
-
- /* Sinda 20150819, workaround for driver skip leave IPS/LPS to speed up sleep time. */
- /* Driver do not leave IPS/LPS when driver is going to sleep, so BTCoexistence think wifi is still under IPS/LPS */
- /* BT should clear UnderIPS/UnderLPS state to avoid mismatch state after wakeup. */
- coex_sta->under_ips = false;
- coex_sta->under_lps = false;
- btcoexist->stop_coex_dm = true;
- } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Pnp notify to WAKE UP\n");
- BTC_TRACE(trace_buf);
- btcoexist->stop_coex_dm = false;
- halbtc8192e1ant_init_hw_config(btcoexist, false);
- halbtc8192e1ant_init_coex_dm(btcoexist);
- halbtc8192e1ant_query_bt_info(btcoexist);
- }
-}
-
-void ex_halbtc8192e1ant_coex_dm_reset(IN struct btc_coexist *btcoexist)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], *****************Coex DM Reset*****************\n");
- BTC_TRACE(trace_buf);
-
- halbtc8192e1ant_init_hw_config(btcoexist, false);
- /* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); */
- /* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x2, 0xfffff, 0x0); */
- halbtc8192e1ant_init_coex_dm(btcoexist);
-}
-
-void ex_halbtc8192e1ant_periodical(IN struct btc_coexist *btcoexist)
-{
-#if (BT_AUTO_REPORT_ONLY_8192E_1ANT == 0)
- halbtc8192e1ant_query_bt_info(btcoexist);
- halbtc8192e1ant_monitor_bt_enable_disable(btcoexist);
-#else
- halbtc8192e1ant_monitor_bt_ctr(btcoexist);
- halbtc8192e1ant_monitor_wifi_ctr(btcoexist);
-
- if (halbtc8192e1ant_is_wifi_status_changed(btcoexist) ||
- coex_dm->auto_tdma_adjust)
-
- halbtc8192e1ant_run_coexist_mechanism(btcoexist);
-
- coex_sta->specific_pkt_period_cnt++;
-#endif
-}
-
-
-void ex_halbtc8192e1ant_dbg_control(IN struct btc_coexist *btcoexist,
- IN u8 op_code, IN u8 op_len, IN u8 *pdata)
-{
- switch (op_code) {
- case BTC_DBG_SET_COEX_NORMAL:
- btcoexist->manual_control = false;
- halbtc8192e1ant_init_coex_dm(btcoexist);
- break;
- case BTC_DBG_SET_COEX_WIFI_ONLY:
- btcoexist->manual_control = true;
- halbtc8192e1ant_power_save_state(btcoexist,
- BTC_PS_WIFI_NATIVE, 0x0, 0x0);
- halbtc8192e1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 9);
- break;
- case BTC_DBG_SET_COEX_BT_ONLY:
- /* todo */
- break;
- default:
- break;
- }
-}
-
-#endif /* #if (RTL8192E_SUPPORT == 1) */
-
-#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */
\ No newline at end of file
diff --git a/hal/btc/HalBtc8192e1Ant.h b/hal/btc/HalBtc8192e1Ant.h
deleted file mode 100644
index e75127c..0000000
--- a/hal/btc/HalBtc8192e1Ant.h
+++ /dev/null
@@ -1,226 +0,0 @@
-
-#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
-
-#if (RTL8192E_SUPPORT == 1)
-
-/* *******************************************
- * The following is for 8192E 1ANT BT Co-exist definition
- * ******************************************* */
-#define BT_AUTO_REPORT_ONLY_8192E_1ANT 1
-
-#define BT_INFO_8192E_1ANT_B_FTP BIT(7)
-#define BT_INFO_8192E_1ANT_B_A2DP BIT(6)
-#define BT_INFO_8192E_1ANT_B_HID BIT(5)
-#define BT_INFO_8192E_1ANT_B_SCO_BUSY BIT(4)
-#define BT_INFO_8192E_1ANT_B_ACL_BUSY BIT(3)
-#define BT_INFO_8192E_1ANT_B_INQ_PAGE BIT(2)
-#define BT_INFO_8192E_1ANT_B_SCO_ESCO BIT(1)
-#define BT_INFO_8192E_1ANT_B_CONNECTION BIT(0)
-
-#define BT_INFO_8192E_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \
- (((_BT_INFO_EXT_&BIT(0))) ? true : false)
-
-#define BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT 2
-
-#define BT_8192E_1ANT_WIFI_NOISY_THRESH 30 /* max: 255 */
-
-enum bt_info_src_8192e_1ant {
- BT_INFO_SRC_8192E_1ANT_WIFI_FW = 0x0,
- BT_INFO_SRC_8192E_1ANT_BT_RSP = 0x1,
- BT_INFO_SRC_8192E_1ANT_BT_ACTIVE_SEND = 0x2,
- BT_INFO_SRC_8192E_1ANT_MAX
-};
-
-enum bt_8192e_1ant_bt_status {
- BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
- BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
- BT_8192E_1ANT_BT_STATUS_INQ_PAGE = 0x2,
- BT_8192E_1ANT_BT_STATUS_ACL_BUSY = 0x3,
- BT_8192E_1ANT_BT_STATUS_SCO_BUSY = 0x4,
- BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
- BT_8192E_1ANT_BT_STATUS_MAX
-};
-
-enum bt_8192e_1ant_wifi_status {
- BT_8192E_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0,
- BT_8192E_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1,
- BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2,
- BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT = 0x3,
- BT_8192E_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4,
- BT_8192E_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5,
- BT_8192E_1ANT_WIFI_STATUS_MAX
-};
-
-enum bt_8192e_1ant_coex_algo {
- BT_8192E_1ANT_COEX_ALGO_UNDEFINED = 0x0,
- BT_8192E_1ANT_COEX_ALGO_SCO = 0x1,
- BT_8192E_1ANT_COEX_ALGO_HID = 0x2,
- BT_8192E_1ANT_COEX_ALGO_A2DP = 0x3,
- BT_8192E_1ANT_COEX_ALGO_A2DP_PANHS = 0x4,
- BT_8192E_1ANT_COEX_ALGO_PANEDR = 0x5,
- BT_8192E_1ANT_COEX_ALGO_PANHS = 0x6,
- BT_8192E_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
- BT_8192E_1ANT_COEX_ALGO_PANEDR_HID = 0x8,
- BT_8192E_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
- BT_8192E_1ANT_COEX_ALGO_HID_A2DP = 0xa,
- BT_8192E_1ANT_COEX_ALGO_MAX = 0xb,
-};
-
-struct coex_dm_8192e_1ant {
- /* fw mechanism */
- boolean cur_ignore_wlan_act;
- boolean pre_ignore_wlan_act;
- u8 pre_ps_tdma;
- u8 cur_ps_tdma;
- u8 ps_tdma_para[5];
- u8 ps_tdma_du_adj_type;
- boolean auto_tdma_adjust;
- boolean pre_ps_tdma_on;
- boolean cur_ps_tdma_on;
- boolean pre_bt_auto_report;
- boolean cur_bt_auto_report;
- u8 pre_lps;
- u8 cur_lps;
- u8 pre_rpwm;
- u8 cur_rpwm;
-
- /* sw mechanism */
- boolean pre_low_penalty_ra;
- boolean cur_low_penalty_ra;
- u32 pre_val0x6c0;
- u32 cur_val0x6c0;
- u32 pre_val0x6c4;
- u32 cur_val0x6c4;
- u32 pre_val0x6c8;
- u32 cur_val0x6c8;
- u8 pre_val0x6cc;
- u8 cur_val0x6cc;
- boolean limited_dig;
-
- u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */
- u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */
- u16 backup_retry_limit;
- u8 backup_ampdu_max_time;
-
- /* algorithm related */
- u8 pre_algorithm;
- u8 cur_algorithm;
- u8 bt_status;
- u8 wifi_chnl_info[3];
-
- u32 pre_ra_mask;
- u32 cur_ra_mask;
- u8 pre_arfr_type;
- u8 cur_arfr_type;
- u8 pre_retry_limit_type;
- u8 cur_retry_limit_type;
- u8 pre_ampdu_time_type;
- u8 cur_ampdu_time_type;
- u32 arp_cnt;
-
- u8 error_condition;
-};
-
-struct coex_sta_8192e_1ant {
- boolean bt_disabled;
- boolean bt_link_exist;
- boolean sco_exist;
- boolean a2dp_exist;
- boolean hid_exist;
- boolean pan_exist;
-
- boolean under_lps;
- boolean under_ips;
- u32 specific_pkt_period_cnt;
- u32 high_priority_tx;
- u32 high_priority_rx;
- u32 low_priority_tx;
- u32 low_priority_rx;
- s8 bt_rssi;
- boolean bt_tx_rx_mask;
- u8 pre_bt_rssi_state;
- u8 pre_wifi_rssi_state[4];
- boolean c2h_bt_info_req_sent;
- u8 bt_info_c2h[BT_INFO_SRC_8192E_1ANT_MAX][10];
- u32 bt_info_c2h_cnt[BT_INFO_SRC_8192E_1ANT_MAX];
- boolean c2h_bt_inquiry_page;
- boolean c2h_bt_page; /* Add for win8.1 page out issue */
- boolean wifi_is_high_pri_task; /* Add for win8.1 page out issue */
- u8 bt_retry_cnt;
- u8 bt_info_ext;
- u32 pop_event_cnt;
- u8 scan_ap_num;
-
- u32 crc_ok_cck;
- u32 crc_ok_11g;
- u32 crc_ok_11n;
- u32 crc_ok_11n_agg;
-
- u32 crc_err_cck;
- u32 crc_err_11g;
- u32 crc_err_11n;
- u32 crc_err_11n_agg;
-
- boolean cck_lock;
- boolean pre_ccklock;
- u8 coex_table_type;
-
- boolean force_lps_on;
-};
-
-/* *******************************************
- * The following is interface which will notify coex module.
- * ******************************************* */
-void ex_halbtc8192e1ant_power_on_setting(IN struct btc_coexist *btcoexist);
-void ex_halbtc8192e1ant_pre_load_firmware(IN struct btc_coexist *btcoexist);
-void ex_halbtc8192e1ant_init_hw_config(IN struct btc_coexist *btcoexist,
- IN boolean wifi_only);
-void ex_halbtc8192e1ant_init_coex_dm(IN struct btc_coexist *btcoexist);
-void ex_halbtc8192e1ant_ips_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8192e1ant_lps_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8192e1ant_scan_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8192e1ant_connect_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8192e1ant_media_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8192e1ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8192e1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
- IN u8 *tmp_buf, IN u8 length);
-void ex_halbtc8192e1ant_rf_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8192e1ant_halt_notify(IN struct btc_coexist *btcoexist);
-void ex_halbtc8192e1ant_pnp_notify(IN struct btc_coexist *btcoexist,
- IN u8 pnp_state);
-void ex_halbtc8192e1ant_coex_dm_reset(IN struct btc_coexist *btcoexist);
-void ex_halbtc8192e1ant_periodical(IN struct btc_coexist *btcoexist);
-void ex_halbtc8192e1ant_display_coex_info(IN struct btc_coexist *btcoexist);
-void ex_halbtc8192e1ant_dbg_control(IN struct btc_coexist *btcoexist,
- IN u8 op_code, IN u8 op_len, IN u8 *pdata);
-
-#else /* #if (RTL8192E_SUPPORT == 1) */
-#define ex_halbtc8192e1ant_power_on_setting(btcoexist)
-#define ex_halbtc8192e1ant_pre_load_firmware(btcoexist)
-#define ex_halbtc8192e1ant_init_hw_config(btcoexist, wifi_only)
-#define ex_halbtc8192e1ant_init_coex_dm(btcoexist)
-#define ex_halbtc8192e1ant_ips_notify(btcoexist, type)
-#define ex_halbtc8192e1ant_lps_notify(btcoexist, type)
-#define ex_halbtc8192e1ant_scan_notify(btcoexist, type)
-#define ex_halbtc8192e1ant_connect_notify(btcoexist, type)
-#define ex_halbtc8192e1ant_media_status_notify(btcoexist, type)
-#define ex_halbtc8192e1ant_specific_packet_notify(btcoexist, type)
-#define ex_halbtc8192e1ant_bt_info_notify(btcoexist, tmp_buf, length)
-#define ex_halbtc8192e1ant_rf_status_notify(btcoexist, type)
-#define ex_halbtc8192e1ant_halt_notify(btcoexist)
-#define ex_halbtc8192e1ant_pnp_notify(btcoexist, pnp_state)
-#define ex_halbtc8192e1ant_coex_dm_reset(btcoexist)
-#define ex_halbtc8192e1ant_periodical(btcoexist)
-#define ex_halbtc8192e1ant_display_coex_info(btcoexist)
-#define ex_halbtc8192e1ant_dbg_control(btcoexist, op_code, op_len, pdata)
-
-#endif
-
-#endif
diff --git a/hal/btc/HalBtc8192e2Ant.c b/hal/btc/HalBtc8192e2Ant.c
deleted file mode 100644
index 76e0e93..0000000
--- a/hal/btc/HalBtc8192e2Ant.c
+++ /dev/null
@@ -1,3949 +0,0 @@
-/* ************************************************************
- * Description:
- *
- * This file is for RTL8192E Co-exist mechanism
- *
- * History
- * 2012/11/15 Cosa first check in.
- *
- * ************************************************************ */
-
-/* ************************************************************
- * include files
- * ************************************************************ */
-#include "Mp_Precomp.h"
-
-
-#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
-
-#if (RTL8192E_SUPPORT == 1)
-/* ************************************************************
- * Global variables, these are static variables
- * ************************************************************ */
-static u8 *trace_buf = &gl_btc_trace_buf[0];
-static struct coex_dm_8192e_2ant glcoex_dm_8192e_2ant;
-static struct coex_dm_8192e_2ant *coex_dm = &glcoex_dm_8192e_2ant;
-static struct coex_sta_8192e_2ant glcoex_sta_8192e_2ant;
-static struct coex_sta_8192e_2ant *coex_sta = &glcoex_sta_8192e_2ant;
-
-const char *const glbt_info_src_8192e_2ant[] = {
- "BT Info[wifi fw]",
- "BT Info[bt rsp]",
- "BT Info[bt auto report]",
-};
-
-u32 glcoex_ver_date_8192e_2ant = 20130912;
-u32 glcoex_ver_8192e_2ant = 0x35;
-
-/* ************************************************************
- * local function proto type if needed
- * ************************************************************
- * ************************************************************
- * local function start with halbtc8192e2ant_
- * ************************************************************ */
-u8 halbtc8192e2ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1)
-{
- s32 bt_rssi = 0;
- u8 bt_rssi_state = coex_sta->pre_bt_rssi_state;
-
- bt_rssi = coex_sta->bt_rssi;
-
- if (level_num == 2) {
- if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
- (coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (bt_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT))
- bt_rssi_state = BTC_RSSI_STATE_HIGH;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else {
- if (bt_rssi < rssi_thresh)
- bt_rssi_state = BTC_RSSI_STATE_LOW;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- } else if (level_num == 3) {
- if (rssi_thresh > rssi_thresh1) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Rssi thresh error!!\n");
- BTC_TRACE(trace_buf);
- return coex_sta->pre_bt_rssi_state;
- }
-
- if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
- (coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (bt_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT))
- bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else if ((coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_MEDIUM) ||
- (coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_STAY_MEDIUM)) {
- if (bt_rssi >= (rssi_thresh1 +
- BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT))
- bt_rssi_state = BTC_RSSI_STATE_HIGH;
- else if (bt_rssi < rssi_thresh)
- bt_rssi_state = BTC_RSSI_STATE_LOW;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
- } else {
- if (bt_rssi < rssi_thresh1)
- bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- }
-
- coex_sta->pre_bt_rssi_state = bt_rssi_state;
-
- return bt_rssi_state;
-}
-
-u8 halbtc8192e2ant_wifi_rssi_state(IN struct btc_coexist *btcoexist,
- IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1)
-{
- s32 wifi_rssi = 0;
- u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index];
-
- btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
-
- if (level_num == 2) {
- if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
- ||
- (coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (wifi_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT))
- wifi_rssi_state = BTC_RSSI_STATE_HIGH;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else {
- if (wifi_rssi < rssi_thresh)
- wifi_rssi_state = BTC_RSSI_STATE_LOW;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- } else if (level_num == 3) {
- if (rssi_thresh > rssi_thresh1) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], wifi RSSI thresh error!!\n");
- BTC_TRACE(trace_buf);
- return coex_sta->pre_wifi_rssi_state[index];
- }
-
- if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
- ||
- (coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (wifi_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT))
- wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else if ((coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_MEDIUM) ||
- (coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_STAY_MEDIUM)) {
- if (wifi_rssi >= (rssi_thresh1 +
- BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT))
- wifi_rssi_state = BTC_RSSI_STATE_HIGH;
- else if (wifi_rssi < rssi_thresh)
- wifi_rssi_state = BTC_RSSI_STATE_LOW;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
- } else {
- if (wifi_rssi < rssi_thresh1)
- wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- }
-
- coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state;
-
- return wifi_rssi_state;
-}
-
-void halbtc8192e2ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist)
-{
- static u32 bt_disable_cnt = 0;
- boolean bt_active = true, bt_disabled = false;
-
- /* This function check if bt is disabled */
-
- if (coex_sta->high_priority_tx == 0 &&
- coex_sta->high_priority_rx == 0 &&
- coex_sta->low_priority_tx == 0 &&
- coex_sta->low_priority_rx == 0)
- bt_active = false;
- if (coex_sta->high_priority_tx == 0xffff &&
- coex_sta->high_priority_rx == 0xffff &&
- coex_sta->low_priority_tx == 0xffff &&
- coex_sta->low_priority_rx == 0xffff)
- bt_active = false;
- if (bt_active) {
- bt_disable_cnt = 0;
- bt_disabled = false;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
- &bt_disabled);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is enabled !!\n");
- BTC_TRACE(trace_buf);
- } else {
- bt_disable_cnt++;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], bt all counters=0, %d times!!\n",
- bt_disable_cnt);
- BTC_TRACE(trace_buf);
- if (bt_disable_cnt >= 2) {
- bt_disabled = true;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
- &bt_disabled);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is disabled !!\n");
- BTC_TRACE(trace_buf);
- }
- }
- if (coex_sta->bt_disabled != bt_disabled) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is from %s to %s!!\n",
- (coex_sta->bt_disabled ? "disabled" : "enabled"),
- (bt_disabled ? "disabled" : "enabled"));
- BTC_TRACE(trace_buf);
- coex_sta->bt_disabled = bt_disabled;
- if (!bt_disabled) {
- } else {
- }
- }
-}
-
-u32 halbtc8192e2ant_decide_ra_mask(IN struct btc_coexist *btcoexist,
- IN u8 ss_type, IN u32 ra_mask_type)
-{
- u32 dis_ra_mask = 0x0;
-
- switch (ra_mask_type) {
- case 0: /* normal mode */
- if (ss_type == 2)
- dis_ra_mask = 0x0; /* enable 2ss */
- else
- dis_ra_mask = 0xfff00000; /* disable 2ss */
- break;
- case 1: /* disable cck 1/2 */
- if (ss_type == 2)
- dis_ra_mask = 0x00000003; /* enable 2ss */
- else
- dis_ra_mask = 0xfff00003; /* disable 2ss */
- break;
- case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */
- if (ss_type == 2)
- dis_ra_mask = 0x0001f1f7; /* enable 2ss */
- else
- dis_ra_mask = 0xfff1f1f7; /* disable 2ss */
- break;
- default:
- break;
- }
-
- return dis_ra_mask;
-}
-
-void halbtc8192e2ant_update_ra_mask(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u32 dis_rate_mask)
-{
- coex_dm->cur_ra_mask = dis_rate_mask;
-
- if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask))
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK,
- &coex_dm->cur_ra_mask);
- coex_dm->pre_ra_mask = coex_dm->cur_ra_mask;
-}
-
-void halbtc8192e2ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- boolean wifi_under_b_mode = false;
-
- coex_dm->cur_arfr_type = type;
-
- if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) {
- switch (coex_dm->cur_arfr_type) {
- case 0: /* normal mode */
- btcoexist->btc_write_4byte(btcoexist, 0x430,
- coex_dm->backup_arfr_cnt1);
- btcoexist->btc_write_4byte(btcoexist, 0x434,
- coex_dm->backup_arfr_cnt2);
- break;
- case 1:
- btcoexist->btc_get(btcoexist,
- BTC_GET_BL_WIFI_UNDER_B_MODE,
- &wifi_under_b_mode);
- if (wifi_under_b_mode) {
- btcoexist->btc_write_4byte(btcoexist,
- 0x430, 0x0);
- btcoexist->btc_write_4byte(btcoexist,
- 0x434, 0x01010101);
- } else {
- btcoexist->btc_write_4byte(btcoexist,
- 0x430, 0x0);
- btcoexist->btc_write_4byte(btcoexist,
- 0x434, 0x04030201);
- }
- break;
- default:
- break;
- }
- }
-
- coex_dm->pre_arfr_type = coex_dm->cur_arfr_type;
-}
-
-void halbtc8192e2ant_retry_limit(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- coex_dm->cur_retry_limit_type = type;
-
- if (force_exec ||
- (coex_dm->pre_retry_limit_type !=
- coex_dm->cur_retry_limit_type)) {
- switch (coex_dm->cur_retry_limit_type) {
- case 0: /* normal mode */
- btcoexist->btc_write_2byte(btcoexist, 0x42a,
- coex_dm->backup_retry_limit);
- break;
- case 1: /* retry limit=8 */
- btcoexist->btc_write_2byte(btcoexist, 0x42a,
- 0x0808);
- break;
- default:
- break;
- }
- }
-
- coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type;
-}
-
-void halbtc8192e2ant_ampdu_max_time(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- coex_dm->cur_ampdu_time_type = type;
-
- if (force_exec ||
- (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) {
- switch (coex_dm->cur_ampdu_time_type) {
- case 0: /* normal mode */
- btcoexist->btc_write_1byte(btcoexist, 0x456,
- coex_dm->backup_ampdu_max_time);
- break;
- case 1: /* AMPDU timw = 0x38 * 32us */
- btcoexist->btc_write_1byte(btcoexist, 0x456,
- 0x38);
- break;
- default:
- break;
- }
- }
-
- coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type;
-}
-
-void halbtc8192e2ant_limited_tx(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type,
- IN u8 retry_limit_type, IN u8 ampdu_time_type)
-{
- u32 dis_ra_mask = 0x0;
-
- coex_dm->cur_ra_mask_type = ra_mask_type;
- dis_ra_mask = halbtc8192e2ant_decide_ra_mask(btcoexist,
- coex_dm->cur_ss_type, ra_mask_type);
- halbtc8192e2ant_update_ra_mask(btcoexist, force_exec, dis_ra_mask);
-
- halbtc8192e2ant_auto_rate_fallback_retry(btcoexist, force_exec,
- arfr_type);
- halbtc8192e2ant_retry_limit(btcoexist, force_exec, retry_limit_type);
- halbtc8192e2ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type);
-}
-
-void halbtc8192e2ant_limited_rx(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean rej_ap_agg_pkt,
- IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size)
-{
- boolean reject_rx_agg = rej_ap_agg_pkt;
- boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size;
- u8 rx_agg_size = agg_buf_size;
-
- /* ============================================ */
- /* Rx Aggregation related setting */
- /* ============================================ */
- btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT,
- &reject_rx_agg);
- /* decide BT control aggregation buf size or not */
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE,
- &bt_ctrl_rx_agg_size);
- /* aggregation buf size, only work when BT control Rx aggregation size. */
- btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size);
- /* real update aggregation setting */
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
-
-
-}
-
-void halbtc8192e2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist)
-{
- u32 reg_hp_txrx, reg_lp_txrx, u32tmp;
- u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
-
- reg_hp_txrx = 0x770;
- reg_lp_txrx = 0x774;
-
- u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
- reg_hp_tx = u32tmp & MASKLWORD;
- reg_hp_rx = (u32tmp & MASKHWORD) >> 16;
-
- u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
- reg_lp_tx = u32tmp & MASKLWORD;
- reg_lp_rx = (u32tmp & MASKHWORD) >> 16;
-
- coex_sta->high_priority_tx = reg_hp_tx;
- coex_sta->high_priority_rx = reg_hp_rx;
- coex_sta->low_priority_tx = reg_lp_tx;
- coex_sta->low_priority_rx = reg_lp_rx;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], High Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n",
- reg_hp_txrx, reg_hp_tx, reg_hp_tx, reg_hp_rx, reg_hp_rx);
- BTC_TRACE(trace_buf);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Low Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n",
- reg_lp_txrx, reg_lp_tx, reg_lp_tx, reg_lp_rx, reg_lp_rx);
- BTC_TRACE(trace_buf);
-
- /* reset counter */
- btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
-}
-
-void halbtc8192e2ant_query_bt_info(IN struct btc_coexist *btcoexist)
-{
- u8 h2c_parameter[1] = {0};
-
- coex_sta->c2h_bt_info_req_sent = true;
-
- h2c_parameter[0] |= BIT(0); /* trigger */
-
- btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter);
-}
-
-boolean halbtc8192e2ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist)
-{
- static boolean pre_wifi_busy = false, pre_under_4way = false,
- pre_bt_hs_on = false;
- boolean wifi_busy = false, under_4way = false, bt_hs_on = false;
- boolean wifi_connected = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
- &under_4way);
-
- if (wifi_connected) {
- if (wifi_busy != pre_wifi_busy) {
- pre_wifi_busy = wifi_busy;
- return true;
- }
- if (under_4way != pre_under_4way) {
- pre_under_4way = under_4way;
- return true;
- }
- if (bt_hs_on != pre_bt_hs_on) {
- pre_bt_hs_on = bt_hs_on;
- return true;
- }
- }
-
- return false;
-}
-
-void halbtc8192e2ant_update_bt_link_info(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean bt_hs_on = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
-
- bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
- bt_link_info->sco_exist = coex_sta->sco_exist;
- bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
- bt_link_info->pan_exist = coex_sta->pan_exist;
- bt_link_info->hid_exist = coex_sta->hid_exist;
-
- /* work around for HS mode. */
- if (bt_hs_on) {
- bt_link_info->pan_exist = true;
- bt_link_info->bt_link_exist = true;
- }
-
- /* check if Sco only */
- if (bt_link_info->sco_exist &&
- !bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist &&
- !bt_link_info->hid_exist)
- bt_link_info->sco_only = true;
- else
- bt_link_info->sco_only = false;
-
- /* check if A2dp only */
- if (!bt_link_info->sco_exist &&
- bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist &&
- !bt_link_info->hid_exist)
- bt_link_info->a2dp_only = true;
- else
- bt_link_info->a2dp_only = false;
-
- /* check if Pan only */
- if (!bt_link_info->sco_exist &&
- !bt_link_info->a2dp_exist &&
- bt_link_info->pan_exist &&
- !bt_link_info->hid_exist)
- bt_link_info->pan_only = true;
- else
- bt_link_info->pan_only = false;
-
- /* check if Hid only */
- if (!bt_link_info->sco_exist &&
- !bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist &&
- bt_link_info->hid_exist)
- bt_link_info->hid_only = true;
- else
- bt_link_info->hid_only = false;
-}
-
-u8 halbtc8192e2ant_action_algorithm(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- struct btc_stack_info *stack_info = &btcoexist->stack_info;
- boolean bt_hs_on = false;
- u8 algorithm = BT_8192E_2ANT_COEX_ALGO_UNDEFINED;
- u8 num_of_diff_profile = 0;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
-
- if (!bt_link_info->bt_link_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], No BT link exists!!!\n");
- BTC_TRACE(trace_buf);
- return algorithm;
- }
-
- if (bt_link_info->sco_exist)
- num_of_diff_profile++;
- if (bt_link_info->hid_exist)
- num_of_diff_profile++;
- if (bt_link_info->pan_exist)
- num_of_diff_profile++;
- if (bt_link_info->a2dp_exist)
- num_of_diff_profile++;
-
- if (num_of_diff_profile == 1) {
- if (bt_link_info->sco_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO only\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8192E_2ANT_COEX_ALGO_SCO;
- } else {
- if (bt_link_info->hid_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], HID only\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8192E_2ANT_COEX_ALGO_HID;
- } else if (bt_link_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], A2DP only\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8192E_2ANT_COEX_ALGO_A2DP;
- } else if (bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], PAN(HS) only\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8192E_2ANT_COEX_ALGO_PANHS;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], PAN(EDR) only\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8192E_2ANT_COEX_ALGO_PANEDR;
- }
- }
- }
- } else if (num_of_diff_profile == 2) {
- if (bt_link_info->sco_exist) {
- if (bt_link_info->hid_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + HID\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8192E_2ANT_COEX_ALGO_SCO;
- } else if (bt_link_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + A2DP ==> SCO\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8192E_2ANT_COEX_ALGO_PANEDR_HID;
- } else if (bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8192E_2ANT_COEX_ALGO_SCO;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8192E_2ANT_COEX_ALGO_SCO_PAN;
- }
- }
- } else {
- if (bt_link_info->hid_exist &&
- bt_link_info->a2dp_exist) {
- if (stack_info->num_of_hid >= 2) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], HID*2 + A2DP\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], HID + A2DP\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8192E_2ANT_COEX_ALGO_HID_A2DP;
- }
- } else if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], HID + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8192E_2ANT_COEX_ALGO_HID;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], HID + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8192E_2ANT_COEX_ALGO_PANEDR_HID;
- }
- } else if (bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8192E_2ANT_COEX_ALGO_A2DP_PANHS;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], A2DP + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8192E_2ANT_COEX_ALGO_PANEDR_A2DP;
- }
- }
- }
- } else if (num_of_diff_profile == 3) {
- if (bt_link_info->sco_exist) {
- if (bt_link_info->hid_exist &&
- bt_link_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + HID + A2DP ==> HID\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8192E_2ANT_COEX_ALGO_PANEDR_HID;
- } else if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + HID + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8192E_2ANT_COEX_ALGO_SCO;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + HID + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8192E_2ANT_COEX_ALGO_SCO_PAN;
- }
- } else if (bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8192E_2ANT_COEX_ALGO_SCO;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8192E_2ANT_COEX_ALGO_PANEDR_HID;
- }
- }
- } else {
- if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], HID + A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8192E_2ANT_COEX_ALGO_HID_A2DP;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], HID + A2DP + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
- }
- }
- }
- } else if (num_of_diff_profile >= 3) {
- if (bt_link_info->sco_exist) {
- if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8192E_2ANT_COEX_ALGO_PANEDR_HID;
- }
- }
- }
- }
-
- return algorithm;
-}
-
-void halbtc8192e2ant_set_fw_dac_swing_level(IN struct btc_coexist *btcoexist,
- IN u8 dac_swing_lvl)
-{
- u8 h2c_parameter[1] = {0};
-
- /* There are several type of dacswing */
- /* 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */
- h2c_parameter[0] = dac_swing_lvl;
-
- btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter);
-}
-
-void halbtc8192e2ant_set_fw_dec_bt_pwr(IN struct btc_coexist *btcoexist,
- IN u8 dec_bt_pwr_lvl)
-{
- u8 h2c_parameter[1] = {0};
-
- h2c_parameter[0] = dec_bt_pwr_lvl;
-
- btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter);
-}
-
-void halbtc8192e2ant_dec_bt_pwr(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 dec_bt_pwr_lvl)
-{
- coex_dm->cur_bt_dec_pwr_lvl = dec_bt_pwr_lvl;
-
- if (!force_exec) {
-#if 0 /* work around, avoid h2c command fail. */
- if (coex_dm->pre_bt_dec_pwr_lvl == coex_dm->cur_bt_dec_pwr_lvl)
- return;
-#endif
- }
- halbtc8192e2ant_set_fw_dec_bt_pwr(btcoexist,
- coex_dm->cur_bt_dec_pwr_lvl);
-
- coex_dm->pre_bt_dec_pwr_lvl = coex_dm->cur_bt_dec_pwr_lvl;
-}
-
-void halbtc8192e2ant_set_bt_auto_report(IN struct btc_coexist *btcoexist,
- IN boolean enable_auto_report)
-{
- u8 h2c_parameter[1] = {0};
-
- h2c_parameter[0] = 0;
-
- if (enable_auto_report)
- h2c_parameter[0] |= BIT(0);
-
- btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter);
-}
-
-void halbtc8192e2ant_bt_auto_report(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean enable_auto_report)
-{
- coex_dm->cur_bt_auto_report = enable_auto_report;
-
- if (!force_exec) {
- if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report)
- return;
- }
- halbtc8192e2ant_set_bt_auto_report(btcoexist,
- coex_dm->cur_bt_auto_report);
-
- coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report;
-}
-
-void halbtc8192e2ant_fw_dac_swing_lvl(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 fw_dac_swing_lvl)
-{
- coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl;
-
- if (!force_exec) {
- if (coex_dm->pre_fw_dac_swing_lvl ==
- coex_dm->cur_fw_dac_swing_lvl)
- return;
- }
-
- halbtc8192e2ant_set_fw_dac_swing_level(btcoexist,
- coex_dm->cur_fw_dac_swing_lvl);
-
- coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl;
-}
-
-void halbtc8192e2ant_set_sw_rf_rx_lpf_corner(IN struct btc_coexist *btcoexist,
- IN boolean rx_rf_shrink_on)
-{
- if (rx_rf_shrink_on) {
- /* Shrink RF Rx LPF corner */
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Shrink RF Rx LPF corner!!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, 0xfffff,
- 0xffffc);
- } else {
- /* Resume RF Rx LPF corner */
- /* After initialized, we can use coex_dm->bt_rf_0x1e_backup */
- if (btcoexist->initilized) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Resume RF Rx LPF corner!!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e,
- 0xfffff, coex_dm->bt_rf_0x1e_backup);
- }
- }
-}
-
-void halbtc8192e2ant_rf_shrink(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean rx_rf_shrink_on)
-{
- coex_dm->cur_rf_rx_lpf_shrink = rx_rf_shrink_on;
-
- if (!force_exec) {
- if (coex_dm->pre_rf_rx_lpf_shrink ==
- coex_dm->cur_rf_rx_lpf_shrink)
- return;
- }
- halbtc8192e2ant_set_sw_rf_rx_lpf_corner(btcoexist,
- coex_dm->cur_rf_rx_lpf_shrink);
-
- coex_dm->pre_rf_rx_lpf_shrink = coex_dm->cur_rf_rx_lpf_shrink;
-}
-
-void halbtc8192e2ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist
- *btcoexist, IN boolean low_penalty_ra)
-{
- u8 h2c_parameter[6] = {0};
-
- h2c_parameter[0] = 0x6; /* op_code, 0x6= Retry_Penalty */
-
- if (low_penalty_ra) {
- h2c_parameter[1] |= BIT(0);
- h2c_parameter[2] =
- 0x00; /* normal rate except MCS7/6/5, OFDM54/48/36 */
- h2c_parameter[3] = 0xf7; /* MCS7 or OFDM54 */
- h2c_parameter[4] = 0xf8; /* MCS6 or OFDM48 */
- h2c_parameter[5] = 0xf9; /* MCS5 or OFDM36 */
- }
-
- btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter);
-}
-
-void halbtc8192e2ant_low_penalty_ra(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean low_penalty_ra)
-{
- coex_dm->cur_low_penalty_ra = low_penalty_ra;
-
- if (!force_exec) {
- if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra)
- return;
- }
- halbtc8192e2ant_set_sw_penalty_tx_rate_adaptive(btcoexist,
- coex_dm->cur_low_penalty_ra);
-
- coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra;
-}
-
-void halbtc8192e2ant_set_dac_swing_reg(IN struct btc_coexist *btcoexist,
- IN u32 level)
-{
- u8 val = (u8)level;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Write SwDacSwing = 0x%x\n", level);
- BTC_TRACE(trace_buf);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x883, 0x3e, val);
-}
-
-void halbtc8192e2ant_set_sw_full_time_dac_swing(IN struct btc_coexist
- *btcoexist, IN boolean sw_dac_swing_on, IN u32 sw_dac_swing_lvl)
-{
- if (sw_dac_swing_on)
- halbtc8192e2ant_set_dac_swing_reg(btcoexist, sw_dac_swing_lvl);
- else
- halbtc8192e2ant_set_dac_swing_reg(btcoexist, 0x18);
-}
-
-
-void halbtc8192e2ant_dac_swing(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean dac_swing_on, IN u32 dac_swing_lvl)
-{
- coex_dm->cur_dac_swing_on = dac_swing_on;
- coex_dm->cur_dac_swing_lvl = dac_swing_lvl;
-
- if (!force_exec) {
- if ((coex_dm->pre_dac_swing_on == coex_dm->cur_dac_swing_on) &&
- (coex_dm->pre_dac_swing_lvl ==
- coex_dm->cur_dac_swing_lvl))
- return;
- }
- delay_ms(30);
- halbtc8192e2ant_set_sw_full_time_dac_swing(btcoexist, dac_swing_on,
- dac_swing_lvl);
-
- coex_dm->pre_dac_swing_on = coex_dm->cur_dac_swing_on;
- coex_dm->pre_dac_swing_lvl = coex_dm->cur_dac_swing_lvl;
-}
-
-void halbtc8192e2ant_set_adc_back_off(IN struct btc_coexist *btcoexist,
- IN boolean adc_back_off)
-{
- if (adc_back_off) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BB BackOff Level On!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc05, 0x30, 0x3);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BB BackOff Level Off!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc05, 0x30, 0x1);
- }
-}
-
-void halbtc8192e2ant_adc_back_off(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean adc_back_off)
-{
- coex_dm->cur_adc_back_off = adc_back_off;
-
- if (!force_exec) {
- if (coex_dm->pre_adc_back_off == coex_dm->cur_adc_back_off)
- return;
- }
- halbtc8192e2ant_set_adc_back_off(btcoexist, coex_dm->cur_adc_back_off);
-
- coex_dm->pre_adc_back_off = coex_dm->cur_adc_back_off;
-}
-
-void halbtc8192e2ant_set_agc_table(IN struct btc_coexist *btcoexist,
- IN boolean agc_table_en)
-{
- /* =================BB AGC Gain Table */
- if (agc_table_en) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BB Agc Table On!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x0a1A0001);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x091B0001);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x081C0001);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x071D0001);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x061E0001);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x051F0001);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BB Agc Table Off!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xaa1A0001);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa91B0001);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa81C0001);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa71D0001);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa61E0001);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa51F0001);
- }
-}
-
-void halbtc8192e2ant_agc_table(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean agc_table_en)
-{
- coex_dm->cur_agc_table_en = agc_table_en;
-
- if (!force_exec) {
- if (coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en)
- return;
- }
- halbtc8192e2ant_set_agc_table(btcoexist, agc_table_en);
-
- coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en;
-}
-
-void halbtc8192e2ant_set_coex_table(IN struct btc_coexist *btcoexist,
- IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc)
-{
- btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
-
- btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
-
- btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
-
- btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
-}
-
-void halbtc8192e2ant_coex_table(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4,
- IN u32 val0x6c8, IN u8 val0x6cc)
-{
- coex_dm->cur_val0x6c0 = val0x6c0;
- coex_dm->cur_val0x6c4 = val0x6c4;
- coex_dm->cur_val0x6c8 = val0x6c8;
- coex_dm->cur_val0x6cc = val0x6cc;
-
- if (!force_exec) {
- if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) &&
- (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) &&
- (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) &&
- (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc))
- return;
- }
- halbtc8192e2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8,
- val0x6cc);
-
- coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0;
- coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4;
- coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8;
- coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc;
-}
-
-void halbtc8192e2ant_coex_table_with_type(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- switch (type) {
- case 0:
- halbtc8192e2ant_coex_table(btcoexist, force_exec,
- 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3);
- break;
- case 1:
- halbtc8192e2ant_coex_table(btcoexist, force_exec,
- 0x5a5a5a5a, 0x5a5a5a5a, 0xffffff, 0x3);
- break;
- case 2:
- halbtc8192e2ant_coex_table(btcoexist, force_exec,
- 0x55555555, 0x5ffb5ffb, 0xffffff, 0x3);
- break;
- case 3:
- halbtc8192e2ant_coex_table(btcoexist, force_exec,
- 0x5fdf5fdf, 0x5fdb5fdb, 0xffffff, 0x3);
- break;
- case 4:
- halbtc8192e2ant_coex_table(btcoexist, force_exec,
- 0xdfffdfff, 0x5ffb5ffb, 0xffffff, 0x3);
- break;
-
- default:
- break;
- }
-}
-
-void halbtc8192e2ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist,
- IN boolean enable)
-{
- u8 h2c_parameter[1] = {0};
-
- if (enable) {
- h2c_parameter[0] |= BIT(0); /* function enable */
- }
-
- btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter);
-}
-
-void halbtc8192e2ant_ignore_wlan_act(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean enable)
-{
- coex_dm->cur_ignore_wlan_act = enable;
-
- if (!force_exec) {
- if (coex_dm->pre_ignore_wlan_act ==
- coex_dm->cur_ignore_wlan_act)
- return;
- }
- halbtc8192e2ant_set_fw_ignore_wlan_act(btcoexist, enable);
-
- coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
-}
-
-void halbtc8192e2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist,
- IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5)
-{
- u8 h2c_parameter[5] = {0};
-
- h2c_parameter[0] = byte1;
- h2c_parameter[1] = byte2;
- h2c_parameter[2] = byte3;
- h2c_parameter[3] = byte4;
- h2c_parameter[4] = byte5;
-
- coex_dm->ps_tdma_para[0] = byte1;
- coex_dm->ps_tdma_para[1] = byte2;
- coex_dm->ps_tdma_para[2] = byte3;
- coex_dm->ps_tdma_para[3] = byte4;
- coex_dm->ps_tdma_para[4] = byte5;
-
- btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
-}
-
-void halbtc8192e2ant_sw_mechanism1(IN struct btc_coexist *btcoexist,
- IN boolean shrink_rx_lpf, IN boolean low_penalty_ra,
- IN boolean limited_dig, IN boolean bt_lna_constrain)
-{
- /*
- u32 wifi_bw;
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- if(BTC_WIFI_BW_HT40 != wifi_bw)
- {
- if (shrink_rx_lpf)
- shrink_rx_lpf = false;
- }
- */
-
- halbtc8192e2ant_rf_shrink(btcoexist, NORMAL_EXEC, shrink_rx_lpf);
- /* halbtc8192e2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra); */
-}
-
-void halbtc8192e2ant_sw_mechanism2(IN struct btc_coexist *btcoexist,
- IN boolean agc_table_shift, IN boolean adc_back_off,
- IN boolean sw_dac_swing, IN u32 dac_swing_lvl)
-{
- halbtc8192e2ant_agc_table(btcoexist, NORMAL_EXEC, agc_table_shift);
- /* halbtc8192e2ant_adc_back_off(btcoexist, NORMAL_EXEC, adc_back_off); */
- halbtc8192e2ant_dac_swing(btcoexist, NORMAL_EXEC, sw_dac_swing,
- dac_swing_lvl);
-}
-
-void halbtc8192e2ant_set_ant_path(IN struct btc_coexist *btcoexist,
- IN u8 ant_pos_type, IN boolean init_hwcfg, IN boolean wifi_off)
-{
- u32 u32tmp = 0;
-
- if (init_hwcfg) {
- btcoexist->btc_write_1byte(btcoexist, 0x944, 0x24);
- btcoexist->btc_write_4byte(btcoexist, 0x930, 0x700700);
- if (btcoexist->chip_interface == BTC_INTF_USB)
- btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30430004);
- else
- btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30030004);
-
- /* 0x4c[27][24]='00', Set Antenna to BB */
- u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c);
- u32tmp &= ~BIT(24);
- u32tmp &= ~BIT(27);
- btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp);
- } else if (wifi_off) {
- if (btcoexist->chip_interface == BTC_INTF_USB)
- btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30430004);
- else
- btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30030004);
-
- /* 0x4c[27][24]='11', Set Antenna to BT, 0x64[8:7]=0, 0x64[2]=1 */
- u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c);
- u32tmp |= BIT(24);
- u32tmp |= BIT(27);
- btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp);
- }
-
- /* ext switch setting */
- switch (ant_pos_type) {
- case BTC_ANT_PATH_WIFI:
- btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x4);
- break;
- case BTC_ANT_PATH_BT:
- btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x20);
- break;
- default:
- case BTC_ANT_PATH_PTA:
- btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x4);
- break;
- }
-}
-
-void halbtc8192e2ant_ps_tdma(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean turn_on, IN u8 type)
-{
- coex_dm->cur_ps_tdma_on = turn_on;
- coex_dm->cur_ps_tdma = type;
-
- if (!force_exec) {
- if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) &&
- (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma))
- return;
- }
- if (turn_on) {
- switch (type) {
- case 1:
- default:
- halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x1a, 0x1a, 0xe1, 0x90);
- break;
- case 2:
- halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x12, 0x12, 0xe1, 0x90);
- break;
- case 3:
- halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x1c, 0x3, 0xf1, 0x90);
- break;
- case 4:
- halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x10, 0x3, 0xf1, 0x90);
- break;
- case 5:
- halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x1a, 0x1a, 0x60, 0x90);
- break;
- case 6:
- halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x12, 0x12, 0x60, 0x90);
- break;
- case 7:
- halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x1c, 0x3, 0x70, 0x90);
- break;
- case 8:
- halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xa3,
- 0x10, 0x3, 0x70, 0x90);
- break;
- case 9:
- halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x1a, 0x1a, 0xe1, 0x10);
- break;
- case 10:
- halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x12, 0x12, 0xe1, 0x10);
- break;
- case 11:
- halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x1c, 0x3, 0xf1, 0x10);
- break;
- case 12:
- halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x10, 0x3, 0xf1, 0x10);
- break;
- case 13:
- halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x1a, 0x1a, 0xe0, 0x10);
- break;
- case 14:
- halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x12, 0x12, 0xe0, 0x10);
- break;
- case 15:
- halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x1c, 0x3, 0xf0, 0x10);
- break;
- case 16:
- halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x12, 0x3, 0xf0, 0x10);
- break;
- case 17:
- halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x61,
- 0x20, 0x03, 0x10, 0x10);
- break;
- case 18:
- halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x5, 0x5, 0xe1, 0x90);
- break;
- case 19:
- halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x25, 0x25, 0xe1, 0x90);
- break;
- case 20:
- halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x25, 0x25, 0x60, 0x90);
- break;
- case 21:
- halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x15, 0x03, 0x70, 0x90);
- break;
- case 71:
- halbtc8192e2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x1a, 0x1a, 0xe1, 0x90);
- break;
- }
- } else {
- /* disable PS tdma */
- switch (type) {
- default:
- case 0: /* ANT2PTA, 0x778=1 */
- halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x8,
- 0x0, 0x0, 0x0, 0x0);
- halbtc8192e2ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_PTA, false, false);
- break;
- case 1: /* ANT2BT, 0x778=3 */
- halbtc8192e2ant_set_fw_pstdma(btcoexist, 0x0,
- 0x0, 0x0, 0x8, 0x0);
- delay_ms(5);
- halbtc8192e2ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_BT, false, false);
- break;
-
- }
- }
-
- /* update pre state */
- coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on;
- coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
-}
-
-void halbtc8192e2ant_set_switch_ss_type(IN struct btc_coexist *btcoexist,
- IN u8 ss_type)
-{
- u8 mimo_ps = BTC_MIMO_PS_DYNAMIC;
- u32 dis_ra_mask = 0x0;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], REAL set SS Type = %d\n", ss_type);
- BTC_TRACE(trace_buf);
-
- dis_ra_mask = halbtc8192e2ant_decide_ra_mask(btcoexist, ss_type,
- coex_dm->cur_ra_mask_type);
- halbtc8192e2ant_update_ra_mask(btcoexist, FORCE_EXEC, dis_ra_mask);
-
- if (ss_type == 1) {
- halbtc8192e2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 1);
- /* switch ofdm path */
- btcoexist->btc_write_1byte(btcoexist, 0xc04, 0x11);
- btcoexist->btc_write_1byte(btcoexist, 0xd04, 0x1);
- btcoexist->btc_write_4byte(btcoexist, 0x90c, 0x81111111);
- /* switch cck patch */
- /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0xe77, 0x4, 0x1); */
- /* btcoexist->btc_write_1byte(btcoexist, 0xa07, 0x81); */
- mimo_ps = BTC_MIMO_PS_STATIC;
- } else if (ss_type == 2) {
- halbtc8192e2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
- btcoexist->btc_write_1byte(btcoexist, 0xc04, 0x33);
- btcoexist->btc_write_1byte(btcoexist, 0xd04, 0x3);
- btcoexist->btc_write_4byte(btcoexist, 0x90c, 0x81121313);
- /* remove, if 0xe77[2]=0x0 then CCK will fail, advised by Jenyu */
- /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0xe77, 0x4, 0x0); */
- /* btcoexist->btc_write_1byte(btcoexist, 0xa07, 0x41); */
- mimo_ps = BTC_MIMO_PS_DYNAMIC;
- }
-
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_SEND_MIMO_PS,
- &mimo_ps); /* set rx 1ss or 2ss */
-}
-
-void halbtc8192e2ant_switch_ss_type(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 new_ss_type)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], %s Switch SS Type = %d\n",
- (force_exec ? "force to" : ""), new_ss_type);
- BTC_TRACE(trace_buf);
- coex_dm->cur_ss_type = new_ss_type;
-
- if (!force_exec) {
- if (coex_dm->pre_ss_type == coex_dm->cur_ss_type)
- return;
- }
- halbtc8192e2ant_set_switch_ss_type(btcoexist, coex_dm->cur_ss_type);
-
- coex_dm->pre_ss_type = coex_dm->cur_ss_type;
-}
-
-void halbtc8192e2ant_coex_all_off(IN struct btc_coexist *btcoexist)
-{
- /* fw all off */
- halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
- halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
- halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- /* sw all off */
- halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
-
- /* hw all off */
- halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-}
-
-void halbtc8192e2ant_init_coex_dm(IN struct btc_coexist *btcoexist)
-{
- /* force to reset coex mechanism */
-
- halbtc8192e2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 1);
- halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 6);
- halbtc8192e2ant_dec_bt_pwr(btcoexist, FORCE_EXEC, 0);
-
- halbtc8192e2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
- halbtc8192e2ant_switch_ss_type(btcoexist, FORCE_EXEC, 2);
-
- halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
-}
-
-void halbtc8192e2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist)
-{
- boolean low_pwr_disable = true;
-
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
-
- halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);
-
- halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
- halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3);
- halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
- halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
-}
-
-boolean halbtc8192e2ant_is_common_action(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean common = false, wifi_connected = false, wifi_busy = false;
- boolean bt_hs_on = false, low_pwr_disable = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- if (bt_link_info->sco_exist || bt_link_info->hid_exist)
- halbtc8192e2ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 0, 0, 0);
- else
- halbtc8192e2ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
-
- if (!wifi_connected) {
- low_pwr_disable = false;
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi non-connected idle!!\n");
- BTC_TRACE(trace_buf);
-
- if ((BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
- coex_dm->bt_status) ||
- (BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE ==
- coex_dm->bt_status)) {
- halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC,
- 2);
- halbtc8192e2ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 1);
- halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 0);
- } else {
- halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC,
- 1);
- halbtc8192e2ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 0);
- halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 1);
- }
-
- halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
- halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false,
- false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false,
- 0x18);
-
- common = true;
- } else {
- if (BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
- coex_dm->bt_status) {
- low_pwr_disable = false;
- btcoexist->btc_set(btcoexist,
- BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi connected + BT non connected-idle!!\n");
- BTC_TRACE(trace_buf);
-
- halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC,
- 2);
- halbtc8192e2ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 1);
- halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 0);
- halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC,
- 6);
- halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8192e2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
-
- common = true;
- } else if (BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE ==
- coex_dm->bt_status) {
- low_pwr_disable = true;
- btcoexist->btc_set(btcoexist,
- BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
-
- if (bt_hs_on)
- return false;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi connected + BT connected-idle!!\n");
- BTC_TRACE(trace_buf);
-
- halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC,
- 2);
- halbtc8192e2ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 1);
- halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 0);
- halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC,
- 6);
- halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8192e2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
-
- common = true;
- } else {
- low_pwr_disable = true;
- btcoexist->btc_set(btcoexist,
- BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
-
- if (wifi_busy) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi Connected-Busy + BT Busy!!\n");
- BTC_TRACE(trace_buf);
- common = false;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi Connected-Idle + BT Busy!!\n");
- BTC_TRACE(trace_buf);
-
- halbtc8192e2ant_switch_ss_type(btcoexist,
- NORMAL_EXEC, 1);
- halbtc8192e2ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 2);
- halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 21);
- halbtc8192e2ant_fw_dac_swing_lvl(btcoexist,
- NORMAL_EXEC, 6);
- halbtc8192e2ant_dec_bt_pwr(btcoexist,
- NORMAL_EXEC, 0);
- halbtc8192e2ant_sw_mechanism1(btcoexist, false,
- false, false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, false,
- false, false, 0x18);
- common = true;
- }
- }
- }
-
- return common;
-}
-void halbtc8192e2ant_tdma_duration_adjust(IN struct btc_coexist *btcoexist,
- IN boolean sco_hid, IN boolean tx_pause, IN u8 max_interval)
-{
- static s32 up, dn, m, n, wait_count;
- s32 result; /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */
- u8 retry_count = 0;
-
-
- if (!coex_dm->auto_tdma_adjust) {
- coex_dm->auto_tdma_adjust = true;
- {
- if (sco_hid) {
- if (tx_pause) {
- if (max_interval == 1) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 13);
- coex_dm->ps_tdma_du_adj_type =
- 13;
- } else if (max_interval == 2) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 14);
- coex_dm->ps_tdma_du_adj_type =
- 14;
- } else if (max_interval == 3) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- }
- } else {
- if (max_interval == 1) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 9);
- coex_dm->ps_tdma_du_adj_type =
- 9;
- } else if (max_interval == 2) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 10);
- coex_dm->ps_tdma_du_adj_type =
- 10;
- } else if (max_interval == 3) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- }
- }
- } else {
- if (tx_pause) {
- if (max_interval == 1) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 5);
- coex_dm->ps_tdma_du_adj_type =
- 5;
- } else if (max_interval == 2) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 6);
- coex_dm->ps_tdma_du_adj_type =
- 6;
- } else if (max_interval == 3) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- }
- } else {
- if (max_interval == 1) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 1);
- coex_dm->ps_tdma_du_adj_type =
- 1;
- } else if (max_interval == 2) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 2);
- coex_dm->ps_tdma_du_adj_type =
- 2;
- } else if (max_interval == 3) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- }
- }
- }
- }
- /* ============ */
- up = 0;
- dn = 0;
- m = 1;
- n = 3;
- result = 0;
- wait_count = 0;
- } else {
- /* accquire the BT TRx retry count from BT_Info byte2 */
- retry_count = coex_sta->bt_retry_cnt;
- result = 0;
- wait_count++;
-
- if (retry_count ==
- 0) { /* no retry in the last 2-second duration */
- up++;
- dn--;
-
- if (dn <= 0)
- dn = 0;
-
- if (up >= n) { /* if retry count during continuous n*2 seconds is 0, enlarge WiFi duration */
- wait_count = 0;
- n = 3;
- up = 0;
- dn = 0;
- result = 1;
- }
- } else if (retry_count <=
- 3) { /* <=3 retry in the last 2-second duration */
- up--;
- dn++;
-
- if (up <= 0)
- up = 0;
-
- if (dn == 2) { /* if continuous 2 retry count(every 2 seconds) >0 and < 3, reduce WiFi duration */
- if (wait_count <= 2)
- m++; /* to avoid loop between the two levels */
- else
- m = 1;
-
- if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */
- m = 20;
-
- n = 3 * m;
- up = 0;
- dn = 0;
- wait_count = 0;
- result = -1;
- }
- } else { /* retry count > 3, once retry count > 3, to reduce WiFi duration */
- if (wait_count == 1)
- m++; /* to avoid loop between the two levels */
- else
- m = 1;
-
- if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */
- m = 20;
-
- n = 3 * m;
- up = 0;
- dn = 0;
- wait_count = 0;
- result = -1;
- }
-
- if (max_interval == 1) {
- if (tx_pause) {
- if (coex_dm->cur_ps_tdma == 71) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 5);
- coex_dm->ps_tdma_du_adj_type = 5;
- } else if (coex_dm->cur_ps_tdma == 1) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 5);
- coex_dm->ps_tdma_du_adj_type = 5;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 6);
- coex_dm->ps_tdma_du_adj_type = 6;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 7);
- coex_dm->ps_tdma_du_adj_type = 7;
- } else if (coex_dm->cur_ps_tdma == 4) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 8);
- coex_dm->ps_tdma_du_adj_type = 8;
- }
- if (coex_dm->cur_ps_tdma == 9) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 13);
- coex_dm->ps_tdma_du_adj_type = 13;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 14);
- coex_dm->ps_tdma_du_adj_type = 14;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 15);
- coex_dm->ps_tdma_du_adj_type = 15;
- } else if (coex_dm->cur_ps_tdma == 12) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 16);
- coex_dm->ps_tdma_du_adj_type = 16;
- }
-
- if (result == -1) {
- if (coex_dm->cur_ps_tdma == 5) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 6);
- coex_dm->ps_tdma_du_adj_type =
- 6;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 8);
- coex_dm->ps_tdma_du_adj_type =
- 8;
- } else if (coex_dm->cur_ps_tdma == 13) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 14);
- coex_dm->ps_tdma_du_adj_type =
- 14;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 16);
- coex_dm->ps_tdma_du_adj_type =
- 16;
- }
- } else if (result == 1) {
- if (coex_dm->cur_ps_tdma == 8) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 6);
- coex_dm->ps_tdma_du_adj_type =
- 6;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 5);
- coex_dm->ps_tdma_du_adj_type =
- 5;
- } else if (coex_dm->cur_ps_tdma == 16) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 14);
- coex_dm->ps_tdma_du_adj_type =
- 14;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 13);
- coex_dm->ps_tdma_du_adj_type =
- 13;
- }
- }
- } else {
- if (coex_dm->cur_ps_tdma == 5) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 71);
- coex_dm->ps_tdma_du_adj_type = 71;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 2);
- coex_dm->ps_tdma_du_adj_type = 2;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 3);
- coex_dm->ps_tdma_du_adj_type = 3;
- } else if (coex_dm->cur_ps_tdma == 8) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 4);
- coex_dm->ps_tdma_du_adj_type = 4;
- }
- if (coex_dm->cur_ps_tdma == 13) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 9);
- coex_dm->ps_tdma_du_adj_type = 9;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 10);
- coex_dm->ps_tdma_du_adj_type = 10;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 11);
- coex_dm->ps_tdma_du_adj_type = 11;
- } else if (coex_dm->cur_ps_tdma == 16) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 12);
- coex_dm->ps_tdma_du_adj_type = 12;
- }
-
- if (result == -1) {
- if (coex_dm->cur_ps_tdma == 71) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 1);
- coex_dm->ps_tdma_du_adj_type =
- 1;
- } else if (coex_dm->cur_ps_tdma == 1) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 2);
- coex_dm->ps_tdma_du_adj_type =
- 2;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 4);
- coex_dm->ps_tdma_du_adj_type =
- 4;
- } else if (coex_dm->cur_ps_tdma == 9) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 10);
- coex_dm->ps_tdma_du_adj_type =
- 10;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 12);
- coex_dm->ps_tdma_du_adj_type =
- 12;
- }
- } else if (result == 1) {
- if (coex_dm->cur_ps_tdma == 4) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 2);
- coex_dm->ps_tdma_du_adj_type =
- 2;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 1);
- coex_dm->ps_tdma_du_adj_type =
- 1;
- } else if (coex_dm->cur_ps_tdma == 1) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 71);
- coex_dm->ps_tdma_du_adj_type =
- 71;
- } else if (coex_dm->cur_ps_tdma == 12) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 10);
- coex_dm->ps_tdma_du_adj_type =
- 10;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 9);
- coex_dm->ps_tdma_du_adj_type =
- 9;
- }
- }
- }
- } else if (max_interval == 2) {
- if (tx_pause) {
- if (coex_dm->cur_ps_tdma == 1) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 6);
- coex_dm->ps_tdma_du_adj_type = 6;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 6);
- coex_dm->ps_tdma_du_adj_type = 6;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 7);
- coex_dm->ps_tdma_du_adj_type = 7;
- } else if (coex_dm->cur_ps_tdma == 4) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 8);
- coex_dm->ps_tdma_du_adj_type = 8;
- }
- if (coex_dm->cur_ps_tdma == 9) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 14);
- coex_dm->ps_tdma_du_adj_type = 14;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 14);
- coex_dm->ps_tdma_du_adj_type = 14;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 15);
- coex_dm->ps_tdma_du_adj_type = 15;
- } else if (coex_dm->cur_ps_tdma == 12) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 16);
- coex_dm->ps_tdma_du_adj_type = 16;
- }
- if (result == -1) {
- if (coex_dm->cur_ps_tdma == 5) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 6);
- coex_dm->ps_tdma_du_adj_type =
- 6;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 8);
- coex_dm->ps_tdma_du_adj_type =
- 8;
- } else if (coex_dm->cur_ps_tdma == 13) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 14);
- coex_dm->ps_tdma_du_adj_type =
- 14;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 16);
- coex_dm->ps_tdma_du_adj_type =
- 16;
- }
- } else if (result == 1) {
- if (coex_dm->cur_ps_tdma == 8) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 6);
- coex_dm->ps_tdma_du_adj_type =
- 6;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 6);
- coex_dm->ps_tdma_du_adj_type =
- 6;
- } else if (coex_dm->cur_ps_tdma == 16) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 14);
- coex_dm->ps_tdma_du_adj_type =
- 14;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 14);
- coex_dm->ps_tdma_du_adj_type =
- 14;
- }
- }
- } else {
- if (coex_dm->cur_ps_tdma == 5) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 2);
- coex_dm->ps_tdma_du_adj_type = 2;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 2);
- coex_dm->ps_tdma_du_adj_type = 2;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 3);
- coex_dm->ps_tdma_du_adj_type = 3;
- } else if (coex_dm->cur_ps_tdma == 8) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 4);
- coex_dm->ps_tdma_du_adj_type = 4;
- }
- if (coex_dm->cur_ps_tdma == 13) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 10);
- coex_dm->ps_tdma_du_adj_type = 10;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 10);
- coex_dm->ps_tdma_du_adj_type = 10;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 11);
- coex_dm->ps_tdma_du_adj_type = 11;
- } else if (coex_dm->cur_ps_tdma == 16) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 12);
- coex_dm->ps_tdma_du_adj_type = 12;
- }
- if (result == -1) {
- if (coex_dm->cur_ps_tdma == 1) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 2);
- coex_dm->ps_tdma_du_adj_type =
- 2;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 4);
- coex_dm->ps_tdma_du_adj_type =
- 4;
- } else if (coex_dm->cur_ps_tdma == 9) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 10);
- coex_dm->ps_tdma_du_adj_type =
- 10;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 12);
- coex_dm->ps_tdma_du_adj_type =
- 12;
- }
- } else if (result == 1) {
- if (coex_dm->cur_ps_tdma == 4) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 2);
- coex_dm->ps_tdma_du_adj_type =
- 2;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 2);
- coex_dm->ps_tdma_du_adj_type =
- 2;
- } else if (coex_dm->cur_ps_tdma == 12) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 10);
- coex_dm->ps_tdma_du_adj_type =
- 10;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 10);
- coex_dm->ps_tdma_du_adj_type =
- 10;
- }
- }
- }
- } else if (max_interval == 3) {
- if (tx_pause) {
- if (coex_dm->cur_ps_tdma == 1) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 7);
- coex_dm->ps_tdma_du_adj_type = 7;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 7);
- coex_dm->ps_tdma_du_adj_type = 7;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 7);
- coex_dm->ps_tdma_du_adj_type = 7;
- } else if (coex_dm->cur_ps_tdma == 4) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 8);
- coex_dm->ps_tdma_du_adj_type = 8;
- }
- if (coex_dm->cur_ps_tdma == 9) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 15);
- coex_dm->ps_tdma_du_adj_type = 15;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 15);
- coex_dm->ps_tdma_du_adj_type = 15;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 15);
- coex_dm->ps_tdma_du_adj_type = 15;
- } else if (coex_dm->cur_ps_tdma == 12) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 16);
- coex_dm->ps_tdma_du_adj_type = 16;
- }
- if (result == -1) {
- if (coex_dm->cur_ps_tdma == 5) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 8);
- coex_dm->ps_tdma_du_adj_type =
- 8;
- } else if (coex_dm->cur_ps_tdma == 13) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 16);
- coex_dm->ps_tdma_du_adj_type =
- 16;
- }
- } else if (result == 1) {
- if (coex_dm->cur_ps_tdma == 8) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 16) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- }
- }
- } else {
- if (coex_dm->cur_ps_tdma == 5) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 3);
- coex_dm->ps_tdma_du_adj_type = 3;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 3);
- coex_dm->ps_tdma_du_adj_type = 3;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 3);
- coex_dm->ps_tdma_du_adj_type = 3;
- } else if (coex_dm->cur_ps_tdma == 8) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 4);
- coex_dm->ps_tdma_du_adj_type = 4;
- }
- if (coex_dm->cur_ps_tdma == 13) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 11);
- coex_dm->ps_tdma_du_adj_type = 11;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 11);
- coex_dm->ps_tdma_du_adj_type = 11;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 11);
- coex_dm->ps_tdma_du_adj_type = 11;
- } else if (coex_dm->cur_ps_tdma == 16) {
- halbtc8192e2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 12);
- coex_dm->ps_tdma_du_adj_type = 12;
- }
- if (result == -1) {
- if (coex_dm->cur_ps_tdma == 1) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 4);
- coex_dm->ps_tdma_du_adj_type =
- 4;
- } else if (coex_dm->cur_ps_tdma == 9) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 12);
- coex_dm->ps_tdma_du_adj_type =
- 12;
- }
- } else if (result == 1) {
- if (coex_dm->cur_ps_tdma == 4) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 12) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8192e2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- }
- }
- }
- }
- }
-
- /* if current PsTdma not match with the recorded one (when scan, dhcp...), */
- /* then we have to adjust it back to the previous record one. */
- if (coex_dm->cur_ps_tdma != coex_dm->ps_tdma_du_adj_type) {
- boolean scan = false, link = false, roam = false;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], PsTdma type dismatch!!!, cur_ps_tdma=%d, recordPsTdma=%d\n",
- coex_dm->cur_ps_tdma, coex_dm->ps_tdma_du_adj_type);
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
-
- if (!scan && !link && !roam)
- halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- coex_dm->ps_tdma_du_adj_type);
- else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n");
- BTC_TRACE(trace_buf);
- }
- }
-}
-
-/* SCO only or SCO+PAN(HS) */
-void halbtc8192e2ant_action_sco(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- u32 wifi_bw;
-
- wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15,
- 0);
-
- halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);
- halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
-
- halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
- halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
-
- bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, 34, 42);
-
- if ((bt_rssi_state == BTC_RSSI_STATE_LOW) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
- halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
- halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13);
- } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
- halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9);
- } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
- halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9);
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- /* sw mechanism */
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8192e2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x6);
- } else {
- halbtc8192e2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x6);
- }
- } else {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8192e2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x6);
- } else {
- halbtc8192e2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x6);
- }
- }
-}
-
-void halbtc8192e2ant_action_sco_pan(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- u32 wifi_bw;
-
- wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15,
- 0);
-
- halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);
- halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
-
- halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
- halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
-
- bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, 34, 42);
-
- if ((bt_rssi_state == BTC_RSSI_STATE_LOW) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
- halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
- halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14);
- } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
- halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 10);
- } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
- halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 10);
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- /* sw mechanism */
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8192e2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x6);
- } else {
- halbtc8192e2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x6);
- }
- } else {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8192e2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x6);
- } else {
- halbtc8192e2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x6);
- }
- }
-}
-
-void halbtc8192e2ant_action_hid(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH;
- u32 wifi_bw;
-
- wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15,
- 0);
- bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, 34, 42);
-
- halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);
- halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
-
- halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
-
- if ((bt_rssi_state == BTC_RSSI_STATE_LOW) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
- halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
- halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13);
- } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
- halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9);
- } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
- halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9);
- }
-
- /* sw mechanism */
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8192e2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8192e2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- } else {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8192e2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8192e2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- }
-}
-
-/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */
-void halbtc8192e2ant_action_a2dp(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH;
- u32 wifi_bw;
- boolean long_dist = false;
-
- wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15,
- 0);
- bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, 34, 42);
-
- if ((bt_rssi_state == BTC_RSSI_STATE_LOW ||
- bt_rssi_state == BTC_RSSI_STATE_STAY_LOW) &&
- (wifi_rssi_state == BTC_RSSI_STATE_LOW ||
- wifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], A2dp, wifi/bt rssi both LOW!!\n");
- BTC_TRACE(trace_buf);
- long_dist = true;
- }
- if (long_dist) {
- halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 2);
- halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true,
- 0x4);
- } else {
- halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);
- halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
- 0x8);
- }
-
- halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
- if (long_dist)
- halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
- else
- halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
-
-
- if (long_dist) {
- halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 17);
- coex_dm->auto_tdma_adjust = false;
- halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
- } else {
- if ((bt_rssi_state == BTC_RSSI_STATE_LOW) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
- halbtc8192e2ant_tdma_duration_adjust(btcoexist, false,
- true, 1);
- halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
- } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
- halbtc8192e2ant_tdma_duration_adjust(btcoexist, false,
- false, 1);
- halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8192e2ant_tdma_duration_adjust(btcoexist, false,
- false, 1);
- halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
- }
- }
-
- /* sw mechanism */
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8192e2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8192e2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- } else {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8192e2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8192e2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- }
-}
-
-void halbtc8192e2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH;
- u32 wifi_bw;
-
- wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15,
- 0);
- bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, 34, 42);
-
- halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);
- halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
-
- halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
- halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
-
- if ((bt_rssi_state == BTC_RSSI_STATE_LOW) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
- halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, true, 2);
- halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
- } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
- halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, false,
- 2);
- halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, false,
- 2);
- halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
- }
-
- /* sw mechanism */
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8192e2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
- true, 0x6);
- } else {
- halbtc8192e2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
- true, 0x6);
- }
- } else {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8192e2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
- true, 0x6);
- } else {
- halbtc8192e2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
- true, 0x6);
- }
- }
-}
-
-void halbtc8192e2ant_action_pan_edr(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH;
- u32 wifi_bw;
-
- wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15,
- 0);
- bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, 34, 42);
-
- halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);
- halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
-
- halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
- halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
-
- if ((bt_rssi_state == BTC_RSSI_STATE_LOW) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
- halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
- halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
- } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
- halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 1);
- } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
- halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 1);
- }
-
- /* sw mechanism */
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8192e2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8192e2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- } else {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8192e2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8192e2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- }
-}
-
-/* PAN(HS) only */
-void halbtc8192e2ant_action_pan_hs(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH;
- u32 wifi_bw;
-
- wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15,
- 0);
- bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, 34, 42);
-
- halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);
- halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
-
- halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
- halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
-
- if ((bt_rssi_state == BTC_RSSI_STATE_LOW) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW))
- halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
- else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM))
- halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH))
- halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
- halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8192e2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8192e2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- } else {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8192e2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8192e2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- }
-}
-
-/* PAN(EDR)+A2DP */
-void halbtc8192e2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH;
- u32 wifi_bw;
-
- wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15,
- 0);
- bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, 34, 42);
-
- halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);
- halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
-
- halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
- halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- if ((bt_rssi_state == BTC_RSSI_STATE_LOW) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
- halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
- halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, true, 3);
- } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
- halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, false,
- 3);
- } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
- halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, false,
- 3);
- }
-
- /* sw mechanism */
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8192e2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8192e2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- } else {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8192e2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8192e2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- }
-}
-
-void halbtc8192e2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH;
- u32 wifi_bw;
-
- wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15,
- 0);
- bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, 34, 42);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);
- halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
-
- halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
- halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
-
- if ((bt_rssi_state == BTC_RSSI_STATE_LOW) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
- halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
- halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14);
- } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
- halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 10);
- } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
- halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 10);
- }
-
- /* sw mechanism */
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8192e2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8192e2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- } else {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8192e2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8192e2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- }
-}
-
-/* HID+A2DP+PAN(EDR) */
-void halbtc8192e2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH;
- u32 wifi_bw;
-
- wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15,
- 0);
- bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, 34, 42);
-
- halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);
- halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
-
- halbtc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
-
- if ((bt_rssi_state == BTC_RSSI_STATE_LOW) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
- halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
- halbtc8192e2ant_tdma_duration_adjust(btcoexist, true, true, 3);
- } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
- halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- halbtc8192e2ant_tdma_duration_adjust(btcoexist, true, false, 3);
- } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
- halbtc8192e2ant_tdma_duration_adjust(btcoexist, true, false, 3);
- }
-
- /* sw mechanism */
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8192e2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8192e2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- } else {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8192e2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8192e2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- }
-}
-
-void halbtc8192e2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH;
- u32 wifi_bw;
-
- wifi_rssi_state = halbtc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15,
- 0);
- bt_rssi_state = halbtc8192e2ant_bt_rssi_state(3, 34, 42);
-
- halbtc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);
- halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
-
- if ((bt_rssi_state == BTC_RSSI_STATE_LOW) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
- halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
- halbtc8192e2ant_tdma_duration_adjust(btcoexist, true, true, 2);
- } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
- halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- halbtc8192e2ant_tdma_duration_adjust(btcoexist, true, false, 2);
- } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
- halbtc8192e2ant_tdma_duration_adjust(btcoexist, true, false, 2);
- }
-
- /* sw mechanism */
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8192e2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8192e2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- } else {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8192e2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8192e2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- }
-}
-
-void halbtc8192e2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist)
-{
- u8 algorithm = 0;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism()===>\n");
- BTC_TRACE(trace_buf);
-
- if (btcoexist->manual_control) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- if (coex_sta->under_ips) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], wifi is under IPS !!!\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- algorithm = halbtc8192e2ant_action_algorithm(btcoexist);
- if (coex_sta->c2h_bt_inquiry_page &&
- (BT_8192E_2ANT_COEX_ALGO_PANHS != algorithm)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is under inquiry/page scan !!\n");
- BTC_TRACE(trace_buf);
- halbtc8192e2ant_action_bt_inquiry(btcoexist);
- return;
- }
-
- coex_dm->cur_algorithm = algorithm;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Algorithm = %d\n",
- coex_dm->cur_algorithm);
- BTC_TRACE(trace_buf);
-
- if (halbtc8192e2ant_is_common_action(btcoexist)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant common.\n");
- BTC_TRACE(trace_buf);
- coex_dm->auto_tdma_adjust = false;
- } else {
- if (coex_dm->cur_algorithm != coex_dm->pre_algorithm) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], pre_algorithm=%d, cur_algorithm=%d\n",
- coex_dm->pre_algorithm, coex_dm->cur_algorithm);
- BTC_TRACE(trace_buf);
- coex_dm->auto_tdma_adjust = false;
- }
- switch (coex_dm->cur_algorithm) {
- case BT_8192E_2ANT_COEX_ALGO_SCO:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = SCO.\n");
- BTC_TRACE(trace_buf);
- halbtc8192e2ant_action_sco(btcoexist);
- break;
- case BT_8192E_2ANT_COEX_ALGO_SCO_PAN:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = SCO+PAN(EDR).\n");
- BTC_TRACE(trace_buf);
- halbtc8192e2ant_action_sco_pan(btcoexist);
- break;
- case BT_8192E_2ANT_COEX_ALGO_HID:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = HID.\n");
- BTC_TRACE(trace_buf);
- halbtc8192e2ant_action_hid(btcoexist);
- break;
- case BT_8192E_2ANT_COEX_ALGO_A2DP:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = A2DP.\n");
- BTC_TRACE(trace_buf);
- halbtc8192e2ant_action_a2dp(btcoexist);
- break;
- case BT_8192E_2ANT_COEX_ALGO_A2DP_PANHS:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n");
- BTC_TRACE(trace_buf);
- halbtc8192e2ant_action_a2dp_pan_hs(btcoexist);
- break;
- case BT_8192E_2ANT_COEX_ALGO_PANEDR:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n");
- BTC_TRACE(trace_buf);
- halbtc8192e2ant_action_pan_edr(btcoexist);
- break;
- case BT_8192E_2ANT_COEX_ALGO_PANHS:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = HS mode.\n");
- BTC_TRACE(trace_buf);
- halbtc8192e2ant_action_pan_hs(btcoexist);
- break;
- case BT_8192E_2ANT_COEX_ALGO_PANEDR_A2DP:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n");
- BTC_TRACE(trace_buf);
- halbtc8192e2ant_action_pan_edr_a2dp(btcoexist);
- break;
- case BT_8192E_2ANT_COEX_ALGO_PANEDR_HID:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n");
- BTC_TRACE(trace_buf);
- halbtc8192e2ant_action_pan_edr_hid(btcoexist);
- break;
- case BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n");
- BTC_TRACE(trace_buf);
- halbtc8192e2ant_action_hid_a2dp_pan_edr(
- btcoexist);
- break;
- case BT_8192E_2ANT_COEX_ALGO_HID_A2DP:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n");
- BTC_TRACE(trace_buf);
- halbtc8192e2ant_action_hid_a2dp(btcoexist);
- break;
- default:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = unknown!!\n");
- BTC_TRACE(trace_buf);
- break;
- }
- coex_dm->pre_algorithm = coex_dm->cur_algorithm;
- }
-}
-
-void halbtc8192e2ant_init_hw_config(IN struct btc_coexist *btcoexist,
- IN boolean back_up)
-{
- u16 u16tmp = 0;
- u8 u8tmp = 0;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], 2Ant Init HW Config!!\n");
- BTC_TRACE(trace_buf);
-
- if (back_up) {
- /* backup rf 0x1e value */
- coex_dm->bt_rf_0x1e_backup =
- btcoexist->btc_get_rf_reg(btcoexist, BTC_RF_A, 0x1e,
- 0xfffff);
-
- coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist,
- 0x430);
- coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist,
- 0x434);
- coex_dm->backup_retry_limit = btcoexist->btc_read_2byte(
- btcoexist, 0x42a);
- coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte(
- btcoexist, 0x456);
- }
-
- /* antenna sw ctrl to bt */
- halbtc8192e2ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, true, false);
-
- halbtc8192e2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
-
- /* antenna switch control parameter */
- btcoexist->btc_write_4byte(btcoexist, 0x858, 0x55555555);
-
- /* coex parameters */
- btcoexist->btc_write_1byte(btcoexist, 0x778, 0x3);
- /* 0x790[5:0]=0x5 */
- u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790);
- u8tmp &= 0xc0;
- u8tmp |= 0x5;
- btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp);
-
- /* enable counter statistics */
- btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4);
-
- /* enable PTA */
- btcoexist->btc_write_1byte(btcoexist, 0x40, 0x20);
- /* enable mailbox interface */
- u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x40);
- u16tmp |= BIT(9);
- btcoexist->btc_write_2byte(btcoexist, 0x40, u16tmp);
-
- /* enable PTA I2C mailbox */
- u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x101);
- u8tmp |= BIT(4);
- btcoexist->btc_write_1byte(btcoexist, 0x101, u8tmp);
-
- /* enable bt clock when wifi is disabled. */
- u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x93);
- u8tmp |= BIT(0);
- btcoexist->btc_write_1byte(btcoexist, 0x93, u8tmp);
- /* enable bt clock when suspend. */
- u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x7);
- u8tmp |= BIT(0);
- btcoexist->btc_write_1byte(btcoexist, 0x7, u8tmp);
-}
-
-/* ************************************************************
- * work around function start with wa_halbtc8192e2ant_
- * ************************************************************
- * ************************************************************
- * extern function start with ex_halbtc8192e2ant_
- * ************************************************************ */
-void ex_halbtc8192e2ant_power_on_setting(IN struct btc_coexist *btcoexist)
-{
-}
-
-void ex_halbtc8192e2ant_init_hw_config(IN struct btc_coexist *btcoexist,
- IN boolean wifi_only)
-{
- halbtc8192e2ant_init_hw_config(btcoexist, true);
-}
-
-void ex_halbtc8192e2ant_init_coex_dm(IN struct btc_coexist *btcoexist)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Coex Mechanism Init!!\n");
- BTC_TRACE(trace_buf);
-
- halbtc8192e2ant_init_coex_dm(btcoexist);
-}
-
-void ex_halbtc8192e2ant_display_coex_info(IN struct btc_coexist *btcoexist)
-{
- struct btc_board_info *board_info = &btcoexist->board_info;
- struct btc_stack_info *stack_info = &btcoexist->stack_info;
- u8 *cli_buf = btcoexist->cli_buf;
- u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0;
- u16 u16tmp[4];
- u32 u32tmp[4];
- u32 fw_ver = 0, bt_patch_ver = 0;
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ============[BT Coexist info]============");
- CL_PRINTF(cli_buf);
-
- if (btcoexist->manual_control) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ============[Under Manual Control]============");
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ==========================================");
- CL_PRINTF(cli_buf);
- }
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ",
- "Ant PG number/ Ant mechanism:",
- board_info->pg_ant_num, board_info->btdm_ant_num);
- CL_PRINTF(cli_buf);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %d_%d/ 0x%x/ 0x%x(%d)",
- "CoexVer/ FwVer/ PatchVer",
- glcoex_ver_date_8192e_2ant, glcoex_ver_8192e_2ant, fw_ver,
- bt_patch_ver, bt_patch_ver);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ",
- "Wifi channel informed to BT",
- coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
- coex_dm->wifi_chnl_info[2]);
- CL_PRINTF(cli_buf);
-
- /* wifi status */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Wifi Status]============");
- CL_PRINTF(cli_buf);
- btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[BT Status]============");
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ",
- "BT [status/ rssi/ retryCnt]",
- ((coex_sta->bt_disabled) ? ("disabled") : ((
- coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan")
- : ((BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
- coex_dm->bt_status) ? "non-connected idle" :
- ((BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)
- ? "connected-idle" : "busy")))),
- coex_sta->bt_rssi, coex_sta->bt_retry_cnt);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d",
- "SCO/HID/PAN/A2DP",
- stack_info->sco_exist, stack_info->hid_exist,
- stack_info->pan_exist, stack_info->a2dp_exist);
- CL_PRINTF(cli_buf);
- btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_BT_LINK_INFO);
-
- bt_info_ext = coex_sta->bt_info_ext;
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
- "BT Info A2DP rate",
- (bt_info_ext & BIT(0)) ? "Basic rate" : "EDR rate");
- CL_PRINTF(cli_buf);
-
- for (i = 0; i < BT_INFO_SRC_8192E_2ANT_MAX; i++) {
- if (coex_sta->bt_info_c2h_cnt[i]) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)",
- glbt_info_src_8192e_2ant[i],
- coex_sta->bt_info_c2h[i][0],
- coex_sta->bt_info_c2h[i][1],
- coex_sta->bt_info_c2h[i][2],
- coex_sta->bt_info_c2h[i][3],
- coex_sta->bt_info_c2h[i][4],
- coex_sta->bt_info_c2h[i][5],
- coex_sta->bt_info_c2h[i][6],
- coex_sta->bt_info_c2h_cnt[i]);
- CL_PRINTF(cli_buf);
- }
- }
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ", "SS Type",
- coex_dm->cur_ss_type);
- CL_PRINTF(cli_buf);
-
- /* Sw mechanism */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Sw mechanism]============");
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ",
- "SM1[ShRf/ LpRA/ LimDig]",
- coex_dm->cur_rf_rx_lpf_shrink, coex_dm->cur_low_penalty_ra,
- coex_dm->limited_dig);
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ",
- "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]",
- coex_dm->cur_agc_table_en, coex_dm->cur_adc_back_off,
- coex_dm->cur_dac_swing_on, coex_dm->cur_dac_swing_lvl);
- CL_PRINTF(cli_buf);
-
- /* Fw mechanism */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Fw mechanism]============");
- CL_PRINTF(cli_buf);
-
- ps_tdma_case = coex_dm->cur_ps_tdma;
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (auto:%d)",
- "PS TDMA",
- coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],
- coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],
- coex_dm->ps_tdma_para[4], ps_tdma_case,
- coex_dm->auto_tdma_adjust);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ",
- "DecBtPwr/ IgnWlanAct",
- coex_dm->cur_bt_dec_pwr_lvl, coex_dm->cur_ignore_wlan_act);
- CL_PRINTF(cli_buf);
-
- /* Hw setting */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Hw setting]============");
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x",
- "RF-A, 0x1e initVal",
- coex_dm->bt_rf_0x1e_backup);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x",
- "backup ARFR1/ARFR2/RL/AMaxTime",
- coex_dm->backup_arfr_cnt1, coex_dm->backup_arfr_cnt2,
- coex_dm->backup_retry_limit,
- coex_dm->backup_ampdu_max_time);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434);
- u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x",
- "0x430/0x434/0x42a/0x456",
- u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc04);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xd04);
- u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x90c);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
- "0xc04/ 0xd04/ 0x90c",
- u32tmp[0], u32tmp[1], u32tmp[2]);
- CL_PRINTF(cli_buf);
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x778",
- u8tmp[0]);
- CL_PRINTF(cli_buf);
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x92c);
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x930);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
- "0x92c/ 0x930",
- (u8tmp[0]), u32tmp[0]);
- CL_PRINTF(cli_buf);
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x40);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x4f);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
- "0x40/ 0x4f",
- u8tmp[0], u8tmp[1]);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
- "0x550(bcn ctrl)/0x522",
- u32tmp[0], u8tmp[0]);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)",
- u32tmp[0]);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
- u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x6cc);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
- "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)",
- u32tmp[0], u32tmp[1], u32tmp[2], u8tmp[0]);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
- "0x770(hp rx[31:16]/tx[15:0])",
- coex_sta->high_priority_rx, coex_sta->high_priority_tx);
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
- "0x774(lp rx[31:16]/tx[15:0])",
- coex_sta->low_priority_rx, coex_sta->low_priority_tx);
- CL_PRINTF(cli_buf);
-#if (BT_AUTO_REPORT_ONLY_8192E_2ANT == 1)
- halbtc8192e2ant_monitor_bt_ctr(btcoexist);
-#endif
- btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
-}
-
-
-void ex_halbtc8192e2ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type)
-{
- if (BTC_IPS_ENTER == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], IPS ENTER notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_ips = true;
- halbtc8192e2ant_coex_all_off(btcoexist);
- halbtc8192e2ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false,
- true);
- } else if (BTC_IPS_LEAVE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], IPS LEAVE notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_ips = false;
- }
-}
-
-void ex_halbtc8192e2ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type)
-{
- if (BTC_LPS_ENABLE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], LPS ENABLE notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_lps = true;
- } else if (BTC_LPS_DISABLE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], LPS DISABLE notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_lps = false;
- }
-}
-
-void ex_halbtc8192e2ant_scan_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- if (BTC_SCAN_START == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCAN START notify\n");
- BTC_TRACE(trace_buf);
- } else if (BTC_SCAN_FINISH == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCAN FINISH notify\n");
- BTC_TRACE(trace_buf);
- }
-}
-
-void ex_halbtc8192e2ant_connect_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- if (BTC_ASSOCIATE_START == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CONNECT START notify\n");
- BTC_TRACE(trace_buf);
- } else if (BTC_ASSOCIATE_FINISH == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CONNECT FINISH notify\n");
- BTC_TRACE(trace_buf);
- }
-}
-
-void ex_halbtc8192e2ant_media_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- u8 h2c_parameter[3] = {0};
- u32 wifi_bw;
- u8 wifi_central_chnl;
-
- if (btcoexist->manual_control ||
- btcoexist->stop_coex_dm ||
- coex_sta->bt_disabled)
- return;
-
- if (BTC_MEDIA_CONNECT == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], MEDIA connect notify\n");
- BTC_TRACE(trace_buf);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], MEDIA disconnect notify\n");
- BTC_TRACE(trace_buf);
- }
-
- /* only 2.4G we need to inform bt the chnl mask */
- btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
- &wifi_central_chnl);
- if ((BTC_MEDIA_CONNECT == type) &&
- (wifi_central_chnl <= 14)) {
- h2c_parameter[0] = 0x1;
- h2c_parameter[1] = wifi_central_chnl;
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- if (BTC_WIFI_BW_HT40 == wifi_bw)
- h2c_parameter[2] = 0x30;
- else
- h2c_parameter[2] = 0x20;
- }
-
- coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
- coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
- coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
-
- btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter);
-}
-
-void ex_halbtc8192e2ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- if (type == BTC_PACKET_DHCP) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], DHCP Packet notify\n");
- BTC_TRACE(trace_buf);
- }
-}
-
-void ex_halbtc8192e2ant_bt_info_notify(IN struct btc_coexist *btcoexist,
- IN u8 *tmp_buf, IN u8 length)
-{
- u8 bt_info = 0;
- u8 i, rsp_source = 0;
- boolean bt_busy = false, limited_dig = false;
- boolean wifi_connected = false;
-
- coex_sta->c2h_bt_info_req_sent = false;
-
- rsp_source = tmp_buf[0] & 0xf;
- if (rsp_source >= BT_INFO_SRC_8192E_2ANT_MAX)
- rsp_source = BT_INFO_SRC_8192E_2ANT_WIFI_FW;
- coex_sta->bt_info_c2h_cnt[rsp_source]++;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source,
- length);
- BTC_TRACE(trace_buf);
- for (i = 0; i < length; i++) {
- coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
- if (i == 1)
- bt_info = tmp_buf[i];
- if (i == length - 1) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n",
- tmp_buf[i]);
- BTC_TRACE(trace_buf);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ",
- tmp_buf[i]);
- BTC_TRACE(trace_buf);
- }
- }
-
- if (BT_INFO_SRC_8192E_2ANT_WIFI_FW != rsp_source) {
- coex_sta->bt_retry_cnt = /* [3:0] */
- coex_sta->bt_info_c2h[rsp_source][2] & 0xf;
-
- coex_sta->bt_rssi =
- coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10;
-
- coex_sta->bt_info_ext =
- coex_sta->bt_info_c2h[rsp_source][4];
-
- /* Here we need to resend some wifi info to BT */
- /* because bt is reset and loss of the info. */
- if ((coex_sta->bt_info_ext & BIT(1))) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- if (wifi_connected)
- ex_halbtc8192e2ant_media_status_notify(
- btcoexist, BTC_MEDIA_CONNECT);
- else
- ex_halbtc8192e2ant_media_status_notify(
- btcoexist, BTC_MEDIA_DISCONNECT);
- }
-
- if ((coex_sta->bt_info_ext & BIT(3))) {
- if (!btcoexist->manual_control &&
- !btcoexist->stop_coex_dm) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n");
- BTC_TRACE(trace_buf);
- halbtc8192e2ant_ignore_wlan_act(btcoexist,
- FORCE_EXEC, false);
- }
- } else {
- /* BT already NOT ignore Wlan active, do nothing here. */
- }
-
-#if (BT_AUTO_REPORT_ONLY_8192E_2ANT == 0)
- if ((coex_sta->bt_info_ext & BIT(4))) {
- /* BT auto report already enabled, do nothing */
- } else
- halbtc8192e2ant_bt_auto_report(btcoexist, FORCE_EXEC,
- true);
-#endif
- }
-
- /* check BIT2 first ==> check if bt is under inquiry or page scan */
- if (bt_info & BT_INFO_8192E_2ANT_B_INQ_PAGE)
- coex_sta->c2h_bt_inquiry_page = true;
- else
- coex_sta->c2h_bt_inquiry_page = false;
-
- /* set link exist status */
- if (!(bt_info & BT_INFO_8192E_2ANT_B_CONNECTION)) {
- coex_sta->bt_link_exist = false;
- coex_sta->pan_exist = false;
- coex_sta->a2dp_exist = false;
- coex_sta->hid_exist = false;
- coex_sta->sco_exist = false;
- } else { /* connection exists */
- coex_sta->bt_link_exist = true;
- if (bt_info & BT_INFO_8192E_2ANT_B_FTP)
- coex_sta->pan_exist = true;
- else
- coex_sta->pan_exist = false;
- if (bt_info & BT_INFO_8192E_2ANT_B_A2DP)
- coex_sta->a2dp_exist = true;
- else
- coex_sta->a2dp_exist = false;
- if (bt_info & BT_INFO_8192E_2ANT_B_HID)
- coex_sta->hid_exist = true;
- else
- coex_sta->hid_exist = false;
- if (bt_info & BT_INFO_8192E_2ANT_B_SCO_ESCO)
- coex_sta->sco_exist = true;
- else
- coex_sta->sco_exist = false;
- }
-
- halbtc8192e2ant_update_bt_link_info(btcoexist);
-
- if (!(bt_info & BT_INFO_8192E_2ANT_B_CONNECTION)) {
- coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n");
- BTC_TRACE(trace_buf);
- } else if (bt_info ==
- BT_INFO_8192E_2ANT_B_CONNECTION) { /* connection exists but no busy */
- coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n");
- BTC_TRACE(trace_buf);
- } else if ((bt_info & BT_INFO_8192E_2ANT_B_SCO_ESCO) ||
- (bt_info & BT_INFO_8192E_2ANT_B_SCO_BUSY)) {
- coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_SCO_BUSY;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n");
- BTC_TRACE(trace_buf);
- } else if (bt_info & BT_INFO_8192E_2ANT_B_ACL_BUSY) {
- coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_ACL_BUSY;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n");
- BTC_TRACE(trace_buf);
- } else {
- coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_MAX;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n");
- BTC_TRACE(trace_buf);
- }
-
- if ((BT_8192E_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
- (BT_8192E_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
- (BT_8192E_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) {
- bt_busy = true;
- limited_dig = true;
- } else {
- bt_busy = false;
- limited_dig = false;
- }
-
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
-
- coex_dm->limited_dig = limited_dig;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_LIMITED_DIG, &limited_dig);
-
- halbtc8192e2ant_run_coexist_mechanism(btcoexist);
-}
-
-void ex_halbtc8192e2ant_halt_notify(IN struct btc_coexist *btcoexist)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n");
- BTC_TRACE(trace_buf);
-
- halbtc8192e2ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false, true);
- halbtc8192e2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
- ex_halbtc8192e2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
-}
-
-void ex_halbtc8192e2ant_periodical(IN struct btc_coexist *btcoexist)
-{
-#if (BT_AUTO_REPORT_ONLY_8192E_2ANT == 0)
- halbtc8192e2ant_query_bt_info(btcoexist);
- halbtc8192e2ant_monitor_bt_ctr(btcoexist);
- halbtc8192e2ant_monitor_bt_enable_disable(btcoexist);
-#else
- if (halbtc8192e2ant_is_wifi_status_changed(btcoexist) ||
- coex_dm->auto_tdma_adjust)
- halbtc8192e2ant_run_coexist_mechanism(btcoexist);
-#endif
-}
-
-#endif
-
-#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */
-
diff --git a/hal/btc/HalBtc8192e2Ant.h b/hal/btc/HalBtc8192e2Ant.h
deleted file mode 100644
index 5a4786a..0000000
--- a/hal/btc/HalBtc8192e2Ant.h
+++ /dev/null
@@ -1,190 +0,0 @@
-
-#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
-
-#if (RTL8192E_SUPPORT == 1)
-/* *******************************************
- * The following is for 8192E 2Ant BT Co-exist definition
- * ******************************************* */
-#define BT_AUTO_REPORT_ONLY_8192E_2ANT 0
-
-#define BT_INFO_8192E_2ANT_B_FTP BIT(7)
-#define BT_INFO_8192E_2ANT_B_A2DP BIT(6)
-#define BT_INFO_8192E_2ANT_B_HID BIT(5)
-#define BT_INFO_8192E_2ANT_B_SCO_BUSY BIT(4)
-#define BT_INFO_8192E_2ANT_B_ACL_BUSY BIT(3)
-#define BT_INFO_8192E_2ANT_B_INQ_PAGE BIT(2)
-#define BT_INFO_8192E_2ANT_B_SCO_ESCO BIT(1)
-#define BT_INFO_8192E_2ANT_B_CONNECTION BIT(0)
-
-#define BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT 2
-
-enum bt_info_src_8192e_2ant {
- BT_INFO_SRC_8192E_2ANT_WIFI_FW = 0x0,
- BT_INFO_SRC_8192E_2ANT_BT_RSP = 0x1,
- BT_INFO_SRC_8192E_2ANT_BT_ACTIVE_SEND = 0x2,
- BT_INFO_SRC_8192E_2ANT_MAX
-};
-
-enum bt_8192e_2ant_bt_status {
- BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
- BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
- BT_8192E_2ANT_BT_STATUS_INQ_PAGE = 0x2,
- BT_8192E_2ANT_BT_STATUS_ACL_BUSY = 0x3,
- BT_8192E_2ANT_BT_STATUS_SCO_BUSY = 0x4,
- BT_8192E_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
- BT_8192E_2ANT_BT_STATUS_MAX
-};
-
-enum bt_8192e_2ant_coex_algo {
- BT_8192E_2ANT_COEX_ALGO_UNDEFINED = 0x0,
- BT_8192E_2ANT_COEX_ALGO_SCO = 0x1,
- BT_8192E_2ANT_COEX_ALGO_SCO_PAN = 0x2,
- BT_8192E_2ANT_COEX_ALGO_HID = 0x3,
- BT_8192E_2ANT_COEX_ALGO_A2DP = 0x4,
- BT_8192E_2ANT_COEX_ALGO_A2DP_PANHS = 0x5,
- BT_8192E_2ANT_COEX_ALGO_PANEDR = 0x6,
- BT_8192E_2ANT_COEX_ALGO_PANHS = 0x7,
- BT_8192E_2ANT_COEX_ALGO_PANEDR_A2DP = 0x8,
- BT_8192E_2ANT_COEX_ALGO_PANEDR_HID = 0x9,
- BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0xa,
- BT_8192E_2ANT_COEX_ALGO_HID_A2DP = 0xb,
- BT_8192E_2ANT_COEX_ALGO_MAX = 0xc
-};
-
-struct coex_dm_8192e_2ant {
- /* fw mechanism */
- u8 pre_bt_dec_pwr_lvl;
- u8 cur_bt_dec_pwr_lvl;
- u8 pre_fw_dac_swing_lvl;
- u8 cur_fw_dac_swing_lvl;
- boolean cur_ignore_wlan_act;
- boolean pre_ignore_wlan_act;
- u8 pre_ps_tdma;
- u8 cur_ps_tdma;
- u8 ps_tdma_para[5];
- u8 ps_tdma_du_adj_type;
- boolean reset_tdma_adjust;
- boolean auto_tdma_adjust;
- boolean pre_ps_tdma_on;
- boolean cur_ps_tdma_on;
- boolean pre_bt_auto_report;
- boolean cur_bt_auto_report;
-
- /* sw mechanism */
- boolean pre_rf_rx_lpf_shrink;
- boolean cur_rf_rx_lpf_shrink;
- u32 bt_rf_0x1e_backup;
- boolean pre_low_penalty_ra;
- boolean cur_low_penalty_ra;
- boolean pre_dac_swing_on;
- u32 pre_dac_swing_lvl;
- boolean cur_dac_swing_on;
- u32 cur_dac_swing_lvl;
- boolean pre_adc_back_off;
- boolean cur_adc_back_off;
- boolean pre_agc_table_en;
- boolean cur_agc_table_en;
- u32 pre_val0x6c0;
- u32 cur_val0x6c0;
- u32 pre_val0x6c4;
- u32 cur_val0x6c4;
- u32 pre_val0x6c8;
- u32 cur_val0x6c8;
- u8 pre_val0x6cc;
- u8 cur_val0x6cc;
- boolean limited_dig;
-
- u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */
- u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */
- u16 backup_retry_limit;
- u8 backup_ampdu_max_time;
-
- /* algorithm related */
- u8 pre_algorithm;
- u8 cur_algorithm;
- u8 bt_status;
- u8 wifi_chnl_info[3];
-
- u8 pre_ss_type;
- u8 cur_ss_type;
-
- u32 pre_ra_mask;
- u32 cur_ra_mask;
- u8 cur_ra_mask_type;
- u8 pre_arfr_type;
- u8 cur_arfr_type;
- u8 pre_retry_limit_type;
- u8 cur_retry_limit_type;
- u8 pre_ampdu_time_type;
- u8 cur_ampdu_time_type;
-};
-
-struct coex_sta_8192e_2ant {
- boolean bt_disabled;
- boolean bt_link_exist;
- boolean sco_exist;
- boolean a2dp_exist;
- boolean hid_exist;
- boolean pan_exist;
-
- boolean under_lps;
- boolean under_ips;
- u32 high_priority_tx;
- u32 high_priority_rx;
- u32 low_priority_tx;
- u32 low_priority_rx;
- u8 bt_rssi;
- u8 pre_bt_rssi_state;
- u8 pre_wifi_rssi_state[4];
- boolean c2h_bt_info_req_sent;
- u8 bt_info_c2h[BT_INFO_SRC_8192E_2ANT_MAX][10];
- u32 bt_info_c2h_cnt[BT_INFO_SRC_8192E_2ANT_MAX];
- boolean c2h_bt_inquiry_page;
- u8 bt_retry_cnt;
- u8 bt_info_ext;
-};
-
-/* *******************************************
- * The following is interface which will notify coex module.
- * ******************************************* */
-void ex_halbtc8192e2ant_power_on_setting(IN struct btc_coexist *btcoexist);
-void ex_halbtc8192e2ant_init_hw_config(IN struct btc_coexist *btcoexist,
- IN boolean wifi_only);
-void ex_halbtc8192e2ant_init_coex_dm(IN struct btc_coexist *btcoexist);
-void ex_halbtc8192e2ant_ips_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8192e2ant_lps_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8192e2ant_scan_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8192e2ant_connect_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8192e2ant_media_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8192e2ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8192e2ant_bt_info_notify(IN struct btc_coexist *btcoexist,
- IN u8 *tmp_buf, IN u8 length);
-void ex_halbtc8192e2ant_halt_notify(IN struct btc_coexist *btcoexist);
-void ex_halbtc8192e2ant_periodical(IN struct btc_coexist *btcoexist);
-void ex_halbtc8192e2ant_display_coex_info(IN struct btc_coexist *btcoexist);
-
-#else /* #if (RTL8192E_SUPPORT == 1) */
-#define ex_halbtc8192e2ant_power_on_setting(btcoexist)
-#define ex_halbtc8192e2ant_init_hw_config(btcoexist, wifi_only)
-#define ex_halbtc8192e2ant_init_coex_dm(btcoexist)
-#define ex_halbtc8192e2ant_ips_notify(btcoexist, type)
-#define ex_halbtc8192e2ant_lps_notify(btcoexist, type)
-#define ex_halbtc8192e2ant_scan_notify(btcoexist, type)
-#define ex_halbtc8192e2ant_connect_notify(btcoexist, type)
-#define ex_halbtc8192e2ant_media_status_notify(btcoexist, type)
-#define ex_halbtc8192e2ant_specific_packet_notify(btcoexist, type)
-#define ex_halbtc8192e2ant_bt_info_notify(btcoexist, tmp_buf, length)
-#define ex_halbtc8192e2ant_halt_notify(btcoexist)
-#define ex_halbtc8192e2ant_periodical(btcoexist)
-#define ex_halbtc8192e2ant_display_coex_info(btcoexist)
-
-#endif
-
-#endif
-
diff --git a/hal/btc/HalBtc8703b1Ant.c b/hal/btc/HalBtc8703b1Ant.c
deleted file mode 100644
index 0225669..0000000
--- a/hal/btc/HalBtc8703b1Ant.c
+++ /dev/null
@@ -1,4592 +0,0 @@
-/* ************************************************************
- * Description:
- *
- * This file is for RTL8703B Co-exist mechanism
- *
- * History
- * 2012/11/15 Cosa first check in.
- *
- * ************************************************************ */
-
-/* ************************************************************
- * include files
- * ************************************************************ */
-#include "Mp_Precomp.h"
-
-#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
-
-#if (RTL8703B_SUPPORT == 1)
-/* ************************************************************
- * Global variables, these are static variables
- * ************************************************************ */
-static u8 *trace_buf = &gl_btc_trace_buf[0];
-static struct coex_dm_8703b_1ant glcoex_dm_8703b_1ant;
-static struct coex_dm_8703b_1ant *coex_dm = &glcoex_dm_8703b_1ant;
-static struct coex_sta_8703b_1ant glcoex_sta_8703b_1ant;
-static struct coex_sta_8703b_1ant *coex_sta = &glcoex_sta_8703b_1ant;
-static struct psdscan_sta_8703b_1ant gl_psd_scan_8703b_1ant;
-static struct psdscan_sta_8703b_1ant *psd_scan = &gl_psd_scan_8703b_1ant;
-
-
-const char *const glbt_info_src_8703b_1ant[] = {
- "BT Info[wifi fw]",
- "BT Info[bt rsp]",
- "BT Info[bt auto report]",
-};
-
-u32 glcoex_ver_date_8703b_1ant = 20160218;
-u32 glcoex_ver_8703b_1ant = 0x09;
-
-/* ************************************************************
- * local function proto type if needed
- * ************************************************************
- * ************************************************************
- * local function start with halbtc8703b1ant_
- * ************************************************************ */
-u8 halbtc8703b1ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1)
-{
- s32 bt_rssi = 0;
- u8 bt_rssi_state = coex_sta->pre_bt_rssi_state;
-
- bt_rssi = coex_sta->bt_rssi;
-
- if (level_num == 2) {
- if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
- (coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (bt_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT))
- bt_rssi_state = BTC_RSSI_STATE_HIGH;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else {
- if (bt_rssi < rssi_thresh)
- bt_rssi_state = BTC_RSSI_STATE_LOW;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- } else if (level_num == 3) {
- if (rssi_thresh > rssi_thresh1) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Rssi thresh error!!\n");
- BTC_TRACE(trace_buf);
- return coex_sta->pre_bt_rssi_state;
- }
-
- if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
- (coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (bt_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT))
- bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else if ((coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_MEDIUM) ||
- (coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_STAY_MEDIUM)) {
- if (bt_rssi >= (rssi_thresh1 +
- BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT))
- bt_rssi_state = BTC_RSSI_STATE_HIGH;
- else if (bt_rssi < rssi_thresh)
- bt_rssi_state = BTC_RSSI_STATE_LOW;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
- } else {
- if (bt_rssi < rssi_thresh1)
- bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- }
-
- coex_sta->pre_bt_rssi_state = bt_rssi_state;
-
- return bt_rssi_state;
-}
-
-u8 halbtc8703b1ant_wifi_rssi_state(IN struct btc_coexist *btcoexist,
- IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1)
-{
- s32 wifi_rssi = 0;
- u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index];
-
- btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
-
- if (level_num == 2) {
- if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
- ||
- (coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (wifi_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT))
- wifi_rssi_state = BTC_RSSI_STATE_HIGH;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else {
- if (wifi_rssi < rssi_thresh)
- wifi_rssi_state = BTC_RSSI_STATE_LOW;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- } else if (level_num == 3) {
- if (rssi_thresh > rssi_thresh1) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], wifi RSSI thresh error!!\n");
- BTC_TRACE(trace_buf);
- return coex_sta->pre_wifi_rssi_state[index];
- }
-
- if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
- ||
- (coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (wifi_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT))
- wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else if ((coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_MEDIUM) ||
- (coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_STAY_MEDIUM)) {
- if (wifi_rssi >= (rssi_thresh1 +
- BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT))
- wifi_rssi_state = BTC_RSSI_STATE_HIGH;
- else if (wifi_rssi < rssi_thresh)
- wifi_rssi_state = BTC_RSSI_STATE_LOW;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
- } else {
- if (wifi_rssi < rssi_thresh1)
- wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- }
-
- coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state;
-
- return wifi_rssi_state;
-}
-
-void halbtc8703b1ant_update_ra_mask(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u32 dis_rate_mask)
-{
- coex_dm->cur_ra_mask = dis_rate_mask;
-
- if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask))
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK,
- &coex_dm->cur_ra_mask);
- coex_dm->pre_ra_mask = coex_dm->cur_ra_mask;
-}
-
-void halbtc8703b1ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- boolean wifi_under_b_mode = false;
-
- coex_dm->cur_arfr_type = type;
-
- if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) {
- switch (coex_dm->cur_arfr_type) {
- case 0: /* normal mode */
- btcoexist->btc_write_4byte(btcoexist, 0x430,
- coex_dm->backup_arfr_cnt1);
- btcoexist->btc_write_4byte(btcoexist, 0x434,
- coex_dm->backup_arfr_cnt2);
- break;
- case 1:
- btcoexist->btc_get(btcoexist,
- BTC_GET_BL_WIFI_UNDER_B_MODE,
- &wifi_under_b_mode);
- if (wifi_under_b_mode) {
- btcoexist->btc_write_4byte(btcoexist,
- 0x430, 0x0);
- btcoexist->btc_write_4byte(btcoexist,
- 0x434, 0x01010101);
- } else {
- btcoexist->btc_write_4byte(btcoexist,
- 0x430, 0x0);
- btcoexist->btc_write_4byte(btcoexist,
- 0x434, 0x04030201);
- }
- break;
- default:
- break;
- }
- }
-
- coex_dm->pre_arfr_type = coex_dm->cur_arfr_type;
-}
-
-void halbtc8703b1ant_retry_limit(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- coex_dm->cur_retry_limit_type = type;
-
- if (force_exec ||
- (coex_dm->pre_retry_limit_type !=
- coex_dm->cur_retry_limit_type)) {
- switch (coex_dm->cur_retry_limit_type) {
- case 0: /* normal mode */
- btcoexist->btc_write_2byte(btcoexist, 0x42a,
- coex_dm->backup_retry_limit);
- break;
- case 1: /* retry limit=8 */
- btcoexist->btc_write_2byte(btcoexist, 0x42a,
- 0x0808);
- break;
- default:
- break;
- }
- }
-
- coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type;
-}
-
-void halbtc8703b1ant_ampdu_max_time(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- coex_dm->cur_ampdu_time_type = type;
-
- if (force_exec ||
- (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) {
- switch (coex_dm->cur_ampdu_time_type) {
- case 0: /* normal mode */
- btcoexist->btc_write_1byte(btcoexist, 0x456,
- coex_dm->backup_ampdu_max_time);
- break;
- case 1: /* AMPDU timw = 0x38 * 32us */
- btcoexist->btc_write_1byte(btcoexist, 0x456,
- 0x38);
- break;
- default:
- break;
- }
- }
-
- coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type;
-}
-
-void halbtc8703b1ant_limited_tx(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type,
- IN u8 retry_limit_type, IN u8 ampdu_time_type)
-{
- switch (ra_mask_type) {
- case 0: /* normal mode */
- halbtc8703b1ant_update_ra_mask(btcoexist, force_exec,
- 0x0);
- break;
- case 1: /* disable cck 1/2 */
- halbtc8703b1ant_update_ra_mask(btcoexist, force_exec,
- 0x00000003);
- break;
- case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */
- halbtc8703b1ant_update_ra_mask(btcoexist, force_exec,
- 0x0001f1f7);
- break;
- default:
- break;
- }
-
- halbtc8703b1ant_auto_rate_fallback_retry(btcoexist, force_exec,
- arfr_type);
- halbtc8703b1ant_retry_limit(btcoexist, force_exec, retry_limit_type);
- halbtc8703b1ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type);
-}
-
-void halbtc8703b1ant_limited_rx(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean rej_ap_agg_pkt,
- IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size)
-{
- boolean reject_rx_agg = rej_ap_agg_pkt;
- boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size;
- u8 rx_agg_size = agg_buf_size;
-
- /* ============================================ */
- /* Rx Aggregation related setting */
- /* ============================================ */
- btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT,
- &reject_rx_agg);
- /* decide BT control aggregation buf size or not */
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE,
- &bt_ctrl_rx_agg_size);
- /* aggregation buf size, only work when BT control Rx aggregation size. */
- btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size);
- /* real update aggregation setting */
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
-
-
-}
-
-void halbtc8703b1ant_query_bt_info(IN struct btc_coexist *btcoexist)
-{
- u8 h2c_parameter[1] = {0};
-
- coex_sta->c2h_bt_info_req_sent = true;
-
- h2c_parameter[0] |= BIT(0); /* trigger */
-
- btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter);
-}
-
-void halbtc8703b1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist)
-{
- u32 reg_hp_txrx, reg_lp_txrx, u32tmp;
- u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
- static u8 num_of_bt_counter_chk = 0, cnt_slave = 0;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
- /* to avoid 0x76e[3] = 1 (WLAN_Act control by PTA) during IPS */
- /* if (! (btcoexist->btc_read_1byte(btcoexist, 0x76e) & 0x8) ) */
-
- reg_hp_txrx = 0x770;
- reg_lp_txrx = 0x774;
-
- u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
- reg_hp_tx = u32tmp & MASKLWORD;
- reg_hp_rx = (u32tmp & MASKHWORD) >> 16;
-
- u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
- reg_lp_tx = u32tmp & MASKLWORD;
- reg_lp_rx = (u32tmp & MASKHWORD) >> 16;
-
- coex_sta->high_priority_tx = reg_hp_tx;
- coex_sta->high_priority_rx = reg_hp_rx;
- coex_sta->low_priority_tx = reg_lp_tx;
- coex_sta->low_priority_rx = reg_lp_rx;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n",
- reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx);
-
- BTC_TRACE(trace_buf);
-
- /* reset counter */
- btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
-
- if ((coex_sta->low_priority_tx > 1150) &&
- (!coex_sta->c2h_bt_inquiry_page))
- coex_sta->pop_event_cnt++;
-
- if ((coex_sta->low_priority_rx >= 1150) && (coex_sta->low_priority_rx >= coex_sta->low_priority_tx)
- && (!coex_sta->under_ips) && (!coex_sta->c2h_bt_inquiry_page) && (coex_sta->bt_link_exist)) {
- if (cnt_slave >= 3) {
- bt_link_info->slave_role = true;
- cnt_slave = 3;
- } else
- cnt_slave++;
- } else {
- if (cnt_slave == 0) {
- bt_link_info->slave_role = false;
- cnt_slave = 0;
- } else
- cnt_slave--;
-
- }
-
- if ((coex_sta->high_priority_tx == 0) && (coex_sta->high_priority_rx == 0) && (coex_sta->low_priority_tx == 0) &&
- (coex_sta->low_priority_rx == 0)) {
- num_of_bt_counter_chk++;
- if (num_of_bt_counter_chk >= 3) {
- halbtc8703b1ant_query_bt_info(btcoexist);
- num_of_bt_counter_chk = 0;
- }
- }
-
-
-#if 0
- /* Add Hi-Pri Tx/Rx counter to avoid false detection */
- if (((coex_sta->hid_exist) || (coex_sta->sco_exist)) &&
- (coex_sta->high_priority_tx + coex_sta->high_priority_rx
- >= 160)
- && (!coex_sta->c2h_bt_inquiry_page))
- coex_sta->bt_hi_pri_link_exist = true;
- else
- coex_sta->bt_hi_pri_link_exist = false;
-
- if ((coex_sta->acl_busy) &&
- (coex_sta->num_of_profile == 0)) {
- if (coex_sta->low_priority_tx +
- coex_sta->low_priority_rx >= 160) {
- coex_sta->pan_exist = true;
- coex_sta->num_of_profile++;
- coex_sta->wrong_profile_notification++;
- }
- }
-#endif
-
-}
-
-
-void halbtc8703b1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist)
-{
- s32 wifi_rssi = 0;
- boolean wifi_busy = false, wifi_under_b_mode = false;
- static u8 cck_lock_counter = 0;
- u32 total_cnt;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
- &wifi_under_b_mode);
-
- if (coex_sta->under_ips) {
- coex_sta->crc_ok_cck = 0;
- coex_sta->crc_ok_11g = 0;
- coex_sta->crc_ok_11n = 0;
- coex_sta->crc_ok_11n_agg = 0;
-
- coex_sta->crc_err_cck = 0;
- coex_sta->crc_err_11g = 0;
- coex_sta->crc_err_11n = 0;
- coex_sta->crc_err_11n_agg = 0;
- } else {
- coex_sta->crc_ok_cck = btcoexist->btc_read_4byte(btcoexist,
- 0xf88);
- coex_sta->crc_ok_11g = btcoexist->btc_read_2byte(btcoexist,
- 0xf94);
- coex_sta->crc_ok_11n = btcoexist->btc_read_2byte(btcoexist,
- 0xf90);
- coex_sta->crc_ok_11n_agg = btcoexist->btc_read_2byte(btcoexist,
- 0xfb8);
-
- coex_sta->crc_err_cck = btcoexist->btc_read_4byte(btcoexist,
- 0xf84);
- coex_sta->crc_err_11g = btcoexist->btc_read_2byte(btcoexist,
- 0xf96);
- coex_sta->crc_err_11n = btcoexist->btc_read_2byte(btcoexist,
- 0xf92);
- coex_sta->crc_err_11n_agg = btcoexist->btc_read_2byte(btcoexist,
- 0xfba);
- }
-
-
- /* reset counter */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xf16, 0x1, 0x1);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xf16, 0x1, 0x0);
-
- if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) {
- total_cnt = coex_sta->crc_ok_cck + coex_sta->crc_ok_11g +
- coex_sta->crc_ok_11n +
- coex_sta->crc_ok_11n_agg;
-
- if ((coex_dm->bt_status == BT_8703B_1ANT_BT_STATUS_ACL_BUSY) ||
- (coex_dm->bt_status ==
- BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY) ||
- (coex_dm->bt_status ==
- BT_8703B_1ANT_BT_STATUS_SCO_BUSY)) {
- if (coex_sta->crc_ok_cck > (total_cnt -
- coex_sta->crc_ok_cck)) {
- if (cck_lock_counter < 3)
- cck_lock_counter++;
- } else {
- if (cck_lock_counter > 0)
- cck_lock_counter--;
- }
-
- } else {
- if (cck_lock_counter > 0)
- cck_lock_counter--;
- }
- } else {
- if (cck_lock_counter > 0)
- cck_lock_counter--;
- }
-
- if (!coex_sta->pre_ccklock) {
-
- if (cck_lock_counter >= 3)
- coex_sta->cck_lock = true;
- else
- coex_sta->cck_lock = false;
- } else {
- if (cck_lock_counter == 0)
- coex_sta->cck_lock = false;
- else
- coex_sta->cck_lock = true;
- }
-
- if (coex_sta->cck_lock)
- coex_sta->cck_ever_lock = true;
-
- coex_sta->pre_ccklock = coex_sta->cck_lock;
-
-
-}
-
-boolean halbtc8703b1ant_is_wifibt_status_changed(IN struct btc_coexist *btcoexist)
-{
- static boolean pre_wifi_busy = false, pre_under_4way = false,
- pre_bt_hs_on = false, pre_bt_off = false;
- boolean wifi_busy = false, under_4way = false, bt_hs_on = false;
- boolean wifi_connected = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
- &under_4way);
-
- if (coex_sta->bt_disabled != pre_bt_off) {
- pre_bt_off = coex_sta->bt_disabled;
-
- if (coex_sta->bt_disabled)
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is disabled !!\n");
- else
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is enabled !!\n");
-
- BTC_TRACE(trace_buf);
- return true;
- }
-
- if (wifi_connected) {
- if (wifi_busy != pre_wifi_busy) {
- pre_wifi_busy = wifi_busy;
- return true;
- }
- if (under_4way != pre_under_4way) {
- pre_under_4way = under_4way;
- return true;
- }
- if (bt_hs_on != pre_bt_hs_on) {
- pre_bt_hs_on = bt_hs_on;
- return true;
- }
- }
-
- return false;
-}
-
-void halbtc8703b1ant_update_bt_link_info(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean bt_hs_on = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
-
- bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
- bt_link_info->sco_exist = coex_sta->sco_exist;
- bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
- bt_link_info->pan_exist = coex_sta->pan_exist;
- bt_link_info->hid_exist = coex_sta->hid_exist;
- bt_link_info->bt_hi_pri_link_exist = coex_sta->bt_hi_pri_link_exist;
- bt_link_info->acl_busy = coex_sta->acl_busy;
-
- /* work around for HS mode. */
- if (bt_hs_on) {
- bt_link_info->pan_exist = true;
- bt_link_info->bt_link_exist = true;
- }
-
- /* check if Sco only */
- if (bt_link_info->sco_exist &&
- !bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist &&
- !bt_link_info->hid_exist)
- bt_link_info->sco_only = true;
- else
- bt_link_info->sco_only = false;
-
- /* check if A2dp only */
- if (!bt_link_info->sco_exist &&
- bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist &&
- !bt_link_info->hid_exist)
- bt_link_info->a2dp_only = true;
- else
- bt_link_info->a2dp_only = false;
-
- /* check if Pan only */
- if (!bt_link_info->sco_exist &&
- !bt_link_info->a2dp_exist &&
- bt_link_info->pan_exist &&
- !bt_link_info->hid_exist)
- bt_link_info->pan_only = true;
- else
- bt_link_info->pan_only = false;
-
- /* check if Hid only */
- if (!bt_link_info->sco_exist &&
- !bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist &&
- bt_link_info->hid_exist)
- bt_link_info->hid_only = true;
- else
- bt_link_info->hid_only = false;
-}
-
-void halbtc8703b1ant_update_wifi_channel_info(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- u8 h2c_parameter[3] = {0};
- u32 wifi_bw;
- u8 wifi_central_chnl;
-
- /* only 2.4G we need to inform bt the chnl mask */
- btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
- &wifi_central_chnl);
- if ((BTC_MEDIA_CONNECT == type) &&
- (wifi_central_chnl <= 14)) {
- h2c_parameter[0] =
- 0x1; /* enable BT AFH skip WL channel for 8703b because BT Rx LO interference */
- /* h2c_parameter[0] = 0x0; */
- h2c_parameter[1] = wifi_central_chnl;
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- if (BTC_WIFI_BW_HT40 == wifi_bw)
- h2c_parameter[2] = 0x30;
- else
- h2c_parameter[2] = 0x20;
- }
-
- coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
- coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
- coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
-
- btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter);
-
-}
-
-void halbtc8703b1ant_set_bt_auto_report(IN struct btc_coexist *btcoexist,
- IN boolean enable_auto_report)
-{
- u8 h2c_parameter[1] = {0};
-
- h2c_parameter[0] = 0;
-
- if (enable_auto_report)
- h2c_parameter[0] |= BIT(0);
-
- btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter);
-}
-
-void halbtc8703b1ant_bt_auto_report(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean enable_auto_report)
-{
- coex_dm->cur_bt_auto_report = enable_auto_report;
-
- if (!force_exec) {
- if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report)
- return;
- }
- halbtc8703b1ant_set_bt_auto_report(btcoexist,
- coex_dm->cur_bt_auto_report);
-
- coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report;
-}
-
-void halbtc8703b1ant_set_fw_low_penalty_ra(IN struct btc_coexist
- *btcoexist, IN boolean low_penalty_ra)
-{
- u8 h2c_parameter[6] = {0};
-
- h2c_parameter[0] = 0x6; /* op_code, 0x6= Retry_Penalty */
-
- if (low_penalty_ra) {
- h2c_parameter[1] |= BIT(0);
- h2c_parameter[2] =
- 0x00; /* normal rate except MCS7/6/5, OFDM54/48/36 */
- h2c_parameter[3] = 0xf7; /* MCS7 or OFDM54 */
- h2c_parameter[4] = 0xf8; /* MCS6 or OFDM48 */
- h2c_parameter[5] = 0xf9; /* MCS5 or OFDM36 */
- }
-
- btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter);
-}
-
-void halbtc8703b1ant_low_penalty_ra(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean low_penalty_ra)
-{
- coex_dm->cur_low_penalty_ra = low_penalty_ra;
-
- if (!force_exec) {
- if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra)
- return;
- }
- halbtc8703b1ant_set_fw_low_penalty_ra(btcoexist,
- coex_dm->cur_low_penalty_ra);
-
- coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra;
-}
-
-void halbtc8703b1ant_write_score_board(
- IN struct btc_coexist *btcoexist,
- IN u16 bitpos,
- IN BOOLEAN state
-)
-{
-
- static u16 originalval = 0x8002;
-
- if (state)
- originalval = originalval | bitpos;
- else
- originalval = originalval & (~bitpos);
-
-
- btcoexist->btc_write_2byte(btcoexist, 0xaa, originalval);
-#if 0
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "\n [BTCoex], ********** Write Scoreboard = %x**********\n",
- originalval);
- BTC_TRACE(trace_buf);
-#endif
-
-}
-
-void halbtc8703b1ant_read_score_board(
- IN struct btc_coexist *btcoexist,
- IN u16 *score_board_val
-)
-{
-
- *score_board_val = (btcoexist->btc_read_2byte(btcoexist,
- 0xaa)) & 0x7fff;
-}
-
-void halbtc8703b1ant_post_activestate_to_bt(
- IN struct btc_coexist *btcoexist,
- IN boolean wifi_active
-)
-{
-
- if (wifi_active)
- halbtc8703b1ant_write_score_board(btcoexist, (u16) BIT(0), TRUE);
- else
- halbtc8703b1ant_write_score_board(btcoexist, (u16) BIT(0), FALSE);
-
- /* The BT should set "No Shunt-down" mode if WL = Active for BT Synthesizer on/off interference WL Lo issue at 8703b b-cut. */
-
-}
-
-void halbtc8703b1ant_post_onoffState_to_bt(
- IN struct btc_coexist *btcoexist,
- IN boolean wifi_on
-)
-{
-
- if (wifi_on)
- halbtc8703b1ant_write_score_board(btcoexist, (u16) BIT(1), TRUE);
- else
- halbtc8703b1ant_write_score_board(btcoexist, (u16) BIT(1), FALSE);
-
-}
-
-void halbtc8703b1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist)
-{
- static u32 bt_disable_cnt = 0;
- boolean bt_active = true, bt_disabled = false;
- u16 u16tmp;
-
- /* This function check if bt is disabled */
-#if 1
- if (coex_sta->high_priority_tx == 0 &&
- coex_sta->high_priority_rx == 0 &&
- coex_sta->low_priority_tx == 0 &&
- coex_sta->low_priority_rx == 0)
- bt_active = false;
- if (coex_sta->high_priority_tx == 0xffff &&
- coex_sta->high_priority_rx == 0xffff &&
- coex_sta->low_priority_tx == 0xffff &&
- coex_sta->low_priority_rx == 0xffff)
- bt_active = false;
-
-
-#else /* 8703b BT can't show correct on/off status in scoreboard[1] 2015/11/26 */
-
- halbtc8703b1ant_read_score_board(btcoexist, &u16tmp);
-
- bt_active = u16tmp & BIT(1);
-
-
-#endif
-
- if (bt_active) {
- bt_disable_cnt = 0;
- bt_disabled = false;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
- &bt_disabled);
- } else {
-
- bt_disable_cnt++;
- if (bt_disable_cnt >= 2) {
- bt_disabled = true;
- bt_disable_cnt = 2;
- }
-
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
- &bt_disabled);
- }
-
-
- if (coex_sta->bt_disabled != bt_disabled) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is from %s to %s!!\n",
- (coex_sta->bt_disabled ? "disabled" : "enabled"),
- (bt_disabled ? "disabled" : "enabled"));
- BTC_TRACE(trace_buf);
- coex_sta->bt_disabled = bt_disabled;
-
- }
-}
-
-void halbtc8703b1ant_enable_gnt_to_gpio(IN struct btc_coexist *btcoexist,
- IN boolean isenable)
-{
-
-#if (BT_8703B_1ANT_ENABLE_GNTBT_TO_GPIO14 == 1)
- if (isenable) {
- /* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x1);
-
- /* enable GNT_BT debug to GPIO */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x40, 0x0);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x1, 0x0);
- } else {
- /* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x0);
-
- /* Disable GNT_BT debug to GPIO, and enable chip_wakeup_host */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x40, 0x1);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x1, 0x1);
- }
-#endif
-}
-
-u32 halbtc8703b1ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist,
- IN u16 reg_addr)
-{
- u32 j = 0;
-
-
- /* wait for ready bit before access 0x7c0 */
- btcoexist->btc_write_4byte(btcoexist, 0x7c0, 0x800F0000 | reg_addr);
-
- do {
- j++;
- } while (((btcoexist->btc_read_1byte(btcoexist,
- 0x7c3)&BIT(5)) == 0) &&
- (j < BT_8703B_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT));
-
-
- return btcoexist->btc_read_4byte(btcoexist,
- 0x7c8); /* get read data */
-
-}
-
-void halbtc8703b1ant_ltecoex_indirect_write_reg(IN struct btc_coexist *btcoexist,
- IN u16 reg_addr, IN u32 bit_mask, IN u32 reg_value)
-{
- u32 val, i = 0, j = 0, bitpos = 0;
-
-
- if (bit_mask == 0x0)
- return;
- if (bit_mask == 0xffffffff) {
- btcoexist->btc_write_4byte(btcoexist, 0x7c4,
- reg_value); /* put write data */
-
- /* wait for ready bit before access 0x7c0 */
- do {
- j++;
- } while (((btcoexist->btc_read_1byte(btcoexist,
- 0x7c3)&BIT(5)) == 0) &&
- (j < BT_8703B_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT));
-
-
- btcoexist->btc_write_4byte(btcoexist, 0x7c0,
- 0xc00F0000 | reg_addr);
- } else {
- for (i = 0; i <= 31; i++) {
- if (((bit_mask >> i) & 0x1) == 0x1) {
- bitpos = i;
- break;
- }
- }
-
- /* read back register value before write */
- val = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist,
- reg_addr);
- val = (val & (~bit_mask)) | (reg_value << bitpos);
-
- btcoexist->btc_write_4byte(btcoexist, 0x7c4,
- val); /* put write data */
-
- /* wait for ready bit before access 0x7c0 */
- do {
- j++;
- } while (((btcoexist->btc_read_1byte(btcoexist,
- 0x7c3)&BIT(5)) == 0) &&
- (j < BT_8703B_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT));
-
-
- btcoexist->btc_write_4byte(btcoexist, 0x7c0,
- 0xc00F0000 | reg_addr);
-
- }
-
-}
-
-void halbtc8703b1ant_ltecoex_enable(IN struct btc_coexist *btcoexist,
- IN boolean enable)
-{
- u8 val;
-
- val = (enable) ? 1 : 0;
- halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist, 0x38, 0x80,
- val); /* 0x38[7] */
-
-}
-
-void halbtc8703b1ant_sw_mechanism(IN struct btc_coexist *btcoexist,
- IN boolean low_penalty_ra)
-{
- halbtc8703b1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra);
-}
-
-void halbtc8703b1ant_ltecoex_pathcontrol_owner(IN struct btc_coexist *btcoexist,
- IN boolean wifi_control)
-{
- u8 val;
-
- val = (wifi_control) ? 1 : 0;
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x4,
- val); /* 0x70[26] */
-
-}
-
-void halbtc8703b1ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist,
- IN u8 control_block, IN boolean sw_control, IN u8 state)
-{
- u32 val = 0, bit_mask;
-
- state = state & 0x1;
- val = (sw_control) ? ((state << 1) | 0x1) : 0;
-
- switch (control_block) {
- case BT_8703B_1ANT_GNT_BLOCK_RFC_BB:
- default:
- bit_mask = 0xc000;
- halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist,
- 0x38, bit_mask, val); /* 0x38[15:14] */
- bit_mask = 0x0c00;
- halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist,
- 0x38, bit_mask, val); /* 0x38[11:10] */
- break;
- case BT_8703B_1ANT_GNT_BLOCK_RFC:
- bit_mask = 0xc000;
- halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist,
- 0x38, bit_mask, val); /* 0x38[15:14] */
- break;
- case BT_8703B_1ANT_GNT_BLOCK_BB:
- bit_mask = 0x0c00;
- halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist,
- 0x38, bit_mask, val); /* 0x38[11:10] */
- break;
-
- }
-
-}
-
-void halbtc8703b1ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist,
- IN u8 control_block, IN boolean sw_control, IN u8 state)
-{
- u32 val = 0, bit_mask;
-
- state = state & 0x1;
- val = (sw_control) ? ((state << 1) | 0x1) : 0;
-
- switch (control_block) {
- case BT_8703B_1ANT_GNT_BLOCK_RFC_BB:
- default:
- bit_mask = 0x3000;
- halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist,
- 0x38, bit_mask, val); /* 0x38[13:12] */
- bit_mask = 0x0300;
- halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist,
- 0x38, bit_mask, val); /* 0x38[9:8] */
- break;
- case BT_8703B_1ANT_GNT_BLOCK_RFC:
- bit_mask = 0x3000;
- halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist,
- 0x38, bit_mask, val); /* 0x38[13:12] */
- break;
- case BT_8703B_1ANT_GNT_BLOCK_BB:
- bit_mask = 0x0300;
- halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist,
- 0x38, bit_mask, val); /* 0x38[9:8] */
- break;
-
- }
-
-}
-
-void halbtc8703b1ant_ltecoex_set_coex_table(IN struct btc_coexist *btcoexist,
- IN u8 table_type, IN u16 table_content)
-{
- u16 reg_addr = 0x0000;
-
- switch (table_type) {
- case BT_8703B_1ANT_CTT_WL_VS_LTE:
- reg_addr = 0xa0;
- break;
- case BT_8703B_1ANT_CTT_BT_VS_LTE:
- reg_addr = 0xa4;
- break;
- }
-
- if (reg_addr != 0x0000)
- halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist, reg_addr,
- 0xffff, table_content); /* 0xa0[15:0] or 0xa4[15:0] */
-
-
-}
-
-
-void halbtc8703b1ant_ltecoex_set_break_table(IN struct btc_coexist *btcoexist,
- IN u8 table_type, IN u8 table_content)
-{
- u16 reg_addr = 0x0000;
-
- switch (table_type) {
- case BT_8703B_1ANT_LBTT_WL_BREAK_LTE:
- reg_addr = 0xa8;
- break;
- case BT_8703B_1ANT_LBTT_BT_BREAK_LTE:
- reg_addr = 0xac;
- break;
- case BT_8703B_1ANT_LBTT_LTE_BREAK_WL:
- reg_addr = 0xb0;
- break;
- case BT_8703B_1ANT_LBTT_LTE_BREAK_BT:
- reg_addr = 0xb4;
- break;
- }
-
- if (reg_addr != 0x0000)
- halbtc8703b1ant_ltecoex_indirect_write_reg(btcoexist, reg_addr,
- 0xff, table_content); /* 0xa8[15:0] or 0xb4[15:0] */
-
-
-}
-
-void halbtc8703b1ant_set_coex_table(IN struct btc_coexist *btcoexist,
- IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc)
-{
- btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
-
- btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
-
- btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
-
- btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
-}
-
-void halbtc8703b1ant_coex_table(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4,
- IN u32 val0x6c8, IN u8 val0x6cc)
-{
- coex_dm->cur_val0x6c0 = val0x6c0;
- coex_dm->cur_val0x6c4 = val0x6c4;
- coex_dm->cur_val0x6c8 = val0x6c8;
- coex_dm->cur_val0x6cc = val0x6cc;
-
- if (!force_exec) {
- if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) &&
- (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) &&
- (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) &&
- (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc))
- return;
- }
- halbtc8703b1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8,
- val0x6cc);
-
- coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0;
- coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4;
- coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8;
- coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc;
-}
-
-void halbtc8703b1ant_coex_table_with_type(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- u32 break_table;
- u8 select_table;
-
- coex_sta->coex_table_type = type;
-
- if (coex_sta->concurrent_rx_mode_on == true) {
- break_table = 0xf0ffffff; /* set WL hi-pri can break BT */
- select_table =
- 0xb; /* set Tx response = Hi-Pri (ex: Transmitting ACK,BA,CTS) */
- } else {
- break_table = 0xffffff;
- select_table = 0x3;
- }
-
- switch (type) {
- case 0:
- halbtc8703b1ant_coex_table(btcoexist, force_exec,
- 0x55555555, 0x55555555, break_table,
- select_table);
- break;
- case 1:
- halbtc8703b1ant_coex_table(btcoexist, force_exec,
- 0x55555555, 0x5a5a5a5a, break_table,
- select_table);
- break;
- case 2:
- halbtc8703b1ant_coex_table(btcoexist, force_exec,
- 0xaa5a5a5a, 0xaa5a5a5a, break_table,
- select_table);
- break;
- case 3:
- halbtc8703b1ant_coex_table(btcoexist, force_exec,
- 0xaa555555, 0xaa5a5a5a, break_table,
- select_table);
- break;
- case 4:
- halbtc8703b1ant_coex_table(btcoexist,
- force_exec, 0xaa555555, 0xaa5a5a5a,
- break_table, select_table);
- break;
- case 5:
- halbtc8703b1ant_coex_table(btcoexist,
- force_exec, 0x5a5a5a5a, 0x5a5a5a5a,
- break_table, select_table);
- break;
- case 6:
- halbtc8703b1ant_coex_table(btcoexist, force_exec,
- 0x55555555, 0xaaaaaaaa, break_table,
- select_table);
- break;
- case 7:
- halbtc8703b1ant_coex_table(btcoexist, force_exec,
- 0xaaaaaaaa, 0xaaaaaaaa, break_table,
- select_table);
- break;
- case 8:
- halbtc8703b1ant_coex_table(btcoexist, force_exec,
- 0x55dd55dd, 0x5ada5ada, break_table,
- select_table);
- break;
- case 9:
- halbtc8703b1ant_coex_table(btcoexist, force_exec,
- 0x55dd55dd, 0x5ada5ada, break_table,
- select_table);
- break;
- case 10:
- halbtc8703b1ant_coex_table(btcoexist, force_exec,
- 0x55dd55dd, 0x5ada5ada, break_table,
- select_table);
- break;
- case 11:
- halbtc8703b1ant_coex_table(btcoexist, force_exec,
- 0x55dd55dd, 0x5ada5ada, break_table,
- select_table);
- break;
- case 12:
- halbtc8703b1ant_coex_table(btcoexist, force_exec,
- 0x55dd55dd, 0x5ada5ada, break_table,
- select_table);
- break;
- case 13:
- halbtc8703b1ant_coex_table(btcoexist, force_exec,
- 0x5fff5fff, 0xaaaaaaaa, break_table,
- select_table);
- break;
- case 14:
- halbtc8703b1ant_coex_table(btcoexist, force_exec,
- 0x5fff5fff, 0x5ada5ada, break_table,
- select_table);
- break;
- case 15:
- halbtc8703b1ant_coex_table(btcoexist, force_exec,
- 0x55dd55dd, 0xaaaaaaaa, break_table,
- select_table);
- break;
- default:
- break;
- }
-}
-
-void halbtc8703b1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist,
- IN boolean enable)
-{
- u8 h2c_parameter[1] = {0};
-
- if (enable) {
- h2c_parameter[0] |= BIT(0); /* function enable */
- }
-
- btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter);
-}
-
-void halbtc8703b1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean enable)
-{
- coex_dm->cur_ignore_wlan_act = enable;
-
- if (!force_exec) {
- if (coex_dm->pre_ignore_wlan_act ==
- coex_dm->cur_ignore_wlan_act)
- return;
- }
- halbtc8703b1ant_set_fw_ignore_wlan_act(btcoexist, enable);
-
- coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
-}
-
-void halbtc8703b1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist,
- IN u8 lps_val, IN u8 rpwm_val)
-{
- u8 lps = lps_val;
- u8 rpwm = rpwm_val;
-
- btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps);
- btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm);
-}
-
-void halbtc8703b1ant_lps_rpwm(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val)
-{
- coex_dm->cur_lps = lps_val;
- coex_dm->cur_rpwm = rpwm_val;
-
- if (!force_exec) {
- if ((coex_dm->pre_lps == coex_dm->cur_lps) &&
- (coex_dm->pre_rpwm == coex_dm->cur_rpwm))
- return;
- }
- halbtc8703b1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val);
-
- coex_dm->pre_lps = coex_dm->cur_lps;
- coex_dm->pre_rpwm = coex_dm->cur_rpwm;
-}
-
-void halbtc8703b1ant_ps_tdma_check_for_power_save_state(
- IN struct btc_coexist *btcoexist, IN boolean new_ps_state)
-{
- u8 lps_mode = 0x0;
- u8 h2c_parameter[5] = {0x8, 0, 0, 0, 0};
-
- btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode);
-
- if (lps_mode) { /* already under LPS state */
- if (new_ps_state) {
- /* keep state under LPS, do nothing. */
- } else {
- /* will leave LPS state, turn off psTdma first */
- /*halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 8); */
- btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
- }
- } else { /* NO PS state */
- if (new_ps_state) {
- /* will enter LPS state, turn off psTdma first */
- /*halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 8);*/
- btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
- } else {
- /* keep state under NO PS state, do nothing. */
- }
- }
-}
-
-void halbtc8703b1ant_power_save_state(IN struct btc_coexist *btcoexist,
- IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val)
-{
- boolean low_pwr_disable = false;
-
- switch (ps_type) {
- case BTC_PS_WIFI_NATIVE:
- /* recover to original 32k low power setting */
- coex_sta->force_lps_on = false;
- low_pwr_disable = false;
- btcoexist->btc_set(btcoexist,
- BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS,
- NULL);
-
- break;
- case BTC_PS_LPS_ON:
- coex_sta->force_lps_on = true;
- halbtc8703b1ant_ps_tdma_check_for_power_save_state(
- btcoexist, true);
- halbtc8703b1ant_lps_rpwm(btcoexist, NORMAL_EXEC,
- lps_val, rpwm_val);
- /* when coex force to enter LPS, do not enter 32k low power. */
- low_pwr_disable = true;
- btcoexist->btc_set(btcoexist,
- BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
- /* power save must executed before psTdma. */
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS,
- NULL);
-
- break;
- case BTC_PS_LPS_OFF:
- coex_sta->force_lps_on = false;
- halbtc8703b1ant_ps_tdma_check_for_power_save_state(
- btcoexist, false);
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS,
- NULL);
-
- break;
- default:
- break;
- }
-}
-
-
-
-void halbtc8703b1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist,
- IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5)
-{
- u8 h2c_parameter[5] = {0};
- u8 real_byte1 = byte1, real_byte5 = byte5;
- boolean ap_enable = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
- &ap_enable);
-
- if (ap_enable) {
- if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], FW for 1Ant AP mode\n");
- BTC_TRACE(trace_buf);
- real_byte1 &= ~BIT(4);
- real_byte1 |= BIT(5);
-
- real_byte5 |= BIT(5);
- real_byte5 &= ~BIT(6);
-
- halbtc8703b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
- }
- } else if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
-
- halbtc8703b1ant_power_save_state(
- btcoexist, BTC_PS_LPS_ON, 0x50,
- 0x4);
- } else {
- halbtc8703b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
- }
-
-
- h2c_parameter[0] = real_byte1;
- h2c_parameter[1] = byte2;
- h2c_parameter[2] = byte3;
- h2c_parameter[3] = byte4;
- h2c_parameter[4] = real_byte5;
-
- coex_dm->ps_tdma_para[0] = real_byte1;
- coex_dm->ps_tdma_para[1] = byte2;
- coex_dm->ps_tdma_para[2] = byte3;
- coex_dm->ps_tdma_para[3] = byte4;
- coex_dm->ps_tdma_para[4] = real_byte5;
-
- btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
-}
-
-
-void halbtc8703b1ant_ps_tdma(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean turn_on, IN u8 type)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_busy = false;
- u8 rssi_adjust_val = 0;
- static u8 psTdmaByte4Modify = 0x0, pre_psTdmaByte4Modify = 0x0;
- static boolean pre_wifi_busy = false;
-
- coex_dm->cur_ps_tdma_on = turn_on;
- coex_dm->cur_ps_tdma = type;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- if (wifi_busy != pre_wifi_busy) {
- force_exec = true;
- pre_wifi_busy = wifi_busy;
- }
-
- /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */
- if ((bt_link_info->slave_role) && (bt_link_info->a2dp_exist))
- psTdmaByte4Modify = 0x1;
- else
- psTdmaByte4Modify = 0x0;
-
- if (pre_psTdmaByte4Modify != psTdmaByte4Modify) {
-
- force_exec = true;
- pre_psTdmaByte4Modify = psTdmaByte4Modify;
- }
-
- if (!force_exec) {
- if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) &&
- (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma))
- return;
- }
-
- if (coex_dm->cur_ps_tdma_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** TDMA(on, %d) **********\n",
- coex_dm->cur_ps_tdma);
- BTC_TRACE(trace_buf);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** TDMA(off, %d) **********\n",
- coex_dm->cur_ps_tdma);
- BTC_TRACE(trace_buf);
- }
-
- if (turn_on) {
-
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8,
- 0x1); /* enable TBTT nterrupt */
- }
-
-
- if (turn_on) {
- switch (type) {
- default:
- halbtc8703b1ant_set_fw_pstdma(btcoexist,
- 0x61, 0x35, 0x03, 0x11, 0x11);
- break;
-
- case 3:
- halbtc8703b1ant_set_fw_pstdma(btcoexist,
- 0x51, 0x3a, 0x03, 0x10, 0x10);
- break;
- case 4:
- halbtc8703b1ant_set_fw_pstdma(btcoexist,
- 0x51, 0x21, 0x03, 0x10, 0x10);
- break;
- case 5:
- halbtc8703b1ant_set_fw_pstdma(btcoexist,
- 0x61, 0x15, 0x03, 0x11, 0x11);
- break;
- case 6:
- halbtc8703b1ant_set_fw_pstdma(btcoexist,
- 0x61, 0x20, 0x03, 0x11, 0x11);
- break;
- case 7:
- halbtc8703b1ant_set_fw_pstdma(btcoexist,
- 0x51, 0x10, 0x03, 0x10, 0x14 | psTdmaByte4Modify);
- break;
- case 8:
- halbtc8703b1ant_set_fw_pstdma(btcoexist,
- 0x51, 0x10, 0x03, 0x10, 0x14 | psTdmaByte4Modify);
- break;
- case 13:
- halbtc8703b1ant_set_fw_pstdma(btcoexist,
- 0x51, 0x25, 0x03, 0x10, 0x10 | psTdmaByte4Modify);
- break;
- case 14:
- halbtc8703b1ant_set_fw_pstdma(btcoexist,
- 0x51, 0x15, 0x03, 0x10, 0x10 | psTdmaByte4Modify);
- break;
- case 15:
- halbtc8703b1ant_set_fw_pstdma(btcoexist,
- 0x51, 0x20, 0x03, 0x10, 0x10 | psTdmaByte4Modify);
- break;
- case 17:
- halbtc8703b1ant_set_fw_pstdma(btcoexist,
- 0x61, 0x10, 0x03, 0x11, 0x14 | psTdmaByte4Modify);
- break;
- case 19:
- halbtc8703b1ant_set_fw_pstdma(btcoexist,
- 0x61, 0x15, 0x03, 0x11, 0x10);
- break;
- case 20:
- halbtc8703b1ant_set_fw_pstdma(btcoexist,
- 0x61, 0x30, 0x03, 0x11, 0x10);
- break;
- case 21:
- halbtc8703b1ant_set_fw_pstdma(btcoexist,
- 0x61, 0x30, 0x03, 0x11, 0x10);
- break;
- case 22:
- halbtc8703b1ant_set_fw_pstdma(btcoexist,
- 0x61, 0x25, 0x03, 0x11, 0x10);
- break;
- case 32:
- halbtc8703b1ant_set_fw_pstdma(btcoexist,
- 0x61, 0x35, 0x03, 0x11, 0x11);
- break;
- case 33:
- halbtc8703b1ant_set_fw_pstdma(btcoexist,
- 0x61, 0x35, 0x03, 0x11, 0x10);
- break;
-
- }
- } else {
-
- /* disable PS tdma */
- switch (type) {
- case 8: /* PTA Control */
- halbtc8703b1ant_set_fw_pstdma(btcoexist, 0x8,
- 0x0, 0x0, 0x0, 0x0);
- break;
- case 0:
- default: /* Software control, Antenna at BT side */
- halbtc8703b1ant_set_fw_pstdma(btcoexist, 0x0,
- 0x0, 0x0, 0x0, 0x0);
- break;
- case 1: /* 2-Ant, 0x778=3, antenna control by antenna diversity */
- halbtc8703b1ant_set_fw_pstdma(btcoexist, 0x0,
- 0x0, 0x0, 0x48, 0x0);
- break;
- }
- }
-
- /* update pre state */
- coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on;
- coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
-}
-
-void halbtc8703b1ant_set_ant_path(IN struct btc_coexist *btcoexist,
- IN u8 ant_pos_type, IN boolean force_exec, IN boolean init_hwcfg,
- IN boolean wifi_off)
-{
- u32 cnt_bt_cal_chk = 0;
- boolean is_in_mp_mode = false;
- u8 u8tmp = 0;
- u32 u32tmp1 = 0, u32tmp2 = 0;
-
- coex_dm->cur_ant_pos_type = ant_pos_type;
-
-#if 1
- u32tmp1 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist,
- 0x38);
- u32tmp2 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist,
- 0x54);
- u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (Before Ant Setup) 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n",
- u8tmp, u32tmp1, u32tmp2);
- BTC_TRACE(trace_buf);
-#endif
-
- if (init_hwcfg) {
- /* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */
- halbtc8703b1ant_ltecoex_enable(btcoexist, 0x0);
-
- /* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */
- halbtc8703b1ant_ltecoex_set_coex_table(btcoexist,
- BT_8703B_1ANT_CTT_WL_VS_LTE, 0xffff);
-
- /* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */
- halbtc8703b1ant_ltecoex_set_coex_table(btcoexist,
- BT_8703B_1ANT_CTT_BT_VS_LTE, 0xffff);
-
- /* Wait If BT IQK running, because Path control owner is at BT during BT IQK (setup by WiFi firmware) */
- while (cnt_bt_cal_chk <= 20) {
- u8tmp = btcoexist->btc_read_1byte(btcoexist,
- 0x49d);
- cnt_bt_cal_chk++;
- if (u8tmp & BIT(0)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ########### BT is calibrating (wait cnt=%d) ###########\n",
- cnt_bt_cal_chk);
- BTC_TRACE(trace_buf);
- delay_ms(50);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** BT is NOT calibrating (wait cnt=%d)**********\n",
- cnt_bt_cal_chk);
- BTC_TRACE(trace_buf);
- break;
- }
- }
-
- /* set Path control owner to WL at initial step */
- halbtc8703b1ant_ltecoex_pathcontrol_owner(btcoexist,
- BT_8703B_1ANT_PCO_WLSIDE);
-
- /* set GNT_BT to SW high */
- halbtc8703b1ant_ltecoex_set_gnt_bt(btcoexist,
- BT_8703B_1ANT_GNT_BLOCK_RFC_BB,
- BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW,
- BT_8703B_1ANT_SIG_STA_SET_TO_HIGH);
- /* Set GNT_WL to SW low */
- halbtc8703b1ant_ltecoex_set_gnt_wl(btcoexist,
- BT_8703B_1ANT_GNT_BLOCK_RFC_BB,
- BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW,
- BT_8703B_1ANT_SIG_STA_SET_TO_LOW);
-
- coex_sta->gnt_control_by_PTA = false;
-
- } else if (wifi_off) {
- /* Disable LTE Coex Function in WiFi side */
- halbtc8703b1ant_ltecoex_enable(btcoexist, 0x0);
-
- /* set Path control owner to BT */
- halbtc8703b1ant_ltecoex_pathcontrol_owner(btcoexist,
- BT_8703B_1ANT_PCO_BTSIDE);
-
- coex_sta->gnt_control_by_PTA = false;
- } else {
-
- halbtc8703b1ant_ltecoex_pathcontrol_owner(btcoexist,
- BT_8703B_1ANT_PCO_WLSIDE);
-
-
- if (force_exec ||
- (coex_dm->cur_ant_pos_type != coex_dm->pre_ant_pos_type) ||
- init_hwcfg || wifi_off) {
- /* internal switch setting */
- switch (ant_pos_type) {
- case BTC_ANT_PATH_WIFI:
- /* set GNT_BT to low */
- halbtc8703b1ant_ltecoex_set_gnt_bt(btcoexist,
- BT_8703B_1ANT_GNT_BLOCK_RFC_BB,
- BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW,
- BT_8703B_1ANT_SIG_STA_SET_TO_LOW);
- /* Set GNT_WL to high */
- halbtc8703b1ant_ltecoex_set_gnt_wl(btcoexist,
- BT_8703B_1ANT_GNT_BLOCK_RFC_BB,
- BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW,
- BT_8703B_1ANT_SIG_STA_SET_TO_HIGH);
-
- coex_sta->gnt_control_by_PTA = false;
- break;
- case BTC_ANT_PATH_BT:
- /*halbtc8703b1ant_ltecoex_pathcontrol_owner(
- btcoexist, BT_8703B_1ANT_PCO_BTSIDE);*/
- /* set GNT_BT to high */
- halbtc8703b1ant_ltecoex_set_gnt_bt(btcoexist,
- BT_8703B_1ANT_GNT_BLOCK_RFC_BB,
- BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW,
- BT_8703B_1ANT_SIG_STA_SET_TO_HIGH);
- /* Set GNT_WL to low */
- halbtc8703b1ant_ltecoex_set_gnt_wl(btcoexist,
- BT_8703B_1ANT_GNT_BLOCK_RFC_BB,
- BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW,
- BT_8703B_1ANT_SIG_STA_SET_TO_LOW);
-
- coex_sta->gnt_control_by_PTA = false;
- break;
- default:
- case BTC_ANT_PATH_PTA:
- /* set GNT_BT to PTA */
- halbtc8703b1ant_ltecoex_set_gnt_bt(btcoexist,
- BT_8703B_1ANT_GNT_BLOCK_RFC_BB,
- BT_8703B_1ANT_GNT_TYPE_CTRL_BY_PTA,
- BT_8703B_1ANT_SIG_STA_SET_BY_HW);
- /* Set GNT_WL to PTA */
- halbtc8703b1ant_ltecoex_set_gnt_wl(btcoexist,
- BT_8703B_1ANT_GNT_BLOCK_RFC_BB,
- BT_8703B_1ANT_GNT_TYPE_CTRL_BY_PTA,
- BT_8703B_1ANT_SIG_STA_SET_BY_HW);
-
- coex_sta->gnt_control_by_PTA = true;
- break;
- }
- }
- }
-
-#if 1
- u32tmp1 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
- u32tmp2 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
- u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73);
-
- if (init_hwcfg) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (After Ant-Setup Init) 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n",
- u8tmp, u32tmp1, u32tmp2);
- BTC_TRACE(trace_buf);
- } else if (wifi_off) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (After Ant-Setup WiFi off) 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n",
- u8tmp, u32tmp1, u32tmp2);
- BTC_TRACE(trace_buf);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (After Ant-Setup Run time) 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n",
- u8tmp, u32tmp1, u32tmp2);
- BTC_TRACE(trace_buf);
- }
-#endif
-
- coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type;
-}
-
-
-boolean halbtc8703b1ant_is_common_action(IN struct btc_coexist *btcoexist)
-{
- boolean common = false, wifi_connected = false, wifi_busy = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- if (!wifi_connected &&
- BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
- coex_dm->bt_status) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n");
- BTC_TRACE(trace_buf);
-
- /* halbtc8703b1ant_sw_mechanism(btcoexist, false); */
-
- common = true;
- } else if (wifi_connected &&
- (BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
- coex_dm->bt_status)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi connected + BT non connected-idle!!\n");
- BTC_TRACE(trace_buf);
-
- /* halbtc8703b1ant_sw_mechanism(btcoexist, false); */
-
- common = true;
- } else if (!wifi_connected &&
- (BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi non connected-idle + BT connected-idle!!\n");
- BTC_TRACE(trace_buf);
-
- /* halbtc8703b1ant_sw_mechanism(btcoexist, false); */
-
- common = true;
- } else if (wifi_connected &&
- (BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi connected + BT connected-idle!!\n");
- BTC_TRACE(trace_buf);
-
- /* halbtc8703b1ant_sw_mechanism(btcoexist, false); */
-
- common = true;
- } else if (!wifi_connected &&
- (BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE != coex_dm->bt_status)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi non connected-idle + BT Busy!!\n");
- BTC_TRACE(trace_buf);
-
- /* halbtc8703b1ant_sw_mechanism(btcoexist, false); */
-
- common = true;
- } else {
- if (wifi_busy) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi Connected-Busy + BT Busy!!\n");
- BTC_TRACE(trace_buf);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi Connected-Idle + BT Busy!!\n");
- BTC_TRACE(trace_buf);
- }
-
- common = false;
- }
-
- return common;
-}
-
-/* *********************************************
- *
- * Software Coex Mechanism start
- *
- * ********************************************* */
-
-/* SCO only or SCO+PAN(HS) */
-
-/*
-void halbtc8703b1ant_action_sco(IN struct btc_coexist* btcoexist)
-{
- halbtc8703b1ant_sw_mechanism(btcoexist, true);
-}
-
-
-void halbtc8703b1ant_action_hid(IN struct btc_coexist* btcoexist)
-{
- halbtc8703b1ant_sw_mechanism(btcoexist, true);
-}
-
-
-void halbtc8703b1ant_action_a2dp(IN struct btc_coexist* btcoexist)
-{
- halbtc8703b1ant_sw_mechanism(btcoexist, false);
-}
-
-void halbtc8703b1ant_action_a2dp_pan_hs(IN struct btc_coexist* btcoexist)
-{
- halbtc8703b1ant_sw_mechanism(btcoexist, false);
-}
-
-void halbtc8703b1ant_action_pan_edr(IN struct btc_coexist* btcoexist)
-{
- halbtc8703b1ant_sw_mechanism(btcoexist, false);
-}
-
-
-void halbtc8703b1ant_action_pan_hs(IN struct btc_coexist* btcoexist)
-{
- halbtc8703b1ant_sw_mechanism(btcoexist, false);
-}
-
-
-void halbtc8703b1ant_action_pan_edr_a2dp(IN struct btc_coexist* btcoexist)
-{
- halbtc8703b1ant_sw_mechanism(btcoexist, false);
-}
-
-void halbtc8703b1ant_action_pan_edr_hid(IN struct btc_coexist* btcoexist)
-{
- halbtc8703b1ant_sw_mechanism(btcoexist, true);
-}
-
-
-void halbtc8703b1ant_action_hid_a2dp_pan_edr(IN struct btc_coexist* btcoexist)
-{
- halbtc8703b1ant_sw_mechanism(btcoexist, true);
-}
-
-void halbtc8703b1ant_action_hid_a2dp(IN struct btc_coexist* btcoexist)
-{
- halbtc8703b1ant_sw_mechanism(btcoexist, true);
-}
-
-*/
-
-/* *********************************************
- *
- * Non-Software Coex Mechanism start
- *
- * ********************************************* */
-u8 halbtc8703b1ant_action_algorithm(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean bt_hs_on = false;
- u8 algorithm = BT_8703B_1ANT_COEX_ALGO_UNDEFINED;
- u8 num_of_diff_profile = 0;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
-
- if (!bt_link_info->bt_link_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], No BT link exists!!!\n");
- BTC_TRACE(trace_buf);
- return algorithm;
- }
-
- if (bt_link_info->sco_exist)
- num_of_diff_profile++;
- if (bt_link_info->hid_exist)
- num_of_diff_profile++;
- if (bt_link_info->pan_exist)
- num_of_diff_profile++;
- if (bt_link_info->a2dp_exist)
- num_of_diff_profile++;
-
- if (num_of_diff_profile == 1) {
- if (bt_link_info->sco_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO only\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8703B_1ANT_COEX_ALGO_SCO;
- } else {
- if (bt_link_info->hid_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = HID only\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8703B_1ANT_COEX_ALGO_HID;
- } else if (bt_link_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = A2DP only\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8703B_1ANT_COEX_ALGO_A2DP;
- } else if (bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = PAN(HS) only\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8703B_1ANT_COEX_ALGO_PANHS;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = PAN(EDR) only\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8703B_1ANT_COEX_ALGO_PANEDR;
- }
- }
- }
- } else if (num_of_diff_profile == 2) {
- if (bt_link_info->sco_exist) {
- if (bt_link_info->hid_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + HID\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8703B_1ANT_COEX_ALGO_HID;
- } else if (bt_link_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + A2DP ==> SCO\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8703B_1ANT_COEX_ALGO_SCO;
- } else if (bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8703B_1ANT_COEX_ALGO_SCO;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8703B_1ANT_COEX_ALGO_PANEDR_HID;
- }
- }
- } else {
- if (bt_link_info->hid_exist &&
- bt_link_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = HID + A2DP\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8703B_1ANT_COEX_ALGO_HID_A2DP;
- } else if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = HID + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8703B_1ANT_COEX_ALGO_HID_A2DP;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = HID + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8703B_1ANT_COEX_ALGO_PANEDR_HID;
- }
- } else if (bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8703B_1ANT_COEX_ALGO_A2DP_PANHS;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = A2DP + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8703B_1ANT_COEX_ALGO_PANEDR_A2DP;
- }
- }
- }
- } else if (num_of_diff_profile == 3) {
- if (bt_link_info->sco_exist) {
- if (bt_link_info->hid_exist &&
- bt_link_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8703B_1ANT_COEX_ALGO_HID;
- } else if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + HID + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8703B_1ANT_COEX_ALGO_HID_A2DP;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8703B_1ANT_COEX_ALGO_PANEDR_HID;
- }
- } else if (bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8703B_1ANT_COEX_ALGO_SCO;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8703B_1ANT_COEX_ALGO_PANEDR_HID;
- }
- }
- } else {
- if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8703B_1ANT_COEX_ALGO_HID_A2DP;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8703B_1ANT_COEX_ALGO_HID_A2DP_PANEDR;
- }
- }
- }
- } else if (num_of_diff_profile >= 3) {
- if (bt_link_info->sco_exist) {
- if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
-
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8703B_1ANT_COEX_ALGO_PANEDR_HID;
- }
- }
- }
- }
-
- return algorithm;
-}
-
-
-
-void halbtc8703b1ant_action_bt_whck_test(IN struct btc_coexist *btcoexist)
-{
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC,
- false, false);
- halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-}
-
-void halbtc8703b1ant_action_wifi_only(IN struct btc_coexist *btcoexist)
-{
- halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8);
- halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, FORCE_EXEC,
- false, false);
- halbtc8703b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
-}
-
-void halbtc8703b1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist)
-{
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC,
- false, false);
- halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
-}
-
-void halbtc8703b1ant_action_hs(IN struct btc_coexist *btcoexist)
-{
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
- halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
-}
-
-void halbtc8703b1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_connected = false, ap_enable = false, wifi_busy = false,
- bt_busy = false;
- boolean wifi_scan = false, wifi_link = false, wifi_roam = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
- &ap_enable);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam);
-
- if ((wifi_link) || (wifi_roam) || (coex_sta->wifi_is_high_pri_task)) {
-
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33);
- halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6);
-
- } else if ((wifi_scan) && (coex_sta->bt_create_connection)) {
-
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22);
- halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6);
-
- } else if ((!wifi_connected) && (!wifi_scan)) {
-
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
- NORMAL_EXEC, false, false);
-
- halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
- } else if ((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) {
-
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22);
- halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
-
- } else if (bt_link_info->a2dp_exist) {
-
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
-
- halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- } else if (wifi_scan) {
-
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
-
- halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
-
- } else if (wifi_busy) {
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 21);
-
- halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- } else {
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 19);
-
- halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- }
-}
-
-void halbtc8703b1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist
- *btcoexist, IN u8 wifi_status)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_connected = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
-
- /* tdma and coex table */
-
- if (bt_link_info->sco_exist) {
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
- halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
- } else { /* HID */
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 6);
- halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
- }
-}
-
-void halbtc8703b1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist
- *btcoexist, IN u8 wifi_status)
-{
-
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_busy = false;
-
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
-
- if (bt_link_info->hid_only) { /* HID */
- halbtc8703b1ant_action_bt_sco_hid_only_busy(btcoexist,
- wifi_status);
- coex_dm->auto_tdma_adjust = false;
- return;
- } else if (bt_link_info->a2dp_only) { /* A2DP */
- if (BT_8703B_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifi_status) {
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 32);
- halbtc8703b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- coex_dm->auto_tdma_adjust = false;
- } else {
-
- if (coex_sta->scan_ap_num >=
- BT_8703B_1ANT_WIFI_NOISY_THRESH) {
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 17);
- } else {
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 7);
- }
-
- halbtc8703b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- coex_dm->auto_tdma_adjust = true;
- }
- } else if (((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) ||
- (bt_link_info->hid_exist && bt_link_info->a2dp_exist &&
- bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */
-
- if (wifi_busy) {
-
- if ((coex_sta->a2dp_bit_pool > 40) && (coex_sta->a2dp_bit_pool < 255))
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 15);
- else
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13);
- } else
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14);
-
- halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
- coex_dm->auto_tdma_adjust = false;
- } else if (bt_link_info->hid_exist &&
- bt_link_info->a2dp_exist) { /* HID+A2DP */
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 8);
- coex_dm->auto_tdma_adjust = false;
-
- halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
- } else if ((bt_link_info->pan_only) || (bt_link_info->hid_exist &&
- bt_link_info->pan_exist)) { /* PAN(OPP,FTP), HID+PAN(OPP,FTP) */
- if (BT_8703B_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifi_status)
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 4);
- else
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3);
-
- halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
- coex_dm->auto_tdma_adjust = false;
- } else {
- /* BT no-profile busy (0x9) */
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33);
- halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- coex_dm->auto_tdma_adjust = false;
- }
-}
-
-void halbtc8703b1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist)
-{
-
- /* tdma and coex table */
- halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8);
- halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC,
- false, false);
- halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-}
-
-void halbtc8703b1ant_action_wifi_not_connected_scan(IN struct btc_coexist
- *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_connected = false, bt_hs_on = false;
- u32 wifi_link_status = 0;
- u32 num_of_wifi_link = 0;
- boolean bt_ctrl_agg_buf_size = false;
- u8 agg_buf_size = 5;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
-
- num_of_wifi_link = wifi_link_status >> 16;
-
- if (num_of_wifi_link >= 2) {
- halbtc8703b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
- halbtc8703b1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
- bt_ctrl_agg_buf_size, agg_buf_size);
-
- if (coex_sta->c2h_bt_inquiry_page) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], BT Is Inquirying\n");
- BTC_TRACE(trace_buf);
- halbtc8703b1ant_action_bt_inquiry(btcoexist);
- } else
- halbtc8703b1ant_action_wifi_multi_port(btcoexist);
- return;
- }
-
- if (coex_sta->c2h_bt_inquiry_page) {
- halbtc8703b1ant_action_bt_inquiry(btcoexist);
- return;
- } else if (bt_hs_on) {
- halbtc8703b1ant_action_hs(btcoexist);
- return;
- }
-
- /* tdma and coex table */
- if (BT_8703B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
- if (bt_link_info->a2dp_exist) {
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 32);
- halbtc8703b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- } else if (bt_link_info->a2dp_exist &&
- bt_link_info->pan_exist) {
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 22);
- halbtc8703b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- } else {
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
- halbtc8703b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- }
- } else if ((BT_8703B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
- (BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY ==
- coex_dm->bt_status)) {
- halbtc8703b1ant_action_bt_sco_hid_only_busy(btcoexist,
- BT_8703B_1ANT_WIFI_STATUS_CONNECTED_SCAN);
- } else {
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
- NORMAL_EXEC, false, false);
- halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
- }
-}
-
-void halbtc8703b1ant_action_wifi_not_connected_asso_auth(
- IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_connected = false, bt_hs_on = false;
- u32 wifi_link_status = 0;
- u32 num_of_wifi_link = 0;
- boolean bt_ctrl_agg_buf_size = false;
- u8 agg_buf_size = 5;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
-
- num_of_wifi_link = wifi_link_status >> 16;
-
- if (num_of_wifi_link >= 2) {
- halbtc8703b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
- halbtc8703b1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
- bt_ctrl_agg_buf_size, agg_buf_size);
-
- if (coex_sta->c2h_bt_inquiry_page) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], BT Is Inquirying\n");
- BTC_TRACE(trace_buf);
- halbtc8703b1ant_action_bt_inquiry(btcoexist);
- } else
- halbtc8703b1ant_action_wifi_multi_port(btcoexist);
- return;
- }
-
- if (coex_sta->c2h_bt_inquiry_page) {
- halbtc8703b1ant_action_bt_inquiry(btcoexist);
- return;
- } else if (bt_hs_on) {
- halbtc8703b1ant_action_hs(btcoexist);
- return;
- }
-
- /* tdma and coex table */
- if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) ||
- (bt_link_info->a2dp_exist)) {
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
- halbtc8703b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4);
- } else if (bt_link_info->pan_exist) {
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
- halbtc8703b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4);
- } else {
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
- NORMAL_EXEC, false, false);
- halbtc8703b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 2);
- }
-}
-
-void halbtc8703b1ant_action_wifi_connected_scan(IN struct btc_coexist
- *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_connected = false, bt_hs_on = false;
- u32 wifi_link_status = 0;
- u32 num_of_wifi_link = 0;
- boolean bt_ctrl_agg_buf_size = false;
- u8 agg_buf_size = 5;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
-
- num_of_wifi_link = wifi_link_status >> 16;
-
- if (num_of_wifi_link >= 2) {
- halbtc8703b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
- halbtc8703b1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
- bt_ctrl_agg_buf_size, agg_buf_size);
-
- if (coex_sta->c2h_bt_inquiry_page) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], BT Is Inquirying\n");
- BTC_TRACE(trace_buf);
- halbtc8703b1ant_action_bt_inquiry(btcoexist);
- } else
- halbtc8703b1ant_action_wifi_multi_port(btcoexist);
- return;
- }
-
- if (coex_sta->c2h_bt_inquiry_page) {
- halbtc8703b1ant_action_bt_inquiry(btcoexist);
- return;
- } else if (bt_hs_on) {
- halbtc8703b1ant_action_hs(btcoexist);
- return;
- }
-
- /* tdma and coex table */
- if (BT_8703B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
- if (bt_link_info->a2dp_exist) {
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 32);
- halbtc8703b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- } else if (bt_link_info->a2dp_exist &&
- bt_link_info->pan_exist) {
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 22);
- halbtc8703b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- } else {
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
- halbtc8703b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- }
- } else if ((BT_8703B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
- (BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY ==
- coex_dm->bt_status)) {
- halbtc8703b1ant_action_bt_sco_hid_only_busy(btcoexist,
- BT_8703B_1ANT_WIFI_STATUS_CONNECTED_SCAN);
- } else {
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
- NORMAL_EXEC, false, false);
- halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
- }
-}
-
-void halbtc8703b1ant_action_wifi_connected_specific_packet(
- IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_connected = false, bt_hs_on = false;
- u32 wifi_link_status = 0;
- u32 num_of_wifi_link = 0;
- boolean bt_ctrl_agg_buf_size = false;
- u8 agg_buf_size = 5;
- boolean wifi_busy = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
-
- num_of_wifi_link = wifi_link_status >> 16;
-
- if (num_of_wifi_link >= 2) {
- halbtc8703b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
- halbtc8703b1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
- bt_ctrl_agg_buf_size, agg_buf_size);
-
- if (coex_sta->c2h_bt_inquiry_page) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], BT Is Inquirying\n");
- BTC_TRACE(trace_buf);
- halbtc8703b1ant_action_bt_inquiry(btcoexist);
- } else
- halbtc8703b1ant_action_wifi_multi_port(btcoexist);
- return;
- }
-
- if (coex_sta->c2h_bt_inquiry_page) {
- halbtc8703b1ant_action_bt_inquiry(btcoexist);
- return;
- } else if (bt_hs_on) {
- halbtc8703b1ant_action_hs(btcoexist);
- return;
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- /* no specific packet process for both WiFi and BT very busy */
- if ((wifi_busy) && ((bt_link_info->pan_exist) ||
- (coex_sta->num_of_profile >= 2)))
- return;
-
- /* tdma and coex table */
- if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist)) {
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
- halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
- } else if (bt_link_info->a2dp_exist) {
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
- halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- } else if (bt_link_info->pan_exist) {
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
- halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- } else {
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
- NORMAL_EXEC, false, false);
- halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
- }
-}
-
-void halbtc8703b1ant_action_wifi_connected(IN struct btc_coexist *btcoexist)
-{
- boolean wifi_busy = false;
- boolean scan = false, link = false, roam = false;
- boolean under_4way = false, ap_enable = false;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CoexForWifiConnect()===>\n");
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
- &under_4way);
- if (under_4way) {
- halbtc8703b1ant_action_wifi_connected_specific_packet(btcoexist);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CoexForWifiConnect(), return for wifi is under 4way<===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
- if (scan || link || roam) {
- if (scan)
- halbtc8703b1ant_action_wifi_connected_scan(btcoexist);
- else
- halbtc8703b1ant_action_wifi_connected_specific_packet(
- btcoexist);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CoexForWifiConnect(), return for wifi is under scan<===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
- &ap_enable);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
-
- /* tdma and coex table */
- if (!wifi_busy) {
- if (BT_8703B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
- halbtc8703b1ant_action_wifi_connected_bt_acl_busy(
- btcoexist,
- BT_8703B_1ANT_WIFI_STATUS_CONNECTED_IDLE);
- } else if ((BT_8703B_1ANT_BT_STATUS_SCO_BUSY ==
- coex_dm->bt_status) ||
- (BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY ==
- coex_dm->bt_status)) {
- halbtc8703b1ant_action_bt_sco_hid_only_busy(btcoexist,
- BT_8703B_1ANT_WIFI_STATUS_CONNECTED_IDLE);
- } else {
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 8);
- halbtc8703b1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_PTA, NORMAL_EXEC, false, false);
- halbtc8703b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 2);
- }
- } else {
- if (BT_8703B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
- halbtc8703b1ant_action_wifi_connected_bt_acl_busy(
- btcoexist,
- BT_8703B_1ANT_WIFI_STATUS_CONNECTED_BUSY);
- } else if ((BT_8703B_1ANT_BT_STATUS_SCO_BUSY ==
- coex_dm->bt_status) ||
- (BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY ==
- coex_dm->bt_status)) {
- halbtc8703b1ant_action_bt_sco_hid_only_busy(btcoexist,
- BT_8703B_1ANT_WIFI_STATUS_CONNECTED_BUSY);
- } else {
- /* halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); */
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 32);
- halbtc8703b1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_PTA, NORMAL_EXEC, false, false);
- /* halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); */
- halbtc8703b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- }
- }
-}
-
-void halbtc8703b1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist)
-{
- u8 algorithm = 0;
-
- algorithm = halbtc8703b1ant_action_algorithm(btcoexist);
- coex_dm->cur_algorithm = algorithm;
-
- if (halbtc8703b1ant_is_common_action(btcoexist)) {
-
- } else {
- switch (coex_dm->cur_algorithm) {
- case BT_8703B_1ANT_COEX_ALGO_SCO:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = SCO.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8703b1ant_action_sco(btcoexist); */
- break;
- case BT_8703B_1ANT_COEX_ALGO_HID:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = HID.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8703b1ant_action_hid(btcoexist); */
- break;
- case BT_8703B_1ANT_COEX_ALGO_A2DP:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = A2DP.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8703b1ant_action_a2dp(btcoexist); */
- break;
- case BT_8703B_1ANT_COEX_ALGO_A2DP_PANHS:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = A2DP+PAN(HS).\n");
- BTC_TRACE(trace_buf);
- /* halbtc8703b1ant_action_a2dp_pan_hs(btcoexist); */
- break;
- case BT_8703B_1ANT_COEX_ALGO_PANEDR:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = PAN(EDR).\n");
- BTC_TRACE(trace_buf);
- /* halbtc8703b1ant_action_pan_edr(btcoexist); */
- break;
- case BT_8703B_1ANT_COEX_ALGO_PANHS:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = HS mode.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8703b1ant_action_pan_hs(btcoexist); */
- break;
- case BT_8703B_1ANT_COEX_ALGO_PANEDR_A2DP:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = PAN+A2DP.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8703b1ant_action_pan_edr_a2dp(btcoexist); */
- break;
- case BT_8703B_1ANT_COEX_ALGO_PANEDR_HID:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = PAN(EDR)+HID.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8703b1ant_action_pan_edr_hid(btcoexist); */
- break;
- case BT_8703B_1ANT_COEX_ALGO_HID_A2DP_PANEDR:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = HID+A2DP+PAN.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8703b1ant_action_hid_a2dp_pan_edr(btcoexist); */
- break;
- case BT_8703B_1ANT_COEX_ALGO_HID_A2DP:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = HID+A2DP.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8703b1ant_action_hid_a2dp(btcoexist); */
- break;
- default:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = coexist All Off!!\n");
- BTC_TRACE(trace_buf);
- /* halbtc8703b1ant_coex_all_off(btcoexist); */
- break;
- }
- coex_dm->pre_algorithm = coex_dm->cur_algorithm;
- }
-}
-
-void halbtc8703b1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_connected = false, bt_hs_on = false;
- boolean increase_scan_dev_num = false;
- boolean bt_ctrl_agg_buf_size = false;
- boolean miracast_plus_bt = false;
- u8 agg_buf_size = 5;
- u32 wifi_link_status = 0;
- u32 num_of_wifi_link = 0, wifi_bw;
- u8 iot_peer = BTC_IOT_PEER_UNKNOWN;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism()===>\n");
- BTC_TRACE(trace_buf);
-
- if (btcoexist->manual_control) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- if (btcoexist->stop_coex_dm) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- if (coex_sta->under_ips) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], wifi is under IPS !!!\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- if (coex_sta->bt_whck_test) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is under WHCK TEST!!!\n");
- BTC_TRACE(trace_buf);
- halbtc8703b1ant_action_bt_whck_test(btcoexist);
- return;
- }
-
- if (coex_sta->bt_disabled) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is disabled !!!\n");
- halbtc8703b1ant_action_wifi_only(btcoexist);
- return;
- }
-
- if ((BT_8703B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
- (BT_8703B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
- (BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status))
- increase_scan_dev_num = true;
-
- btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM,
- &increase_scan_dev_num);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
- num_of_wifi_link = wifi_link_status >> 16;
-
- if ((num_of_wifi_link >= 2) ||
- (wifi_link_status & WIFI_P2P_GO_CONNECTED)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n",
- num_of_wifi_link, wifi_link_status);
- BTC_TRACE(trace_buf);
-
- if (bt_link_info->bt_link_exist) {
- halbtc8703b1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1,
- 0, 1);
- miracast_plus_bt = true;
- } else {
- halbtc8703b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
- miracast_plus_bt = false;
- }
- btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
- &miracast_plus_bt);
- halbtc8703b1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
- bt_ctrl_agg_buf_size, agg_buf_size);
-
- if (coex_sta->c2h_bt_inquiry_page) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], BT Is Inquirying\n");
- BTC_TRACE(trace_buf);
- halbtc8703b1ant_action_bt_inquiry(btcoexist);
- } else
- halbtc8703b1ant_action_wifi_multi_port(btcoexist);
-
- return;
- } else {
- miracast_plus_bt = false;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
- &miracast_plus_bt);
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- if ((bt_link_info->bt_link_exist) && (wifi_connected)) {
- halbtc8703b1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, 0, 1);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer);
-
- if (BTC_IOT_PEER_CISCO != iot_peer) {
- if (bt_link_info->sco_exist) /* if (bt_link_info->bt_hi_pri_link_exist) */
- halbtc8703b1ant_limited_rx(btcoexist,
- NORMAL_EXEC, true, false, 0x5);
- else
- halbtc8703b1ant_limited_rx(btcoexist,
- NORMAL_EXEC, false, false, 0x5);
- } else {
- if (bt_link_info->sco_exist)
- halbtc8703b1ant_limited_rx(btcoexist,
- NORMAL_EXEC, true, false, 0x5);
- else {
- if (BTC_WIFI_BW_HT40 == wifi_bw)
- halbtc8703b1ant_limited_rx(btcoexist,
- NORMAL_EXEC, false, true, 0x10);
- else
- halbtc8703b1ant_limited_rx(btcoexist,
- NORMAL_EXEC, false, true, 0x8);
- }
- }
-
- halbtc8703b1ant_sw_mechanism(btcoexist, true);
- halbtc8703b1ant_run_sw_coexist_mechanism(
- btcoexist); /* just print debug message */
- } else {
- halbtc8703b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
-
- halbtc8703b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
- 0x5);
-
- halbtc8703b1ant_sw_mechanism(btcoexist, false);
- halbtc8703b1ant_run_sw_coexist_mechanism(
- btcoexist); /* just print debug message */
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- if (coex_sta->c2h_bt_inquiry_page) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], BT Is Inquirying\n");
- BTC_TRACE(trace_buf);
- halbtc8703b1ant_action_bt_inquiry(btcoexist);
- return;
- } else if (bt_hs_on) {
- halbtc8703b1ant_action_hs(btcoexist);
- return;
- }
-
-
- if (!wifi_connected) {
- boolean scan = false, link = false, roam = false;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], wifi is non connected-idle !!!\n");
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
-
- if (scan || link || roam) {
- if (scan)
- halbtc8703b1ant_action_wifi_not_connected_scan(
- btcoexist);
- else
- halbtc8703b1ant_action_wifi_not_connected_asso_auth(
- btcoexist);
- } else
- halbtc8703b1ant_action_wifi_not_connected(btcoexist);
- } else /* wifi LPS/Busy */
- halbtc8703b1ant_action_wifi_connected(btcoexist);
-}
-
-u32 halbtc8703b1ant_psd_log2base(IN struct btc_coexist *btcoexist, IN u32 val)
-{
- u8 j;
- u32 tmp, tmp2, val_integerd_b = 0, tindex, shiftcount = 0;
- u32 result, val_fractiond_b = 0, table_fraction[21] = {0, 432, 332, 274, 232, 200,
- 174, 151, 132, 115, 100, 86, 74, 62, 51, 42,
- 32, 23, 15, 7, 0
- };
-
- if (val == 0)
- return 0;
-
- tmp = val;
-
- while (1) {
- if (tmp == 1)
- break;
- else {
- tmp = (tmp >> 1);
- shiftcount++;
- }
- }
-
-
- val_integerd_b = shiftcount + 1;
-
- tmp2 = 1;
- for (j = 1; j <= val_integerd_b; j++)
- tmp2 = tmp2 * 2;
-
- tmp = (val * 100) / tmp2;
- tindex = tmp / 5;
-
- if (tindex > 20)
- tindex = 20;
-
- val_fractiond_b = table_fraction[tindex];
-
- result = val_integerd_b * 100 - val_fractiond_b;
-
- return result;
-
-
-}
-
-void halbtc8703b1ant_init_coex_dm(IN struct btc_coexist *btcoexist)
-{
- /* force to reset coex mechanism */
-
- /* sw all off */
- halbtc8703b1ant_sw_mechanism(btcoexist, false);
-
- /* halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); */
- /* halbtc8703b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); */
-
- coex_sta->pop_event_cnt = 0;
-}
-
-void halbtc8703b1ant_init_hw_config(IN struct btc_coexist *btcoexist,
- IN boolean back_up, IN boolean wifi_only)
-{
- u32 u32tmp0 = 0, u32tmp1 = 0, u32tmp2 = 0;
-
- u32tmp0 = btcoexist->btc_read_4byte(btcoexist, 0x70),
- u32tmp1 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
- u32tmp2 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "\n [BTCoex], ********** 0x70/ 0x38/ 0x54 (Before Init HW config) = 0x%x/ 0x%x/ 0x%x**********\n",
- u32tmp0,
- u32tmp1, u32tmp2);
- BTC_TRACE(trace_buf);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], 1Ant Init HW Config!!\n");
- BTC_TRACE(trace_buf);
-
- /* 0xf0[15:12] --> Chip Cut information */
- coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist,
- 0xf1) & 0xf0) >> 4;
-
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8,
- 0x1); /* enable TBTT nterrupt */
-
- /* BT report packet sample rate */
- btcoexist->btc_write_1byte(btcoexist, 0x790, 0x5);
-
- /* Enable BT counter statistics */
- btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1);
-
- /* Enable PTA (3-wire function form BT side) */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x41, 0x02, 0x1);
-
- /* Enable PTA (tx/rx signal form WiFi side) */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4c6, 0x10, 0x1);
-
- halbtc8703b1ant_enable_gnt_to_gpio(btcoexist, FALSE);
-
- if (btcoexist->btc_read_1byte(btcoexist, 0x80) == 0xc6)
- halbtc8703b1ant_post_onoffState_to_bt(btcoexist, true);
-
- halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8);
-
- /* Antenna config */
- if (wifi_only) {
- coex_sta->concurrent_rx_mode_on = false;
- halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_WIFI,
- FORCE_EXEC, true, false);
- halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_WIFI,
- FORCE_EXEC, false, false);
- } else {
- coex_sta->concurrent_rx_mode_on = true;
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x2, 0x1);
- /* RF 0x1[0] = 0->Set GNT_WL_RF_Rx always = 1 for con-current Rx */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0x1, 0x0);
- halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT,
- FORCE_EXEC, true, false);
- }
-
- /* PTA parameter */
- halbtc8703b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
-
- u32tmp0 = btcoexist->btc_read_4byte(btcoexist, 0x70),
- u32tmp1 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
- u32tmp2 = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** 0x70/ 0x38/ 0x54 (After Init HW config) = 0x%x/ 0x%x/ 0x%x**********\n",
- u32tmp0,
- u32tmp1, u32tmp2);
- BTC_TRACE(trace_buf);
-
-}
-
-
-
-void halbtc8703b1ant_psd_showdata(IN struct btc_coexist *btcoexist)
-{
- u8 *cli_buf = btcoexist->cli_buf;
- u32 delta_freq_per_point;
- u32 freq, freq1, freq2, n = 0, i = 0, j = 0, m = 0, psd_rep1, psd_rep2;
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n\n============[PSD info] (%d)============\n",
- psd_scan->psd_gen_count);
- CL_PRINTF(cli_buf);
-
- if (psd_scan->psd_gen_count == 0) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n No data !!\n");
- CL_PRINTF(cli_buf);
- return;
- }
-
- if (psd_scan->psd_point == 0)
- delta_freq_per_point = 0;
- else
- delta_freq_per_point = psd_scan->psd_band_width /
- psd_scan->psd_point;
-
- /* if (psd_scan->is_psd_show_max_only) */
- if (0) {
- psd_rep1 = psd_scan->psd_max_value / 100;
- psd_rep2 = psd_scan->psd_max_value - psd_rep1 * 100;
-
- freq = ((psd_scan->real_cent_freq - 20) * 1000000 +
- psd_scan->psd_max_value_point * delta_freq_per_point);
- freq1 = freq / 1000000;
- freq2 = freq / 1000 - freq1 * 1000;
-
- if (freq2 < 100)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n Freq = %d.0%d MHz",
- freq1, freq2);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n Freq = %d.%d MHz",
- freq1, freq2);
-
- if (psd_rep2 < 10)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- ", Value = %d.0%d dB, (%d)\n",
- psd_rep1, psd_rep2, psd_scan->psd_max_value);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- ", Value = %d.%d dB, (%d)\n",
- psd_rep1, psd_rep2, psd_scan->psd_max_value);
-
- CL_PRINTF(cli_buf);
- } else {
- m = psd_scan->psd_start_point;
- n = psd_scan->psd_start_point;
- i = 1;
- j = 1;
-
- while (1) {
- do {
- freq = ((psd_scan->real_cent_freq - 20) * 1000000 + m *
- delta_freq_per_point);
- freq1 = freq / 1000000;
- freq2 = freq / 1000 - freq1 * 1000;
-
- if (i == 1) {
- if (freq2 == 0)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n Freq%6d.000", freq1);
- else if (freq2 < 100)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n Freq%6d.0%2d", freq1,
- freq2);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n Freq%6d.%3d", freq1,
- freq2);
- } else if ((i % 8 == 0) ||
- (m == psd_scan->psd_stop_point)) {
- if (freq2 == 0)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%6d.000\n", freq1);
- else if (freq2 < 100)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%6d.0%2d\n", freq1, freq2);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%6d.%3d\n", freq1, freq2);
- } else {
- if (freq2 == 0)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%6d.000", freq1);
- else if (freq2 < 100)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%6d.0%2d", freq1, freq2);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%6d.%3d", freq1, freq2);
- }
-
- i++;
- m++;
- CL_PRINTF(cli_buf);
-
- } while ((i <= 8) && (m <= psd_scan->psd_stop_point));
-
-
- do {
- psd_rep1 = psd_scan->psd_report_max_hold[n] / 100;
- psd_rep2 = psd_scan->psd_report_max_hold[n] - psd_rep1 *
- 100;
-
- if (j == 1) {
- if (psd_rep2 < 10)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n Val %7d.0%d", psd_rep1,
- psd_rep2);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n Val %7d.%d", psd_rep1,
- psd_rep2);
- } else if ((j % 8 == 0) ||
- (n == psd_scan->psd_stop_point)) {
- if (psd_rep2 < 10)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%7d.0%d\n", psd_rep1,
- psd_rep2);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%7d.%d\n", psd_rep1, psd_rep2);
- } else {
- if (psd_rep2 < 10)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%7d.0%d", psd_rep1, psd_rep2);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%7d.%d", psd_rep1, psd_rep2);
- }
-
- j++;
- n++;
- CL_PRINTF(cli_buf);
-
- } while ((j <= 8) && (n <= psd_scan->psd_stop_point));
-
- if ((m > psd_scan->psd_stop_point) ||
- (n > psd_scan->psd_stop_point))
- break;
- else {
- i = 1;
- j = 1;
- }
-
- }
- }
-
-
-}
-
-void halbtc8703b1ant_psd_maxholddata(IN struct btc_coexist *btcoexist,
- IN u32 gen_count)
-{
- u32 i = 0, i_max = 0, val_max = 0;
-
- if (gen_count == 1) {
- memcpy(psd_scan->psd_report_max_hold,
- psd_scan->psd_report,
- BT_8703B_1ANT_ANTDET_PSD_POINTS * sizeof(u32));
-
- for (i = psd_scan->psd_start_point;
- i <= psd_scan->psd_stop_point; i++) {
-
- }
-
- psd_scan->psd_max_value_point = 0;
- psd_scan->psd_max_value = 0;
-
- } else {
- for (i = psd_scan->psd_start_point;
- i <= psd_scan->psd_stop_point; i++) {
- if (psd_scan->psd_report[i] >
- psd_scan->psd_report_max_hold[i])
- psd_scan->psd_report_max_hold[i] =
- psd_scan->psd_report[i];
-
- /* search Max Value */
- if (i == psd_scan->psd_start_point) {
- i_max = i;
- val_max = psd_scan->psd_report_max_hold[i];
- } else {
- if (psd_scan->psd_report_max_hold[i] >
- val_max) {
- i_max = i;
- val_max = psd_scan->psd_report_max_hold[i];
- }
- }
-
-
- }
-
- psd_scan->psd_max_value_point = i_max;
- psd_scan->psd_max_value = val_max;
-
- }
-
-
-}
-
-u32 halbtc8703b1ant_psd_getdata(IN struct btc_coexist *btcoexist, IN u32 point)
-{
- /* reg 0x808[9:0]: FFT data x */
- /* reg 0x808[22]: 0-->1 to get 1 FFT data y */
- /* reg 0x8b4[15:0]: FFT data y report */
-
- u32 val = 0, psd_report = 0;
-
- val = btcoexist->btc_read_4byte(btcoexist, 0x808);
-
- val &= 0xffbffc00;
- val |= point;
-
- btcoexist->btc_write_4byte(btcoexist, 0x808, val);
-
- val |= 0x00400000;
- btcoexist->btc_write_4byte(btcoexist, 0x808, val);
-
-
- val = btcoexist->btc_read_4byte(btcoexist, 0x8b4);
-
- psd_report = val & 0x0000ffff;
-
- return psd_report;
-}
-
-
-boolean halbtc8703b1ant_psd_sweep_point(IN struct btc_coexist *btcoexist,
- IN u32 cent_freq, IN s32 offset, IN u32 span, IN u32 points,
- IN u32 avgnum, IN u32 loopcnt)
-{
- u32 i = 0, val = 0, n = 0, k = 0, j, point_index = 0;
- u32 points1 = 0, psd_report = 0;
- u32 start_p = 0, stop_p = 0, delta_freq_per_point = 156250;
- u32 psd_center_freq = 20 * 10 ^ 6;
- boolean outloop = false, scan , roam, is_sweep_ok = true;
- u8 flag = 0;
- u32 tmp = 0, u32tmp1 = 0;
- u32 wifi_original_channel = 1;
-
- psd_scan->is_psd_running = true;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx PSD Sweep Start!!\n");
- BTC_TRACE(trace_buf);
-
- do {
- switch (flag) {
- case 0: /* Get PSD parameters */
- default:
-
- psd_scan->psd_band_width = 40 * 1000000;
- psd_scan->psd_point = points;
- psd_scan->psd_start_base = points / 2;
- psd_scan->psd_avg_num = avgnum;
- psd_scan->real_cent_freq = cent_freq;
- psd_scan->real_offset = offset;
- psd_scan->real_span = span;
-
-
- points1 = psd_scan->psd_point;
- delta_freq_per_point = psd_scan->psd_band_width /
- psd_scan->psd_point;
-
- /* PSD point setup */
- val = btcoexist->btc_read_4byte(btcoexist, 0x808);
- val &= 0xffff0fff;
-
- switch (psd_scan->psd_point) {
- case 128:
- val |= 0x0;
- break;
- case 256:
- default:
- val |= 0x00004000;
- break;
- case 512:
- val |= 0x00008000;
- break;
- case 1024:
- val |= 0x0000c000;
- break;
- }
-
- switch (psd_scan->psd_avg_num) {
- case 1:
- val |= 0x0;
- break;
- case 8:
- val |= 0x00001000;
- break;
- case 16:
- val |= 0x00002000;
- break;
- case 32:
- default:
- val |= 0x00003000;
- break;
- }
- btcoexist->btc_write_4byte(btcoexist, 0x808, val);
-
- flag = 1;
- break;
- case 1: /* calculate the PSD point index from freq/offset/span */
- psd_center_freq = psd_scan->psd_band_width / 2 +
- offset * (1000000);
-
- start_p = psd_scan->psd_start_base + (psd_center_freq -
- span * (1000000) / 2) / delta_freq_per_point;
- psd_scan->psd_start_point = start_p -
- psd_scan->psd_start_base;
-
- stop_p = psd_scan->psd_start_base + (psd_center_freq +
- span * (1000000) / 2) / delta_freq_per_point;
- psd_scan->psd_stop_point = stop_p -
- psd_scan->psd_start_base - 1;
-
- flag = 2;
- break;
- case 2: /* set RF channel/BW/Mode */
-
- /* set 3-wire off */
- val = btcoexist->btc_read_4byte(btcoexist, 0x88c);
- val |= 0x00300000;
- btcoexist->btc_write_4byte(btcoexist, 0x88c, val);
-
- /* CCK off */
- val = btcoexist->btc_read_4byte(btcoexist, 0x800);
- val &= 0xfeffffff;
- btcoexist->btc_write_4byte(btcoexist, 0x800, val);
-
- /* Tx-pause on */
- btcoexist->btc_write_1byte(btcoexist, 0x522, 0x6f);
-
- /* store WiFi original channel */
- wifi_original_channel = btcoexist->btc_get_rf_reg(
- btcoexist, BTC_RF_A, 0x18, 0x3ff);
-
- /* Set RF channel */
- if (cent_freq == 2484)
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A,
- 0x18, 0x3ff, 0xe);
- else
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A,
- 0x18, 0x3ff, (cent_freq - 2412) / 5 +
- 1); /* WiFi TRx Mask on */
-
- /* save original RCK value */
- u32tmp1 = btcoexist->btc_get_rf_reg(
- btcoexist, BTC_RF_A, 0x1d, 0xfffff);
-
- /* Enter debug mode */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xde,
- 0x2, 0x1);
-
- /* Set RF Rx filter corner */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1d,
- 0xfffff, 0x2e);
-
-
- /* Set RF mode = Rx, RF Gain = 0x320a0 */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x0,
- 0xfffff, 0x320a0);
-
- while (1) {
- if (k++ > BT_8703B_1ANT_ANTDET_SWEEPPOINT_DELAY)
- break;
- }
- flag = 3;
- break;
- case 3:
- psd_scan->psd_gen_count = 0;
- for (j = 1; j <= loopcnt; j++) {
-
- btcoexist->btc_get(btcoexist,
- BTC_GET_BL_WIFI_SCAN, &scan);
- btcoexist->btc_get(btcoexist,
- BTC_GET_BL_WIFI_ROAM, &roam);
-
- if (scan || roam) {
- is_sweep_ok = false;
- break;
- }
- memset(psd_scan->psd_report, 0,
- psd_scan->psd_point * sizeof(u32));
- start_p = psd_scan->psd_start_point +
- psd_scan->psd_start_base;
- stop_p = psd_scan->psd_stop_point +
- psd_scan->psd_start_base + 1;
-
- i = start_p;
- point_index = 0;
-
- while (i < stop_p) {
- if (i >= points1)
- psd_report =
- halbtc8703b1ant_psd_getdata(
- btcoexist, i - points1);
- else
- psd_report =
- halbtc8703b1ant_psd_getdata(
- btcoexist, i);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "Point=%d, psd_raw_data = 0x%08x\n",
- i, psd_report);
- BTC_TRACE(trace_buf);
- if (psd_report == 0)
- tmp = 0;
- else
- /* tmp = 20*log10((double)psd_report); */
- /* 20*log2(x)/log2(10), log2Base return theresult of the psd_report*100 */
- tmp = 6 * halbtc8703b1ant_psd_log2base(
- btcoexist, psd_report);
-
- n = i - psd_scan->psd_start_base;
- psd_scan->psd_report[n] = tmp;
-
-
- halbtc8703b1ant_psd_maxholddata(
- btcoexist, j);
-
- i++;
-
- }
-
- psd_scan->psd_gen_count = j;
- }
-
- flag = 100;
- break;
- case 99: /* error */
-
- outloop = true;
- break;
- case 100: /* recovery */
-
- /* set 3-wire on */
- val = btcoexist->btc_read_4byte(btcoexist, 0x88c);
- val &= 0xffcfffff;
- btcoexist->btc_write_4byte(btcoexist, 0x88c, val);
-
- /* CCK on */
- val = btcoexist->btc_read_4byte(btcoexist, 0x800);
- val |= 0x01000000;
- btcoexist->btc_write_4byte(btcoexist, 0x800, val);
-
- /* Tx-pause off */
- btcoexist->btc_write_1byte(btcoexist, 0x522, 0x0);
-
- /* PSD off */
- val = btcoexist->btc_read_4byte(btcoexist, 0x808);
- val &= 0xffbfffff;
- btcoexist->btc_write_4byte(btcoexist, 0x808, val);
-
- /* restore RF Rx filter corner */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1d,
- 0xfffff, u32tmp1);
-
- /* Exit debug mode */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xde,
- 0x2, 0x0);
-
- /* restore WiFi original channel */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x18,
- 0x3ff, wifi_original_channel);
-
- outloop = true;
- break;
-
- }
-
- } while (!outloop);
-
-
-
- psd_scan->is_psd_running = false;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx PSD Sweep Stop!!\n");
- BTC_TRACE(trace_buf);
- return is_sweep_ok;
-
-}
-
-/* ************************************************************
- * work around function start with wa_halbtc8703b1ant_
- * ************************************************************
- * ************************************************************
- * extern function start with ex_halbtc8703b1ant_
- * ************************************************************ */
-void ex_halbtc8703b1ant_power_on_setting(IN struct btc_coexist *btcoexist)
-{
- struct btc_board_info *board_info = &btcoexist->board_info;
- u8 u8tmp = 0x0;
- u16 u16tmp = 0x0;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx Execute 8703b 1-Ant PowerOn Setting xxxxxxxxxxxxxxxx!!\n");
- BTC_TRACE(trace_buf);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "Ant Det Finish = %s, Ant Det Number = %d\n",
- (board_info->btdm_ant_det_finish ? "Yes" : "No"),
- board_info->btdm_ant_num_by_ant_det);
- BTC_TRACE(trace_buf);
-
- btcoexist->stop_coex_dm = true;
-
- /* enable BB, REG_SYS_FUNC_EN such that we can write BB/MAC reg correctly. */
- u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2);
- btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1));
-
- /* set Path control owner to WiFi */
- halbtc8703b1ant_ltecoex_pathcontrol_owner(btcoexist,
- BT_8703B_1ANT_PCO_WLSIDE);
-
- /* set GNT_BT to high */
- halbtc8703b1ant_ltecoex_set_gnt_bt(btcoexist,
- BT_8703B_1ANT_GNT_BLOCK_RFC_BB,
- BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW,
- BT_8703B_1ANT_SIG_STA_SET_TO_HIGH);
- /* Set GNT_WL to low */
- halbtc8703b1ant_ltecoex_set_gnt_wl(btcoexist,
- BT_8703B_1ANT_GNT_BLOCK_RFC_BB,
- BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW,
- BT_8703B_1ANT_SIG_STA_SET_TO_LOW);
-
- /* set WLAN_ACT = 0 */
- btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4);
-
- halbtc8703b1ant_enable_gnt_to_gpio(btcoexist, FALSE);
-
- /* */
- /* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */
- /* Local setting bit define */
- /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */
- /* BIT1: "0" for internal switch; "1" for external switch */
- /* BIT2: "0" for one antenna; "1" for two antenna */
- /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */
-
- u8tmp = 0;
- board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;
-
- if (btcoexist->chip_interface == BTC_INTF_USB)
- btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp);
- else if (btcoexist->chip_interface == BTC_INTF_SDIO)
- btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, u8tmp);
-
-
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** 0x70(MAC)/0x38/0x54 (Power-On) =0x%x/ 0x%x/ 0x%x**********\n",
- btcoexist->btc_read_4byte(btcoexist, 0x70),
- halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38),
- halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54));
- BTC_TRACE(trace_buf);
-
-
-}
-
-void ex_halbtc8703b1ant_pre_load_firmware(IN struct btc_coexist *btcoexist)
-{
-}
-
-void ex_halbtc8703b1ant_init_hw_config(IN struct btc_coexist *btcoexist,
- IN boolean wifi_only)
-{
- halbtc8703b1ant_init_hw_config(btcoexist, true, wifi_only);
- btcoexist->stop_coex_dm = false;
-}
-
-void ex_halbtc8703b1ant_init_coex_dm(IN struct btc_coexist *btcoexist)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Coex Mechanism Init!!\n");
- BTC_TRACE(trace_buf);
-
- halbtc8703b1ant_init_coex_dm(btcoexist);
-}
-
-void ex_halbtc8703b1ant_display_coex_info(IN struct btc_coexist *btcoexist)
-{
- struct btc_board_info *board_info = &btcoexist->board_info;
- struct btc_stack_info *stack_info = &btcoexist->stack_info;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- u8 *cli_buf = btcoexist->cli_buf;
- u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0;
- u16 u16tmp[4];
- u32 u32tmp[4];
- u32 fa_of_dm, fa_cck;
- u32 fw_ver = 0, bt_patch_ver = 0;
- static u8 pop_report_in_10s = 0;
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ============[BT Coexist info]============");
- CL_PRINTF(cli_buf);
-
- if (btcoexist->manual_control) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ============[Under Manual Control]============");
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ==========================================");
- CL_PRINTF(cli_buf);
- }
- if (btcoexist->stop_coex_dm) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ============[Coex is STOPPED]============");
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ==========================================");
- CL_PRINTF(cli_buf);
- }
-
- if (psd_scan->ant_det_try_count == 0) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d",
- "Ant PG Num/ Mech/ Pos",
- board_info->pg_ant_num, board_info->btdm_ant_num,
- board_info->btdm_ant_pos);
- CL_PRINTF(cli_buf);
- } else {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %d/ %d/ %d (%d/%d/%d)",
- "Ant PG Num/ Mech(Ant_Det)/ Pos",
- board_info->pg_ant_num, board_info->btdm_ant_num_by_ant_det,
- board_info->btdm_ant_pos,
- psd_scan->ant_det_try_count, psd_scan->ant_det_fail_count,
- psd_scan->ant_det_result);
- CL_PRINTF(cli_buf);
-
- if (board_info->btdm_ant_det_finish) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
- "Ant Det PSD Value",
- psd_scan->ant_det_peak_val);
- CL_PRINTF(cli_buf);
- }
- }
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d",
- "BT stack/ hci ext ver",
- ((stack_info->profile_notified) ? "Yes" : "No"),
- stack_info->hci_version);
- CL_PRINTF(cli_buf);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %d_%x/ 0x%x/ 0x%x(%d)/ %c",
- "Version Coex/ Fw/ Patch/ Cut",
- glcoex_ver_date_8703b_1ant, glcoex_ver_8703b_1ant, fw_ver,
- bt_patch_ver, bt_patch_ver, coex_sta->cut_version + 65);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ",
- "Wifi channel informed to BT",
- coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
- coex_dm->wifi_chnl_info[2]);
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s",
- "WifibHiPri/ Ccklock/ CckEverLock",
- (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"),
- (coex_sta->cck_lock ? "Yes" : "No"),
- (coex_sta->cck_ever_lock ? "Yes" : "No"));
- CL_PRINTF(cli_buf);
-
- /* wifi status */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Wifi Status]============");
- CL_PRINTF(cli_buf);
- btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[BT Status]============");
- CL_PRINTF(cli_buf);
-
- pop_report_in_10s++;
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d/ %d] ",
- "BT [status/ rssi/ retryCnt/ popCnt]",
- ((coex_sta->bt_disabled) ? ("disabled") : ((
- coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page")
- : ((BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
- coex_dm->bt_status) ? "non-connected idle" :
- ((BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)
- ? "connected-idle" : "busy")))),
- coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt,
- coex_sta->pop_event_cnt);
- CL_PRINTF(cli_buf);
-
- if (pop_report_in_10s >= 5) {
- coex_sta->pop_event_cnt = 0;
- pop_report_in_10s = 0;
- }
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %d / %d / %d / %d / %d",
- "SCO/HID/PAN/A2DP/Hi-Pri",
- bt_link_info->sco_exist, bt_link_info->hid_exist,
- bt_link_info->pan_exist, bt_link_info->a2dp_exist,
- bt_link_info->bt_hi_pri_link_exist);
- CL_PRINTF(cli_buf);
-
- if (stack_info->profile_notified)
- btcoexist->btc_disp_dbg_msg(btcoexist,
- BTC_DBG_DISP_BT_LINK_INFO);
- else {
- bt_info_ext = coex_sta->bt_info_ext;
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %s / %d",
- "Role/A2DP Rate/Bitpool",
- ((bt_link_info->slave_role) ? "Slave" : "Master"),
- (bt_info_ext & BIT(0)) ? "BR" : "EDR", coex_sta->a2dp_bit_pool);
- CL_PRINTF(cli_buf);
- }
-
-
- for (i = 0; i < BT_INFO_SRC_8703B_1ANT_MAX; i++) {
- if (coex_sta->bt_info_c2h_cnt[i]) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)",
- glbt_info_src_8703b_1ant[i],
- coex_sta->bt_info_c2h[i][0],
- coex_sta->bt_info_c2h[i][1],
- coex_sta->bt_info_c2h[i][2],
- coex_sta->bt_info_c2h[i][3],
- coex_sta->bt_info_c2h[i][4],
- coex_sta->bt_info_c2h[i][5],
- coex_sta->bt_info_c2h[i][6],
- coex_sta->bt_info_c2h_cnt[i]);
- CL_PRINTF(cli_buf);
- }
- }
-
- if (btcoexist->manual_control)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[mechanisms] (before Manual)============");
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[mechanisms]============");
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
- "SM[LowPenaltyRA]",
- coex_dm->cur_low_penalty_ra);
- CL_PRINTF(cli_buf);
-
- ps_tdma_case = coex_dm->cur_ps_tdma;
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (%s,%s)",
- "PS TDMA",
- coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],
- coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],
- coex_dm->ps_tdma_para[4], ps_tdma_case,
- (coex_dm->cur_ps_tdma_on ? "On" : "Off"),
- (coex_dm->auto_tdma_adjust ? "Adj" : "Fix"));
-
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
- "WL/BT Coex Table Type",
- coex_sta->coex_table_type);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
- u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
- "0x6c0/0x6c4/0x6c8(coexTable)",
- u32tmp[0], u32tmp[1], u32tmp[2]);
- CL_PRINTF(cli_buf);
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
- "0x778/0x6cc/IgnWlanAct",
- u8tmp[0], u32tmp[0], coex_dm->cur_ignore_wlan_act);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist,
- 0xa0);
- u32tmp[1] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist,
- 0xa4);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
- "LTE Coex Table W_L/B_L",
- u32tmp[0] & 0xffff, u32tmp[1] & 0xffff);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist,
- 0xa8);
- u32tmp[1] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist,
- 0xac);
- u32tmp[2] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist,
- 0xb0);
- u32tmp[3] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist,
- 0xb4);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
- "LTE Break Table W_L/B_L/L_W/L_B",
- u32tmp[0] & 0xffff, u32tmp[1] & 0xffff,
- u32tmp[2] & 0xffff, u32tmp[3] & 0xffff);
- CL_PRINTF(cli_buf);
-
- /* Hw setting */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Hw setting]============");
- CL_PRINTF(cli_buf);
-
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434);
- u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x",
- "0x430/0x434/0x42a/0x456",
- u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]);
- CL_PRINTF(cli_buf);
-
-
- u32tmp[0] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %s",
- "LTE CoexOn/Path Ctrl Owner",
- (int)((u32tmp[0] & BIT(7)) >> 7), ((u8tmp[0] & BIT(2)) ? "WL" : "BT"));
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
- "LTE 3Wire/OPMode/UART/UARTMode",
- (int)((u32tmp[0] & BIT(6)) >> 6), (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4),
- (int)((u32tmp[0] & BIT(3)) >> 3),
- (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0))));
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %s",
- "GNT_WL_SWCtrl/GNT_BT_SWCtrl/Dbg",
- (int)((u32tmp[0] & BIT(12)) >> 12), (int)((u32tmp[0] & BIT(14)) >> 14),
- ((u8tmp[0] & BIT(3)) ? "On" : "Off"));
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = halbtc8703b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
- "GNT_WL/GNT_BT/LTE_Busy/UART_Busy",
- (int)((u32tmp[0] & BIT(2)) >> 2), (int)((u32tmp[0] & BIT(3)) >> 3),
- (int)((u32tmp[0] & BIT(1)) >> 1), (int)(u32tmp[0] & BIT(0)));
- CL_PRINTF(cli_buf);
-
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
- "0x4c6[4]/0x40[5] (WL/BT PTA)",
- (int)((u8tmp[0] & BIT(4)) >> 4), (int)((u8tmp[1] & BIT(5)) >> 5));
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x953);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ %s",
- "0x550(bcn ctrl)/0x522/4-RxAGC",
- u32tmp[0], u8tmp[0], (u8tmp[1] & 0x2) ? "On" : "Off");
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xda0);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xda4);
- u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0xda8);
- u32tmp[3] = btcoexist->btc_read_4byte(btcoexist, 0xcf0);
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xa5b);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xa5c);
-
- fa_of_dm = ((u32tmp[0] & 0xffff0000) >> 16) + ((u32tmp[1] & 0xffff0000)
- >> 16) + (u32tmp[1] & 0xffff) + (u32tmp[2] & 0xffff) +
- ((u32tmp[3] & 0xffff0000) >> 16) + (u32tmp[3] &
- 0xffff) ;
- fa_cck = (u8tmp[0] << 8) + u8tmp[1];
-
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xc50);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
- "0xc50/OFDM-CCA/OFDM-FA/CCK-FA",
- u32tmp[1] & 0xff, u32tmp[0] & 0xffff, fa_of_dm, fa_cck);
- CL_PRINTF(cli_buf);
-
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
- "CRC_OK CCK/11g/11n/11n-Agg",
- coex_sta->crc_ok_cck, coex_sta->crc_ok_11g,
- coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_agg);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
- "CRC_Err CCK/11g/11n/11n-Agg",
- coex_sta->crc_err_cck, coex_sta->crc_err_11g,
- coex_sta->crc_err_11n, coex_sta->crc_err_11n_agg);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
- "0x770(high-pri rx/tx)",
- coex_sta->high_priority_rx, coex_sta->high_priority_tx);
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
- "0x774(low-pri rx/tx)",
- coex_sta->low_priority_rx, coex_sta->low_priority_tx);
- CL_PRINTF(cli_buf);
-
- halbtc8703b1ant_read_score_board(btcoexist, &u16tmp[0]);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %04x",
- "ScoreBoard[14:0] (from BT)", u16tmp[0]);
- CL_PRINTF(cli_buf);
-
-
- btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
-}
-
-
-void ex_halbtc8703b1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type)
-{
- if (btcoexist->manual_control || btcoexist->stop_coex_dm)
- return;
-
- if (BTC_IPS_ENTER == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], IPS ENTER notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_ips = true;
- coex_sta->under_lps = false;
-
- /* Write WL "Active" in Score-board for LPS off */
- halbtc8703b1ant_post_activestate_to_bt(btcoexist, false);
-
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT,
- FORCE_EXEC, false, true);
- halbtc8703b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
- } else if (BTC_IPS_LEAVE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], IPS LEAVE notify\n");
- BTC_TRACE(trace_buf);
- halbtc8703b1ant_post_activestate_to_bt(btcoexist, true);
-
- halbtc8703b1ant_init_hw_config(btcoexist, false, false);
- halbtc8703b1ant_init_coex_dm(btcoexist);
- halbtc8703b1ant_query_bt_info(btcoexist);
-
- coex_sta->under_ips = false;
- }
-}
-
-void ex_halbtc8703b1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type)
-{
- if (btcoexist->manual_control || btcoexist->stop_coex_dm)
- return;
-
- if (BTC_LPS_ENABLE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], LPS ENABLE notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_lps = true;
- coex_sta->under_ips = false;
-
- if (coex_sta->force_lps_on == true) { /* LPS No-32K */
- /* Write WL "Active" in Score-board for PS-TDMA */
- halbtc8703b1ant_post_activestate_to_bt(btcoexist, true);
-
- } else { /* LPS-32K, need check if this h2c 0x71 can work?? (2015/08/28) */
- /* Write WL "Non-Active" in Score-board for Native-PS */
- halbtc8703b1ant_post_activestate_to_bt(btcoexist, false);
-
- }
- } else if (BTC_LPS_DISABLE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], LPS DISABLE notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_lps = false;
-
-
- /* Write WL "Active" in Score-board for LPS off */
- halbtc8703b1ant_post_activestate_to_bt(btcoexist, true);
-
- }
-}
-
-void ex_halbtc8703b1ant_scan_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- boolean wifi_connected = false;
-
- if (btcoexist->manual_control ||
- btcoexist->stop_coex_dm)
- return;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
-
- halbtc8703b1ant_query_bt_info(btcoexist);
-
- if (BTC_SCAN_START == type) {
-
- coex_sta->wifi_is_high_pri_task = true;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCAN START notify\n");
- BTC_TRACE(trace_buf);
-
- halbtc8703b1ant_post_activestate_to_bt(btcoexist, true);
- halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false,
- 8);
-
- /* Force antenna setup for no scan result issue */
- halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
- FORCE_EXEC, false, false);
-
- if (!wifi_connected) /* non-connected scan */
- halbtc8703b1ant_action_wifi_not_connected_scan(btcoexist);
- else /* wifi is connected */
- halbtc8703b1ant_action_wifi_connected_scan(btcoexist);
-
- } else {
-
- coex_sta->wifi_is_high_pri_task = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
- &coex_sta->scan_ap_num);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCAN FINISH notify (Scan-AP = %d)\n", coex_sta->scan_ap_num);
- BTC_TRACE(trace_buf);
-
- if (!wifi_connected)
- halbtc8703b1ant_action_wifi_not_connected(btcoexist);
- else
- halbtc8703b1ant_action_wifi_connected(btcoexist);
- }
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCAN START Notify() end\n");
- BTC_TRACE(trace_buf);
-
-}
-
-void ex_halbtc8703b1ant_connect_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- boolean wifi_connected = false;
-
- if (btcoexist->manual_control ||
- btcoexist->stop_coex_dm)
- return;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
-
- if (BTC_ASSOCIATE_START == type) {
- coex_sta->wifi_is_high_pri_task = true;
- halbtc8703b1ant_post_activestate_to_bt(btcoexist, true);
- halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false,
- 8);
-
- /* Force antenna setup for no scan result issue */
- halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
- FORCE_EXEC, false, false);
- /* psd_scan->ant_det_is_ant_det_available = TRUE; */
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CONNECT START notify\n");
- BTC_TRACE(trace_buf);
- coex_dm->arp_cnt = 0;
-
- halbtc8703b1ant_action_wifi_not_connected_asso_auth(btcoexist);
- } else {
- coex_sta->wifi_is_high_pri_task = false;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CONNECT FINISH notify\n");
- BTC_TRACE(trace_buf);
-
- if (!wifi_connected) /* non-connected scan */
- halbtc8703b1ant_action_wifi_not_connected(btcoexist);
- else
- halbtc8703b1ant_action_wifi_connected(btcoexist);
- }
-
-}
-
-void ex_halbtc8703b1ant_media_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- boolean wifi_under_b_mode = false;
-
- if (btcoexist->manual_control ||
- btcoexist->stop_coex_dm)
- return;
-
- if (BTC_MEDIA_CONNECT == type) {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], MEDIA connect notify\n");
- BTC_TRACE(trace_buf);
-
- halbtc8703b1ant_post_activestate_to_bt(btcoexist, true);
- halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false,
- 8);
-
- /* Force antenna setup for no scan result issue */
- halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
- FORCE_EXEC, false, false);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
- &wifi_under_b_mode);
-
- /* Set CCK Tx/Rx high Pri except 11b mode */
- if (wifi_under_b_mode) {
- btcoexist->btc_write_1byte(btcoexist, 0x6cd,
- 0x00); /* CCK Tx */
- btcoexist->btc_write_1byte(btcoexist, 0x6cf,
- 0x00); /* CCK Rx */
- } else {
- /* btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x10); */ /*CCK Tx */
- /* btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x10); */ /*CCK Rx */
- btcoexist->btc_write_1byte(btcoexist, 0x6cd,
- 0x00); /* CCK Tx */
- btcoexist->btc_write_1byte(btcoexist, 0x6cf,
- 0x10); /* CCK Rx */
- }
-
- coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist,
- 0x430);
- coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist,
- 0x434);
- coex_dm->backup_retry_limit = btcoexist->btc_read_2byte(
- btcoexist, 0x42a);
- coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte(
- btcoexist, 0x456);
- } else {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], MEDIA disconnect notify\n");
- BTC_TRACE(trace_buf);
-
- halbtc8703b1ant_post_activestate_to_bt(btcoexist, false);
-
- btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */
- btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */
-
- coex_sta->cck_ever_lock = false;
- }
-
- halbtc8703b1ant_update_wifi_channel_info(btcoexist, type);
-
-}
-
-void ex_halbtc8703b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- boolean under_4way = false;
-
- if (btcoexist->manual_control ||
- btcoexist->stop_coex_dm ||
- coex_sta->bt_disabled)
- return;
-
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
- &under_4way);
-
- if (under_4way) {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], specific Packet ---- under_4way!!\n");
- BTC_TRACE(trace_buf);
-
- coex_sta->wifi_is_high_pri_task = true;
- coex_sta->specific_pkt_period_cnt = 2;
- } else if (BTC_PACKET_ARP == type) {
-
- coex_dm->arp_cnt++;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], specific Packet ARP notify -cnt = %d\n", coex_dm->arp_cnt);
- BTC_TRACE(trace_buf);
-
- } else {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n", type);
- BTC_TRACE(trace_buf);
-
- coex_sta->wifi_is_high_pri_task = true;
- coex_sta->specific_pkt_period_cnt = 2;
- }
-
- if (coex_sta->wifi_is_high_pri_task)
- halbtc8703b1ant_action_wifi_connected_specific_packet(btcoexist);
-}
-
-void ex_halbtc8703b1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
- IN u8 *tmp_buf, IN u8 length)
-{
- u8 bt_info = 0;
- u8 i, rsp_source = 0;
- boolean wifi_connected = false;
- boolean bt_busy = false;
-
- coex_sta->c2h_bt_info_req_sent = false;
-
- rsp_source = tmp_buf[0] & 0xf;
- if (rsp_source >= BT_INFO_SRC_8703B_1ANT_MAX)
- rsp_source = BT_INFO_SRC_8703B_1ANT_WIFI_FW;
- coex_sta->bt_info_c2h_cnt[rsp_source]++;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source,
- length);
- BTC_TRACE(trace_buf);
- for (i = 0; i < length; i++) {
- coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
- if (i == 1)
- bt_info = tmp_buf[i];
- if (i == length - 1) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n",
- tmp_buf[i]);
- BTC_TRACE(trace_buf);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ",
- tmp_buf[i]);
- BTC_TRACE(trace_buf);
- }
- }
-
- if (BT_INFO_SRC_8703B_1ANT_WIFI_FW != rsp_source) {
-
- /* if 0xff, it means BT is under WHCK test */
- if (bt_info == 0xff)
- coex_sta->bt_whck_test = true;
- else
- coex_sta->bt_whck_test = false;
-
- coex_sta->bt_retry_cnt = /* [3:0] */
- coex_sta->bt_info_c2h[rsp_source][2] & 0xf;
-
- if (coex_sta->bt_retry_cnt >= 1)
- coex_sta->pop_event_cnt++;
-
- if (coex_sta->bt_info_c2h[rsp_source][2] & 0x20)
- coex_sta->c2h_bt_page = true;
- else
- coex_sta->c2h_bt_page = false;
-
- if (coex_sta->bt_info_c2h[rsp_source][2] & 0x80)
- coex_sta->bt_create_connection = true;
- else
- coex_sta->bt_create_connection = false;
-
- /* unit: %, value-100 to translate to unit: dBm */
- coex_sta->bt_rssi = coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10;
-
- /* coex_sta->bt_info_c2h[rsp_source][3]*2+10; */
-
- if ((coex_sta->bt_info_c2h[rsp_source][1] & 0x49) == 0x49) {
- coex_sta->a2dp_bit_pool =
- coex_sta->bt_info_c2h[rsp_source][6];
- } else
- coex_sta->a2dp_bit_pool = 0;
-
- if (coex_sta->bt_info_c2h[rsp_source][1] & 0x9)
- coex_sta->acl_busy = true;
- else
- coex_sta->acl_busy = false;
-
- coex_sta->bt_info_ext =
- coex_sta->bt_info_c2h[rsp_source][4];
-
- /* Here we need to resend some wifi info to BT */
- /* because bt is reset and loss of the info. */
-
- if ((!btcoexist->manual_control) && (!btcoexist->stop_coex_dm)) {
-
- /* Re-Init */
- if (coex_sta->bt_info_ext & BIT(1)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- if (wifi_connected)
- halbtc8703b1ant_update_wifi_channel_info(btcoexist,
- BTC_MEDIA_CONNECT);
- else
- halbtc8703b1ant_update_wifi_channel_info(btcoexist,
- BTC_MEDIA_DISCONNECT);
- }
-
- /* If Ignore_WLanAct && not SetUp_Link */
- if ((coex_sta->bt_info_ext & BIT(3)) && (!(coex_sta->bt_info_ext & BIT(2)))) {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n");
- BTC_TRACE(trace_buf);
- halbtc8703b1ant_ignore_wlan_act(btcoexist,
- FORCE_EXEC, false);
- }
- }
-
- /* check BIT2 first ==> check if bt is under inquiry or page scan */
- if (bt_info & BT_INFO_8703B_1ANT_B_INQ_PAGE)
- coex_sta->c2h_bt_inquiry_page = true;
- else
- coex_sta->c2h_bt_inquiry_page = false;
-
- }
-
- coex_sta->num_of_profile = 0;
-
- /* set link exist status */
- if (!(bt_info & BT_INFO_8703B_1ANT_B_CONNECTION)) {
- coex_sta->bt_link_exist = false;
- coex_sta->pan_exist = false;
- coex_sta->a2dp_exist = false;
- coex_sta->hid_exist = false;
- coex_sta->sco_exist = false;
-
- coex_sta->bt_hi_pri_link_exist = false;
- } else { /* connection exists */
- coex_sta->bt_link_exist = true;
- if (bt_info & BT_INFO_8703B_1ANT_B_FTP) {
- coex_sta->pan_exist = true;
- coex_sta->num_of_profile++;
- } else
- coex_sta->pan_exist = false;
- if (bt_info & BT_INFO_8703B_1ANT_B_A2DP) {
- coex_sta->a2dp_exist = true;
- coex_sta->num_of_profile++;
- } else
- coex_sta->a2dp_exist = false;
- if (bt_info & BT_INFO_8703B_1ANT_B_HID) {
- coex_sta->hid_exist = true;
- coex_sta->num_of_profile++;
- } else
- coex_sta->hid_exist = false;
- if (bt_info & BT_INFO_8703B_1ANT_B_SCO_ESCO) {
- coex_sta->sco_exist = true;
- coex_sta->num_of_profile++;
- } else
- coex_sta->sco_exist = false;
-
- }
-
-
-
- halbtc8703b1ant_update_bt_link_info(btcoexist);
-
- bt_info = bt_info &
- 0x1f; /* mask profile bit for connect-ilde identification ( for CSR case: A2DP idle --> 0x41) */
-
- if (!(bt_info & BT_INFO_8703B_1ANT_B_CONNECTION)) {
- coex_dm->bt_status = BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n");
- BTC_TRACE(trace_buf);
- } else if (bt_info ==
- BT_INFO_8703B_1ANT_B_CONNECTION) { /* connection exists but no busy */
- coex_dm->bt_status = BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n");
- BTC_TRACE(trace_buf);
- } else if ((bt_info & BT_INFO_8703B_1ANT_B_SCO_ESCO) ||
- (bt_info & BT_INFO_8703B_1ANT_B_SCO_BUSY)) {
- coex_dm->bt_status = BT_8703B_1ANT_BT_STATUS_SCO_BUSY;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n");
- BTC_TRACE(trace_buf);
- } else if (bt_info & BT_INFO_8703B_1ANT_B_ACL_BUSY) {
- if (BT_8703B_1ANT_BT_STATUS_ACL_BUSY != coex_dm->bt_status)
- coex_dm->auto_tdma_adjust = false;
- coex_dm->bt_status = BT_8703B_1ANT_BT_STATUS_ACL_BUSY;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n");
- BTC_TRACE(trace_buf);
- } else {
- coex_dm->bt_status = BT_8703B_1ANT_BT_STATUS_MAX;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n");
- BTC_TRACE(trace_buf);
- }
-
- if ((BT_8703B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
- (BT_8703B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
- (BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status))
- bt_busy = true;
- else
- bt_busy = false;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
-
- if (btcoexist->manual_control) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), No run_coexist_mechanism return for Manual CTRL<===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- if (btcoexist->stop_coex_dm) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), No run_coexist_mechanism return for Stop Coex DM <===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- /* don't run coex mechanism while receve BTInfo if GNT_WL/GNT_BT control by SW */
- if (!coex_sta->gnt_control_by_PTA)
- return;
-
- halbtc8703b1ant_run_coexist_mechanism(btcoexist);
-}
-
-void ex_halbtc8703b1ant_rf_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n");
- BTC_TRACE(trace_buf);
-
- if (BTC_RF_ON == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RF is turned ON!!\n");
- BTC_TRACE(trace_buf);
-
- coex_sta->wl_rf_off_on_event = true;
- btcoexist->stop_coex_dm = false;
-
- halbtc8703b1ant_post_activestate_to_bt(btcoexist, true);
- halbtc8703b1ant_post_onoffState_to_bt(btcoexist, true);
-
- /* halbtc8703b1ant_init_hw_config(btcoexist, false, false); */
- } else if (BTC_RF_OFF == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RF is turned OFF!!\n");
- BTC_TRACE(trace_buf);
- halbtc8703b1ant_post_activestate_to_bt(btcoexist, false);
- halbtc8703b1ant_post_onoffState_to_bt(btcoexist, false);
-
- halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
- halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT,
- FORCE_EXEC, false, true);
-
- btcoexist->stop_coex_dm = true;
- coex_sta->wl_rf_off_on_event = false;
-
- }
-}
-
-void ex_halbtc8703b1ant_halt_notify(IN struct btc_coexist *btcoexist)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n");
- BTC_TRACE(trace_buf);
-
- halbtc8703b1ant_post_activestate_to_bt(btcoexist, false);
- halbtc8703b1ant_post_onoffState_to_bt(btcoexist, false);
-
- halbtc8703b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
- halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, FORCE_EXEC,
- false, true);
-
- ex_halbtc8703b1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
-
- halbtc8703b1ant_enable_gnt_to_gpio(btcoexist, FALSE);
-
- btcoexist->stop_coex_dm = true;
-}
-
-void ex_halbtc8703b1ant_pnp_notify(IN struct btc_coexist *btcoexist,
- IN u8 pnp_state)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n");
- BTC_TRACE(trace_buf);
-
- if (BTC_WIFI_PNP_SLEEP == pnp_state) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Pnp notify to SLEEP\n");
- BTC_TRACE(trace_buf);
-
- halbtc8703b1ant_post_activestate_to_bt(btcoexist, false);
- halbtc8703b1ant_post_onoffState_to_bt(btcoexist, false);
-
- halbtc8703b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- halbtc8703b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT,
- FORCE_EXEC, false, true);
-
- btcoexist->stop_coex_dm = true;
- } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Pnp notify to WAKE UP\n");
- BTC_TRACE(trace_buf);
- halbtc8703b1ant_post_activestate_to_bt(btcoexist, true);
- halbtc8703b1ant_post_onoffState_to_bt(btcoexist, true);
-
- btcoexist->stop_coex_dm = false;
- }
-}
-
-void ex_halbtc8703b1ant_coex_dm_reset(IN struct btc_coexist *btcoexist)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], *****************Coex DM Reset*****************\n");
- BTC_TRACE(trace_buf);
-
- halbtc8703b1ant_init_hw_config(btcoexist, false, false);
- /* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); */
- /* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x2, 0xfffff, 0x0); */
- halbtc8703b1ant_init_coex_dm(btcoexist);
-}
-
-void ex_halbtc8703b1ant_periodical(IN struct btc_coexist *btcoexist)
-{
-
-#if (BT_AUTO_REPORT_ONLY_8703B_1ANT == 0)
- halbtc8703b1ant_query_bt_info(btcoexist);
-#endif
-
- halbtc8703b1ant_monitor_bt_ctr(btcoexist);
- halbtc8703b1ant_monitor_wifi_ctr(btcoexist);
-
- halbtc8703b1ant_monitor_bt_enable_disable(btcoexist);
-
- /* for 4-way, DHCP, EAPOL packet */
- if (coex_sta->specific_pkt_period_cnt > 0) {
-
- coex_sta->specific_pkt_period_cnt--;
-
- if ((coex_sta->specific_pkt_period_cnt == 0) && (coex_sta->wifi_is_high_pri_task))
- coex_sta->wifi_is_high_pri_task = false;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ***************** Hi-Pri Task = %s*****************\n", (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"));
- BTC_TRACE(trace_buf);
-
- }
-
- if (halbtc8703b1ant_is_wifibt_status_changed(btcoexist))
- halbtc8703b1ant_run_coexist_mechanism(btcoexist);
-}
-
-void ex_halbtc8703b1ant_antenna_detection(IN struct btc_coexist *btcoexist,
- IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
-{
- /* No Antenna Detection required because 8730b is only 1-Ant */
-}
-
-void ex_halbtc8703b1ant_antenna_isolation(IN struct btc_coexist *btcoexist,
- IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
-{
-
-
-}
-
-void ex_halbtc8703b1ant_psd_scan(IN struct btc_coexist *btcoexist,
- IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
-{
-
-
-}
-
-void ex_halbtc8703b1ant_display_ant_detection(IN struct btc_coexist *btcoexist)
-{
-
-}
-
-#endif
-
-#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */
diff --git a/hal/btc/HalBtc8703b1Ant.h b/hal/btc/HalBtc8703b1Ant.h
deleted file mode 100644
index cf167a5..0000000
--- a/hal/btc/HalBtc8703b1Ant.h
+++ /dev/null
@@ -1,348 +0,0 @@
-
-#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
-
-#if (RTL8703B_SUPPORT == 1)
-/* *******************************************
- * The following is for 8703B 1ANT BT Co-exist definition
- * ******************************************* */
-#define BT_AUTO_REPORT_ONLY_8703B_1ANT 1
-#define BT_8703B_1ANT_ENABLE_GNTBT_TO_GPIO14 0
-
-#define BT_INFO_8703B_1ANT_B_FTP BIT(7)
-#define BT_INFO_8703B_1ANT_B_A2DP BIT(6)
-#define BT_INFO_8703B_1ANT_B_HID BIT(5)
-#define BT_INFO_8703B_1ANT_B_SCO_BUSY BIT(4)
-#define BT_INFO_8703B_1ANT_B_ACL_BUSY BIT(3)
-#define BT_INFO_8703B_1ANT_B_INQ_PAGE BIT(2)
-#define BT_INFO_8703B_1ANT_B_SCO_ESCO BIT(1)
-#define BT_INFO_8703B_1ANT_B_CONNECTION BIT(0)
-
-#define BT_INFO_8703B_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \
- (((_BT_INFO_EXT_&BIT(0))) ? true : false)
-
-#define BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT 2
-
-#define BT_8703B_1ANT_WIFI_NOISY_THRESH 50 /* max: 255 */
-
-/* for Antenna detection */
-#define BT_8703B_1ANT_ANTDET_PSDTHRES_BACKGROUND 50
-#define BT_8703B_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION 70
-#define BT_8703B_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION 55
-#define BT_8703B_1ANT_ANTDET_PSDTHRES_1ANT 35
-#define BT_8703B_1ANT_ANTDET_RETRY_INTERVAL 10 /* retry timer if ant det is fail, unit: second */
-#define BT_8703B_1ANT_ANTDET_SWEEPPOINT_DELAY 40000
-#define BT_8703B_1ANT_ANTDET_ENABLE 0
-#define BT_8703B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE 0
-
-#define BT_8703B_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT 30000
-
-enum bt_8703b_1ant_signal_state {
- BT_8703B_1ANT_SIG_STA_SET_TO_LOW = 0x0,
- BT_8703B_1ANT_SIG_STA_SET_BY_HW = 0x0,
- BT_8703B_1ANT_SIG_STA_SET_TO_HIGH = 0x1,
- BT_8703B_1ANT_SIG_STA_MAX
-};
-
-enum bt_8703b_1ant_path_ctrl_owner {
- BT_8703B_1ANT_PCO_BTSIDE = 0x0,
- BT_8703B_1ANT_PCO_WLSIDE = 0x1,
- BT_8703B_1ANT_PCO_MAX
-};
-
-enum bt_8703b_1ant_gnt_ctrl_type {
- BT_8703B_1ANT_GNT_TYPE_CTRL_BY_PTA = 0x0,
- BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW = 0x1,
- BT_8703B_1ANT_GNT_TYPE_MAX
-};
-
-enum bt_8703b_1ant_gnt_ctrl_block {
- BT_8703B_1ANT_GNT_BLOCK_RFC_BB = 0x0,
- BT_8703B_1ANT_GNT_BLOCK_RFC = 0x1,
- BT_8703B_1ANT_GNT_BLOCK_BB = 0x2,
- BT_8703B_1ANT_GNT_BLOCK_MAX
-};
-
-enum bt_8703b_1ant_lte_coex_table_type {
- BT_8703B_1ANT_CTT_WL_VS_LTE = 0x0,
- BT_8703B_1ANT_CTT_BT_VS_LTE = 0x1,
- BT_8703B_1ANT_CTT_MAX
-};
-
-enum bt_8703b_1ant_lte_break_table_type {
- BT_8703B_1ANT_LBTT_WL_BREAK_LTE = 0x0,
- BT_8703B_1ANT_LBTT_BT_BREAK_LTE = 0x1,
- BT_8703B_1ANT_LBTT_LTE_BREAK_WL = 0x2,
- BT_8703B_1ANT_LBTT_LTE_BREAK_BT = 0x3,
- BT_8703B_1ANT_LBTT_MAX
-};
-
-enum bt_info_src_8703b_1ant {
- BT_INFO_SRC_8703B_1ANT_WIFI_FW = 0x0,
- BT_INFO_SRC_8703B_1ANT_BT_RSP = 0x1,
- BT_INFO_SRC_8703B_1ANT_BT_ACTIVE_SEND = 0x2,
- BT_INFO_SRC_8703B_1ANT_MAX
-};
-
-enum bt_8703b_1ant_bt_status {
- BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
- BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
- BT_8703B_1ANT_BT_STATUS_INQ_PAGE = 0x2,
- BT_8703B_1ANT_BT_STATUS_ACL_BUSY = 0x3,
- BT_8703B_1ANT_BT_STATUS_SCO_BUSY = 0x4,
- BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
- BT_8703B_1ANT_BT_STATUS_MAX
-};
-
-enum bt_8703b_1ant_wifi_status {
- BT_8703B_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0,
- BT_8703B_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1,
- BT_8703B_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2,
- BT_8703B_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT = 0x3,
- BT_8703B_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4,
- BT_8703B_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5,
- BT_8703B_1ANT_WIFI_STATUS_MAX
-};
-
-enum bt_8703b_1ant_coex_algo {
- BT_8703B_1ANT_COEX_ALGO_UNDEFINED = 0x0,
- BT_8703B_1ANT_COEX_ALGO_SCO = 0x1,
- BT_8703B_1ANT_COEX_ALGO_HID = 0x2,
- BT_8703B_1ANT_COEX_ALGO_A2DP = 0x3,
- BT_8703B_1ANT_COEX_ALGO_A2DP_PANHS = 0x4,
- BT_8703B_1ANT_COEX_ALGO_PANEDR = 0x5,
- BT_8703B_1ANT_COEX_ALGO_PANHS = 0x6,
- BT_8703B_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
- BT_8703B_1ANT_COEX_ALGO_PANEDR_HID = 0x8,
- BT_8703B_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
- BT_8703B_1ANT_COEX_ALGO_HID_A2DP = 0xa,
- BT_8703B_1ANT_COEX_ALGO_MAX = 0xb,
-};
-
-struct coex_dm_8703b_1ant {
- /* hw setting */
- u8 pre_ant_pos_type;
- u8 cur_ant_pos_type;
- /* fw mechanism */
- boolean cur_ignore_wlan_act;
- boolean pre_ignore_wlan_act;
- u8 pre_ps_tdma;
- u8 cur_ps_tdma;
- u8 ps_tdma_para[5];
- u8 ps_tdma_du_adj_type;
- boolean auto_tdma_adjust;
- boolean pre_ps_tdma_on;
- boolean cur_ps_tdma_on;
- boolean pre_bt_auto_report;
- boolean cur_bt_auto_report;
- u8 pre_lps;
- u8 cur_lps;
- u8 pre_rpwm;
- u8 cur_rpwm;
-
- /* sw mechanism */
- boolean pre_low_penalty_ra;
- boolean cur_low_penalty_ra;
- u32 pre_val0x6c0;
- u32 cur_val0x6c0;
- u32 pre_val0x6c4;
- u32 cur_val0x6c4;
- u32 pre_val0x6c8;
- u32 cur_val0x6c8;
- u8 pre_val0x6cc;
- u8 cur_val0x6cc;
- boolean limited_dig;
-
- u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */
- u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */
- u16 backup_retry_limit;
- u8 backup_ampdu_max_time;
-
- /* algorithm related */
- u8 pre_algorithm;
- u8 cur_algorithm;
- u8 bt_status;
- u8 wifi_chnl_info[3];
-
- u32 pre_ra_mask;
- u32 cur_ra_mask;
- u8 pre_arfr_type;
- u8 cur_arfr_type;
- u8 pre_retry_limit_type;
- u8 cur_retry_limit_type;
- u8 pre_ampdu_time_type;
- u8 cur_ampdu_time_type;
- u32 arp_cnt;
-
- u8 error_condition;
-};
-
-struct coex_sta_8703b_1ant {
- boolean bt_disabled;
- boolean bt_link_exist;
- boolean sco_exist;
- boolean a2dp_exist;
- boolean hid_exist;
- boolean pan_exist;
- boolean bt_hi_pri_link_exist;
- u8 num_of_profile;
-
- boolean under_lps;
- boolean under_ips;
- u32 specific_pkt_period_cnt;
- u32 high_priority_tx;
- u32 high_priority_rx;
- u32 low_priority_tx;
- u32 low_priority_rx;
- s8 bt_rssi;
- boolean bt_tx_rx_mask;
- u8 pre_bt_rssi_state;
- u8 pre_wifi_rssi_state[4];
- boolean c2h_bt_info_req_sent;
- u8 bt_info_c2h[BT_INFO_SRC_8703B_1ANT_MAX][10];
- u32 bt_info_c2h_cnt[BT_INFO_SRC_8703B_1ANT_MAX];
- boolean bt_whck_test;
- boolean c2h_bt_inquiry_page;
- boolean c2h_bt_page; /* Add for win8.1 page out issue */
- boolean wifi_is_high_pri_task; /* Add for win8.1 page out issue */
- u8 bt_retry_cnt;
- u8 bt_info_ext;
- u32 pop_event_cnt;
- u8 scan_ap_num;
-
- u32 crc_ok_cck;
- u32 crc_ok_11g;
- u32 crc_ok_11n;
- u32 crc_ok_11n_agg;
-
- u32 crc_err_cck;
- u32 crc_err_11g;
- u32 crc_err_11n;
- u32 crc_err_11n_agg;
-
- boolean cck_lock;
- boolean pre_ccklock;
- boolean cck_ever_lock;
- u8 coex_table_type;
-
- boolean force_lps_on;
- u32 wrong_profile_notification;
-
- boolean concurrent_rx_mode_on;
-
- u16 score_board;
-
- u8 a2dp_bit_pool;
- u8 cut_version;
- boolean acl_busy;
- boolean wl_rf_off_on_event;
- boolean bt_create_connection;
- boolean gnt_control_by_PTA;
-};
-
-#define BT_8703B_1ANT_ANTDET_PSD_POINTS 256 /* MAX:1024 */
-#define BT_8703B_1ANT_ANTDET_PSD_AVGNUM 1 /* MAX:3 */
-#define BT_8703B_1ANT_ANTDET_BUF_LEN 16
-
-struct psdscan_sta_8703b_1ant {
-
- u32 ant_det_bt_le_channel; /* BT LE Channel ex:2412 */
- u32 ant_det_bt_tx_time;
- u32 ant_det_pre_psdscan_peak_val;
- boolean ant_det_is_ant_det_available;
- u32 ant_det_psd_scan_peak_val;
- boolean ant_det_is_btreply_available;
- u32 ant_det_psd_scan_peak_freq;
-
- u8 ant_det_result;
- u8 ant_det_peak_val[BT_8703B_1ANT_ANTDET_BUF_LEN];
- u8 ant_det_peak_freq[BT_8703B_1ANT_ANTDET_BUF_LEN];
- u32 ant_det_try_count;
- u32 ant_det_fail_count;
- u32 ant_det_inteval_count;
- u32 ant_det_thres_offset;
-
- u32 real_cent_freq;
- s32 real_offset;
- u32 real_span;
-
- u32 psd_band_width; /* unit: Hz */
- u32 psd_point; /* 128/256/512/1024 */
- u32 psd_report[1024]; /* unit:dB (20logx), 0~255 */
- u32 psd_report_max_hold[1024]; /* unit:dB (20logx), 0~255 */
- u32 psd_start_point;
- u32 psd_stop_point;
- u32 psd_max_value_point;
- u32 psd_max_value;
- u32 psd_start_base;
- u32 psd_avg_num; /* 1/8/16/32 */
- u32 psd_gen_count;
- boolean is_psd_running;
- boolean is_psd_show_max_only;
-};
-
-/* *******************************************
- * The following is interface which will notify coex module.
- * ******************************************* */
-void ex_halbtc8703b1ant_power_on_setting(IN struct btc_coexist *btcoexist);
-void ex_halbtc8703b1ant_pre_load_firmware(IN struct btc_coexist *btcoexist);
-void ex_halbtc8703b1ant_init_hw_config(IN struct btc_coexist *btcoexist,
- IN boolean wifi_only);
-void ex_halbtc8703b1ant_init_coex_dm(IN struct btc_coexist *btcoexist);
-void ex_halbtc8703b1ant_ips_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8703b1ant_lps_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8703b1ant_scan_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8703b1ant_connect_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8703b1ant_media_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8703b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8703b1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
- IN u8 *tmp_buf, IN u8 length);
-void ex_halbtc8703b1ant_rf_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8703b1ant_halt_notify(IN struct btc_coexist *btcoexist);
-void ex_halbtc8703b1ant_pnp_notify(IN struct btc_coexist *btcoexist,
- IN u8 pnp_state);
-void ex_halbtc8703b1ant_coex_dm_reset(IN struct btc_coexist *btcoexist);
-void ex_halbtc8703b1ant_periodical(IN struct btc_coexist *btcoexist);
-void ex_halbtc8703b1ant_display_coex_info(IN struct btc_coexist *btcoexist);
-void ex_halbtc8703b1ant_antenna_detection(IN struct btc_coexist *btcoexist,
- IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds);
-void ex_halbtc8703b1ant_antenna_isolation(IN struct btc_coexist *btcoexist,
- IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds);
-
-void ex_halbtc8703b1ant_psd_scan(IN struct btc_coexist *btcoexist,
- IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds);
-void ex_halbtc8703b1ant_display_ant_detection(IN struct btc_coexist *btcoexist);
-
-#else
-#define ex_halbtc8703b1ant_power_on_setting(btcoexist)
-#define ex_halbtc8703b1ant_pre_load_firmware(btcoexist)
-#define ex_halbtc8703b1ant_init_hw_config(btcoexist, wifi_only)
-#define ex_halbtc8703b1ant_init_coex_dm(btcoexist)
-#define ex_halbtc8703b1ant_ips_notify(btcoexist, type)
-#define ex_halbtc8703b1ant_lps_notify(btcoexist, type)
-#define ex_halbtc8703b1ant_scan_notify(btcoexist, type)
-#define ex_halbtc8703b1ant_connect_notify(btcoexist, type)
-#define ex_halbtc8703b1ant_media_status_notify(btcoexist, type)
-#define ex_halbtc8703b1ant_specific_packet_notify(btcoexist, type)
-#define ex_halbtc8703b1ant_bt_info_notify(btcoexist, tmp_buf, length)
-#define ex_halbtc8703b1ant_rf_status_notify(btcoexist, type)
-#define ex_halbtc8703b1ant_halt_notify(btcoexist)
-#define ex_halbtc8703b1ant_pnp_notify(btcoexist, pnp_state)
-#define ex_halbtc8703b1ant_coex_dm_reset(btcoexist)
-#define ex_halbtc8703b1ant_periodical(btcoexist)
-#define ex_halbtc8703b1ant_display_coex_info(btcoexist)
-#define ex_halbtc8703b1ant_antenna_detection(btcoexist, cent_freq, offset, span, seconds)
-#define ex_halbtc8703b1ant_antenna_isolation(btcoexist, cent_freq, offset, span, seconds)
-#define ex_halbtc8703b1ant_psd_scan(btcoexist, cent_freq, offset, span, seconds)
-#define ex_halbtc8703b1ant_display_ant_detection(btcoexist)
-
-#endif
-
-
-#endif
diff --git a/hal/btc/HalBtc8723a1Ant.c b/hal/btc/HalBtc8723a1Ant.c
deleted file mode 100644
index 5883a37..0000000
--- a/hal/btc/HalBtc8723a1Ant.c
+++ /dev/null
@@ -1,1544 +0,0 @@
-//============================================================
-// Description:
-//
-// This file is for RTL8723A Co-exist mechanism
-//
-// History
-// 2012/08/22 Cosa first check in.
-// 2012/11/14 Cosa Revise for 8723A 1Ant out sourcing.
-//
-//============================================================
-
-//============================================================
-// include files
-//============================================================
-#include "Mp_Precomp.h"
-
-#if WPP_SOFTWARE_TRACE
-#include "HalBtc8723a1Ant.tmh"
-#endif
-
-#if(BT_30_SUPPORT == 1)
-//============================================================
-// Global variables, these are static variables
-//============================================================
-static COEX_DM_8723A_1ANT GLCoexDm8723a1Ant;
-static PCOEX_DM_8723A_1ANT pCoexDm=&GLCoexDm8723a1Ant;
-static COEX_STA_8723A_1ANT GLCoexSta8723a1Ant;
-static PCOEX_STA_8723A_1ANT pCoexSta=&GLCoexSta8723a1Ant;
-
-const char *const GLBtInfoSrc8723a1Ant[]={
- "BT Info[wifi fw]",
- "BT Info[bt rsp]",
- "BT Info[bt auto report]",
-};
-
-//============================================================
-// local function proto type if needed
-//============================================================
-//============================================================
-// local function start with halbtc8723a1ant_
-//============================================================
-VOID
-halbtc8723a1ant_Reg0x550Bit3(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bSet
- )
-{
- u1Byte u1tmp=0;
-
- u1tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x550);
- if(bSet)
- {
- u1tmp |= BIT3;
- }
- else
- {
- u1tmp &= ~BIT3;
- }
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x550, u1tmp);
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], set 0x550[3]=%d\n", (bSet? 1:0)));
-}
-
-VOID
-halbtc8723a1ant_NotifyFwScan(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte scanType
- )
-{
- u1Byte H2C_Parameter[1] ={0};
-
- if(BTC_SCAN_START == scanType)
- H2C_Parameter[0] = 0x1;
-
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Notify FW for wifi scan, write 0x3b=0x%x\n",
- H2C_Parameter[0]));
-
- pBtCoexist->fBtcFillH2c(pBtCoexist, 0x3b, 1, H2C_Parameter);
-}
-
-VOID
-halbtc8723a1ant_QueryBtInfo(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- u1Byte H2C_Parameter[1] ={0};
-
- pCoexSta->bC2hBtInfoReqSent = TRUE;
-
- H2C_Parameter[0] |= BIT0; // trigger
-
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Query Bt Info, FW write 0x38=0x%x\n",
- H2C_Parameter[0]));
-
- pBtCoexist->fBtcFillH2c(pBtCoexist, 0x38, 1, H2C_Parameter);
-}
-
-VOID
-halbtc8723a1ant_SetSwRfRxLpfCorner(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bRxRfShrinkOn
- )
-{
- if(bRxRfShrinkOn)
- {
- //Shrink RF Rx LPF corner
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Shrink RF Rx LPF corner!!\n"));
- pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, 0xf0ff7);
- }
- else
- {
- //Resume RF Rx LPF corner
- // After initialized, we can use pCoexDm->btRf0x1eBackup
- if(pBtCoexist->bInitilized)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Resume RF Rx LPF corner!!\n"));
- pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, pCoexDm->btRf0x1eBackup);
- }
- }
-}
-
-VOID
-halbtc8723a1ant_RfShrink(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bForceExec,
- IN BOOLEAN bRxRfShrinkOn
- )
-{
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Rx RF Shrink = %s\n",
- (bForceExec? "force to":""), ((bRxRfShrinkOn)? "ON":"OFF")));
- pCoexDm->bCurRfRxLpfShrink = bRxRfShrinkOn;
-
- if(!bForceExec)
- {
- if(pCoexDm->bPreRfRxLpfShrink == pCoexDm->bCurRfRxLpfShrink)
- return;
- }
- halbtc8723a1ant_SetSwRfRxLpfCorner(pBtCoexist, pCoexDm->bCurRfRxLpfShrink);
-
- pCoexDm->bPreRfRxLpfShrink = pCoexDm->bCurRfRxLpfShrink;
-}
-
-VOID
-halbtc8723a1ant_SetSwPenaltyTxRateAdaptive(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bLowPenaltyRa
- )
-{
- u1Byte tmpU1;
-
- tmpU1 = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x4fd);
- tmpU1 |= BIT0;
- if(bLowPenaltyRa)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Tx rate adaptive, set low penalty!!\n"));
- tmpU1 &= ~BIT2;
- }
- else
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Tx rate adaptive, set normal!!\n"));
- tmpU1 |= BIT2;
- }
-
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x4fd, tmpU1);
-}
-
-VOID
-halbtc8723a1ant_LowPenaltyRa(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bForceExec,
- IN BOOLEAN bLowPenaltyRa
- )
-{
- return;
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn LowPenaltyRA = %s\n",
- (bForceExec? "force to":""), ((bLowPenaltyRa)? "ON":"OFF")));
- pCoexDm->bCurLowPenaltyRa = bLowPenaltyRa;
-
- if(!bForceExec)
- {
- if(pCoexDm->bPreLowPenaltyRa == pCoexDm->bCurLowPenaltyRa)
- return;
- }
- halbtc8723a1ant_SetSwPenaltyTxRateAdaptive(pBtCoexist, pCoexDm->bCurLowPenaltyRa);
-
- pCoexDm->bPreLowPenaltyRa = pCoexDm->bCurLowPenaltyRa;
-}
-
-VOID
-halbtc8723a1ant_SetCoexTable(
- IN PBTC_COEXIST pBtCoexist,
- IN u4Byte val0x6c0,
- IN u4Byte val0x6c8,
- IN u1Byte val0x6cc
- )
-{
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c0=0x%x\n", val0x6c0));
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c0, val0x6c0);
-
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c8=0x%x\n", val0x6c8));
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c8, val0x6c8);
-
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6cc=0x%x\n", val0x6cc));
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cc, val0x6cc);
-}
-
-VOID
-halbtc8723a1ant_CoexTable(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bForceExec,
- IN u4Byte val0x6c0,
- IN u4Byte val0x6c8,
- IN u1Byte val0x6cc
- )
-{
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s write Coex Table 0x6c0=0x%x, 0x6c8=0x%x, 0x6cc=0x%x\n",
- (bForceExec? "force to":""), val0x6c0, val0x6c8, val0x6cc));
- pCoexDm->curVal0x6c0 = val0x6c0;
- pCoexDm->curVal0x6c8 = val0x6c8;
- pCoexDm->curVal0x6cc = val0x6cc;
-
- if(!bForceExec)
- {
- if( (pCoexDm->preVal0x6c0 == pCoexDm->curVal0x6c0) &&
- (pCoexDm->preVal0x6c8 == pCoexDm->curVal0x6c8) &&
- (pCoexDm->preVal0x6cc == pCoexDm->curVal0x6cc) )
- return;
- }
- halbtc8723a1ant_SetCoexTable(pBtCoexist, val0x6c0, val0x6c8, val0x6cc);
-
- pCoexDm->preVal0x6c0 = pCoexDm->curVal0x6c0;
- pCoexDm->preVal0x6c8 = pCoexDm->curVal0x6c8;
- pCoexDm->preVal0x6cc = pCoexDm->curVal0x6cc;
-}
-
-VOID
-halbtc8723a1ant_SetFwIgnoreWlanAct(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bEnable
- )
-{
- u1Byte H2C_Parameter[1] ={0};
-
- if(bEnable)
- {
- H2C_Parameter[0] |= BIT0; // function enable
- }
-
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set FW for BT Ignore Wlan_Act, FW write 0x25=0x%x\n",
- H2C_Parameter[0]));
-
- pBtCoexist->fBtcFillH2c(pBtCoexist, 0x25, 1, H2C_Parameter);
-}
-
-VOID
-halbtc8723a1ant_IgnoreWlanAct(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bForceExec,
- IN BOOLEAN bEnable
- )
-{
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Ignore WlanAct %s\n",
- (bForceExec? "force to":""), (bEnable? "ON":"OFF")));
- pCoexDm->bCurIgnoreWlanAct = bEnable;
-
- if(!bForceExec)
- {
- if(pCoexDm->bPreIgnoreWlanAct == pCoexDm->bCurIgnoreWlanAct)
- return;
- }
- halbtc8723a1ant_SetFwIgnoreWlanAct(pBtCoexist, bEnable);
-
- pCoexDm->bPreIgnoreWlanAct = pCoexDm->bCurIgnoreWlanAct;
-}
-
-VOID
-halbtc8723a1ant_SetFwPstdma(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type,
- IN u1Byte byte1,
- IN u1Byte byte2,
- IN u1Byte byte3,
- IN u1Byte byte4,
- IN u1Byte byte5
- )
-{
- u1Byte H2C_Parameter[5] ={0};
- u1Byte realByte1=byte1, realByte5=byte5;
- BOOLEAN bApEnable=FALSE;
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &bApEnable);
-
- // byte1[1:0] != 0 means enable pstdma
- // for 2Ant bt coexist, if byte1 != 0 means enable pstdma
- if(byte1)
- {
- if(bApEnable)
- {
- if(type != 5 && type != 12)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], FW for 1Ant AP mode\n"));
- realByte1 &= ~BIT4;
- realByte1 |= BIT5;
-
- realByte5 |= BIT5;
- realByte5 &= ~BIT6;
- }
- }
- }
- H2C_Parameter[0] = realByte1;
- H2C_Parameter[1] = byte2;
- H2C_Parameter[2] = byte3;
- H2C_Parameter[3] = byte4;
- H2C_Parameter[4] = realByte5;
-
- pCoexDm->psTdmaPara[0] = realByte1;
- pCoexDm->psTdmaPara[1] = byte2;
- pCoexDm->psTdmaPara[2] = byte3;
- pCoexDm->psTdmaPara[3] = byte4;
- pCoexDm->psTdmaPara[4] = realByte5;
-
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], FW write 0x3a(5bytes)=0x%x%08x\n",
- H2C_Parameter[0],
- H2C_Parameter[1]<<24|H2C_Parameter[2]<<16|H2C_Parameter[3]<<8|H2C_Parameter[4]));
-
- pBtCoexist->fBtcFillH2c(pBtCoexist, 0x3a, 5, H2C_Parameter);
-}
-
-VOID
-halbtc8723a1ant_PsTdma(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bForceExec,
- IN BOOLEAN bTurnOn,
- IN u1Byte type
- )
-{
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn %s PS TDMA, type=%d\n",
- (bForceExec? "force to":""), (bTurnOn? "ON":"OFF"), type));
- pCoexDm->bCurPsTdmaOn = bTurnOn;
- pCoexDm->curPsTdma = type;
-
- if(!bForceExec)
- {
- if( (pCoexDm->bPrePsTdmaOn == pCoexDm->bCurPsTdmaOn) &&
- (pCoexDm->prePsTdma == pCoexDm->curPsTdma) )
- return;
- }
- if(pCoexDm->bCurPsTdmaOn)
- {
- switch(pCoexDm->curPsTdma)
- {
- case 1:
- default:
- halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0x1a, 0x1a, 0x0, 0x40);
- break;
- case 2:
- halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0x12, 0x12, 0x0, 0x40);
- break;
- case 3:
- halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x93, 0x3f, 0x3, 0x10, 0x40);
- break;
- case 4:
- halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x93, 0x15, 0x3, 0x10, 0x0);
- break;
- case 5:
- halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0xa9, 0x15, 0x3, 0x35, 0xc0);
- break;
-
- case 8:
- halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x93, 0x25, 0x3, 0x10, 0x0);
- break;
- case 9:
- halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0xa, 0xa, 0x0, 0x40);
- break;
- case 10:
- halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0xa, 0xa, 0x0, 0x40);
- break;
- case 11:
- halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0x5, 0x5, 0x0, 0x40);
- break;
- case 12:
- halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0xa9, 0xa, 0x3, 0x15, 0xc0);
- break;
-
- case 18:
- halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x93, 0x25, 0x3, 0x10, 0x0);
- break;
-
- case 20:
- halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0x2a, 0x2a, 0x0, 0x0);
- break;
- case 21:
- halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x93, 0x20, 0x3, 0x10, 0x40);
- break;
- case 22:
- halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0x1a, 0x1a, 0x2, 0x40);
- break;
- case 23:
- halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0x12, 0x12, 0x2, 0x40);
- break;
- case 24:
- halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0xa, 0xa, 0x2, 0x40);
- break;
- case 25:
- halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0x5, 0x5, 0x2, 0x40);
- break;
- case 26:
- halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x93, 0x25, 0x3, 0x10, 0x0);
- break;
- case 27:
- halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0x5, 0x5, 0x2, 0x40);
- break;
- case 28:
- halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x3, 0x2f, 0x2f, 0x0, 0x0);
- break;
-
- }
- }
- else
- {
- // disable PS tdma
- switch(pCoexDm->curPsTdma)
- {
- case 8:
- halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x8, 0x0, 0x0, 0x0, 0x0);
- break;
- case 0:
- default:
- halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x0, 0x0, 0x0, 0x0, 0x0);
- pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x860, 0x210);
- break;
- case 9:
- halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x0, 0x0, 0x0, 0x0, 0x0);
- pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x860, 0x110);
- break;
-
- }
- }
-
- // update pre state
- pCoexDm->bPrePsTdmaOn = pCoexDm->bCurPsTdmaOn;
- pCoexDm->prePsTdma = pCoexDm->curPsTdma;
-}
-
-
-VOID
-halbtc8723a1ant_CoexAllOff(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- // fw all off
- halbtc8723a1ant_IgnoreWlanAct(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0);
-
- // sw all off
- halbtc8723a1ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a1ant_RfShrink(pBtCoexist, NORMAL_EXEC, FALSE);
-
- // hw all off
- halbtc8723a1ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3);
-}
-
-VOID
-halbtc8723a1ant_InitCoexDm(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- // force to reset coex mechanism
- halbtc8723a1ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, FALSE);
-}
-
-VOID
-halbtc8723a1ant_BtEnableAction(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- halbtc8723a1ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, FALSE);
-}
-
-VOID
-halbtc8723a1ant_MonitorBtCtr(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- u4Byte regHPTxRx, regLPTxRx, u4Tmp;
- u4Byte regHPTx=0, regHPRx=0, regLPTx=0, regLPRx=0;
- u1Byte u1Tmp;
-
- regHPTxRx = 0x770;
- regLPTxRx = 0x774;
-
- u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, regHPTxRx);
- regHPTx = u4Tmp & bMaskLWord;
- regHPRx = (u4Tmp & bMaskHWord)>>16;
-
- u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, regLPTxRx);
- regLPTx = u4Tmp & bMaskLWord;
- regLPRx = (u4Tmp & bMaskHWord)>>16;
-
- pCoexSta->highPriorityTx = regHPTx;
- pCoexSta->highPriorityRx = regHPRx;
- pCoexSta->lowPriorityTx = regLPTx;
- pCoexSta->lowPriorityRx = regLPRx;
-
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], High Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n",
- regHPTxRx, regHPTx, regHPTx, regHPRx, regHPRx));
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Low Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n",
- regLPTxRx, regLPTx, regLPTx, regLPRx, regLPRx));
-
- // reset counter
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0xc);
-}
-
-VOID
-halbtc8723a1ant_MonitorBtEnableDisable(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- static BOOLEAN bPreBtDisabled=FALSE;
- static u4Byte btDisableCnt=0;
- BOOLEAN bBtActive=TRUE, bBtDisabled=FALSE;
-
- // This function check if bt is disabled
-
- if( pCoexSta->highPriorityTx == 0 &&
- pCoexSta->highPriorityRx == 0 &&
- pCoexSta->lowPriorityTx == 0 &&
- pCoexSta->lowPriorityRx == 0)
- {
- bBtActive = FALSE;
- }
- if( pCoexSta->highPriorityTx == 0xffff &&
- pCoexSta->highPriorityRx == 0xffff &&
- pCoexSta->lowPriorityTx == 0xffff &&
- pCoexSta->lowPriorityRx == 0xffff)
- {
- bBtActive = FALSE;
- }
- if(bBtActive)
- {
- btDisableCnt = 0;
- bBtDisabled = FALSE;
- pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled);
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is enabled !!\n"));
- }
- else
- {
- btDisableCnt++;
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], bt all counters=0, %d times!!\n",
- btDisableCnt));
- if(btDisableCnt >= 2)
- {
- bBtDisabled = TRUE;
- pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled);
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is disabled !!\n"));
- }
- }
- if(bPreBtDisabled != bBtDisabled)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is from %s to %s!!\n",
- (bPreBtDisabled ? "disabled":"enabled"),
- (bBtDisabled ? "disabled":"enabled")));
- bPreBtDisabled = bBtDisabled;
- if(!bBtDisabled)
- {
- halbtc8723a1ant_BtEnableAction(pBtCoexist);
- }
- else
- {
- pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_NORMAL_LPS, NULL);
- }
- }
-}
-
-VOID
-halbtc8723a1ant_TdmaDurationAdjust(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- static s4Byte up,dn,m,n,WaitCount;
- s4Byte result; //0: no change, +1: increase WiFi duration, -1: decrease WiFi duration
- u1Byte retryCount=0;
- u1Byte btState;
- BOOLEAN bScan=FALSE, bLink=FALSE, bRoam=FALSE;
- u4Byte wifiBw;
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
- btState = pCoexDm->btStatus;
-
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], TdmaDurationAdjust()\n"));
- if(pCoexDm->psTdmaGlobalCnt != pCoexDm->psTdmaMonitorCnt)
- {
- pCoexDm->psTdmaMonitorCnt = 0;
- pCoexDm->psTdmaGlobalCnt = 0;
- }
- if(pCoexDm->psTdmaMonitorCnt == 0)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], first run BT A2DP + WiFi busy state!!\n"));
- if(btState == BT_STATE_8723A_1ANT_ACL_ONLY_BUSY)
- {
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1);
- pCoexDm->psTdmaDuAdjType = 1;
- }
- else
- {
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 22);
- pCoexDm->psTdmaDuAdjType = 22;
- }
- //============
- up = 0;
- dn = 0;
- m = 1;
- n= 3;
- result = 0;
- WaitCount = 0;
- }
- else
- {
- //accquire the BT TRx retry count from BT_Info byte2
- retryCount = pCoexSta->btRetryCnt;
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], retryCount = %d\n", retryCount));
- result = 0;
- WaitCount++;
-
- if(retryCount == 0) // no retry in the last 2-second duration
- {
- up++;
- dn--;
-
- if (dn <= 0)
- dn = 0;
-
- if(up >= n) // if ³sÄò n Ó2¬í retry count¬°0, «h½Õ¼eWiFi duration
- {
- WaitCount = 0;
- n = 3;
- up = 0;
- dn = 0;
- result = 1;
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Increase wifi duration!!\n"));
- }
- }
- else if (retryCount <= 3) // <=3 retry in the last 2-second duration
- {
- up--;
- dn++;
-
- if (up <= 0)
- up = 0;
-
- if (dn == 2) // if ³sÄò 2 Ó2¬í retry count< 3, «h½Õ¯¶WiFi duration
- {
- if (WaitCount <= 2)
- m++; // ÁקK¤@ª½¦b¨âÓlevel¤¤¨Ó¦^
- else
- m = 1;
-
- if ( m >= 20) //m ³Ì¤jÈ = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration.
- m = 20;
-
- n = 3*m;
- up = 0;
- dn = 0;
- WaitCount = 0;
- result = -1;
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Decrease wifi duration for retryCounter<3!!\n"));
- }
- }
- else //retry count > 3, ¥un1¦¸ retry count > 3, «h½Õ¯¶WiFi duration
- {
- if (WaitCount == 1)
- m++; // ÁקK¤@ª½¦b¨âÓlevel¤¤¨Ó¦^
- else
- m = 1;
-
- if ( m >= 20) //m ³Ì¤jÈ = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration.
- m = 20;
-
- n = 3*m;
- up = 0;
- dn = 0;
- WaitCount = 0;
- result = -1;
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Decrease wifi duration for retryCounter>3!!\n"));
- }
-
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT TxRx counter H+L <= 1200\n"));
- if(btState != BT_STATE_8723A_1ANT_ACL_ONLY_BUSY)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], NOT ACL only busy!\n"));
- if(BTC_WIFI_BW_HT40 != wifiBw)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 20MHz\n"));
- if(result == -1)
- {
- if(pCoexDm->curPsTdma == 22)
- {
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 23);
- pCoexDm->psTdmaDuAdjType = 23;
- }
- else if(pCoexDm->curPsTdma == 23)
- {
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 24);
- pCoexDm->psTdmaDuAdjType = 24;
- }
- else if(pCoexDm->curPsTdma == 24)
- {
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 25);
- pCoexDm->psTdmaDuAdjType = 25;
- }
- }
- else if (result == 1)
- {
- if(pCoexDm->curPsTdma == 25)
- {
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 24);
- pCoexDm->psTdmaDuAdjType = 24;
- }
- else if(pCoexDm->curPsTdma == 24)
- {
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 23);
- pCoexDm->psTdmaDuAdjType = 23;
- }
- else if(pCoexDm->curPsTdma == 23)
- {
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 22);
- pCoexDm->psTdmaDuAdjType = 22;
- }
- }
- // error handle, if not in the following state,
- // set psTdma again.
- if( (pCoexDm->psTdmaDuAdjType != 22) &&
- (pCoexDm->psTdmaDuAdjType != 23) &&
- (pCoexDm->psTdmaDuAdjType != 24) &&
- (pCoexDm->psTdmaDuAdjType != 25) )
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], duration case out of handle!!\n"));
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 23);
- pCoexDm->psTdmaDuAdjType = 23;
- }
- }
- else
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 40MHz\n"));
- if(result == -1)
- {
- if(pCoexDm->curPsTdma == 23)
- {
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 24);
- pCoexDm->psTdmaDuAdjType = 24;
- }
- else if(pCoexDm->curPsTdma == 24)
- {
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 25);
- pCoexDm->psTdmaDuAdjType = 25;
- }
- else if(pCoexDm->curPsTdma == 25)
- {
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 27);
- pCoexDm->psTdmaDuAdjType = 27;
- }
- }
- else if (result == 1)
- {
- if(pCoexDm->curPsTdma == 27)
- {
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 25);
- pCoexDm->psTdmaDuAdjType = 25;
- }
- else if(pCoexDm->curPsTdma == 25)
- {
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 24);
- pCoexDm->psTdmaDuAdjType = 24;
- }
- else if(pCoexDm->curPsTdma == 24)
- {
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 23);
- pCoexDm->psTdmaDuAdjType = 23;
- }
- }
- // error handle, if not in the following state,
- // set psTdma again.
- if( (pCoexDm->psTdmaDuAdjType != 23) &&
- (pCoexDm->psTdmaDuAdjType != 24) &&
- (pCoexDm->psTdmaDuAdjType != 25) &&
- (pCoexDm->psTdmaDuAdjType != 27) )
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], duration case out of handle!!\n"));
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 24);
- pCoexDm->psTdmaDuAdjType = 24;
- }
- }
- }
- else
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ACL only busy\n"));
- if (result == -1)
- {
- if(pCoexDm->curPsTdma == 1)
- {
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2);
- pCoexDm->psTdmaDuAdjType = 2;
- }
- else if(pCoexDm->curPsTdma == 2)
- {
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9);
- pCoexDm->psTdmaDuAdjType = 9;
- }
- else if(pCoexDm->curPsTdma == 9)
- {
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11);
- pCoexDm->psTdmaDuAdjType = 11;
- }
- }
- else if (result == 1)
- {
- if(pCoexDm->curPsTdma == 11)
- {
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9);
- pCoexDm->psTdmaDuAdjType = 9;
- }
- else if(pCoexDm->curPsTdma == 9)
- {
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2);
- pCoexDm->psTdmaDuAdjType = 2;
- }
- else if(pCoexDm->curPsTdma == 2)
- {
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1);
- pCoexDm->psTdmaDuAdjType = 1;
- }
- }
-
- // error handle, if not in the following state,
- // set psTdma again.
- if( (pCoexDm->psTdmaDuAdjType != 1) &&
- (pCoexDm->psTdmaDuAdjType != 2) &&
- (pCoexDm->psTdmaDuAdjType != 9) &&
- (pCoexDm->psTdmaDuAdjType != 11) )
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], duration case out of handle!!\n"));
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2);
- pCoexDm->psTdmaDuAdjType = 2;
- }
- }
- }
- }
-
- // if current PsTdma not match with the recorded one (when scan, dhcp...),
- // then we have to adjust it back to the previous record one.
- if(pCoexDm->curPsTdma != pCoexDm->psTdmaDuAdjType)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PsTdma type dismatch!!!, curPsTdma=%d, recordPsTdma=%d\n",
- pCoexDm->curPsTdma, pCoexDm->psTdmaDuAdjType));
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan);
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink);
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam);
-
- if( !bScan && !bLink && !bRoam)
- {
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, pCoexDm->psTdmaDuAdjType);
- }
- else
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n"));
- }
- }
- pCoexDm->psTdmaMonitorCnt++;
-}
-
-
-VOID
-halbtc8723a1ant_CoexForWifiConnect(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- BOOLEAN bWifiConnected=FALSE, bWifiBusy=FALSE;
- u1Byte btState, btInfoOriginal=0;
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected);
-
- btState = pCoexDm->btStatus;
- btInfoOriginal = pCoexSta->btInfoC2h[BT_INFO_SRC_8723A_1ANT_BT_RSP][0];
-
- if(bWifiConnected)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi connected!!\n"));
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy);
-
- if( !bWifiBusy &&
- ((BT_STATE_8723A_1ANT_NO_CONNECTION == btState) ||
- (BT_STATE_8723A_1ANT_CONNECT_IDLE == btState)) )
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], [Wifi is idle] or [Bt is non connected idle or Bt is connected idle]!!\n"));
-
- if(BT_STATE_8723A_1ANT_NO_CONNECTION == btState)
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 9);
- else if(BT_STATE_8723A_1ANT_CONNECT_IDLE == btState)
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0);
-
- pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x880, 0xff000000, 0xc0);
- }
- else
- {
- if( (BT_STATE_8723A_1ANT_SCO_ONLY_BUSY == btState) ||
- (BT_STATE_8723A_1ANT_ACL_SCO_BUSY == btState) ||
- (BT_STATE_8723A_1ANT_HID_BUSY == btState) ||
- (BT_STATE_8723A_1ANT_HID_SCO_BUSY == btState) )
- {
- pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x880, 0xff000000, 0x60);
- }
- else
- {
- pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x880, 0xff000000, 0xc0);
- }
- switch(btState)
- {
- case BT_STATE_8723A_1ANT_NO_CONNECTION:
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5);
- break;
- case BT_STATE_8723A_1ANT_CONNECT_IDLE:
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12);
- break;
- case BT_STATE_8723A_1ANT_INQ_OR_PAG:
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10);
- break;
- case BT_STATE_8723A_1ANT_SCO_ONLY_BUSY:
- case BT_STATE_8723A_1ANT_ACL_SCO_BUSY:
- case BT_STATE_8723A_1ANT_HID_BUSY:
- case BT_STATE_8723A_1ANT_HID_SCO_BUSY:
- halbtc8723a1ant_TdmaDurationAdjust(pBtCoexist);
- break;
- case BT_STATE_8723A_1ANT_ACL_ONLY_BUSY:
- if (btInfoOriginal&BT_INFO_8723A_1ANT_B_A2DP)
- {
- halbtc8723a1ant_TdmaDurationAdjust(pBtCoexist);
- }
- else if(btInfoOriginal&BT_INFO_8723A_1ANT_B_FTP)
- {
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1);
- }
- else if( (btInfoOriginal&BT_INFO_8723A_1ANT_B_A2DP) &&
- (btInfoOriginal&BT_INFO_8723A_1ANT_B_FTP) )
- {
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6);
- }
- else
- {
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1);
- }
- break;
- default:
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], error!!!, undefined case in halbtc8723a1ant_CoexForWifiConnect()!!\n"));
- break;
- }
- }
- }
- else
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi is disconnected!!\n"));
- }
-
- pCoexDm->psTdmaGlobalCnt++;
-}
-
-//============================================================
-// work around function start with wa_halbtc8723a1ant_
-//============================================================
-VOID
-wa_halbtc8723a1ant_MonitorC2h(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- u1Byte tmp1b=0x0;
- u4Byte curC2hTotalCnt=0x0;
- static u4Byte preC2hTotalCnt=0x0, sameCntPollingTime=0x0;
-
- curC2hTotalCnt+=pCoexSta->btInfoC2hCnt[BT_INFO_SRC_8723A_1ANT_BT_RSP];
-
- if(curC2hTotalCnt == preC2hTotalCnt)
- {
- sameCntPollingTime++;
- }
- else
- {
- preC2hTotalCnt = curC2hTotalCnt;
- sameCntPollingTime = 0;
- }
-
- if(sameCntPollingTime >= 2)
- {
- tmp1b = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x1af);
- if(tmp1b != 0x0)
- {
- pCoexSta->c2hHangDetectCnt++;
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x1af, 0x0);
- }
- }
-}
-
-//============================================================
-// extern function start with EXhalbtc8723a1ant_
-//============================================================
-VOID
-EXhalbtc8723a1ant_InitHwConfig(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 1Ant Init HW Config!!\n"));
-
- // backup rf 0x1e value
- pCoexDm->btRf0x1eBackup =
- pBtCoexist->fBtcGetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff);
-
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x20);
-
- // enable counter statistics
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0x4);
-
- // coex table
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cc, 0x0); // 1-Ant coex
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c8, 0xffff); // wifi break table
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c4, 0x55555555); //coex table
-
- // antenna switch control parameter
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x858, 0xaaaaaaaa);
-
- pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x860, 0x210); //set antenna at wifi side if ANTSW is software control
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x870, 0x300); //SPDT(connected with TRSW) control by hardware PTA
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x874, 0x22804000); //ANTSW keep by GNT_BT
-
- // coexistence parameters
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x778, 0x1); // enable RTK mode PTA
-}
-
-VOID
-EXhalbtc8723a1ant_InitCoexDm(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Coex Mechanism Init!!\n"));
-
- halbtc8723a1ant_InitCoexDm(pBtCoexist);
-}
-
-VOID
-EXhalbtc8723a1ant_DisplayCoexInfo(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo;
- PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo;
- pu1Byte cliBuf=pBtCoexist->cliBuf;
- u1Byte u1Tmp[4], i, btInfoExt, psTdmaCase=0;
- u4Byte u4Tmp[4];
-
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[BT Coexist info]============");
- CL_PRINTF(cliBuf);
-
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", "Ant PG number/ Ant mechanism:", \
- pBoardInfo->pgAntNum, pBoardInfo->btdmAntNum);
- CL_PRINTF(cliBuf);
-
- if(pBtCoexist->bManualControl)
- {
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "[Action Manual control]!!");
- CL_PRINTF(cliBuf);
- }
-
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d", "BT stack/ hci ext ver", \
- ((pStackInfo->bProfileNotified)? "Yes":"No"), pStackInfo->hciVersion);
- CL_PRINTF(cliBuf);
-
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", "Wifi channel informed to BT", \
- pCoexDm->wifiChnlInfo[0], pCoexDm->wifiChnlInfo[1],
- pCoexDm->wifiChnlInfo[2]);
- CL_PRINTF(cliBuf);
-
- // wifi status
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Wifi Status]============");
- CL_PRINTF(cliBuf);
- pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_WIFI_STATUS);
-
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[BT Status]============");
- CL_PRINTF(cliBuf);
-
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ", "BT [status/ rssi/ retryCnt]", \
- ((pCoexSta->bC2hBtInquiryPage)?("inquiry/page scan"):((BT_8723A_1ANT_BT_STATUS_IDLE == pCoexDm->btStatus)? "idle":( (BT_8723A_1ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus)? "connected-idle":"busy"))),
- pCoexSta->btRssi, pCoexSta->btRetryCnt);
- CL_PRINTF(cliBuf);
-
- if(pStackInfo->bProfileNotified)
- {
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", "SCO/HID/PAN/A2DP", \
- pStackInfo->bScoExist, pStackInfo->bHidExist, pStackInfo->bPanExist, pStackInfo->bA2dpExist);
- CL_PRINTF(cliBuf);
-
- pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_BT_LINK_INFO);
- }
-
- btInfoExt = pCoexSta->btInfoExt;
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "BT Info A2DP rate", \
- (btInfoExt&BIT0)? "Basic rate":"EDR rate");
- CL_PRINTF(cliBuf);
-
- for(i=0; ibtInfoC2hCnt[i])
- {
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", GLBtInfoSrc8723a1Ant[i], \
- pCoexSta->btInfoC2h[i][0], pCoexSta->btInfoC2h[i][1],
- pCoexSta->btInfoC2h[i][2], pCoexSta->btInfoC2h[i][3],
- pCoexSta->btInfoC2h[i][4], pCoexSta->btInfoC2h[i][5],
- pCoexSta->btInfoC2h[i][6], pCoexSta->btInfoC2hCnt[i]);
- CL_PRINTF(cliBuf);
- }
- }
-
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "write 0x1af=0x0 num", \
- pCoexSta->c2hHangDetectCnt);
- CL_PRINTF(cliBuf);
-
- // Sw mechanism
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Sw mechanism]============");
- CL_PRINTF(cliBuf);
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d", "SM1[ShRf/ LpRA/ LimDig]", \
- pCoexDm->bCurRfRxLpfShrink, pCoexDm->bCurLowPenaltyRa, pCoexDm->bLimitedDig);
- CL_PRINTF(cliBuf);
-
- // Fw mechanism
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Fw mechanism]============");
- CL_PRINTF(cliBuf);
-
- if(!pBtCoexist->bManualControl)
- {
- psTdmaCase = pCoexDm->curPsTdma;
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x case-%d", "PS TDMA", \
- pCoexDm->psTdmaPara[0], pCoexDm->psTdmaPara[1],
- pCoexDm->psTdmaPara[2], pCoexDm->psTdmaPara[3],
- pCoexDm->psTdmaPara[4], psTdmaCase);
- CL_PRINTF(cliBuf);
-
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ", "IgnWlanAct", \
- pCoexDm->bCurIgnoreWlanAct);
- CL_PRINTF(cliBuf);
- }
-
- // Hw setting
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Hw setting]============");
- CL_PRINTF(cliBuf);
-
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "RF-A, 0x1e initVal", \
- pCoexDm->btRf0x1eBackup);
- CL_PRINTF(cliBuf);
-
- u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x778);
- u1Tmp[1] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x783);
- u1Tmp[2] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x796);
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "0x778/ 0x783/ 0x796", \
- u1Tmp[0], u1Tmp[1], u1Tmp[2]);
- CL_PRINTF(cliBuf);
-
- u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x880);
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x880", \
- u4Tmp[0]);
- CL_PRINTF(cliBuf);
-
- u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x40);
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x40", \
- u1Tmp[0]);
- CL_PRINTF(cliBuf);
-
- u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x550);
- u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x522);
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0x550(bcn ctrl)/0x522", \
- u4Tmp[0], u1Tmp[0]);
- CL_PRINTF(cliBuf);
-
- u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x484);
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x484(rate adaptive)", \
- u4Tmp[0]);
- CL_PRINTF(cliBuf);
-
- u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xc50);
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)", \
- u4Tmp[0]);
- CL_PRINTF(cliBuf);
-
- u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xda0);
- u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xda4);
- u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xda8);
- u4Tmp[3] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xdac);
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "0xda0/0xda4/0xda8/0xdac(FA cnt)", \
- u4Tmp[0], u4Tmp[1], u4Tmp[2], u4Tmp[3]);
- CL_PRINTF(cliBuf);
-
- u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c0);
- u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c4);
- u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c8);
- u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x6cc);
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)", \
- u4Tmp[0], u4Tmp[1], u4Tmp[2], u1Tmp[0]);
- CL_PRINTF(cliBuf);
-
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x770 (hp rx[31:16]/tx[15:0])", \
- pCoexSta->highPriorityRx, pCoexSta->highPriorityTx);
- CL_PRINTF(cliBuf);
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x774(lp rx[31:16]/tx[15:0])", \
- pCoexSta->lowPriorityRx, pCoexSta->lowPriorityTx);
- CL_PRINTF(cliBuf);
-
- pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_COEX_STATISTICS);
-}
-
-
-VOID
-EXhalbtc8723a1ant_IpsNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- )
-{
- if(BTC_IPS_ENTER == type)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS ENTER notify\n"));
- halbtc8723a1ant_CoexAllOff(pBtCoexist);
- }
- else if(BTC_IPS_LEAVE == type)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS LEAVE notify\n"));
- //halbtc8723a1ant_InitCoexDm(pBtCoexist);
- }
-}
-
-VOID
-EXhalbtc8723a1ant_LpsNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- )
-{
- if(BTC_LPS_ENABLE == type)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS ENABLE notify\n"));
- }
- else if(BTC_LPS_DISABLE == type)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS DISABLE notify\n"));
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8);
- }
-}
-
-VOID
-EXhalbtc8723a1ant_ScanNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- )
-{
- BOOLEAN bWifiConnected=FALSE;
-
- halbtc8723a1ant_NotifyFwScan(pBtCoexist, type);
-
- if(pBtCoexist->btInfo.bBtDisabled)
- {
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 9);
- }
- else
- {
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected);
- if(BTC_SCAN_START == type)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN START notify\n"));
- if(!bWifiConnected) // non-connected scan
- {
- //set 0x550[3]=1 before PsTdma
- halbtc8723a1ant_Reg0x550Bit3(pBtCoexist, TRUE);
- }
-
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4);
- }
- else if(BTC_SCAN_FINISH == type)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN FINISH notify\n"));
- if(!bWifiConnected) // non-connected scan
- {
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0);
- }
- else
- {
- halbtc8723a1ant_CoexForWifiConnect(pBtCoexist);
- }
- }
- }
-}
-
-VOID
-EXhalbtc8723a1ant_ConnectNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- )
-{
- BOOLEAN bWifiConnected=FALSE;
-
- if(pBtCoexist->btInfo.bBtDisabled)
- {
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 9);
- }
- else
- {
- if(BTC_ASSOCIATE_START == type)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT START notify\n"));
- //set 0x550[3]=1 before PsTdma
- halbtc8723a1ant_Reg0x550Bit3(pBtCoexist, TRUE);
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); // extend wifi slot
- }
- else if(BTC_ASSOCIATE_FINISH == type)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT FINISH notify\n"));
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected);
- if(!bWifiConnected) // non-connected scan
- {
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0);
- }
- else
- {
- halbtc8723a1ant_CoexForWifiConnect(pBtCoexist);
- }
- }
- }
-}
-
-VOID
-EXhalbtc8723a1ant_MediaStatusNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- )
-{
- if(BTC_MEDIA_CONNECT == type)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA connect notify\n"));
- }
- else
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA disconnect notify\n"));
- }
-}
-
-VOID
-EXhalbtc8723a1ant_SpecialPacketNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- )
-{
- if(type == BTC_PACKET_DHCP)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], DHCP Packet notify\n"));
- if(pBtCoexist->btInfo.bBtDisabled)
- {
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 9);
- }
- else
- {
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 18);
- }
- }
-}
-
-VOID
-EXhalbtc8723a1ant_BtInfoNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN pu1Byte tmpBuf,
- IN u1Byte length
- )
-{
- u1Byte btInfo=0;
- u1Byte i, rspSource=0;
- BOOLEAN bBtHsOn=FALSE, bBtBusy=FALSE, bForceLps=FALSE;
-
- pCoexSta->bC2hBtInfoReqSent = FALSE;
-
- rspSource = BT_INFO_SRC_8723A_1ANT_BT_RSP;
- pCoexSta->btInfoC2hCnt[rspSource]++;
-
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Bt info[%d], length=%d, hex data=[", rspSource, length));
- for(i=0; ibtInfoC2h[rspSource][i] = tmpBuf[i];
- if(i == 0)
- btInfo = tmpBuf[i];
- if(i == length-1)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("0x%02x]\n", tmpBuf[i]));
- }
- else
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("0x%02x, ", tmpBuf[i]));
- }
- }
-
- if(BT_INFO_SRC_8723A_1ANT_WIFI_FW != rspSource)
- {
- pCoexSta->btRetryCnt =
- pCoexSta->btInfoC2h[rspSource][1];
-
- pCoexSta->btRssi =
- pCoexSta->btInfoC2h[rspSource][2]*2+10;
-
- pCoexSta->btInfoExt =
- pCoexSta->btInfoC2h[rspSource][3];
- }
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn);
- // check BIT2 first ==> check if bt is under inquiry or page scan
- if(btInfo & BT_INFO_8723A_1ANT_B_INQ_PAGE)
- {
- pCoexSta->bC2hBtInquiryPage = TRUE;
- }
- else
- {
- pCoexSta->bC2hBtInquiryPage = FALSE;
- }
- btInfo &= ~BIT2;
- if(!(btInfo & BIT0))
- {
- pCoexDm->btStatus = BT_STATE_8723A_1ANT_NO_CONNECTION;
- bForceLps = FALSE;
- }
- else
- {
- bForceLps = TRUE;
- if(btInfo == 0x1)
- {
- pCoexDm->btStatus = BT_STATE_8723A_1ANT_CONNECT_IDLE;
- }
- else if(btInfo == 0x9)
- {
- pCoexDm->btStatus = BT_STATE_8723A_1ANT_ACL_ONLY_BUSY;
- bBtBusy = TRUE;
- }
- else if(btInfo == 0x13)
- {
- pCoexDm->btStatus = BT_STATE_8723A_1ANT_SCO_ONLY_BUSY;
- bBtBusy = TRUE;
- }
- else if(btInfo == 0x1b)
- {
- pCoexDm->btStatus = BT_STATE_8723A_1ANT_ACL_SCO_BUSY;
- bBtBusy = TRUE;
- }
- else if(btInfo == 0x29)
- {
- pCoexDm->btStatus = BT_STATE_8723A_1ANT_HID_BUSY;
- bBtBusy = TRUE;
- }
- else if(btInfo == 0x3b)
- {
- pCoexDm->btStatus = BT_STATE_8723A_1ANT_HID_SCO_BUSY;
- bBtBusy = TRUE;
- }
- }
- pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bBtBusy);
- pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_LIMITED_DIG, &bBtBusy);
- if(bForceLps)
- pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_ENTER_LPS, NULL);
- else
- pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_NORMAL_LPS, NULL);
-
- if( (BT_STATE_8723A_1ANT_NO_CONNECTION == pCoexDm->btStatus) ||
- (BT_STATE_8723A_1ANT_CONNECT_IDLE == pCoexDm->btStatus) )
- {
- if(pCoexSta->bC2hBtInquiryPage)
- pCoexDm->btStatus = BT_STATE_8723A_1ANT_INQ_OR_PAG;
- }
-}
-
-VOID
-EXhalbtc8723a1ant_HaltNotify(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- halbtc8723a1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 0);
-
- halbtc8723a1ant_LowPenaltyRa(pBtCoexist, FORCE_EXEC, FALSE);
- halbtc8723a1ant_RfShrink(pBtCoexist, FORCE_EXEC, FALSE);
-
- halbtc8723a1ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, TRUE);
- EXhalbtc8723a1ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT);
-}
-
-VOID
-EXhalbtc8723a1ant_Periodical(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- BOOLEAN bScan=FALSE, bLink=FALSE, bRoam=FALSE, bWifiConnected=FALSE;
-
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 1Ant Periodical!!\n"));
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan);
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink);
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam);
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected);
-
- // work around for c2h hang
- wa_halbtc8723a1ant_MonitorC2h(pBtCoexist);
-
- halbtc8723a1ant_QueryBtInfo(pBtCoexist);
- halbtc8723a1ant_MonitorBtCtr(pBtCoexist);
- halbtc8723a1ant_MonitorBtEnableDisable(pBtCoexist);
-
-
- if(bScan)
- return;
- if(bLink)
- return;
-
- if(bWifiConnected)
- {
- if(pBtCoexist->btInfo.bBtDisabled)
- {
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 9);
-
- halbtc8723a1ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a1ant_RfShrink(pBtCoexist, NORMAL_EXEC, FALSE);
- }
- else
- {
- halbtc8723a1ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8723a1ant_RfShrink(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a1ant_CoexForWifiConnect(pBtCoexist);
- }
- }
- else
- {
- halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0);
-
- halbtc8723a1ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a1ant_RfShrink(pBtCoexist, NORMAL_EXEC, FALSE);
- }
-}
-
-
-#endif
-
diff --git a/hal/btc/HalBtc8723a1Ant.h b/hal/btc/HalBtc8723a1Ant.h
deleted file mode 100644
index 6d4e1b4..0000000
--- a/hal/btc/HalBtc8723a1Ant.h
+++ /dev/null
@@ -1,171 +0,0 @@
-//===========================================
-// The following is for 8723A 1Ant BT Co-exist definition
-//===========================================
-#define BT_INFO_8723A_1ANT_B_FTP BIT7
-#define BT_INFO_8723A_1ANT_B_A2DP BIT6
-#define BT_INFO_8723A_1ANT_B_HID BIT5
-#define BT_INFO_8723A_1ANT_B_SCO_BUSY BIT4
-#define BT_INFO_8723A_1ANT_B_ACL_BUSY BIT3
-#define BT_INFO_8723A_1ANT_B_INQ_PAGE BIT2
-#define BT_INFO_8723A_1ANT_B_SCO_ESCO BIT1
-#define BT_INFO_8723A_1ANT_B_CONNECTION BIT0
-
-typedef enum _BT_STATE_8723A_1ANT{
- BT_STATE_8723A_1ANT_DISABLED = 0,
- BT_STATE_8723A_1ANT_NO_CONNECTION = 1,
- BT_STATE_8723A_1ANT_CONNECT_IDLE = 2,
- BT_STATE_8723A_1ANT_INQ_OR_PAG = 3,
- BT_STATE_8723A_1ANT_ACL_ONLY_BUSY = 4,
- BT_STATE_8723A_1ANT_SCO_ONLY_BUSY = 5,
- BT_STATE_8723A_1ANT_ACL_SCO_BUSY = 6,
- BT_STATE_8723A_1ANT_HID_BUSY = 7,
- BT_STATE_8723A_1ANT_HID_SCO_BUSY = 8,
- BT_STATE_8723A_1ANT_MAX
-}BT_STATE_8723A_1ANT, *PBT_STATE_8723A_1ANT;
-
-#define BTC_RSSI_COEX_THRESH_TOL_8723A_1ANT 2
-
-typedef enum _BT_INFO_SRC_8723A_1ANT{
- BT_INFO_SRC_8723A_1ANT_WIFI_FW = 0x0,
- BT_INFO_SRC_8723A_1ANT_BT_RSP = 0x1,
- BT_INFO_SRC_8723A_1ANT_BT_ACTIVE_SEND = 0x2,
- BT_INFO_SRC_8723A_1ANT_MAX
-}BT_INFO_SRC_8723A_1ANT,*PBT_INFO_SRC_8723A_1ANT;
-
-typedef enum _BT_8723A_1ANT_BT_STATUS{
- BT_8723A_1ANT_BT_STATUS_IDLE = 0x0,
- BT_8723A_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
- BT_8723A_1ANT_BT_STATUS_NON_IDLE = 0x2,
- BT_8723A_1ANT_BT_STATUS_MAX
-}BT_8723A_1ANT_BT_STATUS,*PBT_8723A_1ANT_BT_STATUS;
-
-typedef enum _BT_8723A_1ANT_COEX_ALGO{
- BT_8723A_1ANT_COEX_ALGO_UNDEFINED = 0x0,
- BT_8723A_1ANT_COEX_ALGO_SCO = 0x1,
- BT_8723A_1ANT_COEX_ALGO_HID = 0x2,
- BT_8723A_1ANT_COEX_ALGO_A2DP = 0x3,
- BT_8723A_1ANT_COEX_ALGO_PANEDR = 0x4,
- BT_8723A_1ANT_COEX_ALGO_PANHS = 0x5,
- BT_8723A_1ANT_COEX_ALGO_PANEDR_A2DP = 0x6,
- BT_8723A_1ANT_COEX_ALGO_PANEDR_HID = 0x7,
- BT_8723A_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x8,
- BT_8723A_1ANT_COEX_ALGO_HID_A2DP = 0x9,
- BT_8723A_1ANT_COEX_ALGO_MAX
-}BT_8723A_1ANT_COEX_ALGO,*PBT_8723A_1ANT_COEX_ALGO;
-
-typedef struct _COEX_DM_8723A_1ANT{
- // fw mechanism
- BOOLEAN bCurIgnoreWlanAct;
- BOOLEAN bPreIgnoreWlanAct;
- u1Byte prePsTdma;
- u1Byte curPsTdma;
- u1Byte psTdmaPara[5];
- u1Byte psTdmaDuAdjType;
- u4Byte psTdmaMonitorCnt;
- u4Byte psTdmaGlobalCnt;
- BOOLEAN bResetTdmaAdjust;
- BOOLEAN bPrePsTdmaOn;
- BOOLEAN bCurPsTdmaOn;
-
- // sw mechanism
- BOOLEAN bPreRfRxLpfShrink;
- BOOLEAN bCurRfRxLpfShrink;
- u4Byte btRf0x1eBackup;
- BOOLEAN bPreLowPenaltyRa;
- BOOLEAN bCurLowPenaltyRa;
- u4Byte preVal0x6c0;
- u4Byte curVal0x6c0;
- u4Byte preVal0x6c8;
- u4Byte curVal0x6c8;
- u1Byte preVal0x6cc;
- u1Byte curVal0x6cc;
- BOOLEAN bLimitedDig;
-
- // algorithm related
- u1Byte preAlgorithm;
- u1Byte curAlgorithm;
- u1Byte btStatus;
- u1Byte wifiChnlInfo[3];
-} COEX_DM_8723A_1ANT, *PCOEX_DM_8723A_1ANT;
-
-typedef struct _COEX_STA_8723A_1ANT{
- u4Byte highPriorityTx;
- u4Byte highPriorityRx;
- u4Byte lowPriorityTx;
- u4Byte lowPriorityRx;
- u1Byte btRssi;
- u1Byte preBtRssiState;
- u1Byte preBtRssiState1;
- u1Byte preWifiRssiState[4];
- BOOLEAN bC2hBtInfoReqSent;
- u1Byte btInfoC2h[BT_INFO_SRC_8723A_1ANT_MAX][10];
- u4Byte btInfoC2hCnt[BT_INFO_SRC_8723A_1ANT_MAX];
- BOOLEAN bC2hBtInquiryPage;
- u1Byte btRetryCnt;
- u1Byte btInfoExt;
- //BOOLEAN bHoldForStackOperation;
- //u1Byte bHoldPeriodCnt;
- // this is for c2h hang work-around
- u4Byte c2hHangDetectCnt;
-}COEX_STA_8723A_1ANT, *PCOEX_STA_8723A_1ANT;
-
-//===========================================
-// The following is interface which will notify coex module.
-//===========================================
-VOID
-EXhalbtc8723a1ant_InitHwConfig(
- IN PBTC_COEXIST pBtCoexist
- );
-VOID
-EXhalbtc8723a1ant_InitCoexDm(
- IN PBTC_COEXIST pBtCoexist
- );
-VOID
-EXhalbtc8723a1ant_IpsNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- );
-VOID
-EXhalbtc8723a1ant_LpsNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- );
-VOID
-EXhalbtc8723a1ant_ScanNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- );
-VOID
-EXhalbtc8723a1ant_ConnectNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- );
-VOID
-EXhalbtc8723a1ant_MediaStatusNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- );
-VOID
-EXhalbtc8723a1ant_SpecialPacketNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- );
-VOID
-EXhalbtc8723a1ant_BtInfoNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN pu1Byte tmpBuf,
- IN u1Byte length
- );
-VOID
-EXhalbtc8723a1ant_HaltNotify(
- IN PBTC_COEXIST pBtCoexist
- );
-VOID
-EXhalbtc8723a1ant_Periodical(
- IN PBTC_COEXIST pBtCoexist
- );
-VOID
-EXhalbtc8723a1ant_DisplayCoexInfo(
- IN PBTC_COEXIST pBtCoexist
- );
-
diff --git a/hal/btc/HalBtc8723a2Ant.c b/hal/btc/HalBtc8723a2Ant.c
deleted file mode 100644
index 1becd5c..0000000
--- a/hal/btc/HalBtc8723a2Ant.c
+++ /dev/null
@@ -1,3746 +0,0 @@
-//============================================================
-// Description:
-//
-// This file is for RTL8723A Co-exist mechanism
-//
-// History
-// 2012/08/22 Cosa first check in.
-// 2012/11/14 Cosa Revise for 8723A 2Ant out sourcing.
-//
-//============================================================
-
-//============================================================
-// include files
-//============================================================
-#include "Mp_Precomp.h"
-
-#if WPP_SOFTWARE_TRACE
-#include "HalBtc8723a2Ant.tmh"
-#endif
-
-#if(BT_30_SUPPORT == 1)
-//============================================================
-// Global variables, these are static variables
-//============================================================
-static COEX_DM_8723A_2ANT GLCoexDm8723a2Ant;
-static PCOEX_DM_8723A_2ANT pCoexDm=&GLCoexDm8723a2Ant;
-static COEX_STA_8723A_2ANT GLCoexSta8723a2Ant;
-static PCOEX_STA_8723A_2ANT pCoexSta=&GLCoexSta8723a2Ant;
-
-const char *const GLBtInfoSrc8723a2Ant[]={
- "BT Info[wifi fw]",
- "BT Info[bt rsp]",
- "BT Info[bt auto report]",
-};
-
-//============================================================
-// local function proto type if needed
-//============================================================
-//============================================================
-// local function start with halbtc8723a2ant_
-//============================================================
-BOOLEAN
-halbtc8723a2ant_IsWifiIdle(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- BOOLEAN bWifiConnected=FALSE, bScan=FALSE, bLink=FALSE, bRoam=FALSE;
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected);
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan);
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink);
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam);
-
- if(bWifiConnected)
- return FALSE;
- if(bScan)
- return FALSE;
- if(bLink)
- return FALSE;
- if(bRoam)
- return FALSE;
-
- return TRUE;
-}
-
-BOOLEAN
-halbtc8723a2ant_IsWifiConnectedIdle(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- BOOLEAN bWifiConnected=FALSE, bScan=FALSE, bLink=FALSE, bRoam=FALSE, bWifiBusy=FALSE;
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected);
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan);
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink);
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam);
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy);
-
- if(bScan)
- return FALSE;
- if(bLink)
- return FALSE;
- if(bRoam)
- return FALSE;
- if(bWifiConnected && !bWifiBusy)
- return TRUE;
- else
- return FALSE;
-}
-
-u1Byte
-halbtc8723a2ant_BtRssiState(
- u1Byte levelNum,
- u1Byte rssiThresh,
- u1Byte rssiThresh1
- )
-{
- s4Byte btRssi=0;
- u1Byte btRssiState=pCoexSta->preBtRssiState;
-
- btRssi = pCoexSta->btRssi;
-
- if(levelNum == 2)
- {
- if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_LOW) ||
- (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_LOW))
- {
- if(btRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8723A_2ANT))
- {
- btRssiState = BTC_RSSI_STATE_HIGH;
- }
- else
- {
- btRssiState = BTC_RSSI_STATE_STAY_LOW;
- }
- }
- else
- {
- if(btRssi < rssiThresh)
- {
- btRssiState = BTC_RSSI_STATE_LOW;
- }
- else
- {
- btRssiState = BTC_RSSI_STATE_STAY_HIGH;
- }
- }
- }
- else if(levelNum == 3)
- {
- if(rssiThresh > rssiThresh1)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Rssi thresh error!!\n"));
- return pCoexSta->preBtRssiState;
- }
-
- if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_LOW) ||
- (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_LOW))
- {
- if(btRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8723A_2ANT))
- {
- btRssiState = BTC_RSSI_STATE_MEDIUM;
- }
- else
- {
- btRssiState = BTC_RSSI_STATE_STAY_LOW;
- }
- }
- else if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_MEDIUM) ||
- (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_MEDIUM))
- {
- if(btRssi >= (rssiThresh1+BTC_RSSI_COEX_THRESH_TOL_8723A_2ANT))
- {
- btRssiState = BTC_RSSI_STATE_HIGH;
- }
- else if(btRssi < rssiThresh)
- {
- btRssiState = BTC_RSSI_STATE_LOW;
- }
- else
- {
- btRssiState = BTC_RSSI_STATE_STAY_MEDIUM;
- }
- }
- else
- {
- if(btRssi < rssiThresh1)
- {
- btRssiState = BTC_RSSI_STATE_MEDIUM;
- }
- else
- {
- btRssiState = BTC_RSSI_STATE_STAY_HIGH;
- }
- }
- }
-
- pCoexSta->preBtRssiState = btRssiState;
-
- return btRssiState;
-}
-
-u1Byte
-halbtc8723a2ant_WifiRssiState(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte index,
- IN u1Byte levelNum,
- IN u1Byte rssiThresh,
- IN u1Byte rssiThresh1
- )
-{
- s4Byte wifiRssi=0;
- u1Byte wifiRssiState=pCoexSta->preWifiRssiState[index];
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi);
-
- if(levelNum == 2)
- {
- if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) ||
- (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW))
- {
- if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8723A_2ANT))
- {
- wifiRssiState = BTC_RSSI_STATE_HIGH;
- }
- else
- {
- wifiRssiState = BTC_RSSI_STATE_STAY_LOW;
- }
- }
- else
- {
- if(wifiRssi < rssiThresh)
- {
- wifiRssiState = BTC_RSSI_STATE_LOW;
- }
- else
- {
- wifiRssiState = BTC_RSSI_STATE_STAY_HIGH;
- }
- }
- }
- else if(levelNum == 3)
- {
- if(rssiThresh > rssiThresh1)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi RSSI thresh error!!\n"));
- return pCoexSta->preWifiRssiState[index];
- }
-
- if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) ||
- (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW))
- {
- if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8723A_2ANT))
- {
- wifiRssiState = BTC_RSSI_STATE_MEDIUM;
- }
- else
- {
- wifiRssiState = BTC_RSSI_STATE_STAY_LOW;
- }
- }
- else if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_MEDIUM) ||
- (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_MEDIUM))
- {
- if(wifiRssi >= (rssiThresh1+BTC_RSSI_COEX_THRESH_TOL_8723A_2ANT))
- {
- wifiRssiState = BTC_RSSI_STATE_HIGH;
- }
- else if(wifiRssi < rssiThresh)
- {
- wifiRssiState = BTC_RSSI_STATE_LOW;
- }
- else
- {
- wifiRssiState = BTC_RSSI_STATE_STAY_MEDIUM;
- }
- }
- else
- {
- if(wifiRssi < rssiThresh1)
- {
- wifiRssiState = BTC_RSSI_STATE_MEDIUM;
- }
- else
- {
- wifiRssiState = BTC_RSSI_STATE_STAY_HIGH;
- }
- }
- }
-
- pCoexSta->preWifiRssiState[index] = wifiRssiState;
-
- return wifiRssiState;
-}
-
-VOID
-halbtc8723a2ant_IndicateWifiChnlBwInfo(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- )
-{
- u1Byte H2C_Parameter[3] ={0};
- u4Byte wifiBw;
- u1Byte wifiCentralChnl;
-
- // only 2.4G we need to inform bt the chnl mask
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, &wifiCentralChnl);
- if( (BTC_MEDIA_CONNECT == type) &&
- (wifiCentralChnl <= 14) )
- {
- H2C_Parameter[0] = 0x1;
- H2C_Parameter[1] = wifiCentralChnl;
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
- if(BTC_WIFI_BW_HT40 == wifiBw)
- H2C_Parameter[2] = 0x30;
- else
- H2C_Parameter[2] = 0x20;
- }
-
- pCoexDm->wifiChnlInfo[0] = H2C_Parameter[0];
- pCoexDm->wifiChnlInfo[1] = H2C_Parameter[1];
- pCoexDm->wifiChnlInfo[2] = H2C_Parameter[2];
-
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], FW write 0x19=0x%x\n",
- H2C_Parameter[0]<<16|H2C_Parameter[1]<<8|H2C_Parameter[2]));
-
- pBtCoexist->fBtcFillH2c(pBtCoexist, 0x19, 3, H2C_Parameter);
-}
-
-VOID
-halbtc8723a2ant_QueryBtInfo(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- u1Byte H2C_Parameter[1] ={0};
-
- pCoexSta->bC2hBtInfoReqSent = TRUE;
-
- H2C_Parameter[0] |= BIT0; // trigger
-
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Query Bt Info, FW write 0x38=0x%x\n",
- H2C_Parameter[0]));
-
- pBtCoexist->fBtcFillH2c(pBtCoexist, 0x38, 1, H2C_Parameter);
-}
-u1Byte
-halbtc8723a2ant_ActionAlgorithm(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo;
- BOOLEAN bBtHsOn=FALSE, bBtBusy=FALSE, bLimitedDig=FALSE;
- u1Byte algorithm=BT_8723A_2ANT_COEX_ALGO_UNDEFINED;
- u1Byte numOfDiffProfile=0;
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn);
-
- //======================
- // here we get BT status first
- //======================
- pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_IDLE;
-
- if((pStackInfo->bScoExist) ||(bBtHsOn) ||(pStackInfo->bHidExist))
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO or HID or HS exists, set BT non-idle !!!\n"));
- pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_NON_IDLE;
- }
- else
- {
- // A2dp profile
- if( (pBtCoexist->stackInfo.numOfLink == 1) &&
- (pStackInfo->bA2dpExist) )
- {
- if( (pCoexSta->lowPriorityTx+ pCoexSta->lowPriorityRx) < 100)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP, low priority tx+rx < 100, set BT connected-idle!!!\n"));
- pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE;
- }
- else
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP, low priority tx+rx >= 100, set BT non-idle!!!\n"));
- pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_NON_IDLE;
- }
- }
- // Pan profile
- if( (pBtCoexist->stackInfo.numOfLink == 1) &&
- (pStackInfo->bPanExist) )
- {
- if((pCoexSta->lowPriorityTx+ pCoexSta->lowPriorityRx) < 600)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN, low priority tx+rx < 600, set BT connected-idle!!!\n"));
- pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE;
- }
- else
- {
- if(pCoexSta->lowPriorityTx)
- {
- if((pCoexSta->lowPriorityRx /pCoexSta->lowPriorityTx)>9 )
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN, low priority rx/tx > 9, set BT connected-idle!!!\n"));
- pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE;
- }
- }
- }
- if(BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE != pCoexDm->btStatus)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN, set BT non-idle!!!\n"));
- pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_NON_IDLE;
- }
- }
- // Pan+A2dp profile
- if( (pBtCoexist->stackInfo.numOfLink == 2) &&
- (pStackInfo->bA2dpExist) &&
- (pStackInfo->bPanExist) )
- {
- if((pCoexSta->lowPriorityTx+ pCoexSta->lowPriorityRx) < 600)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN+A2DP, low priority tx+rx < 600, set BT connected-idle!!!\n"));
- pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE;
- }
- else
- {
- if(pCoexSta->lowPriorityTx)
- {
- if((pCoexSta->lowPriorityRx /pCoexSta->lowPriorityTx)>9 )
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN+A2DP, low priority rx/tx > 9, set BT connected-idle!!!\n"));
- pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE;
- }
- }
- }
- if(BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE != pCoexDm->btStatus)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN+A2DP, set BT non-idle!!!\n"));
- pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_NON_IDLE;
- }
- }
- }
- if(BT_8723A_2ANT_BT_STATUS_IDLE != pCoexDm->btStatus)
- {
- bBtBusy = TRUE;
- bLimitedDig = TRUE;
- }
- else
- {
- bBtBusy = FALSE;
- bLimitedDig = FALSE;
- }
- pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bBtBusy);
- pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_LIMITED_DIG, &bLimitedDig);
- //======================
-
- if(!pStackInfo->bBtLinkExist)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], No profile exists!!!\n"));
- return algorithm;
- }
-
- if(pStackInfo->bScoExist)
- numOfDiffProfile++;
- if(pStackInfo->bHidExist)
- numOfDiffProfile++;
- if(pStackInfo->bPanExist)
- numOfDiffProfile++;
- if(pStackInfo->bA2dpExist)
- numOfDiffProfile++;
-
- if(numOfDiffProfile == 1)
- {
- if(pStackInfo->bScoExist)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO only\n"));
- algorithm = BT_8723A_2ANT_COEX_ALGO_SCO;
- }
- else
- {
- if(pStackInfo->bHidExist)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID only\n"));
- algorithm = BT_8723A_2ANT_COEX_ALGO_HID;
- }
- else if(pStackInfo->bA2dpExist)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP only\n"));
- algorithm = BT_8723A_2ANT_COEX_ALGO_A2DP;
- }
- else if(pStackInfo->bPanExist)
- {
- if(bBtHsOn)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN(HS) only\n"));
- algorithm = BT_8723A_2ANT_COEX_ALGO_PANHS;
- }
- else
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN(EDR) only\n"));
- algorithm = BT_8723A_2ANT_COEX_ALGO_PANEDR;
- }
- }
- }
- }
- else if(numOfDiffProfile == 2)
- {
- if(pStackInfo->bScoExist)
- {
- if(pStackInfo->bHidExist)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID\n"));
- algorithm = BT_8723A_2ANT_COEX_ALGO_HID;
- }
- else if(pStackInfo->bA2dpExist)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + A2DP ==> SCO\n"));
- algorithm = BT_8723A_2ANT_COEX_ALGO_SCO;
- }
- else if(pStackInfo->bPanExist)
- {
- if(bBtHsOn)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + PAN(HS)\n"));
- algorithm = BT_8723A_2ANT_COEX_ALGO_SCO;
- }
- else
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + PAN(EDR)\n"));
- algorithm = BT_8723A_2ANT_COEX_ALGO_PANEDR_HID;
- }
- }
- }
- else
- {
- if( pStackInfo->bHidExist &&
- pStackInfo->bA2dpExist )
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + A2DP\n"));
- algorithm = BT_8723A_2ANT_COEX_ALGO_HID_A2DP;
- }
- else if( pStackInfo->bHidExist &&
- pStackInfo->bPanExist )
- {
- if(bBtHsOn)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + PAN(HS)\n"));
- algorithm = BT_8723A_2ANT_COEX_ALGO_HID_A2DP;
- }
- else
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + PAN(EDR)\n"));
- algorithm = BT_8723A_2ANT_COEX_ALGO_PANEDR_HID;
- }
- }
- else if( pStackInfo->bPanExist &&
- pStackInfo->bA2dpExist )
- {
- if(bBtHsOn)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP + PAN(HS)\n"));
- algorithm = BT_8723A_2ANT_COEX_ALGO_A2DP;
- }
- else
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP + PAN(EDR)\n"));
- algorithm = BT_8723A_2ANT_COEX_ALGO_PANEDR_A2DP;
- }
- }
- }
- }
- else if(numOfDiffProfile == 3)
- {
- if(pStackInfo->bScoExist)
- {
- if( pStackInfo->bHidExist &&
- pStackInfo->bA2dpExist )
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID + A2DP ==> HID\n"));
- algorithm = BT_8723A_2ANT_COEX_ALGO_HID;
- }
- else if( pStackInfo->bHidExist &&
- pStackInfo->bPanExist )
- {
- if(bBtHsOn)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID + PAN(HS)\n"));
- algorithm = BT_8723A_2ANT_COEX_ALGO_HID_A2DP;
- }
- else
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID + PAN(EDR)\n"));
- algorithm = BT_8723A_2ANT_COEX_ALGO_PANEDR_HID;
- }
- }
- else if( pStackInfo->bPanExist &&
- pStackInfo->bA2dpExist )
- {
- if(bBtHsOn)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + A2DP + PAN(HS)\n"));
- algorithm = BT_8723A_2ANT_COEX_ALGO_SCO;
- }
- else
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n"));
- algorithm = BT_8723A_2ANT_COEX_ALGO_PANEDR_HID;
- }
- }
- }
- else
- {
- if( pStackInfo->bHidExist &&
- pStackInfo->bPanExist &&
- pStackInfo->bA2dpExist )
- {
- if(bBtHsOn)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + A2DP + PAN(HS)\n"));
- algorithm = BT_8723A_2ANT_COEX_ALGO_HID_A2DP;
- }
- else
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + A2DP + PAN(EDR)\n"));
- algorithm = BT_8723A_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
- }
- }
- }
- }
- else if(numOfDiffProfile >= 3)
- {
- if(pStackInfo->bScoExist)
- {
- if( pStackInfo->bHidExist &&
- pStackInfo->bPanExist &&
- pStackInfo->bA2dpExist )
- {
- if(bBtHsOn)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n"));
-
- }
- else
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"));
- algorithm = BT_8723A_2ANT_COEX_ALGO_PANEDR_HID;
- }
- }
- }
- }
-
- return algorithm;
-}
-
-BOOLEAN
-halbtc8723a2ant_NeedToDecBtPwr(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- BOOLEAN bRet=FALSE;
- BOOLEAN bBtHsOn=FALSE, bWifiConnected=FALSE;
- s4Byte btHsRssi=0;
- u1Byte btRssiState=BTC_RSSI_STATE_HIGH;
-
- btRssiState = halbtc8723a2ant_BtRssiState(2, 42, 0);
-
- if(!pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn))
- return FALSE;
- if(!pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected))
- return FALSE;
- if(!pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_HS_RSSI, &btHsRssi))
- return FALSE;
- if(BTC_RSSI_LOW(btRssiState))
- return FALSE;
-
- if(bWifiConnected)
- {
- if(bBtHsOn)
- {
- if(btHsRssi > 37)
- {
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Need to decrease bt power for HS mode!!\n"));
- bRet = TRUE;
- }
- }
- else
- {
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Need to decrease bt power for Wifi is connected!!\n"));
- bRet = TRUE;
- }
- }
-
- return bRet;
-}
-
-VOID
-halbtc8723a2ant_SetFwDacSwingLevel(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte dacSwingLvl
- )
-{
- u1Byte H2C_Parameter[1] ={0};
-
- // There are several type of dacswing
- // 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6
- H2C_Parameter[0] = dacSwingLvl;
-
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Set Dac Swing Level=0x%x\n", dacSwingLvl));
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], FW write 0x29=0x%x\n", H2C_Parameter[0]));
-
- pBtCoexist->fBtcFillH2c(pBtCoexist, 0x29, 1, H2C_Parameter);
-}
-
-VOID
-halbtc8723a2ant_SetFwDecBtPwr(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bDecBtPwr
- )
-{
- u1Byte H2C_Parameter[1] ={0};
-
- H2C_Parameter[0] = 0;
-
- if(bDecBtPwr)
- {
- H2C_Parameter[0] |= BIT1;
- }
-
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], decrease Bt Power : %s, FW write 0x21=0x%x\n",
- (bDecBtPwr? "Yes!!":"No!!"), H2C_Parameter[0]));
-
- pBtCoexist->fBtcFillH2c(pBtCoexist, 0x21, 1, H2C_Parameter);
-}
-
-VOID
-halbtc8723a2ant_DecBtPwr(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bForceExec,
- IN BOOLEAN bDecBtPwr
- )
-{
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s Dec BT power = %s\n",
- (bForceExec? "force to":""), ((bDecBtPwr)? "ON":"OFF")));
- pCoexDm->bCurDecBtPwr = bDecBtPwr;
-
- if(!bForceExec)
- {
- if(pCoexDm->bPreDecBtPwr == pCoexDm->bCurDecBtPwr)
- return;
- }
- halbtc8723a2ant_SetFwDecBtPwr(pBtCoexist, pCoexDm->bCurDecBtPwr);
-
- pCoexDm->bPreDecBtPwr = pCoexDm->bCurDecBtPwr;
-}
-
-VOID
-halbtc8723a2ant_FwDacSwingLvl(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bForceExec,
- IN u1Byte fwDacSwingLvl
- )
-{
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s set FW Dac Swing level = %d\n",
- (bForceExec? "force to":""), fwDacSwingLvl));
- pCoexDm->curFwDacSwingLvl = fwDacSwingLvl;
-
- if(!bForceExec)
- {
- if(pCoexDm->preFwDacSwingLvl == pCoexDm->curFwDacSwingLvl)
- return;
- }
-
- halbtc8723a2ant_SetFwDacSwingLevel(pBtCoexist, pCoexDm->curFwDacSwingLvl);
-
- pCoexDm->preFwDacSwingLvl = pCoexDm->curFwDacSwingLvl;
-}
-
-VOID
-halbtc8723a2ant_SetSwRfRxLpfCorner(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bRxRfShrinkOn
- )
-{
- if(bRxRfShrinkOn)
- {
- //Shrink RF Rx LPF corner
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Shrink RF Rx LPF corner!!\n"));
- pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, 0xf0ff7);
- }
- else
- {
- //Resume RF Rx LPF corner
- // After initialized, we can use pCoexDm->btRf0x1eBackup
- if(pBtCoexist->bInitilized)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Resume RF Rx LPF corner!!\n"));
- pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, pCoexDm->btRf0x1eBackup);
- }
- }
-}
-
-VOID
-halbtc8723a2ant_RfShrink(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bForceExec,
- IN BOOLEAN bRxRfShrinkOn
- )
-{
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Rx RF Shrink = %s\n",
- (bForceExec? "force to":""), ((bRxRfShrinkOn)? "ON":"OFF")));
- pCoexDm->bCurRfRxLpfShrink = bRxRfShrinkOn;
-
- if(!bForceExec)
- {
- if(pCoexDm->bPreRfRxLpfShrink == pCoexDm->bCurRfRxLpfShrink)
- return;
- }
- halbtc8723a2ant_SetSwRfRxLpfCorner(pBtCoexist, pCoexDm->bCurRfRxLpfShrink);
-
- pCoexDm->bPreRfRxLpfShrink = pCoexDm->bCurRfRxLpfShrink;
-}
-
-VOID
-halbtc8723a2ant_SetSwPenaltyTxRateAdaptive(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bLowPenaltyRa
- )
-{
- u1Byte tmpU1;
-
- tmpU1 = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x4fd);
- tmpU1 |= BIT0;
- if(bLowPenaltyRa)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Tx rate adaptive, set low penalty!!\n"));
- tmpU1 &= ~BIT2;
- }
- else
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Tx rate adaptive, set normal!!\n"));
- tmpU1 |= BIT2;
- }
-
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x4fd, tmpU1);
-}
-
-VOID
-halbtc8723a2ant_LowPenaltyRa(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bForceExec,
- IN BOOLEAN bLowPenaltyRa
- )
-{
- return;
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn LowPenaltyRA = %s\n",
- (bForceExec? "force to":""), ((bLowPenaltyRa)? "ON":"OFF")));
- pCoexDm->bCurLowPenaltyRa = bLowPenaltyRa;
-
- if(!bForceExec)
- {
- if(pCoexDm->bPreLowPenaltyRa == pCoexDm->bCurLowPenaltyRa)
- return;
- }
- halbtc8723a2ant_SetSwPenaltyTxRateAdaptive(pBtCoexist, pCoexDm->bCurLowPenaltyRa);
-
- pCoexDm->bPreLowPenaltyRa = pCoexDm->bCurLowPenaltyRa;
-}
-
-VOID
-halbtc8723a2ant_SetSwFullTimeDacSwing(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bSwDacSwingOn,
- IN u4Byte swDacSwingLvl
- )
-{
- if(bSwDacSwingOn)
- {
- pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x880, 0xff000000, swDacSwingLvl);
- }
- else
- {
- pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x880, 0xff000000, 0xc0);
- }
-}
-
-
-VOID
-halbtc8723a2ant_DacSwing(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bForceExec,
- IN BOOLEAN bDacSwingOn,
- IN u4Byte dacSwingLvl
- )
-{
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn DacSwing=%s, dacSwingLvl=0x%x\n",
- (bForceExec? "force to":""), ((bDacSwingOn)? "ON":"OFF"), dacSwingLvl));
- pCoexDm->bCurDacSwingOn = bDacSwingOn;
- pCoexDm->curDacSwingLvl = dacSwingLvl;
-
- if(!bForceExec)
- {
- if( (pCoexDm->bPreDacSwingOn == pCoexDm->bCurDacSwingOn) &&
- (pCoexDm->preDacSwingLvl == pCoexDm->curDacSwingLvl) )
- return;
- }
- delay_ms(30);
- halbtc8723a2ant_SetSwFullTimeDacSwing(pBtCoexist, bDacSwingOn, dacSwingLvl);
-
- pCoexDm->bPreDacSwingOn = pCoexDm->bCurDacSwingOn;
- pCoexDm->preDacSwingLvl = pCoexDm->curDacSwingLvl;
-}
-
-VOID
-halbtc8723a2ant_SetAdcBackOff(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bAdcBackOff
- )
-{
- if(bAdcBackOff)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB BackOff Level On!\n"));
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc04,0x3a07611);
- }
- else
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB BackOff Level Off!\n"));
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc04,0x3a05611);
- }
-}
-
-VOID
-halbtc8723a2ant_AdcBackOff(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bForceExec,
- IN BOOLEAN bAdcBackOff
- )
-{
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn AdcBackOff = %s\n",
- (bForceExec? "force to":""), ((bAdcBackOff)? "ON":"OFF")));
- pCoexDm->bCurAdcBackOff = bAdcBackOff;
-
- if(!bForceExec)
- {
- if(pCoexDm->bPreAdcBackOff == pCoexDm->bCurAdcBackOff)
- return;
- }
- halbtc8723a2ant_SetAdcBackOff(pBtCoexist, pCoexDm->bCurAdcBackOff);
-
- pCoexDm->bPreAdcBackOff = pCoexDm->bCurAdcBackOff;
-}
-
-VOID
-halbtc8723a2ant_SetAgcTable(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bAgcTableEn
- )
-{
- u1Byte rssiAdjustVal=0;
-
- if(bAgcTableEn)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table On!\n"));
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x4e1c0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x4d1d0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x4c1e0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x4b1f0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x4a200001);
-
- pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0xdc000);
- pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0x90000);
- pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0x51000);
- pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0x12000);
- pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1a, 0xfffff, 0x00355);
-
- rssiAdjustVal = 6;
- }
- else
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table Off!\n"));
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x641c0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x631d0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x621e0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x611f0001);
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x60200001);
-
- pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0x32000);
- pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0x71000);
- pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0xb0000);
- pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0xfc000);
- pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1a, 0xfffff, 0x30355);
- }
-
- // set rssiAdjustVal for wifi module.
- pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON, &rssiAdjustVal);
-}
-
-
-VOID
-halbtc8723a2ant_AgcTable(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bForceExec,
- IN BOOLEAN bAgcTableEn
- )
-{
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s %s Agc Table\n",
- (bForceExec? "force to":""), ((bAgcTableEn)? "Enable":"Disable")));
- pCoexDm->bCurAgcTableEn = bAgcTableEn;
-
- if(!bForceExec)
- {
- if(pCoexDm->bPreAgcTableEn == pCoexDm->bCurAgcTableEn)
- return;
- }
- halbtc8723a2ant_SetAgcTable(pBtCoexist, bAgcTableEn);
-
- pCoexDm->bPreAgcTableEn = pCoexDm->bCurAgcTableEn;
-}
-
-VOID
-halbtc8723a2ant_SetCoexTable(
- IN PBTC_COEXIST pBtCoexist,
- IN u4Byte val0x6c0,
- IN u4Byte val0x6c8,
- IN u1Byte val0x6cc
- )
-{
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c0=0x%x\n", val0x6c0));
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c0, val0x6c0);
-
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c8=0x%x\n", val0x6c8));
- pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c8, val0x6c8);
-
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6cc=0x%x\n", val0x6cc));
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cc, val0x6cc);
-}
-
-VOID
-halbtc8723a2ant_CoexTable(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bForceExec,
- IN u4Byte val0x6c0,
- IN u4Byte val0x6c8,
- IN u1Byte val0x6cc
- )
-{
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s write Coex Table 0x6c0=0x%x, 0x6c8=0x%x, 0x6cc=0x%x\n",
- (bForceExec? "force to":""), val0x6c0, val0x6c8, val0x6cc));
- pCoexDm->curVal0x6c0 = val0x6c0;
- pCoexDm->curVal0x6c8 = val0x6c8;
- pCoexDm->curVal0x6cc = val0x6cc;
-
- if(!bForceExec)
- {
- if( (pCoexDm->preVal0x6c0 == pCoexDm->curVal0x6c0) &&
- (pCoexDm->preVal0x6c8 == pCoexDm->curVal0x6c8) &&
- (pCoexDm->preVal0x6cc == pCoexDm->curVal0x6cc) )
- return;
- }
- halbtc8723a2ant_SetCoexTable(pBtCoexist, val0x6c0, val0x6c8, val0x6cc);
-
- pCoexDm->preVal0x6c0 = pCoexDm->curVal0x6c0;
- pCoexDm->preVal0x6c8 = pCoexDm->curVal0x6c8;
- pCoexDm->preVal0x6cc = pCoexDm->curVal0x6cc;
-}
-
-VOID
-halbtc8723a2ant_SetFwIgnoreWlanAct(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bEnable
- )
-{
- u1Byte H2C_Parameter[1] ={0};
-
- if(bEnable)
- {
- H2C_Parameter[0] |= BIT0; // function enable
- }
-
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set FW for BT Ignore Wlan_Act, FW write 0x25=0x%x\n",
- H2C_Parameter[0]));
-
- pBtCoexist->fBtcFillH2c(pBtCoexist, 0x25, 1, H2C_Parameter);
-}
-
-VOID
-halbtc8723a2ant_IgnoreWlanAct(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bForceExec,
- IN BOOLEAN bEnable
- )
-{
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Ignore WlanAct %s\n",
- (bForceExec? "force to":""), (bEnable? "ON":"OFF")));
- pCoexDm->bCurIgnoreWlanAct = bEnable;
-
- if(!bForceExec)
- {
- if(pCoexDm->bPreIgnoreWlanAct == pCoexDm->bCurIgnoreWlanAct)
- return;
- }
- halbtc8723a2ant_SetFwIgnoreWlanAct(pBtCoexist, bEnable);
-
- pCoexDm->bPreIgnoreWlanAct = pCoexDm->bCurIgnoreWlanAct;
-}
-
-VOID
-halbtc8723a2ant_SetFwPstdma(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte byte1,
- IN u1Byte byte2,
- IN u1Byte byte3,
- IN u1Byte byte4,
- IN u1Byte byte5
- )
-{
- u1Byte H2C_Parameter[5] ={0};
-
- H2C_Parameter[0] = byte1;
- H2C_Parameter[1] = byte2;
- H2C_Parameter[2] = byte3;
- H2C_Parameter[3] = byte4;
- H2C_Parameter[4] = byte5;
-
- pCoexDm->psTdmaPara[0] = byte1;
- pCoexDm->psTdmaPara[1] = byte2;
- pCoexDm->psTdmaPara[2] = byte3;
- pCoexDm->psTdmaPara[3] = byte4;
- pCoexDm->psTdmaPara[4] = byte5;
-
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], FW write 0x3a(5bytes)=0x%x%08x\n",
- H2C_Parameter[0],
- H2C_Parameter[1]<<24|H2C_Parameter[2]<<16|H2C_Parameter[3]<<8|H2C_Parameter[4]));
-
- pBtCoexist->fBtcFillH2c(pBtCoexist, 0x3a, 5, H2C_Parameter);
-}
-
-VOID
-halbtc8723a2ant_PsTdma(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bForceExec,
- IN BOOLEAN bTurnOn,
- IN u1Byte type
- )
-{
- u4Byte btTxRxCnt=0;
-
- btTxRxCnt = pCoexSta->highPriorityTx+pCoexSta->highPriorityRx+
- pCoexSta->lowPriorityTx+pCoexSta->lowPriorityRx;
-
- if(btTxRxCnt > 3000)
- {
- pCoexDm->bCurPsTdmaOn = TRUE;
- pCoexDm->curPsTdma = 8;
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], turn ON PS TDMA, type=%d for BT tx/rx counters=%d(>3000)\n",
- pCoexDm->curPsTdma, btTxRxCnt));
- }
- else
- {
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn %s PS TDMA, type=%d\n",
- (bForceExec? "force to":""), (bTurnOn? "ON":"OFF"), type));
- pCoexDm->bCurPsTdmaOn = bTurnOn;
- pCoexDm->curPsTdma = type;
- }
-
- if(!bForceExec)
- {
- if( (pCoexDm->bPrePsTdmaOn == pCoexDm->bCurPsTdmaOn) &&
- (pCoexDm->prePsTdma == pCoexDm->curPsTdma) )
- return;
- }
- if(pCoexDm->bCurPsTdmaOn)
- {
- switch(pCoexDm->curPsTdma)
- {
- case 1:
- default:
- halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x98);
- break;
- case 2:
- halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x12, 0x12, 0xe1, 0x98);
- break;
- case 3:
- halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0xa, 0xa, 0xe1, 0x98);
- break;
- case 4:
- halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xa3, 0x5, 0x5, 0xe1, 0x80);
- break;
- case 5:
- halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0x60, 0x98);
- break;
- case 6:
- halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x12, 0x12, 0x60, 0x98);
- break;
- case 7:
- halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0xa, 0xa, 0x60, 0x98);
- break;
- case 8:
- halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xa3, 0x5, 0x5, 0x60, 0x80);
- break;
- case 9:
- halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x98);
- break;
- case 10:
- halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x12, 0x12, 0xe1, 0x98);
- break;
- case 11:
- halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0xa, 0xa, 0xe1, 0x98);
- break;
- case 12:
- halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x5, 0x5, 0xe1, 0x98);
- break;
- case 13:
- halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0x60, 0x98);
- break;
- case 14:
- halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x12, 0x12, 0x60, 0x98);
- break;
- case 15:
- halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0xa, 0xa, 0x60, 0x98);
- break;
- case 16:
- halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x5, 0x5, 0x60, 0x98);
- break;
- case 17:
- halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xa3, 0x2f, 0x2f, 0x60, 0x80);
- break;
- case 18:
- halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x5, 0x5, 0xe1, 0x98);
- break;
- case 19:
- halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x25, 0x25, 0xe1, 0x98);
- break;
- case 20:
- halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x25, 0x25, 0x60, 0x98);
- break;
- }
- }
- else
- {
- // disable PS tdma
- switch(pCoexDm->curPsTdma)
- {
- case 0:
- halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x8, 0x0);
- break;
- case 1:
- halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x0, 0x0);
- break;
- default:
- halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x8, 0x0);
- break;
- }
- }
-
- // update pre state
- pCoexDm->bPrePsTdmaOn = pCoexDm->bCurPsTdmaOn;
- pCoexDm->prePsTdma = pCoexDm->curPsTdma;
-}
-
-
-VOID
-halbtc8723a2ant_CoexAllOff(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- // fw all off
- halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0);
- halbtc8723a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0x20);
- halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE);
-
- // sw all off
- halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_RfShrink(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
-
- // hw all off
- halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3);
-}
-
-VOID
-halbtc8723a2ant_InitCoexDm(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- // force to reset coex mechanism
- halbtc8723a2ant_CoexTable(pBtCoexist, FORCE_EXEC, 0x55555555, 0xffff, 0x3);
- halbtc8723a2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 0);
- halbtc8723a2ant_FwDacSwingLvl(pBtCoexist, FORCE_EXEC, 0x20);
- halbtc8723a2ant_DecBtPwr(pBtCoexist, FORCE_EXEC, FALSE);
- halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, FALSE);
-
- halbtc8723a2ant_AgcTable(pBtCoexist, FORCE_EXEC, FALSE);
- halbtc8723a2ant_AdcBackOff(pBtCoexist, FORCE_EXEC, FALSE);
- halbtc8723a2ant_LowPenaltyRa(pBtCoexist, FORCE_EXEC, FALSE);
- halbtc8723a2ant_RfShrink(pBtCoexist, FORCE_EXEC, FALSE);
- halbtc8723a2ant_DacSwing(pBtCoexist, FORCE_EXEC, FALSE, 0xc0);
-}
-
-VOID
-halbtc8723a2ant_BtInquiryPage(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- BOOLEAN bLowPwrDisable=TRUE;
-
- pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable);
-
- halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3);
- halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8);
-}
-
-VOID
-halbtc8723a2ant_BtEnableAction(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- BOOLEAN bWifiConnected=FALSE;
-
- // Here we need to resend some wifi info to BT
- // because bt is reset and loss of the info.
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected);
- if(bWifiConnected)
- {
- halbtc8723a2ant_IndicateWifiChnlBwInfo(pBtCoexist, BTC_MEDIA_CONNECT);
- }
- else
- {
- halbtc8723a2ant_IndicateWifiChnlBwInfo(pBtCoexist, BTC_MEDIA_DISCONNECT);
- }
-
- halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, FALSE);
-}
-
-VOID
-halbtc8723a2ant_MonitorBtCtr(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- u4Byte regHPTxRx, regLPTxRx, u4Tmp;
- u4Byte regHPTx=0, regHPRx=0, regLPTx=0, regLPRx=0;
- u1Byte u1Tmp;
-
- regHPTxRx = 0x770;
- regLPTxRx = 0x774;
-
- u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, regHPTxRx);
- regHPTx = u4Tmp & bMaskLWord;
- regHPRx = (u4Tmp & bMaskHWord)>>16;
-
- u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, regLPTxRx);
- regLPTx = u4Tmp & bMaskLWord;
- regLPRx = (u4Tmp & bMaskHWord)>>16;
-
- pCoexSta->highPriorityTx = regHPTx;
- pCoexSta->highPriorityRx = regHPRx;
- pCoexSta->lowPriorityTx = regLPTx;
- pCoexSta->lowPriorityRx = regLPRx;
-
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], High Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n",
- regHPTxRx, regHPTx, regHPTx, regHPRx, regHPRx));
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Low Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n",
- regLPTxRx, regLPTx, regLPTx, regLPRx, regLPRx));
-
- // reset counter
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0xc);
-}
-
-VOID
-halbtc8723a2ant_MonitorBtEnableDisable(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- static BOOLEAN bPreBtDisabled=FALSE;
- static u4Byte btDisableCnt=0;
- BOOLEAN bBtActive=TRUE, bBtDisabled=FALSE;
-
- // This function check if bt is disabled
-
- if( pCoexSta->highPriorityTx == 0 &&
- pCoexSta->highPriorityRx == 0 &&
- pCoexSta->lowPriorityTx == 0 &&
- pCoexSta->lowPriorityRx == 0)
- {
- bBtActive = FALSE;
- }
- if( pCoexSta->highPriorityTx == 0xffff &&
- pCoexSta->highPriorityRx == 0xffff &&
- pCoexSta->lowPriorityTx == 0xffff &&
- pCoexSta->lowPriorityRx == 0xffff)
- {
- bBtActive = FALSE;
- }
- if(bBtActive)
- {
- btDisableCnt = 0;
- bBtDisabled = FALSE;
- pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled);
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is enabled !!\n"));
- }
- else
- {
- btDisableCnt++;
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], bt all counters=0, %d times!!\n",
- btDisableCnt));
- if(btDisableCnt >= 2)
- {
- bBtDisabled = TRUE;
- pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled);
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is disabled !!\n"));
- }
- }
- if(bPreBtDisabled != bBtDisabled)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is from %s to %s!!\n",
- (bPreBtDisabled ? "disabled":"enabled"),
- (bBtDisabled ? "disabled":"enabled")));
- bPreBtDisabled = bBtDisabled;
- if(!bBtDisabled)
- {
- halbtc8723a2ant_BtEnableAction(pBtCoexist);
- }
- }
-}
-
-BOOLEAN
-halbtc8723a2ant_IsCommonAction(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo;
- BOOLEAN bCommon=FALSE, bWifiConnected=FALSE;
- BOOLEAN bLowPwrDisable=FALSE;
-
- if(!pStackInfo->bBtLinkExist)
- {
- bLowPwrDisable = FALSE;
- pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable);
- }
- else
- {
- bLowPwrDisable = TRUE;
- pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable);
- }
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected);
-
- if(halbtc8723a2ant_IsWifiIdle(pBtCoexist) &&
- BT_8723A_2ANT_BT_STATUS_IDLE == pCoexDm->btStatus)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi idle + Bt idle!!\n"));
-
- halbtc8723a2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_RfShrink(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3);
-
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0);
- halbtc8723a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0x20);
- halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE);
-
- halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
-
- bCommon = TRUE;
- }
- else if(!halbtc8723a2ant_IsWifiIdle(pBtCoexist) &&
- (BT_8723A_2ANT_BT_STATUS_IDLE == pCoexDm->btStatus) )
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi non-idle + BT idle!!\n"));
-
- halbtc8723a2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8723a2ant_RfShrink(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3);
-
- halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0);
- halbtc8723a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0x20);
- halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE);
-
- halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
-
- bCommon = TRUE;
- }
- else if(halbtc8723a2ant_IsWifiIdle(pBtCoexist) &&
- (BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus) )
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi idle + Bt connected idle!!\n"));
-
- halbtc8723a2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8723a2ant_RfShrink(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3);
-
- halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0);
- halbtc8723a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0x20);
- halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE);
-
- halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
-
- bCommon = TRUE;
- }
- else if(!halbtc8723a2ant_IsWifiIdle(pBtCoexist) &&
- (BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus) )
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi non-idle + Bt connected idle!!\n"));
-
- halbtc8723a2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8723a2ant_RfShrink(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3);
-
- halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0);
- halbtc8723a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0x20);
- halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE);
-
- halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
-
- bCommon = TRUE;
- }
- else if(halbtc8723a2ant_IsWifiIdle(pBtCoexist) &&
- (BT_8723A_2ANT_BT_STATUS_NON_IDLE == pCoexDm->btStatus) )
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi idle + BT non-idle!!\n"));
-
- halbtc8723a2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8723a2ant_RfShrink(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3);
-
- halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0);
- halbtc8723a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0x20);
- halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE);
-
- halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
-
- bCommon = TRUE;
- }
- else if(halbtc8723a2ant_IsWifiConnectedIdle(pBtCoexist) &&
- (BT_8723A_2ANT_BT_STATUS_NON_IDLE == pCoexDm->btStatus) )
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi connected-idle + BT non-idle!!\n"));
-
- halbtc8723a2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8723a2ant_RfShrink(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3);
-
- halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3);
- halbtc8723a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0x20);
- halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE);
-
- halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
-
- bCommon = TRUE;
- }
- else
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi non-idle + BT non-idle!!\n"));
- halbtc8723a2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8723a2ant_RfShrink(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0x20);
-
- bCommon = FALSE;
- }
-
- return bCommon;
-}
-VOID
-halbtc8723a2ant_TdmaDurationAdjust(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bScoHid,
- IN BOOLEAN bTxPause,
- IN u1Byte maxInterval
- )
-{
- static s4Byte up,dn,m,n,WaitCount;
- s4Byte result; //0: no change, +1: increase WiFi duration, -1: decrease WiFi duration
- u1Byte retryCount=0;
-
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TdmaDurationAdjust()\n"));
-
- if(pCoexDm->bResetTdmaAdjust)
- {
- pCoexDm->bResetTdmaAdjust = FALSE;
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], first run TdmaDurationAdjust()!!\n"));
- {
- if(bScoHid)
- {
- if(bTxPause)
- {
- if(maxInterval == 1)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13);
- pCoexDm->psTdmaDuAdjType = 13;
- }
- else if(maxInterval == 2)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14);
- pCoexDm->psTdmaDuAdjType = 14;
- }
- else if(maxInterval == 3)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15);
- pCoexDm->psTdmaDuAdjType = 15;
- }
- else
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15);
- pCoexDm->psTdmaDuAdjType = 15;
- }
- }
- else
- {
- if(maxInterval == 1)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9);
- pCoexDm->psTdmaDuAdjType = 9;
- }
- else if(maxInterval == 2)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10);
- pCoexDm->psTdmaDuAdjType = 10;
- }
- else if(maxInterval == 3)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11);
- pCoexDm->psTdmaDuAdjType = 11;
- }
- else
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11);
- pCoexDm->psTdmaDuAdjType = 11;
- }
- }
- }
- else
- {
- if(bTxPause)
- {
- if(maxInterval == 1)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5);
- pCoexDm->psTdmaDuAdjType = 5;
- }
- else if(maxInterval == 2)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6);
- pCoexDm->psTdmaDuAdjType = 6;
- }
- else if(maxInterval == 3)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7);
- pCoexDm->psTdmaDuAdjType = 7;
- }
- else
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7);
- pCoexDm->psTdmaDuAdjType = 7;
- }
- }
- else
- {
- if(maxInterval == 1)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1);
- pCoexDm->psTdmaDuAdjType = 1;
- }
- else if(maxInterval == 2)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2);
- pCoexDm->psTdmaDuAdjType = 2;
- }
- else if(maxInterval == 3)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3);
- pCoexDm->psTdmaDuAdjType = 3;
- }
- else
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3);
- pCoexDm->psTdmaDuAdjType = 3;
- }
- }
- }
- }
- //============
- up = 0;
- dn = 0;
- m = 1;
- n= 3;
- result = 0;
- WaitCount = 0;
- }
- else
- {
- //accquire the BT TRx retry count from BT_Info byte2
- retryCount = pCoexSta->btRetryCnt;
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], retryCount = %d\n", retryCount));
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], up=%d, dn=%d, m=%d, n=%d, WaitCount=%d\n",
- up, dn, m, n, WaitCount));
- result = 0;
- WaitCount++;
-
- if(retryCount == 0) // no retry in the last 2-second duration
- {
- up++;
- dn--;
-
- if (dn <= 0)
- dn = 0;
-
- if(up >= n) // if ³sÄò n Ó2¬í retry count¬°0, «h½Õ¼eWiFi duration
- {
- WaitCount = 0;
- n = 3;
- up = 0;
- dn = 0;
- result = 1;
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Increase wifi duration!!\n"));
- }
- }
- else if (retryCount <= 3) // <=3 retry in the last 2-second duration
- {
- up--;
- dn++;
-
- if (up <= 0)
- up = 0;
-
- if (dn == 2) // if ³sÄò 2 Ó2¬í retry count< 3, «h½Õ¯¶WiFi duration
- {
- if (WaitCount <= 2)
- m++; // ÁקK¤@ª½¦b¨âÓlevel¤¤¨Ó¦^
- else
- m = 1;
-
- if ( m >= 20) //m ³Ì¤jÈ = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration.
- m = 20;
-
- n = 3*m;
- up = 0;
- dn = 0;
- WaitCount = 0;
- result = -1;
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Decrease wifi duration for retryCounter<3!!\n"));
- }
- }
- else //retry count > 3, ¥un1¦¸ retry count > 3, «h½Õ¯¶WiFi duration
- {
- if (WaitCount == 1)
- m++; // ÁקK¤@ª½¦b¨âÓlevel¤¤¨Ó¦^
- else
- m = 1;
-
- if ( m >= 20) //m ³Ì¤jÈ = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration.
- m = 20;
-
- n = 3*m;
- up = 0;
- dn = 0;
- WaitCount = 0;
- result = -1;
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Decrease wifi duration for retryCounter>3!!\n"));
- }
-
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], max Interval = %d\n", maxInterval));
- if(maxInterval == 1)
- {
- if(bTxPause)
- {
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 1\n"));
-
- if(pCoexDm->curPsTdma == 1)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5);
- pCoexDm->psTdmaDuAdjType = 5;
- }
- else if(pCoexDm->curPsTdma == 2)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6);
- pCoexDm->psTdmaDuAdjType = 6;
- }
- else if(pCoexDm->curPsTdma == 3)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7);
- pCoexDm->psTdmaDuAdjType = 7;
- }
- else if(pCoexDm->curPsTdma == 4)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8);
- pCoexDm->psTdmaDuAdjType = 8;
- }
- if(pCoexDm->curPsTdma == 9)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13);
- pCoexDm->psTdmaDuAdjType = 13;
- }
- else if(pCoexDm->curPsTdma == 10)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14);
- pCoexDm->psTdmaDuAdjType = 14;
- }
- else if(pCoexDm->curPsTdma == 11)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15);
- pCoexDm->psTdmaDuAdjType = 15;
- }
- else if(pCoexDm->curPsTdma == 12)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16);
- pCoexDm->psTdmaDuAdjType = 16;
- }
-
- if(result == -1)
- {
- if(pCoexDm->curPsTdma == 5)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6);
- pCoexDm->psTdmaDuAdjType = 6;
- }
- else if(pCoexDm->curPsTdma == 6)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7);
- pCoexDm->psTdmaDuAdjType = 7;
- }
- else if(pCoexDm->curPsTdma == 7)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8);
- pCoexDm->psTdmaDuAdjType = 8;
- }
- else if(pCoexDm->curPsTdma == 13)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14);
- pCoexDm->psTdmaDuAdjType = 14;
- }
- else if(pCoexDm->curPsTdma == 14)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15);
- pCoexDm->psTdmaDuAdjType = 15;
- }
- else if(pCoexDm->curPsTdma == 15)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16);
- pCoexDm->psTdmaDuAdjType = 16;
- }
- }
- else if (result == 1)
- {
- if(pCoexDm->curPsTdma == 8)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7);
- pCoexDm->psTdmaDuAdjType = 7;
- }
- else if(pCoexDm->curPsTdma == 7)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6);
- pCoexDm->psTdmaDuAdjType = 6;
- }
- else if(pCoexDm->curPsTdma == 6)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5);
- pCoexDm->psTdmaDuAdjType = 5;
- }
- else if(pCoexDm->curPsTdma == 16)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15);
- pCoexDm->psTdmaDuAdjType = 15;
- }
- else if(pCoexDm->curPsTdma == 15)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14);
- pCoexDm->psTdmaDuAdjType = 14;
- }
- else if(pCoexDm->curPsTdma == 14)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13);
- pCoexDm->psTdmaDuAdjType = 13;
- }
- }
- }
- else
- {
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 0\n"));
- if(pCoexDm->curPsTdma == 5)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1);
- pCoexDm->psTdmaDuAdjType = 1;
- }
- else if(pCoexDm->curPsTdma == 6)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2);
- pCoexDm->psTdmaDuAdjType = 2;
- }
- else if(pCoexDm->curPsTdma == 7)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3);
- pCoexDm->psTdmaDuAdjType = 3;
- }
- else if(pCoexDm->curPsTdma == 8)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4);
- pCoexDm->psTdmaDuAdjType = 4;
- }
- if(pCoexDm->curPsTdma == 13)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9);
- pCoexDm->psTdmaDuAdjType = 9;
- }
- else if(pCoexDm->curPsTdma == 14)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10);
- pCoexDm->psTdmaDuAdjType = 10;
- }
- else if(pCoexDm->curPsTdma == 15)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11);
- pCoexDm->psTdmaDuAdjType = 11;
- }
- else if(pCoexDm->curPsTdma == 16)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12);
- pCoexDm->psTdmaDuAdjType = 12;
- }
-
- if(result == -1)
- {
- if(pCoexDm->curPsTdma == 1)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2);
- pCoexDm->psTdmaDuAdjType = 2;
- }
- else if(pCoexDm->curPsTdma == 2)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3);
- pCoexDm->psTdmaDuAdjType = 3;
- }
- else if(pCoexDm->curPsTdma == 3)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4);
- pCoexDm->psTdmaDuAdjType = 4;
- }
- else if(pCoexDm->curPsTdma == 9)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10);
- pCoexDm->psTdmaDuAdjType = 10;
- }
- else if(pCoexDm->curPsTdma == 10)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11);
- pCoexDm->psTdmaDuAdjType = 11;
- }
- else if(pCoexDm->curPsTdma == 11)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12);
- pCoexDm->psTdmaDuAdjType = 12;
- }
- }
- else if (result == 1)
- {
- if(pCoexDm->curPsTdma == 4)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3);
- pCoexDm->psTdmaDuAdjType = 3;
- }
- else if(pCoexDm->curPsTdma == 3)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2);
- pCoexDm->psTdmaDuAdjType = 2;
- }
- else if(pCoexDm->curPsTdma == 2)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1);
- pCoexDm->psTdmaDuAdjType = 1;
- }
- else if(pCoexDm->curPsTdma == 12)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11);
- pCoexDm->psTdmaDuAdjType = 11;
- }
- else if(pCoexDm->curPsTdma == 11)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10);
- pCoexDm->psTdmaDuAdjType = 10;
- }
- else if(pCoexDm->curPsTdma == 10)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9);
- pCoexDm->psTdmaDuAdjType = 9;
- }
- }
- }
- }
- else if(maxInterval == 2)
- {
- if(bTxPause)
- {
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 1\n"));
- if(pCoexDm->curPsTdma == 1)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6);
- pCoexDm->psTdmaDuAdjType = 6;
- }
- else if(pCoexDm->curPsTdma == 2)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6);
- pCoexDm->psTdmaDuAdjType = 6;
- }
- else if(pCoexDm->curPsTdma == 3)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7);
- pCoexDm->psTdmaDuAdjType = 7;
- }
- else if(pCoexDm->curPsTdma == 4)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8);
- pCoexDm->psTdmaDuAdjType = 8;
- }
- if(pCoexDm->curPsTdma == 9)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14);
- pCoexDm->psTdmaDuAdjType = 14;
- }
- else if(pCoexDm->curPsTdma == 10)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14);
- pCoexDm->psTdmaDuAdjType = 14;
- }
- else if(pCoexDm->curPsTdma == 11)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15);
- pCoexDm->psTdmaDuAdjType = 15;
- }
- else if(pCoexDm->curPsTdma == 12)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16);
- pCoexDm->psTdmaDuAdjType = 16;
- }
- if(result == -1)
- {
- if(pCoexDm->curPsTdma == 5)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6);
- pCoexDm->psTdmaDuAdjType = 6;
- }
- else if(pCoexDm->curPsTdma == 6)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7);
- pCoexDm->psTdmaDuAdjType = 7;
- }
- else if(pCoexDm->curPsTdma == 7)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8);
- pCoexDm->psTdmaDuAdjType = 8;
- }
- else if(pCoexDm->curPsTdma == 13)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14);
- pCoexDm->psTdmaDuAdjType = 14;
- }
- else if(pCoexDm->curPsTdma == 14)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15);
- pCoexDm->psTdmaDuAdjType = 15;
- }
- else if(pCoexDm->curPsTdma == 15)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16);
- pCoexDm->psTdmaDuAdjType = 16;
- }
- }
- else if (result == 1)
- {
- if(pCoexDm->curPsTdma == 8)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7);
- pCoexDm->psTdmaDuAdjType = 7;
- }
- else if(pCoexDm->curPsTdma == 7)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6);
- pCoexDm->psTdmaDuAdjType = 6;
- }
- else if(pCoexDm->curPsTdma == 6)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6);
- pCoexDm->psTdmaDuAdjType = 6;
- }
- else if(pCoexDm->curPsTdma == 16)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15);
- pCoexDm->psTdmaDuAdjType = 15;
- }
- else if(pCoexDm->curPsTdma == 15)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14);
- pCoexDm->psTdmaDuAdjType = 14;
- }
- else if(pCoexDm->curPsTdma == 14)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14);
- pCoexDm->psTdmaDuAdjType = 14;
- }
- }
- }
- else
- {
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 0\n"));
- if(pCoexDm->curPsTdma == 5)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2);
- pCoexDm->psTdmaDuAdjType = 2;
- }
- else if(pCoexDm->curPsTdma == 6)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2);
- pCoexDm->psTdmaDuAdjType = 2;
- }
- else if(pCoexDm->curPsTdma == 7)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3);
- pCoexDm->psTdmaDuAdjType = 3;
- }
- else if(pCoexDm->curPsTdma == 8)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4);
- pCoexDm->psTdmaDuAdjType = 4;
- }
- if(pCoexDm->curPsTdma == 13)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10);
- pCoexDm->psTdmaDuAdjType = 10;
- }
- else if(pCoexDm->curPsTdma == 14)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10);
- pCoexDm->psTdmaDuAdjType = 10;
- }
- else if(pCoexDm->curPsTdma == 15)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11);
- pCoexDm->psTdmaDuAdjType = 11;
- }
- else if(pCoexDm->curPsTdma == 16)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12);
- pCoexDm->psTdmaDuAdjType = 12;
- }
- if(result == -1)
- {
- if(pCoexDm->curPsTdma == 1)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2);
- pCoexDm->psTdmaDuAdjType = 2;
- }
- else if(pCoexDm->curPsTdma == 2)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3);
- pCoexDm->psTdmaDuAdjType = 3;
- }
- else if(pCoexDm->curPsTdma == 3)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4);
- pCoexDm->psTdmaDuAdjType = 4;
- }
- else if(pCoexDm->curPsTdma == 9)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10);
- pCoexDm->psTdmaDuAdjType = 10;
- }
- else if(pCoexDm->curPsTdma == 10)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11);
- pCoexDm->psTdmaDuAdjType = 11;
- }
- else if(pCoexDm->curPsTdma == 11)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12);
- pCoexDm->psTdmaDuAdjType = 12;
- }
- }
- else if (result == 1)
- {
- if(pCoexDm->curPsTdma == 4)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3);
- pCoexDm->psTdmaDuAdjType = 3;
- }
- else if(pCoexDm->curPsTdma == 3)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2);
- pCoexDm->psTdmaDuAdjType = 2;
- }
- else if(pCoexDm->curPsTdma == 2)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2);
- pCoexDm->psTdmaDuAdjType = 2;
- }
- else if(pCoexDm->curPsTdma == 12)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11);
- pCoexDm->psTdmaDuAdjType = 11;
- }
- else if(pCoexDm->curPsTdma == 11)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10);
- pCoexDm->psTdmaDuAdjType = 10;
- }
- else if(pCoexDm->curPsTdma == 10)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10);
- pCoexDm->psTdmaDuAdjType = 10;
- }
- }
- }
- }
- else if(maxInterval == 3)
- {
- if(bTxPause)
- {
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 1\n"));
- if(pCoexDm->curPsTdma == 1)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7);
- pCoexDm->psTdmaDuAdjType = 7;
- }
- else if(pCoexDm->curPsTdma == 2)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7);
- pCoexDm->psTdmaDuAdjType = 7;
- }
- else if(pCoexDm->curPsTdma == 3)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7);
- pCoexDm->psTdmaDuAdjType = 7;
- }
- else if(pCoexDm->curPsTdma == 4)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8);
- pCoexDm->psTdmaDuAdjType = 8;
- }
- if(pCoexDm->curPsTdma == 9)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15);
- pCoexDm->psTdmaDuAdjType = 15;
- }
- else if(pCoexDm->curPsTdma == 10)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15);
- pCoexDm->psTdmaDuAdjType = 15;
- }
- else if(pCoexDm->curPsTdma == 11)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15);
- pCoexDm->psTdmaDuAdjType = 15;
- }
- else if(pCoexDm->curPsTdma == 12)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16);
- pCoexDm->psTdmaDuAdjType = 16;
- }
- if(result == -1)
- {
- if(pCoexDm->curPsTdma == 5)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7);
- pCoexDm->psTdmaDuAdjType = 7;
- }
- else if(pCoexDm->curPsTdma == 6)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7);
- pCoexDm->psTdmaDuAdjType = 7;
- }
- else if(pCoexDm->curPsTdma == 7)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8);
- pCoexDm->psTdmaDuAdjType = 8;
- }
- else if(pCoexDm->curPsTdma == 13)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15);
- pCoexDm->psTdmaDuAdjType = 15;
- }
- else if(pCoexDm->curPsTdma == 14)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15);
- pCoexDm->psTdmaDuAdjType = 15;
- }
- else if(pCoexDm->curPsTdma == 15)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16);
- pCoexDm->psTdmaDuAdjType = 16;
- }
- }
- else if (result == 1)
- {
- if(pCoexDm->curPsTdma == 8)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7);
- pCoexDm->psTdmaDuAdjType = 7;
- }
- else if(pCoexDm->curPsTdma == 7)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7);
- pCoexDm->psTdmaDuAdjType = 7;
- }
- else if(pCoexDm->curPsTdma == 6)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7);
- pCoexDm->psTdmaDuAdjType = 7;
- }
- else if(pCoexDm->curPsTdma == 16)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15);
- pCoexDm->psTdmaDuAdjType = 15;
- }
- else if(pCoexDm->curPsTdma == 15)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15);
- pCoexDm->psTdmaDuAdjType = 15;
- }
- else if(pCoexDm->curPsTdma == 14)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15);
- pCoexDm->psTdmaDuAdjType = 15;
- }
- }
- }
- else
- {
- RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 0\n"));
- if(pCoexDm->curPsTdma == 5)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3);
- pCoexDm->psTdmaDuAdjType = 3;
- }
- else if(pCoexDm->curPsTdma == 6)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3);
- pCoexDm->psTdmaDuAdjType = 3;
- }
- else if(pCoexDm->curPsTdma == 7)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3);
- pCoexDm->psTdmaDuAdjType = 3;
- }
- else if(pCoexDm->curPsTdma == 8)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4);
- pCoexDm->psTdmaDuAdjType = 4;
- }
- if(pCoexDm->curPsTdma == 13)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11);
- pCoexDm->psTdmaDuAdjType = 11;
- }
- else if(pCoexDm->curPsTdma == 14)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11);
- pCoexDm->psTdmaDuAdjType = 11;
- }
- else if(pCoexDm->curPsTdma == 15)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11);
- pCoexDm->psTdmaDuAdjType = 11;
- }
- else if(pCoexDm->curPsTdma == 16)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12);
- pCoexDm->psTdmaDuAdjType = 12;
- }
- if(result == -1)
- {
- if(pCoexDm->curPsTdma == 1)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3);
- pCoexDm->psTdmaDuAdjType = 3;
- }
- else if(pCoexDm->curPsTdma == 2)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3);
- pCoexDm->psTdmaDuAdjType = 3;
- }
- else if(pCoexDm->curPsTdma == 3)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4);
- pCoexDm->psTdmaDuAdjType = 4;
- }
- else if(pCoexDm->curPsTdma == 9)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11);
- pCoexDm->psTdmaDuAdjType = 11;
- }
- else if(pCoexDm->curPsTdma == 10)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11);
- pCoexDm->psTdmaDuAdjType = 11;
- }
- else if(pCoexDm->curPsTdma == 11)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12);
- pCoexDm->psTdmaDuAdjType = 12;
- }
- }
- else if (result == 1)
- {
- if(pCoexDm->curPsTdma == 4)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3);
- pCoexDm->psTdmaDuAdjType = 3;
- }
- else if(pCoexDm->curPsTdma == 3)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3);
- pCoexDm->psTdmaDuAdjType = 3;
- }
- else if(pCoexDm->curPsTdma == 2)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3);
- pCoexDm->psTdmaDuAdjType = 3;
- }
- else if(pCoexDm->curPsTdma == 12)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11);
- pCoexDm->psTdmaDuAdjType = 11;
- }
- else if(pCoexDm->curPsTdma == 11)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11);
- pCoexDm->psTdmaDuAdjType = 11;
- }
- else if(pCoexDm->curPsTdma == 10)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11);
- pCoexDm->psTdmaDuAdjType = 11;
- }
- }
- }
- }
- }
-
- // if current PsTdma not match with the recorded one (when scan, dhcp...),
- // then we have to adjust it back to the previous record one.
- if(pCoexDm->curPsTdma != pCoexDm->psTdmaDuAdjType)
- {
- BOOLEAN bScan=FALSE, bLink=FALSE, bRoam=FALSE;
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PsTdma type dismatch!!!, curPsTdma=%d, recordPsTdma=%d\n",
- pCoexDm->curPsTdma, pCoexDm->psTdmaDuAdjType));
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan);
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink);
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam);
-
- if( !bScan && !bLink && !bRoam)
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, pCoexDm->psTdmaDuAdjType);
- }
- else
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n"));
- }
- }
-}
-
-// SCO only or SCO+PAN(HS)
-VOID
-halbtc8723a2ant_ActionSco(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- u1Byte wifiRssiState, wifiRssiState1;
- u4Byte wifiBw;
-
- if(halbtc8723a2ant_NeedToDecBtPwr(pBtCoexist))
- halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE);
- else
- halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3);
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
- if(BTC_WIFI_BW_HT40 == wifiBw)
- {
- wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0);
- // fw mechanism
- if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11);
- }
- else
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15);
- }
-
- // sw mechanism
- halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
- }
- else
- {
- wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 27, 0);
- wifiRssiState1 = halbtc8723a2ant_WifiRssiState(pBtCoexist, 1, 2, 47, 0);
-
- // fw mechanism
- if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11);
- }
- else
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15);
- }
-
- // sw mechanism
- if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
- }
- else
- {
- halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
- }
- }
-}
-
-
-VOID
-halbtc8723a2ant_ActionHid(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- u1Byte wifiRssiState, wifiRssiState1;
- u4Byte wifiBw;
-
- if(halbtc8723a2ant_NeedToDecBtPwr(pBtCoexist))
- halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE);
- else
- halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3);
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
- if(BTC_WIFI_BW_HT40 == wifiBw)
- {
- wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0);
- // fw mechanism
- if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9);
- }
- else
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13);
- }
-
- // sw mechanism
- halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
- }
- else
- {
- wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 27, 0);
- wifiRssiState1 = halbtc8723a2ant_WifiRssiState(pBtCoexist, 1, 2, 47, 0);
-
- // fw mechanism
- if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9);
- }
- else
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13);
- }
-
- // sw mechanism
- if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
- }
- else
- {
- halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
- }
- }
-}
-
-//A2DP only / PAN(EDR) only/ A2DP+PAN(HS)
-VOID
-halbtc8723a2ant_ActionA2dp(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- u1Byte wifiRssiState, wifiRssiState1, btInfoExt;
- u4Byte wifiBw;
-
- btInfoExt = pCoexSta->btInfoExt;
-
- if(halbtc8723a2ant_NeedToDecBtPwr(pBtCoexist))
- halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE);
- else
- halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3);
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
- if(BTC_WIFI_BW_HT40 == wifiBw)
- {
- wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0);
-
- // fw mechanism
- if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
- {
- if(btInfoExt&BIT0) //a2dp rate, 1:basic /0:edr
- {
- halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, FALSE, 3);
- }
- else
- {
- halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, FALSE, 1);
- }
- }
- else
- {
- if(btInfoExt&BIT0) //a2dp rate, 1:basic /0:edr
- {
- halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, TRUE, 3);
- }
- else
- {
- halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, TRUE, 1);
- }
- }
-
- // sw mechanism
- halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
- }
- else
- {
- wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 27, 0);
- wifiRssiState1 = halbtc8723a2ant_WifiRssiState(pBtCoexist, 1, 2, 47, 0);
-
- // fw mechanism
- if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
- {
- if(btInfoExt&BIT0) //a2dp rate, 1:basic /0:edr
- {
- halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, FALSE, 3);
- }
- else
- {
- halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, FALSE, 1);
- }
- }
- else
- {
- if(btInfoExt&BIT0) //a2dp rate, 1:basic /0:edr
- {
- halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, TRUE, 3);
- }
- else
- {
- halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, TRUE, 1);
- }
- }
-
- // sw mechanism
- if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
- }
- else
- {
- halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
- }
- }
-}
-
-VOID
-halbtc8723a2ant_ActionPanEdr(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- u1Byte wifiRssiState, wifiRssiState1, btInfoExt;
- u4Byte wifiBw;
-
- btInfoExt = pCoexSta->btInfoExt;
-
- if(halbtc8723a2ant_NeedToDecBtPwr(pBtCoexist))
- halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE);
- else
- halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3);
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
- if(BTC_WIFI_BW_HT40 == wifiBw)
- {
- wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0);
-
- // fw mechanism
- if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2);
- }
- else
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6);
- }
-
- // sw mechanism
- halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
- }
- else
- {
- wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 27, 0);
- wifiRssiState1 = halbtc8723a2ant_WifiRssiState(pBtCoexist, 1, 2, 47, 0);
-
- // fw mechanism
- if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2);
- }
- else
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6);
- }
-
- // sw mechanism
- if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
- }
- else
- {
- halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
- }
- }
-}
-
-
-//PAN(HS) only
-VOID
-halbtc8723a2ant_ActionPanHs(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- u1Byte wifiRssiState;
- u4Byte wifiBw;
-
- halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3);
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
- if(BTC_WIFI_BW_HT40 == wifiBw)
- {
- wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0);
-
- // fw mechanism
- if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE);
- }
- else
- {
- halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE);
- }
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0);
-
- // sw mechanism
- halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
- }
- else
- {
- wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0);
-
- // fw mechanism
- if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0);
- }
- else
- {
- halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0);
- }
-
- // sw mechanism
- if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
- }
- else
- {
- halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
- }
- }
-}
-
-//PAN(EDR)+A2DP
-VOID
-halbtc8723a2ant_ActionPanEdrA2dp(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- u1Byte wifiRssiState, wifiRssiState1, btInfoExt;
- u4Byte wifiBw;
-
- btInfoExt = pCoexSta->btInfoExt;
-
- if(halbtc8723a2ant_NeedToDecBtPwr(pBtCoexist))
- halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE);
- else
- halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3);
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
- if(BTC_WIFI_BW_HT40 == wifiBw)
- {
- wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0);
-
- // fw mechanism
- if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
- {
- if(btInfoExt&BIT0) //a2dp basic rate
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4);
- }
- else //a2dp edr rate
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2);
- }
- }
- else
- {
- if(btInfoExt&BIT0) //a2dp basic rate
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8);
- }
- else //a2dp edr rate
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6);
- }
- }
-
- // sw mechanism
- halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
- }
- else
- {
- wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 27, 0);
- wifiRssiState1 = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 47, 0);
-
- // fw mechanism
- if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
- {
- if(btInfoExt&BIT0) //a2dp basic rate
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4);
- }
- else //a2dp edr rate
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2);
- }
- }
- else
- {
- if(btInfoExt&BIT0) //a2dp basic rate
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8);
- }
- else //a2dp edr rate
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6);
- }
- }
-
- // sw mechanism
- if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
- }
- else
- {
- halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
- }
- }
-}
-
-VOID
-halbtc8723a2ant_ActionPanEdrHid(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- u1Byte wifiRssiState, wifiRssiState1;
- u4Byte wifiBw;
-
- if(halbtc8723a2ant_NeedToDecBtPwr(pBtCoexist))
- halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE);
- else
- halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3);
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
- if(BTC_WIFI_BW_HT40 == wifiBw)
- {
- wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0);
-
- // fw mechanism
- if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10);
- }
- else
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14);
- }
-
- // sw mechanism
- halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
- }
- else
- {
- wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 27, 0);
- wifiRssiState1 = halbtc8723a2ant_WifiRssiState(pBtCoexist, 1, 2, 47, 0);
-
- // fw mechanism
- if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10);
- }
- else
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14);
- }
-
- // sw mechanism
- if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
- }
- else
- {
- halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
- }
- }
-}
-
-// HID+A2DP+PAN(EDR)
-VOID
-halbtc8723a2ant_ActionHidA2dpPanEdr(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- u1Byte wifiRssiState, wifiRssiState1, btInfoExt;
- u4Byte wifiBw;
-
- btInfoExt = pCoexSta->btInfoExt;
-
- if(halbtc8723a2ant_NeedToDecBtPwr(pBtCoexist))
- halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE);
- else
- halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3);
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
- if(BTC_WIFI_BW_HT40 == wifiBw)
- {
- wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0);
-
- // fw mechanism
- if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
- {
- if(btInfoExt&BIT0) //a2dp basic rate
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12);
- }
- else //a2dp edr rate
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10);
- }
- }
- else
- {
- if(btInfoExt&BIT0) //a2dp basic rate
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16);
- }
- else //a2dp edr rate
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14);
- }
- }
-
- // sw mechanism
- halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
- }
- else
- {
- wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 27, 0);
- wifiRssiState1 = halbtc8723a2ant_WifiRssiState(pBtCoexist, 1, 2, 47, 0);
-
- // fw mechanism
- if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
- {
- if(btInfoExt&BIT0) //a2dp basic rate
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12);
- }
- else //a2dp edr rate
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10);
- }
- }
- else
- {
- if(btInfoExt&BIT0) //a2dp basic rate
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16);
- }
- else //a2dp edr rate
- {
- halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14);
- }
- }
-
- // sw mechanism
- if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
- }
- else
- {
- halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
- }
- }
-}
-
-VOID
-halbtc8723a2ant_ActionHidA2dp(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- u1Byte wifiRssiState, wifiRssiState1, btInfoExt;
- u4Byte wifiBw;
-
- btInfoExt = pCoexSta->btInfoExt;
-
- if(halbtc8723a2ant_NeedToDecBtPwr(pBtCoexist))
- halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE);
- else
- halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3);
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
- if(BTC_WIFI_BW_HT40 == wifiBw)
- {
- wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0);
-
- // fw mechanism
- if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
- {
- if(btInfoExt&BIT0) //a2dp basic rate
- {
- halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, TRUE, FALSE, 3);
- }
- else //a2dp edr rate
- {
- halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, TRUE, FALSE, 1);
- }
- }
- else
- {
- if(btInfoExt&BIT0) //a2dp basic rate
- {
- halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 3);
- }
- else //a2dp edr rate
- {
- halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 1);
- }
- }
-
- // sw mechanism
- halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
- }
- else
- {
- wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 27, 0);
- wifiRssiState1 = halbtc8723a2ant_WifiRssiState(pBtCoexist, 1, 2, 47, 0);
-
- // fw mechanism
- if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
- {
- if(btInfoExt&BIT0) //a2dp basic rate
- {
- halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, TRUE, FALSE, 3);
- }
- else //a2dp edr rate
- {
- halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, TRUE, FALSE, 1);
- }
- }
- else
- {
- if(btInfoExt&BIT0) //a2dp basic rate
- {
- halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 3);
- }
- else //a2dp edr rate
- {
- halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 1);
- }
- }
-
- // sw mechanism
- if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) ||
- (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE);
- halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
- }
- else
- {
- halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
- halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
- }
- }
-}
-
-VOID
-halbtc8723a2ant_RunCoexistMechanism(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo;
- u1Byte btInfoOriginal=0, btRetryCnt=0;
- u1Byte algorithm=0;
-
- if(pBtCoexist->bManualControl)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Manual control!!!\n"));
- return;
- }
-
- if(pStackInfo->bProfileNotified)
- {
- if(pCoexSta->bHoldForStackOperation)
- {
- // if bt inquiry/page/pair, do not execute.
- return;
- }
-
- algorithm = halbtc8723a2ant_ActionAlgorithm(pBtCoexist);
- if(pCoexSta->bHoldPeriodCnt && (BT_8723A_2ANT_COEX_ALGO_PANHS!=algorithm))
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex],Hold BT inquiry/page scan setting (cnt = %d)!!\n",
- pCoexSta->bHoldPeriodCnt));
- if(pCoexSta->bHoldPeriodCnt >= 6)
- {
- pCoexSta->bHoldPeriodCnt = 0;
- // next time the coexist parameters should be reset again.
- }
- else
- pCoexSta->bHoldPeriodCnt++;
- return;
- }
-
- pCoexDm->curAlgorithm = algorithm;
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Algorithm = %d \n", pCoexDm->curAlgorithm));
- if(halbtc8723a2ant_IsCommonAction(pBtCoexist))
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant common.\n"));
- pCoexDm->bResetTdmaAdjust = TRUE;
- }
- else
- {
- if(pCoexDm->curAlgorithm != pCoexDm->preAlgorithm)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], preAlgorithm=%d, curAlgorithm=%d\n",
- pCoexDm->preAlgorithm, pCoexDm->curAlgorithm));
- pCoexDm->bResetTdmaAdjust = TRUE;
- }
- switch(pCoexDm->curAlgorithm)
- {
- case BT_8723A_2ANT_COEX_ALGO_SCO:
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = SCO.\n"));
- halbtc8723a2ant_ActionSco(pBtCoexist);
- break;
- case BT_8723A_2ANT_COEX_ALGO_HID:
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID.\n"));
- halbtc8723a2ant_ActionHid(pBtCoexist);
- break;
- case BT_8723A_2ANT_COEX_ALGO_A2DP:
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = A2DP.\n"));
- halbtc8723a2ant_ActionA2dp(pBtCoexist);
- break;
- case BT_8723A_2ANT_COEX_ALGO_PANEDR:
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n"));
- halbtc8723a2ant_ActionPanEdr(pBtCoexist);
- break;
- case BT_8723A_2ANT_COEX_ALGO_PANHS:
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HS mode.\n"));
- halbtc8723a2ant_ActionPanHs(pBtCoexist);
- break;
- case BT_8723A_2ANT_COEX_ALGO_PANEDR_A2DP:
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n"));
- halbtc8723a2ant_ActionPanEdrA2dp(pBtCoexist);
- break;
- case BT_8723A_2ANT_COEX_ALGO_PANEDR_HID:
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n"));
- halbtc8723a2ant_ActionPanEdrHid(pBtCoexist);
- break;
- case BT_8723A_2ANT_COEX_ALGO_HID_A2DP_PANEDR:
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n"));
- halbtc8723a2ant_ActionHidA2dpPanEdr(pBtCoexist);
- break;
- case BT_8723A_2ANT_COEX_ALGO_HID_A2DP:
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n"));
- halbtc8723a2ant_ActionHidA2dp(pBtCoexist);
- break;
- default:
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n"));
- halbtc8723a2ant_CoexAllOff(pBtCoexist);
- break;
- }
- pCoexDm->preAlgorithm = pCoexDm->curAlgorithm;
- }
- }
-}
-
-//============================================================
-// work around function start with wa_halbtc8723a2ant_
-//============================================================
-VOID
-wa_halbtc8723a2ant_MonitorC2h(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- u1Byte tmp1b=0x0;
- u4Byte curC2hTotalCnt=0x0;
- static u4Byte preC2hTotalCnt=0x0, sameCntPollingTime=0x0;
-
- curC2hTotalCnt+=pCoexSta->btInfoC2hCnt[BT_INFO_SRC_8723A_2ANT_BT_RSP];
-
- if(curC2hTotalCnt == preC2hTotalCnt)
- {
- sameCntPollingTime++;
- }
- else
- {
- preC2hTotalCnt = curC2hTotalCnt;
- sameCntPollingTime = 0;
- }
-
- if(sameCntPollingTime >= 2)
- {
- tmp1b = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x1af);
- if(tmp1b != 0x0)
- {
- pCoexSta->c2hHangDetectCnt++;
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x1af, 0x0);
- }
- }
-}
-
-//============================================================
-// extern function start with EXhalbtc8723a2ant_
-//============================================================
-VOID
-EXhalbtc8723a2ant_PowerOnSetting(
- IN PBTC_COEXIST pBtCoexist
- )
-{
-}
-
-VOID
-EXhalbtc8723a2ant_InitHwConfig(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bWifiOnly
- )
-{
- u4Byte u4Tmp=0;
- u1Byte u1Tmp=0;
-
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 2Ant Init HW Config!!\n"));
-
- // backup rf 0x1e value
- pCoexDm->btRf0x1eBackup =
- pBtCoexist->fBtcGetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff);
-
- // Enable counter statistics
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0x4);
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x778, 0x3);
- pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x20);
-}
-
-VOID
-EXhalbtc8723a2ant_InitCoexDm(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Coex Mechanism Init!!\n"));
-
- halbtc8723a2ant_InitCoexDm(pBtCoexist);
-}
-
-VOID
-EXhalbtc8723a2ant_DisplayCoexInfo(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo;
- PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo;
- pu1Byte cliBuf=pBtCoexist->cliBuf;
- u1Byte u1Tmp[4], i, btInfoExt, psTdmaCase=0;
- u4Byte u4Tmp[4];
-
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[BT Coexist info]============");
- CL_PRINTF(cliBuf);
-
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", "Ant PG number/ Ant mechanism:", \
- pBoardInfo->pgAntNum, pBoardInfo->btdmAntNum);
- CL_PRINTF(cliBuf);
-
- if(pBtCoexist->bManualControl)
- {
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "[Action Manual control]!!");
- CL_PRINTF(cliBuf);
- }
-
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d", "BT stack/ hci ext ver", \
- ((pStackInfo->bProfileNotified)? "Yes":"No"), pStackInfo->hciVersion);
- CL_PRINTF(cliBuf);
-
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", "Wifi channel informed to BT", \
- pCoexDm->wifiChnlInfo[0], pCoexDm->wifiChnlInfo[1],
- pCoexDm->wifiChnlInfo[2]);
- CL_PRINTF(cliBuf);
-
- // wifi status
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Wifi Status]============");
- CL_PRINTF(cliBuf);
- pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_WIFI_STATUS);
-
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[BT Status]============");
- CL_PRINTF(cliBuf);
-
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ", "BT [status/ rssi/ retryCnt]", \
- ((pCoexSta->bC2hBtInquiryPage)?("inquiry/page scan"):((BT_8723A_2ANT_BT_STATUS_IDLE == pCoexDm->btStatus)? "idle":( (BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus)? "connected-idle":"busy"))),
- pCoexSta->btRssi, pCoexSta->btRetryCnt);
- CL_PRINTF(cliBuf);
-
- if(pStackInfo->bProfileNotified)
- {
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", "SCO/HID/PAN/A2DP", \
- pStackInfo->bScoExist, pStackInfo->bHidExist, pStackInfo->bPanExist, pStackInfo->bA2dpExist);
- CL_PRINTF(cliBuf);
-
- pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_BT_LINK_INFO);
- }
-
- btInfoExt = pCoexSta->btInfoExt;
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "BT Info A2DP rate", \
- (btInfoExt&BIT0)? "Basic rate":"EDR rate");
- CL_PRINTF(cliBuf);
-
- for(i=0; ibtInfoC2hCnt[i])
- {
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", GLBtInfoSrc8723a2Ant[i], \
- pCoexSta->btInfoC2h[i][0], pCoexSta->btInfoC2h[i][1],
- pCoexSta->btInfoC2h[i][2], pCoexSta->btInfoC2h[i][3],
- pCoexSta->btInfoC2h[i][4], pCoexSta->btInfoC2h[i][5],
- pCoexSta->btInfoC2h[i][6], pCoexSta->btInfoC2hCnt[i]);
- CL_PRINTF(cliBuf);
- }
- }
-
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "write 0x1af=0x0 num", \
- pCoexSta->c2hHangDetectCnt);
- CL_PRINTF(cliBuf);
-
- // Sw mechanism
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Sw mechanism]============");
- CL_PRINTF(cliBuf);
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d", "SM1[ShRf/ LpRA/ LimDig]", \
- pCoexDm->bCurRfRxLpfShrink, pCoexDm->bCurLowPenaltyRa, pCoexDm->bLimitedDig);
- CL_PRINTF(cliBuf);
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ", "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]", \
- pCoexDm->bCurAgcTableEn, pCoexDm->bCurAdcBackOff, pCoexDm->bCurDacSwingOn, pCoexDm->curDacSwingLvl);
- CL_PRINTF(cliBuf);
-
- // Fw mechanism
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Fw mechanism]============");
- CL_PRINTF(cliBuf);
-
- if(!pBtCoexist->bManualControl)
- {
- psTdmaCase = pCoexDm->curPsTdma;
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x case-%d", "PS TDMA", \
- pCoexDm->psTdmaPara[0], pCoexDm->psTdmaPara[1],
- pCoexDm->psTdmaPara[2], pCoexDm->psTdmaPara[3],
- pCoexDm->psTdmaPara[4], psTdmaCase);
- CL_PRINTF(cliBuf);
-
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", "DecBtPwr/ IgnWlanAct", \
- pCoexDm->bCurDecBtPwr, pCoexDm->bCurIgnoreWlanAct);
- CL_PRINTF(cliBuf);
- }
-
- // Hw setting
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Hw setting]============");
- CL_PRINTF(cliBuf);
-
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "RF-A, 0x1e initVal", \
- pCoexDm->btRf0x1eBackup);
- CL_PRINTF(cliBuf);
-
- u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x778);
- u1Tmp[1] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x783);
- u1Tmp[2] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x796);
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "0x778/ 0x783/ 0x796", \
- u1Tmp[0], u1Tmp[1], u1Tmp[2]);
- CL_PRINTF(cliBuf);
-
- u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x880);
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x880", \
- u4Tmp[0]);
- CL_PRINTF(cliBuf);
-
- u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x40);
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x40", \
- u1Tmp[0]);
- CL_PRINTF(cliBuf);
-
- u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x550);
- u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x522);
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0x550(bcn ctrl)/0x522", \
- u4Tmp[0], u1Tmp[0]);
- CL_PRINTF(cliBuf);
-
- u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x484);
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x484(rate adaptive)", \
- u4Tmp[0]);
- CL_PRINTF(cliBuf);
-
- u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xc50);
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)", \
- u4Tmp[0]);
- CL_PRINTF(cliBuf);
-
- u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xda0);
- u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xda4);
- u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xda8);
- u4Tmp[3] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xdac);
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "0xda0/0xda4/0xda8/0xdac(FA cnt)", \
- u4Tmp[0], u4Tmp[1], u4Tmp[2], u4Tmp[3]);
- CL_PRINTF(cliBuf);
-
- u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c0);
- u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c4);
- u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c8);
- u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x6cc);
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)", \
- u4Tmp[0], u4Tmp[1], u4Tmp[2], u1Tmp[0]);
- CL_PRINTF(cliBuf);
-
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x770 (hp rx[31:16]/tx[15:0])", \
- pCoexSta->highPriorityRx, pCoexSta->highPriorityTx);
- CL_PRINTF(cliBuf);
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x774(lp rx[31:16]/tx[15:0])", \
- pCoexSta->lowPriorityRx, pCoexSta->lowPriorityTx);
- CL_PRINTF(cliBuf);
-
- pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_COEX_STATISTICS);
-}
-
-
-VOID
-EXhalbtc8723a2ant_IpsNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- )
-{
- if(BTC_IPS_ENTER == type)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS ENTER notify\n"));
- halbtc8723a2ant_CoexAllOff(pBtCoexist);
- }
- else if(BTC_IPS_LEAVE == type)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS LEAVE notify\n"));
- //halbtc8723a2ant_InitCoexDm(pBtCoexist);
- }
-}
-
-VOID
-EXhalbtc8723a2ant_LpsNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- )
-{
- if(BTC_LPS_ENABLE == type)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS ENABLE notify\n"));
- }
- else if(BTC_LPS_DISABLE == type)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS DISABLE notify\n"));
- }
-}
-
-VOID
-EXhalbtc8723a2ant_ScanNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- )
-{
- if(BTC_SCAN_START == type)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN START notify\n"));
- }
- else if(BTC_SCAN_FINISH == type)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN FINISH notify\n"));
- }
-}
-
-VOID
-EXhalbtc8723a2ant_ConnectNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- )
-{
- if(BTC_ASSOCIATE_START == type)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT START notify\n"));
- }
- else if(BTC_ASSOCIATE_FINISH == type)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT FINISH notify\n"));
- }
-}
-
-VOID
-EXhalbtc8723a2ant_MediaStatusNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- )
-{
- if(BTC_MEDIA_CONNECT == type)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA connect notify\n"));
- }
- else
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA disconnect notify\n"));
- }
-
- halbtc8723a2ant_IndicateWifiChnlBwInfo(pBtCoexist, type);
-}
-
-VOID
-EXhalbtc8723a2ant_SpecialPacketNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- )
-{
- if(type == BTC_PACKET_DHCP)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], DHCP Packet notify\n"));
- }
-}
-
-VOID
-EXhalbtc8723a2ant_BtInfoNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN pu1Byte tmpBuf,
- IN u1Byte length
- )
-{
- u1Byte btInfo=0;
- u1Byte i, rspSource=0;
- BOOLEAN bBtBusy=FALSE, bLimitedDig=FALSE;
- BOOLEAN bWifiConnected=FALSE, bBtHsOn=FALSE;
-
- pCoexSta->bC2hBtInfoReqSent = FALSE;
-
- rspSource = BT_INFO_SRC_8723A_2ANT_BT_RSP;
- pCoexSta->btInfoC2hCnt[rspSource]++;
-
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Bt info[%d], length=%d, hex data=[", rspSource, length));
- for(i=0; ibtInfoC2h[rspSource][i] = tmpBuf[i];
- if(i == 0)
- btInfo = tmpBuf[i];
- if(i == length-1)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("0x%02x]\n", tmpBuf[i]));
- }
- else
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("0x%02x, ", tmpBuf[i]));
- }
- }
-
- if(BT_INFO_SRC_8723A_2ANT_WIFI_FW != rspSource)
- {
- pCoexSta->btRetryCnt =
- pCoexSta->btInfoC2h[rspSource][1];
-
- pCoexSta->btRssi =
- pCoexSta->btInfoC2h[rspSource][2]*2+10;
-
- pCoexSta->btInfoExt =
- pCoexSta->btInfoC2h[rspSource][3];
- }
-
- pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn);
- // check BIT2 first ==> check if bt is under inquiry or page scan
- if(btInfo & BT_INFO_8723A_2ANT_B_INQ_PAGE)
- {
- pCoexSta->bC2hBtInquiryPage = TRUE;
- }
- else
- {
- pCoexSta->bC2hBtInquiryPage = FALSE;
- }
-}
-
-VOID
-EXhalbtc8723a2ant_StackOperationNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- )
-{
- if(BTC_STACK_OP_INQ_PAGE_PAIR_START == type)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], StackOP Inquiry/page/pair start notify\n"));
- pCoexSta->bHoldForStackOperation = TRUE;
- pCoexSta->bHoldPeriodCnt = 1;
- halbtc8723a2ant_BtInquiryPage(pBtCoexist);
- }
- else if(BTC_STACK_OP_INQ_PAGE_PAIR_FINISH == type)
- {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], StackOP Inquiry/page/pair finish notify\n"));
- pCoexSta->bHoldForStackOperation = FALSE;
- }
-}
-
-VOID
-EXhalbtc8723a2ant_HaltNotify(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Halt notify\n"));
-
- halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, TRUE);
- EXhalbtc8723a2ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT);
-}
-
-VOID
-EXhalbtc8723a2ant_Periodical(
- IN PBTC_COEXIST pBtCoexist
- )
-{
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 2Ant Periodical!!\n"));
-
- // work around for c2h hang
- wa_halbtc8723a2ant_MonitorC2h(pBtCoexist);
-
- halbtc8723a2ant_QueryBtInfo(pBtCoexist);
- halbtc8723a2ant_MonitorBtCtr(pBtCoexist);
- halbtc8723a2ant_MonitorBtEnableDisable(pBtCoexist);
-
- halbtc8723a2ant_RunCoexistMechanism(pBtCoexist);
-}
-
-
-#endif
-
diff --git a/hal/btc/HalBtc8723a2Ant.h b/hal/btc/HalBtc8723a2Ant.h
deleted file mode 100644
index d5d5488..0000000
--- a/hal/btc/HalBtc8723a2Ant.h
+++ /dev/null
@@ -1,184 +0,0 @@
-//===========================================
-// The following is for 8723A 2Ant BT Co-exist definition
-//===========================================
-#define BT_INFO_8723A_2ANT_B_FTP BIT7
-#define BT_INFO_8723A_2ANT_B_A2DP BIT6
-#define BT_INFO_8723A_2ANT_B_HID BIT5
-#define BT_INFO_8723A_2ANT_B_SCO_BUSY BIT4
-#define BT_INFO_8723A_2ANT_B_ACL_BUSY BIT3
-#define BT_INFO_8723A_2ANT_B_INQ_PAGE BIT2
-#define BT_INFO_8723A_2ANT_B_SCO_ESCO BIT1
-#define BT_INFO_8723A_2ANT_B_CONNECTION BIT0
-
-#define BTC_RSSI_COEX_THRESH_TOL_8723A_2ANT 2
-
-typedef enum _BT_INFO_SRC_8723A_2ANT{
- BT_INFO_SRC_8723A_2ANT_WIFI_FW = 0x0,
- BT_INFO_SRC_8723A_2ANT_BT_RSP = 0x1,
- BT_INFO_SRC_8723A_2ANT_BT_ACTIVE_SEND = 0x2,
- BT_INFO_SRC_8723A_2ANT_MAX
-}BT_INFO_SRC_8723A_2ANT,*PBT_INFO_SRC_8723A_2ANT;
-
-typedef enum _BT_8723A_2ANT_BT_STATUS{
- BT_8723A_2ANT_BT_STATUS_IDLE = 0x0,
- BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
- BT_8723A_2ANT_BT_STATUS_NON_IDLE = 0x2,
- BT_8723A_2ANT_BT_STATUS_MAX
-}BT_8723A_2ANT_BT_STATUS,*PBT_8723A_2ANT_BT_STATUS;
-
-typedef enum _BT_8723A_2ANT_COEX_ALGO{
- BT_8723A_2ANT_COEX_ALGO_UNDEFINED = 0x0,
- BT_8723A_2ANT_COEX_ALGO_SCO = 0x1,
- BT_8723A_2ANT_COEX_ALGO_HID = 0x2,
- BT_8723A_2ANT_COEX_ALGO_A2DP = 0x3,
- BT_8723A_2ANT_COEX_ALGO_PANEDR = 0x4,
- BT_8723A_2ANT_COEX_ALGO_PANHS = 0x5,
- BT_8723A_2ANT_COEX_ALGO_PANEDR_A2DP = 0x6,
- BT_8723A_2ANT_COEX_ALGO_PANEDR_HID = 0x7,
- BT_8723A_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x8,
- BT_8723A_2ANT_COEX_ALGO_HID_A2DP = 0x9,
- BT_8723A_2ANT_COEX_ALGO_MAX
-}BT_8723A_2ANT_COEX_ALGO,*PBT_8723A_2ANT_COEX_ALGO;
-
-typedef struct _COEX_DM_8723A_2ANT{
- // fw mechanism
- BOOLEAN bPreDecBtPwr;
- BOOLEAN bCurDecBtPwr;
- //BOOLEAN bPreBtLnaConstrain;
- //BOOLEAN bCurBtLnaConstrain;
- //u1Byte bPreBtPsdMode;
- //u1Byte bCurBtPsdMode;
- u1Byte preFwDacSwingLvl;
- u1Byte curFwDacSwingLvl;
- BOOLEAN bCurIgnoreWlanAct;
- BOOLEAN bPreIgnoreWlanAct;
- u1Byte prePsTdma;
- u1Byte curPsTdma;
- u1Byte psTdmaPara[5];
- u1Byte psTdmaDuAdjType;
- BOOLEAN bResetTdmaAdjust;
- BOOLEAN bPrePsTdmaOn;
- BOOLEAN bCurPsTdmaOn;
- //BOOLEAN bPreBtAutoReport;
- //BOOLEAN bCurBtAutoReport;
-
- // sw mechanism
- BOOLEAN bPreRfRxLpfShrink;
- BOOLEAN bCurRfRxLpfShrink;
- u4Byte btRf0x1eBackup;
- BOOLEAN bPreLowPenaltyRa;
- BOOLEAN bCurLowPenaltyRa;
- BOOLEAN bPreDacSwingOn;
- u4Byte preDacSwingLvl;
- BOOLEAN bCurDacSwingOn;
- u4Byte curDacSwingLvl;
- BOOLEAN bPreAdcBackOff;
- BOOLEAN bCurAdcBackOff;
- BOOLEAN bPreAgcTableEn;
- BOOLEAN bCurAgcTableEn;
- u4Byte preVal0x6c0;
- u4Byte curVal0x6c0;
- u4Byte preVal0x6c8;
- u4Byte curVal0x6c8;
- u1Byte preVal0x6cc;
- u1Byte curVal0x6cc;
- BOOLEAN bLimitedDig;
-
- // algorithm related
- u1Byte preAlgorithm;
- u1Byte curAlgorithm;
- u1Byte btStatus;
- u1Byte wifiChnlInfo[3];
-} COEX_DM_8723A_2ANT, *PCOEX_DM_8723A_2ANT;
-
-typedef struct _COEX_STA_8723A_2ANT{
- u4Byte highPriorityTx;
- u4Byte highPriorityRx;
- u4Byte lowPriorityTx;
- u4Byte lowPriorityRx;
- u1Byte btRssi;
- u1Byte preBtRssiState;
- u1Byte preBtRssiState1;
- u1Byte preWifiRssiState[4];
- BOOLEAN bC2hBtInfoReqSent;
- u1Byte btInfoC2h[BT_INFO_SRC_8723A_2ANT_MAX][10];
- u4Byte btInfoC2hCnt[BT_INFO_SRC_8723A_2ANT_MAX];
- BOOLEAN bC2hBtInquiryPage;
- u1Byte btRetryCnt;
- u1Byte btInfoExt;
- BOOLEAN bHoldForStackOperation;
- u1Byte bHoldPeriodCnt;
- // this is for c2h hang work-around
- u4Byte c2hHangDetectCnt;
-}COEX_STA_8723A_2ANT, *PCOEX_STA_8723A_2ANT;
-
-//===========================================
-// The following is interface which will notify coex module.
-//===========================================
-VOID
-EXhalbtc8723a2ant_PowerOnSetting(
- IN PBTC_COEXIST pBtCoexist
- );
-VOID
-EXhalbtc8723a2ant_InitHwConfig(
- IN PBTC_COEXIST pBtCoexist,
- IN BOOLEAN bWifiOnly
- );
-VOID
-EXhalbtc8723a2ant_InitCoexDm(
- IN PBTC_COEXIST pBtCoexist
- );
-VOID
-EXhalbtc8723a2ant_IpsNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- );
-VOID
-EXhalbtc8723a2ant_LpsNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- );
-VOID
-EXhalbtc8723a2ant_ScanNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- );
-VOID
-EXhalbtc8723a2ant_ConnectNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- );
-VOID
-EXhalbtc8723a2ant_MediaStatusNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- );
-VOID
-EXhalbtc8723a2ant_SpecialPacketNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- );
-VOID
-EXhalbtc8723a2ant_HaltNotify(
- IN PBTC_COEXIST pBtCoexist
- );
-VOID
-EXhalbtc8723a2ant_Periodical(
- IN PBTC_COEXIST pBtCoexist
- );
-VOID
-EXhalbtc8723a2ant_BtInfoNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN pu1Byte tmpBuf,
- IN u1Byte length
- );
-VOID
-EXhalbtc8723a2ant_StackOperationNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
- );
-VOID
-EXhalbtc8723a2ant_DisplayCoexInfo(
- IN PBTC_COEXIST pBtCoexist
- );
-
diff --git a/hal/btc/HalBtc8723b1Ant.c b/hal/btc/HalBtc8723b1Ant.c
deleted file mode 100644
index a15a601..0000000
--- a/hal/btc/HalBtc8723b1Ant.c
+++ /dev/null
@@ -1,4845 +0,0 @@
-/* ************************************************************
- * Description:
- *
- * This file is for RTL8723B Co-exist mechanism
- *
- * History
- * 2012/11/15 Cosa first check in.
- *
- * ************************************************************ */
-
-/* ************************************************************
- * include files
- * ************************************************************ */
-#include "Mp_Precomp.h"
-
-#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
-
-#if (RTL8723B_SUPPORT == 1)
-/* ************************************************************
- * Global variables, these are static variables
- * ************************************************************ */
-static u8 *trace_buf = &gl_btc_trace_buf[0];
-static struct coex_dm_8723b_1ant glcoex_dm_8723b_1ant;
-static struct coex_dm_8723b_1ant *coex_dm = &glcoex_dm_8723b_1ant;
-static struct coex_sta_8723b_1ant glcoex_sta_8723b_1ant;
-static struct coex_sta_8723b_1ant *coex_sta = &glcoex_sta_8723b_1ant;
-static struct psdscan_sta_8723b_1ant gl_psd_scan_8723b_1ant;
-static struct psdscan_sta_8723b_1ant *psd_scan = &gl_psd_scan_8723b_1ant;
-
-
-const char *const glbt_info_src_8723b_1ant[]={
- "BT Info[wifi fw]",
- "BT Info[bt rsp]",
- "BT Info[bt auto report]",
-};
-
-u32 glcoex_ver_date_8723b_1ant = 20151015;
-u32 glcoex_ver_8723b_1ant = 0x63;
-
-/* ************************************************************
- * local function proto type if needed
- * ************************************************************
- * ************************************************************
- * local function start with halbtc8723b1ant_
- * ************************************************************ */
-
-void halbtc8723b1ant_update_ra_mask(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u32 dis_rate_mask)
-{
- coex_dm->cur_ra_mask = dis_rate_mask;
-
- if( force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask))
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK,
- &coex_dm->cur_ra_mask);
- coex_dm->pre_ra_mask = coex_dm->cur_ra_mask;
-}
-
-void halbtc8723b1ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- boolean wifi_under_b_mode = false;
-
- coex_dm->cur_arfr_type = type;
-
- if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) {
- switch (coex_dm->cur_arfr_type) {
- case 0: /* normal mode */
- btcoexist->btc_write_4byte(btcoexist, 0x430,
- coex_dm->backup_arfr_cnt1);
- btcoexist->btc_write_4byte(btcoexist, 0x434,
- coex_dm->backup_arfr_cnt2);
- break;
- case 1:
- btcoexist->btc_get(btcoexist,
- BTC_GET_BL_WIFI_UNDER_B_MODE,
- &wifi_under_b_mode);
- if (wifi_under_b_mode) {
- btcoexist->btc_write_4byte(btcoexist,
- 0x430, 0x0);
- btcoexist->btc_write_4byte(btcoexist,
- 0x434, 0x01010101);
- } else {
- btcoexist->btc_write_4byte(btcoexist,
- 0x430, 0x0);
- btcoexist->btc_write_4byte(btcoexist,
- 0x434, 0x04030201);
- }
- break;
- default:
- break;
- }
- }
-
- coex_dm->pre_arfr_type = coex_dm->cur_arfr_type;
-}
-
-void halbtc8723b1ant_retry_limit(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- coex_dm->cur_retry_limit_type = type;
-
- if (force_exec ||
- (coex_dm->pre_retry_limit_type !=
- coex_dm->cur_retry_limit_type)) {
- switch (coex_dm->cur_retry_limit_type) {
- case 0: /* normal mode */
- btcoexist->btc_write_2byte(btcoexist, 0x42a,
- coex_dm->backup_retry_limit);
- break;
- case 1: /* retry limit=8 */
- btcoexist->btc_write_2byte(btcoexist, 0x42a,
- 0x0808);
- break;
- default:
- break;
- }
- }
-
- coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type;
-}
-
-void halbtc8723b1ant_ampdu_max_time(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- coex_dm->cur_ampdu_time_type = type;
-
- if (force_exec ||
- (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) {
- switch (coex_dm->cur_ampdu_time_type) {
- case 0: /* normal mode */
- btcoexist->btc_write_1byte(btcoexist, 0x456,
- coex_dm->backup_ampdu_max_time);
- break;
- case 1: /* AMPDU timw = 0x38 * 32us */
- btcoexist->btc_write_1byte(btcoexist, 0x456,
- 0x38);
- break;
- default:
- break;
- }
- }
-
- coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type;
-}
-
-void halbtc8723b1ant_limited_tx(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type,
- IN u8 retry_limit_type, IN u8 ampdu_time_type)
-{
- switch (ra_mask_type) {
- case 0: /* normal mode */
- halbtc8723b1ant_update_ra_mask(btcoexist, force_exec,
- 0x0);
- break;
- case 1: /* disable cck 1/2 */
- halbtc8723b1ant_update_ra_mask(btcoexist, force_exec,
- 0x00000003);
- break;
- case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */
- halbtc8723b1ant_update_ra_mask(btcoexist, force_exec,
- 0x0001f1f7);
- break;
- default:
- break;
- }
-
- halbtc8723b1ant_auto_rate_fallback_retry(btcoexist, force_exec,
- arfr_type);
- halbtc8723b1ant_retry_limit(btcoexist, force_exec, retry_limit_type);
- halbtc8723b1ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type);
-}
-
-void halbtc8723b1ant_limited_rx(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean rej_ap_agg_pkt,
- IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size)
-{
- boolean reject_rx_agg = rej_ap_agg_pkt;
- boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size;
- u8 rx_agg_size = agg_buf_size;
-
- /* ============================================ */
- /* Rx Aggregation related setting */
- /* ============================================ */
- btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT,
- &reject_rx_agg);
- /* decide BT control aggregation buf size or not */
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE,
- &bt_ctrl_rx_agg_size);
- /* aggregation buf size, only work when BT control Rx aggregation size. */
- btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size);
- /* real update aggregation setting */
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
-
-
-}
-
-void halbtc8723b1ant_query_bt_info(IN struct btc_coexist *btcoexist)
-{
- u8 h2c_parameter[1] = {0};
-
- coex_sta->c2h_bt_info_req_sent = true;
-
- h2c_parameter[0] |= BIT(0); /* trigger */
-
- btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter);
-}
-
-void halbtc8723b1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist)
-{
- u32 reg_hp_txrx, reg_lp_txrx, u32tmp;
- u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
- static u32 num_of_bt_counter_chk = 0;
-
- reg_hp_txrx = 0x770;
- reg_lp_txrx = 0x774;
-
- u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
- reg_hp_tx = u32tmp & MASKLWORD;
- reg_hp_rx = (u32tmp & MASKHWORD) >> 16;
-
- u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
- reg_lp_tx = u32tmp & MASKLWORD;
- reg_lp_rx = (u32tmp & MASKHWORD) >> 16;
-
- coex_sta->high_priority_tx = reg_hp_tx;
- coex_sta->high_priority_rx = reg_hp_rx;
- coex_sta->low_priority_tx = reg_lp_tx;
- coex_sta->low_priority_rx = reg_lp_rx;
-
- if ((coex_sta->low_priority_tx > 1050) &&
- (!coex_sta->c2h_bt_inquiry_page))
- coex_sta->pop_event_cnt++;
-
- /* reset counter */
- btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
-
- /* This part is for wifi FW and driver to update BT's status as disabled. */
- /* The flow is as the following */
- /* 1. disable BT */
- /* 2. if all BT Tx/Rx counter=0, after 6 sec we query bt info */
- /* 3. Because BT will not rsp from mailbox, so wifi fw will know BT is disabled */
- /* 4. FW will rsp c2h for BT that driver will know BT is disabled. */
- if ((reg_hp_tx == 0) && (reg_hp_rx == 0) && (reg_lp_tx == 0) &&
- (reg_lp_rx == 0)) {
- num_of_bt_counter_chk++;
- if (num_of_bt_counter_chk == 3)
- halbtc8723b1ant_query_bt_info(btcoexist);
- } else
- num_of_bt_counter_chk = 0;
-}
-
-
-void halbtc8723b1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist)
-{
- s32 wifi_rssi = 0;
- boolean wifi_busy = false, wifi_under_b_mode = false;
- static u8 cck_lock_counter = 0;
- u32 total_cnt;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
- &wifi_under_b_mode);
-
- if (coex_sta->under_ips) {
- coex_sta->crc_ok_cck = 0;
- coex_sta->crc_ok_11g = 0;
- coex_sta->crc_ok_11n = 0;
- coex_sta->crc_ok_11n_agg = 0;
-
- coex_sta->crc_err_cck = 0;
- coex_sta->crc_err_11g = 0;
- coex_sta->crc_err_11n = 0;
- coex_sta->crc_err_11n_agg = 0;
- } else {
- coex_sta->crc_ok_cck = btcoexist->btc_read_4byte(btcoexist,
- 0xf88);
- coex_sta->crc_ok_11g = btcoexist->btc_read_2byte(btcoexist,
- 0xf94);
- coex_sta->crc_ok_11n = btcoexist->btc_read_2byte(btcoexist,
- 0xf90);
- coex_sta->crc_ok_11n_agg = btcoexist->btc_read_2byte(btcoexist,
- 0xfb8);
-
- coex_sta->crc_err_cck = btcoexist->btc_read_4byte(btcoexist,
- 0xf84);
- coex_sta->crc_err_11g = btcoexist->btc_read_2byte(btcoexist,
- 0xf96);
- coex_sta->crc_err_11n = btcoexist->btc_read_2byte(btcoexist,
- 0xf92);
- coex_sta->crc_err_11n_agg = btcoexist->btc_read_2byte(btcoexist,
- 0xfba);
- }
-
-
- /* reset counter */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xf16, 0x1, 0x1);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xf16, 0x1, 0x0);
-
- if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) {
- total_cnt = coex_sta->crc_ok_cck + coex_sta->crc_ok_11g +
- coex_sta->crc_ok_11n +
- coex_sta->crc_ok_11n_agg;
-
- if ( (coex_dm->bt_status == BT_8723B_1ANT_BT_STATUS_ACL_BUSY) ||
- (coex_dm->bt_status ==
- BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY) ||
- (coex_dm->bt_status ==
- BT_8723B_1ANT_BT_STATUS_SCO_BUSY)) {
- if (coex_sta->crc_ok_cck > (total_cnt -
-coex_sta->crc_ok_cck)) {
- if (cck_lock_counter < 3)
- cck_lock_counter++;
- } else {
- if (cck_lock_counter > 0)
- cck_lock_counter--;
- }
-
- } else {
- if (cck_lock_counter > 0)
- cck_lock_counter--;
- }
- } else {
- if (cck_lock_counter > 0)
- cck_lock_counter--;
- }
-
- if (!coex_sta->pre_ccklock) {
-
- if (cck_lock_counter >= 3)
- coex_sta->cck_lock = true;
- else
- coex_sta->cck_lock = false;
- } else {
- if (cck_lock_counter == 0)
- coex_sta->cck_lock = false;
- else
- coex_sta->cck_lock = true;
- }
-
- if (coex_sta->cck_lock)
- coex_sta->cck_ever_lock = true;
-
- coex_sta->pre_ccklock = coex_sta->cck_lock;
-
-
-}
-
-boolean halbtc8723b1ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist)
-{
- static boolean pre_wifi_busy = false, pre_under_4way = false,
- pre_bt_hs_on = false;
- boolean wifi_busy = false, under_4way = false, bt_hs_on = false;
- boolean wifi_connected = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
- &under_4way);
-
- if (wifi_connected) {
- if (wifi_busy != pre_wifi_busy) {
- pre_wifi_busy = wifi_busy;
- return true;
- }
- if (under_4way != pre_under_4way) {
- pre_under_4way = under_4way;
- return true;
- }
- if (bt_hs_on != pre_bt_hs_on) {
- pre_bt_hs_on = bt_hs_on;
- return true;
- }
-
-
- }
-
- return false;
-}
-
-void halbtc8723b1ant_update_bt_link_info(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean bt_hs_on = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
-
- bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
- bt_link_info->sco_exist = coex_sta->sco_exist;
- bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
- bt_link_info->pan_exist = coex_sta->pan_exist;
- bt_link_info->hid_exist = coex_sta->hid_exist;
- bt_link_info->bt_hi_pri_link_exist = coex_sta->bt_hi_pri_link_exist;
-
- /* work around for HS mode. */
- if (bt_hs_on) {
- bt_link_info->pan_exist = true;
- bt_link_info->bt_link_exist = true;
- }
-
- /* check if Sco only */
- if( bt_link_info->sco_exist &&
- !bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist &&
- !bt_link_info->hid_exist )
- bt_link_info->sco_only = true;
- else
- bt_link_info->sco_only = false;
-
- /* check if A2dp only */
- if( !bt_link_info->sco_exist &&
- bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist &&
- !bt_link_info->hid_exist )
- bt_link_info->a2dp_only = true;
- else
- bt_link_info->a2dp_only = false;
-
- /* check if Pan only */
- if( !bt_link_info->sco_exist &&
- !bt_link_info->a2dp_exist &&
- bt_link_info->pan_exist &&
- !bt_link_info->hid_exist )
- bt_link_info->pan_only = true;
- else
- bt_link_info->pan_only = false;
-
- /* check if Hid only */
- if( !bt_link_info->sco_exist &&
- !bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist &&
- bt_link_info->hid_exist )
- bt_link_info->hid_only = true;
- else
- bt_link_info->hid_only = false;
-}
-
-void halbtc8723b1ant_set_bt_auto_report(IN struct btc_coexist *btcoexist,
- IN boolean enable_auto_report)
-{
- u8 h2c_parameter[1] = {0};
-
- h2c_parameter[0] = 0;
-
- if (enable_auto_report)
- h2c_parameter[0] |= BIT(0);
-
- btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter);
-}
-
-void halbtc8723b1ant_bt_auto_report(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean enable_auto_report)
-{
- coex_dm->cur_bt_auto_report = enable_auto_report;
-
- if (!force_exec) {
- if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report)
- return;
- }
- halbtc8723b1ant_set_bt_auto_report(btcoexist,
- coex_dm->cur_bt_auto_report);
-
- coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report;
-}
-
-void halbtc8723b1ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist
- *btcoexist, IN boolean low_penalty_ra)
-{
- u8 h2c_parameter[6] = {0};
-
- h2c_parameter[0] = 0x6; /* op_code, 0x6= Retry_Penalty */
-
- if (low_penalty_ra) {
- h2c_parameter[1] |= BIT(0);
- h2c_parameter[2] =
- 0x00; /* normal rate except MCS7/6/5, OFDM54/48/36 */
- h2c_parameter[3] = 0xf7; /* MCS7 or OFDM54 */
- h2c_parameter[4] = 0xf8; /* MCS6 or OFDM48 */
- h2c_parameter[5] = 0xf9; /* MCS5 or OFDM36 */
- }
-
- btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter);
-}
-
-void halbtc8723b1ant_low_penalty_ra(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean low_penalty_ra)
-{
- coex_dm->cur_low_penalty_ra = low_penalty_ra;
-
- if (!force_exec) {
- if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra)
- return;
- }
- halbtc8723b1ant_set_sw_penalty_tx_rate_adaptive(btcoexist,
- coex_dm->cur_low_penalty_ra);
-
- coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra;
-}
-
-void halbtc8723b1ant_set_coex_table(IN struct btc_coexist *btcoexist,
- IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc)
-{
- btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
-
- btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
-
- btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
-
- btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
-}
-
-void halbtc8723b1ant_coex_table(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4,
- IN u32 val0x6c8, IN u8 val0x6cc)
-{
- coex_dm->cur_val0x6c0 = val0x6c0;
- coex_dm->cur_val0x6c4 = val0x6c4;
- coex_dm->cur_val0x6c8 = val0x6c8;
- coex_dm->cur_val0x6cc = val0x6cc;
-
- if (!force_exec) {
- if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) &&
- (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) &&
- (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) &&
- (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc))
- return;
- }
- halbtc8723b1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8,
- val0x6cc);
-
- coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0;
- coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4;
- coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8;
- coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc;
-}
-
-void halbtc8723b1ant_coex_table_with_type(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- struct btc_board_info *board_info = &btcoexist->board_info;
-
-#if BT_8723B_1ANT_ANTDET_ENABLE
-#if BT_8723B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE
- if (board_info->btdm_ant_num_by_ant_det == 2) {
- if (type == 3)
- type = 14;
- else if (type == 4)
- type = 13;
- else if (type == 5)
- type = 8;
- }
-#endif
-#endif
-
- coex_sta->coex_table_type = type;
-
- switch (type) {
- case 0:
- halbtc8723b1ant_coex_table(btcoexist, force_exec,
- 0x55555555, 0x55555555, 0xffffff, 0x3);
- break;
- case 1:
- halbtc8723b1ant_coex_table(btcoexist, force_exec,
- 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3);
- break;
- case 2:
- halbtc8723b1ant_coex_table(btcoexist, force_exec,
- 0x5a5a5a5a, 0x5a5a5a5a, 0xffffff, 0x3);
- break;
- case 3:
- halbtc8723b1ant_coex_table(btcoexist, force_exec,
- 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3);
- break;
- case 4:
- if ((coex_sta->cck_ever_lock) &&
- (coex_sta->scan_ap_num <= 5))
- halbtc8723b1ant_coex_table(btcoexist,
- force_exec, 0x55555555, 0xaaaa5a5a,
- 0xffffff, 0x3);
- else
- halbtc8723b1ant_coex_table(btcoexist,
- force_exec, 0x55555555, 0x5a5a5a5a,
- 0xffffff, 0x3);
- break;
- case 5:
- if ((coex_sta->cck_ever_lock) &&
- (coex_sta->scan_ap_num <= 5))
- halbtc8723b1ant_coex_table(btcoexist,
- force_exec, 0x5a5a5a5a, 0x5aaa5a5a,
- 0xffffff, 0x3);
- else
- halbtc8723b1ant_coex_table(btcoexist,
- force_exec, 0x5a5a5a5a, 0x5aaa5a5a,
- 0xffffff, 0x3);
- break;
- case 6:
- halbtc8723b1ant_coex_table(btcoexist, force_exec,
- 0x55555555, 0xaaaaaaaa, 0xffffff, 0x3);
- break;
- case 7:
- halbtc8723b1ant_coex_table(btcoexist, force_exec,
- 0xaaaaaaaa, 0xaaaaaaaa, 0xffffff, 0x3);
- break;
- case 8:
- halbtc8723b1ant_coex_table(btcoexist, force_exec,
- 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3);
- break;
- case 9:
- halbtc8723b1ant_coex_table(btcoexist, force_exec,
- 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3);
- break;
- case 10:
- halbtc8723b1ant_coex_table(btcoexist, force_exec,
- 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3);
- break;
- case 11:
- halbtc8723b1ant_coex_table(btcoexist, force_exec,
- 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3);
- break;
- case 12:
- halbtc8723b1ant_coex_table(btcoexist, force_exec,
- 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3);
- break;
- case 13:
- halbtc8723b1ant_coex_table(btcoexist, force_exec,
- 0x5fff5fff, 0xaaaaaaaa, 0xffffff, 0x3);
- break;
- case 14:
- halbtc8723b1ant_coex_table(btcoexist, force_exec,
- 0x5fff5fff, 0x5ada5ada, 0xffffff, 0x3);
- break;
- case 15:
- halbtc8723b1ant_coex_table(btcoexist, force_exec,
- 0x55dd55dd, 0xaaaaaaaa, 0xffffff, 0x3);
- break;
- default:
- break;
- }
-}
-
-void halbtc8723b1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist,
- IN boolean enable)
-{
- u8 h2c_parameter[1] = {0};
-
- if (enable) {
- h2c_parameter[0] |= BIT(0); /* function enable */
- }
-
- btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter);
-}
-
-void halbtc8723b1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean enable)
-{
- coex_dm->cur_ignore_wlan_act = enable;
-
- if (!force_exec) {
- if (coex_dm->pre_ignore_wlan_act ==
- coex_dm->cur_ignore_wlan_act)
- return;
- }
- halbtc8723b1ant_set_fw_ignore_wlan_act(btcoexist, enable);
-
- coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
-}
-
-void halbtc8723b1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist,
- IN u8 lps_val, IN u8 rpwm_val)
-{
- u8 lps = lps_val;
- u8 rpwm = rpwm_val;
-
- btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps);
- btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm);
-}
-
-void halbtc8723b1ant_lps_rpwm(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val)
-{
- coex_dm->cur_lps = lps_val;
- coex_dm->cur_rpwm = rpwm_val;
-
- if (!force_exec) {
- if ((coex_dm->pre_lps == coex_dm->cur_lps) &&
- (coex_dm->pre_rpwm == coex_dm->cur_rpwm))
- return;
- }
- halbtc8723b1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val);
-
- coex_dm->pre_lps = coex_dm->cur_lps;
- coex_dm->pre_rpwm = coex_dm->cur_rpwm;
-}
-
-void halbtc8723b1ant_sw_mechanism(IN struct btc_coexist *btcoexist,
- IN boolean low_penalty_ra)
-{
- halbtc8723b1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra);
-}
-
-void halbtc8723b1ant_set_ant_path(IN struct btc_coexist *btcoexist,
- IN u8 ant_pos_type, IN boolean force_exec, IN boolean init_hwcfg,
- IN boolean wifi_off)
-{
- struct btc_board_info *board_info = &btcoexist->board_info;
- u32 fw_ver = 0, u32tmp = 0, cnt_bt_cal_chk = 0;
- boolean pg_ext_switch = false;
- boolean use_ext_switch = false;
- boolean is_in_mp_mode = false;
- u8 h2c_parameter[2] = {0}, u8tmp = 0;
-
- coex_dm->cur_ant_pos_type = ant_pos_type;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_EXT_SWITCH, &pg_ext_switch);
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER,
- &fw_ver); /* [31:16]=fw ver, [15:0]=fw sub ver */
-
- if ((fw_ver > 0 && fw_ver < 0xc0000) || pg_ext_switch)
- use_ext_switch = true;
-
-#if BT_8723B_1ANT_ANTDET_ENABLE
-#if BT_8723B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE
- if (ant_pos_type == BTC_ANT_PATH_PTA) {
- if ((board_info->btdm_ant_det_finish) &&
- (board_info->btdm_ant_num_by_ant_det == 2)) {
- if (board_info->btdm_ant_pos ==
- BTC_ANTENNA_AT_MAIN_PORT)
- ant_pos_type = BTC_ANT_PATH_WIFI;
- else
- ant_pos_type = BTC_ANT_PATH_BT;
- }
- }
-#endif
-#endif
-
- if (init_hwcfg) {
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff,
- 0x780); /* WiFi TRx Mask on */
- /* remove due to interrupt is disabled that polling c2h will fail and delay 100ms. */
- /* btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x3c, 0x15); //BT TRx Mask on */
-
- if (fw_ver >= 0x180000) {
- /* Use H2C to set GNT_BT to HIGH */
- h2c_parameter[0] = 1;
- btcoexist->btc_fill_h2c(btcoexist, 0x6E, 1,
- h2c_parameter);
- } else {
- /* set grant_bt to high */
- btcoexist->btc_write_1byte(btcoexist, 0x765, 0x18);
- }
- /* set wlan_act control by PTA */
- btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4);
-
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20,
- 0x0); /* BT select s0/s1 is controlled by BT */
-
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x39, 0x8, 0x1);
- btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x944, 0x3, 0x3);
- btcoexist->btc_write_1byte(btcoexist, 0x930, 0x77);
- } else if (wifi_off) {
- if (fw_ver >= 0x180000) {
- /* Use H2C to set GNT_BT to HIGH */
- h2c_parameter[0] = 1;
- btcoexist->btc_fill_h2c(btcoexist, 0x6E, 1,
- h2c_parameter);
- } else {
- /* set grant_bt to high */
- btcoexist->btc_write_1byte(btcoexist, 0x765, 0x18);
- }
- /* set wlan_act to always low */
- btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_IS_IN_MP_MODE,
- &is_in_mp_mode);
- if (!is_in_mp_mode)
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67,
- 0x20, 0x0); /* BT select s0/s1 is controlled by BT */
- else
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67,
- 0x20, 0x1); /* BT select s0/s1 is controlled by WiFi */
-
- /* 0x4c[24:23]=00, Set Antenna control by BT_RFE_CTRL BT Vendor 0xac=0xf002 */
- u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c);
- u32tmp &= ~BIT(23);
- u32tmp &= ~BIT(24);
- btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp);
- } else {
- /* Use H2C to set GNT_BT to LOW */
- if (fw_ver >= 0x180000) {
- if (btcoexist->btc_read_1byte(btcoexist, 0x765) != 0) {
- h2c_parameter[0] = 0;
- btcoexist->btc_fill_h2c(btcoexist, 0x6E, 1,
- h2c_parameter);
- }
- } else {
- /* BT calibration check */
- while (cnt_bt_cal_chk <= 20) {
- u8tmp = btcoexist->btc_read_1byte(btcoexist,
- 0x49d);
- cnt_bt_cal_chk++;
- if (u8tmp & BIT(0)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ########### BT is calibrating (wait cnt=%d) ###########\n",
- cnt_bt_cal_chk);
- BTC_TRACE(trace_buf);
- delay_ms(50);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** BT is NOT calibrating (wait cnt=%d)**********\n",
- cnt_bt_cal_chk);
- BTC_TRACE(trace_buf);
- break;
- }
- }
-
- /* set grant_bt to PTA */
- btcoexist->btc_write_1byte(btcoexist, 0x765, 0x0);
- }
-
- if (btcoexist->btc_read_1byte(btcoexist, 0x76e) != 0xc) {
- /* set wlan_act control by PTA */
- btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
- }
-
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20,
- 0x1); /* BT select s0/s1 is controlled by WiFi */
- }
-
- if (use_ext_switch) {
- if (init_hwcfg) {
- /* 0x4c[23]=0, 0x4c[24]=1 Antenna control by WL/BT */
- u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c);
- u32tmp &= ~BIT(23);
- u32tmp |= BIT(24);
- btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp);
-
- btcoexist->btc_write_4byte(btcoexist, 0x948,
- 0x0); /* fixed internal switch S1->WiFi, S0->BT */
-
- if (board_info->btdm_ant_pos ==
- BTC_ANTENNA_AT_MAIN_PORT) {
- /* tell firmware "no antenna inverse" */
- h2c_parameter[0] = 0;
- h2c_parameter[1] = 1; /* ext switch type */
- btcoexist->btc_fill_h2c(btcoexist, 0x65, 2,
- h2c_parameter);
- } else {
- /* tell firmware "antenna inverse" */
- h2c_parameter[0] = 1;
- h2c_parameter[1] = 1; /* ext switch type */
- btcoexist->btc_fill_h2c(btcoexist, 0x65, 2,
- h2c_parameter);
- }
- }
-
- if (force_exec ||
- (coex_dm->cur_ant_pos_type !=
- coex_dm->pre_ant_pos_type)) {
- /* ext switch setting */
- switch (ant_pos_type) {
- case BTC_ANT_PATH_WIFI:
- if (board_info->btdm_ant_pos ==
- BTC_ANTENNA_AT_MAIN_PORT)
- btcoexist->btc_write_1byte_bitmask(
- btcoexist, 0x92c, 0x3,
- 0x1);
- else
- btcoexist->btc_write_1byte_bitmask(
- btcoexist, 0x92c, 0x3,
- 0x2);
- break;
- case BTC_ANT_PATH_BT:
- if (board_info->btdm_ant_pos ==
- BTC_ANTENNA_AT_MAIN_PORT)
- btcoexist->btc_write_1byte_bitmask(
- btcoexist, 0x92c, 0x3,
- 0x2);
- else
- btcoexist->btc_write_1byte_bitmask(
- btcoexist, 0x92c, 0x3,
- 0x1);
- break;
- default:
- case BTC_ANT_PATH_PTA:
- if (board_info->btdm_ant_pos ==
- BTC_ANTENNA_AT_MAIN_PORT)
- btcoexist->btc_write_1byte_bitmask(
- btcoexist, 0x92c, 0x3,
- 0x1);
- else
- btcoexist->btc_write_1byte_bitmask(
- btcoexist, 0x92c, 0x3,
- 0x2);
- break;
- }
- }
- } else {
- if (init_hwcfg) {
- /* 0x4c[23]=1, 0x4c[24]=0 Antenna control by 0x64 */
- u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c);
- u32tmp |= BIT(23);
- u32tmp &= ~BIT(24);
- btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp);
-
- /* Fix Ext switch Main->S1, Aux->S0 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x64, 0x1,
- 0x0);
-
- if (board_info->btdm_ant_pos ==
- BTC_ANTENNA_AT_MAIN_PORT) {
-
- /* tell firmware "no antenna inverse" */
- h2c_parameter[0] = 0;
- h2c_parameter[1] =
- 0; /* internal switch type */
- btcoexist->btc_fill_h2c(btcoexist, 0x65, 2,
- h2c_parameter);
- } else {
-
- /* tell firmware "antenna inverse" */
- h2c_parameter[0] = 1;
- h2c_parameter[1] =
- 0; /* internal switch type */
- btcoexist->btc_fill_h2c(btcoexist, 0x65, 2,
- h2c_parameter);
- }
- }
-
- if (force_exec ||
- (coex_dm->cur_ant_pos_type !=
- coex_dm->pre_ant_pos_type)) {
- /* internal switch setting */
- switch (ant_pos_type) {
- case BTC_ANT_PATH_WIFI:
- if (board_info->btdm_ant_pos ==
- BTC_ANTENNA_AT_MAIN_PORT)
- btcoexist->btc_write_4byte(
- btcoexist, 0x948, 0x0);
- else
- btcoexist->btc_write_4byte(
- btcoexist, 0x948,
- 0x280);
- break;
- case BTC_ANT_PATH_BT:
- if (board_info->btdm_ant_pos ==
- BTC_ANTENNA_AT_MAIN_PORT)
- btcoexist->btc_write_4byte(
- btcoexist, 0x948,
- 0x280);
- else
- btcoexist->btc_write_4byte(
- btcoexist, 0x948, 0x0);
- break;
- default:
- case BTC_ANT_PATH_PTA:
- if (board_info->btdm_ant_pos ==
- BTC_ANTENNA_AT_MAIN_PORT)
- btcoexist->btc_write_4byte(
- btcoexist, 0x948,
- 0x200);
- else
- btcoexist->btc_write_4byte(
- btcoexist, 0x948, 0x80);
- break;
- }
- }
- }
-
- coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type;
-}
-
-void halbtc8723b1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist,
- IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5)
-{
- u8 h2c_parameter[5] = {0};
- u8 real_byte1 = byte1, real_byte5 = byte5;
- boolean ap_enable = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
- &ap_enable);
-
- if (ap_enable) {
- if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
- real_byte1 &= ~BIT(4);
- real_byte1 |= BIT(5);
-
- real_byte5 |= BIT(5);
- real_byte5 &= ~BIT(6);
- }
- }
-
- h2c_parameter[0] = real_byte1;
- h2c_parameter[1] = byte2;
- h2c_parameter[2] = byte3;
- h2c_parameter[3] = byte4;
- h2c_parameter[4] = real_byte5;
-
- coex_dm->ps_tdma_para[0] = real_byte1;
- coex_dm->ps_tdma_para[1] = byte2;
- coex_dm->ps_tdma_para[2] = byte3;
- coex_dm->ps_tdma_para[3] = byte4;
- coex_dm->ps_tdma_para[4] = real_byte5;
-
- btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
-}
-
-
-void halbtc8723b1ant_ps_tdma(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean turn_on, IN u8 type)
-{
- struct btc_board_info *board_info = &btcoexist->board_info;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_busy = false;
- u8 rssi_adjust_val = 0;
- u8 ps_tdma_byte4_val = 0x50, ps_tdma_byte0_val = 0x51,
- ps_tdma_byte3_val = 0x10;
- s8 wifi_duration_adjust = 0x0;
- static boolean pre_wifi_busy = false;
-
- coex_dm->cur_ps_tdma_on = turn_on;
- coex_dm->cur_ps_tdma = type;
-
-#if BT_8723B_1ANT_ANTDET_ENABLE
-#if BT_8723B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE
- if (board_info->btdm_ant_num_by_ant_det == 2) {
- if (turn_on)
- type = type +
- 100; /* for WiFi RSSI low or BT RSSI low */
- else
- type = 1; /* always translate to TDMA(off,1) for TDMA-off case */
- }
-
-#endif
-#endif
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- if (wifi_busy != pre_wifi_busy) {
- force_exec = true;
- pre_wifi_busy = wifi_busy;
- }
-
- if (!force_exec) {
- if( (coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) &&
- (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma) )
- return;
- }
-
- if (coex_sta->scan_ap_num <= 5) {
- wifi_duration_adjust = 5;
-
- if (coex_sta->a2dp_bit_pool >= 35)
- wifi_duration_adjust = -10;
- else if (coex_sta->a2dp_bit_pool >= 45)
- wifi_duration_adjust = -15;
- } else if (coex_sta->scan_ap_num >= 40) {
- wifi_duration_adjust = -15;
-
- if (coex_sta->a2dp_bit_pool < 35)
- wifi_duration_adjust = -5;
- else if (coex_sta->a2dp_bit_pool < 45)
- wifi_duration_adjust = -10;
- } else if (coex_sta->scan_ap_num >= 20) {
- wifi_duration_adjust = -10;
-
- if (coex_sta->a2dp_bit_pool >= 45)
- wifi_duration_adjust = -15;
- } else {
- wifi_duration_adjust = 0;
-
- if (coex_sta->a2dp_bit_pool >= 35)
- wifi_duration_adjust = -10;
- else if (coex_sta->a2dp_bit_pool >= 45)
- wifi_duration_adjust = -15;
- }
-
- if ((type == 1) || (type == 2) || (type == 9) || (type == 11) ||
- (type == 101)
- || (type == 102) || (type == 109) || (type == 101)) {
- if (!coex_sta->force_lps_on) { /* Native power save TDMA, only for A2DP-only case 1/2/9/11 while wifi noisy threshold > 30 */
- ps_tdma_byte0_val = 0x61; /* no null-pkt */
- ps_tdma_byte3_val = 0x11; /* no tx-pause at BT-slot */
- ps_tdma_byte4_val =
- 0x10; /* 0x778 = d/1 toggle, no dynamic slot */
- } else {
- ps_tdma_byte0_val = 0x51; /* null-pkt */
- ps_tdma_byte3_val = 0x10; /* tx-pause at BT-slot */
- ps_tdma_byte4_val =
- 0x50; /* 0x778 = d/1 toggle, dynamic slot */
- }
- } else if ((type == 3) || (type == 13) || (type == 14) ||
- (type == 103) || (type == 113) || (type == 114)) {
- ps_tdma_byte0_val = 0x51; /* null-pkt */
- ps_tdma_byte3_val = 0x10; /* tx-pause at BT-slot */
- ps_tdma_byte4_val =
- 0x10; /* 0x778 = d/1 toggle, no dynamic slot */
-#if 0
- if (!wifi_busy)
- ps_tdma_byte4_val = ps_tdma_byte4_val |
- 0x1; /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */
-#endif
- } else { /* native power save case */
- ps_tdma_byte0_val = 0x61; /* no null-pkt */
- ps_tdma_byte3_val = 0x11; /* no tx-pause at BT-slot */
- ps_tdma_byte4_val =
- 0x11; /* 0x778 = d/1 toggle, no dynamic slot */
- /* psTdmaByte4Va is not defne for 0x778 = d/1, 1/1 case */
- }
-
- /* if (bt_link_info->slave_role == true) */
- if ((bt_link_info->slave_role == true) && (bt_link_info->a2dp_exist))
- ps_tdma_byte4_val = ps_tdma_byte4_val |
- 0x1; /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */
-
- if (type > 100) {
- ps_tdma_byte0_val = ps_tdma_byte0_val |
- 0x82; /* set antenna control by SW */
- ps_tdma_byte3_val = ps_tdma_byte3_val |
- 0x60; /* set antenna no toggle, control by antenna diversity */
- }
-
-
- if (turn_on) {
- switch (type) {
- default:
- halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x51,
- 0x1a, 0x1a, 0x0, ps_tdma_byte4_val);
- break;
- case 1:
- halbtc8723b1ant_set_fw_pstdma(btcoexist,
- ps_tdma_byte0_val, 0x3a +
- wifi_duration_adjust, 0x03,
- ps_tdma_byte3_val, ps_tdma_byte4_val);
- break;
- case 2:
- halbtc8723b1ant_set_fw_pstdma(btcoexist,
- ps_tdma_byte0_val, 0x2d +
- wifi_duration_adjust, 0x03,
- ps_tdma_byte3_val, ps_tdma_byte4_val);
- break;
- case 3:
- halbtc8723b1ant_set_fw_pstdma(btcoexist,
- ps_tdma_byte0_val, 0x30, 0x03,
- ps_tdma_byte3_val, ps_tdma_byte4_val);
- break;
- case 4:
- halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x93,
- 0x15, 0x3, 0x14, 0x0);
- break;
- case 5:
- halbtc8723b1ant_set_fw_pstdma(btcoexist,
- ps_tdma_byte0_val, 0x1f, 0x3,
- ps_tdma_byte3_val, 0x11);
- break;
- case 6:
- halbtc8723b1ant_set_fw_pstdma(btcoexist,
- ps_tdma_byte0_val, 0x20, 0x3,
- ps_tdma_byte3_val, 0x11);
- break;
- case 7:
- halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x13,
- 0xc, 0x5, 0x0, 0x0);
- break;
- case 8:
- halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x93,
- 0x25, 0x3, 0x10, 0x0);
- break;
- case 9:
- halbtc8723b1ant_set_fw_pstdma(btcoexist,
- ps_tdma_byte0_val, 0x21, 0x3,
- ps_tdma_byte3_val, ps_tdma_byte4_val);
- break;
- case 10:
- halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x13,
- 0xa, 0xa, 0x0, 0x40);
- break;
- case 11:
- halbtc8723b1ant_set_fw_pstdma(btcoexist,
- ps_tdma_byte0_val, 0x21, 0x03,
- ps_tdma_byte3_val, ps_tdma_byte4_val);
- break;
- case 12:
- halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x51,
- 0x0a, 0x0a, 0x0, 0x50);
- break;
- case 13:
- if (coex_sta->scan_ap_num <= 3)
- halbtc8723b1ant_set_fw_pstdma(btcoexist,
- ps_tdma_byte0_val, 0x40, 0x3,
- ps_tdma_byte3_val,
- ps_tdma_byte4_val);
- else
- halbtc8723b1ant_set_fw_pstdma(btcoexist,
- ps_tdma_byte0_val, 0x21, 0x3,
- ps_tdma_byte3_val,
- ps_tdma_byte4_val);
- break;
- case 14:
- if (coex_sta->scan_ap_num <= 3)
- halbtc8723b1ant_set_fw_pstdma(btcoexist,
- 0x51, 0x30, 0x3, 0x10, 0x50);
- else
- halbtc8723b1ant_set_fw_pstdma(btcoexist,
- ps_tdma_byte0_val, 0x21, 0x3,
- ps_tdma_byte3_val,
- ps_tdma_byte4_val);
- break;
- case 15:
- halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x13,
- 0xa, 0x3, 0x8, 0x0);
- break;
- case 16:
- halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x93,
- 0x15, 0x3, 0x10, 0x0);
- break;
- case 18:
- halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x93,
- 0x25, 0x3, 0x10, 0x0);
- break;
- case 20:
- halbtc8723b1ant_set_fw_pstdma(btcoexist,
- ps_tdma_byte0_val, 0x3f, 0x03,
- ps_tdma_byte3_val, 0x10);
- break;
- case 21:
- halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x61,
- 0x25, 0x03, 0x11, 0x11);
- break;
- case 22:
- halbtc8723b1ant_set_fw_pstdma(btcoexist,
- ps_tdma_byte0_val, 0x25, 0x03,
- ps_tdma_byte3_val, 0x10);
- break;
- case 23:
- halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x25, 0x3, 0x31, 0x18);
- break;
- case 24:
- halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x15, 0x3, 0x31, 0x18);
- break;
- case 25:
- halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xe3,
- 0xa, 0x3, 0x31, 0x18);
- break;
- case 26:
- halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xe3,
- 0xa, 0x3, 0x31, 0x18);
- break;
- case 27:
- halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x25, 0x3, 0x31, 0x98);
- break;
- case 28:
- halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x69,
- 0x25, 0x3, 0x31, 0x0);
- break;
- case 29:
- halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xab,
- 0x1a, 0x1a, 0x1, 0x10);
- break;
- case 30:
- halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x51,
- 0x30, 0x3, 0x10, 0x10);
- break;
- case 31:
- halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xd3,
- 0x1a, 0x1a, 0, 0x58);
- break;
- case 32:
- halbtc8723b1ant_set_fw_pstdma(btcoexist,
- ps_tdma_byte0_val, 0x35, 0x3,
- ps_tdma_byte3_val, ps_tdma_byte4_val);
- break;
- case 33:
- halbtc8723b1ant_set_fw_pstdma(btcoexist,
- ps_tdma_byte0_val, 0x35, 0x3,
- ps_tdma_byte3_val, 0x10);
- break;
- case 34:
- halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x53,
- 0x1a, 0x1a, 0x0, 0x10);
- break;
- case 35:
- halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x63,
- 0x1a, 0x1a, 0x0, 0x10);
- break;
- case 36:
- halbtc8723b1ant_set_fw_pstdma(btcoexist, 0xd3,
- 0x12, 0x3, 0x14, 0x50);
- break;
- case 40: /* SoftAP only with no sta associated,BT disable ,TDMA mode for power saving */
- /* here softap mode screen off will cost 70-80mA for phone */
- halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x23,
- 0x18, 0x00, 0x10, 0x24);
- break;
-
- /* for 1-Ant translate to 2-Ant */
- case 101:
- halbtc8723b1ant_set_fw_pstdma(btcoexist,
- ps_tdma_byte0_val, 0x3a +
- wifi_duration_adjust, 0x03,
- ps_tdma_byte3_val, ps_tdma_byte4_val);
- break;
- case 102:
- halbtc8723b1ant_set_fw_pstdma(btcoexist,
- ps_tdma_byte0_val, 0x2d +
- wifi_duration_adjust, 0x03,
- ps_tdma_byte3_val, ps_tdma_byte4_val);
- break;
- case 103:
- /* halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x51, 0x1d, 0x1d, 0x0, ps_tdma_byte4_val); */
- halbtc8723b1ant_set_fw_pstdma(btcoexist,
- ps_tdma_byte0_val, 0x3a, 0x03,
- ps_tdma_byte3_val, ps_tdma_byte4_val);
- break;
- case 105:
- halbtc8723b1ant_set_fw_pstdma(btcoexist,
- ps_tdma_byte0_val, 0x15, 0x3,
- ps_tdma_byte3_val, 0x11);
- break;
- case 106:
- halbtc8723b1ant_set_fw_pstdma(btcoexist,
- ps_tdma_byte0_val, 0x20, 0x3,
- ps_tdma_byte3_val, 0x11);
- break;
- case 109:
- halbtc8723b1ant_set_fw_pstdma(btcoexist,
- ps_tdma_byte0_val, 0x21, 0x3,
- ps_tdma_byte3_val, ps_tdma_byte4_val);
- break;
- case 111:
- halbtc8723b1ant_set_fw_pstdma(btcoexist,
- ps_tdma_byte0_val, 0x21, 0x03,
- ps_tdma_byte3_val, ps_tdma_byte4_val);
- break;
- case 113:
- /* halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x51, 0x12, 0x12, 0x0, ps_tdma_byte4_val); */
- halbtc8723b1ant_set_fw_pstdma(btcoexist,
- ps_tdma_byte0_val, 0x21, 0x3,
- ps_tdma_byte3_val, ps_tdma_byte4_val);
- break;
- case 114:
- halbtc8723b1ant_set_fw_pstdma(btcoexist,
- ps_tdma_byte0_val, 0x21, 0x3,
- ps_tdma_byte3_val, ps_tdma_byte4_val);
- break;
- case 120:
- halbtc8723b1ant_set_fw_pstdma(btcoexist,
- ps_tdma_byte0_val, 0x3f, 0x03,
- ps_tdma_byte3_val, 0x10);
- break;
- case 122:
- halbtc8723b1ant_set_fw_pstdma(btcoexist,
- ps_tdma_byte0_val, 0x25, 0x03,
- ps_tdma_byte3_val, 0x10);
- break;
- case 132:
- halbtc8723b1ant_set_fw_pstdma(btcoexist,
- ps_tdma_byte0_val, 0x25, 0x03,
- ps_tdma_byte3_val, ps_tdma_byte4_val);
- break;
- case 133:
- halbtc8723b1ant_set_fw_pstdma(btcoexist,
- ps_tdma_byte0_val, 0x25, 0x03,
- ps_tdma_byte3_val, 0x11);
- break;
-
- }
- } else {
-
- /* disable PS tdma */
- switch (type) {
- case 8: /* PTA Control */
- halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x8,
- 0x0, 0x0, 0x0, 0x0);
- break;
- case 0:
- default: /* Software control, Antenna at BT side */
- halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x0,
- 0x0, 0x0, 0x0, 0x0);
- break;
- case 1: /* 2-Ant, 0x778=3, antenna control by antenna diversity */
- halbtc8723b1ant_set_fw_pstdma(btcoexist, 0x0,
- 0x0, 0x0, 0x48, 0x0);
- break;
- }
- }
- rssi_adjust_val = 0;
- btcoexist->btc_set(btcoexist,
- BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE, &rssi_adjust_val);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x\n",
- btcoexist->btc_read_4byte(btcoexist, 0x948),
- btcoexist->btc_read_1byte(btcoexist, 0x765),
- btcoexist->btc_read_1byte(btcoexist, 0x67));
- BTC_TRACE(trace_buf);
-
- /* update pre state */
- coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on;
- coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
-}
-
-void halbtc8723b1ant_tdma_duration_adjust_for_acl(IN struct btc_coexist
- *btcoexist, IN u8 wifi_status)
-{
- static s32 up, dn, m, n, wait_count;
- s32 result; /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */
- u8 retry_count = 0, bt_info_ext;
- boolean wifi_busy = false;
-
- if (BT_8723B_1ANT_WIFI_STATUS_CONNECTED_BUSY == wifi_status)
- wifi_busy = true;
- else
- wifi_busy = false;
-
- if ((BT_8723B_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN ==
- wifi_status) ||
- (BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SCAN == wifi_status) ||
- (BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT ==
- wifi_status)) {
- if (coex_dm->cur_ps_tdma != 1 &&
- coex_dm->cur_ps_tdma != 2 &&
- coex_dm->cur_ps_tdma != 3 &&
- coex_dm->cur_ps_tdma != 9) {
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 9);
- coex_dm->ps_tdma_du_adj_type = 9;
-
- up = 0;
- dn = 0;
- m = 1;
- n = 3;
- result = 0;
- wait_count = 0;
- }
- return;
- }
-
- if (!coex_dm->auto_tdma_adjust) {
- coex_dm->auto_tdma_adjust = true;
-
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 2);
- coex_dm->ps_tdma_du_adj_type = 2;
- /* ============ */
- up = 0;
- dn = 0;
- m = 1;
- n = 3;
- result = 0;
- wait_count = 0;
- } else {
- /* accquire the BT TRx retry count from BT_Info byte2 */
- retry_count = coex_sta->bt_retry_cnt;
- bt_info_ext = coex_sta->bt_info_ext;
-
- if ((coex_sta->low_priority_tx) > 1050 ||
- (coex_sta->low_priority_rx) > 1250)
- retry_count++;
-
- result = 0;
- wait_count++;
-
- if (retry_count ==
- 0) { /* no retry in the last 2-second duration */
- up++;
- dn--;
-
- if (dn <= 0)
- dn = 0;
-
- if (up >= n) { /* if retry count during continuous n*2 seconds is 0, enlarge WiFi duration */
- wait_count = 0;
- n = 3;
- up = 0;
- dn = 0;
- result = 1;
- }
- } else if (retry_count <=
- 3) { /* <=3 retry in the last 2-second duration */
- up--;
- dn++;
-
- if (up <= 0)
- up = 0;
-
- if (dn == 2) { /* if continuous 2 retry count(every 2 seconds) >0 and < 3, reduce WiFi duration */
- if (wait_count <= 2)
- m++; /* to avoid loop between the two levels */
- else
- m = 1;
-
- if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */
- m = 20;
-
- n = 3 * m;
- up = 0;
- dn = 0;
- wait_count = 0;
- result = -1;
- }
- } else { /* retry count > 3, once retry count > 3, to reduce WiFi duration */
- if (wait_count == 1)
- m++; /* to avoid loop between the two levels */
- else
- m = 1;
-
- if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */
- m = 20;
-
- n = 3 * m;
- up = 0;
- dn = 0;
- wait_count = 0;
- result = -1;
- }
-
- if (result == -1) {
- /* if( (BT_INFO_8723B_1ANT_A2DP_BASIC_RATE(bt_info_ext)) &&
- ((coex_dm->cur_ps_tdma == 1) ||(coex_dm->cur_ps_tdma == 2)) )
- {
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9);
- coex_dm->ps_tdma_du_adj_type = 9;
- }
- else */ if (coex_dm->cur_ps_tdma == 1) {
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 2);
- coex_dm->ps_tdma_du_adj_type = 2;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 9);
- coex_dm->ps_tdma_du_adj_type = 9;
- } else if (coex_dm->cur_ps_tdma == 9) {
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type = 11;
- }
- } else if (result == 1) {
- /* if( (BT_INFO_8723B_1ANT_A2DP_BASIC_RATE(bt_info_ext)) &&
- ((coex_dm->cur_ps_tdma == 1) ||(coex_dm->cur_ps_tdma == 2)) )
- {
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9);
- coex_dm->ps_tdma_du_adj_type = 9;
- }
- else */ if (coex_dm->cur_ps_tdma == 11) {
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 9);
- coex_dm->ps_tdma_du_adj_type = 9;
- } else if (coex_dm->cur_ps_tdma == 9) {
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 2);
- coex_dm->ps_tdma_du_adj_type = 2;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 1);
- coex_dm->ps_tdma_du_adj_type = 1;
- }
- } else { /* no change */
- /* Bryant Modify
- if(wifi_busy != pre_wifi_busy)
- {
- pre_wifi_busy = wifi_busy;
- halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, true, coex_dm->cur_ps_tdma);
- }
- */
-
- }
-
- if (coex_dm->cur_ps_tdma != 1 &&
- coex_dm->cur_ps_tdma != 2 &&
- coex_dm->cur_ps_tdma != 9 &&
- coex_dm->cur_ps_tdma != 11) {
- /* recover to previous adjust type */
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- coex_dm->ps_tdma_du_adj_type);
- }
- }
-}
-
-void halbtc8723b1ant_ps_tdma_check_for_power_save_state(
- IN struct btc_coexist *btcoexist, IN boolean new_ps_state)
-{
- u8 lps_mode = 0x0;
-
- btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode);
-
- if (lps_mode) { /* already under LPS state */
- if (new_ps_state) {
- /* keep state under LPS, do nothing. */
- } else {
- /* will leave LPS state, turn off psTdma first */
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 8);
- }
- } else { /* NO PS state */
- if (new_ps_state) {
- /* will enter LPS state, turn off psTdma first */
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 8);
- } else {
- /* keep state under NO PS state, do nothing. */
- }
- }
-}
-
-void halbtc8723b1ant_power_save_state(IN struct btc_coexist *btcoexist,
- IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val)
-{
- boolean low_pwr_disable = false;
-
- switch (ps_type) {
- case BTC_PS_WIFI_NATIVE:
- /* recover to original 32k low power setting */
- low_pwr_disable = false;
- btcoexist->btc_set(btcoexist,
- BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS,
- NULL);
- coex_sta->force_lps_on = false;
- break;
- case BTC_PS_LPS_ON:
- halbtc8723b1ant_ps_tdma_check_for_power_save_state(
- btcoexist, true);
- halbtc8723b1ant_lps_rpwm(btcoexist, NORMAL_EXEC,
- lps_val, rpwm_val);
- /* when coex force to enter LPS, do not enter 32k low power. */
- low_pwr_disable = true;
- btcoexist->btc_set(btcoexist,
- BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
- /* power save must executed before psTdma. */
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS,
- NULL);
- coex_sta->force_lps_on = true;
- break;
- case BTC_PS_LPS_OFF:
- halbtc8723b1ant_ps_tdma_check_for_power_save_state(
- btcoexist, false);
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS,
- NULL);
- coex_sta->force_lps_on = false;
- break;
- default:
- break;
- }
-}
-
-void halbtc8723b1ant_action_wifi_only(IN struct btc_coexist *btcoexist)
-{
- halbtc8723b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
- halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8);
- halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, FORCE_EXEC,
- false, false);
-}
-
-void halbtc8723b1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist)
-{
- static u32 bt_disable_cnt = 0;
- boolean bt_active = true, bt_disabled = false;
-
- /* This function check if bt is disabled */
-
- if (coex_sta->high_priority_tx == 0 &&
- coex_sta->high_priority_rx == 0 &&
- coex_sta->low_priority_tx == 0 &&
- coex_sta->low_priority_rx == 0)
- bt_active = false;
- if (coex_sta->high_priority_tx == 0xffff &&
- coex_sta->high_priority_rx == 0xffff &&
- coex_sta->low_priority_tx == 0xffff &&
- coex_sta->low_priority_rx == 0xffff)
- bt_active = false;
- if (bt_active) {
- bt_disable_cnt = 0;
- bt_disabled = false;
- } else {
- bt_disable_cnt++;
- if (bt_disable_cnt >= 2)
- bt_disabled = true;
- }
- if (coex_sta->bt_disabled != bt_disabled) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is from %s to %s!!\n",
- (coex_sta->bt_disabled ? "disabled" : "enabled"),
- (bt_disabled ? "disabled" : "enabled"));
- BTC_TRACE(trace_buf);
-
- coex_sta->bt_disabled = bt_disabled;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
- &bt_disabled);
- if (bt_disabled) {
- halbtc8723b1ant_action_wifi_only(btcoexist);
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS,
- NULL);
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS,
- NULL);
- }
- }
-}
-
-/* *********************************************
- *
- * Non-Software Coex Mechanism start
- *
- * ********************************************* */
-void halbtc8723b1ant_action_bt_whck_test(IN struct btc_coexist *btcoexist)
-{
- halbtc8723b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
-
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC,
- false, false);
- halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-}
-
-void halbtc8723b1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist)
-{
- halbtc8723b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
-
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC,
- false, false);
- halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
-}
-
-void halbtc8723b1ant_action_hs(IN struct btc_coexist *btcoexist)
-{
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
- halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
-}
-
-void halbtc8723b1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_connected = false, ap_enable = false, wifi_busy = false,
- bt_busy = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
- &ap_enable);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
-
- if (coex_sta->bt_abnormal_scan) {
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 33);
- halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
- } else if ((!wifi_connected) && (!coex_sta->wifi_is_high_pri_task)) {
- halbtc8723b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
- NORMAL_EXEC, false, false);
- halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
- } else if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) ||
- (bt_link_info->a2dp_exist)) {
- /* SCO/HID/A2DP busy */
- halbtc8723b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
-
- if (coex_sta->c2h_bt_remote_name_req)
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 33);
- else
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 32);
-
- halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- } else if ((bt_link_info->pan_exist) || (wifi_busy)) {
- halbtc8723b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
-
- if (coex_sta->c2h_bt_remote_name_req)
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 33);
- else
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 32);
-
- halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- } else {
- halbtc8723b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
-
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
- NORMAL_EXEC, false, false);
- halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
-
- }
-}
-
-void halbtc8723b1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist
- *btcoexist, IN u8 wifi_status)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_connected = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
-
- /* tdma and coex table */
-
- if (bt_link_info->sco_exist) {
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
- halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
- } else { /* HID */
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 6);
- halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
- }
-}
-
-void halbtc8723b1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist
- *btcoexist, IN u8 wifi_status)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
- if ((coex_sta->low_priority_rx >= 950) && (!coex_sta->under_ips))
- bt_link_info->slave_role = true;
- else
- bt_link_info->slave_role = false;
-
- if (bt_link_info->hid_only) { /* HID */
- halbtc8723b1ant_action_bt_sco_hid_only_busy(btcoexist,
- wifi_status);
- coex_dm->auto_tdma_adjust = false;
- return;
- } else if (bt_link_info->a2dp_only) { /* A2DP */
- if (BT_8723B_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifi_status) {
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 32);
- halbtc8723b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- coex_dm->auto_tdma_adjust = false;
- } else {
- halbtc8723b1ant_tdma_duration_adjust_for_acl(btcoexist,
- wifi_status);
- halbtc8723b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- coex_dm->auto_tdma_adjust = true;
- }
- } else if (((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) ||
- (bt_link_info->hid_exist && bt_link_info->a2dp_exist &&
- bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13);
- halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- coex_dm->auto_tdma_adjust = false;
- } else if (bt_link_info->hid_exist &&
- bt_link_info->a2dp_exist) { /* HID+A2DP */
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14);
- coex_dm->auto_tdma_adjust = false;
-
- halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- } else if ((bt_link_info->pan_only) || (bt_link_info->hid_exist &&
- bt_link_info->pan_exist)) { /* PAN(OPP,FTP), HID+PAN(OPP,FTP) */
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3);
- halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- coex_dm->auto_tdma_adjust = false;
- } else {
- /* BT no-profile busy (0x9) */
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33);
- halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- coex_dm->auto_tdma_adjust = false;
- }
-}
-
-void halbtc8723b1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist)
-{
- /* power save state */
- halbtc8723b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
-
- /* tdma and coex table */
- halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8);
- halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC,
- false, false);
- halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-}
-
-void halbtc8723b1ant_action_wifi_not_connected_scan(IN struct btc_coexist
- *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
- halbtc8723b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
-
- /* tdma and coex table */
- if (BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
- if (bt_link_info->a2dp_exist) {
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 32);
- halbtc8723b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- } else if (bt_link_info->a2dp_exist &&
- bt_link_info->pan_exist) {
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 22);
- halbtc8723b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- } else {
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 20);
- halbtc8723b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- }
- } else if ((BT_8723B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
- (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY ==
- coex_dm->bt_status)) {
- halbtc8723b1ant_action_bt_sco_hid_only_busy(btcoexist,
- BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SCAN);
- } else {
- /* Bryant Add */
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
- NORMAL_EXEC, false, false);
- halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
- }
-}
-
-void halbtc8723b1ant_action_wifi_not_connected_asso_auth(
- IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
- halbtc8723b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
-
- /* tdma and coex table */
- if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) ||
- (bt_link_info->a2dp_exist)) {
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
- halbtc8723b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4);
- } else if (bt_link_info->pan_exist) {
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
- halbtc8723b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4);
- } else {
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
- NORMAL_EXEC, false, false);
- halbtc8723b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 2);
- }
-}
-
-void halbtc8723b1ant_action_wifi_connected_scan(IN struct btc_coexist
- *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
- halbtc8723b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
-
- /* tdma and coex table */
- if (BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
- if (bt_link_info->a2dp_exist) {
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 32);
- halbtc8723b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- } else if (bt_link_info->a2dp_exist &&
- bt_link_info->pan_exist) {
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 22);
- halbtc8723b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- } else {
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 20);
- halbtc8723b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- }
- } else if ((BT_8723B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
- (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY ==
- coex_dm->bt_status)) {
- halbtc8723b1ant_action_bt_sco_hid_only_busy(btcoexist,
- BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SCAN);
- } else {
- /* Bryant Add */
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
- NORMAL_EXEC, false, false);
- halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
- }
-}
-
-void halbtc8723b1ant_action_wifi_connected_specific_packet(
- IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_busy = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- /* no specific packet process for both WiFi and BT very busy */
- if ((wifi_busy) && ((bt_link_info->pan_exist) ||
- (coex_sta->num_of_profile >= 2)))
- return;
-
- halbtc8723b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
-
- /* tdma and coex table */
- if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist)) {
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
- halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
- } else if (bt_link_info->a2dp_exist) {
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
- halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- } else if (bt_link_info->pan_exist) {
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
- halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- } else {
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
- NORMAL_EXEC, false, false);
- halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
- }
-}
-
-void halbtc8723b1ant_action_wifi_connected(IN struct btc_coexist *btcoexist)
-{
- boolean wifi_busy = false;
- boolean scan = false, link = false, roam = false;
- boolean under_4way = false, ap_enable = false;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CoexForWifiConnect()===>\n");
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
- &under_4way);
- if (under_4way) {
- halbtc8723b1ant_action_wifi_connected_specific_packet(btcoexist);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CoexForWifiConnect(), return for wifi is under 4way<===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
- if (scan || link || roam) {
- if (scan)
- halbtc8723b1ant_action_wifi_connected_scan(btcoexist);
- else
- halbtc8723b1ant_action_wifi_connected_specific_packet(
- btcoexist);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CoexForWifiConnect(), return for wifi is under scan<===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
- &ap_enable);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- /* power save state */
- if (!ap_enable &&
- BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status &&
- !btcoexist->bt_link_info.hid_only) {
- if (btcoexist->bt_link_info.a2dp_only) { /* A2DP */
- if (!wifi_busy)
- halbtc8723b1ant_power_save_state(btcoexist,
- BTC_PS_WIFI_NATIVE, 0x0, 0x0);
- else { /* busy */
- if (coex_sta->scan_ap_num >=
- BT_8723B_1ANT_WIFI_NOISY_THRESH) /* no force LPS, no PS-TDMA, use pure TDMA */
- halbtc8723b1ant_power_save_state(
- btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- else
- halbtc8723b1ant_power_save_state(
- btcoexist, BTC_PS_LPS_ON, 0x50,
- 0x4);
- }
- } else if ((coex_sta->pan_exist == false) &&
- (coex_sta->a2dp_exist == false) &&
- (coex_sta->hid_exist == false))
- halbtc8723b1ant_power_save_state(btcoexist,
- BTC_PS_WIFI_NATIVE, 0x0, 0x0);
- else
- halbtc8723b1ant_power_save_state(btcoexist,
- BTC_PS_LPS_ON, 0x50, 0x4);
- } else
- halbtc8723b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
-
- /* tdma and coex table */
- if (!wifi_busy) {
- if (BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
- halbtc8723b1ant_action_wifi_connected_bt_acl_busy(
- btcoexist,
- BT_8723B_1ANT_WIFI_STATUS_CONNECTED_IDLE);
- } else if ((BT_8723B_1ANT_BT_STATUS_SCO_BUSY ==
- coex_dm->bt_status) ||
- (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY ==
- coex_dm->bt_status)) {
- halbtc8723b1ant_action_bt_sco_hid_only_busy(btcoexist,
- BT_8723B_1ANT_WIFI_STATUS_CONNECTED_IDLE);
- } else {
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 8);
- halbtc8723b1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_PTA, NORMAL_EXEC, false, false);
- /* if ((coex_sta->high_priority_tx) +
- (coex_sta->high_priority_rx) <= 60) */
- halbtc8723b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 2);
- /* else
- halbtc8723b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 7); */
- }
- } else {
- if (BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
- halbtc8723b1ant_action_wifi_connected_bt_acl_busy(
- btcoexist,
- BT_8723B_1ANT_WIFI_STATUS_CONNECTED_BUSY);
- } else if ((BT_8723B_1ANT_BT_STATUS_SCO_BUSY ==
- coex_dm->bt_status) ||
- (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY ==
- coex_dm->bt_status)) {
- halbtc8723b1ant_action_bt_sco_hid_only_busy(btcoexist,
- BT_8723B_1ANT_WIFI_STATUS_CONNECTED_BUSY);
- } else {
- /* halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 8);
- halbtc8723b1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_PTA, NORMAL_EXEC, false, false);
- if ((coex_sta->high_priority_tx) +
- (coex_sta->high_priority_rx) <= 60)
- halbtc8723b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 2);
- else
- halbtc8723b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 7); */
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 32);
- halbtc8723b1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_PTA, NORMAL_EXEC, false, false);
- halbtc8723b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
-
- }
- }
-}
-
-void halbtc8723b1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_connected = false, bt_hs_on = false, wifi_busy = false;
- boolean increase_scan_dev_num = false;
- boolean bt_ctrl_agg_buf_size = false;
- boolean miracast_plus_bt = false;
- u8 agg_buf_size = 5;
- u32 wifi_link_status = 0;
- u32 num_of_wifi_link = 0, wifi_bw;
- u8 iot_peer = BTC_IOT_PEER_UNKNOWN;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism()===>\n");
- BTC_TRACE(trace_buf);
-
- if (btcoexist->manual_control) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- if (btcoexist->stop_coex_dm) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- if (coex_sta->under_ips) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], wifi is under IPS !!!\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- if (coex_sta->bt_whck_test) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is under WHCK TEST!!!\n");
- BTC_TRACE(trace_buf);
- halbtc8723b1ant_action_bt_whck_test(btcoexist);
- return;
- }
-
- if ((BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
- (BT_8723B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
- (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status))
- increase_scan_dev_num = true;
-
- btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM,
- &increase_scan_dev_num);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
- num_of_wifi_link = wifi_link_status >> 16;
-
- if ((num_of_wifi_link >= 2) ||
- (wifi_link_status & WIFI_P2P_GO_CONNECTED)) {
- if (bt_link_info->bt_link_exist) {
- halbtc8723b1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1,
- 0, 1);
- miracast_plus_bt = true;
- } else {
- halbtc8723b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0,
- 0, 0);
- miracast_plus_bt = false;
- }
- btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
- &miracast_plus_bt);
- halbtc8723b1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
- bt_ctrl_agg_buf_size, agg_buf_size);
-
- if (((bt_link_info->a2dp_exist) || (wifi_busy)) &&
- (coex_sta->c2h_bt_inquiry_page))
- halbtc8723b1ant_action_bt_inquiry(btcoexist);
- else
- halbtc8723b1ant_action_wifi_multi_port(btcoexist);
-
- return;
- } else {
- miracast_plus_bt = false;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
- &miracast_plus_bt);
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- if ((bt_link_info->bt_link_exist) && (wifi_connected)) {
- halbtc8723b1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, 0, 1);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer);
-
- /* if(BTC_IOT_PEER_CISCO != iot_peer) */
- if ((BTC_IOT_PEER_CISCO != iot_peer) &&
- (BTC_IOT_PEER_BROADCOM != iot_peer)) {
- if (bt_link_info->sco_exist) /* if (bt_link_info->bt_hi_pri_link_exist) */
- /* halbtc8723b1ant_limited_rx(btcoexist, NORMAL_EXEC, true, false, 0x5); */
- halbtc8723b1ant_limited_rx(btcoexist,
- NORMAL_EXEC, false, false, 0x5);
- else
- halbtc8723b1ant_limited_rx(btcoexist,
- NORMAL_EXEC, false, false, 0x5);
- /* halbtc8723b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, true, 0x8); */
- } else {
- if (bt_link_info->sco_exist)
- halbtc8723b1ant_limited_rx(btcoexist,
- NORMAL_EXEC, true, false, 0x5);
- else {
- if (BTC_WIFI_BW_HT40 == wifi_bw)
- halbtc8723b1ant_limited_rx(btcoexist,
- NORMAL_EXEC, false, true, 0x10);
- else
- halbtc8723b1ant_limited_rx(btcoexist,
- NORMAL_EXEC, false, true, 0x8);
- }
- }
-
- halbtc8723b1ant_sw_mechanism(btcoexist, true);
- } else {
- halbtc8723b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
-
- halbtc8723b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
- 0x5);
-
- halbtc8723b1ant_sw_mechanism(btcoexist, false);
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- if (coex_sta->c2h_bt_inquiry_page) {
- halbtc8723b1ant_action_bt_inquiry(btcoexist);
- return;
- } else if (bt_hs_on) {
- halbtc8723b1ant_action_hs(btcoexist);
- return;
- }
-
-
- if (!wifi_connected) {
- boolean scan = false, link = false, roam = false;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], wifi is non connected-idle !!!\n");
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
-
- if (scan || link || roam) {
- if (scan)
- halbtc8723b1ant_action_wifi_not_connected_scan(
- btcoexist);
- else
- halbtc8723b1ant_action_wifi_not_connected_asso_auth(
- btcoexist);
- } else
- halbtc8723b1ant_action_wifi_not_connected(btcoexist);
- } else /* wifi LPS/Busy */
- halbtc8723b1ant_action_wifi_connected(btcoexist);
-}
-
-void halbtc8723b1ant_init_coex_dm(IN struct btc_coexist *btcoexist)
-{
- /* force to reset coex mechanism */
-
- /* sw all off */
- halbtc8723b1ant_sw_mechanism(btcoexist, false);
-
- /* halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); */
- /* halbtc8723b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); */
-
- coex_sta->pop_event_cnt = 0;
-}
-
-void halbtc8723b1ant_init_hw_config(IN struct btc_coexist *btcoexist,
- IN boolean back_up, IN boolean wifi_only)
-{
- u32 u32tmp = 0; /* , fw_ver; */
- u8 u8tmpa = 0, u8tmpb = 0;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], 1Ant Init HW Config!!\n");
- BTC_TRACE(trace_buf);
-
- psd_scan->ant_det_is_ant_det_available = false;
-
- /* 0xf0[15:12] --> Chip Cut information */
- coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist,
- 0xf1) & 0xf0) >> 4;
-
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8,
- 0x1); /* enable TBTT nterrupt */
-
- /* 0x790[5:0]=0x5 */
- btcoexist->btc_write_1byte(btcoexist, 0x790, 0x5);
-
- /* Enable counter statistics */
- /* btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); //0x76e[3] =1, WLAN_Act control by PTA */
- btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1);
-
-
- /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, 0x1); //BT select s0/s1 is controlled by WiFi */
-
- halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8);
-
- /* Antenna config */
- if (wifi_only)
- halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_WIFI,
- FORCE_EXEC, true, false);
- else
- halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT,
- FORCE_EXEC, true, false);
-
- /* PTA parameter */
- halbtc8723b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
-
- u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x948);
- u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765);
- u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x67);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x\n",
- u32tmp, u8tmpa, u8tmpb);
- BTC_TRACE(trace_buf);
-}
-
-void halbtc8723b1ant_mechanism_switch(IN struct btc_coexist *btcoexist,
- IN boolean bSwitchTo2Antenna)
-{
-
- if (bSwitchTo2Antenna) { /* 1-Ant -> 2-Ant */
- /* un-lock TRx Mask setup for 8723b f-cut */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdd, 0x80, 0x1);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdf, 0x1, 0x1);
- /* WiFi TRx Mask on */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff,
- 0x0);
-
- /* BT TRx Mask un-lock 0x2c[0], 0x30[0] = 1 */
- btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x2c,
- 0x7c45);
- btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x30,
- 0x7c45);
-
- /* BT TRx Mask on */
- btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x3c, 0x1);
-
- halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT,
- FORCE_EXEC, false, false);
- } else {
- /* WiFi TRx Mask on */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff,
- 0x780);
-
- /* lock TRx Mask setup for 8723b f-cut */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdd, 0x80, 0x0);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdf, 0x1, 0x0);
-
- /* BT TRx Mask on */
- btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x3c, 0x15);
-
- /* BT TRx Mask ock 0x2c[0], 0x30[0] = 0 */
- btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x2c,
- 0x7c44);
- btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x30,
- 0x7c44);
-
-
- halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
- FORCE_EXEC, false, false);
- }
-
-}
-
-u32 halbtc8723b1ant_psd_log2base(IN struct btc_coexist *btcoexist, IN u32 val)
-{
- u8 j;
- u32 tmp, tmp2, val_integerd_b = 0, tindex, shiftcount = 0;
- u32 result, val_fractiond_b = 0, table_fraction[21] = {0, 432, 332, 274, 232, 200,
- 174, 151, 132, 115, 100, 86, 74, 62, 51, 42,
- 32, 23, 15, 7, 0
- };
-
- if (val == 0)
- return 0;
-
- tmp = val;
-
- while (1) {
- if (tmp == 1)
- break;
- else {
- tmp = (tmp >> 1);
- shiftcount++;
- }
- }
-
-
- val_integerd_b = shiftcount + 1;
-
- tmp2 = 1;
- for (j = 1; j <= val_integerd_b; j++)
- tmp2 = tmp2 * 2;
-
- tmp = (val * 100) / tmp2;
- tindex = tmp / 5;
-
- if (tindex > 20)
- tindex = 20;
-
- val_fractiond_b = table_fraction[tindex];
-
- result = val_integerd_b * 100 - val_fractiond_b;
-
- return result;
-
-
-}
-
-void halbtc8723b1ant_psd_show_antenna_detect_result(IN struct btc_coexist
- *btcoexist)
-{
- u8 *cli_buf = btcoexist->cli_buf;
- struct btc_board_info *board_info = &btcoexist->board_info;
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n============[Antenna Detection info] ============\n");
- CL_PRINTF(cli_buf);
-
- if (psd_scan->ant_det_result == 1)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (>%d)",
- "Ant Det Result", "2-Antenna (Bad-Isolation)",
- BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION);
- else if (psd_scan->ant_det_result == 2)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (%d~%d)",
- "Ant Det Result", "2-Antenna (Good-Isolation)",
- BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION
- + psd_scan->ant_det_thres_offset,
- BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (%d~%d)",
- "Ant Det Result", "1-Antenna",
- BT_8723B_1ANT_ANTDET_PSDTHRES_1ANT,
- BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION
- + psd_scan->ant_det_thres_offset);
-
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s ",
- "Antenna Detection Finish",
- (board_info->btdm_ant_det_finish
- ? "Yes" : "No"));
- CL_PRINTF(cli_buf);
-
- switch (psd_scan->ant_det_result) {
- case 0:
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "(BT is not available)");
- break;
- case 1: /* 2-Ant bad-isolation */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "(BT is available)");
- break;
- case 2: /* 2-Ant good-isolation */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "(BT is available)");
- break;
- case 3: /* 1-Ant */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "(BT is available)");
- break;
- case 4:
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "(Uncertainty result)");
- break;
- case 5:
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "(Pre-Scan fai)");
- break;
- case 6:
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "(WiFi is Scanning)");
- break;
- case 7:
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "(BT is not idle)");
- break;
- case 8:
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "(Abort by WiFi Scanning)");
- break;
- case 9:
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "(Antenna Init is not ready)");
- break;
- case 10:
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "(BT is Inquiry or page)");
- break;
- case 11:
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "(BT is Disabled)");
- break;
- }
- CL_PRINTF(cli_buf);
-
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
- "Ant Detect Total Count", psd_scan->ant_det_try_count);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
- "Ant Detect Fail Count", psd_scan->ant_det_fail_count);
- CL_PRINTF(cli_buf);
-
- if ((!board_info->btdm_ant_det_finish) &&
- (psd_scan->ant_det_result != 5))
- return;
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "BT Response",
- (psd_scan->ant_det_result ? "ok" : "fail"));
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ms", "BT Tx Time",
- psd_scan->ant_det_bt_tx_time);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "BT Tx Ch",
- psd_scan->ant_det_bt_le_channel);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d",
- "WiFi PSD Cent-Ch/Offset/Span",
- psd_scan->real_cent_freq, psd_scan->real_offset,
- psd_scan->real_span);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d dB",
- "PSD Pre-Scan Peak Value",
- psd_scan->ant_det_pre_psdscan_peak_val / 100);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (<= %d)",
- "PSD Pre-Scan result",
- (psd_scan->ant_det_result != 5 ? "ok" : "fail"),
- BT_8723B_1ANT_ANTDET_PSDTHRES_BACKGROUND
- + psd_scan->ant_det_thres_offset);
- CL_PRINTF(cli_buf);
-
- if (psd_scan->ant_det_result == 5)
- return;
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s dB",
- "PSD Scan Peak Value", psd_scan->ant_det_peak_val);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s MHz",
- "PSD Scan Peak Freq", psd_scan->ant_det_peak_freq);
- CL_PRINTF(cli_buf);
-
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "TFBGA Package",
- (board_info->tfbga_package) ? "Yes" : "No");
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
- "PSD Threshold Offset", psd_scan->ant_det_thres_offset);
- CL_PRINTF(cli_buf);
-
-}
-
-void halbtc8723b1ant_psd_showdata(IN struct btc_coexist *btcoexist)
-{
- u8 *cli_buf = btcoexist->cli_buf;
- u32 delta_freq_per_point;
- u32 freq, freq1, freq2, n = 0, i = 0, j = 0, m = 0, psd_rep1, psd_rep2;
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n\n============[PSD info] (%d)============\n",
- psd_scan->psd_gen_count);
- CL_PRINTF(cli_buf);
-
- if (psd_scan->psd_gen_count == 0) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n No data !!\n");
- CL_PRINTF(cli_buf);
- return;
- }
-
- if (psd_scan->psd_point == 0)
- delta_freq_per_point = 0;
- else
- delta_freq_per_point = psd_scan->psd_band_width /
- psd_scan->psd_point;
-
- /* if (psd_scan->is_psd_show_max_only) */
- if (0) {
- psd_rep1 = psd_scan->psd_max_value / 100;
- psd_rep2 = psd_scan->psd_max_value - psd_rep1 * 100;
-
- freq = ((psd_scan->real_cent_freq - 20) * 1000000 +
- psd_scan->psd_max_value_point * delta_freq_per_point);
- freq1 = freq / 1000000;
- freq2 = freq / 1000 - freq1 * 1000;
-
- if (freq2 < 100)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n Freq = %d.0%d MHz",
- freq1, freq2);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n Freq = %d.%d MHz",
- freq1, freq2);
-
- if (psd_rep2 < 10)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- ", Value = %d.0%d dB, (%d)\n",
- psd_rep1, psd_rep2, psd_scan->psd_max_value);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- ", Value = %d.%d dB, (%d)\n",
- psd_rep1, psd_rep2, psd_scan->psd_max_value);
-
- CL_PRINTF(cli_buf);
- } else {
- m = psd_scan->psd_start_point;
- n = psd_scan->psd_start_point;
- i = 1;
- j = 1;
-
- while (1) {
- do {
- freq = ((psd_scan->real_cent_freq - 20) * 1000000 + m *
- delta_freq_per_point);
- freq1 = freq / 1000000;
- freq2 = freq / 1000 - freq1 * 1000;
-
- if (i == 1) {
- if (freq2 == 0)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n Freq%6d.000", freq1);
- else if (freq2 < 100)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n Freq%6d.0%2d", freq1,
- freq2);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n Freq%6d.%3d", freq1,
- freq2);
- } else if ((i % 8 == 0) ||
- (m == psd_scan->psd_stop_point)) {
- if (freq2 == 0)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%6d.000\n", freq1);
- else if (freq2 < 100)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%6d.0%2d\n", freq1, freq2);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%6d.%3d\n", freq1, freq2);
- } else {
- if (freq2 == 0)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%6d.000", freq1);
- else if (freq2 < 100)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%6d.0%2d", freq1, freq2);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%6d.%3d", freq1, freq2);
- }
-
- i++;
- m++;
- CL_PRINTF(cli_buf);
-
- } while ((i <= 8) && (m <= psd_scan->psd_stop_point));
-
-
- do {
- psd_rep1 = psd_scan->psd_report_max_hold[n] / 100;
- psd_rep2 = psd_scan->psd_report_max_hold[n] - psd_rep1 *
- 100;
-
- if (j == 1) {
- if (psd_rep2 < 10)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n Val %7d.0%d", psd_rep1,
- psd_rep2);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n Val %7d.%d", psd_rep1,
- psd_rep2);
- } else if ((j % 8 == 0) ||
- (n == psd_scan->psd_stop_point)) {
- if (psd_rep2 < 10)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%7d.0%d\n", psd_rep1,
- psd_rep2);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%7d.%d\n", psd_rep1, psd_rep2);
- } else {
- if (psd_rep2 < 10)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%7d.0%d", psd_rep1, psd_rep2);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%7d.%d", psd_rep1, psd_rep2);
- }
-
- j++;
- n++;
- CL_PRINTF(cli_buf);
-
- } while ((j <= 8) && (n <= psd_scan->psd_stop_point));
-
- if ((m > psd_scan->psd_stop_point) ||
- (n > psd_scan->psd_stop_point))
- break;
- else {
- i = 1;
- j = 1;
- }
-
- }
- }
-
-
-}
-
-void halbtc8723b1ant_psd_max_holddata(IN struct btc_coexist *btcoexist,
- IN u32 gen_count)
-{
- u32 i = 0, i_max = 0, val_max = 0;
-
- if (gen_count == 1) {
- memcpy(psd_scan->psd_report_max_hold,
- psd_scan->psd_report,
- BT_8723B_1ANT_ANTDET_PSD_POINTS * sizeof(u32));
-
- psd_scan->psd_max_value_point = 0;
- psd_scan->psd_max_value = 0;
-
- } else {
- for (i = psd_scan->psd_start_point;
- i <= psd_scan->psd_stop_point; i++) {
- if (psd_scan->psd_report[i] >
- psd_scan->psd_report_max_hold[i])
- psd_scan->psd_report_max_hold[i] =
- psd_scan->psd_report[i];
-
- /* search Max Value */
- if (i == psd_scan->psd_start_point) {
- i_max = i;
- val_max = psd_scan->psd_report_max_hold[i];
- } else {
- if (psd_scan->psd_report_max_hold[i] >
- val_max) {
- i_max = i;
- val_max = psd_scan->psd_report_max_hold[i];
- }
- }
-
- }
-
- psd_scan->psd_max_value_point = i_max;
- psd_scan->psd_max_value = val_max;
-
- }
-
-
-}
-
-u32 halbtc8723b1ant_psd_getdata(IN struct btc_coexist *btcoexist, IN u32 point)
-{
- /* reg 0x808[9:0]: FFT data x */
- /* reg 0x808[22]: 0-->1 to get 1 FFT data y */
- /* reg 0x8b4[15:0]: FFT data y report */
-
- u32 val = 0, psd_report = 0;
- int k = 0;
-
- val = btcoexist->btc_read_4byte(btcoexist, 0x808);
-
- val &= 0xffbffc00;
- val |= point;
-
- btcoexist->btc_write_4byte(btcoexist, 0x808, val);
-
- val |= 0x00400000;
- btcoexist->btc_write_4byte(btcoexist, 0x808, val);
-
- while (1) {
- if (k++ > BT_8723B_1ANT_ANTDET_SWEEPPOINT_DELAY)
- break;
- }
-
- val = btcoexist->btc_read_4byte(btcoexist, 0x8b4);
-
- psd_report = val & 0x0000ffff;
-
- return psd_report;
-}
-
-
-boolean halbtc8723b1ant_psd_sweep_point(IN struct btc_coexist *btcoexist,
- IN u32 cent_freq, IN s32 offset, IN u32 span, IN u32 points,
- IN u32 avgnum, IN u32 loopcnt)
-{
- u32 i, val, n, k = 0, j, point_index = 0;
- u32 points1 = 0, psd_report = 0;
- u32 start_p = 0, stop_p = 0, delta_freq_per_point = 156250;
- u32 psd_center_freq = 20 * 10 ^ 6;
- boolean outloop = false, scan , roam, is_sweep_ok = true;
- u8 flag = 0;
- u32 tmp;
- u32 wifi_original_channel = 1;
-
- psd_scan->is_psd_running = true;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx PSD Sweep Start!!\n");
- BTC_TRACE(trace_buf);
-
- do {
- switch (flag) {
- case 0: /* Get PSD parameters */
- default:
-
- psd_scan->psd_band_width = 40 * 1000000;
- psd_scan->psd_point = points;
- psd_scan->psd_start_base = points / 2;
- psd_scan->psd_avg_num = avgnum;
- psd_scan->real_cent_freq = cent_freq;
- psd_scan->real_offset = offset;
- psd_scan->real_span = span;
-
-
- points1 = psd_scan->psd_point;
- delta_freq_per_point = psd_scan->psd_band_width /
- psd_scan->psd_point;
-
- /* PSD point setup */
- val = btcoexist->btc_read_4byte(btcoexist, 0x808);
- val &= 0xffff0fff;
-
- switch (psd_scan->psd_point) {
- case 128:
- val |= 0x0;
- break;
- case 256:
- default:
- val |= 0x00004000;
- break;
- case 512:
- val |= 0x00008000;
- break;
- case 1024:
- val |= 0x0000c000;
- break;
- }
-
- switch (psd_scan->psd_avg_num) {
- case 1:
- val |= 0x0;
- break;
- case 8:
- val |= 0x00001000;
- break;
- case 16:
- val |= 0x00002000;
- break;
- case 32:
- default:
- val |= 0x00003000;
- break;
- }
- btcoexist->btc_write_4byte(btcoexist, 0x808, val);
-
- flag = 1;
- break;
- case 1: /* calculate the PSD point index from freq/offset/span */
- psd_center_freq = psd_scan->psd_band_width / 2 +
- offset * (1000000);
-
- start_p = psd_scan->psd_start_base + (psd_center_freq -
- span * (1000000) / 2) / delta_freq_per_point;
- psd_scan->psd_start_point = start_p -
- psd_scan->psd_start_base;
-
- stop_p = psd_scan->psd_start_base + (psd_center_freq +
- span * (1000000) / 2) / delta_freq_per_point;
- psd_scan->psd_stop_point = stop_p -
- psd_scan->psd_start_base - 1;
-
- flag = 2;
- break;
- case 2: /* set RF channel/BW/Mode */
-
- /* set 3-wire off */
- val = btcoexist->btc_read_4byte(btcoexist, 0x88c);
- val |= 0x00300000;
- btcoexist->btc_write_4byte(btcoexist, 0x88c, val);
-
- /* CCK off */
- val = btcoexist->btc_read_4byte(btcoexist, 0x800);
- val &= 0xfeffffff;
- btcoexist->btc_write_4byte(btcoexist, 0x800, val);
-
- /* store WiFi original channel */
- wifi_original_channel = btcoexist->btc_get_rf_reg(
- btcoexist, BTC_RF_A, 0x18, 0x3ff);
-
- /* Set RF channel */
- if (cent_freq == 2484)
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A,
- 0x18, 0x3ff, 0xe);
- else
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A,
- 0x18, 0x3ff, (cent_freq - 2412) / 5 +
- 1); /* WiFi TRx Mask on */
-
-
- /* Set RF Rx filter corner */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e,
- 0xfffff, 0x3e4);
-
- /* Set TRx mask off */
- /* un-lock TRx Mask setup */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdd,
- 0x80, 0x1);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdf,
- 0x1, 0x1);
-
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1,
- 0xfffff, 0x0);
-
- /* Set RF mode = Rx, RF Gain = 0x8a0 */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x0,
- 0xfffff, 0x308a0);
-
- while (1) {
- if (k++ > BT_8723B_1ANT_ANTDET_SWEEPPOINT_DELAY)
- break;
- }
- flag = 3;
- break;
- case 3:
- psd_scan->psd_gen_count = 0;
- for (j = 1; j <= loopcnt; j++) {
-
- btcoexist->btc_get(btcoexist,
- BTC_GET_BL_WIFI_SCAN, &scan);
- btcoexist->btc_get(btcoexist,
- BTC_GET_BL_WIFI_ROAM, &roam);
-
- if (scan || roam) {
- is_sweep_ok = false;
- break;
- }
- memset(psd_scan->psd_report, 0,
- psd_scan->psd_point * sizeof(u32));
- start_p = psd_scan->psd_start_point +
- psd_scan->psd_start_base;
- stop_p = psd_scan->psd_stop_point +
- psd_scan->psd_start_base + 1;
-
- i = start_p;
- point_index = 0;
-
- while (i < stop_p) {
- if (i >= points1)
- psd_report =
- halbtc8723b1ant_psd_getdata(
- btcoexist, i - points1);
- else
- psd_report =
- halbtc8723b1ant_psd_getdata(
- btcoexist, i);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "Point=%d, psd_raw_data = 0x%08x\n",
- i, psd_report);
- BTC_TRACE(trace_buf);
- if (psd_report == 0)
- tmp = 0;
- else
- /* tmp = 20*log10((double)psd_report); */
- /* 20*log2(x)/log2(10), log2Base return theresult of the psd_report*100 */
- tmp = 6 * halbtc8723b1ant_psd_log2base(
- btcoexist, psd_report);
-
- n = i - psd_scan->psd_start_base;
- psd_scan->psd_report[n] = tmp;
-
-
- halbtc8723b1ant_psd_max_holddata(
- btcoexist, j);
-
- i++;
-
- }
-
- psd_scan->psd_gen_count = j;
- }
-
- flag = 100;
- break;
- case 99: /* error */
-
- outloop = true;
- break;
- case 100: /* recovery */
-
- /* set 3-wire on */
- val = btcoexist->btc_read_4byte(btcoexist, 0x88c);
- val &= 0xffcfffff;
- btcoexist->btc_write_4byte(btcoexist, 0x88c, val);
-
- /* CCK on */
- val = btcoexist->btc_read_4byte(btcoexist, 0x800);
- val |= 0x01000000;
- btcoexist->btc_write_4byte(btcoexist, 0x800, val);
-
- /* PSD off */
- val = btcoexist->btc_read_4byte(btcoexist, 0x808);
- val &= 0xffbfffff;
- btcoexist->btc_write_4byte(btcoexist, 0x808, val);
-
- /* TRx Mask on */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1,
- 0xfffff, 0x780);
-
- /* lock TRx Mask setup */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdd,
- 0x80, 0x0);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdf,
- 0x1, 0x0);
-
- /* Set RF Rx filter corner */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e,
- 0xfffff, 0x0);
-
- /* restore WiFi original channel */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x18,
- 0x3ff, wifi_original_channel);
-
- outloop = true;
- break;
-
- }
-
- } while (!outloop);
-
-
-
- psd_scan->is_psd_running = false;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx PSD Sweep Stop!!\n");
- BTC_TRACE(trace_buf);
- return is_sweep_ok;
-
-}
-
-void halbtc8723b1ant_psd_antenna_detection(IN struct btc_coexist *btcoexist,
- IN u32 bt_tx_time, IN u32 bt_le_channel)
-{
- u32 i = 0;
- u32 wlpsd_cent_freq = 2484, wlpsd_span = 2, wlpsd_sweep_count = 50;
- s32 wlpsd_offset = -4;
- u8 bt_le_ch[13] = {3,6,8,11,13,16,18,21,23,26,28,31,33};
-
- u8 h2c_parameter[3] ={0},u8tmpa,u8tmpb;
-
- u8 state=0;
- boolean outloop = false, bt_resp = false;
- u32 freq, freq1, freq2, psd_rep1, psd_rep2, delta_freq_per_point,
- u32tmp;
- struct btc_board_info *board_info = &btcoexist->board_info;
-
- board_info->btdm_ant_det_finish = false;
- memset(psd_scan->ant_det_peak_val, 0, 16*sizeof(u8));
- memset(psd_scan->ant_det_peak_freq, 0, 16*sizeof(u8));
-
- if (board_info->tfbga_package) /* for TFBGA */
- psd_scan->ant_det_thres_offset = 5;
- else
- psd_scan->ant_det_thres_offset = 0;
-
- do {
- switch (state) {
- case 0:
- if (bt_le_channel == 39)
- wlpsd_cent_freq = 2484;
- else {
- for (i = 1; i <= 13; i++) {
- if (bt_le_ch[i - 1] ==
- bt_le_channel) {
- wlpsd_cent_freq = 2412
- + (i - 1) * 5;
- break;
- }
- }
-
- if (i == 14) {
-
- BTC_SPRINTF(trace_buf,
- BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Abort!!, Invalid LE channel = %d\n ",
- bt_le_channel);
- BTC_TRACE(trace_buf);
- outloop = true;
- break;
- }
- }
-
- wlpsd_sweep_count = bt_tx_time * 238 /
- 100; /* bt_tx_time/0.42 */
- wlpsd_sweep_count = wlpsd_sweep_count / 5;
-
- if (wlpsd_sweep_count % 5 != 0)
- wlpsd_sweep_count = (wlpsd_sweep_count /
- 5 + 1) * 5;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), BT_LETxTime=%d, BT_LECh = %d\n",
- bt_tx_time, bt_le_channel);
- BTC_TRACE(trace_buf);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), wlpsd_cent_freq=%d, wlpsd_offset = %d, wlpsd_span = %d, wlpsd_sweep_count = %d\n",
- wlpsd_cent_freq,
- wlpsd_offset,
- wlpsd_span,
- wlpsd_sweep_count);
- BTC_TRACE(trace_buf);
-
- state = 1;
- break;
- case 1: /* stop coex DM & set antenna path */
- /* Stop Coex DM */
- btcoexist->stop_coex_dm = true;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Stop Coex DM!!\n");
- BTC_TRACE(trace_buf);
-
- /* set native power save */
- halbtc8723b1ant_power_save_state(btcoexist,
- BTC_PS_WIFI_NATIVE, 0x0, 0x0);
-
- /* Set TDMA off, */
- halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC,
- false, 0);
-
- /* Set coex table */
- halbtc8723b1ant_coex_table_with_type(btcoexist,
- FORCE_EXEC, 0);
-
- if (board_info->btdm_ant_pos ==
- BTC_ANTENNA_AT_MAIN_PORT) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna at Main Port\n");
- BTC_TRACE(trace_buf);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna at Aux Port\n");
- BTC_TRACE(trace_buf);
- }
-
- /* Set Antenna path, switch WiFi to un-certain antenna port */
- halbtc8723b1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_BT, FORCE_EXEC, false,
- false);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Set Antenna to BT!!\n");
- BTC_TRACE(trace_buf);
-
- /* Set AFH mask on at WiFi channel 2472MHz +/- 10MHz */
- h2c_parameter[0] = 0x1;
- h2c_parameter[1] = 0xd;
- h2c_parameter[2] = 0x14;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Set AFH on, Cent-Ch= %d, Mask=%d\n",
- h2c_parameter[1],
- h2c_parameter[2]);
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_fill_h2c(btcoexist, 0x66, 3,
- h2c_parameter);
-
- u32tmp = btcoexist->btc_read_4byte(btcoexist,
- 0x948);
- u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765);
- u8tmpb = btcoexist->btc_read_1byte(btcoexist,
- 0x778);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x778=0x%x\n",
- u32tmp, u8tmpa, u8tmpb);
- BTC_TRACE(trace_buf);
-
- state = 2;
- break;
- case 2: /* Pre-sweep background psd */
- if (!halbtc8723b1ant_psd_sweep_point(btcoexist,
- wlpsd_cent_freq, wlpsd_offset, wlpsd_span,
- BT_8723B_1ANT_ANTDET_PSD_POINTS,
- BT_8723B_1ANT_ANTDET_PSD_AVGNUM, 3)) {
- board_info->btdm_ant_det_finish = false;
- board_info->btdm_ant_num_by_ant_det = 1;
- psd_scan->ant_det_result = 8;
- state = 99;
- break;
- }
-
- psd_scan->ant_det_pre_psdscan_peak_val =
- psd_scan->psd_max_value;
-
- if (psd_scan->psd_max_value >
- (BT_8723B_1ANT_ANTDET_PSDTHRES_BACKGROUND
- + psd_scan->ant_det_thres_offset) * 100) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Abort Antenna Detection!! becaus background = %d > thres (%d)\n",
- psd_scan->psd_max_value / 100,
- BT_8723B_1ANT_ANTDET_PSDTHRES_BACKGROUND
- + psd_scan->ant_det_thres_offset);
- BTC_TRACE(trace_buf);
- board_info->btdm_ant_det_finish = false;
- board_info->btdm_ant_num_by_ant_det = 1;
- psd_scan->ant_det_result = 5;
- state = 99;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Start Antenna Detection!! becaus background = %d <= thres (%d)\n",
- psd_scan->psd_max_value / 100,
- BT_8723B_1ANT_ANTDET_PSDTHRES_BACKGROUND
- + psd_scan->ant_det_thres_offset);
- BTC_TRACE(trace_buf);
- state = 3;
- }
- break;
- case 3:
- bt_resp = btcoexist->btc_set_bt_ant_detection(
- btcoexist, (u8)(bt_tx_time & 0xff),
- (u8)(bt_le_channel & 0xff));
-
- if (!halbtc8723b1ant_psd_sweep_point(btcoexist,
- wlpsd_cent_freq, wlpsd_offset,
- wlpsd_span,
- BT_8723B_1ANT_ANTDET_PSD_POINTS,
- BT_8723B_1ANT_ANTDET_PSD_AVGNUM,
- wlpsd_sweep_count)) {
- board_info->btdm_ant_det_finish
- = false;
- board_info->btdm_ant_num_by_ant_det
- = 1;
- psd_scan->ant_det_result = 8;
- state = 99;
- break;
- }
-
- psd_scan->ant_det_psd_scan_peak_val =
- psd_scan->psd_max_value;
- psd_scan->ant_det_psd_scan_peak_freq =
- psd_scan->psd_max_value_point;
- state = 4;
- break;
- case 4:
-
- if (psd_scan->psd_point == 0)
- delta_freq_per_point = 0;
- else
- delta_freq_per_point =
- psd_scan->psd_band_width /
- psd_scan->psd_point;
-
- psd_rep1 = psd_scan->psd_max_value / 100;
- psd_rep2 = psd_scan->psd_max_value - psd_rep1 *
- 100;
-
- freq = ((psd_scan->real_cent_freq - 20) *
- 1000000 + psd_scan->psd_max_value_point
- * delta_freq_per_point);
- freq1 = freq / 1000000;
- freq2 = freq / 1000 - freq1 * 1000;
-
- if (freq2 < 100) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Max Value: Freq = %d.0%d MHz",
- freq1, freq2);
- BTC_TRACE(trace_buf);
- CL_SPRINTF(psd_scan->ant_det_peak_freq,
- BT_8723B_1ANT_ANTDET_BUF_LEN,
- "%d.0%d", freq1, freq2);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Max Value: Freq = %d.%d MHz",
- freq1, freq2);
- BTC_TRACE(trace_buf);
- CL_SPRINTF(psd_scan->ant_det_peak_freq,
- BT_8723B_1ANT_ANTDET_BUF_LEN,
- "%d.%d", freq1, freq2);
- }
-
- if (psd_rep2 < 10) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- ", Value = %d.0%d dB\n",
- psd_rep1, psd_rep2);
- BTC_TRACE(trace_buf);
- CL_SPRINTF(psd_scan->ant_det_peak_val,
- BT_8723B_1ANT_ANTDET_BUF_LEN,
- "%d.0%d", psd_rep1, psd_rep2);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- ", Value = %d.%d dB\n",
- psd_rep1, psd_rep2);
- BTC_TRACE(trace_buf);
- CL_SPRINTF(psd_scan->ant_det_peak_val,
- BT_8723B_1ANT_ANTDET_BUF_LEN,
- "%d.%d", psd_rep1, psd_rep2);
- }
-
- psd_scan->ant_det_is_btreply_available = true;
-
- if (bt_resp == false) {
- psd_scan->ant_det_is_btreply_available =
- false;
- psd_scan->ant_det_result = 0;
- board_info->btdm_ant_det_finish = false;
- board_info->btdm_ant_num_by_ant_det = 1;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), BT Response = Fail\n ");
- BTC_TRACE(trace_buf);
- } else if (psd_scan->psd_max_value >
- (BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION)
- * 100) {
- psd_scan->ant_det_result = 1;
- board_info->btdm_ant_det_finish = true;
- board_info->btdm_ant_num_by_ant_det = 2;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 2-Ant, Bad-Isolation!!\n");
- BTC_TRACE(trace_buf);
- } else if (psd_scan->psd_max_value >
- (BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION
- + psd_scan->ant_det_thres_offset) * 100) {
- psd_scan->ant_det_result = 2;
- board_info->btdm_ant_det_finish = true;
- board_info->btdm_ant_num_by_ant_det = 2;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 2-Ant, Good-Isolation!!\n");
- BTC_TRACE(trace_buf);
- } else if (psd_scan->psd_max_value >
- (BT_8723B_1ANT_ANTDET_PSDTHRES_1ANT) *
- 100) {
- psd_scan->ant_det_result = 3;
- board_info->btdm_ant_det_finish = true;
- board_info->btdm_ant_num_by_ant_det = 1;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 1-Ant!!\n");
- BTC_TRACE(trace_buf);
- } else {
- psd_scan->ant_det_result = 4;
- board_info->btdm_ant_det_finish = false;
- board_info->btdm_ant_num_by_ant_det = 1;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 1-Ant, un-certainity!!\n");
- BTC_TRACE(trace_buf);
- }
-
- state = 99;
- break;
- case 99: /* restore setup */
-
- /* Set AFH mask off at WiFi channel 2472MHz +/- 10MHz */
- h2c_parameter[0] = 0x0;
- h2c_parameter[1] = 0x0;
- h2c_parameter[2] = 0x0;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Set AFH on, Cent-Ch= %d, Mask=%d\n",
- h2c_parameter[1], h2c_parameter[2]);
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_fill_h2c(btcoexist, 0x66, 3,
- h2c_parameter);
-
- /* Set Antenna Path */
- halbtc8723b1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_PTA, FORCE_EXEC, false,
- false);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Set Antenna to PTA\n!!");
- BTC_TRACE(trace_buf);
-
- /* Resume Coex DM */
- btcoexist->stop_coex_dm = false;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Resume Coex DM\n!!");
- BTC_TRACE(trace_buf);
-
- /* stimulate coex running */
- halbtc8723b1ant_run_coexist_mechanism(
- btcoexist);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Stimulate Coex running\n!!");
- BTC_TRACE(trace_buf);
-
- outloop = true;
- break;
- }
-
- } while (!outloop);
-
-
-
-}
-
-void halbtc8723b1ant_psd_antenna_detection_check(IN struct btc_coexist
- *btcoexist)
-{
- static u32 ant_det_count = 0, ant_det_fail_count = 0;
- struct btc_board_info *board_info = &btcoexist->board_info;
-
- boolean scan, roam;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
-
-
- /* psd_scan->ant_det_bt_tx_time = 20; */
- psd_scan->ant_det_bt_tx_time =
- BT_8723B_1ANT_ANTDET_BTTXTIME; /* 0.42ms*50 = 20ms (0.42ms = 1 PSD sweep) */
- psd_scan->ant_det_bt_le_channel = BT_8723B_1ANT_ANTDET_BTTXCHANNEL;
-
- ant_det_count++;
-
- psd_scan->ant_det_try_count = ant_det_count;
-
- if (scan || roam) {
- board_info->btdm_ant_det_finish = false;
- psd_scan->ant_det_result = 6;
- } else if (coex_sta->bt_disabled) {
- board_info->btdm_ant_det_finish = false;
- psd_scan->ant_det_result = 11;
- } else if (coex_sta->num_of_profile >= 1) {
- board_info->btdm_ant_det_finish = false;
- psd_scan->ant_det_result = 7;
- } else if (
- !psd_scan->ant_det_is_ant_det_available) { /* Antenna initial setup is not ready */
- board_info->btdm_ant_det_finish = false;
- psd_scan->ant_det_result = 9;
- } else if (coex_sta->c2h_bt_inquiry_page) {
- board_info->btdm_ant_det_finish = false;
- psd_scan->ant_det_result = 10;
- } else
- halbtc8723b1ant_psd_antenna_detection(btcoexist,
- psd_scan->ant_det_bt_tx_time,
- psd_scan->ant_det_bt_le_channel);
-
- if (!board_info->btdm_ant_det_finish)
- ant_det_fail_count++;
-
- psd_scan->ant_det_fail_count = ant_det_fail_count;
-
-}
-
-
-/* ************************************************************
- * work around function start with wa_halbtc8723b1ant_
- * ************************************************************
- * ************************************************************
- * extern function start with ex_halbtc8723b1ant_
- * ************************************************************ */
-void ex_halbtc8723b1ant_power_on_setting(IN struct btc_coexist *btcoexist)
-{
- struct btc_board_info *board_info = &btcoexist->board_info;
- u8 u8tmp=0x0;
- u16 u16tmp=0x0;
- u32 value;
-
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx Execute 8723b 1-Ant PowerOn Setting xxxxxxxxxxxxxxxx!!\n");
- BTC_TRACE(trace_buf);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "Ant Det Finish = %s, Ant Det Number = %d\n",
- (board_info->btdm_ant_det_finish ? "Yes" : "No"),
- board_info->btdm_ant_num_by_ant_det);
- BTC_TRACE(trace_buf);
-
-
- btcoexist->stop_coex_dm = true;
-
- btcoexist->btc_write_1byte(btcoexist, 0x67, 0x20);
-
- /* enable BB, REG_SYS_FUNC_EN such that we can write 0x948 correctly. */
- u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2);
- btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1));
-
- /* set GRAN_BT = 1 */
- btcoexist->btc_write_1byte(btcoexist, 0x765, 0x18);
- /* set WLAN_ACT = 0 */
- btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4);
-
- /* */
- /* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */
- /* Local setting bit define */
- /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */
- /* BIT1: "0" for internal switch; "1" for external switch */
- /* BIT2: "0" for one antenna; "1" for two antenna */
- /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */
- if(btcoexist->chip_interface == BTC_INTF_USB) {
- /* fixed at S0 for USB interface */
- btcoexist->btc_write_4byte(btcoexist, 0x948, 0x0);
-
- u8tmp |= 0x1; /* antenna inverse */
- btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp);
-
- board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT;
- } else {
- /* for PCIE and SDIO interface, we check efuse 0xc3[6] */
- if (board_info->single_ant_path == 0) {
- /* set to S1 */
- btcoexist->btc_write_4byte(btcoexist, 0x948, 0x280);
- board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;
- value = 1;
- } else if (board_info->single_ant_path == 1) {
- /* set to S0 */
- btcoexist->btc_write_4byte(btcoexist, 0x948, 0x0);
- u8tmp |= 0x1; /* antenna inverse */
- board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT;
- value = 0;
- }
-
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_ANTPOSREGRISTRY_CTRL,
- &value);
-
- if(btcoexist->chip_interface == BTC_INTF_PCI)
- btcoexist->btc_write_local_reg_1byte(btcoexist, 0x384,
- u8tmp);
- else if(btcoexist->chip_interface == BTC_INTF_SDIO)
- btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60,
- u8tmp);
- }
-}
-
-void ex_halbtc8723b1ant_pre_load_firmware(IN struct btc_coexist *btcoexist)
-{
-}
-
-void ex_halbtc8723b1ant_init_hw_config(IN struct btc_coexist *btcoexist,
- IN boolean wifi_only)
-{
- halbtc8723b1ant_init_hw_config(btcoexist, true, wifi_only);
- btcoexist->stop_coex_dm = false;
-}
-
-void ex_halbtc8723b1ant_init_coex_dm(IN struct btc_coexist *btcoexist)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Coex Mechanism Init!!\n");
- BTC_TRACE(trace_buf);
-
- btcoexist->stop_coex_dm = false;
-
- halbtc8723b1ant_init_coex_dm(btcoexist);
-
- halbtc8723b1ant_query_bt_info(btcoexist);
-}
-
-void ex_halbtc8723b1ant_display_coex_info(IN struct btc_coexist *btcoexist)
-{
- struct btc_board_info *board_info = &btcoexist->board_info;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- u8 *cli_buf = btcoexist->cli_buf;
- u8 u8tmp[4], i, bt_info_ext, ps_tdma_case=0;
- u16 u16tmp[4];
- u32 u32tmp[4];
- u32 fa_ofdm, fa_cck;
- u32 fw_ver=0, bt_patch_ver=0;
- static u8 pop_report_in_10s = 0;
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ============[BT Coexist info]============");
- CL_PRINTF(cli_buf);
-
- if(btcoexist->manual_control) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ============[Under Manual Control]============");
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ==========================================");
- CL_PRINTF(cli_buf);
- }
- if(btcoexist->stop_coex_dm) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ============[Coex is STOPPED]============");
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ==========================================");
- CL_PRINTF(cli_buf);
- }
-
- if (psd_scan->ant_det_try_count == 0) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d",
- "Ant PG Num/ Mech/ Pos",
- board_info->pg_ant_num, board_info->btdm_ant_num,
- board_info->btdm_ant_pos);
- CL_PRINTF(cli_buf);
- } else {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %d/ %d/ %d (%d/%d/%d)",
- "Ant PG Num/ Mech(Ant_Det)/ Pos",
- board_info->pg_ant_num, board_info->btdm_ant_num_by_ant_det,
- board_info->btdm_ant_pos,
- psd_scan->ant_det_try_count, psd_scan->ant_det_fail_count,
- psd_scan->ant_det_result);
- CL_PRINTF(cli_buf);
-
- if (board_info->btdm_ant_det_finish) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
- "Ant Det PSD Value",
- psd_scan->ant_det_peak_val);
- CL_PRINTF(cli_buf);
- }
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %d_%x/ 0x%x/ 0x%x(%d)/ %c",
- "Version Coex/ Fw/ Patch/ Cut",
- glcoex_ver_date_8723b_1ant, glcoex_ver_8723b_1ant, fw_ver,
- bt_patch_ver, bt_patch_ver, coex_sta->cut_version + 65);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ",
- "Wifi channel informed to BT",
- coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
- coex_dm->wifi_chnl_info[2]);
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s",
- "WifibHiPri/ Ccklock/ CckEverLock",
- (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"),
- (coex_sta->cck_lock ? "Yes" : "No"),
- (coex_sta->cck_ever_lock ? "Yes" : "No"));
- CL_PRINTF(cli_buf);
-
- /* wifi status */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Wifi Status]============");
- CL_PRINTF(cli_buf);
- btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[BT Status]============");
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
- "BT Abnormal scan",
- (coex_sta->bt_abnormal_scan) ? "Yes" : "No");
- CL_PRINTF(cli_buf);
-
- pop_report_in_10s++;
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d/ %d] ",
- "BT [status/ rssi/ retryCnt/ popCnt]",
- ((coex_sta->bt_disabled)? ("disabled"): ((
- coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan")
- : ((BT_8723B_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
- coex_dm->bt_status) ? "non-connected idle" :
- ((BT_8723B_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)
- ? "connected-idle" : "busy")))),
- coex_sta->bt_rssi, coex_sta->bt_retry_cnt,
- coex_sta->pop_event_cnt);
- CL_PRINTF(cli_buf);
-
- if (pop_report_in_10s >= 5) {
- coex_sta->pop_event_cnt = 0;
- pop_report_in_10s = 0;
- }
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %d / %d / %d / %d / %d / %d",
- "SCO/HID/PAN/A2DP/NameReq/WHQL",
- bt_link_info->sco_exist, bt_link_info->hid_exist,
- bt_link_info->pan_exist, bt_link_info->a2dp_exist,
- coex_sta->c2h_bt_remote_name_req,
- coex_sta->bt_whck_test);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
- "BT Role",
- (bt_link_info->slave_role) ? "Slave" : "Master");
- CL_PRINTF(cli_buf);
-
- bt_info_ext = coex_sta->bt_info_ext;
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d",
- "A2DP Rate/Bitpool",
- (bt_info_ext & BIT(0)) ? "BR" : "EDR", coex_sta->a2dp_bit_pool);
- CL_PRINTF(cli_buf);
-
- for (i = 0; i < BT_INFO_SRC_8723B_1ANT_MAX; i++) {
- if (coex_sta->bt_info_c2h_cnt[i]) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)",
- glbt_info_src_8723b_1ant[i],
- coex_sta->bt_info_c2h[i][0],
- coex_sta->bt_info_c2h[i][1],
- coex_sta->bt_info_c2h[i][2],
- coex_sta->bt_info_c2h[i][3],
- coex_sta->bt_info_c2h[i][4],
- coex_sta->bt_info_c2h[i][5],
- coex_sta->bt_info_c2h[i][6],
- coex_sta->bt_info_c2h_cnt[i]);
- CL_PRINTF(cli_buf);
- }
- }
-
-
- if(btcoexist->manual_control)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[mechanisms] (before Manual)============");
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[mechanisms]============");
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
- "SM[LowPenaltyRA]",
- coex_dm->cur_low_penalty_ra);
- CL_PRINTF(cli_buf);
-
- ps_tdma_case = coex_dm->cur_ps_tdma;
- if (board_info->btdm_ant_num_by_ant_det == 2) {
- if (coex_dm->cur_ps_tdma_on)
- ps_tdma_case = ps_tdma_case +
- 100; /* for WiFi RSSI low or BT RSSI low */
- else
- ps_tdma_case =
- 1; /* always translate to TDMA(off,1) for TDMA-off case */
- }
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (%s,%s)",
- "PS TDMA",
- coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],
- coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],
- coex_dm->ps_tdma_para[4], ps_tdma_case,
- (coex_dm->cur_ps_tdma_on ? "On" : "Off"),
- (coex_dm->auto_tdma_adjust ? "Adj" : "Fix"));
-
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
- "Coex Table Type",
- coex_sta->coex_table_type);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
- "IgnWlanAct",
- coex_dm->cur_ignore_wlan_act);
- CL_PRINTF(cli_buf);
-
- /*
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ", "Latest error condition(should be 0)",
- coex_dm->error_condition);
- CL_PRINTF(cli_buf);
- */
-
- /* Hw setting */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Hw setting]============");
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x",
- "backup ARFR1/ARFR2/RL/AMaxTime",
- coex_dm->backup_arfr_cnt1, coex_dm->backup_arfr_cnt2,
- coex_dm->backup_retry_limit,
- coex_dm->backup_ampdu_max_time);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434);
- u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x",
- "0x430/0x434/0x42a/0x456",
- u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]);
- CL_PRINTF(cli_buf);
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x880);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
- "0x778/0x6cc/0x880[29:25]",
- u8tmp[0], u32tmp[0], (u32tmp[1] & 0x3e000000) >> 25);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x948);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x67);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x764);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x76e);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
- "0x948/ 0x67[5] / 0x764 / 0x76e",
- u32tmp[0], ((u8tmp[0] & 0x20) >> 5), (u32tmp[1] & 0xffff),
- u8tmp[1]);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x92c);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x930);
- u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x944);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
- "0x92c[1:0]/ 0x930[7:0]/0x944[1:0]",
- u32tmp[0] & 0x3, u32tmp[1] & 0xff, u32tmp[2] & 0x3);
- CL_PRINTF(cli_buf);
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x39);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40);
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c);
- u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0x64);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
- "0x38[11]/0x40/0x4c[24:23]/0x64[0]",
- ((u8tmp[0] & 0x8) >> 3), u8tmp[1],
- ((u32tmp[0] & 0x01800000) >> 23), u8tmp[2] & 0x1);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
- "0x550(bcn ctrl)/0x522",
- u32tmp[0], u8tmp[0]);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x49c);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
- "0xc50(dig)/0x49c(null-drop)",
- u32tmp[0] & 0xff, u8tmp[0]);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xda0);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xda4);
- u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0xda8);
- u32tmp[3] = btcoexist->btc_read_4byte(btcoexist, 0xcf0);
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xa5b);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xa5c);
-
- fa_ofdm = ((u32tmp[0] & 0xffff0000) >> 16) + ((u32tmp[1] & 0xffff0000)
- >> 16) + (u32tmp[1] & 0xffff) + (u32tmp[2] & 0xffff) +
- ((u32tmp[3] & 0xffff0000) >> 16) + (u32tmp[3] &
- 0xffff) ;
- fa_cck = (u8tmp[0] << 8) + u8tmp[1];
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
- "OFDM-CCA/OFDM-FA/CCK-FA",
- u32tmp[0] & 0xffff, fa_ofdm, fa_cck);
- CL_PRINTF(cli_buf);
-
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
- "CRC_OK CCK/11g/11n/11n-Agg",
- coex_sta->crc_ok_cck, coex_sta->crc_ok_11g,
- coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_agg);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
- "CRC_Err CCK/11g/11n/11n-Agg",
- coex_sta->crc_err_cck, coex_sta->crc_err_11g,
- coex_sta->crc_err_11n, coex_sta->crc_err_11n_agg);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
- u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
- "0x6c0/0x6c4/0x6c8(coexTable)",
- u32tmp[0], u32tmp[1], u32tmp[2]);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
- "0x770(high-pri rx/tx)",
- coex_sta->high_priority_rx, coex_sta->high_priority_tx);
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
- "0x774(low-pri rx/tx)",
- coex_sta->low_priority_rx, coex_sta->low_priority_tx);
- CL_PRINTF(cli_buf);
-#if (BT_AUTO_REPORT_ONLY_8723B_1ANT == 1)
- /* halbtc8723b1ant_monitor_bt_ctr(btcoexist); */
-#endif
- btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
-}
-
-
-void ex_halbtc8723b1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type)
-{
- if(btcoexist->manual_control || btcoexist->stop_coex_dm)
- return;
-
- if (BTC_IPS_ENTER == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], IPS ENTER notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_ips = true;
-
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT,
- FORCE_EXEC, false, true);
- halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
- } else if (BTC_IPS_LEAVE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], IPS LEAVE notify\n");
- BTC_TRACE(trace_buf);
-
- halbtc8723b1ant_init_hw_config(btcoexist, false, false);
- halbtc8723b1ant_init_coex_dm(btcoexist);
- halbtc8723b1ant_query_bt_info(btcoexist);
-
- coex_sta->under_ips = false;
- }
-}
-
-void ex_halbtc8723b1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type)
-{
- if(btcoexist->manual_control || btcoexist->stop_coex_dm)
- return;
-
- if (BTC_LPS_ENABLE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], LPS ENABLE notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_lps = true;
- } else if (BTC_LPS_DISABLE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], LPS DISABLE notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_lps = false;
- }
-}
-
-void ex_halbtc8723b1ant_scan_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- boolean wifi_connected=false, bt_hs_on=false;
- u32 wifi_link_status=0;
- u32 num_of_wifi_link=0;
- boolean bt_ctrl_agg_buf_size=false;
- u8 agg_buf_size=5;
-
- u8 u8tmpa, u8tmpb;
- u32 u32tmp;
-
- if(btcoexist->manual_control ||
- btcoexist->stop_coex_dm )
- return;
-
- if (BTC_SCAN_START == type) {
- coex_sta->wifi_is_high_pri_task = true;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCAN START notify\n");
- BTC_TRACE(trace_buf);
- psd_scan->ant_det_is_ant_det_available = true;
- halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false,
- 8); /* Force antenna setup for no scan result issue */
- halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
- FORCE_EXEC, false, false);
- u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x948);
- u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765);
- u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x67);
-
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x\n",
- u32tmp, u8tmpa, u8tmpb);
- BTC_TRACE(trace_buf);
- } else {
- coex_sta->wifi_is_high_pri_task = false;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCAN FINISH notify\n");
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
- &coex_sta->scan_ap_num);
- }
-
- if(coex_sta->bt_disabled)
- return;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
-&wifi_connected);
-
- halbtc8723b1ant_query_bt_info(btcoexist);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
- num_of_wifi_link = wifi_link_status>>16;
- if (num_of_wifi_link >= 2) {
- halbtc8723b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
- halbtc8723b1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
- bt_ctrl_agg_buf_size, agg_buf_size);
- halbtc8723b1ant_action_wifi_multi_port(btcoexist);
- return;
- }
-
- if (coex_sta->c2h_bt_inquiry_page) {
- halbtc8723b1ant_action_bt_inquiry(btcoexist);
- return;
- } else if (bt_hs_on) {
- halbtc8723b1ant_action_hs(btcoexist);
- return;
- }
-
- if (BTC_SCAN_START == type) {
- if (!wifi_connected) /* non-connected scan */
- halbtc8723b1ant_action_wifi_not_connected_scan(
- btcoexist);
- else /* wifi is connected */
- halbtc8723b1ant_action_wifi_connected_scan(btcoexist);
- } else if (BTC_SCAN_FINISH == type) {
- if (!wifi_connected) /* non-connected scan */
- halbtc8723b1ant_action_wifi_not_connected(btcoexist);
- else
- halbtc8723b1ant_action_wifi_connected(btcoexist);
- }
-}
-
-void ex_halbtc8723b1ant_connect_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- boolean wifi_connected=false, bt_hs_on=false;
- u32 wifi_link_status=0;
- u32 num_of_wifi_link=0;
- boolean bt_ctrl_agg_buf_size=false;
- u8 agg_buf_size=5;
-
- if(btcoexist->manual_control ||
- btcoexist->stop_coex_dm ||
- coex_sta->bt_disabled )
- return;
-
- if (BTC_ASSOCIATE_START == type) {
- coex_sta->wifi_is_high_pri_task = true;
- psd_scan->ant_det_is_ant_det_available = true;
- halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false,
- 8); /* Force antenna setup for no scan result issue */
- halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
- FORCE_EXEC, false, false);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CONNECT START notify\n");
- BTC_TRACE(trace_buf);
- coex_dm->arp_cnt = 0;
- } else {
- coex_sta->wifi_is_high_pri_task = false;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CONNECT FINISH notify\n");
- BTC_TRACE(trace_buf);
- /* coex_dm->arp_cnt = 0; */
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
- num_of_wifi_link = wifi_link_status >> 16;
- if (num_of_wifi_link >= 2) {
- halbtc8723b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
- halbtc8723b1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
- bt_ctrl_agg_buf_size, agg_buf_size);
- halbtc8723b1ant_action_wifi_multi_port(btcoexist);
- return;
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- if (coex_sta->c2h_bt_inquiry_page) {
- halbtc8723b1ant_action_bt_inquiry(btcoexist);
- return;
- } else if (bt_hs_on) {
- halbtc8723b1ant_action_hs(btcoexist);
- return;
- }
-
- if (BTC_ASSOCIATE_START == type)
- halbtc8723b1ant_action_wifi_not_connected_asso_auth(btcoexist);
- else if (BTC_ASSOCIATE_FINISH == type) {
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- if (!wifi_connected) /* non-connected scan */
- halbtc8723b1ant_action_wifi_not_connected(btcoexist);
- else
- halbtc8723b1ant_action_wifi_connected(btcoexist);
- }
-}
-
-void ex_halbtc8723b1ant_media_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- u8 h2c_parameter[3] ={0};
- u32 wifi_bw;
- u8 wifi_central_chnl;
- boolean wifi_under_b_mode = false;
-
- if(btcoexist->manual_control ||
- btcoexist->stop_coex_dm ||
- coex_sta->bt_disabled )
- return;
-
- if (BTC_MEDIA_CONNECT == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], MEDIA connect notify\n");
- BTC_TRACE(trace_buf);
- halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false,
- 8); /* Force antenna setup for no scan result issue */
- halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
- FORCE_EXEC, false, false);
- psd_scan->ant_det_is_ant_det_available = true;
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
- &wifi_under_b_mode);
-
- /* Set CCK Tx/Rx high Pri except 11b mode */
- if (wifi_under_b_mode) {
- btcoexist->btc_write_1byte(btcoexist, 0x6cd,
- 0x00); /* CCK Tx */
- btcoexist->btc_write_1byte(btcoexist, 0x6cf,
- 0x00); /* CCK Rx */
- } else {
- btcoexist->btc_write_1byte(btcoexist, 0x6cd,
- 0x00); /* CCK Tx */
- btcoexist->btc_write_1byte(btcoexist, 0x6cf,
- 0x10); /* CCK Rx */
- }
-
- coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist,
- 0x430);
- coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist,
- 0x434);
- coex_dm->backup_retry_limit = btcoexist->btc_read_2byte(
- btcoexist, 0x42a);
- coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte(
- btcoexist, 0x456);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], MEDIA disconnect notify\n");
- BTC_TRACE(trace_buf);
- coex_dm->arp_cnt = 0;
-
- btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */
- btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */
-
- coex_sta->cck_ever_lock = false;
- }
-
- /* only 2.4G we need to inform bt the chnl mask */
- btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
- &wifi_central_chnl);
- if ((BTC_MEDIA_CONNECT == type) &&
- (wifi_central_chnl <= 14)) {
- /* h2c_parameter[0] = 0x1; */
- h2c_parameter[0] = 0x0;
- h2c_parameter[1] = wifi_central_chnl;
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- if (BTC_WIFI_BW_HT40 == wifi_bw)
- h2c_parameter[2] = 0x30;
- else
- h2c_parameter[2] = 0x20;
- }
-
- coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
- coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
- coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
-
- btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter);
-}
-
-void ex_halbtc8723b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- boolean bt_hs_on=false;
- u32 wifi_link_status=0;
- u32 num_of_wifi_link=0;
- boolean bt_ctrl_agg_buf_size=false, under_4way=false;
- u8 agg_buf_size=5;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
- &under_4way);
-
- if(btcoexist->manual_control ||
- btcoexist->stop_coex_dm ||
- coex_sta->bt_disabled )
- return;
-
- if (BTC_PACKET_DHCP == type ||
- BTC_PACKET_EAPOL == type ||
- BTC_PACKET_ARP == type) {
- if (BTC_PACKET_ARP == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], specific Packet ARP notify\n");
- BTC_TRACE(trace_buf);
-
- coex_dm->arp_cnt++;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ARP Packet Count = %d\n",
- coex_dm->arp_cnt);
- BTC_TRACE(trace_buf);
-
- if ((coex_dm->arp_cnt >= 10) &&
- (!under_4way)) /* if APR PKT > 10 after connect, do not go to ActionWifiConnectedSpecificPacket(btcoexist) */
- coex_sta->wifi_is_high_pri_task = false;
- else
- coex_sta->wifi_is_high_pri_task = true;
- } else {
- coex_sta->wifi_is_high_pri_task = true;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], specific Packet DHCP or EAPOL notify\n");
- BTC_TRACE(trace_buf);
- }
- } else {
- coex_sta->wifi_is_high_pri_task = false;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], specific Packet [Type = %d] notify\n", type);
- BTC_TRACE(trace_buf);
- }
-
- coex_sta->specific_pkt_period_cnt = 0;
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
- num_of_wifi_link = wifi_link_status >> 16;
- if (num_of_wifi_link >= 2) {
- halbtc8723b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
- halbtc8723b1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
- bt_ctrl_agg_buf_size, agg_buf_size);
- halbtc8723b1ant_action_wifi_multi_port(btcoexist);
- return;
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- if (coex_sta->c2h_bt_inquiry_page) {
- halbtc8723b1ant_action_bt_inquiry(btcoexist);
- return;
- } else if (bt_hs_on) {
- halbtc8723b1ant_action_hs(btcoexist);
- return;
- }
-
- if (BTC_PACKET_DHCP == type ||
- BTC_PACKET_EAPOL == type ||
- ((BTC_PACKET_ARP == type) && (coex_sta->wifi_is_high_pri_task)))
- halbtc8723b1ant_action_wifi_connected_specific_packet(btcoexist);
-}
-
-void ex_halbtc8723b1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
- IN u8 *tmp_buf, IN u8 length)
-{
- u8 bt_info = 0;
- u8 i, rsp_source=0;
- boolean wifi_connected=false;
- boolean bt_busy=false;
- struct btc_board_info *board_info = &btcoexist->board_info;
-
- coex_sta->c2h_bt_info_req_sent = false;
-
- rsp_source = tmp_buf[0]&0xf;
- if(rsp_source >= BT_INFO_SRC_8723B_1ANT_MAX)
- rsp_source = BT_INFO_SRC_8723B_1ANT_WIFI_FW;
- coex_sta->bt_info_c2h_cnt[rsp_source]++;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
-"[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source,
-length);
- BTC_TRACE(trace_buf);
- for (i = 0; i < length; i++) {
- coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
- if (i == 1)
- bt_info = tmp_buf[i];
- if (i == length - 1) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n",
- tmp_buf[i]);
- BTC_TRACE(trace_buf);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ",
- tmp_buf[i]);
- BTC_TRACE(trace_buf);
- }
- }
-
- /* if 0xff, it means BT is under WHCK test */
- if (bt_info == 0xff)
- coex_sta->bt_whck_test = true;
- else
- coex_sta->bt_whck_test = false;
-
- if (BT_INFO_SRC_8723B_1ANT_WIFI_FW != rsp_source) {
- coex_sta->bt_retry_cnt = /* [3:0] */
- coex_sta->bt_info_c2h[rsp_source][2]&0xf;
-
- if (coex_sta->bt_retry_cnt >= 1)
- coex_sta->pop_event_cnt++;
-
- if (coex_sta->bt_info_c2h[rsp_source][2]&0x20)
- coex_sta->c2h_bt_remote_name_req = true;
- else
- coex_sta->c2h_bt_remote_name_req = false;
-
- coex_sta->bt_rssi =
- coex_sta->bt_info_c2h[rsp_source][3]*2-90;
- /* coex_sta->bt_info_c2h[rsp_source][3]*2+10; */
-
- coex_sta->bt_info_ext =
- coex_sta->bt_info_c2h[rsp_source][4];
-
- if (coex_sta->bt_info_c2h[rsp_source][1] == 0x49) {
- coex_sta->a2dp_bit_pool =
- coex_sta->bt_info_c2h[rsp_source][6];
- } else
- coex_sta->a2dp_bit_pool = 0;
-
- coex_sta->bt_tx_rx_mask = (coex_sta->bt_info_c2h[rsp_source][2]
- & 0x40);
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TX_RX_MASK,
- &coex_sta->bt_tx_rx_mask);
-
-#if BT_8723B_1ANT_ANTDET_ENABLE
-#if BT_8723B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE
- if ((board_info->btdm_ant_det_finish) &&
- (board_info->btdm_ant_num_by_ant_det == 2)) {
- if (coex_sta->bt_tx_rx_mask) {
- /* BT into is responded by BT FW and BT RF REG 0x3C != 0x15 => Need to switch BT TRx Mask */
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x1\n");
- BTC_TRACE(trace_buf);
-
- /* BT TRx Mask un-lock 0x2c[0], 0x30[0] = 1 */
- btcoexist->btc_set_bt_reg(btcoexist,
- BTC_BT_REG_RF, 0x2c, 0x7c45);
- btcoexist->btc_set_bt_reg(btcoexist,
- BTC_BT_REG_RF, 0x30, 0x7c45);
-
- btcoexist->btc_set_bt_reg(btcoexist,
- BTC_BT_REG_RF, 0x3c, 0x1);
- }
- } else
-#endif
-#endif
-
- {
- if (!coex_sta->bt_tx_rx_mask) {
- /* BT into is responded by BT FW and BT RF REG 0x3C != 0x15 => Need to switch BT TRx Mask */
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x15\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF,
- 0x3c, 0x15);
-
- /* BT TRx Mask lock 0x2c[0], 0x30[0] = 0 */
- btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF,
- 0x2c, 0x7c44);
- btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF,
- 0x30, 0x7c44);
- }
- }
-
- /* Here we need to resend some wifi info to BT */
- /* because bt is reset and loss of the info. */
- if (coex_sta->bt_info_ext & BIT(1)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- if (wifi_connected)
- ex_halbtc8723b1ant_media_status_notify(
- btcoexist, BTC_MEDIA_CONNECT);
- else
- ex_halbtc8723b1ant_media_status_notify(
- btcoexist, BTC_MEDIA_DISCONNECT);
- }
-
- if (coex_sta->bt_info_ext & BIT(3)) {
- if(!btcoexist->manual_control &&
- !btcoexist->stop_coex_dm) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n");
- BTC_TRACE(trace_buf);
- halbtc8723b1ant_ignore_wlan_act(btcoexist,
- FORCE_EXEC, false);
- }
- } else {
- /* BT already NOT ignore Wlan active, do nothing here. */
- }
-#if(BT_AUTO_REPORT_ONLY_8723B_1ANT == 0)
- if ((coex_sta->bt_info_ext & BIT(4))) {
- /* BT auto report already enabled, do nothing */
- } else
- halbtc8723b1ant_bt_auto_report(btcoexist, FORCE_EXEC,
- true);
-#endif
- }
-
- /* check BIT2 first ==> check if bt is under inquiry or page scan */
- if (bt_info & BT_INFO_8723B_1ANT_B_INQ_PAGE)
- coex_sta->c2h_bt_inquiry_page = true;
- else
- coex_sta->c2h_bt_inquiry_page = false;
-
- coex_sta->num_of_profile = 0;
-
- /* set link exist status */
- if (!(bt_info & BT_INFO_8723B_1ANT_B_CONNECTION)) {
- coex_sta->bt_link_exist = false;
- coex_sta->pan_exist = false;
- coex_sta->a2dp_exist = false;
- coex_sta->hid_exist = false;
- coex_sta->sco_exist = false;
-
- coex_sta->bt_hi_pri_link_exist = false;
- } else { /* connection exists */
- coex_sta->bt_link_exist = true;
- if (bt_info & BT_INFO_8723B_1ANT_B_FTP) {
- coex_sta->pan_exist = true;
- coex_sta->num_of_profile++;
- } else
- coex_sta->pan_exist = false;
- if (bt_info & BT_INFO_8723B_1ANT_B_A2DP) {
- coex_sta->a2dp_exist = true;
- coex_sta->num_of_profile++;
- } else
- coex_sta->a2dp_exist = false;
- if (bt_info & BT_INFO_8723B_1ANT_B_HID) {
- coex_sta->hid_exist = true;
- coex_sta->num_of_profile++;
- } else
- coex_sta->hid_exist = false;
- if (bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO) {
- coex_sta->sco_exist = true;
- coex_sta->num_of_profile++;
- } else
- coex_sta->sco_exist = false;
-
- if ((coex_sta->hid_exist == false) &&
- (coex_sta->c2h_bt_inquiry_page == false) &&
- (coex_sta->sco_exist == false)) {
- if (coex_sta->high_priority_tx +
- coex_sta->high_priority_rx >= 160) {
- coex_sta->hid_exist = true;
- coex_sta->wrong_profile_notification++;
- coex_sta->num_of_profile++;
- bt_info = bt_info | 0x28;
- }
- }
-
- /* Add Hi-Pri Tx/Rx counter to avoid false detection */
- if (((coex_sta->hid_exist) || (coex_sta->sco_exist)) &&
- (coex_sta->high_priority_tx +
- coex_sta->high_priority_rx >= 160)
- && (!coex_sta->c2h_bt_inquiry_page))
- coex_sta->bt_hi_pri_link_exist = true;
-
- if ((bt_info & BT_INFO_8723B_1ANT_B_ACL_BUSY) &&
- (coex_sta->num_of_profile == 0)) {
- if (coex_sta->low_priority_tx +
- coex_sta->low_priority_rx >= 160) {
- coex_sta->pan_exist = true;
- coex_sta->num_of_profile++;
- coex_sta->wrong_profile_notification++;
- bt_info = bt_info | 0x88;
- }
- }
- }
-
- halbtc8723b1ant_update_bt_link_info(btcoexist);
-
- bt_info = bt_info &
- 0x1f; /* mask profile bit for connect-ilde identification ( for CSR case: A2DP idle --> 0x41) */
-
- if (!(bt_info & BT_INFO_8723B_1ANT_B_CONNECTION))
- coex_dm->bt_status = BT_8723B_1ANT_BT_STATUS_NON_CONNECTED_IDLE;
- else if (bt_info ==
- BT_INFO_8723B_1ANT_B_CONNECTION) /* connection exists but no busy */
- coex_dm->bt_status = BT_8723B_1ANT_BT_STATUS_CONNECTED_IDLE;
- else if ((bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO) ||
- (bt_info & BT_INFO_8723B_1ANT_B_SCO_BUSY))
- coex_dm->bt_status = BT_8723B_1ANT_BT_STATUS_SCO_BUSY;
- else if (bt_info & BT_INFO_8723B_1ANT_B_ACL_BUSY) {
- if(BT_8723B_1ANT_BT_STATUS_ACL_BUSY != coex_dm->bt_status)
- coex_dm->auto_tdma_adjust = false;
- coex_dm->bt_status = BT_8723B_1ANT_BT_STATUS_ACL_BUSY;
- } else
- coex_dm->bt_status = BT_8723B_1ANT_BT_STATUS_MAX;
-
- if( (BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
- (BT_8723B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
- (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status) )
- bt_busy = true;
- else
- bt_busy = false;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
-
- halbtc8723b1ant_run_coexist_mechanism(btcoexist);
-}
-
-void ex_halbtc8723b1ant_rf_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- u32 u32tmp;
- u8 u8tmpa,u8tmpb, u8tmpc;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n");
- BTC_TRACE(trace_buf);
-
- if (BTC_RF_ON == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RF is turned ON!!\n");
- BTC_TRACE(trace_buf);
- btcoexist->stop_coex_dm = false;
- } else if (BTC_RF_OFF == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RF is turned OFF!!\n");
- BTC_TRACE(trace_buf);
-
- halbtc8723b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
-0x0, 0x0);
- halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
- halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT,
-FORCE_EXEC, false, true);
-
- halbtc8723b1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
- btcoexist->stop_coex_dm = true;
-
- u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x948);
- u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765);
- u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x67);
- u8tmpc = btcoexist->btc_read_1byte(btcoexist, 0x76e);
-
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x, 0x76e=0x%x\n",
- u32tmp, u8tmpa, u8tmpb, u8tmpc);
- BTC_TRACE(trace_buf);
-
- }
-}
-
-void ex_halbtc8723b1ant_halt_notify(IN struct btc_coexist *btcoexist)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n");
- BTC_TRACE(trace_buf);
-
- halbtc8723b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
- halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
- halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, FORCE_EXEC,
- false, true);
-
- halbtc8723b1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
-
- ex_halbtc8723b1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
-
- btcoexist->stop_coex_dm = true;
-}
-
-void ex_halbtc8723b1ant_pnp_notify(IN struct btc_coexist *btcoexist,
- IN u8 pnp_state)
-{
- if (BTC_WIFI_PNP_SLEEP == pnp_state) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Pnp notify to SLEEP\n");
- BTC_TRACE(trace_buf);
-
- halbtc8723b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- halbtc8723b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT,
- FORCE_EXEC, false, true);
- halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
-
- /* Sinda 20150819, workaround for driver skip leave IPS/LPS to speed up sleep time. */
- /* Driver do not leave IPS/LPS when driver is going to sleep, so BTCoexistence think wifi is still under IPS/LPS */
- /* BT should clear UnderIPS/UnderLPS state to avoid mismatch state after wakeup. */
- coex_sta->under_ips = false;
- coex_sta->under_lps = false;
- btcoexist->stop_coex_dm = true;
- } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Pnp notify to WAKE UP\n");
- BTC_TRACE(trace_buf);
- btcoexist->stop_coex_dm = false;
- halbtc8723b1ant_init_hw_config(btcoexist, false, false);
- halbtc8723b1ant_init_coex_dm(btcoexist);
- halbtc8723b1ant_query_bt_info(btcoexist);
- }
-}
-
-void ex_halbtc8723b1ant_coex_dm_reset(IN struct btc_coexist *btcoexist)
-{
-
- halbtc8723b1ant_init_hw_config(btcoexist, false, false);
- /* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); */
- /* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x2, 0xfffff, 0x0); */
- halbtc8723b1ant_init_coex_dm(btcoexist);
-}
-
-void ex_halbtc8723b1ant_periodical(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ==========================Periodical===========================\n");
- BTC_TRACE(trace_buf);
-
-#if(BT_AUTO_REPORT_ONLY_8723B_1ANT == 0)
- halbtc8723b1ant_query_bt_info(btcoexist);
- halbtc8723b1ant_monitor_bt_enable_disable(btcoexist);
-#else
- halbtc8723b1ant_monitor_bt_ctr(btcoexist);
- halbtc8723b1ant_monitor_wifi_ctr(btcoexist);
-#if BT_8723B_1ANT_ANTDET_ENABLE
- halbtc8723b1ant_monitor_bt_enable_disable(btcoexist);
-#endif
-
- if ((coex_sta->high_priority_tx + coex_sta->high_priority_rx < 50) &&
- (bt_link_info->hid_exist == true))
- bt_link_info->hid_exist = false;
-
- if( halbtc8723b1ant_is_wifi_status_changed(btcoexist) ||
- coex_dm->auto_tdma_adjust )
- halbtc8723b1ant_run_coexist_mechanism(btcoexist);
-
- coex_sta->specific_pkt_period_cnt++;
-
- /* sample to set bt to execute Ant detection */
- /* btcoexist->btc_set_bt_ant_detection(btcoexist, 20, 14);
- *
- if (psd_scan->is_ant_det_enable)
- {
- if (psd_scan->psd_gen_count > psd_scan->realseconds)
- psd_scan->psd_gen_count = 0;
-
- halbtc8723b1ant_antenna_detection(btcoexist, psd_scan->realcent_freq, psd_scan->realoffset, psd_scan->realspan, psd_scan->realseconds);
- psd_scan->psd_gen_total_count +=2;
- psd_scan->psd_gen_count += 2;
- }
- */
-#endif
-}
-
-void ex_halbtc8723b1ant_antenna_detection(IN struct btc_coexist *btcoexist,
- IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
-{
-#if BT_8723B_1ANT_ANTDET_ENABLE
- static u32 ant_det_count = 0, ant_det_fail_count = 0;
- struct btc_board_info *board_info = &btcoexist->board_info;
- /*boolean scan, roam;*/
-
- if (seconds == 0) {
- psd_scan->ant_det_try_count = 0;
- psd_scan->ant_det_fail_count = 0;
- ant_det_count = 0;
- ant_det_fail_count = 0;
- board_info->btdm_ant_det_finish = false;
- board_info->btdm_ant_num_by_ant_det = 1;
- return;
- }
-
- if (!board_info->btdm_ant_det_finish) {
- psd_scan->ant_det_inteval_count =
- psd_scan->ant_det_inteval_count + 2;
-
- if (psd_scan->ant_det_inteval_count >=
- BT_8723B_1ANT_ANTDET_RETRY_INTERVAL) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Timer is up, Try Detect!!\n");
- BTC_TRACE(trace_buf);
- halbtc8723b1ant_psd_antenna_detection_check(btcoexist);
-
- if (board_info->btdm_ant_det_finish) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Success!!\n");
- BTC_TRACE(trace_buf);
-#if 1
- if (board_info->btdm_ant_num_by_ant_det == 2)
- halbtc8723b1ant_mechanism_switch(
- btcoexist, true);
- else
- halbtc8723b1ant_mechanism_switch(
- btcoexist, false);
-#endif
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Fail!!\n");
- BTC_TRACE(trace_buf);
- }
- psd_scan->ant_det_inteval_count = 0;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Timer is not up! (%d)\n",
- psd_scan->ant_det_inteval_count);
- BTC_TRACE(trace_buf);
- }
-
- }
-#endif
-
-
-/*
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
-
-
- psd_scan->ant_det_bt_tx_time = seconds;
- psd_scan->ant_det_bt_le_channel = cent_freq;
-
- if (seconds == 0)
- {
- psd_scan->ant_det_try_count = 0;
- psd_scan->ant_det_fail_count = 0;
- ant_det_count = 0;
- ant_det_fail_count = 0;
- board_info->btdm_ant_det_finish = false;
- board_info->btdm_ant_num_by_ant_det = 1;
- return;
- }
- else
- {
- ant_det_count++;
-
- psd_scan->ant_det_try_count = ant_det_count;
-
- if (scan ||roam)
- {
- board_info->btdm_ant_det_finish = false;
- psd_scan->ant_det_result = 6;
- }
- else if (coex_sta->num_of_profile >= 1)
- {
- board_info->btdm_ant_det_finish = false;
- psd_scan->ant_det_result = 7;
- }
- else if (!psd_scan->ant_det_is_ant_det_available)
- {
- board_info->btdm_ant_det_finish = false;
- psd_scan->ant_det_result = 9;
- }
- else if (coex_sta->c2h_bt_inquiry_page)
- {
- board_info->btdm_ant_det_finish = false;
- psd_scan->ant_det_result = 10;
- }
- else
- {
-
- }
-
- if (!board_info->btdm_ant_det_finish)
- ant_det_fail_count++;
-
- psd_scan->ant_det_fail_count = ant_det_fail_count;
- }
-*/
-}
-
-
-void ex_halbtc8723b1ant_display_ant_detection(IN struct btc_coexist *btcoexist)
-{
-#if BT_8723B_1ANT_ANTDET_ENABLE
- struct btc_board_info *board_info = &btcoexist->board_info;
-
- if (psd_scan->ant_det_try_count != 0) {
- halbtc8723b1ant_psd_show_antenna_detect_result(btcoexist);
-
- if (board_info->btdm_ant_det_finish)
- halbtc8723b1ant_psd_showdata(btcoexist);
- return;
- }
-#endif
-
- /* halbtc8723b1ant_show_psd_data(btcoexist); */
-}
-
-#endif
-
-#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */
diff --git a/hal/btc/HalBtc8723b1Ant.h b/hal/btc/HalBtc8723b1Ant.h
deleted file mode 100644
index b0cd79d..0000000
--- a/hal/btc/HalBtc8723b1Ant.h
+++ /dev/null
@@ -1,288 +0,0 @@
-
-#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
-
-#if (RTL8723B_SUPPORT == 1)
-/* *******************************************
- * The following is for 8723B 1ANT BT Co-exist definition
- * ******************************************* */
-#define BT_AUTO_REPORT_ONLY_8723B_1ANT 1
-
-#define BT_INFO_8723B_1ANT_B_FTP BIT(7)
-#define BT_INFO_8723B_1ANT_B_A2DP BIT(6)
-#define BT_INFO_8723B_1ANT_B_HID BIT(5)
-#define BT_INFO_8723B_1ANT_B_SCO_BUSY BIT(4)
-#define BT_INFO_8723B_1ANT_B_ACL_BUSY BIT(3)
-#define BT_INFO_8723B_1ANT_B_INQ_PAGE BIT(2)
-#define BT_INFO_8723B_1ANT_B_SCO_ESCO BIT(1)
-#define BT_INFO_8723B_1ANT_B_CONNECTION BIT(0)
-
-#define BT_INFO_8723B_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \
- (((_BT_INFO_EXT_&BIT(0))) ? true : false)
-
-#define BTC_RSSI_COEX_THRESH_TOL_8723B_1ANT 2
-
-#define BT_8723B_1ANT_WIFI_NOISY_THRESH 50 /* 30 //max: 255 */
-
-/* for Antenna detection */
-#define BT_8723B_1ANT_ANTDET_PSDTHRES_BACKGROUND 50
-#define BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION 70
-#define BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION 55
-#define BT_8723B_1ANT_ANTDET_PSDTHRES_1ANT 32
-#define BT_8723B_1ANT_ANTDET_RETRY_INTERVAL 10 /* retry timer if ant det is fail, unit: second */
-#define BT_8723B_1ANT_ANTDET_SWEEPPOINT_DELAY 40000
-#define BT_8723B_1ANT_ANTDET_ENABLE 1
-#define BT_8723B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE 1
-#define BT_8723B_1ANT_ANTDET_BTTXTIME 100
-#define BT_8723B_1ANT_ANTDET_BTTXCHANNEL 39
-
-enum bt_info_src_8723b_1ant {
- BT_INFO_SRC_8723B_1ANT_WIFI_FW = 0x0,
- BT_INFO_SRC_8723B_1ANT_BT_RSP = 0x1,
- BT_INFO_SRC_8723B_1ANT_BT_ACTIVE_SEND = 0x2,
- BT_INFO_SRC_8723B_1ANT_MAX
-};
-
-enum bt_8723b_1ant_bt_status {
- BT_8723B_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
- BT_8723B_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
- BT_8723B_1ANT_BT_STATUS_INQ_PAGE = 0x2,
- BT_8723B_1ANT_BT_STATUS_ACL_BUSY = 0x3,
- BT_8723B_1ANT_BT_STATUS_SCO_BUSY = 0x4,
- BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
- BT_8723B_1ANT_BT_STATUS_MAX
-};
-
-enum bt_8723b_1ant_wifi_status {
- BT_8723B_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0,
- BT_8723B_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1,
- BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2,
- BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT = 0x3,
- BT_8723B_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4,
- BT_8723B_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5,
- BT_8723B_1ANT_WIFI_STATUS_MAX
-};
-
-enum bt_8723b_1ant_coex_algo {
- BT_8723B_1ANT_COEX_ALGO_UNDEFINED = 0x0,
- BT_8723B_1ANT_COEX_ALGO_SCO = 0x1,
- BT_8723B_1ANT_COEX_ALGO_HID = 0x2,
- BT_8723B_1ANT_COEX_ALGO_A2DP = 0x3,
- BT_8723B_1ANT_COEX_ALGO_A2DP_PANHS = 0x4,
- BT_8723B_1ANT_COEX_ALGO_PANEDR = 0x5,
- BT_8723B_1ANT_COEX_ALGO_PANHS = 0x6,
- BT_8723B_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
- BT_8723B_1ANT_COEX_ALGO_PANEDR_HID = 0x8,
- BT_8723B_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
- BT_8723B_1ANT_COEX_ALGO_HID_A2DP = 0xa,
- BT_8723B_1ANT_COEX_ALGO_MAX = 0xb,
-};
-
-struct coex_dm_8723b_1ant {
- /* hw setting */
- u8 pre_ant_pos_type;
- u8 cur_ant_pos_type;
- /* fw mechanism */
- boolean cur_ignore_wlan_act;
- boolean pre_ignore_wlan_act;
- u8 pre_ps_tdma;
- u8 cur_ps_tdma;
- u8 ps_tdma_para[5];
- u8 ps_tdma_du_adj_type;
- boolean auto_tdma_adjust;
- boolean pre_ps_tdma_on;
- boolean cur_ps_tdma_on;
- boolean pre_bt_auto_report;
- boolean cur_bt_auto_report;
- u8 pre_lps;
- u8 cur_lps;
- u8 pre_rpwm;
- u8 cur_rpwm;
-
- /* sw mechanism */
- boolean pre_low_penalty_ra;
- boolean cur_low_penalty_ra;
- u32 pre_val0x6c0;
- u32 cur_val0x6c0;
- u32 pre_val0x6c4;
- u32 cur_val0x6c4;
- u32 pre_val0x6c8;
- u32 cur_val0x6c8;
- u8 pre_val0x6cc;
- u8 cur_val0x6cc;
-
- u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */
- u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */
- u16 backup_retry_limit;
- u8 backup_ampdu_max_time;
-
- /* algorithm related */
- u8 bt_status;
- u8 wifi_chnl_info[3];
-
- u32 pre_ra_mask;
- u32 cur_ra_mask;
- u8 pre_arfr_type;
- u8 cur_arfr_type;
- u8 pre_retry_limit_type;
- u8 cur_retry_limit_type;
- u8 pre_ampdu_time_type;
- u8 cur_ampdu_time_type;
- u32 arp_cnt;
-
- u8 error_condition;
-};
-
-struct coex_sta_8723b_1ant {
- boolean bt_disabled;
- boolean bt_link_exist;
- boolean sco_exist;
- boolean a2dp_exist;
- boolean hid_exist;
- boolean pan_exist;
- boolean bt_hi_pri_link_exist;
- u8 num_of_profile;
- boolean bt_abnormal_scan;
-
- boolean under_lps;
- boolean under_ips;
- u32 specific_pkt_period_cnt;
- u32 high_priority_tx;
- u32 high_priority_rx;
- u32 low_priority_tx;
- u32 low_priority_rx;
- s8 bt_rssi;
- boolean bt_tx_rx_mask;
- boolean c2h_bt_info_req_sent;
- u8 bt_info_c2h[BT_INFO_SRC_8723B_1ANT_MAX][10];
- u32 bt_info_c2h_cnt[BT_INFO_SRC_8723B_1ANT_MAX];
- boolean bt_whck_test;
- boolean c2h_bt_inquiry_page;
- boolean c2h_bt_remote_name_req;
- boolean wifi_is_high_pri_task; /* Add for win8.1 page out issue */
- u8 bt_retry_cnt;
- u8 bt_info_ext;
- u32 pop_event_cnt;
- u8 scan_ap_num;
-
- u32 crc_ok_cck;
- u32 crc_ok_11g;
- u32 crc_ok_11n;
- u32 crc_ok_11n_agg;
-
- u32 crc_err_cck;
- u32 crc_err_11g;
- u32 crc_err_11n;
- u32 crc_err_11n_agg;
-
- boolean cck_lock;
- boolean pre_ccklock;
- boolean cck_ever_lock;
- u8 coex_table_type;
-
- boolean force_lps_on;
- u32 wrong_profile_notification;
-
- u8 a2dp_bit_pool;
- u8 cut_version;
-};
-
-#define BT_8723B_1ANT_ANTDET_PSD_POINTS 256 /* MAX:1024 */
-#define BT_8723B_1ANT_ANTDET_PSD_AVGNUM 1 /* MAX:3 */
-#define BT_8723B_1ANT_ANTDET_BUF_LEN 16
-
-struct psdscan_sta_8723b_1ant {
-
- u32 ant_det_bt_le_channel; /* BT LE Channel ex:2412 */
- u32 ant_det_bt_tx_time;
- u32 ant_det_pre_psdscan_peak_val;
- boolean ant_det_is_ant_det_available;
- u32 ant_det_psd_scan_peak_val;
- boolean ant_det_is_btreply_available;
- u32 ant_det_psd_scan_peak_freq;
-
- u8 ant_det_result;
- u8 ant_det_peak_val[BT_8723B_1ANT_ANTDET_BUF_LEN];
- u8 ant_det_peak_freq[BT_8723B_1ANT_ANTDET_BUF_LEN];
- u32 ant_det_try_count;
- u32 ant_det_fail_count;
- u32 ant_det_inteval_count;
- u32 ant_det_thres_offset;
-
- u32 real_cent_freq;
- s32 real_offset;
- u32 real_span;
-
- u32 psd_band_width; /* unit: Hz */
- u32 psd_point; /* 128/256/512/1024 */
- u32 psd_report[1024]; /* unit:dB (20logx), 0~255 */
- u32 psd_report_max_hold[1024]; /* unit:dB (20logx), 0~255 */
- u32 psd_start_point;
- u32 psd_stop_point;
- u32 psd_max_value_point;
- u32 psd_max_value;
- u32 psd_start_base;
- u32 psd_avg_num; /* 1/8/16/32 */
- u32 psd_gen_count;
- boolean is_psd_running;
- boolean is_psd_show_max_only;
-};
-
-/* *******************************************
- * The following is interface which will notify coex module.
- * ******************************************* */
-void ex_halbtc8723b1ant_power_on_setting(IN struct btc_coexist *btcoexist);
-void ex_halbtc8723b1ant_pre_load_firmware(IN struct btc_coexist *btcoexist);
-void ex_halbtc8723b1ant_init_hw_config(IN struct btc_coexist *btcoexist,
- IN boolean wifi_only);
-void ex_halbtc8723b1ant_init_coex_dm(IN struct btc_coexist *btcoexist);
-void ex_halbtc8723b1ant_ips_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8723b1ant_lps_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8723b1ant_scan_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8723b1ant_connect_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8723b1ant_media_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8723b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8723b1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
- IN u8 *tmp_buf, IN u8 length);
-void ex_halbtc8723b1ant_rf_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8723b1ant_halt_notify(IN struct btc_coexist *btcoexist);
-void ex_halbtc8723b1ant_pnp_notify(IN struct btc_coexist *btcoexist,
- IN u8 pnp_state);
-void ex_halbtc8723b1ant_coex_dm_reset(IN struct btc_coexist *btcoexist);
-void ex_halbtc8723b1ant_periodical(IN struct btc_coexist *btcoexist);
-void ex_halbtc8723b1ant_display_coex_info(IN struct btc_coexist *btcoexist);
-void ex_halbtc8723b1ant_antenna_detection(IN struct btc_coexist *btcoexist,
- IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds);
-
-void ex_halbtc8723b1ant_display_ant_detection(IN struct btc_coexist *btcoexist);
-
-#else
-#define ex_halbtc8723b1ant_power_on_setting(btcoexist)
-#define ex_halbtc8723b1ant_pre_load_firmware(btcoexist)
-#define ex_halbtc8723b1ant_init_hw_config(btcoexist, wifi_only)
-#define ex_halbtc8723b1ant_init_coex_dm(btcoexist)
-#define ex_halbtc8723b1ant_ips_notify(btcoexist, type)
-#define ex_halbtc8723b1ant_lps_notify(btcoexist, type)
-#define ex_halbtc8723b1ant_scan_notify(btcoexist, type)
-#define ex_halbtc8723b1ant_connect_notify(btcoexist, type)
-#define ex_halbtc8723b1ant_media_status_notify(btcoexist, type)
-#define ex_halbtc8723b1ant_specific_packet_notify(btcoexist, type)
-#define ex_halbtc8723b1ant_bt_info_notify(btcoexist, tmp_buf, length)
-#define ex_halbtc8723b1ant_rf_status_notify(btcoexist, type)
-#define ex_halbtc8723b1ant_halt_notify(btcoexist)
-#define ex_halbtc8723b1ant_pnp_notify(btcoexist, pnp_state)
-#define ex_halbtc8723b1ant_coex_dm_reset(btcoexist)
-#define ex_halbtc8723b1ant_periodical(btcoexist)
-#define ex_halbtc8723b1ant_display_coex_info(btcoexist)
-#define ex_halbtc8723b1ant_antenna_detection(btcoexist, cent_freq, offset, span, seconds)
-#define ex_halbtc8723b1ant_display_ant_detection(btcoexist)
-
-#endif
-
-#endif
diff --git a/hal/btc/HalBtc8723b2Ant.c b/hal/btc/HalBtc8723b2Ant.c
deleted file mode 100644
index 80c1de0..0000000
--- a/hal/btc/HalBtc8723b2Ant.c
+++ /dev/null
@@ -1,4920 +0,0 @@
-/* ************************************************************
- * Description:
- *
- * This file is for RTL8723B Co-exist mechanism
- *
- * History
- * 2012/11/15 Cosa first check in.
- *
- * ************************************************************ */
-
-/* ************************************************************
- * include files
- * ************************************************************ */
-#include "Mp_Precomp.h"
-
-#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
-
-#if (RTL8723B_SUPPORT == 1)
-/* ************************************************************
- * Global variables, these are static variables
- * ************************************************************ */
-static u8 *trace_buf = &gl_btc_trace_buf[0];
-static struct coex_dm_8723b_2ant glcoex_dm_8723b_2ant;
-static struct coex_dm_8723b_2ant *coex_dm = &glcoex_dm_8723b_2ant;
-static struct coex_sta_8723b_2ant glcoex_sta_8723b_2ant;
-static struct coex_sta_8723b_2ant *coex_sta = &glcoex_sta_8723b_2ant;
-
-const char *const glbt_info_src_8723b_2ant[] = {
- "BT Info[wifi fw]",
- "BT Info[bt rsp]",
- "BT Info[bt auto report]",
-};
-
-u32 glcoex_ver_date_8723b_2ant = 20151223;
-u32 glcoex_ver_8723b_2ant = 0x4a;
-
-/* ************************************************************
- * local function proto type if needed
- * ************************************************************
- * ************************************************************
- * local function start with halbtc8723b2ant_
- * ************************************************************ */
-u8 halbtc8723b2ant_bt_rssi_state(u8 *ppre_bt_rssi_state, u8 level_num,
- u8 rssi_thresh, u8 rssi_thresh1)
-{
- s32 bt_rssi = 0;
- u8 bt_rssi_state = *ppre_bt_rssi_state;
-
- bt_rssi = coex_sta->bt_rssi;
-
- if (level_num == 2) {
- if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
- (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
- if (bt_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT))
- bt_rssi_state = BTC_RSSI_STATE_HIGH;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else {
- if (bt_rssi < rssi_thresh)
- bt_rssi_state = BTC_RSSI_STATE_LOW;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- } else if (level_num == 3) {
- if (rssi_thresh > rssi_thresh1) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Rssi thresh error!!\n");
- BTC_TRACE(trace_buf);
- return *ppre_bt_rssi_state;
- }
-
- if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
- (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
- if (bt_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT))
- bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
- (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
- if (bt_rssi >= (rssi_thresh1 +
- BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT))
- bt_rssi_state = BTC_RSSI_STATE_HIGH;
- else if (bt_rssi < rssi_thresh)
- bt_rssi_state = BTC_RSSI_STATE_LOW;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
- } else {
- if (bt_rssi < rssi_thresh1)
- bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- }
-
- *ppre_bt_rssi_state = bt_rssi_state;
-
- return bt_rssi_state;
-}
-
-u8 halbtc8723b2ant_wifi_rssi_state(IN struct btc_coexist *btcoexist,
- IN u8 *pprewifi_rssi_state, IN u8 level_num, IN u8 rssi_thresh,
- IN u8 rssi_thresh1)
-{
- s32 wifi_rssi = 0;
- u8 wifi_rssi_state = *pprewifi_rssi_state;
-
- btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
-
- if (level_num == 2) {
- if ((*pprewifi_rssi_state == BTC_RSSI_STATE_LOW) ||
- (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
- if (wifi_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT))
- wifi_rssi_state = BTC_RSSI_STATE_HIGH;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else {
- if (wifi_rssi < rssi_thresh)
- wifi_rssi_state = BTC_RSSI_STATE_LOW;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- } else if (level_num == 3) {
- if (rssi_thresh > rssi_thresh1) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], wifi RSSI thresh error!!\n");
- BTC_TRACE(trace_buf);
- return *pprewifi_rssi_state;
- }
-
- if ((*pprewifi_rssi_state == BTC_RSSI_STATE_LOW) ||
- (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
- if (wifi_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT))
- wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else if ((*pprewifi_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
- (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
- if (wifi_rssi >= (rssi_thresh1 +
- BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT))
- wifi_rssi_state = BTC_RSSI_STATE_HIGH;
- else if (wifi_rssi < rssi_thresh)
- wifi_rssi_state = BTC_RSSI_STATE_LOW;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
- } else {
- if (wifi_rssi < rssi_thresh1)
- wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- }
-
- *pprewifi_rssi_state = wifi_rssi_state;
-
- return wifi_rssi_state;
-}
-
-void halbtc8723b2ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist)
-{
- static u32 bt_disable_cnt = 0;
- boolean bt_active = true, bt_disabled = false;
-
- /* This function check if bt is disabled */
-
- if (coex_sta->high_priority_tx == 0 &&
- coex_sta->high_priority_rx == 0 &&
- coex_sta->low_priority_tx == 0 &&
- coex_sta->low_priority_rx == 0)
- bt_active = false;
- if (coex_sta->high_priority_tx == 0xffff &&
- coex_sta->high_priority_rx == 0xffff &&
- coex_sta->low_priority_tx == 0xffff &&
- coex_sta->low_priority_rx == 0xffff)
- bt_active = false;
- if (bt_active) {
- bt_disable_cnt = 0;
- bt_disabled = false;
- } else {
- bt_disable_cnt++;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], bt all counters=0, %d times!!\n",
- bt_disable_cnt);
- BTC_TRACE(trace_buf);
- if (bt_disable_cnt >= 2)
- bt_disabled = true;
- }
- if (coex_sta->bt_disabled != bt_disabled) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is from %s to %s!!\n",
- (coex_sta->bt_disabled ? "disabled" : "enabled"),
- (bt_disabled ? "disabled" : "enabled"));
- BTC_TRACE(trace_buf);
-
- coex_sta->bt_disabled = bt_disabled;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
- &bt_disabled);
- if (bt_disabled) {
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS,
- NULL);
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS,
- NULL);
- }
- }
-}
-
-
-void halbtc8723b2ant_limited_rx(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean rej_ap_agg_pkt,
- IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size)
-{
- boolean reject_rx_agg = rej_ap_agg_pkt;
- boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size;
- u8 rx_agg_size = agg_buf_size;
-
- /* ============================================ */
- /* Rx Aggregation related setting */
- /* ============================================ */
- btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT,
- &reject_rx_agg);
- /* decide BT control aggregation buf size or not */
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE,
- &bt_ctrl_rx_agg_size);
- /* aggregation buf size, only work when BT control Rx aggregation size. */
- btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size);
- /* real update aggregation setting */
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
-}
-
-void halbtc8723b2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist)
-{
- u32 reg_hp_txrx, reg_lp_txrx, u32tmp;
- u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
-
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
- reg_hp_txrx = 0x770;
- reg_lp_txrx = 0x774;
-
- u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
- reg_hp_tx = u32tmp & MASKLWORD;
- reg_hp_rx = (u32tmp & MASKHWORD) >> 16;
-
- u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
- reg_lp_tx = u32tmp & MASKLWORD;
- reg_lp_rx = (u32tmp & MASKHWORD) >> 16;
-
- coex_sta->high_priority_tx = reg_hp_tx;
- coex_sta->high_priority_rx = reg_hp_rx;
- coex_sta->low_priority_tx = reg_lp_tx;
- coex_sta->low_priority_rx = reg_lp_rx;
-
- if ((coex_sta->low_priority_tx > 1050) &&
- (!coex_sta->c2h_bt_inquiry_page))
- coex_sta->pop_event_cnt++;
-
- if ((coex_sta->low_priority_rx >= 950) &&
- (coex_sta->low_priority_rx >= coex_sta->low_priority_tx) &&
- (!coex_sta->under_ips))
- bt_link_info->slave_role = true;
- else
- bt_link_info->slave_role = false;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], High Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n",
- reg_hp_txrx, reg_hp_tx, reg_hp_tx, reg_hp_rx, reg_hp_rx);
- BTC_TRACE(trace_buf);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Low Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n",
- reg_lp_txrx, reg_lp_tx, reg_lp_tx, reg_lp_rx, reg_lp_rx);
- BTC_TRACE(trace_buf);
-
- /* reset counter */
- btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
-}
-
-void halbtc8723b2ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist)
-{
-
-
- if (coex_sta->under_ips) {
- coex_sta->crc_ok_cck = 0;
- coex_sta->crc_ok_11g = 0;
- coex_sta->crc_ok_11n = 0;
- coex_sta->crc_ok_11n_agg = 0;
-
- coex_sta->crc_err_cck = 0;
- coex_sta->crc_err_11g = 0;
- coex_sta->crc_err_11n = 0;
- coex_sta->crc_err_11n_agg = 0;
- } else {
- coex_sta->crc_ok_cck = btcoexist->btc_read_4byte(btcoexist,
- 0xf88);
- coex_sta->crc_ok_11g = btcoexist->btc_read_2byte(btcoexist,
- 0xf94);
- coex_sta->crc_ok_11n = btcoexist->btc_read_2byte(btcoexist,
- 0xf90);
- coex_sta->crc_ok_11n_agg = btcoexist->btc_read_2byte(btcoexist,
- 0xfb8);
-
- coex_sta->crc_err_cck = btcoexist->btc_read_4byte(btcoexist,
- 0xf84);
- coex_sta->crc_err_11g = btcoexist->btc_read_2byte(btcoexist,
- 0xf96);
- coex_sta->crc_err_11n = btcoexist->btc_read_2byte(btcoexist,
- 0xf92);
- coex_sta->crc_err_11n_agg = btcoexist->btc_read_2byte(btcoexist,
- 0xfba);
- }
-
- /* reset counter */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xf16, 0x1, 0x1);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xf16, 0x1, 0x0);
-}
-
-void halbtc8723b2ant_query_bt_info(IN struct btc_coexist *btcoexist)
-{
- u8 h2c_parameter[1] = {0};
-
- coex_sta->c2h_bt_info_req_sent = true;
-
- h2c_parameter[0] |= BIT(0); /* trigger */
-
- btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter);
-}
-
-boolean halbtc8723b2ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist)
-{
- static boolean pre_wifi_busy = false, pre_under_4way = false,
- pre_bt_hs_on = false;
- static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
- boolean wifi_busy = false, under_4way = false, bt_hs_on = false;
- boolean wifi_connected = false;
- u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH;
-
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
- &under_4way);
-
- if (wifi_connected) {
- if (wifi_busy != pre_wifi_busy) {
- pre_wifi_busy = wifi_busy;
- return true;
- }
- if (under_4way != pre_under_4way) {
- pre_under_4way = under_4way;
- return true;
- }
- if (bt_hs_on != pre_bt_hs_on) {
- pre_bt_hs_on = bt_hs_on;
- return true;
- }
-
-
- wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state, 2,
- BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES -
- coex_dm->switch_thres_offset, 0);
-
- if ((BTC_RSSI_STATE_HIGH == wifi_rssi_state) ||
- (BTC_RSSI_STATE_LOW == wifi_rssi_state))
- return true;
-
- }
-
- return false;
-}
-
-void halbtc8723b2ant_update_bt_link_info(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean bt_hs_on = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
-
- bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
- bt_link_info->sco_exist = coex_sta->sco_exist;
- bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
- bt_link_info->pan_exist = coex_sta->pan_exist;
- bt_link_info->hid_exist = coex_sta->hid_exist;
-
- /* work around for HS mode. */
- if (bt_hs_on) {
- bt_link_info->pan_exist = true;
- bt_link_info->bt_link_exist = true;
- }
-
- /* check if Sco only */
- if (bt_link_info->sco_exist &&
- !bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist &&
- !bt_link_info->hid_exist)
- bt_link_info->sco_only = true;
- else
- bt_link_info->sco_only = false;
-
- /* check if A2dp only */
- if (!bt_link_info->sco_exist &&
- bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist &&
- !bt_link_info->hid_exist)
- bt_link_info->a2dp_only = true;
- else
- bt_link_info->a2dp_only = false;
-
- /* check if Pan only */
- if (!bt_link_info->sco_exist &&
- !bt_link_info->a2dp_exist &&
- bt_link_info->pan_exist &&
- !bt_link_info->hid_exist)
- bt_link_info->pan_only = true;
- else
- bt_link_info->pan_only = false;
-
- /* check if Hid only */
- if (!bt_link_info->sco_exist &&
- !bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist &&
- bt_link_info->hid_exist)
- bt_link_info->hid_only = true;
- else
- bt_link_info->hid_only = false;
-}
-
-u8 halbtc8723b2ant_action_algorithm(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean bt_hs_on = false;
- u8 algorithm = BT_8723B_2ANT_COEX_ALGO_UNDEFINED;
- u8 num_of_diff_profile = 0;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
-
- if (!bt_link_info->bt_link_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], No BT link exists!!!\n");
- BTC_TRACE(trace_buf);
- return algorithm;
- }
-
- if (bt_link_info->sco_exist)
- num_of_diff_profile++;
- if (bt_link_info->hid_exist)
- num_of_diff_profile++;
- if (bt_link_info->pan_exist)
- num_of_diff_profile++;
- if (bt_link_info->a2dp_exist)
- num_of_diff_profile++;
-
- if (num_of_diff_profile == 1) {
- if (bt_link_info->sco_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO only\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8723B_2ANT_COEX_ALGO_SCO;
- } else {
- if (bt_link_info->hid_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], HID only\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8723B_2ANT_COEX_ALGO_HID;
- } else if (bt_link_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], A2DP only\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8723B_2ANT_COEX_ALGO_A2DP;
- } else if (bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], PAN(HS) only\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723B_2ANT_COEX_ALGO_PANHS;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], PAN(EDR) only\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723B_2ANT_COEX_ALGO_PANEDR;
- }
- }
- }
- } else if (num_of_diff_profile == 2) {
- if (bt_link_info->sco_exist) {
- if (bt_link_info->hid_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + HID\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID;
- } else if (bt_link_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + A2DP ==> SCO\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID;
- } else if (bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8723B_2ANT_COEX_ALGO_SCO;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723B_2ANT_COEX_ALGO_PANEDR_HID;
- }
- }
- } else {
- if (bt_link_info->hid_exist &&
- bt_link_info->a2dp_exist) {
- {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], HID + A2DP\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723B_2ANT_COEX_ALGO_HID_A2DP;
- }
- } else if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], HID + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8723B_2ANT_COEX_ALGO_HID;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], HID + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723B_2ANT_COEX_ALGO_PANEDR_HID;
- }
- } else if (bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723B_2ANT_COEX_ALGO_A2DP_PANHS;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], A2DP + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723B_2ANT_COEX_ALGO_PANEDR_A2DP;
- }
- }
- }
- } else if (num_of_diff_profile == 3) {
- if (bt_link_info->sco_exist) {
- if (bt_link_info->hid_exist &&
- bt_link_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + HID + A2DP ==> HID\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID;
- } else if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + HID + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723B_2ANT_COEX_ALGO_PANEDR_HID;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + HID + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723B_2ANT_COEX_ALGO_PANEDR_HID;
- }
- } else if (bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723B_2ANT_COEX_ALGO_PANEDR_HID;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723B_2ANT_COEX_ALGO_PANEDR_HID;
- }
- }
- } else {
- if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], HID + A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723B_2ANT_COEX_ALGO_HID_A2DP;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], HID + A2DP + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723B_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
- }
- }
- }
- } else if (num_of_diff_profile >= 3) {
- if (bt_link_info->sco_exist) {
- if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
-
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723B_2ANT_COEX_ALGO_PANEDR_HID;
- }
- }
- }
- }
-
- return algorithm;
-}
-
-void halbtc8723b2ant_set_fw_dac_swing_level(IN struct btc_coexist *btcoexist,
- IN u8 dac_swing_lvl)
-{
- u8 h2c_parameter[1] = {0};
-
- /* There are several type of dacswing */
- /* 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */
- h2c_parameter[0] = dac_swing_lvl;
-
- btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter);
-}
-
-void halbtc8723b2ant_set_fw_dec_bt_pwr(IN struct btc_coexist *btcoexist,
- IN u8 dec_bt_pwr_lvl)
-{
- u8 h2c_parameter[1] = {0};
-
- h2c_parameter[0] = dec_bt_pwr_lvl;
-
- btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter);
-}
-
-void halbtc8723b2ant_dec_bt_pwr(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 dec_bt_pwr_lvl)
-{
- coex_dm->cur_bt_dec_pwr_lvl = dec_bt_pwr_lvl;
-
- if (!force_exec) {
- if (coex_dm->pre_bt_dec_pwr_lvl == coex_dm->cur_bt_dec_pwr_lvl)
- return;
- }
- halbtc8723b2ant_set_fw_dec_bt_pwr(btcoexist,
- coex_dm->cur_bt_dec_pwr_lvl);
-
- coex_dm->pre_bt_dec_pwr_lvl = coex_dm->cur_bt_dec_pwr_lvl;
-}
-
-void halbtc8723b2ant_set_bt_auto_report(IN struct btc_coexist *btcoexist,
- IN boolean enable_auto_report)
-{
- u8 h2c_parameter[1] = {0};
-
- h2c_parameter[0] = 0;
-
- if (enable_auto_report)
- h2c_parameter[0] |= BIT(0);
-
- btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter);
-}
-
-void halbtc8723b2ant_bt_auto_report(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean enable_auto_report)
-{
- coex_dm->cur_bt_auto_report = enable_auto_report;
-
- if (!force_exec) {
- if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report)
- return;
- }
- halbtc8723b2ant_set_bt_auto_report(btcoexist,
- coex_dm->cur_bt_auto_report);
-
- coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report;
-}
-
-void halbtc8723b2ant_fw_dac_swing_lvl(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 fw_dac_swing_lvl)
-{
- coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl;
-
- if (!force_exec) {
- if (coex_dm->pre_fw_dac_swing_lvl ==
- coex_dm->cur_fw_dac_swing_lvl)
- return;
- }
-
- halbtc8723b2ant_set_fw_dac_swing_level(btcoexist,
- coex_dm->cur_fw_dac_swing_lvl);
-
- coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl;
-}
-
-void halbtc8723b2ant_set_sw_rf_rx_lpf_corner(IN struct btc_coexist *btcoexist,
- IN boolean rx_rf_shrink_on)
-{
- if (rx_rf_shrink_on) {
- /* Shrink RF Rx LPF corner */
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Shrink RF Rx LPF corner!!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, 0xfffff,
- 0xffffc);
- } else {
- /* Resume RF Rx LPF corner */
- /* After initialized, we can use coex_dm->bt_rf_0x1e_backup */
- if (btcoexist->initilized) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Resume RF Rx LPF corner!!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e,
- 0xfffff, coex_dm->bt_rf_0x1e_backup);
- }
- }
-}
-
-void halbtc8723b2ant_rf_shrink(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean rx_rf_shrink_on)
-{
- coex_dm->cur_rf_rx_lpf_shrink = rx_rf_shrink_on;
-
- if (!force_exec) {
- if (coex_dm->pre_rf_rx_lpf_shrink ==
- coex_dm->cur_rf_rx_lpf_shrink)
- return;
- }
- halbtc8723b2ant_set_sw_rf_rx_lpf_corner(btcoexist,
- coex_dm->cur_rf_rx_lpf_shrink);
-
- coex_dm->pre_rf_rx_lpf_shrink = coex_dm->cur_rf_rx_lpf_shrink;
-}
-
-void halbtc8723b2ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist
- *btcoexist, IN boolean low_penalty_ra)
-{
- u8 h2c_parameter[6] = {0};
-
- h2c_parameter[0] = 0x6; /* op_code, 0x6= Retry_Penalty */
-
- if (low_penalty_ra) {
- h2c_parameter[1] |= BIT(0);
- h2c_parameter[2] =
- 0x00; /* normal rate except MCS7/6/5, OFDM54/48/36 */
- h2c_parameter[3] = 0xf4; /* MCS7 or OFDM54 */
- h2c_parameter[4] = 0xf5; /* MCS6 or OFDM48 */
- h2c_parameter[5] = 0xf6; /* MCS5 or OFDM36 */
- }
-
- btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter);
-}
-
-void halbtc8723b2ant_low_penalty_ra(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean low_penalty_ra)
-{
- coex_dm->cur_low_penalty_ra = low_penalty_ra;
-
- if (!force_exec) {
- if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra)
- return;
- }
- halbtc8723b2ant_set_sw_penalty_tx_rate_adaptive(btcoexist,
- coex_dm->cur_low_penalty_ra);
-
- coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra;
-}
-
-void halbtc8723b2ant_set_dac_swing_reg(IN struct btc_coexist *btcoexist,
- IN u32 level)
-{
- u8 val = (u8)level;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Write SwDacSwing = 0x%x\n", level);
- BTC_TRACE(trace_buf);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x883, 0x3e, val);
-}
-
-void halbtc8723b2ant_set_sw_full_time_dac_swing(IN struct btc_coexist
- *btcoexist, IN boolean sw_dac_swing_on, IN u32 sw_dac_swing_lvl)
-{
- if (sw_dac_swing_on)
- halbtc8723b2ant_set_dac_swing_reg(btcoexist, sw_dac_swing_lvl);
- else
- halbtc8723b2ant_set_dac_swing_reg(btcoexist, 0x18);
-}
-
-
-void halbtc8723b2ant_dac_swing(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean dac_swing_on, IN u32 dac_swing_lvl)
-{
- coex_dm->cur_dac_swing_on = dac_swing_on;
- coex_dm->cur_dac_swing_lvl = dac_swing_lvl;
-
- if (!force_exec) {
- if ((coex_dm->pre_dac_swing_on == coex_dm->cur_dac_swing_on) &&
- (coex_dm->pre_dac_swing_lvl ==
- coex_dm->cur_dac_swing_lvl))
- return;
- }
- delay_ms(30);
- halbtc8723b2ant_set_sw_full_time_dac_swing(btcoexist, dac_swing_on,
- dac_swing_lvl);
-
- coex_dm->pre_dac_swing_on = coex_dm->cur_dac_swing_on;
- coex_dm->pre_dac_swing_lvl = coex_dm->cur_dac_swing_lvl;
-}
-
-void halbtc8723b2ant_set_adc_back_off(IN struct btc_coexist *btcoexist,
- IN boolean adc_back_off)
-{
- if (adc_back_off) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BB BackOff Level On!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc05, 0x30, 0x3);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BB BackOff Level Off!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc05, 0x30, 0x1);
- }
-}
-
-void halbtc8723b2ant_adc_back_off(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean adc_back_off)
-{
- coex_dm->cur_adc_back_off = adc_back_off;
-
- if (!force_exec) {
- if (coex_dm->pre_adc_back_off == coex_dm->cur_adc_back_off)
- return;
- }
- halbtc8723b2ant_set_adc_back_off(btcoexist, coex_dm->cur_adc_back_off);
-
- coex_dm->pre_adc_back_off = coex_dm->cur_adc_back_off;
-}
-
-void halbtc8723b2ant_set_agc_table(IN struct btc_coexist *btcoexist,
- IN boolean agc_table_en)
-{
- u8 rssi_adjust_val = 0;
-
- /* =================BB AGC Gain Table */
- if (agc_table_en) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BB Agc Table On!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6e1A0001);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6d1B0001);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6c1C0001);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6b1D0001);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6a1E0001);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x691F0001);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x68200001);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BB Agc Table Off!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xaa1A0001);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa91B0001);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa81C0001);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa71D0001);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa61E0001);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa51F0001);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa4200001);
- }
-
-
- /* =================RF Gain */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xef, 0xfffff, 0x02000);
- if (agc_table_en) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Agc Table On!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff,
- 0x38fff);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff,
- 0x38ffe);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Agc Table Off!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff,
- 0x380c3);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff,
- 0x28ce6);
- }
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xef, 0xfffff, 0x0);
-
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xed, 0xfffff, 0x1);
- if (agc_table_en) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Agc Table On!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff,
- 0x38fff);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff,
- 0x38ffe);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Agc Table Off!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff,
- 0x380c3);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff,
- 0x28ce6);
- }
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xed, 0xfffff, 0x0);
-
- /* set rssi_adjust_val for wifi module. */
- if (agc_table_en)
- rssi_adjust_val = 8;
- btcoexist->btc_set(btcoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON,
- &rssi_adjust_val);
-}
-
-void halbtc8723b2ant_agc_table(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean agc_table_en)
-{
- coex_dm->cur_agc_table_en = agc_table_en;
-
- if (!force_exec) {
- if (coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en)
- return;
- }
- halbtc8723b2ant_set_agc_table(btcoexist, agc_table_en);
-
- coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en;
-}
-
-void halbtc8723b2ant_set_coex_table(IN struct btc_coexist *btcoexist,
- IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc)
-{
- btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
-
- btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
-
- btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
-
- btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
-}
-
-void halbtc8723b2ant_coex_table(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4,
- IN u32 val0x6c8, IN u8 val0x6cc)
-{
- coex_dm->cur_val0x6c0 = val0x6c0;
- coex_dm->cur_val0x6c4 = val0x6c4;
- coex_dm->cur_val0x6c8 = val0x6c8;
- coex_dm->cur_val0x6cc = val0x6cc;
-
- if (!force_exec) {
- if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) &&
- (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) &&
- (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) &&
- (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc))
- return;
- }
- halbtc8723b2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8,
- val0x6cc);
-
- coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0;
- coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4;
- coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8;
- coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc;
-}
-
-void halbtc8723b2ant_coex_table_with_type(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- coex_sta->coex_table_type = type;
-
- switch (type) {
- case 0:
- halbtc8723b2ant_coex_table(btcoexist, force_exec,
- 0x55555555, 0x55555555, 0xffffff, 0x3);
- break;
- case 1:
- halbtc8723b2ant_coex_table(btcoexist, force_exec,
- 0x55555555, 0x5afa5afa, 0xffffff, 0x3);
- break;
- case 2:
- halbtc8723b2ant_coex_table(btcoexist, force_exec,
- 0x5ada5ada, 0x5ada5ada, 0xffffff, 0x3);
- break;
- case 3:
- halbtc8723b2ant_coex_table(btcoexist, force_exec,
- 0xaaaaaaaa, 0xaaaaaaaa, 0xffffff, 0x3);
- break;
- case 4:
- halbtc8723b2ant_coex_table(btcoexist, force_exec,
- 0xffffffff, 0xffffffff, 0xffffff, 0x3);
- break;
- case 5:
- halbtc8723b2ant_coex_table(btcoexist, force_exec,
- 0x5fff5fff, 0x5fff5fff, 0xffffff, 0x3);
- break;
- case 6:
- halbtc8723b2ant_coex_table(btcoexist, force_exec,
- 0x55ff55ff, 0x5a5a5a5a, 0xffffff, 0x3);
- break;
- case 7:
- halbtc8723b2ant_coex_table(btcoexist, force_exec,
- 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3);
- break;
- case 8:
- halbtc8723b2ant_coex_table(btcoexist, force_exec,
- 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3);
- break;
- case 9:
- halbtc8723b2ant_coex_table(btcoexist, force_exec,
- 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3);
- break;
- case 10:
- halbtc8723b2ant_coex_table(btcoexist, force_exec,
- 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3);
- break;
- case 11:
- halbtc8723b2ant_coex_table(btcoexist, force_exec,
- 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3);
- break;
- case 12:
- halbtc8723b2ant_coex_table(btcoexist, force_exec,
- 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3);
- break;
- case 13:
- halbtc8723b2ant_coex_table(btcoexist, force_exec,
- 0x5fff5fff, 0xaaaaaaaa, 0xffffff, 0x3);
- break;
- case 14:
- halbtc8723b2ant_coex_table(btcoexist, force_exec,
- 0x5fff5fff, 0x5ada5ada, 0xffffff, 0x3);
- break;
- case 15:
- halbtc8723b2ant_coex_table(btcoexist, force_exec,
- 0x55dd55dd, 0xaaaaaaaa, 0xffffff, 0x3);
- break;
- default:
- break;
- }
-}
-
-void halbtc8723b2ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist,
- IN boolean enable)
-{
- u8 h2c_parameter[1] = {0};
-
- if (enable) {
- h2c_parameter[0] |= BIT(0); /* function enable */
- }
-
- btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter);
-}
-
-void halbtc8723b2ant_set_lps_rpwm(IN struct btc_coexist *btcoexist,
- IN u8 lps_val, IN u8 rpwm_val)
-{
- u8 lps = lps_val;
- u8 rpwm = rpwm_val;
-
- btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps);
- btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm);
-}
-
-void halbtc8723b2ant_lps_rpwm(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val)
-{
- coex_dm->cur_lps = lps_val;
- coex_dm->cur_rpwm = rpwm_val;
-
- if (!force_exec) {
- if ((coex_dm->pre_lps == coex_dm->cur_lps) &&
- (coex_dm->pre_rpwm == coex_dm->cur_rpwm))
- return;
- }
- halbtc8723b2ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val);
-
- coex_dm->pre_lps = coex_dm->cur_lps;
- coex_dm->pre_rpwm = coex_dm->cur_rpwm;
-}
-
-void halbtc8723b2ant_ignore_wlan_act(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean enable)
-{
- coex_dm->cur_ignore_wlan_act = enable;
-
- if (!force_exec) {
- if (coex_dm->pre_ignore_wlan_act ==
- coex_dm->cur_ignore_wlan_act)
- return;
- }
- halbtc8723b2ant_set_fw_ignore_wlan_act(btcoexist, enable);
-
- coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
-}
-
-void halbtc8723b2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist,
- IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5)
-{
- u8 h2c_parameter[5] = {0};
-
-
- if ((coex_sta->a2dp_exist) && (coex_sta->hid_exist))
- byte5 = byte5 | 0x1;
-
- h2c_parameter[0] = byte1;
- h2c_parameter[1] = byte2;
- h2c_parameter[2] = byte3;
- h2c_parameter[3] = byte4;
- h2c_parameter[4] = byte5;
-
- coex_dm->ps_tdma_para[0] = byte1;
- coex_dm->ps_tdma_para[1] = byte2;
- coex_dm->ps_tdma_para[2] = byte3;
- coex_dm->ps_tdma_para[3] = byte4;
- coex_dm->ps_tdma_para[4] = byte5;
-
- btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
-}
-
-void halbtc8723b2ant_sw_mechanism1(IN struct btc_coexist *btcoexist,
- IN boolean shrink_rx_lpf, IN boolean low_penalty_ra,
- IN boolean limited_dig, IN boolean bt_lna_constrain)
-{
- /*
- u32 wifi_bw;
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- if(BTC_WIFI_BW_HT40 != wifi_bw)
- {
- if (shrink_rx_lpf)
- shrink_rx_lpf = false;
- }
- */
-
- /* halbtc8723b2ant_rf_shrink(btcoexist, NORMAL_EXEC, shrink_rx_lpf); */
- halbtc8723b2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra);
-}
-
-void halbtc8723b2ant_sw_mechanism2(IN struct btc_coexist *btcoexist,
- IN boolean agc_table_shift, IN boolean adc_back_off,
- IN boolean sw_dac_swing, IN u32 dac_swing_lvl)
-{
- /* halbtc8723b2ant_agc_table(btcoexist, NORMAL_EXEC, agc_table_shift); */
- /* halbtc8723b2ant_adc_back_off(btcoexist, NORMAL_EXEC, adc_back_off); */
- /* halbtc8723b2ant_dac_swing(btcoexist, NORMAL_EXEC, sw_dac_swing, dac_swing_lvl); */
-}
-
-void halbtc8723b2ant_set_ant_path(IN struct btc_coexist *btcoexist,
- IN u8 ant_pos_type, IN boolean init_hwcfg, IN boolean wifi_off)
-{
- struct btc_board_info *board_info = &btcoexist->board_info;
- PADAPTER pAdapter = btcoexist->Adapter;
- u32 fw_ver = 0, u32tmp = 0, cnt_bt_cal_chk = 0;
- boolean pg_ext_switch = false;
- boolean use_ext_switch = false;
- u8 h2c_parameter[2] = {0};
- u32 u32tmp_1[4];
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_EXT_SWITCH, &pg_ext_switch);
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER,
- &fw_ver); /* [31:16]=fw ver, [15:0]=fw sub ver */
-
- if ((fw_ver > 0 && fw_ver < 0xc0000) || pg_ext_switch)
- use_ext_switch = true;
-
- if (init_hwcfg) {
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x39, 0x8, 0x1);
- btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x944, 0x3, 0x3);
- btcoexist->btc_write_1byte(btcoexist, 0x930, 0x77);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, 0x1);
-
- if (fw_ver >= 0x180000) {
- /* Use H2C to set GNT_BT to High to avoid A2DP click */
- h2c_parameter[0] = 1;
- btcoexist->btc_fill_h2c(btcoexist, 0x6E, 1,
- h2c_parameter);
-
- cnt_bt_cal_chk = 0;
- while(1)
- {
- if( pAdapter->bFWReady == FALSE )
- {
- //RT_TRACE(COMP_INIT , DBG_LOUD, ("halbtc8723b2ant_SetAntPath(): we don't need to wait for H2C command completion because of Fw download fail!!!\n"));
- break;
- }
-
- if( btcoexist->btc_read_1byte(btcoexist, 0x765) == 0x18 )
- break;
-
- cnt_bt_cal_chk++;
- if( cnt_bt_cal_chk > 20 )
- break;
- }
- } else
- btcoexist->btc_write_1byte(btcoexist, 0x765, 0x18);
- u32tmp_1[0] = btcoexist->btc_read_4byte(btcoexist, 0x948);
- if( (u32tmp_1[0] == 0x40) || (u32tmp_1[0] == 0x240))
- btcoexist->btc_write_4byte(btcoexist, 0x948, u32tmp_1[0]);
- else
- btcoexist->btc_write_4byte(btcoexist, 0x948, 0x0);
-
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff,
- 0x0); /* WiFi TRx Mask off */
- /* remove due to interrupt is disabled that polling c2h will fail and delay 100ms. */
- /* btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x3c, 0x01); //BT TRx Mask off */
-
- if (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT) {
- /* tell firmware "no antenna inverse" */
- h2c_parameter[0] = 0;
- } else {
- /* tell firmware "antenna inverse" */
- h2c_parameter[0] = 1;
- }
-
- if (use_ext_switch) {
- /* ext switch type */
- h2c_parameter[1] = 1;
- } else {
- /* int switch type */
- h2c_parameter[1] = 0;
- }
- btcoexist->btc_fill_h2c(btcoexist, 0x65, 2, h2c_parameter);
- } else {
- if (fw_ver >= 0x180000) {
- /* Use H2C to set GNT_BT to "Control by PTA"*/
- h2c_parameter[0] = 0;
- btcoexist->btc_fill_h2c(btcoexist, 0x6E, 1,
- h2c_parameter);
-
- cnt_bt_cal_chk = 0;
- while(1)
- {
- if( pAdapter->bFWReady == FALSE )
- {
- //RT_TRACE(COMP_INIT , DBG_LOUD, ("halbtc8723b2ant_SetAntPath(): we don't need to wait for H2C command completion because of Fw download fail!!!\n"));
- break;
- }
-
- if( btcoexist->btc_read_1byte(btcoexist, 0x765) == 0x0 )
- break;
-
- cnt_bt_cal_chk++;
- if( cnt_bt_cal_chk > 20 )
- break;
- }
- } else
- btcoexist->btc_write_1byte(btcoexist, 0x765, 0x0);
- }
-
- /* ext switch setting */
- if (use_ext_switch) {
- if (init_hwcfg) {
- /* 0x4c[23]=0, 0x4c[24]=1 Antenna control by WL/BT */
- u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c);
- u32tmp &= ~BIT(23);
- u32tmp |= BIT(24);
- btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp);
- }
- u32tmp_1[0] = btcoexist->btc_read_4byte(btcoexist, 0x948);
- if( (u32tmp_1[0] == 0x40) || (u32tmp_1[0] == 0x240))
- btcoexist->btc_write_4byte(btcoexist, 0x948, u32tmp_1[0]);
- else
- btcoexist->btc_write_4byte(btcoexist, 0x948, 0x0);
-
- switch (ant_pos_type) {
- case BTC_ANT_WIFI_AT_MAIN:
- btcoexist->btc_write_1byte_bitmask(btcoexist,
- 0x92c, 0x3,
- 0x1); /* ext switch main at wifi */
- break;
- case BTC_ANT_WIFI_AT_AUX:
- btcoexist->btc_write_1byte_bitmask(btcoexist,
- 0x92c, 0x3,
- 0x2); /* ext switch aux at wifi */
- break;
- }
- } else { /* internal switch */
- if (init_hwcfg) {
- /* 0x4c[23]=0, 0x4c[24]=1 Antenna control by WL/BT */
- u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c);
- u32tmp |= BIT(23);
- u32tmp &= ~BIT(24);
- btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp);
- }
-
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x64, 0x1,
- 0x0); /* fixed external switch S1->Main, S0->Aux */
- switch (ant_pos_type) {
- case BTC_ANT_WIFI_AT_MAIN:
- u32tmp_1[0] = btcoexist->btc_read_4byte(btcoexist, 0x948);
- if( (u32tmp_1[0] == 0x40) || (u32tmp_1[0] == 0x240))
- btcoexist->btc_write_4byte(btcoexist, 0x948, u32tmp_1[0]);
- else
- btcoexist->btc_write_4byte(btcoexist, 0x948, 0x0);
- break;
- case BTC_ANT_WIFI_AT_AUX:
- u32tmp_1[0] = btcoexist->btc_read_4byte(btcoexist, 0x948);
- if( (u32tmp_1[0] == 0x40) || (u32tmp_1[0] == 0x240))
- btcoexist->btc_write_4byte(btcoexist, 0x948, u32tmp_1[0]);
- else
- btcoexist->btc_write_4byte(btcoexist, 0x948, 0x280);
- break;
- }
- }
-}
-#if 0
-boolean halbtc8723b2ant_CoexSwitchThresCheck(IN struct btc_coexist *btcoexist)
-{
- static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state1, bt_rssi_state;
- u32 vendor;
- u8 offset = 0;
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_VENDOR, &vendor);
-
- /* if (vendor == BTC_VENDOR_LENOVO) */
- /* offset = 20; */
-
- wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state, 2, BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES
- - coex_dm->switch_thres_offset, 0);
- bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
- BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES -
- coex_dm->switch_thres_offset, 0);
-
- if (BTC_RSSI_LOW(wifi_rssi_state1) || BTC_RSSI_LOW(bt_rssi_state))
- return true;
-
- return false;
-}
-#endif
-
-void halbtc8723b2ant_ps_tdma(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean turn_on, IN u8 type)
-{
- static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state1, bt_rssi_state;
- s8 wifi_duration_adjust = 0x0;
- u8 psTdmaByte4Modify = 0x0;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
- wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state, 2, BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES
- - coex_dm->switch_thres_offset, 0);
- bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
- BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES -
- coex_dm->switch_thres_offset, 0);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], %s turn %s PS TDMA, type=%d\n",
- (force_exec ? "force to" : ""), (turn_on ? "ON" : "OFF"), type);
- BTC_TRACE(trace_buf);
- coex_dm->cur_ps_tdma_on = turn_on;
- coex_dm->cur_ps_tdma = type;
-
- if (!(BTC_RSSI_HIGH(wifi_rssi_state1) &&
- BTC_RSSI_HIGH(bt_rssi_state)) && turn_on)
- /* if (halbtc8723b2ant_CoexSwitchThresCheck(btcoexist) && turn_on) */
- {
- type = type + 100; /* for WiFi RSSI low or BT RSSI low */
- coex_dm->is_switch_to_1dot5_ant = true;
- } else
- coex_dm->is_switch_to_1dot5_ant = false;
-
-
- if (!force_exec) {
- if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) &&
- (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma))
- return;
- }
-
- if (coex_sta->scan_ap_num <= 5) {
- if (coex_sta->a2dp_bit_pool >= 45)
- wifi_duration_adjust = -15;
- else if (coex_sta->a2dp_bit_pool >= 35)
- wifi_duration_adjust = -10;
- else
- wifi_duration_adjust = 5;
- } else if (coex_sta->scan_ap_num <= 20) {
- if (coex_sta->a2dp_bit_pool >= 45)
- wifi_duration_adjust = -15;
- else if (coex_sta->a2dp_bit_pool >= 35)
- wifi_duration_adjust = -10;
- else
- wifi_duration_adjust = 0;
- } else if (coex_sta->scan_ap_num <= 40) {
- if (coex_sta->a2dp_bit_pool >= 45)
- wifi_duration_adjust = -15;
- else if (coex_sta->a2dp_bit_pool >= 35)
- wifi_duration_adjust = -10;
- else
- wifi_duration_adjust = -5;
- } else {
- if (coex_sta->a2dp_bit_pool >= 45)
- wifi_duration_adjust = -15;
- else if (coex_sta->a2dp_bit_pool >= 35)
- wifi_duration_adjust = -10;
- else
- wifi_duration_adjust = -10;
- }
-
- if ((bt_link_info->slave_role == true) && (bt_link_info->a2dp_exist))
- psTdmaByte4Modify =
- 0x1; /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */
-
-
- if (turn_on) {
- switch (type) {
- case 1:
- default:
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x3c + wifi_duration_adjust, 0x03, 0xf1,
- 0x90 | psTdmaByte4Modify);
- break;
- case 2:
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x2d + wifi_duration_adjust, 0x03, 0xf1,
- 0x90 | psTdmaByte4Modify);
- break;
- case 3:
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x1c, 0x3, 0xf1, 0x90 |
- psTdmaByte4Modify);
- break;
- case 4:
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x10, 0x03, 0xf1, 0x90 |
- psTdmaByte4Modify);
- break;
- case 5:
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x3c + wifi_duration_adjust, 0x3, 0x70,
- 0x90 | psTdmaByte4Modify);
- break;
- case 6:
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x2d + wifi_duration_adjust, 0x3, 0x70,
- 0x90 | psTdmaByte4Modify);
- break;
- case 7:
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x1c, 0x3, 0x70, 0x90 |
- psTdmaByte4Modify);
- break;
- case 8:
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xa3,
- 0x10, 0x3, 0x70, 0x90 |
- psTdmaByte4Modify);
- break;
- case 9:
- /*
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x3c + wifi_duration_adjust, 0x03, 0xf1,
- 0x90 | psTdmaByte4Modify);
- */
- /* Bryant Modify for BT no-profile busy case */
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x3c + wifi_duration_adjust, 0x03, 0xf1,
- 0x91);
-
- break;
- case 10:
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x2d + wifi_duration_adjust, 0x03, 0xf1,
- 0x90 | psTdmaByte4Modify);
- break;
- case 11:
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x1c, 0x3, 0xf1, 0x90 |
- psTdmaByte4Modify);
- break;
- case 12:
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x10, 0x3, 0xf1, 0x90 |
- psTdmaByte4Modify);
- break;
- case 13:
- /*
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x3c + wifi_duration_adjust, 0x3, 0x70,
- 0x90 | psTdmaByte4Modify);
- */
- /* Bryant Modify for BT no-profile busy case */
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x3c + wifi_duration_adjust, 0x3, 0x70,
- 0x91);
- break;
- case 14:
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x2d + wifi_duration_adjust, 0x3, 0x70,
- 0x90 | psTdmaByte4Modify);
- break;
- case 15:
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x1c, 0x3, 0x70, 0x90 |
- psTdmaByte4Modify);
- break;
- case 16:
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x10, 0x3, 0x70, 0x90 |
- psTdmaByte4Modify);
- break;
- case 17:
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xa3,
- 0x2f, 0x2f, 0x60, 0x90);
- break;
- case 18:
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x5, 0x5, 0xe1, 0x90);
- break;
- case 19:
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x25, 0x25, 0xe1, 0x90);
- break;
- case 20:
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x25, 0x25, 0x60, 0x90);
- break;
- case 21:
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x15, 0x03, 0x70, 0x90);
- break;
- case 22:
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x35, 0x03, 0xf1, 0x90);
- break;
- case 23:
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x35, 0x03, 0x71, 0x10);
- break;
-
- case 33:
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x1c, 0x3, 0xf1, 0x91);
-
- break;
- case 71:
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x3c + wifi_duration_adjust, 0x03, 0xf1,
- 0x90);
- break;
- case 101:
- case 105:
- case 113:
- case 171:
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xd3,
- 0x3a + wifi_duration_adjust, 0x03, 0x70,
- 0x50 | psTdmaByte4Modify);
- break;
- case 102:
- case 106:
- case 110:
- case 114:
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xd3,
- 0x2d + wifi_duration_adjust, 0x03, 0x70,
- 0x50 | psTdmaByte4Modify);
- break;
- case 103:
- case 107:
- case 111:
- case 115:
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xd3,
- 0x1c, 0x03, 0x70, 0x50 |
- psTdmaByte4Modify);
- break;
- case 104:
- case 108:
- case 112:
- case 116:
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xd3,
- 0x10, 0x03, 0x70, 0x50 |
- psTdmaByte4Modify);
- break;
- case 109:
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x3c, 0x03, 0xf1, 0x90 |
- psTdmaByte4Modify);
- break;
- /* case 113:
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x3c, 0x03, 0x70, 0x90 |
- psTdmaByte4Modify);
- break; */
- case 121:
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x15, 0x03, 0x70, 0x90 |
- psTdmaByte4Modify);
- break;
- case 122:
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x35, 0x03, 0x71, 0x11);
- break;
- case 123:
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x35, 0x03, 0x71, 0x10);
- break;
- case 133:
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0xd3,
- 0x1c, 0x3, 0x70, 0x51);
-
- break;
- }
- } else {
- /* disable PS tdma */
- switch (type) {
- case 0:
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0x0,
- 0x0, 0x0, 0x40, 0x0);
- break;
- case 1:
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0x0,
- 0x0, 0x0, 0x48, 0x0);
- break;
- default:
- halbtc8723b2ant_set_fw_pstdma(btcoexist, 0x0,
- 0x0, 0x0, 0x40, 0x0);
- break;
- }
- }
-
- /* update pre state */
- coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on;
- coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
-}
-
-void halbtc8723b2ant_ps_tdma_check_for_power_save_state(
- IN struct btc_coexist *btcoexist, IN boolean new_ps_state)
-{
- u8 lps_mode = 0x0;
-
- btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode);
-
- if (lps_mode) { /* already under LPS state */
- if (new_ps_state) {
- /* keep state under LPS, do nothing. */
- } else {
- /* will leave LPS state, turn off psTdma first */
- halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 1);
- }
- } else { /* NO PS state */
- if (new_ps_state) {
- /* will enter LPS state, turn off psTdma first */
- halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 1);
- } else {
- /* keep state under NO PS state, do nothing. */
- }
- }
-}
-
-void halbtc8723b2ant_power_save_state(IN struct btc_coexist *btcoexist,
- IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val)
-{
- boolean low_pwr_disable = false;
-
- switch (ps_type) {
- case BTC_PS_WIFI_NATIVE:
- /* recover to original 32k low power setting */
- low_pwr_disable = false;
- btcoexist->btc_set(btcoexist,
- BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS,
- NULL);
- coex_sta->force_lps_on = false;
- break;
- case BTC_PS_LPS_ON:
- halbtc8723b2ant_ps_tdma_check_for_power_save_state(
- btcoexist, true);
- halbtc8723b2ant_lps_rpwm(btcoexist, NORMAL_EXEC,
- lps_val, rpwm_val);
- /* when coex force to enter LPS, do not enter 32k low power. */
- low_pwr_disable = true;
- btcoexist->btc_set(btcoexist,
- BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
- /* power save must executed before psTdma. */
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS,
- NULL);
- coex_sta->force_lps_on = true;
- break;
- case BTC_PS_LPS_OFF:
- halbtc8723b2ant_ps_tdma_check_for_power_save_state(
- btcoexist, false);
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS,
- NULL);
- coex_sta->force_lps_on = false;
- break;
- default:
- break;
- }
-}
-
-
-void halbtc8723b2ant_coex_all_off(IN struct btc_coexist *btcoexist)
-{
- /* fw all off */
- halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
- halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
- halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
- halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- /* sw all off */
- halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
-
- /* hw all off */
- /* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); */
- halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-}
-
-void halbtc8723b2ant_init_coex_dm(IN struct btc_coexist *btcoexist)
-{
- /* force to reset coex mechanism */
- halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
- halbtc8723b2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 1);
- halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 6);
- halbtc8723b2ant_dec_bt_pwr(btcoexist, FORCE_EXEC, 0);
-
- halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
-
- coex_sta->pop_event_cnt = 0;
-
-}
-
-void halbtc8723b2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist)
-{
- static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW,
- prewifi_rssi_state1 = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state;
- boolean wifi_connected = false;
- boolean low_pwr_disable = true;
- boolean scan = false, link = false, roam = false;
- boolean wifi_busy = false;
-
-
- wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state, 2, 15, 0);
- wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state1, 2,
- BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES -
- coex_dm->switch_thres_offset, 0);
- bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
- BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES -
- coex_dm->switch_thres_offset, 0);
-
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
-
- if (coex_sta->bt_abnormal_scan) {
- halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 23);
- halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
- } else if (scan || link || roam) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi link process + BT Inq/Page!!\n");
- BTC_TRACE(trace_buf);
- halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 7);
- halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3);
- } else if (wifi_connected) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi connected + BT Inq/Page!!\n");
- BTC_TRACE(trace_buf);
- halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 7);
-
- if (wifi_busy)
- halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3);
- else
- halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi no-link + BT Inq/Page!!\n");
- BTC_TRACE(trace_buf);
- halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
- halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
- }
-
- halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 6);
- halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
- /*
- coex_dm->need_recover0x948 = true;
- coex_dm->backup0x948 = btcoexist->btc_read_4byte(btcoexist, 0x948);
-
- halbtc8723b2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_AUX, false, false);
- */
-}
-
-
-void halbtc8723b2ant_action_wifi_link_process(IN struct btc_coexist *btcoexist)
-{
- u32 u32tmp;
- u8 u8tmpa, u8tmpb;
-
- halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 15);
- halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22);
-
- halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
-
-
- u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x948);
- u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765);
- u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x76e);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x76e=0x%x\n",
- u32tmp, u8tmpa, u8tmpb);
- BTC_TRACE(trace_buf);
-}
-
-boolean halbtc8723b2ant_action_wifi_idle_process(IN struct btc_coexist
- *btcoexist)
-{
- static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW,
- prewifi_rssi_state1 = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state;
- u8 ap_num = 0;
-
- wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state, 2, 15, 0);
- /* wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist, 1, 2, BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES-coex_dm->switch_thres_offset-coex_dm->switch_thres_offset, 0); */
- wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state1, 2,
- BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES -
- coex_dm->switch_thres_offset - coex_dm->switch_thres_offset, 0);
- bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
- BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES -
- coex_dm->switch_thres_offset - coex_dm->switch_thres_offset, 0);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, &ap_num);
-
- /* define the office environment */
- if (BTC_RSSI_HIGH(wifi_rssi_state1) &&
- (coex_sta->hid_exist == true) &&
- (coex_sta->a2dp_exist == true)) {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi idle process for BT HID+A2DP exist!!\n");
- BTC_TRACE(trace_buf);
-
- halbtc8723b2ant_dac_swing(btcoexist, NORMAL_EXEC, true, 0x6);
- halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- /* sw all off */
- halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false,
- false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false,
- 0x18);
-
- halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
-
- return true;
- } else {
- halbtc8723b2ant_dac_swing(btcoexist, NORMAL_EXEC, true, 0x18);
- return false;
- }
-
-
-}
-
-
-
-boolean halbtc8723b2ant_is_common_action(IN struct btc_coexist *btcoexist)
-{
- boolean common = false, wifi_connected = false, wifi_busy = false;
- boolean bt_hs_on = false, low_pwr_disable = false;
- boolean asus_8723b = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- if (!wifi_connected) {
- low_pwr_disable = false;
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
- halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
- 0x8);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi non-connected idle!!\n");
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff,
- 0x0);
- halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
- halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
- halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false,
- false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false,
- 0x18);
-
- common = true;
- } else {
- if (BT_8723B_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
- coex_dm->bt_status) {
- low_pwr_disable = false;
- btcoexist->btc_set(btcoexist,
- BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
- halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC,
- false, false, 0x8);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi connected + BT non connected-idle!!\n");
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1,
- 0xfffff, 0x0);
- halbtc8723b2ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 0);
-
- halbtc8723b2ant_power_save_state(btcoexist,
- BTC_PS_WIFI_NATIVE, 0x0, 0x0);
- halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 1);
- halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC,
- 0xb);
- halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false,
- false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
-
- common = true;
- } else if (BT_8723B_2ANT_BT_STATUS_CONNECTED_IDLE ==
- coex_dm->bt_status) {
- low_pwr_disable = true;
- btcoexist->btc_set(btcoexist,
- BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
-
- if (bt_hs_on)
- return false;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi connected + BT connected-idle!!\n");
- BTC_TRACE(trace_buf);
- halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC,
- false, false, 0x8);
-
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1,
- 0xfffff, 0x0);
- halbtc8723b2ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 0);
-
- halbtc8723b2ant_power_save_state(btcoexist,
- BTC_PS_WIFI_NATIVE, 0x0, 0x0);
- halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 1);
- halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC,
- 0xb);
- halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8723b2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
-
- common = true;
- } else {
- low_pwr_disable = true;
- btcoexist->btc_set(btcoexist,
- BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
-
- if (wifi_busy) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi Connected-Busy + BT Busy!!\n");
- BTC_TRACE(trace_buf);
- /* btcoexist->btc_get(btcoexist,
- BTC_GET_BL_IS_ASUS_8723B, &asus_8723b);
- if (!asus_8723b)
- common = false;
- else
- common = halbtc8723b2ant_action_wifi_idle_process(
- btcoexist); */
- common = false;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi Connected-Idle + BT Busy!!\n");
- BTC_TRACE(trace_buf);
- /* common = false; */
- common = halbtc8723b2ant_action_wifi_idle_process(
- btcoexist);
- }
- }
- }
-
- return common;
-}
-void halbtc8723b2ant_tdma_duration_adjust(IN struct btc_coexist *btcoexist,
- IN boolean sco_hid, IN boolean tx_pause, IN u8 max_interval)
-{
- static s32 up, dn, m, n, wait_count;
- s32 result; /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */
- u8 retry_count = 0;
-
- if (!coex_dm->auto_tdma_adjust) {
- coex_dm->auto_tdma_adjust = true;
- {
- if (sco_hid) {
- if (tx_pause) {
- if (max_interval == 1) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 13);
- coex_dm->ps_tdma_du_adj_type =
- 13;
- } else if (max_interval == 2) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 14);
- coex_dm->ps_tdma_du_adj_type =
- 14;
- } else if (max_interval == 3) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- }
- } else {
- if (max_interval == 1) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 9);
- coex_dm->ps_tdma_du_adj_type =
- 9;
- } else if (max_interval == 2) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 10);
- coex_dm->ps_tdma_du_adj_type =
- 10;
- } else if (max_interval == 3) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- }
- }
- } else {
- if (tx_pause) {
- if (max_interval == 1) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 5);
- coex_dm->ps_tdma_du_adj_type =
- 5;
- } else if (max_interval == 2) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 6);
- coex_dm->ps_tdma_du_adj_type =
- 6;
- } else if (max_interval == 3) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- }
- } else {
- if (max_interval == 1) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 1);
- coex_dm->ps_tdma_du_adj_type =
- 1;
- } else if (max_interval == 2) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 2);
- coex_dm->ps_tdma_du_adj_type =
- 2;
- } else if (max_interval == 3) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- }
- }
- }
- }
- /* ============ */
- up = 0;
- dn = 0;
- m = 1;
- n = 3;
- result = 0;
- wait_count = 0;
- } else {
- /* accquire the BT TRx retry count from BT_Info byte2 */
- retry_count = coex_sta->bt_retry_cnt;
-
- if ((coex_sta->low_priority_tx) > 1050 ||
- (coex_sta->low_priority_rx) > 1250)
- retry_count++;
-
- result = 0;
- wait_count++;
-
- if (retry_count ==
- 0) { /* no retry in the last 2-second duration */
- up++;
- dn--;
-
- if (dn <= 0)
- dn = 0;
-
- if (up >= n) { /* if retry count during continuous n*2 seconds is 0, enlarge WiFi duration */
- wait_count = 0;
- n = 3;
- up = 0;
- dn = 0;
- result = 1;
- }
- } else if (retry_count <=
- 3) { /* <=3 retry in the last 2-second duration */
- up--;
- dn++;
-
- if (up <= 0)
- up = 0;
-
- if (dn == 2) {/* if continuous 2 retry count(every 2 seconds) >0 and < 3, reduce WiFi duration */
- if (wait_count <= 2)
- m++; /* to avoid loop between the two levels */
- else
- m = 1;
-
- if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */
- m = 20;
-
- n = 3 * m;
- up = 0;
- dn = 0;
- wait_count = 0;
- result = -1;
- }
- } else { /* retry count > 3, once retry count > 3, to reduce WiFi duration */
- if (wait_count == 1)
- m++; /* to avoid loop between the two levels */
- else
- m = 1;
-
- if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */
- m = 20;
-
- n = 3 * m;
- up = 0;
- dn = 0;
- wait_count = 0;
- result = -1;
- }
-
- if (max_interval == 1) {
- if (tx_pause) {
- if (coex_dm->cur_ps_tdma == 71) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 5);
- coex_dm->ps_tdma_du_adj_type = 5;
- } else if (coex_dm->cur_ps_tdma == 1) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 5);
- coex_dm->ps_tdma_du_adj_type = 5;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 6);
- coex_dm->ps_tdma_du_adj_type = 6;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 7);
- coex_dm->ps_tdma_du_adj_type = 7;
- } else if (coex_dm->cur_ps_tdma == 4) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 8);
- coex_dm->ps_tdma_du_adj_type = 8;
- }
- if (coex_dm->cur_ps_tdma == 9) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 13);
- coex_dm->ps_tdma_du_adj_type = 13;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 14);
- coex_dm->ps_tdma_du_adj_type = 14;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 15);
- coex_dm->ps_tdma_du_adj_type = 15;
- } else if (coex_dm->cur_ps_tdma == 12) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 16);
- coex_dm->ps_tdma_du_adj_type = 16;
- }
-
- if (result == -1) {
- if (coex_dm->cur_ps_tdma == 5) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 6);
- coex_dm->ps_tdma_du_adj_type =
- 6;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 8);
- coex_dm->ps_tdma_du_adj_type =
- 8;
- } else if (coex_dm->cur_ps_tdma == 13) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 14);
- coex_dm->ps_tdma_du_adj_type =
- 14;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 16);
- coex_dm->ps_tdma_du_adj_type =
- 16;
- }
- } else if (result == 1) {
- if (coex_dm->cur_ps_tdma == 8) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 6);
- coex_dm->ps_tdma_du_adj_type =
- 6;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 5);
- coex_dm->ps_tdma_du_adj_type =
- 5;
- } else if (coex_dm->cur_ps_tdma == 16) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 14);
- coex_dm->ps_tdma_du_adj_type =
- 14;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 13);
- coex_dm->ps_tdma_du_adj_type =
- 13;
- }
- }
- } else {
- if (coex_dm->cur_ps_tdma == 5) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 71);
- coex_dm->ps_tdma_du_adj_type = 71;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 2);
- coex_dm->ps_tdma_du_adj_type = 2;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 3);
- coex_dm->ps_tdma_du_adj_type = 3;
- } else if (coex_dm->cur_ps_tdma == 8) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 4);
- coex_dm->ps_tdma_du_adj_type = 4;
- }
- if (coex_dm->cur_ps_tdma == 13) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 9);
- coex_dm->ps_tdma_du_adj_type = 9;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 10);
- coex_dm->ps_tdma_du_adj_type = 10;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 11);
- coex_dm->ps_tdma_du_adj_type = 11;
- } else if (coex_dm->cur_ps_tdma == 16) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 12);
- coex_dm->ps_tdma_du_adj_type = 12;
- }
-
- if (result == -1) {
- if (coex_dm->cur_ps_tdma == 71) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 1);
- coex_dm->ps_tdma_du_adj_type =
- 1;
- } else if (coex_dm->cur_ps_tdma == 1) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 2);
- coex_dm->ps_tdma_du_adj_type =
- 2;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 4);
- coex_dm->ps_tdma_du_adj_type =
- 4;
- } else if (coex_dm->cur_ps_tdma == 9) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 10);
- coex_dm->ps_tdma_du_adj_type =
- 10;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 12);
- coex_dm->ps_tdma_du_adj_type =
- 12;
- }
- } else if (result == 1) {
- if (coex_dm->cur_ps_tdma == 4) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 2);
- coex_dm->ps_tdma_du_adj_type =
- 2;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 1);
- coex_dm->ps_tdma_du_adj_type =
- 1;
- } else if (coex_dm->cur_ps_tdma == 1) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 71);
- coex_dm->ps_tdma_du_adj_type =
- 71;
- } else if (coex_dm->cur_ps_tdma == 12) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 10);
- coex_dm->ps_tdma_du_adj_type =
- 10;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 9);
- coex_dm->ps_tdma_du_adj_type =
- 9;
- }
- }
- }
- } else if (max_interval == 2) {
- if (tx_pause) {
- if (coex_dm->cur_ps_tdma == 1) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 6);
- coex_dm->ps_tdma_du_adj_type = 6;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 6);
- coex_dm->ps_tdma_du_adj_type = 6;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 7);
- coex_dm->ps_tdma_du_adj_type = 7;
- } else if (coex_dm->cur_ps_tdma == 4) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 8);
- coex_dm->ps_tdma_du_adj_type = 8;
- }
- if (coex_dm->cur_ps_tdma == 9) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 14);
- coex_dm->ps_tdma_du_adj_type = 14;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 14);
- coex_dm->ps_tdma_du_adj_type = 14;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 15);
- coex_dm->ps_tdma_du_adj_type = 15;
- } else if (coex_dm->cur_ps_tdma == 12) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 16);
- coex_dm->ps_tdma_du_adj_type = 16;
- }
- if (result == -1) {
- if (coex_dm->cur_ps_tdma == 5) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 6);
- coex_dm->ps_tdma_du_adj_type =
- 6;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 8);
- coex_dm->ps_tdma_du_adj_type =
- 8;
- } else if (coex_dm->cur_ps_tdma == 13) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 14);
- coex_dm->ps_tdma_du_adj_type =
- 14;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 16);
- coex_dm->ps_tdma_du_adj_type =
- 16;
- }
- } else if (result == 1) {
- if (coex_dm->cur_ps_tdma == 8) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 6);
- coex_dm->ps_tdma_du_adj_type =
- 6;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 6);
- coex_dm->ps_tdma_du_adj_type =
- 6;
- } else if (coex_dm->cur_ps_tdma == 16) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 14);
- coex_dm->ps_tdma_du_adj_type =
- 14;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 14);
- coex_dm->ps_tdma_du_adj_type =
- 14;
- }
- }
- } else {
- if (coex_dm->cur_ps_tdma == 5) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 2);
- coex_dm->ps_tdma_du_adj_type = 2;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 2);
- coex_dm->ps_tdma_du_adj_type = 2;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 3);
- coex_dm->ps_tdma_du_adj_type = 3;
- } else if (coex_dm->cur_ps_tdma == 8) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 4);
- coex_dm->ps_tdma_du_adj_type = 4;
- }
- if (coex_dm->cur_ps_tdma == 13) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 10);
- coex_dm->ps_tdma_du_adj_type = 10;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 10);
- coex_dm->ps_tdma_du_adj_type = 10;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 11);
- coex_dm->ps_tdma_du_adj_type = 11;
- } else if (coex_dm->cur_ps_tdma == 16) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 12);
- coex_dm->ps_tdma_du_adj_type = 12;
- }
- if (result == -1) {
- if (coex_dm->cur_ps_tdma == 1) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 2);
- coex_dm->ps_tdma_du_adj_type =
- 2;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 4);
- coex_dm->ps_tdma_du_adj_type =
- 4;
- } else if (coex_dm->cur_ps_tdma == 9) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 10);
- coex_dm->ps_tdma_du_adj_type =
- 10;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 12);
- coex_dm->ps_tdma_du_adj_type =
- 12;
- }
- } else if (result == 1) {
- if (coex_dm->cur_ps_tdma == 4) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 2);
- coex_dm->ps_tdma_du_adj_type =
- 2;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 2);
- coex_dm->ps_tdma_du_adj_type =
- 2;
- } else if (coex_dm->cur_ps_tdma == 12) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 10);
- coex_dm->ps_tdma_du_adj_type =
- 10;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 10);
- coex_dm->ps_tdma_du_adj_type =
- 10;
- }
- }
- }
- } else if (max_interval == 3) {
- if (tx_pause) {
- if (coex_dm->cur_ps_tdma == 1) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 7);
- coex_dm->ps_tdma_du_adj_type = 7;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 7);
- coex_dm->ps_tdma_du_adj_type = 7;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 7);
- coex_dm->ps_tdma_du_adj_type = 7;
- } else if (coex_dm->cur_ps_tdma == 4) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 8);
- coex_dm->ps_tdma_du_adj_type = 8;
- }
- if (coex_dm->cur_ps_tdma == 9) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 15);
- coex_dm->ps_tdma_du_adj_type = 15;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 15);
- coex_dm->ps_tdma_du_adj_type = 15;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 15);
- coex_dm->ps_tdma_du_adj_type = 15;
- } else if (coex_dm->cur_ps_tdma == 12) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 16);
- coex_dm->ps_tdma_du_adj_type = 16;
- }
- if (result == -1) {
- if (coex_dm->cur_ps_tdma == 5) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 8);
- coex_dm->ps_tdma_du_adj_type =
- 8;
- } else if (coex_dm->cur_ps_tdma == 13) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 16);
- coex_dm->ps_tdma_du_adj_type =
- 16;
- }
- } else if (result == 1) {
- if (coex_dm->cur_ps_tdma == 8) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 16) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- }
- }
- } else {
- if (coex_dm->cur_ps_tdma == 5) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 3);
- coex_dm->ps_tdma_du_adj_type = 3;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 3);
- coex_dm->ps_tdma_du_adj_type = 3;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 3);
- coex_dm->ps_tdma_du_adj_type = 3;
- } else if (coex_dm->cur_ps_tdma == 8) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 4);
- coex_dm->ps_tdma_du_adj_type = 4;
- }
- if (coex_dm->cur_ps_tdma == 13) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 11);
- coex_dm->ps_tdma_du_adj_type = 11;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 11);
- coex_dm->ps_tdma_du_adj_type = 11;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 11);
- coex_dm->ps_tdma_du_adj_type = 11;
- } else if (coex_dm->cur_ps_tdma == 16) {
- halbtc8723b2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 12);
- coex_dm->ps_tdma_du_adj_type = 12;
- }
- if (result == -1) {
- if (coex_dm->cur_ps_tdma == 1) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 4);
- coex_dm->ps_tdma_du_adj_type =
- 4;
- } else if (coex_dm->cur_ps_tdma == 9) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 12);
- coex_dm->ps_tdma_du_adj_type =
- 12;
- }
- } else if (result == 1) {
- if (coex_dm->cur_ps_tdma == 4) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 12) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8723b2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- }
- }
- }
- }
- }
-
- /* if current PsTdma not match with the recorded one (when scan, dhcp...), */
- /* then we have to adjust it back to the previous record one. */
- if (coex_dm->cur_ps_tdma != coex_dm->ps_tdma_du_adj_type) {
- boolean scan = false, link = false, roam = false;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], PsTdma type dismatch!!!, cur_ps_tdma=%d, recordPsTdma=%d\n",
- coex_dm->cur_ps_tdma, coex_dm->ps_tdma_du_adj_type);
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
-
- if (!scan && !link && !roam)
- halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- coex_dm->ps_tdma_du_adj_type);
- else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n");
- BTC_TRACE(trace_buf);
- }
- }
-}
-
-/* SCO only or SCO+PAN(HS) */
-void halbtc8723b2ant_action_sco(IN struct btc_coexist *btcoexist)
-{
- static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state, bt_rssi_state;
- u32 wifi_bw;
-
- wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state, 2, 15, 0);
- bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
- BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES -
- coex_dm->switch_thres_offset, 0);
-
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
-
- halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
-
- halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 4);
-
- if (BTC_RSSI_HIGH(bt_rssi_state))
- halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- else
- halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- if (BTC_WIFI_BW_LEGACY == wifi_bw) /* for SCO quality at 11b/g mode */
- halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
- else /* for SCO quality & wifi performance balance at 11n mode */
- halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
-
- halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
- halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 0); /* for voice quality */
-
- /* sw mechanism */
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8723b2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
- true, 0x4);
- } else {
- halbtc8723b2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
- true, 0x4);
- }
- } else {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8723b2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
- true, 0x4);
- } else {
- halbtc8723b2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
- true, 0x4);
- }
- }
-}
-
-
-void halbtc8723b2ant_action_hid(IN struct btc_coexist *btcoexist)
-{
- static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state, bt_rssi_state;
- u32 wifi_bw;
-
- wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state, 2, 15, 0);
- bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
- BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES -
- coex_dm->switch_thres_offset, 0);
-
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
-
- halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
-
- halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
- if (BTC_RSSI_HIGH(bt_rssi_state))
- halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- else
- halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- if (BTC_WIFI_BW_LEGACY == wifi_bw) /* for HID at 11b/g mode */
- halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
- else /* for HID quality & wifi performance balance at 11n mode */
- halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 9);
-
- halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
-
- if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH))
- halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9);
- else
- halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13);
-
- /* sw mechanism */
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8723b2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8723b2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- } else {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8723b2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8723b2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- }
-}
-
-/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */
-void halbtc8723b2ant_action_a2dp(IN struct btc_coexist *btcoexist)
-{
- static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW,
- prewifi_rssi_state1 = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state;
- u32 wifi_bw;
- u8 ap_num = 0;
-
- wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state, 2, 15, 0);
- wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state1, 2,
- BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES -
- coex_dm->switch_thres_offset, 0);
- bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
- BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES -
- coex_dm->switch_thres_offset, 0);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, &ap_num);
-
- /* define the office environment */
- if ((ap_num >= 10) && BTC_RSSI_HIGH(wifi_rssi_state1) &&
- BTC_RSSI_HIGH(bt_rssi_state)) {
- /* dbg_print(" AP#>10(%d)\n", ap_num); */
- halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
-
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff,
- 0x0);
- halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
- 0x8);
- halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
- halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
-
- halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
-
- /* sw mechanism */
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- halbtc8723b2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
- true, 0x18);
- } else {
- halbtc8723b2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
- true, 0x18);
- }
- return;
-
- }
-
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
- halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
-
- halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
- if (BTC_RSSI_HIGH(bt_rssi_state))
- halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- else
- halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
-
- if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) {
- halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
- halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- } else {
- halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 13);
- halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50,
- 0x4);
- }
-
-
- if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH))
- halbtc8723b2ant_tdma_duration_adjust(btcoexist, false, false,
- 1);
- else
- halbtc8723b2ant_tdma_duration_adjust(btcoexist, false, true, 1);
-
- /* sw mechanism */
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8723b2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8723b2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- } else {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8723b2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8723b2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- }
-}
-
-void halbtc8723b2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist)
-{
- static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW,
- prewifi_rssi_state1 = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state;
- u32 wifi_bw;
-
- wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state, 2, 15, 0);
- wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state1, 2,
- BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES -
- coex_dm->switch_thres_offset, 0);
- bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
- BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES -
- coex_dm->switch_thres_offset, 0);
-
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
-
- halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
-
- halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
- if (BTC_RSSI_HIGH(bt_rssi_state))
- halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- else
- halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) {
- halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
- halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- } else {
- halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 13);
- halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50,
- 0x4);
- }
-
- halbtc8723b2ant_tdma_duration_adjust(btcoexist, false, true, 2);
-
- /* sw mechanism */
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8723b2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8723b2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- } else {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8723b2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8723b2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- }
-}
-
-void halbtc8723b2ant_action_pan_edr(IN struct btc_coexist *btcoexist)
-{
- static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW,
- prewifi_rssi_state1 = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state;
- u32 wifi_bw;
-
- wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state, 2, 15, 0);
- wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state1, 2,
- BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES -
- coex_dm->switch_thres_offset, 0);
- bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
- BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES -
- coex_dm->switch_thres_offset, 0);
-
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
-
- halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
-
- halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
- if (BTC_RSSI_HIGH(bt_rssi_state))
- halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- else
- halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) {
- halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 10);
- halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- } else {
- halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 13);
- halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50,
- 0x4);
- }
-
- if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH))
- halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 1);
- else
- halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
-
- /* sw mechanism */
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8723b2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8723b2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- } else {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8723b2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8723b2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- }
-}
-
-
-/* PAN(HS) only */
-void halbtc8723b2ant_action_pan_hs(IN struct btc_coexist *btcoexist)
-{
- static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW,
- prewifi_rssi_state1 = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state;
- u32 wifi_bw;
-
- wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state, 2, 15, 0);
- wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state1, 2,
- BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES -
- coex_dm->switch_thres_offset, 0);
- bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
- BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES -
- coex_dm->switch_thres_offset, 0);
-
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
-
- halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
-
- halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
- if (BTC_RSSI_HIGH(bt_rssi_state))
- halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- else
- halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
-
- halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
- halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8723b2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8723b2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- } else {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8723b2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8723b2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- }
-}
-
-/* PAN(EDR)+A2DP */
-void halbtc8723b2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist)
-{
- static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW,
- prewifi_rssi_state1 = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state;
- u8 ap_num = 0;
- u32 wifi_bw;
-
- wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state, 2, 15, 0);
- wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state1, 2,
- BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES -
- coex_dm->switch_thres_offset, 0);
- bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
- BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES -
- coex_dm->switch_thres_offset, 0);
-
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
-
- halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
-
- halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
- if (BTC_RSSI_HIGH(bt_rssi_state))
- halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- else
- halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state))
- halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- else
- halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50,
- 0x4);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
- &ap_num);
-
- if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 12);
-
- if(ap_num < 10)
- halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, false, 1);
- else
- halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, false, 3);
-
- } else {
- halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 13);
- if(ap_num < 10)
- halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, true, 1);
- else
- halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, true, 3);
- }
-
- /* sw mechanism */
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8723b2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8723b2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- } else {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8723b2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8723b2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- }
-}
-
-void halbtc8723b2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist)
-{
- static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW,
- prewifi_rssi_state1 = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state;
- u32 wifi_bw;
-
- wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state, 2, 15, 0);
- wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state1, 2,
- BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES -
- coex_dm->switch_thres_offset, 0);
- bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
- BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES -
- coex_dm->switch_thres_offset, 0);
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
-
- if (BTC_RSSI_HIGH(bt_rssi_state))
- halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- else
- halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) {
- halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
- halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- } else {
- halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 14);
- halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50,
- 0x4);
- }
-
- if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC,
- 3);
- /* halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 11); */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1,
- 0xfffff, 0x780);
- } else {
- halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC,
- 6);
- /* halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1,
- 0xfffff, 0x0);
- }
- halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, false, 2);
- } else {
- halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
- /* halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 14); */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff,
- 0x0);
- halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, true, 2);
- }
-
- /* sw mechanism */
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8723b2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8723b2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- } else {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8723b2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8723b2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- }
-}
-
-/* HID+A2DP+PAN(EDR) */
-void halbtc8723b2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist)
-{
- static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW,
- prewifi_rssi_state1 = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state;
- u32 wifi_bw;
-
- wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state, 2, 15, 0);
- wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state1, 2,
- BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES -
- coex_dm->switch_thres_offset, 0);
- bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
- BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES -
- coex_dm->switch_thres_offset, 0);
-
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
-
- halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
-
- halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
- if (BTC_RSSI_HIGH(bt_rssi_state))
- halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- else
- halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) {
- halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
- halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- } else {
- halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 14);
- halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50,
- 0x4);
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- if (BTC_WIFI_BW_HT40 == wifi_bw)
- halbtc8723b2ant_tdma_duration_adjust(btcoexist, true,
- true, 3);
- else
- halbtc8723b2ant_tdma_duration_adjust(btcoexist, true,
- false, 3);
- } else
- halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, true, 3);
-
- /* sw mechanism */
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8723b2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8723b2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- } else {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8723b2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8723b2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- }
-}
-
-void halbtc8723b2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist)
-{
- static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW,
- prewifi_rssi_state1 = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state;
- u32 wifi_bw;
- u8 ap_num = 0;
-
- wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state, 2, 15, 0);
- /* bt_rssi_state = halbtc8723b2ant_bt_rssi_state(2, 29, 0); */
- wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state1, 2,
- BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES -
- coex_dm->switch_thres_offset, 0);
- bt_rssi_state = halbtc8723b2ant_bt_rssi_state(&pre_bt_rssi_state, 3,
- BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES -
- coex_dm->switch_thres_offset, 37);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
- &ap_num);
-
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
-
- halbtc8723b2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true, 0x5);
-
- halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- if (BTC_WIFI_BW_LEGACY == wifi_bw) {
- if (BTC_RSSI_HIGH(bt_rssi_state))
- halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- else if (BTC_RSSI_MEDIUM(bt_rssi_state))
- halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- else
- halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
- } else {
- /* only 802.11N mode we have to dec bt power to 4 degree */
- if (BTC_RSSI_HIGH(bt_rssi_state)) {
- /* need to check ap Number of Not */
- if (ap_num < 10)
- halbtc8723b2ant_dec_bt_pwr(btcoexist,
- NORMAL_EXEC, 4);
- else
- halbtc8723b2ant_dec_bt_pwr(btcoexist,
- NORMAL_EXEC, 2);
- } else if (BTC_RSSI_MEDIUM(bt_rssi_state))
- halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- else
- halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
- }
-
- if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) {
- halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
- halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- } else {
- halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 14);
- halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50,
- 0x4);
- }
-
- if(BTC_RSSI_HIGH(bt_rssi_state)) {
- if(ap_num < 10)
- halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, false, 1);
- else
- halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, false, 3);
- } else {
- halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 18);
- btcoexist->btc_write_1byte(btcoexist, 0x456, 0x38);
- btcoexist->btc_write_2byte(btcoexist, 0x42a, 0x0808);
- btcoexist->btc_write_4byte(btcoexist, 0x430, 0x0);
- btcoexist->btc_write_4byte(btcoexist, 0x434, 0x01010000);
-
- if(ap_num < 10)
- halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, true, 1);
- else
- halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, true, 3);
- }
-
- /* sw mechanism */
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8723b2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8723b2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- } else {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8723b2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8723b2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- }
-}
-
-void halbtc8723b2ant_action_bt_whck_test(IN struct btc_coexist *btcoexist)
-{
- halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- /* sw all off */
- halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
-
- halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
-
- halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
- halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-}
-
-void halbtc8723b2ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist)
-{
- halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
- halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- /* sw all off */
- halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, false);
- halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
-
- /* hw all off */
- /* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); */
- halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8723b2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
- halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
-}
-
-void halbtc8723b2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist)
-{
- u8 algorithm = 0;
- u32 num_of_wifi_link = 0;
- u32 wifi_link_status = 0;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean miracast_plus_bt = false;
- boolean scan = false, link = false, roam = false;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism()===>\n");
- BTC_TRACE(trace_buf);
-
- if (btcoexist->manual_control) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- if (coex_sta->under_ips) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], wifi is under IPS !!!\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- if (coex_sta->bt_whck_test) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is under WHCK TEST!!!\n");
- BTC_TRACE(trace_buf);
- halbtc8723b2ant_action_bt_whck_test(btcoexist);
- return;
- }
-
- algorithm = halbtc8723b2ant_action_algorithm(btcoexist);
- if (coex_sta->c2h_bt_inquiry_page &&
- (BT_8723B_2ANT_COEX_ALGO_PANHS != algorithm)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is under inquiry/page scan !!\n");
- BTC_TRACE(trace_buf);
- halbtc8723b2ant_action_bt_inquiry(btcoexist);
- return;
- } else {
- /*
- if(coex_dm->need_recover0x948)
- {
- coex_dm->need_recover0x948 = false;
- btcoexist->btc_write_4byte(btcoexist, 0x948, coex_dm->backup0x948);
- }
- */
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
-
- if (scan || link || roam) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], WiFi is under Link Process !!\n");
- BTC_TRACE(trace_buf);
- halbtc8723b2ant_action_wifi_link_process(btcoexist);
- return;
- }
-
- /* for P2P */
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
- num_of_wifi_link = wifi_link_status >> 16;
-
- if ((num_of_wifi_link >= 2) ||
- (wifi_link_status & WIFI_P2P_GO_CONNECTED)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n",
- num_of_wifi_link, wifi_link_status);
- BTC_TRACE(trace_buf);
-
- if (bt_link_info->bt_link_exist)
- miracast_plus_bt = true;
- else
- miracast_plus_bt = false;
-
- btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
- &miracast_plus_bt);
- halbtc8723b2ant_action_wifi_multi_port(btcoexist);
-
- return;
- } else {
- miracast_plus_bt = false;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
- &miracast_plus_bt);
- }
-
- coex_dm->cur_algorithm = algorithm;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Algorithm = %d\n",
- coex_dm->cur_algorithm);
- BTC_TRACE(trace_buf);
-
- if (halbtc8723b2ant_is_common_action(btcoexist)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant common.\n");
- BTC_TRACE(trace_buf);
- coex_dm->auto_tdma_adjust = false;
- } else {
- if (coex_dm->cur_algorithm != coex_dm->pre_algorithm) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], pre_algorithm=%d, cur_algorithm=%d\n",
- coex_dm->pre_algorithm, coex_dm->cur_algorithm);
- BTC_TRACE(trace_buf);
- coex_dm->auto_tdma_adjust = false;
- }
- switch (coex_dm->cur_algorithm) {
- case BT_8723B_2ANT_COEX_ALGO_SCO:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = SCO.\n");
- BTC_TRACE(trace_buf);
- halbtc8723b2ant_action_sco(btcoexist);
- break;
- case BT_8723B_2ANT_COEX_ALGO_HID:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = HID.\n");
- BTC_TRACE(trace_buf);
- halbtc8723b2ant_action_hid(btcoexist);
- break;
- case BT_8723B_2ANT_COEX_ALGO_A2DP:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = A2DP.\n");
- BTC_TRACE(trace_buf);
- halbtc8723b2ant_action_a2dp(btcoexist);
- break;
- case BT_8723B_2ANT_COEX_ALGO_A2DP_PANHS:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n");
- BTC_TRACE(trace_buf);
- halbtc8723b2ant_action_a2dp_pan_hs(btcoexist);
- break;
- case BT_8723B_2ANT_COEX_ALGO_PANEDR:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n");
- BTC_TRACE(trace_buf);
- halbtc8723b2ant_action_pan_edr(btcoexist);
- break;
- case BT_8723B_2ANT_COEX_ALGO_PANHS:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = HS mode.\n");
- BTC_TRACE(trace_buf);
- halbtc8723b2ant_action_pan_hs(btcoexist);
- break;
- case BT_8723B_2ANT_COEX_ALGO_PANEDR_A2DP:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n");
- BTC_TRACE(trace_buf);
- halbtc8723b2ant_action_pan_edr_a2dp(btcoexist);
- break;
- case BT_8723B_2ANT_COEX_ALGO_PANEDR_HID:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n");
- BTC_TRACE(trace_buf);
- halbtc8723b2ant_action_pan_edr_hid(btcoexist);
- break;
- case BT_8723B_2ANT_COEX_ALGO_HID_A2DP_PANEDR:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n");
- BTC_TRACE(trace_buf);
- halbtc8723b2ant_action_hid_a2dp_pan_edr(
- btcoexist);
- break;
- case BT_8723B_2ANT_COEX_ALGO_HID_A2DP:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n");
- BTC_TRACE(trace_buf);
- halbtc8723b2ant_action_hid_a2dp(btcoexist);
- break;
- default:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n");
- BTC_TRACE(trace_buf);
- halbtc8723b2ant_coex_all_off(btcoexist);
- break;
- }
- coex_dm->pre_algorithm = coex_dm->cur_algorithm;
- }
-}
-
-void halbtc8723b2ant_wifi_off_hw_cfg(IN struct btc_coexist *btcoexist)
-{
- boolean is_in_mp_mode = false;
- u8 h2c_parameter[2] = {0};
- u32 fw_ver = 0;
-
- /* set wlan_act to low */
- btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4);
-
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff,
- 0x780); /* WiFi goto standby while GNT_BT 0-->1 */
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
- if (fw_ver >= 0x180000) {
- /* Use H2C to set GNT_BT to HIGH */
- h2c_parameter[0] = 1;
- btcoexist->btc_fill_h2c(btcoexist, 0x6E, 1, h2c_parameter);
- } else
- btcoexist->btc_write_1byte(btcoexist, 0x765, 0x18);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_IS_IN_MP_MODE,
- &is_in_mp_mode);
- if (!is_in_mp_mode)
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20,
- 0x0); /* BT select s0/s1 is controlled by BT */
- else
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20,
- 0x1); /* BT select s0/s1 is controlled by WiFi */
-}
-
-void halbtc8723b2ant_init_hw_config(IN struct btc_coexist *btcoexist,
- IN boolean back_up)
-{
- u8 u8tmp = 0;
- u32 vendor;
-
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], 2Ant Init HW Config!!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_get(btcoexist, BTC_GET_U4_VENDOR, &vendor);
- if (vendor == BTC_VENDOR_LENOVO)
- coex_dm->switch_thres_offset = 0;
- else if (vendor == BTC_VENDOR_ASUS)
- coex_dm->switch_thres_offset = 0;
- else
- coex_dm->switch_thres_offset = 20;
-
- /* 0xf0[15:12] --> Chip Cut information */
- coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist,
- 0xf1) & 0xf0) >> 4;
-
- /* backup rf 0x1e value */
- coex_dm->bt_rf_0x1e_backup =
- btcoexist->btc_get_rf_reg(btcoexist, BTC_RF_A, 0x1e, 0xfffff);
-
- /* 0x790[5:0]=0x5 */
- u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790);
- u8tmp &= 0xc0;
- u8tmp |= 0x5;
- btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp);
-
- /* Antenna config */
- halbtc8723b2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, true,
- false);
- coex_sta->dis_ver_info_cnt = 0;
-
- /* PTA parameter */
- halbtc8723b2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
-
- /* Enable counter statistics */
- btcoexist->btc_write_1byte(btcoexist, 0x76e,
- 0x4); /* 0x76e[3] =1, WLAN_Act control by PTA */
- btcoexist->btc_write_1byte(btcoexist, 0x778, 0x3);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1);
-}
-
-/* ************************************************************
- * work around function start with wa_halbtc8723b2ant_
- * ************************************************************
- * ************************************************************
- * extern function start with ex_halbtc8723b2ant_
- * ************************************************************ */
-void ex_halbtc8723b2ant_power_on_setting(IN struct btc_coexist *btcoexist)
-{
- struct btc_board_info *board_info = &btcoexist->board_info;
- u16 u16tmp = 0x0;
- u32 value = 0;
- u32 u32tmp_1[4];
-
- btcoexist->btc_write_1byte(btcoexist, 0x67, 0x20);
-
- /* enable BB, REG_SYS_FUNC_EN such that we can write 0x948 correctly. */
- u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2);
- btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1));
- DbgPrint("--- TEST 5 ---\n");
-
- btcoexist->btc_write_4byte(btcoexist, 0x948, 0x0);
-
- if (btcoexist->chip_interface == BTC_INTF_USB) {
- /* fixed at S0 for USB interface */
- board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT;
- } else {
- /* for PCIE and SDIO interface, we check efuse 0xc3[6] */
- if (board_info->single_ant_path == 0) {
- /* set to S1 */
- board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;
- } else if (board_info->single_ant_path == 1) {
- /* set to S0 */
- board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT;
- }
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_ANTPOSREGRISTRY_CTRL,
- &value);
- }
-}
-
-void ex_halbtc8723b2ant_pre_load_firmware(IN struct btc_coexist *btcoexist)
-{
- struct btc_board_info *board_info = &btcoexist->board_info;
- u8 u8tmp = 0x4; /* Set BIT2 by default since it's 2ant case */
-
- /* */
- /* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */
- /* Local setting bit define */
- /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */
- /* BIT1: "0" for internal switch; "1" for external switch */
- /* BIT2: "0" for one antenna; "1" for two antenna */
- /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */
- if (btcoexist->chip_interface == BTC_INTF_USB) {
- /* fixed at S0 for USB interface */
- u8tmp |= 0x1; /* antenna inverse */
- btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp);
- } else {
- /* for PCIE and SDIO interface, we check efuse 0xc3[6] */
- if (board_info->single_ant_path == 0) {
- } else if (board_info->single_ant_path == 1) {
- /* set to S0 */
- u8tmp |= 0x1; /* antenna inverse */
- }
-
- if (btcoexist->chip_interface == BTC_INTF_PCI)
- btcoexist->btc_write_local_reg_1byte(btcoexist, 0x384,
- u8tmp);
- else if (btcoexist->chip_interface == BTC_INTF_SDIO)
- btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60,
- u8tmp);
- }
-}
-
-void ex_halbtc8723b2ant_init_hw_config(IN struct btc_coexist *btcoexist,
- IN boolean wifi_only)
-{
- halbtc8723b2ant_init_hw_config(btcoexist, true);
-}
-
-void ex_halbtc8723b2ant_init_coex_dm(IN struct btc_coexist *btcoexist)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Coex Mechanism Init!!\n");
- BTC_TRACE(trace_buf);
-
- halbtc8723b2ant_init_coex_dm(btcoexist);
-}
-
-void ex_halbtc8723b2ant_display_coex_info(IN struct btc_coexist *btcoexist)
-{
- struct btc_board_info *board_info = &btcoexist->board_info;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- u8 *cli_buf = btcoexist->cli_buf;
- u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0;
- u32 u32tmp[4];
- u32 fa_of_dm, fa_cck;
- u32 fw_ver = 0, bt_patch_ver = 0;
- static u8 pop_report_in_10s = 0;
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ============[BT Coexist info]============");
- CL_PRINTF(cli_buf);
-
- if (btcoexist->manual_control) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ============[Under Manual Control]============");
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ==========================================");
- CL_PRINTF(cli_buf);
- }
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ",
- "Ant PG number/ Ant mechanism:",
- board_info->pg_ant_num, board_info->btdm_ant_num);
- CL_PRINTF(cli_buf);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %d_%x/ 0x%x/ 0x%x(%d)/ %c",
- "Version Coex/ Fw/ Patch/ Cut",
- glcoex_ver_date_8723b_2ant, glcoex_ver_8723b_2ant, fw_ver,
- bt_patch_ver, bt_patch_ver, coex_sta->cut_version + 65);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ",
- "Wifi channel informed to BT",
- coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
- coex_dm->wifi_chnl_info[2]);
- CL_PRINTF(cli_buf);
-
- /* wifi status */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Wifi Status]============");
- CL_PRINTF(cli_buf);
- btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[BT Status]============");
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
- "BT Abnormal scan",
- (coex_sta->bt_abnormal_scan) ? "Yes" : "No");
- CL_PRINTF(cli_buf);
-
- pop_report_in_10s++;
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d/ %d] ",
- "BT [status/ rssi/ retryCnt/ popCnt]",
- ((coex_sta->bt_disabled) ? ("disabled") : ((
- coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan")
- : ((BT_8723B_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
- coex_dm->bt_status) ? "non-connected idle" :
- ((BT_8723B_2ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)
- ? "connected-idle" : "busy")))),
- coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt,
- coex_sta->pop_event_cnt);
- CL_PRINTF(cli_buf);
-
- if (pop_report_in_10s >= 5) {
- coex_sta->pop_event_cnt = 0;
- pop_report_in_10s = 0;
- }
-
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %d / %d / %d / %d / %d / %d",
- "SCO/HID/PAN/A2DP/NameReq/WHQL",
- bt_link_info->sco_exist, bt_link_info->hid_exist,
- bt_link_info->pan_exist, bt_link_info->a2dp_exist,
- coex_sta->c2h_bt_remote_name_req,
- coex_sta->bt_whck_test);
- CL_PRINTF(cli_buf);
-
- {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
- "BT Role",
- (bt_link_info->slave_role) ? "Slave" : "Master");
- CL_PRINTF(cli_buf);
- }
-
- bt_info_ext = coex_sta->bt_info_ext;
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d",
- "A2DP Rate/Bitpool",
- (bt_info_ext & BIT(0)) ? "BR" : "EDR", coex_sta->a2dp_bit_pool);
- CL_PRINTF(cli_buf);
-
- for (i = 0; i < BT_INFO_SRC_8723B_2ANT_MAX; i++) {
- if (coex_sta->bt_info_c2h_cnt[i]) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)",
- glbt_info_src_8723b_2ant[i],
- coex_sta->bt_info_c2h[i][0],
- coex_sta->bt_info_c2h[i][1],
- coex_sta->bt_info_c2h[i][2],
- coex_sta->bt_info_c2h[i][3],
- coex_sta->bt_info_c2h[i][4],
- coex_sta->bt_info_c2h[i][5],
- coex_sta->bt_info_c2h[i][6],
- coex_sta->bt_info_c2h_cnt[i]);
- CL_PRINTF(cli_buf);
- }
- }
-
- /* Sw mechanism */
- if (btcoexist->manual_control)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Sw mechanism] (before Manual)============");
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Sw mechanism]============");
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ",
- "SM1[ShRf/ LpRA/ LimDig]",
- coex_dm->cur_rf_rx_lpf_shrink, coex_dm->cur_low_penalty_ra,
- coex_dm->limited_dig);
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ",
- "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]",
- coex_dm->cur_agc_table_en, coex_dm->cur_adc_back_off,
- coex_dm->cur_dac_swing_on, coex_dm->cur_dac_swing_lvl);
- CL_PRINTF(cli_buf);
-
- /* Fw mechanism */
- if (btcoexist->manual_control)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Fw mechanism] (before Manual) ============");
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Fw mechanism]============");
-
- ps_tdma_case = coex_dm->cur_ps_tdma;
-
- if (coex_dm->is_switch_to_1dot5_ant)
- ps_tdma_case = ps_tdma_case + 100;
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (%s,%s)",
- "PS TDMA",
- coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],
- coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],
- coex_dm->ps_tdma_para[4], ps_tdma_case,
- (coex_dm->cur_ps_tdma_on ? "On" : "Off"),
- (coex_dm->auto_tdma_adjust ? "Adj" : "Fix"));
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
- "Coex Table Type",
- coex_sta->coex_table_type);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ",
- "DecBtPwr/ IgnWlanAct",
- coex_dm->cur_bt_dec_pwr_lvl, coex_dm->cur_ignore_wlan_act);
- CL_PRINTF(cli_buf);
-
- /* Hw setting */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Hw setting]============");
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x",
- "RF-A, 0x1e initVal",
- coex_dm->bt_rf_0x1e_backup);
- CL_PRINTF(cli_buf);
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x880);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
- "0x778/0x880[29:25]",
- u8tmp[0], (u32tmp[0] & 0x3e000000) >> 25);
- CL_PRINTF(cli_buf);
-
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x948);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x67);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x765);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
- "0x948/ 0x67[5] / 0x765",
- u32tmp[0], ((u8tmp[0] & 0x20) >> 5), u8tmp[1]);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x92c);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x930);
- u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x944);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
- "0x92c[1:0]/ 0x930[7:0]/0x944[1:0]",
- u32tmp[0] & 0x3, u32tmp[1] & 0xff, u32tmp[2] & 0x3);
- CL_PRINTF(cli_buf);
-
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x39);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40);
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c);
- u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0x64);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
- "0x38[11]/0x40/0x4c[24:23]/0x64[0]",
- ((u8tmp[0] & 0x8) >> 3), u8tmp[1],
- ((u32tmp[0] & 0x01800000) >> 23), u8tmp[2] & 0x1);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
- "0x550(bcn ctrl)/0x522",
- u32tmp[0], u8tmp[0]);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x49c);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
- "0xc50(dig)/0x49c(null-drop)",
- u32tmp[0] & 0xff, u8tmp[0]);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xda0);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xda4);
- u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0xda8);
- u32tmp[3] = btcoexist->btc_read_4byte(btcoexist, 0xcf0);
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xa5b);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xa5c);
-
- fa_of_dm = ((u32tmp[0] & 0xffff0000) >> 16) + ((u32tmp[1] & 0xffff0000)
- >> 16) + (u32tmp[1] & 0xffff) + (u32tmp[2] & 0xffff) + \
- ((u32tmp[3] & 0xffff0000) >> 16) + (u32tmp[3] &
- 0xffff) ;
- fa_cck = (u8tmp[0] << 8) + u8tmp[1];
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
- "OFDM-CCA/OFDM-FA/CCK-FA",
- u32tmp[0] & 0xffff, fa_of_dm, fa_cck);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
- "CRC_OK CCK/11g/11n/11n-Agg",
- coex_sta->crc_ok_cck, coex_sta->crc_ok_11g,
- coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_agg);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
- "CRC_Err CCK/11g/11n/11n-Agg",
- coex_sta->crc_err_cck, coex_sta->crc_err_11g,
- coex_sta->crc_err_11n, coex_sta->crc_err_11n_agg);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
- u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x6cc);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
- "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)",
- u32tmp[0], u32tmp[1], u32tmp[2], u8tmp[0]);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
- "0x770(high-pri rx/tx)",
- coex_sta->high_priority_rx, coex_sta->high_priority_tx);
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
- "0x774(low-pri rx/tx)",
- coex_sta->low_priority_rx, coex_sta->low_priority_tx);
- CL_PRINTF(cli_buf);
-#if (BT_AUTO_REPORT_ONLY_8723B_2ANT == 1)
- /* halbtc8723b2ant_monitor_bt_ctr(btcoexist); */
-#endif
- btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
-}
-
-
-void ex_halbtc8723b2ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type)
-{
- if (BTC_IPS_ENTER == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], IPS ENTER notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_ips = true;
- halbtc8723b2ant_wifi_off_hw_cfg(btcoexist);
- halbtc8723b2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
- halbtc8723b2ant_coex_all_off(btcoexist);
- } else if (BTC_IPS_LEAVE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], IPS LEAVE notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_ips = false;
- halbtc8723b2ant_init_hw_config(btcoexist, false);
- halbtc8723b2ant_init_coex_dm(btcoexist);
- halbtc8723b2ant_query_bt_info(btcoexist);
- }
-}
-
-void ex_halbtc8723b2ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type)
-{
- if (BTC_LPS_ENABLE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], LPS ENABLE notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_lps = true;
- } else if (BTC_LPS_DISABLE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], LPS DISABLE notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_lps = false;
- }
-}
-
-void ex_halbtc8723b2ant_scan_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- u32 u32tmp;
- u8 u8tmpa, u8tmpb;
-
-
-
- u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x948);
- u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765);
- u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x76e);
-
- if (BTC_SCAN_START == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCAN START notify\n");
- BTC_TRACE(trace_buf);
- halbtc8723b2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, FALSE, FALSE);
- } else if (BTC_SCAN_FINISH == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCAN FINISH notify\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
- &coex_sta->scan_ap_num);
- }
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x76e=0x%x\n",
- u32tmp, u8tmpa, u8tmpb);
- BTC_TRACE(trace_buf);
-}
-
-void ex_halbtc8723b2ant_connect_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- if (BTC_ASSOCIATE_START == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CONNECT START notify\n");
- BTC_TRACE(trace_buf);
- halbtc8723b2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, FALSE, FALSE);
- } else if (BTC_ASSOCIATE_FINISH == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CONNECT FINISH notify\n");
- BTC_TRACE(trace_buf);
- }
-}
-
-void ex_halbtc8723b2ant_media_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- u8 h2c_parameter[3] = {0};
- u32 wifi_bw;
- u8 wifi_central_chnl;
- u8 ap_num = 0;
-
- if (BTC_MEDIA_CONNECT == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], MEDIA connect notify\n");
- BTC_TRACE(trace_buf);
- halbtc8723b2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, FALSE, FALSE);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], MEDIA disconnect notify\n");
- BTC_TRACE(trace_buf);
- }
-
- /* only 2.4G we need to inform bt the chnl mask */
- btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
- &wifi_central_chnl);
- if ((BTC_MEDIA_CONNECT == type) &&
- (wifi_central_chnl <= 14)) {
- h2c_parameter[0] = 0x1;
- h2c_parameter[1] = wifi_central_chnl;
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- if (BTC_WIFI_BW_HT40 == wifi_bw)
- h2c_parameter[2] = 0x30;
- else {
- btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
- &ap_num);
- if (ap_num < 10)
- h2c_parameter[2] = 0x30;
- else
- h2c_parameter[2] = 0x20;
- }
- }
-
- coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
- coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
- coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
-
- btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter);
-}
-
-void ex_halbtc8723b2ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- if (type == BTC_PACKET_DHCP) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], DHCP Packet notify\n");
- BTC_TRACE(trace_buf);
- }
-}
-
-void ex_halbtc8723b2ant_bt_info_notify(IN struct btc_coexist *btcoexist,
- IN u8 *tmp_buf, IN u8 length)
-{
- u8 bt_info = 0;
- u8 i, rsp_source = 0;
- boolean bt_busy = false, limited_dig = false;
- boolean wifi_connected = false;
-
- coex_sta->c2h_bt_info_req_sent = false;
-
- rsp_source = tmp_buf[0] & 0xf;
- if (rsp_source >= BT_INFO_SRC_8723B_2ANT_MAX)
- rsp_source = BT_INFO_SRC_8723B_2ANT_WIFI_FW;
- coex_sta->bt_info_c2h_cnt[rsp_source]++;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source,
- length);
- BTC_TRACE(trace_buf);
- for (i = 0; i < length; i++) {
- coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
- if (i == 1)
- bt_info = tmp_buf[i];
- if (i == length - 1) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n",
- tmp_buf[i]);
- BTC_TRACE(trace_buf);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ",
- tmp_buf[i]);
- BTC_TRACE(trace_buf);
- }
- }
-
- if (btcoexist->manual_control) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), return for Manual CTRL<===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- /* if 0xff, it means BT is under WHCK test */
- if (bt_info == 0xff)
- coex_sta->bt_whck_test = true;
- else
- coex_sta->bt_whck_test = false;
-
- if (BT_INFO_SRC_8723B_2ANT_WIFI_FW != rsp_source) {
- coex_sta->bt_retry_cnt = /* [3:0] */
- coex_sta->bt_info_c2h[rsp_source][2] & 0xf;
-
- if (coex_sta->bt_retry_cnt >= 1)
- coex_sta->pop_event_cnt++;
-
- coex_sta->bt_rssi =
- coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10;
-
- coex_sta->bt_info_ext =
- coex_sta->bt_info_c2h[rsp_source][4];
-
- if (coex_sta->bt_info_c2h[rsp_source][2] & 0x20)
- coex_sta->c2h_bt_remote_name_req = true;
- else
- coex_sta->c2h_bt_remote_name_req = false;
-
- if (coex_sta->bt_info_c2h[rsp_source][1] == 0x49) {
- coex_sta->a2dp_bit_pool =
- coex_sta->bt_info_c2h[rsp_source][6];
- } else
- coex_sta->a2dp_bit_pool = 0;
-
- coex_sta->bt_tx_rx_mask = (coex_sta->bt_info_c2h[rsp_source][2]
- & 0x40);
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TX_RX_MASK,
- &coex_sta->bt_tx_rx_mask);
- if (coex_sta->bt_tx_rx_mask) {
- /* BT into is responded by BT FW and BT RF REG 0x3C != 0x01 => Need to switch BT TRx Mask */
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x01\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF,
- 0x3c, 0x01);
- }
-
- /* Here we need to resend some wifi info to BT */
- /* because bt is reset and loss of the info. */
- if ((coex_sta->bt_info_ext & BIT(1))) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- if (wifi_connected)
- ex_halbtc8723b2ant_media_status_notify(
- btcoexist, BTC_MEDIA_CONNECT);
- else
- ex_halbtc8723b2ant_media_status_notify(
- btcoexist, BTC_MEDIA_DISCONNECT);
- }
-
- if ((coex_sta->bt_info_ext & BIT(3))) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n");
- BTC_TRACE(trace_buf);
- halbtc8723b2ant_ignore_wlan_act(btcoexist, FORCE_EXEC,
- false);
- } else {
- /* BT already NOT ignore Wlan active, do nothing here. */
- }
-#if (BT_AUTO_REPORT_ONLY_8723B_2ANT == 0)
- if ((coex_sta->bt_info_ext & BIT(4))) {
- /* BT auto report already enabled, do nothing */
- } else
- halbtc8723b2ant_bt_auto_report(btcoexist, FORCE_EXEC,
- true);
-#endif
- }
-
- /* check BIT2 first ==> check if bt is under inquiry or page scan */
- if (bt_info & BT_INFO_8723B_2ANT_B_INQ_PAGE)
- coex_sta->c2h_bt_inquiry_page = true;
- else
- coex_sta->c2h_bt_inquiry_page = false;
-
- /* set link exist status */
- if (!(bt_info & BT_INFO_8723B_2ANT_B_CONNECTION)) {
- coex_sta->bt_link_exist = false;
- coex_sta->pan_exist = false;
- coex_sta->a2dp_exist = false;
- coex_sta->hid_exist = false;
- coex_sta->sco_exist = false;
- } else { /* connection exists */
- coex_sta->bt_link_exist = true;
- if (bt_info & BT_INFO_8723B_2ANT_B_FTP)
- coex_sta->pan_exist = true;
- else
- coex_sta->pan_exist = false;
- if (bt_info & BT_INFO_8723B_2ANT_B_A2DP)
- coex_sta->a2dp_exist = true;
- else
- coex_sta->a2dp_exist = false;
- if (bt_info & BT_INFO_8723B_2ANT_B_HID)
- coex_sta->hid_exist = true;
- else
- coex_sta->hid_exist = false;
- if (bt_info & BT_INFO_8723B_2ANT_B_SCO_ESCO)
- coex_sta->sco_exist = true;
- else
- coex_sta->sco_exist = false;
-
- if ((coex_sta->hid_exist == false) &&
- (coex_sta->c2h_bt_inquiry_page == false) &&
- (coex_sta->sco_exist == false)) {
- if (coex_sta->high_priority_tx +
- coex_sta->high_priority_rx >= 160) {
- coex_sta->hid_exist = true;
- bt_info = bt_info | 0x28;
- }
- }
- }
-
- halbtc8723b2ant_update_bt_link_info(btcoexist);
-
- if (!(bt_info & BT_INFO_8723B_2ANT_B_CONNECTION)) {
- coex_dm->bt_status = BT_8723B_2ANT_BT_STATUS_NON_CONNECTED_IDLE;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n");
- BTC_TRACE(trace_buf);
- } else if (bt_info ==
- BT_INFO_8723B_2ANT_B_CONNECTION) { /* connection exists but no busy */
- coex_dm->bt_status = BT_8723B_2ANT_BT_STATUS_CONNECTED_IDLE;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n");
- BTC_TRACE(trace_buf);
- } else if ((bt_info & BT_INFO_8723B_2ANT_B_SCO_ESCO) ||
- (bt_info & BT_INFO_8723B_2ANT_B_SCO_BUSY)) {
- coex_dm->bt_status = BT_8723B_2ANT_BT_STATUS_SCO_BUSY;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n");
- BTC_TRACE(trace_buf);
- } else if (bt_info & BT_INFO_8723B_2ANT_B_ACL_BUSY) {
- coex_dm->bt_status = BT_8723B_2ANT_BT_STATUS_ACL_BUSY;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n");
- BTC_TRACE(trace_buf);
- } else {
- coex_dm->bt_status = BT_8723B_2ANT_BT_STATUS_MAX;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n");
- BTC_TRACE(trace_buf);
- }
-
- if ((BT_8723B_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
- (BT_8723B_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
- (BT_8723B_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) {
- bt_busy = true;
- limited_dig = true;
- } else {
- bt_busy = false;
- limited_dig = false;
- }
-
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
-
- coex_dm->limited_dig = limited_dig;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_LIMITED_DIG, &limited_dig);
-
- halbtc8723b2ant_run_coexist_mechanism(btcoexist);
-}
-
-void ex_halbtc8723b2ant_halt_notify(IN struct btc_coexist *btcoexist)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n");
- BTC_TRACE(trace_buf);
-
- halbtc8723b2ant_wifi_off_hw_cfg(btcoexist);
- /* remove due to interrupt is disabled that polling c2h will fail and delay 100ms. */
- /* btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x3c, 0x15); //BT goto standby while GNT_BT 1-->0 */
- halbtc8723b2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
-
- ex_halbtc8723b2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
-}
-
-void ex_halbtc8723b2ant_pnp_notify(IN struct btc_coexist *btcoexist,
- IN u8 pnp_state)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n");
- BTC_TRACE(trace_buf);
-
- if (BTC_WIFI_PNP_SLEEP == pnp_state) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Pnp notify to SLEEP\n");
- BTC_TRACE(trace_buf);
-
- /* Sinda 20150819, workaround for driver skip leave IPS/LPS to speed up sleep time. */
- /* Driver do not leave IPS/LPS when driver is going to sleep, so BTCoexistence think wifi is still under IPS/LPS */
- /* BT should clear UnderIPS/UnderLPS state to avoid mismatch state after wakeup. */
- coex_sta->under_ips = false;
- coex_sta->under_lps = false;
- } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Pnp notify to WAKE UP\n");
- BTC_TRACE(trace_buf);
- halbtc8723b2ant_init_hw_config(btcoexist, false);
- halbtc8723b2ant_init_coex_dm(btcoexist);
- halbtc8723b2ant_query_bt_info(btcoexist);
- }
-}
-
-void ex_halbtc8723b2ant_periodical(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ==========================Periodical===========================\n");
- BTC_TRACE(trace_buf);
- if (coex_sta->dis_ver_info_cnt <= 5) {
- coex_sta->dis_ver_info_cnt += 1;
- if (coex_sta->dis_ver_info_cnt == 3) {
- /* Antenna config to set 0x765 = 0x0 (GNT_BT control by PTA) after initial */
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Set GNT_BT control by PTA\n");
- BTC_TRACE(trace_buf);
- halbtc8723b2ant_set_ant_path(btcoexist,
- BTC_ANT_WIFI_AT_MAIN, false, false);
- }
- }
-
-#if (BT_AUTO_REPORT_ONLY_8723B_2ANT == 0)
- halbtc8723b2ant_query_bt_info(btcoexist);
- halbtc8723b2ant_monitor_bt_enable_disable(btcoexist);
-#else
- halbtc8723b2ant_monitor_bt_ctr(btcoexist);
- halbtc8723b2ant_monitor_wifi_ctr(btcoexist);
-
- /* for some BT speaker that Hi-Pri pkt appear begore start play, this will cause HID exist */
- if ((coex_sta->high_priority_tx + coex_sta->high_priority_rx < 50) &&
- (bt_link_info->hid_exist == true))
- bt_link_info->hid_exist = false;
-
- if (halbtc8723b2ant_is_wifi_status_changed(btcoexist) ||
- coex_dm->auto_tdma_adjust)
- halbtc8723b2ant_run_coexist_mechanism(btcoexist);
-#endif
-}
-
-#endif
-
-#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */
-
diff --git a/hal/btc/HalBtc8723b2Ant.h b/hal/btc/HalBtc8723b2Ant.h
deleted file mode 100644
index 4fe39b2..0000000
--- a/hal/btc/HalBtc8723b2Ant.h
+++ /dev/null
@@ -1,214 +0,0 @@
-
-#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
-
-#if (RTL8723B_SUPPORT == 1)
-/* *******************************************
- * The following is for 8723B 2Ant BT Co-exist definition
- * ******************************************* */
-#define BT_AUTO_REPORT_ONLY_8723B_2ANT 1
-
-
-#define BT_INFO_8723B_2ANT_B_FTP BIT(7)
-#define BT_INFO_8723B_2ANT_B_A2DP BIT(6)
-#define BT_INFO_8723B_2ANT_B_HID BIT(5)
-#define BT_INFO_8723B_2ANT_B_SCO_BUSY BIT(4)
-#define BT_INFO_8723B_2ANT_B_ACL_BUSY BIT(3)
-#define BT_INFO_8723B_2ANT_B_INQ_PAGE BIT(2)
-#define BT_INFO_8723B_2ANT_B_SCO_ESCO BIT(1)
-#define BT_INFO_8723B_2ANT_B_CONNECTION BIT(0)
-
-#define BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT 2
-
-
-#define BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES 42 /* WiFi RSSI Threshold for 2-Ant TDMA/1-Ant PS-TDMA translation */
-#define BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES 46 /* BT RSSI Threshold for 2-Ant TDMA/1-Ant PS-TDMA translation */
-
-enum bt_info_src_8723b_2ant {
- BT_INFO_SRC_8723B_2ANT_WIFI_FW = 0x0,
- BT_INFO_SRC_8723B_2ANT_BT_RSP = 0x1,
- BT_INFO_SRC_8723B_2ANT_BT_ACTIVE_SEND = 0x2,
- BT_INFO_SRC_8723B_2ANT_MAX
-};
-
-enum bt_8723b_2ant_bt_status {
- BT_8723B_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
- BT_8723B_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
- BT_8723B_2ANT_BT_STATUS_INQ_PAGE = 0x2,
- BT_8723B_2ANT_BT_STATUS_ACL_BUSY = 0x3,
- BT_8723B_2ANT_BT_STATUS_SCO_BUSY = 0x4,
- BT_8723B_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
- BT_8723B_2ANT_BT_STATUS_MAX
-};
-
-enum bt_8723b_2ant_coex_algo {
- BT_8723B_2ANT_COEX_ALGO_UNDEFINED = 0x0,
- BT_8723B_2ANT_COEX_ALGO_SCO = 0x1,
- BT_8723B_2ANT_COEX_ALGO_HID = 0x2,
- BT_8723B_2ANT_COEX_ALGO_A2DP = 0x3,
- BT_8723B_2ANT_COEX_ALGO_A2DP_PANHS = 0x4,
- BT_8723B_2ANT_COEX_ALGO_PANEDR = 0x5,
- BT_8723B_2ANT_COEX_ALGO_PANHS = 0x6,
- BT_8723B_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
- BT_8723B_2ANT_COEX_ALGO_PANEDR_HID = 0x8,
- BT_8723B_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
- BT_8723B_2ANT_COEX_ALGO_HID_A2DP = 0xa,
- BT_8723B_2ANT_COEX_ALGO_MAX = 0xb,
-};
-
-struct coex_dm_8723b_2ant {
- /* fw mechanism */
- u8 pre_bt_dec_pwr_lvl;
- u8 cur_bt_dec_pwr_lvl;
- u8 pre_fw_dac_swing_lvl;
- u8 cur_fw_dac_swing_lvl;
- boolean cur_ignore_wlan_act;
- boolean pre_ignore_wlan_act;
- u8 pre_ps_tdma;
- u8 cur_ps_tdma;
- u8 ps_tdma_para[5];
- u8 ps_tdma_du_adj_type;
- boolean reset_tdma_adjust;
- boolean auto_tdma_adjust;
- boolean pre_ps_tdma_on;
- boolean cur_ps_tdma_on;
- boolean pre_bt_auto_report;
- boolean cur_bt_auto_report;
-
- /* sw mechanism */
- boolean pre_rf_rx_lpf_shrink;
- boolean cur_rf_rx_lpf_shrink;
- u32 bt_rf_0x1e_backup;
- boolean pre_low_penalty_ra;
- boolean cur_low_penalty_ra;
- boolean pre_dac_swing_on;
- u32 pre_dac_swing_lvl;
- boolean cur_dac_swing_on;
- u32 cur_dac_swing_lvl;
- boolean pre_adc_back_off;
- boolean cur_adc_back_off;
- boolean pre_agc_table_en;
- boolean cur_agc_table_en;
- u32 pre_val0x6c0;
- u32 cur_val0x6c0;
- u32 pre_val0x6c4;
- u32 cur_val0x6c4;
- u32 pre_val0x6c8;
- u32 cur_val0x6c8;
- u8 pre_val0x6cc;
- u8 cur_val0x6cc;
- boolean limited_dig;
-
- /* algorithm related */
- u8 pre_algorithm;
- u8 cur_algorithm;
- u8 bt_status;
- u8 wifi_chnl_info[3];
-
- boolean need_recover0x948;
- u32 backup0x948;
-
- u8 pre_lps;
- u8 cur_lps;
- u8 pre_rpwm;
- u8 cur_rpwm;
-
- boolean is_switch_to_1dot5_ant;
- u8 switch_thres_offset;
-};
-
-struct coex_sta_8723b_2ant {
- boolean bt_disabled;
- boolean bt_link_exist;
- boolean sco_exist;
- boolean a2dp_exist;
- boolean hid_exist;
- boolean pan_exist;
- boolean bt_abnormal_scan;
- boolean under_lps;
- boolean under_ips;
- u32 high_priority_tx;
- u32 high_priority_rx;
- u32 low_priority_tx;
- u32 low_priority_rx;
- u8 bt_rssi;
- boolean bt_tx_rx_mask;
- u8 pre_bt_rssi_state;
- u8 pre_wifi_rssi_state[4];
- boolean c2h_bt_info_req_sent;
- u8 bt_info_c2h[BT_INFO_SRC_8723B_2ANT_MAX][10];
- u32 bt_info_c2h_cnt[BT_INFO_SRC_8723B_2ANT_MAX];
- boolean bt_whck_test;
- boolean c2h_bt_inquiry_page;
- boolean c2h_bt_remote_name_req;
- u8 bt_retry_cnt;
- u8 bt_info_ext;
- u32 pop_event_cnt;
- u8 scan_ap_num;
-
- u32 crc_ok_cck;
- u32 crc_ok_11g;
- u32 crc_ok_11n;
- u32 crc_ok_11n_agg;
-
- u32 crc_err_cck;
- u32 crc_err_11g;
- u32 crc_err_11n;
- u32 crc_err_11n_agg;
-
- u8 coex_table_type;
- boolean force_lps_on;
-
- u8 dis_ver_info_cnt;
-
- u8 a2dp_bit_pool;
- u8 cut_version;
-};
-
-/* *******************************************
- * The following is interface which will notify coex module.
- * ******************************************* */
-void ex_halbtc8723b2ant_power_on_setting(IN struct btc_coexist *btcoexist);
-void ex_halbtc8723b2ant_pre_load_firmware(IN struct btc_coexist *btcoexist);
-void ex_halbtc8723b2ant_init_hw_config(IN struct btc_coexist *btcoexist,
- IN boolean wifi_only);
-void ex_halbtc8723b2ant_init_coex_dm(IN struct btc_coexist *btcoexist);
-void ex_halbtc8723b2ant_ips_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8723b2ant_lps_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8723b2ant_scan_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8723b2ant_connect_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8723b2ant_media_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8723b2ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8723b2ant_bt_info_notify(IN struct btc_coexist *btcoexist,
- IN u8 *tmp_buf, IN u8 length);
-void ex_halbtc8723b2ant_halt_notify(IN struct btc_coexist *btcoexist);
-void ex_halbtc8723b2ant_pnp_notify(IN struct btc_coexist *btcoexist,
- IN u8 pnp_state);
-void ex_halbtc8723b2ant_periodical(IN struct btc_coexist *btcoexist);
-void ex_halbtc8723b2ant_display_coex_info(IN struct btc_coexist *btcoexist);
-
-#else
-#define ex_halbtc8723b2ant_power_on_setting(btcoexist)
-#define ex_halbtc8723b2ant_pre_load_firmware(btcoexist)
-#define ex_halbtc8723b2ant_init_hw_config(btcoexist, wifi_only)
-#define ex_halbtc8723b2ant_init_coex_dm(btcoexist)
-#define ex_halbtc8723b2ant_ips_notify(btcoexist, type)
-#define ex_halbtc8723b2ant_lps_notify(btcoexist, type)
-#define ex_halbtc8723b2ant_scan_notify(btcoexist, type)
-#define ex_halbtc8723b2ant_connect_notify(btcoexist, type)
-#define ex_halbtc8723b2ant_media_status_notify(btcoexist, type)
-#define ex_halbtc8723b2ant_specific_packet_notify(btcoexist, type)
-#define ex_halbtc8723b2ant_bt_info_notify(btcoexist, tmp_buf, length)
-#define ex_halbtc8723b2ant_halt_notify(btcoexist)
-#define ex_halbtc8723b2ant_pnp_notify(btcoexist, pnp_state)
-#define ex_halbtc8723b2ant_periodical(btcoexist)
-#define ex_halbtc8723b2ant_display_coex_info(btcoexist)
-
-#endif
-
-#endif
diff --git a/hal/btc/HalBtc8812a1Ant.c b/hal/btc/HalBtc8812a1Ant.c
deleted file mode 100644
index e094caa..0000000
--- a/hal/btc/HalBtc8812a1Ant.c
+++ /dev/null
@@ -1,3457 +0,0 @@
-/* ************************************************************
- * Description:
- *
- * This file is for RTL8812A Co-exist mechanism
- *
- * History
- * 2012/11/15 Cosa first check in.
- *
- * ************************************************************ */
-
-/* ************************************************************
- * include files
- * ************************************************************ */
-#include "Mp_Precomp.h"
-
-#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
-
-#if (RTL8812A_SUPPORT == 1)
-/* ************************************************************
- * Global variables, these are static variables
- * ************************************************************ */
-static u8 *trace_buf = &gl_btc_trace_buf[0];
-static struct coex_dm_8812a_1ant glcoex_dm_8812a_1ant;
-static struct coex_dm_8812a_1ant *coex_dm = &glcoex_dm_8812a_1ant;
-static struct coex_sta_8812a_1ant glcoex_sta_8812a_1ant;
-static struct coex_sta_8812a_1ant *coex_sta = &glcoex_sta_8812a_1ant;
-
-const char *const glbt_info_src_8812a_1ant[] = {
- "BT Info[wifi fw]",
- "BT Info[bt rsp]",
- "BT Info[bt auto report]",
-};
-
-u32 glcoex_ver_date_8812a_1ant = 20140708;
-u32 glcoex_ver_8812a_1ant = 0x52;
-
-/* ************************************************************
- * local function proto type if needed
- * ************************************************************
- * ************************************************************
- * local function start with halbtc8812a1ant_
- * ************************************************************ */
-u8 halbtc8812a1ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1)
-{
- s32 bt_rssi = 0;
- u8 bt_rssi_state = coex_sta->pre_bt_rssi_state;
-
- bt_rssi = coex_sta->bt_rssi;
-
- if (level_num == 2) {
- if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
- (coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (bt_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT))
- bt_rssi_state = BTC_RSSI_STATE_HIGH;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else {
- if (bt_rssi < rssi_thresh)
- bt_rssi_state = BTC_RSSI_STATE_LOW;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- } else if (level_num == 3) {
- if (rssi_thresh > rssi_thresh1) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Rssi thresh error!!\n");
- BTC_TRACE(trace_buf);
- return coex_sta->pre_bt_rssi_state;
- }
-
- if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
- (coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (bt_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT))
- bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else if ((coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_MEDIUM) ||
- (coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_STAY_MEDIUM)) {
- if (bt_rssi >= (rssi_thresh1 +
- BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT))
- bt_rssi_state = BTC_RSSI_STATE_HIGH;
- else if (bt_rssi < rssi_thresh)
- bt_rssi_state = BTC_RSSI_STATE_LOW;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
- } else {
- if (bt_rssi < rssi_thresh1)
- bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- }
-
- coex_sta->pre_bt_rssi_state = bt_rssi_state;
-
- return bt_rssi_state;
-}
-
-u8 halbtc8812a1ant_wifi_rssi_state(IN struct btc_coexist *btcoexist,
- IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1)
-{
- s32 wifi_rssi = 0;
- u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index];
-
- btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
-
- if (level_num == 2) {
- if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
- ||
- (coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (wifi_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT))
- wifi_rssi_state = BTC_RSSI_STATE_HIGH;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else {
- if (wifi_rssi < rssi_thresh)
- wifi_rssi_state = BTC_RSSI_STATE_LOW;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- } else if (level_num == 3) {
- if (rssi_thresh > rssi_thresh1) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], wifi RSSI thresh error!!\n");
- BTC_TRACE(trace_buf);
- return coex_sta->pre_wifi_rssi_state[index];
- }
-
- if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
- ||
- (coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (wifi_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT))
- wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else if ((coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_MEDIUM) ||
- (coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_STAY_MEDIUM)) {
- if (wifi_rssi >= (rssi_thresh1 +
- BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT))
- wifi_rssi_state = BTC_RSSI_STATE_HIGH;
- else if (wifi_rssi < rssi_thresh)
- wifi_rssi_state = BTC_RSSI_STATE_LOW;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
- } else {
- if (wifi_rssi < rssi_thresh1)
- wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- }
-
- coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state;
-
- return wifi_rssi_state;
-}
-
-void halbtc8812a1ant_update_ra_mask(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u32 dis_rate_mask)
-{
- coex_dm->cur_ra_mask = dis_rate_mask;
-
- if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask))
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK,
- &coex_dm->cur_ra_mask);
- coex_dm->pre_ra_mask = coex_dm->cur_ra_mask;
-}
-
-/* to check 0x430/0x434 is correct?? */
-void halbtc8812a1ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- boolean wifi_under_b_mode = false;
-
- coex_dm->cur_arfr_type = type;
-
- if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) {
- switch (coex_dm->cur_arfr_type) {
- case 0: /* normal mode */
- btcoexist->btc_write_4byte(btcoexist, 0x430,
- coex_dm->backup_arfr_cnt1);
- btcoexist->btc_write_4byte(btcoexist, 0x434,
- coex_dm->backup_arfr_cnt2);
- break;
- case 1:
- btcoexist->btc_get(btcoexist,
- BTC_GET_BL_WIFI_UNDER_B_MODE,
- &wifi_under_b_mode);
- if (wifi_under_b_mode) {
- btcoexist->btc_write_4byte(btcoexist,
- 0x430, 0x0);
- btcoexist->btc_write_4byte(btcoexist,
- 0x434, 0x01010101);
- } else {
- btcoexist->btc_write_4byte(btcoexist,
- 0x430, 0x0);
- btcoexist->btc_write_4byte(btcoexist,
- 0x434, 0x04030201);
- }
- break;
- default:
- break;
- }
- }
-
- coex_dm->pre_arfr_type = coex_dm->cur_arfr_type;
-}
-
-/* to check 0x42a ?? */
-void halbtc8812a1ant_retry_limit(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- coex_dm->cur_retry_limit_type = type;
-
- if (force_exec ||
- (coex_dm->pre_retry_limit_type !=
- coex_dm->cur_retry_limit_type)) {
- switch (coex_dm->cur_retry_limit_type) {
- case 0: /* normal mode */
- btcoexist->btc_write_2byte(btcoexist, 0x42a,
- coex_dm->backup_retry_limit);
- break;
- case 1: /* retry limit=8 */
- btcoexist->btc_write_2byte(btcoexist, 0x42a,
- 0x0808);
- break;
- default:
- break;
- }
- }
-
- coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type;
-}
-
-/* to check 0x456?? */
-void halbtc8812a1ant_ampdu_max_time(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- coex_dm->cur_ampdu_time_type = type;
-
- if (force_exec ||
- (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) {
- switch (coex_dm->cur_ampdu_time_type) {
- case 0: /* normal mode */
- btcoexist->btc_write_1byte(btcoexist, 0x456,
- coex_dm->backup_ampdu_max_time);
- break;
- case 1: /* AMPDU timw = 0x38 * 32us */
- btcoexist->btc_write_1byte(btcoexist, 0x456,
- 0x38);
- break;
- default:
- break;
- }
- }
-
- coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type;
-}
-
-void halbtc8812a1ant_limited_tx(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type,
- IN u8 retry_limit_type, IN u8 ampdu_time_type)
-{
- switch (ra_mask_type) {
- case 0: /* normal mode */
- halbtc8812a1ant_update_ra_mask(btcoexist, force_exec,
- 0x0);
- break;
- case 1: /* disable cck 1/2 */
- halbtc8812a1ant_update_ra_mask(btcoexist, force_exec,
- 0x00000003);
- break;
- case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */
- halbtc8812a1ant_update_ra_mask(btcoexist, force_exec,
- 0x0001f1f7);
- break;
- default:
- break;
- }
-
- halbtc8812a1ant_auto_rate_fallback_retry(btcoexist, force_exec,
- arfr_type);
- halbtc8812a1ant_retry_limit(btcoexist, force_exec, retry_limit_type);
- halbtc8812a1ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type);
-}
-
-void halbtc8812a1ant_limited_rx(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean rej_ap_agg_pkt,
- IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size)
-{
- boolean reject_rx_agg = rej_ap_agg_pkt;
- boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size;
- u8 rx_agg_size = agg_buf_size;
-
- /* ============================================ */
- /* Rx Aggregation related setting */
- /* ============================================ */
- btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT,
- &reject_rx_agg);
- /* decide BT control aggregation buf size or not */
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE,
- &bt_ctrl_rx_agg_size);
- /* aggregation buf size, only work when BT control Rx aggregation size. */
- btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size);
- /* real update aggregation setting */
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
-
-
-}
-
-void halbtc8812a1ant_query_bt_info(IN struct btc_coexist *btcoexist)
-{
- u8 data_len = 3;
- u8 buf[5] = {0};
-
- if (!coex_sta->bt_disabled) {
- if (!coex_sta->bt_info_query_cnt ||
- (coex_sta->bt_info_c2h_cnt[BT_INFO_SRC_8812A_1ANT_BT_RSP]
- - coex_sta->bt_info_query_cnt) > 2) {
- buf[0] = data_len;
- buf[1] = 0x1; /* polling enable, 1=enable, 0=disable */
- buf[2] = 0x2; /* polling time in seconds */
- buf[3] = 0x1; /* auto report enable, 1=enable, 0=disable */
-
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_INFO,
- (void *)&buf[0]);
- }
- }
- coex_sta->bt_info_query_cnt++;
-}
-
-void halbtc8812a1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist)
-{
- u32 reg_hp_txrx, reg_lp_txrx, u32tmp;
- u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
- static u8 num_of_bt_counter_chk = 0;
-
- reg_hp_txrx = 0x770;
- reg_lp_txrx = 0x774;
-
- u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
- reg_hp_tx = u32tmp & MASKLWORD;
- reg_hp_rx = (u32tmp & MASKHWORD) >> 16;
-
- u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
- reg_lp_tx = u32tmp & MASKLWORD;
- reg_lp_rx = (u32tmp & MASKHWORD) >> 16;
-
- coex_sta->high_priority_tx = reg_hp_tx;
- coex_sta->high_priority_rx = reg_hp_rx;
- coex_sta->low_priority_tx = reg_lp_tx;
- coex_sta->low_priority_rx = reg_lp_rx;
-
- if ((coex_sta->low_priority_tx > 1150) &&
- (!coex_sta->c2h_bt_inquiry_page))
- coex_sta->pop_event_cnt++;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n",
- reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx);
- BTC_TRACE(trace_buf);
-
- /* reset counter */
- btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
-
- if ((reg_hp_tx == 0) && (reg_hp_rx == 0) && (reg_lp_tx == 0) &&
- (reg_lp_rx == 0)) {
- num_of_bt_counter_chk++;
- if (num_of_bt_counter_chk >= 3) {
- halbtc8812a1ant_query_bt_info(btcoexist);
- num_of_bt_counter_chk = 0;
- }
- }
-}
-
-/* to check registers */
-void halbtc8812a1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist)
-{
- s32 wifi_rssi = 0;
- boolean wifi_busy = false, wifi_under_b_mode = false;
- static u8 cck_lock_counter = 0;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
- &wifi_under_b_mode);
-
- if (coex_sta->under_ips) {
- coex_sta->crc_ok_cck = 0;
- coex_sta->crc_ok_11g = 0;
- coex_sta->crc_ok_11n = 0;
- coex_sta->crc_ok_11n_agg = 0;
-
- coex_sta->crc_err_cck = 0;
- coex_sta->crc_err_11g = 0;
- coex_sta->crc_err_11n = 0;
- coex_sta->crc_err_11n_agg = 0;
- } else {
- coex_sta->crc_ok_cck = btcoexist->btc_read_2byte(btcoexist,
- 0xf04);
- coex_sta->crc_ok_11g = btcoexist->btc_read_2byte(btcoexist,
- 0xf14);
- coex_sta->crc_ok_11n = btcoexist->btc_read_2byte(btcoexist,
- 0xf10);
- coex_sta->crc_ok_11n_agg = btcoexist->btc_read_2byte(btcoexist,
- 0xf40);
-
- coex_sta->crc_err_cck = btcoexist->btc_read_2byte(btcoexist,
- 0xf06);
- coex_sta->crc_err_11g = btcoexist->btc_read_2byte(btcoexist,
- 0xf16);
- coex_sta->crc_err_11n = btcoexist->btc_read_2byte(btcoexist,
- 0xf12);
- coex_sta->crc_err_11n_agg = btcoexist->btc_read_2byte(btcoexist,
- 0xf42);
- }
-
-
- /* reset counter */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xb58, 0x1, 0x1);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xb58, 0x1, 0x0);
-
- if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) {
- if ((coex_dm->bt_status == BT_8812A_1ANT_BT_STATUS_ACL_BUSY) ||
- (coex_dm->bt_status ==
- BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY) ||
- (coex_dm->bt_status ==
- BT_8812A_1ANT_BT_STATUS_SCO_BUSY)) {
- if (coex_sta->crc_ok_cck > (coex_sta->crc_ok_11g +
- coex_sta->crc_ok_11n +
- coex_sta->crc_ok_11n_agg)) {
- if (cck_lock_counter < 5)
- cck_lock_counter++;
- } else {
- if (cck_lock_counter > 0)
- cck_lock_counter--;
- }
-
- } else {
- if (cck_lock_counter > 0)
- cck_lock_counter--;
- }
- } else {
- if (cck_lock_counter > 0)
- cck_lock_counter--;
- }
-
- if (!coex_sta->pre_ccklock) {
-
- if (cck_lock_counter >= 5)
- coex_sta->cck_lock = true;
- else
- coex_sta->cck_lock = false;
- } else {
- if (cck_lock_counter == 0)
- coex_sta->cck_lock = false;
- else
- coex_sta->cck_lock = true;
- }
-
- coex_sta->pre_ccklock = coex_sta->cck_lock;
-
-
-}
-
-boolean halbtc8812a1ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist)
-{
- static boolean pre_wifi_busy = false, pre_under_4way = false,
- pre_bt_hs_on = false;
- boolean wifi_busy = false, under_4way = false, bt_hs_on = false;
- boolean wifi_connected = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
- &under_4way);
-
- if (wifi_connected) {
- if (wifi_busy != pre_wifi_busy) {
- pre_wifi_busy = wifi_busy;
- return true;
- }
- if (under_4way != pre_under_4way) {
- pre_under_4way = under_4way;
- return true;
- }
- if (bt_hs_on != pre_bt_hs_on) {
- pre_bt_hs_on = bt_hs_on;
- return true;
- }
- }
-
- return false;
-}
-
-void halbtc8812a1ant_update_bt_link_info(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean bt_hs_on = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
-
- bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
- bt_link_info->sco_exist = coex_sta->sco_exist;
- bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
- bt_link_info->pan_exist = coex_sta->pan_exist;
- bt_link_info->hid_exist = coex_sta->hid_exist;
-
- /* work around for HS mode. */
- if (bt_hs_on) {
- bt_link_info->pan_exist = true;
- bt_link_info->bt_link_exist = true;
- }
-
- /* check if Sco only */
- if (bt_link_info->sco_exist &&
- !bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist &&
- !bt_link_info->hid_exist)
- bt_link_info->sco_only = true;
- else
- bt_link_info->sco_only = false;
-
- /* check if A2dp only */
- if (!bt_link_info->sco_exist &&
- bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist &&
- !bt_link_info->hid_exist)
- bt_link_info->a2dp_only = true;
- else
- bt_link_info->a2dp_only = false;
-
- /* check if Pan only */
- if (!bt_link_info->sco_exist &&
- !bt_link_info->a2dp_exist &&
- bt_link_info->pan_exist &&
- !bt_link_info->hid_exist)
- bt_link_info->pan_only = true;
- else
- bt_link_info->pan_only = false;
-
- /* check if Hid only */
- if (!bt_link_info->sco_exist &&
- !bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist &&
- bt_link_info->hid_exist)
- bt_link_info->hid_only = true;
- else
- bt_link_info->hid_only = false;
-}
-
-u8 halbtc8812a1ant_action_algorithm(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean bt_hs_on = false;
- u8 algorithm = BT_8812A_1ANT_COEX_ALGO_UNDEFINED;
- u8 num_of_diff_profile = 0;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
-
- if (!bt_link_info->bt_link_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], No BT link exists!!!\n");
- BTC_TRACE(trace_buf);
- return algorithm;
- }
-
- if (bt_link_info->sco_exist)
- num_of_diff_profile++;
- if (bt_link_info->hid_exist)
- num_of_diff_profile++;
- if (bt_link_info->pan_exist)
- num_of_diff_profile++;
- if (bt_link_info->a2dp_exist)
- num_of_diff_profile++;
-
- if (num_of_diff_profile == 1) {
- if (bt_link_info->sco_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO only\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8812A_1ANT_COEX_ALGO_SCO;
- } else {
- if (bt_link_info->hid_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = HID only\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8812A_1ANT_COEX_ALGO_HID;
- } else if (bt_link_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = A2DP only\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8812A_1ANT_COEX_ALGO_A2DP;
- } else if (bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = PAN(HS) only\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8812A_1ANT_COEX_ALGO_PANHS;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = PAN(EDR) only\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8812A_1ANT_COEX_ALGO_PANEDR;
- }
- }
- }
- } else if (num_of_diff_profile == 2) {
- if (bt_link_info->sco_exist) {
- if (bt_link_info->hid_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + HID\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8812A_1ANT_COEX_ALGO_HID;
- } else if (bt_link_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + A2DP ==> SCO\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8812A_1ANT_COEX_ALGO_SCO;
- } else if (bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8812A_1ANT_COEX_ALGO_SCO;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8812A_1ANT_COEX_ALGO_PANEDR_HID;
- }
- }
- } else {
- if (bt_link_info->hid_exist &&
- bt_link_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = HID + A2DP\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8812A_1ANT_COEX_ALGO_HID_A2DP;
- } else if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = HID + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8812A_1ANT_COEX_ALGO_HID_A2DP;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = HID + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8812A_1ANT_COEX_ALGO_PANEDR_HID;
- }
- } else if (bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8812A_1ANT_COEX_ALGO_A2DP_PANHS;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = A2DP + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8812A_1ANT_COEX_ALGO_PANEDR_A2DP;
- }
- }
- }
- } else if (num_of_diff_profile == 3) {
- if (bt_link_info->sco_exist) {
- if (bt_link_info->hid_exist &&
- bt_link_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8812A_1ANT_COEX_ALGO_HID;
- } else if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + HID + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8812A_1ANT_COEX_ALGO_HID_A2DP;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8812A_1ANT_COEX_ALGO_PANEDR_HID;
- }
- } else if (bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8812A_1ANT_COEX_ALGO_SCO;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8812A_1ANT_COEX_ALGO_PANEDR_HID;
- }
- }
- } else {
- if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8812A_1ANT_COEX_ALGO_HID_A2DP;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8812A_1ANT_COEX_ALGO_HID_A2DP_PANEDR;
- }
- }
- }
- } else if (num_of_diff_profile >= 3) {
- if (bt_link_info->sco_exist) {
- if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
-
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8812A_1ANT_COEX_ALGO_PANEDR_HID;
- }
- }
- }
- }
-
- return algorithm;
-}
-
-void halbtc8812a1ant_set_bt_auto_report(IN struct btc_coexist *btcoexist,
- IN boolean enable_auto_report)
-{
- u8 h2c_parameter[1] = {0};
-
- h2c_parameter[0] = 0;
-
- if (enable_auto_report)
- h2c_parameter[0] |= BIT(0);
-
- btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter);
-}
-
-void halbtc8812a1ant_bt_auto_report(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean enable_auto_report)
-{
- coex_dm->cur_bt_auto_report = enable_auto_report;
-
- if (!force_exec) {
- if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report)
- return;
- }
- halbtc8812a1ant_set_bt_auto_report(btcoexist,
- coex_dm->cur_bt_auto_report);
-
- coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report;
-}
-
-/* to check */
-void halbtc8812a1ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist
- *btcoexist, IN boolean low_penalty_ra)
-{
- u8 tmp_u1;
-
- tmp_u1 = btcoexist->btc_read_1byte(btcoexist, 0x4fd);
- tmp_u1 |= BIT(0);
- if (low_penalty_ra) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Tx rate adaptive, set low penalty!!\n");
- BTC_TRACE(trace_buf);
- tmp_u1 &= ~BIT(2);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Tx rate adaptive, set normal!!\n");
- BTC_TRACE(trace_buf);
- tmp_u1 |= BIT(2);
- }
-
- btcoexist->btc_write_1byte(btcoexist, 0x4fd, tmp_u1);
-}
-
-void halbtc8812a1ant_low_penalty_ra(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean low_penalty_ra)
-{
- coex_dm->cur_low_penalty_ra = low_penalty_ra;
-
- if (!force_exec) {
- if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra)
- return;
- }
- halbtc8812a1ant_set_sw_penalty_tx_rate_adaptive(btcoexist,
- coex_dm->cur_low_penalty_ra);
-
- coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra;
-}
-
-void halbtc8812a1ant_set_coex_table(IN struct btc_coexist *btcoexist,
- IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc)
-{
- btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
-
- btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
-
- btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
-
- btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
-}
-
-void halbtc8812a1ant_coex_table(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4,
- IN u32 val0x6c8, IN u8 val0x6cc)
-{
- coex_dm->cur_val0x6c0 = val0x6c0;
- coex_dm->cur_val0x6c4 = val0x6c4;
- coex_dm->cur_val0x6c8 = val0x6c8;
- coex_dm->cur_val0x6cc = val0x6cc;
-
- if (!force_exec) {
- if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) &&
- (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) &&
- (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) &&
- (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc))
- return;
- }
- halbtc8812a1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8,
- val0x6cc);
-
- coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0;
- coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4;
- coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8;
- coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc;
-}
-
-void halbtc8812a1ant_coex_table_with_type(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** CoexTable(%d) **********\n", type);
- BTC_TRACE(trace_buf);
-
- coex_sta->coex_table_type = type;
-
- switch (type) {
- case 0:
- halbtc8812a1ant_coex_table(btcoexist, force_exec,
- 0x55555555, 0x55555555, 0xffffff, 0x3);
- break;
- case 1:
- halbtc8812a1ant_coex_table(btcoexist, force_exec,
- 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3);
- break;
- case 2:
- halbtc8812a1ant_coex_table(btcoexist, force_exec,
- 0x5a5a5a5a, 0x5a5a5a5a, 0xffffff, 0x3);
- break;
- case 3:
- halbtc8812a1ant_coex_table(btcoexist, force_exec,
- 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3);
- break;
- case 4:
- halbtc8812a1ant_coex_table(btcoexist, force_exec,
- 0x55555555, 0xaaaa5a5a, 0xffffff, 0x3);
- break;
- case 5:
- halbtc8812a1ant_coex_table(btcoexist, force_exec,
- 0x5a5a5a5a, 0xaa5a5a5a, 0xffffff, 0x3);
- break;
- case 6:
- halbtc8812a1ant_coex_table(btcoexist, force_exec,
- 0x55555555, 0xaaaaaaaa, 0xffffff, 0x3);
- break;
- case 7:
- halbtc8812a1ant_coex_table(btcoexist, force_exec,
- 0xaaaaaaaa, 0xaaaaaaaa, 0xffffff, 0x3);
- break;
- default:
- break;
- }
-}
-
-void halbtc8812a1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist,
- IN boolean enable)
-{
- u8 data_len = 3;
- u8 buf[5] = {0};
-
- buf[0] = data_len;
- buf[1] = 0x1; /* OP_Code */
- buf[2] = 0x1; /* OP_Code_Length */
- if (enable)
- buf[3] = 0x1; /* OP_Code_Content */
- else
- buf[3] = 0x0;
-
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_COEX,
- (void *)&buf[0]);
-}
-
-void halbtc8812a1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean enable)
-{
- coex_dm->cur_ignore_wlan_act = enable;
-
- if (!force_exec) {
- if (coex_dm->pre_ignore_wlan_act ==
- coex_dm->cur_ignore_wlan_act)
- return;
- }
- halbtc8812a1ant_set_fw_ignore_wlan_act(btcoexist, enable);
-
- coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
-}
-
-void halbtc8812a1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist,
- IN u8 lps_val, IN u8 rpwm_val)
-{
- u8 lps = lps_val;
- u8 rpwm = rpwm_val;
-
- btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps);
- btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm);
-}
-
-void halbtc8812a1ant_lps_rpwm(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val)
-{
- coex_dm->cur_lps = lps_val;
- coex_dm->cur_rpwm = rpwm_val;
-
- if (!force_exec) {
- if ((coex_dm->pre_lps == coex_dm->cur_lps) &&
- (coex_dm->pre_rpwm == coex_dm->cur_rpwm))
- return;
- }
- halbtc8812a1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val);
-
- coex_dm->pre_lps = coex_dm->cur_lps;
- coex_dm->pre_rpwm = coex_dm->cur_rpwm;
-}
-
-void halbtc8812a1ant_sw_mechanism(IN struct btc_coexist *btcoexist,
- IN boolean low_penalty_ra)
-{
- halbtc8812a1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra);
-}
-
-/* to check force_exec */
-void halbtc8812a1ant_set_ant_path(IN struct btc_coexist *btcoexist,
- IN u8 ant_pos_type, IN boolean force_exec, IN boolean init_hwcfg,
- IN boolean wifi_off)
-{
- u8 u8tmp = 0;
-
- coex_dm->cur_ant_pos_type = ant_pos_type;
-
- if (init_hwcfg) {
- btcoexist->btc_write_1byte(btcoexist, 0xcb3, 0x77);
- btcoexist->btc_write_4byte(btcoexist, 0x900, 0x00000400);
- btcoexist->btc_write_1byte(btcoexist, 0x76d, 0x1);
- } else if (wifi_off) {
- btcoexist->btc_write_1byte(btcoexist, 0xcb3, 0x77);
- u8tmp = btcoexist->btc_read_1byte(btcoexist, 0xcb7);
- u8tmp &= ~BIT(3);
- u8tmp |= BIT(2);
- btcoexist->btc_write_1byte(btcoexist, 0xcb7, u8tmp);
- }
-
- if (force_exec ||
- (coex_dm->cur_ant_pos_type != coex_dm->pre_ant_pos_type)) {
- /* ext switch setting */
- switch (ant_pos_type) {
- case BTC_ANT_PATH_WIFI:
- u8tmp = btcoexist->btc_read_1byte(btcoexist,
- 0xcb7);
- u8tmp |= BIT(3);
- u8tmp &= ~BIT(2);
- btcoexist->btc_write_1byte(btcoexist, 0xcb7,
- u8tmp);
- break;
- case BTC_ANT_PATH_BT:
- u8tmp = btcoexist->btc_read_1byte(btcoexist,
- 0xcb7);
- u8tmp &= ~BIT(3);
- u8tmp |= BIT(2);
- btcoexist->btc_write_1byte(btcoexist, 0xcb7,
- u8tmp);
- break;
- default:
- case BTC_ANT_PATH_PTA:
- u8tmp = btcoexist->btc_read_1byte(btcoexist,
- 0xcb7);
- u8tmp |= BIT(3);
- u8tmp &= ~BIT(2);
- btcoexist->btc_write_1byte(btcoexist, 0xcb7,
- u8tmp);
- break;
- }
- }
-
- coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type;
-}
-
-void halbtc8812a1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist,
- IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5)
-{
- u8 h2c_parameter[5] = {0};
- u8 real_byte1 = byte1, real_byte5 = byte5;
- boolean ap_enable = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
- &ap_enable);
-
- if (ap_enable) {
- if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], FW for 1Ant AP mode\n");
- BTC_TRACE(trace_buf);
- real_byte1 &= ~BIT(4);
- real_byte1 |= BIT(5);
-
- real_byte5 |= BIT(5);
- real_byte5 &= ~BIT(6);
- }
- }
-
- h2c_parameter[0] = real_byte1;
- h2c_parameter[1] = byte2;
- h2c_parameter[2] = byte3;
- h2c_parameter[3] = byte4;
- h2c_parameter[4] = real_byte5;
-
- coex_dm->ps_tdma_para[0] = real_byte1;
- coex_dm->ps_tdma_para[1] = byte2;
- coex_dm->ps_tdma_para[2] = byte3;
- coex_dm->ps_tdma_para[3] = byte4;
- coex_dm->ps_tdma_para[4] = real_byte5;
-
- btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
-}
-
-
-void halbtc8812a1ant_ps_tdma(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean turn_on, IN u8 type)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_busy = false;
- u8 rssi_adjust_val = 0;
- u8 ps_tdma_byte4_val = 0x50, ps_tdma_byte0_val = 0x51,
- ps_tdma_byte3_val = 0x10;
- s8 wifi_duration_adjust = 0x0;
- static boolean pre_wifi_busy = false;
-
- coex_dm->cur_ps_tdma_on = turn_on;
- coex_dm->cur_ps_tdma = type;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- if (wifi_busy != pre_wifi_busy) {
- force_exec = true;
- pre_wifi_busy = wifi_busy;
- }
-
- if (coex_dm->cur_ps_tdma_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** TDMA(on, %d) **********\n",
- coex_dm->cur_ps_tdma);
- BTC_TRACE(trace_buf);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** TDMA(off, %d) **********\n",
- coex_dm->cur_ps_tdma);
- BTC_TRACE(trace_buf);
- }
-
- if (!force_exec) {
- if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) &&
- (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma))
- return;
- }
-
- if (coex_sta->scan_ap_num <= 5)
- wifi_duration_adjust = 2;
- else if (coex_sta->scan_ap_num >= 40)
- wifi_duration_adjust = -15;
- else if (coex_sta->scan_ap_num >= 20)
- wifi_duration_adjust = -10;
-
- if (!coex_sta->force_lps_on) { /* only for A2DP-only case 1/2/9/11 while wifi noisy threshold > 30 */
- ps_tdma_byte0_val = 0x61; /* no null-pkt */
- ps_tdma_byte3_val = 0x11; /* no tx-pause at BT-slot */
- ps_tdma_byte4_val = 0x10; /* 0x778 = d/1 toggle */
- }
-
- if ((type == 3) || (type == 13) || (type == 14)) {
- ps_tdma_byte4_val = ps_tdma_byte4_val &
- 0xbf; /* no dynamic slot for multi-profile */
-
- if (!wifi_busy)
- ps_tdma_byte4_val = ps_tdma_byte4_val |
- 0x1; /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */
- }
-
- if (bt_link_info->slave_role == true)
- ps_tdma_byte4_val = ps_tdma_byte4_val |
- 0x1; /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */
-
- if (turn_on) {
- switch (type) {
- default:
- halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x51,
- 0x1a, 0x1a, 0x0, ps_tdma_byte4_val);
- break;
- case 1:
- halbtc8812a1ant_set_fw_pstdma(btcoexist,
- ps_tdma_byte0_val, 0x3a +
- wifi_duration_adjust, 0x03,
- ps_tdma_byte3_val, ps_tdma_byte4_val);
- break;
- case 2:
- halbtc8812a1ant_set_fw_pstdma(btcoexist,
- ps_tdma_byte0_val, 0x2d +
- wifi_duration_adjust, 0x03,
- ps_tdma_byte3_val, ps_tdma_byte4_val);
- break;
- case 3:
- halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x51,
- 0x1d, 0x1d, 0x0, ps_tdma_byte4_val);
- break;
- case 4:
- halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x93,
- 0x15, 0x3, 0x14, 0x0);
- break;
- case 5:
- halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x61,
- 0x15, 0x3, 0x11, 0x11);
- break;
- case 6:
- halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x61,
- 0x20, 0x3, 0x11, 0x11);
- break;
- case 7:
- halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x13,
- 0xc, 0x5, 0x0, 0x0);
- break;
- case 8:
- halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x93,
- 0x25, 0x3, 0x10, 0x0);
- break;
- case 9:
- halbtc8812a1ant_set_fw_pstdma(btcoexist,
- ps_tdma_byte0_val, 0x21, 0x3,
- ps_tdma_byte3_val, ps_tdma_byte4_val);
- break;
- case 10:
- halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x13,
- 0xa, 0xa, 0x0, 0x40);
- break;
- case 11:
- halbtc8812a1ant_set_fw_pstdma(btcoexist,
- ps_tdma_byte0_val, 0x21, 0x03,
- ps_tdma_byte3_val, ps_tdma_byte4_val);
- break;
- case 12:
- halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x51,
- 0x0a, 0x0a, 0x0, 0x50);
- break;
- case 13:
- halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x51,
- 0x12, 0x12, 0x0, ps_tdma_byte4_val);
- break;
- case 14:
- halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x51,
- 0x21, 0x3, 0x10, ps_tdma_byte4_val);
- break;
- case 15:
- halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x13,
- 0xa, 0x3, 0x8, 0x0);
- break;
- case 16:
- halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x93,
- 0x15, 0x3, 0x10, 0x0);
- break;
- case 18:
- halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x93,
- 0x25, 0x3, 0x10, 0x0);
- break;
- case 20:
- halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x61,
- 0x3f, 0x03, 0x11, 0x10);
- break;
- case 21:
- halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x61,
- 0x25, 0x03, 0x11, 0x11);
- break;
- case 22:
- halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x61,
- 0x25, 0x03, 0x11, 0x10);
- break;
- case 23:
- halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x25, 0x3, 0x31, 0x18);
- break;
- case 24:
- halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x15, 0x3, 0x31, 0x18);
- break;
- case 25:
- halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xe3,
- 0xa, 0x3, 0x31, 0x18);
- break;
- case 26:
- halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xe3,
- 0xa, 0x3, 0x31, 0x18);
- break;
- case 27:
- halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x25, 0x3, 0x31, 0x98);
- break;
- case 28:
- halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x69,
- 0x25, 0x3, 0x31, 0x0);
- break;
- case 29:
- halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xab,
- 0x1a, 0x1a, 0x1, 0x10);
- break;
- case 30:
- halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x51,
- 0x30, 0x3, 0x10, 0x10);
- break;
- case 31:
- halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xd3,
- 0x1a, 0x1a, 0, 0x58);
- break;
- case 32:
- halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x61,
- 0x35, 0x3, 0x11, 0x11);
- break;
- case 33:
- halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xa3,
- 0x25, 0x3, 0x30, 0x90);
- break;
- case 34:
- halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x53,
- 0x1a, 0x1a, 0x0, 0x10);
- break;
- case 35:
- halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x63,
- 0x1a, 0x1a, 0x0, 0x10);
- break;
- case 36:
- halbtc8812a1ant_set_fw_pstdma(btcoexist, 0xd3,
- 0x12, 0x3, 0x14, 0x50);
- break;
- case 40: /* SoftAP only with no sta associated,BT disable ,TDMA mode for power saving */
- /* here softap mode screen off will cost 70-80mA for phone */
- halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x23,
- 0x18, 0x00, 0x10, 0x24);
- break;
- }
- } else {
-
- /* disable PS tdma */
- switch (type) {
- case 8: /* PTA Control */
- halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x8,
- 0x0, 0x0, 0x0, 0x0);
- break;
- case 0:
- default: /* Software control, Antenna at BT side */
- halbtc8812a1ant_set_fw_pstdma(btcoexist, 0x0,
- 0x0, 0x0, 0x0, 0x0);
- break;
- }
- }
- rssi_adjust_val = 0;
- btcoexist->btc_set(btcoexist,
- BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE, &rssi_adjust_val);
-
-
- /* update pre state */
- coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on;
- coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
-}
-
-boolean halbtc8812a1ant_is_common_action(IN struct btc_coexist *btcoexist)
-{
- boolean common = false, wifi_connected = false, wifi_busy = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- if (!wifi_connected &&
- BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
- coex_dm->bt_status) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n");
- BTC_TRACE(trace_buf);
-
- /* halbtc8812a1ant_sw_mechanism(btcoexist, false); */
-
- common = true;
- } else if (wifi_connected &&
- (BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
- coex_dm->bt_status)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi connected + BT non connected-idle!!\n");
- BTC_TRACE(trace_buf);
-
- /* halbtc8812a1ant_sw_mechanism(btcoexist, false); */
-
- common = true;
- } else if (!wifi_connected &&
- (BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi non connected-idle + BT connected-idle!!\n");
- BTC_TRACE(trace_buf);
-
- /* halbtc8812a1ant_sw_mechanism(btcoexist, false); */
-
- common = true;
- } else if (wifi_connected &&
- (BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi connected + BT connected-idle!!\n");
- BTC_TRACE(trace_buf);
-
- /* halbtc8812a1ant_sw_mechanism(btcoexist, false); */
-
- common = true;
- } else if (!wifi_connected &&
- (BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE != coex_dm->bt_status)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi non connected-idle + BT Busy!!\n");
- BTC_TRACE(trace_buf);
-
- /* halbtc8812a1ant_sw_mechanism(btcoexist, false); */
-
- common = true;
- } else {
- if (wifi_busy) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi Connected-Busy + BT Busy!!\n");
- BTC_TRACE(trace_buf);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi Connected-Idle + BT Busy!!\n");
- BTC_TRACE(trace_buf);
- }
-
- common = false;
- }
-
- return common;
-}
-
-
-void halbtc8812a1ant_tdma_duration_adjust_for_acl(IN struct btc_coexist
- *btcoexist, IN u8 wifi_status)
-{
- static s32 up, dn, m, n, wait_count;
- s32 result; /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */
- u8 retry_count = 0, bt_info_ext;
- boolean wifi_busy = false;
-
- if (BT_8812A_1ANT_WIFI_STATUS_CONNECTED_BUSY == wifi_status)
- wifi_busy = true;
- else
- wifi_busy = false;
-
- if ((BT_8812A_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN ==
- wifi_status) ||
- (BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SCAN == wifi_status) ||
- (BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT ==
- wifi_status)) {
- if (coex_dm->cur_ps_tdma != 1 &&
- coex_dm->cur_ps_tdma != 2 &&
- coex_dm->cur_ps_tdma != 3 &&
- coex_dm->cur_ps_tdma != 9) {
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 9);
- coex_dm->ps_tdma_du_adj_type = 9;
-
- up = 0;
- dn = 0;
- m = 1;
- n = 3;
- result = 0;
- wait_count = 0;
- }
- return;
- }
-
- if (!coex_dm->auto_tdma_adjust) {
- coex_dm->auto_tdma_adjust = true;
-
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 2);
- coex_dm->ps_tdma_du_adj_type = 2;
- /* ============ */
- up = 0;
- dn = 0;
- m = 1;
- n = 3;
- result = 0;
- wait_count = 0;
- } else {
- /* accquire the BT TRx retry count from BT_Info byte2 */
- retry_count = coex_sta->bt_retry_cnt;
- bt_info_ext = coex_sta->bt_info_ext;
-
- if ((coex_sta->low_priority_tx) > 1150 ||
- (coex_sta->low_priority_rx) > 1250)
- retry_count++;
-
- result = 0;
- wait_count++;
-
- if (retry_count ==
- 0) { /* no retry in the last 2-second duration */
- up++;
- dn--;
-
- if (dn <= 0)
- dn = 0;
-
- if (up >= n) { /* if retry count during continuous n*2 seconds is 0, enlarge WiFi duration */
- wait_count = 0;
- n = 3;
- up = 0;
- dn = 0;
- result = 1;
- }
- } else if (retry_count <=
- 3) { /* <=3 retry in the last 2-second duration */
- up--;
- dn++;
-
- if (up <= 0)
- up = 0;
-
- if (dn == 2) { /* if continuous 2 retry count(every 2 seconds) >0 and < 3, reduce WiFi duration */
- if (wait_count <= 2)
- m++; /* to avoid loop between the two levels */
- else
- m = 1;
-
- if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */
- m = 20;
-
- n = 3 * m;
- up = 0;
- dn = 0;
- wait_count = 0;
- result = -1;
- }
- } else { /* retry count > 3, once retry count > 3, to reduce WiFi duration */
- if (wait_count == 1)
- m++; /* to avoid loop between the two levels */
- else
- m = 1;
-
- if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */
- m = 20;
-
- n = 3 * m;
- up = 0;
- dn = 0;
- wait_count = 0;
- result = -1;
- }
-
- if (result == -1) {
- if ((BT_INFO_8812A_1ANT_A2DP_BASIC_RATE(bt_info_ext)) &&
- ((coex_dm->cur_ps_tdma == 1) ||
- (coex_dm->cur_ps_tdma == 2))) {
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 9);
- coex_dm->ps_tdma_du_adj_type = 9;
- } else if (coex_dm->cur_ps_tdma == 1) {
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 2);
- coex_dm->ps_tdma_du_adj_type = 2;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 9);
- coex_dm->ps_tdma_du_adj_type = 9;
- } else if (coex_dm->cur_ps_tdma == 9) {
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type = 11;
- }
- } else if (result == 1) {
- if ((BT_INFO_8812A_1ANT_A2DP_BASIC_RATE(bt_info_ext)) &&
- ((coex_dm->cur_ps_tdma == 1) ||
- (coex_dm->cur_ps_tdma == 2))) {
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 9);
- coex_dm->ps_tdma_du_adj_type = 9;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 9);
- coex_dm->ps_tdma_du_adj_type = 9;
- } else if (coex_dm->cur_ps_tdma == 9) {
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 2);
- coex_dm->ps_tdma_du_adj_type = 2;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 1);
- coex_dm->ps_tdma_du_adj_type = 1;
- }
- } else { /* no change */
- /* Bryant Modify
- if(wifi_busy != pre_wifi_busy)
- {
- pre_wifi_busy = wifi_busy;
- halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, true, coex_dm->cur_ps_tdma);
- }
- */
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** TDMA(on, %d) **********\n",
- coex_dm->cur_ps_tdma);
- BTC_TRACE(trace_buf);
- }
-
- if (coex_dm->cur_ps_tdma != 1 &&
- coex_dm->cur_ps_tdma != 2 &&
- coex_dm->cur_ps_tdma != 9 &&
- coex_dm->cur_ps_tdma != 11) {
- /* recover to previous adjust type */
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- coex_dm->ps_tdma_du_adj_type);
- }
- }
-}
-
-void halbtc8812a1ant_ps_tdma_check_for_power_save_state(
- IN struct btc_coexist *btcoexist, IN boolean new_ps_state)
-{
- u8 lps_mode = 0x0;
-
- btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode);
-
- if (lps_mode) { /* already under LPS state */
- if (new_ps_state) {
- /* keep state under LPS, do nothing. */
- } else {
- /* will leave LPS state, turn off psTdma first */
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 8);
- }
- } else { /* NO PS state */
- if (new_ps_state) {
- /* will enter LPS state, turn off psTdma first */
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 8);
- } else {
- /* keep state under NO PS state, do nothing. */
- }
- }
-}
-
-void halbtc8812a1ant_power_save_state(IN struct btc_coexist *btcoexist,
- IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val)
-{
- boolean low_pwr_disable = false;
-
- switch (ps_type) {
- case BTC_PS_WIFI_NATIVE:
- /* recover to original 32k low power setting */
- low_pwr_disable = false;
- btcoexist->btc_set(btcoexist,
- BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS,
- NULL);
- coex_sta->force_lps_on = false;
- break;
- case BTC_PS_LPS_ON:
- halbtc8812a1ant_ps_tdma_check_for_power_save_state(
- btcoexist, true);
- halbtc8812a1ant_lps_rpwm(btcoexist, NORMAL_EXEC,
- lps_val, rpwm_val);
- /* when coex force to enter LPS, do not enter 32k low power. */
- low_pwr_disable = true;
- btcoexist->btc_set(btcoexist,
- BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
- /* power save must executed before psTdma. */
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS,
- NULL);
- coex_sta->force_lps_on = true;
- break;
- case BTC_PS_LPS_OFF:
- halbtc8812a1ant_ps_tdma_check_for_power_save_state(
- btcoexist, false);
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS,
- NULL);
- coex_sta->force_lps_on = false;
- break;
- default:
- break;
- }
-}
-
-void halbtc8812a1ant_action_wifi_only(IN struct btc_coexist *btcoexist)
-{
- halbtc8812a1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
- halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8);
- halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, FORCE_EXEC,
- false, false);
-}
-
-void halbtc8812a1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist)
-{
- static u32 bt_disable_cnt = 0;
- boolean bt_active = true, bt_disabled = false;
-
- /* This function check if bt is disabled */
-
- if (coex_sta->high_priority_tx == 0 &&
- coex_sta->high_priority_rx == 0 &&
- coex_sta->low_priority_tx == 0 &&
- coex_sta->low_priority_rx == 0)
- bt_active = false;
- if (coex_sta->high_priority_tx == 0xffff &&
- coex_sta->high_priority_rx == 0xffff &&
- coex_sta->low_priority_tx == 0xffff &&
- coex_sta->low_priority_rx == 0xffff)
- bt_active = false;
- if (bt_active) {
- bt_disable_cnt = 0;
- bt_disabled = false;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
- &bt_disabled);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is enabled !!\n");
- BTC_TRACE(trace_buf);
- } else {
- bt_disable_cnt++;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], bt all counters=0, %d times!!\n",
- bt_disable_cnt);
- BTC_TRACE(trace_buf);
- if (bt_disable_cnt >= 2) {
- bt_disabled = true;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
- &bt_disabled);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is disabled !!\n");
- BTC_TRACE(trace_buf);
- halbtc8812a1ant_action_wifi_only(btcoexist);
- }
- }
- if (coex_sta->bt_disabled != bt_disabled) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is from %s to %s!!\n",
- (coex_sta->bt_disabled ? "disabled" : "enabled"),
- (bt_disabled ? "disabled" : "enabled"));
- BTC_TRACE(trace_buf);
- coex_sta->bt_disabled = bt_disabled;
- if (!bt_disabled) {
- } else {
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS,
- NULL);
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS,
- NULL);
- }
- }
-}
-
-/* *********************************************
- *
- * Software Coex Mechanism start
- *
- * ********************************************* */
-
-/* SCO only or SCO+PAN(HS) */
-
-/*
-void halbtc8812a1ant_action_sco(IN struct btc_coexist* btcoexist)
-{
- halbtc8812a1ant_sw_mechanism(btcoexist, true);
-}
-
-
-void halbtc8812a1ant_action_hid(IN struct btc_coexist* btcoexist)
-{
- halbtc8812a1ant_sw_mechanism(btcoexist, true);
-}
-
-
-void halbtc8812a1ant_action_a2dp(IN struct btc_coexist* btcoexist)
-{
- halbtc8812a1ant_sw_mechanism(btcoexist, false);
-}
-
-void halbtc8812a1ant_action_a2dp_pan_hs(IN struct btc_coexist* btcoexist)
-{
- halbtc8812a1ant_sw_mechanism(btcoexist, false);
-}
-
-void halbtc8812a1ant_action_pan_edr(IN struct btc_coexist* btcoexist)
-{
- halbtc8812a1ant_sw_mechanism(btcoexist, false);
-}
-
-
-void halbtc8812a1ant_action_pan_hs(IN struct btc_coexist* btcoexist)
-{
- halbtc8812a1ant_sw_mechanism(btcoexist, false);
-}
-
-
-void halbtc8812a1ant_action_pan_edr_a2dp(IN struct btc_coexist* btcoexist)
-{
- halbtc8812a1ant_sw_mechanism(btcoexist, false);
-}
-
-void halbtc8812a1ant_action_pan_edr_hid(IN struct btc_coexist* btcoexist)
-{
- halbtc8812a1ant_sw_mechanism(btcoexist, true);
-}
-
-
-void halbtc8812a1ant_action_hid_a2dp_pan_edr(IN struct btc_coexist* btcoexist)
-{
- halbtc8812a1ant_sw_mechanism(btcoexist, true);
-}
-
-void halbtc8812a1ant_action_hid_a2dp(IN struct btc_coexist* btcoexist)
-{
- halbtc8812a1ant_sw_mechanism(btcoexist, true);
-}
-
-*/
-
-/* *********************************************
- *
- * Non-Software Coex Mechanism start
- *
- * ********************************************* */
-void halbtc8812a1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist)
-{
- halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
-
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC,
- false, false);
- halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
-}
-
-void halbtc8812a1ant_action_hs(IN struct btc_coexist *btcoexist)
-{
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
- halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
-}
-
-void halbtc8812a1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_connected = false, ap_enable = false, wifi_busy = false,
- bt_busy = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
- &ap_enable);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
-
- if ((!wifi_connected) && (!coex_sta->wifi_is_high_pri_task)) {
- halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
- NORMAL_EXEC, false, false);
- halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
- } else if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) ||
- (bt_link_info->a2dp_exist)) {
- /* SCO/HID/A2DP busy */
- halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
-
- halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- } else if ((bt_link_info->pan_exist) || (wifi_busy)) {
- halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
-
- halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- } else {
- halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
- NORMAL_EXEC, false, false);
- halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
- }
-}
-
-void halbtc8812a1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist
- *btcoexist, IN u8 wifi_status)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_connected = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
-
- /* tdma and coex table */
-
- if (bt_link_info->sco_exist) {
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
- halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
- } else { /* HID */
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 6);
- halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
- }
-}
-
-void halbtc8812a1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist
- *btcoexist, IN u8 wifi_status)
-{
- u8 bt_rssi_state;
-
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- bt_rssi_state = halbtc8812a1ant_bt_rssi_state(2, 28, 0);
-
- if ((coex_sta->low_priority_rx >= 950) && (!coex_sta->under_ips))
- bt_link_info->slave_role = true;
- else
- bt_link_info->slave_role = false;
-
- if (bt_link_info->hid_only) { /* HID */
- halbtc8812a1ant_action_bt_sco_hid_only_busy(btcoexist,
- wifi_status);
- coex_dm->auto_tdma_adjust = false;
- return;
- } else if (bt_link_info->a2dp_only) { /* A2DP */
- if (BT_8812A_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifi_status) {
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 32);
- halbtc8812a1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- coex_dm->auto_tdma_adjust = false;
- } else {
- halbtc8812a1ant_tdma_duration_adjust_for_acl(btcoexist,
- wifi_status);
- halbtc8812a1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- coex_dm->auto_tdma_adjust = true;
- }
- } else if (((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) ||
- (bt_link_info->hid_exist && bt_link_info->a2dp_exist &&
- bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13);
- halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- coex_dm->auto_tdma_adjust = false;
- } else if (bt_link_info->hid_exist &&
- bt_link_info->a2dp_exist) { /* HID+A2DP */
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14);
- coex_dm->auto_tdma_adjust = false;
-
- halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
- } else if ((bt_link_info->pan_only) || (bt_link_info->hid_exist &&
- bt_link_info->pan_exist)) { /* PAN(OPP,FTP), HID+PAN(OPP,FTP) */
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3);
- halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- coex_dm->auto_tdma_adjust = false;
- } else {
- /* BT no-profile busy (0x9) */
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
- halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- coex_dm->auto_tdma_adjust = false;
- }
-}
-
-void halbtc8812a1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist)
-{
- /* power save state */
- halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
-
- /* tdma and coex table */
- halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8);
- halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC,
- false, false);
- halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-}
-
-void halbtc8812a1ant_action_wifi_not_connected_scan(IN struct btc_coexist
- *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
- halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
-
- /* tdma and coex table */
- if (BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
- if (bt_link_info->a2dp_exist) {
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 32);
- halbtc8812a1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- } else if (bt_link_info->a2dp_exist &&
- bt_link_info->pan_exist) {
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 22);
- halbtc8812a1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- } else {
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 20);
- halbtc8812a1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- }
- } else if ((BT_8812A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
- (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY ==
- coex_dm->bt_status)) {
- halbtc8812a1ant_action_bt_sco_hid_only_busy(btcoexist,
- BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SCAN);
- } else {
- /* Bryant Add */
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
- NORMAL_EXEC, false, false);
- halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
- }
-}
-
-void halbtc8812a1ant_action_wifi_not_connected_asso_auth(
- IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
- halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
-
- /* tdma and coex table */
- if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) ||
- (bt_link_info->a2dp_exist)) {
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
- halbtc8812a1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4);
- } else if (bt_link_info->pan_exist) {
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
- halbtc8812a1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4);
- } else {
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
- NORMAL_EXEC, false, false);
- halbtc8812a1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 2);
- }
-}
-
-void halbtc8812a1ant_action_wifi_connected_scan(IN struct btc_coexist
- *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
- halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
-
- /* tdma and coex table */
- if (BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
- if (bt_link_info->a2dp_exist) {
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 32);
- halbtc8812a1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- } else if (bt_link_info->a2dp_exist &&
- bt_link_info->pan_exist) {
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 22);
- halbtc8812a1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- } else {
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 20);
- halbtc8812a1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- }
- } else if ((BT_8812A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
- (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY ==
- coex_dm->bt_status)) {
- halbtc8812a1ant_action_bt_sco_hid_only_busy(btcoexist,
- BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SCAN);
- } else {
- /* Bryant Add */
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
- NORMAL_EXEC, false, false);
- halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
- }
-}
-
-void halbtc8812a1ant_action_wifi_connected_specific_packet(
- IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
- halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
-
- /* tdma and coex table */
- if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) ||
- (bt_link_info->a2dp_exist)) {
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
- halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- } else if (bt_link_info->pan_exist) {
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
- halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- } else {
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
- NORMAL_EXEC, false, false);
- halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
- }
-}
-
-void halbtc8812a1ant_action_wifi_connected(IN struct btc_coexist *btcoexist)
-{
- boolean wifi_busy = false;
- boolean scan = false, link = false, roam = false;
- boolean under_4way = false, ap_enable = false;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CoexForWifiConnect()===>\n");
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
- &under_4way);
- if (under_4way) {
- halbtc8812a1ant_action_wifi_connected_specific_packet(btcoexist);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CoexForWifiConnect(), return for wifi is under 4way<===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
- if (scan || link || roam) {
- if (scan)
- halbtc8812a1ant_action_wifi_connected_scan(btcoexist);
- else
- halbtc8812a1ant_action_wifi_connected_specific_packet(
- btcoexist);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CoexForWifiConnect(), return for wifi is under scan<===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
- &ap_enable);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- /* power save state */
- if (!ap_enable &&
- BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status &&
- !btcoexist->bt_link_info.hid_only) {
- if (btcoexist->bt_link_info.a2dp_only) { /* A2DP */
- if (!wifi_busy)
- halbtc8812a1ant_power_save_state(btcoexist,
- BTC_PS_WIFI_NATIVE, 0x0, 0x0);
- else { /* busy */
- if (coex_sta->scan_ap_num >=
- BT_8812A_1ANT_WIFI_NOISY_THRESH) /* no force LPS, no PS-TDMA, use pure TDMA */
- halbtc8812a1ant_power_save_state(
- btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- else
- halbtc8812a1ant_power_save_state(
- btcoexist, BTC_PS_LPS_ON, 0x50,
- 0x4);
- }
- } else if ((coex_sta->pan_exist == false) &&
- (coex_sta->a2dp_exist == false) &&
- (coex_sta->hid_exist == false))
- halbtc8812a1ant_power_save_state(btcoexist,
- BTC_PS_WIFI_NATIVE, 0x0, 0x0);
- else
- halbtc8812a1ant_power_save_state(btcoexist,
- BTC_PS_LPS_ON, 0x50, 0x4);
- } else
- halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
-
- /* tdma and coex table */
- if (!wifi_busy) {
- if (BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
- halbtc8812a1ant_action_wifi_connected_bt_acl_busy(
- btcoexist,
- BT_8812A_1ANT_WIFI_STATUS_CONNECTED_IDLE);
- } else if ((BT_8812A_1ANT_BT_STATUS_SCO_BUSY ==
- coex_dm->bt_status) ||
- (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY ==
- coex_dm->bt_status)) {
- halbtc8812a1ant_action_bt_sco_hid_only_busy(btcoexist,
- BT_8812A_1ANT_WIFI_STATUS_CONNECTED_IDLE);
- } else {
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 8);
- halbtc8812a1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_PTA, NORMAL_EXEC, false, false);
- if ((coex_sta->high_priority_tx) +
- (coex_sta->high_priority_rx) <= 60)
- halbtc8812a1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 2);
- else
- halbtc8812a1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 7);
- }
- } else {
- if (BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
- halbtc8812a1ant_action_wifi_connected_bt_acl_busy(
- btcoexist,
- BT_8812A_1ANT_WIFI_STATUS_CONNECTED_BUSY);
- } else if ((BT_8812A_1ANT_BT_STATUS_SCO_BUSY ==
- coex_dm->bt_status) ||
- (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY ==
- coex_dm->bt_status)) {
- halbtc8812a1ant_action_bt_sco_hid_only_busy(btcoexist,
- BT_8812A_1ANT_WIFI_STATUS_CONNECTED_BUSY);
- } else {
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 8);
- halbtc8812a1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_PTA, NORMAL_EXEC, false, false);
- if ((coex_sta->high_priority_tx) +
- (coex_sta->high_priority_rx) <= 60)
- halbtc8812a1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 2);
- else
- halbtc8812a1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 7);
- }
- }
-}
-
-void halbtc8812a1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist)
-{
- u8 algorithm = 0;
-
- algorithm = halbtc8812a1ant_action_algorithm(btcoexist);
- coex_dm->cur_algorithm = algorithm;
-
- if (halbtc8812a1ant_is_common_action(btcoexist)) {
-
- } else {
- switch (coex_dm->cur_algorithm) {
- case BT_8812A_1ANT_COEX_ALGO_SCO:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = SCO.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8812a1ant_action_sco(btcoexist); */
- break;
- case BT_8812A_1ANT_COEX_ALGO_HID:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = HID.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8812a1ant_action_hid(btcoexist); */
- break;
- case BT_8812A_1ANT_COEX_ALGO_A2DP:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = A2DP.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8812a1ant_action_a2dp(btcoexist); */
- break;
- case BT_8812A_1ANT_COEX_ALGO_A2DP_PANHS:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = A2DP+PAN(HS).\n");
- BTC_TRACE(trace_buf);
- /* halbtc8812a1ant_action_a2dp_pan_hs(btcoexist); */
- break;
- case BT_8812A_1ANT_COEX_ALGO_PANEDR:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = PAN(EDR).\n");
- BTC_TRACE(trace_buf);
- /* halbtc8812a1ant_action_pan_edr(btcoexist); */
- break;
- case BT_8812A_1ANT_COEX_ALGO_PANHS:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = HS mode.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8812a1ant_action_pan_hs(btcoexist); */
- break;
- case BT_8812A_1ANT_COEX_ALGO_PANEDR_A2DP:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = PAN+A2DP.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8812a1ant_action_pan_edr_a2dp(btcoexist); */
- break;
- case BT_8812A_1ANT_COEX_ALGO_PANEDR_HID:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = PAN(EDR)+HID.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8812a1ant_action_pan_edr_hid(btcoexist); */
- break;
- case BT_8812A_1ANT_COEX_ALGO_HID_A2DP_PANEDR:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = HID+A2DP+PAN.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8812a1ant_action_hid_a2dp_pan_edr(btcoexist); */
- break;
- case BT_8812A_1ANT_COEX_ALGO_HID_A2DP:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = HID+A2DP.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8812a1ant_action_hid_a2dp(btcoexist); */
- break;
- default:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = coexist All Off!!\n");
- BTC_TRACE(trace_buf);
- /* halbtc8812a1ant_coex_all_off(btcoexist); */
- break;
- }
- coex_dm->pre_algorithm = coex_dm->cur_algorithm;
- }
-}
-
-void halbtc8812a1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_connected = false, bt_hs_on = false;
- boolean increase_scan_dev_num = false;
- boolean bt_ctrl_agg_buf_size = false;
- boolean miracast_plus_bt = false;
- u8 agg_buf_size = 5;
- u32 wifi_link_status = 0;
- u32 num_of_wifi_link = 0, wifi_bw;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism()===>\n");
- BTC_TRACE(trace_buf);
-
- if (btcoexist->manual_control) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- if (btcoexist->stop_coex_dm) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- if (coex_sta->under_ips) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], wifi is under IPS !!!\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- if ((BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
- (BT_8812A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
- (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status))
- increase_scan_dev_num = true;
-
- btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM,
- &increase_scan_dev_num);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
- num_of_wifi_link = wifi_link_status >> 16;
-
- if ((num_of_wifi_link >= 2) ||
- (wifi_link_status & WIFI_P2P_GO_CONNECTED)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n",
- num_of_wifi_link, wifi_link_status);
- BTC_TRACE(trace_buf);
-
- if (bt_link_info->bt_link_exist) {
- halbtc8812a1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1,
- 0, 1);
- miracast_plus_bt = true;
- } else {
- halbtc8812a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0,
- 0, 0);
- miracast_plus_bt = false;
- }
- btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
- &miracast_plus_bt);
- halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
- bt_ctrl_agg_buf_size, agg_buf_size);
-
- if ((bt_link_info->a2dp_exist) &&
- (coex_sta->c2h_bt_inquiry_page)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], BT Is Inquirying\n");
- BTC_TRACE(trace_buf);
- halbtc8812a1ant_action_bt_inquiry(btcoexist);
- } else
- halbtc8812a1ant_action_wifi_multi_port(btcoexist);
-
- return;
- } else {
- miracast_plus_bt = false;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
- &miracast_plus_bt);
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- if ((bt_link_info->bt_link_exist) && (wifi_connected)) {
- halbtc8812a1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, 0, 1);
-
- if (bt_link_info->sco_exist)
- halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC, true,
- false, 0x5);
- else {
- if (BTC_WIFI_BW_HT40 == wifi_bw)
- halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC,
- false, true, 0x10);
- else
- halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC,
- false, true, 0x8);
- }
-
- halbtc8812a1ant_sw_mechanism(btcoexist, true);
- halbtc8812a1ant_run_sw_coexist_mechanism(
- btcoexist); /* just print debug message */
- } else {
- halbtc8812a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
-
- halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
- 0x5);
-
- halbtc8812a1ant_sw_mechanism(btcoexist, false);
- halbtc8812a1ant_run_sw_coexist_mechanism(
- btcoexist); /* //just print debug message */
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- if (coex_sta->c2h_bt_inquiry_page) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], BT Is Inquirying\n");
- BTC_TRACE(trace_buf);
- halbtc8812a1ant_action_bt_inquiry(btcoexist);
- return;
- } else if (bt_hs_on) {
- halbtc8812a1ant_action_hs(btcoexist);
- return;
- }
-
-
- if (!wifi_connected) {
- boolean scan = false, link = false, roam = false;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], wifi is non connected-idle !!!\n");
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
-
- if (scan || link || roam) {
- if (scan)
- halbtc8812a1ant_action_wifi_not_connected_scan(
- btcoexist);
- else
- halbtc8812a1ant_action_wifi_not_connected_asso_auth(
- btcoexist);
- } else
- halbtc8812a1ant_action_wifi_not_connected(btcoexist);
- } else /* wifi LPS/Busy */
- halbtc8812a1ant_action_wifi_connected(btcoexist);
-}
-
-void halbtc8812a1ant_init_coex_dm(IN struct btc_coexist *btcoexist)
-{
- /* force to reset coex mechanism */
-
- /* sw all off */
- halbtc8812a1ant_sw_mechanism(btcoexist, false);
-
- /* halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); */
- /* halbtc8812a1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); */
-
- coex_sta->pop_event_cnt = 0;
-}
-
-void halbtc8812a1ant_init_hw_config(IN struct btc_coexist *btcoexist,
- IN boolean back_up, IN boolean wifi_only)
-{
- u8 u8tmp = 0;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], 1Ant Init HW Config!!\n");
- BTC_TRACE(trace_buf);
-
- /* ant sw control to BT */
- halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, FORCE_EXEC,
- true, false);
-
- /* 0x790[5:0]=0x5 */
- u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790);
- u8tmp &= 0xc0;
- u8tmp |= 0x5;
- btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp);
-
- /* PTA parameter */
- btcoexist->btc_write_1byte(btcoexist, 0x6cc, 0x0);
- btcoexist->btc_write_4byte(btcoexist, 0x6c8, 0xffff);
- btcoexist->btc_write_4byte(btcoexist, 0x6c4, 0x55555555);
- btcoexist->btc_write_4byte(btcoexist, 0x6c0, 0x55555555);
-
- /* coex parameters */
- btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1);
-
- /* enable counter statistics */
- btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4);
-
- /* enable PTA */
- btcoexist->btc_write_1byte(btcoexist, 0x40, 0x20);
-
- /* bt clock related */
- u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x4);
- u8tmp |= BIT(7);
- btcoexist->btc_write_1byte(btcoexist, 0x4, u8tmp);
-
- /* bt clock related */
- u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x7);
- u8tmp |= BIT(1);
- btcoexist->btc_write_1byte(btcoexist, 0x7, u8tmp);
-}
-
-/* ************************************************************
- * work around function start with wa_halbtc8812a1ant_
- * ************************************************************
- * ************************************************************
- * extern function start with ex_halbtc8812a1ant_
- * ************************************************************ */
-void ex_halbtc8812a1ant_power_on_setting(IN struct btc_coexist *btcoexist)
-{
-}
-
-void ex_halbtc8812a1ant_pre_load_firmware(IN struct btc_coexist *btcoexist)
-{
-}
-
-void ex_halbtc8812a1ant_init_hw_config(IN struct btc_coexist *btcoexist,
- IN boolean wifi_only)
-{
- halbtc8812a1ant_init_hw_config(btcoexist, true, wifi_only);
- btcoexist->stop_coex_dm = false;
-}
-
-void ex_halbtc8812a1ant_init_coex_dm(IN struct btc_coexist *btcoexist)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Coex Mechanism Init!!\n");
- BTC_TRACE(trace_buf);
-
- btcoexist->stop_coex_dm = false;
-
- halbtc8812a1ant_init_coex_dm(btcoexist);
-
- halbtc8812a1ant_query_bt_info(btcoexist);
-}
-
-void ex_halbtc8812a1ant_display_coex_info(IN struct btc_coexist *btcoexist)
-{
- struct btc_board_info *board_info = &btcoexist->board_info;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- u8 *cli_buf = btcoexist->cli_buf;
- u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0;
- u32 u32tmp[4];
- u32 fw_ver = 0, bt_patch_ver = 0;
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ============[BT Coexist info]============");
- CL_PRINTF(cli_buf);
-
- if (btcoexist->manual_control) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ============[Under Manual Control]============");
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ==========================================");
- CL_PRINTF(cli_buf);
- }
- if (btcoexist->stop_coex_dm) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ============[Coex is STOPPED]============");
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ==========================================");
- CL_PRINTF(cli_buf);
- }
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ",
- "Ant PG number/ Ant mechanism:",
- board_info->pg_ant_num, board_info->btdm_ant_num);
- CL_PRINTF(cli_buf);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %d_%d/ 0x%x/ 0x%x(%d)",
- "CoexVer/ FwVer/ PatchVer",
- glcoex_ver_date_8812a_1ant, glcoex_ver_8812a_1ant, fw_ver,
- bt_patch_ver, bt_patch_ver);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ",
- "Wifi channel informed to BT",
- coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
- coex_dm->wifi_chnl_info[2]);
- CL_PRINTF(cli_buf);
-
- /* wifi status */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Wifi Status]============");
- CL_PRINTF(cli_buf);
- btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[BT Status]============");
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ",
- "BT [status/ rssi/ retryCnt]",
- ((coex_sta->bt_disabled) ? ("disabled") : ((
- coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan")
- : ((BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
- coex_dm->bt_status) ? "non-connected idle" :
- ((BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)
- ? "connected-idle" : "busy")))),
- coex_sta->bt_rssi, coex_sta->bt_retry_cnt);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d",
- "SCO/HID/PAN/A2DP",
- bt_link_info->sco_exist, bt_link_info->hid_exist,
- bt_link_info->pan_exist, bt_link_info->a2dp_exist);
- CL_PRINTF(cli_buf);
- btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_BT_LINK_INFO);
-
- bt_info_ext = coex_sta->bt_info_ext;
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
- "BT Info A2DP rate",
- (bt_info_ext & BIT(0)) ? "Basic rate" : "EDR rate");
- CL_PRINTF(cli_buf);
-
- for (i = 0; i < BT_INFO_SRC_8812A_1ANT_MAX; i++) {
- if (coex_sta->bt_info_c2h_cnt[i]) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)",
- glbt_info_src_8812a_1ant[i],
- coex_sta->bt_info_c2h[i][0],
- coex_sta->bt_info_c2h[i][1],
- coex_sta->bt_info_c2h[i][2],
- coex_sta->bt_info_c2h[i][3],
- coex_sta->bt_info_c2h[i][4],
- coex_sta->bt_info_c2h[i][5],
- coex_sta->bt_info_c2h[i][6],
- coex_sta->bt_info_c2h_cnt[i]);
- CL_PRINTF(cli_buf);
- }
- }
-
- if (!btcoexist->manual_control) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[mechanisms]============");
- CL_PRINTF(cli_buf);
-
- ps_tdma_case = coex_dm->cur_ps_tdma;
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %02x %02x %02x %02x %02x case-%d",
- "PS TDMA",
- coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],
- coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],
- coex_dm->ps_tdma_para[4], ps_tdma_case);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ",
- "Latest error condition(should be 0)",
- coex_dm->error_condition);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ",
- "IgnWlanAct",
- coex_dm->cur_ignore_wlan_act);
- CL_PRINTF(cli_buf);
- }
-
- /* Hw setting */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Hw setting]============");
- CL_PRINTF(cli_buf);
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x778",
- u8tmp[0]);
- CL_PRINTF(cli_buf);
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xcb3);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xcb7);
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x900);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
- "0xcb3/0xcb7/0x900",
- u8tmp[0], u8tmp[1], u32tmp[0]);
- CL_PRINTF(cli_buf);
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x40);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x40",
- u8tmp[0]);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
- "0x550(bcn ctrl)/0x522",
- u32tmp[0], u8tmp[0]);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)",
- u32tmp[0]);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
- u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x6cc);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
- "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)",
- u32tmp[0], u32tmp[1], u32tmp[2], u8tmp[0]);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
- "0x770(hp rx[31:16]/tx[15:0])",
- coex_sta->high_priority_rx, coex_sta->high_priority_tx);
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
- "0x774(lp rx[31:16]/tx[15:0])",
- coex_sta->low_priority_rx, coex_sta->low_priority_tx);
- CL_PRINTF(cli_buf);
-
- btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
-}
-
-
-
-void ex_halbtc8812a1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type)
-{
- if (btcoexist->manual_control || btcoexist->stop_coex_dm)
- return;
-
- if (BTC_IPS_ENTER == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], IPS ENTER notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_ips = true;
-
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT,
- FORCE_EXEC, false, true);
- halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
- } else if (BTC_IPS_LEAVE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], IPS LEAVE notify\n");
- BTC_TRACE(trace_buf);
-
- halbtc8812a1ant_init_hw_config(btcoexist, false, false);
- halbtc8812a1ant_init_coex_dm(btcoexist);
- halbtc8812a1ant_query_bt_info(btcoexist);
-
- coex_sta->under_ips = false;
- }
-}
-
-void ex_halbtc8812a1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type)
-{
- if (btcoexist->manual_control || btcoexist->stop_coex_dm)
- return;
-
- if (BTC_LPS_ENABLE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], LPS ENABLE notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_lps = true;
- } else if (BTC_LPS_DISABLE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], LPS DISABLE notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_lps = false;
- }
-}
-
-void ex_halbtc8812a1ant_scan_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- boolean wifi_connected = false, bt_hs_on = false;
- u32 wifi_link_status = 0;
- u32 num_of_wifi_link = 0;
- boolean bt_ctrl_agg_buf_size = false;
- u8 agg_buf_size = 5;
-
- if (btcoexist->manual_control ||
- btcoexist->stop_coex_dm)
- return;
-
- if (BTC_SCAN_START == type) {
- coex_sta->wifi_is_high_pri_task = true;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCAN START notify\n");
- BTC_TRACE(trace_buf);
-
- halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false,
- 8); /* Force antenna setup for no scan result issue */
- halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
- FORCE_EXEC, false, false);
- } else {
- coex_sta->wifi_is_high_pri_task = false;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCAN FINISH notify\n");
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
- &coex_sta->scan_ap_num);
- }
-
- if (coex_sta->bt_disabled)
- return;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
-
- halbtc8812a1ant_query_bt_info(btcoexist);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
- num_of_wifi_link = wifi_link_status >> 16;
- if (num_of_wifi_link >= 2) {
- halbtc8812a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
- halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
- bt_ctrl_agg_buf_size, agg_buf_size);
- halbtc8812a1ant_action_wifi_multi_port(btcoexist);
- return;
- }
-
- if (coex_sta->c2h_bt_inquiry_page) {
- halbtc8812a1ant_action_bt_inquiry(btcoexist);
- return;
- } else if (bt_hs_on) {
- halbtc8812a1ant_action_hs(btcoexist);
- return;
- }
-
- if (BTC_SCAN_START == type) {
- if (!wifi_connected) /* non-connected scan */
- halbtc8812a1ant_action_wifi_not_connected_scan(
- btcoexist);
- else /* wifi is connected */
- halbtc8812a1ant_action_wifi_connected_scan(btcoexist);
- } else if (BTC_SCAN_FINISH == type) {
- if (!wifi_connected) /* non-connected scan */
- halbtc8812a1ant_action_wifi_not_connected(btcoexist);
- else
- halbtc8812a1ant_action_wifi_connected(btcoexist);
- }
-}
-
-void ex_halbtc8812a1ant_connect_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- boolean wifi_connected = false, bt_hs_on = false;
- u32 wifi_link_status = 0;
- u32 num_of_wifi_link = 0;
- boolean bt_ctrl_agg_buf_size = false;
- u8 agg_buf_size = 5;
-
- if (btcoexist->manual_control ||
- btcoexist->stop_coex_dm ||
- coex_sta->bt_disabled)
- return;
-
- if (BTC_ASSOCIATE_START == type) {
- coex_sta->wifi_is_high_pri_task = true;
- halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false,
- 8); /* Force antenna setup for no scan result issue */
- halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
- FORCE_EXEC, false, false);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CONNECT START notify\n");
- BTC_TRACE(trace_buf);
- coex_dm->arp_cnt = 0;
- } else {
- coex_sta->wifi_is_high_pri_task = false;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CONNECT FINISH notify\n");
- BTC_TRACE(trace_buf);
- /* coex_dm->arp_cnt = 0; */
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
- num_of_wifi_link = wifi_link_status >> 16;
- if (num_of_wifi_link >= 2) {
- halbtc8812a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
- halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
- bt_ctrl_agg_buf_size, agg_buf_size);
- halbtc8812a1ant_action_wifi_multi_port(btcoexist);
- return;
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- if (coex_sta->c2h_bt_inquiry_page) {
- halbtc8812a1ant_action_bt_inquiry(btcoexist);
- return;
- } else if (bt_hs_on) {
- halbtc8812a1ant_action_hs(btcoexist);
- return;
- }
-
- if (BTC_ASSOCIATE_START == type)
- halbtc8812a1ant_action_wifi_not_connected_asso_auth(btcoexist);
- else if (BTC_ASSOCIATE_FINISH == type) {
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- if (!wifi_connected) /* non-connected scan */
- halbtc8812a1ant_action_wifi_not_connected(btcoexist);
- else
- halbtc8812a1ant_action_wifi_connected(btcoexist);
- }
-}
-
-/* to check registers... */
-void ex_halbtc8812a1ant_media_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- u8 data_len = 5;
- u8 buf[6] = {0};
- u8 h2c_parameter[3] = {0};
- u32 wifi_bw;
- u8 wifi_central_chnl;
- boolean wifi_under_b_mode = false;
-
- if (btcoexist->manual_control ||
- btcoexist->stop_coex_dm ||
- coex_sta->bt_disabled)
- return;
-
- if (BTC_MEDIA_CONNECT == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], MEDIA connect notify\n");
- BTC_TRACE(trace_buf);
- halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false,
- 8); /* Force antenna setup for no scan result issue */
- halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
- FORCE_EXEC, false, false);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
- &wifi_under_b_mode);
-#if 0
- /* Set CCK Tx/Rx high Pri except 11b mode */
- if (wifi_under_b_mode) {
- btcoexist->btc_write_1byte(btcoexist, 0x6cd,
- 0x00); /* CCK Tx */
- btcoexist->btc_write_1byte(btcoexist, 0x6cf,
- 0x00); /* CCK Rx */
- } else {
- btcoexist->btc_write_1byte(btcoexist, 0x6cd,
- 0x10); /* CCK Tx */
- btcoexist->btc_write_1byte(btcoexist, 0x6cf,
- 0x10); /* CCK Rx */
- }
-#endif
- coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist,
- 0x430);
- coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist,
- 0x434);
- coex_dm->backup_retry_limit = btcoexist->btc_read_2byte(
- btcoexist, 0x42a);
- coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte(
- btcoexist, 0x456);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], MEDIA disconnect notify\n");
- BTC_TRACE(trace_buf);
- coex_dm->arp_cnt = 0;
-
- btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */
- btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */
- }
-
- /* only 2.4G we need to inform bt the chnl mask */
- btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
- &wifi_central_chnl);
- if ((BTC_MEDIA_CONNECT == type) &&
- (wifi_central_chnl <= 14)) {
- /* h2c_parameter[0] = 0x1; */
- h2c_parameter[0] = 0x0;
- h2c_parameter[1] = wifi_central_chnl;
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- if (BTC_WIFI_BW_HT40 == wifi_bw)
- h2c_parameter[2] = 0x30;
- else
- h2c_parameter[2] = 0x20;
- }
-
- coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
- coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
- coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
-
- buf[0] = data_len;
- buf[1] = 0x5; /* OP_Code */
- buf[2] = 0x3; /* OP_Code_Length */
- buf[3] = h2c_parameter[0]; /* OP_Code_Content */
- buf[4] = h2c_parameter[1];
- buf[5] = h2c_parameter[2];
-
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_COEX,
- (void *)&buf[0]);
-}
-
-void ex_halbtc8812a1ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- boolean bt_hs_on = false;
- u32 wifi_link_status = 0;
- u32 num_of_wifi_link = 0;
- boolean bt_ctrl_agg_buf_size = false;
- u8 agg_buf_size = 5;
-
- if (btcoexist->manual_control ||
- btcoexist->stop_coex_dm ||
- coex_sta->bt_disabled)
- return;
-
- if (BTC_PACKET_DHCP == type ||
- BTC_PACKET_EAPOL == type ||
- BTC_PACKET_ARP == type) {
- if (BTC_PACKET_ARP == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], specific Packet ARP notify\n");
- BTC_TRACE(trace_buf);
-
- coex_dm->arp_cnt++;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ARP Packet Count = %d\n",
- coex_dm->arp_cnt);
- BTC_TRACE(trace_buf);
-
- if (coex_dm->arp_cnt >=
- 10) /* if APR PKT > 10 after connect, do not go to ActionWifiConnectedSpecificPacket(btcoexist) */
- coex_sta->wifi_is_high_pri_task = false;
- else
- coex_sta->wifi_is_high_pri_task = true;
- } else {
- coex_sta->wifi_is_high_pri_task = true;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], specific Packet DHCP or EAPOL notify\n");
- BTC_TRACE(trace_buf);
- }
- } else {
- coex_sta->wifi_is_high_pri_task = false;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], specific Packet [Type = %d] notify\n", type);
- BTC_TRACE(trace_buf);
- }
-
- coex_sta->specific_pkt_period_cnt = 0;
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
- num_of_wifi_link = wifi_link_status >> 16;
- if (num_of_wifi_link >= 2) {
- halbtc8812a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
- halbtc8812a1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
- bt_ctrl_agg_buf_size, agg_buf_size);
- halbtc8812a1ant_action_wifi_multi_port(btcoexist);
- return;
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- if (coex_sta->c2h_bt_inquiry_page) {
- halbtc8812a1ant_action_bt_inquiry(btcoexist);
- return;
- } else if (bt_hs_on) {
- halbtc8812a1ant_action_hs(btcoexist);
- return;
- }
-
- if (BTC_PACKET_DHCP == type ||
- BTC_PACKET_EAPOL == type ||
- ((BTC_PACKET_ARP == type) && (coex_sta->wifi_is_high_pri_task)))
- halbtc8812a1ant_action_wifi_connected_specific_packet(btcoexist);
-}
-
-void ex_halbtc8812a1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
- IN u8 *tmp_buf, IN u8 length)
-{
- u8 bt_info = 0;
- u8 i, rsp_source = 0;
- boolean wifi_connected = false;
- boolean bt_busy = false;
-
- coex_sta->c2h_bt_info_req_sent = false;
-
- rsp_source = tmp_buf[0] & 0xf;
- if (rsp_source >= BT_INFO_SRC_8812A_1ANT_MAX)
- rsp_source = BT_INFO_SRC_8812A_1ANT_WIFI_FW;
- coex_sta->bt_info_c2h_cnt[rsp_source]++;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source,
- length);
- BTC_TRACE(trace_buf);
- for (i = 0; i < length; i++) {
- coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
- if (i == 1)
- bt_info = tmp_buf[i];
- if (i == length - 1) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n",
- tmp_buf[i]);
- BTC_TRACE(trace_buf);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ",
- tmp_buf[i]);
- BTC_TRACE(trace_buf);
- }
- }
-
- if (BT_INFO_SRC_8812A_1ANT_WIFI_FW != rsp_source) {
- coex_sta->bt_retry_cnt = /* [3:0] */
- coex_sta->bt_info_c2h[rsp_source][2] & 0xf;
-
- if (coex_sta->bt_retry_cnt >= 1)
- coex_sta->pop_event_cnt++;
-
- if (coex_sta->bt_info_c2h[rsp_source][2] & 0x20)
- coex_sta->c2h_bt_page = true;
- else
- coex_sta->c2h_bt_page = false;
-
- coex_sta->bt_rssi =
- coex_sta->bt_info_c2h[rsp_source][3] * 2 - 90;
- /* coex_sta->bt_info_c2h[rsp_source][3]*2+10; */
-
- coex_sta->bt_info_ext =
- coex_sta->bt_info_c2h[rsp_source][4];
-
- coex_sta->bt_tx_rx_mask = (coex_sta->bt_info_c2h[rsp_source][2]
- & 0x40);
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TX_RX_MASK,
- &coex_sta->bt_tx_rx_mask);
- if (!coex_sta->bt_tx_rx_mask) {
- /* BT into is responded by BT FW and BT RF REG 0x3C != 0x15 => Need to switch BT TRx Mask */
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x15\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF,
- 0x3c, 0x15);
- }
-
- /* Here we need to resend some wifi info to BT */
- /* because bt is reset and loss of the info. */
- if (coex_sta->bt_info_ext & BIT(1)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- if (wifi_connected)
- ex_halbtc8812a1ant_media_status_notify(
- btcoexist, BTC_MEDIA_CONNECT);
- else
- ex_halbtc8812a1ant_media_status_notify(
- btcoexist, BTC_MEDIA_DISCONNECT);
- }
-
- if (coex_sta->bt_info_ext & BIT(3)) {
- if (!btcoexist->manual_control &&
- !btcoexist->stop_coex_dm) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n");
- BTC_TRACE(trace_buf);
- halbtc8812a1ant_ignore_wlan_act(btcoexist,
- FORCE_EXEC, false);
- }
- } else {
- /* BT already NOT ignore Wlan active, do nothing here. */
- }
-#if (BT_AUTO_REPORT_ONLY_8812A_1ANT == 0)
- if ((coex_sta->bt_info_ext & BIT(4))) {
- /* BT auto report already enabled, do nothing */
- } else
- halbtc8812a1ant_bt_auto_report(btcoexist, FORCE_EXEC,
- true);
-#endif
- }
-
- /* check BIT2 first ==> check if bt is under inquiry or page scan */
- if (bt_info & BT_INFO_8812A_1ANT_B_INQ_PAGE)
- coex_sta->c2h_bt_inquiry_page = true;
- else
- coex_sta->c2h_bt_inquiry_page = false;
-
- /* set link exist status */
- if (!(bt_info & BT_INFO_8812A_1ANT_B_CONNECTION)) {
- coex_sta->bt_link_exist = false;
- coex_sta->pan_exist = false;
- coex_sta->a2dp_exist = false;
- coex_sta->hid_exist = false;
- coex_sta->sco_exist = false;
- } else { /* connection exists */
- coex_sta->bt_link_exist = true;
- if (bt_info & BT_INFO_8812A_1ANT_B_FTP)
- coex_sta->pan_exist = true;
- else
- coex_sta->pan_exist = false;
- if (bt_info & BT_INFO_8812A_1ANT_B_A2DP)
- coex_sta->a2dp_exist = true;
- else
- coex_sta->a2dp_exist = false;
- if (bt_info & BT_INFO_8812A_1ANT_B_HID)
- coex_sta->hid_exist = true;
- else
- coex_sta->hid_exist = false;
- if (bt_info & BT_INFO_8812A_1ANT_B_SCO_ESCO)
- coex_sta->sco_exist = true;
- else
- coex_sta->sco_exist = false;
- }
-
- halbtc8812a1ant_update_bt_link_info(btcoexist);
-
- bt_info = bt_info &
- 0x1f; /* mask profile bit for connect-ilde identification ( for CSR case: A2DP idle --> 0x41) */
-
- if (!(bt_info & BT_INFO_8812A_1ANT_B_CONNECTION)) {
- coex_dm->bt_status = BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n");
- BTC_TRACE(trace_buf);
- } else if (bt_info ==
- BT_INFO_8812A_1ANT_B_CONNECTION) { /* connection exists but no busy */
- coex_dm->bt_status = BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n");
- BTC_TRACE(trace_buf);
- } else if ((bt_info & BT_INFO_8812A_1ANT_B_SCO_ESCO) ||
- (bt_info & BT_INFO_8812A_1ANT_B_SCO_BUSY)) {
- coex_dm->bt_status = BT_8812A_1ANT_BT_STATUS_SCO_BUSY;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n");
- BTC_TRACE(trace_buf);
- } else if (bt_info & BT_INFO_8812A_1ANT_B_ACL_BUSY) {
- if (BT_8812A_1ANT_BT_STATUS_ACL_BUSY != coex_dm->bt_status)
- coex_dm->auto_tdma_adjust = false;
- coex_dm->bt_status = BT_8812A_1ANT_BT_STATUS_ACL_BUSY;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n");
- BTC_TRACE(trace_buf);
- } else {
- coex_dm->bt_status = BT_8812A_1ANT_BT_STATUS_MAX;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n");
- BTC_TRACE(trace_buf);
- }
-
- if ((BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
- (BT_8812A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
- (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status))
- bt_busy = true;
- else
- bt_busy = false;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
-
- halbtc8812a1ant_run_coexist_mechanism(btcoexist);
-}
-
-void ex_halbtc8812a1ant_rf_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n");
- BTC_TRACE(trace_buf);
-
- if (BTC_RF_ON == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RF is turned ON!!\n");
- BTC_TRACE(trace_buf);
- btcoexist->stop_coex_dm = false;
- } else if (BTC_RF_OFF == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RF is turned OFF!!\n");
- BTC_TRACE(trace_buf);
-
- halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
- halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT,
- FORCE_EXEC, false, true);
-
- halbtc8812a1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
- btcoexist->stop_coex_dm = true;
- }
-}
-
-void ex_halbtc8812a1ant_halt_notify(IN struct btc_coexist *btcoexist)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n");
- BTC_TRACE(trace_buf);
-
- halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
- halbtc8812a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
- halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, FORCE_EXEC,
- false, true);
-
- halbtc8812a1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
-
- ex_halbtc8812a1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
-
- btcoexist->stop_coex_dm = true;
-}
-
-void ex_halbtc8812a1ant_pnp_notify(IN struct btc_coexist *btcoexist,
- IN u8 pnp_state)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n");
- BTC_TRACE(trace_buf);
-
- if (BTC_WIFI_PNP_SLEEP == pnp_state) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Pnp notify to SLEEP\n");
- BTC_TRACE(trace_buf);
-
- halbtc8812a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- halbtc8812a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT,
- FORCE_EXEC, false, true);
- halbtc8812a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
-
- /* Sinda 20150819, workaround for driver skip leave IPS/LPS to speed up sleep time. */
- /* Driver do not leave IPS/LPS when driver is going to sleep, so BTCoexistence think wifi is still under IPS/LPS */
- /* BT should clear UnderIPS/UnderLPS state to avoid mismatch state after wakeup. */
- coex_sta->under_ips = false;
- coex_sta->under_lps = false;
- btcoexist->stop_coex_dm = true;
- } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Pnp notify to WAKE UP\n");
- BTC_TRACE(trace_buf);
- btcoexist->stop_coex_dm = false;
- halbtc8812a1ant_init_hw_config(btcoexist, false, false);
- halbtc8812a1ant_init_coex_dm(btcoexist);
- halbtc8812a1ant_query_bt_info(btcoexist);
- }
-}
-
-void ex_halbtc8812a1ant_coex_dm_reset(IN struct btc_coexist *btcoexist)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], *****************Coex DM Reset*****************\n");
- BTC_TRACE(trace_buf);
-
- halbtc8812a1ant_init_hw_config(btcoexist, false, false);
- halbtc8812a1ant_init_coex_dm(btcoexist);
-}
-
-void ex_halbtc8812a1ant_periodical(IN struct btc_coexist *btcoexist)
-{
-#if (BT_AUTO_REPORT_ONLY_8812A_1ANT == 0)
- halbtc8812a1ant_query_bt_info(btcoexist);
- halbtc8812a1ant_monitor_bt_enable_disable(btcoexist);
-#else
- halbtc8812a1ant_monitor_bt_ctr(btcoexist);
- halbtc8812a1ant_monitor_wifi_ctr(btcoexist);
-
- if (halbtc8812a1ant_is_wifi_status_changed(btcoexist) ||
- coex_dm->auto_tdma_adjust)
- halbtc8812a1ant_run_coexist_mechanism(btcoexist);
-
- coex_sta->specific_pkt_period_cnt++;
-#endif
-}
-
-void ex_halbtc8812a1ant_dbg_control(IN struct btc_coexist *btcoexist,
- IN u8 op_code, IN u8 op_len, IN u8 *pdata)
-{
- switch (op_code) {
- case BTC_DBG_SET_COEX_NORMAL:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Set CoexMode to Normal\n");
- BTC_TRACE(trace_buf);
- btcoexist->manual_control = false;
- halbtc8812a1ant_init_coex_dm(btcoexist);
- break;
- case BTC_DBG_SET_COEX_WIFI_ONLY:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Set CoexMode to Wifi Only\n");
- BTC_TRACE(trace_buf);
- btcoexist->manual_control = true;
- halbtc8812a1ant_power_save_state(btcoexist,
- BTC_PS_WIFI_NATIVE, 0x0, 0x0);
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 9);
- break;
- case BTC_DBG_SET_COEX_BT_ONLY:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Set CoexMode to BT only\n");
- BTC_TRACE(trace_buf);
- btcoexist->manual_control = true;
- halbtc8812a1ant_power_save_state(btcoexist,
- BTC_PS_WIFI_NATIVE, 0x0, 0x0);
- halbtc8812a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 0);
- break;
- case BTC_DBG_SET_COEX_DEC_BT_PWR:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Set Dec BT power\n");
- BTC_TRACE(trace_buf);
- {
- u8 data_len = 4;
- u8 buf[6] = {0};
- u8 dec_bt_pwr = 0, pwr_level = 0;
- if (op_len == 2) {
- dec_bt_pwr = pdata[0];
- pwr_level = pdata[1];
-
- buf[0] = data_len;
- buf[1] = 0x3; /* OP_Code */
- buf[2] = 0x2; /* OP_Code_Length */
-
- buf[3] = dec_bt_pwr; /* OP_Code_Content */
- buf[4] = pwr_level;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Set Dec BT power=%d, pwr_level=%d\n",
- dec_bt_pwr, pwr_level);
- BTC_TRACE(trace_buf);
- btcoexist->btc_set(btcoexist,
- BTC_SET_ACT_CTRL_BT_COEX,
- (void *)&buf[0]);
- }
- }
- break;
-
- case BTC_DBG_SET_COEX_BT_AFH_MAP:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Set BT AFH Map\n");
- BTC_TRACE(trace_buf);
- {
- u8 data_len = 5;
- u8 buf[6] = {0};
- if (op_len == 3) {
- buf[0] = data_len;
- buf[1] = 0x5; /* OP_Code */
- buf[2] = 0x3; /* OP_Code_Length */
-
- buf[3] = pdata[0]; /* OP_Code_Content */
- buf[4] = pdata[1];
- buf[5] = pdata[2];
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Set BT AFH Map = %02x %02x %02x\n",
- pdata[0], pdata[1], pdata[2]);
- BTC_TRACE(trace_buf);
- btcoexist->btc_set(btcoexist,
- BTC_SET_ACT_CTRL_BT_COEX,
- (void *)&buf[0]);
- }
- }
- break;
-
- case BTC_DBG_SET_COEX_BT_IGNORE_WLAN_ACT:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Set BT Ignore Wlan Active\n");
- BTC_TRACE(trace_buf);
- {
- u8 data_len = 3;
- u8 buf[6] = {0};
- if (op_len == 1) {
- buf[0] = data_len;
- buf[1] = 0x1; /* OP_Code */
- buf[2] = 0x1; /* OP_Code_Length */
-
- buf[3] = pdata[0]; /* OP_Code_Content */
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Set BT Ignore Wlan Active = 0x%x\n",
- pdata[0]);
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_set(btcoexist,
- BTC_SET_ACT_CTRL_BT_COEX,
- (void *)&buf[0]);
- }
- }
- break;
- default:
- break;
- }
-}
-
-#endif
-
-#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */
\ No newline at end of file
diff --git a/hal/btc/HalBtc8812a1Ant.h b/hal/btc/HalBtc8812a1Ant.h
deleted file mode 100644
index e786d37..0000000
--- a/hal/btc/HalBtc8812a1Ant.h
+++ /dev/null
@@ -1,230 +0,0 @@
-
-#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
-
-#if (RTL8812A_SUPPORT == 1)
-
-/* *******************************************
- * The following is for 8812A 1ANT BT Co-exist definition
- * ******************************************* */
-#define BT_AUTO_REPORT_ONLY_8812A_1ANT 1
-
-#define BT_INFO_8812A_1ANT_B_FTP BIT(7)
-#define BT_INFO_8812A_1ANT_B_A2DP BIT(6)
-#define BT_INFO_8812A_1ANT_B_HID BIT(5)
-#define BT_INFO_8812A_1ANT_B_SCO_BUSY BIT(4)
-#define BT_INFO_8812A_1ANT_B_ACL_BUSY BIT(3)
-#define BT_INFO_8812A_1ANT_B_INQ_PAGE BIT(2)
-#define BT_INFO_8812A_1ANT_B_SCO_ESCO BIT(1)
-#define BT_INFO_8812A_1ANT_B_CONNECTION BIT(0)
-
-#define BT_INFO_8812A_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \
- (((_BT_INFO_EXT_&BIT(0))) ? true : false)
-
-#define BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT 2
-
-#define BT_8812A_1ANT_WIFI_NOISY_THRESH 30 /* max: 255 */
-
-enum bt_info_src_8812a_1ant {
- BT_INFO_SRC_8812A_1ANT_WIFI_FW = 0x0,
- BT_INFO_SRC_8812A_1ANT_BT_RSP = 0x1,
- BT_INFO_SRC_8812A_1ANT_BT_ACTIVE_SEND = 0x2,
- BT_INFO_SRC_8812A_1ANT_MAX
-};
-
-enum bt_8812a_1ant_bt_status {
- BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
- BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
- BT_8812A_1ANT_BT_STATUS_INQ_PAGE = 0x2,
- BT_8812A_1ANT_BT_STATUS_ACL_BUSY = 0x3,
- BT_8812A_1ANT_BT_STATUS_SCO_BUSY = 0x4,
- BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
- BT_8812A_1ANT_BT_STATUS_MAX
-};
-
-enum bt_8812a_1ant_wifi_status {
- BT_8812A_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0,
- BT_8812A_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1,
- BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2,
- BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT = 0x3,
- BT_8812A_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4,
- BT_8812A_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5,
- BT_8812A_1ANT_WIFI_STATUS_MAX
-};
-
-enum bt_8812a_1ant_coex_algo {
- BT_8812A_1ANT_COEX_ALGO_UNDEFINED = 0x0,
- BT_8812A_1ANT_COEX_ALGO_SCO = 0x1,
- BT_8812A_1ANT_COEX_ALGO_HID = 0x2,
- BT_8812A_1ANT_COEX_ALGO_A2DP = 0x3,
- BT_8812A_1ANT_COEX_ALGO_A2DP_PANHS = 0x4,
- BT_8812A_1ANT_COEX_ALGO_PANEDR = 0x5,
- BT_8812A_1ANT_COEX_ALGO_PANHS = 0x6,
- BT_8812A_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
- BT_8812A_1ANT_COEX_ALGO_PANEDR_HID = 0x8,
- BT_8812A_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
- BT_8812A_1ANT_COEX_ALGO_HID_A2DP = 0xa,
- BT_8812A_1ANT_COEX_ALGO_MAX = 0xb,
-};
-
-struct coex_dm_8812a_1ant {
- /* hw setting */
- u8 pre_ant_pos_type;
- u8 cur_ant_pos_type;
- /* fw mechanism */
- boolean cur_ignore_wlan_act;
- boolean pre_ignore_wlan_act;
- u8 pre_ps_tdma;
- u8 cur_ps_tdma;
- u8 ps_tdma_para[5];
- u8 ps_tdma_du_adj_type;
- boolean auto_tdma_adjust;
- boolean pre_ps_tdma_on;
- boolean cur_ps_tdma_on;
- boolean pre_bt_auto_report;
- boolean cur_bt_auto_report;
- u8 pre_lps;
- u8 cur_lps;
- u8 pre_rpwm;
- u8 cur_rpwm;
-
- /* sw mechanism */
- boolean pre_low_penalty_ra;
- boolean cur_low_penalty_ra;
- u32 pre_val0x6c0;
- u32 cur_val0x6c0;
- u32 pre_val0x6c4;
- u32 cur_val0x6c4;
- u32 pre_val0x6c8;
- u32 cur_val0x6c8;
- u8 pre_val0x6cc;
- u8 cur_val0x6cc;
- boolean limited_dig;
-
- u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */
- u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */
- u16 backup_retry_limit;
- u8 backup_ampdu_max_time;
-
- /* algorithm related */
- u8 pre_algorithm;
- u8 cur_algorithm;
- u8 bt_status;
- u8 wifi_chnl_info[3];
-
- u32 pre_ra_mask;
- u32 cur_ra_mask;
- u8 pre_arfr_type;
- u8 cur_arfr_type;
- u8 pre_retry_limit_type;
- u8 cur_retry_limit_type;
- u8 pre_ampdu_time_type;
- u8 cur_ampdu_time_type;
- u32 arp_cnt;
-
- u8 error_condition;
-};
-
-struct coex_sta_8812a_1ant {
- boolean bt_disabled;
- boolean bt_link_exist;
- boolean sco_exist;
- boolean a2dp_exist;
- boolean hid_exist;
- boolean pan_exist;
-
- boolean under_lps;
- boolean under_ips;
- u32 specific_pkt_period_cnt;
- u32 high_priority_tx;
- u32 high_priority_rx;
- u32 low_priority_tx;
- u32 low_priority_rx;
- s8 bt_rssi;
- boolean bt_tx_rx_mask;
- u8 pre_bt_rssi_state;
- u8 pre_wifi_rssi_state[4];
- boolean c2h_bt_info_req_sent;
- u8 bt_info_c2h[BT_INFO_SRC_8812A_1ANT_MAX][10];
- u32 bt_info_c2h_cnt[BT_INFO_SRC_8812A_1ANT_MAX];
- u32 bt_info_query_cnt;
- boolean c2h_bt_inquiry_page;
- boolean c2h_bt_page; /* Add for win8.1 page out issue */
- boolean wifi_is_high_pri_task; /* Add for win8.1 page out issue */
- u8 bt_retry_cnt;
- u8 bt_info_ext;
- u32 pop_event_cnt;
- u8 scan_ap_num;
-
- u32 crc_ok_cck;
- u32 crc_ok_11g;
- u32 crc_ok_11n;
- u32 crc_ok_11n_agg;
-
- u32 crc_err_cck;
- u32 crc_err_11g;
- u32 crc_err_11n;
- u32 crc_err_11n_agg;
-
- boolean cck_lock;
- boolean pre_ccklock;
- u8 coex_table_type;
-
- boolean force_lps_on;
-};
-
-/* *******************************************
- * The following is interface which will notify coex module.
- * ******************************************* */
-void ex_halbtc8812a1ant_power_on_setting(IN struct btc_coexist *btcoexist);
-void ex_halbtc8812a1ant_pre_load_firmware(IN struct btc_coexist *btcoexist);
-void ex_halbtc8812a1ant_init_hw_config(IN struct btc_coexist *btcoexist,
- IN boolean wifi_only);
-void ex_halbtc8812a1ant_init_coex_dm(IN struct btc_coexist *btcoexist);
-void ex_halbtc8812a1ant_ips_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8812a1ant_lps_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8812a1ant_scan_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8812a1ant_connect_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8812a1ant_media_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8812a1ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8812a1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
- IN u8 *tmp_buf, IN u8 length);
-void ex_halbtc8812a1ant_rf_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8812a1ant_halt_notify(IN struct btc_coexist *btcoexist);
-void ex_halbtc8812a1ant_pnp_notify(IN struct btc_coexist *btcoexist,
- IN u8 pnp_state);
-void ex_halbtc8812a1ant_coex_dm_reset(IN struct btc_coexist *btcoexist);
-void ex_halbtc8812a1ant_periodical(IN struct btc_coexist *btcoexist);
-void ex_halbtc8812a1ant_dbg_control(IN struct btc_coexist *btcoexist,
- IN u8 op_code, IN u8 op_len, IN u8 *pdata);
-void ex_halbtc8812a1ant_display_coex_info(IN struct btc_coexist *btcoexist);
-
-#else
-#define ex_halbtc8812a1ant_power_on_setting(btcoexist)
-#define ex_halbtc8812a1ant_pre_load_firmware(btcoexist)
-#define ex_halbtc8812a1ant_init_hw_config(btcoexist, wifi_only)
-#define ex_halbtc8812a1ant_init_coex_dm(btcoexist)
-#define ex_halbtc8812a1ant_ips_notify(btcoexist, type)
-#define ex_halbtc8812a1ant_lps_notify(btcoexist, type)
-#define ex_halbtc8812a1ant_scan_notify(btcoexist, type)
-#define ex_halbtc8812a1ant_connect_notify(btcoexist, type)
-#define ex_halbtc8812a1ant_media_status_notify(btcoexist, type)
-#define ex_halbtc8812a1ant_specific_packet_notify(btcoexist, type)
-#define ex_halbtc8812a1ant_bt_info_notify(btcoexist, tmp_buf, length)
-#define ex_halbtc8812a1ant_rf_status_notify(btcoexist, type)
-#define ex_halbtc8812a1ant_halt_notify(btcoexist)
-#define ex_halbtc8812a1ant_pnp_notify(btcoexist, pnp_state)
-#define ex_halbtc8812a1ant_coex_dm_reset(btcoexist)
-#define ex_halbtc8812a1ant_periodical(btcoexist)
-#define ex_halbtc8812a1ant_dbg_control(btcoexist, op_code, op_len, pdata)
-#define ex_halbtc8812a1ant_display_coex_info(btcoexist)
-
-#endif
-
-#endif
diff --git a/hal/btc/HalBtc8812a2Ant.c b/hal/btc/HalBtc8812a2Ant.c
deleted file mode 100644
index cd8a547..0000000
--- a/hal/btc/HalBtc8812a2Ant.c
+++ /dev/null
@@ -1,4782 +0,0 @@
-/* ************************************************************
- * Description:
- *
- * This file is for RTL8812A Co-exist mechanism
- *
- * History
- * 2012/08/22 Cosa first check in.
- * 2012/11/14 Cosa Revise for 8812A 2Ant out sourcing.
- *
- * ************************************************************ */
-
-/* ************************************************************
- * include files
- * ************************************************************ */
-#include "Mp_Precomp.h"
-
-#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
-
-#if (RTL8812A_SUPPORT == 1)
-/* ************************************************************
- * Global variables, these are static variables
- * ************************************************************ */
-static u8 *trace_buf = &gl_btc_trace_buf[0];
-static struct coex_dm_8812a_2ant glcoex_dm_8812a_2ant;
-static struct coex_dm_8812a_2ant *coex_dm = &glcoex_dm_8812a_2ant;
-static struct coex_sta_8812a_2ant glcoex_sta_8812a_2ant;
-static struct coex_sta_8812a_2ant *coex_sta = &glcoex_sta_8812a_2ant;
-
-const char *const glbt_info_src_8812a_2ant[] = {
- "BT Info[wifi fw]",
- "BT Info[bt rsp]",
- "BT Info[bt auto report]",
-};
-
-u32 glcoex_ver_date_8812a_2ant = 20150724;
-u32 glcoex_ver_8812a_2ant = 0x37;
-
-/* ************************************************************
- * local function proto type if needed
- * ************************************************************
- * ************************************************************
- * local function start with halbtc8812a2ant_
- * ************************************************************ */
-u8 halbtc8812a2ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1)
-{
- s32 bt_rssi = 0;
- u8 bt_rssi_state = coex_sta->pre_bt_rssi_state;
-
- bt_rssi = coex_sta->bt_rssi;
-
- if (level_num == 2) {
- if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
- (coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (bt_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT))
- bt_rssi_state = BTC_RSSI_STATE_HIGH;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else {
- if (bt_rssi < rssi_thresh)
- bt_rssi_state = BTC_RSSI_STATE_LOW;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- } else if (level_num == 3) {
- if (rssi_thresh > rssi_thresh1) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Rssi thresh error!!\n");
- BTC_TRACE(trace_buf);
- return coex_sta->pre_bt_rssi_state;
- }
-
- if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
- (coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (bt_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT))
- bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else if ((coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_MEDIUM) ||
- (coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_STAY_MEDIUM)) {
- if (bt_rssi >= (rssi_thresh1 +
- BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT))
- bt_rssi_state = BTC_RSSI_STATE_HIGH;
- else if (bt_rssi < rssi_thresh)
- bt_rssi_state = BTC_RSSI_STATE_LOW;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
- } else {
- if (bt_rssi < rssi_thresh1)
- bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- }
-
- coex_sta->pre_bt_rssi_state = bt_rssi_state;
-
- return bt_rssi_state;
-}
-
-u8 halbtc8812a2ant_wifi_rssi_state(IN struct btc_coexist *btcoexist,
- IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1)
-{
- s32 wifi_rssi = 0;
- u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index];
-
- btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
-
- if (level_num == 2) {
- if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
- ||
- (coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (wifi_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT))
- wifi_rssi_state = BTC_RSSI_STATE_HIGH;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else {
- if (wifi_rssi < rssi_thresh)
- wifi_rssi_state = BTC_RSSI_STATE_LOW;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- } else if (level_num == 3) {
- if (rssi_thresh > rssi_thresh1) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], wifi RSSI thresh error!!\n");
- BTC_TRACE(trace_buf);
- return coex_sta->pre_wifi_rssi_state[index];
- }
-
- if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
- ||
- (coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (wifi_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT))
- wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else if ((coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_MEDIUM) ||
- (coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_STAY_MEDIUM)) {
- if (wifi_rssi >= (rssi_thresh1 +
- BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT))
- wifi_rssi_state = BTC_RSSI_STATE_HIGH;
- else if (wifi_rssi < rssi_thresh)
- wifi_rssi_state = BTC_RSSI_STATE_LOW;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
- } else {
- if (wifi_rssi < rssi_thresh1)
- wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- }
-
- coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state;
-
- return wifi_rssi_state;
-}
-
-void halbtc8812a2ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist)
-{
- struct btc_stack_info *stack_info = &btcoexist->stack_info;
- static u32 bt_disable_cnt = 0;
- boolean bt_active = true, bt_disabled = false;
-
- /* This function check if bt is disabled */
-
- /* only 8812a need to consider if core stack is installed. */
- if (!stack_info->hci_version)
- bt_active = false;
-
- if (coex_sta->high_priority_tx == 0 &&
- coex_sta->high_priority_rx == 0 &&
- coex_sta->low_priority_tx == 0 &&
- coex_sta->low_priority_rx == 0)
- bt_active = false;
- if (coex_sta->high_priority_tx == 0xffff &&
- coex_sta->high_priority_rx == 0xffff &&
- coex_sta->low_priority_tx == 0xffff &&
- coex_sta->low_priority_rx == 0xffff)
- bt_active = false;
- if (bt_active) {
- bt_disable_cnt = 0;
- bt_disabled = false;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
- &bt_disabled);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is enabled !!\n");
- BTC_TRACE(trace_buf);
- } else {
- bt_disable_cnt++;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], bt is detected as disabled %d times!!\n",
- bt_disable_cnt);
- BTC_TRACE(trace_buf);
- if (bt_disable_cnt >= 2) {
- bt_disabled = true;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
- &bt_disabled);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is disabled !!\n");
- BTC_TRACE(trace_buf);
- }
- }
- if (coex_sta->bt_disabled != bt_disabled) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is from %s to %s!!\n",
- (coex_sta->bt_disabled ? "disabled" : "enabled"),
- (bt_disabled ? "disabled" : "enabled"));
- BTC_TRACE(trace_buf);
- coex_sta->bt_disabled = bt_disabled;
- if (!bt_disabled) {
- } else {
- }
- }
-}
-
-u32 halbtc8812a2ant_decide_ra_mask(IN struct btc_coexist *btcoexist,
- IN u32 ra_mask_type)
-{
- u32 dis_ra_mask = 0x0;
-
- switch (ra_mask_type) {
- case 0: /* normal mode */
- dis_ra_mask = 0x0;
- break;
- case 1: /* disable cck 1/2 */
- dis_ra_mask = 0x00000003;
- break;
- case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */
- dis_ra_mask = 0x0001f1f7;
- break;
- default:
- break;
- }
-
- return dis_ra_mask;
-}
-
-void halbtc8812a2ant_update_ra_mask(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u32 dis_rate_mask)
-{
- coex_dm->cur_ra_mask = dis_rate_mask;
-
- if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask))
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK,
- &coex_dm->cur_ra_mask);
- coex_dm->pre_ra_mask = coex_dm->cur_ra_mask;
-}
-
-void halbtc8812a2ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- boolean wifi_under_b_mode = false;
-
- coex_dm->cur_arfr_type = type;
-
- if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) {
- switch (coex_dm->cur_arfr_type) {
- case 0: /* normal mode */
- btcoexist->btc_write_4byte(btcoexist, 0x430,
- coex_dm->backup_arfr_cnt1);
- btcoexist->btc_write_4byte(btcoexist, 0x434,
- coex_dm->backup_arfr_cnt2);
- break;
- case 1:
- btcoexist->btc_get(btcoexist,
- BTC_GET_BL_WIFI_UNDER_B_MODE,
- &wifi_under_b_mode);
- if (wifi_under_b_mode) {
- btcoexist->btc_write_4byte(btcoexist,
- 0x430, 0x0);
- btcoexist->btc_write_4byte(btcoexist,
- 0x434, 0x01010101);
- } else {
- btcoexist->btc_write_4byte(btcoexist,
- 0x430, 0x0);
- btcoexist->btc_write_4byte(btcoexist,
- 0x434, 0x04030201);
- }
- break;
- default:
- break;
- }
- }
-
- coex_dm->pre_arfr_type = coex_dm->cur_arfr_type;
-}
-
-void halbtc8812a2ant_retry_limit(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- coex_dm->cur_retry_limit_type = type;
-
- if (force_exec ||
- (coex_dm->pre_retry_limit_type !=
- coex_dm->cur_retry_limit_type)) {
- switch (coex_dm->cur_retry_limit_type) {
- case 0: /* normal mode */
- btcoexist->btc_write_2byte(btcoexist, 0x42a,
- coex_dm->backup_retry_limit);
- break;
- case 1: /* retry limit=8 */
- btcoexist->btc_write_2byte(btcoexist, 0x42a,
- 0x0808);
- break;
- default:
- break;
- }
- }
-
- coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type;
-}
-
-void halbtc8812a2ant_ampdu_max_time(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- coex_dm->cur_ampdu_time_type = type;
-
- if (force_exec ||
- (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) {
- switch (coex_dm->cur_ampdu_time_type) {
- case 0: /* normal mode */
- btcoexist->btc_write_1byte(btcoexist, 0x456,
- coex_dm->backup_ampdu_max_time);
- break;
- case 1: /* AMPDU timw = 0x38 * 32us */
- btcoexist->btc_write_1byte(btcoexist, 0x456,
- 0x38);
- break;
- default:
- break;
- }
- }
-
- coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type;
-}
-
-void halbtc8812a2ant_limited_tx(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type,
- IN u8 retry_limit_type, IN u8 ampdu_time_type)
-{
- u32 dis_ra_mask = 0x0;
-
- coex_dm->cur_ra_mask_type = ra_mask_type;
- dis_ra_mask = halbtc8812a2ant_decide_ra_mask(btcoexist, ra_mask_type);
- halbtc8812a2ant_update_ra_mask(btcoexist, force_exec, dis_ra_mask);
-
- halbtc8812a2ant_auto_rate_fallback_retry(btcoexist, force_exec,
- arfr_type);
- halbtc8812a2ant_retry_limit(btcoexist, force_exec, retry_limit_type);
- halbtc8812a2ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type);
-}
-
-void halbtc8812a2ant_limited_rx(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean rej_ap_agg_pkt,
- IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size)
-{
- boolean reject_rx_agg = rej_ap_agg_pkt;
- boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size;
- u8 rx_agg_size = agg_buf_size;
-
- /* ============================================ */
- /* Rx Aggregation related setting */
- /* ============================================ */
- btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT,
- &reject_rx_agg);
- /* decide BT control aggregation buf size or not */
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE,
- &bt_ctrl_rx_agg_size);
- /* aggregation buf size, only work when BT control Rx aggregation size. */
- btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size);
- /* real update aggregation setting */
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
-
-
-}
-
-void halbtc8812a2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist)
-{
- u32 reg_hp_txrx, reg_lp_txrx, u32tmp;
- u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
-
- reg_hp_txrx = 0x770;
- reg_lp_txrx = 0x774;
-
- u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
- reg_hp_tx = u32tmp & MASKLWORD;
- reg_hp_rx = (u32tmp & MASKHWORD) >> 16;
-
- u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
- reg_lp_tx = u32tmp & MASKLWORD;
- reg_lp_rx = (u32tmp & MASKHWORD) >> 16;
-
- coex_sta->high_priority_tx = reg_hp_tx;
- coex_sta->high_priority_rx = reg_hp_rx;
- coex_sta->low_priority_tx = reg_lp_tx;
- coex_sta->low_priority_rx = reg_lp_rx;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], High Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n",
- reg_hp_txrx, reg_hp_tx, reg_hp_tx, reg_hp_rx, reg_hp_rx);
- BTC_TRACE(trace_buf);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Low Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n",
- reg_lp_txrx, reg_lp_tx, reg_lp_tx, reg_lp_rx, reg_lp_rx);
- BTC_TRACE(trace_buf);
-
- /* reset counter */
- btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
-}
-
-void halbtc8812a2ant_query_bt_info(IN struct btc_coexist *btcoexist)
-{
- u8 data_len = 3;
- u8 buf[5] = {0};
-
- if (!coex_sta->bt_disabled) {
- if (!coex_sta->bt_info_query_cnt ||
- (coex_sta->bt_info_c2h_cnt[BT_INFO_SRC_8812A_2ANT_BT_RSP]
- - coex_sta->bt_info_query_cnt) > 2) {
- buf[0] = data_len;
- buf[1] = 0x1; /* polling enable, 1=enable, 0=disable */
- buf[2] = 0x2; /* polling time in seconds */
- buf[3] = 0x1; /* auto report enable, 1=enable, 0=disable */
-
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_INFO,
- (void *)&buf[0]);
- }
- }
- coex_sta->bt_info_query_cnt++;
-}
-
-boolean halbtc8812a2ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist)
-{
- static boolean pre_wifi_busy = false, pre_under_4way = false,
- pre_bt_hs_on = false;
- boolean wifi_busy = false, under_4way = false, bt_hs_on = false;
- boolean wifi_connected = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
- &under_4way);
-
- if (wifi_connected) {
- if (wifi_busy != pre_wifi_busy) {
- pre_wifi_busy = wifi_busy;
- return true;
- }
- if (under_4way != pre_under_4way) {
- pre_under_4way = under_4way;
- return true;
- }
- if (bt_hs_on != pre_bt_hs_on) {
- pre_bt_hs_on = bt_hs_on;
- return true;
- }
- }
-
- return false;
-}
-
-void halbtc8812a2ant_update_bt_link_info(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean bt_hs_on = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
-
- bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
- bt_link_info->sco_exist = coex_sta->sco_exist;
- bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
- bt_link_info->pan_exist = coex_sta->pan_exist;
- bt_link_info->hid_exist = coex_sta->hid_exist;
- bt_link_info->acl_busy = coex_sta->acl_busy;
-
- /* work around for HS mode. */
- if (bt_hs_on) {
- bt_link_info->pan_exist = true;
- bt_link_info->bt_link_exist = true;
- }
-
- /* check if Sco only */
- if (bt_link_info->sco_exist &&
- !bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist &&
- !bt_link_info->hid_exist)
- bt_link_info->sco_only = true;
- else
- bt_link_info->sco_only = false;
-
- /* check if A2dp only */
- if (!bt_link_info->sco_exist &&
- bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist &&
- !bt_link_info->hid_exist)
- bt_link_info->a2dp_only = true;
- else
- bt_link_info->a2dp_only = false;
-
- /* check if Pan only */
- if (!bt_link_info->sco_exist &&
- !bt_link_info->a2dp_exist &&
- bt_link_info->pan_exist &&
- !bt_link_info->hid_exist)
- bt_link_info->pan_only = true;
- else
- bt_link_info->pan_only = false;
-
- /* check if Hid only */
- if (!bt_link_info->sco_exist &&
- !bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist &&
- bt_link_info->hid_exist)
- bt_link_info->hid_only = true;
- else
- bt_link_info->hid_only = false;
-}
-
-u8 halbtc8812a2ant_action_algorithm(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- struct btc_stack_info *stack_info = &btcoexist->stack_info;
- boolean bt_hs_on = false;
- u8 algorithm = BT_8812A_2ANT_COEX_ALGO_UNDEFINED;
- u8 num_of_diff_profile = 0;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
-
- if (!bt_link_info->bt_link_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], No BT link exists!!!\n");
- BTC_TRACE(trace_buf);
- return algorithm;
- }
-
- if (bt_link_info->sco_exist)
- num_of_diff_profile++;
- if (bt_link_info->hid_exist)
- num_of_diff_profile++;
- if (bt_link_info->pan_exist)
- num_of_diff_profile++;
- if (bt_link_info->a2dp_exist)
- num_of_diff_profile++;
-
- if (num_of_diff_profile == 0) {
- if (bt_link_info->acl_busy) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ACL Busy only\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8812A_2ANT_COEX_ALGO_PANEDR;
- }
- } else if (num_of_diff_profile == 1) {
- if (bt_link_info->sco_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO only\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8812A_2ANT_COEX_ALGO_SCO;
- } else {
- if (bt_link_info->hid_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], HID only\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8812A_2ANT_COEX_ALGO_HID;
- } else if (bt_link_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], A2DP only\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8812A_2ANT_COEX_ALGO_A2DP;
- } else if (bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], PAN(HS) only\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8812A_2ANT_COEX_ALGO_PANHS;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], PAN(EDR) only\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8812A_2ANT_COEX_ALGO_PANEDR;
- }
- }
- }
- } else if (num_of_diff_profile == 2) {
- if (bt_link_info->sco_exist) {
- if (bt_link_info->hid_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + HID\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8812A_2ANT_COEX_ALGO_SCO_HID;
- } else if (bt_link_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + A2DP ==> SCO\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8812A_2ANT_COEX_ALGO_PANEDR_HID;
- } else if (bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8812A_2ANT_COEX_ALGO_SCO;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8812A_2ANT_COEX_ALGO_SCO;
- }
- }
- } else {
- if (bt_link_info->hid_exist &&
- bt_link_info->a2dp_exist) {
- if (stack_info->num_of_hid >= 2) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], HID*2 + A2DP\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], HID + A2DP\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8812A_2ANT_COEX_ALGO_HID_A2DP;
- }
- } else if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], HID + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8812A_2ANT_COEX_ALGO_HID;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], HID + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8812A_2ANT_COEX_ALGO_PANEDR_HID;
- }
- } else if (bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8812A_2ANT_COEX_ALGO_A2DP_PANHS;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], A2DP + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8812A_2ANT_COEX_ALGO_PANEDR_A2DP;
- }
- }
- }
- } else if (num_of_diff_profile == 3) {
- if (bt_link_info->sco_exist) {
- if (bt_link_info->hid_exist &&
- bt_link_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + HID + A2DP ==> HID\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8812A_2ANT_COEX_ALGO_PANEDR_HID;
- } else if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + HID + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8812A_2ANT_COEX_ALGO_SCO_HID;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + HID + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8812A_2ANT_COEX_ALGO_SCO_HID;
- }
- } else if (bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8812A_2ANT_COEX_ALGO_SCO;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8812A_2ANT_COEX_ALGO_PANEDR_HID;
- }
- }
- } else {
- if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], HID + A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANHS;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], HID + A2DP + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
- }
- }
- }
- } else if (num_of_diff_profile >= 3) {
- if (bt_link_info->sco_exist) {
- if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8812A_2ANT_COEX_ALGO_PANEDR_HID;
- }
- }
- }
- }
-
- return algorithm;
-}
-
-void halbtc8812a2ant_set_fw_dac_swing_level(IN struct btc_coexist *btcoexist,
- IN u8 dac_swing_lvl)
-{
- u8 h2c_parameter[1] = {0};
-
- /* There are several type of dacswing */
- /* 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */
- h2c_parameter[0] = dac_swing_lvl;
-
- btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter);
-}
-
-void halbtc8812a2ant_set_fw_dec_bt_pwr(IN struct btc_coexist *btcoexist,
- IN u8 dec_bt_pwr_lvl)
-{
- u8 data_len = 4;
- u8 buf[6] = {0};
-
- buf[0] = data_len;
- buf[1] = 0x3; /* OP_Code */
- buf[2] = 0x2; /* OP_Code_Length */
- if (dec_bt_pwr_lvl)
- buf[3] = 0x1; /* OP_Code_Content */
- else
- buf[3] = 0x0;
- buf[4] = dec_bt_pwr_lvl;/* pwr_level */
-
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_COEX,
- (void *)&buf[0]);
-}
-
-void halbtc8812a2ant_dec_bt_pwr(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 dec_bt_pwr_lvl)
-{
- coex_dm->cur_bt_dec_pwr_lvl = dec_bt_pwr_lvl;
-
- if (!force_exec) {
- if (coex_dm->pre_bt_dec_pwr_lvl == coex_dm->cur_bt_dec_pwr_lvl)
- return;
- }
- halbtc8812a2ant_set_fw_dec_bt_pwr(btcoexist,
- coex_dm->cur_bt_dec_pwr_lvl);
-
- coex_dm->pre_bt_dec_pwr_lvl = coex_dm->cur_bt_dec_pwr_lvl;
-}
-
-void halbtc8812a2ant_fw_dac_swing_lvl(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 fw_dac_swing_lvl)
-{
- coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl;
-
- if (!force_exec) {
- if (coex_dm->pre_fw_dac_swing_lvl ==
- coex_dm->cur_fw_dac_swing_lvl)
- return;
- }
-
- halbtc8812a2ant_set_fw_dac_swing_level(btcoexist,
- coex_dm->cur_fw_dac_swing_lvl);
-
- coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl;
-}
-
-void halbtc8812a2ant_set_sw_rf_rx_lpf_corner(IN struct btc_coexist *btcoexist,
- IN boolean rx_rf_shrink_on)
-{
- if (rx_rf_shrink_on) {
- /* Shrink RF Rx LPF corner */
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Shrink RF Rx LPF corner!!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, 0xfffff,
- 0xffffc);
- } else {
- /* Resume RF Rx LPF corner */
- /* After initialized, we can use coex_dm->bt_rf_0x1e_backup */
- if (btcoexist->initilized) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Resume RF Rx LPF corner!!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e,
- 0xfffff, coex_dm->bt_rf_0x1e_backup);
- }
- }
-}
-
-void halbtc8812a2ant_rf_shrink(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean rx_rf_shrink_on)
-{
- coex_dm->cur_rf_rx_lpf_shrink = rx_rf_shrink_on;
-
- if (!force_exec) {
- if (coex_dm->pre_rf_rx_lpf_shrink ==
- coex_dm->cur_rf_rx_lpf_shrink)
- return;
- }
- halbtc8812a2ant_set_sw_rf_rx_lpf_corner(btcoexist,
- coex_dm->cur_rf_rx_lpf_shrink);
-
- coex_dm->pre_rf_rx_lpf_shrink = coex_dm->cur_rf_rx_lpf_shrink;
-}
-
-void halbtc8812a2ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist
- *btcoexist, IN boolean low_penalty_ra)
-{
- u8 tmp_u1;
-
- tmp_u1 = btcoexist->btc_read_1byte(btcoexist, 0x4fd);
- tmp_u1 |= BIT(0);
- if (low_penalty_ra) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Tx rate adaptive, set low penalty!!\n");
- BTC_TRACE(trace_buf);
- tmp_u1 &= ~BIT(2);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Tx rate adaptive, set normal!!\n");
- BTC_TRACE(trace_buf);
- tmp_u1 |= BIT(2);
- }
-
- btcoexist->btc_write_1byte(btcoexist, 0x4fd, tmp_u1);
-}
-
-void halbtc8812a2ant_low_penalty_ra(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean low_penalty_ra)
-{
- return;
- coex_dm->cur_low_penalty_ra = low_penalty_ra;
-
- if (!force_exec) {
- if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra)
- return;
- }
- halbtc8812a2ant_set_sw_penalty_tx_rate_adaptive(btcoexist,
- coex_dm->cur_low_penalty_ra);
-
- coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra;
-}
-
-void halbtc8812a2ant_set_dac_swing_reg(IN struct btc_coexist *btcoexist,
- IN u32 level)
-{
- u8 val = (u8)level;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Write SwDacSwing = 0x%x\n", level);
- BTC_TRACE(trace_buf);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc5b, 0x3e, val);
-}
-
-void halbtc8812a2ant_set_sw_full_time_dac_swing(IN struct btc_coexist
- *btcoexist, IN boolean sw_dac_swing_on, IN u32 sw_dac_swing_lvl)
-{
- if (sw_dac_swing_on)
- halbtc8812a2ant_set_dac_swing_reg(btcoexist, sw_dac_swing_lvl);
- else
- halbtc8812a2ant_set_dac_swing_reg(btcoexist, 0x18);
-}
-
-
-void halbtc8812a2ant_dac_swing(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean dac_swing_on, IN u32 dac_swing_lvl)
-{
- coex_dm->cur_dac_swing_on = dac_swing_on;
- coex_dm->cur_dac_swing_lvl = dac_swing_lvl;
-
- if (!force_exec) {
- if ((coex_dm->pre_dac_swing_on == coex_dm->cur_dac_swing_on) &&
- (coex_dm->pre_dac_swing_lvl ==
- coex_dm->cur_dac_swing_lvl))
- return;
- }
- delay_ms(30);
- halbtc8812a2ant_set_sw_full_time_dac_swing(btcoexist, dac_swing_on,
- dac_swing_lvl);
-
- coex_dm->pre_dac_swing_on = coex_dm->cur_dac_swing_on;
- coex_dm->pre_dac_swing_lvl = coex_dm->cur_dac_swing_lvl;
-}
-
-void halbtc8812a2ant_set_adc_back_off(IN struct btc_coexist *btcoexist,
- IN boolean adc_back_off)
-{
- if (adc_back_off) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BB BackOff Level On!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x8db, 0x60, 0x3);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BB BackOff Level Off!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x8db, 0x60, 0x1);
- }
-}
-
-void halbtc8812a2ant_adc_back_off(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean adc_back_off)
-{
- coex_dm->cur_adc_back_off = adc_back_off;
-
- if (!force_exec) {
- if (coex_dm->pre_adc_back_off == coex_dm->cur_adc_back_off)
- return;
- }
- halbtc8812a2ant_set_adc_back_off(btcoexist, coex_dm->cur_adc_back_off);
-
- coex_dm->pre_adc_back_off = coex_dm->cur_adc_back_off;
-}
-
-void halbtc8812a2ant_set_agc_table(IN struct btc_coexist *btcoexist,
- IN boolean agc_table_en)
-{
- u8 rssi_adjust_val = 0;
-
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xef, 0xfffff, 0x02000);
- if (agc_table_en) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Agc Table On!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff,
- 0x28F4B);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff,
- 0x10AB2);
- rssi_adjust_val = 8;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Agc Table Off!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff,
- 0x2884B);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff,
- 0x104B2);
- }
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xef, 0xfffff, 0x0);
-
- /* set rssi_adjust_val for wifi module. */
- btcoexist->btc_set(btcoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON,
- &rssi_adjust_val);
-}
-
-void halbtc8812a2ant_agc_table(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean agc_table_en)
-{
- coex_dm->cur_agc_table_en = agc_table_en;
-
- if (!force_exec) {
- if (coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en)
- return;
- }
- halbtc8812a2ant_set_agc_table(btcoexist, agc_table_en);
-
- coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en;
-}
-
-void halbtc8812a2ant_set_coex_table(IN struct btc_coexist *btcoexist,
- IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc)
-{
- btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
-
- btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
-
- btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
-
- btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
-}
-
-void halbtc8812a2ant_coex_table(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4,
- IN u32 val0x6c8, IN u8 val0x6cc)
-{
- coex_dm->cur_val0x6c0 = val0x6c0;
- coex_dm->cur_val0x6c4 = val0x6c4;
- coex_dm->cur_val0x6c8 = val0x6c8;
- coex_dm->cur_val0x6cc = val0x6cc;
-
- if (!force_exec) {
- if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) &&
- (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) &&
- (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) &&
- (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc))
- return;
- }
- halbtc8812a2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8,
- val0x6cc);
-
- coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0;
- coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4;
- coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8;
- coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc;
-}
-
-void halbtc8812a2ant_coex_table_with_type(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- switch (type) {
- case 0:
- halbtc8812a2ant_coex_table(btcoexist, force_exec,
- 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3);
- break;
- case 1:
- halbtc8812a2ant_coex_table(btcoexist, force_exec,
- 0x5a5a5a5a, 0x5a5a5a5a, 0xffffff, 0x3);
- break;
- case 2:
- halbtc8812a2ant_coex_table(btcoexist, force_exec,
- 0x55555555, 0x5ffb5ffb, 0xffffff, 0x3);
- break;
- case 3:
- halbtc8812a2ant_coex_table(btcoexist, force_exec,
- 0x5fdf5fdf, 0x5fdb5fdb, 0xffffff, 0x3);
- break;
- case 4:
- halbtc8812a2ant_coex_table(btcoexist, force_exec,
- 0xdfffdfff, 0x5fdb5fdb, 0xffffff, 0x3);
- break;
- case 5:
- halbtc8812a2ant_coex_table(btcoexist, force_exec,
- 0x5ddd5ddd, 0x5fdb5fdb, 0xffffff, 0x3);
- break;
-
- default:
- break;
- }
-}
-
-void halbtc8812a2ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist,
- IN boolean enable)
-{
- u8 data_len = 3;
- u8 buf[5] = {0};
-
- buf[0] = data_len;
- buf[1] = 0x1; /* OP_Code */
- buf[2] = 0x1; /* OP_Code_Length */
- if (enable)
- buf[3] = 0x1; /* OP_Code_Content */
- else
- buf[3] = 0x0;
-
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_COEX,
- (void *)&buf[0]);
-}
-
-void halbtc8812a2ant_ignore_wlan_act(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean enable)
-{
- coex_dm->cur_ignore_wlan_act = enable;
-
- if (!force_exec) {
- if (coex_dm->pre_ignore_wlan_act ==
- coex_dm->cur_ignore_wlan_act)
- return;
- }
- halbtc8812a2ant_set_fw_ignore_wlan_act(btcoexist, enable);
-
- coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
-}
-
-void halbtc8812a2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist,
- IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5)
-{
- u8 h2c_parameter[5] = {0};
- u8 real_byte1 = byte1, real_byte5 = byte5;
- boolean ap_enable = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
- &ap_enable);
-
- if (ap_enable) {
- if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], FW for 1Ant AP mode\n");
- BTC_TRACE(trace_buf);
- real_byte1 &= ~BIT(4);
- real_byte1 |= BIT(5);
-
- real_byte5 |= BIT(5);
- real_byte5 &= ~BIT(6);
- }
- }
-
- h2c_parameter[0] = real_byte1;
- h2c_parameter[1] = byte2;
- h2c_parameter[2] = byte3;
- h2c_parameter[3] = byte4;
- h2c_parameter[4] = real_byte5;
-
-
- coex_dm->ps_tdma_para[0] = real_byte1;
- coex_dm->ps_tdma_para[1] = byte2;
- coex_dm->ps_tdma_para[2] = byte3;
- coex_dm->ps_tdma_para[3] = byte4;
- coex_dm->ps_tdma_para[4] = real_byte5;
-
- btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
-}
-
-void halbtc8812a2ant_set_lps_rpwm(IN struct btc_coexist *btcoexist,
- IN u8 lps_val, IN u8 rpwm_val)
-{
- u8 lps = lps_val;
- u8 rpwm = rpwm_val;
-
- btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps);
- btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm);
-}
-
-void halbtc8812a2ant_lps_rpwm(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val)
-{
- coex_dm->cur_lps = lps_val;
- coex_dm->cur_rpwm = rpwm_val;
-
- if (!force_exec) {
- if ((coex_dm->pre_lps == coex_dm->cur_lps) &&
- (coex_dm->pre_rpwm == coex_dm->cur_rpwm))
- return;
- }
- halbtc8812a2ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val);
-
- coex_dm->pre_lps = coex_dm->cur_lps;
- coex_dm->pre_rpwm = coex_dm->cur_rpwm;
-}
-
-void halbtc8812a2ant_sw_mechanism1(IN struct btc_coexist *btcoexist,
- IN boolean shrink_rx_lpf, IN boolean low_penalty_ra,
- IN boolean limited_dig, IN boolean bt_lna_constrain)
-{
- /*
- u32 wifi_bw;
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- if(BTC_WIFI_BW_HT40 != wifi_bw)
- {
- if (shrink_rx_lpf)
- shrink_rx_lpf = false;
- }
- */
-
- halbtc8812a2ant_rf_shrink(btcoexist, NORMAL_EXEC, shrink_rx_lpf);
- /* halbtc8812a2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra); */
-}
-
-void halbtc8812a2ant_sw_mechanism2(IN struct btc_coexist *btcoexist,
- IN boolean agc_table_shift, IN boolean adc_back_off,
- IN boolean sw_dac_swing, IN u32 dac_swing_lvl)
-{
- /* halbtc8812a2ant_agc_table(btcoexist, NORMAL_EXEC, agc_table_shift); */
- halbtc8812a2ant_adc_back_off(btcoexist, NORMAL_EXEC, adc_back_off);
- halbtc8812a2ant_dac_swing(btcoexist, NORMAL_EXEC, sw_dac_swing,
- dac_swing_lvl);
-}
-
-void halbtc8812a2ant_set_ant_path(IN struct btc_coexist *btcoexist,
- IN u8 ant_pos_type, IN boolean init_hwcfg, IN boolean wifi_off)
-{
- u8 u8tmp = 0;
-
- if (init_hwcfg) {
- btcoexist->btc_write_4byte(btcoexist, 0x900, 0x00000400);
- btcoexist->btc_write_1byte(btcoexist, 0x76d, 0x1);
- } else if (wifi_off) {
-
- }
-
- /* ext switch setting */
- switch (ant_pos_type) {
- case BTC_ANT_WIFI_AT_CPL_MAIN:
- break;
- case BTC_ANT_WIFI_AT_CPL_AUX:
- u8tmp = btcoexist->btc_read_1byte(btcoexist, 0xcb7);
- u8tmp &= ~BIT(3);
- u8tmp |= BIT(2);
- btcoexist->btc_write_1byte(btcoexist, 0xcb7, u8tmp);
- break;
- default:
- break;
- }
-}
-
-void halbtc8812a2ant_ps_tdma(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean turn_on, IN u8 type)
-{
- coex_dm->cur_ps_tdma_on = turn_on;
- coex_dm->cur_ps_tdma = type;
-
- if (!force_exec) {
- if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) &&
- (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma))
- return;
- }
- if (turn_on) {
- switch (type) {
- case 1:
- default:
- halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x1a, 0x1a, 0xa1, 0x90);
- break;
- case 2:
- halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x12, 0x12, 0xa1, 0x90);
- break;
- case 3:
- halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x1c, 0x3, 0xb1, 0x90);
- break;
- case 4:
- halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x10, 0x3, 0xb1, 0x90);
- break;
- case 5:
- halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x1a, 0x1a, 0x21, 0x10);
- break;
- case 6:
- halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x12, 0x12, 0x21, 0x10);
- break;
- case 7:
- halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x1c, 0x3, 0x21, 0x10);
- break;
- case 8:
- halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x10, 0x3, 0x21, 0x10);
- break;
- case 9:
- halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x1a, 0x1a, 0xa1, 0x10);
- break;
- case 10:
- halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x12, 0x12, 0xa1, 0x10);
- break;
- case 11:
- halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x1c, 0x3, 0xb1, 0x10);
- break;
- case 12:
- halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x10, 0x3, 0xb1, 0x10);
- break;
- case 13:
- halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x1a, 0x1a, 0x21, 0x10);
- break;
- case 14:
- halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x12, 0x12, 0x21, 0x10);
- break;
- case 15:
- halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x1c, 0x3, 0x21, 0x10);
- break;
- case 16:
- halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x10, 0x3, 0x21, 0x10);
- break;
- case 17:
- halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x35, 0x3, 0xb1, 0x11);
- break;
- case 18:
- halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x5, 0x5, 0xe1, 0x90);
- break;
- case 19:
- halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x25, 0x25, 0xe1, 0x90);
- break;
- case 20:
- halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x25, 0x25, 0x60, 0x90);
- break;
- case 21:
- halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x15, 0x3, 0x70, 0x90);
- break;
- case 22:
- halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x61,
- 0x1a, 0x1a, 0x21, 0x10);
- break;
- case 23:
- halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x1c, 0x03, 0x31, 0x10);
- break;
-
- case 71:
- halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x1a, 0x1a, 0xe1, 0x90);
- break;
-
- /* following cases is for wifi rssi low, started from 81 */
- case 81:
- halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xd3,
- 0x3a, 0x3, 0x90, 0x50);
- break;
- case 82:
- halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xd3,
- 0x2b, 0x3, 0x90, 0x50);
- break;
- case 83:
- halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xd3,
- 0x21, 0x3, 0x90, 0x50);
- break;
- case 84:
- halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xd3,
- 0x15, 0x3, 0x90, 0x50);
- break;
- case 85:
- halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xd3,
- 0x1d, 0x1d, 0x80, 0x50);
- break;
- case 86:
- halbtc8812a2ant_set_fw_pstdma(btcoexist, 0xd3,
- 0x15, 0x15, 0x80, 0x50);
- break;
- }
- } else {
- /* disable PS tdma */
- switch (type) {
- case 0: /* ANT2PTA, 0x778=0x1 */
- halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x8,
- 0x0, 0x0, 0x0, 0x0);
- break;
- case 1: /* ANT2BT, 0x778=3 */
- halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x0,
- 0x0, 0x0, 0x8, 0x0);
- delay_ms(5);
- halbtc8812a2ant_set_ant_path(btcoexist,
- BTC_ANT_WIFI_AT_CPL_AUX, false, false);
- break;
- default:
- halbtc8812a2ant_set_fw_pstdma(btcoexist, 0x0,
- 0x0, 0x0, 0x0, 0x0);
- break;
- }
- }
-
- /* update pre state */
- coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on;
- coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
-}
-
-void halbtc8812a2ant_coex_all_off(IN struct btc_coexist *btcoexist)
-{
- /* fw all off */
- halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
- halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- /* sw all off */
- halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
-
- /* hw all off */
- halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-}
-
-void halbtc8812a2ant_init_coex_dm(IN struct btc_coexist *btcoexist)
-{
- /* force to reset coex mechanism */
-
- halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 1);
- halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 6);
- halbtc8812a2ant_dec_bt_pwr(btcoexist, FORCE_EXEC, 0);
-
- halbtc8812a2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
-
- halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
-}
-
-void halbtc8812a2ant_ps_tdma_check_for_power_save_state(
- IN struct btc_coexist *btcoexist, IN boolean new_ps_state)
-{
- u8 lps_mode = 0x0;
-
- btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode);
-
- if (lps_mode) { /* already under LPS state */
- if (new_ps_state) {
- /* keep state under LPS, do nothing. */
- } else {
- /* will leave LPS state, turn off psTdma first */
- halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 0);
- }
- } else { /* NO PS state */
- if (new_ps_state) {
- /* will enter LPS state, turn off psTdma first */
- halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 0);
- } else {
- /* keep state under NO PS state, do nothing. */
- }
- }
-}
-
-void halbtc8812a2ant_power_save_state(IN struct btc_coexist *btcoexist,
- IN u8 ps_type, IN boolean low_pwr_disable, IN u8 lps_val,
- IN u8 rpwm_val)
-{
- switch (ps_type) {
- case BTC_PS_WIFI_NATIVE:
- btcoexist->btc_set(btcoexist,
- BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS,
- NULL);
- break;
- case BTC_PS_LPS_ON:
- halbtc8812a2ant_ps_tdma_check_for_power_save_state(
- btcoexist, true);
- halbtc8812a2ant_lps_rpwm(btcoexist, NORMAL_EXEC,
- lps_val, rpwm_val);
- btcoexist->btc_set(btcoexist,
- BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
- /* power save must executed before psTdma. */
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS,
- NULL);
- break;
- default:
- break;
- }
-}
-
-void halbtc8812a2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist)
-{
- halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, true,
- 0x0, 0x0);
-
- halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
- halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3);
- halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
-}
-
-boolean halbtc8812a2ant_is_common_action(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean common = false, wifi_connected = false, wifi_busy = false;
- boolean bt_hs_on = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
-
- if (coex_sta->c2h_bt_inquiry_page) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is under inquiry/page scan !!\n");
- BTC_TRACE(trace_buf);
- halbtc8812a2ant_action_bt_inquiry(btcoexist);
- return true;
- }
-
- if (bt_link_info->sco_exist || bt_link_info->hid_exist)
- halbtc8812a2ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 0, 0, 0);
- else
- halbtc8812a2ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
-
- if (!wifi_connected) {
- halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- false, 0x0, 0x0);
- halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
- 0x8);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi non-connected idle!!\n");
- BTC_TRACE(trace_buf);
-
- if ((BT_8812A_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
- coex_dm->bt_status) ||
- (BT_8812A_2ANT_BT_STATUS_CONNECTED_IDLE ==
- coex_dm->bt_status)) {
- halbtc8812a2ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 1);
- halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 0);
- } else {
- halbtc8812a2ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 0);
- halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 1);
- }
-
- halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8812a2ant_sw_mechanism1(btcoexist, false, false, false,
- false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, false, false, false,
- 0x18);
-
- common = true;
- } else {
- if (BT_8812A_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
- coex_dm->bt_status) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi connected + BT non connected-idle!!\n");
- BTC_TRACE(trace_buf);
- halbtc8812a2ant_power_save_state(btcoexist,
- BTC_PS_WIFI_NATIVE, false, 0x0, 0x0);
- halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC,
- false, false, 0x8);
-
- halbtc8812a2ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 0);
- halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 0);
- halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC,
- 6);
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8812a2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
-
- common = true;
- } else if (BT_8812A_2ANT_BT_STATUS_CONNECTED_IDLE ==
- coex_dm->bt_status) {
- if (bt_hs_on)
- return false;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi connected + BT connected-idle!!\n");
- BTC_TRACE(trace_buf);
- halbtc8812a2ant_power_save_state(btcoexist,
- BTC_PS_WIFI_NATIVE, true, 0x0, 0x0);
- halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC,
- false, false, 0x8);
-
- halbtc8812a2ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 0);
- halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 0);
- halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC,
- 6);
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8812a2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
-
- common = true;
- } else {
- if (wifi_busy) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi Connected-Busy + BT Busy!!\n");
- BTC_TRACE(trace_buf);
- common = false;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi Connected-Idle + BT Busy!!\n");
- BTC_TRACE(trace_buf);
-
- halbtc8812a2ant_power_save_state(btcoexist,
- BTC_PS_WIFI_NATIVE, true, 0x0, 0x0);
-
- halbtc8812a2ant_limited_rx(btcoexist,
- NORMAL_EXEC, false, false, 0x8);
-
- halbtc8812a2ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 0);
-
- halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 17);
-
- halbtc8812a2ant_fw_dac_swing_lvl(btcoexist,
- NORMAL_EXEC, 6);
- halbtc8812a2ant_dec_bt_pwr(btcoexist,
- NORMAL_EXEC, 0);
- halbtc8812a2ant_sw_mechanism1(btcoexist, false,
- false, false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, false,
- false, false, 0x18);
- common = true;
- }
- }
- }
-
- return common;
-}
-
-void halbtc8812a2ant_tdma_duration_adjust(IN struct btc_coexist *btcoexist,
- IN boolean sco_hid, IN boolean tx_pause, IN u8 max_interval)
-{
- static s32 up, dn, m, n, wait_count;
- s32 result; /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */
- u8 retry_count = 0;
-
- coex_dm->auto_tdma_adjust_low_rssi = false;
-
- if (!coex_dm->auto_tdma_adjust) {
- coex_dm->auto_tdma_adjust = true;
- {
- if (sco_hid) {
- if (tx_pause) {
- if (max_interval == 1) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 13);
- coex_dm->ps_tdma_du_adj_type =
- 13;
- } else if (max_interval == 2) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 14);
- coex_dm->ps_tdma_du_adj_type =
- 14;
- } else if (max_interval == 3) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- }
- } else {
- if (max_interval == 1) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 9);
- coex_dm->ps_tdma_du_adj_type =
- 9;
- } else if (max_interval == 2) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 10);
- coex_dm->ps_tdma_du_adj_type =
- 10;
- } else if (max_interval == 3) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- }
- }
- } else {
- if (tx_pause) {
- if (max_interval == 1) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 5);
- coex_dm->ps_tdma_du_adj_type =
- 5;
- } else if (max_interval == 2) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 6);
- coex_dm->ps_tdma_du_adj_type =
- 6;
- } else if (max_interval == 3) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- }
- } else {
- if (max_interval == 1) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 1);
- coex_dm->ps_tdma_du_adj_type =
- 1;
- } else if (max_interval == 2) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 2);
- coex_dm->ps_tdma_du_adj_type =
- 2;
- } else if (max_interval == 3) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- }
- }
- }
- }
- /* ============ */
- up = 0;
- dn = 0;
- m = 1;
- n = 3;
- result = 0;
- wait_count = 0;
- } else {
- /* accquire the BT TRx retry count from BT_Info byte2 */
- retry_count = coex_sta->bt_retry_cnt;
- result = 0;
- wait_count++;
-
- if (retry_count ==
- 0) { /* no retry in the last 2-second duration */
- up++;
- dn--;
-
- if (dn <= 0)
- dn = 0;
-
- if (up >= n) { /* if ³sÄò n Ó2¬í retry count¬°0, «h½Õ¼eWiFi duration */
- wait_count = 0;
- n = 3;
- up = 0;
- dn = 0;
- result = 1;
- }
- } else if (retry_count <=
- 3) { /* <=3 retry in the last 2-second duration */
- up--;
- dn++;
-
- if (up <= 0)
- up = 0;
-
- if (dn == 2) { /* if ³sÄò 2 Ó2¬í retry count< 3, «h½Õ¯¶WiFi duration */
- if (wait_count <= 2)
- m++; /* ÁקK¤@ª½¦b¨âÓlevel¤¤¨Ó¦^ */
- else
- m = 1;
-
- if (m >= 20) /* m ³Ì¤jÈ = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration. */
- m = 20;
-
- n = 3 * m;
- up = 0;
- dn = 0;
- wait_count = 0;
- result = -1;
- }
- } else { /* retry count > 3, ¥un1¦¸ retry count > 3, «h½Õ¯¶WiFi duration */
- if (wait_count == 1)
- m++; /* ÁקK¤@ª½¦b¨âÓlevel¤¤¨Ó¦^ */
- else
- m = 1;
-
- if (m >= 20) /* m ³Ì¤jÈ = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration. */
- m = 20;
-
- n = 3 * m;
- up = 0;
- dn = 0;
- wait_count = 0;
- result = -1;
- }
-
- if (max_interval == 1) {
- if (tx_pause) {
- if (coex_dm->cur_ps_tdma == 71) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 5);
- coex_dm->ps_tdma_du_adj_type = 5;
- } else if (coex_dm->cur_ps_tdma == 1) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 5);
- coex_dm->ps_tdma_du_adj_type = 5;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 6);
- coex_dm->ps_tdma_du_adj_type = 6;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 7);
- coex_dm->ps_tdma_du_adj_type = 7;
- } else if (coex_dm->cur_ps_tdma == 4) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 8);
- coex_dm->ps_tdma_du_adj_type = 8;
- }
- if (coex_dm->cur_ps_tdma == 9) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 13);
- coex_dm->ps_tdma_du_adj_type = 13;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 14);
- coex_dm->ps_tdma_du_adj_type = 14;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 15);
- coex_dm->ps_tdma_du_adj_type = 15;
- } else if (coex_dm->cur_ps_tdma == 12) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 16);
- coex_dm->ps_tdma_du_adj_type = 16;
- }
-
- if (result == -1) {
- if (coex_dm->cur_ps_tdma == 5) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 6);
- coex_dm->ps_tdma_du_adj_type =
- 6;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 8);
- coex_dm->ps_tdma_du_adj_type =
- 8;
- } else if (coex_dm->cur_ps_tdma == 13) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 14);
- coex_dm->ps_tdma_du_adj_type =
- 14;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 16);
- coex_dm->ps_tdma_du_adj_type =
- 16;
- }
- } else if (result == 1) {
- if (coex_dm->cur_ps_tdma == 8) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 6);
- coex_dm->ps_tdma_du_adj_type =
- 6;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 5);
- coex_dm->ps_tdma_du_adj_type =
- 5;
- } else if (coex_dm->cur_ps_tdma == 16) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 14);
- coex_dm->ps_tdma_du_adj_type =
- 14;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 13);
- coex_dm->ps_tdma_du_adj_type =
- 13;
- }
- }
- } else {
- if (coex_dm->cur_ps_tdma == 5) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 71);
- coex_dm->ps_tdma_du_adj_type = 71;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 2);
- coex_dm->ps_tdma_du_adj_type = 2;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 3);
- coex_dm->ps_tdma_du_adj_type = 3;
- } else if (coex_dm->cur_ps_tdma == 8) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 4);
- coex_dm->ps_tdma_du_adj_type = 4;
- }
- if (coex_dm->cur_ps_tdma == 13) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 9);
- coex_dm->ps_tdma_du_adj_type = 9;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 10);
- coex_dm->ps_tdma_du_adj_type = 10;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 11);
- coex_dm->ps_tdma_du_adj_type = 11;
- } else if (coex_dm->cur_ps_tdma == 16) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 12);
- coex_dm->ps_tdma_du_adj_type = 12;
- }
-
- if (result == -1) {
- if (coex_dm->cur_ps_tdma == 71) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 1);
- coex_dm->ps_tdma_du_adj_type =
- 1;
- } else if (coex_dm->cur_ps_tdma == 1) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 2);
- coex_dm->ps_tdma_du_adj_type =
- 2;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 4);
- coex_dm->ps_tdma_du_adj_type =
- 4;
- } else if (coex_dm->cur_ps_tdma == 9) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 10);
- coex_dm->ps_tdma_du_adj_type =
- 10;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 12);
- coex_dm->ps_tdma_du_adj_type =
- 12;
- }
- } else if (result == 1) {
- if (coex_dm->cur_ps_tdma == 4) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 2);
- coex_dm->ps_tdma_du_adj_type =
- 2;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 1);
- coex_dm->ps_tdma_du_adj_type =
- 1;
- } else if (coex_dm->cur_ps_tdma == 1) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 71);
- coex_dm->ps_tdma_du_adj_type =
- 71;
- } else if (coex_dm->cur_ps_tdma == 12) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 10);
- coex_dm->ps_tdma_du_adj_type =
- 10;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 9);
- coex_dm->ps_tdma_du_adj_type =
- 9;
- }
- }
- }
- } else if (max_interval == 2) {
- if (tx_pause) {
- if (coex_dm->cur_ps_tdma == 1) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 6);
- coex_dm->ps_tdma_du_adj_type = 6;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 6);
- coex_dm->ps_tdma_du_adj_type = 6;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 7);
- coex_dm->ps_tdma_du_adj_type = 7;
- } else if (coex_dm->cur_ps_tdma == 4) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 8);
- coex_dm->ps_tdma_du_adj_type = 8;
- }
- if (coex_dm->cur_ps_tdma == 9) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 14);
- coex_dm->ps_tdma_du_adj_type = 14;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 14);
- coex_dm->ps_tdma_du_adj_type = 14;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 15);
- coex_dm->ps_tdma_du_adj_type = 15;
- } else if (coex_dm->cur_ps_tdma == 12) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 16);
- coex_dm->ps_tdma_du_adj_type = 16;
- }
- if (result == -1) {
- if (coex_dm->cur_ps_tdma == 5) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 6);
- coex_dm->ps_tdma_du_adj_type =
- 6;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 8);
- coex_dm->ps_tdma_du_adj_type =
- 8;
- } else if (coex_dm->cur_ps_tdma == 13) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 14);
- coex_dm->ps_tdma_du_adj_type =
- 14;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 16);
- coex_dm->ps_tdma_du_adj_type =
- 16;
- }
- } else if (result == 1) {
- if (coex_dm->cur_ps_tdma == 8) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 6);
- coex_dm->ps_tdma_du_adj_type =
- 6;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 6);
- coex_dm->ps_tdma_du_adj_type =
- 6;
- } else if (coex_dm->cur_ps_tdma == 16) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 14);
- coex_dm->ps_tdma_du_adj_type =
- 14;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 14);
- coex_dm->ps_tdma_du_adj_type =
- 14;
- }
- }
- } else {
- if (coex_dm->cur_ps_tdma == 5) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 2);
- coex_dm->ps_tdma_du_adj_type = 2;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 2);
- coex_dm->ps_tdma_du_adj_type = 2;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 3);
- coex_dm->ps_tdma_du_adj_type = 3;
- } else if (coex_dm->cur_ps_tdma == 8) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 4);
- coex_dm->ps_tdma_du_adj_type = 4;
- }
- if (coex_dm->cur_ps_tdma == 13) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 10);
- coex_dm->ps_tdma_du_adj_type = 10;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 10);
- coex_dm->ps_tdma_du_adj_type = 10;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 11);
- coex_dm->ps_tdma_du_adj_type = 11;
- } else if (coex_dm->cur_ps_tdma == 16) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 12);
- coex_dm->ps_tdma_du_adj_type = 12;
- }
- if (result == -1) {
- if (coex_dm->cur_ps_tdma == 1) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 2);
- coex_dm->ps_tdma_du_adj_type =
- 2;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 4);
- coex_dm->ps_tdma_du_adj_type =
- 4;
- } else if (coex_dm->cur_ps_tdma == 9) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 10);
- coex_dm->ps_tdma_du_adj_type =
- 10;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 12);
- coex_dm->ps_tdma_du_adj_type =
- 12;
- }
- } else if (result == 1) {
- if (coex_dm->cur_ps_tdma == 4) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 2);
- coex_dm->ps_tdma_du_adj_type =
- 2;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 2);
- coex_dm->ps_tdma_du_adj_type =
- 2;
- } else if (coex_dm->cur_ps_tdma == 12) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 10);
- coex_dm->ps_tdma_du_adj_type =
- 10;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 10);
- coex_dm->ps_tdma_du_adj_type =
- 10;
- }
- }
- }
- } else if (max_interval == 3) {
- if (tx_pause) {
- if (coex_dm->cur_ps_tdma == 1) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 7);
- coex_dm->ps_tdma_du_adj_type = 7;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 7);
- coex_dm->ps_tdma_du_adj_type = 7;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 7);
- coex_dm->ps_tdma_du_adj_type = 7;
- } else if (coex_dm->cur_ps_tdma == 4) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 8);
- coex_dm->ps_tdma_du_adj_type = 8;
- }
- if (coex_dm->cur_ps_tdma == 9) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 15);
- coex_dm->ps_tdma_du_adj_type = 15;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 15);
- coex_dm->ps_tdma_du_adj_type = 15;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 15);
- coex_dm->ps_tdma_du_adj_type = 15;
- } else if (coex_dm->cur_ps_tdma == 12) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 16);
- coex_dm->ps_tdma_du_adj_type = 16;
- }
- if (result == -1) {
- if (coex_dm->cur_ps_tdma == 5) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 8);
- coex_dm->ps_tdma_du_adj_type =
- 8;
- } else if (coex_dm->cur_ps_tdma == 13) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 16);
- coex_dm->ps_tdma_du_adj_type =
- 16;
- }
- } else if (result == 1) {
- if (coex_dm->cur_ps_tdma == 8) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 16) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- }
- }
- } else {
- if (coex_dm->cur_ps_tdma == 5) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 3);
- coex_dm->ps_tdma_du_adj_type = 3;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 3);
- coex_dm->ps_tdma_du_adj_type = 3;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 3);
- coex_dm->ps_tdma_du_adj_type = 3;
- } else if (coex_dm->cur_ps_tdma == 8) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 4);
- coex_dm->ps_tdma_du_adj_type = 4;
- }
- if (coex_dm->cur_ps_tdma == 13) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 11);
- coex_dm->ps_tdma_du_adj_type = 11;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 11);
- coex_dm->ps_tdma_du_adj_type = 11;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 11);
- coex_dm->ps_tdma_du_adj_type = 11;
- } else if (coex_dm->cur_ps_tdma == 16) {
- halbtc8812a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 12);
- coex_dm->ps_tdma_du_adj_type = 12;
- }
- if (result == -1) {
- if (coex_dm->cur_ps_tdma == 1) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 4);
- coex_dm->ps_tdma_du_adj_type =
- 4;
- } else if (coex_dm->cur_ps_tdma == 9) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 12);
- coex_dm->ps_tdma_du_adj_type =
- 12;
- }
- } else if (result == 1) {
- if (coex_dm->cur_ps_tdma == 4) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 12) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8812a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- }
- }
- }
- }
- }
-
- /* if current PsTdma not match with the recorded one (when scan, dhcp...), */
- /* then we have to adjust it back to the previous record one. */
- if (coex_dm->cur_ps_tdma != coex_dm->ps_tdma_du_adj_type) {
- boolean scan = false, link = false, roam = false;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], PsTdma type dismatch!!!, cur_ps_tdma=%d, recordPsTdma=%d\n",
- coex_dm->cur_ps_tdma, coex_dm->ps_tdma_du_adj_type);
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
-
- if (!scan && !link && !roam)
- halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- coex_dm->ps_tdma_du_adj_type);
- else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n");
- BTC_TRACE(trace_buf);
- }
- }
-}
-
-/* ******************
- * pstdma for wifi rssi low
- * ****************** */
-void halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low(
- IN struct btc_coexist *btcoexist/* , */ /* IN u8 wifi_status */)
-{
- static s32 up, dn, m, n, wait_count;
- s32 result; /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */
- u8 retry_count = 0, bt_info_ext;
-
- coex_dm->auto_tdma_adjust = false;
-
- retry_count = coex_sta->bt_retry_cnt;
- bt_info_ext = coex_sta->bt_info_ext;
-
- if (!coex_dm->auto_tdma_adjust_low_rssi) {
- coex_dm->auto_tdma_adjust_low_rssi = true;
-
- if (BT_INFO_8812A_2ANT_A2DP_BASIC_RATE(bt_info_ext)) {
- halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 83);
- coex_dm->ps_tdma_du_adj_type = 83;
- } else {
- halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 82);
- coex_dm->ps_tdma_du_adj_type = 82;
- }
- /* ============ */
- up = 0;
- dn = 0;
- m = 1;
- n = 3;
- result = 0;
- wait_count = 0;
- } else {
- /* accquire the BT TRx retry count from BT_Info byte2
- * retry_count = coex_sta->bt_retry_cnt;
- * bt_info_ext = coex_sta->bt_info_ext; */
- result = 0;
- wait_count++;
-
- if ((coex_sta->low_priority_tx) > 1150 ||
- (coex_sta->low_priority_rx) > 1250)
- retry_count++;
-
- if (retry_count ==
- 0) { /* no retry in the last 2-second duration */
- up++;
- dn--;
-
- if (dn <= 0)
- dn = 0;
-
- if (up >= n) { /* if retry count during continuous n*2 seconds is 0, enlarge WiFi duration */
- wait_count = 0;
- n = 3;
- up = 0;
- dn = 0;
- result = 1;
- }
- } else if (retry_count <=
- 3) { /* <=3 retry in the last 2-second duration */
- up--;
- dn++;
-
- if (up <= 0)
- up = 0;
-
- if (dn == 2) { /* if continuous 2 retry count(every 2 seconds) >0 and < 3, reduce WiFi duration */
- if (wait_count <= 2)
- m++; /* to avoid loop between the two levels */
- else
- m = 1;
-
- if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */
- m = 20;
-
- n = 3 * m;
- up = 0;
- dn = 0;
- wait_count = 0;
- result = -1;
- }
- } else { /* retry count > 3, once retry count > 3, to reduce WiFi duration */
- if (wait_count == 1)
- m++; /* to avoid loop between the two levels */
- else
- m = 1;
-
- if (m >= 20) /* maximum of m = 20 ' will recheck if need to adjust wifi duration in maximum time interval 120 seconds */
- m = 20;
-
- n = 3 * m;
- up = 0;
- dn = 0;
- wait_count = 0;
- result = -1;
- }
-
- if (result == -1) {
- if ((BT_INFO_8812A_2ANT_A2DP_BASIC_RATE(bt_info_ext)) &&
- ((coex_dm->cur_ps_tdma == 81) ||
- (coex_dm->cur_ps_tdma == 82))) {
- halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 84);
- coex_dm->ps_tdma_du_adj_type = 84;
- } else if (coex_dm->cur_ps_tdma == 81) {
- halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 82);
- coex_dm->ps_tdma_du_adj_type = 82;
- } else if (coex_dm->cur_ps_tdma == 82) {
- halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 83);
- coex_dm->ps_tdma_du_adj_type = 83;
- } else if (coex_dm->cur_ps_tdma == 83) {
- halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 84);
- coex_dm->ps_tdma_du_adj_type = 84;
- }
- } else if (result == 1) {
- if ((BT_INFO_8812A_2ANT_A2DP_BASIC_RATE(bt_info_ext)) &&
- ((coex_dm->cur_ps_tdma == 81) ||
- (coex_dm->cur_ps_tdma == 82))) {
- halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 83);
- coex_dm->ps_tdma_du_adj_type = 83;
- } else if (coex_dm->cur_ps_tdma == 84) {
- halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 83);
- coex_dm->ps_tdma_du_adj_type = 83;
- } else if (coex_dm->cur_ps_tdma == 83) {
- halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 82);
- coex_dm->ps_tdma_du_adj_type = 82;
- } else if (coex_dm->cur_ps_tdma == 82) {
- halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC,
- true, 81);
- coex_dm->ps_tdma_du_adj_type = 81;
- }
- }
-
- if (coex_dm->cur_ps_tdma != 81 &&
- coex_dm->cur_ps_tdma != 82 &&
- coex_dm->cur_ps_tdma != 83 &&
- coex_dm->cur_ps_tdma != 84) {
- /* recover to previous adjust type */
- halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- coex_dm->ps_tdma_du_adj_type);
- }
- }
-}
-
-void halbtc8812a2ant_get_bt_rssi_threshold(IN struct btc_coexist *btcoexist,
- IN u8 *pThres0, IN u8 *pThres1)
-{
- u8 ant_type;
-
- btcoexist->btc_get(btcoexist, BTC_GET_U1_ANT_TYPE, &ant_type);
-
- switch (ant_type) {
- case BTC_ANT_TYPE_0:
- *pThres0 = 100;
- *pThres1 = 100;
- break;
- case BTC_ANT_TYPE_1:
- *pThres0 = 34;
- *pThres1 = 42;
- break;
- case BTC_ANT_TYPE_2:
- *pThres0 = 34;
- *pThres1 = 42;
- break;
- case BTC_ANT_TYPE_3:
- *pThres0 = 34;
- *pThres1 = 42;
- break;
- case BTC_ANT_TYPE_4:
- *pThres0 = 34;
- *pThres1 = 42;
- break;
- default:
- break;
- }
-}
-
-
-
-void halbtc8812a2ant_action_sco(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH,
- bt_rssi_state = BTC_RSSI_STATE_HIGH;
- u32 wifi_bw;
- u8 bt_thresh0 = 0, bt_thresh1 = 0;
-
-
- halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0,
- &bt_thresh1);
- bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0,
- bt_thresh1);
-
- wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34,
- 0);
- /* bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); */
-
- /* power save state */
- halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, true,
- 0x0, 0x0);
-
- /* coex table */
- if (BTC_RSSI_LOW(bt_rssi_state))
- halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
- else
- halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
-
- /* pstdma */
- if (BTC_RSSI_LOW(bt_rssi_state))
- halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13);
- else
- halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9);
-
- /* decrease BT power */
- if (BTC_RSSI_LOW(bt_rssi_state))
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
- else if (BTC_RSSI_MEDIUM(bt_rssi_state))
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- else
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
-
- /* limited Rx */
- halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
-
- /* fw dac swing level */
- halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- /* sw mechanism */
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if (BTC_RSSI_HIGH(wifi_rssi_state)) {
- halbtc8812a2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
- true, 0x6);
- } else {
- halbtc8812a2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
- true, 0x6);
- }
- } else {
- if (BTC_RSSI_HIGH(wifi_rssi_state)) {
- halbtc8812a2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
- true, 0x6);
- } else {
- halbtc8812a2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
- true, 0x6);
- }
- }
-}
-
-void halbtc8812a2ant_action_sco_hid(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH,
- bt_rssi_state = BTC_RSSI_STATE_HIGH;
- u32 wifi_bw;
- u8 bt_thresh0 = 0, bt_thresh1 = 0;
-
- halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0,
- &bt_thresh1);
- bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0,
- bt_thresh1);
-
- wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34,
- 0);
- /* bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); */
-
- /* power save state */
- halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, true,
- 0x0, 0x0);
-
- /* coex table */
- halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
-
- /* pstdma */
- if (BTC_RSSI_LOW(bt_rssi_state))
- halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13);
- else
- halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9);
-
- /* decrease BT power */
- if (BTC_RSSI_LOW(bt_rssi_state))
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
- else if (BTC_RSSI_MEDIUM(bt_rssi_state))
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- else
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
-
- /* limited Rx */
- halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true, 0x8);
-
- /* fw dac swing level */
- halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- /* sw mechanism */
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if (BTC_RSSI_HIGH(wifi_rssi_state)) {
- halbtc8812a2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x6);
- } else {
- halbtc8812a2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x6);
- }
- } else {
- if (BTC_RSSI_HIGH(wifi_rssi_state)) {
- halbtc8812a2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x6);
- } else {
- halbtc8812a2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x6);
- }
- }
-}
-
-void halbtc8812a2ant_action_hid(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH,
- bt_rssi_state = BTC_RSSI_STATE_HIGH;
- u32 wifi_bw;
- u8 bt_thresh0 = 0, bt_thresh1 = 0;
-
- halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0,
- &bt_thresh1);
- bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0,
- bt_thresh1);
-
- wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34,
- 0);
- /* bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); */
-
- /* power save state */
- halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, true,
- 0x0, 0x0);
-
- /* coex table */
- if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
- else
- halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- /* pstdma */
- if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9);
- else
- halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22);
-
- /* decrease BT power */
- if (BTC_RSSI_LOW(bt_rssi_state))
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
- else if (BTC_RSSI_MEDIUM(bt_rssi_state))
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- else
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
-
- /* limited Rx */
- if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
- 0x8);
- else if (BTC_RSSI_LOW(wifi_rssi_state) &&
- (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
- 0x8);
- else
- halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true,
- 0x8);
-
-
- /* fw dac swing level */
- halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- /* sw mechanism */
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if (BTC_RSSI_HIGH(wifi_rssi_state)) {
- halbtc8812a2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8812a2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- } else {
- if (BTC_RSSI_HIGH(wifi_rssi_state)) {
- halbtc8812a2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8812a2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- }
-}
-
-/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */
-void halbtc8812a2ant_action_a2dp(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH,
- bt_rssi_state = BTC_RSSI_STATE_HIGH;
- u32 wifi_bw;
- u8 bt_thresh0 = 0, bt_thresh1 = 0;
- boolean ap_enable = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
- &ap_enable);
-
- halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0,
- &bt_thresh1);
- bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0,
- bt_thresh1);
-
- wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34,
- 0);
- /* bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); */
-
- /* power save state */
- if ((ap_enable == true) || (BTC_RSSI_HIGH(wifi_rssi_state) &&
- (!BTC_RSSI_LOW(bt_rssi_state))))
- halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- true, 0x0, 0x0);
- else
- halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, true,
- 0x50, 0x4);
-
- /* coex table */
- if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
- else
- halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- /* pstdma */
- if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_tdma_duration_adjust(btcoexist, false, false,
- 1);
- else
- halbtc8812a2ant_tdma_duration_adjust_for_wifi_rssi_low(
- btcoexist);
-
- /* decrease BT power */
- if (BTC_RSSI_LOW(bt_rssi_state))
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
- else if (BTC_RSSI_MEDIUM(bt_rssi_state))
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- else
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
-
- /* limited Rx */
- halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
-
- /* fw dac swing level */
- halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
-
- /* sw mechanism */
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if (BTC_RSSI_HIGH(wifi_rssi_state)) {
- halbtc8812a2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8812a2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- } else {
- if (BTC_RSSI_HIGH(wifi_rssi_state)) {
- halbtc8812a2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8812a2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- }
-}
-
-void halbtc8812a2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH,
- bt_rssi_state = BTC_RSSI_STATE_HIGH;
- u32 wifi_bw;
- u8 bt_thresh0 = 0, bt_thresh1 = 0;
-
- halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0,
- &bt_thresh1);
- bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0,
- bt_thresh1);
-
- wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34,
- 0);
- /* bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); */
-
- /* power save state */
- halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, true,
- 0x0, 0x0);
-
- /* coex table */
- if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
- else
- halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
-
- /* pstdma */
- if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_tdma_duration_adjust(btcoexist, false, false,
- 2);
- else
- halbtc8812a2ant_tdma_duration_adjust(btcoexist, false, true, 2);
-
- /* decrease BT power */
- if (BTC_RSSI_LOW(bt_rssi_state))
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
- else if (BTC_RSSI_MEDIUM(bt_rssi_state))
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- else
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
-
- /* limited Rx */
- halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
-
- /* fw dac swing level */
- halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
-
- /* sw mechanism */
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if (BTC_RSSI_HIGH(wifi_rssi_state)) {
- halbtc8812a2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
- true, 0x6);
- } else {
- halbtc8812a2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
- true, 0x6);
- }
- } else {
- if (BTC_RSSI_HIGH(wifi_rssi_state)) {
- halbtc8812a2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
- true, 0x6);
- } else {
- halbtc8812a2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
- true, 0x6);
- }
- }
-}
-
-void halbtc8812a2ant_action_pan_edr(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH,
- bt_rssi_state = BTC_RSSI_STATE_HIGH;
- u32 wifi_bw;
- u8 bt_thresh0 = 0, bt_thresh1 = 0;
- boolean ap_enable = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
- &ap_enable);
-
-
- halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0,
- &bt_thresh1);
- bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0,
- bt_thresh1);
-
- wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34,
- 0);
- /* bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); */
-
- /* power save state */
- if ((ap_enable == true) || (BTC_RSSI_HIGH(wifi_rssi_state) &&
- (!BTC_RSSI_LOW(bt_rssi_state))))
- halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- true, 0x0, 0x0);
- else
- halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, true,
- 0x50, 0x4);
-
- /* coex table */
- if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
- else
- halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- /* pstdma */
- if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 1);
- else
- halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 85);
-
- /* decrease BT power */
- if (BTC_RSSI_LOW(bt_rssi_state))
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
- else if (BTC_RSSI_MEDIUM(bt_rssi_state))
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- else
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
-
- /* limited Rx */
- halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
-
- /* fw dac swing level */
- halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
-
- /* sw mechanism */
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if (BTC_RSSI_HIGH(wifi_rssi_state)) {
- halbtc8812a2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8812a2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- } else {
- if (BTC_RSSI_HIGH(wifi_rssi_state)) {
- halbtc8812a2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8812a2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- }
-}
-
-/* PAN(HS) only */
-void halbtc8812a2ant_action_pan_hs(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH,
- bt_rssi_state = BTC_RSSI_STATE_HIGH;
- u32 wifi_bw;
-
- wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34,
- 0);
- bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42);
-
- /* power save state */
- halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, true,
- 0x0, 0x0);
-
- /* coex table */
- halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
-
- /* pstdma */
- halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
-
- /* decrease BT power */
- if (BTC_RSSI_LOW(bt_rssi_state))
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
- else if (BTC_RSSI_MEDIUM(bt_rssi_state))
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- else
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
-
- /* limited Rx */
- halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
-
- /* fw dac swing level */
- halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if (BTC_RSSI_HIGH(wifi_rssi_state)) {
- halbtc8812a2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8812a2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- } else {
- if (BTC_RSSI_HIGH(wifi_rssi_state)) {
- halbtc8812a2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8812a2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- }
-}
-
-/* PAN(EDR)+A2DP */
-void halbtc8812a2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH,
- bt_rssi_state = BTC_RSSI_STATE_HIGH;
- u32 wifi_bw;
- u8 bt_thresh0 = 0, bt_thresh1 = 0;
- boolean ap_enable = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
- &ap_enable);
-
- halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0,
- &bt_thresh1);
- bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0,
- bt_thresh1);
-
-
- wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34,
- 0);
- /* bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); */
-
- /* power save state */
- if ((ap_enable == true) || (BTC_RSSI_HIGH(wifi_rssi_state) &&
- (!BTC_RSSI_LOW(bt_rssi_state))))
- halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- true, 0x0, 0x0);
- else if (BTC_RSSI_LOW(wifi_rssi_state) &&
- (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- true, 0x0, 0x0);
- else
- halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, true,
- 0x50, 0x4);
-
- /* coex table */
- if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
- else if (BTC_RSSI_LOW(wifi_rssi_state) &&
- (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
- else
- halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- /* pstdma */
- if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_tdma_duration_adjust(btcoexist, false, false,
- 3);
- else if (BTC_RSSI_LOW(wifi_rssi_state) &&
- (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_tdma_duration_adjust(btcoexist, false, true, 3);
- else {
- coex_dm->auto_tdma_adjust = false;
- halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 86);
- }
-
- /* decrease BT power */
- if (BTC_RSSI_LOW(bt_rssi_state))
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
- else if (BTC_RSSI_MEDIUM(bt_rssi_state))
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- else
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
-
- /* limited Rx */
- halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
-
- /* fw dac swing level */
- halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- /* sw mechanism */
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if (BTC_RSSI_HIGH(wifi_rssi_state)) {
- halbtc8812a2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8812a2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- } else {
- if (BTC_RSSI_HIGH(wifi_rssi_state)) {
- halbtc8812a2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8812a2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- }
-}
-
-void halbtc8812a2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH,
- bt_rssi_state = BTC_RSSI_STATE_HIGH;
- u32 wifi_bw;
- u8 bt_thresh0 = 0, bt_thresh1 = 0;
- boolean ap_enable = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
- &ap_enable);
-
- halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0,
- &bt_thresh1);
- bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0,
- bt_thresh1);
-
- wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34,
- 0);
- /* bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); */
-
- /* power save state */
- if ((ap_enable == true) || (BTC_RSSI_HIGH(wifi_rssi_state) &&
- (!BTC_RSSI_LOW(bt_rssi_state))))
- halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- true, 0x0, 0x0);
- else if (BTC_RSSI_LOW(wifi_rssi_state) &&
- (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- true, 0x0, 0x0);
- else
- halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, true,
- 0x50, 0x4);
-
- /* coex table */
- if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
- else if (BTC_RSSI_LOW(wifi_rssi_state) &&
- (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
- else
- halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- /* pstdma */
- if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 10);
- else if (BTC_RSSI_LOW(wifi_rssi_state) &&
- (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14);
- else
- halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 85);
-
- /* decrease BT power */
- if (BTC_RSSI_LOW(bt_rssi_state))
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
- else if (BTC_RSSI_MEDIUM(bt_rssi_state))
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- else
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
-
- /* limited Rx */
- if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
- 0x8);
- else if (BTC_RSSI_LOW(wifi_rssi_state) &&
- (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
- 0x8);
- else
- halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true,
- 0x8);
-
- /* fw dac swing level */
- halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- /* sw mechanism */
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if (BTC_RSSI_HIGH(wifi_rssi_state)) {
- halbtc8812a2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8812a2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- } else {
- if (BTC_RSSI_HIGH(wifi_rssi_state)) {
- halbtc8812a2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8812a2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- }
-}
-
-/* HID+A2DP+PAN(EDR) */
-void halbtc8812a2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH,
- bt_rssi_state = BTC_RSSI_STATE_HIGH;
- u32 wifi_bw;
- u8 bt_thresh0 = 0, bt_thresh1 = 0;
- boolean ap_enable = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
- &ap_enable);
-
- halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0,
- &bt_thresh1);
- bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0,
- bt_thresh1);
-
- wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34,
- 0);
- /* bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); */
-
- /* power save state */
- if ((ap_enable == true) || (BTC_RSSI_HIGH(wifi_rssi_state) &&
- (!BTC_RSSI_LOW(bt_rssi_state))))
- halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- true, 0x0, 0x0);
- else if (BTC_RSSI_LOW(wifi_rssi_state) &&
- (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- true, 0x0, 0x0);
- else
- halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, true,
- 0x50, 0x4);
-
- /* coex table */
- if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
- else if (BTC_RSSI_LOW(wifi_rssi_state) &&
- (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
- else
- halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- /* pstdma */
- if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_tdma_duration_adjust(btcoexist, true, false, 3);
- else if (BTC_RSSI_LOW(wifi_rssi_state) &&
- (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_tdma_duration_adjust(btcoexist, true, true, 3);
- else {
- coex_dm->auto_tdma_adjust = false;
- halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 86);
- }
-
- /* decrease BT power */
- if (BTC_RSSI_LOW(bt_rssi_state))
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
- else if (BTC_RSSI_MEDIUM(bt_rssi_state))
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- else
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
-
- /* limited Rx */
- if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
- 0x8);
- else if (BTC_RSSI_LOW(wifi_rssi_state) &&
- (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
- 0x8);
- else
- halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true,
- 0x8);
-
-
- /* fw dac swing level */
- halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- /* sw mechanism */
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if (BTC_RSSI_HIGH(wifi_rssi_state)) {
- halbtc8812a2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8812a2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- } else {
- if (BTC_RSSI_HIGH(wifi_rssi_state)) {
- halbtc8812a2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8812a2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- }
-}
-
-void halbtc8812a2ant_action_hid_a2dp_pan_hs(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH,
- bt_rssi_state = BTC_RSSI_STATE_HIGH;
- u32 wifi_bw;
- u8 bt_thresh0 = 0, bt_thresh1 = 0;
-
- halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0,
- &bt_thresh1);
- bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0,
- bt_thresh1);
-
-
- wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34,
- 0);
- /* bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); */
-
- /* power save state */
- halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, true,
- 0x0, 0x0);
-
- /* coex table */
- if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
- else if (BTC_RSSI_LOW(wifi_rssi_state) &&
- (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
- else
- halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- /* pstdma */
- if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_tdma_duration_adjust(btcoexist, true, false, 2);
- else if (BTC_RSSI_LOW(wifi_rssi_state) &&
- (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_tdma_duration_adjust(btcoexist, true, true, 2);
- else
- halbtc8812a2ant_tdma_duration_adjust(btcoexist, true, true, 2);
-
- /* decrease BT power */
- if (BTC_RSSI_LOW(bt_rssi_state))
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
- else if (BTC_RSSI_MEDIUM(bt_rssi_state))
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- else
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
-
- /* limited Rx */
- if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
- 0x8);
- else if (BTC_RSSI_LOW(wifi_rssi_state) &&
- (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
- 0x8);
- else
- halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true,
- 0x8);
-
- /* fw dac swing level */
- halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- /* sw mechanism */
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if (BTC_RSSI_HIGH(wifi_rssi_state)) {
- halbtc8812a2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8812a2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- } else {
- if (BTC_RSSI_HIGH(wifi_rssi_state)) {
- halbtc8812a2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8812a2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- }
-}
-
-void halbtc8812a2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH,
- bt_rssi_state = BTC_RSSI_STATE_HIGH;
- u32 wifi_bw;
- u8 bt_thresh0 = 0, bt_thresh1 = 0;
- boolean ap_enable = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
- &ap_enable);
-
- halbtc8812a2ant_get_bt_rssi_threshold(btcoexist, &bt_thresh0,
- &bt_thresh1);
- bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, bt_thresh0,
- bt_thresh1);
-
- wifi_rssi_state = halbtc8812a2ant_wifi_rssi_state(btcoexist, 0, 2, 34,
- 0);
- /* bt_rssi_state = halbtc8812a2ant_bt_rssi_state(3, 34, 42); */
-
- /* power save state */
- if ((ap_enable == true) || (BTC_RSSI_HIGH(wifi_rssi_state) &&
- (!BTC_RSSI_LOW(bt_rssi_state))))
- halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- true, 0x0, 0x0);
- else if (BTC_RSSI_LOW(wifi_rssi_state) &&
- (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- true, 0x0, 0x0);
- else
- halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, true,
- 0x50, 0x4);
-
- /* coex table */
- if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
- else if (BTC_RSSI_LOW(wifi_rssi_state) &&
- (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
- else
- halbtc8812a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- /* pstdma */
- if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_tdma_duration_adjust(btcoexist, true, false, 2);
- else if (BTC_RSSI_LOW(wifi_rssi_state) &&
- (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_tdma_duration_adjust(btcoexist, true, true, 2);
- else {
- coex_dm->auto_tdma_adjust = false;
- halbtc8812a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 82);
- }
-
- /* decrease BT power */
- if (BTC_RSSI_LOW(bt_rssi_state))
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
- else if (BTC_RSSI_MEDIUM(bt_rssi_state))
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- else
- halbtc8812a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
-
- /* limited Rx */
- if (BTC_RSSI_HIGH(wifi_rssi_state) && (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
- 0x8);
- else if (BTC_RSSI_LOW(wifi_rssi_state) &&
- (!BTC_RSSI_LOW(bt_rssi_state)))
- halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
- 0x8);
- else
- halbtc8812a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true,
- 0x8);
-
- /* fw dac swing level */
- halbtc8812a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- /* sw mechanism */
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if (BTC_RSSI_HIGH(wifi_rssi_state)) {
- halbtc8812a2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8812a2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- } else {
- if (BTC_RSSI_HIGH(wifi_rssi_state)) {
- halbtc8812a2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8812a2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8812a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- }
-}
-
-
-void halbtc8812a2ant_coex_under_5g(IN struct btc_coexist *btcoexist)
-{
- halbtc8812a2ant_coex_all_off(btcoexist);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Under 5G, force set BT to ignore Wlan active!!\n");
- BTC_TRACE(trace_buf);
- halbtc8812a2ant_ignore_wlan_act(btcoexist, NORMAL_EXEC, true);
-}
-/* **************************************************** */
-void halbtc8812a2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist)
-{
- boolean wifi_under_5g = false;
- u8 algorithm = 0;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism()===>\n");
- BTC_TRACE(trace_buf);
-
- if (btcoexist->manual_control) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- if (btcoexist->stop_coex_dm) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- if (coex_sta->under_ips) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], wifi is under IPS !!!\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
- if (wifi_under_5g) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism(), run 5G coex setting!!<===\n");
- BTC_TRACE(trace_buf);
- halbtc8812a2ant_coex_under_5g(btcoexist);
- return;
- }
-
-
- algorithm = halbtc8812a2ant_action_algorithm(btcoexist);
- if (coex_sta->c2h_bt_inquiry_page &&
- (BT_8812A_2ANT_COEX_ALGO_PANHS != algorithm)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is under inquiry/page scan !!\n");
- BTC_TRACE(trace_buf);
- halbtc8812a2ant_action_bt_inquiry(btcoexist);
- return;
- }
-
- coex_dm->cur_algorithm = algorithm;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Algorithm = %d\n",
- coex_dm->cur_algorithm);
- BTC_TRACE(trace_buf);
-
- if (halbtc8812a2ant_is_common_action(btcoexist)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant common.\n");
- BTC_TRACE(trace_buf);
- coex_dm->auto_tdma_adjust = false;
- coex_dm->auto_tdma_adjust_low_rssi = false;
- } else {
- if (coex_dm->cur_algorithm != coex_dm->pre_algorithm) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], pre_algorithm=%d, cur_algorithm=%d\n",
- coex_dm->pre_algorithm, coex_dm->cur_algorithm);
- BTC_TRACE(trace_buf);
- coex_dm->auto_tdma_adjust = false;
- coex_dm->auto_tdma_adjust_low_rssi = false;
- }
- switch (coex_dm->cur_algorithm) {
- case BT_8812A_2ANT_COEX_ALGO_SCO:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = SCO.\n");
- BTC_TRACE(trace_buf);
- halbtc8812a2ant_action_sco(btcoexist);
- break;
- case BT_8812A_2ANT_COEX_ALGO_SCO_HID:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = SCO+HID.\n");
- BTC_TRACE(trace_buf);
- halbtc8812a2ant_action_sco_hid(btcoexist);
- break;
- case BT_8812A_2ANT_COEX_ALGO_HID:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = HID.\n");
- BTC_TRACE(trace_buf);
- halbtc8812a2ant_action_hid(btcoexist);
- break;
- case BT_8812A_2ANT_COEX_ALGO_A2DP:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = A2DP.\n");
- BTC_TRACE(trace_buf);
- halbtc8812a2ant_action_a2dp(btcoexist);
- break;
- case BT_8812A_2ANT_COEX_ALGO_A2DP_PANHS:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n");
- BTC_TRACE(trace_buf);
- halbtc8812a2ant_action_a2dp_pan_hs(btcoexist);
- break;
- case BT_8812A_2ANT_COEX_ALGO_PANEDR:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n");
- BTC_TRACE(trace_buf);
- halbtc8812a2ant_action_pan_edr(btcoexist);
- break;
- case BT_8812A_2ANT_COEX_ALGO_PANHS:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = HS mode.\n");
- BTC_TRACE(trace_buf);
- halbtc8812a2ant_action_pan_hs(btcoexist);
- break;
- case BT_8812A_2ANT_COEX_ALGO_PANEDR_A2DP:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n");
- BTC_TRACE(trace_buf);
- halbtc8812a2ant_action_pan_edr_a2dp(btcoexist);
- break;
- case BT_8812A_2ANT_COEX_ALGO_PANEDR_HID:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n");
- BTC_TRACE(trace_buf);
- halbtc8812a2ant_action_pan_edr_hid(btcoexist);
- break;
- case BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANEDR:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n");
- BTC_TRACE(trace_buf);
- halbtc8812a2ant_action_hid_a2dp_pan_edr(
- btcoexist);
- break;
- case BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANHS:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN(HS).\n");
- BTC_TRACE(trace_buf);
- halbtc8812a2ant_action_hid_a2dp_pan_hs(
- btcoexist);
- break;
- case BT_8812A_2ANT_COEX_ALGO_HID_A2DP:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n");
- BTC_TRACE(trace_buf);
- halbtc8812a2ant_action_hid_a2dp(btcoexist);
- break;
- default:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n");
- BTC_TRACE(trace_buf);
- halbtc8812a2ant_coex_all_off(btcoexist);
- break;
- }
- coex_dm->pre_algorithm = coex_dm->cur_algorithm;
- }
-
-}
-
-void halbtc8812a2ant_init_hw_config(IN struct btc_coexist *btcoexist,
- IN boolean back_up)
-{
- u8 u8tmp = 0;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], 2Ant Init HW Config!!\n");
- BTC_TRACE(trace_buf);
-
- if (back_up) {
- /* backup rf 0x1e value */
- coex_dm->bt_rf_0x1e_backup =
- btcoexist->btc_get_rf_reg(btcoexist, BTC_RF_A, 0x1e,
- 0xfffff);
-
- coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist,
- 0x430);
- coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist,
- 0x434);
- coex_dm->backup_retry_limit = btcoexist->btc_read_2byte(
- btcoexist, 0x42a);
- coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte(
- btcoexist, 0x456);
- }
-
- /* ant sw control to BT */
- halbtc8812a2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_CPL_AUX, true,
- false);
-
- /* 0x790[5:0]=0x5 */
- u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790);
- u8tmp &= 0xc0;
- u8tmp |= 0x5;
- btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp);
-
- /* PTA parameter */
- btcoexist->btc_write_1byte(btcoexist, 0x6cc, 0x0);
- btcoexist->btc_write_4byte(btcoexist, 0x6c8, 0xffff);
- btcoexist->btc_write_4byte(btcoexist, 0x6c4, 0x55555555);
- btcoexist->btc_write_4byte(btcoexist, 0x6c0, 0x55555555);
-
- /* coex parameters */
- btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1);
-
- /* enable counter statistics */
- btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4);
-
- /* enable PTA */
- btcoexist->btc_write_1byte(btcoexist, 0x40, 0x20);
-
- /* bt clock related */
- u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x4);
- u8tmp |= BIT(7);
- btcoexist->btc_write_1byte(btcoexist, 0x4, u8tmp);
-
- /* bt clock related */
- u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x7);
- u8tmp |= BIT(1);
- btcoexist->btc_write_1byte(btcoexist, 0x7, u8tmp);
-}
-
-/* ************************************************************
- * work around function start with wa_halbtc8812a2ant_
- * ************************************************************
- * ************************************************************
- * extern function start with ex_halbtc8812a2ant_
- * ************************************************************ */
-void ex_halbtc8812a2ant_power_on_setting(IN struct btc_coexist *btcoexist)
-{
-}
-
-void ex_halbtc8812a2ant_init_hw_config(IN struct btc_coexist *btcoexist,
- IN boolean wifi_only)
-{
- halbtc8812a2ant_init_hw_config(btcoexist, true);
- btcoexist->stop_coex_dm = false;
-}
-
-void ex_halbtc8812a2ant_init_coex_dm(IN struct btc_coexist *btcoexist)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Coex Mechanism Init!!\n");
- BTC_TRACE(trace_buf);
- btcoexist->stop_coex_dm = false;
- halbtc8812a2ant_init_coex_dm(btcoexist);
-}
-
-void ex_halbtc8812a2ant_display_coex_info(IN struct btc_coexist *btcoexist)
-{
- struct btc_board_info *board_info = &btcoexist->board_info;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- u8 *cli_buf = btcoexist->cli_buf;
- u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0;
- u16 u16tmp[4];
- u32 u32tmp[4];
- u32 fw_ver = 0, bt_patch_ver = 0;
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ============[BT Coexist info]============");
- CL_PRINTF(cli_buf);
-
- if (btcoexist->manual_control) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ============[Under Manual Control]============");
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ==========================================");
- CL_PRINTF(cli_buf);
- }
-
- if (btcoexist->stop_coex_dm) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ============[Coex is STOPPED]============");
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ==========================================");
- CL_PRINTF(cli_buf);
- }
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ",
- "Ant PG number/ Ant mechanism:",
- board_info->pg_ant_num, board_info->btdm_ant_num);
- CL_PRINTF(cli_buf);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %d_%d/ 0x%x/ 0x%x(%d)",
- "CoexVer/ FwVer/ PatchVer",
- glcoex_ver_date_8812a_2ant, glcoex_ver_8812a_2ant, fw_ver,
- bt_patch_ver, bt_patch_ver);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ",
- "Wifi channel informed to BT",
- coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
- coex_dm->wifi_chnl_info[2]);
- CL_PRINTF(cli_buf);
-
- /* wifi status */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Wifi Status]============");
- CL_PRINTF(cli_buf);
- btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[BT Status]============");
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ",
- "BT [status/ rssi/ retryCnt]",
- ((coex_sta->bt_disabled) ? ("disabled") : ((
- coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan")
- : ((BT_8812A_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
- coex_dm->bt_status) ? "non-connected idle" :
- ((BT_8812A_2ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)
- ? "connected-idle" : "busy")))),
- coex_sta->bt_rssi, coex_sta->bt_retry_cnt);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d",
- "SCO/HID/PAN/A2DP",
- bt_link_info->sco_exist, bt_link_info->hid_exist,
- bt_link_info->pan_exist, bt_link_info->a2dp_exist);
- CL_PRINTF(cli_buf);
- btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_BT_LINK_INFO);
-
- bt_info_ext = coex_sta->bt_info_ext;
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
- "BT Info A2DP rate",
- (bt_info_ext & BIT(0)) ? "Basic rate" : "EDR rate");
- CL_PRINTF(cli_buf);
-
- for (i = 0; i < BT_INFO_SRC_8812A_2ANT_MAX; i++) {
- if (coex_sta->bt_info_c2h_cnt[i]) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)",
- glbt_info_src_8812a_2ant[i],
- coex_sta->bt_info_c2h[i][0],
- coex_sta->bt_info_c2h[i][1],
- coex_sta->bt_info_c2h[i][2],
- coex_sta->bt_info_c2h[i][3],
- coex_sta->bt_info_c2h[i][4],
- coex_sta->bt_info_c2h[i][5],
- coex_sta->bt_info_c2h[i][6],
- coex_sta->bt_info_c2h_cnt[i]);
- CL_PRINTF(cli_buf);
- }
- }
-
- /* Sw mechanism */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Sw mechanism]============");
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ",
- "SM1[ShRf/ LpRA/ LimDig]",
- coex_dm->cur_rf_rx_lpf_shrink, coex_dm->cur_low_penalty_ra,
- coex_dm->limited_dig);
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ",
- "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]",
- coex_dm->cur_agc_table_en, coex_dm->cur_adc_back_off,
- coex_dm->cur_dac_swing_on, coex_dm->cur_dac_swing_lvl);
- CL_PRINTF(cli_buf);
-
- /* Fw mechanism */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Fw mechanism]============");
- CL_PRINTF(cli_buf);
-
- ps_tdma_case = coex_dm->cur_ps_tdma;
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (auto:%d/%d)",
- "PS TDMA",
- coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],
- coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],
- coex_dm->ps_tdma_para[4],
- ps_tdma_case, coex_dm->auto_tdma_adjust,
- coex_dm->auto_tdma_adjust_low_rssi);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ",
- "DecBtPwr/ IgnWlanAct",
- coex_dm->cur_bt_dec_pwr_lvl, coex_dm->cur_ignore_wlan_act);
- CL_PRINTF(cli_buf);
-
- /* Hw setting */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Hw setting]============");
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x",
- "RF-A, 0x1e initVal",
- coex_dm->bt_rf_0x1e_backup);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x",
- "backup ARFR1/ARFR2/RL/AMaxTime",
- coex_dm->backup_arfr_cnt1, coex_dm->backup_arfr_cnt2,
- coex_dm->backup_retry_limit,
- coex_dm->backup_ampdu_max_time);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434);
- u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x",
- "0x430/0x434/0x42a/0x456",
- u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]);
- CL_PRINTF(cli_buf);
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x6cc);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x ",
- "0x778 (W_Act)/ 0x6cc (CoTab Sel)",
- u8tmp[0], u8tmp[1]);
- CL_PRINTF(cli_buf);
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x8db);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xc5b);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
- "0x8db(ADC)/0xc5b[29:25](DAC)",
- ((u8tmp[0] & 0x60) >> 5), ((u8tmp[1] & 0x3e) >> 1));
- CL_PRINTF(cli_buf);
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xcb3);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xcb7);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
- "0xcb3/ 0xcb7",
- u8tmp[0], u8tmp[1]);
- CL_PRINTF(cli_buf);
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x40);
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x974);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
- "0x40/ 0x4c[24:23]/ 0x974",
- u8tmp[0], ((u32tmp[0] & 0x01800000) >> 23), u32tmp[1]);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
- "0x550(bcn ctrl)/0x522",
- u32tmp[0], u8tmp[0]);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xa0a);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
- "0xc50(DIG)/0xa0a(CCK-TH)",
- u32tmp[0], u8tmp[0]);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xf48);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xa5b);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xa5c);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
- "0xf48/ 0xa5b (FA cnt-- OFDM : CCK)",
- u32tmp[0], (u8tmp[0] << 8) + u8tmp[1]);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
- u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x6cc);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
- "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)",
- u32tmp[0], u32tmp[1], u32tmp[2], u8tmp[0]);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
- "0x770(high-pri rx/tx)",
- coex_sta->high_priority_rx, coex_sta->high_priority_tx);
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
- "0x774(low-pri rx/tx)",
- coex_sta->low_priority_rx, coex_sta->low_priority_tx);
- CL_PRINTF(cli_buf);
-#if (BT_AUTO_REPORT_ONLY_8812A_2ANT == 1)
- halbtc8812a2ant_monitor_bt_ctr(btcoexist);
-#endif
- btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
-}
-
-
-void ex_halbtc8812a2ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type)
-{
- boolean wifi_under_5g = false;
-
- if (btcoexist->manual_control || btcoexist->stop_coex_dm)
- return;
-
- if (BTC_IPS_ENTER == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], IPS ENTER notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_ips = true;
- halbtc8812a2ant_coex_all_off(btcoexist);
- halbtc8812a2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_CPL_AUX,
- false, true);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], IPS notify, force set BT to ignore Wlan active!!\n");
- BTC_TRACE(trace_buf);
- halbtc8812a2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
- ex_halbtc8812a2ant_media_status_notify(btcoexist,
- BTC_MEDIA_DISCONNECT);
- } else if (BTC_IPS_LEAVE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], IPS LEAVE notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_ips = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G,
- &wifi_under_5g);
- if (!wifi_under_5g) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], IPS notify, force set BT NOT to ignore Wlan active!!\n");
- BTC_TRACE(trace_buf);
- halbtc8812a2ant_ignore_wlan_act(btcoexist, FORCE_EXEC,
- false);
- }
- }
-}
-
-void ex_halbtc8812a2ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type)
-{
-
- if (btcoexist->manual_control || btcoexist->stop_coex_dm)
- return;
-
- if (BTC_LPS_ENABLE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], LPS ENABLE notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_lps = true;
- } else if (BTC_LPS_DISABLE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], LPS DISABLE notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_lps = false;
- }
-}
-
-void ex_halbtc8812a2ant_scan_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- if (BTC_SCAN_START == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCAN START notify\n");
- BTC_TRACE(trace_buf);
- } else if (BTC_SCAN_FINISH == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCAN FINISH notify\n");
- BTC_TRACE(trace_buf);
- }
-}
-
-void ex_halbtc8812a2ant_connect_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- if (BTC_ASSOCIATE_START == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CONNECT START notify\n");
- BTC_TRACE(trace_buf);
- } else if (BTC_ASSOCIATE_FINISH == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CONNECT FINISH notify\n");
- BTC_TRACE(trace_buf);
- }
-}
-
-void ex_halbtc8812a2ant_media_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- u8 data_len = 5;
- u8 buf[6] = {0};
- u8 h2c_parameter[3] = {0};
- u32 wifi_bw;
- u8 wifi_central_chnl;
-
- if (btcoexist->manual_control ||
- btcoexist->stop_coex_dm ||
- coex_sta->bt_disabled)
- return;
-
- if (BTC_MEDIA_CONNECT == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], MEDIA connect notify\n");
- BTC_TRACE(trace_buf);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], MEDIA disconnect notify\n");
- BTC_TRACE(trace_buf);
- }
-
- /* only 2.4G we need to inform bt the chnl mask */
- btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
- &wifi_central_chnl);
- if ((BTC_MEDIA_CONNECT == type) &&
- (wifi_central_chnl <= 14)) {
- h2c_parameter[0] = 0x1;
- h2c_parameter[1] = wifi_central_chnl;
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- if (BTC_WIFI_BW_HT40 == wifi_bw)
- h2c_parameter[2] = 0x30;
- else
- h2c_parameter[2] = 0x20;
- }
-
- coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
- coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
- coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
-
- buf[0] = data_len;
- buf[1] = 0x5; /* OP_Code */
- buf[2] = 0x3; /* OP_Code_Length */
- buf[3] = h2c_parameter[0]; /* OP_Code_Content */
- buf[4] = h2c_parameter[1];
- buf[5] = h2c_parameter[2];
-
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_COEX,
- (void *)&buf[0]);
-}
-
-void ex_halbtc8812a2ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- if (type == BTC_PACKET_DHCP) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], DHCP Packet notify\n");
- BTC_TRACE(trace_buf);
- }
-
-}
-
-void ex_halbtc8812a2ant_bt_info_notify(IN struct btc_coexist *btcoexist,
- IN u8 *tmp_buf, IN u8 length)
-{
- u8 bt_info = 0;
- u8 i, rsp_source = 0;
- boolean bt_busy = false, limited_dig = false;
- boolean wifi_connected = false, wifi_under_5g = false;
-
- coex_sta->c2h_bt_info_req_sent = false;
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
-
- rsp_source = tmp_buf[0] & 0xf;
- if (rsp_source >= BT_INFO_SRC_8812A_2ANT_MAX)
- rsp_source = BT_INFO_SRC_8812A_2ANT_WIFI_FW;
- coex_sta->bt_info_c2h_cnt[rsp_source]++;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source,
- length);
- BTC_TRACE(trace_buf);
- for (i = 0; i < length; i++) {
- coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
- if (i == 1)
- bt_info = tmp_buf[i];
- if (i == length - 1) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n",
- tmp_buf[i]);
- BTC_TRACE(trace_buf);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ",
- tmp_buf[i]);
- BTC_TRACE(trace_buf);
- }
- }
-
- if (BT_INFO_SRC_8812A_2ANT_WIFI_FW != rsp_source) {
- coex_sta->bt_retry_cnt = /* [3:0] */
- coex_sta->bt_info_c2h[rsp_source][2] & 0xf;
-
- coex_sta->bt_rssi =
- coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10;
-
- coex_sta->bt_info_ext =
- coex_sta->bt_info_c2h[rsp_source][4];
-
- /* Here we need to resend some wifi info to BT */
- /* because bt is reset and loss of the info. */
- if ((coex_sta->bt_info_ext & BIT(1))) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- if (wifi_connected)
- ex_halbtc8812a2ant_media_status_notify(
- btcoexist, BTC_MEDIA_CONNECT);
- else
- ex_halbtc8812a2ant_media_status_notify(
- btcoexist, BTC_MEDIA_DISCONNECT);
- }
-
- if ((coex_sta->bt_info_ext & BIT(3)) && !wifi_under_5g) {
- /* BT already ignored WlanAct */
- if (!btcoexist->manual_control &&
- !btcoexist->stop_coex_dm) {
- if (!coex_sta->under_ips) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n");
- BTC_TRACE(trace_buf);
- halbtc8812a2ant_ignore_wlan_act(
- btcoexist, FORCE_EXEC, false);
- }
- }
- } else {
- /* BT already NOT ignore Wlan active, do nothing here. */
-
- if (coex_sta->under_ips) {
- /* work around for 8812a combo hw bug => when IPS, wlanAct is always high. */
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], wifi is under IPS, set BT to ignore Wlan active!!\n");
- BTC_TRACE(trace_buf);
- halbtc8812a2ant_ignore_wlan_act(btcoexist,
- FORCE_EXEC, true);
- }
- }
- }
-
- /* check BIT2 first ==> check if bt is under inquiry or page scan */
- if (bt_info & BT_INFO_8812A_2ANT_B_INQ_PAGE)
- coex_sta->c2h_bt_inquiry_page = true;
- else
- coex_sta->c2h_bt_inquiry_page = false;
-
- /* set link exist status */
- if (!(bt_info & BT_INFO_8812A_2ANT_B_CONNECTION)) {
- coex_sta->bt_link_exist = false;
- coex_sta->pan_exist = false;
- coex_sta->a2dp_exist = false;
- coex_sta->hid_exist = false;
- coex_sta->sco_exist = false;
- coex_sta->acl_busy = false;
- } else { /* connection exists */
- coex_sta->bt_link_exist = true;
- if (bt_info & BT_INFO_8812A_2ANT_B_FTP)
- coex_sta->pan_exist = true;
- else
- coex_sta->pan_exist = false;
- if (bt_info & BT_INFO_8812A_2ANT_B_A2DP)
- coex_sta->a2dp_exist = true;
- else
- coex_sta->a2dp_exist = false;
- if (bt_info & BT_INFO_8812A_2ANT_B_HID)
- coex_sta->hid_exist = true;
- else
- coex_sta->hid_exist = false;
- if (bt_info & BT_INFO_8812A_2ANT_B_SCO_ESCO)
- coex_sta->sco_exist = true;
- else
- coex_sta->sco_exist = false;
- if (bt_info & BT_INFO_8812A_2ANT_B_ACL_BUSY)
- coex_sta->acl_busy = true;
- else
- coex_sta->acl_busy = false;
-
- }
-
- halbtc8812a2ant_update_bt_link_info(btcoexist);
-
- if (!(bt_info & BT_INFO_8812A_2ANT_B_CONNECTION)) {
- coex_dm->bt_status = BT_8812A_2ANT_BT_STATUS_NON_CONNECTED_IDLE;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n");
- BTC_TRACE(trace_buf);
- } else if (bt_info ==
- BT_INFO_8812A_2ANT_B_CONNECTION) { /* connection exists but no busy */
- coex_dm->bt_status = BT_8812A_2ANT_BT_STATUS_CONNECTED_IDLE;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n");
- BTC_TRACE(trace_buf);
- } else if ((bt_info & BT_INFO_8812A_2ANT_B_SCO_ESCO) ||
- (bt_info & BT_INFO_8812A_2ANT_B_SCO_BUSY)) {
- coex_dm->bt_status = BT_8812A_2ANT_BT_STATUS_SCO_BUSY;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n");
- BTC_TRACE(trace_buf);
- } else if (bt_info & BT_INFO_8812A_2ANT_B_ACL_BUSY) {
- coex_dm->bt_status = BT_8812A_2ANT_BT_STATUS_ACL_BUSY;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n");
- BTC_TRACE(trace_buf);
- } else {
- coex_dm->bt_status = BT_8812A_2ANT_BT_STATUS_MAX;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n");
- BTC_TRACE(trace_buf);
- }
-
- if ((BT_8812A_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
- (BT_8812A_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
- (BT_8812A_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) {
- bt_busy = true;
- if (!wifi_under_5g)
- limited_dig = true;
- } else {
- bt_busy = false;
- limited_dig = false;
- }
-
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
-
- coex_dm->limited_dig = limited_dig;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_LIMITED_DIG, &limited_dig);
-
- halbtc8812a2ant_run_coexist_mechanism(btcoexist);
-}
-
-void ex_halbtc8812a2ant_rf_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n");
- BTC_TRACE(trace_buf);
-
- if (BTC_RF_ON == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RF is turned ON!!\n");
- BTC_TRACE(trace_buf);
- btcoexist->stop_coex_dm = false;
- }
- if (BTC_RF_OFF == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RF is turned OFF!!\n");
- BTC_TRACE(trace_buf);
-
- halbtc8812a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- true, 0x0, 0x0);
- halbtc8812a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 1);
- /* halbtc8812a2ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, FORCE_EXEC, false, true); */
- halbtc8812a2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
- btcoexist->stop_coex_dm = true;
-
- }
-}
-
-
-void ex_halbtc8812a2ant_halt_notify(IN struct btc_coexist *btcoexist)
-{
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n");
- BTC_TRACE(trace_buf);
-
- halbtc8812a2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_CPL_AUX, false,
- true);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Halt notify, force set BT to ignore Wlan active!!\n");
- BTC_TRACE(trace_buf);
- halbtc8812a2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
- ex_halbtc8812a2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
-
- /* 0x522=0xff, pause tx */
- btcoexist->btc_write_1byte(btcoexist, 0x522, 0xff);
- /* 0x40[7:6]=2'b01, modify BT mode. */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0xc0, 0x2);
- btcoexist->stop_coex_dm = true;
-}
-
-void ex_halbtc8812a2ant_periodical(IN struct btc_coexist *btcoexist)
-{
-#if (BT_AUTO_REPORT_ONLY_8812A_2ANT == 0)
- halbtc8812a2ant_query_bt_info(btcoexist);
- halbtc8812a2ant_monitor_bt_ctr(btcoexist);
- halbtc8812a2ant_monitor_bt_enable_disable(btcoexist);
-#else
- if (halbtc8812a2ant_is_wifi_status_changed(btcoexist) ||
- coex_dm->auto_tdma_adjust ||
- coex_dm->auto_tdma_adjust_low_rssi)
- halbtc8812a2ant_run_coexist_mechanism(btcoexist);
-#endif
-}
-
-void ex_halbtc8812a2ant_dbg_control(IN struct btc_coexist *btcoexist,
- IN u8 op_code, IN u8 op_len, IN u8 *pdata)
-{
- switch (op_code) {
- case BTC_DBG_SET_COEX_DEC_BT_PWR:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Set Dec BT power\n");
- BTC_TRACE(trace_buf);
- {
- u8 data_len = 4;
- u8 buf[6] = {0};
- u8 dec_bt_pwr = 0, pwr_level = 0;
- if (op_len == 2) {
- dec_bt_pwr = pdata[0];
- pwr_level = pdata[1];
-
- buf[0] = data_len;
- buf[1] = 0x3; /* OP_Code */
- buf[2] = 0x2; /* OP_Code_Length */
-
- buf[3] = dec_bt_pwr; /* OP_Code_Content */
- buf[4] = pwr_level;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Set Dec BT power=%d, pwr_level=%d\n",
- dec_bt_pwr, pwr_level);
- BTC_TRACE(trace_buf);
- btcoexist->btc_set(btcoexist,
- BTC_SET_ACT_CTRL_BT_COEX,
- (void *)&buf[0]);
- }
- }
- break;
-
- case BTC_DBG_SET_COEX_BT_AFH_MAP:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Set BT AFH Map\n");
- BTC_TRACE(trace_buf);
- {
- u8 data_len = 5;
- u8 buf[6] = {0};
- if (op_len == 3) {
- buf[0] = data_len;
- buf[1] = 0x5; /* OP_Code */
- buf[2] = 0x3; /* OP_Code_Length */
-
- buf[3] = pdata[0]; /* OP_Code_Content */
- buf[4] = pdata[1];
- buf[5] = pdata[2];
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Set BT AFH Map = %02x %02x %02x\n",
- pdata[0], pdata[1], pdata[2]);
- BTC_TRACE(trace_buf);
- btcoexist->btc_set(btcoexist,
- BTC_SET_ACT_CTRL_BT_COEX,
- (void *)&buf[0]);
- }
- }
- break;
-
- case BTC_DBG_SET_COEX_BT_IGNORE_WLAN_ACT:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Set BT Ignore Wlan Active\n");
- BTC_TRACE(trace_buf);
- {
- u8 data_len = 3;
- u8 buf[6] = {0};
- if (op_len == 1) {
- buf[0] = data_len;
- buf[1] = 0x1; /* OP_Code */
- buf[2] = 0x1; /* OP_Code_Length */
-
- buf[3] = pdata[0]; /* OP_Code_Content */
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Set BT Ignore Wlan Active = 0x%x\n",
- pdata[0]);
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_set(btcoexist,
- BTC_SET_ACT_CTRL_BT_COEX,
- (void *)&buf[0]);
- }
- }
- break;
-
- default:
- break;
- }
-}
-
-#endif
-
-#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */
\ No newline at end of file
diff --git a/hal/btc/HalBtc8812a2Ant.h b/hal/btc/HalBtc8812a2Ant.h
deleted file mode 100644
index be08dd3..0000000
--- a/hal/btc/HalBtc8812a2Ant.h
+++ /dev/null
@@ -1,202 +0,0 @@
-
-#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
-
-#if (RTL8812A_SUPPORT == 1)
-
-/* *******************************************
- * The following is for 8812A 2Ant BT Co-exist definition
- * ******************************************* */
-#define BT_AUTO_REPORT_ONLY_8812A_2ANT 0
-
-#define BT_INFO_8812A_2ANT_B_FTP BIT(7)
-#define BT_INFO_8812A_2ANT_B_A2DP BIT(6)
-#define BT_INFO_8812A_2ANT_B_HID BIT(5)
-#define BT_INFO_8812A_2ANT_B_SCO_BUSY BIT(4)
-#define BT_INFO_8812A_2ANT_B_ACL_BUSY BIT(3)
-#define BT_INFO_8812A_2ANT_B_INQ_PAGE BIT(2)
-#define BT_INFO_8812A_2ANT_B_SCO_ESCO BIT(1)
-#define BT_INFO_8812A_2ANT_B_CONNECTION BIT(0)
-
-#define BT_INFO_8812A_2ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \
- (((_BT_INFO_EXT_&BIT(0))) ? true : false)
-
-#define BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT 2
-
-enum bt_info_src_8812a_2ant {
- BT_INFO_SRC_8812A_2ANT_WIFI_FW = 0x0,
- BT_INFO_SRC_8812A_2ANT_BT_RSP = 0x1,
- BT_INFO_SRC_8812A_2ANT_BT_ACTIVE_SEND = 0x2,
- BT_INFO_SRC_8812A_2ANT_MAX
-};
-
-enum bt_8812a_2ant_bt_status {
- BT_8812A_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
- BT_8812A_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
- BT_8812A_2ANT_BT_STATUS_INQ_PAGE = 0x2,
- BT_8812A_2ANT_BT_STATUS_ACL_BUSY = 0x3,
- BT_8812A_2ANT_BT_STATUS_SCO_BUSY = 0x4,
- BT_8812A_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
- BT_8812A_2ANT_BT_STATUS_MAX
-};
-
-enum bt_8812a_2ant_coex_algo {
- BT_8812A_2ANT_COEX_ALGO_UNDEFINED = 0x0,
- BT_8812A_2ANT_COEX_ALGO_SCO = 0x1,
- BT_8812A_2ANT_COEX_ALGO_SCO_HID = 0x2,
- BT_8812A_2ANT_COEX_ALGO_HID = 0x3,
- BT_8812A_2ANT_COEX_ALGO_A2DP = 0x4,
- BT_8812A_2ANT_COEX_ALGO_A2DP_PANHS = 0x5,
- BT_8812A_2ANT_COEX_ALGO_PANEDR = 0x6,
- BT_8812A_2ANT_COEX_ALGO_PANHS = 0x7,
- BT_8812A_2ANT_COEX_ALGO_PANEDR_A2DP = 0x8,
- BT_8812A_2ANT_COEX_ALGO_PANEDR_HID = 0x9,
- BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0xa,
- BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANHS = 0xb,
- BT_8812A_2ANT_COEX_ALGO_HID_A2DP = 0xc,
- BT_8812A_2ANT_COEX_ALGO_MAX = 0xd
-};
-
-struct coex_dm_8812a_2ant {
- /* fw mechanism */
- u8 pre_bt_dec_pwr_lvl;
- u8 cur_bt_dec_pwr_lvl;
- u8 pre_fw_dac_swing_lvl;
- u8 cur_fw_dac_swing_lvl;
- boolean cur_ignore_wlan_act;
- boolean pre_ignore_wlan_act;
- u8 pre_ps_tdma;
- u8 cur_ps_tdma;
- u8 ps_tdma_para[5];
- u8 ps_tdma_du_adj_type;
- boolean auto_tdma_adjust;
- boolean auto_tdma_adjust_low_rssi;
- boolean pre_ps_tdma_on;
- boolean cur_ps_tdma_on;
- boolean pre_bt_auto_report;
- boolean cur_bt_auto_report;
- u8 pre_lps;
- u8 cur_lps;
- u8 pre_rpwm;
- u8 cur_rpwm;
-
- /* sw mechanism */
- boolean pre_rf_rx_lpf_shrink;
- boolean cur_rf_rx_lpf_shrink;
- u32 bt_rf_0x1e_backup;
- boolean pre_low_penalty_ra;
- boolean cur_low_penalty_ra;
- boolean pre_dac_swing_on;
- u32 pre_dac_swing_lvl;
- boolean cur_dac_swing_on;
- u32 cur_dac_swing_lvl;
- boolean pre_adc_back_off;
- boolean cur_adc_back_off;
- boolean pre_agc_table_en;
- boolean cur_agc_table_en;
- u32 pre_val0x6c0;
- u32 cur_val0x6c0;
- u32 pre_val0x6c4;
- u32 cur_val0x6c4;
- u32 pre_val0x6c8;
- u32 cur_val0x6c8;
- u8 pre_val0x6cc;
- u8 cur_val0x6cc;
- boolean limited_dig;
- u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */
- u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */
- u16 backup_retry_limit;
- u8 backup_ampdu_max_time;
-
- /* algorithm related */
- u8 pre_algorithm;
- u8 cur_algorithm;
- u8 bt_status;
- u8 wifi_chnl_info[3];
-
- u32 pre_ra_mask;
- u32 cur_ra_mask;
- u8 cur_ra_mask_type;
- u8 pre_arfr_type;
- u8 cur_arfr_type;
- u8 pre_retry_limit_type;
- u8 cur_retry_limit_type;
- u8 pre_ampdu_time_type;
- u8 cur_ampdu_time_type;
-};
-
-struct coex_sta_8812a_2ant {
- boolean bt_disabled;
- boolean bt_link_exist;
- boolean sco_exist;
- boolean a2dp_exist;
- boolean hid_exist;
- boolean pan_exist;
- boolean acl_busy;
-
- boolean under_lps;
- boolean under_ips;
- u32 high_priority_tx;
- u32 high_priority_rx;
- u32 low_priority_tx;
- u32 low_priority_rx;
- u8 bt_rssi;
- u8 pre_bt_rssi_state;
- u8 pre_wifi_rssi_state[4];
- boolean c2h_bt_info_req_sent;
- u8 bt_info_c2h[BT_INFO_SRC_8812A_2ANT_MAX][10];
- u32 bt_info_c2h_cnt[BT_INFO_SRC_8812A_2ANT_MAX];
- u32 bt_info_query_cnt;
- boolean c2h_bt_inquiry_page;
- u8 bt_retry_cnt;
- u8 bt_info_ext;
-};
-
-/* *******************************************
- * The following is interface which will notify coex module.
- * ******************************************* */
-void ex_halbtc8812a2ant_power_on_setting(IN struct btc_coexist *btcoexist);
-void ex_halbtc8812a2ant_init_hw_config(IN struct btc_coexist *btcoexist,
- IN boolean wifi_only);
-void ex_halbtc8812a2ant_init_coex_dm(IN struct btc_coexist *btcoexist);
-void ex_halbtc8812a2ant_ips_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8812a2ant_lps_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8812a2ant_scan_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8812a2ant_connect_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8812a2ant_media_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8812a2ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8812a2ant_bt_info_notify(IN struct btc_coexist *btcoexist,
- IN u8 *tmp_buf, IN u8 length);
-void ex_halbtc8812a2ant_rf_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-
-void ex_halbtc8812a2ant_halt_notify(IN struct btc_coexist *btcoexist);
-void ex_halbtc8812a2ant_periodical(IN struct btc_coexist *btcoexist);
-void ex_halbtc8812a2ant_display_coex_info(IN struct btc_coexist *btcoexist);
-void ex_halbtc8812a2ant_dbg_control(IN struct btc_coexist *btcoexist,
- IN u8 op_code, IN u8 op_len, IN u8 *pdata);
-
-#else
-#define ex_halbtc8812a2ant_power_on_setting(btcoexist)
-#define ex_halbtc8812a2ant_init_hw_config(btcoexist, wifi_only)
-#define ex_halbtc8812a2ant_init_coex_dm(btcoexist)
-#define ex_halbtc8812a2ant_ips_notify(btcoexist, type)
-#define ex_halbtc8812a2ant_lps_notify(btcoexist, type)
-#define ex_halbtc8812a2ant_scan_notify(btcoexist, type)
-#define ex_halbtc8812a2ant_connect_notify(btcoexist, type)
-#define ex_halbtc8812a2ant_media_status_notify(btcoexist, type)
-#define ex_halbtc8812a2ant_specific_packet_notify(btcoexist, type)
-#define ex_halbtc8812a2ant_bt_info_notify(btcoexist, tmp_buf, length)
-#define ex_halbtc8812a2ant_rf_status_notify(btcoexist, type)
-#define ex_halbtc8812a2ant_halt_notify(btcoexist)
-#define ex_halbtc8812a2ant_periodical(btcoexist)
-#define ex_halbtc8812a2ant_display_coex_info(btcoexist)
-#define ex_halbtc8812a2ant_dbg_control(btcoexist, op_code, op_len, pdata)
-#endif
-
-#endif
diff --git a/hal/btc/HalBtc8821a1Ant.c b/hal/btc/HalBtc8821a1Ant.c
deleted file mode 100644
index 81ddf03..0000000
--- a/hal/btc/HalBtc8821a1Ant.c
+++ /dev/null
@@ -1,3100 +0,0 @@
-/* ************************************************************
- * Description:
- *
- * This file is for 8821A_1ANT Co-exist mechanism
- *
- * History
- * 2012/11/15 Cosa first check in.
- *
- * ************************************************************
- * SY modify 2015/04/27
- * ************************************************************
- * include files
- * ************************************************************ */
-#include "Mp_Precomp.h"
-
-#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
-
-#if (RTL8821A_SUPPORT == 1)
-/* ************************************************************
- * Global variables, these are static variables
- * ************************************************************ */
-static u8 *trace_buf = &gl_btc_trace_buf[0];
-static struct coex_dm_8821a_1ant glcoex_dm_8821a_1ant;
-static struct coex_dm_8821a_1ant *coex_dm = &glcoex_dm_8821a_1ant;
-static struct coex_sta_8821a_1ant glcoex_sta_8821a_1ant;
-static struct coex_sta_8821a_1ant *coex_sta = &glcoex_sta_8821a_1ant;
-
-const char *const glbt_info_src_8821a_1ant[] = {
- "BT Info[wifi fw]",
- "BT Info[bt rsp]",
- "BT Info[bt auto report]",
-};
-
-u32 glcoex_ver_date_8821a_1ant = 20150615;
-u32 glcoex_ver_8821a_1ant = 0x61;
-
-/* ************************************************************
- * local function proto type if needed
- * ************************************************************
- * ************************************************************
- * local function start with halbtc8821a1ant_
- * ************************************************************ */
-u8 halbtc8821a1ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1)
-{
- s32 bt_rssi = 0;
- u8 bt_rssi_state = coex_sta->pre_bt_rssi_state;
-
- bt_rssi = coex_sta->bt_rssi;
-
- if (level_num == 2) {
- if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
- (coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (bt_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT))
- bt_rssi_state = BTC_RSSI_STATE_HIGH;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else {
- if (bt_rssi < rssi_thresh)
- bt_rssi_state = BTC_RSSI_STATE_LOW;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- } else if (level_num == 3) {
- if (rssi_thresh > rssi_thresh1) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Rssi thresh error!!\n");
- BTC_TRACE(trace_buf);
- return coex_sta->pre_bt_rssi_state;
- }
-
- if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
- (coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (bt_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT))
- bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else if ((coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_MEDIUM) ||
- (coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_STAY_MEDIUM)) {
- if (bt_rssi >= (rssi_thresh1 +
- BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT))
- bt_rssi_state = BTC_RSSI_STATE_HIGH;
- else if (bt_rssi < rssi_thresh)
- bt_rssi_state = BTC_RSSI_STATE_LOW;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
- } else {
- if (bt_rssi < rssi_thresh1)
- bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- }
-
- coex_sta->pre_bt_rssi_state = bt_rssi_state;
-
- return bt_rssi_state;
-}
-
-u8 halbtc8821a1ant_wifi_rssi_state(IN struct btc_coexist *btcoexist,
- IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1)
-{
- s32 wifi_rssi = 0;
- u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index];
-
- btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
-
- if (level_num == 2) {
- if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
- ||
- (coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (wifi_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT))
- wifi_rssi_state = BTC_RSSI_STATE_HIGH;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else {
- if (wifi_rssi < rssi_thresh)
- wifi_rssi_state = BTC_RSSI_STATE_LOW;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- } else if (level_num == 3) {
- if (rssi_thresh > rssi_thresh1) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], wifi RSSI thresh error!!\n");
- BTC_TRACE(trace_buf);
- return coex_sta->pre_wifi_rssi_state[index];
- }
-
- if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
- ||
- (coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (wifi_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT))
- wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else if ((coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_MEDIUM) ||
- (coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_STAY_MEDIUM)) {
- if (wifi_rssi >= (rssi_thresh1 +
- BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT))
- wifi_rssi_state = BTC_RSSI_STATE_HIGH;
- else if (wifi_rssi < rssi_thresh)
- wifi_rssi_state = BTC_RSSI_STATE_LOW;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
- } else {
- if (wifi_rssi < rssi_thresh1)
- wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- }
-
- coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state;
-
- return wifi_rssi_state;
-}
-
-void halbtc8821a1ant_update_ra_mask(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u32 dis_rate_mask)
-{
- coex_dm->cur_ra_mask = dis_rate_mask;
-
- if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask))
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK,
- &coex_dm->cur_ra_mask);
- coex_dm->pre_ra_mask = coex_dm->cur_ra_mask;
-}
-
-void halbtc8821a1ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- boolean wifi_under_b_mode = false;
-
- coex_dm->cur_arfr_type = type;
-
- if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) {
- switch (coex_dm->cur_arfr_type) {
- case 0: /* normal mode */
- btcoexist->btc_write_4byte(btcoexist, 0x430,
- coex_dm->backup_arfr_cnt1);
- btcoexist->btc_write_4byte(btcoexist, 0x434,
- coex_dm->backup_arfr_cnt2);
- break;
- case 1:
- btcoexist->btc_get(btcoexist,
- BTC_GET_BL_WIFI_UNDER_B_MODE,
- &wifi_under_b_mode);
- if (wifi_under_b_mode) {
- btcoexist->btc_write_4byte(btcoexist,
- 0x430, 0x0);
- btcoexist->btc_write_4byte(btcoexist,
- 0x434, 0x01010101);
- } else {
- btcoexist->btc_write_4byte(btcoexist,
- 0x430, 0x0);
- btcoexist->btc_write_4byte(btcoexist,
- 0x434, 0x04030201);
- }
- break;
- default:
- break;
- }
- }
-
- coex_dm->pre_arfr_type = coex_dm->cur_arfr_type;
-}
-
-void halbtc8821a1ant_retry_limit(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- coex_dm->cur_retry_limit_type = type;
-
- if (force_exec ||
- (coex_dm->pre_retry_limit_type !=
- coex_dm->cur_retry_limit_type)) {
- switch (coex_dm->cur_retry_limit_type) {
- case 0: /* normal mode */
- btcoexist->btc_write_2byte(btcoexist, 0x42a,
- coex_dm->backup_retry_limit);
- break;
- case 1: /* retry limit=8 */
- btcoexist->btc_write_2byte(btcoexist, 0x42a,
- 0x0808);
- break;
- default:
- break;
- }
- }
-
- coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type;
-}
-
-void halbtc8821a1ant_ampdu_max_time(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- coex_dm->cur_ampdu_time_type = type;
-
- if (force_exec ||
- (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) {
- switch (coex_dm->cur_ampdu_time_type) {
- case 0: /* normal mode */
- btcoexist->btc_write_1byte(btcoexist, 0x456,
- coex_dm->backup_ampdu_max_time);
- break;
- case 1: /* AMPDU timw = 0x38 * 32us */
- btcoexist->btc_write_1byte(btcoexist, 0x456,
- 0x38);
- break;
- default:
- break;
- }
- }
-
- coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type;
-}
-
-void halbtc8821a1ant_limited_tx(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type,
- IN u8 retry_limit_type, IN u8 ampdu_time_type)
-{
- switch (ra_mask_type) {
- case 0: /* normal mode */
- halbtc8821a1ant_update_ra_mask(btcoexist, force_exec,
- 0x0);
- break;
- case 1: /* disable cck 1/2 */
- halbtc8821a1ant_update_ra_mask(btcoexist, force_exec,
- 0x00000003);
- break;
- case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */
- halbtc8821a1ant_update_ra_mask(btcoexist, force_exec,
- 0x0001f1f7);
- break;
- default:
- break;
- }
-
- halbtc8821a1ant_auto_rate_fallback_retry(btcoexist, force_exec,
- arfr_type);
- halbtc8821a1ant_retry_limit(btcoexist, force_exec, retry_limit_type);
- halbtc8821a1ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type);
-}
-
-
-/* ture/xxxx/x:1
- * false/false/x: 64
- * false/ture/x:x */
-void halbtc8821a1ant_limited_rx(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean rej_ap_agg_pkt,
- IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size)
-{
- boolean reject_rx_agg = rej_ap_agg_pkt;
- boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size;
- u8 rx_agg_size = agg_buf_size;
-
- /* ============================================ */
- /* Rx Aggregation related setting */
- /* ============================================ */
- btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT,
- &reject_rx_agg);
- /* decide BT control aggregation buf size or not */
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE,
- &bt_ctrl_rx_agg_size);
- /* aggregation buf size, only work when BT control Rx aggregation size. */
- btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size);
- /* real update aggregation setting */
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
-
-
-}
-
-void halbtc8821a1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist)
-{
- u32 reg_hp_txrx, reg_lp_txrx, u32tmp;
- u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
-#if 0
- /* to avoid 0x76e[3] = 1 (WLAN_Act control by PTA) during IPS */
- if (!(btcoexist->btc_read_1byte(btcoexist, 0x76e) & 0x8)) {
- coex_sta->high_priority_tx = 65535;
- coex_sta->high_priority_rx = 65535;
- coex_sta->low_priority_tx = 65535;
- coex_sta->low_priority_rx = 65535;
- return;
- }
-#endif
- reg_hp_txrx = 0x770;
- reg_lp_txrx = 0x774;
-
- u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
- reg_hp_tx = u32tmp & MASKLWORD;
- reg_hp_rx = (u32tmp & MASKHWORD) >> 16;
-
- u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
- reg_lp_tx = u32tmp & MASKLWORD;
- reg_lp_rx = (u32tmp & MASKHWORD) >> 16;
-
- coex_sta->high_priority_tx = reg_hp_tx;
- coex_sta->high_priority_rx = reg_hp_rx;
- coex_sta->low_priority_tx = reg_lp_tx;
- coex_sta->low_priority_rx = reg_lp_rx;
-
- /* reset counter */
- btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
-}
-
-void halbtc8821a1ant_query_bt_info(IN struct btc_coexist *btcoexist)
-{
- u8 h2c_parameter[1] = {0};
-
- coex_sta->c2h_bt_info_req_sent = true;
-
- h2c_parameter[0] |= BIT(0); /* trigger */
-
- btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter);
-}
-
-boolean halbtc8821a1ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist)
-{
- static boolean pre_wifi_busy = false, pre_under_4way = false,
- pre_bt_hs_on = false;
- boolean wifi_busy = false, under_4way = false, bt_hs_on = false;
- boolean wifi_connected = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
- &under_4way);
-
- if (wifi_connected) {
- if (wifi_busy != pre_wifi_busy) {
- pre_wifi_busy = wifi_busy;
- return true;
- }
- if (under_4way != pre_under_4way) {
- pre_under_4way = under_4way;
- return true;
- }
- if (bt_hs_on != pre_bt_hs_on) {
- pre_bt_hs_on = bt_hs_on;
- return true;
- }
- }
-
- return false;
-}
-
-void halbtc8821a1ant_update_bt_link_info(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean bt_hs_on = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
-
- bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
- bt_link_info->sco_exist = coex_sta->sco_exist;
- bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
- bt_link_info->pan_exist = coex_sta->pan_exist;
- bt_link_info->hid_exist = coex_sta->hid_exist;
-
- /* work around for HS mode. */
- if (bt_hs_on) {
- bt_link_info->pan_exist = true;
- bt_link_info->bt_link_exist = true;
- }
-
- /* check if Sco only */
- if (bt_link_info->sco_exist &&
- !bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist &&
- !bt_link_info->hid_exist)
- bt_link_info->sco_only = true;
- else
- bt_link_info->sco_only = false;
-
- /* check if A2dp only */
- if (!bt_link_info->sco_exist &&
- bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist &&
- !bt_link_info->hid_exist)
- bt_link_info->a2dp_only = true;
- else
- bt_link_info->a2dp_only = false;
-
- /* check if Pan only */
- if (!bt_link_info->sco_exist &&
- !bt_link_info->a2dp_exist &&
- bt_link_info->pan_exist &&
- !bt_link_info->hid_exist)
- bt_link_info->pan_only = true;
- else
- bt_link_info->pan_only = false;
-
- /* check if Hid only */
- if (!bt_link_info->sco_exist &&
- !bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist &&
- bt_link_info->hid_exist)
- bt_link_info->hid_only = true;
- else
- bt_link_info->hid_only = false;
-}
-
-u8 halbtc8821a1ant_action_algorithm(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean bt_hs_on = false;
- u8 algorithm = BT_8821A_1ANT_COEX_ALGO_UNDEFINED;
- u8 num_of_diff_profile = 0;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
-
- if (!bt_link_info->bt_link_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], No BT link exists!!!\n");
- BTC_TRACE(trace_buf);
- return algorithm;
- }
-
- if (bt_link_info->sco_exist)
- num_of_diff_profile++;
- if (bt_link_info->hid_exist)
- num_of_diff_profile++;
- if (bt_link_info->pan_exist)
- num_of_diff_profile++;
- if (bt_link_info->a2dp_exist)
- num_of_diff_profile++;
-
- if (num_of_diff_profile == 1) {
- if (bt_link_info->sco_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO only\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8821A_1ANT_COEX_ALGO_SCO;
- } else {
- if (bt_link_info->hid_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = HID only\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8821A_1ANT_COEX_ALGO_HID;
- } else if (bt_link_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = A2DP only\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8821A_1ANT_COEX_ALGO_A2DP;
- } else if (bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = PAN(HS) only\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_1ANT_COEX_ALGO_PANHS;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = PAN(EDR) only\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_1ANT_COEX_ALGO_PANEDR;
- }
- }
- }
- } else if (num_of_diff_profile == 2) {
- if (bt_link_info->sco_exist) {
- if (bt_link_info->hid_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + HID\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8821A_1ANT_COEX_ALGO_HID;
- } else if (bt_link_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + A2DP ==> SCO\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8821A_1ANT_COEX_ALGO_SCO;
- } else if (bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8821A_1ANT_COEX_ALGO_SCO;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_1ANT_COEX_ALGO_PANEDR_HID;
- }
- }
- } else {
- if (bt_link_info->hid_exist &&
- bt_link_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = HID + A2DP\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8821A_1ANT_COEX_ALGO_HID_A2DP;
- } else if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = HID + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_1ANT_COEX_ALGO_HID_A2DP;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = HID + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_1ANT_COEX_ALGO_PANEDR_HID;
- }
- } else if (bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_1ANT_COEX_ALGO_A2DP_PANHS;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = A2DP + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_1ANT_COEX_ALGO_PANEDR_A2DP;
- }
- }
- }
- } else if (num_of_diff_profile == 3) {
- if (bt_link_info->sco_exist) {
- if (bt_link_info->hid_exist &&
- bt_link_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8821A_1ANT_COEX_ALGO_HID;
- } else if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + HID + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_1ANT_COEX_ALGO_HID_A2DP;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_1ANT_COEX_ALGO_PANEDR_HID;
- }
- } else if (bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8821A_1ANT_COEX_ALGO_SCO;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_1ANT_COEX_ALGO_PANEDR_HID;
- }
- }
- } else {
- if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_1ANT_COEX_ALGO_HID_A2DP;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_1ANT_COEX_ALGO_HID_A2DP_PANEDR;
- }
- }
- }
- } else if (num_of_diff_profile >= 3) {
- if (bt_link_info->sco_exist) {
- if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
-
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_1ANT_COEX_ALGO_PANEDR_HID;
- }
- }
- }
- }
-
- return algorithm;
-}
-
-void halbtc8821a1ant_set_bt_auto_report(IN struct btc_coexist *btcoexist,
- IN boolean enable_auto_report)
-{
- u8 h2c_parameter[1] = {0};
-
- h2c_parameter[0] = 0;
-
- if (enable_auto_report)
- h2c_parameter[0] |= BIT(0);
-
- btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter);
-}
-
-void halbtc8821a1ant_bt_auto_report(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean enable_auto_report)
-{
- coex_dm->cur_bt_auto_report = enable_auto_report;
-
- if (!force_exec) {
- if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report)
- return;
- }
- halbtc8821a1ant_set_bt_auto_report(btcoexist,
- coex_dm->cur_bt_auto_report);
-
- coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report;
-}
-
-void halbtc8821a1ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist
- *btcoexist, IN boolean low_penalty_ra)
-{
- u8 h2c_parameter[6] = {0};
-
- h2c_parameter[0] = 0x6; /* op_code, 0x6= Retry_Penalty */
-
- if (low_penalty_ra) {
- h2c_parameter[1] |= BIT(0);
- h2c_parameter[2] =
- 0x00; /* normal rate except MCS7/6/5, OFDM54/48/36 */
- h2c_parameter[3] = 0xf5; /* MCS7 or OFDM54 */
- h2c_parameter[4] = 0xa0; /* MCS6 or OFDM48// */
- h2c_parameter[5] = 0xa0; /* MCS5 or OFDM36 // */
- }
-
- btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter);
-}
-
-void halbtc8821a1ant_low_penalty_ra(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean low_penalty_ra)
-{
- coex_dm->cur_low_penalty_ra = low_penalty_ra;
-
- if (!force_exec) {
- if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra)
- return;
- }
- halbtc8821a1ant_set_sw_penalty_tx_rate_adaptive(btcoexist,
- coex_dm->cur_low_penalty_ra);
-
- coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra;
-}
-
-void halbtc8821a1ant_set_coex_table(IN struct btc_coexist *btcoexist,
- IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc)
-{
- btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
-
- btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
-
- btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
-
- btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
-}
-
-void halbtc8821a1ant_coex_table(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4,
- IN u32 val0x6c8, IN u8 val0x6cc)
-{
- coex_dm->cur_val0x6c0 = val0x6c0;
- coex_dm->cur_val0x6c4 = val0x6c4;
- coex_dm->cur_val0x6c8 = val0x6c8;
- coex_dm->cur_val0x6cc = val0x6cc;
-
- if (!force_exec) {
- if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) &&
- (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) &&
- (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) &&
- (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc))
- return;
- }
- halbtc8821a1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8,
- val0x6cc);
-
- coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0;
- coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4;
- coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8;
- coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc;
-}
-
-void halbtc8821a1ant_coex_table_with_type(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** CoexTable(%d) **********\n", type);
- BTC_TRACE(trace_buf);
-
- switch (type) {
- case 0:
- halbtc8821a1ant_coex_table(btcoexist, force_exec,
- 0x55555555, 0x55555555, 0xffffff, 0x3);
- break;
- case 1:
- halbtc8821a1ant_coex_table(btcoexist, force_exec,
- 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3);
- break;
- case 2:
- halbtc8821a1ant_coex_table(btcoexist, force_exec,
- 0x5a5a5a5a, 0x5a5a5a5a, 0xffffff, 0x3);
- break;
- case 3:
- halbtc8821a1ant_coex_table(btcoexist, force_exec,
- 0x5a5a5a5a, 0xaaaaaaaa, 0xffffff, 0x3);
- break;
- case 4:
- halbtc8821a1ant_coex_table(btcoexist, force_exec,
- 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3);
- break;
- case 5:
- halbtc8821a1ant_coex_table(btcoexist, force_exec,
- 0x5a5a5a5a, 0xaaaa5a5a, 0xffffff, 0x3);
- break;
- case 6:
- halbtc8821a1ant_coex_table(btcoexist, force_exec,
- 0x55555555, 0xaaaa5a5a, 0xffffff, 0x3);
- break;
- case 7:
- halbtc8821a1ant_coex_table(btcoexist, force_exec,
- 0xaaaaaaaa, 0xaaaaaaaa, 0xffffff, 0x3);
- break;
- default:
- break;
- }
-}
-
-void halbtc8821a1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist,
- IN boolean enable)
-{
- u8 h2c_parameter[1] = {0};
-
- if (enable) {
- h2c_parameter[0] |= BIT(0); /* function enable */
- }
-
- btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter);
-}
-
-void halbtc8821a1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean enable)
-{
- coex_dm->cur_ignore_wlan_act = enable;
-
- if (!force_exec) {
- if (coex_dm->pre_ignore_wlan_act ==
- coex_dm->cur_ignore_wlan_act)
- return;
- }
- halbtc8821a1ant_set_fw_ignore_wlan_act(btcoexist, enable);
-
- coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
-}
-
-void halbtc8821a1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist,
- IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5)
-{
- u8 h2c_parameter[5] = {0};
- u8 real_byte1 = byte1, real_byte5 = byte5;
- boolean ap_enable = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
- &ap_enable);
-
- if (ap_enable) {
- if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], FW for 1Ant AP mode\n");
- BTC_TRACE(trace_buf);
- real_byte1 &= ~BIT(4);
- real_byte1 |= BIT(5);
-
- real_byte5 |= BIT(5);
- real_byte5 &= ~BIT(6);
- }
- }
-
- h2c_parameter[0] = real_byte1;
- h2c_parameter[1] = byte2;
- h2c_parameter[2] = byte3;
- h2c_parameter[3] = byte4;
- h2c_parameter[4] = real_byte5;
-
- coex_dm->ps_tdma_para[0] = real_byte1;
- coex_dm->ps_tdma_para[1] = byte2;
- coex_dm->ps_tdma_para[2] = byte3;
- coex_dm->ps_tdma_para[3] = byte4;
- coex_dm->ps_tdma_para[4] = real_byte5;
-
- btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
-}
-
-void halbtc8821a1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist,
- IN u8 lps_val, IN u8 rpwm_val)
-{
- u8 lps = lps_val;
- u8 rpwm = rpwm_val;
-
- btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps);
- btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm);
-}
-
-void halbtc8821a1ant_lps_rpwm(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val)
-{
- coex_dm->cur_lps = lps_val;
- coex_dm->cur_rpwm = rpwm_val;
-
- if (!force_exec) {
- if ((coex_dm->pre_lps == coex_dm->cur_lps) &&
- (coex_dm->pre_rpwm == coex_dm->cur_rpwm))
- return;
- }
- halbtc8821a1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val);
-
- coex_dm->pre_lps = coex_dm->cur_lps;
- coex_dm->pre_rpwm = coex_dm->cur_rpwm;
-}
-
-void halbtc8821a1ant_sw_mechanism(IN struct btc_coexist *btcoexist,
- IN boolean low_penalty_ra)
-{
- halbtc8821a1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra);
-}
-
-void halbtc8821a1ant_set_ant_path(IN struct btc_coexist *btcoexist,
- IN u8 ant_pos_type, IN boolean init_hwcfg, IN boolean wifi_off)
-{
- struct btc_board_info *board_info = &btcoexist->board_info;
- u32 u32tmp = 0;
- u8 h2c_parameter[2] = {0};
-
- if (init_hwcfg) {
- /* 0x4c[23]=0, 0x4c[24]=1 Antenna control by WL/BT */
- u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c);
- u32tmp &= ~BIT(23);
- u32tmp |= BIT(24);
- btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp);
-
- /* 0x765 = 0x18 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x765, 0x18, 0x3);
-
- if (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT) {
- /* tell firmware "antenna inverse" ==> WRONG firmware antenna control code.==>need fw to fix */
- h2c_parameter[0] = 1;
- h2c_parameter[1] = 1;
- btcoexist->btc_fill_h2c(btcoexist, 0x65, 2,
- h2c_parameter);
-
- /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x64, 0x1, 0x1); //Main Ant to BT for IPS case 0x4c[23]=1 */
- } else {
- /* tell firmware "no antenna inverse" ==> WRONG firmware antenna control code.==>need fw to fix */
- h2c_parameter[0] = 0;
- h2c_parameter[1] = 1;
- btcoexist->btc_fill_h2c(btcoexist, 0x65, 2,
- h2c_parameter);
-
- /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x64, 0x1, 0x0); //Aux Ant to BT for IPS case 0x4c[23]=1 */
- }
- } else if (wifi_off) {
- /* 0x4c[24:23]=00, Set Antenna control by BT_RFE_CTRL BT Vendor 0xac=0xf002 */
- u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c);
- u32tmp &= ~BIT(23);
- u32tmp &= ~BIT(24);
- btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp);
-
- /* 0x765 = 0x18 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x765, 0x18, 0x3);
- } else {
- /* 0x765 = 0x0 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x765, 0x18, 0x0);
- }
-
- /* ext switch setting */
- switch (ant_pos_type) {
- case BTC_ANT_PATH_WIFI:
- btcoexist->btc_write_1byte(btcoexist, 0xcb4, 0x77);
- if (board_info->btdm_ant_pos ==
- BTC_ANTENNA_AT_MAIN_PORT)
- btcoexist->btc_write_1byte_bitmask(btcoexist,
- 0xcb7, 0x30, 0x1);
- else
- btcoexist->btc_write_1byte_bitmask(btcoexist,
- 0xcb7, 0x30, 0x2);
- break;
- case BTC_ANT_PATH_BT:
- btcoexist->btc_write_1byte(btcoexist, 0xcb4, 0x77);
- if (board_info->btdm_ant_pos ==
- BTC_ANTENNA_AT_MAIN_PORT)
- btcoexist->btc_write_1byte_bitmask(btcoexist,
- 0xcb7, 0x30, 0x2);
- else
- btcoexist->btc_write_1byte_bitmask(btcoexist,
- 0xcb7, 0x30, 0x1);
- break;
- default:
- case BTC_ANT_PATH_PTA:
- btcoexist->btc_write_1byte(btcoexist, 0xcb4, 0x66);
- if (board_info->btdm_ant_pos ==
- BTC_ANTENNA_AT_MAIN_PORT)
- btcoexist->btc_write_1byte_bitmask(btcoexist,
- 0xcb7, 0x30, 0x1);
- else
- btcoexist->btc_write_1byte_bitmask(btcoexist,
- 0xcb7, 0x30, 0x2);
- break;
- }
-}
-
-void halbtc8821a1ant_ps_tdma(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean turn_on, IN u8 type)
-{
- u8 rssi_adjust_val = 0;
- /* u32 fw_ver=0; */
-
- coex_dm->cur_ps_tdma_on = turn_on;
- coex_dm->cur_ps_tdma = type;
-
- if (coex_dm->cur_ps_tdma_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** TDMA(on, %d) **********\n",
- coex_dm->cur_ps_tdma);
- BTC_TRACE(trace_buf);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** TDMA(off, %d) **********\n",
- coex_dm->cur_ps_tdma);
- BTC_TRACE(trace_buf);
- }
-
- if (!force_exec) {
- if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) &&
- (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma))
- return;
- }
- if (turn_on) {
- switch (type) {
- default:
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51,
- 0x1a, 0x1a, 0x0, 0x50);
- break;
- case 1:
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51,
- 0x3a, 0x03, 0x10, 0x50);
- rssi_adjust_val = 11;
- break;
- case 2:
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51,
- 0x2b, 0x03, 0x10, 0x50);
- rssi_adjust_val = 14;
- break;
- case 3:
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51,
- 0x1d, 0x1d, 0x0, 0x52);
- break;
- case 4:
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x93,
- 0x15, 0x3, 0x14, 0x0);
- rssi_adjust_val = 17;
- break;
- case 5:
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x61,
- 0x15, 0x3, 0x11, 0x10);
- break;
- case 6:
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x61,
- 0x20, 0x3, 0x11, 0x13);
- break;
- case 7:
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x13,
- 0xc, 0x5, 0x0, 0x0);
- break;
- case 8:
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x93,
- 0x25, 0x3, 0x10, 0x0);
- break;
- case 9:
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51,
- 0x21, 0x3, 0x10, 0x50);
- rssi_adjust_val = 18;
- break;
- case 10:
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x13,
- 0xa, 0xa, 0x0, 0x40);
- break;
- case 11:
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51,
- 0x15, 0x03, 0x10, 0x50);
- rssi_adjust_val = 20;
- break;
- case 12:
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51,
- 0x0a, 0x0a, 0x0, 0x50);
- break;
- case 13:
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51,
- 0x12, 0x12, 0x0, 0x50);
- break;
- case 14:
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51,
- 0x1e, 0x3, 0x10, 0x14);
- break;
- case 15:
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x13,
- 0xa, 0x3, 0x8, 0x0);
- break;
- case 16:
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x93,
- 0x15, 0x3, 0x10, 0x0);
- rssi_adjust_val = 18;
- break;
- case 18:
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x93,
- 0x25, 0x3, 0x10, 0x0);
- rssi_adjust_val = 14;
- break;
- case 20:
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x61,
- 0x35, 0x03, 0x11, 0x10);
- break;
- case 21:
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x61,
- 0x25, 0x03, 0x11, 0x11);
- break;
- case 22:
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x61,
- 0x25, 0x03, 0x11, 0x10);
- break;
- case 23:
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x25, 0x3, 0x31, 0x18);
- rssi_adjust_val = 22;
- break;
- case 24:
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x15, 0x3, 0x31, 0x18);
- rssi_adjust_val = 22;
- break;
- case 25:
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xe3,
- 0xa, 0x3, 0x31, 0x18);
- rssi_adjust_val = 22;
- break;
- case 26:
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xe3,
- 0xa, 0x3, 0x31, 0x18);
- rssi_adjust_val = 22;
- break;
- case 27:
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x25, 0x3, 0x31, 0x98);
- rssi_adjust_val = 22;
- break;
- case 28:
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x69,
- 0x25, 0x3, 0x31, 0x0);
- break;
- case 29:
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xab,
- 0x1a, 0x1a, 0x1, 0x10);
- break;
- case 30:
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51,
- 0x30, 0x3, 0x10, 0x10);
- break;
- case 31:
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xd3,
- 0x1a, 0x1a, 0, 0x58);
- break;
- case 32:
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x61,
- 0x35, 0x3, 0x11, 0x11);
- break;
- case 33:
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xa3,
- 0x25, 0x3, 0x30, 0x90);
- break;
- case 34:
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x53,
- 0x1a, 0x1a, 0x0, 0x10);
- break;
- case 35:
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x63,
- 0x1a, 0x1a, 0x0, 0x10);
- break;
- case 36:
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0xd3,
- 0x12, 0x3, 0x14, 0x50);
- break;
- case 40: /* SoftAP only with no sta associated,BT disable ,TDMA mode for power saving */
- /* here softap mode screen off will cost 70-80mA for phone */
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x23,
- 0x18, 0x00, 0x10, 0x24);
- break;
- case 41:
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51,
- 0x15, 0x3, 0x11, 0x11);
- break;
- case 42:
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51,
- 0x20, 0x3, 0x11, 0x11);
- break;
- case 43:
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x51,
- 0x30, 0x3, 0x10, 0x11);
- break;
- }
- } else {
- /* disable PS tdma */
- switch (type) {
- case 8: /* PTA Control */
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x8,
- 0x0, 0x0, 0x0, 0x0);
- halbtc8821a1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_PTA, false, false);
- break;
- case 0:
- default: /* Software control, Antenna at BT side */
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x0,
- 0x0, 0x0, 0x0, 0x0);
- halbtc8821a1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_BT, false, false);
- break;
- case 9: /* Software control, Antenna at WiFi side */
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x0,
- 0x0, 0x0, 0x0, 0x0);
- halbtc8821a1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_WIFI, false, false);
- break;
- case 10: /* under 5G */
- halbtc8821a1ant_set_fw_pstdma(btcoexist, 0x0,
- 0x0, 0x0, 0x8, 0x0);
- halbtc8821a1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_BT, false, false);
- break;
- }
- }
- rssi_adjust_val = 0;
- btcoexist->btc_set(btcoexist,
- BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE, &rssi_adjust_val);
-
- /* update pre state */
- coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on;
- coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
-}
-
-void halbtc8821a1ant_coex_all_off(IN struct btc_coexist *btcoexist)
-{
- /* sw all off */
- halbtc8821a1ant_sw_mechanism(btcoexist, false);
-
- /* hw all off */
- halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-}
-
-boolean halbtc8821a1ant_is_common_action(IN struct btc_coexist *btcoexist)
-{
- boolean common = false, wifi_connected = false, wifi_busy = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- if (!wifi_connected &&
- BT_8821A_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
- coex_dm->bt_status) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n");
- BTC_TRACE(trace_buf);
- halbtc8821a1ant_sw_mechanism(btcoexist, false);
-
- common = true;
- } else if (wifi_connected &&
- (BT_8821A_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
- coex_dm->bt_status)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi connected + BT non connected-idle!!\n");
- BTC_TRACE(trace_buf);
- halbtc8821a1ant_sw_mechanism(btcoexist, false);
-
- common = true;
- } else if (!wifi_connected &&
- (BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi non connected-idle + BT connected-idle!!\n");
- BTC_TRACE(trace_buf);
- halbtc8821a1ant_sw_mechanism(btcoexist, false);
-
- common = true;
- } else if (wifi_connected &&
- (BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi connected + BT connected-idle!!\n");
- BTC_TRACE(trace_buf);
- halbtc8821a1ant_sw_mechanism(btcoexist, false);
-
- common = true;
- } else if (!wifi_connected &&
- (BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE != coex_dm->bt_status)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi non connected-idle + BT Busy!!\n");
- BTC_TRACE(trace_buf);
- halbtc8821a1ant_sw_mechanism(btcoexist, false);
-
- common = true;
- } else {
- if (wifi_busy) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi Connected-Busy + BT Busy!!\n");
- BTC_TRACE(trace_buf);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi Connected-Idle + BT Busy!!\n");
- BTC_TRACE(trace_buf);
- }
-
- common = false;
- }
-
- return common;
-}
-
-void halbtc8821a1ant_ps_tdma_check_for_power_save_state(
- IN struct btc_coexist *btcoexist, IN boolean new_ps_state)
-{
- u8 lps_mode = 0x0;
-
- btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode);
-
- if (lps_mode) { /* already under LPS state */
- if (new_ps_state) {
- /* keep state under LPS, do nothing. */
- } else {
- /* will leave LPS state, turn off psTdma first */
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 1);
- }
- } else { /* NO PS state */
- if (new_ps_state) {
- /* will enter LPS state, turn off psTdma first */
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 0);
- } else {
- /* keep state under NO PS state, do nothing. */
- }
- }
-}
-
-void halbtc8821a1ant_power_save_state(IN struct btc_coexist *btcoexist,
- IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val)
-{
- boolean low_pwr_disable = false;
-
- switch (ps_type) {
- case BTC_PS_WIFI_NATIVE:
- /* recover to original 32k low power setting */
- low_pwr_disable = false;
- btcoexist->btc_set(btcoexist,
- BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS,
- NULL);
- break;
- case BTC_PS_LPS_ON:
- halbtc8821a1ant_ps_tdma_check_for_power_save_state(
- btcoexist, true);
- halbtc8821a1ant_lps_rpwm(btcoexist, NORMAL_EXEC,
- lps_val, rpwm_val);
- /* when coex force to enter LPS, do not enter 32k low power. */
- low_pwr_disable = true;
- btcoexist->btc_set(btcoexist,
- BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
- /* power save must executed before psTdma. */
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS,
- NULL);
- break;
- case BTC_PS_LPS_OFF:
- halbtc8821a1ant_ps_tdma_check_for_power_save_state(
- btcoexist, false);
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS,
- NULL);
- break;
- default:
- break;
- }
-}
-
-void halbtc8821a1ant_coex_under_5g(IN struct btc_coexist *btcoexist)
-{
- halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
-
- halbtc8821a1ant_ignore_wlan_act(btcoexist, NORMAL_EXEC, true);
-
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 10);
-
- halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
-
- halbtc8821a1ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 5);
-}
-
-void halbtc8821a1ant_action_wifi_only(IN struct btc_coexist *btcoexist)
-{
- halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 9);
-}
-
-void halbtc8821a1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist)
-{
- static u32 bt_disable_cnt = 0;
- boolean bt_active = true, bt_disabled = false;
-
- /* This function check if bt is disabled */
-
- if (coex_sta->high_priority_tx == 0 &&
- coex_sta->high_priority_rx == 0 &&
- coex_sta->low_priority_tx == 0 &&
- coex_sta->low_priority_rx == 0)
- bt_active = false;
- if (coex_sta->high_priority_tx == 0xffff &&
- coex_sta->high_priority_rx == 0xffff &&
- coex_sta->low_priority_tx == 0xffff &&
- coex_sta->low_priority_rx == 0xffff)
- bt_active = false;
- if (bt_active) {
- bt_disable_cnt = 0;
- bt_disabled = false;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
- &bt_disabled);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is enabled !!\n");
- BTC_TRACE(trace_buf);
- } else {
- bt_disable_cnt++;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], bt all counters=0, %d times!!\n",
- bt_disable_cnt);
- BTC_TRACE(trace_buf);
- if (bt_disable_cnt >= 2) {
- bt_disabled = true;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
- &bt_disabled);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is disabled !!\n");
- BTC_TRACE(trace_buf);
- halbtc8821a1ant_action_wifi_only(btcoexist);
- }
- }
- if (coex_sta->bt_disabled != bt_disabled) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is from %s to %s!!\n",
- (coex_sta->bt_disabled ? "disabled" : "enabled"),
- (bt_disabled ? "disabled" : "enabled"));
- BTC_TRACE(trace_buf);
- coex_sta->bt_disabled = bt_disabled;
- if (!bt_disabled) {
- } else {
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS,
- NULL);
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS,
- NULL);
- }
- }
-}
-
-/* *********************************************
- *
- * Software Coex Mechanism start
- *
- * ********************************************* */
-
-void halbtc8821a1ant_action_bt_whck_test(IN struct btc_coexist *btcoexist)
-{
- halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
-
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- /* halbtc8821a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, false, false); */
- halbtc8821a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, false, false);
- halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-}
-/* SCO only or SCO+PAN(HS) */
-void halbtc8821a1ant_action_sco(IN struct btc_coexist *btcoexist)
-{
- halbtc8821a1ant_sw_mechanism(btcoexist, true);
-}
-
-void halbtc8821a1ant_action_hid(IN struct btc_coexist *btcoexist)
-{
- halbtc8821a1ant_sw_mechanism(btcoexist, true);
-}
-
-/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */
-void halbtc8821a1ant_action_a2dp(IN struct btc_coexist *btcoexist)
-{
- halbtc8821a1ant_sw_mechanism(btcoexist, false);
-}
-
-void halbtc8821a1ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist)
-{
- halbtc8821a1ant_sw_mechanism(btcoexist, false);
-}
-
-void halbtc8821a1ant_action_pan_edr(IN struct btc_coexist *btcoexist)
-{
- halbtc8821a1ant_sw_mechanism(btcoexist, false);
-}
-
-/* PAN(HS) only */
-void halbtc8821a1ant_action_pan_hs(IN struct btc_coexist *btcoexist)
-{
- halbtc8821a1ant_sw_mechanism(btcoexist, false);
-}
-
-/* PAN(EDR)+A2DP */
-void halbtc8821a1ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist)
-{
- halbtc8821a1ant_sw_mechanism(btcoexist, false);
-}
-
-void halbtc8821a1ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist)
-{
- halbtc8821a1ant_sw_mechanism(btcoexist, true);
-}
-
-/* HID+A2DP+PAN(EDR) */
-void halbtc8821a1ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist)
-{
- halbtc8821a1ant_sw_mechanism(btcoexist, true);
-}
-
-void halbtc8821a1ant_action_hid_a2dp(IN struct btc_coexist *btcoexist)
-{
- halbtc8821a1ant_sw_mechanism(btcoexist, true);
-}
-
-/* *********************************************
- *
- * Non-Software Coex Mechanism start
- *
- * ********************************************* */
-void halbtc8821a1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist)
-{
- halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
-
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
-}
-
-void halbtc8821a1ant_action_hs(IN struct btc_coexist *btcoexist)
-{
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
- halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
-}
-
-void halbtc8821a1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_connected = false, ap_enable = false, wifi_busy = false,
- bt_busy = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
- &ap_enable);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
-
- if ((!wifi_connected) && (!coex_sta->wifi_is_high_pri_task)) {
- halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
-
- halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
- }
-
- /* sy modify */
- else if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) ||
- (bt_link_info->a2dp_exist)) {
- /* SCO/HID/A2DP busy */
- halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
-
- halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- }
-
- /* sy modify */
-
- else if ((bt_link_info->a2dp_exist) &&
- (bt_link_info->hid_exist)) {
- /* A2DP+HID busy */
- halbtc8821a1ant_power_save_state(btcoexist,
- BTC_PS_WIFI_NATIVE, 0x0, 0x0);
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 14);
-
- halbtc8821a1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 1);
- }
-
-
- else if ((bt_link_info->pan_exist) || (wifi_busy)) {
- halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
-
- halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- } else {
- halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
-
- halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
- }
-}
-
-void halbtc8821a1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist
- *btcoexist, IN u8 wifi_status)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_connected = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
-
- /* tdma and coex table */
-
- if (bt_link_info->sco_exist) {
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 41);
- halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
- } else { /* HID */
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 42);
- halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
- }
-}
-
-void halbtc8821a1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist
- *btcoexist, IN u8 wifi_status)
-{
- u8 bt_rssi_state;
-
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- bt_rssi_state = halbtc8821a1ant_bt_rssi_state(2, 28, 0);
-
- if (bt_link_info->hid_only) { /* HID */
- halbtc8821a1ant_action_bt_sco_hid_only_busy(btcoexist,
- wifi_status);
- coex_dm->auto_tdma_adjust = false;
- return;
- } else if (bt_link_info->a2dp_only) { /* A2DP */
- if (BT_8821A_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifi_status) {
- /* halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); */
- /* halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); */
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 32);
- halbtc8821a1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 1);
- coex_dm->auto_tdma_adjust = false;
- } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- /* halbtc8821a1ant_tdma_duration_adjust_for_acl(btcoexist, wifi_status); */
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 14);
- halbtc8821a1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 1);
- } else { /* for low BT RSSI */
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 14);
- halbtc8821a1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 1);
- coex_dm->auto_tdma_adjust = false;
- }
- } else if (bt_link_info->hid_exist &&
- bt_link_info->a2dp_exist) { /* HID+A2DP */
- if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 14);
- coex_dm->auto_tdma_adjust = false;
- } else { /* for low BT RSSI */
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 14);
- coex_dm->auto_tdma_adjust = false;
- }
-
- halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
- } else if ((bt_link_info->pan_only) || (bt_link_info->hid_exist &&
- bt_link_info->pan_exist)) { /* PAN(OPP,FTP), HID+PAN(OPP,FTP) */
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3);
- halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6);
- coex_dm->auto_tdma_adjust = false;
- } else if (((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) ||
- (bt_link_info->hid_exist && bt_link_info->a2dp_exist &&
- bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 43);
- halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
- coex_dm->auto_tdma_adjust = false;
- } else {
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 11);
- halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
- coex_dm->auto_tdma_adjust = false;
- }
-}
-
-void halbtc8821a1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist)
-{
- /* power save state */
- halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
-
- /* tdma and coex table */
- halbtc8821a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8);
- halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-}
-
-void halbtc8821a1ant_action_wifi_not_connected_scan(IN struct btc_coexist
- *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
- halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
-
- /* tdma and coex table */
- if (BT_8821A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
- if (bt_link_info->a2dp_exist) {
- /* sy modify */
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 14);
- halbtc8821a1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 1);
- } else if (bt_link_info->a2dp_exist && bt_link_info->pan_exist) {
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 22);
- halbtc8821a1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- } else {
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 20);
- halbtc8821a1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- }
- } else if ((BT_8821A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
- (BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY ==
- coex_dm->bt_status)) {
- halbtc8821a1ant_action_bt_sco_hid_only_busy(btcoexist,
- BT_8821A_1ANT_WIFI_STATUS_CONNECTED_SCAN);
- } else {
- /* halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); */
- /* halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); */
-
- /* Bryant Add */
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
- }
-}
-
-void halbtc8821a1ant_action_wifi_not_connected_asso_auth(
- IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
- halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
-
- /* tdma and coex table */
- if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist)) {
- /* sy modify */
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14);
- halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
- } else if ((bt_link_info->a2dp_exist) || (bt_link_info->pan_exist)) {
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
- halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- } else {
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
- }
-}
-
-void halbtc8821a1ant_action_wifi_connected_scan(IN struct btc_coexist
- *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
- halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
-
- /* tdma and coex table */
- if (BT_8821A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
- if (bt_link_info->a2dp_exist) {
- /* sy modify */
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 14);
- halbtc8821a1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 1);
- } else if (bt_link_info->a2dp_exist &&
- bt_link_info->pan_exist) {
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 22);
- halbtc8821a1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- } else {
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 20);
- halbtc8821a1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- }
- } else if ((BT_8821A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
- (BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY ==
- coex_dm->bt_status)) {
- halbtc8821a1ant_action_bt_sco_hid_only_busy(btcoexist,
- BT_8821A_1ANT_WIFI_STATUS_CONNECTED_SCAN);
- } else {
- /* halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); */
- /* halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); */
-
- /* Bryant Add */
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
- }
-}
-
-void halbtc8821a1ant_action_wifi_connected_specific_packet(
- IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
- halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
-
- /* tdma and coex table */
- /* sy modify */
- if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) ||
- (bt_link_info->a2dp_exist)) {
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
- halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- }
-
- if ((bt_link_info->hid_exist) && (bt_link_info->a2dp_exist)) {
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 14);
- halbtc8821a1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 1);
- }
-
-
- else if (bt_link_info->pan_exist) {
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
- halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- } else {
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
- }
-}
-
-void halbtc8821a1ant_action_wifi_connected(IN struct btc_coexist *btcoexist)
-{
- boolean wifi_busy = false;
- boolean scan = false, link = false, roam = false;
- boolean under_4way = false, ap_enable = false;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CoexForWifiConnect()===>\n");
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
- &under_4way);
- if (under_4way) {
- halbtc8821a1ant_action_wifi_connected_specific_packet(btcoexist);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CoexForWifiConnect(), return for wifi is under 4way<===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
- if (scan || link || roam) {
- if (scan)
- halbtc8821a1ant_action_wifi_connected_scan(btcoexist);
- else
- halbtc8821a1ant_action_wifi_connected_specific_packet(
- btcoexist);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CoexForWifiConnect(), return for wifi is under scan<===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
- &ap_enable);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- /* power save state */
- if (!ap_enable &&
- BT_8821A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status &&
- !btcoexist->bt_link_info.hid_only) {
- if (!wifi_busy && btcoexist->bt_link_info.a2dp_only) /* A2DP */
- halbtc8821a1ant_power_save_state(btcoexist,
- BTC_PS_WIFI_NATIVE, 0x0, 0x0);
- else
- halbtc8821a1ant_power_save_state(btcoexist,
- BTC_PS_LPS_ON, 0x50, 0x4);
- } else
- halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
-
- /* tdma and coex table */
- if (!wifi_busy) {
- if (BT_8821A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
- halbtc8821a1ant_action_wifi_connected_bt_acl_busy(
- btcoexist,
- BT_8821A_1ANT_WIFI_STATUS_CONNECTED_IDLE);
- } else if ((BT_8821A_1ANT_BT_STATUS_SCO_BUSY ==
- coex_dm->bt_status) ||
- (BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY ==
- coex_dm->bt_status)) {
- halbtc8821a1ant_action_bt_sco_hid_only_busy(btcoexist,
- BT_8821A_1ANT_WIFI_STATUS_CONNECTED_IDLE);
- } else {
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 8);
- halbtc8821a1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 2);
- }
- } else {
- if (BT_8821A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
- halbtc8821a1ant_action_wifi_connected_bt_acl_busy(
- btcoexist,
- BT_8821A_1ANT_WIFI_STATUS_CONNECTED_BUSY);
- } else if ((BT_8821A_1ANT_BT_STATUS_SCO_BUSY ==
- coex_dm->bt_status) ||
- (BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY ==
- coex_dm->bt_status)) {
- halbtc8821a1ant_action_bt_sco_hid_only_busy(btcoexist,
- BT_8821A_1ANT_WIFI_STATUS_CONNECTED_BUSY);
- } else {
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 8);
- halbtc8821a1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 2);
- }
- }
-}
-
-void halbtc8821a1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist)
-{
- u8 algorithm = 0;
-
- algorithm = halbtc8821a1ant_action_algorithm(btcoexist);
- coex_dm->cur_algorithm = algorithm;
-
- if (halbtc8821a1ant_is_common_action(btcoexist)) {
-
- } else {
- switch (coex_dm->cur_algorithm) {
- case BT_8821A_1ANT_COEX_ALGO_SCO:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = SCO.\n");
- BTC_TRACE(trace_buf);
- halbtc8821a1ant_action_sco(btcoexist);
- break;
- case BT_8821A_1ANT_COEX_ALGO_HID:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = HID.\n");
- BTC_TRACE(trace_buf);
- halbtc8821a1ant_action_hid(btcoexist);
- break;
- case BT_8821A_1ANT_COEX_ALGO_A2DP:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = A2DP.\n");
- BTC_TRACE(trace_buf);
- halbtc8821a1ant_action_a2dp(btcoexist);
- break;
- case BT_8821A_1ANT_COEX_ALGO_A2DP_PANHS:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = A2DP+PAN(HS).\n");
- BTC_TRACE(trace_buf);
- halbtc8821a1ant_action_a2dp_pan_hs(btcoexist);
- break;
- case BT_8821A_1ANT_COEX_ALGO_PANEDR:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = PAN(EDR).\n");
- BTC_TRACE(trace_buf);
- halbtc8821a1ant_action_pan_edr(btcoexist);
- break;
- case BT_8821A_1ANT_COEX_ALGO_PANHS:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = HS mode.\n");
- BTC_TRACE(trace_buf);
- halbtc8821a1ant_action_pan_hs(btcoexist);
- break;
- case BT_8821A_1ANT_COEX_ALGO_PANEDR_A2DP:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = PAN+A2DP.\n");
- BTC_TRACE(trace_buf);
- halbtc8821a1ant_action_pan_edr_a2dp(btcoexist);
- break;
- case BT_8821A_1ANT_COEX_ALGO_PANEDR_HID:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = PAN(EDR)+HID.\n");
- BTC_TRACE(trace_buf);
- halbtc8821a1ant_action_pan_edr_hid(btcoexist);
- break;
- case BT_8821A_1ANT_COEX_ALGO_HID_A2DP_PANEDR:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = HID+A2DP+PAN.\n");
- BTC_TRACE(trace_buf);
- halbtc8821a1ant_action_hid_a2dp_pan_edr(
- btcoexist);
- break;
- case BT_8821A_1ANT_COEX_ALGO_HID_A2DP:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = HID+A2DP.\n");
- BTC_TRACE(trace_buf);
- halbtc8821a1ant_action_hid_a2dp(btcoexist);
- break;
- default:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = coexist All Off!!\n");
- BTC_TRACE(trace_buf);
- /* halbtc8821a1ant_coex_all_off(btcoexist); */
- break;
- }
- coex_dm->pre_algorithm = coex_dm->cur_algorithm;
- }
-}
-
-void halbtc8821a1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_connected = false, bt_hs_on = false;
- boolean increase_scan_dev_num = false;
- boolean bt_ctrl_agg_buf_size = false;
- u8 agg_buf_size = 5;
- u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH;
- u32 wifi_link_status = 0;
- u32 num_of_wifi_link = 0;
- boolean wifi_under_5g = false;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism()===>\n");
- BTC_TRACE(trace_buf);
-
- if (btcoexist->manual_control) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- if (btcoexist->stop_coex_dm) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- if (coex_sta->under_ips) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], wifi is under IPS !!!\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
- if (wifi_under_5g) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism(), return for 5G <===\n");
- BTC_TRACE(trace_buf);
- halbtc8821a1ant_coex_under_5g(btcoexist);
- return;
- }
- if (coex_sta->bt_whck_test) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is under WHCK TEST!!!\n");
- BTC_TRACE(trace_buf);
- halbtc8821a1ant_action_bt_whck_test(btcoexist);
- return;
- }
-
- if ((BT_8821A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
- (BT_8821A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
- (BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status))
- increase_scan_dev_num = true;
-
- btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM,
- &increase_scan_dev_num);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
- num_of_wifi_link = wifi_link_status >> 16;
- if ((num_of_wifi_link >= 2) ||
- (wifi_link_status & WIFI_P2P_GO_CONNECTED)) {
- halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
- halbtc8821a1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
- bt_ctrl_agg_buf_size, agg_buf_size);
- halbtc8821a1ant_action_wifi_multi_port(btcoexist);
- return;
- }
-
- if (!bt_link_info->sco_exist && !bt_link_info->hid_exist)
- halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
- else {
- if (wifi_connected) {
- wifi_rssi_state = halbtc8821a1ant_wifi_rssi_state(
- btcoexist, 1, 2, 30, 0);
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- /* halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, 1, 1); */
- halbtc8821a1ant_limited_tx(btcoexist,
- NORMAL_EXEC, 1, 1, 0, 1);
- } else {
- /* halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, 1, 1); */
- halbtc8821a1ant_limited_tx(btcoexist,
- NORMAL_EXEC, 1, 1, 0, 1);
- }
- } else
- halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0,
- 0, 0);
-
- }
-
- if (bt_link_info->sco_exist) {
- bt_ctrl_agg_buf_size = true;
- agg_buf_size = 0x3;
- } else if (bt_link_info->hid_exist) {
- bt_ctrl_agg_buf_size = true;
- agg_buf_size = 0x5;
- } else if (bt_link_info->a2dp_exist || bt_link_info->pan_exist) {
- bt_ctrl_agg_buf_size = true;
- agg_buf_size = 0x8;
- }
- halbtc8821a1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
- bt_ctrl_agg_buf_size, agg_buf_size);
-
- halbtc8821a1ant_run_sw_coexist_mechanism(btcoexist);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- if (coex_sta->c2h_bt_inquiry_page) {
- halbtc8821a1ant_action_bt_inquiry(btcoexist);
- return;
- } else if (bt_hs_on) {
- halbtc8821a1ant_action_hs(btcoexist);
- return;
- }
-
-
- if (!wifi_connected) {
- boolean scan = false, link = false, roam = false;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], wifi is non connected-idle !!!\n");
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
-
- if (scan || link || roam) {
- if (scan)
- halbtc8821a1ant_action_wifi_not_connected_scan(
- btcoexist);
- else
- halbtc8821a1ant_action_wifi_not_connected_asso_auth(
- btcoexist);
- } else
- halbtc8821a1ant_action_wifi_not_connected(btcoexist);
- } else /* wifi LPS/Busy */
- halbtc8821a1ant_action_wifi_connected(btcoexist);
-}
-
-void halbtc8821a1ant_init_coex_dm(IN struct btc_coexist *btcoexist)
-{
- /* force to reset coex mechanism */
- /* sw all off */
- halbtc8821a1ant_sw_mechanism(btcoexist, false);
-
- /* halbtc8821a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); */
- halbtc8821a1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
-}
-
-void halbtc8821a1ant_init_hw_config(IN struct btc_coexist *btcoexist,
- IN boolean back_up, IN boolean wifi_only)
-{
- u8 u8tmp = 0;
- boolean wifi_under_5g = false;
-
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], 1Ant Init HW Config!!\n");
- BTC_TRACE(trace_buf);
-
- if (wifi_only)
- return;
-
- if (back_up) {
- coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist,
- 0x430);
- coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist,
- 0x434);
- coex_dm->backup_retry_limit = btcoexist->btc_read_2byte(
- btcoexist, 0x42a);
- coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte(
- btcoexist, 0x456);
- }
-
- /* 0x790[5:0]=0x5 */
- u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790);
- u8tmp &= 0xc0;
- u8tmp |= 0x5;
- btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
-
- /* Antenna config */
- if (wifi_under_5g)
- halbtc8821a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, true,
- false);
- else
- halbtc8821a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, true,
- false);
-
- /* PTA parameter */
- halbtc8821a1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
-
- /* Enable counter statistics */
- btcoexist->btc_write_1byte(btcoexist, 0x76e,
- 0xc); /* 0x76e[3] =1, WLAN_Act control by PTA */
- btcoexist->btc_write_1byte(btcoexist, 0x778, 0x3);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1);
-}
-
-/* ************************************************************
- * work around function start with wa_halbtc8821a1ant_
- * ************************************************************
- * ************************************************************
- * extern function start with ex_halbtc8821a1ant_
- * ************************************************************ */
-void ex_halbtc8821a1ant_power_on_setting(IN struct btc_coexist *btcoexist)
-{
-}
-
-void ex_halbtc8821a1ant_init_hw_config(IN struct btc_coexist *btcoexist,
- IN boolean wifi_only)
-{
- halbtc8821a1ant_init_hw_config(btcoexist, true, wifi_only);
-}
-
-void ex_halbtc8821a1ant_init_coex_dm(IN struct btc_coexist *btcoexist)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Coex Mechanism Init!!\n");
- BTC_TRACE(trace_buf);
-
- btcoexist->stop_coex_dm = false;
-
- halbtc8821a1ant_init_coex_dm(btcoexist);
-
- halbtc8821a1ant_query_bt_info(btcoexist);
-}
-
-void ex_halbtc8821a1ant_display_coex_info(IN struct btc_coexist *btcoexist)
-{
- struct btc_board_info *board_info = &btcoexist->board_info;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- u8 *cli_buf = btcoexist->cli_buf;
- u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0;
- u16 u16tmp[4];
- u32 u32tmp[4];
- u32 fw_ver = 0, bt_patch_ver = 0;
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ============[BT Coexist info]============");
- CL_PRINTF(cli_buf);
-
- if (btcoexist->manual_control) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ============[Under Manual Control]============");
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ==========================================");
- CL_PRINTF(cli_buf);
- }
- if (btcoexist->stop_coex_dm) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ============[Coex is STOPPED]============");
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ==========================================");
- CL_PRINTF(cli_buf);
- }
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d",
- "Ant PG Num/ Ant Mech/ Ant Pos:",
- board_info->pg_ant_num, board_info->btdm_ant_num,
- board_info->btdm_ant_pos);
- CL_PRINTF(cli_buf);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %d_%x/ 0x%x/ 0x%x(%d)",
- "CoexVer/ FwVer/ PatchVer",
- glcoex_ver_date_8821a_1ant, glcoex_ver_8821a_1ant, fw_ver,
- bt_patch_ver, bt_patch_ver);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ",
- "Wifi channel informed to BT",
- coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
- coex_dm->wifi_chnl_info[2]);
- CL_PRINTF(cli_buf);
-
- /* wifi status */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Wifi Status]============");
- CL_PRINTF(cli_buf);
- btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[BT Status]============");
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ",
- "BT [status/ rssi/ retryCnt]",
- ((coex_sta->bt_disabled) ? ("disabled") : ((
- coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan")
- : ((BT_8821A_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
- coex_dm->bt_status) ? "non-connected idle" :
- ((BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)
- ? "connected-idle" : "busy")))),
- coex_sta->bt_rssi, coex_sta->bt_retry_cnt);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d",
- "SCO/HID/PAN/A2DP",
- bt_link_info->sco_exist, bt_link_info->hid_exist,
- bt_link_info->pan_exist, bt_link_info->a2dp_exist);
- CL_PRINTF(cli_buf);
- btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_BT_LINK_INFO);
-
- bt_info_ext = coex_sta->bt_info_ext;
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
- "BT Info A2DP rate",
- (bt_info_ext & BIT(0)) ? "Basic rate" : "EDR rate");
- CL_PRINTF(cli_buf);
-
- for (i = 0; i < BT_INFO_SRC_8821A_1ANT_MAX; i++) {
- if (coex_sta->bt_info_c2h_cnt[i]) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)",
- glbt_info_src_8821a_1ant[i],
- coex_sta->bt_info_c2h[i][0],
- coex_sta->bt_info_c2h[i][1],
- coex_sta->bt_info_c2h[i][2],
- coex_sta->bt_info_c2h[i][3],
- coex_sta->bt_info_c2h[i][4],
- coex_sta->bt_info_c2h[i][5],
- coex_sta->bt_info_c2h[i][6],
- coex_sta->bt_info_c2h_cnt[i]);
- CL_PRINTF(cli_buf);
- }
- }
-
- if (!btcoexist->manual_control) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
- "SM[LowPenaltyRA]",
- coex_dm->cur_low_penalty_ra);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[mechanisms]============");
- CL_PRINTF(cli_buf);
-
- ps_tdma_case = coex_dm->cur_ps_tdma;
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (auto:%d)",
- "PS TDMA",
- coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],
- coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],
- coex_dm->ps_tdma_para[4], ps_tdma_case,
- coex_dm->auto_tdma_adjust);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ",
- "IgnWlanAct",
- coex_dm->cur_ignore_wlan_act);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ",
- "Latest error condition(should be 0)",
- coex_dm->error_condition);
- CL_PRINTF(cli_buf);
- }
-
- /* Hw setting */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Hw setting]============");
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x",
- "backup ARFR1/ARFR2/RL/AMaxTime",
- coex_dm->backup_arfr_cnt1, coex_dm->backup_arfr_cnt2,
- coex_dm->backup_retry_limit,
- coex_dm->backup_ampdu_max_time);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434);
- u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x",
- "0x430/0x434/0x42a/0x456",
- u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]);
- CL_PRINTF(cli_buf);
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc58);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
- "0x778/ 0xc58[29:25]",
- u8tmp[0], (u32tmp[0] & 0x3e000000) >> 25);
- CL_PRINTF(cli_buf);
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x8db);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x8db[6:5]",
- ((u8tmp[0] & 0x60) >> 5));
- CL_PRINTF(cli_buf);
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x975);
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xcb4);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
- "0xcb4[29:28]/0xcb4[7:0]/0x974[9:8]",
- (u32tmp[0] & 0x30000000) >> 28, u32tmp[0] & 0xff,
- u8tmp[0] & 0x3);
- CL_PRINTF(cli_buf);
-
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x40);
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x64);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
- "0x40/0x4c[24:23]/0x64[0]",
- u8tmp[0], ((u32tmp[0] & 0x01800000) >> 23), u8tmp[1] & 0x1);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
- "0x550(bcn ctrl)/0x522",
- u32tmp[0], u8tmp[0]);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)",
- u32tmp[0] & 0xff);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xf48);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xa5d);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xa5c);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
- "OFDM-FA/ CCK-FA",
- u32tmp[0], (u8tmp[0] << 8) + u8tmp[1]);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
- u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
- "0x6c0/0x6c4/0x6c8(coexTable)",
- u32tmp[0], u32tmp[1], u32tmp[2]);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
- "0x770(high-pri rx/tx)",
- coex_sta->high_priority_rx, coex_sta->high_priority_tx);
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
- "0x774(low-pri rx/tx)",
- coex_sta->low_priority_rx, coex_sta->low_priority_tx);
- CL_PRINTF(cli_buf);
-#if (BT_AUTO_REPORT_ONLY_8821A_1ANT == 1)
- halbtc8821a1ant_monitor_bt_ctr(btcoexist);
-#endif
- btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
-}
-
-
-void ex_halbtc8821a1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type)
-{
- boolean wifi_under_5g = false;
-
- if (btcoexist->manual_control || btcoexist->stop_coex_dm)
- return;
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G,
- &wifi_under_5g);
- if (wifi_under_5g) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism(), return for 5G <===\n");
- BTC_TRACE(trace_buf);
- halbtc8821a1ant_coex_under_5g(btcoexist);
- return;
- }
-
- if (BTC_IPS_ENTER == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], IPS ENTER notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_ips = true;
-
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
- halbtc8821a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false,
- true);
- /* halbtc8821a1ant_set_ant_path_d_cut(btcoexist, false, false, false, BTC_ANT_PATH_BT, BTC_WIFI_STAT_NORMAL_OFF); */
- } else if (BTC_IPS_LEAVE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], IPS LEAVE notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_ips = false;
-
- halbtc8821a1ant_init_hw_config(btcoexist, false, false);
- halbtc8821a1ant_init_coex_dm(btcoexist);
- halbtc8821a1ant_query_bt_info(btcoexist);
- }
-}
-
-void ex_halbtc8821a1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type)
-{
-
-
- if (BTC_LPS_ENABLE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], LPS ENABLE notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_lps = true;
- } else if (BTC_LPS_DISABLE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], LPS DISABLE notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_lps = false;
- }
-}
-
-void ex_halbtc8821a1ant_scan_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- boolean wifi_connected = false, bt_hs_on = false;
- u32 wifi_link_status = 0;
- u32 num_of_wifi_link = 0;
- boolean bt_ctrl_agg_buf_size = false;
- u8 agg_buf_size = 5;
- boolean wifi_under_5g = false;
-
- if (btcoexist->manual_control ||
- btcoexist->stop_coex_dm)
- return;
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
- if (wifi_under_5g) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism(), return for 5G <===\n");
- BTC_TRACE(trace_buf);
- halbtc8821a1ant_coex_under_5g(btcoexist);
- return;
- }
-
- if (BTC_SCAN_START == type) {
- coex_sta->wifi_is_high_pri_task = true;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCAN START notify\n");
- BTC_TRACE(trace_buf);
-
- halbtc8821a1ant_ps_tdma(btcoexist, FORCE_EXEC, false,
- 8); /* Force antenna setup for no scan result issue */
- } else {
- coex_sta->wifi_is_high_pri_task = false;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCAN FINISH notify\n");
- BTC_TRACE(trace_buf);
- }
-
- if (coex_sta->bt_disabled)
- return;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
-
- halbtc8821a1ant_query_bt_info(btcoexist);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
- num_of_wifi_link = wifi_link_status >> 16;
- if (num_of_wifi_link >= 2) {
- halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
- halbtc8821a1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
- bt_ctrl_agg_buf_size, agg_buf_size);
- halbtc8821a1ant_action_wifi_multi_port(btcoexist);
- return;
- }
-
- if (coex_sta->c2h_bt_inquiry_page) {
- halbtc8821a1ant_action_bt_inquiry(btcoexist);
- return;
- } else if (bt_hs_on) {
- halbtc8821a1ant_action_hs(btcoexist);
- return;
- }
-
- if (BTC_SCAN_START == type) {
- if (!wifi_connected) /* non-connected scan */
- halbtc8821a1ant_action_wifi_not_connected_scan(
- btcoexist);
- else /* wifi is connected */
- halbtc8821a1ant_action_wifi_connected_scan(btcoexist);
- } else if (BTC_SCAN_FINISH == type) {
- if (!wifi_connected) /* non-connected scan */
- halbtc8821a1ant_action_wifi_not_connected(btcoexist);
- else
- halbtc8821a1ant_action_wifi_connected(btcoexist);
- }
-}
-
-void ex_halbtc8821a1ant_connect_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- boolean wifi_connected = false, bt_hs_on = false;
- u32 wifi_link_status = 0;
- u32 num_of_wifi_link = 0;
- boolean bt_ctrl_agg_buf_size = false;
- u8 agg_buf_size = 5;
- boolean wifi_under_5g = false;
-
- if (btcoexist->manual_control ||
- btcoexist->stop_coex_dm ||
- coex_sta->bt_disabled)
- return;
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
- if (wifi_under_5g) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism(), return for 5G <===\n");
- BTC_TRACE(trace_buf);
- halbtc8821a1ant_coex_under_5g(btcoexist);
- return;
- }
-
- if (BTC_ASSOCIATE_START == type) {
- coex_sta->wifi_is_high_pri_task = true;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CONNECT START notify\n");
- BTC_TRACE(trace_buf);
- coex_dm->arp_cnt = 0;
- } else {
- coex_sta->wifi_is_high_pri_task = false;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CONNECT FINISH notify\n");
- BTC_TRACE(trace_buf);
- coex_dm->arp_cnt = 0;
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
- num_of_wifi_link = wifi_link_status >> 16;
- if (num_of_wifi_link >= 2) {
- halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
- halbtc8821a1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
- bt_ctrl_agg_buf_size, agg_buf_size);
- halbtc8821a1ant_action_wifi_multi_port(btcoexist);
- return;
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- if (coex_sta->c2h_bt_inquiry_page) {
- halbtc8821a1ant_action_bt_inquiry(btcoexist);
- return;
- } else if (bt_hs_on) {
- halbtc8821a1ant_action_hs(btcoexist);
- return;
- }
-
- if (BTC_ASSOCIATE_START == type)
- halbtc8821a1ant_action_wifi_not_connected_asso_auth(btcoexist);
- else if (BTC_ASSOCIATE_FINISH == type) {
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- if (!wifi_connected) /* non-connected scan */
- halbtc8821a1ant_action_wifi_not_connected(btcoexist);
- else
- halbtc8821a1ant_action_wifi_connected(btcoexist);
- }
-}
-
-void ex_halbtc8821a1ant_media_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- u8 h2c_parameter[3] = {0};
- u32 wifi_bw;
- u8 wifi_central_chnl;
- boolean wifi_under_5g = false;
-
- if (btcoexist->manual_control ||
- btcoexist->stop_coex_dm ||
- coex_sta->bt_disabled)
- return;
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
- if (wifi_under_5g) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism(), return for 5G <===\n");
- BTC_TRACE(trace_buf);
- halbtc8821a1ant_coex_under_5g(btcoexist);
- return;
- }
-
- if (BTC_MEDIA_CONNECT == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], MEDIA connect notify\n");
- BTC_TRACE(trace_buf);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], MEDIA disconnect notify\n");
- BTC_TRACE(trace_buf);
- coex_dm->arp_cnt = 0;
- }
-
- /* only 2.4G we need to inform bt the chnl mask */
- btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
- &wifi_central_chnl);
- if ((BTC_MEDIA_CONNECT == type) &&
- (wifi_central_chnl <= 14)) {
- /* h2c_parameter[0] = 0x1; */
- h2c_parameter[0] = 0x0;
- h2c_parameter[1] = wifi_central_chnl;
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- if (BTC_WIFI_BW_HT40 == wifi_bw)
- h2c_parameter[2] = 0x30;
- else
- h2c_parameter[2] = 0x20;
- }
-
- coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
- coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
- coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
-
- btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter);
-}
-
-void ex_halbtc8821a1ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- boolean bt_hs_on = false;
- u32 wifi_link_status = 0;
- u32 num_of_wifi_link = 0;
- boolean bt_ctrl_agg_buf_size = false;
- u8 agg_buf_size = 5;
- boolean wifi_under_5g = false;
-
- if (btcoexist->manual_control ||
- btcoexist->stop_coex_dm ||
- coex_sta->bt_disabled)
- return;
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
- if (wifi_under_5g) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism(), return for 5G <===\n");
- BTC_TRACE(trace_buf);
- halbtc8821a1ant_coex_under_5g(btcoexist);
- return;
- }
-
- if (BTC_PACKET_DHCP == type ||
- BTC_PACKET_EAPOL == type ||
- BTC_PACKET_ARP == type) {
- coex_sta->wifi_is_high_pri_task = true;
-
- if (BTC_PACKET_ARP == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], specific Packet ARP notify\n");
- BTC_TRACE(trace_buf);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], specific Packet DHCP or EAPOL notify\n");
- BTC_TRACE(trace_buf);
- }
- } else {
- coex_sta->wifi_is_high_pri_task = false;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], specific Packet [Type = %d] notify\n", type);
- BTC_TRACE(trace_buf);
- }
-
- coex_sta->specific_pkt_period_cnt = 0;
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
- num_of_wifi_link = wifi_link_status >> 16;
- if (num_of_wifi_link >= 2) {
- halbtc8821a1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
- halbtc8821a1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
- bt_ctrl_agg_buf_size, agg_buf_size);
- halbtc8821a1ant_action_wifi_multi_port(btcoexist);
- return;
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- if (coex_sta->c2h_bt_inquiry_page) {
- halbtc8821a1ant_action_bt_inquiry(btcoexist);
- return;
- } else if (bt_hs_on) {
- halbtc8821a1ant_action_hs(btcoexist);
- return;
- }
-
- if (BTC_PACKET_DHCP == type ||
- BTC_PACKET_EAPOL == type ||
- BTC_PACKET_ARP == type) {
- if (BTC_PACKET_ARP == type) {
- coex_dm->arp_cnt++;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ARP Packet Count = %d\n",
- coex_dm->arp_cnt);
- BTC_TRACE(trace_buf);
- if (coex_dm->arp_cnt >=
- 10) /* if APR PKT > 10 after connect, do not go to ActionWifiConnectedSpecificPacket(btcoexist) */
- return;
- }
-
- halbtc8821a1ant_action_wifi_connected_specific_packet(btcoexist);
- }
-}
-
-void ex_halbtc8821a1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
- IN u8 *tmp_buf, IN u8 length)
-{
- u8 bt_info = 0;
- u8 i, rsp_source = 0;
- boolean wifi_connected = false;
- boolean bt_busy = false;
- boolean wifi_under_5g = false;
-
-
- coex_sta->c2h_bt_info_req_sent = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
-
- rsp_source = tmp_buf[0] & 0xf;
- if (rsp_source >= BT_INFO_SRC_8821A_1ANT_MAX)
- rsp_source = BT_INFO_SRC_8821A_1ANT_WIFI_FW;
- coex_sta->bt_info_c2h_cnt[rsp_source]++;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source,
- length);
- BTC_TRACE(trace_buf);
- for (i = 0; i < length; i++) {
- coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
- if (i == 1)
- bt_info = tmp_buf[i];
- if (i == length - 1) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n",
- tmp_buf[i]);
- BTC_TRACE(trace_buf);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ",
- tmp_buf[i]);
- BTC_TRACE(trace_buf);
- }
- }
- /* if 0xff, it means BT is under WHCK test */
- if (bt_info == 0xff)
- coex_sta->bt_whck_test = true;
- else
- coex_sta->bt_whck_test = false;
-
- if (BT_INFO_SRC_8821A_1ANT_WIFI_FW != rsp_source) {
- coex_sta->bt_retry_cnt = /* [3:0] */
- coex_sta->bt_info_c2h[rsp_source][2] & 0xf;
-
- if (coex_sta->bt_info_c2h[rsp_source][2] & 0x20)
- coex_sta->c2h_bt_page = true;
- else
- coex_sta->c2h_bt_page = false;
-
- coex_sta->bt_rssi =
- coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10;
-
- coex_sta->bt_info_ext =
- coex_sta->bt_info_c2h[rsp_source][4];
-
- coex_sta->bt_tx_rx_mask = (coex_sta->bt_info_c2h[rsp_source][2]
- & 0x40);
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TX_RX_MASK,
- &coex_sta->bt_tx_rx_mask);
- if (!coex_sta->bt_tx_rx_mask) {
- /* BT into is responded by BT FW and BT RF REG 0x3C != 0x15 => Need to switch BT TRx Mask */
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x15\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF,
- 0x3c, 0x15);
- }
-
- /* Here we need to resend some wifi info to BT */
- /* because bt is reset and loss of the info. */
- if (coex_sta->bt_info_ext & BIT(1)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- if (wifi_connected)
- ex_halbtc8821a1ant_media_status_notify(
- btcoexist, BTC_MEDIA_CONNECT);
- else
- ex_halbtc8821a1ant_media_status_notify(
- btcoexist, BTC_MEDIA_DISCONNECT);
- }
-
- if ((coex_sta->bt_info_ext & BIT(3)) && !wifi_under_5g) {
- if (!btcoexist->manual_control &&
- !btcoexist->stop_coex_dm) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n");
- BTC_TRACE(trace_buf);
- halbtc8821a1ant_ignore_wlan_act(btcoexist,
- FORCE_EXEC, false);
- }
- } else {
- /* BT already NOT ignore Wlan active, do nothing here. */
- }
-#if (BT_AUTO_REPORT_ONLY_8821A_1ANT == 0)
- if ((coex_sta->bt_info_ext & BIT(4))) {
- /* BT auto report already enabled, do nothing */
- } else
- halbtc8821a1ant_bt_auto_report(btcoexist, FORCE_EXEC,
- true);
-#endif
- }
-
- /* check BIT2 first ==> check if bt is under inquiry or page scan */
- if (bt_info & BT_INFO_8821A_1ANT_B_INQ_PAGE)
- coex_sta->c2h_bt_inquiry_page = true;
- else
- coex_sta->c2h_bt_inquiry_page = false;
-
- /* set link exist status */
- if (!(bt_info & BT_INFO_8821A_1ANT_B_CONNECTION)) {
- coex_sta->bt_link_exist = false;
- coex_sta->pan_exist = false;
- coex_sta->a2dp_exist = false;
- coex_sta->hid_exist = false;
- coex_sta->sco_exist = false;
- } else { /* connection exists */
- coex_sta->bt_link_exist = true;
- if (bt_info & BT_INFO_8821A_1ANT_B_FTP)
- coex_sta->pan_exist = true;
- else
- coex_sta->pan_exist = false;
- if (bt_info & BT_INFO_8821A_1ANT_B_A2DP)
- coex_sta->a2dp_exist = true;
- else
- coex_sta->a2dp_exist = false;
- if (bt_info & BT_INFO_8821A_1ANT_B_HID)
- coex_sta->hid_exist = true;
- else
- coex_sta->hid_exist = false;
- if (bt_info & BT_INFO_8821A_1ANT_B_SCO_ESCO)
- coex_sta->sco_exist = true;
- else
- coex_sta->sco_exist = false;
- }
-
- halbtc8821a1ant_update_bt_link_info(btcoexist);
-
- bt_info = bt_info &
- 0x1f; /* mask profile bit for connect-ilde identification ( for CSR case: A2DP idle --> 0x41) */
-
- if (!(bt_info & BT_INFO_8821A_1ANT_B_CONNECTION)) {
- coex_dm->bt_status = BT_8821A_1ANT_BT_STATUS_NON_CONNECTED_IDLE;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n");
- BTC_TRACE(trace_buf);
- } else if (bt_info ==
- BT_INFO_8821A_1ANT_B_CONNECTION) { /* connection exists but no busy */
- coex_dm->bt_status = BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n");
- BTC_TRACE(trace_buf);
- } else if ((bt_info & BT_INFO_8821A_1ANT_B_SCO_ESCO) ||
- (bt_info & BT_INFO_8821A_1ANT_B_SCO_BUSY)) {
- coex_dm->bt_status = BT_8821A_1ANT_BT_STATUS_SCO_BUSY;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n");
- BTC_TRACE(trace_buf);
- } else if (bt_info & BT_INFO_8821A_1ANT_B_ACL_BUSY) {
- if (BT_8821A_1ANT_BT_STATUS_ACL_BUSY != coex_dm->bt_status)
- coex_dm->auto_tdma_adjust = false;
- coex_dm->bt_status = BT_8821A_1ANT_BT_STATUS_ACL_BUSY;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n");
- BTC_TRACE(trace_buf);
- } else {
- coex_dm->bt_status = BT_8821A_1ANT_BT_STATUS_MAX;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n");
- BTC_TRACE(trace_buf);
- }
-
- if ((BT_8821A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
- (BT_8821A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
- (BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status))
- bt_busy = true;
- else
- bt_busy = false;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
-
- halbtc8821a1ant_run_coexist_mechanism(btcoexist);
-}
-
-void ex_halbtc8821a1ant_halt_notify(IN struct btc_coexist *btcoexist)
-{
- boolean wifi_under_5g = false;
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
- if (wifi_under_5g) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism(), return for 5G <===\n");
- BTC_TRACE(trace_buf);
- halbtc8821a1ant_coex_under_5g(btcoexist);
- return;
- }
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n");
- BTC_TRACE(trace_buf);
-
- halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
- halbtc8821a1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
- halbtc8821a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false, true);
- /* halbtc8821a1ant_set_ant_path_d_cut(btcoexist, false, false, false, BTC_ANT_PATH_BT, BTC_WIFI_STAT_NORMAL_OFF); */
-
- halbtc8821a1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
-
- ex_halbtc8821a1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
-
- btcoexist->stop_coex_dm = true;
-}
-
-void ex_halbtc8821a1ant_pnp_notify(IN struct btc_coexist *btcoexist,
- IN u8 pnp_state)
-{
- boolean wifi_under_5g = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
- if (wifi_under_5g) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism(), return for 5G <===\n");
- BTC_TRACE(trace_buf);
- halbtc8821a1ant_coex_under_5g(btcoexist);
- return;
- }
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n");
- BTC_TRACE(trace_buf);
-
- if (BTC_WIFI_PNP_SLEEP == pnp_state) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Pnp notify to SLEEP\n");
- BTC_TRACE(trace_buf);
-
- halbtc8821a1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- halbtc8821a1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- halbtc8821a1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
- halbtc8821a1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, false,
- true);
- /* halbtc8821a1ant_set_ant_path_d_cut(btcoexist, false, false, false, BTC_ANT_PATH_BT, BTC_WIFI_STAT_NORMAL_OFF); */
-
- /* Sinda 20150819, workaround for driver skip leave IPS/LPS to speed up sleep time. */
- /* Driver do not leave IPS/LPS when driver is going to sleep, so BTCoexistence think wifi is still under IPS/LPS */
- /* BT should clear UnderIPS/UnderLPS state to avoid mismatch state after wakeup. */
- coex_sta->under_ips = false;
- coex_sta->under_lps = false;
- btcoexist->stop_coex_dm = true;
- } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Pnp notify to WAKE UP\n");
- BTC_TRACE(trace_buf);
- btcoexist->stop_coex_dm = false;
- halbtc8821a1ant_init_hw_config(btcoexist, false, false);
- halbtc8821a1ant_init_coex_dm(btcoexist);
- halbtc8821a1ant_query_bt_info(btcoexist);
- }
-}
-
-void ex_halbtc8821a1ant_periodical(IN struct btc_coexist *btcoexist)
-{
-#if (BT_AUTO_REPORT_ONLY_8821A_1ANT == 0)
- halbtc8821a1ant_query_bt_info(btcoexist);
- halbtc8821a1ant_monitor_bt_ctr(btcoexist);
- halbtc8821a1ant_monitor_bt_enable_disable(btcoexist);
-#else
- if (halbtc8821a1ant_is_wifi_status_changed(btcoexist) ||
- coex_dm->auto_tdma_adjust) {
- /* if(coex_sta->specific_pkt_period_cnt > 2) */
- /* { */
- halbtc8821a1ant_run_coexist_mechanism(btcoexist);
- /* } */
- }
-
- coex_sta->specific_pkt_period_cnt++;
-#endif
-}
-
-#endif
-
-#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */
-
diff --git a/hal/btc/HalBtc8821a1Ant.h b/hal/btc/HalBtc8821a1Ant.h
deleted file mode 100644
index 6c9c327..0000000
--- a/hal/btc/HalBtc8821a1Ant.h
+++ /dev/null
@@ -1,197 +0,0 @@
-
-#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
-
-#if (RTL8821A_SUPPORT == 1)
-
-/* *******************************************
- * The following is for 8821A 1ANT BT Co-exist definition
- * ******************************************* */
-#define BT_AUTO_REPORT_ONLY_8821A_1ANT 1
-
-#define BT_INFO_8821A_1ANT_B_FTP BIT(7)
-#define BT_INFO_8821A_1ANT_B_A2DP BIT(6)
-#define BT_INFO_8821A_1ANT_B_HID BIT(5)
-#define BT_INFO_8821A_1ANT_B_SCO_BUSY BIT(4)
-#define BT_INFO_8821A_1ANT_B_ACL_BUSY BIT(3)
-#define BT_INFO_8821A_1ANT_B_INQ_PAGE BIT(2)
-#define BT_INFO_8821A_1ANT_B_SCO_ESCO BIT(1)
-#define BT_INFO_8821A_1ANT_B_CONNECTION BIT(0)
-
-#define BT_INFO_8821A_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \
- (((_BT_INFO_EXT_&BIT(0))) ? true : false)
-
-#define BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT 2
-
-enum bt_info_src_8821a_1ant {
- BT_INFO_SRC_8821A_1ANT_WIFI_FW = 0x0,
- BT_INFO_SRC_8821A_1ANT_BT_RSP = 0x1,
- BT_INFO_SRC_8821A_1ANT_BT_ACTIVE_SEND = 0x2,
- BT_INFO_SRC_8821A_1ANT_MAX
-};
-
-enum bt_8821a_1ant_bt_status {
- BT_8821A_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
- BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
- BT_8821A_1ANT_BT_STATUS_INQ_PAGE = 0x2,
- BT_8821A_1ANT_BT_STATUS_ACL_BUSY = 0x3,
- BT_8821A_1ANT_BT_STATUS_SCO_BUSY = 0x4,
- BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
- BT_8821A_1ANT_BT_STATUS_MAX
-};
-
-enum bt_8821a_1ant_wifi_status {
- BT_8821A_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0,
- BT_8821A_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1,
- BT_8821A_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2,
- BT_8821A_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT = 0x3,
- BT_8821A_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4,
- BT_8821A_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5,
- BT_8821A_1ANT_WIFI_STATUS_MAX
-};
-
-enum bt_8821a_1ant_coex_algo {
- BT_8821A_1ANT_COEX_ALGO_UNDEFINED = 0x0,
- BT_8821A_1ANT_COEX_ALGO_SCO = 0x1,
- BT_8821A_1ANT_COEX_ALGO_HID = 0x2,
- BT_8821A_1ANT_COEX_ALGO_A2DP = 0x3,
- BT_8821A_1ANT_COEX_ALGO_A2DP_PANHS = 0x4,
- BT_8821A_1ANT_COEX_ALGO_PANEDR = 0x5,
- BT_8821A_1ANT_COEX_ALGO_PANHS = 0x6,
- BT_8821A_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
- BT_8821A_1ANT_COEX_ALGO_PANEDR_HID = 0x8,
- BT_8821A_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
- BT_8821A_1ANT_COEX_ALGO_HID_A2DP = 0xa,
- BT_8821A_1ANT_COEX_ALGO_MAX = 0xb,
-};
-
-struct coex_dm_8821a_1ant {
- /* fw mechanism */
- boolean cur_ignore_wlan_act;
- boolean pre_ignore_wlan_act;
- u8 pre_ps_tdma;
- u8 cur_ps_tdma;
- u8 ps_tdma_para[5];
- u8 ps_tdma_du_adj_type;
- boolean auto_tdma_adjust;
- boolean pre_ps_tdma_on;
- boolean cur_ps_tdma_on;
- boolean pre_bt_auto_report;
- boolean cur_bt_auto_report;
- u8 pre_lps;
- u8 cur_lps;
- u8 pre_rpwm;
- u8 cur_rpwm;
-
- /* sw mechanism */
- boolean pre_low_penalty_ra;
- boolean cur_low_penalty_ra;
- u32 pre_val0x6c0;
- u32 cur_val0x6c0;
- u32 pre_val0x6c4;
- u32 cur_val0x6c4;
- u32 pre_val0x6c8;
- u32 cur_val0x6c8;
- u8 pre_val0x6cc;
- u8 cur_val0x6cc;
-
- u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */
- u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */
- u16 backup_retry_limit;
- u8 backup_ampdu_max_time;
-
- /* algorithm related */
- u8 pre_algorithm;
- u8 cur_algorithm;
- u8 bt_status;
- u8 wifi_chnl_info[3];
-
- u32 pre_ra_mask;
- u32 cur_ra_mask;
- u8 pre_arfr_type;
- u8 cur_arfr_type;
- u8 pre_retry_limit_type;
- u8 cur_retry_limit_type;
- u8 pre_ampdu_time_type;
- u8 cur_ampdu_time_type;
- u32 arp_cnt;
-
- u8 error_condition;
-};
-
-struct coex_sta_8821a_1ant {
- boolean bt_disabled;
- boolean bt_link_exist;
- boolean sco_exist;
- boolean a2dp_exist;
- boolean hid_exist;
- boolean pan_exist;
-
- boolean under_lps;
- boolean under_ips;
- u32 specific_pkt_period_cnt;
- u32 high_priority_tx;
- u32 high_priority_rx;
- u32 low_priority_tx;
- u32 low_priority_rx;
- u8 bt_rssi;
- boolean bt_tx_rx_mask;
- u8 pre_bt_rssi_state;
- u8 pre_wifi_rssi_state[4];
- boolean c2h_bt_info_req_sent;
- u8 bt_info_c2h[BT_INFO_SRC_8821A_1ANT_MAX][10];
- u32 bt_info_c2h_cnt[BT_INFO_SRC_8821A_1ANT_MAX];
- boolean c2h_bt_inquiry_page;
- boolean c2h_bt_page; /* Add for win8.1 page out issue */
- boolean wifi_is_high_pri_task; /* Add for win8.1 page out issue */
- u8 bt_retry_cnt;
- u8 bt_info_ext;
- boolean
- bt_whck_test; /* Add for ASUS WHQL TEST that enable wifi test bt */
-};
-
-/* *******************************************
- * The following is interface which will notify coex module.
- * ******************************************* */
-void ex_halbtc8821a1ant_power_on_setting(IN struct btc_coexist *btcoexist);
-void ex_halbtc8821a1ant_init_hw_config(IN struct btc_coexist *btcoexist,
- IN boolean wifi_only);
-void ex_halbtc8821a1ant_init_coex_dm(IN struct btc_coexist *btcoexist);
-void ex_halbtc8821a1ant_ips_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8821a1ant_lps_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8821a1ant_scan_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8821a1ant_connect_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8821a1ant_media_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8821a1ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8821a1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
- IN u8 *tmp_buf, IN u8 length);
-void ex_halbtc8821a1ant_halt_notify(IN struct btc_coexist *btcoexist);
-void ex_halbtc8821a1ant_pnp_notify(IN struct btc_coexist *btcoexist,
- IN u8 pnp_state);
-void ex_halbtc8821a1ant_periodical(IN struct btc_coexist *btcoexist);
-void ex_halbtc8821a1ant_display_coex_info(IN struct btc_coexist *btcoexist);
-
-#else
-#define ex_halbtc8821a1ant_power_on_setting(btcoexist)
-#define ex_halbtc8821a1ant_init_hw_config(btcoexist, wifi_only)
-#define ex_halbtc8821a1ant_init_coex_dm(btcoexist)
-#define ex_halbtc8821a1ant_ips_notify(btcoexist, type)
-#define ex_halbtc8821a1ant_lps_notify(btcoexist, type)
-#define ex_halbtc8821a1ant_scan_notify(btcoexist, type)
-#define ex_halbtc8821a1ant_connect_notify(btcoexist, type)
-#define ex_halbtc8821a1ant_media_status_notify(btcoexist, type)
-#define ex_halbtc8821a1ant_specific_packet_notify(btcoexist, type)
-#define ex_halbtc8821a1ant_bt_info_notify(btcoexist, tmp_buf, length)
-#define ex_halbtc8821a1ant_halt_notify(btcoexist)
-#define ex_halbtc8821a1ant_pnp_notify(btcoexist, pnp_state)
-#define ex_halbtc8821a1ant_periodical(btcoexist)
-#define ex_halbtc8821a1ant_display_coex_info(btcoexist)
-
-#endif
-
-#endif
diff --git a/hal/btc/HalBtc8821a2Ant.c b/hal/btc/HalBtc8821a2Ant.c
deleted file mode 100644
index 010a422..0000000
--- a/hal/btc/HalBtc8821a2Ant.c
+++ /dev/null
@@ -1,4560 +0,0 @@
-/* ************************************************************
- * Description:
- *
- * This file is for RTL8821A Co-exist mechanism
- *
- * History
- * 2012/11/15 Cosa first check in.
- *
- * ************************************************************ */
-
-/* ************************************************************
- * include files
- * ************************************************************ */
-#include "Mp_Precomp.h"
-
-#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
-
-#if (RTL8821A_SUPPORT == 1)
-/* ************************************************************
- * Global variables, these are static variables
- * ************************************************************ */
-static u8 *trace_buf = &gl_btc_trace_buf[0];
-static struct coex_dm_8821a_2ant glcoex_dm_8821a_2ant;
-static struct coex_dm_8821a_2ant *coex_dm = &glcoex_dm_8821a_2ant;
-static struct coex_sta_8821a_2ant glcoex_sta_8821a_2ant;
-static struct coex_sta_8821a_2ant *coex_sta = &glcoex_sta_8821a_2ant;
-
-const char *const glbt_info_src_8821a_2ant[] = {
- "BT Info[wifi fw]",
- "BT Info[bt rsp]",
- "BT Info[bt auto report]",
-};
-
-u32 glcoex_ver_date_8821a_2ant = 20150921;
-u32 glcoex_ver_8821a_2ant = 0x58;
-/* modify 20140903v43 a2dpandhid tdmaonoff a2dp glitch _ tdma off 778=3(case1)->778=1(case0)
- * and to improve tp while a2dphid case23->case25 , case123->case125 for asus spec
- * and modify for asus bt WHQL test _ tdma off_ 778=3->1_
- * ************************************************************
- * local function proto type if needed
- * ************************************************************
- * ************************************************************
- * local function start with halbtc8821a2ant_
- * ************************************************************ */
-u8 halbtc8821a2ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1)
-{
- s32 bt_rssi = 0;
- u8 bt_rssi_state = coex_sta->pre_bt_rssi_state;
-
- bt_rssi = coex_sta->bt_rssi;
-
- if (level_num == 2) {
- if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
- (coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (bt_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT))
- bt_rssi_state = BTC_RSSI_STATE_HIGH;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else {
- if (bt_rssi < rssi_thresh)
- bt_rssi_state = BTC_RSSI_STATE_LOW;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- } else if (level_num == 3) {
- if (rssi_thresh > rssi_thresh1) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Rssi thresh error!!\n");
- BTC_TRACE(trace_buf);
- return coex_sta->pre_bt_rssi_state;
- }
-
- if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
- (coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (bt_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT))
- bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else if ((coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_MEDIUM) ||
- (coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_STAY_MEDIUM)) {
- if (bt_rssi >= (rssi_thresh1 +
- BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT))
- bt_rssi_state = BTC_RSSI_STATE_HIGH;
- else if (bt_rssi < rssi_thresh)
- bt_rssi_state = BTC_RSSI_STATE_LOW;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
- } else {
- if (bt_rssi < rssi_thresh1)
- bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- }
-
- coex_sta->pre_bt_rssi_state = bt_rssi_state;
-
- return bt_rssi_state;
-}
-
-u8 halbtc8821a2ant_wifi_rssi_state(IN struct btc_coexist *btcoexist,
- IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1)
-{
- s32 wifi_rssi = 0;
- u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index];
-
- btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
-
- if (level_num == 2) {
- if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
- ||
- (coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (wifi_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT))
- wifi_rssi_state = BTC_RSSI_STATE_HIGH;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else {
- if (wifi_rssi < rssi_thresh)
- wifi_rssi_state = BTC_RSSI_STATE_LOW;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- } else if (level_num == 3) {
- if (rssi_thresh > rssi_thresh1) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], wifi RSSI thresh error!!\n");
- BTC_TRACE(trace_buf);
- return coex_sta->pre_wifi_rssi_state[index];
- }
-
- if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
- ||
- (coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (wifi_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT))
- wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else if ((coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_MEDIUM) ||
- (coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_STAY_MEDIUM)) {
- if (wifi_rssi >= (rssi_thresh1 +
- BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT))
- wifi_rssi_state = BTC_RSSI_STATE_HIGH;
- else if (wifi_rssi < rssi_thresh)
- wifi_rssi_state = BTC_RSSI_STATE_LOW;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
- } else {
- if (wifi_rssi < rssi_thresh1)
- wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- }
-
- coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state;
-
- return wifi_rssi_state;
-}
-
-void halbtc8821a2ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist)
-{
- static u32 bt_disable_cnt = 0;
- boolean bt_active = true, bt_disabled = false;
-
- /* This function check if bt is disabled */
-
- if (coex_sta->high_priority_tx == 0 &&
- coex_sta->high_priority_rx == 0 &&
- coex_sta->low_priority_tx == 0 &&
- coex_sta->low_priority_rx == 0)
- bt_active = false;
- if (coex_sta->high_priority_tx == 0xffff &&
- coex_sta->high_priority_rx == 0xffff &&
- coex_sta->low_priority_tx == 0xffff &&
- coex_sta->low_priority_rx == 0xffff)
- bt_active = false;
- if (bt_active) {
- bt_disable_cnt = 0;
- bt_disabled = false;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
- &bt_disabled);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is enabled !!\n");
- BTC_TRACE(trace_buf);
- } else {
- bt_disable_cnt++;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], bt all counters=0, %d times!!\n",
- bt_disable_cnt);
- BTC_TRACE(trace_buf);
- if (bt_disable_cnt >= 2) {
- bt_disabled = true;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
- &bt_disabled);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is disabled !!\n");
- BTC_TRACE(trace_buf);
- }
- }
- if (coex_sta->bt_disabled != bt_disabled) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is from %s to %s!!\n",
- (coex_sta->bt_disabled ? "disabled" : "enabled"),
- (bt_disabled ? "disabled" : "enabled"));
- BTC_TRACE(trace_buf);
- coex_sta->bt_disabled = bt_disabled;
- if (!bt_disabled) {
- } else {
- }
- }
-}
-
-void halbtc8821a2ant_limited_rx(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean rej_ap_agg_pkt,
- IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size)
-{
- boolean reject_rx_agg = rej_ap_agg_pkt;
- boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size;
- u8 rx_agg_size = agg_buf_size;
-
- /* ============================================ */
- /* Rx Aggregation related setting */
- /* ============================================ */
- btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT,
- &reject_rx_agg);
- /* decide BT control aggregation buf size or not */
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE,
- &bt_ctrl_rx_agg_size);
- /* aggregation buf size, only work when BT control Rx aggregation size. */
- btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size);
- /* real update aggregation setting */
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
-}
-
-void halbtc8821a2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist)
-{
- u32 reg_hp_txrx, reg_lp_txrx, u32tmp;
- u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
-
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
- reg_hp_txrx = 0x770;
- reg_lp_txrx = 0x774;
-
- u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
- reg_hp_tx = u32tmp & MASKLWORD;
- reg_hp_rx = (u32tmp & MASKHWORD) >> 16;
-
- u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
- reg_lp_tx = u32tmp & MASKLWORD;
- reg_lp_rx = (u32tmp & MASKHWORD) >> 16;
-
- coex_sta->high_priority_tx = reg_hp_tx;
- coex_sta->high_priority_rx = reg_hp_rx;
- coex_sta->low_priority_tx = reg_lp_tx;
- coex_sta->low_priority_rx = reg_lp_rx;
-
- if ((coex_sta->low_priority_rx >= 950) &&
- (coex_sta->low_priority_rx >= coex_sta->low_priority_tx) &&
- (!coex_sta->under_ips))
- bt_link_info->slave_role = true;
- else
- bt_link_info->slave_role = false;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], High Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n",
- reg_hp_txrx, reg_hp_tx, reg_hp_tx, reg_hp_rx, reg_hp_rx);
- BTC_TRACE(trace_buf);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Low Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n",
- reg_lp_txrx, reg_lp_tx, reg_lp_tx, reg_lp_rx, reg_lp_rx);
- BTC_TRACE(trace_buf);
-
- /* reset counter */
- btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
-}
-
-void halbtc8821a2ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist)
-{
- if (coex_sta->under_ips) {
- coex_sta->crc_ok_cck = 0;
- coex_sta->crc_ok_11g = 0;
- coex_sta->crc_ok_11n = 0;
- coex_sta->crc_ok_11n_agg = 0;
-
- coex_sta->crc_err_cck = 0;
- coex_sta->crc_err_11g = 0;
- coex_sta->crc_err_11n = 0;
- coex_sta->crc_err_11n_agg = 0;
- } else {
- coex_sta->crc_ok_cck = btcoexist->btc_read_4byte(btcoexist,
- 0xf88);
- coex_sta->crc_ok_11g = btcoexist->btc_read_2byte(btcoexist,
- 0xf94);
- coex_sta->crc_ok_11n = btcoexist->btc_read_2byte(btcoexist,
- 0xf90);
- coex_sta->crc_ok_11n_agg = btcoexist->btc_read_2byte(btcoexist,
- 0xfb8);
-
- coex_sta->crc_err_cck = btcoexist->btc_read_4byte(btcoexist,
- 0xf84);
- coex_sta->crc_err_11g = btcoexist->btc_read_2byte(btcoexist,
- 0xf96);
- coex_sta->crc_err_11n = btcoexist->btc_read_2byte(btcoexist,
- 0xf92);
- coex_sta->crc_err_11n_agg = btcoexist->btc_read_2byte(btcoexist,
- 0xfba);
- }
-
- /* reset counter */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xf16, 0x1, 0x1);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xf16, 0x1, 0x0);
-}
-
-void halbtc8821a2ant_query_bt_info(IN struct btc_coexist *btcoexist)
-{
- u8 h2c_parameter[1] = {0};
-
- coex_sta->c2h_bt_info_req_sent = true;
-
- h2c_parameter[0] |= BIT(0); /* trigger */
-
- btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter);
-}
-
-boolean halbtc8821a2ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist)
-{
- static boolean pre_wifi_busy = false, pre_under_4way = false,
- pre_bt_hs_on = false;
- boolean wifi_busy = false, under_4way = false, bt_hs_on = false;
- boolean wifi_connected = false;
- u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH;
-
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
- &under_4way);
-
- if (wifi_connected) {
- if (wifi_busy != pre_wifi_busy) {
- pre_wifi_busy = wifi_busy;
- return true;
- }
- if (under_4way != pre_under_4way) {
- pre_under_4way = under_4way;
- return true;
- }
- if (bt_hs_on != pre_bt_hs_on) {
- pre_bt_hs_on = bt_hs_on;
- return true;
- }
-
-
- wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 3,
- 2, BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0);
-
- if ((BTC_RSSI_STATE_HIGH == wifi_rssi_state) ||
- (BTC_RSSI_STATE_LOW == wifi_rssi_state))
- return true;
-
- }
-
- return false;
-}
-
-void halbtc8821a2ant_update_bt_link_info(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean bt_hs_on = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
-
- bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
- bt_link_info->sco_exist = coex_sta->sco_exist;
- bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
- bt_link_info->pan_exist = coex_sta->pan_exist;
- bt_link_info->hid_exist = coex_sta->hid_exist;
-
- /* work around for HS mode. */
- if (bt_hs_on) {
- bt_link_info->pan_exist = true;
- bt_link_info->bt_link_exist = true;
- }
-
- /* check if Sco only */
- if (bt_link_info->sco_exist &&
- !bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist &&
- !bt_link_info->hid_exist)
- bt_link_info->sco_only = true;
- else
- bt_link_info->sco_only = false;
-
- /* check if A2dp only */
- if (!bt_link_info->sco_exist &&
- bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist &&
- !bt_link_info->hid_exist)
- bt_link_info->a2dp_only = true;
- else
- bt_link_info->a2dp_only = false;
-
- /* check if Pan only */
- if (!bt_link_info->sco_exist &&
- !bt_link_info->a2dp_exist &&
- bt_link_info->pan_exist &&
- !bt_link_info->hid_exist)
- bt_link_info->pan_only = true;
- else
- bt_link_info->pan_only = false;
-
- /* check if Hid only */
- if (!bt_link_info->sco_exist &&
- !bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist &&
- bt_link_info->hid_exist)
- bt_link_info->hid_only = true;
- else
- bt_link_info->hid_only = false;
-}
-
-u8 halbtc8821a2ant_action_algorithm(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean bt_hs_on = false;
- u8 algorithm = BT_8821A_2ANT_COEX_ALGO_UNDEFINED;
- u8 num_of_diff_profile = 0;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
-
- if (!bt_link_info->bt_link_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], No BT link exists!!!\n");
- BTC_TRACE(trace_buf);
- return algorithm;
- }
-
- if (bt_link_info->sco_exist)
- num_of_diff_profile++;
- if (bt_link_info->hid_exist)
- num_of_diff_profile++;
- if (bt_link_info->pan_exist)
- num_of_diff_profile++;
- if (bt_link_info->a2dp_exist)
- num_of_diff_profile++;
-
- if (num_of_diff_profile == 1) {
- if (bt_link_info->sco_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO only\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8821A_2ANT_COEX_ALGO_SCO;
- } else {
- if (bt_link_info->hid_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], HID only\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8821A_2ANT_COEX_ALGO_HID;
- } else if (bt_link_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], A2DP only\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8821A_2ANT_COEX_ALGO_A2DP;
- } else if (bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], PAN(HS) only\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_2ANT_COEX_ALGO_PANHS;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], PAN(EDR) only\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_2ANT_COEX_ALGO_PANEDR;
- }
- }
- }
- } else if (num_of_diff_profile == 2) {
- if (bt_link_info->sco_exist) {
- if (bt_link_info->hid_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + HID\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8821A_2ANT_COEX_ALGO_SCO;
- } else if (bt_link_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + A2DP ==> SCO\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8821A_2ANT_COEX_ALGO_SCO;
- } else if (bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8821A_2ANT_COEX_ALGO_SCO;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8821A_2ANT_COEX_ALGO_SCO;
- }
- }
- } else {
- if (bt_link_info->hid_exist &&
- bt_link_info->a2dp_exist) {
- {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], HID + A2DP\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_2ANT_COEX_ALGO_HID_A2DP;
- }
- } else if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], HID + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8821A_2ANT_COEX_ALGO_HID;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], HID + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_2ANT_COEX_ALGO_PANEDR_HID;
- }
- } else if (bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_2ANT_COEX_ALGO_A2DP_PANHS;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], A2DP + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_2ANT_COEX_ALGO_PANEDR_A2DP;
- }
- }
- }
- } else if (num_of_diff_profile == 3) {
- if (bt_link_info->sco_exist) {
- if (bt_link_info->hid_exist &&
- bt_link_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + HID + A2DP ==> SCO\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8821A_2ANT_COEX_ALGO_SCO;
- } else if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + HID + PAN(HS) ==> SCO\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8821A_2ANT_COEX_ALGO_SCO;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + HID + PAN(EDR) ==> SCO\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8821A_2ANT_COEX_ALGO_SCO;
- }
- } else if (bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8821A_2ANT_COEX_ALGO_SCO;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8821A_2ANT_COEX_ALGO_SCO;
- }
- }
- } else {
- if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], HID + A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_2ANT_COEX_ALGO_HID_A2DP;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], HID + A2DP + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
- }
- }
- }
- } else if (num_of_diff_profile >= 3) {
- if (bt_link_info->sco_exist) {
- if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
-
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8821A_2ANT_COEX_ALGO_SCO;
- }
- }
- }
- }
-
- return algorithm;
-}
-
-void halbtc8821a2ant_set_fw_dac_swing_level(IN struct btc_coexist *btcoexist,
- IN u8 dac_swing_lvl)
-{
- u8 h2c_parameter[1] = {0};
-
- /* There are several type of dacswing */
- /* 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */
- h2c_parameter[0] = dac_swing_lvl;
-
- btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter);
-}
-
-void halbtc8821a2ant_set_fw_dec_bt_pwr(IN struct btc_coexist *btcoexist,
- IN u8 dec_bt_pwr_lvl)
-{
- u8 h2c_parameter[1] = {0};
-
- h2c_parameter[0] = dec_bt_pwr_lvl;
-
- btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter);
-}
-
-void halbtc8821a2ant_dec_bt_pwr(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 dec_bt_pwr_lvl)
-{
- coex_dm->cur_bt_dec_pwr_lvl = dec_bt_pwr_lvl;
-
- if (!force_exec) {
- if (coex_dm->pre_bt_dec_pwr_lvl == coex_dm->cur_bt_dec_pwr_lvl)
- return;
- }
- halbtc8821a2ant_set_fw_dec_bt_pwr(btcoexist,
- coex_dm->cur_bt_dec_pwr_lvl);
-
- coex_dm->pre_bt_dec_pwr_lvl = coex_dm->cur_bt_dec_pwr_lvl;
-}
-
-void halbtc8821a2ant_set_bt_auto_report(IN struct btc_coexist *btcoexist,
- IN boolean enable_auto_report)
-{
- u8 h2c_parameter[1] = {0};
-
- h2c_parameter[0] = 0;
-
- if (enable_auto_report)
- h2c_parameter[0] |= BIT(0);
-
- btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter);
-}
-
-void halbtc8821a2ant_bt_auto_report(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean enable_auto_report)
-{
- coex_dm->cur_bt_auto_report = enable_auto_report;
-
- if (!force_exec) {
- if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report)
- return;
- }
- halbtc8821a2ant_set_bt_auto_report(btcoexist,
- coex_dm->cur_bt_auto_report);
-
- coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report;
-}
-
-void halbtc8821a2ant_fw_dac_swing_lvl(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 fw_dac_swing_lvl)
-{
- coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl;
-
- if (!force_exec) {
- if (coex_dm->pre_fw_dac_swing_lvl ==
- coex_dm->cur_fw_dac_swing_lvl)
- return;
- }
-
- halbtc8821a2ant_set_fw_dac_swing_level(btcoexist,
- coex_dm->cur_fw_dac_swing_lvl);
-
- coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl;
-}
-
-void halbtc8821a2ant_set_sw_rf_rx_lpf_corner(IN struct btc_coexist *btcoexist,
- IN boolean rx_rf_shrink_on)
-{
- if (rx_rf_shrink_on) {
- /* Shrink RF Rx LPF corner */
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Shrink RF Rx LPF corner!!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, 0xfffff,
- 0xffffc);
- } else {
- /* Resume RF Rx LPF corner */
- /* After initialized, we can use coex_dm->bt_rf_0x1e_backup */
- if (btcoexist->initilized) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Resume RF Rx LPF corner!!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e,
- 0xfffff, coex_dm->bt_rf_0x1e_backup);
- }
- }
-}
-
-void halbtc8821a2ant_rf_shrink(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean rx_rf_shrink_on)
-{
- coex_dm->cur_rf_rx_lpf_shrink = rx_rf_shrink_on;
-
- if (!force_exec) {
- if (coex_dm->pre_rf_rx_lpf_shrink ==
- coex_dm->cur_rf_rx_lpf_shrink)
- return;
- }
- halbtc8821a2ant_set_sw_rf_rx_lpf_corner(btcoexist,
- coex_dm->cur_rf_rx_lpf_shrink);
-
- coex_dm->pre_rf_rx_lpf_shrink = coex_dm->cur_rf_rx_lpf_shrink;
-}
-
-void halbtc8821a2ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist
- *btcoexist, IN boolean low_penalty_ra)
-{
- u8 h2c_parameter[6] = {0};
-
- h2c_parameter[0] = 0x6; /* op_code, 0x6= Retry_Penalty */
-
- if (low_penalty_ra) {
- h2c_parameter[1] |= BIT(0);
- h2c_parameter[2] =
- 0x00; /* normal rate except MCS7/6/5, OFDM54/48/36 */
- h2c_parameter[3] = 0xf5; /* MCS7 or OFDM54 */
- h2c_parameter[4] = 0xa0; /* MCS6 or OFDM48 */
- h2c_parameter[5] = 0xa0; /* MCS5 or OFDM36 */
- /* h2c_parameter[3] = 0xf7; //MCS7 or OFDM54 */
- /* h2c_parameter[4] = 0xf8; //MCS6 or OFDM48 */
- /* h2c_parameter[5] = 0xf9; //MCS5 or OFDM36 */
- }
-
- btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter);
-}
-
-void halbtc8821a2ant_low_penalty_ra(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean low_penalty_ra)
-{
- coex_dm->cur_low_penalty_ra = low_penalty_ra;
-
- if (!force_exec) {
- if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra)
- return;
- }
- halbtc8821a2ant_set_sw_penalty_tx_rate_adaptive(btcoexist,
- coex_dm->cur_low_penalty_ra);
-
- coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra;
-}
-
-void halbtc8821a2ant_set_dac_swing_reg(IN struct btc_coexist *btcoexist,
- IN u32 level)
-{
- u8 val = (u8)level;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Write SwDacSwing = 0x%x\n", level);
- BTC_TRACE(trace_buf);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc5b, 0x3e, val);
-}
-
-void halbtc8821a2ant_set_sw_full_time_dac_swing(IN struct btc_coexist
- *btcoexist, IN boolean sw_dac_swing_on, IN u32 sw_dac_swing_lvl)
-{
- if (sw_dac_swing_on)
- halbtc8821a2ant_set_dac_swing_reg(btcoexist, sw_dac_swing_lvl);
- else
- halbtc8821a2ant_set_dac_swing_reg(btcoexist, 0x18);
-}
-
-
-void halbtc8821a2ant_dac_swing(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean dac_swing_on, IN u32 dac_swing_lvl)
-{
- coex_dm->cur_dac_swing_on = dac_swing_on;
- coex_dm->cur_dac_swing_lvl = dac_swing_lvl;
-
- if (!force_exec) {
- if ((coex_dm->pre_dac_swing_on == coex_dm->cur_dac_swing_on) &&
- (coex_dm->pre_dac_swing_lvl ==
- coex_dm->cur_dac_swing_lvl))
- return;
- }
- delay_ms(30);
- halbtc8821a2ant_set_sw_full_time_dac_swing(btcoexist, dac_swing_on,
- dac_swing_lvl);
-
- coex_dm->pre_dac_swing_on = coex_dm->cur_dac_swing_on;
- coex_dm->pre_dac_swing_lvl = coex_dm->cur_dac_swing_lvl;
-}
-
-void halbtc8821a2ant_set_adc_back_off(IN struct btc_coexist *btcoexist,
- IN boolean adc_back_off)
-{
- if (adc_back_off) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BB BackOff Level On!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x8db, 0x60, 0x3);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BB BackOff Level Off!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x8db, 0x60, 0x1);
- }
-}
-
-void halbtc8821a2ant_adc_back_off(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean adc_back_off)
-{
- coex_dm->cur_adc_back_off = adc_back_off;
-
- if (!force_exec) {
- if (coex_dm->pre_adc_back_off == coex_dm->cur_adc_back_off)
- return;
- }
- halbtc8821a2ant_set_adc_back_off(btcoexist, coex_dm->cur_adc_back_off);
-
- coex_dm->pre_adc_back_off = coex_dm->cur_adc_back_off;
-}
-
-void halbtc8821a2ant_set_agc_table(IN struct btc_coexist *btcoexist,
- IN boolean agc_table_en)
-{
- u8 rssi_adjust_val = 0;
-
- /* =================BB AGC Gain Table */
- if (agc_table_en) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BB Agc Table On!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6e1A0001);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6d1B0001);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6c1C0001);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6b1D0001);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6a1E0001);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x691F0001);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x68200001);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BB Agc Table Off!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xaa1A0001);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa91B0001);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa81C0001);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa71D0001);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa61E0001);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa51F0001);
- btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa4200001);
- }
-
-
- /* =================RF Gain */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xef, 0xfffff, 0x02000);
- if (agc_table_en) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Agc Table On!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff,
- 0x38fff);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff,
- 0x38ffe);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Agc Table Off!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff,
- 0x380c3);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff,
- 0x28ce6);
- }
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xef, 0xfffff, 0x0);
-
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xed, 0xfffff, 0x1);
- if (agc_table_en) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Agc Table On!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff,
- 0x38fff);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff,
- 0x38ffe);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Agc Table Off!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff,
- 0x380c3);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40, 0xfffff,
- 0x28ce6);
- }
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xed, 0xfffff, 0x0);
-
- /* set rssi_adjust_val for wifi module. */
- if (agc_table_en)
- rssi_adjust_val = 8;
- btcoexist->btc_set(btcoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON,
- &rssi_adjust_val);
-}
-
-void halbtc8821a2ant_agc_table(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean agc_table_en)
-{
- coex_dm->cur_agc_table_en = agc_table_en;
-
- if (!force_exec) {
- if (coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en)
- return;
- }
- halbtc8821a2ant_set_agc_table(btcoexist, agc_table_en);
-
- coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en;
-}
-
-void halbtc8821a2ant_set_coex_table(IN struct btc_coexist *btcoexist,
- IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc)
-{
- btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
-
- btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
-
- btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
-
- btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
-}
-
-void halbtc8821a2ant_coex_table(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4,
- IN u32 val0x6c8, IN u8 val0x6cc)
-{
- coex_dm->cur_val0x6c0 = val0x6c0;
- coex_dm->cur_val0x6c4 = val0x6c4;
- coex_dm->cur_val0x6c8 = val0x6c8;
- coex_dm->cur_val0x6cc = val0x6cc;
-
- if (!force_exec) {
- if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) &&
- (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) &&
- (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) &&
- (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc))
- return;
- }
- halbtc8821a2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8,
- val0x6cc);
-
- coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0;
- coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4;
- coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8;
- coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc;
-}
-
-void halbtc8821a2ant_coex_table_with_type(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- coex_sta->coex_table_type = type;
-
- switch (type) {
- case 0:
- halbtc8821a2ant_coex_table(btcoexist, force_exec,
- 0x55555555, 0x55555555, 0xffffff, 0x3);
- break;
- case 1:
- halbtc8821a2ant_coex_table(btcoexist, force_exec,
- 0x55555555, 0x5afa5afa, 0xffffff, 0x3);
- break;
- case 2:
- halbtc8821a2ant_coex_table(btcoexist, force_exec,
- 0x5ada5ada, 0x5ada5ada, 0xffffff, 0x3);
- break;
- case 3:
- halbtc8821a2ant_coex_table(btcoexist, force_exec,
- 0xaaaaaaaa, 0xaaaaaaaa, 0xffffff, 0x3);
- break;
- case 4:
- halbtc8821a2ant_coex_table(btcoexist, force_exec,
- 0xffffffff, 0xffffffff, 0xffffff, 0x3);
- break;
- case 5:
- halbtc8821a2ant_coex_table(btcoexist, force_exec,
- 0x5fff5fff, 0x5fff5fff, 0xffffff, 0x3);
- break;
- case 6:
- halbtc8821a2ant_coex_table(btcoexist, force_exec,
- 0x55ff55ff, 0x5a5a5a5a, 0xffffff, 0x3);
- break;
- case 7:
- halbtc8821a2ant_coex_table(btcoexist, force_exec,
- 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3);
- break;
- case 8:
- halbtc8821a2ant_coex_table(btcoexist, force_exec,
- 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3);
- break;
- case 9:
- halbtc8821a2ant_coex_table(btcoexist, force_exec,
- 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3);
- break;
- case 10:
- halbtc8821a2ant_coex_table(btcoexist, force_exec,
- 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3);
- break;
- case 11:
- halbtc8821a2ant_coex_table(btcoexist, force_exec,
- 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3);
- break;
- case 12:
- halbtc8821a2ant_coex_table(btcoexist, force_exec,
- 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3);
- break;
- case 13:
- halbtc8821a2ant_coex_table(btcoexist, force_exec,
- 0x5fff5fff, 0xaaaaaaaa, 0xffffff, 0x3);
- break;
- case 14:
- halbtc8821a2ant_coex_table(btcoexist, force_exec,
- 0x5fff5fff, 0x5ada5ada, 0xffffff, 0x3);
- break;
- case 15:
- halbtc8821a2ant_coex_table(btcoexist, force_exec,
- 0x55dd55dd, 0xaaaaaaaa, 0xffffff, 0x3);
- break;
- case 16:
- halbtc8821a2ant_coex_table(btcoexist, force_exec,
- 0x5fdf5fdf, 0x5fdb5fdb, 0xffffff, 0x3);
- break;
- case 17:
- halbtc8821a2ant_coex_table(btcoexist, force_exec,
- 0xfafafafa, 0xfafafafa, 0xffffff, 0x3);
- break;
- default:
- break;
- }
-}
-
-void halbtc8821a2ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist,
- IN boolean enable)
-{
- u8 h2c_parameter[1] = {0};
-
- if (enable) {
- h2c_parameter[0] |= BIT(0); /* function enable */
- }
-
- btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter);
-}
-
-void halbtc8821a2ant_set_lps_rpwm(IN struct btc_coexist *btcoexist,
- IN u8 lps_val, IN u8 rpwm_val)
-{
- u8 lps = lps_val;
- u8 rpwm = rpwm_val;
-
- btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps);
- btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm);
-}
-
-void halbtc8821a2ant_lps_rpwm(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val)
-{
- coex_dm->cur_lps = lps_val;
- coex_dm->cur_rpwm = rpwm_val;
-
- if (!force_exec) {
- if ((coex_dm->pre_lps == coex_dm->cur_lps) &&
- (coex_dm->pre_rpwm == coex_dm->cur_rpwm))
- return;
- }
- halbtc8821a2ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val);
-
- coex_dm->pre_lps = coex_dm->cur_lps;
- coex_dm->pre_rpwm = coex_dm->cur_rpwm;
-}
-
-void halbtc8821a2ant_ignore_wlan_act(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean enable)
-{
- coex_dm->cur_ignore_wlan_act = enable;
-
- if (!force_exec) {
- if (coex_dm->pre_ignore_wlan_act ==
- coex_dm->cur_ignore_wlan_act)
- return;
- }
- halbtc8821a2ant_set_fw_ignore_wlan_act(btcoexist, enable);
-
- coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
-}
-
-void halbtc8821a2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist,
- IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5)
-{
- u8 h2c_parameter[5] = {0};
-
- h2c_parameter[0] = byte1;
- h2c_parameter[1] = byte2;
- h2c_parameter[2] = byte3;
- h2c_parameter[3] = byte4;
- h2c_parameter[4] = byte5;
-
- coex_dm->ps_tdma_para[0] = byte1;
- coex_dm->ps_tdma_para[1] = byte2;
- coex_dm->ps_tdma_para[2] = byte3;
- coex_dm->ps_tdma_para[3] = byte4;
- coex_dm->ps_tdma_para[4] = byte5;
-
- btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
-}
-
-void halbtc8821a2ant_sw_mechanism1(IN struct btc_coexist *btcoexist,
- IN boolean shrink_rx_lpf, IN boolean low_penalty_ra,
- IN boolean limited_dig, IN boolean bt_lna_constrain)
-{
- /*
- u32 wifi_bw;
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- if(BTC_WIFI_BW_HT40 != wifi_bw)
- {
- if (shrink_rx_lpf)
- shrink_rx_lpf = false;
- }
- */
-
- /* halbtc8821a2ant_rf_shrink(btcoexist, NORMAL_EXEC, shrink_rx_lpf); */
- halbtc8821a2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra);
-}
-
-void halbtc8821a2ant_sw_mechanism2(IN struct btc_coexist *btcoexist,
- IN boolean agc_table_shift, IN boolean adc_back_off,
- IN boolean sw_dac_swing, IN u32 dac_swing_lvl)
-{
- /* halbtc8821a2ant_agc_table(btcoexist, NORMAL_EXEC, agc_table_shift); */
- /* halbtc8821a2ant_adc_back_off(btcoexist, NORMAL_EXEC, adc_back_off); */
- halbtc8821a2ant_dac_swing(btcoexist, NORMAL_EXEC, sw_dac_swing,
- dac_swing_lvl);
-}
-
-void halbtc8821a2ant_set_ant_path(IN struct btc_coexist *btcoexist,
- IN u8 ant_pos_type, IN boolean init_hwcfg, IN boolean wifi_off)
-{
- struct btc_board_info *board_info = &btcoexist->board_info;
- u32 u32tmp = 0;
- u8 h2c_parameter[2] = {0};
-
- if (init_hwcfg) {
- /* 0x4c[23]=0, 0x4c[24]=1 Antenna control by WL/BT */
- u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c);
- u32tmp &= ~BIT(23);
- u32tmp |= BIT(24);
- btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp);
-
- btcoexist->btc_write_4byte(btcoexist, 0x974, 0x3ff);
- /* btcoexist->btc_write_1byte(btcoexist, 0xcb4, 0x77); */
-
- if (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT) {
- /* tell firmware "antenna inverse" ==> WRONG firmware antenna control code.==>need fw to fix */
- h2c_parameter[0] = 1;
- h2c_parameter[1] = 1;
- btcoexist->btc_fill_h2c(btcoexist, 0x65, 2,
- h2c_parameter);
- } else {
- /* tell firmware "no antenna inverse" ==> WRONG firmware antenna control code.==>need fw to fix */
- h2c_parameter[0] = 0;
- h2c_parameter[1] = 1;
- btcoexist->btc_fill_h2c(btcoexist, 0x65, 2,
- h2c_parameter);
- }
- }
-
- /* ext switch setting */
- switch (ant_pos_type) {
- case BTC_ANT_WIFI_AT_MAIN:
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb7,
- 0x30, 0x1);
- break;
- case BTC_ANT_WIFI_AT_AUX:
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb7,
- 0x30, 0x2);
- break;
- }
-}
-
-void halbtc8821a2ant_ps_tdma(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean turn_on, IN u8 type)
-{
- u8 wifi_rssi_state1, bt_rssi_state;
-
-
- wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2,
- BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0);
- bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2,
- BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0);
-
- if (!(BTC_RSSI_HIGH(wifi_rssi_state1) &&
- BTC_RSSI_HIGH(bt_rssi_state)) && turn_on) {
- type = type + 100; /* for WiFi RSSI low or BT RSSI low */
- }
-
- coex_dm->cur_ps_tdma_on = turn_on;
- coex_dm->cur_ps_tdma = type;
-
- if (!force_exec) {
- if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) &&
- (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma))
- return;
- }
- if (turn_on) {
- switch (type) {
- case 1:
- default:
- /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x90); */
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x3c, 0x03, 0xf1, 0x90);
- break;
- case 2:
- /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x12, 0x12, 0xe1, 0x90); */
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x2d, 0x03, 0xf1, 0x90);
- break;
- case 3:
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x1c, 0x3, 0xf1, 0x90);
- break;
- case 4:
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x10, 0x03, 0xf1, 0x90);
- break;
- case 5:
- /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x1a, 0x1a, 0x60, 0x90); */
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x3c, 0x3, 0x70, 0x90);
- break;
- case 6:
- /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x12, 0x12, 0x60, 0x90); */
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x2d, 0x3, 0x70, 0x90);
- break;
- case 7:
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x1c, 0x3, 0x70, 0x90);
- break;
- case 8:
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xa3,
- 0x10, 0x3, 0x70, 0x90);
- break;
- case 9:
- /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x90); */
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x3c, 0x03, 0xf1, 0x90);
- break;
- case 10:
- /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x12, 0x12, 0xe1, 0x90); */
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x2d, 0x03, 0xf1, 0x90);
- break;
- case 11:
- /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0xa, 0xa, 0xe1, 0x90); */
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x1c, 0x3, 0xf1, 0x90);
- break;
- case 12:
- /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x5, 0x5, 0xe1, 0x90); */
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x10, 0x3, 0xf1, 0x90);
- break;
- case 13:
- /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x1a, 0x1a, 0x60, 0x90); */
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x3c, 0x3, 0x70, 0x90);
- break;
- case 14:
- /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x12, 0x12, 0x60, 0x90); */
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x2d, 0x3, 0x70, 0x90);
- break;
- case 15:
- /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0xa, 0xa, 0x60, 0x90); */
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x1c, 0x3, 0x70, 0x90);
- break;
- case 16:
- /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x5, 0x5, 0x60, 0x90); */
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x10, 0x3, 0x70, 0x90);
- break;
- case 17:
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xa3,
- 0x2f, 0x2f, 0x60, 0x90);
- break;
- case 18:
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x5, 0x5, 0xe1, 0x90);
- break;
- case 19:
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x25, 0x25, 0xe1, 0x90);
- break;
- case 20:
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x25, 0x25, 0x60, 0x90);
- break;
- case 21:
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x15, 0x03, 0x70, 0x90);
- break;
- case 23:
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x1e, 0x03, 0xf0, 0x14);
- break;
- case 24:
- case 124:
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3,
- 0x3c, 0x03, 0x70, 0x50);
- break;
- /* case25/case125 : for lenovo bt pan tp degrade<30% while wifi downlink */
- case 25:
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x14, 0x03, 0xf1, 0x90);
- break;
- case 26:
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x30, 0x03, 0xf1, 0x90);
- break;
- case 71:
- /* halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x90); */
-
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x3c, 0x03, 0xf1, 0x90);
- break;
- case 101:
- case 105:
- case 171:
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3,
- 0x3a, 0x03, 0x70, 0x50);
- break;
- case 102:
- case 106:
- case 110:
- case 114:
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3,
- 0x2d, 0x03, 0x70, 0x50);
- break;
- case 103:
- case 107:
- case 111:
- case 115:
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3,
- 0x1c, 0x03, 0x70, 0x50);
- break;
- case 104:
- case 108:
- case 112:
- case 116:
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3,
- 0x10, 0x03, 0x70, 0x50);
- break;
- case 109:
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x3c, 0x03, 0xf1, 0x90);
- break;
- case 113:
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x3c, 0x03, 0x70, 0x90);
- break;
- case 121:
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x15, 0x03, 0x70, 0x90);
- break;
- case 22:
- case 122:
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x35, 0x03, 0x71, 0x11);
- break;
- case 123:
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3,
- 0x1c, 0x03, 0x70, 0x54);
- break;
- /* case25/case125 : for lenovo bt pan tp degrade<30% while wifi downlink */
- case 125:
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3,
- 0x14, 0x03, 0x70, 0x50);
- break;
- case 126:
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0xd3,
- 0x30, 0x03, 0x70, 0x50);
- break;
- }
- } else {
- /* disable PS tdma */
- switch (type) {
- case 0:
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0x0,
- 0x0, 0x0, 0x40, 0x0);
- break;
- case 1:
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0x0,
- 0x0, 0x0, 0x48, 0x0);
- break;
- default:
- halbtc8821a2ant_set_fw_pstdma(btcoexist, 0x0,
- 0x0, 0x0, 0x40, 0x0);
- break;
- }
- }
-
- /* update pre state */
- coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on;
- coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
-}
-
-void halbtc8821a2ant_ps_tdma_check_for_power_save_state(
- IN struct btc_coexist *btcoexist, IN boolean new_ps_state)
-{
- u8 lps_mode = 0x0;
-
- btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode);
-
- if (lps_mode) { /* already under LPS state */
- if (new_ps_state) {
- /* keep state under LPS, do nothing. */
- } else {
- /* will leave LPS state, turn off psTdma first */
- halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 1);
- }
- } else { /* NO PS state */
- if (new_ps_state) {
- /* will enter LPS state, turn off psTdma first */
- halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 1);
- } else {
- /* keep state under NO PS state, do nothing. */
- }
- }
-}
-
-void halbtc8821a2ant_power_save_state(IN struct btc_coexist *btcoexist,
- IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val)
-{
- boolean low_pwr_disable = false;
-
- switch (ps_type) {
- case BTC_PS_WIFI_NATIVE:
- /* recover to original 32k low power setting */
- low_pwr_disable = false;
- btcoexist->btc_set(btcoexist,
- BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS,
- NULL);
- coex_sta->force_lps_on = false;
- break;
- case BTC_PS_LPS_ON:
- halbtc8821a2ant_ps_tdma_check_for_power_save_state(
- btcoexist, true);
- halbtc8821a2ant_lps_rpwm(btcoexist, NORMAL_EXEC,
- lps_val, rpwm_val);
- /* when coex force to enter LPS, do not enter 32k low power. */
- low_pwr_disable = true;
- btcoexist->btc_set(btcoexist,
- BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
- /* power save must executed before psTdma. */
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS,
- NULL);
- coex_sta->force_lps_on = true;
- break;
- case BTC_PS_LPS_OFF:
- halbtc8821a2ant_ps_tdma_check_for_power_save_state(
- btcoexist, false);
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS,
- NULL);
- coex_sta->force_lps_on = false;
- break;
- default:
- break;
- }
-}
-
-
-void halbtc8821a2ant_coex_all_off(IN struct btc_coexist *btcoexist)
-{
- /* fw all off */
- halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
- halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
- halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
- halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- /* sw all off */
- halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
-
- /* hw all off */
- /* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); */
- halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-}
-
-void halbtc8821a2ant_coex_under_5g(IN struct btc_coexist *btcoexist)
-{
- halbtc8821a2ant_coex_all_off(btcoexist);
-
- halbtc8821a2ant_ignore_wlan_act(btcoexist, NORMAL_EXEC, true);
-}
-
-void halbtc8821a2ant_init_coex_dm(IN struct btc_coexist *btcoexist)
-{
- /* force to reset coex mechanism */
- halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
- halbtc8821a2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 1);
- halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 6);
- halbtc8821a2ant_dec_bt_pwr(btcoexist, FORCE_EXEC, 0);
-
- halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
-}
-
-void halbtc8821a2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state;
- boolean wifi_connected = false;
- boolean low_pwr_disable = true;
- boolean scan = false, link = false, roam = false;
-
-
- wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15,
- 0);
- wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2,
- BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0);
- bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2,
- BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0);
-
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
-
-
- halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
-
- if (scan || link || roam) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi link process + BT Inq/Page!!\n");
- BTC_TRACE(trace_buf);
- halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 15);
- halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22);
- } else if (wifi_connected) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi connected + BT Inq/Page!!\n");
- BTC_TRACE(trace_buf);
- halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 15);
- halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi no-link + BT Inq/Page!!\n");
- BTC_TRACE(trace_buf);
- halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
- halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
- }
-
- halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 6);
- halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
-
-}
-
-
-void halbtc8821a2ant_action_wifi_link_process(IN struct btc_coexist *btcoexist)
-{
- u8 u8tmpa, u8tmpb;
-
- halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 15);
- halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22);
-
- halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
-
-
-
- u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765);
- u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x76e);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], 0x765=0x%x, 0x76e=0x%x\n", u8tmpa,
- u8tmpb);
- BTC_TRACE(trace_buf);
-}
-
-boolean halbtc8821a2ant_action_wifi_idle_process(IN struct btc_coexist
- *btcoexist)
-{
- u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state;
- u8 ap_num = 0;
-
- wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15,
- 0);
- /* wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2, BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); */
- wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2,
- BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES - 20, 0);
- bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2,
- BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, &ap_num);
-
- /* define the office environment */
- if (BTC_RSSI_HIGH(wifi_rssi_state1) &&
- (coex_sta->hid_exist == true) &&
- (coex_sta->a2dp_exist == true)) {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi idle process for BT HID+A2DP exist!!\n");
- BTC_TRACE(trace_buf);
-
- halbtc8821a2ant_dac_swing(btcoexist, NORMAL_EXEC, true, 0x6);
- halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- /* sw all off */
- halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false,
- false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false,
- 0x18);
-
- halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
-
- return true;
- }
-
- /* */
- else if (coex_sta->pan_exist == true) {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi idle process for BT PAN exist!!\n");
- BTC_TRACE(trace_buf);
-
- halbtc8821a2ant_dac_swing(btcoexist, NORMAL_EXEC, true, 0x6);
- halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- /* sw all off */
- halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false,
- false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false,
- 0x18);
-
- halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
-
- return true;
- }
-
- else {
- halbtc8821a2ant_dac_swing(btcoexist, NORMAL_EXEC, true, 0x18);
- return false;
- }
-
-
-}
-
-
-
-boolean halbtc8821a2ant_is_common_action(IN struct btc_coexist *btcoexist)
-{
- boolean common = false, wifi_connected = false, wifi_busy = false;
- boolean bt_hs_on = false, low_pwr_disable = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- if (!wifi_connected) {
- low_pwr_disable = false;
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
- halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
- 0x8);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi non-connected idle!!\n");
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff,
- 0x0);
- halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
- halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
- halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false,
- false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false,
- 0x18);
-
- common = true;
- } else {
- if (BT_8821A_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
- coex_dm->bt_status) {
- low_pwr_disable = false;
- btcoexist->btc_set(btcoexist,
- BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
- halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC,
- false, false, 0x8);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi connected + BT non connected-idle!!\n");
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1,
- 0xfffff, 0x0);
- halbtc8821a2ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 0);
-
- halbtc8821a2ant_power_save_state(btcoexist,
- BTC_PS_WIFI_NATIVE, 0x0, 0x0);
- halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 1);
- halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC,
- 0xb);
- halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false,
- false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
-
- common = true;
- } else if (BT_8821A_2ANT_BT_STATUS_CONNECTED_IDLE ==
- coex_dm->bt_status) {
- low_pwr_disable = true;
- btcoexist->btc_set(btcoexist,
- BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
-
- if (bt_hs_on)
- return false;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi connected + BT connected-idle!!\n");
- BTC_TRACE(trace_buf);
- halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC,
- false, false, 0x8);
-
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1,
- 0xfffff, 0x0);
- halbtc8821a2ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 0);
-
- halbtc8821a2ant_power_save_state(btcoexist,
- BTC_PS_WIFI_NATIVE, 0x0, 0x0);
- halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 1);
- halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC,
- 0xb);
- halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8821a2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
-
- common = true;
- } else {
- low_pwr_disable = true;
- btcoexist->btc_set(btcoexist,
- BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
-
- if (wifi_busy) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi Connected-Busy + BT Busy!!\n");
- BTC_TRACE(trace_buf);
- common = false;
- /* common = halbtc8821a2ant_action_wifi_idle_process(btcoexist); */
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi Connected-Idle + BT Busy!!\n");
- BTC_TRACE(trace_buf);
- /* common = false; */
- common = halbtc8821a2ant_action_wifi_idle_process(
- btcoexist);
- }
- }
- }
-
- return common;
-}
-void halbtc8821a2ant_tdma_duration_adjust(IN struct btc_coexist *btcoexist,
- IN boolean sco_hid, IN boolean tx_pause, IN u8 max_interval)
-{
- static s32 up, dn, m, n, wait_count;
- s32 result; /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */
- u8 retry_count = 0;
-
- if (!coex_dm->auto_tdma_adjust) {
- coex_dm->auto_tdma_adjust = true;
- {
- if (sco_hid) {
- if (tx_pause) {
- if (max_interval == 1) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 13);
- coex_dm->ps_tdma_du_adj_type =
- 13;
- } else if (max_interval == 2) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 14);
- coex_dm->ps_tdma_du_adj_type =
- 14;
- } else if (max_interval == 3) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- }
- } else {
- if (max_interval == 1) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 9);
- coex_dm->ps_tdma_du_adj_type =
- 9;
- } else if (max_interval == 2) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 10);
- coex_dm->ps_tdma_du_adj_type =
- 10;
- } else if (max_interval == 3) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- }
- }
- } else {
- if (tx_pause) {
- if (max_interval == 1) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 5);
- coex_dm->ps_tdma_du_adj_type =
- 5;
- } else if (max_interval == 2) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 6);
- coex_dm->ps_tdma_du_adj_type =
- 6;
- } else if (max_interval == 3) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- }
- } else {
- if (max_interval == 1) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 1);
- coex_dm->ps_tdma_du_adj_type =
- 1;
- } else if (max_interval == 2) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 2);
- coex_dm->ps_tdma_du_adj_type =
- 2;
- } else if (max_interval == 3) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- }
- }
- }
- }
- /* ============ */
- up = 0;
- dn = 0;
- m = 1;
- n = 3;
- result = 0;
- wait_count = 0;
- } else {
- /* accquire the BT TRx retry count from BT_Info byte2 */
- retry_count = coex_sta->bt_retry_cnt;
- result = 0;
- wait_count++;
-
- if (retry_count ==
- 0) { /* no retry in the last 2-second duration */
- up++;
- dn--;
-
- if (dn <= 0)
- dn = 0;
-
- if (up >= n) { /* if ³sÄò n Ó2¬í retry count¬°0, «h½Õ¼eWiFi duration */
- wait_count = 0;
- n = 3;
- up = 0;
- dn = 0;
- result = 1;
- }
- } else if (retry_count <=
- 3) { /* <=3 retry in the last 2-second duration */
- up--;
- dn++;
-
- if (up <= 0)
- up = 0;
-
- if (dn == 2) { /* if ³sÄò 2 Ó2¬í retry count< 3, «h½Õ¯¶WiFi duration */
- if (wait_count <= 2)
- m++; /* ÁקK¤@ª½¦b¨âÓlevel¤¤¨Ó¦^ */
- else
- m = 1;
-
- if (m >= 20) /* m ³Ì¤jÈ = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration. */
- m = 20;
-
- n = 3 * m;
- up = 0;
- dn = 0;
- wait_count = 0;
- result = -1;
- }
- } else { /* retry count > 3, ¥un1¦¸ retry count > 3, «h½Õ¯¶WiFi duration */
- if (wait_count == 1)
- m++; /* ÁקK¤@ª½¦b¨âÓlevel¤¤¨Ó¦^ */
- else
- m = 1;
-
- if (m >= 20) /* m ³Ì¤jÈ = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration. */
- m = 20;
-
- n = 3 * m;
- up = 0;
- dn = 0;
- wait_count = 0;
- result = -1;
- }
-
- if (max_interval == 1) {
- if (tx_pause) {
- if (coex_dm->cur_ps_tdma == 71) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 5);
- coex_dm->ps_tdma_du_adj_type = 5;
- } else if (coex_dm->cur_ps_tdma == 1) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 5);
- coex_dm->ps_tdma_du_adj_type = 5;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 6);
- coex_dm->ps_tdma_du_adj_type = 6;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 7);
- coex_dm->ps_tdma_du_adj_type = 7;
- } else if (coex_dm->cur_ps_tdma == 4) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 8);
- coex_dm->ps_tdma_du_adj_type = 8;
- }
- if (coex_dm->cur_ps_tdma == 9) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 13);
- coex_dm->ps_tdma_du_adj_type = 13;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 14);
- coex_dm->ps_tdma_du_adj_type = 14;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 15);
- coex_dm->ps_tdma_du_adj_type = 15;
- } else if (coex_dm->cur_ps_tdma == 12) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 16);
- coex_dm->ps_tdma_du_adj_type = 16;
- }
-
- if (result == -1) {
- if (coex_dm->cur_ps_tdma == 5) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 6);
- coex_dm->ps_tdma_du_adj_type =
- 6;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 8);
- coex_dm->ps_tdma_du_adj_type =
- 8;
- } else if (coex_dm->cur_ps_tdma == 13) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 14);
- coex_dm->ps_tdma_du_adj_type =
- 14;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 16);
- coex_dm->ps_tdma_du_adj_type =
- 16;
- }
- } else if (result == 1) {
- if (coex_dm->cur_ps_tdma == 8) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 6);
- coex_dm->ps_tdma_du_adj_type =
- 6;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 5);
- coex_dm->ps_tdma_du_adj_type =
- 5;
- } else if (coex_dm->cur_ps_tdma == 16) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 14);
- coex_dm->ps_tdma_du_adj_type =
- 14;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 13);
- coex_dm->ps_tdma_du_adj_type =
- 13;
- }
- }
- } else {
- if (coex_dm->cur_ps_tdma == 5) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 71);
- coex_dm->ps_tdma_du_adj_type = 71;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 2);
- coex_dm->ps_tdma_du_adj_type = 2;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 3);
- coex_dm->ps_tdma_du_adj_type = 3;
- } else if (coex_dm->cur_ps_tdma == 8) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 4);
- coex_dm->ps_tdma_du_adj_type = 4;
- }
- if (coex_dm->cur_ps_tdma == 13) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 9);
- coex_dm->ps_tdma_du_adj_type = 9;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 10);
- coex_dm->ps_tdma_du_adj_type = 10;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 11);
- coex_dm->ps_tdma_du_adj_type = 11;
- } else if (coex_dm->cur_ps_tdma == 16) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 12);
- coex_dm->ps_tdma_du_adj_type = 12;
- }
-
- if (result == -1) {
- if (coex_dm->cur_ps_tdma == 71) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 1);
- coex_dm->ps_tdma_du_adj_type =
- 1;
- } else if (coex_dm->cur_ps_tdma == 1) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 2);
- coex_dm->ps_tdma_du_adj_type =
- 2;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 4);
- coex_dm->ps_tdma_du_adj_type =
- 4;
- } else if (coex_dm->cur_ps_tdma == 9) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 10);
- coex_dm->ps_tdma_du_adj_type =
- 10;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 12);
- coex_dm->ps_tdma_du_adj_type =
- 12;
- }
- } else if (result == 1) {
- if (coex_dm->cur_ps_tdma == 4) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 2);
- coex_dm->ps_tdma_du_adj_type =
- 2;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 1);
- coex_dm->ps_tdma_du_adj_type =
- 1;
- } else if (coex_dm->cur_ps_tdma == 1) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 71);
- coex_dm->ps_tdma_du_adj_type =
- 71;
- } else if (coex_dm->cur_ps_tdma == 12) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 10);
- coex_dm->ps_tdma_du_adj_type =
- 10;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 9);
- coex_dm->ps_tdma_du_adj_type =
- 9;
- }
- }
- }
- } else if (max_interval == 2) {
- if (tx_pause) {
- if (coex_dm->cur_ps_tdma == 1) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 6);
- coex_dm->ps_tdma_du_adj_type = 6;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 6);
- coex_dm->ps_tdma_du_adj_type = 6;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 7);
- coex_dm->ps_tdma_du_adj_type = 7;
- } else if (coex_dm->cur_ps_tdma == 4) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 8);
- coex_dm->ps_tdma_du_adj_type = 8;
- }
- if (coex_dm->cur_ps_tdma == 9) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 14);
- coex_dm->ps_tdma_du_adj_type = 14;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 14);
- coex_dm->ps_tdma_du_adj_type = 14;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 15);
- coex_dm->ps_tdma_du_adj_type = 15;
- } else if (coex_dm->cur_ps_tdma == 12) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 16);
- coex_dm->ps_tdma_du_adj_type = 16;
- }
- if (result == -1) {
- if (coex_dm->cur_ps_tdma == 5) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 6);
- coex_dm->ps_tdma_du_adj_type =
- 6;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 8);
- coex_dm->ps_tdma_du_adj_type =
- 8;
- } else if (coex_dm->cur_ps_tdma == 13) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 14);
- coex_dm->ps_tdma_du_adj_type =
- 14;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 16);
- coex_dm->ps_tdma_du_adj_type =
- 16;
- }
- } else if (result == 1) {
- if (coex_dm->cur_ps_tdma == 8) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 6);
- coex_dm->ps_tdma_du_adj_type =
- 6;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 6);
- coex_dm->ps_tdma_du_adj_type =
- 6;
- } else if (coex_dm->cur_ps_tdma == 16) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 14);
- coex_dm->ps_tdma_du_adj_type =
- 14;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 14);
- coex_dm->ps_tdma_du_adj_type =
- 14;
- }
- }
- } else {
- if (coex_dm->cur_ps_tdma == 5) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 2);
- coex_dm->ps_tdma_du_adj_type = 2;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 2);
- coex_dm->ps_tdma_du_adj_type = 2;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 3);
- coex_dm->ps_tdma_du_adj_type = 3;
- } else if (coex_dm->cur_ps_tdma == 8) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 4);
- coex_dm->ps_tdma_du_adj_type = 4;
- }
- if (coex_dm->cur_ps_tdma == 13) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 10);
- coex_dm->ps_tdma_du_adj_type = 10;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 10);
- coex_dm->ps_tdma_du_adj_type = 10;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 11);
- coex_dm->ps_tdma_du_adj_type = 11;
- } else if (coex_dm->cur_ps_tdma == 16) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 12);
- coex_dm->ps_tdma_du_adj_type = 12;
- }
- if (result == -1) {
- if (coex_dm->cur_ps_tdma == 1) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 2);
- coex_dm->ps_tdma_du_adj_type =
- 2;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 4);
- coex_dm->ps_tdma_du_adj_type =
- 4;
- } else if (coex_dm->cur_ps_tdma == 9) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 10);
- coex_dm->ps_tdma_du_adj_type =
- 10;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 12);
- coex_dm->ps_tdma_du_adj_type =
- 12;
- }
- } else if (result == 1) {
- if (coex_dm->cur_ps_tdma == 4) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 2);
- coex_dm->ps_tdma_du_adj_type =
- 2;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 2);
- coex_dm->ps_tdma_du_adj_type =
- 2;
- } else if (coex_dm->cur_ps_tdma == 12) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 10);
- coex_dm->ps_tdma_du_adj_type =
- 10;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 10);
- coex_dm->ps_tdma_du_adj_type =
- 10;
- }
- }
- }
- } else if (max_interval == 3) {
- if (tx_pause) {
- if (coex_dm->cur_ps_tdma == 1) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 7);
- coex_dm->ps_tdma_du_adj_type = 7;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 7);
- coex_dm->ps_tdma_du_adj_type = 7;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 7);
- coex_dm->ps_tdma_du_adj_type = 7;
- } else if (coex_dm->cur_ps_tdma == 4) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 8);
- coex_dm->ps_tdma_du_adj_type = 8;
- }
- if (coex_dm->cur_ps_tdma == 9) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 15);
- coex_dm->ps_tdma_du_adj_type = 15;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 15);
- coex_dm->ps_tdma_du_adj_type = 15;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 15);
- coex_dm->ps_tdma_du_adj_type = 15;
- } else if (coex_dm->cur_ps_tdma == 12) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 16);
- coex_dm->ps_tdma_du_adj_type = 16;
- }
- if (result == -1) {
- if (coex_dm->cur_ps_tdma == 5) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 8);
- coex_dm->ps_tdma_du_adj_type =
- 8;
- } else if (coex_dm->cur_ps_tdma == 13) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 16);
- coex_dm->ps_tdma_du_adj_type =
- 16;
- }
- } else if (result == 1) {
- if (coex_dm->cur_ps_tdma == 8) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 16) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- }
- }
- } else {
- if (coex_dm->cur_ps_tdma == 5) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 3);
- coex_dm->ps_tdma_du_adj_type = 3;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 3);
- coex_dm->ps_tdma_du_adj_type = 3;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 3);
- coex_dm->ps_tdma_du_adj_type = 3;
- } else if (coex_dm->cur_ps_tdma == 8) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 4);
- coex_dm->ps_tdma_du_adj_type = 4;
- }
- if (coex_dm->cur_ps_tdma == 13) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 11);
- coex_dm->ps_tdma_du_adj_type = 11;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 11);
- coex_dm->ps_tdma_du_adj_type = 11;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 11);
- coex_dm->ps_tdma_du_adj_type = 11;
- } else if (coex_dm->cur_ps_tdma == 16) {
- halbtc8821a2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 12);
- coex_dm->ps_tdma_du_adj_type = 12;
- }
- if (result == -1) {
- if (coex_dm->cur_ps_tdma == 1) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 4);
- coex_dm->ps_tdma_du_adj_type =
- 4;
- } else if (coex_dm->cur_ps_tdma == 9) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 12);
- coex_dm->ps_tdma_du_adj_type =
- 12;
- }
- } else if (result == 1) {
- if (coex_dm->cur_ps_tdma == 4) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 12) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8821a2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- }
- }
- }
- }
- }
-
- /* if current PsTdma not match with the recorded one (when scan, dhcp...), */
- /* then we have to adjust it back to the previous record one. */
- if (coex_dm->cur_ps_tdma != coex_dm->ps_tdma_du_adj_type) {
- boolean scan = false, link = false, roam = false;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], PsTdma type dismatch!!!, cur_ps_tdma=%d, recordPsTdma=%d\n",
- coex_dm->cur_ps_tdma, coex_dm->ps_tdma_du_adj_type);
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
-
- if (!scan && !link && !roam)
- halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- coex_dm->ps_tdma_du_adj_type);
- else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n");
- BTC_TRACE(trace_buf);
- }
- }
-}
-
-/* SCO only or SCO+PAN(HS) */
-void halbtc8821a2ant_action_sco(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- u8 wifi_rssi_state, bt_rssi_state;
- u32 wifi_bw;
-
- wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15,
- 0);
- bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2,
- BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0);
-
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
-
- halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
-
- halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 4);
-
- if (BTC_RSSI_HIGH(bt_rssi_state))
- halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- else
- halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- if (BTC_WIFI_BW_LEGACY == wifi_bw) /* for SCO quality at 11b/g mode */
- halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
- else { /* for SCO quality & wifi performance balance at 11n mode */
- if (BTC_WIFI_BW_HT40 == wifi_bw)
- halbtc8821a2ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 8);
- else {
- if (bt_link_info->sco_only)
- halbtc8821a2ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 17);
- else
- halbtc8821a2ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 12);
- }
- }
-
- halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
- halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 0); /* for voice quality */
-
- /* sw mechanism */
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8821a2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
- true, 0x18);
- } else {
- halbtc8821a2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
- true, 0x18);
- }
- } else {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8821a2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
- true, 0x18);
- } else {
- halbtc8821a2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
- true, 0x18);
- }
- }
-}
-
-
-void halbtc8821a2ant_action_hid(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state, bt_rssi_state;
- u32 wifi_bw;
-
- wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15,
- 0);
- bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2,
- BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0);
-
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
-
- halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
-
- halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
- if (BTC_RSSI_HIGH(bt_rssi_state))
- halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- else
- halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- if (BTC_WIFI_BW_LEGACY == wifi_bw) /* for HID at 11b/g mode */
- halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
- else /* for HID quality & wifi performance balance at 11n mode */
- halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
-
- halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
-
- halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 24);
-
- /* sw mechanism */
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8821a2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8821a2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- } else {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8821a2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8821a2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- }
-}
-
-/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */
-void halbtc8821a2ant_action_a2dp(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state;
- u32 wifi_bw;
- u8 ap_num = 0;
-
- wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15,
- 0);
- wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2,
- BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0);
- bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2,
- BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, &ap_num);
-
- /* define the office environment */
- if ((ap_num >= 10) && BTC_RSSI_HIGH(wifi_rssi_state1) &&
- BTC_RSSI_HIGH(bt_rssi_state)) {
- /* dbg_print(" AP#>10(%d)\n", ap_num); */
- halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
-
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff,
- 0x0);
- halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
- 0x8);
- halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
- halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
-
- halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- /* halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); */
- halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 23);
-
- /* sw mechanism */
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- halbtc8821a2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
- true, 0x6);
- } else {
- halbtc8821a2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
- true, 0x6);
- }
- return;
-
- }
-
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
- halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
-
- halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
- if (BTC_RSSI_HIGH(bt_rssi_state))
- halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- else
- halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
-
- if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) {
- halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
- halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- } else {
- halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 13);
- halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50,
- 0x4);
- }
-
-
- if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- /* halbtc8821a2ant_tdma_duration_adjust(btcoexist, false, false, 1); */
- halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 23);
- } else {
- /* halbtc8821a2ant_tdma_duration_adjust(btcoexist, false, true, 1); */
- halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 23);
- }
-
- /* sw mechanism */
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8821a2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8821a2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- } else {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8821a2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8821a2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- }
-}
-
-void halbtc8821a2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state;
- u32 wifi_bw;
-
- wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15,
- 0);
- wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2,
- BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0);
- bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2,
- BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0);
-
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
-
- halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
-
- halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
- if (BTC_RSSI_HIGH(bt_rssi_state))
- halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- else
- halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) {
- halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
- halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- } else {
- halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 13);
- halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50,
- 0x4);
- }
-
- halbtc8821a2ant_tdma_duration_adjust(btcoexist, false, true, 2);
-
- /* sw mechanism */
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8821a2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8821a2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- } else {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8821a2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8821a2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- }
-}
-
-void halbtc8821a2ant_action_pan_edr(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state;
- u32 wifi_bw;
-
- wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15,
- 0);
- wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2,
- BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0);
- bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2,
- BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0);
-
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
-
- halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
-
- halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
- if (BTC_RSSI_HIGH(bt_rssi_state))
- halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- else
- halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) {
- halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 10);
- halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- } else {
- halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 13);
- halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50,
- 0x4);
- }
-
- if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH))
- halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 26);
- else
- halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 26);
-
- /* sw mechanism */
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8821a2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8821a2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- } else {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8821a2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8821a2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- }
-}
-
-
-/* PAN(HS) only */
-void halbtc8821a2ant_action_pan_hs(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state;
- u32 wifi_bw;
-
- wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15,
- 0);
- wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2,
- BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0);
- bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2,
- BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0);
-
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
-
- halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
-
- halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
- if (BTC_RSSI_HIGH(bt_rssi_state))
- halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- else
- halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
-
- halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
- halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8821a2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8821a2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- } else {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8821a2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8821a2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- }
-}
-
-/* PAN(EDR)+A2DP */
-void halbtc8821a2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state;
- u32 wifi_bw;
-
- wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15,
- 0);
- wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2,
- BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0);
- bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2,
- BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0);
-
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
-
- halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
-
- halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
- if (BTC_RSSI_HIGH(bt_rssi_state))
- halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- else
- halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state))
- halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- else
- halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50,
- 0x4);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 12);
-
- if (BTC_WIFI_BW_HT40 == wifi_bw)
- halbtc8821a2ant_tdma_duration_adjust(btcoexist, false,
- true, 3);
- else
- halbtc8821a2ant_tdma_duration_adjust(btcoexist, false,
- false, 3);
- } else {
- halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 13);
- halbtc8821a2ant_tdma_duration_adjust(btcoexist, false, true, 3);
- }
-
- /* sw mechanism */
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8821a2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8821a2ant_sw_mechanism1(btcoexist, true, false,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- } else {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8821a2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8821a2ant_sw_mechanism1(btcoexist, false, false,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- }
-}
-
-void halbtc8821a2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state;
- u32 wifi_bw;
-
- wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15,
- 0);
- wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2,
- BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0);
- bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2,
- BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0);
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
-
- if (BTC_RSSI_HIGH(bt_rssi_state))
- halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- else
- halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) {
- halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
- halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- } else {
- halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 14);
- halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50,
- 0x4);
- }
-
- if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC,
- 3);
- /* halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 11); */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1,
- 0xfffff, 0x780);
- } else {
- halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC,
- 6);
- /* halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1,
- 0xfffff, 0x0);
- }
- halbtc8821a2ant_tdma_duration_adjust(btcoexist, true, false, 2);
- } else {
- halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
- /* halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 14); */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff,
- 0x0);
- halbtc8821a2ant_tdma_duration_adjust(btcoexist, true, true, 2);
- }
-
- /* sw mechanism */
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8821a2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8821a2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- } else {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8821a2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8821a2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- }
-}
-
-/* HID+A2DP+PAN(EDR) */
-void halbtc8821a2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state;
- u32 wifi_bw;
-
- wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15,
- 0);
- wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2,
- BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0);
- bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2,
- BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0);
-
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
-
- halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
-
- halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
- if (BTC_RSSI_HIGH(bt_rssi_state))
- halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- else
- halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) {
- halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
- halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- } else {
- halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 14);
- halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50,
- 0x4);
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- if (BTC_WIFI_BW_HT40 == wifi_bw)
- halbtc8821a2ant_tdma_duration_adjust(btcoexist, true,
- true, 3);
- else
- halbtc8821a2ant_tdma_duration_adjust(btcoexist, true,
- false, 3);
- } else
- halbtc8821a2ant_tdma_duration_adjust(btcoexist, true, true, 3);
-
- /* sw mechanism */
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8821a2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8821a2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- } else {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8821a2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8821a2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- }
-}
-
-void halbtc8821a2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state;
- u32 wifi_bw;
- u8 ap_num = 0;
-
- wifi_rssi_state = halbtc8821a2ant_wifi_rssi_state(btcoexist, 0, 2, 15,
- 0);
- /* bt_rssi_state = halbtc8821a2ant_bt_rssi_state(2, 29, 0); */
- wifi_rssi_state1 = halbtc8821a2ant_wifi_rssi_state(btcoexist, 1, 2,
- BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0);
- bt_rssi_state = halbtc8821a2ant_bt_rssi_state(3,
- BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 37);
-
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
-
- halbtc8821a2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true, 0x5);
-
- halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- if (BTC_WIFI_BW_LEGACY == wifi_bw) {
- if (BTC_RSSI_HIGH(bt_rssi_state))
- halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- else if (BTC_RSSI_MEDIUM(bt_rssi_state))
- halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- else
- halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
- } else {
- /* only 802.11N mode we have to dec bt power to 4 degree */
- if (BTC_RSSI_HIGH(bt_rssi_state)) {
- btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
- &ap_num);
- /* need to check ap Number of Not */
- if (ap_num < 10)
- halbtc8821a2ant_dec_bt_pwr(btcoexist,
- NORMAL_EXEC, 4);
- else
- halbtc8821a2ant_dec_bt_pwr(btcoexist,
- NORMAL_EXEC, 2);
- } else if (BTC_RSSI_MEDIUM(bt_rssi_state))
- halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
- else
- halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
- }
-
- if (BTC_RSSI_HIGH(wifi_rssi_state1) && BTC_RSSI_HIGH(bt_rssi_state)) {
- halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
- halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
- 0x0, 0x0);
- } else {
- halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 14);
- halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50,
- 0x4);
- }
-
- if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- /* halbtc8821a2ant_tdma_duration_adjust(btcoexist, true, false, 3); */
- halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 23);
- } else {
- /* halbtc8821a2ant_tdma_duration_adjust(btcoexist, true, true, 3); */
- halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 23);
- }
-
- /* sw mechanism */
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8821a2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8821a2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- } else {
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8821a2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, true, false,
- false, 0x18);
- } else {
- halbtc8821a2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
- }
- }
-}
-
-void halbtc8821a2ant_action_bt_whck_test(IN struct btc_coexist *btcoexist)
-{
- halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- /* sw all off */
- halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
-
- halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
-
- halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
- halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-}
-
-void halbtc8821a2ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist)
-{
- halbtc8821a2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
- halbtc8821a2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- /* sw all off */
- halbtc8821a2ant_sw_mechanism1(btcoexist, false, false, false, false);
- halbtc8821a2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
-
- /* hw all off */
- /* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); */
- halbtc8821a2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8821a2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
- halbtc8821a2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
-}
-
-void halbtc8821a2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist)
-{
- boolean wifi_under_5g = false;
- u8 algorithm = 0;
- u32 num_of_wifi_link = 0;
- u32 wifi_link_status = 0;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean miracast_plus_bt = false;
- boolean scan = false, link = false, roam = false;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism()===>\n");
- BTC_TRACE(trace_buf);
-
- if (btcoexist->manual_control) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
- if (wifi_under_5g) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism(), run 5G coex setting!!<===\n");
- BTC_TRACE(trace_buf);
- halbtc8821a2ant_coex_under_5g(btcoexist);
- return;
- }
-
- if (coex_sta->under_ips) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], wifi is under IPS !!!\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- if (coex_sta->bt_whck_test) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is under WHCK TEST!!!\n");
- BTC_TRACE(trace_buf);
- halbtc8821a2ant_action_bt_whck_test(btcoexist);
- return;
- }
-
- algorithm = halbtc8821a2ant_action_algorithm(btcoexist);
- if (coex_sta->c2h_bt_inquiry_page &&
- (BT_8821A_2ANT_COEX_ALGO_PANHS != algorithm)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is under inquiry/page scan !!\n");
- BTC_TRACE(trace_buf);
- halbtc8821a2ant_action_bt_inquiry(btcoexist);
- return;
- } else {
-
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
-
- if (scan || link || roam) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], WiFi is under Link Process !!\n");
- BTC_TRACE(trace_buf);
- halbtc8821a2ant_action_wifi_link_process(btcoexist);
- return;
- }
-
- /* for P2P */
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
- num_of_wifi_link = wifi_link_status >> 16;
-
- if ((num_of_wifi_link >= 2) ||
- (wifi_link_status & WIFI_P2P_GO_CONNECTED)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n",
- num_of_wifi_link, wifi_link_status);
- BTC_TRACE(trace_buf);
-
- if (bt_link_info->bt_link_exist)
- miracast_plus_bt = true;
- else
- miracast_plus_bt = false;
-
- btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
- &miracast_plus_bt);
- halbtc8821a2ant_action_wifi_multi_port(btcoexist);
-
- return;
- } else {
- miracast_plus_bt = false;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
- &miracast_plus_bt);
- }
-
- coex_dm->cur_algorithm = algorithm;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Algorithm = %d\n",
- coex_dm->cur_algorithm);
- BTC_TRACE(trace_buf);
-
- if (halbtc8821a2ant_is_common_action(btcoexist)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant common.\n");
- BTC_TRACE(trace_buf);
- coex_dm->auto_tdma_adjust = false;
- } else {
- if (coex_dm->cur_algorithm != coex_dm->pre_algorithm) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], pre_algorithm=%d, cur_algorithm=%d\n",
- coex_dm->pre_algorithm, coex_dm->cur_algorithm);
- BTC_TRACE(trace_buf);
- coex_dm->auto_tdma_adjust = false;
- }
- switch (coex_dm->cur_algorithm) {
- case BT_8821A_2ANT_COEX_ALGO_SCO:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = SCO.\n");
- BTC_TRACE(trace_buf);
- halbtc8821a2ant_action_sco(btcoexist);
- break;
- case BT_8821A_2ANT_COEX_ALGO_HID:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = HID.\n");
- BTC_TRACE(trace_buf);
- halbtc8821a2ant_action_hid(btcoexist);
- break;
- case BT_8821A_2ANT_COEX_ALGO_A2DP:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = A2DP.\n");
- BTC_TRACE(trace_buf);
- halbtc8821a2ant_action_a2dp(btcoexist);
- break;
- case BT_8821A_2ANT_COEX_ALGO_A2DP_PANHS:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n");
- BTC_TRACE(trace_buf);
- halbtc8821a2ant_action_a2dp_pan_hs(btcoexist);
- break;
- case BT_8821A_2ANT_COEX_ALGO_PANEDR:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n");
- BTC_TRACE(trace_buf);
- halbtc8821a2ant_action_pan_edr(btcoexist);
- break;
- case BT_8821A_2ANT_COEX_ALGO_PANHS:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = HS mode.\n");
- BTC_TRACE(trace_buf);
- halbtc8821a2ant_action_pan_hs(btcoexist);
- break;
- case BT_8821A_2ANT_COEX_ALGO_PANEDR_A2DP:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n");
- BTC_TRACE(trace_buf);
- halbtc8821a2ant_action_pan_edr_a2dp(btcoexist);
- break;
- case BT_8821A_2ANT_COEX_ALGO_PANEDR_HID:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n");
- BTC_TRACE(trace_buf);
- halbtc8821a2ant_action_pan_edr_hid(btcoexist);
- break;
- case BT_8821A_2ANT_COEX_ALGO_HID_A2DP_PANEDR:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n");
- BTC_TRACE(trace_buf);
- halbtc8821a2ant_action_hid_a2dp_pan_edr(
- btcoexist);
- break;
- case BT_8821A_2ANT_COEX_ALGO_HID_A2DP:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n");
- BTC_TRACE(trace_buf);
- halbtc8821a2ant_action_hid_a2dp(btcoexist);
- break;
- default:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n");
- BTC_TRACE(trace_buf);
- halbtc8821a2ant_coex_all_off(btcoexist);
- break;
- }
- coex_dm->pre_algorithm = coex_dm->cur_algorithm;
- }
-}
-
-void halbtc8821a2ant_wifi_off_hw_cfg(IN struct btc_coexist *btcoexist)
-{
- u8 h2c_parameter[2] = {0};
- u32 fw_ver = 0;
-
- /* set wlan_act to low */
- btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4);
-
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff,
- 0x780); /* WiFi goto standby while GNT_BT 0-->1 */
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
- if (fw_ver >= 0x180000) {
- /* Use H2C to set GNT_BT to HIGH */
- h2c_parameter[0] = 1;
- btcoexist->btc_fill_h2c(btcoexist, 0x6E, 1, h2c_parameter);
- } else
- btcoexist->btc_write_1byte(btcoexist, 0x765, 0x18);
-}
-
-void halbtc8821a2ant_init_hw_config(IN struct btc_coexist *btcoexist,
- IN boolean back_up)
-{
- u8 u8tmp = 0;
-
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], 2Ant Init HW Config!!\n");
- BTC_TRACE(trace_buf);
-
- /* backup rf 0x1e value */
- coex_dm->bt_rf_0x1e_backup =
- btcoexist->btc_get_rf_reg(btcoexist, BTC_RF_A, 0x1e, 0xfffff);
-
- /* 0x790[5:0]=0x5 */
- u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790);
- u8tmp &= 0xc0;
- u8tmp |= 0x5;
- btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp);
-
- /* Antenna config */
- halbtc8821a2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, true,
- false);
- coex_sta->dis_ver_info_cnt = 0;
-
- /* PTA parameter */
- halbtc8821a2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
-
- /* Enable counter statistics */
- btcoexist->btc_write_1byte(btcoexist, 0x76e,
- 0x4); /* 0x76e[3] =1, WLAN_Act control by PTA */
- btcoexist->btc_write_1byte(btcoexist, 0x778, 0x3);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1);
-}
-
-/* ************************************************************
- * work around function start with wa_halbtc8821a2ant_
- * ************************************************************
- * ************************************************************
- * extern function start with ex_halbtc8821a2ant_
- * ************************************************************ */
-void ex_halbtc8821a2ant_power_on_setting(IN struct btc_coexist *btcoexist)
-{
-
-}
-
-void ex_halbtc8821a2ant_pre_load_firmware(IN struct btc_coexist *btcoexist)
-{
- struct btc_board_info *board_info = &btcoexist->board_info;
- u8 u8tmp = 0x4; /* Set BIT2 by default since it's 2ant case */
-
- /* */
- /* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */
- /* Local setting bit define */
- /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */
- /* BIT1: "0" for internal switch; "1" for external switch */
- /* BIT2: "0" for one antenna; "1" for two antenna */
- /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */
- if (btcoexist->chip_interface == BTC_INTF_USB) {
- /* fixed at S0 for USB interface */
- u8tmp |= 0x1; /* antenna inverse */
- btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp);
- } else {
- /* for PCIE and SDIO interface, we check efuse 0xc3[6] */
- if (board_info->single_ant_path == 0) {
- } else if (board_info->single_ant_path == 1) {
- /* set to S0 */
- u8tmp |= 0x1; /* antenna inverse */
- }
-
- if (btcoexist->chip_interface == BTC_INTF_PCI)
- btcoexist->btc_write_local_reg_1byte(btcoexist, 0x384,
- u8tmp);
- else if (btcoexist->chip_interface == BTC_INTF_SDIO)
- btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60,
- u8tmp);
- }
-}
-
-void ex_halbtc8821a2ant_init_hw_config(IN struct btc_coexist *btcoexist,
- IN boolean wifi_only)
-{
- halbtc8821a2ant_init_hw_config(btcoexist, true);
-}
-
-void ex_halbtc8821a2ant_init_coex_dm(IN struct btc_coexist *btcoexist)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Coex Mechanism Init!!\n");
- BTC_TRACE(trace_buf);
-
- halbtc8821a2ant_init_coex_dm(btcoexist);
-}
-
-void ex_halbtc8821a2ant_display_coex_info(IN struct btc_coexist *btcoexist)
-{
- struct btc_board_info *board_info = &btcoexist->board_info;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- u8 *cli_buf = btcoexist->cli_buf;
- u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0;
- u32 u32tmp[4];
- u32 fa_of_dm, fa_cck;
- u32 fw_ver = 0, bt_patch_ver = 0;
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ============[BT Coexist info]============");
- CL_PRINTF(cli_buf);
-
- if (btcoexist->manual_control) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ============[Under Manual Control]============");
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ==========================================");
- CL_PRINTF(cli_buf);
- }
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ",
- "Ant PG number/ Ant mechanism:",
- board_info->pg_ant_num, board_info->btdm_ant_num);
- CL_PRINTF(cli_buf);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %d_%x/ 0x%x/ 0x%x(%d)",
- "CoexVer/ FwVer/ PatchVer",
- glcoex_ver_date_8821a_2ant, glcoex_ver_8821a_2ant, fw_ver,
- bt_patch_ver, bt_patch_ver);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ",
- "Wifi channel informed to BT",
- coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
- coex_dm->wifi_chnl_info[2]);
- CL_PRINTF(cli_buf);
-
- /* wifi status */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Wifi Status]============");
- CL_PRINTF(cli_buf);
- btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[BT Status]============");
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %ddBm/ %d] ",
- "BT [status/ rssi/ retryCnt]",
- ((coex_sta->bt_disabled) ? ("disabled") : ((
- coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan")
- : ((BT_8821A_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
- coex_dm->bt_status) ? "non-connected idle" :
- ((BT_8821A_2ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)
- ? "connected-idle" : "busy")))),
- coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d",
- "SCO/HID/PAN/A2DP",
- bt_link_info->sco_exist, bt_link_info->hid_exist,
- bt_link_info->pan_exist, bt_link_info->a2dp_exist);
- CL_PRINTF(cli_buf);
-
- {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
- "BT Role",
- (bt_link_info->slave_role) ? "Slave" : "Master");
- CL_PRINTF(cli_buf);
- }
-
- bt_info_ext = coex_sta->bt_info_ext;
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
- "BT Info A2DP rate",
- (bt_info_ext & BIT(0)) ? "Basic rate" : "EDR rate");
- CL_PRINTF(cli_buf);
-
- for (i = 0; i < BT_INFO_SRC_8821A_2ANT_MAX; i++) {
- if (coex_sta->bt_info_c2h_cnt[i]) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)",
- glbt_info_src_8821a_2ant[i],
- coex_sta->bt_info_c2h[i][0],
- coex_sta->bt_info_c2h[i][1],
- coex_sta->bt_info_c2h[i][2],
- coex_sta->bt_info_c2h[i][3],
- coex_sta->bt_info_c2h[i][4],
- coex_sta->bt_info_c2h[i][5],
- coex_sta->bt_info_c2h[i][6],
- coex_sta->bt_info_c2h_cnt[i]);
- CL_PRINTF(cli_buf);
- }
- }
-
- /* Sw mechanism */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Sw mechanism]============");
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ",
- "SM1[ShRf/ LpRA/ LimDig]",
- coex_dm->cur_rf_rx_lpf_shrink, coex_dm->cur_low_penalty_ra,
- coex_dm->limited_dig);
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ",
- "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]",
- coex_dm->cur_agc_table_en, coex_dm->cur_adc_back_off,
- coex_dm->cur_dac_swing_on, coex_dm->cur_dac_swing_lvl);
- CL_PRINTF(cli_buf);
-
- /* Fw mechanism */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Fw mechanism]============");
- CL_PRINTF(cli_buf);
-
- ps_tdma_case = coex_dm->cur_ps_tdma;
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (auto:%d)",
- "PS TDMA",
- coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],
- coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],
- coex_dm->ps_tdma_para[4], ps_tdma_case,
- coex_dm->auto_tdma_adjust);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
- "Coex Table Type",
- coex_sta->coex_table_type);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ",
- "DecBtPwr/ IgnWlanAct",
- coex_dm->cur_bt_dec_pwr_lvl, coex_dm->cur_ignore_wlan_act);
- CL_PRINTF(cli_buf);
-
- /* Hw setting */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Hw setting]============");
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x",
- "RF-A, 0x1e initVal",
- coex_dm->bt_rf_0x1e_backup);
- CL_PRINTF(cli_buf);
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xc5b);
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x880);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
- "0x778/0x880[29:25]/0xc58[29:25]",
- u8tmp[0], (u32tmp[0] & 0x3e000000) >> 25,
- ((u8tmp[1] & 0x3e) >> 1));
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x764);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x76e);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
- "0x764/ 0x765/ 0x76e",
- (u32tmp[0] & 0xff), (u32tmp[0] & 0xff00) >> 8, u8tmp[0]);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xcb4);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
- "0xcb4[7:0](ctrl)/ 0xcb4[29:28](val)",
- u32tmp[0] & 0xff, ((u32tmp[0] & 0x30000000) >> 28));
- CL_PRINTF(cli_buf);
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x40);
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x974);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
- "0x40/ 0x4c[24:23]/ 0x974",
- u8tmp[0], ((u32tmp[0] & 0x01800000) >> 23), u32tmp[1]);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
- "0x550(bcn ctrl)/0x522",
- u32tmp[0], u8tmp[0]);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x49c);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
- "0xc50(dig)/0x49c(null-drop)",
- u32tmp[0] & 0xff, u8tmp[0]);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xda0);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xda4);
- u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0xda8);
- u32tmp[3] = btcoexist->btc_read_4byte(btcoexist, 0xcf0);
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xa5b);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xa5c);
-
- fa_of_dm = ((u32tmp[0] & 0xffff0000) >> 16) + ((u32tmp[1] & 0xffff0000)
- >> 16) + (u32tmp[1] & 0xffff) + (u32tmp[2] & 0xffff) + \
- ((u32tmp[3] & 0xffff0000) >> 16) + (u32tmp[3] &
- 0xffff) ;
- fa_cck = (u8tmp[0] << 8) + u8tmp[1];
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
- "OFDM-CCA/OFDM-FA/CCK-FA",
- u32tmp[0] & 0xffff, fa_of_dm, fa_cck);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
- "CRC_OK CCK/11g/11n/11n-Agg",
- coex_sta->crc_ok_cck, coex_sta->crc_ok_11g,
- coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_agg);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
- "CRC_Err CCK/11g/11n/11n-Agg",
- coex_sta->crc_err_cck, coex_sta->crc_err_11g,
- coex_sta->crc_err_11n, coex_sta->crc_err_11n_agg);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
- u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x6cc);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
- "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)",
- u32tmp[0], u32tmp[1], u32tmp[2], u8tmp[0]);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
- "0x770(high-pri rx/tx)",
- coex_sta->high_priority_rx, coex_sta->high_priority_tx);
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
- "0x774(low-pri rx/tx)",
- coex_sta->low_priority_rx, coex_sta->low_priority_tx);
- CL_PRINTF(cli_buf);
-#if (BT_AUTO_REPORT_ONLY_8821A_2ANT == 1)
- /* halbtc8821a2ant_monitor_bt_ctr(btcoexist); */
-#endif
- btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
-}
-
-
-void ex_halbtc8821a2ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type)
-{
- if (BTC_IPS_ENTER == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], IPS ENTER notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_ips = true;
- halbtc8821a2ant_wifi_off_hw_cfg(btcoexist);
- halbtc8821a2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
- halbtc8821a2ant_coex_all_off(btcoexist);
- } else if (BTC_IPS_LEAVE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], IPS LEAVE notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_ips = false;
- halbtc8821a2ant_init_hw_config(btcoexist, false);
- halbtc8821a2ant_init_coex_dm(btcoexist);
- halbtc8821a2ant_query_bt_info(btcoexist);
- }
-}
-
-void ex_halbtc8821a2ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type)
-{
- if (BTC_LPS_ENABLE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], LPS ENABLE notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_lps = true;
- } else if (BTC_LPS_DISABLE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], LPS DISABLE notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_lps = false;
- }
-}
-
-void ex_halbtc8821a2ant_scan_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- u8 u8tmpa, u8tmpb;
-
- u8tmpa = btcoexist->btc_read_1byte(btcoexist, 0x765);
- u8tmpb = btcoexist->btc_read_1byte(btcoexist, 0x76e);
-
- if (BTC_SCAN_START == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCAN START notify\n");
- BTC_TRACE(trace_buf);
- } else if (BTC_SCAN_FINISH == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCAN FINISH notify\n");
- BTC_TRACE(trace_buf);
- }
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], 0x765=0x%x, 0x76e=0x%x\n", u8tmpa,
- u8tmpb);
- BTC_TRACE(trace_buf);
-}
-
-void ex_halbtc8821a2ant_connect_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- if (BTC_ASSOCIATE_START == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CONNECT START notify\n");
- BTC_TRACE(trace_buf);
- } else if (BTC_ASSOCIATE_FINISH == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CONNECT FINISH notify\n");
- BTC_TRACE(trace_buf);
- }
-}
-
-void ex_halbtc8821a2ant_media_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- u8 h2c_parameter[3] = {0};
- u32 wifi_bw;
- u8 wifi_central_chnl;
- u8 ap_num = 0;
-
- if (BTC_MEDIA_CONNECT == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], MEDIA connect notify\n");
- BTC_TRACE(trace_buf);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], MEDIA disconnect notify\n");
- BTC_TRACE(trace_buf);
- }
-
- /* only 2.4G we need to inform bt the chnl mask */
- btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
- &wifi_central_chnl);
- if ((BTC_MEDIA_CONNECT == type) &&
- (wifi_central_chnl <= 14)) {
- h2c_parameter[0] = 0x1;
- h2c_parameter[1] = wifi_central_chnl;
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- if (BTC_WIFI_BW_HT40 == wifi_bw)
- h2c_parameter[2] = 0x30;
- else {
- btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
- &ap_num);
- if (ap_num < 10)
- h2c_parameter[2] = 0x30;
- else
- h2c_parameter[2] = 0x20;
- }
- }
-
- coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
- coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
- coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
-
- btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter);
-}
-
-void ex_halbtc8821a2ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- if (type == BTC_PACKET_DHCP) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], DHCP Packet notify\n");
- BTC_TRACE(trace_buf);
- }
-}
-
-void ex_halbtc8821a2ant_bt_info_notify(IN struct btc_coexist *btcoexist,
- IN u8 *tmp_buf, IN u8 length)
-{
- u8 bt_info = 0;
- u8 i, rsp_source = 0;
- boolean bt_busy = false, limited_dig = false;
- boolean wifi_connected = false, wifi_under_5g = false;
-
- coex_sta->c2h_bt_info_req_sent = false;
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
-
- rsp_source = tmp_buf[0] & 0xf;
- if (rsp_source >= BT_INFO_SRC_8821A_2ANT_MAX)
- rsp_source = BT_INFO_SRC_8821A_2ANT_WIFI_FW;
- coex_sta->bt_info_c2h_cnt[rsp_source]++;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source,
- length);
- BTC_TRACE(trace_buf);
- for (i = 0; i < length; i++) {
- coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
- if (i == 1)
- bt_info = tmp_buf[i];
- if (i == length - 1) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n",
- tmp_buf[i]);
- BTC_TRACE(trace_buf);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ",
- tmp_buf[i]);
- BTC_TRACE(trace_buf);
- }
- }
-
- if (btcoexist->manual_control) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), return for Manual CTRL<===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- /* if 0xff, it means BT is under WHCK test */
- if (bt_info == 0xff)
- coex_sta->bt_whck_test = true;
- else
- coex_sta->bt_whck_test = false;
-
- if (BT_INFO_SRC_8821A_2ANT_WIFI_FW != rsp_source) {
- coex_sta->bt_retry_cnt = /* [3:0] */
- coex_sta->bt_info_c2h[rsp_source][2] & 0xf;
-
- coex_sta->bt_rssi =
- coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10;
-
- coex_sta->bt_info_ext =
- coex_sta->bt_info_c2h[rsp_source][4];
-
- coex_sta->bt_tx_rx_mask = (coex_sta->bt_info_c2h[rsp_source][2]
- & 0x40);
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TX_RX_MASK,
- &coex_sta->bt_tx_rx_mask);
- if (coex_sta->bt_tx_rx_mask) {
- /* BT into is responded by BT FW and BT RF REG 0x3C != 0x01 => Need to switch BT TRx Mask */
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x01\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF,
- 0x3c, 0x01);
- }
-
- /* Here we need to resend some wifi info to BT */
- /* because bt is reset and loss of the info. */
- if ((coex_sta->bt_info_ext & BIT(1))) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n");
- BTC_TRACE(trace_buf);
- if (wifi_connected)
- ex_halbtc8821a2ant_media_status_notify(
- btcoexist, BTC_MEDIA_CONNECT);
- else
- ex_halbtc8821a2ant_media_status_notify(
- btcoexist, BTC_MEDIA_DISCONNECT);
- }
-
-
- if (!btcoexist->manual_control && !wifi_under_5g) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT ext info = 0x%x!!\n",
- coex_sta->bt_info_ext);
- BTC_TRACE(trace_buf);
- if ((coex_sta->bt_info_ext & BIT(3))) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT ext info bit3=1, wifi_connected=%d\n",
- wifi_connected);
- BTC_TRACE(trace_buf);
- if (wifi_connected) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n");
- BTC_TRACE(trace_buf);
- halbtc8821a2ant_ignore_wlan_act(
- btcoexist, FORCE_EXEC, false);
- }
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT ext info bit3=0, wifi_connected=%d\n",
- wifi_connected);
- BTC_TRACE(trace_buf);
- /* BT already NOT ignore Wlan active, do nothing here. */
- if (!wifi_connected) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT ext info bit3 check, set BT to ignore Wlan active!!\n");
- BTC_TRACE(trace_buf);
- halbtc8821a2ant_ignore_wlan_act(
- btcoexist, FORCE_EXEC, true);
- }
- }
- }
-
-#if (BT_AUTO_REPORT_ONLY_8821A_2ANT == 0)
- if ((coex_sta->bt_info_ext & BIT(4))) {
- /* BT auto report already enabled, do nothing */
- } else
- halbtc8821a2ant_bt_auto_report(btcoexist, FORCE_EXEC,
- true);
-#endif
- }
-
- /* check BIT2 first ==> check if bt is under inquiry or page scan */
- if (bt_info & BT_INFO_8821A_2ANT_B_INQ_PAGE)
- coex_sta->c2h_bt_inquiry_page = true;
- else
- coex_sta->c2h_bt_inquiry_page = false;
-
- /* set link exist status */
- if (!(bt_info & BT_INFO_8821A_2ANT_B_CONNECTION)) {
- coex_sta->bt_link_exist = false;
- coex_sta->pan_exist = false;
- coex_sta->a2dp_exist = false;
- coex_sta->hid_exist = false;
- coex_sta->sco_exist = false;
- } else { /* connection exists */
- coex_sta->bt_link_exist = true;
- if (bt_info & BT_INFO_8821A_2ANT_B_FTP)
- coex_sta->pan_exist = true;
- else
- coex_sta->pan_exist = false;
- if (bt_info & BT_INFO_8821A_2ANT_B_A2DP)
- coex_sta->a2dp_exist = true;
- else
- coex_sta->a2dp_exist = false;
- if (bt_info & BT_INFO_8821A_2ANT_B_HID)
- coex_sta->hid_exist = true;
- else
- coex_sta->hid_exist = false;
- if (bt_info & BT_INFO_8821A_2ANT_B_SCO_ESCO)
- coex_sta->sco_exist = true;
- else
- coex_sta->sco_exist = false;
-
- if ((coex_sta->hid_exist == false) &&
- (coex_sta->c2h_bt_inquiry_page == false) &&
- (coex_sta->sco_exist == false)) {
- if (coex_sta->high_priority_tx +
- coex_sta->high_priority_rx >= 160)
- coex_sta->hid_exist = true;
- }
- }
-
- halbtc8821a2ant_update_bt_link_info(btcoexist);
-
- if (!(bt_info & BT_INFO_8821A_2ANT_B_CONNECTION)) {
- coex_dm->bt_status = BT_8821A_2ANT_BT_STATUS_NON_CONNECTED_IDLE;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n");
- BTC_TRACE(trace_buf);
- } else if (bt_info ==
- BT_INFO_8821A_2ANT_B_CONNECTION) { /* connection exists but no busy */
- coex_dm->bt_status = BT_8821A_2ANT_BT_STATUS_CONNECTED_IDLE;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n");
- BTC_TRACE(trace_buf);
- } else if ((bt_info & BT_INFO_8821A_2ANT_B_SCO_ESCO) ||
- (bt_info & BT_INFO_8821A_2ANT_B_SCO_BUSY)) {
- coex_dm->bt_status = BT_8821A_2ANT_BT_STATUS_SCO_BUSY;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n");
- BTC_TRACE(trace_buf);
- } else if (bt_info & BT_INFO_8821A_2ANT_B_ACL_BUSY) {
- coex_dm->bt_status = BT_8821A_2ANT_BT_STATUS_ACL_BUSY;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n");
- BTC_TRACE(trace_buf);
- } else {
- coex_dm->bt_status = BT_8821A_2ANT_BT_STATUS_MAX;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n");
- BTC_TRACE(trace_buf);
- }
-
- if ((BT_8821A_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
- (BT_8821A_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
- (BT_8821A_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) {
- bt_busy = true;
- limited_dig = true;
- } else {
- bt_busy = false;
- limited_dig = false;
- }
-
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
-
- coex_dm->limited_dig = limited_dig;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_LIMITED_DIG, &limited_dig);
-
- halbtc8821a2ant_run_coexist_mechanism(btcoexist);
-}
-
-void ex_halbtc8821a2ant_halt_notify(IN struct btc_coexist *btcoexist)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n");
- BTC_TRACE(trace_buf);
-
- halbtc8821a2ant_wifi_off_hw_cfg(btcoexist);
- /* remove due to interrupt is disabled that polling c2h will fail and delay 100ms. */
- /* btcoexist->btc_set_bt_reg(btcoexist, BTC_BT_REG_RF, 0x3c, 0x15); //BT goto standby while GNT_BT 1-->0 */
- halbtc8821a2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
-
- ex_halbtc8821a2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
-}
-
-void ex_halbtc8821a2ant_pnp_notify(IN struct btc_coexist *btcoexist,
- IN u8 pnp_state)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n");
- BTC_TRACE(trace_buf);
-
- if (BTC_WIFI_PNP_SLEEP == pnp_state) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Pnp notify to SLEEP\n");
- BTC_TRACE(trace_buf);
- } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Pnp notify to WAKE UP\n");
- BTC_TRACE(trace_buf);
- halbtc8821a2ant_init_hw_config(btcoexist, false);
- halbtc8821a2ant_init_coex_dm(btcoexist);
- halbtc8821a2ant_query_bt_info(btcoexist);
- }
-}
-
-void ex_halbtc8821a2ant_periodical(IN struct btc_coexist *btcoexist)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ==========================Periodical===========================\n");
- BTC_TRACE(trace_buf);
-
- if (coex_sta->dis_ver_info_cnt <= 5) {
- coex_sta->dis_ver_info_cnt += 1;
- if (coex_sta->dis_ver_info_cnt == 3) {
- /* Antenna config to set 0x765 = 0x0 (GNT_BT control by PTA) after initial */
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Set GNT_BT control by PTA\n");
- BTC_TRACE(trace_buf);
- halbtc8821a2ant_set_ant_path(btcoexist,
- BTC_ANT_WIFI_AT_MAIN, false, false);
- }
- }
-
-#if (BT_AUTO_REPORT_ONLY_8821A_2ANT == 0)
- halbtc8821a2ant_query_bt_info(btcoexist);
- halbtc8821a2ant_monitor_bt_enable_disable(btcoexist);
-#else
- halbtc8821a2ant_monitor_bt_ctr(btcoexist);
- halbtc8821a2ant_monitor_wifi_ctr(btcoexist);
-
- if (halbtc8821a2ant_is_wifi_status_changed(btcoexist) ||
- coex_dm->auto_tdma_adjust)
- halbtc8821a2ant_run_coexist_mechanism(btcoexist);
-#endif
-}
-
-#endif
-
-#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */
\ No newline at end of file
diff --git a/hal/btc/HalBtc8821a2Ant.h b/hal/btc/HalBtc8821a2Ant.h
deleted file mode 100644
index 73252dd..0000000
--- a/hal/btc/HalBtc8821a2Ant.h
+++ /dev/null
@@ -1,205 +0,0 @@
-
-#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
-
-#if (RTL8821A_SUPPORT == 1)
-
-/* *******************************************
- * The following is for 8821A 2Ant BT Co-exist definition
- * ******************************************* */
-#define BT_AUTO_REPORT_ONLY_8821A_2ANT 1
-
-
-#define BT_INFO_8821A_2ANT_B_FTP BIT(7)
-#define BT_INFO_8821A_2ANT_B_A2DP BIT(6)
-#define BT_INFO_8821A_2ANT_B_HID BIT(5)
-#define BT_INFO_8821A_2ANT_B_SCO_BUSY BIT(4)
-#define BT_INFO_8821A_2ANT_B_ACL_BUSY BIT(3)
-#define BT_INFO_8821A_2ANT_B_INQ_PAGE BIT(2)
-#define BT_INFO_8821A_2ANT_B_SCO_ESCO BIT(1)
-#define BT_INFO_8821A_2ANT_B_CONNECTION BIT(0)
-
-#define BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT 2
-
-
-#define BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES 42 /* WiFi RSSI Threshold for 2-Ant TDMA/1-Ant PS-TDMA translation */
-#define BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES 46 /* BT RSSI Threshold for 2-Ant TDMA/1-Ant PS-TDMA translation */
-
-enum bt_info_src_8821a_2ant {
- BT_INFO_SRC_8821A_2ANT_WIFI_FW = 0x0,
- BT_INFO_SRC_8821A_2ANT_BT_RSP = 0x1,
- BT_INFO_SRC_8821A_2ANT_BT_ACTIVE_SEND = 0x2,
- BT_INFO_SRC_8821A_2ANT_MAX
-};
-
-enum bt_8821a_2ant_bt_status {
- BT_8821A_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
- BT_8821A_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
- BT_8821A_2ANT_BT_STATUS_INQ_PAGE = 0x2,
- BT_8821A_2ANT_BT_STATUS_ACL_BUSY = 0x3,
- BT_8821A_2ANT_BT_STATUS_SCO_BUSY = 0x4,
- BT_8821A_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
- BT_8821A_2ANT_BT_STATUS_MAX
-};
-
-enum bt_8821a_2ant_coex_algo {
- BT_8821A_2ANT_COEX_ALGO_UNDEFINED = 0x0,
- BT_8821A_2ANT_COEX_ALGO_SCO = 0x1,
- BT_8821A_2ANT_COEX_ALGO_HID = 0x2,
- BT_8821A_2ANT_COEX_ALGO_A2DP = 0x3,
- BT_8821A_2ANT_COEX_ALGO_A2DP_PANHS = 0x4,
- BT_8821A_2ANT_COEX_ALGO_PANEDR = 0x5,
- BT_8821A_2ANT_COEX_ALGO_PANHS = 0x6,
- BT_8821A_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
- BT_8821A_2ANT_COEX_ALGO_PANEDR_HID = 0x8,
- BT_8821A_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
- BT_8821A_2ANT_COEX_ALGO_HID_A2DP = 0xa,
- BT_8821A_2ANT_COEX_ALGO_MAX = 0xb,
-};
-
-struct coex_dm_8821a_2ant {
- /* fw mechanism */
- u8 pre_bt_dec_pwr_lvl;
- u8 cur_bt_dec_pwr_lvl;
- u8 pre_fw_dac_swing_lvl;
- u8 cur_fw_dac_swing_lvl;
- boolean cur_ignore_wlan_act;
- boolean pre_ignore_wlan_act;
- u8 pre_ps_tdma;
- u8 cur_ps_tdma;
- u8 ps_tdma_para[5];
- u8 ps_tdma_du_adj_type;
- boolean reset_tdma_adjust;
- boolean auto_tdma_adjust;
- boolean pre_ps_tdma_on;
- boolean cur_ps_tdma_on;
- boolean pre_bt_auto_report;
- boolean cur_bt_auto_report;
-
- /* sw mechanism */
- boolean pre_rf_rx_lpf_shrink;
- boolean cur_rf_rx_lpf_shrink;
- u32 bt_rf_0x1e_backup;
- boolean pre_low_penalty_ra;
- boolean cur_low_penalty_ra;
- boolean pre_dac_swing_on;
- u32 pre_dac_swing_lvl;
- boolean cur_dac_swing_on;
- u32 cur_dac_swing_lvl;
- boolean pre_adc_back_off;
- boolean cur_adc_back_off;
- boolean pre_agc_table_en;
- boolean cur_agc_table_en;
- u32 pre_val0x6c0;
- u32 cur_val0x6c0;
- u32 pre_val0x6c4;
- u32 cur_val0x6c4;
- u32 pre_val0x6c8;
- u32 cur_val0x6c8;
- u8 pre_val0x6cc;
- u8 cur_val0x6cc;
- boolean limited_dig;
-
- /* algorithm related */
- u8 pre_algorithm;
- u8 cur_algorithm;
- u8 bt_status;
- u8 wifi_chnl_info[3];
-
- boolean need_recover0x948;
- u32 backup0x948;
-
- u8 pre_lps;
- u8 cur_lps;
- u8 pre_rpwm;
- u8 cur_rpwm;
-};
-
-struct coex_sta_8821a_2ant {
- boolean bt_disabled;
- boolean bt_link_exist;
- boolean sco_exist;
- boolean a2dp_exist;
- boolean hid_exist;
- boolean pan_exist;
-
- boolean under_lps;
- boolean under_ips;
- u32 high_priority_tx;
- u32 high_priority_rx;
- u32 low_priority_tx;
- u32 low_priority_rx;
- u8 bt_rssi;
- boolean bt_tx_rx_mask;
- u8 pre_bt_rssi_state;
- u8 pre_wifi_rssi_state[4];
- boolean c2h_bt_info_req_sent;
- u8 bt_info_c2h[BT_INFO_SRC_8821A_2ANT_MAX][10];
- u32 bt_info_c2h_cnt[BT_INFO_SRC_8821A_2ANT_MAX];
- boolean bt_whck_test;
- boolean c2h_bt_inquiry_page;
- u8 bt_retry_cnt;
- u8 bt_info_ext;
-
- u32 crc_ok_cck;
- u32 crc_ok_11g;
- u32 crc_ok_11n;
- u32 crc_ok_11n_agg;
-
- u32 crc_err_cck;
- u32 crc_err_11g;
- u32 crc_err_11n;
- u32 crc_err_11n_agg;
-
- u8 coex_table_type;
- boolean force_lps_on;
-
- u8 dis_ver_info_cnt;
-};
-
-/* *******************************************
- * The following is interface which will notify coex module.
- * ******************************************* */
-void ex_halbtc8821a2ant_power_on_setting(IN struct btc_coexist *btcoexist);
-void ex_halbtc8821a2ant_pre_load_firmware(IN struct btc_coexist *btcoexist);
-void ex_halbtc8821a2ant_init_hw_config(IN struct btc_coexist *btcoexist,
- IN boolean wifi_only);
-void ex_halbtc8821a2ant_init_coex_dm(IN struct btc_coexist *btcoexist);
-void ex_halbtc8821a2ant_ips_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8821a2ant_lps_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8821a2ant_scan_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8821a2ant_connect_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8821a2ant_media_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8821a2ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8821a2ant_bt_info_notify(IN struct btc_coexist *btcoexist,
- IN u8 *tmp_buf, IN u8 length);
-void ex_halbtc8821a2ant_halt_notify(IN struct btc_coexist *btcoexist);
-void ex_halbtc8821a2ant_pnp_notify(IN struct btc_coexist *btcoexist,
- IN u8 pnp_state);
-void ex_halbtc8821a2ant_periodical(IN struct btc_coexist *btcoexist);
-void ex_halbtc8821a2ant_display_coex_info(IN struct btc_coexist *btcoexist);
-
-#else
-#define ex_halbtc8821a2ant_power_on_setting(btcoexist)
-#define ex_halbtc8821a2ant_pre_load_firmware(btcoexist)
-#define ex_halbtc8821a2ant_init_hw_config(btcoexist, wifi_only)
-#define ex_halbtc8821a2ant_init_coex_dm(btcoexist)
-#define ex_halbtc8821a2ant_ips_notify(btcoexist, type)
-#define ex_halbtc8821a2ant_lps_notify(btcoexist, type)
-#define ex_halbtc8821a2ant_scan_notify(btcoexist, type)
-#define ex_halbtc8821a2ant_connect_notify(btcoexist, type)
-#define ex_halbtc8821a2ant_media_status_notify(btcoexist, type)
-#define ex_halbtc8821a2ant_specific_packet_notify(btcoexist, type)
-#define ex_halbtc8821a2ant_bt_info_notify(btcoexist, tmp_buf, length)
-#define ex_halbtc8821a2ant_halt_notify(btcoexist)
-#define ex_halbtc8821a2ant_pnp_notify(btcoexist, pnp_state)
-#define ex_halbtc8821a2ant_periodical(btcoexist)
-#define ex_halbtc8821a2ant_display_coex_info(btcoexist)
-#endif
-
-#endif
diff --git a/hal/btc/HalBtc8821aCsr2Ant.c b/hal/btc/HalBtc8821aCsr2Ant.c
deleted file mode 100644
index b69d156..0000000
--- a/hal/btc/HalBtc8821aCsr2Ant.c
+++ /dev/null
@@ -1,3997 +0,0 @@
-/* ************************************************************
- * Description:
- *
- * This file is for RTL8821A_CSR_CSR Co-exist mechanism
- *
- * History
- * 2012/08/22 Cosa first check in.
- * 2012/11/14 Cosa Revise for 8821A_CSR 2Ant out sourcing.
- *
- * ************************************************************ */
-
-/* ************************************************************
- * include files
- * ************************************************************ */
-#include "Mp_Precomp.h"
-
-#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
-
-#if (RTL8821A_SUPPORT == 1)
-
-#define _BTCOEX_CSR 1
-
-#ifndef rtw_warn_on_8821acsr2ant
-#define rtw_warn_on_8821acsr2ant(condition) do {} while (0)
-#endif
-/* ************************************************************
- * Global variables, these are static variables
- * ************************************************************ */
-static u8 *trace_buf = &gl_btc_trace_buf[0];
-static struct coex_dm_8821a_csr_2ant glcoex_dm_8821a_csr_2ant;
-static struct coex_dm_8821a_csr_2ant *coex_dm = &glcoex_dm_8821a_csr_2ant;
-static struct coex_sta_8821a_csr_2ant glcoex_sta_8821a_csr_2ant;
-static struct coex_sta_8821a_csr_2ant *coex_sta = &glcoex_sta_8821a_csr_2ant;
-
-const char *const glbt_info_src_8821a_csr_2ant[] = {
- "BT Info[wifi fw]",
- "BT Info[bt rsp]",
- "BT Info[bt auto report]",
-};
-
-u32 glcoex_ver_date_8821a_csr_2ant = 20140901;
-u32 glcoex_ver_8821a_csr_2ant = 0x51;
-
-/* ************************************************************
- * local function proto type if needed
- * ************************************************************
- * ************************************************************
- * local function start with halbtc8821aCsr2ant_
- * ************************************************************ */
-u8 halbtc8821aCsr2ant_bt_rssi_state(u8 level_num, u8 rssi_thresh,
- u8 rssi_thresh1)
-{
- s32 bt_rssi = 0;
- u8 bt_rssi_state = coex_sta->pre_bt_rssi_state;
-
- bt_rssi = coex_sta->bt_rssi;
-
- if (level_num == 2) {
- if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
- (coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (bt_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8821A_CSR_2ANT))
- bt_rssi_state = BTC_RSSI_STATE_HIGH;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else {
- if (bt_rssi < rssi_thresh)
- bt_rssi_state = BTC_RSSI_STATE_LOW;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- } else if (level_num == 3) {
- if (rssi_thresh > rssi_thresh1) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Rssi thresh error!!\n");
- BTC_TRACE(trace_buf);
- return coex_sta->pre_bt_rssi_state;
- }
-
- if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
- (coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (bt_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8821A_CSR_2ANT))
- bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else if ((coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_MEDIUM) ||
- (coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_STAY_MEDIUM)) {
- if (bt_rssi >= (rssi_thresh1 +
- BTC_RSSI_COEX_THRESH_TOL_8821A_CSR_2ANT))
- bt_rssi_state = BTC_RSSI_STATE_HIGH;
- else if (bt_rssi < rssi_thresh)
- bt_rssi_state = BTC_RSSI_STATE_LOW;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
- } else {
- if (bt_rssi < rssi_thresh1)
- bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- }
-
- coex_sta->pre_bt_rssi_state = bt_rssi_state;
-
- return bt_rssi_state;
-}
-
-u8 halbtc8821aCsr2ant_wifi_rssi_state(IN struct btc_coexist *btcoexist,
- IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1)
-{
- s32 wifi_rssi = 0;
- u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index];
-
- btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
-
- if (level_num == 2) {
- if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
- ||
- (coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (wifi_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8821A_CSR_2ANT))
- wifi_rssi_state = BTC_RSSI_STATE_HIGH;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else {
- if (wifi_rssi < rssi_thresh)
- wifi_rssi_state = BTC_RSSI_STATE_LOW;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- } else if (level_num == 3) {
- if (rssi_thresh > rssi_thresh1) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], wifi RSSI thresh error!!\n");
- BTC_TRACE(trace_buf);
- return coex_sta->pre_wifi_rssi_state[index];
- }
-
- if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
- ||
- (coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (wifi_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8821A_CSR_2ANT))
- wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else if ((coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_MEDIUM) ||
- (coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_STAY_MEDIUM)) {
- if (wifi_rssi >= (rssi_thresh1 +
- BTC_RSSI_COEX_THRESH_TOL_8821A_CSR_2ANT))
- wifi_rssi_state = BTC_RSSI_STATE_HIGH;
- else if (wifi_rssi < rssi_thresh)
- wifi_rssi_state = BTC_RSSI_STATE_LOW;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
- } else {
- if (wifi_rssi < rssi_thresh1)
- wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- }
-
- coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state;
-
- return wifi_rssi_state;
-}
-
-void halbtc8821aCsr2ant_monitor_bt_enable_disable(IN struct btc_coexist
- *btcoexist)
-{
- static u32 bt_disable_cnt = 0;
- boolean bt_active = true, bt_disabled = false;
-
- /* This function check if bt is disabled */
-
- if (coex_sta->high_priority_tx == 0 &&
- coex_sta->high_priority_rx == 0 &&
- coex_sta->low_priority_tx == 0 &&
- coex_sta->low_priority_rx == 0)
- bt_active = false;
- if (coex_sta->high_priority_tx == 0xffff &&
- coex_sta->high_priority_rx == 0xffff &&
- coex_sta->low_priority_tx == 0xffff &&
- coex_sta->low_priority_rx == 0xffff)
- bt_active = false;
- if (bt_active) {
- bt_disable_cnt = 0;
- bt_disabled = false;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
- &bt_disabled);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is enabled !!\n");
- BTC_TRACE(trace_buf);
- } else {
- bt_disable_cnt++;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], bt all counters=0, %d times!!\n",
- bt_disable_cnt);
- BTC_TRACE(trace_buf);
- if (bt_disable_cnt >= 2) {
- bt_disabled = true;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
- &bt_disabled);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is disabled !!\n");
- BTC_TRACE(trace_buf);
- }
- }
- if (coex_sta->bt_disabled != bt_disabled) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is from %s to %s!!\n",
- (coex_sta->bt_disabled ? "disabled" : "enabled"),
- (bt_disabled ? "disabled" : "enabled"));
- BTC_TRACE(trace_buf);
- coex_sta->bt_disabled = bt_disabled;
- if (!bt_disabled) {
- } else {
- }
- }
-}
-
-void halbtc8821aCsr2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist)
-{
- u32 reg_hp_txrx, reg_lp_txrx, u32tmp;
- u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
-
- reg_hp_txrx = 0x770;
- reg_lp_txrx = 0x774;
-
- u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
- reg_hp_tx = u32tmp & MASKLWORD;
- reg_hp_rx = (u32tmp & MASKHWORD) >> 16;
-
- u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
- reg_lp_tx = u32tmp & MASKLWORD;
- reg_lp_rx = (u32tmp & MASKHWORD) >> 16;
-
- coex_sta->high_priority_tx = reg_hp_tx;
- coex_sta->high_priority_rx = reg_hp_rx;
- coex_sta->low_priority_tx = reg_lp_tx;
- coex_sta->low_priority_rx = reg_lp_rx;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], High Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n",
- reg_hp_txrx, reg_hp_tx, reg_hp_tx, reg_hp_rx, reg_hp_rx);
- BTC_TRACE(trace_buf);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Low Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n",
- reg_lp_txrx, reg_lp_tx, reg_lp_tx, reg_lp_rx, reg_lp_rx);
- BTC_TRACE(trace_buf);
-
- /* reset counter */
- btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x5d);
-}
-
-void halbtc8821aCsr2ant_update_ra_mask(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u32 dis_rate_mask)
-{
- coex_dm->cur_ra_mask = dis_rate_mask;
-
- if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask))
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK,
- &coex_dm->cur_ra_mask);
- coex_dm->pre_ra_mask = coex_dm->cur_ra_mask;
-}
-
-void halbtc8821aCsr2ant_auto_rate_fallback_retry(IN struct btc_coexist
- *btcoexist, IN boolean force_exec, IN u8 type)
-{
- boolean wifi_under_b_mode = false;
-
- coex_dm->cur_arfr_type = type;
-
- if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) {
- switch (coex_dm->cur_arfr_type) {
- case 0: /* normal mode */
- btcoexist->btc_write_4byte(btcoexist, 0x430,
- coex_dm->backup_arfr_cnt1);
- btcoexist->btc_write_4byte(btcoexist, 0x434,
- coex_dm->backup_arfr_cnt2);
- break;
- case 1:
- btcoexist->btc_get(btcoexist,
- BTC_GET_BL_WIFI_UNDER_B_MODE,
- &wifi_under_b_mode);
- if (wifi_under_b_mode) {
- btcoexist->btc_write_4byte(btcoexist,
- 0x430, 0x0);
- btcoexist->btc_write_4byte(btcoexist,
- 0x434, 0x01010101);
- } else {
- btcoexist->btc_write_4byte(btcoexist,
- 0x430, 0x0);
- btcoexist->btc_write_4byte(btcoexist,
- 0x434, 0x04030201);
- }
- break;
- default:
- break;
- }
- }
-
- coex_dm->pre_arfr_type = coex_dm->cur_arfr_type;
-}
-
-void halbtc8821aCsr2ant_retry_limit(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- coex_dm->cur_retry_limit_type = type;
-
- if (force_exec ||
- (coex_dm->pre_retry_limit_type !=
- coex_dm->cur_retry_limit_type)) {
- switch (coex_dm->cur_retry_limit_type) {
- case 0: /* normal mode */
- btcoexist->btc_write_2byte(btcoexist, 0x42a,
- coex_dm->backup_retry_limit);
- break;
- case 1: /* retry limit=8 */
- btcoexist->btc_write_2byte(btcoexist, 0x42a,
- 0x0808);
- break;
- default:
- break;
- }
- }
-
- coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type;
-}
-
-void halbtc8821aCsr2ant_ampdu_max_time(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- coex_dm->cur_ampdu_time_type = type;
-
- if (force_exec ||
- (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) {
- switch (coex_dm->cur_ampdu_time_type) {
- case 0: /* normal mode */
- btcoexist->btc_write_1byte(btcoexist, 0x456,
- coex_dm->backup_ampdu_max_time);
- break;
- case 1: /* AMPDU timw = 0x38 * 32us */
- btcoexist->btc_write_1byte(btcoexist, 0x456,
- 0x38);
- break;
- case 2:
- btcoexist->btc_write_1byte(btcoexist, 0x456,
- 0x17);
- break;
- default:
- break;
- }
- }
-
- coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type;
-}
-
-void halbtc8821aCsr2Ant_AmpduMaxNum(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- coex_dm->cur_ampdu_num_type = type;
-
- if (force_exec ||
- (coex_dm->pre_ampdu_num_type != coex_dm->cur_ampdu_num_type)) {
- switch (coex_dm->cur_ampdu_num_type) {
- case 0: /* normal mode */
- btcoexist->btc_write_2byte(btcoexist, 0x4ca,
- coex_dm->backup_ampdu_max_num);
- break;
- case 1:
- btcoexist->btc_write_2byte(btcoexist, 0x4ca,
- 0x0808);
- break;
- case 2:
- btcoexist->btc_write_2byte(btcoexist, 0x4ca,
- 0x1f1f);
- break;
- default:
- break;
- }
- }
-
- coex_dm->pre_ampdu_num_type = coex_dm->cur_ampdu_num_type;
-
-}
-
-void halbtc8821aCsr2ant_limited_tx(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type,
- IN u8 retry_limit_type, IN u8 ampdu_time_type, IN u8 ampdu_num_type)
-{
- switch (ra_mask_type) {
- case 0: /* normal mode */
- halbtc8821aCsr2ant_update_ra_mask(btcoexist, force_exec,
- 0x0);
- break;
- case 1: /* disable cck 1/2 */
- halbtc8821aCsr2ant_update_ra_mask(btcoexist, force_exec,
- 0x00000003);
- break;
- case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */
- halbtc8821aCsr2ant_update_ra_mask(btcoexist, force_exec,
- 0x0001f1f7);
- break;
- default:
- break;
- }
-
- halbtc8821aCsr2ant_auto_rate_fallback_retry(btcoexist, force_exec,
- arfr_type);
- halbtc8821aCsr2ant_retry_limit(btcoexist, force_exec, retry_limit_type);
- halbtc8821aCsr2ant_ampdu_max_time(btcoexist, force_exec,
- ampdu_time_type);
- halbtc8821aCsr2Ant_AmpduMaxNum(btcoexist, force_exec, ampdu_num_type);
-}
-
-
-
-void halbtc8821aCsr2ant_limited_rx(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean rej_ap_agg_pkt,
- IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size)
-{
- boolean reject_rx_agg = rej_ap_agg_pkt;
- boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size;
- u8 rx_agg_size = agg_buf_size;
-
- /* ============================================ */
- /* Rx Aggregation related setting */
- /* ============================================ */
- btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT,
- &reject_rx_agg);
- /* decide BT control aggregation buf size or not */
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE,
- &bt_ctrl_rx_agg_size);
- /* aggregation buf size, only work when BT control Rx aggregation size. */
- btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size);
- /* real update aggregation setting */
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
-}
-
-void halbtc8821aCsr2ant_query_bt_info(IN struct btc_coexist *btcoexist)
-{
- u8 h2c_parameter[1] = {0};
-
- coex_sta->c2h_bt_info_req_sent = true;
-
- h2c_parameter[0] |= BIT(0); /* trigger */
-
- rtw_warn_on_8821acsr2ant(_BTCOEX_CSR);
- btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter);
-}
-
-u8 halbtc8821aCsr2ant_action_algorithm(IN struct btc_coexist *btcoexist)
-{
- struct btc_stack_info *stack_info = &btcoexist->stack_info;
- boolean bt_hs_on = false;
- u8 algorithm = BT_8821A_CSR_2ANT_COEX_ALGO_UNDEFINED;
- u8 num_of_diff_profile = 0;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
-
- /* sync StackInfo with BT firmware and stack */
- stack_info->hid_exist = coex_sta->hid_exist;
- stack_info->bt_link_exist = coex_sta->bt_link_exist;
- stack_info->sco_exist = coex_sta->sco_exist;
- stack_info->pan_exist = coex_sta->pan_exist;
- stack_info->a2dp_exist = coex_sta->a2dp_exist;
-
- if (!stack_info->bt_link_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], No profile exists!!!\n");
- BTC_TRACE(trace_buf);
- return algorithm;
- }
-
- if (stack_info->sco_exist)
- num_of_diff_profile++;
- if (stack_info->hid_exist)
- num_of_diff_profile++;
- if (stack_info->pan_exist)
- num_of_diff_profile++;
- if (stack_info->a2dp_exist)
- num_of_diff_profile++;
-
- if (num_of_diff_profile == 1) {
- if (stack_info->sco_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO only\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8821A_CSR_2ANT_COEX_ALGO_SCO;
- } else {
- if (stack_info->hid_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], HID only\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8821A_CSR_2ANT_COEX_ALGO_HID;
- } else if (stack_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], A2DP only\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8821A_CSR_2ANT_COEX_ALGO_A2DP;
- } else if (stack_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], PAN(HS) only\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_CSR_2ANT_COEX_ALGO_PANHS;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], PAN(EDR) only\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR;
- }
- }
- }
- } else if (num_of_diff_profile == 2) {
- if (stack_info->sco_exist) {
- if (stack_info->hid_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + HID\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_HID;
- } else if (stack_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + A2DP ==> SCO\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_HID;
- } else if (stack_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_CSR_2ANT_COEX_ALGO_SCO;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_HID;
- }
- }
- } else {
- if (stack_info->hid_exist &&
- stack_info->a2dp_exist) {
- if (stack_info->num_of_hid >= 2) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], HID*2 + A2DP\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_CSR_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], HID + A2DP\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_CSR_2ANT_COEX_ALGO_HID_A2DP;
- }
- } else if (stack_info->hid_exist &&
- stack_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], HID + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_CSR_2ANT_COEX_ALGO_HID;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], HID + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_HID;
- }
- } else if (stack_info->pan_exist &&
- stack_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_CSR_2ANT_COEX_ALGO_A2DP_PANHS;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], A2DP + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_A2DP;
- }
- }
- }
- } else if (num_of_diff_profile == 3) {
- if (stack_info->sco_exist) {
- if (stack_info->hid_exist &&
- stack_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + HID + A2DP ==> HID\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_HID;
- } else if (stack_info->hid_exist &&
- stack_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + HID + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_HID;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + HID + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_HID;
- }
- } else if (stack_info->pan_exist &&
- stack_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_HID;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_HID;
- }
- }
- } else {
- if (stack_info->hid_exist &&
- stack_info->pan_exist &&
- stack_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], HID + A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_CSR_2ANT_COEX_ALGO_HID_A2DP;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], HID + A2DP + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_CSR_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
- }
- }
- }
- } else if (num_of_diff_profile >= 3) {
- if (stack_info->sco_exist) {
- if (stack_info->hid_exist &&
- stack_info->pan_exist &&
- stack_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
-
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_HID;
- }
- }
- }
- }
-
- return algorithm;
-}
-
-boolean halbtc8821aCsr2ant_need_to_dec_bt_pwr(IN struct btc_coexist *btcoexist)
-{
- boolean ret = false;
- boolean bt_hs_on = false, wifi_connected = false;
- s32 bt_hs_rssi = 0;
- u8 bt_rssi_state;
-
- if (!btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on))
- return false;
- if (!btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected))
- return false;
- if (!btcoexist->btc_get(btcoexist, BTC_GET_S4_HS_RSSI, &bt_hs_rssi))
- return false;
-
- bt_rssi_state = halbtc8821aCsr2ant_bt_rssi_state(2, 35, 0);
-
- if (wifi_connected) {
- if (bt_hs_on) {
- if (bt_hs_rssi > 37)
- ret = true;
- } else {
- if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH))
- ret = true;
- }
- }
-
- return ret;
-}
-
-void halbtc8821aCsr2ant_set_fw_dac_swing_level(IN struct btc_coexist *btcoexist,
- IN u8 dac_swing_lvl)
-{
- u8 h2c_parameter[1] = {0};
-
- /* There are several type of dacswing */
- /* 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */
- h2c_parameter[0] = dac_swing_lvl;
-
- btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter);
-}
-
-void halbtc8821aCsr2ant_set_fw_dec_bt_pwr(IN struct btc_coexist *btcoexist,
- IN boolean dec_bt_pwr)
-{
- u8 h2c_parameter[1] = {0};
-
- h2c_parameter[0] = 0;
-
- if (dec_bt_pwr)
- h2c_parameter[0] |= BIT(1);
-
- rtw_warn_on_8821acsr2ant(_BTCOEX_CSR);
- btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter);
-}
-
-void halbtc8821aCsr2ant_dec_bt_pwr(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean dec_bt_pwr)
-{
- coex_dm->cur_dec_bt_pwr = dec_bt_pwr;
-
- if (!force_exec) {
- if (coex_dm->pre_dec_bt_pwr == coex_dm->cur_dec_bt_pwr)
- return;
- }
-
- /* TODO: may CSR consider to decrease BT power? */
- /* halbtc8821aCsr2ant_set_fw_dec_bt_pwr(btcoexist, coex_dm->cur_dec_bt_pwr); */
-
- coex_dm->pre_dec_bt_pwr = coex_dm->cur_dec_bt_pwr;
-}
-
-void halbtc8821aCsr2ant_set_bt_auto_report(IN struct btc_coexist *btcoexist,
- IN boolean enable_auto_report)
-{
- u8 h2c_parameter[1] = {0};
-
- h2c_parameter[0] = 0;
-
- if (enable_auto_report)
- h2c_parameter[0] |= BIT(0);
-
- rtw_warn_on_8821acsr2ant(_BTCOEX_CSR);
- btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter);
-}
-
-void halbtc8821aCsr2ant_bt_auto_report(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean enable_auto_report)
-{
- coex_dm->cur_bt_auto_report = enable_auto_report;
-
- if (!force_exec) {
- if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report)
- return;
- }
- /* halbtc8821aCsr2ant_set_bt_auto_report(btcoexist, coex_dm->cur_bt_auto_report); */
-
- coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report;
-}
-
-void halbtc8821aCsr2ant_fw_dac_swing_lvl(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 fw_dac_swing_lvl)
-{
- coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl;
-
- if (!force_exec) {
- if (coex_dm->pre_fw_dac_swing_lvl ==
- coex_dm->cur_fw_dac_swing_lvl)
- return;
- }
-
- halbtc8821aCsr2ant_set_fw_dac_swing_level(btcoexist,
- coex_dm->cur_fw_dac_swing_lvl);
-
- coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl;
-}
-
-void halbtc8821aCsr2ant_set_sw_rf_rx_lpf_corner(IN struct btc_coexist
- *btcoexist, IN boolean rx_rf_shrink_on)
-{
- if (rx_rf_shrink_on) {
- /* Shrink RF Rx LPF corner */
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Shrink RF Rx LPF corner!!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, 0xfffff,
- 0xffffc);
- } else {
- /* Resume RF Rx LPF corner */
- /* After initialized, we can use coex_dm->bt_rf_0x1e_backup */
- if (btcoexist->initilized) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Resume RF Rx LPF corner!!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e,
- 0xfffff, coex_dm->bt_rf_0x1e_backup);
- }
- }
-}
-
-void halbtc8821aCsr2ant_rf_shrink(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean rx_rf_shrink_on)
-{
- coex_dm->cur_rf_rx_lpf_shrink = rx_rf_shrink_on;
-
- if (!force_exec) {
- if (coex_dm->pre_rf_rx_lpf_shrink ==
- coex_dm->cur_rf_rx_lpf_shrink)
- return;
- }
- halbtc8821aCsr2ant_set_sw_rf_rx_lpf_corner(btcoexist,
- coex_dm->cur_rf_rx_lpf_shrink);
-
- coex_dm->pre_rf_rx_lpf_shrink = coex_dm->cur_rf_rx_lpf_shrink;
-}
-
-void halbtc8821aCsr2ant_set_sw_penalty_tx_rate_adaptive(
- IN struct btc_coexist *btcoexist, IN boolean low_penalty_ra)
-{
- u8 h2c_parameter[6] = {0};
-
- h2c_parameter[0] = 0x6; /* op_code, 0x6= Retry_Penalty */
-
- if (low_penalty_ra) {
- h2c_parameter[1] |= BIT(0);
- h2c_parameter[2] =
- 0x00; /* normal rate except MCS7/6/5, OFDM54/48/36 */
- h2c_parameter[3] = 0xf7; /* MCS7 or OFDM54 */
- h2c_parameter[4] = 0xf8; /* MCS6 or OFDM48 */
- h2c_parameter[5] = 0xf9; /* MCS5 or OFDM36 */
- }
-
- btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter);
-}
-
-void halbtc8821aCsr2ant_low_penalty_ra(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean low_penalty_ra)
-{
- coex_dm->cur_low_penalty_ra = low_penalty_ra;
-
- if (!force_exec) {
- if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra)
- return;
- }
- halbtc8821aCsr2ant_set_sw_penalty_tx_rate_adaptive(btcoexist,
- coex_dm->cur_low_penalty_ra);
-
- coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra;
-}
-
-void halbtc8821aCsr2ant_set_dac_swing_reg(IN struct btc_coexist *btcoexist,
- IN u32 level)
-{
- u8 val = (u8)level;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Write SwDacSwing = 0x%x\n", level);
- BTC_TRACE(trace_buf);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc5b, 0x3e, val);
-}
-
-void halbtc8821aCsr2ant_set_sw_full_time_dac_swing(IN struct btc_coexist
- *btcoexist, IN boolean sw_dac_swing_on, IN u32 sw_dac_swing_lvl)
-{
- if (sw_dac_swing_on)
- halbtc8821aCsr2ant_set_dac_swing_reg(btcoexist,
- sw_dac_swing_lvl);
- else
- halbtc8821aCsr2ant_set_dac_swing_reg(btcoexist, 0x18);
-}
-
-
-void halbtc8821aCsr2ant_dac_swing(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean dac_swing_on, IN u32 dac_swing_lvl)
-{
- coex_dm->cur_dac_swing_on = dac_swing_on;
- coex_dm->cur_dac_swing_lvl = dac_swing_lvl;
-
- if (!force_exec) {
- if ((coex_dm->pre_dac_swing_on == coex_dm->cur_dac_swing_on) &&
- (coex_dm->pre_dac_swing_lvl ==
- coex_dm->cur_dac_swing_lvl))
- return;
- }
- delay_ms(30);
- halbtc8821aCsr2ant_set_sw_full_time_dac_swing(btcoexist, dac_swing_on,
- dac_swing_lvl);
-
- coex_dm->pre_dac_swing_on = coex_dm->cur_dac_swing_on;
- coex_dm->pre_dac_swing_lvl = coex_dm->cur_dac_swing_lvl;
-}
-
-void halbtc8821aCsr2ant_set_adc_back_off(IN struct btc_coexist *btcoexist,
- IN boolean adc_back_off)
-{
- if (adc_back_off) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BB BackOff Level On!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x8db, 0x60, 0x3);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BB BackOff Level Off!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x8db, 0x60, 0x1);
- }
-}
-
-void halbtc8821aCsr2ant_adc_back_off(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean adc_back_off)
-{
- coex_dm->cur_adc_back_off = adc_back_off;
-
- if (!force_exec) {
- if (coex_dm->pre_adc_back_off == coex_dm->cur_adc_back_off)
- return;
- }
- halbtc8821aCsr2ant_set_adc_back_off(btcoexist,
- coex_dm->cur_adc_back_off);
-
- coex_dm->pre_adc_back_off = coex_dm->cur_adc_back_off;
-}
-
-void halbtc8821aCsr2ant_set_agc_table(IN struct btc_coexist *btcoexist,
- IN boolean agc_table_en)
-{
- u8 rssi_adjust_val = 0;
-
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xef, 0xfffff, 0x02000);
- if (agc_table_en) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Agc Table On!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff,
- 0x28F4B);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff,
- 0x10AB2);
- rssi_adjust_val = 8;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Agc Table Off!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff,
- 0x2884B);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff,
- 0x104B2);
- }
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xef, 0xfffff, 0x0);
-
- /* set rssi_adjust_val for wifi module. */
- btcoexist->btc_set(btcoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON,
- &rssi_adjust_val);
-}
-
-void halbtc8821aCsr2ant_agc_table(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean agc_table_en)
-{
- coex_dm->cur_agc_table_en = agc_table_en;
-
- if (!force_exec) {
- if (coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en)
- return;
- }
- halbtc8821aCsr2ant_set_agc_table(btcoexist, agc_table_en);
-
- coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en;
-}
-
-void halbtc8821aCsr2ant_set_coex_table(IN struct btc_coexist *btcoexist,
- IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc)
-{
- btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
-
- btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
-
- btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
-
- btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
-}
-
-void halbtc8821aCsr2ant_coex_table(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4,
- IN u32 val0x6c8, IN u8 val0x6cc)
-{
- coex_dm->cur_val0x6c0 = val0x6c0;
- coex_dm->cur_val0x6c4 = val0x6c4;
- coex_dm->cur_val0x6c8 = val0x6c8;
- coex_dm->cur_val0x6cc = val0x6cc;
-
- if (!force_exec) {
- if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) &&
- (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) &&
- (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) &&
- (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc))
- return;
- }
- halbtc8821aCsr2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4,
- val0x6c8, val0x6cc);
-
- coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0;
- coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4;
- coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8;
- coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc;
-}
-
-void halbtc8821aCsr2ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist,
- IN boolean enable)
-{
- u8 h2c_parameter[1] = {0};
-
- if (enable) {
- h2c_parameter[0] |= BIT(0); /* function enable */
- }
-
- rtw_warn_on_8821acsr2ant(_BTCOEX_CSR);
- btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter);
-}
-
-void halbtc8821aCsr2ant_ignore_wlan_act(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean enable)
-{
- coex_dm->cur_ignore_wlan_act = enable;
-
- if (!force_exec) {
- if (coex_dm->pre_ignore_wlan_act ==
- coex_dm->cur_ignore_wlan_act)
- return;
- }
- /* halbtc8821aCsr2ant_set_fw_ignore_wlan_act(btcoexist, enable); */
-
- coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
-}
-
-void halbtc8821aCsr2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist,
- IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5)
-{
- u8 h2c_parameter[6] = {0};
-
- h2c_parameter[0] = byte1;
- h2c_parameter[1] = byte2;
- h2c_parameter[2] = byte3;
- h2c_parameter[3] = byte4;
- h2c_parameter[4] = byte5;
- h2c_parameter[5] = 0x01;
-
- coex_dm->ps_tdma_para[0] = byte1;
- coex_dm->ps_tdma_para[1] = byte2;
- coex_dm->ps_tdma_para[2] = byte3;
- coex_dm->ps_tdma_para[3] = byte4;
- coex_dm->ps_tdma_para[4] = byte5;
- coex_dm->ps_tdma_para[5] = 0x01;
-
- btcoexist->btc_fill_h2c(btcoexist, 0x60, 6, h2c_parameter);
-}
-
-void halbtc8821aCsr2ant_sw_mechanism1(IN struct btc_coexist *btcoexist,
- IN boolean shrink_rx_lpf, IN boolean low_penalty_ra,
- IN boolean limited_dig, IN boolean bt_lna_constrain)
-{
- u32 wifi_bw;
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- if (BTC_WIFI_BW_HT40 != wifi_bw) { /* only shrink RF Rx LPF for HT40 */
- if (shrink_rx_lpf)
- shrink_rx_lpf = false;
- }
-
- halbtc8821aCsr2ant_rf_shrink(btcoexist, NORMAL_EXEC, shrink_rx_lpf);
- halbtc8821aCsr2ant_low_penalty_ra(btcoexist, NORMAL_EXEC,
- low_penalty_ra);
-
- /* no limited DIG */
- /* halbtc8821aCsr2ant_setBtLnaConstrain(btcoexist, NORMAL_EXEC, bt_lna_constrain); */
-}
-
-void halbtc8821aCsr2ant_sw_mechanism2(IN struct btc_coexist *btcoexist,
- IN boolean agc_table_shift, IN boolean adc_back_off,
- IN boolean sw_dac_swing, IN u32 dac_swing_lvl)
-{
- /* halbtc8821aCsr2ant_agc_table(btcoexist, NORMAL_EXEC, agc_table_shift); */
- halbtc8821aCsr2ant_adc_back_off(btcoexist, NORMAL_EXEC, adc_back_off);
- halbtc8821aCsr2ant_dac_swing(btcoexist, NORMAL_EXEC, sw_dac_swing,
- dac_swing_lvl);
-}
-
-void halbtc8821aCsr2ant_set_ant_path(IN struct btc_coexist *btcoexist,
- IN u8 ant_pos_type, IN boolean init_hwcfg, IN boolean wifi_off)
-{
- struct btc_board_info *board_info = &btcoexist->board_info;
- u32 u32tmp = 0;
- u8 h2c_parameter[2] = {0};
-
- if (init_hwcfg) {
- /* 0x4c[23]=0, 0x4c[24]=1 Antenna control by WL/BT */
- u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c);
- u32tmp &= ~BIT(23);
- u32tmp |= BIT(24);
- btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp);
-
- btcoexist->btc_write_4byte(btcoexist, 0x974, 0x3ff);
- btcoexist->btc_write_1byte(btcoexist, 0xcb4, 0x77);
-
- if (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT) {
- /* tell firmware "antenna inverse" ==> WRONG firmware antenna control code.==>need fw to fix */
- h2c_parameter[0] = 1;
- h2c_parameter[1] = 1;
- btcoexist->btc_fill_h2c(btcoexist, 0x65, 2,
- h2c_parameter);
- } else {
- /* tell firmware "no antenna inverse" ==> WRONG firmware antenna control code.==>need fw to fix */
- h2c_parameter[0] = 0;
- h2c_parameter[1] = 1;
- btcoexist->btc_fill_h2c(btcoexist, 0x65, 2,
- h2c_parameter);
- }
- }
-
- /* ext switch setting */
- switch (ant_pos_type) {
- case BTC_ANT_WIFI_AT_MAIN:
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb7,
- 0x30, 0x1);
- break;
- case BTC_ANT_WIFI_AT_AUX:
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb7,
- 0x30, 0x2);
- break;
- }
-}
-
-void halbtc8821aCsr2ant_ps_tdma(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean turn_on, IN u8 type)
-{
- coex_dm->cur_ps_tdma_on = turn_on;
- coex_dm->cur_ps_tdma = type;
-
- if (!force_exec) {
- if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) &&
- (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma))
- return;
- }
- if (turn_on) {
- switch (type) {
- case 1:
- default:
- halbtc8821aCsr2ant_set_fw_pstdma(btcoexist,
- 0xe3, 0x1a, 0x1a, 0xe1, 0x90);
- break;
- case 2:
- halbtc8821aCsr2ant_set_fw_pstdma(btcoexist,
- 0xe3, 0x12, 0x12, 0xe1, 0x90);
- break;
- case 3:
- halbtc8821aCsr2ant_set_fw_pstdma(btcoexist,
- 0xe3, 0x1c, 0x3, 0xf1, 0x90);
- break;
- case 4:
- halbtc8821aCsr2ant_set_fw_pstdma(btcoexist,
- 0xe3, 0x10, 0x03, 0xf1, 0x90);
- break;
- case 5:
- halbtc8821aCsr2ant_set_fw_pstdma(btcoexist,
- 0xe3, 0x1a, 0x1a, 0x60, 0x90);
- break;
- case 6:
- halbtc8821aCsr2ant_set_fw_pstdma(btcoexist,
- 0xe3, 0x12, 0x12, 0x60, 0x90);
- break;
- case 7:
- halbtc8821aCsr2ant_set_fw_pstdma(btcoexist,
- 0xe3, 0x1c, 0x3, 0x70, 0x90);
- break;
- case 8:
- halbtc8821aCsr2ant_set_fw_pstdma(btcoexist,
- 0xa3, 0x10, 0x3, 0x70, 0x90);
- break;
- case 9:
- halbtc8821aCsr2ant_set_fw_pstdma(btcoexist,
- 0xe3, 0x1a, 0x1a, 0xe1, 0x90);
- break;
- case 10:
- halbtc8821aCsr2ant_set_fw_pstdma(btcoexist,
- 0xe3, 0x12, 0x12, 0xe1, 0x90);
- break;
- case 11:
- halbtc8821aCsr2ant_set_fw_pstdma(btcoexist,
- 0xe3, 0xa, 0xa, 0xe1, 0x90);
- break;
- case 12:
- halbtc8821aCsr2ant_set_fw_pstdma(btcoexist,
- 0xe3, 0x5, 0x5, 0xe1, 0x90);
- break;
- case 13:
- halbtc8821aCsr2ant_set_fw_pstdma(btcoexist,
- 0xe3, 0x1a, 0x1a, 0x60, 0x90);
- break;
- case 14:
- halbtc8821aCsr2ant_set_fw_pstdma(btcoexist,
- 0xe3, 0x12, 0x12, 0x60, 0x90);
- break;
- case 15:
- halbtc8821aCsr2ant_set_fw_pstdma(btcoexist,
- 0xe3, 0xa, 0xa, 0x60, 0x90);
- break;
- case 16:
- halbtc8821aCsr2ant_set_fw_pstdma(btcoexist,
- 0xe3, 0x5, 0x5, 0x60, 0x90);
- break;
- case 17:
- halbtc8821aCsr2ant_set_fw_pstdma(btcoexist,
- 0xa3, 0x2f, 0x2f, 0x60, 0x90);
- break;
- case 18:
- halbtc8821aCsr2ant_set_fw_pstdma(btcoexist,
- 0xe3, 0x5, 0x5, 0xe1, 0x90);
- break;
- case 19:
- halbtc8821aCsr2ant_set_fw_pstdma(btcoexist,
- 0xe3, 0x25, 0x25, 0xe1, 0x90);
- break;
- case 20:
- halbtc8821aCsr2ant_set_fw_pstdma(btcoexist,
- 0xe3, 0x25, 0x25, 0x60, 0x90);
- break;
- case 21:
- halbtc8821aCsr2ant_set_fw_pstdma(btcoexist,
- 0xe3, 0x15, 0x03, 0x70, 0x90);
- break;
- case 22: /* ad2dp master */
- halbtc8821aCsr2ant_set_fw_pstdma(btcoexist,
- 0xeb, 0x11, 0x11, 0x21, 0x10);
- break;
- case 23: /* a2dp slave */
- halbtc8821aCsr2ant_set_fw_pstdma(btcoexist,
- 0xeb, 0x12, 0x12, 0x20, 0x10);
- break;
- case 71:
- halbtc8821aCsr2ant_set_fw_pstdma(btcoexist,
- 0xe3, 0x1a, 0x1a, 0xe1, 0x90);
- break;
- }
- } else {
- /* disable PS tdma */
- switch (type) {
- case 0:
- halbtc8821aCsr2ant_set_fw_pstdma(btcoexist, 0x0,
- 0x0, 0x0, 0x40, 0x0);
- break;
- case 1:
- halbtc8821aCsr2ant_set_fw_pstdma(btcoexist, 0x0,
- 0x0, 0x0, 0x48, 0x0);
- break;
- default:
- halbtc8821aCsr2ant_set_fw_pstdma(btcoexist, 0x0,
- 0x0, 0x0, 0x40, 0x0);
- break;
- }
- }
-
- /* update pre state */
- coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on;
- coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
-}
-
-void halbtc8821aCsr2ant_coex_all_off(IN struct btc_coexist *btcoexist)
-{
- /* fw all off */
- halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
- halbtc8821aCsr2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
- halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
-
- /* sw all off */
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false, false, false, false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
-
- /* hw all off */
- halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC, 0x55555555,
- 0x55555555, 0xffff, 0x3);
-}
-
-void halbtc8821aCsr2ant_coex_under_5g(IN struct btc_coexist *btcoexist)
-{
- halbtc8821aCsr2ant_coex_all_off(btcoexist);
-
- halbtc8821aCsr2ant_ignore_wlan_act(btcoexist, NORMAL_EXEC, true);
-}
-
-void halbtc8821aCsr2ant_init_coex_dm(IN struct btc_coexist *btcoexist)
-{
- /* force to reset coex mechanism */
- halbtc8821aCsr2ant_coex_table(btcoexist, FORCE_EXEC, 0x55555555,
- 0x55555555, 0xffff, 0x3);
-
- halbtc8821aCsr2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 1);
- halbtc8821aCsr2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 6);
- halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, FORCE_EXEC, false);
-
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false, false, false, false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
-}
-
-void halbtc8821aCsr2ant_bt_inquiry_page(IN struct btc_coexist *btcoexist)
-{
- boolean low_pwr_disable = true;
-
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
-
- halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC, 0x55ff55ff,
- 0x5afa5afa, 0xffff, 0x3);
- halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3);
-}
-boolean halbtc8821aCsr2ant_is_common_action(IN struct btc_coexist *btcoexist)
-{
- boolean common = false, wifi_connected = false, wifi_busy = false;
- boolean low_pwr_disable = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- if (!wifi_connected &&
- BT_8821A_CSR_2ANT_BT_STATUS_IDLE == coex_dm->bt_status) {
- low_pwr_disable = false;
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi IPS + BT IPS!!\n");
- BTC_TRACE(trace_buf);
-
-
- halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
- halbtc8821aCsr2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
- halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
-
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false, false, false,
- false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false, false, false,
- 0x18);
- halbtc8821aCsr2ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0,
- 0, 0);
- halbtc8821aCsr2ant_limited_rx(btcoexist, NORMAL_EXEC, 0, 0, 0);
-
- common = true;
- } else if (wifi_connected &&
- (BT_8821A_CSR_2ANT_BT_STATUS_IDLE ==
- coex_dm->bt_status)) {
- low_pwr_disable = false;
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
-
- if (wifi_busy) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi Busy + BT IPS!!\n");
- BTC_TRACE(trace_buf);
- halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC,
- false, 1);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi LPS + BT IPS!!\n");
- BTC_TRACE(trace_buf);
- halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC,
- false, 1);
- }
-
- halbtc8821aCsr2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
- halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
-
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false, false, false,
- false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false, false, false,
- 0x18);
- halbtc8821aCsr2ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0,
- 0, 0);
- halbtc8821aCsr2ant_limited_rx(btcoexist, NORMAL_EXEC, 0, 0, 0);
-
- common = true;
- } else if (!wifi_connected &&
- (BT_8821A_CSR_2ANT_BT_STATUS_CONNECTED_IDLE ==
- coex_dm->bt_status)) {
- low_pwr_disable = true;
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi IPS + BT LPS!!\n");
- BTC_TRACE(trace_buf);
-
- halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
- halbtc8821aCsr2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
- halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
-
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false, false, false,
- false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false, false, false,
- 0x18);
- halbtc8821aCsr2ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0,
- 0, 0);
- halbtc8821aCsr2ant_limited_rx(btcoexist, NORMAL_EXEC, 0, 0, 0);
-
- common = true;
- } else if (wifi_connected &&
- (BT_8821A_CSR_2ANT_BT_STATUS_CONNECTED_IDLE ==
- coex_dm->bt_status)) {
- low_pwr_disable = true;
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
-
- if (wifi_busy) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi Busy + BT LPS!!\n");
- BTC_TRACE(trace_buf);
- halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC,
- false, 1);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi LPS + BT LPS!!\n");
- BTC_TRACE(trace_buf);
- halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC,
- false, 1);
- }
-
- halbtc8821aCsr2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
- halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
-
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, true, true, true,
- true);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false, false, false,
- 0x18);
- halbtc8821aCsr2ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0,
- 0, 0);
- halbtc8821aCsr2ant_limited_rx(btcoexist, NORMAL_EXEC, 0, 0, 0);
-
- common = true;
- } else if (!wifi_connected &&
- (BT_8821A_CSR_2ANT_BT_STATUS_NON_IDLE ==
- coex_dm->bt_status)) {
- low_pwr_disable = false;
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi IPS + BT Busy!!\n");
- BTC_TRACE(trace_buf);
-
- /* halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1); */
- halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- halbtc8821aCsr2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
- halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
-
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false, false, false,
- false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false, false, false,
- 0x18);
- halbtc8821aCsr2ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0,
- 0, 0);
- halbtc8821aCsr2ant_limited_rx(btcoexist, NORMAL_EXEC, 0, 0, 0);
-
- common = true;
- } else {
- low_pwr_disable = true;
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
-
- if (wifi_busy) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi Busy + BT Busy!!\n");
- BTC_TRACE(trace_buf);
- common = false;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi LPS + BT Busy!!\n");
- BTC_TRACE(trace_buf);
- halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 21);
-
- if (halbtc8821aCsr2ant_need_to_dec_bt_pwr(btcoexist))
- halbtc8821aCsr2ant_dec_bt_pwr(btcoexist,
- NORMAL_EXEC, true);
- else
- halbtc8821aCsr2ant_dec_bt_pwr(btcoexist,
- NORMAL_EXEC, false);
-
- common = true;
- }
-
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, true, true, true,
- true);
- }
-
- if (common == true)
- halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC,
- 0x55ff55ff, 0x5afa5afa, 0xffff, 0x3);
-
- return common;
-}
-void halbtc8821aCsr2ant_tdma_duration_adjust(IN struct btc_coexist *btcoexist,
- IN boolean sco_hid, IN boolean tx_pause, IN u8 max_interval)
-{
- static s32 up, dn, m, n, wait_count;
- s32 result; /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */
- u8 retry_count = 0;
-
- if (coex_dm->reset_tdma_adjust) {
- coex_dm->reset_tdma_adjust = false;
- {
- if (sco_hid) {
- if (tx_pause) {
- if (max_interval == 1) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 13);
- coex_dm->ps_tdma_du_adj_type =
- 13;
- } else if (max_interval == 2) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 14);
- coex_dm->ps_tdma_du_adj_type =
- 14;
- } else if (max_interval == 3) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- }
- } else {
- if (max_interval == 1) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 9);
- coex_dm->ps_tdma_du_adj_type =
- 9;
- } else if (max_interval == 2) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 10);
- coex_dm->ps_tdma_du_adj_type =
- 10;
- } else if (max_interval == 3) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- }
- }
- } else {
- if (tx_pause) {
- if (max_interval == 1) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 5);
- coex_dm->ps_tdma_du_adj_type =
- 5;
- } else if (max_interval == 2) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 6);
- coex_dm->ps_tdma_du_adj_type =
- 6;
- } else if (max_interval == 3) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- }
- } else {
- if (max_interval == 1) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 1);
- coex_dm->ps_tdma_du_adj_type =
- 1;
- } else if (max_interval == 2) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 2);
- coex_dm->ps_tdma_du_adj_type =
- 2;
- } else if (max_interval == 3) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- }
- }
- }
- }
- /* ============ */
- up = 0;
- dn = 0;
- m = 1;
- n = 3;
- result = 0;
- wait_count = 0;
- } else {
- /* accquire the BT TRx retry count from BT_Info byte2 */
- retry_count = coex_sta->bt_retry_cnt;
- result = 0;
- wait_count++;
-
- if (retry_count ==
- 0) { /* no retry in the last 2-second duration */
- up++;
- dn--;
-
- if (dn <= 0)
- dn = 0;
-
- if (up >= n) { /* if ³sÄò n Ó2¬í retry count¬°0, «h½Õ¼eWiFi duration */
- wait_count = 0;
- n = 3;
- up = 0;
- dn = 0;
- result = 1;
- }
- } else if (retry_count <=
- 3) { /* <=3 retry in the last 2-second duration */
- up--;
- dn++;
-
- if (up <= 0)
- up = 0;
-
- if (dn == 2) { /* if ³sÄò 2 Ó2¬í retry count< 3, «h½Õ¯¶WiFi duration */
- if (wait_count <= 2)
- m++; /* ÁקK¤@ª½¦b¨âÓlevel¤¤¨Ó¦^ */
- else
- m = 1;
-
- if (m >= 20) /* m ³Ì¤jÈ = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration. */
- m = 20;
-
- n = 3 * m;
- up = 0;
- dn = 0;
- wait_count = 0;
- result = -1;
- }
- } else { /* retry count > 3, ¥un1¦¸ retry count > 3, «h½Õ¯¶WiFi duration */
- if (wait_count == 1)
- m++; /* ÁקK¤@ª½¦b¨âÓlevel¤¤¨Ó¦^ */
- else
- m = 1;
-
- if (m >= 20) /* m ³Ì¤jÈ = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration. */
- m = 20;
-
- n = 3 * m;
- up = 0;
- dn = 0;
- wait_count = 0;
- result = -1;
- }
-
- if (max_interval == 1) {
- if (tx_pause) {
- if (coex_dm->cur_ps_tdma == 71) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 5);
- coex_dm->ps_tdma_du_adj_type = 5;
- } else if (coex_dm->cur_ps_tdma == 1) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 5);
- coex_dm->ps_tdma_du_adj_type = 5;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 6);
- coex_dm->ps_tdma_du_adj_type = 6;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 7);
- coex_dm->ps_tdma_du_adj_type = 7;
- } else if (coex_dm->cur_ps_tdma == 4) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 8);
- coex_dm->ps_tdma_du_adj_type = 8;
- }
- if (coex_dm->cur_ps_tdma == 9) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 13);
- coex_dm->ps_tdma_du_adj_type = 13;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 14);
- coex_dm->ps_tdma_du_adj_type = 14;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 15);
- coex_dm->ps_tdma_du_adj_type = 15;
- } else if (coex_dm->cur_ps_tdma == 12) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 16);
- coex_dm->ps_tdma_du_adj_type = 16;
- }
-
- if (result == -1) {
- if (coex_dm->cur_ps_tdma == 5) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 6);
- coex_dm->ps_tdma_du_adj_type =
- 6;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 8);
- coex_dm->ps_tdma_du_adj_type =
- 8;
- } else if (coex_dm->cur_ps_tdma == 13) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 14);
- coex_dm->ps_tdma_du_adj_type =
- 14;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 16);
- coex_dm->ps_tdma_du_adj_type =
- 16;
- }
- } else if (result == 1) {
- if (coex_dm->cur_ps_tdma == 8) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 6);
- coex_dm->ps_tdma_du_adj_type =
- 6;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 5);
- coex_dm->ps_tdma_du_adj_type =
- 5;
- } else if (coex_dm->cur_ps_tdma == 16) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 14);
- coex_dm->ps_tdma_du_adj_type =
- 14;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 13);
- coex_dm->ps_tdma_du_adj_type =
- 13;
- }
- }
- } else {
- if (coex_dm->cur_ps_tdma == 5) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 71);
- coex_dm->ps_tdma_du_adj_type = 71;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 2);
- coex_dm->ps_tdma_du_adj_type = 2;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 3);
- coex_dm->ps_tdma_du_adj_type = 3;
- } else if (coex_dm->cur_ps_tdma == 8) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 4);
- coex_dm->ps_tdma_du_adj_type = 4;
- }
- if (coex_dm->cur_ps_tdma == 13) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 9);
- coex_dm->ps_tdma_du_adj_type = 9;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 10);
- coex_dm->ps_tdma_du_adj_type = 10;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 11);
- coex_dm->ps_tdma_du_adj_type = 11;
- } else if (coex_dm->cur_ps_tdma == 16) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 12);
- coex_dm->ps_tdma_du_adj_type = 12;
- }
-
- if (result == -1) {
- if (coex_dm->cur_ps_tdma == 71) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 1);
- coex_dm->ps_tdma_du_adj_type =
- 1;
- } else if (coex_dm->cur_ps_tdma == 1) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 2);
- coex_dm->ps_tdma_du_adj_type =
- 2;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 4);
- coex_dm->ps_tdma_du_adj_type =
- 4;
- } else if (coex_dm->cur_ps_tdma == 9) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 10);
- coex_dm->ps_tdma_du_adj_type =
- 10;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 12);
- coex_dm->ps_tdma_du_adj_type =
- 12;
- }
- } else if (result == 1) {
- if (coex_dm->cur_ps_tdma == 4) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 2);
- coex_dm->ps_tdma_du_adj_type =
- 2;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 1);
- coex_dm->ps_tdma_du_adj_type =
- 1;
- } else if (coex_dm->cur_ps_tdma == 1) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 71);
- coex_dm->ps_tdma_du_adj_type =
- 71;
- } else if (coex_dm->cur_ps_tdma == 12) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 10);
- coex_dm->ps_tdma_du_adj_type =
- 10;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 9);
- coex_dm->ps_tdma_du_adj_type =
- 9;
- }
- }
- }
- } else if (max_interval == 2) {
- if (tx_pause) {
- if (coex_dm->cur_ps_tdma == 1) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 6);
- coex_dm->ps_tdma_du_adj_type = 6;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 6);
- coex_dm->ps_tdma_du_adj_type = 6;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 7);
- coex_dm->ps_tdma_du_adj_type = 7;
- } else if (coex_dm->cur_ps_tdma == 4) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 8);
- coex_dm->ps_tdma_du_adj_type = 8;
- }
- if (coex_dm->cur_ps_tdma == 9) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 14);
- coex_dm->ps_tdma_du_adj_type = 14;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 14);
- coex_dm->ps_tdma_du_adj_type = 14;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 15);
- coex_dm->ps_tdma_du_adj_type = 15;
- } else if (coex_dm->cur_ps_tdma == 12) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 16);
- coex_dm->ps_tdma_du_adj_type = 16;
- }
- if (result == -1) {
- if (coex_dm->cur_ps_tdma == 5) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 6);
- coex_dm->ps_tdma_du_adj_type =
- 6;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 8);
- coex_dm->ps_tdma_du_adj_type =
- 8;
- } else if (coex_dm->cur_ps_tdma == 13) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 14);
- coex_dm->ps_tdma_du_adj_type =
- 14;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 16);
- coex_dm->ps_tdma_du_adj_type =
- 16;
- }
- } else if (result == 1) {
- if (coex_dm->cur_ps_tdma == 8) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 6);
- coex_dm->ps_tdma_du_adj_type =
- 6;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 6);
- coex_dm->ps_tdma_du_adj_type =
- 6;
- } else if (coex_dm->cur_ps_tdma == 16) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 14);
- coex_dm->ps_tdma_du_adj_type =
- 14;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 14);
- coex_dm->ps_tdma_du_adj_type =
- 14;
- }
- }
- } else {
- if (coex_dm->cur_ps_tdma == 5) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 2);
- coex_dm->ps_tdma_du_adj_type = 2;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 2);
- coex_dm->ps_tdma_du_adj_type = 2;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 3);
- coex_dm->ps_tdma_du_adj_type = 3;
- } else if (coex_dm->cur_ps_tdma == 8) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 4);
- coex_dm->ps_tdma_du_adj_type = 4;
- }
- if (coex_dm->cur_ps_tdma == 13) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 10);
- coex_dm->ps_tdma_du_adj_type = 10;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 10);
- coex_dm->ps_tdma_du_adj_type = 10;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 11);
- coex_dm->ps_tdma_du_adj_type = 11;
- } else if (coex_dm->cur_ps_tdma == 16) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 12);
- coex_dm->ps_tdma_du_adj_type = 12;
- }
- if (result == -1) {
- if (coex_dm->cur_ps_tdma == 1) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 2);
- coex_dm->ps_tdma_du_adj_type =
- 2;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 4);
- coex_dm->ps_tdma_du_adj_type =
- 4;
- } else if (coex_dm->cur_ps_tdma == 9) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 10);
- coex_dm->ps_tdma_du_adj_type =
- 10;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 12);
- coex_dm->ps_tdma_du_adj_type =
- 12;
- }
- } else if (result == 1) {
- if (coex_dm->cur_ps_tdma == 4) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 2);
- coex_dm->ps_tdma_du_adj_type =
- 2;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 2);
- coex_dm->ps_tdma_du_adj_type =
- 2;
- } else if (coex_dm->cur_ps_tdma == 12) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 10);
- coex_dm->ps_tdma_du_adj_type =
- 10;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 10);
- coex_dm->ps_tdma_du_adj_type =
- 10;
- }
- }
- }
- } else if (max_interval == 3) {
- if (tx_pause) {
- if (coex_dm->cur_ps_tdma == 1) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 7);
- coex_dm->ps_tdma_du_adj_type = 7;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 7);
- coex_dm->ps_tdma_du_adj_type = 7;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 7);
- coex_dm->ps_tdma_du_adj_type = 7;
- } else if (coex_dm->cur_ps_tdma == 4) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 8);
- coex_dm->ps_tdma_du_adj_type = 8;
- }
- if (coex_dm->cur_ps_tdma == 9) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 15);
- coex_dm->ps_tdma_du_adj_type = 15;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 15);
- coex_dm->ps_tdma_du_adj_type = 15;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 15);
- coex_dm->ps_tdma_du_adj_type = 15;
- } else if (coex_dm->cur_ps_tdma == 12) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 16);
- coex_dm->ps_tdma_du_adj_type = 16;
- }
- if (result == -1) {
- if (coex_dm->cur_ps_tdma == 5) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 8);
- coex_dm->ps_tdma_du_adj_type =
- 8;
- } else if (coex_dm->cur_ps_tdma == 13) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 16);
- coex_dm->ps_tdma_du_adj_type =
- 16;
- }
- } else if (result == 1) {
- if (coex_dm->cur_ps_tdma == 8) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 7);
- coex_dm->ps_tdma_du_adj_type =
- 7;
- } else if (coex_dm->cur_ps_tdma == 16) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 15);
- coex_dm->ps_tdma_du_adj_type =
- 15;
- }
- }
- } else {
- if (coex_dm->cur_ps_tdma == 5) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 3);
- coex_dm->ps_tdma_du_adj_type = 3;
- } else if (coex_dm->cur_ps_tdma == 6) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 3);
- coex_dm->ps_tdma_du_adj_type = 3;
- } else if (coex_dm->cur_ps_tdma == 7) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 3);
- coex_dm->ps_tdma_du_adj_type = 3;
- } else if (coex_dm->cur_ps_tdma == 8) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 4);
- coex_dm->ps_tdma_du_adj_type = 4;
- }
- if (coex_dm->cur_ps_tdma == 13) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 11);
- coex_dm->ps_tdma_du_adj_type = 11;
- } else if (coex_dm->cur_ps_tdma == 14) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 11);
- coex_dm->ps_tdma_du_adj_type = 11;
- } else if (coex_dm->cur_ps_tdma == 15) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 11);
- coex_dm->ps_tdma_du_adj_type = 11;
- } else if (coex_dm->cur_ps_tdma == 16) {
- halbtc8821aCsr2ant_ps_tdma(btcoexist,
- NORMAL_EXEC, true, 12);
- coex_dm->ps_tdma_du_adj_type = 12;
- }
- if (result == -1) {
- if (coex_dm->cur_ps_tdma == 1) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 4);
- coex_dm->ps_tdma_du_adj_type =
- 4;
- } else if (coex_dm->cur_ps_tdma == 9) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 12);
- coex_dm->ps_tdma_du_adj_type =
- 12;
- }
- } else if (result == 1) {
- if (coex_dm->cur_ps_tdma == 4) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 3) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 2) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 3);
- coex_dm->ps_tdma_du_adj_type =
- 3;
- } else if (coex_dm->cur_ps_tdma == 12) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 11) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- } else if (coex_dm->cur_ps_tdma == 10) {
- halbtc8821aCsr2ant_ps_tdma(
- btcoexist, NORMAL_EXEC,
- true, 11);
- coex_dm->ps_tdma_du_adj_type =
- 11;
- }
- }
- }
- }
- }
-
- /* if current PsTdma not match with the recorded one (when scan, dhcp...), */
- /* then we have to adjust it back to the previous record one. */
- if (coex_dm->cur_ps_tdma != coex_dm->ps_tdma_du_adj_type) {
- boolean scan = false, link = false, roam = false;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], PsTdma type dismatch!!!, cur_ps_tdma=%d, recordPsTdma=%d\n",
- coex_dm->cur_ps_tdma, coex_dm->ps_tdma_du_adj_type);
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
-
- if (!scan && !link && !roam)
- halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- coex_dm->ps_tdma_du_adj_type);
- else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n");
- BTC_TRACE(trace_buf);
- }
- }
-
- /* when halbtc8821aCsr2ant_tdma_duration_adjust() is called, fw dac swing is included in the function. */
- /* if(coex_dm->ps_tdma_du_adj_type == 71) */
- /* halbtc8821aCsr2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc); //Skip because A2DP get worse at HT40 */
- /* else */
- halbtc8821aCsr2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC,
- 0x6);
-}
-
-/* SCO only or SCO+PAN(HS) */
-void halbtc8821aCsr2ant_action_sco(IN struct btc_coexist *btcoexist)
-{
- halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC, 0x55555555,
- 0x55555555, 0xffffff, 0x3);
- halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
-
- halbtc8821aCsr2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, true);
-
- halbtc8821aCsr2ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 1, 0, 2, 0);
-
- if (coex_sta->slave == false)
- halbtc8821aCsr2ant_limited_rx(btcoexist, NORMAL_EXEC, false,
- true, 0x4);
- else
- halbtc8821aCsr2ant_limited_rx(btcoexist, NORMAL_EXEC, false,
- true, 0x2);
-
- /*
- wifi_rssi_state = halbtc8821aCsr2ant_wifi_rssi_state(btcoexist, 0, 2, 15, 0);
- bt_rssi_state = halbtc8821aCsr2ant_bt_rssi_state(2, 35, 0);
-
- halbtc8821aCsr2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 4);
-
- if(halbtc8821aCsr2ant_need_to_dec_bt_pwr(btcoexist))
- halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, true);
- else
- halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- if (BTC_WIFI_BW_LEGACY == wifi_bw)
- {
- halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC, 0x5a5a5a5a, 0x5a5a5a5a, 0xffff, 0x3);
- }
- else
- {
- halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC, 0x5aea5aea, 0x5aea5aea, 0xffff, 0x3);
- }
-
- if(BTC_WIFI_BW_HT40 == wifi_bw)
- {
-
-
-
-
- if( (bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- }
- else
- {
- halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- }
-
-
- if( (wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist,true,true,false,false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist,true,false,false,0x18);
- }
- else
- {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist,true,true,false,false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist,false,false,false,0x18);
- }
- }
- else
- {
-
-
-
- if( (bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- }
- else
- {
- halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- }
-
-
- if( (wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist,false,true,false,false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist,true,false,false,0x18);
- }
- else
- {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist,false,true,false,false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist,false,false,false,0x18);
- }
- }
- */
-}
-
-
-void halbtc8821aCsr2ant_action_hid(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state, bt_rssi_state;
- u32 wifi_bw;
-
- wifi_rssi_state = halbtc8821aCsr2ant_wifi_rssi_state(btcoexist, 0, 2,
- 15, 0);
- bt_rssi_state = halbtc8821aCsr2ant_bt_rssi_state(2, 35, 0);
-
- halbtc8821aCsr2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
- if (halbtc8821aCsr2ant_need_to_dec_bt_pwr(btcoexist))
- halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, true);
- else
- halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- if (BTC_WIFI_BW_LEGACY == wifi_bw) /* for HID at 11b/g mode */
- halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC,
- 0x55ff55ff, 0x5a5a5a5a, 0xffff, 0x3);
- else /* for HID quality & wifi performance balance at 11n mode */
- halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC,
- 0x55ff55ff, 0x5aea5aea, 0xffff, 0x3);
-
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- /* fw mechanism */
- if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH))
- halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 9);
- else
- halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 13);
-
- /* sw mechanism */
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, true,
- false, false, 0x18);
- } else {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false,
- false, false, 0x18);
- }
- } else {
- /* fw mechanism */
- if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH))
- halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 9);
- else
- halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 13);
-
- /* sw mechanism */
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false,
- true, false, false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, true,
- false, false, 0x18);
- } else {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false,
- true, false, false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false,
- false, false, 0x18);
- }
- }
-}
-
-/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */
-void halbtc8821aCsr2ant_action_a2dp(IN struct btc_coexist *btcoexist)
-{
- halbtc8821aCsr2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true, 0x8);
-
- if (coex_sta->slave == false) {
- halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC,
- 0xfdfdfdfd, 0xdfdadfda, 0xffffff, 0x3);
- halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22);
- halbtc8821aCsr2ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0,
- 0, 1);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false, false, true,
- 0x0c);
- } else {
- halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC,
- 0xfdfdfdfd, 0xdfdadfda, 0xffffff, 0x3);
- halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 23);
- halbtc8821aCsr2ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0,
- 0, 2);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false, false, true,
- 0x18);
- }
-
- /*
- wifi_rssi_state = halbtc8821aCsr2ant_wifi_rssi_state(btcoexist, 0, 2, 15, 0);
- bt_rssi_state = halbtc8821aCsr2ant_bt_rssi_state(2, 35, 0);
-
-
-
-
-
- if(halbtc8821aCsr2ant_need_to_dec_bt_pwr(btcoexist))
- halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, true);
- else
- halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- if(BTC_WIFI_BW_HT40 == wifi_bw)
- {
-
- if( (bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8821aCsr2ant_tdma_duration_adjust(btcoexist, false, false, 1);
- }
- else
- {
- halbtc8821aCsr2ant_tdma_duration_adjust(btcoexist, false, true, 1);
- }
-
-
- if( (wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist,true,false,false,false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist,true,false,false,0x18);
- }
- else
- {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist,true,false,false,false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist,false,false,false,0x18);
- }
- }
- else
- {
-
- if( (bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8821aCsr2ant_tdma_duration_adjust(btcoexist, false, false, 1);
- }
- else
- {
- halbtc8821aCsr2ant_tdma_duration_adjust(btcoexist, false, true, 1);
- }
-
-
- if( (wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH) )
- {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist,false,false,false,false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist,true,false,false,0x18);
- }
- else
- {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist,false,false,false,false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist,false,false,false,0x18);
- }
- }
- */
-}
-
-void halbtc8821aCsr2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state, bt_rssi_state, bt_info_ext;
- u32 wifi_bw;
-
- bt_info_ext = coex_sta->bt_info_ext;
- wifi_rssi_state = halbtc8821aCsr2ant_wifi_rssi_state(btcoexist, 0, 2,
- 15, 0);
- bt_rssi_state = halbtc8821aCsr2ant_bt_rssi_state(2, 35, 0);
-
- /* fw dac swing is called in halbtc8821aCsr2ant_tdma_duration_adjust() */
- /* halbtc8821aCsr2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6); */
-
-
- if (halbtc8821aCsr2ant_need_to_dec_bt_pwr(btcoexist))
- halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, true);
- else
- halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- /* fw mechanism */
- if (bt_info_ext & BIT(0)) /* a2dp basic rate */
- halbtc8821aCsr2ant_tdma_duration_adjust(btcoexist,
- false, true, 2);
- else /* a2dp edr rate */
- halbtc8821aCsr2ant_tdma_duration_adjust(btcoexist,
- false, true, 1);
-
- /* sw mechanism */
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, true,
- false, false, false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, true,
- false, false, 0x18);
- } else {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, true,
- false, false, false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false,
- false, false, 0x18);
- }
- } else {
- /* fw mechanism */
- if (bt_info_ext & BIT(0)) /* a2dp basic rate */
- halbtc8821aCsr2ant_tdma_duration_adjust(btcoexist,
- false, true, 2);
- else /* a2dp edr rate */
- halbtc8821aCsr2ant_tdma_duration_adjust(btcoexist,
- false, true, 1);
-
- /* sw mechanism */
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false,
- false, false, false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, true,
- false, false, 0x18);
- } else {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false,
- false, false, false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false,
- false, false, 0x18);
- }
- }
-}
-
-void halbtc8821aCsr2ant_action_pan_edr(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state, bt_rssi_state;
- u32 wifi_bw;
-
- wifi_rssi_state = halbtc8821aCsr2ant_wifi_rssi_state(btcoexist, 0, 2,
- 15, 0);
- bt_rssi_state = halbtc8821aCsr2ant_bt_rssi_state(2, 35, 0);
-
- halbtc8821aCsr2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
- if (halbtc8821aCsr2ant_need_to_dec_bt_pwr(btcoexist))
- halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, true);
- else
- halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- if (BTC_WIFI_BW_LEGACY == wifi_bw) /* for HID at 11b/g mode */
- halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC,
- 0x55ff55ff, 0x5aff5aff, 0xffff, 0x3);
- else /* for HID quality & wifi performance balance at 11n mode */
- halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC,
- 0x55ff55ff, 0x5aff5aff, 0xffff, 0x3);
-
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- /* fw mechanism */
- if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH))
- halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 1);
- else
- halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 5);
-
- /* sw mechanism */
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, true,
- false, false, false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, true,
- false, false, 0x18);
- } else {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, true,
- false, false, false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false,
- false, false, 0x18);
- }
- } else {
- /* fw mechanism */
- if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH))
- halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 1);
- else
- halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 5);
-
- /* sw mechanism */
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false,
- false, false, false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, true,
- false, false, 0x18);
- } else {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false,
- false, false, false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false,
- false, false, 0x18);
- }
- }
-}
-
-
-/* PAN(HS) only */
-void halbtc8821aCsr2ant_action_pan_hs(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state, bt_rssi_state;
- u32 wifi_bw;
-
- wifi_rssi_state = halbtc8821aCsr2ant_wifi_rssi_state(btcoexist, 0, 2,
- 15, 0);
- bt_rssi_state = halbtc8821aCsr2ant_bt_rssi_state(2, 35, 0);
-
- halbtc8821aCsr2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- /* fw mechanism */
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH))
- halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC,
- true);
- else
- halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC,
- false);
- halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
-
- /* sw mechanism */
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, true,
- false, false, false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, true,
- false, false, 0x18);
- } else {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, true,
- false, false, false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false,
- false, false, 0x18);
- }
- } else {
- /* fw mechanism */
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH))
- halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC,
- true);
- else
- halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC,
- false);
-
- if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH))
- halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC,
- false, 1);
- else
- halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC,
- false, 1);
-
- /* sw mechanism */
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false,
- false, false, false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, true,
- false, false, 0x18);
- } else {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false,
- false, false, false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false,
- false, false, 0x18);
- }
- }
-}
-
-/* PAN(EDR)+A2DP */
-void halbtc8821aCsr2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state, bt_rssi_state, bt_info_ext;
- u32 wifi_bw;
-
- bt_info_ext = coex_sta->bt_info_ext;
- wifi_rssi_state = halbtc8821aCsr2ant_wifi_rssi_state(btcoexist, 0, 2,
- 15, 0);
- bt_rssi_state = halbtc8821aCsr2ant_bt_rssi_state(2, 35, 0);
-
- halbtc8821aCsr2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
- if (halbtc8821aCsr2ant_need_to_dec_bt_pwr(btcoexist))
- halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, true);
- else
- halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- if (BTC_WIFI_BW_LEGACY == wifi_bw) /* for HID at 11b/g mode */
- halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC,
- 0x55ff55ff, 0x5afa5afa, 0xffff, 0x3);
- else /* for HID quality & wifi performance balance at 11n mode */
- halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC,
- 0x55ff55ff, 0x5afa5afa, 0xffff, 0x3);
-
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- /* fw mechanism */
- if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- if (bt_info_ext & BIT(0)) /* a2dp basic rate */
- halbtc8821aCsr2ant_tdma_duration_adjust(
- btcoexist, false, false, 3);
- else /* a2dp edr rate */
- halbtc8821aCsr2ant_tdma_duration_adjust(
- btcoexist, false, false, 3);
- } else {
- if (bt_info_ext & BIT(0)) /* a2dp basic rate */
- halbtc8821aCsr2ant_tdma_duration_adjust(
- btcoexist, false, true, 3);
- else /* a2dp edr rate */
- halbtc8821aCsr2ant_tdma_duration_adjust(
- btcoexist, false, true, 3);
- }
-
- /* sw mechanism */
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, true,
- false, false, false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, true,
- false, false, 0x18);
- } else {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, true,
- false, false, false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false,
- false, false, 0x18);
- };
- } else {
- /* fw mechanism */
- if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- if (bt_info_ext & BIT(0)) /* a2dp basic rate */
- halbtc8821aCsr2ant_tdma_duration_adjust(
- btcoexist, false, false, 3);
- else /* a2dp edr rate */
- halbtc8821aCsr2ant_tdma_duration_adjust(
- btcoexist, false, false, 3);
- } else {
- if (bt_info_ext & BIT(0)) /* a2dp basic rate */
- halbtc8821aCsr2ant_tdma_duration_adjust(
- btcoexist, false, true, 3);
- else /* a2dp edr rate */
- halbtc8821aCsr2ant_tdma_duration_adjust(
- btcoexist, false, true, 3);
- }
-
- /* sw mechanism */
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false,
- false, false, false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, true,
- false, false, 0x18);
- } else {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false,
- false, false, false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false,
- false, false, 0x18);
- }
- }
-}
-
-void halbtc8821aCsr2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state, bt_rssi_state;
- u32 wifi_bw;
-
- wifi_rssi_state = halbtc8821aCsr2ant_wifi_rssi_state(btcoexist, 0, 2,
- 15, 0);
- bt_rssi_state = halbtc8821aCsr2ant_bt_rssi_state(2, 35, 0);
-
- halbtc8821aCsr2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
- if (halbtc8821aCsr2ant_need_to_dec_bt_pwr(btcoexist))
- halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, true);
- else
- halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- if (BTC_WIFI_BW_LEGACY == wifi_bw) /* for HID at 11b/g mode */
- halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC,
- 0x55ff55ff, 0x5a5f5a5f, 0xffff, 0x3);
- else /* for HID quality & wifi performance balance at 11n mode */
- halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC,
- 0x55ff55ff, 0x5a5f5a5f, 0xffff, 0x3);
-
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- halbtc8821aCsr2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 3);
- /* fw mechanism */
- if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH))
- halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 10);
- else
- halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 14);
-
- /* sw mechanism */
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, true,
- false, false, 0x18);
- } else {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false,
- false, false, 0x18);
- }
- } else {
- halbtc8821aCsr2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
- /* fw mechanism */
- if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH))
- halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 10);
- else
- halbtc8821aCsr2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 14);
-
- /* sw mechanism */
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false,
- true, false, false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, true,
- false, false, 0x18);
- } else {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false,
- true, false, false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false,
- false, false, 0x18);
- }
- }
-}
-
-/* HID+A2DP+PAN(EDR) */
-void halbtc8821aCsr2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist
- *btcoexist)
-{
- u8 wifi_rssi_state, bt_rssi_state, bt_info_ext;
- u32 wifi_bw;
-
- bt_info_ext = coex_sta->bt_info_ext;
- wifi_rssi_state = halbtc8821aCsr2ant_wifi_rssi_state(btcoexist, 0, 2,
- 15, 0);
- bt_rssi_state = halbtc8821aCsr2ant_bt_rssi_state(2, 35, 0);
-
- halbtc8821aCsr2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
-
- if (halbtc8821aCsr2ant_need_to_dec_bt_pwr(btcoexist))
- halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, true);
- else
- halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- if (BTC_WIFI_BW_LEGACY == wifi_bw) /* for HID at 11b/g mode */
- halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC,
- 0x55ff55ff, 0x5a5a5a5a, 0xffff, 0x3);
- else /* for HID quality & wifi performance balance at 11n mode */
- halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC,
- 0x55ff55ff, 0x5a5a5a5a, 0xffff, 0x3);
-
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- /* fw mechanism */
- if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- if (bt_info_ext & BIT(0)) /* a2dp basic rate */
- halbtc8821aCsr2ant_tdma_duration_adjust(
- btcoexist, true, true, 3);
- else /* a2dp edr rate */
- halbtc8821aCsr2ant_tdma_duration_adjust(
- btcoexist, true, true, 3);
- } else {
- if (bt_info_ext & BIT(0)) /* a2dp basic rate */
- halbtc8821aCsr2ant_tdma_duration_adjust(
- btcoexist, true, true, 3);
- else /* a2dp edr rate */
- halbtc8821aCsr2ant_tdma_duration_adjust(
- btcoexist, true, true, 3);
- }
-
- /* sw mechanism */
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, true,
- false, false, 0x18);
- } else {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false,
- false, false, 0x18);
- }
- } else {
- /* fw mechanism */
- if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- if (bt_info_ext & BIT(0)) /* a2dp basic rate */
- halbtc8821aCsr2ant_tdma_duration_adjust(
- btcoexist, true, false, 3);
- else /* a2dp edr rate */
- halbtc8821aCsr2ant_tdma_duration_adjust(
- btcoexist, true, false, 3);
- } else {
- if (bt_info_ext & BIT(0)) /* a2dp basic rate */
- halbtc8821aCsr2ant_tdma_duration_adjust(
- btcoexist, true, true, 3);
- else /* a2dp edr rate */
- halbtc8821aCsr2ant_tdma_duration_adjust(
- btcoexist, true, true, 3);
- }
-
- /* sw mechanism */
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false,
- true, false, false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, true,
- false, false, 0x18);
- } else {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false,
- true, false, false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false,
- false, false, 0x18);
- }
- }
-}
-
-void halbtc8821aCsr2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist)
-{
- u8 wifi_rssi_state, bt_rssi_state, bt_info_ext;
- u32 wifi_bw;
-
- bt_info_ext = coex_sta->bt_info_ext;
- wifi_rssi_state = halbtc8821aCsr2ant_wifi_rssi_state(btcoexist, 0, 2,
- 15, 0);
- bt_rssi_state = halbtc8821aCsr2ant_bt_rssi_state(2, 35, 0);
-
- if (halbtc8821aCsr2ant_need_to_dec_bt_pwr(btcoexist))
- halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, true);
- else
- halbtc8821aCsr2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- if (BTC_WIFI_BW_LEGACY == wifi_bw) { /* for HID at 11b/g mode */
- /* Allen halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC, 0x55ff55ff, 0x5a5a5a5a, 0xffff, 0x3); */
- halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC,
- 0x55ff55ff, 0x5f5b5f5b, 0xffffff, 0x3);
- } else { /* for HID quality & wifi performance balance at 11n mode */
- /* Allen halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC, 0x55ff55ff, 0x5a5a5a5a, 0xffff, 0x3); */
- halbtc8821aCsr2ant_coex_table(btcoexist, NORMAL_EXEC,
- 0x55ff55ff, 0x5f5b5f5b, 0xffffff, 0x3);
-
- }
-
- if (BTC_WIFI_BW_HT40 == wifi_bw) {
- /* fw mechanism */
- if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- if (bt_info_ext & BIT(0)) /* a2dp basic rate */
- halbtc8821aCsr2ant_tdma_duration_adjust(
- btcoexist, true, true, 2);
- else /* a2dp edr rate */
- halbtc8821aCsr2ant_tdma_duration_adjust(
- btcoexist, true, true, 2);
- } else {
- if (bt_info_ext & BIT(0)) /* a2dp basic rate */
- halbtc8821aCsr2ant_tdma_duration_adjust(
- btcoexist, true, true, 2);
- else /* a2dp edr rate */
- halbtc8821aCsr2ant_tdma_duration_adjust(
- btcoexist, true, true, 2);
- }
-
- /* sw mechanism */
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, true,
- false, false, 0x18);
- } else {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, true, true,
- false, false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false,
- false, false, 0x18);
- }
- } else {
- /* fw mechanism */
- if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- if (bt_info_ext & BIT(0)) { /* a2dp basic rate */
- /* halbtc8821aCsr2ant_tdma_duration_adjust(btcoexist, true, false, 2); */
- halbtc8821aCsr2ant_tdma_duration_adjust(
- btcoexist, true, true, 2);
-
- } else { /* a2dp edr rate */
- /* Allen halbtc8821aCsr2ant_tdma_duration_adjust(btcoexist, true, false, 2); */
- halbtc8821aCsr2ant_tdma_duration_adjust(
- btcoexist, true, true, 2);
- }
- } else {
- if (bt_info_ext & BIT(0)) /* a2dp basic rate */
- halbtc8821aCsr2ant_tdma_duration_adjust(
- btcoexist, true, true, 2);
- else /* a2dp edr rate */
- halbtc8821aCsr2ant_tdma_duration_adjust(
- btcoexist, true, true, 2);
- }
-
- /* sw mechanism */
- if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
- (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false,
- true, false, false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, true,
- false, false, 0x18);
- } else {
- halbtc8821aCsr2ant_sw_mechanism1(btcoexist, false,
- true, false, false);
- halbtc8821aCsr2ant_sw_mechanism2(btcoexist, false,
- false, false, 0x18);
- }
- }
-}
-
-void halbtc8821aCsr2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist)
-{
- boolean wifi_under_5g = false;
- u8 algorithm = 0;
-
- if (btcoexist->manual_control) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Manual control!!!\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
-
- if (wifi_under_5g) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism(), run 5G coex setting!!<===\n");
- BTC_TRACE(trace_buf);
- halbtc8821aCsr2ant_coex_under_5g(btcoexist);
- return;
- }
-
- {
- algorithm = halbtc8821aCsr2ant_action_algorithm(btcoexist);
- if (coex_sta->c2h_bt_inquiry_page &&
- (BT_8821A_CSR_2ANT_COEX_ALGO_PANHS != algorithm)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is under inquiry/page scan !!\n");
- BTC_TRACE(trace_buf);
- halbtc8821aCsr2ant_bt_inquiry_page(btcoexist);
- return;
- }
-
- coex_dm->cur_algorithm = algorithm;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Algorithm = %d\n", coex_dm->cur_algorithm);
- BTC_TRACE(trace_buf);
-
- if (halbtc8821aCsr2ant_is_common_action(btcoexist)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant common.\n");
- BTC_TRACE(trace_buf);
- coex_dm->reset_tdma_adjust = true;
- } else {
- if (coex_dm->cur_algorithm != coex_dm->pre_algorithm) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], pre_algorithm=%d, cur_algorithm=%d\n",
- coex_dm->pre_algorithm,
- coex_dm->cur_algorithm);
- BTC_TRACE(trace_buf);
- coex_dm->reset_tdma_adjust = true;
- }
- switch (coex_dm->cur_algorithm) {
- case BT_8821A_CSR_2ANT_COEX_ALGO_SCO:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = SCO.\n");
- BTC_TRACE(trace_buf);
- halbtc8821aCsr2ant_action_sco(
- btcoexist);
- break;
- case BT_8821A_CSR_2ANT_COEX_ALGO_HID:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = HID.\n");
- BTC_TRACE(trace_buf);
- halbtc8821aCsr2ant_action_hid(
- btcoexist);
- break;
- case BT_8821A_CSR_2ANT_COEX_ALGO_A2DP:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = A2DP.\n");
- BTC_TRACE(trace_buf);
- halbtc8821aCsr2ant_action_a2dp(
- btcoexist);
- break;
- case BT_8821A_CSR_2ANT_COEX_ALGO_A2DP_PANHS:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n");
- BTC_TRACE(trace_buf);
- halbtc8821aCsr2ant_action_a2dp_pan_hs(
- btcoexist);
- break;
- case BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n");
- BTC_TRACE(trace_buf);
- halbtc8821aCsr2ant_action_pan_edr(
- btcoexist);
- break;
- case BT_8821A_CSR_2ANT_COEX_ALGO_PANHS:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = HS mode.\n");
- BTC_TRACE(trace_buf);
- halbtc8821aCsr2ant_action_pan_hs(
- btcoexist);
- break;
- case BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_A2DP:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n");
- BTC_TRACE(trace_buf);
- halbtc8821aCsr2ant_action_pan_edr_a2dp(
- btcoexist);
- break;
- case BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_HID:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n");
- BTC_TRACE(trace_buf);
- halbtc8821aCsr2ant_action_pan_edr_hid(
- btcoexist);
- break;
- case BT_8821A_CSR_2ANT_COEX_ALGO_HID_A2DP_PANEDR
- :
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n");
- BTC_TRACE(trace_buf);
- halbtc8821aCsr2ant_action_hid_a2dp_pan_edr(
- btcoexist);
- break;
- case BT_8821A_CSR_2ANT_COEX_ALGO_HID_A2DP:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n");
- BTC_TRACE(trace_buf);
- halbtc8821aCsr2ant_action_hid_a2dp(
- btcoexist);
- break;
- default:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n");
- BTC_TRACE(trace_buf);
- halbtc8821aCsr2ant_coex_all_off(
- btcoexist);
- break;
- }
- coex_dm->pre_algorithm = coex_dm->cur_algorithm;
- }
- }
-}
-
-
-
-/* ************************************************************
- * work around function start with wa_halbtc8821aCsr2ant_
- * ************************************************************
- * ************************************************************
- * extern function start with ex_halbtc8821aCsr2ant_
- * ************************************************************ */
-void ex_halbtc8821aCsr2ant_power_on_setting(IN struct btc_coexist *btcoexist)
-{
-}
-
-void ex_halbtc8821aCsr2ant_init_hw_config(IN struct btc_coexist *btcoexist,
- IN boolean wifi_only)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], 2Ant Init HW Config!!\n");
- BTC_TRACE(trace_buf);
-
- if (wifi_only)
- return;
-
- /* if(back_up) */
- {
- /* backup rf 0x1e value */
- coex_dm->bt_rf_0x1e_backup = btcoexist->btc_get_rf_reg(
- btcoexist, BTC_RF_A, 0x1e, 0xfffff);
- coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist,
- 0x430);
- coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist,
- 0x434);
- coex_dm->backup_retry_limit = btcoexist->btc_read_2byte(
- btcoexist, 0x42a);
- coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte(
- btcoexist, 0x456);
- coex_dm->backup_ampdu_max_num = btcoexist->btc_read_2byte(
- btcoexist, 0x4ca);
- }
-
-#if 0 /* REMOVE */
- /* 0x790[5:0]=0x5 */
- u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790);
- u8tmp &= 0xc0;
- u8tmp |= 0x5;
- btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp);
-#endif
-
- /* Antenna config */
- halbtc8821aCsr2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, true,
- false);
-
- /* PTA parameter */
- halbtc8821aCsr2ant_coex_table(btcoexist, FORCE_EXEC, 0x55555555,
- 0x55555555, 0xffff, 0x3);
-
- /* Enable counter statistics */
- btcoexist->btc_write_1byte(btcoexist, 0x76e,
- 0xc); /* 0x76e[3] =1, WLAN_Act control by PTA */
- btcoexist->btc_write_1byte(btcoexist, 0x778, 0x3);
-
-#if 0 /* REMOVE */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1);
-#endif
-}
-
-void ex_halbtc8821aCsr2ant_init_coex_dm(IN struct btc_coexist *btcoexist)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Coex Mechanism Init!!\n");
- BTC_TRACE(trace_buf);
-
- halbtc8821aCsr2ant_init_coex_dm(btcoexist);
-}
-
-void ex_halbtc8821aCsr2ant_display_coex_info(IN struct btc_coexist *btcoexist)
-{
- struct btc_board_info *board_info = &btcoexist->board_info;
- struct btc_stack_info *stack_info = &btcoexist->stack_info;
- u8 *cli_buf = btcoexist->cli_buf;
- u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0;
- u32 u32tmp[4];
- u32 fw_ver = 0, bt_patch_ver = 0;
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ============[BT Coexist info]============");
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ",
- "Ant PG number/ Ant mechanism:",
- board_info->pg_ant_num, board_info->btdm_ant_num);
- CL_PRINTF(cli_buf);
-
- if (btcoexist->manual_control) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "[Action Manual control]!!");
- CL_PRINTF(cli_buf);
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %d_%d/ 0x%x/ 0x%x(%d)",
- "CoexVer/ FwVer/ PatchVer",
- glcoex_ver_date_8821a_csr_2ant, glcoex_ver_8821a_csr_2ant,
- fw_ver, bt_patch_ver, bt_patch_ver);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ",
- "Wifi channel informed to BT",
- coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
- coex_dm->wifi_chnl_info[2]);
- CL_PRINTF(cli_buf);
-
- /* wifi status */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Wifi Status]============");
- CL_PRINTF(cli_buf);
- btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[BT Status]============");
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ",
- "BT [status/ rssi/ retryCnt]",
- ((coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan") : ((
- BT_8821A_CSR_2ANT_BT_STATUS_IDLE == coex_dm->bt_status)
- ? "idle" : ((BT_8821A_CSR_2ANT_BT_STATUS_CONNECTED_IDLE
- == coex_dm->bt_status) ? "connected-idle" : "busy"))),
- coex_sta->bt_rssi, coex_sta->bt_retry_cnt);
- CL_PRINTF(cli_buf);
-
- if (stack_info->profile_notified) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %d / %d / %d / %d", "SCO/HID/PAN/A2DP",
- stack_info->sco_exist, stack_info->hid_exist,
- stack_info->pan_exist, stack_info->a2dp_exist);
- CL_PRINTF(cli_buf);
-
- btcoexist->btc_disp_dbg_msg(btcoexist,
- BTC_DBG_DISP_BT_LINK_INFO);
- }
-
- bt_info_ext = coex_sta->bt_info_ext;
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
- "BT Info A2DP rate",
- (bt_info_ext & BIT(0)) ? "Basic rate" : "EDR rate");
- CL_PRINTF(cli_buf);
-
- for (i = 0; i < BT_INFO_SRC_8821A_CSR_2ANT_MAX; i++) {
- if (coex_sta->bt_info_c2h_cnt[i]) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)",
- glbt_info_src_8821a_csr_2ant[i],
- coex_sta->bt_info_c2h[i][0],
- coex_sta->bt_info_c2h[i][1],
- coex_sta->bt_info_c2h[i][2],
- coex_sta->bt_info_c2h[i][3],
- coex_sta->bt_info_c2h[i][4],
- coex_sta->bt_info_c2h[i][5],
- coex_sta->bt_info_c2h[i][6],
- coex_sta->bt_info_c2h_cnt[i]);
- CL_PRINTF(cli_buf);
- }
- }
-
- /* Sw mechanism */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Sw mechanism]============");
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ",
- "SM1[ShRf/ LpRA/ LimDig]",
- coex_dm->cur_rf_rx_lpf_shrink, coex_dm->cur_low_penalty_ra,
- coex_dm->limited_dig);
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ",
- "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]",
- coex_dm->cur_agc_table_en, coex_dm->cur_adc_back_off,
- coex_dm->cur_dac_swing_on, coex_dm->cur_dac_swing_lvl);
- CL_PRINTF(cli_buf);
-
- /* Fw mechanism */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Fw mechanism]============");
- CL_PRINTF(cli_buf);
-
- if (!btcoexist->manual_control) {
- ps_tdma_case = coex_dm->cur_ps_tdma;
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %02x %02x %02x %02x %02x case-%d",
- "PS TDMA",
- coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],
- coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],
- coex_dm->ps_tdma_para[4], ps_tdma_case);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ",
- "DecBtPwr/ IgnWlanAct",
- coex_dm->cur_dec_bt_pwr, coex_dm->cur_ignore_wlan_act);
- CL_PRINTF(cli_buf);
- }
-
- /* Hw setting */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Hw setting]============");
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x",
- "RF-A, 0x1e initVal",
- coex_dm->bt_rf_0x1e_backup);
- CL_PRINTF(cli_buf);
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x6cc);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x ",
- "0x778 (W_Act)/ 0x6cc (CoTab Sel)",
- u8tmp[0], u8tmp[1]);
- CL_PRINTF(cli_buf);
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x8db);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xc5b);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
- "0x8db(ADC)/0xc5b[29:25](DAC)",
- ((u8tmp[0] & 0x60) >> 5), ((u8tmp[1] & 0x3e) >> 1));
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xcb4);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
- "0xcb4[7:0](ctrl)/ 0xcb4[29:28](val)",
- u32tmp[0] & 0xff, ((u32tmp[0] & 0x30000000) >> 28));
- CL_PRINTF(cli_buf);
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x40);
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x974);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
- "0x40/ 0x4c[24:23]/ 0x974",
- u8tmp[0], ((u32tmp[0] & 0x01800000) >> 23), u32tmp[1]);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
- "0x550(bcn ctrl)/0x522",
- u32tmp[0], u8tmp[0]);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xa0a);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
- "0xc50(DIG)/0xa0a(CCK-TH)",
- u32tmp[0], u8tmp[0]);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xf48);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xa5b);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xa5c);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
- "OFDM-FA/ CCK-FA",
- u32tmp[0], (u8tmp[0] << 8) + u8tmp[1]);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
- u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
- "0x6c0/0x6c4/0x6c8",
- u32tmp[0], u32tmp[1], u32tmp[2]);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
- "0x770 (hi-pri Rx/Tx)",
- coex_sta->high_priority_rx, coex_sta->high_priority_tx);
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
- "0x774(low-pri Rx/Tx)",
- coex_sta->low_priority_rx, coex_sta->low_priority_tx);
- CL_PRINTF(cli_buf);
-
- btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
-}
-
-
-void ex_halbtc8821aCsr2ant_ips_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- if (BTC_IPS_ENTER == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], IPS ENTER notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_ips = true;
- halbtc8821aCsr2ant_coex_all_off(btcoexist);
- } else if (BTC_IPS_LEAVE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], IPS LEAVE notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_ips = false;
- /* halbtc8821aCsr2ant_init_coex_dm(btcoexist); */
- }
-}
-
-void ex_halbtc8821aCsr2ant_lps_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- if (BTC_LPS_ENABLE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], LPS ENABLE notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_lps = true;
- } else if (BTC_LPS_DISABLE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], LPS DISABLE notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_lps = false;
- }
-}
-
-void ex_halbtc8821aCsr2ant_scan_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- if (BTC_SCAN_START == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCAN START notify\n");
- BTC_TRACE(trace_buf);
- } else if (BTC_SCAN_FINISH == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCAN FINISH notify\n");
- BTC_TRACE(trace_buf);
- }
-}
-
-void ex_halbtc8821aCsr2ant_connect_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- if (BTC_ASSOCIATE_START == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CONNECT START notify\n");
- BTC_TRACE(trace_buf);
- } else if (BTC_ASSOCIATE_FINISH == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CONNECT FINISH notify\n");
- BTC_TRACE(trace_buf);
- }
-}
-
-void ex_halbtc8821aCsr2ant_media_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- u8 h2c_parameter[3] = {0};
- u32 wifi_bw;
- u8 wifi_central_chnl;
-
- if (BTC_MEDIA_CONNECT == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], MEDIA connect notify\n");
- BTC_TRACE(trace_buf);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], MEDIA disconnect notify\n");
- BTC_TRACE(trace_buf);
- }
-
- /* only 2.4G we need to inform bt the chnl mask */
- btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
- &wifi_central_chnl);
- if ((BTC_MEDIA_CONNECT == type) &&
- (wifi_central_chnl <= 14)) {
- h2c_parameter[0] = 0x1;
- h2c_parameter[1] = wifi_central_chnl;
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- if (BTC_WIFI_BW_HT40 == wifi_bw)
- h2c_parameter[2] = 0x30;
- else
- h2c_parameter[2] = 0x20;
- }
-
-}
-
-void ex_halbtc8821aCsr2ant_specific_packet_notify(IN struct btc_coexist
- *btcoexist, IN u8 type)
-{
- if (type == BTC_PACKET_DHCP) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], DHCP Packet notify\n");
- BTC_TRACE(trace_buf);
- }
-}
-
-void ex_halbtc8821aCsr2ant_bt_info_notify(IN struct btc_coexist *btcoexist,
- IN u8 *tmp_buf, IN u8 length)
-{
- u8 bt_info = 0;
- u8 i, rsp_source = 0;
- boolean bt_busy = false, limited_dig = false;
- boolean wifi_connected = false, bt_hs_on = false,
- wifi_under_5g = false;
-
- coex_sta->c2h_bt_info_req_sent = false;
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
-
- rsp_source = tmp_buf[0] & 0xf;
- if (rsp_source >= BT_INFO_SRC_8821A_CSR_2ANT_MAX)
- rsp_source = BT_INFO_SRC_8821A_CSR_2ANT_WIFI_FW;
- coex_sta->bt_info_c2h_cnt[rsp_source]++;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source,
- length);
- BTC_TRACE(trace_buf);
- for (i = 0; i < length; i++) {
- coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
- if (i == 1)
- bt_info = tmp_buf[i];
- if (i == length - 1) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n",
- tmp_buf[i]);
- BTC_TRACE(trace_buf);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ",
- tmp_buf[i]);
- BTC_TRACE(trace_buf);
- }
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- if (BT_INFO_SRC_8821A_CSR_2ANT_WIFI_FW != rsp_source) {
- coex_sta->bt_retry_cnt = /* [3:0] */
- coex_sta->bt_info_c2h[rsp_source][2] & 0xf;
-
- coex_sta->bt_rssi =
- coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10;
-
- coex_sta->bt_info_ext =
- coex_sta->bt_info_c2h[rsp_source][4];
-
-#if 0 /* REMOVE */
- /* Here we need to resend some wifi info to BT */
- /* because bt is reset and loss of the info. */
- if ((coex_sta->bt_info_ext & BIT(1))) {
-
- if (wifi_connected)
- ex_halbtc8821aCsr2ant_media_status_notify(
- btcoexist, BTC_MEDIA_CONNECT);
- else
- ex_halbtc8821aCsr2ant_media_status_notify(
- btcoexist, BTC_MEDIA_DISCONNECT);
- }
-#endif
-
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
-
- if (bt_info ==
- BT_INFO_8821A_CSR_2ANT_B_CONNECTION) { /* connection exists but no busy */
- coex_sta->bt_link_exist = true;
- coex_dm->bt_status =
- BT_8821A_CSR_2ANT_BT_STATUS_CONNECTED_IDLE;
- } else if (bt_info &
- BT_INFO_8821A_CSR_2ANT_B_CONNECTION) { /* connection exists and some link is busy */
- coex_sta->bt_link_exist = true;
-
- if (bt_info & BT_INFO_8821A_CSR_2ANT_B_FTP)
- coex_sta->pan_exist = true;
- else
- coex_sta->pan_exist = false;
-
- if (bt_info & BT_INFO_8821A_CSR_2ANT_B_A2DP)
- coex_sta->a2dp_exist = true;
- else
- coex_sta->a2dp_exist = false;
-
- if (bt_info & BT_INFO_8821A_CSR_2ANT_B_HID)
- coex_sta->hid_exist = true;
- else
- coex_sta->hid_exist = false;
-
- if (bt_info & BT_INFO_8821A_CSR_2ANT_B_SCO_ESCO)
- coex_sta->sco_exist = true;
- else
- coex_sta->sco_exist = false;
-
- if (coex_sta->bt_info_ext & 0x80)
- coex_sta->slave = true; /* Slave */
- else
- coex_sta->slave = false; /* Master */
-
- coex_dm->bt_status =
- BT_8821A_CSR_2ANT_BT_STATUS_NON_IDLE;
- } else {
- coex_sta->bt_link_exist = false;
- coex_sta->pan_exist = false;
- coex_sta->a2dp_exist = false;
- coex_sta->slave = false;
- coex_sta->hid_exist = false;
- coex_sta->sco_exist = false;
- coex_dm->bt_status = BT_8821A_CSR_2ANT_BT_STATUS_IDLE;
- }
-
- if (bt_hs_on)
- coex_dm->bt_status =
- BT_8821A_CSR_2ANT_BT_STATUS_NON_IDLE;
-
- if (bt_info & BT_INFO_8821A_CSR_2ANT_B_INQ_PAGE) {
- coex_sta->c2h_bt_inquiry_page = true;
- coex_dm->bt_status = BT_8821A_CSR_2ANT_BT_STATUS_NON_IDLE;
- } else
- coex_sta->c2h_bt_inquiry_page = false;
-
-
- if (BT_8821A_CSR_2ANT_BT_STATUS_NON_IDLE == coex_dm->bt_status)
- bt_busy = true;
- else
- bt_busy = false;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
-
- if (BT_8821A_CSR_2ANT_BT_STATUS_IDLE != coex_dm->bt_status)
- limited_dig = true;
- else
- limited_dig = false;
- coex_dm->limited_dig = limited_dig;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_LIMITED_DIG, &limited_dig);
-
- halbtc8821aCsr2ant_run_coexist_mechanism(btcoexist);
-}
-
-void ex_halbtc8821aCsr2ant_halt_notify(IN struct btc_coexist *btcoexist)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n");
- BTC_TRACE(trace_buf);
-
- halbtc8821aCsr2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
- ex_halbtc8821aCsr2ant_media_status_notify(btcoexist,
- BTC_MEDIA_DISCONNECT);
-}
-
-void ex_halbtc8821aCsr2ant_pnp_notify(IN struct btc_coexist *btcoexist,
- IN u8 pnp_state)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n");
- BTC_TRACE(trace_buf);
-
- if (BTC_WIFI_PNP_SLEEP == pnp_state) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Pnp notify to SLEEP\n");
- BTC_TRACE(trace_buf);
- halbtc8821aCsr2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
-
- /* Sinda 20150819, workaround for driver skip leave IPS/LPS to speed up sleep time. */
- /* Driver do not leave IPS/LPS when driver is going to sleep, so BTCoexistence think wifi is still under IPS/LPS */
- /* BT should clear UnderIPS/UnderLPS state to avoid mismatch state after wakeup. */
- coex_sta->under_ips = false;
- coex_sta->under_lps = false;
- } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Pnp notify to WAKE UP\n");
- BTC_TRACE(trace_buf);
- }
-}
-
-void ex_halbtc8821aCsr2ant_periodical(IN struct btc_coexist *btcoexist)
-{
- halbtc8821aCsr2ant_monitor_bt_ctr(btcoexist);
- halbtc8821aCsr2ant_monitor_bt_enable_disable(btcoexist);
-}
-
-#endif
-
-#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */
\ No newline at end of file
diff --git a/hal/btc/HalBtc8821aCsr2Ant.h b/hal/btc/HalBtc8821aCsr2Ant.h
deleted file mode 100644
index 8d228fb..0000000
--- a/hal/btc/HalBtc8821aCsr2Ant.h
+++ /dev/null
@@ -1,188 +0,0 @@
-
-#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
-
-#if (RTL8821A_SUPPORT == 1)
-
-/* *******************************************
- * The following is for 8821A_CSR 2Ant BT Co-exist definition
- * ******************************************* */
-#define BT_INFO_8821A_CSR_2ANT_B_FTP BIT(7)
-#define BT_INFO_8821A_CSR_2ANT_B_A2DP BIT(6)
-#define BT_INFO_8821A_CSR_2ANT_B_HID BIT(5)
-#define BT_INFO_8821A_CSR_2ANT_B_SCO_BUSY BIT(4)
-#define BT_INFO_8821A_CSR_2ANT_B_ACL_BUSY BIT(3)
-#define BT_INFO_8821A_CSR_2ANT_B_INQ_PAGE BIT(2)
-#define BT_INFO_8821A_CSR_2ANT_B_SCO_ESCO BIT(1)
-#define BT_INFO_8821A_CSR_2ANT_B_CONNECTION BIT(0)
-
-#define BTC_RSSI_COEX_THRESH_TOL_8821A_CSR_2ANT 2
-
-enum bt_info_src_8821a_csr_2ant {
- BT_INFO_SRC_8821A_CSR_2ANT_WIFI_FW = 0x0,
- BT_INFO_SRC_8821A_CSR_2ANT_BT_RSP = 0x1,
- BT_INFO_SRC_8821A_CSR_2ANT_BT_ACTIVE_SEND = 0x2,
- BT_INFO_SRC_8821A_CSR_2ANT_MAX
-};
-
-enum bt_8821a_csr_2ant_bt_status {
- BT_8821A_CSR_2ANT_BT_STATUS_IDLE = 0x0,
- BT_8821A_CSR_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
- BT_8821A_CSR_2ANT_BT_STATUS_NON_IDLE = 0x2,
- BT_8821A_CSR_2ANT_BT_STATUS_MAX
-};
-
-enum bt_8821a_csr_2ant_coex_algo {
- BT_8821A_CSR_2ANT_COEX_ALGO_UNDEFINED = 0x0,
- BT_8821A_CSR_2ANT_COEX_ALGO_SCO = 0x1,
- BT_8821A_CSR_2ANT_COEX_ALGO_HID = 0x2,
- BT_8821A_CSR_2ANT_COEX_ALGO_A2DP = 0x3,
- BT_8821A_CSR_2ANT_COEX_ALGO_A2DP_PANHS = 0x4,
- BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR = 0x5,
- BT_8821A_CSR_2ANT_COEX_ALGO_PANHS = 0x6,
- BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
- BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_HID = 0x8,
- BT_8821A_CSR_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
- BT_8821A_CSR_2ANT_COEX_ALGO_HID_A2DP = 0xa,
- BT_8821A_CSR_2ANT_COEX_ALGO_MAX = 0xb,
-};
-
-struct coex_dm_8821a_csr_2ant {
- /* fw mechanism */
- boolean pre_dec_bt_pwr;
- boolean cur_dec_bt_pwr;
- u8 pre_fw_dac_swing_lvl;
- u8 cur_fw_dac_swing_lvl;
- boolean cur_ignore_wlan_act;
- boolean pre_ignore_wlan_act;
- u8 pre_ps_tdma;
- u8 cur_ps_tdma;
- u8 ps_tdma_para[6];
- u8 ps_tdma_du_adj_type;
- boolean reset_tdma_adjust;
- boolean pre_ps_tdma_on;
- boolean cur_ps_tdma_on;
- boolean pre_bt_auto_report;
- boolean cur_bt_auto_report;
-
- /* sw mechanism */
- boolean pre_rf_rx_lpf_shrink;
- boolean cur_rf_rx_lpf_shrink;
- u32 bt_rf_0x1e_backup;
- boolean pre_low_penalty_ra;
- boolean cur_low_penalty_ra;
- boolean pre_dac_swing_on;
- u32 pre_dac_swing_lvl;
- boolean cur_dac_swing_on;
- u32 cur_dac_swing_lvl;
- boolean pre_adc_back_off;
- boolean cur_adc_back_off;
- boolean pre_agc_table_en;
- boolean cur_agc_table_en;
- u32 pre_val0x6c0;
- u32 cur_val0x6c0;
- u32 pre_val0x6c4;
- u32 cur_val0x6c4;
- u32 pre_val0x6c8;
- u32 cur_val0x6c8;
- u8 pre_val0x6cc;
- u8 cur_val0x6cc;
- boolean limited_dig;
-
- u32 pre_ra_mask;
- u32 cur_ra_mask;
-
- u8 cur_ampdu_num_type;
- u8 pre_ampdu_num_type;
- u16 backup_ampdu_max_num;
-
- u8 cur_ampdu_time_type;
- u8 pre_ampdu_time_type;
- u8 backup_ampdu_max_time;
-
- u8 cur_arfr_type;
- u8 pre_arfr_type;
- u32 backup_arfr_cnt1;
- u32 backup_arfr_cnt2;
-
- u8 cur_retry_limit_type;
- u8 pre_retry_limit_type;
- u16 backup_retry_limit;
-
- /* algorithm related */
- u8 pre_algorithm;
- u8 cur_algorithm;
- u8 bt_status;
- u8 wifi_chnl_info[3];
-};
-
-struct coex_sta_8821a_csr_2ant {
- boolean bt_disabled;
- boolean bt_link_exist;
- boolean sco_exist;
- boolean a2dp_exist;
- boolean slave;
- boolean hid_exist;
- boolean pan_exist;
-
- boolean under_lps;
- boolean under_ips;
- u32 high_priority_tx;
- u32 high_priority_rx;
- u32 low_priority_tx;
- u32 low_priority_rx;
- u8 bt_rssi;
- u8 pre_bt_rssi_state;
- u8 pre_wifi_rssi_state[4];
- boolean c2h_bt_info_req_sent;
- u8 bt_info_c2h[BT_INFO_SRC_8821A_CSR_2ANT_MAX][10];
- u32 bt_info_c2h_cnt[BT_INFO_SRC_8821A_CSR_2ANT_MAX];
- boolean c2h_bt_inquiry_page;
- u8 bt_retry_cnt;
- u8 bt_info_ext;
-};
-
-/* *******************************************
- * The following is interface which will notify coex module.
- * ******************************************* */
-void ex_halbtc8821aCsr2ant_power_on_setting(IN struct btc_coexist *btcoexist);
-void ex_halbtc8821aCsr2ant_init_hw_config(IN struct btc_coexist *btcoexist,
- IN boolean wifi_only);
-void ex_halbtc8821aCsr2ant_init_coex_dm(IN struct btc_coexist *btcoexist);
-void ex_halbtc8821aCsr2ant_ips_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8821aCsr2ant_lps_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8821aCsr2ant_scan_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8821aCsr2ant_connect_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8821aCsr2ant_media_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8821aCsr2ant_specific_packet_notify(IN struct btc_coexist
- *btcoexist, IN u8 type);
-void ex_halbtc8821aCsr2ant_bt_info_notify(IN struct btc_coexist *btcoexist,
- IN u8 *tmp_buf, IN u8 length);
-void ex_halbtc8821aCsr2ant_halt_notify(IN struct btc_coexist *btcoexist);
-void ex_halbtc8821aCsr2ant_pnp_notify(IN struct btc_coexist *btcoexist,
- IN u8 pnp_state);
-void ex_halbtc8821aCsr2ant_periodical(IN struct btc_coexist *btcoexist);
-void ex_halbtc8821aCsr2ant_display_coex_info(IN struct btc_coexist *btcoexist);
-
-#else
-#define ex_halbtc8821aCsr2ant_power_on_setting(btcoexist)
-#define ex_halbtc8821aCsr2ant_init_hw_config(btcoexist, wifi_only)
-#define ex_halbtc8821aCsr2ant_init_coex_dm(btcoexist)
-#define ex_halbtc8821aCsr2ant_ips_notify(btcoexist, type)
-#define ex_halbtc8821aCsr2ant_lps_notify(btcoexist, type)
-#define ex_halbtc8821aCsr2ant_scan_notify(btcoexist, type)
-#define ex_halbtc8821aCsr2ant_connect_notify(btcoexist, type)
-#define ex_halbtc8821aCsr2ant_media_status_notify(btcoexist, type)
-#define ex_halbtc8821aCsr2ant_specific_packet_notify(btcoexist, type)
-#define ex_halbtc8821aCsr2ant_bt_info_notify(btcoexist, tmp_buf, length)
-#define ex_halbtc8821aCsr2ant_halt_notify(btcoexist)
-#define ex_halbtc8821aCsr2ant_pnp_notify(btcoexist, pnp_state)
-#define ex_halbtc8821aCsr2ant_periodical(btcoexist)
-#define ex_halbtc8821aCsr2ant_display_coex_info(btcoexist)
-#endif
-
-#endif
diff --git a/hal/btc/HalBtc8822b1Ant.c b/hal/btc/HalBtc8822b1Ant.c
deleted file mode 100644
index be0a2ac..0000000
--- a/hal/btc/HalBtc8822b1Ant.c
+++ /dev/null
@@ -1,6006 +0,0 @@
-/* ************************************************************
- * Description:
- *
- * This file is for RTL8822B Co-exist mechanism
- *
- * History
- * 2012/11/15 Cosa first check in.
- *
- * ************************************************************ */
-
-/* ************************************************************
- * include files
- * ************************************************************ */
-#include "Mp_Precomp.h"
-
-#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
-
-#if (RTL8822B_SUPPORT == 1)
-/* ************************************************************
- * Global variables, these are static variables
- * ************************************************************ */
-static u8 *trace_buf = &gl_btc_trace_buf[0];
-static struct coex_dm_8822b_1ant glcoex_dm_8822b_1ant;
-static struct coex_dm_8822b_1ant *coex_dm = &glcoex_dm_8822b_1ant;
-static struct coex_sta_8822b_1ant glcoex_sta_8822b_1ant;
-static struct coex_sta_8822b_1ant *coex_sta = &glcoex_sta_8822b_1ant;
-static struct psdscan_sta_8822b_1ant gl_psd_scan_8822b_1ant;
-static struct psdscan_sta_8822b_1ant *psd_scan = &gl_psd_scan_8822b_1ant;
-static struct rfe_type_8822b_1ant gl_rfe_type_8822b_1ant;
-static struct rfe_type_8822b_1ant *rfe_type = &gl_rfe_type_8822b_1ant;
-
-
-
-const char *const glbt_info_src_8822b_1ant[] = {
- "BT Info[wifi fw]",
- "BT Info[bt rsp]",
- "BT Info[bt auto report]",
-};
-
-u32 glcoex_ver_date_8822b_1ant = 20160411;
-u32 glcoex_ver_8822b_1ant = 0x14;
-
-/* ************************************************************
- * local function proto type if needed
- * ************************************************************
- * ************************************************************
- * local function start with halbtc8822b1ant_
- * ************************************************************ */
-u8 halbtc8822b1ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1)
-{
- s32 bt_rssi = 0;
- u8 bt_rssi_state = coex_sta->pre_bt_rssi_state;
-
- bt_rssi = coex_sta->bt_rssi;
-
- if (level_num == 2) {
- if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
- (coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (bt_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT))
- bt_rssi_state = BTC_RSSI_STATE_HIGH;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else {
- if (bt_rssi < rssi_thresh)
- bt_rssi_state = BTC_RSSI_STATE_LOW;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- } else if (level_num == 3) {
- if (rssi_thresh > rssi_thresh1) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Rssi thresh error!!\n");
- BTC_TRACE(trace_buf);
- return coex_sta->pre_bt_rssi_state;
- }
-
- if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
- (coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (bt_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT))
- bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else if ((coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_MEDIUM) ||
- (coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_STAY_MEDIUM)) {
- if (bt_rssi >= (rssi_thresh1 +
- BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT))
- bt_rssi_state = BTC_RSSI_STATE_HIGH;
- else if (bt_rssi < rssi_thresh)
- bt_rssi_state = BTC_RSSI_STATE_LOW;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
- } else {
- if (bt_rssi < rssi_thresh1)
- bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- }
-
- coex_sta->pre_bt_rssi_state = bt_rssi_state;
-
- return bt_rssi_state;
-}
-
-u8 halbtc8822b1ant_wifi_rssi_state(IN struct btc_coexist *btcoexist,
- IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1)
-{
- s32 wifi_rssi = 0;
- u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index];
-
- btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
-
- if (level_num == 2) {
- if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
- ||
- (coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (wifi_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT))
- wifi_rssi_state = BTC_RSSI_STATE_HIGH;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else {
- if (wifi_rssi < rssi_thresh)
- wifi_rssi_state = BTC_RSSI_STATE_LOW;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- } else if (level_num == 3) {
- if (rssi_thresh > rssi_thresh1) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], wifi RSSI thresh error!!\n");
- BTC_TRACE(trace_buf);
- return coex_sta->pre_wifi_rssi_state[index];
- }
-
- if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
- ||
- (coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (wifi_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT))
- wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else if ((coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_MEDIUM) ||
- (coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_STAY_MEDIUM)) {
- if (wifi_rssi >= (rssi_thresh1 +
- BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT))
- wifi_rssi_state = BTC_RSSI_STATE_HIGH;
- else if (wifi_rssi < rssi_thresh)
- wifi_rssi_state = BTC_RSSI_STATE_LOW;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
- } else {
- if (wifi_rssi < rssi_thresh1)
- wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- }
-
- coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state;
-
- return wifi_rssi_state;
-}
-
-void halbtc8822b1ant_update_ra_mask(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u32 dis_rate_mask)
-{
- coex_dm->cur_ra_mask = dis_rate_mask;
-
- if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask))
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK,
- &coex_dm->cur_ra_mask);
- coex_dm->pre_ra_mask = coex_dm->cur_ra_mask;
-}
-
-void halbtc8822b1ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- boolean wifi_under_b_mode = false;
-
- coex_dm->cur_arfr_type = type;
-
- if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) {
- switch (coex_dm->cur_arfr_type) {
- case 0: /* normal mode */
- btcoexist->btc_write_4byte(btcoexist, 0x430,
- coex_dm->backup_arfr_cnt1);
- btcoexist->btc_write_4byte(btcoexist, 0x434,
- coex_dm->backup_arfr_cnt2);
- break;
- case 1:
- btcoexist->btc_get(btcoexist,
- BTC_GET_BL_WIFI_UNDER_B_MODE,
- &wifi_under_b_mode);
- if (wifi_under_b_mode) {
- btcoexist->btc_write_4byte(btcoexist,
- 0x430, 0x0);
- btcoexist->btc_write_4byte(btcoexist,
- 0x434, 0x01010101);
- } else {
- btcoexist->btc_write_4byte(btcoexist,
- 0x430, 0x0);
- btcoexist->btc_write_4byte(btcoexist,
- 0x434, 0x04030201);
- }
- break;
- default:
- break;
- }
- }
-
- coex_dm->pre_arfr_type = coex_dm->cur_arfr_type;
-}
-
-void halbtc8822b1ant_retry_limit(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- coex_dm->cur_retry_limit_type = type;
-
- if (force_exec ||
- (coex_dm->pre_retry_limit_type !=
- coex_dm->cur_retry_limit_type)) {
- switch (coex_dm->cur_retry_limit_type) {
- case 0: /* normal mode */
- btcoexist->btc_write_2byte(btcoexist, 0x42a,
- coex_dm->backup_retry_limit);
- break;
- case 1: /* retry limit=8 */
- btcoexist->btc_write_2byte(btcoexist, 0x42a,
- 0x0808);
- break;
- default:
- break;
- }
- }
-
- coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type;
-}
-
-void halbtc8822b1ant_ampdu_max_time(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- coex_dm->cur_ampdu_time_type = type;
-
- if (force_exec ||
- (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) {
- switch (coex_dm->cur_ampdu_time_type) {
- case 0: /* normal mode */
- btcoexist->btc_write_1byte(btcoexist, 0x456,
- coex_dm->backup_ampdu_max_time);
- break;
- case 1: /* AMPDU timw = 0x38 * 32us */
- btcoexist->btc_write_1byte(btcoexist, 0x456,
- 0x38);
- break;
- default:
- break;
- }
- }
-
- coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type;
-}
-
-void halbtc8822b1ant_limited_tx(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type,
- IN u8 retry_limit_type, IN u8 ampdu_time_type)
-{
- switch (ra_mask_type) {
- case 0: /* normal mode */
- halbtc8822b1ant_update_ra_mask(btcoexist, force_exec,
- 0x0);
- break;
- case 1: /* disable cck 1/2 */
- halbtc8822b1ant_update_ra_mask(btcoexist, force_exec,
- 0x00000003);
- break;
- case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */
- halbtc8822b1ant_update_ra_mask(btcoexist, force_exec,
- 0x0001f1f7);
- break;
- default:
- break;
- }
-
- halbtc8822b1ant_auto_rate_fallback_retry(btcoexist, force_exec,
- arfr_type);
- halbtc8822b1ant_retry_limit(btcoexist, force_exec, retry_limit_type);
- halbtc8822b1ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type);
-}
-
-/*
-1: true / don't care / don't care
-max: false / false / don't care
-7: false / true / 7
-*/
-
-void halbtc8822b1ant_limited_rx(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean rej_ap_agg_pkt,
- IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size)
-{
- boolean reject_rx_agg = rej_ap_agg_pkt;
- boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size;
- u8 rx_agg_size = agg_buf_size;
-
- /* ============================================ */
- /* Rx Aggregation related setting */
- /* ============================================ */
- btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT,
- &reject_rx_agg);
- /* decide BT control aggregation buf size or not */
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE,
- &bt_ctrl_rx_agg_size);
- /* aggregation buf size, only work when BT control Rx aggregation size. */
- btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size);
- /* real update aggregation setting */
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
-
-
-}
-
-void halbtc8822b1ant_query_bt_info(IN struct btc_coexist *btcoexist)
-{
- u8 h2c_parameter[1] = {0};
-
- coex_sta->c2h_bt_info_req_sent = true;
-
- h2c_parameter[0] |= BIT(0); /* trigger */
-
- btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter);
-}
-
-void halbtc8822b1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist)
-{
- u32 reg_hp_txrx, reg_lp_txrx, u32tmp;
- u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
- static u8 num_of_bt_counter_chk = 0, cnt_slave = 0;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
- /* to avoid 0x76e[3] = 1 (WLAN_Act control by PTA) during IPS */
- /* if (! (btcoexist->btc_read_1byte(btcoexist, 0x76e) & 0x8) ) */
-
- if (coex_sta->under_ips) {
- /* coex_sta->high_priority_tx = 65535; */
- /* coex_sta->high_priority_rx = 65535; */
- /* coex_sta->low_priority_tx = 65535; */
- /* coex_sta->low_priority_rx = 65535; */
- /* return; */
- }
-
- reg_hp_txrx = 0x770;
- reg_lp_txrx = 0x774;
-
- u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
- reg_hp_tx = u32tmp & MASKLWORD;
- reg_hp_rx = (u32tmp & MASKHWORD) >> 16;
-
- u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
- reg_lp_tx = u32tmp & MASKLWORD;
- reg_lp_rx = (u32tmp & MASKHWORD) >> 16;
-
- coex_sta->high_priority_tx = reg_hp_tx;
- coex_sta->high_priority_rx = reg_hp_rx;
- coex_sta->low_priority_tx = reg_lp_tx;
- coex_sta->low_priority_rx = reg_lp_rx;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n",
- reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx);
- BTC_TRACE(trace_buf);
-
- /* reset counter */
- btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
-
- if ((coex_sta->low_priority_tx > 1150) &&
- (!coex_sta->c2h_bt_inquiry_page))
- coex_sta->pop_event_cnt++;
-
- if ((coex_sta->low_priority_rx >= 1150) && (coex_sta->low_priority_rx >= coex_sta->low_priority_tx)
- && (!coex_sta->under_ips) && (!coex_sta->c2h_bt_inquiry_page) && (coex_sta->bt_link_exist) ) {
- if (cnt_slave >= 3) {
- bt_link_info->slave_role = true;
- cnt_slave = 3;
- } else {
- cnt_slave ++;
- }
- } else {
- if(cnt_slave == 0) {
- bt_link_info->slave_role = false;
- cnt_slave = 0;
- } else{
- cnt_slave--;
- }
-
- }
-
- if ((coex_sta->high_priority_tx == 0) && (coex_sta->high_priority_rx == 0) && (coex_sta->low_priority_tx == 0) &&
- (coex_sta->low_priority_rx == 0)) {
- num_of_bt_counter_chk++;
-
- if (num_of_bt_counter_chk >= 3) {
- halbtc8822b1ant_query_bt_info(btcoexist);
- num_of_bt_counter_chk = 0;
- }
- }
-#if 0
- /* Add Hi-Pri Tx/Rx counter to avoid false detection */
- if (((coex_sta->hid_exist) || (coex_sta->sco_exist)) &&
- (coex_sta->high_priority_tx + coex_sta->high_priority_rx
- >= 160)
- && (!coex_sta->c2h_bt_inquiry_page))
- coex_sta->bt_hi_pri_link_exist = true;
- else
- coex_sta->bt_hi_pri_link_exist = false;
-
- if ((coex_sta->acl_busy) &&
- (coex_sta->num_of_profile == 0)) {
- if (coex_sta->low_priority_tx +
- coex_sta->low_priority_rx >= 160) {
- coex_sta->pan_exist = true;
- coex_sta->num_of_profile++;
- coex_sta->wrong_profile_notification++;
- }
- }
-#endif
-
-}
-
-
-void halbtc8822b1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist)
- {
- s32 wifi_rssi = 0;
- boolean wifi_busy = false, wifi_under_b_mode = false;
- static u8 cck_lock_counter = 0;
- u32 total_cnt;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,&wifi_under_b_mode);
-
- if (coex_sta->under_ips) {
- coex_sta->crc_ok_cck = 0;
- coex_sta->crc_ok_11g = 0;
- coex_sta->crc_ok_11n = 0;
- coex_sta->crc_ok_11n_agg = 0;
-
- coex_sta->crc_err_cck = 0;
- coex_sta->crc_err_11g = 0;
- coex_sta->crc_err_11n = 0;
- coex_sta->crc_err_11n_agg = 0;
- } else {
- coex_sta->crc_ok_cck = btcoexist->btc_read_2byte(btcoexist,
- 0xf04);
- coex_sta->crc_ok_11g = btcoexist->btc_read_2byte(btcoexist,
- 0xf14);
- coex_sta->crc_ok_11n = btcoexist->btc_read_2byte(btcoexist,
- 0xf10);
- coex_sta->crc_ok_11n_agg = btcoexist->btc_read_2byte(btcoexist,
- 0xf0c);
-
- coex_sta->crc_err_cck = btcoexist->btc_read_2byte(btcoexist,0xf00) + btcoexist->btc_read_2byte(btcoexist,0xf06);
-
- coex_sta->crc_err_11g = btcoexist->btc_read_2byte(btcoexist,
- 0xf16);
- coex_sta->crc_err_11n = btcoexist->btc_read_2byte(btcoexist,
- 0xf12);
- coex_sta->crc_err_11n_agg = btcoexist->btc_read_2byte(btcoexist,
- 0xf0e);
- }
-
-
- /* reset counter */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xb58, 0x1, 0x1);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xb58, 0x1, 0x0);
-
- if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) {
- total_cnt = coex_sta->crc_ok_cck + coex_sta->crc_ok_11g +
- coex_sta->crc_ok_11n +
- coex_sta->crc_ok_11n_agg;
-
- if ((coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_ACL_BUSY) ||
- (coex_dm->bt_status ==
- BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY) ||
- (coex_dm->bt_status ==
- BT_8822B_1ANT_BT_STATUS_SCO_BUSY)) {
- if (coex_sta->crc_ok_cck > (total_cnt -
- coex_sta->crc_ok_cck)) {
- if (cck_lock_counter < 3)
- cck_lock_counter++;
- } else {
- if (cck_lock_counter > 0)
- cck_lock_counter--;
- }
-
- } else {
- if (cck_lock_counter > 0)
- cck_lock_counter--;
- }
- } else {
- if (cck_lock_counter > 0)
- cck_lock_counter--;
- }
-
- if (!coex_sta->pre_ccklock) {
-
- if (cck_lock_counter >= 3)
- coex_sta->cck_lock = true;
- else
- coex_sta->cck_lock = false;
- } else {
- if (cck_lock_counter == 0)
- coex_sta->cck_lock = false;
- else
- coex_sta->cck_lock = true;
- }
-
- if (coex_sta->cck_lock)
- coex_sta->cck_ever_lock = true;
-
- coex_sta->pre_ccklock = coex_sta->cck_lock;
-
-
- }
-
-
-boolean halbtc8822b1ant_is_wifi_status_changed(IN struct btc_coexist *btcoexist)
-{
- static boolean pre_wifi_busy = false, pre_under_4way = false,
- pre_bt_hs_on = false, pre_bt_off = false;
- boolean wifi_busy = false, under_4way = false, bt_hs_on = false;
- boolean wifi_connected = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
- &under_4way);
- if (coex_sta->bt_disabled != pre_bt_off)
- {
- pre_bt_off = coex_sta->bt_disabled;
-
- if (coex_sta->bt_disabled)
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is disabled !!\n");
- else
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is enabled !!\n");
-
- BTC_TRACE(trace_buf);
-
- coex_sta->bt_coex_supported_feature = 0;
- coex_sta->bt_coex_supported_version = 0;
- return true;
- }
-
- if (wifi_connected) {
- if (wifi_busy != pre_wifi_busy) {
- pre_wifi_busy = wifi_busy;
- return true;
- }
- if (under_4way != pre_under_4way) {
- pre_under_4way = under_4way;
- return true;
- }
- if (bt_hs_on != pre_bt_hs_on) {
- pre_bt_hs_on = bt_hs_on;
- return true;
- }
- }
-
- return false;
-}
-
-void halbtc8822b1ant_update_bt_link_info(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean bt_hs_on = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
-
- bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
- bt_link_info->sco_exist = coex_sta->sco_exist;
- bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
- bt_link_info->pan_exist = coex_sta->pan_exist;
- bt_link_info->hid_exist = coex_sta->hid_exist;
- bt_link_info->bt_hi_pri_link_exist = coex_sta->bt_hi_pri_link_exist;
- bt_link_info->acl_busy = coex_sta->acl_busy;
-
- /* work around for HS mode. */
- if (bt_hs_on) {
- bt_link_info->pan_exist = true;
- bt_link_info->bt_link_exist = true;
- }
-
- /* check if Sco only */
- if (bt_link_info->sco_exist &&
- !bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist &&
- !bt_link_info->hid_exist)
- bt_link_info->sco_only = true;
- else
- bt_link_info->sco_only = false;
-
- /* check if A2dp only */
- if (!bt_link_info->sco_exist &&
- bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist &&
- !bt_link_info->hid_exist)
- bt_link_info->a2dp_only = true;
- else
- bt_link_info->a2dp_only = false;
-
- /* check if Pan only */
- if (!bt_link_info->sco_exist &&
- !bt_link_info->a2dp_exist &&
- bt_link_info->pan_exist &&
- !bt_link_info->hid_exist)
- bt_link_info->pan_only = true;
- else
- bt_link_info->pan_only = false;
-
- /* check if Hid only */
- if (!bt_link_info->sco_exist &&
- !bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist &&
- bt_link_info->hid_exist)
- bt_link_info->hid_only = true;
- else
- bt_link_info->hid_only = false;
-}
-
-void halbtc8822b1ant_update_wifi_channel_info(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- u8 h2c_parameter[3] = {0};
- u32 wifi_bw;
- u8 wifi_central_chnl;
-
- /* only 2.4G we need to inform bt the chnl mask */
- btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
- &wifi_central_chnl);
- if ((BTC_MEDIA_CONNECT == type) &&
- (wifi_central_chnl <= 14)) {
-
- h2c_parameter[0] = 0x1; /* enable BT AFH skip WL channel for 8822b because BT Rx LO interference */
- h2c_parameter[1] = wifi_central_chnl;
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- if (BTC_WIFI_BW_HT40 == wifi_bw)
- h2c_parameter[2] = 0x30;
- else
- h2c_parameter[2] = 0x20;
- }
-
- coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
- coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
- coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
-
- btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter);
-
-}
-
-u8 halbtc8822b1ant_action_algorithm(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean bt_hs_on = false;
- u8 algorithm = BT_8822B_1ANT_COEX_ALGO_UNDEFINED;
- u8 num_of_diff_profile = 0;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
-
- if (!bt_link_info->bt_link_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], No BT link exists!!!\n");
- BTC_TRACE(trace_buf);
- return algorithm;
- }
-
- if (bt_link_info->sco_exist)
- num_of_diff_profile++;
- if (bt_link_info->hid_exist)
- num_of_diff_profile++;
- if (bt_link_info->pan_exist)
- num_of_diff_profile++;
- if (bt_link_info->a2dp_exist)
- num_of_diff_profile++;
-
- if (num_of_diff_profile == 1) {
- if (bt_link_info->sco_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO only\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8822B_1ANT_COEX_ALGO_SCO;
- } else {
- if (bt_link_info->hid_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = HID only\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8822B_1ANT_COEX_ALGO_HID;
- } else if (bt_link_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = A2DP only\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8822B_1ANT_COEX_ALGO_A2DP;
- } else if (bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = PAN(HS) only\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8822B_1ANT_COEX_ALGO_PANHS;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = PAN(EDR) only\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8822B_1ANT_COEX_ALGO_PANEDR;
- }
- }
- }
- } else if (num_of_diff_profile == 2) {
- if (bt_link_info->sco_exist) {
- if (bt_link_info->hid_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + HID\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8822B_1ANT_COEX_ALGO_HID;
- } else if (bt_link_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + A2DP ==> SCO\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8822B_1ANT_COEX_ALGO_SCO;
- } else if (bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8822B_1ANT_COEX_ALGO_SCO;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8822B_1ANT_COEX_ALGO_PANEDR_HID;
- }
- }
- } else {
- if (bt_link_info->hid_exist &&
- bt_link_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = HID + A2DP\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8822B_1ANT_COEX_ALGO_HID_A2DP;
- } else if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = HID + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8822B_1ANT_COEX_ALGO_HID_A2DP;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = HID + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8822B_1ANT_COEX_ALGO_PANEDR_HID;
- }
- } else if (bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8822B_1ANT_COEX_ALGO_A2DP_PANHS;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = A2DP + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8822B_1ANT_COEX_ALGO_PANEDR_A2DP;
- }
- }
- }
- } else if (num_of_diff_profile == 3) {
- if (bt_link_info->sco_exist) {
- if (bt_link_info->hid_exist &&
- bt_link_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8822B_1ANT_COEX_ALGO_HID;
- } else if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + HID + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8822B_1ANT_COEX_ALGO_HID_A2DP;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8822B_1ANT_COEX_ALGO_PANEDR_HID;
- }
- } else if (bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8822B_1ANT_COEX_ALGO_SCO;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8822B_1ANT_COEX_ALGO_PANEDR_HID;
- }
- }
- } else {
- if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8822B_1ANT_COEX_ALGO_HID_A2DP;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8822B_1ANT_COEX_ALGO_HID_A2DP_PANEDR;
- }
- }
- }
- } else if (num_of_diff_profile >= 3) {
- if (bt_link_info->sco_exist) {
- if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
-
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8822B_1ANT_COEX_ALGO_PANEDR_HID;
- }
- }
- }
- }
-
- return algorithm;
-}
-
-void halbtc8822b1ant_set_bt_auto_report(IN struct btc_coexist *btcoexist,
- IN boolean enable_auto_report)
-{
- u8 h2c_parameter[1] = {0};
-
- h2c_parameter[0] = 0;
-
- if (enable_auto_report)
- h2c_parameter[0] |= BIT(0);
-
- btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter);
-}
-
-void halbtc8822b1ant_bt_auto_report(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean enable_auto_report)
-{
- coex_dm->cur_bt_auto_report = enable_auto_report;
-
- if (!force_exec) {
- if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report)
- return;
- }
- halbtc8822b1ant_set_bt_auto_report(btcoexist,
- coex_dm->cur_bt_auto_report);
-
- coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report;
-}
-
-void halbtc8822b1ant_set_sw_penalty_tx_rate_adaptive(IN struct btc_coexist
- *btcoexist, IN boolean low_penalty_ra)
-{
- u8 h2c_parameter[6] = {0};
-
- h2c_parameter[0] = 0x6; /* op_code, 0x6= Retry_Penalty */
-
- if (low_penalty_ra) {
- h2c_parameter[1] |= BIT(0);
- h2c_parameter[2] =
- 0x00; /* normal rate except MCS7/6/5, OFDM54/48/36 */
- h2c_parameter[3] = 0xf7; /* MCS7 or OFDM54 */
- h2c_parameter[4] = 0xf8; /* MCS6 or OFDM48 */
- h2c_parameter[5] = 0xf9; /* MCS5 or OFDM36 */
- }
-
- btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter);
-}
-
-void halbtc8822b1ant_low_penalty_ra(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean low_penalty_ra)
-{
- coex_dm->cur_low_penalty_ra = low_penalty_ra;
-
- if (!force_exec) {
- if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra)
- return;
- }
- halbtc8822b1ant_set_sw_penalty_tx_rate_adaptive(btcoexist,
- coex_dm->cur_low_penalty_ra);
-
- coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra;
-}
-
-void halbtc8822b1ant_write_score_board(
- IN struct btc_coexist *btcoexist,
- IN u16 bitpos,
- IN BOOLEAN state
-)
-{
-
- static u16 originalval = 0x8002;
-
- if (state)
- originalval = originalval | bitpos;
- else
- originalval = originalval & (~bitpos);
-
- btcoexist->btc_write_2byte(btcoexist, 0xaa, originalval);
-}
-
-void halbtc8822b1ant_read_score_board(
- IN struct btc_coexist *btcoexist,
- IN u16 *score_board_val
-)
-{
-
- *score_board_val = (btcoexist->btc_read_2byte(btcoexist,
- 0xaa)) & 0x7fff;
-}
-
-void halbtc8822b1ant_post_activestate_to_bt(
- IN struct btc_coexist *btcoexist,
- IN boolean wifi_active
-)
-{
-
- if (wifi_active)
- halbtc8822b1ant_write_score_board(btcoexist, (u16) BIT(0), TRUE);
- else
- halbtc8822b1ant_write_score_board(btcoexist, (u16) BIT(0), FALSE);
-}
-
-
-void halbtc8822b1ant_post_onoffstate_to_bt(
- IN struct btc_coexist *btcoexist,
- IN boolean wifi_on
-)
-{
-
- if (wifi_on)
- halbtc8822b1ant_write_score_board(btcoexist, (u16) BIT(1), TRUE);
- else
- halbtc8822b1ant_write_score_board(btcoexist, (u16) BIT(1), FALSE);
-}
-
-
-void halbtc8822b1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist)
-{
- static u32 bt_disable_cnt = 0;
- boolean bt_active = true, bt_disabled = false;
- u16 u16tmp;
-
- /* This function check if bt is disabled */
-#if 1
- if (coex_sta->high_priority_tx == 0 &&
- coex_sta->high_priority_rx == 0 &&
- coex_sta->low_priority_tx == 0 &&
- coex_sta->low_priority_rx == 0)
- bt_active = false;
- if (coex_sta->high_priority_tx == 0xffff &&
- coex_sta->high_priority_rx == 0xffff &&
- coex_sta->low_priority_tx == 0xffff &&
- coex_sta->low_priority_rx == 0xffff)
- bt_active = false;
-
-
-#else
-
- /* Read BT on/off status from scoreboard[1], enable this only if BT patch support this feature */
- halbtc8822b1ant_read_score_board(btcoexist, &u16tmp);
-
- bt_active = u16tmp & BIT(1);
-
-
-#endif
-
- if (bt_active) {
- bt_disable_cnt = 0;
- bt_disabled = false;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
- &bt_disabled);
- } else {
-
- bt_disable_cnt++;
- if (bt_disable_cnt >= 2) {
- bt_disabled = true;
- bt_disable_cnt = 2;
- }
-
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
- &bt_disabled);
- }
-
-
- if (coex_sta->bt_disabled != bt_disabled) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is from %s to %s!!\n",
- (coex_sta->bt_disabled ? "disabled" : "enabled"),
- (bt_disabled ? "disabled" : "enabled"));
- BTC_TRACE(trace_buf);
- coex_sta->bt_disabled = bt_disabled;
- }
-
-}
-
-
-
-void halbtc8822b1ant_enable_gnt_to_gpio(IN struct btc_coexist *btcoexist,
- boolean isenable)
-{
- static u8 bitVal[5] = {0,0,0,0,0};
- static boolean state = false;
-
- if (state ==isenable)
- return;
- else
- state = isenable;
-
- if (isenable) {
-
- /* enable GNT_WL, GNT_BT to GPIO for debug */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x1);
-
- /* store original value */
- bitVal[0] = (btcoexist->btc_read_1byte(btcoexist, 0x66) & BIT(4)) >>4; /*0x66[4] */
- bitVal[1] = (btcoexist->btc_read_1byte(btcoexist, 0x67) & BIT(0)); /*0x66[8] */
- bitVal[2] = (btcoexist->btc_read_1byte(btcoexist, 0x42) & BIT(3)) >> 3; /*0x40[19] */
- bitVal[3] = (btcoexist->btc_read_1byte(btcoexist, 0x65) & BIT(7)) >> 7; /*0x64[15] */
- bitVal[4] = (btcoexist->btc_read_1byte(btcoexist, 0x72) & BIT(2)) >> 2; /*0x70[18] */
-
- /* switch GPIO Mux */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, BIT(4), 0x0); /*0x66[4] = 0 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, BIT(0), 0x0); /*0x66[8] = 0 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, BIT(3), 0x0); /*0x40[19] = 0 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x65, BIT(7), 0x0); /*0x64[15] = 0 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x72, BIT(2), 0x0); /*0x70[18] = 0 */
-
-
- } else {
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x0);
-
- /* Restore original value */
- /* switch GPIO Mux */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, BIT(4), bitVal[0]); /*0x66[4] = 0 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, BIT(0), bitVal[1]); /*0x66[8] = 0 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, BIT(3), bitVal[2]); /*0x40[19] = 0 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x65, BIT(7), bitVal[3]); /*0x64[15] = 0 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x72, BIT(2), bitVal[4]); /*0x70[18] = 0 */
- }
-
-}
-
-
-u32 halbtc8822b1ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist,
- IN u16 reg_addr)
-{
- u32 j = 0;
-
-
- /* wait for ready bit before access 0x1700 */
- btcoexist->btc_write_4byte(btcoexist, 0x1700, 0x800F0000 | reg_addr);
-
- do {
- j++;
- } while (((btcoexist->btc_read_1byte(btcoexist,
- 0x1703) & BIT(5)) == 0) &&
- (j < BT_8822B_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT));
-
-
- return btcoexist->btc_read_4byte(btcoexist,
- 0x1708); /* get read data */
-
-}
-
-void halbtc8822b1ant_ltecoex_indirect_write_reg(IN struct btc_coexist *btcoexist,
- IN u16 reg_addr, IN u32 bit_mask, IN u32 reg_value)
-{
- u32 val, i = 0, j = 0, bitpos = 0;
-
-
- if (bit_mask == 0x0)
- return;
- if (bit_mask == 0xffffffff) {
- btcoexist->btc_write_4byte(btcoexist, 0x1704,
- reg_value); /* put write data */
-
- /* wait for ready bit before access 0x1700 */
- do {
- j++;
- } while (((btcoexist->btc_read_1byte(btcoexist,
- 0x1703) & BIT(5)) == 0) &&
- (j < BT_8822B_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT));
-
-
- btcoexist->btc_write_4byte(btcoexist, 0x1700,
- 0xc00F0000 | reg_addr);
- } else {
- for (i = 0; i <= 31; i++) {
- if (((bit_mask >> i) & 0x1) == 0x1) {
- bitpos = i;
- break;
- }
- }
-
- /* read back register value before write */
- val = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
- reg_addr);
- val = (val & (~bit_mask)) | (reg_value << bitpos);
-
- /* put write data value */
- btcoexist->btc_write_4byte(btcoexist, 0x1704,
- val); /* put write data */
-
- /* wait for ready bit before access 0x1700 */
- do {
- j++;
- } while (((btcoexist->btc_read_1byte(btcoexist,
- 0x1703) & BIT(5)) == 0) &&
- (j < BT_8822B_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT));
-
- /* write data add*/
-
- btcoexist->btc_write_4byte(btcoexist, 0x1700,
- 0xc00F0000 | reg_addr);
-
- }
-
-}
-
-void halbtc8822b1ant_ltecoex_enable(IN struct btc_coexist *btcoexist,
- IN boolean enable)
-{
- u8 val;
-
- val = (enable) ? 1 : 0;
- /* 0x38[7] */
- halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist, 0x38, 0x80,
- val); /* 0x38[7] */
-
-}
-
-
-void halbtc8822b1ant_ltecoex_pathcontrol_owner(IN struct btc_coexist *btcoexist,
- IN boolean wifi_control)
-{
- u8 val;
-
- val = (wifi_control) ? 1 : 0;
- /* 0x70[26] */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x4,
- val); /* 0x70[26] */
-
-}
-
-void halbtc8822b1ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist,
- IN u8 control_block, IN boolean sw_control, IN u8 state)
-{
- u32 val = 0, bit_mask;
-
- state = state & 0x1;
- /*LTE indirect 0x38=0xccxx (sw : gnt_wl=1,sw gnt_bt=1)
- 0x38=0xddxx (sw : gnt_bt=1 , sw gnt_wl=0)
- 0x38=0x55xx(hw pta :gnt_wl /gnt_bt ) */
- val = (sw_control) ? ((state << 1) | 0x1) : 0;
-
- switch (control_block) {
- case BT_8822B_1ANT_GNT_BLOCK_RFC_BB:
- default:
- bit_mask = 0xc000;
- halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist,
- 0x38, bit_mask, val); /* 0x38[15:14] */
- bit_mask = 0x0c00;
- halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist,
- 0x38, bit_mask, val); /* 0x38[11:10] */
- break;
- case BT_8822B_1ANT_GNT_BLOCK_RFC:
- bit_mask = 0xc000;
- halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist,
- 0x38, bit_mask, val); /* 0x38[15:14] */
- break;
- case BT_8822B_1ANT_GNT_BLOCK_BB:
- bit_mask = 0x0c00;
- halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist,
- 0x38, bit_mask, val); /* 0x38[11:10] */
- break;
-
- }
-
-}
-
-void halbtc8822b1ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist,
- IN u8 control_block, IN boolean sw_control, IN u8 state)
-{
- u32 val = 0, bit_mask;
- /*LTE indirect 0x38=0xccxx (sw : gnt_wl=1,sw gnt_bt=1)
- 0x38=0xddxx (sw : gnt_bt=1 , sw gnt_wl=0)
- 0x38=0x55xx(hw pta :gnt_wl /gnt_bt ) */
-
- state = state & 0x1;
- val = (sw_control) ? ((state << 1) | 0x1) : 0;
-
- switch (control_block) {
- case BT_8822B_1ANT_GNT_BLOCK_RFC_BB:
- default:
- bit_mask = 0x3000;
- halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist,
- 0x38, bit_mask, val); /* 0x38[13:12] */
- bit_mask = 0x0300;
- halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist,
- 0x38, bit_mask, val); /* 0x38[9:8] */
- break;
- case BT_8822B_1ANT_GNT_BLOCK_RFC:
- bit_mask = 0x3000;
- halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist,
- 0x38, bit_mask, val); /* 0x38[13:12] */
- break;
- case BT_8822B_1ANT_GNT_BLOCK_BB:
- bit_mask = 0x0300;
- halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist,
- 0x38, bit_mask, val); /* 0x38[9:8] */
- break;
-
- }
-
-}
-
-void halbtc8822b1ant_ltecoex_set_coex_table(IN struct btc_coexist *btcoexist,
- IN u8 table_type, IN u16 table_content)
-{
- u16 reg_addr = 0x0000;
-
- switch (table_type) {
- case BT_8822B_1ANT_CTT_WL_VS_LTE:
- reg_addr = 0xa0;
- break;
- case BT_8822B_1ANT_CTT_BT_VS_LTE:
- reg_addr = 0xa4;
- break;
- }
-
- if (reg_addr != 0x0000)
- halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist, reg_addr,
- 0xffff, table_content); /* 0xa0[15:0] or 0xa4[15:0] */
-
-
-}
-
-
-void halbtc8822b1ant_ltcoex_set_break_table(IN struct btc_coexist *btcoexist,
- IN u8 table_type, IN u8 table_content)
-{
- u16 reg_addr = 0x0000;
-
- switch (table_type) {
- case BT_8822B_1ANT_LBTT_WL_BREAK_LTE:
- reg_addr = 0xa8;
- break;
- case BT_8822B_1ANT_LBTT_BT_BREAK_LTE:
- reg_addr = 0xac;
- break;
- case BT_8822B_1ANT_LBTT_LTE_BREAK_WL:
- reg_addr = 0xb0;
- break;
- case BT_8822B_1ANT_LBTT_LTE_BREAK_BT:
- reg_addr = 0xb4;
- break;
- }
-
- if (reg_addr != 0x0000)
- halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist, reg_addr,
- 0xff, table_content); /* 0xa8[15:0] or 0xb4[15:0] */
-
-
-}
-
-void halbtc8822b1ant_set_coex_table(IN struct btc_coexist *btcoexist,
- IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc)
-{
- btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
-
- btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
-
- btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
-
- btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
-}
-
-void halbtc8822b1ant_coex_table(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4,
- IN u32 val0x6c8, IN u8 val0x6cc)
-{
- coex_dm->cur_val0x6c0 = val0x6c0;
- coex_dm->cur_val0x6c4 = val0x6c4;
- coex_dm->cur_val0x6c8 = val0x6c8;
- coex_dm->cur_val0x6cc = val0x6cc;
-
-
-
- if (!force_exec) {
- if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) &&
- (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) &&
- (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) &&
- (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc))
- return;
- }
- halbtc8822b1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8,
- val0x6cc);
-
- coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0;
- coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4;
- coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8;
- coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc;
-}
-
-void halbtc8822b1ant_coex_table_with_type(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- u32 break_table;
- u8 select_table;
-
-
-
- coex_sta->coex_table_type = type;
-
- if (coex_sta->concurrent_rx_mode_on == true) {
-
- break_table = 0xf0ffffff; /* set WL hi-pri can break BT */
- select_table =
- 0xb; /* set Tx response = Hi-Pri (ex: Transmitting ACK,BA,CTS) */
- } else {
-
- break_table = 0xffffff;
- select_table = 0x3;
- }
-
- switch (type) {
- case 0:
- halbtc8822b1ant_coex_table(btcoexist, force_exec,
- 0x55555555, 0x55555555, break_table,
- select_table);
- break;
- case 1:
- halbtc8822b1ant_coex_table(btcoexist, force_exec,
- 0x55555555, 0x5a5a5a5a, break_table,
- select_table);
- break;
- case 2:
- halbtc8822b1ant_coex_table(btcoexist, force_exec,
- 0xaa5a5a5a, 0xaa5a5a5a, break_table,
- select_table);
- break;
- case 3:
- halbtc8822b1ant_coex_table(btcoexist, force_exec,
- 0x55555555, 0xaa5a5a5a, break_table,
- select_table);
- break;
- case 4:
- halbtc8822b1ant_coex_table(btcoexist,
- force_exec, 0xaa555555, 0xaa5a5a5a,
- break_table, select_table);
- break;
- case 5:
- halbtc8822b1ant_coex_table(btcoexist,
- force_exec, 0x5a5a5a5a, 0x5a5a5a5a,
- break_table, select_table);
- break;
- case 6:
- halbtc8822b1ant_coex_table(btcoexist, force_exec,
- 0x55555555, 0xaaaaaaaa, break_table,
- select_table);
- break;
- case 7:
- halbtc8822b1ant_coex_table(btcoexist, force_exec,
- 0xaaaaaaaa, 0xaaaaaaaa, break_table,
- select_table);
- break;
- case 8:
- halbtc8822b1ant_coex_table(btcoexist, force_exec,
- 0xffffffff, 0xffffffff, break_table,
- select_table);
- break;
-
- default:
- break;
- }
-}
-
-void halbtc8822b1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist,
- IN boolean enable)
-{
-
-
- u8 h2c_parameter[1] = {0};
-
- if (enable) {
- h2c_parameter[0] |= BIT(0); /* function enable */
- }
-
- btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter);
-}
-
-void halbtc8822b1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean enable)
-{
-
- coex_dm->cur_ignore_wlan_act = enable;
-
- if (!force_exec) {
- if (coex_dm->pre_ignore_wlan_act ==
- coex_dm->cur_ignore_wlan_act)
- {
-
- coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
- return;
- }
- }
-
- halbtc8822b1ant_set_fw_ignore_wlan_act(btcoexist, enable);
-
- coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
-}
-
-void halbtc8822b1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist,
- IN u8 lps_val, IN u8 rpwm_val)
-{
- u8 lps = lps_val;
- u8 rpwm = rpwm_val;
-
- btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps);
- btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm);
-}
-
-void halbtc8822b1ant_lps_rpwm(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val)
-{
- coex_dm->cur_lps = lps_val;
- coex_dm->cur_rpwm = rpwm_val;
-
- if (!force_exec) {
- if ((coex_dm->pre_lps == coex_dm->cur_lps) &&
- (coex_dm->pre_rpwm == coex_dm->cur_rpwm))
- return;
- }
- halbtc8822b1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val);
-
- coex_dm->pre_lps = coex_dm->cur_lps;
- coex_dm->pre_rpwm = coex_dm->cur_rpwm;
-}
-
-void halbtc8822b1ant_ps_tdma_check_for_power_save_state(
- IN struct btc_coexist *btcoexist, IN boolean new_ps_state)
-{
- u8 lps_mode = 0x0;
- u8 h2c_parameter[5] = {0x8, 0, 0, 0, 0};
-
- btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode);
-
- if (lps_mode) { /* already under LPS state */
- if (new_ps_state) {
- /* keep state under LPS, do nothing. */
- } else {
- /* will leave LPS state, turn off psTdma first */
-
- btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
- }
- } else { /* NO PS state */
- if (new_ps_state) {
- /* will enter LPS state, turn off psTdma first */
-
- btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
- } else {
- /* keep state under NO PS state, do nothing. */
- }
- }
-}
-
-
-void halbtc8822b1ant_power_save_state(IN struct btc_coexist *btcoexist,
- IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val)
-{
- boolean low_pwr_disable = false;
-
- switch (ps_type) {
- case BTC_PS_WIFI_NATIVE:
- /* recover to original 32k low power setting */
- coex_sta->force_lps_on = false;
- low_pwr_disable = false;
- btcoexist->btc_set(btcoexist,
- BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS,
- NULL);
- coex_sta->force_lps_on = false;
- break;
- case BTC_PS_LPS_ON:
-
- coex_sta->force_lps_on = true;
- halbtc8822b1ant_ps_tdma_check_for_power_save_state(
- btcoexist, true);
- halbtc8822b1ant_lps_rpwm(btcoexist, NORMAL_EXEC,
- lps_val, rpwm_val);
- /* when coex force to enter LPS, do not enter 32k low power. */
- low_pwr_disable = true;
- btcoexist->btc_set(btcoexist,
- BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
- /* power save must executed before psTdma. */
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS,
- NULL);
- coex_sta->force_lps_on = true;
- break;
- case BTC_PS_LPS_OFF:
-
- coex_sta->force_lps_on = false;
- halbtc8822b1ant_ps_tdma_check_for_power_save_state(
- btcoexist, false);
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS,
- NULL);
- coex_sta->force_lps_on = false;
- break;
- default:
- break;
- }
-}
-
-
-void halbtc8822b1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist,
- IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5)
-{
- u8 h2c_parameter[5] = {0};
- u8 real_byte1 = byte1, real_byte5 = byte5;
- boolean ap_enable = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
- &ap_enable);
-
- if (ap_enable) {
- if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], FW for 1Ant AP mode\n");
- BTC_TRACE(trace_buf);
-
- real_byte1 &= ~BIT(4);
- real_byte1 |= BIT(5);
-
- real_byte5 |= BIT(5);
- real_byte5 &= ~BIT(6);
-
- halbtc8822b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
- }
- } else if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
-
- halbtc8822b1ant_power_save_state(btcoexist, BTC_PS_LPS_ON, 0x50,
- 0x4);
- } else {
- halbtc8822b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
- }
-
-
- h2c_parameter[0] = real_byte1;
- h2c_parameter[1] = byte2;
- h2c_parameter[2] = byte3;
- h2c_parameter[3] = byte4;
- h2c_parameter[4] = real_byte5;
-
- coex_dm->ps_tdma_para[0] = real_byte1;
- coex_dm->ps_tdma_para[1] = byte2;
- coex_dm->ps_tdma_para[2] = byte3;
- coex_dm->ps_tdma_para[3] = byte4;
- coex_dm->ps_tdma_para[4] = real_byte5;
-
- btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
-}
-
-void halbtc8822b1ant_ps_tdma(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean turn_on, IN u8 type)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_busy = false;
- static u8 psTdmaByte4Modify = 0x0, pre_psTdmaByte4Modify = 0x0;
- static boolean pre_wifi_busy = false;
-
- coex_dm->cur_ps_tdma_on = turn_on;
- coex_dm->cur_ps_tdma = type;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- if (wifi_busy != pre_wifi_busy) {
- force_exec = true;
- pre_wifi_busy = wifi_busy;
- }
-
- /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */
- if ((bt_link_info->slave_role) && (bt_link_info->a2dp_exist))
- psTdmaByte4Modify = 0x1;
- else
- psTdmaByte4Modify = 0x0;
-
- if (pre_psTdmaByte4Modify != psTdmaByte4Modify) {
-
- force_exec = true;
- pre_psTdmaByte4Modify = psTdmaByte4Modify;
- }
-
- if (coex_dm->cur_ps_tdma_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********TDMA(on, %d) **********\n",
- coex_dm->cur_ps_tdma);
- BTC_TRACE(trace_buf);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], **********TDMA(off, %d) **********\n",
- coex_dm->cur_ps_tdma);
- BTC_TRACE(trace_buf);
- }
-
- if (!force_exec) {
- if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) &&
- (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma))
- {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], return for no-TDMA case change\n");
- BTC_TRACE(trace_buf);
-
- return;
- }
- }
-
-
- if (turn_on) {
-
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8,
- 0x1); /* enable TBTT nterrupt */
-
- switch (type) {
- default:
- halbtc8822b1ant_set_fw_pstdma(btcoexist,
- 0x51,0x1a, 0x1a, 0x0, 0x10);
- break;
- case 1:
- halbtc8822b1ant_set_fw_pstdma(btcoexist,
- 0x61, 0x3a,0x03,0x11, 0x10);
- break;
- case 3:
- halbtc8822b1ant_set_fw_pstdma(btcoexist,
- 0x51, 0x3a, 0x03, 0x10, 0x10);
- break;
- case 4:
- halbtc8822b1ant_set_fw_pstdma(btcoexist,
- 0x51, 0x21, 0x03, 0x10, 0x10);
- break;
- case 5:
- halbtc8822b1ant_set_fw_pstdma(btcoexist,
- 0x61, 0x15, 0x3,0x11, 0x11);
- break;
- case 7:
- halbtc8822b1ant_set_fw_pstdma(btcoexist,
- 0x61, 0x10, 0x03, 0x10, 0x14 | psTdmaByte4Modify);
- break;
- case 8:
- halbtc8822b1ant_set_fw_pstdma(btcoexist,
- 0x51, 0x10, 0x03, 0x10, 0x14 | psTdmaByte4Modify);
- break;
- case 13:
- halbtc8822b1ant_set_fw_pstdma(btcoexist,
- 0x51, 0x25, 0x03, 0x10, 0x10 | psTdmaByte4Modify);
- break;
- case 14:
- halbtc8822b1ant_set_fw_pstdma(btcoexist,
- 0x51, 0x15, 0x03, 0x10, 0x10 | psTdmaByte4Modify);
- break;
- case 15:
- halbtc8822b1ant_set_fw_pstdma(btcoexist,
- 0x51, 0x20, 0x03, 0x10, 0x10 | psTdmaByte4Modify);
- break;
- case 17:
- halbtc8822b1ant_set_fw_pstdma(btcoexist,
- 0x61, 0x10, 0x03, 0x11, 0x14 | psTdmaByte4Modify);
- break;;
-
- case 20:
- halbtc8822b1ant_set_fw_pstdma(btcoexist,
- 0x61, 0x30, 0x03,0x11, 0x10);
- break;
- case 22:
- halbtc8822b1ant_set_fw_pstdma(btcoexist,
- 0x61, 0x25, 0x03,0x11, 0x10);
- break;
- case 32:
- halbtc8822b1ant_set_fw_pstdma(btcoexist,
- 0x61, 0x35, 0x3,0x11, 0x11);
- break;
- case 41:/*HID*/
- halbtc8822b1ant_set_fw_pstdma(btcoexist,
- 0x51,0x45, 0x3, 0x11, 0x11);
- break;
- case 42:/*A2DP*/
- halbtc8822b1ant_set_fw_pstdma(btcoexist,
- 0x51,0x1e, 0x3, 0x10, 0x14| psTdmaByte4Modify);
- break;
- case 43:/*A2DP+HID*/
- halbtc8822b1ant_set_fw_pstdma(btcoexist,
- 0x51,0x45, 0x3, 0x10, 0x14);
- break;
- case 44:/*A2DP+OPP old */
- halbtc8822b1ant_set_fw_pstdma(btcoexist,
- 0x51,0x25, 0x3, 0x10, 0x10);
- break;
- case 45:/*OPP new -> WIFI FW check the ncuu_p ack of AP , if has no null_p ack , wifi fw will extened wifi slot */
- halbtc8822b1ant_set_fw_pstdma(btcoexist,
- 0x51,0x3a, 0x3, 0x10, 0x10);
- break;
- case 46:/*A2DP+OPP new-> WIFI FW check the ncuu_p ack of AP , if has no null_p ack , wifi fw will extened wifi slot*/
- halbtc8822b1ant_set_fw_pstdma(btcoexist,
- 0x51,0x1a, 0x3, 0x10, 0x10);
- break;
-
- }
- } else {
-
- switch (type) {
- case 0:
- default: /* Software control, Antenna at BT side */
- halbtc8822b1ant_set_fw_pstdma(btcoexist,
- 0x0,0x0, 0x0, 0x0, 0x0);
- /*
- halbtc8822b1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_BT, FORCE_EXEC, false,
- false); */
- break;
- case 8: /* PTA Control */
- halbtc8822b1ant_set_fw_pstdma(btcoexist,
- 0x8,0x0, 0x0, 0x0, 0x0);
- /*
- halbtc8822b1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_PTA, FORCE_EXEC, false,
- false); */
- break;
- case 9: /* Software control, Antenna at WiFi side */
- halbtc8822b1ant_set_fw_pstdma(btcoexist,
- 0x0,0x0, 0x0, 0x0, 0x0);
- /*
- halbtc8822b1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_WIFI, FORCE_EXEC,false,false); */
- break;
- case 10: /* under 5G , 0x778=1*/
- halbtc8822b1ant_set_fw_pstdma(btcoexist,
- 0x0,0x0, 0x0, 0x0, 0x0);
-
- /*
- halbtc8822b1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_WIFI5G, FORCE_EXEC, false,
- false); */
-
- break;
- }
- }
-
-
- /* update pre state */
- coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on;
- coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
-}
-
-
-void halbtc8822b1ant_sw_mechanism(IN struct btc_coexist *btcoexist,
- IN boolean low_penalty_ra)
-{
- halbtc8822b1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra);
-}
-
-void halbtc8822b1ant_set_rfe_type(IN struct btc_coexist *btcoexist)
-{
- struct btc_board_info *board_info = &btcoexist->board_info;
-
-
- /* the following setup should be got from Efuse in the future */
- rfe_type->rfe_module_type = board_info->rfe_type;
-
- rfe_type->ext_ant_switch_ctrl_polarity = 0;;
-
- switch(rfe_type->rfe_module_type)
- {
- case 0:
- default:
- rfe_type->ext_ant_switch_exist = true;
- rfe_type->ext_ant_switch_type = BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT;
- break;
- case 1:
- rfe_type->ext_ant_switch_exist = true;
- rfe_type->ext_ant_switch_type = BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT;
- break;
- case 2:
- rfe_type->ext_ant_switch_exist = true;
- rfe_type->ext_ant_switch_type = BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT;
- break;
- case 3:
- rfe_type->ext_ant_switch_exist = true;
- rfe_type->ext_ant_switch_type = BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT;
- break;
- case 4:
- rfe_type->ext_ant_switch_exist = true;
- rfe_type->ext_ant_switch_type = BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SP3T; /* SP3T */;
- break;
- }
-
-
-}
-
-
-void halbtc8822b1ant_set_ext_ant_switch(IN struct btc_coexist *btcoexist, IN boolean force_exec, IN u8 ctrl_type, IN u8 pos_type)
-{
- struct btc_board_info *board_info = &btcoexist->board_info;
- boolean switch_polatiry_inverse = false;
- u8 regval_0xcbd = 0, regval_0x64;
- u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0;
-
- if (!rfe_type->ext_ant_switch_exist)
- return;
-
- coex_dm->cur_ext_ant_switch_status = (ctrl_type << 8) + pos_type;
-
- if (!force_exec) {
- if (coex_dm->pre_ext_ant_switch_status == coex_dm->cur_ext_ant_switch_status)
- return;
- }
-
- coex_dm->pre_ext_ant_switch_status = coex_dm->cur_ext_ant_switch_status;
-
- /* swap control polarity if use different switch control polarity*/
- /* Normal switch polarity for SPDT, 0xcbd[1:0] = 2b'01 => Ant to BTG, 0xcbd[1:0] = 2b'10 => Ant to WLG */
- switch_polatiry_inverse = (rfe_type->ext_ant_switch_ctrl_polarity == 1? ~switch_polatiry_inverse: switch_polatiry_inverse);
-
-
- switch(pos_type)
- {
- default:
- case BT_8822B_1ANT_EXT_ANT_SWITCH_TO_BT:
- case BT_8822B_1ANT_EXT_ANT_SWITCH_TO_NOCARE:
-
- break;
- case BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLG:
- switch_polatiry_inverse = ~switch_polatiry_inverse;
- break;
- case BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLA:
- break;
- }
-
-
- if (rfe_type->ext_ant_switch_type == BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT)
- {
- switch(ctrl_type)
- {
- default:
- case BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW:
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x80, 0x0); /* 0x4c[23] = 0 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, 0x01, 0x1); /* 0x4c[24] = 1 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, 0xff, 0x77); /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as cotrol pin */
-
- regval_0xcbd = (switch_polatiry_inverse == false? 0x1 : 0x2); /* 0xcbd[1:0] = 2b'01 for no switch_polatiry_inverse, ANTSWB =1, ANTSW =0 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x3, regval_0xcbd);
-
- break;
- case BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_PTA:
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x80, 0x0); /* 0x4c[23] = 0 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, 0x01, 0x1); /* 0x4c[24] = 1 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, 0xff, 0x66); /* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as cotrol pin */
-
- regval_0xcbd = (switch_polatiry_inverse == false? 0x2 : 0x1); /* 0xcbd[1:0] = 2b'10 for no switch_polatiry_inverse, ANTSWB =1, ANTSW =0 @ GNT_BT=1 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x3, regval_0xcbd);
-
- break;
- case BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV:
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x80, 0x0); /* 0x4c[23] = 0 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, 0x01, 0x1); /* 0x4c[24] = 1 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, 0xff, 0x88); /* */
-
- /* no regval_0xcbd setup required, because antenna switch control value by antenna diversity */
-
- break;
- case BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_MAC:
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x80, 0x1); /* 0x4c[23] = 1 */
-
- regval_0x64 = (switch_polatiry_inverse == false? 0x0 : 0x1); /* 0x64[0] = 1b'0 for no switch_polatiry_inverse, DPDT_SEL_N =1, DPDT_SEL_P =0 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x64, 0x1, regval_0x64);
- break;
- case BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BT:
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x80, 0x0); /* 0x4c[23] = 0 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, 0x01, 0x0); /* 0x4c[24] = 0 */
-
- /* no setup required, because antenna switch control value by BT vendor 0xac[1:0] */
- break;
- }
- }
-
- u32tmp1 = btcoexist->btc_read_4byte(btcoexist, 0xcbd);
- u32tmp2 = btcoexist->btc_read_4byte(btcoexist, 0x4c);
- u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0x64) & 0xff;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (After Ext Ant switch setup) 0xcbd = 0x%08x, 0x4c = 0x%08x, 0x64= 0x%02x**********\n",
- u32tmp1, u32tmp2, u32tmp3);
- BTC_TRACE(trace_buf);
-
-
-}
-
-
-void halbtc8822b1ant_set_ant_path(IN struct btc_coexist *btcoexist,
- IN u8 ant_pos_type, IN boolean force_exec,
- IN u8 phase)
-
-{
- struct btc_board_info *board_info = &btcoexist->board_info;
- u8 u8tmp = 0;
- u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0;
-
- coex_dm->cur_ant_pos_type = (ant_pos_type << 8) + phase;
-
- if (!force_exec) {
- if (coex_dm->cur_ant_pos_type == coex_dm->pre_ant_pos_type)
- return;
- }
-
- coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type;
-
-#if 1
- u32tmp1 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
- 0x38);
- u32tmp2 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
- 0x54);
- u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4);
-
- u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (Before Ant Setup) 0xcb4 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n",
- u32tmp3, u8tmp, u32tmp1, u32tmp2);
- BTC_TRACE(trace_buf);
-#endif
-
- switch (phase)
- {
- case BT_8822B_1ANT_PHASE_COEX_INIT:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (set_ant_path - 1ANT_PHASE_COEX_INIT) **********\n" );
- BTC_TRACE(trace_buf);
-
- /* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */
- halbtc8822b1ant_ltecoex_enable(btcoexist, 0x0);
-
- /* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */
- halbtc8822b1ant_ltecoex_set_coex_table(btcoexist,
- BT_8822B_1ANT_CTT_WL_VS_LTE, 0xffff);
-
- /* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */
- halbtc8822b1ant_ltecoex_set_coex_table(btcoexist,
- BT_8822B_1ANT_CTT_BT_VS_LTE, 0xffff);
-
- /* set GNT_BT to SW high */
- halbtc8822b1ant_ltecoex_set_gnt_bt(btcoexist,
- BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_1ANT_GNT_CTRL_BY_SW,
- BT_8822B_1ANT_SIG_STA_SET_TO_HIGH);
-
- /* set GNT_WL to SW low */
- halbtc8822b1ant_ltecoex_set_gnt_wl(btcoexist,
- BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_1ANT_GNT_CTRL_BY_SW,
- BT_8822B_1ANT_SIG_STA_SET_TO_LOW);
-
- /* set Path control owner to WL at initial step */
- halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist,
- BT_8822B_1ANT_PCO_WLSIDE);
-
- coex_sta->run_time_state = false;
-
- /* Ext switch buffer mux */
- btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, 0x3, 0x0);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, 0x8, 0x0);
-
- if (BTC_ANT_PATH_AUTO == ant_pos_type)
- ant_pos_type = BTC_ANT_PATH_BT;
-
- break;
- case BT_8822B_1ANT_PHASE_WLANONLY_INIT:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (set_ant_path - 1ANT_PHASE_WLANONLY_INIT) **********\n" );
- BTC_TRACE(trace_buf);
-
- /* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */
- halbtc8822b1ant_ltecoex_enable(btcoexist, 0x0);
-
- /* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */
- halbtc8822b1ant_ltecoex_set_coex_table(btcoexist,
- BT_8822B_1ANT_CTT_WL_VS_LTE, 0xffff);
-
- /* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */
- halbtc8822b1ant_ltecoex_set_coex_table(btcoexist,
- BT_8822B_1ANT_CTT_BT_VS_LTE, 0xffff);
-
- /* set GNT_BT to SW Low */
- halbtc8822b1ant_ltecoex_set_gnt_bt(btcoexist,
- BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_1ANT_GNT_CTRL_BY_SW,
- BT_8822B_1ANT_SIG_STA_SET_TO_LOW);
-
- /* Set GNT_WL to SW high */
- halbtc8822b1ant_ltecoex_set_gnt_wl(btcoexist,
- BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_1ANT_GNT_CTRL_BY_SW,
- BT_8822B_1ANT_SIG_STA_SET_TO_HIGH);
-
- /* set Path control owner to WL at initial step */
- halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist,
- BT_8822B_1ANT_PCO_WLSIDE);
-
- coex_sta->run_time_state = false;
-
- /* Ext switch buffer mux */
- btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, 0x3, 0x0);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, 0x8, 0x0);
-
- if (BTC_ANT_PATH_AUTO == ant_pos_type)
- ant_pos_type = BTC_ANT_PATH_WIFI;
-
- break;
- case BT_8822B_1ANT_PHASE_WLAN_OFF:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (set_ant_path - 1ANT_PHASE_WLAN_OFF) **********\n" );
- BTC_TRACE(trace_buf);
-
- /* Disable LTE Coex Function in WiFi side */
- halbtc8822b1ant_ltecoex_enable(btcoexist, 0x0);
-
- /* set Path control owner to BT */
- halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist,
- BT_8822B_1ANT_PCO_BTSIDE);
-
- /* Set Ext Ant Switch to BT control at wifi off step */
- halbtc8822b1ant_set_ext_ant_switch(btcoexist,
- FORCE_EXEC,
- BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BT,
- BT_8822B_1ANT_EXT_ANT_SWITCH_TO_NOCARE);
-
- coex_sta->run_time_state = false;
-
- break;
- case BT_8822B_1ANT_PHASE_2G_RUNTIME:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (set_ant_path - 1ANT_PHASE_2G_RUNTIME) **********\n" );
- BTC_TRACE(trace_buf);
-
- /* set GNT_BT to PTA */
- halbtc8822b1ant_ltecoex_set_gnt_bt(btcoexist,
- BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_1ANT_GNT_CTRL_BY_PTA,
- BT_8822B_1ANT_SIG_STA_SET_BY_HW);
-
- /* Set GNT_WL to PTA */
- halbtc8822b1ant_ltecoex_set_gnt_wl(btcoexist,
- BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_1ANT_GNT_CTRL_BY_PTA,
- BT_8822B_1ANT_SIG_STA_SET_BY_HW);
-
- /* set Path control owner to WL at runtime step */
- halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist,
- BT_8822B_1ANT_PCO_WLSIDE);
-
- coex_sta->run_time_state = true;
-
- if (BTC_ANT_PATH_AUTO == ant_pos_type)
- ant_pos_type = BTC_ANT_PATH_PTA;
-
- break;
- case BT_8822B_1ANT_PHASE_5G_RUNTIME:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (set_ant_path - 1ANT_PHASE_5G_RUNTIME) **********\n" );
- BTC_TRACE(trace_buf);
-
- /* set GNT_BT to SW Hi */
- halbtc8822b1ant_ltecoex_set_gnt_bt(btcoexist,
- BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_1ANT_GNT_CTRL_BY_SW,
- BT_8822B_1ANT_SIG_STA_SET_TO_HIGH);
-
- /* Set GNT_WL to SW Hi */
- halbtc8822b1ant_ltecoex_set_gnt_wl(btcoexist,
- BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_1ANT_GNT_CTRL_BY_SW,
- BT_8822B_1ANT_SIG_STA_SET_TO_HIGH);
-
- /* set Path control owner to WL at runtime step */
- halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist,
- BT_8822B_1ANT_PCO_WLSIDE);
-
- coex_sta->run_time_state = true;
-
- if (BTC_ANT_PATH_AUTO == ant_pos_type)
- ant_pos_type = BTC_ANT_PATH_WIFI5G;
-
- break;
- case BT_8822B_1ANT_PHASE_BTMPMODE :
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (set_ant_path - 1ANT_PHASE_BTMPMODE) **********\n" );
- BTC_TRACE(trace_buf);
-
- /* Disable LTE Coex Function in WiFi side */
- halbtc8822b1ant_ltecoex_enable(btcoexist, 0x0);
-
- /* set GNT_BT to SW Hi */
- halbtc8822b1ant_ltecoex_set_gnt_bt(btcoexist,
- BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_1ANT_GNT_CTRL_BY_SW,
- BT_8822B_1ANT_SIG_STA_SET_TO_HIGH);
-
- /* Set GNT_WL to SW Lo */
- halbtc8822b1ant_ltecoex_set_gnt_wl(btcoexist,
- BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_1ANT_GNT_CTRL_BY_SW,
- BT_8822B_1ANT_SIG_STA_SET_TO_LOW);
-
- /* set Path control owner to WL */
- halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist,
- BT_8822B_1ANT_PCO_WLSIDE);
-
- coex_sta->run_time_state = false;
-
- /* Set Ext Ant Switch to BT side at BT MP mode */
- if (BTC_ANT_PATH_AUTO == ant_pos_type)
- ant_pos_type = BTC_ANT_PATH_BT;
-
- break;
- }
-
-
- if (phase != BT_8822B_1ANT_PHASE_WLAN_OFF)
- {
- switch (ant_pos_type) {
- case BTC_ANT_PATH_WIFI:
- halbtc8822b1ant_set_ext_ant_switch( btcoexist,
- force_exec,
- BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW,
- BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLG);
- break;
- case BTC_ANT_PATH_WIFI5G:
- halbtc8822b1ant_set_ext_ant_switch( btcoexist,
- force_exec,
- BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW,
- BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLA);
- break;
- case BTC_ANT_PATH_BT:
- halbtc8822b1ant_set_ext_ant_switch( btcoexist,
- force_exec,
- BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW,
- BT_8822B_1ANT_EXT_ANT_SWITCH_TO_BT);
- break;
- default:
- case BTC_ANT_PATH_PTA:
- halbtc8822b1ant_set_ext_ant_switch( btcoexist,
- force_exec,
- BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_PTA,
- BT_8822B_1ANT_EXT_ANT_SWITCH_TO_NOCARE);
- break;
- }
-
- }
-#if 1
- u32tmp1 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
- u32tmp2 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
- u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4);
-
- u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (After Ant Setup) 0xcb4 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n",
- u32tmp3, u8tmp, u32tmp1, u32tmp2);
- BTC_TRACE(trace_buf);
-
-#endif
-
-}
-
-
-void halbtc8822b1ant_coex_all_off(IN struct btc_coexist *btcoexist)
-{
- /* sw all off */
- halbtc8822b1ant_sw_mechanism(btcoexist, false);
-
- /* hw all off */
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-}
-boolean halbtc8822b1ant_is_common_action(IN struct btc_coexist *btcoexist)
-{
- boolean common = false, wifi_connected = false, wifi_busy = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- if (!wifi_connected &&
- BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
- coex_dm->bt_status) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n");
- BTC_TRACE(trace_buf);
-
- /* halbtc8822b1ant_sw_mechanism(btcoexist, false); */
-
- common = true;
- } else if (wifi_connected &&
- (BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
- coex_dm->bt_status)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi connected + BT non connected-idle!!\n");
- BTC_TRACE(trace_buf);
-
- /* halbtc8822b1ant_sw_mechanism(btcoexist, false); */
-
- common = true;
- } else if (!wifi_connected &&
- (BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi non connected-idle + BT connected-idle!!\n");
- BTC_TRACE(trace_buf);
-
- /* halbtc8822b1ant_sw_mechanism(btcoexist, false); */
-
- common = true;
- } else if (wifi_connected &&
- (BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi connected + BT connected-idle!!\n");
- BTC_TRACE(trace_buf);
-
- /* halbtc8822b1ant_sw_mechanism(btcoexist, false); */
-
- common = true;
- } else if (!wifi_connected &&
- (BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE != coex_dm->bt_status)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi non connected-idle + BT Busy!!\n");
- BTC_TRACE(trace_buf);
-
- /* halbtc8822b1ant_sw_mechanism(btcoexist, false); */
-
- common = true;
- } else {
- if (wifi_busy) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi Connected-Busy + BT Busy!!\n");
- BTC_TRACE(trace_buf);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi Connected-Idle + BT Busy!!\n");
- BTC_TRACE(trace_buf);
- }
-
- common = false;
- }
-
- return common;
-}
-
-void halbtc8822b1ant_action_wifi_under5g(IN struct btc_coexist *btcoexist)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], under 5g start \n");
- BTC_TRACE(trace_buf);
-
- halbtc8822b1ant_ignore_wlan_act(btcoexist, NORMAL_EXEC, true);
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 10);
-
- halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC,
- BT_8822B_1ANT_PHASE_5G_RUNTIME);
-
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
-
- halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
-
- halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 5);
-
-}
-
-
-
-void halbtc8822b1ant_action_wifi_only(IN struct btc_coexist *btcoexist)
-{
- boolean wifi_under_5g = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
- if(wifi_under_5g)
- {
- halbtc8822b1ant_action_wifi_under5g(btcoexist);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (wlan only -- under 5g ) **********\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- halbtc8822b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
- halbtc8822b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8);
-
- halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC,
- BT_8822B_1ANT_PHASE_2G_RUNTIME);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (wlan only -- under 2g ) **********\n");
- BTC_TRACE(trace_buf);
-
-}
-
-/* *********************************************
- *
- * Software Coex Mechanism start
- *
- * ********************************************* */
-
-/* SCO only or SCO+PAN(HS) */
-
-/*
-void halbtc8822b1ant_action_sco(IN struct btc_coexist* btcoexist)
-{
- halbtc8822b1ant_sw_mechanism(btcoexist, true);
-}
-
-
-void halbtc8822b1ant_action_hid(IN struct btc_coexist* btcoexist)
-{
- halbtc8822b1ant_sw_mechanism(btcoexist, true);
-}
-
-
-void halbtc8822b1ant_action_a2dp(IN struct btc_coexist* btcoexist)
-{
- halbtc8822b1ant_sw_mechanism(btcoexist, false);
-}
-
-void halbtc8822b1ant_action_a2dp_pan_hs(IN struct btc_coexist* btcoexist)
-{
- halbtc8822b1ant_sw_mechanism(btcoexist, false);
-}
-
-void halbtc8822b1ant_action_pan_edr(IN struct btc_coexist* btcoexist)
-{
- halbtc8822b1ant_sw_mechanism(btcoexist, false);
-}
-
-
-void halbtc8822b1ant_action_pan_hs(IN struct btc_coexist* btcoexist)
-{
- halbtc8822b1ant_sw_mechanism(btcoexist, false);
-}
-
-
-void halbtc8822b1ant_action_pan_edr_a2dp(IN struct btc_coexist* btcoexist)
-{
- halbtc8822b1ant_sw_mechanism(btcoexist, false);
-}
-
-void halbtc8822b1ant_action_pan_edr_hid(IN struct btc_coexist* btcoexist)
-{
- halbtc8822b1ant_sw_mechanism(btcoexist, true);
-}
-
-
-void halbtc8822b1ant_action_hid_a2dp_pan_edr(IN struct btc_coexist* btcoexist)
-{
- halbtc8822b1ant_sw_mechanism(btcoexist, true);
-}
-
-void halbtc8822b1ant_action_hid_a2dp(IN struct btc_coexist* btcoexist)
-{
- halbtc8822b1ant_sw_mechanism(btcoexist, true);
-}
-
-*/
-
-/* *********************************************
- *
- * Non-Software Coex Mechanism start
- *
- * ********************************************* */
-void halbtc8822b1ant_action_bt_whck_test(IN struct btc_coexist *btcoexist)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex],action_bt_whck_test\n");
- BTC_TRACE(trace_buf);
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
-
- halbtc8822b1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_AUTO,
- NORMAL_EXEC,
- BT_8822B_1ANT_PHASE_2G_RUNTIME);
-
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-}
-
-void halbtc8822b1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex],action_wifi_multi_port\n");
- BTC_TRACE(trace_buf);
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
-
- halbtc8822b1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_AUTO,
- NORMAL_EXEC,
- BT_8822B_1ANT_PHASE_2G_RUNTIME);
-
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
-}
-
-void halbtc8822b1ant_action_hs(IN struct btc_coexist *btcoexist)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], action_hs\n");
- BTC_TRACE(trace_buf);
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
-
- halbtc8822b1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_AUTO,
- NORMAL_EXEC,
- BT_8822B_1ANT_PHASE_2G_RUNTIME);
-
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
-}
-
-/*"""bt inquiry"""" + wifi any + bt any*/
-void halbtc8822b1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist)
-{
-
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_connected = false, ap_enable = false, wifi_busy = false,
- bt_busy = false;
-
-
- boolean wifi_scan = false, link = false, roam = false;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (bt inquiry) **********\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
- &ap_enable);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
-
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
-
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** scan = %d, link =%d, roam = %d**********\n",
- wifi_scan, link, roam);
- BTC_TRACE(trace_buf);
-
- if ( (link) || (roam) || (coex_sta->wifi_is_high_pri_task)){
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (bt inquiry wifi connect or scan ) **********\n");
- BTC_TRACE(trace_buf);
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 1);
-
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6);
-
- } else if ((wifi_scan) && (coex_sta->bt_create_connection)) {
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22);
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6);
-
- } else if ((!wifi_connected) && (!wifi_scan)) {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (bt inquiry wifi non connect) **********\n");
- BTC_TRACE(trace_buf);
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
-
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- } else if ((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) {
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22);
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- } else if (bt_link_info->a2dp_exist) {
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
-
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- } else if (wifi_scan) {
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
-
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- } else if (wifi_busy) {
-
- /* for BT inquiry/page fail after S4 resume */
- /* halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20); */
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
-
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 1);
- }else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (bt inquiry wifi connect) **********\n");
- BTC_TRACE(trace_buf);
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22);
-
- halbtc8822b1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_AUTO,
- NORMAL_EXEC,
- BT_8822B_1ANT_PHASE_2G_RUNTIME);
-
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 1);
- }
-
-/*
- if ((wifi_link) || (wifi_roam) || (coex_sta->wifi_is_high_pri_task)) {
-
- halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33);
- halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6);
-
- } else if ((wifi_scan) && (coex_sta->bt_create_connection)) {
-
- halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22);
- halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6);
-
- } else if ((!wifi_connected) && (!wifi_scan)) {
-
- halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
-
- halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
- } else if ((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) {
-
- halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22);
- halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
-
- } else if (bt_link_info->a2dp_exist) {
-
- halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
-
- halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- } else if (wifi_scan) {
-
- halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
-
- halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
-
- } else if (wifi_busy) {
- halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 21);
-
- halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- } else {
- halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 19);
-
- halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- }
-*/
-}
-
-void halbtc8822b1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist
- *btcoexist, IN u8 wifi_status)
-{
-
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (bt sco hid only busy) **********\n");
- BTC_TRACE(trace_buf);
-
- /*SCO + wifi conected idle or busy / 0x778=1@wifi slot*/
- if (bt_link_info->sco_exist) {
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
-
- } else { /* HID + wifi conected idle or busy / 0x778=1@wifi slot */
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
-
- }
-}
-
-/*wifi connected + bt acl busy*/
-void halbtc8822b1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist
- *btcoexist, IN u8 wifi_status)
-{
-
- u8 bt_rssi_state;
-
-
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- bt_rssi_state = halbtc8822b1ant_bt_rssi_state(2, 28, 0);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (wifi connect acl busy) **********\n");
- BTC_TRACE(trace_buf);
-
- if (bt_link_info->hid_only) { /* HID + wifi conected idle or busy / 0x778=1@wifi slot */
- halbtc8822b1ant_action_bt_sco_hid_only_busy(btcoexist,
- wifi_status);
- return;
- } else if (bt_link_info->a2dp_only) { /* A2DP + wifi conected idle or busy */
- if (BT_8822B_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifi_status) {
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 32);
- halbtc8822b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 1);
- } else {
- if (coex_sta->scan_ap_num >=
- BT_8822B_1ANT_WIFI_NOISY_THRESH) {
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 17);
- } else {
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 42);
- }
-
- halbtc8822b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 1);
- coex_dm->auto_tdma_adjust = true;
- }
-
- /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */
- } else if (((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) ||
- (bt_link_info->hid_exist && bt_link_info->a2dp_exist &&
- bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 44);
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 1);
- } else if (bt_link_info->hid_exist &&
- bt_link_info->a2dp_exist) { /* HID+A2DP */
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 42);
-
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 1);
-
- } else if ((bt_link_info->pan_only) || (bt_link_info->hid_exist &&
- bt_link_info->pan_exist)) { /* PAN(OPP,FTP), HID+PAN(OPP,FTP)*/
- /*
- if (BT_8723D_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifi_status)
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 4);
- else
- */
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 45);
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 1);
- } else {
- /* BT no-profile busy (0x9) */
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33);
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 1);
- }
-}
-
-/*wifi not connected + bt action*/
-void halbtc8822b1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (wifi not connect) **********\n");
- BTC_TRACE(trace_buf);
-
- /* tdma and coex table */
- halbtc8822b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8);
-
- halbtc8822b1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_AUTO,
- NORMAL_EXEC,
- BT_8822B_1ANT_PHASE_2G_RUNTIME);
-
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-}
-
-/*""""wl not connected scan"""" + bt action*/
-void halbtc8822b1ant_action_wifi_not_connected_scan(IN struct btc_coexist
- *btcoexist)
-{
-
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_connected = false, bt_hs_on = false;
- u32 wifi_link_status = 0;
- u32 num_of_wifi_link = 0;
- boolean bt_ctrl_agg_buf_size = false;
- u8 agg_buf_size = 5;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (wifi non connect scan) **********\n");
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
-
- num_of_wifi_link = wifi_link_status >> 16;
-
- if (num_of_wifi_link >= 2) {
- halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
- halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
- bt_ctrl_agg_buf_size, agg_buf_size);
-
- if (coex_sta->c2h_bt_inquiry_page) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], BT Is Inquirying\n");
- BTC_TRACE(trace_buf);
- halbtc8822b1ant_action_bt_inquiry(btcoexist);
- } else
- halbtc8822b1ant_action_wifi_multi_port(btcoexist);
- return;
- }
-
- if (coex_sta->c2h_bt_inquiry_page) {
- halbtc8822b1ant_action_bt_inquiry(btcoexist);
- return;
- } else if (bt_hs_on) {
- halbtc8822b1ant_action_hs(btcoexist);
- return;
- }
-
- /* tdma and coex table */
- if (BT_8822B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
- if (bt_link_info->a2dp_exist) {
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 32);
- halbtc8822b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 1);
- } else if (bt_link_info->a2dp_exist &&
- bt_link_info->pan_exist) {
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 22);
- halbtc8822b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 1);
- } else {
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
- halbtc8822b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 1);
- }
- } else if ((BT_8822B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
- (BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY ==
- coex_dm->bt_status)) {
- halbtc8822b1ant_action_bt_sco_hid_only_busy(btcoexist,
- BT_8822B_1ANT_WIFI_STATUS_CONNECTED_SCAN);
- } else {
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
-
- halbtc8822b1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_AUTO,
- NORMAL_EXEC,
- BT_8822B_1ANT_PHASE_2G_RUNTIME);
-
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 5);
- }
-}
-
-/*""""wl not connected asso"""" + bt action*/
-void halbtc8822b1ant_action_wifi_not_connected_asso_auth(
- IN struct btc_coexist *btcoexist)
-{
-
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_connected = false, bt_hs_on = false;
- u32 wifi_link_status = 0;
- u32 num_of_wifi_link = 0;
- boolean bt_ctrl_agg_buf_size = false;
- u8 agg_buf_size = 5;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (wifi non connect asso_auth) **********\n");
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
-
- num_of_wifi_link = wifi_link_status >> 16;
-
- if (num_of_wifi_link >= 2) {
-
- halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
- halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
- bt_ctrl_agg_buf_size, agg_buf_size);
-
- if (coex_sta->c2h_bt_inquiry_page) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], BT Is Inquirying\n");
- BTC_TRACE(trace_buf);
- halbtc8822b1ant_action_bt_inquiry(btcoexist);
- } else
- halbtc8822b1ant_action_wifi_multi_port(btcoexist);
- return;
- }
-
- if (coex_sta->c2h_bt_inquiry_page) {
- halbtc8822b1ant_action_bt_inquiry(btcoexist);
- return;
- } else if (bt_hs_on) {
- halbtc8822b1ant_action_hs(btcoexist);
- return;
- }
-
-
- /* tdma and coex table */
- if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) ||
- (bt_link_info->a2dp_exist)) {
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
- halbtc8822b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4);
- } else if (bt_link_info->pan_exist) {
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
- halbtc8822b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4);
- } else {
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
-
- halbtc8822b1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_AUTO,
- NORMAL_EXEC,
- BT_8822B_1ANT_PHASE_2G_RUNTIME);
-
- halbtc8822b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 2);
- }
-}
-
-/*""""wl connected scan"""" + bt action*/
-void halbtc8822b1ant_action_wifi_connected_scan(IN struct btc_coexist
- *btcoexist)
-{
-
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_connected = false, bt_hs_on = false;
- u32 wifi_link_status = 0;
- u32 num_of_wifi_link = 0;
- boolean bt_ctrl_agg_buf_size = false;
- u8 agg_buf_size = 5;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (wifi connect scan) **********\n");
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
-
- num_of_wifi_link = wifi_link_status >> 16;
-
- if (num_of_wifi_link >= 2) {
- halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
- halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
- bt_ctrl_agg_buf_size, agg_buf_size);
-
- if (coex_sta->c2h_bt_inquiry_page) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], BT Is Inquirying\n");
- BTC_TRACE(trace_buf);
- halbtc8822b1ant_action_bt_inquiry(btcoexist);
- } else
- halbtc8822b1ant_action_wifi_multi_port(btcoexist);
- return;
- }
-
- if (coex_sta->c2h_bt_inquiry_page) {
- halbtc8822b1ant_action_bt_inquiry(btcoexist);
- return;
- } else if (bt_hs_on) {
- halbtc8822b1ant_action_hs(btcoexist);
- return;
- }
-
- /* tdma and coex table */
- if (BT_8822B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
- if (bt_link_info->a2dp_exist) {
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 32);
- halbtc8822b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 1);
- } else if (bt_link_info->a2dp_exist &&
- bt_link_info->pan_exist) {
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 22);
- halbtc8822b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 1);
- } else {
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
- halbtc8822b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 1);
- }
- } else if ((BT_8822B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
- (BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY ==
- coex_dm->bt_status)) {
- halbtc8822b1ant_action_bt_sco_hid_only_busy(btcoexist,
- BT_8822B_1ANT_WIFI_STATUS_CONNECTED_SCAN);
- } else {
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
-
- halbtc8822b1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_AUTO,
- NORMAL_EXEC,
- BT_8822B_1ANT_PHASE_2G_RUNTIME);
-
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 5);
- }
-}
-
-/*""""wl connected specific packet"""" + bt action*/
-void halbtc8822b1ant_action_wifi_connected_specific_packet(
- IN struct btc_coexist *btcoexist)
-{
-
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_connected = false, bt_hs_on = false;
- u32 wifi_link_status = 0;
- u32 num_of_wifi_link = 0;
- boolean bt_ctrl_agg_buf_size = false;
- u8 agg_buf_size = 5;
- boolean wifi_busy = false;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (wifi connect specific packet) **********\n");
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
-
- num_of_wifi_link = wifi_link_status >> 16;
-
- if (num_of_wifi_link >= 2) {
- halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
- halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
- bt_ctrl_agg_buf_size, agg_buf_size);
-
- if (coex_sta->c2h_bt_inquiry_page) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], BT Is Inquirying\n");
- BTC_TRACE(trace_buf);
- halbtc8822b1ant_action_bt_inquiry(btcoexist);
- } else
- halbtc8822b1ant_action_wifi_multi_port(btcoexist);
- return;
- }
-
- if (coex_sta->c2h_bt_inquiry_page) {
- halbtc8822b1ant_action_bt_inquiry(btcoexist);
- return;
- } else if (bt_hs_on) {
- halbtc8822b1ant_action_hs(btcoexist);
- return;
- }
-
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- /* no specific packet process for both WiFi and BT very busy */
- if ((wifi_busy) && ((bt_link_info->pan_exist) ||
- (coex_sta->num_of_profile >= 2)))
- return;
-
- /* tdma and coex table */
- if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist)) {
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
- } else if (bt_link_info->a2dp_exist) {
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 1);
- } else if (bt_link_info->pan_exist) {
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 1);
- } else {
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
-
- halbtc8822b1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_AUTO,
- NORMAL_EXEC,
- BT_8822B_1ANT_PHASE_2G_RUNTIME);
-
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 5);
- }
-}
-
-/*wifi connected input point : to set different ps and tdma case (+bt different case)*/
-void halbtc8822b1ant_action_wifi_connected(IN struct btc_coexist *btcoexist)
-{
-
- boolean wifi_busy = false;
- boolean scan = false, link = false, roam = false;
- boolean under_4way = false, ap_enable = false, wifi_under_5g=false;
-
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CoexForWifiConnect()===>\n");
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
-
- if (wifi_under_5g) {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CoexForWifiConnect(), return for wifi is under 5g<===\n");
- BTC_TRACE(trace_buf);
-
- halbtc8822b1ant_action_wifi_under5g(btcoexist);
-
- return;
- } else {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CoexForWifiConnect(), return for wifi is under 2g<===\n");
- BTC_TRACE(trace_buf);
-
- halbtc8822b1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_AUTO,
- NORMAL_EXEC,
- BT_8822B_1ANT_PHASE_2G_RUNTIME);
- }
-
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
- &under_4way);
-
- if (under_4way) {
- halbtc8822b1ant_action_wifi_connected_specific_packet(btcoexist);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CoexForWifiConnect(), return for wifi is under 4way<===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
- if (scan || link || roam) {
- if (scan)
- halbtc8822b1ant_action_wifi_connected_scan(btcoexist);
- else
- halbtc8822b1ant_action_wifi_connected_specific_packet(
- btcoexist);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CoexForWifiConnect(), return for wifi is under scan<===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
- &ap_enable);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- /* tdma and coex table */
- if (!wifi_busy) {
- if (BT_8822B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
- halbtc8822b1ant_action_wifi_connected_bt_acl_busy(
- btcoexist,
- BT_8822B_1ANT_WIFI_STATUS_CONNECTED_IDLE);
- } else if ((BT_8822B_1ANT_BT_STATUS_SCO_BUSY ==
- coex_dm->bt_status) ||
- (BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY ==
- coex_dm->bt_status)) {
- halbtc8822b1ant_action_bt_sco_hid_only_busy(btcoexist,
- BT_8822B_1ANT_WIFI_STATUS_CONNECTED_IDLE);
- } else {
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 8);
-
- halbtc8822b1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_AUTO,
- NORMAL_EXEC,
- BT_8822B_1ANT_PHASE_2G_RUNTIME);
-
- if ((coex_sta->high_priority_tx) +
- (coex_sta->high_priority_rx) <= 60)
- /*sy modify case16 -> case17*/
- halbtc8822b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 1);
- else
- halbtc8822b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 7);
- }
- } else {
- if (BT_8822B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
- halbtc8822b1ant_action_wifi_connected_bt_acl_busy(
- btcoexist,
- BT_8822B_1ANT_WIFI_STATUS_CONNECTED_BUSY);
- } else if ((BT_8822B_1ANT_BT_STATUS_SCO_BUSY ==
- coex_dm->bt_status) ||
- (BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY ==
- coex_dm->bt_status)) {
- halbtc8822b1ant_action_bt_sco_hid_only_busy(btcoexist,
- BT_8822B_1ANT_WIFI_STATUS_CONNECTED_BUSY);
- } else {
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 8);
-
- halbtc8822b1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_AUTO,
- NORMAL_EXEC,
- BT_8822B_1ANT_PHASE_2G_RUNTIME);
-
- if ((coex_sta->high_priority_tx) +
- (coex_sta->high_priority_rx) <= 60)
- /*sy modify case16 -> case17*/
-
- halbtc8822b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 1);
- else
- halbtc8822b1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 7);
- }
- }
-}
-
-void halbtc8822b1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist)
-{
-
- u8 algorithm = 0;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (runswcoexmech) **********\n");
- BTC_TRACE(trace_buf);
- algorithm = halbtc8822b1ant_action_algorithm(btcoexist);
- coex_dm->cur_algorithm = algorithm;
-
- if (halbtc8822b1ant_is_common_action(btcoexist)) {
-
- } else {
- switch (coex_dm->cur_algorithm) {
- case BT_8822B_1ANT_COEX_ALGO_SCO:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = SCO.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8822b1ant_action_sco(btcoexist); */
- break;
- case BT_8822B_1ANT_COEX_ALGO_HID:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = HID.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8822b1ant_action_hid(btcoexist); */
- break;
- case BT_8822B_1ANT_COEX_ALGO_A2DP:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = A2DP.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8822b1ant_action_a2dp(btcoexist); */
- break;
- case BT_8822B_1ANT_COEX_ALGO_A2DP_PANHS:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = A2DP+PAN(HS).\n");
- BTC_TRACE(trace_buf);
- /* halbtc8822b1ant_action_a2dp_pan_hs(btcoexist); */
- break;
- case BT_8822B_1ANT_COEX_ALGO_PANEDR:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = PAN(EDR).\n");
- BTC_TRACE(trace_buf);
- /* halbtc8822b1ant_action_pan_edr(btcoexist); */
- break;
- case BT_8822B_1ANT_COEX_ALGO_PANHS:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = HS mode.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8822b1ant_action_pan_hs(btcoexist); */
- break;
- case BT_8822B_1ANT_COEX_ALGO_PANEDR_A2DP:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = PAN+A2DP.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8822b1ant_action_pan_edr_a2dp(btcoexist); */
- break;
- case BT_8822B_1ANT_COEX_ALGO_PANEDR_HID:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = PAN(EDR)+HID.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8822b1ant_action_pan_edr_hid(btcoexist); */
- break;
- case BT_8822B_1ANT_COEX_ALGO_HID_A2DP_PANEDR:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = HID+A2DP+PAN.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8822b1ant_action_hid_a2dp_pan_edr(btcoexist); */
- break;
- case BT_8822B_1ANT_COEX_ALGO_HID_A2DP:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = HID+A2DP.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8822b1ant_action_hid_a2dp(btcoexist); */
- break;
- default:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = coexist All Off!!\n");
- BTC_TRACE(trace_buf);
- /* halbtc8822b1ant_coex_all_off(btcoexist); */
- break;
- }
- coex_dm->pre_algorithm = coex_dm->cur_algorithm;
- }
-}
-
-void halbtc8822b1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist)
-{
-
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_connected = false, bt_hs_on = false;
- boolean increase_scan_dev_num = false;
- boolean bt_ctrl_agg_buf_size = false;
- boolean miracast_plus_bt = false;
- u8 agg_buf_size = 5;
- u32 wifi_link_status = 0;
- u32 num_of_wifi_link = 0, wifi_bw;
- u8 iot_peer = BTC_IOT_PEER_UNKNOWN;
- boolean wifi_under_5g = false;
-
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism()===>\n");
- BTC_TRACE(trace_buf);
-
- if (btcoexist->manual_control) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- if (btcoexist->stop_coex_dm) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- if (coex_sta->under_ips) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], wifi is under IPS !!!\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- if (!coex_sta->run_time_state){
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], return for run_time_state = false !!!\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
- if(wifi_under_5g)
- {
- halbtc8822b1ant_action_wifi_under5g(btcoexist);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], WiFi is under 5G!!! \n");
- BTC_TRACE(trace_buf);
- return;
- }else{
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], WiFi is under 2G!!!\n");
- BTC_TRACE(trace_buf);
-
- halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
- NORMAL_EXEC, BT_8822B_1ANT_PHASE_2G_RUNTIME);
- }
-
- if (coex_sta->bt_whck_test) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is under WHCK TEST!!!\n");
- BTC_TRACE(trace_buf);
- halbtc8822b1ant_action_bt_whck_test(btcoexist);
- return;
- }
-
- if (coex_sta->bt_disabled) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is disabled !!!\n");
- halbtc8822b1ant_action_wifi_only(btcoexist);
- return;
- }
-
- if ((BT_8822B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
- (BT_8822B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
- (BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status))
- increase_scan_dev_num = true;
-
- btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM,
- &increase_scan_dev_num);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
- num_of_wifi_link = wifi_link_status >> 16;
-
- if ((num_of_wifi_link >= 2) ||
- (wifi_link_status & WIFI_P2P_GO_CONNECTED)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n",
- num_of_wifi_link, wifi_link_status);
- BTC_TRACE(trace_buf);
-
- if (bt_link_info->bt_link_exist) {
- halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1,
- 0, 1);
- miracast_plus_bt = true;
- } else {
- halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
- miracast_plus_bt = false;
- }
- btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
- &miracast_plus_bt);
- halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
- bt_ctrl_agg_buf_size, agg_buf_size);
-
- if ((bt_link_info->a2dp_exist) &&
- (coex_sta->c2h_bt_inquiry_page)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], BT Is Inquirying\n");
- BTC_TRACE(trace_buf);
- halbtc8822b1ant_action_bt_inquiry(btcoexist);
- } else
- halbtc8822b1ant_action_wifi_multi_port(btcoexist);
-
- return;
- } else {
- miracast_plus_bt = false;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
- &miracast_plus_bt);
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- if ((bt_link_info->bt_link_exist) && (wifi_connected)) {
- halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, 0, 1);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer);
-
- if (BTC_IOT_PEER_CISCO != iot_peer) {
- if (bt_link_info->sco_exist) /* if (bt_link_info->bt_hi_pri_link_exist) */
- halbtc8822b1ant_limited_rx(btcoexist,
- NORMAL_EXEC, true, false, 0x5);
- else
- halbtc8822b1ant_limited_rx(btcoexist,
- NORMAL_EXEC, false, false, 0x5);
- } else {
- if (bt_link_info->sco_exist)
- halbtc8822b1ant_limited_rx(btcoexist,
- NORMAL_EXEC, true, false, 0x5);
- else {
- if (BTC_WIFI_BW_HT40 == wifi_bw)
- halbtc8822b1ant_limited_rx(btcoexist,
- NORMAL_EXEC, false, true, 0x10);
- else
- halbtc8822b1ant_limited_rx(btcoexist,
- NORMAL_EXEC, false, true, 0x8);
- }
- }
-
- halbtc8822b1ant_sw_mechanism(btcoexist, true);
- halbtc8822b1ant_run_sw_coexist_mechanism(
- btcoexist); /* just print debug message */
- } else {
- halbtc8822b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
-
- halbtc8822b1ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
- 0x5);
-
- halbtc8822b1ant_sw_mechanism(btcoexist, false);
- halbtc8822b1ant_run_sw_coexist_mechanism(
- btcoexist); /* //just print debug message */
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- if (coex_sta->c2h_bt_inquiry_page) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], BT Is Inquirying\n");
- BTC_TRACE(trace_buf);
- halbtc8822b1ant_action_bt_inquiry(btcoexist);
- return;
- } else if (bt_hs_on) {
- halbtc8822b1ant_action_hs(btcoexist);
- return;
- }
-
-
- if (!wifi_connected) {
- boolean scan = false, link = false, roam = false;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], wifi is non connected-idle !!!\n");
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
-
- if (scan || link || roam) {
- if (scan)
- halbtc8822b1ant_action_wifi_not_connected_scan(
- btcoexist);
- else
- halbtc8822b1ant_action_wifi_not_connected_asso_auth(
- btcoexist);
- } else
- halbtc8822b1ant_action_wifi_not_connected(btcoexist);
- } else /* wifi LPS/Busy */
- halbtc8822b1ant_action_wifi_connected(btcoexist);
-}
-
-u32 halbtc8822b1ant_psd_log2base(IN struct btc_coexist *btcoexist, IN u32 val)
-{
- u8 j;
- u32 tmp, tmp2, val_integerd_b = 0, tindex, shiftcount = 0;
- u32 result, val_fractiond_b = 0, table_fraction[21] = {0, 432, 332, 274, 232, 200,
- 174, 151, 132, 115, 100, 86, 74, 62, 51, 42,
- 32, 23, 15, 7, 0
- };
-
- if (val == 0)
- return 0;
-
- tmp = val;
-
- while (1) {
- if (tmp == 1)
- break;
- else {
- tmp = (tmp >> 1);
- shiftcount++;
- }
- }
-
-
- val_integerd_b = shiftcount + 1;
-
- tmp2 = 1;
- for (j = 1; j <= val_integerd_b; j++)
- tmp2 = tmp2 * 2;
-
- tmp = (val * 100) / tmp2;
- tindex = tmp / 5;
-
- if (tindex > 20)
- tindex = 20;
-
- val_fractiond_b = table_fraction[tindex];
-
- result = val_integerd_b * 100 - val_fractiond_b;
-
- return result;
-
-
-}
-
-void halbtc8822b1ant_init_coex_dm(IN struct btc_coexist *btcoexist)
-{
- /* force to reset coex mechanism */
-
- /* sw all off */
- halbtc8822b1ant_sw_mechanism(btcoexist, false);
-
- /* halbtc8822b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8); */
- /* halbtc8822b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); */
-
- coex_sta->pop_event_cnt = 0;
-}
-
-void halbtc8822b1ant_init_hw_config(IN struct btc_coexist *btcoexist,
- IN boolean back_up, IN boolean wifi_only)
-{
-
- u8 u8tmp = 0;
- boolean wifi_under_5g = false;
- u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0;
-
-
- u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4);
- u32tmp1 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
- u32tmp2 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (Before Init HW config) 0xcb4 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n",
- u32tmp3, u32tmp1, u32tmp2);
- BTC_TRACE(trace_buf);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], 1Ant Init HW Config!!\n");
- BTC_TRACE(trace_buf);
-
- coex_sta->bt_coex_supported_feature = 0;
- coex_sta->bt_coex_supported_version = 0;
-
- /* Setup RF front end type */
- halbtc8822b1ant_set_rfe_type(btcoexist);
-
- /* 0xf0[15:12] --> Chip Cut information */
- coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist,
- 0xf1) & 0xf0) >> 4;
-
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8,
- 0x1); /* enable TBTT nterrupt */
-
- /* BT report packet sample rate */
- /* 0x790[5:0]=0x5 */
- u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790);
- u8tmp &= 0xc0;
- u8tmp |= 0x5;
- btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp);
-
- /* Enable BT counter statistics */
- btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1);
-
- /* Enable PTA (3-wire function form BT side) */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x41, 0x02, 0x1);
-
- /* Enable PTA (tx/rx signal form WiFi side) */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4c6, 0x10, 0x1);
-
- /* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */
- /*btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x1);*/
-
- /* enable GNT_WL */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x40, 0x0);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x1, 0x0);
-
- if (btcoexist->btc_read_1byte(btcoexist, 0x80) == 0xc6)
- halbtc8822b1ant_post_onoffstate_to_bt(btcoexist, TRUE);
-
- /* Antenna config */
- if (wifi_only) {
-
- coex_sta->concurrent_rx_mode_on = false;
- halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_WIFI,
- FORCE_EXEC, BT_8822B_1ANT_PHASE_WLANONLY_INIT);
- } else {
-
- coex_sta->concurrent_rx_mode_on = true;
-
- halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
- FORCE_EXEC, BT_8822B_1ANT_PHASE_COEX_INIT);
- }
-
-
- /* PTA parameter */
- halbtc8822b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
-
- halbtc8822b1ant_enable_gnt_to_gpio(btcoexist, TRUE);
-
-}
-
-
-
-void halbtc8822b1ant_psd_showdata(IN struct btc_coexist *btcoexist)
-{
- u8 *cli_buf = btcoexist->cli_buf;
- u32 delta_freq_per_point;
- u32 freq, freq1, freq2, n = 0, i = 0, j = 0, m = 0, psd_rep1, psd_rep2;
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n\n============[PSD info] (%d)============\n",
- psd_scan->psd_gen_count);
- CL_PRINTF(cli_buf);
-
- if (psd_scan->psd_gen_count == 0) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n No data !!\n");
- CL_PRINTF(cli_buf);
- return;
- }
-
- if (psd_scan->psd_point == 0)
- delta_freq_per_point = 0;
- else
- delta_freq_per_point = psd_scan->psd_band_width /
- psd_scan->psd_point;
-
- /* if (psd_scan->is_psd_show_max_only) */
- if (0) {
- psd_rep1 = psd_scan->psd_max_value / 100;
- psd_rep2 = psd_scan->psd_max_value - psd_rep1 * 100;
-
- freq = ((psd_scan->real_cent_freq - 20) * 1000000 +
- psd_scan->psd_max_value_point * delta_freq_per_point);
- freq1 = freq / 1000000;
- freq2 = freq / 1000 - freq1 * 1000;
-
- if (freq2 < 100)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n Freq = %d.0%d MHz",
- freq1, freq2);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n Freq = %d.%d MHz",
- freq1, freq2);
-
- if (psd_rep2 < 10)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- ", Value = %d.0%d dB, (%d)\n",
- psd_rep1, psd_rep2, psd_scan->psd_max_value);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- ", Value = %d.%d dB, (%d)\n",
- psd_rep1, psd_rep2, psd_scan->psd_max_value);
-
- CL_PRINTF(cli_buf);
- } else {
- m = psd_scan->psd_start_point;
- n = psd_scan->psd_start_point;
- i = 1;
- j = 1;
-
- while (1) {
- do {
- freq = ((psd_scan->real_cent_freq - 20) * 1000000 + m *
- delta_freq_per_point);
- freq1 = freq / 1000000;
- freq2 = freq / 1000 - freq1 * 1000;
-
- if (i == 1) {
- if (freq2 == 0)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n Freq%6d.000", freq1);
- else if (freq2 < 100)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n Freq%6d.0%2d", freq1,
- freq2);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n Freq%6d.%3d", freq1,
- freq2);
- } else if ((i % 8 == 0) ||
- (m == psd_scan->psd_stop_point)) {
- if (freq2 == 0)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%6d.000\n", freq1);
- else if (freq2 < 100)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%6d.0%2d\n", freq1, freq2);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%6d.%3d\n", freq1, freq2);
- } else {
- if (freq2 == 0)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%6d.000", freq1);
- else if (freq2 < 100)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%6d.0%2d", freq1, freq2);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%6d.%3d", freq1, freq2);
- }
-
- i++;
- m++;
- CL_PRINTF(cli_buf);
-
- } while ((i <= 8) && (m <= psd_scan->psd_stop_point));
-
-
- do {
- psd_rep1 = psd_scan->psd_report_max_hold[n] / 100;
- psd_rep2 = psd_scan->psd_report_max_hold[n] - psd_rep1 *
- 100;
-
- if (j == 1) {
- if (psd_rep2 < 10)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n Val %7d.0%d", psd_rep1,
- psd_rep2);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n Val %7d.%d", psd_rep1,
- psd_rep2);
- } else if ((j % 8 == 0) ||
- (n == psd_scan->psd_stop_point)) {
- if (psd_rep2 < 10)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%7d.0%d\n", psd_rep1,
- psd_rep2);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%7d.%d\n", psd_rep1, psd_rep2);
- } else {
- if (psd_rep2 < 10)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%7d.0%d", psd_rep1, psd_rep2);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%7d.%d", psd_rep1, psd_rep2);
- }
-
- j++;
- n++;
- CL_PRINTF(cli_buf);
-
- } while ((j <= 8) && (n <= psd_scan->psd_stop_point));
-
- if ((m > psd_scan->psd_stop_point) ||
- (n > psd_scan->psd_stop_point))
- break;
- else {
- i = 1;
- j = 1;
- }
-
- }
- }
-
-
-}
-
-void halbtc8822b1ant_psd_max_holddata(IN struct btc_coexist *btcoexist,
- IN u32 gen_count)
-{
- u32 i = 0, i_max = 0, val_max = 0;
-
- if (gen_count == 1) {
- memcpy(psd_scan->psd_report_max_hold,
- psd_scan->psd_report,
- BT_8822B_1ANT_ANTDET_PSD_POINTS * sizeof(u32));
-
- for (i = psd_scan->psd_start_point;
- i <= psd_scan->psd_stop_point; i++) {
-
- }
-
- psd_scan->psd_max_value_point = 0;
- psd_scan->psd_max_value = 0;
-
- } else {
- for (i = psd_scan->psd_start_point;
- i <= psd_scan->psd_stop_point; i++) {
- if (psd_scan->psd_report[i] >
- psd_scan->psd_report_max_hold[i])
- psd_scan->psd_report_max_hold[i] =
- psd_scan->psd_report[i];
-
- /* search Max Value */
- if (i == psd_scan->psd_start_point) {
- i_max = i;
- val_max = psd_scan->psd_report_max_hold[i];
- } else {
- if (psd_scan->psd_report_max_hold[i] >
- val_max) {
- i_max = i;
- val_max = psd_scan->psd_report_max_hold[i];
- }
- }
-
-
-
- }
-
- psd_scan->psd_max_value_point = i_max;
- psd_scan->psd_max_value = val_max;
-
- }
-
-
-}
-
-u32 halbtc8822b1ant_psd_getdata(IN struct btc_coexist *btcoexist, IN u32 point)
-{
- /* reg 0x808[9:0]: FFT data x */
- /* reg 0x808[22]: 0-->1 to get 1 FFT data y */
- /* reg 0x8b4[15:0]: FFT data y report */
-
- u32 val = 0, psd_report = 0;
-
- val = btcoexist->btc_read_4byte(btcoexist, 0x808);
-
- val &= 0xffbffc00;
- val |= point;
-
- btcoexist->btc_write_4byte(btcoexist, 0x808, val);
-
- val |= 0x00400000;
- btcoexist->btc_write_4byte(btcoexist, 0x808, val);
-
-
- val = btcoexist->btc_read_4byte(btcoexist, 0x8b4);
-
- psd_report = val & 0x0000ffff;
-
- return psd_report;
-}
-
-
-void halbtc8822b1ant_psd_sweep_point(IN struct btc_coexist *btcoexist,
- IN u32 cent_freq, IN s32 offset, IN u32 span, IN u32 points,
- IN u32 avgnum)
-{
- u32 i, val, n, k = 0;
- u32 points1 = 0, psd_report = 0;
- u32 start_p = 0, stop_p = 0, delta_freq_per_point = 156250;
- u32 psd_center_freq = 20 * 10 ^ 6, freq, freq1, freq2;
- boolean outloop = false;
- u8 flag = 0;
- u32 tmp, psd_rep1, psd_rep2;
- u32 wifi_original_channel = 1;
-
- psd_scan->is_psd_running = true;
-
- do {
- switch (flag) {
- case 0: /* Get PSD parameters */
- default:
-
- psd_scan->psd_band_width = 40 * 1000000;
- psd_scan->psd_point = points;
- psd_scan->psd_start_base = points / 2;
- psd_scan->psd_avg_num = avgnum;
- psd_scan->real_cent_freq = cent_freq;
- psd_scan->real_offset = offset;
- psd_scan->real_span = span;
-
-
- points1 = psd_scan->psd_point;
- delta_freq_per_point = psd_scan->psd_band_width /
- psd_scan->psd_point;
-
- /* PSD point setup */
- val = btcoexist->btc_read_4byte(btcoexist, 0x808);
- val &= 0xffff0fff;
-
- switch (psd_scan->psd_point) {
- case 128:
- val |= 0x0;
- break;
- case 256:
- default:
- val |= 0x00004000;
- break;
- case 512:
- val |= 0x00008000;
- break;
- case 1024:
- val |= 0x0000c000;
- break;
- }
-
- switch (psd_scan->psd_avg_num) {
- case 1:
- val |= 0x0;
- break;
- case 8:
- val |= 0x00001000;
- break;
- case 16:
- val |= 0x00002000;
- break;
- case 32:
- default:
- val |= 0x00003000;
- break;
- }
- btcoexist->btc_write_4byte(btcoexist, 0x808, val);
-
- flag = 1;
- break;
- case 1: /* calculate the PSD point index from freq/offset/span */
- psd_center_freq = psd_scan->psd_band_width / 2 +
- offset * (1000000);
-
- start_p = psd_scan->psd_start_base + (psd_center_freq -
- span * (1000000) / 2) / delta_freq_per_point;
- psd_scan->psd_start_point = start_p -
- psd_scan->psd_start_base;
-
- stop_p = psd_scan->psd_start_base + (psd_center_freq +
- span * (1000000) / 2) / delta_freq_per_point;
- psd_scan->psd_stop_point = stop_p -
- psd_scan->psd_start_base - 1;
-
- flag = 2;
- break;
- case 2: /* set RF channel/BW/Mode */
-
- /* set 3-wire off */
- val = btcoexist->btc_read_4byte(btcoexist, 0x88c);
- val |= 0x00300000;
- btcoexist->btc_write_4byte(btcoexist, 0x88c, val);
-
- /* CCK off */
- val = btcoexist->btc_read_4byte(btcoexist, 0x800);
- val &= 0xfeffffff;
- btcoexist->btc_write_4byte(btcoexist, 0x800, val);
-
- /* store WiFi original channel */
- wifi_original_channel = btcoexist->btc_get_rf_reg(
- btcoexist, BTC_RF_A, 0x18, 0x3ff);
-
- /* Set RF channel */
- if (cent_freq == 2484)
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A,
- 0x18, 0x3ff, 0xe);
- else
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A,
- 0x18, 0x3ff, (cent_freq - 2412) / 5 +
- 1); /* WiFi TRx Mask on */
-
- /* Set RF mode = Rx, RF Gain = 0x8a0 */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x0,
- 0xfffff, 0x308a0);
-
- /* Set RF Rx filter corner */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e,
- 0xfffff, 0x3e4);
-
- /* Set TRx mask off */
- /* un-lock TRx Mask setup */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdd,
- 0x80, 0x1);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdf,
- 0x1, 0x1);
-
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1,
- 0xfffff, 0x0);
-
- flag = 3;
- break;
- case 3:
- memset(psd_scan->psd_report, 0,
- psd_scan->psd_point * sizeof(u32));
- start_p = psd_scan->psd_start_point +
- psd_scan->psd_start_base;
- stop_p = psd_scan->psd_stop_point +
- psd_scan->psd_start_base + 1;
-
- i = start_p;
-
- while (i < stop_p) {
- if (i >= points1)
- psd_report =
- halbtc8822b1ant_psd_getdata(
- btcoexist, i - points1);
- else
- psd_report =
- halbtc8822b1ant_psd_getdata(
- btcoexist, i);
-
- if (psd_report == 0)
- tmp = 0;
- else
- /* tmp = 20*log10((double)psd_report); */
- /* 20*log2(x)/log2(10), log2Base return theresult of the psd_report*100 */
- tmp = 6 * halbtc8822b1ant_psd_log2base(
- btcoexist, psd_report);
-
- n = i - psd_scan->psd_start_base;
- psd_scan->psd_report[n] = tmp;
- psd_rep1 = psd_scan->psd_report[n] / 100;
- psd_rep2 = psd_scan->psd_report[n] - psd_rep1 *
- 100;
-
- freq = ((cent_freq - 20) * 1000000 + n *
- delta_freq_per_point);
- freq1 = freq / 1000000;
- freq2 = freq / 1000 - freq1 * 1000;
-
- i++;
-
- k = 0;
-
- /* Add Delay between PSD point */
- while (1) {
- if (k++ > 20000)
- break;
- }
-
- }
-
- flag = 100;
- break;
- case 99: /* error */
-
- outloop = true;
- break;
- case 100: /* recovery */
-
- /* set 3-wire on */
- val = btcoexist->btc_read_4byte(btcoexist, 0x88c);
- val &= 0xffcfffff;
- btcoexist->btc_write_4byte(btcoexist, 0x88c, val);
-
- /* CCK on */
- val = btcoexist->btc_read_4byte(btcoexist, 0x800);
- val |= 0x01000000;
- btcoexist->btc_write_4byte(btcoexist, 0x800, val);
-
- /* PSD off */
- val = btcoexist->btc_read_4byte(btcoexist, 0x808);
- val &= 0xffbfffff;
- btcoexist->btc_write_4byte(btcoexist, 0x808, val);
-
- /* TRx Mask on */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1,
- 0xfffff, 0x780);
-
- /* lock TRx Mask setup */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdd,
- 0x80, 0x0);
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xdf,
- 0x1, 0x0);
-
- /* Set RF Rx filter corner */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e,
- 0xfffff, 0x0);
-
- /* restore WiFi original channel */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x18,
- 0x3ff, wifi_original_channel);
-
- outloop = true;
- break;
-
- }
-
- } while (!outloop);
-
-
-
- psd_scan->is_psd_running = false;
-
-
-}
-
-#if (BTC_COEX_OFFLOAD == 1)
-void halbtc8822b1ant_wifi_info_notify(IN struct btc_coexist *btcoexist)
-{
- u8 h2c_para[4] = {0};
- u8 opcode_ver = 0;
- u8 ap_num = 0;
- s32 wifi_rssi = 0;
- boolean wifi_busy = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
- btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, &ap_num);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- h2c_para[0] = ap_num; /* AP number */
- h2c_para[1] = (u8)wifi_busy; /* Busy */
- h2c_para[2] = (u8)wifi_rssi; /* RSSI */
-
- btcoexist->btc_coex_h2c_process(btcoexist, COL_OP_WIFI_INFO_NOTIFY,
- opcode_ver, &h2c_para[0], 3);
-}
-
-void halbtc8822b1ant_setManual(IN struct btc_coexist *btcoexist,
- IN boolean manual)
-{
- u8 h2c_para[4] = {0};
- u8 opcode_ver = 0;
- u8 set_type = 0;
-
- if (manual)
- set_type = 1;
- else
- set_type = 0;
-
- h2c_para[0] = set_type; /* set_type */
-
- btcoexist->btc_coex_h2c_process(btcoexist, COL_OP_SET_CONTROL, opcode_ver,
- &h2c_para[0], 1);
-}
-
-/* ************************************************************
- * work around function start with wa_halbtc8822b1ant_
- * ************************************************************
- * ************************************************************
- * extern function start with ex_halbtc8822b1ant_
- * ************************************************************ */
-
-void ex_halbtc8822b1ant_power_on_setting(IN struct btc_coexist *btcoexist)
-{}
-void ex_halbtc8822b1ant_pre_load_firmware(IN struct btc_coexist *btcoexist)
-{}
-void ex_halbtc8822b1ant_init_hw_config(IN struct btc_coexist *btcoexist,
- IN boolean wifi_only)
-{}
-void ex_halbtc8822b1ant_init_coex_dm(IN struct btc_coexist *btcoexist)
-{}
-void ex_halbtc8822b1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type)
-{
- u8 h2c_para[4] = {0};
- u8 opcode_ver = 0;
- u8 ips_notify = 0;
-
- if (BTC_IPS_ENTER == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], IPS ENTER notify\n");
- BTC_TRACE(trace_buf);
- ips_notify = 1;
- } else if (BTC_IPS_LEAVE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], IPS LEAVE notify\n");
- BTC_TRACE(trace_buf);
- }
-
- h2c_para[0] = ips_notify; /* IPS notify */
- h2c_para[1] = 0xff; /* LPS notify */
- h2c_para[2] = 0xff; /* RF state notify */
- h2c_para[3] = 0xff; /* pnp notify */
-
- btcoexist->btc_coex_h2c_process(btcoexist, COL_OP_WIFI_POWER_STATE_NOTIFY,
- opcode_ver, &h2c_para[0], 4);
-}
-void ex_halbtc8822b1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type)
-{
- u8 h2c_para[4] = {0};
- u8 opcode_ver = 0;
- u8 lps_notify = 0;
-
- if (BTC_LPS_ENABLE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], LPS ENABLE notify\n");
- BTC_TRACE(trace_buf);
- lps_notify = 1;
- } else if (BTC_LPS_DISABLE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], LPS DISABLE notify\n");
- BTC_TRACE(trace_buf);
- }
-
- h2c_para[0] = 0xff; /* IPS notify */
- h2c_para[1] = lps_notify; /* LPS notify */
- h2c_para[2] = 0xff; /* RF state notify */
- h2c_para[3] = 0xff; /* pnp notify */
-
- btcoexist->btc_coex_h2c_process(btcoexist, COL_OP_WIFI_POWER_STATE_NOTIFY,
- opcode_ver, &h2c_para[0], 4);
-}
-
-void ex_halbtc8822b1ant_scan_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- u8 h2c_para[4] = {0};
- u8 opcode_ver = 0;
- u8 scan_start = 0;
- boolean under_4way = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
- &under_4way);
- if (BTC_SCAN_START == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCAN START notify\n");
- BTC_TRACE(trace_buf);
- scan_start = 1;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCAN FINISH notify\n");
- BTC_TRACE(trace_buf);
- }
-
- h2c_para[0] = scan_start; /* scan notify */
- h2c_para[1] = 0xff; /* connect notify */
- h2c_para[2] = 0xff; /* specific packet notify */
- if (under_4way)
- h2c_para[3] = 1; /* under 4way progress */
- else
- h2c_para[3] = 0;
-
- btcoexist->btc_coex_h2c_process(btcoexist, COL_OP_WIFI_PROGRESS_NOTIFY,
- opcode_ver, &h2c_para[0], 4);
-}
-
-void ex_halbtc8822b1ant_connect_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- u8 h2c_para[4] = {0};
- u8 opcode_ver = 0;
- u8 connect_start = 0;
- boolean under_4way = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
- &under_4way);
- if (BTC_ASSOCIATE_START == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CONNECT START notify\n");
- BTC_TRACE(trace_buf);
- connect_start = 1;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CONNECT FINISH notify\n");
- BTC_TRACE(trace_buf);
- }
-
- h2c_para[0] = 0xff; /* scan notify */
- h2c_para[1] = connect_start; /* connect notify */
- h2c_para[2] = 0xff; /* specific packet notify */
- if (under_4way)
- h2c_para[3] = 1; /* under 4way progress */
- else
- h2c_para[3] = 0;
-
- btcoexist->btc_coex_h2c_process(btcoexist, COL_OP_WIFI_PROGRESS_NOTIFY,
- opcode_ver, &h2c_para[0], 4);
-}
-
-void ex_halbtc8822b1ant_media_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- u32 wifi_bw;
- u8 wifi_central_chnl;
- u8 h2c_para[5] = {0};
- u8 opcode_ver = 0;
- u8 port = 0, connected = 0, freq = 0, bandwidth = 0, iot_peer = 0;
- boolean wifi_under_5g = false;
-
- if (BTC_MEDIA_CONNECT == type)
- connected = 1;
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- bandwidth = (u8)wifi_bw;
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
- if (wifi_under_5g)
- freq = 1;
- else
- freq = 0;
- btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
- &wifi_central_chnl);
- btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer);
-
- h2c_para[0] = (connected << 4) |
- port; /* port need to be implemented in the future (p2p port, ...) */
- h2c_para[1] = (freq << 4) | bandwidth;
- h2c_para[2] = wifi_central_chnl;
- h2c_para[3] = iot_peer;
- btcoexist->btc_coex_h2c_process(btcoexist, COL_OP_WIFI_STATUS_NOTIFY,
- opcode_ver, &h2c_para[0], 4);
-}
-
-void ex_halbtc8822b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- u8 h2c_para[4] = {0};
- u8 opcode_ver = 0;
- u8 connect_start = 0;
- boolean under_4way = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
- &under_4way);
-
- h2c_para[0] = 0xff; /* scan notify */
- h2c_para[1] = 0xff; /* connect notify */
- h2c_para[2] = type; /* specific packet notify */
- if (under_4way)
- h2c_para[3] = 1; /* under 4way progress */
- else
- h2c_para[3] = 0;
-
- btcoexist->btc_coex_h2c_process(btcoexist, COL_OP_WIFI_PROGRESS_NOTIFY,
- opcode_ver, &h2c_para[0], 4);
-}
-
-void ex_halbtc8822b1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
- IN u8 *tmp_buf, IN u8 length)
-{}
-void ex_halbtc8822b1ant_rf_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- u8 h2c_para[4] = {0};
- u8 opcode_ver = 0;
- u8 rfstate_notify = 0;
-
- if (BTC_RF_ON == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RF is turned ON!!\n");
- BTC_TRACE(trace_buf);
- rfstate_notify = 1;
- } else if (BTC_RF_OFF == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RF is turned OFF!!\n");
- BTC_TRACE(trace_buf);
- }
-
- h2c_para[0] = 0xff; /* IPS notify */
- h2c_para[1] = 0xff; /* LPS notify */
- h2c_para[2] = rfstate_notify; /* RF state notify */
- h2c_para[3] = 0xff; /* pnp notify */
-
- btcoexist->btc_coex_h2c_process(btcoexist, COL_OP_WIFI_POWER_STATE_NOTIFY,
- opcode_ver, &h2c_para[0], 4);
-}
-
-void ex_halbtc8822b1ant_halt_notify(IN struct btc_coexist *btcoexist)
-{}
-void ex_halbtc8822b1ant_pnp_notify(IN struct btc_coexist *btcoexist,
- IN u8 pnp_state)
-{
- u8 h2c_para[4] = {0};
- u8 opcode_ver = 0;
- u8 pnp_notify = 0;
-
- if (BTC_WIFI_PNP_SLEEP == pnp_state) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Pnp notify to SLEEP\n");
- BTC_TRACE(trace_buf);
- pnp_notify = 1;
- } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Pnp notify to WAKE UP\n");
- BTC_TRACE(trace_buf);
- }
-
- h2c_para[0] = 0xff; /* IPS notify */
- h2c_para[1] = 0xff; /* LPS notify */
- h2c_para[2] = 0xff; /* RF state notify */
- h2c_para[3] = pnp_notify; /* pnp notify */
-
- btcoexist->btc_coex_h2c_process(btcoexist, COL_OP_WIFI_POWER_STATE_NOTIFY,
- opcode_ver, &h2c_para[0], 4);
-}
-
-void ex_halbtc8822b1ant_coex_dm_reset(IN struct btc_coexist *btcoexist)
-{}
-void ex_halbtc8822b1ant_periodical(IN struct btc_coexist *btcoexist)
-{
-
- halbtc8822b1ant_wifi_info_notify(btcoexist);
-}
-
-void ex_halbtc8822b1ant_display_coex_info(IN struct btc_coexist *btcoexist)
-{
- struct btc_board_info *board_info = &btcoexist->board_info;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- u8 *cli_buf = btcoexist->cli_buf;
- u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0;
- u16 u16tmp[4];
- u32 u32tmp[4];
- u32 fa_of_dm, fa_cck;
- u32 fw_ver = 0, bt_patch_ver = 0;
- static u8 pop_report_in_10s = 0;
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ============[BT Coexist info]============");
- CL_PRINTF(cli_buf);
-
- if (btcoexist->manual_control) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ============[Under Manual Control]============");
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ==========================================");
- CL_PRINTF(cli_buf);
- }
- if (btcoexist->stop_coex_dm) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ============[Coex is STOPPED]============");
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ==========================================");
- CL_PRINTF(cli_buf);
- }
-
- if (psd_scan->ant_det_try_count == 0) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d",
- "Ant PG Num/ Mech/ Pos",
- board_info->pg_ant_num, board_info->btdm_ant_num,
- board_info->btdm_ant_pos);
- CL_PRINTF(cli_buf);
- } else {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %d/ %d/ %d (%d/%d/%d)",
- "Ant PG Num/ Mech(Ant_Det)/ Pos",
- board_info->pg_ant_num, board_info->btdm_ant_num_by_ant_det,
- board_info->btdm_ant_pos,
- psd_scan->ant_det_try_count, psd_scan->ant_det_fail_count,
- psd_scan->ant_det_result);
- CL_PRINTF(cli_buf);
-
- if (board_info->btdm_ant_det_finish) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
- "Ant Det PSD Value",
- psd_scan->ant_det_peak_val);
- CL_PRINTF(cli_buf);
- }
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %d_%x/ 0x%x/ 0x%x(%d)",
- "CoexVer/ FwVer/ PatchVer",
- glcoex_ver_date_8822b_1ant, glcoex_ver_8822b_1ant, fw_ver,
- bt_patch_ver, bt_patch_ver);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ",
- "Wifi channel informed to BT",
- coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
- coex_dm->wifi_chnl_info[2]);
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s",
- "WifibHiPri/ Ccklock/ CckEverLock",
- (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"),
- (coex_sta->cck_lock ? "Yes" : "No"),
- (coex_sta->cck_ever_lock ? "Yes" : "No"));
- CL_PRINTF(cli_buf);
-
- /* wifi status */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Wifi Status]============");
- CL_PRINTF(cli_buf);
- btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[BT Status]============");
- CL_PRINTF(cli_buf);
-
- pop_report_in_10s++;
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d/ %d] ",
- "BT [status/ rssi/ retryCnt/ popCnt]",
- ((coex_sta->bt_disabled) ? ("disabled") : ((
- coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan")
- : ((BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
- coex_dm->bt_status) ? "non-connected idle" :
- ((BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)
- ? "connected-idle" : "busy")))),
- coex_sta->bt_rssi, coex_sta->bt_retry_cnt,
- coex_sta->pop_event_cnt);
- CL_PRINTF(cli_buf);
-
- if (pop_report_in_10s >= 5) {
- coex_sta->pop_event_cnt = 0;
- pop_report_in_10s = 0;
- }
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %d / %d / %d / %d / %d",
- "SCO/HID/PAN/A2DP/Hi-Pri",
- bt_link_info->sco_exist, bt_link_info->hid_exist,
- bt_link_info->pan_exist, bt_link_info->a2dp_exist,
- bt_link_info->bt_hi_pri_link_exist);
- CL_PRINTF(cli_buf);
-
- {
- bt_info_ext = coex_sta->bt_info_ext;
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s",
- "BT Role/A2DP rate",
- (bt_link_info->slave_role) ? "Slave" : "Master",
- (bt_info_ext & BIT(0)) ? "BR" : "EDR");
- CL_PRINTF(cli_buf);
- }
-
- /*bt info*/
- for (i = 0; i < BT_INFO_SRC_8822B_1ANT_MAX; i++) {
- if (coex_sta->bt_info_c2h_cnt[i]) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)",
- glbt_info_src_8822b_1ant[i],
- coex_sta->bt_info_c2h[i][0],
- coex_sta->bt_info_c2h[i][1],
- coex_sta->bt_info_c2h[i][2],
- coex_sta->bt_info_c2h[i][3],
- coex_sta->bt_info_c2h[i][4],
- coex_sta->bt_info_c2h[i][5],
- coex_sta->bt_info_c2h[i][6],
- coex_sta->bt_info_c2h_cnt[i]);
- CL_PRINTF(cli_buf);
- }
- }
-
-
- if (btcoexist->manual_control)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[mechanisms] (before Manual)============");
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[mechanisms]============");
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
- "SM[LowPenaltyRA]",
- coex_dm->cur_low_penalty_ra);
- CL_PRINTF(cli_buf);
-
- ps_tdma_case = coex_dm->cur_ps_tdma;
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (%s,%s)",
- "PS TDMA",
- coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],
- coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],
- coex_dm->ps_tdma_para[4], ps_tdma_case,
- (coex_dm->cur_ps_tdma_on ? "On" : "Off"),
- (coex_dm->auto_tdma_adjust ? "Adj" : "Fix"));
-
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
- "WL/BT Coex Table Type",
- coex_sta->coex_table_type);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
- u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
- "0x6c0/0x6c4/0x6c8(coexTable)",
- u32tmp[0], u32tmp[1], u32tmp[2]);
- CL_PRINTF(cli_buf);
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
- "0x778/0x6cc/IgnWlanAct",
- u8tmp[0], u32tmp[0], coex_dm->cur_ignore_wlan_act);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
- 0xa0);
- u32tmp[1] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
- 0xa4);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
- "LTE Coex Table W_L/B_L",
- u32tmp[0] & 0xffff, u32tmp[1] & 0xffff);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
- 0xa8);
- u32tmp[1] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
- 0xac);
- u32tmp[2] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
- 0xb0);
- u32tmp[3] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
- 0xb4);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
- "LTE Break Table W_L/B_L/L_W/L_B",
- u32tmp[0] & 0xffff, u32tmp[1] & 0xffff,
- u32tmp[2] & 0xffff, u32tmp[3] & 0xffff);
- CL_PRINTF(cli_buf);
-
- /* Hw setting */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Hw setting]============");
- CL_PRINTF(cli_buf);
-
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434);
- u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x",
- "0x430/0x434/0x42a/0x456",
- u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]);
- CL_PRINTF(cli_buf);
-
-
- u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %s",
- "LTE CoexOn/Path Ctrl Owner",
- (int)((u32tmp[0]&BIT(7)) >> 7), ((u8tmp[0]&BIT(2)) ? "WL" : "BT"));
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
- "LTE 3Wire/OPMode/UART/UARTMode",
- (int)((u32tmp[0]&BIT(6)) >> 6), (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4),
- (int)((u32tmp[0]&BIT(3)) >> 3),
- (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0))));
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %s",
- "GNT_WL_SWCtrl/GNT_BT_SWCtrl/Dbg",
- (int)((u32tmp[0]&BIT(12)) >> 12), (int)((u32tmp[0]&BIT(14)) >> 14),
- ((u8tmp[0]&BIT(3)) ? "On" : "Off"));
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
- "GNT_WL/GNT_BT/LTE_Busy/UART_Busy",
- (int)((u32tmp[0]&BIT(2)) >> 2), (int)((u32tmp[0]&BIT(3)) >> 3),
- (int)((u32tmp[0]&BIT(1)) >> 1), (int)(u32tmp[0]&BIT(0)));
- CL_PRINTF(cli_buf);
-
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
- "0x4c6[4]/0x40[5] (WL/BT PTA)",
- (int)((u8tmp[0] & BIT(4)) >> 4), (int)((u8tmp[1] & BIT(5)) >> 5));
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x953);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ %s",
- "0x550(bcn ctrl)/0x522/4-RxAGC",
- u32tmp[0], u8tmp[0], (u8tmp[1] & 0x2) ? "On" : "Off");
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xda0);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xda4);
- u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0xda8);
- u32tmp[3] = btcoexist->btc_read_4byte(btcoexist, 0xcf0);
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xa5b);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xa5c);
-
- fa_of_dm = ((u32tmp[0] & 0xffff0000) >> 16) + ((u32tmp[1] & 0xffff0000)
- >> 16) + (u32tmp[1] & 0xffff) + (u32tmp[2] & 0xffff) + \
- ((u32tmp[3] & 0xffff0000) >> 16) + (u32tmp[3] &
- 0xffff) ;
- fa_cck = (u8tmp[0] << 8) + u8tmp[1];
-
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xc50);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
- "0xc50/OFDM-CCA/OFDM-FA/CCK-FA",
- u32tmp[1] & 0xff, u32tmp[0] & 0xffff, fa_of_dm, fa_cck);
- CL_PRINTF(cli_buf);
-
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
- "CRC_OK CCK/11g/11n/11n-Agg",
- coex_sta->crc_ok_cck, coex_sta->crc_ok_11g,
- coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_agg);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
- "CRC_Err CCK/11g/11n/11n-Agg",
- coex_sta->crc_err_cck, coex_sta->crc_err_11g,
- coex_sta->crc_err_11n, coex_sta->crc_err_11n_agg);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
- "0x770(high-pri rx/tx)",
- coex_sta->high_priority_rx, coex_sta->high_priority_tx);
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
- "0x774(low-pri rx/tx)",
- coex_sta->low_priority_rx, coex_sta->low_priority_tx);
- CL_PRINTF(cli_buf);
-#if (BT_AUTO_REPORT_ONLY_8822B_1ANT == 1)
- /* halbtc8822b1ant_monitor_bt_ctr(btcoexist); */
-#endif
- btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
-}
-void ex_halbtc8822b1ant_antenna_detection(IN struct btc_coexist *btcoexist,
- IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
-{}
-void ex_halbtc8822b1ant_display_ant_detection(IN struct btc_coexist *btcoexist)
-{}
-void ex_halbtc8822b1ant_dbg_control(IN struct btc_coexist *btcoexist,
- IN u8 op_code, IN u8 op_len, IN u8 *pdata)
-{
- switch (op_code) {
- case BTC_DBG_SET_COEX_MANUAL_CTRL: {
- boolean manual = (boolean)*pdata;
-
- halbtc8822b1ant_setManual(btcoexist, manual);
- }
- break;
- default:
- break;
- }
-}
-
-#else
-void ex_halbtc8822b1ant_power_on_setting(IN struct btc_coexist *btcoexist)
-{
- struct btc_board_info *board_info = &btcoexist->board_info;
- u8 u8tmp = 0x0;
- u16 u16tmp = 0x0;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx Execute 8822b 1-Ant PowerOn Setting!! xxxxxxxxxxxxxxxx\n");
- BTC_TRACE(trace_buf);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "Ant Det Finish = %s, Ant Det Number = %d\n",
- board_info->btdm_ant_det_finish ? "Yes" : "No",
- board_info->btdm_ant_num_by_ant_det);
- BTC_TRACE(trace_buf);
-
- btcoexist->stop_coex_dm = true;
-
- /* enable BB, REG_SYS_FUNC_EN such that we can write 0x948 correctly. */
- u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2);
- btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1));
-
- /* set Path control owner to WiFi */
- halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist,
- BT_8822B_1ANT_PCO_WLSIDE);
-
- /* set GNT_BT to high */
- halbtc8822b1ant_ltecoex_set_gnt_bt(btcoexist,
- BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_1ANT_GNT_CTRL_BY_SW,
- BT_8822B_1ANT_SIG_STA_SET_TO_HIGH);
- /* Set GNT_WL to low */
- halbtc8822b1ant_ltecoex_set_gnt_wl(btcoexist,
- BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
- BT_8822B_1ANT_GNT_CTRL_BY_SW,
- BT_8822B_1ANT_SIG_STA_SET_TO_LOW);
-
- /* set WLAN_ACT = 0 */
- //btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4);
-
- /* SD1 Chunchu red x issue */
- btcoexist->btc_write_1byte(btcoexist, 0xff1a, 0x0);
-
- halbtc8822b1ant_enable_gnt_to_gpio(btcoexist, TRUE);
-
- /* */
- /* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */
- /* Local setting bit define */
- /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */
- /* BIT1: "0" for internal switch; "1" for external switch */
- /* BIT2: "0" for one antenna; "1" for two antenna */
- /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */
-
- u8tmp = 0;
- board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;
-
- if (btcoexist->chip_interface == BTC_INTF_USB)
- btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp);
- else if (btcoexist->chip_interface == BTC_INTF_SDIO)
- btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, u8tmp);
-
- BTC_TRACE(trace_buf);
-
-
-}
-
-void ex_halbtc8822b1ant_pre_load_firmware(IN struct btc_coexist *btcoexist)
-{
-}
-
-void ex_halbtc8822b1ant_init_hw_config(IN struct btc_coexist *btcoexist,
- IN boolean wifi_only)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (ini hw config) **********\n");
-
- halbtc8822b1ant_init_hw_config(btcoexist, true, wifi_only);
- btcoexist->stop_coex_dm = false;
-}
-
-void ex_halbtc8822b1ant_init_coex_dm(IN struct btc_coexist *btcoexist)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Coex Mechanism Init!!\n");
- BTC_TRACE(trace_buf);
-
- btcoexist->stop_coex_dm = false;
-
- halbtc8822b1ant_init_coex_dm(btcoexist);
-
- halbtc8822b1ant_query_bt_info(btcoexist);
-}
-
-void ex_halbtc8822b1ant_display_coex_info(IN struct btc_coexist *btcoexist)
-{
-
- struct btc_board_info *board_info = &btcoexist->board_info;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- u8 *cli_buf = btcoexist->cli_buf;
- u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0;
- u16 u16tmp[4];
- u32 u32tmp[4];
- u32 fa_of_dm, fa_cck;
- u32 fw_ver = 0, bt_patch_ver = 0;
- static u8 pop_report_in_10s = 0;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (display coexinfo) **********\n");
- BTC_TRACE(trace_buf);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** displaycoexinfostart, 0xcb4/0xcbd = 0x%x/0x%x\n",
- btcoexist->btc_read_1byte(btcoexist, 0xcb4),
- btcoexist->btc_read_1byte(btcoexist, 0xcbd));
- BTC_TRACE(trace_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ============[BT Coexist info]============");
- CL_PRINTF(cli_buf);
-
- if (btcoexist->manual_control) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ============[Under Manual Control]============");
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ==========================================");
- CL_PRINTF(cli_buf);
- }
-
- if (btcoexist->stop_coex_dm) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ============[Coex is STOPPED]============");
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ==========================================");
- CL_PRINTF(cli_buf);
- }
-
- if (psd_scan->ant_det_try_count == 0) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
- "Ant PG Num/ Mech/ Pos/ RFE",
- board_info->pg_ant_num, board_info->btdm_ant_num,
- board_info->btdm_ant_pos,
- rfe_type->rfe_module_type);
- CL_PRINTF(cli_buf);
- } else {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %d/ %d/ %d/ %d (%d/%d/%d)",
- "Ant PG Num/ Mech(Ant_Det)/ Pos/ RFE",
- board_info->pg_ant_num, board_info->btdm_ant_num_by_ant_det,
- board_info->btdm_ant_pos,
- rfe_type->rfe_module_type,
- psd_scan->ant_det_try_count, psd_scan->ant_det_fail_count,
- psd_scan->ant_det_result);
- CL_PRINTF(cli_buf);
-
- if (board_info->btdm_ant_det_finish) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
- "Ant Det PSD Value",
- psd_scan->ant_det_peak_val);
- CL_PRINTF(cli_buf);
- }
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %d_%x/ 0x%x/ 0x%x(%d)/ %c",
- "Version Coex/ Fw/ Patch/ Cut",
- glcoex_ver_date_8822b_1ant, glcoex_ver_8822b_1ant, fw_ver,
- bt_patch_ver, bt_patch_ver, coex_sta->cut_version + 65);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ",
- "Wifi channel informed to BT",
- coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
- coex_dm->wifi_chnl_info[2]);
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s",
- "WifibHiPri/ Ccklock/ CckEverLock",
- (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"),
- (coex_sta->cck_lock ? "Yes" : "No"),
- (coex_sta->cck_ever_lock ? "Yes" : "No"));
- CL_PRINTF(cli_buf);
-
- /* wifi status */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Wifi Status]============");
- CL_PRINTF(cli_buf);
- btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[BT Status]============");
- CL_PRINTF(cli_buf);
-
- pop_report_in_10s++;
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d/ %d] ",
- "BT [status/ rssi/ retryCnt/ popCnt]",
- ((coex_sta->bt_disabled) ? ("disabled") : ((
- coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan")
- : ((BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
- coex_dm->bt_status) ? "non-connected idle" :
- ((BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)
- ? "connected-idle" : "busy")))),
- coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt,
- coex_sta->pop_event_cnt);
- CL_PRINTF(cli_buf);
- /*bt rssi */
- /*bt pop_even_cnt : bt retry*/
-
- if (pop_report_in_10s >= 5) {
- coex_sta->pop_event_cnt = 0;
- pop_report_in_10s = 0;
- }
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %d / %d / %d / %d / %d",
- "SCO/HID/PAN/A2DP/Hi-Pri",
- bt_link_info->sco_exist, bt_link_info->hid_exist,
- bt_link_info->pan_exist, bt_link_info->a2dp_exist,
- bt_link_info->bt_hi_pri_link_exist);
- CL_PRINTF(cli_buf);
-
- {
- bt_info_ext = coex_sta->bt_info_ext;
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %s / %d/ %x/ %04x",
- "Role/A2DP Rate/Bitpool/Feature/Ver",
- ((bt_link_info->slave_role) ? "Slave" : "Master"),
- (bt_info_ext & BIT(0)) ? "BR" : "EDR", coex_sta->a2dp_bit_pool,
- coex_sta->bt_coex_supported_feature,
- coex_sta->bt_coex_supported_version);
- CL_PRINTF(cli_buf);
- }
-
- /*bt info*/
- for (i = 0; i < BT_INFO_SRC_8822B_1ANT_MAX; i++) {
- if (coex_sta->bt_info_c2h_cnt[i]) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)",
- glbt_info_src_8822b_1ant[i],
- coex_sta->bt_info_c2h[i][0],
- coex_sta->bt_info_c2h[i][1],
- coex_sta->bt_info_c2h[i][2],
- coex_sta->bt_info_c2h[i][3],
- coex_sta->bt_info_c2h[i][4],
- coex_sta->bt_info_c2h[i][5],
- coex_sta->bt_info_c2h[i][6],
- coex_sta->bt_info_c2h_cnt[i]);
- CL_PRINTF(cli_buf);
- }
- }
-
-
- if (btcoexist->manual_control)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[mechanisms] (before Manual)============");
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[mechanisms]============");
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
- "SM[LowPenaltyRA]",
- coex_dm->cur_low_penalty_ra);
- CL_PRINTF(cli_buf);
-
- /*(ps)tdma*/
- ps_tdma_case = coex_dm->cur_ps_tdma;
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (%s,%s)",
- "PS TDMA",
- coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],
- coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],
- coex_dm->ps_tdma_para[4], ps_tdma_case,
- (coex_dm->cur_ps_tdma_on ? "On" : "Off"),
- (coex_dm->auto_tdma_adjust ? "Adj" : "Fix"));
-
- CL_PRINTF(cli_buf);
-
- /*coex table type*/
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
- "WL/BT Coex Table Type",
- coex_sta->coex_table_type);
- CL_PRINTF(cli_buf);
-
- /*coex table :0x6c0 0x6c4 , break table: 0x6c8*/
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
- u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
- "0x6c0/0x6c4/0x6c8(coexTable)",
- u32tmp[0], u32tmp[1], u32tmp[2]);
- CL_PRINTF(cli_buf);
-
- /*PTA : 0x778=1/3/d , WL BA,RTS,CTS :0x6cc H/L pri */
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
- "0x778/0x6cc/IgnWlanAct",
- u8tmp[0], u32tmp[0], coex_dm->cur_ignore_wlan_act);
- CL_PRINTF(cli_buf);
-
-
- /*LTE : WL/LTE coex table : 0xa0 */
-
- u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
- 0xa0);
-
- /*LTE : BT/LTE coex table : 0xa4 */
- u32tmp[1] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
- 0xa4);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
- "LTE Coex Table W_L/B_L",
- u32tmp[0] & 0xffff, u32tmp[1] & 0xffff);
- CL_PRINTF(cli_buf);
-
- /*LTE : WL/LTE break table : 0xa8 */
- u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
- 0xa8);
- /*LTE : WL/LTE break table : 0xac */
- u32tmp[1] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
- 0xac);
- /*LTE : LTE/WL break table : 0xb0 */
- u32tmp[2] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
- 0xb0);
- /*LTE : LTE/BT break table : 0xb4 */
- u32tmp[3] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
- 0xb4);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
- "LTE Break Table W_L/B_L/L_W/L_B",
- u32tmp[0] & 0xffff, u32tmp[1] & 0xffff,
- u32tmp[2] & 0xffff, u32tmp[3] & 0xffff);
- CL_PRINTF(cli_buf);
-
- /* Hw setting */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Hw setting]============");
- CL_PRINTF(cli_buf);
-
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434);
- u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x",
- "0x430/0x434/0x42a/0x456",
- u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]);
- CL_PRINTF(cli_buf);
-
- /*ANT setting*/
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xcb4);
- u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0xcbd);
- u8tmp[3] = btcoexist->btc_read_1byte(btcoexist, 0x1991);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
- "0xcb4/0xcbd/0x1991",
- u8tmp[1], u8tmp[2], u8tmp[3]);
- CL_PRINTF(cli_buf);
-
- /*LTE on/off , Path ctrl owner*/
- /*sy add*/
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x64);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
- "0x73/ 0x4c/ 0x64[0]", u8tmp[0], (u32tmp[0] & ( BIT(24) | BIT(23) )) >> 23, u8tmp[1]&0x1);
- CL_PRINTF(cli_buf);
-
-
- u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %s",
- "LTE CoexOn/Path Ctrl Owner",
- (int)((u32tmp[0]&BIT(7)) >> 7), ((u8tmp[0]&BIT(2)) ? "WL" : "BT"));
- CL_PRINTF(cli_buf);
-
- /*LTE mode*/
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
- "LTE 3Wire/OPMode/UART/UARTMode",
- (int)((u32tmp[0]&BIT(6)) >> 6), (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4),
- (int)((u32tmp[0]&BIT(3)) >> 3),
- (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0))));
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %s",
- "GNT_WL_SWCtrl/GNT_BT_SWCtrl/Dbg",
- (int)((u32tmp[0]&BIT(12)) >> 12), (int)((u32tmp[0]&BIT(14)) >> 14),
- ((u8tmp[0]&BIT(3)) ? "On" : "Off"));
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
- "GNT_WL/GNT_BT/LTE_Busy/UART_Busy",
- (int)((u32tmp[0]&BIT(2)) >> 2), (int)((u32tmp[0]&BIT(3)) >> 3),
- (int)((u32tmp[0]&BIT(1)) >> 1), (int)(u32tmp[0]&BIT(0)));
- CL_PRINTF(cli_buf);
-
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
- "0x4c6[4]/0x40[5] (WL/BT PTA)",
- (int)((u8tmp[0] & BIT(4)) >> 4), (int)((u8tmp[1] & BIT(5)) >> 5));
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x974);
- u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0xc50);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
- "0x550(bcn ctrl)/0x522/0x974/0xc50",
- u32tmp[0], u8tmp[0], u8tmp[1], u8tmp[2]);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xf48);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xf4c);
- u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0xf08);
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xa5c);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xa5d);
-
- fa_of_dm = (u32tmp[0] & 0xffff) + (u32tmp[1] & 0xffff);
-
- fa_cck = (u8tmp[0] << 8) + u8tmp[1];
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
- "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA",
- u32tmp[2] & 0xffff, fa_cck, ((u32tmp[2] & 0xffff0000) >> 16), fa_of_dm);
- CL_PRINTF(cli_buf);
-
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
- "CRC_OK CCK/11g/11n/11ac",
- coex_sta->crc_ok_cck, coex_sta->crc_ok_11g,
- coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_agg);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
- "CRC_Err CCK/11g/11n/11ac",
- coex_sta->crc_err_cck, coex_sta->crc_err_11g,
- coex_sta->crc_err_11n, coex_sta->crc_err_11n_agg);
- CL_PRINTF(cli_buf);
-
- /*0x770:bt high pri trx*/
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
- "0x770(high-pri rx/tx)",
- coex_sta->high_priority_rx, coex_sta->high_priority_tx);
- CL_PRINTF(cli_buf);
- /*0x774:bt low pri trx*/
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
- "0x774(low-pri rx/tx)",
- coex_sta->low_priority_rx, coex_sta->low_priority_tx);
- CL_PRINTF(cli_buf);
-
- halbtc8822b1ant_read_score_board(btcoexist, &u16tmp[0]);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %04x",
- "ScoreBoard[14:0] (from BT)", u16tmp[0]);
-
- btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** displaycoexinfo end, 0xcb4/0xcbd = 0x%x/0x%x\n",
- btcoexist->btc_read_1byte(btcoexist, 0xcb4),
- btcoexist->btc_read_1byte(btcoexist, 0xcbd));
- BTC_TRACE(trace_buf);
-}
-
-
-void ex_halbtc8822b1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type)
-{
-
- if (btcoexist->manual_control || btcoexist->stop_coex_dm)
- return;
-
-
- if (BTC_IPS_ENTER == type) {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], IPS ENTER notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_ips = true;
-
- halbtc8822b1ant_post_activestate_to_bt(btcoexist, false);
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
-
- halbtc8822b1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_AUTO,
- FORCE_EXEC,
- BT_8822B_1ANT_PHASE_WLAN_OFF);
-
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
- } else if (BTC_IPS_LEAVE == type) {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], IPS LEAVE notify\n");
- BTC_TRACE(trace_buf);
-
- halbtc8822b1ant_post_activestate_to_bt(btcoexist, true);
-
- /*leave IPS : run ini hw config (exclude wifi only)*/
- halbtc8822b1ant_init_hw_config(btcoexist, false, false);
- /*sw all off*/
- halbtc8822b1ant_init_coex_dm(btcoexist);
- /*leave IPS : Query bt info*/
- halbtc8822b1ant_query_bt_info(btcoexist);
-
- coex_sta->under_ips = false;
- }
-}
-
-void ex_halbtc8822b1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type)
-{
- if (btcoexist->manual_control || btcoexist->stop_coex_dm)
- return;
-
- if (BTC_LPS_ENABLE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], LPS ENABLE notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_lps = true;
-
- if (coex_sta->force_lps_on == true) { /* LPS No-32K */
- /* Write WL "Active" in Score-board for PS-TDMA */
- halbtc8822b1ant_post_activestate_to_bt(btcoexist, true);
-
- } else { /* LPS-32K, need check if this h2c 0x71 can work?? (2015/08/28) */
- /* Write WL "Non-Active" in Score-board for Native-PS */
- halbtc8822b1ant_post_activestate_to_bt(btcoexist, false);
-
- }
- } else if (BTC_LPS_DISABLE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], LPS DISABLE notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_lps = false;
-
- halbtc8822b1ant_post_activestate_to_bt(btcoexist, true);
- }
-}
-
-
-void ex_halbtc8822b1ant_scan_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- boolean wifi_connected = false;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCAN notify()\n");
- BTC_TRACE(trace_buf);
-
- halbtc8822b1ant_post_activestate_to_bt(btcoexist, true);
-
- if (btcoexist->manual_control ||
- btcoexist->stop_coex_dm ||
- coex_sta->bt_disabled)
- return;
-
- if (BTC_SCAN_START == type)
- return;
-
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
-
-
- if (BTC_SCAN_START_2G == type) {
- coex_sta->wifi_is_high_pri_task = true;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], 2g SCAN START notify\n");
- BTC_TRACE(trace_buf);
-
-
- if (!wifi_connected) /* non-connected scan */
- halbtc8822b1ant_action_wifi_not_connected_scan(
- btcoexist);
- else /* wifi is connected */
- halbtc8822b1ant_action_wifi_connected_scan(btcoexist);
-
- } else {
- coex_sta->wifi_is_high_pri_task = false;
-
- /*WL scan finish , then get and update sacn ap numbers */
- btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
- &coex_sta->scan_ap_num);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCAN FINISH notify (Scan-AP = %d)\n", coex_sta->scan_ap_num);
- BTC_TRACE(trace_buf);
-
- if (!wifi_connected) /* non-connected scan */
- halbtc8822b1ant_action_wifi_not_connected(btcoexist);
- else
- halbtc8822b1ant_action_wifi_connected(btcoexist);
- }
-
-
-}
-
-void ex_halbtc8822b1ant_switchband_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
-
- boolean wifi_connected = false;
-
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (switchband_notify) **********\n");
- BTC_TRACE(trace_buf);
-
- if (btcoexist->manual_control ||
- btcoexist->stop_coex_dm)
- return;
-
-
- if(type == BTC_SWITCH_TO_5G) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (switchband_notify BTC_SWITCH_TO_5G) **********\n");
- BTC_TRACE(trace_buf);
-
- halbtc8822b1ant_action_wifi_under5g(btcoexist);
- return;
- } else if (type == BTC_SWITCH_TO_24G_NoForScan) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (switchband_notify BTC_SWITCH_TO_2G (no for scan)) **********\n");
- BTC_TRACE(trace_buf);
-
- halbtc8822b1ant_run_coexist_mechanism(btcoexist);
-
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (switchband_notify BTC_SWITCH_TO_2G) **********\n");
- BTC_TRACE(trace_buf);
-
- ex_halbtc8822b1ant_scan_notify(btcoexist,
- BTC_SCAN_START_2G);
- }
-
-}
-
-void ex_halbtc8822b1ant_connect_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- boolean wifi_connected = false;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (connect notify) **********\n");
- BTC_TRACE(trace_buf);
-
- halbtc8822b1ant_post_activestate_to_bt(btcoexist, true);
-
-
- if (btcoexist->manual_control ||
- btcoexist->stop_coex_dm ||
- coex_sta->bt_disabled)
- return;
-
-
- if ( (BTC_ASSOCIATE_5G_START == type) || (BTC_ASSOCIATE_5G_FINISH== type)) {
-
- if (BTC_ASSOCIATE_5G_START== type) {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (5G associate start notify) **********\n");
- BTC_TRACE(trace_buf);
-
- halbtc8822b1ant_action_wifi_under5g(btcoexist);
-
- } else if (BTC_ASSOCIATE_5G_FINISH == type) {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (5G associate finish notify) **********\n");
- BTC_TRACE(trace_buf);
-
- }
-
- return;
-
-}
-
-
- if (BTC_ASSOCIATE_START == type) {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], 2G CONNECT START notify\n");
- BTC_TRACE(trace_buf);
-
- coex_sta->wifi_is_high_pri_task = true;
-
- halbtc8822b1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_AUTO,
- FORCE_EXEC,
- BT_8822B_1ANT_PHASE_2G_RUNTIME);
-
- coex_dm->arp_cnt = 0;
-
- halbtc8822b1ant_action_wifi_not_connected_asso_auth(btcoexist);
-
- } else {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], 2G CONNECT Finish notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->wifi_is_high_pri_task = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
-
- if (!wifi_connected) /* non-connected scan */
- halbtc8822b1ant_action_wifi_not_connected(btcoexist);
- else
- halbtc8822b1ant_action_wifi_connected(btcoexist);
- }
-
-}
-
-void ex_halbtc8822b1ant_media_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- boolean wifi_under_b_mode = false;
- boolean wifi_under_5g = false;
- u32 cnt_bt_cal_chk = 0;
- boolean is_in_mp_mode = false;
- u8 u8tmp = 0;
- u32 u32tmp1 = 0, u32tmp2 = 0;
-
-
- if (btcoexist->manual_control ||
- btcoexist->stop_coex_dm ||
- coex_sta->bt_disabled)
- return;
-
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
- if(wifi_under_5g)
- {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], 5g media notify \n");
- BTC_TRACE(trace_buf);
-
- halbtc8822b1ant_post_activestate_to_bt(btcoexist, true);
-
- halbtc8822b1ant_action_wifi_under5g(btcoexist);
- return;
- }
-
-
-
- if (BTC_MEDIA_CONNECT == type) {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], 2g media connect notify");
- BTC_TRACE(trace_buf);
-
- halbtc8822b1ant_post_activestate_to_bt(btcoexist, true);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
- &wifi_under_b_mode);
-
- /* Set CCK Tx/Rx high Pri except 11b mode */
- if (wifi_under_b_mode) {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (media status notity under b mode) **********\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_write_1byte(btcoexist, 0x6cd,
- 0x00); /* CCK Tx */
- btcoexist->btc_write_1byte(btcoexist, 0x6cf,
- 0x00); /* CCK Rx */
- } else {
- /* btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x10); */ /*CCK Tx */
- /* btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x10); */ /*CCK Rx */
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (media status notity not under b mode) **********\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_write_1byte(btcoexist, 0x6cd,
- 0x00); /* CCK Tx */
- btcoexist->btc_write_1byte(btcoexist, 0x6cf,
- 0x10); /* CCK Rx */
- }
-
- coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist,
- 0x430);
- coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist,
- 0x434);
- coex_dm->backup_retry_limit = btcoexist->btc_read_2byte(
- btcoexist, 0x42a);
- coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte(
- btcoexist, 0x456);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], 2g media disconnect notify\n");
- BTC_TRACE(trace_buf);
- coex_dm->arp_cnt = 0;
-
- halbtc8822b1ant_post_activestate_to_bt(btcoexist, false);
-
- btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */
- btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */
-
- coex_sta->cck_ever_lock = false;
- }
-
- halbtc8822b1ant_update_wifi_channel_info(btcoexist, type);
-
-}
-
-void ex_halbtc8822b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- boolean under_4way = false, wifi_under_5g = false;
-
- if (btcoexist->manual_control ||
- btcoexist->stop_coex_dm ||
- coex_sta->bt_disabled)
- return;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
- if(wifi_under_5g)
- {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], 5g special packet notify \n");
- BTC_TRACE(trace_buf);
-
- halbtc8822b1ant_action_wifi_under5g(btcoexist);
- return;
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
- &under_4way);
-
- if (under_4way) {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], specific Packet ---- under_4way!!\n");
- BTC_TRACE(trace_buf);
-
- coex_sta->wifi_is_high_pri_task = true;
- coex_sta->specific_pkt_period_cnt = 2;
- } else if (BTC_PACKET_ARP == type) {
-
- coex_dm->arp_cnt++;
-
- if (coex_sta->wifi_is_high_pri_task) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], specific Packet ARP notify -cnt = %d\n", coex_dm->arp_cnt);
- BTC_TRACE(trace_buf);
- }
-
- } else {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n", type);
- BTC_TRACE(trace_buf);
-
- coex_sta->wifi_is_high_pri_task = true;
- coex_sta->specific_pkt_period_cnt = 2;
- }
-
- if (coex_sta->wifi_is_high_pri_task)
- halbtc8822b1ant_action_wifi_connected_specific_packet(btcoexist);
-
-}
-
-void ex_halbtc8822b1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
- IN u8 *tmp_buf, IN u8 length)
-{
- u8 bt_info = 0;
- u8 i, rsp_source = 0;
- boolean bt_busy = false;
- boolean wifi_connected = false;
- boolean wifi_under_5g = false;
-
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
-
- coex_sta->c2h_bt_info_req_sent = false;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (BtInfo Notify) **********\n" );
- BTC_TRACE(trace_buf);
-
- rsp_source = tmp_buf[0] & 0xf;
- if (rsp_source >= BT_INFO_SRC_8822B_1ANT_MAX)
- rsp_source = BT_INFO_SRC_8822B_1ANT_WIFI_FW;
- coex_sta->bt_info_c2h_cnt[rsp_source]++;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source,
- length);
- BTC_TRACE(trace_buf);
-
- for (i = 0; i < length; i++) {
- coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
- if (i == 1)
- bt_info = tmp_buf[i];
- if (i == length - 1) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n",
- tmp_buf[i]);
- BTC_TRACE(trace_buf);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ",
- tmp_buf[i]);
- BTC_TRACE(trace_buf);
- }
- }
-
-
- if (BT_INFO_SRC_8822B_1ANT_WIFI_FW != rsp_source) {
-
- /* if 0xff, it means BT is under WHCK test */
- if (bt_info == 0xff)
- coex_sta->bt_whck_test = true;
- else
- coex_sta->bt_whck_test = false;
-
- coex_sta->bt_retry_cnt = /* [3:0] */
- coex_sta->bt_info_c2h[rsp_source][2] & 0xf;
-
- if (coex_sta->bt_retry_cnt >= 1)
- coex_sta->pop_event_cnt++;
-
- if (coex_sta->bt_info_c2h[rsp_source][2] & 0x20)
- coex_sta->c2h_bt_page = true;
- else
- coex_sta->c2h_bt_page = false;
-
- if (coex_sta->bt_info_c2h[rsp_source][2] & 0x80)
- coex_sta->bt_create_connection = true;
- else
- coex_sta->bt_create_connection = false;
-
- /* unit: %, value-100 to translate to unit: dBm */
- coex_sta->bt_rssi = coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10;
-
- /* coex_sta->bt_info_c2h[rsp_source][3] * 2 - 90; */
-
- if ((coex_sta->bt_info_c2h[rsp_source][1] & 0x49) == 0x49) {
- coex_sta->a2dp_bit_pool =
- coex_sta->bt_info_c2h[rsp_source][6];
- } else
- coex_sta->a2dp_bit_pool = 0;
-
- if (coex_sta->bt_info_c2h[rsp_source][1] & 0x9)
- coex_sta->acl_busy = true;
- else
- coex_sta->acl_busy = false;
-
- coex_sta->bt_info_ext =
- coex_sta->bt_info_c2h[rsp_source][4];
-
- /* Here we need to resend some wifi info to BT */
- /* because bt is reset and loss of the info. */
-
- if ((!btcoexist->manual_control) && (!btcoexist->stop_coex_dm)) {
-
- /* Re-Init */
- if (coex_sta->bt_info_ext & BIT(1)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- if (wifi_connected)
- halbtc8822b1ant_update_wifi_channel_info(btcoexist,
- BTC_MEDIA_CONNECT);
- else
- halbtc8822b1ant_update_wifi_channel_info(btcoexist,
- BTC_MEDIA_DISCONNECT);
- }
-
- /* If Ignore_WLanAct && not SetUp_Link */
- if ((coex_sta->bt_info_ext & BIT(3)) && (!(coex_sta->bt_info_ext & BIT(2)))) {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n");
- BTC_TRACE(trace_buf);
- halbtc8822b1ant_ignore_wlan_act(btcoexist,
- FORCE_EXEC, false);
- }
- }
- /* check BIT2 first ==> check if bt is under inquiry or page scan */
- if (bt_info & BT_INFO_8822B_1ANT_B_INQ_PAGE)
- coex_sta->c2h_bt_inquiry_page = true;
- else
- coex_sta->c2h_bt_inquiry_page = false;
- }
-
- coex_sta->num_of_profile = 0;
-
- /* set link exist status */
- if (!(bt_info & BT_INFO_8822B_1ANT_B_CONNECTION)) {
- coex_sta->bt_link_exist = false;
- coex_sta->pan_exist = false;
- coex_sta->a2dp_exist = false;
- coex_sta->hid_exist = false;
- coex_sta->sco_exist = false;
-
- coex_sta->bt_hi_pri_link_exist = false;
- } else { /* connection exists */
- coex_sta->bt_link_exist = true;
- if (bt_info & BT_INFO_8822B_1ANT_B_FTP) {
- coex_sta->pan_exist = true;
- coex_sta->num_of_profile++;
- } else
- coex_sta->pan_exist = false;
- if (bt_info & BT_INFO_8822B_1ANT_B_A2DP) {
- coex_sta->a2dp_exist = true;
- coex_sta->num_of_profile++;
- } else
- coex_sta->a2dp_exist = false;
- if (bt_info & BT_INFO_8822B_1ANT_B_HID) {
- coex_sta->hid_exist = true;
- coex_sta->num_of_profile++;
- } else
- coex_sta->hid_exist = false;
- if (bt_info & BT_INFO_8822B_1ANT_B_SCO_ESCO) {
- coex_sta->sco_exist = true;
- coex_sta->num_of_profile++;
- } else
- coex_sta->sco_exist = false;
-
- }
-
- halbtc8822b1ant_update_bt_link_info(btcoexist);
-
- bt_info = bt_info &
- 0x1f; /* mask profile bit for connect-ilde identification ( for CSR case: A2DP idle --> 0x41) */
-
- if (!(bt_info & BT_INFO_8822B_1ANT_B_CONNECTION)) {
- coex_dm->bt_status = BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n");
- BTC_TRACE(trace_buf);
- } else if (bt_info ==
- BT_INFO_8822B_1ANT_B_CONNECTION) { /* connection exists but no busy */
- coex_dm->bt_status = BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n");
- BTC_TRACE(trace_buf);
- } else if ((bt_info & BT_INFO_8822B_1ANT_B_SCO_ESCO) ||
- (bt_info & BT_INFO_8822B_1ANT_B_SCO_BUSY)) {
- coex_dm->bt_status = BT_8822B_1ANT_BT_STATUS_SCO_BUSY;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n");
- BTC_TRACE(trace_buf);
- } else if (bt_info & BT_INFO_8822B_1ANT_B_ACL_BUSY) {
- if (BT_8822B_1ANT_BT_STATUS_ACL_BUSY != coex_dm->bt_status)
- coex_dm->bt_status = BT_8822B_1ANT_BT_STATUS_ACL_BUSY;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n");
- BTC_TRACE(trace_buf);
- } else {
- coex_dm->bt_status = BT_8822B_1ANT_BT_STATUS_MAX;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n");
- BTC_TRACE(trace_buf);
- }
-
- if ((BT_8822B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
- (BT_8822B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
- (BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status))
- bt_busy = true;
- else
- bt_busy = false;
-
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
-
- halbtc8822b1ant_run_coexist_mechanism(btcoexist);
-}
-
-void ex_halbtc8822b1ant_rf_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n");
- BTC_TRACE(trace_buf);
-
- if (BTC_RF_ON == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RF is turned ON!!\n");
- BTC_TRACE(trace_buf);
- btcoexist->stop_coex_dm = false;
-
- halbtc8822b1ant_post_activestate_to_bt(btcoexist, true);
- halbtc8822b1ant_post_onoffstate_to_bt(btcoexist, true);
- } else if (BTC_RF_OFF == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RF is turned OFF!!\n");
- BTC_TRACE(trace_buf);
-
- halbtc8822b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
-
- halbtc8822b1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_AUTO,
- FORCE_EXEC,
- BT_8822B_1ANT_PHASE_WLAN_OFF);
-
- halbtc8822b1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
-
- btcoexist->stop_coex_dm = true;
-
- halbtc8822b1ant_post_activestate_to_bt(btcoexist, false);
- halbtc8822b1ant_post_onoffstate_to_bt(btcoexist, false);
-
- }
-}
-
-void ex_halbtc8822b1ant_halt_notify(IN struct btc_coexist *btcoexist)
-{
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n");
- BTC_TRACE(trace_buf);
-
- halbtc8822b1ant_post_activestate_to_bt(btcoexist, false);
- halbtc8822b1ant_post_onoffstate_to_bt(btcoexist, false);
-
- halbtc8822b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
-
- halbtc8822b1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_AUTO,
- FORCE_EXEC,
- BT_8822B_1ANT_PHASE_WLAN_OFF);
-
- halbtc8822b1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
-
- ex_halbtc8822b1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
-
- halbtc8822b1ant_enable_gnt_to_gpio(btcoexist, FALSE);
-
- btcoexist->stop_coex_dm = true;
-}
-
-void ex_halbtc8822b1ant_pnp_notify(IN struct btc_coexist *btcoexist,
- IN u8 pnp_state)
-{
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n");
- BTC_TRACE(trace_buf);
-
- if (BTC_WIFI_PNP_SLEEP == pnp_state) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Pnp notify to SLEEP\n");
- BTC_TRACE(trace_buf);
-
- halbtc8822b1ant_post_activestate_to_bt(btcoexist, false);
- halbtc8822b1ant_post_onoffstate_to_bt(btcoexist, false);
-
- halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
-
- halbtc8822b1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_AUTO,
- FORCE_EXEC,
- BT_8822B_1ANT_PHASE_WLAN_OFF);
-
- halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 5);
-
- halbtc8822b1ant_enable_gnt_to_gpio(btcoexist, FALSE);
-
- btcoexist->stop_coex_dm = true;
- } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Pnp notify to WAKE UP\n");
- BTC_TRACE(trace_buf);
-
- halbtc8822b1ant_post_activestate_to_bt(btcoexist, true);
- halbtc8822b1ant_post_onoffstate_to_bt(btcoexist, true);
-
- btcoexist->stop_coex_dm = false;
- }
-}
-
-void ex_halbtc8822b1ant_coex_dm_reset(IN struct btc_coexist *btcoexist)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], *****************Coex DM Reset*****************\n");
- BTC_TRACE(trace_buf);
-
- halbtc8822b1ant_init_hw_config(btcoexist, false, false);
- halbtc8822b1ant_init_coex_dm(btcoexist);
-}
-
-void ex_halbtc8822b1ant_periodical(IN struct btc_coexist *btcoexist)
-{
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ==========================Periodical===========================\n");
- BTC_TRACE(trace_buf);
-
-#if (BT_AUTO_REPORT_ONLY_8822B_1ANT == 0)
- halbtc8822b1ant_query_bt_info(btcoexist);
-#endif
-
- halbtc8822b1ant_monitor_bt_ctr(btcoexist);
- halbtc8822b1ant_monitor_wifi_ctr(btcoexist);
-
- halbtc8822b1ant_monitor_bt_enable_disable(btcoexist);
-
- /* for 4-way, DHCP, EAPOL packet */
- if (coex_sta->specific_pkt_period_cnt > 0) {
-
- coex_sta->specific_pkt_period_cnt--;
-
- if ((coex_sta->specific_pkt_period_cnt == 0) && (coex_sta->wifi_is_high_pri_task))
- coex_sta->wifi_is_high_pri_task = false;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ***************** Hi-Pri Task = %s*****************\n", (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"));
- BTC_TRACE(trace_buf);
- }
-
-
- if (coex_sta->bt_coex_supported_feature == 0)
- coex_sta->bt_coex_supported_feature = btcoexist->btc_get_bt_coex_supported_feature(btcoexist);
-
- if ( (coex_sta->bt_coex_supported_version == 0) && (!coex_sta->bt_disabled) )
- coex_sta->bt_coex_supported_version = btcoexist->btc_get_bt_coex_supported_version(btcoexist);
-
- if (halbtc8822b1ant_is_wifi_status_changed(btcoexist))
- halbtc8822b1ant_run_coexist_mechanism(btcoexist);
-
-}
-
-void ex_halbtc8822b1ant_antenna_detection(IN struct btc_coexist *btcoexist,
- IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
-{
-}
-
-void ex_halbtc8822b1ant_antenna_isolation(IN struct btc_coexist *btcoexist,
- IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
-{
-
-
-}
-
-void ex_halbtc8822b1ant_psd_scan(IN struct btc_coexist *btcoexist,
- IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
-{
-
-
-}
-
-void ex_halbtc8822b1ant_display_ant_detection(IN struct btc_coexist *btcoexist)
-{
-
-}
-
-void ex_halbtc8822b1ant_dbg_control(IN struct btc_coexist *btcoexist,
- IN u8 op_code, IN u8 op_len, IN u8 *pdata)
-{}
-#endif /* #if(BTC_COEX_OFFLOAD == 1) */
-
-#endif
-
-#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */
-
diff --git a/hal/btc/halbtc8723d1ant.c b/hal/btc/halbtc8723d1ant.c
deleted file mode 100644
index f877b20..0000000
--- a/hal/btc/halbtc8723d1ant.c
+++ /dev/null
@@ -1,5465 +0,0 @@
-/* ************************************************************
- * Description:
- *
- * This file is for RTL8723D Co-exist mechanism
- *
- * History
- * 2012/11/15 Cosa first check in.
- *
- * ************************************************************ */
-
-/* ************************************************************
- * include files
- * ************************************************************ */
-#include "Mp_Precomp.h"
-
-#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
-
-#if (RTL8723D_SUPPORT == 1)
-/* ************************************************************
- * Global variables, these are static variables
- * ************************************************************ */
-static u8 *trace_buf = &gl_btc_trace_buf[0];
-static struct coex_dm_8723d_1ant glcoex_dm_8723d_1ant;
-static struct coex_dm_8723d_1ant *coex_dm = &glcoex_dm_8723d_1ant;
-static struct coex_sta_8723d_1ant glcoex_sta_8723d_1ant;
-static struct coex_sta_8723d_1ant *coex_sta = &glcoex_sta_8723d_1ant;
-static struct psdscan_sta_8723d_1ant gl_psd_scan_8723d_1ant;
-static struct psdscan_sta_8723d_1ant *psd_scan = &gl_psd_scan_8723d_1ant;
-
-
-const char *const glbt_info_src_8723d_1ant[] = {
- "BT Info[wifi fw]",
- "BT Info[bt rsp]",
- "BT Info[bt auto report]",
-};
-
-u32 glcoex_ver_date_8723d_1ant = 20160218;
-u32 glcoex_ver_8723d_1ant = 0x05;
-
-/* ************************************************************
- * local function proto type if needed
- * ************************************************************
- * ************************************************************
- * local function start with halbtc8723d1ant_
- * ************************************************************ */
-u8 halbtc8723d1ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1)
-{
- s32 bt_rssi = 0;
- u8 bt_rssi_state = coex_sta->pre_bt_rssi_state;
-
- bt_rssi = coex_sta->bt_rssi;
-
- if (level_num == 2) {
- if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
- (coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (bt_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8723D_1ANT))
- bt_rssi_state = BTC_RSSI_STATE_HIGH;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else {
- if (bt_rssi < rssi_thresh)
- bt_rssi_state = BTC_RSSI_STATE_LOW;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- } else if (level_num == 3) {
- if (rssi_thresh > rssi_thresh1) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Rssi thresh error!!\n");
- BTC_TRACE(trace_buf);
- return coex_sta->pre_bt_rssi_state;
- }
-
- if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
- (coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (bt_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8723D_1ANT))
- bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else if ((coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_MEDIUM) ||
- (coex_sta->pre_bt_rssi_state ==
- BTC_RSSI_STATE_STAY_MEDIUM)) {
- if (bt_rssi >= (rssi_thresh1 +
- BTC_RSSI_COEX_THRESH_TOL_8723D_1ANT))
- bt_rssi_state = BTC_RSSI_STATE_HIGH;
- else if (bt_rssi < rssi_thresh)
- bt_rssi_state = BTC_RSSI_STATE_LOW;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
- } else {
- if (bt_rssi < rssi_thresh1)
- bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- }
-
- coex_sta->pre_bt_rssi_state = bt_rssi_state;
-
- return bt_rssi_state;
-}
-
-u8 halbtc8723d1ant_wifi_rssi_state(IN struct btc_coexist *btcoexist,
- IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1)
-{
- s32 wifi_rssi = 0;
- u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index];
-
- btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
-
- if (level_num == 2) {
- if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
- ||
- (coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (wifi_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8723D_1ANT))
- wifi_rssi_state = BTC_RSSI_STATE_HIGH;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else {
- if (wifi_rssi < rssi_thresh)
- wifi_rssi_state = BTC_RSSI_STATE_LOW;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- } else if (level_num == 3) {
- if (rssi_thresh > rssi_thresh1) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], wifi RSSI thresh error!!\n");
- BTC_TRACE(trace_buf);
- return coex_sta->pre_wifi_rssi_state[index];
- }
-
- if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW)
- ||
- (coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_STAY_LOW)) {
- if (wifi_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8723D_1ANT))
- wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else if ((coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_MEDIUM) ||
- (coex_sta->pre_wifi_rssi_state[index] ==
- BTC_RSSI_STATE_STAY_MEDIUM)) {
- if (wifi_rssi >= (rssi_thresh1 +
- BTC_RSSI_COEX_THRESH_TOL_8723D_1ANT))
- wifi_rssi_state = BTC_RSSI_STATE_HIGH;
- else if (wifi_rssi < rssi_thresh)
- wifi_rssi_state = BTC_RSSI_STATE_LOW;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
- } else {
- if (wifi_rssi < rssi_thresh1)
- wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- }
-
- coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state;
-
- return wifi_rssi_state;
-}
-
-void halbtc8723d1ant_update_ra_mask(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u32 dis_rate_mask)
-{
- coex_dm->cur_ra_mask = dis_rate_mask;
-
- if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask))
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK,
- &coex_dm->cur_ra_mask);
- coex_dm->pre_ra_mask = coex_dm->cur_ra_mask;
-}
-
-void halbtc8723d1ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- boolean wifi_under_b_mode = false;
-
- coex_dm->cur_arfr_type = type;
-
- if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) {
- switch (coex_dm->cur_arfr_type) {
- case 0: /* normal mode */
- btcoexist->btc_write_4byte(btcoexist, 0x430,
- coex_dm->backup_arfr_cnt1);
- btcoexist->btc_write_4byte(btcoexist, 0x434,
- coex_dm->backup_arfr_cnt2);
- break;
- case 1:
- btcoexist->btc_get(btcoexist,
- BTC_GET_BL_WIFI_UNDER_B_MODE,
- &wifi_under_b_mode);
- if (wifi_under_b_mode) {
- btcoexist->btc_write_4byte(btcoexist,
- 0x430, 0x0);
- btcoexist->btc_write_4byte(btcoexist,
- 0x434, 0x01010101);
- } else {
- btcoexist->btc_write_4byte(btcoexist,
- 0x430, 0x0);
- btcoexist->btc_write_4byte(btcoexist,
- 0x434, 0x04030201);
- }
- break;
- default:
- break;
- }
- }
-
- coex_dm->pre_arfr_type = coex_dm->cur_arfr_type;
-}
-
-void halbtc8723d1ant_retry_limit(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- coex_dm->cur_retry_limit_type = type;
-
- if (force_exec ||
- (coex_dm->pre_retry_limit_type !=
- coex_dm->cur_retry_limit_type)) {
- switch (coex_dm->cur_retry_limit_type) {
- case 0: /* normal mode */
- btcoexist->btc_write_2byte(btcoexist, 0x42a,
- coex_dm->backup_retry_limit);
- break;
- case 1: /* retry limit=8 */
- btcoexist->btc_write_2byte(btcoexist, 0x42a,
- 0x0808);
- break;
- default:
- break;
- }
- }
-
- coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type;
-}
-
-void halbtc8723d1ant_ampdu_max_time(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- coex_dm->cur_ampdu_time_type = type;
-
- if (force_exec ||
- (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) {
- switch (coex_dm->cur_ampdu_time_type) {
- case 0: /* normal mode */
- btcoexist->btc_write_1byte(btcoexist, 0x456,
- coex_dm->backup_ampdu_max_time);
- break;
- case 1: /* AMPDU timw = 0x38 * 32us */
- btcoexist->btc_write_1byte(btcoexist, 0x456,
- 0x38);
- break;
- default:
- break;
- }
- }
-
- coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type;
-}
-
-void halbtc8723d1ant_limited_tx(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type,
- IN u8 retry_limit_type, IN u8 ampdu_time_type)
-{
- switch (ra_mask_type) {
- case 0: /* normal mode */
- halbtc8723d1ant_update_ra_mask(btcoexist, force_exec,
- 0x0);
- break;
- case 1: /* disable cck 1/2 */
- halbtc8723d1ant_update_ra_mask(btcoexist, force_exec,
- 0x00000003);
- break;
- case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */
- halbtc8723d1ant_update_ra_mask(btcoexist, force_exec,
- 0x0001f1f7);
- break;
- default:
- break;
- }
-
- halbtc8723d1ant_auto_rate_fallback_retry(btcoexist, force_exec,
- arfr_type);
- halbtc8723d1ant_retry_limit(btcoexist, force_exec, retry_limit_type);
- halbtc8723d1ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type);
-}
-
-void halbtc8723d1ant_limited_rx(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean rej_ap_agg_pkt,
- IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size)
-{
- boolean reject_rx_agg = rej_ap_agg_pkt;
- boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size;
- u8 rx_agg_size = agg_buf_size;
-
- /* ============================================ */
- /* Rx Aggregation related setting */
- /* ============================================ */
- btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT,
- &reject_rx_agg);
- /* decide BT control aggregation buf size or not */
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE,
- &bt_ctrl_rx_agg_size);
- /* aggregation buf size, only work when BT control Rx aggregation size. */
- btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size);
- /* real update aggregation setting */
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
-
-
-}
-
-void halbtc8723d1ant_query_bt_info(IN struct btc_coexist *btcoexist)
-{
- u8 h2c_parameter[1] = {0};
-
- coex_sta->c2h_bt_info_req_sent = true;
-
- h2c_parameter[0] |= BIT(0); /* trigger */
-
- btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], WL query BT info!!\n");
- BTC_TRACE(trace_buf);
-}
-
-void halbtc8723d1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist)
-{
- u32 reg_hp_txrx, reg_lp_txrx, u32tmp;
- u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
- static u8 num_of_bt_counter_chk = 0, cnt_slave = 0;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
- /* to avoid 0x76e[3] = 1 (WLAN_Act control by PTA) during IPS */
- /* if (! (btcoexist->btc_read_1byte(btcoexist, 0x76e) & 0x8) ) */
-
- reg_hp_txrx = 0x770;
- reg_lp_txrx = 0x774;
-
- u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
- reg_hp_tx = u32tmp & MASKLWORD;
- reg_hp_rx = (u32tmp & MASKHWORD) >> 16;
-
- u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
- reg_lp_tx = u32tmp & MASKLWORD;
- reg_lp_rx = (u32tmp & MASKHWORD) >> 16;
-
- coex_sta->high_priority_tx = reg_hp_tx;
- coex_sta->high_priority_rx = reg_hp_rx;
- coex_sta->low_priority_tx = reg_lp_tx;
- coex_sta->low_priority_rx = reg_lp_rx;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n",
- reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx);
-
- BTC_TRACE(trace_buf);
-
- /* reset counter */
- btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
-
- if ((coex_sta->low_priority_tx > 1150) &&
- (!coex_sta->c2h_bt_inquiry_page))
- coex_sta->pop_event_cnt++;
-
- if ((coex_sta->low_priority_rx >= 1150) && (coex_sta->low_priority_rx >= coex_sta->low_priority_tx)
- && (!coex_sta->under_ips) && (!coex_sta->c2h_bt_inquiry_page) && (coex_sta->bt_link_exist)) {
- if (cnt_slave >= 3) {
- bt_link_info->slave_role = true;
- cnt_slave = 3;
- } else
- cnt_slave++;
- } else {
- if (cnt_slave == 0) {
- bt_link_info->slave_role = false;
- cnt_slave = 0;
- } else
- cnt_slave--;
-
- }
-
- if ((coex_sta->high_priority_tx == 0) && (coex_sta->high_priority_rx == 0) && (coex_sta->low_priority_tx == 0) &&
- (coex_sta->low_priority_rx == 0)) {
- num_of_bt_counter_chk++;
- if (num_of_bt_counter_chk >= 3) {
- halbtc8723d1ant_query_bt_info(btcoexist);
- num_of_bt_counter_chk = 0;
- }
- }
-
-#if 0
- /* Add Hi-Pri Tx/Rx counter to avoid false detection */
- if (((coex_sta->hid_exist) || (coex_sta->sco_exist)) &&
- (coex_sta->high_priority_tx + coex_sta->high_priority_rx
- >= 160)
- && (!coex_sta->c2h_bt_inquiry_page))
- coex_sta->bt_hi_pri_link_exist = true;
- else
- coex_sta->bt_hi_pri_link_exist = false;
-
- if ((coex_sta->acl_busy) &&
- (coex_sta->num_of_profile == 0)) {
- if (coex_sta->low_priority_tx +
- coex_sta->low_priority_rx >= 160) {
- coex_sta->pan_exist = true;
- coex_sta->num_of_profile++;
- coex_sta->wrong_profile_notification++;
- }
- }
-#endif
-
-}
-
-
-
-void halbtc8723d1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist)
-{
- s32 wifi_rssi = 0;
- boolean wifi_busy = false, wifi_under_b_mode = false;
- static u8 cck_lock_counter = 0;
- u32 total_cnt;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
- &wifi_under_b_mode);
-
- if (coex_sta->under_ips) {
- coex_sta->crc_ok_cck = 0;
- coex_sta->crc_ok_11g = 0;
- coex_sta->crc_ok_11n = 0;
- coex_sta->crc_ok_11n_agg = 0;
-
- coex_sta->crc_err_cck = 0;
- coex_sta->crc_err_11g = 0;
- coex_sta->crc_err_11n = 0;
- coex_sta->crc_err_11n_agg = 0;
- } else {
- coex_sta->crc_ok_cck = btcoexist->btc_read_4byte(btcoexist,
- 0xf88);
- coex_sta->crc_ok_11g = btcoexist->btc_read_2byte(btcoexist,
- 0xf94);
- coex_sta->crc_ok_11n = btcoexist->btc_read_2byte(btcoexist,
- 0xf90);
- coex_sta->crc_ok_11n_agg = btcoexist->btc_read_2byte(btcoexist,
- 0xfb8);
-
- coex_sta->crc_err_cck = btcoexist->btc_read_4byte(btcoexist,
- 0xf84);
- coex_sta->crc_err_11g = btcoexist->btc_read_2byte(btcoexist,
- 0xf96);
- coex_sta->crc_err_11n = btcoexist->btc_read_2byte(btcoexist,
- 0xf92);
- coex_sta->crc_err_11n_agg = btcoexist->btc_read_2byte(btcoexist,
- 0xfba);
- }
-
-
- /* reset counter */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xf16, 0x1, 0x1);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xf16, 0x1, 0x0);
-
- if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) {
- total_cnt = coex_sta->crc_ok_cck + coex_sta->crc_ok_11g +
- coex_sta->crc_ok_11n +
- coex_sta->crc_ok_11n_agg;
-
- if ((coex_dm->bt_status == BT_8723D_1ANT_BT_STATUS_ACL_BUSY) ||
- (coex_dm->bt_status ==
- BT_8723D_1ANT_BT_STATUS_ACL_SCO_BUSY) ||
- (coex_dm->bt_status ==
- BT_8723D_1ANT_BT_STATUS_SCO_BUSY)) {
- if (coex_sta->crc_ok_cck > (total_cnt -
- coex_sta->crc_ok_cck)) {
- if (cck_lock_counter < 3)
- cck_lock_counter++;
- } else {
- if (cck_lock_counter > 0)
- cck_lock_counter--;
- }
-
- } else {
- if (cck_lock_counter > 0)
- cck_lock_counter--;
- }
- } else {
- if (cck_lock_counter > 0)
- cck_lock_counter--;
- }
-
- if (!coex_sta->pre_ccklock) {
-
- if (cck_lock_counter >= 3)
- coex_sta->cck_lock = true;
- else
- coex_sta->cck_lock = false;
- } else {
- if (cck_lock_counter == 0)
- coex_sta->cck_lock = false;
- else
- coex_sta->cck_lock = true;
- }
-
- if (coex_sta->cck_lock)
- coex_sta->cck_ever_lock = true;
-
- coex_sta->pre_ccklock = coex_sta->cck_lock;
-
-
-}
-
-boolean halbtc8723d1ant_is_wifibt_status_changed(IN struct btc_coexist *btcoexist)
-{
- static boolean pre_wifi_busy = false, pre_under_4way = false,
- pre_bt_hs_on = false, pre_bt_off = false;
- boolean wifi_busy = false, under_4way = false, bt_hs_on = false;
- boolean wifi_connected = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
- &under_4way);
-
- if (coex_sta->bt_disabled != pre_bt_off) {
- pre_bt_off = coex_sta->bt_disabled;
-
- if (coex_sta->bt_disabled)
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is disabled !!\n");
- else
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is enabled !!\n");
-
- BTC_TRACE(trace_buf);
- return true;
- }
-
- if (wifi_connected) {
- if (wifi_busy != pre_wifi_busy) {
- pre_wifi_busy = wifi_busy;
- return true;
- }
- if (under_4way != pre_under_4way) {
- pre_under_4way = under_4way;
- return true;
- }
- if (bt_hs_on != pre_bt_hs_on) {
- pre_bt_hs_on = bt_hs_on;
- return true;
- }
- }
-
- return false;
-}
-
-void halbtc8723d1ant_update_bt_link_info(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean bt_hs_on = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
-
- bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
- bt_link_info->sco_exist = coex_sta->sco_exist;
- bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
- bt_link_info->pan_exist = coex_sta->pan_exist;
- bt_link_info->hid_exist = coex_sta->hid_exist;
- bt_link_info->bt_hi_pri_link_exist = coex_sta->bt_hi_pri_link_exist;
- bt_link_info->acl_busy = coex_sta->acl_busy;
-
- /* work around for HS mode. */
- if (bt_hs_on) {
- bt_link_info->pan_exist = true;
- bt_link_info->bt_link_exist = true;
- }
-
- /* check if Sco only */
- if (bt_link_info->sco_exist &&
- !bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist &&
- !bt_link_info->hid_exist)
- bt_link_info->sco_only = true;
- else
- bt_link_info->sco_only = false;
-
- /* check if A2dp only */
- if (!bt_link_info->sco_exist &&
- bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist &&
- !bt_link_info->hid_exist)
- bt_link_info->a2dp_only = true;
- else
- bt_link_info->a2dp_only = false;
-
- /* check if Pan only */
- if (!bt_link_info->sco_exist &&
- !bt_link_info->a2dp_exist &&
- bt_link_info->pan_exist &&
- !bt_link_info->hid_exist)
- bt_link_info->pan_only = true;
- else
- bt_link_info->pan_only = false;
-
- /* check if Hid only */
- if (!bt_link_info->sco_exist &&
- !bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist &&
- bt_link_info->hid_exist)
- bt_link_info->hid_only = true;
- else
- bt_link_info->hid_only = false;
-}
-
-void halbtc8723d1ant_update_wifi_channel_info(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- u8 h2c_parameter[3] = {0};
- u32 wifi_bw;
- u8 wifi_central_chnl;
-
- /* only 2.4G we need to inform bt the chnl mask */
- btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
- &wifi_central_chnl);
- if ((BTC_MEDIA_CONNECT == type) &&
- (wifi_central_chnl <= 14)) {
- h2c_parameter[0] =
- 0x1; /* enable BT AFH skip WL channel for 8723d because BT Rx LO interference */
- /* h2c_parameter[0] = 0x0; */
- h2c_parameter[1] = wifi_central_chnl;
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- if (BTC_WIFI_BW_HT40 == wifi_bw)
- h2c_parameter[2] = 0x30;
- else
- h2c_parameter[2] = 0x20;
- }
-
- coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
- coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
- coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
-
- btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter);
-
-}
-
-u8 halbtc8723d1ant_action_algorithm(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean bt_hs_on = false;
- u8 algorithm = BT_8723D_1ANT_COEX_ALGO_UNDEFINED;
- u8 num_of_diff_profile = 0;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
-
- if (!bt_link_info->bt_link_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], No BT link exists!!!\n");
- BTC_TRACE(trace_buf);
- return algorithm;
- }
-
- if (bt_link_info->sco_exist)
- num_of_diff_profile++;
- if (bt_link_info->hid_exist)
- num_of_diff_profile++;
- if (bt_link_info->pan_exist)
- num_of_diff_profile++;
- if (bt_link_info->a2dp_exist)
- num_of_diff_profile++;
-
- if (num_of_diff_profile == 1) {
- if (bt_link_info->sco_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO only\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8723D_1ANT_COEX_ALGO_SCO;
- } else {
- if (bt_link_info->hid_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = HID only\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8723D_1ANT_COEX_ALGO_HID;
- } else if (bt_link_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = A2DP only\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8723D_1ANT_COEX_ALGO_A2DP;
- } else if (bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = PAN(HS) only\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723D_1ANT_COEX_ALGO_PANHS;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = PAN(EDR) only\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723D_1ANT_COEX_ALGO_PANEDR;
- }
- }
- }
- } else if (num_of_diff_profile == 2) {
- if (bt_link_info->sco_exist) {
- if (bt_link_info->hid_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + HID\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8723D_1ANT_COEX_ALGO_HID;
- } else if (bt_link_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + A2DP ==> SCO\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8723D_1ANT_COEX_ALGO_SCO;
- } else if (bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8723D_1ANT_COEX_ALGO_SCO;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723D_1ANT_COEX_ALGO_PANEDR_HID;
- }
- }
- } else {
- if (bt_link_info->hid_exist &&
- bt_link_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = HID + A2DP\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8723D_1ANT_COEX_ALGO_HID_A2DP;
- } else if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = HID + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723D_1ANT_COEX_ALGO_HID_A2DP;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = HID + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723D_1ANT_COEX_ALGO_PANEDR_HID;
- }
- } else if (bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723D_1ANT_COEX_ALGO_A2DP_PANHS;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = A2DP + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723D_1ANT_COEX_ALGO_PANEDR_A2DP;
- }
- }
- }
- } else if (num_of_diff_profile == 3) {
- if (bt_link_info->sco_exist) {
- if (bt_link_info->hid_exist &&
- bt_link_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8723D_1ANT_COEX_ALGO_HID;
- } else if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + HID + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723D_1ANT_COEX_ALGO_HID_A2DP;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723D_1ANT_COEX_ALGO_PANEDR_HID;
- }
- } else if (bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8723D_1ANT_COEX_ALGO_SCO;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723D_1ANT_COEX_ALGO_PANEDR_HID;
- }
- }
- } else {
- if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723D_1ANT_COEX_ALGO_HID_A2DP;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723D_1ANT_COEX_ALGO_HID_A2DP_PANEDR;
- }
- }
- }
- } else if (num_of_diff_profile >= 3) {
- if (bt_link_info->sco_exist) {
- if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
-
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723D_1ANT_COEX_ALGO_PANEDR_HID;
- }
- }
- }
- }
-
- return algorithm;
-}
-
-void halbtc8723d1ant_set_bt_auto_report(IN struct btc_coexist *btcoexist,
- IN boolean enable_auto_report)
-{
- u8 h2c_parameter[1] = {0};
-
- h2c_parameter[0] = 0;
-
- if (enable_auto_report)
- h2c_parameter[0] |= BIT(0);
-
- btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter);
-}
-
-void halbtc8723d1ant_bt_auto_report(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean enable_auto_report)
-{
- coex_dm->cur_bt_auto_report = enable_auto_report;
-
- if (!force_exec) {
- if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report)
- return;
- }
- halbtc8723d1ant_set_bt_auto_report(btcoexist,
- coex_dm->cur_bt_auto_report);
-
- coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report;
-}
-
-void halbtc8723d1ant_set_fw_low_penalty_ra(IN struct btc_coexist
- *btcoexist, IN boolean low_penalty_ra)
-{
- u8 h2c_parameter[6] = {0};
-
- h2c_parameter[0] = 0x6; /* op_code, 0x6= Retry_Penalty */
-
- if (low_penalty_ra) {
- h2c_parameter[1] |= BIT(0);
- h2c_parameter[2] =
- 0x00; /* normal rate except MCS7/6/5, OFDM54/48/36 */
- h2c_parameter[3] = 0xf7; /* MCS7 or OFDM54 */
- h2c_parameter[4] = 0xf8; /* MCS6 or OFDM48 */
- h2c_parameter[5] = 0xf9; /* MCS5 or OFDM36 */
- }
-
- btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter);
-}
-
-void halbtc8723d1ant_low_penalty_ra(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean low_penalty_ra)
-{
- coex_dm->cur_low_penalty_ra = low_penalty_ra;
-
- if (!force_exec) {
- if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra)
- return;
- }
- halbtc8723d1ant_set_fw_low_penalty_ra(btcoexist,
- coex_dm->cur_low_penalty_ra);
-
- coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra;
-}
-
-void halbtc8723d1ant_sw_mechanism(IN struct btc_coexist *btcoexist,
- IN boolean low_penalty_ra)
-{
- halbtc8723d1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra);
-}
-
-void halbtc8723d1ant_write_score_board(
- IN struct btc_coexist *btcoexist,
- IN u16 bitpos,
- IN BOOLEAN state
-)
-{
-
- static u16 originalval = 0x8002;
-
- if (state)
- originalval = originalval | bitpos;
- else
- originalval = originalval & (~bitpos);
-
-
- btcoexist->btc_write_2byte(btcoexist, 0xaa, originalval);
-
-}
-
-void halbtc8723d1ant_read_score_board(
- IN struct btc_coexist *btcoexist,
- IN u16 *score_board_val
-)
-{
-
- *score_board_val = (btcoexist->btc_read_2byte(btcoexist,
- 0xaa)) & 0x7fff;
-}
-
-void halbtc8723d1ant_post_activestate_to_bt(
- IN struct btc_coexist *btcoexist,
- IN boolean wifi_active
-)
-{
-
- if (wifi_active)
- halbtc8723d1ant_write_score_board(btcoexist, (u16) BIT(0), TRUE);
- else
- halbtc8723d1ant_write_score_board(btcoexist, (u16) BIT(0), FALSE);
-
- /* The BT should set "No Shunt-down" mode if WL = Active for BT Synthesizer on/off interference WL Lo issue at 8703b b-cut. */
-
-}
-
-void halbtc8723d1ant_post_onoffstate_to_bt(
- IN struct btc_coexist *btcoexist,
- IN boolean wifi_on
-)
-{
-
- if (wifi_on)
- halbtc8723d1ant_write_score_board(btcoexist, (u16) BIT(1), TRUE);
- else
- halbtc8723d1ant_write_score_board(btcoexist, (u16) BIT(1), FALSE);
-
-}
-
-void halbtc8723d1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist)
-{
- static u32 bt_disable_cnt = 0;
- boolean bt_active = true, bt_disabled = false;
- u16 u16tmp;
-
- /* This function check if bt is disabled */
-#if 0
- if (coex_sta->high_priority_tx == 0 &&
- coex_sta->high_priority_rx == 0 &&
- coex_sta->low_priority_tx == 0 &&
- coex_sta->low_priority_rx == 0)
- bt_active = false;
- if (coex_sta->high_priority_tx == 0xffff &&
- coex_sta->high_priority_rx == 0xffff &&
- coex_sta->low_priority_tx == 0xffff &&
- coex_sta->low_priority_rx == 0xffff)
- bt_active = false;
-
-
-#else
-
- /* Read BT on/off status from scoreboard[1], enable this only if BT patch support this feature */
- halbtc8723d1ant_read_score_board(btcoexist, &u16tmp);
-
- bt_active = u16tmp & BIT(1);
-
-
-#endif
-
- if (bt_active) {
- bt_disable_cnt = 0;
- bt_disabled = false;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
- &bt_disabled);
- } else {
-
- bt_disable_cnt++;
- if (bt_disable_cnt >= 2) {
- bt_disabled = true;
- bt_disable_cnt = 2;
- }
-
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
- &bt_disabled);
- }
-
-
- if (coex_sta->bt_disabled != bt_disabled) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is from %s to %s!!\n",
- (coex_sta->bt_disabled ? "disabled" : "enabled"),
- (bt_disabled ? "disabled" : "enabled"));
- BTC_TRACE(trace_buf);
- coex_sta->bt_disabled = bt_disabled;
- }
-
-}
-
-void halbtc8723d1ant_enable_gnt_to_gpio(IN struct btc_coexist *btcoexist,
- boolean isenable)
-{
-
- if (isenable) {
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x1);
-
- /* enable GNT_BT to GPIO debug */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x40, 0x0);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x1, 0x0);
-
- /* 0x48[20] = 0 for GPIO14 = GNT_WL*/
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4a, 0x10, 0x0);
- /* 0x40[17] = 0 for GPIO14 = GNT_WL*/
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, 0x02, 0x0);
-
- /* 0x66[9] = 0 for GPIO15 = GNT_B T*/
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x02, 0x0);
- /* 0x66[7] = 0
- for GPIO15 = GNT_BT*/
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, 0x80, 0x0);
- /* 0x8[8] = 0 for GPIO15 = GNT_BT*/
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x9, 0x1, 0x0);
-
- /* BT Vendor Reg 0x76[0] = 0 for GPIO15 = GNT_BT, this is not set here*/
- } else {
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x0);
-
- /* Disable GNT_BT debug to GPIO, and enable chip_wakeup_host */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x40, 0x1);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x1, 0x1);
-
- /* 0x48[20] = 0 for GPIO14 = GNT_WL*/
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4a, 0x10, 0x1);
- }
-
-
-}
-
-u32 halbtc8723d1ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist,
- IN u16 reg_addr)
-{
- u32 j = 0;
-
-
- /* wait for ready bit before access 0x7c0 */
- btcoexist->btc_write_4byte(btcoexist, 0x7c0, 0x800F0000 | reg_addr);
-
- do {
- j++;
- } while (((btcoexist->btc_read_1byte(btcoexist,
- 0x7c3)&BIT(5)) == 0) &&
- (j < BT_8723D_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT));
-
-
- return btcoexist->btc_read_4byte(btcoexist,
- 0x7c8); /* get read data */
-
-}
-
-void halbtc8723d1ant_ltecoex_indirect_write_reg(IN struct btc_coexist *btcoexist,
- IN u16 reg_addr, IN u32 bit_mask, IN u32 reg_value)
-{
- u32 val, i = 0, j = 0, bitpos = 0;
-
-
- if (bit_mask == 0x0)
- return;
- if (bit_mask == 0xffffffff) {
- btcoexist->btc_write_4byte(btcoexist, 0x7c4,
- reg_value); /* put write data */
-
- /* wait for ready bit before access 0x7c0 */
- do {
- j++;
- } while (((btcoexist->btc_read_1byte(btcoexist,
- 0x7c3)&BIT(5)) == 0) &&
- (j < BT_8723D_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT));
-
-
- btcoexist->btc_write_4byte(btcoexist, 0x7c0,
- 0xc00F0000 | reg_addr);
- } else {
- for (i = 0; i <= 31; i++) {
- if (((bit_mask >> i) & 0x1) == 0x1) {
- bitpos = i;
- break;
- }
- }
-
- /* read back register value before write */
- val = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist,
- reg_addr);
- val = (val & (~bit_mask)) | (reg_value << bitpos);
-
- btcoexist->btc_write_4byte(btcoexist, 0x7c4,
- val); /* put write data */
-
- /* wait for ready bit before access 0x7c0 */
- do {
- j++;
- } while (((btcoexist->btc_read_1byte(btcoexist,
- 0x7c3)&BIT(5)) == 0) &&
- (j < BT_8723D_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT));
-
-
- btcoexist->btc_write_4byte(btcoexist, 0x7c0,
- 0xc00F0000 | reg_addr);
-
- }
-
-}
-
-void halbtc8723d1ant_ltecoex_enable(IN struct btc_coexist *btcoexist,
- IN boolean enable)
-{
- u8 val;
-
- val = (enable) ? 1 : 0;
- halbtc8723d1ant_ltecoex_indirect_write_reg(btcoexist, 0x38, 0x80,
- val); /* 0x38[7] */
-
-}
-
-void halbtc8723d1ant_ltecoex_pathcontrol_owner(IN struct btc_coexist *btcoexist,
- IN boolean wifi_control)
-{
- u8 val;
-
- val = (wifi_control) ? 1 : 0;
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x4,
- val); /* 0x70[26] */
-
-}
-
-void halbtc8723d1ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist,
- IN u8 control_block, IN boolean sw_control, IN u8 state)
-{
- u32 val = 0, bit_mask;
-
- state = state & 0x1;
- val = (sw_control) ? ((state << 1) | 0x1) : 0;
-
- switch (control_block) {
- case BT_8723D_1ANT_GNT_BLOCK_RFC_BB:
- default:
- bit_mask = 0xc000;
- halbtc8723d1ant_ltecoex_indirect_write_reg(btcoexist,
- 0x38, bit_mask, val); /* 0x38[15:14] */
- bit_mask = 0x0c00;
- halbtc8723d1ant_ltecoex_indirect_write_reg(btcoexist,
- 0x38, bit_mask, val); /* 0x38[11:10] */
- break;
- case BT_8723D_1ANT_GNT_BLOCK_RFC:
- bit_mask = 0xc000;
- halbtc8723d1ant_ltecoex_indirect_write_reg(btcoexist,
- 0x38, bit_mask, val); /* 0x38[15:14] */
- break;
- case BT_8723D_1ANT_GNT_BLOCK_BB:
- bit_mask = 0x0c00;
- halbtc8723d1ant_ltecoex_indirect_write_reg(btcoexist,
- 0x38, bit_mask, val); /* 0x38[11:10] */
- break;
-
- }
-
-}
-
-void halbtc8723d1ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist,
- IN u8 control_block, IN boolean sw_control, IN u8 state)
-{
- u32 val = 0, bit_mask;
-
- state = state & 0x1;
- val = (sw_control) ? ((state << 1) | 0x1) : 0;
-
- switch (control_block) {
- case BT_8723D_1ANT_GNT_BLOCK_RFC_BB:
- default:
- bit_mask = 0x3000;
- halbtc8723d1ant_ltecoex_indirect_write_reg(btcoexist,
- 0x38, bit_mask, val); /* 0x38[13:12] */
- bit_mask = 0x0300;
- halbtc8723d1ant_ltecoex_indirect_write_reg(btcoexist,
- 0x38, bit_mask, val); /* 0x38[9:8] */
- break;
- case BT_8723D_1ANT_GNT_BLOCK_RFC:
- bit_mask = 0x3000;
- halbtc8723d1ant_ltecoex_indirect_write_reg(btcoexist,
- 0x38, bit_mask, val); /* 0x38[13:12] */
- break;
- case BT_8723D_1ANT_GNT_BLOCK_BB:
- bit_mask = 0x0300;
- halbtc8723d1ant_ltecoex_indirect_write_reg(btcoexist,
- 0x38, bit_mask, val); /* 0x38[9:8] */
- break;
-
- }
-
-}
-
-void halbtc8723d1ant_ltecoex_set_coex_table(IN struct btc_coexist *btcoexist,
- IN u8 table_type, IN u16 table_content)
-{
- u16 reg_addr = 0x0000;
-
- switch (table_type) {
- case BT_8723D_1ANT_CTT_WL_VS_LTE:
- reg_addr = 0xa0;
- break;
- case BT_8723D_1ANT_CTT_BT_VS_LTE:
- reg_addr = 0xa4;
- break;
- }
-
- if (reg_addr != 0x0000)
- halbtc8723d1ant_ltecoex_indirect_write_reg(btcoexist, reg_addr,
- 0xffff, table_content); /* 0xa0[15:0] or 0xa4[15:0] */
-
-
-}
-
-
-void halbtc8723d1ant_ltecoex_set_break_table(IN struct btc_coexist *btcoexist,
- IN u8 table_type, IN u8 table_content)
-{
- u16 reg_addr = 0x0000;
-
- switch (table_type) {
- case BT_8723D_1ANT_LBTT_WL_BREAK_LTE:
- reg_addr = 0xa8;
- break;
- case BT_8723D_1ANT_LBTT_BT_BREAK_LTE:
- reg_addr = 0xac;
- break;
- case BT_8723D_1ANT_LBTT_LTE_BREAK_WL:
- reg_addr = 0xb0;
- break;
- case BT_8723D_1ANT_LBTT_LTE_BREAK_BT:
- reg_addr = 0xb4;
- break;
- }
-
- if (reg_addr != 0x0000)
- halbtc8723d1ant_ltecoex_indirect_write_reg(btcoexist, reg_addr,
- 0xff, table_content); /* 0xa8[15:0] or 0xb4[15:0] */
-
-
-}
-
-void halbtc8723d1ant_set_coex_table(IN struct btc_coexist *btcoexist,
- IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc)
-{
- btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
-
- btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
-
- btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
-
- btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
-}
-
-void halbtc8723d1ant_coex_table(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4,
- IN u32 val0x6c8, IN u8 val0x6cc)
-{
- coex_dm->cur_val0x6c0 = val0x6c0;
- coex_dm->cur_val0x6c4 = val0x6c4;
- coex_dm->cur_val0x6c8 = val0x6c8;
- coex_dm->cur_val0x6cc = val0x6cc;
-
- if (!force_exec) {
- if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) &&
- (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) &&
- (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) &&
- (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc))
- return;
- }
-
- halbtc8723d1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8,
- val0x6cc);
-
- coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0;
- coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4;
- coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8;
- coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc;
-}
-
-void halbtc8723d1ant_coex_table_with_type(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- u32 break_table;
- u8 select_table;
-
- coex_sta->coex_table_type = type;
-
- if (coex_sta->concurrent_rx_mode_on == true) {
- break_table = 0xf0ffffff; /* set WL hi-pri can break BT */
- select_table =
- 0xb; /* set Tx response = Hi-Pri (ex: Transmitting ACK,BA,CTS) */
- } else {
- break_table = 0xffffff;
- select_table = 0x3;
- }
-
- switch (type) {
- case 0:
- halbtc8723d1ant_coex_table(btcoexist, force_exec,
- 0x55555555, 0x55555555, break_table,
- select_table);
- break;
- case 1:
- halbtc8723d1ant_coex_table(btcoexist, force_exec,
- 0x55555555, 0x5a5a5a5a, break_table,
- select_table);
- break;
- case 2:
- halbtc8723d1ant_coex_table(btcoexist, force_exec,
- 0xaa5a5a5a, 0xaa5a5a5a, break_table,
- select_table);
- break;
- case 3:
- halbtc8723d1ant_coex_table(btcoexist, force_exec,
- 0xaa555555, 0xaa5a5a5a, break_table,
- select_table);
- break;
- case 4:
- halbtc8723d1ant_coex_table(btcoexist,
- force_exec, 0xaa555555, 0xaa5a5a5a,
- break_table, select_table);
- break;
- case 5:
- halbtc8723d1ant_coex_table(btcoexist,
- force_exec, 0x5a5a5a5a, 0x5a5a5a5a,
- break_table, select_table);
- break;
- case 6:
- halbtc8723d1ant_coex_table(btcoexist, force_exec,
- 0x55555555, 0xaaaaaaaa, break_table,
- select_table);
- break;
- case 7:
- halbtc8723d1ant_coex_table(btcoexist, force_exec,
- 0xaaaaaaaa, 0xaaaaaaaa, break_table,
- select_table);
- break;
- case 8:
- halbtc8723d1ant_coex_table(btcoexist, force_exec,
- 0x55dd55dd, 0x5ada5ada, break_table,
- select_table);
- break;
- case 9:
- halbtc8723d1ant_coex_table(btcoexist, force_exec,
- 0x55dd55dd, 0x5ada5ada, break_table,
- select_table);
- break;
- case 10:
- halbtc8723d1ant_coex_table(btcoexist, force_exec,
- 0x55dd55dd, 0x5ada5ada, break_table,
- select_table);
- break;
- case 11:
- halbtc8723d1ant_coex_table(btcoexist, force_exec,
- 0x55dd55dd, 0x5ada5ada, break_table,
- select_table);
- break;
- case 12:
- halbtc8723d1ant_coex_table(btcoexist, force_exec,
- 0x55dd55dd, 0x5ada5ada, break_table,
- select_table);
- break;
- case 13:
- halbtc8723d1ant_coex_table(btcoexist, force_exec,
- 0x5fff5fff, 0xaaaaaaaa, break_table,
- select_table);
- break;
- case 14:
- halbtc8723d1ant_coex_table(btcoexist, force_exec,
- 0x5fff5fff, 0x5ada5ada, break_table,
- select_table);
- break;
- case 15:
- halbtc8723d1ant_coex_table(btcoexist, force_exec,
- 0x55dd55dd, 0xaaaaaaaa, break_table,
- select_table);
- break;
- default:
- break;
- }
-}
-
-void halbtc8723d1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist,
- IN boolean enable)
-{
- u8 h2c_parameter[1] = {0};
-
- if (enable)
- h2c_parameter[0] |= BIT(0); /* function enable */
-
- btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter);
-}
-
-void halbtc8723d1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean enable)
-{
- coex_dm->cur_ignore_wlan_act = enable;
-
- if (!force_exec) {
- if (coex_dm->pre_ignore_wlan_act ==
- coex_dm->cur_ignore_wlan_act)
- return;
- }
- halbtc8723d1ant_set_fw_ignore_wlan_act(btcoexist, enable);
-
- coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
-}
-
-void halbtc8723d1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist,
- IN u8 lps_val, IN u8 rpwm_val)
-{
- u8 lps = lps_val;
- u8 rpwm = rpwm_val;
-
- btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps);
- btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm);
-}
-
-void halbtc8723d1ant_lps_rpwm(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val)
-{
- coex_dm->cur_lps = lps_val;
- coex_dm->cur_rpwm = rpwm_val;
-
- if (!force_exec) {
- if ((coex_dm->pre_lps == coex_dm->cur_lps) &&
- (coex_dm->pre_rpwm == coex_dm->cur_rpwm))
- return;
- }
- halbtc8723d1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val);
-
- coex_dm->pre_lps = coex_dm->cur_lps;
- coex_dm->pre_rpwm = coex_dm->cur_rpwm;
-}
-
-void halbtc8723d1ant_ps_tdma_check_for_power_save_state(
- IN struct btc_coexist *btcoexist, IN boolean new_ps_state)
-{
- u8 lps_mode = 0x0;
- u8 h2c_parameter[5] = {0x8, 0, 0, 0, 0};
-
- btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode);
-
- if (lps_mode) { /* already under LPS state */
- if (new_ps_state) {
- /* keep state under LPS, do nothing. */
- } else {
- /* will leave LPS state, turn off psTdma first */
- /*halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 8); */
- btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
- }
- } else { /* NO PS state */
- if (new_ps_state) {
- /* will enter LPS state, turn off psTdma first */
- /*halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 8);*/
- btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
- } else {
- /* keep state under NO PS state, do nothing. */
- }
- }
-}
-
-void halbtc8723d1ant_power_save_state(IN struct btc_coexist *btcoexist,
- IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val)
-{
- boolean low_pwr_disable = false;
-
- switch (ps_type) {
- case BTC_PS_WIFI_NATIVE:
- /* recover to original 32k low power setting */
- coex_sta->force_lps_on = false;
- low_pwr_disable = false;
- btcoexist->btc_set(btcoexist,
- BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS,
- NULL);
-
- break;
- case BTC_PS_LPS_ON:
- coex_sta->force_lps_on = true;
- halbtc8723d1ant_ps_tdma_check_for_power_save_state(
- btcoexist, true);
- halbtc8723d1ant_lps_rpwm(btcoexist, NORMAL_EXEC,
- lps_val, rpwm_val);
- /* when coex force to enter LPS, do not enter 32k low power. */
- low_pwr_disable = true;
- btcoexist->btc_set(btcoexist,
- BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
- /* power save must executed before psTdma. */
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS,
- NULL);
-
- break;
- case BTC_PS_LPS_OFF:
- coex_sta->force_lps_on = false;
- halbtc8723d1ant_ps_tdma_check_for_power_save_state(
- btcoexist, false);
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS,
- NULL);
-
- break;
- default:
- break;
- }
-}
-
-
-void halbtc8723d1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist,
- IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5)
-{
- u8 h2c_parameter[5] = {0};
- u8 real_byte1 = byte1, real_byte5 = byte5;
- boolean ap_enable = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
- &ap_enable);
-
- if (ap_enable) {
- if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], FW for 1Ant AP mode\n");
- BTC_TRACE(trace_buf);
- real_byte1 &= ~BIT(4);
- real_byte1 |= BIT(5);
-
- real_byte5 |= BIT(5);
- real_byte5 &= ~BIT(6);
-
- halbtc8723d1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
- }
- } else if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
-
- halbtc8723d1ant_power_save_state(
- btcoexist, BTC_PS_LPS_ON, 0x50,
- 0x4);
- } else {
- halbtc8723d1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
- }
-
-
- h2c_parameter[0] = real_byte1;
- h2c_parameter[1] = byte2;
- h2c_parameter[2] = byte3;
- h2c_parameter[3] = byte4;
- h2c_parameter[4] = real_byte5;
-
- coex_dm->ps_tdma_para[0] = real_byte1;
- coex_dm->ps_tdma_para[1] = byte2;
- coex_dm->ps_tdma_para[2] = byte3;
- coex_dm->ps_tdma_para[3] = byte4;
- coex_dm->ps_tdma_para[4] = real_byte5;
-
- btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
-}
-
-
-void halbtc8723d1ant_ps_tdma(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean turn_on, IN u8 type)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- struct btc_board_info *board_info = &btcoexist->board_info;
- boolean wifi_busy = false;
- u8 rssi_adjust_val = 0;
- static u8 psTdmaByte4Modify = 0x0, pre_psTdmaByte4Modify = 0x0;
- static boolean pre_wifi_busy = false;
-
-
-#if BT_8723D_1ANT_ANTDET_ENABLE
-#if BT_8723D_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE
- if (board_info->btdm_ant_num_by_ant_det == 2) {
- if (turn_on)
- type = type +
- 100; /* for WiFi RSSI low or BT RSSI low */
- }
-
-#endif
-#endif
-
- coex_dm->cur_ps_tdma_on = turn_on;
- coex_dm->cur_ps_tdma = type;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- if (wifi_busy != pre_wifi_busy) {
- force_exec = true;
- pre_wifi_busy = wifi_busy;
- }
-
- /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */
- if ((bt_link_info->slave_role) && (bt_link_info->a2dp_exist))
- psTdmaByte4Modify = 0x1;
- else
- psTdmaByte4Modify = 0x0;
-
- if (pre_psTdmaByte4Modify != psTdmaByte4Modify) {
-
- force_exec = true;
- pre_psTdmaByte4Modify = psTdmaByte4Modify;
- }
-
- if (!force_exec) {
- if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) &&
- (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma))
- return;
- }
-
- if (coex_dm->cur_ps_tdma_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** TDMA(on, %d) **********\n",
- coex_dm->cur_ps_tdma);
- BTC_TRACE(trace_buf);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** TDMA(off, %d) **********\n",
- coex_dm->cur_ps_tdma);
- BTC_TRACE(trace_buf);
- }
-
-
- if (turn_on) {
-
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8,
- 0x1); /* enable TBTT nterrupt */
- }
-
-
- if (turn_on) {
- switch (type) {
- default:
- halbtc8723d1ant_set_fw_pstdma(btcoexist,
- 0x61, 0x35, 0x03, 0x11, 0x11);
- break;
-
- case 3:
- halbtc8723d1ant_set_fw_pstdma(btcoexist,
- 0x51, 0x3a, 0x03, 0x10, 0x10);
- break;
- case 4:
- halbtc8723d1ant_set_fw_pstdma(btcoexist,
- 0x51, 0x21, 0x03, 0x10, 0x10);
- break;
- case 5:
- halbtc8723d1ant_set_fw_pstdma(btcoexist,
- 0x61, 0x15, 0x03, 0x11, 0x11);
- break;
- case 6:
- halbtc8723d1ant_set_fw_pstdma(btcoexist,
- 0x61, 0x20, 0x03, 0x11, 0x11);
- break;
- case 7:
- halbtc8723d1ant_set_fw_pstdma(btcoexist,
- 0x51, 0x10, 0x03, 0x10, 0x14 | psTdmaByte4Modify);
- break;
- case 8:
- halbtc8723d1ant_set_fw_pstdma(btcoexist,
- 0x51, 0x10, 0x03, 0x10, 0x14 | psTdmaByte4Modify);
- break;
- case 13:
- halbtc8723d1ant_set_fw_pstdma(btcoexist,
- 0x51, 0x25, 0x03, 0x10, 0x10 | psTdmaByte4Modify);
- break;
- case 14:
- halbtc8723d1ant_set_fw_pstdma(btcoexist,
- 0x51, 0x15, 0x03, 0x10, 0x10 | psTdmaByte4Modify);
- break;
- case 15:
- halbtc8723d1ant_set_fw_pstdma(btcoexist,
- 0x51, 0x20, 0x03, 0x10, 0x10 | psTdmaByte4Modify);
- break;
- case 17:
- halbtc8723d1ant_set_fw_pstdma(btcoexist,
- 0x61, 0x10, 0x03, 0x11, 0x14 | psTdmaByte4Modify);
- break;
- case 19:
- halbtc8723d1ant_set_fw_pstdma(btcoexist,
- 0x61, 0x15, 0x03, 0x11, 0x10);
- break;
- case 20:
- halbtc8723d1ant_set_fw_pstdma(btcoexist,
- 0x61, 0x30, 0x03, 0x11, 0x10);
- break;
- case 21:
- halbtc8723d1ant_set_fw_pstdma(btcoexist,
- 0x61, 0x30, 0x03, 0x11, 0x10);
- break;
- case 22:
- halbtc8723d1ant_set_fw_pstdma(btcoexist,
- 0x61, 0x25, 0x03, 0x11, 0x10);
- break;
- case 32:
- halbtc8723d1ant_set_fw_pstdma(btcoexist,
- 0x61, 0x35, 0x03, 0x11, 0x11);
- break;
- case 33:
- halbtc8723d1ant_set_fw_pstdma(btcoexist,
- 0x61, 0x35, 0x03, 0x11, 0x10);
- break;
-
- /* 1-Ant to 2-Ant TDMA case */
- case 103:
- halbtc8723d1ant_set_fw_pstdma(btcoexist,
- 0xd3, 0x3a, 0x03, 0x70, 0x10);
- break;
- case 104:
- halbtc8723d1ant_set_fw_pstdma(btcoexist,
- 0xd3, 0x21, 0x03, 0x70, 0x10);
- break;
- case 105:
- halbtc8723d1ant_set_fw_pstdma(btcoexist,
- 0xe3, 0x15, 0x03, 0x71, 0x11);
- break;
- case 106:
- halbtc8723d1ant_set_fw_pstdma(btcoexist,
- 0xe3, 0x20, 0x03, 0x71, 0x11);
- break;
- case 107:
- halbtc8723d1ant_set_fw_pstdma(btcoexist,
- 0xd3, 0x10, 0x03, 0x70, 0x14 | psTdmaByte4Modify);
- break;
- case 108:
- halbtc8723d1ant_set_fw_pstdma(btcoexist,
- 0xd3, 0x10, 0x03, 0x70, 0x14 | psTdmaByte4Modify);
- break;
- case 113:
- halbtc8723d1ant_set_fw_pstdma(btcoexist,
- 0xd3, 0x25, 0x03, 0x70, 0x10 | psTdmaByte4Modify);
- break;
- case 114:
- halbtc8723d1ant_set_fw_pstdma(btcoexist,
- 0xd3, 0x15, 0x03, 0x70, 0x10 | psTdmaByte4Modify);
- break;
- case 115:
- halbtc8723d1ant_set_fw_pstdma(btcoexist,
- 0xd3, 0x20, 0x03, 0x70, 0x10 | psTdmaByte4Modify);
- break;
- case 117:
- halbtc8723d1ant_set_fw_pstdma(btcoexist,
- 0xe3, 0x10, 0x03, 0x71, 0x14 | psTdmaByte4Modify);
- break;
- case 119:
- halbtc8723d1ant_set_fw_pstdma(btcoexist,
- 0xe3, 0x15, 0x03, 0x71, 0x10);
- break;
- case 120:
- halbtc8723d1ant_set_fw_pstdma(btcoexist,
- 0xe3, 0x30, 0x03, 0x71, 0x10);
- break;
- case 121:
- halbtc8723d1ant_set_fw_pstdma(btcoexist,
- 0xe3, 0x30, 0x03, 0x71, 0x10);
- break;
- case 122:
- halbtc8723d1ant_set_fw_pstdma(btcoexist,
- 0xe3, 0x25, 0x03, 0x71, 0x10);
- break;
- case 132:
- halbtc8723d1ant_set_fw_pstdma(btcoexist,
- 0xe3, 0x35, 0x03, 0x71, 0x11);
- break;
- case 133:
- halbtc8723d1ant_set_fw_pstdma(btcoexist,
- 0xe3, 0x35, 0x03, 0x71, 0x10);
- break;
-
- }
- } else {
-
- /* disable PS tdma */
- switch (type) {
- case 8: /* PTA Control */
- halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x8,
- 0x0, 0x0, 0x0, 0x0);
- break;
- case 0:
- default: /* Software control, Antenna at BT side */
- halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x0,
- 0x0, 0x0, 0x0, 0x0);
- break;
- case 1: /* 2-Ant, 0x778=3, antenna control by antenna diversity */
- halbtc8723d1ant_set_fw_pstdma(btcoexist, 0x0,
- 0x0, 0x0, 0x48, 0x0);
- break;
- }
- }
-
- /* update pre state */
- coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on;
- coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
-}
-
-
-void halbtc8723d1ant_set_ant_path(IN struct btc_coexist *btcoexist,
- IN u8 ant_pos_type, IN boolean force_exec, IN boolean init_hwcfg,
- IN boolean wifi_off)
-{
- struct btc_board_info *board_info = &btcoexist->board_info;
- u32 cnt_bt_cal_chk = 0;
- boolean is_in_mp_mode = false;
- u8 u8tmp = 0;
- u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0;
- u16 u16tmp1 = 0;
-
-#if BT_8723D_1ANT_ANTDET_ENABLE
-#if BT_8723D_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE
- if (ant_pos_type == BTC_ANT_PATH_PTA) {
- if ((board_info->btdm_ant_det_finish) &&
- (board_info->btdm_ant_num_by_ant_det == 2)) {
- if (board_info->btdm_ant_pos ==
- BTC_ANTENNA_AT_MAIN_PORT)
- ant_pos_type = BTC_ANT_PATH_WIFI;
- else
- ant_pos_type = BTC_ANT_PATH_BT;
- }
- }
-#endif
-#endif
-
- coex_dm->cur_ant_pos_type = ant_pos_type;
-
-#if 1
- u32tmp1 = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist,
- 0x38);
- u32tmp2 = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist,
- 0x54);
- u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73);
-
- u16tmp1 = btcoexist->btc_read_2byte(btcoexist, 0x948);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (Before Ant Setup) 0x948 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n",
- u16tmp1, u8tmp, u32tmp1, u32tmp2);
- BTC_TRACE(trace_buf);
-#endif
-
- if (init_hwcfg) {
- /* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */
- halbtc8723d1ant_ltecoex_enable(btcoexist, 0x0);
-
- /* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */
- halbtc8723d1ant_ltecoex_set_coex_table(btcoexist,
- BT_8723D_1ANT_CTT_WL_VS_LTE, 0xffff);
-
- /* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */
- halbtc8723d1ant_ltecoex_set_coex_table(btcoexist,
- BT_8723D_1ANT_CTT_BT_VS_LTE, 0xffff);
-
- /* Wait If BT IQK running, because Path control owner is at BT during BT IQK (setup by WiFi firmware) */
- while (cnt_bt_cal_chk <= 20) {
- u8tmp = btcoexist->btc_read_1byte(btcoexist,
- 0x49d);
- cnt_bt_cal_chk++;
- if (u8tmp & BIT(0)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ########### BT is calibrating (wait cnt=%d) ###########\n",
- cnt_bt_cal_chk);
- BTC_TRACE(trace_buf);
- delay_ms(50);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** BT is NOT calibrating (wait cnt=%d)**********\n",
- cnt_bt_cal_chk);
- BTC_TRACE(trace_buf);
- break;
- }
- }
-
- /* Set Path control to WL */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x80, 0x1);
-
- /* set Path control owner to WL at initial step */
- halbtc8723d1ant_ltecoex_pathcontrol_owner(btcoexist,
- BT_8723D_1ANT_PCO_WLSIDE);
-
- /* set GNT_BT to SW high */
- halbtc8723d1ant_ltecoex_set_gnt_bt(btcoexist,
- BT_8723D_1ANT_GNT_BLOCK_RFC_BB,
- BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW,
- BT_8723D_1ANT_SIG_STA_SET_TO_HIGH);
- /* Set GNT_WL to SW low */
- halbtc8723d1ant_ltecoex_set_gnt_wl(btcoexist,
- BT_8723D_1ANT_GNT_BLOCK_RFC_BB,
- BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW,
- BT_8723D_1ANT_SIG_STA_SET_TO_LOW);
-
- coex_sta->gnt_control_by_PTA = false;
-
- } else if (wifi_off) {
- /* Disable LTE Coex Function in WiFi side */
- halbtc8723d1ant_ltecoex_enable(btcoexist, 0x0);
-
- /* Set Path control to BT */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x80, 0x0);
-
- /* set Path control owner to BT */
- halbtc8723d1ant_ltecoex_pathcontrol_owner(btcoexist,
- BT_8723D_1ANT_PCO_BTSIDE);
-
- coex_sta->gnt_control_by_PTA = false;
- } else {
-
- halbtc8723d1ant_ltecoex_pathcontrol_owner(btcoexist,
- BT_8723D_1ANT_PCO_WLSIDE);
-
- /* set GNT_BT to PTA */
- halbtc8723d1ant_ltecoex_set_gnt_bt(btcoexist,
- BT_8723D_1ANT_GNT_BLOCK_RFC_BB,
- BT_8723D_1ANT_GNT_TYPE_CTRL_BY_PTA,
- BT_8723D_1ANT_SIG_STA_SET_BY_HW);
- /* Set GNT_WL to PTA */
- halbtc8723d1ant_ltecoex_set_gnt_wl(btcoexist,
- BT_8723D_1ANT_GNT_BLOCK_RFC_BB,
- BT_8723D_1ANT_GNT_TYPE_CTRL_BY_PTA,
- BT_8723D_1ANT_SIG_STA_SET_BY_HW);
-
- coex_sta->gnt_control_by_PTA = true;
- }
-
- if (force_exec ||
- (coex_dm->cur_ant_pos_type !=
- coex_dm->pre_ant_pos_type)) {
- /* internal switch setting */
- switch (ant_pos_type) {
- case BTC_ANT_PATH_WIFI:
- if (board_info->btdm_ant_pos ==
- BTC_ANTENNA_AT_MAIN_PORT) {
- u16tmp1 = btcoexist->btc_read_2byte(
- btcoexist, 0x948);
- if ((u16tmp1 == 0x140) ||
- (u16tmp1 == 0x40))
- btcoexist->btc_write_2byte(
- btcoexist, 0x948,
- u16tmp1);
- else
- btcoexist->btc_write_2byte(
- btcoexist, 0x948, 0x0);
- } else {
- u16tmp1 = btcoexist->btc_read_2byte(
- btcoexist, 0x948);
- if ((u16tmp1 == 0x140) ||
- (u16tmp1 == 0x40))
- btcoexist->btc_write_2byte(
- btcoexist, 0x948,
- u16tmp1);
- else
- btcoexist->btc_write_2byte(
- btcoexist, 0x948,
- 0x280);
- }
- break;
- case BTC_ANT_PATH_BT:
- if (board_info->btdm_ant_pos ==
- BTC_ANTENNA_AT_MAIN_PORT) {
- u16tmp1 = btcoexist->btc_read_2byte(
- btcoexist, 0x948);
- if ((u16tmp1 == 0x140) ||
- (u16tmp1 == 0x40))
- btcoexist->btc_write_2byte(
- btcoexist, 0x948,
- u16tmp1);
- else
- btcoexist->btc_write_2byte(
- btcoexist, 0x948,
- 0x280);
- } else {
- u16tmp1 = btcoexist->btc_read_2byte(
- btcoexist, 0x948);
- if ((u16tmp1 == 0x140) ||
- (u16tmp1 == 0x40))
- btcoexist->btc_write_2byte(
- btcoexist, 0x948,
- u16tmp1);
- else
- btcoexist->btc_write_2byte(
- btcoexist, 0x948, 0x0);
- }
- break;
- default:
- case BTC_ANT_PATH_PTA:
- if (board_info->btdm_ant_pos ==
- BTC_ANTENNA_AT_MAIN_PORT)
- btcoexist->btc_write_2byte(
- btcoexist, 0x948,
- 0x200);
- else
- btcoexist->btc_write_2byte(
- btcoexist, 0x948, 0x80);
- break;
- }
- }
-
-
-#if 1
- u32tmp1 = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
- u32tmp2 = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
- u16tmp1 = btcoexist->btc_read_2byte(btcoexist, 0x948);
- u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73);
-
- if (init_hwcfg) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (After Ant-Setup Init) 0x948 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n",
- u16tmp1, u8tmp, u32tmp1, u32tmp2);
- BTC_TRACE(trace_buf);
- } else if (wifi_off) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (After Ant-Setup WiFi off) 0x948 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n",
- u16tmp1, u8tmp, u32tmp1, u32tmp2);
- BTC_TRACE(trace_buf);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (After Ant-Setup Run time) 0x948 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n",
- u16tmp1, u8tmp, u32tmp1, u32tmp2);
- BTC_TRACE(trace_buf);
- }
-#endif
-
- coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type;
-}
-
-
-boolean halbtc8723d1ant_is_common_action(IN struct btc_coexist *btcoexist)
-{
- boolean common = false, wifi_connected = false, wifi_busy = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- if (!wifi_connected &&
- BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
- coex_dm->bt_status) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n");
- BTC_TRACE(trace_buf);
-
- /* halbtc8723d1ant_sw_mechanism(btcoexist, false); */
-
- common = true;
- } else if (wifi_connected &&
- (BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
- coex_dm->bt_status)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi connected + BT non connected-idle!!\n");
- BTC_TRACE(trace_buf);
-
- /* halbtc8723d1ant_sw_mechanism(btcoexist, false); */
-
- common = true;
- } else if (!wifi_connected &&
- (BT_8723D_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi non connected-idle + BT connected-idle!!\n");
- BTC_TRACE(trace_buf);
-
- /* halbtc8723d1ant_sw_mechanism(btcoexist, false); */
-
- common = true;
- } else if (wifi_connected &&
- (BT_8723D_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi connected + BT connected-idle!!\n");
- BTC_TRACE(trace_buf);
-
- /* halbtc8723d1ant_sw_mechanism(btcoexist, false); */
-
- common = true;
- } else if (!wifi_connected &&
- (BT_8723D_1ANT_BT_STATUS_CONNECTED_IDLE != coex_dm->bt_status)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi non connected-idle + BT Busy!!\n");
- BTC_TRACE(trace_buf);
-
- /* halbtc8723d1ant_sw_mechanism(btcoexist, false); */
-
- common = true;
- } else {
- if (wifi_busy) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi Connected-Busy + BT Busy!!\n");
- BTC_TRACE(trace_buf);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi Connected-Idle + BT Busy!!\n");
- BTC_TRACE(trace_buf);
- }
-
- common = false;
- }
-
- return common;
-}
-
-
-/* *********************************************
- *
- * Software Coex Mechanism start
- *
- * ********************************************* */
-
-/* SCO only or SCO+PAN(HS) */
-
-/*
-void halbtc8723d1ant_action_sco(IN struct btc_coexist* btcoexist)
-{
- halbtc8723d1ant_sw_mechanism(btcoexist, true);
-}
-
-
-void halbtc8723d1ant_action_hid(IN struct btc_coexist* btcoexist)
-{
- halbtc8723d1ant_sw_mechanism(btcoexist, true);
-}
-
-
-void halbtc8723d1ant_action_a2dp(IN struct btc_coexist* btcoexist)
-{
- halbtc8723d1ant_sw_mechanism(btcoexist, false);
-}
-
-void halbtc8723d1ant_action_a2dp_pan_hs(IN struct btc_coexist* btcoexist)
-{
- halbtc8723d1ant_sw_mechanism(btcoexist, false);
-}
-
-void halbtc8723d1ant_action_pan_edr(IN struct btc_coexist* btcoexist)
-{
- halbtc8723d1ant_sw_mechanism(btcoexist, false);
-}
-
-
-void halbtc8723d1ant_action_pan_hs(IN struct btc_coexist* btcoexist)
-{
- halbtc8723d1ant_sw_mechanism(btcoexist, false);
-}
-
-
-void halbtc8723d1ant_action_pan_edr_a2dp(IN struct btc_coexist* btcoexist)
-{
- halbtc8723d1ant_sw_mechanism(btcoexist, false);
-}
-
-void halbtc8723d1ant_action_pan_edr_hid(IN struct btc_coexist* btcoexist)
-{
- halbtc8723d1ant_sw_mechanism(btcoexist, true);
-}
-
-
-void halbtc8723d1ant_action_hid_a2dp_pan_edr(IN struct btc_coexist* btcoexist)
-{
- halbtc8723d1ant_sw_mechanism(btcoexist, true);
-}
-
-void halbtc8723d1ant_action_hid_a2dp(IN struct btc_coexist* btcoexist)
-{
- halbtc8723d1ant_sw_mechanism(btcoexist, true);
-}
-
-*/
-
-/* *********************************************
- *
- * Non-Software Coex Mechanism start
- *
- * ********************************************* */
-void halbtc8723d1ant_action_bt_whck_test(IN struct btc_coexist *btcoexist)
-{
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC,
- false, false);
- halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-}
-
-void halbtc8723d1ant_action_wifi_only(IN struct btc_coexist *btcoexist)
-{
- halbtc8723d1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8);
- halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, FORCE_EXEC,
- false, false);
- halbtc8723d1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
-}
-
-void halbtc8723d1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist)
-{
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC,
- false, false);
- halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
-}
-
-void halbtc8723d1ant_action_hs(IN struct btc_coexist *btcoexist)
-{
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
- halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
-}
-
-void halbtc8723d1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_connected = false, ap_enable = false, wifi_busy = false,
- bt_busy = false;
- boolean wifi_scan = false, wifi_link = false, wifi_roam = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
- &ap_enable);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam);
-
- if ((wifi_link) || (wifi_roam) || (coex_sta->wifi_is_high_pri_task)) {
-
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33);
- halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6);
-
- } else if ((wifi_scan) && (coex_sta->bt_create_connection)) {
-
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22);
- halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6);
-
- } else if ((!wifi_connected) && (!wifi_scan)) {
-
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
-
- halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
- } else if ((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) {
-
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22);
- halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
-
- } else if (bt_link_info->a2dp_exist) {
-
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
-
- halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- } else if (wifi_scan) {
-
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
-
- halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
-
- } else if (wifi_busy) {
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 21);
-
- halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- } else {
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 19);
-
- halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- }
-}
-
-void halbtc8723d1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist
- *btcoexist, IN u8 wifi_status)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_connected = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
-
- /* tdma and coex table */
-
- if (bt_link_info->sco_exist) {
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
- halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
- } else { /* HID */
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 6);
- halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
- }
-}
-
-void halbtc8723d1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist
- *btcoexist, IN u8 wifi_status)
-{
-
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_busy = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- if (bt_link_info->hid_only) { /* HID */
- halbtc8723d1ant_action_bt_sco_hid_only_busy(btcoexist,
- wifi_status);
- coex_dm->auto_tdma_adjust = false;
- return;
- } else if (bt_link_info->a2dp_only) { /* A2DP */
- if (BT_8723D_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifi_status) {
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 32);
- halbtc8723d1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- coex_dm->auto_tdma_adjust = false;
- } else {
-
- if (coex_sta->scan_ap_num >=
- BT_8723D_1ANT_WIFI_NOISY_THRESH) {
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 17);
- } else {
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 7);
- }
-
- halbtc8723d1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- coex_dm->auto_tdma_adjust = true;
- }
- } else if (((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) ||
- (bt_link_info->hid_exist && bt_link_info->a2dp_exist &&
- bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */
-
- if (wifi_busy) {
-
- if ((coex_sta->a2dp_bit_pool > 40) && (coex_sta->a2dp_bit_pool < 255))
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 15);
- else
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13);
- } else
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14);
-
- halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
- coex_dm->auto_tdma_adjust = false;
- } else if (bt_link_info->hid_exist &&
- bt_link_info->a2dp_exist) { /* HID+A2DP */
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 8);
- coex_dm->auto_tdma_adjust = false;
-
- halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
- } else if ((bt_link_info->pan_only) || (bt_link_info->hid_exist &&
- bt_link_info->pan_exist)) { /* PAN(OPP,FTP), HID+PAN(OPP,FTP) */
- if (BT_8723D_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifi_status)
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 4);
- else
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3);
-
- halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
- coex_dm->auto_tdma_adjust = false;
- } else {
- /* BT no-profile busy (0x9) */
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 33);
- halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- coex_dm->auto_tdma_adjust = false;
- }
-}
-
-void halbtc8723d1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist)
-{
- /* tdma and coex table */
- halbtc8723d1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8);
- halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC,
- false, false);
- halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-}
-
-void halbtc8723d1ant_action_wifi_not_connected_scan(IN struct btc_coexist
- *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_connected = false, bt_hs_on = false;
- u32 wifi_link_status = 0;
- u32 num_of_wifi_link = 0;
- boolean bt_ctrl_agg_buf_size = false;
- u8 agg_buf_size = 5;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
-
- num_of_wifi_link = wifi_link_status >> 16;
-
- if (num_of_wifi_link >= 2) {
- halbtc8723d1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
- halbtc8723d1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
- bt_ctrl_agg_buf_size, agg_buf_size);
-
- if (coex_sta->c2h_bt_inquiry_page) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], BT Is Inquirying\n");
- BTC_TRACE(trace_buf);
- halbtc8723d1ant_action_bt_inquiry(btcoexist);
- } else
- halbtc8723d1ant_action_wifi_multi_port(btcoexist);
- return;
- }
-
- if (coex_sta->c2h_bt_inquiry_page) {
- halbtc8723d1ant_action_bt_inquiry(btcoexist);
- return;
- } else if (bt_hs_on) {
- halbtc8723d1ant_action_hs(btcoexist);
- return;
- }
-
- /* tdma and coex table */
- if (BT_8723D_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
- if (bt_link_info->a2dp_exist) {
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 32);
- halbtc8723d1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- } else if (bt_link_info->a2dp_exist &&
- bt_link_info->pan_exist) {
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 22);
- halbtc8723d1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- } else {
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
- halbtc8723d1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- }
- } else if ((BT_8723D_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
- (BT_8723D_1ANT_BT_STATUS_ACL_SCO_BUSY ==
- coex_dm->bt_status)) {
- halbtc8723d1ant_action_bt_sco_hid_only_busy(btcoexist,
- BT_8723D_1ANT_WIFI_STATUS_CONNECTED_SCAN);
- } else {
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
- NORMAL_EXEC, false, false);
- halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
- }
-}
-
-void halbtc8723d1ant_action_wifi_connected_scan(IN struct btc_coexist
- *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_connected = false, bt_hs_on = false;
- u32 wifi_link_status = 0;
- u32 num_of_wifi_link = 0;
- boolean bt_ctrl_agg_buf_size = false;
- u8 agg_buf_size = 5;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
-
- num_of_wifi_link = wifi_link_status >> 16;
-
- if (num_of_wifi_link >= 2) {
- halbtc8723d1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
- halbtc8723d1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
- bt_ctrl_agg_buf_size, agg_buf_size);
-
- if (coex_sta->c2h_bt_inquiry_page) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], BT Is Inquirying\n");
- BTC_TRACE(trace_buf);
- halbtc8723d1ant_action_bt_inquiry(btcoexist);
- } else
- halbtc8723d1ant_action_wifi_multi_port(btcoexist);
- return;
- }
-
- if (coex_sta->c2h_bt_inquiry_page) {
- halbtc8723d1ant_action_bt_inquiry(btcoexist);
- return;
- } else if (bt_hs_on) {
- halbtc8723d1ant_action_hs(btcoexist);
- return;
- }
-
-
- /* tdma and coex table */
- if (BT_8723D_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
- if (bt_link_info->a2dp_exist) {
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 32);
- halbtc8723d1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- } else if (bt_link_info->a2dp_exist &&
- bt_link_info->pan_exist) {
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 22);
- halbtc8723d1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- } else {
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
- halbtc8723d1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- }
- } else if ((BT_8723D_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
- (BT_8723D_1ANT_BT_STATUS_ACL_SCO_BUSY ==
- coex_dm->bt_status)) {
- halbtc8723d1ant_action_bt_sco_hid_only_busy(btcoexist,
- BT_8723D_1ANT_WIFI_STATUS_CONNECTED_SCAN);
- } else {
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
- NORMAL_EXEC, false, false);
- halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
- }
-}
-
-void halbtc8723d1ant_action_wifi_not_connected_asso_auth(
- IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_connected = false, bt_hs_on = false;
- u32 wifi_link_status = 0;
- u32 num_of_wifi_link = 0;
- boolean bt_ctrl_agg_buf_size = false;
- u8 agg_buf_size = 5;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
-
- num_of_wifi_link = wifi_link_status >> 16;
-
- if (num_of_wifi_link >= 2) {
- halbtc8723d1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
- halbtc8723d1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
- bt_ctrl_agg_buf_size, agg_buf_size);
-
- if (coex_sta->c2h_bt_inquiry_page) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], BT Is Inquirying\n");
- BTC_TRACE(trace_buf);
- halbtc8723d1ant_action_bt_inquiry(btcoexist);
- } else
- halbtc8723d1ant_action_wifi_multi_port(btcoexist);
- return;
- }
-
- if (coex_sta->c2h_bt_inquiry_page) {
- halbtc8723d1ant_action_bt_inquiry(btcoexist);
- return;
- } else if (bt_hs_on) {
- halbtc8723d1ant_action_hs(btcoexist);
- return;
- }
-
- /* tdma and coex table */
- if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist) ||
- (bt_link_info->a2dp_exist)) {
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
- halbtc8723d1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4);
- } else if (bt_link_info->pan_exist) {
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
- halbtc8723d1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 4);
- } else {
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
- NORMAL_EXEC, false, false);
- halbtc8723d1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 2);
- }
-}
-
-void halbtc8723d1ant_action_wifi_connected_specific_packet(
- IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_connected = false, bt_hs_on = false;
- u32 wifi_link_status = 0;
- u32 num_of_wifi_link = 0;
- boolean bt_ctrl_agg_buf_size = false;
- u8 agg_buf_size = 5;
- boolean wifi_busy = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
-
- num_of_wifi_link = wifi_link_status >> 16;
-
- if (num_of_wifi_link >= 2) {
- halbtc8723d1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
- halbtc8723d1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
- bt_ctrl_agg_buf_size, agg_buf_size);
-
- if (coex_sta->c2h_bt_inquiry_page) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], BT Is Inquirying\n");
- BTC_TRACE(trace_buf);
- halbtc8723d1ant_action_bt_inquiry(btcoexist);
- } else
- halbtc8723d1ant_action_wifi_multi_port(btcoexist);
- return;
- }
-
- if (coex_sta->c2h_bt_inquiry_page) {
- halbtc8723d1ant_action_bt_inquiry(btcoexist);
- return;
- } else if (bt_hs_on) {
- halbtc8723d1ant_action_hs(btcoexist);
- return;
- }
-
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- /* no specific packet process for both WiFi and BT very busy */
- if ((wifi_busy) && ((bt_link_info->pan_exist) ||
- (coex_sta->num_of_profile >= 2)))
- return;
-
- /* tdma and coex table */
- if ((bt_link_info->sco_exist) || (bt_link_info->hid_exist)) {
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
- halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
- } else if (bt_link_info->a2dp_exist) {
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
- halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- } else if (bt_link_info->pan_exist) {
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
- halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
- } else {
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
- halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
- NORMAL_EXEC, false, false);
- halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
- }
-}
-
-void halbtc8723d1ant_action_wifi_connected(IN struct btc_coexist *btcoexist)
-{
- boolean wifi_busy = false;
- boolean scan = false, link = false, roam = false;
- boolean under_4way = false, ap_enable = false;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CoexForWifiConnect()===>\n");
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
- &under_4way);
- if (under_4way) {
- halbtc8723d1ant_action_wifi_connected_specific_packet(btcoexist);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CoexForWifiConnect(), return for wifi is under 4way<===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
- if (scan || link || roam) {
- if (scan)
- halbtc8723d1ant_action_wifi_connected_scan(btcoexist);
- else
- halbtc8723d1ant_action_wifi_connected_specific_packet(
- btcoexist);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CoexForWifiConnect(), return for wifi is under scan<===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
- &ap_enable);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
-
- /* tdma and coex table */
- if (!wifi_busy) {
- if (BT_8723D_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
- halbtc8723d1ant_action_wifi_connected_bt_acl_busy(
- btcoexist,
- BT_8723D_1ANT_WIFI_STATUS_CONNECTED_IDLE);
- } else if ((BT_8723D_1ANT_BT_STATUS_SCO_BUSY ==
- coex_dm->bt_status) ||
- (BT_8723D_1ANT_BT_STATUS_ACL_SCO_BUSY ==
- coex_dm->bt_status)) {
- halbtc8723d1ant_action_bt_sco_hid_only_busy(btcoexist,
- BT_8723D_1ANT_WIFI_STATUS_CONNECTED_IDLE);
- } else {
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 8);
- halbtc8723d1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_PTA, NORMAL_EXEC, false, false);
- halbtc8723d1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 2);
- }
- } else {
- if (BT_8723D_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
- halbtc8723d1ant_action_wifi_connected_bt_acl_busy(
- btcoexist,
- BT_8723D_1ANT_WIFI_STATUS_CONNECTED_BUSY);
- } else if ((BT_8723D_1ANT_BT_STATUS_SCO_BUSY ==
- coex_dm->bt_status) ||
- (BT_8723D_1ANT_BT_STATUS_ACL_SCO_BUSY ==
- coex_dm->bt_status)) {
- halbtc8723d1ant_action_bt_sco_hid_only_busy(btcoexist,
- BT_8723D_1ANT_WIFI_STATUS_CONNECTED_BUSY);
- } else {
- /* halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8); */
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
- 32);
- halbtc8723d1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_PTA, NORMAL_EXEC, false, false);
- /* halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); */
- halbtc8723d1ant_coex_table_with_type(btcoexist,
- NORMAL_EXEC, 4);
- }
- }
-}
-
-void halbtc8723d1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist)
-{
- u8 algorithm = 0;
-
- algorithm = halbtc8723d1ant_action_algorithm(btcoexist);
- coex_dm->cur_algorithm = algorithm;
-
- if (halbtc8723d1ant_is_common_action(btcoexist)) {
-
- } else {
- switch (coex_dm->cur_algorithm) {
- case BT_8723D_1ANT_COEX_ALGO_SCO:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = SCO.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8723d1ant_action_sco(btcoexist); */
- break;
- case BT_8723D_1ANT_COEX_ALGO_HID:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = HID.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8723d1ant_action_hid(btcoexist); */
- break;
- case BT_8723D_1ANT_COEX_ALGO_A2DP:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = A2DP.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8723d1ant_action_a2dp(btcoexist); */
- break;
- case BT_8723D_1ANT_COEX_ALGO_A2DP_PANHS:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = A2DP+PAN(HS).\n");
- BTC_TRACE(trace_buf);
- /* halbtc8723d1ant_action_a2dp_pan_hs(btcoexist); */
- break;
- case BT_8723D_1ANT_COEX_ALGO_PANEDR:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = PAN(EDR).\n");
- BTC_TRACE(trace_buf);
- /* halbtc8723d1ant_action_pan_edr(btcoexist); */
- break;
- case BT_8723D_1ANT_COEX_ALGO_PANHS:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = HS mode.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8723d1ant_action_pan_hs(btcoexist); */
- break;
- case BT_8723D_1ANT_COEX_ALGO_PANEDR_A2DP:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = PAN+A2DP.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8723d1ant_action_pan_edr_a2dp(btcoexist); */
- break;
- case BT_8723D_1ANT_COEX_ALGO_PANEDR_HID:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = PAN(EDR)+HID.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8723d1ant_action_pan_edr_hid(btcoexist); */
- break;
- case BT_8723D_1ANT_COEX_ALGO_HID_A2DP_PANEDR:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = HID+A2DP+PAN.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8723d1ant_action_hid_a2dp_pan_edr(btcoexist); */
- break;
- case BT_8723D_1ANT_COEX_ALGO_HID_A2DP:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = HID+A2DP.\n");
- BTC_TRACE(trace_buf);
- /* halbtc8723d1ant_action_hid_a2dp(btcoexist); */
- break;
- default:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action algorithm = coexist All Off!!\n");
- BTC_TRACE(trace_buf);
- /* halbtc8723d1ant_coex_all_off(btcoexist); */
- break;
- }
- coex_dm->pre_algorithm = coex_dm->cur_algorithm;
- }
-}
-
-
-void halbtc8723d1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean wifi_connected = false, bt_hs_on = false;
- boolean increase_scan_dev_num = false;
- boolean bt_ctrl_agg_buf_size = false;
- boolean miracast_plus_bt = false;
- u8 agg_buf_size = 5;
- u32 wifi_link_status = 0;
- u32 num_of_wifi_link = 0, wifi_bw;
- u8 iot_peer = BTC_IOT_PEER_UNKNOWN;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism()===>\n");
- BTC_TRACE(trace_buf);
-
- if (btcoexist->manual_control) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- if (btcoexist->stop_coex_dm) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- if (coex_sta->under_ips) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], wifi is under IPS !!!\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- if (coex_sta->bt_whck_test) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is under WHCK TEST!!!\n");
- BTC_TRACE(trace_buf);
- halbtc8723d1ant_action_bt_whck_test(btcoexist);
- return;
- }
-
- if (coex_sta->bt_disabled) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is disabled !!!\n");
- halbtc8723d1ant_action_wifi_only(btcoexist);
- return;
- }
-
- if ((BT_8723D_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
- (BT_8723D_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
- (BT_8723D_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status))
- increase_scan_dev_num = true;
-
- btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM,
- &increase_scan_dev_num);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
- num_of_wifi_link = wifi_link_status >> 16;
-
- if ((num_of_wifi_link >= 2) ||
- (wifi_link_status & WIFI_P2P_GO_CONNECTED)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n",
- num_of_wifi_link, wifi_link_status);
- BTC_TRACE(trace_buf);
-
- if (bt_link_info->bt_link_exist) {
- halbtc8723d1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1,
- 0, 1);
- miracast_plus_bt = true;
- } else {
- halbtc8723d1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
- miracast_plus_bt = false;
- }
- btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
- &miracast_plus_bt);
- halbtc8723d1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
- bt_ctrl_agg_buf_size, agg_buf_size);
-
- if (coex_sta->c2h_bt_inquiry_page) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], BT Is Inquirying\n");
- BTC_TRACE(trace_buf);
- halbtc8723d1ant_action_bt_inquiry(btcoexist);
- } else
- halbtc8723d1ant_action_wifi_multi_port(btcoexist);
-
-
- return;
- } else {
- miracast_plus_bt = false;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
- &miracast_plus_bt);
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
-
- if ((bt_link_info->bt_link_exist) && (wifi_connected)) {
- halbtc8723d1ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 1, 0, 1);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer);
-
- if (BTC_IOT_PEER_CISCO != iot_peer) {
- if (bt_link_info->sco_exist) /* if (bt_link_info->bt_hi_pri_link_exist) */
- halbtc8723d1ant_limited_rx(btcoexist,
- NORMAL_EXEC, true, false, 0x5);
- else
- halbtc8723d1ant_limited_rx(btcoexist,
- NORMAL_EXEC, false, false, 0x5);
- } else {
- if (bt_link_info->sco_exist)
- halbtc8723d1ant_limited_rx(btcoexist,
- NORMAL_EXEC, true, false, 0x5);
- else {
- if (BTC_WIFI_BW_HT40 == wifi_bw)
- halbtc8723d1ant_limited_rx(btcoexist,
- NORMAL_EXEC, false, true, 0x10);
- else
- halbtc8723d1ant_limited_rx(btcoexist,
- NORMAL_EXEC, false, true, 0x8);
- }
- }
-
- halbtc8723d1ant_sw_mechanism(btcoexist, true);
- halbtc8723d1ant_run_sw_coexist_mechanism(
- btcoexist); /* just print debug message */
- } else {
- halbtc8723d1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
-
- halbtc8723d1ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
- 0x5);
-
- halbtc8723d1ant_sw_mechanism(btcoexist, false);
- halbtc8723d1ant_run_sw_coexist_mechanism(
- btcoexist); /* just print debug message */
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- if (coex_sta->c2h_bt_inquiry_page) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], BT Is Inquirying\n");
- BTC_TRACE(trace_buf);
- halbtc8723d1ant_action_bt_inquiry(btcoexist);
- return;
- } else if (bt_hs_on) {
- halbtc8723d1ant_action_hs(btcoexist);
- return;
- }
-
-
- if (!wifi_connected) {
- boolean scan = false, link = false, roam = false;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], wifi is non connected-idle !!!\n");
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
-
- if (scan || link || roam) {
- if (scan)
- halbtc8723d1ant_action_wifi_not_connected_scan(
- btcoexist);
- else
- halbtc8723d1ant_action_wifi_not_connected_asso_auth(
- btcoexist);
- } else
- halbtc8723d1ant_action_wifi_not_connected(btcoexist);
- } else /* wifi LPS/Busy */
- halbtc8723d1ant_action_wifi_connected(btcoexist);
-}
-
-void halbtc8723d1ant_init_coex_dm(IN struct btc_coexist *btcoexist)
-{
- /* force to reset coex mechanism */
-
- /* sw all off */
- halbtc8723d1ant_sw_mechanism(btcoexist, false);
-
- coex_sta->pop_event_cnt = 0;
-}
-
-void halbtc8723d1ant_init_hw_config(IN struct btc_coexist *btcoexist,
- IN boolean back_up, IN boolean wifi_only)
-{
- u32 u32tmp1 = 0, u32tmp2 = 0;
- u16 u16tmp1 = 0;
- struct btc_board_info *board_info = &btcoexist->board_info;
-
-
- u16tmp1 = btcoexist->btc_read_2byte(btcoexist, 0x948);
- u32tmp1 = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
- u32tmp2 = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (Before Init HW config) 0x948= 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n",
- u16tmp1, u32tmp1, u32tmp2);
- BTC_TRACE(trace_buf);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], 1Ant Init HW Config!!\n");
- BTC_TRACE(trace_buf);
-
- /* 0xf0[15:12] --> Chip Cut information */
- coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist,
- 0xf1) & 0xf0) >> 4;
-
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8,
- 0x1); /* enable TBTT nterrupt */
-
- /* BT report packet sample rate */
- btcoexist->btc_write_1byte(btcoexist, 0x790, 0x5);
-
- /* Init 0x778 = 0x1 for 1-Ant */
- btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1);
-
- /* Enable PTA (3-wire function form BT side) */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x41, 0x02, 0x1);
-
- /* Enable PTA (tx/rx signal form WiFi side) */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4c6, 0x10, 0x1);
-
- halbtc8723d1ant_enable_gnt_to_gpio(btcoexist, FALSE);
-
- /* check if WL firmware download ok */
- if (btcoexist->btc_read_1byte(btcoexist, 0x80) == 0xc6)
- halbtc8723d1ant_post_onoffstate_to_bt(btcoexist, true);
-
- halbtc8723d1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8);
-
- /* Antenna config */
- if (wifi_only) {
- coex_sta->concurrent_rx_mode_on = false;
- halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_WIFI,
- FORCE_EXEC, true, false);
- halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_WIFI,
- FORCE_EXEC, false, false);
- } else {
- coex_sta->concurrent_rx_mode_on = true;
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x2, 0x1);
- /* RF 0x1[0] = 0->Set GNT_WL_RF_Rx always = 1 for con-current Rx */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0x1, 0x0);
- halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT,
- FORCE_EXEC, true, false);
-
- if (board_info->btdm_ant_pos ==
- BTC_ANTENNA_AT_MAIN_PORT) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** Single Antenna, Antenna at Main Port: S1**********\n");
- BTC_TRACE(trace_buf);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** Single Antenna, Antenna at Aux Port: S0**********\n");
- BTC_TRACE(trace_buf);
- }
- }
-
- /* PTA parameter */
- halbtc8723d1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
-
- psd_scan->ant_det_is_ant_det_available = TRUE;
-
-}
-
-u32 halbtc8723d1ant_psd_log2base(IN struct btc_coexist *btcoexist, IN u32 val)
-{
- u8 j;
- u32 tmp, tmp2, val_integerd_b = 0, tindex, shiftcount = 0;
- u32 result, val_fractiond_b = 0, table_fraction[21] = {0, 432, 332, 274, 232, 200,
- 174, 151, 132, 115, 100, 86, 74, 62, 51, 42,
- 32, 23, 15, 7, 0
- };
-
- if (val == 0)
- return 0;
-
- tmp = val;
-
- while (1) {
- if (tmp == 1)
- break;
- else {
- tmp = (tmp >> 1);
- shiftcount++;
- }
- }
-
-
- val_integerd_b = shiftcount + 1;
-
- tmp2 = 1;
- for (j = 1; j <= val_integerd_b; j++)
- tmp2 = tmp2 * 2;
-
- tmp = (val * 100) / tmp2;
- tindex = tmp / 5;
-
- if (tindex > 20)
- tindex = 20;
-
- val_fractiond_b = table_fraction[tindex];
-
- result = val_integerd_b * 100 - val_fractiond_b;
-
- return result;
-
-
-}
-
-void halbtc8723d1ant_psd_show_antenna_detect_result(IN struct btc_coexist
- *btcoexist)
-{
- u8 *cli_buf = btcoexist->cli_buf;
- struct btc_board_info *board_info = &btcoexist->board_info;
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n============[Antenna Detection info] ============\n");
- CL_PRINTF(cli_buf);
-
- if (psd_scan->ant_det_result == 1)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (>%d)",
- "Ant Det Result", "2-Antenna (Bad-Isolation)",
- BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION);
- else if (psd_scan->ant_det_result == 2)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (%d~%d)",
- "Ant Det Result", "2-Antenna (Good-Isolation)",
- BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION
- + psd_scan->ant_det_thres_offset,
- BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (%d~%d)",
- "Ant Det Result", "1-Antenna",
- BT_8723D_1ANT_ANTDET_PSDTHRES_1ANT,
- BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION
- + psd_scan->ant_det_thres_offset);
-
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s ",
- "Antenna Detection Finish",
- (board_info->btdm_ant_det_finish
- ? "Yes" : "No"));
- CL_PRINTF(cli_buf);
-
- switch (psd_scan->ant_det_result) {
- case 0:
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "(BT is not available)");
- break;
- case 1: /* 2-Ant bad-isolation */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "(BT is available)");
- break;
- case 2: /* 2-Ant good-isolation */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "(BT is available)");
- break;
- case 3: /* 1-Ant */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "(BT is available)");
- break;
- case 4:
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "(Uncertainty result)");
- break;
- case 5:
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "(Pre-Scan fai)");
- break;
- case 6:
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "(WiFi is Scanning)");
- break;
- case 7:
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "(BT is not idle)");
- break;
- case 8:
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "(Abort by WiFi Scanning)");
- break;
- case 9:
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "(Antenna Init is not ready)");
- break;
- case 10:
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "(BT is Inquiry or page)");
- break;
- case 11:
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "(BT is Disabled)");
- break;
- }
- CL_PRINTF(cli_buf);
-
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
- "Ant Detect Total Count", psd_scan->ant_det_try_count);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
- "Ant Detect Fail Count", psd_scan->ant_det_fail_count);
- CL_PRINTF(cli_buf);
-
- if ((!board_info->btdm_ant_det_finish) &&
- (psd_scan->ant_det_result != 5))
- return;
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "BT Response",
- (psd_scan->ant_det_result ? "ok" : "fail"));
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ms", "BT Tx Time",
- psd_scan->ant_det_bt_tx_time);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "BT Tx Ch",
- psd_scan->ant_det_bt_le_channel);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d",
- "WiFi PSD Cent-Ch/Offset/Span",
- psd_scan->real_cent_freq, psd_scan->real_offset,
- psd_scan->real_span);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d dB",
- "PSD Pre-Scan Peak Value",
- psd_scan->ant_det_pre_psdscan_peak_val / 100);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (<= %d)",
- "PSD Pre-Scan result",
- (psd_scan->ant_det_result != 5 ? "ok" : "fail"),
- BT_8723D_1ANT_ANTDET_PSDTHRES_BACKGROUND
- + psd_scan->ant_det_thres_offset);
- CL_PRINTF(cli_buf);
-
- if (psd_scan->ant_det_result == 5)
- return;
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s dB",
- "PSD Scan Peak Value", psd_scan->ant_det_peak_val);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s MHz",
- "PSD Scan Peak Freq", psd_scan->ant_det_peak_freq);
- CL_PRINTF(cli_buf);
-
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "TFBGA Package",
- (board_info->tfbga_package) ? "Yes" : "No");
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
- "PSD Threshold Offset", psd_scan->ant_det_thres_offset);
- CL_PRINTF(cli_buf);
-
-}
-
-
-
-void halbtc8723d1ant_psd_showdata(IN struct btc_coexist *btcoexist)
-{
- u8 *cli_buf = btcoexist->cli_buf;
- u32 delta_freq_per_point;
- u32 freq, freq1, freq2, n = 0, i = 0, j = 0, m = 0, psd_rep1, psd_rep2;
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n\n============[PSD info] (%d)============\n",
- psd_scan->psd_gen_count);
- CL_PRINTF(cli_buf);
-
- if (psd_scan->psd_gen_count == 0) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n No data !!\n");
- CL_PRINTF(cli_buf);
- return;
- }
-
- if (psd_scan->psd_point == 0)
- delta_freq_per_point = 0;
- else
- delta_freq_per_point = psd_scan->psd_band_width /
- psd_scan->psd_point;
-
- /* if (psd_scan->is_psd_show_max_only) */
- if (0) {
- psd_rep1 = psd_scan->psd_max_value / 100;
- psd_rep2 = psd_scan->psd_max_value - psd_rep1 * 100;
-
- freq = ((psd_scan->real_cent_freq - 20) * 1000000 +
- psd_scan->psd_max_value_point * delta_freq_per_point);
- freq1 = freq / 1000000;
- freq2 = freq / 1000 - freq1 * 1000;
-
- if (freq2 < 100)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n Freq = %d.0%d MHz",
- freq1, freq2);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n Freq = %d.%d MHz",
- freq1, freq2);
-
- if (psd_rep2 < 10)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- ", Value = %d.0%d dB, (%d)\n",
- psd_rep1, psd_rep2, psd_scan->psd_max_value);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- ", Value = %d.%d dB, (%d)\n",
- psd_rep1, psd_rep2, psd_scan->psd_max_value);
-
- CL_PRINTF(cli_buf);
- } else {
- m = psd_scan->psd_start_point;
- n = psd_scan->psd_start_point;
- i = 1;
- j = 1;
-
- while (1) {
- do {
- freq = ((psd_scan->real_cent_freq - 20) * 1000000 + m *
- delta_freq_per_point);
- freq1 = freq / 1000000;
- freq2 = freq / 1000 - freq1 * 1000;
-
- if (i == 1) {
- if (freq2 == 0)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n Freq%6d.000", freq1);
- else if (freq2 < 100)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n Freq%6d.0%2d", freq1,
- freq2);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n Freq%6d.%3d", freq1,
- freq2);
- } else if ((i % 8 == 0) ||
- (m == psd_scan->psd_stop_point)) {
- if (freq2 == 0)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%6d.000\n", freq1);
- else if (freq2 < 100)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%6d.0%2d\n", freq1, freq2);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%6d.%3d\n", freq1, freq2);
- } else {
- if (freq2 == 0)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%6d.000", freq1);
- else if (freq2 < 100)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%6d.0%2d", freq1, freq2);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%6d.%3d", freq1, freq2);
- }
-
- i++;
- m++;
- CL_PRINTF(cli_buf);
-
- } while ((i <= 8) && (m <= psd_scan->psd_stop_point));
-
-
- do {
- psd_rep1 = psd_scan->psd_report_max_hold[n] / 100;
- psd_rep2 = psd_scan->psd_report_max_hold[n] - psd_rep1 *
- 100;
-
- if (j == 1) {
- if (psd_rep2 < 10)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n Val %7d.0%d", psd_rep1,
- psd_rep2);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n Val %7d.%d", psd_rep1,
- psd_rep2);
- } else if ((j % 8 == 0) ||
- (n == psd_scan->psd_stop_point)) {
- if (psd_rep2 < 10)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%7d.0%d\n", psd_rep1,
- psd_rep2);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%7d.%d\n", psd_rep1, psd_rep2);
- } else {
- if (psd_rep2 < 10)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%7d.0%d", psd_rep1, psd_rep2);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%7d.%d", psd_rep1, psd_rep2);
- }
-
- j++;
- n++;
- CL_PRINTF(cli_buf);
-
- } while ((j <= 8) && (n <= psd_scan->psd_stop_point));
-
- if ((m > psd_scan->psd_stop_point) ||
- (n > psd_scan->psd_stop_point))
- break;
- else {
- i = 1;
- j = 1;
- }
-
- }
- }
-
-
-}
-
-void halbtc8723d1ant_psd_maxholddata(IN struct btc_coexist *btcoexist,
- IN u32 gen_count)
-{
- u32 i = 0, i_max = 0, val_max = 0;
-
- if (gen_count == 1) {
- memcpy(psd_scan->psd_report_max_hold,
- psd_scan->psd_report,
- BT_8723D_1ANT_ANTDET_PSD_POINTS * sizeof(u32));
-
- for (i = psd_scan->psd_start_point;
- i <= psd_scan->psd_stop_point; i++) {
-
- }
-
- psd_scan->psd_max_value_point = 0;
- psd_scan->psd_max_value = 0;
-
- } else {
- for (i = psd_scan->psd_start_point;
- i <= psd_scan->psd_stop_point; i++) {
- if (psd_scan->psd_report[i] >
- psd_scan->psd_report_max_hold[i])
- psd_scan->psd_report_max_hold[i] =
- psd_scan->psd_report[i];
-
- /* search Max Value */
- if (i == psd_scan->psd_start_point) {
- i_max = i;
- val_max = psd_scan->psd_report_max_hold[i];
- } else {
- if (psd_scan->psd_report_max_hold[i] >
- val_max) {
- i_max = i;
- val_max = psd_scan->psd_report_max_hold[i];
- }
- }
-
-
- }
-
- psd_scan->psd_max_value_point = i_max;
- psd_scan->psd_max_value = val_max;
-
- }
-
-
-}
-
-u32 halbtc8723d1ant_psd_getdata(IN struct btc_coexist *btcoexist, IN u32 point)
-{
- /* reg 0x808[9:0]: FFT data x */
- /* reg 0x808[22]: 0-->1 to get 1 FFT data y */
- /* reg 0x8b4[15:0]: FFT data y report */
-
- u32 val = 0, psd_report = 0;
-
- val = btcoexist->btc_read_4byte(btcoexist, 0x808);
-
- val &= 0xffbffc00;
- val |= point;
-
- btcoexist->btc_write_4byte(btcoexist, 0x808, val);
-
- val |= 0x00400000;
- btcoexist->btc_write_4byte(btcoexist, 0x808, val);
-
-
- val = btcoexist->btc_read_4byte(btcoexist, 0x8b4);
-
- psd_report = val & 0x0000ffff;
-
- return psd_report;
-}
-
-
-boolean halbtc8723d1ant_psd_sweep_point(IN struct btc_coexist *btcoexist,
- IN u32 cent_freq, IN s32 offset, IN u32 span, IN u32 points,
- IN u32 avgnum, IN u32 loopcnt)
-{
- u32 i = 0, val = 0, n = 0, k = 0, j, point_index = 0;
- u32 points1 = 0, psd_report = 0;
- u32 start_p = 0, stop_p = 0, delta_freq_per_point = 156250;
- u32 psd_center_freq = 20 * 10 ^ 6;
- boolean outloop = false, scan , roam, is_sweep_ok = true;
- u8 flag = 0;
- u32 tmp = 0, u32tmp1 = 0;
- u32 wifi_original_channel = 1;
-
- psd_scan->is_psd_running = true;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx PSD Sweep Start!!\n");
- BTC_TRACE(trace_buf);
-
- do {
- switch (flag) {
- case 0: /* Get PSD parameters */
- default:
-
- psd_scan->psd_band_width = 40 * 1000000;
- psd_scan->psd_point = points;
- psd_scan->psd_start_base = points / 2;
- psd_scan->psd_avg_num = avgnum;
- psd_scan->real_cent_freq = cent_freq;
- psd_scan->real_offset = offset;
- psd_scan->real_span = span;
-
-
- points1 = psd_scan->psd_point;
- delta_freq_per_point = psd_scan->psd_band_width /
- psd_scan->psd_point;
-
- /* PSD point setup */
- val = btcoexist->btc_read_4byte(btcoexist, 0x808);
- val &= 0xffff0fff;
-
- switch (psd_scan->psd_point) {
- case 128:
- val |= 0x0;
- break;
- case 256:
- default:
- val |= 0x00004000;
- break;
- case 512:
- val |= 0x00008000;
- break;
- case 1024:
- val |= 0x0000c000;
- break;
- }
-
- switch (psd_scan->psd_avg_num) {
- case 1:
- val |= 0x0;
- break;
- case 8:
- val |= 0x00001000;
- break;
- case 16:
- val |= 0x00002000;
- break;
- case 32:
- default:
- val |= 0x00003000;
- break;
- }
- btcoexist->btc_write_4byte(btcoexist, 0x808, val);
-
- flag = 1;
- break;
- case 1: /* calculate the PSD point index from freq/offset/span */
- psd_center_freq = psd_scan->psd_band_width / 2 +
- offset * (1000000);
-
- start_p = psd_scan->psd_start_base + (psd_center_freq -
- span * (1000000) / 2) / delta_freq_per_point;
- psd_scan->psd_start_point = start_p -
- psd_scan->psd_start_base;
-
- stop_p = psd_scan->psd_start_base + (psd_center_freq +
- span * (1000000) / 2) / delta_freq_per_point;
- psd_scan->psd_stop_point = stop_p -
- psd_scan->psd_start_base - 1;
-
- flag = 2;
- break;
- case 2: /* set RF channel/BW/Mode */
-
- /* set 3-wire off */
- val = btcoexist->btc_read_4byte(btcoexist, 0x88c);
- val |= 0x00300000;
- btcoexist->btc_write_4byte(btcoexist, 0x88c, val);
-
- /* CCK off */
- val = btcoexist->btc_read_4byte(btcoexist, 0x800);
- val &= 0xfeffffff;
- btcoexist->btc_write_4byte(btcoexist, 0x800, val);
-
- /* Tx-pause on */
- btcoexist->btc_write_1byte(btcoexist, 0x522, 0x6f);
-
- /* store WiFi original channel */
- wifi_original_channel = btcoexist->btc_get_rf_reg(
- btcoexist, BTC_RF_A, 0x18, 0x3ff);
-
- /* Set RF channel */
- if (cent_freq == 2484)
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A,
- 0x18, 0x3ff, 0xe);
- else
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A,
- 0x18, 0x3ff, (cent_freq - 2412) / 5 +
- 1); /* WiFi TRx Mask on */
-
- /* save original RCK value */
- u32tmp1 = btcoexist->btc_get_rf_reg(
- btcoexist, BTC_RF_A, 0x1d, 0xfffff);
-
- /* Enter debug mode */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xde,
- 0x2, 0x1);
-
- /* Set RF Rx filter corner */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1d,
- 0xfffff, 0x2e);
-
-
- /* Set RF mode = Rx, RF Gain = 0x320a0 */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x0,
- 0xfffff, 0x320a0);
-
- while (1) {
- if (k++ > BT_8723D_1ANT_ANTDET_SWEEPPOINT_DELAY)
- break;
- }
- flag = 3;
- break;
- case 3:
- psd_scan->psd_gen_count = 0;
- for (j = 1; j <= loopcnt; j++) {
-
- btcoexist->btc_get(btcoexist,
- BTC_GET_BL_WIFI_SCAN, &scan);
- btcoexist->btc_get(btcoexist,
- BTC_GET_BL_WIFI_ROAM, &roam);
-
- if (scan || roam) {
- is_sweep_ok = false;
- break;
- }
- memset(psd_scan->psd_report, 0,
- psd_scan->psd_point * sizeof(u32));
- start_p = psd_scan->psd_start_point +
- psd_scan->psd_start_base;
- stop_p = psd_scan->psd_stop_point +
- psd_scan->psd_start_base + 1;
-
- i = start_p;
- point_index = 0;
-
- while (i < stop_p) {
- if (i >= points1)
- psd_report =
- halbtc8723d1ant_psd_getdata(
- btcoexist, i - points1);
- else
- psd_report =
- halbtc8723d1ant_psd_getdata(
- btcoexist, i);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "Point=%d, psd_raw_data = 0x%08x\n",
- i, psd_report);
- BTC_TRACE(trace_buf);
- if (psd_report == 0)
- tmp = 0;
- else
- /* tmp = 20*log10((double)psd_report); */
- /* 20*log2(x)/log2(10), log2Base return theresult of the psd_report*100 */
- tmp = 6 * halbtc8723d1ant_psd_log2base(
- btcoexist, psd_report);
-
- n = i - psd_scan->psd_start_base;
- psd_scan->psd_report[n] = tmp;
-
-
- halbtc8723d1ant_psd_maxholddata(
- btcoexist, j);
-
- i++;
-
- }
-
- psd_scan->psd_gen_count = j;
- }
-
- flag = 100;
- break;
- case 99: /* error */
-
- outloop = true;
- break;
- case 100: /* recovery */
-
- /* set 3-wire on */
- val = btcoexist->btc_read_4byte(btcoexist, 0x88c);
- val &= 0xffcfffff;
- btcoexist->btc_write_4byte(btcoexist, 0x88c, val);
-
- /* CCK on */
- val = btcoexist->btc_read_4byte(btcoexist, 0x800);
- val |= 0x01000000;
- btcoexist->btc_write_4byte(btcoexist, 0x800, val);
-
- /* Tx-pause off */
- btcoexist->btc_write_1byte(btcoexist, 0x522, 0x0);
-
- /* PSD off */
- val = btcoexist->btc_read_4byte(btcoexist, 0x808);
- val &= 0xffbfffff;
- btcoexist->btc_write_4byte(btcoexist, 0x808, val);
-
- /* restore RF Rx filter corner */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1d,
- 0xfffff, u32tmp1);
-
- /* Exit debug mode */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xde,
- 0x2, 0x0);
-
- /* restore WiFi original channel */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x18,
- 0x3ff, wifi_original_channel);
-
- outloop = true;
- break;
-
- }
-
- } while (!outloop);
-
-
-
- psd_scan->is_psd_running = false;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx PSD Sweep Stop!!\n");
- BTC_TRACE(trace_buf);
- return is_sweep_ok;
-
-}
-
-
-void halbtc8723d1ant_psd_antenna_detection(IN struct btc_coexist *btcoexist,
- IN u32 bt_tx_time, IN u32 bt_le_channel)
-{
- u32 i = 0;
- u32 wlpsd_cent_freq = 2484, wlpsd_span = 2, wlpsd_sweep_count = 50;
- s32 wlpsd_offset = -4;
- u8 bt_le_ch[13] = {3, 6, 8, 11, 13, 16, 18, 21, 23, 26, 28, 31, 33};
-
- u8 h2c_parameter[3] = {0}, u8tmpa, u8tmpb;
-
- u8 state = 0;
- boolean outloop = false, bt_resp = false;
- u32 freq, freq1, freq2, psd_rep1, psd_rep2, delta_freq_per_point,
- u32tmp, u32tmp0, u32tmp1, u32tmp2;
- struct btc_board_info *board_info = &btcoexist->board_info;
-
- board_info->btdm_ant_det_finish = false;
- memset(psd_scan->ant_det_peak_val, 0, 16 * sizeof(u8));
- memset(psd_scan->ant_det_peak_freq, 0, 16 * sizeof(u8));
-
- if (board_info->tfbga_package) /* for TFBGA */
- psd_scan->ant_det_thres_offset = 5;
- else
- psd_scan->ant_det_thres_offset = 0;
-
- do {
- switch (state) {
- case 0:
- if (bt_le_channel == 39)
- wlpsd_cent_freq = 2484;
- else {
- for (i = 1; i <= 13; i++) {
- if (bt_le_ch[i - 1] ==
- bt_le_channel) {
- wlpsd_cent_freq = 2412
- + (i - 1) * 5;
- break;
- }
- }
-
- if (i == 14) {
-
- BTC_SPRINTF(trace_buf,
- BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Abort!!, Invalid LE channel = %d\n ",
- bt_le_channel);
- BTC_TRACE(trace_buf);
- outloop = true;
- break;
- }
- }
-
- wlpsd_sweep_count = bt_tx_time * 238 /
- 100; /* bt_tx_time/0.42 */
- wlpsd_sweep_count = wlpsd_sweep_count / 5;
-
- if (wlpsd_sweep_count % 5 != 0)
- wlpsd_sweep_count = (wlpsd_sweep_count /
- 5 + 1) * 5;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), BT_LETxTime=%d, BT_LECh = %d\n",
- bt_tx_time, bt_le_channel);
- BTC_TRACE(trace_buf);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), wlpsd_cent_freq=%d, wlpsd_offset = %d, wlpsd_span = %d, wlpsd_sweep_count = %d\n",
- wlpsd_cent_freq,
- wlpsd_offset,
- wlpsd_span,
- wlpsd_sweep_count);
- BTC_TRACE(trace_buf);
-
- state = 1;
- break;
- case 1: /* stop coex DM & set antenna path */
- /* Stop Coex DM */
- btcoexist->stop_coex_dm = true;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Stop Coex DM!!\n");
- BTC_TRACE(trace_buf);
-
- /* Set TDMA off, */
- halbtc8723d1ant_ps_tdma(btcoexist, FORCE_EXEC,
- false, 0);
-
- /* Set coex table */
- halbtc8723d1ant_coex_table_with_type(btcoexist,
- FORCE_EXEC, 0);
-
- if (board_info->btdm_ant_pos ==
- BTC_ANTENNA_AT_MAIN_PORT) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna at Main Port\n");
- BTC_TRACE(trace_buf);
-
- /* Set Antenna path, switch WiFi to un-certain antenna port */
- halbtc8723d1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_BT, FORCE_EXEC, false,
- false);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna at Aux Port\n");
- BTC_TRACE(trace_buf);
-
- /* Set Antenna path, switch WiFi to un-certain antenna port */
- halbtc8723d1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_WIFI, FORCE_EXEC, false,
- false);
- }
-
-
-
-
- /* Set Antenna Path, both GNT_WL/GNT_BT = 1, and control by SW */
- /* set GNT_BT to SW high */
- halbtc8723d1ant_ltecoex_set_gnt_bt(btcoexist,
- BT_8723D_1ANT_GNT_BLOCK_RFC_BB,
- BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW,
- BT_8723D_1ANT_SIG_STA_SET_TO_HIGH);
- /* Set GNT_WL to SW high */
- halbtc8723d1ant_ltecoex_set_gnt_wl(btcoexist,
- BT_8723D_1ANT_GNT_BLOCK_RFC_BB,
- BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW,
- BT_8723D_1ANT_SIG_STA_SET_TO_HIGH);
-
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Set Antenna to BT!!\n");
- BTC_TRACE(trace_buf);
-
- /* Set AFH mask on at WiFi channel 2472MHz +/- 10MHz */
- h2c_parameter[0] = 0x1;
- h2c_parameter[1] = 0xd;
- h2c_parameter[2] = 0x14;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Set AFH on, Cent-Ch= %d, Mask=%d\n",
- h2c_parameter[1],
- h2c_parameter[2]);
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_fill_h2c(btcoexist, 0x66, 3,
- h2c_parameter);
-
- u32tmp0 = btcoexist->btc_read_4byte(btcoexist, 0x70);
- u32tmp1 = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
- u32tmp2 = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** 0x70 = 0x%x, 0x38= 0x%x, 0x54= 0x%x (Before Ant Det) **********\n",
- u32tmp0, u32tmp1, u32tmp2);
- BTC_TRACE(trace_buf);
-
- state = 2;
- break;
- case 2: /* Pre-sweep background psd */
- if (!halbtc8723d1ant_psd_sweep_point(btcoexist,
- wlpsd_cent_freq, wlpsd_offset, wlpsd_span,
- BT_8723D_1ANT_ANTDET_PSD_POINTS,
- BT_8723D_1ANT_ANTDET_PSD_AVGNUM, 3)) {
- board_info->btdm_ant_det_finish = false;
- board_info->btdm_ant_num_by_ant_det = 1;
- psd_scan->ant_det_result = 8;
- state = 99;
- break;
- }
-
- psd_scan->ant_det_pre_psdscan_peak_val =
- psd_scan->psd_max_value;
-
- if (psd_scan->psd_max_value >
- (BT_8723D_1ANT_ANTDET_PSDTHRES_BACKGROUND
- + psd_scan->ant_det_thres_offset) * 100) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Abort Antenna Detection!! becaus background = %d > thres (%d)\n",
- psd_scan->psd_max_value / 100,
- BT_8723D_1ANT_ANTDET_PSDTHRES_BACKGROUND
- + psd_scan->ant_det_thres_offset);
- BTC_TRACE(trace_buf);
- board_info->btdm_ant_det_finish = false;
- board_info->btdm_ant_num_by_ant_det = 1;
- psd_scan->ant_det_result = 5;
- state = 99;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Start Antenna Detection!! becaus background = %d <= thres (%d)\n",
- psd_scan->psd_max_value / 100,
- BT_8723D_1ANT_ANTDET_PSDTHRES_BACKGROUND
- + psd_scan->ant_det_thres_offset);
- BTC_TRACE(trace_buf);
- state = 3;
- }
- break;
- case 3:
-
- bt_resp = btcoexist->btc_set_bt_ant_detection(
- btcoexist, (u8)(bt_tx_time & 0xff),
- (u8)(bt_le_channel & 0xff));
-
- if (!halbtc8723d1ant_psd_sweep_point(btcoexist,
- wlpsd_cent_freq, wlpsd_offset,
- wlpsd_span,
- BT_8723D_1ANT_ANTDET_PSD_POINTS,
- BT_8723D_1ANT_ANTDET_PSD_AVGNUM,
- wlpsd_sweep_count)) {
- board_info->btdm_ant_det_finish = false;
- board_info->btdm_ant_num_by_ant_det = 1;
- psd_scan->ant_det_result = 8;
- state = 99;
- break;
- }
-
- psd_scan->ant_det_psd_scan_peak_val =
- psd_scan->psd_max_value;
- psd_scan->ant_det_psd_scan_peak_freq =
- psd_scan->psd_max_value_point;
- state = 4;
- break;
- case 4:
-
- if (psd_scan->psd_point == 0)
- delta_freq_per_point = 0;
- else
- delta_freq_per_point =
- psd_scan->psd_band_width /
- psd_scan->psd_point;
-
- psd_rep1 = psd_scan->psd_max_value / 100;
- psd_rep2 = psd_scan->psd_max_value - psd_rep1 *
- 100;
-
- freq = ((psd_scan->real_cent_freq - 20) *
- 1000000 + psd_scan->psd_max_value_point
- * delta_freq_per_point);
- freq1 = freq / 1000000;
- freq2 = freq / 1000 - freq1 * 1000;
-
- if (freq2 < 100) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Max Value: Freq = %d.0%d MHz",
- freq1, freq2);
- BTC_TRACE(trace_buf);
- CL_SPRINTF(psd_scan->ant_det_peak_freq,
- BT_8723D_1ANT_ANTDET_BUF_LEN,
- "%d.0%d", freq1, freq2);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Max Value: Freq = %d.%d MHz",
- freq1, freq2);
- BTC_TRACE(trace_buf);
- CL_SPRINTF(psd_scan->ant_det_peak_freq,
- BT_8723D_1ANT_ANTDET_BUF_LEN,
- "%d.%d", freq1, freq2);
- }
-
- if (psd_rep2 < 10) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- ", Value = %d.0%d dB\n",
- psd_rep1, psd_rep2);
- BTC_TRACE(trace_buf);
- CL_SPRINTF(psd_scan->ant_det_peak_val,
- BT_8723D_1ANT_ANTDET_BUF_LEN,
- "%d.0%d", psd_rep1, psd_rep2);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- ", Value = %d.%d dB\n",
- psd_rep1, psd_rep2);
- BTC_TRACE(trace_buf);
- CL_SPRINTF(psd_scan->ant_det_peak_val,
- BT_8723D_1ANT_ANTDET_BUF_LEN,
- "%d.%d", psd_rep1, psd_rep2);
- }
-
- psd_scan->ant_det_is_btreply_available = true;
-
- if (bt_resp == false) {
- psd_scan->ant_det_is_btreply_available =
- false;
- psd_scan->ant_det_result = 0;
- board_info->btdm_ant_det_finish = false;
- board_info->btdm_ant_num_by_ant_det = 1;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), BT Response = Fail\n ");
- BTC_TRACE(trace_buf);
- } else if (psd_scan->psd_max_value >
- (BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION)
- * 100) {
- psd_scan->ant_det_result = 1;
- board_info->btdm_ant_det_finish = true;
- board_info->btdm_ant_num_by_ant_det = 2;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 2-Ant, Bad-Isolation!!\n");
- BTC_TRACE(trace_buf);
- } else if (psd_scan->psd_max_value >
- (BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION
- + psd_scan->ant_det_thres_offset) * 100) {
- psd_scan->ant_det_result = 2;
- board_info->btdm_ant_det_finish = true;
- board_info->btdm_ant_num_by_ant_det = 2;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 2-Ant, Good-Isolation!!\n");
- BTC_TRACE(trace_buf);
- } else if (psd_scan->psd_max_value >
- (BT_8723D_1ANT_ANTDET_PSDTHRES_1ANT) *
- 100) {
- psd_scan->ant_det_result = 3;
- board_info->btdm_ant_det_finish = true;
- board_info->btdm_ant_num_by_ant_det = 1;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 1-Ant!!\n");
- BTC_TRACE(trace_buf);
- } else {
- psd_scan->ant_det_result = 4;
- board_info->btdm_ant_det_finish = false;
- board_info->btdm_ant_num_by_ant_det = 1;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 1-Ant, un-certainity!!\n");
- BTC_TRACE(trace_buf);
- }
-
- state = 99;
- break;
- case 99: /* restore setup */
-
- /* Set AFH mask off at WiFi channel 2472MHz +/- 10MHz */
- h2c_parameter[0] = 0x0;
- h2c_parameter[1] = 0x0;
- h2c_parameter[2] = 0x0;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Set AFH on, Cent-Ch= %d, Mask=%d\n",
- h2c_parameter[1], h2c_parameter[2]);
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_fill_h2c(btcoexist, 0x66, 3,
- h2c_parameter);
-
- /* Set Antenna Path, GNT_WL/GNT_BT control by PTA */
- halbtc8723d1ant_set_ant_path(btcoexist,
- BTC_ANT_PATH_PTA, FORCE_EXEC, false,
- false);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Set Antenna to PTA\n!!");
- BTC_TRACE(trace_buf);
-
- /* Resume Coex DM */
- btcoexist->stop_coex_dm = false;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Resume Coex DM\n!!");
- BTC_TRACE(trace_buf);
-
- /* stimulate coex running */
- halbtc8723d1ant_run_coexist_mechanism(
- btcoexist);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Stimulate Coex running\n!!");
- BTC_TRACE(trace_buf);
-
- outloop = true;
- break;
- }
-
- } while (!outloop);
-
-
-
-}
-
-void halbtc8723d1ant_psd_antenna_detection_check(IN struct btc_coexist
- *btcoexist)
-{
- static u32 ant_det_count = 0, ant_det_fail_count = 0;
- struct btc_board_info *board_info = &btcoexist->board_info;
-
- boolean scan, roam;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
-
-
- /* psd_scan->ant_det_bt_tx_time = 20; */
- psd_scan->ant_det_bt_tx_time =
- BT_8723D_1ANT_ANTDET_BTTXTIME; /* 0.42ms*50 = 20ms (0.42ms = 1 PSD sweep) */
- psd_scan->ant_det_bt_le_channel = BT_8723D_1ANT_ANTDET_BTTXCHANNEL;
-
- ant_det_count++;
-
- psd_scan->ant_det_try_count = ant_det_count;
-
- if (scan || roam) {
- board_info->btdm_ant_det_finish = false;
- psd_scan->ant_det_result = 6;
- } else if (coex_sta->bt_disabled) {
- board_info->btdm_ant_det_finish = false;
- psd_scan->ant_det_result = 11;
- } else if (coex_sta->num_of_profile >= 1) {
- board_info->btdm_ant_det_finish = false;
- psd_scan->ant_det_result = 7;
- } else if (
- !psd_scan->ant_det_is_ant_det_available) { /* Antenna initial setup is not ready */
- board_info->btdm_ant_det_finish = false;
- psd_scan->ant_det_result = 9;
- } else if (coex_sta->c2h_bt_inquiry_page) {
- board_info->btdm_ant_det_finish = false;
- psd_scan->ant_det_result = 10;
- } else {
-
- btcoexist->stop_coex_dm = true;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Stop Coex DM!!\n");
- BTC_TRACE(trace_buf);
-
- halbtc8723d1ant_psd_antenna_detection(btcoexist,
- psd_scan->ant_det_bt_tx_time,
- psd_scan->ant_det_bt_le_channel);
-
- delay_ms(psd_scan->ant_det_bt_tx_time);
-
- btcoexist->stop_coex_dm = false;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Resume Coex DM\n!!");
- BTC_TRACE(trace_buf);
-
- /* stimulate coex running */
- /*
- halbtc8723d1ant_run_coexist_mechanism(
- btcoexist);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Stimulate Coex running\n!!");
- BTC_TRACE(trace_buf);
- */
- }
-
- if (!board_info->btdm_ant_det_finish)
- ant_det_fail_count++;
-
- psd_scan->ant_det_fail_count = ant_det_fail_count;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), result = %d, fail_count = %d, finish = %s\n",
- psd_scan->ant_det_result,
- psd_scan->ant_det_fail_count,
- board_info->btdm_ant_det_finish == TRUE ? "Yes" : "No");
- BTC_TRACE(trace_buf);
-
-}
-
-
-/* ************************************************************
- * work around function start with wa_halbtc8723d1ant_
- * ************************************************************
- * ************************************************************
- * extern function start with ex_halbtc8723d1ant_
- * ************************************************************ */
-void ex_halbtc8723d1ant_power_on_setting(IN struct btc_coexist *btcoexist)
-{
- struct btc_board_info *board_info = &btcoexist->board_info;
- u8 u8tmp = 0x0;
- u16 u16tmp = 0x0;
- u32 value = 0;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx Execute 8723d 1-Ant PowerOn Setting xxxxxxxxxxxxxxxx!!\n");
- BTC_TRACE(trace_buf);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "Ant Det Finish = %s, Ant Det Number = %d\n",
- (board_info->btdm_ant_det_finish ? "Yes" : "No"),
- board_info->btdm_ant_num_by_ant_det);
- BTC_TRACE(trace_buf);
-
- btcoexist->stop_coex_dm = true;
- psd_scan->ant_det_is_ant_det_available = FALSE;
- /* halbtc8723d1ant_post_onoffstate_to_bt(btcoexist, TRUE); */
-
- /* enable BB, REG_SYS_FUNC_EN such that we can write BB Register correctly. */
- u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2);
- btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1));
-
- /* set Path control owner to WiFi */
- halbtc8723d1ant_ltecoex_pathcontrol_owner(btcoexist,
- BT_8723D_1ANT_PCO_WLSIDE);
-
- /* set GNT_BT to high */
- halbtc8723d1ant_ltecoex_set_gnt_bt(btcoexist,
- BT_8723D_1ANT_GNT_BLOCK_RFC_BB,
- BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW,
- BT_8723D_1ANT_SIG_STA_SET_TO_HIGH);
- /* Set GNT_WL to low */
- halbtc8723d1ant_ltecoex_set_gnt_wl(btcoexist,
- BT_8723D_1ANT_GNT_BLOCK_RFC_BB,
- BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW,
- BT_8723D_1ANT_SIG_STA_SET_TO_LOW);
-
- /* Local setting bit define */
- /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */
- /* BIT1: "0" for internal switch; "1" for external switch */
- /* BIT2: "0" for one antenna; "1" for two antenna */
- /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */
-
- /* Set path control to WL */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x80, 0x1);
-
- /* Set Antenna Path to BT side */
- /* Check efuse 0xc3[6] for Single Antenna Path */
- if (board_info->single_ant_path == 0) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** Single Antenna, Antenna at Main Port: S1**********\n");
- BTC_TRACE(trace_buf);
-
- /* set to S1 */
- board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;
- btcoexist->btc_write_2byte(btcoexist, 0x948, 0x280);
- u8tmp = 0;
- } else if (board_info->single_ant_path == 1) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** Single Antenna, Antenna at Aux Port: S0**********\n");
- BTC_TRACE(trace_buf);
-
- /* set to S0 */
- board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT;
- btcoexist->btc_write_2byte(btcoexist, 0x948, 0x0);
- u8tmp = 1;
- }
-
- /* Write Single Antenna Position to Registry to tell BT for 8723d. This line can be removed
- since BT EFuse also add "single antenna position" in EFuse for 8723d*/
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_ANTPOSREGRISTRY_CTRL,
- &value);
-
- /* Save"single antenna position" info in Local register setting for FW reading, because FW may not ready at power on */
- if (btcoexist->chip_interface == BTC_INTF_PCI)
- btcoexist->btc_write_local_reg_1byte(btcoexist, 0x3e0, u8tmp);
- else if (btcoexist->chip_interface == BTC_INTF_USB)
- btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp);
- else if (btcoexist->chip_interface == BTC_INTF_SDIO)
- btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, u8tmp);
-
- /* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */
- halbtc8723d1ant_enable_gnt_to_gpio(btcoexist, FALSE);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** LTE coex Reg 0x38 (Power-On) = 0x%x**********\n",
- halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x38));
- BTC_TRACE(trace_buf);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** MAC Reg 0x70/ BB Reg 0x948 (Power-On) = 0x%x / 0x%x**********\n",
- btcoexist->btc_read_4byte(btcoexist, 0x70), btcoexist->btc_read_2byte(btcoexist, 0x948));
- BTC_TRACE(trace_buf);
-
-}
-
-void ex_halbtc8723d1ant_pre_load_firmware(IN struct btc_coexist *btcoexist)
-{
-}
-
-void ex_halbtc8723d1ant_init_hw_config(IN struct btc_coexist *btcoexist,
- IN boolean wifi_only)
-{
- halbtc8723d1ant_init_hw_config(btcoexist, true, wifi_only);
- btcoexist->stop_coex_dm = false;
-
-}
-
-void ex_halbtc8723d1ant_init_coex_dm(IN struct btc_coexist *btcoexist)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Coex Mechanism Init!!\n");
- BTC_TRACE(trace_buf);
-
- halbtc8723d1ant_init_coex_dm(btcoexist);
-
- /* halbtc8723d1ant_query_bt_info(btcoexist); */
-}
-
-void ex_halbtc8723d1ant_display_coex_info(IN struct btc_coexist *btcoexist)
-{
- struct btc_board_info *board_info = &btcoexist->board_info;
- struct btc_stack_info *stack_info = &btcoexist->stack_info;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- u8 *cli_buf = btcoexist->cli_buf;
- u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0;
- u16 u16tmp[4];
- u32 u32tmp[4];
- u32 fa_of_dm, fa_cck;
- u32 fw_ver = 0, bt_patch_ver = 0;
- static u8 pop_report_in_10s = 0;
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ============[BT Coexist info]============");
- CL_PRINTF(cli_buf);
-
- if (btcoexist->manual_control) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ============[Under Manual Control]============");
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ==========================================");
- CL_PRINTF(cli_buf);
- }
- if (btcoexist->stop_coex_dm) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ============[Coex is STOPPED]============");
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ==========================================");
- CL_PRINTF(cli_buf);
- }
-
- if (psd_scan->ant_det_try_count == 0) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %s",
- "Ant PG Num/ Mech/ Pos",
- board_info->pg_ant_num, board_info->btdm_ant_num,
- (board_info->btdm_ant_pos == 1 ? "S1" : "S0"));
- CL_PRINTF(cli_buf);
- } else {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %d/ %d/ %s (%d/%d/%d)",
- "Ant PG Num/ Mech(Ant_Det)/ Pos",
- board_info->pg_ant_num, board_info->btdm_ant_num_by_ant_det,
- (board_info->btdm_ant_pos == 1 ? "S1" : "S0"),
- psd_scan->ant_det_try_count, psd_scan->ant_det_fail_count,
- psd_scan->ant_det_result);
- CL_PRINTF(cli_buf);
-
- if (board_info->btdm_ant_det_finish) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
- "Ant Det PSD Value",
- psd_scan->ant_det_peak_val);
- CL_PRINTF(cli_buf);
- }
- }
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d",
- "BT stack/ hci ext ver",
- ((stack_info->profile_notified) ? "Yes" : "No"),
- stack_info->hci_version);
- CL_PRINTF(cli_buf);
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %d_%x/ 0x%x/ 0x%x(%d)/ %c",
- "Version Coex/ Fw/ Patch/ Cut",
- glcoex_ver_date_8723d_1ant, glcoex_ver_8723d_1ant, fw_ver,
- bt_patch_ver, bt_patch_ver, coex_sta->cut_version + 65);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ",
- "Wifi channel informed to BT",
- coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
- coex_dm->wifi_chnl_info[2]);
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s",
- "WifibHiPri/ Ccklock/ CckEverLock",
- (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"),
- (coex_sta->cck_lock ? "Yes" : "No"),
- (coex_sta->cck_ever_lock ? "Yes" : "No"));
- CL_PRINTF(cli_buf);
-
- /* wifi status */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Wifi Status]============");
- CL_PRINTF(cli_buf);
- btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[BT Status]============");
- CL_PRINTF(cli_buf);
-
- pop_report_in_10s++;
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d/ %d] ",
- "BT [status/ rssi/ retryCnt/ popCnt]",
- ((coex_sta->bt_disabled) ? ("disabled") : ((
- coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page")
- : ((BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
- coex_dm->bt_status) ? "non-connected idle" :
- ((BT_8723D_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)
- ? "connected-idle" : "busy")))),
- coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt,
- coex_sta->pop_event_cnt);
- CL_PRINTF(cli_buf);
-
- if (pop_report_in_10s >= 5) {
- coex_sta->pop_event_cnt = 0;
- pop_report_in_10s = 0;
- }
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %d / %d / %d / %d / %d",
- "SCO/HID/PAN/A2DP/Hi-Pri",
- bt_link_info->sco_exist, bt_link_info->hid_exist,
- bt_link_info->pan_exist, bt_link_info->a2dp_exist,
- bt_link_info->bt_hi_pri_link_exist);
- CL_PRINTF(cli_buf);
-
- if (stack_info->profile_notified)
- btcoexist->btc_disp_dbg_msg(btcoexist,
- BTC_DBG_DISP_BT_LINK_INFO);
- else {
- bt_info_ext = coex_sta->bt_info_ext;
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %s / %d",
- "Role/A2DP Rate/Bitpool",
- ((bt_link_info->slave_role) ? "Slave" : "Master"),
- (bt_info_ext & BIT(0)) ? "BR" : "EDR", coex_sta->a2dp_bit_pool);
- CL_PRINTF(cli_buf);
- }
-
-
- for (i = 0; i < BT_INFO_SRC_8723D_1ANT_MAX; i++) {
- if (coex_sta->bt_info_c2h_cnt[i]) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)",
- glbt_info_src_8723d_1ant[i],
- coex_sta->bt_info_c2h[i][0],
- coex_sta->bt_info_c2h[i][1],
- coex_sta->bt_info_c2h[i][2],
- coex_sta->bt_info_c2h[i][3],
- coex_sta->bt_info_c2h[i][4],
- coex_sta->bt_info_c2h[i][5],
- coex_sta->bt_info_c2h[i][6],
- coex_sta->bt_info_c2h_cnt[i]);
- CL_PRINTF(cli_buf);
- }
- }
-
-
- if (btcoexist->manual_control)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[mechanisms] (before Manual)============");
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[mechanisms]============");
-
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
- "SM[LowPenaltyRA]",
- coex_dm->cur_low_penalty_ra);
- CL_PRINTF(cli_buf);
-
- ps_tdma_case = coex_dm->cur_ps_tdma;
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (%s,%s)",
- "PS TDMA",
- coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],
- coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],
- coex_dm->ps_tdma_para[4], ps_tdma_case,
- (coex_dm->cur_ps_tdma_on ? "On" : "Off"),
- (coex_dm->auto_tdma_adjust ? "Adj" : "Fix"));
-
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
- "WL/BT Coex Table Type",
- coex_sta->coex_table_type);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
- u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
- "0x6c0/0x6c4/0x6c8(coexTable)",
- u32tmp[0], u32tmp[1], u32tmp[2]);
- CL_PRINTF(cli_buf);
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
- "0x778/0x6cc/IgnWlanAct",
- u8tmp[0], u32tmp[0], coex_dm->cur_ignore_wlan_act);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist,
- 0xa0);
- u32tmp[1] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist,
- 0xa4);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
- "LTE Coex Table W_L/B_L",
- u32tmp[0] & 0xffff, u32tmp[1] & 0xffff);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist,
- 0xa8);
- u32tmp[1] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist,
- 0xac);
- u32tmp[2] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist,
- 0xb0);
- u32tmp[3] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist,
- 0xb4);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
- "LTE Break Table W_L/B_L/L_W/L_B",
- u32tmp[0] & 0xffff, u32tmp[1] & 0xffff,
- u32tmp[2] & 0xffff, u32tmp[3] & 0xffff);
- CL_PRINTF(cli_buf);
-
- /* Hw setting */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Hw setting]============");
- CL_PRINTF(cli_buf);
-
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434);
- u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x",
- "0x430/0x434/0x42a/0x456",
- u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]);
- CL_PRINTF(cli_buf);
-
-
- u32tmp[0] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %s",
- "LTE CoexOn/Path Ctrl Owner",
- (int)((u32tmp[0] & BIT(7)) >> 7), ((u8tmp[0] & BIT(2)) ? "WL" : "BT"));
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
- "LTE 3Wire/OPMode/UART/UARTMode",
- (int)((u32tmp[0] & BIT(6)) >> 6), (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4),
- (int)((u32tmp[0] & BIT(3)) >> 3),
- (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0))));
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %s",
- "GNT_WL_SWCtrl/GNT_BT_SWCtrl/Dbg",
- (int)((u32tmp[0] & BIT(12)) >> 12), (int)((u32tmp[0] & BIT(14)) >> 14),
- ((u8tmp[0] & BIT(3)) ? "On" : "Off"));
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = halbtc8723d1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
- "GNT_WL/GNT_BT/LTE_Busy/UART_Busy",
- (int)((u32tmp[0] & BIT(2)) >> 2), (int)((u32tmp[0] & BIT(3)) >> 3),
- (int)((u32tmp[0] & BIT(1)) >> 1), (int)(u32tmp[0] & BIT(0)));
- CL_PRINTF(cli_buf);
-
-
- u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x948);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
- "0x948/0x4c6[4]/0x40[5] (W/B PTA_En)",
- u16tmp[0], (int)((u8tmp[0] & BIT(4)) >> 4), (int)((u8tmp[1] & BIT(5)) >> 5));
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x953);
- u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0x67);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ %s",
- "0x550/0x522/0x67[7]/4-RxAGC",
- u32tmp[0], u8tmp[0], ((u8tmp[2] & 0x80) >> 7), (u8tmp[1] & 0x2) ? "On" : "Off");
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xda0);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xda4);
- u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0xda8);
- u32tmp[3] = btcoexist->btc_read_4byte(btcoexist, 0xcf0);
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xa5b);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xa5c);
-
- fa_of_dm = ((u32tmp[0] & 0xffff0000) >> 16) + ((u32tmp[1] & 0xffff0000)
- >> 16) + (u32tmp[1] & 0xffff) + (u32tmp[2] & 0xffff) +
- ((u32tmp[3] & 0xffff0000) >> 16) + (u32tmp[3] & 0xffff);
- fa_cck = (u8tmp[0] << 8) + u8tmp[1];
-
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xc50);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
- "0xc50/OFDM-CCA/OFDM-FA/CCK-FA",
- u32tmp[1] & 0xff, u32tmp[0] & 0xffff, fa_of_dm, fa_cck);
- CL_PRINTF(cli_buf);
-
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
- "CRC_OK CCK/11g/11n/11n-Agg",
- coex_sta->crc_ok_cck, coex_sta->crc_ok_11g,
- coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_agg);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
- "CRC_Err CCK/11g/11n/11n-Agg",
- coex_sta->crc_err_cck, coex_sta->crc_err_11g,
- coex_sta->crc_err_11n, coex_sta->crc_err_11n_agg);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
- "0x770(high-pri rx/tx)",
- coex_sta->high_priority_rx, coex_sta->high_priority_tx);
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
- "0x774(low-pri rx/tx)",
- coex_sta->low_priority_rx, coex_sta->low_priority_tx);
- CL_PRINTF(cli_buf);
-
- halbtc8723d1ant_read_score_board(btcoexist, &u16tmp[0]);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %04x",
- "ScoreBoard[14:0] (from BT)", u16tmp[0]);
- CL_PRINTF(cli_buf);
-
- btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
-}
-
-
-void ex_halbtc8723d1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type)
-{
- if (btcoexist->manual_control || btcoexist->stop_coex_dm)
- return;
-
- if (BTC_IPS_ENTER == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], IPS ENTER notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_ips = true;
-
- /* Write WL "Active" in Score-board for LPS off */
- halbtc8723d1ant_post_activestate_to_bt(btcoexist, false);
-
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT,
- FORCE_EXEC, false, true);
- halbtc8723d1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
- } else if (BTC_IPS_LEAVE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], IPS LEAVE notify\n");
- BTC_TRACE(trace_buf);
- halbtc8723d1ant_post_activestate_to_bt(btcoexist, true);
-
- halbtc8723d1ant_init_hw_config(btcoexist, false, false);
- halbtc8723d1ant_init_coex_dm(btcoexist);
-
- coex_sta->under_ips = false;
- }
-}
-
-void ex_halbtc8723d1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type)
-{
- if (btcoexist->manual_control || btcoexist->stop_coex_dm)
- return;
-
- if (BTC_LPS_ENABLE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], LPS ENABLE notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_lps = true;
-
- if (coex_sta->force_lps_on == true) { /* LPS No-32K */
- /* Write WL "Active" in Score-board for PS-TDMA */
- halbtc8723d1ant_post_activestate_to_bt(btcoexist, true);
-
- } else { /* LPS-32K, need check if this h2c 0x71 can work?? (2015/08/28) */
- /* Write WL "Non-Active" in Score-board for Native-PS */
- halbtc8723d1ant_post_activestate_to_bt(btcoexist, false);
-
- }
- } else if (BTC_LPS_DISABLE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], LPS DISABLE notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_lps = false;
-
- /* Write WL "Active" in Score-board for LPS off */
- halbtc8723d1ant_post_activestate_to_bt(btcoexist, true);
-
- }
-}
-
-void ex_halbtc8723d1ant_scan_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- boolean wifi_connected = false;
-
- if (btcoexist->manual_control ||
- btcoexist->stop_coex_dm)
- return;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
-
- halbtc8723d1ant_query_bt_info(btcoexist);
-
- if (BTC_SCAN_START == type) {
-
- if (!wifi_connected)
- coex_sta->wifi_is_high_pri_task = true;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCAN START notify\n");
- BTC_TRACE(trace_buf);
-
- halbtc8723d1ant_post_activestate_to_bt(btcoexist, true);
- halbtc8723d1ant_ps_tdma(btcoexist, FORCE_EXEC, false,
- 8);
-
- /* Force antenna setup for no scan result issue */
- halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
- FORCE_EXEC, false, false);
-
- if (!wifi_connected) /* non-connected scan */
- halbtc8723d1ant_action_wifi_not_connected_scan(btcoexist);
- else /* wifi is connected */
- halbtc8723d1ant_action_wifi_connected_scan(btcoexist);
-
- } else {
-
- coex_sta->wifi_is_high_pri_task = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
- &coex_sta->scan_ap_num);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCAN FINISH notify (Scan-AP = %d)\n", coex_sta->scan_ap_num);
- BTC_TRACE(trace_buf);
-
- if (!wifi_connected)
- halbtc8723d1ant_action_wifi_not_connected(btcoexist);
- else
- halbtc8723d1ant_action_wifi_connected(btcoexist);
- }
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCAN Notify() end\n");
- BTC_TRACE(trace_buf);
-
-}
-
-void ex_halbtc8723d1ant_connect_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- boolean wifi_connected = false;
-
- if (btcoexist->manual_control ||
- btcoexist->stop_coex_dm)
- return;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
-
- if (BTC_ASSOCIATE_START == type) {
-
- coex_sta->wifi_is_high_pri_task = true;
-
- halbtc8723d1ant_post_activestate_to_bt(btcoexist, true);
- halbtc8723d1ant_ps_tdma(btcoexist, FORCE_EXEC, false,
- 8);
-
- /* Force antenna setup for no scan result issue */
- halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
- FORCE_EXEC, false, false);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CONNECT START notify\n");
- BTC_TRACE(trace_buf);
-
- coex_dm->arp_cnt = 0;
-
- halbtc8723d1ant_action_wifi_not_connected_asso_auth(btcoexist);
- } else {
-
- coex_sta->wifi_is_high_pri_task = false;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CONNECT FINISH notify\n");
- BTC_TRACE(trace_buf);
-
- if (!wifi_connected) /* non-connected scan */
- halbtc8723d1ant_action_wifi_not_connected(btcoexist);
- else
- halbtc8723d1ant_action_wifi_connected(btcoexist);
- }
-
-}
-
-void ex_halbtc8723d1ant_media_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- boolean wifi_under_b_mode = false;
-
- if (btcoexist->manual_control ||
- btcoexist->stop_coex_dm)
- return;
-
- if (BTC_MEDIA_CONNECT == type) {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], MEDIA connect notify\n");
- BTC_TRACE(trace_buf);
-
- halbtc8723d1ant_post_activestate_to_bt(btcoexist, true);
- halbtc8723d1ant_ps_tdma(btcoexist, FORCE_EXEC, false,
- 8);
-
- /* Force antenna setup for no scan result issue */
- halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
- FORCE_EXEC, false, false);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
- &wifi_under_b_mode);
-
- /* Set CCK Tx/Rx high Pri except 11b mode */
- if (wifi_under_b_mode) {
- btcoexist->btc_write_1byte(btcoexist, 0x6cd,
- 0x00); /* CCK Tx */
- btcoexist->btc_write_1byte(btcoexist, 0x6cf,
- 0x00); /* CCK Rx */
- } else {
- /* btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x10); */ /*CCK Tx */
- /* btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x10); */ /*CCK Rx */
- btcoexist->btc_write_1byte(btcoexist, 0x6cd,
- 0x00); /* CCK Tx */
- btcoexist->btc_write_1byte(btcoexist, 0x6cf,
- 0x10); /* CCK Rx */
- }
-
- coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist,
- 0x430);
- coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist,
- 0x434);
- coex_dm->backup_retry_limit = btcoexist->btc_read_2byte(
- btcoexist, 0x42a);
- coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte(
- btcoexist, 0x456);
- } else {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], MEDIA disconnect notify\n");
- BTC_TRACE(trace_buf);
-
- halbtc8723d1ant_post_activestate_to_bt(btcoexist, false);
-
- btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */
- btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */
-
- coex_sta->cck_ever_lock = false;
- }
-
- halbtc8723d1ant_update_wifi_channel_info(btcoexist, type);
-
-}
-
-void ex_halbtc8723d1ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- boolean under_4way = false;
-
- if (btcoexist->manual_control ||
- btcoexist->stop_coex_dm ||
- coex_sta->bt_disabled)
- return;
-
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
- &under_4way);
-
- if (under_4way) {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], specific Packet ---- under_4way!!\n");
- BTC_TRACE(trace_buf);
-
- coex_sta->wifi_is_high_pri_task = true;
- coex_sta->specific_pkt_period_cnt = 2;
- } else if (BTC_PACKET_ARP == type) {
-
- coex_dm->arp_cnt++;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], specific Packet ARP notify -cnt = %d\n", coex_dm->arp_cnt);
- BTC_TRACE(trace_buf);
-
- } else {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n", type);
- BTC_TRACE(trace_buf);
-
- coex_sta->wifi_is_high_pri_task = true;
- coex_sta->specific_pkt_period_cnt = 2;
- }
-
- if (coex_sta->wifi_is_high_pri_task)
- halbtc8723d1ant_action_wifi_connected_specific_packet(btcoexist);
-}
-
-void ex_halbtc8723d1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
- IN u8 *tmp_buf, IN u8 length)
-{
- u8 bt_info = 0;
- u8 i, rsp_source = 0;
- boolean wifi_connected = false;
- boolean bt_busy = false;
-
- coex_sta->c2h_bt_info_req_sent = false;
-
- rsp_source = tmp_buf[0] & 0xf;
- if (rsp_source >= BT_INFO_SRC_8723D_1ANT_MAX)
- rsp_source = BT_INFO_SRC_8723D_1ANT_WIFI_FW;
- coex_sta->bt_info_c2h_cnt[rsp_source]++;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source,
- length);
- BTC_TRACE(trace_buf);
- for (i = 0; i < length; i++) {
- coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
- if (i == 1)
- bt_info = tmp_buf[i];
- if (i == length - 1) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n",
- tmp_buf[i]);
- BTC_TRACE(trace_buf);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ",
- tmp_buf[i]);
- BTC_TRACE(trace_buf);
- }
- }
-
- if (BT_INFO_SRC_8723D_1ANT_WIFI_FW != rsp_source) {
-
- /* if 0xff, it means BT is under WHCK test */
- if (bt_info == 0xff)
- coex_sta->bt_whck_test = true;
- else
- coex_sta->bt_whck_test = false;
-
- coex_sta->bt_retry_cnt = /* [3:0] */
- coex_sta->bt_info_c2h[rsp_source][2] & 0xf;
-
- if (coex_sta->bt_retry_cnt >= 1)
- coex_sta->pop_event_cnt++;
-
- if (coex_sta->bt_info_c2h[rsp_source][2] & 0x20)
- coex_sta->c2h_bt_page = true;
- else
- coex_sta->c2h_bt_page = false;
-
- if (coex_sta->bt_info_c2h[rsp_source][2] & 0x80)
- coex_sta->bt_create_connection = true;
- else
- coex_sta->bt_create_connection = false;
-
- /* unit: %, value-100 to translate to unit: dBm */
- coex_sta->bt_rssi = coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10;
-
- /* coex_sta->bt_info_c2h[rsp_source][3] * 2 - 90; */
-
- if ((coex_sta->bt_info_c2h[rsp_source][1] & 0x49) == 0x49) {
- coex_sta->a2dp_bit_pool =
- coex_sta->bt_info_c2h[rsp_source][6];
- } else
- coex_sta->a2dp_bit_pool = 0;
-
- if (coex_sta->bt_info_c2h[rsp_source][1] & 0x9)
- coex_sta->acl_busy = true;
- else
- coex_sta->acl_busy = false;
-
- coex_sta->bt_info_ext =
- coex_sta->bt_info_c2h[rsp_source][4];
-
- /* Here we need to resend some wifi info to BT */
- /* because bt is reset and loss of the info. */
-
- if ((!btcoexist->manual_control) && (!btcoexist->stop_coex_dm)) {
-
- /* Re-Init */
- if (coex_sta->bt_info_ext & BIT(1)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n");
- BTC_TRACE(trace_buf);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- if (wifi_connected)
- halbtc8723d1ant_update_wifi_channel_info(btcoexist,
- BTC_MEDIA_CONNECT);
- else
- halbtc8723d1ant_update_wifi_channel_info(btcoexist,
- BTC_MEDIA_DISCONNECT);
- }
-
- /* If Ignore_WLanAct && not SetUp_Link */
- if ((coex_sta->bt_info_ext & BIT(3)) && (!(coex_sta->bt_info_ext & BIT(2)))) {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n");
- BTC_TRACE(trace_buf);
- halbtc8723d1ant_ignore_wlan_act(btcoexist,
- FORCE_EXEC, false);
- }
- }
- /* check BIT2 first ==> check if bt is under inquiry or page scan */
- if (bt_info & BT_INFO_8723D_1ANT_B_INQ_PAGE)
- coex_sta->c2h_bt_inquiry_page = true;
- else
- coex_sta->c2h_bt_inquiry_page = false;
- }
-
- coex_sta->num_of_profile = 0;
-
- /* set link exist status */
- if (!(bt_info & BT_INFO_8723D_1ANT_B_CONNECTION)) {
- coex_sta->bt_link_exist = false;
- coex_sta->pan_exist = false;
- coex_sta->a2dp_exist = false;
- coex_sta->hid_exist = false;
- coex_sta->sco_exist = false;
-
- coex_sta->bt_hi_pri_link_exist = false;
- } else { /* connection exists */
- coex_sta->bt_link_exist = true;
- if (bt_info & BT_INFO_8723D_1ANT_B_FTP) {
- coex_sta->pan_exist = true;
- coex_sta->num_of_profile++;
- } else
- coex_sta->pan_exist = false;
- if (bt_info & BT_INFO_8723D_1ANT_B_A2DP) {
- coex_sta->a2dp_exist = true;
- coex_sta->num_of_profile++;
- } else
- coex_sta->a2dp_exist = false;
- if (bt_info & BT_INFO_8723D_1ANT_B_HID) {
- coex_sta->hid_exist = true;
- coex_sta->num_of_profile++;
- } else
- coex_sta->hid_exist = false;
- if (bt_info & BT_INFO_8723D_1ANT_B_SCO_ESCO) {
- coex_sta->sco_exist = true;
- coex_sta->num_of_profile++;
- } else
- coex_sta->sco_exist = false;
-
- }
-
- halbtc8723d1ant_update_bt_link_info(btcoexist);
-
- bt_info = bt_info &
- 0x1f; /* mask profile bit for connect-ilde identification ( for CSR case: A2DP idle --> 0x41) */
-
- if (!(bt_info & BT_INFO_8723D_1ANT_B_CONNECTION)) {
- coex_dm->bt_status = BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n");
- BTC_TRACE(trace_buf);
- } else if (bt_info ==
- BT_INFO_8723D_1ANT_B_CONNECTION) { /* connection exists but no busy */
- coex_dm->bt_status = BT_8723D_1ANT_BT_STATUS_CONNECTED_IDLE;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n");
- BTC_TRACE(trace_buf);
- } else if ((bt_info & BT_INFO_8723D_1ANT_B_SCO_ESCO) ||
- (bt_info & BT_INFO_8723D_1ANT_B_SCO_BUSY)) {
- coex_dm->bt_status = BT_8723D_1ANT_BT_STATUS_SCO_BUSY;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n");
- BTC_TRACE(trace_buf);
- } else if (bt_info & BT_INFO_8723D_1ANT_B_ACL_BUSY) {
- if (BT_8723D_1ANT_BT_STATUS_ACL_BUSY != coex_dm->bt_status)
- coex_dm->auto_tdma_adjust = false;
- coex_dm->bt_status = BT_8723D_1ANT_BT_STATUS_ACL_BUSY;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n");
- BTC_TRACE(trace_buf);
- } else {
- coex_dm->bt_status = BT_8723D_1ANT_BT_STATUS_MAX;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n");
- BTC_TRACE(trace_buf);
- }
-
- if ((BT_8723D_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
- (BT_8723D_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
- (BT_8723D_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status))
- bt_busy = true;
- else
- bt_busy = false;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
-
- if (btcoexist->manual_control) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), No run_coexist_mechanism return for Manual CTRL<===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- if (btcoexist->stop_coex_dm) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), No run_coexist_mechanism return for Stop Coex DM <===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- /* don't run coex mechanism while receve BTInfo if GNT_WL/GNT_BT control by SW */
- if (!coex_sta->gnt_control_by_PTA)
- return;
-
- halbtc8723d1ant_run_coexist_mechanism(btcoexist);
-}
-
-void ex_halbtc8723d1ant_rf_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n");
- BTC_TRACE(trace_buf);
-
- if (BTC_RF_ON == type) {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RF is turned ON!!\n");
- BTC_TRACE(trace_buf);
-
- coex_sta->wl_rf_off_on_event = true;
- btcoexist->stop_coex_dm = false;
-
- halbtc8723d1ant_post_activestate_to_bt(btcoexist, TRUE);
- halbtc8723d1ant_post_onoffstate_to_bt(btcoexist, TRUE);
-
- } else if (BTC_RF_OFF == type) {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RF is turned OFF!!\n");
- BTC_TRACE(trace_buf);
-
- halbtc8723d1ant_post_activestate_to_bt(btcoexist, FALSE);
- halbtc8723d1ant_post_onoffstate_to_bt(btcoexist, FALSE);
-
- halbtc8723d1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
- halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT,
- FORCE_EXEC, false, true);
-
- btcoexist->stop_coex_dm = true;
- coex_sta->wl_rf_off_on_event = false;
- }
-}
-
-void ex_halbtc8723d1ant_halt_notify(IN struct btc_coexist *btcoexist)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n");
- BTC_TRACE(trace_buf);
-
- /* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */
- halbtc8723d1ant_enable_gnt_to_gpio(btcoexist, FALSE);
-
-
- halbtc8723d1ant_post_activestate_to_bt(btcoexist, FALSE);
- halbtc8723d1ant_post_onoffstate_to_bt(btcoexist, FALSE);
-
- halbtc8723d1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
- halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT, FORCE_EXEC,
- false, true);
-
- halbtc8723d1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
-
- ex_halbtc8723d1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
-
- btcoexist->stop_coex_dm = true;
-}
-
-void ex_halbtc8723d1ant_pnp_notify(IN struct btc_coexist *btcoexist,
- IN u8 pnp_state)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n");
- BTC_TRACE(trace_buf);
-
- if (BTC_WIFI_PNP_SLEEP == pnp_state) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Pnp notify to SLEEP\n");
- BTC_TRACE(trace_buf);
-
- /* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */
- halbtc8723d1ant_enable_gnt_to_gpio(btcoexist, FALSE);
-
- halbtc8723d1ant_post_activestate_to_bt(btcoexist, FALSE);
- halbtc8723d1ant_post_onoffstate_to_bt(btcoexist, FALSE);
-
- halbtc8723d1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_BT,
- FORCE_EXEC, false, true);
-
- btcoexist->stop_coex_dm = true;
- } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Pnp notify to WAKE UP\n");
- BTC_TRACE(trace_buf);
-
- halbtc8723d1ant_post_activestate_to_bt(btcoexist, TRUE);
- halbtc8723d1ant_post_onoffstate_to_bt(btcoexist, TRUE);
-
- btcoexist->stop_coex_dm = false;
- }
-}
-
-
-void ex_halbtc8723d1ant_coex_dm_reset(IN struct btc_coexist *btcoexist)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], *****************Coex DM Reset*****************\n");
- BTC_TRACE(trace_buf);
-
- halbtc8723d1ant_init_hw_config(btcoexist, false, false);
- halbtc8723d1ant_init_coex_dm(btcoexist);
-}
-
-void ex_halbtc8723d1ant_periodical(IN struct btc_coexist *btcoexist)
-{
-
-#if (BT_AUTO_REPORT_ONLY_8723D_1ANT == 0)
- halbtc8723d1ant_query_bt_info(btcoexist);
-
-#endif
-
- halbtc8723d1ant_monitor_bt_ctr(btcoexist);
- halbtc8723d1ant_monitor_wifi_ctr(btcoexist);
-
- halbtc8723d1ant_monitor_bt_enable_disable(btcoexist);
-
- /* for 4-way, DHCP, EAPOL packet */
- if (coex_sta->specific_pkt_period_cnt > 0) {
-
- coex_sta->specific_pkt_period_cnt--;
-
- if ((coex_sta->specific_pkt_period_cnt == 0) && (coex_sta->wifi_is_high_pri_task))
- coex_sta->wifi_is_high_pri_task = false;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ***************** Hi-Pri Task = %s*****************\n", (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"));
- BTC_TRACE(trace_buf);
-
- }
-
- if (halbtc8723d1ant_is_wifibt_status_changed(btcoexist))
- halbtc8723d1ant_run_coexist_mechanism(btcoexist);
-
-
-}
-
-void ex_halbtc8723d1ant_antenna_detection(IN struct btc_coexist *btcoexist,
- IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
-{
-#if BT_8723D_1ANT_ANTDET_ENABLE
- static u32 ant_det_count = 0, ant_det_fail_count = 0;
- struct btc_board_info *board_info = &btcoexist->board_info;
- /*boolean scan, roam;*/
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx Call AntennaDetect()!!\n");
- BTC_TRACE(trace_buf);
-
- if (seconds == 0) {
- psd_scan->ant_det_try_count = 0;
- psd_scan->ant_det_fail_count = 0;
- ant_det_count = 0;
- ant_det_fail_count = 0;
- board_info->btdm_ant_det_finish = false;
- board_info->btdm_ant_num_by_ant_det = 1;
- return;
- }
-
- if (!board_info->btdm_ant_det_finish) {
- psd_scan->ant_det_inteval_count =
- psd_scan->ant_det_inteval_count + 2;
-
- if (psd_scan->ant_det_inteval_count >=
- BT_8723D_2ANT_ANTDET_RETRY_INTERVAL) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Timer is up, Try Detect!!\n");
- BTC_TRACE(trace_buf);
- halbtc8723d1ant_psd_antenna_detection_check(btcoexist);
-
- if (board_info->btdm_ant_det_finish) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Success!!\n");
- BTC_TRACE(trace_buf);
-#if 1
- if (board_info->btdm_ant_num_by_ant_det == 2)
- halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_WIFI,
- FORCE_EXEC, false, false);
- else
- halbtc8723d1ant_set_ant_path(btcoexist, BTC_ANT_PATH_PTA,
- FORCE_EXEC, false, false);
-#endif
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Fail!!\n");
- BTC_TRACE(trace_buf);
- }
- psd_scan->ant_det_inteval_count = 0;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Timer is not up! (%d)\n",
- psd_scan->ant_det_inteval_count);
- BTC_TRACE(trace_buf);
- }
-
- }
-#endif
-
-
-}
-
-
-void ex_halbtc8723d1ant_display_ant_detection(IN struct btc_coexist *btcoexist)
-{
-#if BT_8723D_1ANT_ANTDET_ENABLE
- struct btc_board_info *board_info = &btcoexist->board_info;
-
- if (psd_scan->ant_det_try_count != 0) {
- halbtc8723d1ant_psd_show_antenna_detect_result(btcoexist);
-
- if (board_info->btdm_ant_det_finish)
- halbtc8723d1ant_psd_showdata(btcoexist);
- return;
- }
-#endif
-
-}
-
-void ex_halbtc8723d1ant_antenna_isolation(IN struct btc_coexist *btcoexist,
- IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
-{
-
-
-}
-
-void ex_halbtc8723d1ant_psd_scan(IN struct btc_coexist *btcoexist,
- IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
-{
-
-
-}
-
-
-#endif
-
-#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */
diff --git a/hal/btc/halbtc8723d1ant.h b/hal/btc/halbtc8723d1ant.h
deleted file mode 100644
index 2ccd575..0000000
--- a/hal/btc/halbtc8723d1ant.h
+++ /dev/null
@@ -1,348 +0,0 @@
-
-#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
-
-#if (RTL8723D_SUPPORT == 1)
-
-/* *******************************************
- * The following is for 8723D 1ANT BT Co-exist definition
- * ******************************************* */
-#define BT_AUTO_REPORT_ONLY_8723D_1ANT 1
-
-#define BT_INFO_8723D_1ANT_B_FTP BIT(7)
-#define BT_INFO_8723D_1ANT_B_A2DP BIT(6)
-#define BT_INFO_8723D_1ANT_B_HID BIT(5)
-#define BT_INFO_8723D_1ANT_B_SCO_BUSY BIT(4)
-#define BT_INFO_8723D_1ANT_B_ACL_BUSY BIT(3)
-#define BT_INFO_8723D_1ANT_B_INQ_PAGE BIT(2)
-#define BT_INFO_8723D_1ANT_B_SCO_ESCO BIT(1)
-#define BT_INFO_8723D_1ANT_B_CONNECTION BIT(0)
-
-#define BT_INFO_8723D_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \
- (((_BT_INFO_EXT_&BIT(0))) ? true : false)
-
-#define BTC_RSSI_COEX_THRESH_TOL_8723D_1ANT 2
-
-#define BT_8723D_1ANT_WIFI_NOISY_THRESH 30 /* max: 255 */
-
-/* for Antenna detection */
-#define BT_8723D_1ANT_ANTDET_PSDTHRES_BACKGROUND 50
-#define BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION 70
-#define BT_8723D_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION 55
-#define BT_8723D_1ANT_ANTDET_PSDTHRES_1ANT 35
-#define BT_8723D_1ANT_ANTDET_RETRY_INTERVAL 10 /* retry timer if ant det is fail, unit: second */
-#define BT_8723D_1ANT_ANTDET_SWEEPPOINT_DELAY 40000
-#define BT_8723D_1ANT_ANTDET_ENABLE 0
-#define BT_8723D_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE 0
-#define BT_8723D_1ANT_ANTDET_BTTXTIME 100
-#define BT_8723D_1ANT_ANTDET_BTTXCHANNEL 39
-
-#define BT_8723D_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT 30000
-
-enum bt_8723d_1ant_signal_state {
- BT_8723D_1ANT_SIG_STA_SET_TO_LOW = 0x0,
- BT_8723D_1ANT_SIG_STA_SET_BY_HW = 0x0,
- BT_8723D_1ANT_SIG_STA_SET_TO_HIGH = 0x1,
- BT_8723D_1ANT_SIG_STA_MAX
-};
-
-enum bt_8723d_1ant_path_ctrl_owner {
- BT_8723D_1ANT_PCO_BTSIDE = 0x0,
- BT_8723D_1ANT_PCO_WLSIDE = 0x1,
- BT_8723D_1ANT_PCO_MAX
-};
-
-enum bt_8723d_1ant_gnt_ctrl_type {
- BT_8723D_1ANT_GNT_TYPE_CTRL_BY_PTA = 0x0,
- BT_8723D_1ANT_GNT_TYPE_CTRL_BY_SW = 0x1,
- BT_8723D_1ANT_GNT_TYPE_MAX
-};
-
-enum bt_8723d_1ant_gnt_ctrl_block {
- BT_8723D_1ANT_GNT_BLOCK_RFC_BB = 0x0,
- BT_8723D_1ANT_GNT_BLOCK_RFC = 0x1,
- BT_8723D_1ANT_GNT_BLOCK_BB = 0x2,
- BT_8723D_1ANT_GNT_BLOCK_MAX
-};
-
-enum bt_8723d_1ant_lte_coex_table_type {
- BT_8723D_1ANT_CTT_WL_VS_LTE = 0x0,
- BT_8723D_1ANT_CTT_BT_VS_LTE = 0x1,
- BT_8723D_1ANT_CTT_MAX
-};
-
-enum bt_8723d_1ant_lte_break_table_type {
- BT_8723D_1ANT_LBTT_WL_BREAK_LTE = 0x0,
- BT_8723D_1ANT_LBTT_BT_BREAK_LTE = 0x1,
- BT_8723D_1ANT_LBTT_LTE_BREAK_WL = 0x2,
- BT_8723D_1ANT_LBTT_LTE_BREAK_BT = 0x3,
- BT_8723D_1ANT_LBTT_MAX
-};
-
-enum bt_info_src_8723d_1ant {
- BT_INFO_SRC_8723D_1ANT_WIFI_FW = 0x0,
- BT_INFO_SRC_8723D_1ANT_BT_RSP = 0x1,
- BT_INFO_SRC_8723D_1ANT_BT_ACTIVE_SEND = 0x2,
- BT_INFO_SRC_8723D_1ANT_MAX
-};
-
-enum bt_8723d_1ant_bt_status {
- BT_8723D_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
- BT_8723D_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
- BT_8723D_1ANT_BT_STATUS_INQ_PAGE = 0x2,
- BT_8723D_1ANT_BT_STATUS_ACL_BUSY = 0x3,
- BT_8723D_1ANT_BT_STATUS_SCO_BUSY = 0x4,
- BT_8723D_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
- BT_8723D_1ANT_BT_STATUS_MAX
-};
-
-enum bt_8723d_1ant_wifi_status {
- BT_8723D_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0,
- BT_8723D_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1,
- BT_8723D_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2,
- BT_8723D_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT = 0x3,
- BT_8723D_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4,
- BT_8723D_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5,
- BT_8723D_1ANT_WIFI_STATUS_MAX
-};
-
-enum bt_8723d_1ant_coex_algo {
- BT_8723D_1ANT_COEX_ALGO_UNDEFINED = 0x0,
- BT_8723D_1ANT_COEX_ALGO_SCO = 0x1,
- BT_8723D_1ANT_COEX_ALGO_HID = 0x2,
- BT_8723D_1ANT_COEX_ALGO_A2DP = 0x3,
- BT_8723D_1ANT_COEX_ALGO_A2DP_PANHS = 0x4,
- BT_8723D_1ANT_COEX_ALGO_PANEDR = 0x5,
- BT_8723D_1ANT_COEX_ALGO_PANHS = 0x6,
- BT_8723D_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
- BT_8723D_1ANT_COEX_ALGO_PANEDR_HID = 0x8,
- BT_8723D_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
- BT_8723D_1ANT_COEX_ALGO_HID_A2DP = 0xa,
- BT_8723D_1ANT_COEX_ALGO_MAX = 0xb,
-};
-
-struct coex_dm_8723d_1ant {
- /* hw setting */
- u8 pre_ant_pos_type;
- u8 cur_ant_pos_type;
- /* fw mechanism */
- boolean cur_ignore_wlan_act;
- boolean pre_ignore_wlan_act;
- u8 pre_ps_tdma;
- u8 cur_ps_tdma;
- u8 ps_tdma_para[5];
- u8 ps_tdma_du_adj_type;
- boolean auto_tdma_adjust;
- boolean pre_ps_tdma_on;
- boolean cur_ps_tdma_on;
- boolean pre_bt_auto_report;
- boolean cur_bt_auto_report;
- u8 pre_lps;
- u8 cur_lps;
- u8 pre_rpwm;
- u8 cur_rpwm;
-
- /* sw mechanism */
- boolean pre_low_penalty_ra;
- boolean cur_low_penalty_ra;
- u32 pre_val0x6c0;
- u32 cur_val0x6c0;
- u32 pre_val0x6c4;
- u32 cur_val0x6c4;
- u32 pre_val0x6c8;
- u32 cur_val0x6c8;
- u8 pre_val0x6cc;
- u8 cur_val0x6cc;
- boolean limited_dig;
-
- u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */
- u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */
- u16 backup_retry_limit;
- u8 backup_ampdu_max_time;
-
- /* algorithm related */
- u8 pre_algorithm;
- u8 cur_algorithm;
- u8 bt_status;
- u8 wifi_chnl_info[3];
-
- u32 pre_ra_mask;
- u32 cur_ra_mask;
- u8 pre_arfr_type;
- u8 cur_arfr_type;
- u8 pre_retry_limit_type;
- u8 cur_retry_limit_type;
- u8 pre_ampdu_time_type;
- u8 cur_ampdu_time_type;
- u32 arp_cnt;
-
- u8 error_condition;
-};
-
-struct coex_sta_8723d_1ant {
- boolean bt_disabled;
- boolean bt_link_exist;
- boolean sco_exist;
- boolean a2dp_exist;
- boolean hid_exist;
- boolean pan_exist;
- boolean bt_hi_pri_link_exist;
- u8 num_of_profile;
-
- boolean under_lps;
- boolean under_ips;
- u32 specific_pkt_period_cnt;
- u32 high_priority_tx;
- u32 high_priority_rx;
- u32 low_priority_tx;
- u32 low_priority_rx;
- s8 bt_rssi;
- boolean bt_tx_rx_mask;
- u8 pre_bt_rssi_state;
- u8 pre_wifi_rssi_state[4];
- boolean c2h_bt_info_req_sent;
- u8 bt_info_c2h[BT_INFO_SRC_8723D_1ANT_MAX][10];
- u32 bt_info_c2h_cnt[BT_INFO_SRC_8723D_1ANT_MAX];
- boolean bt_whck_test;
- boolean c2h_bt_inquiry_page;
- boolean c2h_bt_page; /* Add for win8.1 page out issue */
- boolean wifi_is_high_pri_task; /* Add for win8.1 page out issue */
- u8 bt_retry_cnt;
- u8 bt_info_ext;
- u32 pop_event_cnt;
- u8 scan_ap_num;
-
- u32 crc_ok_cck;
- u32 crc_ok_11g;
- u32 crc_ok_11n;
- u32 crc_ok_11n_agg;
-
- u32 crc_err_cck;
- u32 crc_err_11g;
- u32 crc_err_11n;
- u32 crc_err_11n_agg;
-
- boolean cck_lock;
- boolean pre_ccklock;
- boolean cck_ever_lock;
- u8 coex_table_type;
-
- boolean force_lps_on;
- u32 wrong_profile_notification;
-
- boolean concurrent_rx_mode_on;
-
- u16 score_board;
-
- u8 a2dp_bit_pool;
- u8 cut_version;
- boolean acl_busy;
- boolean wl_rf_off_on_event;
- boolean bt_create_connection;
- boolean gnt_control_by_PTA;
-};
-
-#define BT_8723D_1ANT_ANTDET_PSD_POINTS 256 /* MAX:1024 */
-#define BT_8723D_1ANT_ANTDET_PSD_AVGNUM 1 /* MAX:3 */
-#define BT_8723D_1ANT_ANTDET_BUF_LEN 16
-
-struct psdscan_sta_8723d_1ant {
-
- u32 ant_det_bt_le_channel; /* BT LE Channel ex:2412 */
- u32 ant_det_bt_tx_time;
- u32 ant_det_pre_psdscan_peak_val;
- boolean ant_det_is_ant_det_available;
- u32 ant_det_psd_scan_peak_val;
- boolean ant_det_is_btreply_available;
- u32 ant_det_psd_scan_peak_freq;
-
- u8 ant_det_result;
- u8 ant_det_peak_val[BT_8723D_1ANT_ANTDET_BUF_LEN];
- u8 ant_det_peak_freq[BT_8723D_1ANT_ANTDET_BUF_LEN];
- u32 ant_det_try_count;
- u32 ant_det_fail_count;
- u32 ant_det_inteval_count;
- u32 ant_det_thres_offset;
-
- u32 real_cent_freq;
- s32 real_offset;
- u32 real_span;
-
- u32 psd_band_width; /* unit: Hz */
- u32 psd_point; /* 128/256/512/1024 */
- u32 psd_report[1024]; /* unit:dB (20logx), 0~255 */
- u32 psd_report_max_hold[1024]; /* unit:dB (20logx), 0~255 */
- u32 psd_start_point;
- u32 psd_stop_point;
- u32 psd_max_value_point;
- u32 psd_max_value;
- u32 psd_start_base;
- u32 psd_avg_num; /* 1/8/16/32 */
- u32 psd_gen_count;
- boolean is_psd_running;
- boolean is_psd_show_max_only;
-};
-
-/* *******************************************
- * The following is interface which will notify coex module.
- * ******************************************* */
-void ex_halbtc8723d1ant_power_on_setting(IN struct btc_coexist *btcoexist);
-void ex_halbtc8723d1ant_pre_load_firmware(IN struct btc_coexist *btcoexist);
-void ex_halbtc8723d1ant_init_hw_config(IN struct btc_coexist *btcoexist,
- IN boolean wifi_only);
-void ex_halbtc8723d1ant_init_coex_dm(IN struct btc_coexist *btcoexist);
-void ex_halbtc8723d1ant_ips_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8723d1ant_lps_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8723d1ant_scan_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8723d1ant_connect_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8723d1ant_media_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8723d1ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8723d1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
- IN u8 *tmp_buf, IN u8 length);
-void ex_halbtc8723d1ant_rf_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8723d1ant_halt_notify(IN struct btc_coexist *btcoexist);
-void ex_halbtc8723d1ant_pnp_notify(IN struct btc_coexist *btcoexist,
- IN u8 pnp_state);
-void ex_halbtc8723d1ant_coex_dm_reset(IN struct btc_coexist *btcoexist);
-void ex_halbtc8723d1ant_periodical(IN struct btc_coexist *btcoexist);
-void ex_halbtc8723d1ant_display_coex_info(IN struct btc_coexist *btcoexist);
-void ex_halbtc8723d1ant_antenna_detection(IN struct btc_coexist *btcoexist,
- IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds);
-void ex_halbtc8723d1ant_antenna_isolation(IN struct btc_coexist *btcoexist,
- IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds);
-
-void ex_halbtc8723d1ant_psd_scan(IN struct btc_coexist *btcoexist,
- IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds);
-void ex_halbtc8723d1ant_display_ant_detection(IN struct btc_coexist *btcoexist);
-
-#else
-#define ex_halbtc8723d1ant_power_on_setting(btcoexist)
-#define ex_halbtc8723d1ant_pre_load_firmware(btcoexist)
-#define ex_halbtc8723d1ant_init_hw_config(btcoexist, wifi_only)
-#define ex_halbtc8723d1ant_init_coex_dm(btcoexist)
-#define ex_halbtc8723d1ant_ips_notify(btcoexist, type)
-#define ex_halbtc8723d1ant_lps_notify(btcoexist, type)
-#define ex_halbtc8723d1ant_scan_notify(btcoexist, type)
-#define ex_halbtc8723d1ant_connect_notify(btcoexist, type)
-#define ex_halbtc8723d1ant_media_status_notify(btcoexist, type)
-#define ex_halbtc8723d1ant_specific_packet_notify(btcoexist, type)
-#define ex_halbtc8723d1ant_bt_info_notify(btcoexist, tmp_buf, length)
-#define ex_halbtc8723d1ant_rf_status_notify(btcoexist, type)
-#define ex_halbtc8723d1ant_halt_notify(btcoexist)
-#define ex_halbtc8723d1ant_pnp_notify(btcoexist, pnp_state)
-#define ex_halbtc8723d1ant_coex_dm_reset(btcoexist)
-#define ex_halbtc8723d1ant_periodical(btcoexist)
-#define ex_halbtc8723d1ant_display_coex_info(btcoexist)
-#define ex_halbtc8723d1ant_antenna_detection(btcoexist, cent_freq, offset, span, seconds)
-#define ex_halbtc8723d1ant_antenna_isolation(btcoexist, cent_freq, offset, span, seconds)
-#define ex_halbtc8723d1ant_psd_scan(btcoexist, cent_freq, offset, span, seconds)
-#define ex_halbtc8723d1ant_display_ant_detection(btcoexist)
-#endif
-
-#endif
diff --git a/hal/btc/halbtc8723d2ant.c b/hal/btc/halbtc8723d2ant.c
deleted file mode 100644
index a2801ae..0000000
--- a/hal/btc/halbtc8723d2ant.c
+++ /dev/null
@@ -1,5411 +0,0 @@
-/* ************************************************************
- * Description:
- *
- * This file is for RTL8723D Co-exist mechanism
- *
- * History
- * 2012/11/15 Cosa first check in.
- *
- * ************************************************************ */
-
-/* ************************************************************
- * include files
- * ************************************************************ */
-#include "Mp_Precomp.h"
-
-#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
-
-#if (RTL8723D_SUPPORT == 1)
-/* ************************************************************
- * Global variables, these are static variables
- * ************************************************************ */
-static u8 *trace_buf = &gl_btc_trace_buf[0];
-static struct coex_dm_8723d_2ant glcoex_dm_8723d_2ant;
-static struct coex_dm_8723d_2ant *coex_dm = &glcoex_dm_8723d_2ant;
-static struct coex_sta_8723d_2ant glcoex_sta_8723d_2ant;
-static struct coex_sta_8723d_2ant *coex_sta = &glcoex_sta_8723d_2ant;
-static struct psdscan_sta_8723d_2ant gl_psd_scan_8723d_2ant;
-static struct psdscan_sta_8723d_2ant *psd_scan = &gl_psd_scan_8723d_2ant;
-
-const char *const glbt_info_src_8723d_2ant[] = {
- "BT Info[wifi fw]",
- "BT Info[bt rsp]",
- "BT Info[bt auto report]",
-};
-
-u32 glcoex_ver_date_8723d_2ant = 20160218;
-u32 glcoex_ver_8723d_2ant = 0x05;
-
-/* ************************************************************
- * local function proto type if needed
- * ************************************************************
- * ************************************************************
- * local function start with halbtc8723d2ant_
- * ************************************************************ */
-u8 halbtc8723d2ant_bt_rssi_state(u8 *ppre_bt_rssi_state, u8 level_num,
- u8 rssi_thresh, u8 rssi_thresh1)
-{
- s32 bt_rssi = 0;
- u8 bt_rssi_state = *ppre_bt_rssi_state;
-
- bt_rssi = coex_sta->bt_rssi;
-
- if (level_num == 2) {
- if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
- (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
- if (bt_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8723D_2ANT))
- bt_rssi_state = BTC_RSSI_STATE_HIGH;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else {
- if (bt_rssi < rssi_thresh)
- bt_rssi_state = BTC_RSSI_STATE_LOW;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- } else if (level_num == 3) {
- if (rssi_thresh > rssi_thresh1) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT Rssi thresh error!!\n");
- BTC_TRACE(trace_buf);
- return *ppre_bt_rssi_state;
- }
-
- if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
- (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
- if (bt_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8723D_2ANT))
- bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
- (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
- if (bt_rssi >= (rssi_thresh1 +
- BTC_RSSI_COEX_THRESH_TOL_8723D_2ANT))
- bt_rssi_state = BTC_RSSI_STATE_HIGH;
- else if (bt_rssi < rssi_thresh)
- bt_rssi_state = BTC_RSSI_STATE_LOW;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
- } else {
- if (bt_rssi < rssi_thresh1)
- bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- }
-
- *ppre_bt_rssi_state = bt_rssi_state;
-
- return bt_rssi_state;
-}
-
-u8 halbtc8723d2ant_wifi_rssi_state(IN struct btc_coexist *btcoexist,
- IN u8 *pprewifi_rssi_state, IN u8 level_num, IN u8 rssi_thresh,
- IN u8 rssi_thresh1)
-{
- s32 wifi_rssi = 0;
- u8 wifi_rssi_state = *pprewifi_rssi_state;
-
- btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
-
- if (level_num == 2) {
- if ((*pprewifi_rssi_state == BTC_RSSI_STATE_LOW) ||
- (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
- if (wifi_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8723D_2ANT))
- wifi_rssi_state = BTC_RSSI_STATE_HIGH;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else {
- if (wifi_rssi < rssi_thresh)
- wifi_rssi_state = BTC_RSSI_STATE_LOW;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- } else if (level_num == 3) {
- if (rssi_thresh > rssi_thresh1) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], wifi RSSI thresh error!!\n");
- BTC_TRACE(trace_buf);
- return *pprewifi_rssi_state;
- }
-
- if ((*pprewifi_rssi_state == BTC_RSSI_STATE_LOW) ||
- (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
- if (wifi_rssi >= (rssi_thresh +
- BTC_RSSI_COEX_THRESH_TOL_8723D_2ANT))
- wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
- } else if ((*pprewifi_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
- (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
- if (wifi_rssi >= (rssi_thresh1 +
- BTC_RSSI_COEX_THRESH_TOL_8723D_2ANT))
- wifi_rssi_state = BTC_RSSI_STATE_HIGH;
- else if (wifi_rssi < rssi_thresh)
- wifi_rssi_state = BTC_RSSI_STATE_LOW;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
- } else {
- if (wifi_rssi < rssi_thresh1)
- wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
- else
- wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
- }
- }
-
- *pprewifi_rssi_state = wifi_rssi_state;
-
- return wifi_rssi_state;
-}
-
-void halbtc8723d2ant_coex_switch_threshold(IN struct btc_coexist *btcoexist,
- IN u8 isolation_measuared)
-{
- s8 interference_wl_tx = 0, interference_bt_tx = 0;
-
-
- interference_wl_tx = BT_8723D_2ANT_WIFI_MAX_TX_POWER - isolation_measuared;
- interference_bt_tx = BT_8723D_2ANT_BT_MAX_TX_POWER - isolation_measuared;
-
-
-
- coex_sta->wifi_coex_thres = BT_8723D_2ANT_WIFI_RSSI_COEXSWITCH_THRES1;
- coex_sta->wifi_coex_thres2 = BT_8723D_2ANT_WIFI_RSSI_COEXSWITCH_THRES2;
-
- coex_sta->bt_coex_thres = BT_8723D_2ANT_BT_RSSI_COEXSWITCH_THRES1;
- coex_sta->bt_coex_thres2 = BT_8723D_2ANT_BT_RSSI_COEXSWITCH_THRES2;
-
-
- /*
- coex_sta->wifi_coex_thres = interference_wl_tx + BT_8723D_2ANT_WIFI_SIR_THRES1;
- coex_sta->wifi_coex_thres2 = interference_wl_tx + BT_8723D_2ANT_WIFI_SIR_THRES2;
-
- coex_sta->bt_coex_thres = interference_bt_tx + BT_8723D_2ANT_BT_SIR_THRES1;
- coex_sta->bt_coex_thres2 = interference_bt_tx + BT_8723D_2ANT_BT_SIR_THRES2;
- */
-
-
-
-
-
- /*
- if ( BT_8723D_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 < (isolation_measuared -
- BT_8723D_2ANT_DEFAULT_ISOLATION) )
- coex_sta->wifi_coex_thres = BT_8723D_2ANT_WIFI_RSSI_COEXSWITCH_THRES1;
- else
- coex_sta->wifi_coex_thres = BT_8723D_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 - (isolation_measuared -
- BT_8723D_2ANT_DEFAULT_ISOLATION);
-
- if ( BT_8723D_2ANT_BT_RSSI_COEXSWITCH_THRES1 < (isolation_measuared -
- BT_8723D_2ANT_DEFAULT_ISOLATION) )
- coex_sta->bt_coex_thres = BT_8723D_2ANT_BT_RSSI_COEXSWITCH_THRES1;
- else
- coex_sta->bt_coex_thres = BT_8723D_2ANT_BT_RSSI_COEXSWITCH_THRES1 - (isolation_measuared -
- BT_8723D_2ANT_DEFAULT_ISOLATION);
-
- */
-}
-
-
-void halbtc8723d2ant_limited_rx(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean rej_ap_agg_pkt,
- IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size)
-{
- boolean reject_rx_agg = rej_ap_agg_pkt;
- boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size;
- u8 rx_agg_size = agg_buf_size;
-
- /* ============================================ */
- /* Rx Aggregation related setting */
- /* ============================================ */
- btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT,
- &reject_rx_agg);
- /* decide BT control aggregation buf size or not */
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE,
- &bt_ctrl_rx_agg_size);
- /* aggregation buf size, only work when BT control Rx aggregation size. */
- btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size);
- /* real update aggregation setting */
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
-}
-
-void halbtc8723d2ant_query_bt_info(IN struct btc_coexist *btcoexist)
-{
- u8 h2c_parameter[1] = {0};
-
- coex_sta->c2h_bt_info_req_sent = true;
-
- h2c_parameter[0] |= BIT(0); /* trigger */
-
- btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter);
-}
-
-void halbtc8723d2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist)
-{
- u32 reg_hp_txrx, reg_lp_txrx, u32tmp;
- u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
- static u8 num_of_bt_counter_chk = 0, cnt_slave = 0;
-
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
- reg_hp_txrx = 0x770;
- reg_lp_txrx = 0x774;
-
- u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
- reg_hp_tx = u32tmp & MASKLWORD;
- reg_hp_rx = (u32tmp & MASKHWORD) >> 16;
-
- u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
- reg_lp_tx = u32tmp & MASKLWORD;
- reg_lp_rx = (u32tmp & MASKHWORD) >> 16;
-
- coex_sta->high_priority_tx = reg_hp_tx;
- coex_sta->high_priority_rx = reg_hp_rx;
- coex_sta->low_priority_tx = reg_lp_tx;
- coex_sta->low_priority_rx = reg_lp_rx;
-
-
- /* reset counter */
- btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
-
- if ((coex_sta->low_priority_tx > 1050) &&
- (!coex_sta->c2h_bt_inquiry_page))
- coex_sta->pop_event_cnt++;
-
- if ((coex_sta->low_priority_rx >= 950) && (coex_sta->low_priority_rx >= coex_sta->low_priority_tx)
- && (!coex_sta->under_ips) && (!coex_sta->c2h_bt_inquiry_page) && (coex_sta->bt_link_exist)) {
- if (cnt_slave >= 2) {
- bt_link_info->slave_role = true;
- cnt_slave = 2;
- } else
- cnt_slave++;
- } else {
- if (cnt_slave == 0) {
- bt_link_info->slave_role = false;
- cnt_slave = 0;
- } else
- cnt_slave--;
-
- }
-
- if ((coex_sta->high_priority_tx == 0) && (coex_sta->high_priority_rx == 0) && (coex_sta->low_priority_tx == 0) &&
- (coex_sta->low_priority_rx == 0)) {
- num_of_bt_counter_chk++;
- if (num_of_bt_counter_chk >= 3) {
- halbtc8723d2ant_query_bt_info(btcoexist);
- num_of_bt_counter_chk = 0;
- }
- }
-
-}
-
-void halbtc8723d2ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist)
-{
-
-
- if (coex_sta->under_ips) {
- coex_sta->crc_ok_cck = 0;
- coex_sta->crc_ok_11g = 0;
- coex_sta->crc_ok_11n = 0;
- coex_sta->crc_ok_11n_agg = 0;
-
- coex_sta->crc_err_cck = 0;
- coex_sta->crc_err_11g = 0;
- coex_sta->crc_err_11n = 0;
- coex_sta->crc_err_11n_agg = 0;
- } else {
- coex_sta->crc_ok_cck = btcoexist->btc_read_4byte(btcoexist,
- 0xf88);
- coex_sta->crc_ok_11g = btcoexist->btc_read_2byte(btcoexist,
- 0xf94);
- coex_sta->crc_ok_11n = btcoexist->btc_read_2byte(btcoexist,
- 0xf90);
- coex_sta->crc_ok_11n_agg = btcoexist->btc_read_2byte(btcoexist,
- 0xfb8);
-
- coex_sta->crc_err_cck = btcoexist->btc_read_4byte(btcoexist,
- 0xf84);
- coex_sta->crc_err_11g = btcoexist->btc_read_2byte(btcoexist,
- 0xf96);
- coex_sta->crc_err_11n = btcoexist->btc_read_2byte(btcoexist,
- 0xf92);
- coex_sta->crc_err_11n_agg = btcoexist->btc_read_2byte(btcoexist,
- 0xfba);
- }
-
- /* reset counter */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xf16, 0x1, 0x1);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0xf16, 0x1, 0x0);
-}
-
-
-boolean halbtc8723d2ant_is_wifibt_status_changed(IN struct btc_coexist *btcoexist)
-{
- static boolean pre_wifi_busy = false, pre_under_4way = false,
- pre_bt_hs_on = false, pre_bt_off = false;
- static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
- boolean wifi_busy = false, under_4way = false, bt_hs_on = false;
- boolean wifi_connected = false;
- u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH;
-
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
- &under_4way);
-
- if (coex_sta->bt_disabled != pre_bt_off) {
- pre_bt_off = coex_sta->bt_disabled;
-
- if (coex_sta->bt_disabled)
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is disabled !!\n");
- else
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is enabled !!\n");
-
- BTC_TRACE(trace_buf);
- return true;
- }
-
- if (wifi_connected) {
- if (wifi_busy != pre_wifi_busy) {
- pre_wifi_busy = wifi_busy;
- return true;
- }
- if (under_4way != pre_under_4way) {
- pre_under_4way = under_4way;
- return true;
- }
- if (bt_hs_on != pre_bt_hs_on) {
- pre_bt_hs_on = bt_hs_on;
- return true;
- }
-
- }
-
- return false;
-}
-
-void halbtc8723d2ant_update_bt_link_info(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean bt_hs_on = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
-
- bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
- bt_link_info->sco_exist = coex_sta->sco_exist;
- bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
- bt_link_info->pan_exist = coex_sta->pan_exist;
- bt_link_info->hid_exist = coex_sta->hid_exist;
- bt_link_info->acl_busy = coex_sta->acl_busy;
-
- /* work around for HS mode. */
- if (bt_hs_on) {
- bt_link_info->pan_exist = true;
- bt_link_info->bt_link_exist = true;
- }
-
- /* check if Sco only */
- if (bt_link_info->sco_exist &&
- !bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist &&
- !bt_link_info->hid_exist)
- bt_link_info->sco_only = true;
- else
- bt_link_info->sco_only = false;
-
- /* check if A2dp only */
- if (!bt_link_info->sco_exist &&
- bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist &&
- !bt_link_info->hid_exist)
- bt_link_info->a2dp_only = true;
- else
- bt_link_info->a2dp_only = false;
-
- /* check if Pan only */
- if (!bt_link_info->sco_exist &&
- !bt_link_info->a2dp_exist &&
- bt_link_info->pan_exist &&
- !bt_link_info->hid_exist)
- bt_link_info->pan_only = true;
- else
- bt_link_info->pan_only = false;
-
- /* check if Hid only */
- if (!bt_link_info->sco_exist &&
- !bt_link_info->a2dp_exist &&
- !bt_link_info->pan_exist &&
- bt_link_info->hid_exist)
- bt_link_info->hid_only = true;
- else
- bt_link_info->hid_only = false;
-}
-
-void halbtc8723d2ant_update_wifi_channel_info(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- u8 h2c_parameter[3] = {0};
- u32 wifi_bw;
- u8 wifi_central_chnl;
-
- /* only 2.4G we need to inform bt the chnl mask */
- btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
- &wifi_central_chnl);
- if ((BTC_MEDIA_CONNECT == type) &&
- (wifi_central_chnl <= 14)) {
- h2c_parameter[0] =
- 0x1; /* enable BT AFH skip WL channel for 8723d because BT Rx LO interference */
- /* h2c_parameter[0] = 0x0; */
- h2c_parameter[1] = wifi_central_chnl;
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
- if (BTC_WIFI_BW_HT40 == wifi_bw)
- h2c_parameter[2] = 0x30;
- else
- h2c_parameter[2] = 0x20;
- }
-
- coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
- coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
- coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
-
- btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter);
-
-}
-
-void halbtc8723d2ant_set_fw_dac_swing_level(IN struct btc_coexist *btcoexist,
- IN u8 dac_swing_lvl)
-{
- u8 h2c_parameter[1] = {0};
-
- /* There are several type of dacswing */
- /* 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */
- h2c_parameter[0] = dac_swing_lvl;
-
- btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter);
-}
-
-void halbtc8723d2ant_fw_dac_swing_lvl(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 fw_dac_swing_lvl)
-{
- coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl;
-
- if (!force_exec) {
- if (coex_dm->pre_fw_dac_swing_lvl ==
- coex_dm->cur_fw_dac_swing_lvl)
- return;
- }
-
- halbtc8723d2ant_set_fw_dac_swing_level(btcoexist,
- coex_dm->cur_fw_dac_swing_lvl);
-
- coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl;
-}
-
-void halbtc8723d2ant_set_fw_dec_bt_pwr(IN struct btc_coexist *btcoexist,
- IN u8 dec_bt_pwr_lvl)
-{
- u8 h2c_parameter[1] = {0};
-
- h2c_parameter[0] = dec_bt_pwr_lvl;
-
- btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter);
-}
-
-void halbtc8723d2ant_dec_bt_pwr(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 dec_bt_pwr_lvl)
-{
- coex_dm->cur_bt_dec_pwr_lvl = dec_bt_pwr_lvl;
-
- if (!force_exec) {
- if (coex_dm->pre_bt_dec_pwr_lvl == coex_dm->cur_bt_dec_pwr_lvl)
- return;
- }
- halbtc8723d2ant_set_fw_dec_bt_pwr(btcoexist,
- coex_dm->cur_bt_dec_pwr_lvl);
-
- coex_dm->pre_bt_dec_pwr_lvl = coex_dm->cur_bt_dec_pwr_lvl;
-}
-
-void halbtc8723d2ant_set_fw_low_penalty_ra(IN struct btc_coexist
- *btcoexist, IN boolean low_penalty_ra)
-{
- u8 h2c_parameter[6] = {0};
-
- h2c_parameter[0] = 0x6; /* op_code, 0x6= Retry_Penalty */
-
- if (low_penalty_ra) {
- h2c_parameter[1] |= BIT(0);
- h2c_parameter[2] =
- 0x00; /* normal rate except MCS7/6/5, OFDM54/48/36 */
- h2c_parameter[3] = 0xf7; /* MCS7 or OFDM54 */
- h2c_parameter[4] = 0xf8; /* MCS6 or OFDM48 */
- h2c_parameter[5] = 0xf9; /* MCS5 or OFDM36 */
- }
-
- btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter);
-}
-
-void halbtc8723d2ant_low_penalty_ra(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean low_penalty_ra)
-{
- coex_dm->cur_low_penalty_ra = low_penalty_ra;
-
- if (!force_exec) {
- if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra)
- return;
- }
- halbtc8723d2ant_set_fw_low_penalty_ra(btcoexist,
- coex_dm->cur_low_penalty_ra);
-
- coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra;
-}
-
-void halbtc8723d2ant_set_bt_auto_report(IN struct btc_coexist *btcoexist,
- IN boolean enable_auto_report)
-{
- u8 h2c_parameter[1] = {0};
-
- h2c_parameter[0] = 0;
-
- if (enable_auto_report)
- h2c_parameter[0] |= BIT(0);
-
- btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter);
-}
-
-void halbtc8723d2ant_bt_auto_report(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean enable_auto_report)
-{
- coex_dm->cur_bt_auto_report = enable_auto_report;
-
- if (!force_exec) {
- if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report)
- return;
- }
- halbtc8723d2ant_set_bt_auto_report(btcoexist,
- coex_dm->cur_bt_auto_report);
-
- coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report;
-}
-
-void halbtc8723d2ant_sw_mechanism1(IN struct btc_coexist *btcoexist,
- IN boolean shrink_rx_lpf, IN boolean low_penalty_ra,
- IN boolean limited_dig, IN boolean bt_lna_constrain)
-{
-
- halbtc8723d2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra);
-}
-
-void halbtc8723d2ant_sw_mechanism2(IN struct btc_coexist *btcoexist,
- IN boolean agc_table_shift, IN boolean adc_back_off,
- IN boolean sw_dac_swing, IN u32 dac_swing_lvl)
-{
- /* halbtc8723d2ant_agc_table(btcoexist, NORMAL_EXEC, agc_table_shift); */
- /* halbtc8723d2ant_adc_back_off(btcoexist, NORMAL_EXEC, adc_back_off); */
-}
-
-void halbtc8723d2ant_write_score_board(
- IN struct btc_coexist *btcoexist,
- IN u16 bitpos,
- IN BOOLEAN state
-)
-{
-
- static u16 originalval = 0x8002;
-
- if (state)
- originalval = originalval | bitpos;
- else
- originalval = originalval & (~bitpos);
-
-
- btcoexist->btc_write_2byte(btcoexist, 0xaa, originalval);
-
-}
-
-void halbtc8723d2ant_read_score_board(
- IN struct btc_coexist *btcoexist,
- IN u16 *score_board_val
-)
-{
-
- *score_board_val = (btcoexist->btc_read_2byte(btcoexist,
- 0xaa)) & 0x7fff;
-}
-
-void halbtc8723d2ant_post_activestate_to_bt(
- IN struct btc_coexist *btcoexist,
- IN boolean wifi_active
-)
-{
-
- if (wifi_active)
- halbtc8723d2ant_write_score_board(btcoexist, (u16) BIT(0), TRUE);
- else
- halbtc8723d2ant_write_score_board(btcoexist, (u16) BIT(0), FALSE);
-
- /* The BT should set "No Shunt-down" mode if WL = Active for BT Synthesizer on/off interference WL Lo issue at 8703b b-cut. */
-
-}
-
-void halbtc8723d2ant_post_onoffstate_to_bt(
- IN struct btc_coexist *btcoexist,
- IN boolean wifi_on
-)
-{
-
- if (wifi_on)
- halbtc8723d2ant_write_score_board(btcoexist, (u16) BIT(1), TRUE);
- else
- halbtc8723d2ant_write_score_board(btcoexist, (u16) BIT(1), FALSE);
-
-}
-
-void halbtc8723d2ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist)
-{
- static u32 bt_disable_cnt = 0;
- boolean bt_active = true, bt_disabled = false;
- u16 u16tmp;
-
- /* This function check if bt is disabled */
-#if 0
- if (coex_sta->high_priority_tx == 0 &&
- coex_sta->high_priority_rx == 0 &&
- coex_sta->low_priority_tx == 0 &&
- coex_sta->low_priority_rx == 0)
- bt_active = false;
- if (coex_sta->high_priority_tx == 0xffff &&
- coex_sta->high_priority_rx == 0xffff &&
- coex_sta->low_priority_tx == 0xffff &&
- coex_sta->low_priority_rx == 0xffff)
- bt_active = false;
-
-
-#else
-
- /* Read BT on/off status from scoreboard[1], enable this only if BT patch support this feature */
- halbtc8723d2ant_read_score_board(btcoexist, &u16tmp);
-
- bt_active = u16tmp & BIT(1);
-
-
-#endif
-
- if (bt_active) {
- bt_disable_cnt = 0;
- bt_disabled = false;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
- &bt_disabled);
- } else {
-
- bt_disable_cnt++;
- if (bt_disable_cnt >= 2) {
- bt_disabled = true;
- bt_disable_cnt = 2;
- }
-
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
- &bt_disabled);
- }
-
-
- if (coex_sta->bt_disabled != bt_disabled) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is from %s to %s!!\n",
- (coex_sta->bt_disabled ? "disabled" : "enabled"),
- (bt_disabled ? "disabled" : "enabled"));
- BTC_TRACE(trace_buf);
- coex_sta->bt_disabled = bt_disabled;
- }
-
-}
-
-void halbtc8723d2ant_enable_gnt_to_gpio(IN struct btc_coexist *btcoexist,
- boolean isenable)
-{
-
- if (isenable) {
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x1);
-
- /* enable GNT_BT to GPIO debug */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x40, 0x0);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x1, 0x0);
-
- /* 0x48[20] = 0 for GPIO14 = GNT_WL*/
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4a, 0x10, 0x0);
- /* 0x40[17] = 0 for GPIO14 = GNT_WL*/
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, 0x02, 0x0);
-
- /* 0x66[9] = 0 for GPIO15 = GNT_BT*/
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x02, 0x0);
- /* 0x66[7] = 0
- for GPIO15 = GNT_BT*/
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, 0x80, 0x0);
- /* 0x8[8] = 0 for GPIO15 = GNT_BT*/
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x9, 0x1, 0x0);
-
- /* BT Vendor Reg 0x76[0] = 0 for GPIO15 = GNT_BT, this is not set here*/
- } else {
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x0);
-
- /* Disable GNT_BT debug to GPIO, and enable chip_wakeup_host */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, 0x40, 0x1);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x1, 0x1);
-
- /* 0x48[20] = 0 for GPIO14 = GNT_WL*/
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4a, 0x10, 0x1);
- }
-
-
-}
-
-u32 halbtc8723d2ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist,
- IN u16 reg_addr)
-{
- u32 j = 0;
-
-
- /* wait for ready bit before access 0x7c0 */
- btcoexist->btc_write_4byte(btcoexist, 0x7c0, 0x800F0000 | reg_addr);
-
- do {
- j++;
- } while (((btcoexist->btc_read_1byte(btcoexist,
- 0x7c3)&BIT(5)) == 0) &&
- (j < BT_8723D_2ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT));
-
-
- return btcoexist->btc_read_4byte(btcoexist,
- 0x7c8); /* get read data */
-
-}
-
-void halbtc8723d2ant_ltecoex_indirect_write_reg(IN struct btc_coexist *btcoexist,
- IN u16 reg_addr, IN u32 bit_mask, IN u32 reg_value)
-{
- u32 val, i = 0, j = 0, bitpos = 0;
-
-
- if (bit_mask == 0x0)
- return;
- if (bit_mask == 0xffffffff) {
- btcoexist->btc_write_4byte(btcoexist, 0x7c4,
- reg_value); /* put write data */
-
- /* wait for ready bit before access 0x7c0 */
- do {
- j++;
- } while (((btcoexist->btc_read_1byte(btcoexist,
- 0x7c3)&BIT(5)) == 0) &&
- (j < BT_8723D_2ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT));
-
-
- btcoexist->btc_write_4byte(btcoexist, 0x7c0,
- 0xc00F0000 | reg_addr);
- } else {
- for (i = 0; i <= 31; i++) {
- if (((bit_mask >> i) & 0x1) == 0x1) {
- bitpos = i;
- break;
- }
- }
-
- /* read back register value before write */
- val = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist,
- reg_addr);
- val = (val & (~bit_mask)) | (reg_value << bitpos);
-
- btcoexist->btc_write_4byte(btcoexist, 0x7c4,
- val); /* put write data */
-
- /* wait for ready bit before access 0x7c0 */
- do {
- j++;
- } while (((btcoexist->btc_read_1byte(btcoexist,
- 0x7c3)&BIT(5)) == 0) &&
- (j < BT_8723D_2ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT));
-
-
- btcoexist->btc_write_4byte(btcoexist, 0x7c0,
- 0xc00F0000 | reg_addr);
-
- }
-
-}
-
-void halbtc8723d2ant_ltecoex_enable(IN struct btc_coexist *btcoexist,
- IN boolean enable)
-{
- u8 val;
-
- val = (enable) ? 1 : 0;
- halbtc8723d2ant_ltecoex_indirect_write_reg(btcoexist, 0x38, 0x80,
- val); /* 0x38[7] */
-
-}
-
-void halbtc8723d2ant_ltecoex_pathcontrol_owner(IN struct btc_coexist *btcoexist,
- IN boolean wifi_control)
-{
- u8 val;
-
- val = (wifi_control) ? 1 : 0;
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x4,
- val); /* 0x70[26] */
-
-}
-
-void halbtc8723d2ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist,
- IN u8 control_block, IN boolean sw_control, IN u8 state)
-{
- u32 val = 0, bit_mask;
-
- state = state & 0x1;
- val = (sw_control) ? ((state << 1) | 0x1) : 0;
-
- switch (control_block) {
- case BT_8723D_2ANT_GNT_BLOCK_RFC_BB:
- default:
- bit_mask = 0xc000;
- halbtc8723d2ant_ltecoex_indirect_write_reg(btcoexist,
- 0x38, bit_mask, val); /* 0x38[15:14] */
- bit_mask = 0x0c00;
- halbtc8723d2ant_ltecoex_indirect_write_reg(btcoexist,
- 0x38, bit_mask, val); /* 0x38[11:10] */
- break;
- case BT_8723D_2ANT_GNT_BLOCK_RFC:
- bit_mask = 0xc000;
- halbtc8723d2ant_ltecoex_indirect_write_reg(btcoexist,
- 0x38, bit_mask, val); /* 0x38[15:14] */
- break;
- case BT_8723D_2ANT_GNT_BLOCK_BB:
- bit_mask = 0x0c00;
- halbtc8723d2ant_ltecoex_indirect_write_reg(btcoexist,
- 0x38, bit_mask, val); /* 0x38[11:10] */
- break;
-
- }
-
-}
-
-void halbtc8723d2ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist,
- IN u8 control_block, IN boolean sw_control, IN u8 state)
-{
- u32 val = 0, bit_mask;
-
- state = state & 0x1;
- val = (sw_control) ? ((state << 1) | 0x1) : 0;
-
- switch (control_block) {
- case BT_8723D_2ANT_GNT_BLOCK_RFC_BB:
- default:
- bit_mask = 0x3000;
- halbtc8723d2ant_ltecoex_indirect_write_reg(btcoexist,
- 0x38, bit_mask, val); /* 0x38[13:12] */
- bit_mask = 0x0300;
- halbtc8723d2ant_ltecoex_indirect_write_reg(btcoexist,
- 0x38, bit_mask, val); /* 0x38[9:8] */
- break;
- case BT_8723D_2ANT_GNT_BLOCK_RFC:
- bit_mask = 0x3000;
- halbtc8723d2ant_ltecoex_indirect_write_reg(btcoexist,
- 0x38, bit_mask, val); /* 0x38[13:12] */
- break;
- case BT_8723D_2ANT_GNT_BLOCK_BB:
- bit_mask = 0x0300;
- halbtc8723d2ant_ltecoex_indirect_write_reg(btcoexist,
- 0x38, bit_mask, val); /* 0x38[9:8] */
- break;
-
- }
-
-}
-
-void halbtc8723d2ant_ltecoex_set_coex_table(IN struct btc_coexist *btcoexist,
- IN u8 table_type, IN u16 table_content)
-{
- u16 reg_addr = 0x0000;
-
- switch (table_type) {
- case BT_8723D_2ANT_CTT_WL_VS_LTE:
- reg_addr = 0xa0;
- break;
- case BT_8723D_2ANT_CTT_BT_VS_LTE:
- reg_addr = 0xa4;
- break;
- }
-
- if (reg_addr != 0x0000)
- halbtc8723d2ant_ltecoex_indirect_write_reg(btcoexist, reg_addr,
- 0xffff, table_content); /* 0xa0[15:0] or 0xa4[15:0] */
-
-
-}
-
-
-void halbtc8723d2ant_ltecoex_set_break_table(IN struct btc_coexist *btcoexist,
- IN u8 table_type, IN u8 table_content)
-{
- u16 reg_addr = 0x0000;
-
- switch (table_type) {
- case BT_8723D_2ANT_LBTT_WL_BREAK_LTE:
- reg_addr = 0xa8;
- break;
- case BT_8723D_2ANT_LBTT_BT_BREAK_LTE:
- reg_addr = 0xac;
- break;
- case BT_8723D_2ANT_LBTT_LTE_BREAK_WL:
- reg_addr = 0xb0;
- break;
- case BT_8723D_2ANT_LBTT_LTE_BREAK_BT:
- reg_addr = 0xb4;
- break;
- }
-
- if (reg_addr != 0x0000)
- halbtc8723d2ant_ltecoex_indirect_write_reg(btcoexist, reg_addr,
- 0xff, table_content); /* 0xa8[15:0] or 0xb4[15:0] */
-
-
-}
-
-
-void halbtc8723d2ant_set_coex_table(IN struct btc_coexist *btcoexist,
- IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc)
-{
- btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
-
- btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
-
- btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
-
- btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
-}
-
-void halbtc8723d2ant_coex_table(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4,
- IN u32 val0x6c8, IN u8 val0x6cc)
-{
- coex_dm->cur_val0x6c0 = val0x6c0;
- coex_dm->cur_val0x6c4 = val0x6c4;
- coex_dm->cur_val0x6c8 = val0x6c8;
- coex_dm->cur_val0x6cc = val0x6cc;
-
- if (!force_exec) {
- if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) &&
- (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) &&
- (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) &&
- (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc))
- return;
- }
- halbtc8723d2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8,
- val0x6cc);
-
- coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0;
- coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4;
- coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8;
- coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc;
-}
-
-void halbtc8723d2ant_coex_table_with_type(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 type)
-{
- u32 break_table;
- u8 select_table;
-
- coex_sta->coex_table_type = type;
-
- if (coex_sta->concurrent_rx_mode_on == true) {
- break_table = 0xf0ffffff; /* set WL hi-pri can break BT */
- select_table =
- 0xb; /* set Tx response = Hi-Pri (ex: Transmitting ACK,BA,CTS) */
- } else {
- break_table = 0xffffff;
- select_table = 0x3;
- }
-
- switch (type) {
- case 0:
- halbtc8723d2ant_coex_table(btcoexist, force_exec,
- 0xffffffff, 0xffffffff, break_table, select_table);
- break;
- case 1:
- halbtc8723d2ant_coex_table(btcoexist, force_exec,
- 0xaaaaaaaa, 0xaaaaaaaa, break_table, select_table);
- break;
- case 2:
- halbtc8723d2ant_coex_table(btcoexist, force_exec,
- 0x5a5a5a5a, 0x5a5a5a5a, break_table, select_table);
- break;
- case 3:
- halbtc8723d2ant_coex_table(btcoexist, force_exec,
- 0xdafadafa, 0xdafadafa, break_table, select_table);
- break;
- case 4:
- halbtc8723d2ant_coex_table(btcoexist, force_exec,
- 0xddffddff, 0xffbbffbb, break_table, select_table);
- break;
- case 5:
- halbtc8723d2ant_coex_table(btcoexist, force_exec,
- 0x5fff5fff, 0x5fff5fff, break_table, select_table);
- break;
- case 6:
- halbtc8723d2ant_coex_table(btcoexist, force_exec,
- 0x55ff55ff, 0x5a5a5a5a, break_table, select_table);
- break;
- case 7:
- halbtc8723d2ant_coex_table(btcoexist, force_exec,
- 0x5aff55ff, 0x5a7a5a7a, break_table, select_table);
- break;
- case 8:
- halbtc8723d2ant_coex_table(btcoexist, force_exec,
- 0x55555555, 0xaaaaaaaa, break_table, select_table);
- break;
- default:
- break;
- }
-}
-
-void halbtc8723d2ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist,
- IN boolean enable)
-{
- u8 h2c_parameter[1] = {0};
-
- if (enable)
- h2c_parameter[0] |= BIT(0); /* function enable */
-
- btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter);
-}
-
-void halbtc8723d2ant_ignore_wlan_act(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean enable)
-{
- coex_dm->cur_ignore_wlan_act = enable;
-
- if (!force_exec) {
- if (coex_dm->pre_ignore_wlan_act ==
- coex_dm->cur_ignore_wlan_act)
- return;
- }
- halbtc8723d2ant_set_fw_ignore_wlan_act(btcoexist, enable);
-
- coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
-}
-
-void halbtc8723d2ant_set_lps_rpwm(IN struct btc_coexist *btcoexist,
- IN u8 lps_val, IN u8 rpwm_val)
-{
- u8 lps = lps_val;
- u8 rpwm = rpwm_val;
-
- btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps);
- btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm);
-}
-
-void halbtc8723d2ant_lps_rpwm(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val)
-{
- coex_dm->cur_lps = lps_val;
- coex_dm->cur_rpwm = rpwm_val;
-
- if (!force_exec) {
- if ((coex_dm->pre_lps == coex_dm->cur_lps) &&
- (coex_dm->pre_rpwm == coex_dm->cur_rpwm))
- return;
- }
- halbtc8723d2ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val);
-
- coex_dm->pre_lps = coex_dm->cur_lps;
- coex_dm->pre_rpwm = coex_dm->cur_rpwm;
-}
-
-void halbtc8723d2ant_ps_tdma_check_for_power_save_state(
- IN struct btc_coexist *btcoexist, IN boolean new_ps_state)
-{
- u8 lps_mode = 0x0;
- u8 h2c_parameter[5] = {0, 0, 0, 0x40, 0};
-
- btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode);
-
- if (lps_mode) { /* already under LPS state */
- if (new_ps_state) {
- /* keep state under LPS, do nothing. */
- } else {
- /* will leave LPS state, turn off psTdma first */
- /*halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 8); */
- btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
- }
- } else { /* NO PS state */
- if (new_ps_state) {
- /* will enter LPS state, turn off psTdma first */
- /*halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
- 8);*/
- btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
- } else {
- /* keep state under NO PS state, do nothing. */
- }
- }
-}
-
-void halbtc8723d2ant_power_save_state(IN struct btc_coexist *btcoexist,
- IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val)
-{
- boolean low_pwr_disable = false;
-
- switch (ps_type) {
- case BTC_PS_WIFI_NATIVE:
- /* recover to original 32k low power setting */
- low_pwr_disable = false;
- btcoexist->btc_set(btcoexist,
- BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS,
- NULL);
- coex_sta->force_lps_on = false;
- break;
- case BTC_PS_LPS_ON:
- halbtc8723d2ant_ps_tdma_check_for_power_save_state(
- btcoexist, true);
- halbtc8723d2ant_lps_rpwm(btcoexist, NORMAL_EXEC,
- lps_val, rpwm_val);
- /* when coex force to enter LPS, do not enter 32k low power. */
- low_pwr_disable = true;
- btcoexist->btc_set(btcoexist,
- BTC_SET_ACT_DISABLE_LOW_POWER,
- &low_pwr_disable);
- /* power save must executed before psTdma. */
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS,
- NULL);
- coex_sta->force_lps_on = true;
- break;
- case BTC_PS_LPS_OFF:
- halbtc8723d2ant_ps_tdma_check_for_power_save_state(
- btcoexist, false);
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS,
- NULL);
- coex_sta->force_lps_on = false;
- break;
- default:
- break;
- }
-}
-
-
-
-void halbtc8723d2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist,
- IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5)
-{
- u8 h2c_parameter[5] = {0};
- u8 real_byte1 = byte1, real_byte5 = byte5;
- boolean ap_enable = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
- &ap_enable);
-
- if (ap_enable) {
- if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], FW for 1Ant AP mode\n");
- BTC_TRACE(trace_buf);
- real_byte1 &= ~BIT(4);
- real_byte1 |= BIT(5);
-
- real_byte5 |= BIT(5);
- real_byte5 &= ~BIT(6);
-
- halbtc8723d2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
- }
- } else if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
-
- halbtc8723d2ant_power_save_state(
- btcoexist, BTC_PS_LPS_ON, 0x50,
- 0x4);
- } else {
- halbtc8723d2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, 0x0,
- 0x0);
- }
-
-
- h2c_parameter[0] = real_byte1;
- h2c_parameter[1] = byte2;
- h2c_parameter[2] = byte3;
- h2c_parameter[3] = byte4;
- h2c_parameter[4] = real_byte5;
-
- coex_dm->ps_tdma_para[0] = real_byte1;
- coex_dm->ps_tdma_para[1] = byte2;
- coex_dm->ps_tdma_para[2] = byte3;
- coex_dm->ps_tdma_para[3] = byte4;
- coex_dm->ps_tdma_para[4] = real_byte5;
-
- btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
-}
-
-void halbtc8723d2ant_ps_tdma(IN struct btc_coexist *btcoexist,
- IN boolean force_exec, IN boolean turn_on, IN u8 type)
-{
-
- static u8 psTdmaByte4Modify = 0x0, pre_psTdmaByte4Modify = 0x0;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
-
- coex_dm->cur_ps_tdma_on = turn_on;
- coex_dm->cur_ps_tdma = type;
-
- /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */
- if ((bt_link_info->slave_role) && (bt_link_info->a2dp_exist))
- psTdmaByte4Modify = 0x1;
- else
- psTdmaByte4Modify = 0x0;
-
- if (pre_psTdmaByte4Modify != psTdmaByte4Modify) {
-
- force_exec = true;
- pre_psTdmaByte4Modify = psTdmaByte4Modify;
- }
-
- if (!force_exec) {
- if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) &&
- (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma))
- return;
- }
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], %s turn %s PS TDMA, type=%d\n",
- (force_exec ? "force to" : ""), (turn_on ? "ON" : "OFF"), type);
- BTC_TRACE(trace_buf);
-
-
- if (turn_on) {
-
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8,
- 0x1); /* enable TBTT nterrupt */
- }
-
-
- if (turn_on) {
- switch (type) {
- case 1:
- default:
- halbtc8723d2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x10, 0x03, 0xf1,
- 0x14 | psTdmaByte4Modify);
- break;
- case 2:
- halbtc8723d2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x35, 0x03, 0x71,
- 0x11 | psTdmaByte4Modify);
- break;
- case 3:
- halbtc8723d2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x3a, 0x3, 0xf1,
- 0x10 | psTdmaByte4Modify);
- break;
- case 4:
- halbtc8723d2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x21, 0x3, 0xf1,
- 0x10 | psTdmaByte4Modify);
- break;
- case 5:
- halbtc8723d2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x30, 0x3, 0xf1,
- 0x10 | psTdmaByte4Modify);
- break;
- case 6:
- halbtc8723d2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x1c, 0x3, 0xf1,
- 0x10 | psTdmaByte4Modify);
- break;
- case 7:
- halbtc8723d2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x25, 0x3, 0xf1,
- 0x10 | psTdmaByte4Modify);
- break;
- case 11:
- halbtc8723d2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x30, 0x03, 0x71,
- 0x10 | psTdmaByte4Modify);
- break;
- case 12:
- halbtc8723d2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x21, 0x03, 0x71,
- 0x11 | psTdmaByte4Modify);
- break;
- case 13:
- halbtc8723d2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x1c, 0x03, 0x71,
- 0x10 | psTdmaByte4Modify);
- break;
- case 101:
- halbtc8723d2ant_set_fw_pstdma(btcoexist, 0xd3,
- 0x10, 0x03, 0x70,
- 0x14 | psTdmaByte4Modify);
- break;
- case 102:
- halbtc8723d2ant_set_fw_pstdma(btcoexist, 0xe3,
- 0x35, 0x03, 0x71,
- 0x11 | psTdmaByte4Modify);
- break;
- case 103:
- halbtc8723d2ant_set_fw_pstdma(btcoexist, 0xd3,
- 0x3a, 0x3, 0x70,
- 0x10 | psTdmaByte4Modify);
- break;
- case 104:
- halbtc8723d2ant_set_fw_pstdma(btcoexist, 0xd3,
- 0x21, 0x3, 0x70,
- 0x10 | psTdmaByte4Modify);
- break;
- case 105:
- halbtc8723d2ant_set_fw_pstdma(btcoexist, 0xd3,
- 0x30, 0x3, 0x70,
- 0x10 | psTdmaByte4Modify);
- break;
- case 106:
- halbtc8723d2ant_set_fw_pstdma(btcoexist, 0xd3,
- 0x1c, 0x3, 0x70,
- 0x10 | psTdmaByte4Modify);
- break;
- case 107:
- halbtc8723d2ant_set_fw_pstdma(btcoexist, 0xd3,
- 0x25, 0x3, 0x70,
- 0x10 | psTdmaByte4Modify);
- break;
-
-
- }
- } else {
- /* disable PS tdma */
- switch (type) {
- case 0:
- halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x0,
- 0x0, 0x0, 0x40, 0x0);
- break;
- case 1:
- halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x0,
- 0x0, 0x0, 0x48, 0x0);
- break;
- default:
- halbtc8723d2ant_set_fw_pstdma(btcoexist, 0x0,
- 0x0, 0x0, 0x40, 0x0);
- break;
- }
- }
-
- /* update pre state */
- coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on;
- coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
-}
-
-void halbtc8723d2ant_set_ant_path(IN struct btc_coexist *btcoexist,
- IN u8 ant_pos_type, IN boolean init_hwcfg, IN boolean wifi_off)
-{
- struct btc_board_info *board_info = &btcoexist->board_info;
- u32 u32tmp = 0;
- boolean pg_ext_switch = false;
- u8 h2c_parameter[2] = {0}, u8tmp0 = 0;
- boolean is_in_mp_mode = false;
- u32 u32tmp0 = 0, u32tmp1 = 0, u32tmp2 = 0;
- u16 u16tmp0 = 0;
-
-
- if (init_hwcfg) {
-
- /* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */
- halbtc8723d2ant_ltecoex_enable(btcoexist, 0x0);
-
- /* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */
- halbtc8723d2ant_ltecoex_set_coex_table(btcoexist,
- BT_8723D_1ANT_CTT_WL_VS_LTE, 0xffff);
-
- /* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */
- halbtc8723d2ant_ltecoex_set_coex_table(btcoexist,
- BT_8723D_1ANT_CTT_BT_VS_LTE, 0xffff);
-
- /* Set Path control to WL */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x80, 0x1);
-
- /* set Path control owner to WL at initial step */
- halbtc8723d2ant_ltecoex_pathcontrol_owner(btcoexist,
- BT_8723D_1ANT_PCO_WLSIDE);
-
- /* set GNT_BT to high */
- halbtc8723d2ant_ltecoex_set_gnt_bt(btcoexist,
- BT_8723D_2ANT_GNT_BLOCK_RFC_BB,
- BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW,
- BT_8723D_2ANT_SIG_STA_SET_TO_HIGH);
- /* Set GNT_WL to high */
- halbtc8723d2ant_ltecoex_set_gnt_wl(btcoexist,
- BT_8723D_2ANT_GNT_BLOCK_RFC_BB,
- BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW,
- BT_8723D_2ANT_SIG_STA_SET_TO_HIGH);
-
- /* Send antenna info (inverse, non-inverse, Int/Ext) to Firmware */
- if (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT) {
- /* tell firmware "no antenna inverse" */
- h2c_parameter[0] = 0;
- } else {
- /* tell firmware "antenna inverse" */
- h2c_parameter[0] = 1;
- }
-
- /* int switch type */
- h2c_parameter[1] = 0;
- btcoexist->btc_fill_h2c(btcoexist, 0x65, 2, h2c_parameter);
-
- coex_sta->gnt_control_by_PTA = false;
- } else if (wifi_off) {
- /* Disable LTE Coex Function in WiFi side */
- halbtc8723d2ant_ltecoex_enable(btcoexist, 0x0);
-
- /* Set Path control to BT */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x80, 0x0);
-
- halbtc8723d2ant_ltecoex_pathcontrol_owner(btcoexist,
- BT_8723D_1ANT_PCO_BTSIDE);/* set Path control owner to BT */
-
- coex_sta->gnt_control_by_PTA = false;
- } else {
-
- /* set GNT_BT to PTA */
- halbtc8723d2ant_ltecoex_set_gnt_bt(btcoexist,
- BT_8723D_2ANT_GNT_BLOCK_RFC_BB,
- BT_8723D_2ANT_GNT_TYPE_CTRL_BY_PTA,
- BT_8723D_2ANT_SIG_STA_SET_BY_HW);
- /* Set GNT_WL to PTA */
- halbtc8723d2ant_ltecoex_set_gnt_wl(btcoexist,
- BT_8723D_2ANT_GNT_BLOCK_RFC_BB,
- BT_8723D_2ANT_GNT_TYPE_CTRL_BY_PTA,
- BT_8723D_2ANT_SIG_STA_SET_BY_HW);
-
- coex_sta->gnt_control_by_PTA = true;
- }
-
- switch (ant_pos_type) {
- case BTC_ANT_WIFI_AT_MAIN:
- u16tmp0 = btcoexist->btc_read_2byte(btcoexist, 0x948);
- if ((u16tmp0 == 0x140) || (u16tmp0 == 0x40))
- btcoexist->btc_write_2byte(btcoexist, 0x948, u16tmp0);
- else
- btcoexist->btc_write_2byte(btcoexist, 0x948, 0x0);
- break;
- case BTC_ANT_WIFI_AT_AUX:
- u16tmp0 = btcoexist->btc_read_2byte(btcoexist, 0x948);
- if ((u16tmp0 == 0x140) || (u16tmp0 == 0x40))
- btcoexist->btc_write_2byte(btcoexist, 0x948, u16tmp0);
- else
- btcoexist->btc_write_2byte(btcoexist, 0x948, 0x280);
- break;
- }
-
-
- u8tmp0 = btcoexist->btc_read_1byte(btcoexist, 0x67);
- u16tmp0 = btcoexist->btc_read_2byte(btcoexist, 0x948);
- u32tmp0 = btcoexist->btc_read_4byte(btcoexist, 0x70);
- u32tmp1 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
- u32tmp2 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** 0x67 = 0x%x, 0x948 = 0x%x, 0x70 = 0x%x, 0x38= 0x%x, 0x54= 0x%x (After Set Ant Path) **********\n",
- u8tmp0, u16tmp0, u32tmp0, u32tmp1, u32tmp2);
- BTC_TRACE(trace_buf);
-
-}
-
-u8 halbtc8723d2ant_action_algorithm(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean bt_hs_on = false;
- u8 algorithm = BT_8723D_2ANT_COEX_ALGO_UNDEFINED;
- u8 num_of_diff_profile = 0;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
-
- if (!bt_link_info->bt_link_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], No BT link exists!!!\n");
- BTC_TRACE(trace_buf);
- return algorithm;
- }
-
- if (bt_link_info->sco_exist)
- num_of_diff_profile++;
- if (bt_link_info->hid_exist)
- num_of_diff_profile++;
- if (bt_link_info->pan_exist)
- num_of_diff_profile++;
- if (bt_link_info->a2dp_exist)
- num_of_diff_profile++;
-
- if (num_of_diff_profile == 0) {
-
- if (bt_link_info->acl_busy) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], No-Profile busy\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8723D_2ANT_COEX_ALGO_NOPROFILEBUSY;
- }
- } else if (num_of_diff_profile == 1) {
- if (bt_link_info->sco_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO only\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8723D_2ANT_COEX_ALGO_SCO;
- } else {
- if (bt_link_info->hid_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], HID only\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8723D_2ANT_COEX_ALGO_HID;
- } else if (bt_link_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], A2DP only\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8723D_2ANT_COEX_ALGO_A2DP;
- } else if (bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], PAN(HS) only\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723D_2ANT_COEX_ALGO_PANHS;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], PAN(EDR) only\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723D_2ANT_COEX_ALGO_PANEDR;
- }
- }
- }
- } else if (num_of_diff_profile == 2) {
- if (bt_link_info->sco_exist) {
- if (bt_link_info->hid_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + HID\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8723D_2ANT_COEX_ALGO_SCO;
- } else if (bt_link_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + A2DP ==> A2DP\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8723D_2ANT_COEX_ALGO_A2DP;
- } else if (bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8723D_2ANT_COEX_ALGO_SCO;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8723D_2ANT_COEX_ALGO_PANEDR;
- }
- }
- } else {
- if (bt_link_info->hid_exist &&
- bt_link_info->a2dp_exist) {
- {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], HID + A2DP\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723D_2ANT_COEX_ALGO_HID_A2DP;
- }
- } else if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], HID + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8723D_2ANT_COEX_ALGO_HID;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], HID + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723D_2ANT_COEX_ALGO_PANEDR_HID;
- }
- } else if (bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723D_2ANT_COEX_ALGO_A2DP_PANHS;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], A2DP + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723D_2ANT_COEX_ALGO_PANEDR_A2DP;
- }
- }
- }
- } else if (num_of_diff_profile == 3) {
- if (bt_link_info->sco_exist) {
- if (bt_link_info->hid_exist &&
- bt_link_info->a2dp_exist) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + HID + A2DP ==> HID + A2DP\n");
- BTC_TRACE(trace_buf);
- algorithm = BT_8723D_2ANT_COEX_ALGO_HID_A2DP;
- } else if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + HID + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723D_2ANT_COEX_ALGO_PANEDR_HID;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + HID + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723D_2ANT_COEX_ALGO_PANEDR_HID;
- }
- } else if (bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723D_2ANT_COEX_ALGO_PANEDR_A2DP;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723D_2ANT_COEX_ALGO_PANEDR_A2DP;
- }
- }
- } else {
- if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], HID + A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723D_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], HID + A2DP + PAN(EDR)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723D_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
- }
- }
- }
- } else if (num_of_diff_profile >= 3) {
- if (bt_link_info->sco_exist) {
- if (bt_link_info->hid_exist &&
- bt_link_info->pan_exist &&
- bt_link_info->a2dp_exist) {
- if (bt_hs_on) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723D_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n");
- BTC_TRACE(trace_buf);
- algorithm =
- BT_8723D_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
- }
- }
- }
- }
-
- return algorithm;
-}
-
-
-
-void halbtc8723d2ant_action_coex_all_off(IN struct btc_coexist *btcoexist)
-{
-
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- /* fw all off */
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
-
- halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
- halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- /* sw all off */
- halbtc8723d2ant_sw_mechanism1(btcoexist, false, false, false, false);
- halbtc8723d2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
-
-}
-
-void halbtc8723d2ant_action_init_coex_dm(IN struct btc_coexist *btcoexist)
-{
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- /* fw all off */
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
-
- halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
- halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- /* sw all off */
- halbtc8723d2ant_sw_mechanism1(btcoexist, false, false, false, false);
- halbtc8723d2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
-
- coex_sta->pop_event_cnt = 0;
-}
-
-void halbtc8723d2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist)
-{
-
- boolean wifi_connected = false;
- boolean scan = false, link = false, roam = false;
- boolean wifi_busy = false;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
-
- if (link || roam || coex_sta->wifi_is_high_pri_task) {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi link/roam/hi-pri-task process + BT Inq/Page!!\n");
- BTC_TRACE(trace_buf);
-
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 8);
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 11);
-
- } else if (scan) {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi scan process + BT Inq/Page!!\n");
- BTC_TRACE(trace_buf);
-
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 8);
-
- if (coex_sta->bt_create_connection)
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 12);
- else
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 11);
-
- } else if (wifi_connected) {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi connected + BT Inq/Page!!\n");
- BTC_TRACE(trace_buf);
-
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 7);
-
- if (wifi_busy) {
-
- if ((bt_link_info->a2dp_exist) && (bt_link_info->acl_busy))
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13);
- else
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 11);
-
- } else
-
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13);
- } else {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi no-link + BT Inq/Page!!\n");
- BTC_TRACE(trace_buf);
-
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- }
-
- halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0x18);
- halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8723d2ant_sw_mechanism1(btcoexist, false, false, false, false);
- halbtc8723d2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
-
-}
-
-void halbtc8723d2ant_action_wifi_link_process(IN struct btc_coexist *btcoexist)
-{
- u32 u32tmp, u32tmpb;
- u8 u8tmpa;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
- halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0x18);
- halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
-
- if ((bt_link_info->a2dp_exist) && (bt_link_info->acl_busy))
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13);
- else
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 11);
-
- halbtc8723d2ant_sw_mechanism1(btcoexist, false, false, false, false);
- halbtc8723d2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
-
-}
-
-
-void halbtc8723d2ant_action_wifi_nonconnected(IN struct btc_coexist *btcoexist)
-{
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- /* fw all off */
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
-
- halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
- halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- /* sw all off */
- halbtc8723d2ant_sw_mechanism1(btcoexist, false, false, false, false);
- halbtc8723d2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
-}
-
-void halbtc8723d2ant_action_bt_idle(IN struct btc_coexist *btcoexist)
-{
- static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state, bt_rssi_state;
-
- static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state2, bt_rssi_state2;
-
- boolean wifi_connected = false;
- boolean scan = false, link = false, roam = false;
- boolean wifi_busy = false;
-
- wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state, 2,
- coex_sta->wifi_coex_thres , 0);
-
- wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state2, 2,
- coex_sta->wifi_coex_thres2 , 0);
-
- bt_rssi_state = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
- coex_sta->bt_coex_thres , 0);
-
- bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
- coex_sta->bt_coex_thres2 , 0);
-
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
-
- if (scan || link || roam) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi link process + BT Idle!!\n");
- BTC_TRACE(trace_buf);
-
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 7);
-
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 11);
- } else if (wifi_connected) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi connected + BT Idle!!\n");
- BTC_TRACE(trace_buf);
-
- if (wifi_busy) {
- if (!BTC_RSSI_HIGH(bt_rssi_state2))
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 2);
- else
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 0);
- } else {
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 0);
- }
-
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
-
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Wifi no-link + BT Idle!!\n");
- BTC_TRACE(trace_buf);
-
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC,
- 0);
-
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- }
-
- halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0x18);
- halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8723d2ant_sw_mechanism1(btcoexist, false, false, false, false);
- halbtc8723d2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
-
-}
-
-
-/* SCO only or SCO+PAN(HS) */
-void halbtc8723d2ant_action_sco(IN struct btc_coexist *btcoexist)
-{
- static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state, bt_rssi_state;
-
- static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state2, bt_rssi_state2;
- boolean wifi_busy = false;
-
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state, 2,
- coex_sta->wifi_coex_thres , 0);
-
- wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state2, 2,
- coex_sta->wifi_coex_thres2 , 0);
-
- bt_rssi_state = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
- coex_sta->bt_coex_thres , 0);
-
- bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
- coex_sta->bt_coex_thres2 , 0);
-
-
- if (BTC_RSSI_HIGH(wifi_rssi_state) &&
- BTC_RSSI_HIGH(bt_rssi_state)) {
-
- halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
- halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- } else {
-
- halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
- halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
-
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- }
-
-
- /* sw mechanism */
- halbtc8723d2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8723d2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
-
-}
-
-
-void halbtc8723d2ant_action_hid(IN struct btc_coexist *btcoexist)
-{
- static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state, bt_rssi_state;
-
- static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state2, bt_rssi_state2;
- boolean wifi_busy = false;
-
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state, 2,
- coex_sta->wifi_coex_thres , 0);
-
- wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state2, 2,
- coex_sta->wifi_coex_thres2 , 0);
-
- bt_rssi_state = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
- coex_sta->bt_coex_thres , 0);
-
- bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
- coex_sta->bt_coex_thres2 , 0);
-
-
- if (BTC_RSSI_HIGH(wifi_rssi_state) &&
- BTC_RSSI_HIGH(bt_rssi_state)) {
-
- halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
- halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- } else {
-
- halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
- halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
-
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- }
-
-
- /* sw mechanism */
- halbtc8723d2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8723d2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
-
-}
-
-/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */
-void halbtc8723d2ant_action_a2dp(IN struct btc_coexist *btcoexist)
-{
- static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state, bt_rssi_state;
-
- static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state2, bt_rssi_state2;
- boolean wifi_busy = false;
-
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state, 2,
- coex_sta->wifi_coex_thres , 0);
-
- wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state2, 2,
- coex_sta->wifi_coex_thres2 , 0);
-
- bt_rssi_state = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
- coex_sta->bt_coex_thres , 0);
-
- bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
- coex_sta->bt_coex_thres2 , 0);
-
-
- if (BTC_RSSI_HIGH(wifi_rssi_state) &&
- BTC_RSSI_HIGH(bt_rssi_state)) {
-
- halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
- halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- } else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
- BTC_RSSI_HIGH(bt_rssi_state2)) {
-
- halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
- halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
-
- if (wifi_busy)
-
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 1);
- else
-
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 2);
- } else {
-
- halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
- halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- coex_dm->is_switch_to_1dot5_ant = true;
-
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
-
- if (wifi_busy)
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 101);
- else
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 102);
-
- }
-
- /* sw mechanism */
- halbtc8723d2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8723d2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
-
-}
-
-void halbtc8723d2ant_action_pan_edr(IN struct btc_coexist *btcoexist)
-{
- static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state, bt_rssi_state;
-
- static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state2, bt_rssi_state2;
- boolean wifi_busy = false;
-
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state, 2,
- coex_sta->wifi_coex_thres , 0);
-
- wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state2, 2,
- coex_sta->wifi_coex_thres2 , 0);
-
- bt_rssi_state = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
- coex_sta->bt_coex_thres , 0);
-
- bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
- coex_sta->bt_coex_thres2 , 0);
-
-#if 0
- halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
- halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
-#endif
-
-
-#if 1
- if (BTC_RSSI_HIGH(wifi_rssi_state) &&
- BTC_RSSI_HIGH(bt_rssi_state)) {
-
- halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
- halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- } else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
- BTC_RSSI_HIGH(bt_rssi_state2)) {
-
- halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
- halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
-
- if (wifi_busy)
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3);
- else
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 4);
- } else {
-
- halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
- halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- coex_dm->is_switch_to_1dot5_ant = true;
-
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
-
- if (wifi_busy)
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 103);
- else
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 104);
-
- }
-
-#endif
-
-
- /* sw mechanism */
- halbtc8723d2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8723d2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
-
-}
-
-
-/* PAN(HS) only */
-void halbtc8723d2ant_action_pan_hs(IN struct btc_coexist *btcoexist)
-{
- static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state, bt_rssi_state;
-
- static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state2, bt_rssi_state2;
- boolean wifi_busy = false;
-
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state, 2,
- coex_sta->wifi_coex_thres , 0);
-
- wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state2, 2,
- coex_sta->wifi_coex_thres2 , 0);
-
- bt_rssi_state = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
- coex_sta->bt_coex_thres , 0);
-
- bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
- coex_sta->bt_coex_thres2 , 0);
-
- if (BTC_RSSI_HIGH(wifi_rssi_state) &&
- BTC_RSSI_HIGH(bt_rssi_state)) {
-
- halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
- halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- } else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
- BTC_RSSI_HIGH(bt_rssi_state2)) {
-
- halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
- halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
-
-
- } else {
-
- halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
- halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- coex_dm->is_switch_to_1dot5_ant = true;
-
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- }
-
-
- /* sw mechanism */
- halbtc8723d2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8723d2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
-}
-
-
-void halbtc8723d2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist)
-{
- static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state, bt_rssi_state;
-
- static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state2, bt_rssi_state2;
- boolean wifi_busy = false;
-
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state, 2,
- coex_sta->wifi_coex_thres , 0);
-
- wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state2, 2,
- coex_sta->wifi_coex_thres2 , 0);
-
- bt_rssi_state = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
- coex_sta->bt_coex_thres , 0);
-
- bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
- coex_sta->bt_coex_thres2 , 0);
-
-
- if (BTC_RSSI_HIGH(wifi_rssi_state) &&
- BTC_RSSI_HIGH(bt_rssi_state)) {
-
- halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
- halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- } else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
- BTC_RSSI_HIGH(bt_rssi_state2)) {
-
- halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
- halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
-
- if (wifi_busy)
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 1);
- else
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 2);
-
-
- } else {
-
- halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
- halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- coex_dm->is_switch_to_1dot5_ant = true;
-
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
-
- if (wifi_busy)
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 101);
- else
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 102);
-
- }
-
-
- /* sw mechanism */
- halbtc8723d2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8723d2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
-
-}
-
-
-void halbtc8723d2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist)
-{
- static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state, bt_rssi_state;
-
- static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state2, bt_rssi_state2;
- boolean wifi_busy = false;
-
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state, 2,
- coex_sta->wifi_coex_thres , 0);
-
- wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state2, 2,
- coex_sta->wifi_coex_thres2 , 0);
-
- bt_rssi_state = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
- coex_sta->bt_coex_thres , 0);
-
- bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
- coex_sta->bt_coex_thres2 , 0);
-
-
- if (BTC_RSSI_HIGH(wifi_rssi_state) &&
- BTC_RSSI_HIGH(bt_rssi_state)) {
-
- halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
- halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- } else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
- BTC_RSSI_HIGH(bt_rssi_state2)) {
-
- halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
- halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
-
- if (wifi_busy) {
-
- if ((coex_sta->a2dp_bit_pool > 40) && (coex_sta->a2dp_bit_pool < 255))
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 7);
- else
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
- } else
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 6);
-
- } else {
-
- halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
- halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- coex_dm->is_switch_to_1dot5_ant = true;
-
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
-
- if (wifi_busy) {
-
- if ((coex_sta->a2dp_bit_pool > 40) && (coex_sta->a2dp_bit_pool < 255))
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 107);
- else
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 105);
- } else
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 106);
-
- }
-
-
- /* sw mechanism */
- halbtc8723d2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8723d2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
-
-}
-
-
-
-/* PAN(EDR)+A2DP */
-void halbtc8723d2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist)
-{
- static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state, bt_rssi_state;
-
- static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state2, bt_rssi_state2;
- boolean wifi_busy = false;
-
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state, 2,
- coex_sta->wifi_coex_thres , 0);
-
- wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state2, 2,
- coex_sta->wifi_coex_thres2 , 0);
-
- bt_rssi_state = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
- coex_sta->bt_coex_thres , 0);
-
- bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
- coex_sta->bt_coex_thres2 , 0);
-
- if (BTC_RSSI_HIGH(wifi_rssi_state) &&
- BTC_RSSI_HIGH(bt_rssi_state)) {
-
- halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
- halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- } else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
- BTC_RSSI_HIGH(bt_rssi_state2)) {
-
- halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
- halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
-
- if (wifi_busy) {
-
- if ((coex_sta->a2dp_bit_pool > 40) && (coex_sta->a2dp_bit_pool < 255))
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 7);
- else
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
- } else
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 6);
- } else {
-
- halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
- halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- coex_dm->is_switch_to_1dot5_ant = true;
-
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
-
- if (wifi_busy) {
-
- if ((coex_sta->a2dp_bit_pool > 40) && (coex_sta->a2dp_bit_pool < 255))
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 107);
- else
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 105);
- } else
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 106);
-
- }
-
-
- /* sw mechanism */
- halbtc8723d2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8723d2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
-
-}
-
-void halbtc8723d2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist)
-{
- static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state, bt_rssi_state;
-
- static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state2, bt_rssi_state2;
- boolean wifi_busy = false;
-
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state, 2,
- coex_sta->wifi_coex_thres , 0);
-
- wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state2, 2,
- coex_sta->wifi_coex_thres2 , 0);
-
- bt_rssi_state = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
- coex_sta->bt_coex_thres , 0);
-
- bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
- coex_sta->bt_coex_thres2 , 0);
-
-
- if (BTC_RSSI_HIGH(wifi_rssi_state) &&
- BTC_RSSI_HIGH(bt_rssi_state)) {
-
- halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
- halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- } else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
- BTC_RSSI_HIGH(bt_rssi_state2)) {
-
- halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
- halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
-
- if (wifi_busy)
-
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3);
- else
-
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 4);
-
-
- } else {
-
- halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
- halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- coex_dm->is_switch_to_1dot5_ant = true;
-
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
-
- if (wifi_busy)
-
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 103);
- else
-
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 104);
-
- }
-
-
- /* sw mechanism */
- halbtc8723d2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8723d2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
-
-}
-
-/* HID+A2DP+PAN(EDR) */
-void halbtc8723d2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist)
-{
- static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state, bt_rssi_state;
-
- static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
- static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
- u8 wifi_rssi_state2, bt_rssi_state2;
- boolean wifi_busy = false;
-
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
-
- wifi_rssi_state = halbtc8723d2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state, 2,
- coex_sta->wifi_coex_thres , 0);
-
- wifi_rssi_state2 = halbtc8723d2ant_wifi_rssi_state(btcoexist,
- &prewifi_rssi_state2, 2,
- coex_sta->wifi_coex_thres2 , 0);
-
- bt_rssi_state = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state, 2,
- coex_sta->bt_coex_thres , 0);
-
- bt_rssi_state2 = halbtc8723d2ant_bt_rssi_state(&pre_bt_rssi_state2, 2,
- coex_sta->bt_coex_thres2 , 0);
-
-
- if (BTC_RSSI_HIGH(wifi_rssi_state) &&
- BTC_RSSI_HIGH(bt_rssi_state)) {
-
- halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
- halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
- } else if (BTC_RSSI_HIGH(wifi_rssi_state2) &&
- BTC_RSSI_HIGH(bt_rssi_state2)) {
-
- halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
- halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
-
- coex_dm->is_switch_to_1dot5_ant = false;
-
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
-
- if (wifi_busy) {
-
- if ((coex_sta->a2dp_bit_pool > 40) && (coex_sta->a2dp_bit_pool < 255))
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 7);
- else
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
- } else
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 6);
- } else {
-
- halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
- halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- coex_dm->is_switch_to_1dot5_ant = true;
-
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
-
- if (wifi_busy) {
-
- if ((coex_sta->a2dp_bit_pool > 40) && (coex_sta->a2dp_bit_pool < 255))
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 107);
- else
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 105);
- } else
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 106);
- }
-
- /* sw mechanism */
- halbtc8723d2ant_sw_mechanism1(btcoexist, false, true,
- false, false);
- halbtc8723d2ant_sw_mechanism2(btcoexist, false, false,
- false, 0x18);
-
-}
-
-
-
-void halbtc8723d2ant_action_bt_whck_test(IN struct btc_coexist *btcoexist)
-{
- halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
- halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- /* sw mechanism all off */
- halbtc8723d2ant_sw_mechanism1(btcoexist, false, false, false, false);
- halbtc8723d2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
-
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
-}
-
-void halbtc8723d2ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist)
-{
- halbtc8723d2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0x18);
- halbtc8723d2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
-
- /* sw mechanism all off */
- halbtc8723d2ant_sw_mechanism1(btcoexist, false, false, false, false);
- halbtc8723d2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
-
- /* hw all off */
- halbtc8723d2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
-
- halbtc8723d2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
-}
-
-void halbtc8723d2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist)
-{
- u8 algorithm = 0;
- u32 num_of_wifi_link = 0;
- u32 wifi_link_status = 0;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- boolean miracast_plus_bt = false;
- boolean scan = false, link = false, roam = false, wifi_connected = false;
-
-
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism()===>\n");
- BTC_TRACE(trace_buf);
-
- if (btcoexist->manual_control) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- if (btcoexist->stop_coex_dm) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- if (coex_sta->under_ips) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], wifi is under IPS !!!\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- if (coex_sta->bt_whck_test) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is under WHCK TEST!!!\n");
- BTC_TRACE(trace_buf);
- halbtc8723d2ant_action_bt_whck_test(btcoexist);
- return;
- }
-
- if (coex_sta->bt_disabled) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is disabled!!!\n");
- BTC_TRACE(trace_buf);
- halbtc8723d2ant_action_coex_all_off(btcoexist);
- return;
- }
-
- if (coex_sta->c2h_bt_inquiry_page) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT is under inquiry/page scan !!\n");
- BTC_TRACE(trace_buf);
- halbtc8723d2ant_action_bt_inquiry(btcoexist);
- return;
- }
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
-
- if (scan || link || roam) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], WiFi is under Link Process !!\n");
- BTC_TRACE(trace_buf);
- halbtc8723d2ant_action_wifi_link_process(btcoexist);
- return;
- }
-
- /* for P2P */
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
- &wifi_link_status);
- num_of_wifi_link = wifi_link_status >> 16;
-
- if ((num_of_wifi_link >= 2) ||
- (wifi_link_status & WIFI_P2P_GO_CONNECTED)) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n",
- num_of_wifi_link, wifi_link_status);
- BTC_TRACE(trace_buf);
-
- if (bt_link_info->bt_link_exist)
- miracast_plus_bt = true;
- else
- miracast_plus_bt = false;
-
- btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
- &miracast_plus_bt);
- halbtc8723d2ant_action_wifi_multi_port(btcoexist);
-
- return;
- } else {
- miracast_plus_bt = false;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
- &miracast_plus_bt);
- }
-
-
- algorithm = halbtc8723d2ant_action_algorithm(btcoexist);
- coex_dm->cur_algorithm = algorithm;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Algorithm = %d\n",
- coex_dm->cur_algorithm);
- BTC_TRACE(trace_buf);
-
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
-
- if (!wifi_connected) {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, wifi non-connected!!.\n");
- BTC_TRACE(trace_buf);
- halbtc8723d2ant_action_wifi_nonconnected(btcoexist);
-
- } else if ((BT_8723D_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
- coex_dm->bt_status) || (BT_8723D_2ANT_BT_STATUS_CONNECTED_IDLE ==
- coex_dm->bt_status)) {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, bt idle!!.\n");
- BTC_TRACE(trace_buf);
-
- halbtc8723d2ant_action_bt_idle(btcoexist);
-
- } else {
-
- if (coex_dm->cur_algorithm != coex_dm->pre_algorithm) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], pre_algorithm=%d, cur_algorithm=%d\n",
- coex_dm->pre_algorithm, coex_dm->cur_algorithm);
- BTC_TRACE(trace_buf);
- }
-
- switch (coex_dm->cur_algorithm) {
-
- case BT_8723D_2ANT_COEX_ALGO_SCO:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = SCO.\n");
- BTC_TRACE(trace_buf);
- halbtc8723d2ant_action_sco(btcoexist);
- break;
- case BT_8723D_2ANT_COEX_ALGO_HID:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = HID.\n");
- BTC_TRACE(trace_buf);
- halbtc8723d2ant_action_hid(btcoexist);
- break;
- case BT_8723D_2ANT_COEX_ALGO_A2DP:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = A2DP.\n");
- BTC_TRACE(trace_buf);
- halbtc8723d2ant_action_a2dp(btcoexist);
- break;
- case BT_8723D_2ANT_COEX_ALGO_A2DP_PANHS:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n");
- BTC_TRACE(trace_buf);
- halbtc8723d2ant_action_a2dp_pan_hs(btcoexist);
- break;
- case BT_8723D_2ANT_COEX_ALGO_PANEDR:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n");
- BTC_TRACE(trace_buf);
- halbtc8723d2ant_action_pan_edr(btcoexist);
- break;
- case BT_8723D_2ANT_COEX_ALGO_PANHS:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = HS mode.\n");
- BTC_TRACE(trace_buf);
- halbtc8723d2ant_action_pan_hs(btcoexist);
- break;
- case BT_8723D_2ANT_COEX_ALGO_PANEDR_A2DP:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n");
- BTC_TRACE(trace_buf);
- halbtc8723d2ant_action_pan_edr_a2dp(btcoexist);
- break;
- case BT_8723D_2ANT_COEX_ALGO_PANEDR_HID:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n");
- BTC_TRACE(trace_buf);
- halbtc8723d2ant_action_pan_edr_hid(btcoexist);
- break;
- case BT_8723D_2ANT_COEX_ALGO_HID_A2DP_PANEDR:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n");
- BTC_TRACE(trace_buf);
- halbtc8723d2ant_action_hid_a2dp_pan_edr(
- btcoexist);
- break;
- case BT_8723D_2ANT_COEX_ALGO_HID_A2DP:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n");
- BTC_TRACE(trace_buf);
- halbtc8723d2ant_action_hid_a2dp(btcoexist);
- break;
- case BT_8723D_2ANT_COEX_ALGO_NOPROFILEBUSY:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = No-Profile busy.\n");
- BTC_TRACE(trace_buf);
- halbtc8723d2ant_action_bt_idle(btcoexist);
- break;
- default:
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n");
- BTC_TRACE(trace_buf);
- halbtc8723d2ant_action_coex_all_off(btcoexist);
- break;
- }
- coex_dm->pre_algorithm = coex_dm->cur_algorithm;
- }
-}
-
-void halbtc8723d2ant_init_hw_config(IN struct btc_coexist *btcoexist,
- IN boolean wifi_only)
-{
- u8 u8tmp = 0;
- u32 vendor;
- u32 u32tmp0 = 0, u32tmp1 = 0, u32tmp2 = 0;
-
-
- u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x67);
- u32tmp0 = btcoexist->btc_read_4byte(btcoexist, 0x70);
- u32tmp1 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
- u32tmp2 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** 0x67 = 0x%x, 0x70 = 0x%x, 0x38= 0x%x, 0x54= 0x%x (Before Init HW config) **********\n",
- u8tmp, u32tmp0, u32tmp1, u32tmp2);
- BTC_TRACE(trace_buf);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], 2Ant Init HW Config!!\n");
- BTC_TRACE(trace_buf);
-
-#if 0
- btcoexist->btc_get(btcoexist, BTC_GET_U4_VENDOR, &vendor);
- if (vendor == BTC_VENDOR_LENOVO)
- coex_dm->switch_thres_offset = 0;
- else
- coex_dm->switch_thres_offset = 20;
-#endif
- /* 0xf0[15:12] --> Chip Cut information */
- coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist,
- 0xf1) & 0xf0) >> 4;
-
- coex_sta->dis_ver_info_cnt = 0;
-
- /* default isolation = 15dB */
- coex_sta->isolation_btween_wb = BT_8723D_2ANT_DEFAULT_ISOLATION;
- halbtc8723d2ant_coex_switch_threshold(btcoexist, coex_sta->isolation_btween_wb);
-
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8,
- 0x1); /* enable TBTT nterrupt */
-
- /* BT report packet sample rate */
- btcoexist->btc_write_1byte(btcoexist, 0x790, 0x5);
-
- /* Init 0x778 = 0x1 for 2-Ant */
- btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1);
-
- /* Enable PTA (3-wire function form BT side) */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1);
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x41, 0x02, 0x1);
-
- /* Enable PTA (tx/rx signal form WiFi side) */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4c6, 0x10, 0x1);
-
- halbtc8723d2ant_enable_gnt_to_gpio(btcoexist, FALSE);
-
- /* check if WL firmware download ok */
- if (btcoexist->btc_read_1byte(btcoexist, 0x80) == 0xc6)
- halbtc8723d2ant_post_onoffstate_to_bt(btcoexist, true);
-
- /* Enable counter statistics */
- btcoexist->btc_write_1byte(btcoexist, 0x76e,
- 0x4); /* 0x76e[3] =1, WLAN_Act control by PTA */
-
- if (wifi_only) {
- coex_sta->concurrent_rx_mode_on = false;
- /* Path config */
- halbtc8723d2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, true,
- false);
- halbtc8723d2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, false,
- false);
- } else {
- /* coex_sta->concurrent_rx_mode_on = true; */
- /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x2, 0x1); */
-
- /* RF 0x1[0] = 0->Set GNT_WL_RF_Rx always = 1 for con-current Rx */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0x1, 0x0);
-
- /* Path config */
- halbtc8723d2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, true,
- false);
- }
-
- /* WLAN_Tx by GNT_WL 0x950[29] = 0 */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x20, 0x0);
-
- halbtc8723d2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
-
- halbtc8723d2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
-
- u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x67);
- u32tmp0 = btcoexist->btc_read_4byte(btcoexist, 0x70);
- u32tmp1 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
- u32tmp2 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** 0x67 = 0x%x, 0x70 = 0x%x, 0x38= 0x%x, 0x54= 0x%x (After Init HW config) **********\n",
- u8tmp, u32tmp0, u32tmp1, u32tmp2);
- BTC_TRACE(trace_buf);
-
- psd_scan->ant_det_is_ant_det_available = TRUE;
-
-}
-
-u32 halbtc8723d2ant_psd_log2base(IN struct btc_coexist *btcoexist, IN u32 val)
-{
- u8 j;
- u32 tmp, tmp2, val_integerd_b = 0, tindex, shiftcount = 0;
- u32 result, val_fractiond_b = 0, table_fraction[21] = {0, 432, 332, 274, 232, 200,
- 174, 151, 132, 115, 100, 86, 74, 62, 51, 42,
- 32, 23, 15, 7, 0
- };
-
- if (val == 0)
- return 0;
-
- tmp = val;
-
- while (1) {
- if (tmp == 1)
- break;
- else {
- tmp = (tmp >> 1);
- shiftcount++;
- }
- }
-
-
- val_integerd_b = shiftcount + 1;
-
- tmp2 = 1;
- for (j = 1; j <= val_integerd_b; j++)
- tmp2 = tmp2 * 2;
-
- tmp = (val * 100) / tmp2;
- tindex = tmp / 5;
-
- if (tindex > 20)
- tindex = 20;
-
- val_fractiond_b = table_fraction[tindex];
-
- result = val_integerd_b * 100 - val_fractiond_b;
-
- return result;
-
-
-}
-
-void halbtc8723d2ant_psd_show_antenna_detect_result(IN struct btc_coexist
- *btcoexist)
-{
- u8 *cli_buf = btcoexist->cli_buf;
- struct btc_board_info *board_info = &btcoexist->board_info;
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n============[Antenna Detection info] ============\n");
- CL_PRINTF(cli_buf);
-
- if (psd_scan->ant_det_result == 1)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (>%d)",
- "Ant Det Result", "2-Antenna (Bad-Isolation)",
- BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION);
- else if (psd_scan->ant_det_result == 2)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (%d~%d)",
- "Ant Det Result", "2-Antenna (Good-Isolation)",
- BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION
- + psd_scan->ant_det_thres_offset,
- BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (%d~%d)",
- "Ant Det Result", "1-Antenna",
- BT_8723D_2ANT_ANTDET_PSDTHRES_1ANT,
- BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION
- + psd_scan->ant_det_thres_offset);
-
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s ",
- "Antenna Detection Finish",
- (board_info->btdm_ant_det_finish
- ? "Yes" : "No"));
- CL_PRINTF(cli_buf);
-
- switch (psd_scan->ant_det_result) {
- case 0:
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "(BT is not available)");
- break;
- case 1: /* 2-Ant bad-isolation */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "(BT is available)");
- break;
- case 2: /* 2-Ant good-isolation */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "(BT is available)");
- break;
- case 3: /* 1-Ant */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "(BT is available)");
- break;
- case 4:
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "(Uncertainty result)");
- break;
- case 5:
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "(Pre-Scan fai)");
- break;
- case 6:
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "(WiFi is Scanning)");
- break;
- case 7:
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "(BT is not idle)");
- break;
- case 8:
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "(Abort by WiFi Scanning)");
- break;
- case 9:
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "(Antenna Init is not ready)");
- break;
- case 10:
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "(BT is Inquiry or page)");
- break;
- case 11:
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "(BT is Disabled)");
- break;
- }
- CL_PRINTF(cli_buf);
-
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
- "Ant Detect Total Count", psd_scan->ant_det_try_count);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
- "Ant Detect Fail Count", psd_scan->ant_det_fail_count);
- CL_PRINTF(cli_buf);
-
- if ((!board_info->btdm_ant_det_finish) &&
- (psd_scan->ant_det_result != 5))
- return;
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "BT Response",
- (psd_scan->ant_det_result ? "ok" : "fail"));
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ms", "BT Tx Time",
- psd_scan->ant_det_bt_tx_time);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "BT Tx Ch",
- psd_scan->ant_det_bt_le_channel);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d",
- "WiFi PSD Cent-Ch/Offset/Span",
- psd_scan->real_cent_freq, psd_scan->real_offset,
- psd_scan->real_span);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d dB",
- "PSD Pre-Scan Peak Value",
- psd_scan->ant_det_pre_psdscan_peak_val / 100);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (<= %d)",
- "PSD Pre-Scan result",
- (psd_scan->ant_det_result != 5 ? "ok" : "fail"),
- BT_8723D_2ANT_ANTDET_PSDTHRES_BACKGROUND
- + psd_scan->ant_det_thres_offset);
- CL_PRINTF(cli_buf);
-
- if (psd_scan->ant_det_result == 5)
- return;
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s dB",
- "PSD Scan Peak Value", psd_scan->ant_det_peak_val);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s MHz",
- "PSD Scan Peak Freq", psd_scan->ant_det_peak_freq);
- CL_PRINTF(cli_buf);
-
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "TFBGA Package",
- (board_info->tfbga_package) ? "Yes" : "No");
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
- "PSD Threshold Offset", psd_scan->ant_det_thres_offset);
- CL_PRINTF(cli_buf);
-
-}
-
-void halbtc8723d2ant_psd_showdata(IN struct btc_coexist *btcoexist)
-{
- u8 *cli_buf = btcoexist->cli_buf;
- u32 delta_freq_per_point;
- u32 freq, freq1, freq2, n = 0, i = 0, j = 0, m = 0, psd_rep1, psd_rep2;
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n\n============[PSD info] (%d)============\n",
- psd_scan->psd_gen_count);
- CL_PRINTF(cli_buf);
-
- if (psd_scan->psd_gen_count == 0) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n No data !!\n");
- CL_PRINTF(cli_buf);
- return;
- }
-
- if (psd_scan->psd_point == 0)
- delta_freq_per_point = 0;
- else
- delta_freq_per_point = psd_scan->psd_band_width /
- psd_scan->psd_point;
-
- /* if (psd_scan->is_psd_show_max_only) */
- if (0) {
- psd_rep1 = psd_scan->psd_max_value / 100;
- psd_rep2 = psd_scan->psd_max_value - psd_rep1 * 100;
-
- freq = ((psd_scan->real_cent_freq - 20) * 1000000 +
- psd_scan->psd_max_value_point * delta_freq_per_point);
- freq1 = freq / 1000000;
- freq2 = freq / 1000 - freq1 * 1000;
-
- if (freq2 < 100)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n Freq = %d.0%d MHz",
- freq1, freq2);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n Freq = %d.%d MHz",
- freq1, freq2);
-
- if (psd_rep2 < 10)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- ", Value = %d.0%d dB, (%d)\n",
- psd_rep1, psd_rep2, psd_scan->psd_max_value);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- ", Value = %d.%d dB, (%d)\n",
- psd_rep1, psd_rep2, psd_scan->psd_max_value);
-
- CL_PRINTF(cli_buf);
- } else {
- m = psd_scan->psd_start_point;
- n = psd_scan->psd_start_point;
- i = 1;
- j = 1;
-
- while (1) {
- do {
- freq = ((psd_scan->real_cent_freq - 20) * 1000000 + m *
- delta_freq_per_point);
- freq1 = freq / 1000000;
- freq2 = freq / 1000 - freq1 * 1000;
-
- if (i == 1) {
- if (freq2 == 0)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n Freq%6d.000", freq1);
- else if (freq2 < 100)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n Freq%6d.0%2d", freq1,
- freq2);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n Freq%6d.%3d", freq1,
- freq2);
- } else if ((i % 8 == 0) ||
- (m == psd_scan->psd_stop_point)) {
- if (freq2 == 0)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%6d.000\n", freq1);
- else if (freq2 < 100)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%6d.0%2d\n", freq1, freq2);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%6d.%3d\n", freq1, freq2);
- } else {
- if (freq2 == 0)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%6d.000", freq1);
- else if (freq2 < 100)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%6d.0%2d", freq1, freq2);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%6d.%3d", freq1, freq2);
- }
-
- i++;
- m++;
- CL_PRINTF(cli_buf);
-
- } while ((i <= 8) && (m <= psd_scan->psd_stop_point));
-
-
- do {
- psd_rep1 = psd_scan->psd_report_max_hold[n] / 100;
- psd_rep2 = psd_scan->psd_report_max_hold[n] - psd_rep1 *
- 100;
-
- if (j == 1) {
- if (psd_rep2 < 10)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n Val %7d.0%d", psd_rep1,
- psd_rep2);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n Val %7d.%d", psd_rep1,
- psd_rep2);
- } else if ((j % 8 == 0) ||
- (n == psd_scan->psd_stop_point)) {
- if (psd_rep2 < 10)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%7d.0%d\n", psd_rep1,
- psd_rep2);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%7d.%d\n", psd_rep1, psd_rep2);
- } else {
- if (psd_rep2 < 10)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%7d.0%d", psd_rep1, psd_rep2);
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "%7d.%d", psd_rep1, psd_rep2);
- }
-
- j++;
- n++;
- CL_PRINTF(cli_buf);
-
- } while ((j <= 8) && (n <= psd_scan->psd_stop_point));
-
- if ((m > psd_scan->psd_stop_point) ||
- (n > psd_scan->psd_stop_point))
- break;
- else {
- i = 1;
- j = 1;
- }
-
- }
- }
-
-
-}
-
-void halbtc8723d2ant_psd_maxholddata(IN struct btc_coexist *btcoexist,
- IN u32 gen_count)
-{
- u32 i = 0, i_max = 0, val_max = 0;
-
- if (gen_count == 1) {
- memcpy(psd_scan->psd_report_max_hold,
- psd_scan->psd_report,
- BT_8723D_2ANT_ANTDET_PSD_POINTS * sizeof(u32));
-
- psd_scan->psd_max_value_point = 0;
- psd_scan->psd_max_value = 0;
-
- } else {
- for (i = psd_scan->psd_start_point;
- i <= psd_scan->psd_stop_point; i++) {
- if (psd_scan->psd_report[i] >
- psd_scan->psd_report_max_hold[i])
- psd_scan->psd_report_max_hold[i] =
- psd_scan->psd_report[i];
-
- /* search Max Value */
- if (i == psd_scan->psd_start_point) {
- i_max = i;
- val_max = psd_scan->psd_report_max_hold[i];
- } else {
- if (psd_scan->psd_report_max_hold[i] >
- val_max) {
- i_max = i;
- val_max = psd_scan->psd_report_max_hold[i];
- }
- }
-
- }
-
- psd_scan->psd_max_value_point = i_max;
- psd_scan->psd_max_value = val_max;
-
- }
-
-
-}
-
-u32 halbtc8723d2ant_psd_getdata(IN struct btc_coexist *btcoexist, IN u32 point)
-{
- /* reg 0x808[9:0]: FFT data x */
- /* reg 0x808[22]: 0-->1 to get 1 FFT data y */
- /* reg 0x8b4[15:0]: FFT data y report */
-
- u32 val = 0, psd_report = 0;
- int k = 0;
-
- val = btcoexist->btc_read_4byte(btcoexist, 0x808);
-
- val &= 0xffbffc00;
- val |= point;
-
- btcoexist->btc_write_4byte(btcoexist, 0x808, val);
-
- val |= 0x00400000;
- btcoexist->btc_write_4byte(btcoexist, 0x808, val);
-
- while (1) {
- if (k++ > BT_8723D_2ANT_ANTDET_SWEEPPOINT_DELAY)
- break;
- }
-
- val = btcoexist->btc_read_4byte(btcoexist, 0x8b4);
-
- psd_report = val & 0x0000ffff;
-
- return psd_report;
-}
-
-
-boolean halbtc8723d2ant_psd_sweep_point(IN struct btc_coexist *btcoexist,
- IN u32 cent_freq, IN s32 offset, IN u32 span, IN u32 points,
- IN u32 avgnum, IN u32 loopcnt)
-{
- u32 i = 0, val = 0, n = 0, k = 0, j, point_index = 0;
- u32 points1 = 0, psd_report = 0;
- u32 start_p = 0, stop_p = 0, delta_freq_per_point = 156250;
- u32 psd_center_freq = 20 * 10 ^ 6;
- boolean outloop = false, scan , roam, is_sweep_ok = true;
- u8 flag = 0;
- u32 tmp = 0, u32tmp1 = 0;
- u32 wifi_original_channel = 1;
-
- psd_scan->is_psd_running = true;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx PSD Sweep Start!!\n");
- BTC_TRACE(trace_buf);
-
- do {
- switch (flag) {
- case 0: /* Get PSD parameters */
- default:
-
- psd_scan->psd_band_width = 40 * 1000000;
- psd_scan->psd_point = points;
- psd_scan->psd_start_base = points / 2;
- psd_scan->psd_avg_num = avgnum;
- psd_scan->real_cent_freq = cent_freq;
- psd_scan->real_offset = offset;
- psd_scan->real_span = span;
-
-
- points1 = psd_scan->psd_point;
- delta_freq_per_point = psd_scan->psd_band_width /
- psd_scan->psd_point;
-
- /* PSD point setup */
- val = btcoexist->btc_read_4byte(btcoexist, 0x808);
- val &= 0xffff0fff;
-
- switch (psd_scan->psd_point) {
- case 128:
- val |= 0x0;
- break;
- case 256:
- default:
- val |= 0x00004000;
- break;
- case 512:
- val |= 0x00008000;
- break;
- case 1024:
- val |= 0x0000c000;
- break;
- }
-
- switch (psd_scan->psd_avg_num) {
- case 1:
- val |= 0x0;
- break;
- case 8:
- val |= 0x00001000;
- break;
- case 16:
- val |= 0x00002000;
- break;
- case 32:
- default:
- val |= 0x00003000;
- break;
- }
- btcoexist->btc_write_4byte(btcoexist, 0x808, val);
-
- flag = 1;
- break;
- case 1: /* calculate the PSD point index from freq/offset/span */
- psd_center_freq = psd_scan->psd_band_width / 2 +
- offset * (1000000);
-
- start_p = psd_scan->psd_start_base + (psd_center_freq -
- span * (1000000) / 2) / delta_freq_per_point;
- psd_scan->psd_start_point = start_p -
- psd_scan->psd_start_base;
-
- stop_p = psd_scan->psd_start_base + (psd_center_freq +
- span * (1000000) / 2) / delta_freq_per_point;
- psd_scan->psd_stop_point = stop_p -
- psd_scan->psd_start_base - 1;
-
- flag = 2;
- break;
- case 2: /* set RF channel/BW/Mode */
-
- /* set 3-wire off */
- val = btcoexist->btc_read_4byte(btcoexist, 0x88c);
- val |= 0x00300000;
- btcoexist->btc_write_4byte(btcoexist, 0x88c, val);
-
- /* CCK off */
- val = btcoexist->btc_read_4byte(btcoexist, 0x800);
- val &= 0xfeffffff;
- btcoexist->btc_write_4byte(btcoexist, 0x800, val);
-
- /* Tx-pause on */
- btcoexist->btc_write_1byte(btcoexist, 0x522, 0x6f);
-
- /* store WiFi original channel */
- wifi_original_channel = btcoexist->btc_get_rf_reg(
- btcoexist, BTC_RF_A, 0x18, 0x3ff);
-
- /* Set RF channel */
- if (cent_freq == 2484)
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A,
- 0x18, 0x3ff, 0xe);
- else
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A,
- 0x18, 0x3ff, (cent_freq - 2412) / 5 +
- 1); /* WiFi TRx Mask on */
-
- /* save original RCK value */
- u32tmp1 = btcoexist->btc_get_rf_reg(
- btcoexist, BTC_RF_A, 0x1d, 0xfffff);
-
- /* Enter debug mode */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xde,
- 0x2, 0x1);
-
- /* Set RF Rx filter corner */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1d,
- 0xfffff, 0x2e);
-
-
- /* Set RF mode = Rx, RF Gain = 0x320a0 */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x0,
- 0xfffff, 0x320a0);
-
- while (1) {
- if (k++ > BT_8723D_2ANT_ANTDET_SWEEPPOINT_DELAY)
- break;
- }
- flag = 3;
- break;
- case 3:
- psd_scan->psd_gen_count = 0;
-
- for (j = 1; j <= loopcnt; j++) {
-
- /* btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x0, 0xfffff, 0x320a0); */
-
- btcoexist->btc_get(btcoexist,
- BTC_GET_BL_WIFI_SCAN, &scan);
- btcoexist->btc_get(btcoexist,
- BTC_GET_BL_WIFI_ROAM, &roam);
-
- if (scan || roam) {
- is_sweep_ok = false;
- break;
- }
- memset(psd_scan->psd_report, 0,
- psd_scan->psd_point * sizeof(u32));
- start_p = psd_scan->psd_start_point +
- psd_scan->psd_start_base;
- stop_p = psd_scan->psd_stop_point +
- psd_scan->psd_start_base + 1;
-
- i = start_p;
- point_index = 0;
-
- while (i < stop_p) {
- if (i >= points1)
- psd_report =
- halbtc8723d2ant_psd_getdata(
- btcoexist, i - points1);
- else
- psd_report =
- halbtc8723d2ant_psd_getdata(
- btcoexist, i);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "Point=%d, psd_raw_data = 0x%08x\n",
- i, psd_report);
- BTC_TRACE(trace_buf);
- if (psd_report == 0)
- tmp = 0;
- else
- /* tmp = 20*log10((double)psd_report); */
- /* 20*log2(x)/log2(10), log2Base return theresult of the psd_report*100 */
- tmp = 6 * halbtc8723d2ant_psd_log2base(
- btcoexist, psd_report);
-
- n = i - psd_scan->psd_start_base;
- psd_scan->psd_report[n] = tmp;
-
-
- halbtc8723d2ant_psd_maxholddata(
- btcoexist, j);
-
- i++;
-
- }
-
- psd_scan->psd_gen_count = j;
-
-
- /*
- val = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
- tmp = btcoexist->btc_read_4byte(btcoexist, 0x64);
- u32tmp1 = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "0x54 = 0x%08x, 0x67 = 0x%08x, 0x6c4 = 0x%08x\n", val, (tmp & 0xff000000) >> 24 ,u32tmp1);
- BTC_TRACE(trace_buf);
- */
-
- }
-
- flag = 100;
- break;
- case 99: /* error */
-
- outloop = true;
- break;
- case 100: /* recovery */
-
- /* set 3-wire on */
- val = btcoexist->btc_read_4byte(btcoexist, 0x88c);
- val &= 0xffcfffff;
- btcoexist->btc_write_4byte(btcoexist, 0x88c, val);
-
- /* CCK on */
- val = btcoexist->btc_read_4byte(btcoexist, 0x800);
- val |= 0x01000000;
- btcoexist->btc_write_4byte(btcoexist, 0x800, val);
-
- /* Tx-pause off */
- btcoexist->btc_write_1byte(btcoexist, 0x522, 0x0);
-
- /* PSD off */
- val = btcoexist->btc_read_4byte(btcoexist, 0x808);
- val &= 0xffbfffff;
- btcoexist->btc_write_4byte(btcoexist, 0x808, val);
-
- /* restore RF Rx filter corner */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1d,
- 0xfffff, u32tmp1);
-
- /* Exit debug mode */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xde,
- 0x2, 0x0);
-
- /* restore WiFi original channel */
- btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x18,
- 0x3ff, wifi_original_channel);
-
- outloop = true;
- break;
-
- }
-
- } while (!outloop);
-
-
-
- psd_scan->is_psd_running = false;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx PSD Sweep Stop!!\n");
- BTC_TRACE(trace_buf);
- return is_sweep_ok;
-
-}
-
-void halbtc8723d2ant_psd_antenna_detection(IN struct btc_coexist *btcoexist,
- IN u32 bt_tx_time, IN u32 bt_le_channel)
-{
- u32 i = 0;
- u32 wlpsd_cent_freq = 2484, wlpsd_span = 2, wlpsd_sweep_count = 50;
- s32 wlpsd_offset = -4;
- u8 bt_le_ch[13] = {3, 6, 8, 11, 13, 16, 18, 21, 23, 26, 28, 31, 33};
-
- u8 h2c_parameter[3] = {0}, u8tmpa, u8tmpb;
-
- u8 state = 0;
- boolean outloop = false, bt_resp = false;
- u32 freq, freq1, freq2, psd_rep1, psd_rep2, delta_freq_per_point,
- u32tmp, u32tmp0, u32tmp1, u32tmp2;
- struct btc_board_info *board_info = &btcoexist->board_info;
-
- board_info->btdm_ant_det_finish = false;
- memset(psd_scan->ant_det_peak_val, 0, 16 * sizeof(u8));
- memset(psd_scan->ant_det_peak_freq, 0, 16 * sizeof(u8));
-
- if (board_info->tfbga_package) /* for TFBGA */
- psd_scan->ant_det_thres_offset = 5;
- else
- psd_scan->ant_det_thres_offset = 0;
-
- do {
- switch (state) {
- case 0:
- if (bt_le_channel == 39)
- wlpsd_cent_freq = 2484;
- else {
- for (i = 1; i <= 13; i++) {
- if (bt_le_ch[i - 1] ==
- bt_le_channel) {
- wlpsd_cent_freq = 2412
- + (i - 1) * 5;
- break;
- }
- }
-
- if (i == 14) {
-
- BTC_SPRINTF(trace_buf,
- BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Abort!!, Invalid LE channel = %d\n ",
- bt_le_channel);
- BTC_TRACE(trace_buf);
- outloop = true;
- break;
- }
- }
-
- wlpsd_sweep_count = bt_tx_time * 238 /
- 100; /* bt_tx_time/0.42 */
- wlpsd_sweep_count = wlpsd_sweep_count / 5;
-
- if (wlpsd_sweep_count % 5 != 0)
- wlpsd_sweep_count = (wlpsd_sweep_count /
- 5 + 1) * 5;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), BT_LETxTime=%d, BT_LECh = %d\n",
- bt_tx_time, bt_le_channel);
- BTC_TRACE(trace_buf);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), wlpsd_cent_freq=%d, wlpsd_offset = %d, wlpsd_span = %d, wlpsd_sweep_count = %d\n",
- wlpsd_cent_freq,
- wlpsd_offset,
- wlpsd_span,
- wlpsd_sweep_count);
- BTC_TRACE(trace_buf);
-
- state = 1;
- break;
- case 1: /* stop coex DM & set antenna path */
- /* Stop Coex DM */
- /*
- btcoexist->stop_coex_dm = true;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Stop Coex DM!!\n");
- BTC_TRACE(trace_buf); */
-
- /* Set TDMA off, */
- halbtc8723d2ant_ps_tdma(btcoexist, FORCE_EXEC,
- false, 0);
-
- /* Set coex table */
- halbtc8723d2ant_coex_table_with_type(btcoexist,
- FORCE_EXEC, 0);
-
- if (board_info->btdm_ant_pos ==
- BTC_ANTENNA_AT_MAIN_PORT) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna at Main Port\n");
- BTC_TRACE(trace_buf);
-
-
- /* Set Antenna Path, both GNT_WL/GNT_BT = 1, and control by SW */
- /* Set Antenna path, switch WiFi to un-certain antenna port */
-
- halbtc8723d2ant_set_ant_path(btcoexist,
- BTC_ANT_WIFI_AT_AUX, true,
- false);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna at Aux Port\n");
- BTC_TRACE(trace_buf);
-
-
- /* Set Antenna Path, both GNT_WL/GNT_BT = 1, and control by SW */
- /* Set Antenna path, switch WiFi to un-certain antenna port */
-
- halbtc8723d2ant_set_ant_path(btcoexist,
- BTC_ANT_WIFI_AT_MAIN, true,
- false);
- }
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Set Antenna to BT!!\n");
- BTC_TRACE(trace_buf);
-
- /* Set AFH mask on at WiFi channel 2472MHz +/- 10MHz */
- h2c_parameter[0] = 0x1;
- h2c_parameter[1] = 0xd;
- h2c_parameter[2] = 0x14;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Set AFH on, Cent-Ch= %d, Mask=%d\n",
- h2c_parameter[1],
- h2c_parameter[2]);
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_fill_h2c(btcoexist, 0x66, 3,
- h2c_parameter);
-
- u32tmp = btcoexist->btc_read_2byte(btcoexist, 0x948);
- u32tmp0 = btcoexist->btc_read_4byte(btcoexist, 0x70);
- u32tmp1 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
- u32tmp2 = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** 0x948 = 0x%x, 0x70 = 0x%x, 0x38= 0x%x, 0x54= 0x%x (Before Ant Det) **********\n",
- u32tmp, u32tmp0, u32tmp1, u32tmp2);
- BTC_TRACE(trace_buf);
-
- state = 2;
- break;
- case 2: /* Pre-sweep background psd */
- if (!halbtc8723d2ant_psd_sweep_point(btcoexist,
- wlpsd_cent_freq, wlpsd_offset, wlpsd_span,
- BT_8723D_2ANT_ANTDET_PSD_POINTS,
- BT_8723D_2ANT_ANTDET_PSD_AVGNUM, 3)) {
- board_info->btdm_ant_det_finish = false;
- board_info->btdm_ant_num_by_ant_det = 1;
- psd_scan->ant_det_result = 8;
- state = 99;
- break;
- }
-
- psd_scan->ant_det_pre_psdscan_peak_val =
- psd_scan->psd_max_value;
-
- if (psd_scan->psd_max_value >
- (BT_8723D_2ANT_ANTDET_PSDTHRES_BACKGROUND
- + psd_scan->ant_det_thres_offset) * 100) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Abort Antenna Detection!! becaus background = %d > thres (%d)\n",
- psd_scan->psd_max_value / 100,
- BT_8723D_2ANT_ANTDET_PSDTHRES_BACKGROUND
- + psd_scan->ant_det_thres_offset);
- BTC_TRACE(trace_buf);
- board_info->btdm_ant_det_finish = false;
- board_info->btdm_ant_num_by_ant_det = 1;
- psd_scan->ant_det_result = 5;
- state = 99;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Start Antenna Detection!! becaus background = %d <= thres (%d)\n",
- psd_scan->psd_max_value / 100,
- BT_8723D_2ANT_ANTDET_PSDTHRES_BACKGROUND
- + psd_scan->ant_det_thres_offset);
- BTC_TRACE(trace_buf);
- state = 3;
- }
- break;
- case 3:
- bt_resp = btcoexist->btc_set_bt_ant_detection(
- btcoexist, (u8)(bt_tx_time & 0xff),
- (u8)(bt_le_channel & 0xff));
-
- if (!halbtc8723d2ant_psd_sweep_point(btcoexist,
- wlpsd_cent_freq, wlpsd_offset,
- wlpsd_span,
- BT_8723D_2ANT_ANTDET_PSD_POINTS,
- BT_8723D_2ANT_ANTDET_PSD_AVGNUM,
- wlpsd_sweep_count)) {
- board_info->btdm_ant_det_finish = false;
- board_info->btdm_ant_num_by_ant_det = 1;
- psd_scan->ant_det_result = 8;
- state = 99;
- break;
- }
-
- psd_scan->ant_det_psd_scan_peak_val =
- psd_scan->psd_max_value;
- psd_scan->ant_det_psd_scan_peak_freq =
- psd_scan->psd_max_value_point;
- state = 4;
- break;
- case 4:
-
- if (psd_scan->psd_point == 0)
- delta_freq_per_point = 0;
- else
- delta_freq_per_point =
- psd_scan->psd_band_width /
- psd_scan->psd_point;
-
- psd_rep1 = psd_scan->psd_max_value / 100;
- psd_rep2 = psd_scan->psd_max_value - psd_rep1 *
- 100;
-
- freq = ((psd_scan->real_cent_freq - 20) *
- 1000000 + psd_scan->psd_max_value_point
- * delta_freq_per_point);
- freq1 = freq / 1000000;
- freq2 = freq / 1000 - freq1 * 1000;
-
- if (freq2 < 100) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Max Value: Freq = %d.0%d MHz",
- freq1, freq2);
- BTC_TRACE(trace_buf);
- CL_SPRINTF(psd_scan->ant_det_peak_freq,
- BT_8723D_2ANT_ANTDET_BUF_LEN,
- "%d.0%d", freq1, freq2);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Max Value: Freq = %d.%d MHz",
- freq1, freq2);
- BTC_TRACE(trace_buf);
- CL_SPRINTF(psd_scan->ant_det_peak_freq,
- BT_8723D_2ANT_ANTDET_BUF_LEN,
- "%d.%d", freq1, freq2);
- }
-
- if (psd_rep2 < 10) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- ", Value = %d.0%d dB\n",
- psd_rep1, psd_rep2);
- BTC_TRACE(trace_buf);
- CL_SPRINTF(psd_scan->ant_det_peak_val,
- BT_8723D_2ANT_ANTDET_BUF_LEN,
- "%d.0%d", psd_rep1, psd_rep2);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- ", Value = %d.%d dB\n",
- psd_rep1, psd_rep2);
- BTC_TRACE(trace_buf);
- CL_SPRINTF(psd_scan->ant_det_peak_val,
- BT_8723D_2ANT_ANTDET_BUF_LEN,
- "%d.%d", psd_rep1, psd_rep2);
- }
-
- psd_scan->ant_det_is_btreply_available = true;
-
- if (bt_resp == false) {
- psd_scan->ant_det_is_btreply_available =
- false;
- psd_scan->ant_det_result = 0;
- board_info->btdm_ant_det_finish = false;
- board_info->btdm_ant_num_by_ant_det = 1;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), BT Response = Fail\n ");
- BTC_TRACE(trace_buf);
- } else if (psd_scan->psd_max_value >
- (BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION)
- * 100) {
- psd_scan->ant_det_result = 1;
- board_info->btdm_ant_det_finish = true;
- board_info->btdm_ant_num_by_ant_det = 2;
- coex_sta->isolation_btween_wb = (u8)(85 - psd_scan->psd_max_value / 100) & 0xff;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 2-Ant, Bad-Isolation!!\n");
- BTC_TRACE(trace_buf);
- } else if (psd_scan->psd_max_value >
- (BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION
- + psd_scan->ant_det_thres_offset) * 100) {
- psd_scan->ant_det_result = 2;
- board_info->btdm_ant_det_finish = true;
- board_info->btdm_ant_num_by_ant_det = 2;
- coex_sta->isolation_btween_wb = (u8)(85 - psd_scan->psd_max_value / 100) & 0xff;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 2-Ant, Good-Isolation!!\n");
- BTC_TRACE(trace_buf);
- } else if (psd_scan->psd_max_value >
- (BT_8723D_2ANT_ANTDET_PSDTHRES_1ANT) *
- 100) {
- psd_scan->ant_det_result = 3;
- board_info->btdm_ant_det_finish = true;
- board_info->btdm_ant_num_by_ant_det = 1;
- coex_sta->isolation_btween_wb = (u8)(85 - psd_scan->psd_max_value / 100) & 0xff;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 1-Ant!!\n");
- BTC_TRACE(trace_buf);
- } else {
- psd_scan->ant_det_result = 4;
- board_info->btdm_ant_det_finish = false;
- board_info->btdm_ant_num_by_ant_det = 1;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 1-Ant, un-certainity!!\n");
- BTC_TRACE(trace_buf);
- }
-
- state = 99;
- break;
- case 99: /* restore setup */
-
- /* Set AFH mask off at WiFi channel 2472MHz +/- 10MHz */
- h2c_parameter[0] = 0x0;
- h2c_parameter[1] = 0x0;
- h2c_parameter[2] = 0x0;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Set AFH on, Cent-Ch= %d, Mask=%d\n",
- h2c_parameter[1], h2c_parameter[2]);
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_fill_h2c(btcoexist, 0x66, 3,
- h2c_parameter);
-
- /* Set Antenna Path, GNT_WL/GNT_BT control by PTA */
- /* Set Antenna path, switch WiFi to certain antenna port */
- halbtc8723d2ant_set_ant_path(btcoexist,
- BTC_ANT_WIFI_AT_MAIN, false,
- false);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Set Antenna to PTA\n!!");
- BTC_TRACE(trace_buf);
-
- /* Resume Coex DM */
- /*
- btcoexist->stop_coex_dm = false;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Resume Coex DM\n!!");
- BTC_TRACE(trace_buf); */
-
- /* stimulate coex running */
- /*
- halbtc8723d2ant_run_coexist_mechanism(
- btcoexist);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Stimulate Coex running\n!!");
- BTC_TRACE(trace_buf); */
-
- outloop = true;
- break;
- }
-
- } while (!outloop);
-
-
-
-}
-
-void halbtc8723d2ant_psd_antenna_detection_check(IN struct btc_coexist
- *btcoexist)
-{
- static u32 ant_det_count = 0, ant_det_fail_count = 0;
- struct btc_board_info *board_info = &btcoexist->board_info;
-
- boolean scan, roam;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
-
-
- /* psd_scan->ant_det_bt_tx_time = 20; */
- psd_scan->ant_det_bt_tx_time =
- BT_8723D_2ANT_ANTDET_BTTXTIME; /* 0.42ms*50 = 20ms (0.42ms = 1 PSD sweep) */
- psd_scan->ant_det_bt_le_channel = BT_8723D_2ANT_ANTDET_BTTXCHANNEL;
-
- ant_det_count++;
-
- psd_scan->ant_det_try_count = ant_det_count;
-
- if (scan || roam) {
- board_info->btdm_ant_det_finish = false;
- psd_scan->ant_det_result = 6;
- } else if (coex_sta->bt_disabled) {
- board_info->btdm_ant_det_finish = false;
- psd_scan->ant_det_result = 11;
- } else if (coex_sta->num_of_profile >= 1) {
- board_info->btdm_ant_det_finish = false;
- psd_scan->ant_det_result = 7;
- } else if (
- !psd_scan->ant_det_is_ant_det_available) { /* Antenna initial setup is not ready */
- board_info->btdm_ant_det_finish = false;
- psd_scan->ant_det_result = 9;
- } else if (coex_sta->c2h_bt_inquiry_page) {
- board_info->btdm_ant_det_finish = false;
- psd_scan->ant_det_result = 10;
- } else {
-
- btcoexist->stop_coex_dm = true;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Stop Coex DM!!\n");
- BTC_TRACE(trace_buf);
-
- halbtc8723d2ant_psd_antenna_detection(btcoexist,
- psd_scan->ant_det_bt_tx_time,
- psd_scan->ant_det_bt_le_channel);
-
- delay_ms(psd_scan->ant_det_bt_tx_time);
-
- btcoexist->stop_coex_dm = false;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Resume Coex DM\n!!");
- BTC_TRACE(trace_buf);
-
- /* stimulate coex running */
-
- halbtc8723d2ant_run_coexist_mechanism(
- btcoexist);
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Stimulate Coex running\n!!");
- BTC_TRACE(trace_buf);
- }
-
-
- if (!board_info->btdm_ant_det_finish)
- ant_det_fail_count++;
-
- psd_scan->ant_det_fail_count = ant_det_fail_count;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), result = %d, fail_count = %d, finish = %s\n",
- psd_scan->ant_det_result,
- psd_scan->ant_det_fail_count,
- board_info->btdm_ant_det_finish == TRUE ? "Yes" : "No");
- BTC_TRACE(trace_buf);
-
-}
-
-
-/* ************************************************************
- * work around function start with wa_halbtc8723d2ant_
- * ************************************************************
- * ************************************************************
- * extern function start with ex_halbtc8723d2ant_
- * ************************************************************ */
-void ex_halbtc8723d2ant_power_on_setting(IN struct btc_coexist *btcoexist)
-{
- struct btc_board_info *board_info = &btcoexist->board_info;
- u8 u8tmp = 0x0;
- u16 u16tmp = 0x0;
- u32 value = 0;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx Execute 8723d 2-Ant PowerOn Setting xxxxxxxxxxxxxxxx!!\n");
- BTC_TRACE(trace_buf);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "Ant Det Finish = %s, Ant Det Number = %d\n",
- (board_info->btdm_ant_det_finish ? "Yes" : "No"),
- board_info->btdm_ant_num_by_ant_det);
- BTC_TRACE(trace_buf);
-
-
- btcoexist->stop_coex_dm = true;
- psd_scan->ant_det_is_ant_det_available = FALSE;
-
- /* enable BB, REG_SYS_FUNC_EN such that we can write BB Register correctly. */
- u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2);
- btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1));
-
- /* set Path control owner to WiFi */
- halbtc8723d2ant_ltecoex_pathcontrol_owner(btcoexist,
- BT_8723D_2ANT_PCO_WLSIDE);
-
- /* set GNT_BT to high */
- halbtc8723d2ant_ltecoex_set_gnt_bt(btcoexist,
- BT_8723D_2ANT_GNT_BLOCK_RFC_BB,
- BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW,
- BT_8723D_2ANT_SIG_STA_SET_TO_HIGH);
- /* Set GNT_WL to high */
- halbtc8723d2ant_ltecoex_set_gnt_wl(btcoexist,
- BT_8723D_2ANT_GNT_BLOCK_RFC_BB,
- BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW,
- BT_8723D_2ANT_SIG_STA_SET_TO_HIGH);
-
- /* Local setting bit define */
- /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */
- /* BIT1: "0" for internal switch; "1" for external switch */
- /* BIT2: "0" for one antenna; "1" for two antenna */
- /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */
-
- /* Set path control to WL */
- btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x80, 0x1);
- btcoexist->btc_write_2byte(btcoexist, 0x948, 0x0);
-
- /* Check efuse 0xc3[6] for Single Antenna Path */
- if (board_info->single_ant_path == 0) {
- /* set to S1 */
- board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;
- u8tmp = 4;
- } else if (board_info->single_ant_path == 1) {
- /* set to S0 */
- board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT;
- u8tmp = 5;
- }
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** (Power On) single_ant_path = %d, btdm_ant_pos = %d **********\n",
- board_info->single_ant_path , board_info->btdm_ant_pos);
- BTC_TRACE(trace_buf);
-
- /* Write Single Antenna Position to Registry to tell BT for 872db. This line can be removed
- since BT EFuse also add "single antenna position" in EFuse for 8723d*/
- btcoexist->btc_set(btcoexist, BTC_SET_ACT_ANTPOSREGRISTRY_CTRL,
- &value);
-
- /* Save"single antenna position" info in Local register setting for FW reading, because FW may not ready at power on */
- if (btcoexist->chip_interface == BTC_INTF_PCI)
- btcoexist->btc_write_local_reg_1byte(btcoexist, 0x3e0, u8tmp);
- else if (btcoexist->chip_interface == BTC_INTF_USB)
- btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp);
- else if (btcoexist->chip_interface == BTC_INTF_SDIO)
- btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, u8tmp);
-
- /* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */
- halbtc8723d2ant_enable_gnt_to_gpio(btcoexist, FALSE);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** LTE coex Reg 0x38 (Power-On) = 0x%x**********\n",
- halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x38));
- BTC_TRACE(trace_buf);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ********** MAC Reg 0x70/ BB Reg 0x948 (Power-On) = 0x%x / 0x%x**********\n",
- btcoexist->btc_read_4byte(btcoexist, 0x70), btcoexist->btc_read_2byte(btcoexist, 0x948));
- BTC_TRACE(trace_buf);
-}
-
-void ex_halbtc8723d2ant_pre_load_firmware(IN struct btc_coexist *btcoexist)
-{
- struct btc_board_info *board_info = &btcoexist->board_info;
- u8 u8tmp = 0x4; /* Set BIT2 by default since it's 2ant case */
-
- /* */
- /* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */
- /* Local setting bit define */
- /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */
- /* BIT1: "0" for internal switch; "1" for external switch */
- /* BIT2: "0" for one antenna; "1" for two antenna */
- /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */
- if (btcoexist->chip_interface == BTC_INTF_USB) {
- /* fixed at S0 for USB interface */
- u8tmp |= 0x1; /* antenna inverse */
- btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp);
- } else {
- /* for PCIE and SDIO interface, we check efuse 0xc3[6] */
- if (board_info->single_ant_path == 0) {
- } else if (board_info->single_ant_path == 1) {
- /* set to S0 */
- u8tmp |= 0x1; /* antenna inverse */
- }
-
- if (btcoexist->chip_interface == BTC_INTF_PCI)
- btcoexist->btc_write_local_reg_1byte(btcoexist, 0x3e0,
- u8tmp);
- else if (btcoexist->chip_interface == BTC_INTF_SDIO)
- btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60,
- u8tmp);
- }
-}
-
-
-void ex_halbtc8723d2ant_init_hw_config(IN struct btc_coexist *btcoexist,
- IN boolean wifi_only)
-{
- btcoexist->stop_coex_dm = false;
- halbtc8723d2ant_init_hw_config(btcoexist, wifi_only);
-}
-
-void ex_halbtc8723d2ant_init_coex_dm(IN struct btc_coexist *btcoexist)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Coex Mechanism Init!!\n");
- BTC_TRACE(trace_buf);
-
- btcoexist->stop_coex_dm = false;
-
- halbtc8723d2ant_action_init_coex_dm(btcoexist);
-}
-
-void ex_halbtc8723d2ant_display_coex_info(IN struct btc_coexist *btcoexist)
-{
- struct btc_board_info *board_info = &btcoexist->board_info;
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
- u8 *cli_buf = btcoexist->cli_buf;
- u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0;
- u32 u32tmp[4];
- u16 u16tmp[4];
- u32 fa_of_dm, fa_cck;
- u32 fw_ver = 0, bt_patch_ver = 0;
- static u8 pop_report_in_10s = 0;
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ============[BT Coexist info]============");
- CL_PRINTF(cli_buf);
-
- if (btcoexist->manual_control) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ============[Under Manual Control]============");
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n ==========================================");
- CL_PRINTF(cli_buf);
- }
-
- if (psd_scan->ant_det_try_count == 0) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %s",
- "Ant PG Num/ Mech/ Pos",
- board_info->pg_ant_num, board_info->btdm_ant_num,
- (board_info->btdm_ant_pos == 1 ? "S1" : "S0"));
- CL_PRINTF(cli_buf);
- } else {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %d/ %d/ %s (retry=%d/fail=%d/result=%d)",
- "Ant PG Num/ Mech(Ant_Det)/ Pos",
- board_info->pg_ant_num, board_info->btdm_ant_num_by_ant_det,
- (board_info->btdm_ant_pos == 1 ? "S1" : "S0"),
- psd_scan->ant_det_try_count, psd_scan->ant_det_fail_count,
- psd_scan->ant_det_result);
- CL_PRINTF(cli_buf);
-
- if (board_info->btdm_ant_det_finish) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
- "Ant Det PSD Value",
- psd_scan->ant_det_peak_val);
- CL_PRINTF(cli_buf);
- }
- }
-
-
- btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
- btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %d_%x/ 0x%x/ 0x%x(%d)/ %c",
- "Version Coex/ Fw/ Patch/ Cut",
- glcoex_ver_date_8723d_2ant, glcoex_ver_8723d_2ant, fw_ver,
- bt_patch_ver, bt_patch_ver, coex_sta->cut_version + 65);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ",
- "Wifi channel informed to BT",
- coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
- coex_dm->wifi_chnl_info[2]);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d ",
- "Isolation/WL_Thres/BT_Thres",
- coex_sta->isolation_btween_wb,
- coex_sta->wifi_coex_thres,
- coex_sta->bt_coex_thres);
- CL_PRINTF(cli_buf);
-
- /* wifi status */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Wifi Status]============");
- CL_PRINTF(cli_buf);
- btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[BT Status]============");
- CL_PRINTF(cli_buf);
-
- pop_report_in_10s++;
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d/ %d] ",
- "BT [status/ rssi/ retryCnt/ popCnt]",
- ((coex_sta->bt_disabled) ? ("disabled") : ((
- coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page")
- : ((BT_8723D_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
- coex_dm->bt_status) ? "non-connected idle" :
- ((BT_8723D_2ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)
- ? "connected-idle" : "busy")))),
- coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt,
- coex_sta->pop_event_cnt);
- CL_PRINTF(cli_buf);
-
- if (pop_report_in_10s >= 5) {
- coex_sta->pop_event_cnt = 0;
- pop_report_in_10s = 0;
- }
-
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %d / %d / %d / %d / %d / %d",
- "SCO/HID/PAN/A2DP/NameReq/WHQL",
- bt_link_info->sco_exist, bt_link_info->hid_exist,
- bt_link_info->pan_exist, bt_link_info->a2dp_exist,
- coex_sta->c2h_bt_remote_name_req,
- coex_sta->bt_whck_test);
- CL_PRINTF(cli_buf);
-
- bt_info_ext = coex_sta->bt_info_ext;
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %s / %d",
- "Role/A2DP Rate/Bitpool",
- ((bt_link_info->slave_role) ? "Slave" : "Master"),
- (bt_info_ext & BIT(0)) ? "BR" : "EDR", coex_sta->a2dp_bit_pool);
- CL_PRINTF(cli_buf);
-
- for (i = 0; i < BT_INFO_SRC_8723D_2ANT_MAX; i++) {
- if (coex_sta->bt_info_c2h_cnt[i]) {
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)",
- glbt_info_src_8723d_2ant[i],
- coex_sta->bt_info_c2h[i][0],
- coex_sta->bt_info_c2h[i][1],
- coex_sta->bt_info_c2h[i][2],
- coex_sta->bt_info_c2h[i][3],
- coex_sta->bt_info_c2h[i][4],
- coex_sta->bt_info_c2h[i][5],
- coex_sta->bt_info_c2h[i][6],
- coex_sta->bt_info_c2h_cnt[i]);
- CL_PRINTF(cli_buf);
- }
- }
-
- /* Sw mechanism */
- if (btcoexist->manual_control)
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[mechanism] (before Manual)============");
- else
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[mechanism]============");
-
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ 0x%x/ 0x%x ",
- "LowP-RA/ DecWLPwr/ DecBTPwr",
- (coex_dm->cur_low_penalty_ra ? "On" : "Off"),
- coex_dm->cur_fw_dac_swing_lvl,
- coex_dm->cur_bt_dec_pwr_lvl);
- CL_PRINTF(cli_buf);
-
- ps_tdma_case = coex_dm->cur_ps_tdma;
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (%s, %s)",
- "PS TDMA",
- coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],
- coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],
- coex_dm->ps_tdma_para[4], ps_tdma_case,
- (coex_dm->cur_ps_tdma_on ? "On" : "Off"),
- (coex_dm->is_switch_to_1dot5_ant ? "1.5Ant" : "2Ant"));
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
- "WL/BT Coex Table Type",
- coex_sta->coex_table_type);
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
- u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
- "0x6c0/0x6c4/0x6c8(coexTable)",
- u32tmp[0], u32tmp[1], u32tmp[2]);
- CL_PRINTF(cli_buf);
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
- "0x778/0x6cc/IgnWlanAct",
- u8tmp[0], u32tmp[0], coex_dm->cur_ignore_wlan_act);
- CL_PRINTF(cli_buf);
-
-
- u32tmp[0] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist,
- 0xa0);
- u32tmp[1] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist,
- 0xa4);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
- "LTE Coex Table W_L/B_L",
- u32tmp[0] & 0xffff, u32tmp[1] & 0xffff);
- CL_PRINTF(cli_buf);
-
-
- u32tmp[0] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist,
- 0xa8);
- u32tmp[1] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist,
- 0xac);
- u32tmp[2] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist,
- 0xb0);
- u32tmp[3] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist,
- 0xb4);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
- "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
- "LTE Break Table W_L/B_L/L_W/L_B",
- u32tmp[0] & 0xffff, u32tmp[1] & 0xffff,
- u32tmp[2] & 0xffff, u32tmp[3] & 0xffff);
- CL_PRINTF(cli_buf);
-
- /* Hw setting */
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
- "============[Hw setting]============");
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434);
- u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x",
- "0x430/0x434/0x42a/0x456",
- u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]);
- CL_PRINTF(cli_buf);
-
-
- u32tmp[0] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %s",
- "LTE CoexOn/Path Ctrl Owner",
- (int)((u32tmp[0] & BIT(7)) >> 7), ((u8tmp[0] & BIT(2)) ? "WL" : "BT"));
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
- "LTE 3Wire/OPMode/UART/UARTMode",
- (int)((u32tmp[0] & BIT(6)) >> 6), (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4),
- (int)((u32tmp[0] & BIT(3)) >> 3),
- (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0))));
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %s",
- "GNT_WL_SWCtrl/GNT_BT_SWCtrl/Dbg",
- (int)((u32tmp[0] & BIT(12)) >> 12), (int)((u32tmp[0] & BIT(14)) >> 14),
- ((u8tmp[0] & BIT(3)) ? "On" : "Off"));
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = halbtc8723d2ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
- "GNT_WL/GNT_BT/LTE_Busy/UART_Busy",
- (int)((u32tmp[0] & BIT(2)) >> 2), (int)((u32tmp[0] & BIT(3)) >> 3),
- (int)((u32tmp[0] & BIT(1)) >> 1), (int)(u32tmp[0] & BIT(0)));
- CL_PRINTF(cli_buf);
-
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
- "0x4c6[4]/0x40[5] (WL/BT PTA)",
- (int)((u8tmp[0] & BIT(4)) >> 4), (int)((u8tmp[1] & BIT(5)) >> 5));
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x953);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ %s",
- "0x550(bcn ctrl)/0x522/4-RxAGC",
- u32tmp[0], u8tmp[0], (u8tmp[1] & 0x2) ? "On" : "Off");
- CL_PRINTF(cli_buf);
-
- u32tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x948);
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x67);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xc50);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
- "0x948/ 0x67[7]/ 0xc50[7:0]",
- u32tmp[0],
- ((u8tmp[0] & 0x80) >> 7), u32tmp[1] & 0xff);
- CL_PRINTF(cli_buf);
-
-
- u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xda0);
- u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xda4);
- u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0xda8);
- u32tmp[3] = btcoexist->btc_read_4byte(btcoexist, 0xcf0);
-
- u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xa5b);
- u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xa5c);
-
- fa_of_dm = ((u32tmp[0] & 0xffff0000) >> 16) + ((u32tmp[1] & 0xffff0000)
- >> 16) + (u32tmp[1] & 0xffff) + (u32tmp[2] & 0xffff) +
- ((u32tmp[3] & 0xffff0000) >> 16) + (u32tmp[3] & 0xffff);
- fa_cck = (u8tmp[0] << 8) + u8tmp[1];
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
- "OFDM-CCA/OFDM-FA/CCK-FA",
- u32tmp[0] & 0xffff, fa_of_dm, fa_cck);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
- "CRC_OK CCK/11g/11n/11n-Agg",
- coex_sta->crc_ok_cck, coex_sta->crc_ok_11g,
- coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_agg);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
- "CRC_Err CCK/11g/11n/11n-Agg",
- coex_sta->crc_err_cck, coex_sta->crc_err_11g,
- coex_sta->crc_err_11n, coex_sta->crc_err_11n_agg);
- CL_PRINTF(cli_buf);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
- "0x770(high-pri rx/tx)",
- coex_sta->high_priority_rx, coex_sta->high_priority_tx);
- CL_PRINTF(cli_buf);
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
- "0x774(low-pri rx/tx)",
- coex_sta->low_priority_rx, coex_sta->low_priority_tx);
- CL_PRINTF(cli_buf);
-
- halbtc8723d2ant_read_score_board(btcoexist, &u16tmp[0]);
-
- CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %04x",
- "ScoreBoard[14:0] (from BT)", u16tmp[0]);
- CL_PRINTF(cli_buf);
-
- btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
-}
-
-
-void ex_halbtc8723d2ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type)
-{
- if (btcoexist->manual_control || btcoexist->stop_coex_dm)
- return;
-
- if (BTC_IPS_ENTER == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], IPS ENTER notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_ips = true;
- coex_sta->under_lps = false;
- halbtc8723d2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, false,
- true);
- halbtc8723d2ant_action_coex_all_off(btcoexist);
- } else if (BTC_IPS_LEAVE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], IPS LEAVE notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_ips = false;
- halbtc8723d2ant_init_hw_config(btcoexist, false);
- halbtc8723d2ant_action_init_coex_dm(btcoexist);
- halbtc8723d2ant_query_bt_info(btcoexist);
- }
-}
-
-void ex_halbtc8723d2ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type)
-{
- if (btcoexist->manual_control || btcoexist->stop_coex_dm)
- return;
-
- if (BTC_LPS_ENABLE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], LPS ENABLE notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_lps = true;
- coex_sta->under_ips = false;
- } else if (BTC_LPS_DISABLE == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], LPS DISABLE notify\n");
- BTC_TRACE(trace_buf);
- coex_sta->under_lps = false;
- }
-}
-
-void ex_halbtc8723d2ant_scan_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- u32 u32tmp;
- u8 u8tmpa, u8tmpb;
- boolean wifi_connected = false;
-
-
- if (btcoexist->manual_control ||
- btcoexist->stop_coex_dm)
- return;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
-
- halbtc8723d2ant_query_bt_info(btcoexist); /* this can't be removed for RF off_on event, or BT would dis-connect */
-
- if (BTC_SCAN_START == type) {
-
- if (!wifi_connected)
- coex_sta->wifi_is_high_pri_task = true;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCAN START notify\n");
- BTC_TRACE(trace_buf);
-
- halbtc8723d2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, false,
- false);
-
- halbtc8723d2ant_run_coexist_mechanism(btcoexist);
-
- } else if (BTC_SCAN_FINISH == type) {
-
- coex_sta->wifi_is_high_pri_task = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
- &coex_sta->scan_ap_num);
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], SCAN FINISH notify (Scan-AP = %d)\n", coex_sta->scan_ap_num);
- BTC_TRACE(trace_buf);
-
- halbtc8723d2ant_run_coexist_mechanism(btcoexist);
- }
-
-}
-
-void ex_halbtc8723d2ant_connect_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- if (btcoexist->manual_control ||
- btcoexist->stop_coex_dm ||
- coex_sta->bt_disabled)
- return;
-
- if (BTC_ASSOCIATE_START == type) {
-
- coex_sta->wifi_is_high_pri_task = true;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CONNECT START notify\n");
- BTC_TRACE(trace_buf);
-
- halbtc8723d2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, false,
- false);
-
- halbtc8723d2ant_run_coexist_mechanism(btcoexist);
-
- coex_dm->arp_cnt = 0;
-
- } else if (BTC_ASSOCIATE_FINISH == type) {
-
- coex_sta->wifi_is_high_pri_task = false;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], CONNECT FINISH notify\n");
- BTC_TRACE(trace_buf);
-
- halbtc8723d2ant_run_coexist_mechanism(btcoexist);
- }
-}
-
-void ex_halbtc8723d2ant_media_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- u8 h2c_parameter[3] = {0};
- u32 wifi_bw;
- u8 wifi_central_chnl;
- u8 ap_num = 0;
- boolean wifi_under_b_mode = false;
-
- if (btcoexist->manual_control ||
- btcoexist->stop_coex_dm ||
- coex_sta->bt_disabled)
- return;
-
- if (BTC_MEDIA_CONNECT == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], MEDIA connect notify\n");
- BTC_TRACE(trace_buf);
-
- halbtc8723d2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, false,
- false);
-
- /* psd_scan->ant_det_is_ant_det_available = TRUE; */
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
- &wifi_under_b_mode);
-
- /* Set CCK Tx/Rx high Pri except 11b mode */
- if (wifi_under_b_mode) {
- btcoexist->btc_write_1byte(btcoexist, 0x6cd,
- 0x00); /* CCK Tx */
- btcoexist->btc_write_1byte(btcoexist, 0x6cf,
- 0x00); /* CCK Rx */
- } else {
-
- btcoexist->btc_write_1byte(btcoexist, 0x6cd,
- 0x00); /* CCK Tx */
- btcoexist->btc_write_1byte(btcoexist, 0x6cf,
- 0x10); /* CCK Rx */
- }
-
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], MEDIA disconnect notify\n");
- BTC_TRACE(trace_buf);
-
- btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */
- btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */
- }
-
-
- halbtc8723d2ant_update_wifi_channel_info(btcoexist, type);
-}
-
-void ex_halbtc8723d2ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- boolean under_4way = false;
-
- if (btcoexist->manual_control ||
- btcoexist->stop_coex_dm ||
- coex_sta->bt_disabled)
- return;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
- &under_4way);
-
- if (under_4way) {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], specific Packet ---- under_4way!!\n");
- BTC_TRACE(trace_buf);
-
- coex_sta->wifi_is_high_pri_task = true;
- coex_sta->specific_pkt_period_cnt = 2;
-
- } else if (BTC_PACKET_ARP == type) {
-
- coex_dm->arp_cnt++;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], specific Packet ARP notify -cnt = %d\n", coex_dm->arp_cnt);
- BTC_TRACE(trace_buf);
-
- } else {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n", type);
- BTC_TRACE(trace_buf);
-
- coex_sta->wifi_is_high_pri_task = true;
- coex_sta->specific_pkt_period_cnt = 2;
- }
-
- if (coex_sta->wifi_is_high_pri_task)
- halbtc8723d2ant_run_coexist_mechanism(btcoexist);
-
-}
-
-void ex_halbtc8723d2ant_bt_info_notify(IN struct btc_coexist *btcoexist,
- IN u8 *tmp_buf, IN u8 length)
-{
- u8 bt_info = 0;
- u8 i, rsp_source = 0;
- boolean bt_busy = false, limited_dig = false;
- boolean wifi_connected = false;
-
- coex_sta->c2h_bt_info_req_sent = false;
-
- btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
- &wifi_connected);
-
- rsp_source = tmp_buf[0] & 0xf;
- if (rsp_source >= BT_INFO_SRC_8723D_2ANT_MAX)
- rsp_source = BT_INFO_SRC_8723D_2ANT_WIFI_FW;
- coex_sta->bt_info_c2h_cnt[rsp_source]++;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source,
- length);
- BTC_TRACE(trace_buf);
- for (i = 0; i < length; i++) {
- coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
- if (i == 1)
- bt_info = tmp_buf[i];
-
- if (i == length - 1) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n",
- tmp_buf[i]);
- BTC_TRACE(trace_buf);
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ",
- tmp_buf[i]);
- BTC_TRACE(trace_buf);
- }
- }
-
- if (BT_INFO_SRC_8723D_2ANT_WIFI_FW != rsp_source) {
-
- /* if 0xff, it means BT is under WHCK test */
- if (bt_info == 0xff)
- coex_sta->bt_whck_test = true;
- else
- coex_sta->bt_whck_test = false;
-
- coex_sta->bt_retry_cnt = /* [3:0] */
- coex_sta->bt_info_c2h[rsp_source][2] & 0xf;
-
- if (coex_sta->bt_retry_cnt >= 1)
- coex_sta->pop_event_cnt++;
-
- if (coex_sta->bt_info_c2h[rsp_source][2] & 0x80)
- coex_sta->bt_create_connection = true;
- else
- coex_sta->bt_create_connection = false;
-
- /* unit: %, value-100 to translate to unit: dBm */
- coex_sta->bt_rssi = coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10;
-
- if (coex_sta->bt_info_c2h[rsp_source][2] & 0x20)
- coex_sta->c2h_bt_remote_name_req = true;
- else
- coex_sta->c2h_bt_remote_name_req = false;
-
- if ((coex_sta->bt_info_c2h[rsp_source][1] & 0x49) == 0x49) {
- coex_sta->a2dp_bit_pool =
- coex_sta->bt_info_c2h[rsp_source][6];
- } else
- coex_sta->a2dp_bit_pool = 0;
-
- if (coex_sta->bt_info_c2h[rsp_source][1] & 0x9)
- coex_sta->acl_busy = true;
- else
- coex_sta->acl_busy = false;
-
- coex_sta->bt_info_ext =
- coex_sta->bt_info_c2h[rsp_source][4];
-
- /* Here we need to resend some wifi info to BT */
- /* because bt is reset and loss of the info. */
-
- if ((!btcoexist->manual_control) && (!btcoexist->stop_coex_dm)) {
-
- /* Re-Init */
- if ((coex_sta->bt_info_ext & BIT(1))) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n");
- BTC_TRACE(trace_buf);
- if (wifi_connected)
- ex_halbtc8723d2ant_media_status_notify(
- btcoexist, BTC_MEDIA_CONNECT);
- else
- ex_halbtc8723d2ant_media_status_notify(
- btcoexist, BTC_MEDIA_DISCONNECT);
- }
-
-
- /* If Ignore_WLanAct && not SetUp_Link */
- if ((coex_sta->bt_info_ext & BIT(3)) && (!(coex_sta->bt_info_ext & BIT(2)))) {
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n");
- BTC_TRACE(trace_buf);
- halbtc8723d2ant_ignore_wlan_act(btcoexist,
- FORCE_EXEC, false);
- }
- }
-
- /* check BIT2 first ==> check if bt is under inquiry or page scan */
- if (bt_info & BT_INFO_8723D_2ANT_B_INQ_PAGE)
- coex_sta->c2h_bt_inquiry_page = true;
- else
- coex_sta->c2h_bt_inquiry_page = false;
- }
-
- coex_sta->num_of_profile = 0;
-
- /* set link exist status */
- if (!(bt_info & BT_INFO_8723D_2ANT_B_CONNECTION)) {
- coex_sta->bt_link_exist = false;
- coex_sta->pan_exist = false;
- coex_sta->a2dp_exist = false;
- coex_sta->hid_exist = false;
- coex_sta->sco_exist = false;
- } else { /* connection exists */
- coex_sta->bt_link_exist = true;
- if (bt_info & BT_INFO_8723D_2ANT_B_FTP) {
- coex_sta->pan_exist = true;
- coex_sta->num_of_profile++;
- } else
- coex_sta->pan_exist = false;
-
- if (bt_info & BT_INFO_8723D_2ANT_B_A2DP) {
- coex_sta->a2dp_exist = true;
- coex_sta->num_of_profile++;
- } else
- coex_sta->a2dp_exist = false;
-
- if (bt_info & BT_INFO_8723D_2ANT_B_HID) {
- coex_sta->hid_exist = true;
- coex_sta->num_of_profile++;
- } else
- coex_sta->hid_exist = false;
-
- if (bt_info & BT_INFO_8723D_2ANT_B_SCO_ESCO) {
- coex_sta->sco_exist = true;
- coex_sta->num_of_profile++;
- } else
- coex_sta->sco_exist = false;
-
- }
-
- halbtc8723d2ant_update_bt_link_info(btcoexist);
-
- if (!(bt_info & BT_INFO_8723D_2ANT_B_CONNECTION)) {
- coex_dm->bt_status = BT_8723D_2ANT_BT_STATUS_NON_CONNECTED_IDLE;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n");
- BTC_TRACE(trace_buf);
- } else if (bt_info ==
- BT_INFO_8723D_2ANT_B_CONNECTION) { /* connection exists but no busy */
- coex_dm->bt_status = BT_8723D_2ANT_BT_STATUS_CONNECTED_IDLE;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n");
- BTC_TRACE(trace_buf);
- } else if ((bt_info & BT_INFO_8723D_2ANT_B_SCO_ESCO) ||
- (bt_info & BT_INFO_8723D_2ANT_B_SCO_BUSY)) {
- coex_dm->bt_status = BT_8723D_2ANT_BT_STATUS_SCO_BUSY;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n");
- BTC_TRACE(trace_buf);
- } else if (bt_info & BT_INFO_8723D_2ANT_B_ACL_BUSY) {
- coex_dm->bt_status = BT_8723D_2ANT_BT_STATUS_ACL_BUSY;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n");
- BTC_TRACE(trace_buf);
- } else {
- coex_dm->bt_status = BT_8723D_2ANT_BT_STATUS_MAX;
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n");
- BTC_TRACE(trace_buf);
- }
-
- if ((BT_8723D_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
- (BT_8723D_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
- (BT_8723D_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) {
- bt_busy = true;
- limited_dig = true;
- } else {
- bt_busy = false;
- limited_dig = false;
- }
-
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
-
- coex_dm->limited_dig = limited_dig;
- btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_LIMITED_DIG, &limited_dig);
-
- if (btcoexist->manual_control) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), No run_coexist_mechanism return for Manual CTRL<===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- if (btcoexist->stop_coex_dm) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], BtInfoNotify(), No run_coexist_mechanism return for Stop Coex DM <===\n");
- BTC_TRACE(trace_buf);
- return;
- }
-
- /* don't run coex mechanism while receve BTInfo if GNT_WL/GNT_BT control by SW */
- if (!coex_sta->gnt_control_by_PTA)
- return;
-
- halbtc8723d2ant_run_coexist_mechanism(btcoexist);
-}
-
-void ex_halbtc8723d2ant_rf_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n");
- BTC_TRACE(trace_buf);
-
- if (BTC_RF_ON == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RF is turned ON!!\n");
- BTC_TRACE(trace_buf);
-
- coex_sta->wl_rf_off_on_event = true;
- btcoexist->stop_coex_dm = false;
-
- halbtc8723d2ant_post_onoffstate_to_bt(btcoexist, TRUE);
- } else if (BTC_RF_OFF == type) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], RF is turned OFF!!\n");
- BTC_TRACE(trace_buf);
-
- halbtc8723d2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, false,
- true);
- halbtc8723d2ant_action_coex_all_off(btcoexist);
- halbtc8723d2ant_post_onoffstate_to_bt(btcoexist, FALSE);
- btcoexist->stop_coex_dm = true;
- coex_sta->wl_rf_off_on_event = false;
-
- }
-}
-
-void ex_halbtc8723d2ant_halt_notify(IN struct btc_coexist *btcoexist)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n");
- BTC_TRACE(trace_buf);
-
- halbtc8723d2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN, false,
- true);
-
- ex_halbtc8723d2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
-
- halbtc8723d2ant_enable_gnt_to_gpio(btcoexist, FALSE);
-
- halbtc8723d2ant_post_onoffstate_to_bt(btcoexist, FALSE);
-}
-
-void ex_halbtc8723d2ant_pnp_notify(IN struct btc_coexist *btcoexist,
- IN u8 pnp_state)
-{
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n");
- BTC_TRACE(trace_buf);
-
- if (BTC_WIFI_PNP_SLEEP == pnp_state) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Pnp notify to SLEEP\n");
- BTC_TRACE(trace_buf);
-
- /* Sinda 20150819, workaround for driver skip leave IPS/LPS to speed up sleep time. */
- /* Driver do not leave IPS/LPS when driver is going to sleep, so BTCoexistence think wifi is still under IPS/LPS */
- /* BT should clear UnderIPS/UnderLPS state to avoid mismatch state after wakeup. */
- coex_sta->under_ips = false;
- coex_sta->under_lps = false;
-
- halbtc8723d2ant_enable_gnt_to_gpio(btcoexist, FALSE);
- halbtc8723d2ant_post_onoffstate_to_bt(btcoexist, FALSE);
- } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], Pnp notify to WAKE UP\n");
- BTC_TRACE(trace_buf);
-
- halbtc8723d2ant_post_onoffstate_to_bt(btcoexist, TRUE);
- }
-}
-
-void ex_halbtc8723d2ant_periodical(IN struct btc_coexist *btcoexist)
-{
- struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
-
-#if (BT_AUTO_REPORT_ONLY_8723D_2ANT == 0)
- halbtc8723d2ant_query_bt_info(btcoexist);
-#endif
-
- halbtc8723d2ant_monitor_bt_ctr(btcoexist);
- halbtc8723d2ant_monitor_wifi_ctr(btcoexist);
- halbtc8723d2ant_monitor_bt_enable_disable(btcoexist);
-
- /* for 4-way, DHCP, EAPOL packet */
- if (coex_sta->specific_pkt_period_cnt > 0) {
-
- coex_sta->specific_pkt_period_cnt--;
-
- if ((coex_sta->specific_pkt_period_cnt == 0) && (coex_sta->wifi_is_high_pri_task))
- coex_sta->wifi_is_high_pri_task = false;
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "[BTCoex], ***************** Hi-Pri Task = %s*****************\n", (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"));
- BTC_TRACE(trace_buf);
-
- }
-
- if (halbtc8723d2ant_is_wifibt_status_changed(btcoexist))
- halbtc8723d2ant_run_coexist_mechanism(btcoexist);
-}
-
-
-void ex_halbtc8723d2ant_antenna_detection(IN struct btc_coexist *btcoexist,
- IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
-{
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx Ext Call AntennaDetect()!!\n");
- BTC_TRACE(trace_buf);
-
-#if BT_8723D_2ANT_ANTDET_ENABLE
- static u32 ant_det_count = 0, ant_det_fail_count = 0;
- struct btc_board_info *board_info = &btcoexist->board_info;
- /*boolean scan, roam;*/
-
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx Call AntennaDetect()!!\n");
- BTC_TRACE(trace_buf);
-
- if (seconds == 0) {
- psd_scan->ant_det_try_count = 0;
- psd_scan->ant_det_fail_count = 0;
- ant_det_count = 0;
- ant_det_fail_count = 0;
- board_info->btdm_ant_det_finish = false;
- board_info->btdm_ant_num_by_ant_det = 1;
- return;
- }
-
- if (!board_info->btdm_ant_det_finish) {
- psd_scan->ant_det_inteval_count =
- psd_scan->ant_det_inteval_count + 2;
-
- if (psd_scan->ant_det_inteval_count >=
- BT_8723D_2ANT_ANTDET_RETRY_INTERVAL) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Timer is up, Try Detect!!\n");
- BTC_TRACE(trace_buf);
- halbtc8723d2ant_psd_antenna_detection_check(btcoexist);
-
- if (board_info->btdm_ant_det_finish) {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Success!!\n");
- BTC_TRACE(trace_buf);
-
-#if 0
- board_info->btdm_ant_det_finish = false;
-#endif
-
-#if 0
- if (board_info->btdm_ant_num_by_ant_det == 2)
- halbtc8723d2ant_mechanism_switch(
- btcoexist, true);
- else
- halbtc8723d2ant_mechanism_switch(
- btcoexist, false);
-#endif
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Fail!!\n");
- BTC_TRACE(trace_buf);
- }
- psd_scan->ant_det_inteval_count = 0;
- } else {
- BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
- "xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Timer is not up! (%d)\n",
- psd_scan->ant_det_inteval_count);
- BTC_TRACE(trace_buf);
- }
-
- }
-#endif
-
-
-}
-
-
-void ex_halbtc8723d2ant_display_ant_detection(IN struct btc_coexist *btcoexist)
-{
-
-#if BT_8723D_2ANT_ANTDET_ENABLE
- struct btc_board_info *board_info = &btcoexist->board_info;
-
- if (psd_scan->ant_det_try_count != 0) {
- halbtc8723d2ant_psd_show_antenna_detect_result(btcoexist);
-
- if (board_info->btdm_ant_det_finish)
- halbtc8723d2ant_psd_showdata(btcoexist);
- return;
- }
-#endif
-
-}
-
-
-#endif
-
-#endif /* #if (RTL8723D_SUPPORT == 1) */
diff --git a/hal/btc/halbtc8723d2ant.h b/hal/btc/halbtc8723d2ant.h
deleted file mode 100644
index 15a56ce..0000000
--- a/hal/btc/halbtc8723d2ant.h
+++ /dev/null
@@ -1,348 +0,0 @@
-
-#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
-
-#if (RTL8723D_SUPPORT == 1)
-
-/* *******************************************
- * The following is for 8723D 2Ant BT Co-exist definition
- * ******************************************* */
-#define BT_AUTO_REPORT_ONLY_8723D_2ANT 1
-
-
-#define BT_INFO_8723D_2ANT_B_FTP BIT(7)
-#define BT_INFO_8723D_2ANT_B_A2DP BIT(6)
-#define BT_INFO_8723D_2ANT_B_HID BIT(5)
-#define BT_INFO_8723D_2ANT_B_SCO_BUSY BIT(4)
-#define BT_INFO_8723D_2ANT_B_ACL_BUSY BIT(3)
-#define BT_INFO_8723D_2ANT_B_INQ_PAGE BIT(2)
-#define BT_INFO_8723D_2ANT_B_SCO_ESCO BIT(1)
-#define BT_INFO_8723D_2ANT_B_CONNECTION BIT(0)
-
-#define BTC_RSSI_COEX_THRESH_TOL_8723D_2ANT 2
-
-
-#define BT_8723D_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 80 /* unit: % WiFi RSSI Threshold for 2-Ant free-run/2-Ant TDMA translation, default = 42 */
-#define BT_8723D_2ANT_BT_RSSI_COEXSWITCH_THRES1 80 /* unit: % BT RSSI Threshold for 2-Ant free-run/2-Ant TDMA translation, default = 46 */
-#define BT_8723D_2ANT_WIFI_RSSI_COEXSWITCH_THRES2 80 /* unit: % WiFi RSSI Threshold for 1-Ant TDMA/1-Ant PS-TDMA translation, default = 42 */
-#define BT_8723D_2ANT_BT_RSSI_COEXSWITCH_THRES2 80 /* unit: % BT RSSI Threshold for 1-Ant TDMA/1-Ant PS-TDMA translation, default = 46 */
-#define BT_8723D_2ANT_DEFAULT_ISOLATION 15 /* unit: dB */
-#define BT_8723D_2ANT_WIFI_MAX_TX_POWER 15 /* unit: dBm */
-#define BT_8723D_2ANT_BT_MAX_TX_POWER 3 /* unit: dBm */
-#define BT_8723D_2ANT_WIFI_SIR_THRES1 -15 /* unit: dB */
-#define BT_8723D_2ANT_WIFI_SIR_THRES2 -30 /* unit: dB */
-#define BT_8723D_2ANT_BT_SIR_THRES1 -15 /* unit: dB */
-#define BT_8723D_2ANT_BT_SIR_THRES2 -30 /* unit: dB */
-
-
-/* for Antenna detection */
-#define BT_8723D_2ANT_ANTDET_PSDTHRES_BACKGROUND 50
-#define BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION 70
-#define BT_8723D_2ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION 52
-#define BT_8723D_2ANT_ANTDET_PSDTHRES_1ANT 40
-#define BT_8723D_2ANT_ANTDET_RETRY_INTERVAL 10 /* retry timer if ant det is fail, unit: second */
-#define BT_8723D_2ANT_ANTDET_SWEEPPOINT_DELAY 40000
-#define BT_8723D_2ANT_ANTDET_ENABLE 0
-#define BT_8723D_2ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE 0
-#define BT_8723D_2ANT_ANTDET_BTTXTIME 100
-#define BT_8723D_2ANT_ANTDET_BTTXCHANNEL 39
-
-#define BT_8723D_2ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT 30000
-
-enum bt_8723d_2ant_signal_state {
- BT_8723D_2ANT_SIG_STA_SET_TO_LOW = 0x0,
- BT_8723D_2ANT_SIG_STA_SET_BY_HW = 0x0,
- BT_8723D_2ANT_SIG_STA_SET_TO_HIGH = 0x1,
- BT_8723D_2ANT_SIG_STA_MAX
-};
-
-enum bt_8723d_2ant_path_ctrl_owner {
- BT_8723D_2ANT_PCO_BTSIDE = 0x0,
- BT_8723D_2ANT_PCO_WLSIDE = 0x1,
- BT_8723D_2ANT_PCO_MAX
-};
-
-enum bt_8723d_2ant_gnt_ctrl_type {
- BT_8723D_2ANT_GNT_TYPE_CTRL_BY_PTA = 0x0,
- BT_8723D_2ANT_GNT_TYPE_CTRL_BY_SW = 0x1,
- BT_8723D_2ANT_GNT_TYPE_MAX
-};
-
-enum bt_8723d_2ant_gnt_ctrl_block {
- BT_8723D_2ANT_GNT_BLOCK_RFC_BB = 0x0,
- BT_8723D_2ANT_GNT_BLOCK_RFC = 0x1,
- BT_8723D_2ANT_GNT_BLOCK_BB = 0x2,
- BT_8723D_2ANT_GNT_BLOCK_MAX
-};
-
-enum bt_8723d_2ant_lte_coex_table_type {
- BT_8723D_2ANT_CTT_WL_VS_LTE = 0x0,
- BT_8723D_2ANT_CTT_BT_VS_LTE = 0x1,
- BT_8723D_2ANT_CTT_MAX
-};
-
-enum bt_8723d_2ant_lte_break_table_type {
- BT_8723D_2ANT_LBTT_WL_BREAK_LTE = 0x0,
- BT_8723D_2ANT_LBTT_BT_BREAK_LTE = 0x1,
- BT_8723D_2ANT_LBTT_LTE_BREAK_WL = 0x2,
- BT_8723D_2ANT_LBTT_LTE_BREAK_BT = 0x3,
- BT_8723D_2ANT_LBTT_MAX
-};
-
-enum bt_info_src_8723d_2ant {
- BT_INFO_SRC_8723D_2ANT_WIFI_FW = 0x0,
- BT_INFO_SRC_8723D_2ANT_BT_RSP = 0x1,
- BT_INFO_SRC_8723D_2ANT_BT_ACTIVE_SEND = 0x2,
- BT_INFO_SRC_8723D_2ANT_MAX
-};
-
-enum bt_8723d_2ant_bt_status {
- BT_8723D_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
- BT_8723D_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
- BT_8723D_2ANT_BT_STATUS_INQ_PAGE = 0x2,
- BT_8723D_2ANT_BT_STATUS_ACL_BUSY = 0x3,
- BT_8723D_2ANT_BT_STATUS_SCO_BUSY = 0x4,
- BT_8723D_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
- BT_8723D_2ANT_BT_STATUS_MAX
-};
-
-enum bt_8723d_2ant_coex_algo {
- BT_8723D_2ANT_COEX_ALGO_UNDEFINED = 0x0,
- BT_8723D_2ANT_COEX_ALGO_SCO = 0x1,
- BT_8723D_2ANT_COEX_ALGO_HID = 0x2,
- BT_8723D_2ANT_COEX_ALGO_A2DP = 0x3,
- BT_8723D_2ANT_COEX_ALGO_A2DP_PANHS = 0x4,
- BT_8723D_2ANT_COEX_ALGO_PANEDR = 0x5,
- BT_8723D_2ANT_COEX_ALGO_PANHS = 0x6,
- BT_8723D_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
- BT_8723D_2ANT_COEX_ALGO_PANEDR_HID = 0x8,
- BT_8723D_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
- BT_8723D_2ANT_COEX_ALGO_HID_A2DP = 0xa,
- BT_8723D_2ANT_COEX_ALGO_NOPROFILEBUSY = 0xb,
- BT_8723D_2ANT_COEX_ALGO_MAX
-};
-
-struct coex_dm_8723d_2ant {
- /* fw mechanism */
- u8 pre_bt_dec_pwr_lvl;
- u8 cur_bt_dec_pwr_lvl;
- u8 pre_fw_dac_swing_lvl;
- u8 cur_fw_dac_swing_lvl;
- boolean cur_ignore_wlan_act;
- boolean pre_ignore_wlan_act;
- u8 pre_ps_tdma;
- u8 cur_ps_tdma;
- u8 ps_tdma_para[5];
- u8 ps_tdma_du_adj_type;
- boolean reset_tdma_adjust;
- boolean auto_tdma_adjust;
- boolean pre_ps_tdma_on;
- boolean cur_ps_tdma_on;
- boolean pre_bt_auto_report;
- boolean cur_bt_auto_report;
-
- /* sw mechanism */
- boolean pre_rf_rx_lpf_shrink;
- boolean cur_rf_rx_lpf_shrink;
- u32 bt_rf_0x1e_backup;
- boolean pre_low_penalty_ra;
- boolean cur_low_penalty_ra;
- boolean pre_dac_swing_on;
- u32 pre_dac_swing_lvl;
- boolean cur_dac_swing_on;
- u32 cur_dac_swing_lvl;
- boolean pre_adc_back_off;
- boolean cur_adc_back_off;
- boolean pre_agc_table_en;
- boolean cur_agc_table_en;
- u32 pre_val0x6c0;
- u32 cur_val0x6c0;
- u32 pre_val0x6c4;
- u32 cur_val0x6c4;
- u32 pre_val0x6c8;
- u32 cur_val0x6c8;
- u8 pre_val0x6cc;
- u8 cur_val0x6cc;
- boolean limited_dig;
-
- /* algorithm related */
- u8 pre_algorithm;
- u8 cur_algorithm;
- u8 bt_status;
- u8 wifi_chnl_info[3];
-
- boolean need_recover0x948;
- u32 backup0x948;
-
- u8 pre_lps;
- u8 cur_lps;
- u8 pre_rpwm;
- u8 cur_rpwm;
-
- boolean is_switch_to_1dot5_ant;
- u8 switch_thres_offset;
- u32 arp_cnt;
-};
-
-struct coex_sta_8723d_2ant {
- boolean bt_disabled;
- boolean bt_link_exist;
- boolean sco_exist;
- boolean a2dp_exist;
- boolean hid_exist;
- boolean pan_exist;
-
- boolean under_lps;
- boolean under_ips;
- u32 high_priority_tx;
- u32 high_priority_rx;
- u32 low_priority_tx;
- u32 low_priority_rx;
- u8 bt_rssi;
- boolean bt_tx_rx_mask;
- u8 pre_bt_rssi_state;
- u8 pre_wifi_rssi_state[4];
- boolean c2h_bt_info_req_sent;
- u8 bt_info_c2h[BT_INFO_SRC_8723D_2ANT_MAX][10];
- u32 bt_info_c2h_cnt[BT_INFO_SRC_8723D_2ANT_MAX];
- boolean bt_whck_test;
- boolean c2h_bt_inquiry_page;
- boolean c2h_bt_remote_name_req;
- u8 bt_retry_cnt;
- u8 bt_info_ext;
- u32 pop_event_cnt;
- u8 scan_ap_num;
-
- u32 crc_ok_cck;
- u32 crc_ok_11g;
- u32 crc_ok_11n;
- u32 crc_ok_11n_agg;
-
- u32 crc_err_cck;
- u32 crc_err_11g;
- u32 crc_err_11n;
- u32 crc_err_11n_agg;
-
- u8 coex_table_type;
- boolean force_lps_on;
-
- u8 dis_ver_info_cnt;
-
- u8 a2dp_bit_pool;
- u8 cut_version;
-
- boolean concurrent_rx_mode_on;
-
- u16 score_board;
- u8 isolation_btween_wb; /* 0~ 50 */
- u8 wifi_coex_thres;
- u8 bt_coex_thres;
- u8 wifi_coex_thres2;
- u8 bt_coex_thres2;
-
- u8 num_of_profile;
- boolean acl_busy;
- boolean wl_rf_off_on_event;
- boolean bt_create_connection;
- boolean gnt_control_by_PTA;
- boolean wifi_is_high_pri_task;
- u32 specific_pkt_period_cnt;
-};
-
-#define BT_8723D_2ANT_ANTDET_PSD_POINTS 256 /* MAX:1024 */
-#define BT_8723D_2ANT_ANTDET_PSD_AVGNUM 1 /* MAX:3 */
-#define BT_8723D_2ANT_ANTDET_BUF_LEN 16
-
-struct psdscan_sta_8723d_2ant {
-
- u32 ant_det_bt_le_channel; /* BT LE Channel ex:2412 */
- u32 ant_det_bt_tx_time;
- u32 ant_det_pre_psdscan_peak_val;
- boolean ant_det_is_ant_det_available;
- u32 ant_det_psd_scan_peak_val;
- boolean ant_det_is_btreply_available;
- u32 ant_det_psd_scan_peak_freq;
-
- u8 ant_det_result;
- u8 ant_det_peak_val[BT_8723D_2ANT_ANTDET_BUF_LEN];
- u8 ant_det_peak_freq[BT_8723D_2ANT_ANTDET_BUF_LEN];
- u32 ant_det_try_count;
- u32 ant_det_fail_count;
- u32 ant_det_inteval_count;
- u32 ant_det_thres_offset;
-
- u32 real_cent_freq;
- s32 real_offset;
- u32 real_span;
-
- u32 psd_band_width; /* unit: Hz */
- u32 psd_point; /* 128/256/512/1024 */
- u32 psd_report[1024]; /* unit:dB (20logx), 0~255 */
- u32 psd_report_max_hold[1024]; /* unit:dB (20logx), 0~255 */
- u32 psd_start_point;
- u32 psd_stop_point;
- u32 psd_max_value_point;
- u32 psd_max_value;
- u32 psd_start_base;
- u32 psd_avg_num; /* 1/8/16/32 */
- u32 psd_gen_count;
- boolean is_psd_running;
- boolean is_psd_show_max_only;
-};
-
-
-/* *******************************************
- * The following is interface which will notify coex module.
- * ******************************************* */
-void ex_halbtc8723d2ant_power_on_setting(IN struct btc_coexist *btcoexist);
-void ex_halbtc8723d2ant_pre_load_firmware(IN struct btc_coexist *btcoexist);
-void ex_halbtc8723d2ant_init_hw_config(IN struct btc_coexist *btcoexist,
- IN boolean wifi_only);
-void ex_halbtc8723d2ant_init_coex_dm(IN struct btc_coexist *btcoexist);
-void ex_halbtc8723d2ant_ips_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8723d2ant_lps_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8723d2ant_scan_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8723d2ant_connect_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8723d2ant_media_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8723d2ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8723d2ant_bt_info_notify(IN struct btc_coexist *btcoexist,
- IN u8 *tmp_buf, IN u8 length);
-void ex_halbtc8723d2ant_rf_status_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
-void ex_halbtc8723d2ant_halt_notify(IN struct btc_coexist *btcoexist);
-void ex_halbtc8723d2ant_pnp_notify(IN struct btc_coexist *btcoexist,
- IN u8 pnp_state);
-void ex_halbtc8723d2ant_periodical(IN struct btc_coexist *btcoexist);
-void ex_halbtc8723d2ant_display_coex_info(IN struct btc_coexist *btcoexist);
-void ex_halbtc8723d2ant_antenna_detection(IN struct btc_coexist *btcoexist,
- IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds);
-void ex_halbtc8723d2ant_display_ant_detection(IN struct btc_coexist *btcoexist);
-
-
-#else
-#define ex_halbtc8723d2ant_power_on_setting(btcoexist)
-#define ex_halbtc8723d2ant_pre_load_firmware(btcoexist)
-#define ex_halbtc8723d2ant_init_hw_config(btcoexist, wifi_only)
-#define ex_halbtc8723d2ant_init_coex_dm(btcoexist)
-#define ex_halbtc8723d2ant_ips_notify(btcoexist, type)
-#define ex_halbtc8723d2ant_lps_notify(btcoexist, type)
-#define ex_halbtc8723d2ant_scan_notify(btcoexist, type)
-#define ex_halbtc8723d2ant_connect_notify(btcoexist, type)
-#define ex_halbtc8723d2ant_media_status_notify(btcoexist, type)
-#define ex_halbtc8723d2ant_specific_packet_notify(btcoexist, type)
-#define ex_halbtc8723d2ant_bt_info_notify(btcoexist, tmp_buf, length)
-#define ex_halbtc8723d2ant_rf_status_notify(btcoexist, type)
-#define ex_halbtc8723d2ant_halt_notify(btcoexist)
-#define ex_halbtc8723d2ant_pnp_notify(btcoexist, pnp_state)
-#define ex_halbtc8723d2ant_periodical(btcoexist)
-#define ex_halbtc8723d2ant_display_coex_info(btcoexist)
-#define ex_halbtc8723d2ant_display_ant_detection(btcoexist)
-#define ex_halbtc8723d2ant_antenna_detection(btcoexist, centFreq, offset, span, seconds)
-#endif
-
-#endif
diff --git a/hal/btc/halbtc8822b1ant.c b/hal/btc/halbtc8822b1ant.c
new file mode 100644
index 0000000..d95168c
--- /dev/null
+++ b/hal/btc/halbtc8822b1ant.c
@@ -0,0 +1,6782 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+
+/* ************************************************************
+ * Description:
+ *
+ * This file is for RTL8822B Co-exist mechanism
+ *
+ * History
+ * 2012/11/15 Cosa first check in.
+ *
+ * ************************************************************ */
+
+/* ************************************************************
+ * include files
+ * ************************************************************ */
+/*only for rf4ce*/
+#include "mp_precomp.h"
+
+
+#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
+
+#if (RTL8822B_SUPPORT == 1)
+/* ************************************************************
+ * Global variables, these are static variables
+ * ************************************************************ */
+static u8 *trace_buf = &gl_btc_trace_buf[0];
+static struct coex_dm_8822b_1ant glcoex_dm_8822b_1ant;
+static struct coex_dm_8822b_1ant *coex_dm = &glcoex_dm_8822b_1ant;
+static struct coex_sta_8822b_1ant glcoex_sta_8822b_1ant;
+static struct coex_sta_8822b_1ant *coex_sta = &glcoex_sta_8822b_1ant;
+static struct psdscan_sta_8822b_1ant gl_psd_scan_8822b_1ant;
+static struct psdscan_sta_8822b_1ant *psd_scan = &gl_psd_scan_8822b_1ant;
+static struct rfe_type_8822b_1ant gl_rfe_type_8822b_1ant;
+static struct rfe_type_8822b_1ant *rfe_type = &gl_rfe_type_8822b_1ant;
+
+
+
+static const char *const glbt_info_src_8822b_1ant[] = {
+ "BT Info[wifi fw]",
+ "BT Info[bt rsp]",
+ "BT Info[bt auto report]",
+};
+
+u32 glcoex_ver_date_8822b_1ant = 20180427;
+u32 glcoex_ver_8822b_1ant = 0x59;
+u32 glcoex_ver_btdesired_8822b_1ant = 0x56;
+
+
+/* ************************************************************
+ * local function proto type if needed
+ * ************************************************************
+ * ************************************************************
+ * local function start with halbtc8822b1ant_
+ * ************************************************************ */
+static
+u8 halbtc8822b1ant_bt_rssi_state(IN struct btc_coexist *btcoexist,
+ u8 *ppre_bt_rssi_state, u8 level_num,
+ u8 rssi_thresh, u8 rssi_thresh1)
+{
+ s32 bt_rssi = 0;
+ u8 bt_rssi_state = *ppre_bt_rssi_state;
+
+ bt_rssi = coex_sta->bt_rssi;
+
+ if (level_num == 2) {
+ if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
+ (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
+ if (bt_rssi >= (rssi_thresh +
+ BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT))
+ bt_rssi_state = BTC_RSSI_STATE_HIGH;
+ else
+ bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+ } else {
+ if (bt_rssi < rssi_thresh)
+ bt_rssi_state = BTC_RSSI_STATE_LOW;
+ else
+ bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+ }
+ } else if (level_num == 3) {
+ if (rssi_thresh > rssi_thresh1) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT Rssi thresh error!!\n");
+ BTC_TRACE(trace_buf);
+ return *ppre_bt_rssi_state;
+ }
+
+ if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
+ (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
+ if (bt_rssi >= (rssi_thresh +
+ BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT))
+ bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
+ else
+ bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+ } else if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
+ (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
+ if (bt_rssi >= (rssi_thresh1 +
+ BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT))
+ bt_rssi_state = BTC_RSSI_STATE_HIGH;
+ else if (bt_rssi < rssi_thresh)
+ bt_rssi_state = BTC_RSSI_STATE_LOW;
+ else
+ bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
+ } else {
+ if (bt_rssi < rssi_thresh1)
+ bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
+ else
+ bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+ }
+ }
+
+ *ppre_bt_rssi_state = bt_rssi_state;
+
+ return bt_rssi_state;
+}
+
+
+static
+u8 halbtc8822b1ant_wifi_rssi_state(IN struct btc_coexist *btcoexist,
+ IN u8 *pprewifi_rssi_state, IN u8 level_num, IN u8 rssi_thresh,
+ IN u8 rssi_thresh1)
+{
+ s32 wifi_rssi = 0;
+ u8 wifi_rssi_state = *pprewifi_rssi_state;
+
+ btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
+
+ if (level_num == 2) {
+ if ((*pprewifi_rssi_state == BTC_RSSI_STATE_LOW) ||
+ (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
+ if (wifi_rssi >= (rssi_thresh +
+ BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT))
+ wifi_rssi_state = BTC_RSSI_STATE_HIGH;
+ else
+ wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+ } else {
+ if (wifi_rssi < rssi_thresh)
+ wifi_rssi_state = BTC_RSSI_STATE_LOW;
+ else
+ wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+ }
+ } else if (level_num == 3) {
+ if (rssi_thresh > rssi_thresh1) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], wifi RSSI thresh error!!\n");
+ BTC_TRACE(trace_buf);
+ return *pprewifi_rssi_state;
+ }
+
+ if ((*pprewifi_rssi_state == BTC_RSSI_STATE_LOW) ||
+ (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
+ if (wifi_rssi >= (rssi_thresh +
+ BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT))
+ wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
+ else
+ wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+ } else if ((*pprewifi_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
+ (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
+ if (wifi_rssi >= (rssi_thresh1 +
+ BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT))
+ wifi_rssi_state = BTC_RSSI_STATE_HIGH;
+ else if (wifi_rssi < rssi_thresh)
+ wifi_rssi_state = BTC_RSSI_STATE_LOW;
+ else
+ wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
+ } else {
+ if (wifi_rssi < rssi_thresh1)
+ wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
+ else
+ wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+ }
+ }
+
+ *pprewifi_rssi_state = wifi_rssi_state;
+
+ return wifi_rssi_state;
+}
+
+/*
+ * rx agg size setting :
+ * 1: TRUE / don't care / don't care
+ * max: FALSE / FALSE / don't care
+ * 7: FALSE / TRUE / 7
+ */
+
+static
+void halbtc8822b1ant_limited_rx(IN struct btc_coexist *btcoexist,
+ IN boolean force_exec, IN boolean rej_ap_agg_pkt,
+ IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size)
+{
+ boolean reject_rx_agg = rej_ap_agg_pkt;
+ boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size;
+ u8 rx_agg_size = agg_buf_size;
+
+ /* ============================================ */
+ /* Rx Aggregation related setting */
+ /* ============================================ */
+ btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT,
+ &reject_rx_agg);
+ /* decide BT control aggregation buf size or not */
+ btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE,
+ &bt_ctrl_rx_agg_size);
+ /* aggregation buf size, only work when BT control Rx aggregation size*/
+ btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size);
+ /* real update aggregation setting */
+ btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
+
+
+}
+
+void halbtc8822b1ant_query_bt_info(IN struct btc_coexist *btcoexist)
+{
+ u8 h2c_parameter[1] = {0};
+
+ if (coex_sta->bt_disabled) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], No query BT info because BT is disabled!\n");
+ BTC_TRACE(trace_buf);
+ return;
+ }
+
+
+ h2c_parameter[0] |= BIT(0); /* trigger */
+
+ btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter);
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], WL query BT info!!\n");
+ BTC_TRACE(trace_buf);
+}
+
+
+
+static
+void halbtc8822b1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist)
+{
+ u32 reg_hp_txrx, reg_lp_txrx, u32tmp;
+ u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
+ static u8 num_of_bt_counter_chk = 0, cnt_slave = 0, cnt_autoslot_hang = 0;
+ struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+
+ reg_hp_txrx = 0x770;
+ reg_lp_txrx = 0x774;
+
+ u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
+ reg_hp_tx = u32tmp & MASKLWORD;
+ reg_hp_rx = (u32tmp & MASKHWORD) >> 16;
+
+ u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
+ reg_lp_tx = u32tmp & MASKLWORD;
+ reg_lp_rx = (u32tmp & MASKHWORD) >> 16;
+
+ coex_sta->high_priority_tx = reg_hp_tx;
+ coex_sta->high_priority_rx = reg_hp_rx;
+ coex_sta->low_priority_tx = reg_lp_tx;
+ coex_sta->low_priority_rx = reg_lp_rx;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n",
+ reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx);
+ BTC_TRACE(trace_buf);
+
+ /* reset counter */
+ btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
+
+ if ((coex_sta->low_priority_tx > 1150) &&
+ (!coex_sta->c2h_bt_inquiry_page))
+ coex_sta->pop_event_cnt++;
+
+ if ((coex_sta->low_priority_rx >= 1150) &&
+ (coex_sta->low_priority_rx >= coex_sta->low_priority_tx)
+ && (!coex_sta->under_ips) &&
+ (!coex_sta->c2h_bt_inquiry_page) &&
+ (coex_sta->bt_link_exist)) {
+ if (cnt_slave >= 3) {
+ bt_link_info->slave_role = TRUE;
+ cnt_slave = 3;
+ } else {
+ cnt_slave++;
+ }
+ } else {
+ if (cnt_slave == 0) {
+ bt_link_info->slave_role = FALSE;
+ cnt_slave = 0;
+ } else {
+ cnt_slave--;
+ }
+
+ }
+
+ if (coex_sta->is_tdma_btautoslot) {
+ if ((coex_sta->low_priority_tx >= 1300) &&
+ (coex_sta->low_priority_rx <= 150)) {
+ if (cnt_autoslot_hang >= 2) {
+ coex_sta->is_tdma_btautoslot_hang = TRUE;
+ cnt_autoslot_hang = 2;
+ } else
+ cnt_autoslot_hang++;
+ } else {
+ if (cnt_autoslot_hang == 0) {
+ coex_sta->is_tdma_btautoslot_hang = FALSE;
+ cnt_autoslot_hang = 0;
+ } else
+ cnt_autoslot_hang--;
+ }
+ }
+
+ if (bt_link_info->hid_only) {
+ if (coex_sta->low_priority_tx > 50)
+ coex_sta->is_hid_low_pri_tx_overhead = true;
+ else
+ coex_sta->is_hid_low_pri_tx_overhead = false;
+ }
+
+ if ((coex_sta->high_priority_tx == 0) &&
+ (coex_sta->high_priority_rx == 0) &&
+ (coex_sta->low_priority_tx == 0) &&
+ (coex_sta->low_priority_rx == 0)) {
+ num_of_bt_counter_chk++;
+
+ if (num_of_bt_counter_chk >= 3) {
+ halbtc8822b1ant_query_bt_info(
+ btcoexist);
+ num_of_bt_counter_chk = 0;
+ }
+ }
+
+}
+
+
+void halbtc8822b1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist)
+{
+ s32 wifi_rssi = 0;
+ boolean wifi_busy = FALSE, wifi_under_b_mode = FALSE,
+ wifi_scan = FALSE;
+ boolean bt_idle = FALSE, wl_idle = FALSE;
+ static u8 cck_lock_counter = 0, wl_noisy_count0 = 0,
+ wl_noisy_count1 = 3, wl_noisy_count2 = 0;
+ u32 total_cnt, reg_val1, reg_val2, cnt_cck;
+ static u8 cnt = 0, cnt_ccklocking = 0;
+ u8 h2c_parameter[1] = {0};
+ struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+ /* Only enable for windows becaus 8821cu H2C 0x69 unknown fail @ linux */
+ if (btcoexist->chip_interface != BTC_INTF_USB) {
+ /*send h2c to query WL FW dbg info */
+ if (((coex_dm->cur_ps_tdma_on) && (coex_sta->force_lps_ctrl)) ||
+ ((coex_sta->acl_busy) && (bt_link_info->a2dp_exist))) {
+ h2c_parameter[0] = 0x8;
+ btcoexist->btc_fill_h2c(btcoexist, 0x69, 1, h2c_parameter);
+ }
+ }
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+ btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
+ &wifi_under_b_mode);
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan);
+
+ coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+ PHYDM_INFO_CRC32_OK_CCK);
+ coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+ PHYDM_INFO_CRC32_OK_LEGACY);
+ coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+ PHYDM_INFO_CRC32_OK_HT);
+ coex_sta->crc_ok_11n_vht = btcoexist->btc_phydm_query_PHY_counter(
+ btcoexist, PHYDM_INFO_CRC32_OK_VHT);
+
+ coex_sta->crc_err_cck = btcoexist->btc_phydm_query_PHY_counter(
+ btcoexist, PHYDM_INFO_CRC32_ERROR_CCK);
+ coex_sta->crc_err_11g = btcoexist->btc_phydm_query_PHY_counter(
+ btcoexist, PHYDM_INFO_CRC32_ERROR_LEGACY);
+ coex_sta->crc_err_11n = btcoexist->btc_phydm_query_PHY_counter(
+ btcoexist, PHYDM_INFO_CRC32_ERROR_HT);
+ coex_sta->crc_err_11n_vht = btcoexist->btc_phydm_query_PHY_counter(
+ btcoexist, PHYDM_INFO_CRC32_ERROR_VHT);
+
+ /* CCK lock identification */
+ if (coex_sta->cck_lock)
+ cnt_ccklocking++;
+ else if (cnt_ccklocking != 0)
+ cnt_ccklocking--;
+
+ if (cnt_ccklocking >= 3) {
+ cnt_ccklocking = 3;
+ coex_sta->cck_lock_ever = TRUE;
+ }
+
+ /* WiFi environment noisy identification */
+ cnt_cck = coex_sta->crc_ok_cck + coex_sta->crc_err_cck;
+
+ if ((!wifi_busy) && (!coex_sta->cck_lock)) {
+ if (cnt_cck > 250) {
+ if (wl_noisy_count2 < 3)
+ wl_noisy_count2++;
+
+ if (wl_noisy_count2 == 3) {
+ wl_noisy_count0 = 0;
+ wl_noisy_count1 = 0;
+ }
+
+ } else if (cnt_cck < 100) {
+ if (wl_noisy_count0 < 3)
+ wl_noisy_count0++;
+
+ if (wl_noisy_count0 == 3) {
+ wl_noisy_count1 = 0;
+ wl_noisy_count2 = 0;
+ }
+
+ } else {
+ if (wl_noisy_count1 < 3)
+ wl_noisy_count1++;
+
+ if (wl_noisy_count1 == 3) {
+ wl_noisy_count0 = 0;
+ wl_noisy_count2 = 0;
+ }
+ }
+
+ if (wl_noisy_count2 == 3)
+ coex_sta->wl_noisy_level = 2;
+ else if (wl_noisy_count1 == 3)
+ coex_sta->wl_noisy_level = 1;
+ else
+ coex_sta->wl_noisy_level = 0;
+ }
+
+}
+
+
+static
+boolean halbtc8822b1ant_is_wifibt_status_changed(IN struct btc_coexist *btcoexist)
+{
+ static boolean pre_wifi_busy = FALSE, pre_under_4way = FALSE,
+ pre_bt_hs_on = FALSE, pre_rf4ce_enabled = FALSE, pre_bt_off = FALSE,
+ pre_bt_slave = FALSE, pre_hid_low_pri_tx_overhead = FALSE,
+ pre_wifi_under_lps = FALSE, pre_bt_setup_link = FALSE;
+ static u8 pre_hid_busy_num = 0, pre_wl_noisy_level = 0;
+ boolean wifi_busy = FALSE, under_4way = FALSE, bt_hs_on = FALSE, rf4ce_enabled = FALSE;
+ boolean wifi_connected = FALSE;
+ struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+ static u8 cnt_wifi_busytoidle = 0;
+ u32 wifi_link_status = 0, num_of_wifi_link = 0;
+ static u32 pre_num_of_wifi_link = 0;
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected);
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &under_4way);
+ btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
+ &wifi_link_status);
+
+ if (wifi_busy) {
+ coex_sta->gl_wifi_busy = TRUE;
+ cnt_wifi_busytoidle = 3;
+ } else {
+ if ((coex_sta->gl_wifi_busy) && (cnt_wifi_busytoidle > 0))
+ cnt_wifi_busytoidle--;
+ else if (cnt_wifi_busytoidle == 0)
+ coex_sta->gl_wifi_busy = FALSE;
+ }
+
+ if (coex_sta->bt_disabled != pre_bt_off) {
+ pre_bt_off = coex_sta->bt_disabled;
+
+ if (coex_sta->bt_disabled)
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT is disabled !!\n");
+ else
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT is enabled !!\n");
+
+ BTC_TRACE(trace_buf);
+
+ coex_sta->bt_coex_supported_feature = 0;
+ coex_sta->bt_coex_supported_version = 0;
+ coex_sta->bt_ble_scan_type = 0;
+ coex_sta->bt_ble_scan_para[0] = 0;
+ coex_sta->bt_ble_scan_para[1] = 0;
+ coex_sta->bt_ble_scan_para[2] = 0;
+ coex_sta->bt_reg_vendor_ac = 0xffff;
+ coex_sta->bt_reg_vendor_ae = 0xffff;
+ coex_sta->legacy_forbidden_slot = 0;
+ coex_sta->le_forbidden_slot = 0;
+ coex_sta->bt_a2dp_vendor_id = 0;
+ coex_sta->bt_a2dp_device_name = 0;
+ return TRUE;
+ }
+
+ num_of_wifi_link = wifi_link_status >> 16;
+
+ if (num_of_wifi_link != pre_num_of_wifi_link) {
+ pre_num_of_wifi_link = num_of_wifi_link;
+ return TRUE;
+ }
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_RF4CE_CONNECTED, &rf4ce_enabled);
+
+ if (rf4ce_enabled != pre_rf4ce_enabled) {
+ pre_rf4ce_enabled = rf4ce_enabled;
+
+ if (rf4ce_enabled)
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], rf4ce is enabled !!\n");
+ else
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], rf4ce is disabled !!\n");
+
+ BTC_TRACE(trace_buf);
+
+ return TRUE;
+ }
+
+ if (wifi_connected) {
+ if (wifi_busy != pre_wifi_busy) {
+ pre_wifi_busy = wifi_busy;
+ return TRUE;
+ }
+ if (under_4way != pre_under_4way) {
+ pre_under_4way = under_4way;
+ return TRUE;
+ }
+ if (bt_hs_on != pre_bt_hs_on) {
+ pre_bt_hs_on = bt_hs_on;
+ return TRUE;
+ }
+ if (coex_sta->wl_noisy_level != pre_wl_noisy_level) {
+ pre_wl_noisy_level = coex_sta->wl_noisy_level;
+ return TRUE;
+ }
+ if (coex_sta->under_lps != pre_wifi_under_lps) {
+ pre_wifi_under_lps = coex_sta->under_lps;
+ if (coex_sta->under_lps == TRUE)
+ return TRUE;
+ }
+ }
+
+ if (!coex_sta->bt_disabled) {
+ if (coex_sta->hid_busy_num != pre_hid_busy_num) {
+ pre_hid_busy_num = coex_sta->hid_busy_num;
+ return TRUE;
+ }
+
+ if (bt_link_info->slave_role != pre_bt_slave) {
+ pre_bt_slave = bt_link_info->slave_role;
+ return TRUE;
+ }
+
+ if (pre_hid_low_pri_tx_overhead != coex_sta->is_hid_low_pri_tx_overhead) {
+ pre_hid_low_pri_tx_overhead = coex_sta->is_hid_low_pri_tx_overhead;
+ return TRUE;
+ }
+
+ if (pre_bt_setup_link != coex_sta->is_setupLink) {
+ pre_bt_setup_link = coex_sta->is_setupLink;
+ return TRUE;
+ }
+ }
+
+ return FALSE;
+}
+
+
+
+void halbtc8822b1ant_update_bt_link_info(IN struct btc_coexist *btcoexist)
+{
+ struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+ boolean bt_hs_on = FALSE;
+ boolean bt_busy = FALSE;
+ u32 val = 0;
+ static u8 pre_num_of_profile = 0, cur_num_of_profile = 0, cnt = 0;
+ boolean increase_scan_dev_num = FALSE;
+ static u8 wd_cnt = 0;
+
+ if (++wd_cnt >= 3)
+ wd_cnt = 0;
+
+ if (coex_sta->is_ble_scan_en && (wd_cnt == 0)) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT ext info bit4 check, query BLE Scan type!!\n");
+ BTC_TRACE(trace_buf);
+ coex_sta->bt_ble_scan_type = btcoexist->btc_get_ble_scan_type_from_bt(
+ btcoexist);
+
+ if ((coex_sta->bt_ble_scan_type & 0x1) == 0x1)
+ coex_sta->bt_ble_scan_para[0] =
+ btcoexist->btc_get_ble_scan_para_from_bt(btcoexist,
+ 0x1);
+ if ((coex_sta->bt_ble_scan_type & 0x2) == 0x2)
+ coex_sta->bt_ble_scan_para[1] =
+ btcoexist->btc_get_ble_scan_para_from_bt(btcoexist,
+ 0x2);
+ if ((coex_sta->bt_ble_scan_type & 0x4) == 0x4)
+ coex_sta->bt_ble_scan_para[2] =
+ btcoexist->btc_get_ble_scan_para_from_bt(btcoexist,
+ 0x4);
+ }
+
+ coex_sta->num_of_profile = 0;
+
+ /* set link exist status */
+ if (!(coex_sta->bt_info & BT_INFO_8822B_1ANT_B_CONNECTION)) {
+ coex_sta->bt_link_exist = FALSE;
+ coex_sta->pan_exist = FALSE;
+ coex_sta->a2dp_exist = FALSE;
+ coex_sta->hid_exist = FALSE;
+ coex_sta->sco_exist = FALSE;
+ coex_sta->msft_mr_exist = FALSE;
+ } else { /* connection exists */
+ coex_sta->bt_link_exist = TRUE;
+ if (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_FTP) {
+ coex_sta->pan_exist = TRUE;
+ coex_sta->num_of_profile++;
+ } else
+ coex_sta->pan_exist = FALSE;
+
+ if (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_A2DP) {
+ coex_sta->a2dp_exist = TRUE;
+ coex_sta->num_of_profile++;
+ } else
+ coex_sta->a2dp_exist = FALSE;
+
+ if (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_HID) {
+ coex_sta->hid_exist = TRUE;
+ coex_sta->num_of_profile++;
+ } else
+ coex_sta->hid_exist = FALSE;
+
+ if (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_SCO_ESCO) {
+ coex_sta->sco_exist = TRUE;
+ coex_sta->num_of_profile++;
+ } else
+ coex_sta->sco_exist = FALSE;
+
+ if ((coex_sta->hid_busy_num == 0) && (coex_sta->hid_pair_cnt > 0))
+ coex_sta->msft_mr_exist = true;
+ else
+ coex_sta->msft_mr_exist = false;
+ }
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+
+ bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
+ bt_link_info->sco_exist = coex_sta->sco_exist;
+ bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
+ bt_link_info->pan_exist = coex_sta->pan_exist;
+ bt_link_info->hid_exist = coex_sta->hid_exist;
+ bt_link_info->acl_busy = coex_sta->acl_busy;
+
+ /* work around for HS mode. */
+ if (bt_hs_on) {
+ bt_link_info->pan_exist = TRUE;
+ bt_link_info->bt_link_exist = TRUE;
+ }
+
+ /* check if Sco only */
+ if (bt_link_info->sco_exist &&
+ !bt_link_info->a2dp_exist &&
+ !bt_link_info->pan_exist &&
+ !bt_link_info->hid_exist)
+ bt_link_info->sco_only = TRUE;
+ else
+ bt_link_info->sco_only = FALSE;
+
+ /* check if A2dp only */
+ if (!bt_link_info->sco_exist &&
+ bt_link_info->a2dp_exist &&
+ !bt_link_info->pan_exist &&
+ !bt_link_info->hid_exist)
+ bt_link_info->a2dp_only = TRUE;
+ else
+ bt_link_info->a2dp_only = FALSE;
+
+ /* check if Pan only */
+ if (!bt_link_info->sco_exist &&
+ !bt_link_info->a2dp_exist &&
+ bt_link_info->pan_exist &&
+ !bt_link_info->hid_exist)
+ bt_link_info->pan_only = TRUE;
+ else
+ bt_link_info->pan_only = FALSE;
+
+ /* check if Hid only */
+ if (!bt_link_info->sco_exist &&
+ !bt_link_info->a2dp_exist &&
+ !bt_link_info->pan_exist &&
+ bt_link_info->hid_exist)
+ bt_link_info->hid_only = TRUE;
+ else
+ bt_link_info->hid_only = FALSE;
+
+ if (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_INQ_PAGE) {
+ coex_dm->bt_status = BT_8822B_1ANT_BT_STATUS_INQ_PAGE;
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BtInfoNotify(), BT Inq/page!!!\n");
+ } else if (!(coex_sta->bt_info & BT_INFO_8822B_1ANT_B_CONNECTION)) {
+ coex_dm->bt_status = BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE;
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n");
+ } else if (coex_sta->bt_info == BT_INFO_8822B_1ANT_B_CONNECTION) {
+ /* connection exists but no busy */
+
+ if (coex_sta->msft_mr_exist) {
+ coex_dm->bt_status = BT_8822B_1ANT_BT_STATUS_ACL_BUSY;
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BtInfoNotify(), BT ACL busy!!\n");
+ } else {
+ coex_dm->bt_status = BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE;
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n");
+ }
+ } else if (((coex_sta->bt_info & BT_INFO_8822B_1ANT_B_SCO_ESCO) ||
+ (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_SCO_BUSY)) &&
+ (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_ACL_BUSY)) {
+ coex_dm->bt_status = BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY;
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BtInfoNotify(), BT ACL SCO busy!!!\n");
+ } else if ((coex_sta->bt_info & BT_INFO_8822B_1ANT_B_SCO_ESCO) ||
+ (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_SCO_BUSY)) {
+ coex_dm->bt_status = BT_8822B_1ANT_BT_STATUS_SCO_BUSY;
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n");
+ } else if (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_ACL_BUSY) {
+ coex_dm->bt_status = BT_8822B_1ANT_BT_STATUS_ACL_BUSY;
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n");
+ } else {
+ coex_dm->bt_status = BT_8822B_1ANT_BT_STATUS_MAX;
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n");
+ }
+
+ BTC_TRACE(trace_buf);
+
+ if ((coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_ACL_BUSY) ||
+ (coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_SCO_BUSY) ||
+ (coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY)) {
+ bt_busy = TRUE;
+ increase_scan_dev_num = TRUE;
+ } else {
+ bt_busy = FALSE;
+ increase_scan_dev_num = FALSE;
+ }
+
+ btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
+ btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM,
+ &increase_scan_dev_num);
+
+ cur_num_of_profile = coex_sta->num_of_profile;
+
+ if (cur_num_of_profile != pre_num_of_profile)
+ cnt = 2;
+
+ if (bt_link_info->a2dp_exist) {
+
+ if (((coex_sta->bt_a2dp_vendor_id == 0) &&
+ (coex_sta->bt_a2dp_device_name == 0)) ||
+ (cur_num_of_profile != pre_num_of_profile)) {
+
+ btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_DEVICE_INFO, &val);
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BtInfoNotify(), get BT DEVICE_INFO = %x\n", val);
+ BTC_TRACE(trace_buf);
+
+ coex_sta->bt_a2dp_vendor_id = (u8)(val & 0xff);
+ coex_sta->bt_a2dp_device_name = (val & 0xffffff00) >> 8;
+ }
+
+ if (((coex_sta->legacy_forbidden_slot == 0) &&
+ (coex_sta->le_forbidden_slot == 0)) ||
+ (cur_num_of_profile != pre_num_of_profile) ||
+ (cnt > 0)) {
+
+ if (cnt > 0)
+ cnt--;
+
+ btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_FORBIDDEN_SLOT_VAL, &val);
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BtInfoNotify(), get BT FORBIDDEN_SLOT_VAL = %x\n", val);
+ BTC_TRACE(trace_buf);
+
+ coex_sta->legacy_forbidden_slot = (u16)(val & 0xffff);
+ coex_sta->le_forbidden_slot = (u16)((val & 0xffff0000) >> 16);
+ }
+ }
+
+ pre_num_of_profile = coex_sta->num_of_profile;
+}
+
+
+static
+void halbtc8822b1ant_update_wifi_channel_info(IN struct btc_coexist *btcoexist,
+ IN u8 type)
+{
+ u8 h2c_parameter[3] = {0}, i;
+ u32 wifi_bw;
+ u8 wifi_central_chnl = 0;
+ u8 wifi_5g_chnl[19] = {120, 124, 128, 132, 136, 140, 144, 149, 153, 157, 118, 126, 134, 142, 151, 159, 122, 138, 155};
+ u8 bt_skip_cneter_chanl[19] = {2, 8, 17, 26, 34, 42, 51, 62, 71, 77, 2, 12, 29, 46, 66, 76, 10, 37, 68};
+ u8 bt_skip_span[19] = {4, 8, 8, 10, 8, 10, 8, 8, 10, 4, 4, 16, 16, 16, 16, 4, 20, 34, 20};
+ boolean wifi_under_5g = FALSE;
+
+
+ btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+
+ if (type == BTC_MEDIA_CONNECT) {
+ btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
+ &wifi_central_chnl);
+ coex_sta->wl_center_channel = wifi_central_chnl;
+
+ if (!wifi_under_5g) {
+
+ h2c_parameter[0] = 0x1;
+ h2c_parameter[1] = wifi_central_chnl;
+
+ if (wifi_bw == BTC_WIFI_BW_HT40)
+ h2c_parameter[2] = 0x30;
+ else
+ h2c_parameter[2] = 0x30;
+ } else { /* for 5G */
+
+ for (i = 0; i <= 18; i++) {
+ if (wifi_central_chnl == wifi_5g_chnl[i])
+ break;
+ }
+
+ if (i <= 18) {
+ h2c_parameter[0] = 0x3;
+ h2c_parameter[1] = bt_skip_cneter_chanl[i];
+ h2c_parameter[2] = bt_skip_span[i];
+ }
+
+ }
+ }
+
+ coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
+ coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
+ coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
+
+ btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter);
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], para[0:2] = 0x%x 0x%x 0x%x\n",
+ h2c_parameter[0], h2c_parameter[1], h2c_parameter[2]);
+ BTC_TRACE(trace_buf);
+
+}
+
+
+static
+u8 halbtc8822b1ant_action_algorithm(IN struct btc_coexist *btcoexist)
+{
+ struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+ boolean bt_hs_on = FALSE;
+ u8 algorithm = BT_8822B_1ANT_COEX_ALGO_UNDEFINED;
+ u8 num_of_diff_profile = 0;
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+
+ if (!bt_link_info->bt_link_exist) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], No BT link exists!!!\n");
+ BTC_TRACE(trace_buf);
+ return algorithm;
+ }
+
+ if (bt_link_info->sco_exist)
+ num_of_diff_profile++;
+ if (bt_link_info->hid_exist)
+ num_of_diff_profile++;
+ if (bt_link_info->pan_exist)
+ num_of_diff_profile++;
+ if (bt_link_info->a2dp_exist)
+ num_of_diff_profile++;
+
+ if (num_of_diff_profile == 1) {
+ if (bt_link_info->sco_exist) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT Profile = SCO only\n");
+ BTC_TRACE(trace_buf);
+ algorithm = BT_8822B_1ANT_COEX_ALGO_SCO;
+ } else {
+ if (bt_link_info->hid_exist) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT Profile = HID only\n");
+ BTC_TRACE(trace_buf);
+ algorithm = BT_8822B_1ANT_COEX_ALGO_HID;
+ } else if (bt_link_info->a2dp_exist) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT Profile = A2DP only\n");
+ BTC_TRACE(trace_buf);
+ algorithm = BT_8822B_1ANT_COEX_ALGO_A2DP;
+ } else if (bt_link_info->pan_exist) {
+ if (bt_hs_on) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT Profile = PAN(HS) only\n");
+ BTC_TRACE(trace_buf);
+ algorithm =
+ BT_8822B_1ANT_COEX_ALGO_PANHS;
+ } else {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT Profile = PAN(EDR) only\n");
+ BTC_TRACE(trace_buf);
+ algorithm =
+ BT_8822B_1ANT_COEX_ALGO_PANEDR;
+ }
+ }
+ }
+ } else if (num_of_diff_profile == 2) {
+ if (bt_link_info->sco_exist) {
+ if (bt_link_info->hid_exist) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT Profile = SCO + HID\n");
+ BTC_TRACE(trace_buf);
+ algorithm = BT_8822B_1ANT_COEX_ALGO_HID;
+ } else if (bt_link_info->a2dp_exist) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT Profile = SCO + A2DP ==> SCO\n");
+ BTC_TRACE(trace_buf);
+ algorithm = BT_8822B_1ANT_COEX_ALGO_SCO;
+ } else if (bt_link_info->pan_exist) {
+ if (bt_hs_on) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT Profile = SCO + PAN(HS)\n");
+ BTC_TRACE(trace_buf);
+ algorithm = BT_8822B_1ANT_COEX_ALGO_SCO;
+ } else {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT Profile = SCO + PAN(EDR)\n");
+ BTC_TRACE(trace_buf);
+ algorithm =
+ BT_8822B_1ANT_COEX_ALGO_PANEDR_HID;
+ }
+ }
+ } else {
+ if (bt_link_info->hid_exist &&
+ bt_link_info->a2dp_exist) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT Profile = HID + A2DP\n");
+ BTC_TRACE(trace_buf);
+ algorithm = BT_8822B_1ANT_COEX_ALGO_HID_A2DP;
+ } else if (bt_link_info->hid_exist &&
+ bt_link_info->pan_exist) {
+ if (bt_hs_on) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT Profile = HID + PAN(HS)\n");
+ BTC_TRACE(trace_buf);
+ algorithm =
+ BT_8822B_1ANT_COEX_ALGO_HID_A2DP;
+ } else {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT Profile = HID + PAN(EDR)\n");
+ BTC_TRACE(trace_buf);
+ algorithm =
+ BT_8822B_1ANT_COEX_ALGO_PANEDR_HID;
+ }
+ } else if (bt_link_info->pan_exist &&
+ bt_link_info->a2dp_exist) {
+ if (bt_hs_on) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT Profile = A2DP + PAN(HS)\n");
+ BTC_TRACE(trace_buf);
+ algorithm =
+ BT_8822B_1ANT_COEX_ALGO_A2DP_PANHS;
+ } else {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT Profile = A2DP + PAN(EDR)\n");
+ BTC_TRACE(trace_buf);
+ algorithm =
+ BT_8822B_1ANT_COEX_ALGO_PANEDR_A2DP;
+ }
+ }
+ }
+ } else if (num_of_diff_profile == 3) {
+ if (bt_link_info->sco_exist) {
+ if (bt_link_info->hid_exist &&
+ bt_link_info->a2dp_exist) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n");
+ BTC_TRACE(trace_buf);
+ algorithm = BT_8822B_1ANT_COEX_ALGO_HID;
+ } else if (bt_link_info->hid_exist &&
+ bt_link_info->pan_exist) {
+ if (bt_hs_on) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT Profile = SCO + HID + PAN(HS)\n");
+ BTC_TRACE(trace_buf);
+ algorithm =
+ BT_8822B_1ANT_COEX_ALGO_HID_A2DP;
+ } else {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n");
+ BTC_TRACE(trace_buf);
+ algorithm =
+ BT_8822B_1ANT_COEX_ALGO_PANEDR_HID;
+ }
+ } else if (bt_link_info->pan_exist &&
+ bt_link_info->a2dp_exist) {
+ if (bt_hs_on) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n");
+ BTC_TRACE(trace_buf);
+ algorithm = BT_8822B_1ANT_COEX_ALGO_SCO;
+ } else {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n");
+ BTC_TRACE(trace_buf);
+ algorithm =
+ BT_8822B_1ANT_COEX_ALGO_PANEDR_HID;
+ }
+ }
+ } else {
+ if (bt_link_info->hid_exist &&
+ bt_link_info->pan_exist &&
+ bt_link_info->a2dp_exist) {
+ if (bt_hs_on) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n");
+ BTC_TRACE(trace_buf);
+ algorithm =
+ BT_8822B_1ANT_COEX_ALGO_HID_A2DP;
+ } else {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n");
+ BTC_TRACE(trace_buf);
+ algorithm =
+ BT_8822B_1ANT_COEX_ALGO_HID_A2DP_PANEDR;
+ }
+ }
+ }
+ } else if (num_of_diff_profile >= 3) {
+ if (bt_link_info->sco_exist) {
+ if (bt_link_info->hid_exist &&
+ bt_link_info->pan_exist &&
+ bt_link_info->a2dp_exist) {
+ if (bt_hs_on) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n");
+ BTC_TRACE(trace_buf);
+
+ } else {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n");
+ BTC_TRACE(trace_buf);
+ algorithm =
+ BT_8822B_1ANT_COEX_ALGO_PANEDR_HID;
+ }
+ }
+ }
+ }
+
+ return algorithm;
+}
+
+
+static
+void halbtc8822b1ant_low_penalty_ra(IN struct btc_coexist *btcoexist,
+ IN boolean force_exec, IN boolean low_penalty_ra)
+{
+#if 1
+ coex_dm->cur_low_penalty_ra = low_penalty_ra;
+
+ if (!force_exec) {
+ if (coex_dm->pre_low_penalty_ra ==
+ coex_dm->cur_low_penalty_ra)
+ return;
+ }
+
+ if (low_penalty_ra)
+ btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 10);
+ else
+ btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 0);
+
+ coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra;
+
+#endif
+}
+
+static
+void halbtc8822b1ant_mimo_ps(
+ IN struct btc_coexist *btcoexist,
+ IN boolean force_exec,
+ IN u8 state)
+{
+ static u8 pre_state = 0;
+
+ if (!force_exec) {
+ if (state == pre_state)
+ return;
+ }
+
+ pre_state = state;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], halbtc8822b1ant_mimo_ps(), state = %d\n", state);
+ BTC_TRACE(trace_buf);
+
+ btcoexist->btc_set(btcoexist, BTC_SET_MIMO_PS_MODE, &state);
+}
+
+
+static
+void halbtc8822b1ant_write_score_board(
+ IN struct btc_coexist *btcoexist,
+ IN u16 bitpos,
+ IN boolean state
+)
+{
+
+ static u16 originalval = 0x8002, preval = 0x0;
+
+ if (state)
+ originalval = originalval | bitpos;
+ else
+ originalval = originalval & (~bitpos);
+
+ coex_sta->score_board_WB = originalval;
+
+ if (originalval != preval) {
+
+ preval = originalval;
+ btcoexist->btc_write_2byte(btcoexist, 0xaa, originalval);
+ } else {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], halbtc8822b1ant_write_score_board: return for nochange\n");
+ BTC_TRACE(trace_buf);
+ }
+}
+
+
+static
+void halbtc8822b1ant_read_score_board(
+ IN struct btc_coexist *btcoexist,
+ IN u16 *score_board_val
+)
+{
+
+ *score_board_val = (btcoexist->btc_read_2byte(btcoexist,
+ 0xaa)) & 0x7fff;
+}
+
+static
+void halbtc8822b1ant_post_state_to_bt(
+ IN struct btc_coexist *btcoexist,
+ IN u16 type,
+ IN boolean state
+)
+{
+
+ halbtc8822b1ant_write_score_board(btcoexist, (u16) type, state);
+
+}
+
+static
+void halbtc8822b1ant_adjust_wl_tx_power(IN struct btc_coexist *btcoexist,
+ IN boolean force_exec, IN u8 fw_dac_swing_lvl)
+{
+
+ coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl;
+
+ if (!force_exec) {
+ if (coex_dm->pre_fw_dac_swing_lvl ==
+ coex_dm->cur_fw_dac_swing_lvl)
+ return;
+ }
+
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc5b, 0xff, fw_dac_swing_lvl);
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0xe5b, 0xff, fw_dac_swing_lvl);
+
+ coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl;
+}
+
+static
+void halbtc8822b1ant_adjust_bt_tx_power(IN struct btc_coexist *btcoexist,
+ IN boolean force_exec, IN u8 dec_bt_pwr_lvl)
+{
+ u8 h2c_parameter[1] = {0};
+
+ coex_dm->cur_bt_dec_pwr_lvl = dec_bt_pwr_lvl;
+
+ if (!force_exec) {
+ if (coex_dm->pre_bt_dec_pwr_lvl == coex_dm->cur_bt_dec_pwr_lvl)
+ return;
+ }
+
+ h2c_parameter[0] = 0 - dec_bt_pwr_lvl;
+
+ btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter);
+
+ coex_dm->pre_bt_dec_pwr_lvl = coex_dm->cur_bt_dec_pwr_lvl;
+}
+
+static
+void halbtc8822b1ant_adjust_wl_rx_gain(IN struct btc_coexist *btcoexist,
+ IN boolean force_exec, IN boolean agc_table_en)
+{
+u32 rx_gain_value_enable[] = {0xff000003, 0xea240003, 0xe9260003,
+ 0xe8280003, 0xe72a0003, 0xe62c0003, 0xaf2e0003, 0xae300003,
+ 0xad320003, 0xac340003, 0xab360003, 0x8d380003, 0x8c3a0003,
+ 0x8b3c0003, 0x8a3e0003, 0x6e400003, 0x6d420003, 0x6c440003,
+ 0x6b460003, 0x6a480003, 0x694a0003, 0x684c0003, 0x674e0003,
+ 0x66500003, 0x65520003, 0x64540003, 0x64560003, 0x007e0403};
+
+u32 rx_gain_value_disable[] = {0xff000003, 0xeb240003, 0xea260003,
+ 0xe9280003, 0xe82a0003, 0xe72c0003, 0xe62e0003, 0xe5300003,
+ 0xc8320003, 0xc7340003, 0xc6360003, 0xc5380003, 0xc43a0003,
+ 0xc33c0003, 0xc23e0003, 0xc1400003, 0xc0420003, 0xa5440003,
+ 0xa4460003, 0xa3480003, 0xa24a0003, 0xa14c0003, 0x834e0003,
+ 0x82500003, 0x81520003, 0x80540003, 0x65560003, 0x007e0403};
+
+ u8 i;
+
+ coex_dm->cur_agc_table_en = agc_table_en;
+
+ if (!force_exec) {
+ if (coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en)
+ return;
+ }
+
+ if (agc_table_en) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BB Agc Table On!\n");
+ BTC_TRACE(trace_buf);
+
+ for (i = 0; i <= 100; i++) {
+ btcoexist->btc_write_4byte(btcoexist,
+ 0x81c, rx_gain_value_enable[i]);
+
+ if (rx_gain_value_enable[i] == 0x007e0403)
+ break;
+ }
+
+ } else {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BB Agc Table Off!\n");
+ BTC_TRACE(trace_buf);
+
+ for (i = 0; i <= 100; i++) {
+ btcoexist->btc_write_4byte(btcoexist,
+ 0x81c, rx_gain_value_disable[i]);
+
+ if (rx_gain_value_disable[i] == 0x007e0403)
+ break;
+ }
+ }
+
+
+ coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en;
+}
+
+static
+void halbtc8822b1ant_adjust_bt_rx_gain(IN struct btc_coexist *btcoexist,
+ IN boolean force_exec, IN boolean rx_gain_en)
+{
+
+ /* use scoreboard[4] to notify BT Rx gain table change */
+ halbtc8822b1ant_post_state_to_bt(btcoexist,
+ BT_8822B_1ANT_SCOREBOARD_RXGAIN,
+ rx_gain_en);
+}
+
+
+
+static
+void halbtc8822b1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist)
+{
+ static u32 bt_disable_cnt = 0;
+ boolean bt_active = TRUE, bt_disabled = FALSE,
+ wifi_under_5g = FALSE;
+ u16 u16tmp;
+
+ /* This function check if bt is disabled */
+#if 0
+ if (coex_sta->high_priority_tx == 0 &&
+ coex_sta->high_priority_rx == 0 &&
+ coex_sta->low_priority_tx == 0 &&
+ coex_sta->low_priority_rx == 0)
+ bt_active = FALSE;
+ if (coex_sta->high_priority_tx == 0xffff &&
+ coex_sta->high_priority_rx == 0xffff &&
+ coex_sta->low_priority_tx == 0xffff &&
+ coex_sta->low_priority_rx == 0xffff)
+ bt_active = FALSE;
+
+
+#else
+
+ /* Read BT on/off status from scoreboard[1],
+ * enable this only if BT patch support this feature
+ */
+ halbtc8822b1ant_read_score_board(btcoexist, &u16tmp);
+
+ bt_active = u16tmp & BIT(1);
+
+
+#endif
+
+ if (bt_active) {
+ bt_disable_cnt = 0;
+ bt_disabled = FALSE;
+ btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
+ &bt_disabled);
+ } else {
+
+ bt_disable_cnt++;
+ if (bt_disable_cnt >= 2) {
+ bt_disabled = TRUE;
+ bt_disable_cnt = 2;
+ }
+
+ btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
+ &bt_disabled);
+ }
+
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G,
+ &wifi_under_5g);
+
+ if ((wifi_under_5g) || (bt_disabled))
+ halbtc8822b1ant_low_penalty_ra(btcoexist,
+ NORMAL_EXEC, FALSE);
+ else
+ halbtc8822b1ant_low_penalty_ra(btcoexist,
+ NORMAL_EXEC, TRUE);
+
+
+ if (coex_sta->bt_disabled != bt_disabled) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT is from %s to %s!!\n",
+ (coex_sta->bt_disabled ? "disabled" :
+ "enabled"),
+ (bt_disabled ? "disabled" : "enabled"));
+ BTC_TRACE(trace_buf);
+ coex_sta->bt_disabled = bt_disabled;
+
+ /*for win10 RS3 BT disable->enable trigger wifi scan issue */
+ if (!coex_sta->bt_disabled) {
+ coex_sta->is_bt_reenable = TRUE;
+ coex_sta->cnt_bt_reenable = 15;
+ } else {
+ coex_sta->is_bt_reenable = FALSE;
+ coex_sta->cnt_bt_reenable = 0;
+ }
+ }
+
+}
+
+
+
+static
+void halbtc8822b1ant_enable_gnt_to_gpio(IN struct btc_coexist *btcoexist,
+ boolean isenable)
+{
+#if BT_8822B_1ANT_COEX_DBG
+ static u8 bitVal[5] = {0, 0, 0, 0, 0};
+ static boolean state = FALSE;
+
+ if (state == isenable)
+ return;
+
+ state = isenable;
+
+ if (isenable) {
+
+ /* enable GNT_WL, GNT_BT to GPIO for debug */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x1);
+
+ /* store original value */
+ bitVal[0] = (btcoexist->btc_read_1byte(btcoexist,
+ 0x66) & BIT(4)) >> 4; /*0x66[4] */
+ bitVal[1] = (btcoexist->btc_read_1byte(btcoexist,
+ 0x67) & BIT(0)); /*0x66[8] */
+ bitVal[2] = (btcoexist->btc_read_1byte(btcoexist,
+ 0x42) & BIT(3)) >> 3; /*0x40[19] */
+ bitVal[3] = (btcoexist->btc_read_1byte(btcoexist,
+ 0x65) & BIT(7)) >> 7; /*0x64[15] */
+ bitVal[4] = (btcoexist->btc_read_1byte(btcoexist,
+ 0x72) & BIT(2)) >> 2; /*0x70[18] */
+
+ /* switch GPIO Mux */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, BIT(4),
+ 0x0); /*0x66[4] = 0 */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, BIT(0),
+ 0x0); /*0x66[8] = 0 */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, BIT(3),
+ 0x0); /*0x40[19] = 0 */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x65, BIT(7),
+ 0x0); /*0x64[15] = 0 */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x72, BIT(2),
+ 0x0); /*0x70[18] = 0 */
+
+
+ } else {
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x0);
+
+ /* Restore original value */
+ /* switch GPIO Mux */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, BIT(4),
+ bitVal[0]); /*0x66[4] = 0 */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, BIT(0),
+ bitVal[1]); /*0x66[8] = 0 */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, BIT(3),
+ bitVal[2]); /*0x40[19] = 0 */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x65, BIT(7),
+ bitVal[3]); /*0x64[15] = 0 */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x72, BIT(2),
+ bitVal[4]); /*0x70[18] = 0 */
+ }
+#endif
+}
+
+
+
+u32 halbtc8822b1ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist,
+ IN u16 reg_addr)
+{
+ u32 j = 0, delay_count = 0;
+
+ /* wait for ready bit before access 0x1700 */
+ while (1) {
+ if ((btcoexist->btc_read_1byte(btcoexist, 0x1703)&BIT(5)) == 0) {
+ delay_ms(10);
+ delay_count++;
+ if (delay_count >= 10) {
+ delay_count = 0;
+ break;
+ }
+ } else
+ break;
+ }
+
+ btcoexist->btc_write_4byte(btcoexist, 0x1700, 0x800F0000 | reg_addr);
+
+ return btcoexist->btc_read_4byte(btcoexist,
+ 0x1708); /* get read data */
+}
+
+
+void halbtc8822b1ant_ltecoex_indirect_write_reg(IN struct btc_coexist
+ *btcoexist,
+ IN u16 reg_addr, IN u32 bit_mask, IN u32 reg_value)
+{
+ u32 val, i = 0, j = 0, bitpos = 0, delay_count = 0;
+
+
+ if (bit_mask == 0x0)
+ return;
+
+ if (bit_mask == 0xffffffff) {
+ /* wait for ready bit before access 0x1700/0x1704 */
+ while (1) {
+ if ((btcoexist->btc_read_1byte(btcoexist, 0x1703)&BIT(5)) == 0) {
+ delay_ms(10);
+ delay_count++;
+ if (delay_count >= 10) {
+ delay_count = 0;
+ break;
+ }
+ } else
+ break;
+ }
+
+ btcoexist->btc_write_4byte(btcoexist, 0x1704,
+ reg_value); /* put write data */
+
+ btcoexist->btc_write_4byte(btcoexist, 0x1700,
+ 0xc00F0000 | reg_addr);
+ } else {
+ for (i = 0; i <= 31; i++) {
+ if (((bit_mask >> i) & 0x1) == 0x1) {
+ bitpos = i;
+ break;
+ }
+ }
+
+ /* read back register value before write */
+ val = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
+ reg_addr);
+ val = (val & (~bit_mask)) | (reg_value << bitpos);
+
+ /* wait for ready bit before access 0x1700/0x1704 */
+ while (1) {
+ if ((btcoexist->btc_read_1byte(btcoexist, 0x1703)&BIT(5)) == 0) {
+ delay_ms(10);
+ delay_count++;
+ if (delay_count >= 10) {
+ delay_count = 0;
+ break;
+ }
+ } else
+ break;
+ }
+
+ btcoexist->btc_write_4byte(btcoexist, 0x1704,
+ val); /* put write data */
+
+ btcoexist->btc_write_4byte(btcoexist, 0x1700,
+ 0xc00F0000 | reg_addr);
+
+ }
+
+}
+
+
+void halbtc8822b1ant_ltecoex_enable(IN struct btc_coexist *btcoexist,
+ IN boolean enable)
+{
+ u8 val;
+
+ val = (enable) ? 1 : 0;
+ /* 0x38[7] */
+ halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist, 0x38, 0x80, val);
+
+}
+
+
+
+void halbtc8822b1ant_ltecoex_pathcontrol_owner(IN struct btc_coexist *btcoexist,
+ IN boolean wifi_control)
+{
+ u8 val;
+
+ val = (wifi_control) ? 1 : 0;
+ /* 0x70[26] */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x4, val);
+
+}
+
+
+void halbtc8822b1ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist,
+ IN u8 control_block, IN boolean sw_control, IN u8 state)
+{
+ u32 val = 0, bit_mask;
+
+ state = state & 0x1;
+ /*LTE indirect 0x38=0xccxx (sw : gnt_wl=1,sw gnt_bt=1)
+ *0x38=0xddxx (sw : gnt_bt=1 , sw gnt_wl=0)
+ *0x38=0x55xx(hw pta :gnt_wl /gnt_bt )
+ */
+ val = (sw_control) ? ((state << 1) | 0x1) : 0;
+
+ switch (control_block) {
+ case BT_8822B_1ANT_GNT_BLOCK_RFC_BB:
+ default:
+ bit_mask = 0xc000;
+ halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist,
+ 0x38, bit_mask, val); /* 0x38[15:14] */
+ bit_mask = 0x0c00;
+ halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist,
+ 0x38, bit_mask, val); /* 0x38[11:10] */
+ break;
+ case BT_8822B_1ANT_GNT_BLOCK_RFC:
+ bit_mask = 0xc000;
+ halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist,
+ 0x38, bit_mask, val); /* 0x38[15:14] */
+ break;
+ case BT_8822B_1ANT_GNT_BLOCK_BB:
+ bit_mask = 0x0c00;
+ halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist,
+ 0x38, bit_mask, val); /* 0x38[11:10] */
+ break;
+
+ }
+
+}
+
+
+void halbtc8822b1ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist,
+ IN u8 control_block, IN boolean sw_control, IN u8 state)
+{
+ u32 val = 0, bit_mask;
+ /*LTE indirect 0x38=0xccxx (sw : gnt_wl=1,sw gnt_bt=1)
+ *0x38=0xddxx (sw : gnt_bt=1 , sw gnt_wl=0)
+ *0x38=0x55xx(hw pta :gnt_wl /gnt_bt )
+ */
+
+ state = state & 0x1;
+ val = (sw_control) ? ((state << 1) | 0x1) : 0;
+
+ switch (control_block) {
+ case BT_8822B_1ANT_GNT_BLOCK_RFC_BB:
+ default:
+ bit_mask = 0x3000;
+ halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist,
+ 0x38, bit_mask, val); /* 0x38[13:12] */
+ bit_mask = 0x0300;
+ halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist,
+ 0x38, bit_mask, val); /* 0x38[9:8] */
+ break;
+ case BT_8822B_1ANT_GNT_BLOCK_RFC:
+ bit_mask = 0x3000;
+ halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist,
+ 0x38, bit_mask, val); /* 0x38[13:12] */
+ break;
+ case BT_8822B_1ANT_GNT_BLOCK_BB:
+ bit_mask = 0x0300;
+ halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist,
+ 0x38, bit_mask, val); /* 0x38[9:8] */
+ break;
+
+ }
+
+}
+
+
+void halbtc8822b1ant_ltecoex_set_coex_table(IN struct btc_coexist *btcoexist,
+ IN u8 table_type, IN u16 table_content)
+{
+ u16 reg_addr = 0x0000;
+
+ switch (table_type) {
+ case BT_8822B_1ANT_CTT_WL_VS_LTE:
+ reg_addr = 0xa0;
+ break;
+ case BT_8822B_1ANT_CTT_BT_VS_LTE:
+ reg_addr = 0xa4;
+ break;
+ }
+
+ if (reg_addr != 0x0000)
+ halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist, reg_addr,
+ 0xffff, table_content); /* 0xa0[15:0] or 0xa4[15:0] */
+
+
+}
+
+
+
+
+void halbtc8822b1ant_ltcoex_set_break_table(IN struct btc_coexist *btcoexist,
+ IN u8 table_type, IN u8 table_content)
+{
+ u16 reg_addr = 0x0000;
+
+ switch (table_type) {
+ case BT_8822B_1ANT_LBTT_WL_BREAK_LTE:
+ reg_addr = 0xa8;
+ break;
+ case BT_8822B_1ANT_LBTT_BT_BREAK_LTE:
+ reg_addr = 0xac;
+ break;
+ case BT_8822B_1ANT_LBTT_LTE_BREAK_WL:
+ reg_addr = 0xb0;
+ break;
+ case BT_8822B_1ANT_LBTT_LTE_BREAK_BT:
+ reg_addr = 0xb4;
+ break;
+ }
+
+ if (reg_addr != 0x0000)
+ halbtc8822b1ant_ltecoex_indirect_write_reg(btcoexist, reg_addr,
+ 0xff, table_content); /* 0xa8[15:0] or 0xb4[15:0] */
+
+
+}
+
+
+
+
+void halbtc8822b1ant_set_wltoggle_coex_table(IN struct btc_coexist *btcoexist,
+ IN boolean force_exec, IN u8 interval,
+ IN u8 val0x6c4_b0, IN u8 val0x6c4_b1, IN u8 val0x6c4_b2,
+ IN u8 val0x6c4_b3)
+{
+ static u8 pre_h2c_parameter[6] = {0};
+ u8 cur_h2c_parameter[6] = {0};
+ u8 i, match_cnt = 0;
+
+ cur_h2c_parameter[0] = 0x7; /* op_code, 0x7= wlan toggle slot*/
+
+ cur_h2c_parameter[1] = interval;
+ cur_h2c_parameter[2] = val0x6c4_b0;
+ cur_h2c_parameter[3] = val0x6c4_b1;
+ cur_h2c_parameter[4] = val0x6c4_b2;
+ cur_h2c_parameter[5] = val0x6c4_b3;
+
+ if (!force_exec) {
+ for (i = 1; i <= 5; i++) {
+ if (cur_h2c_parameter[i] != pre_h2c_parameter[i])
+ break;
+
+ match_cnt++;
+ }
+
+ if (match_cnt == 5)
+ return;
+ }
+
+ for (i = 1; i <= 5; i++)
+ pre_h2c_parameter[i] = cur_h2c_parameter[i];
+
+ btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, cur_h2c_parameter);
+}
+
+
+
+void halbtc8822b1ant_set_coex_table(IN struct btc_coexist *btcoexist,
+ IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc)
+{
+ btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
+
+ btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
+
+ btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
+
+ btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
+}
+
+
+void halbtc8822b1ant_coex_table(IN struct btc_coexist *btcoexist,
+ IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4,
+ IN u32 val0x6c8, IN u8 val0x6cc)
+{
+ coex_dm->cur_val0x6c0 = val0x6c0;
+ coex_dm->cur_val0x6c4 = val0x6c4;
+ coex_dm->cur_val0x6c8 = val0x6c8;
+ coex_dm->cur_val0x6cc = val0x6cc;
+
+
+
+ if (!force_exec) {
+ if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) &&
+ (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) &&
+ (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) &&
+ (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc))
+ return;
+ }
+ halbtc8822b1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8,
+ val0x6cc);
+
+ coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0;
+ coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4;
+ coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8;
+ coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc;
+}
+
+
+void halbtc8822b1ant_coex_table_with_type(IN struct btc_coexist *btcoexist,
+ IN boolean force_exec, IN u8 type)
+{
+ u32 break_table;
+ u8 select_table;
+
+
+ coex_sta->coex_table_type = type;
+
+ if (coex_sta->concurrent_rx_mode_on == TRUE) {
+ /* set WL hi-pri can break BT */
+ break_table = 0xf0ffffff;
+ /* set Tx response = Hi-Pri
+ (ex: Transmitting ACK,BA,CTS) */
+ select_table = 0xb;
+ } else {
+ break_table = 0xffffff;
+ select_table = 0x3;
+ }
+
+ switch (type) {
+ case 0:
+ halbtc8822b1ant_coex_table(btcoexist, force_exec,
+ 0x55555555, 0x55555555, break_table,
+ select_table);
+ break;
+ case 1:
+ halbtc8822b1ant_coex_table(btcoexist, force_exec,
+ 0x55555555, 0x5a5a5a5a, break_table,
+ select_table);
+ break;
+ case 2:
+ halbtc8822b1ant_coex_table(btcoexist, force_exec,
+ 0x65555555, 0xaaaaaaaa, break_table,
+ select_table);
+ break;
+ case 3:
+ halbtc8822b1ant_coex_table(btcoexist, force_exec,
+ 0x65555555, 0x6a5a5a5a, break_table,
+ select_table);
+ break;
+ case 4:
+ halbtc8822b1ant_coex_table(btcoexist, force_exec,
+ 0xaa555555, 0xaa5a5a5a, break_table,
+ select_table);
+ break;
+ case 5:
+ halbtc8822b1ant_coex_table(btcoexist, force_exec,
+ 0x5a5a5a5a, 0x5a5a5a5a, break_table,
+ select_table);
+ break;
+ case 6:
+ halbtc8822b1ant_coex_table(btcoexist, force_exec,
+ 0x55555555, 0xaa5a5a5a, break_table,
+ select_table);
+ break;
+ case 7:
+ halbtc8822b1ant_coex_table(btcoexist, force_exec,
+ 0x65555555, 0xaaaa5aaa, break_table,
+ select_table);
+ break;
+ case 8:
+ halbtc8822b1ant_coex_table(btcoexist, force_exec,
+ 0xffffffff, 0xffffffff, break_table,
+ select_table);
+ break;
+ case 9:
+ halbtc8822b1ant_coex_table(btcoexist, force_exec,
+ 0x65555555, 0xaaaaaaaa, break_table,
+ select_table);
+ break;
+ case 10:
+ halbtc8822b1ant_coex_table(btcoexist, force_exec,
+ 0xaa5555aa, 0xaaaaaaaa, break_table,
+ select_table);
+ break;
+ case 11:
+ halbtc8822b1ant_coex_table(btcoexist, force_exec,
+ 0xa5a55555, 0xaaaa5a5a, break_table,
+ select_table);
+ break;
+ case 12:
+ halbtc8822b1ant_coex_table(btcoexist, force_exec,
+ 0xaaaaa5aa, 0xaaaaa5aa, break_table,
+ select_table);
+ break;
+ case 13:
+ halbtc8822b1ant_coex_table(btcoexist, force_exec,
+ 0xaa5555aa, 0x6a5a5a5a, break_table,
+ select_table);
+ break;
+ case 14:
+ halbtc8822b1ant_coex_table(btcoexist, force_exec,
+ 0xaa5555aa, 0x5a5a5a5a, break_table,
+ select_table);
+ break;
+ case 15:
+ halbtc8822b1ant_coex_table(btcoexist, force_exec,
+ 0x55555555, 0xaaaa55aa, break_table,
+ select_table);
+ break;
+ case 16:
+ halbtc8822b1ant_coex_table(btcoexist, force_exec,
+ 0x5a5a555a, 0x5a5a555a, break_table,
+ select_table);
+ break;
+ case 17:
+ halbtc8822b1ant_coex_table(btcoexist, force_exec,
+ 0xaaaa55aa, 0xaaaa55aa, break_table,
+ select_table);
+ break;
+ case 18:
+ halbtc8822b1ant_coex_table(btcoexist, force_exec,
+ 0x55555555, 0x5aaa5a5a, break_table,
+ select_table);
+ break;
+ case 19:
+ halbtc8822b1ant_coex_table(btcoexist, force_exec,
+ 0xa5555555, 0xaaaa5aaa, break_table,
+ select_table);
+ break;
+ case 20:
+ halbtc8822b1ant_coex_table(btcoexist, force_exec,
+ 0x55555555, 0xaaaa5aaa, break_table,
+ select_table);
+ break;
+ case 21:
+ halbtc8822b1ant_coex_table(btcoexist, force_exec,
+ 0x55555555, 0xaaaa5afa, break_table,
+ select_table);
+ break;
+ case 22:
+ halbtc8822b1ant_coex_table(btcoexist, force_exec,
+ 0xaaffffaa, 0xfafafafa, break_table,
+ select_table);
+ break;
+ case 23:
+ halbtc8822b1ant_coex_table(btcoexist, force_exec,
+ 0xffff55ff, 0xfafafafa, break_table,
+ select_table);
+ break;
+ case 24:
+ halbtc8822b1ant_coex_table(btcoexist, force_exec,
+ 0x55555555, 0xfafafafa, break_table,
+ select_table);
+ break;
+ case 25:
+ halbtc8822b1ant_coex_table(btcoexist, force_exec,
+ 0xffffffff, 0xaa5a5a5a, break_table,
+ select_table);
+ break;
+ case 26:
+ halbtc8822b1ant_coex_table(btcoexist, force_exec,
+ 0xffff55ff, 0xaaaaaaaa, break_table,
+ select_table);
+ default:
+ break;
+ }
+}
+
+
+void halbtc8822b1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist,
+ IN boolean enable)
+{
+
+
+ u8 h2c_parameter[1] = {0};
+
+ if (enable)
+ h2c_parameter[0] |= BIT(0); /* function enable */
+
+ btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter);
+}
+
+
+void halbtc8822b1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist,
+ IN boolean force_exec, IN boolean enable)
+{
+
+ coex_dm->cur_ignore_wlan_act = enable;
+
+ if (!force_exec) {
+ if (coex_dm->pre_ignore_wlan_act ==
+ coex_dm->cur_ignore_wlan_act) {
+
+ coex_dm->pre_ignore_wlan_act =
+ coex_dm->cur_ignore_wlan_act;
+ return;
+ }
+ }
+
+ halbtc8822b1ant_set_fw_ignore_wlan_act(btcoexist, enable);
+
+ coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
+}
+
+
+void halbtc8822b1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist,
+ IN u8 lps_val, IN u8 rpwm_val)
+{
+ u8 lps = lps_val;
+ u8 rpwm = rpwm_val;
+
+ btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps);
+ btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm);
+}
+
+
+void halbtc8822b1ant_lps_rpwm(IN struct btc_coexist *btcoexist,
+ IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val)
+{
+ coex_dm->cur_lps = lps_val;
+ coex_dm->cur_rpwm = rpwm_val;
+
+ if (!force_exec) {
+ if ((coex_dm->pre_lps == coex_dm->cur_lps) &&
+ (coex_dm->pre_rpwm == coex_dm->cur_rpwm))
+ return;
+ }
+ halbtc8822b1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val);
+
+ coex_dm->pre_lps = coex_dm->cur_lps;
+ coex_dm->pre_rpwm = coex_dm->cur_rpwm;
+}
+
+
+
+void halbtc8822b1ant_ps_tdma_check_for_power_save_state(
+ IN struct btc_coexist *btcoexist, IN boolean new_ps_state)
+{
+ u8 lps_mode = 0x0;
+ u8 h2c_parameter[5] = {0x8, 0, 0, 0, 0};
+
+ btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode);
+
+ if (lps_mode) { /* already under LPS state */
+ if (new_ps_state) {
+ /* keep state under LPS, do nothing. */
+ } else {
+ /* will leave LPS state, turn off psTdma first */
+
+ btcoexist->btc_fill_h2c(btcoexist, 0x60, 5,
+ h2c_parameter);
+ }
+ } else { /* NO PS state */
+ if (new_ps_state) {
+ /* will enter LPS state, turn off psTdma first */
+
+ btcoexist->btc_fill_h2c(btcoexist, 0x60, 5,
+ h2c_parameter);
+ } else {
+ /* keep state under NO PS state, do nothing. */
+ }
+ }
+}
+
+
+
+
+boolean halbtc8822b1ant_power_save_state(IN struct btc_coexist *btcoexist,
+ IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val)
+{
+ boolean low_pwr_disable = FALSE, result = TRUE;
+
+ switch (ps_type) {
+ case BTC_PS_WIFI_NATIVE:
+ /* recover to original 32k low power setting */
+ coex_sta->force_lps_ctrl = FALSE;
+ low_pwr_disable = FALSE;
+ /* btcoexist->btc_set(btcoexist,
+ over to original 32k low power setting */
+
+ btcoexist->btc_set(btcoexist, BTC_SET_ACT_PRE_NORMAL_LPS,
+ NULL);
+ break;
+ case BTC_PS_LPS_ON:
+
+ coex_sta->force_lps_ctrl = TRUE;
+ halbtc8822b1ant_ps_tdma_check_for_power_save_state(
+ btcoexist, TRUE);
+ halbtc8822b1ant_lps_rpwm(btcoexist, NORMAL_EXEC,
+ lps_val, rpwm_val);
+ /* when coex force to enter LPS, do not enter 32k low power. */
+ low_pwr_disable = TRUE;
+ btcoexist->btc_set(btcoexist,
+ BTC_SET_ACT_DISABLE_LOW_POWER,
+ &low_pwr_disable);
+ /* power save must executed before psTdma. */
+ btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS,
+ NULL);
+
+ break;
+ case BTC_PS_LPS_OFF:
+
+ coex_sta->force_lps_ctrl = TRUE;
+ halbtc8822b1ant_ps_tdma_check_for_power_save_state(
+ btcoexist, FALSE);
+ result = btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS,
+ NULL);
+
+ break;
+ default:
+ break;
+ }
+
+ return result;
+}
+
+
+
+
+void halbtc8822b1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist,
+ IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5)
+{
+ u8 h2c_parameter[5] = {0};
+ u8 real_byte1 = byte1, real_byte5 = byte5;
+ boolean ap_enable = FALSE, result = FALSE;
+ struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+ u8 ps_type = BTC_PS_WIFI_NATIVE;
+
+ if (byte5 & BIT(2))
+ coex_sta->is_tdma_btautoslot = TRUE;
+ else
+ coex_sta->is_tdma_btautoslot = FALSE;
+
+ /* release bt-auto slot for auto-slot hang is detected!! */
+ if (coex_sta->is_tdma_btautoslot)
+ if ((coex_sta->is_tdma_btautoslot_hang) ||
+ (bt_link_info->slave_role))
+ byte5 = byte5 & 0xfb;
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
+ &ap_enable);
+
+ if ((ap_enable) && (byte1 & BIT(4) && !(byte1 & BIT(5)))) {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], halbtc8822b1ant_set_fw_pstdma == FW for 1Ant AP mode\n");
+ BTC_TRACE(trace_buf);
+
+ real_byte1 &= ~BIT(4);
+ real_byte1 |= BIT(5);
+
+ real_byte5 |= BIT(5);
+ real_byte5 &= ~BIT(6);
+
+ ps_type = BTC_PS_WIFI_NATIVE;
+ halbtc8822b1ant_power_save_state(btcoexist,
+ ps_type, 0x0,
+ 0x0);
+
+ } else if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], halbtc8822b1ant_set_fw_pstdma == Force LPS (byte1 = 0x%x)\n", byte1);
+ BTC_TRACE(trace_buf);
+
+ ps_type = BTC_PS_LPS_OFF;
+ if (!halbtc8822b1ant_power_save_state(btcoexist, ps_type, 0x50, 0x4))
+ result = TRUE;
+ } else {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], halbtc8822b1ant_set_fw_pstdma == native power save (byte1 = 0x%x)\n", byte1);
+ BTC_TRACE(trace_buf);
+
+ ps_type = BTC_PS_WIFI_NATIVE;
+ halbtc8822b1ant_power_save_state(btcoexist,
+ ps_type, 0x0,
+ 0x0);
+ }
+
+
+ coex_sta->is_set_ps_state_fail = result;
+
+ if (!coex_sta->is_set_ps_state_fail) {
+ h2c_parameter[0] = real_byte1;
+ h2c_parameter[1] = byte2;
+ h2c_parameter[2] = byte3;
+ h2c_parameter[3] = byte4;
+ h2c_parameter[4] = real_byte5;
+
+ coex_dm->ps_tdma_para[0] = real_byte1;
+ coex_dm->ps_tdma_para[1] = byte2;
+ coex_dm->ps_tdma_para[2] = byte3;
+ coex_dm->ps_tdma_para[3] = byte4;
+ coex_dm->ps_tdma_para[4] = real_byte5;
+
+ btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
+
+ } else {
+ coex_sta->cnt_set_ps_state_fail++;
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], halbtc8822b1ant_set_fw_pstdma == Force Leave LPS Fail (cnt = %d)\n",
+ coex_sta->cnt_set_ps_state_fail);
+ BTC_TRACE(trace_buf);
+ }
+
+ if (ps_type == BTC_PS_WIFI_NATIVE)
+ btcoexist->btc_set(btcoexist, BTC_SET_ACT_POST_NORMAL_LPS, NULL);
+}
+
+
+
+void halbtc8822b1ant_ps_tdma(IN struct btc_coexist *btcoexist,
+ IN boolean force_exec, IN boolean turn_on, IN u8 type)
+{
+ struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+ struct btc_board_info *board_info = &btcoexist->board_info;
+ boolean wifi_busy = FALSE;
+ static u8 psTdmaByte4Modify = 0x0, pre_psTdmaByte4Modify = 0x0;
+ static boolean pre_wifi_busy = FALSE;
+
+ coex_dm->cur_ps_tdma_on = turn_on;
+ coex_dm->cur_ps_tdma = type;
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+ if (wifi_busy != pre_wifi_busy) {
+ force_exec = TRUE;
+ pre_wifi_busy = wifi_busy;
+ }
+
+ /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */
+ if (bt_link_info->slave_role)
+ psTdmaByte4Modify = 0x1;
+ else
+ psTdmaByte4Modify = 0x0;
+
+ if (pre_psTdmaByte4Modify != psTdmaByte4Modify) {
+
+ force_exec = TRUE;
+ pre_psTdmaByte4Modify = psTdmaByte4Modify;
+ }
+
+ if (!force_exec) {
+ if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) &&
+ (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Skip TDMA because no change TDMA(%s, %d)\n",
+ (coex_dm->cur_ps_tdma_on ? "on" : "off"),
+ coex_dm->cur_ps_tdma);
+ BTC_TRACE(trace_buf);
+ return;
+ }
+ }
+
+ if (coex_dm->cur_ps_tdma_on) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ********** TDMA(on, %d) **********\n",
+ coex_dm->cur_ps_tdma);
+ BTC_TRACE(trace_buf);
+
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8,
+ 0x1); /* enable TBTT nterrupt */
+ } else {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ********** TDMA(off, %d) **********\n",
+ coex_dm->cur_ps_tdma);
+ BTC_TRACE(trace_buf);
+ }
+
+
+
+ if (turn_on) {
+
+ /* enable TBTT nterrupt */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, 0x1);
+
+ switch (type) {
+ default:
+ halbtc8822b1ant_set_fw_pstdma(btcoexist,
+ 0x61, 0x35, 0x03, 0x11, 0x11);
+ break;
+ case 1:
+ halbtc8822b1ant_set_fw_pstdma(btcoexist,
+ 0x61, 0x3a, 0x03, 0x11, 0x10);
+ break;
+ case 3:
+ halbtc8822b1ant_set_fw_pstdma(btcoexist,
+ 0x51, 0x30, 0x03, 0x10, 0x50);
+ break;
+ case 4:
+ halbtc8822b1ant_set_fw_pstdma(btcoexist,
+ 0x51, 0x21, 0x03, 0x10, 0x50);
+ break;
+ case 5:
+ halbtc8822b1ant_set_fw_pstdma(btcoexist,
+ 0x61, 0x15, 0x3, 0x11, 0x11);
+ break;
+ case 6:
+ halbtc8822b1ant_set_fw_pstdma(btcoexist,
+ 0x61, 0x25, 0x3, 0x11, 0x11);
+ break;
+ case 7:
+ halbtc8822b1ant_set_fw_pstdma(btcoexist,
+ 0x51, 0x10, 0x03, 0x10, 0x54 |
+ psTdmaByte4Modify);
+ break;
+ case 8:
+ halbtc8822b1ant_set_fw_pstdma(btcoexist,
+ 0x51, 0x10, 0x03, 0x10, 0x14 |
+ psTdmaByte4Modify);
+ break;
+ case 10:
+ halbtc8822b1ant_set_fw_pstdma(btcoexist,
+ 0x51, 0x10, 0x07, 0x10, 0x55);
+ break;
+ case 11:
+ halbtc8822b1ant_set_fw_pstdma(btcoexist,
+ 0x61, 0x25, 0x03, 0x11, 0x11);
+ break;
+ case 12:
+ halbtc8822b1ant_set_fw_pstdma(btcoexist,
+ 0x51, 0x30, 0x03, 0x10, 0x50 |
+ psTdmaByte4Modify);
+ break;
+ case 13:
+ halbtc8822b1ant_set_fw_pstdma(btcoexist,
+ 0x51, 0x10, 0x07, 0x10, 0x54);
+ break;
+ case 14:
+ halbtc8822b1ant_set_fw_pstdma(btcoexist,
+ 0x51, 0x15, 0x03, 0x10, 0x50 |
+ psTdmaByte4Modify);
+ break;
+ case 15:
+ halbtc8822b1ant_set_fw_pstdma(btcoexist,
+ 0x51, 0x20, 0x03, 0x10, 0x10 |
+ psTdmaByte4Modify);
+ break;
+ case 17:
+ halbtc8822b1ant_set_fw_pstdma(btcoexist,
+ 0x61, 0x10, 0x03, 0x11, 0x14 |
+ psTdmaByte4Modify);
+ break;
+ case 18:
+ halbtc8822b1ant_set_fw_pstdma(btcoexist,
+ 0x51, 0x30, 0x03, 0x10, 0x50);
+ break;
+ case 20:
+ halbtc8822b1ant_set_fw_pstdma(btcoexist,
+ 0x61, 0x30, 0x03, 0x11, 0x10);
+ break;
+ case 21:
+ halbtc8822b1ant_set_fw_pstdma(btcoexist,
+ 0x61, 0x30, 0x03, 0x11, 0x10);
+ break;
+ case 22:
+ halbtc8822b1ant_set_fw_pstdma(btcoexist,
+ 0x61, 0x25, 0x03, 0x11, 0x10);
+ break;
+ case 25:
+ halbtc8822b1ant_set_fw_pstdma(btcoexist,
+ 0x51, 0x3a, 0x3, 0x11, 0x50);
+ break;
+ case 26:
+ halbtc8822b1ant_set_fw_pstdma(btcoexist,
+ 0x51, 0x10, 0x03, 0x10, 0x55);
+ break;
+ case 27:
+ halbtc8822b1ant_set_fw_pstdma(btcoexist,
+ 0x61, 0x10, 0x03, 0x11, 0x15);
+ break;
+ case 32:
+ halbtc8822b1ant_set_fw_pstdma(btcoexist,
+ 0x61, 0x35, 0x3, 0x11, 0x11);
+ break;
+ case 33:
+ halbtc8822b1ant_set_fw_pstdma(btcoexist,
+ 0x61, 0x35, 0x03, 0x11, 0x10);
+ break;
+ case 36:
+ halbtc8822b1ant_set_fw_pstdma(btcoexist,
+ 0x61, 0x50, 0x03, 0x11, 0x10);
+ break;
+ case 37:
+ halbtc8822b1ant_set_fw_pstdma(btcoexist,
+ 0x61, 0x3c, 0x03, 0x11, 0x10);
+ break;
+ case 50:
+ halbtc8822b1ant_set_fw_pstdma(btcoexist,
+ 0x51, 0x4a, 0x3, 0x10, 0x10);
+ break;
+ case 105:
+ halbtc8822b1ant_set_fw_pstdma(btcoexist,
+ 0x51, 0x3f, 0x3, 0x10, 0x50);
+ break;
+
+ }
+ } else {
+
+ switch (type) {
+ case 0:
+ default: /* Software control, Antenna at BT side */
+ halbtc8822b1ant_set_fw_pstdma(btcoexist,
+ 0x0, 0x0, 0x0, 0x0, 0x0);
+ break;
+ case 8: /* PTA Control */
+ halbtc8822b1ant_set_fw_pstdma(btcoexist,
+ 0x8, 0x0, 0x0, 0x0, 0x0);
+ break;
+ case 9: /* Software control, Antenna at WiFi side */
+ halbtc8822b1ant_set_fw_pstdma(btcoexist,
+ 0x0, 0x0, 0x0, 0x0, 0x0);
+ break;
+ case 10: /* under 5G , 0x778=1*/
+ halbtc8822b1ant_set_fw_pstdma(btcoexist,
+ 0x0, 0x0, 0x0, 0x0, 0x0);
+ break;
+ }
+ }
+
+
+ if (!coex_sta->is_set_ps_state_fail) {
+ /* update pre state */
+ coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on;
+ coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
+ }
+}
+
+
+/* rf4 type by efuse, and for ant at main aux inverse use,
+ * because is 2x2, and control types are the same, does not need
+ */
+
+void halbtc8822b1ant_set_rfe_type(IN struct btc_coexist *btcoexist)
+{
+ struct btc_board_info *board_info = &btcoexist->board_info;
+
+ /* Ext switch buffer mux */
+ btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff);
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, 0x3, 0x0);
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, 0x8, 0x0);
+
+ /* the following setup should be got from Efuse in the future */
+ rfe_type->rfe_module_type = board_info->rfe_type;
+
+ rfe_type->ext_ant_switch_ctrl_polarity = 0;
+ rfe_type->ext_ant_switch_exist = TRUE;
+ rfe_type->ext_ant_switch_type = BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT;
+
+#if 0
+ switch (rfe_type->rfe_module_type) {
+ case 0:
+ default:
+ rfe_type->ext_ant_switch_exist = TRUE;
+ rfe_type->ext_ant_switch_type =
+ BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT;
+ break;
+ case 1:
+ rfe_type->ext_ant_switch_exist = TRUE;
+ rfe_type->ext_ant_switch_type =
+ BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT;
+ break;
+ case 2:
+ rfe_type->ext_ant_switch_exist = TRUE;
+ rfe_type->ext_ant_switch_type =
+ BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT;
+ break;
+ case 3:
+ rfe_type->ext_ant_switch_exist = TRUE;
+ rfe_type->ext_ant_switch_type =
+ BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT;
+ break;
+ case 4:
+ rfe_type->ext_ant_switch_exist = TRUE;
+ rfe_type->ext_ant_switch_type =
+ BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT;
+ break;
+ case 5:
+ rfe_type->ext_ant_switch_exist = TRUE;
+ rfe_type->ext_ant_switch_type =
+ BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT;
+ break;
+ case 6:
+ rfe_type->ext_ant_switch_exist = TRUE;
+ rfe_type->ext_ant_switch_type =
+ BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT;
+ break;
+ case 7:
+ rfe_type->ext_ant_switch_exist = TRUE;
+ rfe_type->ext_ant_switch_type =
+ BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT;
+ break;
+ }
+#endif
+
+}
+
+/*anttenna control by bb mac bt antdiv pta to write 0x4c 0xcb4,0xcbd*/
+
+
+void halbtc8822b1ant_set_ext_ant_switch(IN struct btc_coexist *btcoexist,
+ IN boolean force_exec, IN u8 ctrl_type, IN u8 pos_type)
+{
+ boolean switch_polatiry_inverse = FALSE;
+ u8 regval_0xcbd = 0, regval_0x64;
+ u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0;
+
+ /* Ext switch buffer mux */
+ btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff);
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, 0x3, 0x0);
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, 0x8, 0x0);
+
+ if (!rfe_type->ext_ant_switch_exist)
+ return;
+
+ coex_dm->cur_ext_ant_switch_status = (ctrl_type << 8) + pos_type;
+
+ if (!force_exec) {
+ if (coex_dm->pre_ext_ant_switch_status ==
+ coex_dm->cur_ext_ant_switch_status)
+ return;
+ }
+
+ coex_dm->pre_ext_ant_switch_status = coex_dm->cur_ext_ant_switch_status;
+
+ /* swap control polarity if use different switch control polarity*/
+ /* Normal switch polarity for SPDT,
+ * 0xcbd[1:0] = 2b'01 => Ant to BTG, WLA
+ * 0xcbd[1:0] = 2b'10 => Ant to WLG
+ */
+ switch_polatiry_inverse = (rfe_type->ext_ant_switch_ctrl_polarity == 1 ?
+ !switch_polatiry_inverse : switch_polatiry_inverse);
+
+
+ switch (pos_type) {
+ default:
+ case BT_8822B_1ANT_EXT_ANT_SWITCH_TO_BT:
+ case BT_8822B_1ANT_EXT_ANT_SWITCH_TO_NOCARE:
+ case BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLA:
+ case BT_8822B_1ANT_EXT_ANT_SWITCH_TO_S0WLG_S1BT:
+
+ break;
+ case BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLG:
+
+ break;
+ }
+
+
+ if (rfe_type->ext_ant_switch_type ==
+ BT_8822B_1ANT_EXT_ANT_SWITCH_USE_SPDT) {
+ switch (ctrl_type) {
+ default:
+ case BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW:
+ /* 0x4c[23] = 0 */
+ btcoexist->btc_write_1byte_bitmask(
+ btcoexist, 0x4e, 0x80,
+ 0x0);
+ /* 0x4c[24] = 1 */
+ btcoexist->btc_write_1byte_bitmask(
+ btcoexist, 0x4f, 0x01,
+ 0x1);
+ /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin*/
+ btcoexist->btc_write_1byte_bitmask(
+ btcoexist, 0xcb4, 0xff,
+ 0x77);
+
+ /* 0xcbd[1:0] = 2b'01 for no switch_polatiry_inverse,
+ * ANTSWB =1, ANTSW =0
+ */
+ if (pos_type == BT_8822B_1ANT_EXT_ANT_SWITCH_TO_S0WLG_S1BT)
+ regval_0xcbd = 0x3;
+ else if (pos_type == BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLG)
+ regval_0xcbd = (!switch_polatiry_inverse ? 0x2 : 0x1);
+ else
+ regval_0xcbd = (!switch_polatiry_inverse ? 0x1 : 0x2);
+ btcoexist->btc_write_1byte_bitmask(btcoexist,
+ 0xcbd, 0x3, regval_0xcbd);
+
+ break;
+ case BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_PTA:
+ /* 0x4c[23] = 0 */
+ btcoexist->btc_write_1byte_bitmask(
+ btcoexist, 0x4e, 0x80,
+ 0x0);
+ /* 0x4c[24] = 1 */
+ btcoexist->btc_write_1byte_bitmask(
+ btcoexist, 0x4f, 0x01,
+ 0x1);
+ /* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */
+ btcoexist->btc_write_1byte_bitmask(
+ btcoexist, 0xcb4, 0xff,
+ 0x66);
+
+ /* 0xcbd[1:0] = 2b'10 for no switch_polatiry_inverse,
+ * ANTSWB =1, ANTSW =0 @ GNT_BT=1
+ */
+ regval_0xcbd = (!switch_polatiry_inverse ? 0x2 : 0x1);
+ btcoexist->btc_write_1byte_bitmask(
+ btcoexist, 0xcbd, 0x3,
+ regval_0xcbd);
+
+ break;
+ case BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV:
+ /* 0x4c[23] = 0 */
+ btcoexist->btc_write_1byte_bitmask(
+ btcoexist, 0x4e, 0x80,
+ 0x0);
+ /* 0x4c[24] = 1 */
+ btcoexist->btc_write_1byte_bitmask(
+ btcoexist, 0x4f, 0x01,
+ 0x1);
+ btcoexist->btc_write_1byte_bitmask(
+ btcoexist, 0xcb4, 0xff,
+ 0x88);
+
+ /* no regval_0xcbd setup required, because
+ * antenna switch control value by antenna diversity
+ */
+
+ break;
+ case BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_MAC:
+ /* 0x4c[23] = 1 */
+ btcoexist->btc_write_1byte_bitmask(
+ btcoexist, 0x4e, 0x80,
+ 0x1);
+
+ /* 0x64[0] = 1b'0 for no switch_polatiry_inverse,
+ * DPDT_SEL_N =1, DPDT_SEL_P =0
+ */
+ regval_0x64 = (!switch_polatiry_inverse ? 0x0 : 0x1);
+ btcoexist->btc_write_1byte_bitmask(
+ btcoexist, 0x64, 0x1,
+ regval_0x64);
+ break;
+ case BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BT:
+ /* 0x4c[23] = 0 */
+ btcoexist->btc_write_1byte_bitmask(
+ btcoexist, 0x4e, 0x80,
+ 0x0);
+ /* 0x4c[24] = 0 */
+ btcoexist->btc_write_1byte_bitmask(
+ btcoexist, 0x4f, 0x01,
+ 0x0);
+
+ /* no setup required, because antenna switch control
+ * value by BT vendor 0xac[1:0]
+ */
+ break;
+ }
+ }
+
+ u32tmp1 = btcoexist->btc_read_4byte(btcoexist, 0xcbc);
+ u32tmp2 = btcoexist->btc_read_4byte(btcoexist, 0x4c);
+ u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0x64) & 0xff;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], (After Ext Ant switch setup) 0xcbc = 0x%08x, 0x4c = 0x%08x, 0x64= 0x%02x\n",
+ u32tmp1, u32tmp2, u32tmp3);
+ BTC_TRACE(trace_buf);
+
+
+}
+
+/* set gnt_wl gnt_bt control by sw high low, or
+ * hwpta while in power on, ini, wlan off, wlan only, wl2g non-currrent,
+ * wl2g current, wl5g
+ */
+
+
+void halbtc8822b1ant_set_ant_path(IN struct btc_coexist *btcoexist,
+ IN u8 ant_pos_type, IN boolean force_exec,
+ IN u8 phase)
+
+{
+ u8 u8tmp = 0;
+ u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0;
+
+ u32tmp1 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
+ 0x38);
+
+ /* To avoid indirect access fail */
+ if (((u32tmp1 & 0xf000) >> 12) != ((u32tmp1 & 0x0f00) >> 8)) {
+ force_exec = TRUE;
+ coex_sta->gnt_error_cnt++;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex],(Before Ant Setup) 0x38= 0x%x\n",
+ u32tmp1);
+ BTC_TRACE(trace_buf);
+ }
+
+ /* Ext switch buffer mux */
+ btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff);
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, 0x3, 0x0);
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, 0x8, 0x0);
+
+ coex_dm->cur_ant_pos_type = (ant_pos_type << 8) + phase;
+
+ if (!force_exec) {
+ if (coex_dm->cur_ant_pos_type ==
+ coex_dm->pre_ant_pos_type)
+ return;
+ }
+
+ coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type;
+
+#if BT_8822B_1ANT_COEX_DBG
+ u32tmp1 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
+ 0x38);
+ u32tmp2 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
+ 0x54);
+ u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4);
+
+ u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73);
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ********** (Before Ant Setup) 0xcb4 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n",
+ u32tmp3, u8tmp, u32tmp1, u32tmp2);
+ BTC_TRACE(trace_buf);
+#endif
+
+ switch (phase) {
+ case BT_8822B_1ANT_PHASE_COEX_POWERON:
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ********** (set_ant_path - 1ANT_PHASE_COEX_POWERON) **********\n");
+ BTC_TRACE(trace_buf);
+
+ /* set Path control owner to BT at power-on step */
+ halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist,
+ BT_8822B_1ANT_PCO_BTSIDE);
+
+ /* set GNT_BT to SW high */
+ halbtc8822b1ant_ltecoex_set_gnt_bt(btcoexist,
+ BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
+ BT_8822B_1ANT_GNT_CTRL_BY_SW,
+ BT_8822B_1ANT_SIG_STA_SET_TO_HIGH);
+ /* Set GNT_WL to SW high */
+ halbtc8822b1ant_ltecoex_set_gnt_wl(btcoexist,
+ BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
+ BT_8822B_1ANT_GNT_CTRL_BY_SW,
+ BT_8822B_1ANT_SIG_STA_SET_TO_HIGH);
+
+ if (ant_pos_type == BTC_ANT_PATH_AUTO)
+ ant_pos_type = BTC_ANT_PATH_BT;
+
+ coex_sta->run_time_state = FALSE;
+ break;
+ case BT_8822B_1ANT_PHASE_COEX_INIT:
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ********** (set_ant_path - 1ANT_PHASE_COEX_INIT) **********\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b1ant_ltecoex_enable(btcoexist, 0x0);
+
+
+ halbtc8822b1ant_ltecoex_set_coex_table(btcoexist,
+ BT_8822B_1ANT_CTT_WL_VS_LTE,
+ 0xffff);
+
+ halbtc8822b1ant_ltecoex_set_coex_table(btcoexist,
+ BT_8822B_1ANT_CTT_BT_VS_LTE,
+ 0xffff);
+
+ /* set GNT_BT to SW high */
+ halbtc8822b1ant_ltecoex_set_gnt_bt(btcoexist,
+ BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
+ BT_8822B_1ANT_GNT_CTRL_BY_SW,
+ BT_8822B_1ANT_SIG_STA_SET_TO_HIGH);
+
+ /* set GNT_WL to SW low */
+ halbtc8822b1ant_ltecoex_set_gnt_wl(btcoexist,
+ BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
+ BT_8822B_1ANT_GNT_CTRL_BY_SW,
+ BT_8822B_1ANT_SIG_STA_SET_TO_LOW);
+
+ /* set Path control owner to WL at initial step */
+ halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist,
+ BT_8822B_1ANT_PCO_WLSIDE);
+
+ coex_sta->run_time_state = FALSE;
+
+ if (BTC_ANT_PATH_AUTO == ant_pos_type)
+ ant_pos_type = BTC_ANT_PATH_BT;
+
+ break;
+ case BT_8822B_1ANT_PHASE_WLANONLY_INIT:
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ********** (set_ant_path - 1ANT_PHASE_WLANONLY_INIT) **********\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b1ant_ltecoex_enable(btcoexist, 0x0);
+
+ halbtc8822b1ant_ltecoex_set_coex_table(btcoexist,
+ BT_8822B_1ANT_CTT_WL_VS_LTE,
+ 0xffff);
+
+ halbtc8822b1ant_ltecoex_set_coex_table(btcoexist,
+ BT_8822B_1ANT_CTT_BT_VS_LTE,
+ 0xffff);
+
+ /* set GNT_BT to SW Low */
+ halbtc8822b1ant_ltecoex_set_gnt_bt(btcoexist,
+ BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
+ BT_8822B_1ANT_GNT_CTRL_BY_SW,
+ BT_8822B_1ANT_SIG_STA_SET_TO_LOW);
+
+ /* Set GNT_WL to SW high */
+ halbtc8822b1ant_ltecoex_set_gnt_wl(btcoexist,
+ BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
+ BT_8822B_1ANT_GNT_CTRL_BY_SW,
+ BT_8822B_1ANT_SIG_STA_SET_TO_HIGH);
+
+ /* set Path control owner to WL at initial step */
+ halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist,
+ BT_8822B_1ANT_PCO_WLSIDE);
+
+ coex_sta->run_time_state = FALSE;
+
+ if (BTC_ANT_PATH_AUTO == ant_pos_type)
+ ant_pos_type = BTC_ANT_PATH_WIFI;
+
+ break;
+ case BT_8822B_1ANT_PHASE_WLAN_OFF:
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ********** (set_ant_path - 1ANT_PHASE_WLAN_OFF) **********\n");
+ BTC_TRACE(trace_buf);
+
+ /* Disable LTE Coex Function in WiFi side */
+ halbtc8822b1ant_ltecoex_enable(btcoexist, 0x0);
+
+ /* set Path control owner to BT */
+ halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist,
+ BT_8822B_1ANT_PCO_BTSIDE);
+
+ /* Set Ext Ant Switch to BT control at wifi off step */
+ halbtc8822b1ant_set_ext_ant_switch(btcoexist,
+ FORCE_EXEC,
+ BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BT,
+ BT_8822B_1ANT_EXT_ANT_SWITCH_TO_NOCARE);
+
+ coex_sta->run_time_state = FALSE;
+
+ break;
+ case BT_8822B_1ANT_PHASE_2G_RUNTIME:
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ********** (set_ant_path - 1ANT_PHASE_2G_RUNTIME) **********\n");
+ BTC_TRACE(trace_buf);
+
+ /* set GNT_BT to PTA */
+ halbtc8822b1ant_ltecoex_set_gnt_bt(btcoexist,
+ BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
+ BT_8822B_1ANT_GNT_CTRL_BY_PTA,
+ BT_8822B_1ANT_SIG_STA_SET_BY_HW);
+
+ /* Set GNT_WL to PTA */
+ halbtc8822b1ant_ltecoex_set_gnt_wl(btcoexist,
+ BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
+ BT_8822B_1ANT_GNT_CTRL_BY_PTA,
+ BT_8822B_1ANT_SIG_STA_SET_BY_HW);
+
+ /* set Path control owner to WL at runtime step */
+ halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist,
+ BT_8822B_1ANT_PCO_WLSIDE);
+
+ coex_sta->run_time_state = TRUE;
+
+ if (BTC_ANT_PATH_AUTO == ant_pos_type)
+ ant_pos_type = BTC_ANT_PATH_PTA;
+
+ break;
+ case BT_8822B_1ANT_PHASE_5G_RUNTIME:
+ case BT_8822B_1ANT_PHASE_2G_FREERUN_ANT_WL:
+ case BT_8822B_1ANT_PHASE_2G_FREERUN_ANT_BT:
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ********** (set_ant_path - %d)\n", phase);
+ BTC_TRACE(trace_buf);
+
+ /* set GNT_BT to SW Hi */
+ halbtc8822b1ant_ltecoex_set_gnt_bt(btcoexist,
+ BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
+ BT_8822B_1ANT_GNT_CTRL_BY_SW,
+ BT_8822B_1ANT_SIG_STA_SET_TO_HIGH);
+
+ /* Set GNT_WL to SW Hi */
+ halbtc8822b1ant_ltecoex_set_gnt_wl(btcoexist,
+ BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
+ BT_8822B_1ANT_GNT_CTRL_BY_SW,
+ BT_8822B_1ANT_SIG_STA_SET_TO_HIGH);
+
+ /* set Path control owner to WL at runtime step */
+ halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist,
+ BT_8822B_1ANT_PCO_WLSIDE);
+
+ coex_sta->run_time_state = TRUE;
+
+ if (phase == BT_8822B_1ANT_PHASE_2G_FREERUN_ANT_WL)
+ ant_pos_type = BTC_ANT_PATH_WIFI;
+ else if (phase == BT_8822B_1ANT_PHASE_2G_FREERUN_ANT_BT)
+ ant_pos_type = BTC_ANT_PATH_BT;
+ if (BTC_ANT_PATH_AUTO == ant_pos_type)
+ ant_pos_type = BTC_ANT_PATH_WIFI5G;
+
+ break;
+ case BT_8822B_1ANT_PHASE_BTMPMODE:
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ********** (set_ant_path - 1ANT_PHASE_BTMPMODE) **********\n");
+ BTC_TRACE(trace_buf);
+
+ /* Disable LTE Coex Function in WiFi side */
+ halbtc8822b1ant_ltecoex_enable(btcoexist, 0x0);
+
+ /* set GNT_BT to SW Hi */
+ halbtc8822b1ant_ltecoex_set_gnt_bt(btcoexist,
+ BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
+ BT_8822B_1ANT_GNT_CTRL_BY_SW,
+ BT_8822B_1ANT_SIG_STA_SET_TO_HIGH);
+
+ /* Set GNT_WL to SW Lo */
+ halbtc8822b1ant_ltecoex_set_gnt_wl(btcoexist,
+ BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
+ BT_8822B_1ANT_GNT_CTRL_BY_SW,
+ BT_8822B_1ANT_SIG_STA_SET_TO_LOW);
+
+ /* set Path control owner to WL */
+ halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist,
+ BT_8822B_1ANT_PCO_WLSIDE);
+
+ coex_sta->run_time_state = FALSE;
+
+ /* Set Ext Ant Switch to BT side at BT MP mode */
+ if (BTC_ANT_PATH_AUTO == ant_pos_type)
+ ant_pos_type = BTC_ANT_PATH_BT;
+
+ break;
+ case BT_8822B_1ANT_PHASE_MCC_DUALBAND_RUNTIME:
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], (set_ant_path - 1ANT_PHASE_MCC_DUALBAND_RUNTIME)\n");
+ BTC_TRACE(trace_buf);
+
+ /* set GNT_BT to PTA */
+ halbtc8822b1ant_ltecoex_set_gnt_bt(btcoexist,
+ BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
+ BT_8822B_1ANT_GNT_CTRL_BY_PTA,
+ BT_8822B_1ANT_SIG_STA_SET_BY_HW);
+
+ /* Set GNT_WL to PTA */
+ halbtc8822b1ant_ltecoex_set_gnt_wl(btcoexist,
+ BT_8822B_1ANT_GNT_BLOCK_RFC_BB,
+ BT_8822B_1ANT_GNT_CTRL_BY_PTA,
+ BT_8822B_1ANT_SIG_STA_SET_BY_HW);
+
+ /* set Path control owner to WL at runtime step */
+ halbtc8822b1ant_ltecoex_pathcontrol_owner(btcoexist,
+ BT_8822B_1ANT_PCO_WLSIDE);
+
+ coex_sta->run_time_state = TRUE;
+
+ if (ant_pos_type == BTC_ANT_PATH_AUTO)
+ ant_pos_type = BTC_ANT_PATH_PTA;
+
+ break;
+ }
+
+
+ if ((phase != BT_8822B_1ANT_PHASE_WLAN_OFF) &&
+ (phase != BT_8822B_1ANT_PHASE_MCC_DUALBAND_RUNTIME)) {
+ switch (ant_pos_type) {
+ case BTC_ANT_PATH_WIFI:
+ if (phase == BT_8822B_1ANT_PHASE_2G_FREERUN_ANT_WL) {
+ halbtc8822b1ant_set_ext_ant_switch(
+ btcoexist,
+ force_exec,
+ BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW,
+ BT_8822B_1ANT_EXT_ANT_SWITCH_TO_S0WLG_S1BT);
+ } else {
+ halbtc8822b1ant_set_ext_ant_switch(
+ btcoexist,
+ force_exec,
+ BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW,
+ BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLG);
+ }
+ break;
+ case BTC_ANT_PATH_WIFI5G:
+ halbtc8822b1ant_set_ext_ant_switch(
+ btcoexist,
+ force_exec,
+ BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW,
+ BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLA);
+ break;
+ case BTC_ANT_PATH_BT:
+ halbtc8822b1ant_set_ext_ant_switch(
+ btcoexist,
+ force_exec,
+ BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW,
+ BT_8822B_1ANT_EXT_ANT_SWITCH_TO_BT);
+ break;
+ default:
+ case BTC_ANT_PATH_PTA:
+ halbtc8822b1ant_set_ext_ant_switch(
+ btcoexist,
+ force_exec,
+ BT_8822B_1ANT_EXT_ANT_SWITCH_CTRL_BY_PTA,
+ BT_8822B_1ANT_EXT_ANT_SWITCH_TO_NOCARE);
+ break;
+ }
+
+ }
+#if BT_8822B_1ANT_COEX_DBG
+ u32tmp1 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
+ u32tmp2 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
+ u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcbd);
+
+ u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73);
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], (After Ant Setup) 0xcbd = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n",
+ u32tmp3, u8tmp, u32tmp1, u32tmp2);
+ BTC_TRACE(trace_buf);
+
+#endif
+
+}
+
+boolean halbtc8822b1ant_is_common_action(IN struct btc_coexist *btcoexist)
+{
+ boolean common = FALSE, wifi_connected = FALSE, wifi_busy = FALSE;
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+ &wifi_connected);
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+ if (!wifi_connected &&
+ coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n");
+ BTC_TRACE(trace_buf);
+ common = TRUE;
+ } else if (wifi_connected &&
+ (coex_dm->bt_status ==
+ BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE)) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Wifi connected + BT non connected-idle!!\n");
+ BTC_TRACE(trace_buf);
+ common = TRUE;
+ } else if (!wifi_connected &&
+ (BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE ==
+ coex_dm->bt_status)) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Wifi non connected-idle + BT connected-idle!!\n");
+ BTC_TRACE(trace_buf);
+ common = TRUE;
+ } else if (wifi_connected &&
+ (BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE ==
+ coex_dm->bt_status)) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Wifi connected + BT connected-idle!!\n");
+ BTC_TRACE(trace_buf);
+ common = TRUE;
+ } else if (!wifi_connected &&
+ (BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE !=
+ coex_dm->bt_status)) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Wifi non connected-idle + BT Busy!!\n");
+ BTC_TRACE(trace_buf);
+ common = TRUE;
+ } else {
+ if (wifi_busy) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Wifi Connected-Busy + BT Busy!!\n");
+ BTC_TRACE(trace_buf);
+ } else {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Wifi Connected-Idle + BT Busy!!\n");
+ BTC_TRACE(trace_buf);
+ }
+
+ common = FALSE;
+ }
+
+ return common;
+}
+
+void halbtc8822b1ant_action_wifi_freerun(IN struct btc_coexist *btcoexist)
+{
+#if 0
+ struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], under 5g start\n");
+ BTC_TRACE(trace_buf);
+
+ /* for SUMA fine tune */
+ if (bt_link_info->a2dp_only) {
+ halbtc8822b1ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xc8);
+ halbtc8822b1ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 2);
+ halbtc8822b1ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, TRUE);
+ halbtc8822b1ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, TRUE);
+
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8);
+
+ halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC,
+ BT_8822B_1ANT_PHASE_2G_FREERUN_ANT_BT);
+ } else if ((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) {
+ halbtc8822b1ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8);
+ halbtc8822b1ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 10);
+ halbtc8822b1ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, TRUE);
+ halbtc8822b1ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, TRUE);
+
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8);
+
+ halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC,
+ BT_8822B_1ANT_PHASE_2G_FREERUN_ANT_WL);
+ }
+#endif
+}
+
+
+void halbtc8822b1ant_action_bt_whql_test(IN struct btc_coexist *btcoexist)
+{
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex],action_bt_whck_test\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b1ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8);
+ halbtc8822b1ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b1ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+ halbtc8822b1ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8);
+
+ halbtc8822b1ant_set_ant_path(btcoexist,
+ BTC_ANT_PATH_AUTO,
+ NORMAL_EXEC,
+ BT_8822B_1ANT_PHASE_2G_RUNTIME);
+}
+
+
+void halbtc8822b1ant_action_bt_hs(IN struct btc_coexist *btcoexist)
+{
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], action_hs\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b1ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8);
+ halbtc8822b1ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b1ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+ halbtc8822b1ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 5);
+
+ halbtc8822b1ant_set_ant_path(btcoexist,
+ BTC_ANT_PATH_AUTO,
+ NORMAL_EXEC,
+ BT_8822B_1ANT_PHASE_2G_RUNTIME);
+}
+
+
+void halbtc8822b1ant_action_bt_relink(IN struct btc_coexist *btcoexist)
+{
+ struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+ if (((!coex_sta->is_bt_multi_link) && (!bt_link_info->pan_exist)) ||
+ ((bt_link_info->a2dp_exist) && (bt_link_info->hid_exist))) {
+
+ halbtc8822b1ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8);
+ halbtc8822b1ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b1ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+ halbtc8822b1ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8);
+ }
+}
+
+
+void halbtc8822b1ant_action_bt_idle(IN struct btc_coexist *btcoexist)
+{
+ boolean wifi_busy = FALSE;
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+ halbtc8822b1ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8);
+ halbtc8822b1ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b1ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+ halbtc8822b1ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+
+ if (!wifi_busy) {
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 32);
+
+ } else { /* if wl busy */
+ /* for initiator scan on */
+ if ((coex_sta->bt_ble_scan_type & 0x2) &&
+ (BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+ coex_dm->bt_status)) {
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 36);
+ } else {
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 33);
+ }
+ }
+}
+
+
+/*"""bt inquiry"""" + wifi any + bt any*/
+
+void halbtc8822b1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist)
+{
+
+ struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+ boolean wifi_connected = FALSE, wifi_busy = FALSE,
+ bt_busy = FALSE;
+ boolean wifi_scan = FALSE, link = FALSE, roam = FALSE;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ********** (bt inquiry) **********\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b1ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8);
+ halbtc8822b1ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b1ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+ halbtc8822b1ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected);
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+ btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan);
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
+
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ********** scan = %d, link =%d, roam = %d**********\n",
+ wifi_scan, link, roam);
+ BTC_TRACE(trace_buf);
+
+ if ((link) || (roam) || (coex_sta->wifi_is_high_pri_task)) {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ********** (bt inquiry wifi connect or scan ) **********\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 1);
+
+ } else if ((wifi_scan) && (coex_sta->bt_create_connection)) {
+
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 22);
+
+ } else if ((!wifi_connected) && (!wifi_scan)) {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ********** (bt inquiry wifi non connect) **********\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8);
+
+ } else if ((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist)) {
+
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 22);
+ } else if (bt_link_info->a2dp_exist) {
+
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 23);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 32);
+ } else if (wifi_scan) {
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 20);
+ } else if (wifi_busy) {
+
+ /*aaaa->55aa for bt connect while wl busy*/
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 23);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 32);
+ } else {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ********** (bt inquiry wifi connect) **********\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 23);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 32);
+ }
+
+}
+
+
+void halbtc8822b1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist
+ *btcoexist)
+{
+ struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+ boolean wifi_connected = FALSE, wifi_busy = FALSE;
+ u32 wifi_bw = 1;
+
+ halbtc8822b1ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8);
+ halbtc8822b1ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b1ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+ halbtc8822b1ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected);
+ btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+ if (!wifi_busy)
+ wifi_busy = coex_sta->gl_wifi_busy;
+
+ if (coex_sta->msft_mr_exist) {
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8);
+
+ } else if (bt_link_info->sco_exist) {
+ if (coex_sta->is_bt_multi_link) {
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 25);
+ } else {
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 5);
+ }
+ } else if (coex_sta->is_hid_rcu) {
+ if (coex_sta->voice_over_HOGP) {
+ if (!wifi_busy)
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
+ else if (coex_sta->bt_coex_supported_feature & BIT(11))
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
+ else
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+
+ if (wifi_busy)
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 37);
+ else
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 6);
+ } else {
+ if (!wifi_busy)
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
+ else if (coex_sta->bt_coex_supported_feature & BIT(11))
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
+ else
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
+
+ if (wifi_busy && coex_sta->wl_noisy_level == 0)
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 36);
+ else if (wifi_busy)
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 37);
+ else
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 6);
+ }
+ } else {
+ if (coex_sta->is_hid_low_pri_tx_overhead) {
+ if (coex_sta->hid_busy_num < 2)
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
+ else
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 18);
+ } else if (coex_sta->hid_busy_num < 2) {
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 11);
+ } else if (wifi_bw == 0) { /* if 11bg mode */
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 11);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 11);
+ } else {
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 11);
+ }
+ }
+}
+
+void halbtc8822b1ant_action_bt_mr(IN struct btc_coexist *btcoexist)
+{
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], RunCoexistMechanism(), microsoft MR!!\n");
+ BTC_TRACE(trace_buf);
+
+ if (coex_sta->wl_center_channel <= 14) {
+ halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+ NORMAL_EXEC,
+ BT_8822B_1ANT_PHASE_2G_FREERUN_ANT_WL);
+
+ halbtc8822b1ant_action_bt_sco_hid_only_busy(btcoexist);
+
+ /* Enter MIMO Power Save, 0:enable */
+ halbtc8822b1ant_mimo_ps(btcoexist, NORMAL_EXEC, 0);
+ } else {
+ halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+ NORMAL_EXEC,
+ BT_8822B_1ANT_PHASE_5G_RUNTIME);
+
+ halbtc8822b1ant_action_bt_sco_hid_only_busy(btcoexist);
+
+ /* No MIMO Power Save, 3:disable */
+ halbtc8822b1ant_mimo_ps(btcoexist, NORMAL_EXEC, 3);
+ }
+}
+
+
+void halbtc8822b1ant_action_rf4ce(IN struct btc_coexist *btcoexist)
+{
+ halbtc8822b1ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8);
+ halbtc8822b1ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b1ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+ halbtc8822b1ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 50);
+}
+
+
+void halbtc8822b1ant_action_wifi_under5g(IN struct btc_coexist *btcoexist)
+{
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], under 5g start\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b1ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8);
+ halbtc8822b1ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b1ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+ halbtc8822b1ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+
+ halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC,
+ BT_8822B_1ANT_PHASE_5G_RUNTIME);
+
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8);
+}
+
+void halbtc8822b1ant_action_wifi_only(IN struct btc_coexist *btcoexist)
+{
+ boolean wifi_under_5g = FALSE, rf4ce_enabled = FALSE,
+ wifi_connected = FALSE;
+
+ halbtc8822b1ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8);
+ halbtc8822b1ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b1ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+ halbtc8822b1ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_RF4CE_CONNECTED, &rf4ce_enabled);
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected);
+
+#if 0
+ if (wifi_under_5g) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ********** (wlan only -- under 5g ) **********\n");
+ BTC_TRACE(trace_buf);
+ halbtc8822b1ant_action_wifi_under5g(btcoexist);
+ } else
+#endif
+ if ((rf4ce_enabled) && (wifi_connected)) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ********** (wlan only -- rf4ce enable ) **********\n");
+ BTC_TRACE(trace_buf);
+ halbtc8822b1ant_action_rf4ce(btcoexist);
+ } else {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ********** (wlan only -- under 2g ) **********\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
+ halbtc8822b1ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 8);
+
+ halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC,
+ BT_8822B_1ANT_PHASE_2G_RUNTIME);
+ }
+}
+
+void halbtc8822b1ant_action_wifi_native_lps(IN struct btc_coexist *btcoexist)
+{
+ halbtc8822b1ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8);
+ halbtc8822b1ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b1ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+ halbtc8822b1ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8);
+}
+
+void halbtc8822b1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist,
+ IN u8 multi_port_type)
+{
+ struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+ boolean miracast_plus_bt = FALSE;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex],action_wifi_multi_port\n");
+ BTC_TRACE(trace_buf);
+
+ if (bt_link_info->bt_link_exist)
+ miracast_plus_bt = TRUE;
+ else
+ miracast_plus_bt = FALSE;
+
+ btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
+ &miracast_plus_bt);
+
+ halbtc8822b1ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8);
+ halbtc8822b1ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b1ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+ halbtc8822b1ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+
+ if (multi_port_type == BTC_MULTIPORT_MCC_DUAL_BAND)
+ halbtc8822b1ant_set_ant_path(btcoexist,
+ BTC_ANT_PATH_AUTO,
+ NORMAL_EXEC,
+ BT_8822B_1ANT_PHASE_MCC_DUALBAND_RUNTIME);
+ else
+ halbtc8822b1ant_set_ant_path(btcoexist,
+ BTC_ANT_PATH_AUTO,
+ NORMAL_EXEC,
+ BT_8822B_1ANT_PHASE_2G_RUNTIME);
+
+
+ /* for A2DP + miracast + DL */
+ if (multi_port_type == BTC_MULTIPORT_MCC_DUAL_BAND) {
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 25);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8);
+ } else if (multi_port_type == BTC_MULTIPORT_SCC) {
+ if (bt_link_info->a2dp_exist) {
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 17);
+ } else if (bt_link_info->pan_exist) {
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 33);
+ } else {
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8);
+ }
+ } else { //BTC_MULTIPORT_MCC_DUAL_CHANNEL
+ if (!bt_link_info->pan_exist)
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
+ else
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
+
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8);
+ }
+}
+
+void halbtc8822b1ant_action_wifi_linkscan_process(IN struct btc_coexist
+ *btcoexist)
+{
+ struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+ halbtc8822b1ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8);
+ halbtc8822b1ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b1ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+ halbtc8822b1ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+
+ if (bt_link_info->pan_exist) {
+
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 22);
+ } else if (bt_link_info->a2dp_exist) {
+
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 27);
+ } else {
+
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 21);
+ }
+}
+
+void halbtc8822b1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist
+ *btcoexist)
+{
+ struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+ boolean wifi_busy = FALSE, wifi_turbo = FALSE,
+ wifi_cckdeadlock_ap = FALSE, bt_slave_latency = FALSE,
+ ap_enable = FALSE;
+ u32 wifi_bw = 1;
+ static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+ u8 wifi_rssi_state;
+ static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+ u8 wifi_rssi_state2;
+ u8 iot_peer = BTC_IOT_PEER_UNKNOWN, tb_type;
+
+ btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+ btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, &coex_sta->scan_ap_num);
+ btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer);
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &ap_enable);
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "############# [BTCoex], scan_ap_num = %d, wl_noisy_level = %d\n",
+ coex_sta->scan_ap_num, coex_sta->wl_noisy_level);
+ BTC_TRACE(trace_buf);
+
+ if (!wifi_busy)
+ wifi_busy = coex_sta->gl_wifi_busy;
+
+ if ((wifi_busy) && (coex_sta->wl_noisy_level == 0))
+ wifi_turbo = TRUE;
+
+ if (iot_peer == BTC_IOT_PEER_ATHEROS && coex_sta->cck_lock_ever)
+ wifi_cckdeadlock_ap = TRUE;
+
+ if (coex_sta->bt_coex_supported_feature & BIT(11))
+ bt_slave_latency = TRUE;
+ else
+ bt_slave_latency = FALSE;
+
+ wifi_rssi_state = halbtc8822b1ant_wifi_rssi_state(btcoexist,
+ &prewifi_rssi_state, 2,
+ 40, 0);
+
+ wifi_rssi_state2 = halbtc8822b1ant_wifi_rssi_state(btcoexist,
+ &prewifi_rssi_state2, 2,
+ 42, 0);
+
+ if ((btcoexist->board_info.customerID == RT_CID_LENOVO_CHINA) &&
+ (coex_sta->scan_ap_num <= 10) &&
+ (iot_peer == BTC_IOT_PEER_ATHEROS)) {
+
+ if (((bt_link_info->a2dp_only) && (coex_sta->is_bt_multi_link) &&
+ (coex_sta->hid_pair_cnt == 0)) ||
+ ((bt_link_info->a2dp_exist) && (bt_link_info->pan_exist))) {
+ /* for some case, OPP may disappear during CPT_for_WiFi test */
+ /* for CPT_for_WiFi */
+ if (BTC_RSSI_LOW(wifi_rssi_state2)) {
+ halbtc8822b1ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 20);
+
+ if (wifi_busy) {
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 22);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 105);
+ } else {
+ //halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 22);
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 23);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 13);
+ }
+ } else { /* for CPT_for_BT */
+ halbtc8822b1ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 24);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 13);
+ }
+
+ return;
+ }
+ }
+
+ halbtc8822b1ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
+
+ if ((bt_link_info->a2dp_exist) && (coex_sta->is_bt_a2dp_sink)) {
+ if (ap_enable)
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+ else if (coex_sta->wl_noisy_level == 0 && wifi_cckdeadlock_ap)
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 13);
+ else
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6);
+
+ if (ap_enable)
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8);
+ else
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 12);
+ } else if (bt_link_info->a2dp_only) { /* A2DP */
+ if (wifi_busy && (coex_sta->bt_ble_scan_type & 0x2)) {
+ if (coex_sta->wl_noisy_level == 0 && wifi_cckdeadlock_ap)
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 10);
+ else if (coex_sta->wl_noisy_level == 0 && !wifi_cckdeadlock_ap)
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 9);
+ else
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
+ } else if (wifi_busy && !(coex_sta->bt_ble_scan_type & 0x2)) {
+ if (coex_sta->wl_noisy_level == 0 && wifi_cckdeadlock_ap)
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 13);
+ else
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
+ } else { /*wifi idle */
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
+ }
+
+ if (coex_sta->connect_ap_period_cnt > 0 || !wifi_busy)
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 26);
+ else
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 7);
+ } else if (((bt_link_info->a2dp_exist) &&
+ (bt_link_info->pan_exist)) ||
+ (bt_link_info->hid_exist && bt_link_info->a2dp_exist &&
+ bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */
+
+ if (coex_sta->wl_noisy_level == 0 && wifi_cckdeadlock_ap)
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 14);
+ else if (bt_link_info->hid_exist)
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
+ else if (wifi_turbo)
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 19);
+ else
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+
+ if (wifi_busy)
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 13);
+ else
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 14);
+ } else if (bt_link_info->hid_exist && coex_sta->is_hid_rcu &&
+ coex_sta->voice_over_HOGP && bt_link_info->a2dp_exist) {
+ /* RCU voice + A2DP */
+ /* Change coex table if slave latency support or not */
+ if (wifi_busy && !bt_slave_latency) {
+ if (coex_sta->wl_noisy_level == 0 && wifi_cckdeadlock_ap)
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 10);
+ else if (coex_sta->wl_noisy_level == 0 && !wifi_cckdeadlock_ap)
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 9);
+ else
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
+ } else if (wifi_busy && bt_slave_latency) {
+ if (coex_sta->wl_noisy_level == 0 && wifi_cckdeadlock_ap)
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 13);
+ else
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
+ } else { /*wifi idle */
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
+ }
+
+ if (coex_sta->connect_ap_period_cnt > 0 || !wifi_busy)
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 10);
+ else
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 13);
+ } else if (bt_link_info->hid_exist && coex_sta->is_hid_rcu &&
+ bt_link_info->a2dp_exist) {
+ /* RCU + A2DP */
+ /* Change coex table if slave latency support or not */
+ if (wifi_busy && !bt_slave_latency) {
+ if (coex_sta->wl_noisy_level == 0 && wifi_cckdeadlock_ap)
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 10);
+ else if (coex_sta->wl_noisy_level == 0 && !wifi_cckdeadlock_ap)
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 9);
+ else
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
+ } else if (wifi_busy && bt_slave_latency) {
+ if (coex_sta->wl_noisy_level == 0 && wifi_cckdeadlock_ap)
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 13);
+ else
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
+ } else { /*wifi idle */
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
+ }
+
+ if (coex_sta->connect_ap_period_cnt > 0 || !wifi_busy)
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 26);
+ else
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 7);
+ } else if (bt_link_info->hid_exist && bt_link_info->a2dp_exist) {
+ /* HID+A2DP */
+ if (coex_sta->wl_noisy_level == 0 && wifi_cckdeadlock_ap) {
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 14);
+ } else if (wifi_bw == 0) {/* if 11bg mode */
+ if (coex_sta->hid_busy_num < 2) /* for 2/18-4/18 HID lag @ Asus */
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
+ else
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 21);
+
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 7);
+ } else {
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 7);
+ }
+ /* PAN(OPP,FTP), HID+PAN(OPP,FTP) */
+
+ } else if ((bt_link_info->pan_only) || (bt_link_info->hid_exist && bt_link_info->pan_exist)) {
+
+ if ((bt_link_info->pan_only) &&
+ (btcoexist->board_info.customerID == RT_CID_LENOVO_CHINA) &&
+ (wifi_busy) && (BTC_RSSI_HIGH(wifi_rssi_state2))) {
+
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 10);
+
+ } else {
+
+ if (coex_sta->cck_lock_ever) {
+ if ((bt_link_info->hid_exist) && (coex_sta->hid_busy_num < 2))
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 14);
+ else
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 13);
+ } else if (bt_link_info->hid_exist) {
+ if (coex_sta->hid_busy_num < 2)
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
+ else
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
+ } else if (wifi_turbo)
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 19);
+ else
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+
+ if (!wifi_busy)
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 4);
+ else
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 3);
+ }
+ } else {
+ /* BT no-profile busy (0x9) */
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 33);
+ }
+
+}
+
+
+
+/* wifi connected input point:
+ * to set different ps and tdma case (+bt different case)
+ */
+
+
+/*wifi not connected + bt action*/
+
+void halbtc8822b1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist)
+{
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ********** (wifi not connect) **********\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b1ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8);
+ halbtc8822b1ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b1ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+ halbtc8822b1ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+
+ /* tdma and coex table */
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b1ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 8);
+
+ halbtc8822b1ant_set_ant_path(btcoexist,
+ BTC_ANT_PATH_AUTO,
+ NORMAL_EXEC,
+ BT_8822B_1ANT_PHASE_2G_RUNTIME);
+}
+
+
+void halbtc8822b1ant_action_wifi_connected(IN struct btc_coexist *btcoexist)
+{
+ struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+ boolean wifi_busy = FALSE, rf4ce_enabled = FALSE;
+ boolean wifi_under_5g = FALSE;
+ u8 wifi_rssi_state;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], CoexForWifiConnect()===>\n");
+ BTC_TRACE(trace_buf);
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_RF4CE_CONNECTED, &rf4ce_enabled);
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+#if 0
+ if (wifi_under_5g) {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], CoexForWifiConnect(), return for wifi is under 5g<===\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b1ant_action_wifi_under5g(btcoexist);
+
+ return;
+ }
+#endif
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], CoexForWifiConnect(), return for wifi is under 2g<===\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b1ant_set_ant_path(btcoexist,
+ BTC_ANT_PATH_AUTO,
+ NORMAL_EXEC,
+ BT_8822B_1ANT_PHASE_2G_RUNTIME);
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+ if ((coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_ACL_BUSY) ||
+ (coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY)) {
+
+ if (bt_link_info->hid_only) /* HID only */
+ halbtc8822b1ant_action_bt_sco_hid_only_busy(btcoexist);
+ else
+ halbtc8822b1ant_action_wifi_connected_bt_acl_busy(btcoexist);
+
+ } else if (coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_SCO_BUSY)
+ halbtc8822b1ant_action_bt_sco_hid_only_busy(btcoexist);
+ else if (rf4ce_enabled)
+ halbtc8822b1ant_action_rf4ce(btcoexist);
+ else
+ halbtc8822b1ant_action_bt_idle(btcoexist);
+
+}
+
+
+
+void halbtc8822b1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist)
+{
+
+ u8 algorithm = 0;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ********** (run sw coex mech) **********\n");
+ BTC_TRACE(trace_buf);
+ algorithm = halbtc8822b1ant_action_algorithm(btcoexist);
+ coex_dm->cur_algorithm = algorithm;
+
+ if (halbtc8822b1ant_is_common_action(btcoexist)) {
+
+ } else {
+ switch (coex_dm->cur_algorithm) {
+ case BT_8822B_1ANT_COEX_ALGO_SCO:
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Action algorithm = SCO.\n");
+ BTC_TRACE(trace_buf);
+ break;
+ case BT_8822B_1ANT_COEX_ALGO_HID:
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Action algorithm = HID.\n");
+ BTC_TRACE(trace_buf);
+ break;
+ case BT_8822B_1ANT_COEX_ALGO_A2DP:
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Action algorithm = A2DP.\n");
+ BTC_TRACE(trace_buf);
+ break;
+ case BT_8822B_1ANT_COEX_ALGO_A2DP_PANHS:
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Action algorithm = A2DP+PAN(HS).\n");
+ BTC_TRACE(trace_buf);
+ break;
+ case BT_8822B_1ANT_COEX_ALGO_PANEDR:
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Action algorithm = PAN(EDR).\n");
+ BTC_TRACE(trace_buf);
+ break;
+ case BT_8822B_1ANT_COEX_ALGO_PANHS:
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Action algorithm = HS mode.\n");
+ BTC_TRACE(trace_buf);
+ break;
+ case BT_8822B_1ANT_COEX_ALGO_PANEDR_A2DP:
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Action algorithm = PAN+A2DP.\n");
+ BTC_TRACE(trace_buf);
+ break;
+ case BT_8822B_1ANT_COEX_ALGO_PANEDR_HID:
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Action algorithm = PAN(EDR)+HID.\n");
+ BTC_TRACE(trace_buf);
+ break;
+ case BT_8822B_1ANT_COEX_ALGO_HID_A2DP_PANEDR:
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Action algorithm = HID+A2DP+PAN.\n");
+ BTC_TRACE(trace_buf);
+ break;
+ case BT_8822B_1ANT_COEX_ALGO_HID_A2DP:
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Action algorithm = HID+A2DP.\n");
+ BTC_TRACE(trace_buf);
+ break;
+ default:
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Action algorithm = coexist All Off!!\n");
+ BTC_TRACE(trace_buf);
+ break;
+ }
+ coex_dm->pre_algorithm = coex_dm->cur_algorithm;
+ }
+}
+
+static
+void halbtc8822b1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist)
+{
+
+ struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+ boolean wifi_connected = FALSE, bt_hs_on = FALSE;
+ boolean bt_ctrl_agg_buf_size = FALSE;
+ u8 agg_buf_size = 5, mcc_dualband = BTC_MULTIPORT_SCC;
+ u32 wifi_link_status = 0;
+ u32 num_of_wifi_link = 0, wifi_bw;
+ u8 iot_peer = BTC_IOT_PEER_UNKNOWN;
+ boolean wifi_under_5g = FALSE;
+ boolean scan = FALSE, link = FALSE, roam = FALSE, under_4way = FALSE;
+ u8 wifi_central_chnl = 0;
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &under_4way);
+
+ btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected);
+
+ btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
+ &wifi_central_chnl);
+ coex_sta->wl_center_channel = wifi_central_chnl;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], RunCoexistMechanism()===>\n");
+ BTC_TRACE(trace_buf);
+
+ if (btcoexist->manual_control) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n");
+ BTC_TRACE(trace_buf);
+ return;
+ }
+
+ if (btcoexist->stop_coex_dm) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n");
+ BTC_TRACE(trace_buf);
+ return;
+ }
+
+ if (coex_sta->under_ips) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], RunCoexistMechanism(), wifi is under IPS !!!\n");
+ BTC_TRACE(trace_buf);
+ return;
+ }
+
+ if (!coex_sta->run_time_state) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], RunCoexistMechanism(), return for run_time_state = FALSE !!!\n");
+ BTC_TRACE(trace_buf);
+ return;
+ }
+
+ if (coex_sta->freeze_coexrun_by_btinfo) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], RunCoexistMechanism(), return for freeze_coexrun_by_btinfo\n");
+ BTC_TRACE(trace_buf);
+ return;
+ }
+
+ if ((coex_sta->msft_mr_exist) && (wifi_connected)) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], RunCoexistMechanism(), microsoft MR!!\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b1ant_action_bt_mr(btcoexist);
+ return;
+ }
+
+ /* No MIMO Power Save, 3:disable */
+ halbtc8822b1ant_mimo_ps(btcoexist, NORMAL_EXEC, 3);
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_DUAL_BAND_CONNECTED, &mcc_dualband);
+ if (mcc_dualband == BTC_MULTIPORT_MCC_DUAL_BAND) {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], RunCoexistMechanism(), mcc dual band!!\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b1ant_action_wifi_multi_port(btcoexist, BTC_MULTIPORT_MCC_DUAL_BAND);
+ return;
+ }
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+ if ((wifi_under_5g) &&
+ (coex_sta->switch_band_notify_to != BTC_SWITCH_TO_24G) &&
+ (coex_sta->switch_band_notify_to != BTC_SWITCH_TO_24G_NOFORSCAN)) {
+ halbtc8822b1ant_action_wifi_under5g(btcoexist);
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], WiFi is under 5G!!!\n");
+ BTC_TRACE(trace_buf);
+ return;
+ } else {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], WiFi is under 2G!!!\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+ NORMAL_EXEC,
+ BT_8822B_1ANT_PHASE_2G_RUNTIME);
+ }
+
+halbtc8822b1ant_post_state_to_bt(btcoexist,
+ BT_8822B_1ANT_SCOREBOARD_BTCQDDR,
+ TRUE);
+
+
+ if ((coex_sta->under_lps) && (!coex_sta->force_lps_ctrl) &&
+ (!coex_sta->acl_busy)) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], RunCoexistMechanism(), wifi is under LPS !!!\n");
+ BTC_TRACE(trace_buf);
+ halbtc8822b1ant_action_wifi_native_lps(btcoexist);
+ return;
+ }
+
+ if (coex_sta->bt_whck_test) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT is under WHCK TEST!!!\n");
+ BTC_TRACE(trace_buf);
+ halbtc8822b1ant_action_bt_whql_test(btcoexist);
+ return;
+ }
+
+ if (coex_sta->bt_disabled) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT is disabled !!!\n");
+ BTC_TRACE(trace_buf);
+ halbtc8822b1ant_action_wifi_only(btcoexist);
+ return;
+ }
+
+ if (coex_sta->c2h_bt_inquiry_page) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT is under inquiry/page scan !!\n");
+ BTC_TRACE(trace_buf);
+ halbtc8822b1ant_action_bt_inquiry(btcoexist);
+ return;
+ }
+
+ if ((coex_sta->is_setupLink) &&
+ (coex_sta->bt_relink_downcount != 0)) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT is re-link !!!\n");
+ BTC_TRACE(trace_buf);
+ halbtc8822b1ant_action_bt_relink(btcoexist);
+ return;
+ }
+
+ btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
+ &wifi_link_status);
+
+ num_of_wifi_link = wifi_link_status >> 16;
+
+ if ((num_of_wifi_link >= 2) ||
+ (wifi_link_status & WIFI_P2P_GO_CONNECTED)) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n",
+ num_of_wifi_link, wifi_link_status);
+ BTC_TRACE(trace_buf);
+
+ if (scan || link || roam || under_4way) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n",
+ scan, link, roam, under_4way);
+ BTC_TRACE(trace_buf);
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], wifi is under linkscan process + Multi-Port !!\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b1ant_action_wifi_linkscan_process(btcoexist);
+ } else
+ halbtc8822b1ant_action_wifi_multi_port(btcoexist, mcc_dualband);
+
+ return;
+ }
+
+ if ((bt_link_info->bt_link_exist) && (wifi_connected)) {
+
+ btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer);
+
+ if (iot_peer == BTC_IOT_PEER_CISCO) {
+
+ if (wifi_bw == BTC_WIFI_BW_HT40)
+ halbtc8822b1ant_limited_rx(btcoexist,
+ NORMAL_EXEC, FALSE, TRUE, 0x10);
+ else
+ halbtc8822b1ant_limited_rx(btcoexist,
+ NORMAL_EXEC, FALSE, TRUE, 0x8);
+ }
+ }
+
+ /* just print debug message */
+ halbtc8822b1ant_run_sw_coexist_mechanism(btcoexist);
+
+ if ((BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+ coex_dm->bt_status) ||
+ (BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE ==
+ coex_dm->bt_status)) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "############# [BTCoex], BT Is idle\n");
+ BTC_TRACE(trace_buf);
+ halbtc8822b1ant_action_bt_idle(btcoexist);
+ return;
+ }
+
+ if (scan || link || roam || under_4way) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n",
+ scan, link, roam, under_4way);
+ BTC_TRACE(trace_buf);
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], wifi is under linkscan process!!\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b1ant_action_wifi_linkscan_process(btcoexist);
+ } else if (wifi_connected) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], wifi is under connected!!\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b1ant_action_wifi_connected(btcoexist);
+ } else {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], wifi is under not-connected!!\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b1ant_action_wifi_not_connected(btcoexist);
+ }
+
+}
+
+static
+void halbtc8822b1ant_init_coex_dm(IN struct btc_coexist *btcoexist)
+{
+ /* force to reset coex mechanism */
+
+ halbtc8822b1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, FALSE);
+
+ /* sw all off */
+ coex_sta->pop_event_cnt = 0;
+ coex_sta->cnt_RemoteNameReq = 0;
+ coex_sta->cnt_ReInit = 0;
+ coex_sta->cnt_setupLink = 0;
+ coex_sta->cnt_IgnWlanAct = 0;
+ coex_sta->cnt_Page = 0;
+ coex_sta->cnt_RoleSwitch = 0;
+ coex_sta->switch_band_notify_to = BTC_NOT_SWITCH;
+
+ coex_sta->pop_event_cnt = 0;
+
+ halbtc8822b1ant_query_bt_info(btcoexist);
+}
+
+static
+void halbtc8822b1ant_init_hw_config(IN struct btc_coexist *btcoexist,
+ IN boolean back_up, IN boolean wifi_only)
+{
+
+ u8 u8tmp = 0, i = 0;
+ u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], 1Ant Init HW Config!!\n");
+ BTC_TRACE(trace_buf);
+
+ u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcbc);
+ u32tmp1 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
+ u32tmp2 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ********** (Before Init HW config) 0xcbc = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n",
+ u32tmp3, u32tmp1, u32tmp2);
+ BTC_TRACE(trace_buf);
+
+#if 0
+ coex_sta->bt_coex_supported_feature = 0;
+ coex_sta->bt_coex_supported_version = 0;
+ coex_sta->bt_ble_scan_type = 0;
+ coex_sta->bt_ble_scan_para[0] = 0;
+ coex_sta->bt_ble_scan_para[1] = 0;
+ coex_sta->bt_ble_scan_para[2] = 0;
+#endif
+ coex_sta->bt_reg_vendor_ac = 0xffff;
+ coex_sta->bt_reg_vendor_ae = 0xffff;
+ coex_sta->isolation_btween_wb = BT_8822B_1ANT_DEFAULT_ISOLATION;
+ coex_sta->gnt_error_cnt = 0;
+ coex_sta->bt_relink_downcount = 0;
+ coex_sta->is_set_ps_state_fail = FALSE;
+ coex_sta->cnt_set_ps_state_fail = 0;
+
+ for (i = 0; i <= 9; i++)
+ coex_sta->bt_afh_map[i] = 0;
+
+ /* Setup RF front end type */
+ halbtc8822b1ant_set_rfe_type(btcoexist);
+
+ if ((rfe_type->rfe_module_type == 2) ||
+ (rfe_type->rfe_module_type == 4))
+ halbtc8822b1ant_post_state_to_bt(btcoexist,
+ BT_8822B_1ANT_SCOREBOARD_EXTFEM, TRUE);
+ else
+ halbtc8822b1ant_post_state_to_bt(btcoexist,
+ BT_8822B_1ANT_SCOREBOARD_EXTFEM, FALSE);
+
+ /* 0xf0[15:12] --> Chip Cut information */
+ coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist,
+ 0xf1) & 0xf0) >> 4;
+
+ /* enable TBTT nterrupt */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, 0x1);
+
+ /* BT report packet sample rate */
+ /* 0x790[5:0]=0x5 */
+ u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790);
+ u8tmp &= 0xc0;
+ u8tmp |= 0x5;
+ btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp);
+
+ /* Enable BT counter statistics */
+ btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1);
+
+ /* Enable PTA (3-wire function form BT side) */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1);
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x41, 0x02, 0x1);
+
+ /* Enable PTA (tx/rx signal form WiFi side) */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4c6, 0x10, 0x1);
+ /*GNT_BT=1 while select both */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x763, 0x10, 0x1);
+
+ halbtc8822b1ant_enable_gnt_to_gpio(btcoexist, TRUE);
+
+#if 0
+ if (btcoexist->btc_read_1byte(btcoexist, 0x80) == 0xc6)
+ halbtc8822b1ant_post_state_to_bt(btcoexist,
+ BT_8822B_1ANT_SCOREBOARD_ONOFF, TRUE);
+#endif
+
+ /* PTA parameter */
+ halbtc8822b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
+ halbtc8822b1ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 8);
+
+ /* Antenna config */
+ if (coex_sta->is_rf_state_off) {
+
+ halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+ FORCE_EXEC,
+ BT_8822B_1ANT_PHASE_WLAN_OFF);
+
+ btcoexist->stop_coex_dm = TRUE;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ********** halbtc8822b1ant_init_hw_config (RF Off)**********\n");
+ BTC_TRACE(trace_buf);
+ } else if (wifi_only) {
+
+ coex_sta->concurrent_rx_mode_on = FALSE;
+ halbtc8822b1ant_set_ant_path(btcoexist,
+ BTC_ANT_PATH_WIFI,
+ FORCE_EXEC,
+ BT_8822B_1ANT_PHASE_WLANONLY_INIT);
+ btcoexist->stop_coex_dm = TRUE;
+ } else {
+
+ coex_sta->concurrent_rx_mode_on = TRUE;
+
+ halbtc8822b1ant_set_ant_path(btcoexist,
+ BTC_ANT_PATH_AUTO,
+ FORCE_EXEC,
+ BT_8822B_1ANT_PHASE_COEX_INIT);
+ btcoexist->stop_coex_dm = FALSE;
+ }
+
+ u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcbc);
+ u32tmp1 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
+ u32tmp2 = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ********** (After Init HW config) 0xcbc = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n",
+ u32tmp3, u32tmp1, u32tmp2);
+ BTC_TRACE(trace_buf);
+
+}
+
+#if 0
+void halbtc8822b1ant_wifi_info_notify(IN struct btc_coexist *btcoexist)
+{
+ u8 h2c_para[4] = {0};
+ u8 opcode_ver = 0;
+ u8 ap_num = 0;
+ s32 wifi_rssi = 0;
+ boolean wifi_busy = FALSE;
+
+ btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
+ btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, &ap_num);
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+ h2c_para[0] = ap_num; /* AP number */
+ h2c_para[1] = (u8)wifi_busy; /* Busy */
+ h2c_para[2] = (u8)wifi_rssi; /* RSSI */
+
+ btcoexist->btc_coex_h2c_process(btcoexist, COL_OP_WIFI_INFO_NOTIFY,
+ opcode_ver, &h2c_para[0], 3);
+}
+
+void halbtc8822b1ant_setManual(IN struct btc_coexist *btcoexist,
+ IN boolean manual)
+{
+ u8 h2c_para[4] = {0};
+ u8 opcode_ver = 0;
+ u8 set_type = 0;
+
+ if (manual)
+ set_type = 1;
+ else
+ set_type = 0;
+
+ h2c_para[0] = set_type; /* set_type */
+
+ btcoexist->btc_coex_h2c_process(btcoexist, COL_OP_SET_CONTROL,
+ opcode_ver,
+ &h2c_para[0], 1);
+}
+
+/* ************************************************************
+ * work around function start with wa_halbtc8822b1ant_
+ * ************************************************************
+ * ************************************************************
+ * extern function start with ex_halbtc8822b1ant_
+ * ************************************************************ */
+
+void ex_halbtc8822b1ant_power_on_setting(IN struct btc_coexist *btcoexist)
+{
+ coex_sta->is_rf_state_off = FALSE;
+
+}
+void ex_halbtc8822b1ant_pre_load_firmware(IN struct btc_coexist *btcoexist)
+{}
+void ex_halbtc8822b1ant_init_hw_config(IN struct btc_coexist *btcoexist,
+ IN boolean wifi_only)
+{}
+static
+void ex_halbtc8822b1ant_init_coex_dm(IN struct btc_coexist *btcoexist)
+{}
+void ex_halbtc8822b1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type)
+{
+ u8 h2c_para[4] = {0};
+ u8 opcode_ver = 0;
+ u8 ips_notify = 0;
+
+ if (BTC_IPS_ENTER == type) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], IPS ENTER notify\n");
+ BTC_TRACE(trace_buf);
+ ips_notify = 1;
+ } else if (BTC_IPS_LEAVE == type) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], IPS LEAVE notify\n");
+ BTC_TRACE(trace_buf);
+ }
+
+ h2c_para[0] = ips_notify; /* IPS notify */
+ h2c_para[1] = 0xff; /* LPS notify */
+ h2c_para[2] = 0xff; /* RF state notify */
+ h2c_para[3] = 0xff; /* pnp notify */
+
+ btcoexist->btc_coex_h2c_process(btcoexist,
+ COL_OP_WIFI_POWER_STATE_NOTIFY,
+ opcode_ver, &h2c_para[0], 4);
+}
+void ex_halbtc8822b1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type)
+{
+ u8 h2c_para[4] = {0};
+ u8 opcode_ver = 0;
+ u8 lps_notify = 0;
+
+ if (BTC_LPS_ENABLE == type) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], LPS ENABLE notify\n");
+ BTC_TRACE(trace_buf);
+ lps_notify = 1;
+ } else if (BTC_LPS_DISABLE == type) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], LPS DISABLE notify\n");
+ BTC_TRACE(trace_buf);
+ }
+
+ h2c_para[0] = 0xff; /* IPS notify */
+ h2c_para[1] = lps_notify; /* LPS notify */
+ h2c_para[2] = 0xff; /* RF state notify */
+ h2c_para[3] = 0xff; /* pnp notify */
+
+ btcoexist->btc_coex_h2c_process(btcoexist,
+ COL_OP_WIFI_POWER_STATE_NOTIFY,
+ opcode_ver, &h2c_para[0], 4);
+}
+
+void ex_halbtc8822b1ant_scan_notify(IN struct btc_coexist *btcoexist,
+ IN u8 type)
+{
+ u8 h2c_para[4] = {0};
+ u8 opcode_ver = 0;
+ u8 scan_start = 0;
+ boolean under_4way = FALSE;
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
+ &under_4way);
+ if (BTC_SCAN_START == type) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], SCAN START notify\n");
+ BTC_TRACE(trace_buf);
+ scan_start = 1;
+ } else {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], SCAN FINISH notify\n");
+ BTC_TRACE(trace_buf);
+ }
+
+ h2c_para[0] = scan_start; /* scan notify */
+ h2c_para[1] = 0xff; /* connect notify */
+ h2c_para[2] = 0xff; /* specific packet notify */
+ if (under_4way)
+ h2c_para[3] = 1; /* under 4way progress */
+ else
+ h2c_para[3] = 0;
+
+ btcoexist->btc_coex_h2c_process(btcoexist, COL_OP_WIFI_PROGRESS_NOTIFY,
+ opcode_ver, &h2c_para[0], 4);
+}
+
+void ex_halbtc8822b1ant_connect_notify(IN struct btc_coexist *btcoexist,
+ IN u8 type)
+{
+ u8 h2c_para[4] = {0};
+ u8 opcode_ver = 0;
+ u8 connect_start = 0;
+ boolean under_4way = FALSE;
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
+ &under_4way);
+ if (BTC_ASSOCIATE_START == type) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], CONNECT START notify\n");
+ BTC_TRACE(trace_buf);
+ connect_start = 1;
+ } else {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], CONNECT FINISH notify\n");
+ BTC_TRACE(trace_buf);
+ }
+
+ h2c_para[0] = 0xff; /* scan notify */
+ h2c_para[1] = connect_start; /* connect notify */
+ h2c_para[2] = 0xff; /* specific packet notify */
+ if (under_4way)
+ h2c_para[3] = 1; /* under 4way progress */
+ else
+ h2c_para[3] = 0;
+
+ btcoexist->btc_coex_h2c_process(btcoexist, COL_OP_WIFI_PROGRESS_NOTIFY,
+ opcode_ver, &h2c_para[0], 4);
+}
+
+void ex_halbtc8822b1ant_media_status_notify(IN struct btc_coexist *btcoexist,
+ IN u8 type)
+{
+ u32 wifi_bw;
+ u8 wifi_central_chnl;
+ u8 h2c_para[5] = {0};
+ u8 opcode_ver = 0;
+ u8 port = 0, connected = 0, freq = 0, bandwidth = 0, iot_peer = 0;
+ boolean wifi_under_5g = FALSE;
+
+ if (BTC_MEDIA_CONNECT == type)
+ connected = 1;
+
+ btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+ bandwidth = (u8)wifi_bw;
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+ if (wifi_under_5g)
+ freq = 1;
+ else
+ freq = 0;
+ btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
+ &wifi_central_chnl);
+ btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer);
+
+ /* port need to be implemented in the future (p2p port, ...) */
+ h2c_para[0] = (connected << 4) | port;
+ h2c_para[1] = (freq << 4) | bandwidth;
+ h2c_para[2] = wifi_central_chnl;
+ h2c_para[3] = iot_peer;
+ btcoexist->btc_coex_h2c_process(btcoexist, COL_OP_WIFI_STATUS_NOTIFY,
+ opcode_ver, &h2c_para[0], 4);
+}
+
+void ex_halbtc8822b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
+ IN u8 type)
+{
+ u8 h2c_para[4] = {0};
+ u8 opcode_ver = 0;
+ u8 connect_start = 0;
+ boolean under_4way = FALSE;
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
+ &under_4way);
+
+ h2c_para[0] = 0xff; /* scan notify */
+ h2c_para[1] = 0xff; /* connect notify */
+ h2c_para[2] = type; /* specific packet notify */
+ if (under_4way)
+ h2c_para[3] = 1; /* under 4way progress */
+ else
+ h2c_para[3] = 0;
+
+ btcoexist->btc_coex_h2c_process(btcoexist, COL_OP_WIFI_PROGRESS_NOTIFY,
+ opcode_ver, &h2c_para[0], 4);
+}
+
+void ex_halbtc8822b1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
+ IN u8 *tmp_buf, IN u8 length)
+{}
+void ex_halbtc8822b1ant_rf_status_notify(IN struct btc_coexist *btcoexist,
+ IN u8 type)
+{
+ u8 h2c_para[4] = {0};
+ u8 opcode_ver = 0;
+ u8 rfstate_notify = 0;
+
+ if (BTC_RF_ON == type) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], RF is turned ON!!\n");
+ BTC_TRACE(trace_buf);
+ rfstate_notify = 1;
+ coex_sta->is_rf_state_off = FALSE;
+ } else if (BTC_RF_OFF == type) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], RF is turned OFF!!\n");
+ BTC_TRACE(trace_buf);
+ coex_sta->is_rf_state_off = TRUE;
+ }
+
+ h2c_para[0] = 0xff; /* IPS notify */
+ h2c_para[1] = 0xff; /* LPS notify */
+ h2c_para[2] = rfstate_notify; /* RF state notify */
+ h2c_para[3] = 0xff; /* pnp notify */
+
+ btcoexist->btc_coex_h2c_process(btcoexist,
+ COL_OP_WIFI_POWER_STATE_NOTIFY,
+ opcode_ver, &h2c_para[0], 4);
+}
+
+void ex_halbtc8822b1ant_halt_notify(IN struct btc_coexist *btcoexist)
+{}
+void ex_halbtc8822b1ant_pnp_notify(IN struct btc_coexist *btcoexist,
+ IN u8 pnp_state)
+{
+ u8 h2c_para[4] = {0};
+ u8 opcode_ver = 0;
+ u8 pnp_notify = 0;
+
+ if (BTC_WIFI_PNP_SLEEP == pnp_state) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Pnp notify to SLEEP\n");
+ BTC_TRACE(trace_buf);
+ pnp_notify = 1;
+ } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Pnp notify to WAKE UP\n");
+ BTC_TRACE(trace_buf);
+ }
+
+ h2c_para[0] = 0xff; /* IPS notify */
+ h2c_para[1] = 0xff; /* LPS notify */
+ h2c_para[2] = 0xff; /* RF state notify */
+ h2c_para[3] = pnp_notify; /* pnp notify */
+
+ btcoexist->btc_coex_h2c_process(btcoexist,
+ COL_OP_WIFI_POWER_STATE_NOTIFY,
+ opcode_ver, &h2c_para[0], 4);
+}
+
+void ex_halbtc8822b1ant_coex_dm_reset(IN struct btc_coexist *btcoexist)
+{}
+void ex_halbtc8822b1ant_periodical(IN struct btc_coexist *btcoexist)
+{
+
+ halbtc8822b1ant_wifi_info_notify(btcoexist);
+}
+
+void ex_halbtc8822b1ant_display_coex_info(IN struct btc_coexist *btcoexist)
+{
+ struct btc_board_info *board_info = &btcoexist->board_info;
+ struct btc_stack_info *stack_info = &btcoexist->stack_info;
+ struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+ u8 *cli_buf = btcoexist->cli_buf;
+ u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0;
+ u16 u16tmp[4];
+ u32 u32tmp[4];
+ u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck;
+ u32 fw_ver = 0, bt_patch_ver = 0, bt_coex_ver = 0;
+ static u8 pop_report_in_10s = 0;
+ u32 phyver = 0;
+ boolean lte_coex_on = FALSE;
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n ============[BT Coexist info]============");
+ CL_PRINTF(cli_buf);
+
+ if (btcoexist->manual_control) {
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n ============[Under Manual Control]============");
+ CL_PRINTF(cli_buf);
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n ==========================================");
+ CL_PRINTF(cli_buf);
+ }
+ if (btcoexist->stop_coex_dm) {
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n ============[Coex is STOPPED]============");
+ CL_PRINTF(cli_buf);
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n ==========================================");
+ CL_PRINTF(cli_buf);
+ }
+
+ if (psd_scan->ant_det_try_count == 0) {
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %d/ %d/ %s / %d",
+ "Ant PG Num/ Mech/ Pos/ RFE",
+ board_info->pg_ant_num, board_info->btdm_ant_num,
+ (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT
+ ? "Main" : "Aux"),
+ rfe_type->rfe_module_type);
+ CL_PRINTF(cli_buf);
+ } else {
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %d/ %d/ %s/ %d (%d/%d/%d)",
+ "Ant PG Num/ Mech(Ant_Det)/ Pos/ RFE",
+ board_info->pg_ant_num,
+ board_info->btdm_ant_num_by_ant_det,
+ (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT
+ ? "Main" : "Aux"),
+ rfe_type->rfe_module_type,
+ psd_scan->ant_det_try_count,
+ psd_scan->ant_det_fail_count,
+ psd_scan->ant_det_result);
+ CL_PRINTF(cli_buf);
+
+ if (board_info->btdm_ant_det_finish) {
+ if (psd_scan->ant_det_result != 12)
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
+ "Ant Det PSD Value",
+ psd_scan->ant_det_peak_val);
+ else
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %d",
+ "Ant Det PSD Value",
+ psd_scan->ant_det_psd_scan_peak_val / 100);
+
+ CL_PRINTF(cli_buf);
+ }
+ }
+
+ btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
+ btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %d_%x/ 0x%x/ 0x%x(%d)",
+ "CoexVer/ FwVer/ PatchVer",
+ glcoex_ver_date_8822b_1ant, glcoex_ver_8822b_1ant, fw_ver,
+ bt_patch_ver, bt_patch_ver);
+ CL_PRINTF(cli_buf);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ",
+ "Wifi channel informed to BT",
+ coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
+ coex_dm->wifi_chnl_info[2]);
+ CL_PRINTF(cli_buf);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %s/ %d",
+ "HiPr/ Locking/ warn/ Locked/ Noisy",
+ (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"),
+ (coex_sta->cck_lock ? "Yes" : "No"),
+ (coex_sta->cck_lock_warn ? "Yes" : "No"),
+ (coex_sta->cck_lock_ever ? "Yes" : "No"),
+ coex_sta->wl_noisy_level);
+ CL_PRINTF(cli_buf);
+
+ /* wifi status */
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+ "============[Wifi Status]============");
+ CL_PRINTF(cli_buf);
+ btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+ "============[BT Status]============");
+ CL_PRINTF(cli_buf);
+
+ pop_report_in_10s++;
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d/ %d] ",
+ "BT [status/ rssi/ retryCnt/ popCnt]",
+ ((coex_sta->bt_disabled) ? ("disabled") : ((
+ coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page scan")
+ : ((BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+ coex_dm->bt_status) ? "non-connected idle" :
+ ((BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)
+ ? "connected-idle" : "busy")))),
+ coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt,
+ coex_sta->pop_event_cnt);
+ CL_PRINTF(cli_buf);
+
+ if (pop_report_in_10s >= 5) {
+ coex_sta->pop_event_cnt = 0;
+ pop_report_in_10s = 0;
+ }
+
+ if (coex_sta->num_of_profile != 0)
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %s%s%s%s%s",
+ "Profiles",
+ ((bt_link_info->a2dp_exist) ? "A2DP," : ""),
+ ((bt_link_info->sco_exist) ? "SCO," : ""),
+ ((bt_link_info->hid_exist) ?
+ ((coex_sta->hid_busy_num >= 2) ? "HID(4/18)," : "HID(2/18),") : ""),
+ ((bt_link_info->pan_exist) ? "PAN," : ""),
+ ((coex_sta->voice_over_HOGP) ? "Voice" : ""));
+ else
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = None", "Profiles");
+
+ CL_PRINTF(cli_buf);
+
+ if (bt_link_info->a2dp_exist) {
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s",
+ "A2DP Rate/Bitpool/Auto_Slot",
+ ((coex_sta->is_A2DP_3M) ? "3M" : "No_3M"),
+ coex_sta->a2dp_bit_pool,
+ ((coex_sta->is_autoslot) ? "On" : "Off"));
+ CL_PRINTF(cli_buf);
+ }
+
+ if (bt_link_info->hid_exist) {
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+ "HID PairNum/Forbid_Slot",
+ coex_sta->hid_pair_cnt,
+ coex_sta->forbidden_slot
+ );
+ CL_PRINTF(cli_buf);
+ }
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %s/ 0x%x/ 0x%x",
+ "Role/IgnWlanAct/Feature/BLEScan",
+ ((bt_link_info->slave_role) ? "Slave" : "Master"),
+ ((coex_dm->cur_ignore_wlan_act) ? "Yes":"No"),
+ coex_sta->bt_coex_supported_feature,
+ coex_sta->bt_ble_scan_type);
+ CL_PRINTF(cli_buf);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d",
+ "ReInit/ReLink/IgnWlact/Page/NameReq",
+ coex_sta->cnt_ReInit,
+ coex_sta->cnt_setupLink,
+ coex_sta->cnt_IgnWlanAct,
+ coex_sta->cnt_Page,
+ coex_sta->cnt_RemoteNameReq
+ );
+ CL_PRINTF(cli_buf);
+
+ halbtc8822b1ant_read_score_board(btcoexist, &u16tmp[0]);
+
+ if ((coex_sta->bt_reg_vendor_ae == 0xffff) ||
+ (coex_sta->bt_reg_vendor_ac == 0xffff))
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = x/ x/ %04x",
+ "0xae[4]/0xac[1:0]/Scoreboard", u16tmp[0]);
+ else
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = 0x%x/ 0x%x/ %04x",
+ "0xae[4]/0xac[1:0]/Scoreboard",
+ ((coex_sta->bt_reg_vendor_ae & BIT(4))>>4),
+ coex_sta->bt_reg_vendor_ac & 0x3, u16tmp[0]);
+ CL_PRINTF(cli_buf);
+
+ for (i = 0; i < BT_INFO_SRC_8822B_1ANT_MAX; i++) {
+ if (coex_sta->bt_info_c2h_cnt[i]) {
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)",
+ glbt_info_src_8822b_1ant[i],
+ coex_sta->bt_info_c2h[i][0],
+ coex_sta->bt_info_c2h[i][1],
+ coex_sta->bt_info_c2h[i][2],
+ coex_sta->bt_info_c2h[i][3],
+ coex_sta->bt_info_c2h[i][4],
+ coex_sta->bt_info_c2h[i][5],
+ coex_sta->bt_info_c2h[i][6],
+ coex_sta->bt_info_c2h_cnt[i]);
+ CL_PRINTF(cli_buf);
+ }
+ }
+
+
+ if (btcoexist->manual_control)
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+ "============[mechanisms] (before Manual)============");
+ else
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+ "============[mechanisms]============");
+ CL_PRINTF(cli_buf);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
+ "SM[LowPenaltyRA]",
+ coex_dm->cur_low_penalty_ra);
+ CL_PRINTF(cli_buf);
+
+ ps_tdma_case = coex_dm->cur_ps_tdma;
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (%s,%s)",
+ "PS TDMA",
+ coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],
+ coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],
+ coex_dm->ps_tdma_para[4], ps_tdma_case,
+ (coex_dm->cur_ps_tdma_on ? "On" : "Off"),
+ (coex_dm->auto_tdma_adjust ? "Adj" : "Fix"));
+
+ CL_PRINTF(cli_buf);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
+ "WL/BT Coex Table Type",
+ coex_sta->coex_table_type);
+ CL_PRINTF(cli_buf);
+
+ u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
+ u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
+ u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
+ "0x6c0/0x6c4/0x6c8(coexTable)",
+ u32tmp[0], u32tmp[1], u32tmp[2]);
+ CL_PRINTF(cli_buf);
+
+ u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
+ u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc);
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
+ "0x778/0x6cc/IgnWlanAct",
+ u8tmp[0], u32tmp[0], coex_dm->cur_ignore_wlan_act);
+ CL_PRINTF(cli_buf);
+
+ u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
+ 0xa0);
+ u32tmp[1] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
+ 0xa4);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+ "LTE Coex Table W_L/B_L",
+ u32tmp[0] & 0xffff, u32tmp[1] & 0xffff);
+ CL_PRINTF(cli_buf);
+
+ u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
+ 0xa8);
+ u32tmp[1] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
+ 0xac);
+ u32tmp[2] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
+ 0xb0);
+ u32tmp[3] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
+ 0xb4);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+ "LTE Break Table W_L/B_L/L_W/L_B",
+ u32tmp[0] & 0xffff, u32tmp[1] & 0xffff,
+ u32tmp[2] & 0xffff, u32tmp[3] & 0xffff);
+ CL_PRINTF(cli_buf);
+
+ /* Hw setting */
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+ "============[Hw setting]============");
+ CL_PRINTF(cli_buf);
+#if 0
+ u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430);
+ u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434);
+ u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a);
+ u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456);
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x",
+ "0x430/0x434/0x42a/0x456",
+ u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]);
+ CL_PRINTF(cli_buf);
+#endif
+
+ u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
+ u32tmp[1] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
+ u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %s",
+ "LTE CoexOn/Path Ctrl Owner",
+ (int)((u32tmp[0]&BIT(7)) >> 7),
+ ((u8tmp[0]&BIT(2)) ? "WL" : "BT"));
+ CL_PRINTF(cli_buf);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+ "LTE 3Wire/OPMode/UART/UARTMode",
+ (int)((u32tmp[0]&BIT(6)) >> 6),
+ (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4),
+ (int)((u32tmp[0]&BIT(3)) >> 3),
+ (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0))));
+ CL_PRINTF(cli_buf);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %s",
+ "GNT_WL_SWCtrl/GNT_BT_SWCtrl/Dbg",
+ (int)((u32tmp[0]&BIT(12)) >> 12),
+ (int)((u32tmp[0]&BIT(14)) >> 14),
+ ((u8tmp[0]&BIT(3)) ? "On" : "Off"));
+ CL_PRINTF(cli_buf);
+
+ u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+ "GNT_WL/GNT_BT/LTE_Busy/UART_Busy",
+ (int)((u32tmp[0]&BIT(2)) >> 2),
+ (int)((u32tmp[0]&BIT(3)) >> 3),
+ (int)((u32tmp[0]&BIT(1)) >> 1), (int)(u32tmp[0]&BIT(0)));
+ CL_PRINTF(cli_buf);
+
+
+ u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6);
+ u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+ "0x4c6[4]/0x40[5] (WL/BT PTA)",
+ (int)((u8tmp[0] & BIT(4)) >> 4),
+ (int)((u8tmp[1] & BIT(5)) >> 5));
+ CL_PRINTF(cli_buf);
+
+ u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
+ u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
+ u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x953);
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ %s",
+ "0x550(bcn ctrl)/0x522/4-RxAGC",
+ u32tmp[0], u8tmp[0], (u8tmp[1] & 0x2) ? "On" : "Off");
+ CL_PRINTF(cli_buf);
+
+ u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xda0);
+ u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xda4);
+ u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0xda8);
+ u32tmp[3] = btcoexist->btc_read_4byte(btcoexist, 0xcf0);
+
+ u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xa5b);
+ u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xa5c);
+
+ fa_ofdm = ((u32tmp[0] & 0xffff0000) >> 16) + ((u32tmp[1] & 0xffff0000)
+ >> 16) + (u32tmp[1] & 0xffff) + (u32tmp[2] & 0xffff) +
+ ((u32tmp[3] & 0xffff0000) >> 16) + (u32tmp[3] &
+ 0xffff);
+ fa_cck = (u8tmp[0] << 8) + u8tmp[1];
+
+ u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xc50);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+ "0xc50/OFDM-CCA/OFDM-FA/CCK-FA",
+ u32tmp[1] & 0xff, u32tmp[0] & 0xffff, fa_ofdm, fa_cck);
+ CL_PRINTF(cli_buf);
+
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+ "CRC_OK CCK/11g/11n/11n-Agg",
+ coex_sta->crc_ok_cck, coex_sta->crc_ok_11g,
+ coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_agg);
+ CL_PRINTF(cli_buf);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+ "CRC_Err CCK/11g/11n/11n-Agg",
+ coex_sta->crc_err_cck, coex_sta->crc_err_11g,
+ coex_sta->crc_err_11n, coex_sta->crc_err_11n_agg);
+ CL_PRINTF(cli_buf);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+ "0x770(high-pri rx/tx)",
+ coex_sta->high_priority_rx, coex_sta->high_priority_tx);
+ CL_PRINTF(cli_buf);
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+ "0x774(low-pri rx/tx)",
+ coex_sta->low_priority_rx, coex_sta->low_priority_tx);
+ CL_PRINTF(cli_buf);
+#if (BT_AUTO_REPORT_ONLY_8822B_1ANT == 1)
+ /* halbtc8822b1ant_monitor_bt_ctr(btcoexist); */
+#endif
+ btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
+}
+void ex_halbtc8822b1ant_antenna_detection(IN struct btc_coexist *btcoexist,
+ IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
+{}
+void ex_halbtc8822b1ant_display_ant_detection(IN struct btc_coexist *btcoexist)
+{}
+void ex_halbtc8822b1ant_dbg_control(IN struct btc_coexist *btcoexist,
+ IN u8 op_code, IN u8 op_len, IN u8 *pdata)
+{
+ switch (op_code) {
+ case BTC_DBG_SET_COEX_MANUAL_CTRL: {
+ boolean manual = (boolean) *pdata;
+
+ halbtc8822b1ant_setManual(btcoexist, manual);
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+#else
+void ex_halbtc8822b1ant_power_on_setting(IN struct btc_coexist *btcoexist)
+{
+ struct btc_board_info *board_info = &btcoexist->board_info;
+ u8 u8tmp = 0x0;
+ u16 u16tmp = 0x0;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "xxxxxxxxxxxxxxxx Execute 8822b 1-Ant PowerOn Setting!! xxxxxxxxxxxxxxxx\n");
+ BTC_TRACE(trace_buf);
+
+ btcoexist->stop_coex_dm = TRUE;
+ coex_sta->is_rf_state_off = FALSE;
+
+ /* enable BB, REG_SYS_FUNC_EN such that we can write 0x948 correctly. */
+ u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2);
+ btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1));
+
+ /* Setup RF front end type */
+ halbtc8822b1ant_set_rfe_type(btcoexist);
+
+ /* Set Antenna Path to BT side */
+ halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC,
+ BT_8822B_1ANT_PHASE_COEX_POWERON);
+
+ /* set WLAN_ACT = 0 */
+ /* btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4); */
+
+ /* SD1 Chunchu red x issue */
+ btcoexist->btc_write_1byte(btcoexist, 0xff1a, 0x0);
+
+ halbtc8822b1ant_enable_gnt_to_gpio(btcoexist, TRUE);
+
+ /* S0 or S1 setting and Local register setting
+ * (By the setting fw can get ant number, S0/S1, ... info)
+ */
+ /* Local setting bit define */
+ /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */
+ /* BIT1: "0" for internal switch; "1" for external switch */
+ /* BIT2: "0" for one antenna; "1" for two antenna */
+ /* NOTE: here default all internal switch and 1-antenna ==>
+ * BIT1=0 and BIT2=0
+ */
+
+ u8tmp = 0;
+ board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;
+
+ if (btcoexist->chip_interface == BTC_INTF_PCI)
+ btcoexist->btc_write_local_reg_1byte(btcoexist, 0x3e0, u8tmp);
+ else if (btcoexist->chip_interface == BTC_INTF_USB)
+ btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp);
+ else if (btcoexist->chip_interface == BTC_INTF_SDIO)
+ btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, u8tmp);
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ********** LTE coex Reg 0x38 (Power-On) = 0x%x\n",
+ halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38));
+ BTC_TRACE(trace_buf);
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ********** MAC Reg 0x70/ BB Reg 0xcbc (Power-On) = 0x%x / 0x%x\n",
+ btcoexist->btc_read_4byte(btcoexist, 0x70),
+ btcoexist->btc_read_4byte(btcoexist, 0xcbc));
+ BTC_TRACE(trace_buf);
+
+}
+
+void ex_halbtc8822b1ant_pre_load_firmware(IN struct btc_coexist *btcoexist)
+{
+}
+
+void ex_halbtc8822b1ant_init_hw_config(IN struct btc_coexist *btcoexist,
+ IN boolean wifi_only)
+{
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ********** (ini hw config) **********\n");
+
+ halbtc8822b1ant_init_hw_config(btcoexist, TRUE, wifi_only);
+ btcoexist->stop_coex_dm = FALSE;
+}
+
+void ex_halbtc8822b1ant_init_coex_dm(IN struct btc_coexist *btcoexist)
+{
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Coex Mechanism Init!!\n");
+ BTC_TRACE(trace_buf);
+
+ btcoexist->stop_coex_dm = FALSE;
+
+ halbtc8822b1ant_init_coex_dm(btcoexist);
+
+ halbtc8822b1ant_query_bt_info(btcoexist);
+}
+
+
+
+void ex_halbtc8822b1ant_display_simple_coex_info(IN struct btc_coexist *btcoexist)
+{
+ struct btc_board_info *board_info = &btcoexist->board_info;
+ struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+ u8 *cli_buf = btcoexist->cli_buf;
+ u32 bt_patch_ver = 0, bt_coex_ver = 0;
+ static u8 cnt = 0;
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n _____[BT Coexist info]____");
+ CL_PRINTF(cli_buf);
+
+ if (btcoexist->manual_control) {
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n __[Under Manual Control]_");
+ CL_PRINTF(cli_buf);
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n _________________________");
+ CL_PRINTF(cli_buf);
+ }
+ if (btcoexist->stop_coex_dm) {
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n ____[Coex is STOPPED]____");
+ CL_PRINTF(cli_buf);
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n _________________________");
+ CL_PRINTF(cli_buf);
+ }
+
+ if (!coex_sta->bt_disabled) {
+ if (coex_sta->bt_coex_supported_feature == 0)
+ btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_FEATURE,
+ &coex_sta->bt_coex_supported_feature);
+
+ if ((coex_sta->bt_coex_supported_version == 0) ||
+ (coex_sta->bt_coex_supported_version == 0xffff))
+ btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_VERSION,
+ &coex_sta->bt_coex_supported_version);
+
+ if (coex_sta->bt_reg_vendor_ac == 0xffff)
+ coex_sta->bt_reg_vendor_ac = (u16)(
+ btcoexist->btc_get_bt_reg(btcoexist, 3,
+ 0xac) & 0xffff);
+
+ if (coex_sta->bt_reg_vendor_ae == 0xffff)
+ coex_sta->bt_reg_vendor_ae = (u16)(
+ btcoexist->btc_get_bt_reg(btcoexist, 3,
+ 0xae) & 0xffff);
+
+ btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER,
+ &bt_patch_ver);
+ btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver;
+
+ if (coex_sta->num_of_profile > 0) {
+ cnt++;
+
+ if (cnt >= 3) {
+ btcoexist->btc_get_bt_afh_map_from_bt(btcoexist, 0,
+ &coex_sta->bt_afh_map[0]);
+ cnt = 0;
+ }
+ }
+ }
+
+ // BT coex. info.
+ if (psd_scan->ant_det_try_count == 0) {
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %d/ %d/ %s / %d",
+ "Ant PG Num/ Mech/ Pos/ RFE",
+ board_info->pg_ant_num, board_info->btdm_ant_num,
+ (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT
+ ? "Main" : "Aux"),
+ rfe_type->rfe_module_type);
+ CL_PRINTF(cli_buf);
+ } else {
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %d/ %d/ %s/ %d (%d/%d/%d)",
+ "Ant PG Num/ Mech(Ant_Det)/ Pos/ RFE",
+ board_info->pg_ant_num,
+ board_info->btdm_ant_num_by_ant_det,
+ (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT
+ ? "Main" : "Aux"),
+ rfe_type->rfe_module_type,
+ psd_scan->ant_det_try_count,
+ psd_scan->ant_det_fail_count,
+ psd_scan->ant_det_result);
+ CL_PRINTF(cli_buf);
+
+ if (board_info->btdm_ant_det_finish) {
+
+ if (psd_scan->ant_det_result != 12)
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %s",
+ "Ant Det PSD Value",
+ psd_scan->ant_det_peak_val);
+ else
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %d",
+ "Ant Det PSD Value",
+ psd_scan->ant_det_psd_scan_peak_val
+ / 100);
+ CL_PRINTF(cli_buf);
+ }
+ }
+
+ bt_coex_ver = ((coex_sta->bt_coex_supported_version & 0xff00) >> 8);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)",
+ "CoexVer WL/ BT_Desired/ BT_Report",
+ glcoex_ver_date_8822b_1ant, glcoex_ver_8822b_1ant,
+ glcoex_ver_btdesired_8822b_1ant,
+ bt_coex_ver,
+ (bt_coex_ver == 0xff ? "Unknown" :
+ (coex_sta->bt_disabled ? "BT-disable" :
+ (bt_coex_ver >= glcoex_ver_btdesired_8822b_1ant ?
+ "Match" : "Mis-Match"))));
+ CL_PRINTF(cli_buf);
+
+ // BT Status
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %s",
+ "BT status",
+ ((coex_sta->bt_disabled) ? ("disabled") : ((
+ coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page")
+ : ((BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+ coex_dm->bt_status) ? "non-connected idle" :
+ ((coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE)
+ ? "connected-idle" : "busy")))));
+ CL_PRINTF(cli_buf);
+
+ // HW Settings
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+ "0x770(Hi-pri rx/tx)",
+ coex_sta->high_priority_rx, coex_sta->high_priority_tx);
+ CL_PRINTF(cli_buf);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s",
+ "0x774(Lo-pri rx/tx)",
+ coex_sta->low_priority_rx, coex_sta->low_priority_tx,
+ (bt_link_info->slave_role ? "(Slave!!)" : (
+ coex_sta->is_tdma_btautoslot_hang ? "(auto-slot hang!!)" : "")));
+ CL_PRINTF(cli_buf);
+
+}
+
+
+void ex_halbtc8822b1ant_display_coex_info(IN struct btc_coexist *btcoexist)
+{
+ struct btc_board_info *board_info = &btcoexist->board_info;
+ struct btc_stack_info *stack_info = &btcoexist->stack_info;
+ struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+ u8 *cli_buf = btcoexist->cli_buf;
+ u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0;
+ u16 u16tmp[4];
+ u32 u32tmp[4];
+ u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck;
+ u32 fw_ver = 0, bt_patch_ver = 0, bt_coex_ver = 0;
+ static u8 pop_report_in_10s = 0;
+ u32 phyver = 0;
+ boolean lte_coex_on = FALSE;
+ static u8 cnt = 0;
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n ============[BT Coexist info]============");
+ CL_PRINTF(cli_buf);
+
+ if (btcoexist->manual_control) {
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n ============[Under Manual Control]============");
+ CL_PRINTF(cli_buf);
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n ==========================================");
+ CL_PRINTF(cli_buf);
+ }
+ if (btcoexist->stop_coex_dm) {
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n ============[Coex is STOPPED]============");
+ CL_PRINTF(cli_buf);
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n ==========================================");
+ CL_PRINTF(cli_buf);
+ }
+
+ if (!coex_sta->bt_disabled) {
+ if (coex_sta->bt_coex_supported_feature == 0)
+ btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_FEATURE,
+ &coex_sta->bt_coex_supported_feature);
+
+ if ((coex_sta->bt_coex_supported_version == 0) ||
+ (coex_sta->bt_coex_supported_version == 0xffff))
+ btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_VERSION,
+ &coex_sta->bt_coex_supported_version);
+
+ if (coex_sta->bt_reg_vendor_ac == 0xffff)
+ coex_sta->bt_reg_vendor_ac = (u16)(
+ btcoexist->btc_get_bt_reg(btcoexist, 3,
+ 0xac) & 0xffff);
+
+ if (coex_sta->bt_reg_vendor_ae == 0xffff)
+ coex_sta->bt_reg_vendor_ae = (u16)(
+ btcoexist->btc_get_bt_reg(btcoexist, 3,
+ 0xae) & 0xffff);
+
+ btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER,
+ &bt_patch_ver);
+ btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver;
+
+ if (coex_sta->num_of_profile > 0) {
+ cnt++;
+
+ if (cnt >= 3) {
+ btcoexist->btc_get_bt_afh_map_from_bt(btcoexist, 0,
+ &coex_sta->bt_afh_map[0]);
+ cnt = 0;
+ }
+ }
+ }
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %d/ %d/ %s / %d",
+ "Ant PG Num/ Mech/ Pos/ RFE",
+ board_info->pg_ant_num, board_info->btdm_ant_num,
+ (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT
+ ? "Main" : "Aux"),
+ rfe_type->rfe_module_type);
+ CL_PRINTF(cli_buf);
+
+ bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver;
+ btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
+ phyver = btcoexist->btc_get_bt_phydm_version(btcoexist);
+
+ bt_coex_ver = ((coex_sta->bt_coex_supported_version & 0xff00) >> 8);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)",
+ "CoexVer WL/ BT_Desired/ BT_Report",
+ glcoex_ver_date_8822b_1ant, glcoex_ver_8822b_1ant,
+ glcoex_ver_btdesired_8822b_1ant,
+ bt_coex_ver,
+ (bt_coex_ver == 0xff ? "Unknown" :
+ (coex_sta->bt_disabled ? "BT-disable" :
+ (bt_coex_ver >= glcoex_ver_btdesired_8822b_1ant ?
+ "Match" : "Mis-Match"))));
+ CL_PRINTF(cli_buf);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c",
+ "W_FW/ B_FW/ Phy/ Kt",
+ fw_ver, bt_patch_ver, phyver,
+ coex_sta->cut_version + 65);
+ CL_PRINTF(cli_buf);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x (RF-Ch = %d)",
+ "AFH Map to BT",
+ coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
+ coex_dm->wifi_chnl_info[2], coex_sta->wl_center_channel);
+ CL_PRINTF(cli_buf);
+
+ /* wifi status */
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+ "============[Wifi Status]============");
+ CL_PRINTF(cli_buf);
+ btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+ "============[BT Status]============");
+ CL_PRINTF(cli_buf);
+
+ pop_report_in_10s++;
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %s/ %ddBm/ %d/ %d",
+ "BT status/ rssi/ retryCnt/ popCnt",
+ ((coex_sta->bt_disabled) ? ("disabled") : ((
+ coex_sta->c2h_bt_inquiry_page) ? ("inquiry-page")
+ : ((BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+ coex_dm->bt_status) ? "non-connecte-idle" :
+ ((coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE)
+ ? "connected-idle" : "busy")))),
+ coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt,
+ coex_sta->pop_event_cnt);
+ CL_PRINTF(cli_buf);
+
+ if (pop_report_in_10s >= 5) {
+ coex_sta->pop_event_cnt = 0;
+ pop_report_in_10s = 0;
+ }
+
+ if (coex_sta->num_of_profile != 0)
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %s%s%s%s%s%s (multilink = %d)",
+ "Profiles",
+ ((bt_link_info->a2dp_exist) ?
+ ((coex_sta->is_bt_a2dp_sink) ? "A2DP sink," :
+ "A2DP,") : ""),
+ ((bt_link_info->sco_exist) ? "HFP," : ""),
+ ((bt_link_info->hid_exist) ?
+ ((coex_sta->is_hid_rcu) ? "HID(RCU)" :
+ ((coex_sta->hid_busy_num >= 2) ? "HID(4/18)," :
+ "HID(2/18),")) : ""),
+ ((bt_link_info->pan_exist) ?
+ ((coex_sta->is_bt_opp_exist) ? "OPP," : "PAN,") : ""),
+ ((coex_sta->voice_over_HOGP) ? "Voice," : ""),
+ ((coex_sta->msft_mr_exist) ? "MR" : ""),
+ coex_sta->is_bt_multi_link);
+ else {
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %s", "Profiles",
+ (coex_sta->msft_mr_exist) ? "MR" : "None");
+ }
+
+ CL_PRINTF(cli_buf);
+
+ if (bt_link_info->a2dp_exist) {
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s",
+ "A2DP Rate/Bitpool/Auto_Slot",
+ ((coex_sta->is_A2DP_3M) ? "3M" : "No_3M"),
+ coex_sta->a2dp_bit_pool,
+ ((coex_sta->is_autoslot) ? "On" : "Off")
+ );
+ CL_PRINTF(cli_buf);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ %d/ %d",
+ "V_ID/D_name/FBSlot_Legacy/FBSlot_Le",
+ coex_sta->bt_a2dp_vendor_id,
+ coex_sta->bt_a2dp_device_name,
+ coex_sta->legacy_forbidden_slot,
+ coex_sta->le_forbidden_slot
+ );
+ CL_PRINTF(cli_buf);
+ }
+
+ if (bt_link_info->hid_exist) {
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
+ "HID PairNum",
+ coex_sta->hid_pair_cnt
+ );
+ CL_PRINTF(cli_buf);
+ }
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s/ 0x%x",
+ "Role/RoleSwCnt/IgnWlact/Feature",
+ ((bt_link_info->slave_role) ? "Slave" : "Master"),
+ coex_sta->cnt_RoleSwitch,
+ ((coex_dm->cur_ignore_wlan_act) ? "Yes" : "No"),
+ coex_sta->bt_coex_supported_feature);
+ CL_PRINTF(cli_buf);
+
+ if (coex_sta->is_ble_scan_en) {
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+ "BLEScan Type/TV/Init/Ble",
+ coex_sta->bt_ble_scan_type,
+ (coex_sta->bt_ble_scan_type & 0x1 ?
+ coex_sta->bt_ble_scan_para[0] : 0x0),
+ (coex_sta->bt_ble_scan_type & 0x2 ?
+ coex_sta->bt_ble_scan_para[1] : 0x0),
+ (coex_sta->bt_ble_scan_type & 0x4 ?
+ coex_sta->bt_ble_scan_para[2] : 0x0));
+ CL_PRINTF(cli_buf);
+ }
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d",
+ "ReInit/ReLink/IgnWlact/Page/NameReq",
+ coex_sta->cnt_ReInit,
+ coex_sta->cnt_setupLink,
+ coex_sta->cnt_IgnWlanAct,
+ coex_sta->cnt_Page,
+ coex_sta->cnt_RemoteNameReq
+ );
+ CL_PRINTF(cli_buf);
+
+ halbtc8822b1ant_read_score_board(btcoexist, &u16tmp[0]);
+
+ if ((coex_sta->bt_reg_vendor_ae == 0xffff) ||
+ (coex_sta->bt_reg_vendor_ac == 0xffff))
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = x/ x/ 0x%04x",
+ "0xae[4]/0xac[1:0]/Scoreboard(B->W)", u16tmp[0]);
+ else
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = 0x%x/ 0x%x/ 0x%04x",
+ "0xae[4]/0xac[1:0]/Scoreboard(B->W)",
+ ((coex_sta->bt_reg_vendor_ae & BIT(4)) >> 4),
+ coex_sta->bt_reg_vendor_ac & 0x3, u16tmp[0]);
+ CL_PRINTF(cli_buf);
+
+ if (coex_sta->num_of_profile > 0) {
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %02x%02x%02x%02x %02x%02x%02x%02x %02x%02x",
+ "AFH MAP",
+ coex_sta->bt_afh_map[0],
+ coex_sta->bt_afh_map[1],
+ coex_sta->bt_afh_map[2],
+ coex_sta->bt_afh_map[3],
+ coex_sta->bt_afh_map[4],
+ coex_sta->bt_afh_map[5],
+ coex_sta->bt_afh_map[6],
+ coex_sta->bt_afh_map[7],
+ coex_sta->bt_afh_map[8],
+ coex_sta->bt_afh_map[9]
+ );
+ CL_PRINTF(cli_buf);
+ }
+
+ for (i = 0; i < BT_INFO_SRC_8822B_1ANT_MAX; i++) {
+ if (coex_sta->bt_info_c2h_cnt[i]) {
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x (%d)",
+ glbt_info_src_8822b_1ant[i],
+ coex_sta->bt_info_c2h[i][0],
+ coex_sta->bt_info_c2h[i][1],
+ coex_sta->bt_info_c2h[i][2],
+ coex_sta->bt_info_c2h[i][3],
+ coex_sta->bt_info_c2h[i][4],
+ coex_sta->bt_info_c2h[i][5],
+ coex_sta->bt_info_c2h[i][6],
+ coex_sta->bt_info_c2h_cnt[i]);
+ CL_PRINTF(cli_buf);
+ }
+ }
+
+
+ if (btcoexist->manual_control)
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+ "============[mechanisms] (before Manual)============");
+ else
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+ "============[Mechanisms]============");
+
+ CL_PRINTF(cli_buf);
+
+ ps_tdma_case = coex_dm->cur_ps_tdma;
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %02x %02x %02x %02x %02x (case-%d, %s)",
+ "TDMA",
+ coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],
+ coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],
+ coex_dm->ps_tdma_para[4], ps_tdma_case,
+ (coex_dm->cur_ps_tdma_on ? "TDMA On" : "TDMA Off"));
+
+ CL_PRINTF(cli_buf);
+
+ u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
+ u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
+ u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %d/ 0x%x/ 0x%x/ 0x%x",
+ "Table/0x6c0/0x6c4/0x6c8",
+ coex_sta->coex_table_type, u32tmp[0], u32tmp[1], u32tmp[2]);
+ CL_PRINTF(cli_buf);
+
+ u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
+ u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc);
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = 0x%x/ 0x%x/ 0x%04x",
+ "0x778/0x6cc/Scoreboard(W->B)",
+ u8tmp[0], u32tmp[0], coex_sta->score_board_WB);
+ CL_PRINTF(cli_buf);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d/ %d",
+ "AntDiv/BtCtrlLPS/LPRA/PsFail/g_busy",
+ ((board_info->ant_div_cfg) ? "On" : "Off"),
+ ((coex_sta->force_lps_ctrl) ? "On" : "Off"),
+ ((coex_dm->cur_low_penalty_ra) ? "On" : "Off"),
+ coex_sta->cnt_set_ps_state_fail,
+ coex_sta->gl_wifi_busy);
+ CL_PRINTF(cli_buf);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d",
+ "Null All/Retry/Ack/BT_Empty/BT_Late",
+ coex_sta->wl_fw_dbg_info[1],
+ coex_sta->wl_fw_dbg_info[2],
+ coex_sta->wl_fw_dbg_info[3],
+ coex_sta->wl_fw_dbg_info[4],
+ coex_sta->wl_fw_dbg_info[5]);
+ CL_PRINTF(cli_buf);
+
+ u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
+ lte_coex_on = ((u32tmp[0] & BIT(7)) >> 7) ? TRUE : FALSE;
+
+ if (lte_coex_on) {
+
+ u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
+ 0xa0);
+ u32tmp[1] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
+ 0xa4);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+ "LTE Coex Table W_L/B_L",
+ u32tmp[0] & 0xffff, u32tmp[1] & 0xffff);
+ CL_PRINTF(cli_buf);
+
+ u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
+ 0xa8);
+ u32tmp[1] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
+ 0xac);
+ u32tmp[2] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
+ 0xb0);
+ u32tmp[3] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist,
+ 0xb4);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+ "LTE Break Table W_L/B_L/L_W/L_B",
+ u32tmp[0] & 0xffff, u32tmp[1] & 0xffff,
+ u32tmp[2] & 0xffff, u32tmp[3] & 0xffff);
+ CL_PRINTF(cli_buf);
+ }
+
+ /* Hw setting */
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+ "============[Hw setting]============");
+ CL_PRINTF(cli_buf);
+
+ u32tmp[0] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
+ u32tmp[1] = halbtc8822b1ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
+ u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s",
+ "LTE Coex/Path Owner",
+ ((lte_coex_on) ? "On" : "Off"),
+ ((u8tmp[0] & BIT(2)) ? "WL" : "BT"));
+ CL_PRINTF(cli_buf);
+
+ if (lte_coex_on) {
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %d/ %d/ %d/ %d",
+ "LTE 3Wire/OPMode/UART/UARTMode",
+ (int)((u32tmp[0] & BIT(6)) >> 6),
+ (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4),
+ (int)((u32tmp[0] & BIT(3)) >> 3),
+ (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0))));
+ CL_PRINTF(cli_buf);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+ "LTE_Busy/UART_Busy",
+ (int)((u32tmp[1] & BIT(1)) >> 1),
+ (int)(u32tmp[1] & BIT(0)));
+ CL_PRINTF(cli_buf);
+ }
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %s (BB:%s)/ %s (BB:%s)/ %s (gnt_err = %d)",
+ "GNT_WL_Ctrl/GNT_BT_Ctrl/Dbg",
+ ((u32tmp[0] & BIT(12)) ? "SW" : "HW"),
+ ((u32tmp[0] & BIT(8)) ? "SW" : "HW"),
+ ((u32tmp[0] & BIT(14)) ? "SW" : "HW"),
+ ((u32tmp[0] & BIT(10)) ? "SW" : "HW"),
+ ((u8tmp[0] & BIT(3)) ? "On" : "Off"),
+ coex_sta->gnt_error_cnt);
+ CL_PRINTF(cli_buf);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+ "GNT_WL/GNT_BT",
+ (int)((u32tmp[1] & BIT(2)) >> 2),
+ (int)((u32tmp[1] & BIT(3)) >> 3));
+ CL_PRINTF(cli_buf);
+
+
+ u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xcb0);
+ u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xcb4);
+ u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xcba);
+ u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xcbd);
+ u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0xc58);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = 0x%04x/ 0x%04x/ 0x%02x/ 0x%02x/ 0x%02x %s",
+ "0xcb0/0xcb4/0xcb8[23:16]/0xcbd/0xc58",
+ u32tmp[0], u32tmp[1], u8tmp[0], u8tmp[1], u8tmp[2],
+ ((u8tmp[1] & 0x1) == 0x1 ? "(BT_WL5G)" : "(WL2G)"));
+ CL_PRINTF(cli_buf);
+
+ u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c);
+ u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0x64);
+ u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6);
+ u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+ "4c[24:23]/64[0]/4c6[4]/40[5]",
+ (u32tmp[0] & (BIT(24) | BIT(23))) >> 23, u8tmp[2] & 0x1,
+ (int)((u8tmp[0] & BIT(4)) >> 4),
+ (int)((u8tmp[1] & BIT(5)) >> 5));
+ CL_PRINTF(cli_buf);
+
+ u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
+ u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
+ u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x953);
+ u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0xc50);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = 0x%x/ 0x%x/ %s/ 0x%x",
+ "0x550/0x522/4-RxAGC/0xc50",
+ u32tmp[0], u8tmp[0], (u8tmp[1] & 0x2) ? "On" : "Off", u8tmp[2]);
+ CL_PRINTF(cli_buf);
+
+ fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+ PHYDM_INFO_FA_OFDM);
+ fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+ PHYDM_INFO_FA_CCK);
+ cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+ PHYDM_INFO_CCA_OFDM);
+ cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+ PHYDM_INFO_CCA_CCK);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+ "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA",
+ cca_cck, fa_cck, cca_ofdm, fa_ofdm);
+ CL_PRINTF(cli_buf);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d (Rx_rate Data/RTS= %d/%d)",
+ "CRC_OK CCK/11g/11n/11ac",
+ coex_sta->crc_ok_cck, coex_sta->crc_ok_11g,
+ coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht,
+ coex_sta->wl_rx_rate, coex_sta->wl_rts_rx_rate);
+ CL_PRINTF(cli_buf);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+ "CRC_Err CCK/11g/11n/11ac",
+ coex_sta->crc_err_cck, coex_sta->crc_err_11g,
+ coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht);
+ CL_PRINTF(cli_buf);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %s/ %d",
+ "HiPr/ Locking/ warn/ Locked/ Noisy",
+ (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"),
+ (coex_sta->cck_lock ? "Yes" : "No"),
+ (coex_sta->cck_lock_warn ? "Yes" : "No"),
+ (coex_sta->cck_lock_ever ? "Yes" : "No"),
+ coex_sta->wl_noisy_level);
+ CL_PRINTF(cli_buf);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+ "0x770(Hi-pri rx/tx)",
+ coex_sta->high_priority_rx, coex_sta->high_priority_tx);
+ CL_PRINTF(cli_buf);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s",
+ "0x774(Lo-pri rx/tx)",
+ coex_sta->low_priority_rx, coex_sta->low_priority_tx,
+ (bt_link_info->slave_role ? "(Slave!!)" : (
+ coex_sta->is_tdma_btautoslot_hang ? "(auto-slot hang!!)" : "")));
+ CL_PRINTF(cli_buf);
+
+ btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
+}
+
+void ex_halbtc8822b1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type)
+{
+
+ if (btcoexist->manual_control || btcoexist->stop_coex_dm)
+ return;
+
+
+ if (BTC_IPS_ENTER == type) {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], IPS ENTER notify\n");
+ BTC_TRACE(trace_buf);
+ coex_sta->under_ips = TRUE;
+
+ /* Write WL "Active" in Score-board for LPS off */
+ halbtc8822b1ant_post_state_to_bt(btcoexist,
+ BT_8822B_1ANT_SCOREBOARD_ACTIVE |
+ BT_8822B_1ANT_SCOREBOARD_ONOFF |
+ BT_8822B_1ANT_SCOREBOARD_SCAN |
+ BT_8822B_1ANT_SCOREBOARD_UNDERTEST |
+ BT_8822B_1ANT_SCOREBOARD_RXGAIN,
+ FALSE);
+
+ halbtc8822b1ant_set_ant_path(btcoexist,
+ BTC_ANT_PATH_AUTO,
+ FORCE_EXEC,
+ BT_8822B_1ANT_PHASE_WLAN_OFF);
+
+ halbtc8822b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
+ } else if (BTC_IPS_LEAVE == type) {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], IPS LEAVE notify\n");
+ BTC_TRACE(trace_buf);
+ halbtc8822b1ant_post_state_to_bt(btcoexist,
+ BT_8822B_1ANT_SCOREBOARD_ACTIVE |
+ BT_8822B_1ANT_SCOREBOARD_ONOFF,
+ TRUE);
+
+ /*leave IPS : run ini hw config (exclude wifi only)*/
+ halbtc8822b1ant_init_hw_config(btcoexist, FALSE, FALSE);
+ /*sw all off*/
+ halbtc8822b1ant_init_coex_dm(btcoexist);
+
+ coex_sta->under_ips = FALSE;
+ }
+}
+
+void ex_halbtc8822b1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type)
+{
+ static boolean pre_force_lps_on = FALSE;
+
+ if (btcoexist->manual_control || btcoexist->stop_coex_dm)
+ return;
+
+ if (type == BTC_LPS_ENABLE) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], LPS ENABLE notify\n");
+ BTC_TRACE(trace_buf);
+ coex_sta->under_lps = TRUE;
+
+ if (coex_sta->force_lps_ctrl == TRUE) { /* LPS No-32K */
+ /* Write WL "Active" in Score-board for PS-TDMA */
+ pre_force_lps_on = TRUE;
+ halbtc8822b1ant_post_state_to_bt(btcoexist,
+ BT_8822B_1ANT_SCOREBOARD_ACTIVE, TRUE);
+ } else { /* LPS-32K, need check if this h2c 0x71 can work?? (2015/08/28) */
+ /* Write WL "Non-Active" in Score-board for Native-PS */
+ pre_force_lps_on = FALSE;
+ halbtc8822b1ant_post_state_to_bt(btcoexist,
+ BT_8822B_1ANT_SCOREBOARD_ACTIVE, FALSE);
+
+ halbtc8822b1ant_action_wifi_native_lps(btcoexist);
+ }
+ } else if (BTC_LPS_DISABLE == type) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], LPS DISABLE notify\n");
+ BTC_TRACE(trace_buf);
+ coex_sta->under_lps = FALSE;
+
+ /* Write WL "Active" in Score-board for LPS off */
+ halbtc8822b1ant_post_state_to_bt(btcoexist,
+ BT_8822B_1ANT_SCOREBOARD_ACTIVE, TRUE);
+
+ if ((!pre_force_lps_on) && (!coex_sta->force_lps_ctrl))
+ halbtc8822b1ant_query_bt_info(btcoexist);
+ }
+}
+
+void ex_halbtc8822b1ant_scan_notify(IN struct btc_coexist *btcoexist,
+ IN u8 type)
+{
+ boolean wifi_connected = FALSE;
+ boolean wifi_under_5g = FALSE;
+
+ if (btcoexist->manual_control ||
+ btcoexist->stop_coex_dm)
+ return;
+
+ coex_sta->freeze_coexrun_by_btinfo = FALSE;
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected);
+
+ if (wifi_connected)
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ********** WL connected before SCAN\n");
+ else
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ********** WL is not connected before SCAN\n");
+
+ BTC_TRACE(trace_buf);
+
+ if ((type == BTC_SCAN_START) || (type == BTC_SCAN_START_2G)) {
+
+ halbtc8822b1ant_post_state_to_bt(btcoexist,
+ BT_8822B_1ANT_SCOREBOARD_ACTIVE |
+ BT_8822B_1ANT_SCOREBOARD_SCAN |
+ BT_8822B_1ANT_SCOREBOARD_ONOFF,
+ TRUE);
+
+ halbtc8822b1ant_query_bt_info(btcoexist);
+ }
+
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+
+ if ((type == BTC_SCAN_START) && (wifi_under_5g)) {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], SCAN START notify (5G)\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+ FORCE_EXEC,
+ BT_8822B_1ANT_PHASE_5G_RUNTIME);
+ halbtc8822b1ant_run_coexist_mechanism(btcoexist);
+ } else if ((type == BTC_SCAN_START_2G) || (type == BTC_SCAN_START)) {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], SCAN START notify (2G)\n");
+ BTC_TRACE(trace_buf);
+
+ if (!wifi_connected)
+ coex_sta->wifi_is_high_pri_task = TRUE;
+
+ /* Force antenna setup for no scan result issue */
+ halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+ FORCE_EXEC,
+ BT_8822B_1ANT_PHASE_2G_RUNTIME);
+
+ halbtc8822b1ant_run_coexist_mechanism(btcoexist);
+ } else {
+
+ btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
+ &coex_sta->scan_ap_num);
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], SCAN FINISH notify (Scan-AP = %d)\n",
+ coex_sta->scan_ap_num);
+ BTC_TRACE(trace_buf);
+
+ coex_sta->wifi_is_high_pri_task = FALSE;
+
+ halbtc8822b1ant_run_coexist_mechanism(btcoexist);
+ }
+
+}
+
+
+
+
+void ex_halbtc8822b1ant_scan_notify_without_bt(IN struct btc_coexist *btcoexist,
+ IN u8 type)
+{
+ boolean wifi_under_5g = FALSE;
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+
+ if (BTC_SCAN_START == type) {
+
+ if (wifi_under_5g)
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x3, 1);
+ else /* under 2.4G */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x3, 2);
+ } else if (type == BTC_SCAN_START_2G)
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x3, 2);
+}
+
+void ex_halbtc8822b1ant_switchband_notify(IN struct btc_coexist *btcoexist,
+ IN u8 type)
+{
+
+ if (btcoexist->manual_control ||
+ btcoexist->stop_coex_dm)
+ return;
+
+ coex_sta->switch_band_notify_to = type;
+
+ if (type == BTC_SWITCH_TO_5G) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], switchband_notify --- BTC_SWITCH_TO_5G\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b1ant_run_coexist_mechanism(btcoexist);
+ } else if (type == BTC_SWITCH_TO_24G_NOFORSCAN) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], switchband_notify --- BTC_SWITCH_TO_24G_NOFORSCAN\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b1ant_run_coexist_mechanism(btcoexist);
+ } else {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], switchband_notify --- BTC_SWITCH_TO_2G\n");
+ BTC_TRACE(trace_buf);
+
+ ex_halbtc8822b1ant_scan_notify(btcoexist, BTC_SCAN_START_2G);
+ }
+
+ coex_sta->switch_band_notify_to = BTC_NOT_SWITCH;
+
+}
+
+
+void ex_halbtc8822b1ant_switchband_notify_without_bt(IN struct btc_coexist
+ *btcoexist,
+ IN u8 type)
+{
+
+ if (type == BTC_SWITCH_TO_5G)
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x3, 1);
+ else if (type == BTC_SWITCH_TO_24G_NOFORSCAN)
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x3, 2);
+ else
+ ex_halbtc8822b1ant_scan_notify_without_bt(btcoexist, BTC_SCAN_START_2G);
+}
+
+void ex_halbtc8822b1ant_connect_notify(IN struct btc_coexist *btcoexist,
+ IN u8 type)
+{
+
+ if (btcoexist->manual_control ||
+ btcoexist->stop_coex_dm)
+ return;
+
+ halbtc8822b1ant_post_state_to_bt(btcoexist,
+ BT_8822B_1ANT_SCOREBOARD_ACTIVE |
+ BT_8822B_1ANT_SCOREBOARD_SCAN |
+ BT_8822B_1ANT_SCOREBOARD_ONOFF,
+ TRUE);
+
+ if ((type == BTC_ASSOCIATE_5G_START) ||
+ (type == BTC_ASSOCIATE_5G_FINISH)) {
+
+ if (type == BTC_ASSOCIATE_5G_START)
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], connect_notify --- 5G start\n");
+ else
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], connect_notify --- 5G finish\n");
+
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+ FORCE_EXEC,
+ BT_8822B_1ANT_PHASE_5G_RUNTIME);
+
+ halbtc8822b1ant_run_coexist_mechanism(btcoexist);
+ } else if (type == BTC_ASSOCIATE_START) {
+
+ coex_sta->wifi_is_high_pri_task = TRUE;
+ coex_dm->arp_cnt = 0;
+ coex_sta->connect_ap_period_cnt = 2;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], CONNECT START notify (2G)\n");
+ BTC_TRACE(trace_buf);
+
+ /* Force antenna setup for no scan result issue */
+ halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+ FORCE_EXEC,
+ BT_8822B_1ANT_PHASE_2G_RUNTIME);
+
+ halbtc8822b1ant_run_coexist_mechanism(btcoexist);
+
+ /* To keep TDMA case during connect process,
+ to avoid changed by Btinfo and runcoexmechanism */
+ coex_sta->freeze_coexrun_by_btinfo = TRUE;
+ } else {
+
+ coex_sta->wifi_is_high_pri_task = FALSE;
+ coex_sta->freeze_coexrun_by_btinfo = FALSE;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], CONNECT FINISH notify (2G)\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b1ant_run_coexist_mechanism(btcoexist);
+ }
+
+}
+
+
+void ex_halbtc8822b1ant_media_status_notify(IN struct btc_coexist *btcoexist,
+ IN u8 type)
+{
+ boolean wifi_under_b_mode = FALSE;
+ boolean wifi_under_5g = FALSE;
+
+ if (btcoexist->manual_control ||
+ btcoexist->stop_coex_dm)
+ return;
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+
+ if (type == BTC_MEDIA_CONNECT) {
+
+ halbtc8822b1ant_post_state_to_bt(btcoexist,
+ BT_8822B_1ANT_SCOREBOARD_ACTIVE, TRUE);
+
+ if (wifi_under_5g) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], media_status_notify --- 5G\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+ FORCE_EXEC,
+ BT_8822B_1ANT_PHASE_5G_RUNTIME);
+
+ halbtc8822b1ant_run_coexist_mechanism(btcoexist);
+ } else {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], media_status_notify --- 2G\n");
+ BTC_TRACE(trace_buf);
+
+ /* Force antenna setup for no scan result issue */
+ halbtc8822b1ant_set_ant_path(btcoexist,
+ BTC_ANT_PATH_AUTO,
+ FORCE_EXEC,
+ BT_8822B_1ANT_PHASE_2G_RUNTIME);
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
+ &wifi_under_b_mode);
+
+ /* Set CCK Tx/Rx high Pri except 11b mode */
+ if (wifi_under_b_mode) {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], media status notity --- under b mode\n");
+ BTC_TRACE(trace_buf);
+ btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x00); /* CCK Tx */
+ btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x00); /* CCK Rx */
+ } else {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], media status notity --- under b mode\n");
+ BTC_TRACE(trace_buf);
+ btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x00); /* CCK Tx */
+ btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x10); /* CCK Rx */
+ }
+
+ halbtc8822b1ant_run_coexist_mechanism(btcoexist);
+ }
+ } else {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], media disconnect notify\n");
+ BTC_TRACE(trace_buf);
+ coex_dm->arp_cnt = 0;
+
+ halbtc8822b1ant_post_state_to_bt(btcoexist,
+ BT_8822B_1ANT_SCOREBOARD_ACTIVE, FALSE);
+
+ btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */
+ btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */
+
+ coex_sta->cck_lock_ever = FALSE;
+ coex_sta->cck_lock_warn = FALSE;
+ coex_sta->cck_lock = FALSE;
+
+ halbtc8822b1ant_run_coexist_mechanism(btcoexist);
+ }
+
+ halbtc8822b1ant_update_wifi_channel_info(btcoexist, type);
+
+}
+
+void ex_halbtc8822b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
+ IN u8 type)
+{
+ boolean under_4way = FALSE, wifi_under_5g = FALSE;
+
+ if (btcoexist->manual_control ||
+ btcoexist->stop_coex_dm)
+ return;
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+ if (wifi_under_5g) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], 5g special packet notify\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b1ant_run_coexist_mechanism(btcoexist);
+ return;
+ }
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
+ &under_4way);
+
+ if (under_4way) {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], specific Packet ---- under_4way!!\n");
+ BTC_TRACE(trace_buf);
+
+ coex_sta->wifi_is_high_pri_task = TRUE;
+ coex_sta->specific_pkt_period_cnt = 2;
+ } else if (BTC_PACKET_ARP == type) {
+
+ coex_dm->arp_cnt++;
+
+ if (coex_sta->wifi_is_high_pri_task) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], specific Packet ARP notify -cnt = %d\n",
+ coex_dm->arp_cnt);
+ BTC_TRACE(trace_buf);
+ }
+
+ } else {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n",
+ type);
+ BTC_TRACE(trace_buf);
+
+ coex_sta->wifi_is_high_pri_task = TRUE;
+ coex_sta->specific_pkt_period_cnt = 2;
+ }
+
+ if (coex_sta->wifi_is_high_pri_task) {
+ halbtc8822b1ant_post_state_to_bt(btcoexist,
+ BT_8822B_1ANT_SCOREBOARD_SCAN, TRUE);
+ halbtc8822b1ant_run_coexist_mechanism(btcoexist);
+ }
+
+}
+
+
+void ex_halbtc8822b1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
+ IN u8 *tmp_buf, IN u8 length)
+{
+ u8 i, rsp_source = 0;
+ boolean wifi_connected = FALSE;
+ boolean wifi_scan = FALSE, wifi_link = FALSE, wifi_roam = FALSE,
+ wifi_busy = FALSE;
+ static boolean is_scoreboard_scan = FALSE;
+
+ rsp_source = tmp_buf[0] & 0xf;
+ if (rsp_source >= BT_INFO_SRC_8822B_1ANT_MAX)
+ rsp_source = BT_INFO_SRC_8822B_1ANT_WIFI_FW;
+ coex_sta->bt_info_c2h_cnt[rsp_source]++;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Bt_info[%d], len=%d, data=[", rsp_source,
+ length);
+ BTC_TRACE(trace_buf);
+
+ if ((rsp_source == BT_INFO_SRC_8822B_1ANT_BT_RSP) ||
+ (rsp_source == BT_INFO_SRC_8822B_1ANT_BT_ACTIVE_SEND)) {
+ if (coex_sta->bt_disabled) {
+ coex_sta->bt_disabled = FALSE;
+ coex_sta->is_bt_reenable = TRUE;
+ coex_sta->cnt_bt_reenable = 15;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT enable detected by bt_info\n");
+ BTC_TRACE(trace_buf);
+ }
+ }
+
+ for (i = 0; i < length; i++) {
+ coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
+
+ if (i == length - 1) {
+ /* last one */
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n",
+ tmp_buf[i]);
+ BTC_TRACE(trace_buf);
+ } else {
+ /* normal */
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ",
+ tmp_buf[i]);
+ BTC_TRACE(trace_buf);
+ }
+ }
+
+ coex_sta->bt_info = coex_sta->bt_info_c2h[rsp_source][1];
+ coex_sta->bt_info_ext = coex_sta->bt_info_c2h[rsp_source][4];
+ coex_sta->bt_info_ext2 = coex_sta->bt_info_c2h[rsp_source][5];
+
+ if (BT_INFO_SRC_8822B_1ANT_WIFI_FW != rsp_source) {
+
+ /* if 0xff, it means BT is under WHCK test */
+ coex_sta->bt_whck_test = ((coex_sta->bt_info == 0xff) ? TRUE :
+ FALSE);
+
+ coex_sta->bt_create_connection = ((
+ coex_sta->bt_info_c2h[rsp_source][2] & 0x80) ? TRUE :
+ FALSE);
+
+ /* unit: %, value-100 to translate to unit: dBm */
+ coex_sta->bt_rssi = coex_sta->bt_info_c2h[rsp_source][3] * 2 +
+ 10;
+
+ coex_sta->c2h_bt_remote_name_req = ((
+ coex_sta->bt_info_c2h[rsp_source][2] & 0x20) ? TRUE :
+ FALSE);
+
+ coex_sta->is_A2DP_3M = ((coex_sta->bt_info_c2h[rsp_source][2] &
+ 0x10) ? TRUE : FALSE);
+
+ coex_sta->acl_busy = ((coex_sta->bt_info_c2h[rsp_source][1] &
+ 0x8) ? TRUE : FALSE);
+
+ coex_sta->voice_over_HOGP = ((coex_sta->bt_info_ext & 0x10) ?
+ TRUE : FALSE);
+
+ coex_sta->c2h_bt_inquiry_page = ((coex_sta->bt_info &
+ BT_INFO_8822B_1ANT_B_INQ_PAGE) ? TRUE : FALSE);
+
+ coex_sta->a2dp_bit_pool = (((
+ coex_sta->bt_info_c2h[rsp_source][1] & 0x49) == 0x49) ?
+ (coex_sta->bt_info_c2h[rsp_source][6] & 0x7f) : 0);
+
+ coex_sta->is_bt_a2dp_sink = (coex_sta->bt_info_c2h[rsp_source][6] & 0x80) ?
+ TRUE : FALSE;
+
+ coex_sta->bt_retry_cnt = coex_sta->bt_info_c2h[rsp_source][2] &
+ 0xf;
+
+ coex_sta->is_autoslot = coex_sta->bt_info_ext2 & 0x8;
+
+ coex_sta->forbidden_slot = coex_sta->bt_info_ext2 & 0x7;
+
+ coex_sta->hid_busy_num = (coex_sta->bt_info_ext2 & 0x30) >> 4;
+
+ coex_sta->hid_pair_cnt = (coex_sta->bt_info_ext2 & 0xc0) >> 6;
+
+ coex_sta->is_bt_opp_exist = (coex_sta->bt_info_ext2 & 0x1) ? TRUE : FALSE;
+
+ if (coex_sta->bt_retry_cnt >= 1)
+ coex_sta->pop_event_cnt++;
+
+ if (coex_sta->c2h_bt_remote_name_req)
+ coex_sta->cnt_RemoteNameReq++;
+
+ if (coex_sta->bt_info_ext & BIT(1))
+ coex_sta->cnt_ReInit++;
+
+ if (coex_sta->bt_info_ext & BIT(2)) {
+ coex_sta->cnt_setupLink++;
+ coex_sta->is_setupLink = TRUE;
+
+ if (coex_sta->is_bt_reenable)
+ coex_sta->bt_relink_downcount = 8;
+ else
+ coex_sta->bt_relink_downcount = 2;
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Re-Link start in BT info!!\n");
+ BTC_TRACE(trace_buf);
+ }
+
+ if (coex_sta->bt_info_ext & BIT(3))
+ coex_sta->cnt_IgnWlanAct++;
+
+ if (coex_sta->bt_info_ext & BIT(6))
+ coex_sta->cnt_RoleSwitch++;
+
+ if (coex_sta->bt_info_ext & BIT(7))
+ coex_sta->is_bt_multi_link = TRUE;
+ else
+ coex_sta->is_bt_multi_link = FALSE;
+
+ if (coex_sta->bt_info_ext & BIT(0))
+ coex_sta->is_hid_rcu = TRUE;
+ else
+ coex_sta->is_hid_rcu = FALSE;
+
+ if (coex_sta->bt_info_ext & BIT(5))
+ coex_sta->is_ble_scan_en = TRUE;
+ else
+ coex_sta->is_ble_scan_en = FALSE;
+
+ if (coex_sta->bt_create_connection) {
+ coex_sta->cnt_Page++;
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan);
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link);
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam);
+
+ if ((wifi_link) || (wifi_roam) || (wifi_scan) ||
+ (coex_sta->wifi_is_high_pri_task) || (wifi_busy)) {
+
+ is_scoreboard_scan = TRUE;
+ halbtc8822b1ant_post_state_to_bt(btcoexist,
+ BT_8822B_1ANT_SCOREBOARD_SCAN, TRUE);
+
+ } else
+ halbtc8822b1ant_post_state_to_bt(btcoexist,
+ BT_8822B_1ANT_SCOREBOARD_SCAN, FALSE);
+
+ } else {
+ if (is_scoreboard_scan) {
+ halbtc8822b1ant_post_state_to_bt(btcoexist,
+ BT_8822B_1ANT_SCOREBOARD_SCAN, FALSE);
+ is_scoreboard_scan = FALSE;
+ }
+ }
+
+ /* Here we need to resend some wifi info to BT */
+ /* because bt is reset and loss of the info. */
+
+ if ((!btcoexist->manual_control) &&
+ (!btcoexist->stop_coex_dm)) {
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+ &wifi_connected);
+
+ /* Re-Init */
+ if ((coex_sta->bt_info_ext & BIT(1))) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n");
+ BTC_TRACE(trace_buf);
+ if (wifi_connected)
+ halbtc8822b1ant_update_wifi_channel_info(
+ btcoexist, BTC_MEDIA_CONNECT);
+ else
+ halbtc8822b1ant_update_wifi_channel_info(
+ btcoexist,
+ BTC_MEDIA_DISCONNECT);
+ }
+
+ /* If Ignore_WLanAct && not SetUp_Link */
+ if ((coex_sta->bt_info_ext & BIT(3)) &&
+ (!(coex_sta->bt_info_ext & BIT(2)))) {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n");
+ BTC_TRACE(trace_buf);
+ halbtc8822b1ant_ignore_wlan_act(btcoexist,
+ FORCE_EXEC, FALSE);
+ }
+ }
+
+ }
+
+ halbtc8822b1ant_update_bt_link_info(btcoexist);
+
+ halbtc8822b1ant_run_coexist_mechanism(btcoexist);
+}
+
+
+void ex_halbtc8822b1ant_wl_fwdbginfo_notify(IN struct btc_coexist *btcoexist,
+ IN u8 *tmp_buf, IN u8 length)
+{
+ u8 i = 0;
+ static u8 tmp_buf_pre[10] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], WiFi Fw Dbg info = %d %d %d %d %d %d (len = %d)\n",
+ tmp_buf[0], tmp_buf[1],
+ tmp_buf[2], tmp_buf[3],
+ tmp_buf[4], tmp_buf[5], length);
+ BTC_TRACE(trace_buf);
+
+ if (tmp_buf[0] == 0x8) {
+ for (i = 1; i <= 5; i++) {
+ coex_sta->wl_fw_dbg_info[i] =
+ (tmp_buf[i] >= tmp_buf_pre[i]) ?
+ (tmp_buf[i] - tmp_buf_pre[i]) :
+ (255 - tmp_buf_pre[i] + tmp_buf[i]);
+
+ tmp_buf_pre[i] = tmp_buf[i];
+ }
+ }
+}
+
+
+void ex_halbtc8822b1ant_rx_rate_change_notify(IN struct btc_coexist *btcoexist,
+ IN BOOLEAN is_data_frame, IN u8 btc_rate_id)
+{
+ BOOLEAN wifi_connected = FALSE;
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+ &wifi_connected);
+
+ if (is_data_frame) {
+ coex_sta->wl_rx_rate = btc_rate_id;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], rx_rate_change_notify data rate id = %d, RTS_Rate = %d\n",
+ coex_sta->wl_rx_rate, coex_sta->wl_rts_rx_rate);
+ BTC_TRACE(trace_buf);
+ } else {
+ coex_sta->wl_rts_rx_rate = btc_rate_id;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], rts_rate_change_notify RTS rate id = %d, RTS_Rate = %d\n",
+ coex_sta->wl_rts_rx_rate, coex_sta->wl_rts_rx_rate);
+ BTC_TRACE(trace_buf);
+ }
+
+ if ((wifi_connected) &&
+ ((coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_ACL_BUSY) ||
+ (coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_ACL_SCO_BUSY) ||
+ (coex_dm->bt_status == BT_8822B_1ANT_BT_STATUS_SCO_BUSY))) {
+
+ if ((coex_sta->wl_rx_rate == BTC_CCK_5_5) ||
+ (coex_sta->wl_rx_rate == BTC_OFDM_6) ||
+ (coex_sta->wl_rx_rate == BTC_MCS_0)) {
+
+ coex_sta->cck_lock_warn = TRUE;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], cck lock warning...\n");
+ BTC_TRACE(trace_buf);
+ } else if ((coex_sta->wl_rx_rate == BTC_CCK_1) ||
+ (coex_sta->wl_rx_rate == BTC_CCK_2) ||
+ (coex_sta->wl_rts_rx_rate == BTC_CCK_1) ||
+ (coex_sta->wl_rts_rx_rate == BTC_CCK_2)) {
+
+ coex_sta->cck_lock = TRUE;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], cck locking...\n");
+ BTC_TRACE(trace_buf);
+ } else {
+ coex_sta->cck_lock_warn = FALSE;
+ coex_sta->cck_lock = FALSE;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], cck unlock...\n");
+ BTC_TRACE(trace_buf);
+ }
+ } else {
+ if ((coex_dm->bt_status ==
+ BT_8822B_1ANT_BT_STATUS_CONNECTED_IDLE) ||
+ (coex_dm->bt_status ==
+ BT_8822B_1ANT_BT_STATUS_NON_CONNECTED_IDLE)) {
+ coex_sta->cck_lock_warn = FALSE;
+ coex_sta->cck_lock = FALSE;
+ }
+ }
+
+}
+
+
+
+void ex_halbtc8822b1ant_rf_status_notify(IN struct btc_coexist *btcoexist,
+ IN u8 type)
+{
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n");
+ BTC_TRACE(trace_buf);
+
+ if (BTC_RF_ON == type) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], RF is turned ON!!\n");
+ BTC_TRACE(trace_buf);
+ btcoexist->stop_coex_dm = FALSE;
+ coex_sta->is_rf_state_off = FALSE;
+
+ } else if (BTC_RF_OFF == type) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], RF is turned OFF!!\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b1ant_post_state_to_bt(btcoexist,
+ BT_8822B_1ANT_SCOREBOARD_ACTIVE |
+ BT_8822B_1ANT_SCOREBOARD_ONOFF |
+ BT_8822B_1ANT_SCOREBOARD_SCAN |
+ BT_8822B_1ANT_SCOREBOARD_UNDERTEST,
+ FALSE);
+
+ halbtc8822b1ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 0);
+
+ halbtc8822b1ant_set_ant_path(btcoexist,
+ BTC_ANT_PATH_AUTO,
+ FORCE_EXEC,
+ BT_8822B_1ANT_PHASE_WLAN_OFF);
+ /* for test : s3 bt disppear , fail rate 1/600*/
+
+ halbtc8822b1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, TRUE);
+
+ btcoexist->stop_coex_dm = TRUE;
+ coex_sta->is_rf_state_off = TRUE;
+ }
+}
+
+void ex_halbtc8822b1ant_halt_notify(IN struct btc_coexist *btcoexist)
+{
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b1ant_post_state_to_bt(btcoexist,
+ BT_8822B_1ANT_SCOREBOARD_ACTIVE |
+ BT_8822B_1ANT_SCOREBOARD_ONOFF |
+ BT_8822B_1ANT_SCOREBOARD_SCAN |
+ BT_8822B_1ANT_SCOREBOARD_UNDERTEST |
+ BT_8822B_1ANT_SCOREBOARD_RXGAIN,
+ FALSE);
+
+ halbtc8822b1ant_set_ant_path(btcoexist,
+ BTC_ANT_PATH_AUTO,
+ FORCE_EXEC,
+ BT_8822B_1ANT_PHASE_WLAN_OFF);
+
+ halbtc8822b1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, TRUE);
+
+ ex_halbtc8822b1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
+
+ halbtc8822b1ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 0);
+
+ btcoexist->stop_coex_dm = TRUE;
+}
+
+
+void ex_halbtc8822b1ant_pnp_notify(IN struct btc_coexist *btcoexist,
+ IN u8 pnp_state)
+{
+ boolean wifi_under_5g = FALSE;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n");
+ BTC_TRACE(trace_buf);
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+
+ if ((pnp_state == BTC_WIFI_PNP_SLEEP) ||
+ (pnp_state == BTC_WIFI_PNP_SLEEP_KEEP_ANT)) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Pnp notify to SLEEP\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b1ant_post_state_to_bt(btcoexist,
+ BT_8822B_1ANT_SCOREBOARD_ACTIVE |
+ BT_8822B_1ANT_SCOREBOARD_ONOFF |
+ BT_8822B_1ANT_SCOREBOARD_SCAN |
+ BT_8822B_1ANT_SCOREBOARD_UNDERTEST |
+ BT_8822B_1ANT_SCOREBOARD_RXGAIN,
+ FALSE);
+
+ if (pnp_state == BTC_WIFI_PNP_SLEEP_KEEP_ANT) {
+
+ if (wifi_under_5g)
+ halbtc8822b1ant_set_ant_path(btcoexist,
+ BTC_ANT_PATH_AUTO, FORCE_EXEC,
+ BT_8822B_1ANT_PHASE_5G_RUNTIME);
+ else
+ halbtc8822b1ant_set_ant_path(btcoexist,
+ BTC_ANT_PATH_AUTO, FORCE_EXEC,
+ BT_8822B_1ANT_PHASE_2G_RUNTIME);
+ } else {
+
+ halbtc8822b1ant_set_ant_path(btcoexist,
+ BTC_ANT_PATH_AUTO,
+ FORCE_EXEC,
+ BT_8822B_1ANT_PHASE_WLAN_OFF);
+ }
+
+ btcoexist->stop_coex_dm = TRUE;
+ } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Pnp notify to WAKE UP\n");
+ BTC_TRACE(trace_buf);
+#if 0
+ halbtc8822b1ant_post_state_to_bt(btcoexist,
+ BT_8822B_1ANT_SCOREBOARD_ACTIVE |
+ BT_8822B_1ANT_SCOREBOARD_ONOFF,
+ TRUE);
+#endif
+ }
+}
+
+void ex_halbtc8822b1ant_coex_dm_reset(IN struct btc_coexist *btcoexist)
+{
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], *****************Coex DM Reset*****************\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b1ant_init_hw_config(btcoexist, FALSE, FALSE);
+ halbtc8822b1ant_init_coex_dm(btcoexist);
+}
+
+void ex_halbtc8822b1ant_periodical(IN struct btc_coexist *btcoexist)
+{
+
+ boolean wifi_busy = FALSE;
+ u16 bt_scoreboard_val = 0;
+ u32 bt_patch_ver;
+ boolean bt_relink_finish = FALSE;
+
+#if 0
+ boolean rf4ce_connected = FALSE;
+#endif
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ==========================Periodical===========================\n");
+ BTC_TRACE(trace_buf);
+
+#if (BT_AUTO_REPORT_ONLY_8822B_1ANT == 0)
+ halbtc8822b1ant_query_bt_info(btcoexist);
+#endif
+
+ halbtc8822b1ant_monitor_bt_ctr(btcoexist);
+ halbtc8822b1ant_monitor_wifi_ctr(btcoexist);
+
+ halbtc8822b1ant_monitor_bt_enable_disable(btcoexist);
+
+ if (coex_sta->bt_relink_downcount != 0) {
+ coex_sta->bt_relink_downcount--;
+
+ if (coex_sta->bt_relink_downcount == 0) {
+ coex_sta->is_setupLink = FALSE;
+ bt_relink_finish = TRUE;
+ }
+ }
+
+ /* for 4-way, DHCP, EAPOL packet */
+ if (coex_sta->specific_pkt_period_cnt > 0) {
+
+ coex_sta->specific_pkt_period_cnt--;
+
+ if ((coex_sta->specific_pkt_period_cnt == 0) &&
+ (coex_sta->wifi_is_high_pri_task))
+ coex_sta->wifi_is_high_pri_task = FALSE;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ***************** Hi-Pri Task = %s*****************\n",
+ (coex_sta->wifi_is_high_pri_task ? "Yes" :
+ "No"));
+ BTC_TRACE(trace_buf);
+ }
+
+ /*for A2DP glitch during connecting AP*/
+ if (coex_sta->connect_ap_period_cnt > 0)
+ coex_sta->connect_ap_period_cnt--;
+
+ if (coex_sta->cnt_bt_reenable > 0) {
+ coex_sta->cnt_bt_reenable--;
+ if (coex_sta->cnt_bt_reenable == 0) {
+ coex_sta->is_bt_reenable = false;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT renable 30s finish!!\n");
+ BTC_TRACE(trace_buf);
+ }
+ }
+
+ if (halbtc8822b1ant_is_wifibt_status_changed(btcoexist) || (bt_relink_finish)
+ || (coex_sta->is_set_ps_state_fail))
+ halbtc8822b1ant_run_coexist_mechanism(btcoexist);
+}
+
+void ex_halbtc8822b1ant_antenna_detection(IN struct btc_coexist *btcoexist,
+ IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
+{
+}
+
+void ex_halbtc8822b1ant_antenna_isolation(IN struct btc_coexist *btcoexist,
+ IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
+{
+
+
+}
+
+void ex_halbtc8822b1ant_psd_scan(IN struct btc_coexist *btcoexist,
+ IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
+{
+
+
+}
+
+void ex_halbtc8822b1ant_display_ant_detection(IN struct btc_coexist *btcoexist)
+{
+
+}
+
+void ex_halbtc8822b1ant_dbg_control(IN struct btc_coexist *btcoexist,
+ IN u8 op_code, IN u8 op_len, IN u8 *pdata)
+{}
+#endif /* #if(BTC_COEX_OFFLOAD == 1) */
+
+#endif
+
+#else
+
+void ex_halbtc8822b1ant_switch_band_without_bt(IN struct btc_coexist *btcoexist,
+ IN boolean wifi_only_5g)
+{
+ /* ant switch WL2G or WL5G*/
+ if (wifi_only_5g)
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x3, 1);
+ else
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x3, 2);
+
+}
+
+#endif /* #if (BT_SUPPORT == 1 && COEX_SUPPORT == 1) */
diff --git a/hal/btc/HalBtc8822b1Ant.h b/hal/btc/halbtc8822b1ant.h
similarity index 70%
rename from hal/btc/HalBtc8822b1Ant.h
rename to hal/btc/halbtc8822b1ant.h
index 4f091f1..2ec4f7c 100644
--- a/hal/btc/HalBtc8822b1Ant.h
+++ b/hal/btc/halbtc8822b1ant.h
@@ -1,3 +1,17 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
@@ -6,6 +20,7 @@
/* *******************************************
* The following is for 8822B 1ANT BT Co-exist definition
* ******************************************* */
+#define BT_8822B_1ANT_COEX_DBG 0
#define BT_AUTO_REPORT_ONLY_8822B_1ANT 1
#define BT_INFO_8822B_1ANT_B_FTP BIT(7)
@@ -22,7 +37,8 @@
#define BTC_RSSI_COEX_THRESH_TOL_8822B_1ANT 2
-#define BT_8822B_1ANT_WIFI_NOISY_THRESH 30 /* max: 255 */
+#define BT_8822B_1ANT_WIFI_NOISY_THRESH 150 /* max: 255 */
+#define BT_8822B_1ANT_DEFAULT_ISOLATION 15 /* unit: dB */
/* for Antenna detection */
#define BT_8822B_1ANT_ANTDET_PSDTHRES_BACKGROUND 50
@@ -34,7 +50,7 @@
#define BT_8822B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE 0
#define BT_8822B_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT 30000
-#define BT_8822B_1ANT_WIFI_NOISY_THRESH 30 /* max: 255 */
+
enum bt_8822b_1ant_signal_state {
@@ -114,9 +130,11 @@ enum bt_8822b_1ant_coex_algo {
BT_8822B_1ANT_COEX_ALGO_PANHS = 0x6,
BT_8822B_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
BT_8822B_1ANT_COEX_ALGO_PANEDR_HID = 0x8,
- BT_8822B_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
- BT_8822B_1ANT_COEX_ALGO_HID_A2DP = 0xa,
- BT_8822B_1ANT_COEX_ALGO_MAX = 0xb,
+ BT_8822B_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
+ BT_8822B_1ANT_COEX_ALGO_HID_A2DP = 0xa,
+ BT_8822B_1ANT_COEX_ALGO_NOPROFILEBUSY = 0xb,
+ BT_8822B_1ANT_COEX_ALGO_A2DPSINK = 0xc,
+ BT_8822B_1ANT_COEX_ALGO_MAX
};
enum bt_8822b_1ant_ext_ant_switch_type {
@@ -139,19 +157,36 @@ enum bt_8822b_1ant_ext_ant_switch_pos_type {
BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLG = 0x1,
BT_8822B_1ANT_EXT_ANT_SWITCH_TO_WLA = 0x2,
BT_8822B_1ANT_EXT_ANT_SWITCH_TO_NOCARE = 0x3,
+ BT_8822B_1ANT_EXT_ANT_SWITCH_TO_S0WLG_S1BT = 0x4,
BT_8822B_1ANT_EXT_ANT_SWITCH_TO_MAX
};
-enum bt_8822b_1ant_phase{
+enum bt_8822b_1ant_phase {
BT_8822B_1ANT_PHASE_COEX_INIT = 0x0,
- BT_8822B_1ANT_PHASE_WLANONLY_INIT = 0x1,
+ BT_8822B_1ANT_PHASE_WLANONLY_INIT = 0x1,
BT_8822B_1ANT_PHASE_WLAN_OFF = 0x2,
BT_8822B_1ANT_PHASE_2G_RUNTIME = 0x3,
BT_8822B_1ANT_PHASE_5G_RUNTIME = 0x4,
BT_8822B_1ANT_PHASE_BTMPMODE = 0x5,
+ BT_8822B_1ANT_PHASE_COEX_POWERON = 0x6,
+ BT_8822B_1ANT_PHASE_2G_FREERUN_ANT_WL = 0x7,
+ BT_8822B_1ANT_PHASE_2G_FREERUN_ANT_BT = 0x8,
+ BT_8822B_1ANT_PHASE_MCC_DUALBAND_RUNTIME = 0x9,
+ BT_8822B_1ANT_PHASE_2G_FREERUN_ANT_S0WLS1BT = 0xa,
BT_8822B_1ANT_PHASE_MAX
};
+/*ADD SCOREBOARD TO FIX BT LPS 32K ISSUE WHILE WL BUSY*/
+enum bt_8822b_1ant_Scoreboard {
+ BT_8822B_1ANT_SCOREBOARD_ACTIVE = BIT(0),
+ BT_8822B_1ANT_SCOREBOARD_ONOFF = BIT(1),
+ BT_8822B_1ANT_SCOREBOARD_SCAN = BIT(2),
+ BT_8822B_1ANT_SCOREBOARD_UNDERTEST = BIT(3),
+ BT_8822B_1ANT_SCOREBOARD_RXGAIN = BIT(4),
+ BT_8822B_1ANT_SCOREBOARD_WLBUSY = BIT(6),
+ BT_8822B_1ANT_SCOREBOARD_EXTFEM = BIT(8),
+ BT_8822B_1ANT_SCOREBOARD_BTCQDDR = BIT(10)
+};
struct coex_dm_8822b_1ant {
/* hw setting */
@@ -173,6 +208,10 @@ struct coex_dm_8822b_1ant {
u8 cur_lps;
u8 pre_rpwm;
u8 cur_rpwm;
+ u8 pre_bt_dec_pwr_lvl;
+ u8 cur_bt_dec_pwr_lvl;
+ u8 pre_fw_dac_swing_lvl;
+ u8 cur_fw_dac_swing_lvl;
/* sw mechanism */
boolean pre_low_penalty_ra;
@@ -212,6 +251,8 @@ struct coex_dm_8822b_1ant {
u32 cur_ext_ant_switch_status;
u8 error_condition;
+ boolean pre_agc_table_en;
+ boolean cur_agc_table_en;
};
struct coex_sta_8822b_1ant {
@@ -221,7 +262,7 @@ struct coex_sta_8822b_1ant {
boolean a2dp_exist;
boolean hid_exist;
boolean pan_exist;
- boolean bt_hi_pri_link_exist;
+ boolean msft_mr_exist;
u8 num_of_profile;
boolean under_lps;
@@ -231,63 +272,126 @@ struct coex_sta_8822b_1ant {
u32 high_priority_rx;
u32 low_priority_tx;
u32 low_priority_rx;
+ boolean is_hiPri_rx_overhead;
s8 bt_rssi;
- boolean bt_tx_rx_mask;
u8 pre_bt_rssi_state;
u8 pre_wifi_rssi_state[4];
- boolean c2h_bt_info_req_sent;
u8 bt_info_c2h[BT_INFO_SRC_8822B_1ANT_MAX][10];
u32 bt_info_c2h_cnt[BT_INFO_SRC_8822B_1ANT_MAX];
boolean bt_whck_test;
boolean c2h_bt_inquiry_page;
- boolean c2h_bt_page; /* Add for win8.1 page out issue */
+ boolean c2h_bt_remote_name_req;
+ boolean c2h_bt_page; /* Add for win8.1 page out issue */
boolean wifi_is_high_pri_task; /* Add for win8.1 page out issue */
- u8 bt_retry_cnt;
+
u8 bt_info_ext;
+ u8 bt_info_ext2;
u32 pop_event_cnt;
u8 scan_ap_num;
+ u8 bt_retry_cnt;
u32 crc_ok_cck;
u32 crc_ok_11g;
u32 crc_ok_11n;
- u32 crc_ok_11n_agg;
+ u32 crc_ok_11n_vht;
u32 crc_err_cck;
u32 crc_err_11g;
u32 crc_err_11n;
- u32 crc_err_11n_agg;
+ u32 crc_err_11n_vht;
+
+ boolean cck_lock;
+ boolean cck_lock_ever;
+ boolean cck_lock_warn;
- boolean cck_lock;
- boolean pre_ccklock;
- boolean cck_ever_lock;
u8 coex_table_type;
- boolean force_lps_on;
- u32 wrong_profile_notification;
+ boolean force_lps_ctrl;
boolean concurrent_rx_mode_on;
- u32 special_pkt_period_cnt;
-
u16 score_board;
+ u8 isolation_btween_wb; /* 0~ 50 */
u8 a2dp_bit_pool;
u8 cut_version;
- boolean acl_busy;
- boolean wl_rf_off_on_event;
- boolean bt_create_connection;
- boolean run_time_state;
+ boolean acl_busy;
+ boolean bt_create_connection;
u32 bt_coex_supported_feature;
u32 bt_coex_supported_version;
+
+ u8 bt_ble_scan_type;
+ u32 bt_ble_scan_para[3];
+
+ boolean run_time_state;
+ boolean freeze_coexrun_by_btinfo;
+
+ boolean is_A2DP_3M;
+ boolean voice_over_HOGP;
+ u8 bt_info;
+ boolean is_autoslot;
+ u8 forbidden_slot;
+ u8 hid_busy_num;
+ u8 hid_pair_cnt;
+
+ u32 cnt_RemoteNameReq;
+ u32 cnt_setupLink;
+ u32 cnt_ReInit;
+ u32 cnt_IgnWlanAct;
+ u32 cnt_Page;
+ u32 cnt_RoleSwitch;
+
+ u16 bt_reg_vendor_ac;
+ u16 bt_reg_vendor_ae;
+
+ boolean is_setupLink;
+ u8 wl_noisy_level;
+ u32 gnt_error_cnt;
+ u8 bt_afh_map[10];
+ u8 bt_relink_downcount;
+ boolean is_tdma_btautoslot;
+ boolean is_tdma_btautoslot_hang;
+
+ u8 switch_band_notify_to;
+ boolean is_rf_state_off;
+
+ boolean is_hid_low_pri_tx_overhead;
+ boolean is_bt_multi_link;
+ boolean is_bt_a2dp_sink;
+
+ boolean is_set_ps_state_fail;
+ u8 cnt_set_ps_state_fail;
+
+ u8 wl_fw_dbg_info[10];
+ u8 wl_rx_rate;
+ u8 wl_rts_rx_rate;
+ u8 wl_center_channel;
+
+ u16 score_board_WB;
+ boolean is_hid_rcu;
+ u16 legacy_forbidden_slot;
+ u16 le_forbidden_slot;
+ u8 bt_a2dp_vendor_id;
+ u32 bt_a2dp_device_name;
+ boolean is_ble_scan_en;
+
+ boolean is_bt_opp_exist;
+ boolean gl_wifi_busy;
+
+ boolean is_mimo_ps;
+ u8 connect_ap_period_cnt;
+ boolean is_bt_reenable;
+ u8 cnt_bt_reenable;
};
-struct rfe_type_8822b_1ant{
+struct rfe_type_8822b_1ant {
- u8 rfe_module_type;
+ u8 rfe_module_type;
boolean ext_ant_switch_exist;
- u8 ext_ant_switch_type;
- u8 ext_ant_switch_ctrl_polarity; /* iF 0: ANTSW(rfe_sel9)=0, ANTSWB(rfe_sel8)=1 => Ant to BT/5G */
+ u8 ext_ant_switch_type;
+ /* iF 0: ANTSW(rfe_sel9)=0, ANTSWB(rfe_sel8)=1 => Ant to BT/5G */
+ u8 ext_ant_switch_ctrl_polarity;
};
@@ -330,6 +434,7 @@ struct psdscan_sta_8822b_1ant {
u32 psd_gen_count;
boolean is_psd_running;
boolean is_psd_show_max_only;
+ boolean is_AntDet_running;
};
/* *******************************************
@@ -346,8 +451,13 @@ void ex_halbtc8822b1ant_lps_notify(IN struct btc_coexist *btcoexist,
IN u8 type);
void ex_halbtc8822b1ant_scan_notify(IN struct btc_coexist *btcoexist,
IN u8 type);
+void ex_halbtc8822b1ant_scan_notify_without_bt(IN struct btc_coexist *btcoexist,
+ IN u8 type);
void ex_halbtc8822b1ant_switchband_notify(IN struct btc_coexist *btcoexist,
- IN u8 type);
+ IN u8 type);
+void ex_halbtc8822b1ant_switchband_notify_without_bt(IN struct btc_coexist
+ *btcoexist,
+ IN u8 type);
void ex_halbtc8822b1ant_connect_notify(IN struct btc_coexist *btcoexist,
IN u8 type);
void ex_halbtc8822b1ant_media_status_notify(IN struct btc_coexist *btcoexist,
@@ -356,6 +466,10 @@ void ex_halbtc8822b1ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
IN u8 type);
void ex_halbtc8822b1ant_bt_info_notify(IN struct btc_coexist *btcoexist,
IN u8 *tmp_buf, IN u8 length);
+void ex_halbtc8822b1ant_wl_fwdbginfo_notify(IN struct btc_coexist *btcoexist,
+ IN u8 *tmp_buf, IN u8 length);
+void ex_halbtc8822b1ant_rx_rate_change_notify(IN struct btc_coexist *btcoexist,
+ IN BOOLEAN is_data_frame, IN u8 btc_rate_id);
void ex_halbtc8822b1ant_rf_status_notify(IN struct btc_coexist *btcoexist,
IN u8 type);
void ex_halbtc8822b1ant_halt_notify(IN struct btc_coexist *btcoexist);
@@ -365,6 +479,8 @@ void ex_halbtc8822b1ant_ScoreBoardStatusNotify(IN struct btc_coexist *btcoexist,
IN u8 *tmp_buf, IN u8 length);
void ex_halbtc8822b1ant_coex_dm_reset(IN struct btc_coexist *btcoexist);
void ex_halbtc8822b1ant_periodical(IN struct btc_coexist *btcoexist);
+void ex_halbtc8822b1ant_display_simple_coex_info(IN struct btc_coexist *btcoexist);
+
void ex_halbtc8822b1ant_display_coex_info(IN struct btc_coexist *btcoexist);
void ex_halbtc8822b1ant_antenna_detection(IN struct btc_coexist *btcoexist,
IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds);
@@ -386,11 +502,15 @@ void ex_halbtc8822b1ant_dbg_control(IN struct btc_coexist *btcoexist,
#define ex_halbtc8822b1ant_ips_notify(btcoexist, type)
#define ex_halbtc8822b1ant_lps_notify(btcoexist, type)
#define ex_halbtc8822b1ant_scan_notify(btcoexist, type)
+#define ex_halbtc8822b1ant_scan_notify_without_bt(btcoexist, type)
#define ex_halbtc8822b1ant_switchband_notify(btcoexist, type)
+#define ex_halbtc8822b1ant_switchband_notify_without_bt(btcoexist, type)
#define ex_halbtc8822b1ant_connect_notify(btcoexist, type)
#define ex_halbtc8822b1ant_media_status_notify(btcoexist, type)
#define ex_halbtc8822b1ant_specific_packet_notify(btcoexist, type)
#define ex_halbtc8822b1ant_bt_info_notify(btcoexist, tmp_buf, length)
+#define ex_halbtc8822b1ant_wl_fwdbginfo_notify(btcoexist, tmp_buf, length)
+#define ex_halbtc8822b1ant_rx_rate_change_notify(btcoexist, is_data_frame, btc_rate_id)
#define ex_halbtc8822b1ant_rf_status_notify(btcoexist, type)
#define ex_halbtc8822b1ant_halt_notify(btcoexist)
#define ex_halbtc8822b1ant_pnp_notify(btcoexist, pnp_state)
@@ -404,5 +524,12 @@ void ex_halbtc8822b1ant_dbg_control(IN struct btc_coexist *btcoexist,
#define ex_halbtc8822b1ant_display_ant_detection(btcoexist)
#define ex_halbtc8822b1ant_dbg_control(btcoexist, op_code, op_len, pdata)
#endif
+#else
+
+void ex_halbtc8822b1ant_init_hw_config_without_bt(IN struct btc_coexist
+ *btcoexist);
+void ex_halbtc8822b1ant_switch_band_without_bt(IN struct btc_coexist *btcoexist,
+ IN boolean wifi_only_5g);
+
#endif
diff --git a/hal/btc/halbtc8822b2ant.c b/hal/btc/halbtc8822b2ant.c
new file mode 100644
index 0000000..6fdf427
--- /dev/null
+++ b/hal/btc/halbtc8822b2ant.c
@@ -0,0 +1,6123 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+
+/* ************************************************************
+ * Description:
+ *
+ * This file is for RTL8822B Co-exist mechanism
+ *
+ * History
+ * 2012/11/15 Cosa first check in.
+ *
+ * ************************************************************ */
+
+/* ************************************************************
+ * include files
+ * ************************************************************ */
+#include "mp_precomp.h"
+
+#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
+
+#if (RTL8822B_SUPPORT == 1)
+/* ************************************************************
+ * Global variables, these are static variables
+ * ************************************************************ */
+static u8 *trace_buf = &gl_btc_trace_buf[0];
+static struct coex_dm_8822b_2ant glcoex_dm_8822b_2ant;
+static struct coex_dm_8822b_2ant *coex_dm = &glcoex_dm_8822b_2ant;
+static struct coex_sta_8822b_2ant glcoex_sta_8822b_2ant;
+static struct coex_sta_8822b_2ant *coex_sta = &glcoex_sta_8822b_2ant;
+static struct psdscan_sta_8822b_2ant gl_psd_scan_8822b_2ant;
+static struct psdscan_sta_8822b_2ant *psd_scan = &gl_psd_scan_8822b_2ant;
+static struct rfe_type_8822b_2ant gl_rfe_type_8822b_2ant;
+static struct rfe_type_8822b_2ant *rfe_type = &gl_rfe_type_8822b_2ant;
+
+static const char *const glbt_info_src_8822b_2ant[] = {
+ "BT Info[wifi fw]",
+ "BT Info[bt rsp]",
+ "BT Info[bt auto report]",
+};
+
+u32 glcoex_ver_date_8822b_2ant = 20180427;
+u32 glcoex_ver_8822b_2ant = 0x59;
+u32 glcoex_ver_btdesired_8822b_2ant = 0x56;
+
+
+/* ************************************************************
+ * local function proto type if needed
+ * ************************************************************
+ * ************************************************************
+ * local function start with halbtc8822b2ant_
+ * ************************************************************ */
+static
+u8 halbtc8822b2ant_bt_rssi_state(IN struct btc_coexist *btcoexist,
+ u8 *ppre_bt_rssi_state, u8 level_num,
+ u8 rssi_thresh, u8 rssi_thresh1)
+{
+ s32 bt_rssi = 0;
+ u8 bt_rssi_state = *ppre_bt_rssi_state;
+
+ bt_rssi = coex_sta->bt_rssi;
+
+ if (level_num == 2) {
+ if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
+ (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
+ if (bt_rssi >= (rssi_thresh +
+ BTC_RSSI_COEX_THRESH_TOL_8822B_2ANT))
+ bt_rssi_state = BTC_RSSI_STATE_HIGH;
+ else
+ bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+ } else {
+ if (bt_rssi < rssi_thresh)
+ bt_rssi_state = BTC_RSSI_STATE_LOW;
+ else
+ bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+ }
+ } else if (level_num == 3) {
+ if (rssi_thresh > rssi_thresh1) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT Rssi thresh error!!\n");
+ BTC_TRACE(trace_buf);
+ return *ppre_bt_rssi_state;
+ }
+
+ if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
+ (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
+ if (bt_rssi >= (rssi_thresh +
+ BTC_RSSI_COEX_THRESH_TOL_8822B_2ANT))
+ bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
+ else
+ bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+ } else if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
+ (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
+ if (bt_rssi >= (rssi_thresh1 +
+ BTC_RSSI_COEX_THRESH_TOL_8822B_2ANT))
+ bt_rssi_state = BTC_RSSI_STATE_HIGH;
+ else if (bt_rssi < rssi_thresh)
+ bt_rssi_state = BTC_RSSI_STATE_LOW;
+ else
+ bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
+ } else {
+ if (bt_rssi < rssi_thresh1)
+ bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
+ else
+ bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+ }
+ }
+
+ *ppre_bt_rssi_state = bt_rssi_state;
+
+ return bt_rssi_state;
+}
+
+
+static
+u8 halbtc8822b2ant_wifi_rssi_state(IN struct btc_coexist *btcoexist,
+ IN u8 *pprewifi_rssi_state, IN u8 level_num, IN u8 rssi_thresh,
+ IN u8 rssi_thresh1)
+{
+ s32 wifi_rssi = 0;
+ u8 wifi_rssi_state = *pprewifi_rssi_state;
+
+ btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
+
+ if (level_num == 2) {
+ if ((*pprewifi_rssi_state == BTC_RSSI_STATE_LOW) ||
+ (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
+ if (wifi_rssi >= (rssi_thresh +
+ BTC_RSSI_COEX_THRESH_TOL_8822B_2ANT))
+ wifi_rssi_state = BTC_RSSI_STATE_HIGH;
+ else
+ wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+ } else {
+ if (wifi_rssi < rssi_thresh)
+ wifi_rssi_state = BTC_RSSI_STATE_LOW;
+ else
+ wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+ }
+ } else if (level_num == 3) {
+ if (rssi_thresh > rssi_thresh1) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], wifi RSSI thresh error!!\n");
+ BTC_TRACE(trace_buf);
+ return *pprewifi_rssi_state;
+ }
+
+ if ((*pprewifi_rssi_state == BTC_RSSI_STATE_LOW) ||
+ (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
+ if (wifi_rssi >= (rssi_thresh +
+ BTC_RSSI_COEX_THRESH_TOL_8822B_2ANT))
+ wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
+ else
+ wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
+ } else if ((*pprewifi_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
+ (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
+ if (wifi_rssi >= (rssi_thresh1 +
+ BTC_RSSI_COEX_THRESH_TOL_8822B_2ANT))
+ wifi_rssi_state = BTC_RSSI_STATE_HIGH;
+ else if (wifi_rssi < rssi_thresh)
+ wifi_rssi_state = BTC_RSSI_STATE_LOW;
+ else
+ wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
+ } else {
+ if (wifi_rssi < rssi_thresh1)
+ wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
+ else
+ wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
+ }
+ }
+
+ *pprewifi_rssi_state = wifi_rssi_state;
+
+ return wifi_rssi_state;
+}
+
+
+static
+void halbtc8822b2ant_coex_switch_threshold(IN struct btc_coexist *btcoexist,
+ IN u8 isolation_measuared)
+{
+ s8 interference_wl_tx = 0, interference_bt_tx = 0;
+
+
+ interference_wl_tx = BT_8822B_2ANT_WIFI_MAX_TX_POWER -
+ isolation_measuared;
+ interference_bt_tx = BT_8822B_2ANT_BT_MAX_TX_POWER -
+ isolation_measuared;
+
+ /* coex_sta->isolation_btween_wb default = 25dB, should be from config file */
+ if (coex_sta->isolation_btween_wb > 20) {
+
+ coex_sta->wifi_coex_thres = BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES1;
+ coex_sta->wifi_coex_thres2 = BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES2;
+
+ coex_sta->bt_coex_thres = BT_8822B_2ANT_BT_RSSI_COEXSWITCH_THRES1;
+ coex_sta->bt_coex_thres2 = BT_8822B_2ANT_BT_RSSI_COEXSWITCH_THRES2;
+ } else {
+
+ coex_sta->wifi_coex_thres = 90;
+ coex_sta->wifi_coex_thres2 = 90;
+
+ coex_sta->bt_coex_thres = 90;
+ coex_sta->bt_coex_thres2 = 90;
+ }
+
+#if 0
+ coex_sta->wifi_coex_thres = interference_wl_tx + BT_8822B_2ANT_WIFI_SIR_THRES1;
+ coex_sta->wifi_coex_thres2 = interference_wl_tx + BT_8822B_2ANT_WIFI_SIR_THRES2;
+
+ coex_sta->bt_coex_thres = interference_bt_tx + BT_8822B_2ANT_BT_SIR_THRES1;
+ coex_sta->bt_coex_thres2 = interference_bt_tx + BT_8822B_2ANT_BT_SIR_THRES2;
+#endif
+
+
+#if 0
+ if (BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 < (isolation_measuared -
+ BT_8822B_2ANT_DEFAULT_ISOLATION))
+ coex_sta->wifi_coex_thres = BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES1;
+ else
+ coex_sta->wifi_coex_thres = BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 - (isolation_measuared -
+ BT_8822B_2ANT_DEFAULT_ISOLATION);
+
+ if (BT_8822B_2ANT_BT_RSSI_COEXSWITCH_THRES1 < (isolation_measuared -
+ BT_8822B_2ANT_DEFAULT_ISOLATION))
+ coex_sta->bt_coex_thres = BT_8822B_2ANT_BT_RSSI_COEXSWITCH_THRES1;
+ else
+ coex_sta->bt_coex_thres = BT_8822B_2ANT_BT_RSSI_COEXSWITCH_THRES1 - (isolation_measuared -
+ BT_8822B_2ANT_DEFAULT_ISOLATION);
+
+#endif
+}
+
+static
+void halbtc8822b2ant_query_bt_info(IN struct btc_coexist *btcoexist)
+{
+ u8 h2c_parameter[1] = {0};
+
+ if (coex_sta->bt_disabled) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], No query BT info because BT is disabled!\n");
+ BTC_TRACE(trace_buf);
+ return;
+ }
+
+
+ h2c_parameter[0] |= BIT(0); /* trigger */
+
+ btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter);
+}
+
+
+static
+void halbtc8822b2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist)
+{
+ u32 reg_hp_txrx, reg_lp_txrx, u32tmp;
+ u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
+ static u8 num_of_bt_counter_chk = 0, cnt_slave = 0, cnt_autoslot_hang = 0;
+
+ struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+ reg_hp_txrx = 0x770;
+ reg_lp_txrx = 0x774;
+
+ u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
+ reg_hp_tx = u32tmp & MASKLWORD;
+ reg_hp_rx = (u32tmp & MASKHWORD) >> 16;
+
+ u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
+ reg_lp_tx = u32tmp & MASKLWORD;
+ reg_lp_rx = (u32tmp & MASKHWORD) >> 16;
+
+ coex_sta->high_priority_tx = reg_hp_tx;
+ coex_sta->high_priority_rx = reg_hp_rx;
+ coex_sta->low_priority_tx = reg_lp_tx;
+ coex_sta->low_priority_rx = reg_lp_rx;
+
+
+ /* reset counter */
+ btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
+
+ if ((coex_sta->low_priority_tx > 1050) &&
+ (!coex_sta->c2h_bt_inquiry_page))
+ coex_sta->pop_event_cnt++;
+
+ if ((coex_sta->low_priority_rx >= 950) &&
+ (coex_sta->low_priority_rx >= coex_sta->low_priority_tx)
+ && (!coex_sta->under_ips) && (!coex_sta->c2h_bt_inquiry_page) &&
+ (coex_sta->bt_link_exist)) {
+ if (cnt_slave >= 2) {
+ bt_link_info->slave_role = TRUE;
+ cnt_slave = 2;
+ } else {
+ cnt_slave++;
+ }
+ } else {
+ if (cnt_slave == 0) {
+ bt_link_info->slave_role = FALSE;
+ cnt_slave = 0;
+ } else {
+ cnt_slave--;
+ }
+
+ }
+
+ if (coex_sta->is_tdma_btautoslot) {
+ if ((coex_sta->low_priority_tx >= 1300) &&
+ (coex_sta->low_priority_rx <= 150)) {
+ if (cnt_autoslot_hang >= 2) {
+ coex_sta->is_tdma_btautoslot_hang = TRUE;
+ cnt_autoslot_hang = 2;
+ } else {
+ cnt_autoslot_hang++;
+ }
+ } else {
+ if (cnt_autoslot_hang == 0) {
+ coex_sta->is_tdma_btautoslot_hang = FALSE;
+ cnt_autoslot_hang = 0;
+ } else {
+ cnt_autoslot_hang--;
+ }
+ }
+ }
+
+ if (coex_sta->sco_exist) {
+ if ((coex_sta->high_priority_tx >= 400) &&
+ (coex_sta->high_priority_rx >= 400))
+ coex_sta->is_eSCO_mode = FALSE;
+ else
+ coex_sta->is_eSCO_mode = TRUE;
+ }
+
+ if (bt_link_info->hid_only) {
+ if (coex_sta->low_priority_tx > 50)
+ coex_sta->is_hid_low_pri_tx_overhead = true;
+ else
+ coex_sta->is_hid_low_pri_tx_overhead = false;
+ }
+
+ if ((coex_sta->high_priority_tx == 0) &&
+ (coex_sta->high_priority_rx == 0) &&
+ (coex_sta->low_priority_tx == 0) &&
+ (coex_sta->low_priority_rx == 0)) {
+ num_of_bt_counter_chk++;
+ if (num_of_bt_counter_chk >= 3) {
+ halbtc8822b2ant_query_bt_info(btcoexist);
+ num_of_bt_counter_chk = 0;
+ }
+ }
+
+}
+
+static
+void halbtc8822b2ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist)
+{
+ s32 wifi_rssi = 0;
+ boolean wifi_busy = FALSE, wifi_under_b_mode = FALSE,
+ wifi_scan = FALSE;
+ boolean bt_idle = FALSE;
+ static u8 cck_lock_counter = 0, wl_noisy_count0 = 0,
+ wl_noisy_count1 = 3, wl_noisy_count2 = 0;
+ u32 total_cnt, cnt_cck;
+ u32 cnt_crcok = 0, cnt_crcerr = 0;
+ static u8 cnt = 0, cnt_ccklocking = 0;
+ u8 h2c_parameter[1] = {0};
+ struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+ /* Only enable for windows becaus 8821cu H2C 0x69 unknown fail @ linux */
+ if (btcoexist->chip_interface != BTC_INTF_USB) {
+ /*send h2c to query WL FW dbg info */
+ if (((coex_dm->cur_ps_tdma_on) && (coex_sta->force_lps_ctrl)) ||
+ ((coex_sta->acl_busy) && (bt_link_info->a2dp_exist))) {
+ h2c_parameter[0] = 0x8;
+ btcoexist->btc_fill_h2c(btcoexist, 0x69, 1, h2c_parameter);
+ }
+ }
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+ btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
+ &wifi_under_b_mode);
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan);
+
+ coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_PHY_counter(
+ btcoexist,
+ PHYDM_INFO_CRC32_OK_CCK);
+ coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_PHY_counter(
+ btcoexist,
+ PHYDM_INFO_CRC32_OK_LEGACY);
+ coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_PHY_counter(
+ btcoexist,
+ PHYDM_INFO_CRC32_OK_HT);
+ coex_sta->crc_ok_11n_vht =
+ btcoexist->btc_phydm_query_PHY_counter(
+ btcoexist,
+ PHYDM_INFO_CRC32_OK_VHT);
+
+ coex_sta->crc_err_cck = btcoexist->btc_phydm_query_PHY_counter(
+ btcoexist, PHYDM_INFO_CRC32_ERROR_CCK);
+ coex_sta->crc_err_11g = btcoexist->btc_phydm_query_PHY_counter(
+ btcoexist, PHYDM_INFO_CRC32_ERROR_LEGACY);
+ coex_sta->crc_err_11n = btcoexist->btc_phydm_query_PHY_counter(
+ btcoexist, PHYDM_INFO_CRC32_ERROR_HT);
+ coex_sta->crc_err_11n_vht =
+ btcoexist->btc_phydm_query_PHY_counter(
+ btcoexist,
+ PHYDM_INFO_CRC32_ERROR_VHT);
+
+ cnt_crcok = coex_sta->crc_ok_cck + coex_sta->crc_ok_11g
+ + coex_sta->crc_ok_11n
+ + coex_sta->crc_ok_11n_vht;
+
+ cnt_crcerr = coex_sta->crc_err_cck + coex_sta->crc_err_11g
+ + coex_sta->crc_err_11n
+ + coex_sta->crc_err_11n_vht;
+
+ if ((wifi_busy) && (cnt_crcerr != 0)) {
+
+ coex_sta->now_crc_ratio = cnt_crcok/cnt_crcerr;
+
+ if (cnt == 0)
+ coex_sta->acc_crc_ratio = coex_sta->now_crc_ratio;
+ else
+ coex_sta->acc_crc_ratio = (coex_sta->acc_crc_ratio * 7 +
+ coex_sta->now_crc_ratio * 3)/10;
+
+ if (cnt >= 10)
+ cnt = 0;
+ else
+ cnt++;
+ }
+
+
+ /* CCK lock identification */
+ if (coex_sta->cck_lock)
+ cnt_ccklocking++;
+ else if (cnt_ccklocking != 0)
+ cnt_ccklocking--;
+
+ if (cnt_ccklocking >= 3) {
+ cnt_ccklocking = 3;
+ coex_sta->cck_lock_ever = TRUE;
+ }
+
+ /* WiFi environment noisy identification */
+ cnt_cck = coex_sta->crc_ok_cck + coex_sta->crc_err_cck;
+
+ if ((!wifi_busy) && (!coex_sta->cck_lock)) {
+ if (cnt_cck > 250) {
+ if (wl_noisy_count2 < 3)
+ wl_noisy_count2++;
+
+ if (wl_noisy_count2 == 3) {
+ wl_noisy_count0 = 0;
+ wl_noisy_count1 = 0;
+ }
+
+ } else if (cnt_cck < 100) {
+ if (wl_noisy_count0 < 3)
+ wl_noisy_count0++;
+
+ if (wl_noisy_count0 == 3) {
+ wl_noisy_count1 = 0;
+ wl_noisy_count2 = 0;
+ }
+
+ } else {
+ if (wl_noisy_count1 < 3)
+ wl_noisy_count1++;
+
+ if (wl_noisy_count1 == 3) {
+ wl_noisy_count0 = 0;
+ wl_noisy_count2 = 0;
+ }
+ }
+
+ if (wl_noisy_count2 == 3)
+ coex_sta->wl_noisy_level = 2;
+ else if (wl_noisy_count1 == 3)
+ coex_sta->wl_noisy_level = 1;
+ else
+ coex_sta->wl_noisy_level = 0;
+ }
+}
+
+
+static
+boolean halbtc8822b2ant_is_wifibt_status_changed(IN struct btc_coexist
+ *btcoexist)
+{
+ static boolean pre_wifi_busy = FALSE, pre_under_4way = FALSE,
+ pre_bt_hs_on = FALSE, pre_bt_off = FALSE,
+ pre_bt_slave = FALSE, pre_hid_low_pri_tx_overhead = FALSE,
+ pre_wifi_under_lps = FALSE, pre_bt_setup_link = FALSE;
+ static u8 pre_hid_busy_num = 0, pre_wl_noisy_level = 0;
+ boolean wifi_busy = FALSE, under_4way = FALSE, bt_hs_on = FALSE;
+ boolean wifi_connected = FALSE;
+ struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+ static u8 cnt_wifi_busytoidle = 0;
+ u32 wifi_link_status = 0, num_of_wifi_link = 0;
+ static u32 pre_num_of_wifi_link = 0;
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected);
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &under_4way);
+ btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
+ &wifi_link_status);
+
+ if (wifi_busy) {
+ coex_sta->gl_wifi_busy = TRUE;
+ cnt_wifi_busytoidle = 6;
+ } else {
+ if ((coex_sta->gl_wifi_busy) && (cnt_wifi_busytoidle > 0))
+ cnt_wifi_busytoidle--;
+ else if (cnt_wifi_busytoidle == 0)
+ coex_sta->gl_wifi_busy = FALSE;
+ }
+
+ if (coex_sta->bt_disabled != pre_bt_off) {
+ pre_bt_off = coex_sta->bt_disabled;
+
+ if (coex_sta->bt_disabled)
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT is disabled !!\n");
+ else
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT is enabled !!\n");
+
+ BTC_TRACE(trace_buf);
+
+ coex_sta->bt_coex_supported_feature = 0;
+ coex_sta->bt_coex_supported_version = 0;
+ coex_sta->bt_ble_scan_type = 0;
+ coex_sta->bt_ble_scan_para[0] = 0;
+ coex_sta->bt_ble_scan_para[1] = 0;
+ coex_sta->bt_ble_scan_para[2] = 0;
+ coex_sta->bt_reg_vendor_ac = 0xffff;
+ coex_sta->bt_reg_vendor_ae = 0xffff;
+ coex_sta->legacy_forbidden_slot = 0;
+ coex_sta->le_forbidden_slot = 0;
+ coex_sta->bt_a2dp_vendor_id = 0;
+ coex_sta->bt_a2dp_device_name = 0;
+ return TRUE;
+ }
+
+ num_of_wifi_link = wifi_link_status >> 16;
+
+ if (num_of_wifi_link != pre_num_of_wifi_link) {
+ pre_num_of_wifi_link = num_of_wifi_link;
+ return TRUE;
+ }
+
+ if (wifi_connected) {
+ if (wifi_busy != pre_wifi_busy) {
+ pre_wifi_busy = wifi_busy;
+ return TRUE;
+ }
+ if (under_4way != pre_under_4way) {
+ pre_under_4way = under_4way;
+ return TRUE;
+ }
+ if (bt_hs_on != pre_bt_hs_on) {
+ pre_bt_hs_on = bt_hs_on;
+ return TRUE;
+ }
+ if (coex_sta->wl_noisy_level != pre_wl_noisy_level) {
+ pre_wl_noisy_level = coex_sta->wl_noisy_level;
+ return TRUE;
+ }
+ if (coex_sta->under_lps != pre_wifi_under_lps) {
+ pre_wifi_under_lps = coex_sta->under_lps;
+ if (coex_sta->under_lps)
+ return TRUE;
+ }
+ }
+
+ if (!coex_sta->bt_disabled) {
+ if (coex_sta->hid_busy_num != pre_hid_busy_num) {
+ pre_hid_busy_num = coex_sta->hid_busy_num;
+ return TRUE;
+ }
+
+ if (bt_link_info->slave_role != pre_bt_slave) {
+ pre_bt_slave = bt_link_info->slave_role;
+ return TRUE;
+ }
+
+ if (pre_hid_low_pri_tx_overhead != coex_sta->is_hid_low_pri_tx_overhead) {
+ pre_hid_low_pri_tx_overhead = coex_sta->is_hid_low_pri_tx_overhead;
+ return TRUE;
+ }
+
+ if (pre_bt_setup_link != coex_sta->is_setupLink) {
+ pre_bt_setup_link = coex_sta->is_setupLink;
+ return TRUE;
+ }
+ }
+
+ return FALSE;
+}
+
+
+static
+void halbtc8822b2ant_update_bt_link_info(IN struct btc_coexist *btcoexist)
+{
+
+ struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+ boolean bt_hs_on = FALSE;
+ boolean bt_busy = FALSE;
+ u32 val = 0;
+ static u8 pre_num_of_profile = 0, cur_num_of_profile = 0, cnt = 0;
+ static u8 wd_cnt = 0;
+
+ if (++wd_cnt >= 3)
+ wd_cnt = 0;
+
+ if (coex_sta->is_ble_scan_en && (wd_cnt == 0)) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT ext info bit4 check, query BLE Scan type!!\n");
+ BTC_TRACE(trace_buf);
+ coex_sta->bt_ble_scan_type = btcoexist->btc_get_ble_scan_type_from_bt(
+ btcoexist);
+
+ if ((coex_sta->bt_ble_scan_type & 0x1) == 0x1)
+ coex_sta->bt_ble_scan_para[0] =
+ btcoexist->btc_get_ble_scan_para_from_bt(btcoexist,
+ 0x1);
+ if ((coex_sta->bt_ble_scan_type & 0x2) == 0x2)
+ coex_sta->bt_ble_scan_para[1] =
+ btcoexist->btc_get_ble_scan_para_from_bt(btcoexist,
+ 0x2);
+ if ((coex_sta->bt_ble_scan_type & 0x4) == 0x4)
+ coex_sta->bt_ble_scan_para[2] =
+ btcoexist->btc_get_ble_scan_para_from_bt(btcoexist,
+ 0x4);
+ }
+
+ coex_sta->num_of_profile = 0;
+
+ /* set link exist status */
+ if (!(coex_sta->bt_info & BT_INFO_8822B_1ANT_B_CONNECTION)) {
+ coex_sta->bt_link_exist = FALSE;
+ coex_sta->pan_exist = FALSE;
+ coex_sta->a2dp_exist = FALSE;
+ coex_sta->hid_exist = FALSE;
+ coex_sta->sco_exist = FALSE;
+ } else { /* connection exists */
+ coex_sta->bt_link_exist = TRUE;
+ if (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_FTP) {
+ coex_sta->pan_exist = TRUE;
+ coex_sta->num_of_profile++;
+ } else {
+ coex_sta->pan_exist = FALSE;
+ }
+
+ if (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_A2DP) {
+ coex_sta->a2dp_exist = TRUE;
+ coex_sta->num_of_profile++;
+ } else {
+ coex_sta->a2dp_exist = FALSE;
+ }
+
+ if (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_HID) {
+ coex_sta->hid_exist = TRUE;
+ coex_sta->num_of_profile++;
+ } else {
+ coex_sta->hid_exist = FALSE;
+ }
+
+ if (coex_sta->bt_info & BT_INFO_8822B_1ANT_B_SCO_ESCO) {
+ coex_sta->sco_exist = TRUE;
+ coex_sta->num_of_profile++;
+ } else {
+ coex_sta->sco_exist = FALSE;
+ }
+
+ }
+
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+
+ bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
+ bt_link_info->sco_exist = coex_sta->sco_exist;
+ bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
+ bt_link_info->pan_exist = coex_sta->pan_exist;
+ bt_link_info->hid_exist = coex_sta->hid_exist;
+ bt_link_info->acl_busy = coex_sta->acl_busy;
+
+ /* work around for HS mode. */
+ if (bt_hs_on) {
+ bt_link_info->pan_exist = TRUE;
+ bt_link_info->bt_link_exist = TRUE;
+ }
+
+ /* check if Sco only */
+ if (bt_link_info->sco_exist &&
+ !bt_link_info->a2dp_exist &&
+ !bt_link_info->pan_exist &&
+ !bt_link_info->hid_exist)
+ bt_link_info->sco_only = TRUE;
+ else
+ bt_link_info->sco_only = FALSE;
+
+ /* check if A2dp only */
+ if (!bt_link_info->sco_exist &&
+ bt_link_info->a2dp_exist &&
+ !bt_link_info->pan_exist &&
+ !bt_link_info->hid_exist)
+ bt_link_info->a2dp_only = TRUE;
+ else
+ bt_link_info->a2dp_only = FALSE;
+
+ /* check if Pan only */
+ if (!bt_link_info->sco_exist &&
+ !bt_link_info->a2dp_exist &&
+ bt_link_info->pan_exist &&
+ !bt_link_info->hid_exist)
+ bt_link_info->pan_only = TRUE;
+ else
+ bt_link_info->pan_only = FALSE;
+
+ /* check if Hid only */
+ if (!bt_link_info->sco_exist &&
+ !bt_link_info->a2dp_exist &&
+ !bt_link_info->pan_exist &&
+ bt_link_info->hid_exist)
+ bt_link_info->hid_only = TRUE;
+ else
+ bt_link_info->hid_only = FALSE;
+
+ if (coex_sta->bt_info & BT_INFO_8822B_2ANT_B_INQ_PAGE) {
+ coex_dm->bt_status = BT_8822B_2ANT_BT_STATUS_INQ_PAGE;
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BtInfoNotify(), BT Inq/page!!!\n");
+ } else if (!(coex_sta->bt_info & BT_INFO_8822B_2ANT_B_CONNECTION)) {
+ coex_dm->bt_status = BT_8822B_2ANT_BT_STATUS_NON_CONNECTED_IDLE;
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n");
+ } else if (coex_sta->bt_info == BT_INFO_8822B_2ANT_B_CONNECTION) {
+ /* connection exists but no busy */
+ coex_dm->bt_status = BT_8822B_2ANT_BT_STATUS_CONNECTED_IDLE;
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n");
+ } else if (((coex_sta->bt_info & BT_INFO_8822B_2ANT_B_SCO_ESCO) ||
+ (coex_sta->bt_info & BT_INFO_8822B_2ANT_B_SCO_BUSY)) &&
+ (coex_sta->bt_info & BT_INFO_8822B_2ANT_B_ACL_BUSY)) {
+ coex_dm->bt_status = BT_8822B_2ANT_BT_STATUS_ACL_SCO_BUSY;
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BtInfoNotify(), BT ACL SCO busy!!!\n");
+ } else if ((coex_sta->bt_info & BT_INFO_8822B_2ANT_B_SCO_ESCO) ||
+ (coex_sta->bt_info & BT_INFO_8822B_2ANT_B_SCO_BUSY)) {
+ coex_dm->bt_status = BT_8822B_2ANT_BT_STATUS_SCO_BUSY;
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n");
+ } else if (coex_sta->bt_info & BT_INFO_8822B_2ANT_B_ACL_BUSY) {
+ coex_dm->bt_status = BT_8822B_2ANT_BT_STATUS_ACL_BUSY;
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n");
+ } else {
+ coex_dm->bt_status = BT_8822B_2ANT_BT_STATUS_MAX;
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n");
+ }
+
+ BTC_TRACE(trace_buf);
+
+ if ((coex_dm->bt_status == BT_8822B_2ANT_BT_STATUS_ACL_BUSY) ||
+ (coex_dm->bt_status == BT_8822B_2ANT_BT_STATUS_SCO_BUSY) ||
+ (coex_dm->bt_status == BT_8822B_2ANT_BT_STATUS_ACL_SCO_BUSY))
+ bt_busy = TRUE;
+ else
+ bt_busy = FALSE;
+
+ btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
+
+ cur_num_of_profile = coex_sta->num_of_profile;
+
+ if (cur_num_of_profile != pre_num_of_profile)
+ cnt = 2;
+
+ if (bt_link_info->a2dp_exist) {
+
+ if (((coex_sta->bt_a2dp_vendor_id == 0) &&
+ (coex_sta->bt_a2dp_device_name == 0)) ||
+ (cur_num_of_profile != pre_num_of_profile)) {
+
+ btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_DEVICE_INFO, &val);
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BtInfoNotify(), get BT DEVICE_INFO = %x\n", val);
+ BTC_TRACE(trace_buf);
+
+ coex_sta->bt_a2dp_vendor_id = (u8)(val & 0xff);
+ coex_sta->bt_a2dp_device_name = (val & 0xffffff00) >> 8;
+ }
+
+ if (((coex_sta->legacy_forbidden_slot == 0) &&
+ (coex_sta->le_forbidden_slot == 0)) ||
+ (cur_num_of_profile != pre_num_of_profile) ||
+ (cnt > 0)) {
+
+ if (cnt > 0)
+ cnt--;
+
+ btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_FORBIDDEN_SLOT_VAL, &val);
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BtInfoNotify(), get BT FORBIDDEN_SLOT_VAL = %x\n", val);
+ BTC_TRACE(trace_buf);
+
+ coex_sta->legacy_forbidden_slot = (u16)(val & 0xffff);
+ coex_sta->le_forbidden_slot = (u16)((val & 0xffff0000) >> 16);
+ }
+ }
+
+ pre_num_of_profile = coex_sta->num_of_profile;
+}
+
+
+static
+void halbtc8822b2ant_update_wifi_channel_info(IN struct btc_coexist *btcoexist,
+ IN u8 type)
+{
+ u8 h2c_parameter[3] = {0}, i;
+ u32 wifi_bw;
+ u8 wifi_central_chnl = 0;
+ u8 wifi_5g_chnl[19] = {120, 124, 128, 132, 136, 140, 144, 149, 153, 157, 118, 126, 134, 142, 151, 159, 122, 138, 155};
+ u8 bt_skip_cneter_chanl[19] = {2, 8, 17, 26, 34, 42, 51, 62, 71, 77, 2, 12, 29, 46, 66, 76, 10, 37, 68};
+ u8 bt_skip_span[19] = {4, 8, 8, 10, 8, 10, 8, 8, 10, 4, 4, 16, 16, 16, 16, 4, 20, 34, 20};
+ boolean wifi_under_5g = FALSE;
+
+
+ btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+
+ if (type == BTC_MEDIA_CONNECT) {
+ btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
+ &wifi_central_chnl);
+ coex_sta->wl_center_channel = wifi_central_chnl;
+
+ if (!wifi_under_5g) {
+
+ h2c_parameter[0] = 0x1;
+ h2c_parameter[1] = wifi_central_chnl;
+
+ if (wifi_bw == BTC_WIFI_BW_HT40)
+ h2c_parameter[2] = 0x36;
+ else
+ h2c_parameter[2] = 0x30;
+ } else { /* for 5G */
+
+ for (i = 0; i <= 18; i++) {
+ if (wifi_central_chnl == wifi_5g_chnl[i])
+ break;
+ }
+
+ if (i <= 18) {
+ h2c_parameter[0] = 0x3;
+ h2c_parameter[1] = bt_skip_cneter_chanl[i];
+ h2c_parameter[2] = bt_skip_span[i];
+ }
+
+ }
+ }
+
+ coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
+ coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
+ coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
+
+ btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter);
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], para[0:2] = 0x%x 0x%x 0x%x\n",
+ h2c_parameter[0], h2c_parameter[1], h2c_parameter[2]);
+ BTC_TRACE(trace_buf);
+
+}
+
+
+static
+void halbtc8822b2ant_low_penalty_ra(IN struct btc_coexist *btcoexist,
+ IN boolean force_exec, IN boolean low_penalty_ra)
+{
+
+#if 1
+ coex_dm->cur_low_penalty_ra = low_penalty_ra;
+
+ if (!force_exec) {
+ if (coex_dm->pre_low_penalty_ra ==
+ coex_dm->cur_low_penalty_ra)
+ return;
+ }
+
+ if (low_penalty_ra)
+ btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 10);
+ else
+ btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 0);
+
+ coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra;
+
+#endif
+
+}
+
+static
+void halbtc8822b2ant_write_score_board(
+ IN struct btc_coexist *btcoexist,
+ IN u16 bitpos,
+ IN boolean state
+)
+{
+
+ static u16 originalval = 0x8002, preval = 0x0;
+
+ if (state)
+ originalval = originalval | bitpos;
+ else
+ originalval = originalval & (~bitpos);
+
+ coex_sta->score_board_WB = originalval;
+
+ if (originalval != preval) {
+
+ preval = originalval;
+ btcoexist->btc_write_2byte(btcoexist, 0xaa, originalval);
+ } else {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], halbtc8822b2ant_write_score_board: return for nochange\n");
+ BTC_TRACE(trace_buf);
+ }
+}
+
+
+static
+void halbtc8822b2ant_read_score_board(
+ IN struct btc_coexist *btcoexist,
+ IN u16 *score_board_val
+)
+{
+
+ *score_board_val = (btcoexist->btc_read_2byte(btcoexist,
+ 0xaa)) & 0x7fff;
+}
+
+static
+void halbtc8822b2ant_post_state_to_bt(
+ IN struct btc_coexist *btcoexist,
+ IN u16 type,
+ IN BOOLEAN state
+)
+{
+
+ halbtc8822b2ant_write_score_board(btcoexist, (u16) type, state);
+
+}
+
+static
+void halbtc8822b2ant_adjust_wl_tx_power(IN struct btc_coexist *btcoexist,
+ IN boolean force_exec, IN u8 fw_dac_swing_lvl)
+{
+
+ coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl;
+
+ if (!force_exec) {
+ if (coex_dm->pre_fw_dac_swing_lvl ==
+ coex_dm->cur_fw_dac_swing_lvl)
+ return;
+ }
+
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc5b, 0xff, fw_dac_swing_lvl);
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0xe5b, 0xff, fw_dac_swing_lvl);
+
+ coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl;
+}
+
+static
+void halbtc8822b2ant_adjust_bt_tx_power(IN struct btc_coexist *btcoexist,
+ IN boolean force_exec, IN u8 dec_bt_pwr_lvl)
+{
+ u8 h2c_parameter[1] = {0};
+
+ coex_dm->cur_bt_dec_pwr_lvl = dec_bt_pwr_lvl;
+
+ if (!force_exec) {
+ if (coex_dm->pre_bt_dec_pwr_lvl == coex_dm->cur_bt_dec_pwr_lvl)
+ return;
+ }
+
+ //h2c_parameter[0] = 0 - dec_bt_pwr_lvl;
+ h2c_parameter[0] = dec_bt_pwr_lvl;
+
+
+ btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter);
+
+ coex_dm->pre_bt_dec_pwr_lvl = coex_dm->cur_bt_dec_pwr_lvl;
+}
+
+static
+void halbtc8822b2ant_adjust_wl_rx_gain(IN struct btc_coexist *btcoexist,
+ IN boolean force_exec, IN boolean agc_table_en)
+{
+
+ /*20171116*/
+
+ u32 rx_gain_value_enable[] = {0xff000003,
+ 0xbd120003, 0xbe100003, 0xbf080003, 0xbf060003, 0xbf050003,
+ 0xbc140003, 0xbb160003, 0xba180003, 0xb91a0003, 0xb81c0003,
+ 0xb71e0003, 0xb4200003, 0xb5220003, 0xb4240003, 0xb3260003,
+ 0xb2280003, 0xb12a0003, 0xb02c0003, 0xaf2e0003, 0xae300003,
+ 0xad320003, 0xac340003, 0xab360003, 0x8d380003, 0x8c3a0003,
+ 0x8b3c0003, 0x8a3e0003, 0x6e400003, 0x6d420003, 0x6c440003,
+ 0x6b460003, 0x6a480003, 0x694a0003, 0x684c0003, 0x674e0003,
+ 0x66500003, 0x65520003, 0x64540003, 0x64560003, 0x007e0403};
+
+ u32 rx_gain_value_disable[] = {0xff000003,
+ 0xf4120003, 0xf5100003, 0xf60e0003, 0xf70c0003, 0xf80a0003,
+ 0xf3140003, 0xf2160003, 0xf1180003, 0xf01a0003, 0xef1c0003,
+ 0xee1e0003, 0xed200003, 0xec220003, 0xeb240003, 0xea260003,
+ 0xe9280003, 0xe82a0003, 0xe72c0003, 0xe62e0003, 0xe5300003,
+ 0xc8320003, 0xc7340003, 0xc6360003, 0xc5380003, 0xc43a0003,
+ 0xc33c0003, 0xc23e0003, 0xc1400003, 0xc0420003, 0xa5440003,
+ 0xa4460003, 0xa3480003, 0xa24a0003, 0xa14c0003, 0x834e0003,
+ 0x82500003, 0x81520003, 0x80540003, 0x65560003, 0x007e0403};
+
+
+#if 0
+ /*20170110*/
+
+ u32 rx_gain_value_enable[] = {0xff000003,
+ 0xb6200003, 0xb5220003, 0xb4240003, 0xb3260003,
+ 0xb2280003, 0xb12a0003, 0xb02c0003, 0xaf2e0003, 0xae300003,
+ 0xad320003, 0xac340003, 0xab360003, 0x8d380003, 0x8c3a0003,
+ 0x8b3c0003, 0x8a3e0003, 0x6e400003, 0x6d420003, 0x6c440003,
+ 0x6b460003, 0x6a480003, 0x694a0003, 0x684c0003, 0x674e0003,
+ 0x66500003, 0x65520003, 0x64540003, 0x64560003, 0x007e0403};
+
+ /*20170110*/
+
+
+ u32 rx_gain_value_disable[] = {0xff000003, 0xeb240003, 0xea260003,
+ 0xe9280003, 0xe82a0003, 0xe72c0003, 0xe62e0003, 0xe5300003,
+ 0xc8320003, 0xc7340003, 0xc6360003, 0xc5380003, 0xc43a0003,
+ 0xc33c0003, 0xc23e0003, 0xc1400003, 0xc0420003, 0xa5440003,
+ 0xa4460003, 0xa3480003, 0xa24a0003, 0xa14c0003, 0x834e0003,
+ 0x82500003, 0x81520003, 0x80540003, 0x65560003, 0x007e0403};
+#endif
+ u8 i;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], *************wl rx gain*************\n");
+ BTC_TRACE(trace_buf);
+
+ coex_dm->cur_agc_table_en = agc_table_en;
+
+ if (!force_exec) {
+ if (coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en)
+ return;
+ }
+
+ if (agc_table_en) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BB Agc Table On!\n");
+ BTC_TRACE(trace_buf);
+
+ for (i = 0; i <= 100; i++) {
+ btcoexist->btc_write_4byte(btcoexist,
+ 0x81c, rx_gain_value_enable[i]);
+
+ if (rx_gain_value_enable[i] == 0x007e0403)
+ break;
+ }
+
+ /* set Rx filter corner RCK offset */
+ btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xde, 0x2, 0x1);
+ btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1d, 0x3f, 0x3f);
+ btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_B, 0xde, 0x2, 0x1);
+ btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_B, 0x1d, 0x3f, 0x3f);
+ /* ADC clock 80M */
+ /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x8ad, 0x3, 0x3); */
+
+ } else {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BB Agc Table Off!\n");
+ BTC_TRACE(trace_buf);
+
+ for (i = 0; i <= 100; i++) {
+ btcoexist->btc_write_4byte(btcoexist,
+ 0x81c, rx_gain_value_disable[i]);
+
+ if (rx_gain_value_disable[i] == 0x007e0403)
+ break;
+ }
+
+ /* set Rx filter corner RCK offset */
+ btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1d, 0x3f, 0x4);
+ btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xde, 0x2, 0x0);
+ btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_B, 0x1d, 0x3f, 0x4);
+ btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_B, 0xde, 0x2, 0x0);
+ /* ADC clock 160M */
+ /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x8ad, 0x3, 0x0); */
+ }
+
+
+ coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en;
+}
+
+static
+void halbtc8822b2ant_adjust_bt_rx_gain(IN struct btc_coexist *btcoexist,
+ IN boolean force_exec, IN boolean rx_gain_en)
+{
+ u8 lna_constrain_level = 0;
+
+ /* use scoreboard[4] to notify BT Rx gain table change */
+ halbtc8822b2ant_post_state_to_bt(btcoexist,
+ BT_8822B_2ANT_SCOREBOARD_RXGAIN,
+ rx_gain_en);
+
+ if (rx_gain_en)
+ lna_constrain_level = 1;
+ else
+ lna_constrain_level = 7;
+
+ btcoexist->btc_set(btcoexist,
+ BTC_SET_BL_BT_LNA_CONSTRAIN_LEVEL,
+ &lna_constrain_level);
+}
+
+
+static
+void halbtc8822b2ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist)
+{
+ static u32 bt_disable_cnt = 0;
+ boolean bt_active = TRUE, bt_disabled = FALSE, wifi_under_5g = FALSE;
+ u16 u16tmp;
+
+ /* This function check if bt is disabled */
+#if 0
+ if (coex_sta->high_priority_tx == 0 &&
+ coex_sta->high_priority_rx == 0 &&
+ coex_sta->low_priority_tx == 0 &&
+ coex_sta->low_priority_rx == 0)
+ bt_active = FALSE;
+ if (coex_sta->high_priority_tx == 0xffff &&
+ coex_sta->high_priority_rx == 0xffff &&
+ coex_sta->low_priority_tx == 0xffff &&
+ coex_sta->low_priority_rx == 0xffff)
+ bt_active = FALSE;
+
+
+#else
+
+ /* Read BT on/off status from scoreboard[1],
+ * enable this only if BT patch support this feature
+ */
+ halbtc8822b2ant_read_score_board(btcoexist, &u16tmp);
+
+ bt_active = u16tmp & BIT(1);
+
+
+#endif
+
+ if (bt_active) {
+ bt_disable_cnt = 0;
+ bt_disabled = FALSE;
+ btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
+ &bt_disabled);
+ } else {
+
+ bt_disable_cnt++;
+ if (bt_disable_cnt >= 10) {
+ bt_disabled = TRUE;
+ bt_disable_cnt = 10;
+ }
+
+ btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
+ &bt_disabled);
+ }
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+
+ if ((wifi_under_5g) || (bt_disabled))
+ halbtc8822b2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, FALSE);
+ else
+ halbtc8822b2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, TRUE);
+
+
+ if (coex_sta->bt_disabled != bt_disabled) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT is from %s to %s!!\n",
+ (coex_sta->bt_disabled ? "disabled" : "enabled"),
+ (bt_disabled ? "disabled" : "enabled"));
+ BTC_TRACE(trace_buf);
+ coex_sta->bt_disabled = bt_disabled;
+ }
+
+}
+
+static
+void halbtc8822b2ant_enable_gnt_to_gpio(IN struct btc_coexist *btcoexist,
+ boolean isenable)
+{
+#if BT_8822B_2ANT_COEX_DBG
+ static u8 bitVal[5] = {0, 0, 0, 0, 0};
+#if 0
+ static boolean state = FALSE;
+
+ if (state == isenable)
+ return;
+
+ state = isenable;
+#endif
+
+ if (isenable) {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], enable_gnt_to_gpio!!\n");
+ BTC_TRACE(trace_buf);
+
+ /* enable GNT_WL, GNT_BT to GPIO for debug */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x1);
+
+ /* store original value */
+ bitVal[0] = (btcoexist->btc_read_1byte(btcoexist,
+ 0x66) & BIT(4)) >> 4; /*0x66[4] */
+ bitVal[1] = (btcoexist->btc_read_1byte(btcoexist,
+ 0x67) & BIT(0)); /*0x66[8] */
+ bitVal[2] = (btcoexist->btc_read_1byte(btcoexist,
+ 0x42) & BIT(3)) >> 3; /*0x40[19] */
+ bitVal[3] = (btcoexist->btc_read_1byte(btcoexist,
+ 0x65) & BIT(7)) >> 7; /*0x64[15] */
+ bitVal[4] = (btcoexist->btc_read_1byte(btcoexist,
+ 0x72) & BIT(2)) >> 2; /*0x70[18] */
+
+ /* switch GPIO Mux */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, BIT(4),
+ 0x0); /*0x66[4] = 0 */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, BIT(0),
+ 0x0); /*0x66[8] = 0 */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, BIT(3),
+ 0x0); /*0x40[19] = 0 */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x65, BIT(7),
+ 0x0); /*0x64[15] = 0 */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x72, BIT(2),
+ 0x0); /*0x70[18] = 0 */
+
+
+ } else {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], disable_gnt_to_gpio!!\n");
+ BTC_TRACE(trace_buf);
+
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x0);
+
+ /* Restore original value */
+ /* switch GPIO Mux */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, BIT(4),
+ bitVal[0]); /*0x66[4] = 0 */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, BIT(0),
+ bitVal[1]); /*0x66[8] = 0 */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, BIT(3),
+ bitVal[2]); /*0x40[19] = 0 */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x65, BIT(7),
+ bitVal[3]); /*0x64[15] = 0 */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x72, BIT(2),
+ bitVal[4]); /*0x70[18] = 0 */
+ }
+
+#endif
+}
+
+
+static
+u32 halbtc8822b2ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist,
+ IN u16 reg_addr)
+{
+ u32 delay_count = 0;
+
+ while (1) {
+ if ((btcoexist->btc_read_1byte(btcoexist, 0x1703)&BIT(5)) == 0) {
+ delay_ms(10);
+ delay_count++;
+ if (delay_count >= 10) {
+ delay_count = 0;
+ break;
+ }
+ } else {
+ break;
+ }
+ }
+
+ /* wait for ready bit before access 0x1700 */
+ btcoexist->btc_write_4byte(btcoexist, 0x1700, 0x800F0000 | reg_addr);
+
+ return btcoexist->btc_read_4byte(btcoexist,
+ 0x1708); /* get read data */
+
+}
+
+
+static
+void halbtc8822b2ant_ltecoex_indirect_write_reg(IN struct btc_coexist
+ *btcoexist,
+ IN u16 reg_addr, IN u32 bit_mask, IN u32 reg_value)
+{
+ u32 val, i = 0, bitpos = 0, delay_count = 0;
+
+
+ if (bit_mask == 0x0)
+ return;
+ if (bit_mask == 0xffffffff) {
+ /* wait for ready bit before access 0x1700/0x1704 */
+ while (1) {
+ if ((btcoexist->btc_read_1byte(btcoexist, 0x1703)&BIT(5)) == 0) {
+ delay_ms(10);
+ delay_count++;
+ if (delay_count >= 10) {
+ delay_count = 0;
+ break;
+ }
+ } else {
+ break;
+ }
+ }
+
+ btcoexist->btc_write_4byte(btcoexist, 0x1704,
+ reg_value); /* put write data */
+
+ btcoexist->btc_write_4byte(btcoexist, 0x1700,
+ 0xc00F0000 | reg_addr);
+ } else {
+ for (i = 0; i <= 31; i++) {
+ if (((bit_mask >> i) & 0x1) == 0x1) {
+ bitpos = i;
+ break;
+ }
+ }
+
+ /* read back register value before write */
+ val = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist,
+ reg_addr);
+ val = (val & (~bit_mask)) | (reg_value << bitpos);
+
+ /* wait for ready bit before access 0x1700/0x1704 */
+ while (1) {
+ if ((btcoexist->btc_read_1byte(btcoexist, 0x1703)&BIT(5)) == 0) {
+ delay_ms(10);
+ delay_count++;
+ if (delay_count >= 10) {
+ delay_count = 0;
+ break;
+ }
+ } else {
+ break;
+ }
+ }
+
+ btcoexist->btc_write_4byte(btcoexist, 0x1704,
+ val); /* put write data */
+
+ btcoexist->btc_write_4byte(btcoexist, 0x1700,
+ 0xc00F0000 | reg_addr);
+ }
+
+}
+
+
+static
+void halbtc8822b2ant_ltecoex_enable(IN struct btc_coexist *btcoexist,
+ IN boolean enable)
+{
+ u8 val;
+
+ val = (enable) ? 1 : 0;
+ halbtc8822b2ant_ltecoex_indirect_write_reg(btcoexist, 0x38, 0x80,
+ val); /* 0x38[7] */
+
+}
+
+static
+void halbtc8822b2ant_ltecoex_pathcontrol_owner(IN struct btc_coexist *btcoexist,
+ IN boolean wifi_control)
+{
+ u8 val;
+
+ val = (wifi_control) ? 1 : 0;
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x4,
+ val); /* 0x70[26] */
+
+}
+
+static
+void halbtc8822b2ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist,
+ IN u8 control_block, IN boolean sw_control, IN u8 state)
+{
+ u32 val = 0, bit_mask;
+
+ state = state & 0x1;
+ val = (sw_control) ? ((state << 1) | 0x1) : 0;
+
+ switch (control_block) {
+ case BT_8822B_2ANT_GNT_BLOCK_RFC_BB:
+ default:
+ bit_mask = 0xc000;
+ halbtc8822b2ant_ltecoex_indirect_write_reg(btcoexist,
+ 0x38, bit_mask, val); /* 0x38[15:14] */
+ bit_mask = 0x0c00;
+ halbtc8822b2ant_ltecoex_indirect_write_reg(btcoexist,
+ 0x38, bit_mask, val); /* 0x38[11:10] */
+ break;
+ case BT_8822B_2ANT_GNT_BLOCK_RFC:
+ bit_mask = 0xc000;
+ halbtc8822b2ant_ltecoex_indirect_write_reg(btcoexist,
+ 0x38, bit_mask, val); /* 0x38[15:14] */
+ break;
+ case BT_8822B_2ANT_GNT_BLOCK_BB:
+ bit_mask = 0x0c00;
+ halbtc8822b2ant_ltecoex_indirect_write_reg(btcoexist,
+ 0x38, bit_mask, val); /* 0x38[11:10] */
+ break;
+
+ }
+
+}
+
+static
+void halbtc8822b2ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist,
+ IN u8 control_block, IN boolean sw_control, IN u8 state)
+{
+ u32 val = 0, bit_mask;
+
+ state = state & 0x1;
+ val = (sw_control) ? ((state << 1) | 0x1) : 0;
+
+ switch (control_block) {
+ case BT_8822B_2ANT_GNT_BLOCK_RFC_BB:
+ default:
+ bit_mask = 0x3000;
+ halbtc8822b2ant_ltecoex_indirect_write_reg(btcoexist,
+ 0x38, bit_mask, val); /* 0x38[13:12] */
+ bit_mask = 0x0300;
+ halbtc8822b2ant_ltecoex_indirect_write_reg(btcoexist,
+ 0x38, bit_mask, val); /* 0x38[9:8] */
+ break;
+ case BT_8822B_2ANT_GNT_BLOCK_RFC:
+ bit_mask = 0x3000;
+ halbtc8822b2ant_ltecoex_indirect_write_reg(btcoexist,
+ 0x38, bit_mask, val); /* 0x38[13:12] */
+ break;
+ case BT_8822B_2ANT_GNT_BLOCK_BB:
+ bit_mask = 0x0300;
+ halbtc8822b2ant_ltecoex_indirect_write_reg(btcoexist,
+ 0x38, bit_mask, val); /* 0x38[9:8] */
+ break;
+
+ }
+
+}
+
+static
+void halbtc8822b2ant_ltecoex_set_coex_table(IN struct btc_coexist *btcoexist,
+ IN u8 table_type, IN u16 table_content)
+{
+ u16 reg_addr = 0x0000;
+
+ switch (table_type) {
+ case BT_8822B_2ANT_CTT_WL_VS_LTE:
+ reg_addr = 0xa0;
+ break;
+ case BT_8822B_2ANT_CTT_BT_VS_LTE:
+ reg_addr = 0xa4;
+ break;
+ }
+
+ if (reg_addr != 0x0000)
+ halbtc8822b2ant_ltecoex_indirect_write_reg(btcoexist, reg_addr,
+ 0xffff, table_content); /* 0xa0[15:0] or 0xa4[15:0] */
+
+
+}
+
+
+static
+void halbtc8822b2ant_set_wltoggle_coex_table(IN struct btc_coexist *btcoexist,
+ IN boolean force_exec, IN u8 interval,
+ IN u8 val0x6c4_b0, IN u8 val0x6c4_b1, IN u8 val0x6c4_b2,
+ IN u8 val0x6c4_b3)
+{
+ static u8 pre_h2c_parameter[6] = {0};
+ u8 cur_h2c_parameter[6] = {0};
+ u8 i, match_cnt = 0;
+
+ cur_h2c_parameter[0] = 0x7; /* op_code, 0x7= wlan toggle slot*/
+
+ cur_h2c_parameter[1] = interval;
+ cur_h2c_parameter[2] = val0x6c4_b0;
+ cur_h2c_parameter[3] = val0x6c4_b1;
+ cur_h2c_parameter[4] = val0x6c4_b2;
+ cur_h2c_parameter[5] = val0x6c4_b3;
+
+ if (!force_exec) {
+ for (i = 1; i <= 5; i++) {
+ if (cur_h2c_parameter[i] != pre_h2c_parameter[i])
+ break;
+
+ match_cnt++;
+ }
+
+ if (match_cnt == 5)
+ return;
+ }
+
+ for (i = 1; i <= 5; i++)
+ pre_h2c_parameter[i] = cur_h2c_parameter[i];
+
+ btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, cur_h2c_parameter);
+}
+
+static
+void halbtc8822b2ant_set_coex_table(IN struct btc_coexist *btcoexist,
+ IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc)
+{
+ btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
+
+ btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
+
+ btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
+
+ btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
+}
+
+static
+void halbtc8822b2ant_coex_table(IN struct btc_coexist *btcoexist,
+ IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4,
+ IN u32 val0x6c8, IN u8 val0x6cc)
+{
+ coex_dm->cur_val0x6c0 = val0x6c0;
+ coex_dm->cur_val0x6c4 = val0x6c4;
+ coex_dm->cur_val0x6c8 = val0x6c8;
+ coex_dm->cur_val0x6cc = val0x6cc;
+
+ if (!force_exec) {
+ if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) &&
+ (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) &&
+ (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) &&
+ (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc))
+ return;
+ }
+ halbtc8822b2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8,
+ val0x6cc);
+
+ coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0;
+ coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4;
+ coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8;
+ coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc;
+}
+
+static
+void halbtc8822b2ant_coex_table_with_type(IN struct btc_coexist *btcoexist,
+ IN boolean force_exec, IN u8 type)
+{
+ u32 break_table;
+ u8 select_table;
+
+ coex_sta->coex_table_type = type;
+
+ if (coex_sta->concurrent_rx_mode_on) {
+ break_table = 0xf0ffffff; /* set WL hi-pri can break BT */
+ /* set Tx response = Hi-Pri (ex: Transmitting ACK,BA,CTS) */
+ select_table = 0xb;
+ } else {
+ break_table = 0xffffff;
+ select_table = 0x3;
+ }
+
+ switch (type) {
+ case 0:
+ halbtc8822b2ant_coex_table(btcoexist, force_exec,
+ 0xffffffff, 0xffffffff, break_table, select_table);
+ break;
+ case 1:
+ halbtc8822b2ant_coex_table(btcoexist, force_exec,
+ 0x55555555, 0x5a5a5a5a, break_table, select_table);
+ break;
+ case 2:
+ halbtc8822b2ant_coex_table(btcoexist, force_exec,
+ 0x5a5a5a5a, 0x5a5a5a5a, break_table, select_table);
+ break;
+ case 3:
+ halbtc8822b2ant_coex_table(btcoexist, force_exec,
+ 0x55555555, 0x5a5a5a5a, break_table, select_table);
+ break;
+ case 4:
+ halbtc8822b2ant_coex_table(btcoexist, force_exec,
+ 0x55555555, 0x5a5a5a5a, break_table, select_table);
+ break;
+ case 5:
+ halbtc8822b2ant_coex_table(btcoexist, force_exec,
+ 0x55555555, 0x55555555, break_table, select_table);
+ break;
+ case 6:
+ halbtc8822b2ant_coex_table(btcoexist, force_exec,
+ 0xa5555555, 0xfafafafa, break_table, select_table);
+ break;
+ case 7:
+ halbtc8822b2ant_coex_table(btcoexist, force_exec,
+ 0xa5555555, 0xaa5a5a5a, break_table, select_table);
+ break;
+ case 8:
+ halbtc8822b2ant_coex_table(btcoexist, force_exec,
+ 0xffff55ff, 0xfafafafa, break_table, select_table);
+ break;
+ case 9:
+ halbtc8822b2ant_coex_table(btcoexist, force_exec,
+ 0x5a5a5a5a, 0xaaaa5aaa, break_table, select_table);
+ break;
+ case 10:
+ halbtc8822b2ant_coex_table(btcoexist, force_exec,
+ 0x55555555, 0x5a5a555a, break_table, select_table);
+ break;
+ case 11:
+ halbtc8822b2ant_coex_table(btcoexist, force_exec,
+ 0xaaffffaa, 0xfafafafa, break_table, select_table);
+ break;
+ case 12:
+ halbtc8822b2ant_coex_table(btcoexist, force_exec,
+ 0xffff55ff, 0x5afa5afa, break_table, select_table);
+ break;
+ case 13:
+ halbtc8822b2ant_coex_table(btcoexist, force_exec,
+ 0xffffffff, 0xfafafafa, break_table, select_table);
+ break;
+ case 14:
+ halbtc8822b2ant_coex_table(btcoexist, force_exec,
+ 0xffff55ff, 0xaaaaaaaa, break_table, select_table);
+ break;
+ default:
+ break;
+ }
+}
+
+static
+void halbtc8822b2ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist,
+ IN boolean enable)
+{
+ u8 h2c_parameter[1] = {0};
+ u32 RTL97F_8822B = 0;
+
+ if (RTL97F_8822B)
+ return;
+
+ if (enable)
+ h2c_parameter[0] |= BIT(0); /* function enable */
+
+ btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter);
+}
+
+static
+void halbtc8822b2ant_ignore_wlan_act(IN struct btc_coexist *btcoexist,
+ IN boolean force_exec, IN boolean enable)
+{
+ coex_dm->cur_ignore_wlan_act = enable;
+
+ if (!force_exec) {
+ if (coex_dm->pre_ignore_wlan_act ==
+ coex_dm->cur_ignore_wlan_act)
+ return;
+ }
+ halbtc8822b2ant_set_fw_ignore_wlan_act(btcoexist, enable);
+
+ coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
+}
+
+static
+void halbtc8822b2ant_set_lps_rpwm(IN struct btc_coexist *btcoexist,
+ IN u8 lps_val, IN u8 rpwm_val)
+{
+ u8 lps = lps_val;
+ u8 rpwm = rpwm_val;
+
+ btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps);
+ btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm);
+}
+
+static
+void halbtc8822b2ant_lps_rpwm(IN struct btc_coexist *btcoexist,
+ IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val)
+{
+ coex_dm->cur_lps = lps_val;
+ coex_dm->cur_rpwm = rpwm_val;
+
+ if (!force_exec) {
+ if ((coex_dm->pre_lps == coex_dm->cur_lps) &&
+ (coex_dm->pre_rpwm == coex_dm->cur_rpwm))
+ return;
+ }
+ halbtc8822b2ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val);
+
+ coex_dm->pre_lps = coex_dm->cur_lps;
+ coex_dm->pre_rpwm = coex_dm->cur_rpwm;
+}
+
+
+static
+void halbtc8822b2ant_ps_tdma_check_for_power_save_state(
+ IN struct btc_coexist *btcoexist, IN boolean new_ps_state)
+{
+ u8 lps_mode = 0x0;
+ u8 h2c_parameter[5] = {0, 0, 0, 0x40, 0};
+ u32 RTL97F_8822B = 0;
+
+ if (RTL97F_8822B)
+ return;
+
+ btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode);
+
+ if (lps_mode) { /* already under LPS state */
+ if (new_ps_state) {
+ /* keep state under LPS, do nothing. */
+ } else {
+ /* will leave LPS state, turn off psTdma first */
+#if 0
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE,
+ 8);
+#endif
+ btcoexist->btc_fill_h2c(btcoexist, 0x60, 5,
+ h2c_parameter);
+ }
+ } else { /* NO PS state */
+ if (new_ps_state) {
+ /* will enter LPS state, turn off psTdma first */
+#if 0
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE,
+ 8);
+#endif
+ btcoexist->btc_fill_h2c(btcoexist, 0x60, 5,
+ h2c_parameter);
+ } else {
+ /* keep state under NO PS state, do nothing. */
+ }
+ }
+}
+
+
+static
+boolean halbtc8822b2ant_power_save_state(IN struct btc_coexist *btcoexist,
+ IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val)
+{
+ boolean low_pwr_disable = FALSE, result = TRUE;
+
+ switch (ps_type) {
+ case BTC_PS_WIFI_NATIVE:
+ coex_sta->force_lps_ctrl = FALSE;
+ /* recover to original 32k low power setting */
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], halbtc8822b2ant_power_save_state == BTC_PS_WIFI_NATIVE\n");
+ BTC_TRACE(trace_buf);
+
+ low_pwr_disable = FALSE;
+ /* btcoexist->btc_set(btcoexist,
+ over to original 32k low power setting */
+
+ btcoexist->btc_set(btcoexist, BTC_SET_ACT_PRE_NORMAL_LPS,
+ NULL);
+ break;
+ case BTC_PS_LPS_ON:
+ coex_sta->force_lps_ctrl = TRUE;
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], halbtc8822b2ant_power_save_state == BTC_PS_LPS_ON\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b2ant_ps_tdma_check_for_power_save_state(
+ btcoexist, TRUE);
+ halbtc8822b2ant_lps_rpwm(btcoexist, NORMAL_EXEC,
+ lps_val, rpwm_val);
+ /* when coex force to enter LPS, do not enter 32k low power. */
+ low_pwr_disable = TRUE;
+ btcoexist->btc_set(btcoexist,
+ BTC_SET_ACT_DISABLE_LOW_POWER,
+ &low_pwr_disable);
+ /* power save must executed before psTdma. */
+ btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS,
+ NULL);
+ break;
+ case BTC_PS_LPS_OFF:
+ coex_sta->force_lps_ctrl = TRUE;
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], halbtc8822b2ant_power_save_state == BTC_PS_LPS_OFF\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b2ant_ps_tdma_check_for_power_save_state(
+ btcoexist, FALSE);
+ result = btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS,
+ NULL);
+ break;
+ default:
+ break;
+ }
+
+ return result;
+}
+
+
+
+
+static
+void halbtc8822b2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist,
+ IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5)
+{
+ u8 h2c_parameter[5] = {0};
+ u8 real_byte1 = byte1, real_byte5 = byte5;
+ boolean ap_enable = FALSE, result = FALSE;
+ struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+ u8 ps_type = BTC_PS_WIFI_NATIVE;
+
+ if (byte5 & BIT(2))
+ coex_sta->is_tdma_btautoslot = TRUE;
+ else
+ coex_sta->is_tdma_btautoslot = FALSE;
+
+ /* release bt-auto slot for auto-slot hang is detected!! */
+ if (coex_sta->is_tdma_btautoslot)
+ if ((coex_sta->is_tdma_btautoslot_hang) ||
+ (bt_link_info->slave_role))
+ byte5 = byte5 & 0xfb;
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
+ &ap_enable);
+
+ if ((ap_enable) && (byte1 & BIT(4) && !(byte1 & BIT(5)))) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], halbtc8822b2ant_set_fw_pstdma == FW for AP mode\n");
+ BTC_TRACE(trace_buf);
+
+ real_byte1 &= ~BIT(4);
+ real_byte1 |= BIT(5);
+
+ real_byte5 |= BIT(5);
+ real_byte5 &= ~BIT(6);
+
+ ps_type = BTC_PS_WIFI_NATIVE;
+ halbtc8822b2ant_power_save_state(btcoexist,
+ ps_type, 0x0, 0x0);
+ } else if (byte1 & BIT(4) && !(byte1 & BIT(5))) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], halbtc8822b2ant_set_fw_pstdma == Force LPS (byte1 = 0x%x)\n", byte1);
+ BTC_TRACE(trace_buf);
+
+#if 0
+ halbtc8822b2ant_power_save_state(
+ btcoexist, BTC_PS_LPS_ON, 0x50,
+ 0x4);
+#endif
+ ps_type = BTC_PS_LPS_OFF;
+ if (!halbtc8822b2ant_power_save_state(btcoexist, ps_type, 0x50, 0x4))
+ result = TRUE;
+
+ } else {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], halbtc8822b2ant_set_fw_pstdma == Native LPS (byte1 = 0x%x)\n", byte1);
+ BTC_TRACE(trace_buf);
+
+ ps_type = BTC_PS_WIFI_NATIVE;
+ halbtc8822b2ant_power_save_state(btcoexist, ps_type, 0x0, 0x0);
+ }
+
+
+ coex_sta->is_set_ps_state_fail = result;
+
+ if (!coex_sta->is_set_ps_state_fail) {
+ h2c_parameter[0] = real_byte1;
+ h2c_parameter[1] = byte2;
+ h2c_parameter[2] = byte3;
+ h2c_parameter[3] = byte4;
+ h2c_parameter[4] = real_byte5;
+
+ coex_dm->ps_tdma_para[0] = real_byte1;
+ coex_dm->ps_tdma_para[1] = byte2;
+ coex_dm->ps_tdma_para[2] = byte3;
+ coex_dm->ps_tdma_para[3] = byte4;
+ coex_dm->ps_tdma_para[4] = real_byte5;
+
+ btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
+
+ } else {
+ coex_sta->cnt_set_ps_state_fail++;
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], halbtc8822b2ant_set_fw_pstdma == Force Leave LPS Fail (cnt = %d)\n",
+ coex_sta->cnt_set_ps_state_fail);
+ BTC_TRACE(trace_buf);
+ }
+
+ if (ps_type == BTC_PS_WIFI_NATIVE)
+ btcoexist->btc_set(btcoexist, BTC_SET_ACT_POST_NORMAL_LPS, NULL);
+}
+
+
+static
+void halbtc8822b2ant_ps_tdma(IN struct btc_coexist *btcoexist,
+ IN boolean force_exec, IN boolean turn_on, IN u8 type)
+{
+ static u8 psTdmaByte4Modify = 0x0, pre_psTdmaByte4Modify = 0x0;
+ struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+ coex_dm->cur_ps_tdma_on = turn_on;
+ coex_dm->cur_ps_tdma = type;
+
+ /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */
+ if (bt_link_info->slave_role)
+ psTdmaByte4Modify = 0x1;
+ else
+ psTdmaByte4Modify = 0x0;
+
+ if (pre_psTdmaByte4Modify != psTdmaByte4Modify) {
+ force_exec = TRUE;
+ pre_psTdmaByte4Modify = psTdmaByte4Modify;
+ }
+
+ if (!force_exec) {
+ if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) &&
+ (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Skip TDMA because no change TDMA(%s, %d)\n",
+ (coex_dm->cur_ps_tdma_on ? "on" : "off"),
+ coex_dm->cur_ps_tdma);
+ BTC_TRACE(trace_buf);
+ return;
+ }
+ }
+
+ if (coex_dm->cur_ps_tdma_on) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ********** TDMA(on, %d) **********\n",
+ coex_dm->cur_ps_tdma);
+ BTC_TRACE(trace_buf);
+
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8,
+ 0x1); /* enable TBTT nterrupt */
+ } else {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ********** TDMA(off, %d) **********\n",
+ coex_dm->cur_ps_tdma);
+ BTC_TRACE(trace_buf);
+ }
+
+
+ if (turn_on) {
+ switch (type) {
+ case 1:
+ halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61,
+ 0x10, 0x03, 0x91,
+ 0x54 | psTdmaByte4Modify);
+ break;
+ case 2:
+ default:
+ halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61,
+ 0x35, 0x03, 0x11,
+ 0x11 | psTdmaByte4Modify);
+ break;
+ case 3:
+ halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61,
+ 0x3a, 0x3, 0x91,
+ 0x10 | psTdmaByte4Modify);
+ break;
+ case 4:
+ halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61,
+ 0x21, 0x3, 0x91,
+ 0x10 | psTdmaByte4Modify);
+ break;
+ case 5:
+ halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61,
+ 0x25, 0x3, 0x91,
+ 0x10 | psTdmaByte4Modify);
+ break;
+ case 6:
+ halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61,
+ 0x10, 0x3, 0x91,
+ 0x10 | psTdmaByte4Modify);
+ break;
+ case 7:
+ halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61,
+ 0x20, 0x3, 0x91,
+ 0x10 | psTdmaByte4Modify);
+ break;
+ case 8:
+ halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61,
+ 0x15, 0x03, 0x11,
+ 0x11);
+ break;
+ case 10:
+ halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61,
+ 0x30, 0x03, 0x11,
+ 0x10);
+ break;
+ case 11:
+ halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61,
+ 0x35, 0x03, 0x11,
+ 0x10 | psTdmaByte4Modify);
+ break;
+ case 12:
+ halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61,
+ 0x35, 0x03, 0x11, 0x11);
+ break;
+ case 13:
+ halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61,
+ 0x1c, 0x03, 0x11,
+ 0x10 | psTdmaByte4Modify);
+ break;
+ case 14:
+ halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61,
+ 0x20, 0x03, 0x11,
+ 0x11);
+ break;
+ case 15:
+ halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61,
+ 0x10, 0x03, 0x11,
+ 0x14);
+ break;
+ case 16:
+ halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61,
+ 0x10, 0x03, 0x11,
+ 0x15);
+ break;
+ case 21:
+ halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61,
+ 0x30, 0x03, 0x11,
+ 0x10);
+ break;
+ case 22:
+ halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61,
+ 0x25, 0x03, 0x11,
+ 0x10);
+ break;
+ case 23:
+ halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61,
+ 0x10, 0x03, 0x11,
+ 0x10);
+ break;
+ case 25:
+ halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x51,
+ 0x3a, 0x3, 0x11,
+ 0x50);
+ break;
+ case 51:
+ halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61,
+ 0x10, 0x03, 0x91,
+ 0x10 | psTdmaByte4Modify);
+ break;
+ case 101:
+ halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61,
+ 0x25, 0x03, 0x11,
+ 0x11 | psTdmaByte4Modify);
+ break;
+ case 102:
+ halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61,
+ 0x35, 0x03, 0x11,
+ 0x11 | psTdmaByte4Modify);
+ break;
+ case 103:
+ halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x51,
+ 0x3a, 0x3, 0x10,
+ 0x50 | psTdmaByte4Modify);
+ break;
+ case 104:
+ halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x51,
+ 0x21, 0x3, 0x10,
+ 0x50 | psTdmaByte4Modify);
+ break;
+ case 105:
+ halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x51,
+ 0x30, 0x3, 0x10,
+ 0x50 | psTdmaByte4Modify);
+ break;
+ case 106:
+ halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x51,
+ 0x10, 0x3, 0x10,
+ 0x50 | psTdmaByte4Modify);
+ break;
+ case 107:
+ halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x51,
+ 0x10, 0x7, 0x10,
+ 0x54 | psTdmaByte4Modify);
+ break;
+ case 108:
+ halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x51,
+ 0x30, 0x3, 0x10,
+ 0x50 | psTdmaByte4Modify);
+ break;
+ case 109:
+ halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x51,
+ 0x10, 0x03, 0x10,
+ 0x54 | psTdmaByte4Modify);
+ break;
+ case 110:
+ halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x55,
+ 0x30, 0x03, 0x10,
+ 0x50 | psTdmaByte4Modify);
+ break;
+ case 111:
+ halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61,
+ 0x25, 0x03, 0x11,
+ 0x11 | psTdmaByte4Modify);
+ break;
+ case 113:
+ halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61,
+ 0x48, 0x03, 0x11,
+ 0x10);
+ break;
+ case 119:
+ halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x61,
+ 0x10, 0x03, 0x11,
+ 0x14 | psTdmaByte4Modify);
+ break;
+ case 151:
+ halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x51,
+ 0x10, 0x03, 0x10,
+ 0x50 | psTdmaByte4Modify);
+ break;
+ }
+ } else {
+ /* disable PS tdma */
+ switch (type) {
+
+ case 0:
+ halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x0,
+ 0x0, 0x0, 0x40, 0x0);
+ break;
+ default:
+ halbtc8822b2ant_set_fw_pstdma(btcoexist, 0x0,
+ 0x0, 0x0, 0x40, 0x0);
+ break;
+ }
+ }
+
+ if (!coex_sta->is_set_ps_state_fail) {
+ /* update pre state */
+ coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on;
+ coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
+ }
+}
+
+/*anttenna control by bb mac bt antdiv pta to write 0x4c 0xcb4,0xcbd*/
+static
+void halbtc8822b2ant_set_ext_ant_switch(IN struct btc_coexist *btcoexist,
+ IN boolean force_exec, IN u8 ctrl_type, IN u8 pos_type)
+{
+
+ boolean switch_polatiry_inverse = FALSE;
+ u8 regval_0xcbc = 0, regval_0x64;
+ u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0;
+
+ if (!rfe_type->ext_ant_switch_exist)
+ return;
+
+ coex_dm->cur_ext_ant_switch_status = (ctrl_type << 8) + pos_type;
+
+ if (!force_exec) {
+ if (coex_dm->pre_ext_ant_switch_status ==
+ coex_dm->cur_ext_ant_switch_status)
+ return;
+ }
+ coex_dm->pre_ext_ant_switch_status = coex_dm->cur_ext_ant_switch_status;
+
+
+ /* Ext switch buffer mux */
+ btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff);
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, 0x3, 0x0);
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, 0x8, 0x0);
+
+ switch (ctrl_type) {
+ default:
+ case BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW:
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e,
+ 0x80, 0x0); /* 0x4c[23] = 0 */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f,
+ 0x01, 0x1); /* 0x4c[24] = 1 */
+ /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as conctrol pin */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4,
+ 0xff, 0x77);
+
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd,
+ 0x03, 0x1);
+
+ break;
+ case BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_PTA:
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e,
+ 0x80, 0x0); /* 0x4c[23] = 0 */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f,
+ 0x01, 0x1); /* 0x4c[24] = 1 */
+ /* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as conctrol pin */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4,
+ 0xff, 0x66);
+
+ /* 0xcb4[29:28] = 2b'10 for no switch_polatiry_inverse,
+ * DPDT_SEL_N =1, DPDT_SEL_P =0 @ GNT_BT=1
+ */
+ regval_0xcbc = (!switch_polatiry_inverse ? 0x2 : 0x1);
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbc,
+ 0x03, regval_0xcbc);
+
+ break;
+ case BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV:
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e,
+ 0x80, 0x0); /* 0x4c[23] = 0 */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f,
+ 0x01, 0x1);/* 0x4c[24] = 1 */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, 0xff, 0x88);
+ break;
+ case BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_MAC:
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e,
+ 0x80, 0x1); /* 0x4c[23] = 1 */
+
+ /* 0x64[0] = 1b'0 for no switch_polatiry_inverse,
+ * DPDT_SEL_N =1, DPDT_SEL_P =0
+ */
+ regval_0x64 = (!switch_polatiry_inverse ? 0x0 : 0x1);
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x64, 0x1,
+ regval_0x64);
+ break;
+ case BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_BT:
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e,
+ 0x80, 0x0); /* 0x4c[23] = 0 */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f,
+ 0x01, 0x0); /* 0x4c[24] = 0 */
+
+ /* no setup required, because antenna switch control value by
+ * BT vendor 0x1c[1:0]
+ */
+ break;
+ }
+
+ /* PAPE, LNA_ON control by BT while WLAN off for current leakage issue*/
+ if (ctrl_type == BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_BT) {
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20,
+ 0x0); /* PAPE 0x64[29] = 0 */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x10,
+ 0x0); /* LNA_ON 0x64[28] = 0 */
+ } else {
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20,
+ 0x1); /* PAPE 0x64[29] = 1 */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x10,
+ 0x1); /* LNA_ON 0x64[28] = 1 */
+ }
+
+#if BT_8822B_2ANT_COEX_DBG
+
+ u32tmp1 = btcoexist->btc_read_4byte(btcoexist, 0xcbc);
+ u32tmp2 = btcoexist->btc_read_4byte(btcoexist, 0x4c);
+ u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0x64) & 0xff;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], (After Ext Ant switch setup) 0xcbc = 0x%08x, 0x4c = 0x%08x, 0x64= 0x%02x\n",
+ u32tmp1, u32tmp2, u32tmp3);
+ BTC_TRACE(trace_buf);
+#endif
+
+
+}
+
+/* rf4 type by efuse, and for ant at main aux inverse use,
+ * because is 2x2, and control types are the same, does not need
+ */
+static
+void halbtc8822b2ant_set_rfe_type(IN struct btc_coexist *btcoexist)
+{
+
+ struct btc_board_info *board_info = &btcoexist->board_info;
+
+
+ rfe_type->ext_band_switch_exist = FALSE;
+ rfe_type->ext_band_switch_type =
+ BT_8822B_2ANT_EXT_BAND_SWITCH_USE_SPDT; /* SPDT; */
+ rfe_type->ext_band_switch_ctrl_polarity = 0;
+ /* Ext switch buffer mux */
+ btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff);
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, 0x3, 0x0);
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, 0x8, 0x0);
+
+ if (rfe_type->ext_band_switch_exist) {
+
+ /* band switch use RFE_ctrl1 (pin name: PAPE_A) and
+ * RFE_ctrl3 (pin name: LNAON_A)
+ */
+
+ /* set RFE_ctrl1 as software control */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb0, 0xf0, 0x7);
+
+ /* set RFE_ctrl3 as software control */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb1, 0xf0, 0x7);
+
+ }
+
+
+ /* the following setup should be got from Efuse in the future */
+ rfe_type->rfe_module_type = board_info->rfe_type;
+ rfe_type->ext_ant_switch_ctrl_polarity = 0;
+ rfe_type->ext_ant_switch_exist = TRUE;
+ rfe_type->ext_ant_switch_type = BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT;
+
+#if 0
+ switch (rfe_type->rfe_module_type) {
+ case 0:
+ default:
+ rfe_type->ext_ant_switch_exist = TRUE;
+ rfe_type->ext_ant_switch_type = BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT;
+ break;
+ case 1:
+ rfe_type->ext_ant_switch_exist = TRUE;
+ rfe_type->ext_ant_switch_type = BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT;
+ break;
+ case 2:
+ rfe_type->ext_ant_switch_exist = TRUE;
+ rfe_type->ext_ant_switch_type = BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT;
+ break;
+ case 3:
+ rfe_type->ext_ant_switch_exist = TRUE;
+ rfe_type->ext_ant_switch_type = BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT;
+ break;
+ case 4:
+ rfe_type->ext_ant_switch_exist = TRUE;
+ rfe_type->ext_ant_switch_type =
+ BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT;
+ break;
+ case 5:
+ rfe_type->ext_ant_switch_exist = TRUE;
+ rfe_type->ext_ant_switch_type = BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT;
+ break;
+ case 6:
+ rfe_type->ext_ant_switch_exist = TRUE;
+ rfe_type->ext_ant_switch_type = BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT;
+ break;
+ case 7:
+ rfe_type->ext_ant_switch_exist = TRUE;
+ rfe_type->ext_ant_switch_type = BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT;
+ break;
+ }
+#endif
+
+#if 0
+
+ if (rfe_type->wlg_Locate_at_btg)
+ halbtc8822b2ant_set_int_block(btcoexist, FORCE_EXEC,
+ BT_8822B_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_BTG);
+ else
+ halbtc8822b2ant_set_int_block(btcoexist, FORCE_EXEC,
+ BT_8822B_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_WLAG);
+#endif
+
+}
+
+/* set gnt_wl gnt_bt control by sw high low, or hwpta while in
+ * power on, ini, wlan off, wlan only, wl2g non-currrent, wl2g current, wl5g
+ */
+static
+void halbtc8822b2ant_set_ant_path(IN struct btc_coexist *btcoexist,
+ IN u8 ant_pos_type, IN boolean force_exec,
+ IN u8 phase)
+{
+
+ u8 u8tmp = 0;
+ u32 u32tmp1 = 0;
+ u32 u32tmp2 = 0, u32tmp3 = 0;
+
+ u32tmp1 = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist,
+ 0x38);
+
+ /* To avoid indirect access fail */
+ if (((u32tmp1 & 0xf000) >> 12) != ((u32tmp1 & 0x0f00) >> 8)) {
+ force_exec = TRUE;
+ coex_sta->gnt_error_cnt++;
+ }
+
+ coex_sta->is_2g_freerun = ((phase == BT_8822B_2ANT_PHASE_2G_FREERUN) ? TRUE : FALSE);
+
+ coex_dm->cur_ant_pos_type = (ant_pos_type << 8) + phase;
+
+ if (!force_exec) {
+ if (coex_dm->cur_ant_pos_type == coex_dm->pre_ant_pos_type)
+ return;
+ }
+
+ coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type;
+
+#if BT_8822B_2ANT_COEX_DBG
+ u32tmp1 = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist,
+ 0x38);
+ u32tmp2 = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist,
+ 0x54);
+ u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73);
+
+ u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4);
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], (Before Ant Setup) 0xcb4 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n",
+ u32tmp3, u8tmp, u32tmp1, u32tmp2);
+ BTC_TRACE(trace_buf);
+#endif
+
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, 0xff, 0x77);
+
+ switch (phase) {
+ case BT_8822B_2ANT_PHASE_COEX_POWERON:
+
+ /* set Path control owner to WL at initial step */
+ halbtc8822b2ant_ltecoex_pathcontrol_owner(btcoexist,
+ BT_8822B_2ANT_PCO_BTSIDE);
+
+ /* set GNT_BT to SW high */
+ halbtc8822b2ant_ltecoex_set_gnt_bt(btcoexist,
+ BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
+ BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
+ BT_8822B_2ANT_SIG_STA_SET_TO_HIGH);
+ /* Set GNT_WL to SW high */
+ halbtc8822b2ant_ltecoex_set_gnt_wl(btcoexist,
+ BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
+ BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
+ BT_8822B_2ANT_SIG_STA_SET_TO_HIGH);
+
+ coex_sta->run_time_state = FALSE;
+
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x03, 2);
+
+ break;
+ case BT_8822B_2ANT_PHASE_COEX_INIT:
+ /* Ext switch buffer mux */
+ btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff);
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x1991, 0x3, 0x0);
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbe, 0x8, 0x0);
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e,
+ 0x80, 0x0); /* 0x4c[23] = 0 */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f,
+ 0x01, 0x1); /* 0x4c[24] = 1 */
+
+ /* Disable LTE Coex Function in WiFi side
+ * (this should be on if LTE coex is required)
+ */
+ halbtc8822b2ant_ltecoex_enable(btcoexist, 0x0);
+
+ /* GNT_WL_LTE always = 1
+ * (this should be config if LTE coex is required)
+ */
+ halbtc8822b2ant_ltecoex_set_coex_table(
+ btcoexist,
+ BT_8822B_2ANT_CTT_WL_VS_LTE,
+ 0xffff);
+
+ /* GNT_BT_LTE always = 1
+ * (this should be config if LTE coex is required)
+ */
+ halbtc8822b2ant_ltecoex_set_coex_table(
+ btcoexist,
+ BT_8822B_2ANT_CTT_BT_VS_LTE,
+ 0xffff);
+
+ /* set Path control owner to WL at initial step */
+ halbtc8822b2ant_ltecoex_pathcontrol_owner(
+ btcoexist,
+ BT_8822B_2ANT_PCO_WLSIDE);
+
+ /* set GNT_BT to SW high */
+ halbtc8822b2ant_ltecoex_set_gnt_bt(btcoexist,
+ BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
+ BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
+ BT_8822B_2ANT_SIG_STA_SET_TO_HIGH);
+ /* Set GNT_WL to SW high */
+ halbtc8822b2ant_ltecoex_set_gnt_wl(btcoexist,
+ BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
+ BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
+ BT_8822B_2ANT_SIG_STA_SET_TO_HIGH);
+
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x03, 2);
+
+ coex_sta->run_time_state = FALSE;
+
+ break;
+ case BT_8822B_2ANT_PHASE_WLANONLY_INIT:
+ /* Disable LTE Coex Function in WiFi side
+ * (this should be on if LTE coex is required)
+ */
+ halbtc8822b2ant_ltecoex_enable(btcoexist, 0x0);
+
+ /* GNT_WL_LTE always = 1
+ * (this should be config if LTE coex is required)
+ */
+ halbtc8822b2ant_ltecoex_set_coex_table(
+ btcoexist,
+ BT_8822B_2ANT_CTT_WL_VS_LTE,
+ 0xffff);
+
+ /* GNT_BT_LTE always = 1
+ * (this should be config if LTE coex is required)
+ */
+ halbtc8822b2ant_ltecoex_set_coex_table(
+ btcoexist,
+ BT_8822B_2ANT_CTT_BT_VS_LTE,
+ 0xffff);
+
+ /* set Path control owner to WL at initial step */
+ halbtc8822b2ant_ltecoex_pathcontrol_owner(
+ btcoexist,
+ BT_8822B_2ANT_PCO_WLSIDE);
+
+ /* set GNT_BT to SW Low */
+ halbtc8822b2ant_ltecoex_set_gnt_bt(btcoexist,
+ BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
+ BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
+ BT_8822B_2ANT_SIG_STA_SET_TO_LOW);
+ /* Set GNT_WL to SW high */
+ halbtc8822b2ant_ltecoex_set_gnt_wl(btcoexist,
+ BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
+ BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
+ BT_8822B_2ANT_SIG_STA_SET_TO_HIGH);
+
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x03, 2);
+
+ coex_sta->run_time_state = FALSE;
+
+ break;
+ case BT_8822B_2ANT_PHASE_WLAN_OFF:
+ /* Disable LTE Coex Function in WiFi side */
+ halbtc8822b2ant_ltecoex_enable(btcoexist, 0x0);
+
+ /* set Path control owner to BT */
+ halbtc8822b2ant_ltecoex_pathcontrol_owner(
+ btcoexist,
+ BT_8822B_2ANT_PCO_BTSIDE);
+
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x03, 1);
+
+ coex_sta->run_time_state = FALSE;
+ break;
+ case BT_8822B_2ANT_PHASE_2G_RUNTIME:
+ case BT_8822B_2ANT_PHASE_2G_FREERUN:
+
+ /* set Path control owner to WL at runtime step */
+ halbtc8822b2ant_ltecoex_pathcontrol_owner(
+ btcoexist,
+ BT_8822B_2ANT_PCO_WLSIDE);
+
+ if (phase ==
+ BT_8822B_2ANT_PHASE_2G_FREERUN) {
+ /* set GNT_BT to SW Hi */
+ halbtc8822b2ant_ltecoex_set_gnt_bt(btcoexist,
+ BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
+ BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
+ BT_8822B_2ANT_SIG_STA_SET_TO_HIGH);
+ /* Set GNT_WL to SW Hi */
+ halbtc8822b2ant_ltecoex_set_gnt_wl(btcoexist,
+ BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
+ BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
+ BT_8822B_2ANT_SIG_STA_SET_TO_HIGH);
+ } else {
+ /* set GNT_BT to PTA */
+ halbtc8822b2ant_ltecoex_set_gnt_bt(
+ btcoexist,
+ BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
+ BT_8822B_2ANT_GNT_TYPE_CTRL_BY_PTA,
+ BT_8822B_2ANT_SIG_STA_SET_BY_HW);
+
+ /* Set GNT_WL to PTA */
+ halbtc8822b2ant_ltecoex_set_gnt_wl(
+ btcoexist,
+ BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
+ BT_8822B_2ANT_GNT_TYPE_CTRL_BY_PTA,
+ BT_8822B_2ANT_SIG_STA_SET_BY_HW);
+ }
+
+ coex_sta->run_time_state = TRUE;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ************* under2g 0xcbd setting =2 *************\n");
+ BTC_TRACE(trace_buf);
+
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x03, 2);
+ break;
+
+ case BT_8822B_2ANT_PHASE_5G_RUNTIME:
+
+ /* set Path control owner to WL at runtime step */
+ halbtc8822b2ant_ltecoex_pathcontrol_owner(
+ btcoexist,
+ BT_8822B_2ANT_PCO_WLSIDE);
+
+ /* set GNT_BT to SW Hi */
+ halbtc8822b2ant_ltecoex_set_gnt_bt(btcoexist,
+ BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
+ BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
+ BT_8822B_2ANT_SIG_STA_SET_TO_HIGH);
+ /* Set GNT_WL to SW Hi */
+ halbtc8822b2ant_ltecoex_set_gnt_wl(btcoexist,
+ BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
+ BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
+ BT_8822B_2ANT_SIG_STA_SET_TO_HIGH);
+
+ coex_sta->run_time_state = TRUE;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ************* under5g 0xcbd setting =1 *************\n");
+ BTC_TRACE(trace_buf);
+
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x03, 1);
+
+ break;
+ case BT_8822B_2ANT_PHASE_BTMPMODE:
+ /* Disable LTE Coex Function in WiFi side */
+ halbtc8822b2ant_ltecoex_enable(btcoexist, 0x0);
+
+ /* set Path control owner to WL */
+ halbtc8822b2ant_ltecoex_pathcontrol_owner(
+ btcoexist,
+ BT_8822B_2ANT_PCO_WLSIDE);
+
+ /* set GNT_BT to SW Hi */
+ halbtc8822b2ant_ltecoex_set_gnt_bt(btcoexist,
+ BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
+ BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
+ BT_8822B_2ANT_SIG_STA_SET_TO_HIGH);
+
+ /* Set GNT_WL to SW Lo */
+ halbtc8822b2ant_ltecoex_set_gnt_wl(btcoexist,
+ BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
+ BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
+ BT_8822B_2ANT_SIG_STA_SET_TO_LOW);
+
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcbd, 0x03, 1);
+
+ coex_sta->run_time_state = FALSE;
+ break;
+ }
+#if BT_8822B_2ANT_COEX_DBG
+ u32tmp1 = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
+ u32tmp2 = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
+ u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4);
+ u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73);
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], (After Ant-Setup phase---%d) 0xcb4 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n",
+ phase, u32tmp3, u8tmp, u32tmp1, u32tmp2);
+
+ BTC_TRACE(trace_buf);
+#endif
+
+}
+
+
+static
+u8 halbtc8822b2ant_action_algorithm(IN struct btc_coexist *btcoexist)
+{
+ struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+ boolean bt_hs_on = FALSE;
+ u8 algorithm = BT_8822B_2ANT_COEX_ALGO_UNDEFINED;
+ u8 num_of_diff_profile = 0;
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
+
+ if (!bt_link_info->bt_link_exist) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], No BT link exists!!!\n");
+ BTC_TRACE(trace_buf);
+ return algorithm;
+ }
+
+ if (bt_link_info->sco_exist)
+ num_of_diff_profile++;
+ if (bt_link_info->hid_exist)
+ num_of_diff_profile++;
+ if (bt_link_info->pan_exist)
+ num_of_diff_profile++;
+ if (bt_link_info->a2dp_exist)
+ num_of_diff_profile++;
+
+ if (num_of_diff_profile == 0) {
+
+ if (bt_link_info->acl_busy) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], No-Profile busy\n");
+ BTC_TRACE(trace_buf);
+ algorithm = BT_8822B_2ANT_COEX_ALGO_NOPROFILEBUSY;
+ }
+ } else if ((bt_link_info->a2dp_exist) && (coex_sta->is_bt_a2dp_sink)) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], A2DP Sink\n");
+ BTC_TRACE(trace_buf);
+ algorithm = BT_8822B_2ANT_COEX_ALGO_A2DPSINK;
+ } else if (num_of_diff_profile == 1) {
+ if (bt_link_info->sco_exist) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], SCO only\n");
+ BTC_TRACE(trace_buf);
+ algorithm = BT_8822B_2ANT_COEX_ALGO_SCO;
+ } else {
+ if (bt_link_info->hid_exist) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], HID only\n");
+ BTC_TRACE(trace_buf);
+ algorithm = BT_8822B_2ANT_COEX_ALGO_HID;
+ } else if (bt_link_info->a2dp_exist) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], A2DP only\n");
+ BTC_TRACE(trace_buf);
+ algorithm = BT_8822B_2ANT_COEX_ALGO_A2DP;
+ } else if (bt_link_info->pan_exist) {
+ if (bt_hs_on) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], PAN(HS) only\n");
+ BTC_TRACE(trace_buf);
+ algorithm =
+ BT_8822B_2ANT_COEX_ALGO_PANHS;
+ } else {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], PAN(EDR) only\n");
+ BTC_TRACE(trace_buf);
+ algorithm =
+ BT_8822B_2ANT_COEX_ALGO_PANEDR;
+ }
+ }
+ }
+ } else if (num_of_diff_profile == 2) {
+ if (bt_link_info->sco_exist) {
+ if (bt_link_info->hid_exist) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], SCO + HID\n");
+ BTC_TRACE(trace_buf);
+ algorithm = BT_8822B_2ANT_COEX_ALGO_SCO;
+ } else if (bt_link_info->a2dp_exist) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], SCO + A2DP ==> A2DP\n");
+ BTC_TRACE(trace_buf);
+ algorithm = BT_8822B_2ANT_COEX_ALGO_A2DP;
+ } else if (bt_link_info->pan_exist) {
+ if (bt_hs_on) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], SCO + PAN(HS)\n");
+ BTC_TRACE(trace_buf);
+ algorithm = BT_8822B_2ANT_COEX_ALGO_SCO;
+ } else {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], SCO + PAN(EDR)\n");
+ BTC_TRACE(trace_buf);
+ algorithm =
+ BT_8822B_2ANT_COEX_ALGO_PANEDR;
+ }
+ }
+ } else {
+ if (bt_link_info->hid_exist &&
+ bt_link_info->a2dp_exist) {
+ {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], HID + A2DP\n");
+ BTC_TRACE(trace_buf);
+ algorithm =
+ BT_8822B_2ANT_COEX_ALGO_HID_A2DP;
+ }
+ } else if (bt_link_info->hid_exist &&
+ bt_link_info->pan_exist) {
+ if (bt_hs_on) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], HID + PAN(HS)\n");
+ BTC_TRACE(trace_buf);
+ algorithm = BT_8822B_2ANT_COEX_ALGO_HID;
+ } else {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], HID + PAN(EDR)\n");
+ BTC_TRACE(trace_buf);
+ algorithm =
+ BT_8822B_2ANT_COEX_ALGO_PANEDR_HID;
+ }
+ } else if (bt_link_info->pan_exist &&
+ bt_link_info->a2dp_exist) {
+ if (bt_hs_on) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], A2DP + PAN(HS)\n");
+ BTC_TRACE(trace_buf);
+ algorithm =
+ BT_8822B_2ANT_COEX_ALGO_A2DP_PANHS;
+ } else {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], A2DP + PAN(EDR)\n");
+ BTC_TRACE(trace_buf);
+ algorithm =
+ BT_8822B_2ANT_COEX_ALGO_PANEDR_A2DP;
+ }
+ }
+ }
+ } else if (num_of_diff_profile == 3) {
+ if (bt_link_info->sco_exist) {
+ if (bt_link_info->hid_exist &&
+ bt_link_info->a2dp_exist) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], SCO + HID + A2DP ==> HID + A2DP\n");
+ BTC_TRACE(trace_buf);
+ algorithm = BT_8822B_2ANT_COEX_ALGO_HID_A2DP;
+ } else if (bt_link_info->hid_exist &&
+ bt_link_info->pan_exist) {
+ if (bt_hs_on) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], SCO + HID + PAN(HS)\n");
+ BTC_TRACE(trace_buf);
+ algorithm =
+ BT_8822B_2ANT_COEX_ALGO_PANEDR_HID;
+ } else {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], SCO + HID + PAN(EDR)\n");
+ BTC_TRACE(trace_buf);
+ algorithm =
+ BT_8822B_2ANT_COEX_ALGO_PANEDR_HID;
+ }
+ } else if (bt_link_info->pan_exist &&
+ bt_link_info->a2dp_exist) {
+ if (bt_hs_on) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], SCO + A2DP + PAN(HS)\n");
+ BTC_TRACE(trace_buf);
+ algorithm =
+ BT_8822B_2ANT_COEX_ALGO_PANEDR_A2DP;
+ } else {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n");
+ BTC_TRACE(trace_buf);
+ algorithm =
+ BT_8822B_2ANT_COEX_ALGO_PANEDR_A2DP;
+ }
+ }
+ } else {
+ if (bt_link_info->hid_exist &&
+ bt_link_info->pan_exist &&
+ bt_link_info->a2dp_exist) {
+ if (bt_hs_on) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], HID + A2DP + PAN(HS)\n");
+ BTC_TRACE(trace_buf);
+ algorithm =
+ BT_8822B_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
+ } else {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], HID + A2DP + PAN(EDR)\n");
+ BTC_TRACE(trace_buf);
+ algorithm =
+ BT_8822B_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
+ }
+ }
+ }
+ } else if (num_of_diff_profile >= 3) {
+ if (bt_link_info->sco_exist) {
+ if (bt_link_info->hid_exist &&
+ bt_link_info->pan_exist &&
+ bt_link_info->a2dp_exist) {
+ if (bt_hs_on) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n");
+ BTC_TRACE(trace_buf);
+ algorithm =
+ BT_8822B_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
+ } else {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n");
+ BTC_TRACE(trace_buf);
+ algorithm =
+ BT_8822B_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
+ }
+ }
+ }
+ }
+
+ return algorithm;
+}
+
+static
+void halbtc8822b2ant_action_wifi_freerun(IN struct btc_coexist *btcoexist)
+{
+ boolean wifi_busy = FALSE;
+ static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+ u8 bt_rssi_state;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ************* freerunXXXX*************\n");
+ BTC_TRACE(trace_buf);
+
+ bt_rssi_state = halbtc8822b2ant_bt_rssi_state(btcoexist,
+ &pre_bt_rssi_state, 2, 55, 0);
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+ if (!wifi_busy)
+ wifi_busy = coex_sta->gl_wifi_busy;
+
+ halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
+
+ halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC,
+ BT_8822B_2ANT_PHASE_2G_FREERUN);
+
+ halbtc8822b2ant_update_wifi_channel_info(btcoexist, BTC_MEDIA_CONNECT);
+
+ halbtc8822b2ant_post_state_to_bt(btcoexist, BT_8822B_2ANT_SCOREBOARD_BTCQDDR, TRUE);
+
+ /*avoid tdma off to write 0xc5b ,0xe5b */
+ if (wifi_busy) {
+ halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, FORCE_EXEC, TRUE);
+ halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, TRUE);
+
+ if (BTC_RSSI_HIGH(bt_rssi_state))
+ halbtc8822b2ant_adjust_bt_tx_power(btcoexist, FORCE_EXEC, 0xeb);
+ else
+ halbtc8822b2ant_adjust_bt_tx_power(btcoexist, FORCE_EXEC, 0xf3);
+
+ halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd4);
+ } else {
+ halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, FORCE_EXEC, TRUE);
+ halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, TRUE);
+ halbtc8822b2ant_adjust_bt_tx_power(btcoexist, FORCE_EXEC, 0x0);
+ halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8);
+ }
+}
+
+
+
+static
+void halbtc8822b2ant_action_coex_all_off(IN struct btc_coexist *btcoexist)
+{
+
+ halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8);
+ halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+ halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+
+ halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
+}
+
+static
+void halbtc8822b2ant_action_bt_whql_test(IN struct btc_coexist *btcoexist)
+{
+ halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8);
+ halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+ halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+
+ halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
+}
+
+static
+void halbtc8822b2ant_action_bt_hs(IN struct btc_coexist *btcoexist)
+{
+ static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+ static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+ u8 wifi_rssi_state, bt_rssi_state;
+
+ static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+ static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
+ u8 wifi_rssi_state2, bt_rssi_state2;
+ boolean wifi_busy = FALSE, wifi_turbo = FALSE;
+
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+ btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
+ &coex_sta->scan_ap_num);
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n",
+ coex_sta->scan_ap_num, coex_sta->wl_noisy_level);
+ BTC_TRACE(trace_buf);
+
+#if 1
+ if ((wifi_busy) && (coex_sta->wl_noisy_level == 0))
+ wifi_turbo = TRUE;
+#endif
+
+
+ wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+ &prewifi_rssi_state, 2,
+ coex_sta->wifi_coex_thres, 0);
+
+ wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+ &prewifi_rssi_state2, 2,
+ coex_sta->wifi_coex_thres2, 0);
+
+ bt_rssi_state = halbtc8822b2ant_bt_rssi_state(btcoexist,
+ &pre_bt_rssi_state, 2,
+ coex_sta->bt_coex_thres, 0);
+
+ bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(btcoexist,
+ &pre_bt_rssi_state2, 2,
+ coex_sta->bt_coex_thres2, 0);
+
+ if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+ BTC_RSSI_HIGH(bt_rssi_state)) {
+
+ halbtc8822b2ant_action_wifi_freerun(btcoexist);
+ } else {
+
+ halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8);
+ halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+ halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+
+ coex_dm->is_switch_to_1dot5_ant = TRUE;
+
+ halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
+ }
+
+}
+
+static
+void halbtc8822b2ant_action_bt_relink(IN struct btc_coexist *btcoexist)
+{
+ struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+ if (((!coex_sta->is_bt_multi_link) && (!bt_link_info->pan_exist)) ||
+ ((bt_link_info->a2dp_exist) && (bt_link_info->hid_exist))) {
+
+ halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8);
+ halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+ halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+
+ halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
+ }
+}
+
+static
+void halbtc8822b2ant_action_bt_idle(IN struct btc_coexist *btcoexist)
+{
+
+ boolean wifi_busy = FALSE;
+
+ halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8);
+ halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+ halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+ if (!wifi_busy) {
+ halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 14);
+ } else { /* if wl busy */
+ if ((coex_sta->bt_ble_scan_type & 0x2) &&
+ (BT_8822B_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+ coex_dm->bt_status)) {/* for A2DP + RCU off (initiator scan on) */
+ halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 14);
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 12);
+ } else {
+ halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 12);
+ }
+ }
+}
+
+static
+void halbtc8822b2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist)
+{
+
+ boolean wifi_connected = FALSE;
+ boolean wifi_scan = FALSE, wifi_link = FALSE, wifi_roam = FALSE;
+ boolean wifi_busy = FALSE;
+ struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected);
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan);
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link);
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam);
+
+ halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8);
+ halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+ halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+
+ if ((coex_sta->bt_create_connection) && ((wifi_link) || (wifi_roam)
+ || (wifi_scan) || (wifi_busy) || (coex_sta->wifi_is_high_pri_task))) {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Wifi link/roam/Scan/busy/hi-pri-task + BT Inq/Page!!\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
+
+ if ((bt_link_info->a2dp_exist) && (!bt_link_info->pan_exist))
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 15);
+ else
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 11);
+ } else if ((!wifi_connected) && (!wifi_scan)) {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Wifi no-link + no-scan + BT Inq/Page!!\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
+
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
+ } else if (bt_link_info->pan_exist) {
+ halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
+
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 22);
+
+
+ } else if (bt_link_info->a2dp_exist) {
+
+ halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 10);
+
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 8);
+
+ } else {
+
+ halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
+
+ if ((wifi_link) || (wifi_roam) || (wifi_scan) || (wifi_busy)
+ || (coex_sta->wifi_is_high_pri_task))
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 21);
+ else
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 23);
+ }
+
+}
+
+
+/* SCO only or SCO+PAN(HS) */
+static
+void halbtc8822b2ant_action_sco(IN struct btc_coexist *btcoexist)
+{
+ static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+ static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+ u8 wifi_rssi_state, bt_rssi_state;
+
+ static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+ static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
+ u8 wifi_rssi_state2, bt_rssi_state2;
+ boolean wifi_busy = FALSE;
+ u32 wifi_bw = 1;
+
+ btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW,
+ &wifi_bw);
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+ wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+ &prewifi_rssi_state, 2,
+ coex_sta->wifi_coex_thres , 0);
+
+ wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+ &prewifi_rssi_state2, 2,
+ coex_sta->wifi_coex_thres2, 0);
+
+ bt_rssi_state = halbtc8822b2ant_bt_rssi_state(btcoexist,
+ &pre_bt_rssi_state, 2,
+ coex_sta->bt_coex_thres, 0);
+
+ bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(btcoexist,
+ &pre_bt_rssi_state2, 2,
+ coex_sta->bt_coex_thres2, 0);
+
+
+ if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+ BTC_RSSI_HIGH(bt_rssi_state)) {
+
+ halbtc8822b2ant_action_wifi_freerun(btcoexist);
+ } else {
+
+ halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8);
+ halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+ halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+
+ coex_dm->is_switch_to_1dot5_ant = FALSE;
+
+ if (coex_sta->is_bt_multi_link) {
+ halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 11);
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 25);
+ } else {
+ if (coex_sta->is_eSCO_mode)
+ halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
+ else /* 2-Ant free run if SCO mode */
+ halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 8);
+ }
+ }
+
+}
+
+
+static
+void halbtc8822b2ant_action_hid(IN struct btc_coexist *btcoexist)
+{
+ static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+ static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+ u8 wifi_rssi_state, bt_rssi_state;
+
+ static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+ static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
+ u8 wifi_rssi_state2, bt_rssi_state2;
+ boolean wifi_busy = FALSE;
+ u32 wifi_bw = 1;
+
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+ btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
+
+ wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+ &prewifi_rssi_state, 2,
+ coex_sta->wifi_coex_thres, 0);
+
+ wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+ &prewifi_rssi_state2, 2,
+ coex_sta->wifi_coex_thres2, 0);
+
+ bt_rssi_state = halbtc8822b2ant_bt_rssi_state(btcoexist,
+ &pre_bt_rssi_state, 2,
+ coex_sta->bt_coex_thres, 0);
+
+ bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(btcoexist,
+ &pre_bt_rssi_state2, 2,
+ coex_sta->bt_coex_thres2, 0);
+
+
+ if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+ BTC_RSSI_HIGH(bt_rssi_state)) {
+
+ halbtc8822b2ant_action_wifi_freerun(btcoexist);
+ } else {
+
+ halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8);
+ halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+ halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+
+ coex_dm->is_switch_to_1dot5_ant = FALSE;
+
+ if (coex_sta->is_hid_low_pri_tx_overhead) {
+
+ halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 108);
+ } else if (coex_sta->is_hid_rcu) {
+
+ halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 12);
+
+ if (wifi_busy)
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 113);
+ else
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 111);
+ } else if (wifi_bw == 0) { /* if 11bg mode */
+
+ halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 111);
+ } else {
+
+ halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE,
+ 111);
+ }
+ }
+
+}
+
+
+static
+void halbtc8822b2ant_action_a2dpsink(IN struct btc_coexist *btcoexist)
+{
+ static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+ static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+ u8 wifi_rssi_state, bt_rssi_state;
+
+ static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+ static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
+ u8 wifi_rssi_state2, bt_rssi_state2;
+ boolean wifi_busy = FALSE, wifi_turbo = FALSE;
+ boolean ap_enable = FALSE;
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+ btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
+ &coex_sta->scan_ap_num);
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &ap_enable);
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n",
+ coex_sta->scan_ap_num, coex_sta->wl_noisy_level);
+ BTC_TRACE(trace_buf);
+
+#if 1
+ if ((wifi_busy) && (coex_sta->wl_noisy_level == 0))
+ wifi_turbo = TRUE;
+#endif
+
+ wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+ &prewifi_rssi_state, 2,
+ coex_sta->wifi_coex_thres, 0);
+
+ wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+ &prewifi_rssi_state2, 2,
+ coex_sta->wifi_coex_thres2, 0);
+
+ bt_rssi_state = halbtc8822b2ant_bt_rssi_state(btcoexist,
+ &pre_bt_rssi_state, 2,
+ coex_sta->bt_coex_thres, 0);
+
+ bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(btcoexist,
+ &pre_bt_rssi_state2, 2,
+ coex_sta->bt_coex_thres2, 0);
+
+
+ if (BTC_RSSI_HIGH(wifi_rssi_state) ||ap_enable) {
+
+ halbtc8822b2ant_action_wifi_freerun(btcoexist);
+ } else {
+
+ halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8);
+ halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+ halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+
+ coex_dm->is_switch_to_1dot5_ant = TRUE;
+
+ if ((coex_sta->bt_relink_downcount != 0)
+ && (wifi_busy)) {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "############# [BTCoex], BT Re-Link + A2DP + WL busy\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
+
+ } else {
+ halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 105);
+ }
+
+ }
+}
+
+/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */
+static
+void halbtc8822b2ant_action_a2dp(IN struct btc_coexist *btcoexist)
+{
+ static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+ static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+ u8 wifi_rssi_state, bt_rssi_state;
+
+ static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+ static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
+ u8 wifi_rssi_state2, bt_rssi_state2;
+ boolean wifi_busy = FALSE, wifi_turbo = FALSE;
+
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+ btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
+ &coex_sta->scan_ap_num);
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n",
+ coex_sta->scan_ap_num, coex_sta->wl_noisy_level);
+ BTC_TRACE(trace_buf);
+
+
+ if ((wifi_busy) && (coex_sta->wl_noisy_level == 0))
+ wifi_turbo = TRUE;
+
+ wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+ &prewifi_rssi_state, 2,
+ coex_sta->wifi_coex_thres, 0);
+
+ wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+ &prewifi_rssi_state2, 2,
+ 45, 0);
+
+ bt_rssi_state = halbtc8822b2ant_bt_rssi_state(btcoexist,
+ &pre_bt_rssi_state, 2,
+ coex_sta->bt_coex_thres, 0);
+
+ bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(btcoexist,
+ &pre_bt_rssi_state2, 2,
+ coex_sta->bt_coex_thres2, 0);
+
+ if (BTC_RSSI_HIGH(wifi_rssi_state)) {
+
+ halbtc8822b2ant_action_wifi_freerun(btcoexist);
+ } else {
+
+ halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8);
+ halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+ halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+
+ coex_dm->is_switch_to_1dot5_ant = TRUE;
+
+ if ((coex_sta->bt_relink_downcount != 0)
+ && (wifi_busy)) {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "############# [BTCoex], BT Re-Link + A2DP + WL busy\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
+
+ } else {
+
+ halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
+
+ if (BTC_RSSI_HIGH(wifi_rssi_state2))
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 119);
+ else
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 109);
+ }
+ }
+}
+
+
+static
+void halbtc8822b2ant_action_pan_edr(IN struct btc_coexist *btcoexist)
+{
+ static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+ static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+ u8 wifi_rssi_state, bt_rssi_state;
+
+ static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+ static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
+ u8 wifi_rssi_state2, bt_rssi_state2;
+ boolean wifi_busy = FALSE, wifi_turbo = FALSE;
+
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+ btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
+ &coex_sta->scan_ap_num);
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n",
+ coex_sta->scan_ap_num, coex_sta->wl_noisy_level);
+ BTC_TRACE(trace_buf);
+
+#if 1
+ if ((wifi_busy) && (coex_sta->wl_noisy_level == 0))
+ wifi_turbo = TRUE;
+#endif
+
+ wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+ &prewifi_rssi_state, 2,
+ coex_sta->wifi_coex_thres, 0);
+
+ wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+ &prewifi_rssi_state2, 2,
+ coex_sta->wifi_coex_thres2, 0);
+
+ bt_rssi_state = halbtc8822b2ant_bt_rssi_state(btcoexist,
+ &pre_bt_rssi_state, 2,
+ coex_sta->bt_coex_thres, 0);
+
+ bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(btcoexist,
+ &pre_bt_rssi_state2, 2,
+ coex_sta->bt_coex_thres2, 0);
+
+
+ if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+ BTC_RSSI_HIGH(bt_rssi_state)) {
+
+ halbtc8822b2ant_action_wifi_freerun(btcoexist);
+ } else {
+
+ halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8);
+ halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+ halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+
+ coex_dm->is_switch_to_1dot5_ant = TRUE;
+
+ halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 11);
+
+ if (wifi_busy)
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 103);
+ else
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 104);
+ }
+
+}
+
+static
+void halbtc8822b2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist)
+{
+ static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+ static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+ u8 wifi_rssi_state, bt_rssi_state;
+
+ static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+ static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
+ u8 wifi_rssi_state2, bt_rssi_state2;
+ boolean wifi_busy = FALSE;
+ u32 wifi_bw = 1;
+
+ btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW,
+ &wifi_bw);
+
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+ wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+ &prewifi_rssi_state, 2,
+ coex_sta->wifi_coex_thres, 0);
+
+ wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+ &prewifi_rssi_state2, 2,
+ 45, 0);
+
+ bt_rssi_state = halbtc8822b2ant_bt_rssi_state(btcoexist,
+ &pre_bt_rssi_state, 2,
+ coex_sta->bt_coex_thres, 0);
+
+ bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(btcoexist,
+ &pre_bt_rssi_state2, 2,
+ coex_sta->bt_coex_thres2, 0);
+
+
+ if (BTC_RSSI_HIGH(wifi_rssi_state)) {
+
+ halbtc8822b2ant_action_wifi_freerun(btcoexist);
+ } else {
+
+ halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8);
+ halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+ halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+
+ coex_dm->is_switch_to_1dot5_ant = TRUE;
+
+ if ((coex_sta->bt_relink_downcount != 0)
+ && (wifi_busy)) {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "############# [BTCoex], BT Re-Link + A2DP + WL busy\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
+ halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
+ } else {
+
+ halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 12);
+
+ if (BTC_RSSI_HIGH(wifi_rssi_state2))
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 119);
+ else
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 109);
+ }
+ }
+
+}
+
+static
+void halbtc8822b2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist)
+{
+ static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+ static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+ u8 wifi_rssi_state, bt_rssi_state;
+
+ static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+ static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
+ u8 wifi_rssi_state2, bt_rssi_state2;
+ boolean wifi_busy = FALSE, wifi_turbo = FALSE;
+
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+ btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
+ &coex_sta->scan_ap_num);
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n",
+ coex_sta->scan_ap_num, coex_sta->wl_noisy_level);
+ BTC_TRACE(trace_buf);
+
+#if 1
+ if ((wifi_busy) && (coex_sta->wl_noisy_level == 0))
+ wifi_turbo = TRUE;
+#endif
+
+
+ wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+ &prewifi_rssi_state, 2,
+ coex_sta->wifi_coex_thres, 0);
+
+ wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+ &prewifi_rssi_state2, 2,
+ coex_sta->wifi_coex_thres2, 0);
+
+ bt_rssi_state = halbtc8822b2ant_bt_rssi_state(btcoexist,
+ &pre_bt_rssi_state, 2,
+ coex_sta->bt_coex_thres, 0);
+
+ bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(btcoexist,
+ &pre_bt_rssi_state2, 2,
+ coex_sta->bt_coex_thres2, 0);
+
+
+ if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+ BTC_RSSI_HIGH(bt_rssi_state)) {
+
+ halbtc8822b2ant_action_wifi_freerun(btcoexist);
+ } else {
+
+ halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8);
+ halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+ halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+
+ coex_dm->is_switch_to_1dot5_ant = TRUE;
+
+ if (wifi_turbo)
+ halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6);
+ else
+ halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
+
+ if (wifi_busy) {
+
+ if ((coex_sta->a2dp_bit_pool > 40) &&
+ (coex_sta->a2dp_bit_pool < 255))
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 107);
+ else
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 105);
+ } else
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 106);
+
+ }
+
+}
+
+
+
+
+/* PAN(EDR)+A2DP */
+static
+void halbtc8822b2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist)
+{
+ static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+ static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+ u8 wifi_rssi_state, bt_rssi_state;
+
+ static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+ static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
+ u8 wifi_rssi_state2, bt_rssi_state2;
+ boolean wifi_busy = FALSE, wifi_turbo = FALSE;
+
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+ btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
+ &coex_sta->scan_ap_num);
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n",
+ coex_sta->scan_ap_num, coex_sta->wl_noisy_level);
+ BTC_TRACE(trace_buf);
+
+ if ((wifi_busy) && (coex_sta->wl_noisy_level == 0))
+ wifi_turbo = TRUE;
+
+ wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+ &prewifi_rssi_state, 2,
+ coex_sta->wifi_coex_thres, 0);
+
+ wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+ &prewifi_rssi_state2, 2,
+ coex_sta->wifi_coex_thres2, 0);
+
+ bt_rssi_state = halbtc8822b2ant_bt_rssi_state(btcoexist,
+ &pre_bt_rssi_state, 2,
+ coex_sta->bt_coex_thres, 0);
+
+ bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(btcoexist,
+ &pre_bt_rssi_state2, 2,
+ coex_sta->bt_coex_thres2, 0);
+
+ if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+ BTC_RSSI_HIGH(bt_rssi_state)) {
+
+ halbtc8822b2ant_action_wifi_freerun(btcoexist);
+ } else {
+
+ halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8);
+ halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+ halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+
+ coex_dm->is_switch_to_1dot5_ant = TRUE;
+
+ halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
+ if (wifi_busy)
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 107);
+ else
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 106);
+ }
+
+}
+
+
+static
+void halbtc8822b2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist)
+{
+ static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+ static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+ u8 wifi_rssi_state, bt_rssi_state;
+
+ static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+ static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
+ u8 wifi_rssi_state2, bt_rssi_state2;
+ boolean wifi_busy = FALSE;
+ u32 wifi_bw = 1;
+
+ btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW,
+ &wifi_bw);
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+ wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+ &prewifi_rssi_state, 2,
+ coex_sta->wifi_coex_thres, 0);
+
+ wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+ &prewifi_rssi_state2, 2,
+ coex_sta->wifi_coex_thres2, 0);
+
+ bt_rssi_state = halbtc8822b2ant_bt_rssi_state(btcoexist,
+ &pre_bt_rssi_state, 2,
+ coex_sta->bt_coex_thres, 0);
+
+ bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(btcoexist,
+ &pre_bt_rssi_state2, 2,
+ coex_sta->bt_coex_thres2, 0);
+
+
+ if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+ BTC_RSSI_HIGH(bt_rssi_state)) {
+
+ halbtc8822b2ant_action_wifi_freerun(btcoexist);
+ } else {
+
+ halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8);
+ halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+ halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+
+ coex_dm->is_switch_to_1dot5_ant = TRUE;
+
+ halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 12);
+
+ if (wifi_busy)
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 103);
+ else
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 104);
+ }
+
+}
+
+
+/* HID+A2DP+PAN(EDR) */
+static
+void halbtc8822b2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist)
+{
+ static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW;
+ static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW;
+ u8 wifi_rssi_state, bt_rssi_state;
+
+ static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW;
+ static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW;
+ u8 wifi_rssi_state2, bt_rssi_state2;
+ boolean wifi_busy = FALSE;
+ u32 wifi_bw = 1;
+
+ btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW,
+ &wifi_bw);
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+
+ wifi_rssi_state = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+ &prewifi_rssi_state, 2,
+ coex_sta->wifi_coex_thres, 0);
+
+ wifi_rssi_state2 = halbtc8822b2ant_wifi_rssi_state(btcoexist,
+ &prewifi_rssi_state2, 2,
+ coex_sta->wifi_coex_thres2, 0);
+
+ bt_rssi_state = halbtc8822b2ant_bt_rssi_state(btcoexist,
+ &pre_bt_rssi_state, 2,
+ coex_sta->bt_coex_thres, 0);
+
+ bt_rssi_state2 = halbtc8822b2ant_bt_rssi_state(btcoexist,
+ &pre_bt_rssi_state2, 2,
+ coex_sta->bt_coex_thres2, 0);
+
+
+ if (BTC_RSSI_HIGH(wifi_rssi_state) &&
+ BTC_RSSI_HIGH(bt_rssi_state)) {
+
+ halbtc8822b2ant_action_wifi_freerun(btcoexist);
+ } else {
+
+ halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8);
+ halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+ halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+
+ coex_dm->is_switch_to_1dot5_ant = TRUE;
+
+ if (coex_sta->hid_busy_num >= 2) {
+ halbtc8822b2ant_coex_table_with_type(btcoexist,
+ NORMAL_EXEC, 12);
+
+ if (wifi_bw == 0) {
+ halbtc8822b2ant_set_wltoggle_coex_table(
+ btcoexist,
+ NORMAL_EXEC,
+ 0x1, 0xaa,
+ 0x5a, 0xaa,
+ 0xaa);
+ }
+ else
+ halbtc8822b2ant_set_wltoggle_coex_table(
+ btcoexist,
+ NORMAL_EXEC,
+ 0x2, 0xaa,
+ 0x5a, 0xaa,
+ 0xaa);
+
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 110);
+ } else {
+ halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
+
+ if (wifi_busy) {
+
+ if ((coex_sta->a2dp_bit_pool > 40) &&
+ (coex_sta->a2dp_bit_pool < 255))
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 107);
+ else
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 105);
+ } else
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 106);
+ }
+ }
+
+}
+
+static
+void halbtc8822b2ant_action_wifi_under5g(IN struct btc_coexist *btcoexist)
+{
+
+ /* fw all off */
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ************* under5g *************\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8);
+ halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+ halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+
+ halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC,
+ BT_8822B_2ANT_PHASE_5G_RUNTIME);
+
+ halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
+
+}
+
+
+static
+void halbtc8822b2ant_action_wifi_native_lps(IN struct btc_coexist *btcoexist)
+{
+ halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8);
+ halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+ halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+
+ halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
+
+}
+
+static
+void halbtc8822b2ant_action_wifi_link_process(IN struct btc_coexist *btcoexist)
+{
+ struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+ halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8);
+ halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+ halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+
+ if (bt_link_info->pan_exist) {
+ halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
+
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 22);
+
+ } else if (bt_link_info->a2dp_exist) {
+ halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
+
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 16);
+
+ } else {
+ halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
+
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 21);
+
+ }
+
+}
+
+static
+void halbtc8822b2ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist)
+{
+ halbtc8822b2ant_adjust_wl_tx_power(btcoexist, NORMAL_EXEC, 0xd8);
+ halbtc8822b2ant_adjust_bt_tx_power(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b2ant_adjust_wl_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+ halbtc8822b2ant_adjust_bt_rx_gain(btcoexist, NORMAL_EXEC, FALSE);
+
+ halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
+}
+
+
+static
+void halbtc8822b2ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist,
+ IN u8 multi_port_type)
+{
+ struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+ boolean miracast_plus_bt = FALSE;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex],action_wifi_multi_port\n");
+ BTC_TRACE(trace_buf);
+
+ if (bt_link_info->bt_link_exist)
+ miracast_plus_bt = TRUE;
+ else
+ miracast_plus_bt = FALSE;
+
+ btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT,
+ &miracast_plus_bt);
+
+ if (multi_port_type == BTC_MULTIPORT_MCC_DUAL_BAND) {
+ halbtc8822b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 13);
+ halbtc8822b2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0);
+ } else {
+ halbtc8822b2ant_action_wifi_freerun(btcoexist);
+ }
+}
+
+static
+void halbtc8822b2ant_action_wifi_connected(IN struct btc_coexist *btcoexist)
+ {
+ switch (coex_dm->cur_algorithm) {
+
+ case BT_8822B_2ANT_COEX_ALGO_SCO:
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Action 2-Ant, algorithm = SCO.\n");
+ BTC_TRACE(trace_buf);
+ halbtc8822b2ant_action_sco(btcoexist);
+ break;
+ case BT_8822B_2ANT_COEX_ALGO_HID:
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Action 2-Ant, algorithm = HID.\n");
+ BTC_TRACE(trace_buf);
+ halbtc8822b2ant_action_hid(btcoexist);
+ break;
+ case BT_8822B_2ANT_COEX_ALGO_A2DP:
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Action 2-Ant, algorithm = A2DP.\n");
+ BTC_TRACE(trace_buf);
+ halbtc8822b2ant_action_a2dp(btcoexist);
+ break;
+ case BT_8822B_2ANT_COEX_ALGO_A2DPSINK:
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Action 2-Ant, algorithm = A2DP Sink.\n");
+ BTC_TRACE(trace_buf);
+ halbtc8822b2ant_action_a2dpsink(btcoexist);
+ break;
+ case BT_8822B_2ANT_COEX_ALGO_A2DP_PANHS:
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n");
+ BTC_TRACE(trace_buf);
+ halbtc8822b2ant_action_a2dp_pan_hs(btcoexist);
+ break;
+ case BT_8822B_2ANT_COEX_ALGO_PANEDR:
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n");
+ BTC_TRACE(trace_buf);
+ halbtc8822b2ant_action_pan_edr(btcoexist);
+ break;
+ case BT_8822B_2ANT_COEX_ALGO_PANEDR_A2DP:
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n");
+ BTC_TRACE(trace_buf);
+ halbtc8822b2ant_action_pan_edr_a2dp(btcoexist);
+ break;
+ case BT_8822B_2ANT_COEX_ALGO_PANEDR_HID:
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n");
+ BTC_TRACE(trace_buf);
+ halbtc8822b2ant_action_pan_edr_hid(btcoexist);
+ break;
+ case BT_8822B_2ANT_COEX_ALGO_HID_A2DP_PANEDR:
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n");
+ BTC_TRACE(trace_buf);
+ halbtc8822b2ant_action_hid_a2dp_pan_edr(
+ btcoexist);
+ break;
+ case BT_8822B_2ANT_COEX_ALGO_HID_A2DP:
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n");
+ BTC_TRACE(trace_buf);
+ halbtc8822b2ant_action_hid_a2dp(btcoexist);
+ break;
+ case BT_8822B_2ANT_COEX_ALGO_NOPROFILEBUSY:
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Action 2-Ant, algorithm = No-Profile busy.\n");
+ BTC_TRACE(trace_buf);
+ halbtc8822b2ant_action_bt_idle(btcoexist);
+ break;
+ default:
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n");
+ BTC_TRACE(trace_buf);
+ halbtc8822b2ant_action_coex_all_off(btcoexist);
+ break;
+ }
+
+ coex_dm->pre_algorithm = coex_dm->cur_algorithm;
+
+ }
+
+static
+void halbtc8822b2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist)
+{
+ u8 algorithm = 0, mcc_dualband = BTC_MULTIPORT_SCC;
+ u32 num_of_wifi_link = 0;
+ u32 wifi_link_status = 0;
+ struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+ boolean scan = FALSE, link = FALSE, roam = FALSE,
+ under_4way = FALSE, wifi_connected = FALSE,
+ wifi_under_5g = FALSE, bt_hs_on = FALSE;
+ u8 wifi_central_chnl = 0;
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
+ &under_4way);
+
+ btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
+ &wifi_central_chnl);
+ coex_sta->wl_center_channel = wifi_central_chnl;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], RunCoexistMechanism()===>\n");
+ BTC_TRACE(trace_buf);
+
+ if (btcoexist->manual_control) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n");
+ BTC_TRACE(trace_buf);
+ return;
+ }
+
+ if (btcoexist->stop_coex_dm) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n");
+ BTC_TRACE(trace_buf);
+ return;
+ }
+
+ if (coex_sta->under_ips) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], wifi is under IPS !!!\n");
+ BTC_TRACE(trace_buf);
+ return;
+ }
+
+ if (!coex_sta->run_time_state) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], return for run_time_state = FALSE !!!\n");
+ BTC_TRACE(trace_buf);
+ return;
+ }
+
+ if (coex_sta->freeze_coexrun_by_btinfo) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BtInfoNotify(), return for freeze_coexrun_by_btinfo\n");
+ BTC_TRACE(trace_buf);
+ return;
+ }
+
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_DUAL_BAND_CONNECTED, &mcc_dualband);
+ if (mcc_dualband == BTC_MULTIPORT_MCC_DUAL_BAND) {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], RunCoexistMechanism(), mcc dual band!!\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b2ant_action_wifi_multi_port(btcoexist, BTC_MULTIPORT_MCC_DUAL_BAND);
+ return;
+ }
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+ if ((wifi_under_5g) &&
+ (coex_sta->switch_band_notify_to != BTC_SWITCH_TO_24G) &&
+ (coex_sta->switch_band_notify_to != BTC_SWITCH_TO_24G_NOFORSCAN)) {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], WiFi is under 5G!!!\n");
+ BTC_TRACE(trace_buf);
+ halbtc8822b2ant_action_wifi_under5g(btcoexist);
+ return;
+ } else {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], WiFi is under 2G!!!\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+ NORMAL_EXEC,
+ BT_8822B_2ANT_PHASE_2G_RUNTIME);
+ }
+
+halbtc8822b2ant_post_state_to_bt(btcoexist,
+ BT_8822B_2ANT_SCOREBOARD_BTCQDDR,
+ TRUE);
+
+ if ((coex_sta->under_lps) && (!coex_sta->force_lps_ctrl) &&
+ (!coex_sta->acl_busy)) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], RunCoexistMechanism(), wifi is under LPS !!!\n");
+ BTC_TRACE(trace_buf);
+ halbtc8822b2ant_action_wifi_native_lps(btcoexist);
+ return;
+ }
+
+ if (coex_sta->bt_whck_test) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT is under WHCK TEST!!!\n");
+ BTC_TRACE(trace_buf);
+ halbtc8822b2ant_action_bt_whql_test(btcoexist);
+ return;
+ }
+
+ if (coex_sta->bt_disabled) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT is disabled!!!\n");
+ BTC_TRACE(trace_buf);
+ halbtc8822b2ant_action_coex_all_off(btcoexist);
+ return;
+ }
+
+ if (coex_sta->c2h_bt_inquiry_page) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT is under inquiry/page scan !!\n");
+ BTC_TRACE(trace_buf);
+ halbtc8822b2ant_action_bt_inquiry(btcoexist);
+ return;
+ }
+
+ if ((coex_sta->is_setupLink) && (!coex_sta->is_2g_freerun)) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT is re-link !!!\n");
+ BTC_TRACE(trace_buf);
+ halbtc8822b2ant_action_bt_relink(btcoexist);
+ return;
+ }
+
+ /* for P2P */
+ btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS,
+ &wifi_link_status);
+ num_of_wifi_link = wifi_link_status >> 16;
+
+ if ((num_of_wifi_link >= 2) ||
+ (wifi_link_status & WIFI_P2P_GO_CONNECTED)) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n",
+ num_of_wifi_link, wifi_link_status);
+ BTC_TRACE(trace_buf);
+
+ if (scan || link || roam || under_4way) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n",
+ scan, link, roam, under_4way);
+ BTC_TRACE(trace_buf);
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], wifi is under linkscan process + Multi-Port !!\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b2ant_action_wifi_link_process(btcoexist);
+ } else {
+ halbtc8822b2ant_action_wifi_multi_port(btcoexist, mcc_dualband);
+ }
+
+ return;
+ }
+
+ if ((BT_8822B_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+ coex_dm->bt_status) ||
+ (BT_8822B_2ANT_BT_STATUS_CONNECTED_IDLE ==
+ coex_dm->bt_status)) {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Action 2-Ant, bt idle!!.\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b2ant_action_bt_idle(btcoexist);
+ return;
+ }
+
+ algorithm = halbtc8822b2ant_action_algorithm(btcoexist);
+ coex_dm->cur_algorithm = algorithm;
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Algorithm = %d\n",
+ coex_dm->cur_algorithm);
+ BTC_TRACE(trace_buf);
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected);
+
+ if (scan || link || roam || under_4way) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], WiFi is under Link Process !!\n");
+ BTC_TRACE(trace_buf);
+ halbtc8822b2ant_action_wifi_link_process(btcoexist);
+ } else if (wifi_connected) {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Action 2-Ant, wifi connected!!.\n");
+ BTC_TRACE(trace_buf);
+ halbtc8822b2ant_action_wifi_connected(btcoexist);
+
+ } else {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Action 2-Ant, wifi not-connected!!.\n");
+ BTC_TRACE(trace_buf);
+ halbtc8822b2ant_action_wifi_not_connected(btcoexist);
+ }
+}
+
+static
+void halbtc8822b2ant_init_coex_dm(IN struct btc_coexist *btcoexist)
+{
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Coex Mechanism Init!!\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, FALSE);
+
+ coex_sta->pop_event_cnt = 0;
+ coex_sta->cnt_RemoteNameReq = 0;
+ coex_sta->cnt_ReInit = 0;
+ coex_sta->cnt_setupLink = 0;
+ coex_sta->cnt_IgnWlanAct = 0;
+ coex_sta->cnt_Page = 0;
+ coex_sta->cnt_RoleSwitch = 0;
+ coex_sta->switch_band_notify_to = BTC_NOT_SWITCH;
+
+ halbtc8822b2ant_query_bt_info(btcoexist);
+}
+
+
+static
+void halbtc8822b2ant_init_hw_config(IN struct btc_coexist *btcoexist,
+ IN boolean wifi_only)
+{
+ u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0;
+ u32 RTL97F_8822B = 0;
+ u8 i = 0;
+
+
+ u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4);
+ u32tmp1 = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
+ u32tmp2 = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
+
+ if (RTL97F_8822B) {
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, 0x04, 0x0);
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x41, 0x02, 0x0);
+
+ /* set GNT_BT to SW high */
+ halbtc8822b2ant_ltecoex_set_gnt_bt(btcoexist,
+ BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
+ BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
+ BT_8822B_2ANT_SIG_STA_SET_TO_HIGH);
+ /* Set GNT_WL to SW high */
+ halbtc8822b2ant_ltecoex_set_gnt_wl(btcoexist,
+ BT_8822B_2ANT_GNT_BLOCK_RFC_BB,
+ BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW,
+ BT_8822B_2ANT_SIG_STA_SET_TO_HIGH);
+ return;
+ }
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], (Before Init HW config) 0xcb4 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n",
+ u32tmp3, u32tmp1, u32tmp2);
+ BTC_TRACE(trace_buf);
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], 2Ant Init HW Config!!\n");
+ BTC_TRACE(trace_buf);
+
+ coex_sta->bt_coex_supported_feature = 0;
+ coex_sta->bt_coex_supported_version = 0;
+ coex_sta->bt_ble_scan_type = 0;
+ coex_sta->bt_ble_scan_para[0] = 0;
+ coex_sta->bt_ble_scan_para[1] = 0;
+ coex_sta->bt_ble_scan_para[2] = 0;
+ coex_sta->bt_reg_vendor_ac = 0xffff;
+ coex_sta->bt_reg_vendor_ae = 0xffff;
+ coex_sta->isolation_btween_wb = BT_8822B_2ANT_DEFAULT_ISOLATION;
+ coex_sta->gnt_error_cnt = 0;
+ coex_sta->bt_relink_downcount = 0;
+ coex_sta->is_set_ps_state_fail = FALSE;
+ coex_sta->cnt_set_ps_state_fail = 0;
+
+ for (i = 0; i <= 9; i++)
+ coex_sta->bt_afh_map[i] = 0;
+
+ /* 0xf0[15:12] --> Chip Cut information */
+ coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist,
+ 0xf1) & 0xf0) >> 4;
+
+ coex_sta->dis_ver_info_cnt = 0;
+
+ if ((rfe_type->rfe_module_type == 2) ||
+ (rfe_type->rfe_module_type == 4))
+ halbtc8822b2ant_post_state_to_bt(btcoexist,
+ BT_8822B_2ANT_SCOREBOARD_EXTFEM, TRUE);
+ else
+ halbtc8822b2ant_post_state_to_bt(btcoexist,
+ BT_8822B_2ANT_SCOREBOARD_EXTFEM, FALSE);
+
+ halbtc8822b2ant_coex_switch_threshold(btcoexist,
+ coex_sta->isolation_btween_wb);
+
+ /* enable TBTT nterrupt */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, 0x1);
+
+ /* BT report packet sample rate */
+ btcoexist->btc_write_1byte(btcoexist, 0x790, 0x5);
+
+ /* Init 0x778 = 0x1 for 2-Ant */
+ btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1);
+
+ /* Enable PTA (3-wire function form BT side) */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1);
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x41, 0x02, 0x1);
+
+ /* Enable PTA (tx/rx signal form WiFi side) */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4c6, 0x10, 0x1);
+
+ halbtc8822b2ant_enable_gnt_to_gpio(btcoexist, TRUE);
+
+ /*GNT_BT=1 while select both */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x763, 0x10, 0x1);
+
+
+ /* Enable counter statistics */ /* 0x76e[3] =1, WLAN_Act control by PTA */
+ btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4);
+
+ halbtc8822b2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 5);
+
+ halbtc8822b2ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 0);
+
+
+ if (coex_sta->is_rf_state_off) {
+
+ halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+ FORCE_EXEC,
+ BT_8822B_2ANT_PHASE_WLAN_OFF);
+
+ btcoexist->stop_coex_dm = TRUE;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ********** halbtc8822b2ant_init_hw_config (RF Off)**********\n");
+ BTC_TRACE(trace_buf);
+ } else if (wifi_only) {
+ coex_sta->concurrent_rx_mode_on = FALSE;
+ /* Path config */
+ /* Set Antenna Path */
+ halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+ FORCE_EXEC,
+ BT_8822B_2ANT_PHASE_WLANONLY_INIT);
+
+ btcoexist->stop_coex_dm = TRUE;
+ } else {
+ /* Set BT polluted packet on for Tx rate adaptive not including
+ * Tx retry break by PTA, 0x45c[19] =1
+ */
+ btcoexist->btc_write_1byte_bitmask(btcoexist, 0x45e, 0x8, 0x1);
+
+ coex_sta->concurrent_rx_mode_on = TRUE;
+
+ btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0x2, 0x0);
+
+ /* Set Antenna Path */
+ halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+ FORCE_EXEC,
+ BT_8822B_2ANT_PHASE_COEX_INIT);
+
+ btcoexist->stop_coex_dm = FALSE;
+ }
+}
+
+
+
+/* ************************************************************
+ * work around function start with wa_halbtc8822b2ant_
+ * ************************************************************
+ * ************************************************************
+ * extern function start with ex_halbtc8822b2ant_
+ * ************************************************************ */
+void ex_halbtc8822b2ant_power_on_setting(IN struct btc_coexist *btcoexist)
+{
+ struct btc_board_info *board_info = &btcoexist->board_info;
+ u8 u8tmp = 0x0;
+ u16 u16tmp = 0x0;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "xxxxxxxxxxxxxxxx Execute 8822b 2-Ant PowerOn Setting xxxxxxxxxxxxxxxx!!\n");
+ BTC_TRACE(trace_buf);
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "Ant Det Finish = %s, Ant Det Number = %d\n",
+ (board_info->btdm_ant_det_finish ? "Yes" : "No"),
+ board_info->btdm_ant_num_by_ant_det);
+ BTC_TRACE(trace_buf);
+
+
+ btcoexist->stop_coex_dm = TRUE;
+ coex_sta->is_rf_state_off = FALSE;
+ psd_scan->ant_det_is_ant_det_available = FALSE;
+
+ /* enable BB, REG_SYS_FUNC_EN such that we can write BB Reg correctly */
+ u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2);
+ btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1));
+
+
+ /* Local setting bit define */
+ /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */
+ /* BIT1: "0" for internal switch; "1" for external switch */
+ /* BIT2: "0" for one antenna; "1" for two antenna */
+ /* NOTE: here default all internal switch and 1-antenna ==>
+ * BIT1=0 and BIT2=0
+ */
+
+ /* Check efuse 0xc3[6] for Single Antenna Path */
+#if 0
+ if (board_info->single_ant_path == 0) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ********** Single Antenna, Antenna at Aux Port\n");
+ BTC_TRACE(trace_buf);
+
+ board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT;
+
+ u8tmp = 7;
+ } else if (board_info->single_ant_path == 1) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ********** Single Antenna, Antenna at Main Port\n");
+ BTC_TRACE(trace_buf);
+
+ board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;
+
+ u8tmp = 6;
+ }
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ********** (Power On) single_ant_path = %d, btdm_ant_pos = %d\n",
+ board_info->single_ant_path , board_info->btdm_ant_pos);
+ BTC_TRACE(trace_buf);
+#endif
+
+ /* Setup RF front end type */
+ halbtc8822b2ant_set_rfe_type(btcoexist);
+
+ /* Set Antenna Path to BT side */
+ halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC,
+ BT_8822B_2ANT_PHASE_COEX_POWERON);
+
+ /* Save"single antenna position" info in Local register setting for
+ * FW reading, because FW may not ready at power on
+ */
+ if (btcoexist->chip_interface == BTC_INTF_PCI)
+ btcoexist->btc_write_local_reg_1byte(btcoexist, 0x3e0, u8tmp);
+ else if (btcoexist->chip_interface == BTC_INTF_USB)
+ btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp);
+ else if (btcoexist->chip_interface == BTC_INTF_SDIO)
+ btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, u8tmp);
+
+ /* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */
+ halbtc8822b2ant_enable_gnt_to_gpio(btcoexist, TRUE);
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ********** LTE coex Reg 0x38 (Power-On) = 0x%x**********\n",
+ halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, 0x38));
+ BTC_TRACE(trace_buf);
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ********** MAC Reg 0x70/ BB Reg 0xcbc (Power-On) = 0x%x / 0x%x\n",
+ btcoexist->btc_read_4byte(btcoexist, 0x70),
+ btcoexist->btc_read_4byte(btcoexist, 0xcbc));
+ BTC_TRACE(trace_buf);
+
+}
+
+void ex_halbtc8822b2ant_pre_load_firmware(IN struct btc_coexist *btcoexist)
+{
+ struct btc_board_info *board_info = &btcoexist->board_info;
+ u8 u8tmp = 0x4; /* Set BIT2 by default since it's 2ant case */
+
+ /* */
+ /* S0 or S1 setting and Local register setting
+ * (By the setting fw can get ant number, S0/S1, ... info)
+ */
+ /* Local setting bit define */
+ /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */
+ /* BIT1: "0" for internal switch; "1" for external switch */
+ /* BIT2: "0" for one antenna; "1" for two antenna */
+ /* NOTE: here default all internal switch and 1-antenna ==>
+ * BIT1=0 and BIT2=0
+ */
+ if (btcoexist->chip_interface == BTC_INTF_USB) {
+ /* fixed at S0 for USB interface */
+ u8tmp |= 0x1; /* antenna inverse */
+ btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp);
+ } else {
+ /* for PCIE and SDIO interface, we check efuse 0xc3[6] */
+ if (board_info->single_ant_path == 0) {
+ } else if (board_info->single_ant_path == 1) {
+ /* set to S0 */
+ u8tmp |= 0x1; /* antenna inverse */
+ }
+
+ if (btcoexist->chip_interface == BTC_INTF_PCI)
+ btcoexist->btc_write_local_reg_1byte(btcoexist, 0x3e0,
+ u8tmp);
+ else if (btcoexist->chip_interface == BTC_INTF_SDIO)
+ btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60,
+ u8tmp);
+ }
+}
+
+void ex_halbtc8822b2ant_init_hw_config(IN struct btc_coexist *btcoexist,
+ IN boolean wifi_only)
+{
+ halbtc8822b2ant_init_hw_config(btcoexist, wifi_only);
+}
+
+void ex_halbtc8822b2ant_init_coex_dm(IN struct btc_coexist *btcoexist)
+{
+
+ halbtc8822b2ant_init_coex_dm(btcoexist);
+}
+
+
+void ex_halbtc8822b2ant_display_simple_coex_info(IN struct btc_coexist *btcoexist)
+{
+ struct btc_board_info *board_info = &btcoexist->board_info;
+ struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+ u8 *cli_buf = btcoexist->cli_buf;
+ u32 bt_patch_ver = 0, bt_coex_ver = 0;
+ static u8 cnt = 0;
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n _____[BT Coexist info]____");
+ CL_PRINTF(cli_buf);
+
+ if (btcoexist->manual_control) {
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n __[Under Manual Control]_");
+ CL_PRINTF(cli_buf);
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n _________________________");
+ CL_PRINTF(cli_buf);
+ }
+
+ if (!coex_sta->bt_disabled) {
+ if (coex_sta->bt_coex_supported_feature == 0)
+ btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_FEATURE,
+ &coex_sta->bt_coex_supported_feature);
+
+ if ((coex_sta->bt_coex_supported_version == 0) ||
+ (coex_sta->bt_coex_supported_version == 0xffff))
+ btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_VERSION,
+ &coex_sta->bt_coex_supported_version);
+
+ if (coex_sta->bt_reg_vendor_ac == 0xffff)
+ coex_sta->bt_reg_vendor_ac = (u16)(
+ btcoexist->btc_get_bt_reg(btcoexist, 3,
+ 0xac) & 0xffff);
+
+ if (coex_sta->bt_reg_vendor_ae == 0xffff)
+ coex_sta->bt_reg_vendor_ae = (u16)(
+ btcoexist->btc_get_bt_reg(btcoexist, 3,
+ 0xae) & 0xffff);
+
+ btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER,
+ &bt_patch_ver);
+ btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver;
+
+ if (coex_sta->num_of_profile > 0) {
+ cnt++;
+
+ if (cnt >= 3) {
+ btcoexist->btc_get_bt_afh_map_from_bt(btcoexist, 0,
+ &coex_sta->bt_afh_map[0]);
+ cnt = 0;
+ }
+ }
+ }
+
+ // BT coex. info.
+ if (psd_scan->ant_det_try_count == 0) {
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %d/ %d/ %s / %d",
+ "Ant PG Num/ Mech/ Pos/ RFE",
+ board_info->pg_ant_num, board_info->btdm_ant_num,
+ (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT
+ ? "Main" : "Aux"),
+ rfe_type->rfe_module_type);
+ CL_PRINTF(cli_buf);
+ } else {
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %d/ %d/ %s/ %d (%d/%d/%d)",
+ "Ant PG Num/ Mech(Ant_Det)/ Pos/ RFE",
+ board_info->pg_ant_num,
+ board_info->btdm_ant_num_by_ant_det,
+ (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT
+ ? "Main" : "Aux"),
+ rfe_type->rfe_module_type,
+ psd_scan->ant_det_try_count,
+ psd_scan->ant_det_fail_count,
+ psd_scan->ant_det_result);
+ CL_PRINTF(cli_buf);
+
+
+ if (board_info->btdm_ant_det_finish) {
+
+ if (psd_scan->ant_det_result != 12)
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %s",
+ "Ant Det PSD Value",
+ psd_scan->ant_det_peak_val);
+ else
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %d",
+ "Ant Det PSD Value",
+ psd_scan->ant_det_psd_scan_peak_val
+ / 100);
+ CL_PRINTF(cli_buf);
+ }
+ }
+
+ bt_coex_ver = (coex_sta->bt_coex_supported_version & 0xff);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)",
+ "CoexVer WL/ BT_Desired/ BT_Report",
+ glcoex_ver_date_8822b_2ant, glcoex_ver_8822b_2ant,
+ glcoex_ver_btdesired_8822b_2ant,
+ bt_coex_ver,
+ (bt_coex_ver == 0xff ? "Unknown" :
+ (coex_sta->bt_disabled ? "BT-disable" :
+ (bt_coex_ver >= glcoex_ver_btdesired_8822b_2ant ?
+ "Match" : "Mis-Match"))));
+ CL_PRINTF(cli_buf);
+
+ // BT status
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %s",
+ "BT status",
+ ((coex_sta->bt_disabled) ? ("disabled") : ((
+ coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page")
+ : ((BT_8822B_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+ coex_dm->bt_status) ? "non-connected idle" :
+ ((coex_dm->bt_status == BT_8822B_2ANT_BT_STATUS_CONNECTED_IDLE)
+ ? "connected-idle" : "busy")))));
+ CL_PRINTF(cli_buf);
+
+ // HW Settings
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+ "0x770(Hi-pri rx/tx)",
+ coex_sta->high_priority_rx, coex_sta->high_priority_tx);
+ CL_PRINTF(cli_buf);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s",
+ "0x774(Lo-pri rx/tx)",
+ coex_sta->low_priority_rx, coex_sta->low_priority_tx,
+ (bt_link_info->slave_role ? "(Slave!!)" : (
+ coex_sta->is_tdma_btautoslot_hang ? "(auto-slot hang!!)" : "")));
+ CL_PRINTF(cli_buf);
+
+}
+
+
+void ex_halbtc8822b2ant_display_coex_info(IN struct btc_coexist *btcoexist)
+{
+ struct btc_board_info *board_info = &btcoexist->board_info;
+ struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
+
+ u8 *cli_buf = btcoexist->cli_buf;
+ u8 u8tmp[4], i, ps_tdma_case = 0;
+ u32 u32tmp[4];
+ u16 u16tmp[4];
+ u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck, ratio_ofdm;
+ u32 fw_ver = 0, bt_patch_ver = 0, bt_coex_ver = 0;
+ static u8 pop_report_in_10s = 0;
+ u32 phyver = 0;
+ boolean lte_coex_on = FALSE;
+ static u8 cnt = 0;
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n ============[BT Coexist info]============");
+ CL_PRINTF(cli_buf);
+
+ if (btcoexist->manual_control) {
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n ============[Under Manual Control]============");
+ CL_PRINTF(cli_buf);
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n ==========================================");
+ CL_PRINTF(cli_buf);
+ }
+
+ if (!coex_sta->bt_disabled) {
+ if (coex_sta->bt_coex_supported_feature == 0)
+ btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_FEATURE,
+ &coex_sta->bt_coex_supported_feature);
+
+ if ((coex_sta->bt_coex_supported_version == 0) ||
+ (coex_sta->bt_coex_supported_version == 0xffff))
+ btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_VERSION,
+ &coex_sta->bt_coex_supported_version);
+
+ if (coex_sta->bt_reg_vendor_ac == 0xffff)
+ coex_sta->bt_reg_vendor_ac = (u16)(
+ btcoexist->btc_get_bt_reg(btcoexist, 3,
+ 0xac) & 0xffff);
+
+ if (coex_sta->bt_reg_vendor_ae == 0xffff)
+ coex_sta->bt_reg_vendor_ae = (u16)(
+ btcoexist->btc_get_bt_reg(btcoexist, 3,
+ 0xae) & 0xffff);
+
+ btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER,
+ &bt_patch_ver);
+ btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver;
+
+ if (coex_sta->num_of_profile > 0) {
+ cnt++;
+
+ if (cnt >= 3) {
+ btcoexist->btc_get_bt_afh_map_from_bt(btcoexist, 0,
+ &coex_sta->bt_afh_map[0]);
+ cnt = 0;
+ }
+ }
+ }
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %d/ %d/ %s / %d",
+ "Ant PG Num/ Mech/ Pos/ RFE",
+ board_info->pg_ant_num, board_info->btdm_ant_num,
+ (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT
+ ? "Main" : "Aux"),
+ rfe_type->rfe_module_type);
+ CL_PRINTF(cli_buf);
+
+ bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver;
+ btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
+ phyver = btcoexist->btc_get_bt_phydm_version(btcoexist);
+
+ bt_coex_ver = (coex_sta->bt_coex_supported_version & 0xff);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)",
+ "CoexVer WL/ BT_Desired/ BT_Report",
+ glcoex_ver_date_8822b_2ant, glcoex_ver_8822b_2ant,
+ glcoex_ver_btdesired_8822b_2ant,
+ bt_coex_ver,
+ (bt_coex_ver == 0xff ? "Unknown" :
+ (coex_sta->bt_disabled ? "BT-disable" :
+ (bt_coex_ver >= glcoex_ver_btdesired_8822b_2ant ?
+ "Match" : "Mis-Match"))));
+ CL_PRINTF(cli_buf);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c",
+ "W_FW/ B_FW/ Phy/ Kt",
+ fw_ver, bt_patch_ver, phyver,
+ coex_sta->cut_version + 65);
+ CL_PRINTF(cli_buf);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x (RF-Ch = %d)",
+ "AFH Map to BT",
+ coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
+ coex_dm->wifi_chnl_info[2], coex_sta->wl_center_channel);
+ CL_PRINTF(cli_buf);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d ",
+ "Isolation/WL_Thres/BT_Thres",
+ coex_sta->isolation_btween_wb,
+ coex_sta->wifi_coex_thres,
+ coex_sta->bt_coex_thres);
+ CL_PRINTF(cli_buf);
+
+ /* wifi status */
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+ "============[Wifi Status]============");
+ CL_PRINTF(cli_buf);
+ btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+ "============[BT Status]============");
+ CL_PRINTF(cli_buf);
+
+ pop_report_in_10s++;
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %s/ %ddBm/ %d/ %d",
+ "BT status/ rssi/ retryCnt/ popCnt",
+ ((coex_sta->bt_disabled) ? ("disabled") : ((
+ coex_sta->c2h_bt_inquiry_page) ? ("inquiry-page")
+ : ((BT_8822B_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
+ coex_dm->bt_status) ? "non-connected-idle" :
+ ((coex_dm->bt_status == BT_8822B_2ANT_BT_STATUS_CONNECTED_IDLE)
+ ? "connected-idle" : "busy")))),
+ coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt,
+ coex_sta->pop_event_cnt);
+ CL_PRINTF(cli_buf);
+
+ if (pop_report_in_10s >= 5) {
+ coex_sta->pop_event_cnt = 0;
+ pop_report_in_10s = 0;
+ }
+
+
+ if (coex_sta->num_of_profile != 0)
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %s%s%s%s%s (multilink = %d)",
+ "Profiles",
+ ((bt_link_info->a2dp_exist) ?
+ ((coex_sta->is_bt_a2dp_sink) ? "A2DP sink," :
+ "A2DP,") : ""),
+ ((bt_link_info->sco_exist) ? "HFP," : ""),
+ ((bt_link_info->hid_exist) ?
+ ((coex_sta->is_hid_rcu) ? "HID(RCU)" :
+ ((coex_sta->hid_busy_num >= 2) ? "HID(4/18)," :
+ "HID(2/18),")) : ""),
+ ((bt_link_info->pan_exist) ?
+ ((coex_sta->is_bt_opp_exist) ? "OPP," : "PAN,") : ""),
+ ((coex_sta->voice_over_HOGP) ? "Voice" : ""),
+ coex_sta->is_bt_multi_link);
+ else
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = None", "Profiles");
+
+ CL_PRINTF(cli_buf);
+
+
+ if (bt_link_info->a2dp_exist) {
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s",
+ "A2DP Rate/Bitpool/Auto_Slot",
+ ((coex_sta->is_A2DP_3M) ? "3M" : "No_3M"),
+ coex_sta->a2dp_bit_pool,
+ ((coex_sta->is_autoslot) ? "On" : "Off")
+ );
+ CL_PRINTF(cli_buf);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ %d/ %d",
+ "V_ID/D_name/FBSlot_Legacy/FBSlot_Le",
+ coex_sta->bt_a2dp_vendor_id,
+ coex_sta->bt_a2dp_device_name,
+ coex_sta->legacy_forbidden_slot,
+ coex_sta->le_forbidden_slot
+ );
+ CL_PRINTF(cli_buf);
+ }
+
+ if (bt_link_info->hid_exist) {
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d",
+ "HID PairNum",
+ coex_sta->hid_pair_cnt
+ );
+ CL_PRINTF(cli_buf);
+ }
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s/ 0x%x",
+ "Role/RoleSwCnt/IgnWlact/Feature",
+ ((bt_link_info->slave_role) ? "Slave" : "Master"),
+ coex_sta->cnt_RoleSwitch,
+ ((coex_dm->cur_ignore_wlan_act) ? "Yes" : "No"),
+ coex_sta->bt_coex_supported_feature);
+ CL_PRINTF(cli_buf);
+
+ if (coex_sta->is_ble_scan_en) {
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+ "BLEScan Type/TV/Init/Ble",
+ coex_sta->bt_ble_scan_type,
+ (coex_sta->bt_ble_scan_type & 0x1 ?
+ coex_sta->bt_ble_scan_para[0] : 0x0),
+ (coex_sta->bt_ble_scan_type & 0x2 ?
+ coex_sta->bt_ble_scan_para[1] : 0x0),
+ (coex_sta->bt_ble_scan_type & 0x4 ?
+ coex_sta->bt_ble_scan_para[2] : 0x0));
+ CL_PRINTF(cli_buf);
+ }
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d",
+ "ReInit/ReLink/IgnWlact/Page/NameReq",
+ coex_sta->cnt_ReInit,
+ coex_sta->cnt_setupLink,
+ coex_sta->cnt_IgnWlanAct,
+ coex_sta->cnt_Page,
+ coex_sta->cnt_RemoteNameReq
+ );
+ CL_PRINTF(cli_buf);
+
+ halbtc8822b2ant_read_score_board(btcoexist, &u16tmp[0]);
+
+ if ((coex_sta->bt_reg_vendor_ae == 0xffff) ||
+ (coex_sta->bt_reg_vendor_ac == 0xffff))
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = x/ x/ 0x%04x",
+ "0xae[4]/0xac[1:0]/Scoreboard(B->W)", u16tmp[0]);
+ else
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = 0x%x/ 0x%x/ 0x%04x",
+ "0xae[4]/0xac[1:0]/Scoreboard(B->W)",
+ (int)((coex_sta->bt_reg_vendor_ae & BIT(4)) >> 4),
+ coex_sta->bt_reg_vendor_ac & 0x3, u16tmp[0]);
+ CL_PRINTF(cli_buf);
+
+ if (coex_sta->num_of_profile > 0) {
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %02x%02x%02x%02x %02x%02x%02x%02x %02x%02x",
+ "AFH MAP",
+ coex_sta->bt_afh_map[0],
+ coex_sta->bt_afh_map[1],
+ coex_sta->bt_afh_map[2],
+ coex_sta->bt_afh_map[3],
+ coex_sta->bt_afh_map[4],
+ coex_sta->bt_afh_map[5],
+ coex_sta->bt_afh_map[6],
+ coex_sta->bt_afh_map[7],
+ coex_sta->bt_afh_map[8],
+ coex_sta->bt_afh_map[9]
+ );
+ CL_PRINTF(cli_buf);
+ }
+
+ for (i = 0; i < BT_INFO_SRC_8822B_2ANT_MAX; i++) {
+ if (coex_sta->bt_info_c2h_cnt[i]) {
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)",
+ glbt_info_src_8822b_2ant[i],
+ coex_sta->bt_info_c2h[i][0],
+ coex_sta->bt_info_c2h[i][1],
+ coex_sta->bt_info_c2h[i][2],
+ coex_sta->bt_info_c2h[i][3],
+ coex_sta->bt_info_c2h[i][4],
+ coex_sta->bt_info_c2h[i][5],
+ coex_sta->bt_info_c2h[i][6],
+ coex_sta->bt_info_c2h_cnt[i]);
+ CL_PRINTF(cli_buf);
+ }
+ }
+
+ /* Sw mechanism */
+ if (btcoexist->manual_control)
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+ "============[mechanism] (before Manual)============");
+ else
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+ "============[Mechanism]============");
+
+ CL_PRINTF(cli_buf);
+
+
+ ps_tdma_case = coex_dm->cur_ps_tdma;
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %02x %02x %02x %02x %02x (case-%d, %s, %s)",
+ "TDMA",
+ coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],
+ coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],
+ coex_dm->ps_tdma_para[4], ps_tdma_case,
+ (coex_dm->cur_ps_tdma_on ? "TDMA On" : "TDMA Off"),
+ (coex_dm->is_switch_to_1dot5_ant ? "1.5Ant" : "2Ant"));
+ CL_PRINTF(cli_buf);
+
+ u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
+ u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
+ u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %d/ 0x%x/ 0x%x/ 0x%x",
+ "Table/0x6c0/0x6c4/0x6c8",
+ coex_sta->coex_table_type, u32tmp[0], u32tmp[1], u32tmp[2]);
+ CL_PRINTF(cli_buf);
+
+ u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
+ u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc);
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = 0x%x/ 0x%x/ 0x%04x",
+ "0x778/0x6cc/Scoreboard(W->B)",
+ u8tmp[0], u32tmp[0], coex_sta->score_board_WB);
+ CL_PRINTF(cli_buf);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d/ %d",
+ "AntDiv/BtCtrlLPS/LPRA/PsFail/g_busy",
+ ((board_info->ant_div_cfg) ? "On" : "Off"),
+ ((coex_sta->force_lps_ctrl) ? "On" : "Off"),
+ ((coex_dm->cur_low_penalty_ra) ? "On" : "Off"),
+ coex_sta->cnt_set_ps_state_fail,
+ coex_sta->gl_wifi_busy);
+ CL_PRINTF(cli_buf);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d",
+ "Null All/Retry/Ack/BT_Empty/BT_Late",
+ coex_sta->wl_fw_dbg_info[1],
+ coex_sta->wl_fw_dbg_info[2],
+ coex_sta->wl_fw_dbg_info[3],
+ coex_sta->wl_fw_dbg_info[4],
+ coex_sta->wl_fw_dbg_info[5]);
+ CL_PRINTF(cli_buf);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+ "WL_Pwr/ BT_Pwr", coex_dm->cur_fw_dac_swing_lvl,
+ coex_dm->cur_bt_dec_pwr_lvl);
+ CL_PRINTF(cli_buf);
+
+ u32tmp[0] = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
+ lte_coex_on = ((u32tmp[0] & BIT(7)) >> 7) ? TRUE : FALSE;
+
+ if (lte_coex_on) {
+
+ u32tmp[0] = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist,
+ 0xa0);
+ u32tmp[1] = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist,
+ 0xa4);
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
+ "LTE Coex Table W_L/B_L",
+ u32tmp[0] & 0xffff, u32tmp[1] & 0xffff);
+ CL_PRINTF(cli_buf);
+
+
+ u32tmp[0] = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist,
+ 0xa8);
+ u32tmp[1] = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist,
+ 0xac);
+ u32tmp[2] = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist,
+ 0xb0);
+ u32tmp[3] = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist,
+ 0xb4);
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+ "LTE Break Table W_L/B_L/L_W/L_B",
+ u32tmp[0] & 0xffff, u32tmp[1] & 0xffff,
+ u32tmp[2] & 0xffff, u32tmp[3] & 0xffff);
+ CL_PRINTF(cli_buf);
+
+ }
+
+ /* Hw setting */
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
+ "============[Hw setting]============");
+ CL_PRINTF(cli_buf);
+
+ u32tmp[0] = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, 0x38);
+ u32tmp[1] = halbtc8822b2ant_ltecoex_indirect_read_reg(btcoexist, 0x54);
+ u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s",
+ "LTE Coex/Path Owner",
+ ((lte_coex_on) ? "On" : "Off"),
+ ((u8tmp[0] & BIT(2)) ? "WL" : "BT"));
+ CL_PRINTF(cli_buf);
+
+ if (lte_coex_on) {
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %d/ %d/ %d/ %d",
+ "LTE 3Wire/OPMode/UART/UARTMode",
+ (int)((u32tmp[0] & BIT(6)) >> 6),
+ (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4),
+ (int)((u32tmp[0] & BIT(3)) >> 3),
+ (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0))));
+ CL_PRINTF(cli_buf);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+ "LTE_Busy/UART_Busy",
+ (int)((u32tmp[1] & BIT(1)) >> 1),
+ (int)(u32tmp[1] & BIT(0)));
+ CL_PRINTF(cli_buf);
+ }
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = %s (BB:%s)/ %s (BB:%s)/ %s (gnt_err = %d)",
+ "GNT_WL_Ctrl/GNT_BT_Ctrl/Dbg",
+ ((u32tmp[0] & BIT(12)) ? "SW" : "HW"),
+ ((u32tmp[0] & BIT(8)) ? "SW" : "HW"),
+ ((u32tmp[0] & BIT(14)) ? "SW" : "HW"),
+ ((u32tmp[0] & BIT(10)) ? "SW" : "HW"),
+ ((u8tmp[0] & BIT(3)) ? "On" : "Off"),
+ coex_sta->gnt_error_cnt);
+ CL_PRINTF(cli_buf);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+ "GNT_WL/GNT_BT",
+ (int)((u32tmp[1] & BIT(2)) >> 2),
+ (int)((u32tmp[1] & BIT(3)) >> 3));
+ CL_PRINTF(cli_buf);
+
+
+ u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xcb0);
+ u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xcb4);
+ u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xcba);
+ u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xcbd);
+ u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0xc58);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = 0x%04x/ 0x%04x/ 0x%02x/ 0x%02x 0x%02x %s",
+ "0xcb0/0xcb4/0xcb8[23:16]/0xcbd/0xc58",
+ u32tmp[0], u32tmp[1], u8tmp[0], u8tmp[1], u8tmp[2],
+ ((u8tmp[1] & 0x1) == 0x1 ? "(BT_WL5G)" : "(WL2G)"));
+ CL_PRINTF(cli_buf);
+
+ u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c);
+ u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0x64);
+ u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6);
+ u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+ "4c[24:23]/64[0]/4c6[4]/40[5]",
+ (int)(u32tmp[0] & (BIT(24) | BIT(23))) >> 23, u8tmp[2] & 0x1,
+ (int)((u8tmp[0] & BIT(4)) >> 4),
+ (int)((u8tmp[1] & BIT(5)) >> 5));
+ CL_PRINTF(cli_buf);
+
+ u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
+ u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
+ u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x953);
+ u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0xc50);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = 0x%x/ 0x%x/ %s/ 0x%x",
+ "0x550/0x522/4-RxAGC/0xc50",
+ u32tmp[0], u8tmp[0], (u8tmp[1] & 0x2) ? "On" : "Off", u8tmp[2]);
+ CL_PRINTF(cli_buf);
+
+ fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+ PHYDM_INFO_FA_OFDM);
+ fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+ PHYDM_INFO_FA_CCK);
+ cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+ PHYDM_INFO_CCA_OFDM);
+ cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist,
+ PHYDM_INFO_CCA_CCK);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
+ "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
+ "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA",
+ cca_cck, fa_cck, cca_ofdm, fa_ofdm);
+ CL_PRINTF(cli_buf);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d (Rx_rate Data/RTS= %d/%d)",
+ "CRC_OK CCK/11g/11n/11ac",
+ coex_sta->crc_ok_cck, coex_sta->crc_ok_11g,
+ coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht,
+ coex_sta->wl_rx_rate, coex_sta->wl_rts_rx_rate);
+ CL_PRINTF(cli_buf);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d",
+ "CRC_Err CCK/11g/11n/11ac",
+ coex_sta->crc_err_cck, coex_sta->crc_err_11g,
+ coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht);
+ CL_PRINTF(cli_buf);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %s/ %d",
+ "HiPr/ Locking/ warn/ Locked/ Noisy",
+ (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"),
+ (coex_sta->cck_lock ? "Yes" : "No"),
+ (coex_sta->cck_lock_warn ? "Yes" : "No"),
+ (coex_sta->cck_lock_ever ? "Yes" : "No"),
+ coex_sta->wl_noisy_level);
+ CL_PRINTF(cli_buf);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
+ "0x770(Hi-pri rx/tx)",
+ coex_sta->high_priority_rx, coex_sta->high_priority_tx);
+ CL_PRINTF(cli_buf);
+
+ CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s",
+ "0x774(Lo-pri rx/tx)",
+ coex_sta->low_priority_rx, coex_sta->low_priority_tx,
+ (bt_link_info->slave_role ? "(Slave!!)" : (
+ coex_sta->is_tdma_btautoslot_hang ? "(auto-slot hang!!)" : "")));
+ CL_PRINTF(cli_buf);
+
+ btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
+}
+
+
+void ex_halbtc8822b2ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type)
+{
+ if (btcoexist->manual_control || btcoexist->stop_coex_dm)
+ return;
+
+ if (BTC_IPS_ENTER == type) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], IPS ENTER notify\n");
+ BTC_TRACE(trace_buf);
+ coex_sta->under_ips = TRUE;
+ coex_sta->under_lps = FALSE;
+
+ halbtc8822b2ant_post_state_to_bt(btcoexist,
+ BT_8822B_2ANT_SCOREBOARD_ACTIVE |
+ BT_8822B_2ANT_SCOREBOARD_ONOFF |
+ BT_8822B_2ANT_SCOREBOARD_SCAN |
+ BT_8822B_2ANT_SCOREBOARD_UNDERTEST |
+ BT_8822B_2ANT_SCOREBOARD_RXGAIN,
+ FALSE);
+
+ halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+ FORCE_EXEC,
+ BT_8822B_2ANT_PHASE_WLAN_OFF);
+
+ halbtc8822b2ant_action_coex_all_off(btcoexist);
+ } else if (BTC_IPS_LEAVE == type) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], IPS LEAVE notify\n");
+ BTC_TRACE(trace_buf);
+ coex_sta->under_ips = FALSE;
+
+ halbtc8822b2ant_init_hw_config(btcoexist, FALSE);
+ halbtc8822b2ant_init_coex_dm(btcoexist);
+ halbtc8822b2ant_query_bt_info(btcoexist);
+ }
+}
+
+
+
+void ex_halbtc8822b2ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type)
+{
+ static boolean pre_force_lps_on = FALSE;
+
+ if (btcoexist->manual_control || btcoexist->stop_coex_dm)
+ return;
+
+ if (BTC_LPS_ENABLE == type) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], LPS ENABLE notify\n");
+ BTC_TRACE(trace_buf);
+ coex_sta->under_lps = TRUE;
+ coex_sta->under_ips = FALSE;
+
+ if (coex_sta->force_lps_ctrl) { /* LPS No-32K */
+ /* Write WL "Active" in Score-board for PS-TDMA */
+ pre_force_lps_on = TRUE;
+ halbtc8822b2ant_post_state_to_bt(btcoexist,
+ BT_8822B_2ANT_SCOREBOARD_ACTIVE, TRUE);
+
+ } else {
+ /* Write WL "Non-Active" in Score-board for Native-PS */
+ pre_force_lps_on = FALSE;
+ halbtc8822b2ant_post_state_to_bt(btcoexist,
+ BT_8822B_2ANT_SCOREBOARD_ACTIVE, FALSE);
+ halbtc8822b2ant_action_wifi_native_lps(btcoexist);
+ }
+
+ } else if (BTC_LPS_DISABLE == type) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], LPS DISABLE notify\n");
+ BTC_TRACE(trace_buf);
+ coex_sta->under_lps = FALSE;
+
+ halbtc8822b2ant_post_state_to_bt(btcoexist,
+ BT_8822B_2ANT_SCOREBOARD_ACTIVE, TRUE);
+
+ if ((!pre_force_lps_on) && (!coex_sta->force_lps_ctrl))
+ halbtc8822b2ant_query_bt_info(btcoexist);
+ }
+}
+
+void ex_halbtc8822b2ant_scan_notify(IN struct btc_coexist *btcoexist,
+ IN u8 type)
+{
+ boolean wifi_connected = FALSE;
+ boolean wifi_under_5g = FALSE;
+
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], SCAN notify()\n");
+ BTC_TRACE(trace_buf);
+
+ if (btcoexist->manual_control ||
+ btcoexist->stop_coex_dm)
+ return;
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected);
+
+ /* this can't be removed for RF off_on event, or BT would dis-connect */
+ if ((type == BTC_SCAN_START) || (type == BTC_SCAN_START_2G)) {
+
+ halbtc8822b2ant_post_state_to_bt(btcoexist,
+ BT_8822B_2ANT_SCOREBOARD_ACTIVE |
+ BT_8822B_2ANT_SCOREBOARD_SCAN |
+ BT_8822B_2ANT_SCOREBOARD_ONOFF,
+ TRUE);
+
+ halbtc8822b2ant_query_bt_info(btcoexist);
+ }
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+
+ if ((type == BTC_SCAN_START) && (wifi_under_5g)) {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], SCAN START notify (5G)\n");
+ BTC_TRACE(trace_buf);
+ halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+ FORCE_EXEC,
+ BT_8822B_2ANT_PHASE_5G_RUNTIME);
+
+ halbtc8822b2ant_run_coexist_mechanism(btcoexist);
+ } else if ((type == BTC_SCAN_START_2G) || (type == BTC_SCAN_START)) {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], SCAN START notify (2G)\n");
+ BTC_TRACE(trace_buf);
+
+ if (!wifi_connected)
+ coex_sta->wifi_is_high_pri_task = TRUE;
+
+ halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+ FORCE_EXEC,
+ BT_8822B_2ANT_PHASE_2G_RUNTIME);
+
+ halbtc8822b2ant_run_coexist_mechanism(btcoexist);
+
+ } else if (BTC_SCAN_FINISH == type) {
+
+ btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM,
+ &coex_sta->scan_ap_num);
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], SCAN FINISH notify (Scan-AP = %d)\n",
+ coex_sta->scan_ap_num);
+ BTC_TRACE(trace_buf);
+
+ coex_sta->wifi_is_high_pri_task = FALSE;
+
+ halbtc8822b2ant_run_coexist_mechanism(btcoexist);
+ }
+
+}
+
+
+void ex_halbtc8822b2ant_switchband_notify(IN struct btc_coexist *btcoexist,
+ IN u8 type)
+{
+ if (btcoexist->manual_control ||
+ btcoexist->stop_coex_dm)
+ return;
+ coex_sta->switch_band_notify_to = type;
+
+ if (type == BTC_SWITCH_TO_5G) {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], switchband_notify --- switch to 5G\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b2ant_run_coexist_mechanism(btcoexist);
+
+ } else if (type == BTC_SWITCH_TO_24G_NOFORSCAN) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ********** switchband_notify --- BTC_SWITCH_TO_2G (no for scan)\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b2ant_run_coexist_mechanism(btcoexist);
+
+ } else {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], switchband_notify --- switch to 2G\n");
+ BTC_TRACE(trace_buf);
+
+ ex_halbtc8822b2ant_scan_notify(btcoexist,
+ BTC_SCAN_START_2G);
+ }
+ coex_sta->switch_band_notify_to = BTC_NOT_SWITCH;
+}
+
+
+void ex_halbtc8822b2ant_connect_notify(IN struct btc_coexist *btcoexist,
+ IN u8 type)
+{
+
+ if (btcoexist->manual_control ||
+ btcoexist->stop_coex_dm)
+ return;
+
+ halbtc8822b2ant_post_state_to_bt(btcoexist,
+ BT_8822B_2ANT_SCOREBOARD_ACTIVE |
+ BT_8822B_2ANT_SCOREBOARD_SCAN |
+ BT_8822B_2ANT_SCOREBOARD_ONOFF,
+ TRUE);
+
+ if ((BTC_ASSOCIATE_5G_START == type) ||
+ (BTC_ASSOCIATE_5G_FINISH == type)) {
+
+ if (BTC_ASSOCIATE_5G_START == type)
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], connect_notify --- 5G start\n");
+ else
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], connect_notify --- 5G finish\n");
+
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+ FORCE_EXEC,
+ BT_8822B_2ANT_PHASE_5G_RUNTIME);
+
+ halbtc8822b2ant_run_coexist_mechanism(btcoexist);
+ } else if (type == BTC_ASSOCIATE_START) {
+
+ coex_sta->wifi_is_high_pri_task = TRUE;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], CONNECT START notify (2G)\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+ FORCE_EXEC,
+ BT_8822B_2ANT_PHASE_2G_RUNTIME);
+
+ halbtc8822b2ant_run_coexist_mechanism(btcoexist);
+
+ /* To keep TDMA case during connect process,
+ * to avoid changed by Btinfo and runcoexmechanism
+ */
+ coex_sta->freeze_coexrun_by_btinfo = TRUE;
+
+ coex_dm->arp_cnt = 0;
+
+ } else if (BTC_ASSOCIATE_FINISH == type) {
+
+ coex_sta->wifi_is_high_pri_task = FALSE;
+ coex_sta->freeze_coexrun_by_btinfo = FALSE;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], CONNECT FINISH notify (2G)\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b2ant_run_coexist_mechanism(btcoexist);
+ }
+}
+
+void ex_halbtc8822b2ant_media_status_notify(IN struct btc_coexist *btcoexist,
+ IN u8 type)
+{
+ boolean wifi_under_b_mode = FALSE, wifi_under_5g = FALSE;
+
+
+ if (btcoexist->manual_control ||
+ btcoexist->stop_coex_dm)
+ return;
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+
+ if (type == BTC_MEDIA_CONNECT) {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], MEDIA connect notify\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b2ant_post_state_to_bt(btcoexist,
+ BT_8822B_2ANT_SCOREBOARD_ACTIVE, TRUE);
+
+ if (wifi_under_5g) {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], WiFi is under 5G!!!\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+ FORCE_EXEC,
+ BT_8822B_2ANT_PHASE_5G_RUNTIME);
+
+ halbtc8822b2ant_run_coexist_mechanism(btcoexist);
+ } else {
+
+ halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+ FORCE_EXEC,
+ BT_8822B_2ANT_PHASE_2G_RUNTIME);
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE,
+ &wifi_under_b_mode);
+
+ /* Set CCK Tx/Rx high Pri except 11b mode */
+ if (wifi_under_b_mode) {
+ btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x00); /* CCK Tx */
+ btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x00); /* CCK Rx */
+ } else {
+
+ btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x00); /* CCK Tx */
+ btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x10); /* CCK Rx */
+ }
+
+ halbtc8822b2ant_run_coexist_mechanism(btcoexist);
+ }
+ } else {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], MEDIA disconnect notify\n");
+ BTC_TRACE(trace_buf);
+
+ btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */
+ btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */
+
+ halbtc8822b2ant_post_state_to_bt(btcoexist,
+ BT_8822B_2ANT_SCOREBOARD_ACTIVE, FALSE);
+
+ coex_sta->cck_lock_ever = FALSE;
+ coex_sta->cck_lock_warn = FALSE;
+ coex_sta->cck_lock = FALSE;
+
+ halbtc8822b2ant_run_coexist_mechanism(btcoexist);
+ }
+
+
+ halbtc8822b2ant_update_wifi_channel_info(btcoexist, type);
+}
+
+void ex_halbtc8822b2ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
+ IN u8 type)
+{
+ boolean under_4way = FALSE, wifi_under_5g = FALSE;
+
+ if (btcoexist->manual_control ||
+ btcoexist->stop_coex_dm)
+ return;
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+
+ if (wifi_under_5g) {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], WiFi is under 5G!!!\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b2ant_run_coexist_mechanism(btcoexist);
+ return;
+ }
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
+ &under_4way);
+
+ if (under_4way) {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], specific Packet ---- under_4way!!\n");
+ BTC_TRACE(trace_buf);
+
+ coex_sta->wifi_is_high_pri_task = TRUE;
+ coex_sta->specific_pkt_period_cnt = 2;
+
+ } else if (BTC_PACKET_ARP == type) {
+
+ coex_dm->arp_cnt++;
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], specific Packet ARP notify -cnt = %d\n",
+ coex_dm->arp_cnt);
+ BTC_TRACE(trace_buf);
+
+ } else {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n",
+ type);
+ BTC_TRACE(trace_buf);
+
+ coex_sta->wifi_is_high_pri_task = TRUE;
+ coex_sta->specific_pkt_period_cnt = 2;
+ }
+
+ if (coex_sta->wifi_is_high_pri_task) {
+ halbtc8822b2ant_post_state_to_bt(btcoexist,
+ BT_8822B_2ANT_SCOREBOARD_SCAN, TRUE);
+ halbtc8822b2ant_run_coexist_mechanism(btcoexist);
+ }
+
+}
+
+
+void ex_halbtc8822b2ant_bt_info_notify(IN struct btc_coexist *btcoexist,
+ IN u8 *tmp_buf, IN u8 length)
+{
+ u8 i, rsp_source = 0;
+ boolean wifi_connected = FALSE;
+ boolean wifi_scan = FALSE, wifi_link = FALSE, wifi_roam = FALSE,
+ wifi_busy = FALSE;
+ static boolean is_scoreboard_scan = FALSE;
+
+
+ rsp_source = tmp_buf[0] & 0xf;
+ if (rsp_source >= BT_INFO_SRC_8822B_2ANT_MAX)
+ rsp_source = BT_INFO_SRC_8822B_2ANT_WIFI_FW;
+ coex_sta->bt_info_c2h_cnt[rsp_source]++;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Bt_info[%d], len=%d, data=[", rsp_source,
+ length);
+ BTC_TRACE(trace_buf);
+
+ for (i = 0; i < length; i++) {
+ coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
+
+ if (i == length - 1) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n",
+ tmp_buf[i]);
+ BTC_TRACE(trace_buf);
+ } else {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ",
+ tmp_buf[i]);
+ BTC_TRACE(trace_buf);
+ }
+ }
+
+ coex_sta->bt_info = coex_sta->bt_info_c2h[rsp_source][1];
+ coex_sta->bt_info_ext = coex_sta->bt_info_c2h[rsp_source][4];
+ coex_sta->bt_info_ext2 = coex_sta->bt_info_c2h[rsp_source][5];
+
+ if (BT_INFO_SRC_8822B_2ANT_WIFI_FW != rsp_source) {
+
+ /* if 0xff, it means BT is under WHCK test */
+ coex_sta->bt_whck_test = ((coex_sta->bt_info == 0xff) ? TRUE :
+ FALSE);
+
+ coex_sta->bt_create_connection = ((
+ coex_sta->bt_info_c2h[rsp_source][2] & 0x80) ? TRUE :
+ FALSE);
+
+ /* unit: %, value-100 to translate to unit: dBm */
+ coex_sta->bt_rssi = coex_sta->bt_info_c2h[rsp_source][3] * 2 +
+ 10;
+
+ coex_sta->c2h_bt_remote_name_req = ((
+ coex_sta->bt_info_c2h[rsp_source][2] & 0x20) ? TRUE :
+ FALSE);
+
+ coex_sta->is_A2DP_3M = ((coex_sta->bt_info_c2h[rsp_source][2] &
+ 0x10) ? TRUE : FALSE);
+
+ coex_sta->acl_busy = ((coex_sta->bt_info_c2h[rsp_source][1] &
+ 0x8) ? TRUE : FALSE);
+
+ coex_sta->voice_over_HOGP = ((coex_sta->bt_info_ext & 0x10) ?
+ TRUE : FALSE);
+
+ coex_sta->c2h_bt_inquiry_page = ((coex_sta->bt_info &
+ BT_INFO_8822B_2ANT_B_INQ_PAGE) ? TRUE : FALSE);
+
+ coex_sta->a2dp_bit_pool = (((
+ coex_sta->bt_info_c2h[rsp_source][1] & 0x49) == 0x49) ?
+ (coex_sta->bt_info_c2h[rsp_source][6] & 0x7f) : 0);
+
+ coex_sta->is_bt_a2dp_sink = (coex_sta->bt_info_c2h[rsp_source][6] & 0x80) ?
+ TRUE : FALSE;
+
+ coex_sta->bt_retry_cnt = coex_sta->bt_info_c2h[rsp_source][2] &
+ 0xf;
+
+ coex_sta->is_autoslot = coex_sta->bt_info_ext2 & 0x8;
+
+ coex_sta->forbidden_slot = coex_sta->bt_info_ext2 & 0x7;
+
+ coex_sta->hid_busy_num = (coex_sta->bt_info_ext2 & 0x30) >> 4;
+
+ coex_sta->hid_pair_cnt = (coex_sta->bt_info_ext2 & 0xc0) >> 6;
+
+ coex_sta->is_bt_opp_exist = (coex_sta->bt_info_ext2 & 0x1) ? TRUE : FALSE;
+
+ if (coex_sta->bt_retry_cnt >= 1)
+ coex_sta->pop_event_cnt++;
+
+ if (coex_sta->c2h_bt_remote_name_req)
+ coex_sta->cnt_RemoteNameReq++;
+
+ if (coex_sta->bt_info_ext & BIT(1))
+ coex_sta->cnt_ReInit++;
+
+ if (coex_sta->bt_info_ext & BIT(2)) {
+ coex_sta->cnt_setupLink++;
+ coex_sta->is_setupLink = TRUE;
+ coex_sta->bt_relink_downcount = 2;
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Re-Link start in BT info!!\n");
+ BTC_TRACE(trace_buf);
+ }
+
+ if (coex_sta->bt_info_ext & BIT(3))
+ coex_sta->cnt_IgnWlanAct++;
+
+ if (coex_sta->bt_info_ext & BIT(6))
+ coex_sta->cnt_RoleSwitch++;
+
+ if (coex_sta->bt_info_ext & BIT(7))
+ coex_sta->is_bt_multi_link = TRUE;
+ else
+ coex_sta->is_bt_multi_link = FALSE;
+
+ if (coex_sta->bt_info_ext & BIT(0))
+ coex_sta->is_hid_rcu = TRUE;
+ else
+ coex_sta->is_hid_rcu = FALSE;
+
+ if (coex_sta->bt_info_ext & BIT(5))
+ coex_sta->is_ble_scan_en = TRUE;
+ else
+ coex_sta->is_ble_scan_en = FALSE;
+
+ if (coex_sta->bt_create_connection) {
+ coex_sta->cnt_Page++;
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY,
+ &wifi_busy);
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan);
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link);
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam);
+
+ if ((wifi_link) || (wifi_roam) || (wifi_scan) ||
+ (coex_sta->wifi_is_high_pri_task) || (wifi_busy)) {
+
+ is_scoreboard_scan = TRUE;
+ halbtc8822b2ant_post_state_to_bt(btcoexist,
+ BT_8822B_2ANT_SCOREBOARD_SCAN, TRUE);
+
+ } else
+ halbtc8822b2ant_post_state_to_bt(btcoexist,
+ BT_8822B_2ANT_SCOREBOARD_SCAN, FALSE);
+
+ } else {
+ if (is_scoreboard_scan) {
+ halbtc8822b2ant_post_state_to_bt(btcoexist,
+ BT_8822B_2ANT_SCOREBOARD_SCAN, FALSE);
+ is_scoreboard_scan = FALSE;
+ }
+ }
+
+ /* Here we need to resend some wifi info to BT */
+ /* because bt is reset and loss of the info. */
+
+ if ((!btcoexist->manual_control) &&
+ (!btcoexist->stop_coex_dm)) {
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+ &wifi_connected);
+
+ /* Re-Init */
+ if ((coex_sta->bt_info_ext & BIT(1))) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n");
+ BTC_TRACE(trace_buf);
+ if (wifi_connected)
+ halbtc8822b2ant_update_wifi_channel_info(
+ btcoexist, BTC_MEDIA_CONNECT);
+ else
+ halbtc8822b2ant_update_wifi_channel_info(
+ btcoexist,
+ BTC_MEDIA_DISCONNECT);
+ }
+
+
+ /* If Ignore_WLanAct && not SetUp_Link */
+ if ((coex_sta->bt_info_ext & BIT(3)) &&
+ (!(coex_sta->bt_info_ext & BIT(2))) &&
+ (!(coex_sta->bt_info_ext & BIT(6)))) {
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n");
+ BTC_TRACE(trace_buf);
+ halbtc8822b2ant_ignore_wlan_act(btcoexist,
+ FORCE_EXEC, FALSE);
+ } else {
+ if (coex_sta->bt_info_ext & BIT(2)) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT ignore Wlan active because Re-link!!\n");
+ BTC_TRACE(trace_buf);
+ } else if (coex_sta->bt_info_ext & BIT(6)) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], BT ignore Wlan active because Role-Switch!!\n");
+ BTC_TRACE(trace_buf);
+ }
+ }
+ }
+
+ }
+
+ halbtc8822b2ant_update_bt_link_info(btcoexist);
+
+ halbtc8822b2ant_run_coexist_mechanism(btcoexist);
+}
+
+void ex_halbtc8822b2ant_wl_fwdbginfo_notify(IN struct btc_coexist *btcoexist,
+ IN u8 *tmp_buf, IN u8 length)
+{
+ u8 i = 0;
+ static u8 tmp_buf_pre[10] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], WiFi Fw Dbg info = %d %d %d %d %d %d (len = %d)\n",
+ tmp_buf[0], tmp_buf[1],
+ tmp_buf[2], tmp_buf[3],
+ tmp_buf[4], tmp_buf[5], length);
+ BTC_TRACE(trace_buf);
+
+ if (tmp_buf[0] == 0x8) {
+ for (i = 1; i <= 5; i++) {
+ coex_sta->wl_fw_dbg_info[i] =
+ (tmp_buf[i] >= tmp_buf_pre[i]) ?
+ (tmp_buf[i] - tmp_buf_pre[i]) :
+ (255 - tmp_buf_pre[i] + tmp_buf[i]);
+
+ tmp_buf_pre[i] = tmp_buf[i];
+ }
+ }
+}
+
+
+void ex_halbtc8822b2ant_rx_rate_change_notify(IN struct btc_coexist *btcoexist,
+ IN BOOLEAN is_data_frame, IN u8 btc_rate_id)
+{
+ BOOLEAN wifi_connected = FALSE;
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
+ &wifi_connected);
+
+ if (is_data_frame) {
+ coex_sta->wl_rx_rate = btc_rate_id;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], rx_rate_change_notify data rate id = %d, RTS_Rate = %d\n",
+ coex_sta->wl_rx_rate, coex_sta->wl_rts_rx_rate);
+ BTC_TRACE(trace_buf);
+ } else {
+ coex_sta->wl_rts_rx_rate = btc_rate_id;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], rts_rate_change_notify RTS rate id = %d, RTS_Rate = %d\n",
+ coex_sta->wl_rts_rx_rate, coex_sta->wl_rts_rx_rate);
+ BTC_TRACE(trace_buf);
+ }
+
+ if ((wifi_connected) &&
+ ((coex_dm->bt_status == BT_8822B_2ANT_BT_STATUS_ACL_BUSY) ||
+ (coex_dm->bt_status == BT_8822B_2ANT_BT_STATUS_ACL_SCO_BUSY) ||
+ (coex_dm->bt_status == BT_8822B_2ANT_BT_STATUS_SCO_BUSY))) {
+
+ if ((coex_sta->wl_rx_rate == BTC_CCK_5_5) ||
+ (coex_sta->wl_rx_rate == BTC_OFDM_6) ||
+ (coex_sta->wl_rx_rate == BTC_MCS_0)) {
+
+ coex_sta->cck_lock_warn = TRUE;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], cck lock warning...\n");
+ BTC_TRACE(trace_buf);
+ } else if ((coex_sta->wl_rx_rate == BTC_CCK_1) ||
+ (coex_sta->wl_rx_rate == BTC_CCK_2) ||
+ (coex_sta->wl_rts_rx_rate == BTC_CCK_1) ||
+ (coex_sta->wl_rts_rx_rate == BTC_CCK_2)) {
+
+ coex_sta->cck_lock = TRUE;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], cck locking...\n");
+ BTC_TRACE(trace_buf);
+ } else {
+ coex_sta->cck_lock_warn = FALSE;
+ coex_sta->cck_lock = FALSE;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], cck unlock...\n");
+ BTC_TRACE(trace_buf);
+ }
+ } else {
+ if ((coex_dm->bt_status ==
+ BT_8822B_2ANT_BT_STATUS_CONNECTED_IDLE) ||
+ (coex_dm->bt_status ==
+ BT_8822B_2ANT_BT_STATUS_NON_CONNECTED_IDLE)) {
+ coex_sta->cck_lock_warn = FALSE;
+ coex_sta->cck_lock = FALSE;
+ }
+ }
+
+}
+
+
+void ex_halbtc8822b2ant_rf_status_notify(IN struct btc_coexist *btcoexist,
+ IN u8 type)
+{
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n");
+ BTC_TRACE(trace_buf);
+
+ if (BTC_RF_ON == type) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], RF is turned ON!!\n");
+ BTC_TRACE(trace_buf);
+
+ btcoexist->stop_coex_dm = FALSE;
+ coex_sta->is_rf_state_off = FALSE;
+#if 0
+ halbtc8822b2ant_post_state_to_bt(btcoexist,
+ BT_8822B_2ANT_SCOREBOARD_ACTIVE, TRUE);
+ halbtc8822b2ant_post_state_to_bt(btcoexist,
+ BT_8822B_2ANT_SCOREBOARD_ONOFF, TRUE);
+#endif
+ } else if (BTC_RF_OFF == type) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], RF is turned OFF!!\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+ FORCE_EXEC,
+ BT_8822B_2ANT_PHASE_WLAN_OFF);
+
+ halbtc8822b2ant_action_coex_all_off(btcoexist);
+
+ halbtc8822b2ant_post_state_to_bt(btcoexist,
+ BT_8822B_2ANT_SCOREBOARD_ACTIVE |
+ BT_8822B_2ANT_SCOREBOARD_ONOFF |
+ BT_8822B_2ANT_SCOREBOARD_SCAN |
+ BT_8822B_2ANT_SCOREBOARD_UNDERTEST |
+ BT_8822B_2ANT_SCOREBOARD_RXGAIN,
+ FALSE);
+
+ btcoexist->stop_coex_dm = TRUE;
+ coex_sta->is_rf_state_off = TRUE;
+ }
+}
+
+void ex_halbtc8822b2ant_halt_notify(IN struct btc_coexist *btcoexist)
+{
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n");
+ BTC_TRACE(trace_buf);
+
+ halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC,
+ BT_8822B_2ANT_PHASE_WLAN_OFF);
+
+ ex_halbtc8822b2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
+
+ halbtc8822b2ant_post_state_to_bt(btcoexist,
+ BT_8822B_2ANT_SCOREBOARD_ACTIVE |
+ BT_8822B_2ANT_SCOREBOARD_ONOFF |
+ BT_8822B_2ANT_SCOREBOARD_SCAN |
+ BT_8822B_2ANT_SCOREBOARD_UNDERTEST |
+ BT_8822B_2ANT_SCOREBOARD_RXGAIN,
+ FALSE);
+
+ btcoexist->stop_coex_dm = TRUE;
+}
+
+void ex_halbtc8822b2ant_pnp_notify(IN struct btc_coexist *btcoexist,
+ IN u8 pnp_state)
+{
+ boolean wifi_under_5g = FALSE;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n");
+ BTC_TRACE(trace_buf);
+
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
+
+ if ((BTC_WIFI_PNP_SLEEP == pnp_state) ||
+ (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state)) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Pnp notify to SLEEP\n");
+ BTC_TRACE(trace_buf);
+
+ /* Sinda 20150819, workaround for driver skip leave IPS/LPS to
+ * speed up sleep time.
+ * Driver do not leave IPS/LPS when driver is going to sleep,
+ * so BTCoexistence think wifi is still under IPS/LPS.
+ * BT should clear UnderIPS/UnderLPS state to avoid mismatch
+ * state after wakeup.
+ */
+ coex_sta->under_ips = FALSE;
+ coex_sta->under_lps = FALSE;
+
+ halbtc8822b2ant_post_state_to_bt(btcoexist,
+ BT_8822B_2ANT_SCOREBOARD_ACTIVE |
+ BT_8822B_2ANT_SCOREBOARD_ONOFF |
+ BT_8822B_2ANT_SCOREBOARD_SCAN |
+ BT_8822B_2ANT_SCOREBOARD_UNDERTEST |
+ BT_8822B_2ANT_SCOREBOARD_RXGAIN,
+ FALSE);
+
+ if (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state) {
+
+ if (wifi_under_5g)
+ halbtc8822b2ant_set_ant_path(btcoexist,
+ BTC_ANT_PATH_AUTO, FORCE_EXEC,
+ BT_8822B_2ANT_PHASE_5G_RUNTIME);
+ else
+ halbtc8822b2ant_set_ant_path(btcoexist,
+ BTC_ANT_PATH_AUTO, FORCE_EXEC,
+ BT_8822B_2ANT_PHASE_2G_RUNTIME);
+ } else {
+
+ halbtc8822b2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO,
+ FORCE_EXEC,
+ BT_8822B_2ANT_PHASE_WLAN_OFF);
+ }
+
+ btcoexist->stop_coex_dm = TRUE;
+ } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) {
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], Pnp notify to WAKE UP\n");
+ BTC_TRACE(trace_buf);
+#if 0
+ halbtc8822b2ant_post_state_to_bt(btcoexist,
+ BT_8822B_2ANT_SCOREBOARD_ACTIVE, TRUE);
+ halbtc8822b2ant_post_state_to_bt(btcoexist,
+ BT_8822B_2ANT_SCOREBOARD_ONOFF, TRUE);
+#endif
+ }
+}
+
+void ex_halbtc8822b2ant_periodical(IN struct btc_coexist *btcoexist)
+{
+ boolean wifi_busy = FALSE;
+ u16 bt_scoreboard_val = 0;
+ boolean bt_relink_finish = FALSE;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ************* Periodical *************\n");
+ BTC_TRACE(trace_buf);
+
+#if (BT_AUTO_REPORT_ONLY_8822B_2ANT == 0)
+ halbtc8822b2ant_query_bt_info(btcoexist);
+#endif
+
+ halbtc8822b2ant_monitor_bt_ctr(btcoexist);
+ halbtc8822b2ant_monitor_wifi_ctr(btcoexist);
+ halbtc8822b2ant_monitor_bt_enable_disable(btcoexist);
+
+#if 0
+ btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
+ halbtc8822b2ant_read_score_board(btcoexist, &bt_scoreboard_val);
+
+ if (wifi_busy) {
+ halbtc8822b2ant_post_state_to_bt(btcoexist,
+ BT_8822B_2ANT_SCOREBOARD_UNDERTEST, TRUE);
+ /*for bt lps32 clock offset*/
+ if (bt_scoreboard_val & BIT(6))
+ halbtc8822b2ant_query_bt_info(btcoexist);
+ } else {
+ halbtc8822b2ant_post_state_to_bt(btcoexist,
+ BT_8822B_2ANT_SCOREBOARD_UNDERTEST, FALSE);
+#if 0
+ halbtc8822b2ant_post_state_to_bt(btcoexist,
+ BT_8822B_2ANT_SCOREBOARD_WLBUSY,
+ FALSE);
+#endif
+ }
+#endif
+
+ if (coex_sta->bt_relink_downcount != 0) {
+ coex_sta->bt_relink_downcount--;
+
+ if (coex_sta->bt_relink_downcount == 0) {
+ coex_sta->is_setupLink = FALSE;
+ bt_relink_finish = TRUE;
+ }
+ }
+
+ /* for 4-way, DHCP, EAPOL packet */
+ if (coex_sta->specific_pkt_period_cnt > 0) {
+
+ coex_sta->specific_pkt_period_cnt--;
+
+ if ((coex_sta->specific_pkt_period_cnt == 0) &&
+ (coex_sta->wifi_is_high_pri_task))
+ coex_sta->wifi_is_high_pri_task = FALSE;
+
+ BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE,
+ "[BTCoex], ***************** Hi-Pri Task = %s*****************\n",
+ (coex_sta->wifi_is_high_pri_task ? "Yes" :
+ "No"));
+ BTC_TRACE(trace_buf);
+
+ }
+
+ if (halbtc8822b2ant_is_wifibt_status_changed(btcoexist) || (bt_relink_finish)
+ || (coex_sta->is_set_ps_state_fail))
+ halbtc8822b2ant_run_coexist_mechanism(btcoexist);
+}
+
+void ex_halbtc8822b2ant_antenna_detection(IN struct btc_coexist *btcoexist,
+ IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds)
+{
+
+}
+
+
+void ex_halbtc8822b2ant_display_ant_detection(IN struct btc_coexist *btcoexist)
+{
+}
+
+
+#endif
+
+#endif /* #if (RTL8822B_SUPPORT == 1) */
diff --git a/hal/btc/halbtc8822b2ant.h b/hal/btc/halbtc8822b2ant.h
new file mode 100644
index 0000000..acbb959
--- /dev/null
+++ b/hal/btc/halbtc8822b2ant.h
@@ -0,0 +1,572 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#if (BT_SUPPORT == 1 && COEX_SUPPORT == 1)
+
+#if (RTL8822B_SUPPORT == 1)
+
+/* *******************************************
+ * The following is for 8822B 2Ant BT Co-exist definition
+ * ******************************************* */
+#define BT_8822B_2ANT_COEX_DBG 0
+#define BT_AUTO_REPORT_ONLY_8822B_2ANT 1
+
+
+
+
+#define BT_INFO_8822B_2ANT_B_FTP BIT(7)
+#define BT_INFO_8822B_2ANT_B_A2DP BIT(6)
+#define BT_INFO_8822B_2ANT_B_HID BIT(5)
+#define BT_INFO_8822B_2ANT_B_SCO_BUSY BIT(4)
+#define BT_INFO_8822B_2ANT_B_ACL_BUSY BIT(3)
+#define BT_INFO_8822B_2ANT_B_INQ_PAGE BIT(2)
+#define BT_INFO_8822B_2ANT_B_SCO_ESCO BIT(1)
+#define BT_INFO_8822B_2ANT_B_CONNECTION BIT(0)
+
+#define BTC_RSSI_COEX_THRESH_TOL_8822B_2ANT 2
+
+
+/* unit: % WiFi RSSI Threshold for 2-Ant free-run/2-Ant TDMA translation.
+ * (default = 42)
+ */
+#define BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 25
+/* unit: % BT RSSI Threshold for 2-Ant free-run/2-Ant TDMA translation.
+ * (default = 46)
+ */
+#define BT_8822B_2ANT_BT_RSSI_COEXSWITCH_THRES1 22
+/* unit: % WiFi RSSI Threshold for 1-Ant TDMA/1-Ant PS-TDMA translation.
+ * (default = 42)
+ */
+#define BT_8822B_2ANT_WIFI_RSSI_COEXSWITCH_THRES2 25
+/* unit: % BT RSSI Threshold for 1-Ant TDMA/1-Ant PS-TDMA translation.
+ * (default = 46)
+ */
+#define BT_8822B_2ANT_BT_RSSI_COEXSWITCH_THRES2 22
+
+#define BT_8822B_2ANT_DEFAULT_ISOLATION 25 /* unit: dB */
+#define BT_8822B_2ANT_WIFI_MAX_TX_POWER 15 /* unit: dBm */
+#define BT_8822B_2ANT_BT_MAX_TX_POWER 3 /* unit: dBm */
+#define BT_8822B_2ANT_WIFI_SIR_THRES1 -15 /* unit: dB */
+#define BT_8822B_2ANT_WIFI_SIR_THRES2 -30 /* unit: dB */
+#define BT_8822B_2ANT_BT_SIR_THRES1 -15 /* unit: dB */
+#define BT_8822B_2ANT_BT_SIR_THRES2 -30 /* unit: dB */
+
+
+/* for Antenna detection */
+#define BT_8822B_2ANT_ANTDET_PSDTHRES_BACKGROUND 50
+#define BT_8822B_2ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION 70
+#define BT_8822B_2ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION 52
+#define BT_8822B_2ANT_ANTDET_PSDTHRES_1ANT 40
+#define BT_8822B_2ANT_ANTDET_RETRY_INTERVAL 10 /* retry timer if ant det is fail, unit: second */
+#define BT_8822B_2ANT_ANTDET_SWEEPPOINT_DELAY 60000
+#define BT_8822B_2ANT_ANTDET_ENABLE 0
+#define BT_8822B_2ANT_ANTDET_BTTXTIME 100
+#define BT_8822B_2ANT_ANTDET_BTTXCHANNEL 39
+#define BT_8822B_2ANT_ANTDET_PSD_SWWEEPCOUNT 50
+
+
+#define BT_8822B_2ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT 30000
+
+enum bt_8822b_2ant_signal_state {
+ BT_8822B_2ANT_SIG_STA_SET_TO_LOW = 0x0,
+ BT_8822B_2ANT_SIG_STA_SET_BY_HW = 0x0,
+ BT_8822B_2ANT_SIG_STA_SET_TO_HIGH = 0x1,
+ BT_8822B_2ANT_SIG_STA_MAX
+};
+
+enum bt_8822b_2ant_path_ctrl_owner {
+ BT_8822B_2ANT_PCO_BTSIDE = 0x0,
+ BT_8822B_2ANT_PCO_WLSIDE = 0x1,
+ BT_8822B_2ANT_PCO_MAX
+};
+
+enum bt_8822b_2ant_gnt_ctrl_type {
+ BT_8822B_2ANT_GNT_TYPE_CTRL_BY_PTA = 0x0,
+ BT_8822B_2ANT_GNT_TYPE_CTRL_BY_SW = 0x1,
+ BT_8822B_2ANT_GNT_TYPE_MAX
+};
+
+enum bt_8822b_2ant_gnt_ctrl_block {
+ BT_8822B_2ANT_GNT_BLOCK_RFC_BB = 0x0,
+ BT_8822B_2ANT_GNT_BLOCK_RFC = 0x1,
+ BT_8822B_2ANT_GNT_BLOCK_BB = 0x2,
+ BT_8822B_2ANT_GNT_BLOCK_MAX
+};
+
+enum bt_8822b_2ant_lte_coex_table_type {
+ BT_8822B_2ANT_CTT_WL_VS_LTE = 0x0,
+ BT_8822B_2ANT_CTT_BT_VS_LTE = 0x1,
+ BT_8822B_2ANT_CTT_MAX
+};
+
+enum bt_8822b_2ant_lte_break_table_type {
+ BT_8822B_2ANT_LBTT_WL_BREAK_LTE = 0x0,
+ BT_8822B_2ANT_LBTT_BT_BREAK_LTE = 0x1,
+ BT_8822B_2ANT_LBTT_LTE_BREAK_WL = 0x2,
+ BT_8822B_2ANT_LBTT_LTE_BREAK_BT = 0x3,
+ BT_8822B_2ANT_LBTT_MAX
+};
+
+enum bt_info_src_8822b_2ant {
+ BT_INFO_SRC_8822B_2ANT_WIFI_FW = 0x0,
+ BT_INFO_SRC_8822B_2ANT_BT_RSP = 0x1,
+ BT_INFO_SRC_8822B_2ANT_BT_ACTIVE_SEND = 0x2,
+ BT_INFO_SRC_8822B_2ANT_MAX
+};
+
+enum bt_8822b_2ant_bt_status {
+ BT_8822B_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
+ BT_8822B_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
+ BT_8822B_2ANT_BT_STATUS_INQ_PAGE = 0x2,
+ BT_8822B_2ANT_BT_STATUS_ACL_BUSY = 0x3,
+ BT_8822B_2ANT_BT_STATUS_SCO_BUSY = 0x4,
+ BT_8822B_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
+ BT_8822B_2ANT_BT_STATUS_MAX
+};
+
+enum bt_8822b_2ant_coex_algo {
+ BT_8822B_2ANT_COEX_ALGO_UNDEFINED = 0x0,
+ BT_8822B_2ANT_COEX_ALGO_SCO = 0x1,
+ BT_8822B_2ANT_COEX_ALGO_HID = 0x2,
+ BT_8822B_2ANT_COEX_ALGO_A2DP = 0x3,
+ BT_8822B_2ANT_COEX_ALGO_A2DP_PANHS = 0x4,
+ BT_8822B_2ANT_COEX_ALGO_PANEDR = 0x5,
+ BT_8822B_2ANT_COEX_ALGO_PANHS = 0x6,
+ BT_8822B_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
+ BT_8822B_2ANT_COEX_ALGO_PANEDR_HID = 0x8,
+ BT_8822B_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
+ BT_8822B_2ANT_COEX_ALGO_HID_A2DP = 0xa,
+ BT_8822B_2ANT_COEX_ALGO_NOPROFILEBUSY = 0xb,
+ BT_8822B_2ANT_COEX_ALGO_A2DPSINK = 0xc,
+ BT_8822B_2ANT_COEX_ALGO_MAX
+};
+
+enum bt_8822b_2ant_ext_ant_switch_type {
+ BT_8822B_2ANT_EXT_ANT_SWITCH_USE_DPDT = 0x0,
+ BT_8822B_2ANT_EXT_ANT_SWITCH_USE_SPDT = 0x1,
+ BT_8822B_2ANT_EXT_ANT_SWITCH_NONE = 0x2,
+ BT_8822B_2ANT_EXT_ANT_SWITCH_MAX
+};
+
+enum bt_8822b_2ant_ext_ant_switch_ctrl_type {
+ BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW = 0x0,
+ BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_PTA = 0x1,
+ BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV = 0x2,
+ BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_MAC = 0x3,
+ BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_BY_BT = 0x4,
+ BT_8822B_2ANT_EXT_ANT_SWITCH_CTRL_MAX
+};
+
+enum bt_8822b_2ant_ext_ant_switch_pos_type {
+ BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_BT = 0x0,
+ BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_WLG = 0x1,
+ BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_WLA = 0x2,
+ BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_NOCARE = 0x3,
+ BT_8822B_2ANT_EXT_ANT_SWITCH_MAIN_TO_MAX
+};
+
+enum bt_8822b_2ant_ext_band_switch_pos_type {
+ BT_8822B_2ANT_EXT_BAND_SWITCH_TO_WLG = 0x0,
+ BT_8822B_2ANT_EXT_BAND_SWITCH_TO_WLA = 0x1,
+ BT_8822B_2ANT_EXT_BAND_SWITCH_TO_MAX
+};
+
+enum bt_8822b_2ant_int_block {
+ BT_8822B_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_BTG = 0x0,
+ BT_8822B_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_WLAG = 0x1,
+ BT_8822B_2ANT_INT_BLOCK_SWITCH_TO_WLA_OF_WLAG = 0x2,
+ BT_8822B_2ANT_INT_BLOCK_SWITCH_TO_MAX
+};
+
+enum bt_8822b_2ant_phase {
+ BT_8822B_2ANT_PHASE_COEX_INIT = 0x0,
+ BT_8822B_2ANT_PHASE_WLANONLY_INIT = 0x1,
+ BT_8822B_2ANT_PHASE_WLAN_OFF = 0x2,
+ BT_8822B_2ANT_PHASE_2G_RUNTIME = 0x3,
+ BT_8822B_2ANT_PHASE_5G_RUNTIME = 0x4,
+ BT_8822B_2ANT_PHASE_BTMPMODE = 0x5,
+ BT_8822B_2ANT_PHASE_ANTENNA_DET = 0x6,
+ BT_8822B_2ANT_PHASE_COEX_POWERON = 0x7,
+ BT_8822B_2ANT_PHASE_2G_RUNTIME_CONCURRENT = 0x8,
+ BT_8822B_2ANT_PHASE_2G_FREERUN = 0x9,
+ BT_8822B_2ANT_PHASE_MAX
+};
+
+/*ADD SCOREBOARD TO FIX BT LPS 32K ISSUE WHILE WL BUSY*/
+
+enum bt_8822b_2ant_Scoreboard {
+ BT_8822B_2ANT_SCOREBOARD_ACTIVE = BIT(0),
+ BT_8822B_2ANT_SCOREBOARD_ONOFF = BIT(1),
+ BT_8822B_2ANT_SCOREBOARD_SCAN = BIT(2),
+ BT_8822B_2ANT_SCOREBOARD_UNDERTEST = BIT(3),
+ BT_8822B_2ANT_SCOREBOARD_RXGAIN = BIT(4),
+ BT_8822B_2ANT_SCOREBOARD_WLBUSY = BIT(6),
+ BT_8822B_2ANT_SCOREBOARD_EXTFEM = BIT(8),
+ BT_8822B_2ANT_SCOREBOARD_BTCQDDR = BIT(10)
+};
+
+
+
+
+
+struct coex_dm_8822b_2ant {
+ /* hw setting */
+ u32 pre_ant_pos_type;
+ u32 cur_ant_pos_type;
+ /* fw mechanism */
+ u8 pre_bt_dec_pwr_lvl;
+ u8 cur_bt_dec_pwr_lvl;
+ u8 pre_fw_dac_swing_lvl;
+ u8 cur_fw_dac_swing_lvl;
+ boolean cur_ignore_wlan_act;
+ boolean pre_ignore_wlan_act;
+ u8 pre_ps_tdma;
+ u8 cur_ps_tdma;
+ u8 ps_tdma_para[5];
+ u8 ps_tdma_du_adj_type;
+ boolean reset_tdma_adjust;
+ boolean pre_ps_tdma_on;
+ boolean cur_ps_tdma_on;
+ boolean pre_bt_auto_report;
+ boolean cur_bt_auto_report;
+
+ /* sw mechanism */
+ boolean pre_rf_rx_lpf_shrink;
+ boolean cur_rf_rx_lpf_shrink;
+ u32 bt_rf_0x1e_backup;
+ boolean pre_low_penalty_ra;
+ boolean cur_low_penalty_ra;
+ boolean pre_dac_swing_on;
+ u32 pre_dac_swing_lvl;
+ boolean cur_dac_swing_on;
+ u32 cur_dac_swing_lvl;
+ boolean pre_adc_back_off;
+ boolean cur_adc_back_off;
+ boolean pre_agc_table_en;
+ boolean cur_agc_table_en;
+ u32 pre_val0x6c0;
+ u32 cur_val0x6c0;
+ u32 pre_val0x6c4;
+ u32 cur_val0x6c4;
+ u32 pre_val0x6c8;
+ u32 cur_val0x6c8;
+ u8 pre_val0x6cc;
+ u8 cur_val0x6cc;
+ boolean limited_dig;
+
+ /* algorithm related */
+ u8 pre_algorithm;
+ u8 cur_algorithm;
+ u8 bt_status;
+ u8 wifi_chnl_info[3];
+
+ boolean need_recover0x948;
+ u32 backup0x948;
+
+ u8 pre_lps;
+ u8 cur_lps;
+ u8 pre_rpwm;
+ u8 cur_rpwm;
+
+ boolean is_switch_to_1dot5_ant;
+ u8 switch_thres_offset;
+ u32 arp_cnt;
+
+ u32 pre_ext_ant_switch_status;
+ u32 cur_ext_ant_switch_status;
+
+ u8 pre_ext_band_switch_status;
+ u8 cur_ext_band_switch_status;
+
+ u8 pre_int_block_status;
+ u8 cur_int_block_status;
+};
+
+
+struct coex_sta_8822b_2ant {
+ boolean bt_disabled;
+ boolean bt_link_exist;
+ boolean sco_exist;
+ boolean a2dp_exist;
+ boolean hid_exist;
+ boolean pan_exist;
+
+ boolean under_lps;
+ boolean under_ips;
+ u32 high_priority_tx;
+ u32 high_priority_rx;
+ u32 low_priority_tx;
+ u32 low_priority_rx;
+ boolean is_hiPri_rx_overhead;
+ u8 bt_rssi;
+ u8 pre_bt_rssi_state;
+ u8 pre_wifi_rssi_state[4];
+ u8 bt_info_c2h[BT_INFO_SRC_8822B_2ANT_MAX][10];
+ u32 bt_info_c2h_cnt[BT_INFO_SRC_8822B_2ANT_MAX];
+ boolean bt_whck_test;
+ boolean c2h_bt_inquiry_page;
+ boolean c2h_bt_remote_name_req;
+
+ u8 bt_info_ext;
+ u8 bt_info_ext2;
+ u32 pop_event_cnt;
+ u8 scan_ap_num;
+ u8 bt_retry_cnt;
+
+ u32 crc_ok_cck;
+ u32 crc_ok_11g;
+ u32 crc_ok_11n;
+ u32 crc_ok_11n_vht;
+
+ u32 crc_err_cck;
+ u32 crc_err_11g;
+ u32 crc_err_11n;
+ u32 crc_err_11n_vht;
+
+ u32 acc_crc_ratio;
+ u32 now_crc_ratio;
+
+ boolean cck_lock;
+ boolean cck_lock_ever;
+ boolean cck_lock_warn;
+
+ u8 coex_table_type;
+ boolean force_lps_ctrl;
+
+ u8 dis_ver_info_cnt;
+
+ u8 a2dp_bit_pool;
+ u8 cut_version;
+
+ boolean concurrent_rx_mode_on;
+
+ u16 score_board;
+ u8 isolation_btween_wb; /* 0~ 50 */
+ u8 wifi_coex_thres;
+ u8 bt_coex_thres;
+ u8 wifi_coex_thres2;
+ u8 bt_coex_thres2;
+
+ u8 num_of_profile;
+ boolean acl_busy;
+ boolean bt_create_connection;
+ boolean wifi_is_high_pri_task;
+ u32 specific_pkt_period_cnt;
+ u32 bt_coex_supported_feature;
+ u32 bt_coex_supported_version;
+
+ u8 bt_ble_scan_type;
+ u32 bt_ble_scan_para[3];
+
+ boolean run_time_state;
+ boolean freeze_coexrun_by_btinfo;
+
+ boolean is_A2DP_3M;
+ boolean voice_over_HOGP;
+ u8 bt_info;
+ boolean is_autoslot;
+ u8 forbidden_slot;
+ u8 hid_busy_num;
+ u8 hid_pair_cnt;
+
+ u32 cnt_RemoteNameReq;
+ u32 cnt_setupLink;
+ u32 cnt_ReInit;
+ u32 cnt_IgnWlanAct;
+ u32 cnt_Page;
+ u32 cnt_RoleSwitch;
+
+ u16 bt_reg_vendor_ac;
+ u16 bt_reg_vendor_ae;
+
+ boolean is_setupLink;
+ u8 wl_noisy_level;
+ u32 gnt_error_cnt;
+
+ u8 bt_afh_map[10];
+ u8 bt_relink_downcount;
+ boolean is_tdma_btautoslot;
+ boolean is_tdma_btautoslot_hang;
+
+ boolean is_eSCO_mode;
+ u8 switch_band_notify_to;
+ boolean is_rf_state_off;
+
+ boolean is_hid_low_pri_tx_overhead;
+ boolean is_bt_multi_link;
+ boolean is_bt_a2dp_sink;
+
+ boolean is_set_ps_state_fail;
+ u8 cnt_set_ps_state_fail;
+
+ u8 wl_fw_dbg_info[10];
+ u8 wl_rx_rate;
+ u8 wl_rts_rx_rate;
+ u8 wl_center_channel;
+
+ boolean is_2g_freerun;
+
+ u16 score_board_WB;
+ boolean is_hid_rcu;
+ u16 legacy_forbidden_slot;
+ u16 le_forbidden_slot;
+ u8 bt_a2dp_vendor_id;
+ u32 bt_a2dp_device_name;
+ boolean is_ble_scan_en;
+
+ boolean is_bt_opp_exist;
+ boolean gl_wifi_busy;
+};
+
+
+#define BT_8822B_2ANT_EXT_BAND_SWITCH_USE_DPDT 0
+#define BT_8822B_2ANT_EXT_BAND_SWITCH_USE_SPDT 1
+
+
+struct rfe_type_8822b_2ant {
+
+ u8 rfe_module_type;
+ boolean ext_ant_switch_exist;
+ u8 ext_ant_switch_type; /* 0:DPDT, 1:SPDT */
+ /* iF 0: DPDT_P=0, DPDT_N=1 => BTG to Main, WL_A+G to Aux */
+ u8 ext_ant_switch_ctrl_polarity;
+
+ boolean ext_band_switch_exist;
+ u8 ext_band_switch_type; /* 0:DPDT, 1:SPDT */
+ u8 ext_band_switch_ctrl_polarity;
+
+ /* If true: WLG at BTG, If false: WLG at WLAG */
+ boolean wlg_Locate_at_btg;
+
+ boolean ext_ant_switch_diversity; /* If diversity on */
+};
+
+#define BT_8822B_2ANT_ANTDET_PSD_POINTS 256 /* MAX:1024 */
+#define BT_8822B_2ANT_ANTDET_PSD_AVGNUM 1 /* MAX:3 */
+#define BT_8822B_2ANT_ANTDET_BUF_LEN 16
+
+struct psdscan_sta_8822b_2ant {
+
+ u32 ant_det_bt_le_channel; /* BT LE Channel ex:2412 */
+ u32 ant_det_bt_tx_time;
+ u32 ant_det_pre_psdscan_peak_val;
+ boolean ant_det_is_ant_det_available;
+ u32 ant_det_psd_scan_peak_val;
+ boolean ant_det_is_btreply_available;
+ u32 ant_det_psd_scan_peak_freq;
+
+ u8 ant_det_result;
+ u8 ant_det_peak_val[BT_8822B_2ANT_ANTDET_BUF_LEN];
+ u8 ant_det_peak_freq[BT_8822B_2ANT_ANTDET_BUF_LEN];
+ u32 ant_det_try_count;
+ u32 ant_det_fail_count;
+ u32 ant_det_inteval_count;
+ u32 ant_det_thres_offset;
+
+ u32 real_cent_freq;
+ s32 real_offset;
+ u32 real_span;
+
+ u32 psd_band_width; /* unit: Hz */
+ u32 psd_point; /* 128/256/512/1024 */
+ u32 psd_report[1024]; /* unit:dB (20logx), 0~255 */
+ u32 psd_report_max_hold[1024]; /* unit:dB (20logx), 0~255 */
+ u32 psd_start_point;
+ u32 psd_stop_point;
+ u32 psd_max_value_point;
+ u32 psd_max_value;
+ u32 psd_max_value2;
+ /* filter loop_max_value that below BT_8822B_1ANT_ANTDET_PSDTHRES_1ANT,
+ * and average the rest
+ */
+ u32 psd_avg_value;
+ /*max value in each loop */
+ u32 psd_loop_max_value[BT_8822B_2ANT_ANTDET_PSD_SWWEEPCOUNT];
+ u32 psd_start_base;
+ u32 psd_avg_num; /* 1/8/16/32 */
+ u32 psd_gen_count;
+ boolean is_AntDet_running;
+ boolean is_psd_show_max_only;
+};
+
+
+/* *******************************************
+ * The following is interface which will notify coex module.
+ * ******************************************* */
+void ex_halbtc8822b2ant_power_on_setting(IN struct btc_coexist *btcoexist);
+void ex_halbtc8822b2ant_pre_load_firmware(IN struct btc_coexist *btcoexist);
+void ex_halbtc8822b2ant_init_hw_config(IN struct btc_coexist *btcoexist,
+ IN boolean wifi_only);
+void ex_halbtc8822b2ant_init_coex_dm(IN struct btc_coexist *btcoexist);
+void ex_halbtc8822b2ant_ips_notify(IN struct btc_coexist *btcoexist,
+ IN u8 type);
+void ex_halbtc8822b2ant_lps_notify(IN struct btc_coexist *btcoexist,
+ IN u8 type);
+void ex_halbtc8822b2ant_scan_notify(IN struct btc_coexist *btcoexist,
+ IN u8 type);
+void ex_halbtc8822b2ant_switchband_notify(IN struct btc_coexist *btcoexist,
+ IN u8 type);
+void ex_halbtc8822b2ant_connect_notify(IN struct btc_coexist *btcoexist,
+ IN u8 type);
+void ex_halbtc8822b2ant_media_status_notify(IN struct btc_coexist *btcoexist,
+ IN u8 type);
+void ex_halbtc8822b2ant_specific_packet_notify(IN struct btc_coexist *btcoexist,
+ IN u8 type);
+void ex_halbtc8822b2ant_bt_info_notify(IN struct btc_coexist *btcoexist,
+ IN u8 *tmp_buf, IN u8 length);
+void ex_halbtc8822b2ant_wl_fwdbginfo_notify(IN struct btc_coexist *btcoexist,
+ IN u8 *tmp_buf, IN u8 length);
+void ex_halbtc8822b2ant_rx_rate_change_notify(IN struct btc_coexist *btcoexist,
+ IN BOOLEAN is_data_frame, IN u8 btc_rate_id);
+void ex_halbtc8822b2ant_rf_status_notify(IN struct btc_coexist *btcoexist,
+ IN u8 type);
+void ex_halbtc8822b2ant_halt_notify(IN struct btc_coexist *btcoexist);
+void ex_halbtc8822b2ant_pnp_notify(IN struct btc_coexist *btcoexist,
+ IN u8 pnp_state);
+void ex_halbtc8822b2ant_periodical(IN struct btc_coexist *btcoexist);
+void ex_halbtc8822b2ant_display_simple_coex_info(IN struct btc_coexist *btcoexist);
+
+void ex_halbtc8822b2ant_display_coex_info(IN struct btc_coexist *btcoexist);
+void ex_halbtc8822b2ant_antenna_detection(IN struct btc_coexist *btcoexist,
+ IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds);
+void ex_halbtc8822b2ant_display_ant_detection(IN struct btc_coexist *btcoexist);
+
+
+#else
+#define ex_halbtc8822b2ant_power_on_setting(btcoexist)
+#define ex_halbtc8822b2ant_pre_load_firmware(btcoexist)
+#define ex_halbtc8822b2ant_init_hw_config(btcoexist, wifi_only)
+#define ex_halbtc8822b2ant_init_coex_dm(btcoexist)
+#define ex_halbtc8822b2ant_ips_notify(btcoexist, type)
+#define ex_halbtc8822b2ant_lps_notify(btcoexist, type)
+#define ex_halbtc8822b2ant_scan_notify(btcoexist, type)
+#define ex_halbtc8822b2ant_switchband_notify(btcoexist, type)
+#define ex_halbtc8822b2ant_connect_notify(btcoexist, type)
+#define ex_halbtc8822b2ant_media_status_notify(btcoexist, type)
+#define ex_halbtc8822b2ant_specific_packet_notify(btcoexist, type)
+#define ex_halbtc8822b2ant_bt_info_notify(btcoexist, tmp_buf, length)
+#define ex_halbtc8822b2ant_wl_fwdbginfo_notify(btcoexist, tmp_buf, length)
+#define ex_halbtc8822b2ant_rx_rate_change_notify(btcoexist, is_data_frame, btc_rate_id)
+#define ex_halbtc8822b2ant_rf_status_notify(btcoexist, type)
+#define ex_halbtc8822b2ant_halt_notify(btcoexist)
+#define ex_halbtc8822b2ant_pnp_notify(btcoexist, pnp_state)
+#define ex_halbtc8822b2ant_periodical(btcoexist)
+#define ex_halbtc8822b2ant_display_coex_info(btcoexist)
+#define ex_halbtc8822b2ant_display_ant_detection(btcoexist)
+#define ex_halbtc8822b2ant_antenna_detection(btcoexist, cent_freq, offset, span, seconds)
+#define ex_halbtc8822b2ant_display_simple_coex_info(btcoexist)
+#endif
+
+#endif
diff --git a/hal/btc/halbtc8822bwifionly.c b/hal/btc/halbtc8822bwifionly.c
new file mode 100644
index 0000000..8de6409
--- /dev/null
+++ b/hal/btc/halbtc8822bwifionly.c
@@ -0,0 +1,68 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#include "mp_precomp.h"
+
+
+VOID
+ex_hal8822b_wifi_only_hw_config(
+ IN struct wifi_only_cfg *pwifionlycfg
+ )
+{
+ /*BB control*/
+ halwifionly_phy_set_bb_reg(pwifionlycfg, 0x4c, 0x01800000, 0x2);
+ /*SW control*/
+ halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcb4, 0xff, 0x77);
+ /*antenna mux switch */
+ halwifionly_phy_set_bb_reg(pwifionlycfg, 0x974, 0x300, 0x3);
+
+ halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1990, 0x300, 0x0);
+
+ halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcbc, 0x80000, 0x0);
+ /*switch to WL side controller and gnt_wl gnt_bt debug signal */
+ halwifionly_phy_set_bb_reg(pwifionlycfg, 0x70, 0xff000000, 0x0e);
+ /*gnt_wl=1 , gnt_bt=0*/
+ halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1704, 0xffffffff, 0x7700);
+ halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1700, 0xffffffff, 0xc00f0038);
+}
+
+VOID
+ex_hal8822b_wifi_only_scannotify(
+ IN struct wifi_only_cfg *pwifionlycfg,
+ IN u1Byte is_5g
+ )
+{
+ hal8822b_wifi_only_switch_antenna(pwifionlycfg, is_5g);
+}
+
+VOID
+ex_hal8822b_wifi_only_switchbandnotify(
+ IN struct wifi_only_cfg *pwifionlycfg,
+ IN u1Byte is_5g
+ )
+{
+ hal8822b_wifi_only_switch_antenna(pwifionlycfg, is_5g);
+}
+
+VOID
+hal8822b_wifi_only_switch_antenna(IN struct wifi_only_cfg *pwifionlycfg,
+ IN u1Byte is_5g
+ )
+{
+
+ if (is_5g)
+ halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcbc, 0x300, 0x1);
+ else
+ halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcbc, 0x300, 0x2);
+}
diff --git a/hal/btc/halbtc8822bwifionly.h b/hal/btc/halbtc8822bwifionly.h
new file mode 100644
index 0000000..4ca6f48
--- /dev/null
+++ b/hal/btc/halbtc8822bwifionly.h
@@ -0,0 +1,36 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __INC_HAL8822BWIFIONLYHWCFG_H
+#define __INC_HAL8822BWIFIONLYHWCFG_H
+
+VOID
+ex_hal8822b_wifi_only_hw_config(
+ IN struct wifi_only_cfg *pwifionlycfg
+ );
+VOID
+ex_hal8822b_wifi_only_scannotify(
+ IN struct wifi_only_cfg *pwifionlycfg,
+ IN u1Byte is_5g
+ );
+VOID
+ex_hal8822b_wifi_only_switchbandnotify(
+ IN struct wifi_only_cfg *pwifionlycfg,
+ IN u1Byte is_5g
+ );
+VOID
+hal8822b_wifi_only_switch_antenna(IN struct wifi_only_cfg *pwifionlycfg,
+ IN u1Byte is_5g
+ );
+#endif
diff --git a/hal/btc/HalBtcOutSrc.h b/hal/btc/halbtcoutsrc.h
similarity index 52%
rename from hal/btc/HalBtcOutSrc.h
rename to hal/btc/halbtcoutsrc.h
index 8ec3299..fefcf34 100644
--- a/hal/btc/HalBtcOutSrc.h
+++ b/hal/btc/halbtcoutsrc.h
@@ -1,13 +1,132 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
#ifndef __HALBTC_OUT_SRC_H__
#define __HALBTC_OUT_SRC_H__
+enum {
+ BTC_CCK_1,
+ BTC_CCK_2,
+ BTC_CCK_5_5,
+ BTC_CCK_11,
+ BTC_OFDM_6,
+ BTC_OFDM_9,
+ BTC_OFDM_12,
+ BTC_OFDM_18,
+ BTC_OFDM_24,
+ BTC_OFDM_36,
+ BTC_OFDM_48,
+ BTC_OFDM_54,
+ BTC_MCS_0,
+ BTC_MCS_1,
+ BTC_MCS_2,
+ BTC_MCS_3,
+ BTC_MCS_4,
+ BTC_MCS_5,
+ BTC_MCS_6,
+ BTC_MCS_7,
+ BTC_MCS_8,
+ BTC_MCS_9,
+ BTC_MCS_10,
+ BTC_MCS_11,
+ BTC_MCS_12,
+ BTC_MCS_13,
+ BTC_MCS_14,
+ BTC_MCS_15,
+ BTC_MCS_16,
+ BTC_MCS_17,
+ BTC_MCS_18,
+ BTC_MCS_19,
+ BTC_MCS_20,
+ BTC_MCS_21,
+ BTC_MCS_22,
+ BTC_MCS_23,
+ BTC_MCS_24,
+ BTC_MCS_25,
+ BTC_MCS_26,
+ BTC_MCS_27,
+ BTC_MCS_28,
+ BTC_MCS_29,
+ BTC_MCS_30,
+ BTC_MCS_31,
+ BTC_VHT_1SS_MCS_0,
+ BTC_VHT_1SS_MCS_1,
+ BTC_VHT_1SS_MCS_2,
+ BTC_VHT_1SS_MCS_3,
+ BTC_VHT_1SS_MCS_4,
+ BTC_VHT_1SS_MCS_5,
+ BTC_VHT_1SS_MCS_6,
+ BTC_VHT_1SS_MCS_7,
+ BTC_VHT_1SS_MCS_8,
+ BTC_VHT_1SS_MCS_9,
+ BTC_VHT_2SS_MCS_0,
+ BTC_VHT_2SS_MCS_1,
+ BTC_VHT_2SS_MCS_2,
+ BTC_VHT_2SS_MCS_3,
+ BTC_VHT_2SS_MCS_4,
+ BTC_VHT_2SS_MCS_5,
+ BTC_VHT_2SS_MCS_6,
+ BTC_VHT_2SS_MCS_7,
+ BTC_VHT_2SS_MCS_8,
+ BTC_VHT_2SS_MCS_9,
+ BTC_VHT_3SS_MCS_0,
+ BTC_VHT_3SS_MCS_1,
+ BTC_VHT_3SS_MCS_2,
+ BTC_VHT_3SS_MCS_3,
+ BTC_VHT_3SS_MCS_4,
+ BTC_VHT_3SS_MCS_5,
+ BTC_VHT_3SS_MCS_6,
+ BTC_VHT_3SS_MCS_7,
+ BTC_VHT_3SS_MCS_8,
+ BTC_VHT_3SS_MCS_9,
+ BTC_VHT_4SS_MCS_0,
+ BTC_VHT_4SS_MCS_1,
+ BTC_VHT_4SS_MCS_2,
+ BTC_VHT_4SS_MCS_3,
+ BTC_VHT_4SS_MCS_4,
+ BTC_VHT_4SS_MCS_5,
+ BTC_VHT_4SS_MCS_6,
+ BTC_VHT_4SS_MCS_7,
+ BTC_VHT_4SS_MCS_8,
+ BTC_VHT_4SS_MCS_9,
+ BTC_MCS_32,
+ BTC_UNKNOWN,
+ BTC_PKT_MGNT,
+ BTC_PKT_CTRL,
+ BTC_PKT_UNKNOWN,
+ BTC_PKT_NOT_FOR_ME,
+ BTC_RATE_MAX
+};
+
+enum {
+ BTC_MULTIPORT_SCC,
+ BTC_MULTIPORT_MCC_DUAL_CHANNEL,
+ BTC_MULTIPORT_MCC_DUAL_BAND,
+ BTC_MULTIPORT_MAX
+};
#define BTC_COEX_OFFLOAD 0
#define BTC_TMP_BUF_SHORT 20
extern u1Byte gl_btc_trace_buf[];
#define BTC_SPRINTF rsprintf
-#define BTC_TRACE(_MSG_) RT_TRACE(COMP_COEX, DBG_LOUD, (_MSG_))
+#define BTC_TRACE(_MSG_)\
+do {\
+ if (GLBtcDbgType[COMP_COEX] & BIT(DBG_LOUD)) {\
+ RTW_INFO("%s", _MSG_);\
+ } \
+} while (0)
#define BT_PrintData(adapter, _MSG_, len, data) RTW_DBG_DUMP((_MSG_), data, len)
@@ -31,34 +150,34 @@ extern u1Byte gl_btc_trace_buf[];
#define BT_COEX_ANT_TYPE_ANTDIV 1
#define BT_COEX_ANT_TYPE_DETECTED 2
-#define BTC_MIMO_PS_STATIC 0 // 1ss
-#define BTC_MIMO_PS_DYNAMIC 1 // 2ss
+#define BTC_MIMO_PS_STATIC 0 /* 1ss */
+#define BTC_MIMO_PS_DYNAMIC 1 /* 2ss */
#define BTC_RATE_DISABLE 0
#define BTC_RATE_ENABLE 1
-// single Antenna definition
+/* single Antenna definition */
#define BTC_ANT_PATH_WIFI 0
#define BTC_ANT_PATH_BT 1
#define BTC_ANT_PATH_PTA 2
#define BTC_ANT_PATH_WIFI5G 3
#define BTC_ANT_PATH_AUTO 4
-// dual Antenna definition
+/* dual Antenna definition */
#define BTC_ANT_WIFI_AT_MAIN 0
#define BTC_ANT_WIFI_AT_AUX 1
#define BTC_ANT_WIFI_AT_DIVERSITY 2
-// coupler Antenna definition
+/* coupler Antenna definition */
#define BTC_ANT_WIFI_AT_CPL_MAIN 0
#define BTC_ANT_WIFI_AT_CPL_AUX 1
-typedef enum _BTC_POWERSAVE_TYPE{
- BTC_PS_WIFI_NATIVE = 0, // wifi original power save behavior
+typedef enum _BTC_POWERSAVE_TYPE {
+ BTC_PS_WIFI_NATIVE = 0, /* wifi original power save behavior */
BTC_PS_LPS_ON = 1,
BTC_PS_LPS_OFF = 2,
BTC_PS_MAX
} BTC_POWERSAVE_TYPE, *PBTC_POWERSAVE_TYPE;
-typedef enum _BTC_BT_REG_TYPE{
+typedef enum _BTC_BT_REG_TYPE {
BTC_BT_REG_RF = 0,
BTC_BT_REG_MODEM = 1,
BTC_BT_REG_BLUEWIZE = 2,
@@ -67,7 +186,7 @@ typedef enum _BTC_BT_REG_TYPE{
BTC_BT_REG_MAX
} BTC_BT_REG_TYPE, *PBTC_BT_REG_TYPE;
-typedef enum _BTC_CHIP_INTERFACE{
+typedef enum _BTC_CHIP_INTERFACE {
BTC_INTF_UNKNOWN = 0,
BTC_INTF_PCI = 1,
BTC_INTF_USB = 2,
@@ -75,28 +194,28 @@ typedef enum _BTC_CHIP_INTERFACE{
BTC_INTF_MAX
} BTC_CHIP_INTERFACE, *PBTC_CHIP_INTERFACE;
-typedef enum _BTC_CHIP_TYPE{
+typedef enum _BTC_CHIP_TYPE {
BTC_CHIP_UNDEF = 0,
BTC_CHIP_CSR_BC4 = 1,
BTC_CHIP_CSR_BC8 = 2,
- BTC_CHIP_RTL8723A = 3,
- BTC_CHIP_RTL8821 = 4,
- BTC_CHIP_RTL8723B = 5,
+ BTC_CHIP_RTL8723A = 3,
+ BTC_CHIP_RTL8821 = 4,
+ BTC_CHIP_RTL8723B = 5,
BTC_CHIP_MAX
} BTC_CHIP_TYPE, *PBTC_CHIP_TYPE;
-// following is for wifi link status
+/* following is for wifi link status */
#define WIFI_STA_CONNECTED BIT0
#define WIFI_AP_CONNECTED BIT1
#define WIFI_HS_CONNECTED BIT2
#define WIFI_P2P_GO_CONNECTED BIT3
#define WIFI_P2P_GC_CONNECTED BIT4
-// following is for command line utility
+/* following is for command line utility */
#define CL_SPRINTF rsprintf
#define CL_PRINTF DCMD_Printf
-struct btc_board_info{
+struct btc_board_info {
/* The following is some board information */
u8 bt_chip_type;
u8 pg_ant_num; /* pg ant number */
@@ -106,12 +225,18 @@ struct btc_board_info{
u8 single_ant_path; /* current used for 8723b only, 1=>s0, 0=>s1 */
boolean tfbga_package; /* for Antenna detect threshold */
boolean btdm_ant_det_finish;
+ boolean btdm_ant_det_already_init_phydm;
u8 ant_type;
u8 rfe_type;
u8 ant_div_cfg;
+ boolean btdm_ant_det_complete_fail;
+ u8 ant_det_result;
+ boolean ant_det_result_five_complete;
+ u32 antdetval;
+ u8 customerID;
};
-typedef enum _BTC_DBG_OPCODE{
+typedef enum _BTC_DBG_OPCODE {
BTC_DBG_SET_COEX_NORMAL = 0x0,
BTC_DBG_SET_COEX_WIFI_ONLY = 0x1,
BTC_DBG_SET_COEX_BT_ONLY = 0x2,
@@ -120,9 +245,9 @@ typedef enum _BTC_DBG_OPCODE{
BTC_DBG_SET_COEX_BT_IGNORE_WLAN_ACT = 0x5,
BTC_DBG_SET_COEX_MANUAL_CTRL = 0x6,
BTC_DBG_MAX
-}BTC_DBG_OPCODE,*PBTC_DBG_OPCODE;
+} BTC_DBG_OPCODE, *PBTC_DBG_OPCODE;
-typedef enum _BTC_RSSI_STATE{
+typedef enum _BTC_RSSI_STATE {
BTC_RSSI_STATE_HIGH = 0x0,
BTC_RSSI_STATE_MEDIUM = 0x1,
BTC_RSSI_STATE_LOW = 0x2,
@@ -130,48 +255,48 @@ typedef enum _BTC_RSSI_STATE{
BTC_RSSI_STATE_STAY_MEDIUM = 0x4,
BTC_RSSI_STATE_STAY_LOW = 0x5,
BTC_RSSI_MAX
-}BTC_RSSI_STATE,*PBTC_RSSI_STATE;
-#define BTC_RSSI_HIGH(_rssi_) ((_rssi_==BTC_RSSI_STATE_HIGH||_rssi_==BTC_RSSI_STATE_STAY_HIGH)? TRUE:FALSE)
-#define BTC_RSSI_MEDIUM(_rssi_) ((_rssi_==BTC_RSSI_STATE_MEDIUM||_rssi_==BTC_RSSI_STATE_STAY_MEDIUM)? TRUE:FALSE)
-#define BTC_RSSI_LOW(_rssi_) ((_rssi_==BTC_RSSI_STATE_LOW||_rssi_==BTC_RSSI_STATE_STAY_LOW)? TRUE:FALSE)
+} BTC_RSSI_STATE, *PBTC_RSSI_STATE;
+#define BTC_RSSI_HIGH(_rssi_) ((_rssi_ == BTC_RSSI_STATE_HIGH || _rssi_ == BTC_RSSI_STATE_STAY_HIGH) ? TRUE:FALSE)
+#define BTC_RSSI_MEDIUM(_rssi_) ((_rssi_ == BTC_RSSI_STATE_MEDIUM || _rssi_ == BTC_RSSI_STATE_STAY_MEDIUM) ? TRUE:FALSE)
+#define BTC_RSSI_LOW(_rssi_) ((_rssi_ == BTC_RSSI_STATE_LOW || _rssi_ == BTC_RSSI_STATE_STAY_LOW) ? TRUE:FALSE)
-typedef enum _BTC_WIFI_ROLE{
+typedef enum _BTC_WIFI_ROLE {
BTC_ROLE_STATION = 0x0,
BTC_ROLE_AP = 0x1,
BTC_ROLE_IBSS = 0x2,
BTC_ROLE_HS_MODE = 0x3,
BTC_ROLE_MAX
-}BTC_WIFI_ROLE,*PBTC_WIFI_ROLE;
+} BTC_WIFI_ROLE, *PBTC_WIFI_ROLE;
-typedef enum _BTC_WIRELESS_FREQ{
+typedef enum _BTC_WIRELESS_FREQ {
BTC_FREQ_2_4G = 0x0,
BTC_FREQ_5G = 0x1,
- BTC_FREQ_MAX
-}BTC_WIRELESS_FREQ,*PBTC_WIRELESS_FREQ;
+ BTC_FREQ_MAX
+} BTC_WIRELESS_FREQ, *PBTC_WIRELESS_FREQ;
-typedef enum _BTC_WIFI_BW_MODE{
+typedef enum _BTC_WIFI_BW_MODE {
BTC_WIFI_BW_LEGACY = 0x0,
BTC_WIFI_BW_HT20 = 0x1,
BTC_WIFI_BW_HT40 = 0x2,
BTC_WIFI_BW_HT80 = 0x3,
BTC_WIFI_BW_HT160 = 0x4,
- BTC_WIFI_BW_MAX
-}BTC_WIFI_BW_MODE,*PBTC_WIFI_BW_MODE;
+ BTC_WIFI_BW_MAX
+} BTC_WIFI_BW_MODE, *PBTC_WIFI_BW_MODE;
-typedef enum _BTC_WIFI_TRAFFIC_DIR{
+typedef enum _BTC_WIFI_TRAFFIC_DIR {
BTC_WIFI_TRAFFIC_TX = 0x0,
BTC_WIFI_TRAFFIC_RX = 0x1,
- BTC_WIFI_TRAFFIC_MAX
-}BTC_WIFI_TRAFFIC_DIR,*PBTC_WIFI_TRAFFIC_DIR;
+ BTC_WIFI_TRAFFIC_MAX
+} BTC_WIFI_TRAFFIC_DIR, *PBTC_WIFI_TRAFFIC_DIR;
-typedef enum _BTC_WIFI_PNP{
+typedef enum _BTC_WIFI_PNP {
BTC_WIFI_PNP_WAKE_UP = 0x0,
BTC_WIFI_PNP_SLEEP = 0x1,
+ BTC_WIFI_PNP_SLEEP_KEEP_ANT = 0x2,
BTC_WIFI_PNP_MAX
-}BTC_WIFI_PNP,*PBTC_WIFI_PNP;
+} BTC_WIFI_PNP, *PBTC_WIFI_PNP;
-typedef enum _BTC_IOT_PEER
-{
+typedef enum _BTC_IOT_PEER {
BTC_IOT_PEER_UNKNOWN = 0,
BTC_IOT_PEER_REALTEK = 1,
BTC_IOT_PEER_REALTEK_92SE = 2,
@@ -179,22 +304,22 @@ typedef enum _BTC_IOT_PEER
BTC_IOT_PEER_RALINK = 4,
BTC_IOT_PEER_ATHEROS = 5,
BTC_IOT_PEER_CISCO = 6,
- BTC_IOT_PEER_MERU = 7,
+ BTC_IOT_PEER_MERU = 7,
BTC_IOT_PEER_MARVELL = 8,
- BTC_IOT_PEER_REALTEK_SOFTAP = 9,// peer is RealTek SOFT_AP, by Bohn, 2009.12.17
- BTC_IOT_PEER_SELF_SOFTAP = 10, // Self is SoftAP
+ BTC_IOT_PEER_REALTEK_SOFTAP = 9, /* peer is RealTek SOFT_AP, by Bohn, 2009.12.17 */
+ BTC_IOT_PEER_SELF_SOFTAP = 10, /* Self is SoftAP */
BTC_IOT_PEER_AIRGO = 11,
- BTC_IOT_PEER_INTEL = 12,
- BTC_IOT_PEER_RTK_APCLIENT = 13,
- BTC_IOT_PEER_REALTEK_81XX = 14,
- BTC_IOT_PEER_REALTEK_WOW = 15,
+ BTC_IOT_PEER_INTEL = 12,
+ BTC_IOT_PEER_RTK_APCLIENT = 13,
+ BTC_IOT_PEER_REALTEK_81XX = 14,
+ BTC_IOT_PEER_REALTEK_WOW = 15,
BTC_IOT_PEER_REALTEK_JAGUAR_BCUTAP = 16,
BTC_IOT_PEER_REALTEK_JAGUAR_CCUTAP = 17,
BTC_IOT_PEER_MAX,
-}BTC_IOT_PEER, *PBTC_IOT_PEER;
+} BTC_IOT_PEER, *PBTC_IOT_PEER;
-//for 8723b-d cut large current issue
-typedef enum _BTC_WIFI_COEX_STATE{
+/* for 8723b-d cut large current issue */
+typedef enum _BTC_WIFI_COEX_STATE {
BTC_WIFI_STAT_INIT,
BTC_WIFI_STAT_IQK,
BTC_WIFI_STAT_NORMAL_OFF,
@@ -202,30 +327,32 @@ typedef enum _BTC_WIFI_COEX_STATE{
BTC_WIFI_STAT_NORMAL,
BTC_WIFI_STAT_ANT_DIV,
BTC_WIFI_STAT_MAX
-}BTC_WIFI_COEX_STATE,*PBTC_WIFI_COEX_STATE;
+} BTC_WIFI_COEX_STATE, *PBTC_WIFI_COEX_STATE;
-typedef enum _BTC_ANT_TYPE{
+typedef enum _BTC_ANT_TYPE {
BTC_ANT_TYPE_0,
BTC_ANT_TYPE_1,
BTC_ANT_TYPE_2,
BTC_ANT_TYPE_3,
BTC_ANT_TYPE_4,
BTC_ANT_TYPE_MAX
-}BTC_ANT_TYPE,*PBTC_ANT_TYPE;
+} BTC_ANT_TYPE, *PBTC_ANT_TYPE;
-typedef enum _BTC_VENDOR{
+typedef enum _BTC_VENDOR {
BTC_VENDOR_LENOVO,
- BTC_VENDOR_ASUS,
+ BTC_VENDOR_ASUS,
BTC_VENDOR_OTHER
-}BTC_VENDOR,*PBTC_VENDOR;
+} BTC_VENDOR, *PBTC_VENDOR;
-// defined for BFP_BTC_GET
-typedef enum _BTC_GET_TYPE{
- // type BOOLEAN
+/* defined for BFP_BTC_GET */
+typedef enum _BTC_GET_TYPE {
+ /* type BOOLEAN */
BTC_GET_BL_HS_OPERATION,
BTC_GET_BL_HS_CONNECTING,
+ BTC_GET_BL_WIFI_FW_READY,
BTC_GET_BL_WIFI_CONNECTED,
+ BTC_GET_BL_WIFI_DUAL_BAND_CONNECTED,
BTC_GET_BL_WIFI_BUSY,
BTC_GET_BL_WIFI_SCAN,
BTC_GET_BL_WIFI_LINK,
@@ -238,23 +365,28 @@ typedef enum _BTC_GET_TYPE{
BTC_GET_BL_EXT_SWITCH,
BTC_GET_BL_WIFI_IS_IN_MP_MODE,
BTC_GET_BL_IS_ASUS_8723B,
+ BTC_GET_BL_RF4CE_CONNECTED,
- // type s4Byte
+ /* type s4Byte */
BTC_GET_S4_WIFI_RSSI,
BTC_GET_S4_HS_RSSI,
-
- // type u4Byte
+
+ /* type u4Byte */
BTC_GET_U4_WIFI_BW,
BTC_GET_U4_WIFI_TRAFFIC_DIRECTION,
BTC_GET_U4_WIFI_FW_VER,
BTC_GET_U4_WIFI_LINK_STATUS,
BTC_GET_U4_BT_PATCH_VER,
BTC_GET_U4_VENDOR,
+ BTC_GET_U4_SUPPORTED_VERSION,
+ BTC_GET_U4_SUPPORTED_FEATURE,
+ BTC_GET_U4_BT_DEVICE_INFO,
+ BTC_GET_U4_BT_FORBIDDEN_SLOT_VAL,
BTC_GET_U4_WIFI_IQK_TOTAL,
BTC_GET_U4_WIFI_IQK_OK,
BTC_GET_U4_WIFI_IQK_FAIL,
- // type u1Byte
+ /* type u1Byte */
BTC_GET_U1_WIFI_DOT11_CHNL,
BTC_GET_U1_WIFI_CENTRAL_CHNL,
BTC_GET_U1_WIFI_HS_CHNL,
@@ -264,16 +396,20 @@ typedef enum _BTC_GET_TYPE{
BTC_GET_U1_ANT_TYPE,
BTC_GET_U1_IOT_PEER,
- //===== for 1Ant ======
+ /* type u2Byte */
+ BTC_GET_U2_BEACON_PERIOD,
+
+ /*===== for 1Ant ======*/
BTC_GET_U1_LPS_MODE,
BTC_GET_MAX
-}BTC_GET_TYPE,*PBTC_GET_TYPE;
+} BTC_GET_TYPE, *PBTC_GET_TYPE;
-// defined for BFP_BTC_SET
-typedef enum _BTC_SET_TYPE{
- // type BOOLEAN
+/* defined for BFP_BTC_SET */
+typedef enum _BTC_SET_TYPE {
+ /* type BOOLEAN */
BTC_SET_BL_BT_DISABLE,
+ BTC_SET_BL_BT_ENABLE_DISABLE_CHANGE,
BTC_SET_BL_BT_TRAFFIC_BUSY,
BTC_SET_BL_BT_LIMITED_DIG,
BTC_SET_BL_FORCE_TO_ROAM,
@@ -282,157 +418,163 @@ typedef enum _BTC_SET_TYPE{
BTC_SET_BL_INC_SCAN_DEV_NUM,
BTC_SET_BL_BT_TX_RX_MASK,
BTC_SET_BL_MIRACAST_PLUS_BT,
+ BTC_SET_BL_BT_LNA_CONSTRAIN_LEVEL,
- // type u1Byte
+ /* type u1Byte */
BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON,
BTC_SET_U1_AGG_BUF_SIZE,
- // type trigger some action
+ /* type trigger some action */
BTC_SET_ACT_GET_BT_RSSI,
BTC_SET_ACT_AGGREGATE_CTRL,
BTC_SET_ACT_ANTPOSREGRISTRY_CTRL,
- //===== for 1Ant ======
- // type BOOLEAN
- // type u1Byte
+ // for mimo ps mode setting
+ BTC_SET_MIMO_PS_MODE,
+ /*===== for 1Ant ======*/
+ /* type BOOLEAN */
+
+ /* type u1Byte */
BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE,
BTC_SET_U1_LPS_VAL,
BTC_SET_U1_RPWM_VAL,
- // type trigger some action
+ /* type trigger some action */
BTC_SET_ACT_LEAVE_LPS,
BTC_SET_ACT_ENTER_LPS,
BTC_SET_ACT_NORMAL_LPS,
+ BTC_SET_ACT_PRE_NORMAL_LPS,
+ BTC_SET_ACT_POST_NORMAL_LPS,
BTC_SET_ACT_DISABLE_LOW_POWER,
BTC_SET_ACT_UPDATE_RAMASK,
BTC_SET_ACT_SEND_MIMO_PS,
- // BT Coex related
+ /* BT Coex related */
BTC_SET_ACT_CTRL_BT_INFO,
BTC_SET_ACT_CTRL_BT_COEX,
BTC_SET_ACT_CTRL_8723B_ANT,
- //=================
+ /*=================*/
BTC_SET_MAX
-}BTC_SET_TYPE,*PBTC_SET_TYPE;
+} BTC_SET_TYPE, *PBTC_SET_TYPE;
-typedef enum _BTC_DBG_DISP_TYPE{
+typedef enum _BTC_DBG_DISP_TYPE {
BTC_DBG_DISP_COEX_STATISTICS = 0x0,
BTC_DBG_DISP_BT_LINK_INFO = 0x1,
BTC_DBG_DISP_WIFI_STATUS = 0x2,
BTC_DBG_DISP_MAX
-}BTC_DBG_DISP_TYPE,*PBTC_DBG_DISP_TYPE;
+} BTC_DBG_DISP_TYPE, *PBTC_DBG_DISP_TYPE;
-typedef enum _BTC_NOTIFY_TYPE_IPS{
+typedef enum _BTC_NOTIFY_TYPE_IPS {
BTC_IPS_LEAVE = 0x0,
BTC_IPS_ENTER = 0x1,
BTC_IPS_MAX
-}BTC_NOTIFY_TYPE_IPS,*PBTC_NOTIFY_TYPE_IPS;
-typedef enum _BTC_NOTIFY_TYPE_LPS{
+} BTC_NOTIFY_TYPE_IPS, *PBTC_NOTIFY_TYPE_IPS;
+typedef enum _BTC_NOTIFY_TYPE_LPS {
BTC_LPS_DISABLE = 0x0,
BTC_LPS_ENABLE = 0x1,
BTC_LPS_MAX
-}BTC_NOTIFY_TYPE_LPS,*PBTC_NOTIFY_TYPE_LPS;
-typedef enum _BTC_NOTIFY_TYPE_SCAN{
+} BTC_NOTIFY_TYPE_LPS, *PBTC_NOTIFY_TYPE_LPS;
+typedef enum _BTC_NOTIFY_TYPE_SCAN {
BTC_SCAN_FINISH = 0x0,
BTC_SCAN_START = 0x1,
BTC_SCAN_START_2G = 0x2,
BTC_SCAN_MAX
-}BTC_NOTIFY_TYPE_SCAN,*PBTC_NOTIFY_TYPE_SCAN;
-typedef enum _BTC_NOTIFY_TYPE_SWITCHBAND{
+} BTC_NOTIFY_TYPE_SCAN, *PBTC_NOTIFY_TYPE_SCAN;
+typedef enum _BTC_NOTIFY_TYPE_SWITCHBAND {
BTC_NOT_SWITCH = 0x0,
BTC_SWITCH_TO_24G = 0x1,
BTC_SWITCH_TO_5G = 0x2,
- BTC_SWITCH_TO_24G_NoForScan = 0x3,
+ BTC_SWITCH_TO_24G_NOFORSCAN = 0x3,
BTC_SWITCH_MAX
-}BTC_NOTIFY_TYPE_SWITCHBAND,*PBTC_NOTIFY_TYPE_SWITCHBAND;
-typedef enum _BTC_NOTIFY_TYPE_ASSOCIATE{
+} BTC_NOTIFY_TYPE_SWITCHBAND, *PBTC_NOTIFY_TYPE_SWITCHBAND;
+typedef enum _BTC_NOTIFY_TYPE_ASSOCIATE {
BTC_ASSOCIATE_FINISH = 0x0,
BTC_ASSOCIATE_START = 0x1,
BTC_ASSOCIATE_5G_FINISH = 0x2,
BTC_ASSOCIATE_5G_START = 0x3,
BTC_ASSOCIATE_MAX
-}BTC_NOTIFY_TYPE_ASSOCIATE,*PBTC_NOTIFY_TYPE_ASSOCIATE;
-typedef enum _BTC_NOTIFY_TYPE_MEDIA_STATUS{
+} BTC_NOTIFY_TYPE_ASSOCIATE, *PBTC_NOTIFY_TYPE_ASSOCIATE;
+typedef enum _BTC_NOTIFY_TYPE_MEDIA_STATUS {
BTC_MEDIA_DISCONNECT = 0x0,
BTC_MEDIA_CONNECT = 0x1,
BTC_MEDIA_MAX
-}BTC_NOTIFY_TYPE_MEDIA_STATUS,*PBTC_NOTIFY_TYPE_MEDIA_STATUS;
-typedef enum _BTC_NOTIFY_TYPE_SPECIFIC_PACKET{
+} BTC_NOTIFY_TYPE_MEDIA_STATUS, *PBTC_NOTIFY_TYPE_MEDIA_STATUS;
+typedef enum _BTC_NOTIFY_TYPE_SPECIFIC_PACKET {
BTC_PACKET_UNKNOWN = 0x0,
BTC_PACKET_DHCP = 0x1,
BTC_PACKET_ARP = 0x2,
BTC_PACKET_EAPOL = 0x3,
BTC_PACKET_MAX
-}BTC_NOTIFY_TYPE_SPECIFIC_PACKET,*PBTC_NOTIFY_TYPE_SPECIFIC_PACKET;
-typedef enum _BTC_NOTIFY_TYPE_STACK_OPERATION{
+} BTC_NOTIFY_TYPE_SPECIFIC_PACKET, *PBTC_NOTIFY_TYPE_SPECIFIC_PACKET;
+typedef enum _BTC_NOTIFY_TYPE_STACK_OPERATION {
BTC_STACK_OP_NONE = 0x0,
BTC_STACK_OP_INQ_PAGE_PAIR_START = 0x1,
BTC_STACK_OP_INQ_PAGE_PAIR_FINISH = 0x2,
BTC_STACK_OP_MAX
-}BTC_NOTIFY_TYPE_STACK_OPERATION,*PBTC_NOTIFY_TYPE_STACK_OPERATION;
+} BTC_NOTIFY_TYPE_STACK_OPERATION, *PBTC_NOTIFY_TYPE_STACK_OPERATION;
-//Bryant Add
-typedef enum _BTC_ANTENNA_POS{
+/* Bryant Add */
+typedef enum _BTC_ANTENNA_POS {
BTC_ANTENNA_AT_MAIN_PORT = 0x1,
BTC_ANTENNA_AT_AUX_PORT = 0x2,
-}BTC_ANTENNA_POS,*PBTC_ANTENNA_POS;
+} BTC_ANTENNA_POS, *PBTC_ANTENNA_POS;
-//Bryant Add
-typedef enum _BTC_BT_OFFON{
+/* Bryant Add */
+typedef enum _BTC_BT_OFFON {
BTC_BT_OFF = 0x0,
BTC_BT_ON = 0x1,
-}BTC_BTOFFON,*PBTC_BT_OFFON;
+} BTC_BTOFFON, *PBTC_BT_OFFON;
-//==================================================
-// For following block is for coex offload
-//==================================================
-typedef struct _COL_H2C{
+/*==================================================
+For following block is for coex offload
+==================================================*/
+typedef struct _COL_H2C {
u1Byte opcode;
u1Byte opcode_ver:4;
u1Byte req_num:4;
u1Byte buf[1];
-}COL_H2C, *PCOL_H2C;
+} COL_H2C, *PCOL_H2C;
#define COL_C2H_ACK_HDR_LEN 3
-typedef struct _COL_C2H_ACK{
+typedef struct _COL_C2H_ACK {
u1Byte status;
u1Byte opcode_ver:4;
u1Byte req_num:4;
u1Byte ret_len;
u1Byte buf[1];
-}COL_C2H_ACK, *PCOL_C2H_ACK;
+} COL_C2H_ACK, *PCOL_C2H_ACK;
#define COL_C2H_IND_HDR_LEN 3
-typedef struct _COL_C2H_IND{
+typedef struct _COL_C2H_IND {
u1Byte type;
u1Byte version;
u1Byte length;
u1Byte data[1];
-}COL_C2H_IND, *PCOL_C2H_IND;
-
-//============================================
-// NOTE: for debug message, the following define should match
-// the strings in coexH2cResultString.
-//============================================
-typedef enum _COL_H2C_STATUS{
- // c2h status
- COL_STATUS_C2H_OK = 0x00, // Wifi received H2C request and check content ok.
- COL_STATUS_C2H_UNKNOWN = 0x01, // Not handled routine
- COL_STATUS_C2H_UNKNOWN_OPCODE = 0x02, // Invalid OP code, It means that wifi firmware received an undefiend OP code.
- COL_STATUS_C2H_OPCODE_VER_MISMATCH = 0x03, // Wifi firmware and wifi driver mismatch, need to update wifi driver or wifi or.
- COL_STATUS_C2H_PARAMETER_ERROR = 0x04, // Error paraneter.(ex: parameters = NULL but it should have values)
- COL_STATUS_C2H_PARAMETER_OUT_OF_RANGE = 0x05, // Wifi firmware needs to check the parameters from H2C request and return the status.(ex: ch = 500, it's wrong)
- // other COL status start from here
- COL_STATUS_C2H_REQ_NUM_MISMATCH , // c2h req_num mismatch, means this c2h is not we expected.
- COL_STATUS_H2C_HALMAC_FAIL , // HALMAC return fail.
- COL_STATUS_H2C_TIMTOUT , // not received the c2h response from fw
- COL_STATUS_INVALID_C2H_LEN , // invalid coex offload c2h ack length, must >= 3
- COL_STATUS_COEX_DATA_OVERFLOW , // coex returned length over the c2h ack length.
+} COL_C2H_IND, *PCOL_C2H_IND;
+
+/*============================================
+NOTE: for debug message, the following define should match
+the strings in coexH2cResultString.
+============================================*/
+typedef enum _COL_H2C_STATUS {
+ /* c2h status */
+ COL_STATUS_C2H_OK = 0x00, /* Wifi received H2C request and check content ok. */
+ COL_STATUS_C2H_UNKNOWN = 0x01, /* Not handled routine */
+ COL_STATUS_C2H_UNKNOWN_OPCODE = 0x02, /* Invalid OP code, It means that wifi firmware received an undefiend OP code. */
+ COL_STATUS_C2H_OPCODE_VER_MISMATCH = 0x03, /* Wifi firmware and wifi driver mismatch, need to update wifi driver or wifi or. */
+ COL_STATUS_C2H_PARAMETER_ERROR = 0x04, /* Error paraneter.(ex: parameters = NULL but it should have values) */
+ COL_STATUS_C2H_PARAMETER_OUT_OF_RANGE = 0x05, /* Wifi firmware needs to check the parameters from H2C request and return the status.(ex: ch = 500, it's wrong) */
+ /* other COL status start from here */
+ COL_STATUS_C2H_REQ_NUM_MISMATCH , /* c2h req_num mismatch, means this c2h is not we expected. */
+ COL_STATUS_H2C_HALMAC_FAIL , /* HALMAC return fail. */
+ COL_STATUS_H2C_TIMTOUT , /* not received the c2h response from fw */
+ COL_STATUS_INVALID_C2H_LEN , /* invalid coex offload c2h ack length, must >= 3 */
+ COL_STATUS_COEX_DATA_OVERFLOW , /* coex returned length over the c2h ack length. */
COL_STATUS_MAX
-}COL_H2C_STATUS,*PCOL_H2C_STATUS;
+} COL_H2C_STATUS, *PCOL_H2C_STATUS;
#define COL_MAX_H2C_REQ_NUM 16
#define COL_H2C_BUF_LEN 20
-typedef enum _COL_OPCODE{
+typedef enum _COL_OPCODE {
COL_OP_WIFI_STATUS_NOTIFY = 0x0,
COL_OP_WIFI_PROGRESS_NOTIFY = 0x1,
COL_OP_WIFI_INFO_NOTIFY = 0x2,
@@ -440,47 +582,47 @@ typedef enum _COL_OPCODE{
COL_OP_SET_CONTROL = 0x4,
COL_OP_GET_CONTROL = 0x5,
COL_OP_WIFI_OPCODE_MAX
-}COL_OPCODE,*PCOL_OPCODE;
+} COL_OPCODE, *PCOL_OPCODE;
-typedef enum _COL_IND_TYPE{
+typedef enum _COL_IND_TYPE {
COL_IND_BT_INFO = 0x0,
COL_IND_PSTDMA = 0x1,
COL_IND_LIMITED_TX_RX = 0x2,
COL_IND_COEX_TABLE = 0x3,
COL_IND_REQ = 0x4,
COL_IND_MAX
-}COL_IND_TYPE,*PCOL_IND_TYPE;
+} COL_IND_TYPE, *PCOL_IND_TYPE;
-typedef struct _COL_SINGLE_H2C_RECORD{
- u1Byte h2c_buf[COL_H2C_BUF_LEN]; // the latest sent h2c buffer
+typedef struct _COL_SINGLE_H2C_RECORD {
+ u1Byte h2c_buf[COL_H2C_BUF_LEN]; /* the latest sent h2c buffer */
u4Byte h2c_len;
- u1Byte c2h_ack_buf[COL_H2C_BUF_LEN]; // the latest received c2h buffer
+ u1Byte c2h_ack_buf[COL_H2C_BUF_LEN]; /* the latest received c2h buffer */
u4Byte c2h_ack_len;
- u4Byte count; // the total number of the sent h2c command
- u4Byte status[COL_STATUS_MAX]; // the c2h status for the sent h2c command
+ u4Byte count; /* the total number of the sent h2c command */
+ u4Byte status[COL_STATUS_MAX]; /* the c2h status for the sent h2c command */
} COL_SINGLE_H2C_RECORD, *PCOL_SINGLE_H2C_RECORD;
-typedef struct _COL_SINGLE_C2H_IND_RECORD{
- u1Byte ind_buf[COL_H2C_BUF_LEN]; // the latest received c2h indication buffer
+typedef struct _COL_SINGLE_C2H_IND_RECORD {
+ u1Byte ind_buf[COL_H2C_BUF_LEN]; /* the latest received c2h indication buffer */
u4Byte ind_len;
- u4Byte count; // the total number of the rcvd c2h indication
- u4Byte status[COL_STATUS_MAX]; // the c2h indication verified status
+ u4Byte count; /* the total number of the rcvd c2h indication */
+ u4Byte status[COL_STATUS_MAX]; /* the c2h indication verified status */
} COL_SINGLE_C2H_IND_RECORD, *PCOL_SINGLE_C2H_IND_RECORD;
-typedef struct _BTC_OFFLOAD{
- // H2C command related
+typedef struct _BTC_OFFLOAD {
+ /* H2C command related */
u1Byte h2c_req_num;
u4Byte cnt_h2c_sent;
COL_SINGLE_H2C_RECORD h2c_record[COL_OP_WIFI_OPCODE_MAX];
- // C2H Ack related
+ /* C2H Ack related */
u4Byte cnt_c2h_ack;
u4Byte status[COL_STATUS_MAX];
- struct completion c2h_event[COL_MAX_H2C_REQ_NUM]; // for req_num = 1~COL_MAX_H2C_REQ_NUM
+ struct completion c2h_event[COL_MAX_H2C_REQ_NUM]; /* for req_num = 1~COL_MAX_H2C_REQ_NUM */
u1Byte c2h_ack_buf[COL_MAX_H2C_REQ_NUM][COL_H2C_BUF_LEN];
u1Byte c2h_ack_len[COL_MAX_H2C_REQ_NUM];
- // C2H Indication related
+ /* C2H Indication related */
u4Byte cnt_c2h_ind;
COL_SINGLE_C2H_IND_RECORD c2h_ind_record[COL_IND_MAX];
u4Byte c2h_ind_status[COL_STATUS_MAX];
@@ -488,87 +630,87 @@ typedef struct _BTC_OFFLOAD{
u1Byte c2h_ind_len;
} BTC_OFFLOAD, *PBTC_OFFLOAD;
extern BTC_OFFLOAD gl_coex_offload;
-//==================================================
+/*==================================================*/
typedef u1Byte
(*BFP_BTC_R1)(
- IN PVOID pBtcContext,
+ IN PVOID pBtcContext,
IN u4Byte RegAddr
);
typedef u2Byte
(*BFP_BTC_R2)(
- IN PVOID pBtcContext,
+ IN PVOID pBtcContext,
IN u4Byte RegAddr
);
typedef u4Byte
(*BFP_BTC_R4)(
- IN PVOID pBtcContext,
+ IN PVOID pBtcContext,
IN u4Byte RegAddr
);
typedef VOID
(*BFP_BTC_W1)(
- IN PVOID pBtcContext,
+ IN PVOID pBtcContext,
IN u4Byte RegAddr,
IN u1Byte Data
);
typedef VOID
(*BFP_BTC_W1_BIT_MASK)(
- IN PVOID pBtcContext,
+ IN PVOID pBtcContext,
IN u4Byte regAddr,
IN u1Byte bitMask,
IN u1Byte data1b
);
typedef VOID
(*BFP_BTC_W2)(
- IN PVOID pBtcContext,
+ IN PVOID pBtcContext,
IN u4Byte RegAddr,
IN u2Byte Data
);
typedef VOID
(*BFP_BTC_W4)(
- IN PVOID pBtcContext,
+ IN PVOID pBtcContext,
IN u4Byte RegAddr,
IN u4Byte Data
);
typedef VOID
(*BFP_BTC_LOCAL_REG_W1)(
- IN PVOID pBtcContext,
+ IN PVOID pBtcContext,
IN u4Byte RegAddr,
IN u1Byte Data
);
typedef VOID
(*BFP_BTC_SET_BB_REG)(
- IN PVOID pBtcContext,
+ IN PVOID pBtcContext,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
);
-typedef u4Byte
+typedef u4Byte
(*BFP_BTC_GET_BB_REG)(
- IN PVOID pBtcContext,
+ IN PVOID pBtcContext,
IN u4Byte RegAddr,
IN u4Byte BitMask
);
typedef VOID
-(*BFP_BTC_SET_RF_REG)(
- IN PVOID pBtcContext,
- IN u1Byte eRFPath,
+(*BFP_BTC_SET_RF_REG)(
+ IN PVOID pBtcContext,
+ IN enum rf_path eRFPath,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
);
-typedef u4Byte
+typedef u4Byte
(*BFP_BTC_GET_RF_REG)(
- IN PVOID pBtcContext,
- IN u1Byte eRFPath,
+ IN PVOID pBtcContext,
+ IN enum rf_path eRFPath,
IN u4Byte RegAddr,
IN u4Byte BitMask
);
typedef VOID
(*BFP_BTC_FILL_H2C)(
- IN PVOID pBtcContext,
- IN u1Byte elementId,
- IN u4Byte cmdLen,
+ IN PVOID pBtcContext,
+ IN u1Byte elementId,
+ IN u4Byte cmdLen,
IN pu1Byte pCmdBuffer
);
@@ -587,23 +729,29 @@ typedef BOOLEAN
);
typedef u2Byte
(*BFP_BTC_SET_BT_REG)(
- IN PVOID pBtcContext,
+ IN PVOID pBtcContext,
IN u1Byte regType,
IN u4Byte offset,
IN u4Byte value
);
typedef BOOLEAN
(*BFP_BTC_SET_BT_ANT_DETECTION)(
- IN PVOID pBtcContext,
+ IN PVOID pBtcContext,
IN u1Byte txTime,
IN u1Byte btChnl
);
-typedef u2Byte
+
+typedef BOOLEAN
+(*BFP_BTC_SET_BT_TRX_MASK)(
+ IN PVOID pBtcContext,
+ IN u1Byte bt_trx_mask
+ );
+
+typedef u4Byte
(*BFP_BTC_GET_BT_REG)(
- IN PVOID pBtcContext,
+ IN PVOID pBtcContext,
IN u1Byte regType,
- IN u4Byte offset,
- IN pu4Byte data
+ IN u4Byte offset
);
typedef VOID
(*BFP_BTC_DISP_DBG_MSG)(
@@ -620,50 +768,95 @@ typedef COL_H2C_STATUS
IN u1Byte h2c_par_len
);
-typedef u4Byte
+typedef u4Byte
(*BFP_BTC_GET_BT_COEX_SUPPORTED_FEATURE)(
- IN PVOID pBtcContext
+ IN PVOID pBtcContext
);
-typedef u4Byte
+typedef u4Byte
(*BFP_BTC_GET_BT_COEX_SUPPORTED_VERSION)(
- IN PVOID pBtcContext
+ IN PVOID pBtcContext
);
-typedef u4Byte
+typedef u4Byte
(*BFP_BTC_GET_PHYDM_VERSION)(
- IN PVOID pBtcContext
- );
-
-typedef struct _BTC_BT_INFO{
- BOOLEAN bBtDisabled;
- u1Byte rssiAdjustForAgcTableOn;
- u1Byte rssiAdjustFor1AntCoexType;
- BOOLEAN bPreBtCtrlAggBufSize;
- BOOLEAN bBtCtrlAggBufSize;
- BOOLEAN bPreRejectAggPkt;
- BOOLEAN bRejectAggPkt;
- BOOLEAN bIncreaseScanDevNum;
- BOOLEAN bBtTxRxMask;
- u1Byte preAggBufSize;
- u1Byte aggBufSize;
- BOOLEAN bBtBusy;
- BOOLEAN bLimitedDig;
- u2Byte btHciVer;
- u2Byte btRealFwVer;
- u1Byte btFwVer;
- u4Byte getBtFwVerCnt;
- BOOLEAN bMiracastPlusBt;
-
- BOOLEAN bBtDisableLowPwr;
-
- BOOLEAN bBtCtrlLps;
- BOOLEAN bBtLpsOn;
- BOOLEAN bForceToRoam; // for 1Ant solution
- u1Byte lpsVal;
- u1Byte rpwmVal;
- u4Byte raMask;
-} BTC_BT_INFO, *PBTC_BT_INFO;
+ IN PVOID pBtcContext
+ );
+
+typedef VOID
+(*BTC_PHYDM_MODIFY_RA_PCR_THRESHLOD)(
+ IN PVOID pDM_Odm,
+ IN u1Byte RA_offset_direction,
+ IN u1Byte RA_threshold_offset
+ );
+
+typedef u4Byte
+(*BTC_PHYDM_CMNINFOQUERY)(
+ IN PVOID pDM_Odm,
+ IN u1Byte info_type
+ );
+
+typedef VOID
+(*BTC_PHYDM_MODIFY_ANTDIV_HWSW)(
+ IN PVOID pDM_Odm,
+ IN u1Byte type
+ );
+
+typedef u1Byte
+(*BFP_BTC_GET_ANT_DET_VAL_FROM_BT)(
+
+ IN PVOID pBtcContext
+ );
+
+typedef u1Byte
+(*BFP_BTC_GET_BLE_SCAN_TYPE_FROM_BT)(
+ IN PVOID pBtcContext
+ );
+
+typedef u4Byte
+(*BFP_BTC_GET_BLE_SCAN_PARA_FROM_BT)(
+ IN PVOID pBtcContext,
+ IN u1Byte scanType
+ );
+
+typedef BOOLEAN
+(*BFP_BTC_GET_BT_AFH_MAP_FROM_BT)(
+ IN PVOID pBtcContext,
+ IN u1Byte mapType,
+ OUT pu1Byte afhMap
+ );
+
+struct btc_bt_info {
+ boolean bt_disabled;
+ boolean bt_enable_disable_change;
+ u8 rssi_adjust_for_agc_table_on;
+ u8 rssi_adjust_for_1ant_coex_type;
+ boolean pre_bt_ctrl_agg_buf_size;
+ boolean bt_ctrl_agg_buf_size;
+ boolean pre_reject_agg_pkt;
+ boolean reject_agg_pkt;
+ boolean increase_scan_dev_num;
+ boolean bt_tx_rx_mask;
+ u8 pre_agg_buf_size;
+ u8 agg_buf_size;
+ boolean bt_busy;
+ boolean limited_dig;
+ u16 bt_hci_ver;
+ u16 bt_real_fw_ver;
+ u8 bt_fw_ver;
+ u32 get_bt_fw_ver_cnt;
+ u32 bt_get_fw_ver;
+ boolean miracast_plus_bt;
+
+ boolean bt_disable_low_pwr;
+
+ boolean bt_ctrl_lps;
+ boolean bt_lps_on;
+ boolean force_to_roam; /* for 1Ant solution */
+ u8 lps_val;
+ u8 rpwm_val;
+ u32 ra_mask;
+};
struct btc_stack_info {
boolean profile_notified;
@@ -695,45 +888,57 @@ struct btc_bt_link_info {
boolean acl_busy;
};
-typedef struct _BTC_STATISTICS{
- u4Byte cntBind;
- u4Byte cntPowerOn;
- u4Byte cntPreLoadFirmware;
- u4Byte cntInitHwConfig;
- u4Byte cntInitCoexDm;
- u4Byte cntIpsNotify;
- u4Byte cntLpsNotify;
- u4Byte cntScanNotify;
- u4Byte cntConnectNotify;
- u4Byte cntMediaStatusNotify;
- u4Byte cntSpecificPacketNotify;
- u4Byte cntBtInfoNotify;
- u4Byte cntRfStatusNotify;
- u4Byte cntPeriodical;
- u4Byte cntCoexDmSwitch;
- u4Byte cntStackOperationNotify;
- u4Byte cntDbgCtrl;
-} BTC_STATISTICS, *PBTC_STATISTICS;
-
-struct btc_coexist{
- BOOLEAN bBinded; // make sure only one adapter can bind the data context
- PVOID Adapter; // default adapter
+#ifdef CONFIG_RF4CE_COEXIST
+struct btc_rf4ce_info {
+ u8 link_state;
+};
+#endif
+
+struct btc_statistics {
+ u32 cnt_bind;
+ u32 cnt_power_on;
+ u32 cnt_pre_load_firmware;
+ u32 cnt_init_hw_config;
+ u32 cnt_init_coex_dm;
+ u32 cnt_ips_notify;
+ u32 cnt_lps_notify;
+ u32 cnt_scan_notify;
+ u32 cnt_connect_notify;
+ u32 cnt_media_status_notify;
+ u32 cnt_specific_packet_notify;
+ u32 cnt_bt_info_notify;
+ u32 cnt_rf_status_notify;
+ u32 cnt_periodical;
+ u32 cnt_coex_dm_switch;
+ u32 cnt_stack_operation_notify;
+ u32 cnt_dbg_ctrl;
+ u32 cnt_rate_id_notify;
+};
+
+struct btc_coexist {
+ BOOLEAN bBinded; /*make sure only one adapter can bind the data context*/
+ PVOID Adapter; /*default adapter*/
struct btc_board_info board_info;
- BTC_BT_INFO btInfo; // some bt info referenced by non-bt module
+ struct btc_bt_info bt_info; /*some bt info referenced by non-bt module*/
struct btc_stack_info stack_info;
struct btc_bt_link_info bt_link_info;
+
+#ifdef CONFIG_RF4CE_COEXIST
+ struct btc_rf4ce_info rf4ce_info;
+#endif
BTC_CHIP_INTERFACE chip_interface;
+ PVOID odm_priv;
BOOLEAN initilized;
BOOLEAN stop_coex_dm;
BOOLEAN manual_control;
BOOLEAN bdontenterLPS;
pu1Byte cli_buf;
- BTC_STATISTICS statistics;
+ struct btc_statistics statistics;
u1Byte pwrModeVal[10];
- // function pointers
- // io related
+ /* function pointers */
+ /* io related */
BFP_BTC_R1 btc_read_1byte;
BFP_BTC_W1 btc_write_1byte;
BFP_BTC_W1_BIT_MASK btc_write_1byte_bitmask;
@@ -742,19 +947,19 @@ struct btc_coexist{
BFP_BTC_R4 btc_read_4byte;
BFP_BTC_W4 btc_write_4byte;
BFP_BTC_LOCAL_REG_W1 btc_write_local_reg_1byte;
- // read/write bb related
+ /* read/write bb related */
BFP_BTC_SET_BB_REG btc_set_bb_reg;
BFP_BTC_GET_BB_REG btc_get_bb_reg;
- // read/write rf related
+ /* read/write rf related */
BFP_BTC_SET_RF_REG btc_set_rf_reg;
BFP_BTC_GET_RF_REG btc_get_rf_reg;
- // fill h2c related
+ /* fill h2c related */
BFP_BTC_FILL_H2C btc_fill_h2c;
- // other
+ /* other */
BFP_BTC_DISP_DBG_MSG btc_disp_dbg_msg;
- // normal get/set related
+ /* normal get/set related */
BFP_BTC_GET btc_get;
BFP_BTC_SET btc_set;
@@ -764,9 +969,17 @@ struct btc_coexist{
BFP_BTC_SET_BT_ANT_DETECTION btc_set_bt_ant_detection;
BFP_BTC_COEX_H2C_PROCESS btc_coex_h2c_process;
+ BFP_BTC_SET_BT_TRX_MASK btc_set_bt_trx_mask;
BFP_BTC_GET_BT_COEX_SUPPORTED_FEATURE btc_get_bt_coex_supported_feature;
BFP_BTC_GET_BT_COEX_SUPPORTED_VERSION btc_get_bt_coex_supported_version;
BFP_BTC_GET_PHYDM_VERSION btc_get_bt_phydm_version;
+ BTC_PHYDM_MODIFY_RA_PCR_THRESHLOD btc_phydm_modify_RA_PCR_threshold;
+ BTC_PHYDM_CMNINFOQUERY btc_phydm_query_PHY_counter;
+ BTC_PHYDM_MODIFY_ANTDIV_HWSW btc_phydm_modify_ANTDIV_HwSw;
+ BFP_BTC_GET_ANT_DET_VAL_FROM_BT btc_get_ant_det_val_from_bt;
+ BFP_BTC_GET_BLE_SCAN_TYPE_FROM_BT btc_get_ble_scan_type_from_bt;
+ BFP_BTC_GET_BLE_SCAN_PARA_FROM_BT btc_get_ble_scan_para_from_bt;
+ BFP_BTC_GET_BT_AFH_MAP_FROM_BT btc_get_bt_afh_map_from_bt;
};
typedef struct btc_coexist *PBTC_COEXIST;
@@ -774,7 +987,7 @@ extern struct btc_coexist GLBtCoexist;
BOOLEAN
EXhalbtcoutsrc_InitlizeVariables(
- IN PVOID Adapter
+ IN PVOID Adapter
);
VOID
EXhalbtcoutsrc_PowerOnSetting(
@@ -809,6 +1022,11 @@ EXhalbtcoutsrc_ScanNotify(
IN u1Byte type
);
VOID
+EXhalbtcoutsrc_SetAntennaPathNotify(
+ IN PBTC_COEXIST pBtCoexist,
+ IN u1Byte type
+ );
+VOID
EXhalbtcoutsrc_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte action
@@ -832,7 +1050,19 @@ EXhalbtcoutsrc_BtInfoNotify(
VOID
EXhalbtcoutsrc_RfStatusNotify(
IN PBTC_COEXIST pBtCoexist,
- IN u1Byte type
+ IN u1Byte type
+ );
+VOID
+EXhalbtcoutsrc_WlFwDbgInfoNotify(
+ IN PBTC_COEXIST pBtCoexist,
+ IN pu1Byte tmpBuf,
+ IN u1Byte length
+ );
+VOID
+EXhalbtcoutsrc_rx_rate_change_notify(
+ IN PBTC_COEXIST pBtCoexist,
+ IN BOOLEAN is_data_frame,
+ IN u1Byte btc_rate_id
);
VOID
EXhalbtcoutsrc_StackOperationNotify(
@@ -849,12 +1079,6 @@ EXhalbtcoutsrc_PnpNotify(
IN u1Byte pnpState
);
VOID
-EXhalbtcoutsrc_ScoreBoardStatusNotify(
- IN PBTC_COEXIST pBtCoexist,
- IN pu1Byte tmpBuf,
- IN u1Byte length
- );
-VOID
EXhalbtcoutsrc_CoexDmSwitch(
IN PBTC_COEXIST pBtCoexist
);
diff --git a/hal/btc/Mp_Precomp.h b/hal/btc/mp_precomp.h
similarity index 53%
rename from hal/btc/Mp_Precomp.h
rename to hal/btc/mp_precomp.h
index d5ebdbf..2c333c2 100644
--- a/hal/btc/Mp_Precomp.h
+++ b/hal/btc/mp_precomp.h
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2013 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2013 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,12 +11,7 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#ifndef __MP_PRECOMP_H__
#define __MP_PRECOMP_H__
@@ -41,10 +36,10 @@
#define WPP_SOFTWARE_TRACE 0
-typedef enum _BTC_MSG_COMP_TYPE{
+typedef enum _BTC_MSG_COMP_TYPE {
COMP_COEX = 0,
COMP_MAX
-}BTC_MSG_COMP_TYPE;
+} BTC_MSG_COMP_TYPE;
extern u4Byte GLBtcDbgType[];
#define DBG_OFF 0
@@ -54,21 +49,6 @@ extern u4Byte GLBtcDbgType[];
#define DBG_LOUD 4
#define DBG_TRACE 5
-#if DBG
-#ifdef RT_TRACE
-#undef RT_TRACE
-#define RT_TRACE(dbgtype, dbgflag, printstr)\
-do {\
- if (GLBtcDbgType[dbgtype] & BIT(dbgflag))\
- {\
- DbgPrint printstr;\
- }\
-} while (0)
-#endif
-#else
-#define RT_TRACE(dbgtype, dbgflag, printstr)
-#endif
-
#ifdef CONFIG_BT_COEXIST
#define BT_SUPPORT 1
#define COEX_SUPPORT 1
@@ -79,24 +59,69 @@ do {\
#define HS_SUPPORT 0
#endif
-#include "HalBtcOutSrc.h"
-#include "HalBtc8188c2Ant.h"
-#include "HalBtc8192d2Ant.h"
-#include "HalBtc8192e1Ant.h"
-#include "HalBtc8192e2Ant.h"
-#include "HalBtc8723a1Ant.h"
-#include "HalBtc8723a2Ant.h"
-#include "HalBtc8723b1Ant.h"
-#include "HalBtc8723b2Ant.h"
-#include "HalBtc8812a1Ant.h"
-#include "HalBtc8812a2Ant.h"
-#include "HalBtc8821a1Ant.h"
-#include "HalBtc8821a2Ant.h"
-#include "HalBtc8821aCsr2Ant.h"
-#include "HalBtc8703b1Ant.h"
+#include "halbtcoutsrc.h"
+
+/* for wifi only mode */
+#include "hal_btcoex_wifionly.h"
+
+#ifdef CONFIG_BT_COEXIST
+
+#ifdef CONFIG_RTL8192E
+#include "halbtc8192e1ant.h"
+#include "halbtc8192e2ant.h"
+#endif
+
+#ifdef CONFIG_RTL8723B
+#include "halbtc8723bwifionly.h"
+#include "halbtc8723b1ant.h"
+#include "halbtc8723b2ant.h"
+#endif
+
+#ifdef CONFIG_RTL8812A
+#include "halbtc8812a1ant.h"
+#include "halbtc8812a2ant.h"
+#endif
+
+#ifdef CONFIG_RTL8821A
+#include "halbtc8821a1ant.h"
+#include "halbtc8821a2ant.h"
+#endif
+
+#ifdef CONFIG_RTL8703B
+#include "halbtc8703b1ant.h"
+#endif
+
+#ifdef CONFIG_RTL8723D
#include "halbtc8723d1ant.h"
#include "halbtc8723d2ant.h"
-#include "HalBtc8822b1Ant.h"
+#endif
+
+#ifdef CONFIG_RTL8822B
+#include "halbtc8822bwifionly.h"
+#include "halbtc8822b1ant.h"
+#include "halbtc8822b2ant.h"
+#endif
+
+#ifdef CONFIG_RTL8821C
+#include "halbtc8821cwifionly.h"
+#include "halbtc8821c1ant.h"
+#include "halbtc8821c2ant.h"
+#endif
+
+#else /* CONFIG_BT_COEXIST */
+
+#ifdef CONFIG_RTL8723B
+#include "halbtc8723bwifionly.h"
+#endif
+
+#ifdef CONFIG_RTL8822B
+#include "halbtc8822bwifionly.h"
+#endif
+
+#ifdef CONFIG_RTL8821C
+#include "halbtc8821cwifionly.h"
+#endif
+#endif /* CONFIG_BT_COEXIST */
-#endif // __MP_PRECOMP_H__
+#endif /* __MP_PRECOMP_H__ */
diff --git a/hal/efuse/efuse_mask.h b/hal/efuse/efuse_mask.h
index e1c38c1..8270569 100644
--- a/hal/efuse/efuse_mask.h
+++ b/hal/efuse/efuse_mask.h
@@ -1,98 +1,138 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
#if DEV_BUS_TYPE == RT_USB_INTERFACE
-#if defined(CONFIG_RTL8188E)
- #include "rtl8188e/HalEfuseMask8188E_USB.h"
-#endif
+ #if defined(CONFIG_RTL8188E)
+ #include "rtl8188e/HalEfuseMask8188E_USB.h"
+ #endif
-#if defined(CONFIG_RTL8812A)
- #include "rtl8812a/HalEfuseMask8812A_USB.h"
-#endif
+ #if defined(CONFIG_RTL8812A)
+ #include "rtl8812a/HalEfuseMask8812A_USB.h"
+ #endif
-#if defined(CONFIG_RTL8821A)
- #include "rtl8812a/HalEfuseMask8821A_USB.h"
-#endif
+ #if defined(CONFIG_RTL8821A)
+ #include "rtl8812a/HalEfuseMask8821A_USB.h"
+ #endif
-#if defined(CONFIG_RTL8192E)
- #include "rtl8192e/HalEfuseMask8192E_USB.h"
-#endif
+ #if defined(CONFIG_RTL8192E)
+ #include "rtl8192e/HalEfuseMask8192E_USB.h"
+ #endif
-#if defined(CONFIG_RTL8723B)
- #include "rtl8723b/HalEfuseMask8723B_USB.h"
-#endif
+ #if defined(CONFIG_RTL8723B)
+ #include "rtl8723b/HalEfuseMask8723B_USB.h"
+ #endif
-#if defined(CONFIG_RTL8814A)
- #include "rtl8814a/HalEfuseMask8814A_USB.h"
-#endif
+ #if defined(CONFIG_RTL8814A)
+ #include "rtl8814a/HalEfuseMask8814A_USB.h"
+ #endif
-#if defined(CONFIG_RTL8703B)
- #include "rtl8703b/HalEfuseMask8703B_USB.h"
-#endif
+ #if defined(CONFIG_RTL8703B)
+ #include "rtl8703b/HalEfuseMask8703B_USB.h"
+ #endif
-#if defined(CONFIG_RTL8723D)
- #include "rtl8723d/HalEfuseMask8723D_USB.h"
-#endif
+ #if defined(CONFIG_RTL8723D)
+ #include "rtl8723d/HalEfuseMask8723D_USB.h"
+ #endif
-#if defined(CONFIG_RTL8188F)
- #include "rtl8188f/HalEfuseMask8188F_USB.h"
-#endif
+ #if defined(CONFIG_RTL8188F)
+ #include "rtl8188f/HalEfuseMask8188F_USB.h"
+ #endif
-#if defined(CONFIG_RTL8822B)
- #include "rtl8822b/HalEfuseMask8822B_USB.h"
-#endif
+ #if defined(CONFIG_RTL8822B)
+ #include "rtl8822b/HalEfuseMask8822B_USB.h"
+ #endif
+
+ #if defined(CONFIG_RTL8821C)
+ #include "rtl8821c/HalEfuseMask8821C_USB.h"
+ #endif
#elif DEV_BUS_TYPE == RT_PCI_INTERFACE
-#if defined(CONFIG_RTL8188E)
- #include "rtl8188e/HalEfuseMask8188E_PCIE.h"
-#endif
+ #if defined(CONFIG_RTL8188E)
+ #include "rtl8188e/HalEfuseMask8188E_PCIE.h"
+ #endif
-#if defined(CONFIG_RTL8812A)
- #include "rtl8812a/HalEfuseMask8812A_PCIE.h"
-#endif
+ #if defined(CONFIG_RTL8812A)
+ #include "rtl8812a/HalEfuseMask8812A_PCIE.h"
+ #endif
-#if defined(CONFIG_RTL8821A)
- #include "rtl8812a/HalEfuseMask8821A_PCIE.h"
-#endif
+ #if defined(CONFIG_RTL8821A)
+ #include "rtl8812a/HalEfuseMask8821A_PCIE.h"
+ #endif
-#if defined(CONFIG_RTL8192E)
- #include "rtl8192e/HalEfuseMask8192E_PCIE.h"
-#endif
+ #if defined(CONFIG_RTL8192E)
+ #include "rtl8192e/HalEfuseMask8192E_PCIE.h"
+ #endif
-#if defined(CONFIG_RTL8723B)
- #include "rtl8723b/HalEfuseMask8723B_PCIE.h"
-#endif
+ #if defined(CONFIG_RTL8723B)
+ #include "rtl8723b/HalEfuseMask8723B_PCIE.h"
+ #endif
-#if defined(CONFIG_RTL8814A)
- #include "rtl8814a/HalEfuseMask8814A_PCIE.h"
-#endif
+ #if defined(CONFIG_RTL8814A)
+ #include "rtl8814a/HalEfuseMask8814A_PCIE.h"
+ #endif
-#if defined(CONFIG_RTL8703B)
- #include "rtl8703b/HalEfuseMask8703B_PCIE.h"
-#endif
+ #if defined(CONFIG_RTL8703B)
+ #include "rtl8703b/HalEfuseMask8703B_PCIE.h"
+ #endif
-#if defined(CONFIG_RTL8822B)
- #include "rtl8822b/HalEfuseMask8822B_PCIE.h"
-#endif
-#if defined(CONFIG_RTL8723D)
- #include "rtl8723d/HalEfuseMask8723D_PCIE.h"
-#endif
+ #if defined(CONFIG_RTL8822B)
+ #include "rtl8822b/HalEfuseMask8822B_PCIE.h"
+ #endif
+ #if defined(CONFIG_RTL8723D)
+ #include "rtl8723d/HalEfuseMask8723D_PCIE.h"
+ #endif
+ #if defined(CONFIG_RTL8821C)
+ #include "rtl8821c/HalEfuseMask8821C_PCIE.h"
+ #endif
#elif DEV_BUS_TYPE == RT_SDIO_INTERFACE
+ #if defined(CONFIG_RTL8723B)
+ #include "rtl8723b/HalEfuseMask8723B_SDIO.h"
+ #endif
-#if defined(CONFIG_RTL8188E)
- #include "rtl8188e/HalEfuseMask8188E_SDIO.h"
-#endif
+ #if defined(CONFIG_RTL8188E)
+ #include "rtl8188e/HalEfuseMask8188E_SDIO.h"
+ #endif
-#if defined(CONFIG_RTL8703B)
- #include "rtl8703b/HalEfuseMask8703B_SDIO.h"
-#endif
+ #if defined(CONFIG_RTL8703B)
+ #include "rtl8703b/HalEfuseMask8703B_SDIO.h"
+ #endif
-#if defined(CONFIG_RTL8188F)
- #include "rtl8188f/HalEfuseMask8188F_SDIO.h"
-#endif
+ #if defined(CONFIG_RTL8188F)
+ #include "rtl8188f/HalEfuseMask8188F_SDIO.h"
+ #endif
-#if defined(CONFIG_RTL8723D)
- #include "rtl8723d/HalEfuseMask8723D_SDIO.h"
-#endif
+ #if defined(CONFIG_RTL8723D)
+ #include "rtl8723d/HalEfuseMask8723D_SDIO.h"
+ #endif
+
+ #if defined(CONFIG_RTL8192E)
+ #include "rtl8192e/HalEfuseMask8192E_SDIO.h"
+ #endif
+
+ #if defined(CONFIG_RTL8821A)
+ #include "rtl8812a/HalEfuseMask8821A_SDIO.h"
+ #endif
+
+ #if defined(CONFIG_RTL8821C)
+ #include "rtl8821c/HalEfuseMask8821C_SDIO.h"
+ #endif
+
+ #if defined(CONFIG_RTL8822B)
+ #include "rtl8822b/HalEfuseMask8822B_SDIO.h"
+ #endif
#endif
diff --git a/hal/efuse/rtl8822b/HalEfuseMask8822B_PCIE.c b/hal/efuse/rtl8822b/HalEfuseMask8822B_PCIE.c
index 8e072a8..d8d61b9 100644
--- a/hal/efuse/rtl8822b/HalEfuseMask8822B_PCIE.c
+++ b/hal/efuse/rtl8822b/HalEfuseMask8822B_PCIE.c
@@ -1,22 +1,17 @@
/******************************************************************************
-*
-* Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved.
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of version 2 of the GNU General Public License as
-* published by the Free Software Foundation.
-*
-* This program is distributed in the hope that it will be useful, but WITHOUT
-* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-* more details.
-*
-* You should have received a copy of the GNU General Public License along with
-* this program; if not, write to the Free Software Foundation, Inc.,
-* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
-*
-*
-******************************************************************************/
+ *
+ * Copyright(c) 2015 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
#include
#include "HalEfuseMask8822B_PCIE.h"
@@ -37,7 +32,7 @@ u1Byte Array_MP_8822B_MPCIE[] = {
0x00,
0x00,
0x00,
- 0x0F,
+ 0x03,
0xF7,
0xFF,
0xFF,
@@ -75,7 +70,6 @@ u1Byte Array_MP_8822B_MPCIE[] = {
0x00,
0x00,
-
};
u2Byte
diff --git a/hal/efuse/rtl8822b/HalEfuseMask8822B_PCIE.h b/hal/efuse/rtl8822b/HalEfuseMask8822B_PCIE.h
index e863d6a..af3faaa 100644
--- a/hal/efuse/rtl8822b/HalEfuseMask8822B_PCIE.h
+++ b/hal/efuse/rtl8822b/HalEfuseMask8822B_PCIE.h
@@ -1,22 +1,17 @@
/******************************************************************************
-*
-* Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved.
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of version 2 of the GNU General Public License as
-* published by the Free Software Foundation.
-*
-* This program is distributed in the hope that it will be useful, but WITHOUT
-* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-* more details.
-*
-* You should have received a copy of the GNU General Public License along with
-* this program; if not, write to the Free Software Foundation, Inc.,
-* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
-*
-*
-******************************************************************************/
+ *
+ * Copyright(c) 2015 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
/******************************************************************************
diff --git a/hal/efuse/rtl8822b/HalEfuseMask8822B_SDIO.c b/hal/efuse/rtl8822b/HalEfuseMask8822B_SDIO.c
new file mode 100644
index 0000000..313fa8d
--- /dev/null
+++ b/hal/efuse/rtl8822b/HalEfuseMask8822B_SDIO.c
@@ -0,0 +1,100 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2015 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#include
+
+#include "HalEfuseMask8822B_SDIO.h"
+
+/******************************************************************************
+* MSDIO.TXT
+******************************************************************************/
+
+u1Byte Array_MP_8822B_MSDIO[] = {
+0xFF,
+0xF7,
+0xEF,
+0xDE,
+0xFC,
+0xFB,
+0x10,
+0x00,
+0x00,
+0x00,
+0x00,
+0x03,
+0xF7,
+0xFF,
+0xFF,
+0xFF,
+0xFF,
+0xFF,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+
+};
+
+u2Byte EFUSE_GetArrayLen_MP_8822B_MSDIO(VOID)
+{
+ return sizeof(Array_MP_8822B_MSDIO) / sizeof(u1Byte);
+}
+
+VOID EFUSE_GetMaskArray_MP_8822B_MSDIO(pu1Byte Array)
+{
+ u2Byte len = EFUSE_GetArrayLen_MP_8822B_MSDIO(), i = 0;
+
+ for (i = 0; i < len; ++i)
+ Array[i] = Array_MP_8822B_MSDIO[i];
+}
+
+BOOLEAN EFUSE_IsAddressMasked_MP_8822B_MSDIO(u2Byte Offset)
+{
+ int r = Offset / 16;
+ int c = (Offset % 16) / 2;
+ int result = 0;
+
+ if (c < 4) /*Upper double word*/
+ result = (Array_MP_8822B_MSDIO[r] & (0x10 << c));
+ else
+ result = (Array_MP_8822B_MSDIO[r] & (0x01 << (c - 4)));
+
+ return (result > 0) ? 0 : 1;
+}
diff --git a/hal/efuse/rtl8822b/HalEfuseMask8822B_SDIO.h b/hal/efuse/rtl8822b/HalEfuseMask8822B_SDIO.h
new file mode 100644
index 0000000..7ace94e
--- /dev/null
+++ b/hal/efuse/rtl8822b/HalEfuseMask8822B_SDIO.h
@@ -0,0 +1,27 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2015 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+
+
+/******************************************************************************
+* MSDIO.TXT
+******************************************************************************/
+
+
+u2Byte EFUSE_GetArrayLen_MP_8822B_MSDIO(VOID);
+
+VOID EFUSE_GetMaskArray_MP_8822B_MSDIO(pu1Byte Array);
+
+BOOLEAN EFUSE_IsAddressMasked_MP_8822B_MSDIO(u2Byte Offset);
diff --git a/hal/efuse/rtl8822b/HalEfuseMask8822B_USB.c b/hal/efuse/rtl8822b/HalEfuseMask8822B_USB.c
index 84dfde4..532d8b2 100644
--- a/hal/efuse/rtl8822b/HalEfuseMask8822B_USB.c
+++ b/hal/efuse/rtl8822b/HalEfuseMask8822B_USB.c
@@ -1,22 +1,17 @@
/******************************************************************************
-*
-* Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved.
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of version 2 of the GNU General Public License as
-* published by the Free Software Foundation.
-*
-* This program is distributed in the hope that it will be useful, but WITHOUT
-* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-* more details.
-*
-* You should have received a copy of the GNU General Public License along with
-* this program; if not, write to the Free Software Foundation, Inc.,
-* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
-*
-*
-******************************************************************************/
+ *
+ * Copyright(c) 2015 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
#include
#include "HalEfuseMask8822B_USB.h"
@@ -37,15 +32,15 @@ u1Byte Array_MP_8822B_MUSB[] = {
0x00,
0x00,
0x00,
- 0x0F,
+ 0x03,
0xF7,
0x00,
0x00,
0x00,
0xFF,
0xFF,
- 0xF3,
- 0x00,
+ 0xFF,
+ 0xFF,
0xF0,
0x00,
0x00,
@@ -56,9 +51,7 @@ u1Byte Array_MP_8822B_MUSB[] = {
0x00,
0x00,
0x00,
- 0x08,
0x00,
- 0x80,
0x00,
0x00,
0x00,
@@ -74,7 +67,8 @@ u1Byte Array_MP_8822B_MUSB[] = {
0x00,
0x00,
0x00,
-
+ 0x00,
+ 0x00,
};
u2Byte EFUSE_GetArrayLen_MP_8822B_MUSB(VOID)
diff --git a/hal/efuse/rtl8822b/HalEfuseMask8822B_USB.h b/hal/efuse/rtl8822b/HalEfuseMask8822B_USB.h
index b98ef77..ef368f2 100644
--- a/hal/efuse/rtl8822b/HalEfuseMask8822B_USB.h
+++ b/hal/efuse/rtl8822b/HalEfuseMask8822B_USB.h
@@ -1,22 +1,17 @@
/******************************************************************************
-*
-* Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved.
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of version 2 of the GNU General Public License as
-* published by the Free Software Foundation.
-*
-* This program is distributed in the hope that it will be useful, but WITHOUT
-* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-* more details.
-*
-* You should have received a copy of the GNU General Public License along with
-* this program; if not, write to the Free Software Foundation, Inc.,
-* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
-*
-*
-******************************************************************************/
+ *
+ * Copyright(c) 2015 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
diff --git a/hal/hal_btcoex.c b/hal/hal_btcoex.c
index 4e213e7..9e63f2c 100644
--- a/hal/hal_btcoex.c
+++ b/hal/hal_btcoex.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2013 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2013 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,19 +11,14 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#define __HAL_BTCOEX_C__
#ifdef CONFIG_BT_COEXIST
#include
#include
-#include
+#include "btc/mp_precomp.h"
/* ************************************
* Global variables
@@ -166,10 +161,25 @@ typedef enum _bt_c2h_status {
/* C2H BT OP CODES */
typedef enum _bt_op_code {
- BT_OP_GET_BT_VERSION = 0,
- BT_OP_WRITE_REG_ADDR = 12,
- BT_OP_WRITE_REG_VALUE,
- BT_OP_READ_REG = 17
+ BT_OP_GET_BT_VERSION = 0x00,
+ BT_OP_WRITE_REG_ADDR = 0x0c,
+ BT_OP_WRITE_REG_VALUE = 0x0d,
+
+ BT_OP_READ_REG = 0x11,
+
+ BT_LO_OP_GET_AFH_MAP_L = 0x1e,
+ BT_LO_OP_GET_AFH_MAP_M = 0x1f,
+ BT_LO_OP_GET_AFH_MAP_H = 0x20,
+
+ BT_OP_GET_BT_COEX_SUPPORTED_FEATURE = 0x2a,
+ BT_OP_GET_BT_COEX_SUPPORTED_VERSION = 0x2b,
+ BT_OP_GET_BT_ANT_DET_VAL = 0x2c,
+ BT_OP_GET_BT_BLE_SCAN_TYPE = 0x2d,
+ BT_OP_GET_BT_BLE_SCAN_PARA = 0x2e,
+ BT_OP_GET_BT_DEVICE_INFO = 0x30,
+ BT_OP_GET_BT_FORBIDDEN_SLOT_VAL = 0x31,
+ BT_OP_SET_BT_LANCONSTRAIN_LEVEL = 0x32,
+ BT_OP_MAX
} BT_OP_CODE;
#define BTC_MPOPER_TIMEOUT 50 /* unit: ms */
@@ -266,6 +276,22 @@ static u8 halbtcoutsrc_IsCsrBtCoex(PBTC_COEXIST pBtCoexist)
return _FALSE;
}
+static void halbtcoutsrc_EnterPwrLock(PBTC_COEXIST pBtCoexist)
+{
+ struct dvobj_priv *dvobj = adapter_to_dvobj((PADAPTER)pBtCoexist->Adapter);
+ struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
+
+ _enter_pwrlock(&pwrpriv->lock);
+}
+
+static void halbtcoutsrc_ExitPwrLock(PBTC_COEXIST pBtCoexist)
+{
+ struct dvobj_priv *dvobj = adapter_to_dvobj((PADAPTER)pBtCoexist->Adapter);
+ struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
+
+ _exit_pwrlock(&pwrpriv->lock);
+}
+
static u8 halbtcoutsrc_IsHwMailboxExist(PBTC_COEXIST pBtCoexist)
{
if (pBtCoexist->board_info.bt_chip_type == BTC_CHIP_CSR_BC4
@@ -278,17 +304,17 @@ static u8 halbtcoutsrc_IsHwMailboxExist(PBTC_COEXIST pBtCoexist)
return _TRUE;
}
-static void halbtcoutsrc_LeaveLps(PBTC_COEXIST pBtCoexist)
+static u8 halbtcoutsrc_LeaveLps(PBTC_COEXIST pBtCoexist)
{
PADAPTER padapter;
padapter = pBtCoexist->Adapter;
- pBtCoexist->btInfo.bBtCtrlLps = _TRUE;
- pBtCoexist->btInfo.bBtLpsOn = _FALSE;
+ pBtCoexist->bt_info.bt_ctrl_lps = _TRUE;
+ pBtCoexist->bt_info.bt_lps_on = _FALSE;
- rtw_btcoex_LPS_Leave(padapter);
+ return rtw_btcoex_LPS_Leave(padapter);
}
void halbtcoutsrc_EnterLps(PBTC_COEXIST pBtCoexist)
@@ -299,8 +325,8 @@ void halbtcoutsrc_EnterLps(PBTC_COEXIST pBtCoexist)
padapter = pBtCoexist->Adapter;
if (pBtCoexist->bdontenterLPS == _FALSE) {
- pBtCoexist->btInfo.bBtCtrlLps = _TRUE;
- pBtCoexist->btInfo.bBtLpsOn = _TRUE;
+ pBtCoexist->bt_info.bt_ctrl_lps = _TRUE;
+ pBtCoexist->bt_info.bt_lps_on = _TRUE;
rtw_btcoex_LPS_Enter(padapter);
}
@@ -311,18 +337,17 @@ void halbtcoutsrc_NormalLps(PBTC_COEXIST pBtCoexist)
PADAPTER padapter;
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Normal LPS behavior!!!\n"));
padapter = pBtCoexist->Adapter;
- if (pBtCoexist->btInfo.bBtCtrlLps) {
- pBtCoexist->btInfo.bBtLpsOn = _FALSE;
+ if (pBtCoexist->bt_info.bt_ctrl_lps) {
+ pBtCoexist->bt_info.bt_lps_on = _FALSE;
rtw_btcoex_LPS_Leave(padapter);
- pBtCoexist->btInfo.bBtCtrlLps = _FALSE;
+ pBtCoexist->bt_info.bt_ctrl_lps = _FALSE;
/* recover the LPS state to the original */
#if 0
- padapter->HalFunc.UpdateLPSStatusHandler(
+ padapter->hal_func.UpdateLPSStatusHandler(
padapter,
pPSC->RegLeisurePsMode,
pPSC->RegPowerSaveMode);
@@ -330,6 +355,24 @@ void halbtcoutsrc_NormalLps(PBTC_COEXIST pBtCoexist)
}
}
+void halbtcoutsrc_Pre_NormalLps(PBTC_COEXIST pBtCoexist)
+{
+ PADAPTER padapter;
+
+ padapter = pBtCoexist->Adapter;
+
+ if (pBtCoexist->bt_info.bt_ctrl_lps) {
+ pBtCoexist->bt_info.bt_lps_on = _FALSE;
+ rtw_btcoex_LPS_Leave(padapter);
+ }
+}
+
+void halbtcoutsrc_Post_NormalLps(PBTC_COEXIST pBtCoexist)
+{
+ if (pBtCoexist->bt_info.bt_ctrl_lps)
+ pBtCoexist->bt_info.bt_ctrl_lps = _FALSE;
+}
+
/*
* Constraint:
* 1. this function will request pwrctrl->lock
@@ -341,7 +384,7 @@ void halbtcoutsrc_LeaveLowPower(PBTC_COEXIST pBtCoexist)
PHAL_DATA_TYPE pHalData;
struct pwrctrl_priv *pwrctrl;
s32 ready;
- u32 stime;
+ systime stime;
s32 utime;
u32 timeout; /* unit: ms */
@@ -397,7 +440,7 @@ void halbtcoutsrc_NormalLowPower(PBTC_COEXIST pBtCoexist)
void halbtcoutsrc_DisableLowPower(PBTC_COEXIST pBtCoexist, u8 bLowPwrDisable)
{
- pBtCoexist->btInfo.bBtDisableLowPwr = bLowPwrDisable;
+ pBtCoexist->bt_info.bt_disable_low_pwr = bLowPwrDisable;
if (bLowPwrDisable)
halbtcoutsrc_LeaveLowPower(pBtCoexist); /* leave 32k low power. */
else
@@ -425,26 +468,26 @@ void halbtcoutsrc_AggregationCheck(PBTC_COEXIST pBtCoexist)
else
preTime = curTime;
- if (pBtCoexist->btInfo.bRejectAggPkt) {
+ if (pBtCoexist->bt_info.reject_agg_pkt) {
bNeedToAct = _TRUE;
- pBtCoexist->btInfo.bPreRejectAggPkt = pBtCoexist->btInfo.bRejectAggPkt;
+ pBtCoexist->bt_info.pre_reject_agg_pkt = pBtCoexist->bt_info.reject_agg_pkt;
} else {
- if (pBtCoexist->btInfo.bPreRejectAggPkt) {
+ if (pBtCoexist->bt_info.pre_reject_agg_pkt) {
bNeedToAct = _TRUE;
- pBtCoexist->btInfo.bPreRejectAggPkt = pBtCoexist->btInfo.bRejectAggPkt;
+ pBtCoexist->bt_info.pre_reject_agg_pkt = pBtCoexist->bt_info.reject_agg_pkt;
}
- if (pBtCoexist->btInfo.bPreBtCtrlAggBufSize !=
- pBtCoexist->btInfo.bBtCtrlAggBufSize) {
+ if (pBtCoexist->bt_info.pre_bt_ctrl_agg_buf_size !=
+ pBtCoexist->bt_info.bt_ctrl_agg_buf_size) {
bNeedToAct = _TRUE;
- pBtCoexist->btInfo.bPreBtCtrlAggBufSize = pBtCoexist->btInfo.bBtCtrlAggBufSize;
+ pBtCoexist->bt_info.pre_bt_ctrl_agg_buf_size = pBtCoexist->bt_info.bt_ctrl_agg_buf_size;
}
- if (pBtCoexist->btInfo.bBtCtrlAggBufSize) {
- if (pBtCoexist->btInfo.preAggBufSize !=
- pBtCoexist->btInfo.aggBufSize)
+ if (pBtCoexist->bt_info.bt_ctrl_agg_buf_size) {
+ if (pBtCoexist->bt_info.pre_agg_buf_size !=
+ pBtCoexist->bt_info.agg_buf_size)
bNeedToAct = _TRUE;
- pBtCoexist->btInfo.preAggBufSize = pBtCoexist->btInfo.aggBufSize;
+ pBtCoexist->bt_info.pre_agg_buf_size = pBtCoexist->bt_info.agg_buf_size;
}
}
@@ -452,9 +495,50 @@ void halbtcoutsrc_AggregationCheck(PBTC_COEXIST pBtCoexist)
rtw_btcoex_rx_ampdu_apply(padapter);
}
+u8 halbtcoutsrc_is_autoload_fail(PBTC_COEXIST pBtCoexist)
+{
+ PADAPTER padapter;
+ PHAL_DATA_TYPE pHalData;
+
+ padapter = pBtCoexist->Adapter;
+ pHalData = GET_HAL_DATA(padapter);
+
+ return pHalData->bautoload_fail_flag;
+}
+
+u8 halbtcoutsrc_is_fw_ready(PBTC_COEXIST pBtCoexist)
+{
+ PADAPTER padapter;
+
+ padapter = pBtCoexist->Adapter;
+
+ return GET_HAL_DATA(padapter)->bFWReady;
+}
+
+u8 halbtcoutsrc_IsDualBandConnected(PADAPTER padapter)
+{
+ u8 ret = BTC_MULTIPORT_SCC;
+
+#ifdef CONFIG_MCC_MODE
+ if (MCC_EN(padapter) && (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))) {
+ struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+ struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
+ u8 band0 = mccobjpriv->iface[0]->mlmeextpriv.cur_channel > 14 ? BAND_ON_5G : BAND_ON_2_4G;
+ u8 band1 = mccobjpriv->iface[1]->mlmeextpriv.cur_channel > 14 ? BAND_ON_5G : BAND_ON_2_4G;
+
+ if (band0 != band1)
+ ret = BTC_MULTIPORT_MCC_DUAL_BAND;
+ else
+ ret = BTC_MULTIPORT_MCC_DUAL_CHANNEL;
+ }
+#endif
+
+ return ret;
+}
+
u8 halbtcoutsrc_IsWifiBusy(PADAPTER padapter)
{
- if (rtw_mi_check_status(padapter, MI_AP_MODE))
+ if (rtw_mi_check_status(padapter, MI_AP_ASSOC))
return _TRUE;
if (rtw_mi_busy_traffic_check(padapter, _FALSE))
return _TRUE;
@@ -531,22 +615,10 @@ u32 halbtcoutsrc_GetWifiLinkStatus(PBTC_COEXIST pBtCoexist)
return retVal;
}
-static u8 _is_btfwver_valid(PBTC_COEXIST pBtCoexist, u16 btfwver)
-{
- if (!btfwver)
- return _FALSE;
-
- if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter))
- if (btfwver == 0x8723)
- return _FALSE;
-
- return _TRUE;
-}
-
static void _btmpoper_timer_hdl(void *p)
{
- if (GLBtcBtMpRptWait) {
- GLBtcBtMpRptWait = 0;
+ if (GLBtcBtMpRptWait == _TRUE) {
+ GLBtcBtMpRptWait = _FALSE;
_rtw_up_sema(&GLBtcBtMpRptSema);
}
}
@@ -562,7 +634,6 @@ static u8 _btmpoper_cmd(PBTC_COEXIST pBtCoexist, u8 opcode, u8 opcodever, u8 *cm
u8 buf[H2C_BTMP_OPER_LEN] = {0};
u8 buflen;
u8 seq;
- u8 timer_cancelled;
s32 ret;
@@ -580,33 +651,34 @@ static u8 _btmpoper_cmd(PBTC_COEXIST pBtCoexist, u8 opcode, u8 opcodever, u8 *cm
if (cmd && size)
_rtw_memcpy(buf + 2, cmd, size);
- GLBtcBtMpRptWait = 1;
- GLBtcBtMpRptWiFiOK = 0;
- GLBtcBtMpRptBTOK = 0;
+ GLBtcBtMpRptWait = _TRUE;
+ GLBtcBtMpRptWiFiOK = _FALSE;
+ GLBtcBtMpRptBTOK = _FALSE;
GLBtcBtMpRptStatus = 0;
padapter = pBtCoexist->Adapter;
_set_timer(&GLBtcBtMpOperTimer, BTC_MPOPER_TIMEOUT);
if (rtw_hal_fill_h2c_cmd(padapter, H2C_BT_MP_OPER, buflen, buf) == _FAIL) {
- _cancel_timer(&GLBtcBtMpOperTimer, &timer_cancelled);
+ _cancel_timer_ex(&GLBtcBtMpOperTimer);
ret = BT_STATUS_H2C_FAIL;
goto exit;
}
_rtw_down_sema(&GLBtcBtMpRptSema);
- /* GLBtcBtMpRptWait should be 0 here*/
+ /* GLBtcBtMpRptWait should be _FALSE here*/
- if (!GLBtcBtMpRptWiFiOK) {
- RTW_INFO("%s: Didn't get H2C Rsp Event!\n", __FUNCTION__);
+ if (GLBtcBtMpRptWiFiOK == _FALSE) {
+ RTW_ERR("%s: Didn't get H2C Rsp Event!\n", __FUNCTION__);
ret = BT_STATUS_H2C_TIMTOUT;
goto exit;
}
- if (!GLBtcBtMpRptBTOK) {
- RTW_INFO("%s: Didn't get BT response!\n", __FUNCTION__);
+ if (GLBtcBtMpRptBTOK == _FALSE) {
+ RTW_DBG("%s: Didn't get BT response!\n", __FUNCTION__);
ret = BT_STATUS_H2C_BT_NO_RSP;
goto exit;
}
+
if (seq != GLBtcBtMpRptSeq) {
- RTW_INFO("%s: Sequence number not match!(%d!=%d)!\n",
+ RTW_ERR("%s: Sequence number not match!(%d!=%d)!\n",
__FUNCTION__, seq, GLBtcBtMpRptSeq);
ret = BT_STATUS_C2H_REQNUM_MISMATCH;
goto exit;
@@ -616,23 +688,23 @@ static u8 _btmpoper_cmd(PBTC_COEXIST pBtCoexist, u8 opcode, u8 opcodever, u8 *cm
/* Examine the status reported from C2H */
case BT_STATUS_OK:
ret = BT_STATUS_BT_OP_SUCCESS;
- RTW_INFO("%s: C2H status = BT_STATUS_BT_OP_SUCCESS\n", __FUNCTION__);
+ RTW_DBG("%s: C2H status = BT_STATUS_BT_OP_SUCCESS\n", __FUNCTION__);
break;
case BT_STATUS_VERSION_MISMATCH:
ret = BT_STATUS_OPCODE_L_VERSION_MISMATCH;
- RTW_INFO("%s: C2H status = BT_STATUS_OPCODE_L_VERSION_MISMATCH\n", __FUNCTION__);
+ RTW_DBG("%s: C2H status = BT_STATUS_OPCODE_L_VERSION_MISMATCH\n", __FUNCTION__);
break;
case BT_STATUS_UNKNOWN_OPCODE:
ret = BT_STATUS_UNKNOWN_OPCODE_L;
- RTW_INFO("%s: C2H status = MP_BT_STATUS_UNKNOWN_OPCODE_L\n", __FUNCTION__);
+ RTW_DBG("%s: C2H status = MP_BT_STATUS_UNKNOWN_OPCODE_L\n", __FUNCTION__);
break;
case BT_STATUS_ERROR_PARAMETER:
ret = BT_STATUS_PARAMETER_FORMAT_ERROR_L;
- RTW_INFO("%s: C2H status = MP_BT_STATUS_PARAMETER_FORMAT_ERROR_L\n", __FUNCTION__);
+ RTW_DBG("%s: C2H status = MP_BT_STATUS_PARAMETER_FORMAT_ERROR_L\n", __FUNCTION__);
break;
default:
ret = BT_STATUS_UNKNOWN_STATUS_L;
- RTW_INFO("%s: C2H status = MP_BT_STATUS_UNKNOWN_STATUS_L\n", __FUNCTION__);
+ RTW_DBG("%s: C2H status = MP_BT_STATUS_UNKNOWN_STATUS_L\n", __FUNCTION__);
break;
}
@@ -642,49 +714,164 @@ static u8 _btmpoper_cmd(PBTC_COEXIST pBtCoexist, u8 opcode, u8 opcodever, u8 *cm
u32 halbtcoutsrc_GetBtPatchVer(PBTC_COEXIST pBtCoexist)
{
- if (_is_btfwver_valid(pBtCoexist, pBtCoexist->btInfo.btRealFwVer) == _TRUE)
- goto exit;
+ if (pBtCoexist->bt_info.get_bt_fw_ver_cnt <= 5) {
+ if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
+ _irqL irqL;
+ u8 ret;
+
+ _enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
+
+ ret = _btmpoper_cmd(pBtCoexist, BT_OP_GET_BT_VERSION, 0, NULL, 0);
+ if (BT_STATUS_BT_OP_SUCCESS == ret) {
+ pBtCoexist->bt_info.bt_real_fw_ver = le16_to_cpu(*(u16 *)GLBtcBtMpRptRsp);
+ pBtCoexist->bt_info.bt_fw_ver = *(GLBtcBtMpRptRsp + 2);
+ pBtCoexist->bt_info.get_bt_fw_ver_cnt++;
+ }
+
+ _exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
+ } else {
+#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
+ u1Byte dataLen = 2;
+ u1Byte buf[4] = {0};
+
+ buf[0] = 0x0; /* OP_Code */
+ buf[1] = 0x0; /* OP_Code_Length */
+ BT_SendEventExtBtCoexControl(pBtCoexist->Adapter, _FALSE, dataLen, &buf[0]);
+#endif /* !CONFIG_BT_COEXIST_SOCKET_TRX */
+ }
+ }
+
+exit:
+ return pBtCoexist->bt_info.bt_real_fw_ver;
+}
+
+s32 halbtcoutsrc_GetWifiRssi(PADAPTER padapter)
+{
+ return rtw_phydm_get_min_rssi(padapter);
+}
+
+u32 halbtcoutsrc_GetBtCoexSupportedFeature(void *pBtcContext)
+{
+ PBTC_COEXIST pBtCoexist;
+ u32 ret = BT_STATUS_BT_OP_SUCCESS;
+ u32 data = 0;
+
+ pBtCoexist = (PBTC_COEXIST)pBtcContext;
if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
+ u8 buf[3] = {0};
_irqL irqL;
- u8 ret;
+ u8 op_code;
+ u8 status;
+
+ _enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
+
+ op_code = BT_OP_GET_BT_COEX_SUPPORTED_FEATURE;
+ status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);
+ if (status == BT_STATUS_BT_OP_SUCCESS)
+ data = le16_to_cpu(*(u16 *)GLBtcBtMpRptRsp);
+ else
+ ret = SET_BT_MP_OPER_RET(op_code, status);
+
+ _exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
+
+ } else
+ ret = BT_STATUS_NOT_IMPLEMENT;
+ return data;
+}
+
+u32 halbtcoutsrc_GetBtCoexSupportedVersion(void *pBtcContext)
+{
+ PBTC_COEXIST pBtCoexist;
+ u32 ret = BT_STATUS_BT_OP_SUCCESS;
+ u32 data = 0xFFFF;
+
+ pBtCoexist = (PBTC_COEXIST)pBtcContext;
+
+ if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
+ u8 buf[3] = {0};
+ _irqL irqL;
+ u8 op_code;
+ u8 status;
_enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
- ret = _btmpoper_cmd(pBtCoexist, BT_OP_GET_BT_VERSION, 0, NULL, 0);
- if (BT_STATUS_BT_OP_SUCCESS == ret) {
- pBtCoexist->btInfo.btRealFwVer = le16_to_cpu(*(u16 *)GLBtcBtMpRptRsp);
- pBtCoexist->btInfo.btFwVer = *(GLBtcBtMpRptRsp + 2);
- }
- pBtCoexist->btInfo.getBtFwVerCnt++;
+ op_code = BT_OP_GET_BT_COEX_SUPPORTED_VERSION;
+ status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);
+ if (status == BT_STATUS_BT_OP_SUCCESS)
+ data = le16_to_cpu(*(u16 *)GLBtcBtMpRptRsp);
+ else
+ ret = SET_BT_MP_OPER_RET(op_code, status);
_exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
- } else {
-#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
- u1Byte dataLen = 2;
- u1Byte buf[4] = {0};
- buf[0] = 0x0; /* OP_Code */
- buf[1] = 0x0; /* OP_Code_Length */
- BT_SendEventExtBtCoexControl(pBtCoexist->Adapter, _FALSE, dataLen, &buf[0]);
-#endif /* !CONFIG_BT_COEXIST_SOCKET_TRX */
- }
+ } else
+ ret = BT_STATUS_NOT_IMPLEMENT;
-exit:
- return pBtCoexist->btInfo.btRealFwVer;
+ return data;
}
-s32 halbtcoutsrc_GetWifiRssi(PADAPTER padapter)
+u32 halbtcoutsrc_GetBtDeviceInfo(void *pBtcContext)
{
- PHAL_DATA_TYPE pHalData;
- s32 UndecoratedSmoothedPWDB = 0;
+ PBTC_COEXIST pBtCoexist;
+ u32 ret = BT_STATUS_BT_OP_SUCCESS;
+ u32 btDeviceInfo = 0;
- pHalData = GET_HAL_DATA(padapter);
+ pBtCoexist = (PBTC_COEXIST)pBtcContext;
+
+ if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
+ u8 buf[3] = {0};
+ _irqL irqL;
+ u8 op_code;
+ u8 status;
+
+ _enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
+
+ op_code = BT_OP_GET_BT_DEVICE_INFO;
+ status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);
+ if (status == BT_STATUS_BT_OP_SUCCESS)
+ btDeviceInfo = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp);
+ else
+ ret = SET_BT_MP_OPER_RET(op_code, status);
+
+ _exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
+
+ } else
+ ret = BT_STATUS_NOT_IMPLEMENT;
+
+ return btDeviceInfo;
+}
+
+u32 halbtcoutsrc_GetBtForbiddenSlotVal(void *pBtcContext)
+{
+ PBTC_COEXIST pBtCoexist;
+ u32 ret = BT_STATUS_BT_OP_SUCCESS;
+ u32 btForbiddenSlotVal = 0;
+
+ pBtCoexist = (PBTC_COEXIST)pBtcContext;
+
+ if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
+ u8 buf[3] = {0};
+ _irqL irqL;
+ u8 op_code;
+ u8 status;
+
+ _enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
+
+ op_code = BT_OP_GET_BT_FORBIDDEN_SLOT_VAL;
+ status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);
+ if (status == BT_STATUS_BT_OP_SUCCESS)
+ btForbiddenSlotVal = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp);
+ else
+ ret = SET_BT_MP_OPER_RET(op_code, status);
+
+ _exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
- UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB;
+ } else
+ ret = BT_STATUS_NOT_IMPLEMENT;
- return UndecoratedSmoothedPWDB;
+ return btForbiddenSlotVal;
}
static u8 halbtcoutsrc_GetWifiScanAPNum(PADAPTER padapter)
@@ -718,6 +905,7 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf)
s32 *pS4Tmp;
u32 *pU4Tmp;
u8 *pU1Tmp;
+ u16 *pU2Tmp;
u8 ret;
@@ -734,6 +922,7 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf)
pS4Tmp = (s32 *)pOutBuf;
pU4Tmp = (u32 *)pOutBuf;
pU1Tmp = (u8 *)pOutBuf;
+ pU2Tmp = (u16*)pOutBuf;
ret = _TRUE;
switch (getType) {
@@ -747,10 +936,18 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf)
ret = _FALSE;
break;
+ case BTC_GET_BL_WIFI_FW_READY:
+ *pu8 = halbtcoutsrc_is_fw_ready(pBtCoexist);
+ break;
+
case BTC_GET_BL_WIFI_CONNECTED:
*pu8 = (rtw_mi_check_status(padapter, MI_LINKED)) ? _TRUE : _FALSE;
break;
+ case BTC_GET_BL_WIFI_DUAL_BAND_CONNECTED:
+ *pu8 = halbtcoutsrc_IsDualBandConnected(padapter);
+ break;
+
case BTC_GET_BL_WIFI_BUSY:
*pu8 = halbtcoutsrc_IsWifiBusy(padapter);
break;
@@ -778,7 +975,7 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf)
break;
case BTC_GET_BL_WIFI_UNDER_5G:
- *pu8 = (pHalData->CurrentBandType == 1) ? _TRUE : _FALSE;
+ *pu8 = (pHalData->current_band_type == BAND_ON_5G) ? _TRUE : _FALSE;
break;
case BTC_GET_BL_WIFI_AP_MODE_ENABLE:
@@ -811,6 +1008,17 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf)
*pu8 = _FALSE;
break;
+ case BTC_GET_BL_RF4CE_CONNECTED:
+#ifdef CONFIG_RF4CE_COEXIST
+ if (hal_btcoex_get_rf4ce_link_state() == 0)
+ *pu8 = FALSE;
+ else
+ *pu8 = TRUE;
+#else
+ *pu8 = FALSE;
+#endif
+ break;
+
case BTC_GET_S4_WIFI_RSSI:
*pS4Tmp = halbtcoutsrc_GetWifiRssi(padapter);
break;
@@ -824,7 +1032,7 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf)
if (IsLegacyOnly(mlmeext->cur_wireless_mode))
*pU4Tmp = BTC_WIFI_BW_LEGACY;
else {
- switch (pHalData->CurrentChannelBW) {
+ switch (pHalData->current_channel_bw) {
case CHANNEL_WIDTH_20:
*pU4Tmp = BTC_WIFI_BW_HT20;
break;
@@ -838,7 +1046,7 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf)
*pU4Tmp = BTC_WIFI_BW_HT160;
break;
default:
- RTW_INFO("[BTCOEX] unkown bandwidth(%d)\n", pHalData->CurrentChannelBW);
+ RTW_INFO("[BTCOEX] unknown bandwidth(%d)\n", pHalData->current_channel_bw);
*pU4Tmp = BTC_WIFI_BW_HT40;
break;
}
@@ -855,11 +1063,11 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf)
else
*pU4Tmp = BTC_WIFI_TRAFFIC_RX;
}
- break;
+ break;
case BTC_GET_U4_WIFI_FW_VER:
- *pU4Tmp = pHalData->FirmwareVersion << 16;
- *pU4Tmp |= pHalData->FirmwareSubVersion;
+ *pU4Tmp = pHalData->firmware_version << 16;
+ *pU4Tmp |= pHalData->firmware_sub_version;
break;
case BTC_GET_U4_WIFI_LINK_STATUS:
@@ -874,16 +1082,31 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf)
*pU4Tmp = BTC_VENDOR_OTHER;
break;
+ case BTC_GET_U4_SUPPORTED_VERSION:
+ *pU4Tmp = halbtcoutsrc_GetBtCoexSupportedVersion(pBtCoexist);
+ break;
+ case BTC_GET_U4_SUPPORTED_FEATURE:
+ *pU4Tmp = halbtcoutsrc_GetBtCoexSupportedFeature(pBtCoexist);
+ break;
+
+ case BTC_GET_U4_BT_DEVICE_INFO:
+ *pU4Tmp = halbtcoutsrc_GetBtDeviceInfo(pBtCoexist);
+ break;
+
+ case BTC_GET_U4_BT_FORBIDDEN_SLOT_VAL:
+ *pU4Tmp = halbtcoutsrc_GetBtForbiddenSlotVal(pBtCoexist);
+ break;
+
case BTC_GET_U4_WIFI_IQK_TOTAL:
- *pU4Tmp = pHalData->odmpriv.nIQK_Cnt;
+ *pU4Tmp = pHalData->odmpriv.n_iqk_cnt;
break;
case BTC_GET_U4_WIFI_IQK_OK:
- *pU4Tmp = pHalData->odmpriv.nIQK_OK_Cnt;
+ *pU4Tmp = pHalData->odmpriv.n_iqk_ok_cnt;
break;
case BTC_GET_U4_WIFI_IQK_FAIL:
- *pU4Tmp = pHalData->odmpriv.nIQK_Fail_Cnt;
+ *pU4Tmp = pHalData->odmpriv.n_iqk_fail_cnt;
break;
case BTC_GET_U1_WIFI_DOT11_CHNL:
@@ -891,7 +1114,7 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf)
break;
case BTC_GET_U1_WIFI_CENTRAL_CHNL:
- *pU1Tmp = pHalData->CurrentChannel;
+ *pU1Tmp = pHalData->current_channel;
break;
case BTC_GET_U1_WIFI_HS_CHNL:
@@ -954,6 +1177,10 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf)
*pU1Tmp = padapter->dvobj->pwrctl_priv.pwr_mode;
break;
+ case BTC_GET_U2_BEACON_PERIOD:
+ *pU2Tmp = mlmeext->mlmext_info.bcn_interval;
+ break;
+
default:
ret = _FALSE;
break;
@@ -962,6 +1189,30 @@ u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf)
return ret;
}
+u16 halbtcoutsrc_LnaConstrainLvl(void *pBtcContext, u8 *lna_constrain_level)
+{
+ PBTC_COEXIST pBtCoexist;
+ u16 ret = BT_STATUS_BT_OP_SUCCESS;
+
+ pBtCoexist = (PBTC_COEXIST)pBtcContext;
+
+ if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
+ _irqL irqL;
+ u8 op_code;
+
+ _enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
+
+ ret = _btmpoper_cmd(pBtCoexist, BT_OP_SET_BT_LANCONSTRAIN_LEVEL, 0, lna_constrain_level, 1);
+
+ _exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
+ } else {
+ ret = BT_STATUS_NOT_IMPLEMENT;
+ RTW_INFO("%s halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == FALSE\n", __func__);
+ }
+
+ return ret;
+}
+
u8 halbtcoutsrc_Set(void *pBtcContext, u8 setType, void *pInBuf)
{
PBTC_COEXIST pBtCoexist;
@@ -971,6 +1222,7 @@ u8 halbtcoutsrc_Set(void *pBtcContext, u8 setType, void *pInBuf)
u8 *pU1Tmp;
u32 *pU4Tmp;
u8 ret;
+ u8 result = _TRUE;
pBtCoexist = (PBTC_COEXIST)pBtcContext;
@@ -987,48 +1239,52 @@ u8 halbtcoutsrc_Set(void *pBtcContext, u8 setType, void *pInBuf)
switch (setType) {
/* set some u8 type variables. */
case BTC_SET_BL_BT_DISABLE:
- pBtCoexist->btInfo.bBtDisabled = *pu8;
+ pBtCoexist->bt_info.bt_disabled = *pu8;
+ break;
+
+ case BTC_SET_BL_BT_ENABLE_DISABLE_CHANGE:
+ pBtCoexist->bt_info.bt_enable_disable_change = *pu8;
break;
case BTC_SET_BL_BT_TRAFFIC_BUSY:
- pBtCoexist->btInfo.bBtBusy = *pu8;
+ pBtCoexist->bt_info.bt_busy = *pu8;
break;
case BTC_SET_BL_BT_LIMITED_DIG:
- pBtCoexist->btInfo.bLimitedDig = *pu8;
+ pBtCoexist->bt_info.limited_dig = *pu8;
break;
case BTC_SET_BL_FORCE_TO_ROAM:
- pBtCoexist->btInfo.bForceToRoam = *pu8;
+ pBtCoexist->bt_info.force_to_roam = *pu8;
break;
case BTC_SET_BL_TO_REJ_AP_AGG_PKT:
- pBtCoexist->btInfo.bRejectAggPkt = *pu8;
+ pBtCoexist->bt_info.reject_agg_pkt = *pu8;
break;
case BTC_SET_BL_BT_CTRL_AGG_SIZE:
- pBtCoexist->btInfo.bBtCtrlAggBufSize = *pu8;
+ pBtCoexist->bt_info.bt_ctrl_agg_buf_size = *pu8;
break;
case BTC_SET_BL_INC_SCAN_DEV_NUM:
- pBtCoexist->btInfo.bIncreaseScanDevNum = *pu8;
+ pBtCoexist->bt_info.increase_scan_dev_num = *pu8;
break;
case BTC_SET_BL_BT_TX_RX_MASK:
- pBtCoexist->btInfo.bBtTxRxMask = *pu8;
+ pBtCoexist->bt_info.bt_tx_rx_mask = *pu8;
break;
case BTC_SET_BL_MIRACAST_PLUS_BT:
- pBtCoexist->btInfo.bMiracastPlusBt = *pu8;
+ pBtCoexist->bt_info.miracast_plus_bt = *pu8;
break;
/* set some u8 type variables. */
case BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON:
- pBtCoexist->btInfo.rssiAdjustForAgcTableOn = *pU1Tmp;
+ pBtCoexist->bt_info.rssi_adjust_for_agc_table_on = *pU1Tmp;
break;
case BTC_SET_U1_AGG_BUF_SIZE:
- pBtCoexist->btInfo.aggBufSize = *pU1Tmp;
+ pBtCoexist->bt_info.agg_buf_size = *pU1Tmp;
break;
/* the following are some action which will be triggered */
@@ -1047,20 +1303,20 @@ u8 halbtcoutsrc_Set(void *pBtcContext, u8 setType, void *pInBuf)
/* =======1Ant=========== */
/* set some u8 type variables. */
case BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE:
- pBtCoexist->btInfo.rssiAdjustFor1AntCoexType = *pU1Tmp;
+ pBtCoexist->bt_info.rssi_adjust_for_1ant_coex_type = *pU1Tmp;
break;
case BTC_SET_U1_LPS_VAL:
- pBtCoexist->btInfo.lpsVal = *pU1Tmp;
+ pBtCoexist->bt_info.lps_val = *pU1Tmp;
break;
case BTC_SET_U1_RPWM_VAL:
- pBtCoexist->btInfo.rpwmVal = *pU1Tmp;
+ pBtCoexist->bt_info.rpwm_val = *pU1Tmp;
break;
/* the following are some action which will be triggered */
case BTC_SET_ACT_LEAVE_LPS:
- halbtcoutsrc_LeaveLps(pBtCoexist);
+ result = halbtcoutsrc_LeaveLps(pBtCoexist);
break;
case BTC_SET_ACT_ENTER_LPS:
@@ -1071,12 +1327,21 @@ u8 halbtcoutsrc_Set(void *pBtcContext, u8 setType, void *pInBuf)
halbtcoutsrc_NormalLps(pBtCoexist);
break;
+ case BTC_SET_ACT_PRE_NORMAL_LPS:
+ halbtcoutsrc_Pre_NormalLps(pBtCoexist);
+ break;
+
+ case BTC_SET_ACT_POST_NORMAL_LPS:
+ halbtcoutsrc_Post_NormalLps(pBtCoexist);
+ break;
+
case BTC_SET_ACT_DISABLE_LOW_POWER:
halbtcoutsrc_DisableLowPower(pBtCoexist, *pu8);
break;
case BTC_SET_ACT_UPDATE_RAMASK:
- pBtCoexist->btInfo.raMask = *pU4Tmp;
+ /*
+ pBtCoexist->bt_info.ra_mask = *pU4Tmp;
if (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) == _TRUE) {
struct sta_info *psta;
@@ -1084,8 +1349,9 @@ u8 halbtcoutsrc_Set(void *pBtcContext, u8 setType, void *pInBuf)
cur_network = &padapter->mlmeextpriv.mlmext_info.network;
psta = rtw_get_stainfo(&padapter->stapriv, cur_network->MacAddress);
- rtw_hal_update_ra_mask(psta, 0);
+ rtw_hal_update_ra_mask(psta);
}
+ */
break;
case BTC_SET_ACT_SEND_MIMO_PS: {
@@ -1147,13 +1413,16 @@ u8 halbtcoutsrc_Set(void *pBtcContext, u8 setType, void *pInBuf)
ret = _FALSE;
#endif
break;
+ case BTC_SET_BL_BT_LNA_CONSTRAIN_LEVEL:
+ halbtcoutsrc_LnaConstrainLvl(pBtCoexist, pu8);
+ break;
/* ===================== */
default:
ret = _FALSE;
break;
}
- return ret;
+ return result;
}
u8 halbtcoutsrc_UnderIps(PBTC_COEXIST pBtCoexist)
@@ -1398,26 +1667,29 @@ void halbtcoutsrc_DisplayWifiStatus(PBTC_COEXIST pBtCoexist)
BOOLEAN bBtHsOn = _FALSE, bLowPower = _FALSE;
u8 wifiChnl = 0, wifiP2PChnl = 0, nScanAPNum = 0, FwPSState;
u32 iqk_cnt_total = 0, iqk_cnt_ok = 0, iqk_cnt_fail = 0;
+ u16 wifiBcnInterval = 0;
wifiLinkStatus = halbtcoutsrc_GetWifiLinkStatus(pBtCoexist);
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d", "STA/vWifi/HS/p2pGo/p2pGc", \
+ CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d (mcc+2band = %d)", "STA/vWifi/HS/p2pGo/p2pGc",
((wifiLinkStatus & WIFI_STA_CONNECTED) ? 1 : 0), ((wifiLinkStatus & WIFI_AP_CONNECTED) ? 1 : 0),
((wifiLinkStatus & WIFI_HS_CONNECTED) ? 1 : 0), ((wifiLinkStatus & WIFI_P2P_GO_CONNECTED) ? 1 : 0),
- ((wifiLinkStatus & WIFI_P2P_GC_CONNECTED) ? 1 : 0));
+ ((wifiLinkStatus & WIFI_P2P_GC_CONNECTED) ? 1 : 0),
+ halbtcoutsrc_IsDualBandConnected(padapter) ? 1 : 0);
CL_PRINTF(cliBuf);
pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan);
pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink);
pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam);
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ", "Link/ Roam/ Scan", \
+ CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ", "Link/ Roam/ Scan",
bLink, bRoam, bScan);
CL_PRINTF(cliBuf);
pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_IQK_TOTAL, &iqk_cnt_total);
pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_IQK_OK, &iqk_cnt_ok);
pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_IQK_FAIL, &iqk_cnt_fail);
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ", "IQK Total/ OK/ Fail", \
- iqk_cnt_total, iqk_cnt_ok, iqk_cnt_fail);
+ CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d %s %s",
+ "IQK All/ OK/ Fail/AutoLoad/FWDL", iqk_cnt_total, iqk_cnt_ok, iqk_cnt_fail,
+ ((halbtcoutsrc_is_autoload_fail(pBtCoexist) == _TRUE) ? "fail":"ok"), ((halbtcoutsrc_is_fw_ready(pBtCoexist) == _TRUE) ? "ok":"fail"));
CL_PRINTF(cliBuf);
if (wifiLinkStatus & WIFI_STA_CONNECTED) {
@@ -1427,10 +1699,11 @@ void halbtcoutsrc_DisplayWifiStatus(PBTC_COEXIST pBtCoexist)
pBtCoexist->btc_get(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi);
pBtCoexist->btc_get(pBtCoexist, BTC_GET_U1_WIFI_DOT11_CHNL, &wifiChnl);
+ pBtCoexist->btc_get(pBtCoexist, BTC_GET_U2_BEACON_PERIOD, &wifiBcnInterval);
if ((wifiLinkStatus & WIFI_P2P_GO_CONNECTED) || (wifiLinkStatus & WIFI_P2P_GC_CONNECTED))
pBtCoexist->btc_get(pBtCoexist, BTC_GET_U1_WIFI_P2P_CHNL, &wifiP2PChnl);
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d dBm/ %d/ %d", "RSSI/ STA_Chnl/ P2P_Chnl", \
- wifiRssi -100, wifiChnl, wifiP2PChnl);
+ CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d dBm/ %d/ %d/ %d", "RSSI/ STA_Chnl/ P2P_Chnl/ BI",
+ wifiRssi-100, wifiChnl, wifiP2PChnl, wifiBcnInterval);
CL_PRINTF(cliBuf);
pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifiFreq);
@@ -1439,7 +1712,7 @@ void halbtcoutsrc_DisplayWifiStatus(PBTC_COEXIST pBtCoexist)
pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir);
pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, &bWifiUnderBMode);
pBtCoexist->btc_get(pBtCoexist, BTC_GET_U1_AP_NUM, &nScanAPNum);
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %s/ %s/ %d ", "Band/ BW/ Traffic/ APCnt", \
+ CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %s/ %s/ %d ", "Band/ BW/ Traffic/ APCnt",
GLBtcWifiFreqString[wifiFreq], ((bWifiUnderBMode) ? "11b" : GLBtcWifiBwString[wifiBw]),
((!bWifiBusy) ? "idle" : ((BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) ? "uplink" : "downlink")),
nScanAPNum);
@@ -1452,12 +1725,12 @@ void halbtcoutsrc_DisplayWifiStatus(PBTC_COEXIST pBtCoexist)
((halbtcoutsrc_Under32K(pBtCoexist) == _TRUE) ? ", 32k" : ""));
CL_PRINTF(cliBuf);
- CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x %02x (0x%x/0x%x)", "Power mode cmd(lps/rpwm)", \
+ CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x %02x (0x%x/0x%x)", "Power mode cmd(lps/rpwm)",
pBtCoexist->pwrModeVal[0], pBtCoexist->pwrModeVal[1],
pBtCoexist->pwrModeVal[2], pBtCoexist->pwrModeVal[3],
pBtCoexist->pwrModeVal[4], pBtCoexist->pwrModeVal[5],
- pBtCoexist->btInfo.lpsVal,
- pBtCoexist->btInfo.rpwmVal);
+ pBtCoexist->bt_info.lps_val,
+ pBtCoexist->bt_info.rpwm_val);
CL_PRINTF(cliBuf);
}
@@ -1605,7 +1878,7 @@ void halbtcoutsrc_SetBbReg(void *pBtcContext, u32 RegAddr, u32 BitMask, u32 Data
pBtCoexist = (PBTC_COEXIST)pBtcContext;
padapter = pBtCoexist->Adapter;
- PHY_SetBBReg(padapter, RegAddr, BitMask, Data);
+ phy_set_bb_reg(padapter, RegAddr, BitMask, Data);
}
@@ -1618,10 +1891,10 @@ u32 halbtcoutsrc_GetBbReg(void *pBtcContext, u32 RegAddr, u32 BitMask)
pBtCoexist = (PBTC_COEXIST)pBtcContext;
padapter = pBtCoexist->Adapter;
- return PHY_QueryBBReg(padapter, RegAddr, BitMask);
+ return phy_query_bb_reg(padapter, RegAddr, BitMask);
}
-void halbtcoutsrc_SetRfReg(void *pBtcContext, u8 eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
+void halbtcoutsrc_SetRfReg(void *pBtcContext, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
{
PBTC_COEXIST pBtCoexist;
PADAPTER padapter;
@@ -1630,10 +1903,10 @@ void halbtcoutsrc_SetRfReg(void *pBtcContext, u8 eRFPath, u32 RegAddr, u32 BitMa
pBtCoexist = (PBTC_COEXIST)pBtcContext;
padapter = pBtCoexist->Adapter;
- PHY_SetRFReg(padapter, eRFPath, RegAddr, BitMask, Data);
+ phy_set_rf_reg(padapter, eRFPath, RegAddr, BitMask, Data);
}
-u32 halbtcoutsrc_GetRfReg(void *pBtcContext, u8 eRFPath, u32 RegAddr, u32 BitMask)
+u32 halbtcoutsrc_GetRfReg(void *pBtcContext, enum rf_path eRFPath, u32 RegAddr, u32 BitMask)
{
PBTC_COEXIST pBtCoexist;
PADAPTER padapter;
@@ -1642,7 +1915,7 @@ u32 halbtcoutsrc_GetRfReg(void *pBtcContext, u8 eRFPath, u32 RegAddr, u32 BitMas
pBtCoexist = (PBTC_COEXIST)pBtcContext;
padapter = pBtCoexist->Adapter;
- return PHY_QueryRFReg(padapter, eRFPath, RegAddr, BitMask);
+ return phy_query_rf_reg(padapter, eRFPath, RegAddr, BitMask);
}
u16 halbtcoutsrc_SetBtReg(void *pBtcContext, u8 RegType, u32 RegAddr, u32 Data)
@@ -1700,7 +1973,39 @@ u8 halbtcoutsrc_SetBtAntDetection(void *pBtcContext, u8 txTime, u8 btChnl)
#endif
}
-u16 halbtcoutsrc_GetBtReg(void *pBtcContext, u8 RegType, u32 RegAddr, u32 *data)
+BOOLEAN
+halbtcoutsrc_SetBtTRXMASK(
+ IN PVOID pBtcContext,
+ IN u1Byte bt_trx_mask
+ )
+{
+ /* Always return _FALSE since we don't implement this yet */
+#if 0
+ struct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext;
+ PADAPTER Adapter = pBtCoexist->Adapter;
+ BOOLEAN bStatus = FALSE;
+ u1Byte btCanTx = 0;
+
+ if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter) || IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)
+ || IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
+
+ if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter))
+ bStatus = NDBG_SetBtTRXMASK(Adapter, 1, bt_trx_mask, &btCanTx);
+ else
+ bStatus = NDBG_SetBtTRXMASK(Adapter, 2, bt_trx_mask, &btCanTx);
+ }
+
+
+ if (bStatus)
+ return TRUE;
+ else
+ return FALSE;
+#else
+ return _FALSE;
+#endif
+}
+
+u16 halbtcoutsrc_GetBtReg_with_status(void *pBtcContext, u8 RegType, u32 RegAddr, u32 *data)
{
PBTC_COEXIST pBtCoexist;
u16 ret = BT_STATUS_BT_OP_SUCCESS;
@@ -1733,6 +2038,13 @@ u16 halbtcoutsrc_GetBtReg(void *pBtcContext, u8 RegType, u32 RegAddr, u32 *data)
return ret;
}
+u32 halbtcoutsrc_GetBtReg(void *pBtcContext, u8 RegType, u32 RegAddr)
+{
+ u32 regVal;
+
+ return (BT_STATUS_BT_OP_SUCCESS == halbtcoutsrc_GetBtReg_with_status(pBtcContext, RegType, RegAddr, ®Val)) ? regVal : 0xffffffff;
+}
+
void halbtcoutsrc_FillH2cCmd(void *pBtcContext, u8 elementId, u32 cmdLen, u8 *pCmdBuffer)
{
PBTC_COEXIST pBtCoexist;
@@ -1772,15 +2084,10 @@ static COL_H2C_STATUS halbtcoutsrc_send_h2c(PADAPTER Adapter, PCOL_H2C pcol_h2c,
if (TRUE) {
#if 0 /*(USE_HAL_MAC_API == 1) */
if (RT_STATUS_SUCCESS == HAL_MAC_Send_BT_COEX(&GET_HAL_MAC_INFO(Adapter), (pu1Byte)(pcol_h2c), (u4Byte)h2c_cmd_len, 1)) {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("HAL_MAC_Send_BT_COEX successfully.\n"));
- if (wait_for_completion_timeout(&gl_coex_offload.c2h_event[pcol_h2c->req_num], 20))
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[COL], received H2C rsp event!!\n"));
- else {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[COL], H2C timeout!!\n"));
+ if (!wait_for_completion_timeout(&gl_coex_offload.c2h_event[pcol_h2c->req_num], 20)) {
h2c_status = COL_STATUS_H2C_TIMTOUT;
}
} else {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("HAL_MAC_Send_BT_COEX fail.\n"));
h2c_status = COL_STATUS_H2C_HALMAC_FAIL;
}
#endif
@@ -1796,11 +2103,8 @@ static COL_H2C_STATUS halbtcoutsrc_check_c2h_ack(PADAPTER Adapter, PCOL_SINGLE_H
u8 req_num = p_h2c_cmd->req_num;
PCOL_C2H_ACK p_c2h_ack = (PCOL_C2H_ACK)&gl_coex_offload.c2h_ack_buf[req_num];
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[COL], c2h ack len=%d, coex return len=%d!!!\n",
- gl_coex_offload.c2h_ack_len[req_num], p_c2h_ack->ret_len));
if ((COL_C2H_ACK_HDR_LEN + p_c2h_ack->ret_len) > gl_coex_offload.c2h_ack_len[req_num]) {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[COL], coex data overflow!!!\n"));
c2h_status = COL_STATUS_COEX_DATA_OVERFLOW;
return c2h_status;
}
@@ -1810,18 +2114,13 @@ static COL_H2C_STATUS halbtcoutsrc_check_c2h_ack(PADAPTER Adapter, PCOL_SINGLE_H
pH2cRecord->c2h_ack_len = gl_coex_offload.c2h_ack_len[req_num];
}
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[COL], c2h ack: status=0x%x, opcode_ver=0x%x, req_num=%d, ret_len=%d\n",
- p_c2h_ack->status, p_c2h_ack->opcode_ver, p_c2h_ack->req_num, p_c2h_ack->ret_len));
if (p_c2h_ack->req_num != p_h2c_cmd->req_num) {
c2h_status = COL_STATUS_C2H_REQ_NUM_MISMATCH;
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[COL], Error!! C2H req_num Mismatch!!\n"));
} else if (p_c2h_ack->opcode_ver != p_h2c_cmd->opcode_ver) {
c2h_status = COL_STATUS_C2H_OPCODE_VER_MISMATCH;
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[COL], Error!! OPCode version mismatch!!\n"));
} else {
c2h_status = p_c2h_ack->status;
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[COL], status from fw = %d!!\n", c2h_status));
}
return c2h_status;
@@ -1846,8 +2145,6 @@ COL_H2C_STATUS halbtcoutsrc_CoexH2cProcess(void *pBtCoexist,
_rtw_memmove(&pcol_h2c->buf[0], ph2c_par, h2c_par_len);
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[COL], H2C opcode/ opcode_ver/ req_num/ h2c_par_len=%d/ %d/ %d/ %d\n",
- pcol_h2c->opcode, pcol_h2c->opcode_ver, pcol_h2c->req_num, h2c_par_len));
col_h2c_len = h2c_par_len + 2; /* 2=sizeof(OPCode, OPCode_version and Request number) */
BT_PrintData(Adapter, "[COL], H2C cmd: ", col_h2c_len, H2C_Parameter);
@@ -1867,7 +2164,6 @@ COL_H2C_STATUS halbtcoutsrc_CoexH2cProcess(void *pBtCoexist,
c2h_status = halbtcoutsrc_check_c2h_ack(Adapter, &gl_coex_offload.h2c_record[opcode]);
ret_status = c2h_status;
} else {
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[COL], H2C failed for opCode=%d\n", opcode));
/* check h2c status error, return error status code to upper layer. */
ret_status = h2c_status;
}
@@ -1877,36 +2173,151 @@ COL_H2C_STATUS halbtcoutsrc_CoexH2cProcess(void *pBtCoexist,
return ret_status;
}
-u32 halbtcoutsrc_GetBtCoexSupportedFeature(void *pBtcContext)
+u8 halbtcoutsrc_GetAntDetValFromBt(void *pBtcContext)
{
- struct btc_coexist *pBtCoexist=(struct btc_coexist *)pBtcContext;
- PADAPTER Adapter=pBtCoexist->Adapter;
- u4Byte coexSupportedFeature=0x0;
+ /* Always return 0 since we don't implement this yet */
+#if 0
+ struct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext;
+ PADAPTER Adapter = pBtCoexist->Adapter;
+ u1Byte AntDetVal = 0x0;
u1Byte opcodeVer = 1;
BOOLEAN status = false;
+ status = NDBG_GetAntDetValFromBt(Adapter, opcodeVer, &AntDetVal);
- return coexSupportedFeature;
+ RT_TRACE(COMP_DBG, DBG_LOUD, ("$$$ halbtcoutsrc_GetAntDetValFromBt(): status = %d, feature = %x\n", status, AntDetVal));
+
+ return AntDetVal;
+#else
+ return 0;
+#endif
}
-u32 halbtcoutsrc_GetBtCoexSupportedVersion(void *pBtcContext)
+u8 halbtcoutsrc_GetBleScanTypeFromBt(void *pBtcContext)
{
- struct btc_coexist *pBtCoexist=(struct btc_coexist *)pBtcContext;
- PADAPTER Adapter=pBtCoexist->Adapter;
- u32 coexSupportedVersion=0x0;
- u8 opcodeVer = 1;
- u8 status = false;
+ PBTC_COEXIST pBtCoexist;
+ u32 ret = BT_STATUS_BT_OP_SUCCESS;
+ u8 data = 0;
+ pBtCoexist = (PBTC_COEXIST)pBtcContext;
- return coexSupportedVersion;
-}
+ if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
+ u8 buf[3] = {0};
+ _irqL irqL;
+ u8 op_code;
+ u8 status;
-u32 halbtcoutsrc_GetPhydmVersion(void *pBtcContext)
-{
- struct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext;
- PADAPTER Adapter = pBtCoexist->Adapter;
-#ifdef CONFIG_RTL8192E
+ _enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
+
+ op_code = BT_OP_GET_BT_BLE_SCAN_TYPE;
+ status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);
+ if (status == BT_STATUS_BT_OP_SUCCESS)
+ data = *(u8 *)GLBtcBtMpRptRsp;
+ else
+ ret = SET_BT_MP_OPER_RET(op_code, status);
+
+ _exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
+
+ } else
+ ret = BT_STATUS_NOT_IMPLEMENT;
+
+ return data;
+}
+
+u32 halbtcoutsrc_GetBleScanParaFromBt(void *pBtcContext, u8 scanType)
+{
+ PBTC_COEXIST pBtCoexist;
+ u32 ret = BT_STATUS_BT_OP_SUCCESS;
+ u32 data = 0;
+
+ pBtCoexist = (PBTC_COEXIST)pBtcContext;
+
+ if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) {
+ u8 buf[3] = {0};
+ _irqL irqL;
+ u8 op_code;
+ u8 status;
+
+ buf[0] = scanType;
+
+ _enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
+
+ op_code = BT_OP_GET_BT_BLE_SCAN_PARA;
+ status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 1);
+ if (status == BT_STATUS_BT_OP_SUCCESS)
+ data = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp);
+ else
+ ret = SET_BT_MP_OPER_RET(op_code, status);
+
+ _exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
+
+ } else
+ ret = BT_STATUS_NOT_IMPLEMENT;
+
+ return data;
+}
+
+u8 halbtcoutsrc_GetBtAFHMapFromBt(void *pBtcContext, u8 mapType, u8 *afhMap)
+{
+ struct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext;
+ u8 buf[2] = {0};
+ _irqL irqL;
+ u8 op_code;
+ u32 *AfhMapL = (u32 *)&(afhMap[0]);
+ u32 *AfhMapM = (u32 *)&(afhMap[4]);
+ u16 *AfhMapH = (u16 *)&(afhMap[8]);
+ u8 status;
+ u32 ret = BT_STATUS_BT_OP_SUCCESS;
+
+ if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _FALSE)
+ return _FALSE;
+
+ buf[0] = 0;
+ buf[1] = mapType;
+
+ _enter_critical_mutex(&GLBtcBtMpOperLock, &irqL);
+
+ op_code = BT_LO_OP_GET_AFH_MAP_L;
+ status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);
+ if (status == BT_STATUS_BT_OP_SUCCESS)
+ *AfhMapL = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp);
+ else {
+ ret = SET_BT_MP_OPER_RET(op_code, status);
+ goto exit;
+ }
+
+ op_code = BT_LO_OP_GET_AFH_MAP_M;
+ status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);
+ if (status == BT_STATUS_BT_OP_SUCCESS)
+ *AfhMapM = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp);
+ else {
+ ret = SET_BT_MP_OPER_RET(op_code, status);
+ goto exit;
+ }
+
+ op_code = BT_LO_OP_GET_AFH_MAP_H;
+ status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0);
+ if (status == BT_STATUS_BT_OP_SUCCESS)
+ *AfhMapH = le16_to_cpu(*(u16 *)GLBtcBtMpRptRsp);
+ else {
+ ret = SET_BT_MP_OPER_RET(op_code, status);
+ goto exit;
+ }
+
+exit:
+
+ _exit_critical_mutex(&GLBtcBtMpOperLock, &irqL);
+
+ return (ret == BT_STATUS_BT_OP_SUCCESS) ? _TRUE : _FALSE;
+}
+
+u32 halbtcoutsrc_GetPhydmVersion(void *pBtcContext)
+{
+ struct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext;
+ PADAPTER Adapter = pBtCoexist->Adapter;
+
+#ifdef CONFIG_RTL8192E
return RELEASE_VERSION_8192E;
#endif
@@ -1934,6 +2345,36 @@ u32 halbtcoutsrc_GetPhydmVersion(void *pBtcContext)
return RELEASE_VERSION_8723D;
#endif
+#ifdef CONFIG_RTL8821C
+ return RELEASE_VERSION_8821C;
+#endif
+}
+
+void halbtcoutsrc_phydm_modify_AntDiv_HwSw(void *pBtcContext, u8 is_hw)
+{
+ /* empty function since we don't need it */
+}
+
+void halbtcoutsrc_phydm_modify_RA_PCR_threshold(void *pBtcContext, u8 RA_offset_direction, u8 RA_threshold_offset)
+{
+ struct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext;
+
+/* switch to #if 0 in case the phydm version does not provide the function */
+#if 1
+ phydm_modify_RA_PCR_threshold(pBtCoexist->odm_priv, RA_offset_direction, RA_threshold_offset);
+#endif
+}
+
+u32 halbtcoutsrc_phydm_query_PHY_counter(void *pBtcContext, u8 info_type)
+{
+ struct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext;
+
+/* switch to #if 0 in case the phydm version does not provide the function */
+#if 1
+ return phydm_cmn_info_query((struct dm_struct *)pBtCoexist->odm_priv, (enum phydm_info_query)info_type);
+#else
+ return 0;
+#endif
}
#if 0
@@ -1967,14 +2408,12 @@ static void BT_CoexOffloadC2hAckCheck(PADAPTER Adapter, u8 *tmpBuf, u8 length)
gl_coex_offload.cnt_c2h_ack++;
if (length < COL_C2H_ACK_HDR_LEN) { /* c2h ack length must >= 3 (status, opcode_ver, req_num and ret_len) */
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[COL], invalid c2h ack length (%d)!!!\n", length));
gl_coex_offload.status[COL_STATUS_INVALID_C2H_LEN]++;
} else {
BT_PrintData(Adapter, "[COL], c2h ack:", length, tmpBuf);
p_c2h_ack = (PCOL_C2H_ACK)tmpBuf;
req_num = p_c2h_ack->req_num;
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[COL], req_num = %d!!!\n", req_num));
_rtw_memmove(&gl_coex_offload.c2h_ack_buf[req_num][0], tmpBuf, length);
gl_coex_offload.c2h_ack_len[req_num] = length;
@@ -1998,7 +2437,6 @@ static void BT_CoexOffloadC2hIndCheck(PADAPTER Adapter, u8 *tmpBuf, u8 length)
gl_coex_offload.cnt_c2h_ind++;
if (length < COL_C2H_IND_HDR_LEN) { /* c2h indication length must >= 3 (type, version and length) */
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[COL], invalid c2h indication length (%d)!!!\n", length));
gl_coex_offload.c2h_ind_status[COL_STATUS_INVALID_C2H_LEN]++;
} else {
BT_PrintData(Adapter, "[COL], c2h indication:", length, tmpBuf);
@@ -2007,8 +2445,6 @@ static void BT_CoexOffloadC2hIndCheck(PADAPTER Adapter, u8 *tmpBuf, u8 length)
ind_type = p_c2h_ind->type;
ind_version = p_c2h_ind->version;
ind_length = p_c2h_ind->length;
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[COL], type/ version/ length = %d/ %d/ %d!!!\n",
- ind_type, ind_version, ind_length));
_rtw_memmove(&gl_coex_offload.c2h_ind_buf[0], tmpBuf, length);
gl_coex_offload.c2h_ind_len = length;
@@ -2032,7 +2468,6 @@ void BT_CoexOffloadC2hCheck(PADAPTER Adapter, u8 *Buffer, u8 Length)
BT_PrintData(Adapter, "[COL], c2h packet:", Length - 2, Buffer + 2);
c2hSubCmdId = (u1Byte)C2H_HDR_GET_C2H_SUB_CMD_ID(Buffer);
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[COL], c2hSubCmdId = 0x%x\n", c2hSubCmdId));
if (c2hSubCmdId == C2H_SUB_CMD_ID_H2C_ACK_HDR ||
c2hSubCmdId == C2H_SUB_CMD_ID_BT_COEX_INFO) {
@@ -2040,10 +2475,8 @@ void BT_CoexOffloadC2hCheck(PADAPTER Adapter, u8 *Buffer, u8 Length)
/* coex c2h ack */
h2cCmdId = (u1Byte)H2C_ACK_HDR_GET_H2C_CMD_ID(Buffer);
h2cSubCmdId = (u1Byte)H2C_ACK_HDR_GET_H2C_SUB_CMD_ID(Buffer);
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[COL], h2cCmdId/ h2cSubCmdId = 0x%x/ 0x%x\n", h2cCmdId, h2cSubCmdId));
if (h2cCmdId == 0xff && h2cSubCmdId == 0x60) {
c2hAckLen = (u1Byte)C2H_HDR_GET_LEN(Buffer);
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[COL], c2hAckLen = 0x%x\n", c2hAckLen));
if (c2hAckLen >= 8)
BT_CoexOffloadC2hAckCheck(Adapter, &Buffer[12], (u1Byte)(c2hAckLen - 8));
else
@@ -2052,7 +2485,6 @@ void BT_CoexOffloadC2hCheck(PADAPTER Adapter, u8 *Buffer, u8 Length)
} else if (c2hSubCmdId == C2H_SUB_CMD_ID_BT_COEX_INFO) {
/* coex c2h indication */
c2hIndLen = (u1Byte)C2H_HDR_GET_LEN(Buffer);
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[COL], c2hAckLen = 0x%x\n", c2hIndLen));
BT_CoexOffloadC2hIndCheck(Adapter, &Buffer[4], (u1Byte)c2hIndLen);
}
}
@@ -2066,7 +2498,6 @@ void BT_CoexOffloadC2hCheck(PADAPTER Adapter, u8 *Buffer, u8 Length)
u8 EXhalbtcoutsrc_BindBtCoexWithAdapter(void *padapter)
{
PBTC_COEXIST pBtCoexist = &GLBtCoexist;
- u8 antNum = 1, chipType = 0, singleAntPath = 0;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA((PADAPTER)padapter);
if (pBtCoexist->bBinded)
@@ -2074,17 +2505,26 @@ u8 EXhalbtcoutsrc_BindBtCoexWithAdapter(void *padapter)
else
pBtCoexist->bBinded = _TRUE;
- pBtCoexist->statistics.cntBind++;
+ pBtCoexist->statistics.cnt_bind++;
pBtCoexist->Adapter = padapter;
+ pBtCoexist->odm_priv = (PVOID)&(pHalData->odmpriv);
pBtCoexist->stack_info.profile_notified = _FALSE;
- pBtCoexist->btInfo.bBtCtrlAggBufSize = _FALSE;
- pBtCoexist->btInfo.aggBufSize = 5;
+ pBtCoexist->bt_info.bt_ctrl_agg_buf_size = _FALSE;
+ pBtCoexist->bt_info.agg_buf_size = 5;
+
+ pBtCoexist->bt_info.increase_scan_dev_num = _FALSE;
+ pBtCoexist->bt_info.miracast_plus_bt = _FALSE;
- pBtCoexist->btInfo.bIncreaseScanDevNum = _FALSE;
- pBtCoexist->btInfo.bMiracastPlusBt = _FALSE;
+ return _TRUE;
+}
+
+void EXhalbtcoutsrc_AntInfoSetting(void *padapter)
+{
+ PBTC_COEXIST pBtCoexist = &GLBtCoexist;
+ u8 antNum = 1, singleAntPath = 0;
antNum = rtw_btcoex_get_pg_ant_num((PADAPTER)padapter);
EXhalbtcoutsrc_SetAntNum(BT_COEX_ANT_TYPE_PG, antNum);
@@ -2094,6 +2534,8 @@ u8 EXhalbtcoutsrc_BindBtCoexWithAdapter(void *padapter)
EXhalbtcoutsrc_SetSingleAntPath(singleAntPath);
}
+ pBtCoexist->board_info.customerID = RT_CID_DEFAULT;
+
/* set default antenna position to main port */
pBtCoexist->board_info.btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT;
@@ -2101,16 +2543,11 @@ u8 EXhalbtcoutsrc_BindBtCoexWithAdapter(void *padapter)
pBtCoexist->board_info.btdm_ant_num_by_ant_det = 1;
pBtCoexist->board_info.tfbga_package = rtw_btcoex_is_tfbga_package_type((PADAPTER)padapter);
- if (pBtCoexist->board_info.tfbga_package)
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Package Type = TFBGA\n"));
- else
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Package Type = Non-TFBGA\n"));
pBtCoexist->board_info.rfe_type = rtw_btcoex_get_pg_rfe_type((PADAPTER)padapter);
pBtCoexist->board_info.ant_div_cfg = rtw_btcoex_get_ant_div_cfg((PADAPTER)padapter);
- return _TRUE;
}
u8 EXhalbtcoutsrc_InitlizeVariables(void *padapter)
@@ -2158,15 +2595,21 @@ u8 EXhalbtcoutsrc_InitlizeVariables(void *padapter)
pBtCoexist->btc_get_bt_reg = halbtcoutsrc_GetBtReg;
pBtCoexist->btc_set_bt_reg = halbtcoutsrc_SetBtReg;
pBtCoexist->btc_set_bt_ant_detection = halbtcoutsrc_SetBtAntDetection;
+ pBtCoexist->btc_set_bt_trx_mask = halbtcoutsrc_SetBtTRXMASK;
pBtCoexist->btc_coex_h2c_process = halbtcoutsrc_CoexH2cProcess;
pBtCoexist->btc_get_bt_coex_supported_feature = halbtcoutsrc_GetBtCoexSupportedFeature;
pBtCoexist->btc_get_bt_coex_supported_version= halbtcoutsrc_GetBtCoexSupportedVersion;
+ pBtCoexist->btc_get_ant_det_val_from_bt = halbtcoutsrc_GetAntDetValFromBt;
+ pBtCoexist->btc_get_ble_scan_type_from_bt = halbtcoutsrc_GetBleScanTypeFromBt;
+ pBtCoexist->btc_get_ble_scan_para_from_bt = halbtcoutsrc_GetBleScanParaFromBt;
+ pBtCoexist->btc_get_bt_afh_map_from_bt = halbtcoutsrc_GetBtAFHMapFromBt;
pBtCoexist->btc_get_bt_phydm_version = halbtcoutsrc_GetPhydmVersion;
+ pBtCoexist->btc_phydm_modify_RA_PCR_threshold = halbtcoutsrc_phydm_modify_RA_PCR_threshold;
+ pBtCoexist->btc_phydm_query_PHY_counter = halbtcoutsrc_phydm_query_PHY_counter;
+ pBtCoexist->btc_phydm_modify_ANTDIV_HwSw = halbtcoutsrc_phydm_modify_AntDiv_HwSw;
pBtCoexist->cli_buf = &GLBtcDbgBuf[0];
- pBtCoexist->board_info.single_ant_path = 0;
-
GLBtcWiFiInScanState = _FALSE;
GLBtcWiFiInIQKState = _FALSE;
@@ -2180,43 +2623,79 @@ u8 EXhalbtcoutsrc_InitlizeVariables(void *padapter)
/* BT Control H2C/C2H*/
GLBtcBtMpOperSeq = 0;
_rtw_mutex_init(&GLBtcBtMpOperLock);
- _init_timer(&GLBtcBtMpOperTimer, ((PADAPTER)padapter)->pnetdev, _btmpoper_timer_hdl, pBtCoexist);
+ rtw_init_timer(&GLBtcBtMpOperTimer, padapter, _btmpoper_timer_hdl, pBtCoexist);
_rtw_init_sema(&GLBtcBtMpRptSema, 0);
GLBtcBtMpRptSeq = 0;
GLBtcBtMpRptStatus = 0;
_rtw_memset(GLBtcBtMpRptRsp, 0, C2H_MAX_SIZE);
GLBtcBtMpRptRspSize = 0;
- GLBtcBtMpRptWait = 0;
- GLBtcBtMpRptWiFiOK = 0;
- GLBtcBtMpRptBTOK = 0;
+ GLBtcBtMpRptWait = _FALSE;
+ GLBtcBtMpRptWiFiOK = _FALSE;
+ GLBtcBtMpRptBTOK = _FALSE;
return _TRUE;
}
void EXhalbtcoutsrc_PowerOnSetting(PBTC_COEXIST pBtCoexist)
{
+ HAL_DATA_TYPE *pHalData = NULL;
+
if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
return;
- /* Power on setting function is only added in 8723B currently */
+ pHalData = GET_HAL_DATA((PADAPTER)pBtCoexist->Adapter);
+
if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+#ifdef CONFIG_RTL8723B
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8723b2ant_power_on_setting(pBtCoexist);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8723b1ant_power_on_setting(pBtCoexist);
+#endif
}
- if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+#ifdef CONFIG_RTL8703B
+ else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
+ if (pBtCoexist->board_info.btdm_ant_num == 1)
+ ex_halbtc8703b1ant_power_on_setting(pBtCoexist);
+ }
+#endif
+
+#ifdef CONFIG_RTL8723D
+ else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8723d2ant_power_on_setting(pBtCoexist);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8723d1ant_power_on_setting(pBtCoexist);
}
+#endif
+
+#ifdef CONFIG_RTL8821A
+ else if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
+ if (pBtCoexist->board_info.btdm_ant_num == 1)
+ ex_halbtc8821a1ant_power_on_setting(pBtCoexist);
+ else if (pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8821a2ant_power_on_setting(pBtCoexist);
+ }
+#endif
- if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
+#ifdef CONFIG_RTL8822B
+ else if ((IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) && (pHalData->EEPROMBluetoothCoexist == _TRUE)) {
if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8822b1ant_power_on_setting(pBtCoexist);
+ else if (pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8822b2ant_power_on_setting(pBtCoexist);
+ }
+#endif
+
+#ifdef CONFIG_RTL8821C
+ else if ((IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) && (pHalData->EEPROMBluetoothCoexist == _TRUE)) {
+ if (pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8821c2ant_power_on_setting(pBtCoexist);
+ else if (pBtCoexist->board_info.btdm_ant_num == 1)
+ ex_halbtc8821c1ant_power_on_setting(pBtCoexist);
}
+#endif
}
void EXhalbtcoutsrc_PreLoadFirmware(PBTC_COEXIST pBtCoexist)
@@ -2224,21 +2703,34 @@ void EXhalbtcoutsrc_PreLoadFirmware(PBTC_COEXIST pBtCoexist)
if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
return;
- pBtCoexist->statistics.cntPreLoadFirmware++;
+ pBtCoexist->statistics.cnt_pre_load_firmware++;
if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+#ifdef CONFIG_RTL8723B
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8723b2ant_pre_load_firmware(pBtCoexist);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8723b1ant_pre_load_firmware(pBtCoexist);
+#endif
}
- if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+#ifdef CONFIG_RTL8723D
+ else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8723d2ant_pre_load_firmware(pBtCoexist);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8723d1ant_pre_load_firmware(pBtCoexist);
}
+#endif
+
+#ifdef CONFIG_RTL8821C
+ else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
+ if (pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8821c2ant_pre_load_firmware(pBtCoexist);
+ else if (pBtCoexist->board_info.btdm_ant_num == 1)
+ ex_halbtc8821c1ant_pre_load_firmware(pBtCoexist);
+ }
+#endif
}
void EXhalbtcoutsrc_init_hw_config(PBTC_COEXIST pBtCoexist, u8 bWifiOnly)
@@ -2246,42 +2738,85 @@ void EXhalbtcoutsrc_init_hw_config(PBTC_COEXIST pBtCoexist, u8 bWifiOnly)
if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
return;
- pBtCoexist->statistics.cntInitHwConfig++;
+ pBtCoexist->statistics.cnt_init_hw_config++;
if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
- if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE)
- ex_halbtc8821aCsr2ant_init_hw_config(pBtCoexist, bWifiOnly);
- else if (pBtCoexist->board_info.btdm_ant_num == 2)
+#ifdef CONFIG_RTL8821A
+ if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8821a2ant_init_hw_config(pBtCoexist, bWifiOnly);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8821a1ant_init_hw_config(pBtCoexist, bWifiOnly);
- } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+#endif
+ }
+
+#ifdef CONFIG_RTL8723B
+ else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8723b2ant_init_hw_config(pBtCoexist, bWifiOnly);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8723b1ant_init_hw_config(pBtCoexist, bWifiOnly);
- } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8703B
+ else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8703b1ant_init_hw_config(pBtCoexist, bWifiOnly);
- } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8723D
+ else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8723d2ant_init_hw_config(pBtCoexist, bWifiOnly);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8723d1ant_init_hw_config(pBtCoexist, bWifiOnly);
- } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8192E
+ else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8192e2ant_init_hw_config(pBtCoexist, bWifiOnly);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8192e1ant_init_hw_config(pBtCoexist, bWifiOnly);
- } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8812A
+ else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8812a2ant_init_hw_config(pBtCoexist, bWifiOnly);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8812a1ant_init_hw_config(pBtCoexist, bWifiOnly);
- } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8822B
+ else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8822b1ant_init_hw_config(pBtCoexist, bWifiOnly);
+ else if (pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8822b2ant_init_hw_config(pBtCoexist, bWifiOnly);
+ #ifdef CONFIG_FW_MULTI_PORT_SUPPORT
+ rtw_hal_set_default_port_id_cmd(pBtCoexist->Adapter, 0);
+ rtw_hal_set_wifi_port_id_cmd(pBtCoexist->Adapter);
+ #endif
+ }
+#endif
+
+#ifdef CONFIG_RTL8821C
+ else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
+ if (pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8821c2ant_init_hw_config(pBtCoexist, bWifiOnly);
+ else if (pBtCoexist->board_info.btdm_ant_num == 1)
+ ex_halbtc8821c1ant_init_hw_config(pBtCoexist, bWifiOnly);
+ #ifdef CONFIG_FW_MULTI_PORT_SUPPORT
+ rtw_hal_set_default_port_id_cmd(pBtCoexist->Adapter, 0);
+ rtw_hal_set_wifi_port_id_cmd(pBtCoexist->Adapter);
+ #endif
}
+#endif
}
void EXhalbtcoutsrc_init_coex_dm(PBTC_COEXIST pBtCoexist)
@@ -2289,42 +2824,77 @@ void EXhalbtcoutsrc_init_coex_dm(PBTC_COEXIST pBtCoexist)
if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
return;
- pBtCoexist->statistics.cntInitCoexDm++;
+ pBtCoexist->statistics.cnt_init_coex_dm++;
if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
- if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE)
- ex_halbtc8821aCsr2ant_init_coex_dm(pBtCoexist);
- else if (pBtCoexist->board_info.btdm_ant_num == 2)
+#ifdef CONFIG_RTL8821A
+ if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8821a2ant_init_coex_dm(pBtCoexist);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8821a1ant_init_coex_dm(pBtCoexist);
- } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+#endif
+ }
+
+#ifdef CONFIG_RTL8723B
+ else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8723b2ant_init_coex_dm(pBtCoexist);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8723b1ant_init_coex_dm(pBtCoexist);
- } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8703B
+ else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8703b1ant_init_coex_dm(pBtCoexist);
- } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8723D
+ else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8723d2ant_init_coex_dm(pBtCoexist);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8723d1ant_init_coex_dm(pBtCoexist);
- } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8192E
+ else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8192e2ant_init_coex_dm(pBtCoexist);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8192e1ant_init_coex_dm(pBtCoexist);
- } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8812A
+ else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8812a2ant_init_coex_dm(pBtCoexist);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8812a1ant_init_coex_dm(pBtCoexist);
- } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8822B
+ else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8822b1ant_init_coex_dm(pBtCoexist);
+ else if (pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8822b2ant_init_coex_dm(pBtCoexist);
+ }
+#endif
+
+#ifdef CONFIG_RTL8821C
+ else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
+ if (pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8821c2ant_init_coex_dm(pBtCoexist);
+ else if (pBtCoexist->board_info.btdm_ant_num == 1)
+ ex_halbtc8821c1ant_init_coex_dm(pBtCoexist);
}
+#endif
pBtCoexist->initilized = _TRUE;
}
@@ -2336,7 +2906,7 @@ void EXhalbtcoutsrc_ips_notify(PBTC_COEXIST pBtCoexist, u8 type)
if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
return;
- pBtCoexist->statistics.cntIpsNotify++;
+ pBtCoexist->statistics.cnt_ips_notify++;
if (pBtCoexist->manual_control)
return;
@@ -2352,40 +2922,74 @@ void EXhalbtcoutsrc_ips_notify(PBTC_COEXIST pBtCoexist, u8 type)
* halbtcoutsrc_LeaveLowPower(pBtCoexist); */
if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
- if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE)
- ex_halbtc8821aCsr2ant_ips_notify(pBtCoexist, ipsType);
- else if (pBtCoexist->board_info.btdm_ant_num == 2)
+#ifdef CONFIG_RTL8821A
+ if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8821a2ant_ips_notify(pBtCoexist, ipsType);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8821a1ant_ips_notify(pBtCoexist, ipsType);
- } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+#endif
+ }
+
+#ifdef CONFIG_RTL8723B
+ else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8723b2ant_ips_notify(pBtCoexist, ipsType);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8723b1ant_ips_notify(pBtCoexist, ipsType);
- } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8703B
+ else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8703b1ant_ips_notify(pBtCoexist, ipsType);
- } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8723D
+ else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8723d2ant_ips_notify(pBtCoexist, ipsType);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8723d1ant_ips_notify(pBtCoexist, ipsType);
- } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8192E
+ else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8192e2ant_ips_notify(pBtCoexist, ipsType);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8192e1ant_ips_notify(pBtCoexist, ipsType);
- } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8812A
+ else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8812a2ant_ips_notify(pBtCoexist, ipsType);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8812a1ant_ips_notify(pBtCoexist, ipsType);
- } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8822B
+ else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8822b1ant_ips_notify(pBtCoexist, ipsType);
+ else if (pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8822b2ant_ips_notify(pBtCoexist, ipsType);
}
+#endif
+#ifdef CONFIG_RTL8821C
+ else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
+ if (pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8821c2ant_ips_notify(pBtCoexist, ipsType);
+ else if (pBtCoexist->board_info.btdm_ant_num == 1)
+ ex_halbtc8821c1ant_ips_notify(pBtCoexist, ipsType);
+ }
+#endif
/* halbtcoutsrc_NormalLowPower(pBtCoexist); */
}
@@ -2397,7 +3001,7 @@ void EXhalbtcoutsrc_lps_notify(PBTC_COEXIST pBtCoexist, u8 type)
if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
return;
- pBtCoexist->statistics.cntLpsNotify++;
+ pBtCoexist->statistics.cnt_lps_notify++;
if (pBtCoexist->manual_control)
return;
@@ -2410,40 +3014,75 @@ void EXhalbtcoutsrc_lps_notify(PBTC_COEXIST pBtCoexist, u8 type)
}
if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
- if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE)
- ex_halbtc8821aCsr2ant_lps_notify(pBtCoexist, lpsType);
- else if (pBtCoexist->board_info.btdm_ant_num == 2)
+#ifdef CONFIG_RTL8821A
+ if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8821a2ant_lps_notify(pBtCoexist, lpsType);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8821a1ant_lps_notify(pBtCoexist, lpsType);
- } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+#endif
+ }
+
+#ifdef CONFIG_RTL8723B
+ else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8723b2ant_lps_notify(pBtCoexist, lpsType);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8723b1ant_lps_notify(pBtCoexist, lpsType);
- } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8703B
+ else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8703b1ant_lps_notify(pBtCoexist, lpsType);
- } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8723D
+ else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8723d2ant_lps_notify(pBtCoexist, lpsType);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8723d1ant_lps_notify(pBtCoexist, lpsType);
- } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8192E
+ else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8192e2ant_lps_notify(pBtCoexist, lpsType);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8192e1ant_lps_notify(pBtCoexist, lpsType);
- } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8812A
+ else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8812a2ant_lps_notify(pBtCoexist, lpsType);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8812a1ant_lps_notify(pBtCoexist, lpsType);
- } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
- if (pBtCoexist->board_info.btdm_ant_num == 1)
- ex_halbtc8822b1ant_lps_notify(pBtCoexist, lpsType);
}
-}
+#endif
+
+#ifdef CONFIG_RTL8822B
+ else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
+ if (pBtCoexist->board_info.btdm_ant_num == 1)
+ ex_halbtc8822b1ant_lps_notify(pBtCoexist, lpsType);
+ else if (pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8822b2ant_lps_notify(pBtCoexist, lpsType);
+ }
+#endif
+
+#ifdef CONFIG_RTL8821C
+ else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
+ if (pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8821c2ant_lps_notify(pBtCoexist, lpsType);
+ else if (pBtCoexist->board_info.btdm_ant_num == 1)
+ ex_halbtc8821c1ant_lps_notify(pBtCoexist, lpsType);
+ }
+#endif
+}
void EXhalbtcoutsrc_scan_notify(PBTC_COEXIST pBtCoexist, u8 type)
{
@@ -2451,7 +3090,7 @@ void EXhalbtcoutsrc_scan_notify(PBTC_COEXIST pBtCoexist, u8 type)
if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
return;
- pBtCoexist->statistics.cntScanNotify++;
+ pBtCoexist->statistics.cnt_scan_notify++;
if (pBtCoexist->manual_control)
return;
@@ -2467,95 +3106,187 @@ void EXhalbtcoutsrc_scan_notify(PBTC_COEXIST pBtCoexist, u8 type)
* halbtcoutsrc_LeaveLowPower(pBtCoexist); */
if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
- if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE)
- ex_halbtc8821aCsr2ant_scan_notify(pBtCoexist, scanType);
- else if (pBtCoexist->board_info.btdm_ant_num == 2)
+#ifdef CONFIG_RTL8821A
+ if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8821a2ant_scan_notify(pBtCoexist, scanType);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8821a1ant_scan_notify(pBtCoexist, scanType);
- } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+#endif
+ }
+
+#ifdef CONFIG_RTL8723B
+ else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8723b2ant_scan_notify(pBtCoexist, scanType);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8723b1ant_scan_notify(pBtCoexist, scanType);
- } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8703B
+ else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8703b1ant_scan_notify(pBtCoexist, scanType);
- } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8723D
+ else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8723d2ant_scan_notify(pBtCoexist, scanType);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8723d1ant_scan_notify(pBtCoexist, scanType);
- } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8192E
+ else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8192e2ant_scan_notify(pBtCoexist, scanType);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8192e1ant_scan_notify(pBtCoexist, scanType);
- } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8812A
+ else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8812a2ant_scan_notify(pBtCoexist, scanType);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8812a1ant_scan_notify(pBtCoexist, scanType);
- } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8822B
+ else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8822b1ant_scan_notify(pBtCoexist, scanType);
+ else if (pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8822b2ant_scan_notify(pBtCoexist, scanType);
}
+#endif
+
+#ifdef CONFIG_RTL8821C
+ else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
+ if (pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8821c2ant_scan_notify(pBtCoexist, scanType);
+ else if (pBtCoexist->board_info.btdm_ant_num == 1)
+ ex_halbtc8821c1ant_scan_notify(pBtCoexist, scanType);
+ }
+#endif
/* halbtcoutsrc_NormalLowPower(pBtCoexist); */
}
-void EXhalbtcoutsrc_connect_notify(PBTC_COEXIST pBtCoexist, u8 action)
+void EXhalbtcoutsrc_SetAntennaPathNotify(PBTC_COEXIST pBtCoexist, u8 type)
{
- u8 assoType;
+#if 0
+ u8 switchType;
if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
return;
- pBtCoexist->statistics.cntConnectNotify++;
+
if (pBtCoexist->manual_control)
return;
- if (action)
- assoType = BTC_ASSOCIATE_START;
- else
- assoType = BTC_ASSOCIATE_FINISH;
+ halbtcoutsrc_LeaveLowPower(pBtCoexist);
+ switchType = type;
+
+ if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+ if (pBtCoexist->board_info.btdm_ant_num == 1)
+ ex_halbtc8723b1ant_set_antenna_notify(pBtCoexist, type);
+ }
+ if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+ if (pBtCoexist->board_info.btdm_ant_num == 1)
+ ex_halbtc8723d1ant_set_antenna_notify(pBtCoexist, type);
+ else if (pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8723d2ant_set_antenna_notify(pBtCoexist, type);
+ }
+
+ halbtcoutsrc_NormalLowPower(pBtCoexist);
+#endif
+}
+
+void EXhalbtcoutsrc_connect_notify(PBTC_COEXIST pBtCoexist, u8 assoType)
+{
+ if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
+ return;
+ pBtCoexist->statistics.cnt_connect_notify++;
+ if (pBtCoexist->manual_control)
+ return;
+
/* All notify is called in cmd thread, don't need to leave low power again
* halbtcoutsrc_LeaveLowPower(pBtCoexist); */
-
if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
- if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE)
- ex_halbtc8821aCsr2ant_connect_notify(pBtCoexist, assoType);
- else if (pBtCoexist->board_info.btdm_ant_num == 2)
+#ifdef CONFIG_RTL8821A
+ if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8821a2ant_connect_notify(pBtCoexist, assoType);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8821a1ant_connect_notify(pBtCoexist, assoType);
- } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+#endif
+ }
+
+#ifdef CONFIG_RTL8723B
+ else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8723b2ant_connect_notify(pBtCoexist, assoType);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8723b1ant_connect_notify(pBtCoexist, assoType);
- } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8703B
+ else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8703b1ant_connect_notify(pBtCoexist, assoType);
- } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8723D
+ else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8723d2ant_connect_notify(pBtCoexist, assoType);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8723d1ant_connect_notify(pBtCoexist, assoType);
- } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8192E
+ else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8192e2ant_connect_notify(pBtCoexist, assoType);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8192e1ant_connect_notify(pBtCoexist, assoType);
- } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8812A
+ else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8812a2ant_connect_notify(pBtCoexist, assoType);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8812a1ant_connect_notify(pBtCoexist, assoType);
- } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8822B
+ else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8822b1ant_connect_notify(pBtCoexist, assoType);
+ else if (pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8822b2ant_connect_notify(pBtCoexist, assoType);
}
+#endif
+
+#ifdef CONFIG_RTL8821C
+ else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
+ if (pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8821c2ant_connect_notify(pBtCoexist, assoType);
+ else if (pBtCoexist->board_info.btdm_ant_num == 1)
+ ex_halbtc8821c1ant_connect_notify(pBtCoexist, assoType);
+ }
+#endif
/* halbtcoutsrc_NormalLowPower(pBtCoexist); */
}
@@ -2567,7 +3298,7 @@ void EXhalbtcoutsrc_media_status_notify(PBTC_COEXIST pBtCoexist, RT_MEDIA_STATUS
if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
return;
- pBtCoexist->statistics.cntMediaStatusNotify++;
+ pBtCoexist->statistics.cnt_media_status_notify++;
if (pBtCoexist->manual_control)
return;
@@ -2578,41 +3309,75 @@ void EXhalbtcoutsrc_media_status_notify(PBTC_COEXIST pBtCoexist, RT_MEDIA_STATUS
/* All notify is called in cmd thread, don't need to leave low power again
* halbtcoutsrc_LeaveLowPower(pBtCoexist); */
-
if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
- if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE)
- ex_halbtc8821aCsr2ant_media_status_notify(pBtCoexist, mStatus);
- else if (pBtCoexist->board_info.btdm_ant_num == 2)
+#ifdef CONFIG_RTL8821A
+ if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8821a2ant_media_status_notify(pBtCoexist, mStatus);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8821a1ant_media_status_notify(pBtCoexist, mStatus);
- } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+#endif
+ }
+
+#ifdef CONFIG_RTL8723B
+ else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8723b2ant_media_status_notify(pBtCoexist, mStatus);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8723b1ant_media_status_notify(pBtCoexist, mStatus);
- } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8703B
+ else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8703b1ant_media_status_notify(pBtCoexist, mStatus);
- } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8723D
+ else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8723d2ant_media_status_notify(pBtCoexist, mStatus);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8723d1ant_media_status_notify(pBtCoexist, mStatus);
- } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8192E
+ else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8192e2ant_media_status_notify(pBtCoexist, mStatus);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8192e1ant_media_status_notify(pBtCoexist, mStatus);
- } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8812A
+ else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8812a2ant_media_status_notify(pBtCoexist, mStatus);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8812a1ant_media_status_notify(pBtCoexist, mStatus);
- } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8822B
+ else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8822b1ant_media_status_notify(pBtCoexist, mStatus);
+ else if (pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8822b2ant_media_status_notify(pBtCoexist, mStatus);
}
+#endif
+
+#ifdef CONFIG_RTL8821C
+ else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
+ if (pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8821c2ant_media_status_notify(pBtCoexist, mStatus);
+ else if (pBtCoexist->board_info.btdm_ant_num == 1)
+ ex_halbtc8821c1ant_media_status_notify(pBtCoexist, mStatus);
+ }
+#endif
/* halbtcoutsrc_NormalLowPower(pBtCoexist); */
}
@@ -2623,7 +3388,7 @@ void EXhalbtcoutsrc_specific_packet_notify(PBTC_COEXIST pBtCoexist, u8 pktType)
if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
return;
- pBtCoexist->statistics.cntSpecificPacketNotify++;
+ pBtCoexist->statistics.cnt_specific_packet_notify++;
if (pBtCoexist->manual_control)
return;
@@ -2640,41 +3405,75 @@ void EXhalbtcoutsrc_specific_packet_notify(PBTC_COEXIST pBtCoexist, u8 pktType)
/* All notify is called in cmd thread, don't need to leave low power again
* halbtcoutsrc_LeaveLowPower(pBtCoexist); */
-
if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
- if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE)
- ex_halbtc8821aCsr2ant_specific_packet_notify(pBtCoexist, packetType);
- else if (pBtCoexist->board_info.btdm_ant_num == 2)
+#ifdef CONFIG_RTL8821A
+ if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8821a2ant_specific_packet_notify(pBtCoexist, packetType);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8821a1ant_specific_packet_notify(pBtCoexist, packetType);
- } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+#endif
+ }
+
+#ifdef CONFIG_RTL8723B
+ else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8723b2ant_specific_packet_notify(pBtCoexist, packetType);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8723b1ant_specific_packet_notify(pBtCoexist, packetType);
- } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8703B
+ else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8703b1ant_specific_packet_notify(pBtCoexist, packetType);
- } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8723D
+ else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8723d2ant_specific_packet_notify(pBtCoexist, packetType);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8723d1ant_specific_packet_notify(pBtCoexist, packetType);
- } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8192E
+ else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8192e2ant_specific_packet_notify(pBtCoexist, packetType);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8192e1ant_specific_packet_notify(pBtCoexist, packetType);
- } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8812A
+ else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8812a2ant_specific_packet_notify(pBtCoexist, packetType);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8812a1ant_specific_packet_notify(pBtCoexist, packetType);
- } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8822B
+ else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8822b1ant_specific_packet_notify(pBtCoexist, packetType);
+ else if (pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8822b2ant_specific_packet_notify(pBtCoexist, packetType);
+ }
+#endif
+
+#ifdef CONFIG_RTL8821C
+ else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
+ if (pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8821c2ant_specific_packet_notify(pBtCoexist, packetType);
+ else if (pBtCoexist->board_info.btdm_ant_num == 1)
+ ex_halbtc8821c1ant_specific_packet_notify(pBtCoexist, packetType);
}
+#endif
/* halbtcoutsrc_NormalLowPower(pBtCoexist); */
}
@@ -2684,49 +3483,147 @@ void EXhalbtcoutsrc_bt_info_notify(PBTC_COEXIST pBtCoexist, u8 *tmpBuf, u8 lengt
if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
return;
- pBtCoexist->statistics.cntBtInfoNotify++;
+ pBtCoexist->statistics.cnt_bt_info_notify++;
/* All notify is called in cmd thread, don't need to leave low power again
* halbtcoutsrc_LeaveLowPower(pBtCoexist); */
-
if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
- if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE)
- ex_halbtc8821aCsr2ant_bt_info_notify(pBtCoexist, tmpBuf, length);
- else if (pBtCoexist->board_info.btdm_ant_num == 2)
+#ifdef CONFIG_RTL8821A
+ if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8821a2ant_bt_info_notify(pBtCoexist, tmpBuf, length);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8821a1ant_bt_info_notify(pBtCoexist, tmpBuf, length);
- } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+#endif
+ }
+
+#ifdef CONFIG_RTL8723B
+ else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8723b2ant_bt_info_notify(pBtCoexist, tmpBuf, length);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8723b1ant_bt_info_notify(pBtCoexist, tmpBuf, length);
- } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8703B
+ else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8703b1ant_bt_info_notify(pBtCoexist, tmpBuf, length);
- } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8723D
+ else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8723d2ant_bt_info_notify(pBtCoexist, tmpBuf, length);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8723d1ant_bt_info_notify(pBtCoexist, tmpBuf, length);
- } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8192E
+ else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8192e2ant_bt_info_notify(pBtCoexist, tmpBuf, length);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8192e1ant_bt_info_notify(pBtCoexist, tmpBuf, length);
- } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8812A
+ else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8812a2ant_bt_info_notify(pBtCoexist, tmpBuf, length);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8812a1ant_bt_info_notify(pBtCoexist, tmpBuf, length);
- } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8822B
+ else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8822b1ant_bt_info_notify(pBtCoexist, tmpBuf, length);
+ else if (pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8822b2ant_bt_info_notify(pBtCoexist, tmpBuf, length);
}
+#endif
+
+#ifdef CONFIG_RTL8821C
+ else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
+ if (pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8821c2ant_bt_info_notify(pBtCoexist, tmpBuf, length);
+ else if (pBtCoexist->board_info.btdm_ant_num == 1)
+ ex_halbtc8821c1ant_bt_info_notify(pBtCoexist, tmpBuf, length);
+ }
+#endif
/* halbtcoutsrc_NormalLowPower(pBtCoexist); */
}
+void EXhalbtcoutsrc_WlFwDbgInfoNotify(PBTC_COEXIST pBtCoexist, u8* tmpBuf, u8 length)
+{
+ if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
+ return;
+
+ if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
+#ifdef CONFIG_RTL8703B
+ if (pBtCoexist->board_info.btdm_ant_num == 1)
+ ex_halbtc8703b1ant_wl_fwdbginfo_notify(pBtCoexist, tmpBuf, length);
+#endif
+ }
+
+#ifdef CONFIG_RTL8723D
+ else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+ if (pBtCoexist->board_info.btdm_ant_num == 1)
+ ex_halbtc8723d1ant_wl_fwdbginfo_notify(pBtCoexist, tmpBuf, length);
+ else if (pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8723d2ant_wl_fwdbginfo_notify(pBtCoexist, tmpBuf, length);
+ }
+#endif
+
+#ifdef CONFIG_RTL8821C
+ else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
+ if (pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8821c2ant_wl_fwdbginfo_notify(pBtCoexist, tmpBuf, length);
+ else if (pBtCoexist->board_info.btdm_ant_num == 1)
+ ex_halbtc8821c1ant_wl_fwdbginfo_notify(pBtCoexist, tmpBuf, length);
+ }
+#endif
+}
+
+void EXhalbtcoutsrc_rx_rate_change_notify(PBTC_COEXIST pBtCoexist, u8 is_data_frame, u8 btc_rate_id)
+{
+ if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
+ return;
+
+ pBtCoexist->statistics.cnt_rate_id_notify++;
+
+ if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
+#ifdef CONFIG_RTL8703B
+ if (pBtCoexist->board_info.btdm_ant_num == 1)
+ ex_halbtc8703b1ant_rx_rate_change_notify(pBtCoexist, is_data_frame, btc_rate_id);
+#endif
+ }
+
+#ifdef CONFIG_RTL8723D
+ else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+ if (pBtCoexist->board_info.btdm_ant_num == 1)
+ ex_halbtc8723d1ant_rx_rate_change_notify(pBtCoexist, is_data_frame, btc_rate_id);
+ else if (pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8723d2ant_rx_rate_change_notify(pBtCoexist, is_data_frame, btc_rate_id);
+ }
+#endif
+
+#ifdef CONFIG_RTL8821C
+ else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
+ if (pBtCoexist->board_info.btdm_ant_num == 1)
+ ex_halbtc8821c1ant_rx_rate_change_notify(pBtCoexist, is_data_frame, btc_rate_id);
+ else if (pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8821c2ant_rx_rate_change_notify(pBtCoexist, is_data_frame, btc_rate_id);
+ }
+#endif
+}
+
VOID
EXhalbtcoutsrc_RfStatusNotify(
IN PBTC_COEXIST pBtCoexist,
@@ -2735,24 +3632,46 @@ EXhalbtcoutsrc_RfStatusNotify(
{
if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
return;
- pBtCoexist->statistics.cntRfStatusNotify++;
+ pBtCoexist->statistics.cnt_rf_status_notify++;
- if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
- } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+ if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+#ifdef CONFIG_RTL8723B
if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8723b1ant_rf_status_notify(pBtCoexist, type);
- } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
+#endif
+ }
+
+#ifdef CONFIG_RTL8703B
+ else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8703b1ant_rf_status_notify(pBtCoexist, type);
- } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8723D
+ else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8723d1ant_rf_status_notify(pBtCoexist, type);
- } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
- } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
- } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8822B
+ else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8822b1ant_rf_status_notify(pBtCoexist, type);
+ else if (pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8822b2ant_rf_status_notify(pBtCoexist, type);
+ }
+#endif
+
+#ifdef CONFIG_RTL8821C
+ else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
+ if (pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8821c2ant_rf_status_notify(pBtCoexist, type);
+ else if (pBtCoexist->board_info.btdm_ant_num == 1)
+ ex_halbtc8821c1ant_rf_status_notify(pBtCoexist, type);
}
+#endif
}
void EXhalbtcoutsrc_StackOperationNotify(PBTC_COEXIST pBtCoexist, u8 type)
@@ -2787,41 +3706,74 @@ void EXhalbtcoutsrc_halt_notify(PBTC_COEXIST pBtCoexist)
return;
if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
- if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE)
- ex_halbtc8821aCsr2ant_halt_notify(pBtCoexist);
- else if (pBtCoexist->board_info.btdm_ant_num == 2)
+#ifdef CONFIG_RTL8821A
+ if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8821a2ant_halt_notify(pBtCoexist);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8821a1ant_halt_notify(pBtCoexist);
- } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+#endif
+ }
+
+#ifdef CONFIG_RTL8723B
+ else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8723b2ant_halt_notify(pBtCoexist);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8723b1ant_halt_notify(pBtCoexist);
- } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8703B
+ else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8703b1ant_halt_notify(pBtCoexist);
- } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8723D
+ else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8723d2ant_halt_notify(pBtCoexist);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8723d1ant_halt_notify(pBtCoexist);
- } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8192E
+ else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8192e2ant_halt_notify(pBtCoexist);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8192e1ant_halt_notify(pBtCoexist);
- } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8812A
+ else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8812a2ant_halt_notify(pBtCoexist);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8812a1ant_halt_notify(pBtCoexist);
- } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8822B
+ else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8822b1ant_halt_notify(pBtCoexist);
+ else if (pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8822b2ant_halt_notify(pBtCoexist);
}
+#endif
- pBtCoexist->bBinded = FALSE;
+#ifdef CONFIG_RTL8821C
+ else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
+ if (pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8821c2ant_halt_notify(pBtCoexist);
+ else if (pBtCoexist->board_info.btdm_ant_num == 1)
+ ex_halbtc8821c1ant_halt_notify(pBtCoexist);
+ }
+#endif
}
void EXhalbtcoutsrc_SwitchBtTRxMask(PBTC_COEXIST pBtCoexist)
@@ -2844,48 +3796,69 @@ void EXhalbtcoutsrc_pnp_notify(PBTC_COEXIST pBtCoexist, u8 pnpState)
/* currently only 1ant we have to do the notification, */
/* once pnp is notified to sleep state, we have to leave LPS that we can sleep normally. */
/* */
-
if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+#ifdef CONFIG_RTL8723B
if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8723b1ant_pnp_notify(pBtCoexist, pnpState);
else if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8723b2ant_pnp_notify(pBtCoexist, pnpState);
- } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
+#endif
+ }
+
+#ifdef CONFIG_RTL8703B
+ else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8703b1ant_pnp_notify(pBtCoexist, pnpState);
- } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8723D
+ else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8723d1ant_pnp_notify(pBtCoexist, pnpState);
else if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8723d2ant_pnp_notify(pBtCoexist, pnpState);
- } else if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
- if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE)
- ex_halbtc8821aCsr2ant_pnp_notify(pBtCoexist, pnpState);
- else if (pBtCoexist->board_info.btdm_ant_num == 1)
+ }
+#endif
+
+#ifdef CONFIG_RTL8821A
+ else if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
+ if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8821a1ant_pnp_notify(pBtCoexist, pnpState);
else if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8821a2ant_pnp_notify(pBtCoexist, pnpState);
- } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8192E
+ else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8192e1ant_pnp_notify(pBtCoexist, pnpState);
- } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8812A
+ else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8812a1ant_pnp_notify(pBtCoexist, pnpState);
- } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8822B
+ else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8822b1ant_pnp_notify(pBtCoexist, pnpState);
+ else if (pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8822b2ant_pnp_notify(pBtCoexist, pnpState);
}
-}
+#endif
-void EXhalbtcoutsrc_ScoreBoardStatusNotify(PBTC_COEXIST pBtCoexist, u8 *tmpBuf, u8 length)
-{
-#if 0
- if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
- if (pBtCoexist->board_info.btdm_ant_num == 1)
- ex_halbtc8703b1ant_ScoreBoardStatusNotify(pBtCoexist, tmpBuf, length);
- } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
- if (pBtCoexist->board_info.btdm_ant_num == 1)
- ;/*ex_halbtc8723d1ant_ScoreBoardStatusNotify(pBtCoexist, tmpBuf, length);*/
+#ifdef CONFIG_RTL8821C
+ else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
+ if (pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8821c2ant_pnp_notify(pBtCoexist, pnpState);
+ else if (pBtCoexist->board_info.btdm_ant_num == 1)
+ ex_halbtc8821c1ant_pnp_notify(pBtCoexist, pnpState);
}
#endif
}
@@ -2894,11 +3867,12 @@ void EXhalbtcoutsrc_CoexDmSwitch(PBTC_COEXIST pBtCoexist)
{
if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
return;
- pBtCoexist->statistics.cntCoexDmSwitch++;
+ pBtCoexist->statistics.cnt_coex_dm_switch++;
halbtcoutsrc_LeaveLowPower(pBtCoexist);
if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+#ifdef CONFIG_RTL8723B
if (pBtCoexist->board_info.btdm_ant_num == 1) {
pBtCoexist->stop_coex_dm = TRUE;
ex_halbtc8723b1ant_coex_dm_reset(pBtCoexist);
@@ -2907,7 +3881,11 @@ void EXhalbtcoutsrc_CoexDmSwitch(PBTC_COEXIST pBtCoexist)
ex_halbtc8723b2ant_init_coex_dm(pBtCoexist);
pBtCoexist->stop_coex_dm = FALSE;
}
- } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+#endif
+ }
+
+#ifdef CONFIG_RTL8723D
+ else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 1) {
pBtCoexist->stop_coex_dm = TRUE;
ex_halbtc8723d1ant_coex_dm_reset(pBtCoexist);
@@ -2917,6 +3895,7 @@ void EXhalbtcoutsrc_CoexDmSwitch(PBTC_COEXIST pBtCoexist)
pBtCoexist->stop_coex_dm = FALSE;
}
}
+#endif
halbtcoutsrc_NormalLowPower(pBtCoexist);
}
@@ -2925,48 +3904,82 @@ void EXhalbtcoutsrc_periodical(PBTC_COEXIST pBtCoexist)
{
if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
return;
- pBtCoexist->statistics.cntPeriodical++;
+ pBtCoexist->statistics.cnt_periodical++;
/* Periodical should be called in cmd thread, */
/* don't need to leave low power again
* halbtcoutsrc_LeaveLowPower(pBtCoexist); */
-
if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
- if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE)
- ex_halbtc8821aCsr2ant_periodical(pBtCoexist);
- else if (pBtCoexist->board_info.btdm_ant_num == 2)
+#ifdef CONFIG_RTL8821A
+ if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8821a2ant_periodical(pBtCoexist);
else if (pBtCoexist->board_info.btdm_ant_num == 1) {
if (!halbtcoutsrc_UnderIps(pBtCoexist))
ex_halbtc8821a1ant_periodical(pBtCoexist);
}
- } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+#endif
+ }
+
+#ifdef CONFIG_RTL8723B
+ else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8723b2ant_periodical(pBtCoexist);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8723b1ant_periodical(pBtCoexist);
- } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8723D
+ else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8723d2ant_periodical(pBtCoexist);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8723d1ant_periodical(pBtCoexist);
- } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8703B
+ else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8703b1ant_periodical(pBtCoexist);
- } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8192E
+ else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8192e2ant_periodical(pBtCoexist);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8192e1ant_periodical(pBtCoexist);
- } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8812A
+ else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8812a2ant_periodical(pBtCoexist);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8812a1ant_periodical(pBtCoexist);
- } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8822B
+ else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8822b1ant_periodical(pBtCoexist);
+ else if (pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8822b2ant_periodical(pBtCoexist);
+ }
+#endif
+
+#ifdef CONFIG_RTL8821C
+ else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
+ if (pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8821c2ant_periodical(pBtCoexist);
+ else if (pBtCoexist->board_info.btdm_ant_num == 1)
+ ex_halbtc8821c1ant_periodical(pBtCoexist);
}
+#endif
/* halbtcoutsrc_NormalLowPower(pBtCoexist); */
}
@@ -2976,23 +3989,32 @@ void EXhalbtcoutsrc_dbg_control(PBTC_COEXIST pBtCoexist, u8 opCode, u8 opLen, u8
if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
return;
- pBtCoexist->statistics.cntDbgCtrl++;
+ pBtCoexist->statistics.cnt_dbg_ctrl++;
/* This function doesn't be called yet, */
/* default no need to leave low power to avoid deadlock
* halbtcoutsrc_LeaveLowPower(pBtCoexist); */
-
if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
+#ifdef CONFIG_RTL8192E
if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8192e1ant_dbg_control(pBtCoexist, opCode, opLen, pData);
- } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
+#endif
+ }
+
+#ifdef CONFIG_RTL8812A
+ else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8812a2ant_dbg_control(pBtCoexist, opCode, opLen, pData);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8812a1ant_dbg_control(pBtCoexist, opCode, opLen, pData);
- } else if(IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter))
+ }
+#endif
+
+#ifdef CONFIG_RTL8822B
+ else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter))
if(pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8822b1ant_dbg_control(pBtCoexist, opCode, opLen, pData);
+#endif
/* halbtcoutsrc_NormalLowPower(pBtCoexist); */
}
@@ -3102,8 +4124,8 @@ void EXhalbtcoutsrc_SetBtPatchVersion(u16 btHciVersion, u16 btPatchVersion)
if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
return;
- pBtCoexist->btInfo.btRealFwVer = btPatchVersion;
- pBtCoexist->btInfo.btHciVer = btHciVersion;
+ pBtCoexist->bt_info.bt_real_fw_ver = btPatchVersion;
+ pBtCoexist->bt_info.bt_hci_ver = btHciVersion;
}
#if 0
@@ -3178,40 +4200,80 @@ void EXhalbtcoutsrc_DisplayBtCoexInfo(PBTC_COEXIST pBtCoexist)
halbtcoutsrc_LeaveLowPower(pBtCoexist);
+ /* To prevent the racing with IPS enter */
+ halbtcoutsrc_EnterPwrLock(pBtCoexist);
+
if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) {
- if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE)
- ex_halbtc8821aCsr2ant_display_coex_info(pBtCoexist);
- else if (pBtCoexist->board_info.btdm_ant_num == 2)
+#ifdef CONFIG_RTL8821A
+ if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8821a2ant_display_coex_info(pBtCoexist);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8821a1ant_display_coex_info(pBtCoexist);
- } else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+#endif
+ }
+
+#ifdef CONFIG_RTL8723B
+ else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8723b2ant_display_coex_info(pBtCoexist);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8723b1ant_display_coex_info(pBtCoexist);
- } else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8703B
+ else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8703b1ant_display_coex_info(pBtCoexist);
- } else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8723D
+ else if (IS_HARDWARE_TYPE_8723D(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8723d2ant_display_coex_info(pBtCoexist);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8723d1ant_display_coex_info(pBtCoexist);
- } else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8192E
+ else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8192e2ant_display_coex_info(pBtCoexist);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8192e1ant_display_coex_info(pBtCoexist);
- } else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8812A
+ else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
ex_halbtc8812a2ant_display_coex_info(pBtCoexist);
else if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8812a1ant_display_coex_info(pBtCoexist);
- } else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
+ }
+#endif
+
+#ifdef CONFIG_RTL8822B
+ else if (IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8822b1ant_display_coex_info(pBtCoexist);
+ else if (pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8822b2ant_display_coex_info(pBtCoexist);
+ }
+#endif
+
+#ifdef CONFIG_RTL8821C
+ else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
+ if (pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8821c2ant_display_coex_info(pBtCoexist);
+ else if (pBtCoexist->board_info.btdm_ant_num == 1)
+ ex_halbtc8821c1ant_display_coex_info(pBtCoexist);
}
+#endif
+
+ halbtcoutsrc_ExitPwrLock(pBtCoexist);
halbtcoutsrc_NormalLowPower(pBtCoexist);
}
@@ -3224,19 +4286,30 @@ void EXhalbtcoutsrc_DisplayAntDetection(PBTC_COEXIST pBtCoexist)
halbtcoutsrc_LeaveLowPower(pBtCoexist);
if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) {
+#ifdef CONFIG_RTL8723B
if (pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8723b1ant_display_ant_detection(pBtCoexist);
+#endif
+ }
+
+#ifdef CONFIG_RTL8821C
+ else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
+ if (pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8821c2ant_display_ant_detection(pBtCoexist);
+ else if (pBtCoexist->board_info.btdm_ant_num == 1)
+ ex_halbtc8821c1ant_display_ant_detection(pBtCoexist);
}
+#endif
halbtcoutsrc_NormalLowPower(pBtCoexist);
}
-void EXhalbtcoutsrc_BTOffOnNotify(PBTC_COEXIST pBtCoexist, u8 bBTON)
+void ex_halbtcoutsrc_pta_off_on_notify(PBTC_COEXIST pBtCoexist, u8 bBTON)
{
-#if 0 /* Jenyu Need commit to windows' SVN */
+#ifdef CONFIG_RTL8812A
if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) {
if (pBtCoexist->board_info.btdm_ant_num == 2)
- ex_halbtc8812a2ant_bt_off_on_notify(pBtCoexist, (bBTON == _TRUE) ? BTC_BT_ON : BTC_BT_OFF);
+ ex_halbtc8812a2ant_pta_off_on_notify(pBtCoexist, (bBTON == _TRUE) ? BTC_BT_ON : BTC_BT_OFF);
}
#endif
}
@@ -3246,6 +4319,18 @@ void EXhalbtcoutsrc_set_rfe_type(u8 type)
GLBtCoexist.board_info.rfe_type= type;
}
+#ifdef CONFIG_RF4CE_COEXIST
+void EXhalbtcoutsrc_set_rf4ce_link_state(u8 state)
+{
+ GLBtCoexist.rf4ce_info.link_state = state;
+}
+
+u8 EXhalbtcoutsrc_get_rf4ce_link_state(void)
+{
+ return GLBtCoexist.rf4ce_info.link_state;
+}
+#endif
+
void EXhalbtcoutsrc_switchband_notify(struct btc_coexist *pBtCoexist, u8 type)
{
if(!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist))
@@ -3254,15 +4339,299 @@ void EXhalbtcoutsrc_switchband_notify(struct btc_coexist *pBtCoexist, u8 type)
if(pBtCoexist->manual_control)
return;
-
- halbtcoutsrc_LeaveLowPower(pBtCoexist);
+ /* Driver should guarantee that the HW status isn't in low power mode */
+ /* halbtcoutsrc_LeaveLowPower(pBtCoexist); */
if(IS_HARDWARE_TYPE_8822B(pBtCoexist->Adapter)) {
+#ifdef CONFIG_RTL8822B
if(pBtCoexist->board_info.btdm_ant_num == 1)
ex_halbtc8822b1ant_switchband_notify(pBtCoexist, type);
+ else if(pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8822b2ant_switchband_notify(pBtCoexist, type);
+#endif
}
- halbtcoutsrc_NormalLowPower(pBtCoexist);
+#ifdef CONFIG_RTL8821C
+ else if (IS_HARDWARE_TYPE_8821C(pBtCoexist->Adapter)) {
+ if (pBtCoexist->board_info.btdm_ant_num == 2)
+ ex_halbtc8821c2ant_switchband_notify(pBtCoexist, type);
+ else if (pBtCoexist->board_info.btdm_ant_num == 1)
+ ex_halbtc8821c1ant_switchband_notify(pBtCoexist, type);
+ }
+#endif
+
+ /* halbtcoutsrc_NormalLowPower(pBtCoexist); */
+}
+
+u8 EXhalbtcoutsrc_rate_id_to_btc_rate_id(u8 rate_id)
+{
+ u8 btc_rate_id = BTC_UNKNOWN;
+
+ switch (rate_id) {
+ /* CCK rates */
+ case DESC_RATE1M:
+ btc_rate_id = BTC_CCK_1;
+ break;
+ case DESC_RATE2M:
+ btc_rate_id = BTC_CCK_2;
+ break;
+ case DESC_RATE5_5M:
+ btc_rate_id = BTC_CCK_5_5;
+ break;
+ case DESC_RATE11M:
+ btc_rate_id = BTC_CCK_11;
+ break;
+
+ /* OFDM rates */
+ case DESC_RATE6M:
+ btc_rate_id = BTC_OFDM_6;
+ break;
+ case DESC_RATE9M:
+ btc_rate_id = BTC_OFDM_9;
+ break;
+ case DESC_RATE12M:
+ btc_rate_id = BTC_OFDM_12;
+ break;
+ case DESC_RATE18M:
+ btc_rate_id = BTC_OFDM_18;
+ break;
+ case DESC_RATE24M:
+ btc_rate_id = BTC_OFDM_24;
+ break;
+ case DESC_RATE36M:
+ btc_rate_id = BTC_OFDM_36;
+ break;
+ case DESC_RATE48M:
+ btc_rate_id = BTC_OFDM_48;
+ break;
+ case DESC_RATE54M:
+ btc_rate_id = BTC_OFDM_54;
+ break;
+
+ /* MCS rates */
+ case DESC_RATEMCS0:
+ btc_rate_id = BTC_MCS_0;
+ break;
+ case DESC_RATEMCS1:
+ btc_rate_id = BTC_MCS_1;
+ break;
+ case DESC_RATEMCS2:
+ btc_rate_id = BTC_MCS_2;
+ break;
+ case DESC_RATEMCS3:
+ btc_rate_id = BTC_MCS_3;
+ break;
+ case DESC_RATEMCS4:
+ btc_rate_id = BTC_MCS_4;
+ break;
+ case DESC_RATEMCS5:
+ btc_rate_id = BTC_MCS_5;
+ break;
+ case DESC_RATEMCS6:
+ btc_rate_id = BTC_MCS_6;
+ break;
+ case DESC_RATEMCS7:
+ btc_rate_id = BTC_MCS_7;
+ break;
+ case DESC_RATEMCS8:
+ btc_rate_id = BTC_MCS_8;
+ break;
+ case DESC_RATEMCS9:
+ btc_rate_id = BTC_MCS_9;
+ break;
+ case DESC_RATEMCS10:
+ btc_rate_id = BTC_MCS_10;
+ break;
+ case DESC_RATEMCS11:
+ btc_rate_id = BTC_MCS_11;
+ break;
+ case DESC_RATEMCS12:
+ btc_rate_id = BTC_MCS_12;
+ break;
+ case DESC_RATEMCS13:
+ btc_rate_id = BTC_MCS_13;
+ break;
+ case DESC_RATEMCS14:
+ btc_rate_id = BTC_MCS_14;
+ break;
+ case DESC_RATEMCS15:
+ btc_rate_id = BTC_MCS_15;
+ break;
+ case DESC_RATEMCS16:
+ btc_rate_id = BTC_MCS_16;
+ break;
+ case DESC_RATEMCS17:
+ btc_rate_id = BTC_MCS_17;
+ break;
+ case DESC_RATEMCS18:
+ btc_rate_id = BTC_MCS_18;
+ break;
+ case DESC_RATEMCS19:
+ btc_rate_id = BTC_MCS_19;
+ break;
+ case DESC_RATEMCS20:
+ btc_rate_id = BTC_MCS_20;
+ break;
+ case DESC_RATEMCS21:
+ btc_rate_id = BTC_MCS_21;
+ break;
+ case DESC_RATEMCS22:
+ btc_rate_id = BTC_MCS_22;
+ break;
+ case DESC_RATEMCS23:
+ btc_rate_id = BTC_MCS_23;
+ break;
+ case DESC_RATEMCS24:
+ btc_rate_id = BTC_MCS_24;
+ break;
+ case DESC_RATEMCS25:
+ btc_rate_id = BTC_MCS_25;
+ break;
+ case DESC_RATEMCS26:
+ btc_rate_id = BTC_MCS_26;
+ break;
+ case DESC_RATEMCS27:
+ btc_rate_id = BTC_MCS_27;
+ break;
+ case DESC_RATEMCS28:
+ btc_rate_id = BTC_MCS_28;
+ break;
+ case DESC_RATEMCS29:
+ btc_rate_id = BTC_MCS_29;
+ break;
+ case DESC_RATEMCS30:
+ btc_rate_id = BTC_MCS_30;
+ break;
+ case DESC_RATEMCS31:
+ btc_rate_id = BTC_MCS_31;
+ break;
+
+ case DESC_RATEVHTSS1MCS0:
+ btc_rate_id = BTC_VHT_1SS_MCS_0;
+ break;
+ case DESC_RATEVHTSS1MCS1:
+ btc_rate_id = BTC_VHT_1SS_MCS_1;
+ break;
+ case DESC_RATEVHTSS1MCS2:
+ btc_rate_id = BTC_VHT_1SS_MCS_2;
+ break;
+ case DESC_RATEVHTSS1MCS3:
+ btc_rate_id = BTC_VHT_1SS_MCS_3;
+ break;
+ case DESC_RATEVHTSS1MCS4:
+ btc_rate_id = BTC_VHT_1SS_MCS_4;
+ break;
+ case DESC_RATEVHTSS1MCS5:
+ btc_rate_id = BTC_VHT_1SS_MCS_5;
+ break;
+ case DESC_RATEVHTSS1MCS6:
+ btc_rate_id = BTC_VHT_1SS_MCS_6;
+ break;
+ case DESC_RATEVHTSS1MCS7:
+ btc_rate_id = BTC_VHT_1SS_MCS_7;
+ break;
+ case DESC_RATEVHTSS1MCS8:
+ btc_rate_id = BTC_VHT_1SS_MCS_8;
+ break;
+ case DESC_RATEVHTSS1MCS9:
+ btc_rate_id = BTC_VHT_1SS_MCS_9;
+ break;
+
+ case DESC_RATEVHTSS2MCS0:
+ btc_rate_id = BTC_VHT_2SS_MCS_0;
+ break;
+ case DESC_RATEVHTSS2MCS1:
+ btc_rate_id = BTC_VHT_2SS_MCS_1;
+ break;
+ case DESC_RATEVHTSS2MCS2:
+ btc_rate_id = BTC_VHT_2SS_MCS_2;
+ break;
+ case DESC_RATEVHTSS2MCS3:
+ btc_rate_id = BTC_VHT_2SS_MCS_3;
+ break;
+ case DESC_RATEVHTSS2MCS4:
+ btc_rate_id = BTC_VHT_2SS_MCS_4;
+ break;
+ case DESC_RATEVHTSS2MCS5:
+ btc_rate_id = BTC_VHT_2SS_MCS_5;
+ break;
+ case DESC_RATEVHTSS2MCS6:
+ btc_rate_id = BTC_VHT_2SS_MCS_6;
+ break;
+ case DESC_RATEVHTSS2MCS7:
+ btc_rate_id = BTC_VHT_2SS_MCS_7;
+ break;
+ case DESC_RATEVHTSS2MCS8:
+ btc_rate_id = BTC_VHT_2SS_MCS_8;
+ break;
+ case DESC_RATEVHTSS2MCS9:
+ btc_rate_id = BTC_VHT_2SS_MCS_9;
+ break;
+
+ case DESC_RATEVHTSS3MCS0:
+ btc_rate_id = BTC_VHT_3SS_MCS_0;
+ break;
+ case DESC_RATEVHTSS3MCS1:
+ btc_rate_id = BTC_VHT_3SS_MCS_1;
+ break;
+ case DESC_RATEVHTSS3MCS2:
+ btc_rate_id = BTC_VHT_3SS_MCS_2;
+ break;
+ case DESC_RATEVHTSS3MCS3:
+ btc_rate_id = BTC_VHT_3SS_MCS_3;
+ break;
+ case DESC_RATEVHTSS3MCS4:
+ btc_rate_id = BTC_VHT_3SS_MCS_4;
+ break;
+ case DESC_RATEVHTSS3MCS5:
+ btc_rate_id = BTC_VHT_3SS_MCS_5;
+ break;
+ case DESC_RATEVHTSS3MCS6:
+ btc_rate_id = BTC_VHT_3SS_MCS_6;
+ break;
+ case DESC_RATEVHTSS3MCS7:
+ btc_rate_id = BTC_VHT_3SS_MCS_7;
+ break;
+ case DESC_RATEVHTSS3MCS8:
+ btc_rate_id = BTC_VHT_3SS_MCS_8;
+ break;
+ case DESC_RATEVHTSS3MCS9:
+ btc_rate_id = BTC_VHT_3SS_MCS_9;
+ break;
+
+ case DESC_RATEVHTSS4MCS0:
+ btc_rate_id = BTC_VHT_4SS_MCS_0;
+ break;
+ case DESC_RATEVHTSS4MCS1:
+ btc_rate_id = BTC_VHT_4SS_MCS_1;
+ break;
+ case DESC_RATEVHTSS4MCS2:
+ btc_rate_id = BTC_VHT_4SS_MCS_2;
+ break;
+ case DESC_RATEVHTSS4MCS3:
+ btc_rate_id = BTC_VHT_4SS_MCS_3;
+ break;
+ case DESC_RATEVHTSS4MCS4:
+ btc_rate_id = BTC_VHT_4SS_MCS_4;
+ break;
+ case DESC_RATEVHTSS4MCS5:
+ btc_rate_id = BTC_VHT_4SS_MCS_5;
+ break;
+ case DESC_RATEVHTSS4MCS6:
+ btc_rate_id = BTC_VHT_4SS_MCS_6;
+ break;
+ case DESC_RATEVHTSS4MCS7:
+ btc_rate_id = BTC_VHT_4SS_MCS_7;
+ break;
+ case DESC_RATEVHTSS4MCS8:
+ btc_rate_id = BTC_VHT_4SS_MCS_8;
+ break;
+ case DESC_RATEVHTSS4MCS9:
+ btc_rate_id = BTC_VHT_4SS_MCS_9;
+ break;
+ }
+
+ return btc_rate_id;
}
static void halbt_init_hw_config92C(PADAPTER padapter)
@@ -3348,7 +4717,7 @@ u8 hal_btcoex_IsBtDisabled(PADAPTER padapter)
if (!hal_btcoex_IsBtExist(padapter))
return _TRUE;
- if (GLBtCoexist.btInfo.bBtDisabled)
+ if (GLBtCoexist.bt_info.bt_disabled)
return _TRUE;
else
return _FALSE;
@@ -3378,10 +4747,6 @@ u8 hal_btcoex_Initialize(PADAPTER padapter)
_rtw_memset(&GLBtCoexist, 0, sizeof(GLBtCoexist));
- hal_btcoex_SetBTCoexist(padapter, rtw_btcoex_get_bt_coexist(padapter));
- hal_btcoex_SetChipType(padapter, rtw_btcoex_get_chip_type(padapter));
- hal_btcoex_SetPgAntNum(padapter, rtw_btcoex_get_pg_ant_num(padapter));
-
ret = EXhalbtcoutsrc_InitlizeVariables((void *)padapter);
return ret;
@@ -3392,6 +4757,23 @@ void hal_btcoex_PowerOnSetting(PADAPTER padapter)
EXhalbtcoutsrc_PowerOnSetting(&GLBtCoexist);
}
+void hal_btcoex_AntInfoSetting(PADAPTER padapter)
+{
+ hal_btcoex_SetBTCoexist(padapter, rtw_btcoex_get_bt_coexist(padapter));
+ hal_btcoex_SetChipType(padapter, rtw_btcoex_get_chip_type(padapter));
+ hal_btcoex_SetPgAntNum(padapter, rtw_btcoex_get_pg_ant_num(padapter));
+
+ EXhalbtcoutsrc_AntInfoSetting(padapter);
+}
+
+void hal_btcoex_PowerOffSetting(PADAPTER padapter)
+{
+ /* Clear the WiFi on/off bit in scoreboard reg. if necessary */
+ if (IS_HARDWARE_TYPE_8703B(padapter) || IS_HARDWARE_TYPE_8723D(padapter)
+ || IS_HARDWARE_TYPE_8821C(padapter) || IS_HARDWARE_TYPE_8822B(padapter))
+ rtw_write16(padapter, 0xaa, 0x8000);
+}
+
void hal_btcoex_PreLoadFirmware(PADAPTER padapter)
{
EXhalbtcoutsrc_PreLoadFirmware(&GLBtCoexist);
@@ -3423,7 +4805,25 @@ void hal_btcoex_ScanNotify(PADAPTER padapter, u8 type)
void hal_btcoex_ConnectNotify(PADAPTER padapter, u8 action)
{
- EXhalbtcoutsrc_connect_notify(&GLBtCoexist, action);
+ u8 assoType = 0;
+ u8 is_5g_band = _FALSE;
+
+ is_5g_band = (padapter->mlmeextpriv.cur_channel > 14) ? _TRUE : _FALSE;
+
+ if (action == _TRUE) {
+ if (is_5g_band == _TRUE)
+ assoType = BTC_ASSOCIATE_5G_START;
+ else
+ assoType = BTC_ASSOCIATE_START;
+ }
+ else {
+ if (is_5g_band == _TRUE)
+ assoType = BTC_ASSOCIATE_5G_FINISH;
+ else
+ assoType = BTC_ASSOCIATE_FINISH;
+ }
+
+ EXhalbtcoutsrc_connect_notify(&GLBtCoexist, assoType);
}
void hal_btcoex_MediaStatusNotify(PADAPTER padapter, u8 mediaStatus)
@@ -3454,7 +4854,7 @@ void hal_btcoex_BtMpRptNotify(PADAPTER padapter, u8 length, u8 *tmpBuf)
u8 extid, status, len, seq;
- if (!GLBtcBtMpRptWait)
+ if (GLBtcBtMpRptWait == _FALSE)
return;
if ((length < 3) || (!tmpBuf))
@@ -3464,48 +4864,66 @@ void hal_btcoex_BtMpRptNotify(PADAPTER padapter, u8 length, u8 *tmpBuf)
/* not response from BT FW then exit*/
switch (extid) {
case C2H_WIFI_FW_ACTIVE_RSP:
- GLBtcBtMpRptWiFiOK = 1;
- return;
+ GLBtcBtMpRptWiFiOK = _TRUE;
+ break;
case C2H_TRIG_BY_BT_FW:
- _cancel_timer_ex(&GLBtcBtMpOperTimer);
- GLBtcBtMpRptWait = 0;
- GLBtcBtMpRptBTOK = 1;
+ GLBtcBtMpRptBTOK = _TRUE;
+
+ status = tmpBuf[1] & 0xF;
+ len = length - 3;
+ seq = tmpBuf[2] >> 4;
+
+ GLBtcBtMpRptSeq = seq;
+ GLBtcBtMpRptStatus = status;
+ _rtw_memcpy(GLBtcBtMpRptRsp, tmpBuf + 3, len);
+ GLBtcBtMpRptRspSize = len;
+
break;
default:
return;
}
- status = tmpBuf[1] & 0xF;
- len = tmpBuf[1] >> 4;
- seq = tmpBuf[2] >> 4;
-
- GLBtcBtMpRptSeq = seq;
- GLBtcBtMpRptStatus = status;
- _rtw_memcpy(GLBtcBtMpRptRsp, tmpBuf + 3, len);
- GLBtcBtMpRptRspSize = len;
- _rtw_up_sema(&GLBtcBtMpRptSema);
+ if ((GLBtcBtMpRptWiFiOK == _TRUE) && (GLBtcBtMpRptBTOK == _TRUE)) {
+ GLBtcBtMpRptWait = _FALSE;
+ _cancel_timer_ex(&GLBtcBtMpOperTimer);
+ _rtw_up_sema(&GLBtcBtMpRptSema);
+ }
}
void hal_btcoex_SuspendNotify(PADAPTER padapter, u8 state)
{
- if (state == 1)
- state = BTC_WIFI_PNP_SLEEP;
- else
- state = BTC_WIFI_PNP_WAKE_UP;
-
- EXhalbtcoutsrc_pnp_notify(&GLBtCoexist, state);
+ switch (state) {
+ case BTCOEX_SUSPEND_STATE_SUSPEND:
+ EXhalbtcoutsrc_pnp_notify(&GLBtCoexist, BTC_WIFI_PNP_SLEEP);
+ break;
+ case BTCOEX_SUSPEND_STATE_SUSPEND_KEEP_ANT:
+ /* should switch to "#if 1" once all ICs' coex. revision are upgraded to support the KEEP_ANT case */
+#if 0
+ EXhalbtcoutsrc_pnp_notify(&GLBtCoexist, BTC_WIFI_PNP_SLEEP_KEEP_ANT);
+#else
+ EXhalbtcoutsrc_pnp_notify(&GLBtCoexist, BTC_WIFI_PNP_SLEEP);
+ EXhalbtcoutsrc_pnp_notify(&GLBtCoexist, BTC_WIFI_PNP_SLEEP_KEEP_ANT);
+#endif
+ break;
+ case BTCOEX_SUSPEND_STATE_RESUME:
+#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
+ /* re-download FW after resume, inform WL FW port number */
+ rtw_hal_set_wifi_port_id_cmd(GLBtCoexist.Adapter);
+#endif
+ EXhalbtcoutsrc_pnp_notify(&GLBtCoexist, BTC_WIFI_PNP_WAKE_UP);
+ break;
+ }
}
-void hal_btcoex_HaltNotify(PADAPTER padapter)
+void hal_btcoex_HaltNotify(PADAPTER padapter, u8 do_halt)
{
- EXhalbtcoutsrc_halt_notify(&GLBtCoexist);
-}
+ if (do_halt == 1)
+ EXhalbtcoutsrc_halt_notify(&GLBtCoexist);
-void hal_btcoex_ScoreBoardStatusNotify(PADAPTER padapter, u8 length, u8 *tmpBuf)
-{
- EXhalbtcoutsrc_ScoreBoardStatusNotify(&GLBtCoexist, tmpBuf, length);
+ GLBtCoexist.bBinded = _FALSE;
+ GLBtCoexist.Adapter = NULL;
}
void hal_btcoex_SwitchBtTRxMask(PADAPTER padapter)
@@ -3515,22 +4933,29 @@ void hal_btcoex_SwitchBtTRxMask(PADAPTER padapter)
void hal_btcoex_Hanlder(PADAPTER padapter)
{
+ u32 bt_patch_ver;
+
EXhalbtcoutsrc_periodical(&GLBtCoexist);
+
+ if (GLBtCoexist.bt_info.bt_get_fw_ver == 0) {
+ GLBtCoexist.btc_get(&GLBtCoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
+ GLBtCoexist.bt_info.bt_get_fw_ver = bt_patch_ver;
+ }
}
s32 hal_btcoex_IsBTCoexRejectAMPDU(PADAPTER padapter)
{
- return (s32)GLBtCoexist.btInfo.bRejectAggPkt;
+ return (s32)GLBtCoexist.bt_info.reject_agg_pkt;
}
s32 hal_btcoex_IsBTCoexCtrlAMPDUSize(PADAPTER padapter)
{
- return (s32)GLBtCoexist.btInfo.bBtCtrlAggBufSize;
+ return (s32)GLBtCoexist.bt_info.bt_ctrl_agg_buf_size;
}
u32 hal_btcoex_GetAMPDUSize(PADAPTER padapter)
{
- return (u32)GLBtCoexist.btInfo.aggBufSize;
+ return (u32)GLBtCoexist.bt_info.agg_buf_size;
}
void hal_btcoex_SetManualControl(PADAPTER padapter, u8 bmanual)
@@ -3557,10 +4982,10 @@ u8 hal_btcoex_IsBtControlLps(PADAPTER padapter)
if (hal_btcoex_IsBtExist(padapter) == _FALSE)
return _FALSE;
- if (GLBtCoexist.btInfo.bBtDisabled)
+ if (GLBtCoexist.bt_info.bt_disabled)
return _FALSE;
- if (GLBtCoexist.btInfo.bBtCtrlLps)
+ if (GLBtCoexist.bt_info.bt_ctrl_lps)
return _TRUE;
return _FALSE;
@@ -3574,10 +4999,10 @@ u8 hal_btcoex_IsLpsOn(PADAPTER padapter)
if (hal_btcoex_IsBtExist(padapter) == _FALSE)
return _FALSE;
- if (GLBtCoexist.btInfo.bBtDisabled)
+ if (GLBtCoexist.bt_info.bt_disabled)
return _FALSE;
- if (GLBtCoexist.btInfo.bBtLpsOn)
+ if (GLBtCoexist.bt_info.bt_lps_on)
return _TRUE;
return _FALSE;
@@ -3585,12 +5010,12 @@ u8 hal_btcoex_IsLpsOn(PADAPTER padapter)
u8 hal_btcoex_RpwmVal(PADAPTER padapter)
{
- return GLBtCoexist.btInfo.rpwmVal;
+ return GLBtCoexist.bt_info.rpwm_val;
}
u8 hal_btcoex_LpsVal(PADAPTER padapter)
{
- return GLBtCoexist.btInfo.lpsVal;
+ return GLBtCoexist.bt_info.lps_val;
}
u32 hal_btcoex_GetRaMask(PADAPTER padapter)
@@ -3598,7 +5023,7 @@ u32 hal_btcoex_GetRaMask(PADAPTER padapter)
if (!hal_btcoex_IsBtExist(padapter))
return 0;
- if (GLBtCoexist.btInfo.bBtDisabled)
+ if (GLBtCoexist.bt_info.bt_disabled)
return 0;
/* Modify by YiWei , suggest by Cosa and Jenyu
@@ -3607,14 +5032,11 @@ u32 hal_btcoex_GetRaMask(PADAPTER padapter)
/*if (GLBtCoexist.board_info.btdm_ant_num != 1)
return 0;*/
- return GLBtCoexist.btInfo.raMask;
+ return GLBtCoexist.bt_info.ra_mask;
}
void hal_btcoex_RecordPwrMode(PADAPTER padapter, u8 *pCmdBuf, u8 cmdLen)
{
- RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], FW write pwrModeCmd=0x%04x%08x\n",
- pCmdBuf[0] << 8 | pCmdBuf[1],
- pCmdBuf[2] << 24 | pCmdBuf[3] << 16 | pCmdBuf[4] << 8 | pCmdBuf[5]));
_rtw_memcpy(GLBtCoexist.pwrModeVal, pCmdBuf, cmdLen);
}
@@ -3775,7 +5197,7 @@ u8 hal_btcoex_IncreaseScanDeviceNum(PADAPTER padapter)
if (!hal_btcoex_IsBtExist(padapter))
return _FALSE;
- if (GLBtCoexist.btInfo.bIncreaseScanDevNum)
+ if (GLBtCoexist.bt_info.increase_scan_dev_num)
return _TRUE;
return _FALSE;
@@ -3804,9 +5226,9 @@ void hal_btcoex_StackUpdateProfileInfo(void)
EXhalbtcoutsrc_StackUpdateProfileInfo();
}
-void hal_btcoex_BTOffOnNotify(PADAPTER padapter, u8 bBTON)
+void hal_btcoex_pta_off_on_notify(PADAPTER padapter, u8 bBTON)
{
- EXhalbtcoutsrc_BTOffOnNotify(&GLBtCoexist, bBTON);
+ ex_halbtcoutsrc_pta_off_on_notify(&GLBtCoexist, bBTON);
}
/*
@@ -3956,9 +5378,7 @@ hal_btcoex_AntIsolationConfig_ParaFile(
_rtw_memset(pHalData->para_file_buf , 0 , MAX_PARA_FILE_BUF_LEN);
-
- rtw_merge_string(rtw_phy_para_file_path, PATH_LENGTH_MAX, rtw_phy_file_path, pFileName);
-
+ rtw_get_phy_file_path(Adapter, pFileName);
if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) {
rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
if (rlen > 0)
@@ -3982,7 +5402,7 @@ u16 hal_btcoex_btreg_read(PADAPTER padapter, u8 type, u16 addr, u32 *data)
halbtcoutsrc_LeaveLowPower(&GLBtCoexist);
- ret = halbtcoutsrc_GetBtReg(&GLBtCoexist, type, addr, data);
+ ret = halbtcoutsrc_GetBtReg_with_status(&GLBtCoexist, type, addr, data);
halbtcoutsrc_NormalLowPower(&GLBtCoexist);
@@ -4006,6 +5426,19 @@ void hal_btcoex_set_rfe_type(u8 type)
{
EXhalbtcoutsrc_set_rfe_type(type);
}
+
+#ifdef CONFIG_RF4CE_COEXIST
+void hal_btcoex_set_rf4ce_link_state(u8 state)
+{
+ EXhalbtcoutsrc_set_rf4ce_link_state(state);
+}
+
+u8 hal_btcoex_get_rf4ce_link_state(void)
+{
+ return EXhalbtcoutsrc_get_rf4ce_link_state();
+}
+#endif /* CONFIG_RF4CE_COEXIST */
+
void hal_btcoex_switchband_notify(u8 under_scan, u8 band_type)
{
switch (band_type) {
@@ -4013,7 +5446,7 @@ void hal_btcoex_switchband_notify(u8 under_scan, u8 band_type)
if (under_scan)
EXhalbtcoutsrc_switchband_notify(&GLBtCoexist, BTC_SWITCH_TO_24G);
else
- EXhalbtcoutsrc_switchband_notify(&GLBtCoexist, BTC_SWITCH_TO_24G_NoForScan);
+ EXhalbtcoutsrc_switchband_notify(&GLBtCoexist, BTC_SWITCH_TO_24G_NOFORSCAN);
break;
case BAND_ON_5G:
EXhalbtcoutsrc_switchband_notify(&GLBtCoexist, BTC_SWITCH_TO_5G);
@@ -4023,4 +5456,14 @@ void hal_btcoex_switchband_notify(u8 under_scan, u8 band_type)
break;
}
}
+
+void hal_btcoex_WlFwDbgInfoNotify(PADAPTER padapter, u8* tmpBuf, u8 length)
+{
+ EXhalbtcoutsrc_WlFwDbgInfoNotify(&GLBtCoexist, tmpBuf, length);
+}
+
+void hal_btcoex_rx_rate_change_notify(PADAPTER padapter, u8 is_data_frame, u8 rate_id)
+{
+ EXhalbtcoutsrc_rx_rate_change_notify(&GLBtCoexist, is_data_frame, EXhalbtcoutsrc_rate_id_to_btc_rate_id(rate_id));
+}
#endif /* CONFIG_BT_COEXIST */
diff --git a/hal/hal_btcoex_wifionly.c b/hal/hal_btcoex_wifionly.c
new file mode 100644
index 0000000..8201513
--- /dev/null
+++ b/hal/hal_btcoex_wifionly.c
@@ -0,0 +1,204 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#include
+
+#if (CONFIG_BTCOEX_SUPPORT_WIFI_ONLY_CFG == 1)
+
+#include "btc/mp_precomp.h"
+
+struct wifi_only_cfg GLBtCoexistWifiOnly;
+
+void halwifionly_write1byte(PVOID pwifionlyContext, u32 RegAddr, u8 Data)
+{
+ struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
+ PADAPTER Adapter = pwifionlycfg->Adapter;
+
+ rtw_write8(Adapter, RegAddr, Data);
+}
+
+void halwifionly_write2byte(PVOID pwifionlyContext, u32 RegAddr, u16 Data)
+{
+ struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
+ PADAPTER Adapter = pwifionlycfg->Adapter;
+
+ rtw_write16(Adapter, RegAddr, Data);
+}
+
+void halwifionly_write4byte(PVOID pwifionlyContext, u32 RegAddr, u32 Data)
+{
+ struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
+ PADAPTER Adapter = pwifionlycfg->Adapter;
+
+ rtw_write32(Adapter, RegAddr, Data);
+}
+
+u8 halwifionly_read1byte(PVOID pwifionlyContext, u32 RegAddr)
+{
+ struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
+ PADAPTER Adapter = pwifionlycfg->Adapter;
+
+ return rtw_read8(Adapter, RegAddr);
+}
+
+u16 halwifionly_read2byte(PVOID pwifionlyContext, u32 RegAddr)
+{
+ struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
+ PADAPTER Adapter = pwifionlycfg->Adapter;
+
+ return rtw_read16(Adapter, RegAddr);
+}
+
+u32 halwifionly_read4byte(PVOID pwifionlyContext, u32 RegAddr)
+{
+ struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
+ PADAPTER Adapter = pwifionlycfg->Adapter;
+
+ return rtw_read32(Adapter, RegAddr);
+}
+
+void halwifionly_bitmaskwrite1byte(PVOID pwifionlyContext, u32 regAddr, u8 bitMask, u8 data)
+{
+ u8 originalValue, bitShift = 0;
+ u8 i;
+
+ struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
+ PADAPTER Adapter = pwifionlycfg->Adapter;
+
+ if (bitMask != 0xff) {
+ originalValue = rtw_read8(Adapter, regAddr);
+ for (i = 0; i <= 7; i++) {
+ if ((bitMask >> i) & 0x1)
+ break;
+ }
+ bitShift = i;
+ data = ((originalValue) & (~bitMask)) | (((data << bitShift)) & bitMask);
+ }
+ rtw_write8(Adapter, regAddr, data);
+}
+
+void halwifionly_phy_set_rf_reg(PVOID pwifionlyContext, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
+{
+ struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
+ PADAPTER Adapter = pwifionlycfg->Adapter;
+
+ phy_set_rf_reg(Adapter, eRFPath, RegAddr, BitMask, Data);
+}
+
+void halwifionly_phy_set_bb_reg(PVOID pwifionlyContext, u32 RegAddr, u32 BitMask, u32 Data)
+{
+ struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext;
+ PADAPTER Adapter = pwifionlycfg->Adapter;
+
+ phy_set_bb_reg(Adapter, RegAddr, BitMask, Data);
+}
+
+void hal_btcoex_wifionly_switchband_notify(PADAPTER padapter)
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+ u8 is_5g = _FALSE;
+
+ if (pHalData->current_band_type == BAND_ON_5G)
+ is_5g = _TRUE;
+
+ if (IS_HARDWARE_TYPE_8822B(padapter)) {
+#ifdef CONFIG_RTL8822B
+ ex_hal8822b_wifi_only_switchbandnotify(&GLBtCoexistWifiOnly, is_5g);
+#endif
+ }
+
+#ifdef CONFIG_RTL8821C
+ else if (IS_HARDWARE_TYPE_8821C(padapter))
+ ex_hal8821c_wifi_only_switchbandnotify(&GLBtCoexistWifiOnly, is_5g);
+#endif
+}
+
+void hal_btcoex_wifionly_scan_notify(PADAPTER padapter)
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+ u8 is_5g = _FALSE;
+
+ if (pHalData->current_band_type == BAND_ON_5G)
+ is_5g = _TRUE;
+
+ if (IS_HARDWARE_TYPE_8822B(padapter)) {
+#ifdef CONFIG_RTL8822B
+ ex_hal8822b_wifi_only_scannotify(&GLBtCoexistWifiOnly, is_5g);
+#endif
+ }
+
+#ifdef CONFIG_RTL8821C
+ else if (IS_HARDWARE_TYPE_8821C(padapter))
+ ex_hal8821c_wifi_only_scannotify(&GLBtCoexistWifiOnly, is_5g);
+#endif
+}
+
+void hal_btcoex_wifionly_hw_config(PADAPTER padapter)
+{
+ struct wifi_only_cfg *pwifionlycfg = &GLBtCoexistWifiOnly;
+
+ if (IS_HARDWARE_TYPE_8723B(padapter)) {
+#ifdef CONFIG_RTL8723B
+ ex_hal8723b_wifi_only_hw_config(pwifionlycfg);
+#endif
+ }
+
+#ifdef CONFIG_RTL8822B
+ else if (IS_HARDWARE_TYPE_8822B(padapter))
+ ex_hal8822b_wifi_only_hw_config(pwifionlycfg);
+#endif
+
+#ifdef CONFIG_RTL8821C
+ else if (IS_HARDWARE_TYPE_8821C(padapter))
+ ex_hal8821c_wifi_only_hw_config(pwifionlycfg);
+#endif
+}
+
+void hal_btcoex_wifionly_initlizevariables(PADAPTER padapter)
+{
+ struct wifi_only_cfg *pwifionlycfg = &GLBtCoexistWifiOnly;
+ struct wifi_only_haldata *pwifionly_haldata = &pwifionlycfg->haldata_info;
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+
+ _rtw_memset(&GLBtCoexistWifiOnly, 0, sizeof(GLBtCoexistWifiOnly));
+
+ pwifionlycfg->Adapter = padapter;
+
+#ifdef CONFIG_PCI_HCI
+ pwifionlycfg->chip_interface = WIFIONLY_INTF_PCI;
+#elif defined(CONFIG_USB_HCI)
+ pwifionlycfg->chip_interface = WIFIONLY_INTF_USB;
+#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+ pwifionlycfg->chip_interface = WIFIONLY_INTF_SDIO;
+#else
+ pwifionlycfg->chip_interface = WIFIONLY_INTF_UNKNOWN;
+#endif
+
+ pwifionly_haldata->customer_id = CUSTOMER_NORMAL;
+}
+
+void hal_btcoex_wifionly_AntInfoSetting(PADAPTER padapter)
+{
+ struct wifi_only_cfg *pwifionlycfg = &GLBtCoexistWifiOnly;
+ struct wifi_only_haldata *pwifionly_haldata = &pwifionlycfg->haldata_info;
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+
+ pwifionly_haldata->efuse_pg_antnum = pHalData->EEPROMBluetoothAntNum;
+ pwifionly_haldata->efuse_pg_antpath = pHalData->ant_path;
+ pwifionly_haldata->rfe_type = pHalData->rfe_type;
+ pwifionly_haldata->ant_div_cfg = pHalData->AntDivCfg;
+}
+
+#endif
+
diff --git a/hal/hal_com.c b/hal/hal_com.c
index 225804d..c3376b0 100644
--- a/hal/hal_com.c
+++ b/hal/hal_com.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,12 +11,7 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#define _HAL_COM_C_
#include
@@ -24,6 +19,24 @@
#include "hal_data.h"
+#ifdef RTW_HALMAC
+#include "../../hal/hal_halmac.h"
+#endif
+
+void rtw_dump_fw_info(void *sel, _adapter *adapter)
+{
+ HAL_DATA_TYPE *hal_data = NULL;
+
+ if (!adapter)
+ return;
+
+ hal_data = GET_HAL_DATA(adapter);
+ if (hal_data->bFWReady)
+ RTW_PRINT_SEL(sel, "FW VER -%d.%d\n", hal_data->firmware_version, hal_data->firmware_sub_version);
+ else
+ RTW_PRINT_SEL(sel, "FW not ready\n");
+}
+
/* #define CONFIG_GTK_OL_DBG */
/*#define DBG_SEC_CAM_MOVE*/
@@ -34,7 +47,7 @@ void rtw_hal_move_sta_gk_to_dk(_adapter *adapter)
int cam_id, index = 0;
u8 *addr = NULL;
- if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
+ if (!MLME_IS_STA(adapter))
return;
addr = get_bssid(pmlmepriv);
@@ -174,19 +187,19 @@ void rtw_hal_config_rftype(PADAPTER padapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
- if (IS_1T1R(pHalData->VersionID)) {
+ if (IS_1T1R(pHalData->version_id)) {
pHalData->rf_type = RF_1T1R;
pHalData->NumTotalRFPath = 1;
- } else if (IS_2T2R(pHalData->VersionID)) {
+ } else if (IS_2T2R(pHalData->version_id)) {
pHalData->rf_type = RF_2T2R;
pHalData->NumTotalRFPath = 2;
- } else if (IS_1T2R(pHalData->VersionID)) {
+ } else if (IS_1T2R(pHalData->version_id)) {
pHalData->rf_type = RF_1T2R;
pHalData->NumTotalRFPath = 2;
- } else if (IS_3T3R(pHalData->VersionID)) {
+ } else if (IS_3T3R(pHalData->version_id)) {
pHalData->rf_type = RF_3T3R;
pHalData->NumTotalRFPath = 3;
- } else if (IS_4T4R(pHalData->VersionID)) {
+ } else if (IS_4T4R(pHalData->version_id)) {
pHalData->rf_type = RF_4T4R;
pHalData->NumTotalRFPath = 4;
} else {
@@ -215,11 +228,8 @@ void rtw_hal_config_rftype(PADAPTER padapter)
* def_chplan channel plan used when HW/SW both invalid
* AutoLoadFail efuse autoload fail or not
*
- * Return:
- * Final channel plan decision
- *
*/
-u8 hal_com_config_channel_plan(
+void hal_com_config_channel_plan(
IN PADAPTER padapter,
IN char *hw_alpha2,
IN u8 hw_chplan,
@@ -229,6 +239,7 @@ u8 hal_com_config_channel_plan(
IN BOOLEAN AutoLoadFail
)
{
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter);
PHAL_DATA_TYPE pHalData;
u8 force_hw_chplan = _FALSE;
int chplan = -1;
@@ -289,7 +300,7 @@ u8 hal_com_config_channel_plan(
/* cancel hw_alpha2 because chplan is specified by sw_chplan*/
country_ent = NULL;
chplan = sw_chplan;
- } else if (sw_chplan != RTW_CHPLAN_MAX)
+ } else if (sw_chplan != RTW_CHPLAN_UNSPECIFIED)
RTW_PRINT("%s unsupported sw_chplan:0x%02X\n", __func__, sw_chplan);
done:
@@ -302,10 +313,9 @@ u8 hal_com_config_channel_plan(
} else
RTW_PRINT("%s chplan:0x%02X\n", __func__, chplan);
- padapter->mlmepriv.country_ent = country_ent;
+ rfctl->country_ent = country_ent;
+ rfctl->ChannelPlan = chplan;
pHalData->bDisableSWChannelPlan = force_hw_chplan;
-
- return chplan;
}
BOOLEAN
@@ -317,7 +327,7 @@ HAL_IsLegalChannel(
BOOLEAN bLegalChannel = _TRUE;
if (Channel > 14) {
- if (IsSupported5G(Adapter->registrypriv.wireless_mode) == _FALSE) {
+ if (is_supported_5g(Adapter->registrypriv.wireless_mode) == _FALSE) {
bLegalChannel = _FALSE;
RTW_INFO("Channel > 14 but wireless_mode do not support 5G\n");
}
@@ -600,7 +610,7 @@ u8 MRateToHwRate(u8 rate)
return ret;
}
-u8 HwRateToMRate(u8 rate)
+u8 hw_rate_to_m_rate(u8 rate)
{
u8 ret_rate = MGN_1M;
@@ -860,7 +870,7 @@ u8 HwRateToMRate(u8 rate)
break;
default:
- RTW_INFO("HwRateToMRate(): Non supported Rate [%x]!!!\n", rate);
+ RTW_INFO("hw_rate_to_m_rate(): Non supported Rate [%x]!!!\n", rate);
break;
}
@@ -1100,6 +1110,12 @@ Hal_MappingOutPipe(
}
+void rtw_hal_reqtxrpt(_adapter *padapter, u8 macid)
+{
+ if (padapter->hal_func.reqtxrpt)
+ padapter->hal_func.reqtxrpt(padapter, macid);
+}
+
void rtw_hal_dump_macaddr(void *sel, _adapter *adapter)
{
int i;
@@ -1113,7 +1129,7 @@ void rtw_hal_dump_macaddr(void *sel, _adapter *adapter)
for (i = 0; i < dvobj->iface_nums; i++) {
iface = dvobj->padapters[i];
if (iface) {
- rtw_hal_get_macaddr_port(iface, mac_addr);
+ rtw_hal_get_hwreg(iface, HW_VAR_MAC_ADDR, mac_addr);
RTW_PRINT_SEL(sel, ADPT_FMT"- hw port(%d) mac_addr ="MAC_FMT"\n",
ADPT_ARG(iface), iface->hw_port, MAC_ARG(mac_addr));
}
@@ -1121,12 +1137,58 @@ void rtw_hal_dump_macaddr(void *sel, _adapter *adapter)
#endif
}
-void rtw_restore_mac_addr(_adapter *adapter)
+#ifdef RTW_HALMAC
+void rtw_hal_hw_port_enable(_adapter *adapter)
+{
+#if 1
+ u8 port_enable = _TRUE;
+
+ rtw_hal_set_hwreg(adapter, HW_VAR_PORT_CFG, &port_enable);
+#else
+ struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+ struct rtw_halmac_bcn_ctrl bcn_ctrl;
+
+ _rtw_memset(&bcn_ctrl, 0, sizeof(struct rtw_halmac_bcn_ctrl));
+ bcn_ctrl.enable_bcn = 1;
+ bcn_ctrl.rx_bssid_fit = 1;
+ bcn_ctrl.rxbcn_rpt = 1;
+
+ /*rtw_halmac_get_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport,
+ struct rtw_halmac_bcn_ctrl *bcn_ctrl)*/
+ if (rtw_halmac_set_bcn_ctrl(dvobj, get_hw_port(adapter), &bcn_ctrl) == -1) {
+ RTW_ERR(ADPT_FMT" - hw port(%d) enable fail!!\n", ADPT_ARG(adapter), get_hw_port(adapter));
+ rtw_warn_on(1);
+ }
+#endif
+}
+void rtw_hal_hw_port_disable(_adapter *adapter)
+{
+ u8 port_enable = _FALSE;
+
+ rtw_hal_set_hwreg(adapter, HW_VAR_PORT_CFG, &port_enable);
+}
+
+void rtw_restore_hw_port_cfg(_adapter *adapter)
{
#ifdef CONFIG_MI_WITH_MBSSID_CAM
+
+#else
+ int i;
_adapter *iface;
struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+ for (i = 0; i < dvobj->iface_nums; i++) {
+ iface = dvobj->padapters[i];
+ if (iface)
+ rtw_hal_hw_port_enable(iface);
+ }
+#endif
+}
+#endif
+
+void rtw_restore_mac_addr(_adapter *adapter)
+{
+#ifdef CONFIG_MI_WITH_MBSSID_CAM
rtw_mbid_cam_restore(adapter);
#else
int i;
@@ -1136,7 +1198,7 @@ void rtw_restore_mac_addr(_adapter *adapter)
for (i = 0; i < dvobj->iface_nums; i++) {
iface = dvobj->padapters[i];
if (iface)
- rtw_hal_set_macaddr_port(iface, adapter_mac_addr(iface));
+ rtw_hal_set_hwreg(iface, HW_VAR_MAC_ADDR, adapter_mac_addr(iface));
}
#endif
if (1)
@@ -1149,32 +1211,26 @@ void rtw_init_hal_com_default_value(PADAPTER Adapter)
struct registry_priv *regsty = adapter_to_regsty(Adapter);
pHalData->AntDetection = 1;
- pHalData->u1ForcedIgiLb = regsty->force_igi_lb;
+ pHalData->antenna_test = _FALSE;
+ pHalData->RegIQKFWOffload = regsty->iqk_fw_offload;
+ pHalData->ch_switch_offload = regsty->ch_switch_offload;
}
-/*
-* C2H event format:
-* Field TRIGGER CONTENT CMD_SEQ CMD_LEN CMD_ID
-* BITS [127:120] [119:16] [15:8] [7:4] [3:0]
-*/
-
+#ifdef CONFIG_FW_C2H_REG
void c2h_evt_clear(_adapter *adapter)
{
rtw_write8(adapter, REG_C2HEVT_CLEAR, C2H_EVT_HOST_CLOSE);
}
-s32 c2h_evt_read(_adapter *adapter, u8 *buf)
+s32 c2h_evt_read_88xx(_adapter *adapter, u8 *buf)
{
s32 ret = _FAIL;
- struct c2h_evt_hdr *c2h_evt;
int i;
u8 trigger;
if (buf == NULL)
goto exit;
-#if defined(CONFIG_RTL8188E)
-
trigger = rtw_read8(adapter, REG_C2HEVT_CLEAR);
if (trigger == C2H_EVT_HOST_CLOSE) {
@@ -1183,27 +1239,23 @@ s32 c2h_evt_read(_adapter *adapter, u8 *buf)
goto clear_evt; /* Not a valid value */
}
- c2h_evt = (struct c2h_evt_hdr *)buf;
+ _rtw_memset(buf, 0, C2H_REG_LEN);
- _rtw_memset(c2h_evt, 0, 16);
-
- *buf = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL);
- *(buf + 1) = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 1);
-
- RTW_DBG_DUMP("c2h_evt_read(): ",
- &c2h_evt , sizeof(c2h_evt));
+ /* Read ID, LEN, SEQ */
+ SET_C2H_ID_88XX(buf, rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL));
+ SET_C2H_SEQ_88XX(buf, rtw_read8(adapter, REG_C2HEVT_CMD_SEQ_88XX));
+ SET_C2H_PLEN_88XX(buf, rtw_read8(adapter, REG_C2HEVT_CMD_LEN_88XX));
if (0) {
- RTW_INFO("%s id:%u, len:%u, seq:%u, trigger:0x%02x\n", __func__
- , c2h_evt->id, c2h_evt->plen, c2h_evt->seq, trigger);
+ RTW_INFO("%s id=0x%02x, seq=%u, plen=%u, trigger=0x%02x\n", __func__
+ , C2H_ID_88XX(buf), C2H_SEQ_88XX(buf), C2H_PLEN_88XX(buf), trigger);
}
/* Read the content */
- for (i = 0; i < c2h_evt->plen; i++)
- c2h_evt->payload[i] = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 2 + i);
+ for (i = 0; i < C2H_PLEN_88XX(buf); i++)
+ *(C2H_PAYLOAD_88XX(buf) + i) = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 2 + i);
- RTW_DBG_DUMP("c2h_evt_read(): Command Content:\n",
- c2h_evt->payload, c2h_evt->plen);
+ RTW_DBG_DUMP("payload: ", C2H_PAYLOAD_88XX(buf), C2H_PLEN_88XX(buf));
ret = _SUCCESS;
@@ -1213,72 +1265,118 @@ s32 c2h_evt_read(_adapter *adapter, u8 *buf)
* If this field isn't clear, the FW won't update the next command message.
*/
c2h_evt_clear(adapter);
-#endif
+
exit:
return ret;
}
+#endif /* CONFIG_FW_C2H_REG */
-/*
-* C2H event format:
-* Field TRIGGER CMD_LEN CONTENT CMD_SEQ CMD_ID
-* BITS [127:120] [119:112] [111:16] [15:8] [7:0]
-*/
-s32 c2h_evt_read_88xx(_adapter *adapter, u8 *buf)
+#ifdef CONFIG_FW_C2H_PKT
+#ifndef DBG_C2H_PKT_PRE_HDL
+#define DBG_C2H_PKT_PRE_HDL 0
+#endif
+#ifndef DBG_C2H_PKT_HDL
+#define DBG_C2H_PKT_HDL 0
+#endif
+void rtw_hal_c2h_pkt_pre_hdl(_adapter *adapter, u8 *buf, u16 len)
{
+#ifdef RTW_HALMAC
+ /* TODO: extract hal_mac IC's code here*/
+#else
+ u8 parse_fail = 0;
+ u8 hdl_here = 0;
s32 ret = _FAIL;
- struct c2h_evt_hdr_88xx *c2h_evt;
- int i;
- u8 trigger;
+ u8 id, seq, plen;
+ u8 *payload;
- if (buf == NULL)
+ if (rtw_hal_c2h_pkt_hdr_parse(adapter, buf, len, &id, &seq, &plen, &payload) != _SUCCESS) {
+ parse_fail = 1;
goto exit;
+ }
-#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) \
- || defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8723B) \
- || defined(CONFIG_RTL8703B) || defined(CONFIG_RTL8723D)
-
- trigger = rtw_read8(adapter, REG_C2HEVT_CLEAR);
+ hdl_here = rtw_hal_c2h_id_handle_directly(adapter, id, seq, plen, payload) == _TRUE ? 1 : 0;
+ if (hdl_here)
+ ret = rtw_hal_c2h_handler(adapter, id, seq, plen, payload);
+ else
+ ret = rtw_c2h_packet_wk_cmd(adapter, buf, len);
- if (trigger == C2H_EVT_HOST_CLOSE) {
- goto exit; /* Not ready */
- } else if (trigger != C2H_EVT_FW_CLOSE) {
- goto clear_evt; /* Not a valid value */
+exit:
+ if (parse_fail)
+ RTW_ERR("%s parse fail, buf=%p, len=:%u\n", __func__, buf, len);
+ else if (ret != _SUCCESS || DBG_C2H_PKT_PRE_HDL > 0) {
+ RTW_PRINT("%s: id=0x%02x, seq=%u, plen=%u, %s %s\n", __func__, id, seq, plen
+ , hdl_here ? "handle" : "enqueue"
+ , ret == _SUCCESS ? "ok" : "fail"
+ );
+ if (DBG_C2H_PKT_PRE_HDL >= 2)
+ RTW_PRINT_DUMP("dump: ", buf, len);
}
+#endif
+}
- c2h_evt = (struct c2h_evt_hdr_88xx *)buf;
+void rtw_hal_c2h_pkt_hdl(_adapter *adapter, u8 *buf, u16 len)
+{
+#ifdef RTW_HALMAC
+ adapter->hal_func.hal_mac_c2h_handler(adapter, buf, len);
+#else
+ u8 parse_fail = 0;
+ u8 bypass = 0;
+ s32 ret = _FAIL;
+ u8 id, seq, plen;
+ u8 *payload;
- _rtw_memset(c2h_evt, 0, 16);
+ if (rtw_hal_c2h_pkt_hdr_parse(adapter, buf, len, &id, &seq, &plen, &payload) != _SUCCESS) {
+ parse_fail = 1;
+ goto exit;
+ }
- c2h_evt->id = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL);
- c2h_evt->seq = rtw_read8(adapter, REG_C2HEVT_CMD_SEQ_88XX);
- c2h_evt->plen = rtw_read8(adapter, REG_C2HEVT_CMD_LEN_88XX);
+#ifdef CONFIG_WOWLAN
+ if (adapter_to_pwrctl(adapter)->wowlan_mode == _TRUE) {
+ bypass = 1;
+ ret = _SUCCESS;
+ goto exit;
+ }
+#endif
- RTW_DBG_DUMP("c2h_evt_read(): ",
- &c2h_evt , sizeof(c2h_evt));
+ ret = rtw_hal_c2h_handler(adapter, id, seq, plen, payload);
- if (0) {
- RTW_INFO("%s id:%u, len:%u, seq:%u, trigger:0x%02x\n", __func__
- , c2h_evt->id, c2h_evt->plen, c2h_evt->seq, trigger);
+exit:
+ if (parse_fail)
+ RTW_ERR("%s parse fail, buf=%p, len=:%u\n", __func__, buf, len);
+ else if (ret != _SUCCESS || bypass || DBG_C2H_PKT_HDL > 0) {
+ RTW_PRINT("%s: id=0x%02x, seq=%u, plen=%u, %s %s\n", __func__, id, seq, plen
+ , !bypass ? "handle" : "bypass"
+ , ret == _SUCCESS ? "ok" : "fail"
+ );
+ if (DBG_C2H_PKT_HDL >= 2)
+ RTW_PRINT_DUMP("dump: ", buf, len);
}
+#endif
+}
+#endif /* CONFIG_FW_C2H_PKT */
- /* Read the content */
- for (i = 0; i < c2h_evt->plen; i++)
- c2h_evt->payload[i] = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 2 + i);
+void c2h_iqk_offload(_adapter *adapter, u8 *data, u8 len)
+{
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+ struct submit_ctx *iqk_sctx = &hal_data->iqk_sctx;
- RTW_DBG_DUMP("c2h_evt_read(): Command Content:\n",
- c2h_evt->payload, c2h_evt->plen);
+ RTW_INFO("IQK offload finish in %dms\n", rtw_get_passing_time_ms(iqk_sctx->submit_time));
+ if (0)
+ RTW_INFO_DUMP("C2H_IQK_FINISH: ", data, len);
- ret = _SUCCESS;
+ rtw_sctx_done(&iqk_sctx);
+}
-clear_evt:
- /*
- * Clear event to notify FW we have read the command.
- * If this field isn't clear, the FW won't update the next command message.
- */
- c2h_evt_clear(adapter);
-#endif
-exit:
- return ret;
+int c2h_iqk_offload_wait(_adapter *adapter, u32 timeout_ms)
+{
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+ struct submit_ctx *iqk_sctx = &hal_data->iqk_sctx;
+
+ iqk_sctx->submit_time = rtw_get_current_time();
+ iqk_sctx->timeout_ms = timeout_ms;
+ iqk_sctx->status = RTW_SCTX_SUBMITTED;
+
+ return rtw_sctx_wait(iqk_sctx, __func__);
}
#define GET_C2H_MAC_HIDDEN_RPT_UUID_X(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 0, 0, 8)
@@ -1286,7 +1384,8 @@ s32 c2h_evt_read_88xx(_adapter *adapter, u8 *buf)
#define GET_C2H_MAC_HIDDEN_RPT_UUID_Z(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 2, 0, 5)
#define GET_C2H_MAC_HIDDEN_RPT_UUID_CRC(_data) LE_BITS_TO_2BYTE(((u8 *)(_data)) + 2, 5, 11)
#define GET_C2H_MAC_HIDDEN_RPT_HCI_TYPE(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 4, 0, 4)
-#define GET_C2H_MAC_HIDDEN_RPT_PACKAGE_TYPE(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 4, 4, 4)
+#define GET_C2H_MAC_HIDDEN_RPT_PACKAGE_TYPE(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 4, 4, 3)
+#define GET_C2H_MAC_HIDDEN_RPT_TR_SWITCH(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 4, 7, 1)
#define GET_C2H_MAC_HIDDEN_RPT_WL_FUNC(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 5, 0, 4)
#define GET_C2H_MAC_HIDDEN_RPT_HW_STYPE(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 5, 4, 4)
#define GET_C2H_MAC_HIDDEN_RPT_BW(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 6, 0, 3)
@@ -1295,9 +1394,10 @@ s32 c2h_evt_read_88xx(_adapter *adapter, u8 *buf)
#define GET_C2H_MAC_HIDDEN_RPT_NIC_ROUTER(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 7, 6, 2)
#ifndef DBG_C2H_MAC_HIDDEN_RPT_HANDLE
- #define DBG_C2H_MAC_HIDDEN_RPT_HANDLE 0
+#define DBG_C2H_MAC_HIDDEN_RPT_HANDLE 0
#endif
+#ifdef CONFIG_RTW_MAC_HIDDEN_RPT
int c2h_mac_hidden_rpt_hdl(_adapter *adapter, u8 *data, u8 len)
{
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
@@ -1312,6 +1412,7 @@ int c2h_mac_hidden_rpt_hdl(_adapter *adapter, u8 *data, u8 len)
u8 hci_type;
u8 package_type;
+ u8 tr_switch;
u8 wl_func;
u8 hw_stype;
u8 bw;
@@ -1334,6 +1435,8 @@ int c2h_mac_hidden_rpt_hdl(_adapter *adapter, u8 *data, u8 len)
hci_type = GET_C2H_MAC_HIDDEN_RPT_HCI_TYPE(data);
package_type = GET_C2H_MAC_HIDDEN_RPT_PACKAGE_TYPE(data);
+ tr_switch = GET_C2H_MAC_HIDDEN_RPT_TR_SWITCH(data);
+
wl_func = GET_C2H_MAC_HIDDEN_RPT_WL_FUNC(data);
hw_stype = GET_C2H_MAC_HIDDEN_RPT_HW_STYPE(data);
@@ -1345,24 +1448,72 @@ int c2h_mac_hidden_rpt_hdl(_adapter *adapter, u8 *data, u8 len)
if (DBG_C2H_MAC_HIDDEN_RPT_HANDLE) {
for (i = 0; i < len; i++)
- RTW_INFO("%s: 0x%02X\n", __func__, *(data + i));
+ RTW_PRINT("%s: 0x%02X\n", __func__, *(data + i));
- RTW_INFO("uuid x:0x%02x y:0x%02x z:0x%x crc:0x%x\n", uuid_x, uuid_y, uuid_z, uuid_crc);
- RTW_INFO("hci_type:0x%x\n", hci_type);
- RTW_INFO("package_type:0x%x\n", package_type);
- RTW_INFO("wl_func:0x%x\n", wl_func);
- RTW_INFO("hw_stype:0x%x\n", hw_stype);
- RTW_INFO("bw:0x%x\n", bw);
- RTW_INFO("ant_num:0x%x\n", ant_num);
- RTW_INFO("protocol:0x%x\n", protocol);
- RTW_INFO("nic:0x%x\n", nic);
+ RTW_PRINT("uuid x:0x%02x y:0x%02x z:0x%x crc:0x%x\n", uuid_x, uuid_y, uuid_z, uuid_crc);
+ RTW_PRINT("hci_type:0x%x\n", hci_type);
+ RTW_PRINT("package_type:0x%x\n", package_type);
+ RTW_PRINT("tr_switch:0x%x\n", tr_switch);
+ RTW_PRINT("wl_func:0x%x\n", wl_func);
+ RTW_PRINT("hw_stype:0x%x\n", hw_stype);
+ RTW_PRINT("bw:0x%x\n", bw);
+ RTW_PRINT("ant_num:0x%x\n", ant_num);
+ RTW_PRINT("protocol:0x%x\n", protocol);
+ RTW_PRINT("nic:0x%x\n", nic);
}
+ /*
+ * NOTICE:
+ * for now, the following is common info/format
+ * if there is any hal difference need to export
+ * some IC dependent code will need to be implement
+ */
hal_data->PackageType = package_type;
hal_spec->wl_func &= mac_hidden_wl_func_to_hal_wl_func(wl_func);
hal_spec->bw_cap &= mac_hidden_max_bw_to_hal_bw_cap(bw);
- hal_spec->nss_num = rtw_min(hal_spec->nss_num, ant_num);
+ hal_spec->tx_nss_num = rtw_min(hal_spec->tx_nss_num, ant_num);
+ hal_spec->rx_nss_num = rtw_min(hal_spec->rx_nss_num, ant_num);
hal_spec->proto_cap &= mac_hidden_proto_to_hal_proto_cap(protocol);
+ hal_spec->hci_type = hci_type;
+
+ /* TODO: tr_switch */
+
+ ret = _SUCCESS;
+
+exit:
+ return ret;
+}
+
+int c2h_mac_hidden_rpt_2_hdl(_adapter *adapter, u8 *data, u8 len)
+{
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+ struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+ int ret = _FAIL;
+
+ int i;
+
+ if (len < MAC_HIDDEN_RPT_2_LEN) {
+ RTW_WARN("%s len(%u) < %d\n", __func__, len, MAC_HIDDEN_RPT_2_LEN);
+ goto exit;
+ }
+
+ if (DBG_C2H_MAC_HIDDEN_RPT_HANDLE) {
+ for (i = 0; i < len; i++)
+ RTW_PRINT("%s: 0x%02X\n", __func__, *(data + i));
+ }
+
+ #ifdef CONFIG_RTL8188F
+ if (IS_8188F(hal_data->version_id)) {
+ #define GET_C2H_MAC_HIDDEN_RPT_IRV(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 0, 0, 4)
+ u8 irv = GET_C2H_MAC_HIDDEN_RPT_IRV(data);
+
+ if (DBG_C2H_MAC_HIDDEN_RPT_HANDLE)
+ RTW_PRINT("irv:0x%x\n", irv);
+
+ if(irv != 0xf)
+ hal_data->version_id.CUTVersion = irv;
+ }
+ #endif
ret = _SUCCESS;
@@ -1372,29 +1523,32 @@ int c2h_mac_hidden_rpt_hdl(_adapter *adapter, u8 *data, u8 len)
int hal_read_mac_hidden_rpt(_adapter *adapter)
{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
int ret = _FAIL;
int ret_fwdl;
- u8 mac_hidden_rpt[MAC_HIDDEN_RPT_LEN] = {0};
- u32 start = rtw_get_current_time();
+ u8 mac_hidden_rpt[MAC_HIDDEN_RPT_LEN + MAC_HIDDEN_RPT_2_LEN] = {0};
+ systime start = rtw_get_current_time();
u32 cnt = 0;
u32 timeout_ms = 800;
u32 min_cnt = 10;
- u8 id = C2H_MAC_HIDDEN_RPT + 1;
+ u8 id = C2H_DEFEATURE_RSVD;
int i;
#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
u8 hci_type = rtw_get_intf_type(adapter);
if ((hci_type == RTW_USB || hci_type == RTW_PCIE)
- && !rtw_is_hw_init_completed(adapter))
+ && !rtw_is_hw_init_completed(adapter))
rtw_hal_power_on(adapter);
#endif
- /* clear data ready */
- rtw_write8(adapter, REG_C2HEVT_MSG_NORMAL, id);
+ /* inform FW mac hidden rpt from reg is needed */
+ rtw_write8(adapter, REG_C2HEVT_MSG_NORMAL, C2H_DEFEATURE_RSVD);
/* download FW */
+ pHalData->not_xmitframe_fw_dl = 1;
ret_fwdl = rtw_hal_fw_dl(adapter, _FALSE);
+ pHalData->not_xmitframe_fw_dl = 0;
if (ret_fwdl != _SUCCESS)
goto mac_hidden_rpt_hdl;
@@ -1410,12 +1564,16 @@ int hal_read_mac_hidden_rpt(_adapter *adapter)
if (id == C2H_MAC_HIDDEN_RPT) {
/* read data */
- for (i = 0; i < MAC_HIDDEN_RPT_LEN; i++)
+ for (i = 0; i < MAC_HIDDEN_RPT_LEN + MAC_HIDDEN_RPT_2_LEN; i++)
mac_hidden_rpt[i] = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 2 + i);
}
+ /* inform FW mac hidden rpt has read */
+ rtw_write8(adapter, REG_C2HEVT_MSG_NORMAL, C2H_DBG);
+
mac_hidden_rpt_hdl:
c2h_mac_hidden_rpt_hdl(adapter, mac_hidden_rpt, MAC_HIDDEN_RPT_LEN);
+ c2h_mac_hidden_rpt_2_hdl(adapter, mac_hidden_rpt + MAC_HIDDEN_RPT_LEN, MAC_HIDDEN_RPT_2_LEN);
if (ret_fwdl == _SUCCESS && id == C2H_MAC_HIDDEN_RPT)
ret = _SUCCESS;
@@ -1424,7 +1582,7 @@ int hal_read_mac_hidden_rpt(_adapter *adapter)
#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
if ((hci_type == RTW_USB || hci_type == RTW_PCIE)
- && !rtw_is_hw_init_completed(adapter))
+ && !rtw_is_hw_init_completed(adapter))
rtw_hal_power_off(adapter);
#endif
@@ -1433,148 +1591,563 @@ int hal_read_mac_hidden_rpt(_adapter *adapter)
return ret;
}
+#endif /* CONFIG_RTW_MAC_HIDDEN_RPT */
-u8 rtw_hal_networktype_to_raid(_adapter *adapter, struct sta_info *psta)
-{
- if (IS_NEW_GENERATION_IC(adapter))
- return networktype_to_raid_ex(adapter, psta);
- else
- return networktype_to_raid(adapter, psta);
-
-}
-u8 rtw_get_mgntframe_raid(_adapter *adapter, unsigned char network_type)
+int c2h_defeature_dbg_hdl(_adapter *adapter, u8 *data, u8 len)
{
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+ struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+ int ret = _FAIL;
- u8 raid;
- if (IS_NEW_GENERATION_IC(adapter)) {
+ int i;
- raid = (network_type & WIRELESS_11B) ? RATEID_IDX_B
- : RATEID_IDX_G;
- } else {
- raid = (network_type & WIRELESS_11B) ? RATR_INX_WIRELESS_B
- : RATR_INX_WIRELESS_G;
+ if (len < DEFEATURE_DBG_LEN) {
+ RTW_WARN("%s len(%u) < %d\n", __func__, len, DEFEATURE_DBG_LEN);
+ goto exit;
}
- return raid;
-}
-void rtw_hal_update_sta_rate_mask(PADAPTER padapter, struct sta_info *psta)
-{
- u8 i, rf_type, limit;
- u64 tx_ra_bitmap;
+ for (i = 0; i < len; i++)
+ RTW_PRINT("%s: 0x%02X\n", __func__, *(data + i));
- if (psta == NULL)
- return;
+ ret = _SUCCESS;
+
+exit:
+ return ret;
+}
- tx_ra_bitmap = 0;
+#ifndef DBG_CUSTOMER_STR_RPT_HANDLE
+#define DBG_CUSTOMER_STR_RPT_HANDLE 0
+#endif
- /* b/g mode ra_bitmap */
- for (i = 0; i < sizeof(psta->bssrateset); i++) {
- if (psta->bssrateset[i])
- tx_ra_bitmap |= rtw_get_bit_value_from_ieee_value(psta->bssrateset[i] & 0x7f);
- }
+#ifdef CONFIG_RTW_CUSTOMER_STR
+s32 rtw_hal_h2c_customer_str_req(_adapter *adapter)
+{
+ u8 h2c_data[H2C_CUSTOMER_STR_REQ_LEN] = {0};
-#ifdef CONFIG_80211N_HT
-#ifdef CONFIG_80211AC_VHT
- /* AC mode ra_bitmap */
- if (psta->vhtpriv.vht_option)
- tx_ra_bitmap |= (rtw_vht_rate_to_bitmap(psta->vhtpriv.vht_mcs_map) << 12);
- else
-#endif /* CONFIG_80211AC_VHT */
- {
- /* n mode ra_bitmap */
- if (psta->htpriv.ht_option) {
- rf_type = RF_1T1R;
- rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
- if (rf_type == RF_2T2R)
- limit = 16; /* 2R */
- else if (rf_type == RF_3T3R)
- limit = 24; /* 3R */
- else
- limit = 8; /* 1R */
+ SET_H2CCMD_CUSTOMER_STR_REQ_EN(h2c_data, 1);
+ return rtw_hal_fill_h2c_cmd(adapter, H2C_CUSTOMER_STR_REQ, H2C_CUSTOMER_STR_REQ_LEN, h2c_data);
+}
+#define C2H_CUSTOMER_STR_RPT_BYTE0(_data) ((u8 *)(_data))
+#define C2H_CUSTOMER_STR_RPT_2_BYTE8(_data) ((u8 *)(_data))
- /* Handling SMPS mode for AP MODE only*/
- if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) {
- /*0:static SMPS, 1:dynamic SMPS, 3:SMPS disabled, 2:reserved*/
- if (psta->htpriv.smps_cap == 0 || psta->htpriv.smps_cap == 1) {
- /*operate with only one active receive chain // 11n-MCS rate <= MSC7*/
- limit = 8;/* 1R*/
- }
- }
+int c2h_customer_str_rpt_hdl(_adapter *adapter, u8 *data, u8 len)
+{
+ struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+ int ret = _FAIL;
+ int i;
- for (i = 0; i < limit; i++) {
- if (psta->htpriv.ht_cap.supp_mcs_set[i / 8] & BIT(i % 8))
- tx_ra_bitmap |= BIT(i + 12);
- }
- }
+ if (len < CUSTOMER_STR_RPT_LEN) {
+ RTW_WARN("%s len(%u) < %d\n", __func__, len, CUSTOMER_STR_RPT_LEN);
+ goto exit;
}
-#endif /* CONFIG_80211N_HT */
- RTW_INFO("supp_mcs_set = %02x, %02x, %02x, rf_type=%d, tx_ra_bitmap=%016llx\n"
- , psta->htpriv.ht_cap.supp_mcs_set[0], psta->htpriv.ht_cap.supp_mcs_set[1], psta->htpriv.ht_cap.supp_mcs_set[2], rf_type, tx_ra_bitmap);
- psta->ra_mask = tx_ra_bitmap;
- psta->init_rate = get_highest_rate_idx(tx_ra_bitmap) & 0x3f;
-}
-#ifndef SEC_CAM_ACCESS_TIMEOUT_MS
- #define SEC_CAM_ACCESS_TIMEOUT_MS 200
-#endif
+ if (DBG_CUSTOMER_STR_RPT_HANDLE)
+ RTW_PRINT_DUMP("customer_str_rpt: ", data, CUSTOMER_STR_RPT_LEN);
-#ifndef DBG_SEC_CAM_ACCESS
- #define DBG_SEC_CAM_ACCESS 0
-#endif
+ _enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
-u32 rtw_sec_read_cam(_adapter *adapter, u8 addr)
-{
- _mutex *mutex = &adapter_to_dvobj(adapter)->cam_ctl.sec_cam_access_mutex;
- u32 rdata;
- u32 cnt = 0;
- u32 start = 0, end = 0;
- u8 timeout = 0;
- u8 sr = 0;
+ if (dvobj->customer_str_sctx != NULL) {
+ if (dvobj->customer_str_sctx->status != RTW_SCTX_SUBMITTED)
+ RTW_WARN("%s invalid sctx.status:%d\n", __func__, dvobj->customer_str_sctx->status);
+ _rtw_memcpy(dvobj->customer_str, C2H_CUSTOMER_STR_RPT_BYTE0(data), CUSTOMER_STR_RPT_LEN);
+ dvobj->customer_str_sctx->status = RTX_SCTX_CSTR_WAIT_RPT2;
+ } else
+ RTW_WARN("%s sctx not set\n", __func__);
- _enter_critical_mutex(mutex, NULL);
+ _exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
- rtw_write32(adapter, REG_CAMCMD, CAM_POLLINIG | addr);
+ ret = _SUCCESS;
- start = rtw_get_current_time();
- while (1) {
- if (rtw_is_surprise_removed(adapter)) {
- sr = 1;
- break;
- }
+exit:
+ return ret;
+}
- cnt++;
- if (0 == (rtw_read32(adapter, REG_CAMCMD) & CAM_POLLINIG))
- break;
+int c2h_customer_str_rpt_2_hdl(_adapter *adapter, u8 *data, u8 len)
+{
+ struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+ int ret = _FAIL;
+ int i;
- if (rtw_get_passing_time_ms(start) > SEC_CAM_ACCESS_TIMEOUT_MS) {
- timeout = 1;
- break;
- }
+ if (len < CUSTOMER_STR_RPT_2_LEN) {
+ RTW_WARN("%s len(%u) < %d\n", __func__, len, CUSTOMER_STR_RPT_2_LEN);
+ goto exit;
}
- end = rtw_get_current_time();
- rdata = rtw_read32(adapter, REG_CAMREAD);
+ if (DBG_CUSTOMER_STR_RPT_HANDLE)
+ RTW_PRINT_DUMP("customer_str_rpt_2: ", data, CUSTOMER_STR_RPT_2_LEN);
- _exit_critical_mutex(mutex, NULL);
+ _enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
- if (DBG_SEC_CAM_ACCESS || timeout) {
- RTW_INFO(FUNC_ADPT_FMT" addr:0x%02x, rdata:0x%08x, to:%u, polling:%u, %d ms\n"
- , FUNC_ADPT_ARG(adapter), addr, rdata, timeout, cnt, rtw_get_time_interval_ms(start, end));
- }
+ if (dvobj->customer_str_sctx != NULL) {
+ if (dvobj->customer_str_sctx->status != RTX_SCTX_CSTR_WAIT_RPT2)
+ RTW_WARN("%s rpt not ready\n", __func__);
+ _rtw_memcpy(dvobj->customer_str + CUSTOMER_STR_RPT_LEN, C2H_CUSTOMER_STR_RPT_2_BYTE8(data), CUSTOMER_STR_RPT_2_LEN);
+ rtw_sctx_done(&dvobj->customer_str_sctx);
+ } else
+ RTW_WARN("%s sctx not set\n", __func__);
- return rdata;
+ _exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
+
+ ret = _SUCCESS;
+
+exit:
+ return ret;
}
-void rtw_sec_write_cam(_adapter *adapter, u8 addr, u32 wdata)
+/* read customer str */
+s32 rtw_hal_customer_str_read(_adapter *adapter, u8 *cs)
{
- _mutex *mutex = &adapter_to_dvobj(adapter)->cam_ctl.sec_cam_access_mutex;
- u32 cnt = 0;
- u32 start = 0, end = 0;
- u8 timeout = 0;
- u8 sr = 0;
+ struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+ struct submit_ctx sctx;
+ s32 ret = _SUCCESS;
- _enter_critical_mutex(mutex, NULL);
+ _enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
+ if (dvobj->customer_str_sctx != NULL)
+ ret = _FAIL;
+ else {
+ rtw_sctx_init(&sctx, 2 * 1000);
+ dvobj->customer_str_sctx = &sctx;
+ }
+ _exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
+
+ if (ret == _FAIL) {
+ RTW_WARN("%s another handle ongoing\n", __func__);
+ goto exit;
+ }
+
+ ret = rtw_customer_str_req_cmd(adapter);
+ if (ret != _SUCCESS) {
+ RTW_WARN("%s read cmd fail\n", __func__);
+ _enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
+ dvobj->customer_str_sctx = NULL;
+ _exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
+ goto exit;
+ }
+
+ /* wait till rpt done or timeout */
+ rtw_sctx_wait(&sctx, __func__);
+
+ _enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
+ dvobj->customer_str_sctx = NULL;
+ if (sctx.status == RTW_SCTX_DONE_SUCCESS)
+ _rtw_memcpy(cs, dvobj->customer_str, RTW_CUSTOMER_STR_LEN);
+ else
+ ret = _FAIL;
+ _exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
+
+exit:
+ return ret;
+}
+
+s32 rtw_hal_h2c_customer_str_write(_adapter *adapter, const u8 *cs)
+{
+ u8 h2c_data_w1[H2C_CUSTOMER_STR_W1_LEN] = {0};
+ u8 h2c_data_w2[H2C_CUSTOMER_STR_W2_LEN] = {0};
+ u8 h2c_data_w3[H2C_CUSTOMER_STR_W3_LEN] = {0};
+ s32 ret;
+
+ SET_H2CCMD_CUSTOMER_STR_W1_EN(h2c_data_w1, 1);
+ _rtw_memcpy(H2CCMD_CUSTOMER_STR_W1_BYTE0(h2c_data_w1), cs, 6);
+
+ SET_H2CCMD_CUSTOMER_STR_W2_EN(h2c_data_w2, 1);
+ _rtw_memcpy(H2CCMD_CUSTOMER_STR_W2_BYTE6(h2c_data_w2), cs + 6, 6);
+
+ SET_H2CCMD_CUSTOMER_STR_W3_EN(h2c_data_w3, 1);
+ _rtw_memcpy(H2CCMD_CUSTOMER_STR_W3_BYTE12(h2c_data_w3), cs + 6 + 6, 4);
+
+ ret = rtw_hal_fill_h2c_cmd(adapter, H2C_CUSTOMER_STR_W1, H2C_CUSTOMER_STR_W1_LEN, h2c_data_w1);
+ if (ret != _SUCCESS) {
+ RTW_WARN("%s w1 fail\n", __func__);
+ goto exit;
+ }
+
+ ret = rtw_hal_fill_h2c_cmd(adapter, H2C_CUSTOMER_STR_W2, H2C_CUSTOMER_STR_W2_LEN, h2c_data_w2);
+ if (ret != _SUCCESS) {
+ RTW_WARN("%s w2 fail\n", __func__);
+ goto exit;
+ }
+
+ ret = rtw_hal_fill_h2c_cmd(adapter, H2C_CUSTOMER_STR_W3, H2C_CUSTOMER_STR_W3_LEN, h2c_data_w3);
+ if (ret != _SUCCESS) {
+ RTW_WARN("%s w3 fail\n", __func__);
+ goto exit;
+ }
+
+exit:
+ return ret;
+}
+
+/* write customer str and check if value reported is the same as requested */
+s32 rtw_hal_customer_str_write(_adapter *adapter, const u8 *cs)
+{
+ struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+ struct submit_ctx sctx;
+ s32 ret = _SUCCESS;
+
+ _enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
+ if (dvobj->customer_str_sctx != NULL)
+ ret = _FAIL;
+ else {
+ rtw_sctx_init(&sctx, 2 * 1000);
+ dvobj->customer_str_sctx = &sctx;
+ }
+ _exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
+
+ if (ret == _FAIL) {
+ RTW_WARN("%s another handle ongoing\n", __func__);
+ goto exit;
+ }
+
+ ret = rtw_customer_str_write_cmd(adapter, cs);
+ if (ret != _SUCCESS) {
+ RTW_WARN("%s write cmd fail\n", __func__);
+ _enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
+ dvobj->customer_str_sctx = NULL;
+ _exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
+ goto exit;
+ }
+
+ ret = rtw_customer_str_req_cmd(adapter);
+ if (ret != _SUCCESS) {
+ RTW_WARN("%s read cmd fail\n", __func__);
+ _enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
+ dvobj->customer_str_sctx = NULL;
+ _exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
+ goto exit;
+ }
+
+ /* wait till rpt done or timeout */
+ rtw_sctx_wait(&sctx, __func__);
+
+ _enter_critical_mutex(&dvobj->customer_str_mutex, NULL);
+ dvobj->customer_str_sctx = NULL;
+ if (sctx.status == RTW_SCTX_DONE_SUCCESS) {
+ if (_rtw_memcmp(cs, dvobj->customer_str, RTW_CUSTOMER_STR_LEN) != _TRUE) {
+ RTW_WARN("%s read back check fail\n", __func__);
+ RTW_INFO_DUMP("write req: ", cs, RTW_CUSTOMER_STR_LEN);
+ RTW_INFO_DUMP("read back: ", dvobj->customer_str, RTW_CUSTOMER_STR_LEN);
+ ret = _FAIL;
+ }
+ } else
+ ret = _FAIL;
+ _exit_critical_mutex(&dvobj->customer_str_mutex, NULL);
+
+exit:
+ return ret;
+}
+#endif /* CONFIG_RTW_CUSTOMER_STR */
+
+#ifdef RTW_PER_CMD_SUPPORT_FW
+#define H2C_REQ_PER_RPT_LEN 5
+#define SET_H2CCMD_REQ_PER_RPT_GROUP_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
+#define SET_H2CCMD_REQ_PER_RPT_RPT_TYPE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
+#define SET_H2CCMD_REQ_PER_RPT_MACID_BMAP(__pH2CCmd, __Value) SET_BITS_TO_LE_4BYTE(__pH2CCmd + 1, 0, 32, __Value)
+
+u8 rtw_hal_set_req_per_rpt_cmd(_adapter *adapter, u8 group_macid,
+ u8 rpt_type, u32 macid_bitmap)
+{
+ u8 ret = _FAIL;
+ u8 cmd_buf[H2C_REQ_PER_RPT_LEN] = {0};
+
+ SET_H2CCMD_REQ_PER_RPT_GROUP_MACID(cmd_buf, group_macid);
+ SET_H2CCMD_REQ_PER_RPT_RPT_TYPE(cmd_buf, rpt_type);
+ SET_H2CCMD_REQ_PER_RPT_MACID_BMAP(cmd_buf, macid_bitmap);
+
+ ret = rtw_hal_fill_h2c_cmd(adapter,
+ H2C_REQ_PER_RPT,
+ H2C_REQ_PER_RPT_LEN,
+ cmd_buf);
+ return ret;
+}
+
+#define GET_C2H_PER_RATE_RPT_TYPE0_MACID0(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)), 0, 8)
+#define GET_C2H_PER_RATE_RPT_TYPE0_PER0(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 1, 0, 8)
+#define GET_C2H_PER_RATE_RPT_TYPE0_RATE0(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 2, 0, 8)
+#define GET_C2H_PER_RATE_RPT_TYPE0_BW0(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 3, 0, 2)
+#define GET_C2H_PER_RATE_RPT_TYPE0_TOTAL_PKT0(_data) LE_BITS_TO_2BYTE(((u8 *)(_data)) + 4, 0, 16)
+#define GET_C2H_PER_RATE_RPT_TYPE0_MACID1(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 6, 0, 8)
+#define GET_C2H_PER_RATE_RPT_TYPE0_PER1(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 7, 0, 8)
+#define GET_C2H_PER_RATE_RPT_TYPE0_RATE1(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 8, 0, 8)
+#define GET_C2H_PER_RATE_RPT_TYPE0_BW1(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 9, 0, 2)
+#define GET_C2H_PER_RATE_RPT_TYPE0_TOTAL_PKT1(_data) LE_BITS_TO_2BYTE(((u8 *)(_data)) + 10, 0, 16)
+
+#define GET_C2H_PER_RATE_RPT_TYPE1_MACID0(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)), 0, 8)
+#define GET_C2H_PER_RATE_RPT_TYPE1_PER0(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 1, 0, 8)
+#define GET_C2H_PER_RATE_RPT_TYPE1_RATE0(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 2, 0, 8)
+#define GET_C2H_PER_RATE_RPT_TYPE1_BW0(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 3, 0, 2)
+#define GET_C2H_PER_RATE_RPT_TYPE1_MACID1(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 4, 0, 8)
+#define GET_C2H_PER_RATE_RPT_TYPE1_PER1(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 5, 0, 8)
+#define GET_C2H_PER_RATE_RPT_TYPE1_RATE1(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 6, 0, 8)
+#define GET_C2H_PER_RATE_RPT_TYPE1_BW1(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 7, 0, 2)
+#define GET_C2H_PER_RATE_RPT_TYPE1_MACID2(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 8, 0, 8)
+#define GET_C2H_PER_RATE_RPT_TYPE1_PER2(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 9, 0, 8)
+#define GET_C2H_PER_RATE_RPT_TYPE1_RATE2(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 10, 0, 8)
+#define GET_C2H_PER_RATE_RPT_TYPE1_BW2(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 11, 0, 2)
+
+static void per_rate_rpt_update(_adapter *adapter, u8 mac_id,
+ u8 per, u8 rate,
+ u8 bw, u8 total_pkt)
+{
+#ifdef CONFIG_RTW_MESH
+ rtw_ieee80211s_update_metric(adapter, mac_id,
+ per, rate,
+ bw, total_pkt);
+#endif
+}
+
+int c2h_per_rate_rpt_hdl(_adapter *adapter, u8 *data, u8 len)
+{
+ /* Now only consider type0, since it covers all params in type1
+ * type0: mac_id, per, rate, bw, total_pkt
+ * type1: mac_id, per, rate, bw
+ */
+ u8 mac_id[2] = {0}, per[2] = {0}, rate[2] = {0}, bw[2] = {0};
+ u16 total_pkt[2] = {0};
+ int ret = _FAIL, i, macid_cnt = 0;
+
+ /* type0:
+ * 1 macid includes 6 bytes info + 1 byte 0xff
+ * 2 macid includes 2*6 bytes info
+ */
+ if (!(len == 7 || len == 12)) {
+ RTW_WARN("%s len(%u) != 7 or 12\n", __FUNCTION__, len);
+ goto exit;
+ }
+
+ macid_cnt++;
+ mac_id[0] = GET_C2H_PER_RATE_RPT_TYPE0_MACID0(data);
+ per[0] = GET_C2H_PER_RATE_RPT_TYPE0_PER0(data);
+ rate[0] = GET_C2H_PER_RATE_RPT_TYPE0_RATE0(data);
+ bw[0] = GET_C2H_PER_RATE_RPT_TYPE0_BW0(data);
+ total_pkt[0] = GET_C2H_PER_RATE_RPT_TYPE0_TOTAL_PKT0(data);
+
+ mac_id[1] = GET_C2H_PER_RATE_RPT_TYPE0_MACID1(data);
+ /* 0xff means no report anymore */
+ if (mac_id[1] == 0xff)
+ goto update_per;
+ if (len != 12) {
+ RTW_WARN("%s incorrect format\n", __FUNCTION__);
+ goto exit;
+ }
+ macid_cnt++;
+ per[1] = GET_C2H_PER_RATE_RPT_TYPE0_PER1(data);
+ rate[1] = GET_C2H_PER_RATE_RPT_TYPE0_RATE1(data);
+ bw[1] = GET_C2H_PER_RATE_RPT_TYPE0_BW1(data);
+ total_pkt[1] = GET_C2H_PER_RATE_RPT_TYPE0_TOTAL_PKT1(data);
+
+update_per:
+ for (i = 0; i < macid_cnt; i++) {
+ RTW_DBG("[%s] type0 rpt[%d]: macid = %u, per = %u, "
+ "rate = %u, bw = %u, total_pkt = %u\n",
+ __FUNCTION__, i, mac_id[i], per[i],
+ rate[i], bw[i], total_pkt[i]);
+ per_rate_rpt_update(adapter, mac_id[i],
+ per[i], rate[i],
+ bw[i], total_pkt[i]);
+ }
+ ret = _SUCCESS;
+exit:
+ return ret;
+}
+#endif /* RTW_PER_CMD_SUPPORT_FW */
+
+void rtw_hal_update_sta_wset(_adapter *adapter, struct sta_info *psta)
+{
+ u8 w_set = 0;
+
+ if (psta->wireless_mode & WIRELESS_11B)
+ w_set |= WIRELESS_CCK;
+
+ if ((psta->wireless_mode & WIRELESS_11G) || (psta->wireless_mode & WIRELESS_11A))
+ w_set |= WIRELESS_OFDM;
+
+ if (psta->wireless_mode & WIRELESS_11_24N)
+ w_set |= WIRELESS_HT;
+
+ if ((psta->wireless_mode & WIRELESS_11AC) || (psta->wireless_mode & WIRELESS_11_5N))
+ w_set |= WIRELESS_VHT;
+
+ psta->cmn.support_wireless_set = w_set;
+}
+
+void rtw_hal_update_sta_mimo_type(_adapter *adapter, struct sta_info *psta)
+{
+ s8 tx_nss, rx_nss;
+
+ tx_nss = rtw_get_sta_tx_nss(adapter, psta);
+ rx_nss = rtw_get_sta_rx_nss(adapter, psta);
+ if ((tx_nss == 1) && (rx_nss == 1))
+ psta->cmn.mimo_type = RF_1T1R;
+ else if ((tx_nss == 1) && (rx_nss == 2))
+ psta->cmn.mimo_type = RF_1T2R;
+ else if ((tx_nss == 2) && (rx_nss == 2))
+ psta->cmn.mimo_type = RF_2T2R;
+ else if ((tx_nss == 2) && (rx_nss == 3))
+ psta->cmn.mimo_type = RF_2T3R;
+ else if ((tx_nss == 2) && (rx_nss == 4))
+ psta->cmn.mimo_type = RF_2T4R;
+ else if ((tx_nss == 3) && (rx_nss == 3))
+ psta->cmn.mimo_type = RF_3T3R;
+ else if ((tx_nss == 3) && (rx_nss == 4))
+ psta->cmn.mimo_type = RF_3T4R;
+ else if ((tx_nss == 4) && (rx_nss == 4))
+ psta->cmn.mimo_type = RF_4T4R;
+ else
+ rtw_warn_on(1);
+
+ RTW_INFO("STA - MAC_ID:%d, Tx - %d SS, Rx - %d SS\n",
+ psta->cmn.mac_id, tx_nss, rx_nss);
+}
+
+void rtw_hal_update_sta_smps_cap(_adapter *adapter, struct sta_info *psta)
+{
+ /*Spatial Multiplexing Power Save*/
+#if 0
+ if (check_fwstate(&adapter->mlmepriv, WIFI_AP_STATE) == _TRUE) {
+ #ifdef CONFIG_80211N_HT
+ if (psta->htpriv.ht_option) {
+ if (psta->htpriv.smps_cap == 0)
+ psta->cmn.sm_ps = SM_PS_STATIC;
+ else if (psta->htpriv.smps_cap == 1)
+ psta->cmn.sm_ps = SM_PS_DYNAMIC;
+ else
+ psta->cmn.sm_ps = SM_PS_DISABLE;
+ }
+ #endif /* CONFIG_80211N_HT */
+ } else
+#endif
+ psta->cmn.sm_ps = SM_PS_DISABLE;
+
+ RTW_INFO("STA - MAC_ID:%d, SM_PS %d\n",
+ psta->cmn.mac_id, psta->cmn.sm_ps);
+}
+
+u8 rtw_get_mgntframe_raid(_adapter *adapter, unsigned char network_type)
+{
+
+ u8 raid;
+ if (IS_NEW_GENERATION_IC(adapter)) {
+
+ raid = (network_type & WIRELESS_11B) ? RATEID_IDX_B
+ : RATEID_IDX_G;
+ } else {
+ raid = (network_type & WIRELESS_11B) ? RATR_INX_WIRELESS_B
+ : RATR_INX_WIRELESS_G;
+ }
+ return raid;
+}
+
+void rtw_hal_update_sta_rate_mask(PADAPTER padapter, struct sta_info *psta)
+{
+ struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter);
+ u8 i, rf_type, tx_nss;
+ u64 tx_ra_bitmap = 0;
+
+ if (psta == NULL)
+ return;
+
+ /* b/g mode ra_bitmap */
+ for (i = 0; i < sizeof(psta->bssrateset); i++) {
+ if (psta->bssrateset[i])
+ tx_ra_bitmap |= rtw_get_bit_value_from_ieee_value(psta->bssrateset[i] & 0x7f);
+ }
+
+#ifdef CONFIG_80211N_HT
+ rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
+ tx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num);
+#ifdef CONFIG_80211AC_VHT
+ if (psta->vhtpriv.vht_option) {
+ /* AC mode ra_bitmap */
+ tx_ra_bitmap |= (rtw_vht_mcs_map_to_bitmap(psta->vhtpriv.vht_mcs_map, tx_nss) << 12);
+ } else
+#endif /* CONFIG_80211AC_VHT */
+ if (psta->htpriv.ht_option) {
+ /* n mode ra_bitmap */
+
+ /* Handling SMPS mode for AP MODE only*/
+ if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) {
+ /*0:static SMPS, 1:dynamic SMPS, 3:SMPS disabled, 2:reserved*/
+ if (psta->htpriv.smps_cap == 0 || psta->htpriv.smps_cap == 1) {
+ /*operate with only one active receive chain // 11n-MCS rate <= MSC7*/
+ tx_nss = rtw_min(tx_nss, 1);
+ }
+ }
+
+ tx_ra_bitmap |= (rtw_ht_mcs_set_to_bitmap(psta->htpriv.ht_cap.supp_mcs_set, tx_nss) << 12);
+ }
+#endif /* CONFIG_80211N_HT */
+ psta->cmn.ra_info.ramask = tx_ra_bitmap;
+ psta->init_rate = get_highest_rate_idx(tx_ra_bitmap) & 0x3f;
+}
+
+void rtw_hal_update_sta_ra_info(PADAPTER padapter, struct sta_info *psta)
+{
+ rtw_hal_update_sta_mimo_type(padapter, psta);
+ rtw_hal_update_sta_smps_cap(padapter, psta);
+ rtw_hal_update_sta_rate_mask(padapter, psta);
+}
+
+#ifndef SEC_CAM_ACCESS_TIMEOUT_MS
+ #define SEC_CAM_ACCESS_TIMEOUT_MS 200
+#endif
+
+#ifndef DBG_SEC_CAM_ACCESS
+ #define DBG_SEC_CAM_ACCESS 0
+#endif
+
+u32 rtw_sec_read_cam(_adapter *adapter, u8 addr)
+{
+ _mutex *mutex = &adapter_to_dvobj(adapter)->cam_ctl.sec_cam_access_mutex;
+ u32 rdata;
+ u32 cnt = 0;
+ systime start = 0, end = 0;
+ u8 timeout = 0;
+ u8 sr = 0;
+
+ _enter_critical_mutex(mutex, NULL);
+
+ rtw_write32(adapter, REG_CAMCMD, CAM_POLLINIG | addr);
+
+ start = rtw_get_current_time();
+ while (1) {
+ if (rtw_is_surprise_removed(adapter)) {
+ sr = 1;
+ break;
+ }
+
+ cnt++;
+ if (0 == (rtw_read32(adapter, REG_CAMCMD) & CAM_POLLINIG))
+ break;
+
+ if (rtw_get_passing_time_ms(start) > SEC_CAM_ACCESS_TIMEOUT_MS) {
+ timeout = 1;
+ break;
+ }
+ }
+ end = rtw_get_current_time();
+
+ rdata = rtw_read32(adapter, REG_CAMREAD);
+
+ _exit_critical_mutex(mutex, NULL);
+
+ if (DBG_SEC_CAM_ACCESS || timeout) {
+ RTW_INFO(FUNC_ADPT_FMT" addr:0x%02x, rdata:0x%08x, to:%u, polling:%u, %d ms\n"
+ , FUNC_ADPT_ARG(adapter), addr, rdata, timeout, cnt, rtw_get_time_interval_ms(start, end));
+ }
+
+ return rdata;
+}
+
+void rtw_sec_write_cam(_adapter *adapter, u8 addr, u32 wdata)
+{
+ _mutex *mutex = &adapter_to_dvobj(adapter)->cam_ctl.sec_cam_access_mutex;
+ u32 cnt = 0;
+ systime start = 0, end = 0;
+ u8 timeout = 0;
+ u8 sr = 0;
+
+ _enter_critical_mutex(mutex, NULL);
rtw_write32(adapter, REG_CAMWRITE, wdata);
rtw_write32(adapter, REG_CAMCMD, CAM_POLLINIG | CAM_WRITE | addr);
@@ -1671,7 +2244,7 @@ void rtw_sec_write_cam_ent(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key)
}
#else
- j = 5;
+ j = 7;
#endif
for (; j >= 0; j--) {
@@ -1682,6 +2255,10 @@ void rtw_sec_write_cam_ent(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key)
case 1:
wdata = (mac[2] | (mac[3] << 8) | (mac[4] << 16) | (mac[5] << 24));
break;
+ case 6:
+ case 7:
+ wdata = 0;
+ break;
default:
i = (j - 2) << 2;
wdata = (key[i] | (key[i + 1] << 8) | (key[i + 2] << 16) | (key[i + 3] << 24));
@@ -1694,6 +2271,14 @@ void rtw_sec_write_cam_ent(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key)
}
}
+void rtw_sec_clr_cam_ent(_adapter *adapter, u8 id)
+{
+ u8 addr;
+
+ addr = (id << 3);
+ rtw_sec_write_cam(adapter, addr, 0);
+}
+
bool rtw_sec_read_cam_is_gk(_adapter *adapter, u8 id)
{
bool res;
@@ -1977,10 +2562,12 @@ int rtw_mbid_cam_cache_dump(void *sel, const char *fun_name, _adapter *adapter)
iface = dvobj->padapters[iface_id];
if (iface) {
- if (check_fwstate(&iface->mlmepriv, WIFI_STATION_STATE) == _TRUE)
+ if (MLME_IS_STA(iface))
RTW_PRINT_SEL(sel, "ROLE:%s\n", "STA");
- else if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) == _TRUE)
+ else if (MLME_IS_AP(iface))
RTW_PRINT_SEL(sel, "ROLE:%s\n", "AP");
+ else if (MLME_IS_MESH(iface))
+ RTW_PRINT_SEL(sel, "ROLE:%s\n", "MESH");
else
RTW_PRINT_SEL(sel, "ROLE:%s\n", "NONE");
}
@@ -2065,10 +2652,10 @@ static void enable_mbssid_cam(_adapter *adapter)
{
u8 max_cam_id = rtw_get_max_mbid_cam_id(adapter);
/*enable MBSSID*/
- rtw_write32(adapter, REG_RCR, rtw_read32(adapter, REG_RCR) | RCR_ENMBID);
+ rtw_hal_rcr_add(adapter, RCR_ENMBID);
if (max_cam_id != INVALID_CAM_ID) {
rtw_write8(adapter, REG_MBID_NUM,
- ((rtw_read8(adapter, REG_MBID_NUM) & 0xF8) | (max_cam_id & 0x07)));
+ ((rtw_read8(adapter, REG_MBID_NUM) & 0xF8) | ((max_cam_id -1) & 0x07)));
}
}
void rtw_mbid_cam_restore(_adapter *adapter)
@@ -2099,7 +2686,7 @@ void rtw_hal_set_macaddr_mbid(_adapter *adapter, u8 *mac_addr)
u8 idx = 0;
if ((check_fwstate(&adapter->mlmepriv, WIFI_STATION_STATE) == _TRUE) &&
- (adapter_to_dvobj(adapter)->iface_state.sta_num == 1)) {
+ (DEV_STA_NUM(adapter_to_dvobj(adapter)) == 1)) {
for (idx = 0; idx < 6; idx++)
rtw_write8(GET_PRIMARY_ADAPTER(adapter), (REG_MACID + idx), val[idx]);
} else {
@@ -2107,7 +2694,7 @@ void rtw_hal_set_macaddr_mbid(_adapter *adapter, u8 *mac_addr)
u8 entry_id;
if ((check_fwstate(&adapter->mlmepriv, WIFI_AP_STATE) == _TRUE) &&
- (adapter_to_dvobj(adapter)->iface_state.ap_num == 1)) {
+ (DEV_AP_NUM(adapter_to_dvobj(adapter)) == 1)) {
entry_id = 0;
if (rtw_mbid_cam_assign(adapter, val, entry_id)) {
RTW_INFO(FUNC_ADPT_FMT" Root AP assigned success\n", FUNC_ADPT_ARG(adapter));
@@ -2153,10 +2740,19 @@ void rtw_hal_change_macaddr_mbid(_adapter *adapter, u8 *mac_addr)
write_mbssid_cam(adapter, entry_id, mac_addr);
}
+#ifdef CONFIG_SWTIMER_BASED_TXBCN
+u16 rtw_hal_bcn_interval_adjust(_adapter *adapter, u16 bcn_interval)
+{
+ if (adapter_to_dvobj(adapter)->inter_bcn_space != bcn_interval)
+ return adapter_to_dvobj(adapter)->inter_bcn_space;
+ else
+ return bcn_interval;
+}
+#endif/*CONFIG_SWTIMER_BASED_TXBCN*/
#endif/*#ifdef CONFIG_MI_WITH_MBSSID_CAM*/
-void rtw_hal_set_macaddr_port(_adapter *adapter, u8 *val)
+static void rtw_hal_set_macaddr_port(_adapter *adapter, u8 *val)
{
u8 idx = 0;
u32 reg_macid = 0;
@@ -2167,6 +2763,9 @@ void rtw_hal_set_macaddr_port(_adapter *adapter, u8 *val)
RTW_INFO("%s "ADPT_FMT"- hw port(%d) mac_addr ="MAC_FMT"\n", __func__,
ADPT_ARG(adapter), adapter->hw_port, MAC_ARG(val));
+#ifdef RTW_HALMAC
+ rtw_halmac_set_mac_address(adapter_to_dvobj(adapter), adapter->hw_port, val);
+#else /* !RTW_HALMAC */
switch (adapter->hw_port) {
case HW_PORT0:
default:
@@ -2190,8 +2789,10 @@ void rtw_hal_set_macaddr_port(_adapter *adapter, u8 *val)
for (idx = 0; idx < 6; idx++)
rtw_write8(GET_PRIMARY_ADAPTER(adapter), (reg_macid + idx), val[idx]);
+#endif /* !RTW_HALMAC */
}
-void rtw_hal_get_macaddr_port(_adapter *adapter, u8 *mac_addr)
+
+static void rtw_hal_get_macaddr_port(_adapter *adapter, u8 *mac_addr)
{
u8 idx = 0;
u32 reg_macid = 0;
@@ -2200,6 +2801,9 @@ void rtw_hal_get_macaddr_port(_adapter *adapter, u8 *mac_addr)
return;
_rtw_memset(mac_addr, 0, ETH_ALEN);
+#ifdef RTW_HALMAC
+ rtw_halmac_get_mac_address(adapter_to_dvobj(adapter), adapter->hw_port, mac_addr);
+#else /* !RTW_HALMAC */
switch (adapter->hw_port) {
case HW_PORT0:
default:
@@ -2223,13 +2827,17 @@ void rtw_hal_get_macaddr_port(_adapter *adapter, u8 *mac_addr)
for (idx = 0; idx < 6; idx++)
mac_addr[idx] = rtw_read8(GET_PRIMARY_ADAPTER(adapter), (reg_macid + idx));
+#endif /* !RTW_HALMAC */
RTW_INFO("%s "ADPT_FMT"- hw port(%d) mac_addr ="MAC_FMT"\n", __func__,
ADPT_ARG(adapter), adapter->hw_port, MAC_ARG(mac_addr));
}
-void rtw_hal_set_bssid(_adapter *adapter, u8 *val)
+static void rtw_hal_set_bssid(_adapter *adapter, u8 *val)
{
+#ifdef RTW_HALMAC
+ rtw_halmac_set_bssid(adapter_to_dvobj(adapter), adapter->hw_port, val);
+#else /* !RTW_HALMAC */
u8 idx = 0;
u32 reg_bssid = 0;
@@ -2256,59 +2864,242 @@ void rtw_hal_set_bssid(_adapter *adapter, u8 *val)
for (idx = 0 ; idx < 6; idx++)
rtw_write8(adapter, (reg_bssid + idx), val[idx]);
+#endif /* !RTW_HALMAC */
RTW_INFO("%s "ADPT_FMT"- hw port -%d BSSID: "MAC_FMT"\n", __func__, ADPT_ARG(adapter), adapter->hw_port, MAC_ARG(val));
}
-void rtw_hal_get_msr(_adapter *adapter, u8 *net_type)
+static inline u8 hw_var_rcr_config(_adapter *adapter, u32 rcr)
{
- switch (adapter->hw_port) {
- case HW_PORT0:
- /*REG_CR - BIT[17:16]-Network Type for port 1*/
- *net_type = rtw_read8(adapter, MSR) & 0x03;
- break;
- case HW_PORT1:
- /*REG_CR - BIT[19:18]-Network Type for port 1*/
- *net_type = (rtw_read8(adapter, MSR) & 0x0C) >> 2;
- break;
-#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B)
- case HW_PORT2:
- /*REG_CR_EXT- BIT[1:0]-Network Type for port 2*/
- *net_type = rtw_read8(adapter, MSR1) & 0x03;
- break;
- case HW_PORT3:
- /*REG_CR_EXT- BIT[3:2]-Network Type for port 3*/
- *net_type = (rtw_read8(adapter, MSR1) & 0x0C) >> 2;
- break;
- case HW_PORT4:
- /*REG_CR_EXT- BIT[5:4]-Network Type for port 4*/
- *net_type = (rtw_read8(adapter, MSR1) & 0x30) >> 4;
- break;
-#endif /*#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B)*/
- default:
- RTW_INFO("[WARN] "ADPT_FMT"- invalid hw port -%d\n",
- ADPT_ARG(adapter), adapter->hw_port);
- rtw_warn_on(1);
- break;
- }
+ int err;
+
+ err = rtw_write32(adapter, REG_RCR, rcr);
+ if (err == _SUCCESS)
+ GET_HAL_DATA(adapter)->ReceiveConfig = rcr;
+ return err;
}
-void rtw_hal_set_msr(_adapter *adapter, u8 net_type)
+static inline u8 hw_var_rcr_get(_adapter *adapter, u32 *rcr)
{
- u8 val8 = 0;
+ u32 v32;
- switch (adapter->hw_port) {
- case HW_PORT0:
-#if defined(CONFIG_MI_WITH_MBSSID_CAM) && defined(CONFIG_MBSSID_CAM) /*For 2 hw ports - 88E/92E/8812/8821/8723B*/
- if (rtw_get_mbid_cam_entry_num(adapter)) {
- if (net_type != _HW_STATE_NOLINK_)
- net_type = _HW_STATE_AP_;
- }
-#endif
- /*REG_CR - BIT[17:16]-Network Type for port 0*/
- val8 = rtw_read8(adapter, MSR) & 0x0C;
- val8 |= net_type;
- rtw_write8(adapter, MSR, val8);
+ v32 = rtw_read32(adapter, REG_RCR);
+ if (rcr)
+ *rcr = v32;
+ GET_HAL_DATA(adapter)->ReceiveConfig = v32;
+ return _SUCCESS;
+}
+
+/* only check SW RCR variable */
+inline u8 rtw_hal_rcr_check(_adapter *adapter, u32 check_bit)
+{
+ PHAL_DATA_TYPE hal;
+ u32 rcr;
+
+ hal = GET_HAL_DATA(adapter);
+
+ rcr = hal->ReceiveConfig;
+ if ((rcr & check_bit) == check_bit)
+ return 1;
+
+ return 0;
+}
+
+inline u8 rtw_hal_rcr_add(_adapter *adapter, u32 add)
+{
+ PHAL_DATA_TYPE hal;
+ u32 rcr;
+ u8 ret = _SUCCESS;
+
+ hal = GET_HAL_DATA(adapter);
+
+ rtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr);
+ rcr |= add;
+ if (rcr != hal->ReceiveConfig)
+ ret = rtw_hal_set_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr);
+
+ return ret;
+}
+
+inline u8 rtw_hal_rcr_clear(_adapter *adapter, u32 clear)
+{
+ PHAL_DATA_TYPE hal;
+ u32 rcr;
+ u8 ret = _SUCCESS;
+
+ hal = GET_HAL_DATA(adapter);
+
+ rtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr);
+ rcr &= ~clear;
+ if (rcr != hal->ReceiveConfig)
+ ret = rtw_hal_set_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr);
+
+ return ret;
+}
+
+void rtw_hal_rcr_set_chk_bssid(_adapter *adapter, u8 self_action)
+{
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+ u32 rcr, rcr_new;
+ struct mi_state mstate, mstate_s;
+
+ rtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr);
+ rcr_new = rcr;
+
+#ifdef CONFIG_MI_WITH_MBSSID_CAM
+ rcr_new &= ~(RCR_CBSSID_BCN | RCR_CBSSID_DATA);
+#else
+ rtw_mi_status_no_self(adapter, &mstate);
+ rtw_mi_status_no_others(adapter, &mstate_s);
+
+ /* only adjust parameters interested */
+ switch (self_action) {
+ case MLME_SCAN_ENTER:
+ mstate_s.scan_num = 1;
+ mstate_s.scan_enter_num = 1;
+ break;
+ case MLME_SCAN_DONE:
+ mstate_s.scan_enter_num = 0;
+ break;
+#ifdef CONFIG_TDLS
+ case MLME_TDLS_LINKED:
+ mstate_s.ld_tdls_num = 1;
+ break;
+ case MLME_TDLS_NOLINK:
+ mstate_s.ld_tdls_num = 0;
+ break;
+#endif
+#ifdef CONFIG_AP_MODE
+ case MLME_AP_STARTED:
+ mstate_s.ap_num = 1;
+ break;
+ case MLME_AP_STOPPED:
+ mstate_s.ap_num = 0;
+ mstate_s.ld_ap_num = 0;
+ break;
+#endif
+#ifdef CONFIG_RTW_MESH
+ case MLME_MESH_STARTED:
+ mstate_s.mesh_num = 1;
+ break;
+ case MLME_MESH_STOPPED:
+ mstate_s.mesh_num = 0;
+ mstate_s.ld_mesh_num = 0;
+ break;
+#endif
+ case MLME_ACTION_NONE:
+ case MLME_STA_CONNECTING:
+ case MLME_ADHOC_STARTED:
+ /* caller without effect of decision */
+ break;
+ default:
+ rtw_warn_on(1);
+ };
+
+ rtw_mi_status_merge(&mstate, &mstate_s);
+
+ if (MSTATE_AP_NUM(&mstate) || MSTATE_MESH_NUM(&mstate) || MSTATE_TDLS_LD_NUM(&mstate)
+ #ifdef CONFIG_FIND_BEST_CHANNEL
+ || MSTATE_SCAN_ENTER_NUM(&mstate)
+ #endif
+ || hal_data->in_cta_test
+ )
+ rcr_new &= ~RCR_CBSSID_DATA;
+ else
+ rcr_new |= RCR_CBSSID_DATA;
+
+ if ((MSTATE_AP_NUM(&mstate) && adapter->registrypriv.wifi_spec) /* for 11n Logo 4.2.31/4.2.32 */
+ || MSTATE_MESH_NUM(&mstate)
+ || MSTATE_SCAN_ENTER_NUM(&mstate)
+ || hal_data->in_cta_test
+ )
+ rcr_new &= ~RCR_CBSSID_BCN;
+ else
+ rcr_new |= RCR_CBSSID_BCN;
+#endif /* CONFIG_MI_WITH_MBSSID_CAM */
+
+ if (rcr != rcr_new)
+ rtw_hal_set_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr_new);
+}
+
+static void hw_var_set_rcr_am(_adapter *adapter, u8 enable)
+{
+ u32 rcr = RCR_AM;
+
+ if (enable)
+ rtw_hal_rcr_add(adapter, rcr);
+ else
+ rtw_hal_rcr_clear(adapter, rcr);
+}
+
+static void rtw_hal_get_msr(_adapter *adapter, u8 *net_type)
+{
+#ifdef RTW_HALMAC
+ rtw_halmac_get_network_type(adapter_to_dvobj(adapter),
+ adapter->hw_port, net_type);
+#else /* !RTW_HALMAC */
+ switch (adapter->hw_port) {
+ case HW_PORT0:
+ /*REG_CR - BIT[17:16]-Network Type for port 1*/
+ *net_type = rtw_read8(adapter, MSR) & 0x03;
+ break;
+ case HW_PORT1:
+ /*REG_CR - BIT[19:18]-Network Type for port 1*/
+ *net_type = (rtw_read8(adapter, MSR) & 0x0C) >> 2;
+ break;
+#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B)
+ case HW_PORT2:
+ /*REG_CR_EXT- BIT[1:0]-Network Type for port 2*/
+ *net_type = rtw_read8(adapter, MSR1) & 0x03;
+ break;
+ case HW_PORT3:
+ /*REG_CR_EXT- BIT[3:2]-Network Type for port 3*/
+ *net_type = (rtw_read8(adapter, MSR1) & 0x0C) >> 2;
+ break;
+ case HW_PORT4:
+ /*REG_CR_EXT- BIT[5:4]-Network Type for port 4*/
+ *net_type = (rtw_read8(adapter, MSR1) & 0x30) >> 4;
+ break;
+#endif /*#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B)*/
+ default:
+ RTW_INFO("[WARN] "ADPT_FMT"- invalid hw port -%d\n",
+ ADPT_ARG(adapter), adapter->hw_port);
+ rtw_warn_on(1);
+ break;
+ }
+#endif /* !RTW_HALMAC */
+}
+
+#if defined(CONFIG_MI_WITH_MBSSID_CAM) && defined(CONFIG_MBSSID_CAM) /*For 2 hw ports - 88E/92E/8812/8821/8723B*/
+static u8 rtw_hal_net_type_decision(_adapter *adapter, u8 net_type)
+{
+ if ((adapter->hw_port == HW_PORT0) && (rtw_get_mbid_cam_entry_num(adapter))) {
+ if (net_type != _HW_STATE_NOLINK_)
+ return _HW_STATE_AP_;
+ }
+ return net_type;
+}
+#endif
+static void rtw_hal_set_msr(_adapter *adapter, u8 net_type)
+{
+#ifdef RTW_HALMAC
+ #if defined(CONFIG_MI_WITH_MBSSID_CAM) && defined(CONFIG_MBSSID_CAM)
+ net_type = rtw_hal_net_type_decision(adapter, net_type);
+ #endif
+ rtw_halmac_set_network_type(adapter_to_dvobj(adapter),
+ adapter->hw_port, net_type);
+#else /* !RTW_HALMAC */
+ u8 val8 = 0;
+
+ switch (adapter->hw_port) {
+ case HW_PORT0:
+ #if defined(CONFIG_MI_WITH_MBSSID_CAM) && defined(CONFIG_MBSSID_CAM)
+ net_type = rtw_hal_net_type_decision(adapter, net_type);
+ #endif
+ /*REG_CR - BIT[17:16]-Network Type for port 0*/
+ val8 = rtw_read8(adapter, MSR) & 0x0C;
+ val8 |= net_type;
+ rtw_write8(adapter, MSR, val8);
break;
case HW_PORT1:
/*REG_CR - BIT[19:18]-Network Type for port 1*/
@@ -2342,29 +3133,19 @@ void rtw_hal_set_msr(_adapter *adapter, u8 net_type)
rtw_warn_on(1);
break;
}
+#endif /* !RTW_HALMAC */
}
-void rtw_hal_port_reconfig(_adapter *adapter, u8 port)
+static void hw_var_set_bcn_interval(struct _ADAPTER *a, u16 interval)
{
-#ifdef CONFIG_CONCURRENT_MODE
- u8 hal_port_num = 0;
- struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
- struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
-
- if (port > (hal_spec->port_num - 1)) {
- RTW_INFO("[WARN] "ADPT_FMT"- hw_port : %d,will switch to invalid port-%d\n",
- ADPT_ARG(adapter), adapter->hw_port, port);
- rtw_warn_on(1);
- }
-
- RTW_PRINT(ADPT_FMT"- hw_port : %d,will switch to port-%d\n",
- ADPT_ARG(adapter), adapter->hw_port, port);
-
-#endif
-
+#ifdef RTW_HALMAC
+ rtw_halmac_set_bcn_interval(adapter_to_dvobj(a), a->hw_port, interval);
+#else /* !RTW_HALMAC */
+ RTW_ERR(FUNC_ADPT_FMT ": Not implemented yet!!\n", FUNC_ADPT_ARG(a));
+ rtw_warn_on(1);
+#endif /* !RTW_HALMAC */
}
-
void hw_var_port_switch(_adapter *adapter)
{
#ifdef CONFIG_CONCURRENT_MODE
@@ -2581,9 +3362,191 @@ const char *const _h2c_msr_role_str[] = {
"GO",
"TDLS",
"ADHOC",
+ "MESH",
"INVALID",
};
+#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
+s32 rtw_hal_set_default_port_id_cmd(_adapter *adapter, u8 mac_id)
+{
+ s32 ret = _SUCCESS;
+ u8 parm[H2C_DEFAULT_PORT_ID_LEN] = {0};
+ struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+
+ SET_H2CCMD_DFTPID_PORT_ID(parm, adapter->hw_port);
+ SET_H2CCMD_DFTPID_MAC_ID(parm, mac_id);
+
+ RTW_DBG_DUMP("DFT port id parm:", parm, H2C_DEFAULT_PORT_ID_LEN);
+ RTW_INFO("%s port_id :%d, mad_id:%d\n", __func__, adapter->hw_port, mac_id);
+
+ ret = rtw_hal_fill_h2c_cmd(adapter, H2C_DEFAULT_PORT_ID, H2C_DEFAULT_PORT_ID_LEN, parm);
+ dvobj->default_port_id = adapter->hw_port;
+
+ return ret;
+}
+s32 rtw_set_default_port_id(_adapter *adapter)
+{
+ s32 ret = _SUCCESS;
+ struct sta_info *psta;
+ struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
+ struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+
+ if (adapter->hw_port == dvobj->default_port_id)
+ return ret;
+
+ if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) {
+ psta = rtw_get_stainfo(&adapter->stapriv, get_bssid(pmlmepriv));
+ if (psta)
+ ret = rtw_hal_set_default_port_id_cmd(adapter, psta->cmn.mac_id);
+ } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) {
+
+ } else {
+ }
+
+ return ret;
+}
+s32 rtw_set_ps_rsvd_page(_adapter *adapter)
+{
+ s32 ret = _SUCCESS;
+ u16 media_status_rpt = RT_MEDIA_CONNECT;
+ struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+
+ if (adapter->hw_port == dvobj->default_port_id)
+ return ret;
+
+ rtw_hal_set_hwreg(adapter, HW_VAR_H2C_FW_JOINBSSRPT,
+ (u8 *)&media_status_rpt);
+
+ return ret;
+}
+
+#endif
+
+#ifdef CONFIG_P2P_PS
+#ifdef RTW_HALMAC
+void rtw_set_p2p_ps_offload_cmd(_adapter *adapter, u8 p2p_ps_state)
+{
+ PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
+ struct wifidirect_info *pwdinfo = &adapter->wdinfo;
+ struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
+ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+ WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
+ struct sta_priv *pstapriv = &adapter->stapriv;
+ struct sta_info *psta;
+ HAL_P2P_PS_PARA p2p_ps_para;
+ int status = -1;
+ u8 i;
+
+ _rtw_memset(&p2p_ps_para, 0, sizeof(HAL_P2P_PS_PARA));
+ _rtw_memcpy((&p2p_ps_para) , &hal->p2p_ps_offload , sizeof(hal->p2p_ps_offload));
+
+ (&p2p_ps_para)->p2p_port_id = adapter->hw_port;
+ (&p2p_ps_para)->p2p_group = 0;
+ psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress);
+ if (psta) {
+ (&p2p_ps_para)->p2p_macid = psta->cmn.mac_id;
+ } else {
+ if (p2p_ps_state != P2P_PS_DISABLE) {
+ RTW_ERR("%s , psta was NULL\n", __func__);
+ return;
+ }
+ }
+
+
+ switch (p2p_ps_state) {
+ case P2P_PS_DISABLE:
+ RTW_INFO("P2P_PS_DISABLE\n");
+ _rtw_memset(&p2p_ps_para , 0, sizeof(HAL_P2P_PS_PARA));
+ break;
+
+ case P2P_PS_ENABLE:
+ RTW_INFO("P2P_PS_ENABLE\n");
+ /* update CTWindow value. */
+ if (pwdinfo->ctwindow > 0) {
+ (&p2p_ps_para)->ctwindow_en = 1;
+ (&p2p_ps_para)->ctwindow_length = pwdinfo->ctwindow;
+ /*RTW_INFO("%s , ctwindow_length = %d\n" , __func__ , (&p2p_ps_para)->ctwindow_length);*/
+ }
+
+
+ if ((pwdinfo->opp_ps == 1) || (pwdinfo->noa_num > 0)) {
+ (&p2p_ps_para)->offload_en = 1;
+ if (pwdinfo->role == P2P_ROLE_GO) {
+ (&p2p_ps_para)->role = 1;
+ (&p2p_ps_para)->all_sta_sleep = 0;
+ } else
+ (&p2p_ps_para)->role = 0;
+
+ (&p2p_ps_para)->discovery = 0;
+ }
+ /* hw only support 2 set of NoA */
+ for (i = 0; i < pwdinfo->noa_num; i++) {
+ /* To control the register setting for which NOA */
+ (&p2p_ps_para)->noa_sel = i;
+ (&p2p_ps_para)->noa_en = 1;
+ /* config P2P NoA Descriptor Register */
+ /* config NOA duration */
+ (&p2p_ps_para)->noa_duration_para = pwdinfo->noa_duration[i];
+ /* config NOA interval */
+ (&p2p_ps_para)->noa_interval_para = pwdinfo->noa_interval[i];
+ /* config NOA start time */
+ (&p2p_ps_para)->noa_start_time_para = pwdinfo->noa_start_time[i];
+ /* config NOA count */
+ (&p2p_ps_para)->noa_count_para = pwdinfo->noa_count[i];
+ /*RTW_INFO("%s , noa_duration_para = %d , noa_interval_para = %d , noa_start_time_para = %d , noa_count_para = %d\n" , __func__ ,
+ (&p2p_ps_para)->noa_duration_para , (&p2p_ps_para)->noa_interval_para ,
+ (&p2p_ps_para)->noa_start_time_para , (&p2p_ps_para)->noa_count_para);*/
+ status = rtw_halmac_p2pps(adapter_to_dvobj(adapter) , (&p2p_ps_para));
+ if (status == -1)
+ RTW_ERR("%s , rtw_halmac_p2pps fail\n", __func__);
+ }
+
+ break;
+
+ case P2P_PS_SCAN:
+ /*This feature FW not ready 20161116 YiWei*/
+ return;
+ RTW_INFO("P2P_PS_SCAN\n");
+ (&p2p_ps_para)->discovery = 1;
+ /*
+ (&p2p_ps_para)->ctwindow_length = pwdinfo->ctwindow;
+ (&p2p_ps_para)->noa_duration_para = pwdinfo->noa_duration[0];
+ (&p2p_ps_para)->noa_interval_para = pwdinfo->noa_interval[0];
+ (&p2p_ps_para)->noa_start_time_para = pwdinfo->noa_start_time[0];
+ (&p2p_ps_para)->noa_count_para = pwdinfo->noa_count[0];
+ */
+ break;
+
+ case P2P_PS_SCAN_DONE:
+ /*This feature FW not ready 20161116 YiWei*/
+ return;
+ RTW_INFO("P2P_PS_SCAN_DONE\n");
+ (&p2p_ps_para)->discovery = 0;
+ /*
+ pwdinfo->p2p_ps_state = P2P_PS_ENABLE;
+ (&p2p_ps_para)->ctwindow_length = pwdinfo->ctwindow;
+ (&p2p_ps_para)->noa_duration_para = pwdinfo->noa_duration[0];
+ (&p2p_ps_para)->noa_interval_para = pwdinfo->noa_interval[0];
+ (&p2p_ps_para)->noa_start_time_para = pwdinfo->noa_start_time[0];
+ (&p2p_ps_para)->noa_count_para = pwdinfo->noa_count[0];
+ */
+ break;
+
+ default:
+ break;
+ }
+
+ if (p2p_ps_state != P2P_PS_ENABLE || (&p2p_ps_para)->noa_en == 0) {
+ status = rtw_halmac_p2pps(adapter_to_dvobj(adapter) , (&p2p_ps_para));
+ if (status == -1)
+ RTW_ERR("%s , rtw_halmac_p2pps fail\n", __func__);
+ }
+ _rtw_memcpy(&hal->p2p_ps_offload , (&p2p_ps_para) , sizeof(hal->p2p_ps_offload));
+
+}
+#endif /* RTW_HALMAC */
+#endif /* CONFIG_P2P */
+
/*
* rtw_hal_set_FwMediaStatusRpt_cmd -
*
@@ -2610,30 +3573,15 @@ s32 rtw_hal_set_FwMediaStatusRpt_cmd(_adapter *adapter, bool opmode, bool miraca
SET_H2CCMD_MSRRPT_PARM_ROLE(parm, role);
SET_H2CCMD_MSRRPT_PARM_MACID(parm, macid);
SET_H2CCMD_MSRRPT_PARM_MACID_END(parm, macid_end);
-
- RTW_DBG_DUMP("MediaStatusRpt parm:", parm, H2C_MEDIA_STATUS_RPT_LEN);
-
-#ifdef CONFIG_DFS_MASTER
- /* workaround for TXPAUSE cleared issue by FW's MediaStatusRpt handling */
- if (macid_ind == 0 && macid == 1) {
- u8 parm0_bak = parm[0];
-
- SET_H2CCMD_MSRRPT_PARM_MACID_IND(&parm0_bak, 0);
- if (macid_ctl->h2c_msr[macid] == parm0_bak) {
- ret = _SUCCESS;
- goto post_action;
- }
- }
+#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
+ SET_H2CCMD_MSRRPT_PARM_PORT_NUM(parm, adapter->hw_port);
#endif
+ RTW_DBG_DUMP("MediaStatusRpt parm:", parm, H2C_MEDIA_STATUS_RPT_LEN);
ret = rtw_hal_fill_h2c_cmd(adapter, H2C_MEDIA_STATUS_RPT, H2C_MEDIA_STATUS_RPT_LEN, parm);
if (ret != _SUCCESS)
goto exit;
-#ifdef CONFIG_DFS_MASTER
-post_action:
-#endif
-
#if defined(CONFIG_RTL8188E)
if (rtw_get_chip_type(adapter) == RTL8188E) {
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
@@ -2659,8 +3607,8 @@ s32 rtw_hal_set_FwMediaStatusRpt_cmd(_adapter *adapter, bool opmode, bool miraca
#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
/* TODO: this should move to IOT issue area */
if (rtw_get_chip_type(adapter) == RTL8812
- || rtw_get_chip_type(adapter) == RTL8821
- ) {
+ || rtw_get_chip_type(adapter) == RTL8821
+ ) {
if (MLME_IS_STA(adapter))
Hal_PatchwithJaguar_8812(adapter, opmode);
}
@@ -2670,8 +3618,17 @@ s32 rtw_hal_set_FwMediaStatusRpt_cmd(_adapter *adapter, bool opmode, bool miraca
if (macid_ind == 0)
macid_end = macid;
- for (i = macid; macid <= macid_end; macid++)
+ for (i = macid; macid <= macid_end; macid++) {
rtw_macid_ctl_set_h2c_msr(macid_ctl, macid, parm[0]);
+ if (!opmode) {
+ rtw_macid_ctl_set_bw(macid_ctl, macid, CHANNEL_WIDTH_20);
+ rtw_macid_ctl_set_vht_en(macid_ctl, macid, 0);
+ rtw_macid_ctl_set_rate_bmp0(macid_ctl, macid, 0);
+ rtw_macid_ctl_set_rate_bmp1(macid_ctl, macid, 0);
+ }
+ }
+ if (!opmode)
+ rtw_update_tx_rate_bmp(adapter_to_dvobj(adapter));
exit:
return ret;
@@ -2689,7 +3646,7 @@ inline s32 rtw_hal_set_FwMediaStatusRpt_range_cmd(_adapter *adapter, bool opmode
void rtw_hal_set_FwRsvdPage_cmd(PADAPTER padapter, PRSVDPAGE_LOC rsvdpageloc)
{
- struct hal_ops *pHalFunc = &padapter->HalFunc;
+ struct hal_ops *pHalFunc = &padapter->hal_func;
u8 u1H2CRsvdPageParm[H2C_RSVDPAGE_LOC_LEN] = {0};
u8 ret = 0;
@@ -2714,13 +3671,23 @@ void rtw_hal_set_FwRsvdPage_cmd(PADAPTER padapter, PRSVDPAGE_LOC rsvdpageloc)
#ifdef CONFIG_GPIO_WAKEUP
void rtw_hal_switch_gpio_wl_ctrl(_adapter *padapter, u8 index, u8 enable)
{
+ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
+
+ if (IS_8723D_SERIES(pHalData->version_id) || IS_8822B_SERIES(pHalData->version_id))
+ rtw_hal_set_hwreg(padapter, HW_SET_GPIO_WL_CTRL, (u8 *)(&enable));
/*
* Switch GPIO_13, GPIO_14 to wlan control, or pull GPIO_13,14 MUST fail.
* It happended at 8723B/8192E/8821A. New IC will check multi function GPIO,
* and implement HAL function.
* TODO: GPIO_8 multi function?
*/
- if (index == 13 || index == 14)
+
+ if ((index == 13 || index == 14)
+ #if defined(CONFIG_RTL8821A) && defined(CONFIG_SDIO_HCI)
+ /* 8821A's LED2 circuit(used by HW_LED strategy) needs enable WL GPIO control of GPIO[14:13], can't disable */
+ && (!IS_HW_LED_STRATEGY(rtw_led_get_strategy(padapter)) || enable)
+ #endif
+ )
rtw_hal_set_hwreg(padapter, HW_SET_GPIO_WL_CTRL, (u8 *)(&enable));
}
@@ -2776,41 +3743,91 @@ void rtw_hal_set_output_gpio(_adapter *padapter, u8 index, u8 outputval)
__FUNCTION__, index, outputval);
}
}
+void rtw_hal_set_input_gpio(_adapter *padapter, u8 index)
+{
+ if (index <= 7) {
+ /* config GPIO mode */
+ rtw_write8(padapter, REG_GPIO_PIN_CTRL + 3,
+ rtw_read8(padapter, REG_GPIO_PIN_CTRL + 3) & ~BIT(index));
+
+ /* config GPIO Sel */
+ /* 0: input */
+ /* 1: output */
+ rtw_write8(padapter, REG_GPIO_PIN_CTRL + 2,
+ rtw_read8(padapter, REG_GPIO_PIN_CTRL + 2) & ~BIT(index));
+
+ } else if (index <= 15) {
+ /* 88C Series: */
+ /* index: 11~8 transform to 3~0 */
+ /* 8723 Series: */
+ /* index: 12~8 transform to 4~0 */
+
+ index -= 8;
+
+ /* config GPIO mode */
+ rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 3,
+ rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 3) & ~BIT(index));
+
+ /* config GPIO Sel */
+ /* 0: input */
+ /* 1: output */
+ rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 2,
+ rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 2) & ~BIT(index));
+ } else
+ RTW_INFO("%s: invalid GPIO%d\n", __func__, index);
+
+}
+
#endif
void rtw_hal_set_FwAoacRsvdPage_cmd(PADAPTER padapter, PRSVDPAGE_LOC rsvdpageloc)
{
- struct hal_ops *pHalFunc = &padapter->HalFunc;
+ struct hal_ops *pHalFunc = &padapter->hal_func;
struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
u8 res = 0, count = 0, ret = 0;
#ifdef CONFIG_WOWLAN
u8 u1H2CAoacRsvdPageParm[H2C_AOAC_RSVDPAGE_LOC_LEN] = {0};
- RTW_INFO("AOACRsvdPageLoc: RWC=%d ArpRsp=%d NbrAdv=%d GtkRsp=%d GtkInfo=%d ProbeReq=%d NetworkList=%d\n",
- rsvdpageloc->LocRemoteCtrlInfo, rsvdpageloc->LocArpRsp,
- rsvdpageloc->LocNbrAdv, rsvdpageloc->LocGTKRsp,
- rsvdpageloc->LocGTKInfo, rsvdpageloc->LocProbeReq,
- rsvdpageloc->LocNetList);
+ RTW_INFO("%s: RWC: %d ArpRsp: %d NbrAdv: %d LocNDPInfo: %d\n",
+ __func__, rsvdpageloc->LocRemoteCtrlInfo,
+ rsvdpageloc->LocArpRsp, rsvdpageloc->LocNbrAdv,
+ rsvdpageloc->LocNDPInfo);
+ RTW_INFO("%s:GtkRsp: %d GtkInfo: %d ProbeReq: %d NetworkList: %d\n",
+ __func__, rsvdpageloc->LocGTKRsp, rsvdpageloc->LocGTKInfo,
+ rsvdpageloc->LocProbeReq, rsvdpageloc->LocNetList);
if (check_fwstate(pmlmepriv, _FW_LINKED)) {
SET_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(u1H2CAoacRsvdPageParm, rsvdpageloc->LocRemoteCtrlInfo);
SET_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(u1H2CAoacRsvdPageParm, rsvdpageloc->LocArpRsp);
- /* SET_H2CCMD_AOAC_RSVDPAGE_LOC_NEIGHBOR_ADV(u1H2CAoacRsvdPageParm, rsvdpageloc->LocNbrAdv); */
+ SET_H2CCMD_AOAC_RSVDPAGE_LOC_NEIGHBOR_ADV(u1H2CAoacRsvdPageParm,
+ rsvdpageloc->LocNbrAdv);
+ SET_H2CCMD_AOAC_RSVDPAGE_LOC_NDP_INFO(u1H2CAoacRsvdPageParm,
+ rsvdpageloc->LocNDPInfo);
+#ifdef CONFIG_GTK_OL
SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_RSP(u1H2CAoacRsvdPageParm, rsvdpageloc->LocGTKRsp);
SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_INFO(u1H2CAoacRsvdPageParm, rsvdpageloc->LocGTKInfo);
-#ifdef CONFIG_GTK_OL
SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_EXT_MEM(u1H2CAoacRsvdPageParm, rsvdpageloc->LocGTKEXTMEM);
#endif /* CONFIG_GTK_OL */
ret = rtw_hal_fill_h2c_cmd(padapter,
H2C_AOAC_RSVD_PAGE,
H2C_AOAC_RSVDPAGE_LOC_LEN,
u1H2CAoacRsvdPageParm);
+
+ RTW_INFO("AOAC Report=%d\n", rsvdpageloc->LocAOACReport);
+ _rtw_memset(&u1H2CAoacRsvdPageParm, 0, sizeof(u1H2CAoacRsvdPageParm));
+ SET_H2CCMD_AOAC_RSVDPAGE_LOC_AOAC_REPORT(u1H2CAoacRsvdPageParm,
+ rsvdpageloc->LocAOACReport);
+ ret = rtw_hal_fill_h2c_cmd(padapter,
+ H2C_AOAC_RSVDPAGE3,
+ H2C_AOAC_RSVDPAGE_LOC_LEN,
+ u1H2CAoacRsvdPageParm);
+ pwrpriv->wowlan_aoac_rpt_loc = rsvdpageloc->LocAOACReport;
}
#ifdef CONFIG_PNO_SUPPORT
else {
- if (!pwrpriv->pno_in_resume) {
+ if (!pwrpriv->wowlan_in_resume) {
RTW_INFO("NLO_INFO=%d\n", rsvdpageloc->LocPNOInfo);
_rtw_memset(&u1H2CAoacRsvdPageParm, 0,
sizeof(u1H2CAoacRsvdPageParm));
@@ -2826,17 +3843,156 @@ void rtw_hal_set_FwAoacRsvdPage_cmd(PADAPTER padapter, PRSVDPAGE_LOC rsvdpageloc
#endif /* CONFIG_WOWLAN */
}
-#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
-static void rtw_hal_force_enable_rxdma(_adapter *adapter)
+#ifdef DBG_FW_DEBUG_MSG_PKT
+void rtw_hal_set_fw_dbg_msg_pkt_rsvd_page_cmd(PADAPTER padapter, PRSVDPAGE_LOC rsvdpageloc)
{
- RTW_INFO("%s: Set 0x690=0x00\n", __func__);
- rtw_write8(adapter, REG_WOW_CTRL,
- (rtw_read8(adapter, REG_WOW_CTRL) & 0xf0));
- RTW_PRINT("%s: Release RXDMA\n", __func__);
- rtw_write32(adapter, REG_RXPKT_NUM,
- (rtw_read32(adapter, REG_RXPKT_NUM) & (~RW_RELEASE_EN)));
-}
+ struct hal_ops *pHalFunc = &padapter->hal_func;
+ u8 u1H2C_fw_dbg_msg_pkt_parm[H2C_FW_DBG_MSG_PKT_LEN] = {0};
+ u8 ret = 0;
+
+
+ RTW_INFO("RsvdPageLoc: loc_fw_dbg_msg_pkt =%d\n", rsvdpageloc->loc_fw_dbg_msg_pkt);
+
+ SET_H2CCMD_FW_DBG_MSG_PKT_EN(u1H2C_fw_dbg_msg_pkt_parm, 1);
+ SET_H2CCMD_RSVDPAGE_LOC_FW_DBG_MSG_PKT(u1H2C_fw_dbg_msg_pkt_parm, rsvdpageloc->loc_fw_dbg_msg_pkt);
+ ret = rtw_hal_fill_h2c_cmd(padapter,
+ H2C_FW_DBG_MSG_PKT,
+ H2C_FW_DBG_MSG_PKT_LEN,
+ u1H2C_fw_dbg_msg_pkt_parm);
+
+}
+#endif /*DBG_FW_DEBUG_MSG_PKT*/
+
+/*#define DBG_GET_RSVD_PAGE*/
+int rtw_hal_get_rsvd_page(_adapter *adapter, u32 page_offset,
+ u32 page_num, u8 *buffer, u32 buffer_size)
+{
+ u32 addr = 0, size = 0, count = 0;
+ u32 page_size = 0, data_low = 0, data_high = 0;
+ u16 txbndy = 0, offset = 0;
+ u8 i = 0;
+ bool rst = _FALSE;
+
+ rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, &page_size);
+
+ addr = page_offset * page_size;
+ size = page_num * page_size;
+
+ if (buffer_size < size) {
+ RTW_ERR("%s buffer_size(%d) < get page total size(%d)\n",
+ __func__, buffer_size, size);
+ return rst;
+ }
+#ifdef RTW_HALMAC
+ if (rtw_halmac_dump_fifo(adapter_to_dvobj(adapter), 2, addr, size, buffer) < 0)
+ rst = _FALSE;
+ else
+ rst = _TRUE;
+#else
+ txbndy = rtw_read8(adapter, REG_TDECTRL + 1);
+
+ offset = (txbndy + page_offset) * page_size / 8;
+ count = (buffer_size / 8) + 1;
+
+ rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, 0x69);
+
+ for (i = 0 ; i < count ; i++) {
+ rtw_write32(adapter, REG_PKTBUF_DBG_CTRL, offset + i);
+ data_low = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_L);
+ data_high = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H);
+ _rtw_memcpy(buffer + (i * 8),
+ &data_low, sizeof(data_low));
+ _rtw_memcpy(buffer + ((i * 8) + 4),
+ &data_high, sizeof(data_high));
+ }
+ rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, 0x0);
+ rst = _TRUE;
+#endif /*RTW_HALMAC*/
+
+#ifdef DBG_GET_RSVD_PAGE
+ RTW_INFO("%s [page_offset:%d , page_num:%d][start_addr:0x%04x , size:%d]\n",
+ __func__, page_offset, page_num, addr, size);
+ RTW_INFO_DUMP("\n", buffer, size);
+ RTW_INFO(" ==================================================\n");
+#endif
+ return rst;
+}
+
+void rtw_dump_rsvd_page(void *sel, _adapter *adapter, u8 page_offset, u8 page_num)
+{
+ u32 page_size = 0;
+ u8 *buffer = NULL;
+ u32 buf_size = 0;
+
+ if (page_num == 0)
+ return;
+
+ RTW_PRINT_SEL(sel, "======= RSVD PAGE DUMP =======\n");
+ RTW_PRINT_SEL(sel, "page_offset:%d, page_num:%d\n", page_offset, page_num);
+
+ rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, &page_size);
+ if (page_size) {
+ buf_size = page_size * page_num;
+ buffer = rtw_zvmalloc(buf_size);
+
+ if (buffer) {
+ rtw_hal_get_rsvd_page(adapter, page_offset, page_num, buffer, buf_size);
+ RTW_DUMP_SEL(sel, buffer, buf_size);
+ rtw_vmfree(buffer, buf_size);
+ } else
+ RTW_PRINT_SEL(sel, "ERROR - rsvd_buf mem allocate failed\n");
+ } else
+ RTW_PRINT_SEL(sel, "ERROR - Tx page size is zero ??\n");
+
+ RTW_PRINT_SEL(sel, "==========================\n");
+}
+
+#ifdef CONFIG_SUPPORT_FIFO_DUMP
+void rtw_dump_fifo(void *sel, _adapter *adapter, u8 fifo_sel, u32 fifo_addr, u32 fifo_size)
+{
+ u8 *buffer = NULL;
+ u8 buff_size = 0;
+ static const char * const fifo_sel_str[] = {
+ "TX", "RX", "RSVD_PAGE", "REPORT", "LLT", "RXBUF_FW"
+ };
+
+ if (fifo_sel > 5) {
+ RTW_ERR("fifo_sel:%d invalid\n", fifo_sel);
+ return;
+ }
+
+ RTW_PRINT_SEL(sel, "========= FIFO DUMP =========\n");
+ RTW_PRINT_SEL(sel, "%s FIFO DUMP [start_addr:0x%04x , size:%d]\n", fifo_sel_str[fifo_sel], fifo_addr, fifo_size);
+
+ if (fifo_size) {
+ buff_size = RND4(fifo_size);
+ buffer = rtw_zvmalloc(buff_size);
+ if (buffer == NULL)
+ buff_size = 0;
+ }
+
+ rtw_halmac_dump_fifo(adapter_to_dvobj(adapter), fifo_sel, fifo_addr, buff_size, buffer);
+
+ if (buffer) {
+ RTW_DUMP_SEL(sel, buffer, fifo_size);
+ rtw_vmfree(buffer, buff_size);
+ }
+ RTW_PRINT_SEL(sel, "==========================\n");
+}
+#endif
+
+#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
+static void rtw_hal_force_enable_rxdma(_adapter *adapter)
+{
+ RTW_INFO("%s: Set 0x690=0x00\n", __func__);
+ rtw_write8(adapter, REG_WOW_CTRL,
+ (rtw_read8(adapter, REG_WOW_CTRL) & 0xf0));
+ RTW_PRINT("%s: Release RXDMA\n", __func__);
+ rtw_write32(adapter, REG_RXPKT_NUM,
+ (rtw_read32(adapter, REG_RXPKT_NUM) & (~RW_RELEASE_EN)));
+}
+#if defined(CONFIG_RTL8188E)
static void rtw_hal_disable_tx_report(_adapter *adapter)
{
rtw_write8(adapter, REG_TX_RPT_CTRL,
@@ -2850,7 +4006,7 @@ static void rtw_hal_enable_tx_report(_adapter *adapter)
((rtw_read8(adapter, REG_TX_RPT_CTRL) | BIT(1))) | BIT(5));
RTW_INFO("enable TX_RPT:0x%02x\n", rtw_read8(adapter, REG_TX_RPT_CTRL));
}
-
+#endif
static void rtw_hal_release_rx_dma(_adapter *adapter)
{
u32 val32 = 0;
@@ -2865,9 +4021,9 @@ static void rtw_hal_release_rx_dma(_adapter *adapter)
static u8 rtw_hal_pause_rx_dma(_adapter *adapter)
{
+ PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
u8 ret = 0;
s8 trycnt = 100;
- u16 len = 0;
u32 tmp = 0;
int res = 0;
/* RX DMA stop */
@@ -2876,47 +4032,42 @@ static u8 rtw_hal_pause_rx_dma(_adapter *adapter)
(rtw_read32(adapter, REG_RXPKT_NUM) | RW_RELEASE_EN));
do {
if ((rtw_read32(adapter, REG_RXPKT_NUM) & RXDMA_IDLE)) {
+#ifdef CONFIG_USB_HCI
+ /* stop interface before leave */
+ if (_TRUE == hal->usb_intf_start) {
+ rtw_intf_stop(adapter);
+ RTW_ENABLE_FUNC(adapter, DF_RX_BIT);
+ RTW_ENABLE_FUNC(adapter, DF_TX_BIT);
+ }
+#endif /* CONFIG_USB_HCI */
+
RTW_PRINT("RX_DMA_IDLE is true\n");
ret = _SUCCESS;
break;
}
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
else {
- /* If RX_DMA is not idle, receive one pkt from DMA */
- res = sdio_local_read(adapter,
- SDIO_REG_RX0_REQ_LEN, 4, (u8 *)&tmp);
- len = le16_to_cpu(tmp);
- RTW_PRINT("RX len:%d\n", len);
-
- if (len > 0)
- res = RecvOnePkt(adapter, len);
- else
- RTW_PRINT("read length fail %d\n", len);
-
+ res = RecvOnePkt(adapter);
RTW_PRINT("RecvOnePkt Result: %d\n", res);
}
#endif /* CONFIG_SDIO_HCI || CONFIG_GSPI_HCI */
+
#ifdef CONFIG_USB_HCI
else {
- rtw_intf_start(adapter);
-
- tmp = rtw_read32(adapter, REG_RXPKT_NUM) & RXDMA_IDLE;
- if (tmp) {
- rtw_intf_stop(adapter);
- RTW_ENABLE_FUNC(adapter, DF_RX_BIT);
- RTW_ENABLE_FUNC(adapter, DF_TX_BIT);
- }
+ /* to avoid interface start repeatedly */
+ if (_FALSE == hal->usb_intf_start)
+ rtw_intf_start(adapter);
}
-#endif
+#endif /* CONFIG_USB_HCI */
} while (trycnt--);
if (trycnt < 0) {
- tmp = rtw_read16(adapter, REG_RXPKT_NUM + 3);
+ tmp = rtw_read16(adapter, REG_RXPKT_NUM + 2);
RTW_PRINT("Stop RX DMA failed......\n");
- RTW_PRINT("%s, RXPKT_NUM: 0x%04x\n",
- __func__, tmp);
- tmp = rtw_read16(adapter, REG_RXPKT_NUM + 2);
+ RTW_PRINT("%s, RXPKT_NUM: 0x%02x\n",
+ __func__, ((tmp & 0xFF00) >> 8));
+
if (tmp & BIT(3))
RTW_PRINT("%s, RX DMA has req\n",
__func__);
@@ -2930,12 +4081,15 @@ static u8 rtw_hal_pause_rx_dma(_adapter *adapter)
}
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
+#ifndef RTW_HALMAC
static u8 rtw_hal_enable_cpwm2(_adapter *adapter)
{
u8 ret = 0;
int res = 0;
u32 tmp = 0;
-
+#ifdef CONFIG_GPIO_WAKEUP
+ return _SUCCESS;
+#else
RTW_PRINT("%s\n", __func__);
res = sdio_local_read(adapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
@@ -2956,53 +4110,98 @@ static u8 rtw_hal_enable_cpwm2(_adapter *adapter)
RTW_INFO("sdio_local_write fail\n");
ret = _FAIL;
}
-
return ret;
+#endif /* CONFIG_CPIO_WAKEUP */
}
+#endif
#endif /* CONFIG_SDIO_HCI, CONFIG_GSPI_HCI */
#endif /* CONFIG_WOWLAN || CONFIG_AP_WOWLAN */
#ifdef CONFIG_WOWLAN
/*
* rtw_hal_check_wow_ctrl
- * chk_type: _TRUE means to check enable, if 0x690 & bit1, WOW enable successful
- * _FALSE means to check disable, if 0x690 & bit1, WOW disable fail
+ * chk_type: _TRUE means to check enable, if 0x690 & bit1 (for 8051), WOW enable successful.
+ * If 0x1C7 == 0 (for 3081), WOW enable successful.
+ * _FALSE means to check disable, if 0x690 & bit1 (for 8051), WOW disable fail.
+ * If 0x120 & bit16 || 0x284 & bit18 (for 3081), WOW disable fail.
*/
static u8 rtw_hal_check_wow_ctrl(_adapter *adapter, u8 chk_type)
{
+ u32 fe1_imr = 0xFF, rxpkt_num = 0xFF;
u8 mstatus = 0;
+ u8 reason = 0xFF;
u8 trycnt = 25;
u8 res = _FALSE;
- mstatus = rtw_read8(adapter, REG_WOW_CTRL);
- RTW_INFO("%s mstatus:0x%02x\n", __func__, mstatus);
+ if (IS_HARDWARE_TYPE_JAGUAR2(adapter)) {
+ if (chk_type) {
+ reason = rtw_read8(adapter, REG_WOWLAN_WAKE_REASON);
+ RTW_INFO("%s reason:0x%02x\n", __func__, reason);
+
+ while (reason && trycnt > 1) {
+ reason = rtw_read8(adapter, REG_WOWLAN_WAKE_REASON);
+ RTW_PRINT("Loop index: %d :0x%02x\n",
+ trycnt, reason);
+ trycnt--;
+ rtw_msleep_os(20);
+ }
+ if (!reason)
+ res = _TRUE;
+ else
+ res = _FALSE;
+ } else {
+ /* Wait FW to cleare 0x120 bit16, 0x284 bit18 to 0 */
+ fe1_imr = rtw_read32(adapter, REG_FE1IMR); /* RxDone IMR for 3081 */
+ rxpkt_num = rtw_read32(adapter, REG_RXPKT_NUM); /* Release RXDMA */
+ RTW_PRINT("%s REG_FE1IMR (reg120): 0x%x, REG_RXPKT_NUM(reg284): 0x%x\n", __func__, fe1_imr, rxpkt_num);
+
+ while (((fe1_imr & BIT_FS_RXDONE_INT_EN) || (rxpkt_num & BIT_RW_RELEASE_EN)) && trycnt > 1) {
+ rtw_msleep_os(20);
+ fe1_imr = rtw_read32(adapter, REG_FE1IMR);
+ rxpkt_num = rtw_read32(adapter, REG_RXPKT_NUM);
+ RTW_PRINT("Loop index: %d :0x%x, 0x%x\n",
+ trycnt, fe1_imr, rxpkt_num);
+ trycnt--;
+ }
- if (chk_type) {
- while (!(mstatus & BIT1) && trycnt > 1) {
- mstatus = rtw_read8(adapter, REG_WOW_CTRL);
- RTW_PRINT("Loop index: %d :0x%02x\n",
- trycnt, mstatus);
- trycnt--;
- rtw_msleep_os(20);
+ if ((fe1_imr & BIT_FS_RXDONE_INT_EN) || (rxpkt_num & BIT_RW_RELEASE_EN))
+ res = _FALSE;
+ else
+ res = _TRUE;
}
- if (mstatus & BIT1)
- res = _TRUE;
- else
- res = _FALSE;
} else {
- while (mstatus & BIT1 && trycnt > 1) {
- mstatus = rtw_read8(adapter, REG_WOW_CTRL);
- RTW_PRINT("Loop index: %d :0x%02x\n",
- trycnt, mstatus);
- trycnt--;
- rtw_msleep_os(20);
- }
+ mstatus = rtw_read8(adapter, REG_WOW_CTRL);
+ RTW_INFO("%s mstatus:0x%02x\n", __func__, mstatus);
- if (mstatus & BIT1)
- res = _FALSE;
- else
- res = _TRUE;
+
+ if (chk_type) {
+ while (!(mstatus & BIT1) && trycnt > 1) {
+ mstatus = rtw_read8(adapter, REG_WOW_CTRL);
+ RTW_PRINT("Loop index: %d :0x%02x\n",
+ trycnt, mstatus);
+ trycnt--;
+ rtw_msleep_os(20);
+ }
+ if (mstatus & BIT1)
+ res = _TRUE;
+ else
+ res = _FALSE;
+ } else {
+ while (mstatus & BIT1 && trycnt > 1) {
+ mstatus = rtw_read8(adapter, REG_WOW_CTRL);
+ RTW_PRINT("Loop index: %d :0x%02x\n",
+ trycnt, mstatus);
+ trycnt--;
+ rtw_msleep_os(20);
+ }
+
+ if (mstatus & BIT1)
+ res = _FALSE;
+ else
+ res = _TRUE;
+ }
}
+
RTW_PRINT("%s check_type: %d res: %d trycnt: %d\n",
__func__, chk_type, res, (25 - trycnt));
return res;
@@ -3015,7 +4214,7 @@ static u8 rtw_hal_check_pno_enabled(_adapter *adapter)
u8 res = 0, count = 0;
u8 ret = _FALSE;
- if (ppwrpriv->wowlan_pno_enable && ppwrpriv->pno_in_resume == _FALSE) {
+ if (ppwrpriv->wowlan_pno_enable && ppwrpriv->wowlan_in_resume == _FALSE) {
res = rtw_read8(adapter, REG_PNO_STATUS);
while (!(res & BIT(7)) && count < 25) {
RTW_INFO("[%d] cmd: 0x81 REG_PNO_STATUS: 0x%02x\n",
@@ -3051,7 +4250,7 @@ static void rtw_hal_fw_sync_cam_id(_adapter *adapter)
int cam_id, index = 0;
u8 *addr = NULL;
- if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
+ if (!MLME_IS_STA(adapter))
return;
addr = get_bssid(pmlmepriv);
@@ -3076,87 +4275,249 @@ static void rtw_hal_fw_sync_cam_id(_adapter *adapter)
rtw_write8(adapter, REG_SECCFG, 0xcc);
}
+
static void rtw_hal_update_gtk_offload_info(_adapter *adapter)
{
+ struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
+ struct aoac_report *paoac_rpt = &pwrctl->wowlan_aoac_rpt;
struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
struct security_priv *psecuritypriv = &adapter->securitypriv;
struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
_irqL irqL;
u8 get_key[16];
- u8 gtk_keyindex = 0;
+ u8 gtk_id = 0, offset = 0, i = 0, sz = 0;
+ u64 replay_count = 0, tmp_iv_hdr = 0, pkt_pn = 0;
- if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
+ if (!MLME_IS_STA(adapter))
return;
_rtw_memset(get_key, 0, sizeof(get_key));
+ _rtw_memcpy(&replay_count,
+ paoac_rpt->replay_counter_eapol_key, 8);
- if (psecuritypriv->binstallKCK_KEK == _TRUE) {
+ /*read gtk key index*/
+ gtk_id = paoac_rpt->key_index;
- /*read gtk key index*/
- gtk_keyindex = rtw_read8(adapter, 0x48c);
+ if (gtk_id == 5 || gtk_id == 0) {
+ RTW_INFO("%s no rekey event happened.\n", __func__);
+ } else if (gtk_id > 0 && gtk_id < 4) {
+ RTW_INFO("%s update security key.\n", __func__);
+ /*read key from sec-cam,for DK ,keyindex is equal to cam-id*/
+ rtw_sec_read_cam_ent(adapter, gtk_id,
+ NULL, NULL, get_key);
+ rtw_clean_hw_dk_cam(adapter);
+
+ if (_rtw_camid_is_gk(adapter, gtk_id)) {
+ _enter_critical_bh(&cam_ctl->lock, &irqL);
+ _rtw_memcpy(&dvobj->cam_cache[gtk_id].key,
+ get_key, 16);
+ _exit_critical_bh(&cam_ctl->lock, &irqL);
+ } else {
+ struct setkey_parm parm_gtk;
- if (gtk_keyindex > 4) {
- RTW_INFO("%s [ERROR] gtk_keyindex:%d invalid\n", __func__, gtk_keyindex);
- rtw_warn_on(1);
- return;
+ parm_gtk.algorithm = paoac_rpt->security_type;
+ parm_gtk.keyid = gtk_id;
+ _rtw_memcpy(parm_gtk.key, get_key, 16);
+ setkey_hdl(adapter, (u8 *)&parm_gtk);
}
- /*read key from sec-cam,for DK ,keyindex is equal to cam-id*/
- rtw_sec_read_cam_ent(adapter, gtk_keyindex, NULL, NULL, get_key);
-
- /*update key into related sw variable*/
- _enter_critical_bh(&cam_ctl->lock, &irqL);
- if (_rtw_camid_is_gk(adapter, gtk_keyindex)) {
- psecuritypriv->dot118021XGrpKeyid = gtk_keyindex;
- _rtw_memcpy(psecuritypriv->dot118021XGrpKey[gtk_keyindex].skey, get_key, 16);
- _rtw_memcpy(&dvobj->cam_cache[gtk_keyindex].key, get_key, 16);
+
+ /*update key into related sw variable and sec-cam cache*/
+ psecuritypriv->dot118021XGrpKeyid = gtk_id;
+ _rtw_memcpy(&psecuritypriv->dot118021XGrpKey[gtk_id],
+ get_key, 16);
+ /* update SW TKIP TX/RX MIC value */
+ if (psecuritypriv->dot118021XGrpPrivacy == _TKIP_) {
+ offset = RTW_KEK_LEN + RTW_TKIP_MIC_LEN;
+ _rtw_memcpy(
+ &psecuritypriv->dot118021XGrptxmickey[gtk_id],
+ &(paoac_rpt->group_key[offset]),
+ RTW_TKIP_MIC_LEN);
+
+ offset = RTW_KEK_LEN;
+ _rtw_memcpy(
+ &psecuritypriv->dot118021XGrprxmickey[gtk_id],
+ &(paoac_rpt->group_key[offset]),
+ RTW_TKIP_MIC_LEN);
}
- _exit_critical_bh(&cam_ctl->lock, &irqL);
+ RTW_PRINT("GTK (%d) "KEY_FMT"\n", gtk_id,
+ KEY_ARG(psecuritypriv->dot118021XGrpKey[gtk_id].skey));
+ }
+
+ /* Update broadcast RX IV */
+ if (psecuritypriv->dot118021XGrpPrivacy == _AES_) {
+ sz = sizeof(psecuritypriv->iv_seq[0]);
+ for (i = 0 ; i < 4 ; i++) {
+ _rtw_memcpy(&tmp_iv_hdr, paoac_rpt->rxgtk_iv[i], sz);
+ tmp_iv_hdr = le64_to_cpu(tmp_iv_hdr);
+ pkt_pn = CCMPH_2_PN(tmp_iv_hdr);
+ _rtw_memcpy(psecuritypriv->iv_seq[i], &pkt_pn, sz);
+ }
+ }
- RTW_PRINT("GTK (%d) "KEY_FMT"\n",
- gtk_keyindex,
- KEY_ARG(psecuritypriv->dot118021XGrpKey[gtk_keyindex].skey));
+ rtw_clean_dk_section(adapter);
- rtw_write8(adapter, REG_SECCFG, 0x0c);
-#ifdef CONFIG_GTK_OL_DBG
- /* if (gtk_keyindex != 5) */
- dump_sec_cam(RTW_DBGDUMP, adapter);
-#endif
+ rtw_write8(adapter, REG_SECCFG, 0x0c);
+
+ #ifdef CONFIG_GTK_OL_DBG
+ /* if (gtk_keyindex != 5) */
+ dump_sec_cam(RTW_DBGDUMP, adapter);
+ dump_sec_cam_cache(RTW_DBGDUMP, adapter);
+ #endif
+}
+#endif /*CONFIG_GTK_OL*/
+
+static void rtw_dump_aoac_rpt(_adapter *adapter)
+{
+ struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
+ struct aoac_report *paoac_rpt = &pwrctl->wowlan_aoac_rpt;
+ int i = 0;
+
+ RTW_INFO_DUMP("[AOAC-RPT] IV -", paoac_rpt->iv, 8);
+ RTW_INFO_DUMP("[AOAC-RPT] Replay counter of EAPOL key - ",
+ paoac_rpt->replay_counter_eapol_key, 8);
+ RTW_INFO_DUMP("[AOAC-RPT] Group key - ", paoac_rpt->group_key, 32);
+ RTW_INFO("[AOAC-RPT] Key Index - %d\n", paoac_rpt->key_index);
+ RTW_INFO("[AOAC-RPT] Security Type - %d\n", paoac_rpt->security_type);
+ RTW_INFO("[AOAC-RPT] wow_pattern_idx - %d\n",
+ paoac_rpt->wow_pattern_idx);
+ RTW_INFO("[AOAC-RPT] version_info - %d\n", paoac_rpt->version_info);
+ RTW_INFO_DUMP("[AOAC-RPT] RX PTK IV-", paoac_rpt->rxptk_iv, 8);
+ RTW_INFO_DUMP("[AOAC-RPT] RX GTK[0] IV-", paoac_rpt->rxgtk_iv[0], 8);
+ RTW_INFO_DUMP("[AOAC-RPT] RX GTK[1] IV-", paoac_rpt->rxgtk_iv[1], 8);
+ RTW_INFO_DUMP("[AOAC-RPT] RX GTK[2] IV-", paoac_rpt->rxgtk_iv[2], 8);
+ RTW_INFO_DUMP("[AOAC-RPT] RX GTK[3] IV-", paoac_rpt->rxgtk_iv[3], 8);
+}
+
+static void rtw_hal_get_aoac_rpt(_adapter *adapter)
+{
+ struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
+ struct aoac_report *paoac_rpt = &pwrctl->wowlan_aoac_rpt;
+ u32 page_offset = 0, page_number = 0;
+ u32 page_size = 0, buf_size = 0;
+ u8 *buffer = NULL;
+ u8 i = 0, tmp = 0;
+ int ret = -1;
+
+ /* read aoac report from rsvd page */
+ page_offset = pwrctl->wowlan_aoac_rpt_loc;
+ page_number = 1;
+
+ rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, &page_size);
+ buf_size = page_size * page_number;
+
+ buffer = rtw_zvmalloc(buf_size);
+
+ if (buffer == NULL) {
+ RTW_ERR("%s buffer allocate failed size(%d)\n",
+ __func__, buf_size);
+ return;
+ }
+
+ RTW_INFO("Get AOAC Report from rsvd page_offset:%d\n", page_offset);
+
+ ret = rtw_hal_get_rsvd_page(adapter, page_offset,
+ page_number, buffer, buf_size);
+
+ if (ret == _FALSE) {
+ RTW_ERR("%s get aoac report failed\n", __func__);
+ rtw_warn_on(1);
+ goto _exit;
}
+
+ _rtw_memset(paoac_rpt, 0, sizeof(struct aoac_report));
+ _rtw_memcpy(paoac_rpt, buffer, sizeof(struct aoac_report));
+
+ for (i = 0 ; i < 4 ; i++) {
+ tmp = paoac_rpt->replay_counter_eapol_key[i];
+ paoac_rpt->replay_counter_eapol_key[i] =
+ paoac_rpt->replay_counter_eapol_key[7 - i];
+ paoac_rpt->replay_counter_eapol_key[7 - i] = tmp;
+ }
+
+ rtw_dump_aoac_rpt(adapter);
+
+_exit:
+ if (buffer)
+ rtw_vmfree(buffer, buf_size);
}
-#endif
static void rtw_hal_update_tx_iv(_adapter *adapter)
{
struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
- u64 iv_low = 0, iv_high = 0;
-
- /* 3.1 read fw iv */
- iv_low = rtw_read32(adapter, REG_TXPKTBUF_IV_LOW);
- /* only low two bytes is PN, check AES_IV macro for detail */
- iv_low &= 0xffff;
- iv_high = rtw_read32(adapter, REG_TXPKTBUF_IV_HIGH);
- /* get the real packet number */
- pwrctl->wowlan_fw_iv = iv_high << 16 | iv_low;
- RTW_PRINT("fw_iv: 0x%016llx\n", pwrctl->wowlan_fw_iv);
+ struct aoac_report *paoac_rpt = &pwrctl->wowlan_aoac_rpt;
+ struct sta_info *psta;
+ struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
+ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+ struct security_priv *psecpriv = &adapter->securitypriv;
+
+ u16 val16 = 0;
+ u32 val32 = 0;
+ u64 txiv = 0;
+ u8 *pval = NULL;
+
+ psta = rtw_get_stainfo(&adapter->stapriv,
+ get_my_bssid(&pmlmeinfo->network));
+
/* Update TX iv data. */
- rtw_set_sec_pn(adapter);
+ pval = (u8 *)&paoac_rpt->iv;
+
+ if (psecpriv->dot11PrivacyAlgrthm == _TKIP_) {
+ val16 = ((u16)(paoac_rpt->iv[2]) << 0) +
+ ((u16)(paoac_rpt->iv[0]) << 8);
+ val32 = ((u32)(paoac_rpt->iv[4]) << 0) +
+ ((u32)(paoac_rpt->iv[5]) << 8) +
+ ((u32)(paoac_rpt->iv[6]) << 16) +
+ ((u32)(paoac_rpt->iv[7]) << 24);
+ } else if (psecpriv->dot11PrivacyAlgrthm == _AES_) {
+ val16 = ((u16)(paoac_rpt->iv[0]) << 0) +
+ ((u16)(paoac_rpt->iv[1]) << 8);
+ val32 = ((u32)(paoac_rpt->iv[4]) << 0) +
+ ((u32)(paoac_rpt->iv[5]) << 8) +
+ ((u32)(paoac_rpt->iv[6]) << 16) +
+ ((u32)(paoac_rpt->iv[7]) << 24);
+ }
+
+ if (psta) {
+ txiv = val16 + ((u64)val32 << 16);
+ if (txiv != 0)
+ psta->dot11txpn.val = txiv;
+ }
+}
+
+static void rtw_hal_update_sw_security_info(_adapter *adapter)
+{
+ struct security_priv *psecpriv = &adapter->securitypriv;
+ u8 sz = sizeof (psecpriv->iv_seq);
+
+ rtw_hal_update_tx_iv(adapter);
+#ifdef CONFIG_GTK_OL
+ if (psecpriv->binstallKCK_KEK == _TRUE &&
+ psecpriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK)
+ rtw_hal_update_gtk_offload_info(adapter);
+#else
+ _rtw_memset(psecpriv->iv_seq, 0, sz);
+#endif
}
static u8 rtw_hal_set_keep_alive_cmd(_adapter *adapter, u8 enable, u8 pkt_type)
{
- struct hal_ops *pHalFunc = &adapter->HalFunc;
+ struct hal_ops *pHalFunc = &adapter->hal_func;
u8 u1H2CKeepAliveParm[H2C_KEEP_ALIVE_CTRL_LEN] = {0};
u8 adopt = 1, check_period = 5;
u8 ret = _FAIL;
- RTW_INFO("%s(): enable = %d\n", __func__, enable);
SET_H2CCMD_KEEPALIVE_PARM_ENABLE(u1H2CKeepAliveParm, enable);
SET_H2CCMD_KEEPALIVE_PARM_ADOPT(u1H2CKeepAliveParm, adopt);
SET_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(u1H2CKeepAliveParm, pkt_type);
SET_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(u1H2CKeepAliveParm, check_period);
-
+#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
+ SET_H2CCMD_KEEPALIVE_PARM_PORT_NUM(u1H2CKeepAliveParm, adapter->hw_port);
+ RTW_INFO("%s(): enable = %d, port = %d\n", __func__, enable, adapter->hw_port);
+#else
+ RTW_INFO("%s(): enable = %d\n", __func__, enable);
+#endif
ret = rtw_hal_fill_h2c_cmd(adapter,
H2C_KEEP_ALIVE,
H2C_KEEP_ALIVE_CTRL_LEN,
@@ -3167,16 +4528,21 @@ static u8 rtw_hal_set_keep_alive_cmd(_adapter *adapter, u8 enable, u8 pkt_type)
static u8 rtw_hal_set_disconnect_decision_cmd(_adapter *adapter, u8 enable)
{
- struct hal_ops *pHalFunc = &adapter->HalFunc;
+ struct hal_ops *pHalFunc = &adapter->hal_func;
u8 u1H2CDisconDecisionParm[H2C_DISCON_DECISION_LEN] = {0};
- u8 adopt = 1, check_period = 10, trypkt_num = 0;
+ u8 adopt = 1, check_period = 30, trypkt_num = 5;
u8 ret = _FAIL;
- RTW_INFO("%s(): enable = %d\n", __func__, enable);
SET_H2CCMD_DISCONDECISION_PARM_ENABLE(u1H2CDisconDecisionParm, enable);
SET_H2CCMD_DISCONDECISION_PARM_ADOPT(u1H2CDisconDecisionParm, adopt);
SET_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(u1H2CDisconDecisionParm, check_period);
SET_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(u1H2CDisconDecisionParm, trypkt_num);
+#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
+ SET_H2CCMD_DISCONDECISION_PORT_NUM(u1H2CDisconDecisionParm, adapter->hw_port);
+ RTW_INFO("%s(): enable = %d, port = %d\n", __func__, enable, adapter->hw_port);
+#else
+ RTW_INFO("%s(): enable = %d\n", __func__, enable);
+#endif
ret = rtw_hal_fill_h2c_cmd(adapter,
H2C_DISCON_DECISION,
@@ -3187,18 +4553,22 @@ static u8 rtw_hal_set_disconnect_decision_cmd(_adapter *adapter, u8 enable)
static u8 rtw_hal_set_wowlan_ctrl_cmd(_adapter *adapter, u8 enable, u8 change_unit)
{
+ struct registry_priv *registry_par = &adapter->registrypriv;
struct security_priv *psecpriv = &adapter->securitypriv;
struct pwrctrl_priv *ppwrpriv = adapter_to_pwrctl(adapter);
- struct hal_ops *pHalFunc = &adapter->HalFunc;
+ struct hal_ops *pHalFunc = &adapter->hal_func;
u8 u1H2CWoWlanCtrlParm[H2C_WOWLAN_LEN] = {0};
- u8 discont_wake = 1, gpionum = 0, gpio_dur = 0;
+ u8 discont_wake = 0, gpionum = 0, gpio_dur = 0;
u8 hw_unicast = 0, gpio_pulse_cnt = 0, gpio_pulse_en = 0;
u8 sdio_wakeup_enable = 1;
u8 gpio_high_active = 0;
u8 magic_pkt = 0;
u8 gpio_unit = 0; /*0: 64ns, 1: 8ms*/
u8 ret = _FAIL;
+#ifdef CONFIG_DIS_UPHY
+ u8 dis_uphy = 0, dis_uphy_unit = 0, dis_uphy_time = 0;
+#endif /* CONFIG_DIS_UPHY */
#ifdef CONFIG_GPIO_WAKEUP
gpio_high_active = ppwrpriv->is_high_active;
@@ -3206,13 +4576,17 @@ static u8 rtw_hal_set_wowlan_ctrl_cmd(_adapter *adapter, u8 enable, u8 change_un
sdio_wakeup_enable = 0;
#endif /* CONFIG_GPIO_WAKEUP */
- if (!ppwrpriv->wowlan_pno_enable)
+ if (!ppwrpriv->wowlan_pno_enable &&
+ registry_par->wakeup_event & BIT(0))
magic_pkt = enable;
- if (psecpriv->dot11PrivacyAlgrthm == _WEP40_ || psecpriv->dot11PrivacyAlgrthm == _WEP104_)
- hw_unicast = 1;
- else
- hw_unicast = 0;
+ if ((registry_par->wakeup_event & BIT(1)) &&
+ (psecpriv->dot11PrivacyAlgrthm == _WEP40_ ||
+ psecpriv->dot11PrivacyAlgrthm == _WEP104_))
+ hw_unicast = 1;
+
+ if (registry_par->wakeup_event & BIT(2))
+ discont_wake = enable;
RTW_INFO("%s(): enable=%d change_unit=%d\n", __func__,
enable, change_unit);
@@ -3239,13 +4613,11 @@ static u8 rtw_hal_set_wowlan_ctrl_cmd(_adapter *adapter, u8 enable, u8 change_un
SET_H2CCMD_WOWLAN_GPIO_ACTIVE(u1H2CWoWlanCtrlParm, gpio_high_active);
#ifdef CONFIG_GTK_OL
- if (enable == _TRUE) {
- /* GTK rekey only for AES, if GTK rekey is TKIP, then wake up*/
- if (psecpriv->dot118021XGrpPrivacy == _AES_)
- SET_H2CCMD_WOWLAN_REKEY_WAKE_UP(u1H2CWoWlanCtrlParm, 0);
- else if (psecpriv->dot118021XGrpPrivacy == _TKIP_)
- SET_H2CCMD_WOWLAN_REKEY_WAKE_UP(u1H2CWoWlanCtrlParm, 1);
- }
+ if (psecpriv->binstallKCK_KEK == _TRUE &&
+ psecpriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK)
+ SET_H2CCMD_WOWLAN_REKEY_WAKE_UP(u1H2CWoWlanCtrlParm, 0);
+ else
+ SET_H2CCMD_WOWLAN_REKEY_WAKE_UP(u1H2CWoWlanCtrlParm, 1);
#else
SET_H2CCMD_WOWLAN_REKEY_WAKE_UP(u1H2CWoWlanCtrlParm, enable);
#endif
@@ -3259,6 +4631,26 @@ static u8 rtw_hal_set_wowlan_ctrl_cmd(_adapter *adapter, u8 enable, u8 change_un
SET_H2CCMD_WOWLAN_GPIO_PULSE_EN(u1H2CWoWlanCtrlParm, gpio_pulse_en);
SET_H2CCMD_WOWLAN_GPIO_PULSE_COUNT(u1H2CWoWlanCtrlParm, gpio_pulse_cnt);
+#ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE
+ if (enable)
+ SET_H2CCMD_WOWLAN_GPIO_INPUT_EN(u1H2CWoWlanCtrlParm, 1);
+#endif
+
+#ifdef CONFIG_DIS_UPHY
+ if (enable) {
+ dis_uphy = 1;
+ /* time unit: 0 -> ms, 1 -> 256 ms*/
+ dis_uphy_unit = 1;
+ dis_uphy_time = 0x4;
+ }
+
+ SET_H2CCMD_WOWLAN_DIS_UPHY(u1H2CWoWlanCtrlParm, dis_uphy);
+ SET_H2CCMD_WOWLAN_HOST_2_DEV(u1H2CWoWlanCtrlParm, 1);
+ SET_H2CCMD_WOWLAN_DIS_UPHY_UNIT(u1H2CWoWlanCtrlParm, dis_uphy_unit);
+ SET_H2CCMD_WOWLAN_DIS_UPHY_TIME(u1H2CWoWlanCtrlParm, dis_uphy_time);
+#endif /* CONFIG_DIS_UPHY */
+
+
ret = rtw_hal_fill_h2c_cmd(adapter,
H2C_WOWLAN,
H2C_WOWLAN_LEN,
@@ -3268,7 +4660,7 @@ static u8 rtw_hal_set_wowlan_ctrl_cmd(_adapter *adapter, u8 enable, u8 change_un
static u8 rtw_hal_set_remote_wake_ctrl_cmd(_adapter *adapter, u8 enable)
{
- struct hal_ops *pHalFunc = &adapter->HalFunc;
+ struct hal_ops *pHalFunc = &adapter->hal_func;
struct security_priv *psecuritypriv = &(adapter->securitypriv);
struct pwrctrl_priv *ppwrpriv = adapter_to_pwrctl(adapter);
struct registry_priv *pregistrypriv = &adapter->registrypriv;
@@ -3284,30 +4676,36 @@ static u8 rtw_hal_set_remote_wake_ctrl_cmd(_adapter *adapter, u8 enable)
u1H2CRemoteWakeCtrlParm, 1);
#ifdef CONFIG_GTK_OL
if (psecuritypriv->binstallKCK_KEK == _TRUE &&
- psecuritypriv->dot11PrivacyAlgrthm == _AES_) {
+ psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK) {
SET_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN(
u1H2CRemoteWakeCtrlParm, 1);
} else {
- RTW_INFO("no kck or security is not AES\n");
+ RTW_INFO("no kck kek\n");
SET_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN(
u1H2CRemoteWakeCtrlParm, 0);
}
#endif /* CONFIG_GTK_OL */
- if (pregistrypriv->default_patterns_en == _FALSE) {
- SET_H2CCMD_REMOTE_WAKE_CTRL_FW_UNICAST_EN(
- u1H2CRemoteWakeCtrlParm, enable);
- /*
- * filter NetBios name service pkt to avoid being waked-up
- * by this kind of unicast pkt this exceptional modification
- * is used for match competitor's behavior
- */
- SET_H2CCMD_REMOTE_WAKE_CTRL_NBNS_FILTER_EN(
+#ifdef CONFIG_IPV6
+ if (ppwrpriv->wowlan_ns_offload_en == _TRUE) {
+ RTW_INFO("enable NS offload\n");
+ SET_H2CCMD_REMOTE_WAKE_CTRL_NDP_OFFLOAD_EN(
u1H2CRemoteWakeCtrlParm, enable);
}
+ /*
+ * filter NetBios name service pkt to avoid being waked-up
+ * by this kind of unicast pkt this exceptional modification
+ * is used for match competitor's behavior
+ */
+
+ SET_H2CCMD_REMOTE_WAKE_CTRL_NBNS_FILTER_EN(
+ u1H2CRemoteWakeCtrlParm, enable);
+#endif /*CONFIG_IPV6*/
+
if ((psecuritypriv->dot11PrivacyAlgrthm == _AES_) ||
- (psecuritypriv->dot11PrivacyAlgrthm == _NO_PRIVACY_)) {
+ (psecuritypriv->dot11PrivacyAlgrthm == _TKIP_) ||
+ (psecuritypriv->dot11PrivacyAlgrthm == _NO_PRIVACY_)) {
SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_ACTION(
u1H2CRemoteWakeCtrlParm, 0);
} else {
@@ -3315,6 +4713,20 @@ static u8 rtw_hal_set_remote_wake_ctrl_cmd(_adapter *adapter, u8 enable)
u1H2CRemoteWakeCtrlParm, 1);
}
+ if (psecuritypriv->dot11PrivacyAlgrthm == _TKIP_ &&
+ psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK) {
+ SET_H2CCMD_REMOTE_WAKE_CTRL_TKIP_OFFLOAD_EN(
+ u1H2CRemoteWakeCtrlParm, enable);
+
+ if (IS_HARDWARE_TYPE_8188E(adapter) ||
+ IS_HARDWARE_TYPE_8812(adapter)) {
+ SET_H2CCMD_REMOTE_WAKE_CTRL_TKIP_OFFLOAD_EN(
+ u1H2CRemoteWakeCtrlParm, 0);
+ SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_ACTION(
+ u1H2CRemoteWakeCtrlParm, 1);
+ }
+ }
+
SET_H2CCMD_REMOTE_WAKE_CTRL_FW_PARSING_UNTIL_WAKEUP(
u1H2CRemoteWakeCtrlParm, 1);
}
@@ -3347,7 +4759,7 @@ static u8 rtw_hal_set_remote_wake_ctrl_cmd(_adapter *adapter, u8 enable)
static u8 rtw_hal_set_global_info_cmd(_adapter *adapter, u8 group_alg, u8 pairwise_alg)
{
- struct hal_ops *pHalFunc = &adapter->HalFunc;
+ struct hal_ops *pHalFunc = &adapter->hal_func;
u8 ret = _FAIL;
u8 u1H2CAOACGlobalInfoParm[H2C_AOAC_GLOBAL_INFO_LEN] = {0};
@@ -3371,7 +4783,7 @@ static u8 rtw_hal_set_scan_offload_info_cmd(_adapter *adapter,
PRSVDPAGE_LOC rsvdpageloc, u8 enable)
{
struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
- struct hal_ops *pHalFunc = &adapter->HalFunc;
+ struct hal_ops *pHalFunc = &adapter->hal_func;
u8 u1H2CScanOffloadInfoParm[H2C_SCAN_OFFLOAD_CTRL_LEN] = {0};
u8 res = 0, count = 0, ret = _FAIL;
@@ -3403,13 +4815,13 @@ void rtw_hal_set_fw_wow_related_cmd(_adapter *padapter, u8 enable)
struct security_priv *psecpriv = &padapter->securitypriv;
struct pwrctrl_priv *ppwrpriv = adapter_to_pwrctl(padapter);
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+ struct registry_priv *pregistry = &padapter->registrypriv;
struct sta_info *psta = NULL;
u16 media_status_rpt;
u8 pkt_type = 0;
u8 ret = _SUCCESS;
RTW_PRINT("+%s()+: enable=%d\n", __func__, enable);
- _func_enter_;
rtw_hal_set_wowlan_ctrl_cmd(padapter, enable, _FALSE);
@@ -3419,7 +4831,9 @@ void rtw_hal_set_fw_wow_related_cmd(_adapter *padapter, u8 enable)
psecpriv->dot11PrivacyAlgrthm);
if (!(ppwrpriv->wowlan_pno_enable)) {
- rtw_hal_set_disconnect_decision_cmd(padapter, enable);
+ if (pregistry->wakeup_event & BIT(2))
+ rtw_hal_set_disconnect_decision_cmd(padapter,
+ enable);
#ifdef CONFIG_ARP_KEEP_ALIVE
if ((psecpriv->dot11PrivacyAlgrthm == _WEP40_) ||
(psecpriv->dot11PrivacyAlgrthm == _WEP104_))
@@ -3446,7 +4860,6 @@ void rtw_hal_set_fw_wow_related_cmd(_adapter *padapter, u8 enable)
rtw_hal_set_remote_wake_ctrl_cmd(padapter, enable);
}
- _func_exit_;
RTW_PRINT("-%s()-\n", __func__);
}
#endif /* CONFIG_WOWLAN */
@@ -3456,7 +4869,7 @@ static u8 rtw_hal_set_ap_wowlan_ctrl_cmd(_adapter *adapter, u8 enable)
{
struct security_priv *psecpriv = &adapter->securitypriv;
struct pwrctrl_priv *ppwrpriv = adapter_to_pwrctl(adapter);
- struct hal_ops *pHalFunc = &adapter->HalFunc;
+ struct hal_ops *pHalFunc = &adapter->hal_func;
u8 u1H2CAPWoWlanCtrlParm[H2C_AP_WOW_GPIO_CTRL_LEN] = {0};
u8 gpionum = 0, gpio_dur = 0;
@@ -3494,7 +4907,7 @@ static u8 rtw_hal_set_ap_wowlan_ctrl_cmd(_adapter *adapter, u8 enable)
static u8 rtw_hal_set_ap_offload_ctrl_cmd(_adapter *adapter, u8 enable)
{
- struct hal_ops *pHalFunc = &adapter->HalFunc;
+ struct hal_ops *pHalFunc = &adapter->hal_func;
u8 u1H2CAPOffloadCtrlParm[H2C_WOWLAN_LEN] = {0};
u8 ret = _FAIL;
@@ -3512,7 +4925,7 @@ static u8 rtw_hal_set_ap_offload_ctrl_cmd(_adapter *adapter, u8 enable)
static u8 rtw_hal_set_ap_ps_cmd(_adapter *adapter, u8 enable)
{
- struct hal_ops *pHalFunc = &adapter->HalFunc;
+ struct hal_ops *pHalFunc = &adapter->hal_func;
u8 ap_ps_parm[H2C_AP_PS_LEN] = {0};
u8 ret = _FAIL;
@@ -3538,7 +4951,7 @@ static u8 rtw_hal_set_ap_ps_cmd(_adapter *adapter, u8 enable)
static void rtw_hal_set_ap_rsvdpage_loc_cmd(PADAPTER padapter,
PRSVDPAGE_LOC rsvdpageloc)
{
- struct hal_ops *pHalFunc = &padapter->HalFunc;
+ struct hal_ops *pHalFunc = &padapter->hal_func;
u8 rsvdparm[H2C_AOAC_RSVDPAGE_LOC_LEN] = {0};
u8 ret = _FAIL, header = 0;
@@ -3591,8 +5004,9 @@ static void rtw_hal_ap_wow_enable(_adapter *padapter)
struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
struct security_priv *psecuritypriv = &padapter->securitypriv;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
- struct hal_ops *pHalFunc = &padapter->HalFunc;
+ struct hal_ops *pHalFunc = &padapter->hal_func;
struct sta_info *psta = NULL;
+ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
#ifdef DBG_CHECK_FW_PS_STATE
struct dvobj_priv *psdpriv = padapter->dvobj;
struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
@@ -3618,10 +5032,10 @@ static void rtw_hal_ap_wow_enable(_adapter *padapter)
issue_beacon(padapter, 0);
rtw_msleep_os(2);
-
+ #if defined(CONFIG_RTL8188E)
if (IS_HARDWARE_TYPE_8188E(padapter))
rtw_hal_disable_tx_report(padapter);
-
+ #endif
/* RX DMA stop */
res = rtw_hal_pause_rx_dma(padapter);
if (res == _FAIL)
@@ -3644,16 +5058,19 @@ static void rtw_hal_ap_wow_enable(_adapter *padapter)
rtw_write8(padapter, REG_MCUTST_WOWLAN, 0);
#ifdef CONFIG_USB_HCI
rtw_mi_intf_stop(padapter);
+#endif
+#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
/* Invoid SE0 reset signal during suspending*/
rtw_write8(padapter, REG_RSV_CTRL, 0x20);
- rtw_write8(padapter, REG_RSV_CTRL, 0x60);
-#endif /*CONFIG_USB_HCI*/
+ if (IS_8188F(pHalData->version_id) == FALSE)
+ rtw_write8(padapter, REG_RSV_CTRL, 0x60);
+#endif
}
static void rtw_hal_ap_wow_disable(_adapter *padapter)
{
struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
- struct hal_ops *pHalFunc = &padapter->HalFunc;
+ struct hal_ops *pHalFunc = &padapter->hal_func;
#ifdef DBG_CHECK_FW_PS_STATE
struct dvobj_priv *psdpriv = padapter->dvobj;
struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
@@ -3678,17 +5095,28 @@ static void rtw_hal_ap_wow_disable(_adapter *padapter)
}
#endif /*DBG_CHECK_FW_PS_STATE*/
+ #if defined(CONFIG_RTL8188E)
if (IS_HARDWARE_TYPE_8188E(padapter))
rtw_hal_enable_tx_report(padapter);
+ #endif
rtw_hal_force_enable_rxdma(padapter);
rtw_hal_fw_dl(padapter, _FALSE);
#ifdef CONFIG_GPIO_WAKEUP
+ #ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE
+ if (pwrctl->is_high_active == 0)
+ rtw_hal_set_input_gpio(padapter, WAKEUP_GPIO_IDX);
+ else
+ rtw_hal_set_output_gpio(padapter, WAKEUP_GPIO_IDX, 0);
+ #else
val8 = (pwrctl->is_high_active == 0) ? 1 : 0;
RTW_PRINT("Set Wake GPIO to default(%d).\n", val8);
rtw_hal_set_output_gpio(padapter, WAKEUP_GPIO_IDX, val8);
+
+ rtw_hal_switch_gpio_wl_ctrl(padapter, WAKEUP_GPIO_IDX, _FALSE);
+ #endif/*CONFIG_WAKEUP_GPIO_INPUT_MODE*/
#endif
media_status_rpt = RT_MEDIA_CONNECT;
@@ -3779,7 +5207,7 @@ static void rtw_hal_construct_P2PBeacon(_adapter *padapter, u8 *pframe, u32 *pLe
SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/);
/* pmlmeext->mgnt_seq++; */
- SetFrameSubType(pframe, WIFI_BEACON);
+ set_frame_sub_type(pframe, WIFI_BEACON);
pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
@@ -3925,11 +5353,11 @@ static void rtw_hal_construct_P2PBeacon(_adapter *padapter, u8 *pframe, u32 *pLe
pframe += len;
pktlen += len;
-#ifdef CONFIG_WFD
+ #ifdef CONFIG_WFD
len = rtw_append_beacon_wfd_ie(padapter, pframe);
pframe += len;
pktlen += len;
-#endif
+ #endif
}
#endif /* CONFIG_P2P */
@@ -4012,17 +5440,6 @@ static void rtw_hal_construct_P2PBeacon(_adapter *padapter, u8 *pframe, u32 *pLe
#endif
}
-static int get_reg_classes_full_count(struct p2p_channels channel_list)
-{
- int cnt = 0;
- int i;
-
- for (i = 0; i < channel_list.reg_classes; i++)
- cnt += channel_list.reg_class[i].channels;
-
- return cnt;
-}
-
static void rtw_hal_construct_P2PProbeRsp(_adapter *padapter, u8 *pframe, u32 *pLength)
{
/* struct xmit_frame *pmgntframe; */
@@ -4069,7 +5486,7 @@ static void rtw_hal_construct_P2PProbeRsp(_adapter *padapter, u8 *pframe, u32 *p
_rtw_memcpy(pwlanhdr->addr3, mac, ETH_ALEN);
SetSeqNum(pwlanhdr, 0);
- SetFrameSubType(fctrl, WIFI_PROBERSP);
+ set_frame_sub_type(fctrl, WIFI_PROBERSP);
pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
pframe += pktlen;
@@ -4346,6 +5763,7 @@ static void rtw_hal_construct_P2PProbeRsp(_adapter *padapter, u8 *pframe, u32 *p
}
static void rtw_hal_construct_P2PNegoRsp(_adapter *padapter, u8 *pframe, u32 *pLength)
{
+ struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list);
unsigned char category = RTW_WLAN_CATEGORY_PUBLIC;
u8 action = P2P_PUB_ACTION_ACTION;
u32 p2poui = cpu_to_be32(P2POUI);
@@ -4391,7 +5809,7 @@ static void rtw_hal_construct_P2PNegoRsp(_adapter *padapter, u8 *pframe, u32 *pL
_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN);
SetSeqNum(pwlanhdr, 0);
- SetFrameSubType(pframe, WIFI_ACTION);
+ set_frame_sub_type(pframe, WIFI_ACTION);
pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
pframe += pktlen;
@@ -4572,7 +5990,7 @@ static void rtw_hal_construct_P2PNegoRsp(_adapter *padapter, u8 *pframe, u32 *pL
/* Intended P2P Interface Address */
/* Type: */
- p2pie[p2pielen++] = P2P_ATTR_INTENTED_IF_ADDR;
+ p2pie[p2pielen++] = P2P_ATTR_INTENDED_IF_ADDR;
/* Length: */
*(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN);
@@ -4590,8 +6008,8 @@ static void rtw_hal_construct_P2PNegoRsp(_adapter *padapter, u8 *pframe, u32 *pL
/* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */
/* + number of channels in all classes */
len_channellist_attr = 3
- + (1 + 1) * (u16)pmlmeext->channel_list.reg_classes
- + get_reg_classes_full_count(pmlmeext->channel_list);
+ + (1 + 1) * (u16)ch_list->reg_classes
+ + get_reg_classes_full_count(ch_list);
#ifdef CONFIG_CONCURRENT_MODE
if (rtw_mi_buddy_check_fwstate(padapter, _FW_LINKED))
@@ -4637,37 +6055,22 @@ static void rtw_hal_construct_P2PNegoRsp(_adapter *padapter, u8 *pframe, u32 *pL
/* Channel List */
p2pie[p2pielen++] = union_ch;
- } else {
- int i, j;
- for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) {
- /* Operating Class */
- p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class;
-
- /* Number of Channels */
- p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels;
-
- /* Channel List */
- for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++)
- p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i];
- }
- }
-#else /* CONFIG_CONCURRENT_MODE */
+ } else
+#endif /* CONFIG_CONCURRENT_MODE */
{
int i, j;
- for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) {
+ for (j = 0; j < ch_list->reg_classes; j++) {
/* Operating Class */
- p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class;
+ p2pie[p2pielen++] = ch_list->reg_class[j].reg_class;
/* Number of Channels */
- p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels;
+ p2pie[p2pielen++] = ch_list->reg_class[j].channels;
/* Channel List */
- for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++)
- p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i];
+ for (i = 0; i < ch_list->reg_class[j].channels; i++)
+ p2pie[p2pielen++] = ch_list->reg_class[j].channel[i];
}
}
-#endif /* CONFIG_CONCURRENT_MODE */
-
/* Device Info */
/* Type: */
@@ -4807,7 +6210,7 @@ static void rtw_hal_construct_P2PInviteRsp(_adapter *padapter, u8 *pframe, u32 *
_rtw_memset(pwlanhdr->addr3, 0, ETH_ALEN);
SetSeqNum(pwlanhdr, 0);
- SetFrameSubType(pframe, WIFI_ACTION);
+ set_frame_sub_type(pframe, WIFI_ACTION);
pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
@@ -4863,6 +6266,8 @@ static void rtw_hal_construct_P2PInviteRsp(_adapter *padapter, u8 *pframe, u32 *
/* due to defult value is FAIL INFO UNAVAILABLE, so the following IE is not needed */
#if 0
if (status_code == P2P_STATUS_SUCCESS) {
+ struct p2p_channels *ch_list = &(adapter_to_rfctl(padapter)->channel_list);
+
if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) {
/* The P2P Invitation request frame asks this Wi-Fi device to be the P2P GO */
/* In this case, the P2P Invitation response frame should carry the two more P2P attributes. */
@@ -4917,8 +6322,8 @@ static void rtw_hal_construct_P2PInviteRsp(_adapter *padapter, u8 *pframe, u32 *
/* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */
/* + number of channels in all classes */
len_channellist_attr = 3
- + (1 + 1) * (u16)pmlmeext->channel_list.reg_classes
- + get_reg_classes_full_count(pmlmeext->channel_list);
+ + (1 + 1) * (u16)ch_list->reg_classes
+ + get_reg_classes_full_count(ch_list);
#ifdef CONFIG_CONCURRENT_MODE
if (rtw_mi_check_status(padapter, MI_LINKED))
@@ -4964,36 +6369,22 @@ static void rtw_hal_construct_P2PInviteRsp(_adapter *padapter, u8 *pframe, u32 *
/* Channel List */
p2pie[p2pielen++] = union_ch;
- } else {
- int i, j;
- for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) {
- /* Operating Class */
- p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class;
-
- /* Number of Channels */
- p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels;
-
- /* Channel List */
- for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++)
- p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i];
- }
- }
-#else /* CONFIG_CONCURRENT_MODE */
+ } else
+#endif /* CONFIG_CONCURRENT_MODE */
{
int i, j;
- for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) {
+ for (j = 0; j < ch_list->reg_classes; j++) {
/* Operating Class */
- p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class;
+ p2pie[p2pielen++] = ch_list->reg_class[j].reg_class;
/* Number of Channels */
- p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels;
+ p2pie[p2pielen++] = ch_list->reg_class[j].channels;
/* Channel List */
- for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++)
- p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i];
+ for (i = 0; i < ch_list->reg_class[j].channels; i++)
+ p2pie[p2pielen++] = ch_list->reg_class[j].channel[i];
}
}
-#endif /* CONFIG_CONCURRENT_MODE */
}
#endif
@@ -5062,7 +6453,7 @@ static void rtw_hal_construct_P2PProvisionDisRsp(_adapter *padapter, u8 *pframe,
_rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN);
SetSeqNum(pwlanhdr, 0);
- SetFrameSubType(pframe, WIFI_ACTION);
+ set_frame_sub_type(pframe, WIFI_ACTION);
pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
@@ -5136,7 +6527,7 @@ static void rtw_hal_construct_P2PProvisionDisRsp(_adapter *padapter, u8 *pframe,
u8 rtw_hal_set_FwP2PRsvdPage_cmd(_adapter *adapter, PRSVDPAGE_LOC rsvdpageloc)
{
u8 u1H2CP2PRsvdPageParm[H2C_P2PRSVDPAGE_LOC_LEN] = {0};
- struct hal_ops *pHalFunc = &adapter->HalFunc;
+ struct hal_ops *pHalFunc = &adapter->hal_func;
u8 ret = _FAIL;
RTW_INFO("P2PRsvdPageLoc: P2PBeacon=%d P2PProbeRsp=%d NegoRsp=%d InviteRsp=%d PDRsp=%d\n",
@@ -5165,7 +6556,7 @@ u8 rtw_hal_set_p2p_wowlan_offload_cmd(_adapter *adapter)
u8 offload_cmd[H2C_P2P_OFFLOAD_LEN] = {0};
struct wifidirect_info *pwdinfo = &(adapter->wdinfo);
struct P2P_WoWlan_Offload_t *p2p_wowlan_offload = (struct P2P_WoWlan_Offload_t *)offload_cmd;
- struct hal_ops *pHalFunc = &adapter->HalFunc;
+ struct hal_ops *pHalFunc = &adapter->hal_func;
u8 ret = _FAIL;
_rtw_memset(p2p_wowlan_offload, 0 , sizeof(struct P2P_WoWlan_Offload_t));
@@ -5202,7 +6593,7 @@ u8 rtw_hal_set_p2p_wowlan_offload_cmd(_adapter *adapter)
}
#endif /* CONFIG_P2P_WOWLAN */
-static void rtw_hal_construct_beacon(_adapter *padapter,
+void rtw_hal_construct_beacon(_adapter *padapter,
u8 *pframe, u32 *pLength)
{
struct rtw_ieee80211_hdr *pwlanhdr;
@@ -5227,7 +6618,7 @@ static void rtw_hal_construct_beacon(_adapter *padapter,
SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/);
/* pmlmeext->mgnt_seq++; */
- SetFrameSubType(pframe, WIFI_BEACON);
+ set_frame_sub_type(pframe, WIFI_BEACON);
pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
@@ -5317,10 +6708,10 @@ static void rtw_hal_construct_PSPoll(_adapter *padapter,
fctrl = &(pwlanhdr->frame_ctl);
*(fctrl) = 0;
SetPwrMgt(fctrl);
- SetFrameSubType(pframe, WIFI_PSPOLL);
+ set_frame_sub_type(pframe, WIFI_PSPOLL);
/* AID. */
- SetDuration(pframe, (pmlmeinfo->aid | 0xc000));
+ set_duration(pframe, (pmlmeinfo->aid | 0xc000));
/* BSSID. */
_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
@@ -5331,15 +6722,12 @@ static void rtw_hal_construct_PSPoll(_adapter *padapter,
*pLength = 16;
}
-void rtw_hal_construct_NullFunctionData(
+
+#ifdef DBG_FW_DEBUG_MSG_PKT
+void rtw_hal_construct_fw_dbg_msg_pkt(
PADAPTER padapter,
u8 *pframe,
- u32 *pLength,
- u8 *StaAddr,
- u8 bQoS,
- u8 AC,
- u8 bEosp,
- u8 bForcePowerSave)
+ u32 *plength)
{
struct rtw_ieee80211_hdr *pwlanhdr;
u16 *fctrl;
@@ -5348,6 +6736,7 @@ void rtw_hal_construct_NullFunctionData(
struct wlan_network *cur_network = &pmlmepriv->cur_network;
struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+ u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
/* RTW_INFO("%s:%d\n", __FUNCTION__, bForcePowerSave); */
@@ -5356,12 +6745,57 @@ void rtw_hal_construct_NullFunctionData(
fctrl = &pwlanhdr->frame_ctl;
*(fctrl) = 0;
- if (bForcePowerSave)
- SetPwrMgt(fctrl);
- switch (cur_network->network.InfrastructureMode) {
- case Ndis802_11Infrastructure:
- SetToDs(fctrl);
+ _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
+ _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
+ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
+
+ SetSeqNum(pwlanhdr, 0);
+
+ set_frame_sub_type(pframe, WIFI_DATA);
+
+ pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+
+ *plength = pktlen;
+}
+#endif /*DBG_FW_DEBUG_MSG_PKT*/
+
+void rtw_hal_construct_NullFunctionData(
+ PADAPTER padapter,
+ u8 *pframe,
+ u32 *pLength,
+ u8 *StaAddr,
+ u8 bQoS,
+ u8 AC,
+ u8 bEosp,
+ u8 bForcePowerSave)
+{
+ struct rtw_ieee80211_hdr *pwlanhdr;
+ u16 *fctrl;
+ u32 pktlen;
+ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+ struct wlan_network *cur_network = &pmlmepriv->cur_network;
+ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
+ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+ u8 bssid[ETH_ALEN];
+
+ /* RTW_INFO("%s:%d\n", __FUNCTION__, bForcePowerSave); */
+
+ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+ fctrl = &pwlanhdr->frame_ctl;
+ *(fctrl) = 0;
+ if (bForcePowerSave)
+ SetPwrMgt(fctrl);
+
+ if (NULL == StaAddr) {
+ _rtw_memcpy(bssid, adapter_mac_addr(padapter), ETH_ALEN);
+ StaAddr = bssid;
+ }
+
+ switch (cur_network->network.InfrastructureMode) {
+ case Ndis802_11Infrastructure:
+ SetToDs(fctrl);
_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
_rtw_memcpy(pwlanhdr->addr3, StaAddr, ETH_ALEN);
@@ -5381,11 +6815,12 @@ void rtw_hal_construct_NullFunctionData(
}
SetSeqNum(pwlanhdr, 0);
+ set_duration(pwlanhdr, 0);
if (bQoS == _TRUE) {
struct rtw_ieee80211_hdr_3addr_qos *pwlanqoshdr;
- SetFrameSubType(pframe, WIFI_QOS_DATA_NULL);
+ set_frame_sub_type(pframe, WIFI_QOS_DATA_NULL);
pwlanqoshdr = (struct rtw_ieee80211_hdr_3addr_qos *)pframe;
SetPriority(&pwlanqoshdr->qc, AC);
@@ -5393,7 +6828,7 @@ void rtw_hal_construct_NullFunctionData(
pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos);
} else {
- SetFrameSubType(pframe, WIFI_DATA_NULL);
+ set_frame_sub_type(pframe, WIFI_DATA_NULL);
pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
}
@@ -5426,7 +6861,7 @@ void rtw_hal_construct_ProbeRsp(_adapter *padapter, u8 *pframe, u32 *pLength,
_rtw_memcpy(pwlanhdr->addr3, bssid, ETH_ALEN);
SetSeqNum(pwlanhdr, 0);
- SetFrameSubType(fctrl, WIFI_PROBERSP);
+ set_frame_sub_type(fctrl, WIFI_PROBERSP);
pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
pframe += pktlen;
@@ -5442,6 +6877,52 @@ void rtw_hal_construct_ProbeRsp(_adapter *padapter, u8 *pframe, u32 *pLength,
}
#ifdef CONFIG_WOWLAN
+static void rtw_hal_append_tkip_mic(PADAPTER padapter,
+ u8 *pframe, u32 offset)
+{
+ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
+ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+ struct rtw_ieee80211_hdr *pwlanhdr;
+ struct mic_data micdata;
+ struct sta_info *psta = NULL;
+ int res = 0;
+
+ u8 *payload = (u8 *)(pframe + offset);
+
+ u8 mic[8];
+ u8 priority[4] = {0x0};
+ u8 null_key[16] = {0x0};
+
+ RTW_INFO("%s(): Add MIC, offset: %d\n", __func__, offset);
+
+ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+ psta = rtw_get_stainfo(&padapter->stapriv,
+ get_my_bssid(&(pmlmeinfo->network)));
+ if (psta != NULL) {
+ res = _rtw_memcmp(&psta->dot11tkiptxmickey.skey[0],
+ null_key, 16);
+ if (res == _TRUE)
+ RTW_INFO("%s(): STA dot11tkiptxmickey==0\n", __func__);
+ rtw_secmicsetkey(&micdata, &psta->dot11tkiptxmickey.skey[0]);
+ }
+
+ rtw_secmicappend(&micdata, pwlanhdr->addr3, 6); /* DA */
+
+ rtw_secmicappend(&micdata, pwlanhdr->addr2, 6); /* SA */
+
+ priority[0] = 0;
+
+ rtw_secmicappend(&micdata, &priority[0], 4);
+
+ rtw_secmicappend(&micdata, payload, 36); /* payload length = 8 + 28 */
+
+ rtw_secgetmic(&micdata, &(mic[0]));
+
+ payload += 36;
+
+ _rtw_memcpy(payload, &(mic[0]), 8);
+}
/*
* Description:
* Construct the ARP response packet to support ARP offload.
@@ -5465,7 +6946,7 @@ static void rtw_hal_construct_ARPRsp(
u8 *pARPRspPkt = pframe;
/* for TKIP Cal MIC */
u8 *payload = pframe;
- u8 EncryptionHeadOverhead = 0;
+ u8 EncryptionHeadOverhead = 0, arp_offset = 0;
/* RTW_INFO("%s:%d\n", __FUNCTION__, bForcePowerSave); */
pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
@@ -5477,14 +6958,14 @@ static void rtw_hal_construct_ARPRsp(
/* MAC Header. */
/* ------------------------------------------------------------------------- */
SetFrameType(fctrl, WIFI_DATA);
- /* SetFrameSubType(fctrl, 0); */
+ /* set_frame_sub_type(fctrl, 0); */
SetToDs(fctrl);
_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
_rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN);
_rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
SetSeqNum(pwlanhdr, 0);
- SetDuration(pwlanhdr, 0);
+ set_duration(pwlanhdr, 0);
/* SET_80211_HDR_FRAME_CONTROL(pARPRspPkt, 0); */
/* SET_80211_HDR_TYPE_AND_SUBTYPE(pARPRspPkt, Type_Data); */
/* SET_80211_HDR_TO_DS(pARPRspPkt, 1); */
@@ -5529,7 +7010,8 @@ static void rtw_hal_construct_ARPRsp(
/* ------------------------------------------------------------------------- */
/* Frame Body. */
/* ------------------------------------------------------------------------- */
- pARPRspPkt = (u8 *)(pframe + *pLength);
+ arp_offset = *pLength;
+ pARPRspPkt = (u8 *)(pframe + arp_offset);
payload = pARPRspPkt; /* Get Payload pointer */
/* LLC header */
_rtw_memcpy(pARPRspPkt, ARPLLCHeader, 8);
@@ -5564,45 +7046,193 @@ static void rtw_hal_construct_ARPRsp(
*pLength += 28;
if (psecuritypriv->dot11PrivacyAlgrthm == _TKIP_) {
- u8 mic[8];
- struct mic_data micdata;
- struct sta_info *psta = NULL;
- u8 priority[4] = {0x0, 0x0, 0x0, 0x0};
- u8 null_key[16] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+ if (IS_HARDWARE_TYPE_8188E(padapter) ||
+ IS_HARDWARE_TYPE_8812(padapter)) {
+ rtw_hal_append_tkip_mic(padapter, pframe, arp_offset);
+ }
+ *pLength += 8;
+ }
+}
- RTW_INFO("%s(): Add MIC\n", __FUNCTION__);
+#ifdef CONFIG_IPV6
+/*
+ * Description: Neighbor Discovery Offload.
+ */
+static void rtw_hal_construct_na_message(_adapter *padapter,
+ u8 *pframe, u32 *pLength)
+{
+ struct rtw_ieee80211_hdr *pwlanhdr = NULL;
+ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+ struct wlan_network *cur_network = &pmlmepriv->cur_network;
+ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+ struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
+ struct security_priv *psecuritypriv = &padapter->securitypriv;
- psta = rtw_get_stainfo(&padapter->stapriv,
- get_my_bssid(&(pmlmeinfo->network)));
- if (psta != NULL) {
- if (_rtw_memcmp(&psta->dot11tkiptxmickey.skey[0],
- null_key, 16) == _TRUE) {
- RTW_INFO("%s(): STA dot11tkiptxmickey==0\n",
- __func__);
- }
- /* start to calculate the mic code */
- rtw_secmicsetkey(&micdata,
- &psta->dot11tkiptxmickey.skey[0]);
- }
+ u32 pktlen = 0;
+ u16 *fctrl = NULL;
- rtw_secmicappend(&micdata, pwlanhdr->addr3, 6); /* DA */
+ u8 ns_hdr[8] = {0xAA, 0xAA, 0x03, 0x00, 0x00, 0x00, 0x86, 0xDD};
+ u8 ipv6_info[4] = {0x60, 0x00, 0x00, 0x00};
+ u8 ipv6_contx[4] = {0x00, 0x20, 0x3a, 0xff};
+ u8 icmpv6_hdr[8] = {0x88, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00};
+ u8 val8 = 0;
+
+ u8 *p_na_msg = pframe;
+ /* for TKIP Cal MIC */
+ u8 *payload = pframe;
+ u8 EncryptionHeadOverhead = 0, na_msg_offset = 0;
+ /* RTW_INFO("%s:%d\n", __FUNCTION__, bForcePowerSave); */
+
+ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+ fctrl = &pwlanhdr->frame_ctl;
+ *(fctrl) = 0;
- rtw_secmicappend(&micdata, pwlanhdr->addr2, 6); /* SA */
+ /* ------------------------------------------------------------------------- */
+ /* MAC Header. */
+ /* ------------------------------------------------------------------------- */
+ SetFrameType(fctrl, WIFI_DATA);
+ SetToDs(fctrl);
+ _rtw_memcpy(pwlanhdr->addr1,
+ get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
+ _rtw_memcpy(pwlanhdr->addr2,
+ adapter_mac_addr(padapter), ETH_ALEN);
+ _rtw_memcpy(pwlanhdr->addr3,
+ get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
- priority[0] = 0;
+ SetSeqNum(pwlanhdr, 0);
+ set_duration(pwlanhdr, 0);
- rtw_secmicappend(&micdata, &priority[0], 4);
+#ifdef CONFIG_WAPI_SUPPORT
+ *pLength = sMacHdrLng;
+#else
+ *pLength = 24;
+#endif
+ switch (psecuritypriv->dot11PrivacyAlgrthm) {
+ case _WEP40_:
+ case _WEP104_:
+ EncryptionHeadOverhead = 4;
+ break;
+ case _TKIP_:
+ EncryptionHeadOverhead = 8;
+ break;
+ case _AES_:
+ EncryptionHeadOverhead = 8;
+ break;
+#ifdef CONFIG_WAPI_SUPPORT
+ case _SMS4_:
+ EncryptionHeadOverhead = 18;
+ break;
+#endif
+ default:
+ EncryptionHeadOverhead = 0;
+ }
- rtw_secmicappend(&micdata, payload, 36); /* payload length = 8 + 28 */
+ if (EncryptionHeadOverhead > 0) {
+ _rtw_memset(&(pframe[*pLength]), 0, EncryptionHeadOverhead);
+ *pLength += EncryptionHeadOverhead;
+ /* SET_80211_HDR_WEP(pARPRspPkt, 1); */ /* Suggested by CCW. */
+ SetPrivacy(fctrl);
+ }
- rtw_secgetmic(&micdata, &(mic[0]));
+ /* ------------------------------------------------------------------------- */
+ /* Frame Body. */
+ /* ------------------------------------------------------------------------- */
+ na_msg_offset = *pLength;
+ p_na_msg = (u8 *)(pframe + na_msg_offset);
+ payload = p_na_msg; /* Get Payload pointer */
- pARPRspPkt += 28;
- _rtw_memcpy(pARPRspPkt, &(mic[0]), 8);
+ /* LLC header */
+ val8 = sizeof(ns_hdr);
+ _rtw_memcpy(p_na_msg, ns_hdr, val8);
+ *pLength += val8;
+ p_na_msg += val8;
+
+ /* IPv6 Header */
+ /* 1 . Information (4 bytes): 0x60 0x00 0x00 0x00 */
+ val8 = sizeof(ipv6_info);
+ _rtw_memcpy(p_na_msg, ipv6_info, val8);
+ *pLength += val8;
+ p_na_msg += val8;
+
+ /* 2 . playload : 0x00 0x20 , NextProt : 0x3a (ICMPv6) HopLim : 0xff */
+ val8 = sizeof(ipv6_contx);
+ _rtw_memcpy(p_na_msg, ipv6_contx, val8);
+ *pLength += val8;
+ p_na_msg += val8;
+
+ /* 3 . SA : 16 bytes , DA : 16 bytes ( Fw will filled ) */
+ _rtw_memset(&(p_na_msg[*pLength]), 0, 32);
+ *pLength += 32;
+ p_na_msg += 32;
+
+ /* ICMPv6 */
+ /* 1. Type : 0x88 (NA)
+ * 2. Code : 0x00
+ * 3. ChechSum : 0x00 0x00 (RSvd)
+ * 4. NAFlag: 0x60 0x00 0x00 0x00 ( Solicited , Override)
+ */
+ val8 = sizeof(icmpv6_hdr);
+ _rtw_memcpy(p_na_msg, icmpv6_hdr, val8);
+ *pLength += val8;
+ p_na_msg += val8;
+
+ /* TA: 16 bytes*/
+ _rtw_memset(&(p_na_msg[*pLength]), 0, 16);
+ *pLength += 16;
+ p_na_msg += 16;
+
+ /* ICMPv6 Target Link Layer Address */
+ p_na_msg[0] = 0x02; /* type */
+ p_na_msg[1] = 0x01; /* len 1 unit of 8 octes */
+ *pLength += 2;
+ p_na_msg += 2;
+
+ _rtw_memset(&(p_na_msg[*pLength]), 0, 6);
+ *pLength += 6;
+ p_na_msg += 6;
+ if (psecuritypriv->dot11PrivacyAlgrthm == _TKIP_) {
+ if (IS_HARDWARE_TYPE_8188E(padapter) ||
+ IS_HARDWARE_TYPE_8812(padapter)) {
+ rtw_hal_append_tkip_mic(padapter, pframe,
+ na_msg_offset);
+ }
*pLength += 8;
}
}
+/*
+ * Description: Neighbor Discovery Protocol Information.
+ */
+static void rtw_hal_construct_ndp_info(_adapter *padapter,
+ u8 *pframe, u32 *pLength)
+{
+ struct mlme_ext_priv *pmlmeext = NULL;
+ struct mlme_ext_info *pmlmeinfo = NULL;
+ struct rtw_ndp_info ndp_info;
+ u8 *pndp_info = pframe;
+ u8 len = sizeof(struct rtw_ndp_info);
+
+ RTW_INFO("%s: len: %d\n", __func__, len);
+
+ pmlmeext = &padapter->mlmeextpriv;
+ pmlmeinfo = &pmlmeext->mlmext_info;
+
+ _rtw_memset(pframe, 0, len);
+ _rtw_memset(&ndp_info, 0, len);
+
+ ndp_info.enable = 1;
+ ndp_info.check_remote_ip = 0;
+ ndp_info.num_of_target_ip = 1;
+
+ _rtw_memcpy(&ndp_info.target_link_addr, adapter_mac_addr(padapter),
+ ETH_ALEN);
+ _rtw_memcpy(&ndp_info.target_ipv6_addr, pmlmeinfo->ip6_addr,
+ RTW_IPv6_ADDR_LEN);
+
+ _rtw_memcpy(pndp_info, &ndp_info, len);
+}
+#endif /* CONFIG_IPV6 */
#ifdef CONFIG_PNO_SUPPORT
static void rtw_hal_construct_ProbeReq(_adapter *padapter, u8 *pframe,
@@ -5632,7 +7262,7 @@ static void rtw_hal_construct_ProbeReq(_adapter *padapter, u8 *pframe,
_rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN);
SetSeqNum(pwlanhdr, 0);
- SetFrameSubType(pframe, WIFI_PROBEREQ);
+ set_frame_sub_type(pframe, WIFI_PROBEREQ);
pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
pframe += pktlen;
@@ -5811,7 +7441,7 @@ static void rtw_hal_construct_GTKRsp(
/* MAC Header. */
/* ------------------------------------------------------------------------- */
SetFrameType(fctrl, WIFI_DATA);
- /* SetFrameSubType(fctrl, 0); */
+ /* set_frame_sub_type(fctrl, 0); */
SetToDs(fctrl);
_rtw_memcpy(pwlanhdr->addr1,
@@ -5824,7 +7454,7 @@ static void rtw_hal_construct_GTKRsp(
get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
SetSeqNum(pwlanhdr, 0);
- SetDuration(pwlanhdr, 0);
+ set_duration(pwlanhdr, 0);
#ifdef CONFIG_WAPI_SUPPORT
*pLength = sMacHdrLng;
@@ -5873,6 +7503,11 @@ static void rtw_hal_construct_GTKRsp(
/* GTK element */
pGTKRspPkt += 8;
+ /* GTK frame body after LLC, part 1 */
+ /* TKIP key_length = 32, AES key_length = 16 */
+ if (psecuritypriv->dot118021XGrpPrivacy == _TKIP_)
+ GTKbody_a[8] = 0x20;
+
/* GTK frame body after LLC, part 1 */
_rtw_memcpy(pGTKRspPkt, GTKbody_a, 11);
*pLength += 11;
@@ -5882,9 +7517,89 @@ static void rtw_hal_construct_GTKRsp(
*pLength += 88;
pGTKRspPkt += 88;
+ if (psecuritypriv->dot118021XGrpPrivacy == _TKIP_)
+ *pLength += 8;
}
#endif /* CONFIG_GTK_OL */
+#define PN_2_CCMPH(ch,key_id) ((ch) & 0x000000000000ffff) \
+ | (((ch) & 0x0000ffffffff0000) << 16) \
+ | (((key_id) << 30)) \
+ | BIT(29)
+static void rtw_hal_construct_remote_control_info(_adapter *adapter,
+ u8 *pframe, u32 *pLength)
+{
+ struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
+ struct sta_priv *pstapriv = &adapter->stapriv;
+ struct security_priv *psecuritypriv = &adapter->securitypriv;
+ struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
+ struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
+ struct sta_info *psta;
+ struct stainfo_rxcache *prxcache;
+ u8 cur_dot11rxiv[8], id = 0, tid_id = 0, i = 0;
+ size_t sz = 0, total = 0;
+ u64 ccmp_hdr = 0, tmp_key = 0;
+
+ psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
+
+ if (psta == NULL) {
+ rtw_warn_on(1);
+ return;
+ }
+
+ prxcache = &psta->sta_recvpriv.rxcache;
+ sz = sizeof(cur_dot11rxiv);
+
+ /* 3 SEC IV * 1 page */
+ rtw_get_sec_iv(adapter, cur_dot11rxiv,
+ get_my_bssid(&pmlmeinfo->network));
+
+ _rtw_memcpy(pframe, cur_dot11rxiv, sz);
+ *pLength += sz;
+ pframe += sz;
+
+ _rtw_memset(&cur_dot11rxiv, 0, sz);
+
+ if (psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK) {
+ id = psecuritypriv->dot118021XGrpKeyid;
+ tid_id = prxcache->last_tid;
+ REMOTE_INFO_CTRL_SET_VALD_EN(cur_dot11rxiv, 0xdd);
+ REMOTE_INFO_CTRL_SET_PTK_EN(cur_dot11rxiv, 1);
+ REMOTE_INFO_CTRL_SET_GTK_EN(cur_dot11rxiv, 1);
+ REMOTE_INFO_CTRL_SET_GTK_IDX(cur_dot11rxiv, id);
+ _rtw_memcpy(pframe, cur_dot11rxiv, sz);
+ *pLength += sz;
+ pframe += sz;
+
+ _rtw_memcpy(pframe, prxcache->iv[tid_id], sz);
+ *pLength += sz;
+ pframe += sz;
+
+ total = sizeof(psecuritypriv->iv_seq);
+ total /= sizeof(psecuritypriv->iv_seq[0]);
+
+ for (i = 0 ; i < total ; i ++) {
+ ccmp_hdr =
+ le64_to_cpu(*(u64*)psecuritypriv->iv_seq[i]);
+ _rtw_memset(&cur_dot11rxiv, 0, sz);
+ if (ccmp_hdr != 0) {
+ tmp_key = i;
+ ccmp_hdr = PN_2_CCMPH(ccmp_hdr, tmp_key);
+ *(u64*)cur_dot11rxiv = cpu_to_le64(ccmp_hdr);
+ _rtw_memcpy(pframe, cur_dot11rxiv, sz);
+ }
+ *pLength += sz;
+ pframe += sz;
+ }
+ }
+}
+
+/*#define DBG_RSVD_PAGE_CFG*/
+#ifdef DBG_RSVD_PAGE_CFG
+#define RSVD_PAGE_CFG(ops, v1, v2, v3) \
+ RTW_INFO("=== [RSVD][%s]-NeedPage:%d, TotalPageNum:%d TotalPacketLen:%d ===\n", \
+ ops, v1, v2, v3)
+#endif
void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index,
u8 tx_desc, u32 page_size, u8 *page_num, u32 *total_pkt_len,
RSVDPAGE_LOC *rsvd_page_loc)
@@ -5894,15 +7609,14 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index,
struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
struct mlme_ext_priv *pmlmeext;
struct mlme_ext_info *pmlmeinfo;
- u32 ARPLegnth = 0, GTKLegnth = 0, PNOLength = 0, ScanInfoLength = 0;
- u32 SSIDLegnth = 0, ProbeReqLength = 0;
+ u32 ARPLength = 0, GTKLength = 0, PNOLength = 0, ScanInfoLength = 0;
+ u32 SSIDLegnth = 0, ProbeReqLength = 0, ns_len = 0, rc_len = 0;
u8 CurtPktPageNum = 0;
- u8 currentip[4];
- u8 cur_dot11txpn[8];
#ifdef CONFIG_GTK_OL
struct sta_priv *pstapriv = &adapter->stapriv;
struct sta_info *psta;
+ struct security_priv *psecpriv = &adapter->securitypriv;
u8 kek[RTW_KEK_LEN];
u8 kck[RTW_KCK_LEN];
#endif /* CONFIG_GTK_OL */
@@ -5916,40 +7630,75 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index,
if (pwrctl->wowlan_pno_enable == _FALSE) {
/* ARP RSP * 1 page */
- rtw_get_current_ip_address(adapter, currentip);
rsvd_page_loc->LocArpRsp = *page_num;
RTW_INFO("LocArpRsp: %d\n", rsvd_page_loc->LocArpRsp);
rtw_hal_construct_ARPRsp(adapter, &pframe[index],
- &ARPLegnth, currentip);
+ &ARPLength, pmlmeinfo->ip_addr);
rtw_hal_fill_fake_txdesc(adapter,
&pframe[index - tx_desc],
- ARPLegnth, _FALSE, _FALSE, _TRUE);
+ ARPLength, _FALSE, _FALSE, _TRUE);
- CurtPktPageNum = (u8)PageNum(tx_desc + ARPLegnth, page_size);
+ CurtPktPageNum = (u8)PageNum(tx_desc + ARPLength, page_size);
*page_num += CurtPktPageNum;
index += (CurtPktPageNum * page_size);
+ #ifdef DBG_RSVD_PAGE_CFG
+ RSVD_PAGE_CFG("WOW-ARPRsp", CurtPktPageNum, *page_num, 0);
+ #endif
+
+#ifdef CONFIG_IPV6
+ /* 2 NS offload and NDP Info*/
+ if (pwrctl->wowlan_ns_offload_en == _TRUE) {
+ rsvd_page_loc->LocNbrAdv = *page_num;
+ RTW_INFO("LocNbrAdv: %d\n", rsvd_page_loc->LocNbrAdv);
+ rtw_hal_construct_na_message(adapter,
+ &pframe[index], &ns_len);
+ rtw_hal_fill_fake_txdesc(adapter,
+ &pframe[index - tx_desc],
+ ns_len, _FALSE,
+ _FALSE, _TRUE);
+ CurtPktPageNum = (u8)PageNum(tx_desc + ns_len,
+ page_size);
+ *page_num += CurtPktPageNum;
+ index += (CurtPktPageNum * page_size);
+ #ifdef DBG_RSVD_PAGE_CFG
+ RSVD_PAGE_CFG("WOW-NbrAdv", CurtPktPageNum, *page_num, 0);
+ #endif
- /* 3 SEC IV * 1 page */
- rtw_get_sec_iv(adapter, cur_dot11txpn,
- get_my_bssid(&pmlmeinfo->network));
+ rsvd_page_loc->LocNDPInfo = *page_num;
+ RTW_INFO("LocNDPInfo: %d\n",
+ rsvd_page_loc->LocNDPInfo);
- rsvd_page_loc->LocRemoteCtrlInfo = *page_num;
+ rtw_hal_construct_ndp_info(adapter,
+ &pframe[index - tx_desc],
+ &ns_len);
+ CurtPktPageNum =
+ (u8)PageNum(tx_desc + ns_len, page_size);
+ *page_num += CurtPktPageNum;
+ index += (CurtPktPageNum * page_size);
+ #ifdef DBG_RSVD_PAGE_CFG
+ RSVD_PAGE_CFG("WOW-NDPInfo", CurtPktPageNum, *page_num, 0);
+ #endif
+ }
+#endif /*CONFIG_IPV6*/
+ /* 3 Remote Control Info. * 1 page */
+ rsvd_page_loc->LocRemoteCtrlInfo = *page_num;
RTW_INFO("LocRemoteCtrlInfo: %d\n", rsvd_page_loc->LocRemoteCtrlInfo);
-
- _rtw_memcpy(pframe + index - tx_desc, cur_dot11txpn, _AES_IV_LEN_);
-
- CurtPktPageNum = (u8)PageNum(_AES_IV_LEN_, page_size);
-
+ rtw_hal_construct_remote_control_info(adapter,
+ &pframe[index - tx_desc],
+ &rc_len);
+ CurtPktPageNum = (u8)PageNum(rc_len, page_size);
*page_num += CurtPktPageNum;
-
- *total_pkt_len = index + _AES_IV_LEN_;
+ *total_pkt_len = index + rc_len;
+ #ifdef DBG_RSVD_PAGE_CFG
+ RSVD_PAGE_CFG("WOW-RCI", CurtPktPageNum, *page_num, *total_pkt_len);
+ #endif
#ifdef CONFIG_GTK_OL
index += (CurtPktPageNum * page_size);
@@ -5983,13 +7732,20 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index,
kek, RTW_KEK_LEN);
CurtPktPageNum = (u8)PageNum(tx_desc + 2 + RTW_KCK_LEN + RTW_KEK_LEN, page_size);
} else {
- _rtw_memcpy(pframe + index - tx_desc, kck, RTW_KCK_LEN);
- _rtw_memcpy(pframe + index - tx_desc + RTW_KCK_LEN, kek, RTW_KEK_LEN);
- CurtPktPageNum = (u8)PageNum(tx_desc + RTW_KCK_LEN + RTW_KEK_LEN, page_size);
- }
-
+ _rtw_memcpy(pframe + index - tx_desc, kck, RTW_KCK_LEN);
+ _rtw_memcpy(pframe + index - tx_desc + RTW_KCK_LEN,
+ kek, RTW_KEK_LEN);
+ GTKLength = tx_desc + RTW_KCK_LEN + RTW_KEK_LEN;
+ if (psta != NULL &&
+ psecuritypriv->dot118021XGrpPrivacy == _TKIP_) {
+ _rtw_memcpy(pframe + index - tx_desc + 56,
+ &psta->dot11tkiptxmickey, RTW_TKIP_MIC_LEN);
+ GTKLength += RTW_TKIP_MIC_LEN;
+ }
+ CurtPktPageNum = (u8)PageNum(GTKLength, page_size);
+ }
#if 0
{
int i;
@@ -6010,19 +7766,22 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index,
*page_num += CurtPktPageNum;
index += (CurtPktPageNum * page_size);
+ #ifdef DBG_RSVD_PAGE_CFG
+ RSVD_PAGE_CFG("WOW-GTKInfo", CurtPktPageNum, *page_num, 0);
+ #endif
/* 3 GTK Response */
rsvd_page_loc->LocGTKRsp = *page_num;
RTW_INFO("LocGTKRsp: %d\n", rsvd_page_loc->LocGTKRsp);
- rtw_hal_construct_GTKRsp(adapter, &pframe[index], >KLegnth);
+ rtw_hal_construct_GTKRsp(adapter, &pframe[index], >KLength);
rtw_hal_fill_fake_txdesc(adapter, &pframe[index - tx_desc],
- GTKLegnth, _FALSE, _FALSE, _TRUE);
+ GTKLength, _FALSE, _FALSE, _TRUE);
#if 0
{
int gj;
printk("123GTK pkt=>\n");
- for (gj = 0; gj < GTKLegnth + tx_desc; gj++) {
+ for (gj = 0; gj < GTKLength + tx_desc; gj++) {
printk(" %02x ", pframe[index - tx_desc + gj]);
if ((gj + 1) % 16 == 0)
printk("\n");
@@ -6032,19 +7791,22 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index,
RTW_INFO("%s(): HW_VAR_SET_TX_CMD: GTK RSP %p %d\n",
__FUNCTION__, &pframe[index - tx_desc],
- (tx_desc + GTKLegnth));
+ (tx_desc + GTKLength));
#endif
- CurtPktPageNum = (u8)PageNum(tx_desc + GTKLegnth, page_size);
+ CurtPktPageNum = (u8)PageNum(tx_desc + GTKLength, page_size);
*page_num += CurtPktPageNum;
index += (CurtPktPageNum * page_size);
+ #ifdef DBG_RSVD_PAGE_CFG
+ RSVD_PAGE_CFG("WOW-GTKRsp", CurtPktPageNum, *page_num, 0);
+ #endif
/* below page is empty for GTK extension memory */
/* 3(11) GTK EXT MEM */
rsvd_page_loc->LocGTKEXTMEM = *page_num;
-
+ RTW_INFO("LocGTKEXTMEM: %d\n", rsvd_page_loc->LocGTKEXTMEM);
CurtPktPageNum = 2;
if (page_size >= 256)
@@ -6053,11 +7815,24 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index,
*page_num += CurtPktPageNum;
/* extension memory for FW */
*total_pkt_len = index + (page_size * CurtPktPageNum);
-
+ #ifdef DBG_RSVD_PAGE_CFG
+ RSVD_PAGE_CFG("WOW-GTKEXTMEM", CurtPktPageNum, *page_num, *total_pkt_len);
+ #endif
#endif /* CONFIG_GTK_OL */
+
+ index += (CurtPktPageNum * page_size);
+
+ /*Reserve 1 page for AOAC report*/
+ rsvd_page_loc->LocAOACReport = *page_num;
+ RTW_INFO("LocAOACReport: %d\n", rsvd_page_loc->LocAOACReport);
+ *page_num += 1;
+ *total_pkt_len = index + (page_size * 1);
+ #ifdef DBG_RSVD_PAGE_CFG
+ RSVD_PAGE_CFG("WOW-AOAC", 1, *page_num, *total_pkt_len);
+ #endif
} else {
#ifdef CONFIG_PNO_SUPPORT
- if (pwrctl->pno_in_resume == _FALSE &&
+ if (pwrctl->wowlan_in_resume == _FALSE &&
pwrctl->pno_inited == _TRUE) {
/* Broadcast Probe Request */
@@ -6082,6 +7857,9 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index,
*page_num += CurtPktPageNum;
index += (CurtPktPageNum * page_size);
+ #ifdef DBG_RSVD_PAGE_CFG
+ RSVD_PAGE_CFG("WOW-ProbeReq", CurtPktPageNum, *page_num, 0);
+ #endif
/* Hidden SSID Probe Request */
ssid_num = pwrctl->pnlo_info->hidden_ssid_num;
@@ -6106,6 +7884,9 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index,
*page_num += CurtPktPageNum;
index += (CurtPktPageNum * page_size);
+ #ifdef DBG_RSVD_PAGE_CFG
+ RSVD_PAGE_CFG("WOW-ProbeReq", CurtPktPageNum, *page_num, 0);
+ #endif
}
/* PNO INFO Page */
@@ -6118,6 +7899,9 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index,
CurtPktPageNum = (u8)PageNum(PNOLength, page_size);
*page_num += CurtPktPageNum;
index += (CurtPktPageNum * page_size);
+ #ifdef DBG_RSVD_PAGE_CFG
+ RSVD_PAGE_CFG("WOW-PNOInfo", CurtPktPageNum, *page_num, 0);
+ #endif
/* Scan Info Page */
rsvd_page_loc->LocScanInfo = *page_num;
@@ -6130,7 +7914,9 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index,
*page_num += CurtPktPageNum;
*total_pkt_len = index + ScanInfoLength;
index += (CurtPktPageNum * page_size);
-
+ #ifdef DBG_RSVD_PAGE_CFG
+ RSVD_PAGE_CFG("WOW-ScanInfo", CurtPktPageNum, *page_num, *total_pkt_len);
+ #endif
}
#endif /* CONFIG_PNO_SUPPORT */
}
@@ -6139,10 +7925,25 @@ void rtw_hal_set_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index,
static void rtw_hal_gate_bb(_adapter *adapter, bool stop)
{
struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
- u8 val8 = 0;
+ u8 i = 0, val8 = 0, empty = _FAIL;
u16 val16 = 0;
if (stop) {
+ /* checking TX queue status */
+ for (i = 0 ; i < 5 ; i++) {
+ rtw_hal_get_hwreg(adapter, HW_VAR_CHK_MGQ_CPU_EMPTY, &empty);
+ if (empty) {
+ break;
+ } else {
+ RTW_WARN("%s: MGQ_CPU is busy(%d)!\n",
+ __func__, i);
+ rtw_mdelay_os(10);
+ }
+ }
+
+ if (val8 == 5)
+ RTW_ERR("%s: Polling MGQ_CPU empty fail!\n", __func__);
+
/* Pause TX*/
pwrpriv->wowlan_txpause_status = rtw_read8(adapter, REG_TXPAUSE);
rtw_write8(adapter, REG_TXPAUSE, 0xff);
@@ -6179,80 +7980,49 @@ static void rtw_hal_reset_mac_rx(_adapter *adapter)
RTW_INFO("0x%04x: %02x\n", REG_CR, rtw_read8(adapter, REG_CR));
}
-static void rtw_hal_set_wow_rxff_boundary(_adapter *adapter, bool wow_mode)
-{
- u8 val8 = 0;
- u16 rxff_bndy = 0;
- u32 rx_dma_buff_sz = 0;
-
- val8 = rtw_read8(adapter, REG_FIFOPAGE + 3);
- if (val8 != 0)
- RTW_INFO("%s:[%04x]some PKTs in TXPKTBUF\n",
- __func__, (REG_FIFOPAGE + 3));
-
- rtw_hal_reset_mac_rx(adapter);
-
- if (wow_mode) {
- rtw_hal_get_def_var(adapter, HAL_DEF_RX_DMA_SZ_WOW,
- (u8 *)&rx_dma_buff_sz);
- rxff_bndy = rx_dma_buff_sz - 1;
-
- rtw_write16(adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
- RTW_INFO("%s: wow mode, 0x%04x: 0x%04x\n", __func__,
- REG_TRXFF_BNDY + 2,
- rtw_read16(adapter, (REG_TRXFF_BNDY + 2)));
- } else {
- rtw_hal_get_def_var(adapter, HAL_DEF_RX_DMA_SZ,
- (u8 *)&rx_dma_buff_sz);
- rxff_bndy = rx_dma_buff_sz - 1;
- rtw_write16(adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
- RTW_INFO("%s: normal mode, 0x%04x: 0x%04x\n", __func__,
- REG_TRXFF_BNDY + 2,
- rtw_read16(adapter, (REG_TRXFF_BNDY + 2)));
- }
-}
-
-static int rtw_hal_set_pattern(_adapter *adapter, u8 *pattern,
- u8 len, u8 *mask, u8 idx)
+static u8 rtw_hal_wow_pattern_generate(_adapter *adapter, u8 idx, struct rtl_wow_pattern *pwow_pattern)
{
struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
- struct mlme_ext_priv *pmlmeext = NULL;
- struct mlme_ext_info *pmlmeinfo = NULL;
- struct rtl_wow_pattern wow_pattern;
+ u8 *pattern;
+ u8 len = 0;
+ u8 *mask;
+
u8 mask_hw[MAX_WKFM_SIZE] = {0};
u8 content[MAX_WKFM_PATTERN_SIZE] = {0};
u8 broadcast_addr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
u8 multicast_addr1[2] = {0x33, 0x33};
u8 multicast_addr2[3] = {0x01, 0x00, 0x5e};
- u8 res = _FALSE, index = 0, mask_len = 0;
+ u8 mask_len = 0;
u8 mac_addr[ETH_ALEN] = {0};
u16 count = 0;
int i, j;
- if (pwrctl->wowlan_pattern_idx > MAX_WKFM_NUM) {
+ if (pwrctl->wowlan_pattern_idx > MAX_WKFM_CAM_NUM) {
RTW_INFO("%s pattern_idx is more than MAX_FMC_NUM: %d\n",
- __func__, MAX_WKFM_NUM);
- return _FALSE;
+ __func__, MAX_WKFM_CAM_NUM);
+ return _FAIL;
}
- pmlmeext = &adapter->mlmeextpriv;
- pmlmeinfo = &pmlmeext->mlmext_info;
+ pattern = pwrctl->patterns[idx].content;
+ len = pwrctl->patterns[idx].len;
+ mask = pwrctl->patterns[idx].mask;
+
_rtw_memcpy(mac_addr, adapter_mac_addr(adapter), ETH_ALEN);
- _rtw_memset(&wow_pattern, 0, sizeof(struct rtl_wow_pattern));
+ _rtw_memset(pwow_pattern, 0, sizeof(struct rtl_wow_pattern));
mask_len = DIV_ROUND_UP(len, 8);
/* 1. setup A1 table */
if (memcmp(pattern, broadcast_addr, ETH_ALEN) == 0)
- wow_pattern.type = PATTERN_BROADCAST;
+ pwow_pattern->type = PATTERN_BROADCAST;
else if (memcmp(pattern, multicast_addr1, 2) == 0)
- wow_pattern.type = PATTERN_MULTICAST;
+ pwow_pattern->type = PATTERN_MULTICAST;
else if (memcmp(pattern, multicast_addr2, 3) == 0)
- wow_pattern.type = PATTERN_MULTICAST;
+ pwow_pattern->type = PATTERN_MULTICAST;
else if (memcmp(pattern, mac_addr, ETH_ALEN) == 0)
- wow_pattern.type = PATTERN_UNICAST;
+ pwow_pattern->type = PATTERN_UNICAST;
else
- wow_pattern.type = PATTERN_INVALID;
+ pwow_pattern->type = PATTERN_INVALID;
/* translate mask from os to mask for hw */
@@ -6286,6 +8056,349 @@ static int rtw_hal_set_pattern(_adapter *adapter, u8 *pattern,
/* Set bit 0-5 to zero */
mask_hw[0] &= 0xC0;
+ for (i = 0; i < (MAX_WKFM_SIZE / 4); i++) {
+ pwow_pattern->mask[i] = mask_hw[i * 4];
+ pwow_pattern->mask[i] |= (mask_hw[i * 4 + 1] << 8);
+ pwow_pattern->mask[i] |= (mask_hw[i * 4 + 2] << 16);
+ pwow_pattern->mask[i] |= (mask_hw[i * 4 + 3] << 24);
+ }
+
+ /* To get the wake up pattern from the mask.
+ * We do not count first 12 bits which means
+ * DA[6] and SA[6] in the pattern to match HW design. */
+ count = 0;
+ for (i = 12; i < len; i++) {
+ if ((mask[i / 8] >> (i % 8)) & 0x01) {
+ content[count] = pattern[i];
+ count++;
+ }
+ }
+
+ pwow_pattern->crc = rtw_calc_crc(content, count);
+
+ if (pwow_pattern->crc != 0) {
+ if (pwow_pattern->type == PATTERN_INVALID)
+ pwow_pattern->type = PATTERN_VALID;
+ }
+
+ return _SUCCESS;
+}
+
+#ifndef CONFIG_WOW_PATTERN_HW_CAM
+static void rtw_hal_set_wow_rxff_boundary(_adapter *adapter, bool wow_mode)
+{
+ u8 val8 = 0;
+ u16 rxff_bndy = 0;
+ u32 rx_dma_buff_sz = 0;
+
+ val8 = rtw_read8(adapter, REG_FIFOPAGE + 3);
+ if (val8 != 0)
+ RTW_INFO("%s:[%04x]some PKTs in TXPKTBUF\n",
+ __func__, (REG_FIFOPAGE + 3));
+
+ rtw_hal_reset_mac_rx(adapter);
+
+ if (wow_mode) {
+ rtw_hal_get_def_var(adapter, HAL_DEF_RX_DMA_SZ_WOW,
+ (u8 *)&rx_dma_buff_sz);
+ rxff_bndy = rx_dma_buff_sz - 1;
+
+ rtw_write16(adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
+ RTW_INFO("%s: wow mode, 0x%04x: 0x%04x\n", __func__,
+ REG_TRXFF_BNDY + 2,
+ rtw_read16(adapter, (REG_TRXFF_BNDY + 2)));
+ } else {
+ rtw_hal_get_def_var(adapter, HAL_DEF_RX_DMA_SZ,
+ (u8 *)&rx_dma_buff_sz);
+ rxff_bndy = rx_dma_buff_sz - 1;
+ rtw_write16(adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
+ RTW_INFO("%s: normal mode, 0x%04x: 0x%04x\n", __func__,
+ REG_TRXFF_BNDY + 2,
+ rtw_read16(adapter, (REG_TRXFF_BNDY + 2)));
+ }
+}
+
+bool rtw_read_from_frame_mask(_adapter *adapter, u8 idx)
+{
+ u32 data_l = 0, data_h = 0, rx_dma_buff_sz = 0, page_sz = 0;
+ u16 offset, rx_buf_ptr = 0;
+ u16 cam_start_offset = 0;
+ u16 ctrl_l = 0, ctrl_h = 0;
+ u8 count = 0, tmp = 0;
+ int i = 0;
+ bool res = _TRUE;
+
+ if (idx > MAX_WKFM_CAM_NUM) {
+ RTW_INFO("[Error]: %s, pattern index is out of range\n",
+ __func__);
+ return _FALSE;
+ }
+
+ rtw_hal_get_def_var(adapter, HAL_DEF_RX_DMA_SZ_WOW,
+ (u8 *)&rx_dma_buff_sz);
+
+ if (rx_dma_buff_sz == 0) {
+ RTW_INFO("[Error]: %s, rx_dma_buff_sz is 0!!\n", __func__);
+ return _FALSE;
+ }
+
+ rtw_hal_get_def_var(adapter, HAL_DEF_RX_PAGE_SIZE, (u8 *)&page_sz);
+
+ if (page_sz == 0) {
+ RTW_INFO("[Error]: %s, page_sz is 0!!\n", __func__);
+ return _FALSE;
+ }
+
+ offset = (u16)PageNum(rx_dma_buff_sz, page_sz);
+ cam_start_offset = offset * page_sz;
+
+ ctrl_l = 0x0;
+ ctrl_h = 0x0;
+
+ /* Enable RX packet buffer access */
+ rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT);
+
+ /* Read the WKFM CAM */
+ for (i = 0; i < (WKFMCAM_ADDR_NUM / 2); i++) {
+ /*
+ * Set Rx packet buffer offset.
+ * RxBufer pointer increases 1, we can access 8 bytes in Rx packet buffer.
+ * CAM start offset (unit: 1 byte) = Index*WKFMCAM_SIZE
+ * RxBufer pointer addr = (CAM start offset + per entry offset of a WKFMCAM)/8
+ * * Index: The index of the wake up frame mask
+ * * WKFMCAM_SIZE: the total size of one WKFM CAM
+ * * per entry offset of a WKFM CAM: Addr i * 4 bytes
+ */
+ rx_buf_ptr =
+ (cam_start_offset + idx * WKFMCAM_SIZE + i * 8) >> 3;
+ rtw_write16(adapter, REG_PKTBUF_DBG_CTRL, rx_buf_ptr);
+
+ rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_l);
+ data_l = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_L);
+ data_h = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H);
+
+ RTW_INFO("[%d]: %08x %08x\n", i, data_h, data_l);
+
+ count = 0;
+
+ do {
+ tmp = rtw_read8(adapter, REG_RXPKTBUF_CTRL);
+ rtw_udelay_os(2);
+ count++;
+ } while (!tmp && count < 100);
+
+ if (count >= 100) {
+ RTW_INFO("%s count:%d\n", __func__, count);
+ res = _FALSE;
+ }
+ }
+
+ /* Disable RX packet buffer access */
+ rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL,
+ DISABLE_TRXPKT_BUF_ACCESS);
+ return res;
+}
+
+bool rtw_write_to_frame_mask(_adapter *adapter, u8 idx,
+ struct rtl_wow_pattern *context)
+{
+ u32 data = 0, rx_dma_buff_sz = 0, page_sz = 0;
+ u16 offset, rx_buf_ptr = 0;
+ u16 cam_start_offset = 0;
+ u16 ctrl_l = 0, ctrl_h = 0;
+ u8 count = 0, tmp = 0;
+ int res = 0, i = 0;
+
+ if (idx > MAX_WKFM_CAM_NUM) {
+ RTW_INFO("[Error]: %s, pattern index is out of range\n",
+ __func__);
+ return _FALSE;
+ }
+
+ rtw_hal_get_def_var(adapter, HAL_DEF_RX_DMA_SZ_WOW,
+ (u8 *)&rx_dma_buff_sz);
+
+ if (rx_dma_buff_sz == 0) {
+ RTW_INFO("[Error]: %s, rx_dma_buff_sz is 0!!\n", __func__);
+ return _FALSE;
+ }
+
+ rtw_hal_get_def_var(adapter, HAL_DEF_RX_PAGE_SIZE, (u8 *)&page_sz);
+
+ if (page_sz == 0) {
+ RTW_INFO("[Error]: %s, page_sz is 0!!\n", __func__);
+ return _FALSE;
+ }
+
+ offset = (u16)PageNum(rx_dma_buff_sz, page_sz);
+
+ cam_start_offset = offset * page_sz;
+
+ if (IS_HARDWARE_TYPE_8188E(adapter)) {
+ ctrl_l = 0x0001;
+ ctrl_h = 0x0001;
+ } else {
+ ctrl_l = 0x0f01;
+ ctrl_h = 0xf001;
+ }
+
+ /* Enable RX packet buffer access */
+ rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT);
+
+ /* Write the WKFM CAM */
+ for (i = 0; i < WKFMCAM_ADDR_NUM; i++) {
+ /*
+ * Set Rx packet buffer offset.
+ * RxBufer pointer increases 1, we can access 8 bytes in Rx packet buffer.
+ * CAM start offset (unit: 1 byte) = Index*WKFMCAM_SIZE
+ * RxBufer pointer addr = (CAM start offset + per entry offset of a WKFMCAM)/8
+ * * Index: The index of the wake up frame mask
+ * * WKFMCAM_SIZE: the total size of one WKFM CAM
+ * * per entry offset of a WKFM CAM: Addr i * 4 bytes
+ */
+ rx_buf_ptr =
+ (cam_start_offset + idx * WKFMCAM_SIZE + i * 4) >> 3;
+ rtw_write16(adapter, REG_PKTBUF_DBG_CTRL, rx_buf_ptr);
+
+ if (i == 0) {
+ if (context->type == PATTERN_VALID)
+ data = BIT(31);
+ else if (context->type == PATTERN_BROADCAST)
+ data = BIT(31) | BIT(26);
+ else if (context->type == PATTERN_MULTICAST)
+ data = BIT(31) | BIT(25);
+ else if (context->type == PATTERN_UNICAST)
+ data = BIT(31) | BIT(24);
+
+ if (context->crc != 0)
+ data |= context->crc;
+
+ rtw_write32(adapter, REG_PKTBUF_DBG_DATA_L, data);
+ rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_l);
+ } else if (i == 1) {
+ data = 0;
+ rtw_write32(adapter, REG_PKTBUF_DBG_DATA_H, data);
+ rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_h);
+ } else if (i == 2 || i == 4) {
+ data = context->mask[i - 2];
+ rtw_write32(adapter, REG_PKTBUF_DBG_DATA_L, data);
+ /* write to RX packet buffer*/
+ rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_l);
+ } else if (i == 3 || i == 5) {
+ data = context->mask[i - 2];
+ rtw_write32(adapter, REG_PKTBUF_DBG_DATA_H, data);
+ /* write to RX packet buffer*/
+ rtw_write16(adapter, REG_RXPKTBUF_CTRL, ctrl_h);
+ }
+
+ count = 0;
+ do {
+ tmp = rtw_read8(adapter, REG_RXPKTBUF_CTRL);
+ rtw_udelay_os(2);
+ count++;
+ } while (tmp && count < 100);
+
+ if (count >= 100)
+ res = _FALSE;
+ else
+ res = _TRUE;
+ }
+
+ /* Disable RX packet buffer access */
+ rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL,
+ DISABLE_TRXPKT_BUF_ACCESS);
+
+ return res;
+}
+void rtw_clean_pattern(_adapter *adapter)
+{
+ struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
+ struct rtl_wow_pattern zero_pattern;
+ int i = 0;
+
+ _rtw_memset(&zero_pattern, 0, sizeof(struct rtl_wow_pattern));
+
+ zero_pattern.type = PATTERN_INVALID;
+
+ for (i = 0; i < MAX_WKFM_CAM_NUM; i++)
+ rtw_write_to_frame_mask(adapter, i, &zero_pattern);
+
+ rtw_write8(adapter, REG_WKFMCAM_NUM, 0);
+}
+static int rtw_hal_set_pattern(_adapter *adapter, u8 *pattern,
+ u8 len, u8 *mask, u8 idx)
+{
+ struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
+ struct mlme_ext_priv *pmlmeext = NULL;
+ struct mlme_ext_info *pmlmeinfo = NULL;
+ struct rtl_wow_pattern wow_pattern;
+ u8 mask_hw[MAX_WKFM_SIZE] = {0};
+ u8 content[MAX_WKFM_PATTERN_SIZE] = {0};
+ u8 broadcast_addr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+ u8 multicast_addr1[2] = {0x33, 0x33};
+ u8 multicast_addr2[3] = {0x01, 0x00, 0x5e};
+ u8 res = _FALSE, index = 0, mask_len = 0;
+ u8 mac_addr[ETH_ALEN] = {0};
+ u16 count = 0;
+ int i, j;
+
+ if (pwrctl->wowlan_pattern_idx > MAX_WKFM_CAM_NUM) {
+ RTW_INFO("%s pattern_idx is more than MAX_FMC_NUM: %d\n",
+ __func__, MAX_WKFM_CAM_NUM);
+ return _FALSE;
+ }
+
+ pmlmeext = &adapter->mlmeextpriv;
+ pmlmeinfo = &pmlmeext->mlmext_info;
+ _rtw_memcpy(mac_addr, adapter_mac_addr(adapter), ETH_ALEN);
+ _rtw_memset(&wow_pattern, 0, sizeof(struct rtl_wow_pattern));
+
+ mask_len = DIV_ROUND_UP(len, 8);
+
+ /* 1. setup A1 table */
+ if (memcmp(pattern, broadcast_addr, ETH_ALEN) == 0)
+ wow_pattern.type = PATTERN_BROADCAST;
+ else if (memcmp(pattern, multicast_addr1, 2) == 0)
+ wow_pattern.type = PATTERN_MULTICAST;
+ else if (memcmp(pattern, multicast_addr2, 3) == 0)
+ wow_pattern.type = PATTERN_MULTICAST;
+ else if (memcmp(pattern, mac_addr, ETH_ALEN) == 0)
+ wow_pattern.type = PATTERN_UNICAST;
+ else
+ wow_pattern.type = PATTERN_INVALID;
+
+ /* translate mask from os to mask for hw */
+
+/******************************************************************************
+ * pattern from OS uses 'ethenet frame', like this:
+
+ | 6 | 6 | 2 | 20 | Variable | 4 |
+ |--------+--------+------+-----------+------------+-----|
+ | 802.3 Mac Header | IP Header | TCP Packet | FCS |
+ | DA | SA | Type |
+
+ * BUT, packet catched by our HW is in '802.11 frame', begin from LLC,
+
+ | 24 or 30 | 6 | 2 | 20 | Variable | 4 |
+ |-------------------+--------+------+-----------+------------+-----|
+ | 802.11 MAC Header | LLC | IP Header | TCP Packet | FCS |
+ | Others | Tpye |
+
+ * Therefore, we need translate mask_from_OS to mask_to_hw.
+ * We should left-shift mask by 6 bits, then set the new bit[0~5] = 0,
+ * because new mask[0~5] means 'SA', but our HW packet begins from LLC,
+ * bit[0~5] corresponds to first 6 Bytes in LLC, they just don't match.
+ ******************************************************************************/
+ /* Shift 6 bits */
+ for (i = 0; i < mask_len - 1; i++) {
+ mask_hw[i] = mask[i] >> 6;
+ mask_hw[i] |= (mask[i + 1] & 0x3F) << 2;
+ }
+
+ mask_hw[i] = (mask[i] >> 6) & 0x3F;
+ /* Set bit 0-5 to zero */
+ mask_hw[0] &= 0xC0;
+
for (i = 0; i < (MAX_WKFM_SIZE / 4); i++) {
wow_pattern.mask[i] = mask_hw[i * 4];
wow_pattern.mask[i] |= (mask_hw[i * 4 + 1] << 8);
@@ -6319,52 +8432,300 @@ static int rtw_hal_set_pattern(_adapter *adapter, u8 *pattern,
/* write pattern */
res = rtw_write_to_frame_mask(adapter, index, &wow_pattern);
- if (res == _FALSE)
- RTW_INFO("%s: ERROR!! idx: %d write_to_frame_mask_cam fail\n",
- __func__, idx);
+ if (res == _FALSE)
+ RTW_INFO("%s: ERROR!! idx: %d write_to_frame_mask_cam fail\n",
+ __func__, idx);
+
+ return res;
+}
+void rtw_fill_pattern(_adapter *adapter)
+{
+ int i = 0, total = 0, index;
+ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
+ struct rtl_wow_pattern wow_pattern;
+
+ total = pwrpriv->wowlan_pattern_idx;
+
+ if (total > MAX_WKFM_CAM_NUM)
+ total = MAX_WKFM_CAM_NUM;
+
+ for (i = 0 ; i < total ; i++) {
+ if (_SUCCESS == rtw_hal_wow_pattern_generate(adapter, i, &wow_pattern)) {
+
+ index = i;
+ if (!pwrpriv->bInSuspend)
+ index += 2;
+
+ if (rtw_write_to_frame_mask(adapter, index, &wow_pattern) == _FALSE)
+ RTW_INFO("%s: ERROR!! idx: %d write_to_frame_mask_cam fail\n", __func__, i);
+ }
+
+ }
+ rtw_write8(adapter, REG_WKFMCAM_NUM, total);
+
+}
+
+#else /*CONFIG_WOW_PATTERN_HW_CAM*/
+
+#define WOW_CAM_ACCESS_TIMEOUT_MS 200
+#define WOW_VALID_BIT BIT31
+#define WOW_BC_BIT BIT26
+#define WOW_MC_BIT BIT25
+#define WOW_UC_BIT BIT24
+
+static u32 _rtw_wow_pattern_read_cam(_adapter *adapter, u8 addr)
+{
+ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
+ _mutex *mutex = &pwrpriv->wowlan_pattern_cam_mutex;
+
+ u32 rdata = 0;
+ u32 cnt = 0;
+ systime start = 0;
+ u8 timeout = 0;
+ u8 rst = _FALSE;
+
+ _enter_critical_mutex(mutex, NULL);
+
+ rtw_write32(adapter, REG_WKFMCAM_CMD, BIT_WKFCAM_POLLING_V1 | BIT_WKFCAM_ADDR_V2(addr));
+
+ start = rtw_get_current_time();
+ while (1) {
+ if (rtw_is_surprise_removed(adapter))
+ break;
+
+ cnt++;
+ if (0 == (rtw_read32(adapter, REG_WKFMCAM_CMD) & BIT_WKFCAM_POLLING_V1)) {
+ rst = _SUCCESS;
+ break;
+ }
+ if (rtw_get_passing_time_ms(start) > WOW_CAM_ACCESS_TIMEOUT_MS) {
+ timeout = 1;
+ break;
+ }
+ }
+
+ rdata = rtw_read32(adapter, REG_WKFMCAM_RWD);
+
+ _exit_critical_mutex(mutex, NULL);
+
+ /*RTW_INFO("%s ==> addr:0x%02x , rdata:0x%08x\n", __func__, addr, rdata);*/
+
+ if (timeout)
+ RTW_ERR(FUNC_ADPT_FMT" failed due to polling timeout\n", FUNC_ADPT_ARG(adapter));
+
+ return rdata;
+}
+void rtw_wow_pattern_read_cam_ent(_adapter *adapter, u8 id, struct rtl_wow_pattern *context)
+{
+ int i;
+ u32 rdata;
+
+ _rtw_memset(context, 0, sizeof(struct rtl_wow_pattern));
+
+ for (i = 4; i >= 0; i--) {
+ rdata = _rtw_wow_pattern_read_cam(adapter, (id << 3) | i);
+
+ switch (i) {
+ case 4:
+ if (rdata & WOW_BC_BIT)
+ context->type = PATTERN_BROADCAST;
+ else if (rdata & WOW_MC_BIT)
+ context->type = PATTERN_MULTICAST;
+ else if (rdata & WOW_UC_BIT)
+ context->type = PATTERN_UNICAST;
+ else
+ context->type = PATTERN_INVALID;
+
+ context->crc = rdata & 0xFFFF;
+ break;
+ default:
+ _rtw_memcpy(&context->mask[i], (u8 *)(&rdata), 4);
+ break;
+ }
+ }
+}
+
+static void _rtw_wow_pattern_write_cam(_adapter *adapter, u8 addr, u32 wdata)
+{
+ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
+ _mutex *mutex = &pwrpriv->wowlan_pattern_cam_mutex;
+ u32 cnt = 0;
+ systime start = 0, end = 0;
+ u8 timeout = 0;
+
+ /*RTW_INFO("%s ==> addr:0x%02x , wdata:0x%08x\n", __func__, addr, wdata);*/
+ _enter_critical_mutex(mutex, NULL);
+
+ rtw_write32(adapter, REG_WKFMCAM_RWD, wdata);
+ rtw_write32(adapter, REG_WKFMCAM_CMD, BIT_WKFCAM_POLLING_V1 | BIT_WKFCAM_WE | BIT_WKFCAM_ADDR_V2(addr));
+
+ start = rtw_get_current_time();
+ while (1) {
+ if (rtw_is_surprise_removed(adapter))
+ break;
+
+ cnt++;
+ if (0 == (rtw_read32(adapter, REG_WKFMCAM_CMD) & BIT_WKFCAM_POLLING_V1))
+ break;
+
+ if (rtw_get_passing_time_ms(start) > WOW_CAM_ACCESS_TIMEOUT_MS) {
+ timeout = 1;
+ break;
+ }
+ }
+ end = rtw_get_current_time();
+
+ _exit_critical_mutex(mutex, NULL);
+
+ if (timeout) {
+ RTW_ERR(FUNC_ADPT_FMT" addr:0x%02x, wdata:0x%08x, to:%u, polling:%u, %d ms\n"
+ , FUNC_ADPT_ARG(adapter), addr, wdata, timeout, cnt, rtw_get_time_interval_ms(start, end));
+ }
+}
+
+void rtw_wow_pattern_write_cam_ent(_adapter *adapter, u8 id, struct rtl_wow_pattern *context)
+{
+ int j;
+ u8 addr;
+ u32 wdata = 0;
+
+ for (j = 4; j >= 0; j--) {
+ switch (j) {
+ case 4:
+ wdata = context->crc;
+
+ if (PATTERN_BROADCAST == context->type)
+ wdata |= WOW_BC_BIT;
+ if (PATTERN_MULTICAST == context->type)
+ wdata |= WOW_MC_BIT;
+ if (PATTERN_UNICAST == context->type)
+ wdata |= WOW_UC_BIT;
+ if (PATTERN_INVALID != context->type)
+ wdata |= WOW_VALID_BIT;
+ break;
+ default:
+ wdata = context->mask[j];
+ break;
+ }
+
+ addr = (id << 3) + j;
+
+ _rtw_wow_pattern_write_cam(adapter, addr, wdata);
+ }
+}
+
+static u8 _rtw_wow_pattern_clean_cam(_adapter *adapter)
+{
+ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
+ _mutex *mutex = &pwrpriv->wowlan_pattern_cam_mutex;
+ u32 cnt = 0;
+ systime start = 0;
+ u8 timeout = 0;
+ u8 rst = _FAIL;
+
+ _enter_critical_mutex(mutex, NULL);
+ rtw_write32(adapter, REG_WKFMCAM_CMD, BIT_WKFCAM_POLLING_V1 | BIT_WKFCAM_CLR_V1);
+
+ start = rtw_get_current_time();
+ while (1) {
+ if (rtw_is_surprise_removed(adapter))
+ break;
+
+ cnt++;
+ if (0 == (rtw_read32(adapter, REG_WKFMCAM_CMD) & BIT_WKFCAM_POLLING_V1)) {
+ rst = _SUCCESS;
+ break;
+ }
+ if (rtw_get_passing_time_ms(start) > WOW_CAM_ACCESS_TIMEOUT_MS) {
+ timeout = 1;
+ break;
+ }
+ }
+ _exit_critical_mutex(mutex, NULL);
+
+ if (timeout)
+ RTW_ERR(FUNC_ADPT_FMT" falied ,polling timeout\n", FUNC_ADPT_ARG(adapter));
+
+ return rst;
+}
+
+void rtw_clean_pattern(_adapter *adapter)
+{
+ if (_FAIL == _rtw_wow_pattern_clean_cam(adapter))
+ RTW_ERR("rtw_clean_pattern failed\n");
+}
+
+void rtw_dump_wow_pattern(void *sel, struct rtl_wow_pattern *pwow_pattern, u8 idx)
+{
+ int j;
+
+ RTW_PRINT_SEL(sel, "=======WOW CAM-ID[%d]=======\n", idx);
+ RTW_PRINT_SEL(sel, "[WOW CAM] type:%d\n", pwow_pattern->type);
+ RTW_PRINT_SEL(sel, "[WOW CAM] crc:0x%04x\n", pwow_pattern->crc);
+ for (j = 0; j < 4; j++)
+ RTW_PRINT_SEL(sel, "[WOW CAM] Mask:0x%08x\n", pwow_pattern->mask[j]);
+}
+
+void rtw_fill_pattern(_adapter *adapter)
+{
+ int i = 0, total = 0;
+ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
+ struct rtl_wow_pattern wow_pattern;
+
+ total = pwrpriv->wowlan_pattern_idx;
+
+ if (total > MAX_WKFM_CAM_NUM)
+ total = MAX_WKFM_CAM_NUM;
+
+ for (i = 0 ; i < total ; i++) {
+ if (_SUCCESS == rtw_hal_wow_pattern_generate(adapter, i, &wow_pattern)) {
+ rtw_dump_wow_pattern(RTW_DBGDUMP, &wow_pattern, i);
+ rtw_wow_pattern_write_cam_ent(adapter, i, &wow_pattern);
+ }
+ }
+}
+
+#endif
+void rtw_wow_pattern_cam_dump(_adapter *adapter)
+{
+
+#ifndef CONFIG_WOW_PATTERN_HW_CAM
+ int i;
+
+ for (i = 0 ; i < MAX_WKFM_CAM_NUM; i++) {
+ RTW_INFO("=======[%d]=======\n", i);
+ rtw_read_from_frame_mask(adapter, i);
+ }
+#else
+ struct rtl_wow_pattern context;
+ int i;
+
+ for (i = 0 ; i < MAX_WKFM_CAM_NUM; i++) {
+ rtw_wow_pattern_read_cam_ent(adapter, i, &context);
+ rtw_dump_wow_pattern(RTW_DBGDUMP, &context, i);
+ }
- return res;
+#endif
}
+
static void rtw_hal_dl_pattern(_adapter *adapter, u8 mode)
{
- struct registry_priv *pregistrypriv = &adapter->registrypriv;
struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
- int i = 0, total = 0;
-
- total = pwrpriv->wowlan_pattern_idx;
-
- if (total > MAX_WKFM_NUM)
- total = MAX_WKFM_NUM;
-
- rtw_clean_pattern(adapter);
switch (mode) {
case 0:
- RTW_INFO("%s: total patterns: %d\n", __func__, total);
+ rtw_clean_pattern(adapter);
+ RTW_INFO("%s: total patterns: %d\n", __func__, pwrpriv->wowlan_pattern_idx);
break;
case 1:
rtw_set_default_pattern(adapter);
- for (i = 0 ; i < total ; i++) {
- rtw_hal_set_pattern(adapter,
- pwrpriv->patterns[i].content,
- pwrpriv->patterns[i].len,
- pwrpriv->patterns[i].mask, i);
- }
- rtw_write8(adapter, REG_WKFMCAM_NUM, total);
- RTW_INFO("%s: pattern total: %d downloaded\n",
- __func__, total);
+ rtw_fill_pattern(adapter);
+ RTW_INFO("%s: pattern total: %d downloaded\n", __func__, pwrpriv->wowlan_pattern_idx);
break;
case 2:
- pwrpriv->wowlan_pattern_idx = DEFAULT_PATTERN_NUM;
-
- for (i = DEFAULT_PATTERN_NUM ; i < MAX_WKFM_NUM ; i++) {
- _rtw_memset(pwrpriv->patterns[i].content, '\0',
- sizeof(pwrpriv->patterns[i].content));
- _rtw_memset(pwrpriv->patterns[i].mask, '\0',
- sizeof(pwrpriv->patterns[i].mask));
- pwrpriv->patterns[i].len = 0;
- }
+ rtw_clean_pattern(adapter);
+ rtw_wow_pattern_sw_reset(adapter);
RTW_INFO("%s: clean patterns\n", __func__);
break;
default:
@@ -6378,8 +8739,9 @@ static void rtw_hal_wow_enable(_adapter *adapter)
struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
struct security_priv *psecuritypriv = &adapter->securitypriv;
struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
- struct hal_ops *pHalFunc = &adapter->HalFunc;
+ struct hal_ops *pHalFunc = &adapter->hal_func;
struct sta_info *psta = NULL;
+ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
int res;
u16 media_status_rpt;
@@ -6387,35 +8749,45 @@ static void rtw_hal_wow_enable(_adapter *adapter)
RTW_PRINT("%s, WOWLAN_ENABLE\n", __func__);
rtw_hal_gate_bb(adapter, _TRUE);
#ifdef CONFIG_GTK_OL
- if (psecuritypriv->dot11PrivacyAlgrthm == _AES_)
+ if (psecuritypriv->binstallKCK_KEK == _TRUE)
rtw_hal_fw_sync_cam_id(adapter);
#endif
if (IS_HARDWARE_TYPE_8723B(adapter))
rtw_hal_backup_rate(adapter);
+ rtw_hal_fw_dl(adapter, _TRUE);
+ media_status_rpt = RT_MEDIA_CONNECT;
+ rtw_hal_set_hwreg(adapter, HW_VAR_H2C_FW_JOINBSSRPT,
+ (u8 *)&media_status_rpt);
+
/* RX DMA stop */
+ #if defined(CONFIG_RTL8188E)
if (IS_HARDWARE_TYPE_8188E(adapter))
rtw_hal_disable_tx_report(adapter);
+ #endif
res = rtw_hal_pause_rx_dma(adapter);
if (res == _FAIL)
RTW_PRINT("[WARNING] pause RX DMA fail\n");
+ #ifndef CONFIG_WOW_PATTERN_HW_CAM
/* Reconfig RX_FF Boundary */
rtw_hal_set_wow_rxff_boundary(adapter, _TRUE);
+ #endif
/* redownload wow pattern */
rtw_hal_dl_pattern(adapter, 1);
- rtw_hal_fw_dl(adapter, _TRUE);
- media_status_rpt = RT_MEDIA_CONNECT;
- rtw_hal_set_hwreg(adapter, HW_VAR_H2C_FW_JOINBSSRPT,
- (u8 *)&media_status_rpt);
-
if (!pwrctl->wowlan_pno_enable) {
psta = rtw_get_stainfo(&adapter->stapriv, get_bssid(pmlmepriv));
- if (psta != NULL)
+
+ if (psta != NULL) {
+ #ifdef CONFIG_FW_MULTI_PORT_SUPPORT
+ rtw_hal_set_default_port_id_cmd(adapter, psta->cmn.mac_id);
+ #endif
+
rtw_sta_media_status_rpt(adapter, psta, 1);
+ }
}
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
@@ -6443,25 +8815,80 @@ static void rtw_hal_wow_enable(_adapter *adapter)
pwrctl->wowlan_wake_reason);
#ifdef CONFIG_GTK_OL_DBG
dump_sec_cam(RTW_DBGDUMP, adapter);
+ dump_sec_cam_cache(RTW_DBGDUMP, adapter);
#endif
#ifdef CONFIG_USB_HCI
/* free adapter's resource */
rtw_mi_intf_stop(adapter);
+#endif
+#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
/* Invoid SE0 reset signal during suspending*/
rtw_write8(adapter, REG_RSV_CTRL, 0x20);
- rtw_write8(adapter, REG_RSV_CTRL, 0x60);
-#endif /*CONFIG_USB_HCI*/
+ if (IS_8188F(pHalData->version_id) == FALSE)
+ rtw_write8(adapter, REG_RSV_CTRL, 0x60);
+#endif
rtw_hal_gate_bb(adapter, _FALSE);
}
+#define DBG_WAKEUP_REASON
+#ifdef DBG_WAKEUP_REASON
+void _dbg_wake_up_reason_string(_adapter *adapter, const char *srt_res)
+{
+ RTW_INFO(ADPT_FMT "- wake up reason - %s\n", ADPT_ARG(adapter), srt_res);
+}
+void _dbg_rtw_wake_up_reason(_adapter *adapter, u8 reason)
+{
+ if (RX_PAIRWISEKEY == reason)
+ _dbg_wake_up_reason_string(adapter, "Rx pairwise key");
+ else if (RX_GTK == reason)
+ _dbg_wake_up_reason_string(adapter, "Rx GTK");
+ else if (RX_FOURWAY_HANDSHAKE == reason)
+ _dbg_wake_up_reason_string(adapter, "Rx four way handshake");
+ else if (RX_DISASSOC == reason)
+ _dbg_wake_up_reason_string(adapter, "Rx disassoc");
+ else if (RX_DEAUTH == reason)
+ _dbg_wake_up_reason_string(adapter, "Rx deauth");
+ else if (RX_ARP_REQUEST == reason)
+ _dbg_wake_up_reason_string(adapter, "Rx ARP request");
+ else if (FW_DECISION_DISCONNECT == reason)
+ _dbg_wake_up_reason_string(adapter, "FW detect disconnect");
+ else if (RX_MAGIC_PKT == reason)
+ _dbg_wake_up_reason_string(adapter, "Rx magic packet");
+ else if (RX_UNICAST_PKT == reason)
+ _dbg_wake_up_reason_string(adapter, "Rx unicast packet");
+ else if (RX_PATTERN_PKT == reason)
+ _dbg_wake_up_reason_string(adapter, "Rx pattern packet");
+ else if (RTD3_SSID_MATCH == reason)
+ _dbg_wake_up_reason_string(adapter, "RTD3 SSID match");
+ else if (RX_REALWOW_V2_WAKEUP_PKT == reason)
+ _dbg_wake_up_reason_string(adapter, "Rx real WOW V2 wakeup packet");
+ else if (RX_REALWOW_V2_ACK_LOST == reason)
+ _dbg_wake_up_reason_string(adapter, "Rx real WOW V2 ack lost");
+ else if (ENABLE_FAIL_DMA_IDLE == reason)
+ _dbg_wake_up_reason_string(adapter, "enable fail DMA idle");
+ else if (ENABLE_FAIL_DMA_PAUSE == reason)
+ _dbg_wake_up_reason_string(adapter, "enable fail DMA pause");
+ else if (AP_OFFLOAD_WAKEUP == reason)
+ _dbg_wake_up_reason_string(adapter, "AP offload wakeup");
+ else if (CLK_32K_UNLOCK == reason)
+ _dbg_wake_up_reason_string(adapter, "clk 32k unlock");
+ else if (RTIME_FAIL_DMA_IDLE == reason)
+ _dbg_wake_up_reason_string(adapter, "RTIME fail DMA idle");
+ else if (CLK_32K_LOCK == reason)
+ _dbg_wake_up_reason_string(adapter, "clk 32k lock");
+ else
+ _dbg_wake_up_reason_string(adapter, "unknown reasoen");
+}
+#endif
+
static void rtw_hal_wow_disable(_adapter *adapter)
{
struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
struct security_priv *psecuritypriv = &adapter->securitypriv;
struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
- struct hal_ops *pHalFunc = &adapter->HalFunc;
+ struct hal_ops *pHalFunc = &adapter->hal_func;
struct sta_info *psta = NULL;
int res;
u16 media_status_rpt;
@@ -6480,12 +8907,17 @@ static void rtw_hal_wow_disable(_adapter *adapter)
if (0) {
RTW_INFO("0x630:0x%02x\n", rtw_read8(adapter, 0x630));
RTW_INFO("0x631:0x%02x\n", rtw_read8(adapter, 0x631));
+ RTW_INFO("0x634:0x%02x\n", rtw_read8(adapter, 0x634));
+ RTW_INFO("0x1c7:0x%02x\n", rtw_read8(adapter, 0x1c7));
}
pwrctl->wowlan_wake_reason = rtw_read8(adapter, REG_WOWLAN_WAKE_REASON);
RTW_PRINT("wakeup_reason: 0x%02x\n",
pwrctl->wowlan_wake_reason);
+ #ifdef DBG_WAKEUP_REASON
+ _dbg_rtw_wake_up_reason(adapter, pwrctl->wowlan_wake_reason);
+ #endif
rtw_hal_set_fw_wow_related_cmd(adapter, 0);
@@ -6505,40 +8937,57 @@ static void rtw_hal_wow_disable(_adapter *adapter)
/* clean HW pattern match */
rtw_hal_dl_pattern(adapter, 0);
+ #ifndef CONFIG_WOW_PATTERN_HW_CAM
/* config RXFF boundary to original */
rtw_hal_set_wow_rxff_boundary(adapter, _FALSE);
-
+ #endif
rtw_hal_release_rx_dma(adapter);
+ #if defined(CONFIG_RTL8188E)
if (IS_HARDWARE_TYPE_8188E(adapter))
rtw_hal_enable_tx_report(adapter);
+ #endif
- rtw_hal_update_tx_iv(adapter);
-
-#ifdef CONFIG_GTK_OL
- if (psecuritypriv->dot11PrivacyAlgrthm == _AES_)
- rtw_hal_update_gtk_offload_info(adapter);
-#endif /*CONFIG_GTK_OL*/
+ if ((pwrctl->wowlan_wake_reason != RX_DISASSOC) ||
+ (pwrctl->wowlan_wake_reason != RX_DEAUTH) ||
+ (pwrctl->wowlan_wake_reason != FW_DECISION_DISCONNECT)) {
+ rtw_hal_get_aoac_rpt(adapter);
+ rtw_hal_update_sw_security_info(adapter);
+ }
rtw_hal_fw_dl(adapter, _FALSE);
#ifdef CONFIG_GPIO_WAKEUP
+
+#ifdef CONFIG_WAKEUP_GPIO_INPUT_MODE
+ if (pwrctl->is_high_active == 0)
+ rtw_hal_set_input_gpio(adapter, WAKEUP_GPIO_IDX);
+ else
+ rtw_hal_set_output_gpio(adapter, WAKEUP_GPIO_IDX, 0);
+#else
val8 = (pwrctl->is_high_active == 0) ? 1 : 0;
RTW_PRINT("Set Wake GPIO to default(%d).\n", val8);
+
rtw_hal_set_output_gpio(adapter, WAKEUP_GPIO_IDX, val8);
+ rtw_hal_switch_gpio_wl_ctrl(adapter, WAKEUP_GPIO_IDX, _FALSE);
#endif
- if ((pwrctl->wowlan_wake_reason != FWDecisionDisconnect) &&
- (pwrctl->wowlan_wake_reason != Rx_Pairwisekey) &&
- (pwrctl->wowlan_wake_reason != Rx_DisAssoc) &&
- (pwrctl->wowlan_wake_reason != Rx_DeAuth)) {
+#endif
+ if ((pwrctl->wowlan_wake_reason != FW_DECISION_DISCONNECT) &&
+ (pwrctl->wowlan_wake_reason != RX_PAIRWISEKEY) &&
+ (pwrctl->wowlan_wake_reason != RX_DISASSOC) &&
+ (pwrctl->wowlan_wake_reason != RX_DEAUTH)) {
media_status_rpt = RT_MEDIA_CONNECT;
rtw_hal_set_hwreg(adapter, HW_VAR_H2C_FW_JOINBSSRPT,
(u8 *)&media_status_rpt);
- if (psta != NULL)
+ if (psta != NULL) {
+ #ifdef CONFIG_FW_MULTI_PORT_SUPPORT
+ rtw_hal_set_default_port_id_cmd(adapter, psta->cmn.mac_id);
+ #endif
rtw_sta_media_status_rpt(adapter, psta, 1);
+ }
}
rtw_hal_gate_bb(adapter, _FALSE);
}
@@ -6569,6 +9018,9 @@ void rtw_hal_set_p2p_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index,
*page_num += CurtPktPageNum;
index += (CurtPktPageNum * page_size);
+ #ifdef DBG_RSVD_PAGE_CFG
+ RSVD_PAGE_CFG("WOW-P2P-Beacon", CurtPktPageNum, *page_num, 0);
+ #endif
/* P2P Probe rsp */
rsvd_page_loc->LocP2PProbeRsp = *page_num;
@@ -6585,6 +9037,9 @@ void rtw_hal_set_p2p_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index,
*page_num += CurtPktPageNum;
index += (CurtPktPageNum * page_size);
+ #ifdef DBG_RSVD_PAGE_CFG
+ RSVD_PAGE_CFG("WOW-P2P-ProbeRsp", CurtPktPageNum, *page_num, 0);
+ #endif
/* P2P nego rsp */
rsvd_page_loc->LocNegoRsp = *page_num;
@@ -6601,6 +9056,9 @@ void rtw_hal_set_p2p_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index,
*page_num += CurtPktPageNum;
index += (CurtPktPageNum * page_size);
+ #ifdef DBG_RSVD_PAGE_CFG
+ RSVD_PAGE_CFG("WOW-P2P-NegoRsp", CurtPktPageNum, *page_num, 0);
+ #endif
/* P2P invite rsp */
rsvd_page_loc->LocInviteRsp = *page_num;
@@ -6617,6 +9075,9 @@ void rtw_hal_set_p2p_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index,
*page_num += CurtPktPageNum;
index += (CurtPktPageNum * page_size);
+ #ifdef DBG_RSVD_PAGE_CFG
+ RSVD_PAGE_CFG("WOW-P2P-InviteRsp", CurtPktPageNum, *page_num, 0);
+ #endif
/* P2P provision discovery rsp */
rsvd_page_loc->LocPDRsp = *page_num;
@@ -6634,6 +9095,9 @@ void rtw_hal_set_p2p_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index,
*page_num += CurtPktPageNum;
*total_pkt_len = index + P2PPDRspLength;
+ #ifdef DBG_RSVD_PAGE_CFG
+ RSVD_PAGE_CFG("WOW-P2P-PDR", CurtPktPageNum, *page_num, *total_pkt_len);
+ #endif
index += (CurtPktPageNum * page_size);
@@ -6641,73 +9105,76 @@ void rtw_hal_set_p2p_wow_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 index,
}
#endif /* CONFIG_P2P_WOWLAN */
-#ifdef CONFIG_LPS_PG
- #define LPSPG_RSVD_PAGE_SET_MACID(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 0, 8, _value)/*used macid*/
- #define LPSPG_RSVD_PAGE_SET_MBSSCAMID(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 8, 8, _value)/*used BSSID CAM entry*/
- #define LPSPG_RSVD_PAGE_SET_PMC_NUM(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 16, 8, _value)/*Max used Pattern Match CAM entry*/
- #define LPSPG_RSVD_PAGE_SET_MU_RAID_GID(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 24, 8, _value)/*Max MU rate table Group ID*/
- #define LPSPG_RSVD_PAGE_SET_SEC_CAM_NUM(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x04, 0, 8, _value)/*used Security CAM entry number*/
- #define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID1(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 0, 8, _value)/*used Security CAM entry -1*/
- #define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID2(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 8, 8, _value)/*used Security CAM entry -2*/
- #define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID3(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 16, 8, _value)/*used Security CAM entry -3*/
- #define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID4(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 24, 8, _value)/*used Security CAM entry -4*/
- #define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID5(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 0, 8, _value)/*used Security CAM entry -5*/
- #define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID6(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 8, 8, _value)/*used Security CAM entry -6*/
- #define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID7(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 16, 8, _value)/*used Security CAM entry -7*/
- #define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID8(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 24, 8, _value)/*used Security CAM entry -8*/
-#endif
#ifdef CONFIG_LPS_PG
#include "hal_halmac.h"
#define DBG_LPSPG_SEC_DUMP
#define LPS_PG_INFO_RSVD_LEN 16
+#define LPS_PG_INFO_RSVD_PAGE_NUM 1
+#define DBG_LPSPG_INFO_DUMP
static void rtw_hal_set_lps_pg_info_rsvd_page(_adapter *adapter)
{
- u8 cur_pag_num = 0;
struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
struct sta_info *psta = rtw_get_stainfo(&adapter->stapriv, get_bssid(&adapter->mlmepriv));
struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+ PHAL_DATA_TYPE phal_data = GET_HAL_DATA(adapter);
u8 lps_pg_info[LPS_PG_INFO_RSVD_LEN] = {0};
#ifdef CONFIG_MBSSID_CAM
u8 cam_id = INVALID_CAM_ID;
#endif
u8 *psec_cam_id = lps_pg_info + 8;
u8 sec_cam_num = 0;
+ u8 drv_rsvdpage_num = 0;
if (!psta) {
- RTW_INFO("%s [ERROR] sta is NULL\n", __func__);
+ RTW_ERR("%s [ERROR] sta is NULL\n", __func__);
rtw_warn_on(1);
return;
}
- LPSPG_RSVD_PAGE_SET_MACID(lps_pg_info, psta->mac_id); /*used macid*/
- RTW_INFO("[LPSPG-INFO] mac_id:%d\n", psta->mac_id);
+ /*Byte 0 - used macid*/
+ LPSPG_RSVD_PAGE_SET_MACID(lps_pg_info, psta->cmn.mac_id);
+ RTW_INFO("[LPSPG-INFO] mac_id:%d\n", psta->cmn.mac_id);
#ifdef CONFIG_MBSSID_CAM
+ /*Byte 1 - used BSSID CAM entry*/
cam_id = rtw_mbid_cam_search_by_ifaceid(adapter, adapter->iface_id);
if (cam_id != INVALID_CAM_ID)
- LPSPG_RSVD_PAGE_SET_MBSSCAMID(lps_pg_info, cam_id); /*used BSSID CAM entry*/
+ LPSPG_RSVD_PAGE_SET_MBSSCAMID(lps_pg_info, cam_id);
RTW_INFO("[LPSPG-INFO] mbss_cam_id:%d\n", cam_id);
#endif
#ifdef CONFIG_WOWLAN /*&& pattern match cam used*/
+ /*Btye 2 - Max used Pattern Match CAM entry*/
if (pwrpriv->wowlan_mode == _TRUE &&
check_fwstate(&adapter->mlmepriv, _FW_LINKED) == _TRUE) {
- LPSPG_RSVD_PAGE_SET_PMC_NUM(lps_pg_info, pwrpriv->wowlan_pattern_idx); /*Max used Pattern Match CAM entry*/
- RTW_INFO("[LPSPG-INFO] Max Pattern Match CAM entry :%d\n", _value);
+ LPSPG_RSVD_PAGE_SET_PMC_NUM(lps_pg_info, pwrpriv->wowlan_pattern_idx);
+ RTW_INFO("[LPSPG-INFO] Max Pattern Match CAM entry :%d\n", pwrpriv->wowlan_pattern_idx);
}
#endif
#ifdef CONFIG_BEAMFORMING /*&& MU BF*/
- LPSPG_RSVD_PAGE_SET_MU_RAID_GID(lps_pg_info, _value); /*Max MU rate table Group ID*/
- RTW_INFO("[LPSPG-INFO] Max MU rate table Group ID :%d\n", _value);
+ /*Btye 3 - Max MU rate table Group ID*/
+ LPSPG_RSVD_PAGE_SET_MU_RAID_GID(lps_pg_info, 0);
+ RTW_INFO("[LPSPG-INFO] Max MU rate table Group ID :%d\n", 0);
#endif
+ /*Btye 8 ~15 - used Security CAM entry */
sec_cam_num = rtw_get_sec_camid(adapter, 8, psec_cam_id);
+
+ /*Btye 4 - used Security CAM entry number*/
if (sec_cam_num < 8)
- LPSPG_RSVD_PAGE_SET_SEC_CAM_NUM(lps_pg_info, sec_cam_num); /*used Security CAM entry number*/
+ LPSPG_RSVD_PAGE_SET_SEC_CAM_NUM(lps_pg_info, sec_cam_num);
RTW_INFO("[LPSPG-INFO] Security CAM entry number :%d\n", sec_cam_num);
+ /*Btye 5 - Txbuf used page number for fw offload*/
+ if (pwrpriv->wowlan_mode == _TRUE || pwrpriv->wowlan_ap_mode == _TRUE)
+ drv_rsvdpage_num = rtw_hal_get_txbuff_rsvd_page_num(adapter, _TRUE);
+ else
+ drv_rsvdpage_num = rtw_hal_get_txbuff_rsvd_page_num(adapter, _FALSE);
+ LPSPG_RSVD_PAGE_SET_DRV_RSVDPAGE_NUM(lps_pg_info, drv_rsvdpage_num);
+ RTW_INFO("[LPSPG-INFO] DRV's rsvd page numbers :%d\n", drv_rsvdpage_num);
+
#ifdef DBG_LPSPG_SEC_DUMP
{
int i;
@@ -6730,9 +9197,13 @@ static void rtw_hal_set_lps_pg_info_rsvd_page(_adapter *adapter)
rtw_halmac_download_rsvd_page(dvobj, pwrpriv->lpspg_rsvd_page_locate, lps_pg_info, LPS_PG_INFO_RSVD_LEN);
+#ifdef DBG_LPSPG_INFO_DUMP
+ RTW_INFO("Get LPS-PG INFO from rsvd page_offset:%d\n", pwrpriv->lpspg_rsvd_page_locate);
+ rtw_dump_rsvd_page(RTW_DBGDUMP, adapter, pwrpriv->lpspg_rsvd_page_locate, 1);
+#endif
}
-#define DBG_LPSPG_INFO_DUMP
+
static u8 rtw_hal_set_lps_pg_info_cmd(_adapter *adapter)
{
struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
@@ -6749,7 +9220,7 @@ static u8 rtw_hal_set_lps_pg_info_cmd(_adapter *adapter)
SET_H2CCMD_LPSPG_MBID_CAM_EN(lpspg_info, 1); /*BSSIDCAM_En*/
#endif
-#ifdef CONFIG_WOWLAN /*&& pattern match cam used*/
+#if defined(CONFIG_WOWLAN) && defined(CONFIG_WOW_PATTERN_HW_CAM)
if (pwrpriv->wowlan_mode == _TRUE &&
check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {
@@ -6787,11 +9258,77 @@ static u8 rtw_hal_set_lps_pg_info_cmd(_adapter *adapter)
u8 rtw_hal_set_lps_pg_info(_adapter *adapter)
{
u8 ret = _FAIL;
+ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
+
+ if (pwrpriv->lpspg_rsvd_page_locate == 0) {
+ RTW_ERR("%s [ERROR] lpspg_rsvd_page_locate = 0\n", __func__);
+ rtw_warn_on(1);
+ return ret;
+ }
rtw_hal_set_lps_pg_info_rsvd_page(adapter);
ret = rtw_hal_set_lps_pg_info_cmd(adapter);
+ if (_SUCCESS == ret)
+ pwrpriv->blpspg_info_up = _FALSE;
+
return ret;
}
+
+void rtw_hal_lps_pg_rssi_lv_decide(_adapter *adapter, struct sta_info *sta)
+{
+#if 0
+ if (sta->cmn.ra_info.rssi_level >= 4)
+ sta->lps_pg_rssi_lv = 3; /*RSSI High - 1SS_VHT_MCS7*/
+ else if (sta->cmn.ra_info.rssi_level >= 2)
+ sta->lps_pg_rssi_lv = 2; /*RSSI Middle - 1SS_VHT_MCS3*/
+ else
+ sta->lps_pg_rssi_lv = 1; /*RSSI Lower - Lowest_rate*/
+#else
+ sta->lps_pg_rssi_lv = 0;
+#endif
+ RTW_INFO("%s mac-id:%d, rssi:%d, rssi_level:%d, lps_pg_rssi_lv:%d\n",
+ __func__, sta->cmn.mac_id, sta->cmn.rssi_stat.rssi, sta->cmn.ra_info.rssi_level, sta->lps_pg_rssi_lv);
+}
+
+void rtw_hal_lps_pg_handler(_adapter *adapter, enum lps_pg_hdl_id hdl_id)
+{
+ switch (hdl_id) {
+ case LPS_PG_INFO_CFG:
+ rtw_hal_set_lps_pg_info(adapter);
+ break;
+ case LPS_PG_REDLEMEM:
+ {
+ /*set xmit_block*/
+ rtw_set_xmit_block(adapter, XMIT_BLOCK_REDLMEM);
+ if (_FAIL == rtw_hal_fw_mem_dl(adapter, FW_EMEM))
+ rtw_warn_on(1);
+ /*clearn xmit_block*/
+ rtw_clr_xmit_block(adapter, XMIT_BLOCK_REDLMEM);
+ }
+ break;
+
+ case LPS_PG_RESEND_H2C:
+ {
+ struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl;
+ struct sta_info *sta;
+ int i;
+
+ for (i = 0; i < MACID_NUM_SW_LIMIT; i++) {
+ sta = macid_ctl->sta[i];
+ if (sta && !is_broadcast_mac_addr(sta->cmn.mac_addr)) {
+ rtw_hal_lps_pg_rssi_lv_decide(adapter, sta);
+ set_sta_rate(adapter, sta);
+ sta->lps_pg_rssi_lv = 0;
+ }
+ }
+ }
+ break;
+
+ default:
+ break;
+ }
+}
+
#endif /*CONFIG_LPS_PG*/
/*
@@ -6803,24 +9340,30 @@ u8 rtw_hal_set_lps_pg_info(_adapter *adapter)
* so we need to set the packet length to total lengh.
* TRUE: At the second time, we should send the first packet (default:beacon)
* to Hw again and set the lengh in descriptor to the real beacon lengh.
+ * page_num - The amount of reserved page which driver need.
+ * If this is not NULL, this function doesn't real download reserved
+ * page, but just count the number of reserved page.
+ *
* 2009.10.15 by tynli.
+ * 2017.06.20 modified by Lucas.
*
* Page Size = 128: 8188e, 8723a/b, 8192c/d,
* Page Size = 256: 8192e, 8821a
* Page Size = 512: 8812a
*/
-void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished)
+/*#define DBG_DUMP_SET_RSVD_PAGE*/
+static void _rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished, u8 *page_num)
{
PHAL_DATA_TYPE pHalData;
- struct xmit_frame *pcmdframe;
+ struct xmit_frame *pcmdframe = NULL;
struct pkt_attrib *pattrib;
struct xmit_priv *pxmitpriv;
struct mlme_ext_priv *pmlmeext;
struct mlme_ext_info *pmlmeinfo;
struct pwrctrl_priv *pwrctl;
struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
- struct hal_ops *pHalFunc = &adapter->HalFunc;
+ struct hal_ops *pHalFunc = &adapter->hal_func;
u32 BeaconLength = 0, ProbeRspLength = 0, PSPollLength = 0;
u32 NullDataLength = 0, QosNullLength = 0, BTQosNullLength = 0;
u32 ProbeReqLength = 0, NullFunctionDataLength = 0;
@@ -6831,6 +9374,10 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished)
u32 TotalPacketLen = 0, MaxRsvdPageBufSize = 0, PageSize = 0;
RSVDPAGE_LOC RsvdPageLoc;
+#ifdef DBG_FW_DEBUG_MSG_PKT
+ u32 fw_dbg_msg_pkt_len = 0;
+#endif /*DBG_FW_DEBUG_MSG_PKT*/
+
#ifdef DBG_CONFIG_ERROR_DETECT
struct sreset_priv *psrtpriv;
#endif /* DBG_CONFIG_ERROR_DETECT */
@@ -6855,33 +9402,42 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished)
return;
}
- if (pwrctl->wowlan_mode == _TRUE || pwrctl->wowlan_ap_mode == _TRUE)
- RsvdPageNum = rtw_hal_get_txbuff_rsvd_page_num(adapter, _TRUE);
- else
- RsvdPageNum = rtw_hal_get_txbuff_rsvd_page_num(adapter, _FALSE);
-
- RTW_INFO("%s PageSize: %d, RsvdPageNUm: %d\n", __func__, PageSize, RsvdPageNum);
+ /* Prepare ReservedPagePacket */
+ if (page_num) {
+ ReservedPagePacket = rtw_zmalloc(MAX_CMDBUF_SZ);
+ if (!ReservedPagePacket) {
+ RTW_WARN("%s: alloc ReservedPagePacket fail!\n", __FUNCTION__);
+ *page_num = 0xFF;
+ return;
+ }
+ } else {
+ if (pwrctl->wowlan_mode == _TRUE || pwrctl->wowlan_ap_mode == _TRUE)
+ RsvdPageNum = rtw_hal_get_txbuff_rsvd_page_num(adapter, _TRUE);
+ else
+ RsvdPageNum = rtw_hal_get_txbuff_rsvd_page_num(adapter, _FALSE);
- MaxRsvdPageBufSize = RsvdPageNum * PageSize;
+ RTW_INFO("%s PageSize: %d, RsvdPageNUm: %d\n", __func__, PageSize, RsvdPageNum);
- if (MaxRsvdPageBufSize > MAX_CMDBUF_SZ) {
- RTW_INFO("%s MaxRsvdPageBufSize(%d) is larger than MAX_CMDBUF_SZ(%d)",
- __func__, MaxRsvdPageBufSize, MAX_CMDBUF_SZ);
- rtw_warn_on(1);
- return;
- }
+ MaxRsvdPageBufSize = RsvdPageNum * PageSize;
+ if (MaxRsvdPageBufSize > MAX_CMDBUF_SZ) {
+ RTW_ERR("%s MaxRsvdPageBufSize(%d) is larger than MAX_CMDBUF_SZ(%d)",
+ __func__, MaxRsvdPageBufSize, MAX_CMDBUF_SZ);
+ rtw_warn_on(1);
+ return;
+ }
- pcmdframe = rtw_alloc_cmdxmitframe(pxmitpriv);
+ pcmdframe = rtw_alloc_cmdxmitframe(pxmitpriv);
+ if (pcmdframe == NULL) {
+ RTW_ERR("%s: alloc ReservedPagePacket fail!\n", __FUNCTION__);
+ return;
+ }
- if (pcmdframe == NULL) {
- RTW_INFO("%s: alloc ReservedPagePacket fail!\n", __FUNCTION__);
- return;
+ ReservedPagePacket = pcmdframe->buf_addr;
}
- ReservedPagePacket = pcmdframe->buf_addr;
_rtw_memset(&RsvdPageLoc, 0, sizeof(RSVDPAGE_LOC));
- /* beacon * 2 pages */
+ /* beacon * 1 pages */
BufIndex = TxDescOffset;
rtw_hal_construct_beacon(adapter,
&ReservedPagePacket[BufIndex], &BeaconLength);
@@ -6891,14 +9447,15 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished)
* packet, it will be filled in front of the packet in TXPKTBUF.
*/
CurtPktPageNum = (u8)PageNum((TxDescLen + BeaconLength), PageSize);
- /* If we don't add 1 more page, ARP offload function will fail at 8723bs.*/
- if (CurtPktPageNum == 1)
- CurtPktPageNum += 1;
TotalPageNum += CurtPktPageNum;
BufIndex += (CurtPktPageNum * PageSize);
+ #ifdef DBG_RSVD_PAGE_CFG
+ RSVD_PAGE_CFG("Beacon", CurtPktPageNum, TotalPageNum, TotalPacketLen);
+ #endif
+
if (pwrctl->wowlan_ap_mode == _TRUE) {
/* (4) probe response*/
RsvdPageLoc.LocProbeRsp = TotalPageNum;
@@ -6914,6 +9471,9 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished)
TotalPageNum += CurtPktPageNum;
TotalPacketLen = BufIndex + ProbeRspLength;
BufIndex += (CurtPktPageNum * PageSize);
+ #ifdef DBG_RSVD_PAGE_CFG
+ RSVD_PAGE_CFG("ProbeRsp", CurtPktPageNum, TotalPageNum, TotalPacketLen);
+ #endif
goto download_page;
}
@@ -6931,39 +9491,51 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished)
TotalPageNum += CurtPktPageNum;
BufIndex += (CurtPktPageNum * PageSize);
+ #ifdef DBG_RSVD_PAGE_CFG
+ RSVD_PAGE_CFG("PSPoll", CurtPktPageNum, TotalPageNum, TotalPacketLen);
+ #endif
#ifdef CONFIG_BT_COEXIST
- /* BT Qos null data * 1 page */
- RsvdPageLoc.LocBTQosNull = TotalPageNum;
- RTW_INFO("LocBTQosNull: %d\n", RsvdPageLoc.LocBTQosNull);
- rtw_hal_construct_NullFunctionData(
- adapter,
- &ReservedPagePacket[BufIndex],
- &BTQosNullLength,
- get_my_bssid(&pmlmeinfo->network),
- _TRUE, 0, 0, _FALSE);
- rtw_hal_fill_fake_txdesc(adapter,
- &ReservedPagePacket[BufIndex - TxDescLen],
- BTQosNullLength, _FALSE, _TRUE, _FALSE);
+ if (pwrctl->wowlan_mode == _FALSE ||
+ pwrctl->wowlan_in_resume == _TRUE) {
+ /* BT Qos null data * 1 page */
+ RsvdPageLoc.LocBTQosNull = TotalPageNum;
- CurtPktPageNum = (u8)PageNum(TxDescLen + BTQosNullLength, PageSize);
+ RTW_INFO("LocBTQosNull: %d\n", RsvdPageLoc.LocBTQosNull);
- TotalPageNum += CurtPktPageNum;
+ rtw_hal_construct_NullFunctionData(adapter,
+ &ReservedPagePacket[BufIndex],
+ &BTQosNullLength,
+ get_my_bssid(&pmlmeinfo->network),
+ _TRUE, 0, 0, _FALSE);
- BufIndex += (CurtPktPageNum * PageSize);
+ rtw_hal_fill_fake_txdesc(adapter,
+ &ReservedPagePacket[BufIndex - TxDescLen],
+ BTQosNullLength, _FALSE, _TRUE, _FALSE);
+
+ CurtPktPageNum = (u8)PageNum(TxDescLen + BTQosNullLength,
+ PageSize);
+
+ TotalPageNum += CurtPktPageNum;
+ BufIndex += (CurtPktPageNum * PageSize);
+
+ #ifdef DBG_RSVD_PAGE_CFG
+ RSVD_PAGE_CFG("BTQosNull", CurtPktPageNum, TotalPageNum, TotalPacketLen);
+ #endif
+ }
#endif /* CONFIG_BT_COEXIT */
#ifdef CONFIG_MCC_MODE
if (MCC_EN(adapter)) {
dl_mcc_page = rtw_hal_dl_mcc_fw_rsvd_page(adapter, ReservedPagePacket,
- &BufIndex, TxDescLen, PageSize,
- &TotalPageNum, &TotalPacketLen, &RsvdPageLoc);
- } else
+ &BufIndex, TxDescLen, PageSize, &TotalPageNum, &RsvdPageLoc, page_num);
+ } else {
dl_mcc_page = _FAIL;
+ }
- if (dl_mcc_page == _FAIL) {
+ if (dl_mcc_page == _FAIL)
#endif /* CONFIG_MCC_MODE */
-
+ {
/* null data * 1 page */
RsvdPageLoc.LocNullData = TotalPageNum;
RTW_INFO("LocNullData: %d\n", RsvdPageLoc.LocNullData);
@@ -6982,33 +9554,63 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished)
TotalPageNum += CurtPktPageNum;
BufIndex += (CurtPktPageNum * PageSize);
-#ifdef CONFIG_MCC_MODE
+ #ifdef DBG_RSVD_PAGE_CFG
+ RSVD_PAGE_CFG("NullData", CurtPktPageNum, TotalPageNum, TotalPacketLen);
+ #endif
+ }
+
+ if (pwrctl->wowlan_mode == _FALSE ||
+ pwrctl->wowlan_in_resume == _TRUE) {
+ /* Qos null data * 1 page */
+ RsvdPageLoc.LocQosNull = TotalPageNum;
+ RTW_INFO("LocQosNull: %d\n", RsvdPageLoc.LocQosNull);
+ rtw_hal_construct_NullFunctionData(adapter,
+ &ReservedPagePacket[BufIndex],
+ &QosNullLength,
+ get_my_bssid(&pmlmeinfo->network),
+ _TRUE, 0, 0, _FALSE);
+ rtw_hal_fill_fake_txdesc(adapter,
+ &ReservedPagePacket[BufIndex - TxDescLen],
+ QosNullLength, _FALSE, _FALSE, _FALSE);
+
+ CurtPktPageNum = (u8)PageNum(TxDescLen + QosNullLength,
+ PageSize);
+
+ TotalPageNum += CurtPktPageNum;
+
+ BufIndex += (CurtPktPageNum * PageSize);
+ #ifdef DBG_RSVD_PAGE_CFG
+ RSVD_PAGE_CFG("QosNull", CurtPktPageNum, TotalPageNum, TotalPacketLen);
+ #endif
}
-#endif /* CONFIG_MCC_MODE */
- /* Qos null data * 1 page */
- RsvdPageLoc.LocQosNull = TotalPageNum;
- RTW_INFO("LocQosNull: %d\n", RsvdPageLoc.LocQosNull);
- rtw_hal_construct_NullFunctionData(
- adapter,
- &ReservedPagePacket[BufIndex],
- &QosNullLength,
- get_my_bssid(&pmlmeinfo->network),
- _TRUE, 0, 0, _FALSE);
- rtw_hal_fill_fake_txdesc(adapter,
+ TotalPacketLen = BufIndex;
+
+#ifdef DBG_FW_DEBUG_MSG_PKT
+ RsvdPageLoc.loc_fw_dbg_msg_pkt = TotalPageNum;
+ RTW_INFO("loc_fw_dbg_msg_pkt: %d\n", RsvdPageLoc.loc_fw_dbg_msg_pkt);
+ rtw_hal_construct_fw_dbg_msg_pkt(
+ adapter,
+ &ReservedPagePacket[BufIndex],
+ &fw_dbg_msg_pkt_len);
+
+ rtw_hal_fill_fake_txdesc(adapter,
&ReservedPagePacket[BufIndex - TxDescLen],
- QosNullLength, _FALSE, _FALSE, _FALSE);
+ fw_dbg_msg_pkt_len, _FALSE, _FALSE, _FALSE);
- CurtPktPageNum = (u8)PageNum(TxDescLen + QosNullLength, PageSize);
+ CurtPktPageNum = (u8)PageNum(TxDescLen + fw_dbg_msg_pkt_len, PageSize);
- TotalPageNum += CurtPktPageNum;
+ TotalPageNum += CurtPktPageNum;
- TotalPacketLen = BufIndex + QosNullLength;
+ TotalPacketLen = BufIndex + fw_dbg_msg_pkt_len;
+ BufIndex += (CurtPktPageNum * PageSize);
- BufIndex += (CurtPktPageNum * PageSize);
+
+#endif /*DBG_FW_DEBUG_MSG_PKT*/
#ifdef CONFIG_WOWLAN
- if (pwrctl->wowlan_mode == _TRUE) {
+ if (pwrctl->wowlan_mode == _TRUE &&
+ pwrctl->wowlan_in_resume == _FALSE) {
rtw_hal_set_wow_fw_rsvd_page(adapter, ReservedPagePacket,
BufIndex, TxDescLen, PageSize,
&TotalPageNum, &TotalPacketLen, &RsvdPageLoc);
@@ -7026,15 +9628,49 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished)
#ifdef CONFIG_LPS_PG
/* must reserved last 1 x page for LPS PG Info*/
pwrctl->lpspg_rsvd_page_locate = TotalPageNum;
+ pwrctl->blpspg_info_up = _TRUE;
+ if (page_num)
+ TotalPageNum += LPS_PG_INFO_RSVD_PAGE_NUM;
+
+ #ifdef DBG_RSVD_PAGE_CFG
+ RSVD_PAGE_CFG("LPS_PG", LPS_PG_INFO_RSVD_PAGE_NUM,
+ (page_num) ? TotalPageNum : (TotalPageNum + LPS_PG_INFO_RSVD_PAGE_NUM),
+ TotalPacketLen);
+ #endif
+
#endif
+ /*Note: BufIndex already add a TxDescOffset offset in first Beacon page
+ * The "TotalPacketLen" is calculate by BufIndex.
+ * We need to decrease TxDescOffset before doing length check. by yiwei
+ */
+ TotalPacketLen = TotalPacketLen - TxDescOffset;
+
download_page:
+ if (page_num) {
+ *page_num = TotalPageNum;
+ rtw_mfree(ReservedPagePacket, MAX_CMDBUF_SZ);
+ ReservedPagePacket = NULL;
+ return;
+ }
+
/* RTW_INFO("%s BufIndex(%d), TxDescLen(%d), PageSize(%d)\n",__func__, BufIndex, TxDescLen, PageSize);*/
RTW_INFO("%s PageNum(%d), pktlen(%d)\n",
__func__, TotalPageNum, TotalPacketLen);
+#ifdef CONFIG_LPS_PG
+ if ((TotalPageNum + LPS_PG_INFO_RSVD_PAGE_NUM) > RsvdPageNum) {
+ pwrctl->lpspg_rsvd_page_locate = 0;
+ pwrctl->blpspg_info_up = _FALSE;
+
+ RTW_ERR("%s [LPS_PG] rsvd page %d is not enough! need %d pages\n",
+ __func__, RsvdPageNum, (TotalPageNum + LPS_PG_INFO_RSVD_PAGE_NUM));
+ rtw_warn_on(1);
+ }
+#endif
+
if (TotalPacketLen > MaxRsvdPageBufSize) {
- RTW_INFO("%s(ERROR): rsvd page size is not enough!!TotalPacketLen %d, MaxRsvdPageBufSize %d\n",
+ RTW_ERR("%s : rsvd page size is not enough!!TotalPacketLen %d, MaxRsvdPageBufSize %d\n",
__FUNCTION__, TotalPacketLen, MaxRsvdPageBufSize);
rtw_warn_on(1);
goto error;
@@ -7043,8 +9679,8 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished)
pattrib = &pcmdframe->attrib;
update_mgntframe_attrib(adapter, pattrib);
pattrib->qsel = QSLT_BEACON;
- pattrib->pktlen = TotalPacketLen - TxDescOffset;
- pattrib->last_txcmdsz = TotalPacketLen - TxDescOffset;
+ pattrib->pktlen = TotalPacketLen;
+ pattrib->last_txcmdsz = TotalPacketLen;
#ifdef CONFIG_PCI_HCI
dump_mgntframe(adapter, pcmdframe);
#else
@@ -7052,36 +9688,237 @@ void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished)
#endif
}
- RTW_INFO("%s: Set RSVD page location to Fw ,TotalPacketLen(%d), TotalPageNum(%d)\n",
- __func__, TotalPacketLen, TotalPageNum);
+ RTW_INFO("%s: Set RSVD page location to Fw ,TotalPacketLen(%d), TotalPageNum(%d)\n",
+ __func__, TotalPacketLen, TotalPageNum);
+#ifdef DBG_DUMP_SET_RSVD_PAGE
+ RTW_INFO(" ==================================================\n");
+ RTW_INFO_DUMP("\n", ReservedPagePacket, TotalPacketLen);
+ RTW_INFO(" ==================================================\n");
+#endif
+ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {
+ rtw_hal_set_FwRsvdPage_cmd(adapter, &RsvdPageLoc);
+#ifdef DBG_FW_DEBUG_MSG_PKT
+ rtw_hal_set_fw_dbg_msg_pkt_rsvd_page_cmd(adapter, &RsvdPageLoc);
+#endif /*DBG_FW_DEBUG_MSG_PKT*/
+#ifdef CONFIG_WOWLAN
+ if (pwrctl->wowlan_mode == _TRUE &&
+ pwrctl->wowlan_in_resume == _FALSE)
+ rtw_hal_set_FwAoacRsvdPage_cmd(adapter, &RsvdPageLoc);
+#endif /* CONFIG_WOWLAN */
+#ifdef CONFIG_AP_WOWLAN
+ if (pwrctl->wowlan_ap_mode == _TRUE)
+ rtw_hal_set_ap_rsvdpage_loc_cmd(adapter, &RsvdPageLoc);
+#endif /* CONFIG_AP_WOWLAN */
+ } else if (pwrctl->wowlan_pno_enable) {
+#ifdef CONFIG_PNO_SUPPORT
+ rtw_hal_set_FwAoacRsvdPage_cmd(adapter, &RsvdPageLoc);
+ if (pwrctl->wowlan_in_resume)
+ rtw_hal_set_scan_offload_info_cmd(adapter,
+ &RsvdPageLoc, 0);
+ else
+ rtw_hal_set_scan_offload_info_cmd(adapter,
+ &RsvdPageLoc, 1);
+#endif /* CONFIG_PNO_SUPPORT */
+ }
+
+#ifdef CONFIG_P2P_WOWLAN
+ if (_TRUE == pwrctl->wowlan_p2p_mode)
+ rtw_hal_set_FwP2PRsvdPage_cmd(adapter, &RsvdPageLoc);
+#endif /* CONFIG_P2P_WOWLAN */
+
+ return;
+error:
+ rtw_free_xmitframe(pxmitpriv, pcmdframe);
+}
+
+void rtw_hal_set_fw_rsvd_page(struct _ADAPTER *adapter, bool finished)
+{
+ _rtw_hal_set_fw_rsvd_page(adapter, finished, NULL);
+}
+
+/**
+ * rtw_hal_get_rsvd_page_num() - Get needed reserved page number
+ * @adapter: struct _ADAPTER*
+ *
+ * Caculate needed reserved page number.
+ * In different state would get different number, for example normal mode and
+ * WOW mode would need different reserved page size.
+ *
+ * Return the number of reserved page which driver need.
+ */
+u8 rtw_hal_get_rsvd_page_num(struct _ADAPTER *adapter)
+{
+ u8 num = 0;
+
+
+ _rtw_hal_set_fw_rsvd_page(adapter, _FALSE, &num);
+
+ return num;
+}
+
+static void hw_var_set_mlme_sitesurvey(_adapter *adapter, u8 variable, u8 *val)
+{
+ struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+ u16 value_rxfltmap2;
+ int i;
+ _adapter *iface;
+
+#ifdef DBG_IFACE_STATUS
+ DBG_IFACE_STATUS_DUMP(adapter);
+#endif
+
+#ifdef CONFIG_FIND_BEST_CHANNEL
+ /* Receive all data frames */
+ value_rxfltmap2 = 0xFFFF;
+#else
+ /* not to receive data frame */
+ value_rxfltmap2 = 0;
+#endif
+
+ if (*((u8 *)val)) { /* under sitesurvey */
+ /*
+ * 1. configure REG_RXFLTMAP2
+ * 2. disable TSF update & buddy TSF update to avoid updating wrong TSF due to clear RCR_CBSSID_BCN
+ * 3. config RCR to receive different BSSID BCN or probe rsp
+ */
+ rtw_write16(adapter, REG_RXFLTMAP2, value_rxfltmap2);
+
+#ifdef CONFIG_MI_WITH_MBSSID_CAM
+ /*do nothing~~*/
+#else
+
+ /* disable update TSF */
+ for (i = 0; i < dvobj->iface_nums; i++) {
+ iface = dvobj->padapters[i];
+ if (!iface)
+ continue;
+
+ if (rtw_linked_check(iface)
+ && !MLME_IS_AP(iface) && !MLME_IS_MESH(iface)
+ ) {
+ if (iface->hw_port == HW_PORT1)
+ rtw_write8(iface, REG_BCN_CTRL_1, rtw_read8(iface, REG_BCN_CTRL_1) | DIS_TSF_UDT);
+ else
+ rtw_write8(iface, REG_BCN_CTRL, rtw_read8(iface, REG_BCN_CTRL) | DIS_TSF_UDT);
+
+ iface->mlmeextpriv.en_hw_update_tsf = _FALSE;
+ }
+ }
+#endif /* CONFIG_MI_WITH_MBSSID_CAM */
+
+ rtw_hal_rcr_set_chk_bssid(adapter, MLME_SCAN_ENTER);
+
+ /* Save orignal RRSR setting. needed? */
+ hal_data->RegRRSR = rtw_read16(adapter, REG_RRSR);
+
+ #if defined(CONFIG_BEAMFORMING) && (defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A))
+ if (IS_8812_SERIES(hal_data->version_id) || IS_8821_SERIES(hal_data->version_id)) {
+ /* set 718[1:0]=2'b00 to avoid BF scan hang */
+ hal_data->backup_snd_ptcl_ctrl = rtw_read8(adapter, REG_SND_PTCL_CTRL_8812A);
+ rtw_write8(adapter, REG_SND_PTCL_CTRL_8812A, (hal_data->backup_snd_ptcl_ctrl & 0xfc));
+ }
+ #endif
+
+ if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter))
+ StopTxBeacon(adapter);
+ } else { /* sitesurvey done */
+ /*
+ * 1. enable rx data frame
+ * 2. config RCR not to receive different BSSID BCN or probe rsp
+ * 3. doesn't enable TSF update & buddy TSF right now to avoid HW conflict
+ * so, we enable TSF update when rx first BCN after sitesurvey done
+ */
+ if (rtw_mi_check_fwstate(adapter, _FW_LINKED | WIFI_AP_STATE | WIFI_MESH_STATE)) {
+ /* enable to rx data frame */
+ rtw_write16(adapter, REG_RXFLTMAP2, 0xFFFF);
+ }
+
+ rtw_hal_rcr_set_chk_bssid(adapter, MLME_SCAN_DONE);
+
+#ifdef CONFIG_MI_WITH_MBSSID_CAM
+ /*if ((rtw_mi_get_assoced_sta_num(adapter) == 1) && (!rtw_mi_check_status(adapter, MI_AP_MODE)))
+ rtw_write8(adapter, REG_BCN_CTRL, rtw_read8(adapter, REG_BCN_CTRL)&(~DIS_TSF_UDT));*/
+#else
+
+ for (i = 0; i < dvobj->iface_nums; i++) {
+ iface = dvobj->padapters[i];
+ if (!iface)
+ continue;
+ if (rtw_linked_check(iface)
+ && !MLME_IS_AP(iface) && !MLME_IS_MESH(iface)
+ ) {
+ /* enable HW TSF update when recive beacon*/
+ /*if (iface->hw_port == HW_PORT1)
+ rtw_write8(iface, REG_BCN_CTRL_1, rtw_read8(iface, REG_BCN_CTRL_1)&(~(DIS_TSF_UDT)));
+ else
+ rtw_write8(iface, REG_BCN_CTRL, rtw_read8(iface, REG_BCN_CTRL)&(~(DIS_TSF_UDT)));
+ */
+ iface->mlmeextpriv.en_hw_update_tsf = _TRUE;
+ }
+ }
+#endif /* CONFIG_MI_WITH_MBSSID_CAM */
+
+ /* Restore orignal RRSR setting. needed? */
+ rtw_write16(adapter, REG_RRSR, hal_data->RegRRSR);
+
+ #if defined(CONFIG_BEAMFORMING) && (defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A))
+ if (IS_8812_SERIES(hal_data->version_id) || IS_8821_SERIES(hal_data->version_id)) {
+ /* Restore orignal 0x718 setting*/
+ rtw_write8(adapter, REG_SND_PTCL_CTRL_8812A, hal_data->backup_snd_ptcl_ctrl);
+ }
+ #endif
+
+ if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) {
+ ResumeTxBeacon(adapter);
+ rtw_mi_tx_beacon_hdl(adapter);
+ }
+ }
+}
+
+#ifdef CONFIG_TSF_RESET_OFFLOAD
+static int rtw_hal_h2c_reset_tsf(_adapter *adapter, u8 reset_port)
+{
+ u8 buf[2];
+ int ret;
+
+ if (reset_port == HW_PORT0) {
+ buf[0] = 0x1;
+ buf[1] = 0;
+ } else {
+ buf[0] = 0x0;
+ buf[1] = 0x1;
+ }
+
+ ret = rtw_hal_fill_h2c_cmd(adapter, H2C_RESET_TSF, 2, buf);
- if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {
- rtw_hal_set_FwRsvdPage_cmd(adapter, &RsvdPageLoc);
- if (pwrctl->wowlan_mode == _TRUE)
- rtw_hal_set_FwAoacRsvdPage_cmd(adapter, &RsvdPageLoc);
-#ifdef CONFIG_AP_WOWLAN
- if (pwrctl->wowlan_ap_mode == _TRUE)
- rtw_hal_set_ap_rsvdpage_loc_cmd(adapter, &RsvdPageLoc);
-#endif /* CONFIG_AP_WOWLAN */
- } else if (pwrctl->wowlan_pno_enable) {
-#ifdef CONFIG_PNO_SUPPORT
- rtw_hal_set_FwAoacRsvdPage_cmd(adapter, &RsvdPageLoc);
- if (pwrctl->pno_in_resume)
- rtw_hal_set_scan_offload_info_cmd(adapter,
- &RsvdPageLoc, 0);
- else
- rtw_hal_set_scan_offload_info_cmd(adapter,
- &RsvdPageLoc, 1);
-#endif /* CONFIG_PNO_SUPPORT */
+ return ret;
+}
+
+int rtw_hal_reset_tsf(_adapter *adapter, u8 reset_port)
+{
+ u8 reset_cnt_before = 0, reset_cnt_after = 0, loop_cnt = 0;
+ u32 reg_reset_tsf_cnt = (reset_port == HW_PORT0) ?
+ REG_FW_RESET_TSF_CNT_0 : REG_FW_RESET_TSF_CNT_1;
+ int ret;
+
+ /* site survey will cause reset tsf fail */
+ rtw_mi_buddy_scan_abort(adapter, _FALSE);
+ reset_cnt_after = reset_cnt_before = rtw_read8(adapter, reg_reset_tsf_cnt);
+ ret = rtw_hal_h2c_reset_tsf(adapter, reset_port);
+ if (ret != _SUCCESS)
+ return ret;
+
+ while ((reset_cnt_after == reset_cnt_before) && (loop_cnt < 10)) {
+ rtw_msleep_os(100);
+ loop_cnt++;
+ reset_cnt_after = rtw_read8(adapter, reg_reset_tsf_cnt);
}
-#ifdef CONFIG_P2P_WOWLAN
- if (_TRUE == pwrctl->wowlan_p2p_mode)
- rtw_hal_set_FwP2PRsvdPage_cmd(adapter, &RsvdPageLoc);
-#endif /* CONFIG_P2P_WOWLAN */
- return;
-error:
- rtw_free_xmitframe(pxmitpriv, pcmdframe);
+
+ return (loop_cnt >= 10) ? _FAIL : _SUCCESS;
}
+#endif /* CONFIG_TSF_RESET_OFFLOAD */
+
static void rtw_hal_set_hw_update_tsf(PADAPTER padapter)
{
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
@@ -7096,13 +9933,14 @@ static void rtw_hal_set_hw_update_tsf(PADAPTER padapter)
if (!pmlmeext->en_hw_update_tsf)
return;
- /* check REG_RCR bit is set */
- if (!(rtw_read32(padapter, REG_RCR) & RCR_CBSSID_BCN))
+ /* check RCR */
+ if (!rtw_hal_rcr_check(padapter, RCR_CBSSID_BCN))
return;
- /* enable hw update tsf function for non-AP */
- if (rtw_linked_check(padapter) &&
- check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) {
+ /* enable hw update tsf function for non-AP and non-Mesh */
+ if (rtw_linked_check(padapter)
+ && !MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter)
+ ) {
#ifdef CONFIG_CONCURRENT_MODE
if (padapter->hw_port == HW_PORT1)
rtw_write8(padapter, REG_BCN_CTRL_1, rtw_read8(padapter, REG_BCN_CTRL_1) & (~DIS_TSF_UDT));
@@ -7113,6 +9951,60 @@ static void rtw_hal_set_hw_update_tsf(PADAPTER padapter)
pmlmeext->en_hw_update_tsf = _FALSE;
}
+static void hw_var_set_correct_tsf(_adapter *adapter)
+{
+#ifdef CONFIG_MI_WITH_MBSSID_CAM
+ /*do nothing*/
+#else
+ u64 tsf;
+ struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv;
+ struct mlme_ext_info *mlmeinfo = &(mlmeext->mlmext_info);
+
+ tsf = mlmeext->TSFValue - rtw_modular64(mlmeext->TSFValue, (mlmeinfo->bcn_interval * 1024)) - 1024; /*us*/
+
+ if ((mlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE
+ || (mlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)
+ StopTxBeacon(adapter);
+
+ rtw_hal_correct_tsf(adapter, adapter->hw_port, tsf);
+
+#ifdef CONFIG_CONCURRENT_MODE
+ /* Update buddy port's TSF if it is SoftAP/Mesh for beacon TX issue! */
+ if ((mlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE
+ && (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter))
+ ) {
+ struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+ int i;
+ _adapter *iface;
+
+ for (i = 0; i < dvobj->iface_nums; i++) {
+ iface = dvobj->padapters[i];
+ if (!iface)
+ continue;
+ if (iface == adapter)
+ continue;
+
+ if ((MLME_IS_AP(iface) || MLME_IS_MESH(iface))
+ && check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE
+ ) {
+ rtw_hal_correct_tsf(iface, iface->hw_port, tsf);
+ #ifdef CONFIG_TSF_RESET_OFFLOAD
+ if (rtw_hal_reset_tsf(iface, iface->hw_port) == _FAIL)
+ RTW_INFO("%s-[ERROR] "ADPT_FMT" Reset port%d TSF fail\n"
+ , __func__, ADPT_ARG(iface), iface->hw_port);
+ #endif /* CONFIG_TSF_RESET_OFFLOAD*/
+ }
+ }
+ }
+#endif /* CONFIG_CONCURRENT_MODE */
+
+ if ((mlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE
+ || (mlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)
+ ResumeTxBeacon(adapter);
+
+#endif /*CONFIG_MI_WITH_MBSSID_CAM*/
+}
+
#ifdef CONFIG_TDLS
#ifdef CONFIG_TDLS_CH_SW
s32 rtw_hal_ch_sw_oper_offload(_adapter *padapter, u8 channel, u8 channel_offset, u16 bwmode)
@@ -7134,17 +10026,41 @@ s32 rtw_hal_ch_sw_oper_offload(_adapter *padapter, u8 channel, u8 channel_offset
default:
break;
}
- SET_H2CCMD_CH_SW_OPER_OFFLOAD_RFE_TYPE(ch_sw_h2c_buf, pHalData->RFEType);
+ SET_H2CCMD_CH_SW_OPER_OFFLOAD_RFE_TYPE(ch_sw_h2c_buf, pHalData->rfe_type);
return rtw_hal_fill_h2c_cmd(padapter, H2C_CHNL_SWITCH_OPER_OFFLOAD, sizeof(ch_sw_h2c_buf), ch_sw_h2c_buf);
}
#endif
#endif
-void SetHwReg(_adapter *adapter, u8 variable, u8 *val)
+#ifdef CONFIG_WMMPS_STA
+void rtw_hal_update_uapsd_tid(_adapter *adapter)
+{
+ struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
+ struct qos_priv *pqospriv = &pmlmepriv->qospriv;
+
+ /* write complement of pqospriv->uapsd_tid to mac register 0x693 because
+ it's designed for "0" represents "enable" and "1" represents "disable" */
+ rtw_write8(adapter, REG_WMMPS_UAPSD_TID, (u8)(~pqospriv->uapsd_tid));
+}
+#endif /* CONFIG_WMMPS_STA */
+
+#if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT)
+/* For multi-port support, driver needs to inform the port ID to FW for btc operations */
+s32 rtw_hal_set_wifi_port_id_cmd(_adapter *adapter)
+{
+ u8 port_id = 0;
+ u8 h2c_buf[H2C_BTC_WL_PORT_ID_LEN] = {0};
+
+ SET_H2CCMD_BTC_WL_PORT_ID(h2c_buf, adapter->hw_port);
+ return rtw_hal_fill_h2c_cmd(adapter, H2C_BTC_WL_PORT_ID, H2C_BTC_WL_PORT_ID_LEN, h2c_buf);
+}
+#endif
+
+u8 SetHwReg(_adapter *adapter, u8 variable, u8 *val)
{
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
- _func_enter_;
+ u8 ret = _SUCCESS;
switch (variable) {
case HW_VAR_MEDIA_STATUS: {
@@ -7163,6 +10079,18 @@ void SetHwReg(_adapter *adapter, u8 variable, u8 *val)
case HW_VAR_BSSID:
rtw_hal_set_bssid(adapter, val);
break;
+ case HW_VAR_RCR:
+ ret = hw_var_rcr_config(adapter, *((u32 *)val));
+ break;
+ case HW_VAR_ON_RCR_AM:
+ hw_var_set_rcr_am(adapter, 1);
+ break;
+ case HW_VAR_OFF_RCR_AM:
+ hw_var_set_rcr_am(adapter, 0);
+ break;
+ case HW_VAR_BEACON_INTERVAL:
+ hw_var_set_bcn_interval(adapter, *(u16 *)val);
+ break;
#ifdef CONFIG_MBSSID_CAM
case HW_VAR_MBSSID_CAM_WRITE: {
u32 cmd = 0;
@@ -7172,7 +10100,7 @@ void SetHwReg(_adapter *adapter, u8 variable, u8 *val)
cmd = BIT_MBIDCAM_POLL | BIT_MBIDCAM_WT_EN | BIT_MBIDCAM_VALID | cam_val[1];
rtw_write32(adapter, REG_MBIDCAMCFG_2, cmd);
}
- break;
+ break;
case HW_VAR_MBSSID_CAM_CLEAR: {
u32 cmd;
u8 entry_id = *(u8 *)val;
@@ -7182,17 +10110,12 @@ void SetHwReg(_adapter *adapter, u8 variable, u8 *val)
cmd = BIT_MBIDCAM_POLL | BIT_MBIDCAM_WT_EN | ((entry_id & MBIDCAM_ADDR_MASK) << MBIDCAM_ADDR_SHIFT);
rtw_write32(adapter, REG_MBIDCAMCFG_2, cmd);
}
- break;
+ break;
case HW_VAR_RCR_MBSSID_EN:
if (*((u8 *)val))
- rtw_write32(adapter, REG_RCR, rtw_read32(adapter, REG_RCR) | RCR_ENMBID);
- else {
- u32 val32;
-
- val32 = rtw_read32(adapter, REG_RCR);
- val32 &= ~(RCR_ENMBID);
- rtw_write32(adapter, REG_RCR, val32);
- }
+ rtw_hal_rcr_add(adapter, RCR_ENMBID);
+ else
+ rtw_hal_rcr_clear(adapter, RCR_ENMBID);
break;
#endif
case HW_VAR_PORT_SWITCH:
@@ -7201,7 +10124,7 @@ void SetHwReg(_adapter *adapter, u8 variable, u8 *val)
case HW_VAR_INIT_RTS_RATE: {
u16 brate_cfg = *((u16 *)val);
u8 rate_index = 0;
- HAL_VERSION *hal_ver = &hal_data->VersionID;
+ HAL_VERSION *hal_ver = &hal_data->version_id;
if (IS_8188E(*hal_ver)) {
@@ -7213,7 +10136,7 @@ void SetHwReg(_adapter *adapter, u8 variable, u8 *val)
} else
rtw_warn_on(1);
}
- break;
+ break;
case HW_VAR_SEC_CFG: {
u16 reg_scr_ori;
u16 reg_scr;
@@ -7230,7 +10153,7 @@ void SetHwReg(_adapter *adapter, u8 variable, u8 *val)
if (reg_scr != reg_scr_ori)
rtw_write16(adapter, REG_SECCFG, reg_scr);
}
- break;
+ break;
case HW_VAR_SEC_DK_CFG: {
struct security_priv *sec = &adapter->securitypriv;
u8 reg_scr = rtw_read8(adapter, REG_SECCFG);
@@ -7244,7 +10167,7 @@ void SetHwReg(_adapter *adapter, u8 variable, u8 *val)
rtw_write8(adapter, REG_SECCFG, reg_scr);
}
- break;
+ break;
case HW_VAR_ASIX_IOT:
/* enable ASIX IOT function */
@@ -7290,30 +10213,82 @@ void SetHwReg(_adapter *adapter, u8 variable, u8 *val)
break;
}
}
- break;
+ break;
#endif /*defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)*/
+ case HW_VAR_MLME_SITESURVEY:
+ hw_var_set_mlme_sitesurvey(adapter, variable, val);
+ #ifdef CONFIG_BT_COEXIST
+ if (hal_data->EEPROMBluetoothCoexist == 1)
+ rtw_btcoex_ScanNotify(adapter, *val ? _TRUE : _FALSE);
+ #endif
+ break;
+
case HW_VAR_EN_HW_UPDATE_TSF:
rtw_hal_set_hw_update_tsf(adapter);
break;
+ case HW_VAR_CORRECT_TSF:
+ hw_var_set_correct_tsf(adapter);
+ break;
+
+ case HW_VAR_APFM_ON_MAC:
+ hal_data->bMacPwrCtrlOn = *val;
+ RTW_INFO("%s: bMacPwrCtrlOn=%d\n", __func__, hal_data->bMacPwrCtrlOn);
+ break;
+#ifdef CONFIG_WMMPS_STA
+ case HW_VAR_UAPSD_TID:
+ rtw_hal_update_uapsd_tid(adapter);
+ break;
+#endif /* CONFIG_WMMPS_STA */
+#ifdef CONFIG_LPS_PG
+ case HW_VAR_LPS_PG_HANDLE:
+ rtw_hal_lps_pg_handler(adapter, *val);
+ break;
+#endif
+#ifdef CONFIG_LPS_LCLK_WD_TIMER
+ case HW_VAR_DM_IN_LPS_LCLK:
+ rtw_phydm_wd_lps_lclk_hdl(adapter);
+ break;
+#endif
+ case HW_VAR_ENABLE_RX_BAR:
+ if (*val == _TRUE) {
+ /* enable RX BAR */
+ u16 val16 = rtw_read16(adapter, REG_RXFLTMAP1);
+
+ val16 |= BIT(8);
+ rtw_write16(adapter, REG_RXFLTMAP1, val16);
+ } else {
+ /* disable RX BAR */
+ u16 val16 = rtw_read16(adapter, REG_RXFLTMAP1);
+
+ val16 &= (~BIT(8));
+ rtw_write16(adapter, REG_RXFLTMAP1, val16);
+ }
+ RTW_INFO("[HW_VAR_ENABLE_RX_BAR] 0x%02X=0x%02X\n",
+ REG_RXFLTMAP1, rtw_read16(adapter, REG_RXFLTMAP1));
+ break;
default:
if (0)
RTW_PRINT(FUNC_ADPT_FMT" variable(%d) not defined!\n",
FUNC_ADPT_ARG(adapter), variable);
+ ret = _FAIL;
break;
}
- _func_exit_;
+ return ret;
}
void GetHwReg(_adapter *adapter, u8 variable, u8 *val)
{
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+ u64 val64;
- _func_enter_;
switch (variable) {
+ case HW_VAR_MAC_ADDR:
+ rtw_hal_get_macaddr_port(adapter, val);
+ break;
case HW_VAR_BASIC_RATE:
*((u16 *)val) = hal_data->BasicRateSet;
break;
@@ -7331,8 +10306,45 @@ void GetHwReg(_adapter *adapter, u8 variable, u8 *val)
*val = _TRUE;
else
*val = _FALSE;
+ break;
+ case HW_VAR_APFM_ON_MAC:
+ *val = hal_data->bMacPwrCtrlOn;
+ break;
+ case HW_VAR_RCR:
+ hw_var_rcr_get(adapter, (u32 *)val);
+ break;
+ case HW_VAR_FWLPS_RF_ON:
+ /* When we halt NIC, we should check if FW LPS is leave. */
+ if (rtw_is_surprise_removed(adapter)
+ || (adapter_to_pwrctl(adapter)->rf_pwrstate == rf_off)
+ ) {
+ /*
+ * If it is in HW/SW Radio OFF or IPS state,
+ * we do not check Fw LPS Leave,
+ * because Fw is unload.
+ */
+ *val = _TRUE;
+ } else {
+ u32 rcr = 0;
+
+ rtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)&rcr);
+ if (rcr & (RCR_UC_MD_EN | RCR_BC_MD_EN | RCR_TIM_PARSER_EN))
+ *val = _FALSE;
+ else
+ *val = _TRUE;
+ }
+ break;
+ case HW_VAR_TSF:
+ /* read and save HIGH 32bits TSF value */
+ val64 = rtw_read32(adapter, REG_TSFTR+4);
+ val64 = val64 << 32;
+
+ /* read and save LOW 32bits TSF value */
+ val64 |= rtw_read32(adapter, REG_TSFTR);
+ *((u64*)val) = val64;
break;
+
default:
if (0)
RTW_PRINT(FUNC_ADPT_FMT" variable(%d) not defined!\n",
@@ -7340,7 +10352,27 @@ void GetHwReg(_adapter *adapter, u8 variable, u8 *val)
break;
}
- _func_exit_;
+}
+
+static u32 _get_page_size(struct _ADAPTER *a)
+{
+#ifdef RTW_HALMAC
+ struct dvobj_priv *d;
+ u32 size = 0;
+ int err = 0;
+
+
+ d = adapter_to_dvobj(a);
+
+ err = rtw_halmac_get_page_size(d, &size);
+ if (!err)
+ return size;
+
+ RTW_WARN(FUNC_ADPT_FMT ": Fail to get Page size!!(err=%d)\n",
+ FUNC_ADPT_ARG(a), err);
+#endif /* RTW_HALMAC */
+
+ return PAGE_SIZE_128;
}
u8
@@ -7360,9 +10392,6 @@ SetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value)
case HAL_DEF_ANT_DETECT:
hal_data->AntDetection = *((u8 *)value);
break;
- case HAL_DEF_DBG_DIS_PWT:
- hal_data->bDisableTXPowerTraining = *((u8 *)value);
- break;
default:
RTW_PRINT("%s: [WARNING] HAL_DEF_VARIABLE(%d) not defined!\n", __FUNCTION__, variable);
bResult = _FAIL;
@@ -7417,6 +10446,35 @@ u8 rtw_hal_query_txbfee_rf_num(_adapter *adapter)
return 1;
}
+#ifdef RTW_BEAMFORMING_VERSION_2
+void rtw_hal_beamforming_config_csirate(PADAPTER adapter)
+{
+ struct dm_struct *p_dm_odm;
+ struct beamforming_info *bf_info;
+ u8 fix_rate_enable = 0;
+ u8 new_csi_rate_idx;
+
+ /* Acting as BFee */
+ if (IS_BEAMFORMEE(adapter)) {
+ #if 0
+ /* Do not enable now because it will affect MU performance and CTS/BA rate. 2016.07.19. by tynli. [PCIE-1660] */
+ if (IS_HARDWARE_TYPE_8821C(Adapter))
+ FixRateEnable = 1; /* Support after 8821C */
+ #endif
+
+ p_dm_odm = adapter_to_phydm(adapter);
+ bf_info = GET_BEAMFORM_INFO(adapter);
+
+ rtw_halmac_bf_cfg_csi_rate(adapter_to_dvobj(adapter),
+ p_dm_odm->rssi_min,
+ bf_info->cur_csi_rpt_rate,
+ fix_rate_enable, &new_csi_rate_idx);
+
+ if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate)
+ bf_info->cur_csi_rpt_rate = new_csi_rate_idx;
+ }
+}
+#endif
#endif
u8
@@ -7433,302 +10491,44 @@ GetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value)
pmlmepriv = &adapter->mlmepriv;
pstapriv = &adapter->stapriv;
- psta = rtw_get_stainfo(pstapriv, pmlmepriv->cur_network.network.MacAddress);
- if (psta)
- *((int *)value) = psta->rssi_stat.UndecoratedSmoothedPWDB;
- }
- break;
- case HAL_DEF_DBG_DUMP_RXPKT:
- *((u8 *)value) = hal_data->bDumpRxPkt;
- break;
- case HAL_DEF_DBG_DUMP_TXPKT:
- *((u8 *)value) = hal_data->bDumpTxPkt;
- break;
- case HAL_DEF_ANT_DETECT:
- *((u8 *)value) = hal_data->AntDetection;
- break;
- case HAL_DEF_MACID_SLEEP:
- *(u8 *)value = _FALSE;
- break;
- case HAL_DEF_TX_PAGE_SIZE:
- *((u32 *)value) = PAGE_SIZE_128;
- break;
- case HAL_DEF_DBG_DIS_PWT:
- *(u8 *)value = hal_data->bDisableTXPowerTraining;
- break;
- case HAL_DEF_EXPLICIT_BEAMFORMER:
- case HAL_DEF_EXPLICIT_BEAMFORMEE:
- case HAL_DEF_VHT_MU_BEAMFORMER:
- case HAL_DEF_VHT_MU_BEAMFORMEE:
- *(u8 *)value = _FALSE;
- break;
-#ifdef CONFIG_BEAMFORMING
- case HAL_DEF_BEAMFORMER_CAP:
- *(u8 *)value = rtw_hal_query_txbfer_rf_num(adapter);
- break;
- case HAL_DEF_BEAMFORMEE_CAP:
- *(u8 *)value = rtw_hal_query_txbfee_rf_num(adapter);
- break;
-#endif
- default:
- RTW_PRINT("%s: [WARNING] HAL_DEF_VARIABLE(%d) not defined!\n", __FUNCTION__, variable);
- bResult = _FAIL;
- break;
- }
-
- return bResult;
-}
-
-void SetHalODMVar(
- PADAPTER Adapter,
- HAL_ODM_VARIABLE eVariable,
- PVOID pValue1,
- BOOLEAN bSet)
-{
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
- PDM_ODM_T podmpriv = &pHalData->odmpriv;
- /* _irqL irqL; */
- switch (eVariable) {
- case HAL_ODM_STA_INFO: {
- struct sta_info *psta = (struct sta_info *)pValue1;
- if (bSet) {
- RTW_INFO("### Set STA_(%d) info ###\n", psta->mac_id);
- ODM_CmnInfoPtrArrayHook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->mac_id, psta);
- } else {
- RTW_INFO("### Clean STA_(%d) info ###\n", psta->mac_id);
- /* _enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */
- ODM_CmnInfoPtrArrayHook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->mac_id, NULL);
-
- /* _exit_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */
- }
- }
- break;
- case HAL_ODM_P2P_STATE:
- ODM_CmnInfoUpdate(podmpriv, ODM_CMNINFO_WIFI_DIRECT, bSet);
- break;
- case HAL_ODM_WIFI_DISPLAY_STATE:
- ODM_CmnInfoUpdate(podmpriv, ODM_CMNINFO_WIFI_DISPLAY, bSet);
- break;
- case HAL_ODM_REGULATION:
- ODM_CmnInfoInit(podmpriv, ODM_CMNINFO_DOMAIN_CODE_2G, pHalData->Regulation2_4G);
- ODM_CmnInfoInit(podmpriv, ODM_CMNINFO_DOMAIN_CODE_5G, pHalData->Regulation5G);
- break;
-#if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR)
- case HAL_ODM_NOISE_MONITOR: {
- struct noise_info *pinfo = (struct noise_info *)pValue1;
-
-#ifdef DBG_NOISE_MONITOR
- RTW_INFO("### Noise monitor chan(%d)-bPauseDIG:%d,IGIValue:0x%02x,max_time:%d (ms) ###\n",
- pinfo->chan, pinfo->bPauseDIG, pinfo->IGIValue, pinfo->max_time);
-#endif
-
- pHalData->noise[pinfo->chan] = ODM_InbandNoise_Monitor(podmpriv, pinfo->bPauseDIG, pinfo->IGIValue, pinfo->max_time);
- RTW_INFO("chan_%d, noise = %d (dBm)\n", pinfo->chan, pHalData->noise[pinfo->chan]);
-#ifdef DBG_NOISE_MONITOR
- RTW_INFO("noise_a = %d, noise_b = %d noise_all:%d\n",
- podmpriv->noise_level.noise[ODM_RF_PATH_A],
- podmpriv->noise_level.noise[ODM_RF_PATH_B],
- podmpriv->noise_level.noise_all);
-#endif
- }
- break;
-#endif/*#ifdef CONFIG_BACKGROUND_NOISE_MONITOR*/
-
- case HAL_ODM_INITIAL_GAIN: {
- u8 rx_gain = *((u8 *)(pValue1));
- /*printk("rx_gain:%x\n",rx_gain);*/
- if (rx_gain == 0xff) {/*restore rx gain*/
- /*ODM_Write_DIG(podmpriv,pDigTable->BackupIGValue);*/
- odm_PauseDIG(podmpriv, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_0, rx_gain);
- } else {
- /*pDigTable->BackupIGValue = pDigTable->CurIGValue;*/
- /*ODM_Write_DIG(podmpriv,rx_gain);*/
- odm_PauseDIG(podmpriv, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_0, rx_gain);
- }
- }
- break;
- case HAL_ODM_FA_CNT_DUMP:
- if (*((u8 *)pValue1))
- podmpriv->DebugComponents |= (ODM_COMP_DIG | ODM_COMP_FA_CNT);
- else
- podmpriv->DebugComponents &= ~(ODM_COMP_DIG | ODM_COMP_FA_CNT);
- break;
- case HAL_ODM_DBG_FLAG:
- ODM_CmnInfoUpdate(podmpriv, ODM_CMNINFO_DBG_COMP, *((u8Byte *)pValue1));
- break;
- case HAL_ODM_DBG_LEVEL:
- ODM_CmnInfoUpdate(podmpriv, ODM_CMNINFO_DBG_LEVEL, *((u4Byte *)pValue1));
- break;
- case HAL_ODM_RX_INFO_DUMP: {
- PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure(podmpriv , PHYDM_FALSEALMCNT);
- pDIG_T pDM_DigTable = &podmpriv->DM_DigTable;
- void *sel;
-
- sel = pValue1;
-
- _RTW_PRINT_SEL(sel , "============ Rx Info dump ===================\n");
- _RTW_PRINT_SEL(sel , "bLinked = %d, RSSI_Min = %d(%%), CurrentIGI = 0x%x\n", podmpriv->bLinked, podmpriv->RSSI_Min, pDM_DigTable->CurIGValue);
- _RTW_PRINT_SEL(sel , "Cnt_Cck_fail = %d, Cnt_Ofdm_fail = %d, Total False Alarm = %d\n", FalseAlmCnt->Cnt_Cck_fail, FalseAlmCnt->Cnt_Ofdm_fail, FalseAlmCnt->Cnt_all);
-
- if (podmpriv->bLinked) {
- _RTW_PRINT_SEL(sel , "RxRate = %s", HDATA_RATE(podmpriv->RxRate));
- _RTW_PRINT_SEL(sel , " RSSI_A = %d(%%), RSSI_B = %d(%%)\n", podmpriv->RSSI_A, podmpriv->RSSI_B);
-#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
- rtw_dump_raw_rssi_info(Adapter, sel);
-#endif
- }
- }
- break;
- case HAL_ODM_RX_Dframe_INFO: {
- void *sel;
-
- sel = pValue1;
-
- /*_RTW_PRINT_SEL(sel , "HAL_ODM_RX_Dframe_INFO\n");*/
-#ifdef DBG_RX_DFRAME_RAW_DATA
- rtw_dump_rx_dframe_info(Adapter, sel);
-#endif
- }
- break;
-
-#ifdef CONFIG_AUTO_CHNL_SEL_NHM
- case HAL_ODM_AUTO_CHNL_SEL: {
- ACS_OP acs_op = *(ACS_OP *)pValue1;
-
- rtw_phydm_func_set(Adapter, ODM_BB_NHM_CNT);
-
- if (ACS_INIT == acs_op) {
-#ifdef DBG_AUTO_CHNL_SEL_NHM
- RTW_INFO("[ACS-"ADPT_FMT"] HAL_ODM_AUTO_CHNL_SEL: ACS_INIT\n", ADPT_ARG(Adapter));
-#endif
- odm_AutoChannelSelectInit(podmpriv);
- } else if (ACS_RESET == acs_op) {
- /* Reset statistics for auto channel selection mechanism.*/
-#ifdef DBG_AUTO_CHNL_SEL_NHM
- RTW_INFO("[ACS-"ADPT_FMT"] HAL_ODM_AUTO_CHNL_SEL: ACS_RESET\n", ADPT_ARG(Adapter));
-#endif
- odm_AutoChannelSelectReset(podmpriv);
-
- } else if (ACS_SELECT == acs_op) {
- /* Collect NHM measurement result after current channel */
-#ifdef DBG_AUTO_CHNL_SEL_NHM
- RTW_INFO("[ACS-"ADPT_FMT"] HAL_ODM_AUTO_CHNL_SEL: ACS_SELECT, CH(%d)\n", ADPT_ARG(Adapter), rtw_get_acs_channel(Adapter));
-#endif
- odm_AutoChannelSelect(podmpriv, rtw_get_acs_channel(Adapter));
- } else
- RTW_INFO("[ACS-"ADPT_FMT"] HAL_ODM_AUTO_CHNL_SEL: Unexpected OP\n", ADPT_ARG(Adapter));
-
- }
- break;
-#endif
-#ifdef CONFIG_ANTENNA_DIVERSITY
- case HAL_ODM_ANTDIV_SELECT: {
- u8 antenna = (*(u8 *)pValue1);
-
- /*switch antenna*/
- ODM_UpdateRxIdleAnt(&pHalData->odmpriv, antenna);
- /*RTW_INFO("==> HAL_ODM_ANTDIV_SELECT, Ant_(%s)\n", (antenna == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");*/
-
- }
- break;
-#endif
-
- default:
- break;
- }
-}
-
-void GetHalODMVar(
- PADAPTER Adapter,
- HAL_ODM_VARIABLE eVariable,
- PVOID pValue1,
- PVOID pValue2)
-{
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
- PDM_ODM_T podmpriv = &pHalData->odmpriv;
-
- switch (eVariable) {
-#if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR)
- case HAL_ODM_NOISE_MONITOR: {
- u8 chan = *(u8 *)pValue1;
- *(s16 *)pValue2 = pHalData->noise[chan];
-#ifdef DBG_NOISE_MONITOR
- RTW_INFO("### Noise monitor chan(%d)-noise:%d (dBm) ###\n",
- chan, pHalData->noise[chan]);
-#endif
- }
- break;
-#endif/*#ifdef CONFIG_BACKGROUND_NOISE_MONITOR*/
- case HAL_ODM_DBG_FLAG:
- *((u8Byte *)pValue1) = podmpriv->DebugComponents;
- break;
- case HAL_ODM_DBG_LEVEL:
- *((u4Byte *)pValue1) = podmpriv->DebugLevel;
- break;
-
-#ifdef CONFIG_AUTO_CHNL_SEL_NHM
- case HAL_ODM_AUTO_CHNL_SEL: {
-#ifdef DBG_AUTO_CHNL_SEL_NHM
- RTW_INFO("[ACS-"ADPT_FMT"] HAL_ODM_AUTO_CHNL_SEL: GET_BEST_CHAN\n", ADPT_ARG(Adapter));
-#endif
- /* Retrieve better channel from NHM mechanism */
- if (IsSupported24G(Adapter->registrypriv.wireless_mode))
- *((u8 *)(pValue1)) = ODM_GetAutoChannelSelectResult(podmpriv, BAND_ON_2_4G);
- if (IsSupported5G(Adapter->registrypriv.wireless_mode))
- *((u8 *)(pValue2)) = ODM_GetAutoChannelSelectResult(podmpriv, BAND_ON_5G);
- }
- break;
-#endif
-#ifdef CONFIG_ANTENNA_DIVERSITY
- case HAL_ODM_ANTDIV_SELECT: {
- pFAT_T pDM_FatTable = &podmpriv->DM_FatTable;
- *((u8 *)pValue1) = pDM_FatTable->RxIdleAnt;
- }
- break;
-#endif
- case HAL_ODM_INITIAL_GAIN: {
- pDIG_T pDM_DigTable = &podmpriv->DM_DigTable;
- *((u8 *)pValue1) = pDM_DigTable->CurIGValue;
+ psta = rtw_get_stainfo(pstapriv, pmlmepriv->cur_network.network.MacAddress);
+ if (psta)
+ *((int *)value) = psta->cmn.rssi_stat.rssi;
}
break;
- default:
+ case HAL_DEF_DBG_DUMP_RXPKT:
+ *((u8 *)value) = hal_data->bDumpRxPkt;
break;
- }
-}
-
-
-u32 rtw_phydm_ability_ops(_adapter *adapter, HAL_PHYDM_OPS ops, u32 ability)
-{
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
- PDM_ODM_T podmpriv = &pHalData->odmpriv;
- u32 result = 0;
-
- switch (ops) {
- case HAL_PHYDM_DIS_ALL_FUNC:
- podmpriv->SupportAbility = DYNAMIC_FUNC_DISABLE;
+ case HAL_DEF_DBG_DUMP_TXPKT:
+ *((u8 *)value) = hal_data->bDumpTxPkt;
break;
- case HAL_PHYDM_FUNC_SET:
- podmpriv->SupportAbility |= ability;
+ case HAL_DEF_ANT_DETECT:
+ *((u8 *)value) = hal_data->AntDetection;
break;
- case HAL_PHYDM_FUNC_CLR:
- podmpriv->SupportAbility &= ~(ability);
+ case HAL_DEF_TX_PAGE_SIZE:
+ *((u32 *)value) = _get_page_size(adapter);
break;
- case HAL_PHYDM_ABILITY_BK:
- /* dm flag backup*/
- podmpriv->BK_SupportAbility = podmpriv->SupportAbility;
+ case HAL_DEF_EXPLICIT_BEAMFORMER:
+ case HAL_DEF_EXPLICIT_BEAMFORMEE:
+ case HAL_DEF_VHT_MU_BEAMFORMER:
+ case HAL_DEF_VHT_MU_BEAMFORMEE:
+ *(u8 *)value = _FALSE;
break;
- case HAL_PHYDM_ABILITY_RESTORE:
- /* restore dm flag */
- podmpriv->SupportAbility = podmpriv->BK_SupportAbility;
+#ifdef CONFIG_BEAMFORMING
+ case HAL_DEF_BEAMFORMER_CAP:
+ *(u8 *)value = rtw_hal_query_txbfer_rf_num(adapter);
break;
- case HAL_PHYDM_ABILITY_SET:
- podmpriv->SupportAbility = ability;
+ case HAL_DEF_BEAMFORMEE_CAP:
+ *(u8 *)value = rtw_hal_query_txbfee_rf_num(adapter);
break;
- case HAL_PHYDM_ABILITY_GET:
- result = podmpriv->SupportAbility;
+#endif
+ default:
+ RTW_PRINT("%s: [WARNING] HAL_DEF_VARIABLE(%d) not defined!\n", __FUNCTION__, variable);
+ bResult = _FAIL;
break;
}
- return result;
+
+ return bResult;
}
@@ -7925,8 +10725,13 @@ ParseQualifiedString(
return _FALSE;
i = (*Start);
- while ((c = In[(*Start)++]) != RightQualifier)
- ; /* find ']' */
+ c = In[(*Start)++];
+ while (c != RightQualifier && c != '\0')
+ c = In[(*Start)++];
+
+ if (c == '\0')
+ return _FALSE;
+
j = (*Start) - 2;
strncpy((char *)Out, (const char *)(In + i), j - i + 1);
@@ -7956,34 +10761,37 @@ void rtw_hal_check_rxfifo_full(_adapter *adapter)
{
struct dvobj_priv *psdpriv = adapter->dvobj;
struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
+ struct registry_priv *regsty = &adapter->registrypriv;
int save_cnt = _FALSE;
- /* switch counter to RX fifo */
- if (IS_8188E(pHalData->VersionID) ||
- IS_8188F(pHalData->VersionID) ||
- IS_8812_SERIES(pHalData->VersionID) ||
- IS_8821_SERIES(pHalData->VersionID) ||
- IS_8723B_SERIES(pHalData->VersionID) ||
- IS_8192E(pHalData->VersionID) ||
- IS_8703B_SERIES(pHalData->VersionID) ||
- IS_8723D_SERIES(pHalData->VersionID)) {
- rtw_write8(adapter, REG_RXERR_RPT + 3, rtw_read8(adapter, REG_RXERR_RPT + 3) | 0xa0);
- save_cnt = _TRUE;
- } else {
- /* todo: other chips */
- }
+ if (regsty->check_hw_status == 1) {
+ /* switch counter to RX fifo */
+ if (IS_8188E(pHalData->version_id) ||
+ IS_8188F(pHalData->version_id) ||
+ IS_8812_SERIES(pHalData->version_id) ||
+ IS_8821_SERIES(pHalData->version_id) ||
+ IS_8723B_SERIES(pHalData->version_id) ||
+ IS_8192E(pHalData->version_id) ||
+ IS_8703B_SERIES(pHalData->version_id) ||
+ IS_8723D_SERIES(pHalData->version_id)) {
+ rtw_write8(adapter, REG_RXERR_RPT + 3, rtw_read8(adapter, REG_RXERR_RPT + 3) | 0xa0);
+ save_cnt = _TRUE;
+ } else {
+ /* todo: other chips */
+ }
- if (save_cnt) {
- pdbgpriv->dbg_rx_fifo_last_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow;
- pdbgpriv->dbg_rx_fifo_curr_overflow = rtw_read16(adapter, REG_RXERR_RPT);
- pdbgpriv->dbg_rx_fifo_diff_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow - pdbgpriv->dbg_rx_fifo_last_overflow;
- } else {
- /* special value to indicate no implementation */
- pdbgpriv->dbg_rx_fifo_last_overflow = 1;
- pdbgpriv->dbg_rx_fifo_curr_overflow = 1;
- pdbgpriv->dbg_rx_fifo_diff_overflow = 1;
+ if (save_cnt) {
+ pdbgpriv->dbg_rx_fifo_last_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow;
+ pdbgpriv->dbg_rx_fifo_curr_overflow = rtw_read16(adapter, REG_RXERR_RPT);
+ pdbgpriv->dbg_rx_fifo_diff_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow - pdbgpriv->dbg_rx_fifo_last_overflow;
+ } else {
+ /* special value to indicate no implementation */
+ pdbgpriv->dbg_rx_fifo_last_overflow = 1;
+ pdbgpriv->dbg_rx_fifo_curr_overflow = 1;
+ pdbgpriv->dbg_rx_fifo_diff_overflow = 1;
+ }
}
}
@@ -8071,6 +10879,10 @@ void rtw_dump_raw_rssi_info(_adapter *padapter, void *sel)
#ifdef DBG_RX_DFRAME_RAW_DATA
void rtw_dump_rx_dframe_info(_adapter *padapter, void *sel)
{
+#define DBG_RX_DFRAME_RAW_DATA_UC 0
+#define DBG_RX_DFRAME_RAW_DATA_BMC 1
+#define DBG_RX_DFRAME_RAW_DATA_TYPES 2
+
_irqL irqL;
u8 isCCKrate, rf_path;
struct recv_priv *precvpriv = &(padapter->recvpriv);
@@ -8078,9 +10890,8 @@ void rtw_dump_rx_dframe_info(_adapter *padapter, void *sel)
struct sta_priv *pstapriv = &padapter->stapriv;
struct sta_info *psta;
struct sta_recv_dframe_info *psta_dframe_info;
- int i;
+ int i, j;
_list *plist, *phead;
- char *BW;
u8 bc_addr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
u8 null_addr[6] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
@@ -8098,53 +10909,38 @@ void rtw_dump_rx_dframe_info(_adapter *padapter, void *sel)
plist = get_next(plist);
if (psta) {
- psta_dframe_info = &psta->sta_dframe_info;
- if ((_rtw_memcmp(psta->hwaddr, bc_addr, 6) != _TRUE)
- && (_rtw_memcmp(psta->hwaddr, null_addr, 6) != _TRUE)
- && (_rtw_memcmp(psta->hwaddr, adapter_mac_addr(padapter), 6) != _TRUE)) {
-
-
- isCCKrate = (psta_dframe_info->sta_data_rate <= DESC_RATE11M) ? TRUE : FALSE;
-
- switch (psta_dframe_info->sta_bw_mode) {
-
- case CHANNEL_WIDTH_20:
- BW = "20M";
- break;
-
- case CHANNEL_WIDTH_40:
- BW = "40M";
- break;
-
- case CHANNEL_WIDTH_80:
- BW = "80M";
- break;
-
- case CHANNEL_WIDTH_160:
- BW = "160M";
- break;
-
- default:
- BW = "";
- break;
- }
+ if ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, 6) != _TRUE)
+ && (_rtw_memcmp(psta->cmn.mac_addr, null_addr, 6) != _TRUE)
+ && (_rtw_memcmp(psta->cmn.mac_addr, adapter_mac_addr(padapter), 6) != _TRUE)) {
RTW_PRINT_SEL(sel, "==============================\n");
- _RTW_PRINT_SEL(sel, "macaddr =" MAC_FMT "\n", MAC_ARG(psta->hwaddr));
- _RTW_PRINT_SEL(sel, "BW=%s, sgi =%d\n", BW, psta_dframe_info->sta_sgi);
- _RTW_PRINT_SEL(sel, "Rx_Data_Rate = %s\n", HDATA_RATE(psta_dframe_info->sta_data_rate));
-
- for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {
-
- if (!isCCKrate) {
-
- _RTW_PRINT_SEL(sel , "RF_PATH_%d RSSI:%d(dBm)", rf_path, psta_dframe_info->sta_RxPwr[rf_path]);
- _RTW_PRINT_SEL(sel , ",rx_ofdm_snr:%d(dB)\n", psta_dframe_info->sta_ofdm_snr[rf_path]);
-
- } else
-
- _RTW_PRINT_SEL(sel , "RF_PATH_%d RSSI:%d(dBm)\n", rf_path, (psta_dframe_info->sta_mimo_signal_strength[rf_path]) - 100);
+ RTW_PRINT_SEL(sel, "macaddr =" MAC_FMT "\n", MAC_ARG(psta->cmn.mac_addr));
+
+ for (j = 0; j < DBG_RX_DFRAME_RAW_DATA_TYPES; j++) {
+ if (j == DBG_RX_DFRAME_RAW_DATA_UC) {
+ psta_dframe_info = &psta->sta_dframe_info;
+ RTW_PRINT_SEL(sel, "\n");
+ RTW_PRINT_SEL(sel, "Unicast:\n");
+ } else if (j == DBG_RX_DFRAME_RAW_DATA_BMC) {
+ psta_dframe_info = &psta->sta_dframe_info_bmc;
+ RTW_PRINT_SEL(sel, "\n");
+ RTW_PRINT_SEL(sel, "Broadcast/Multicast:\n");
+ }
+
+ isCCKrate = (psta_dframe_info->sta_data_rate <= DESC_RATE11M) ? TRUE : FALSE;
+
+ RTW_PRINT_SEL(sel, "BW=%s, sgi =%d\n", ch_width_str(psta_dframe_info->sta_bw_mode), psta_dframe_info->sta_sgi);
+ RTW_PRINT_SEL(sel, "Rx_Data_Rate = %s\n", HDATA_RATE(psta_dframe_info->sta_data_rate));
+
+ for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {
+ if (!isCCKrate) {
+ RTW_PRINT_SEL(sel , "RF_PATH_%d RSSI:%d(dBm)", rf_path, psta_dframe_info->sta_RxPwr[rf_path]);
+ _RTW_PRINT_SEL(sel , ",rx_ofdm_snr:%d(dB)\n", psta_dframe_info->sta_ofdm_snr[rf_path]);
+ } else
+ RTW_PRINT_SEL(sel , "RF_PATH_%d RSSI:%d(dBm)\n", rf_path, (psta_dframe_info->sta_mimo_signal_strength[rf_path]) - 100);
+ }
}
+
}
}
}
@@ -8165,7 +10961,7 @@ void rtw_store_phy_info(_adapter *padapter, union recv_frame *prframe)
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
struct sta_info *psta = prframe->u.hdr.psta;
- PODM_PHY_INFO_T pPhyInfo = (PODM_PHY_INFO_T)(&pattrib->phy_info);
+ struct phydm_phyinfo_struct *p_phy_info = &pattrib->phy_info;
struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;
psample_pkt_rssi->data_rate = pattrib->data_rate;
ptr = prframe->u.hdr.rx_data;
@@ -8176,36 +10972,39 @@ void rtw_store_phy_info(_adapter *padapter, union recv_frame *prframe)
if (precvpriv->store_law_data_flag) {
isCCKrate = (pattrib->data_rate <= DESC_RATE11M) ? TRUE : FALSE;
- psample_pkt_rssi->pwdball = pPhyInfo->RxPWDBAll;
- psample_pkt_rssi->pwr_all = pPhyInfo->RecvSignalPower;
+ psample_pkt_rssi->pwdball = p_phy_info->rx_pwdb_all;
+ psample_pkt_rssi->pwr_all = p_phy_info->recv_signal_power;
for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {
- psample_pkt_rssi->mimo_signal_strength[rf_path] = pPhyInfo->RxMIMOSignalStrength[rf_path];
- psample_pkt_rssi->mimo_signal_quality[rf_path] = pPhyInfo->RxMIMOSignalQuality[rf_path];
+ psample_pkt_rssi->mimo_signal_strength[rf_path] = p_phy_info->rx_mimo_signal_strength[rf_path];
+ psample_pkt_rssi->mimo_signal_quality[rf_path] = p_phy_info->rx_mimo_signal_quality[rf_path];
if (!isCCKrate) {
- psample_pkt_rssi->ofdm_pwr[rf_path] = pPhyInfo->RxPwr[rf_path];
- psample_pkt_rssi->ofdm_snr[rf_path] = pPhyInfo->RxSNR[rf_path];
+ psample_pkt_rssi->ofdm_pwr[rf_path] = p_phy_info->rx_pwr[rf_path];
+ psample_pkt_rssi->ofdm_snr[rf_path] = p_phy_info->rx_snr[rf_path];
}
}
#ifdef DBG_RX_DFRAME_RAW_DATA
- if (dframe_type == WIFI_DATA_TYPE || dframe_type == WIFI_QOS_DATA_TYPE) {
+ if ((dframe_type == WIFI_DATA_TYPE) || (dframe_type == WIFI_QOS_DATA_TYPE) || (padapter->registrypriv.mp_mode == 1)) {
/*RTW_INFO("=>%s WIFI_DATA_TYPE or WIFI_QOS_DATA_TYPE\n", __FUNCTION__);*/
if (psta) {
- psta_dframe_info = &psta->sta_dframe_info;
- /*RTW_INFO("=>%s psta->hwaddr="MAC_FMT" !\n", __FUNCTION__, MAC_ARG(psta->hwaddr));*/
- if (_rtw_memcmp(psta->hwaddr, bc_addr, ETH_ALEN) != _TRUE) {
-
+ if (IS_MCAST(get_ra(get_recvframe_data(prframe))))
+ psta_dframe_info = &psta->sta_dframe_info_bmc;
+ else
+ psta_dframe_info = &psta->sta_dframe_info;
+ /*RTW_INFO("=>%s psta->cmn.mac_addr="MAC_FMT" !\n",
+ __FUNCTION__, MAC_ARG(psta->cmn.mac_addr));*/
+ if ((_rtw_memcmp(psta->cmn.mac_addr, bc_addr, ETH_ALEN) != _TRUE) || (padapter->registrypriv.mp_mode == 1)) {
psta_dframe_info->sta_data_rate = pattrib->data_rate;
psta_dframe_info->sta_sgi = pattrib->sgi;
psta_dframe_info->sta_bw_mode = pattrib->bw;
for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {
- psta_dframe_info->sta_mimo_signal_strength[rf_path] = (pPhyInfo->RxMIMOSignalStrength[rf_path]);/*Percentage to dbm*/
+ psta_dframe_info->sta_mimo_signal_strength[rf_path] = (p_phy_info->rx_mimo_signal_strength[rf_path]);/*Percentage to dbm*/
if (!isCCKrate) {
- psta_dframe_info->sta_ofdm_snr[rf_path] = pPhyInfo->RxSNR[rf_path];
- psta_dframe_info->sta_RxPwr[rf_path] = pPhyInfo->RxPwr[rf_path];
+ psta_dframe_info->sta_ofdm_snr[rf_path] = p_phy_info->rx_snr[rf_path];
+ psta_dframe_info->sta_RxPwr[rf_path] = p_phy_info->rx_pwr[rf_path];
}
}
}
@@ -8216,61 +11015,6 @@ void rtw_store_phy_info(_adapter *padapter, union recv_frame *prframe)
}
-
-int check_phy_efuse_tx_power_info_valid(PADAPTER padapter)
-{
- PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
- u8 *pContent = pHalData->efuse_eeprom_data;
- int index = 0;
- u16 tx_index_offset = 0x0000;
-
- switch (rtw_get_chip_type(padapter)) {
- case RTL8723B:
- tx_index_offset = EEPROM_TX_PWR_INX_8723B;
- break;
- case RTL8703B:
- tx_index_offset = EEPROM_TX_PWR_INX_8703B;
- break;
- case RTL8723D:
- tx_index_offset = EEPROM_TX_PWR_INX_8723D;
- break;
- case RTL8188E:
- tx_index_offset = EEPROM_TX_PWR_INX_88E;
- break;
- case RTL8188F:
- tx_index_offset = EEPROM_TX_PWR_INX_8188F;
- break;
- case RTL8192E:
- tx_index_offset = EEPROM_TX_PWR_INX_8192E;
- break;
- case RTL8821:
- tx_index_offset = EEPROM_TX_PWR_INX_8821;
- break;
- case RTL8812:
- tx_index_offset = EEPROM_TX_PWR_INX_8812;
- break;
- case RTL8814A:
- tx_index_offset = EEPROM_TX_PWR_INX_8814;
- break;
- case RTL8822B:
- tx_index_offset = EEPROM_TX_PWR_INX_8822B;
- break;
- case RTL8821C:
- tx_index_offset = EEPROM_TX_PWR_INX_8821C;
- break;
- default:
- tx_index_offset = 0x0010;
- break;
- }
-
- /* TODO: chacking length by ICs */
- for (index = 0 ; index < 11 ; index++) {
- if (pContent[tx_index_offset + index] == 0xFF)
- return _FALSE;
- }
- return _TRUE;
-}
-
int hal_efuse_macaddr_offset(_adapter *adapter)
{
u8 interface_type = 0;
@@ -8418,23 +11162,16 @@ void rtw_dump_cur_efuse(PADAPTER padapter)
EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&mapsize, _FALSE);
if (mapsize <= 0 || mapsize > EEPROM_MAX_SIZE) {
- RTW_INFO("wrong map size %d\n", mapsize);
+ RTW_ERR("wrong map size %d\n", mapsize);
return;
}
+#ifdef CONFIG_RTW_DEBUG
if (hal_data->efuse_file_status == EFUSE_FILE_LOADED)
- RTW_INFO("Use EFUSE FILE\n");
+ RTW_MAP_DUMP_SEL(RTW_DBGDUMP, "EFUSE FILE", hal_data->efuse_eeprom_data, mapsize);
else
- RTW_INFO("HW EFUSE\n");
-
-#ifdef CONFIG_RTW_DEBUG
-#ifdef PLATFORM_LINUX
- RTW_INFO("eFuse Content:\n");
- print_hex_dump(KERN_DEBUG, "eFuse ",
- DUMP_PREFIX_OFFSET, 16, 1,
- hal_data->efuse_eeprom_data, mapsize, false);
-#endif /* PLATFORM_LINUX */
-#endif /* CONFIG_RTW_DEBUG */
+ RTW_MAP_DUMP_SEL(RTW_DBGDUMP, "HW EFUSE", hal_data->efuse_eeprom_data, mapsize);
+#endif
}
@@ -8452,12 +11189,13 @@ u32 Hal_readPGDataFromConfigFile(PADAPTER padapter)
return _FALSE;
}
- ret = rtw_efuse_file_read(padapter, EFUSE_MAP_PATH, hal_data->efuse_eeprom_data, maplen);
- if (ret == _FALSE)
- ret = rtw_read_efuse_from_file(EFUSE_MAP_PATH, hal_data->efuse_eeprom_data);
+ ret = rtw_read_efuse_from_file(EFUSE_MAP_PATH, hal_data->efuse_eeprom_data, maplen);
hal_data->efuse_file_status = ((ret == _FAIL) ? EFUSE_FILE_FAILED : EFUSE_FILE_LOADED);
+ if (hal_data->efuse_file_status == EFUSE_FILE_LOADED)
+ rtw_dump_cur_efuse(padapter);
+
return ret;
}
@@ -8467,8 +11205,8 @@ u32 Hal_ReadMACAddrFromFile(PADAPTER padapter, u8 *mac_addr)
u32 ret = _FAIL;
if (rtw_read_macaddr_from_file(WIFIMAC_PATH, mac_addr) == _SUCCESS
- && rtw_check_invalid_mac_address(mac_addr, _TRUE) == _FALSE
- ) {
+ && rtw_check_invalid_mac_address(mac_addr, _TRUE) == _FALSE
+ ) {
hal_data->macaddr_file_status = MACADDR_FILE_LOADED;
ret = _SUCCESS;
} else
@@ -8485,6 +11223,9 @@ int hal_config_macaddr(_adapter *adapter, bool autoload_fail)
int addr_offset = hal_efuse_macaddr_offset(adapter);
u8 *hw_addr = NULL;
int ret = _SUCCESS;
+#if defined(CONFIG_RTL8822B) && defined(CONFIG_USB_HCI)
+ u8 ft_mac_addr[ETH_ALEN] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff}; /* FT USB2 for 8822B */
+#endif
if (autoload_fail)
goto bypass_hw_pg;
@@ -8504,6 +11245,11 @@ int hal_config_macaddr(_adapter *adapter, bool autoload_fail)
hw_addr = addr;
}
+#if defined(CONFIG_RTL8822B) && defined(CONFIG_USB_HCI)
+ if (_rtw_memcmp(hw_addr, ft_mac_addr, ETH_ALEN))
+ hw_addr[0] = 0xff;
+#endif
+
/* check hw pg data */
if (hw_addr && rtw_check_invalid_mac_address(hw_addr, _TRUE) == _FALSE) {
_rtw_memcpy(hal_data->EEPROMMACAddr, hw_addr, ETH_ALEN);
@@ -8559,18 +11305,18 @@ void rtw_bb_rf_gain_offset(_adapter *padapter)
}
#if defined(CONFIG_RTL8723B)
- if (value & BIT4 || (registry_par->RegPwrTrimEnable == 1)) {
+ if (value & BIT4 && (registry_par->RegPwrTrimEnable == 1)) {
RTW_INFO("Offset RF Gain.\n");
RTW_INFO("Offset RF Gain. pHalData->EEPROMRFGainVal=0x%x\n", pHalData->EEPROMRFGainVal);
if (pHalData->EEPROMRFGainVal != 0xff) {
- if (pHalData->ant_path == ODM_RF_PATH_A)
+ if (pHalData->ant_path == RF_PATH_A)
GainValue = (pHalData->EEPROMRFGainVal & 0x0f);
else
GainValue = (pHalData->EEPROMRFGainVal & 0xf0) >> 4;
- RTW_INFO("Ant PATH_%d GainValue Offset = 0x%x\n", (pHalData->ant_path == ODM_RF_PATH_A) ? (ODM_RF_PATH_A) : (ODM_RF_PATH_B), GainValue);
+ RTW_INFO("Ant PATH_%d GainValue Offset = 0x%x\n", (pHalData->ant_path == RF_PATH_A) ? (RF_PATH_A) : (RF_PATH_B), GainValue);
for (i = 0; i < ArrayLen; i += 2) {
/* RTW_INFO("ArrayLen in =%d ,Array 1 =0x%x ,Array2 =0x%x\n",i,Array[i],Array[i]+1); */
@@ -8586,7 +11332,7 @@ void rtw_bb_rf_gain_offset(_adapter *padapter)
res = rtw_hal_read_rfreg(padapter, RF_PATH_A, 0x7f, 0xffffffff);
RTW_INFO("Offset RF Gain. before reg 0x7f=0x%08x\n", res);
- PHY_SetRFReg(padapter, RF_PATH_A, REG_RF_BB_GAIN_OFFSET, BIT18 | BIT17 | BIT16 | BIT15, target);
+ phy_set_rf_reg(padapter, RF_PATH_A, REG_RF_BB_GAIN_OFFSET, BIT18 | BIT17 | BIT16 | BIT15, target);
res = rtw_hal_read_rfreg(padapter, RF_PATH_A, 0x7f, 0xffffffff);
RTW_INFO("Offset RF Gain. After reg 0x7f=0x%08x\n", res);
@@ -8598,7 +11344,7 @@ void rtw_bb_rf_gain_offset(_adapter *padapter)
RTW_INFO("Using the default RF gain.\n");
#elif defined(CONFIG_RTL8188E)
- if (value & BIT4 || (registry_par->RegPwrTrimEnable == 1)) {
+ if (value & BIT4 && (registry_par->RegPwrTrimEnable == 1)) {
RTW_INFO("8188ES Offset RF Gain.\n");
RTW_INFO("8188ES Offset RF Gain. EEPROMRFGainVal=0x%x\n",
pHalData->EEPROMRFGainVal);
@@ -8756,10 +11502,18 @@ void dm_DynamicUsbTxAgg(_adapter *padapter, u8 from_timer)
{
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+ struct registry_priv *registry_par = &padapter->registrypriv;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
u8 cur_wireless_mode = WIRELESS_INVALID;
#ifdef CONFIG_USB_RX_AGGREGATION
+ if (!registry_par->dynamic_agg_enable)
+ return;
+
+#ifdef RTW_HALMAC
+ if (IS_HARDWARE_TYPE_8822BU(padapter) || IS_HARDWARE_TYPE_8821CU(padapter))
+ rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, NULL);
+#else /* !RTW_HALMAC */
if (IS_HARDWARE_TYPE_8821U(padapter)) { /* || IS_HARDWARE_TYPE_8192EU(padapter)) */
/* This AGG_PH_TH only for UsbRxAggMode == USB_RX_AGG_USB */
if ((pHalData->rxagg_mode == RX_AGG_USB) && (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)) {
@@ -8796,7 +11550,9 @@ void dm_DynamicUsbTxAgg(_adapter *padapter, u8 from_timer)
rtw_set_usb_agg_by_mode(padapter, cur_wireless_mode);
#endif /* CONFIG_PLATFORM_NOVATEK_NT72668 */
}
-#endif
+#endif /* RTW_HALMAC */
+#endif /* CONFIG_USB_RX_AGGREGATION */
+
}
/* bus-agg check for SoftAP mode */
@@ -8805,7 +11561,7 @@ inline u8 rtw_hal_busagg_qsel_check(_adapter *padapter, u8 pre_qsel, u8 next_qse
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
u8 chk_rst = _SUCCESS;
- if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
+ if (!MLME_IS_AP(padapter) && !MLME_IS_MESH(padapter))
return chk_rst;
/* if((pre_qsel == 0xFF)||(next_qsel== 0xFF)) */
@@ -8870,7 +11626,9 @@ u8 rtw_hal_get_gpio(_adapter *adapter, u8 gpio_num)
{
u8 value = 0;
u8 direction = 0;
- u32 gpio_ctrl_reg_to_set = REG_GPIO_PIN_CTRL + 2;
+ u32 gpio_pin_input_val = REG_GPIO_PIN_CTRL;
+ u32 gpio_pin_output_val = REG_GPIO_PIN_CTRL + 1;
+ u32 gpio_pin_output_en = REG_GPIO_PIN_CTRL + 2;
u8 gpio_num_to_set = gpio_num;
struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
@@ -8883,18 +11641,20 @@ u8 rtw_hal_get_gpio(_adapter *adapter, u8 gpio_num)
LeaveAllPowerSaveModeDirect(adapter);
if (gpio_num > 7) {
- gpio_ctrl_reg_to_set = REG_GPIO_PIN_CTRL_2 + 2;
+ gpio_pin_input_val = REG_GPIO_PIN_CTRL_2;
+ gpio_pin_output_val = REG_GPIO_PIN_CTRL_2 + 1;
+ gpio_pin_output_en = REG_GPIO_PIN_CTRL_2 + 2;
gpio_num_to_set = gpio_num - 8;
}
/* Read GPIO Direction */
- direction = (rtw_read8(adapter, gpio_ctrl_reg_to_set) & BIT(gpio_num_to_set)) >> gpio_num;
+ direction = (rtw_read8(adapter, gpio_pin_output_en) & BIT(gpio_num_to_set)) >> gpio_num_to_set;
/* According the direction to read register value */
if (direction)
- value = (rtw_read8(adapter, gpio_ctrl_reg_to_set) & BIT(gpio_num_to_set)) >> gpio_num;
+ value = (rtw_read8(adapter, gpio_pin_output_val) & BIT(gpio_num_to_set)) >> gpio_num_to_set;
else
- value = (rtw_read8(adapter, gpio_ctrl_reg_to_set) & BIT(gpio_num_to_set)) >> gpio_num;
+ value = (rtw_read8(adapter, gpio_pin_input_val) & BIT(gpio_num_to_set)) >> gpio_num_to_set;
rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
RTW_INFO("%s direction=%d value=%d\n", __FUNCTION__, direction, value);
@@ -8906,7 +11666,8 @@ int rtw_hal_set_gpio_output_value(_adapter *adapter, u8 gpio_num, bool isHigh)
{
u8 direction = 0;
u8 res = -1;
- u32 gpio_ctrl_reg_to_set = REG_GPIO_PIN_CTRL + 2;
+ u32 gpio_pin_output_val = REG_GPIO_PIN_CTRL + 1;
+ u32 gpio_pin_output_en = REG_GPIO_PIN_CTRL + 2;
u8 gpio_num_to_set = gpio_num;
if (rtw_hal_gpio_func_check(adapter, gpio_num) == _FAIL)
@@ -8917,19 +11678,20 @@ int rtw_hal_set_gpio_output_value(_adapter *adapter, u8 gpio_num, bool isHigh)
LeaveAllPowerSaveModeDirect(adapter);
if (gpio_num > 7) {
- gpio_ctrl_reg_to_set = REG_GPIO_PIN_CTRL_2 + 2;
+ gpio_pin_output_val = REG_GPIO_PIN_CTRL_2 + 1;
+ gpio_pin_output_en = REG_GPIO_PIN_CTRL_2 + 2;
gpio_num_to_set = gpio_num - 8;
}
/* Read GPIO direction */
- direction = (rtw_read8(adapter, REG_GPIO_PIN_CTRL + 2) & BIT(gpio_num)) >> gpio_num;
+ direction = (rtw_read8(adapter, gpio_pin_output_en) & BIT(gpio_num_to_set)) >> gpio_num_to_set;
/* If GPIO is output direction, setting value. */
if (direction) {
if (isHigh)
- rtw_write8(adapter, gpio_ctrl_reg_to_set, rtw_read8(adapter, gpio_ctrl_reg_to_set) | BIT(gpio_num_to_set));
+ rtw_write8(adapter, gpio_pin_output_val, rtw_read8(adapter, gpio_pin_output_val) | BIT(gpio_num_to_set));
else
- rtw_write8(adapter, gpio_ctrl_reg_to_set, rtw_read8(adapter, gpio_ctrl_reg_to_set) & ~BIT(gpio_num_to_set));
+ rtw_write8(adapter, gpio_pin_output_val, rtw_read8(adapter, gpio_pin_output_val) & ~BIT(gpio_num_to_set));
RTW_INFO("%s Set gpio %x[%d]=%d\n", __FUNCTION__, REG_GPIO_PIN_CTRL + 1, gpio_num, isHigh);
res = 0;
@@ -9080,7 +11842,7 @@ void rtw_hal_ch_sw_iqk_info_backup(_adapter *padapter)
u8 i;
/* If it's an existed record, overwrite it */
- res = rtw_hal_ch_sw_iqk_info_search(padapter, pHalData->CurrentChannel, pHalData->CurrentChannelBW);
+ res = rtw_hal_ch_sw_iqk_info_search(padapter, pHalData->current_channel, pHalData->current_channel_bw);
if ((res >= 0) && (res < MAX_IQK_INFO_BACKUP_CHNL_NUM)) {
rtw_hal_set_hwreg(padapter, HW_VAR_CH_SW_IQK_INFO_BACKUP, (u8 *)&(pHalData->iqk_reg_backup[res]));
return;
@@ -9118,42 +11880,42 @@ void rtw_dump_mac_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_coun
return;
}
if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter))
- PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT26, 0x0);/*clear bit-26*/
-
- PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x3);
- mac_cck_ok = PHY_QueryMacReg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */
- PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x0);
- mac_ofdm_ok = PHY_QueryMacReg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */
- PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x6);
- mac_ht_ok = PHY_QueryMacReg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */
+ phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x0);/*clear bit-26*/
+
+ phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x3);
+ mac_cck_ok = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */
+ phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x0);
+ mac_ofdm_ok = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */
+ phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x6);
+ mac_ht_ok = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */
mac_vht_ok = 0;
if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) {
- PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x0);
- PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT26, 0x1);
- mac_vht_ok = PHY_QueryMacReg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]*/
- PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT26, 0x0);/*clear bit-26*/
- }
-
- PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x4);
- mac_cck_err = PHY_QueryMacReg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */
- PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x1);
- mac_ofdm_err = PHY_QueryMacReg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */
- PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x7);
- mac_ht_err = PHY_QueryMacReg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */
+ phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x0);
+ phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x1);
+ mac_vht_ok = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]*/
+ phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x0);/*clear bit-26*/
+ }
+
+ phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x4);
+ mac_cck_err = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */
+ phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x1);
+ mac_ofdm_err = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */
+ phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x7);
+ mac_ht_err = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */
mac_vht_err = 0;
if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) {
- PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x1);
- PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT26, 0x1);
- mac_vht_err = PHY_QueryMacReg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]*/
- PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT26, 0x0);/*clear bit-26*/
+ phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x1);
+ phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x1);
+ mac_vht_err = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]*/
+ phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x0);/*clear bit-26*/
}
- PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x5);
- mac_cck_fa = PHY_QueryMacReg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */
- PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x2);
- mac_ofdm_fa = PHY_QueryMacReg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */
- PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x9);
- mac_ht_fa = PHY_QueryMacReg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */
+ phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x5);
+ mac_cck_fa = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */
+ phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x2);
+ mac_ofdm_fa = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */
+ phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x9);
+ mac_ht_fa = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */
/* Mac_DropPacket */
rtw_write32(padapter, REG_RXERR_RPT, (rtw_read32(padapter, REG_RXERR_RPT) & 0x0FFFFFFF) | Mac_DropPacket);
@@ -9173,11 +11935,11 @@ void rtw_reset_mac_rx_counters(_adapter *padapter)
if (IS_HARDWARE_TYPE_8703B(padapter) ||
IS_HARDWARE_TYPE_8723D(padapter) ||
IS_HARDWARE_TYPE_8188F(padapter))
- PHY_SetMacReg(padapter, REG_RCR, BIT19, 0x1);
+ phy_set_mac_reg(padapter, REG_RCR, BIT19, 0x1);
/* reset mac counter */
- PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT27, 0x1);
- PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT27, 0x0);
+ phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT27, 0x1);
+ phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT27, 0x0);
}
void rtw_dump_phy_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter)
@@ -9188,28 +11950,28 @@ void rtw_dump_phy_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_coun
return;
}
if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) {
- cckok = PHY_QueryBBReg(padapter, 0xF04, 0x3FFF); /* [13:0] */
- ofdmok = PHY_QueryBBReg(padapter, 0xF14, 0x3FFF); /* [13:0] */
- htok = PHY_QueryBBReg(padapter, 0xF10, 0x3FFF); /* [13:0] */
- vht_ok = PHY_QueryBBReg(padapter, 0xF0C, 0x3FFF); /* [13:0] */
- cckcrc = PHY_QueryBBReg(padapter, 0xF04, 0x3FFF0000); /* [29:16] */
- ofdmcrc = PHY_QueryBBReg(padapter, 0xF14, 0x3FFF0000); /* [29:16] */
- htcrc = PHY_QueryBBReg(padapter, 0xF10, 0x3FFF0000); /* [29:16] */
- vht_err = PHY_QueryBBReg(padapter, 0xF0C, 0x3FFF0000); /* [29:16] */
- CCK_FA = PHY_QueryBBReg(padapter, 0xA5C, bMaskLWord);
- OFDM_FA = PHY_QueryBBReg(padapter, 0xF48, bMaskLWord);
+ cckok = phy_query_bb_reg(padapter, 0xF04, 0x3FFF); /* [13:0] */
+ ofdmok = phy_query_bb_reg(padapter, 0xF14, 0x3FFF); /* [13:0] */
+ htok = phy_query_bb_reg(padapter, 0xF10, 0x3FFF); /* [13:0] */
+ vht_ok = phy_query_bb_reg(padapter, 0xF0C, 0x3FFF); /* [13:0] */
+ cckcrc = phy_query_bb_reg(padapter, 0xF04, 0x3FFF0000); /* [29:16] */
+ ofdmcrc = phy_query_bb_reg(padapter, 0xF14, 0x3FFF0000); /* [29:16] */
+ htcrc = phy_query_bb_reg(padapter, 0xF10, 0x3FFF0000); /* [29:16] */
+ vht_err = phy_query_bb_reg(padapter, 0xF0C, 0x3FFF0000); /* [29:16] */
+ CCK_FA = phy_query_bb_reg(padapter, 0xA5C, bMaskLWord);
+ OFDM_FA = phy_query_bb_reg(padapter, 0xF48, bMaskLWord);
} else {
- cckok = PHY_QueryBBReg(padapter, 0xF88, bMaskDWord);
- ofdmok = PHY_QueryBBReg(padapter, 0xF94, bMaskLWord);
- htok = PHY_QueryBBReg(padapter, 0xF90, bMaskLWord);
+ cckok = phy_query_bb_reg(padapter, 0xF88, bMaskDWord);
+ ofdmok = phy_query_bb_reg(padapter, 0xF94, bMaskLWord);
+ htok = phy_query_bb_reg(padapter, 0xF90, bMaskLWord);
vht_ok = 0;
- cckcrc = PHY_QueryBBReg(padapter, 0xF84, bMaskDWord);
- ofdmcrc = PHY_QueryBBReg(padapter, 0xF94, bMaskHWord);
- htcrc = PHY_QueryBBReg(padapter, 0xF90, bMaskHWord);
+ cckcrc = phy_query_bb_reg(padapter, 0xF84, bMaskDWord);
+ ofdmcrc = phy_query_bb_reg(padapter, 0xF94, bMaskHWord);
+ htcrc = phy_query_bb_reg(padapter, 0xF90, bMaskHWord);
vht_err = 0;
- OFDM_FA = PHY_QueryBBReg(padapter, 0xCF0, bMaskLWord) + PHY_QueryBBReg(padapter, 0xCF2, bMaskLWord) +
- PHY_QueryBBReg(padapter, 0xDA2, bMaskLWord) + PHY_QueryBBReg(padapter, 0xDA4, bMaskLWord) +
- PHY_QueryBBReg(padapter, 0xDA6, bMaskLWord) + PHY_QueryBBReg(padapter, 0xDA8, bMaskLWord);
+ OFDM_FA = phy_query_bb_reg(padapter, 0xCF0, bMaskLWord) + phy_query_bb_reg(padapter, 0xCF2, bMaskLWord) +
+ phy_query_bb_reg(padapter, 0xDA2, bMaskLWord) + phy_query_bb_reg(padapter, 0xDA4, bMaskLWord) +
+ phy_query_bb_reg(padapter, 0xDA6, bMaskLWord) + phy_query_bb_reg(padapter, 0xDA8, bMaskLWord);
CCK_FA = (rtw_read8(padapter, 0xA5B) << 8) | (rtw_read8(padapter, 0xA5C));
}
@@ -9224,8 +11986,8 @@ void rtw_dump_phy_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_coun
void rtw_reset_phy_trx_ok_counters(_adapter *padapter)
{
if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) {
- PHY_SetBBReg(padapter, 0xB58, BIT0, 0x1);
- PHY_SetBBReg(padapter, 0xB58, BIT0, 0x0);
+ phy_set_bb_reg(padapter, 0xB58, BIT0, 0x1);
+ phy_set_bb_reg(padapter, 0xB58, BIT0, 0x0);
}
}
void rtw_reset_phy_rx_counters(_adapter *padapter)
@@ -9234,23 +11996,23 @@ void rtw_reset_phy_rx_counters(_adapter *padapter)
if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) {
rtw_reset_phy_trx_ok_counters(padapter);
- PHY_SetBBReg(padapter, 0x9A4, BIT17, 0x1);/* reset OFDA FA counter */
- PHY_SetBBReg(padapter, 0x9A4, BIT17, 0x0);
+ phy_set_bb_reg(padapter, 0x9A4, BIT17, 0x1);/* reset OFDA FA counter */
+ phy_set_bb_reg(padapter, 0x9A4, BIT17, 0x0);
- PHY_SetBBReg(padapter, 0xA2C, BIT15, 0x0);/* reset CCK FA counter */
- PHY_SetBBReg(padapter, 0xA2C, BIT15, 0x1);
+ phy_set_bb_reg(padapter, 0xA2C, BIT15, 0x0);/* reset CCK FA counter */
+ phy_set_bb_reg(padapter, 0xA2C, BIT15, 0x1);
} else {
- PHY_SetBBReg(padapter, 0xF14, BIT16, 0x1);
+ phy_set_bb_reg(padapter, 0xF14, BIT16, 0x1);
rtw_msleep_os(10);
- PHY_SetBBReg(padapter, 0xF14, BIT16, 0x0);
+ phy_set_bb_reg(padapter, 0xF14, BIT16, 0x0);
- PHY_SetBBReg(padapter, 0xD00, BIT27, 0x1);/* reset OFDA FA counter */
- PHY_SetBBReg(padapter, 0xC0C, BIT31, 0x1);/* reset OFDA FA counter */
- PHY_SetBBReg(padapter, 0xD00, BIT27, 0x0);
- PHY_SetBBReg(padapter, 0xC0C, BIT31, 0x0);
+ phy_set_bb_reg(padapter, 0xD00, BIT27, 0x1);/* reset OFDA FA counter */
+ phy_set_bb_reg(padapter, 0xC0C, BIT31, 0x1);/* reset OFDA FA counter */
+ phy_set_bb_reg(padapter, 0xD00, BIT27, 0x0);
+ phy_set_bb_reg(padapter, 0xC0C, BIT31, 0x0);
- PHY_SetBBReg(padapter, 0xA2C, BIT15, 0x0);/* reset CCK FA counter */
- PHY_SetBBReg(padapter, 0xA2C, BIT15, 0x1);
+ phy_set_bb_reg(padapter, 0xA2C, BIT15, 0x0);/* reset CCK FA counter */
+ phy_set_bb_reg(padapter, 0xA2C, BIT15, 0x1);
}
}
#ifdef DBG_RX_COUNTER_DUMP
@@ -9326,115 +12088,41 @@ void rtw_dump_rx_counters(_adapter *padapter)
}
}
#endif
-void rtw_get_noise(_adapter *padapter)
-{
-#if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR)
- struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
- struct noise_info info;
- if (rtw_linked_check(padapter)) {
- info.bPauseDIG = _TRUE;
- info.IGIValue = 0x1e;
- info.max_time = 100;/* ms */
- info.chan = pmlmeext->cur_channel ;/* rtw_get_oper_ch(padapter); */
- rtw_ps_deny(padapter, PS_DENY_IOCTL);
- LeaveAllPowerSaveModeDirect(padapter);
-
- rtw_hal_set_odm_var(padapter, HAL_ODM_NOISE_MONITOR, &info, _FALSE);
- /* ODM_InbandNoise_Monitor(podmpriv,_TRUE,0x20,100); */
- rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL);
- rtw_hal_get_odm_var(padapter, HAL_ODM_NOISE_MONITOR, &(info.chan), &(padapter->recvpriv.noise));
-#ifdef DBG_NOISE_MONITOR
- RTW_INFO("chan:%d,noise_level:%d\n", info.chan, padapter->recvpriv.noise);
-#endif
- }
-#endif
-
-}
-u8 rtw_get_current_tx_sgi(_adapter *padapter, u8 macid)
+u8 rtw_get_current_tx_sgi(_adapter *padapter, struct sta_info *psta)
{
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
- PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
- pRA_T pRA_Table = &pDM_Odm->DM_RA_Table;
u8 curr_tx_sgi = 0;
+ struct ra_sta_info *ra_info;
-#if defined(CONFIG_RTL8188E)
- curr_tx_sgi = ODM_RA_GetDecisionRate_8188E(pDM_Odm, macid);
-#else
- curr_tx_sgi = ((pRA_Table->link_tx_rate[macid]) & 0x80) >> 7;
-#endif
+ if (!psta)
+ return curr_tx_sgi;
- return curr_tx_sgi;
+ if (padapter->fix_rate == 0xff) {
+ ra_info = &psta->cmn.ra_info;
+ curr_tx_sgi = ((ra_info->curr_tx_rate) & 0x80) >> 7;
+ } else {
+ curr_tx_sgi = ((padapter->fix_rate) & 0x80) >> 7;
+ }
+ return curr_tx_sgi;
}
-u8 rtw_get_current_tx_rate(_adapter *padapter, u8 macid)
+u8 rtw_get_current_tx_rate(_adapter *padapter, struct sta_info *psta)
{
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
- PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
- pRA_T pRA_Table = &pDM_Odm->DM_RA_Table;
u8 rate_id = 0;
+ struct ra_sta_info *ra_info;
-#if (RATE_ADAPTIVE_SUPPORT == 1)
- rate_id = ODM_RA_GetDecisionRate_8188E(pDM_Odm, macid);
-#else
- rate_id = (pRA_Table->link_tx_rate[macid]) & 0x7f;
-#endif
+ if (!psta)
+ return rate_id;
- return rate_id;
+ if (padapter->fix_rate == 0xff) {
+ ra_info = &psta->cmn.ra_info;
+ rate_id = ra_info->curr_tx_rate & 0x7f;
+ } else {
+ rate_id = padapter->fix_rate & 0x7f;
+ }
+ return rate_id;
}
-#ifdef CONFIG_FW_C2H_DEBUG
-
-/* C2H RX package original is 128.
-if enable CONFIG_FW_C2H_DEBUG, it should increase to 256.
- C2H FW debug message:
- without aggregate:
- {C2H_CmdID,Seq,SubID,Len,Content[0~n]}
- Content[0~n]={'a','b','c',...,'z','\n'}
- with aggregate:
- {C2H_CmdID,Seq,SubID,Len,Content[0~n]}
- Content[0~n]={'a','b','c',...,'z','\n',Extend C2H pkt 2...}
- Extend C2H pkt 2={C2H CmdID,Seq,SubID,Len,Content = {'a','b','c',...,'z','\n'}}
- Author: Isaac */
-
-void Debug_FwC2H(PADAPTER padapter, u8 *pdata, u8 len)
-{
- int i = 0;
- int cnt = 0, total_length = 0;
- u8 buf[128] = {0};
- u8 more_data = _FALSE;
- u8 *nextdata = NULL;
- u8 test = 0;
-
- u8 data_len;
- u8 seq_no;
-
- nextdata = pdata;
- do {
- data_len = *(nextdata + 1);
- seq_no = *(nextdata + 2);
-
- for (i = 0 ; i < data_len - 2 ; i++) {
- cnt += sprintf((buf + cnt), "%c", nextdata[3 + i]);
-
- if (nextdata[3 + i] == 0x0a && nextdata[4 + i] == 0xff)
- more_data = _TRUE;
- else if (nextdata[3 + i] == 0x0a && nextdata[4 + i] != 0xff)
- more_data = _FALSE;
- }
-
- RTW_INFO("[RTKFW, SEQ=%d]: %s", seq_no, buf);
- data_len += 3;
- total_length += data_len;
-
- if (more_data == _TRUE) {
- _rtw_memset(buf, '\0', 128);
- cnt = 0;
- nextdata = (pdata + total_length);
- }
- } while (more_data == _TRUE);
-}
-#endif /*CONFIG_FW_C2H_DEBUG*/
void update_IOT_info(_adapter *padapter)
{
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
@@ -9449,14 +12137,10 @@ void update_IOT_info(_adapter *padapter)
case HT_IOT_PEER_RALINK:
pmlmeinfo->turboMode_cts2self = 0;
pmlmeinfo->turboMode_rtsen = 1;
- /* disable high power */
- rtw_phydm_func_clr(padapter, ODM_BB_DYNAMIC_TXPWR);
break;
case HT_IOT_PEER_REALTEK:
/* rtw_write16(padapter, 0x4cc, 0xffff); */
/* rtw_write16(padapter, 0x546, 0x01c0); */
- /* disable high power */
- rtw_phydm_func_clr(padapter, ODM_BB_DYNAMIC_TXPWR);
break;
default:
pmlmeinfo->turboMode_cts2self = 0;
@@ -9465,30 +12149,6 @@ void update_IOT_info(_adapter *padapter)
}
}
-#ifdef CONFIG_AUTO_CHNL_SEL_NHM
-void rtw_acs_start(_adapter *padapter, bool bStart)
-{
- if (_TRUE == bStart) {
- ACS_OP acs_op = ACS_INIT;
-
- rtw_hal_set_odm_var(padapter, HAL_ODM_AUTO_CHNL_SEL, &acs_op, _TRUE);
- rtw_set_acs_channel(padapter, 0);
- SET_ACS_STATE(padapter, ACS_ENABLE);
- } else {
- SET_ACS_STATE(padapter, ACS_DISABLE);
-#ifdef DBG_AUTO_CHNL_SEL_NHM
- if (1) {
- u8 best_24g_ch = 0;
- u8 best_5g_ch = 0;
-
- rtw_hal_get_odm_var(padapter, HAL_ODM_AUTO_CHNL_SEL, &(best_24g_ch), &(best_5g_ch));
- RTW_INFO("[ACS-"ADPT_FMT"] Best 2.4G CH:%u\n", ADPT_ARG(padapter), best_24g_ch);
- RTW_INFO("[ACS-"ADPT_FMT"] Best 5G CH:%u\n", ADPT_ARG(padapter), best_5g_ch);
- }
-#endif
- }
-}
-#endif
/* TODO: merge with phydm, see odm_SetCrystalCap() */
void hal_set_crystal_cap(_adapter *adapter, u8 crystal_cap)
@@ -9500,13 +12160,13 @@ void hal_set_crystal_cap(_adapter *adapter, u8 crystal_cap)
case RTL8188E:
case RTL8188F:
/* write 0x24[16:11] = 0x24[22:17] = CrystalCap */
- PHY_SetBBReg(adapter, REG_AFE_XTAL_CTRL, 0x007FF800, (crystal_cap | (crystal_cap << 6)));
+ phy_set_bb_reg(adapter, REG_AFE_XTAL_CTRL, 0x007FF800, (crystal_cap | (crystal_cap << 6)));
break;
#endif
#if defined(CONFIG_RTL8812A)
case RTL8812:
/* write 0x2C[30:25] = 0x2C[24:19] = CrystalCap */
- PHY_SetBBReg(adapter, REG_MAC_PHY_CTRL, 0x7FF80000, (crystal_cap | (crystal_cap << 6)));
+ phy_set_bb_reg(adapter, REG_MAC_PHY_CTRL, 0x7FF80000, (crystal_cap | (crystal_cap << 6)));
break;
#endif
#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || \
@@ -9518,13 +12178,13 @@ void hal_set_crystal_cap(_adapter *adapter, u8 crystal_cap)
case RTL8821:
case RTL8192E:
/* write 0x2C[23:18] = 0x2C[17:12] = CrystalCap */
- PHY_SetBBReg(adapter, REG_MAC_PHY_CTRL, 0x00FFF000, (crystal_cap | (crystal_cap << 6)));
+ phy_set_bb_reg(adapter, REG_MAC_PHY_CTRL, 0x00FFF000, (crystal_cap | (crystal_cap << 6)));
break;
#endif
#if defined(CONFIG_RTL8814A)
case RTL8814A:
/* write 0x2C[26:21] = 0x2C[20:15] = CrystalCap*/
- PHY_SetBBReg(adapter, REG_MAC_PHY_CTRL, 0x07FF8000, (crystal_cap | (crystal_cap << 6)));
+ phy_set_bb_reg(adapter, REG_MAC_PHY_CTRL, 0x07FF8000, (crystal_cap | (crystal_cap << 6)));
break;
#endif
#if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
@@ -9533,8 +12193,8 @@ void hal_set_crystal_cap(_adapter *adapter, u8 crystal_cap)
case RTL8821C:
/* write 0x28[6:1] = 0x24[30:25] = CrystalCap */
crystal_cap = crystal_cap & 0x3F;
- PHY_SetBBReg(adapter, REG_AFE_XTAL_CTRL, 0x7E000000, crystal_cap);
- PHY_SetBBReg(adapter, REG_AFE_PLL_CTRL, 0x7E, crystal_cap);
+ phy_set_bb_reg(adapter, REG_AFE_XTAL_CTRL, 0x7E000000, crystal_cap);
+ phy_set_bb_reg(adapter, REG_AFE_PLL_CTRL, 0x7E, crystal_cap);
break;
#endif
default:
@@ -9652,7 +12312,11 @@ void dump_hal_spec(void *sel, _adapter *adapter)
RTW_PRINT_SEL(sel, "macid_num:%u\n", hal_spec->macid_num);
RTW_PRINT_SEL(sel, "sec_cap:0x%02x\n", hal_spec->sec_cap);
RTW_PRINT_SEL(sel, "sec_cam_ent_num:%u\n", hal_spec->sec_cam_ent_num);
- RTW_PRINT_SEL(sel, "nss_num:%u\n", hal_spec->nss_num);
+ RTW_PRINT_SEL(sel, "rfpath_num_2g:%u\n", hal_spec->rfpath_num_2g);
+ RTW_PRINT_SEL(sel, "rfpath_num_5g:%u\n", hal_spec->rfpath_num_5g);
+ RTW_PRINT_SEL(sel, "max_tx_cnt:%u\n", hal_spec->max_tx_cnt);
+ RTW_PRINT_SEL(sel, "tx_nss_num:%u\n", hal_spec->tx_nss_num);
+ RTW_PRINT_SEL(sel, "rx_nss_num:%u\n", hal_spec->rx_nss_num);
RTW_PRINT_SEL(sel, "band_cap:");
for (i = 0; i < BAND_CAP_BIT_NUM; i++) {
@@ -9681,6 +12345,8 @@ void dump_hal_spec(void *sel, _adapter *adapter)
_RTW_PRINT_SEL(sel, "%s ", _wl_func_str[i]);
}
_RTW_PRINT_SEL(sel, "\n");
+
+ RTW_PRINT_SEL(sel, "pg_txpwr_saddr:0x%X\n", hal_spec->pg_txpwr_saddr);
}
inline bool hal_chk_band_cap(_adapter *adapter, u8 cap)
@@ -9747,9 +12413,9 @@ inline bool hal_is_wireless_mode_support(_adapter *adapter, u8 mode)
/*
* hal_largest_bw - starting from in_bw, get largest bw supported by HAL
* @adapter:
-* @in_bw: starting bw, value of CHANNEL_WIDTH
+* @in_bw: starting bw, value of enum channel_width
*
-* Returns: value of CHANNEL_WIDTH
+* Returns: value of enum channel_width
*/
u8 hal_largest_bw(_adapter *adapter, u8 in_bw)
{
@@ -9790,38 +12456,36 @@ void rtw_hal_correct_tsf(_adapter *padapter, u8 hw_port, u64 tsf)
void ResumeTxBeacon(_adapter *padapter)
{
- PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
-
-
- /* 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value */
- /* which should be read from register to a global variable. */
+#ifdef CONFIG_MI_WITH_MBSSID_CAM
+#else
+ rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2,
+ rtw_read8(padapter, REG_FWHW_TXQ_CTRL + 2) | BIT(6));
- RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+ResumeTxBeacon\n"));
+#ifdef RTW_HALMAC
+ /* Add this for driver using HALMAC because driver doesn't have setup time init by self */
+ /* TBTT setup time */
+ rtw_write8(padapter, REG_TBTT_PROHIBIT, TBTT_PROHIBIT_SETUP_TIME);
+#endif
- pHalData->RegFwHwTxQCtrl |= BIT(6);
- rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2, pHalData->RegFwHwTxQCtrl);
- rtw_write8(padapter, REG_TBTT_PROHIBIT + 1, 0xff);
- pHalData->RegReg542 |= BIT(0);
- rtw_write8(padapter, REG_TBTT_PROHIBIT + 2, pHalData->RegReg542);
+ /* TBTT hold time: 0x540[19:8] */
+ rtw_write8(padapter, REG_TBTT_PROHIBIT + 1, TBTT_PROHIBIT_HOLD_TIME & 0xFF);
+ rtw_write8(padapter, REG_TBTT_PROHIBIT + 2,
+ (rtw_read8(padapter, REG_TBTT_PROHIBIT + 2) & 0xF0) | (TBTT_PROHIBIT_HOLD_TIME >> 8));
+#endif
}
void StopTxBeacon(_adapter *padapter)
{
- PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
-
-
- /* 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value */
- /* which should be read from register to a global variable. */
-
- RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+StopTxBeacon\n"));
-
- pHalData->RegFwHwTxQCtrl &= ~BIT(6);
- rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2, pHalData->RegFwHwTxQCtrl);
- rtw_write8(padapter, REG_TBTT_PROHIBIT + 1, 0x64);
- pHalData->RegReg542 &= ~BIT(0);
- rtw_write8(padapter, REG_TBTT_PROHIBIT + 2, pHalData->RegReg542);
+#ifdef CONFIG_MI_WITH_MBSSID_CAM
+#else
+ rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2,
+ rtw_read8(padapter, REG_FWHW_TXQ_CTRL + 2) & (~BIT6));
- /*CheckFwRsvdPageContent(padapter);*/ /* 2010.06.23. Added by tynli. */
+ /* TBTT hold time: 0x540[19:8] */
+ rtw_write8(padapter, REG_TBTT_PROHIBIT + 1, TBTT_PROHIBIT_HOLD_TIME_STOP_BCN & 0xFF);
+ rtw_write8(padapter, REG_TBTT_PROHIBIT + 2,
+ (rtw_read8(padapter, REG_TBTT_PROHIBIT + 2) & 0xF0) | (TBTT_PROHIBIT_HOLD_TIME_STOP_BCN >> 8));
+#endif
}
#ifdef CONFIG_MI_WITH_MBSSID_CAM /*HW port0 - MBSS*/
@@ -9829,7 +12493,7 @@ void hw_var_set_opmode_mbid(_adapter *Adapter, u8 mode)
{
RTW_INFO("%s()-"ADPT_FMT" mode = %d\n", __func__, ADPT_ARG(Adapter), mode);
- rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR) & (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN)));
+ rtw_hal_rcr_set_chk_bssid(Adapter, MLME_ACTION_NONE);
/* disable Port0 TSF update*/
rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL) | DIS_TSF_UDT);
@@ -9838,7 +12502,7 @@ void hw_var_set_opmode_mbid(_adapter *Adapter, u8 mode)
Set_MSR(Adapter, mode);
if ((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) {
- if (!rtw_mi_check_status(Adapter, MI_AP_MODE))
+ if (!rtw_mi_get_ap_num(Adapter) && !rtw_mi_get_mesh_num(Adapter))
StopTxBeacon(Adapter);
rtw_write8(Adapter, REG_BCN_CTRL, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_ATIM);/*disable atim wnd*/
@@ -9858,9 +12522,9 @@ void hw_var_set_opmode_mbid(_adapter *Adapter, u8 mode)
rtw_write8(Adapter, REG_BCNDMATIM, 0x02); /* 2ms */
/*rtw_write8(Adapter, REG_BCN_MAX_ERR, 0xFF);*/
- rtw_write8(Adapter, REG_ATIMWND, 0x0a); /* 10ms */
+ rtw_write8(Adapter, REG_ATIMWND, 0x0c); /* 12ms */
rtw_write16(Adapter, REG_BCNTCFG, 0x00);
- rtw_write16(Adapter, REG_TBTT_PROHIBIT, 0xff04);
+
rtw_write16(Adapter, REG_TSFTR_SYN_OFFSET, 0x7fff);/* +32767 (~32ms) */
/*reset TSF*/
@@ -9869,6 +12533,9 @@ void hw_var_set_opmode_mbid(_adapter *Adapter, u8 mode)
/*enable BCN0 Function for if1*/
/*don't enable update TSF0 for if1 (due to TSF update when beacon,probe rsp are received)*/
rtw_write8(Adapter, REG_BCN_CTRL, (DIS_TSF_UDT | EN_BCN_FUNCTION | EN_TXBCN_RPT | DIS_BCNQ_SUB));
+ #ifdef CONFIG_BCN_XMIT_PROTECT
+ rtw_write8(Adapter, REG_CCK_CHECK, rtw_read8(Adapter, REG_CCK_CHECK) | BIT_EN_BCN_PKT_REL);
+ #endif
if (IS_HARDWARE_TYPE_8821(Adapter) || IS_HARDWARE_TYPE_8192E(Adapter))/* select BCN on port 0 for DualBeacon*/
rtw_write8(Adapter, REG_CCK_CHECK, rtw_read8(Adapter, REG_CCK_CHECK) & (~BIT_BCN_PORT_SEL));
@@ -9914,3 +12581,248 @@ void rtw_hal_antdiv_rssi_compared(_adapter *padapter, WLAN_BSSID_EX *dst, WLAN_B
}
}
#endif
+
+#ifdef CONFIG_PHY_CAPABILITY_QUERY
+void rtw_dump_phy_cap_by_phydmapi(void *sel, _adapter *adapter)
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
+ struct phy_spec_t *phy_spec = &pHalData->phy_spec;
+
+ RTW_PRINT_SEL(sel, "[PHY SPEC] TRx Capability : 0x%08x\n", phy_spec->trx_cap);
+ RTW_PRINT_SEL(sel, "[PHY SPEC] Tx Stream Num Index : %d\n", (phy_spec->trx_cap >> 24) & 0xFF); /*Tx Stream Num Index [31:24]*/
+ RTW_PRINT_SEL(sel, "[PHY SPEC] Rx Stream Num Index : %d\n", (phy_spec->trx_cap >> 16) & 0xFF); /*Rx Stream Num Index [23:16]*/
+ RTW_PRINT_SEL(sel, "[PHY SPEC] Tx Path Num Index : %d\n", (phy_spec->trx_cap >> 8) & 0xFF);/*Tx Path Num Index [15:8]*/
+ RTW_PRINT_SEL(sel, "[PHY SPEC] Rx Path Num Index : %d\n\n", (phy_spec->trx_cap & 0xFF));/*Rx Path Num Index [7:0]*/
+
+ RTW_PRINT_SEL(sel, "[PHY SPEC] STBC Capability : 0x%08x\n", phy_spec->stbc_cap);
+ RTW_PRINT_SEL(sel, "[PHY SPEC] VHT STBC Tx : %s\n", ((phy_spec->stbc_cap >> 24) & 0xFF) ? "Supported" : "N/A"); /*VHT STBC Tx [31:24]*/
+ /*VHT STBC Rx [23:16]
+ 0 = not support
+ 1 = support for 1 spatial stream
+ 2 = support for 1 or 2 spatial streams
+ 3 = support for 1 or 2 or 3 spatial streams
+ 4 = support for 1 or 2 or 3 or 4 spatial streams*/
+ RTW_PRINT_SEL(sel, "[PHY SPEC] VHT STBC Rx :%d\n", ((phy_spec->stbc_cap >> 16) & 0xFF));
+ RTW_PRINT_SEL(sel, "[PHY SPEC] HT STBC Tx : %s\n", ((phy_spec->stbc_cap >> 8) & 0xFF) ? "Supported" : "N/A"); /*HT STBC Tx [15:8]*/
+ /*HT STBC Rx [7:0]
+ 0 = not support
+ 1 = support for 1 spatial stream
+ 2 = support for 1 or 2 spatial streams
+ 3 = support for 1 or 2 or 3 spatial streams*/
+ RTW_PRINT_SEL(sel, "[PHY SPEC] HT STBC Rx : %d\n\n", (phy_spec->stbc_cap & 0xFF));
+
+ RTW_PRINT_SEL(sel, "[PHY SPEC] LDPC Capability : 0x%08x\n", phy_spec->ldpc_cap);
+ RTW_PRINT_SEL(sel, "[PHY SPEC] VHT LDPC Tx : %s\n", ((phy_spec->ldpc_cap >> 24) & 0xFF) ? "Supported" : "N/A"); /*VHT LDPC Tx [31:24]*/
+ RTW_PRINT_SEL(sel, "[PHY SPEC] VHT LDPC Rx : %s\n", ((phy_spec->ldpc_cap >> 16) & 0xFF) ? "Supported" : "N/A"); /*VHT LDPC Rx [23:16]*/
+ RTW_PRINT_SEL(sel, "[PHY SPEC] HT LDPC Tx : %s\n", ((phy_spec->ldpc_cap >> 8) & 0xFF) ? "Supported" : "N/A"); /*HT LDPC Tx [15:8]*/
+ RTW_PRINT_SEL(sel, "[PHY SPEC] HT LDPC Rx : %s\n\n", (phy_spec->ldpc_cap & 0xFF) ? "Supported" : "N/A"); /*HT LDPC Rx [7:0]*/
+ #ifdef CONFIG_BEAMFORMING
+ RTW_PRINT_SEL(sel, "[PHY SPEC] TxBF Capability : 0x%08x\n", phy_spec->txbf_cap);
+ RTW_PRINT_SEL(sel, "[PHY SPEC] VHT MU Bfer : %s\n", ((phy_spec->txbf_cap >> 28) & 0xF) ? "Supported" : "N/A"); /*VHT MU Bfer [31:28]*/
+ RTW_PRINT_SEL(sel, "[PHY SPEC] VHT MU Bfee : %s\n", ((phy_spec->txbf_cap >> 24) & 0xF) ? "Supported" : "N/A"); /*VHT MU Bfee [27:24]*/
+ RTW_PRINT_SEL(sel, "[PHY SPEC] VHT SU Bfer : %s\n", ((phy_spec->txbf_cap >> 20) & 0xF) ? "Supported" : "N/A"); /*VHT SU Bfer [23:20]*/
+ RTW_PRINT_SEL(sel, "[PHY SPEC] VHT SU Bfee : %s\n", ((phy_spec->txbf_cap >> 16) & 0xF) ? "Supported" : "N/A"); /*VHT SU Bfee [19:16]*/
+ RTW_PRINT_SEL(sel, "[PHY SPEC] HT Bfer : %s\n", ((phy_spec->txbf_cap >> 4) & 0xF) ? "Supported" : "N/A"); /*HT Bfer [7:4]*/
+ RTW_PRINT_SEL(sel, "[PHY SPEC] HT Bfee : %s\n\n", (phy_spec->txbf_cap & 0xF) ? "Supported" : "N/A"); /*HT Bfee [3:0]*/
+
+ RTW_PRINT_SEL(sel, "[PHY SPEC] TxBF parameter : 0x%08x\n", phy_spec->txbf_param);
+ RTW_PRINT_SEL(sel, "[PHY SPEC] VHT Sounding Dim : %d\n", (phy_spec->txbf_param >> 24) & 0xFF); /*VHT Sounding Dim [31:24]*/
+ RTW_PRINT_SEL(sel, "[PHY SPEC] VHT Steering Ant : %d\n", (phy_spec->txbf_param >> 16) & 0xFF); /*VHT Steering Ant [23:16]*/
+ RTW_PRINT_SEL(sel, "[PHY SPEC] HT Sounding Dim : %d\n", (phy_spec->txbf_param >> 8) & 0xFF); /*HT Sounding Dim [15:8]*/
+ RTW_PRINT_SEL(sel, "[PHY SPEC] HT Steering Ant : %d\n", phy_spec->txbf_param & 0xFF); /*HT Steering Ant [7:0]*/
+ #endif
+}
+#else
+void rtw_dump_phy_cap_by_hal(void *sel, _adapter *adapter)
+{
+ u8 phy_cap = _FALSE;
+
+ /* STBC */
+ rtw_hal_get_def_var(adapter, HAL_DEF_TX_STBC, (u8 *)&phy_cap);
+ RTW_PRINT_SEL(sel, "[HAL] STBC Tx : %s\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
+
+ phy_cap = _FALSE;
+ rtw_hal_get_def_var(adapter, HAL_DEF_RX_STBC, (u8 *)&phy_cap);
+ RTW_PRINT_SEL(sel, "[HAL] STBC Rx : %s\n\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
+
+ /* LDPC support */
+ phy_cap = _FALSE;
+ rtw_hal_get_def_var(adapter, HAL_DEF_TX_LDPC, (u8 *)&phy_cap);
+ RTW_PRINT_SEL(sel, "[HAL] LDPC Tx : %s\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
+
+ phy_cap = _FALSE;
+ rtw_hal_get_def_var(adapter, HAL_DEF_RX_LDPC, (u8 *)&phy_cap);
+ RTW_PRINT_SEL(sel, "[HAL] LDPC Rx : %s\n\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
+
+ #ifdef CONFIG_BEAMFORMING
+ phy_cap = _FALSE;
+ rtw_hal_get_def_var(adapter, HAL_DEF_EXPLICIT_BEAMFORMER, (u8 *)&phy_cap);
+ RTW_PRINT_SEL(sel, "[HAL] Beamformer: %s\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
+
+ phy_cap = _FALSE;
+ rtw_hal_get_def_var(adapter, HAL_DEF_EXPLICIT_BEAMFORMEE, (u8 *)&phy_cap);
+ RTW_PRINT_SEL(sel, "[HAL] Beamformee: %s\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
+
+ phy_cap = _FALSE;
+ rtw_hal_get_def_var(adapter, HAL_DEF_VHT_MU_BEAMFORMER, &phy_cap);
+ RTW_PRINT_SEL(sel, "[HAL] VHT MU Beamformer: %s\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
+
+ phy_cap = _FALSE;
+ rtw_hal_get_def_var(adapter, HAL_DEF_VHT_MU_BEAMFORMEE, &phy_cap);
+ RTW_PRINT_SEL(sel, "[HAL] VHT MU Beamformee: %s\n", (_TRUE == phy_cap) ? "Supported" : "N/A");
+ #endif
+}
+#endif
+void rtw_dump_phy_cap(void *sel, _adapter *adapter)
+{
+ RTW_PRINT_SEL(sel, "\n ======== PHY Capability ========\n");
+#ifdef CONFIG_PHY_CAPABILITY_QUERY
+ rtw_dump_phy_cap_by_phydmapi(sel, adapter);
+#else
+ rtw_dump_phy_cap_by_hal(sel, adapter);
+#endif
+}
+
+inline s16 translate_dbm_to_percentage(s16 signal)
+{
+ if ((signal <= -100) || (signal >= 20))
+ return 0;
+ else if (signal >= 0)
+ return 100;
+ else
+ return 100 + signal;
+}
+
+#ifdef CONFIG_SWTIMER_BASED_TXBCN
+#ifdef CONFIG_BCN_RECOVERY
+#define REG_CPU_MGQ_INFO 0x041C
+#define BIT_BCN_POLL BIT(28)
+u8 rtw_ap_bcn_recovery(_adapter *padapter)
+{
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
+
+ if (hal_data->issue_bcn_fail >= 2) {
+ RTW_ERR("%s ISSUE BCN Fail\n", __func__);
+ rtw_write8(padapter, REG_CPU_MGQ_INFO + 3, 0x10);
+ hal_data->issue_bcn_fail = 0;
+ }
+ return _SUCCESS;
+}
+#endif /*CONFIG_BCN_RECOVERY*/
+
+#ifdef CONFIG_BCN_XMIT_PROTECT
+u8 rtw_ap_bcn_queue_empty_check(_adapter *padapter, u32 txbcn_timer_ms)
+{
+ u32 start_time = rtw_get_current_time();
+ u8 bcn_queue_empty = _FALSE;
+
+ do {
+ if (rtw_read16(padapter, REG_TXPKT_EMPTY) & BIT(11)) {
+ bcn_queue_empty = _TRUE;
+ break;
+ }
+ } while (rtw_get_passing_time_ms(start_time) <= (txbcn_timer_ms + 10));
+
+ if (bcn_queue_empty == _FALSE)
+ RTW_ERR("%s BCN queue not empty\n", __func__);
+
+ return bcn_queue_empty;
+}
+#endif /*CONFIG_BCN_XMIT_PROTECT*/
+#endif /*CONFIG_SWTIMER_BASED_TXBCN*/
+
+static void _rf_type_to_ant_path(enum rf_type rf, enum bb_path *tx,
+ enum bb_path *rx)
+{
+ if (tx) {
+ switch (rf) {
+ case RF_1T1R:
+ case RF_1T2R:
+ *tx = BB_PATH_A;
+ break;
+ case RF_2T2R:
+ case RF_2T3R:
+ case RF_2T4R:
+ *tx = BB_PATH_AB;
+ break;
+ case RF_3T3R:
+ case RF_3T4R:
+ *tx = BB_PATH_ABC;
+ break;
+ case RF_4T4R:
+ default:
+ *tx = BB_PATH_ABCD;
+ break;
+ }
+ }
+
+ if (rx) {
+ switch (rf) {
+ case RF_1T1R:
+ *rx = BB_PATH_A;
+ break;
+ case RF_1T2R:
+ case RF_2T2R:
+ *rx = BB_PATH_AB;
+ break;
+ case RF_2T3R:
+ case RF_3T3R:
+ *rx = BB_PATH_ABC;
+ break;
+ case RF_2T4R:
+ case RF_3T4R:
+ case RF_4T4R:
+ default:
+ *rx = BB_PATH_ABCD;
+ break;
+ }
+ }
+}
+
+/**
+ * rtw_hal_get_rf_path() - Get RF path related information
+ * @d: struct dvobj_priv*
+ * @type: RF type, nTnR
+ * @tx: Tx path
+ * @rx: Rx path
+ *
+ * Get RF type, TX path and RX path information.
+ */
+void rtw_hal_get_rf_path(struct dvobj_priv *d, enum rf_type *type,
+ enum bb_path *tx, enum bb_path *rx)
+{
+ struct _ADAPTER *a;
+ u8 val8 = RF_1T1R;
+ enum rf_type rf;
+
+
+ a = dvobj_get_primary_adapter(d);
+
+ rtw_hal_get_hwreg(a, HW_VAR_RF_TYPE, &val8);
+ rf = (enum rf_type)val8;
+ if (type)
+ *type = rf;
+
+ if (tx || rx)
+ _rf_type_to_ant_path(rf, tx, rx);
+}
+
+#ifdef RTW_CHANNEL_SWITCH_OFFLOAD
+void rtw_hal_switch_chnl_and_set_bw_offload(_adapter *adapter, u8 central_ch, u8 pri_ch_idx, u8 bw)
+{
+ u8 h2c[H2C_SINGLE_CHANNELSWITCH_V2_LEN] = {0};
+ PHAL_DATA_TYPE hal;
+ struct submit_ctx *chsw_sctx;
+
+ hal = GET_HAL_DATA(adapter);
+ chsw_sctx = &hal->chsw_sctx;
+
+ SET_H2CCMD_SINGLE_CH_SWITCH_V2_CENTRAL_CH_NUM(h2c, central_ch);
+ SET_H2CCMD_SINGLE_CH_SWITCH_V2_PRIMARY_CH_IDX(h2c, pri_ch_idx);
+ SET_H2CCMD_SINGLE_CH_SWITCH_V2_BW(h2c, bw);
+
+ rtw_sctx_init(chsw_sctx, 10);
+ rtw_hal_fill_h2c_cmd(adapter, H2C_SINGLE_CHANNELSWITCH_V2, H2C_SINGLE_CHANNELSWITCH_V2_LEN, h2c);
+ rtw_sctx_wait(chsw_sctx, __func__);
+}
+#endif /* RTW_CHANNEL_SWITCH_OFFLOAD */
diff --git a/hal/hal_com_c2h.h b/hal/hal_com_c2h.h
index 24599ec..1efabc9 100644
--- a/hal/hal_com_c2h.h
+++ b/hal/hal_com_c2h.h
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,35 +11,70 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#ifndef __COMMON_C2H_H__
#define __COMMON_C2H_H__
+#define C2H_TYPE_REG 0
+#define C2H_TYPE_PKT 1
+
+/*
+* C2H event format:
+* Fields TRIGGER PAYLOAD SEQ PLEN ID
+* BITS [127:120] [119:16] [15:8] [7:4] [3:0]
+*/
+#define C2H_ID(_c2h) LE_BITS_TO_1BYTE(((u8*)(_c2h)), 0, 4)
+#define C2H_PLEN(_c2h) LE_BITS_TO_1BYTE(((u8*)(_c2h)), 4, 4)
+#define C2H_SEQ(_c2h) LE_BITS_TO_1BYTE(((u8*)(_c2h)) + 1, 0, 8)
+#define C2H_PAYLOAD(_c2h) (((u8*)(_c2h)) + 2)
+
+#define SET_C2H_ID(_c2h, _val) SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)), 0, 4, _val)
+#define SET_C2H_PLEN(_c2h, _val) SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)), 4, 4, _val)
+#define SET_C2H_SEQ(_c2h, _val) SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)) + 1 , 0, 8, _val)
+
+/*
+* C2H event format:
+* Fields TRIGGER PLEN PAYLOAD SEQ ID
+* BITS [127:120] [119:112] [111:16] [15:8] [7:0]
+*/
+#define C2H_ID_88XX(_c2h) LE_BITS_TO_1BYTE(((u8*)(_c2h)), 0, 8)
+#define C2H_SEQ_88XX(_c2h) LE_BITS_TO_1BYTE(((u8*)(_c2h)) + 1, 0, 8)
+#define C2H_PAYLOAD_88XX(_c2h) (((u8*)(_c2h)) + 2)
+#define C2H_PLEN_88XX(_c2h) LE_BITS_TO_1BYTE(((u8*)(_c2h)) + 14, 0, 8)
+#define C2H_TRIGGER_88XX(_c2h) LE_BITS_TO_1BYTE(((u8*)(_c2h)) + 15, 0, 8)
+
+#define SET_C2H_ID_88XX(_c2h, _val) SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)), 0, 8, _val)
+#define SET_C2H_SEQ_88XX(_c2h, _val) SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)) + 1, 0, 8, _val)
+#define SET_C2H_PLEN_88XX(_c2h, _val) SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)) + 14, 0, 8, _val)
+
typedef enum _C2H_EVT {
C2H_DBG = 0x00,
C2H_LB = 0x01,
C2H_TXBF = 0x02,
C2H_CCX_TX_RPT = 0x03,
+ C2H_AP_REQ_TXRPT = 0x04,
C2H_FW_SCAN_COMPLETE = 0x7,
C2H_BT_INFO = 0x09,
C2H_BT_MP_INFO = 0x0B,
C2H_RA_RPT = 0x0C,
+ C2H_SPC_STAT = 0x0D,
C2H_RA_PARA_RPT = 0x0E,
C2H_FW_CHNL_SWITCH_COMPLETE = 0x10,
C2H_IQK_FINISH = 0x11,
C2H_MAILBOX_STATUS = 0x15,
C2H_P2P_RPORT = 0x16,
-#ifdef CONFIG_MCC_MODE
C2H_MCC = 0x17,
-#endif /* CONFIG_MCC_MODE */
C2H_MAC_HIDDEN_RPT = 0x19,
+ C2H_MAC_HIDDEN_RPT_2 = 0x1A,
C2H_BCN_EARLY_RPT = 0x1E,
- C2H_BT_SCOREBOARD_STATUS = 0x20,
+ C2H_DEFEATURE_DBG = 0x22,
+ C2H_CUSTOMER_STR_RPT = 0x24,
+ C2H_CUSTOMER_STR_RPT_2 = 0x25,
+ C2H_WLAN_INFO = 0x27,
+#ifdef RTW_PER_CMD_SUPPORT_FW
+ C2H_PER_RATE_RPT = 0x2c,
+#endif
+ C2H_DEFEATURE_RSVD = 0xFD,
C2H_EXTEND = 0xff,
} C2H_EVT;
@@ -47,8 +82,42 @@ typedef enum _EXTEND_C2H_EVT {
EXTEND_C2H_DBG_PRINT = 0
} EXTEND_C2H_EVT;
+#define C2H_REG_LEN 16
+
+/* C2H_IQK_FINISH, 0x11 */
+#define IQK_OFFLOAD_LEN 1
+void c2h_iqk_offload(_adapter *adapter, u8 *data, u8 len);
+int c2h_iqk_offload_wait(_adapter *adapter, u32 timeout_ms);
+#define rtl8812_iqk_wait c2h_iqk_offload_wait /* TODO: remove this after phydm call c2h_iqk_offload_wait instead */
+
+#ifdef CONFIG_RTW_MAC_HIDDEN_RPT
+/* C2H_MAC_HIDDEN_RPT, 0x19 */
#define MAC_HIDDEN_RPT_LEN 8
int c2h_mac_hidden_rpt_hdl(_adapter *adapter, u8 *data, u8 len);
+
+/* C2H_MAC_HIDDEN_RPT_2, 0x1A */
+#define MAC_HIDDEN_RPT_2_LEN 5
+int c2h_mac_hidden_rpt_2_hdl(_adapter *adapter, u8 *data, u8 len);
int hal_read_mac_hidden_rpt(_adapter *adapter);
+#endif /* CONFIG_RTW_MAC_HIDDEN_RPT */
+
+/* C2H_DEFEATURE_DBG, 0x22 */
+#define DEFEATURE_DBG_LEN 1
+int c2h_defeature_dbg_hdl(_adapter *adapter, u8 *data, u8 len);
+
+#ifdef CONFIG_RTW_CUSTOMER_STR
+/* C2H_CUSTOMER_STR_RPT, 0x24 */
+#define CUSTOMER_STR_RPT_LEN 8
+int c2h_customer_str_rpt_hdl(_adapter *adapter, u8 *data, u8 len);
+
+/* C2H_CUSTOMER_STR_RPT_2, 0x25 */
+#define CUSTOMER_STR_RPT_2_LEN 8
+int c2h_customer_str_rpt_2_hdl(_adapter *adapter, u8 *data, u8 len);
+#endif /* CONFIG_RTW_CUSTOMER_STR */
+
+#ifdef RTW_PER_CMD_SUPPORT_FW
+/* C2H_PER_RATE_RPT, 0x2c */
+int c2h_per_rate_rpt_hdl(_adapter *adapter, u8 *data, u8 len);
+#endif
#endif /* __COMMON_C2H_H__ */
diff --git a/hal/hal_com_phycfg.c b/hal/hal_com_phycfg.c
index f912e39..04df339 100644
--- a/hal/hal_com_phycfg.c
+++ b/hal/hal_com_phycfg.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,371 +11,1581 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#define _HAL_COM_PHYCFG_C_
#include
#include
-/*
-* rtw_regsty_get_target_tx_power -
-*
-* Return dBm or -1 for undefined
-*/
-s8 rtw_regsty_get_target_tx_power(
- IN PADAPTER Adapter,
- IN u8 Band,
- IN u8 RfPath,
- IN RATE_SECTION RateSection
-) {
- struct registry_priv *regsty = adapter_to_regsty(Adapter);
- s8 value = 0;
+#define PG_TXPWR_1PATH_BYTE_NUM_2G 18
+#define PG_TXPWR_BASE_BYTE_NUM_2G 11
- if (RfPath > RF_PATH_D) {
- RTW_PRINT("%s invalid RfPath:%d\n", __func__, RfPath);
- return -1;
- }
+#define PG_TXPWR_1PATH_BYTE_NUM_5G 24
+#define PG_TXPWR_BASE_BYTE_NUM_5G 14
- if (Band != BAND_ON_2_4G
-#ifdef CONFIG_NL80211_BAND_5GHZ
- && Band != BAND_ON_5G
-#endif
- ) {
- RTW_PRINT("%s invalid Band:%d\n", __func__, Band);
- return -1;
- }
+#define PG_TXPWR_MSB_DIFF_S4BIT(_pg_v) (((_pg_v) & 0xf0) >> 4)
+#define PG_TXPWR_LSB_DIFF_S4BIT(_pg_v) ((_pg_v) & 0x0f)
+#define PG_TXPWR_MSB_DIFF_TO_S8BIT(_pg_v) ((PG_TXPWR_MSB_DIFF_S4BIT(_pg_v) & BIT3) ? (PG_TXPWR_MSB_DIFF_S4BIT(_pg_v) | 0xF0) : PG_TXPWR_MSB_DIFF_S4BIT(_pg_v))
+#define PG_TXPWR_LSB_DIFF_TO_S8BIT(_pg_v) ((PG_TXPWR_LSB_DIFF_S4BIT(_pg_v) & BIT3) ? (PG_TXPWR_LSB_DIFF_S4BIT(_pg_v) | 0xF0) : PG_TXPWR_LSB_DIFF_S4BIT(_pg_v))
+#define IS_PG_TXPWR_BASE_INVALID(_base) ((_base) > 63)
+#define IS_PG_TXPWR_DIFF_INVALID(_diff) ((_diff) > 7 || (_diff) < -8)
+#define PG_TXPWR_INVALID_BASE 255
+#define PG_TXPWR_INVALID_DIFF 8
- if (RateSection >= RATE_SECTION_NUM
-#ifdef CONFIG_NL80211_BAND_5GHZ
- || (Band == BAND_ON_5G && RateSection == CCK)
+#if !IS_PG_TXPWR_BASE_INVALID(PG_TXPWR_INVALID_BASE)
+#error "PG_TXPWR_BASE definition has problem"
#endif
- ) {
- RTW_PRINT("%s invalid RateSection:%d in %sG, RfPath:%d\n", __func__
- , RateSection, (Band == BAND_ON_2_4G) ? "2.4" : "5", RfPath);
- return -1;
- }
- if (Band == BAND_ON_2_4G)
- value = regsty->target_tx_pwr_2g[RfPath][RateSection];
-#ifdef CONFIG_NL80211_BAND_5GHZ
- else /* BAND_ON_5G */
- value = regsty->target_tx_pwr_5g[RfPath][RateSection - 1];
+#if !IS_PG_TXPWR_DIFF_INVALID(PG_TXPWR_INVALID_DIFF)
+#error "PG_TXPWR_DIFF definition has problem"
#endif
- return value;
-}
+#define PG_TXPWR_SRC_PG_DATA 0
+#define PG_TXPWR_SRC_IC_DEF 1
+#define PG_TXPWR_SRC_DEF 2
+#define PG_TXPWR_SRC_NUM 3
-bool rtw_regsty_chk_target_tx_power_valid(_adapter *adapter) {
- struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
- HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
- int path, tx_num, band, rs;
- s8 target;
+const char *const _pg_txpwr_src_str[] = {
+ "PG_DATA",
+ "IC_DEF",
+ "DEF",
+ "UNKNOWN"
+};
- for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
- if (!hal_is_band_support(adapter, band))
- continue;
+#define pg_txpwr_src_str(src) (((src) >= PG_TXPWR_SRC_NUM) ? _pg_txpwr_src_str[PG_TXPWR_SRC_NUM] : _pg_txpwr_src_str[(src)])
- for (path = 0; path < RF_PATH_MAX; path++) {
- if (path >= hal_data->NumTotalRFPath)
- break;
+#ifndef DBG_PG_TXPWR_READ
+#define DBG_PG_TXPWR_READ 0
+#endif
- for (rs = 0; rs < RATE_SECTION_NUM; rs++) {
- tx_num = rate_section_to_tx_num(rs);
- if (tx_num >= hal_spec->nss_num)
- continue;
+#if DBG_PG_TXPWR_READ
+static void dump_pg_txpwr_info_2g(void *sel, TxPowerInfo24G *txpwr_info, u8 rfpath_num, u8 max_tx_cnt)
+{
+ int path, group, tx_idx;
+
+ RTW_PRINT_SEL(sel, "2.4G\n");
+ RTW_PRINT_SEL(sel, "CCK-1T base:\n");
+ RTW_PRINT_SEL(sel, "%4s ", "");
+ for (group = 0; group < MAX_CHNL_GROUP_24G; group++)
+ _RTW_PRINT_SEL(sel, "G%02d ", group);
+ _RTW_PRINT_SEL(sel, "\n");
+ for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+ RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+ for (group = 0; group < MAX_CHNL_GROUP_24G; group++)
+ _RTW_PRINT_SEL(sel, "%3u ", txpwr_info->IndexCCK_Base[path][group]);
+ _RTW_PRINT_SEL(sel, "\n");
+ }
+ RTW_PRINT_SEL(sel, "\n");
+
+ RTW_PRINT_SEL(sel, "CCK diff:\n");
+ RTW_PRINT_SEL(sel, "%4s ", "");
+ for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
+ _RTW_PRINT_SEL(sel, "%dT ", path + 1);
+ _RTW_PRINT_SEL(sel, "\n");
+ for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+ RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+ for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+ _RTW_PRINT_SEL(sel, "%2d ", txpwr_info->CCK_Diff[path][tx_idx]);
+ _RTW_PRINT_SEL(sel, "\n");
+ }
+ RTW_PRINT_SEL(sel, "\n");
+
+ RTW_PRINT_SEL(sel, "BW40-1S base:\n");
+ RTW_PRINT_SEL(sel, "%4s ", "");
+ for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++)
+ _RTW_PRINT_SEL(sel, "G%02d ", group);
+ _RTW_PRINT_SEL(sel, "\n");
+ for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+ RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+ for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++)
+ _RTW_PRINT_SEL(sel, "%3u ", txpwr_info->IndexBW40_Base[path][group]);
+ _RTW_PRINT_SEL(sel, "\n");
+ }
+ RTW_PRINT_SEL(sel, "\n");
+
+ RTW_PRINT_SEL(sel, "OFDM diff:\n");
+ RTW_PRINT_SEL(sel, "%4s ", "");
+ for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
+ _RTW_PRINT_SEL(sel, "%dT ", path + 1);
+ _RTW_PRINT_SEL(sel, "\n");
+ for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+ RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+ for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+ _RTW_PRINT_SEL(sel, "%2d ", txpwr_info->OFDM_Diff[path][tx_idx]);
+ _RTW_PRINT_SEL(sel, "\n");
+ }
+ RTW_PRINT_SEL(sel, "\n");
+
+ RTW_PRINT_SEL(sel, "BW20 diff:\n");
+ RTW_PRINT_SEL(sel, "%4s ", "");
+ for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
+ _RTW_PRINT_SEL(sel, "%dS ", path + 1);
+ _RTW_PRINT_SEL(sel, "\n");
+ for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+ RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+ for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+ _RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW20_Diff[path][tx_idx]);
+ _RTW_PRINT_SEL(sel, "\n");
+ }
+ RTW_PRINT_SEL(sel, "\n");
+
+ RTW_PRINT_SEL(sel, "BW40 diff:\n");
+ RTW_PRINT_SEL(sel, "%4s ", "");
+ for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
+ _RTW_PRINT_SEL(sel, "%dS ", path + 1);
+ _RTW_PRINT_SEL(sel, "\n");
+ for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+ RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+ for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+ _RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW40_Diff[path][tx_idx]);
+ _RTW_PRINT_SEL(sel, "\n");
+ }
+ RTW_PRINT_SEL(sel, "\n");
+}
- if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
- continue;
+static void dump_pg_txpwr_info_5g(void *sel, TxPowerInfo5G *txpwr_info, u8 rfpath_num, u8 max_tx_cnt)
+{
+ int path, group, tx_idx;
+
+ RTW_PRINT_SEL(sel, "5G\n");
+ RTW_PRINT_SEL(sel, "BW40-1S base:\n");
+ RTW_PRINT_SEL(sel, "%4s ", "");
+ for (group = 0; group < MAX_CHNL_GROUP_5G; group++)
+ _RTW_PRINT_SEL(sel, "G%02d ", group);
+ _RTW_PRINT_SEL(sel, "\n");
+ for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+ RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+ for (group = 0; group < MAX_CHNL_GROUP_5G; group++)
+ _RTW_PRINT_SEL(sel, "%3u ", txpwr_info->IndexBW40_Base[path][group]);
+ _RTW_PRINT_SEL(sel, "\n");
+ }
+ RTW_PRINT_SEL(sel, "\n");
+
+ RTW_PRINT_SEL(sel, "OFDM diff:\n");
+ RTW_PRINT_SEL(sel, "%4s ", "");
+ for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
+ _RTW_PRINT_SEL(sel, "%dT ", path + 1);
+ _RTW_PRINT_SEL(sel, "\n");
+ for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+ RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+ for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+ _RTW_PRINT_SEL(sel, "%2d ", txpwr_info->OFDM_Diff[path][tx_idx]);
+ _RTW_PRINT_SEL(sel, "\n");
+ }
+ RTW_PRINT_SEL(sel, "\n");
+
+ RTW_PRINT_SEL(sel, "BW20 diff:\n");
+ RTW_PRINT_SEL(sel, "%4s ", "");
+ for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
+ _RTW_PRINT_SEL(sel, "%dS ", path + 1);
+ _RTW_PRINT_SEL(sel, "\n");
+ for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+ RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+ for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+ _RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW20_Diff[path][tx_idx]);
+ _RTW_PRINT_SEL(sel, "\n");
+ }
+ RTW_PRINT_SEL(sel, "\n");
+
+ RTW_PRINT_SEL(sel, "BW40 diff:\n");
+ RTW_PRINT_SEL(sel, "%4s ", "");
+ for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
+ _RTW_PRINT_SEL(sel, "%dS ", path + 1);
+ _RTW_PRINT_SEL(sel, "\n");
+ for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+ RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+ for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+ _RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW40_Diff[path][tx_idx]);
+ _RTW_PRINT_SEL(sel, "\n");
+ }
+ RTW_PRINT_SEL(sel, "\n");
+
+ RTW_PRINT_SEL(sel, "BW80 diff:\n");
+ RTW_PRINT_SEL(sel, "%4s ", "");
+ for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
+ _RTW_PRINT_SEL(sel, "%dS ", path + 1);
+ _RTW_PRINT_SEL(sel, "\n");
+ for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+ RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+ for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+ _RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW80_Diff[path][tx_idx]);
+ _RTW_PRINT_SEL(sel, "\n");
+ }
+ RTW_PRINT_SEL(sel, "\n");
+
+ RTW_PRINT_SEL(sel, "BW160 diff:\n");
+ RTW_PRINT_SEL(sel, "%4s ", "");
+ for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++)
+ _RTW_PRINT_SEL(sel, "%dS ", path + 1);
+ _RTW_PRINT_SEL(sel, "\n");
+ for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+ RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+ for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+ _RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW160_Diff[path][tx_idx]);
+ _RTW_PRINT_SEL(sel, "\n");
+ }
+ RTW_PRINT_SEL(sel, "\n");
+}
+#endif /* DBG_PG_TXPWR_READ */
+
+const struct map_t pg_txpwr_def_info =
+ MAP_ENT(0xB8, 1, 0xFF
+ , MAPSEG_ARRAY_ENT(0x10, 168,
+ 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE, 0xEE, 0xEE,
+ 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
+ 0x04, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D,
+ 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A,
+ 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x04, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
+ 0xEE, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24,
+ 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
+ 0x2A, 0x2A, 0x2A, 0x2A, 0x04, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D,
+ 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
+ 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x04, 0xEE,
+ 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE)
+ );
- if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter))
- continue;
+#ifdef CONFIG_RTL8188E
+static const struct map_t rtl8188e_pg_txpwr_def_info =
+ MAP_ENT(0xB8, 1, 0xFF
+ , MAPSEG_ARRAY_ENT(0x10, 12,
+ 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24)
+ );
+#endif
- target = rtw_regsty_get_target_tx_power(adapter, band, path, rs);
- if (target == -1)
- return _FALSE;
- }
- }
- }
+#ifdef CONFIG_RTL8188F
+static const struct map_t rtl8188f_pg_txpwr_def_info =
+ MAP_ENT(0xB8, 1, 0xFF
+ , MAPSEG_ARRAY_ENT(0x10, 12,
+ 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x27, 0x27, 0x27, 0x27, 0x27, 0x24)
+ );
+#endif
- return _TRUE;
-}
+#ifdef CONFIG_RTL8723B
+static const struct map_t rtl8723b_pg_txpwr_def_info =
+ MAP_ENT(0xB8, 2, 0xFF
+ , MAPSEG_ARRAY_ENT(0x10, 12,
+ 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0xE0)
+ , MAPSEG_ARRAY_ENT(0x3A, 12,
+ 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0xE0)
+ );
+#endif
-/*
-* PHY_GetTxPowerByRateBase -
-*
-* Return 2 times of dBm
-*/
-u8
-PHY_GetTxPowerByRateBase(
- IN PADAPTER Adapter,
- IN u8 Band,
- IN u8 RfPath,
- IN u8 TxNum,
- IN RATE_SECTION RateSection
-) {
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
- u8 value = 0;
+#ifdef CONFIG_RTL8703B
+static const struct map_t rtl8703b_pg_txpwr_def_info =
+ MAP_ENT(0xB8, 1, 0xFF
+ , MAPSEG_ARRAY_ENT(0x10, 12,
+ 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02)
+ );
+#endif
- if (RfPath > RF_PATH_D) {
- RTW_PRINT("%s invalid RfPath:%d\n", __func__, RfPath);
- return 0;
- }
+#ifdef CONFIG_RTL8723D
+static const struct map_t rtl8723d_pg_txpwr_def_info =
+ MAP_ENT(0xB8, 2, 0xFF
+ , MAPSEG_ARRAY_ENT(0x10, 12,
+ 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02)
+ , MAPSEG_ARRAY_ENT(0x3A, 12,
+ 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x21, 0x21, 0x21, 0x21, 0x21, 0x02)
+ );
+#endif
- if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {
- RTW_PRINT("%s invalid Band:%d\n", __func__, Band);
- return 0;
- }
+#ifdef CONFIG_RTL8192E
+static const struct map_t rtl8192e_pg_txpwr_def_info =
+ MAP_ENT(0xB8, 2, 0xFF
+ , MAPSEG_ARRAY_ENT(0x10, 14,
+ 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE)
+ , MAPSEG_ARRAY_ENT(0x3A, 14,
+ 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE)
+ );
+#endif
- if (RateSection >= RATE_SECTION_NUM
- || (Band == BAND_ON_5G && RateSection == CCK)
- ) {
- RTW_PRINT("%s invalid RateSection:%d in %sG, RfPath:%d, TxNum:%d\n", __func__
- , RateSection, (Band == BAND_ON_2_4G) ? "2.4" : "5", RfPath, TxNum);
- return 0;
- }
+#ifdef CONFIG_RTL8821A
+static const struct map_t rtl8821a_pg_txpwr_def_info =
+ MAP_ENT(0xB8, 1, 0xFF
+ , MAPSEG_ARRAY_ENT(0x10, 39,
+ 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
+ 0x04, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00)
+ );
+#endif
- if (Band == BAND_ON_2_4G)
- value = pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][RateSection];
- else /* BAND_ON_5G */
- value = pHalData->TxPwrByRateBase5G[RfPath][TxNum][RateSection - 1];
+#ifdef CONFIG_RTL8821C
+static const struct map_t rtl8821c_pg_txpwr_def_info =
+ MAP_ENT(0xB8, 1, 0xFF
+ , MAPSEG_ARRAY_ENT(0x10, 54,
+ 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28,
+ 0x02, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xEC, 0xFF, 0xFF, 0xFF, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D,
+ 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02)
+ );
+#endif
- return value;
-}
+#ifdef CONFIG_RTL8812A
+static const struct map_t rtl8812a_pg_txpwr_def_info =
+ MAP_ENT(0xB8, 1, 0xFF
+ , MAPSEG_ARRAY_ENT(0x10, 82,
+ 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
+ 0x02, 0xEE, 0xFF, 0xFF, 0xEE, 0xFF, 0x00, 0xEE, 0xFF, 0xFF, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D,
+ 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xFF, 0xFF, 0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A,
+ 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE, 0xFF, 0xFF, 0xEE, 0xFF,
+ 0x00, 0xEE)
+ );
+#endif
-VOID
-phy_SetTxPowerByRateBase(
- IN PADAPTER Adapter,
- IN u8 Band,
- IN u8 RfPath,
- IN RATE_SECTION RateSection,
- IN u8 TxNum,
- IN u8 Value
-) {
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+#ifdef CONFIG_RTL8822B
+static const struct map_t rtl8822b_pg_txpwr_def_info =
+ MAP_ENT(0xB8, 1, 0xFF
+ , MAPSEG_ARRAY_ENT(0x10, 82,
+ 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
+ 0x02, 0xEE, 0xFF, 0xFF, 0xEE, 0xFF, 0xEC, 0xEC, 0xFF, 0xFF, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D,
+ 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xFF, 0xFF, 0xFF, 0xFF, 0x2A, 0x2A, 0x2A, 0x2A,
+ 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE, 0xFF, 0xFF, 0xEE, 0xFF,
+ 0xEC, 0xEC)
+ );
+#endif
- if (RfPath > RF_PATH_D) {
- RTW_PRINT("%s invalid RfPath:%d\n", __func__, RfPath);
- return;
- }
+#ifdef CONFIG_RTL8814A
+static const struct map_t rtl8814a_pg_txpwr_def_info =
+ MAP_ENT(0xB8, 1, 0xFF
+ , MAPSEG_ARRAY_ENT(0x10, 168,
+ 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xEE, 0xEE,
+ 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
+ 0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x00, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D,
+ 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A,
+ 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
+ 0x00, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02,
+ 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A,
+ 0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x00, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D,
+ 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
+ 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x02, 0xEE,
+ 0xEE, 0xEE, 0xEE, 0xEE, 0x00, 0xEE, 0xEE, 0xEE)
+ );
+#endif
- if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {
- RTW_PRINT("%s invalid Band:%d\n", __func__, Band);
- return;
+const struct map_t *hal_pg_txpwr_def_info(_adapter *adapter)
+{
+ u8 interface_type = 0;
+ const struct map_t *map = NULL;
+
+ interface_type = rtw_get_intf_type(adapter);
+
+ switch (rtw_get_chip_type(adapter)) {
+#ifdef CONFIG_RTL8723B
+ case RTL8723B:
+ map = &rtl8723b_pg_txpwr_def_info;
+ break;
+#endif
+#ifdef CONFIG_RTL8703B
+ case RTL8703B:
+ map = &rtl8703b_pg_txpwr_def_info;
+ break;
+#endif
+#ifdef CONFIG_RTL8723D
+ case RTL8723D:
+ map = &rtl8723d_pg_txpwr_def_info;
+ break;
+#endif
+#ifdef CONFIG_RTL8188E
+ case RTL8188E:
+ map = &rtl8188e_pg_txpwr_def_info;
+ break;
+#endif
+#ifdef CONFIG_RTL8188F
+ case RTL8188F:
+ map = &rtl8188f_pg_txpwr_def_info;
+ break;
+#endif
+#ifdef CONFIG_RTL8812A
+ case RTL8812:
+ map = &rtl8812a_pg_txpwr_def_info;
+ break;
+#endif
+#ifdef CONFIG_RTL8821A
+ case RTL8821:
+ map = &rtl8821a_pg_txpwr_def_info;
+ break;
+#endif
+#ifdef CONFIG_RTL8192E
+ case RTL8192E:
+ map = &rtl8192e_pg_txpwr_def_info;
+ break;
+#endif
+#ifdef CONFIG_RTL8814A
+ case RTL8814A:
+ map = &rtl8814a_pg_txpwr_def_info;
+ break;
+#endif
+#ifdef CONFIG_RTL8822B
+ case RTL8822B:
+ map = &rtl8822b_pg_txpwr_def_info;
+ break;
+#endif
+#ifdef CONFIG_RTL8821C
+ case RTL8821C:
+ map = &rtl8821c_pg_txpwr_def_info;
+ break;
+#endif
}
- if (RateSection >= RATE_SECTION_NUM
- || (Band == BAND_ON_5G && RateSection == CCK)
- ) {
- RTW_PRINT("%s invalid RateSection:%d in %sG, RfPath:%d, TxNum:%d\n", __func__
- , RateSection, (Band == BAND_ON_2_4G) ? "2.4" : "5", RfPath, TxNum);
- return;
+ if (map == NULL) {
+ RTW_ERR("%s: unknown chip_type:%u\n"
+ , __func__, rtw_get_chip_type(adapter));
+ rtw_warn_on(1);
}
- if (Band == BAND_ON_2_4G)
- pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][RateSection] = Value;
- else /* BAND_ON_5G */
- pHalData->TxPwrByRateBase5G[RfPath][TxNum][RateSection - 1] = Value;
+ return map;
}
-/*
-* phy_get_target_tx_power -
-*
-* Return 2 times of dBm
-*/
-u8 phy_get_target_tx_power(
- IN PADAPTER Adapter,
- IN u8 Band,
- IN u8 RfPath,
- IN RATE_SECTION RateSection
-) {
- struct registry_priv *regsty = adapter_to_regsty(Adapter);
- s16 target_power;
+static u8 hal_chk_pg_txpwr_info_2g(_adapter *adapter, TxPowerInfo24G *pwr_info)
+{
+ struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+ u8 path, group, tx_idx;
- if (phy_is_tx_power_by_rate_needed(Adapter) == _FALSE && regsty->target_tx_pwr_valid == _TRUE)
- target_power = 2 * rtw_regsty_get_target_tx_power(Adapter, Band, RfPath, RateSection);
- else
- target_power = PHY_GetTxPowerByRateBase(Adapter, Band, RfPath, rate_section_to_tx_num(RateSection), RateSection);
+ if (pwr_info == NULL || !hal_chk_band_cap(adapter, BAND_CAP_2G))
+ return _SUCCESS;
+
+ for (path = 0; path < MAX_RF_PATH; path++) {
+ if (!HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path))
+ continue;
+ for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
+ if (IS_PG_TXPWR_BASE_INVALID(pwr_info->IndexCCK_Base[path][group])
+ || IS_PG_TXPWR_BASE_INVALID(pwr_info->IndexBW40_Base[path][group]))
+ return _FAIL;
+ }
+ for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
+ if (!HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx))
+ continue;
+ if (IS_PG_TXPWR_DIFF_INVALID(pwr_info->CCK_Diff[path][tx_idx])
+ || IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx])
+ || IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])
+ || IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW40_Diff[path][tx_idx]))
+ return _FAIL;
+ }
+ }
- return target_power;
+ return _SUCCESS;
}
-#ifdef TX_POWER_BY_RATE_OLD
-VOID
-phy_StoreTxPowerByRateBaseOld(
- IN PADAPTER pAdapter
-) {
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
- u16 rawValue = 0;
- u8 base = 0;
- u8 path = 0;
+static u8 hal_chk_pg_txpwr_info_5g(_adapter *adapter, TxPowerInfo5G *pwr_info)
+{
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+ struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+ u8 path, group, tx_idx;
- rawValue = (u16)(pHalData->MCSTxPowerLevelOriginalOffset[0][7] >> 8) & 0xFF;
- base = (rawValue >> 4) * 10 + (rawValue & 0xF);
- phy_SetTxPowerByRateBase(pAdapter, BAND_ON_2_4G, ODM_RF_PATH_A, CCK, RF_1TX, base);
+ if (pwr_info == NULL || !hal_chk_band_cap(adapter, BAND_CAP_5G))
+ return _SUCCESS;
- rawValue = (u16)(pHalData->MCSTxPowerLevelOriginalOffset[0][1] >> 24) & 0xFF;
- base = (rawValue >> 4) * 10 + (rawValue & 0xF);
- phy_SetTxPowerByRateBase(pAdapter, BAND_ON_2_4G, ODM_RF_PATH_A, OFDM, RF_1TX, base);
+ for (path = 0; path < MAX_RF_PATH; path++) {
+ if (!HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path))
+ continue;
+ for (group = 0; group < MAX_CHNL_GROUP_5G; group++)
+ if (IS_PG_TXPWR_BASE_INVALID(pwr_info->IndexBW40_Base[path][group]))
+ return _FAIL;
+ for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
+ if (!HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx))
+ continue;
+ if (IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx])
+ || IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])
+ || IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW40_Diff[path][tx_idx])
+ || IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW80_Diff[path][tx_idx])
+ || IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW160_Diff[path][tx_idx]))
+ return _FAIL;
+ }
+ }
+#endif /* CONFIG_IEEE80211_BAND_5GHZ */
+ return _SUCCESS;
+}
- rawValue = (u16)(pHalData->MCSTxPowerLevelOriginalOffset[0][3] >> 24) & 0xFF;
- base = (rawValue >> 4) * 10 + (rawValue & 0xF);
- phy_SetTxPowerByRateBase(pAdapter, BAND_ON_2_4G, ODM_RF_PATH_A, HT_MCS0_MCS7, RF_1TX, base);
+static inline void hal_init_pg_txpwr_info_2g(_adapter *adapter, TxPowerInfo24G *pwr_info)
+{
+ struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+ u8 path, group, tx_idx;
- rawValue = (u16)(pHalData->MCSTxPowerLevelOriginalOffset[0][5] >> 24) & 0xFF;
- base = (rawValue >> 4) * 10 + (rawValue & 0xF);
- phy_SetTxPowerByRateBase(pAdapter, BAND_ON_2_4G, ODM_RF_PATH_A, HT_MCS8_MCS15, RF_2TX, base);
+ if (pwr_info == NULL)
+ return;
- rawValue = (u16)(pHalData->MCSTxPowerLevelOriginalOffset[0][7] & 0xFF);
- base = (rawValue >> 4) * 10 + (rawValue & 0xF);
- phy_SetTxPowerByRateBase(pAdapter, BAND_ON_2_4G, ODM_RF_PATH_B, CCK, RF_1TX, base);
+ _rtw_memset(pwr_info, 0, sizeof(TxPowerInfo24G));
- rawValue = (u16)(pHalData->MCSTxPowerLevelOriginalOffset[0][9] >> 24) & 0xFF;
- base = (rawValue >> 4) * 10 + (rawValue & 0xF);
- phy_SetTxPowerByRateBase(pAdapter, BAND_ON_2_4G, ODM_RF_PATH_B, OFDM, RF_1TX, base);
+ /* init with invalid value */
+ for (path = 0; path < MAX_RF_PATH; path++) {
+ for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
+ pwr_info->IndexCCK_Base[path][group] = PG_TXPWR_INVALID_BASE;
+ pwr_info->IndexBW40_Base[path][group] = PG_TXPWR_INVALID_BASE;
+ }
+ for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
+ pwr_info->CCK_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
+ pwr_info->OFDM_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
+ pwr_info->BW20_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
+ pwr_info->BW40_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
+ }
+ }
- rawValue = (u16)(pHalData->MCSTxPowerLevelOriginalOffset[0][11] >> 24) & 0xFF;
- base = (rawValue >> 4) * 10 + (rawValue & 0xF);
- phy_SetTxPowerByRateBase(pAdapter, BAND_ON_2_4G, ODM_RF_PATH_B, HT_MCS0_MCS7, RF_1TX, base);
+ /* init for dummy base and diff */
+ for (path = 0; path < MAX_RF_PATH; path++) {
+ if (!HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path))
+ break;
+ /* 2.4G BW40 base has 1 less group than CCK base*/
+ pwr_info->IndexBW40_Base[path][MAX_CHNL_GROUP_24G - 1] = 0;
- rawValue = (u16)(pHalData->MCSTxPowerLevelOriginalOffset[0][13] >> 24) & 0xFF;
- base = (rawValue >> 4) * 10 + (rawValue & 0xF);
- phy_SetTxPowerByRateBase(pAdapter, BAND_ON_2_4G, ODM_RF_PATH_B, HT_MCS8_MCS15, RF_2TX, base);
+ /* dummy diff */
+ pwr_info->CCK_Diff[path][0] = 0; /* 2.4G CCK-1TX */
+ pwr_info->BW40_Diff[path][0] = 0; /* 2.4G BW40-1S */
+ }
}
-#endif /* TX_POWER_BY_RATE_OLD */
-VOID
-phy_StoreTxPowerByRateBase(
- IN PADAPTER pAdapter
-) {
- struct hal_spec_t *hal_spec = GET_HAL_SPEC(pAdapter);
+static inline void hal_init_pg_txpwr_info_5g(_adapter *adapter, TxPowerInfo5G *pwr_info)
+{
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+ struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+ u8 path, group, tx_idx;
- u8 rate_sec_base[RATE_SECTION_NUM] = {
- MGN_11M,
- MGN_54M,
- MGN_MCS7,
- MGN_MCS15,
- MGN_MCS23,
- MGN_MCS31,
- MGN_VHT1SS_MCS7,
- MGN_VHT2SS_MCS7,
- MGN_VHT3SS_MCS7,
- MGN_VHT4SS_MCS7,
- };
+ if (pwr_info == NULL)
+ return;
- u8 band, path, rs, tx_num, base, index;
+ _rtw_memset(pwr_info, 0, sizeof(TxPowerInfo5G));
+
+ /* init with invalid value */
+ for (path = 0; path < MAX_RF_PATH; path++) {
+ for (group = 0; group < MAX_CHNL_GROUP_5G; group++)
+ pwr_info->IndexBW40_Base[path][group] = PG_TXPWR_INVALID_BASE;
+ for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
+ pwr_info->OFDM_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
+ pwr_info->BW20_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
+ pwr_info->BW40_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
+ pwr_info->BW80_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
+ pwr_info->BW160_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF;
+ }
+ }
- for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
+ for (path = 0; path < MAX_RF_PATH; path++) {
+ if (!HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path))
+ break;
+ /* dummy diff */
+ pwr_info->BW40_Diff[path][0] = 0; /* 5G BW40-1S */
+ }
+#endif /* CONFIG_IEEE80211_BAND_5GHZ */
+}
- for (path = RF_PATH_A; path < RF_PATH_MAX; path++) {
- /* TODO: 8814A's NumTotalRFPath differs at probe(3) and up(4), need fixed
- if (path >= hal_data->NumTotalRFPath)
- break;
- */
+#if DBG_PG_TXPWR_READ
+#define LOAD_PG_TXPWR_WARN_COND(_txpwr_src) 1
+#else
+#define LOAD_PG_TXPWR_WARN_COND(_txpwr_src) (_txpwr_src > PG_TXPWR_SRC_PG_DATA)
+#endif
- for (rs = 0; rs < RATE_SECTION_NUM; rs++) {
- tx_num = rate_section_to_tx_num(rs);
- if (tx_num >= hal_spec->nss_num)
- continue;
+u16 hal_load_pg_txpwr_info_path_2g(
+ _adapter *adapter,
+ TxPowerInfo24G *pwr_info,
+ u32 path,
+ u8 txpwr_src,
+ const struct map_t *txpwr_map,
+ u16 pg_offset)
+{
+ struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+ u16 offset = pg_offset;
+ u8 group, tx_idx;
+ u8 val;
+ u8 tmp_base;
+ s8 tmp_diff;
+
+ if (pwr_info == NULL || !hal_chk_band_cap(adapter, BAND_CAP_2G)) {
+ offset += PG_TXPWR_1PATH_BYTE_NUM_2G;
+ goto exit;
+ }
- if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
- continue;
+ if (DBG_PG_TXPWR_READ)
+ RTW_INFO("%s [%c] offset:0x%03x\n", __func__, rf_path_char(path), offset);
+
+ for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
+ if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path)) {
+ tmp_base = map_read8(txpwr_map, offset);
+ if (!IS_PG_TXPWR_BASE_INVALID(tmp_base)
+ && IS_PG_TXPWR_BASE_INVALID(pwr_info->IndexCCK_Base[path][group])
+ ) {
+ pwr_info->IndexCCK_Base[path][group] = tmp_base;
+ if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
+ RTW_INFO("[%c] 2G G%02d CCK-1T base:%u from %s\n", rf_path_char(path), group, tmp_base, pg_txpwr_src_str(txpwr_src));
+ }
+ }
+ offset++;
+ }
- base = _PHY_GetTxPowerByRate(pAdapter, band, path, tx_num, rate_sec_base[rs]);
- phy_SetTxPowerByRateBase(pAdapter, band, path, rs, tx_num, base);
+ for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++) {
+ if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path)) {
+ tmp_base = map_read8(txpwr_map, offset);
+ if (!IS_PG_TXPWR_BASE_INVALID(tmp_base)
+ && IS_PG_TXPWR_BASE_INVALID(pwr_info->IndexBW40_Base[path][group])
+ ) {
+ pwr_info->IndexBW40_Base[path][group] = tmp_base;
+ if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
+ RTW_INFO("[%c] 2G G%02d BW40-1S base:%u from %s\n", rf_path_char(path), group, tmp_base, pg_txpwr_src_str(txpwr_src));
}
}
+ offset++;
}
-}
-#ifdef TX_POWER_BY_RATE_OLD
-u8
-PHY_GetRateSectionIndexOfTxPowerByRate(
- IN PADAPTER pAdapter,
- IN u32 RegAddr,
- IN u32 BitMask
-) {
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
- PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
- u8 index = 0;
+ for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
+ if (tx_idx == 0) {
+ if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) {
+ val = map_read8(txpwr_map, offset);
+ tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
+ if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
+ && IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])
+ ) {
+ pwr_info->BW20_Diff[path][tx_idx] = tmp_diff;
+ if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
+ RTW_INFO("[%c] 2G BW20-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
+ }
+ tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
+ if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
+ && IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx])
+ ) {
+ pwr_info->OFDM_Diff[path][tx_idx] = tmp_diff;
+ if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
+ RTW_INFO("[%c] 2G OFDM-%dT diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
+ }
+ }
+ offset++;
+ } else {
+ if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) {
+ val = map_read8(txpwr_map, offset);
+ tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
+ if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
+ && IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW40_Diff[path][tx_idx])
+ ) {
+ pwr_info->BW40_Diff[path][tx_idx] = tmp_diff;
+ if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
+ RTW_INFO("[%c] 2G BW40-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
- if (pDM_Odm->PhyRegPgVersion == 0) {
- switch (RegAddr) {
- case rTxAGC_A_Rate18_06:
- index = 0;
- break;
- case rTxAGC_A_Rate54_24:
- index = 1;
+ }
+ tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
+ if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
+ && IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])
+ ) {
+ pwr_info->BW20_Diff[path][tx_idx] = tmp_diff;
+ if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
+ RTW_INFO("[%c] 2G BW20-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
+ }
+ }
+ offset++;
+
+ if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) {
+ val = map_read8(txpwr_map, offset);
+ tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
+ if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
+ && IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx])
+ ) {
+ pwr_info->OFDM_Diff[path][tx_idx] = tmp_diff;
+ if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
+ RTW_INFO("[%c] 2G OFDM-%dT diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
+ }
+ tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
+ if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
+ && IS_PG_TXPWR_DIFF_INVALID(pwr_info->CCK_Diff[path][tx_idx])
+ ) {
+ pwr_info->CCK_Diff[path][tx_idx] = tmp_diff;
+ if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
+ RTW_INFO("[%c] 2G CCK-%dT diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
+ }
+ }
+ offset++;
+ }
+ }
+
+ if (offset != pg_offset + PG_TXPWR_1PATH_BYTE_NUM_2G) {
+ RTW_ERR("%s parse %d bytes != %d\n", __func__, offset - pg_offset, PG_TXPWR_1PATH_BYTE_NUM_2G);
+ rtw_warn_on(1);
+ }
+
+exit:
+ return offset;
+}
+
+u16 hal_load_pg_txpwr_info_path_5g(
+ _adapter *adapter,
+ TxPowerInfo5G *pwr_info,
+ u32 path,
+ u8 txpwr_src,
+ const struct map_t *txpwr_map,
+ u16 pg_offset)
+{
+ struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+ u16 offset = pg_offset;
+ u8 group, tx_idx;
+ u8 val;
+ u8 tmp_base;
+ s8 tmp_diff;
+
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+ if (pwr_info == NULL || !hal_chk_band_cap(adapter, BAND_CAP_5G))
+#endif
+ {
+ offset += PG_TXPWR_1PATH_BYTE_NUM_5G;
+ goto exit;
+ }
+
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+ if (DBG_PG_TXPWR_READ)
+ RTW_INFO("%s[%c] eaddr:0x%03x\n", __func__, rf_path_char(path), offset);
+
+ for (group = 0; group < MAX_CHNL_GROUP_5G; group++) {
+ if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path)) {
+ tmp_base = map_read8(txpwr_map, offset);
+ if (!IS_PG_TXPWR_BASE_INVALID(tmp_base)
+ && IS_PG_TXPWR_BASE_INVALID(pwr_info->IndexBW40_Base[path][group])
+ ) {
+ pwr_info->IndexBW40_Base[path][group] = tmp_base;
+ if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
+ RTW_INFO("[%c] 5G G%02d BW40-1S base:%u from %s\n", rf_path_char(path), group, tmp_base, pg_txpwr_src_str(txpwr_src));
+ }
+ }
+ offset++;
+ }
+
+ for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
+ if (tx_idx == 0) {
+ if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) {
+ val = map_read8(txpwr_map, offset);
+ tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
+ if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
+ && IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])
+ ) {
+ pwr_info->BW20_Diff[path][tx_idx] = tmp_diff;
+ if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
+ RTW_INFO("[%c] 5G BW20-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
+ }
+ tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
+ if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
+ && IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx])
+ ) {
+ pwr_info->OFDM_Diff[path][tx_idx] = tmp_diff;
+ if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
+ RTW_INFO("[%c] 5G OFDM-%dT diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
+ }
+ }
+ offset++;
+ } else {
+ if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) {
+ val = map_read8(txpwr_map, offset);
+ tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
+ if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
+ && IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW40_Diff[path][tx_idx])
+ ) {
+ pwr_info->BW40_Diff[path][tx_idx] = tmp_diff;
+ if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
+ RTW_INFO("[%c] 5G BW40-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
+ }
+ tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
+ if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
+ && IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx])
+ ) {
+ pwr_info->BW20_Diff[path][tx_idx] = tmp_diff;
+ if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
+ RTW_INFO("[%c] 5G BW20-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
+ }
+ }
+ offset++;
+ }
+ }
+
+ /* OFDM diff 2T ~ 3T */
+ if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, 1)) {
+ val = map_read8(txpwr_map, offset);
+ tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
+ if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
+ && IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][1])
+ ) {
+ pwr_info->OFDM_Diff[path][1] = tmp_diff;
+ if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
+ RTW_INFO("[%c] 5G OFDM-%dT diff:%d from %s\n", rf_path_char(path), 2, tmp_diff, pg_txpwr_src_str(txpwr_src));
+ }
+ if (HAL_SPEC_CHK_TX_CNT(hal_spec, 2)) {
+ tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
+ if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
+ && IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][2])
+ ) {
+ pwr_info->OFDM_Diff[path][2] = tmp_diff;
+ if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
+ RTW_INFO("[%c] 5G OFDM-%dT diff:%d from %s\n", rf_path_char(path), 3, tmp_diff, pg_txpwr_src_str(txpwr_src));
+ }
+ }
+ }
+ offset++;
+
+ /* OFDM diff 4T */
+ if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, 3)) {
+ val = map_read8(txpwr_map, offset);
+ tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
+ if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
+ && IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][3])
+ ) {
+ pwr_info->OFDM_Diff[path][3] = tmp_diff;
+ if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
+ RTW_INFO("[%c] 5G OFDM-%dT diff:%d from %s\n", rf_path_char(path), 4, tmp_diff, pg_txpwr_src_str(txpwr_src));
+ }
+ }
+ offset++;
+
+ for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
+ if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) {
+ val = map_read8(txpwr_map, offset);
+ tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val);
+ if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
+ && IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW80_Diff[path][tx_idx])
+ ) {
+ pwr_info->BW80_Diff[path][tx_idx] = tmp_diff;
+ if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
+ RTW_INFO("[%c] 5G BW80-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
+ }
+ tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val);
+ if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff)
+ && IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW160_Diff[path][tx_idx])
+ ) {
+ pwr_info->BW160_Diff[path][tx_idx] = tmp_diff;
+ if (LOAD_PG_TXPWR_WARN_COND(txpwr_src))
+ RTW_INFO("[%c] 5G BW160-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src));
+ }
+ }
+ offset++;
+ }
+
+ if (offset != pg_offset + PG_TXPWR_1PATH_BYTE_NUM_5G) {
+ RTW_ERR("%s parse %d bytes != %d\n", __func__, offset - pg_offset, PG_TXPWR_1PATH_BYTE_NUM_5G);
+ rtw_warn_on(1);
+ }
+
+#endif /* #ifdef CONFIG_IEEE80211_BAND_5GHZ */
+
+exit:
+ return offset;
+}
+
+void hal_load_pg_txpwr_info(
+ _adapter *adapter,
+ TxPowerInfo24G *pwr_info_2g,
+ TxPowerInfo5G *pwr_info_5g,
+ u8 *pg_data,
+ BOOLEAN AutoLoadFail
+)
+{
+ struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+ u8 path;
+ u16 pg_offset;
+ u8 txpwr_src = PG_TXPWR_SRC_PG_DATA;
+ struct map_t pg_data_map = MAP_ENT(184, 1, 0xFF, MAPSEG_PTR_ENT(0x00, 184, pg_data));
+ const struct map_t *txpwr_map = NULL;
+
+ /* init with invalid value and some dummy base and diff */
+ hal_init_pg_txpwr_info_2g(adapter, pwr_info_2g);
+ hal_init_pg_txpwr_info_5g(adapter, pwr_info_5g);
+
+select_src:
+ pg_offset = hal_spec->pg_txpwr_saddr;
+
+ switch (txpwr_src) {
+ case PG_TXPWR_SRC_PG_DATA:
+ txpwr_map = &pg_data_map;
+ break;
+ case PG_TXPWR_SRC_IC_DEF:
+ txpwr_map = hal_pg_txpwr_def_info(adapter);
+ break;
+ case PG_TXPWR_SRC_DEF:
+ default:
+ txpwr_map = &pg_txpwr_def_info;
+ break;
+ };
+
+ if (txpwr_map == NULL)
+ goto end_parse;
+
+ for (path = 0; path < MAX_RF_PATH ; path++) {
+ if (!HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && !HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path))
break;
- case rTxAGC_A_CCK1_Mcs32:
- index = 6;
+ pg_offset = hal_load_pg_txpwr_info_path_2g(adapter, pwr_info_2g, path, txpwr_src, txpwr_map, pg_offset);
+ pg_offset = hal_load_pg_txpwr_info_path_5g(adapter, pwr_info_5g, path, txpwr_src, txpwr_map, pg_offset);
+ }
+
+ if (hal_chk_pg_txpwr_info_2g(adapter, pwr_info_2g) == _SUCCESS
+ && hal_chk_pg_txpwr_info_5g(adapter, pwr_info_5g) == _SUCCESS)
+ goto exit;
+
+end_parse:
+ txpwr_src++;
+ if (txpwr_src < PG_TXPWR_SRC_NUM)
+ goto select_src;
+
+ if (hal_chk_pg_txpwr_info_2g(adapter, pwr_info_2g) != _SUCCESS
+ || hal_chk_pg_txpwr_info_5g(adapter, pwr_info_5g) != _SUCCESS)
+ rtw_warn_on(1);
+
+exit:
+ #if DBG_PG_TXPWR_READ
+ if (pwr_info_2g)
+ dump_pg_txpwr_info_2g(RTW_DBGDUMP, pwr_info_2g, 4, 4);
+ if (pwr_info_5g)
+ dump_pg_txpwr_info_5g(RTW_DBGDUMP, pwr_info_5g, 4, 4);
+ #endif
+
+ return;
+}
+
+#ifdef CONFIG_EFUSE_CONFIG_FILE
+
+#define EFUSE_POWER_INDEX_INVALID 0xFF
+
+static u8 _check_phy_efuse_tx_power_info_valid(u8 *pg_data, int base_len, u16 pg_offset)
+{
+ int ff_cnt = 0;
+ int i;
+
+ for (i = 0; i < base_len; i++) {
+ if (*(pg_data + pg_offset + i) == 0xFF)
+ ff_cnt++;
+ }
+
+ if (ff_cnt == 0)
+ return _TRUE;
+ else if (ff_cnt == base_len)
+ return _FALSE;
+ else
+ return EFUSE_POWER_INDEX_INVALID;
+}
+
+int check_phy_efuse_tx_power_info_valid(_adapter *adapter)
+{
+ struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+ u8 *pg_data = hal_data->efuse_eeprom_data;
+ u16 pg_offset = hal_spec->pg_txpwr_saddr;
+ u8 path;
+ u8 valid_2g_path_bmp = 0;
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+ u8 valid_5g_path_bmp = 0;
+#endif
+ int result = _FALSE;
+
+ for (path = 0; path < MAX_RF_PATH; path++) {
+ u8 ret = _FALSE;
+
+ if (!HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && !HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path))
break;
- case rTxAGC_B_CCK11_A_CCK2_11:
- if (BitMask == bMaskH3Bytes)
- index = 7;
- else if (BitMask == 0x000000ff)
- index = 15;
+
+ if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path)) {
+ ret = _check_phy_efuse_tx_power_info_valid(pg_data, PG_TXPWR_BASE_BYTE_NUM_2G, pg_offset);
+ if (ret == _TRUE)
+ valid_2g_path_bmp |= BIT(path);
+ else if (ret == EFUSE_POWER_INDEX_INVALID)
+ return _FALSE;
+ }
+ pg_offset += PG_TXPWR_1PATH_BYTE_NUM_2G;
+
+ #ifdef CONFIG_IEEE80211_BAND_5GHZ
+ if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path)) {
+ ret = _check_phy_efuse_tx_power_info_valid(pg_data, PG_TXPWR_BASE_BYTE_NUM_5G, pg_offset);
+ if (ret == _TRUE)
+ valid_5g_path_bmp |= BIT(path);
+ else if (ret == EFUSE_POWER_INDEX_INVALID)
+ return _FALSE;
+ }
+ #endif
+ pg_offset += PG_TXPWR_1PATH_BYTE_NUM_5G;
+ }
+
+ if ((hal_chk_band_cap(adapter, BAND_CAP_2G) && valid_2g_path_bmp)
+ #ifdef CONFIG_IEEE80211_BAND_5GHZ
+ || (hal_chk_band_cap(adapter, BAND_CAP_5G) && valid_5g_path_bmp)
+ #endif
+ )
+ return _TRUE;
+
+ return _FALSE;
+}
+#endif /* CONFIG_EFUSE_CONFIG_FILE */
+
+void hal_load_txpwr_info(
+ _adapter *adapter,
+ TxPowerInfo24G *pwr_info_2g,
+ TxPowerInfo5G *pwr_info_5g,
+ u8 *pg_data
+)
+{
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+ struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+ u8 max_tx_cnt = hal_spec->max_tx_cnt;
+ u8 rfpath, ch_idx, group, tx_idx;
+
+ /* load from pg data (or default value) */
+ hal_load_pg_txpwr_info(adapter, pwr_info_2g, pwr_info_5g, pg_data, _FALSE);
+
+ /* transform to hal_data */
+ for (rfpath = 0; rfpath < MAX_RF_PATH; rfpath++) {
+
+ if (!pwr_info_2g || !HAL_SPEC_CHK_RF_PATH_2G(hal_spec, rfpath))
+ goto bypass_2g;
+
+ /* 2.4G base */
+ for (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++) {
+ u8 cck_group;
+
+ if (rtw_get_ch_group(ch_idx + 1, &group, &cck_group) != BAND_ON_2_4G)
+ continue;
+
+ hal_data->Index24G_CCK_Base[rfpath][ch_idx] = pwr_info_2g->IndexCCK_Base[rfpath][cck_group];
+ hal_data->Index24G_BW40_Base[rfpath][ch_idx] = pwr_info_2g->IndexBW40_Base[rfpath][group];
+ }
+
+ /* 2.4G diff */
+ for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
+ if (tx_idx >= max_tx_cnt)
+ break;
+
+ hal_data->CCK_24G_Diff[rfpath][tx_idx] = pwr_info_2g->CCK_Diff[rfpath][tx_idx];
+ hal_data->OFDM_24G_Diff[rfpath][tx_idx] = pwr_info_2g->OFDM_Diff[rfpath][tx_idx];
+ hal_data->BW20_24G_Diff[rfpath][tx_idx] = pwr_info_2g->BW20_Diff[rfpath][tx_idx];
+ hal_data->BW40_24G_Diff[rfpath][tx_idx] = pwr_info_2g->BW40_Diff[rfpath][tx_idx];
+ }
+bypass_2g:
+ ;
+
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+ if (!pwr_info_5g || !HAL_SPEC_CHK_RF_PATH_5G(hal_spec, rfpath))
+ goto bypass_5g;
+
+ /* 5G base */
+ for (ch_idx = 0; ch_idx < CENTER_CH_5G_ALL_NUM; ch_idx++) {
+ if (rtw_get_ch_group(center_ch_5g_all[ch_idx], &group, NULL) != BAND_ON_5G)
+ continue;
+ hal_data->Index5G_BW40_Base[rfpath][ch_idx] = pwr_info_5g->IndexBW40_Base[rfpath][group];
+ }
+
+ for (ch_idx = 0 ; ch_idx < CENTER_CH_5G_80M_NUM; ch_idx++) {
+ u8 upper, lower;
+
+ if (rtw_get_ch_group(center_ch_5g_80m[ch_idx], &group, NULL) != BAND_ON_5G)
+ continue;
+
+ upper = pwr_info_5g->IndexBW40_Base[rfpath][group];
+ lower = pwr_info_5g->IndexBW40_Base[rfpath][group + 1];
+ hal_data->Index5G_BW80_Base[rfpath][ch_idx] = (upper + lower) / 2;
+ }
+
+ /* 5G diff */
+ for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) {
+ if (tx_idx >= max_tx_cnt)
+ break;
+
+ hal_data->OFDM_5G_Diff[rfpath][tx_idx] = pwr_info_5g->OFDM_Diff[rfpath][tx_idx];
+ hal_data->BW20_5G_Diff[rfpath][tx_idx] = pwr_info_5g->BW20_Diff[rfpath][tx_idx];
+ hal_data->BW40_5G_Diff[rfpath][tx_idx] = pwr_info_5g->BW40_Diff[rfpath][tx_idx];
+ hal_data->BW80_5G_Diff[rfpath][tx_idx] = pwr_info_5g->BW80_Diff[rfpath][tx_idx];
+ }
+bypass_5g:
+ ;
+#endif /* CONFIG_IEEE80211_BAND_5GHZ */
+ }
+}
+
+void dump_hal_txpwr_info_2g(void *sel, _adapter *adapter, u8 rfpath_num, u8 max_tx_cnt)
+{
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+ int path, ch_idx, tx_idx;
+
+ RTW_PRINT_SEL(sel, "2.4G\n");
+ RTW_PRINT_SEL(sel, "CCK-1T base:\n");
+ RTW_PRINT_SEL(sel, "%4s ", "");
+ for (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++)
+ _RTW_PRINT_SEL(sel, "%2d ", center_ch_2g[ch_idx]);
+ _RTW_PRINT_SEL(sel, "\n");
+ for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+ RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+ for (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++)
+ _RTW_PRINT_SEL(sel, "%2u ", hal_data->Index24G_CCK_Base[path][ch_idx]);
+ _RTW_PRINT_SEL(sel, "\n");
+ }
+ RTW_PRINT_SEL(sel, "\n");
+
+ RTW_PRINT_SEL(sel, "CCK diff:\n");
+ RTW_PRINT_SEL(sel, "%4s ", "");
+ for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+ _RTW_PRINT_SEL(sel, "%dT ", tx_idx + 1);
+ _RTW_PRINT_SEL(sel, "\n");
+ for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+ RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+ for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+ _RTW_PRINT_SEL(sel, "%2d ", hal_data->CCK_24G_Diff[path][tx_idx]);
+ _RTW_PRINT_SEL(sel, "\n");
+ }
+ RTW_PRINT_SEL(sel, "\n");
+
+ RTW_PRINT_SEL(sel, "BW40-1S base:\n");
+ RTW_PRINT_SEL(sel, "%4s ", "");
+ for (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++)
+ _RTW_PRINT_SEL(sel, "%2d ", center_ch_2g[ch_idx]);
+ _RTW_PRINT_SEL(sel, "\n");
+ for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+ RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+ for (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++)
+ _RTW_PRINT_SEL(sel, "%2u ", hal_data->Index24G_BW40_Base[path][ch_idx]);
+ _RTW_PRINT_SEL(sel, "\n");
+ }
+ RTW_PRINT_SEL(sel, "\n");
+
+ RTW_PRINT_SEL(sel, "OFDM diff:\n");
+ RTW_PRINT_SEL(sel, "%4s ", "");
+ for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+ _RTW_PRINT_SEL(sel, "%dT ", tx_idx + 1);
+ _RTW_PRINT_SEL(sel, "\n");
+ for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+ RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+ for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+ _RTW_PRINT_SEL(sel, "%2d ", hal_data->OFDM_24G_Diff[path][tx_idx]);
+ _RTW_PRINT_SEL(sel, "\n");
+ }
+ RTW_PRINT_SEL(sel, "\n");
+
+ RTW_PRINT_SEL(sel, "BW20 diff:\n");
+ RTW_PRINT_SEL(sel, "%4s ", "");
+ for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+ _RTW_PRINT_SEL(sel, "%dS ", tx_idx + 1);
+ _RTW_PRINT_SEL(sel, "\n");
+ for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+ RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+ for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+ _RTW_PRINT_SEL(sel, "%2d ", hal_data->BW20_24G_Diff[path][tx_idx]);
+ _RTW_PRINT_SEL(sel, "\n");
+ }
+ RTW_PRINT_SEL(sel, "\n");
+
+ RTW_PRINT_SEL(sel, "BW40 diff:\n");
+ RTW_PRINT_SEL(sel, "%4s ", "");
+ for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+ _RTW_PRINT_SEL(sel, "%dS ", tx_idx + 1);
+ _RTW_PRINT_SEL(sel, "\n");
+ for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+ RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+ for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+ _RTW_PRINT_SEL(sel, "%2d ", hal_data->BW40_24G_Diff[path][tx_idx]);
+ _RTW_PRINT_SEL(sel, "\n");
+ }
+ RTW_PRINT_SEL(sel, "\n");
+}
+
+void dump_hal_txpwr_info_5g(void *sel, _adapter *adapter, u8 rfpath_num, u8 max_tx_cnt)
+{
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+ int path, ch_idx, tx_idx;
+ u8 dump_section = 0;
+ u8 ch_idx_s = 0;
+
+ RTW_PRINT_SEL(sel, "5G\n");
+ RTW_PRINT_SEL(sel, "BW40-1S base:\n");
+ do {
+ #define DUMP_5G_BW40_BASE_SECTION_NUM 3
+ u8 end[DUMP_5G_BW40_BASE_SECTION_NUM] = {64, 144, 177};
+
+ RTW_PRINT_SEL(sel, "%4s ", "");
+ for (ch_idx = ch_idx_s; ch_idx < CENTER_CH_5G_ALL_NUM; ch_idx++) {
+ _RTW_PRINT_SEL(sel, "%3d ", center_ch_5g_all[ch_idx]);
+ if (end[dump_section] == center_ch_5g_all[ch_idx])
+ break;
+ }
+ _RTW_PRINT_SEL(sel, "\n");
+ for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+ RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+ for (ch_idx = ch_idx_s; ch_idx < CENTER_CH_5G_ALL_NUM; ch_idx++) {
+ _RTW_PRINT_SEL(sel, "%3u ", hal_data->Index5G_BW40_Base[path][ch_idx]);
+ if (end[dump_section] == center_ch_5g_all[ch_idx])
+ break;
+ }
+ _RTW_PRINT_SEL(sel, "\n");
+ }
+ RTW_PRINT_SEL(sel, "\n");
+
+ ch_idx_s = ch_idx + 1;
+ dump_section++;
+ if (dump_section >= DUMP_5G_BW40_BASE_SECTION_NUM)
break;
+ } while (1);
+
+ RTW_PRINT_SEL(sel, "BW80-1S base:\n");
+ RTW_PRINT_SEL(sel, "%4s ", "");
+ for (ch_idx = 0; ch_idx < CENTER_CH_5G_80M_NUM; ch_idx++)
+ _RTW_PRINT_SEL(sel, "%3d ", center_ch_5g_80m[ch_idx]);
+ _RTW_PRINT_SEL(sel, "\n");
+ for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+ RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+ for (ch_idx = 0; ch_idx < CENTER_CH_5G_80M_NUM; ch_idx++)
+ _RTW_PRINT_SEL(sel, "%3u ", hal_data->Index5G_BW80_Base[path][ch_idx]);
+ _RTW_PRINT_SEL(sel, "\n");
+ }
+ RTW_PRINT_SEL(sel, "\n");
+
+ RTW_PRINT_SEL(sel, "OFDM diff:\n");
+ RTW_PRINT_SEL(sel, "%4s ", "");
+ for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+ _RTW_PRINT_SEL(sel, "%dT ", tx_idx + 1);
+ _RTW_PRINT_SEL(sel, "\n");
+ for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+ RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+ for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+ _RTW_PRINT_SEL(sel, "%2d ", hal_data->OFDM_5G_Diff[path][tx_idx]);
+ _RTW_PRINT_SEL(sel, "\n");
+ }
+ RTW_PRINT_SEL(sel, "\n");
+
+ RTW_PRINT_SEL(sel, "BW20 diff:\n");
+ RTW_PRINT_SEL(sel, "%4s ", "");
+ for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+ _RTW_PRINT_SEL(sel, "%dS ", tx_idx + 1);
+ _RTW_PRINT_SEL(sel, "\n");
+ for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+ RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+ for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+ _RTW_PRINT_SEL(sel, "%2d ", hal_data->BW20_5G_Diff[path][tx_idx]);
+ _RTW_PRINT_SEL(sel, "\n");
+ }
+ RTW_PRINT_SEL(sel, "\n");
+
+ RTW_PRINT_SEL(sel, "BW40 diff:\n");
+ RTW_PRINT_SEL(sel, "%4s ", "");
+ for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+ _RTW_PRINT_SEL(sel, "%dS ", tx_idx + 1);
+ _RTW_PRINT_SEL(sel, "\n");
+ for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+ RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+ for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+ _RTW_PRINT_SEL(sel, "%2d ", hal_data->BW40_5G_Diff[path][tx_idx]);
+ _RTW_PRINT_SEL(sel, "\n");
+ }
+ RTW_PRINT_SEL(sel, "\n");
+
+ RTW_PRINT_SEL(sel, "BW80 diff:\n");
+ RTW_PRINT_SEL(sel, "%4s ", "");
+ for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+ _RTW_PRINT_SEL(sel, "%dS ", tx_idx + 1);
+ _RTW_PRINT_SEL(sel, "\n");
+ for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) {
+ RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path));
+ for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++)
+ _RTW_PRINT_SEL(sel, "%2d ", hal_data->BW80_5G_Diff[path][tx_idx]);
+ _RTW_PRINT_SEL(sel, "\n");
+ }
+ RTW_PRINT_SEL(sel, "\n");
+#endif /* CONFIG_IEEE80211_BAND_5GHZ */
+}
+
+/*
+* rtw_regsty_get_target_tx_power -
+*
+* Return dBm or -1 for undefined
+*/
+s8 rtw_regsty_get_target_tx_power(
+ IN PADAPTER Adapter,
+ IN u8 Band,
+ IN u8 RfPath,
+ IN RATE_SECTION RateSection
+)
+{
+ struct registry_priv *regsty = adapter_to_regsty(Adapter);
+ s8 value = 0;
+
+ if (RfPath > RF_PATH_D) {
+ RTW_PRINT("%s invalid RfPath:%d\n", __func__, RfPath);
+ return -1;
+ }
+
+ if (Band != BAND_ON_2_4G
+ #ifdef CONFIG_IEEE80211_BAND_5GHZ
+ && Band != BAND_ON_5G
+ #endif
+ ) {
+ RTW_PRINT("%s invalid Band:%d\n", __func__, Band);
+ return -1;
+ }
+
+ if (RateSection >= RATE_SECTION_NUM
+ #ifdef CONFIG_IEEE80211_BAND_5GHZ
+ || (Band == BAND_ON_5G && RateSection == CCK)
+ #endif
+ ) {
+ RTW_PRINT("%s invalid RateSection:%d in Band:%d, RfPath:%d\n", __func__
+ , RateSection, Band, RfPath);
+ return -1;
+ }
+
+ if (Band == BAND_ON_2_4G)
+ value = regsty->target_tx_pwr_2g[RfPath][RateSection];
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+ else /* BAND_ON_5G */
+ value = regsty->target_tx_pwr_5g[RfPath][RateSection - 1];
+#endif
+
+ return value;
+}
+
+bool rtw_regsty_chk_target_tx_power_valid(_adapter *adapter)
+{
+ struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+ int path, tx_num, band, rs;
+ s8 target;
+
+ for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
+ if (!hal_is_band_support(adapter, band))
+ continue;
+
+ for (path = 0; path < RF_PATH_MAX; path++) {
+ if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
+ break;
+
+ for (rs = 0; rs < RATE_SECTION_NUM; rs++) {
+ tx_num = rate_section_to_tx_num(rs);
+ if (tx_num >= hal_spec->tx_nss_num)
+ continue;
+
+ if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
+ continue;
+
+ if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter))
+ continue;
+
+ target = rtw_regsty_get_target_tx_power(adapter, band, path, rs);
+ if (target == -1) {
+ RTW_PRINT("%s return _FALSE for band:%d, path:%d, rs:%d, t:%d\n", __func__, band, path, rs, target);
+ return _FALSE;
+ }
+ }
+ }
+ }
+
+ return _TRUE;
+}
+
+/*
+* PHY_GetTxPowerByRateBase -
+*
+* Return 2 times of dBm
+*/
+u8
+PHY_GetTxPowerByRateBase(
+ IN PADAPTER Adapter,
+ IN u8 Band,
+ IN u8 RfPath,
+ IN RATE_SECTION RateSection
+)
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+ u8 value = 0;
+
+ if (RfPath > RF_PATH_D) {
+ RTW_PRINT("%s invalid RfPath:%d\n", __func__, RfPath);
+ return 0;
+ }
+
+ if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {
+ RTW_PRINT("%s invalid Band:%d\n", __func__, Band);
+ return 0;
+ }
+
+ if (RateSection >= RATE_SECTION_NUM
+ || (Band == BAND_ON_5G && RateSection == CCK)
+ ) {
+ RTW_PRINT("%s invalid RateSection:%d in Band:%d, RfPath:%d\n", __func__
+ , RateSection, Band, RfPath);
+ return 0;
+ }
+
+ if (Band == BAND_ON_2_4G)
+ value = pHalData->TxPwrByRateBase2_4G[RfPath][RateSection];
+ else /* BAND_ON_5G */
+ value = pHalData->TxPwrByRateBase5G[RfPath][RateSection - 1];
+
+ return value;
+}
+
+VOID
+phy_SetTxPowerByRateBase(
+ IN PADAPTER Adapter,
+ IN u8 Band,
+ IN u8 RfPath,
+ IN RATE_SECTION RateSection,
+ IN u8 Value
+)
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+
+ if (RfPath > RF_PATH_D) {
+ RTW_PRINT("%s invalid RfPath:%d\n", __func__, RfPath);
+ return;
+ }
+
+ if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {
+ RTW_PRINT("%s invalid Band:%d\n", __func__, Band);
+ return;
+ }
+
+ if (RateSection >= RATE_SECTION_NUM
+ || (Band == BAND_ON_5G && RateSection == CCK)
+ ) {
+ RTW_PRINT("%s invalid RateSection:%d in %sG, RfPath:%d\n", __func__
+ , RateSection, (Band == BAND_ON_2_4G) ? "2.4" : "5", RfPath);
+ return;
+ }
+
+ if (Band == BAND_ON_2_4G)
+ pHalData->TxPwrByRateBase2_4G[RfPath][RateSection] = Value;
+ else /* BAND_ON_5G */
+ pHalData->TxPwrByRateBase5G[RfPath][RateSection - 1] = Value;
+}
+
+static inline BOOLEAN phy_is_txpwr_by_rate_undefined_of_band_path(_adapter *adapter, u8 band, u8 path)
+{
+ struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+ u8 rate_idx = 0;
+
+ for (rate_idx = 0; rate_idx < TX_PWR_BY_RATE_NUM_RATE; rate_idx++) {
+ if (hal_data->TxPwrByRateOffset[band][path][rate_idx] != 0)
+ goto exit;
+ }
+
+exit:
+ return rate_idx >= TX_PWR_BY_RATE_NUM_RATE ? _TRUE : _FALSE;
+}
+
+static inline void phy_txpwr_by_rate_duplicate_band_path(_adapter *adapter, u8 band, u8 s_path, u8 t_path)
+{
+ struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+ u8 rate_idx = 0;
+
+ for (rate_idx = 0; rate_idx < TX_PWR_BY_RATE_NUM_RATE; rate_idx++)
+ hal_data->TxPwrByRateOffset[band][t_path][rate_idx] = hal_data->TxPwrByRateOffset[band][s_path][rate_idx];
+}
+
+static void phy_txpwr_by_rate_chk_for_path_dup(_adapter *adapter)
+{
+ struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+ u8 band, path;
+ s8 src_path;
+
+ for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++)
+ for (path = RF_PATH_A; path < RF_PATH_MAX; path++)
+ hal_data->txpwr_by_rate_undefined_band_path[band][path] = 0;
+
+ for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
+ if (!hal_is_band_support(adapter, band))
+ continue;
+
+ for (path = RF_PATH_A; path < RF_PATH_MAX; path++) {
+ if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
+ continue;
+
+ if (phy_is_txpwr_by_rate_undefined_of_band_path(adapter, band, path))
+ hal_data->txpwr_by_rate_undefined_band_path[band][path] = 1;
+ }
+ }
+
+ for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
+ if (!hal_is_band_support(adapter, band))
+ continue;
+
+ src_path = -1;
+ for (path = RF_PATH_A; path < RF_PATH_MAX; path++) {
+ if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
+ continue;
+
+ /* find src */
+ if (src_path == -1 && hal_data->txpwr_by_rate_undefined_band_path[band][path] == 0)
+ src_path = path;
+ }
+
+ if (src_path == -1) {
+ RTW_ERR("%s all power by rate undefined\n", __func__);
+ continue;
+ }
+
+ for (path = RF_PATH_A; path < RF_PATH_MAX; path++) {
+ if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
+ continue;
+
+ /* duplicate src to undefined one */
+ if (hal_data->txpwr_by_rate_undefined_band_path[band][path] == 1) {
+ RTW_INFO("%s duplicate %s [%c] to [%c]\n", __func__
+ , band_str(band), rf_path_char(src_path), rf_path_char(path));
+ phy_txpwr_by_rate_duplicate_band_path(adapter, band, src_path, path);
+ }
+ }
+ }
+}
+
+VOID
+phy_StoreTxPowerByRateBase(
+ IN PADAPTER pAdapter
+)
+{
+ struct hal_spec_t *hal_spec = GET_HAL_SPEC(pAdapter);
+ struct registry_priv *regsty = adapter_to_regsty(pAdapter);
+
+ u8 rate_sec_base[RATE_SECTION_NUM] = {
+ MGN_11M,
+ MGN_54M,
+ MGN_MCS7,
+ MGN_MCS15,
+ MGN_MCS23,
+ MGN_MCS31,
+ MGN_VHT1SS_MCS7,
+ MGN_VHT2SS_MCS7,
+ MGN_VHT3SS_MCS7,
+ MGN_VHT4SS_MCS7,
+ };
+
+ u8 band, path, rs, tx_num, base, index;
+
+ for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
+ if (!hal_is_band_support(pAdapter, band))
+ continue;
+
+ for (path = RF_PATH_A; path < RF_PATH_MAX; path++) {
+ if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
+ break;
+
+ for (rs = 0; rs < RATE_SECTION_NUM; rs++) {
+ tx_num = rate_section_to_tx_num(rs);
+ if (tx_num >= hal_spec->tx_nss_num)
+ continue;
- case rTxAGC_A_Mcs03_Mcs00:
- index = 2;
- break;
- case rTxAGC_A_Mcs07_Mcs04:
- index = 3;
- break;
- case rTxAGC_A_Mcs11_Mcs08:
- index = 4;
- break;
- case rTxAGC_A_Mcs15_Mcs12:
- index = 5;
- break;
- case rTxAGC_B_Rate18_06:
- index = 8;
- break;
- case rTxAGC_B_Rate54_24:
- index = 9;
- break;
- case rTxAGC_B_CCK1_55_Mcs32:
- index = 14;
- break;
- case rTxAGC_B_Mcs03_Mcs00:
- index = 10;
- break;
- case rTxAGC_B_Mcs07_Mcs04:
- index = 11;
- break;
- case rTxAGC_B_Mcs11_Mcs08:
- index = 12;
- break;
- case rTxAGC_B_Mcs15_Mcs12:
- index = 13;
- break;
- default:
- RTW_INFO("Invalid RegAddr 0x3%x in PHY_GetRateSectionIndexOfTxPowerByRate()", RegAddr);
- break;
- };
- }
+ if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
+ continue;
- return index;
+ if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter))
+ continue;
+
+ if (regsty->target_tx_pwr_valid == _TRUE)
+ base = 2 * rtw_regsty_get_target_tx_power(pAdapter, band, path, rs);
+ else
+ base = _PHY_GetTxPowerByRate(pAdapter, band, path, rate_sec_base[rs]);
+ phy_SetTxPowerByRateBase(pAdapter, band, path, rs, base);
+ }
+ }
+ }
}
-#endif /* TX_POWER_BY_RATE_OLD */
VOID
PHY_GetRateValuesOfTxPowerByRate(
- IN PADAPTER pAdapter,
- IN u32 RegAddr,
- IN u32 BitMask,
- IN u32 Value,
- OUT u8 *Rate,
- OUT s8 *PwrByRateVal,
- OUT u8 *RateNum
-) {
+ IN PADAPTER pAdapter,
+ IN u32 RegAddr,
+ IN u32 BitMask,
+ IN u32 Value,
+ OUT u8 *Rate,
+ OUT s8 *PwrByRateVal,
+ OUT u8 *RateNum
+)
+{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
- PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
+ struct dm_struct *pDM_Odm = &pHalData->odmpriv;
u8 index = 0, i = 0;
switch (RegAddr) {
@@ -387,7 +1597,7 @@ PHY_GetRateValuesOfTxPowerByRate(
Rate[3] = MGN_18M;
for (i = 0; i < 4; ++i) {
PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((Value >> (i * 8)) & 0xF));
+ ((Value >> (i * 8)) & 0xF));
}
*RateNum = 4;
break;
@@ -400,7 +1610,7 @@ PHY_GetRateValuesOfTxPowerByRate(
Rate[3] = MGN_54M;
for (i = 0; i < 4; ++i) {
PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((Value >> (i * 8)) & 0xF));
+ ((Value >> (i * 8)) & 0xF));
}
*RateNum = 4;
break;
@@ -408,7 +1618,7 @@ PHY_GetRateValuesOfTxPowerByRate(
case rTxAGC_A_CCK1_Mcs32:
Rate[0] = MGN_1M;
PwrByRateVal[0] = (s8)((((Value >> (8 + 4)) & 0xF)) * 10 +
- ((Value >> 8) & 0xF));
+ ((Value >> 8) & 0xF));
*RateNum = 1;
break;
@@ -419,13 +1629,13 @@ PHY_GetRateValuesOfTxPowerByRate(
Rate[2] = MGN_11M;
for (i = 1; i < 4; ++i) {
PwrByRateVal[i - 1] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((Value >> (i * 8)) & 0xF));
+ ((Value >> (i * 8)) & 0xF));
}
*RateNum = 3;
} else if (BitMask == 0x000000ff) {
Rate[0] = MGN_11M;
PwrByRateVal[0] = (s8)((((Value >> 4) & 0xF)) * 10 +
- (Value & 0xF));
+ (Value & 0xF));
*RateNum = 1;
}
break;
@@ -438,7 +1648,7 @@ PHY_GetRateValuesOfTxPowerByRate(
Rate[3] = MGN_MCS3;
for (i = 0; i < 4; ++i) {
PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((Value >> (i * 8)) & 0xF));
+ ((Value >> (i * 8)) & 0xF));
}
*RateNum = 4;
break;
@@ -451,7 +1661,7 @@ PHY_GetRateValuesOfTxPowerByRate(
Rate[3] = MGN_MCS7;
for (i = 0; i < 4; ++i) {
PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((Value >> (i * 8)) & 0xF));
+ ((Value >> (i * 8)) & 0xF));
}
*RateNum = 4;
break;
@@ -464,7 +1674,7 @@ PHY_GetRateValuesOfTxPowerByRate(
Rate[3] = MGN_MCS11;
for (i = 0; i < 4; ++i) {
PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((Value >> (i * 8)) & 0xF));
+ ((Value >> (i * 8)) & 0xF));
}
*RateNum = 4;
break;
@@ -477,7 +1687,7 @@ PHY_GetRateValuesOfTxPowerByRate(
Rate[3] = MGN_MCS15;
for (i = 0; i < 4; ++i) {
PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((Value >> (i * 8)) & 0xF));
+ ((Value >> (i * 8)) & 0xF));
}
*RateNum = 4;
@@ -489,7 +1699,7 @@ PHY_GetRateValuesOfTxPowerByRate(
Rate[2] = MGN_5_5M;
for (i = 1; i < 4; ++i) {
PwrByRateVal[i - 1] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((Value >> (i * 8)) & 0xF));
+ ((Value >> (i * 8)) & 0xF));
}
*RateNum = 3;
break;
@@ -504,7 +1714,7 @@ PHY_GetRateValuesOfTxPowerByRate(
Rate[3] = MGN_11M;
for (i = 0; i < 4; ++i) {
PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((Value >> (i * 8)) & 0xF));
+ ((Value >> (i * 8)) & 0xF));
}
*RateNum = 4;
break;
@@ -519,7 +1729,7 @@ PHY_GetRateValuesOfTxPowerByRate(
Rate[3] = MGN_18M;
for (i = 0; i < 4; ++i) {
PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((Value >> (i * 8)) & 0xF));
+ ((Value >> (i * 8)) & 0xF));
}
*RateNum = 4;
break;
@@ -534,7 +1744,7 @@ PHY_GetRateValuesOfTxPowerByRate(
Rate[3] = MGN_54M;
for (i = 0; i < 4; ++i) {
PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((Value >> (i * 8)) & 0xF));
+ ((Value >> (i * 8)) & 0xF));
}
*RateNum = 4;
break;
@@ -549,7 +1759,7 @@ PHY_GetRateValuesOfTxPowerByRate(
Rate[3] = MGN_MCS3;
for (i = 0; i < 4; ++i) {
PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((Value >> (i * 8)) & 0xF));
+ ((Value >> (i * 8)) & 0xF));
}
*RateNum = 4;
break;
@@ -564,7 +1774,7 @@ PHY_GetRateValuesOfTxPowerByRate(
Rate[3] = MGN_MCS7;
for (i = 0; i < 4; ++i) {
PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((Value >> (i * 8)) & 0xF));
+ ((Value >> (i * 8)) & 0xF));
}
*RateNum = 4;
break;
@@ -579,7 +1789,7 @@ PHY_GetRateValuesOfTxPowerByRate(
Rate[3] = MGN_MCS11;
for (i = 0; i < 4; ++i) {
PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((Value >> (i * 8)) & 0xF));
+ ((Value >> (i * 8)) & 0xF));
}
*RateNum = 4;
break;
@@ -594,7 +1804,7 @@ PHY_GetRateValuesOfTxPowerByRate(
Rate[3] = MGN_MCS15;
for (i = 0; i < 4; ++i) {
PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((Value >> (i * 8)) & 0xF));
+ ((Value >> (i * 8)) & 0xF));
}
*RateNum = 4;
break;
@@ -609,7 +1819,7 @@ PHY_GetRateValuesOfTxPowerByRate(
Rate[3] = MGN_VHT1SS_MCS3;
for (i = 0; i < 4; ++i) {
PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((Value >> (i * 8)) & 0xF));
+ ((Value >> (i * 8)) & 0xF));
}
*RateNum = 4;
break;
@@ -624,7 +1834,7 @@ PHY_GetRateValuesOfTxPowerByRate(
Rate[3] = MGN_VHT1SS_MCS7;
for (i = 0; i < 4; ++i) {
PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((Value >> (i * 8)) & 0xF));
+ ((Value >> (i * 8)) & 0xF));
}
*RateNum = 4;
break;
@@ -639,7 +1849,7 @@ PHY_GetRateValuesOfTxPowerByRate(
Rate[3] = MGN_VHT2SS_MCS1;
for (i = 0; i < 4; ++i) {
PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((Value >> (i * 8)) & 0xF));
+ ((Value >> (i * 8)) & 0xF));
}
*RateNum = 4;
break;
@@ -654,7 +1864,7 @@ PHY_GetRateValuesOfTxPowerByRate(
Rate[3] = MGN_VHT2SS_MCS5;
for (i = 0; i < 4; ++i) {
PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((Value >> (i * 8)) & 0xF));
+ ((Value >> (i * 8)) & 0xF));
}
*RateNum = 4;
break;
@@ -669,7 +1879,7 @@ PHY_GetRateValuesOfTxPowerByRate(
Rate[3] = MGN_VHT2SS_MCS9;
for (i = 0; i < 4; ++i) {
PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((Value >> (i * 8)) & 0xF));
+ ((Value >> (i * 8)) & 0xF));
}
*RateNum = 4;
break;
@@ -684,7 +1894,7 @@ PHY_GetRateValuesOfTxPowerByRate(
Rate[3] = MGN_MCS19;
for (i = 0; i < 4; ++i) {
PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((Value >> (i * 8)) & 0xF));
+ ((Value >> (i * 8)) & 0xF));
}
*RateNum = 4;
break;
@@ -699,7 +1909,7 @@ PHY_GetRateValuesOfTxPowerByRate(
Rate[3] = MGN_MCS23;
for (i = 0; i < 4; ++i) {
PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((Value >> (i * 8)) & 0xF));
+ ((Value >> (i * 8)) & 0xF));
}
*RateNum = 4;
break;
@@ -714,7 +1924,7 @@ PHY_GetRateValuesOfTxPowerByRate(
Rate[3] = MGN_VHT3SS_MCS3;
for (i = 0; i < 4; ++i) {
PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((Value >> (i * 8)) & 0xF));
+ ((Value >> (i * 8)) & 0xF));
}
*RateNum = 4;
break;
@@ -729,7 +1939,7 @@ PHY_GetRateValuesOfTxPowerByRate(
Rate[3] = MGN_VHT3SS_MCS7;
for (i = 0; i < 4; ++i) {
PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((Value >> (i * 8)) & 0xF));
+ ((Value >> (i * 8)) & 0xF));
}
*RateNum = 4;
break;
@@ -742,7 +1952,7 @@ PHY_GetRateValuesOfTxPowerByRate(
Rate[1] = MGN_VHT3SS_MCS9;
for (i = 0; i < 2; ++i) {
PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
- ((Value >> (i * 8)) & 0xF));
+ ((Value >> (i * 8)) & 0xF));
}
*RateNum = 2;
break;
@@ -755,14 +1965,14 @@ PHY_GetRateValuesOfTxPowerByRate(
void
PHY_StoreTxPowerByRateNew(
- IN PADAPTER pAdapter,
- IN u32 Band,
- IN u32 RfPath,
- IN u32 TxNum,
- IN u32 RegAddr,
- IN u32 BitMask,
- IN u32 Data
-) {
+ IN PADAPTER pAdapter,
+ IN u32 Band,
+ IN u32 RfPath,
+ IN u32 RegAddr,
+ IN u32 BitMask,
+ IN u32 Data
+)
+{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
u8 i = 0, rates[4] = {0}, rateNum = 0;
s8 PwrByRateVal[4] = {0};
@@ -774,282 +1984,134 @@ PHY_StoreTxPowerByRateNew(
return;
}
- if (RfPath > ODM_RF_PATH_D) {
+ if (RfPath > RF_PATH_D) {
RTW_PRINT("Invalid RfPath %d\n", RfPath);
return;
}
- if (TxNum > ODM_RF_PATH_D) {
- RTW_PRINT("Invalid TxNum %d\n", TxNum);
- return;
- }
-
for (i = 0; i < rateNum; ++i) {
u8 rate_idx = PHY_GetRateIndexOfTxPowerByRate(rates[i]);
- if (IS_1T_RATE(rates[i]))
- pHalData->TxPwrByRateOffset[Band][RfPath][RF_1TX][rate_idx] = PwrByRateVal[i];
- else if (IS_2T_RATE(rates[i]))
- pHalData->TxPwrByRateOffset[Band][RfPath][RF_2TX][rate_idx] = PwrByRateVal[i];
- else if (IS_3T_RATE(rates[i]))
- pHalData->TxPwrByRateOffset[Band][RfPath][RF_3TX][rate_idx] = PwrByRateVal[i];
- else if (IS_4T_RATE(rates[i]))
- pHalData->TxPwrByRateOffset[Band][RfPath][RF_4TX][rate_idx] = PwrByRateVal[i];
- else
- rtw_warn_on(1);
+ pHalData->TxPwrByRateOffset[Band][RfPath][rate_idx] = PwrByRateVal[i];
}
}
-#ifdef TX_POWER_BY_RATE_OLD
-void
-PHY_StoreTxPowerByRateOld(
- IN PADAPTER pAdapter,
- IN u32 RegAddr,
- IN u32 BitMask,
- IN u32 Data
-) {
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
- u8 index = PHY_GetRateSectionIndexOfTxPowerByRate(pAdapter, RegAddr, BitMask);
-
- pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][index] = Data;
- /* RTW_INFO("MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n", pHalData->pwrGroupCnt, */
- /* pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][0]); */
-}
-#endif /* TX_POWER_BY_RATE_OLD */
-
VOID
PHY_InitTxPowerByRate(
- IN PADAPTER pAdapter
-) {
+ IN PADAPTER pAdapter
+)
+{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
- u8 band = 0, rfPath = 0, TxNum = 0, rate = 0, i = 0, j = 0;
+ u8 band = 0, rfPath = 0, rate = 0, i = 0, j = 0;
- if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
- for (i = 0; i < MAX_PG_GROUP; ++i)
- for (j = 0; j < 16; ++j)
- pHalData->MCSTxPowerLevelOriginalOffset[i][j] = 0;
- } else {
- for (band = BAND_ON_2_4G; band <= BAND_ON_5G; ++band)
- for (rfPath = 0; rfPath < TX_PWR_BY_RATE_NUM_RF; ++rfPath)
- for (TxNum = 0; TxNum < TX_PWR_BY_RATE_NUM_RF; ++TxNum)
- for (rate = 0; rate < TX_PWR_BY_RATE_NUM_RATE; ++rate)
- pHalData->TxPwrByRateOffset[band][rfPath][TxNum][rate] = 0;
- }
+ for (band = BAND_ON_2_4G; band <= BAND_ON_5G; ++band)
+ for (rfPath = 0; rfPath < TX_PWR_BY_RATE_NUM_RF; ++rfPath)
+ for (rate = 0; rate < TX_PWR_BY_RATE_NUM_RATE; ++rate)
+ pHalData->TxPwrByRateOffset[band][rfPath][rate] = 0;
}
VOID
-PHY_StoreTxPowerByRate(
- IN PADAPTER pAdapter,
- IN u32 Band,
- IN u32 RfPath,
- IN u32 TxNum,
- IN u32 RegAddr,
- IN u32 BitMask,
- IN u32 Data
-) {
+phy_store_tx_power_by_rate(
+ IN PADAPTER pAdapter,
+ IN u32 Band,
+ IN u32 RfPath,
+ IN u32 TxNum,
+ IN u32 RegAddr,
+ IN u32 BitMask,
+ IN u32 Data
+)
+{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
- PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
-
- if (pDM_Odm->PhyRegPgVersion > 0)
- PHY_StoreTxPowerByRateNew(pAdapter, Band, RfPath, TxNum, RegAddr, BitMask, Data);
-#ifdef TX_POWER_BY_RATE_OLD
- else if (pDM_Odm->PhyRegPgVersion == 0) {
- PHY_StoreTxPowerByRateOld(pAdapter, RegAddr, BitMask, Data);
+ struct dm_struct *pDM_Odm = &pHalData->odmpriv;
- if (RegAddr == rTxAGC_A_Mcs15_Mcs12 && pHalData->rf_type == RF_1T1R)
- pHalData->pwrGroupCnt++;
- else if (RegAddr == rTxAGC_B_Mcs15_Mcs12 && pHalData->rf_type != RF_1T1R)
- pHalData->pwrGroupCnt++;
- }
-#endif
+ if (pDM_Odm->phy_reg_pg_version > 0)
+ PHY_StoreTxPowerByRateNew(pAdapter, Band, RfPath, RegAddr, BitMask, Data);
else
- RTW_INFO("Invalid PHY_REG_PG.txt version %d\n", pDM_Odm->PhyRegPgVersion);
-
-}
-
-#ifdef TX_POWER_BY_RATE_OLD
-VOID
-phy_ConvertTxPowerByRateByBase(
- IN u32 *pData,
- IN u8 Start,
- IN u8 End,
- IN u8 BaseValue
-) {
- s8 i = 0;
- u8 TempValue = 0;
- u32 TempData = 0;
-
- for (i = 3; i >= 0; --i) {
- if (i >= Start && i <= End) {
- /* Get the exact value */
- TempValue = (u8)(*pData >> (i * 8)) & 0xF;
- TempValue += ((u8)((*pData >> (i * 8 + 4)) & 0xF)) * 10;
-
- /* Change the value to a relative value */
- TempValue = (TempValue > BaseValue) ? TempValue - BaseValue : BaseValue - TempValue;
- } else
- TempValue = (u8)(*pData >> (i * 8)) & 0xFF;
-
- TempData <<= 8;
- TempData |= TempValue;
- }
-
- *pData = TempData;
-}
-
+ RTW_INFO("Invalid PHY_REG_PG.txt version %d\n", pDM_Odm->phy_reg_pg_version);
-VOID
-PHY_ConvertTxPowerByRateInDbmToRelativeValuesOld(
- IN PADAPTER pAdapter
-) {
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
- u8 base = 0;
-
- /* RTW_INFO("===>PHY_ConvertTxPowerByRateInDbmToRelativeValuesOld()\n" ); */
-
- /* CCK */
- base = PHY_GetTxPowerByRateBase(pAdapter, BAND_ON_2_4G, ODM_RF_PATH_A, RF_1TX, CCK);
- phy_ConvertTxPowerByRateByBase(
- &(pHalData->MCSTxPowerLevelOriginalOffset[0][6]), 1, 1, base);
- phy_ConvertTxPowerByRateByBase(
- &(pHalData->MCSTxPowerLevelOriginalOffset[0][7]), 1, 3, base);
-
- /* OFDM */
- base = PHY_GetTxPowerByRateBase(pAdapter, BAND_ON_2_4G, ODM_RF_PATH_A, RF_1TX, OFDM);
- phy_ConvertTxPowerByRateByBase(
- &(pHalData->MCSTxPowerLevelOriginalOffset[0][0]), 0, 3, base);
- phy_ConvertTxPowerByRateByBase(
- &(pHalData->MCSTxPowerLevelOriginalOffset[0][1]), 0, 3, base);
-
- /* HT MCS0~7 */
- base = PHY_GetTxPowerByRateBase(pAdapter, BAND_ON_2_4G, ODM_RF_PATH_A, RF_1TX, HT_MCS0_MCS7);
- phy_ConvertTxPowerByRateByBase(
- &(pHalData->MCSTxPowerLevelOriginalOffset[0][2]), 0, 3, base);
- phy_ConvertTxPowerByRateByBase(
- &(pHalData->MCSTxPowerLevelOriginalOffset[0][3]), 0, 3, base);
-
- /* HT MCS8~15 */
- base = PHY_GetTxPowerByRateBase(pAdapter, BAND_ON_2_4G, ODM_RF_PATH_A, RF_2TX, HT_MCS8_MCS15);
- phy_ConvertTxPowerByRateByBase(
- &(pHalData->MCSTxPowerLevelOriginalOffset[0][4]), 0, 3, base);
- phy_ConvertTxPowerByRateByBase(
- &(pHalData->MCSTxPowerLevelOriginalOffset[0][5]), 0, 3, base);
-
- /* CCK */
- base = PHY_GetTxPowerByRateBase(pAdapter, BAND_ON_2_4G, ODM_RF_PATH_B, RF_1TX, CCK);
- phy_ConvertTxPowerByRateByBase(
- &(pHalData->MCSTxPowerLevelOriginalOffset[0][14]), 1, 3, base);
- phy_ConvertTxPowerByRateByBase(
- &(pHalData->MCSTxPowerLevelOriginalOffset[0][15]), 0, 0, base);
-
- /* OFDM */
- base = PHY_GetTxPowerByRateBase(pAdapter, BAND_ON_2_4G, ODM_RF_PATH_B, RF_1TX, OFDM);
- phy_ConvertTxPowerByRateByBase(
- &(pHalData->MCSTxPowerLevelOriginalOffset[0][8]), 0, 3, base);
- phy_ConvertTxPowerByRateByBase(
- &(pHalData->MCSTxPowerLevelOriginalOffset[0][9]), 0, 3, base);
-
- /* HT MCS0~7 */
- base = PHY_GetTxPowerByRateBase(pAdapter, BAND_ON_2_4G, ODM_RF_PATH_B, RF_1TX, HT_MCS0_MCS7);
- phy_ConvertTxPowerByRateByBase(
- &(pHalData->MCSTxPowerLevelOriginalOffset[0][10]), 0, 3, base);
- phy_ConvertTxPowerByRateByBase(
- &(pHalData->MCSTxPowerLevelOriginalOffset[0][11]), 0, 3, base);
-
- /* HT MCS8~15 */
- base = PHY_GetTxPowerByRateBase(pAdapter, BAND_ON_2_4G, ODM_RF_PATH_B, RF_2TX, HT_MCS8_MCS15);
- phy_ConvertTxPowerByRateByBase(
- &(pHalData->MCSTxPowerLevelOriginalOffset[0][12]), 0, 3, base);
- phy_ConvertTxPowerByRateByBase(
- &(pHalData->MCSTxPowerLevelOriginalOffset[0][13]), 0, 3, base);
-
- /* RTW_INFO("<===PHY_ConvertTxPowerByRateInDbmToRelativeValuesOld()\n" ); */
}
-#endif /* TX_POWER_BY_RATE_OLD */
VOID
phy_ConvertTxPowerByRateInDbmToRelativeValues(
- IN PADAPTER pAdapter
-) {
+ IN PADAPTER pAdapter
+)
+{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
u8 base = 0, i = 0, value = 0,
- band = 0, path = 0, txNum = 0, index = 0,
- startIndex = 0, endIndex = 0;
- u8 cckRates[4] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M},
- ofdmRates[8] = {MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M},
- mcs0_7Rates[8] = {MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7},
- mcs8_15Rates[8] = {MGN_MCS8, MGN_MCS9, MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14, MGN_MCS15},
- mcs16_23Rates[8] = {MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19, MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23},
- vht1ssRates[10] = {MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4,
- MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9
- },
- vht2ssRates[10] = {MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4,
- MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9
- },
- vht3ssRates[10] = {MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4,
- MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9
- };
+ band = 0, path = 0, index = 0,
+ startIndex = 0, endIndex = 0;
+ u8 cckRates[4] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M},
+ ofdmRates[8] = {MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M},
+ mcs0_7Rates[8] = {MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7},
+ mcs8_15Rates[8] = {MGN_MCS8, MGN_MCS9, MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14, MGN_MCS15},
+ mcs16_23Rates[8] = {MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19, MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23},
+ vht1ssRates[10] = {MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4,
+ MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9},
+ vht2ssRates[10] = {MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4,
+ MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9},
+ vht3ssRates[10] = {MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4,
+ MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9};
/* RTW_INFO("===>PHY_ConvertTxPowerByRateInDbmToRelativeValues()\n" ); */
for (band = BAND_ON_2_4G; band <= BAND_ON_5G; ++band) {
- for (path = ODM_RF_PATH_A; path <= ODM_RF_PATH_D; ++path) {
- for (txNum = RF_1TX; txNum < RF_MAX_TX_NUM; ++txNum) {
- /* CCK */
- base = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, MGN_11M);
+ for (path = RF_PATH_A; path <= RF_PATH_D; ++path) {
+ /* CCK */
+ if (band == BAND_ON_2_4G) {
+ base = PHY_GetTxPowerByRateBase(pAdapter, band, path, CCK);
for (i = 0; i < sizeof(cckRates); ++i) {
- value = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, cckRates[i]);
- PHY_SetTxPowerByRate(pAdapter, band, path, txNum, cckRates[i], value - base);
+ value = PHY_GetTxPowerByRate(pAdapter, band, path, cckRates[i]);
+ PHY_SetTxPowerByRate(pAdapter, band, path, cckRates[i], value - base);
}
+ }
- /* OFDM */
- base = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, MGN_54M);
- for (i = 0; i < sizeof(ofdmRates); ++i) {
- value = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, ofdmRates[i]);
- PHY_SetTxPowerByRate(pAdapter, band, path, txNum, ofdmRates[i], value - base);
- }
+ /* OFDM */
+ base = PHY_GetTxPowerByRateBase(pAdapter, band, path, OFDM);
+ for (i = 0; i < sizeof(ofdmRates); ++i) {
+ value = PHY_GetTxPowerByRate(pAdapter, band, path, ofdmRates[i]);
+ PHY_SetTxPowerByRate(pAdapter, band, path, ofdmRates[i], value - base);
+ }
- /* HT MCS0~7 */
- base = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, MGN_MCS7);
- for (i = 0; i < sizeof(mcs0_7Rates); ++i) {
- value = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, mcs0_7Rates[i]);
- PHY_SetTxPowerByRate(pAdapter, band, path, txNum, mcs0_7Rates[i], value - base);
- }
+ /* HT MCS0~7 */
+ base = PHY_GetTxPowerByRateBase(pAdapter, band, path, HT_1SS);
+ for (i = 0; i < sizeof(mcs0_7Rates); ++i) {
+ value = PHY_GetTxPowerByRate(pAdapter, band, path, mcs0_7Rates[i]);
+ PHY_SetTxPowerByRate(pAdapter, band, path, mcs0_7Rates[i], value - base);
+ }
- /* HT MCS8~15 */
- base = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, MGN_MCS15);
- for (i = 0; i < sizeof(mcs8_15Rates); ++i) {
- value = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, mcs8_15Rates[i]);
- PHY_SetTxPowerByRate(pAdapter, band, path, txNum, mcs8_15Rates[i], value - base);
- }
+ /* HT MCS8~15 */
+ base = PHY_GetTxPowerByRateBase(pAdapter, band, path, HT_2SS);
+ for (i = 0; i < sizeof(mcs8_15Rates); ++i) {
+ value = PHY_GetTxPowerByRate(pAdapter, band, path, mcs8_15Rates[i]);
+ PHY_SetTxPowerByRate(pAdapter, band, path, mcs8_15Rates[i], value - base);
+ }
- /* HT MCS16~23 */
- base = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, MGN_MCS23);
- for (i = 0; i < sizeof(mcs16_23Rates); ++i) {
- value = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, mcs16_23Rates[i]);
- PHY_SetTxPowerByRate(pAdapter, band, path, txNum, mcs16_23Rates[i], value - base);
- }
+ /* HT MCS16~23 */
+ base = PHY_GetTxPowerByRateBase(pAdapter, band, path, HT_3SS);
+ for (i = 0; i < sizeof(mcs16_23Rates); ++i) {
+ value = PHY_GetTxPowerByRate(pAdapter, band, path, mcs16_23Rates[i]);
+ PHY_SetTxPowerByRate(pAdapter, band, path, mcs16_23Rates[i], value - base);
+ }
- /* VHT 1SS */
- base = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, MGN_VHT1SS_MCS7);
- for (i = 0; i < sizeof(vht1ssRates); ++i) {
- value = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, vht1ssRates[i]);
- PHY_SetTxPowerByRate(pAdapter, band, path, txNum, vht1ssRates[i], value - base);
- }
+ /* VHT 1SS */
+ base = PHY_GetTxPowerByRateBase(pAdapter, band, path, VHT_1SS);
+ for (i = 0; i < sizeof(vht1ssRates); ++i) {
+ value = PHY_GetTxPowerByRate(pAdapter, band, path, vht1ssRates[i]);
+ PHY_SetTxPowerByRate(pAdapter, band, path, vht1ssRates[i], value - base);
+ }
- /* VHT 2SS */
- base = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, MGN_VHT2SS_MCS7);
- for (i = 0; i < sizeof(vht2ssRates); ++i) {
- value = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, vht2ssRates[i]);
- PHY_SetTxPowerByRate(pAdapter, band, path, txNum, vht2ssRates[i], value - base);
- }
+ /* VHT 2SS */
+ base = PHY_GetTxPowerByRateBase(pAdapter, band, path, VHT_2SS);
+ for (i = 0; i < sizeof(vht2ssRates); ++i) {
+ value = PHY_GetTxPowerByRate(pAdapter, band, path, vht2ssRates[i]);
+ PHY_SetTxPowerByRate(pAdapter, band, path, vht2ssRates[i], value - base);
+ }
- /* VHT 3SS */
- base = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, MGN_VHT3SS_MCS7);
- for (i = 0; i < sizeof(vht3ssRates); ++i) {
- value = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, vht3ssRates[i]);
- PHY_SetTxPowerByRate(pAdapter, band, path, txNum, vht3ssRates[i], value - base);
- }
+ /* VHT 3SS */
+ base = PHY_GetTxPowerByRateBase(pAdapter, band, path, VHT_3SS);
+ for (i = 0; i < sizeof(vht3ssRates); ++i) {
+ value = PHY_GetTxPowerByRate(pAdapter, band, path, vht3ssRates[i]);
+ PHY_SetTxPowerByRate(pAdapter, band, path, vht3ssRates[i], value - base);
}
}
}
@@ -1063,91 +2125,48 @@ phy_ConvertTxPowerByRateInDbmToRelativeValues(
*/
VOID
PHY_TxPowerByRateConfiguration(
- IN PADAPTER pAdapter
-) {
+ IN PADAPTER pAdapter
+)
+{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+ phy_txpwr_by_rate_chk_for_path_dup(pAdapter);
phy_StoreTxPowerByRateBase(pAdapter);
phy_ConvertTxPowerByRateInDbmToRelativeValues(pAdapter);
}
VOID
-PHY_SetTxPowerIndexByRateSection(
- IN PADAPTER pAdapter,
- IN u8 RFPath,
- IN u8 Channel,
- IN u8 RateSection
-) {
+phy_set_tx_power_index_by_rate_section(
+ IN PADAPTER pAdapter,
+ IN enum rf_path RFPath,
+ IN u8 Channel,
+ IN u8 RateSection
+)
+{
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
- if (RateSection == CCK) {
- u8 cckRates[] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M};
- if (pHalData->CurrentBandType == BAND_ON_2_4G)
- PHY_SetTxPowerIndexByRateArray(pAdapter, RFPath, pHalData->CurrentChannelBW, Channel,
- cckRates, sizeof(cckRates) / sizeof(u8));
-
- } else if (RateSection == OFDM) {
- u8 ofdmRates[] = {MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M};
- PHY_SetTxPowerIndexByRateArray(pAdapter, RFPath, pHalData->CurrentChannelBW, Channel,
- ofdmRates, sizeof(ofdmRates) / sizeof(u8));
-
- } else if (RateSection == HT_MCS0_MCS7) {
- u8 htRates1T[] = {MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7};
- PHY_SetTxPowerIndexByRateArray(pAdapter, RFPath, pHalData->CurrentChannelBW, Channel,
- htRates1T, sizeof(htRates1T) / sizeof(u8));
-
- } else if (RateSection == HT_MCS8_MCS15) {
- u8 htRates2T[] = {MGN_MCS8, MGN_MCS9, MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14, MGN_MCS15};
- PHY_SetTxPowerIndexByRateArray(pAdapter, RFPath, pHalData->CurrentChannelBW, Channel,
- htRates2T, sizeof(htRates2T) / sizeof(u8));
-
- } else if (RateSection == HT_MCS16_MCS23) {
- u1Byte htRates3T[] = {MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19, MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23};
- PHY_SetTxPowerIndexByRateArray(pAdapter, RFPath, pHalData->CurrentChannelBW, Channel,
- htRates3T, sizeof(htRates3T) / sizeof(u1Byte));
-
- } else if (RateSection == HT_MCS24_MCS31) {
- u1Byte htRates4T[] = {MGN_MCS24, MGN_MCS25, MGN_MCS26, MGN_MCS27, MGN_MCS28, MGN_MCS29, MGN_MCS30, MGN_MCS31};
- PHY_SetTxPowerIndexByRateArray(pAdapter, RFPath, pHalData->CurrentChannelBW, Channel,
- htRates4T, sizeof(htRates4T) / sizeof(u1Byte));
-
- } else if (RateSection == VHT_1SSMCS0_1SSMCS9) {
- u8 vhtRates1T[] = {MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4,
- MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9
- };
- PHY_SetTxPowerIndexByRateArray(pAdapter, RFPath, pHalData->CurrentChannelBW, Channel,
- vhtRates1T, sizeof(vhtRates1T) / sizeof(u8));
-
- } else if (RateSection == VHT_2SSMCS0_2SSMCS9) {
- u8 vhtRates2T[] = {MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4,
- MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9
- };
-
- PHY_SetTxPowerIndexByRateArray(pAdapter, RFPath, pHalData->CurrentChannelBW, Channel,
- vhtRates2T, sizeof(vhtRates2T) / sizeof(u8));
- } else if (RateSection == VHT_3SSMCS0_3SSMCS9) {
- u1Byte vhtRates3T[] = {MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4,
- MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9
- };
-
- PHY_SetTxPowerIndexByRateArray(pAdapter, RFPath, pHalData->CurrentChannelBW, Channel,
- vhtRates3T, sizeof(vhtRates3T) / sizeof(u1Byte));
- } else if (RateSection == VHT_4SSMCS0_4SSMCS9) {
- u1Byte vhtRates4T[] = {MGN_VHT4SS_MCS0, MGN_VHT4SS_MCS1, MGN_VHT4SS_MCS2, MGN_VHT4SS_MCS3, MGN_VHT4SS_MCS4,
- MGN_VHT4SS_MCS5, MGN_VHT4SS_MCS6, MGN_VHT4SS_MCS7, MGN_VHT4SS_MCS8, MGN_VHT4SS_MCS9
- };
-
- PHY_SetTxPowerIndexByRateArray(pAdapter, RFPath, pHalData->CurrentChannelBW, Channel,
- vhtRates4T, sizeof(vhtRates4T) / sizeof(u1Byte));
- } else
- RTW_INFO("Invalid RateSection %d in %s", RateSection, __FUNCTION__);
+ if (RateSection >= RATE_SECTION_NUM) {
+ RTW_INFO("Invalid RateSection %d in %s", RateSection, __func__);
+ rtw_warn_on(1);
+ goto exit;
+ }
+
+ if (RateSection == CCK && pHalData->current_band_type != BAND_ON_2_4G)
+ goto exit;
+
+ PHY_SetTxPowerIndexByRateArray(pAdapter, RFPath, pHalData->current_channel_bw, Channel,
+ rates_by_sections[RateSection].rates, rates_by_sections[RateSection].rate_num);
+
+exit:
+ return;
}
BOOLEAN
phy_GetChnlIndex(
- IN u8 Channel,
- OUT u8 *ChannelIdx
-) {
+ IN u8 Channel,
+ OUT u8 *ChannelIdx
+)
+{
u8 i = 0;
BOOLEAN bIn24G = _TRUE;
@@ -1170,15 +2189,17 @@ phy_GetChnlIndex(
u8
PHY_GetTxPowerIndexBase(
- IN PADAPTER pAdapter,
- IN u8 RFPath,
- IN u8 Rate,
- IN CHANNEL_WIDTH BandWidth,
- IN u8 Channel,
- OUT PBOOLEAN bIn24G
-) {
+ IN PADAPTER pAdapter,
+ IN enum rf_path RFPath,
+ IN u8 Rate,
+ u8 ntx_idx,
+ IN enum channel_width BandWidth,
+ IN u8 Channel,
+ OUT PBOOLEAN bIn24G
+)
+{
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
- PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
+ struct dm_struct *pDM_Odm = &pHalData->odmpriv;
u8 i = 0; /* default set to 1S */
u8 txPower = 0;
u8 chnlIdx = (Channel - 1);
@@ -1190,159 +2211,179 @@ PHY_GetTxPowerIndexBase(
*bIn24G = phy_GetChnlIndex(Channel, &chnlIdx);
- /* RTW_INFO("[%s] Channel Index: %d\n", (*bIn24G?"2.4G":"5G"), chnlIdx); */
+ if (0)
+ RTW_INFO("[%s] Channel Index: %d\n", (*bIn24G ? "2.4G" : "5G"), chnlIdx);
- if (*bIn24G) { /* 3 ============================== 2.4 G ============================== */
- if (IS_CCK_RATE(Rate))
+ if (*bIn24G) {
+ if (IS_CCK_RATE(Rate)) {
+ /* CCK-nTX */
txPower = pHalData->Index24G_CCK_Base[RFPath][chnlIdx];
- else if (MGN_6M <= Rate)
- txPower = pHalData->Index24G_BW40_Base[RFPath][chnlIdx];
- else
- RTW_INFO("PHY_GetTxPowerIndexBase: INVALID Rate.\n");
+ txPower += pHalData->CCK_24G_Diff[RFPath][RF_1TX];
+ if (ntx_idx >= RF_2TX)
+ txPower += pHalData->CCK_24G_Diff[RFPath][RF_2TX];
+ if (ntx_idx >= RF_3TX)
+ txPower += pHalData->CCK_24G_Diff[RFPath][RF_3TX];
+ if (ntx_idx >= RF_4TX)
+ txPower += pHalData->CCK_24G_Diff[RFPath][RF_4TX];
+ goto exit;
+ }
- /* RTW_INFO("Base Tx power(RF-%c, Rate #%d, Channel Index %d) = 0x%X\n", */
- /* ((RFPath==0)?'A':'B'), Rate, chnlIdx, txPower); */
+ txPower = pHalData->Index24G_BW40_Base[RFPath][chnlIdx];
- /* OFDM-1T */
+ /* OFDM-nTX */
if ((MGN_6M <= Rate && Rate <= MGN_54M) && !IS_CCK_RATE(Rate)) {
- txPower += pHalData->OFDM_24G_Diff[RFPath][TX_1S];
- /* RTW_INFO("+PowerDiff 2.4G (RF-%c): (OFDM-1T) = (%d)\n", ((RFPath==0)?'A':'B'), pHalData->OFDM_24G_Diff[RFPath][TX_1S]); */
+ txPower += pHalData->OFDM_24G_Diff[RFPath][RF_1TX];
+ if (ntx_idx >= RF_2TX)
+ txPower += pHalData->OFDM_24G_Diff[RFPath][RF_2TX];
+ if (ntx_idx >= RF_3TX)
+ txPower += pHalData->OFDM_24G_Diff[RFPath][RF_3TX];
+ if (ntx_idx >= RF_4TX)
+ txPower += pHalData->OFDM_24G_Diff[RFPath][RF_4TX];
+ goto exit;
}
- /* BW20-1S, BW20-2S */
+
+ /* BW20-nS */
if (BandWidth == CHANNEL_WIDTH_20) {
if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
- txPower += pHalData->BW20_24G_Diff[RFPath][TX_1S];
+ txPower += pHalData->BW20_24G_Diff[RFPath][RF_1TX];
if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
- txPower += pHalData->BW20_24G_Diff[RFPath][TX_2S];
+ txPower += pHalData->BW20_24G_Diff[RFPath][RF_2TX];
if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
- txPower += pHalData->BW20_24G_Diff[RFPath][TX_3S];
+ txPower += pHalData->BW20_24G_Diff[RFPath][RF_3TX];
if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
- txPower += pHalData->BW20_24G_Diff[RFPath][TX_4S];
-
- /* RTW_INFO("+PowerDiff 2.4G (RF-%c): (BW20-1S, BW20-2S, BW20-3S, BW20-4S) = (%d, %d, %d, %d)\n", ((RFPath==0)?'A':(RFPath==1)?'B':(RFPath==2)?'C':'D'), */
- /* pHalData->BW20_24G_Diff[RFPath][TX_1S], pHalData->BW20_24G_Diff[RFPath][TX_2S], */
- /* pHalData->BW20_24G_Diff[RFPath][TX_3S], pHalData->BW20_24G_Diff[RFPath][TX_4S]); */
+ txPower += pHalData->BW20_24G_Diff[RFPath][RF_4TX];
+ goto exit;
}
- /* BW40-1S, BW40-2S */
- else if (BandWidth == CHANNEL_WIDTH_40) {
+
+ /* BW40-nS */
+ if (BandWidth == CHANNEL_WIDTH_40) {
if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
- txPower += pHalData->BW40_24G_Diff[RFPath][TX_1S];
+ txPower += pHalData->BW40_24G_Diff[RFPath][RF_1TX];
if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
- txPower += pHalData->BW40_24G_Diff[RFPath][TX_2S];
+ txPower += pHalData->BW40_24G_Diff[RFPath][RF_2TX];
if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
- txPower += pHalData->BW40_24G_Diff[RFPath][TX_3S];
+ txPower += pHalData->BW40_24G_Diff[RFPath][RF_3TX];
if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
- txPower += pHalData->BW40_24G_Diff[RFPath][TX_4S];
-
- /* RTW_INFO("+PowerDiff 2.4G (RF-%c): (BW40-1S, BW40-2S, BW40-3S, BW40-4S) = (%d, %d, %d, %d)\n", ((RFPath==0)?'A':(RFPath==1)?'B':(RFPath==2)?'C':'D'), */
- /* pHalData->BW40_24G_Diff[RFPath][TX_1S], pHalData->BW40_24G_Diff[RFPath][TX_2S], */
- /* pHalData->BW40_24G_Diff[RFPath][TX_3S], pHalData->BW40_24G_Diff[RFPath][TX_4S]); */
+ txPower += pHalData->BW40_24G_Diff[RFPath][RF_4TX];
+ goto exit;
}
+
/* Willis suggest adopt BW 40M power index while in BW 80 mode */
- else if (BandWidth == CHANNEL_WIDTH_80) {
+ if (BandWidth == CHANNEL_WIDTH_80) {
if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
- txPower += pHalData->BW40_24G_Diff[RFPath][TX_1S];
+ txPower += pHalData->BW40_24G_Diff[RFPath][RF_1TX];
if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
- txPower += pHalData->BW40_24G_Diff[RFPath][TX_2S];
+ txPower += pHalData->BW40_24G_Diff[RFPath][RF_2TX];
if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
- txPower += pHalData->BW40_24G_Diff[RFPath][TX_3S];
+ txPower += pHalData->BW40_24G_Diff[RFPath][RF_3TX];
if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
- txPower += pHalData->BW40_24G_Diff[RFPath][TX_4S];
-
- /* RTW_INFO("+PowerDiff 2.4G (RF-%c): (BW40-1S, BW40-2S, BW40-3S, BW40-4T) = (%d, %d, %d, %d) P.S. Current is in BW 80MHz\n", ((RFPath==0)?'A':(RFPath==1)?'B':(RFPath==2)?'C':'D'), */
- /* pHalData->BW40_24G_Diff[RFPath][TX_1S], pHalData->BW40_24G_Diff[RFPath][TX_2S], */
- /* pHalData->BW40_24G_Diff[RFPath][TX_3S], pHalData->BW40_24G_Diff[RFPath][TX_4S]); */
+ txPower += pHalData->BW40_24G_Diff[RFPath][RF_4TX];
+ goto exit;
}
- } else { /* 3 ============================== 5 G ============================== */
- if (MGN_6M <= Rate)
+ }
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+ else {
+ if (Rate >= MGN_6M)
txPower = pHalData->Index5G_BW40_Base[RFPath][chnlIdx];
- else
- RTW_INFO("===> mpt_ProQueryCalTxPower_Jaguar: INVALID Rate.\n");
-
- /* RTW_INFO("Base Tx power(RF-%c, Rate #%d, Channel Index %d) = 0x%X\n", */
- /* ((RFPath==0)?'A':'B'), Rate, chnlIdx, txPower); */
+ else {
+ RTW_INFO("===>PHY_GetTxPowerIndexBase: INVALID Rate(0x%02x).\n", Rate);
+ goto exit;
+ }
- /* OFDM-1T */
+ /* OFDM-nTX */
if ((MGN_6M <= Rate && Rate <= MGN_54M) && !IS_CCK_RATE(Rate)) {
- txPower += pHalData->OFDM_5G_Diff[RFPath][TX_1S];
- /* RTW_INFO("+PowerDiff 5G (RF-%c): (OFDM-1T) = (%d)\n", ((RFPath==0)?'A':'B'), pHalData->OFDM_5G_Diff[RFPath][TX_1S]); */
+ txPower += pHalData->OFDM_5G_Diff[RFPath][RF_1TX];
+ if (ntx_idx >= RF_2TX)
+ txPower += pHalData->OFDM_5G_Diff[RFPath][RF_2TX];
+ if (ntx_idx >= RF_3TX)
+ txPower += pHalData->OFDM_5G_Diff[RFPath][RF_3TX];
+ if (ntx_idx >= RF_4TX)
+ txPower += pHalData->OFDM_5G_Diff[RFPath][RF_4TX];
+ goto exit;
}
- /* BW20-1S, BW20-2S */
+ /* BW20-nS */
if (BandWidth == CHANNEL_WIDTH_20) {
if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
- txPower += pHalData->BW20_5G_Diff[RFPath][TX_1S];
+ txPower += pHalData->BW20_5G_Diff[RFPath][RF_1TX];
if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
- txPower += pHalData->BW20_5G_Diff[RFPath][TX_2S];
+ txPower += pHalData->BW20_5G_Diff[RFPath][RF_2TX];
if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
- txPower += pHalData->BW20_5G_Diff[RFPath][TX_3S];
+ txPower += pHalData->BW20_5G_Diff[RFPath][RF_3TX];
if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
- txPower += pHalData->BW20_5G_Diff[RFPath][TX_4S];
-
- /* RTW_INFO("+PowerDiff 5G (RF-%c): (BW20-1S, BW20-2S, BW20-3S, BW20-4S) = (%d, %d, %d, %d)\n", ((RFPath==0)?'A':(RFPath==1)?'B':(RFPath==2)?'C':'D'), */
- /* pHalData->BW20_5G_Diff[RFPath][TX_1S], pHalData->BW20_5G_Diff[RFPath][TX_2S], */
- /* pHalData->BW20_5G_Diff[RFPath][TX_3S], pHalData->BW20_5G_Diff[RFPath][TX_4S]); */
+ txPower += pHalData->BW20_5G_Diff[RFPath][RF_4TX];
+ goto exit;
}
- /* BW40-1S, BW40-2S */
- else if (BandWidth == CHANNEL_WIDTH_40) {
+
+ /* BW40-nS */
+ if (BandWidth == CHANNEL_WIDTH_40) {
if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
- txPower += pHalData->BW40_5G_Diff[RFPath][TX_1S];
+ txPower += pHalData->BW40_5G_Diff[RFPath][RF_1TX];
if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
- txPower += pHalData->BW40_5G_Diff[RFPath][TX_2S];
+ txPower += pHalData->BW40_5G_Diff[RFPath][RF_2TX];
if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
- txPower += pHalData->BW40_5G_Diff[RFPath][TX_3S];
+ txPower += pHalData->BW40_5G_Diff[RFPath][RF_3TX];
if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
- txPower += pHalData->BW40_5G_Diff[RFPath][TX_4S];
-
- /* RTW_INFO("+PowerDiff 5G(RF-%c): (BW40-1S, BW40-2S) = (%d, %d, %d, %d)\n", ((RFPath==0)?'A':(RFPath==1)?'B':(RFPath==2)?'C':'D'), */
- /* pHalData->BW40_5G_Diff[RFPath][TX_1S], pHalData->BW40_5G_Diff[RFPath][TX_2S], */
- /* pHalData->BW40_5G_Diff[RFPath][TX_3S], pHalData->BW40_5G_Diff[RFPath][TX_4S]); */
+ txPower += pHalData->BW40_5G_Diff[RFPath][RF_4TX];
+ goto exit;
}
- /* BW80-1S, BW80-2S */
- else if (BandWidth == CHANNEL_WIDTH_80) {
- /* <20121220, Kordan> Get the index of array "Index5G_BW80_Base". */
- for (i = 0; i < CENTER_CH_5G_80M_NUM; ++i)
- if (center_ch_5g_80m[i] == Channel)
+
+ /* BW80-nS */
+ if (BandWidth == CHANNEL_WIDTH_80) {
+ /* get 80MHz cch index */
+ for (i = 0; i < CENTER_CH_5G_80M_NUM; ++i) {
+ if (center_ch_5g_80m[i] == Channel) {
chnlIdx = i;
+ break;
+ }
+ }
+ if (i >= CENTER_CH_5G_80M_NUM) {
+ rtw_warn_on(1);
+ txPower = 0;
+ goto exit;
+ }
txPower = pHalData->Index5G_BW80_Base[RFPath][chnlIdx];
if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
- txPower += + pHalData->BW80_5G_Diff[RFPath][TX_1S];
+ txPower += + pHalData->BW80_5G_Diff[RFPath][RF_1TX];
if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
- txPower += pHalData->BW80_5G_Diff[RFPath][TX_2S];
+ txPower += pHalData->BW80_5G_Diff[RFPath][RF_2TX];
if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
- txPower += pHalData->BW80_5G_Diff[RFPath][TX_3S];
+ txPower += pHalData->BW80_5G_Diff[RFPath][RF_3TX];
if ((MGN_MCS23 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
- txPower += pHalData->BW80_5G_Diff[RFPath][TX_4S];
-
- /* RTW_INFO("+PowerDiff 5G(RF-%c): (BW80-1S, BW80-2S, BW80-3S, BW80-4S) = (%d, %d, %d, %d)\n",((RFPath==0)?'A':(RFPath==1)?'B':(RFPath==2)?'C':'D'), */
- /* pHalData->BW80_5G_Diff[RFPath][TX_1S], pHalData->BW80_5G_Diff[RFPath][TX_2S], */
- /* pHalData->BW80_5G_Diff[RFPath][TX_3S], pHalData->BW80_5G_Diff[RFPath][TX_4S]); */
+ txPower += pHalData->BW80_5G_Diff[RFPath][RF_4TX];
+ goto exit;
}
+
+ /* TODO: BW160-nS */
+ rtw_warn_on(1);
}
+#endif /* CONFIG_IEEE80211_BAND_5GHZ */
+exit:
return txPower;
}
s8
PHY_GetTxPowerTrackingOffset(
- PADAPTER pAdapter,
- u8 RFPath,
- u8 Rate
-) {
+ PADAPTER pAdapter,
+ enum rf_path RFPath,
+ u8 Rate
+)
+{
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
- PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
+ struct dm_struct *pDM_Odm = &pHalData->odmpriv;
s8 offset = 0;
- if (pDM_Odm->RFCalibrateInfo.TxPowerTrackControl == _FALSE)
+ if (pDM_Odm->rf_calibrate_info.txpowertrack_control == _FALSE)
return offset;
if ((Rate == MGN_1M) || (Rate == MGN_2M) || (Rate == MGN_5_5M) || (Rate == MGN_11M)) {
- offset = pDM_Odm->RFCalibrateInfo.Remnant_CCKSwingIdx;
+ offset = pDM_Odm->rf_calibrate_info.remnant_cck_swing_idx;
/*RTW_INFO("+Remnant_CCKSwingIdx = 0x%x\n", RFPath, Rate, pRFCalibrateInfo->Remnant_CCKSwingIdx);*/
} else {
- offset = pDM_Odm->RFCalibrateInfo.Remnant_OFDMSwingIdx[RFPath];
+ offset = pDM_Odm->rf_calibrate_info.remnant_ofdm_swing_idx[RFPath];
/*RTW_INFO("+Remanant_OFDMSwingIdx[RFPath %u][Rate 0x%x] = 0x%x\n", RFPath, Rate, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath]); */
}
@@ -1350,10 +2391,12 @@ PHY_GetTxPowerTrackingOffset(
return offset;
}
+/*The same as MRateToHwRate in hal_com.c*/
u8
PHY_GetRateIndexOfTxPowerByRate(
- IN u8 Rate
-) {
+ IN u8 Rate
+)
+{
u8 index = 0;
switch (Rate) {
case MGN_1M:
@@ -1618,12 +2661,12 @@ PHY_GetRateIndexOfTxPowerByRate(
s8
_PHY_GetTxPowerByRate(
- IN PADAPTER pAdapter,
- IN u8 Band,
- IN u8 RFPath,
- IN u8 TxNum,
- IN u8 Rate
-) {
+ IN PADAPTER pAdapter,
+ IN u8 Band,
+ IN enum rf_path RFPath,
+ IN u8 Rate
+)
+{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
s8 value = 0;
u8 rateIndex = PHY_GetRateIndexOfTxPowerByRate(Rate);
@@ -1632,20 +2675,16 @@ _PHY_GetTxPowerByRate(
RTW_INFO("Invalid band %d in %s\n", Band, __func__);
goto exit;
}
- if (RFPath > ODM_RF_PATH_D) {
+ if (RFPath > RF_PATH_D) {
RTW_INFO("Invalid RfPath %d in %s\n", RFPath, __func__);
goto exit;
}
- if (TxNum >= RF_MAX_TX_NUM) {
- RTW_INFO("Invalid TxNum %d in %s\n", TxNum, __func__);
- goto exit;
- }
if (rateIndex >= TX_PWR_BY_RATE_NUM_RATE) {
RTW_INFO("Invalid RateIndex %d in %s\n", rateIndex, __func__);
goto exit;
}
- value = pHalData->TxPwrByRateOffset[Band][RFPath][TxNum][rateIndex];
+ value = pHalData->TxPwrByRateOffset[Band][RFPath][rateIndex];
exit:
return value;
@@ -1654,69 +2693,27 @@ _PHY_GetTxPowerByRate(
s8
PHY_GetTxPowerByRate(
- IN PADAPTER pAdapter,
- IN u8 Band,
- IN u8 RFPath,
- IN u8 TxNum,
- IN u8 Rate
-) {
+ IN PADAPTER pAdapter,
+ IN u8 Band,
+ IN enum rf_path RFPath,
+ IN u8 Rate
+)
+{
if (!phy_is_tx_power_by_rate_needed(pAdapter))
return 0;
- return _PHY_GetTxPowerByRate(pAdapter, Band, RFPath, TxNum, Rate);
-}
-
-#ifdef CONFIG_PHYDM_POWERTRACK_BY_TSSI
-s8
-PHY_GetTxPowerByRateOriginal(
- IN PADAPTER pAdapter,
- IN u8 Band,
- IN u8 RFPath,
- IN u8 TxNum,
- IN u8 Rate
-) {
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
- s8 value = 0, limit = 0;
- u8 rateIndex = PHY_GetRateIndexOfTxPowerByRate(Rate);
-
- if ((pAdapter->registrypriv.RegEnableTxPowerByRate == 2 && pHalData->EEPROMRegulatory == 2) ||
- pAdapter->registrypriv.RegEnableTxPowerByRate == 0)
- return 0;
-
- if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {
- DBG_871X("Invalid band %d in %s\n", Band, __func__);
- return value;
- }
- if (RFPath > ODM_RF_PATH_D) {
- DBG_871X("Invalid RfPath %d in %s\n", RFPath, __func__);
- return value;
- }
- if (TxNum >= RF_MAX_TX_NUM) {
- DBG_871X("Invalid TxNum %d in %s\n", TxNum, __func__);
- return value;
- }
- if (rateIndex >= TX_PWR_BY_RATE_NUM_RATE) {
- DBG_871X("Invalid RateIndex %d in %s\n", rateIndex, __func__);
- return value;
- }
-
- value = pHalData->TxPwrByRate[Band][RFPath][TxNum][rateIndex];
-
- return value;
+ return _PHY_GetTxPowerByRate(pAdapter, Band, RFPath, Rate);
}
-#endif
-
-
VOID
PHY_SetTxPowerByRate(
- IN PADAPTER pAdapter,
- IN u8 Band,
- IN u8 RFPath,
- IN u8 TxNum,
- IN u8 Rate,
- IN s8 Value
-) {
+ IN PADAPTER pAdapter,
+ IN u8 Band,
+ IN enum rf_path RFPath,
+ IN u8 Rate,
+ IN s8 Value
+)
+{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
u8 rateIndex = PHY_GetRateIndexOfTxPowerByRate(Rate);
@@ -1724,704 +2721,522 @@ PHY_SetTxPowerByRate(
RTW_INFO("Invalid band %d in %s\n", Band, __FUNCTION__);
return;
}
- if (RFPath > ODM_RF_PATH_D) {
+ if (RFPath > RF_PATH_D) {
RTW_INFO("Invalid RfPath %d in %s\n", RFPath, __FUNCTION__);
return;
}
- if (TxNum >= RF_MAX_TX_NUM) {
- RTW_INFO("Invalid TxNum %d in %s\n", TxNum, __FUNCTION__);
- return;
- }
if (rateIndex >= TX_PWR_BY_RATE_NUM_RATE) {
RTW_INFO("Invalid RateIndex %d in %s\n", rateIndex, __FUNCTION__);
return;
}
- pHalData->TxPwrByRateOffset[Band][RFPath][TxNum][rateIndex] = Value;
+ pHalData->TxPwrByRateOffset[Band][RFPath][rateIndex] = Value;
}
VOID
-PHY_SetTxPowerLevelByPath(
- IN PADAPTER Adapter,
- IN u8 channel,
- IN u8 path
-) {
+phy_set_tx_power_level_by_path(
+ IN PADAPTER Adapter,
+ IN u8 channel,
+ IN u8 path
+)
+{
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
- BOOLEAN bIsIn24G = (pHalData->CurrentBandType == BAND_ON_2_4G);
+ BOOLEAN bIsIn24G = (pHalData->current_band_type == BAND_ON_2_4G);
/* if ( pMgntInfo->RegNByteAccess == 0 ) */
{
if (bIsIn24G)
- PHY_SetTxPowerIndexByRateSection(Adapter, path, channel, CCK);
-
- PHY_SetTxPowerIndexByRateSection(Adapter, path, channel, OFDM);
- PHY_SetTxPowerIndexByRateSection(Adapter, path, channel, HT_MCS0_MCS7);
-
- if (IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter))
- PHY_SetTxPowerIndexByRateSection(Adapter, path, channel, VHT_1SSMCS0_1SSMCS9);
-
- if (pHalData->NumTotalRFPath >= 2) {
- PHY_SetTxPowerIndexByRateSection(Adapter, path, channel, HT_MCS8_MCS15);
+ phy_set_tx_power_index_by_rate_section(Adapter, path, channel, CCK);
- if (IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter))
- PHY_SetTxPowerIndexByRateSection(Adapter, path, channel, VHT_2SSMCS0_2SSMCS9);
-
- if (IS_HARDWARE_TYPE_8814A(Adapter)) {
- PHY_SetTxPowerIndexByRateSection(Adapter, path, channel, HT_MCS16_MCS23);
- PHY_SetTxPowerIndexByRateSection(Adapter, path, channel, VHT_3SSMCS0_3SSMCS9);
- }
- }
- }
-}
-
-VOID
-PHY_SetTxPowerIndexByRateArray(
- IN PADAPTER pAdapter,
- IN u8 RFPath,
- IN CHANNEL_WIDTH BandWidth,
- IN u8 Channel,
- IN u8 *Rates,
- IN u8 RateArraySize
-) {
- u32 powerIndex = 0;
- int i = 0;
-
- for (i = 0; i < RateArraySize; ++i) {
- powerIndex = PHY_GetTxPowerIndex(pAdapter, RFPath, Rates[i], BandWidth, Channel);
- PHY_SetTxPowerIndex(pAdapter, powerIndex, RFPath, Rates[i]);
- }
-}
-
-s8
-phy_GetWorldWideLimit(
- s8 *LimitTable
-) {
- s8 min = LimitTable[0];
- u8 i = 0;
-
- for (i = 0; i < MAX_REGULATION_NUM; ++i) {
- if (LimitTable[i] < min)
- min = LimitTable[i];
- }
-
- return min;
-}
-
-s8
-phy_GetChannelIndexOfTxPowerLimit(
- IN u8 Band,
- IN u8 Channel
-) {
- s8 channelIndex = -1;
- u8 i = 0;
-
- if (Band == BAND_ON_2_4G)
- channelIndex = Channel - 1;
- else if (Band == BAND_ON_5G) {
- for (i = 0; i < CENTER_CH_5G_ALL_NUM; ++i) {
- if (center_ch_5g_all[i] == Channel)
- channelIndex = i;
- }
- } else
- RTW_PRINT("Invalid Band %d in %s\n", Band, __func__);
-
- if (channelIndex == -1)
- RTW_PRINT("Invalid Channel %d of Band %d in %s\n", Channel, Band, __func__);
-
- return channelIndex;
-}
-
-s8
-PHY_GetTxPowerLimit(
- IN PADAPTER Adapter,
- IN u32 RegPwrTblSel,
- IN BAND_TYPE Band,
- IN CHANNEL_WIDTH Bandwidth,
- IN u8 RfPath,
- IN u8 DataRate,
- IN u8 Channel
-) {
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
- s16 band = -1, regulation = -1, bandwidth = -1,
- rateSection = -1, channel = -1;
- s8 powerLimit = MAX_POWER_INDEX;
-
- if ((Adapter->registrypriv.RegEnableTxPowerLimit == 2 && pHalData->EEPROMRegulatory != 1) ||
- Adapter->registrypriv.RegEnableTxPowerLimit == 0)
- return MAX_POWER_INDEX;
-
- switch (RegPwrTblSel) {
- case 1:
- regulation = TXPWR_LMT_ETSI;
- break;
- case 2:
- regulation = TXPWR_LMT_MKK;
- break;
- case 3:
- regulation = TXPWR_LMT_FCC;
- break;
- case 4:
- regulation = TXPWR_LMT_WW;
- break;
- default:
- regulation = (Band == BAND_ON_2_4G) ? pHalData->Regulation2_4G : pHalData->Regulation5G;
- break;
- }
-
- /* RTW_INFO("pMgntInfo->RegPwrTblSel %d, final regulation %d\n", Adapter->registrypriv.RegPwrTblSel, regulation ); */
-
-
- if (Band == BAND_ON_2_4G)
- band = 0;
- else if (Band == BAND_ON_5G)
- band = 1;
-
- if (Bandwidth == CHANNEL_WIDTH_20)
- bandwidth = 0;
- else if (Bandwidth == CHANNEL_WIDTH_40)
- bandwidth = 1;
- else if (Bandwidth == CHANNEL_WIDTH_80)
- bandwidth = 2;
- else if (Bandwidth == CHANNEL_WIDTH_160)
- bandwidth = 3;
-
- switch (DataRate) {
- case MGN_1M:
- case MGN_2M:
- case MGN_5_5M:
- case MGN_11M:
- rateSection = 0;
- break;
-
- case MGN_6M:
- case MGN_9M:
- case MGN_12M:
- case MGN_18M:
- case MGN_24M:
- case MGN_36M:
- case MGN_48M:
- case MGN_54M:
- rateSection = 1;
- break;
-
- case MGN_MCS0:
- case MGN_MCS1:
- case MGN_MCS2:
- case MGN_MCS3:
- case MGN_MCS4:
- case MGN_MCS5:
- case MGN_MCS6:
- case MGN_MCS7:
- rateSection = 2;
- break;
-
- case MGN_MCS8:
- case MGN_MCS9:
- case MGN_MCS10:
- case MGN_MCS11:
- case MGN_MCS12:
- case MGN_MCS13:
- case MGN_MCS14:
- case MGN_MCS15:
- rateSection = 3;
- break;
-
- case MGN_MCS16:
- case MGN_MCS17:
- case MGN_MCS18:
- case MGN_MCS19:
- case MGN_MCS20:
- case MGN_MCS21:
- case MGN_MCS22:
- case MGN_MCS23:
- rateSection = 4;
- break;
-
- case MGN_MCS24:
- case MGN_MCS25:
- case MGN_MCS26:
- case MGN_MCS27:
- case MGN_MCS28:
- case MGN_MCS29:
- case MGN_MCS30:
- case MGN_MCS31:
- rateSection = 5;
- break;
-
- case MGN_VHT1SS_MCS0:
- case MGN_VHT1SS_MCS1:
- case MGN_VHT1SS_MCS2:
- case MGN_VHT1SS_MCS3:
- case MGN_VHT1SS_MCS4:
- case MGN_VHT1SS_MCS5:
- case MGN_VHT1SS_MCS6:
- case MGN_VHT1SS_MCS7:
- case MGN_VHT1SS_MCS8:
- case MGN_VHT1SS_MCS9:
- rateSection = 6;
- break;
+ phy_set_tx_power_index_by_rate_section(Adapter, path, channel, OFDM);
+ phy_set_tx_power_index_by_rate_section(Adapter, path, channel, HT_MCS0_MCS7);
- case MGN_VHT2SS_MCS0:
- case MGN_VHT2SS_MCS1:
- case MGN_VHT2SS_MCS2:
- case MGN_VHT2SS_MCS3:
- case MGN_VHT2SS_MCS4:
- case MGN_VHT2SS_MCS5:
- case MGN_VHT2SS_MCS6:
- case MGN_VHT2SS_MCS7:
- case MGN_VHT2SS_MCS8:
- case MGN_VHT2SS_MCS9:
- rateSection = 7;
- break;
+ if (IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter))
+ phy_set_tx_power_index_by_rate_section(Adapter, path, channel, VHT_1SSMCS0_1SSMCS9);
- case MGN_VHT3SS_MCS0:
- case MGN_VHT3SS_MCS1:
- case MGN_VHT3SS_MCS2:
- case MGN_VHT3SS_MCS3:
- case MGN_VHT3SS_MCS4:
- case MGN_VHT3SS_MCS5:
- case MGN_VHT3SS_MCS6:
- case MGN_VHT3SS_MCS7:
- case MGN_VHT3SS_MCS8:
- case MGN_VHT3SS_MCS9:
- rateSection = 8;
- break;
+ if (pHalData->NumTotalRFPath >= 2) {
+ phy_set_tx_power_index_by_rate_section(Adapter, path, channel, HT_MCS8_MCS15);
- case MGN_VHT4SS_MCS0:
- case MGN_VHT4SS_MCS1:
- case MGN_VHT4SS_MCS2:
- case MGN_VHT4SS_MCS3:
- case MGN_VHT4SS_MCS4:
- case MGN_VHT4SS_MCS5:
- case MGN_VHT4SS_MCS6:
- case MGN_VHT4SS_MCS7:
- case MGN_VHT4SS_MCS8:
- case MGN_VHT4SS_MCS9:
- rateSection = 9;
- break;
+ if (IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter))
+ phy_set_tx_power_index_by_rate_section(Adapter, path, channel, VHT_2SSMCS0_2SSMCS9);
- default:
- RTW_INFO("Wrong rate 0x%x\n", DataRate);
- break;
+ if (IS_HARDWARE_TYPE_8814A(Adapter)) {
+ phy_set_tx_power_index_by_rate_section(Adapter, path, channel, HT_MCS16_MCS23);
+ phy_set_tx_power_index_by_rate_section(Adapter, path, channel, VHT_3SSMCS0_3SSMCS9);
+ }
+ }
}
+}
+
+#ifndef DBG_TX_POWER_IDX
+#define DBG_TX_POWER_IDX 0
+#endif
+
+VOID
+PHY_SetTxPowerIndexByRateArray(
+ IN PADAPTER pAdapter,
+ IN enum rf_path RFPath,
+ IN enum channel_width BandWidth,
+ IN u8 Channel,
+ IN u8 *Rates,
+ IN u8 RateArraySize
+)
+{
+ u32 powerIndex = 0;
+ int i = 0;
- if (Band == BAND_ON_5G && rateSection == 0)
- RTW_INFO("Wrong rate 0x%x: No CCK in 5G Band\n", DataRate);
+ for (i = 0; i < RateArraySize; ++i) {
+#if DBG_TX_POWER_IDX
+ struct txpwr_idx_comp tic;
- /* workaround for wrong index combination to obtain tx power limit, */
- /* OFDM only exists in BW 20M */
- if (rateSection == 1)
- bandwidth = 0;
+ powerIndex = rtw_hal_get_tx_power_index(pAdapter, RFPath, Rates[i], BandWidth, Channel, &tic);
+ RTW_INFO("TXPWR: [%c][%s]ch:%u, %s %uT, pwr_idx:%u = %u + (%d=%d:%d) + (%d) + (%d)\n"
+ , rf_path_char(RFPath), ch_width_str(BandWidth), Channel, MGN_RATE_STR(Rates[i]), tic.ntx_idx + 1
+ , powerIndex, tic.base, (tic.by_rate > tic.limit ? tic.limit : tic.by_rate), tic.by_rate, tic.limit, tic.tpt, tic.ebias);
+#else
+ powerIndex = phy_get_tx_power_index(pAdapter, RFPath, Rates[i], BandWidth, Channel);
+#endif
+ PHY_SetTxPowerIndex(pAdapter, powerIndex, RFPath, Rates[i]);
+ }
+}
- /* workaround for wrong index combination to obtain tx power limit, */
- /* CCK table will only be given in BW 20M */
- if (rateSection == 0)
- bandwidth = 0;
+#ifdef CONFIG_TXPWR_LIMIT
+const char *const _txpwr_lmt_rs_str[] = {
+ "CCK",
+ "OFDM",
+ "HT",
+ "VHT",
+ "UNKNOWN",
+};
- /* workaround for wrong indxe combination to obtain tx power limit, */
- /* HT on 80M will reference to HT on 40M */
- if ((rateSection == 2 || rateSection == 3) && Band == BAND_ON_5G && bandwidth == 2)
- bandwidth = 1;
+static s8
+phy_GetChannelIndexOfTxPowerLimit(
+ IN u8 Band,
+ IN u8 Channel
+)
+{
+ s8 channelIndex = -1;
+ u8 i = 0;
if (Band == BAND_ON_2_4G)
- channel = phy_GetChannelIndexOfTxPowerLimit(BAND_ON_2_4G, Channel);
- else if (Band == BAND_ON_5G)
- channel = phy_GetChannelIndexOfTxPowerLimit(BAND_ON_5G, Channel);
- else if (Band == BAND_ON_BOTH) {
- /* BAND_ON_BOTH don't care temporarily */
- }
+ channelIndex = Channel - 1;
+ else if (Band == BAND_ON_5G) {
+ for (i = 0; i < CENTER_CH_5G_ALL_NUM; ++i) {
+ if (center_ch_5g_all[i] == Channel)
+ channelIndex = i;
+ }
+ } else
+ RTW_PRINT("Invalid Band %d in %s\n", Band, __func__);
+
+ if (channelIndex == -1)
+ RTW_PRINT("Invalid Channel %d of Band %d in %s\n", Channel, Band, __func__);
+
+ return channelIndex;
+}
- if (band == -1 || regulation == -1 || bandwidth == -1 ||
- rateSection == -1 || channel == -1) {
- /* RTW_INFO("Wrong index value to access power limit table [band %d][regulation %d][bandwidth %d][rf_path %d][rate_section %d][chnlGroup %d]\n", */
- /* band, regulation, bandwidth, RfPath, rateSection, channelGroup ); */
+/*
+* return txpwr limit absolute value
+* MAX_POWER_INDEX is returned when NO limit
+*/
+s8 phy_get_txpwr_lmt_abs(
+ IN PADAPTER Adapter,
+ IN const char *regd_name,
+ IN BAND_TYPE Band,
+ IN enum channel_width bw,
+ u8 tlrs,
+ u8 ntx_idx,
+ u8 cch,
+ u8 lock
+)
+{
+ struct dvobj_priv *dvobj = adapter_to_dvobj(Adapter);
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(Adapter);
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(Adapter);
+ struct txpwr_lmt_ent *ent = NULL;
+ _irqL irqL;
+ _list *cur, *head;
+ s8 ch_idx;
+ u8 is_ww_regd = 0;
+ s8 lmt = MAX_POWER_INDEX;
+
+ if ((Adapter->registrypriv.RegEnableTxPowerLimit == 2 && hal_data->EEPROMRegulatory != 1) ||
+ Adapter->registrypriv.RegEnableTxPowerLimit == 0)
+ goto exit;
- return MAX_POWER_INDEX;
+ if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) {
+ RTW_ERR("%s invalid band:%u\n", __func__, Band);
+ rtw_warn_on(1);
+ goto exit;
}
- if (Band == BAND_ON_2_4G) {
- s8 limits[10] = {0};
- u8 i = 0;
- if (bandwidth >= MAX_2_4G_BANDWIDTH_NUM)
- bandwidth = MAX_2_4G_BANDWIDTH_NUM - 1;
- for (i = 0; i < MAX_REGULATION_NUM; ++i)
- limits[i] = pHalData->TxPwrLimit_2_4G[i][bandwidth][rateSection][channel][RfPath];
-
- powerLimit = (regulation == TXPWR_LMT_WW) ? phy_GetWorldWideLimit(limits) :
- pHalData->TxPwrLimit_2_4G[regulation][bandwidth][rateSection][channel][RfPath];
-
- } else if (Band == BAND_ON_5G) {
- s8 limits[10] = {0};
- u8 i = 0;
- for (i = 0; i < MAX_REGULATION_NUM; ++i)
- limits[i] = pHalData->TxPwrLimit_5G[i][bandwidth][rateSection][channel][RfPath];
-
- powerLimit = (regulation == TXPWR_LMT_WW) ? phy_GetWorldWideLimit(limits) :
- pHalData->TxPwrLimit_5G[regulation][bandwidth][rateSection][channel][RfPath];
- } else
- RTW_INFO("No power limit table of the specified band\n");
-
- /* combine 5G VHT & HT rate */
- /* 5G 20M and 40M HT and VHT can cross reference */
- /*
- if ( Band == BAND_ON_5G && powerLimit == MAX_POWER_INDEX ) {
- if ( bandwidth == 0 || bandwidth == 1 ) {
- RT_TRACE( COMP_INIT, DBG_LOUD, ( "No power limit table of the specified band %d, bandwidth %d, ratesection %d, rf path %d\n",
- band, bandwidth, rateSection, RfPath ) );
- if ( rateSection == 2 )
- powerLimit = pHalData->TxPwrLimit_5G[regulation]
- [bandwidth][4][channelGroup][RfPath];
- else if ( rateSection == 4 )
- powerLimit = pHalData->TxPwrLimit_5G[regulation]
- [bandwidth][2][channelGroup][RfPath];
- else if ( rateSection == 3 )
- powerLimit = pHalData->TxPwrLimit_5G[regulation]
- [bandwidth][5][channelGroup][RfPath];
- else if ( rateSection == 5 )
- powerLimit = pHalData->TxPwrLimit_5G[regulation]
- [bandwidth][3][channelGroup][RfPath];
- }
+ if (Band == BAND_ON_5G && tlrs == TXPWR_LMT_RS_CCK) {
+ RTW_ERR("5G has no CCK\n");
+ goto exit;
}
- */
- /* RTW_INFO("TxPwrLmt[Regulation %d][Band %d][BW %d][RFPath %d][Rate 0x%x][Chnl %d] = %d\n", */
- /* regulation, pHalData->CurrentBandType, Bandwidth, RfPath, DataRate, Channel, powerLimit); */
- return powerLimit;
-}
-#ifdef CONFIG_PHYDM_POWERTRACK_BY_TSSI
-s8
-PHY_GetTxPowerLimitOriginal(
- IN PADAPTER Adapter,
- IN u32 RegPwrTblSel,
- IN BAND_TYPE Band,
- IN CHANNEL_WIDTH Bandwidth,
- IN u8 RfPath,
- IN u8 DataRate,
- IN u8 Channel
-) {
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
- s16 band = -1, regulation = -1, bandwidth = -1,
- rateSection = -1, channel = -1;
- s8 powerLimit = MAX_POWER_INDEX;
+ if (lock)
+ _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
- if ((Adapter->registrypriv.RegEnableTxPowerLimit == 2 && pHalData->EEPROMRegulatory != 1) ||
- Adapter->registrypriv.RegEnableTxPowerLimit == 0)
- return MAX_POWER_INDEX;
+ if (!regd_name) /* no regd_name specified, use currnet */
+ regd_name = rfctl->regd_name;
- switch (Adapter->registrypriv.RegPwrTblSel) {
- case 1:
- regulation = TXPWR_LMT_ETSI;
- break;
+ if (rfctl->txpwr_regd_num == 0
+ || strcmp(regd_name, regd_str(TXPWR_LMT_NONE)) == 0)
+ goto release_lock;
- case 2:
- regulation = TXPWR_LMT_MKK;
- break;
+ if (strcmp(regd_name, regd_str(TXPWR_LMT_WW)) == 0)
+ is_ww_regd = 1;
- case 3:
- regulation = TXPWR_LMT_FCC;
- break;
+ if (!is_ww_regd) {
+ ent = _rtw_txpwr_lmt_get_by_name(rfctl, regd_name);
+ if (!ent)
+ goto release_lock;
+ }
- case 4:
- regulation = TXPWR_LMT_WW;
- break;
+ ch_idx = phy_GetChannelIndexOfTxPowerLimit(Band, cch);
+ if (ch_idx == -1)
+ goto release_lock;
- default:
- regulation = (Band == BAND_ON_2_4G) ? pHalData->Regulation2_4G
- : pHalData->Regulation5G;
- break;
+ if (Band == BAND_ON_2_4G) {
+ if (!is_ww_regd) {
+ lmt = ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx];
+ if (lmt != -MAX_POWER_INDEX)
+ goto release_lock;
+ }
+
+ /* search for min value for WW regd or WW limit */
+ lmt = MAX_POWER_INDEX;
+ head = &rfctl->txpwr_lmt_list;
+ cur = get_next(head);
+ while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
+ ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
+ cur = get_next(cur);
+ if (ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx] != -MAX_POWER_INDEX)
+ lmt = rtw_min(lmt, ent->lmt_2g[bw][tlrs][ch_idx][ntx_idx]);
+ }
}
+ #ifdef CONFIG_IEEE80211_BAND_5GHZ
+ else if (Band == BAND_ON_5G) {
+ if (!is_ww_regd) {
+ lmt = ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx];
+ if (lmt != -MAX_POWER_INDEX)
+ goto release_lock;
+ }
- /*DBG_871X("pMgntInfo->RegPwrTblSel %d, final regulation %d\n", Adapter->registrypriv.RegPwrTblSel, regulation );*/
+ /* search for min value for WW regd or WW limit */
+ lmt = MAX_POWER_INDEX;
+ head = &rfctl->txpwr_lmt_list;
+ cur = get_next(head);
+ while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
+ ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
+ cur = get_next(cur);
+ if (ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx] != -MAX_POWER_INDEX)
+ lmt = rtw_min(lmt, ent->lmt_5g[bw][tlrs - 1][ch_idx][ntx_idx]);
+ }
+ }
+ #endif
+release_lock:
+ if (lock)
+ _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
- if (Band == BAND_ON_2_4G)
- band = 0;
- else if (Band == BAND_ON_5G)
- band = 1;
-
- if (Bandwidth == CHANNEL_WIDTH_20)
- bandwidth = 0;
- else if (Bandwidth == CHANNEL_WIDTH_40)
- bandwidth = 1;
- else if (Bandwidth == CHANNEL_WIDTH_80)
- bandwidth = 2;
- else if (Bandwidth == CHANNEL_WIDTH_160)
- bandwidth = 3;
-
- switch (DataRate) {
- case MGN_1M:
- case MGN_2M:
- case MGN_5_5M:
- case MGN_11M:
- rateSection = 0;
- break;
+exit:
+ return lmt;
+}
- case MGN_6M:
- case MGN_9M:
- case MGN_12M:
- case MGN_18M:
- case MGN_24M:
- case MGN_36M:
- case MGN_48M:
- case MGN_54M:
- rateSection = 1;
- break;
+/*
+* return txpwr limit diff value
+* MAX_POWER_INDEX is returned when NO limit
+*/
+inline s8 phy_get_txpwr_lmt(_adapter *adapter
+ , const char *regd_name
+ , BAND_TYPE band, enum channel_width bw
+ , u8 rfpath, u8 rs, u8 ntx_idx, u8 cch, u8 lock
+)
+{
+ u8 tlrs;
+ s8 lmt = MAX_POWER_INDEX;
+
+ if (IS_CCK_RATE_SECTION(rs))
+ tlrs = TXPWR_LMT_RS_CCK;
+ else if (IS_OFDM_RATE_SECTION(rs))
+ tlrs = TXPWR_LMT_RS_OFDM;
+ else if (IS_HT_RATE_SECTION(rs))
+ tlrs = TXPWR_LMT_RS_HT;
+ else if (IS_VHT_RATE_SECTION(rs))
+ tlrs = TXPWR_LMT_RS_VHT;
+ else {
+ RTW_ERR("%s invalid rs %u\n", __func__, rs);
+ rtw_warn_on(1);
+ goto exit;
+ }
- case MGN_MCS0:
- case MGN_MCS1:
- case MGN_MCS2:
- case MGN_MCS3:
- case MGN_MCS4:
- case MGN_MCS5:
- case MGN_MCS6:
- case MGN_MCS7:
- rateSection = 2;
- break;
+ lmt = phy_get_txpwr_lmt_abs(adapter, regd_name, band, bw, tlrs, ntx_idx, cch, lock);
- case MGN_MCS8:
- case MGN_MCS9:
- case MGN_MCS10:
- case MGN_MCS11:
- case MGN_MCS12:
- case MGN_MCS13:
- case MGN_MCS14:
- case MGN_MCS15:
- rateSection = 3;
- break;
+ if (lmt != MAX_POWER_INDEX) {
+ /* return diff value */
+ lmt = lmt - PHY_GetTxPowerByRateBase(adapter, band, rfpath, rs);
+ }
- case MGN_MCS16:
- case MGN_MCS17:
- case MGN_MCS18:
- case MGN_MCS19:
- case MGN_MCS20:
- case MGN_MCS21:
- case MGN_MCS22:
- case MGN_MCS23:
- rateSection = 4;
- break;
+exit:
+ return lmt;
+}
- case MGN_MCS24:
- case MGN_MCS25:
- case MGN_MCS26:
- case MGN_MCS27:
- case MGN_MCS28:
- case MGN_MCS29:
- case MGN_MCS30:
- case MGN_MCS31:
- rateSection = 5;
- break;
+/*
+* May search for secondary channels for min limit
+* return txpwr limit diff value
+*/
+s8
+PHY_GetTxPowerLimit(_adapter *adapter
+ , const char *regd_name
+ , BAND_TYPE band, enum channel_width bw
+ , u8 rfpath, u8 rate, u8 ntx_idx, u8 cch)
+{
+ struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+ BOOLEAN no_sc = _FALSE;
+ s8 tlrs = -1, rs = -1;
+ s8 lmt = MAX_POWER_INDEX;
+ u8 tmp_cch = 0;
+ u8 tmp_bw;
+ u8 bw_bmp = 0;
+ s8 min_lmt = MAX_POWER_INDEX;
+ u8 final_bw = bw, final_cch = cch;
+ _irqL irqL;
+
+#ifdef CONFIG_MP_INCLUDED
+ /* MP mode channel don't use secondary channel */
+ if (rtw_mp_mode_check(adapter) == _TRUE)
+ no_sc = _TRUE;
+#endif
+ if (IS_CCK_RATE(rate)) {
+ tlrs = TXPWR_LMT_RS_CCK;
+ rs = CCK;
+ } else if (IS_OFDM_RATE(rate)) {
+ tlrs = TXPWR_LMT_RS_OFDM;
+ rs = OFDM;
+ } else if (IS_HT_RATE(rate)) {
+ tlrs = TXPWR_LMT_RS_HT;
+ rs = HT_1SS + (IS_HT1SS_RATE(rate) ? 0 : IS_HT2SS_RATE(rate) ? 1 : IS_HT3SS_RATE(rate) ? 2 : IS_HT4SS_RATE(rate) ? 3 : 0);
+ } else if (IS_VHT_RATE(rate)) {
+ tlrs = TXPWR_LMT_RS_VHT;
+ rs = VHT_1SS + (IS_VHT1SS_RATE(rate) ? 0 : IS_VHT2SS_RATE(rate) ? 1 : IS_VHT3SS_RATE(rate) ? 2 : IS_VHT4SS_RATE(rate) ? 3 : 0);
+ } else {
+ RTW_ERR("%s invalid rate 0x%x\n", __func__, rate);
+ rtw_warn_on(1);
+ goto exit;
+ }
- case MGN_VHT1SS_MCS0:
- case MGN_VHT1SS_MCS1:
- case MGN_VHT1SS_MCS2:
- case MGN_VHT1SS_MCS3:
- case MGN_VHT1SS_MCS4:
- case MGN_VHT1SS_MCS5:
- case MGN_VHT1SS_MCS6:
- case MGN_VHT1SS_MCS7:
- case MGN_VHT1SS_MCS8:
- case MGN_VHT1SS_MCS9:
- rateSection = 6;
- break;
+ if (no_sc == _TRUE) {
+ /* use the input center channel and bandwidth directly */
+ tmp_cch = cch;
+ bw_bmp = ch_width_to_bw_cap(bw);
+ } else {
+ /*
+ * find the possible tx bandwidth bmp for this rate, and then will get center channel for each bandwidth
+ * if no possible tx bandwidth bmp, select valid bandwidth up to current RF bandwidth into bmp
+ */
+ if (tlrs == TXPWR_LMT_RS_CCK || tlrs == TXPWR_LMT_RS_OFDM)
+ bw_bmp = BW_CAP_20M; /* CCK, OFDM only BW 20M */
+ else if (tlrs == TXPWR_LMT_RS_HT) {
+ bw_bmp = rtw_get_tx_bw_bmp_of_ht_rate(dvobj, rate, bw);
+ if (bw_bmp == 0)
+ bw_bmp = ch_width_to_bw_cap(bw > CHANNEL_WIDTH_40 ? CHANNEL_WIDTH_40 : bw);
+ } else if (tlrs == TXPWR_LMT_RS_VHT) {
+ bw_bmp = rtw_get_tx_bw_bmp_of_vht_rate(dvobj, rate, bw);
+ if (bw_bmp == 0)
+ bw_bmp = ch_width_to_bw_cap(bw > CHANNEL_WIDTH_160 ? CHANNEL_WIDTH_160 : bw);
+ } else
+ rtw_warn_on(1);
+ }
- case MGN_VHT2SS_MCS0:
- case MGN_VHT2SS_MCS1:
- case MGN_VHT2SS_MCS2:
- case MGN_VHT2SS_MCS3:
- case MGN_VHT2SS_MCS4:
- case MGN_VHT2SS_MCS5:
- case MGN_VHT2SS_MCS6:
- case MGN_VHT2SS_MCS7:
- case MGN_VHT2SS_MCS8:
- case MGN_VHT2SS_MCS9:
- rateSection = 7;
- break;
+ if (bw_bmp == 0)
+ goto exit;
- case MGN_VHT3SS_MCS0:
- case MGN_VHT3SS_MCS1:
- case MGN_VHT3SS_MCS2:
- case MGN_VHT3SS_MCS3:
- case MGN_VHT3SS_MCS4:
- case MGN_VHT3SS_MCS5:
- case MGN_VHT3SS_MCS6:
- case MGN_VHT3SS_MCS7:
- case MGN_VHT3SS_MCS8:
- case MGN_VHT3SS_MCS9:
- rateSection = 8;
- break;
+ _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
- case MGN_VHT4SS_MCS0:
- case MGN_VHT4SS_MCS1:
- case MGN_VHT4SS_MCS2:
- case MGN_VHT4SS_MCS3:
- case MGN_VHT4SS_MCS4:
- case MGN_VHT4SS_MCS5:
- case MGN_VHT4SS_MCS6:
- case MGN_VHT4SS_MCS7:
- case MGN_VHT4SS_MCS8:
- case MGN_VHT4SS_MCS9:
- rateSection = 9;
- break;
+ /* loop for each possible tx bandwidth to find minimum limit */
+ for (tmp_bw = CHANNEL_WIDTH_20; tmp_bw <= bw; tmp_bw++) {
+ if (!(ch_width_to_bw_cap(tmp_bw) & bw_bmp))
+ continue;
+
+ if (no_sc == _FALSE) {
+ if (tmp_bw == CHANNEL_WIDTH_20)
+ tmp_cch = hal_data->cch_20;
+ else if (tmp_bw == CHANNEL_WIDTH_40)
+ tmp_cch = hal_data->cch_40;
+ else if (tmp_bw == CHANNEL_WIDTH_80)
+ tmp_cch = hal_data->cch_80;
+ else {
+ tmp_cch = 0;
+ rtw_warn_on(1);
+ }
+ }
+
+ lmt = phy_get_txpwr_lmt_abs(adapter, regd_name, band, tmp_bw, tlrs, ntx_idx, tmp_cch, 0);
+
+ if (min_lmt >= lmt) {
+ min_lmt = lmt;
+ final_cch = tmp_cch;
+ final_bw = tmp_bw;
+ }
- default:
- DBG_871X("Wrong rate 0x%x\n", DataRate);
- break;
}
- if (Band == BAND_ON_5G && rateSection == 0)
- DBG_871X("Wrong rate 0x%x: No CCK in 5G Band\n", DataRate);
+ _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+
+ if (min_lmt != MAX_POWER_INDEX) {
+ /* return diff value */
+ min_lmt = min_lmt - PHY_GetTxPowerByRateBase(adapter, band, rfpath, rs);
+ }
- /*workaround for wrong index combination to obtain tx power limit,*/
- /*OFDM only exists in BW 20M*/
- if (rateSection == 1)
- bandwidth = 0;
+exit:
- /*workaround for wrong index combination to obtain tx power limit,*/
- /*CCK table will only be given in BW 20M*/
- if (rateSection == 0)
- bandwidth = 0;
+ if (0) {
+ if (final_bw != bw && (IS_HT_RATE(rate) || IS_VHT_RATE(rate)))
+ RTW_INFO("%s min_lmt: %s ch%u -> %s ch%u\n"
+ , MGN_RATE_STR(rate)
+ , ch_width_str(bw), cch
+ , ch_width_str(final_bw), final_cch);
+ }
- /*workaround for wrong indxe combination to obtain tx power limit,*/
- /*HT on 80M will reference to HT on 40M*/
- if ((rateSection == 2 || rateSection == 3) && Band == BAND_ON_5G && bandwidth == 2)
- bandwidth = 1;
+ return min_lmt;
+}
- if (Band == BAND_ON_2_4G)
- channel = phy_GetChannelIndexOfTxPowerLimit(BAND_ON_2_4G, Channel);
- else if (Band == BAND_ON_5G)
- channel = phy_GetChannelIndexOfTxPowerLimit(BAND_ON_5G, Channel);
- else if (Band == BAND_ON_BOTH)
- /*BAND_ON_BOTH don't care temporarily*/
-
- if (band == -1 || regulation == -1 || bandwidth == -1 ||
- rateSection == -1 || channel == -1) {
- /*DBG_871X("Wrong index value to access power limit table [band %d][regulation %d][bandwidth %d][rf_path %d][rate_section %d][chnlGroup %d]\n",*/
- /* band, regulation, bandwidth, RfPath, rateSection, channelGroup );*/
-
- return MAX_POWER_INDEX;
- }
+static void phy_txpwr_lmt_cck_ofdm_mt_chk(_adapter *adapter)
+{
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+ struct txpwr_lmt_ent *ent;
+ _list *cur, *head;
+ u8 channel, tlrs, ntx_idx;
- if (Band == BAND_ON_2_4G) {
- s8 limits[10] = {0};
- u8 i = 0;
+ rfctl->txpwr_lmt_2g_cck_ofdm_state = 0;
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+ rfctl->txpwr_lmt_5g_cck_ofdm_state = 0;
+#endif
- if (bandwidth >= MAX_2_4G_BANDWIDTH_NUM)
- bandwidth = MAX_2_4G_BANDWIDTH_NUM - 1;
+ head = &rfctl->txpwr_lmt_list;
+ cur = get_next(head);
- for (i = 0; i < MAX_REGULATION_NUM; ++i)
- limits[i] = pHalData->TxPwrLimit_2_4G_Original[i][bandwidth][rateSection][channel][RfPath];
+ while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
+ ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
+ cur = get_next(cur);
- powerLimit = (regulation == TXPWR_LMT_WW) ? phy_GetWorldWideLimit(limits) :
- pHalData->TxPwrLimit_2_4G_Original[regulation][bandwidth][rateSection][channel][RfPath];
+ /* check 2G CCK, OFDM state*/
+ for (tlrs = TXPWR_LMT_RS_CCK; tlrs <= TXPWR_LMT_RS_OFDM; tlrs++) {
+ for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
+ for (channel = 0; channel < CENTER_CH_2G_NUM; ++channel) {
+ if (ent->lmt_2g[CHANNEL_WIDTH_20][tlrs][channel][ntx_idx] != MAX_POWER_INDEX) {
+ if (tlrs == TXPWR_LMT_RS_CCK)
+ rfctl->txpwr_lmt_2g_cck_ofdm_state |= TXPWR_LMT_HAS_CCK_1T << ntx_idx;
+ else
+ rfctl->txpwr_lmt_2g_cck_ofdm_state |= TXPWR_LMT_HAS_OFDM_1T << ntx_idx;
+ break;
+ }
+ }
+ }
+ }
- } else if (Band == BAND_ON_5G) {
- s8 limits[10] = {0};
- u8 i = 0;
+ /* if 2G OFDM multi-TX is not defined, reference HT20 */
+ for (channel = 0; channel < CENTER_CH_2G_NUM; ++channel) {
+ for (ntx_idx = RF_2TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
+ if (rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx))
+ continue;
+ ent->lmt_2g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_OFDM][channel][ntx_idx] =
+ ent->lmt_2g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_HT][channel][ntx_idx];
+ }
+ }
- for (i = 0; i < MAX_REGULATION_NUM; ++i)
- limits[i] = pHalData->TxPwrLimit_5G_Original[i][bandwidth][rateSection][channel][RfPath];
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+ /* check 5G OFDM state*/
+ for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
+ for (channel = 0; channel < CENTER_CH_5G_ALL_NUM; ++channel) {
+ if (ent->lmt_5g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_OFDM - 1][channel][ntx_idx] != MAX_POWER_INDEX) {
+ rfctl->txpwr_lmt_5g_cck_ofdm_state |= TXPWR_LMT_HAS_OFDM_1T << ntx_idx;
+ break;
+ }
+ }
+ }
- powerLimit = (regulation == TXPWR_LMT_WW) ? phy_GetWorldWideLimit(limits) :
- pHalData->TxPwrLimit_5G_Original[regulation][bandwidth][rateSection][channel][RfPath];
- } else
- DBG_871X("No power limit table of the specified band\n");
-
- /*combine 5G VHT & HT rate*/
- /*5G 20M and 40M HT and VHT can cross reference*/
- /*
- if (Band == BAND_ON_5G && powerLimit == MAX_POWER_INDEX) {
- if (bandwidth == 0 || bandwidth == 1) {
- RT_TRACE(COMP_INIT, DBG_LOUD, ( "No power limit table of the specified band %d, bandwidth %d, ratesection %d, rf path %d\n",
- band, bandwidth, rateSection, RfPath));
- if (rateSection == 2)
- powerLimit = pHalData->TxPwrLimit_5G_Original[regulation]
- [bandwidth][4][channelGroup][RfPath];
- else if (rateSection == 4)
- powerLimit = pHalData->TxPwrLimit_5G_Original[regulation]
- [bandwidth][2][channelGroup][RfPath];
- else if (rateSection == 3)
- powerLimit = pHalData->TxPwrLimit_5G_Original[regulation]
- [bandwidth][5][channelGroup][RfPath];
- else if (rateSection == 5)
- powerLimit = pHalData->TxPwrLimit_5G_Original[regulation]
- [bandwidth][3][channelGroup][RfPath];
+ for (channel = 0; channel < CENTER_CH_5G_ALL_NUM; ++channel) {
+ for (ntx_idx = RF_2TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
+ if (rfctl->txpwr_lmt_5g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx))
+ continue;
+ /* if 5G OFDM multi-TX is not defined, reference HT20 */
+ ent->lmt_5g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_OFDM - 1][channel][ntx_idx] =
+ ent->lmt_5g[CHANNEL_WIDTH_20][TXPWR_LMT_RS_HT - 1][channel][ntx_idx];
+ }
}
+#endif /* CONFIG_IEEE80211_BAND_5GHZ */
}
- */
- /*DBG_871X("TxPwrLmt[Regulation %d][Band %d][BW %d][RFPath %d][Rate 0x%x][Chnl %d] = %d\n",*/
- /* regulation, pHalData->CurrentBandType, Bandwidth, RfPath, DataRate, Channel, powerLimit);*/
- return powerLimit;
}
-#endif
-
-VOID
-phy_CrossReferenceHTAndVHTTxPowerLimit(
- IN PADAPTER pAdapter
-) {
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
- u8 regulation, bw, channel, rs, ref_rs;
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+static void phy_txpwr_lmt_cross_ref_ht_vht(_adapter *adapter)
+{
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+ struct txpwr_lmt_ent *ent;
+ _list *cur, *head;
+ u8 bw, channel, tlrs, ref_tlrs, ntx_idx;
int ht_ref_vht_5g_20_40 = 0;
int vht_ref_ht_5g_20_40 = 0;
int ht_has_ref_5g_20_40 = 0;
int vht_has_ref_5g_20_40 = 0;
- pHalData->tx_pwr_lmt_5g_20_40_ref = 0;
+ rfctl->txpwr_lmt_5g_20_40_ref = 0;
- for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) {
+ head = &rfctl->txpwr_lmt_list;
+ cur = get_next(head);
+
+ while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
+ ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
+ cur = get_next(cur);
for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; ++bw) {
for (channel = 0; channel < CENTER_CH_5G_ALL_NUM; ++channel) {
- for (rs = 0; rs < MAX_RATE_SECTION_NUM; ++rs) {
+ for (tlrs = TXPWR_LMT_RS_HT; tlrs < TXPWR_LMT_RS_NUM; ++tlrs) {
/* 5G 20M 40M VHT and HT can cross reference */
if (bw == CHANNEL_WIDTH_20 || bw == CHANNEL_WIDTH_40) {
- if (rs == HT_1SS)
- ref_rs = VHT_1SS;
- else if (rs == HT_2SS)
- ref_rs = VHT_2SS;
- else if (rs == HT_3SS)
- ref_rs = VHT_3SS;
- else if (rs == HT_4SS)
- ref_rs = VHT_4SS;
- else if (rs == VHT_1SS)
- ref_rs = HT_1SS;
- else if (rs == VHT_2SS)
- ref_rs = HT_2SS;
- else if (rs == VHT_3SS)
- ref_rs = HT_3SS;
- else if (rs == VHT_4SS)
- ref_rs = HT_4SS;
+ if (tlrs == TXPWR_LMT_RS_HT)
+ ref_tlrs = TXPWR_LMT_RS_VHT;
+ else if (tlrs == TXPWR_LMT_RS_VHT)
+ ref_tlrs = TXPWR_LMT_RS_HT;
else
continue;
- if (pHalData->TxPwrLimit_5G[regulation][bw][ref_rs][channel][RF_PATH_A] == MAX_POWER_INDEX)
- continue;
+ for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
- if (IS_HT_RATE_SECTION(rs))
- ht_has_ref_5g_20_40++;
- else if (IS_VHT_RATE_SECTION(rs))
- vht_has_ref_5g_20_40++;
- else
- continue;
+ if (ent->lmt_5g[bw][ref_tlrs - 1][channel][ntx_idx] == MAX_POWER_INDEX)
+ continue;
- if (pHalData->TxPwrLimit_5G[regulation][bw][rs][channel][RF_PATH_A] != MAX_POWER_INDEX)
- continue;
+ if (tlrs == TXPWR_LMT_RS_HT)
+ ht_has_ref_5g_20_40++;
+ else if (tlrs == TXPWR_LMT_RS_VHT)
+ vht_has_ref_5g_20_40++;
+ else
+ continue;
- if (IS_HT_RATE_SECTION(rs) && IS_VHT_RATE_SECTION(ref_rs))
- ht_ref_vht_5g_20_40++;
- else if (IS_VHT_RATE_SECTION(rs) && IS_HT_RATE_SECTION(ref_rs))
- vht_ref_ht_5g_20_40++;
+ if (ent->lmt_5g[bw][tlrs - 1][channel][ntx_idx] != MAX_POWER_INDEX)
+ continue;
- if (0)
- RTW_INFO("reg:%u, bw:%u, ch:%u, %s ref %s\n"
- , regulation, bw, channel
- , rate_section_str(rs), rate_section_str(ref_rs));
+ if (tlrs == TXPWR_LMT_RS_HT && ref_tlrs == TXPWR_LMT_RS_VHT)
+ ht_ref_vht_5g_20_40++;
+ else if (tlrs == TXPWR_LMT_RS_VHT && ref_tlrs == TXPWR_LMT_RS_HT)
+ vht_ref_ht_5g_20_40++;
- pHalData->TxPwrLimit_5G[regulation][bw][rs][channel][RF_PATH_A] =
- pHalData->TxPwrLimit_5G[regulation][bw][ref_rs][channel][RF_PATH_A];
+ if (0)
+ RTW_INFO("reg:%s, bw:%u, ch:%u, %s-%uT ref %s-%uT\n"
+ , ent->regd_name, bw, channel
+ , txpwr_lmt_rs_str(tlrs), ntx_idx + 1
+ , txpwr_lmt_rs_str(ref_tlrs), ntx_idx + 1);
+
+ ent->lmt_5g[bw][tlrs - 1][channel][ntx_idx] =
+ ent->lmt_5g[bw][ref_tlrs - 1][channel][ntx_idx];
+ }
}
}
@@ -2436,170 +3251,307 @@ phy_CrossReferenceHTAndVHTTxPowerLimit(
/* 5G 20M&40M HT all come from VHT*/
if (ht_ref_vht_5g_20_40 && ht_has_ref_5g_20_40 == ht_ref_vht_5g_20_40)
- pHalData->tx_pwr_lmt_5g_20_40_ref |= TX_PWR_LMT_REF_HT_FROM_VHT;
+ rfctl->txpwr_lmt_5g_20_40_ref |= TXPWR_LMT_REF_HT_FROM_VHT;
/* 5G 20M&40M VHT all come from HT*/
if (vht_ref_ht_5g_20_40 && vht_has_ref_5g_20_40 == vht_ref_ht_5g_20_40)
- pHalData->tx_pwr_lmt_5g_20_40_ref |= TX_PWR_LMT_REF_VHT_FROM_HT;
+ rfctl->txpwr_lmt_5g_20_40_ref |= TXPWR_LMT_REF_VHT_FROM_HT;
}
+#endif /* CONFIG_IEEE80211_BAND_5GHZ */
-VOID
-PHY_ConvertTxPowerLimitToPowerIndex(
- IN PADAPTER Adapter
-) {
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
- u8 base;
- u8 regulation, bw, channel, rateSection;
- s8 tempValue = 0, tempPwrLmt = 0;
- u8 rfPath = 0;
+#ifndef DBG_TXPWR_LMT_BAND_CHK
+#define DBG_TXPWR_LMT_BAND_CHK 0
+#endif
- if (pHalData->odmpriv.PhyRegPgValueType != PHY_REG_PG_EXACT_VALUE) {
- rtw_warn_on(1);
- return;
- }
+#if DBG_TXPWR_LMT_BAND_CHK
+/* check if larger bandwidth limit is less than smaller bandwidth for HT & VHT rate */
+void phy_txpwr_limit_bandwidth_chk(_adapter *adapter)
+{
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+ struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+ u8 band, bw, path, tlrs, ntx_idx, cch, offset, scch;
+ u8 ch_num, n, i;
+
+ for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
+ if (!hal_is_band_support(adapter, band))
+ continue;
+
+ for (bw = CHANNEL_WIDTH_40; bw <= CHANNEL_WIDTH_80; bw++) {
+ if (bw >= CHANNEL_WIDTH_160)
+ continue;
+ if (band == BAND_ON_2_4G && bw >= CHANNEL_WIDTH_80)
+ continue;
- phy_CrossReferenceHTAndVHTTxPowerLimit(Adapter);
+ if (band == BAND_ON_2_4G)
+ ch_num = center_chs_2g_num(bw);
+ else
+ ch_num = center_chs_5g_num(bw);
- for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) {
+ if (ch_num == 0) {
+ rtw_warn_on(1);
+ break;
+ }
- for (bw = 0; bw < MAX_2_4G_BANDWIDTH_NUM; ++bw) {
+ for (tlrs = TXPWR_LMT_RS_HT; tlrs < TXPWR_LMT_RS_NUM; tlrs++) {
- for (channel = 0; channel < CENTER_CH_2G_NUM; ++channel) {
+ if (band == BAND_ON_2_4G && tlrs == TXPWR_LMT_RS_VHT)
+ continue;
+ if (band == BAND_ON_5G && tlrs == TXPWR_LMT_RS_CCK)
+ continue;
+ if (bw > CHANNEL_WIDTH_20 && (tlrs == TXPWR_LMT_RS_CCK || tlrs == TXPWR_LMT_RS_OFDM))
+ continue;
+ if (bw > CHANNEL_WIDTH_40 && tlrs == TXPWR_LMT_RS_HT)
+ continue;
+ if (tlrs == TXPWR_LMT_RS_VHT && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter))
+ continue;
- for (rateSection = CCK; rateSection <= HT_4SS; ++rateSection) {
- tempPwrLmt = pHalData->TxPwrLimit_2_4G[regulation][bw][rateSection][channel][RF_PATH_A];
+ for (ntx_idx = RF_1TX; ntx_idx < MAX_TX_COUNT; ntx_idx++) {
+ struct txpwr_lmt_ent *ent;
+ _list *cur, *head;
- if (tempPwrLmt != MAX_POWER_INDEX) {
+ if (ntx_idx >= hal_spec->tx_nss_num)
+ continue;
- for (rfPath = RF_PATH_A; rfPath < MAX_RF_PATH; ++rfPath) {
- base = phy_get_target_tx_power(Adapter, BAND_ON_2_4G, rfPath, rateSection);
- tempValue = tempPwrLmt - base;
- pHalData->TxPwrLimit_2_4G[regulation][bw][rateSection][channel][rfPath] = tempValue;
- }
+ /* bypass CCK multi-TX is not defined */
+ if (tlrs == TXPWR_LMT_RS_CCK && ntx_idx > RF_1TX) {
+ if (band == BAND_ON_2_4G
+ && !(rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_CCK_1T << ntx_idx)))
+ continue;
}
- }
- }
- }
- }
- if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(Adapter)) {
+ /* bypass OFDM multi-TX is not defined */
+ if (tlrs == TXPWR_LMT_RS_OFDM && ntx_idx > RF_1TX) {
+ if (band == BAND_ON_2_4G
+ && !(rfctl->txpwr_lmt_2g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx)))
+ continue;
+ #ifdef CONFIG_IEEE80211_BAND_5GHZ
+ if (band == BAND_ON_5G
+ && !(rfctl->txpwr_lmt_5g_cck_ofdm_state & (TXPWR_LMT_HAS_OFDM_1T << ntx_idx)))
+ continue;
+ #endif
+ }
- for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) {
+ /* bypass 5G 20M, 40M pure reference */
+ #ifdef CONFIG_IEEE80211_BAND_5GHZ
+ if (band == BAND_ON_5G && (bw == CHANNEL_WIDTH_20 || bw == CHANNEL_WIDTH_40)) {
+ if (rfctl->txpwr_lmt_5g_20_40_ref == TXPWR_LMT_REF_HT_FROM_VHT) {
+ if (tlrs == TXPWR_LMT_RS_HT)
+ continue;
+ } else if (rfctl->txpwr_lmt_5g_20_40_ref == TXPWR_LMT_REF_VHT_FROM_HT) {
+ if (tlrs == TXPWR_LMT_RS_VHT && bw <= CHANNEL_WIDTH_40)
+ continue;
+ }
+ }
+ #endif
- for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; ++bw) {
+ for (n = 0; n < ch_num; n++) {
+ u8 cch_by_bw[3];
+ u8 offset_by_bw; /* bitmap, 0 for lower, 1 for upper */
+ u8 bw_pos;
+ s8 lmt[3];
- for (channel = 0; channel < CENTER_CH_5G_ALL_NUM; ++channel) {
+ if (band == BAND_ON_2_4G)
+ cch = center_chs_2g(bw, n);
+ else
+ cch = center_chs_5g(bw, n);
- for (rateSection = OFDM; rateSection <= VHT_4SS; ++rateSection) {
- tempPwrLmt = pHalData->TxPwrLimit_5G[regulation][bw][rateSection][channel][RF_PATH_A];
+ if (cch == 0) {
+ rtw_warn_on(1);
+ break;
+ }
- if (tempPwrLmt != MAX_POWER_INDEX) {
+ _rtw_memset(cch_by_bw, 0, 3);
+ cch_by_bw[bw] = cch;
+ offset_by_bw = 0x01;
+
+ do {
+ for (bw_pos = bw; bw_pos >= CHANNEL_WIDTH_40; bw_pos--)
+ cch_by_bw[bw_pos - 1] = rtw_get_scch_by_cch_offset(cch_by_bw[bw_pos], bw_pos, offset_by_bw & BIT(bw_pos) ? HAL_PRIME_CHNL_OFFSET_UPPER : HAL_PRIME_CHNL_OFFSET_LOWER);
+
+ head = &rfctl->txpwr_lmt_list;
+ cur = get_next(head);
+ while ((rtw_end_of_queue_search(head, cur)) == _FALSE) {
+ ent = LIST_CONTAINOR(cur, struct txpwr_lmt_ent, list);
+ cur = get_next(cur);
+
+ for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--)
+ lmt[bw_pos] = phy_get_txpwr_lmt_abs(adapter, ent->regd_name, band, bw_pos, tlrs, ntx_idx, cch_by_bw[bw_pos], 0);
+
+ for (bw_pos = bw; bw_pos > CHANNEL_WIDTH_20; bw_pos--)
+ if (lmt[bw_pos] > lmt[bw_pos - 1])
+ break;
+ if (bw_pos == CHANNEL_WIDTH_20)
+ continue;
+
+ RTW_PRINT_SEL(RTW_DBGDUMP, "[%s][%s][%s][%uT][%-4s] cch:"
+ , band_str(band)
+ , ch_width_str(bw)
+ , txpwr_lmt_rs_str(tlrs)
+ , ntx_idx + 1
+ , ent->regd_name
+ );
+ for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--)
+ _RTW_PRINT_SEL(RTW_DBGDUMP, "%03u ", cch_by_bw[bw_pos]);
+ _RTW_PRINT_SEL(RTW_DBGDUMP, "limit:");
+ for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--) {
+ if (lmt[bw_pos] == MAX_POWER_INDEX)
+ _RTW_PRINT_SEL(RTW_DBGDUMP, "N/A ");
+ else
+ _RTW_PRINT_SEL(RTW_DBGDUMP, "%2u%s ", lmt[bw_pos] / 2, lmt[bw_pos] % 2 ? ".5" : "");
+ }
+ _RTW_PRINT_SEL(RTW_DBGDUMP, "\n");
+ }
+ for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--)
+ lmt[bw_pos] = phy_get_txpwr_lmt_abs(adapter, regd_str(TXPWR_LMT_WW), band, bw_pos, tlrs, ntx_idx, cch_by_bw[bw_pos], 0);
- for (rfPath = RF_PATH_A; rfPath < MAX_RF_PATH; ++rfPath) {
- base = phy_get_target_tx_power(Adapter, BAND_ON_5G, rfPath, rateSection);
- tempValue = tempPwrLmt - base;
- pHalData->TxPwrLimit_5G[regulation][bw][rateSection][channel][rfPath] = tempValue;
+ for (bw_pos = bw; bw_pos > CHANNEL_WIDTH_20; bw_pos--)
+ if (lmt[bw_pos] > lmt[bw_pos - 1])
+ break;
+ if (bw_pos != CHANNEL_WIDTH_20) {
+ RTW_PRINT_SEL(RTW_DBGDUMP, "[%s][%s][%s][%uT][%-4s] cch:"
+ , band_str(band)
+ , ch_width_str(bw)
+ , txpwr_lmt_rs_str(tlrs)
+ , ntx_idx + 1
+ , regd_str(TXPWR_LMT_WW)
+ );
+ for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--)
+ _RTW_PRINT_SEL(RTW_DBGDUMP, "%03u ", cch_by_bw[bw_pos]);
+ _RTW_PRINT_SEL(RTW_DBGDUMP, "limit:");
+ for (bw_pos = bw; bw_pos < CHANNEL_WIDTH_160; bw_pos--) {
+ if (lmt[bw_pos] == MAX_POWER_INDEX)
+ _RTW_PRINT_SEL(RTW_DBGDUMP, "N/A ");
+ else
+ _RTW_PRINT_SEL(RTW_DBGDUMP, "%2u%s ", lmt[bw_pos] / 2, lmt[bw_pos] % 2 ? ".5" : "");
+ }
+ _RTW_PRINT_SEL(RTW_DBGDUMP, "\n");
}
- }
- }
- }
- }
- }
- }
+
+ offset_by_bw += 2;
+ if (offset_by_bw & BIT(bw + 1))
+ break;
+ } while (1); /* loop for all ch combinations */
+ } /* loop for center channels */
+ } /* loop fo each ntx_idx */
+ } /* loop for tlrs */
+ } /* loop for bandwidth */
+ } /* loop for band */
}
+#endif /* DBG_TXPWR_LMT_BAND_CHK */
-/*
-* PHY_InitTxPowerLimit - Set all hal_data.TxPwrLimit_2_4G, TxPwrLimit_5G array to MAX_POWER_INDEX
-*/
-VOID
-PHY_InitTxPowerLimit(
- IN PADAPTER Adapter
-) {
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
- u8 i, j, k, l, m;
-
- for (i = 0; i < MAX_REGULATION_NUM; ++i)
- for (j = 0; j < MAX_2_4G_BANDWIDTH_NUM; ++j)
- for (k = 0; k < MAX_RATE_SECTION_NUM; ++k)
- for (m = 0; m < CENTER_CH_2G_NUM; ++m)
- for (l = 0; l < MAX_RF_PATH; ++l)
- pHalData->TxPwrLimit_2_4G[i][j][k][m][l] = MAX_POWER_INDEX;
-
- for (i = 0; i < MAX_REGULATION_NUM; ++i)
- for (j = 0; j < MAX_5G_BANDWIDTH_NUM; ++j)
- for (k = 0; k < MAX_RATE_SECTION_NUM; ++k)
- for (m = 0; m < CENTER_CH_5G_ALL_NUM; ++m)
- for (l = 0; l < MAX_RF_PATH; ++l)
- pHalData->TxPwrLimit_5G[i][j][k][m][l] = MAX_POWER_INDEX;
+static void phy_txpwr_lmt_post_hdl(_adapter *adapter)
+{
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+ _irqL irqL;
+
+ _enter_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+ if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter))
+ phy_txpwr_lmt_cross_ref_ht_vht(adapter);
+#endif
+ phy_txpwr_lmt_cck_ofdm_mt_chk(adapter);
+
+#if DBG_TXPWR_LMT_BAND_CHK
+ phy_txpwr_limit_bandwidth_chk(adapter);
+#endif
+
+ _exit_critical_mutex(&rfctl->txpwr_lmt_mutex, &irqL);
+}
+
+BOOLEAN
+GetS1ByteIntegerFromStringInDecimal(
+ IN char *str,
+ IN OUT s8 *val
+)
+{
+ u8 negative = 0;
+ u16 i = 0;
+
+ *val = 0;
+
+ while (str[i] != '\0') {
+ if (i == 0 && (str[i] == '+' || str[i] == '-')) {
+ if (str[i] == '-')
+ negative = 1;
+ } else if (str[i] >= '0' && str[i] <= '9') {
+ *val *= 10;
+ *val += (str[i] - '0');
+ } else
+ return _FALSE;
+ ++i;
+ }
+
+ if (negative)
+ *val = -*val;
+
+ return _TRUE;
}
+#endif /* CONFIG_TXPWR_LIMIT */
/*
-* PHY_SetTxPowerLimit - Parsing TX power limit from phydm array, called by odm_ConfigBB_TXPWR_LMT_XXX in phydm
+* phy_set_tx_power_limit - Parsing TX power limit from phydm array, called by odm_ConfigBB_TXPWR_LMT_XXX in phydm
*/
VOID
-PHY_SetTxPowerLimit(
- IN PDM_ODM_T pDM_Odm,
- IN u8 *Regulation,
- IN u8 *Band,
- IN u8 *Bandwidth,
- IN u8 *RateSection,
- IN u8 *RfPath,
- IN u8 *Channel,
- IN u8 *PowerLimit
-) {
- PADAPTER Adapter = pDM_Odm->Adapter;
+phy_set_tx_power_limit(
+ IN struct dm_struct *pDM_Odm,
+ IN u8 *Regulation,
+ IN u8 *Band,
+ IN u8 *Bandwidth,
+ IN u8 *RateSection,
+ IN u8 *ntx,
+ IN u8 *Channel,
+ IN u8 *PowerLimit
+)
+{
+#ifdef CONFIG_TXPWR_LIMIT
+ PADAPTER Adapter = pDM_Odm->adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
- u8 regulation = 0, bandwidth = 0, rateSection = 0, channel;
+ u8 band = 0, bandwidth = 0, tlrs = 0, channel;
+ u8 ntx_idx;
s8 powerLimit = 0, prevPowerLimit, channelIndex;
if (0)
- RTW_INFO("Index of power limit table [band %s][regulation %s][bw %s][rate section %s][rf path %s][chnl %s][val %s]\n"
- , Band, Regulation, Bandwidth, RateSection, RfPath, Channel, PowerLimit);
+ RTW_INFO("Index of power limit table [regulation %s][band %s][bw %s][rate section %s][ntx %s][chnl %s][val %s]\n"
+ , Regulation, Band, Bandwidth, RateSection, ntx, Channel, PowerLimit);
- if (GetU1ByteIntegerFromStringInDecimal((s8 *)Channel, &channel) == _FALSE
- || GetU1ByteIntegerFromStringInDecimal((s8 *)PowerLimit, &powerLimit) == _FALSE
- ) {
+ if (GetU1ByteIntegerFromStringInDecimal((char *)Channel, &channel) == _FALSE
+ || GetS1ByteIntegerFromStringInDecimal((char *)PowerLimit, &powerLimit) == _FALSE
+ ) {
RTW_PRINT("Illegal index of power limit table [ch %s][val %s]\n", Channel, PowerLimit);
return;
}
- powerLimit = powerLimit > MAX_POWER_INDEX ? MAX_POWER_INDEX : powerLimit;
+ if (powerLimit < -MAX_POWER_INDEX || powerLimit > MAX_POWER_INDEX)
+ RTW_PRINT("Illegal power limit value [ch %s][val %s]\n", Channel, PowerLimit);
- if (eqNByte(Regulation, (u8 *)("FCC"), 3))
- regulation = TXPWR_LMT_FCC;
- else if (eqNByte(Regulation, (u8 *)("MKK"), 3))
- regulation = TXPWR_LMT_MKK;
- else if (eqNByte(Regulation, (u8 *)("ETSI"), 4))
- regulation = TXPWR_LMT_ETSI;
- else if (eqNByte(Regulation, (u8 *)("WW13"), 4))
- regulation = TXPWR_LMT_WW;
+ powerLimit = powerLimit > MAX_POWER_INDEX ? MAX_POWER_INDEX : powerLimit;
+ powerLimit = powerLimit < -MAX_POWER_INDEX ? -MAX_POWER_INDEX + 1 : powerLimit;
+
+ if (eqNByte(RateSection, (u8 *)("CCK"), 3))
+ tlrs = TXPWR_LMT_RS_CCK;
+ else if (eqNByte(RateSection, (u8 *)("OFDM"), 4))
+ tlrs = TXPWR_LMT_RS_OFDM;
+ else if (eqNByte(RateSection, (u8 *)("HT"), 2))
+ tlrs = TXPWR_LMT_RS_HT;
+ else if (eqNByte(RateSection, (u8 *)("VHT"), 3))
+ tlrs = TXPWR_LMT_RS_VHT;
else {
- RTW_PRINT("unknown regulation:%s", Regulation);
+ RTW_PRINT("Wrong rate section:%s\n", RateSection);
return;
}
- if (eqNByte(RateSection, (u8 *)("CCK"), 3) && eqNByte(RfPath, (u8 *)("1T"), 2))
- rateSection = CCK;
- else if (eqNByte(RateSection, (u8 *)("OFDM"), 4) && eqNByte(RfPath, (u8 *)("1T"), 2))
- rateSection = OFDM;
- else if (eqNByte(RateSection, (u8 *)("HT"), 2) && eqNByte(RfPath, (u8 *)("1T"), 2))
- rateSection = HT_1SS;
- else if (eqNByte(RateSection, (u8 *)("HT"), 2) && eqNByte(RfPath, (u8 *)("2T"), 2))
- rateSection = HT_2SS;
- else if (eqNByte(RateSection, (u8 *)("HT"), 2) && eqNByte(RfPath, (u8 *)("3T"), 2))
- rateSection = HT_3SS;
- else if (eqNByte(RateSection, (u8 *)("HT"), 2) && eqNByte(RfPath, (u8 *)("4T"), 2))
- rateSection = HT_4SS;
- else if (eqNByte(RateSection, (u8 *)("VHT"), 3) && eqNByte(RfPath, (u8 *)("1T"), 2))
- rateSection = VHT_1SS;
- else if (eqNByte(RateSection, (u8 *)("VHT"), 3) && eqNByte(RfPath, (u8 *)("2T"), 2))
- rateSection = VHT_2SS;
- else if (eqNByte(RateSection, (u8 *)("VHT"), 3) && eqNByte(RfPath, (u8 *)("3T"), 2))
- rateSection = VHT_3SS;
- else if (eqNByte(RateSection, (u8 *)("VHT"), 3) && eqNByte(RfPath, (u8 *)("4T"), 2))
- rateSection = VHT_4SS;
+ if (eqNByte(ntx, (u8 *)("1T"), 2))
+ ntx_idx = RF_1TX;
+ else if (eqNByte(ntx, (u8 *)("2T"), 2))
+ ntx_idx = RF_2TX;
+ else if (eqNByte(ntx, (u8 *)("3T"), 2))
+ ntx_idx = RF_3TX;
+ else if (eqNByte(ntx, (u8 *)("4T"), 2))
+ ntx_idx = RF_4TX;
else {
- RTW_PRINT("Wrong rate section: (%s,%s)\n", RateSection, RfPath);
+ RTW_PRINT("Wrong tx num:%s\n", ntx);
return;
}
@@ -2609,12 +3561,15 @@ PHY_SetTxPowerLimit(
bandwidth = CHANNEL_WIDTH_40;
else if (eqNByte(Bandwidth, (u8 *)("80M"), 3))
bandwidth = CHANNEL_WIDTH_80;
+ else if (eqNByte(Bandwidth, (u8 *)("160M"), 4))
+ bandwidth = CHANNEL_WIDTH_160;
else {
RTW_PRINT("unknown bandwidth: %s\n", Bandwidth);
return;
}
if (eqNByte(Band, (u8 *)("2.4G"), 4)) {
+ band = BAND_ON_2_4G;
channelIndex = phy_GetChannelIndexOfTxPowerLimit(BAND_ON_2_4G, channel);
if (channelIndex == -1) {
@@ -2627,20 +3582,11 @@ PHY_SetTxPowerLimit(
return;
}
- prevPowerLimit = pHalData->TxPwrLimit_2_4G[regulation][bandwidth][rateSection][channelIndex][RF_PATH_A];
-
- if (prevPowerLimit != MAX_POWER_INDEX)
- RTW_PRINT("duplicate tx power limit combination [band %s][regulation %s][bw %s][rate section %s][rf path %s][chnl %s]\n"
- , Band, Regulation, Bandwidth, RateSection, RfPath, Channel);
-
- if (powerLimit < prevPowerLimit)
- pHalData->TxPwrLimit_2_4G[regulation][bandwidth][rateSection][channelIndex][RF_PATH_A] = powerLimit;
-
- if (0)
- RTW_INFO("2.4G Band value : [regulation %d][bw %d][rate_section %d][chnl %d][val %d]\n"
- , regulation, bandwidth, rateSection, channelIndex, pHalData->TxPwrLimit_2_4G[regulation][bandwidth][rateSection][channelIndex][ODM_RF_PATH_A]);
- } else if (eqNByte(Band, (u8 *)("5G"), 2)) {
-
+ rtw_txpwr_lmt_add(adapter_to_rfctl(Adapter), Regulation, band, bandwidth, tlrs, ntx_idx, channelIndex, powerLimit);
+ }
+#ifdef CONFIG_IEEE80211_BAND_5GHZ
+ else if (eqNByte(Band, (u8 *)("5G"), 2)) {
+ band = BAND_ON_5G;
channelIndex = phy_GetChannelIndexOfTxPowerLimit(BAND_ON_5G, channel);
if (channelIndex == -1) {
@@ -2648,81 +3594,36 @@ PHY_SetTxPowerLimit(
return;
}
- prevPowerLimit = pHalData->TxPwrLimit_5G[regulation][bandwidth][rateSection][channelIndex][RF_PATH_A];
-
- if (prevPowerLimit != MAX_POWER_INDEX)
- RTW_PRINT("duplicate tx power limit combination [band %s][regulation %s][bw %s][rate section %s][rf path %s][chnl %s]\n"
- , Band, Regulation, Bandwidth, RateSection, RfPath, Channel);
-
- if (powerLimit < prevPowerLimit)
- pHalData->TxPwrLimit_5G[regulation][bandwidth][rateSection][channelIndex][RF_PATH_A] = powerLimit;
-
- if (0)
- RTW_INFO("5G Band value : [regulation %d][bw %d][rate_section %d][chnl %d][val %d]\n"
- , regulation, bandwidth, rateSection, channel, pHalData->TxPwrLimit_5G[regulation][bandwidth][rateSection][channelIndex][RF_PATH_A]);
- } else {
- RTW_PRINT("Cannot recognize the band info in %s\n", Band);
+ rtw_txpwr_lmt_add(adapter_to_rfctl(Adapter), Regulation, band, bandwidth, tlrs, ntx_idx, channelIndex, powerLimit);
+ }
+#endif
+ else {
+ RTW_PRINT("unknown/unsupported band:%s\n", Band);
return;
}
+#endif
}
u8
-PHY_GetTxPowerIndex(
- IN PADAPTER pAdapter,
- IN u8 RFPath,
- IN u8 Rate,
- IN CHANNEL_WIDTH BandWidth,
- IN u8 Channel
-) {
- u8 txPower = 0x3E;
-
- if (IS_HARDWARE_TYPE_8814A(pAdapter)) {
-#if (RTL8814A_SUPPORT == 1)
- txPower = PHY_GetTxPowerIndex_8814A(pAdapter, RFPath, Rate, BandWidth, Channel);
-#endif
- } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter)) {
-#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
- txPower = PHY_GetTxPowerIndex_8812A(pAdapter, RFPath, Rate, BandWidth, Channel);
-#endif
- } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
-#if (RTL8723B_SUPPORT == 1)
- txPower = PHY_GetTxPowerIndex_8723B(pAdapter, RFPath, Rate, BandWidth, Channel);
-#endif
- } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
-#if (RTL8703B_SUPPORT == 1)
- txPower = PHY_GetTxPowerIndex_8703B(pAdapter, RFPath, Rate, BandWidth, Channel);
-#endif
- } else if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
-#if (RTL8723D_SUPPORT == 1)
- txPower = PHY_GetTxPowerIndex_8723D(pAdapter, RFPath, Rate, BandWidth, Channel);
-#endif
- } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
-#if (RTL8192E_SUPPORT == 1)
- txPower = PHY_GetTxPowerIndex_8192E(pAdapter, RFPath, Rate, BandWidth, Channel);
-#endif
- } else if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
-#if (RTL8188E_SUPPORT == 1)
- txPower = PHY_GetTxPowerIndex_8188E(pAdapter, RFPath, Rate, BandWidth, Channel);
-#endif
- } else if (IS_HARDWARE_TYPE_8188F(pAdapter)) {
-#if (RTL8188F_SUPPORT == 1)
- txPower = PHY_GetTxPowerIndex_8188F(pAdapter, RFPath, Rate, BandWidth, Channel);
-#endif
- } else if (IS_HARDWARE_TYPE_8822B(pAdapter))
- txPower = rtw_hal_get_tx_power_index(pAdapter, RFPath, Rate, BandWidth, Channel);
- else if (IS_HARDWARE_TYPE_8821C(pAdapter))
- txPower = rtw_hal_get_tx_power_index(pAdapter, RFPath, Rate, BandWidth, Channel);
-
- return txPower;
+phy_get_tx_power_index(
+ IN PADAPTER pAdapter,
+ IN enum rf_path RFPath,
+ IN u8 Rate,
+ IN enum channel_width BandWidth,
+ IN u8 Channel
+)
+{
+ return rtw_hal_get_tx_power_index(pAdapter, RFPath, Rate, BandWidth, Channel, NULL);
}
VOID
PHY_SetTxPowerIndex(
- IN PADAPTER pAdapter,
- IN u32 PowerIndex,
- IN u8 RFPath,
- IN u8 Rate
-) {
+ IN PADAPTER pAdapter,
+ IN u32 PowerIndex,
+ IN enum rf_path RFPath,
+ IN u8 Rate
+)
+{
if (IS_HARDWARE_TYPE_8814A(pAdapter)) {
#if (RTL8814A_SUPPORT == 1)
PHY_SetTxPowerIndex_8814A(pAdapter, PowerIndex, RFPath, Rate);
@@ -2761,41 +3662,99 @@ PHY_SetTxPowerIndex(
rtw_hal_set_tx_power_index(pAdapter, PowerIndex, RFPath, Rate);
}
-bool phy_is_tx_power_limit_needed(_adapter *adapter) {
+void dump_tx_power_idx_title(void *sel, _adapter *adapter)
+{
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+ u8 bw = hal_data->current_channel_bw;
+
+ RTW_PRINT_SEL(sel, "%s", ch_width_str(bw));
+ if (bw >= CHANNEL_WIDTH_80)
+ _RTW_PRINT_SEL(sel, ", cch80:%u", hal_data->cch_80);
+ if (bw >= CHANNEL_WIDTH_40)
+ _RTW_PRINT_SEL(sel, ", cch40:%u", hal_data->cch_40);
+ _RTW_PRINT_SEL(sel, ", cch20:%u\n", hal_data->cch_20);
+
+ RTW_PRINT_SEL(sel, "%-4s %-9s %2s %-3s %-4s %-3s %-4s %-4s %-3s %-5s\n"
+ , "path", "rate", "", "pwr", "base", "", "(byr", "lmt)", "tpt", "ebias");
+}
+
+void dump_tx_power_idx_by_path_rs(void *sel, _adapter *adapter, u8 rfpath, u8 rs)
+{
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+ struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
+ u8 power_idx;
+ struct txpwr_idx_comp tic;
+ u8 tx_num, i;
+ u8 band = hal_data->current_band_type;
+ u8 cch = hal_data->current_channel;
+ u8 bw = hal_data->current_channel_bw;
+
+ if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, rfpath))
+ return;
+
+ if (rs >= RATE_SECTION_NUM)
+ return;
+
+ tx_num = rate_section_to_tx_num(rs);
+ if (tx_num >= hal_spec->tx_nss_num || tx_num >= hal_spec->max_tx_cnt)
+ return;
+
+ if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
+ return;
+
+ if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter))
+ return;
+
+ for (i = 0; i < rates_by_sections[rs].rate_num; i++) {
+ power_idx = rtw_hal_get_tx_power_index(adapter, rfpath, rates_by_sections[rs].rates[i], bw, cch, &tic);
+
+ RTW_PRINT_SEL(sel, "%4c %9s %uT %3u %4u %3d (%3d %3d) %3d %5d\n"
+ , rf_path_char(rfpath), MGN_RATE_STR(rates_by_sections[rs].rates[i]), tic.ntx_idx + 1
+ , power_idx, tic.base, (tic.by_rate > tic.limit ? tic.limit : tic.by_rate), tic.by_rate, tic.limit, tic.tpt, tic.ebias);
+ }
+}
+
+void dump_tx_power_idx(void *sel, _adapter *adapter)
+{
+ u8 rfpath, rs;
+
+ dump_tx_power_idx_title(sel, adapter);
+ for (rfpath = RF_PATH_A; rfpath < RF_PATH_MAX; rfpath++)
+ for (rs = CCK; rs < RATE_SECTION_NUM; rs++)
+ dump_tx_power_idx_by_path_rs(sel, adapter, rfpath, rs);
+}
+
+bool phy_is_tx_power_limit_needed(_adapter *adapter)
+{
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter));
+#ifdef CONFIG_TXPWR_LIMIT
if (regsty->RegEnableTxPowerLimit == 1
- || (regsty->RegEnableTxPowerLimit == 2 && hal_data->EEPROMRegulatory == 1))
+ || (regsty->RegEnableTxPowerLimit == 2 && hal_data->EEPROMRegulatory == 1))
return _TRUE;
+#endif
+
return _FALSE;
}
-bool phy_is_tx_power_by_rate_needed(_adapter *adapter) {
+bool phy_is_tx_power_by_rate_needed(_adapter *adapter)
+{
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter));
if (regsty->RegEnableTxPowerByRate == 1
- || (regsty->RegEnableTxPowerByRate == 2 && hal_data->EEPROMRegulatory != 2))
+ || (regsty->RegEnableTxPowerByRate == 2 && hal_data->EEPROMRegulatory != 2))
return _TRUE;
return _FALSE;
}
-int phy_load_tx_power_by_rate(_adapter *adapter, const char *hal_file_name, u8 force) {
+int phy_load_tx_power_by_rate(_adapter *adapter, u8 chk_file)
+{
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter));
int ret = _FAIL;
- if (!force
- && !rtw_is_phy_file_readable(hal_file_name)
- && hal_data->txpwr_by_rate_loaded == 1
- && hal_data->txpwr_by_rate_from_file == 0
- ) {
- /* No file and already load default(compile-time) table */
- ret = _SUCCESS;
- goto exit;
- }
-
hal_data->txpwr_by_rate_loaded = 0;
PHY_InitTxPowerByRate(adapter);
@@ -2803,16 +3762,16 @@ int phy_load_tx_power_by_rate(_adapter *adapter, const char *hal_file_name, u8 f
hal_data->txpwr_limit_loaded = 0;
#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
- if (rtw_is_phy_file_readable(hal_file_name)
- && phy_ConfigBBWithPgParaFile(adapter, hal_file_name) == _SUCCESS
- ) {
+ if (chk_file
+ && phy_ConfigBBWithPgParaFile(adapter, PHY_FILE_PHY_REG_PG) == _SUCCESS
+ ) {
hal_data->txpwr_by_rate_from_file = 1;
goto post_hdl;
}
#endif
#ifdef CONFIG_EMBEDDED_FWIMG
- if (HAL_STATUS_SUCCESS == ODM_ConfigBBWithHeaderFile(&hal_data->odmpriv, CONFIG_BB_PHY_REG_PG)) {
+ if (HAL_STATUS_SUCCESS == odm_config_bb_with_header_file(&hal_data->odmpriv, CONFIG_BB_PHY_REG_PG)) {
RTW_INFO("default power by rate loaded\n");
hal_data->txpwr_by_rate_from_file = 0;
goto post_hdl;
@@ -2823,7 +3782,7 @@ int phy_load_tx_power_by_rate(_adapter *adapter, const char *hal_file_name, u8 f
goto exit;
post_hdl:
- if (hal_data->odmpriv.PhyRegPgValueType != PHY_REG_PG_EXACT_VALUE) {
+ if (hal_data->odmpriv.phy_reg_pg_value_type != PHY_REG_PG_EXACT_VALUE) {
rtw_warn_on(1);
goto exit;
}
@@ -2831,264 +3790,116 @@ int phy_load_tx_power_by_rate(_adapter *adapter, const char *hal_file_name, u8 f
PHY_TxPowerByRateConfiguration(adapter);
hal_data->txpwr_by_rate_loaded = 1;
- ret = _SUCCESS;
-
-exit:
- return ret;
-}
-
-int phy_load_tx_power_limit(_adapter *adapter, const char *hal_file_name, u8 force) {
- HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
- struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter));
- int ret = _FAIL;
-
- if (!force
- && !rtw_is_phy_file_readable(hal_file_name)
- && hal_data->txpwr_by_rate_loaded == 1
- && hal_data->txpwr_by_rate_from_file == 0
- ) {
- /* No file and already load default(compile-time) table */
- ret = _SUCCESS;
- goto exit;
- }
-
- hal_data->txpwr_limit_loaded = 0;
- PHY_InitTxPowerLimit(adapter);
-
- if (!hal_data->txpwr_by_rate_loaded && regsty->target_tx_pwr_valid != _TRUE) {
- RTW_ERR("%s():Read Tx power limit before target tx power is specify\n", __func__);
- goto exit;
- }
-
-#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
- if (rtw_is_phy_file_readable(hal_file_name)
- && PHY_ConfigRFWithPowerLimitTableParaFile(adapter, hal_file_name) == _SUCCESS
- ) {
- hal_data->txpwr_limit_from_file = 1;
- goto post_hdl;
- }
-#endif
-
-#ifdef CONFIG_EMBEDDED_FWIMG
- if (HAL_STATUS_SUCCESS == ODM_ConfigRFWithHeaderFile(&hal_data->odmpriv, CONFIG_RF_TXPWR_LMT, (ODM_RF_RADIO_PATH_E)0)) {
- RTW_INFO("default power limit loaded\n");
- hal_data->txpwr_limit_from_file = 0;
- goto post_hdl;
- }
-#endif
-
- RTW_ERR("%s():Read Tx power limit fail\n", __func__);
- goto exit;
-
-post_hdl:
- PHY_ConvertTxPowerLimitToPowerIndex(adapter);
- hal_data->txpwr_limit_loaded = 1;
- ret = _SUCCESS;
-
-exit:
- return ret;
-}
-
-const char *hal_phy_reg_pg_str(_adapter *adapter) {
- u8 interface_type = 0;
- const char *str = NULL;
-
- interface_type = rtw_get_intf_type(adapter);
-
- switch (rtw_get_chip_type(adapter)) {
-#ifdef CONFIG_RTL8723B
- case RTL8723B:
- str = RTL8723B_PHY_REG_PG;
- break;
-#endif
-#ifdef CONFIG_RTL8703B
- case RTL8703B:
- str = RTL8703B_PHY_REG_PG;
- break;
-#endif
-#ifdef CONFIG_RTL8723D
- case RTL8723D:
- str = RTL8723D_PHY_REG_PG;
- break;
-#endif
-#ifdef CONFIG_RTL8188E
- case RTL8188E:
- str = RTL8188E_PHY_REG_PG;
- break;
-#endif
-#ifdef CONFIG_RTL8188F
- case RTL8188F:
- str = RTL8188F_PHY_REG_PG;
- break;
-#endif
-#ifdef CONFIG_RTL8812A
- case RTL8812:
- str = RTL8812_PHY_REG_PG;
- break;
-#endif
-#ifdef CONFIG_RTL8821A
- case RTL8821:
- str = RTL8821_PHY_REG_PG;
- break;
-#endif
-#ifdef CONFIG_RTL8192E
- case RTL8192E:
- str = RTL8192E_PHY_REG_PG;
- break;
-#endif
-#ifdef CONFIG_RTL8814A
- case RTL8814A:
- str = RTL8814A_PHY_REG_PG;
- break;
-#endif
-#ifdef CONFIG_RTL8822B
- case RTL8822B:
- str = RTL8822B_PHY_REG_PG;
- break;
-#endif
-#ifdef CONFIG_RTL8821C
- case RTL8821C:
- str = RTL8821C_PHY_REG_PG;
- break;
-#endif
- }
-
- if (str == NULL) {
- RTW_ERR("%s: unknown chip_type:%u\n"
- , __func__, rtw_get_chip_type(adapter));
- }
-
- return str;
+ ret = _SUCCESS;
+
+exit:
+ return ret;
}
-const char *hal_txpwr_lmt_str(_adapter *adapter) {
- u8 interface_type = 0;
- const char *str = NULL;
+#ifdef CONFIG_TXPWR_LIMIT
+int phy_load_tx_power_limit(_adapter *adapter, u8 chk_file)
+{
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+ struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter));
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+ int ret = _FAIL;
- interface_type = rtw_get_intf_type(adapter);
+ hal_data->txpwr_limit_loaded = 0;
+ rtw_regd_exc_list_free(rfctl);
+ rtw_txpwr_lmt_list_free(rfctl);
- switch (rtw_get_chip_type(adapter)) {
-#ifdef CONFIG_RTL8723B
- case RTL8723B:
- str = RTL8723B_TXPWR_LMT;
- break;
-#endif
-#ifdef CONFIG_RTL8703B
- case RTL8703B:
- str = RTL8703B_TXPWR_LMT;
- break;
-#endif
-#ifdef CONFIG_RTL8723D
- case RTL8723D:
- str = RTL8723D_TXPWR_LMT;
- break;
-#endif
-#ifdef CONFIG_RTL8188E
- case RTL8188E:
- str = RTL8188E_TXPWR_LMT;
- break;
-#endif
-#ifdef CONFIG_RTL8188F
- case RTL8188F:
- str = RTL8188F_TXPWR_LMT;
- break;
-#endif
-#ifdef CONFIG_RTL8812A
- case RTL8812:
- str = RTL8812_TXPWR_LMT;
- break;
-#endif
-#ifdef CONFIG_RTL8821A
- case RTL8821:
- str = RTL8821_TXPWR_LMT;
- break;
-#endif
-#ifdef CONFIG_RTL8192E
- case RTL8192E:
- str = RTL8192E_TXPWR_LMT;
- break;
-#endif
-#ifdef CONFIG_RTL8814A
- case RTL8814A:
- str = RTL8814A_TXPWR_LMT;
- break;
-#endif
-#ifdef CONFIG_RTL8822B
- case RTL8822B:
- str = RTL8822B_TXPWR_LMT;
- break;
-#endif
-#ifdef CONFIG_RTL8821C
- case RTL8821C:
- str = RTL8821C_TXPWR_LMT;
- break;
-#endif
+ if (!hal_data->txpwr_by_rate_loaded && regsty->target_tx_pwr_valid != _TRUE) {
+ RTW_ERR("%s():Read Tx power limit before target tx power is specify\n", __func__);
+ goto exit;
}
- if (str == NULL) {
- RTW_ERR("%s: unknown chip_type:%u\n"
- , __func__, rtw_get_chip_type(adapter));
+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
+ if (chk_file
+ && PHY_ConfigRFWithPowerLimitTableParaFile(adapter, PHY_FILE_TXPWR_LMT) == _SUCCESS
+ ) {
+ hal_data->txpwr_limit_from_file = 1;
+ goto post_hdl;
+ }
+#endif
+
+#ifdef CONFIG_EMBEDDED_FWIMG
+ if (odm_config_rf_with_header_file(&hal_data->odmpriv, CONFIG_RF_TXPWR_LMT, RF_PATH_A) == HAL_STATUS_SUCCESS) {
+ RTW_INFO("default power limit loaded\n");
+ hal_data->txpwr_limit_from_file = 0;
+ goto post_hdl;
}
+#endif
+
+ RTW_ERR("%s():Read Tx power limit fail\n", __func__);
+ goto exit;
+
+post_hdl:
+ phy_txpwr_lmt_post_hdl(adapter);
+ rtw_txpwr_init_regd(rfctl);
+ hal_data->txpwr_limit_loaded = 1;
+ ret = _SUCCESS;
- return str;
+exit:
+ return ret;
}
+#endif /* CONFIG_TXPWR_LIMIT */
-void phy_load_tx_power_ext_info(_adapter *adapter, u8 chk_file, u8 force) {
+void phy_load_tx_power_ext_info(_adapter *adapter, u8 chk_file)
+{
struct registry_priv *regsty = adapter_to_regsty(adapter);
- const char *str = NULL;
/* check registy target tx power */
regsty->target_tx_pwr_valid = rtw_regsty_chk_target_tx_power_valid(adapter);
/* power by rate and limit */
if (phy_is_tx_power_by_rate_needed(adapter)
- || (phy_is_tx_power_limit_needed(adapter) && regsty->target_tx_pwr_valid != _TRUE)
- ) {
- str = chk_file ? hal_phy_reg_pg_str(adapter) : NULL;
- phy_load_tx_power_by_rate(adapter, str, force);
- }
+ || (phy_is_tx_power_limit_needed(adapter) && regsty->target_tx_pwr_valid != _TRUE)
+ )
+ phy_load_tx_power_by_rate(adapter, chk_file);
- if (phy_is_tx_power_limit_needed(adapter)) {
- str = chk_file ? hal_txpwr_lmt_str(adapter) : NULL;
- phy_load_tx_power_limit(adapter, str, force);
- }
+#ifdef CONFIG_TXPWR_LIMIT
+ if (phy_is_tx_power_limit_needed(adapter))
+ phy_load_tx_power_limit(adapter, chk_file);
+#endif
}
-inline void phy_reload_tx_power_ext_info(_adapter *adapter) {
- phy_load_tx_power_ext_info(adapter, 1, 1);
+inline void phy_reload_tx_power_ext_info(_adapter *adapter)
+{
+ phy_load_tx_power_ext_info(adapter, 1);
}
-inline void phy_reload_default_tx_power_ext_info(_adapter *adapter) {
- phy_load_tx_power_ext_info(adapter, 0, 1);
+inline void phy_reload_default_tx_power_ext_info(_adapter *adapter)
+{
+ phy_load_tx_power_ext_info(adapter, 0);
}
-void dump_tx_power_ext_info(void *sel, _adapter *adapter) {
+void dump_tx_power_ext_info(void *sel, _adapter *adapter)
+{
struct registry_priv *regsty = adapter_to_regsty(adapter);
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
- if (phy_is_tx_power_by_rate_needed(adapter)
- || (phy_is_tx_power_limit_needed(adapter) && regsty->target_tx_pwr_valid != _TRUE))
- RTW_PRINT_SEL(sel, "target_tx_power: from powr by rate\n");
- else if (regsty->target_tx_pwr_valid == _TRUE)
+ if (regsty->target_tx_pwr_valid == _TRUE)
RTW_PRINT_SEL(sel, "target_tx_power: from registry\n");
+ else if (phy_is_tx_power_by_rate_needed(adapter))
+ RTW_PRINT_SEL(sel, "target_tx_power: from power by rate\n");
else
RTW_PRINT_SEL(sel, "target_tx_power: unavailable\n");
-
RTW_PRINT_SEL(sel, "tx_power_by_rate: %s, %s, %s\n"
- , phy_is_tx_power_by_rate_needed(adapter) ? "enabled" : "disabled"
- , hal_data->txpwr_by_rate_loaded ? "loaded" : "unloaded"
- , hal_data->txpwr_by_rate_from_file ? "file" : "default"
- );
+ , phy_is_tx_power_by_rate_needed(adapter) ? "enabled" : "disabled"
+ , hal_data->txpwr_by_rate_loaded ? "loaded" : "unloaded"
+ , hal_data->txpwr_by_rate_from_file ? "file" : "default"
+ );
RTW_PRINT_SEL(sel, "tx_power_limit: %s, %s, %s\n"
- , phy_is_tx_power_limit_needed(adapter) ? "enabled" : "disabled"
- , hal_data->txpwr_limit_loaded ? "loaded" : "unloaded"
- , hal_data->txpwr_limit_from_file ? "file" : "default"
- );
+ , phy_is_tx_power_limit_needed(adapter) ? "enabled" : "disabled"
+ , hal_data->txpwr_limit_loaded ? "loaded" : "unloaded"
+ , hal_data->txpwr_limit_from_file ? "file" : "default"
+ );
}
-void dump_target_tx_power(void *sel, _adapter *adapter) {
+void dump_target_tx_power(void *sel, _adapter *adapter)
+{
struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
struct registry_priv *regsty = adapter_to_regsty(adapter);
@@ -3100,14 +3911,15 @@ void dump_target_tx_power(void *sel, _adapter *adapter) {
continue;
for (path = 0; path < RF_PATH_MAX; path++) {
- if (path >= hal_data->NumTotalRFPath)
+ if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
break;
- RTW_PRINT_SEL(sel, "[%s][%c]\n", band_str(band), rf_path_char(path));
+ RTW_PRINT_SEL(sel, "[%s][%c]%s\n", band_str(band), rf_path_char(path)
+ , (regsty->target_tx_pwr_valid == _FALSE && hal_data->txpwr_by_rate_undefined_band_path[band][path]) ? "(dup)" : "");
for (rs = 0; rs < RATE_SECTION_NUM; rs++) {
tx_num = rate_section_to_tx_num(rs);
- if (tx_num >= hal_spec->nss_num)
+ if (tx_num >= hal_spec->tx_nss_num)
continue;
if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
@@ -3116,7 +3928,7 @@ void dump_target_tx_power(void *sel, _adapter *adapter) {
if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter))
continue;
- target = phy_get_target_tx_power(adapter, band, path, rs);
+ target = PHY_GetTxPowerByRateBase(adapter, band, path, rs);
if (target % 2)
_RTW_PRINT_SEL(sel, "%7s: %2d.5\n", rate_section_str(rs), target / 2);
@@ -3130,7 +3942,8 @@ void dump_target_tx_power(void *sel, _adapter *adapter) {
return;
}
-void dump_tx_power_by_rate(void *sel, _adapter *adapter) {
+void dump_tx_power_by_rate(void *sel, _adapter *adapter)
+{
struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
int path, tx_num, band, n, rs;
@@ -3142,14 +3955,15 @@ void dump_tx_power_by_rate(void *sel, _adapter *adapter) {
continue;
for (path = 0; path < RF_PATH_MAX; path++) {
- if (path >= hal_data->NumTotalRFPath)
+ if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path))
break;
- RTW_PRINT_SEL(sel, "[%s][%c]\n", band_str(band), rf_path_char(path));
+ RTW_PRINT_SEL(sel, "[%s][%c]%s\n", band_str(band), rf_path_char(path)
+ , hal_data->txpwr_by_rate_undefined_band_path[band][path] ? "(dup)" : "");
for (rs = 0; rs < RATE_SECTION_NUM; rs++) {
tx_num = rate_section_to_tx_num(rs);
- if (tx_num >= hal_spec->nss_num)
+ if (tx_num >= hal_spec->tx_nss_num)
continue;
if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
@@ -3163,13 +3977,13 @@ void dump_tx_power_by_rate(void *sel, _adapter *adapter) {
else
max_rate_num = 8;
rate_num = rate_section_rate_num(rs);
- base = PHY_GetTxPowerByRateBase(adapter, band, path, tx_num, rs);
+ base = PHY_GetTxPowerByRateBase(adapter, band, path, rs);
RTW_PRINT_SEL(sel, "%7s: ", rate_section_str(rs));
/* dump power by rate in db */
for (n = rate_num - 1; n >= 0; n--) {
- by_rate_offset = PHY_GetTxPowerByRate(adapter, band, path, tx_num, rates_by_sections[rs].rates[n]);
+ by_rate_offset = PHY_GetTxPowerByRate(adapter, band, path, rates_by_sections[rs].rates[n]);
if ((base + by_rate_offset) % 2)
_RTW_PRINT_SEL(sel, "%2d.5 ", (base + by_rate_offset) / 2);
@@ -3183,7 +3997,7 @@ void dump_tx_power_by_rate(void *sel, _adapter *adapter) {
/* dump power by rate in offset */
for (n = rate_num - 1; n >= 0; n--) {
- by_rate_offset = PHY_GetTxPowerByRate(adapter, band, path, tx_num, rates_by_sections[rs].rates[n]);
+ by_rate_offset = PHY_GetTxPowerByRate(adapter, band, path, rates_by_sections[rs].rates[n]);
_RTW_PRINT_SEL(sel, "%3d ", by_rate_offset);
}
RTW_PRINT_SEL(sel, "\n");
@@ -3193,184 +4007,24 @@ void dump_tx_power_by_rate(void *sel, _adapter *adapter) {
}
}
-void dump_tx_power_limit(void *sel, _adapter *adapter) {
+/*
+ * phy file path is stored in global char array rtw_phy_para_file_path
+ * need to care about racing
+ */
+int rtw_get_phy_file_path(_adapter *adapter, const char *file_name)
+{
+#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
- HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
- struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter));
-
- int bw, band, ch_num, rs, i, path;
- u8 ch, n, rd;
-
- if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter))
- RTW_PRINT_SEL(sel, "tx_pwr_lmt_5g_20_40_ref:0x%02x\n", hal_data->tx_pwr_lmt_5g_20_40_ref);
-
- for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) {
- if (!hal_is_band_support(adapter, band))
- continue;
-
- rd = (band == BAND_ON_2_4G ? hal_data->Regulation2_4G : hal_data->Regulation5G);
-
- for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; bw++) {
-
- if (bw >= CHANNEL_WIDTH_160)
- break;
- if (band == BAND_ON_2_4G && bw >= CHANNEL_WIDTH_80)
- break;
-
- if (band == BAND_ON_2_4G)
- ch_num = CENTER_CH_2G_NUM;
- else
- ch_num = center_chs_5g_num(bw);
-
- if (ch_num == 0) {
- rtw_warn_on(1);
- break;
- }
-
- for (rs = 0; rs < RATE_SECTION_NUM; rs++) {
- if (band == BAND_ON_2_4G && IS_VHT_RATE_SECTION(rs))
- continue;
- if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs))
- continue;
- if (bw > CHANNEL_WIDTH_20 && (IS_CCK_RATE_SECTION(rs) || IS_OFDM_RATE_SECTION(rs)))
- continue;
- if (bw > CHANNEL_WIDTH_40 && IS_HT_RATE_SECTION(rs))
- continue;
-
- if (rate_section_to_tx_num(rs) >= hal_spec->nss_num)
- continue;
-
- if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter))
- continue;
-
- /* by pass 5G 20M, 40M pure reference */
- if (band == BAND_ON_5G && (bw == CHANNEL_WIDTH_20 || bw == CHANNEL_WIDTH_40)) {
- if (hal_data->tx_pwr_lmt_5g_20_40_ref == TX_PWR_LMT_REF_HT_FROM_VHT) {
- if (IS_HT_RATE_SECTION(rs))
- continue;
- } else if (hal_data->tx_pwr_lmt_5g_20_40_ref == TX_PWR_LMT_REF_VHT_FROM_HT) {
- if (IS_VHT_RATE_SECTION(rs) && bw <= CHANNEL_WIDTH_40)
- continue;
- }
- }
-
- RTW_PRINT_SEL(sel, "[%s][%s][%s]\n"
- , band_str(band)
- , ch_width_str(bw)
- , rate_section_str(rs)
- );
-
- /* header for limit in db */
- RTW_PRINT_SEL(sel, "%3s %5s %5s %5s %5s "
- , "ch"
- , (rd == TXPWR_LMT_FCC ? "*FCC" : "FCC")
- , (rd == TXPWR_LMT_ETSI ? "*ETSI" : "ETSI")
- , (rd == TXPWR_LMT_MKK ? "*MKK" : "MKK")
- , (rd == TXPWR_LMT_WW ? "*WW" : "WW")
- );
-
- /* header for limit offset */
- for (path = 0; path < RF_PATH_MAX; path++) {
- if (path >= hal_data->NumTotalRFPath)
- break;
- _RTW_PRINT_SEL(sel, "|%3c %3c %3c %3c "
- , (rd == TXPWR_LMT_FCC ? rf_path_char(path) : ' ')
- , (rd == TXPWR_LMT_ETSI ? rf_path_char(path) : ' ')
- , (rd == TXPWR_LMT_MKK ? rf_path_char(path) : ' ')
- , (rd == TXPWR_LMT_WW ? rf_path_char(path) : ' ')
- );
- }
- _RTW_PRINT_SEL(sel, "\n");
-
- for (n = 0; n < ch_num; n++) {
- s8 limit_idx[RF_PATH_MAX][MAX_REGULATION_NUM];
- s8 limit_offset[MAX_REGULATION_NUM];
- u8 base;
-
- if (band == BAND_ON_2_4G)
- ch = n + 1;
- else
- ch = center_chs_5g(bw, n);
-
- if (ch == 0) {
- rtw_warn_on(1);
- break;
- }
-
- /* dump limit in db (calculate from path A) */
- limit_offset[0] = PHY_GetTxPowerLimit(adapter, 3, band, bw, RF_PATH_A, rates_by_sections[rs].rates[0], ch); /* FCC */
- limit_offset[1] = PHY_GetTxPowerLimit(adapter, 1, band, bw, RF_PATH_A, rates_by_sections[rs].rates[0], ch); /* ETSI */
- limit_offset[2] = PHY_GetTxPowerLimit(adapter, 2, band, bw, RF_PATH_A, rates_by_sections[rs].rates[0], ch); /* MKK */
- limit_offset[3] = PHY_GetTxPowerLimit(adapter, 4, band, bw, RF_PATH_A, rates_by_sections[rs].rates[0], ch); /* WW */
-
- base = phy_get_target_tx_power(adapter, band, RF_PATH_A, rs);
-
- RTW_PRINT_SEL(sel, "%3u ", ch);
- for (i = 0; i < MAX_REGULATION_NUM; i++) {
- if (limit_offset[i] == MAX_POWER_INDEX) {
- limit_idx[0][i] = MAX_POWER_INDEX;
- _RTW_PRINT_SEL(sel, "%5s ", "NA");
- } else {
- limit_idx[0][i] = limit_offset[i] + base;
- if ((limit_offset[i] + base) % 2)
- _RTW_PRINT_SEL(sel, "%3d.5 ", (limit_offset[i] + base) / 2);
- else
- _RTW_PRINT_SEL(sel, "%5d ", (limit_offset[i] + base) / 2);
- }
- }
-
- /* dump limit offset of each path */
- for (path = 0; path < RF_PATH_MAX; path++) {
- if (path >= hal_data->NumTotalRFPath)
- break;
- limit_offset[0] = PHY_GetTxPowerLimit(adapter, 3, band, bw, path, rates_by_sections[rs].rates[0], ch); /* FCC */
- limit_offset[1] = PHY_GetTxPowerLimit(adapter, 1, band, bw, path, rates_by_sections[rs].rates[0], ch); /* ETSI */
- limit_offset[2] = PHY_GetTxPowerLimit(adapter, 2, band, bw, path, rates_by_sections[rs].rates[0], ch); /* MKK */
- limit_offset[3] = PHY_GetTxPowerLimit(adapter, 4, band, bw, path, rates_by_sections[rs].rates[0], ch); /* WW */
-
- base = phy_get_target_tx_power(adapter, band, path, rs);
-
- _RTW_PRINT_SEL(sel, "|");
- for (i = 0; i < MAX_REGULATION_NUM; i++) {
- if (limit_offset[i] == MAX_POWER_INDEX) {
- limit_idx[path][i] = MAX_POWER_INDEX;
- _RTW_PRINT_SEL(sel, "%3s ", "NA");
- } else {
- limit_idx[path][i] = limit_offset[i] + base;
- _RTW_PRINT_SEL(sel, "%3d ", limit_offset[i]);
- }
- }
- }
-
- /* compare limit_idx of each path, print 'x' when mismatch */
- if (hal_data->NumTotalRFPath > 1) {
- for (i = 0; i < MAX_REGULATION_NUM; i++) {
- for (path = 0; path < RF_PATH_MAX; path++) {
- if (path >= hal_data->NumTotalRFPath)
- break;
- if (limit_idx[path][i] != limit_idx[(path + 1) % hal_data->NumTotalRFPath][i])
- break;
- }
- if (path >= hal_data->NumTotalRFPath)
- _RTW_PRINT_SEL(sel, " ");
- else
- _RTW_PRINT_SEL(sel, "x");
- }
- }
- _RTW_PRINT_SEL(sel, "\n");
+ int len = 0;
- }
- RTW_PRINT_SEL(sel, "\n");
- }
- }
- }
-}
+ if (file_name) {
+ len += snprintf(rtw_phy_para_file_path, PATH_LENGTH_MAX, "%s", rtw_phy_file_path);
+ #if defined(CONFIG_MULTIDRV) || defined(REALTEK_CONFIG_PATH_WITH_IC_NAME_FOLDER)
+ len += snprintf(rtw_phy_para_file_path + len, PATH_LENGTH_MAX - len, "%s/", hal_spec->ic_name);
+ #endif
+ len += snprintf(rtw_phy_para_file_path + len, PATH_LENGTH_MAX - len, "%s", file_name);
-int rtw_is_phy_file_readable(const char *hal_file_name) {
-#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
- if (hal_file_name) {
- rtw_merge_string(rtw_phy_para_file_path, PATH_LENGTH_MAX, rtw_phy_file_path, hal_file_name);
- return rtw_is_file_readable(rtw_phy_para_file_path);
+ return _TRUE;
}
#endif
return _FALSE;
@@ -3379,9 +4033,10 @@ int rtw_is_phy_file_readable(const char *hal_file_name) {
#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
int
phy_ConfigMACWithParaFile(
- IN PADAPTER Adapter,
- IN char *pFileName
-) {
+ IN PADAPTER Adapter,
+ IN char *pFileName
+)
+{
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
int rlen = 0, rtStatus = _FAIL;
char *szLine, *ptmp;
@@ -3393,8 +4048,7 @@ phy_ConfigMACWithParaFile(
_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
if ((pHalData->mac_reg_len == 0) && (pHalData->mac_reg == NULL)) {
- rtw_merge_string(rtw_phy_para_file_path, PATH_LENGTH_MAX, rtw_phy_file_path, pFileName);
-
+ rtw_get_phy_file_path(Adapter, pFileName);
if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) {
rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
if (rlen > 0) {
@@ -3441,10 +4095,11 @@ phy_ConfigMACWithParaFile(
int
phy_ConfigBBWithParaFile(
- IN PADAPTER Adapter,
- IN char *pFileName,
- IN u32 ConfigType
-) {
+ IN PADAPTER Adapter,
+ IN char *pFileName,
+ IN u32 ConfigType
+)
+{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
int rlen = 0, rtStatus = _FAIL;
char *szLine, *ptmp;
@@ -3472,8 +4127,7 @@ phy_ConfigBBWithParaFile(
_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
if ((pBufLen != NULL) && (*pBufLen == 0) && (pBuf == NULL)) {
- rtw_merge_string(rtw_phy_para_file_path, PATH_LENGTH_MAX, rtw_phy_file_path, pFileName);
-
+ rtw_get_phy_file_path(Adapter, pFileName);
if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) {
rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
if (rlen > 0) {
@@ -3533,10 +4187,10 @@ phy_ConfigBBWithParaFile(
szLine += u4bMove;
if (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) {
/* RTW_INFO("[BB-ADDR]%03lX=%08lX\n", u4bRegOffset, u4bRegValue); */
- PHY_SetBBReg(Adapter, u4bRegOffset, bMaskDWord, u4bRegValue);
+ phy_set_bb_reg(Adapter, u4bRegOffset, bMaskDWord, u4bRegValue);
if (u4bRegOffset == 0xa24)
- pHalData->odmpriv.RFCalibrateInfo.RegA24 = u4bRegValue;
+ pHalData->odmpriv.rf_calibrate_info.rega24 = u4bRegValue;
/* Add 1us delay between BB/RF register setting. */
rtw_udelay_os(1);
@@ -3552,9 +4206,10 @@ phy_ConfigBBWithParaFile(
VOID
phy_DecryptBBPgParaFile(
- PADAPTER Adapter,
- char *buffer
-) {
+ PADAPTER Adapter,
+ char *buffer
+)
+{
u32 i = 0, j = 0;
u8 map[95] = {0};
u8 currentChar;
@@ -3589,9 +4244,10 @@ phy_DecryptBBPgParaFile(
int
phy_ParseBBPgParaFile(
- PADAPTER Adapter,
- char *buffer
-) {
+ PADAPTER Adapter,
+ char *buffer
+)
+{
int rtStatus = _SUCCESS;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
char *szLine, *ptmp;
@@ -3616,10 +4272,10 @@ phy_ParseBBPgParaFile(
if (firstLine) {
if (eqNByte(szLine, (u8 *)("#[v1]"), 5)) {
- pHalData->odmpriv.PhyRegPgVersion = szLine[3] - '0';
+ pHalData->odmpriv.phy_reg_pg_version = szLine[3] - '0';
/* RTW_INFO("This is a new format PHY_REG_PG.txt\n"); */
} else if (eqNByte(szLine, (u8 *)("#[v0]"), 5)) {
- pHalData->odmpriv.PhyRegPgVersion = szLine[3] - '0';
+ pHalData->odmpriv.phy_reg_pg_version = szLine[3] - '0';
/* RTW_INFO("This is a old format PHY_REG_PG.txt ok\n"); */
} else {
RTW_INFO("The format in PHY_REG_PG are invalid %s\n", szLine);
@@ -3627,12 +4283,12 @@ phy_ParseBBPgParaFile(
}
if (eqNByte(szLine + 5, (u8 *)("[Exact]#"), 8)) {
- pHalData->odmpriv.PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE;
+ pHalData->odmpriv.phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE;
/* RTW_INFO("The values in PHY_REG_PG are exact values ok\n"); */
firstLine = _FALSE;
continue;
} else if (eqNByte(szLine + 5, (pu1Byte)("[Relative]#"), 11)) {
- pHalData->odmpriv.PhyRegPgValueType = PHY_REG_PG_RELATIVE_VALUE;
+ pHalData->odmpriv.phy_reg_pg_value_type = PHY_REG_PG_RELATIVE_VALUE;
/* RTW_INFO("The values in PHY_REG_PG are relative values ok\n"); */
firstLine = _FALSE;
continue;
@@ -3642,7 +4298,7 @@ phy_ParseBBPgParaFile(
}
}
- if (pHalData->odmpriv.PhyRegPgVersion == 0) {
+ if (pHalData->odmpriv.phy_reg_pg_version == 0) {
/* Get 1st hex value as register offset. */
if (GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) {
szLine += u4bMove;
@@ -3657,14 +4313,14 @@ phy_ParseBBPgParaFile(
else
return _FAIL;
- if (pHalData->odmpriv.PhyRegPgValueType == PHY_REG_PG_RELATIVE_VALUE) {
+ if (pHalData->odmpriv.phy_reg_pg_value_type == PHY_REG_PG_RELATIVE_VALUE) {
/* Get 3rd hex value as register value. */
if (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) {
- PHY_StoreTxPowerByRate(Adapter, 0, 0, 1, u4bRegOffset, u4bRegMask, u4bRegValue);
+ phy_store_tx_power_by_rate(Adapter, 0, 0, 1, u4bRegOffset, u4bRegMask, u4bRegValue);
/* RTW_INFO("[ADDR] %03X=%08X Mask=%08x\n", u4bRegOffset, u4bRegValue, u4bRegMask); */
} else
return _FAIL;
- } else if (pHalData->odmpriv.PhyRegPgValueType == PHY_REG_PG_EXACT_VALUE) {
+ } else if (pHalData->odmpriv.phy_reg_pg_value_type == PHY_REG_PG_EXACT_VALUE) {
u32 combineValue = 0;
u8 integer = 0, fraction = 0;
@@ -3714,12 +4370,12 @@ phy_ParseBBPgParaFile(
combineValue <<= 8;
combineValue |= (((integer / 10) << 4) + (integer % 10));
/* RTW_INFO(" %d", integer ); */
- PHY_StoreTxPowerByRate(Adapter, 0, 0, 1, u4bRegOffset, u4bRegMask, combineValue);
+ phy_store_tx_power_by_rate(Adapter, 0, 0, 1, u4bRegOffset, u4bRegMask, combineValue);
/* RTW_INFO("[ADDR] 0x%3x = 0x%4x\n", u4bRegOffset, combineValue ); */
}
}
- } else if (pHalData->odmpriv.PhyRegPgVersion > 0) {
+ } else if (pHalData->odmpriv.phy_reg_pg_version > 0) {
u32 index = 0, cnt = 0;
if (eqNByte(szLine, "0xffff", 6))
@@ -3773,14 +4429,14 @@ phy_ParseBBPgParaFile(
else
return _FAIL;
- if (pHalData->odmpriv.PhyRegPgValueType == PHY_REG_PG_RELATIVE_VALUE) {
+ if (pHalData->odmpriv.phy_reg_pg_value_type == PHY_REG_PG_RELATIVE_VALUE) {
/* Get 3rd hex value as register value. */
if (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) {
- PHY_StoreTxPowerByRate(Adapter, band, rf_path, tx_num, u4bRegOffset, u4bRegMask, u4bRegValue);
+ phy_store_tx_power_by_rate(Adapter, band, rf_path, tx_num, u4bRegOffset, u4bRegMask, u4bRegValue);
/* RTW_INFO("[ADDR] %03X (tx_num %d) =%08X Mask=%08x\n", u4bRegOffset, tx_num, u4bRegValue, u4bRegMask); */
} else
return _FAIL;
- } else if (pHalData->odmpriv.PhyRegPgValueType == PHY_REG_PG_EXACT_VALUE) {
+ } else if (pHalData->odmpriv.phy_reg_pg_value_type == PHY_REG_PG_EXACT_VALUE) {
u32 combineValue = 0;
u8 integer = 0, fraction = 0;
@@ -3830,7 +4486,7 @@ phy_ParseBBPgParaFile(
combineValue <<= 8;
combineValue |= (((integer / 10) << 4) + (integer % 10));
/* RTW_INFO(" %d", integer ); */
- PHY_StoreTxPowerByRate(Adapter, band, rf_path, tx_num, u4bRegOffset, u4bRegMask, combineValue);
+ phy_store_tx_power_by_rate(Adapter, band, rf_path, tx_num, u4bRegOffset, u4bRegMask, combineValue);
/* RTW_INFO("[ADDR] 0x%3x (tx_num %d) = 0x%4x\n", u4bRegOffset, tx_num, combineValue ); */
}
@@ -3845,8 +4501,9 @@ phy_ParseBBPgParaFile(
int
phy_ConfigBBWithPgParaFile(
- IN PADAPTER Adapter,
- IN const char *pFileName) {
+ IN PADAPTER Adapter,
+ IN const char *pFileName)
+{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
int rlen = 0, rtStatus = _FAIL;
@@ -3856,8 +4513,7 @@ phy_ConfigBBWithPgParaFile(
_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
if (pHalData->bb_phy_reg_pg == NULL) {
- rtw_merge_string(rtw_phy_para_file_path, PATH_LENGTH_MAX, rtw_phy_file_path, pFileName);
-
+ rtw_get_phy_file_path(Adapter, pFileName);
if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) {
rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
if (rlen > 0) {
@@ -3891,9 +4547,10 @@ phy_ConfigBBWithPgParaFile(
int
phy_ConfigBBWithMpParaFile(
- IN PADAPTER Adapter,
- IN char *pFileName
-) {
+ IN PADAPTER Adapter,
+ IN char *pFileName
+)
+{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
int rlen = 0, rtStatus = _FAIL;
char *szLine, *ptmp;
@@ -3905,8 +4562,7 @@ phy_ConfigBBWithMpParaFile(
_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
if ((pHalData->bb_phy_reg_mp_len == 0) && (pHalData->bb_phy_reg_mp == NULL)) {
- rtw_merge_string(rtw_phy_para_file_path, PATH_LENGTH_MAX, rtw_phy_file_path, pFileName);
-
+ rtw_get_phy_file_path(Adapter, pFileName);
if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) {
rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
if (rlen > 0) {
@@ -3959,7 +4615,7 @@ phy_ConfigBBWithMpParaFile(
szLine += u4bMove;
if (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) {
/* RTW_INFO("[ADDR]%03lX=%08lX\n", u4bRegOffset, u4bRegValue); */
- PHY_SetBBReg(Adapter, u4bRegOffset, bMaskDWord, u4bRegValue);
+ phy_set_bb_reg(Adapter, u4bRegOffset, bMaskDWord, u4bRegValue);
/* Add 1us delay between BB/RF register setting. */
rtw_udelay_os(1);
@@ -3977,10 +4633,11 @@ phy_ConfigBBWithMpParaFile(
int
PHY_ConfigRFWithParaFile(
- IN PADAPTER Adapter,
- IN char *pFileName,
- IN u8 eRFPath
-) {
+ IN PADAPTER Adapter,
+ IN char *pFileName,
+ IN enum rf_path eRFPath
+)
+{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
int rlen = 0, rtStatus = _FAIL;
char *szLine, *ptmp;
@@ -3993,11 +4650,11 @@ PHY_ConfigRFWithParaFile(
return rtStatus;
switch (eRFPath) {
- case ODM_RF_PATH_A:
+ case RF_PATH_A:
pBuf = pHalData->rf_radio_a;
pBufLen = &pHalData->rf_radio_a_len;
break;
- case ODM_RF_PATH_B:
+ case RF_PATH_B:
pBuf = pHalData->rf_radio_b;
pBufLen = &pHalData->rf_radio_b_len;
break;
@@ -4009,8 +4666,7 @@ PHY_ConfigRFWithParaFile(
_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
if ((pBufLen != NULL) && (*pBufLen == 0) && (pBuf == NULL)) {
- rtw_merge_string(rtw_phy_para_file_path, PATH_LENGTH_MAX, rtw_phy_file_path, pFileName);
-
+ rtw_get_phy_file_path(Adapter, pFileName);
if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) {
rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
if (rlen > 0) {
@@ -4021,12 +4677,15 @@ PHY_ConfigRFWithParaFile(
*pBufLen = rlen;
switch (eRFPath) {
- case ODM_RF_PATH_A:
+ case RF_PATH_A:
pHalData->rf_radio_a = pBuf;
break;
- case ODM_RF_PATH_B:
+ case RF_PATH_B:
pHalData->rf_radio_b = pBuf;
break;
+ default:
+ RTW_INFO("Unknown RF path!! %d\r\n", eRFPath);
+ break;
}
} else
RTW_INFO("%s(): eRFPath=%d alloc fail !\n", __FUNCTION__, eRFPath);
@@ -4075,7 +4734,7 @@ PHY_ConfigRFWithParaFile(
/* Get 2nd hex value as register value. */
szLine += u4bMove;
if (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) {
- PHY_SetRFReg(Adapter, eRFPath, u4bRegOffset, bRFRegOffsetMask, u4bRegValue);
+ phy_set_rf_reg(Adapter, eRFPath, u4bRegOffset, bRFRegOffsetMask, u4bRegValue);
/* Temp add, for frequency lock, if no delay, that may cause */
/* frequency shift, ex: 2412MHz => 2417MHz */
@@ -4098,14 +4757,15 @@ PHY_ConfigRFWithParaFile(
VOID
initDeltaSwingIndexTables(
- PADAPTER Adapter,
- char *Band,
- char *Path,
- char *Sign,
- char *Channel,
- char *Rate,
- char *Data
-) {
+ PADAPTER Adapter,
+ char *Band,
+ char *Path,
+ char *Sign,
+ char *Channel,
+ char *Rate,
+ char *Data
+)
+{
#define STR_EQUAL_5G(_band, _path, _sign, _rate, _chnl) \
((strcmp(Band, _band) == 0) && (strcmp(Path, _path) == 0) && (strcmp(Sign, _sign) == 0) &&\
(strcmp(Rate, _rate) == 0) && (strcmp(Channel, _chnl) == 0)\
@@ -4123,8 +4783,8 @@ initDeltaSwingIndexTables(
} } while (0)\
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
- PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
- PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
+ struct dm_struct *pDM_Odm = &pHalData->odmpriv;
+ struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
u32 j = 0;
char *token;
char delim[] = ",";
@@ -4134,65 +4794,66 @@ initDeltaSwingIndexTables(
/* Band, Path, Sign, Channel, Rate, Data); */
if (STR_EQUAL_2G("2G", "A", "+", "CCK"))
- STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, j);
+ STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_p, j);
else if (STR_EQUAL_2G("2G", "A", "-", "CCK"))
- STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, j);
+ STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_n, j);
else if (STR_EQUAL_2G("2G", "B", "+", "CCK"))
- STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, j);
+ STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_p, j);
else if (STR_EQUAL_2G("2G", "B", "-", "CCK"))
- STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, j);
+ STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_n, j);
else if (STR_EQUAL_2G("2G", "A", "+", "ALL"))
- STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, j);
+ STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2ga_p, j);
else if (STR_EQUAL_2G("2G", "A", "-", "ALL"))
- STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, j);
+ STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2ga_n, j);
else if (STR_EQUAL_2G("2G", "B", "+", "ALL"))
- STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, j);
+ STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2gb_p, j);
else if (STR_EQUAL_2G("2G", "B", "-", "ALL"))
- STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, j);
+ STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2gb_n, j);
else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "0"))
- STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[0], j);
+ STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_p[0], j);
else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "0"))
- STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[0], j);
+ STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_n[0], j);
else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "0"))
- STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[0], j);
+ STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_p[0], j);
else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "0"))
- STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[0], j);
+ STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_n[0], j);
else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "1"))
- STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[1], j);
+ STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_p[1], j);
else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "1"))
- STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[1], j);
+ STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_n[1], j);
else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "1"))
- STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[1], j);
+ STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_p[1], j);
else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "1"))
- STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[1], j);
+ STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_n[1], j);
else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "2"))
- STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[2], j);
+ STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_p[2], j);
else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "2"))
- STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[2], j);
+ STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_n[2], j);
else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "2"))
- STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[2], j);
+ STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_p[2], j);
else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "2"))
- STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[2], j);
+ STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_n[2], j);
else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "3"))
- STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[3], j);
+ STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_p[3], j);
else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "3"))
- STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[3], j);
+ STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_n[3], j);
else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "3"))
- STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[3], j);
+ STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_p[3], j);
else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "3"))
- STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[3], j);
+ STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_n[3], j);
else
RTW_INFO("===>initDeltaSwingIndexTables(): The input is invalid!!\n");
}
int
PHY_ConfigRFWithTxPwrTrackParaFile(
- IN PADAPTER Adapter,
- IN char *pFileName
-) {
+ IN PADAPTER Adapter,
+ IN char *pFileName
+)
+{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
- PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
- PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
+ struct dm_struct *pDM_Odm = &pHalData->odmpriv;
+ struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
int rlen = 0, rtStatus = _FAIL;
char *szLine, *ptmp;
u32 i = 0, j = 0;
@@ -4204,8 +4865,7 @@ PHY_ConfigRFWithTxPwrTrackParaFile(
_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
if ((pHalData->rf_tx_pwr_track_len == 0) && (pHalData->rf_tx_pwr_track == NULL)) {
- rtw_merge_string(rtw_phy_para_file_path, PATH_LENGTH_MAX, rtw_phy_file_path, pFileName);
-
+ rtw_get_phy_file_path(Adapter, pFileName);
if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) {
rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
if (rlen > 0) {
@@ -4263,42 +4923,164 @@ PHY_ConfigRFWithTxPwrTrackParaFile(
RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName);
#if 0
for (i = 0; i < DELTA_SWINGIDX_SIZE; ++i) {
- RTW_INFO("pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P[%d] = %d\n", i, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P[i]);
- RTW_INFO("pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N[%d] = %d\n", i, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N[i]);
- RTW_INFO("pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P[%d] = %d\n", i, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P[i]);
- RTW_INFO("pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N[%d] = %d\n", i, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N[i]);
- RTW_INFO("pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P[%d] = %d\n", i, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P[i]);
- RTW_INFO("pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N[%d] = %d\n", i, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N[i]);
- RTW_INFO("pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P[%d] = %d\n", i, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P[i]);
- RTW_INFO("pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N[%d] = %d\n", i, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N[i]);
+ RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2ga_p[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2ga_p[i]);
+ RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2ga_n[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2ga_n[i]);
+ RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2gb_p[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2gb_p[i]);
+ RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2gb_n[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2gb_n[i]);
+ RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_p[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_p[i]);
+ RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_n[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_n[i]);
+ RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_p[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_p[i]);
+ RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_n[%d] = %d\n", i, pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_n[i]);
for (j = 0; j < 3; ++j) {
- RTW_INFO("pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[%d][%d] = %d\n", j, i, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[j][i]);
- RTW_INFO("pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[%d][%d] = %d\n", j, i, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[j][i]);
- RTW_INFO("pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[%d][%d] = %d\n", j, i, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[j][i]);
- RTW_INFO("pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[%d][%d] = %d\n", j, i, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[j][i]);
+ RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_5ga_p[%d][%d] = %d\n", j, i, pRFCalibrateInfo->delta_swing_table_idx_5ga_p[j][i]);
+ RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_5ga_n[%d][%d] = %d\n", j, i, pRFCalibrateInfo->delta_swing_table_idx_5ga_n[j][i]);
+ RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_5gb_p[%d][%d] = %d\n", j, i, pRFCalibrateInfo->delta_swing_table_idx_5gb_p[j][i]);
+ RTW_INFO("pRFCalibrateInfo->delta_swing_table_idx_5gb_n[%d][%d] = %d\n", j, i, pRFCalibrateInfo->delta_swing_table_idx_5gb_n[j][i]);
}
}
#endif
return rtStatus;
}
-int
+#ifdef CONFIG_TXPWR_LIMIT
+
+#ifndef DBG_TXPWR_LMT_FILE_PARSE
+#define DBG_TXPWR_LMT_FILE_PARSE 0
+#endif
+
+#define PARSE_RET_NO_HDL 0
+#define PARSE_RET_SUCCESS 1
+#define PARSE_RET_FAIL 2
+
+/*
+* @@Ver=2.0
+* or
+* @@DomainCode=0x28, Regulation=C6
+* or
+* @@CountryCode=GB, Regulation=C7
+*/
+static u8 parse_reg_exc_config(_adapter *adapter, char *szLine)
+{
+#define VER_PREFIX "Ver="
+#define DOMAIN_PREFIX "DomainCode=0x"
+#define COUNTRY_PREFIX "CountryCode="
+#define REG_PREFIX "Regulation="
+
+ const u8 ver_prefix_len = strlen(VER_PREFIX);
+ const u8 domain_prefix_len = strlen(DOMAIN_PREFIX);
+ const u8 country_prefix_len = strlen(COUNTRY_PREFIX);
+ const u8 reg_prefix_len = strlen(REG_PREFIX);
+ u32 i, i_val_s, i_val_e;
+ u32 j;
+ u8 domain = 0xFF;
+ char *country = NULL;
+ u8 parse_reg = 0;
+
+ if (szLine[0] != '@' || szLine[1] != '@')
+ return PARSE_RET_NO_HDL;
+
+ i = 2;
+ if (strncmp(szLine + i, VER_PREFIX, ver_prefix_len) == 0)
+ ; /* nothing to do */
+ else if (strncmp(szLine + i, DOMAIN_PREFIX, domain_prefix_len) == 0) {
+ /* get string after domain prefix to ',' */
+ i += domain_prefix_len;
+ i_val_s = i;
+ while (szLine[i] != ',') {
+ if (szLine[i] == '\0')
+ return PARSE_RET_FAIL;
+ i++;
+ }
+ i_val_e = i;
+
+ /* check if all hex */
+ for (j = i_val_s; j < i_val_e; j++)
+ if (IsHexDigit(szLine[j]) == _FALSE)
+ return PARSE_RET_FAIL;
+
+ /* get value from hex string */
+ if (sscanf(szLine + i_val_s, "%hhx", &domain) != 1)
+ return PARSE_RET_FAIL;
+
+ parse_reg = 1;
+ } else if (strncmp(szLine + i, COUNTRY_PREFIX, country_prefix_len) == 0) {
+ /* get string after country prefix to ',' */
+ i += country_prefix_len;
+ i_val_s = i;
+ while (szLine[i] != ',') {
+ if (szLine[i] == '\0')
+ return PARSE_RET_FAIL;
+ i++;
+ }
+ i_val_e = i;
+
+ if (i_val_e - i_val_s != 2)
+ return PARSE_RET_FAIL;
+
+ /* check if all alpha */
+ for (j = i_val_s; j < i_val_e; j++)
+ if (is_alpha(szLine[j]) == _FALSE)
+ return PARSE_RET_FAIL;
+
+ country = szLine + i_val_s;
+
+ parse_reg = 1;
+
+ } else
+ return PARSE_RET_FAIL;
+
+ if (parse_reg) {
+ /* move to 'R' */
+ while (szLine[i] != 'R') {
+ if (szLine[i] == '\0')
+ return PARSE_RET_FAIL;
+ i++;
+ }
+
+ /* check if matching regulation prefix */
+ if (strncmp(szLine + i, REG_PREFIX, reg_prefix_len) != 0)
+ return PARSE_RET_FAIL;
+
+ /* get string after regulation prefix ending with space */
+ i += reg_prefix_len;
+ i_val_s = i;
+ while (szLine[i] != ' ' && szLine[i] != '\t' && szLine[i] != '\0')
+ i++;
+
+ if (i == i_val_s)
+ return PARSE_RET_FAIL;
+
+ rtw_regd_exc_add_with_nlen(adapter_to_rfctl(adapter), country, domain, szLine + i_val_s, i - i_val_s);
+ }
+
+ return PARSE_RET_SUCCESS;
+}
+
+static int
phy_ParsePowerLimitTableFile(
- PADAPTER Adapter,
- char *buffer
-) {
+ PADAPTER Adapter,
+ char *buffer
+)
+{
+#define LD_STAGE_EXC_MAPPING 0
+#define LD_STAGE_TAB_DEFINE 1
+#define LD_STAGE_TAB_START 2
+#define LD_STAGE_COLUMN_DEFINE 3
+#define LD_STAGE_CH_ROW 4
+
+ int rtStatus = _FAIL;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
- PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
+ struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
+ u8 loadingStage = LD_STAGE_EXC_MAPPING;
u32 i = 0, forCnt = 0;
- u8 loadingStage = 0, limitValue = 0, fraction = 0;
+ u8 limitValue = 0, fraction = 0, negative = 0;
char *szLine, *ptmp;
- int rtStatus = _SUCCESS;
- char band[10], bandwidth[10], rateSection[10],
- regulation[TXPWR_LMT_MAX_REGULATION_NUM][10], rfPath[10], colNumBuf[10];
+ char band[10], bandwidth[10], rateSection[10], ntx[10], colNumBuf[10];
+ char **regulation = NULL;
u8 colNum = 0;
- RTW_INFO("===>phy_ParsePowerLimitTableFile()\n");
+ RTW_INFO("%s enter\n", __func__);
if (Adapter->registrypriv.RegDecryptCustomFile == 1)
phy_DecryptBBPgParaFile(Adapter, buffer);
@@ -4307,20 +5089,25 @@ phy_ParsePowerLimitTableFile(
for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) {
if (isAllSpaceOrTab(szLine, sizeof(*szLine)))
continue;
-
- /* skip comment */
if (IsCommentString(szLine))
continue;
- if (loadingStage == 0) {
- for (forCnt = 0; forCnt < TXPWR_LMT_MAX_REGULATION_NUM; ++forCnt)
- _rtw_memset((PVOID) regulation[forCnt], 0, 10);
- _rtw_memset((PVOID) band, 0, 10);
- _rtw_memset((PVOID) bandwidth, 0, 10);
- _rtw_memset((PVOID) rateSection, 0, 10);
- _rtw_memset((PVOID) rfPath, 0, 10);
- _rtw_memset((PVOID) colNumBuf, 0, 10);
+ if (loadingStage == LD_STAGE_EXC_MAPPING) {
+ if (szLine[0] == '#' || szLine[1] == '#') {
+ loadingStage = LD_STAGE_TAB_DEFINE;
+ if (DBG_TXPWR_LMT_FILE_PARSE)
+ dump_regd_exc_list(RTW_DBGDUMP, adapter_to_rfctl(Adapter));
+ } else {
+ if (parse_reg_exc_config(Adapter, szLine) == PARSE_RET_FAIL) {
+ RTW_ERR("Fail to parse regulation exception ruls!\n");
+ goto exit;
+ }
+ continue;
+ }
+ }
+ if (loadingStage == LD_STAGE_TAB_DEFINE) {
+ /* read "## 2.4G, 20M, 1T, CCK" */
if (szLine[0] != '#' || szLine[1] != '#')
continue;
@@ -4332,25 +5119,30 @@ phy_ParsePowerLimitTableFile(
szLine[--i] = ' '; /* return the space in front of the regulation info */
/* Parse the label of the table */
+ _rtw_memset((PVOID) band, 0, 10);
+ _rtw_memset((PVOID) bandwidth, 0, 10);
+ _rtw_memset((PVOID) ntx, 0, 10);
+ _rtw_memset((PVOID) rateSection, 0, 10);
if (!ParseQualifiedString(szLine, &i, band, ' ', ',')) {
- RTW_INFO("Fail to parse band!\n");
- return _FAIL;
+ RTW_ERR("Fail to parse band!\n");
+ goto exit;
}
if (!ParseQualifiedString(szLine, &i, bandwidth, ' ', ',')) {
- RTW_INFO("Fail to parse bandwidth!\n");
- return _FAIL;
+ RTW_ERR("Fail to parse bandwidth!\n");
+ goto exit;
}
- if (!ParseQualifiedString(szLine, &i, rfPath, ' ', ',')) {
- RTW_INFO("Fail to parse rf path!\n");
- return _FAIL;
+ if (!ParseQualifiedString(szLine, &i, ntx, ' ', ',')) {
+ RTW_ERR("Fail to parse ntx!\n");
+ goto exit;
}
if (!ParseQualifiedString(szLine, &i, rateSection, ' ', ',')) {
- RTW_INFO("Fail to parse rate!\n");
- return _FAIL;
+ RTW_ERR("Fail to parse rate!\n");
+ goto exit;
}
- loadingStage = 1;
- } else if (loadingStage == 1) {
+ loadingStage = LD_STAGE_TAB_START;
+ } else if (loadingStage == LD_STAGE_TAB_START) {
+ /* read "## START" */
if (szLine[0] != '#' || szLine[1] != '#')
continue;
@@ -4360,12 +5152,13 @@ phy_ParsePowerLimitTableFile(
++i;
if (!eqNByte((u8 *)(szLine + i), (u8 *)("START"), 5)) {
- RTW_INFO("Lost \"## START\" label\n");
- return _FAIL;
+ RTW_ERR("Missing \"## START\" label\n");
+ goto exit;
}
- loadingStage = 2;
- } else if (loadingStage == 2) {
+ loadingStage = LD_STAGE_COLUMN_DEFINE;
+ } else if (loadingStage == LD_STAGE_COLUMN_DEFINE) {
+ /* read "## #5# FCC ETSI MKK IC KCC" */
if (szLine[0] != '#' || szLine[1] != '#')
continue;
@@ -4374,39 +5167,59 @@ phy_ParsePowerLimitTableFile(
while (szLine[i] == ' ' || szLine[i] == '\t')
++i;
+ _rtw_memset((PVOID) colNumBuf, 0, 10);
if (!ParseQualifiedString(szLine, &i, colNumBuf, '#', '#')) {
- RTW_INFO("Fail to parse column number!\n");
- return _FAIL;
+ RTW_ERR("Fail to parse column number!\n");
+ goto exit;
+ }
+ if (!GetU1ByteIntegerFromStringInDecimal(colNumBuf, &colNum)) {
+ RTW_ERR("Column number \"%s\" is not unsigned decimal\n", colNumBuf);
+ goto exit;
+ }
+ if (colNum == 0) {
+ RTW_ERR("Column number is 0\n");
+ goto exit;
}
- if (!GetU1ByteIntegerFromStringInDecimal(colNumBuf, &colNum))
- return _FAIL;
+ if (DBG_TXPWR_LMT_FILE_PARSE)
+ RTW_PRINT("[%s][%s][%s][%s] column num:%d\n", band, bandwidth, rateSection, ntx, colNum);
- if (colNum > TXPWR_LMT_MAX_REGULATION_NUM) {
- RTW_INFO("unvalid col number %d (greater than max %d)\n",
- colNum, TXPWR_LMT_MAX_REGULATION_NUM);
- return _FAIL;
+ regulation = (char **)rtw_zmalloc(sizeof(char *) * colNum);
+ if (!regulation) {
+ RTW_ERR("Regulation alloc fail\n");
+ goto exit;
}
for (forCnt = 0; forCnt < colNum; ++forCnt) {
- u8 regulation_name_cnt = 0;
+ u32 i_ns;
/* skip the space */
while (szLine[i] == ' ' || szLine[i] == '\t')
- ++i;
+ i++;
+ i_ns = i;
while (szLine[i] != ' ' && szLine[i] != '\t' && szLine[i] != '\0')
- regulation[forCnt][regulation_name_cnt++] = szLine[i++];
- /* RTW_INFO("regulation %s!\n", regulation[forCnt]); */
+ i++;
- if (regulation_name_cnt == 0) {
- RTW_INFO("unvalid number of regulation!\n");
- return _FAIL;
+ regulation[forCnt] = (char *)rtw_malloc(i - i_ns + 1);
+ if (!regulation[forCnt]) {
+ RTW_ERR("Regulation alloc fail\n");
+ goto exit;
}
+
+ _rtw_memcpy(regulation[forCnt], szLine + i_ns, i - i_ns);
+ regulation[forCnt][i - i_ns] = '\0';
+ }
+
+ if (DBG_TXPWR_LMT_FILE_PARSE) {
+ RTW_PRINT("column name:");
+ for (forCnt = 0; forCnt < colNum; ++forCnt)
+ _RTW_PRINT(" %s", regulation[forCnt]);
+ _RTW_PRINT("\n");
}
- loadingStage = 3;
- } else if (loadingStage == 3) {
+ loadingStage = LD_STAGE_CH_ROW;
+ } else if (loadingStage == LD_STAGE_CH_ROW) {
char channel[10] = {0}, powerLimit[10] = {0};
u8 cnt = 0;
@@ -4417,18 +5230,29 @@ phy_ParsePowerLimitTableFile(
++i;
if (eqNByte((u8 *)(szLine + i), (u8 *)("END"), 3)) {
- loadingStage = 0;
+ loadingStage = LD_STAGE_TAB_DEFINE;
+ if (regulation) {
+ for (forCnt = 0; forCnt < colNum; ++forCnt) {
+ if (regulation[forCnt]) {
+ rtw_mfree(regulation[forCnt], strlen(regulation[forCnt]) + 1);
+ regulation[forCnt] = NULL;
+ }
+ }
+ rtw_mfree((u8 *)regulation, sizeof(char *) * colNum);
+ regulation = NULL;
+ }
+ colNum = 0;
continue;
} else {
- RTW_INFO("Wrong format\n");
- RTW_INFO("<===== phy_ParsePowerLimitTableFile()\n");
- return _FAIL;
+ RTW_ERR("Missing \"## END\" label\n");
+ goto exit;
}
}
if ((szLine[0] != 'c' && szLine[0] != 'C') ||
- (szLine[1] != 'h' && szLine[1] != 'H')) {
- RTW_INFO("Meet wrong channel => power limt pair '%c','%c'(%d,%d)\n", szLine[0], szLine[1], szLine[0], szLine[1]);
+ (szLine[1] != 'h' && szLine[1] != 'H')
+ ) {
+ RTW_WARN("Wrong channel prefix: '%c','%c'(%d,%d)\n", szLine[0], szLine[1], szLine[0], szLine[1]);
continue;
}
i = 2;/* move to the location behind 'h' */
@@ -4450,15 +5274,31 @@ phy_ParsePowerLimitTableFile(
/* load the power limit value */
cnt = 0;
fraction = 0;
+ negative = 0;
_rtw_memset((PVOID) powerLimit, 0, 10);
- while ((szLine[i] >= '0' && szLine[i] <= '9') || szLine[i] == '.') {
- if (szLine[i] == '.') {
+
+ while ((szLine[i] >= '0' && szLine[i] <= '9') || szLine[i] == '.'
+ || szLine[i] == '+' || szLine[i] == '-'
+ ) {
+ /* try to get valid decimal number */
+ if (szLine[i] == '+' || szLine[i] == '-') {
+ if (cnt != 0) {
+ RTW_ERR("Wrong position for sign '%c'\n", szLine[i]);
+ goto exit;
+ }
+ if (szLine[i] == '-') {
+ negative = 1;
+ ++i;
+ continue;
+ }
+
+ } else if (szLine[i] == '.') {
if ((szLine[i + 1] >= '0' && szLine[i + 1] <= '9')) {
fraction = szLine[i + 1];
i += 2;
} else {
- RTW_INFO("Wrong fraction in TXPWR_LMT.txt\n");
- return _FAIL;
+ RTW_ERR("Wrong fraction '%c'(%d)\n", szLine[i + 1], szLine[i + 1]);
+ goto exit;
}
break;
@@ -4470,15 +5310,41 @@ phy_ParsePowerLimitTableFile(
}
if (powerLimit[0] == '\0') {
- powerLimit[0] = '6';
- powerLimit[1] = '3';
- i += 2;
+ if (szLine[i] == 'W' && szLine[i + 1] == 'W') {
+ /*
+ * case "WW" assign special value -63
+ * means to get minimal limit in other regulations at same channel
+ */
+ powerLimit[0] = '-';
+ powerLimit[1] = '6';
+ powerLimit[2] = '3';
+ i += 2;
+ } else if (szLine[i] == 'N' && szLine[i + 1] == 'A') {
+ /*
+ * case "NA" assign special value 63
+ * means no limitation
+ */
+ powerLimit[0] = '6';
+ powerLimit[1] = '3';
+ i += 2;
+ } else {
+ RTW_ERR("Wrong limit expression \"%c%c\"(%d, %d)\n"
+ , szLine[i], szLine[i + 1], szLine[i], szLine[i + 1]);
+ goto exit;
+ }
} else {
- if (!GetU1ByteIntegerFromStringInDecimal(powerLimit, &limitValue))
- return _FAIL;
+ /* transform dicimal value to power index */
+ if (!GetU1ByteIntegerFromStringInDecimal(powerLimit, &limitValue)) {
+ RTW_ERR("Limit \"%s\" is not valid decimal\n", powerLimit);
+ goto exit;
+ }
limitValue *= 2;
cnt = 0;
+
+ if (negative)
+ powerLimit[cnt++] = '-';
+
if (fraction == '5')
++limitValue;
@@ -4511,26 +5377,37 @@ phy_ParsePowerLimitTableFile(
/* RTW_INFO("ch%s => %s\n", channel, powerLimit); */
/* store the power limit value */
- PHY_SetTxPowerLimit(pDM_Odm, (u8 *)regulation[forCnt], (u8 *)band,
- (u8 *)bandwidth, (u8 *)rateSection, (u8 *)rfPath, (u8 *)channel, (u8 *)powerLimit);
+ phy_set_tx_power_limit(pDM_Odm, (u8 *)regulation[forCnt], (u8 *)band,
+ (u8 *)bandwidth, (u8 *)rateSection, (u8 *)ntx, (u8 *)channel, (u8 *)powerLimit);
}
- } else {
- RTW_INFO("Abnormal loading stage in phy_ParsePowerLimitTableFile()!\n");
- rtStatus = _FAIL;
- break;
}
}
- RTW_INFO("<===phy_ParsePowerLimitTableFile()\n");
+ rtStatus = _SUCCESS;
+
+exit:
+ if (regulation) {
+ for (forCnt = 0; forCnt < colNum; ++forCnt) {
+ if (regulation[forCnt]) {
+ rtw_mfree(regulation[forCnt], strlen(regulation[forCnt]) + 1);
+ regulation[forCnt] = NULL;
+ }
+ }
+ rtw_mfree((u8 *)regulation, sizeof(char *) * colNum);
+ regulation = NULL;
+ }
+
+ RTW_INFO("%s return %d\n", __func__, rtStatus);
return rtStatus;
}
int
PHY_ConfigRFWithPowerLimitTableParaFile(
- IN PADAPTER Adapter,
- IN const char *pFileName
-) {
+ IN PADAPTER Adapter,
+ IN const char *pFileName
+)
+{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
int rlen = 0, rtStatus = _FAIL;
@@ -4540,8 +5417,7 @@ PHY_ConfigRFWithPowerLimitTableParaFile(
_rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN);
if (pHalData->rf_tx_pwr_lmt == NULL) {
- rtw_merge_string(rtw_phy_para_file_path, PATH_LENGTH_MAX, rtw_phy_file_path, pFileName);
-
+ rtw_get_phy_file_path(Adapter, pFileName);
if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) {
rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN);
if (rlen > 0) {
@@ -4570,8 +5446,10 @@ PHY_ConfigRFWithPowerLimitTableParaFile(
return rtStatus;
}
+#endif /* CONFIG_TXPWR_LIMIT */
-void phy_free_filebuf_mask(_adapter *padapter, u8 mask) {
+void phy_free_filebuf_mask(_adapter *padapter, u8 mask)
+{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
if (pHalData->mac_reg && (mask & LOAD_MAC_PARA_FILE)) {
@@ -4616,7 +5494,8 @@ void phy_free_filebuf_mask(_adapter *padapter, u8 mask) {
}
}
-inline void phy_free_filebuf(_adapter *padapter) {
+inline void phy_free_filebuf(_adapter *padapter)
+{
phy_free_filebuf_mask(padapter, 0xFF);
}
diff --git a/hal/hal_dm.c b/hal/hal_dm.c
index 851d529..9102ca5 100644
--- a/hal/hal_dm.c
+++ b/hal/hal_dm.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2014 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2014 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,20 +11,15 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#include
#include
/* A mapping from HalData to ODM. */
-ODM_BOARD_TYPE_E boardType(u8 InterfaceSel)
+enum odm_board_type boardType(u8 InterfaceSel)
{
- ODM_BOARD_TYPE_E board = ODM_BOARD_DEFAULT;
+ enum odm_board_type board = ODM_BOARD_DEFAULT;
#ifdef CONFIG_PCI_HCI
INTERFACE_SELECT_PCIE pcie = (INTERFACE_SELECT_PCIE)InterfaceSel;
@@ -70,57 +65,159 @@ ODM_BOARD_TYPE_E boardType(u8 InterfaceSel)
return board;
}
+void rtw_hal_update_iqk_fw_offload_cap(_adapter *adapter)
+{
+ PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
+ struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
+
+ if (hal->RegIQKFWOffload) {
+ rtw_sctx_init(&hal->iqk_sctx, 0);
+ phydm_fwoffload_ability_init(p_dm_odm, PHYDM_RF_IQK_OFFLOAD);
+ } else
+ phydm_fwoffload_ability_clear(p_dm_odm, PHYDM_RF_IQK_OFFLOAD);
+
+ RTW_INFO("IQK FW offload:%s\n", hal->RegIQKFWOffload ? "enable" : "disable");
+}
+
+#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1))
+void rtw_phydm_iqk_trigger(_adapter *adapter)
+{
+ struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
+ u8 clear = _TRUE;
+ u8 segment = _FALSE;
+ u8 rfk_forbidden = _FALSE;
+
+ /*segment = _rtw_phydm_iqk_segment_chk(adapter);*/
+ halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
+ halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_IQK_SEGMENT, segment);
+ halrf_segment_iqk_trigger(p_dm_odm, clear, segment);
+}
+#endif
+
+void rtw_phydm_iqk_trigger_dbg(_adapter *adapter, bool recovery, bool clear, bool segment)
+{
+ struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
+
+#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1))
+ halrf_segment_iqk_trigger(p_dm_odm, clear, segment);
+#else
+ halrf_iqk_trigger(p_dm_odm, recovery);
+#endif
+}
+void rtw_phydm_lck_trigger(_adapter *adapter)
+{
+ struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
+
+ halrf_lck_trigger(p_dm_odm);
+}
+#ifdef CONFIG_DBG_RF_CAL
+void rtw_hal_iqk_test(_adapter *adapter, bool recovery, bool clear, bool segment)
+{
+ struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
+
+ rtw_ps_deny(adapter, PS_DENY_IOCTL);
+ LeaveAllPowerSaveModeDirect(adapter);
+
+ rtw_phydm_ability_backup(adapter);
+ rtw_phydm_func_disable_all(adapter);
+
+ halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_ABILITY, HAL_RF_IQK);
+
+ rtw_phydm_iqk_trigger_dbg(adapter, recovery, clear, segment);
+ rtw_phydm_ability_restore(adapter);
+
+ rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
+}
+
+void rtw_hal_lck_test(_adapter *adapter)
+{
+ struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
+
+ rtw_ps_deny(adapter, PS_DENY_IOCTL);
+ LeaveAllPowerSaveModeDirect(adapter);
+
+ rtw_phydm_ability_backup(adapter);
+ rtw_phydm_func_disable_all(adapter);
+
+ halrf_cmn_info_set(p_dm_odm, HALRF_CMNINFO_ABILITY, HAL_RF_LCK);
+
+ rtw_phydm_lck_trigger(adapter);
+
+ rtw_phydm_ability_restore(adapter);
+ rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL);
+}
+#endif
+
+#ifdef CONFIG_FW_OFFLOAD_PARAM_INIT
+void rtw_hal_update_param_init_fw_offload_cap(_adapter *adapter)
+{
+ struct dm_struct *p_dm_odm = adapter_to_phydm(adapter);
+
+ if (adapter->registrypriv.fw_param_init)
+ phydm_fwoffload_ability_init(p_dm_odm, PHYDM_PHY_PARAM_OFFLOAD);
+ else
+ phydm_fwoffload_ability_clear(p_dm_odm, PHYDM_PHY_PARAM_OFFLOAD);
+
+ RTW_INFO("Init-Parameter FW offload:%s\n", adapter->registrypriv.fw_param_init ? "enable" : "disable");
+}
+#endif
+
+void record_ra_info(void *p_dm_void, u8 macid, struct cmn_sta_info *p_sta, u64 ra_mask)
+{
+ struct dm_struct *p_dm = (struct dm_struct *)p_dm_void;
+ _adapter *adapter = p_dm->adapter;
+ struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+ struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
+
+ rtw_macid_ctl_set_bw(macid_ctl, macid, p_sta->ra_info.ra_bw_mode);
+ rtw_macid_ctl_set_vht_en(macid_ctl, macid, p_sta->ra_info.is_vht_enable);
+ rtw_macid_ctl_set_rate_bmp0(macid_ctl, macid, ra_mask);
+ rtw_macid_ctl_set_rate_bmp1(macid_ctl, macid, ra_mask >> 32);
+
+ rtw_update_tx_rate_bmp(adapter_to_dvobj(adapter));
+}
+
+void rtw_phydm_ops_func_init(struct dm_struct *p_phydm)
+{
+ struct ra_table *p_ra_t = &p_phydm->dm_ra_table;
+
+ p_ra_t->record_ra_info = record_ra_info;
+}
+
void Init_ODM_ComInfo(_adapter *adapter)
{
struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
- PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
- struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
- struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
+ struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
int i;
_rtw_memset(pDM_Odm, 0, sizeof(*pDM_Odm));
- pDM_Odm->Adapter = adapter;
+ pDM_Odm->adapter = adapter;
- ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PLATFORM, ODM_CE);
+ /*phydm_op_mode could be change for different scenarios: ex: SoftAP - PHYDM_BALANCE_MODE*/
+ pHalData->phydm_op_mode = PHYDM_PERFORMANCE_MODE;/*Service one device*/
+
+ odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_PLATFORM, ODM_CE);
rtw_odm_init_ic_type(adapter);
if (rtw_get_intf_type(adapter) == RTW_GSPI)
- ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_INTERFACE, ODM_ITRF_SDIO);
- else
- ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_INTERFACE, rtw_get_intf_type(adapter));
-
- ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_MP_TEST_CHIP, IS_NORMAL_CHIP(pHalData->VersionID));
-
- ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PATCH_ID, pHalData->CustomerID);
-
- ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BWIFI_TEST, adapter->registrypriv.wifi_spec);
-
-
- if (pHalData->rf_type == RF_1T1R)
- ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_1T1R);
- else if (pHalData->rf_type == RF_1T2R)
- ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_1T2R);
- else if (pHalData->rf_type == RF_2T2R)
- ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_2T2R);
- else if (pHalData->rf_type == RF_2T2R_GREEN)
- ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_2T2R_GREEN);
- else if (pHalData->rf_type == RF_2T3R)
- ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_2T3R);
- else if (pHalData->rf_type == RF_2T4R)
- ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_2T4R);
- else if (pHalData->rf_type == RF_3T3R)
- ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_3T3R);
- else if (pHalData->rf_type == RF_3T4R)
- ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_3T4R);
- else if (pHalData->rf_type == RF_4T4R)
- ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_4T4R);
+ odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_INTERFACE, ODM_ITRF_SDIO);
else
- ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_XTXR);
+ odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_INTERFACE, rtw_get_intf_type(adapter));
+
+ odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_MP_TEST_CHIP, IS_NORMAL_CHIP(pHalData->version_id));
+ odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_PATCH_ID, pHalData->CustomerID);
+
+ odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BWIFI_TEST, adapter->registrypriv.wifi_spec);
+
+#ifdef CONFIG_ADVANCE_OTA
+ odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_ADVANCE_OTA, adapter->registrypriv.adv_ota);
+#endif
+ odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, pHalData->rf_type);
{
/* 1 ======= BoardType: ODM_CMNINFO_BOARD_TYPE ======= */
@@ -128,84 +225,1016 @@ void Init_ODM_ComInfo(_adapter *adapter)
if (pHalData->ExternalLNA_2G != 0) {
odm_board_type |= ODM_BOARD_EXT_LNA;
- ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, 1);
+ odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_LNA, 1);
}
- if (pHalData->ExternalLNA_5G != 0) {
+ if (pHalData->external_lna_5g != 0) {
odm_board_type |= ODM_BOARD_EXT_LNA_5G;
- ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, 1);
+ odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, 1);
}
if (pHalData->ExternalPA_2G != 0) {
odm_board_type |= ODM_BOARD_EXT_PA;
- ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, 1);
+ odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_PA, 1);
}
- if (pHalData->ExternalPA_5G != 0) {
+ if (pHalData->external_pa_5g != 0) {
odm_board_type |= ODM_BOARD_EXT_PA_5G;
- ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, 1);
+ odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, 1);
}
if (pHalData->EEPROMBluetoothCoexist)
odm_board_type |= ODM_BOARD_BT;
- ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, odm_board_type);
+ odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, odm_board_type);
/* 1 ============== End of BoardType ============== */
}
- ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_DOMAIN_CODE_2G, pHalData->Regulation2_4G);
- ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_DOMAIN_CODE_5G, pHalData->Regulation5G);
+ rtw_hal_set_odm_var(adapter, HAL_ODM_REGULATION, NULL, _TRUE);
#ifdef CONFIG_DFS_MASTER
- ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_DFS_REGION_DOMAIN, adapter->registrypriv.dfs_region_domain);
- ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_DFS_MASTER_ENABLE, &(adapter_to_rfctl(adapter)->dfs_master_enabled));
+ odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_DFS_REGION_DOMAIN, adapter->registrypriv.dfs_region_domain);
+ odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_DFS_MASTER_ENABLE, &(adapter_to_rfctl(adapter)->dfs_master_enabled));
#endif
- ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GPA, pHalData->TypeGPA);
- ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_APA, pHalData->TypeAPA);
- ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GLNA, pHalData->TypeGLNA);
- ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_ALNA, pHalData->TypeALNA);
+ odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_GPA, pHalData->TypeGPA);
+ odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_APA, pHalData->TypeAPA);
+ odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_GLNA, pHalData->TypeGLNA);
+ odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_ALNA, pHalData->TypeALNA);
- ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RFE_TYPE, pHalData->RFEType);
+ odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RFE_TYPE, pHalData->rfe_type);
- ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_TRSW, 0);
+ odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_TRSW, 0);
/*Add by YuChen for kfree init*/
- ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_REGRFKFREEENABLE, adapter->registrypriv.RegPwrTrimEnable);
- ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RFKFREEENABLE, pHalData->RfKFreeEnable);
- ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_ANTENNA_TYPE, pHalData->TRxAntDivType);
+ odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_REGRFKFREEENABLE, adapter->registrypriv.RegPwrTrimEnable);
+ odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RFKFREEENABLE, pHalData->RfKFreeEnable);
+
+ odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_ANTENNA_TYPE, pHalData->TRxAntDivType);
+ odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BE_FIX_TX_ANT, pHalData->b_fix_tx_ant);
+ odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH, pHalData->with_extenal_ant_switch);
+
+ /* (8822B) efuse 0x3D7 & 0x3D8 for TX PA bias */
+ odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EFUSE0X3D7, pHalData->efuse0x3d7);
+ odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EFUSE0X3D8, pHalData->efuse0x3d8);
/*Add by YuChen for adaptivity init*/
- phydm_adaptivityInfoInit(pDM_Odm, PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE, (adapter->registrypriv.adaptivity_mode != 0) ? TRUE : FALSE);
- phydm_adaptivityInfoInit(pDM_Odm, PHYDM_ADAPINFO_DCBACKOFF, adapter->registrypriv.adaptivity_dc_backoff);
- phydm_adaptivityInfoInit(pDM_Odm, PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY, (adapter->registrypriv.adaptivity_dml != 0) ? TRUE : FALSE);
- phydm_adaptivityInfoInit(pDM_Odm, PHYDM_ADAPINFO_TH_L2H_INI, adapter->registrypriv.adaptivity_th_l2h_ini);
- phydm_adaptivityInfoInit(pDM_Odm, PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF, adapter->registrypriv.adaptivity_th_edcca_hl_diff);
+ odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ADAPTIVITY, &(adapter->registrypriv.adaptivity_en));
+ phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE, (adapter->registrypriv.adaptivity_mode != 0) ? TRUE : FALSE);
+ phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_DCBACKOFF, adapter->registrypriv.adaptivity_dc_backoff);
+ phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY, (adapter->registrypriv.adaptivity_dml != 0) ? TRUE : FALSE);
+ phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_TH_L2H_INI, adapter->registrypriv.adaptivity_th_l2h_ini);
+ phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF, adapter->registrypriv.adaptivity_th_edcca_hl_diff);
+
+ /*halrf info init*/
+ halrf_cmn_info_init(pDM_Odm, HALRF_CMNINFO_EEPROM_THERMAL_VALUE, pHalData->eeprom_thermal_meter);
+
+ if (rtw_odm_adaptivity_needed(adapter) == _TRUE)
+ rtw_odm_adaptivity_config_msg(RTW_DBGDUMP, adapter);
+#ifdef CONFIG_IQK_PA_OFF
+ odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_IQKPAOFF, 1);
+#endif
+ rtw_hal_update_iqk_fw_offload_cap(adapter);
+ #ifdef CONFIG_FW_OFFLOAD_PARAM_INIT
+ rtw_hal_update_param_init_fw_offload_cap(adapter);
+ #endif
/* Pointer reference */
- ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_TX_UNI, &(dvobj->traffic_stat.tx_bytes));
- ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_RX_UNI, &(dvobj->traffic_stat.rx_bytes));
- ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_WM_MODE, &(pmlmeext->cur_wireless_mode));
- ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_BAND, &(pHalData->CurrentBandType));
- ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_FORCED_RATE, &(pHalData->ForcedDataRate));
- ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_FORCED_IGI_LB, &(pHalData->u1ForcedIgiLb));
-
- ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_SEC_CHNL_OFFSET, &(pHalData->nCur40MhzPrimeSC));
- ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_SEC_MODE, &(adapter->securitypriv.dot11PrivacyAlgrthm));
- ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_BW, &(pHalData->CurrentChannelBW));
- ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_CHNL, &(pHalData->CurrentChannel));
- ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_NET_CLOSED, &(adapter->net_closed));
- ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_FORCED_IGI_LB, &(pHalData->u1ForcedIgiLb));
-
- ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_SCAN, &(pmlmepriv->bScanInProcess));
- ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_POWER_SAVING, &(pwrctl->bpower_saving));
+ /*Antenna diversity relative parameters*/
+ odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ANT_DIV, &(pHalData->AntDivCfg));
+ odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_MP_MODE, &(adapter->registrypriv.mp_mode));
+
+ odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BB_OPERATION_MODE, &(pHalData->phydm_op_mode));
+ odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_TX_UNI, &(dvobj->traffic_stat.tx_bytes));
+ odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RX_UNI, &(dvobj->traffic_stat.rx_bytes));
+
+ odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BAND, &(pHalData->current_band_type));
+ odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_FORCED_RATE, &(pHalData->ForcedDataRate));
+
+ odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SEC_CHNL_OFFSET, &(pHalData->nCur40MhzPrimeSC));
+ odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SEC_MODE, &(adapter->securitypriv.dot11PrivacyAlgrthm));
+ odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BW, &(pHalData->current_channel_bw));
+ odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_CHNL, &(pHalData->current_channel));
+ odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_NET_CLOSED, &(adapter->net_closed));
+
+ odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SCAN, &(pHalData->bScanInProcess));
+ odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_POWER_SAVING, &(pwrctl->bpower_saving));
/*Add by Yuchen for phydm beamforming*/
- ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_TX_TP, &(dvobj->traffic_stat.cur_tx_tp));
- ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_RX_TP, &(dvobj->traffic_stat.cur_rx_tp));
+ odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_TX_TP, &(dvobj->traffic_stat.cur_tx_tp));
+ odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RX_TP, &(dvobj->traffic_stat.cur_rx_tp));
+ odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ANT_TEST, &(pHalData->antenna_test));
+#ifdef CONFIG_RTL8723B
+ odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_IS1ANTENNA, &pHalData->EEPROMBluetoothAntNum);
+ odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RFDEFAULTPATH, &pHalData->ant_path);
+#endif /*CONFIG_RTL8723B*/
#ifdef CONFIG_USB_HCI
- ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_HUBUSBMODE, &(dvobj->usb_speed));
+ odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_HUBUSBMODE, &(dvobj->usb_speed));
#endif
+
+#ifdef CONFIG_DYNAMIC_SOML
+ odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ADAPTIVE_SOML, &(adapter->registrypriv.dyn_soml_en));
+#endif
+
+ /*halrf info hook*/
+#ifdef CONFIG_MP_INCLUDED
+ halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_CON_TX, &(adapter->mppriv.mpt_ctx.is_start_cont_tx));
+ halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_SINGLE_TONE, &(adapter->mppriv.mpt_ctx.is_single_tone));
+ halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_CARRIER_SUPPRESSION, &(adapter->mppriv.mpt_ctx.is_carrier_suppression));
+ halrf_cmn_info_hook(pDM_Odm, HALRF_CMNINFO_MP_RATE_INDEX, &(adapter->mppriv.mpt_ctx.mpt_rate_index));
+#endif/*CONFIG_MP_INCLUDED*/
for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
- ODM_CmnInfoPtrArrayHook(pDM_Odm, ODM_CMNINFO_STA_STATUS, i, NULL);
+ odm_cmn_info_ptr_array_hook(pDM_Odm, ODM_CMNINFO_STA_STATUS, i, NULL);
+ phydm_init_debug_setting(pDM_Odm);
+ rtw_phydm_ops_func_init(pDM_Odm);
/* TODO */
- /* ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_BT_OPERATION, _FALSE); */
- /* ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_BT_DISABLE_EDCA, _FALSE); */
+ /* odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BT_OPERATION, _FALSE); */
+ /* odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BT_DISABLE_EDCA, _FALSE); */
}
+
+
+static u32 edca_setting_UL[HT_IOT_PEER_MAX] =
+/*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM,*/
+/*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP(DownLink/Tx) */
+{ 0x5e4322, 0xa44f, 0x5e4322, 0x5ea32b, 0x5ea422, 0x5ea322, 0x3ea430, 0x5ea42b, 0x5ea44f, 0x5e4322, 0x5e4322};
+
+static u32 edca_setting_DL[HT_IOT_PEER_MAX] =
+/*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM,*/
+/*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP(UpLink/Rx)*/
+{ 0xa44f, 0x5ea44f, 0x5e4322, 0x5ea42b, 0xa44f, 0xa630, 0x5ea630, 0x5ea42b, 0xa44f, 0xa42b, 0xa42b};
+
+static u32 edca_setting_dl_g_mode[HT_IOT_PEER_MAX] =
+/*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM,*/
+/*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP */
+{ 0x4322, 0xa44f, 0x5e4322, 0xa42b, 0x5e4322, 0x4322, 0xa42b, 0x5ea42b, 0xa44f, 0x5e4322, 0x5ea42b};
+
+void rtw_hal_turbo_edca(_adapter *adapter)
+{
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+ struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+ struct recv_priv *precvpriv = &(adapter->recvpriv);
+ struct registry_priv *pregpriv = &adapter->registrypriv;
+ struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv);
+ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+
+ /* Parameter suggested by Scott */
+#if 0
+ u32 EDCA_BE_UL = edca_setting_UL[p_mgnt_info->iot_peer];
+ u32 EDCA_BE_DL = edca_setting_DL[p_mgnt_info->iot_peer];
+#endif
+ u32 EDCA_BE_UL = 0x5ea42b;
+ u32 EDCA_BE_DL = 0x00a42b;
+ u8 ic_type = rtw_get_chip_type(adapter);
+
+ u8 iot_peer = 0;
+ u8 wireless_mode = 0xFF; /* invalid value */
+ u8 traffic_index;
+ u32 edca_param;
+ u64 cur_tx_bytes = 0;
+ u64 cur_rx_bytes = 0;
+ u8 bbtchange = _TRUE;
+ u8 is_bias_on_rx = _FALSE;
+ u8 is_linked = _FALSE;
+ u8 interface_type;
+
+ if (hal_data->dis_turboedca)
+ return;
+
+ if (rtw_mi_check_status(adapter, MI_ASSOC))
+ is_linked = _TRUE;
+
+ if (is_linked != _TRUE) {
+ precvpriv->is_any_non_be_pkts = _FALSE;
+ return;
+ }
+
+ if ((pregpriv->wifi_spec == 1)) { /* || (pmlmeinfo->HT_enable == 0)) */
+ precvpriv->is_any_non_be_pkts = _FALSE;
+ return;
+ }
+
+ interface_type = rtw_get_intf_type(adapter);
+ wireless_mode = pmlmeext->cur_wireless_mode;
+
+ iot_peer = pmlmeinfo->assoc_AP_vendor;
+
+ if (iot_peer >= HT_IOT_PEER_MAX) {
+ precvpriv->is_any_non_be_pkts = _FALSE;
+ return;
+ }
+
+ if (ic_type == RTL8188E) {
+ if ((iot_peer == HT_IOT_PEER_RALINK) || (iot_peer == HT_IOT_PEER_ATHEROS))
+ is_bias_on_rx = _TRUE;
+ }
+
+ /* Check if the status needs to be changed. */
+ if ((bbtchange) || (!precvpriv->is_any_non_be_pkts)) {
+ cur_tx_bytes = dvobj->traffic_stat.cur_tx_bytes;
+ cur_rx_bytes = dvobj->traffic_stat.cur_rx_bytes;
+
+ /* traffic, TX or RX */
+ if (is_bias_on_rx) {
+ if (cur_tx_bytes > (cur_rx_bytes << 2)) {
+ /* Uplink TP is present. */
+ traffic_index = UP_LINK;
+ } else {
+ /* Balance TP is present. */
+ traffic_index = DOWN_LINK;
+ }
+ } else {
+ if (cur_rx_bytes > (cur_tx_bytes << 2)) {
+ /* Downlink TP is present. */
+ traffic_index = DOWN_LINK;
+ } else {
+ /* Balance TP is present. */
+ traffic_index = UP_LINK;
+ }
+ }
+#if 0
+ if ((p_dm_odm->dm_edca_table.prv_traffic_idx != traffic_index)
+ || (!p_dm_odm->dm_edca_table.is_current_turbo_edca))
+#endif
+ {
+ if (interface_type == RTW_PCIE) {
+ EDCA_BE_UL = 0x6ea42b;
+ EDCA_BE_DL = 0x6ea42b;
+ }
+
+ /* 92D txop can't be set to 0x3e for cisco1250 */
+ if ((iot_peer == HT_IOT_PEER_CISCO) && (wireless_mode == ODM_WM_N24G)) {
+ EDCA_BE_DL = edca_setting_DL[iot_peer];
+ EDCA_BE_UL = edca_setting_UL[iot_peer];
+ }
+ /* merge from 92s_92c_merge temp*/
+ else if ((iot_peer == HT_IOT_PEER_CISCO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == (ODM_WM_B | ODM_WM_G)) || (wireless_mode == ODM_WM_A) || (wireless_mode == ODM_WM_B)))
+ EDCA_BE_DL = edca_setting_dl_g_mode[iot_peer];
+ else if ((iot_peer == HT_IOT_PEER_AIRGO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == ODM_WM_A)))
+ EDCA_BE_DL = 0xa630;
+ else if (iot_peer == HT_IOT_PEER_MARVELL) {
+ EDCA_BE_DL = edca_setting_DL[iot_peer];
+ EDCA_BE_UL = edca_setting_UL[iot_peer];
+ } else if (iot_peer == HT_IOT_PEER_ATHEROS) {
+ /* Set DL EDCA for Atheros peer to 0x3ea42b.*/
+ /* Suggested by SD3 Wilson for ASUS TP issue.*/
+ EDCA_BE_DL = edca_setting_DL[iot_peer];
+ }
+
+ if ((ic_type == RTL8812) || (ic_type == RTL8821) || (ic_type == RTL8192E)) { /* add 8812AU/8812AE */
+ EDCA_BE_UL = 0x5ea42b;
+ EDCA_BE_DL = 0x5ea42b;
+
+ RTW_DBG("8812A: EDCA_BE_UL=0x%x EDCA_BE_DL =0x%x\n", EDCA_BE_UL, EDCA_BE_DL);
+ }
+
+ if (interface_type == RTW_PCIE &&
+ ((ic_type == RTL8822B)
+ || (ic_type == RTL8814A))) {
+ EDCA_BE_UL = 0x6ea42b;
+ EDCA_BE_DL = 0x6ea42b;
+ }
+
+ if (traffic_index == DOWN_LINK)
+ edca_param = EDCA_BE_DL;
+ else
+ edca_param = EDCA_BE_UL;
+#ifdef CONFIG_RTW_CUSTOMIZE_BEEDCA
+ edca_param = CONFIG_RTW_CUSTOMIZE_BEEDCA;
+#endif
+ rtw_hal_set_hwreg(adapter, HW_VAR_AC_PARAM_BE, (u8 *)(&edca_param));
+
+ RTW_DBG("Turbo EDCA =0x%x\n", edca_param);
+
+ hal_data->prv_traffic_idx = traffic_index;
+ }
+
+ hal_data->is_turbo_edca = _TRUE;
+ } else {
+ /* */
+ /* Turn Off EDCA turbo here. */
+ /* Restore original EDCA according to the declaration of AP. */
+ /* */
+ if (hal_data->is_turbo_edca) {
+ edca_param = hal_data->ac_param_be;
+ rtw_hal_set_hwreg(adapter, HW_VAR_AC_PARAM_BE, (u8 *)(&edca_param));
+ hal_data->is_turbo_edca = _FALSE;
+ }
+ }
+
+}
+
+s8 rtw_phydm_get_min_rssi(_adapter *adapter)
+{
+ struct dm_struct *phydm = adapter_to_phydm(adapter);
+ s8 rssi_min = 0;
+
+ rssi_min = phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_RSSI_MIN);
+ return rssi_min;
+}
+
+u8 rtw_phydm_get_cur_igi(_adapter *adapter)
+{
+ struct dm_struct *phydm = adapter_to_phydm(adapter);
+ u8 cur_igi = 0;
+
+ cur_igi = phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CURR_IGI);
+ return cur_igi;
+}
+
+u32 rtw_phydm_get_phy_cnt(_adapter *adapter, enum phy_cnt cnt)
+{
+ struct dm_struct *phydm = adapter_to_phydm(adapter);
+
+ if (cnt == FA_OFDM)
+ return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_FA_OFDM);
+ else if (cnt == FA_CCK)
+ return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_FA_CCK);
+ else if (cnt == FA_TOTAL)
+ return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_FA_TOTAL);
+ else if (cnt == CCA_OFDM)
+ return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CCA_OFDM);
+ else if (cnt == CCA_CCK)
+ return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CCA_CCK);
+ else if (cnt == CCA_ALL)
+ return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CCA_ALL);
+ else if (cnt == CRC32_OK_VHT)
+ return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_VHT);
+ else if (cnt == CRC32_OK_HT)
+ return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_HT);
+ else if (cnt == CRC32_OK_LEGACY)
+ return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_LEGACY);
+ else if (cnt == CRC32_OK_CCK)
+ return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_OK_CCK);
+ else if (cnt == CRC32_ERROR_VHT)
+ return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_VHT);
+ else if (cnt == CRC32_ERROR_HT)
+ return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_HT);
+ else if (cnt == CRC32_ERROR_LEGACY)
+ return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_LEGACY);
+ else if (cnt == CRC32_ERROR_CCK)
+ return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CRC32_ERROR_CCK);
+ else
+ return 0;
+}
+
+u8 rtw_phydm_is_iqk_in_progress(_adapter *adapter)
+{
+ u8 rts = _FALSE;
+ struct dm_struct *podmpriv = adapter_to_phydm(adapter);
+
+ odm_acquire_spin_lock(podmpriv, RT_IQK_SPINLOCK);
+ if (podmpriv->rf_calibrate_info.is_iqk_in_progress == _TRUE) {
+ RTW_ERR("IQK InProgress\n");
+ rts = _TRUE;
+ }
+ odm_release_spin_lock(podmpriv, RT_IQK_SPINLOCK);
+
+ return rts;
+}
+
+void SetHalODMVar(
+ PADAPTER Adapter,
+ HAL_ODM_VARIABLE eVariable,
+ PVOID pValue1,
+ BOOLEAN bSet)
+{
+ struct dm_struct *podmpriv = adapter_to_phydm(Adapter);
+ /* _irqL irqL; */
+ switch (eVariable) {
+ case HAL_ODM_STA_INFO: {
+ struct sta_info *psta = (struct sta_info *)pValue1;
+
+ if (bSet) {
+ RTW_INFO("### Set STA_(%d) info ###\n", psta->cmn.mac_id);
+ odm_cmn_info_ptr_array_hook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->cmn.mac_id, psta);
+ psta->cmn.dm_ctrl = STA_DM_CTRL_ACTIVE;
+ phydm_cmn_sta_info_hook(podmpriv, psta->cmn.mac_id, &(psta->cmn));
+ } else {
+ RTW_INFO("### Clean STA_(%d) info ###\n", psta->cmn.mac_id);
+ /* _enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */
+ psta->cmn.dm_ctrl = 0;
+ odm_cmn_info_ptr_array_hook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->cmn.mac_id, NULL);
+ phydm_cmn_sta_info_hook(podmpriv, psta->cmn.mac_id, NULL);
+
+ /* _exit_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */
+ }
+ }
+ break;
+ case HAL_ODM_P2P_STATE:
+ odm_cmn_info_update(podmpriv, ODM_CMNINFO_WIFI_DIRECT, bSet);
+ break;
+ case HAL_ODM_WIFI_DISPLAY_STATE:
+ odm_cmn_info_update(podmpriv, ODM_CMNINFO_WIFI_DISPLAY, bSet);
+ break;
+ case HAL_ODM_REGULATION:
+ /* used to auto enable/disable adaptivity by SD7 */
+ odm_cmn_info_init(podmpriv, ODM_CMNINFO_DOMAIN_CODE_2G, 0);
+ odm_cmn_info_init(podmpriv, ODM_CMNINFO_DOMAIN_CODE_5G, 0);
+ break;
+ case HAL_ODM_INITIAL_GAIN: {
+ u8 rx_gain = *((u8 *)(pValue1));
+ /*printk("rx_gain:%x\n",rx_gain);*/
+ if (rx_gain == 0xff) {/*restore rx gain*/
+ /*odm_write_dig(podmpriv,pDigTable->backup_ig_value);*/
+ odm_pause_dig(podmpriv, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_0, rx_gain);
+ } else {
+ /*pDigTable->backup_ig_value = pDigTable->cur_ig_value;*/
+ /*odm_write_dig(podmpriv,rx_gain);*/
+ odm_pause_dig(podmpriv, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_0, rx_gain);
+ }
+ }
+ break;
+ case HAL_ODM_RX_INFO_DUMP: {
+ u8 cur_igi = 0;
+ s8 rssi_min;
+ void *sel;
+
+ sel = pValue1;
+ cur_igi = rtw_phydm_get_cur_igi(Adapter);
+ rssi_min = rtw_phydm_get_min_rssi(Adapter);
+
+ _RTW_PRINT_SEL(sel, "============ Rx Info dump ===================\n");
+ _RTW_PRINT_SEL(sel, "is_linked = %d, rssi_min = %d(%%), current_igi = 0x%x\n", podmpriv->is_linked, rssi_min, cur_igi);
+ _RTW_PRINT_SEL(sel, "cnt_cck_fail = %d, cnt_ofdm_fail = %d, Total False Alarm = %d\n",
+ rtw_phydm_get_phy_cnt(Adapter, FA_CCK),
+ rtw_phydm_get_phy_cnt(Adapter, FA_OFDM),
+ rtw_phydm_get_phy_cnt(Adapter, FA_TOTAL));
+
+ if (podmpriv->is_linked) {
+ _RTW_PRINT_SEL(sel, "rx_rate = %s", HDATA_RATE(podmpriv->rx_rate));
+ if (IS_HARDWARE_TYPE_8814A(Adapter))
+ _RTW_PRINT_SEL(sel, " rssi_a = %d(%%), rssi_b = %d(%%), rssi_c = %d(%%), rssi_d = %d(%%)\n",
+ podmpriv->rssi_a, podmpriv->rssi_b, podmpriv->rssi_c, podmpriv->rssi_d);
+ else
+ _RTW_PRINT_SEL(sel, " rssi_a = %d(%%), rssi_b = %d(%%)\n", podmpriv->rssi_a, podmpriv->rssi_b);
+#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
+ rtw_dump_raw_rssi_info(Adapter, sel);
+#endif
+ }
+ }
+ break;
+ case HAL_ODM_RX_Dframe_INFO: {
+ void *sel;
+
+ sel = pValue1;
+
+ /*_RTW_PRINT_SEL(sel , "HAL_ODM_RX_Dframe_INFO\n");*/
+#ifdef DBG_RX_DFRAME_RAW_DATA
+ rtw_dump_rx_dframe_info(Adapter, sel);
+#endif
+ }
+ break;
+
+#ifdef CONFIG_ANTENNA_DIVERSITY
+ case HAL_ODM_ANTDIV_SELECT: {
+ u8 antenna = (*(u8 *)pValue1);
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+ /*switch antenna*/
+ odm_update_rx_idle_ant(&pHalData->odmpriv, antenna);
+ /*RTW_INFO("==> HAL_ODM_ANTDIV_SELECT, Ant_(%s)\n", (antenna == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");*/
+
+ }
+ break;
+#endif
+
+ default:
+ break;
+ }
+}
+
+void GetHalODMVar(
+ PADAPTER Adapter,
+ HAL_ODM_VARIABLE eVariable,
+ PVOID pValue1,
+ PVOID pValue2)
+{
+ struct dm_struct *podmpriv = adapter_to_phydm(Adapter);
+
+ switch (eVariable) {
+#ifdef CONFIG_ANTENNA_DIVERSITY
+ case HAL_ODM_ANTDIV_SELECT: {
+ struct phydm_fat_struct *pDM_FatTable = &podmpriv->dm_fat_table;
+ *((u8 *)pValue1) = pDM_FatTable->rx_idle_ant;
+ }
+ break;
+#endif
+ case HAL_ODM_INITIAL_GAIN:
+ *((u8 *)pValue1) = rtw_phydm_get_cur_igi(Adapter);
+ break;
+ default:
+ break;
+ }
+}
+
+#ifdef RTW_HALMAC
+#include "../hal_halmac.h"
+#endif
+
+enum hal_status
+rtw_phydm_fw_iqk(
+ struct dm_struct *p_dm_odm,
+ u8 clear,
+ u8 segment
+)
+{
+ #ifdef RTW_HALMAC
+ struct _ADAPTER *adapter = p_dm_odm->adapter;
+
+ if (rtw_halmac_iqk(adapter_to_dvobj(adapter), clear, segment) == 0)
+ return HAL_STATUS_SUCCESS;
+ #endif
+ return HAL_STATUS_FAILURE;
+}
+
+enum hal_status
+rtw_phydm_cfg_phy_para(
+ struct dm_struct *p_dm_odm,
+ enum phydm_halmac_param config_type,
+ u32 offset,
+ u32 data,
+ u32 mask,
+ enum rf_path e_rf_path,
+ u32 delay_time)
+{
+ #ifdef RTW_HALMAC
+ struct _ADAPTER *adapter = p_dm_odm->adapter;
+ struct rtw_phy_parameter para;
+
+ switch (config_type) {
+ case PHYDM_HALMAC_CMD_MAC_W8:
+ para.cmd = 0; /* MAC register */
+ para.data.mac.offset = offset;
+ para.data.mac.value = data;
+ para.data.mac.msk = mask;
+ para.data.mac.msk_en = (mask) ? 1 : 0;
+ para.data.mac.size = 1;
+ break;
+ case PHYDM_HALMAC_CMD_MAC_W16:
+ para.cmd = 0; /* MAC register */
+ para.data.mac.offset = offset;
+ para.data.mac.value = data;
+ para.data.mac.msk = mask;
+ para.data.mac.msk_en = (mask) ? 1 : 0;
+ para.data.mac.size = 2;
+ break;
+ case PHYDM_HALMAC_CMD_MAC_W32:
+ para.cmd = 0; /* MAC register */
+ para.data.mac.offset = offset;
+ para.data.mac.value = data;
+ para.data.mac.msk = mask;
+ para.data.mac.msk_en = (mask) ? 1 : 0;
+ para.data.mac.size = 4;
+ break;
+ case PHYDM_HALMAC_CMD_BB_W8:
+ para.cmd = 1; /* BB register */
+ para.data.bb.offset = offset;
+ para.data.bb.value = data;
+ para.data.bb.msk = mask;
+ para.data.bb.msk_en = (mask) ? 1 : 0;
+ para.data.bb.size = 1;
+ break;
+ case PHYDM_HALMAC_CMD_BB_W16:
+ para.cmd = 1; /* BB register */
+ para.data.bb.offset = offset;
+ para.data.bb.value = data;
+ para.data.bb.msk = mask;
+ para.data.bb.msk_en = (mask) ? 1 : 0;
+ para.data.bb.size = 2;
+ break;
+ case PHYDM_HALMAC_CMD_BB_W32:
+ para.cmd = 1; /* BB register */
+ para.data.bb.offset = offset;
+ para.data.bb.value = data;
+ para.data.bb.msk = mask;
+ para.data.bb.msk_en = (mask) ? 1 : 0;
+ para.data.bb.size = 4;
+ break;
+ case PHYDM_HALMAC_CMD_RF_W:
+ para.cmd = 2; /* RF register */
+ para.data.rf.offset = offset;
+ para.data.rf.value = data;
+ para.data.rf.msk = mask;
+ para.data.rf.msk_en = (mask) ? 1 : 0;
+ if (e_rf_path == RF_PATH_A)
+ para.data.rf.path = 0;
+ else if (e_rf_path == RF_PATH_B)
+ para.data.rf.path = 1;
+ else if (e_rf_path == RF_PATH_C)
+ para.data.rf.path = 2;
+ else if (e_rf_path == RF_PATH_D)
+ para.data.rf.path = 3;
+ else
+ para.data.rf.path = 0;
+ break;
+ case PHYDM_HALMAC_CMD_DELAY_US:
+ para.cmd = 3; /* Delay */
+ para.data.delay.unit = 0; /* microsecond */
+ para.data.delay.value = delay_time;
+ break;
+ case PHYDM_HALMAC_CMD_DELAY_MS:
+ para.cmd = 3; /* Delay */
+ para.data.delay.unit = 1; /* millisecond */
+ para.data.delay.value = delay_time;
+ break;
+ case PHYDM_HALMAC_CMD_END:
+ para.cmd = 0xFF; /* End command */
+ break;
+ default:
+ return HAL_STATUS_FAILURE;
+ }
+
+ if (rtw_halmac_cfg_phy_para(adapter_to_dvobj(adapter), ¶))
+ return HAL_STATUS_FAILURE;
+ #endif /*RTW_HALMAC*/
+ return HAL_STATUS_SUCCESS;
+}
+
+
+#ifdef CONFIG_LPS_LCLK_WD_TIMER
+void rtw_phydm_wd_lps_lclk_hdl(_adapter *adapter)
+{
+ struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
+ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
+ struct dm_struct *podmpriv = &(pHalData->odmpriv);
+ struct sta_priv *pstapriv = &adapter->stapriv;
+ struct sta_info *psta = NULL;
+ u8 rssi_min = 0;
+ u32 rssi_rpt = 0;
+ bool is_linked = _FALSE;
+
+ if (!rtw_is_hw_init_completed(adapter))
+ return;
+
+ if (rtw_mi_check_status(adapter, MI_ASSOC))
+ is_linked = _TRUE;
+
+ if (is_linked == _FALSE)
+ return;
+
+ psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
+ if (psta == NULL)
+ return;
+
+ odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_LINK, is_linked);
+
+ phydm_watchdog_lps_32k(&pHalData->odmpriv);
+}
+
+void rtw_phydm_watchdog_in_lps_lclk(_adapter *adapter)
+{
+ struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
+ struct sta_priv *pstapriv = &adapter->stapriv;
+ struct sta_info *psta = NULL;
+ u8 cur_igi = 0;
+ s8 min_rssi = 0;
+
+ if (!rtw_is_hw_init_completed(adapter))
+ return;
+
+ psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
+ if (psta == NULL)
+ return;
+
+ cur_igi = rtw_phydm_get_cur_igi(adapter);
+ min_rssi = rtw_phydm_get_min_rssi(adapter);
+ if (min_rssi <= 0)
+ min_rssi = psta->cmn.rssi_stat.rssi;
+ /*RTW_INFO("%s "ADPT_FMT" cur_ig_value=%d, min_rssi = %d\n", __func__, ADPT_ARG(adapter), cur_igi, min_rssi);*/
+
+ if (min_rssi <= 0)
+ return;
+
+ if ((cur_igi > min_rssi + 5) ||
+ (cur_igi < min_rssi - 5)) {
+#ifdef CONFIG_LPS
+ rtw_dm_in_lps_wk_cmd(adapter);
+#endif
+ }
+}
+#endif /*CONFIG_LPS_LCLK_WD_TIMER*/
+
+void dump_sta_traffic(void *sel, _adapter *adapter, struct sta_info *psta)
+{
+ struct ra_sta_info *ra_info;
+ u8 curr_sgi = _FALSE;
+
+ if (!psta)
+ return;
+ RTW_PRINT_SEL(sel, "====== mac_id : %d ======\n", psta->cmn.mac_id);
+
+ ra_info = &psta->cmn.ra_info;
+ curr_sgi = (ra_info->curr_tx_rate & 0x80) ? _TRUE : _FALSE;
+ RTW_PRINT_SEL(sel, "tx_rate : %s(%s) rx_rate : %s, rx_rate_bmc : %s, rssi : %d %%\n"
+ , HDATA_RATE((ra_info->curr_tx_rate & 0x7F)), (curr_sgi) ? "S" : "L"
+ , HDATA_RATE((psta->curr_rx_rate & 0x7F)), HDATA_RATE((psta->curr_rx_rate_bmc & 0x7F)), psta->cmn.rssi_stat.rssi
+ );
+
+ if (0) {
+ RTW_PRINT_SEL(sel, "tx_bytes:%llu(%llu - %llu)\n"
+ , psta->sta_stats.tx_bytes - psta->sta_stats.last_tx_bytes
+ , psta->sta_stats.tx_bytes, psta->sta_stats.last_tx_bytes
+ );
+ RTW_PRINT_SEL(sel, "rx_uc_bytes:%llu(%llu - %llu)\n"
+ , sta_rx_uc_bytes(psta) - sta_last_rx_uc_bytes(psta)
+ , sta_rx_uc_bytes(psta), sta_last_rx_uc_bytes(psta)
+ );
+ RTW_PRINT_SEL(sel, "rx_mc_bytes:%llu(%llu - %llu)\n"
+ , psta->sta_stats.rx_mc_bytes - psta->sta_stats.last_rx_mc_bytes
+ , psta->sta_stats.rx_mc_bytes, psta->sta_stats.last_rx_mc_bytes
+ );
+ RTW_PRINT_SEL(sel, "rx_bc_bytes:%llu(%llu - %llu)\n"
+ , psta->sta_stats.rx_bc_bytes - psta->sta_stats.last_rx_bc_bytes
+ , psta->sta_stats.rx_bc_bytes, psta->sta_stats.last_rx_bc_bytes
+ );
+ }
+
+ RTW_PRINT_SEL(sel, "TP {Tx,Rx,Total} = { %d , %d , %d } Mbps\n",
+ (psta->sta_stats.tx_tp_mbytes << 3), (psta->sta_stats.rx_tp_mbytes << 3),
+ (psta->sta_stats.tx_tp_mbytes + psta->sta_stats.rx_tp_mbytes) << 3);
+
+ RTW_PRINT_SEL(sel, "Moving-AVG TP {Tx,Rx,Total} = { %d , %d , %d } Mbps\n\n",
+ (psta->cmn.tx_moving_average_tp << 3), (psta->cmn.rx_moving_average_tp << 3),
+ (psta->cmn.tx_moving_average_tp + psta->cmn.rx_moving_average_tp) << 3);
+
+}
+
+void dump_sta_info(void *sel, struct sta_info *psta)
+{
+ struct ra_sta_info *ra_info;
+ u8 curr_tx_sgi = _FALSE;
+ u8 curr_tx_rate = 0;
+
+ if (!psta)
+ return;
+
+ ra_info = &psta->cmn.ra_info;
+
+ RTW_PRINT_SEL(sel, "============ STA [" MAC_FMT "] ===================\n",
+ MAC_ARG(psta->cmn.mac_addr));
+ RTW_PRINT_SEL(sel, "mac_id : %d\n", psta->cmn.mac_id);
+ RTW_PRINT_SEL(sel, "wireless_mode : 0x%02x\n", psta->wireless_mode);
+ RTW_PRINT_SEL(sel, "mimo_type : %d\n", psta->cmn.mimo_type);
+ RTW_PRINT_SEL(sel, "bw_mode : %s, ra_bw_mode : %s\n",
+ ch_width_str(psta->cmn.bw_mode), ch_width_str(ra_info->ra_bw_mode));
+ RTW_PRINT_SEL(sel, "rate_id : %d\n", ra_info->rate_id);
+ RTW_PRINT_SEL(sel, "rssi : %d (%%), rssi_level : %d\n", psta->cmn.rssi_stat.rssi, ra_info->rssi_level);
+ RTW_PRINT_SEL(sel, "is_support_sgi : %s, is_vht_enable : %s\n",
+ (ra_info->is_support_sgi) ? "Y" : "N", (ra_info->is_vht_enable) ? "Y" : "N");
+ RTW_PRINT_SEL(sel, "disable_ra : %s, disable_pt : %s\n",
+ (ra_info->disable_ra) ? "Y" : "N", (ra_info->disable_pt) ? "Y" : "N");
+ RTW_PRINT_SEL(sel, "is_noisy : %s\n", (ra_info->is_noisy) ? "Y" : "N");
+ RTW_PRINT_SEL(sel, "txrx_state : %d\n", ra_info->txrx_state);/*0: uplink, 1:downlink, 2:bi-direction*/
+
+ curr_tx_sgi = (ra_info->curr_tx_rate & 0x80) ? _TRUE : _FALSE;
+ curr_tx_rate = ra_info->curr_tx_rate & 0x7F;
+ RTW_PRINT_SEL(sel, "curr_tx_rate : %s (%s)\n",
+ HDATA_RATE(curr_tx_rate), (curr_tx_sgi) ? "S" : "L");
+ RTW_PRINT_SEL(sel, "curr_tx_bw : %s\n", ch_width_str(ra_info->curr_tx_bw));
+ RTW_PRINT_SEL(sel, "curr_retry_ratio : %d\n", ra_info->curr_retry_ratio);
+ RTW_PRINT_SEL(sel, "ra_mask : 0x%016llx\n\n", ra_info->ramask);
+}
+
+void rtw_phydm_ra_registed(_adapter *adapter, struct sta_info *psta)
+{
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+
+ if (psta == NULL) {
+ RTW_ERR(FUNC_ADPT_FMT" sta is NULL\n", FUNC_ADPT_ARG(adapter));
+ rtw_warn_on(1);
+ return;
+ }
+
+ phydm_ra_registed(&hal_data->odmpriv, psta->cmn.mac_id, psta->cmn.rssi_stat.rssi);
+ dump_sta_info(RTW_DBGDUMP, psta);
+}
+
+static void init_phydm_info(_adapter *adapter)
+{
+ PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
+ struct dm_struct *phydm = &(hal_data->odmpriv);
+
+ halrf_cmn_info_init(phydm, HALRF_CMNINFO_FW_VER,
+ ((hal_data->firmware_version << 16) | hal_data->firmware_sub_version));
+
+ #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1))
+ /*PHYDM API - thermal trim*/
+ phydm_get_thermal_trim_offset(phydm);
+ /*PHYDM API - power trim*/
+ phydm_get_power_trim_offset(phydm);
+ #endif
+}
+void rtw_phydm_init(_adapter *adapter)
+{
+ PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
+ struct dm_struct *phydm = &(hal_data->odmpriv);
+
+ init_phydm_info(adapter);
+ odm_dm_init(phydm);
+}
+
+#ifdef CONFIG_LPS_PG
+static void _lps_pg_state_update(_adapter *adapter)
+{
+ u8 is_in_lpspg = _FALSE;
+ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
+ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
+ struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
+ struct sta_priv *pstapriv = &adapter->stapriv;
+ struct sta_info *psta = NULL;
+
+ if ((pwrpriv->lps_level == LPS_PG) && (pwrpriv->pwr_mode != PS_MODE_ACTIVE) && (pwrpriv->rpwm <= PS_STATE_S2))
+ is_in_lpspg = _TRUE;
+ psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
+
+ if (psta)
+ psta->cmn.ra_info.disable_ra = (is_in_lpspg) ? _TRUE : _FALSE;
+}
+#endif
+
+/*#define DBG_PHYDM_STATE_CHK*/
+
+
+static u8 _rtw_phydm_rfk_condition_check(_adapter *adapter)
+{
+ u8 rst = _FALSE;
+
+ if (rtw_mi_stayin_union_ch_chk(adapter))
+ rst = _TRUE;
+
+ #ifdef CONFIG_MCC_MODE
+ /*not in MCC State*/
+ if (MCC_EN(adapter))
+ if (!rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC))
+ rst = _TRUE;
+ #endif
+
+ #if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)
+
+ #endif
+
+ return rst;
+}
+#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1))
+static u8 _rtw_phydm_iqk_segment_chk(_adapter *adapter)
+{
+ u8 rst = _FALSE;
+ struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+
+#if 0
+ if (dvobj->traffic_stat.cur_tx_tp > 2 || dvobj->traffic_stat.cur_rx_tp > 2)
+ rst = _TRUE;
+#else
+ rst = _TRUE;
+#endif
+ return rst;
+}
+#endif
+
+/*check the tx low rate while unlinked to any AP;for pwr tracking */
+static u8 _rtw_phydm_pwr_tracking_rate_check(_adapter *adapter)
+{
+ int i;
+ _adapter *iface;
+ u8 if_tx_rate = 0xFF;
+ u8 tx_rate = 0xFF;
+ struct mlme_ext_priv *pmlmeext = NULL;
+ struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+
+ for (i = 0; i < dvobj->iface_nums; i++) {
+ iface = dvobj->padapters[i];
+ pmlmeext = &(iface->mlmeextpriv);
+ if ((iface) && rtw_is_adapter_up(iface)) {
+#ifdef CONFIG_P2P
+ if (!rtw_p2p_chk_role(&(iface)->wdinfo, P2P_ROLE_DISABLE))
+ if_tx_rate = IEEE80211_OFDM_RATE_6MB;
+ else
+#endif
+ if_tx_rate = pmlmeext->tx_rate;
+ if(if_tx_rate < tx_rate)
+ tx_rate = if_tx_rate;
+
+ RTW_DBG("%s i=%d tx_rate =0x%x\n", __func__, i, if_tx_rate);
+ }
+ }
+ RTW_DBG("%s tx_low_rate (unlinked to any AP)=0x%x\n", __func__, tx_rate);
+ return tx_rate;
+}
+
+#ifdef CONFIG_DYNAMIC_SOML
+void rtw_dyn_soml_byte_update(_adapter *adapter, u8 data_rate, u32 size)
+{
+ struct dm_struct *phydm = adapter_to_phydm(adapter);
+
+ phydm_soml_bytes_acq(phydm, data_rate, size);
+}
+
+void rtw_dyn_soml_para_set(_adapter *adapter, u8 train_num, u8 intvl,
+ u8 period, u8 delay)
+{
+ struct dm_struct *phydm = adapter_to_phydm(adapter);
+
+ phydm_adaptive_soml_para_set(phydm, train_num, intvl, period, delay);
+ RTW_INFO("%s.\n", __func__);
+}
+
+void rtw_dyn_soml_config(_adapter *adapter)
+{
+ RTW_INFO("%s.\n", __func__);
+
+ if (adapter->registrypriv.dyn_soml_en == 1) {
+ /* Must after phydm_adaptive_soml_init() */
+ rtw_hal_set_hwreg(adapter , HW_VAR_SET_SOML_PARAM , NULL);
+ RTW_INFO("dyn_soml_en = 1\n");
+ } else {
+ if (adapter->registrypriv.dyn_soml_en == 2) {
+ rtw_dyn_soml_para_set(adapter,
+ adapter->registrypriv.dyn_soml_train_num,
+ adapter->registrypriv.dyn_soml_interval,
+ adapter->registrypriv.dyn_soml_period,
+ adapter->registrypriv.dyn_soml_delay);
+ RTW_INFO("dyn_soml_en = 2\n");
+ RTW_INFO("dyn_soml_en, param = %d, %d, %d, %d\n",
+ adapter->registrypriv.dyn_soml_train_num,
+ adapter->registrypriv.dyn_soml_interval,
+ adapter->registrypriv.dyn_soml_period,
+ adapter->registrypriv.dyn_soml_delay);
+ } else if (adapter->registrypriv.dyn_soml_en == 0) {
+ RTW_INFO("dyn_soml_en = 0\n");
+ } else
+ RTW_ERR("%s, wrong setting: dyn_soml_en = %d\n", __func__,
+ adapter->registrypriv.dyn_soml_en);
+ }
+}
+#endif
+
+void rtw_phydm_watchdog(_adapter *adapter)
+{
+ u8 bLinked = _FALSE;
+ u8 bsta_state = _FALSE;
+ u8 bBtDisabled = _TRUE;
+ u8 rfk_forbidden = _TRUE;
+ u8 segment_iqk = _TRUE;
+ u8 tx_unlinked_low_rate = 0xFF;
+ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter);
+ struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
+
+ if (!rtw_is_hw_init_completed(adapter)) {
+ RTW_DBG("%s skip due to hw_init_completed == FALSE\n", __func__);
+ return;
+ }
+ if (rtw_mi_check_fwstate(adapter, _FW_UNDER_SURVEY))
+ pHalData->bScanInProcess = _TRUE;
+ else
+ pHalData->bScanInProcess = _FALSE;
+
+ if (rtw_mi_check_status(adapter, MI_ASSOC)) {
+ bLinked = _TRUE;
+ if (rtw_mi_check_status(adapter, MI_STA_LINKED))
+ bsta_state = _TRUE;
+ }
+
+ odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_LINK, bLinked);
+ odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_STATION_STATE, bsta_state);
+
+#ifdef CONFIG_BT_COEXIST
+ bBtDisabled = rtw_btcoex_IsBtDisabled(adapter);
+#endif /* CONFIG_BT_COEXIST */
+ odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_BT_ENABLED,
+ (bBtDisabled == _TRUE) ? _FALSE : _TRUE);
+#ifdef CONFIG_LPS_PG
+ _lps_pg_state_update(adapter);
+#endif
+
+ if (bLinked == _TRUE) {
+ rfk_forbidden = (_rtw_phydm_rfk_condition_check(adapter) == _TRUE) ? _FALSE : _TRUE;
+ halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_RFK_FORBIDDEN, rfk_forbidden);
+
+ #if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1))
+ segment_iqk = _rtw_phydm_iqk_segment_chk(adapter);
+ halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_IQK_SEGMENT, segment_iqk);
+ #endif
+ } else {
+ tx_unlinked_low_rate = _rtw_phydm_pwr_tracking_rate_check(adapter);
+ halrf_cmn_info_set(&pHalData->odmpriv, HALRF_CMNINFO_RATE_INDEX, tx_unlinked_low_rate);
+ }
+#ifdef DBG_PHYDM_STATE_CHK
+ RTW_INFO("%s rfk_forbidden = %s, segment_iqk = %s\n",
+ __func__, (rfk_forbidden) ? "Y" : "N", (segment_iqk) ? "Y" : "N");
+#endif
+
+ /*if (!rtw_mi_stayin_union_band_chk(adapter)) {
+ #ifdef DBG_PHYDM_STATE_CHK
+ RTW_ERR("Not stay in union band, skip phydm\n");
+ #endif
+ goto _exit;
+ }*/
+ if (pwrctl->bpower_saving)
+ phydm_watchdog_lps(&pHalData->odmpriv);
+ else
+ phydm_watchdog(&pHalData->odmpriv);
+
+ #ifdef CONFIG_RTW_ACS
+ rtw_acs_update_current_info(adapter);
+ #endif
+
+_exit:
+ return;
+}
+
diff --git a/hal/hal_dm.h b/hal/hal_dm.h
index 1232708..299a060 100644
--- a/hal/hal_dm.h
+++ b/hal/hal_dm.h
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,15 +11,78 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#ifndef __HAL_DM_H__
#define __HAL_DM_H__
+#define adapter_to_phydm(adapter) (&(GET_HAL_DATA(adapter)->odmpriv))
+
void Init_ODM_ComInfo(_adapter *adapter);
+void rtw_phydm_init(_adapter *adapter);
+
+void rtw_hal_turbo_edca(_adapter *adapter);
+u8 rtw_phydm_is_iqk_in_progress(_adapter *adapter);
+
+void GetHalODMVar(
+ PADAPTER Adapter,
+ HAL_ODM_VARIABLE eVariable,
+ PVOID pValue1,
+ PVOID pValue2);
+void SetHalODMVar(
+ PADAPTER Adapter,
+ HAL_ODM_VARIABLE eVariable,
+ PVOID pValue1,
+ BOOLEAN bSet);
+
+void rtw_phydm_ra_registed(_adapter *adapter, struct sta_info *psta);
+
+#ifdef CONFIG_DYNAMIC_SOML
+void rtw_dyn_soml_byte_update(_adapter *adapter, u8 data_rate, u32 size);
+void rtw_dyn_soml_para_set(_adapter *adapter, u8 train_num, u8 intvl,
+ u8 period, u8 delay);
+void rtw_dyn_soml_config(_adapter *adapter);
+#endif
+void rtw_phydm_watchdog(_adapter *adapter);
+
+void rtw_hal_update_iqk_fw_offload_cap(_adapter *adapter);
+void dump_sta_info(void *sel, struct sta_info *psta);
+void dump_sta_traffic(void *sel, _adapter *adapter, struct sta_info *psta);
+
+#ifdef CONFIG_DBG_RF_CAL
+void rtw_hal_iqk_test(_adapter *adapter, bool recovery, bool clear, bool segment);
+void rtw_hal_lck_test(_adapter *adapter);
+#endif
+
+s8 rtw_phydm_get_min_rssi(_adapter *adapter);
+u8 rtw_phydm_get_cur_igi(_adapter *adapter);
+
+
+#ifdef CONFIG_LPS_LCLK_WD_TIMER
+extern void phydm_rssi_monitor_check(void *p_dm_void);
+
+void rtw_phydm_wd_lps_lclk_hdl(_adapter *adapter);
+void rtw_phydm_watchdog_in_lps_lclk(_adapter *adapter);
+#endif
+
+enum phy_cnt {
+ FA_OFDM,
+ FA_CCK,
+ FA_TOTAL,
+ CCA_OFDM,
+ CCA_CCK,
+ CCA_ALL,
+ CRC32_OK_VHT,
+ CRC32_OK_HT,
+ CRC32_OK_LEGACY,
+ CRC32_OK_CCK,
+ CRC32_ERROR_VHT,
+ CRC32_ERROR_HT,
+ CRC32_ERROR_LEGACY,
+ CRC32_ERROR_CCK,
+};
+u32 rtw_phydm_get_phy_cnt(_adapter *adapter, enum phy_cnt cnt);
+#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8814B_SUPPORT == 1))
+void rtw_phydm_iqk_trigger(_adapter *adapter);
+#endif
#endif /* __HAL_DM_H__ */
diff --git a/hal/hal_dm_acs.c b/hal/hal_dm_acs.c
new file mode 100644
index 0000000..5c19d99
--- /dev/null
+++ b/hal/hal_dm_acs.c
@@ -0,0 +1,554 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2014 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#include
+#include
+
+
+#if defined(CONFIG_RTW_ACS) || defined(CONFIG_BACKGROUND_NOISE_MONITOR)
+static void _rtw_bss_nums_count(_adapter *adapter, u8 *pbss_nums)
+{
+ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv);
+ _queue *queue = &(pmlmepriv->scanned_queue);
+ struct wlan_network *pnetwork = NULL;
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+
+ _list *plist, *phead;
+ _irqL irqL;
+ int chan_idx = -1;
+
+ if (pbss_nums == NULL) {
+ RTW_ERR("%s pbss_nums is null pointer\n", __func__);
+ return;
+ }
+ _rtw_memset(pbss_nums, 0, MAX_CHANNEL_NUM);
+
+ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+ phead = get_list_head(queue);
+ plist = get_next(phead);
+ while (1) {
+ if (rtw_end_of_queue_search(phead, plist) == _TRUE)
+ break;
+
+ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list);
+ if (!pnetwork)
+ break;
+ chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), pnetwork->network.Configuration.DSConfig);
+ if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {
+ RTW_ERR("%s can't get chan_idx(CH:%d)\n",
+ __func__, pnetwork->network.Configuration.DSConfig);
+ chan_idx = 0;
+ }
+ /*if (pnetwork->network.Reserved[0] != BSS_TYPE_PROB_REQ)*/
+
+ pbss_nums[chan_idx]++;
+
+ plist = get_next(plist);
+ }
+ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL);
+}
+
+u8 rtw_get_ch_num_by_idx(_adapter *adapter, u8 idx)
+{
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+ RT_CHANNEL_INFO *pch_set = rfctl->channel_set;
+ u8 max_chan_nums = rfctl->max_chan_nums;
+
+ if (idx >= max_chan_nums)
+ return 0;
+ return pch_set[idx].ChannelNum;
+}
+#endif /*defined(CONFIG_RTW_ACS) || defined(CONFIG_BACKGROUND_NOISE_MONITOR)*/
+
+
+#ifdef CONFIG_RTW_ACS
+void rtw_acs_version_dump(void *sel, _adapter *adapter)
+{
+ _RTW_PRINT_SEL(sel, "RTK_ACS VER_%d\n", RTK_ACS_VERSION);
+}
+u8 rtw_phydm_clm_ratio(_adapter *adapter)
+{
+ struct dm_struct *phydm = adapter_to_phydm(adapter);
+
+ return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_CLM_RATIO);
+}
+u8 rtw_phydm_nhm_ratio(_adapter *adapter)
+{
+ struct dm_struct *phydm = adapter_to_phydm(adapter);
+
+ return phydm_cmn_info_query(phydm, (enum phydm_info_query) PHYDM_INFO_NHM_RATIO);
+}
+void rtw_acs_reset(_adapter *adapter)
+{
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+ struct auto_chan_sel *pacs = &hal_data->acs;
+
+ _rtw_memset(pacs, 0, sizeof(struct auto_chan_sel));
+ #ifdef CONFIG_RTW_ACS_DBG
+ rtw_acs_adv_reset(adapter);
+ #endif /*CONFIG_RTW_ACS_DBG*/
+}
+
+#ifdef CONFIG_RTW_ACS_DBG
+u8 rtw_is_acs_igi_valid(_adapter *adapter)
+{
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+ struct auto_chan_sel *pacs = &hal_data->acs;
+
+ if ((pacs->igi) && ((pacs->igi >= 0x1E) || (pacs->igi < 0x60)))
+ return _TRUE;
+
+ return _FALSE;
+}
+void rtw_acs_adv_setting(_adapter *adapter, RT_SCAN_TYPE scan_type, u16 scan_time, u8 igi, u8 bw)
+{
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+ struct auto_chan_sel *pacs = &hal_data->acs;
+ struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
+ struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
+
+ pacs->scan_type = scan_type;
+ pacs->scan_time = scan_time;
+ pacs->igi = igi;
+ pacs->bw = bw;
+ RTW_INFO("[ACS] ADV setting - scan_type:%c, ch_ms:%d(ms), igi:0x%02x, bw:%d\n",
+ pacs->scan_type ? 'A' : 'P', pacs->scan_time, pacs->igi, pacs->bw);
+}
+void rtw_acs_adv_reset(_adapter *adapter)
+{
+ rtw_acs_adv_setting(adapter, SCAN_ACTIVE, 0, 0, 0);
+}
+#endif /*CONFIG_RTW_ACS_DBG*/
+
+void rtw_acs_trigger(_adapter *adapter, u16 scan_time_ms, u8 scan_chan, enum NHM_PID pid)
+{
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+ struct dm_struct *phydm = adapter_to_phydm(adapter);
+#if (RTK_ACS_VERSION == 3)
+ struct clm_para_info clm_para;
+ struct nhm_para_info nhm_para;
+ struct env_trig_rpt trig_rpt;
+
+ scan_time_ms -= 10;
+
+ init_acs_clm(clm_para, scan_time_ms);
+
+ if (pid == NHM_PID_IEEE_11K_HIGH)
+ init_11K_high_nhm(nhm_para, scan_time_ms);
+ else if (pid == NHM_PID_IEEE_11K_LOW)
+ init_11K_low_nhm(nhm_para, scan_time_ms);
+ else
+ init_acs_nhm(nhm_para, scan_time_ms);
+
+ hal_data->acs.trig_rst = phydm_env_mntr_trigger(phydm, &nhm_para, &clm_para, &trig_rpt);
+ if (hal_data->acs.trig_rst == (NHM_SUCCESS | CLM_SUCCESS)) {
+ hal_data->acs.trig_rpt.clm_rpt_stamp = trig_rpt.clm_rpt_stamp;
+ hal_data->acs.trig_rpt.nhm_rpt_stamp = trig_rpt.nhm_rpt_stamp;
+ /*RTW_INFO("[ACS] trigger success (rst = 0x%02x, clm_stamp:%d, nhm_stamp:%d)\n",
+ hal_data->acs.trig_rst, hal_data->acs.trig_rpt.clm_rpt_stamp, hal_data->acs.trig_rpt.nhm_rpt_stamp);*/
+ } else
+ RTW_ERR("[ACS] trigger failed (rst = 0x%02x)\n", hal_data->acs.trig_rst);
+#else
+ phydm_ccx_monitor_trigger(phydm, scan_time_ms);
+#endif
+
+ hal_data->acs.trigger_ch = scan_chan;
+ hal_data->acs.triggered = _TRUE;
+
+ #ifdef CONFIG_RTW_ACS_DBG
+ RTW_INFO("[ACS] Trigger CH:%d, Times:%d\n", hal_data->acs.trigger_ch, scan_time_ms);
+ #endif
+}
+void rtw_acs_get_rst(_adapter *adapter)
+{
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+ struct dm_struct *phydm = adapter_to_phydm(adapter);
+ int chan_idx = -1;
+ u8 cur_chan = hal_data->acs.trigger_ch;
+
+ if (cur_chan == 0)
+ return;
+
+ if (!hal_data->acs.triggered)
+ return;
+
+ chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), cur_chan);
+ if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {
+ RTW_ERR("[ACS] %s can't get chan_idx(CH:%d)\n", __func__, cur_chan);
+ return;
+ }
+#if (RTK_ACS_VERSION == 3)
+ if (!(hal_data->acs.trig_rst == (NHM_SUCCESS | CLM_SUCCESS))) {
+ RTW_ERR("[ACS] get_rst return, due to acs trigger failed\n");
+ return;
+ }
+
+ {
+ struct env_mntr_rpt rpt = {0};
+ u8 rst;
+
+ rst = phydm_env_mntr_result(phydm, &rpt);
+ if ((rst == (NHM_SUCCESS | CLM_SUCCESS)) &&
+ (rpt.clm_rpt_stamp == hal_data->acs.trig_rpt.clm_rpt_stamp) &&
+ (rpt.nhm_rpt_stamp == hal_data->acs.trig_rpt.nhm_rpt_stamp)){
+ hal_data->acs.clm_ratio[chan_idx] = rpt.clm_ratio;
+ hal_data->acs.nhm_ratio[chan_idx] = rpt.nhm_ratio;
+ _rtw_memcpy(&hal_data->acs.nhm[chan_idx][0], rpt.nhm_result, NHM_RPT_NUM);
+
+ /*RTW_INFO("[ACS] get_rst success (rst = 0x%02x, clm_stamp:%d:%d, nhm_stamp:%d:%d)\n",
+ rst,
+ hal_data->acs.trig_rpt.clm_rpt_stamp, rpt.clm_rpt_stamp,
+ hal_data->acs.trig_rpt.nhm_rpt_stamp, rpt.nhm_rpt_stamp);*/
+ } else {
+ RTW_ERR("[ACS] get_rst failed (rst = 0x%02x, clm_stamp:%d:%d, nhm_stamp:%d:%d)\n",
+ rst,
+ hal_data->acs.trig_rpt.clm_rpt_stamp, rpt.clm_rpt_stamp,
+ hal_data->acs.trig_rpt.nhm_rpt_stamp, rpt.nhm_rpt_stamp);
+ }
+ }
+
+#else
+ phydm_ccx_monitor_result(phydm);
+
+ hal_data->acs.clm_ratio[chan_idx] = rtw_phydm_clm_ratio(adapter);
+ hal_data->acs.nhm_ratio[chan_idx] = rtw_phydm_nhm_ratio(adapter);
+#endif
+ hal_data->acs.triggered = _FALSE;
+ #ifdef CONFIG_RTW_ACS_DBG
+ RTW_INFO("[ACS] Result CH:%d, CLM:%d NHM:%d\n",
+ cur_chan, hal_data->acs.clm_ratio[chan_idx], hal_data->acs.nhm_ratio[chan_idx]);
+ #endif
+}
+
+void _rtw_phydm_acs_select_best_chan(_adapter *adapter)
+{
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+ u8 ch_idx;
+ u8 ch_idx_24g = 0xFF, ch_idx_5g = 0xFF;
+ u8 min_itf_24g = 0xFF, min_itf_5g = 0xFF;
+ u8 *pbss_nums = hal_data->acs.bss_nums;
+ u8 *pclm_ratio = hal_data->acs.clm_ratio;
+ u8 *pnhm_ratio = hal_data->acs.nhm_ratio;
+ u8 *pinterference_time = hal_data->acs.interference_time;
+ u8 max_chan_nums = rfctl->max_chan_nums;
+
+ for (ch_idx = 0; ch_idx < max_chan_nums; ch_idx++) {
+ if (pbss_nums[ch_idx])
+ pinterference_time[ch_idx] = (pclm_ratio[ch_idx] / 2) + pnhm_ratio[ch_idx];
+ else
+ pinterference_time[ch_idx] = pclm_ratio[ch_idx] + pnhm_ratio[ch_idx];
+
+ if (rtw_get_ch_num_by_idx(adapter, ch_idx) < 14) {
+ if (pinterference_time[ch_idx] < min_itf_24g) {
+ min_itf_24g = pinterference_time[ch_idx];
+ ch_idx_24g = ch_idx;
+ }
+ } else {
+ if (pinterference_time[ch_idx] < min_itf_5g) {
+ min_itf_5g = pinterference_time[ch_idx];
+ ch_idx_5g = ch_idx;
+ }
+ }
+ }
+ if (ch_idx_24g != 0xFF)
+ hal_data->acs.best_chan_24g = rtw_get_ch_num_by_idx(adapter, ch_idx_24g);
+
+ if (ch_idx_5g != 0xFF)
+ hal_data->acs.best_chan_5g = rtw_get_ch_num_by_idx(adapter, ch_idx_5g);
+
+ hal_data->acs.trigger_ch = 0;
+}
+
+void rtw_acs_info_dump(void *sel, _adapter *adapter)
+{
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+ u8 max_chan_nums = rfctl->max_chan_nums;
+ u8 ch_idx, ch_num;
+
+ _RTW_PRINT_SEL(sel, "========== ACS (VER-%d) ==========\n", RTK_ACS_VERSION);
+ _RTW_PRINT_SEL(sel, "Best 24G Channel:%d\n", hal_data->acs.best_chan_24g);
+ _RTW_PRINT_SEL(sel, "Best 5G Channel:%d\n\n", hal_data->acs.best_chan_5g);
+
+ #ifdef CONFIG_RTW_ACS_DBG
+ _RTW_PRINT_SEL(sel, "Advanced setting - scan_type:%c, ch_ms:%d(ms), igi:0x%02x, bw:%d\n",
+ hal_data->acs.scan_type ? 'A' : 'P', hal_data->acs.scan_time, hal_data->acs.igi, hal_data->acs.bw);
+
+ _RTW_PRINT_SEL(sel, "BW 20MHz\n");
+ _RTW_PRINT_SEL(sel, "%5s %3s %3s %3s(%%) %3s(%%) %3s\n",
+ "Index", "CH", "BSS", "CLM", "NHM", "ITF");
+
+ for (ch_idx = 0; ch_idx < max_chan_nums; ch_idx++) {
+ ch_num = rtw_get_ch_num_by_idx(adapter, ch_idx);
+ _RTW_PRINT_SEL(sel, "%5d %3d %3d %6d %6d %3d\n",
+ ch_idx, ch_num, hal_data->acs.bss_nums[ch_idx],
+ hal_data->acs.clm_ratio[ch_idx],
+ hal_data->acs.nhm_ratio[ch_idx],
+ hal_data->acs.interference_time[ch_idx]);
+ }
+ #endif
+}
+void rtw_acs_select_best_chan(_adapter *adapter)
+{
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+
+ _rtw_bss_nums_count(adapter, hal_data->acs.bss_nums);
+ _rtw_phydm_acs_select_best_chan(adapter);
+ rtw_acs_info_dump(RTW_DBGDUMP, adapter);
+}
+
+void rtw_acs_start(_adapter *adapter)
+{
+ rtw_acs_reset(adapter);
+ if (GET_ACS_STATE(adapter) != ACS_ENABLE)
+ SET_ACS_STATE(adapter, ACS_ENABLE);
+}
+void rtw_acs_stop(_adapter *adapter)
+{
+ SET_ACS_STATE(adapter, ACS_DISABLE);
+}
+
+
+u8 rtw_acs_get_clm_ratio_by_ch_num(_adapter *adapter, u8 chan)
+{
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+ int chan_idx = -1;
+
+ chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), chan);
+ if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {
+ RTW_ERR("[ACS] Get CLM fail, can't get chan_idx(CH:%d)\n", chan);
+ return 0;
+ }
+
+ return hal_data->acs.clm_ratio[chan_idx];
+}
+u8 rtw_acs_get_clm_ratio_by_ch_idx(_adapter *adapter, u8 ch_idx)
+{
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+
+ if (ch_idx >= MAX_CHANNEL_NUM) {
+ RTW_ERR("%s [ACS] ch_idx(%d) is invalid\n", __func__, ch_idx);
+ return 0;
+ }
+
+ return hal_data->acs.clm_ratio[ch_idx];
+}
+u8 rtw_acs_get_nhm_ratio_by_ch_num(_adapter *adapter, u8 chan)
+{
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+ int chan_idx = -1;
+
+ chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), chan);
+ if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {
+ RTW_ERR("[ACS] Get NHM fail, can't get chan_idx(CH:%d)\n", chan);
+ return 0;
+ }
+
+ return hal_data->acs.nhm_ratio[chan_idx];
+}
+u8 rtw_acs_get_num_ratio_by_ch_idx(_adapter *adapter, u8 ch_idx)
+{
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+
+ if (ch_idx >= MAX_CHANNEL_NUM) {
+ RTW_ERR("%s [ACS] ch_idx(%d) is invalid\n", __func__, ch_idx);
+ return 0;
+ }
+
+ return hal_data->acs.nhm_ratio[ch_idx];
+}
+void rtw_acs_chan_info_dump(void *sel, _adapter *adapter)
+{
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+ u8 max_chan_nums = rfctl->max_chan_nums;
+ u8 ch_idx, ch_num;
+ u8 utilization;
+
+ _RTW_PRINT_SEL(sel, "BW 20MHz\n");
+ _RTW_PRINT_SEL(sel, "%5s %3s %7s(%%) %12s(%%) %11s(%%) %9s(%%) %8s(%%)\n",
+ "Index", "CH", "Quality", "Availability", "Utilization",
+ "WIFI Util", "Interference Util");
+
+ for (ch_idx = 0; ch_idx < max_chan_nums; ch_idx++) {
+ ch_num = rtw_get_ch_num_by_idx(adapter, ch_idx);
+ utilization = hal_data->acs.clm_ratio[ch_idx] + hal_data->acs.nhm_ratio[ch_idx];
+ _RTW_PRINT_SEL(sel, "%5d %3d %7d %12d %12d %12d %12d\n",
+ ch_idx, ch_num,
+ (100-hal_data->acs.interference_time[ch_idx]),
+ (100-utilization),
+ utilization,
+ hal_data->acs.clm_ratio[ch_idx],
+ hal_data->acs.nhm_ratio[ch_idx]);
+ }
+}
+void rtw_acs_current_info_dump(void *sel, _adapter *adapter)
+{
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+ u8 ch, cen_ch, bw, offset;
+
+ _RTW_PRINT_SEL(sel, "========== ACS (VER-%d) ==========\n", RTK_ACS_VERSION);
+
+ ch = rtw_get_oper_ch(adapter);
+ bw = rtw_get_oper_bw(adapter);
+ offset = rtw_get_oper_choffset(adapter);
+
+ _RTW_PRINT_SEL(sel, "Current Channel:%d\n", ch);
+ if ((bw == CHANNEL_WIDTH_80) ||(bw == CHANNEL_WIDTH_40)) {
+ cen_ch = rtw_get_center_ch(ch, bw, offset);
+ _RTW_PRINT_SEL(sel, "Center Channel:%d\n", cen_ch);
+ }
+
+ _RTW_PRINT_SEL(sel, "Current BW %s\n", ch_width_str(bw));
+ if (0)
+ _RTW_PRINT_SEL(sel, "Current IGI 0x%02x\n", rtw_phydm_get_cur_igi(adapter));
+ _RTW_PRINT_SEL(sel, "CLM:%d, NHM:%d\n\n",
+ hal_data->acs.cur_ch_clm_ratio, hal_data->acs.cur_ch_nhm_ratio);
+}
+
+void rtw_acs_update_current_info(_adapter *adapter)
+{
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+
+ hal_data->acs.cur_ch_clm_ratio = rtw_phydm_clm_ratio(adapter);
+ hal_data->acs.cur_ch_nhm_ratio = rtw_phydm_nhm_ratio(adapter);
+
+ #ifdef CONFIG_RTW_ACS_DBG
+ rtw_acs_current_info_dump(RTW_DBGDUMP, adapter);
+ #endif
+}
+#endif /*CONFIG_RTW_ACS*/
+
+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
+void rtw_noise_monitor_version_dump(void *sel, _adapter *adapter)
+{
+ _RTW_PRINT_SEL(sel, "RTK_NOISE_MONITOR VER_%d\n", RTK_NOISE_MONITOR_VERSION);
+}
+void rtw_nm_enable(_adapter *adapter)
+{
+ SET_NM_STATE(adapter, NM_ENABLE);
+}
+void rtw_nm_disable(_adapter *adapter)
+{
+ SET_NM_STATE(adapter, NM_DISABLE);
+}
+void rtw_noise_info_dump(void *sel, _adapter *adapter)
+{
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+ struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter);
+ u8 max_chan_nums = rfctl->max_chan_nums;
+ u8 ch_idx, ch_num;
+
+ _RTW_PRINT_SEL(sel, "========== NM (VER-%d) ==========\n", RTK_NOISE_MONITOR_VERSION);
+
+ _RTW_PRINT_SEL(sel, "%5s %3s %3s %10s", "Index", "CH", "BSS", "Noise(dBm)\n");
+
+ _rtw_bss_nums_count(adapter, hal_data->nm.bss_nums);
+
+ for (ch_idx = 0; ch_idx < max_chan_nums; ch_idx++) {
+ ch_num = rtw_get_ch_num_by_idx(adapter, ch_idx);
+ _RTW_PRINT_SEL(sel, "%5d %3d %3d %10d\n",
+ ch_idx, ch_num, hal_data->nm.bss_nums[ch_idx],
+ hal_data->nm.noise[ch_idx]);
+ }
+}
+
+void rtw_noise_measure(_adapter *adapter, u8 chan, u8 is_pause_dig, u8 igi_value, u32 max_time)
+{
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+ struct dm_struct *phydm = &hal_data->odmpriv;
+ int chan_idx = -1;
+ s16 noise = 0;
+
+ #ifdef DBG_NOISE_MONITOR
+ RTW_INFO("[NM] chan(%d)-PauseDIG:%s, IGIValue:0x%02x, max_time:%d (ms)\n",
+ chan, (is_pause_dig) ? "Y" : "N", igi_value, max_time);
+ #endif
+
+ chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), chan);
+ if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {
+ RTW_ERR("[NM] Get noise fail, can't get chan_idx(CH:%d)\n", chan);
+ return;
+ }
+ noise = odm_inband_noise_monitor(phydm, is_pause_dig, igi_value, max_time); /*dBm*/
+
+ hal_data->nm.noise[chan_idx] = noise;
+
+ #ifdef DBG_NOISE_MONITOR
+ RTW_INFO("[NM] %s chan_%d, noise = %d (dBm)\n", __func__, chan, hal_data->nm.noise[chan_idx]);
+
+ RTW_INFO("[NM] noise_a = %d, noise_b = %d noise_all:%d\n",
+ phydm->noise_level.noise[RF_PATH_A],
+ phydm->noise_level.noise[RF_PATH_B],
+ phydm->noise_level.noise_all);
+ #endif /*DBG_NOISE_MONITOR*/
+}
+
+s16 rtw_noise_query_by_chan_num(_adapter *adapter, u8 chan)
+{
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+ s16 noise = 0;
+ int chan_idx = -1;
+
+ chan_idx = rtw_chset_search_ch(adapter_to_chset(adapter), chan);
+ if ((chan_idx == -1) || (chan_idx >= MAX_CHANNEL_NUM)) {
+ RTW_ERR("[NM] Get noise fail, can't get chan_idx(CH:%d)\n", chan);
+ return noise;
+ }
+ noise = hal_data->nm.noise[chan_idx];
+
+ #ifdef DBG_NOISE_MONITOR
+ RTW_INFO("[NM] %s chan_%d, noise = %d (dBm)\n", __func__, chan, noise);
+ #endif/*DBG_NOISE_MONITOR*/
+ return noise;
+}
+s16 rtw_noise_query_by_chan_idx(_adapter *adapter, u8 ch_idx)
+{
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+ s16 noise = 0;
+
+ if (ch_idx >= MAX_CHANNEL_NUM) {
+ RTW_ERR("[NM] %s ch_idx(%d) is invalid\n", __func__, ch_idx);
+ return noise;
+ }
+ noise = hal_data->nm.noise[ch_idx];
+
+ #ifdef DBG_NOISE_MONITOR
+ RTW_INFO("[NM] %s ch_idx %d, noise = %d (dBm)\n", __func__, ch_idx, noise);
+ #endif/*DBG_NOISE_MONITOR*/
+ return noise;
+}
+
+s16 rtw_noise_measure_curchan(_adapter *padapter)
+{
+ s16 noise = 0;
+ u8 igi_value = 0x1E;
+ u32 max_time = 100;/* ms */
+ u8 is_pause_dig = _TRUE;
+ u8 cur_chan = rtw_get_oper_ch(padapter);
+
+ if (rtw_linked_check(padapter) == _FALSE)
+ return noise;
+
+ rtw_ps_deny(padapter, PS_DENY_IOCTL);
+ LeaveAllPowerSaveModeDirect(padapter);
+ rtw_noise_measure(padapter, cur_chan, is_pause_dig, igi_value, max_time);
+ noise = rtw_noise_query_by_chan_num(padapter, cur_chan);
+ rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL);
+
+ return noise;
+}
+#endif /*CONFIG_BACKGROUND_NOISE_MONITOR*/
+
diff --git a/hal/hal_dm_acs.h b/hal/hal_dm_acs.h
new file mode 100644
index 0000000..871c144
--- /dev/null
+++ b/hal/hal_dm_acs.h
@@ -0,0 +1,167 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+#ifndef __HAL_DM_ACS_H__
+#define __HAL_DM_ACS_H__
+#ifdef CONFIG_RTW_ACS
+#define RTK_ACS_VERSION 3
+
+#if (RTK_ACS_VERSION == 3)
+enum NHM_PID {
+ NHM_PID_ACS,
+ NHM_PID_IEEE_11K_HIGH,
+ NHM_PID_IEEE_11K_LOW,
+};
+
+#define init_clm_param(clm, app, lv, time) \
+ do {\
+ clm.clm_app = app;\
+ clm.clm_lv = lv;\
+ clm.mntr_time = time;\
+ } while (0)
+
+#define init_nhm_param(nhm, txon, cca, cnt_opt, app, lv, time) \
+ do {\
+ nhm.incld_txon = txon;\
+ nhm.incld_cca = cca;\
+ nhm.div_opt = cnt_opt;\
+ nhm.nhm_app = app;\
+ nhm.nhm_lv = lv;\
+ nhm.mntr_time = time;\
+ } while (0)
+
+
+#define init_acs_clm(clm, time) \
+ init_clm_param(clm, CLM_ACS, CLM_LV_2, time)
+
+#define init_acs_nhm(nhm, time) \
+ init_nhm_param(nhm, NHM_EXCLUDE_TXON, NHM_EXCLUDE_CCA, NHM_CNT_ALL, NHM_ACS, NHM_LV_2, time)
+
+#define init_11K_high_nhm(nhm, time) \
+ init_nhm_param(nhm, NHM_EXCLUDE_TXON, NHM_EXCLUDE_CCA, NHM_CNT_ALL, IEEE_11K_HIGH, NHM_LV_2, time)
+
+#define init_11K_low_nhm(nhm, time) \
+ init_nhm_param(nhm, NHM_EXCLUDE_TXON, NHM_EXCLUDE_CCA, NHM_CNT_ALL, IEEE_11K_LOW, NHM_LV_2, time)
+
+
+#endif /*(RTK_ACS_VERSION == 3)*/
+void rtw_acs_version_dump(void *sel, _adapter *adapter);
+extern void phydm_ccx_monitor_trigger(void *p_dm_void, u16 monitor_time);
+extern void phydm_ccx_monitor_result(void *p_dm_void);
+
+#define GET_ACS_STATE(padapter) (ATOMIC_READ(&GET_HAL_DATA(padapter)->acs.state))
+#define SET_ACS_STATE(padapter, set_state) (ATOMIC_SET(&GET_HAL_DATA(padapter)->acs.state, set_state))
+#define IS_ACS_ENABLE(padapter) ((GET_ACS_STATE(padapter) == ACS_ENABLE) ? _TRUE : _FALSE)
+
+enum ACS_STATE {
+ ACS_DISABLE,
+ ACS_ENABLE,
+};
+
+#define ACS_BW_20M BIT(0)
+#define ACS_BW_40M BIT(1)
+#define ACS_BW_80M BIT(2)
+#define ACS_BW_160M BIT(3)
+
+struct auto_chan_sel {
+ ATOMIC_T state;
+ u8 trigger_ch;
+ bool triggered;
+ u8 clm_ratio[MAX_CHANNEL_NUM];
+ u8 nhm_ratio[MAX_CHANNEL_NUM];
+ #if (RTK_ACS_VERSION == 3)
+ u8 nhm[MAX_CHANNEL_NUM][NHM_RPT_NUM];
+ #endif
+ u8 bss_nums[MAX_CHANNEL_NUM];
+ u8 interference_time[MAX_CHANNEL_NUM];
+ u8 cur_ch_clm_ratio;
+ u8 cur_ch_nhm_ratio;
+ u8 best_chan_5g;
+ u8 best_chan_24g;
+
+ #if (RTK_ACS_VERSION == 3)
+ u8 trig_rst;
+ struct env_trig_rpt trig_rpt;
+ #endif
+
+ #ifdef CONFIG_RTW_ACS_DBG
+ RT_SCAN_TYPE scan_type;
+ u16 scan_time;
+ u8 igi;
+ u8 bw;
+ #endif
+};
+
+#define rtw_acs_get_best_chan_24g(adapter) (GET_HAL_DATA(adapter)->acs.best_chan_24g)
+#define rtw_acs_get_best_chan_5g(adapter) (GET_HAL_DATA(adapter)->acs.best_chan_5g)
+
+#ifdef CONFIG_RTW_ACS_DBG
+#define rtw_is_acs_passiv_scan(adapter) (((GET_HAL_DATA(adapter)->acs.scan_type) == SCAN_PASSIVE) ? _TRUE : _FALSE)
+
+#define rtw_acs_get_adv_st(adapter) (GET_HAL_DATA(adapter)->acs.scan_time)
+#define rtw_is_acs_st_valid(adapter) ((GET_HAL_DATA(adapter)->acs.scan_time) ? _TRUE : _FALSE)
+
+#define rtw_acs_get_adv_igi(adapter) (GET_HAL_DATA(adapter)->acs.igi)
+u8 rtw_is_acs_igi_valid(_adapter *adapter);
+
+#define rtw_acs_get_adv_bw(adapter) (GET_HAL_DATA(adapter)->acs.bw)
+
+void rtw_acs_adv_setting(_adapter *adapter, RT_SCAN_TYPE scan_type, u16 scan_time, u8 igi, u8 bw);
+void rtw_acs_adv_reset(_adapter *adapter);
+#endif
+
+u8 rtw_acs_get_clm_ratio_by_ch_num(_adapter *adapter, u8 chan);
+u8 rtw_acs_get_clm_ratio_by_ch_idx(_adapter *adapter, u8 ch_idx);
+u8 rtw_acs_get_nhm_ratio_by_ch_num(_adapter *adapter, u8 chan);
+u8 rtw_acs_get_num_ratio_by_ch_idx(_adapter *adapter, u8 ch_idx);
+
+void rtw_acs_reset(_adapter *adapter);
+void rtw_acs_trigger(_adapter *adapter, u16 scan_time_ms, u8 scan_chan, enum NHM_PID pid);
+void rtw_acs_get_rst(_adapter *adapter);
+void rtw_acs_select_best_chan(_adapter *adapter);
+void rtw_acs_info_dump(void *sel, _adapter *adapter);
+void rtw_acs_update_current_info(_adapter *adapter);
+void rtw_acs_chan_info_dump(void *sel, _adapter *adapter);
+void rtw_acs_current_info_dump(void *sel, _adapter *adapter);
+
+void rtw_acs_start(_adapter *adapter);
+void rtw_acs_stop(_adapter *adapter);
+
+#endif /*CONFIG_RTW_ACS*/
+
+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
+#define RTK_NOISE_MONITOR_VERSION 3
+#define GET_NM_STATE(padapter) (ATOMIC_READ(&GET_HAL_DATA(padapter)->nm.state))
+#define SET_NM_STATE(padapter, set_state) (ATOMIC_SET(&GET_HAL_DATA(padapter)->nm.state, set_state))
+#define IS_NM_ENABLE(padapter) ((GET_NM_STATE(padapter) == NM_ENABLE) ? _TRUE : _FALSE)
+
+enum NM_STATE {
+ NM_DISABLE,
+ NM_ENABLE,
+};
+
+struct noise_monitor {
+ ATOMIC_T state;
+ s16 noise[MAX_CHANNEL_NUM];
+ u8 bss_nums[MAX_CHANNEL_NUM];
+};
+void rtw_nm_enable(_adapter *adapter);
+void rtw_nm_disable(_adapter *adapter);
+void rtw_noise_measure(_adapter *adapter, u8 chan, u8 is_pause_dig, u8 igi_value, u32 max_time);
+s16 rtw_noise_query_by_chan_num(_adapter *adapter, u8 chan);
+s16 rtw_noise_query_by_chan_idx(_adapter *adapter, u8 ch_idx);
+s16 rtw_noise_measure_curchan(_adapter *padapter);
+void rtw_noise_info_dump(void *sel, _adapter *adapter);
+#endif
+#endif /* __HAL_DM_ACS_H__ */
diff --git a/hal/hal_halmac.c b/hal/hal_halmac.c
index fb49134..06cdb99 100644
--- a/hal/hal_halmac.c
+++ b/hal/hal_halmac.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2015 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,21 +11,17 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#define _HAL_HALMAC_C_
#include /* PADAPTER, struct dvobj_priv, SDIO_ERR_VAL8 and etc. */
#include /* efuse, PHAL_DATA_TYPE and etc. */
-#include "halmac/halmac_api.h" /* HALMAC_FW_SIZE_MAX_88XX and etc. */
#include "hal_halmac.h" /* dvobj_to_halmac() and ect. */
#define DEFAULT_INDICATOR_TIMELMT 1000 /* ms */
-#define FIRMWARE_MAX_SIZE HALMAC_FW_SIZE_MAX_88XX
+#define MSG_PREFIX "[HALMAC]"
+
+#define RTW_HALMAC_DLFW_MEM_NO_STOP_TX
/*
* Driver API for HALMAC operations
@@ -33,6 +29,37 @@
#ifdef CONFIG_SDIO_HCI
#include
+
+static u8 _halmac_mac_reg_page0_chk(const char *func, struct dvobj_priv *dvobj, u32 offset)
+{
+#if defined(CONFIG_IO_CHECK_IN_ANA_LOW_CLK) && defined(CONFIG_LPS_LCLK)
+ struct pwrctrl_priv *pwrpriv = &dvobj->pwrctl_priv;
+ u32 mac_reg_offset = 0;
+
+ if (pwrpriv->pwr_mode == PS_MODE_ACTIVE)
+ return _TRUE;
+
+ if (pwrpriv->lps_level == LPS_NORMAL)
+ return _TRUE;
+
+ if (pwrpriv->rpwm >= PS_STATE_S2)
+ return _TRUE;
+
+ if (offset & (WLAN_IOREG_DEVICE_ID << 13)) { /*WLAN_IOREG_OFFSET*/
+ mac_reg_offset = offset & HALMAC_WLAN_MAC_REG_MSK;
+ if (mac_reg_offset < 0x100) {
+ RTW_ERR(FUNC_ADPT_FMT
+ "access MAC REG -0x%04x in PS-mode:0x%02x (rpwm:0x%02x, lps_level:0x%02x)\n",
+ FUNC_ADPT_ARG(dvobj_get_primary_adapter(dvobj)), mac_reg_offset,
+ pwrpriv->pwr_mode, pwrpriv->rpwm, pwrpriv->lps_level);
+ rtw_warn_on(1);
+ return _FALSE;
+ }
+ }
+#endif
+ return _TRUE;
+}
+
static u8 _halmac_sdio_cmd52_read(void *p, u32 offset)
{
struct dvobj_priv *d;
@@ -41,9 +68,10 @@ static u8 _halmac_sdio_cmd52_read(void *p, u32 offset)
d = (struct dvobj_priv *)p;
+ _halmac_mac_reg_page0_chk(__func__, d, offset);
ret = rtw_sdio_read_cmd52(d, offset, &val, 1);
if (_FAIL == ret) {
- RTW_INFO("%s: [ERROR] I/O FAIL!\n", __FUNCTION__);
+ RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
return SDIO_ERR_VAL8;
}
@@ -57,9 +85,10 @@ static void _halmac_sdio_cmd52_write(void *p, u32 offset, u8 val)
d = (struct dvobj_priv *)p;
+ _halmac_mac_reg_page0_chk(__func__, d, offset);
ret = rtw_sdio_write_cmd52(d, offset, &val, 1);
if (_FAIL == ret)
- RTW_INFO("%s: [ERROR] I/O FAIL!\n", __FUNCTION__);
+ RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
}
static u8 _halmac_sdio_reg_read_8(void *p, u32 offset)
@@ -67,18 +96,19 @@ static u8 _halmac_sdio_reg_read_8(void *p, u32 offset)
struct dvobj_priv *d;
u8 *pbuf;
u8 val;
- int err;
+ u8 ret;
d = (struct dvobj_priv *)p;
val = SDIO_ERR_VAL8;
+ _halmac_mac_reg_page0_chk(__func__, d, offset);
pbuf = rtw_zmalloc(1);
if (!pbuf)
return val;
- err = d->intf_ops->read(d, offset, pbuf, 1, 0);
- if (err) {
- RTW_INFO("%s: [ERROR] I/O FAIL!\n", __FUNCTION__);
+ ret = rtw_sdio_read_cmd53(d, offset, pbuf, 1);
+ if (ret == _FAIL) {
+ RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
goto exit;
}
@@ -95,18 +125,19 @@ static u16 _halmac_sdio_reg_read_16(void *p, u32 offset)
struct dvobj_priv *d;
u8 *pbuf;
u16 val;
- int err;
+ u8 ret;
d = (struct dvobj_priv *)p;
val = SDIO_ERR_VAL16;
+ _halmac_mac_reg_page0_chk(__func__, d, offset);
pbuf = rtw_zmalloc(2);
if (!pbuf)
return val;
- err = d->intf_ops->read(d, offset, pbuf, 2, 0);
- if (err) {
- RTW_INFO("%s: [ERROR] I/O FAIL!\n", __FUNCTION__);
+ ret = rtw_sdio_read_cmd53(d, offset, pbuf, 2);
+ if (ret == _FAIL) {
+ RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
goto exit;
}
@@ -123,18 +154,19 @@ static u32 _halmac_sdio_reg_read_32(void *p, u32 offset)
struct dvobj_priv *d;
u8 *pbuf;
u32 val;
- int err;
+ u8 ret;
d = (struct dvobj_priv *)p;
val = SDIO_ERR_VAL32;
+ _halmac_mac_reg_page0_chk(__func__, d, offset);
pbuf = rtw_zmalloc(4);
if (!pbuf)
return val;
- err = d->intf_ops->read(d, offset, pbuf, 4, 0);
- if (err) {
- RTW_INFO("%s: [ERROR] I/O FAIL!\n", __FUNCTION__);
+ ret = rtw_sdio_read_cmd53(d, offset, pbuf, 4);
+ if (ret == _FAIL) {
+ RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
goto exit;
}
@@ -146,22 +178,53 @@ static u32 _halmac_sdio_reg_read_32(void *p, u32 offset)
return val;
}
+static u8 _halmac_sdio_reg_read_n(void *p, u32 offset, u32 size, u8 *data)
+{
+ struct dvobj_priv *d = (struct dvobj_priv *)p;
+ u8 *pbuf;
+ u8 ret;
+ u8 rst = _FALSE;
+ u32 sdio_read_size;
+
+
+ sdio_read_size = RND4(size);
+ sdio_read_size = rtw_sdio_cmd53_align_size(d, sdio_read_size);
+
+ pbuf = rtw_zmalloc(sdio_read_size);
+ if ((!pbuf) || (!data))
+ return rst;
+
+ ret = rtw_sdio_read_cmd53(d, offset, pbuf, sdio_read_size);
+ if (ret == _FAIL) {
+ RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
+ goto exit;
+ }
+
+ _rtw_memcpy(data, pbuf, size);
+ rst = _TRUE;
+exit:
+ rtw_mfree(pbuf, sdio_read_size);
+
+ return rst;
+}
+
static void _halmac_sdio_reg_write_8(void *p, u32 offset, u8 val)
{
struct dvobj_priv *d;
u8 *pbuf;
- int err;
+ u8 ret;
d = (struct dvobj_priv *)p;
+ _halmac_mac_reg_page0_chk(__func__, d, offset);
pbuf = rtw_zmalloc(1);
if (!pbuf)
return;
_rtw_memcpy(pbuf, &val, 1);
- err = d->intf_ops->write(d, offset, pbuf, 1, 0);
- if (err)
- RTW_INFO("%s: [ERROR] I/O FAIL!\n", __FUNCTION__);
+ ret = rtw_sdio_write_cmd53(d, offset, pbuf, 1);
+ if (ret == _FAIL)
+ RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
rtw_mfree(pbuf, 1);
}
@@ -170,19 +233,20 @@ static void _halmac_sdio_reg_write_16(void *p, u32 offset, u16 val)
{
struct dvobj_priv *d;
u8 *pbuf;
- int err;
+ u8 ret;
d = (struct dvobj_priv *)p;
+ _halmac_mac_reg_page0_chk(__func__, d, offset);
val = cpu_to_le16(val);
pbuf = rtw_zmalloc(2);
if (!pbuf)
return;
_rtw_memcpy(pbuf, &val, 2);
- err = d->intf_ops->write(d, offset, pbuf, 2, 0);
- if (err)
- RTW_INFO("%s: [ERROR] I/O FAIL!\n", __FUNCTION__);
+ ret = rtw_sdio_write_cmd53(d, offset, pbuf, 2);
+ if (ret == _FAIL)
+ RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
rtw_mfree(pbuf, 2);
}
@@ -191,23 +255,40 @@ static void _halmac_sdio_reg_write_32(void *p, u32 offset, u32 val)
{
struct dvobj_priv *d;
u8 *pbuf;
- int err;
+ u8 ret;
d = (struct dvobj_priv *)p;
+ _halmac_mac_reg_page0_chk(__func__, d, offset);
val = cpu_to_le32(val);
pbuf = rtw_zmalloc(4);
if (!pbuf)
return;
_rtw_memcpy(pbuf, &val, 4);
- err = d->intf_ops->write(d, offset, pbuf, 4, 0);
- if (err)
- RTW_INFO("%s: [ERROR] I/O FAIL!\n", __FUNCTION__);
+ ret = rtw_sdio_write_cmd53(d, offset, pbuf, 4);
+ if (ret == _FAIL)
+ RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
rtw_mfree(pbuf, 4);
}
+static u8 _halmac_sdio_read_cia(void *p, u32 offset)
+{
+ struct dvobj_priv *d;
+ u8 data = 0;
+ u8 ret;
+
+
+ d = (struct dvobj_priv *)p;
+
+ ret = rtw_sdio_f0_read(d, offset, &data, 1);
+ if (ret == _FAIL)
+ RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
+
+ return data;
+}
+
#else /* !CONFIG_SDIO_HCI */
static u8 _halmac_reg_read_8(void *p, u32 offset)
@@ -217,7 +298,7 @@ static u8 _halmac_reg_read_8(void *p, u32 offset)
d = (struct dvobj_priv *)p;
- adapter = d->padapters[IFACE_ID0];
+ adapter = dvobj_get_primary_adapter(d);
return rtw_read8(adapter, offset);
}
@@ -229,7 +310,7 @@ static u16 _halmac_reg_read_16(void *p, u32 offset)
d = (struct dvobj_priv *)p;
- adapter = d->padapters[IFACE_ID0];
+ adapter = dvobj_get_primary_adapter(d);
return rtw_read16(adapter, offset);
}
@@ -241,7 +322,7 @@ static u32 _halmac_reg_read_32(void *p, u32 offset)
d = (struct dvobj_priv *)p;
- adapter = d->padapters[IFACE_ID0];
+ adapter = dvobj_get_primary_adapter(d);
return rtw_read32(adapter, offset);
}
@@ -254,11 +335,11 @@ static void _halmac_reg_write_8(void *p, u32 offset, u8 val)
d = (struct dvobj_priv *)p;
- adapter = d->padapters[IFACE_ID0];
+ adapter = dvobj_get_primary_adapter(d);
err = rtw_write8(adapter, offset, val);
if (err == _FAIL)
- RTW_INFO("%s: [ERROR] I/O FAIL!\n", __FUNCTION__);
+ RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
}
static void _halmac_reg_write_16(void *p, u32 offset, u16 val)
@@ -269,11 +350,11 @@ static void _halmac_reg_write_16(void *p, u32 offset, u16 val)
d = (struct dvobj_priv *)p;
- adapter = d->padapters[IFACE_ID0];
+ adapter = dvobj_get_primary_adapter(d);
err = rtw_write16(adapter, offset, val);
if (err == _FAIL)
- RTW_INFO("%s: [ERROR] I/O FAIL!\n", __FUNCTION__);
+ RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
}
static void _halmac_reg_write_32(void *p, u32 offset, u32 val)
@@ -284,11 +365,11 @@ static void _halmac_reg_write_32(void *p, u32 offset, u32 val)
d = (struct dvobj_priv *)p;
- adapter = d->padapters[IFACE_ID0];
+ adapter = dvobj_get_primary_adapter(d);
err = rtw_write32(adapter, offset, val);
if (err == _FAIL)
- RTW_INFO("%s: [ERROR] I/O FAIL!\n", __FUNCTION__);
+ RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__);
}
#endif /* !CONFIG_SDIO_HCI */
@@ -317,7 +398,13 @@ static u8 _halmac_memset(void *p, void *addr, u8 value, u32 size)
static void _halmac_udelay(void *p, u32 us)
{
- rtw_udelay_os(us);
+ /* Most hardware polling wait time < 50us) */
+ if (us <= 50)
+ rtw_udelay_os(us);
+ else if (us <= 1000)
+ rtw_usleep_os(us);
+ else
+ rtw_msleep_os(RTW_DIV_ROUND_UP(us, 1000));
}
static u8 _halmac_mutex_init(void *p, HALMAC_MUTEX *pMutex)
@@ -352,41 +439,47 @@ static u8 _halmac_mutex_unlock(void *p, HALMAC_MUTEX *pMutex)
static u8 _halmac_msg_print(void *p, u32 msg_type, u8 msg_level, s8 *fmt, ...)
{
#define MSG_LEN 100
-#define MSG_PREFIX "[HALMAC]"
va_list args;
u8 str[MSG_LEN] = {0};
- u32 type;
- u8 level;
+ int err;
+ u8 ret = _TRUE;
str[0] = '\n';
- type = 0xFFFFFFFF;
- if (rtw_drv_log_level <= _DRV_ERR_)
- level = HALMAC_DBG_ERR;
- else if (rtw_drv_log_level <= _DRV_INFO_)
- level = HALMAC_DBG_WARN;
- else
- level = HALMAC_DBG_TRACE;
-
- if (!(type & BIT(msg_type)))
- return _TRUE;
- if (level < msg_level)
- return _TRUE;
-
va_start(args, fmt);
- vsnprintf(str, MSG_LEN, fmt, args);
+ err = vsnprintf(str, MSG_LEN, fmt, args);
va_end(args);
- if (msg_level <= HALMAC_DBG_ERR)
+ /* An output error is encountered */
+ if (err < 0)
+ return _FALSE;
+ /* Output may be truncated due to size limit */
+ if ((err == (MSG_LEN - 1)) && (str[MSG_LEN - 2] != '\n'))
+ ret = _FALSE;
+
+ if (msg_level == HALMAC_DBG_ALWAYS)
+ RTW_PRINT(MSG_PREFIX "%s", str);
+ else if (msg_level <= HALMAC_DBG_ERR)
RTW_ERR(MSG_PREFIX "%s", str);
else if (msg_level <= HALMAC_DBG_WARN)
RTW_WARN(MSG_PREFIX "%s", str);
else
RTW_DBG(MSG_PREFIX "%s", str);
+ return ret;
+}
+
+static u8 _halmac_buff_print(void *p, u32 msg_type, u8 msg_level, s8 *buf, u32 size)
+{
+ if (msg_level <= HALMAC_DBG_WARN)
+ RTW_INFO_DUMP(MSG_PREFIX, buf, size);
+ else
+ RTW_DBG_DUMP(MSG_PREFIX, buf, size);
+
return _TRUE;
}
+
const char *const RTW_HALMAC_FEATURE_NAME[] = {
"HALMAC_FEATURE_CFG_PARA",
"HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE",
@@ -398,28 +491,27 @@ const char *const RTW_HALMAC_FEATURE_NAME[] = {
"HALMAC_FEATURE_IQK",
"HALMAC_FEATURE_POWER_TRACKING",
"HALMAC_FEATURE_PSD",
+ "HALMAC_FEATURE_FW_SNDING",
"HALMAC_FEATURE_ALL"
};
-static inline u8 is_valid_id_status(HALMAC_FEATURE_ID id, HALMAC_CMD_PROCESS_STATUS status)
+static inline u8 is_valid_id_status(enum halmac_feature_id id, enum halmac_cmd_process_status status)
{
switch (id) {
case HALMAC_FEATURE_CFG_PARA:
- RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
+ RTW_DBG("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
break;
case HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE:
RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
- if (HALMAC_CMD_PROCESS_DONE != status) {
- RTW_INFO("%s: id(%d) unspecified status(%d)!\n",
+ if (HALMAC_CMD_PROCESS_DONE != status)
+ RTW_INFO("%s: id(%d) unspecified status(%d)!\n",
__FUNCTION__, id, status);
- }
break;
case HALMAC_FEATURE_DUMP_LOGICAL_EFUSE:
RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
- if (HALMAC_CMD_PROCESS_DONE != status) {
- RTW_INFO("%s: id(%d) unspecified status(%d)!\n",
+ if (HALMAC_CMD_PROCESS_DONE != status)
+ RTW_INFO("%s: id(%d) unspecified status(%d)!\n",
__FUNCTION__, id, status);
- }
break;
case HALMAC_FEATURE_UPDATE_PACKET:
RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
@@ -442,18 +534,21 @@ static inline u8 is_valid_id_status(HALMAC_FEATURE_ID id, HALMAC_CMD_PROCESS_STA
case HALMAC_FEATURE_PSD:
RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
break;
+ case HALMAC_FEATURE_FW_SNDING:
+ RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
+ break;
case HALMAC_FEATURE_ALL:
RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]);
break;
default:
- RTW_INFO("%s: unknown feature id(%d)\n", __FUNCTION__, id);
+ RTW_ERR("%s: unknown feature id(%d)\n", __FUNCTION__, id);
return _FALSE;
}
return _TRUE;
}
-static int init_halmac_event_with_waittime(struct dvobj_priv *d, HALMAC_FEATURE_ID id, u8 *buf, u32 size, u32 time)
+static int init_halmac_event_with_waittime(struct dvobj_priv *d, enum halmac_feature_id id, u8 *buf, u32 size, u32 time)
{
struct submit_ctx *sctx;
@@ -463,7 +558,7 @@ static int init_halmac_event_with_waittime(struct dvobj_priv *d, HALMAC_FEATURE_
if (!sctx)
return -1;
} else {
- RTW_INFO("%s: id(%d) sctx is not NULL!!\n", __FUNCTION__, id);
+ RTW_WARN("%s: id(%d) sctx is not NULL!!\n", __FUNCTION__, id);
sctx = d->hmpriv.indicator[id].sctx;
d->hmpriv.indicator[id].sctx = NULL;
}
@@ -479,12 +574,12 @@ static int init_halmac_event_with_waittime(struct dvobj_priv *d, HALMAC_FEATURE_
return 0;
}
-static inline int init_halmac_event(struct dvobj_priv *d, HALMAC_FEATURE_ID id, u8 *buf, u32 size)
+static inline int init_halmac_event(struct dvobj_priv *d, enum halmac_feature_id id, u8 *buf, u32 size)
{
return init_halmac_event_with_waittime(d, id, buf, size, DEFAULT_INDICATOR_TIMELMT);
}
-static void free_halmac_event(struct dvobj_priv *d, HALMAC_FEATURE_ID id)
+static void free_halmac_event(struct dvobj_priv *d, enum halmac_feature_id id)
{
struct submit_ctx *sctx;
@@ -497,8 +592,10 @@ static void free_halmac_event(struct dvobj_priv *d, HALMAC_FEATURE_ID id)
rtw_mfree((u8 *)sctx, sizeof(*sctx));
}
-static int wait_halmac_event(struct dvobj_priv *d, HALMAC_FEATURE_ID id)
+static int wait_halmac_event(struct dvobj_priv *d, enum halmac_feature_id id)
{
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
struct submit_ctx *sctx;
int ret;
@@ -512,6 +609,13 @@ static int wait_halmac_event(struct dvobj_priv *d, HALMAC_FEATURE_ID id)
if (_SUCCESS == ret)
return 0;
+ /* timeout! We have to reset halmac state */
+ RTW_ERR("%s: Wait id(%d, %s) TIMEOUT! Reset HALMAC state!\n",
+ __FUNCTION__, id, RTW_HALMAC_FEATURE_NAME[id]);
+ mac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(mac);
+ api->halmac_reset_feature(mac, id);
+
return -1;
}
@@ -519,7 +623,7 @@ static int wait_halmac_event(struct dvobj_priv *d, HALMAC_FEATURE_ID id)
* Return:
* Always return _TRUE, HALMAC don't care the return value.
*/
-static u8 _halmac_event_indication(void *p, HALMAC_FEATURE_ID feature_id, HALMAC_CMD_PROCESS_STATUS process_status, u8 *buf, u32 size)
+static u8 _halmac_event_indication(void *p, enum halmac_feature_id feature_id, enum halmac_cmd_process_status process_status, u8 *buf, u32 size)
{
struct dvobj_priv *d;
PADAPTER adapter;
@@ -531,10 +635,11 @@ static u8 _halmac_event_indication(void *p, HALMAC_FEATURE_ID feature_id, HALMAC
d = (struct dvobj_priv *)p;
- adapter = d->padapters[IFACE_ID0];
+ adapter = dvobj_get_primary_adapter(d);
hal = GET_HAL_DATA(adapter);
tbl = d->hmpriv.indicator;
+ /* Filter(Skip) middle status indication */
ret = is_valid_id_status(feature_id, process_status);
if (_FALSE == ret)
goto exit;
@@ -543,23 +648,24 @@ static u8 _halmac_event_indication(void *p, HALMAC_FEATURE_ID feature_id, HALMAC
indicator->status = process_status;
indicator->ret_size = size;
if (!indicator->sctx) {
- RTW_INFO("%s: No feature id(%d) waiting!!\n", __FUNCTION__, feature_id);
+ RTW_WARN("%s: No feature id(%d, %s) waiting!!\n", __FUNCTION__, feature_id, RTW_HALMAC_FEATURE_NAME[feature_id]);
goto exit;
}
sctx = indicator->sctx;
if (HALMAC_CMD_PROCESS_ERROR == process_status) {
- RTW_INFO("%s: Something wrong id(%d)!!\n", __FUNCTION__, feature_id);
+ RTW_ERR("%s: Something wrong id(%d, %s)!!\n", __FUNCTION__, feature_id, RTW_HALMAC_FEATURE_NAME[feature_id]);
rtw_sctx_done_err(&sctx, RTW_SCTX_DONE_UNKNOWN);
goto exit;
}
if (size > indicator->buf_size) {
- RTW_INFO("%s: id(%d) buffer is not enough(%d<%d), data will be truncated!\n",
- __FUNCTION__, feature_id, indicator->buf_size, size);
+ RTW_WARN("%s: id(%d, %s) buffer is not enough(%d<%d), data will be truncated!\n",
+ __FUNCTION__, feature_id, RTW_HALMAC_FEATURE_NAME[feature_id], indicator->buf_size, size);
cpsz = indicator->buf_size;
- } else
+ } else {
cpsz = size;
+ }
if (cpsz && indicator->buffer)
_rtw_memcpy(indicator->buffer, buf, cpsz);
@@ -569,17 +675,19 @@ static u8 _halmac_event_indication(void *p, HALMAC_FEATURE_ID feature_id, HALMAC
return _TRUE;
}
-HALMAC_PLATFORM_API rtw_halmac_platform_api = {
+struct halmac_platform_api rtw_halmac_platform_api = {
/* R/W register */
#ifdef CONFIG_SDIO_HCI
.SDIO_CMD52_READ = _halmac_sdio_cmd52_read,
.SDIO_CMD53_READ_8 = _halmac_sdio_reg_read_8,
.SDIO_CMD53_READ_16 = _halmac_sdio_reg_read_16,
.SDIO_CMD53_READ_32 = _halmac_sdio_reg_read_32,
+ .SDIO_CMD53_READ_N = _halmac_sdio_reg_read_n,
.SDIO_CMD52_WRITE = _halmac_sdio_cmd52_write,
.SDIO_CMD53_WRITE_8 = _halmac_sdio_reg_write_8,
.SDIO_CMD53_WRITE_16 = _halmac_sdio_reg_write_16,
.SDIO_CMD53_WRITE_32 = _halmac_sdio_reg_write_32,
+ .SDIO_CMD52_CIA_READ = _halmac_sdio_read_cia,
#endif /* CONFIG_SDIO_HCI */
#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCIE_HCI)
.REG_READ_8 = _halmac_reg_read_8,
@@ -612,13 +720,14 @@ HALMAC_PLATFORM_API rtw_halmac_platform_api = {
.MUTEX_UNLOCK = _halmac_mutex_unlock,
.MSG_PRINT = _halmac_msg_print,
+ .BUFF_PRINT = _halmac_buff_print,
.EVENT_INDICATION = _halmac_event_indication,
};
u8 rtw_halmac_read8(struct intf_hdl *pintfhdl, u32 addr)
{
- PHALMAC_ADAPTER mac;
- PHALMAC_API api;
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
/* WARNING: pintf_dev should not be null! */
@@ -630,8 +739,8 @@ u8 rtw_halmac_read8(struct intf_hdl *pintfhdl, u32 addr)
u16 rtw_halmac_read16(struct intf_hdl *pintfhdl, u32 addr)
{
- PHALMAC_ADAPTER mac;
- PHALMAC_API api;
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
/* WARNING: pintf_dev should not be null! */
@@ -643,8 +752,8 @@ u16 rtw_halmac_read16(struct intf_hdl *pintfhdl, u32 addr)
u32 rtw_halmac_read32(struct intf_hdl *pintfhdl, u32 addr)
{
- PHALMAC_ADAPTER mac;
- PHALMAC_API api;
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
/* WARNING: pintf_dev should not be null! */
@@ -654,11 +763,161 @@ u32 rtw_halmac_read32(struct intf_hdl *pintfhdl, u32 addr)
return api->halmac_reg_read_32(mac, addr);
}
+static void _read_register(struct dvobj_priv *d, u32 addr, u32 cnt, u8 *buf)
+{
+#if 1
+ struct _ADAPTER *a;
+ u32 i, n;
+ u16 val16;
+ u32 val32;
+
+
+ a = dvobj_get_primary_adapter(d);
+
+ i = addr & 0x3;
+ /* Handle address not start from 4 bytes alignment case */
+ if (i) {
+ val32 = cpu_to_le32(rtw_read32(a, addr & ~0x3));
+ n = 4 - i;
+ _rtw_memcpy(buf, ((u8 *)&val32) + i, n);
+ i = n;
+ cnt -= n;
+ }
+
+ while (cnt) {
+ if (cnt >= 4)
+ n = 4;
+ else if (cnt >= 2)
+ n = 2;
+ else
+ n = 1;
+ cnt -= n;
+
+ switch (n) {
+ case 1:
+ buf[i] = rtw_read8(a, addr+i);
+ i++;
+ break;
+ case 2:
+ val16 = cpu_to_le16(rtw_read16(a, addr+i));
+ _rtw_memcpy(&buf[i], &val16, 2);
+ i += 2;
+ break;
+ case 4:
+ val32 = cpu_to_le32(rtw_read32(a, addr+i));
+ _rtw_memcpy(&buf[i], &val32, 4);
+ i += 4;
+ break;
+ }
+ }
+#else
+ struct _ADAPTER *a;
+ u32 i;
+
+
+ a = dvobj_get_primary_adapter(d);
+ for (i = 0; i < cnt; i++)
+ buf[i] = rtw_read8(a, addr + i);
+#endif
+}
+
+#ifdef CONFIG_SDIO_HCI
+static int _sdio_read_local(struct dvobj_priv *d, u32 addr, u32 cnt, u8 *buf)
+{
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
+
+
+ if (buf == NULL)
+ return -1;
+
+ mac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(mac);
+
+ status = api->halmac_reg_sdio_cmd53_read_n(mac, addr, cnt, buf);
+ if (status != HALMAC_RET_SUCCESS) {
+ RTW_ERR("%s: addr=0x%08x cnt=%d err=%d\n",
+ __FUNCTION__, addr, cnt, status);
+ return -1;
+ }
+
+ return 0;
+}
+#endif /* CONFIG_SDIO_HCI */
+
+void rtw_halmac_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem)
+{
+ struct dvobj_priv *d;
+
+
+ if (pmem == NULL) {
+ RTW_ERR("pmem is NULL\n");
+ return;
+ }
+
+ d = pintfhdl->pintf_dev;
+
+#ifdef CONFIG_SDIO_HCI
+ if (addr & 0xFFFF0000) {
+ int err = 0;
+
+ err = _sdio_read_local(d, addr, cnt, pmem);
+ if (!err)
+ return;
+ }
+#endif /* CONFIG_SDIO_HCI */
+
+ _read_register(d, addr, cnt, pmem);
+}
+
+#ifdef CONFIG_SDIO_INDIRECT_ACCESS
+u8 rtw_halmac_iread8(struct intf_hdl *pintfhdl, u32 addr)
+{
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+
+ /* WARNING: pintf_dev should not be null! */
+ mac = dvobj_to_halmac(pintfhdl->pintf_dev);
+ api = HALMAC_GET_API(mac);
+
+ /*return api->halmac_reg_read_indirect_8(mac, addr);*/
+ return api->halmac_reg_read_8(mac, addr);
+}
+
+u16 rtw_halmac_iread16(struct intf_hdl *pintfhdl, u32 addr)
+{
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ u16 val16 = 0;
+
+ /* WARNING: pintf_dev should not be null! */
+ mac = dvobj_to_halmac(pintfhdl->pintf_dev);
+ api = HALMAC_GET_API(mac);
+
+ /*return api->halmac_reg_read_indirect_16(mac, addr);*/
+ return api->halmac_reg_read_16(mac, addr);
+}
+
+u32 rtw_halmac_iread32(struct intf_hdl *pintfhdl, u32 addr)
+{
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+
+
+ /* WARNING: pintf_dev should not be null! */
+ mac = dvobj_to_halmac(pintfhdl->pintf_dev);
+ api = HALMAC_GET_API(mac);
+
+ return api->halmac_reg_read_indirect_32(mac, addr);
+}
+#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
+
int rtw_halmac_write8(struct intf_hdl *pintfhdl, u32 addr, u8 value)
{
- PHALMAC_ADAPTER mac;
- PHALMAC_API api;
- HALMAC_RET_STATUS status;
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
/* WARNING: pintf_dev should not be null! */
@@ -675,9 +934,9 @@ int rtw_halmac_write8(struct intf_hdl *pintfhdl, u32 addr, u8 value)
int rtw_halmac_write16(struct intf_hdl *pintfhdl, u32 addr, u16 value)
{
- PHALMAC_ADAPTER mac;
- PHALMAC_API api;
- HALMAC_RET_STATUS status;
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
/* WARNING: pintf_dev should not be null! */
@@ -694,9 +953,9 @@ int rtw_halmac_write16(struct intf_hdl *pintfhdl, u32 addr, u16 value)
int rtw_halmac_write32(struct intf_hdl *pintfhdl, u32 addr, u32 value)
{
- PHALMAC_ADAPTER mac;
- PHALMAC_API api;
- HALMAC_RET_STATUS status;
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
/* WARNING: pintf_dev should not be null! */
@@ -711,15 +970,58 @@ int rtw_halmac_write32(struct intf_hdl *pintfhdl, u32 addr, u32 value)
return -1;
}
+static int init_write_rsvd_page_size(struct dvobj_priv *d)
+{
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ u32 size = 0;
+ struct halmac_ofld_func_info ofld_info;
+ enum halmac_ret_status status;
+ int err = 0;
+
+
+#ifdef CONFIG_USB_HCI
+ /* for USB do not exceed MAX_CMDBUF_SZ */
+ size = 0x1000;
+#elif defined(CONFIG_PCIE_HCI)
+ size = MAX_CMDBUF_SZ - TXDESC_OFFSET;
+#elif defined(CONFIG_SDIO_HCI)
+ size = 0x7000; /* 28KB */
+#endif
+
+ /* If size==0, use HALMAC default setting and don't call any function */
+ if (!size)
+ return 0;
+
+ err = rtw_halmac_set_max_dl_fw_size(d, size);
+ if (err) {
+ RTW_ERR("%s: Fail to set max download fw size!\n", __FUNCTION__);
+ return -1;
+ }
+
+ mac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(mac);
+
+ _rtw_memset(&ofld_info, 0, sizeof(ofld_info));
+ ofld_info.halmac_malloc_max_sz = 0xFFFFFFFF;
+ ofld_info.rsvd_pg_drv_buf_max_sz = size;
+ status = api->halmac_ofld_func_cfg(mac, &ofld_info);
+ if (status != HALMAC_RET_SUCCESS) {
+ RTW_ERR("%s: Fail to config offload parameters!\n", __FUNCTION__);
+ return -1;
+ }
+
+ return 0;
+}
+
static int init_priv(struct halmacpriv *priv)
{
struct halmac_indicator *indicator;
u32 count, size;
- size = sizeof(*priv);
- _rtw_memset(priv, 0, size);
-
+ if (priv->indicator)
+ RTW_WARN("%s: HALMAC private data is not CLEAR!\n", __FUNCTION__);
count = HALMAC_FEATURE_ALL + 1;
size = sizeof(*indicator) * count;
indicator = (struct halmac_indicator *)rtw_zmalloc(size);
@@ -750,7 +1052,7 @@ static void deinit_priv(struct halmacpriv *priv)
if (!indicator[i].sctx)
continue;
- RTW_INFO("%s: %s id(%d) sctx still exist!!\n",
+ RTW_WARN("%s: %s id(%d) sctx still exist!!\n",
__FUNCTION__, RTW_HALMAC_FEATURE_NAME[i], i);
sctx = indicator[i].sctx;
indicator[i].sctx = NULL;
@@ -763,24 +1065,58 @@ static void deinit_priv(struct halmacpriv *priv)
}
}
-int rtw_halmac_init_adapter(struct dvobj_priv *d, PHALMAC_PLATFORM_API pf_api)
+#ifdef CONFIG_SDIO_HCI
+static enum halmac_sdio_spec_ver _sdio_ver_drv2halmac(struct dvobj_priv *d)
+{
+ bool v3;
+ enum halmac_sdio_spec_ver ver;
+
+
+ v3 = rtw_is_sdio30(dvobj_get_primary_adapter(d));
+ if (v3)
+ ver = HALMAC_SDIO_SPEC_VER_3_00;
+ else
+ ver = HALMAC_SDIO_SPEC_VER_2_00;
+
+ return ver;
+}
+#endif /* CONFIG_SDIO_HCI */
+
+void rtw_halmac_get_version(char *str, u32 len)
+{
+ enum halmac_ret_status status;
+ struct halmac_ver ver;
+
+
+ status = halmac_get_version(&ver);
+ if (status != HALMAC_RET_SUCCESS)
+ return;
+
+ rtw_sprintf(str, len, "V%d_%02d_%02d",
+ ver.major_ver, ver.prototype_ver, ver.minor_ver);
+}
+
+int rtw_halmac_init_adapter(struct dvobj_priv *d, struct halmac_platform_api *pf_api)
{
- PHALMAC_ADAPTER halmac;
- PHALMAC_API api;
- HALMAC_INTERFACE intf;
- HALMAC_RET_STATUS status;
+ struct halmac_adapter *halmac;
+ struct halmac_api *api;
+ enum halmac_interface intf;
+ enum halmac_ret_status status;
int err = 0;
+#ifdef CONFIG_SDIO_HCI
+ struct halmac_sdio_hw_info info;
+#endif /* CONFIG_SDIO_HCI */
halmac = dvobj_to_halmac(d);
if (halmac) {
- err = 0;
- goto out;
+ RTW_WARN("%s: initialize already completed!\n", __FUNCTION__);
+ goto error;
}
err = init_priv(&d->hmpriv);
if (err)
- goto out;
+ goto error;
#ifdef CONFIG_SDIO_HCI
intf = HALMAC_INTERFACE_SDIO;
@@ -794,141 +1130,1955 @@ int rtw_halmac_init_adapter(struct dvobj_priv *d, PHALMAC_PLATFORM_API pf_api)
#endif
status = halmac_init_adapter(d, pf_api, intf, &halmac, &api);
if (HALMAC_RET_SUCCESS != status) {
- RTW_INFO("%s: halmac_init_adapter fail!(status=%d)\n", __FUNCTION__, status);
+ RTW_ERR("%s: halmac_init_adapter fail!(status=%d)\n", __FUNCTION__, status);
err = -1;
- goto out;
+ if (halmac)
+ goto deinit;
+ goto free;
}
dvobj_set_halmac(d, halmac);
-out:
- if (err)
- rtw_halmac_deinit_adapter(d);
+ status = api->halmac_interface_integration_tuning(halmac);
+ if (status != HALMAC_RET_SUCCESS) {
+ RTW_ERR("%s: halmac_interface_integration_tuning fail!(status=%d)\n", __FUNCTION__, status);
+ err = -1;
+ goto deinit;
+ }
+
+ status = api->halmac_phy_cfg(halmac, HALMAC_INTF_PHY_PLATFORM_ALL);
+ if (status != HALMAC_RET_SUCCESS) {
+ RTW_ERR("%s: halmac_phy_cfg fail!(status=%d)\n", __FUNCTION__, status);
+ err = -1;
+ goto deinit;
+ }
+
+ init_write_rsvd_page_size(d);
+
+#ifdef CONFIG_SDIO_HCI
+ _rtw_memset(&info, 0, sizeof(info));
+ info.spec_ver = _sdio_ver_drv2halmac(d);
+ /* Convert clock speed unit to MHz from Hz */
+ info.clock_speed = RTW_DIV_ROUND_UP(rtw_sdio_get_clock(d), 1000000);
+ info.block_size = rtw_sdio_get_block_size(d);
+ RTW_DBG("%s: SDIO ver=%u clock=%uMHz blk_size=%u bytes\n",
+ __FUNCTION__, info.spec_ver+2, info.clock_speed,
+ info.block_size);
+ status = api->halmac_sdio_hw_info(halmac, &info);
+ if (status != HALMAC_RET_SUCCESS) {
+ RTW_ERR("%s: halmac_sdio_hw_info fail!(status=%d)\n",
+ __FUNCTION__, status);
+ err = -1;
+ goto deinit;
+ }
+#endif /* CONFIG_SDIO_HCI */
+
+ return 0;
+
+deinit:
+ status = halmac_deinit_adapter(halmac);
+ dvobj_set_halmac(d, NULL);
+ if (status != HALMAC_RET_SUCCESS)
+ RTW_ERR("%s: halmac_deinit_adapter fail!(status=%d)\n",
+ __FUNCTION__, status);
+
+free:
+ deinit_priv(&d->hmpriv);
+error:
return err;
}
int rtw_halmac_deinit_adapter(struct dvobj_priv *d)
{
- PHALMAC_ADAPTER halmac;
- HALMAC_RET_STATUS status;
+ struct halmac_adapter *halmac;
+ enum halmac_ret_status status;
int err = 0;
halmac = dvobj_to_halmac(d);
- if (!halmac) {
- err = 0;
- goto out;
+ if (halmac) {
+ status = halmac_deinit_adapter(halmac);
+ dvobj_set_halmac(d, NULL);
+ if (status != HALMAC_RET_SUCCESS)
+ err = -1;
}
deinit_priv(&d->hmpriv);
- status = halmac_deinit_adapter(halmac);
- dvobj_set_halmac(d, NULL);
- if (status != HALMAC_RET_SUCCESS) {
- err = -1;
- goto out;
- }
-
-out:
return err;
}
-int rtw_halmac_poweron(struct dvobj_priv *d)
+static inline enum halmac_portid _hw_port_drv2halmac(enum _hw_port hwport)
{
- PHALMAC_ADAPTER halmac;
- PHALMAC_API api;
- HALMAC_RET_STATUS status;
- int err = -1;
-
+ enum halmac_portid port = HALMAC_PORTID_NUM;
- halmac = dvobj_to_halmac(d);
- if (!halmac)
- goto out;
-
- api = HALMAC_GET_API(halmac);
- status = api->halmac_pre_init_system_cfg(halmac);
- if (status != HALMAC_RET_SUCCESS)
- goto out;
+ switch (hwport) {
+ case HW_PORT0:
+ port = HALMAC_PORTID0;
+ break;
+ case HW_PORT1:
+ port = HALMAC_PORTID1;
+ break;
+ case HW_PORT2:
+ port = HALMAC_PORTID2;
+ break;
+ case HW_PORT3:
+ port = HALMAC_PORTID3;
+ break;
+ case HW_PORT4:
+ port = HALMAC_PORTID4;
+ break;
+ default:
+ break;
+ }
+
+ return port;
+}
+
+static enum halmac_network_type_select _network_type_drv2halmac(u8 type)
+{
+ enum halmac_network_type_select network = HALMAC_NETWORK_UNDEFINE;
+
+
+ switch (type) {
+ case _HW_STATE_NOLINK_:
+ case _HW_STATE_MONITOR_:
+ network = HALMAC_NETWORK_NO_LINK;
+ break;
+
+ case _HW_STATE_ADHOC_:
+ network = HALMAC_NETWORK_ADHOC;
+ break;
+
+ case _HW_STATE_STATION_:
+ network = HALMAC_NETWORK_INFRASTRUCTURE;
+ break;
+
+ case _HW_STATE_AP_:
+ network = HALMAC_NETWORK_AP;
+ break;
+ }
+
+ return network;
+}
+
+static u8 _network_type_halmac2drv(enum halmac_network_type_select network)
+{
+ u8 type = _HW_STATE_NOLINK_;
+
+
+ switch (network) {
+ case HALMAC_NETWORK_NO_LINK:
+ case HALMAC_NETWORK_UNDEFINE:
+ type = _HW_STATE_NOLINK_;
+ break;
+
+ case HALMAC_NETWORK_ADHOC:
+ type = _HW_STATE_ADHOC_;
+ break;
+
+ case HALMAC_NETWORK_INFRASTRUCTURE:
+ type = _HW_STATE_STATION_;
+ break;
+
+ case HALMAC_NETWORK_AP:
+ type = _HW_STATE_AP_;
+ break;
+ }
+
+ return type;
+}
+
+static void _beacon_ctrl_halmac2drv(struct halmac_bcn_ctrl *ctrl,
+ struct rtw_halmac_bcn_ctrl *drv_ctrl)
+{
+ drv_ctrl->rx_bssid_fit = ctrl->dis_rx_bssid_fit ? 0 : 1;
+ drv_ctrl->txbcn_rpt = ctrl->en_txbcn_rpt ? 1 : 0;
+ drv_ctrl->tsf_update = ctrl->dis_tsf_udt ? 0 : 1;
+ drv_ctrl->enable_bcn = ctrl->en_bcn ? 1 : 0;
+ drv_ctrl->rxbcn_rpt = ctrl->en_rxbcn_rpt ? 1 : 0;
+ drv_ctrl->p2p_ctwin = ctrl->en_p2p_ctwin ? 1 : 0;
+ drv_ctrl->p2p_bcn_area = ctrl->en_p2p_bcn_area ? 1 : 0;
+}
+
+static void _beacon_ctrl_drv2halmac(struct rtw_halmac_bcn_ctrl *drv_ctrl,
+ struct halmac_bcn_ctrl *ctrl)
+{
+ ctrl->dis_rx_bssid_fit = drv_ctrl->rx_bssid_fit ? 0 : 1;
+ ctrl->en_txbcn_rpt = drv_ctrl->txbcn_rpt ? 1 : 0;
+ ctrl->dis_tsf_udt = drv_ctrl->tsf_update ? 0 : 1;
+ ctrl->en_bcn = drv_ctrl->enable_bcn ? 1 : 0;
+ ctrl->en_rxbcn_rpt = drv_ctrl->rxbcn_rpt ? 1 : 0;
+ ctrl->en_p2p_ctwin = drv_ctrl->p2p_ctwin ? 1 : 0;
+ ctrl->en_p2p_bcn_area = drv_ctrl->p2p_bcn_area ? 1 : 0;
+}
+
+int rtw_halmac_get_hw_value(struct dvobj_priv *d, enum halmac_hw_id hw_id, void *pvalue)
+{
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
+
+
+ mac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(mac);
+
+ status = api->halmac_get_hw_value(mac, hw_id, pvalue);
+ if (HALMAC_RET_SUCCESS != status)
+ return -1;
+
+ return 0;
+}
+
+/**
+ * rtw_halmac_get_tx_fifo_size() - TX FIFO size
+ * @d: struct dvobj_priv*
+ * @size: TX FIFO size, unit is byte.
+ *
+ * Get TX FIFO size(byte) from HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_get_tx_fifo_size(struct dvobj_priv *d, u32 *size)
+{
+ struct halmac_adapter *halmac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
+ u32 val = 0;
+
+
+ halmac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(halmac);
+
+ status = api->halmac_get_hw_value(halmac, HALMAC_HW_TXFIFO_SIZE, &val);
+ if (status != HALMAC_RET_SUCCESS)
+ return -1;
+
+ *size = val;
+
+ return 0;
+}
+
+/**
+ * rtw_halmac_get_rx_fifo_size() - RX FIFO size
+ * @d: struct dvobj_priv*
+ * @size: RX FIFO size, unit is byte
+ *
+ * Get RX FIFO size(byte) from HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_get_rx_fifo_size(struct dvobj_priv *d, u32 *size)
+{
+ struct halmac_adapter *halmac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
+ u32 val = 0;
+
+
+ halmac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(halmac);
+
+ status = api->halmac_get_hw_value(halmac, HALMAC_HW_RXFIFO_SIZE, &val);
+ if (status != HALMAC_RET_SUCCESS)
+ return -1;
+
+ *size = val;
+
+ return 0;
+}
+
+/**
+ * rtw_halmac_get_rsvd_drv_pg_bndy() - Reserve page boundary of driver
+ * @d: struct dvobj_priv*
+ * @size: Page size, unit is byte
+ *
+ * Get reserve page boundary of driver from HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_get_rsvd_drv_pg_bndy(struct dvobj_priv *d, u16 *bndy)
+{
+ struct halmac_adapter *halmac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
+ u16 val = 0;
+
+
+ halmac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(halmac);
+
+ status = api->halmac_get_hw_value(halmac, HALMAC_HW_RSVD_PG_BNDY, &val);
+ if (status != HALMAC_RET_SUCCESS)
+ return -1;
+
+ *bndy = val;
+
+ return 0;
+}
+
+/**
+ * rtw_halmac_get_page_size() - Page size
+ * @d: struct dvobj_priv*
+ * @size: Page size, unit is byte
+ *
+ * Get TX/RX page size(byte) from HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_get_page_size(struct dvobj_priv *d, u32 *size)
+{
+ struct halmac_adapter *halmac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
+ u32 val = 0;
+
+
+ halmac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(halmac);
+
+ status = api->halmac_get_hw_value(halmac, HALMAC_HW_PAGE_SIZE, &val);
+ if (status != HALMAC_RET_SUCCESS)
+ return -1;
+
+ *size = val;
+
+ return 0;
+}
+
+/**
+ * rtw_halmac_get_tx_agg_align_size() - TX aggregation align size
+ * @d: struct dvobj_priv*
+ * @size: TX aggregation align size, unit is byte
+ *
+ * Get TX aggregation align size(byte) from HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_get_tx_agg_align_size(struct dvobj_priv *d, u16 *size)
+{
+ struct halmac_adapter *halmac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
+ u16 val = 0;
+
+
+ halmac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(halmac);
+
+ status = api->halmac_get_hw_value(halmac, HALMAC_HW_TX_AGG_ALIGN_SIZE, &val);
+ if (status != HALMAC_RET_SUCCESS)
+ return -1;
+
+ *size = val;
+
+ return 0;
+}
+
+/**
+ * rtw_halmac_get_rx_agg_align_size() - RX aggregation align size
+ * @d: struct dvobj_priv*
+ * @size: RX aggregation align size, unit is byte
+ *
+ * Get RX aggregation align size(byte) from HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_get_rx_agg_align_size(struct dvobj_priv *d, u8 *size)
+{
+ struct halmac_adapter *halmac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
+ u8 val = 0;
+
+
+ halmac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(halmac);
+
+ status = api->halmac_get_hw_value(halmac, HALMAC_HW_RX_AGG_ALIGN_SIZE, &val);
+ if (status != HALMAC_RET_SUCCESS)
+ return -1;
+
+ *size = val;
+
+ return 0;
+}
+
+/*
+ * Description:
+ * Get RX driver info size. RX driver info is a small memory space between
+ * scriptor and RX payload.
+ *
+ * +-------------------------+
+ * | RX descriptor |
+ * | usually 24 bytes |
+ * +-------------------------+
+ * | RX driver info |
+ * | depends on driver cfg |
+ * +-------------------------+
+ * | RX paylad |
+ * | |
+ * +-------------------------+
+ *
+ * Parameter:
+ * d pointer to struct dvobj_priv of driver
+ * sz rx driver info size in bytes.
+ *
+ * Rteurn:
+ * 0 Success
+ * other Fail
+ */
+int rtw_halmac_get_rx_drv_info_sz(struct dvobj_priv *d, u8 *sz)
+{
+ enum halmac_ret_status status;
+ struct halmac_adapter *halmac = dvobj_to_halmac(d);
+ struct halmac_api *api = HALMAC_GET_API(halmac);
+ u8 dw = 0;
+
+ status = api->halmac_get_hw_value(halmac, HALMAC_HW_DRV_INFO_SIZE, &dw);
+ if (status != HALMAC_RET_SUCCESS)
+ return -1;
+
+ *sz = dw * 8;
+ return 0;
+}
+
+/**
+ * rtw_halmac_get_tx_desc_size() - TX descriptor size
+ * @d: struct dvobj_priv*
+ * @size: TX descriptor size, unit is byte.
+ *
+ * Get TX descriptor size(byte) from HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_get_tx_desc_size(struct dvobj_priv *d, u32 *size)
+{
+ struct halmac_adapter *halmac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
+ u32 val = 0;
+
+
+ halmac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(halmac);
+
+ status = api->halmac_get_hw_value(halmac, HALMAC_HW_TX_DESC_SIZE, &val);
+ if (status != HALMAC_RET_SUCCESS)
+ return -1;
+
+ *size = val;
+
+ return 0;
+}
+
+/**
+ * rtw_halmac_get_rx_desc_size() - RX descriptor size
+ * @d: struct dvobj_priv*
+ * @size: RX descriptor size, unit is byte.
+ *
+ * Get RX descriptor size(byte) from HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_get_rx_desc_size(struct dvobj_priv *d, u32 *size)
+{
+ struct halmac_adapter *halmac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
+ u32 val = 0;
+
+
+ halmac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(halmac);
+
+ status = api->halmac_get_hw_value(halmac, HALMAC_HW_RX_DESC_SIZE, &val);
+ if (status != HALMAC_RET_SUCCESS)
+ return -1;
+
+ *size = val;
+
+ return 0;
+}
+
+
+/**
+ * rtw_halmac_get_fw_max_size() - Firmware MAX size
+ * @d: struct dvobj_priv*
+ * @size: MAX Firmware size, unit is byte.
+ *
+ * Get Firmware MAX size(byte) from HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+static int rtw_halmac_get_fw_max_size(struct dvobj_priv *d, u32 *size)
+{
+ struct halmac_adapter *halmac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
+ u32 val = 0;
+
+
+ halmac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(halmac);
+
+ status = api->halmac_get_hw_value(halmac, HALMAC_HW_FW_MAX_SIZE, &val);
+ if (status != HALMAC_RET_SUCCESS)
+ return -1;
+
+ *size = val;
+
+ return 0;
+}
+
+/**
+ * rtw_halmac_get_ori_h2c_size() - Original H2C MAX size
+ * @d: struct dvobj_priv*
+ * @size: H2C MAX size, unit is byte.
+ *
+ * Get original H2C MAX size(byte) from HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_get_ori_h2c_size(struct dvobj_priv *d, u32 *size)
+{
+ struct halmac_adapter *halmac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
+ u32 val = 0;
+
+
+ halmac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(halmac);
+
+ status = api->halmac_get_hw_value(halmac, HALMAC_HW_ORI_H2C_SIZE, &val);
+ if (status != HALMAC_RET_SUCCESS)
+ return -1;
+
+ *size = val;
+
+ return 0;
+}
+
+int rtw_halmac_get_oqt_size(struct dvobj_priv *d, u8 *size)
+{
+ enum halmac_ret_status status;
+ struct halmac_adapter *halmac;
+ struct halmac_api *api;
+ u8 val;
+
+
+ if (!size)
+ return -1;
+
+ halmac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(halmac);
+
+ status = api->halmac_get_hw_value(halmac, HALMAC_HW_AC_OQT_SIZE, &val);
+ if (status != HALMAC_RET_SUCCESS)
+ return -1;
+
+ *size = val;
+ return 0;
+}
+
+int rtw_halmac_get_ac_queue_number(struct dvobj_priv *d, u8 *num)
+{
+ enum halmac_ret_status status;
+ struct halmac_adapter *halmac;
+ struct halmac_api *api;
+ u8 val;
+
+
+ if (!num)
+ return -1;
+
+ halmac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(halmac);
+
+ status = api->halmac_get_hw_value(halmac, HALMAC_HW_AC_QUEUE_NUM, &val);
+ if (status != HALMAC_RET_SUCCESS)
+ return -1;
+
+ *num = val;
+ return 0;
+}
+
+/**
+ * rtw_halmac_get_mac_address() - Get MAC address of specific port
+ * @d: struct dvobj_priv*
+ * @hwport: port
+ * @addr: buffer for storing MAC address
+ *
+ * Get MAC address of specific port from HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_get_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr)
+{
+ struct halmac_adapter *halmac;
+ struct halmac_api *api;
+ enum halmac_portid port;
+ union halmac_wlan_addr hwa;
+ enum halmac_ret_status status;
+ int err = -1;
+
+
+ if (!addr)
+ goto out;
+
+ halmac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(halmac);
+ port = _hw_port_drv2halmac(hwport);
+ _rtw_memset(&hwa, 0, sizeof(hwa));
+
+ status = api->halmac_get_mac_addr(halmac, port, &hwa);
+ if (status != HALMAC_RET_SUCCESS)
+ goto out;
+
+ _rtw_memcpy(addr, hwa.addr, 6);
+
+ err = 0;
+out:
+ return err;
+}
+
+/**
+ * rtw_halmac_get_network_type() - Get network type of specific port
+ * @d: struct dvobj_priv*
+ * @hwport: port
+ * @type: buffer to put network type (_HW_STATE_*)
+ *
+ * Get network type of specific port from HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_get_network_type(struct dvobj_priv *d, enum _hw_port hwport, u8 *type)
+{
+#if 0
+ struct halmac_adapter *halmac;
+ struct halmac_api *api;
+ enum halmac_portid port;
+ enum halmac_network_type_select network;
+ enum halmac_ret_status status;
+ int err = -1;
+
+
+ halmac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(halmac);
+ port = _hw_port_drv2halmac(hwport);
+ network = HALMAC_NETWORK_UNDEFINE;
+
+ status = api->halmac_get_net_type(halmac, port, &network);
+ if (status != HALMAC_RET_SUCCESS)
+ goto out;
+
+ *type = _network_type_halmac2drv(network);
+
+ err = 0;
+out:
+ return err;
+#else
+ struct _ADAPTER *a;
+ enum halmac_portid port;
+ enum halmac_network_type_select network;
+ u32 val;
+ int err = -1;
+
+
+ a = dvobj_get_primary_adapter(d);
+ port = _hw_port_drv2halmac(hwport);
+ network = HALMAC_NETWORK_UNDEFINE;
+
+ switch (port) {
+ case HALMAC_PORTID0:
+ val = rtw_read32(a, REG_CR);
+ network = BIT_GET_NETYPE0(val);
+ break;
+
+ case HALMAC_PORTID1:
+ val = rtw_read32(a, REG_CR);
+ network = BIT_GET_NETYPE1(val);
+ break;
+
+ case HALMAC_PORTID2:
+ val = rtw_read32(a, REG_CR_EXT);
+ network = BIT_GET_NETYPE2(val);
+ break;
+
+ case HALMAC_PORTID3:
+ val = rtw_read32(a, REG_CR_EXT);
+ network = BIT_GET_NETYPE3(val);
+ break;
+
+ case HALMAC_PORTID4:
+ val = rtw_read32(a, REG_CR_EXT);
+ network = BIT_GET_NETYPE4(val);
+ break;
+
+ default:
+ goto out;
+ }
+
+ *type = _network_type_halmac2drv(network);
+
+ err = 0;
+out:
+ return err;
+#endif
+}
+
+/**
+ * rtw_halmac_get_bcn_ctrl() - Get beacon control setting of specific port
+ * @d: struct dvobj_priv*
+ * @hwport: port
+ * @bcn_ctrl: setting of beacon control
+ *
+ * Get beacon control setting of specific port from HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_get_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport,
+ struct rtw_halmac_bcn_ctrl *bcn_ctrl)
+{
+ struct halmac_adapter *halmac;
+ struct halmac_api *api;
+ enum halmac_portid port;
+ struct halmac_bcn_ctrl ctrl;
+ enum halmac_ret_status status;
+ int err = -1;
+
+
+ halmac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(halmac);
+ port = _hw_port_drv2halmac(hwport);
+ _rtw_memset(&ctrl, 0, sizeof(ctrl));
+
+ status = api->halmac_rw_bcn_ctrl(halmac, port, 0, &ctrl);
+ if (status != HALMAC_RET_SUCCESS)
+ goto out;
+ _beacon_ctrl_halmac2drv(&ctrl, bcn_ctrl);
+
+ err = 0;
+out:
+ return err;
+}
+
+/*
+ * Note:
+ * When this function return, the register REG_RCR may be changed.
+ */
+int rtw_halmac_config_rx_info(struct dvobj_priv *d, enum halmac_drv_info info)
+{
+ struct halmac_adapter *halmac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
+ int err = -1;
+
+
+ halmac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(halmac);
+
+ status = api->halmac_cfg_drv_info(halmac, info);
+ if (status != HALMAC_RET_SUCCESS)
+ goto out;
+
+ err = 0;
+out:
+ return err;
+}
+
+/**
+ * rtw_halmac_set_max_dl_fw_size() - Set the MAX download firmware size
+ * @d: struct dvobj_priv*
+ * @size: the max download firmware size in one I/O
+ *
+ * Set the max download firmware size in one I/O.
+ * Please also consider the max size of the callback function "SEND_RSVD_PAGE"
+ * could accept, because download firmware would call "SEND_RSVD_PAGE" to send
+ * firmware to IC.
+ *
+ * If the value of "size" is not even, it would be rounded down to nearest
+ * even, and 0 and 1 are both invalid value.
+ *
+ * Return 0 for setting OK, otherwise fail.
+ */
+int rtw_halmac_set_max_dl_fw_size(struct dvobj_priv *d, u32 size)
+{
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
+
+
+ if (!size || (size == 1))
+ return -1;
+
+ mac = dvobj_to_halmac(d);
+ if (!mac) {
+ RTW_ERR("%s: HALMAC is not ready!!\n", __FUNCTION__);
+ return -1;
+ }
+ api = HALMAC_GET_API(mac);
+
+ size &= ~1; /* round down to even */
+ status = api->halmac_cfg_max_dl_size(mac, size);
+ if (status != HALMAC_RET_SUCCESS) {
+ RTW_WARN("%s: Fail to cfg_max_dl_size(%d), err=%d!!\n",
+ __FUNCTION__, size, status);
+ return -1;
+ }
+
+ return 0;
+}
+
+/**
+ * rtw_halmac_set_mac_address() - Set mac address of specific port
+ * @d: struct dvobj_priv*
+ * @hwport: port
+ * @addr: mac address
+ *
+ * Set self mac address of specific port to HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_set_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr)
+{
+ struct halmac_adapter *halmac;
+ struct halmac_api *api;
+ enum halmac_portid port;
+ union halmac_wlan_addr hwa;
+ enum halmac_ret_status status;
+ int err = -1;
+
+
+ halmac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(halmac);
+
+ port = _hw_port_drv2halmac(hwport);
+ _rtw_memset(&hwa, 0, sizeof(hwa));
+ _rtw_memcpy(hwa.addr, addr, 6);
+
+ status = api->halmac_cfg_mac_addr(halmac, port, &hwa);
+ if (status != HALMAC_RET_SUCCESS)
+ goto out;
+
+ err = 0;
+out:
+ return err;
+}
+
+/**
+ * rtw_halmac_set_bssid() - Set BSSID of specific port
+ * @d: struct dvobj_priv*
+ * @hwport: port
+ * @addr: BSSID, mac address of AP
+ *
+ * Set BSSID of specific port to HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_set_bssid(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr)
+{
+ struct halmac_adapter *halmac;
+ struct halmac_api *api;
+ enum halmac_portid port;
+ union halmac_wlan_addr hwa;
+ enum halmac_ret_status status;
+ int err = -1;
+
+
+ halmac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(halmac);
+ port = _hw_port_drv2halmac(hwport);
+
+ _rtw_memset(&hwa, 0, sizeof(hwa));
+ _rtw_memcpy(hwa.addr, addr, 6);
+ status = api->halmac_cfg_bssid(halmac, port, &hwa);
+ if (status != HALMAC_RET_SUCCESS)
+ goto out;
+
+ err = 0;
+out:
+ return err;
+}
+
+/**
+ * rtw_halmac_set_tx_address() - Set transmitter address of specific port
+ * @d: struct dvobj_priv*
+ * @hwport: port
+ * @addr: transmitter address
+ *
+ * Set transmitter address of specific port to HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_set_tx_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr)
+{
+ struct halmac_adapter *halmac;
+ struct halmac_api *api;
+ enum halmac_portid port;
+ union halmac_wlan_addr hwa;
+ enum halmac_ret_status status;
+ int err = -1;
+
+
+ halmac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(halmac);
+ port = _hw_port_drv2halmac(hwport);
+ _rtw_memset(&hwa, 0, sizeof(hwa));
+ _rtw_memcpy(hwa.addr, addr, 6);
+
+ status = api->halmac_cfg_transmitter_addr(halmac, port, &hwa);
+ if (status != HALMAC_RET_SUCCESS)
+ goto out;
+
+ err = 0;
+out:
+ return err;
+}
+
+/**
+ * rtw_halmac_set_network_type() - Set network type of specific port
+ * @d: struct dvobj_priv*
+ * @hwport: port
+ * @type: network type (_HW_STATE_*)
+ *
+ * Set network type of specific port to HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_set_network_type(struct dvobj_priv *d, enum _hw_port hwport, u8 type)
+{
+ struct halmac_adapter *halmac;
+ struct halmac_api *api;
+ enum halmac_portid port;
+ enum halmac_network_type_select network;
+ enum halmac_ret_status status;
+ int err = -1;
+
+
+ halmac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(halmac);
+ port = _hw_port_drv2halmac(hwport);
+ network = _network_type_drv2halmac(type);
+
+ status = api->halmac_cfg_net_type(halmac, port, network);
+ if (status != HALMAC_RET_SUCCESS)
+ goto out;
+
+ err = 0;
+out:
+ return err;
+}
+
+/**
+ * rtw_halmac_reset_tsf() - Reset TSF timer of specific port
+ * @d: struct dvobj_priv*
+ * @hwport: port
+ *
+ * Notice HALMAC to reset timing synchronization function(TSF) timer of
+ * specific port.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_reset_tsf(struct dvobj_priv *d, enum _hw_port hwport)
+{
+ struct halmac_adapter *halmac;
+ struct halmac_api *api;
+ enum halmac_portid port;
+ enum halmac_ret_status status;
+ int err = -1;
+
+
+ halmac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(halmac);
+ port = _hw_port_drv2halmac(hwport);
+
+ status = api->halmac_cfg_tsf_rst(halmac, port);
+ if (status != HALMAC_RET_SUCCESS)
+ goto out;
+
+ err = 0;
+out:
+ return err;
+}
+
+/**
+ * rtw_halmac_set_bcn_interval() - Set beacon interval of each port
+ * @d: struct dvobj_priv*
+ * @hwport: port
+ * @space: beacon interval, unit is ms
+ *
+ * Set beacon interval of specific port to HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_set_bcn_interval(struct dvobj_priv *d, enum _hw_port hwport,
+ u32 interval)
+{
+ struct halmac_adapter *halmac;
+ struct halmac_api *api;
+ enum halmac_portid port;
+ enum halmac_ret_status status;
+ int err = -1;
+
+
+ halmac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(halmac);
+ port = _hw_port_drv2halmac(hwport);
+
+ status = api->halmac_cfg_bcn_space(halmac, port, interval);
+ if (status != HALMAC_RET_SUCCESS)
+ goto out;
+
+ err = 0;
+out:
+ return err;
+}
+
+/**
+ * rtw_halmac_set_bcn_ctrl() - Set beacon control setting of each port
+ * @d: struct dvobj_priv*
+ * @hwport: port
+ * @bcn_ctrl: setting of beacon control
+ *
+ * Set beacon control setting of specific port to HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_set_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport,
+ struct rtw_halmac_bcn_ctrl *bcn_ctrl)
+{
+ struct halmac_adapter *halmac;
+ struct halmac_api *api;
+ enum halmac_portid port;
+ struct halmac_bcn_ctrl ctrl;
+ enum halmac_ret_status status;
+ int err = -1;
+
+
+ halmac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(halmac);
+ port = _hw_port_drv2halmac(hwport);
+ _rtw_memset(&ctrl, 0, sizeof(ctrl));
+ _beacon_ctrl_drv2halmac(bcn_ctrl, &ctrl);
+
+ status = api->halmac_rw_bcn_ctrl(halmac, port, 1, &ctrl);
+ if (status != HALMAC_RET_SUCCESS)
+ goto out;
+
+ err = 0;
+out:
+ return err;
+}
+
+/**
+ * rtw_halmac_set_aid() - Set association identifier(AID) of specific port
+ * @d: struct dvobj_priv*
+ * @hwport: port
+ * @aid: Association identifier
+ *
+ * Set association identifier(AID) of specific port to HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_set_aid(struct dvobj_priv *d, enum _hw_port hwport, u16 aid)
+{
+ struct halmac_adapter *halmac;
+ struct halmac_api *api;
+ enum halmac_portid port;
+ enum halmac_ret_status status;
+ int err = -1;
+
+
+ halmac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(halmac);
+ port = _hw_port_drv2halmac(hwport);
+
+#if 0
+ status = api->halmac_cfg_aid(halmac, port, aid);
+ if (status != HALMAC_RET_SUCCESS)
+ goto out;
+#else
+{
+ struct _ADAPTER *a;
+ u32 addr;
+ u16 val;
+
+ a = dvobj_get_primary_adapter(d);
+
+ switch (port) {
+ case 0:
+ addr = REG_BCN_PSR_RPT;
+ val = rtw_read16(a, addr);
+ val = BIT_SET_PS_AID_0(val, aid);
+ rtw_write16(a, addr, val);
+ break;
+
+ case 1:
+ addr = REG_BCN_PSR_RPT1;
+ val = rtw_read16(a, addr);
+ val = BIT_SET_PS_AID_1(val, aid);
+ rtw_write16(a, addr, val);
+ break;
+
+ case 2:
+ addr = REG_BCN_PSR_RPT2;
+ val = rtw_read16(a, addr);
+ val = BIT_SET_PS_AID_2(val, aid);
+ rtw_write16(a, addr, val);
+ break;
+
+ case 3:
+ addr = REG_BCN_PSR_RPT3;
+ val = rtw_read16(a, addr);
+ val = BIT_SET_PS_AID_3(val, aid);
+ rtw_write16(a, addr, val);
+ break;
+
+ case 4:
+ addr = REG_BCN_PSR_RPT4;
+ val = rtw_read16(a, addr);
+ val = BIT_SET_PS_AID_4(val, aid);
+ rtw_write16(a, addr, val);
+ break;
+
+ default:
+ goto out;
+ }
+}
+#endif
+
+ err = 0;
+out:
+ return err;
+}
+
+int rtw_halmac_set_bandwidth(struct dvobj_priv *d, u8 channel, u8 pri_ch_idx, u8 bw)
+{
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
+
+
+ mac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(mac);
+
+ status = api->halmac_cfg_ch_bw(mac, channel, pri_ch_idx, bw);
+ if (HALMAC_RET_SUCCESS != status)
+ return -1;
+
+ return 0;
+}
+
+/**
+ * rtw_halmac_set_edca() - config edca parameter
+ * @d: struct dvobj_priv*
+ * @queue: XMIT_[VO/VI/BE/BK]_QUEUE
+ * @aifs: Arbitration inter-frame space(AIFS)
+ * @cw: Contention window(CW)
+ * @txop: MAX Transmit Opportunity(TXOP)
+ *
+ * Return: 0 if process OK, otherwise -1.
+ */
+int rtw_halmac_set_edca(struct dvobj_priv *d, u8 queue, u8 aifs, u8 cw, u16 txop)
+{
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ enum halmac_acq_id ac;
+ struct halmac_edca_para edca;
+ enum halmac_ret_status status;
+
+
+ mac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(mac);
+
+ switch (queue) {
+ case XMIT_VO_QUEUE:
+ ac = HALMAC_ACQ_ID_VO;
+ break;
+ case XMIT_VI_QUEUE:
+ ac = HALMAC_ACQ_ID_VI;
+ break;
+ case XMIT_BE_QUEUE:
+ ac = HALMAC_ACQ_ID_BE;
+ break;
+ case XMIT_BK_QUEUE:
+ ac = HALMAC_ACQ_ID_BK;
+ break;
+ default:
+ return -1;
+ }
+
+ edca.aifs = aifs;
+ edca.cw = cw;
+ edca.txop_limit = txop;
+
+ status = api->halmac_cfg_edca_para(mac, ac, &edca);
+ if (status != HALMAC_RET_SUCCESS)
+ return -1;
+
+ return 0;
+}
+
+/*
+ * Description:
+ * Power on device hardware.
+ * [Notice!] If device's power state is on before,
+ * it would be power off first and turn on power again.
+ *
+ * Return:
+ * 0 power on success
+ * -1 power on fail
+ * -2 power state unchange
+ */
+int rtw_halmac_poweron(struct dvobj_priv *d)
+{
+ struct halmac_adapter *halmac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
+ int err = -1;
+
+
+ halmac = dvobj_to_halmac(d);
+ if (!halmac)
+ goto out;
+
+ api = HALMAC_GET_API(halmac);
+
+ status = api->halmac_pre_init_system_cfg(halmac);
+ if (status != HALMAC_RET_SUCCESS)
+ goto out;
+
+#ifdef CONFIG_SDIO_HCI
+ status = api->halmac_sdio_cmd53_4byte(halmac, HALMAC_SDIO_CMD53_4BYTE_MODE_RW);
+ if (status != HALMAC_RET_SUCCESS)
+ goto out;
+#endif /* CONFIG_SDIO_HCI */
+
+ status = api->halmac_mac_power_switch(halmac, HALMAC_MAC_POWER_ON);
+ if (HALMAC_RET_PWR_UNCHANGE == status) {
+ /*
+ * Work around for warm reboot but device not power off,
+ * but it would also fall into this case when auto power on is enabled.
+ */
+ api->halmac_mac_power_switch(halmac, HALMAC_MAC_POWER_OFF);
+ status = api->halmac_mac_power_switch(halmac, HALMAC_MAC_POWER_ON);
+ RTW_WARN("%s: Power state abnormal, try to recover...%s\n",
+ __FUNCTION__, (HALMAC_RET_SUCCESS == status)?"OK":"FAIL!");
+ }
+ if (HALMAC_RET_SUCCESS != status) {
+ if (HALMAC_RET_PWR_UNCHANGE == status)
+ err = -2;
+ goto out;
+ }
+
+ status = api->halmac_init_system_cfg(halmac);
+ if (status != HALMAC_RET_SUCCESS)
+ goto out;
+
+ err = 0;
+out:
+ return err;
+}
+
+/*
+ * Description:
+ * Power off device hardware.
+ *
+ * Return:
+ * 0 Power off success
+ * -1 Power off fail
+ */
+int rtw_halmac_poweroff(struct dvobj_priv *d)
+{
+ struct halmac_adapter *halmac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
+ int err = -1;
+
+
+ halmac = dvobj_to_halmac(d);
+ if (!halmac)
+ goto out;
+
+ api = HALMAC_GET_API(halmac);
+
+ status = api->halmac_mac_power_switch(halmac, HALMAC_MAC_POWER_OFF);
+ if ((HALMAC_RET_SUCCESS != status)
+ && (HALMAC_RET_PWR_UNCHANGE != status))
+ goto out;
+
+ err = 0;
+out:
+ return err;
+}
+
+#ifdef CONFIG_SUPPORT_TRX_SHARED
+static inline enum halmac_rx_fifo_expanding_mode _trx_share_mode_drv2halmac(u8 trx_share_mode)
+{
+ if (0 == trx_share_mode)
+ return HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE;
+ else if (1 == trx_share_mode)
+ return HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK;
+ else if (2 == trx_share_mode)
+ return HALMAC_RX_FIFO_EXPANDING_MODE_2_BLOCK;
+ else if (3 == trx_share_mode)
+ return HALMAC_RX_FIFO_EXPANDING_MODE_3_BLOCK;
+ else
+ return HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE;
+}
+
+static enum halmac_rx_fifo_expanding_mode _rtw_get_trx_share_mode(struct _ADAPTER *adapter)
+{
+ struct registry_priv *registry_par = &adapter->registrypriv;
+
+ return _trx_share_mode_drv2halmac(registry_par->trx_share_mode);
+}
+
+void dump_trx_share_mode(void *sel, struct _ADAPTER *adapter)
+{
+ struct registry_priv *registry_par = &adapter->registrypriv;
+ u8 mode = _trx_share_mode_drv2halmac(registry_par->trx_share_mode);
+
+ if (HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK == mode)
+ RTW_PRINT_SEL(sel, "TRx share mode : %s\n", "RX_FIFO_EXPANDING_MODE_1");
+ else if (HALMAC_RX_FIFO_EXPANDING_MODE_2_BLOCK == mode)
+ RTW_PRINT_SEL(sel, "TRx share mode : %s\n", "RX_FIFO_EXPANDING_MODE_2");
+ else if (HALMAC_RX_FIFO_EXPANDING_MODE_3_BLOCK == mode)
+ RTW_PRINT_SEL(sel, "TRx share mode : %s\n", "RX_FIFO_EXPANDING_MODE_3");
+ else
+ RTW_PRINT_SEL(sel, "TRx share mode : %s\n", "DISABLE");
+}
+#endif
+
+static enum halmac_drv_rsvd_pg_num _rsvd_page_num_drv2halmac(u8 num)
+{
+ if (num <= 8)
+ return HALMAC_RSVD_PG_NUM8;
+ if (num <= 16)
+ return HALMAC_RSVD_PG_NUM16;
+ if (num <= 24)
+ return HALMAC_RSVD_PG_NUM24;
+ if (num <= 32)
+ return HALMAC_RSVD_PG_NUM32;
+ if (num <= 64)
+ return HALMAC_RSVD_PG_NUM64;
+
+ if (num > 128)
+ RTW_WARN("%s: Fail to allocate RSVD page(%d)!!"
+ " The MAX RSVD page number is 128...\n",
+ __FUNCTION__, num);
+
+ return HALMAC_RSVD_PG_NUM128;
+}
+
+static u8 _rsvd_page_num_halmac2drv(enum halmac_drv_rsvd_pg_num rsvd_page_number)
+{
+ u8 num = 0;
+
+
+ switch (rsvd_page_number) {
+ case HALMAC_RSVD_PG_NUM8:
+ num = 8;
+ break;
+
+ case HALMAC_RSVD_PG_NUM16:
+ num = 16;
+ break;
+
+ case HALMAC_RSVD_PG_NUM24:
+ num = 24;
+ break;
+
+ case HALMAC_RSVD_PG_NUM32:
+ num = 32;
+ break;
+
+ case HALMAC_RSVD_PG_NUM64:
+ num = 64;
+ break;
+
+ case HALMAC_RSVD_PG_NUM128:
+ num = 128;
+ break;
+ }
+
+ return num;
+}
+
+static enum halmac_trx_mode _choose_trx_mode(struct dvobj_priv *d)
+{
+ PADAPTER p;
+
+
+ p = dvobj_get_primary_adapter(d);
+
+ if (p->registrypriv.wifi_spec)
+ return HALMAC_TRX_MODE_WMM;
+
+#ifdef CONFIG_SUPPORT_TRX_SHARED
+ if (_rtw_get_trx_share_mode(p))
+ return HALMAC_TRX_MODE_TRXSHARE;
+#endif
+
+ return HALMAC_TRX_MODE_NORMAL;
+}
+
+static inline enum halmac_rf_type _rf_type_drv2halmac(enum rf_type rf_drv)
+{
+ enum halmac_rf_type rf_mac;
+
+
+ switch (rf_drv) {
+ case RF_1T1R:
+ rf_mac = HALMAC_RF_1T1R;
+ break;
+ case RF_1T2R:
+ rf_mac = HALMAC_RF_1T2R;
+ break;
+ case RF_2T2R:
+ rf_mac = HALMAC_RF_2T2R;
+ break;
+ case RF_2T3R:
+ rf_mac = HALMAC_RF_2T3R;
+ break;
+ case RF_2T4R:
+ rf_mac = HALMAC_RF_2T4R;
+ break;
+ case RF_3T3R:
+ rf_mac = HALMAC_RF_3T3R;
+ break;
+ case RF_3T4R:
+ rf_mac = HALMAC_RF_3T4R;
+ break;
+ case RF_4T4R:
+ rf_mac = HALMAC_RF_4T4R;
+ break;
+ default:
+ rf_mac = HALMAC_RF_MAX_TYPE;
+ RTW_ERR("%s: Invalid RF type(0x%x)!\n", __FUNCTION__, rf_drv);
+ break;
+ }
+
+ return rf_mac;
+}
+
+static inline enum rf_type _rf_type_halmac2drv(enum halmac_rf_type rf_mac)
+{
+ enum rf_type rf_drv;
+
+
+ switch (rf_mac) {
+ case HALMAC_RF_1T2R:
+ rf_drv = RF_1T2R;
+ break;
+ case HALMAC_RF_2T4R:
+ rf_drv = RF_2T4R;
+ break;
+ case HALMAC_RF_2T2R:
+ case HALMAC_RF_2T2R_GREEN:
+ rf_drv = RF_2T2R;
+ break;
+ case HALMAC_RF_2T3R:
+ rf_drv = RF_2T3R;
+ break;
+ case HALMAC_RF_1T1R:
+ rf_drv = RF_1T1R;
+ break;
+ case HALMAC_RF_3T3R:
+ rf_drv = RF_3T3R;
+ break;
+ case HALMAC_RF_3T4R:
+ rf_drv = RF_3T4R;
+ break;
+ case HALMAC_RF_4T4R:
+ rf_drv = RF_4T4R;
+ break;
+ default:
+ rf_drv = RF_TYPE_MAX;
+ RTW_ERR("%s: Invalid RF type(0x%x)!\n", __FUNCTION__, rf_mac);
+ break;
+ }
+
+ return rf_drv;
+}
+
+static enum odm_cut_version _cut_version_drv2phydm(
+ enum tag_HAL_Cut_Version_Definition cut_drv)
+{
+ enum odm_cut_version cut_phydm = ODM_CUT_A;
+ u32 diff;
+
+
+ if (cut_drv > K_CUT_VERSION)
+ RTW_WARN("%s: unknown cut_ver=%d !!\n", __FUNCTION__, cut_drv);
+
+ diff = cut_drv - A_CUT_VERSION;
+ cut_phydm += diff;
+
+ return cut_phydm;
+}
+
+static int _send_general_info_by_reg(struct dvobj_priv *d,
+ struct halmac_general_info *info)
+{
+ struct _ADAPTER *a;
+ struct hal_com_data *hal;
+ enum tag_HAL_Cut_Version_Definition cut_drv;
+ enum rf_type rftype;
+ enum odm_cut_version cut_phydm;
+ u8 h2c[RTW_HALMAC_H2C_MAX_SIZE] = {0};
+
+
+ a = dvobj_get_primary_adapter(d);
+ hal = GET_HAL_DATA(a);
+ rftype = _rf_type_halmac2drv(info->rf_type);
+ cut_drv = GET_CVID_CUT_VERSION(hal->version_id);
+ cut_phydm = _cut_version_drv2phydm(cut_drv);
+
+#define CLASS_GENERAL_INFO_REG 0x02
+#define CMD_ID_GENERAL_INFO_REG 0x0C
+#define GENERAL_INFO_REG_SET_CMD_ID(buf, v) SET_BITS_TO_LE_4BYTE(buf, 0, 5, v)
+#define GENERAL_INFO_REG_SET_CLASS(buf, v) SET_BITS_TO_LE_4BYTE(buf, 5, 3, v)
+#define GENERAL_INFO_REG_SET_RFE_TYPE(buf, v) SET_BITS_TO_LE_4BYTE(buf, 8, 8, v)
+#define GENERAL_INFO_REG_SET_RF_TYPE(buf, v) SET_BITS_TO_LE_4BYTE(buf, 16, 8, v)
+#define GENERAL_INFO_REG_SET_CUT_VERSION(buf, v) SET_BITS_TO_LE_4BYTE(buf, 24, 8, v)
+#define GENERAL_INFO_REG_SET_RX_ANT_STATUS(buf, v) SET_BITS_TO_LE_1BYTE(buf+4, 0, 4, v)
+#define GENERAL_INFO_REG_SET_TX_ANT_STATUS(buf, v) SET_BITS_TO_LE_1BYTE(buf+4, 4, 4, v)
+
+ GENERAL_INFO_REG_SET_CMD_ID(h2c, CMD_ID_GENERAL_INFO_REG);
+ GENERAL_INFO_REG_SET_CLASS(h2c, CLASS_GENERAL_INFO_REG);
+ GENERAL_INFO_REG_SET_RFE_TYPE(h2c, info->rfe_type);
+ GENERAL_INFO_REG_SET_RF_TYPE(h2c, rftype);
+ GENERAL_INFO_REG_SET_CUT_VERSION(h2c, cut_phydm);
+ GENERAL_INFO_REG_SET_RX_ANT_STATUS(h2c, info->rx_ant_status);
+ GENERAL_INFO_REG_SET_TX_ANT_STATUS(h2c, info->tx_ant_status);
+
+ return rtw_halmac_send_h2c(d, h2c);
+}
+
+static int _send_general_info(struct dvobj_priv *d)
+{
+ struct _ADAPTER *adapter;
+ struct hal_com_data *hal;
+ struct halmac_adapter *halmac;
+ struct halmac_api *api;
+ struct halmac_general_info info;
+ enum halmac_ret_status status;
+ enum rf_type rf = RF_1T1R;
+ enum bb_path txpath = BB_PATH_A;
+ enum bb_path rxpath = BB_PATH_A;
+ int err;
+
+
+ adapter = dvobj_get_primary_adapter(d);
+ hal = GET_HAL_DATA(adapter);
+ halmac = dvobj_to_halmac(d);
+ if (!halmac)
+ return -1;
+ api = HALMAC_GET_API(halmac);
+
+ _rtw_memset(&info, 0, sizeof(info));
+ info.rfe_type = (u8)hal->rfe_type;
+ rtw_hal_get_rf_path(d, &rf, &txpath, &rxpath);
+ info.rf_type = _rf_type_drv2halmac(rf);
+ info.tx_ant_status = (u8)txpath;
+ info.rx_ant_status = (u8)rxpath;
+
+ status = api->halmac_send_general_info(halmac, &info);
+ switch (status) {
+ case HALMAC_RET_SUCCESS:
+ break;
+ case HALMAC_RET_NO_DLFW:
+ RTW_WARN("%s: halmac_send_general_info() fail because fw not dl!\n",
+ __FUNCTION__);
+ // fallthrough
+ default:
+ return -1;
+ }
+
+ err = _send_general_info_by_reg(d, &info);
+ if (err) {
+ RTW_ERR("%s: Fail to send general info by register!\n",
+ __FUNCTION__);
+ return -1;
+ }
+
+ return 0;
+}
+
+static int _cfg_drv_rsvd_pg_num(struct dvobj_priv *d)
+{
+ struct _ADAPTER *a;
+ struct hal_com_data *hal;
+ struct halmac_adapter *halmac;
+ struct halmac_api *api;
+ enum halmac_drv_rsvd_pg_num rsvd_page_number;
+ enum halmac_ret_status status;
+ u8 drv_rsvd_num;
+
+
+ a = dvobj_get_primary_adapter(d);
+ hal = GET_HAL_DATA(a);
+ halmac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(halmac);
+
+ drv_rsvd_num = rtw_hal_get_rsvd_page_num(a);
+ rsvd_page_number = _rsvd_page_num_drv2halmac(drv_rsvd_num);
+ status = api->halmac_cfg_drv_rsvd_pg_num(halmac, rsvd_page_number);
+ if (status != HALMAC_RET_SUCCESS)
+ return -1;
+ hal->drv_rsvd_page_number = _rsvd_page_num_halmac2drv(rsvd_page_number);
+
+ if (drv_rsvd_num != hal->drv_rsvd_page_number)
+ RTW_INFO("%s: request %d pages, but allocate %d pages\n",
+ __FUNCTION__, drv_rsvd_num, hal->drv_rsvd_page_number);
+
+ return 0;
+}
+
+static void _debug_dlfw_fail(struct dvobj_priv *d)
+{
+ struct _ADAPTER *a;
+ u32 addr;
+ u32 v32, i, n;
+ u8 data[0x100] = {0};
+
+
+ a = dvobj_get_primary_adapter(d);
+
+ /* read 0x80[15:0], 0x10F8[31:0] once */
+ addr = 0x80;
+ v32 = rtw_read16(a, addr);
+ RTW_PRINT("%s: 0x%X = 0x%04x\n", __FUNCTION__, addr, v32);
+
+ addr = 0x10F8;
+ v32 = rtw_read32(a, addr);
+ RTW_PRINT("%s: 0x%X = 0x%08x\n", __FUNCTION__, addr, v32);
+
+ /* read 0x10FC[31:0], 5 times */
+ addr = 0x10FC;
+ n = 5;
+ for (i = 0; i < n; i++) {
+ v32 = rtw_read32(a, addr);
+ RTW_PRINT("%s: 0x%X = 0x%08x (%u/%u)\n",
+ __FUNCTION__, addr, v32, i, n);
+ }
+
+ /*
+ * write 0x3A[7:0]=0x28 and 0xF6[7:0]=0x01
+ * and then read 0xC0[31:0] 5 times
+ */
+ addr = 0x3A;
+ v32 = 0x28;
+ rtw_write8(a, addr, (u8)v32);
+ v32 = rtw_read8(a, addr);
+ RTW_PRINT("%s: 0x%X = 0x%02x\n", __FUNCTION__, addr, v32);
+
+ addr = 0xF6;
+ v32 = 0x1;
+ rtw_write8(a, addr, (u8)v32);
+ v32 = rtw_read8(a, addr);
+ RTW_PRINT("%s: 0x%X = 0x%02x\n", __FUNCTION__, addr, v32);
+
+ addr = 0xC0;
+ n = 5;
+ for (i = 0; i < n; i++) {
+ v32 = rtw_read32(a, addr);
+ RTW_PRINT("%s: 0x%X = 0x%08x (%u/%u)\n",
+ __FUNCTION__, addr, v32, i, n);
+ }
+
+ /* 0x00~0xFF, 0x1000~0x10FF */
+ addr = 0;
+ n = 0x100;
+ for (i = 0; i < n; i+=4)
+ *(u32*)&data[i] = cpu_to_le32(rtw_read32(a, addr+i));
+ for (i = 0; i < n; i++) {
+ if (i % 16 == 0)
+ RTW_PRINT("0x%04x\t", addr+i);
+ _RTW_PRINT("0x%02x", data[i]);
+ if (i % 16 == 15)
+ _RTW_PRINT("\n");
+ else
+ _RTW_PRINT(" ");
+ }
+
+ addr = 0x1000;
+ n = 0x100;
+ for (i = 0; i < n; i+=4)
+ *(u32*)&data[i] = cpu_to_le32(rtw_read32(a, addr+i));
+ for (i = 0; i < n; i++) {
+ if (i % 16 == 0)
+ RTW_PRINT("0x%04x\t", addr+i);
+ _RTW_PRINT("0x%02x", data[i]);
+ if (i % 16 == 15)
+ _RTW_PRINT("\n");
+ else
+ _RTW_PRINT(" ");
+ }
+
+ /* read 0x80 after 10 secs */
+ rtw_msleep_os(10000);
+ addr = 0x80;
+ v32 = rtw_read16(a, addr);
+ RTW_PRINT("%s: 0x%X = 0x%04x (after 10 secs)\n",
+ __FUNCTION__, addr, v32);
+}
+
+static enum halmac_ret_status _enter_cpu_sleep_mode(struct dvobj_priv *d)
+{
+ struct hal_com_data *hal;
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+
+
+ hal = GET_HAL_DATA(dvobj_get_primary_adapter(d));
+ mac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(mac);
+
+#ifdef CONFIG_RTL8822B
+ /* Support after firmware version 21 */
+ if (hal->firmware_version < 21)
+ return HALMAC_RET_NOT_SUPPORT;
+#elif defined(CONFIG_RTL8821C)
+ /* Support after firmware version 13.6 or 16 */
+ if (hal->firmware_version == 13) {
+ if (hal->firmware_sub_version < 6)
+ return HALMAC_RET_NOT_SUPPORT;
+ } else if (hal->firmware_version < 16) {
+ return HALMAC_RET_NOT_SUPPORT;
+ }
+#endif
+
+ return api->halmac_enter_cpu_sleep_mode(mac);
+}
+
+/*
+ * _cpu_sleep() - Let IC CPU enter sleep mode
+ * @d: struct dvobj_priv*
+ * @timeout: time limit of wait, unit is ms
+ * 0 for no limit
+ *
+ * Rteurn 0 for CPU in sleep mode, otherwise fail to enter sleep mode.
+ * Error codes definition are as follow:
+ * -1 HALMAC enter sleep return fail
+ * -2 HALMAC get CPU mode return fail
+ * -110 timeout
+ */
+static int _cpu_sleep(struct dvobj_priv *d, u32 timeout)
+{
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
+ enum halmac_wlcpu_mode mode = HALMAC_WLCPU_UNDEFINE;
+ systime start_t;
+ s32 period = 0;
+ u32 cnt = 0;
+ int err = 0;
+
+
+ mac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(mac);
+
+ start_t = rtw_get_current_time();
+
+ status = _enter_cpu_sleep_mode(d);
+ if (status != HALMAC_RET_SUCCESS) {
+ if (status != HALMAC_RET_NOT_SUPPORT)
+ err = -1;
+ goto exit;
+ }
+
+ do {
+ cnt++;
+
+ mode = HALMAC_WLCPU_UNDEFINE;
+ status = api->halmac_get_cpu_mode(mac, &mode);
+
+ period = rtw_get_passing_time_ms(start_t);
+
+ if (status != HALMAC_RET_SUCCESS) {
+ err = -2;
+ break;
+ }
+ if (mode == HALMAC_WLCPU_SLEEP)
+ break;
+ if (period > timeout) {
+ err = -110;
+ break;
+ }
+
+ rtw_msleep_os(1);
+ } while (1);
+
+exit:
+ if (err)
+ RTW_ERR("%s: Fail to enter sleep mode! (%d, %d)\n",
+ __FUNCTION__, status, mode);
+
+ RTW_INFO("%s: Cost %dms to polling %u times. (err=%d)\n",
+ __FUNCTION__, period, cnt, err);
+
+ return err;
+}
+
+/*
+ * Description:
+ * Downlaod Firmware Flow
+ *
+ * Parameters:
+ * d pointer of struct dvobj_priv
+ * fw firmware array
+ * fwsize firmware size
+ * re_dl re-download firmware or not
+ * 0: run in init hal flow, not re-download
+ * 1: it is a stand alone operation, not in init hal flow
+ *
+ * Return:
+ * 0 Success
+ * others Fail
+ */
+static int download_fw(struct dvobj_priv *d, u8 *fw, u32 fwsize, u8 re_dl)
+{
+ PHAL_DATA_TYPE hal;
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ struct halmac_fw_version fw_vesion;
+ enum halmac_ret_status status;
+ int err = 0;
+
+
+ hal = GET_HAL_DATA(dvobj_get_primary_adapter(d));
+ mac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(mac);
- status = api->halmac_mac_power_switch(halmac, HALMAC_MAC_POWER_ON);
- if (status != HALMAC_RET_SUCCESS)
- goto out;
+ if ((!fw) || (!fwsize))
+ return -1;
- status = api->halmac_init_system_cfg(halmac);
- if (status != HALMAC_RET_SUCCESS)
- goto out;
+ /* 1. Driver Stop Tx */
+ /* ToDo */
- err = 0;
-out:
- return err;
-}
+ /* 2. Driver Check Tx FIFO is empty */
+ err = rtw_halmac_txfifo_wait_empty(d, 2000); /* wait 2s */
+ if (err) {
+ err = -1;
+ goto resume_tx;
+ }
-int rtw_halmac_poweroff(struct dvobj_priv *d)
-{
- PHALMAC_ADAPTER halmac;
- PHALMAC_API api;
- HALMAC_RET_STATUS status;
- int err = -1;
+ /* 3. Config MAX download size */
+ /*
+ * Already done in rtw_halmac_init_adapter() or
+ * somewhere calling rtw_halmac_set_max_dl_fw_size().
+ */
+
+ if (re_dl) {
+ /* 4. Enter IC CPU sleep mode */
+ err = _cpu_sleep(d, 2000);
+ if (err) {
+ RTW_ERR("%s: IC CPU fail to enter sleep mode!(%d)\n",
+ __FUNCTION__, err);
+ /* skip this error */
+ err = 0;
+ }
+ }
+ /* 5. Download Firmware */
+ status = api->halmac_download_firmware(mac, fw, fwsize);
+ if (status != HALMAC_RET_SUCCESS) {
+ RTW_ERR("%s: download firmware FAIL! status=0x%02x\n",
+ __FUNCTION__, status);
+ _debug_dlfw_fail(d);
+ err = -1;
+ goto resume_tx;
+ }
- halmac = dvobj_to_halmac(d);
- if (!halmac)
- goto out;
+ /* 5.1. (Driver) Reset driver variables if needed */
+ hal->LastHMEBoxNum = 0;
- api = HALMAC_GET_API(halmac);
+ /* 5.2. (Driver) Get FW version */
+ status = api->halmac_get_fw_version(mac, &fw_vesion);
+ if (status == HALMAC_RET_SUCCESS) {
+ hal->firmware_version = fw_vesion.version;
+ hal->firmware_sub_version = fw_vesion.sub_version;
+ hal->firmware_size = fwsize;
+ }
- status = api->halmac_mac_power_switch(halmac, HALMAC_MAC_POWER_OFF);
- if (status != HALMAC_RET_SUCCESS)
- goto out;
+resume_tx:
+ /* 6. Driver resume TX if needed */
+ /* ToDo */
- err = 0;
-out:
- return err;
-}
+ if (err)
+ goto exit;
-/*
- * Note:
- * When this function return, the register REG_RCR may be changed.
- */
-int rtw_halmac_config_rx_info(struct dvobj_priv *d, HALMAC_DRV_INFO info)
-{
- PHALMAC_ADAPTER halmac;
- PHALMAC_API api;
- HALMAC_RET_STATUS status;
- int err = -1;
+ if (re_dl) {
+ enum halmac_trx_mode mode;
+ /* 7. Change reserved page size */
+ err = _cfg_drv_rsvd_pg_num(d);
+ if (err)
+ return -1;
- halmac = dvobj_to_halmac(d);
- api = HALMAC_GET_API(halmac);
+ /* 8. Init TRX Configuration */
+ mode = _choose_trx_mode(d);
+ status = api->halmac_init_trx_cfg(mac, mode);
+ if (HALMAC_RET_SUCCESS != status)
+ return -1;
- status = api->halmac_cfg_drv_info(halmac, info);
- if (status != HALMAC_RET_SUCCESS)
- goto out;
+ /* 9. Config RX Aggregation */
+ err = rtw_halmac_rx_agg_switch(d, _TRUE);
+ if (err)
+ return -1;
- err = 0;
-out:
+ /* 10. Send General Info */
+ err = _send_general_info(d);
+ if (err)
+ return -1;
+ }
+
+exit:
return err;
}
-static HALMAC_RET_STATUS init_mac_flow(struct dvobj_priv *d)
+static int init_mac_flow(struct dvobj_priv *d)
{
PADAPTER p;
- PHALMAC_ADAPTER halmac;
- PHALMAC_API api;
- HALMAC_WLAN_ADDR hwa;
- HALMAC_RET_STATUS status;
- u8 wifi_test = 0;
+ struct hal_com_data *hal;
+ struct halmac_adapter *halmac;
+ struct halmac_api *api;
+ enum halmac_drv_rsvd_pg_num rsvd_page_number;
+ union halmac_wlan_addr hwa;
+ enum halmac_trx_mode trx_mode;
+ enum halmac_ret_status status;
+ u8 drv_rsvd_num;
u8 nettype;
- int err;
+ int err, err_ret = -1;
- p = d->padapters[IFACE_ID0];
+ p = dvobj_get_primary_adapter(d);
+ hal = GET_HAL_DATA(p);
halmac = dvobj_to_halmac(d);
api = HALMAC_GET_API(halmac);
- if (p->registrypriv.wifi_spec)
- wifi_test = 1;
+
+#ifdef CONFIG_SUPPORT_TRX_SHARED
+ status = api->halmac_cfg_rxff_expand_mode(halmac,
+ _rtw_get_trx_share_mode(p));
+ if (status != HALMAC_RET_SUCCESS)
+ goto out;
+#endif
+
+#if 0 /* It is not necessary to call this in normal driver */
+ status = api->halmac_cfg_la_mode(halmac, HALMAC_LA_MODE_DISABLE);
+ if (status != HALMAC_RET_SUCCESS)
+ goto out;
+#endif
+
+ err = _cfg_drv_rsvd_pg_num(d);
+ if (err)
+ goto out;
#ifdef CONFIG_USB_HCI
status = api->halmac_set_bulkout_num(halmac, d->RtNumOutPipes);
@@ -936,10 +3086,8 @@ static HALMAC_RET_STATUS init_mac_flow(struct dvobj_priv *d)
goto out;
#endif /* CONFIG_USB_HCI */
- if (wifi_test)
- status = api->halmac_init_mac_cfg(halmac, HALMAC_TRX_MODE_WMM);
- else
- status = api->halmac_init_mac_cfg(halmac, HALMAC_TRX_MODE_NORMAL);
+ trx_mode = _choose_trx_mode(d);
+ status = api->halmac_init_mac_cfg(halmac, trx_mode);
if (status != HALMAC_RET_SUCCESS)
goto out;
@@ -948,9 +3096,9 @@ static HALMAC_RET_STATUS init_mac_flow(struct dvobj_priv *d)
goto out;
nettype = dvobj_to_regsty(d)->wireless_mode;
- if (IsSupportedVHT(nettype) == _TRUE)
+ if (is_supported_vht(nettype) == _TRUE)
status = api->halmac_cfg_operation_mode(halmac, HALMAC_WIRELESS_MODE_AC);
- else if (IsSupportedHT(nettype) == _TRUE)
+ else if (is_supported_ht(nettype) == _TRUE)
status = api->halmac_cfg_operation_mode(halmac, HALMAC_WIRELESS_MODE_N);
else if (IsSupportedTxOFDM(nettype) == _TRUE)
status = api->halmac_cfg_operation_mode(halmac, HALMAC_WIRELESS_MODE_G);
@@ -959,85 +3107,27 @@ static HALMAC_RET_STATUS init_mac_flow(struct dvobj_priv *d)
if (status != HALMAC_RET_SUCCESS)
goto out;
+ err_ret = 0;
out:
- return status;
+ return err_ret;
}
-static inline HALMAC_RF_TYPE _rf_type_drv2halmac(RT_RF_TYPE_DEF_E rf_drv)
+static int _drv_enable_trx(struct dvobj_priv *d)
{
- HALMAC_RF_TYPE rf_mac;
+ struct _ADAPTER *adapter;
+ u32 status;
- switch (rf_drv) {
- case RF_1T2R:
- rf_mac = HALMAC_RF_1T2R;
- break;
- case RF_2T4R:
- rf_mac = HALMAC_RF_2T4R;
- break;
- case RF_2T2R:
- rf_mac = HALMAC_RF_2T2R;
- break;
- case RF_1T1R:
- rf_mac = HALMAC_RF_1T1R;
- break;
- case RF_2T2R_GREEN:
- rf_mac = HALMAC_RF_2T2R_GREEN;
- break;
- case RF_2T3R:
- rf_mac = HALMAC_RF_2T3R;
- break;
- case RF_3T3R:
- rf_mac = HALMAC_RF_3T3R;
- break;
- case RF_3T4R:
- rf_mac = HALMAC_RF_3T4R;
- break;
- case RF_4T4R:
- rf_mac = HALMAC_RF_4T4R;
- break;
- default:
- rf_mac = (HALMAC_RF_TYPE)rf_drv;
- break;
+ adapter = dvobj_get_primary_adapter(d);
+ if (adapter->bup == _FALSE) {
+ status = rtw_start_drv_threads(adapter);
+ if (status == _FAIL) {
+ RTW_ERR("%s: Start threads Failed!\n", __FUNCTION__);
+ return -1;
+ }
}
- return rf_mac;
-}
-
-static int _send_general_info(struct dvobj_priv *d)
-{
- PADAPTER adapter;
- PHAL_DATA_TYPE hal;
- PHALMAC_ADAPTER halmac;
- PHALMAC_API api;
- HALMAC_GENERAL_INFO info;
- HALMAC_RET_STATUS status;
- u8 val8;
-
-
- adapter = d->padapters[IFACE_ID0];
- hal = GET_HAL_DATA(adapter);
- halmac = dvobj_to_halmac(d);
- if (!halmac)
- return -1;
- api = HALMAC_GET_API(halmac);
-
- _rtw_memset(&info, 0, sizeof(info));
- info.rfe_type = (u8)hal->RFEType;
- rtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, &val8);
- info.rf_type = _rf_type_drv2halmac(val8);
-
- status = api->halmac_send_general_info(halmac, &info);
- switch (status) {
- case HALMAC_RET_SUCCESS:
- break;
- case HALMAC_RET_NO_DLFW:
- RTW_WARN("%s: halmac_send_general_info() fail because fw not dl!\n",
- __FUNCTION__);
- /* go through */
- default:
- return -1;
- }
+ rtw_intf_start(adapter);
return 0;
}
@@ -1052,15 +3142,15 @@ static int _send_general_info(struct dvobj_priv *d)
static int _halmac_init_hal(struct dvobj_priv *d, u8 *fw, u32 fwsize)
{
PADAPTER adapter;
- PHALMAC_ADAPTER halmac;
- PHALMAC_API api;
- HALMAC_RET_STATUS status;
- u32 ok = _TRUE;
+ struct halmac_adapter *halmac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
+ u32 ok;
u8 fw_ok = _FALSE;
int err, err_ret = -1;
- adapter = d->padapters[IFACE_ID0];
+ adapter = dvobj_get_primary_adapter(d);
halmac = dvobj_to_halmac(d);
if (!halmac)
goto out;
@@ -1074,33 +3164,35 @@ static int _halmac_init_hal(struct dvobj_priv *d, u8 *fw, u32 fwsize)
/* halmac_mac_power_switch(on) */
/* halmac_Init_system_cfg */
ok = rtw_hal_power_on(adapter);
- if (_FALSE == ok)
+ if (_FAIL == ok)
goto out;
/* StatePowerOn */
/* DownloadFW */
- d->hmpriv.send_general_info = 0;
if (fw && fwsize) {
- err = rtw_halmac_dlfw(d, fw, fwsize);
+ err = download_fw(d, fw, fwsize, 0);
if (err)
goto out;
fw_ok = _TRUE;
}
/* InitMACFlow */
- status = init_mac_flow(d);
- if (status != HALMAC_RET_SUCCESS)
+ err = init_mac_flow(d);
+ if (err)
+ goto out;
+
+ /* Driver insert flow: Enable TR/RX */
+ err = _drv_enable_trx(d);
+ if (err)
goto out;
/* halmac_send_general_info */
if (_TRUE == fw_ok) {
- d->hmpriv.send_general_info = 0;
err = _send_general_info(d);
if (err)
goto out;
- } else
- d->hmpriv.send_general_info = 1;
+ }
/* Init Phy parameter-MAC */
ok = rtw_hal_init_mac_register(adapter);
@@ -1161,11 +3253,16 @@ int rtw_halmac_init_hal_fw(struct dvobj_priv *d, u8 *fw, u32 fwsize)
int rtw_halmac_init_hal_fw_file(struct dvobj_priv *d, u8 *fwpath)
{
u8 *fw = NULL;
- u32 fwmaxsize, size = 0;
+ u32 fwmaxsize = 0, size = 0;
int err = 0;
- fwmaxsize = FIRMWARE_MAX_SIZE;
+ err = rtw_halmac_get_fw_max_size(d, &fwmaxsize);
+ if (err) {
+ RTW_ERR("%s: Fail to get Firmware MAX size(err=%d)\n", __FUNCTION__, err);
+ return -1;
+ }
+
fw = rtw_zmalloc(fwmaxsize);
if (!fw)
return -1;
@@ -1180,7 +3277,7 @@ int rtw_halmac_init_hal_fw_file(struct dvobj_priv *d, u8 *fwpath)
exit:
rtw_mfree(fw, fwmaxsize);
- fw = NULL;
+ /*fw = NULL;*/
return err;
}
@@ -1188,13 +3285,13 @@ int rtw_halmac_init_hal_fw_file(struct dvobj_priv *d, u8 *fwpath)
int rtw_halmac_deinit_hal(struct dvobj_priv *d)
{
PADAPTER adapter;
- PHALMAC_ADAPTER halmac;
- PHALMAC_API api;
- HALMAC_RET_STATUS status;
+ struct halmac_adapter *halmac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
int err = -1;
- adapter = d->padapters[IFACE_ID0];
+ adapter = dvobj_get_primary_adapter(d);
halmac = dvobj_to_halmac(d);
if (!halmac)
goto out;
@@ -1213,9 +3310,9 @@ int rtw_halmac_deinit_hal(struct dvobj_priv *d)
int rtw_halmac_self_verify(struct dvobj_priv *d)
{
- PHALMAC_ADAPTER mac;
- PHALMAC_API api;
- HALMAC_RET_STATUS status;
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
int err = -1;
@@ -1226,82 +3323,262 @@ int rtw_halmac_self_verify(struct dvobj_priv *d)
if (status != HALMAC_RET_SUCCESS)
goto out;
- status = api->halmac_h2c_lb(mac);
- if (status != HALMAC_RET_SUCCESS)
- goto out;
+ status = api->halmac_h2c_lb(mac);
+ if (status != HALMAC_RET_SUCCESS)
+ goto out;
+
+ err = 0;
+out:
+ return err;
+}
+
+static u8 rtw_halmac_txfifo_is_empty(struct dvobj_priv *d)
+{
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
+ u32 chk_num = 10;
+ u8 rst = _FALSE;
+
+
+ mac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(mac);
+
+ status = api->halmac_txfifo_is_empty(mac, chk_num);
+ if (status == HALMAC_RET_SUCCESS)
+ rst = _TRUE;
+
+ return rst;
+}
+
+/**
+ * rtw_halmac_txfifo_wait_empty() - Wait TX FIFO to be emtpy
+ * @d: struct dvobj_priv*
+ * @timeout: time limit of wait, unit is ms
+ * 0 for no limit
+ *
+ * Wait TX FIFO to be emtpy.
+ *
+ * Rteurn 0 for TX FIFO is empty, otherwise not empty.
+ */
+int rtw_halmac_txfifo_wait_empty(struct dvobj_priv *d, u32 timeout)
+{
+ struct _ADAPTER *a;
+ u8 empty = _FALSE;
+ u32 cnt = 0;
+ systime start_time = 0;
+ u32 pass_time; /* ms */
+
+
+ a = dvobj_get_primary_adapter(d);
+ start_time = rtw_get_current_time();
+
+ do {
+ cnt++;
+ empty = rtw_halmac_txfifo_is_empty(d);
+ if (empty == _TRUE)
+ break;
+
+ if (timeout) {
+ pass_time = rtw_get_passing_time_ms(start_time);
+ if (pass_time > timeout)
+ break;
+ }
+ if (RTW_CANNOT_IO(a)) {
+ RTW_WARN("%s: Interrupted by I/O forbiden!\n", __FUNCTION__);
+ break;
+ }
+
+ rtw_msleep_os(2);
+ } while (1);
+
+ if (empty == _FALSE) {
+#ifdef CONFIG_RTW_DEBUG
+ u16 dbg_reg[] = {0x210, 0x230, 0x234, 0x238, 0x23C, 0x240,
+ 0x41A, 0x10FC, 0x10F8, 0x11F4, 0x11F8};
+ u8 i;
+ u32 val;
+
+ if (!RTW_CANNOT_IO(a)) {
+ for (i = 0; i < ARRAY_SIZE(dbg_reg); i++) {
+ val = rtw_read32(a, dbg_reg[i]);
+ RTW_ERR("REG_%X:0x%08x\n", dbg_reg[i], val);
+ }
+ }
+#endif /* CONFIG_RTW_DEBUG */
+
+ RTW_ERR("%s: Fail to wait txfifo empty!(cnt=%d)\n",
+ __FUNCTION__, cnt);
+ return -1;
+ }
+
+ return 0;
+}
+
+static enum halmac_dlfw_mem _fw_mem_drv2halmac(enum fw_mem mem, u8 tx_stop)
+{
+ enum halmac_dlfw_mem mem_halmac = HALMAC_DLFW_MEM_UNDEFINE;
+
+
+ switch (mem) {
+ case FW_EMEM:
+ if (tx_stop == _FALSE)
+ mem_halmac = HALMAC_DLFW_MEM_EMEM_RSVD_PG;
+ else
+ mem_halmac = HALMAC_DLFW_MEM_EMEM;
+ break;
+
+ case FW_IMEM:
+ case FW_DMEM:
+ mem_halmac = HALMAC_DLFW_MEM_UNDEFINE;
+ break;
+ }
+
+ return mem_halmac;
+}
+
+int rtw_halmac_dlfw_mem(struct dvobj_priv *d, u8 *fw, u32 fwsize, enum fw_mem mem)
+{
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
+ enum halmac_dlfw_mem dlfw_mem;
+ u8 tx_stop = _FALSE;
+ u32 chk_timeout = 2000; /* unit: ms */
+ int err = 0;
+
+
+ mac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(mac);
+
+ if ((!fw) || (!fwsize))
+ return -1;
+
+#ifndef RTW_HALMAC_DLFW_MEM_NO_STOP_TX
+ /* 1. Driver Stop Tx */
+ /* ToDo */
+
+ /* 2. Driver Check Tx FIFO is empty */
+ err = rtw_halmac_txfifo_wait_empty(d, chk_timeout);
+ if (err)
+ tx_stop = _FALSE;
+ else
+ tx_stop = _TRUE;
+#endif /* !RTW_HALMAC_DLFW_MEM_NO_STOP_TX */
+
+ /* 3. Download Firmware MEM */
+ dlfw_mem = _fw_mem_drv2halmac(mem, tx_stop);
+ if (dlfw_mem == HALMAC_DLFW_MEM_UNDEFINE) {
+ err = -1;
+ goto resume_tx;
+ }
+ status = api->halmac_free_download_firmware(mac, dlfw_mem, fw, fwsize);
+ if (status != HALMAC_RET_SUCCESS) {
+ RTW_ERR("%s: halmac_free_download_firmware fail(err=0x%x)\n",
+ __FUNCTION__, status);
+ err = -1;
+ goto resume_tx;
+ }
+
+resume_tx:
+#ifndef RTW_HALMAC_DLFW_MEM_NO_STOP_TX
+ /* 4. Driver resume TX if needed */
+ /* ToDo */
+#endif /* !RTW_HALMAC_DLFW_MEM_NO_STOP_TX */
+
+ return err;
+}
+
+int rtw_halmac_dlfw_mem_from_file(struct dvobj_priv *d, u8 *fwpath, enum fw_mem mem)
+{
+ u8 *fw = NULL;
+ u32 fwmaxsize = 0, size = 0;
+ int err = 0;
+
+
+ err = rtw_halmac_get_fw_max_size(d, &fwmaxsize);
+ if (err) {
+ RTW_ERR("%s: Fail to get Firmware MAX size(err=%d)\n", __FUNCTION__, err);
+ return -1;
+ }
+
+ fw = rtw_zmalloc(fwmaxsize);
+ if (!fw)
+ return -1;
+
+ size = rtw_retrieve_from_file(fwpath, fw, fwmaxsize);
+ if (size)
+ err = rtw_halmac_dlfw_mem(d, fw, size, mem);
+ else
+ err = -1;
+
+ rtw_mfree(fw, fwmaxsize);
+ /*fw = NULL;*/
- err = 0;
-out:
return err;
}
+/*
+ * Return:
+ * 0 Success
+ * -22 Invalid arguemnt
+ */
int rtw_halmac_dlfw(struct dvobj_priv *d, u8 *fw, u32 fwsize)
{
- PHALMAC_ADAPTER mac;
- PHALMAC_API api;
- HALMAC_RET_STATUS status;
- int err = 0;
- PHAL_DATA_TYPE hal;
- HALMAC_FW_VERSION fw_vesion;
-
-
- mac = dvobj_to_halmac(d);
- api = HALMAC_GET_API(mac);
- hal = GET_HAL_DATA(d->padapters[IFACE_ID0]);
+ PADAPTER adapter;
+ enum halmac_ret_status status;
+ u32 ok;
+ int err, err_ret = -1;
- if ((!fw) || (!fwsize))
- return -1;
- /* 1. Driver Stop Tx */
- /* ToDo */
+ if (!fw || !fwsize)
+ return -22;
- /* 2. Driver Check Tx FIFO is empty */
- /* ToDo */
+ adapter = dvobj_get_primary_adapter(d);
- /* 3. Config MAX download size */
-#ifdef CONFIG_USB_HCI
- /* for USB do not exceed MAX_CMDBUF_SZ */
- api->halmac_cfg_max_dl_size(mac, 0x1000);
-#elif defined CONFIG_PCIE_HCI
- /* required a even length from u32 */
- api->halmac_cfg_max_dl_size(mac, (MAX_CMDBUF_SZ - TXDESC_OFFSET) & 0xFFFFFFFE);
-#endif
+ /* re-download firmware */
+ if (rtw_is_hw_init_completed(adapter))
+ return download_fw(d, fw, fwsize, 1);
- /* 4. Download Firmware */
- status = api->halmac_download_firmware(mac, fw, fwsize);
- if (HALMAC_RET_SUCCESS != status)
- return -1;
+ /* Download firmware before hal init */
+ /* Power on, download firmware and init mac */
+ ok = rtw_hal_power_on(adapter);
+ if (_FAIL == ok)
+ goto out;
- if (d->hmpriv.send_general_info) {
- d->hmpriv.send_general_info = 0;
- err = _send_general_info(d);
+ err = download_fw(d, fw, fwsize, 0);
+ if (err) {
+ err_ret = err;
+ goto out;
}
- /* 5. Driver resume TX if needed */
- /* ToDo */
-
- /* 6. Reset driver variables if needed */
- hal->LastHMEBoxNum = 0;
+ err = init_mac_flow(d);
+ if (err)
+ goto out;
+ err = _send_general_info(d);
+ if (err)
+ goto out;
- /* 7. Get FW version */
- status = api->halmac_get_fw_version(mac, &fw_vesion);
- if (status == HALMAC_RET_SUCCESS) {
- hal->FirmwareVersion = fw_vesion.version;
- hal->FirmwareSubVersion = fw_vesion.sub_version;
- }
+ err_ret = 0;
- return err;
+out:
+ return err_ret;
}
int rtw_halmac_dlfw_from_file(struct dvobj_priv *d, u8 *fwpath)
{
u8 *fw = NULL;
- u32 fwmaxsize, size = 0;
+ u32 fwmaxsize = 0, size = 0;
int err = 0;
- fwmaxsize = FIRMWARE_MAX_SIZE;
+ err = rtw_halmac_get_fw_max_size(d, &fwmaxsize);
+ if (err) {
+ RTW_ERR("%s: Fail to get Firmware MAX size(err=%d)\n", __FUNCTION__, err);
+ return -1;
+ }
+
fw = rtw_zmalloc(fwmaxsize);
if (!fw)
return -1;
@@ -1313,7 +3590,7 @@ int rtw_halmac_dlfw_from_file(struct dvobj_priv *d, u8 *fwpath)
err = -1;
rtw_mfree(fw, fwmaxsize);
- fw = NULL;
+ /*fw = NULL;*/
return err;
}
@@ -1332,12 +3609,12 @@ int rtw_halmac_dlfw_from_file(struct dvobj_priv *d, u8 *fwpath)
int rtw_halmac_phy_power_switch(struct dvobj_priv *d, u8 enable)
{
PADAPTER adapter;
- PHALMAC_ADAPTER halmac;
- PHALMAC_API api;
- HALMAC_RET_STATUS status;
+ struct halmac_adapter *halmac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
- adapter = d->padapters[IFACE_ID0];
+ adapter = dvobj_get_primary_adapter(d);
halmac = dvobj_to_halmac(d);
if (!halmac)
return -1;
@@ -1356,8 +3633,6 @@ static u8 _is_fw_read_cmd_down(PADAPTER adapter, u8 msgbox_num)
int retry_cnts = 100;
u8 valid;
- /* RTW_INFO("_is_fw_read_cmd_down, reg_1cc(%x), msg_box(%d)...\n", rtw_read8(adapter, REG_HMETFR), msgbox_num); */
-
do {
valid = rtw_read8(adapter, REG_HMETFR) & BIT(msgbox_num);
if (0 == valid)
@@ -1366,52 +3641,68 @@ static u8 _is_fw_read_cmd_down(PADAPTER adapter, u8 msgbox_num)
rtw_msleep_os(1);
} while ((!read_down) && (retry_cnts--));
+ if (_FALSE == read_down)
+ RTW_WARN("%s, reg_1cc(%x), msg_box(%d)...\n", __func__, rtw_read8(adapter, REG_HMETFR), msgbox_num);
+
return read_down;
}
+/**
+ * rtw_halmac_send_h2c() - Send H2C to firmware
+ * @d: struct dvobj_priv*
+ * @h2c: H2C data buffer, suppose to be 8 bytes
+ *
+ * Send H2C to firmware by message box register(0x1D0~0x1D3 & 0x1F0~0x1F3).
+ *
+ * Assume firmware be ready to accept H2C here, please check
+ * (hal->bFWReady == _TRUE) before call this function or make sure firmware is
+ * ready.
+ *
+ * Return: 0 if process OK, otherwise fail to send this H2C.
+ */
int rtw_halmac_send_h2c(struct dvobj_priv *d, u8 *h2c)
{
- PADAPTER adapter = d->padapters[IFACE_ID0];
+ PADAPTER adapter = dvobj_get_primary_adapter(d);
PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
u8 h2c_box_num = 0;
u32 msgbox_addr = 0;
u32 msgbox_ex_addr = 0;
u32 h2c_cmd = 0;
u32 h2c_cmd_ex = 0;
- s32 ret = _FAIL;
+ int err = -1;
- if (adapter->bFWReady == _FALSE) {
- RTW_INFO("%s: return H2C cmd because fw is not ready\n", __FUNCTION__);
- return ret;
- }
if (!h2c) {
- RTW_INFO("%s: pbuf is NULL\n", __FUNCTION__);
- return ret;
+ RTW_WARN("%s: pbuf is NULL\n", __FUNCTION__);
+ return err;
}
if (rtw_is_surprise_removed(adapter)) {
- RTW_INFO("%s: surprise removed\n", __FUNCTION__);
- return ret;
+ RTW_WARN("%s: surprise removed\n", __FUNCTION__);
+ return err;
}
_enter_critical_mutex(&d->h2c_fwcmd_mutex, NULL);
- /* pay attention to if race condition happened in H2C cmd setting */
+ /* pay attention to if race condition happened in H2C cmd setting */
h2c_box_num = hal->LastHMEBoxNum;
if (!_is_fw_read_cmd_down(adapter, h2c_box_num)) {
- RTW_INFO(" fw read cmd failed...\n");
+ RTW_WARN(" fw read cmd failed...\n");
+#ifdef DBG_CONFIG_ERROR_DETECT
+ hal->srestpriv.self_dect_fw = _TRUE;
+ hal->srestpriv.self_dect_fw_cnt++;
+#endif /* DBG_CONFIG_ERROR_DETECT */
goto exit;
}
- /* Write Ext command(byte 4 -7) */
+ /* Write Ext command (byte 4~7) */
msgbox_ex_addr = REG_HMEBOX_E0 + (h2c_box_num * EX_MESSAGE_BOX_SIZE);
_rtw_memcpy((u8 *)(&h2c_cmd_ex), h2c + 4, EX_MESSAGE_BOX_SIZE);
h2c_cmd_ex = le32_to_cpu(h2c_cmd_ex);
rtw_write32(adapter, msgbox_ex_addr, h2c_cmd_ex);
- /* Write command (byte 0 -3 ) */
+ /* Write command (byte 0~3) */
msgbox_addr = REG_HMEBOX0 + (h2c_box_num * MESSAGE_BOX_SIZE);
_rtw_memcpy((u8 *)(&h2c_cmd), h2c, 4);
h2c_cmd = le32_to_cpu(h2c_cmd);
@@ -1419,18 +3710,36 @@ int rtw_halmac_send_h2c(struct dvobj_priv *d, u8 *h2c)
/* update last msg box number */
hal->LastHMEBoxNum = (h2c_box_num + 1) % MAX_H2C_BOX_NUMS;
- ret = _SUCCESS;
+ err = 0;
+#ifdef DBG_H2C_CONTENT
+ RTW_INFO_DUMP("[H2C] - ", h2c, RTW_HALMAC_H2C_MAX_SIZE);
+#endif
exit:
_exit_critical_mutex(&d->h2c_fwcmd_mutex, NULL);
- return ret;
+ return err;
}
+/**
+ * rtw_halmac_c2h_handle() - Handle C2H for HALMAC
+ * @d: struct dvobj_priv*
+ * @c2h: Full C2H packet, including RX description and payload
+ * @size: Size(byte) of c2h
+ *
+ * Send C2H packet to HALMAC to process C2H packets, and the expected C2H ID is
+ * 0xFF. This function won't have any I/O, so caller doesn't have to call it in
+ * I/O safe place(ex. command thread).
+ *
+ * Please sure doesn't call this function in the same thread as someone is
+ * waiting HALMAC C2H ack, otherwise there is a deadlock happen.
+ *
+ * Return: 0 if process OK, otherwise no action for this C2H.
+ */
int rtw_halmac_c2h_handle(struct dvobj_priv *d, u8 *c2h, u32 size)
{
- PHALMAC_ADAPTER mac;
- PHALMAC_API api;
- HALMAC_RET_STATUS status;
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
mac = dvobj_to_halmac(d);
@@ -1443,11 +3752,30 @@ int rtw_halmac_c2h_handle(struct dvobj_priv *d, u8 *c2h, u32 size)
return 0;
}
+int rtw_halmac_get_available_efuse_size(struct dvobj_priv *d, u32 *size)
+{
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
+ u32 val;
+
+
+ mac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(mac);
+
+ status = api->halmac_get_efuse_available_size(mac, &val);
+ if (HALMAC_RET_SUCCESS != status)
+ return -1;
+
+ *size = val;
+ return 0;
+}
+
int rtw_halmac_get_physical_efuse_size(struct dvobj_priv *d, u32 *size)
{
- PHALMAC_ADAPTER mac;
- PHALMAC_API api;
- HALMAC_RET_STATUS status;
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
u32 val;
@@ -1464,10 +3792,10 @@ int rtw_halmac_get_physical_efuse_size(struct dvobj_priv *d, u32 *size)
int rtw_halmac_read_physical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size)
{
- PHALMAC_ADAPTER mac;
- PHALMAC_API api;
- HALMAC_RET_STATUS status;
- HALMAC_FEATURE_ID id;
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
+ enum halmac_feature_id id;
int ret;
@@ -1479,7 +3807,7 @@ int rtw_halmac_read_physical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size)
if (ret)
return -1;
- status = api->halmac_dump_efuse_map(mac, HALMAC_EFUSE_R_AUTO);
+ status = api->halmac_dump_efuse_map(mac, HALMAC_EFUSE_R_DRV);
if (HALMAC_RET_SUCCESS != status) {
free_halmac_event(d, id);
return -1;
@@ -1494,37 +3822,61 @@ int rtw_halmac_read_physical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size)
int rtw_halmac_read_physical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data)
{
- PHALMAC_ADAPTER mac;
- PHALMAC_API api;
- HALMAC_RET_STATUS status;
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
u8 v;
u32 i;
+ u8 *efuse = NULL;
+ u32 size = 0;
+ int err = 0;
mac = dvobj_to_halmac(d);
api = HALMAC_GET_API(mac);
- for (i = 0; i < cnt; i++) {
- status = api->halmac_read_efuse(mac, offset + i, &v);
- if (HALMAC_RET_SUCCESS != status)
+ if (api->halmac_read_efuse) {
+ for (i = 0; i < cnt; i++) {
+ status = api->halmac_read_efuse(mac, offset + i, &v);
+ if (HALMAC_RET_SUCCESS != status)
+ return -1;
+ data[i] = v;
+ }
+ } else {
+ err = rtw_halmac_get_physical_efuse_size(d, &size);
+ if (err)
return -1;
- data[i] = v;
+
+ efuse = rtw_zmalloc(size);
+ if (!efuse)
+ return -1;
+
+ err = rtw_halmac_read_physical_efuse_map(d, efuse, size);
+ if (err)
+ err = -1;
+ else
+ _rtw_memcpy(data, efuse + offset, cnt);
+
+ rtw_mfree(efuse, size);
}
- return 0;
+ return err;
}
int rtw_halmac_write_physical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data)
{
- PHALMAC_ADAPTER mac;
- PHALMAC_API api;
- HALMAC_RET_STATUS status;
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
u32 i;
mac = dvobj_to_halmac(d);
api = HALMAC_GET_API(mac);
+ if (api->halmac_write_efuse == NULL)
+ return -1;
+
for (i = 0; i < cnt; i++) {
status = api->halmac_write_efuse(mac, offset + i, data[i]);
if (HALMAC_RET_SUCCESS != status)
@@ -1536,9 +3888,9 @@ int rtw_halmac_write_physical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u
int rtw_halmac_get_logical_efuse_size(struct dvobj_priv *d, u32 *size)
{
- PHALMAC_ADAPTER mac;
- PHALMAC_API api;
- HALMAC_RET_STATUS status;
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
u32 val;
@@ -1553,12 +3905,12 @@ int rtw_halmac_get_logical_efuse_size(struct dvobj_priv *d, u32 *size)
return 0;
}
-int rtw_halmac_read_logical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size)
+int rtw_halmac_read_logical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size, u8 *maskmap, u32 masksize)
{
- PHALMAC_ADAPTER mac;
- PHALMAC_API api;
- HALMAC_RET_STATUS status;
- HALMAC_FEATURE_ID id;
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
+ enum halmac_feature_id id;
int ret;
@@ -1570,7 +3922,7 @@ int rtw_halmac_read_logical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size)
if (ret)
return -1;
- status = api->halmac_dump_logical_efuse_map(mac, HALMAC_EFUSE_R_AUTO);
+ status = api->halmac_dump_logical_efuse_map(mac, HALMAC_EFUSE_R_DRV);
if (HALMAC_RET_SUCCESS != status) {
free_halmac_event(d, id);
return -1;
@@ -1580,23 +3932,36 @@ int rtw_halmac_read_logical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size)
if (ret)
return -1;
+ if (maskmap && masksize) {
+ struct halmac_pg_efuse_info pginfo;
+
+ pginfo.efuse_map = map;
+ pginfo.efuse_map_size = size;
+ pginfo.efuse_mask = maskmap;
+ pginfo.efuse_mask_size = masksize;
+
+ status = api->halmac_mask_logical_efuse(mac, &pginfo);
+ if (status != HALMAC_RET_SUCCESS)
+ RTW_WARN("%s: mask logical efuse FAIL!\n", __FUNCTION__);
+ }
+
return 0;
}
int rtw_halmac_write_logical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size, u8 *maskmap, u32 masksize)
{
- PHALMAC_ADAPTER mac;
- PHALMAC_API api;
- HALMAC_PG_EFUSE_INFO pginfo;
- HALMAC_RET_STATUS status;
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ struct halmac_pg_efuse_info pginfo;
+ enum halmac_ret_status status;
mac = dvobj_to_halmac(d);
api = HALMAC_GET_API(mac);
- pginfo.pEfuse_map = map;
+ pginfo.efuse_map = map;
pginfo.efuse_map_size = size;
- pginfo.pEfuse_mask = maskmap;
+ pginfo.efuse_mask = maskmap;
pginfo.efuse_mask_size = masksize;
status = api->halmac_pg_efuse_by_map(mac, &pginfo, HALMAC_EFUSE_R_AUTO);
@@ -1608,9 +3973,9 @@ int rtw_halmac_write_logical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size,
int rtw_halmac_read_logical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data)
{
- PHALMAC_ADAPTER mac;
- PHALMAC_API api;
- HALMAC_RET_STATUS status;
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
u8 v;
u32 i;
@@ -1630,9 +3995,9 @@ int rtw_halmac_read_logical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8
int rtw_halmac_write_logical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data)
{
- PHALMAC_ADAPTER mac;
- PHALMAC_API api;
- HALMAC_RET_STATUS status;
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
u32 i;
@@ -1650,12 +4015,13 @@ int rtw_halmac_write_logical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8
int rtw_halmac_write_bt_physical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data)
{
- PHALMAC_ADAPTER mac;
- PHALMAC_API api;
- HALMAC_RET_STATUS status;
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
u32 i;
u8 bank = 1;
+
mac = dvobj_to_halmac(d);
api = HALMAC_GET_API(mac);
@@ -1673,18 +4039,17 @@ int rtw_halmac_write_bt_physical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt
int rtw_halmac_read_bt_physical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size)
{
- PHALMAC_ADAPTER mac;
- PHALMAC_API api;
- HALMAC_RET_STATUS status;
- HALMAC_FEATURE_ID id;
- int ret;
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
int bank = 1;
+
mac = dvobj_to_halmac(d);
api = HALMAC_GET_API(mac);
status = api->halmac_dump_efuse_map_bt(mac, bank, size, map);
- if (HALMAC_RET_SUCCESS != status) {
+ if (HALMAC_RET_SUCCESS != status) {
printk("%s: halmac_dump_efuse_map_bt fail!\n", __FUNCTION__);
return -1;
}
@@ -1694,291 +4059,581 @@ int rtw_halmac_read_bt_physical_efuse_map(struct dvobj_priv *d, u8 *map, u32 siz
return 0;
}
-static inline u8 _hw_port_drv2halmac(enum _hw_port hwport)
+static enum hal_fifo_sel _fifo_sel_drv2halmac(u8 fifo_sel)
{
- u8 port = 0;
+ switch (fifo_sel) {
+ case 0:
+ return HAL_FIFO_SEL_TX;
+ case 1:
+ return HAL_FIFO_SEL_RX;
+ case 2:
+ return HAL_FIFO_SEL_RSVD_PAGE;
+ case 3:
+ return HAL_FIFO_SEL_REPORT;
+ case 4:
+ return HAL_FIFO_SEL_LLT;
+ case 5:
+ return HAL_FIFO_SEL_RXBUF_FW;
+ }
+ return HAL_FIFO_SEL_RSVD_PAGE;
+}
- switch (hwport) {
- case HW_PORT0:
- port = 0;
- break;
- case HW_PORT1:
- port = 1;
- break;
- case HW_PORT2:
- port = 2;
- break;
- case HW_PORT3:
- port = 3;
- break;
- case HW_PORT4:
- port = 4;
- break;
- default:
- port = hwport;
- break;
+/*#define CONFIG_HALMAC_FIFO_DUMP*/
+int rtw_halmac_dump_fifo(struct dvobj_priv *d, u8 fifo_sel, u32 addr, u32 size, u8 *buffer)
+{
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ enum hal_fifo_sel halmac_fifo_sel;
+ enum halmac_ret_status status;
+ u8 *pfifo_map = NULL;
+ u32 fifo_size = 0;
+ s8 ret = 0;/* 0:success, -1:error */
+ u8 mem_created = _FALSE;
+
+
+ mac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(mac);
+
+ if ((size != 0) && (buffer == NULL))
+ return -1;
+
+ halmac_fifo_sel = _fifo_sel_drv2halmac(fifo_sel);
+
+ if ((size) && (buffer)) {
+ pfifo_map = buffer;
+ fifo_size = size;
+ } else {
+ fifo_size = api->halmac_get_fifo_size(mac, halmac_fifo_sel);
+
+ if (fifo_size)
+ pfifo_map = rtw_zvmalloc(fifo_size);
+ if (pfifo_map == NULL)
+ return -1;
+ mem_created = _TRUE;
}
- return port;
+ status = api->halmac_dump_fifo(mac, halmac_fifo_sel, addr, fifo_size, pfifo_map);
+ if (HALMAC_RET_SUCCESS != status) {
+ ret = -1;
+ goto _exit;
+ }
+
+#ifdef CONFIG_HALMAC_FIFO_DUMP
+ {
+ static const char * const fifo_sel_str[] = {
+ "TX", "RX", "RSVD_PAGE", "REPORT", "LLT", "RXBUF_FW"
+ };
+
+ RTW_INFO("%s FIFO DUMP [start_addr:0x%04x , size:%d]\n", fifo_sel_str[halmac_fifo_sel], addr, fifo_size);
+ RTW_INFO_DUMP("\n", pfifo_map, fifo_size);
+ RTW_INFO(" ==================================================\n");
+ }
+#endif /* CONFIG_HALMAC_FIFO_DUMP */
+
+_exit:
+ if ((mem_created == _TRUE) && pfifo_map)
+ rtw_vmfree(pfifo_map, fifo_size);
+
+ return ret;
}
-int rtw_halmac_set_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr)
+/*
+ * rtw_halmac_rx_agg_switch() - Switch RX aggregation function and setting
+ * @d struct dvobj_priv *
+ * @enable 0/1 for disable/enable RX aggregation function
+ *
+ * This function could help to on/off bus RX aggregation function, and is only
+ * useful for SDIO and USB interface. Although only "enable" flag is brough in,
+ * some setting would be taken from other places, and they are from:
+ * [DMA aggregation]
+ * struct hal_com_data.rxagg_dma_size
+ * struct hal_com_data.rxagg_dma_timeout
+ * [USB aggregation] (only use for USB interface)
+ * struct hal_com_data.rxagg_usb_size
+ * struct hal_com_data.rxagg_usb_timeout
+ * If above values of size and timeout are both 0 means driver would not
+ * control the threshold setting and leave it to HALMAC handle.
+ *
+ * From HALMAC V1_04_04, driver force the size threshold be hard limit, and the
+ * rx size can not exceed the setting.
+ *
+ * Return 0 for success, otherwise fail.
+ */
+int rtw_halmac_rx_agg_switch(struct dvobj_priv *d, u8 enable)
{
- PHALMAC_ADAPTER halmac;
- PHALMAC_API api;
- u8 port;
- HALMAC_WLAN_ADDR hwa;
- HALMAC_RET_STATUS status;
- int err = -1;
+ struct _ADAPTER *adapter;
+ struct hal_com_data *hal;
+ struct halmac_adapter *halmac;
+ struct halmac_api *api;
+ struct halmac_rxagg_cfg rxaggcfg;
+ enum halmac_ret_status status;
+ adapter = dvobj_get_primary_adapter(d);
+ hal = GET_HAL_DATA(adapter);
halmac = dvobj_to_halmac(d);
api = HALMAC_GET_API(halmac);
+ _rtw_memset((void *)&rxaggcfg, 0, sizeof(rxaggcfg));
+ rxaggcfg.mode = HALMAC_RX_AGG_MODE_NONE;
+ /*
+ * Always enable size limit to avoid rx size exceed
+ * driver defined size.
+ */
+ rxaggcfg.threshold.size_limit_en = 1;
+
+#ifdef RTW_RX_AGGREGATION
+ if (_TRUE == enable) {
+#ifdef CONFIG_SDIO_HCI
+ rxaggcfg.mode = HALMAC_RX_AGG_MODE_DMA;
+ rxaggcfg.threshold.drv_define = 0;
+ if (hal->rxagg_dma_size || hal->rxagg_dma_timeout) {
+ rxaggcfg.threshold.drv_define = 1;
+ rxaggcfg.threshold.timeout = hal->rxagg_dma_timeout;
+ rxaggcfg.threshold.size = hal->rxagg_dma_size;
+ RTW_INFO("%s: RX aggregation threshold: "
+ "timeout=%u size=%u\n",
+ __FUNCTION__,
+ hal->rxagg_dma_timeout,
+ hal->rxagg_dma_size);
+ }
+#elif defined(CONFIG_USB_HCI)
+ switch (hal->rxagg_mode) {
+ case RX_AGG_DISABLE:
+ rxaggcfg.mode = HALMAC_RX_AGG_MODE_NONE;
+ break;
- port = _hw_port_drv2halmac(hwport);
- _rtw_memset(&hwa, 0, sizeof(hwa));
- _rtw_memcpy(hwa.Address, addr, 6);
+ case RX_AGG_DMA:
+ rxaggcfg.mode = HALMAC_RX_AGG_MODE_DMA;
+ if (hal->rxagg_dma_size || hal->rxagg_dma_timeout) {
+ rxaggcfg.threshold.drv_define = 1;
+ rxaggcfg.threshold.timeout = hal->rxagg_dma_timeout;
+ rxaggcfg.threshold.size = hal->rxagg_dma_size;
+ }
+ break;
- status = api->halmac_cfg_mac_addr(halmac, port, &hwa);
+ case RX_AGG_USB:
+ case RX_AGG_MIX:
+ rxaggcfg.mode = HALMAC_RX_AGG_MODE_USB;
+ if (hal->rxagg_usb_size || hal->rxagg_usb_timeout) {
+ rxaggcfg.threshold.drv_define = 1;
+ rxaggcfg.threshold.timeout = hal->rxagg_usb_timeout;
+ rxaggcfg.threshold.size = hal->rxagg_usb_size;
+ }
+ break;
+ }
+#endif /* CONFIG_USB_HCI */
+ }
+#endif /* RTW_RX_AGGREGATION */
+
+ status = api->halmac_cfg_rx_aggregation(halmac, &rxaggcfg);
if (status != HALMAC_RET_SUCCESS)
- goto out;
+ return -1;
- err = 0;
-out:
- return err;
+ return 0;
}
-int rtw_halmac_set_bssid(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr)
+int rtw_halmac_download_rsvd_page(struct dvobj_priv *dvobj, u8 pg_offset, u8 *pbuf, u32 size)
{
- PHALMAC_ADAPTER halmac;
- PHALMAC_API api;
- u8 port;
- HALMAC_WLAN_ADDR hwa;
- HALMAC_RET_STATUS status;
- int err = -1;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+ struct halmac_adapter *halmac = dvobj_to_halmac(dvobj);
+ struct halmac_api *api = HALMAC_GET_API(halmac);
- halmac = dvobj_to_halmac(d);
+ status = api->halmac_dl_drv_rsvd_page(halmac, pg_offset, pbuf, size);
+ if (status != HALMAC_RET_SUCCESS)
+ return -1;
+
+ return 0;
+}
+
+/*
+ * Description
+ * Fill following spec info from HALMAC API:
+ * sec_cam_ent_num
+ *
+ * Return
+ * 0 Success
+ * others Fail
+ */
+int rtw_halmac_fill_hal_spec(struct dvobj_priv *dvobj, struct hal_spec_t *spec)
+{
+ enum halmac_ret_status status;
+ struct halmac_adapter *halmac;
+ struct halmac_api *api;
+ u8 cam = 0; /* Security Cam Entry Number */
+
+
+ halmac = dvobj_to_halmac(dvobj);
api = HALMAC_GET_API(halmac);
- port = _hw_port_drv2halmac(hwport);
- _rtw_memset(&hwa, 0, sizeof(HALMAC_WLAN_ADDR));
- _rtw_memcpy(hwa.Address, addr, 6);
- status = api->halmac_cfg_bssid(halmac, port, &hwa);
+ /* Prepare data from HALMAC */
+ status = api->halmac_get_hw_value(halmac, HALMAC_HW_CAM_ENTRY_NUM, &cam);
if (status != HALMAC_RET_SUCCESS)
- goto out;
+ return -1;
- err = 0;
-out:
- return err;
+ /* Fill data to hal_spec_t */
+ spec->sec_cam_ent_num = cam;
+
+ return 0;
}
-int rtw_halmac_set_bandwidth(struct dvobj_priv *d, u8 channel, u8 pri_ch_idx, u8 bw)
+int rtw_halmac_p2pps(struct dvobj_priv *dvobj, struct hal_p2p_ps_para *pp2p_ps_para)
+{
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+ struct halmac_adapter *halmac = dvobj_to_halmac(dvobj);
+ struct halmac_api *api = HALMAC_GET_API(halmac);
+ struct halmac_p2pps halmac_p2p_ps;
+
+ (&halmac_p2p_ps)->offload_en = pp2p_ps_para->offload_en;
+ (&halmac_p2p_ps)->role = pp2p_ps_para->role;
+ (&halmac_p2p_ps)->ctwindow_en = pp2p_ps_para->ctwindow_en;
+ (&halmac_p2p_ps)->noa_en = pp2p_ps_para->noa_en;
+ (&halmac_p2p_ps)->noa_sel = pp2p_ps_para->noa_sel;
+ (&halmac_p2p_ps)->all_sta_sleep = pp2p_ps_para->all_sta_sleep;
+ (&halmac_p2p_ps)->discovery = pp2p_ps_para->discovery;
+ (&halmac_p2p_ps)->p2p_port_id = _hw_port_drv2halmac(pp2p_ps_para->p2p_port_id);
+ (&halmac_p2p_ps)->p2p_group = pp2p_ps_para->p2p_group;
+ (&halmac_p2p_ps)->p2p_macid = pp2p_ps_para->p2p_macid;
+ (&halmac_p2p_ps)->ctwindow_length = pp2p_ps_para->ctwindow_length;
+ (&halmac_p2p_ps)->noa_duration_para = pp2p_ps_para->noa_duration_para;
+ (&halmac_p2p_ps)->noa_interval_para = pp2p_ps_para->noa_interval_para;
+ (&halmac_p2p_ps)->noa_start_time_para = pp2p_ps_para->noa_start_time_para;
+ (&halmac_p2p_ps)->noa_count_para = pp2p_ps_para->noa_count_para;
+
+ status = api->halmac_p2pps(halmac, (&halmac_p2p_ps));
+ if (status != HALMAC_RET_SUCCESS)
+ return -1;
+
+ return 0;
+
+}
+
+/**
+ * rtw_halmac_iqk() - Run IQ Calibration
+ * @d: struct dvobj_priv*
+ * @clear: IQK parameters
+ * @segment: IQK parameters
+ *
+ * Process IQ Calibration(IQK).
+ *
+ * Rteurn: 0 for OK, otherwise fail.
+ */
+int rtw_halmac_iqk(struct dvobj_priv *d, u8 clear, u8 segment)
{
- PHALMAC_ADAPTER mac;
- PHALMAC_API api;
- HALMAC_RET_STATUS status;
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
+ enum halmac_feature_id id;
+ struct halmac_iqk_para para;
+ int ret;
+ u8 retry = 3;
+ u8 delay = 1; /* ms */
mac = dvobj_to_halmac(d);
api = HALMAC_GET_API(mac);
+ id = HALMAC_FEATURE_IQK;
+
+ ret = init_halmac_event(d, id, NULL, 0);
+ if (ret)
+ return -1;
+
+ para.clear = clear;
+ para.segment_iqk = segment;
+
+ do {
+ status = api->halmac_start_iqk(mac, ¶);
+ if (status != HALMAC_RET_BUSY_STATE)
+ break;
+ RTW_WARN("%s: Fail to start IQK, status is BUSY! retry=%d\n", __FUNCTION__, retry);
+ if (!retry)
+ break;
+ retry--;
+ rtw_msleep_os(delay);
+ } while (1);
+ if (status != HALMAC_RET_SUCCESS) {
+ free_halmac_event(d, id);
+ return -1;
+ }
- status = api->halmac_cfg_ch_bw(mac, channel, pri_ch_idx, bw);
- if (HALMAC_RET_SUCCESS != status)
+ ret = wait_halmac_event(d, id);
+ if (ret)
return -1;
return 0;
}
-int rtw_halmac_get_hw_value(struct dvobj_priv *d, HALMAC_HW_ID hw_id, VOID *pvalue)
+static inline u32 _phy_parameter_val_drv2halmac(u32 val, u8 msk_en, u32 msk)
{
- PHALMAC_ADAPTER mac;
- PHALMAC_API api;
- HALMAC_RET_STATUS status;
-
+ if (!msk_en)
+ return val;
- mac = dvobj_to_halmac(d);
- api = HALMAC_GET_API(mac);
+ return (val << bitshift(msk));
+}
- status = api->halmac_get_hw_value(mac, hw_id, pvalue);
- if (HALMAC_RET_SUCCESS != status)
+static int _phy_parameter_drv2halmac(struct rtw_phy_parameter *para, struct halmac_phy_parameter_info *info)
+{
+ if (!para || !info)
return -1;
- return 0;
-}
+ _rtw_memset(info, 0, sizeof(*info));
-int rtw_halmac_dump_fifo(struct dvobj_priv *d, HAL_FIFO_SEL halmac_fifo_sel)
-{
- PHALMAC_ADAPTER mac;
- PHALMAC_API api;
- HALMAC_RET_STATUS status;
- u8 *pfifo_map = NULL;
- u32 fifo_size = 0;
- s8 ret = 0;
+ switch (para->cmd) {
+ case 0:
+ /* MAC register */
+ switch (para->data.mac.size) {
+ case 1:
+ info->cmd_id = HALMAC_PARAMETER_CMD_MAC_W8;
+ break;
+ case 2:
+ info->cmd_id = HALMAC_PARAMETER_CMD_MAC_W16;
+ break;
+ default:
+ info->cmd_id = HALMAC_PARAMETER_CMD_MAC_W32;
+ break;
+ }
+ info->content.MAC_REG_W.value = _phy_parameter_val_drv2halmac(
+ para->data.mac.value,
+ para->data.mac.msk_en,
+ para->data.mac.msk);
+ info->content.MAC_REG_W.msk = para->data.mac.msk;
+ info->content.MAC_REG_W.offset = para->data.mac.offset;
+ info->content.MAC_REG_W.msk_en = para->data.mac.msk_en;
+ break;
- mac = dvobj_to_halmac(d);
- api = HALMAC_GET_API(mac);
+ case 1:
+ /* BB register */
+ switch (para->data.bb.size) {
+ case 1:
+ info->cmd_id = HALMAC_PARAMETER_CMD_BB_W8;
+ break;
+ case 2:
+ info->cmd_id = HALMAC_PARAMETER_CMD_BB_W16;
+ break;
+ default:
+ info->cmd_id = HALMAC_PARAMETER_CMD_BB_W32;
+ break;
+ }
+ info->content.BB_REG_W.value = _phy_parameter_val_drv2halmac(
+ para->data.bb.value,
+ para->data.bb.msk_en,
+ para->data.bb.msk);
+ info->content.BB_REG_W.msk = para->data.bb.msk;
+ info->content.BB_REG_W.offset = para->data.bb.offset;
+ info->content.BB_REG_W.msk_en = para->data.bb.msk_en;
+ break;
- fifo_size = api->halmac_get_fifo_size(mac, halmac_fifo_sel);
- if (fifo_size)
- pfifo_map = rtw_vmalloc(fifo_size);
- if (pfifo_map == NULL)
- return -1;
+ case 2:
+ /* RF register */
+ info->cmd_id = HALMAC_PARAMETER_CMD_RF_W;
+ info->content.RF_REG_W.value = _phy_parameter_val_drv2halmac(
+ para->data.rf.value,
+ para->data.rf.msk_en,
+ para->data.rf.msk);
+ info->content.RF_REG_W.msk = para->data.rf.msk;
+ info->content.RF_REG_W.offset = para->data.rf.offset;
+ info->content.RF_REG_W.msk_en = para->data.rf.msk_en;
+ info->content.RF_REG_W.rf_path = para->data.rf.path;
+ break;
- status = api->halmac_dump_fifo(mac, halmac_fifo_sel, pfifo_map, fifo_size);
- if (HALMAC_RET_SUCCESS != status) {
- ret = -1;
- goto _exit;
- }
+ case 3:
+ /* Delay register */
+ if (para->data.delay.unit == 0)
+ info->cmd_id = HALMAC_PARAMETER_CMD_DELAY_US;
+ else
+ info->cmd_id = HALMAC_PARAMETER_CMD_DELAY_MS;
+ info->content.DELAY_TIME.delay_time = para->data.delay.value;
+ break;
-_exit:
- if (pfifo_map)
- rtw_vmfree(pfifo_map, fifo_size);
- return ret;
+ case 0xFF:
+ /* Latest(End) command */
+ info->cmd_id = HALMAC_PARAMETER_CMD_END;
+ break;
+
+ default:
+ return -1;
+ }
+ return 0;
}
-int rtw_halmac_rx_agg_switch(struct dvobj_priv *d, u8 enable)
+/**
+ * rtw_halmac_cfg_phy_para() - Register(Phy parameter) configuration
+ * @d: struct dvobj_priv*
+ * @para: phy parameter
+ *
+ * Configure registers by firmware using H2C/C2H mechanism.
+ * The latest command should be para->cmd==0xFF(End command) to finish all
+ * processes.
+ *
+ * Return: 0 for OK, otherwise fail.
+ */
+int rtw_halmac_cfg_phy_para(struct dvobj_priv *d, struct rtw_phy_parameter *para)
{
- PADAPTER adapter;
- PHAL_DATA_TYPE hal;
- PHALMAC_ADAPTER halmac;
- PHALMAC_API api;
- HALMAC_RXAGG_CFG rxaggcfg;
- HALMAC_RET_STATUS status;
- int err = -1;
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
+ enum halmac_feature_id id;
+ struct halmac_phy_parameter_info info;
+ u8 full_fifo;
+ int err, ret;
- adapter = d->padapters[IFACE_ID0];
- hal = GET_HAL_DATA(adapter);
- halmac = dvobj_to_halmac(d);
- api = HALMAC_GET_API(halmac);
- _rtw_memset((void *)&rxaggcfg, 0, sizeof(rxaggcfg));
+ mac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(mac);
+ id = HALMAC_FEATURE_CFG_PARA;
+ full_fifo = 1; /* ToDo: How to deciede? */
+ ret = 0;
- if (_TRUE == enable) {
-#ifdef CONFIG_SDIO_HCI
- rxaggcfg.mode = HALMAC_RX_AGG_MODE_DMA;
- rxaggcfg.threshold.drv_define = 0;
-#elif defined(CONFIG_USB_HCI) && defined(CONFIG_USB_RX_AGGREGATION)
- switch (hal->rxagg_mode) {
- case RX_AGG_DISABLE:
- rxaggcfg.mode = HALMAC_RX_AGG_MODE_NONE;
- break;
+ err = _phy_parameter_drv2halmac(para, &info);
+ if (err)
+ return -1;
- case RX_AGG_DMA:
- rxaggcfg.mode = HALMAC_RX_AGG_MODE_DMA;
- if (hal->rxagg_dma_size || hal->rxagg_dma_timeout) {
- rxaggcfg.threshold.drv_define = 1;
- rxaggcfg.threshold.timeout = hal->rxagg_dma_timeout;
- rxaggcfg.threshold.size = hal->rxagg_dma_size;
- }
- break;
+ err = init_halmac_event(d, id, NULL, 0);
+ if (err)
+ return -1;
- case RX_AGG_USB:
- case RX_AGG_MIX:
- rxaggcfg.mode = HALMAC_RX_AGG_MODE_USB;
- if (hal->rxagg_usb_size || hal->rxagg_usb_timeout) {
- rxaggcfg.threshold.drv_define = 1;
- rxaggcfg.threshold.timeout = hal->rxagg_usb_timeout;
- rxaggcfg.threshold.size = hal->rxagg_usb_size;
+ status = api->halmac_cfg_parameter(mac, &info, full_fifo);
+ if (info.cmd_id == HALMAC_PARAMETER_CMD_END) {
+ if (status == HALMAC_RET_SUCCESS) {
+ err = wait_halmac_event(d, id);
+ if (err)
+ ret = -1;
+ } else {
+ free_halmac_event(d, id);
+ ret = -1;
+ RTW_ERR("%s: Fail to send END of cfg parameter, status is 0x%x!\n", __FUNCTION__, status);
+ }
+ } else {
+ if (status == HALMAC_RET_PARA_SENDING) {
+ err = wait_halmac_event(d, id);
+ if (err)
+ ret = -1;
+ } else {
+ free_halmac_event(d, id);
+ if (status != HALMAC_RET_SUCCESS) {
+ ret = -1;
+ RTW_ERR("%s: Fail to cfg parameter, status is 0x%x!\n", __FUNCTION__, status);
}
- break;
}
-#endif /* CONFIG_USB_HCI */
- } else
- rxaggcfg.mode = HALMAC_RX_AGG_MODE_NONE;
-
- status = api->halmac_cfg_rx_aggregation(halmac, &rxaggcfg);
- if (status != HALMAC_RET_SUCCESS)
- goto out;
+ }
- err = 0;
-out:
- return err;
+ return ret;
}
-int rtw_halmac_get_wow_reason(struct dvobj_priv *d, u8 *reason)
+static enum halmac_wlled_mode _led_mode_drv2halmac(u8 drv_mode)
{
- PADAPTER adapter;
- u8 val8;
- int err = -1;
-
+ enum halmac_wlled_mode halmac_mode;
- adapter = d->padapters[IFACE_ID0];
- val8 = rtw_read8(adapter, 0x1C7);
- if (val8 == 0xEA)
- goto out;
+ switch (drv_mode) {
+ case 1:
+ halmac_mode = HALMAC_WLLED_MODE_TX;
+ break;
+ case 2:
+ halmac_mode = HALMAC_WLLED_MODE_RX;
+ break;
+ case 3:
+ halmac_mode = HALMAC_WLLED_MODE_SW_CTRL;
+ break;
+ case 0:
+ default:
+ halmac_mode = HALMAC_WLLED_MODE_TRX;
+ break;
+ }
- *reason = val8;
- err = 0;
-out:
- return err;
+ return halmac_mode;
}
-/*
- * Description:
- * Get RX driver info size. RX driver info is a small memory space between
- * scriptor and RX payload.
- *
- * +-------------------------+
- * | RX descriptor |
- * | usually 24 bytes |
- * +-------------------------+
- * | RX driver info |
- * | depends on driver cfg |
- * +-------------------------+
- * | RX paylad |
- * | |
- * +-------------------------+
+/**
+ * rtw_halmac_led_cfg() - Configure Hardware LED Mode
+ * @d: struct dvobj_priv*
+ * @enable: enable or disable LED function
+ * 0: disable
+ * 1: enable
+ * @mode: WLan LED mode (valid when enable==1)
+ * 0: Blink when TX(transmit packet) and RX(receive packet)
+ * 1: Blink when TX only
+ * 2: Blink when RX only
+ * 3: Software control
*
- * Parameter:
- * d pointer to struct dvobj_priv of driver
- * sz rx driver info size in bytes.
+ * Configure hardware WLan LED mode.
+ * If want to change LED mode after enabled, need to disable LED first and
+ * enable again to set new mode.
*
- * Rteurn:
- * 0 Success
- * other Fail
+ * Rteurn 0 for OK, otherwise fail.
*/
-int rtw_halmac_get_drv_info_sz(struct dvobj_priv *d, u8 *sz)
+int rtw_halmac_led_cfg(struct dvobj_priv *d, u8 enable, u8 mode)
{
- HALMAC_RET_STATUS status;
- u8 dw = 6; /* max number */
+ struct halmac_adapter *halmac;
+ struct halmac_api *api;
+ enum halmac_wlled_mode led_mode;
+ enum halmac_ret_status status;
-#if 0 /* TODO wait for halmac ready */
- status = api->halmac_get_hw_value(halmac, HALMAC_HW_RX_, &dw);
- if (status != HALMAC_RET_SUCCESS)
- return -1;
-#endif
- *sz = dw * 8;
- return 0;
-}
-int rtw_halmac_get_rsvd_drv_pg_bndy(struct dvobj_priv *dvobj, u16 *drv_pg)
-{
- HALMAC_RET_STATUS status;
- PHALMAC_ADAPTER halmac = dvobj_to_halmac(dvobj);
- PHALMAC_API api = HALMAC_GET_API(halmac);
+ halmac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(halmac);
- status = api->halmac_get_hw_value(halmac, HALMAC_HW_RSVD_PG_BNDY, drv_pg);
- if (status != HALMAC_RET_SUCCESS)
- return -1;
+ if (enable) {
+ status = api->halmac_pinmux_set_func(halmac,
+ HALMAC_GPIO_FUNC_WL_LED);
+ if (status != HALMAC_RET_SUCCESS) {
+ RTW_ERR("%s: pinmux set fail!(0x%x)\n",
+ __FUNCTION__, status);
+ return -1;
+ }
+
+ led_mode = _led_mode_drv2halmac(mode);
+ status = api->halmac_pinmux_wl_led_mode(halmac, led_mode);
+ if (status != HALMAC_RET_SUCCESS) {
+ RTW_ERR("%s: mode set fail!(0x%x)\n",
+ __FUNCTION__, status);
+ return -1;
+ }
+ } else {
+ /* Change LED to software control and turn off */
+ api->halmac_pinmux_wl_led_mode(halmac,
+ HALMAC_WLLED_MODE_SW_CTRL);
+ api->halmac_pinmux_wl_led_sw_ctrl(halmac, 0);
+
+ status = api->halmac_pinmux_free_func(halmac,
+ HALMAC_GPIO_FUNC_WL_LED);
+ if (status != HALMAC_RET_SUCCESS) {
+ RTW_ERR("%s: pinmux free fail!(0x%x)\n",
+ __FUNCTION__, status);
+ return -1;
+ }
+ }
return 0;
}
-int rtw_halmac_download_rsvd_page(struct dvobj_priv *dvobj, u16 page_idx, u8 *pbuf, u8 length)
+/**
+ * rtw_halmac_led_switch() - Turn Hardware LED on/off
+ * @d: struct dvobj_priv*
+ * @on: LED light or not
+ * 0: Off
+ * 1: On(Light)
+ *
+ * Turn Hardware WLan LED On/Off.
+ * Before use this function, user should call rtw_halmac_led_ctrl() to switch
+ * mode to "software control(3)" first, otherwise control would fail.
+ * The interval between on and off must be longer than 1 ms, or the LED would
+ * keep light or dark only.
+ * Ex. Turn off LED at first, turn on after 0.5ms and turn off again after
+ * 0.5ms. The LED during this flow will only keep dark, and miss the turn on
+ * operation between two turn off operations.
+ */
+void rtw_halmac_led_switch(struct dvobj_priv *d, u8 on)
{
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
- PHALMAC_ADAPTER halmac = dvobj_to_halmac(dvobj);
- PHALMAC_API api = HALMAC_GET_API(halmac);
+ struct halmac_adapter *halmac;
+ struct halmac_api *api;
- /*status = api->halmac_get_hw_value(halmac, HALMAC_HW_RSVD_PG_BNDY, drv_pg);*/
- if (status != HALMAC_RET_SUCCESS)
- return -1;
- return 0;
+ halmac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(halmac);
+ api->halmac_pinmux_wl_led_sw_ctrl(halmac, on);
}
#ifdef CONFIG_SDIO_HCI
@@ -1998,16 +4653,16 @@ int rtw_halmac_query_tx_page_num(struct dvobj_priv *d)
{
PADAPTER adapter;
struct halmacpriv *hmpriv;
- PHALMAC_ADAPTER halmac;
- PHALMAC_API api;
- HALMAC_RQPN_MAP rqpn;
- HALMAC_DMA_MAPPING dmaqueue;
- HALMAC_TXFF_ALLOCATION fifosize;
- HALMAC_RET_STATUS status;
+ struct halmac_adapter *halmac;
+ struct halmac_api *api;
+ struct halmac_rqpn_map rqpn;
+ enum halmac_dma_mapping dmaqueue;
+ struct halmac_txff_allocation fifosize;
+ enum halmac_ret_status status;
u8 i;
- adapter = d->padapters[IFACE_ID0];
+ adapter = dvobj_get_primary_adapter(d);
hmpriv = &d->hmpriv;
halmac = dvobj_to_halmac(d);
api = HALMAC_GET_API(halmac);
@@ -2102,9 +4757,9 @@ int rtw_halmac_get_tx_queue_page_num(struct dvobj_priv *d, u8 queue, u32 *page)
*/
u32 rtw_halmac_sdio_get_tx_addr(struct dvobj_priv *d, u8 *desc, u32 size)
{
- PHALMAC_ADAPTER mac;
- PHALMAC_API api;
- HALMAC_RET_STATUS status;
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
u32 addr;
@@ -2120,9 +4775,9 @@ u32 rtw_halmac_sdio_get_tx_addr(struct dvobj_priv *d, u8 *desc, u32 size)
int rtw_halmac_sdio_tx_allowed(struct dvobj_priv *d, u8 *buf, u32 size)
{
- PHALMAC_ADAPTER mac;
- PHALMAC_API api;
- HALMAC_RET_STATUS status;
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
mac = dvobj_to_halmac(d);
@@ -2151,9 +4806,9 @@ u32 rtw_halmac_sdio_get_rx_addr(struct dvobj_priv *d, u8 *seq)
#ifdef CONFIG_USB_HCI
u8 rtw_halmac_usb_get_bulkout_id(struct dvobj_priv *d, u8 *buf, u32 size)
{
- PHALMAC_ADAPTER mac;
- PHALMAC_API api;
- HALMAC_RET_STATUS status;
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
u8 bulkout_id;
@@ -2167,9 +4822,38 @@ u8 rtw_halmac_usb_get_bulkout_id(struct dvobj_priv *d, u8 *buf, u32 size)
return bulkout_id;
}
-static inline HALMAC_USB_MODE _usb_mode_drv2halmac(enum RTW_USB_SPEED usb_mode)
+/**
+ * rtw_halmac_usb_get_txagg_desc_num() - MAX descriptor number in one bulk for TX
+ * @d: struct dvobj_priv*
+ * @size: TX FIFO size, unit is byte.
+ *
+ * Get MAX descriptor number in one bulk out from HALMAC.
+ *
+ * Rteurn 0 for OK, otherwise fail.
+ */
+int rtw_halmac_usb_get_txagg_desc_num(struct dvobj_priv *d, u8 *num)
+{
+ struct halmac_adapter *halmac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
+ u8 val = 0;
+
+
+ halmac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(halmac);
+
+ status = api->halmac_get_hw_value(halmac, HALMAC_HW_USB_TXAGG_DESC_NUM, &val);
+ if (status != HALMAC_RET_SUCCESS)
+ return -1;
+
+ *num = val;
+
+ return 0;
+}
+
+static inline enum halmac_usb_mode _usb_mode_drv2halmac(enum RTW_USB_SPEED usb_mode)
{
- HALMAC_USB_MODE halmac_usb_mode = HALMAC_USB_MODE_U2;
+ enum halmac_usb_mode halmac_usb_mode = HALMAC_USB_MODE_U2;
switch (usb_mode) {
case RTW_USB_SPEED_2:
@@ -2188,13 +4872,13 @@ static inline HALMAC_USB_MODE _usb_mode_drv2halmac(enum RTW_USB_SPEED usb_mode)
u8 rtw_halmac_switch_usb_mode(struct dvobj_priv *d, enum RTW_USB_SPEED usb_mode)
{
- PHALMAC_ADAPTER mac;
- PHALMAC_API api;
- HALMAC_RET_STATUS status;
PADAPTER adapter;
- HALMAC_USB_MODE halmac_usb_mode;
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
+ enum halmac_usb_mode halmac_usb_mode;
- adapter = d->padapters[IFACE_ID0];
+ adapter = dvobj_get_primary_adapter(d);
mac = dvobj_to_halmac(d);
api = HALMAC_GET_API(mac);
halmac_usb_mode = _usb_mode_drv2halmac(usb_mode);
@@ -2206,3 +4890,143 @@ u8 rtw_halmac_switch_usb_mode(struct dvobj_priv *d, enum RTW_USB_SPEED usb_mode)
return _SUCCESS;
}
#endif /* CONFIG_USB_HCI */
+
+#ifdef CONFIG_BEAMFORMING
+#ifdef RTW_BEAMFORMING_VERSION_2
+int rtw_halmac_bf_add_mu_bfer(struct dvobj_priv *d, u16 paid, u16 csi_para,
+ u16 my_aid, enum halmac_csi_seg_len sel, u8 *addr)
+{
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
+ struct halmac_mu_bfer_init_para param;
+
+
+ mac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(mac);
+
+ _rtw_memset(¶m, 0, sizeof(param));
+ param.paid = paid;
+ param.csi_para = csi_para;
+ param.my_aid = my_aid;
+ param.csi_length_sel = sel;
+ _rtw_memcpy(param.bfer_address.addr, addr, 6);
+
+ status = api->halmac_mu_bfer_entry_init(mac, ¶m);
+ if (status != HALMAC_RET_SUCCESS)
+ return -1;
+
+ return 0;
+}
+
+int rtw_halmac_bf_del_mu_bfer(struct dvobj_priv *d)
+{
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
+
+
+ mac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(mac);
+
+ status = api->halmac_mu_bfer_entry_del(mac);
+ if (status != HALMAC_RET_SUCCESS)
+ return -1;
+
+ return 0;
+}
+
+
+int rtw_halmac_bf_cfg_sounding(struct dvobj_priv *d,
+ enum halmac_snd_role role, enum halmac_data_rate rate)
+{
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
+
+
+ mac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(mac);
+
+ status = api->halmac_cfg_sounding(mac, role, rate);
+ if (status != HALMAC_RET_SUCCESS)
+ return -1;
+
+ return 0;
+}
+
+int rtw_halmac_bf_del_sounding(struct dvobj_priv *d,
+ enum halmac_snd_role role)
+{
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
+
+
+ mac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(mac);
+
+ status = api->halmac_del_sounding(mac, role);
+ if (status != HALMAC_RET_SUCCESS)
+ return -1;
+
+ return 0;
+}
+
+int rtw_halmac_bf_cfg_csi_rate(struct dvobj_priv *d,
+ u8 rssi, u8 current_rate, u8 fixrate_en,
+ u8 *new_rate)
+{
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
+
+
+ mac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(mac);
+
+ status = api->halmac_cfg_csi_rate(mac,
+ rssi, current_rate, fixrate_en, new_rate);
+ if (status != HALMAC_RET_SUCCESS)
+ return -1;
+
+ return 0;
+}
+
+int rtw_halmac_bf_cfg_mu_mimo(struct dvobj_priv *d, enum halmac_snd_role role,
+ u8 *sounding_sts, u16 grouping_bitmap, u8 mu_tx_en,
+ u32 *given_gid_tab, u32 *given_user_pos)
+{
+ struct halmac_adapter *mac;
+ struct halmac_api *api;
+ enum halmac_ret_status status;
+ struct halmac_cfg_mumimo_para param;
+
+
+ mac = dvobj_to_halmac(d);
+ api = HALMAC_GET_API(mac);
+
+ _rtw_memset(¶m, 0, sizeof(param));
+
+ param.role = role;
+ param.grouping_bitmap = grouping_bitmap;
+ param.mu_tx_en = mu_tx_en;
+
+ if (sounding_sts)
+ _rtw_memcpy(param.sounding_sts, sounding_sts, 6);
+
+ if (given_gid_tab)
+ _rtw_memcpy(param.given_gid_tab, given_gid_tab, 8);
+
+ if (given_user_pos)
+ _rtw_memcpy(param.given_user_pos, given_user_pos, 16);
+
+ status = api->halmac_cfg_mumimo(mac, ¶m);
+ if (status != HALMAC_RET_SUCCESS)
+ return -1;
+
+ return 0;
+}
+
+#endif /* RTW_BEAMFORMING_VERSION_2 */
+#endif /* CONFIG_BEAMFORMING */
diff --git a/hal/hal_halmac.h b/hal/hal_halmac.h
index c59df43..4555b18 100644
--- a/hal/hal_halmac.h
+++ b/hal/hal_halmac.h
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2015 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,24 +11,20 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#ifndef _HAL_HALMAC_H_
#define _HAL_HALMAC_H_
#include /* adapter_to_dvobj(), struct intf_hdl and etc. */
-#include "halmac/halmac_api.h" /* PHALMAC_ADAPTER and etc. */
+#include /* struct hal_spec_t */
+#include "halmac/halmac_api.h" /* struct halmac_adapter* and etc. */
/* HALMAC Definition for Driver */
-#define RTW_HALMAC_H2C_MAX_SIZE HALMAC_H2C_CMD_ORIGINAL_SIZE_88XX
+#define RTW_HALMAC_H2C_MAX_SIZE 8
#define RTW_HALMAC_BA_SSN_RPT_SIZE 4
#define dvobj_set_halmac(d, mac) ((d)->halmac = (mac))
-#define dvobj_to_halmac(d) ((PHALMAC_ADAPTER)((d)->halmac))
+#define dvobj_to_halmac(d) ((struct halmac_adapter *)((d)->halmac))
#define adapter_to_halmac(p) dvobj_to_halmac(adapter_to_dvobj(p))
/* for H2C cmd */
@@ -41,18 +37,123 @@ typedef enum _RTW_HALMAC_MODE {
RTW_HALMAC_MODE_WIFI_TEST,
} RTW_HALMAC_MODE;
-extern HALMAC_PLATFORM_API rtw_halmac_platform_api;
+union rtw_phy_para_data {
+ struct _mac {
+ u32 value; /* value to be set in bit mask(msk) */
+ u32 msk; /* bit mask */
+ u16 offset; /* address */
+ u8 msk_en; /* 0/1 for msk invalid/valid */
+ u8 size; /* Unit is bytes, and value should be 1/2/4 */
+ } mac;
+ struct _bb {
+ u32 value;
+ u32 msk;
+ u16 offset;
+ u8 msk_en;
+ u8 size;
+ } bb;
+ struct _rf {
+ u32 value;
+ u32 msk;
+ u8 offset;
+ u8 msk_en;
+ /*
+ * 0: path A
+ * 1: path B
+ * 2: path C
+ * 3: path D
+ */
+ u8 path;
+ } rf;
+ struct _delay {
+ /*
+ * 0: microsecond (us)
+ * 1: millisecond (ms)
+ */
+ u8 unit;
+ u16 value;
+ } delay;
+};
+
+struct rtw_phy_parameter {
+ /*
+ * 0: MAC register
+ * 1: BB register
+ * 2: RF register
+ * 3: Delay
+ * 0xFF: Latest(End) command
+ */
+ u8 cmd;
+ union rtw_phy_para_data data;
+};
+
+struct rtw_halmac_bcn_ctrl {
+ u8 rx_bssid_fit:1; /* 0:HW handle beacon, 1:ignore */
+ u8 txbcn_rpt:1; /* Enable TXBCN report in ad hoc and AP mode */
+ u8 tsf_update:1; /* Update TSF when beacon or probe response */
+ u8 enable_bcn:1; /* Enable beacon related functions */
+ u8 rxbcn_rpt:1; /* Enable RXBCNOK report */
+ u8 p2p_ctwin:1; /* Enable P2P CTN WINDOWS function */
+ u8 p2p_bcn_area:1; /* Enable P2P BCN area on function */
+};
+
+extern struct halmac_platform_api rtw_halmac_platform_api;
/* HALMAC API for Driver(HAL) */
u8 rtw_halmac_read8(struct intf_hdl *, u32 addr);
u16 rtw_halmac_read16(struct intf_hdl *, u32 addr);
u32 rtw_halmac_read32(struct intf_hdl *, u32 addr);
+void rtw_halmac_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
+#ifdef CONFIG_SDIO_INDIRECT_ACCESS
+u8 rtw_halmac_iread8(struct intf_hdl *pintfhdl, u32 addr);
+u16 rtw_halmac_iread16(struct intf_hdl *pintfhdl, u32 addr);
+u32 rtw_halmac_iread32(struct intf_hdl *pintfhdl, u32 addr);
+#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
int rtw_halmac_write8(struct intf_hdl *, u32 addr, u8 value);
int rtw_halmac_write16(struct intf_hdl *, u32 addr, u16 value);
int rtw_halmac_write32(struct intf_hdl *, u32 addr, u32 value);
-int rtw_halmac_init_adapter(struct dvobj_priv *, PHALMAC_PLATFORM_API);
+/* Software Information */
+void rtw_halmac_get_version(char *str, u32 len);
+
+/* Software Initialization */
+int rtw_halmac_init_adapter(struct dvobj_priv *d, struct halmac_platform_api *pf_api);
int rtw_halmac_deinit_adapter(struct dvobj_priv *);
+
+/* Get operations */
+int rtw_halmac_get_hw_value(struct dvobj_priv *d, enum halmac_hw_id hw_id, void *pvalue);
+int rtw_halmac_get_tx_fifo_size(struct dvobj_priv *d, u32 *size);
+int rtw_halmac_get_rx_fifo_size(struct dvobj_priv *d, u32 *size);
+int rtw_halmac_get_rsvd_drv_pg_bndy(struct dvobj_priv *d, u16 *bndy);
+int rtw_halmac_get_page_size(struct dvobj_priv *d, u32 *size);
+int rtw_halmac_get_tx_agg_align_size(struct dvobj_priv *d, u16 *size);
+int rtw_halmac_get_rx_agg_align_size(struct dvobj_priv *d, u8 *size);
+int rtw_halmac_get_rx_drv_info_sz(struct dvobj_priv *, u8 *sz);
+int rtw_halmac_get_tx_desc_size(struct dvobj_priv *d, u32 *size);
+int rtw_halmac_get_rx_desc_size(struct dvobj_priv *d, u32 *size);
+int rtw_halmac_get_ori_h2c_size(struct dvobj_priv *d, u32 *size);
+int rtw_halmac_get_oqt_size(struct dvobj_priv *d, u8 *size);
+int rtw_halmac_get_ac_queue_number(struct dvobj_priv *d, u8 *num);
+int rtw_halmac_get_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr);
+int rtw_halmac_get_network_type(struct dvobj_priv *d, enum _hw_port hwport, u8 *type);
+int rtw_halmac_get_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport, struct rtw_halmac_bcn_ctrl *bcn_ctrl);
+/*int rtw_halmac_get_wow_reason(struct dvobj_priv *, u8 *reason);*/
+
+/* Set operations */
+int rtw_halmac_config_rx_info(struct dvobj_priv *d, enum halmac_drv_info info);
+int rtw_halmac_set_max_dl_fw_size(struct dvobj_priv *d, u32 size);
+int rtw_halmac_set_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr);
+int rtw_halmac_set_bssid(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr);
+int rtw_halmac_set_tx_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr);
+int rtw_halmac_set_network_type(struct dvobj_priv *d, enum _hw_port hwport, u8 type);
+int rtw_halmac_reset_tsf(struct dvobj_priv *d, enum _hw_port hwport);
+int rtw_halmac_set_bcn_interval(struct dvobj_priv *d, enum _hw_port hwport, u32 space);
+int rtw_halmac_set_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport, struct rtw_halmac_bcn_ctrl *bcn_ctrl);
+int rtw_halmac_set_aid(struct dvobj_priv *d, enum _hw_port hwport, u16 aid);
+int rtw_halmac_set_bandwidth(struct dvobj_priv *d, u8 channel, u8 pri_ch_idx, u8 bw);
+int rtw_halmac_set_edca(struct dvobj_priv *d, u8 queue, u8 aifs, u8 cw, u16 txop);
+
+/* Functions */
int rtw_halmac_poweron(struct dvobj_priv *);
int rtw_halmac_poweroff(struct dvobj_priv *);
int rtw_halmac_init_hal(struct dvobj_priv *);
@@ -60,18 +161,23 @@ int rtw_halmac_init_hal_fw(struct dvobj_priv *, u8 *fw, u32 fwsize);
int rtw_halmac_init_hal_fw_file(struct dvobj_priv *, u8 *fwpath);
int rtw_halmac_deinit_hal(struct dvobj_priv *);
int rtw_halmac_self_verify(struct dvobj_priv *);
+int rtw_halmac_txfifo_wait_empty(struct dvobj_priv *d, u32 timeout);
int rtw_halmac_dlfw(struct dvobj_priv *, u8 *fw, u32 fwsize);
int rtw_halmac_dlfw_from_file(struct dvobj_priv *, u8 *fwpath);
+int rtw_halmac_dlfw_mem(struct dvobj_priv *d, u8 *fw, u32 fwsize, enum fw_mem mem);
+int rtw_halmac_dlfw_mem_from_file(struct dvobj_priv *d, u8 *fwpath, enum fw_mem mem);
int rtw_halmac_phy_power_switch(struct dvobj_priv *, u8 enable);
int rtw_halmac_send_h2c(struct dvobj_priv *, u8 *h2c);
int rtw_halmac_c2h_handle(struct dvobj_priv *, u8 *c2h, u32 size);
+/* eFuse */
+int rtw_halmac_get_available_efuse_size(struct dvobj_priv *d, u32 *size);
int rtw_halmac_get_physical_efuse_size(struct dvobj_priv *, u32 *size);
int rtw_halmac_read_physical_efuse_map(struct dvobj_priv *, u8 *map, u32 size);
int rtw_halmac_read_physical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data);
int rtw_halmac_write_physical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data);
int rtw_halmac_get_logical_efuse_size(struct dvobj_priv *, u32 *size);
-int rtw_halmac_read_logical_efuse_map(struct dvobj_priv *, u8 *map, u32 size);
+int rtw_halmac_read_logical_efuse_map(struct dvobj_priv *, u8 *map, u32 size, u8 *maskmap, u32 masksize);
int rtw_halmac_write_logical_efuse_map(struct dvobj_priv *, u8 *map, u32 size, u8 *maskmap, u32 masksize);
int rtw_halmac_read_logical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data);
int rtw_halmac_write_logical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data);
@@ -79,19 +185,17 @@ int rtw_halmac_write_logical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8
int rtw_halmac_write_bt_physical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data);
int rtw_halmac_read_bt_physical_efuse_map(struct dvobj_priv *, u8 *map, u32 size);
-int rtw_halmac_config_rx_info(struct dvobj_priv *, HALMAC_DRV_INFO);
-int rtw_halmac_set_mac_address(struct dvobj_priv *, enum _hw_port, u8 *addr);
-int rtw_halmac_set_bssid(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr);
-
-int rtw_halmac_set_bandwidth(struct dvobj_priv *, u8 channel, u8 pri_ch_idx, u8 bw);
+int rtw_halmac_dump_fifo(struct dvobj_priv *d, u8 fifo_sel, u32 addr, u32 size, u8 *buffer);
int rtw_halmac_rx_agg_switch(struct dvobj_priv *, u8 enable);
-int rtw_halmac_get_hw_value(struct dvobj_priv *d, HALMAC_HW_ID hw_id, VOID *pvalue);
-int rtw_halmac_get_wow_reason(struct dvobj_priv *, u8 *reason);
-int rtw_halmac_get_drv_info_sz(struct dvobj_priv *d, u8 *sz);
-
-int rtw_halmac_get_rsvd_drv_pg_bndy(struct dvobj_priv *dvobj, u16 *drv_pg);
-int rtw_halmac_download_rsvd_page(struct dvobj_priv *dvobj, u16 page_idx, u8 *pbuf, u8 length);
+/* Specific function APIs*/
+int rtw_halmac_download_rsvd_page(struct dvobj_priv *dvobj, u8 pg_offset, u8 *pbuf, u32 size);
+int rtw_halmac_fill_hal_spec(struct dvobj_priv *, struct hal_spec_t *);
+int rtw_halmac_p2pps(struct dvobj_priv *dvobj, PHAL_P2P_PS_PARA pp2p_ps_para);
+int rtw_halmac_iqk(struct dvobj_priv *d, u8 clear, u8 segment);
+int rtw_halmac_cfg_phy_para(struct dvobj_priv *d, struct rtw_phy_parameter *para);
+int rtw_halmac_led_cfg(struct dvobj_priv *d, u8 enable, u8 mode);
+void rtw_halmac_led_switch(struct dvobj_priv *d, u8 on);
#ifdef CONFIG_SDIO_HCI
int rtw_halmac_query_tx_page_num(struct dvobj_priv *);
@@ -103,7 +207,34 @@ u32 rtw_halmac_sdio_get_rx_addr(struct dvobj_priv *, u8 *seq);
#ifdef CONFIG_USB_HCI
u8 rtw_halmac_usb_get_bulkout_id(struct dvobj_priv *, u8 *buf, u32 size);
+int rtw_halmac_usb_get_txagg_desc_num(struct dvobj_priv *d, u8 *num);
u8 rtw_halmac_switch_usb_mode(struct dvobj_priv *d, enum RTW_USB_SPEED usb_mode);
#endif /* CONFIG_USB_HCI */
+#ifdef CONFIG_SUPPORT_TRX_SHARED
+void dump_trx_share_mode(void *sel, _adapter *adapter);
+#endif
+
+#ifdef CONFIG_BEAMFORMING
+#ifdef RTW_BEAMFORMING_VERSION_2
+int rtw_halmac_bf_add_mu_bfer(struct dvobj_priv *d, u16 paid, u16 csi_para,
+ u16 my_aid, enum halmac_csi_seg_len sel, u8 *addr);
+int rtw_halmac_bf_del_mu_bfer(struct dvobj_priv *d);
+
+int rtw_halmac_bf_cfg_sounding(struct dvobj_priv *d, enum halmac_snd_role role,
+ enum halmac_data_rate rate);
+int rtw_halmac_bf_del_sounding(struct dvobj_priv *d, enum halmac_snd_role role);
+
+int rtw_halmac_bf_cfg_csi_rate(struct dvobj_priv *d, u8 rssi, u8 current_rate,
+ u8 fixrate_en, u8 *new_rate);
+
+int rtw_halmac_bf_cfg_mu_mimo(struct dvobj_priv *d, enum halmac_snd_role role,
+ u8 *sounding_sts, u16 grouping_bitmap, u8 mu_tx_en,
+ u32 *given_gid_tab, u32 *given_user_pos);
+#define rtw_halmac_bf_cfg_mu_bfee(d, gid_tab, user_pos) \
+ rtw_halmac_bf_cfg_mu_mimo(d, HAL_BFEE, NULL, 0, 0, gid_tab, user_pos)
+
+#endif /* RTW_BEAMFORMING_VERSION_2 */
+#endif /* CONFIG_BEAMFORMING */
+
#endif /* _HAL_HALMAC_H_ */
diff --git a/hal/hal_hci/hal_usb.c b/hal/hal_hci/hal_usb.c
index 060fe9c..e47135b 100644
--- a/hal/hal_hci/hal_usb.c
+++ b/hal/hal_hci/hal_usb.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,32 +11,18 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#define _HAL_USB_C_
#include
#include
-#ifdef CONFIG_RTL8821C
- #include /* MAX_RECVBUF_SZ */
-#endif /* CONFIG_RTL8821C */
-
int usb_init_recv_priv(_adapter *padapter, u16 ini_in_buf_sz)
{
struct recv_priv *precvpriv = &padapter->recvpriv;
int i, res = _SUCCESS;
struct recv_buf *precvbuf;
-#ifdef CONFIG_RECV_THREAD_MODE
- _rtw_init_sema(&precvpriv->recv_sema, 0);/* will be removed */
- _rtw_init_sema(&precvpriv->terminate_recvthread_sema, 0);/* will be removed */
-#endif /* CONFIG_RECV_THREAD_MODE */
-
#ifdef PLATFORM_LINUX
tasklet_init(&precvpriv->recv_tasklet,
(void(*)(unsigned long))usb_recv_tasklet,
@@ -79,7 +65,6 @@ int usb_init_recv_priv(_adapter *padapter, u16 ini_in_buf_sz)
precvpriv->pallocated_recv_buf = rtw_zmalloc(NR_RECVBUFF * sizeof(struct recv_buf) + 4);
if (precvpriv->pallocated_recv_buf == NULL) {
res = _FAIL;
- RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("alloc recv_buf fail!\n"));
goto exit;
}
@@ -228,7 +213,7 @@ void usb_free_recv_priv(_adapter *padapter, u16 ini_in_buf_sz)
IF_DEQUEUE(&precvpriv->rx_indicate_queue, m);
if (m == NULL)
break;
- m_freem(m);
+ rtw_os_pkt_free(m);
}
mtx_destroy(&precvpriv->rx_indicate_queue.ifq_mtx);
#endif /* CONFIG_RX_INDICATE_QUEUE */
@@ -236,6 +221,42 @@ void usb_free_recv_priv(_adapter *padapter, u16 ini_in_buf_sz)
#endif /* PLATFORM_FREEBSD */
}
+#ifdef CONFIG_FW_C2H_REG
+void usb_c2h_hisr_hdl(_adapter *adapter, u8 *buf)
+{
+ u8 *c2h_evt = buf;
+ u8 id, seq, plen;
+ u8 *payload;
+
+ if (rtw_hal_c2h_reg_hdr_parse(adapter, buf, &id, &seq, &plen, &payload) != _SUCCESS)
+ return;
+
+ if (0)
+ RTW_PRINT("%s C2H == %d\n", __func__, id);
+
+ if (rtw_hal_c2h_id_handle_directly(adapter, id, seq, plen, payload)) {
+ /* Handle directly */
+ rtw_hal_c2h_handler(adapter, id, seq, plen, payload);
+
+ /* Replace with special pointer to trigger c2h_evt_clear only */
+ if (rtw_cbuf_push(adapter->evtpriv.c2h_queue, (void*)&adapter->evtpriv) != _SUCCESS)
+ RTW_ERR("%s rtw_cbuf_push fail\n", __func__);
+ } else {
+ c2h_evt = rtw_malloc(C2H_REG_LEN);
+ if (c2h_evt != NULL) {
+ _rtw_memcpy(c2h_evt, buf, C2H_REG_LEN);
+ if (rtw_cbuf_push(adapter->evtpriv.c2h_queue, (void*)c2h_evt) != _SUCCESS)
+ RTW_ERR("%s rtw_cbuf_push fail\n", __func__);
+ } else {
+ /* Error handling for malloc fail */
+ if (rtw_cbuf_push(adapter->evtpriv.c2h_queue, (void*)NULL) != _SUCCESS)
+ RTW_ERR("%s rtw_cbuf_push fail\n", __func__);
+ }
+ }
+ _set_workitem(&adapter->evtpriv.c2h_wk);
+}
+#endif
+
#ifdef CONFIG_USB_SUPPORT_ASYNC_VDN_REQ
int usb_write_async(struct usb_device *udev, u32 addr, void *pdata, u16 len)
{
@@ -263,10 +284,8 @@ int usb_async_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val)
struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)pintfhdl->pintf_dev;
struct usb_device *udev = pdvobjpriv->pusbdev;
- _func_enter_;
data = val;
ret = usb_write_async(udev, addr, &data, 1);
- _func_exit_;
return ret;
}
@@ -278,10 +297,8 @@ int usb_async_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val)
struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)pintfhdl->pintf_dev;
struct usb_device *udev = pdvobjpriv->pusbdev;
- _func_enter_;
data = val;
ret = usb_write_async(udev, addr, &data, 2);
- _func_exit_;
return ret;
}
@@ -293,10 +310,8 @@ int usb_async_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val)
struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)pintfhdl->pintf_dev;
struct usb_device *udev = pdvobjpriv->pusbdev;
- _func_enter_;
data = val;
ret = usb_write_async(udev, addr, &data, 4);
- _func_exit_;
return ret;
}
@@ -311,7 +326,6 @@ u8 usb_read8(struct intf_hdl *pintfhdl, u32 addr)
u16 len;
u8 data = 0;
- _func_enter_;
request = 0x05;
requesttype = 0x01;/* read_in */
@@ -322,7 +336,6 @@ u8 usb_read8(struct intf_hdl *pintfhdl, u32 addr)
usbctrl_vendorreq(pintfhdl, request, wvalue, index,
&data, len, requesttype);
- _func_exit_;
return data;
}
@@ -336,7 +349,6 @@ u16 usb_read16(struct intf_hdl *pintfhdl, u32 addr)
u16 len;
u16 data = 0;
- _func_enter_;
request = 0x05;
requesttype = 0x01;/* read_in */
@@ -347,7 +359,6 @@ u16 usb_read16(struct intf_hdl *pintfhdl, u32 addr)
usbctrl_vendorreq(pintfhdl, request, wvalue, index,
&data, len, requesttype);
- _func_exit_;
return data;
@@ -362,7 +373,6 @@ u32 usb_read32(struct intf_hdl *pintfhdl, u32 addr)
u16 len;
u32 data = 0;
- _func_enter_;
request = 0x05;
requesttype = 0x01;/* read_in */
@@ -373,7 +383,6 @@ u32 usb_read32(struct intf_hdl *pintfhdl, u32 addr)
usbctrl_vendorreq(pintfhdl, request, wvalue, index,
&data, len, requesttype);
- _func_exit_;
return data;
}
@@ -388,7 +397,6 @@ int usb_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val)
u8 data;
int ret;
- _func_enter_;
request = 0x05;
requesttype = 0x00;/* write_out */
@@ -401,7 +409,6 @@ int usb_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val)
ret = usbctrl_vendorreq(pintfhdl, request, wvalue, index,
&data, len, requesttype);
- _func_exit_;
return ret;
}
@@ -416,7 +423,6 @@ int usb_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val)
u16 data;
int ret;
- _func_enter_;
request = 0x05;
requesttype = 0x00;/* write_out */
@@ -429,7 +435,6 @@ int usb_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val)
ret = usbctrl_vendorreq(pintfhdl, request, wvalue, index,
&data, len, requesttype);
- _func_exit_;
return ret;
@@ -445,7 +450,6 @@ int usb_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val)
u32 data;
int ret;
- _func_enter_;
request = 0x05;
requesttype = 0x00;/* write_out */
@@ -457,7 +461,6 @@ int usb_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val)
ret = usbctrl_vendorreq(pintfhdl, request, wvalue, index,
&data, len, requesttype);
- _func_exit_;
return ret;
@@ -473,7 +476,6 @@ int usb_writeN(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata)
u8 buf[VENDOR_CMD_MAX_DATA_LEN] = {0};
int ret;
- _func_enter_;
request = 0x05;
requesttype = 0x00;/* write_out */
@@ -485,7 +487,6 @@ int usb_writeN(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata)
ret = usbctrl_vendorreq(pintfhdl, request, wvalue, index,
buf, len, requesttype);
- _func_exit_;
return ret;
}
diff --git a/hal/hal_intf.c b/hal/hal_intf.c
index 99e2221..18d1a66 100644
--- a/hal/hal_intf.c
+++ b/hal/hal_intf.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,12 +11,7 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#define _HAL_INTF_C_
@@ -41,38 +36,49 @@ const u32 _chip_type_to_odm_ic_type[] = {
void rtw_hal_chip_configure(_adapter *padapter)
{
- padapter->HalFunc.intf_chip_configure(padapter);
+ padapter->hal_func.intf_chip_configure(padapter);
}
-void rtw_hal_read_chip_info(_adapter *padapter)
+/*
+ * Description:
+ * Read chip internal ROM data
+ *
+ * Return:
+ * _SUCCESS success
+ * _FAIL fail
+ */
+u8 rtw_hal_read_chip_info(_adapter *padapter)
{
+ u8 rtn = _SUCCESS;
u8 hci_type = rtw_get_intf_type(padapter);
- u32 start = rtw_get_current_time();
+ systime start = rtw_get_current_time();
/* before access eFuse, make sure card enable has been called */
if ((hci_type == RTW_SDIO || hci_type == RTW_GSPI)
&& !rtw_is_hw_init_completed(padapter))
rtw_hal_power_on(padapter);
- padapter->HalFunc.read_adapter_info(padapter);
+ rtn = padapter->hal_func.read_adapter_info(padapter);
if ((hci_type == RTW_SDIO || hci_type == RTW_GSPI)
&& !rtw_is_hw_init_completed(padapter))
rtw_hal_power_off(padapter);
RTW_INFO("%s in %d ms\n", __func__, rtw_get_passing_time_ms(start));
+
+ return rtn;
}
void rtw_hal_read_chip_version(_adapter *padapter)
{
- padapter->HalFunc.read_chip_version(padapter);
+ padapter->hal_func.read_chip_version(padapter);
rtw_odm_init_ic_type(padapter);
}
void rtw_hal_def_value_init(_adapter *padapter)
{
if (is_primary_adapter(padapter)) {
- padapter->HalFunc.init_default_value(padapter);
+ padapter->hal_func.init_default_value(padapter);
rtw_init_hal_com_default_value(padapter);
@@ -126,11 +132,11 @@ void rtw_hal_dm_init(_adapter *padapter)
if (is_primary_adapter(padapter)) {
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
- padapter->HalFunc.dm_init(padapter);
+ padapter->hal_func.dm_init(padapter);
_rtw_spinlock_init(&pHalData->IQKSpinLock);
- phy_load_tx_power_ext_info(padapter, 1, 1);
+ phy_load_tx_power_ext_info(padapter, 1);
}
}
void rtw_hal_dm_deinit(_adapter *padapter)
@@ -138,26 +144,58 @@ void rtw_hal_dm_deinit(_adapter *padapter)
if (is_primary_adapter(padapter)) {
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
- padapter->HalFunc.dm_deinit(padapter);
+ padapter->hal_func.dm_deinit(padapter);
_rtw_spinlock_free(&pHalData->IQKSpinLock);
}
}
-void rtw_hal_sw_led_init(_adapter *padapter)
+
+#ifdef CONFIG_RTW_SW_LED
+void rtw_hal_sw_led_init(_adapter *padapter)
{
- if (padapter->HalFunc.InitSwLeds)
- padapter->HalFunc.InitSwLeds(padapter);
+ struct led_priv *ledpriv = adapter_to_led(padapter);
+
+ if (ledpriv->bRegUseLed == _FALSE)
+ return;
+
+ if (!is_primary_adapter(padapter))
+ return;
+
+ if (padapter->hal_func.InitSwLeds) {
+ padapter->hal_func.InitSwLeds(padapter);
+ rtw_led_set_ctl_en_mask_primary(padapter);
+ rtw_led_set_iface_en(padapter, 1);
+ }
}
void rtw_hal_sw_led_deinit(_adapter *padapter)
{
- if (padapter->HalFunc.DeInitSwLeds)
- padapter->HalFunc.DeInitSwLeds(padapter);
+ struct led_priv *ledpriv = adapter_to_led(padapter);
+
+ if (ledpriv->bRegUseLed == _FALSE)
+ return;
+
+ if (!is_primary_adapter(padapter))
+ return;
+
+ if (padapter->hal_func.DeInitSwLeds)
+ padapter->hal_func.DeInitSwLeds(padapter);
}
+#endif
u32 rtw_hal_power_on(_adapter *padapter)
{
- return padapter->HalFunc.hal_power_on(padapter);
+ u32 ret = 0;
+ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
+
+ ret = padapter->hal_func.hal_power_on(padapter);
+
+#ifdef CONFIG_BT_COEXIST
+ if ((ret == _SUCCESS) && (pHalData->EEPROMBluetoothCoexist == _TRUE))
+ rtw_btcoex_PowerOnSetting(padapter);
+#endif
+
+ return ret;
}
void rtw_hal_power_off(_adapter *padapter)
{
@@ -165,7 +203,11 @@ void rtw_hal_power_off(_adapter *padapter)
_rtw_memset(macid_ctl->h2c_msr, 0, MACID_NUM_SW_LIMIT);
- padapter->HalFunc.hal_power_off(padapter);
+#ifdef CONFIG_BT_COEXIST
+ rtw_btcoex_PowerOffSetting(padapter);
+#endif
+
+ padapter->hal_func.hal_power_off(padapter);
}
@@ -181,27 +223,34 @@ void rtw_hal_init_opmode(_adapter *padapter)
networkType = Ndis802_11IBSS;
else if (fw_state & WIFI_STATION_STATE)
networkType = Ndis802_11Infrastructure;
+#ifdef CONFIG_AP_MODE
else if (fw_state & WIFI_AP_STATE)
networkType = Ndis802_11APMode;
+#endif
+#ifdef CONFIG_RTW_MESH
+ else if (fw_state & WIFI_MESH_STATE)
+ networkType = Ndis802_11_mesh;
+#endif
else
return;
- rtw_setopmode_cmd(padapter, networkType, _FALSE);
+ rtw_setopmode_cmd(padapter, networkType, RTW_CMDF_DIRECTLY);
}
uint rtw_hal_init(_adapter *padapter)
{
uint status = _SUCCESS;
struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
- PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
int i;
- status = padapter->HalFunc.hal_init(padapter);
+ status = padapter->hal_func.hal_init(padapter);
if (status == _SUCCESS) {
- pHalData->hw_init_completed = _TRUE;
+ rtw_set_hw_init_completed(padapter, _TRUE);
rtw_restore_mac_addr(padapter);
-
+ #ifdef RTW_HALMAC
+ rtw_restore_hw_port_cfg(padapter);
+ #endif
if (padapter->registrypriv.notch_filter == 1)
rtw_hal_notch_filter(padapter, 1);
@@ -218,12 +267,17 @@ uint rtw_hal_init(_adapter *padapter)
rtw_bb_rf_gain_offset(padapter);
#endif /*CONFIG_RF_POWER_TRIM*/
+#if (RTL8822B_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)
+#ifdef CONFIG_DYNAMIC_SOML
+ rtw_dyn_soml_config(padapter);
+#endif
+#endif
+
} else {
- pHalData->hw_init_completed = _FALSE;
- RTW_INFO("rtw_hal_init: hal__init fail\n");
+ rtw_set_hw_init_completed(padapter, _FALSE);
+ RTW_ERR("%s: fail\n", __func__);
}
- RT_TRACE(_module_hal_init_c_, _drv_err_, ("-rtl871x_hal_init:status=0x%x\n", status));
return status;
@@ -233,64 +287,53 @@ uint rtw_hal_deinit(_adapter *padapter)
{
uint status = _SUCCESS;
struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
- PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
int i;
- _func_enter_;
- status = padapter->HalFunc.hal_deinit(padapter);
+ status = padapter->hal_func.hal_deinit(padapter);
if (status == _SUCCESS) {
rtw_led_control(padapter, LED_CTL_POWER_OFF);
- pHalData->hw_init_completed = _FALSE;
+ rtw_set_hw_init_completed(padapter, _FALSE);
} else
RTW_INFO("\n rtw_hal_deinit: hal_init fail\n");
- _func_exit_;
return status;
}
-void rtw_hal_set_hwreg(_adapter *padapter, u8 variable, u8 *val)
+u8 rtw_hal_set_hwreg(_adapter *padapter, u8 variable, u8 *val)
{
- padapter->HalFunc.SetHwRegHandler(padapter, variable, val);
+ return padapter->hal_func.set_hw_reg_handler(padapter, variable, val);
}
void rtw_hal_get_hwreg(_adapter *padapter, u8 variable, u8 *val)
{
- padapter->HalFunc.GetHwRegHandler(padapter, variable, val);
-}
-
-#ifdef CONFIG_C2H_PACKET_EN
-void rtw_hal_set_hwreg_with_buf(_adapter *padapter, u8 variable, u8 *pbuf, int len)
-{
- if (padapter->HalFunc.SetHwRegHandlerWithBuf)
- padapter->HalFunc.SetHwRegHandlerWithBuf(padapter, variable, pbuf, len);
+ padapter->hal_func.GetHwRegHandler(padapter, variable, val);
}
-#endif
u8 rtw_hal_set_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue)
{
- return padapter->HalFunc.SetHalDefVarHandler(padapter, eVariable, pValue);
+ return padapter->hal_func.SetHalDefVarHandler(padapter, eVariable, pValue);
}
u8 rtw_hal_get_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue)
{
- return padapter->HalFunc.GetHalDefVarHandler(padapter, eVariable, pValue);
+ return padapter->hal_func.get_hal_def_var_handler(padapter, eVariable, pValue);
}
void rtw_hal_set_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1, BOOLEAN bSet)
{
- padapter->HalFunc.SetHalODMVarHandler(padapter, eVariable, pValue1, bSet);
+ padapter->hal_func.SetHalODMVarHandler(padapter, eVariable, pValue1, bSet);
}
void rtw_hal_get_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1, PVOID pValue2)
{
- padapter->HalFunc.GetHalODMVarHandler(padapter, eVariable, pValue1, pValue2);
+ padapter->hal_func.GetHalODMVarHandler(padapter, eVariable, pValue1, pValue2);
}
/* FOR SDIO & PCIE */
void rtw_hal_enable_interrupt(_adapter *padapter)
{
#if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI)
- padapter->HalFunc.enable_interrupt(padapter);
+ padapter->hal_func.enable_interrupt(padapter);
#endif /* #if defined(CONFIG_PCI_HCI) || defined (CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) */
}
@@ -298,7 +341,7 @@ void rtw_hal_enable_interrupt(_adapter *padapter)
void rtw_hal_disable_interrupt(_adapter *padapter)
{
#if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI)
- padapter->HalFunc.disable_interrupt(padapter);
+ padapter->hal_func.disable_interrupt(padapter);
#endif /* #if defined(CONFIG_PCI_HCI) || defined (CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) */
}
@@ -306,24 +349,43 @@ void rtw_hal_disable_interrupt(_adapter *padapter)
u8 rtw_hal_check_ips_status(_adapter *padapter)
{
u8 val = _FALSE;
- if (padapter->HalFunc.check_ips_status)
- val = padapter->HalFunc.check_ips_status(padapter);
+ if (padapter->hal_func.check_ips_status)
+ val = padapter->hal_func.check_ips_status(padapter);
else
- RTW_INFO("%s: HalFunc.check_ips_status is NULL!\n", __FUNCTION__);
+ RTW_INFO("%s: hal_func.check_ips_status is NULL!\n", __FUNCTION__);
return val;
}
s32 rtw_hal_fw_dl(_adapter *padapter, u8 wowlan)
{
- return padapter->HalFunc.fw_dl(padapter, wowlan);
+ return padapter->hal_func.fw_dl(padapter, wowlan);
+}
+
+#ifdef RTW_HALMAC
+s32 rtw_hal_fw_mem_dl(_adapter *padapter, enum fw_mem mem)
+{
+ systime dlfw_start_time = rtw_get_current_time();
+ struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+ struct debug_priv *pdbgpriv = &dvobj->drv_dbg;
+ s32 rst = _FALSE;
+
+ rst = padapter->hal_func.fw_mem_dl(padapter, mem);
+ RTW_INFO("%s in %dms\n", __func__, rtw_get_passing_time_ms(dlfw_start_time));
+
+ if (rst == _FALSE)
+ pdbgpriv->dbg_fw_mem_dl_error_cnt++;
+ if (1)
+ RTW_INFO("%s dbg_fw_mem_dl_error_cnt:%d\n", __func__, pdbgpriv->dbg_fw_mem_dl_error_cnt);
+ return rst;
}
+#endif
#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
void rtw_hal_clear_interrupt(_adapter *padapter)
{
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
- padapter->HalFunc.clear_interrupt(padapter);
+ padapter->hal_func.clear_interrupt(padapter);
#endif
}
#endif
@@ -332,14 +394,14 @@ void rtw_hal_clear_interrupt(_adapter *padapter)
u32 rtw_hal_inirp_init(_adapter *padapter)
{
if (is_primary_adapter(padapter))
- return padapter->HalFunc.inirp_init(padapter);
+ return padapter->hal_func.inirp_init(padapter);
return _SUCCESS;
}
u32 rtw_hal_inirp_deinit(_adapter *padapter)
{
if (is_primary_adapter(padapter))
- return padapter->HalFunc.inirp_deinit(padapter);
+ return padapter->hal_func.inirp_deinit(padapter);
return _SUCCESS;
}
@@ -348,26 +410,78 @@ u32 rtw_hal_inirp_deinit(_adapter *padapter)
#if defined(CONFIG_PCI_HCI)
void rtw_hal_irp_reset(_adapter *padapter)
{
- padapter->HalFunc.irp_reset(GET_PRIMARY_ADAPTER(padapter));
+ padapter->hal_func.irp_reset(GET_PRIMARY_ADAPTER(padapter));
+}
+
+void rtw_hal_pci_dbi_write(_adapter *padapter, u16 addr, u8 data)
+{
+ u16 cmd[2];
+
+ cmd[0] = addr;
+ cmd[1] = data;
+
+ padapter->hal_func.set_hw_reg_handler(padapter, HW_VAR_DBI, (u8 *) cmd);
+}
+
+u8 rtw_hal_pci_dbi_read(_adapter *padapter, u16 addr)
+{
+ padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_DBI, (u8 *)(&addr));
+
+ return (u8)addr;
+}
+
+void rtw_hal_pci_mdio_write(_adapter *padapter, u8 addr, u16 data)
+{
+ u16 cmd[2];
+
+ cmd[0] = (u16)addr;
+ cmd[1] = data;
+
+ padapter->hal_func.set_hw_reg_handler(padapter, HW_VAR_MDIO, (u8 *) cmd);
+}
+
+u16 rtw_hal_pci_mdio_read(_adapter *padapter, u8 addr)
+{
+ padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_MDIO, &addr);
+
+ return (u8)addr;
}
+
+u8 rtw_hal_pci_l1off_nic_support(_adapter *padapter)
+{
+ u8 l1off;
+
+ padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_L1OFF_NIC_SUPPORT, &l1off);
+ return l1off;
+}
+
+u8 rtw_hal_pci_l1off_capability(_adapter *padapter)
+{
+ u8 l1off;
+
+ padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_L1OFF_CAPABILITY, &l1off);
+ return l1off;
+}
+
+
#endif /* #if defined(CONFIG_PCI_HCI) */
/* for USB Auto-suspend */
u8 rtw_hal_intf_ps_func(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val)
{
- if (padapter->HalFunc.interface_ps_func)
- return padapter->HalFunc.interface_ps_func(padapter, efunc_id, val);
+ if (padapter->hal_func.interface_ps_func)
+ return padapter->hal_func.interface_ps_func(padapter, efunc_id, val);
return _FAIL;
}
s32 rtw_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe)
{
- return padapter->HalFunc.hal_xmitframe_enqueue(padapter, pxmitframe);
+ return padapter->hal_func.hal_xmitframe_enqueue(padapter, pxmitframe);
}
s32 rtw_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe)
{
- return padapter->HalFunc.hal_xmit(padapter, pxmitframe);
+ return padapter->hal_func.hal_xmit(padapter, pxmitframe);
}
/*
@@ -376,82 +490,79 @@ s32 rtw_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe)
s32 rtw_hal_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe)
{
s32 ret = _FAIL;
- u8 *pframe, subtype;
- struct rtw_ieee80211_hdr *pwlanhdr;
- struct sta_info *psta;
- struct sta_priv *pstapriv = &padapter->stapriv;
update_mgntframe_attrib_addr(padapter, pmgntframe);
- pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
- subtype = GetFrameSubType(pframe); /* bit(7)~bit(2) */
-
- /* pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; */
- /* _rtw_memcpy(pmgntframe->attrib.ra, pwlanhdr->addr1, ETH_ALEN); */
-
-#ifdef CONFIG_IEEE80211W
- if (padapter->securitypriv.binstallBIPkey == _TRUE && (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC ||
- subtype == WIFI_ACTION)) {
- if (IS_MCAST(pmgntframe->attrib.ra) && pmgntframe->attrib.key_type != IEEE80211W_NO_KEY) {
- pmgntframe->attrib.encrypt = _BIP_;
- /* pmgntframe->attrib.bswenc = _TRUE; */
- } else if (pmgntframe->attrib.key_type != IEEE80211W_NO_KEY) {
- psta = rtw_get_stainfo(pstapriv, pmgntframe->attrib.ra);
- if (psta && psta->bpairwise_key_installed == _TRUE) {
- pmgntframe->attrib.encrypt = _AES_;
- pmgntframe->attrib.bswenc = _TRUE;
- } else {
- RTW_INFO("%s, %d, bpairwise_key_installed is FALSE\n", __func__, __LINE__);
- goto no_mgmt_coalesce;
- }
- }
- RTW_INFO("encrypt=%d, bswenc=%d\n", pmgntframe->attrib.encrypt, pmgntframe->attrib.bswenc);
+
+#if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)
+ if ((!MLME_IS_MESH(padapter) && SEC_IS_BIP_KEY_INSTALLED(&padapter->securitypriv) == _TRUE)
+ #ifdef CONFIG_RTW_MESH
+ || (MLME_IS_MESH(padapter) && padapter->mesh_info.mesh_auth_id)
+ #endif
+ )
rtw_mgmt_xmitframe_coalesce(padapter, pmgntframe->pkt, pmgntframe);
- }
-#endif /* CONFIG_IEEE80211W */
+#endif
+
no_mgmt_coalesce:
- ret = padapter->HalFunc.mgnt_xmit(padapter, pmgntframe);
+ ret = padapter->hal_func.mgnt_xmit(padapter, pmgntframe);
return ret;
}
s32 rtw_hal_init_xmit_priv(_adapter *padapter)
{
- return padapter->HalFunc.init_xmit_priv(padapter);
+ return padapter->hal_func.init_xmit_priv(padapter);
}
void rtw_hal_free_xmit_priv(_adapter *padapter)
{
- padapter->HalFunc.free_xmit_priv(padapter);
+ padapter->hal_func.free_xmit_priv(padapter);
}
s32 rtw_hal_init_recv_priv(_adapter *padapter)
{
- return padapter->HalFunc.init_recv_priv(padapter);
+ return padapter->hal_func.init_recv_priv(padapter);
}
void rtw_hal_free_recv_priv(_adapter *padapter)
{
- padapter->HalFunc.free_recv_priv(padapter);
+ padapter->hal_func.free_recv_priv(padapter);
}
-void rtw_hal_update_ra_mask(struct sta_info *psta, u8 rssi_level)
+void rtw_sta_ra_registed(_adapter *padapter, struct sta_info *psta)
{
- _adapter *padapter;
- struct mlme_priv *pmlmepriv;
+ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
- if (!psta)
+ if (psta == NULL) {
+ RTW_ERR(FUNC_ADPT_FMT" sta is NULL\n", FUNC_ADPT_ARG(padapter));
+ rtw_warn_on(1);
return;
+ }
- padapter = psta->padapter;
+#ifdef CONFIG_AP_MODE
+ if (MLME_IS_AP(padapter) || MLME_IS_MESH(padapter)) {
+ if (psta->cmn.aid > padapter->stapriv.max_aid) {
+ RTW_ERR("station aid %d exceed the max number\n", psta->cmn.aid);
+ rtw_warn_on(1);
+ return;
+ }
+ rtw_ap_update_sta_ra_info(padapter, psta);
+ }
+#endif
- pmlmepriv = &(padapter->mlmepriv);
+ psta->cmn.ra_info.ra_bw_mode = rtw_get_tx_bw_mode(padapter, psta);
+ /*set correct initial date rate for each mac_id */
+ hal_data->INIDATA_RATE[psta->cmn.mac_id] = psta->init_rate;
- if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
- add_RATid(padapter, psta, rssi_level);
- else
- padapter->HalFunc.UpdateRAMaskHandler(padapter, psta->mac_id, rssi_level);
+ rtw_phydm_ra_registed(padapter, psta);
}
-void rtw_hal_add_ra_tid(_adapter *padapter, u64 bitmap, u8 *arg, u8 rssi_level)
+void rtw_hal_update_ra_mask(struct sta_info *psta)
{
- padapter->HalFunc.Add_RateATid(padapter, bitmap, arg, rssi_level);
+ _adapter *padapter;
+
+ if (!psta)
+ return;
+
+ padapter = psta->padapter;
+ rtw_sta_ra_registed(padapter, psta);
}
/* Start specifical interface thread */
@@ -459,7 +570,7 @@ void rtw_hal_start_thread(_adapter *padapter)
{
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
#ifndef CONFIG_SDIO_TX_TASKLET
- padapter->HalFunc.run_thread(padapter);
+ padapter->hal_func.run_thread(padapter);
#endif
#endif
}
@@ -469,7 +580,7 @@ void rtw_hal_stop_thread(_adapter *padapter)
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
#ifndef CONFIG_SDIO_TX_TASKLET
- padapter->HalFunc.cancel_thread(padapter);
+ padapter->hal_func.cancel_thread(padapter);
#endif
#endif
@@ -478,22 +589,22 @@ void rtw_hal_stop_thread(_adapter *padapter)
u32 rtw_hal_read_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask)
{
u32 data = 0;
- if (padapter->HalFunc.read_bbreg)
- data = padapter->HalFunc.read_bbreg(padapter, RegAddr, BitMask);
+ if (padapter->hal_func.read_bbreg)
+ data = padapter->hal_func.read_bbreg(padapter, RegAddr, BitMask);
return data;
}
void rtw_hal_write_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data)
{
- if (padapter->HalFunc.write_bbreg)
- padapter->HalFunc.write_bbreg(padapter, RegAddr, BitMask, Data);
+ if (padapter->hal_func.write_bbreg)
+ padapter->hal_func.write_bbreg(padapter, RegAddr, BitMask, Data);
}
-u32 rtw_hal_read_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask)
+u32 rtw_hal_read_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask)
{
u32 data = 0;
- if (padapter->HalFunc.read_rfreg) {
- data = padapter->HalFunc.read_rfreg(padapter, eRFPath, RegAddr, BitMask);
+ if (padapter->hal_func.read_rfreg) {
+ data = padapter->hal_func.read_rfreg(padapter, eRFPath, RegAddr, BitMask);
if (match_rf_read_sniff_ranges(eRFPath, RegAddr, BitMask)) {
RTW_INFO("DBG_IO rtw_hal_read_rfreg(%u, 0x%04x, 0x%08x) read:0x%08x(0x%08x)\n"
@@ -504,16 +615,16 @@ u32 rtw_hal_read_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask
return data;
}
-void rtw_hal_write_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
+void rtw_hal_write_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
{
- if (padapter->HalFunc.write_rfreg) {
+ if (padapter->hal_func.write_rfreg) {
if (match_rf_write_sniff_ranges(eRFPath, RegAddr, BitMask)) {
RTW_INFO("DBG_IO rtw_hal_write_rfreg(%u, 0x%04x, 0x%08x) write:0x%08x(0x%08x)\n"
, eRFPath, RegAddr, BitMask, (Data << PHY_CalculateBitShift(BitMask)), Data);
}
- padapter->HalFunc.write_rfreg(padapter, eRFPath, RegAddr, BitMask, Data);
+ padapter->hal_func.write_rfreg(padapter, eRFPath, RegAddr, BitMask, Data);
#ifdef CONFIG_PCI_HCI
if (!IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(padapter)) /*For N-Series IC, suggest by Jenyu*/
@@ -526,106 +637,103 @@ void rtw_hal_write_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMa
s32 rtw_hal_interrupt_handler(_adapter *padapter)
{
s32 ret = _FAIL;
- ret = padapter->HalFunc.interrupt_handler(padapter);
+ ret = padapter->hal_func.interrupt_handler(padapter);
return ret;
}
#endif
#if defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT)
void rtw_hal_interrupt_handler(_adapter *padapter, u16 pkt_len, u8 *pbuf)
{
- padapter->HalFunc.interrupt_handler(padapter, pkt_len, pbuf);
+ padapter->hal_func.interrupt_handler(padapter, pkt_len, pbuf);
}
#endif
-void rtw_hal_set_bwmode(_adapter *padapter, CHANNEL_WIDTH Bandwidth, u8 Offset)
+void rtw_hal_set_chnl_bw(_adapter *padapter, u8 channel, enum channel_width Bandwidth, u8 Offset40, u8 Offset80)
{
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
- PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
+ u8 cch_160 = Bandwidth == CHANNEL_WIDTH_160 ? channel : 0;
+ u8 cch_80 = Bandwidth == CHANNEL_WIDTH_80 ? channel : 0;
+ u8 cch_40 = Bandwidth == CHANNEL_WIDTH_40 ? channel : 0;
+ u8 cch_20 = Bandwidth == CHANNEL_WIDTH_20 ? channel : 0;
- ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK);
- if (pDM_Odm->RFCalibrateInfo.bIQKInProgress == _TRUE)
+ if (rtw_phydm_is_iqk_in_progress(padapter))
RTW_ERR("%s, %d, IQK may race condition\n", __func__, __LINE__);
- ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK);
- padapter->HalFunc.set_bwmode_handler(padapter, Bandwidth, Offset);
-
-}
-void rtw_hal_set_chan(_adapter *padapter, u8 channel)
-{
- PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
- PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
+#ifdef CONFIG_MP_INCLUDED
+ /* MP mode channel don't use secondary channel */
+ if (rtw_mp_mode_check(padapter) == _FALSE)
+#endif
+ {
+ #if 0
+ if (cch_160 != 0)
+ cch_80 = rtw_get_scch_by_cch_offset(cch_160, CHANNEL_WIDTH_160, Offset80);
+ #endif
+ if (cch_80 != 0)
+ cch_40 = rtw_get_scch_by_cch_offset(cch_80, CHANNEL_WIDTH_80, Offset80);
+ if (cch_40 != 0)
+ cch_20 = rtw_get_scch_by_cch_offset(cch_40, CHANNEL_WIDTH_40, Offset40);
+ }
- ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK);
- if (pDM_Odm->RFCalibrateInfo.bIQKInProgress == _TRUE)
- RTW_ERR("%s, %d, IQK may race condition\n", __func__, __LINE__);
- ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK);
- padapter->HalFunc.set_channel_handler(padapter, channel);
-}
+ pHalData->cch_80 = cch_80;
+ pHalData->cch_40 = cch_40;
+ pHalData->cch_20 = cch_20;
-void rtw_hal_set_chnl_bw(_adapter *padapter, u8 channel, CHANNEL_WIDTH Bandwidth, u8 Offset40, u8 Offset80)
-{
- PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
- PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
+ if (0)
+ RTW_INFO("%s cch:%u, %s, offset40:%u, offset80:%u (%u, %u, %u)\n", __func__
+ , channel, ch_width_str(Bandwidth), Offset40, Offset80
+ , pHalData->cch_80, pHalData->cch_40, pHalData->cch_20);
- ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK);
- if (pDM_Odm->RFCalibrateInfo.bIQKInProgress == _TRUE)
- RTW_ERR("%s, %d, IQK may race condition\n", __func__, __LINE__);
- ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK);
- padapter->HalFunc.set_chnl_bw_handler(padapter, channel, Bandwidth, Offset40, Offset80);
+ padapter->hal_func.set_chnl_bw_handler(padapter, channel, Bandwidth, Offset40, Offset80);
}
void rtw_hal_set_tx_power_level(_adapter *padapter, u8 channel)
{
- if (padapter->HalFunc.set_tx_power_level_handler)
- padapter->HalFunc.set_tx_power_level_handler(padapter, channel);
+ if (padapter->hal_func.set_tx_power_level_handler)
+ padapter->hal_func.set_tx_power_level_handler(padapter, channel);
}
void rtw_hal_get_tx_power_level(_adapter *padapter, s32 *powerlevel)
{
- if (padapter->HalFunc.get_tx_power_level_handler)
- padapter->HalFunc.get_tx_power_level_handler(padapter, powerlevel);
+ if (padapter->hal_func.get_tx_power_level_handler)
+ padapter->hal_func.get_tx_power_level_handler(padapter, powerlevel);
}
void rtw_hal_dm_watchdog(_adapter *padapter)
{
- if (!is_primary_adapter(padapter))
- return;
-
-#ifdef CONFIG_MCC_MODE
- if (MCC_EN(padapter)) {
- if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
- return;
- }
-#endif /* CONFIG_MCC_MODE */
- padapter->HalFunc.hal_dm_watchdog(padapter);
+ rtw_hal_turbo_edca(padapter);
+ padapter->hal_func.hal_dm_watchdog(padapter);
+#ifdef CONFIG_PCI_DYNAMIC_ASPM
+ rtw_pci_aspm_config_dynamic_l1_ilde_time(padapter);
+#endif
}
#ifdef CONFIG_LPS_LCLK_WD_TIMER
void rtw_hal_dm_watchdog_in_lps(_adapter *padapter)
{
#if defined(CONFIG_CONCURRENT_MODE)
+#ifndef CONFIG_FW_MULTI_PORT_SUPPORT
if (padapter->hw_port != HW_PORT0)
return;
+#endif
#endif
- if (adapter_to_pwrctl(padapter)->bFwCurrentInPSMode == _TRUE) {
- padapter->HalFunc.hal_dm_watchdog_in_lps(padapter);/* this fuction caller is in interrupt context */
- }
+ if (adapter_to_pwrctl(padapter)->bFwCurrentInPSMode == _TRUE)
+ rtw_phydm_watchdog_in_lps_lclk(padapter);/* this function caller is in interrupt context */
}
-#endif
+#endif /*CONFIG_LPS_LCLK_WD_TIMER*/
void rtw_hal_bcn_related_reg_setting(_adapter *padapter)
{
- padapter->HalFunc.SetBeaconRelatedRegistersHandler(padapter);
+ padapter->hal_func.SetBeaconRelatedRegistersHandler(padapter);
}
#ifdef CONFIG_HOSTAPD_MLME
s32 rtw_hal_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt)
{
- if (padapter->HalFunc.hostap_mgnt_xmit_entry)
- return padapter->HalFunc.hostap_mgnt_xmit_entry(padapter, pkt);
+ if (padapter->hal_func.hostap_mgnt_xmit_entry)
+ return padapter->hal_func.hostap_mgnt_xmit_entry(padapter, pkt);
return _FAIL;
}
#endif /* CONFIG_HOSTAPD_MLME */
@@ -633,49 +741,44 @@ s32 rtw_hal_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt)
#ifdef DBG_CONFIG_ERROR_DETECT
void rtw_hal_sreset_init(_adapter *padapter)
{
- padapter->HalFunc.sreset_init_value(padapter);
+ padapter->hal_func.sreset_init_value(padapter);
}
void rtw_hal_sreset_reset(_adapter *padapter)
{
padapter = GET_PRIMARY_ADAPTER(padapter);
- padapter->HalFunc.silentreset(padapter);
+ padapter->hal_func.silentreset(padapter);
}
void rtw_hal_sreset_reset_value(_adapter *padapter)
{
- padapter->HalFunc.sreset_reset_value(padapter);
+ padapter->hal_func.sreset_reset_value(padapter);
}
void rtw_hal_sreset_xmit_status_check(_adapter *padapter)
{
- if (!is_primary_adapter(padapter))
- return;
-
- padapter->HalFunc.sreset_xmit_status_check(padapter);
+ padapter->hal_func.sreset_xmit_status_check(padapter);
}
void rtw_hal_sreset_linked_status_check(_adapter *padapter)
{
- if (!is_primary_adapter(padapter))
- return;
- padapter->HalFunc.sreset_linked_status_check(padapter);
+ padapter->hal_func.sreset_linked_status_check(padapter);
}
u8 rtw_hal_sreset_get_wifi_status(_adapter *padapter)
{
- return padapter->HalFunc.sreset_get_wifi_status(padapter);
+ return padapter->hal_func.sreset_get_wifi_status(padapter);
}
bool rtw_hal_sreset_inprogress(_adapter *padapter)
{
padapter = GET_PRIMARY_ADAPTER(padapter);
- return padapter->HalFunc.sreset_inprogress(padapter);
+ return padapter->hal_func.sreset_inprogress(padapter);
}
#endif /* DBG_CONFIG_ERROR_DETECT */
#ifdef CONFIG_IOL
-int rtw_hal_iol_cmd(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt)
+int rtw_hal_iol_cmd(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_waiting_ms, u32 bndy_cnt)
{
- if (adapter->HalFunc.IOL_exec_cmds_sync)
- return adapter->HalFunc.IOL_exec_cmds_sync(adapter, xmit_frame, max_wating_ms, bndy_cnt);
+ if (adapter->hal_func.IOL_exec_cmds_sync)
+ return adapter->hal_func.IOL_exec_cmds_sync(adapter, xmit_frame, max_waiting_ms, bndy_cnt);
return _FAIL;
}
#endif
@@ -683,116 +786,371 @@ int rtw_hal_iol_cmd(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wat
#ifdef CONFIG_XMIT_THREAD_MODE
s32 rtw_hal_xmit_thread_handler(_adapter *padapter)
{
- return padapter->HalFunc.xmit_thread_handler(padapter);
+ return padapter->hal_func.xmit_thread_handler(padapter);
+}
+#endif
+
+#ifdef CONFIG_RECV_THREAD_MODE
+s32 rtw_hal_recv_hdl(_adapter *adapter)
+{
+ return adapter->hal_func.recv_hdl(adapter);
}
#endif
void rtw_hal_notch_filter(_adapter *adapter, bool enable)
{
- if (adapter->HalFunc.hal_notch_filter)
- adapter->HalFunc.hal_notch_filter(adapter, enable);
+ if (adapter->hal_func.hal_notch_filter)
+ adapter->hal_func.hal_notch_filter(adapter, enable);
}
-bool rtw_hal_c2h_valid(_adapter *adapter, u8 *buf)
+#ifdef CONFIG_FW_C2H_REG
+inline bool rtw_hal_c2h_valid(_adapter *adapter, u8 *buf)
{
HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
- HAL_VERSION *hal_ver = &HalData->VersionID;
+ HAL_VERSION *hal_ver = &HalData->version_id;
bool ret = _FAIL;
- if (IS_8188E(*hal_ver))
- ret = c2h_evt_valid((struct c2h_evt_hdr *)buf);
- else if (IS_8192E(*hal_ver) || IS_8812_SERIES(*hal_ver) || IS_8821_SERIES(*hal_ver) || IS_8723B_SERIES(*hal_ver))
- ret = c2h_evt_valid((struct c2h_evt_hdr_88xx *)buf);
- else
- rtw_warn_on(1);
+ ret = C2H_ID_88XX(buf) || C2H_PLEN_88XX(buf);
return ret;
}
-s32 rtw_hal_c2h_evt_read(_adapter *adapter, u8 *buf)
+inline s32 rtw_hal_c2h_evt_read(_adapter *adapter, u8 *buf)
{
HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
- HAL_VERSION *hal_ver = &HalData->VersionID;
+ HAL_VERSION *hal_ver = &HalData->version_id;
s32 ret = _FAIL;
- if (IS_8188E(*hal_ver))
- ret = c2h_evt_read(adapter, buf);
- else if (IS_8192E(*hal_ver) || IS_8812_SERIES(*hal_ver) || IS_8821_SERIES(*hal_ver) || IS_8723B_SERIES(*hal_ver))
- ret = c2h_evt_read_88xx(adapter, buf);
- else
- rtw_warn_on(1);
+ ret = c2h_evt_read_88xx(adapter, buf);
return ret;
}
-s32 rtw_hal_c2h_handler(_adapter *adapter, u8 *c2h_evt)
+bool rtw_hal_c2h_reg_hdr_parse(_adapter *adapter, u8 *buf, u8 *id, u8 *seq, u8 *plen, u8 **payload)
+{
+ HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
+ HAL_VERSION *hal_ver = &HalData->version_id;
+ bool ret = _FAIL;
+
+ *id = C2H_ID_88XX(buf);
+ *seq = C2H_SEQ_88XX(buf);
+ *plen = C2H_PLEN_88XX(buf);
+ *payload = C2H_PAYLOAD_88XX(buf);
+ ret = _SUCCESS;
+
+ return ret;
+}
+#endif /* CONFIG_FW_C2H_REG */
+
+#ifdef CONFIG_FW_C2H_PKT
+bool rtw_hal_c2h_pkt_hdr_parse(_adapter *adapter, u8 *buf, u16 len, u8 *id, u8 *seq, u8 *plen, u8 **payload)
+{
+ HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter);
+ HAL_VERSION *hal_ver = &HalData->version_id;
+ bool ret = _FAIL;
+
+ if (!buf || len > 256 || len < 3)
+ goto exit;
+
+ *id = C2H_ID_88XX(buf);
+ *seq = C2H_SEQ_88XX(buf);
+ *plen = len - 2;
+ *payload = C2H_PAYLOAD_88XX(buf);
+ ret = _SUCCESS;
+
+exit:
+ return ret;
+}
+#endif /* CONFIG_FW_C2H_PKT */
+
+#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTL8723B)
+#include /* for MPTBT_FwC2hBtMpCtrl */
+#endif
+s32 c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload)
+{
+ u8 sub_id = 0;
+ s32 ret = _SUCCESS;
+
+ switch (id) {
+ case C2H_FW_SCAN_COMPLETE:
+ RTW_INFO("[C2H], FW Scan Complete\n");
+ break;
+
+#ifdef CONFIG_BT_COEXIST
+ case C2H_BT_INFO:
+ rtw_btcoex_BtInfoNotify(adapter, plen, payload);
+ break;
+ case C2H_BT_MP_INFO:
+ #if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTL8723B)
+ MPTBT_FwC2hBtMpCtrl(adapter, payload, plen);
+ #endif
+ rtw_btcoex_BtMpRptNotify(adapter, plen, payload);
+ break;
+ case C2H_MAILBOX_STATUS:
+ RTW_DBG_DUMP("C2H_MAILBOX_STATUS: ", payload, plen);
+ break;
+ case C2H_WLAN_INFO:
+ rtw_btcoex_WlFwDbgInfoNotify(adapter, payload, plen);
+ break;
+#endif /* CONFIG_BT_COEXIST */
+
+ case C2H_IQK_FINISH:
+ c2h_iqk_offload(adapter, payload, plen);
+ break;
+
+#if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)
+ case C2H_FW_CHNL_SWITCH_COMPLETE:
+ rtw_tdls_chsw_oper_done(adapter);
+ break;
+ case C2H_BCN_EARLY_RPT:
+ rtw_tdls_ch_sw_back_to_base_chnl(adapter);
+ break;
+#endif
+
+#ifdef CONFIG_MCC_MODE
+ case C2H_MCC:
+ rtw_hal_mcc_c2h_handler(adapter, plen, payload);
+ break;
+#endif
+
+#ifdef CONFIG_RTW_MAC_HIDDEN_RPT
+ case C2H_MAC_HIDDEN_RPT:
+ c2h_mac_hidden_rpt_hdl(adapter, payload, plen);
+ break;
+ case C2H_MAC_HIDDEN_RPT_2:
+ c2h_mac_hidden_rpt_2_hdl(adapter, payload, plen);
+ break;
+#endif
+
+ case C2H_DEFEATURE_DBG:
+ c2h_defeature_dbg_hdl(adapter, payload, plen);
+ break;
+
+#ifdef CONFIG_RTW_CUSTOMER_STR
+ case C2H_CUSTOMER_STR_RPT:
+ c2h_customer_str_rpt_hdl(adapter, payload, plen);
+ break;
+ case C2H_CUSTOMER_STR_RPT_2:
+ c2h_customer_str_rpt_2_hdl(adapter, payload, plen);
+ break;
+#endif
+#ifdef RTW_PER_CMD_SUPPORT_FW
+ case C2H_PER_RATE_RPT:
+ c2h_per_rate_rpt_hdl(adapter, payload, plen);
+ break;
+#endif
+ case C2H_EXTEND:
+ sub_id = payload[0];
+ /* no handle, goto default */
+ // fallthrough
+ default:
+ if (phydm_c2H_content_parsing(adapter_to_phydm(adapter), id, plen, payload) != TRUE)
+ ret = _FAIL;
+ break;
+ }
+
+exit:
+ if (ret != _SUCCESS) {
+ if (id == C2H_EXTEND)
+ RTW_WARN("%s: unknown C2H(0x%02x, 0x%02x)\n", __func__, id, sub_id);
+ else
+ RTW_WARN("%s: unknown C2H(0x%02x)\n", __func__, id);
+ }
+
+ return ret;
+}
+
+#ifndef RTW_HALMAC
+s32 rtw_hal_c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload)
{
s32 ret = _FAIL;
- if (adapter->HalFunc.c2h_handler)
- ret = adapter->HalFunc.c2h_handler(adapter, c2h_evt);
+
+ ret = adapter->hal_func.c2h_handler(adapter, id, seq, plen, payload);
+ if (ret != _SUCCESS)
+ ret = c2h_handler(adapter, id, seq, plen, payload);
+
return ret;
}
-c2h_id_filter rtw_hal_c2h_id_filter_ccx(_adapter *adapter)
+s32 rtw_hal_c2h_id_handle_directly(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload)
{
- return adapter->HalFunc.c2h_id_filter_ccx;
+ switch (id) {
+ case C2H_CCX_TX_RPT:
+ case C2H_BT_MP_INFO:
+ case C2H_FW_CHNL_SWITCH_COMPLETE:
+ case C2H_IQK_FINISH:
+ case C2H_MCC:
+ case C2H_BCN_EARLY_RPT:
+ case C2H_AP_REQ_TXRPT:
+ case C2H_SPC_STAT:
+ return _TRUE;
+ default:
+ return _FALSE;
+ }
}
+#endif /* !RTW_HALMAC */
s32 rtw_hal_is_disable_sw_channel_plan(PADAPTER padapter)
{
return GET_HAL_DATA(padapter)->bDisableSWChannelPlan;
}
-s32 rtw_hal_macid_sleep(PADAPTER padapter, u8 macid)
+static s32 _rtw_hal_macid_sleep(_adapter *adapter, u8 macid, u8 sleep)
{
- struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
- struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
- u8 support;
-
- support = _FALSE;
- rtw_hal_get_def_var(padapter, HAL_DEF_MACID_SLEEP, &support);
- if (_FALSE == support)
- return _FAIL;
+ struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
+ u16 reg_sleep;
+ u8 bit_shift;
+ u32 val32;
+ s32 ret = _FAIL;
if (macid >= macid_ctl->num) {
- RTW_ERR(FUNC_ADPT_FMT": Invalid macid(%u)\n",
- FUNC_ADPT_ARG(padapter), macid);
- return _FAIL;
+ RTW_ERR(ADPT_FMT" %s invalid macid(%u)\n"
+ , ADPT_ARG(adapter), sleep ? "sleep" : "wakeup" , macid);
+ goto exit;
+ }
+
+ if (macid < 32) {
+ reg_sleep = macid_ctl->reg_sleep_m0;
+ bit_shift = macid;
+ #if (MACID_NUM_SW_LIMIT > 32)
+ } else if (macid < 64) {
+ reg_sleep = macid_ctl->reg_sleep_m1;
+ bit_shift = macid - 32;
+ #endif
+ #if (MACID_NUM_SW_LIMIT > 64)
+ } else if (macid < 96) {
+ reg_sleep = macid_ctl->reg_sleep_m2;
+ bit_shift = macid - 64;
+ #endif
+ #if (MACID_NUM_SW_LIMIT > 96)
+ } else if (macid < 128) {
+ reg_sleep = macid_ctl->reg_sleep_m3;
+ bit_shift = macid - 96;
+ #endif
+ } else {
+ rtw_warn_on(1);
+ goto exit;
}
- rtw_hal_set_hwreg(padapter, HW_VAR_MACID_SLEEP, &macid);
+ if (!reg_sleep) {
+ rtw_warn_on(1);
+ goto exit;
+ }
- return _SUCCESS;
+ val32 = rtw_read32(adapter, reg_sleep);
+ RTW_INFO(ADPT_FMT" %s macid=%d, ori reg_0x%03x=0x%08x\n"
+ , ADPT_ARG(adapter), sleep ? "sleep" : "wakeup"
+ , macid, reg_sleep, val32);
+
+ ret = _SUCCESS;
+
+ if (sleep) {
+ if (val32 & BIT(bit_shift))
+ goto exit;
+ val32 |= BIT(bit_shift);
+ } else {
+ if (!(val32 & BIT(bit_shift)))
+ goto exit;
+ val32 &= ~BIT(bit_shift);
+ }
+
+ rtw_write32(adapter, reg_sleep, val32);
+
+exit:
+ return ret;
}
-s32 rtw_hal_macid_wakeup(PADAPTER padapter, u8 macid)
+inline s32 rtw_hal_macid_sleep(_adapter *adapter, u8 macid)
{
- struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
- struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
- u8 support;
+ return _rtw_hal_macid_sleep(adapter, macid, 1);
+}
- support = _FALSE;
- rtw_hal_get_def_var(padapter, HAL_DEF_MACID_SLEEP, &support);
- if (_FALSE == support)
- return _FAIL;
+inline s32 rtw_hal_macid_wakeup(_adapter *adapter, u8 macid)
+{
+ return _rtw_hal_macid_sleep(adapter, macid, 0);
+}
- if (macid >= macid_ctl->num) {
- RTW_ERR(FUNC_ADPT_FMT": Invalid macid(%u)\n",
- FUNC_ADPT_ARG(padapter), macid);
- return _FAIL;
- }
+static s32 _rtw_hal_macid_bmp_sleep(_adapter *adapter, struct macid_bmp *bmp, u8 sleep)
+{
+ struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
+ u16 reg_sleep;
+ u32 *m = &bmp->m0;
+ u8 mid = 0;
+ u32 val32;
+
+ do {
+ if (*m == 0)
+ goto move_next;
+
+ if (mid == 0)
+ reg_sleep = macid_ctl->reg_sleep_m0;
+ #if (MACID_NUM_SW_LIMIT > 32)
+ else if (mid == 1)
+ reg_sleep = macid_ctl->reg_sleep_m1;
+ #endif
+ #if (MACID_NUM_SW_LIMIT > 64)
+ else if (mid == 2)
+ reg_sleep = macid_ctl->reg_sleep_m2;
+ #endif
+ #if (MACID_NUM_SW_LIMIT > 96)
+ else if (mid == 3)
+ reg_sleep = macid_ctl->reg_sleep_m3;
+ #endif
+ else {
+ rtw_warn_on(1);
+ break;
+ }
+
+ if (!reg_sleep) {
+ rtw_warn_on(1);
+ break;
+ }
+
+ val32 = rtw_read32(adapter, reg_sleep);
+ RTW_INFO(ADPT_FMT" %s m%u=0x%08x, ori reg_0x%03x=0x%08x\n"
+ , ADPT_ARG(adapter), sleep ? "sleep" : "wakeup"
+ , mid, *m, reg_sleep, val32);
+
+ if (sleep) {
+ if ((val32 & *m) == *m)
+ goto move_next;
+ val32 |= *m;
+ } else {
+ if ((val32 & *m) == 0)
+ goto move_next;
+ val32 &= ~(*m);
+ }
- rtw_hal_set_hwreg(padapter, HW_VAR_MACID_WAKEUP, &macid);
+ rtw_write32(adapter, reg_sleep, val32);
+
+move_next:
+ m++;
+ mid++;
+ } while (mid * 32 < MACID_NUM_SW_LIMIT);
return _SUCCESS;
}
+inline s32 rtw_hal_macid_sleep_all_used(_adapter *adapter)
+{
+ struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
+
+ return _rtw_hal_macid_bmp_sleep(adapter, &macid_ctl->used, 1);
+}
+
+inline s32 rtw_hal_macid_wakeup_all_used(_adapter *adapter)
+{
+ struct macid_ctl_t *macid_ctl = adapter_to_macidctl(adapter);
+
+ return _rtw_hal_macid_bmp_sleep(adapter, &macid_ctl->used, 0);
+}
+
s32 rtw_hal_fill_h2c_cmd(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer)
{
_adapter *pri_adapter = GET_PRIMARY_ADAPTER(padapter);
- if (pri_adapter->bFWReady == _TRUE)
- return padapter->HalFunc.fill_h2c_cmd(padapter, ElementID, CmdLen, pCmdBuffer);
+ if (GET_HAL_DATA(pri_adapter)->bFWReady == _TRUE)
+ return padapter->hal_func.fill_h2c_cmd(padapter, ElementID, CmdLen, pCmdBuffer);
else if (padapter->registrypriv.mp_mode == 0)
RTW_PRINT(FUNC_ADPT_FMT" FW doesn't exit when no MP mode, by pass H2C id:0x%02x\n"
, FUNC_ADPT_ARG(padapter), ElementID);
@@ -802,52 +1160,64 @@ s32 rtw_hal_fill_h2c_cmd(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBu
void rtw_hal_fill_fake_txdesc(_adapter *padapter, u8 *pDesc, u32 BufferLen,
u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame)
{
- padapter->HalFunc.fill_fake_txdesc(padapter, pDesc, BufferLen, IsPsPoll, IsBTQosNull, bDataFrame);
+ padapter->hal_func.fill_fake_txdesc(padapter, pDesc, BufferLen, IsPsPoll, IsBTQosNull, bDataFrame);
}
+
u8 rtw_hal_get_txbuff_rsvd_page_num(_adapter *adapter, bool wowlan)
{
- return adapter->HalFunc.hal_get_tx_buff_rsvd_page_num(adapter, wowlan);
+ u8 num = 0;
+
+
+ if (adapter->hal_func.hal_get_tx_buff_rsvd_page_num) {
+ num = adapter->hal_func.hal_get_tx_buff_rsvd_page_num(adapter, wowlan);
+ } else {
+#ifdef RTW_HALMAC
+ num = GET_HAL_DATA(adapter)->drv_rsvd_page_number;
+#endif /* RTW_HALMAC */
+ }
+
+ return num;
}
#ifdef CONFIG_GPIO_API
void rtw_hal_update_hisr_hsisr_ind(_adapter *padapter, u32 flag)
{
- if (padapter->HalFunc.update_hisr_hsisr_ind)
- padapter->HalFunc.update_hisr_hsisr_ind(padapter, flag);
+ if (padapter->hal_func.update_hisr_hsisr_ind)
+ padapter->hal_func.update_hisr_hsisr_ind(padapter, flag);
}
int rtw_hal_gpio_func_check(_adapter *padapter, u8 gpio_num)
{
int ret = _SUCCESS;
- if (padapter->HalFunc.hal_gpio_func_check)
- ret = padapter->HalFunc.hal_gpio_func_check(padapter, gpio_num);
+ if (padapter->hal_func.hal_gpio_func_check)
+ ret = padapter->hal_func.hal_gpio_func_check(padapter, gpio_num);
return ret;
}
void rtw_hal_gpio_multi_func_reset(_adapter *padapter, u8 gpio_num)
{
- if (padapter->HalFunc.hal_gpio_multi_func_reset)
- padapter->HalFunc.hal_gpio_multi_func_reset(padapter, gpio_num);
+ if (padapter->hal_func.hal_gpio_multi_func_reset)
+ padapter->hal_func.hal_gpio_multi_func_reset(padapter, gpio_num);
}
#endif
void rtw_hal_fw_correct_bcn(_adapter *padapter)
{
- if (padapter->HalFunc.fw_correct_bcn)
- padapter->HalFunc.fw_correct_bcn(padapter);
+ if (padapter->hal_func.fw_correct_bcn)
+ padapter->hal_func.fw_correct_bcn(padapter);
}
-void rtw_hal_set_tx_power_index(PADAPTER padapter, u32 powerindex, u8 rfpath, u8 rate)
+void rtw_hal_set_tx_power_index(PADAPTER padapter, u32 powerindex, enum rf_path rfpath, u8 rate)
{
- return padapter->HalFunc.set_tx_power_index_handler(padapter, powerindex, rfpath, rate);
+ return padapter->hal_func.set_tx_power_index_handler(padapter, powerindex, rfpath, rate);
}
-u8 rtw_hal_get_tx_power_index(PADAPTER padapter, u8 rfpath, u8 rate, u8 bandwidth, u8 channel)
+u8 rtw_hal_get_tx_power_index(PADAPTER padapter, enum rf_path rfpath, u8 rate, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic)
{
- return padapter->HalFunc.get_tx_power_index_handler(padapter, rfpath, rate, bandwidth, channel);
+ return padapter->hal_func.get_tx_power_index_handler(padapter, rfpath, rate, bandwidth, channel, tic);
}
#ifdef RTW_HALMAC
@@ -861,7 +1231,7 @@ u8 rtw_hal_get_tx_power_index(PADAPTER padapter, u8 rfpath, u8 rate, u8 bandwidt
*/
u8 rtw_hal_init_mac_register(PADAPTER adapter)
{
- return adapter->HalFunc.init_mac_register(adapter);
+ return adapter->hal_func.init_mac_register(adapter);
}
/*
@@ -874,87 +1244,102 @@ u8 rtw_hal_init_mac_register(PADAPTER adapter)
*/
u8 rtw_hal_init_phy(PADAPTER adapter)
{
- return adapter->HalFunc.init_phy(adapter);
+ return adapter->hal_func.init_phy(adapter);
}
#endif /* RTW_HALMAC */
+#ifdef CONFIG_RFKILL_POLL
+bool rtw_hal_rfkill_poll(_adapter *adapter, u8 *valid)
+{
+ bool ret;
+
+ if (adapter->hal_func.hal_radio_onoff_check)
+ ret = adapter->hal_func.hal_radio_onoff_check(adapter, valid);
+ else {
+ *valid = 0;
+ ret = _FALSE;
+ }
+ return ret;
+}
+#endif
+
#define rtw_hal_error_msg(ops_fun) \
- RTW_PRINT("### %s - Error : Please hook HalFunc.%s ###\n", __FUNCTION__, ops_fun)
+ RTW_PRINT("### %s - Error : Please hook hal_func.%s ###\n", __FUNCTION__, ops_fun)
u8 rtw_hal_ops_check(_adapter *padapter)
{
u8 ret = _SUCCESS;
#if 1
/*** initialize section ***/
- if (NULL == padapter->HalFunc.read_chip_version) {
+ if (NULL == padapter->hal_func.read_chip_version) {
rtw_hal_error_msg("read_chip_version");
ret = _FAIL;
}
- if (NULL == padapter->HalFunc.init_default_value) {
+ if (NULL == padapter->hal_func.init_default_value) {
rtw_hal_error_msg("init_default_value");
ret = _FAIL;
}
- if (NULL == padapter->HalFunc.intf_chip_configure) {
+ if (NULL == padapter->hal_func.intf_chip_configure) {
rtw_hal_error_msg("intf_chip_configure");
ret = _FAIL;
}
- if (NULL == padapter->HalFunc.read_adapter_info) {
+ if (NULL == padapter->hal_func.read_adapter_info) {
rtw_hal_error_msg("read_adapter_info");
ret = _FAIL;
}
- if (NULL == padapter->HalFunc.hal_power_on) {
+ if (NULL == padapter->hal_func.hal_power_on) {
rtw_hal_error_msg("hal_power_on");
ret = _FAIL;
}
- if (NULL == padapter->HalFunc.hal_power_off) {
+ if (NULL == padapter->hal_func.hal_power_off) {
rtw_hal_error_msg("hal_power_off");
ret = _FAIL;
}
- if (NULL == padapter->HalFunc.hal_init) {
+ if (NULL == padapter->hal_func.hal_init) {
rtw_hal_error_msg("hal_init");
ret = _FAIL;
}
- if (NULL == padapter->HalFunc.hal_deinit) {
+ if (NULL == padapter->hal_func.hal_deinit) {
rtw_hal_error_msg("hal_deinit");
ret = _FAIL;
}
/*** xmit section ***/
- if (NULL == padapter->HalFunc.init_xmit_priv) {
+ if (NULL == padapter->hal_func.init_xmit_priv) {
rtw_hal_error_msg("init_xmit_priv");
ret = _FAIL;
}
- if (NULL == padapter->HalFunc.free_xmit_priv) {
+ if (NULL == padapter->hal_func.free_xmit_priv) {
rtw_hal_error_msg("free_xmit_priv");
ret = _FAIL;
}
- if (NULL == padapter->HalFunc.hal_xmit) {
+ if (NULL == padapter->hal_func.hal_xmit) {
rtw_hal_error_msg("hal_xmit");
ret = _FAIL;
}
- if (NULL == padapter->HalFunc.mgnt_xmit) {
+ if (NULL == padapter->hal_func.mgnt_xmit) {
rtw_hal_error_msg("mgnt_xmit");
ret = _FAIL;
}
#ifdef CONFIG_XMIT_THREAD_MODE
- if (NULL == padapter->HalFunc.xmit_thread_handler) {
+ if (NULL == padapter->hal_func.xmit_thread_handler) {
rtw_hal_error_msg("xmit_thread_handler");
ret = _FAIL;
}
#endif
- if (NULL == padapter->HalFunc.hal_xmitframe_enqueue) {
+ if (NULL == padapter->hal_func.hal_xmitframe_enqueue) {
rtw_hal_error_msg("hal_xmitframe_enqueue");
ret = _FAIL;
}
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
#ifndef CONFIG_SDIO_TX_TASKLET
- if (NULL == padapter->HalFunc.run_thread) {
+ if (NULL == padapter->hal_func.run_thread) {
rtw_hal_error_msg("run_thread");
ret = _FAIL;
}
- if (NULL == padapter->HalFunc.cancel_thread) {
+ if (NULL == padapter->hal_func.cancel_thread) {
rtw_hal_error_msg("cancel_thread");
ret = _FAIL;
}
@@ -962,20 +1347,26 @@ u8 rtw_hal_ops_check(_adapter *padapter)
#endif
/*** recv section ***/
- if (NULL == padapter->HalFunc.init_recv_priv) {
+ if (NULL == padapter->hal_func.init_recv_priv) {
rtw_hal_error_msg("init_recv_priv");
ret = _FAIL;
}
- if (NULL == padapter->HalFunc.free_recv_priv) {
+ if (NULL == padapter->hal_func.free_recv_priv) {
rtw_hal_error_msg("free_recv_priv");
ret = _FAIL;
}
+#ifdef CONFIG_RECV_THREAD_MODE
+ if (NULL == padapter->hal_func.recv_hdl) {
+ rtw_hal_error_msg("recv_hdl");
+ ret = _FAIL;
+ }
+#endif
#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
- if (NULL == padapter->HalFunc.inirp_init) {
+ if (NULL == padapter->hal_func.inirp_init) {
rtw_hal_error_msg("inirp_init");
ret = _FAIL;
}
- if (NULL == padapter->HalFunc.inirp_deinit) {
+ if (NULL == padapter->hal_func.inirp_deinit) {
rtw_hal_error_msg("inirp_deinit");
ret = _FAIL;
}
@@ -984,24 +1375,24 @@ u8 rtw_hal_ops_check(_adapter *padapter)
/*** interrupt hdl section ***/
#if defined(CONFIG_PCI_HCI)
- if (NULL == padapter->HalFunc.irp_reset) {
+ if (NULL == padapter->hal_func.irp_reset) {
rtw_hal_error_msg("irp_reset");
ret = _FAIL;
}
#endif/*#if defined(CONFIG_PCI_HCI)*/
#if (defined(CONFIG_PCI_HCI)) || (defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT))
- if (NULL == padapter->HalFunc.interrupt_handler) {
+ if (NULL == padapter->hal_func.interrupt_handler) {
rtw_hal_error_msg("interrupt_handler");
ret = _FAIL;
}
#endif /*#if (defined(CONFIG_PCI_HCI)) || (defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT))*/
#if defined(CONFIG_PCI_HCI) || defined(CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI)
- if (NULL == padapter->HalFunc.enable_interrupt) {
+ if (NULL == padapter->hal_func.enable_interrupt) {
rtw_hal_error_msg("enable_interrupt");
ret = _FAIL;
}
- if (NULL == padapter->HalFunc.disable_interrupt) {
+ if (NULL == padapter->hal_func.disable_interrupt) {
rtw_hal_error_msg("disable_interrupt");
ret = _FAIL;
}
@@ -1009,181 +1400,172 @@ u8 rtw_hal_ops_check(_adapter *padapter)
/*** DM section ***/
- if (NULL == padapter->HalFunc.dm_init) {
+ if (NULL == padapter->hal_func.dm_init) {
rtw_hal_error_msg("dm_init");
ret = _FAIL;
}
- if (NULL == padapter->HalFunc.dm_deinit) {
+ if (NULL == padapter->hal_func.dm_deinit) {
rtw_hal_error_msg("dm_deinit");
ret = _FAIL;
}
- if (NULL == padapter->HalFunc.hal_dm_watchdog) {
+ if (NULL == padapter->hal_func.hal_dm_watchdog) {
rtw_hal_error_msg("hal_dm_watchdog");
ret = _FAIL;
}
-#ifdef CONFIG_LPS_LCLK_WD_TIMER
- if (NULL == padapter->HalFunc.hal_dm_watchdog_in_lps) {
- rtw_hal_error_msg("hal_dm_watchdog_in_lps");
- ret = _FAIL;
- }
-#endif
/*** xxx section ***/
- if (NULL == padapter->HalFunc.set_bwmode_handler) {
- rtw_hal_error_msg("set_bwmode_handler");
- ret = _FAIL;
- }
-
- if (NULL == padapter->HalFunc.set_channel_handler) {
- rtw_hal_error_msg("set_channel_handler");
- ret = _FAIL;
- }
-
- if (NULL == padapter->HalFunc.set_chnl_bw_handler) {
+ if (NULL == padapter->hal_func.set_chnl_bw_handler) {
rtw_hal_error_msg("set_chnl_bw_handler");
ret = _FAIL;
}
- if (NULL == padapter->HalFunc.SetHwRegHandler) {
- rtw_hal_error_msg("SetHwRegHandler");
+ if (NULL == padapter->hal_func.set_hw_reg_handler) {
+ rtw_hal_error_msg("set_hw_reg_handler");
ret = _FAIL;
}
- if (NULL == padapter->HalFunc.GetHwRegHandler) {
+ if (NULL == padapter->hal_func.GetHwRegHandler) {
rtw_hal_error_msg("GetHwRegHandler");
ret = _FAIL;
}
- if (NULL == padapter->HalFunc.GetHalDefVarHandler) {
- rtw_hal_error_msg("GetHalDefVarHandler");
+ if (NULL == padapter->hal_func.get_hal_def_var_handler) {
+ rtw_hal_error_msg("get_hal_def_var_handler");
ret = _FAIL;
}
- if (NULL == padapter->HalFunc.SetHalDefVarHandler) {
+ if (NULL == padapter->hal_func.SetHalDefVarHandler) {
rtw_hal_error_msg("SetHalDefVarHandler");
ret = _FAIL;
}
- if (NULL == padapter->HalFunc.GetHalODMVarHandler) {
+ if (NULL == padapter->hal_func.GetHalODMVarHandler) {
rtw_hal_error_msg("GetHalODMVarHandler");
ret = _FAIL;
}
- if (NULL == padapter->HalFunc.SetHalODMVarHandler) {
+ if (NULL == padapter->hal_func.SetHalODMVarHandler) {
rtw_hal_error_msg("SetHalODMVarHandler");
ret = _FAIL;
}
- if (NULL == padapter->HalFunc.UpdateRAMaskHandler) {
- rtw_hal_error_msg("UpdateRAMaskHandler");
- ret = _FAIL;
- }
- if (NULL == padapter->HalFunc.SetBeaconRelatedRegistersHandler) {
+ if (NULL == padapter->hal_func.SetBeaconRelatedRegistersHandler) {
rtw_hal_error_msg("SetBeaconRelatedRegistersHandler");
ret = _FAIL;
}
- if (NULL == padapter->HalFunc.Add_RateATid) {
- rtw_hal_error_msg("Add_RateATid");
+ if (NULL == padapter->hal_func.fill_h2c_cmd) {
+ rtw_hal_error_msg("fill_h2c_cmd");
ret = _FAIL;
}
- if (NULL == padapter->HalFunc.fill_h2c_cmd) {
- rtw_hal_error_msg("fill_h2c_cmd");
+#ifdef RTW_HALMAC
+ if (NULL == padapter->hal_func.hal_mac_c2h_handler) {
+ rtw_hal_error_msg("hal_mac_c2h_handler");
+ ret = _FAIL;
+ }
+#elif !defined(CONFIG_RTL8188E)
+ if (NULL == padapter->hal_func.c2h_handler) {
+ rtw_hal_error_msg("c2h_handler");
ret = _FAIL;
}
+#endif
+
#if defined(CONFIG_LPS) || defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
- if (NULL == padapter->HalFunc.fill_fake_txdesc) {
+ if (NULL == padapter->hal_func.fill_fake_txdesc) {
rtw_hal_error_msg("fill_fake_txdesc");
ret = _FAIL;
}
#endif
- if (NULL == padapter->HalFunc.hal_get_tx_buff_rsvd_page_num) {
+
+#ifndef RTW_HALMAC
+ if (NULL == padapter->hal_func.hal_get_tx_buff_rsvd_page_num) {
rtw_hal_error_msg("hal_get_tx_buff_rsvd_page_num");
ret = _FAIL;
}
+#endif /* !RTW_HALMAC */
#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
- if (NULL == padapter->HalFunc.clear_interrupt) {
+ if (NULL == padapter->hal_func.clear_interrupt) {
rtw_hal_error_msg("clear_interrupt");
ret = _FAIL;
}
#endif
#endif /* CONFIG_WOWLAN */
- if (NULL == padapter->HalFunc.fw_dl) {
+ if (NULL == padapter->hal_func.fw_dl) {
rtw_hal_error_msg("fw_dl");
ret = _FAIL;
}
+#if defined(RTW_HALMAC) && defined(CONFIG_LPS_PG)
+ if (NULL == padapter->hal_func.fw_mem_dl) {
+ rtw_hal_error_msg("fw_mem_dl");
+ ret = _FAIL;
+ }
+#endif
+
if ((IS_HARDWARE_TYPE_8814A(padapter)
|| IS_HARDWARE_TYPE_8822BU(padapter) || IS_HARDWARE_TYPE_8822BS(padapter))
- && NULL == padapter->HalFunc.fw_correct_bcn) {
+ && NULL == padapter->hal_func.fw_correct_bcn) {
rtw_hal_error_msg("fw_correct_bcn");
ret = _FAIL;
}
if (IS_HARDWARE_TYPE_8822B(padapter) || IS_HARDWARE_TYPE_8821C(padapter)) {
- if (!padapter->HalFunc.set_tx_power_index_handler) {
+ if (!padapter->hal_func.set_tx_power_index_handler) {
rtw_hal_error_msg("set_tx_power_index_handler");
ret = _FAIL;
}
- if (!padapter->HalFunc.get_tx_power_index_handler) {
- rtw_hal_error_msg("get_tx_power_index_handler");
- ret = _FAIL;
- }
+ }
+
+ if (!padapter->hal_func.get_tx_power_index_handler) {
+ rtw_hal_error_msg("get_tx_power_index_handler");
+ ret = _FAIL;
}
/*** SReset section ***/
#ifdef DBG_CONFIG_ERROR_DETECT
- if (NULL == padapter->HalFunc.sreset_init_value) {
+ if (NULL == padapter->hal_func.sreset_init_value) {
rtw_hal_error_msg("sreset_init_value");
ret = _FAIL;
}
- if (NULL == padapter->HalFunc.sreset_reset_value) {
+ if (NULL == padapter->hal_func.sreset_reset_value) {
rtw_hal_error_msg("sreset_reset_value");
ret = _FAIL;
}
- if (NULL == padapter->HalFunc.silentreset) {
+ if (NULL == padapter->hal_func.silentreset) {
rtw_hal_error_msg("silentreset");
ret = _FAIL;
}
- if (NULL == padapter->HalFunc.sreset_xmit_status_check) {
+ if (NULL == padapter->hal_func.sreset_xmit_status_check) {
rtw_hal_error_msg("sreset_xmit_status_check");
ret = _FAIL;
}
- if (NULL == padapter->HalFunc.sreset_linked_status_check) {
+ if (NULL == padapter->hal_func.sreset_linked_status_check) {
rtw_hal_error_msg("sreset_linked_status_check");
ret = _FAIL;
}
- if (NULL == padapter->HalFunc.sreset_get_wifi_status) {
+ if (NULL == padapter->hal_func.sreset_get_wifi_status) {
rtw_hal_error_msg("sreset_get_wifi_status");
ret = _FAIL;
}
- if (NULL == padapter->HalFunc.sreset_inprogress) {
+ if (NULL == padapter->hal_func.sreset_inprogress) {
rtw_hal_error_msg("sreset_inprogress");
ret = _FAIL;
}
#endif /* #ifdef DBG_CONFIG_ERROR_DETECT */
#ifdef RTW_HALMAC
- if (NULL == padapter->HalFunc.init_mac_register) {
+ if (NULL == padapter->hal_func.init_mac_register) {
rtw_hal_error_msg("init_mac_register");
ret = _FAIL;
}
- if (NULL == padapter->HalFunc.init_phy) {
+ if (NULL == padapter->hal_func.init_phy) {
rtw_hal_error_msg("init_phy");
ret = _FAIL;
}
#endif /* RTW_HALMAC */
-#ifdef CONFIG_NAPI
- if (NULL == padapter->HalFunc.napi_irq_disable) {
- rtw_hal_error_msg("napi_irq_disable");
- ret = _FAIL;
- }
- if (NULL == padapter->HalFunc.napi_irq_enable) {
- rtw_hal_error_msg("napi_irq_enable");
- ret = _FAIL;
- }
- if (NULL == padapter->HalFunc.napi_poll) {
- rtw_hal_error_msg("napi_poll");
+#ifdef CONFIG_RFKILL_POLL
+ if (padapter->hal_func.hal_radio_onoff_check == NULL) {
+ rtw_hal_error_msg("hal_radio_onoff_check");
ret = _FAIL;
}
#endif
diff --git a/hal/hal_mcc.c b/hal/hal_mcc.c
index eb65f59..27138c7 100644
--- a/hal/hal_mcc.c
+++ b/hal/hal_mcc.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2015 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2015 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,11 +11,7 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- ******************************************************************************/
+ *****************************************************************************/
#ifdef CONFIG_MCC_MODE
#define _HAL_MCC_C_
@@ -24,14 +20,211 @@
#include /* HAL_DATA */
#include /* power control */
-/* backup IQK value */
-void rtw_hal_mcc_backup_IQK_val(PADAPTER padapter)
+/* use for AP/GO + STA/GC case */
+#define MCC_DURATION_IDX 0 /* druration for station side */
+#define MCC_TSF_SYNC_OFFSET_IDX 1
+#define MCC_START_TIME_OFFSET_IDX 2
+#define MCC_INTERVAL_IDX 3
+#define MCC_GUARD_OFFSET0_IDX 4
+#define MCC_GUARD_OFFSET1_IDX 5
+#define MCC_STOP_THRESHOLD 6
+#define TU 1024 /* 1 TU equals 1024 microseconds */
+/* druration, TSF sync offset, start time offset, interval (unit:TU (1024 microseconds))*/
+u8 mcc_switch_channel_policy_table[][7]={
+ {20, 50, 40, 100, 0, 0, 30},
+ {80, 50, 10, 100, 0, 0, 30},
+ {36, 50, 32, 100, 0, 0, 30},
+ {30, 50, 35, 100, 0, 0, 30},
+};
+
+const int mcc_max_policy_num = sizeof(mcc_switch_channel_policy_table) /sizeof(u8) /7;
+struct mi_state mcc_mstate;
+
+static void dump_iqk_val_table(PADAPTER padapter)
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+ struct hal_iqk_reg_backup *iqk_reg_backup = pHalData->iqk_reg_backup;
+ u8 total_rf_path = pHalData->NumTotalRFPath;
+ u8 rf_path_idx = 0;
+ u8 backup_chan_idx = 0;
+ u8 backup_reg_idx = 0;
+
+#ifdef CONFIG_MCC_MODE_V2
+#else
+
+ RTW_INFO("=============dump IQK backup table================\n");
+ for (backup_chan_idx = 0; backup_chan_idx < MAX_IQK_INFO_BACKUP_CHNL_NUM; backup_chan_idx++) {
+ for (rf_path_idx = 0; rf_path_idx < total_rf_path; rf_path_idx++) {
+ for(backup_reg_idx = 0; backup_reg_idx < MAX_IQK_INFO_BACKUP_REG_NUM; backup_reg_idx++) {
+ RTW_INFO("ch:%d. bw:%d. rf path:%d. reg[%d] = 0x%02x \n"
+ , iqk_reg_backup[backup_chan_idx].central_chnl
+ , iqk_reg_backup[backup_chan_idx].bw_mode
+ , rf_path_idx
+ , backup_reg_idx
+ , iqk_reg_backup[backup_chan_idx].reg_backup[rf_path_idx][backup_reg_idx]
+ );
+ }
+ }
+ }
+ RTW_INFO("=============================================\n");
+
+#endif
+}
+
+static void rtw_hal_mcc_build_p2p_noa_attr(PADAPTER padapter, u8 *ie, u32 *ie_len)
+{
+ struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
+ struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+ struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
+ u8 p2p_noa_attr_ie[MAX_P2P_IE_LEN] = {0x00};
+ u32 p2p_noa_attr_len = 0;
+ u8 noa_desc_num = 1;
+ u8 opp_ps = 0; /* Disable OppPS */
+ u8 noa_count = 255;
+ u32 noa_duration;
+ u32 noa_interval;
+ u8 noa_index = 0;
+ u8 mcc_policy_idx = 0;
+
+ mcc_policy_idx = pmccobjpriv->policy_index;
+ noa_duration = mcc_switch_channel_policy_table[mcc_policy_idx][MCC_DURATION_IDX] * TU;
+ noa_interval = mcc_switch_channel_policy_table[mcc_policy_idx][MCC_INTERVAL_IDX] * TU;
+
+ /* P2P OUI(4 bytes) */
+ _rtw_memcpy(p2p_noa_attr_ie, P2P_OUI, 4);
+ p2p_noa_attr_len = p2p_noa_attr_len + 4;
+
+ /* attrute ID(1 byte) */
+ p2p_noa_attr_ie[p2p_noa_attr_len] = P2P_ATTR_NOA;
+ p2p_noa_attr_len = p2p_noa_attr_len + 1;
+
+ /* attrute length(2 bytes) length = noa_desc_num*13 + 2 */
+ RTW_PUT_LE16(p2p_noa_attr_ie + p2p_noa_attr_len, (noa_desc_num * 13 + 2));
+ p2p_noa_attr_len = p2p_noa_attr_len + 2;
+
+ /* Index (1 byte) */
+ p2p_noa_attr_ie[p2p_noa_attr_len] = noa_index;
+ p2p_noa_attr_len = p2p_noa_attr_len + 1;
+
+ /* CTWindow and OppPS Parameters (1 byte) */
+ p2p_noa_attr_ie[p2p_noa_attr_len] = opp_ps;
+ p2p_noa_attr_len = p2p_noa_attr_len+ 1;
+
+ /* NoA Count (1 byte) */
+ p2p_noa_attr_ie[p2p_noa_attr_len] = noa_count;
+ p2p_noa_attr_len = p2p_noa_attr_len + 1;
+
+ /* NoA Duration (4 bytes) unit: microseconds */
+ RTW_PUT_LE32(p2p_noa_attr_ie + p2p_noa_attr_len, noa_duration);
+ p2p_noa_attr_len = p2p_noa_attr_len + 4;
+
+ /* NoA Interval (4 bytes) unit: microseconds */
+ RTW_PUT_LE32(p2p_noa_attr_ie + p2p_noa_attr_len, noa_interval);
+ p2p_noa_attr_len = p2p_noa_attr_len + 4;
+
+ /* NoA Start Time (4 bytes) unit: microseconds */
+ RTW_PUT_LE32(p2p_noa_attr_ie + p2p_noa_attr_len, pmccadapriv->noa_start_time);
+ if (0)
+ RTW_INFO("indxe:%d, start_time=0x%02x:0x%02x:0x%02x:0x%02x\n"
+ , noa_index
+ , p2p_noa_attr_ie[p2p_noa_attr_len]
+ , p2p_noa_attr_ie[p2p_noa_attr_len + 1]
+ , p2p_noa_attr_ie[p2p_noa_attr_len + 2]
+ , p2p_noa_attr_ie[p2p_noa_attr_len + 3]);
+
+ p2p_noa_attr_len = p2p_noa_attr_len + 4;
+ rtw_set_ie(ie, _VENDOR_SPECIFIC_IE_, p2p_noa_attr_len, (u8 *)p2p_noa_attr_ie, ie_len);
+}
+
+
+/**
+ * rtw_hal_mcc_update_go_p2p_ie - update go p2p ie(add NoA attribute)
+ * @padapter: the adapter to be update go p2p ie
+ */
+static void rtw_hal_mcc_update_go_p2p_ie(PADAPTER padapter)
+{
+ struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
+ struct mcc_obj_priv *mccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
+ u8 *pos = NULL;
+
+
+ /* no noa attribute, build it */
+ if (pmccadapriv->p2p_go_noa_ie_len == 0)
+ rtw_hal_mcc_build_p2p_noa_attr(padapter, pmccadapriv->p2p_go_noa_ie, &pmccadapriv->p2p_go_noa_ie_len);
+ else {
+ /* has noa attribut, modify it */
+ u32 noa_duration = 0;
+
+ /* update index */
+ pos = pmccadapriv->p2p_go_noa_ie + pmccadapriv->p2p_go_noa_ie_len - 15;
+ /* 0~255 */
+ (*pos) = ((*pos) + 1) % 256;
+ if (0)
+ RTW_INFO("indxe:%d\n", (*pos));
+
+
+ /* update duration */
+ noa_duration = mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_DURATION_IDX] * TU;
+ pos = pmccadapriv->p2p_go_noa_ie + pmccadapriv->p2p_go_noa_ie_len - 12;
+ RTW_PUT_LE32(pos, noa_duration);
+
+ /* update start time */
+ pos = pmccadapriv->p2p_go_noa_ie + pmccadapriv->p2p_go_noa_ie_len - 4;
+ RTW_PUT_LE32(pos, pmccadapriv->noa_start_time);
+ if (0)
+ RTW_INFO("start_time=0x%02x:0x%02x:0x%02x:0x%02x\n"
+ , ((u8*)(pos))[0]
+ , ((u8*)(pos))[1]
+ , ((u8*)(pos))[2]
+ , ((u8*)(pos))[3]);
+
+ }
+
+ if (0) {
+ RTW_INFO("p2p_go_noa_ie_len:%d\n", pmccadapriv->p2p_go_noa_ie_len);
+ RTW_INFO_DUMP("\n", pmccadapriv->p2p_go_noa_ie, pmccadapriv->p2p_go_noa_ie_len);
+ }
+ update_beacon(padapter, _VENDOR_SPECIFIC_IE_, P2P_OUI, _TRUE);
+}
+
+/**
+ * rtw_hal_mcc_remove_go_p2p_ie - remove go p2p ie(add NoA attribute)
+ * @padapter: the adapter to be update go p2p ie
+ */
+static void rtw_hal_mcc_remove_go_p2p_ie(PADAPTER padapter)
+{
+ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+ struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
+
+ /* chech has noa ie or not */
+ if (pmccadapriv->p2p_go_noa_ie_len == 0)
+ return;
+
+ pmccadapriv->p2p_go_noa_ie_len = 0;
+ update_beacon(padapter, _VENDOR_SPECIFIC_IE_, P2P_OUI, _TRUE);
+}
+
+/* restore IQK value for all interface */
+void rtw_hal_mcc_restore_iqk_val(PADAPTER padapter)
{
u8 take_care_iqk = _FALSE;
+ struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+ _adapter *iface = NULL;
+ u8 i = 0;
rtw_hal_get_hwreg(padapter, HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO, &take_care_iqk);
- if (take_care_iqk == _TRUE && MCC_EN(padapter))
- rtw_hal_ch_sw_iqk_info_restore(padapter, CH_SW_USE_CASE_MCC);
+ if (take_care_iqk == _TRUE && MCC_EN(padapter)) {
+ for (i = 0; i < dvobj->iface_nums; i++) {
+ iface = dvobj->padapters[i];
+ if (iface == NULL)
+ continue;
+
+ rtw_hal_ch_sw_iqk_info_restore(iface, CH_SW_USE_CASE_MCC);
+ }
+ }
+
+ if (0)
+ dump_iqk_val_table(padapter);
}
u8 rtw_hal_check_mcc_status(PADAPTER padapter, u8 mcc_status)
@@ -58,25 +251,74 @@ void rtw_hal_clear_mcc_status(PADAPTER padapter, u8 mcc_status)
pmccobjpriv->mcc_status &= (~mcc_status);
}
-static void rtw_hal_config_mcc_role_setting(PADAPTER padapter)
+static void rtw_hal_mcc_update_policy_table(PADAPTER adapter)
+{
+ struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+ struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
+ u8 mcc_duration = mccobjpriv->duration;
+ s8 mcc_policy_idx = mccobjpriv->policy_index;
+ u8 interval = mcc_switch_channel_policy_table[mcc_policy_idx][MCC_INTERVAL_IDX];
+ u8 new_mcc_duration_time = 0;
+ u8 new_starttime_offset = 0;
+
+ /* convert % to ms */
+ new_mcc_duration_time = mcc_duration * interval / 100;
+
+ /* start time offset = (interval - duration time)/2 */
+ new_starttime_offset = (interval - new_mcc_duration_time) >> 1;
+
+ /* update modified parameters */
+ mcc_switch_channel_policy_table[mcc_policy_idx][MCC_DURATION_IDX]
+ = new_mcc_duration_time;
+
+ mcc_switch_channel_policy_table[mcc_policy_idx][MCC_START_TIME_OFFSET_IDX]
+ = new_starttime_offset;
+
+
+}
+
+static void rtw_hal_config_mcc_switch_channel_setting(PADAPTER padapter)
+{
+ struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+ struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
+ struct registry_priv *registry_par = &padapter->registrypriv;
+ u8 mcc_duration = 0;
+ s8 mcc_policy_idx = 0;
+
+ mcc_policy_idx = registry_par->rtw_mcc_policy_table_idx;
+ mcc_duration = mccobjpriv->duration;
+
+ if (mcc_policy_idx < 0 || mcc_policy_idx >= mcc_max_policy_num) {
+ mccobjpriv->policy_index = 0;
+ RTW_INFO("[MCC] can't find table(%d), use default policy(%d)\n",
+ mcc_policy_idx, mccobjpriv->policy_index);
+ } else
+ mccobjpriv->policy_index = mcc_policy_idx;
+
+ /* convert % to time */
+ if (mcc_duration != 0)
+ rtw_hal_mcc_update_policy_table(padapter);
+
+ RTW_INFO("[MCC] policy(%d): %d,%d,%d,%d,%d,%d\n"
+ , mccobjpriv->policy_index
+ , mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_DURATION_IDX]
+ , mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_TSF_SYNC_OFFSET_IDX]
+ , mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_START_TIME_OFFSET_IDX]
+ , mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_INTERVAL_IDX]
+ , mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_GUARD_OFFSET0_IDX]
+ , mcc_switch_channel_policy_table[mccobjpriv->policy_index][MCC_GUARD_OFFSET1_IDX]);
+
+}
+
+static void rtw_hal_mcc_assign_tx_threshold(PADAPTER padapter)
{
- struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
- struct mcc_obj_priv *pmccobjpriv = &(pdvobjpriv->mcc_objpriv);
- struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
- struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
- struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
- struct wlan_network *cur_network = &(pmlmepriv->cur_network);
- struct sta_priv *pstapriv = &padapter->stapriv;
- struct sta_info *psta = NULL;
struct registry_priv *preg = &padapter->registrypriv;
+ struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
+ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
- /* GO/AP is 1nd order GC/STA is 2nd order */
switch (pmccadapriv->role) {
case MCC_ROLE_STA:
case MCC_ROLE_GC:
- pmccadapriv->order = 1;
- pmccadapriv->mcc_duration = pmccobjpriv->duration;
-
switch (pmlmeext->cur_bwmode) {
case CHANNEL_WIDTH_20:
/*
@@ -100,24 +342,9 @@ static void rtw_hal_config_mcc_role_setting(PADAPTER padapter)
, FUNC_ADPT_ARG(padapter), pmlmeext->cur_bwmode);
break;
}
-
- /* assign used mac to avoid affecting RA */
- pmccadapriv->mgmt_queue_macid = MCC_ROLE_STA_GC_MGMT_QUEUE_MACID;
-
- psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress);
- if (psta) {
- /* combine AP/GO macid and mgmt queue macid to bitmap */
- pmccadapriv->mcc_macid_bitmap = BIT(psta->mac_id) | BIT(pmccadapriv->mgmt_queue_macid);
- } else {
- RTW_INFO(FUNC_ADPT_FMT":AP/GO station info is NULL\n", FUNC_ADPT_ARG(padapter));
- rtw_warn_on(1);
- }
break;
case MCC_ROLE_AP:
case MCC_ROLE_GO:
- pmccadapriv->order = 0;
- pmccadapriv->mcc_duration = 100 - pmccobjpriv->duration; /* 100 means beacon interval */
-
switch (pmlmeext->cur_bwmode) {
case CHANNEL_WIDTH_20:
pmccadapriv->mcc_target_tx_bytes_to_port = preg->rtw_mcc_ap_bw20_target_tx_tp * 128 * pmccadapriv->mcc_duration;
@@ -134,47 +361,163 @@ static void rtw_hal_config_mcc_role_setting(PADAPTER padapter)
, FUNC_ADPT_ARG(padapter), pmlmeext->cur_bwmode);
break;
}
+ break;
+ }
+}
+static void rtw_hal_config_mcc_role_setting(PADAPTER padapter, u8 order)
+{
+ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
+ struct mcc_obj_priv *pmccobjpriv = &(pdvobjpriv->mcc_objpriv);
+ struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
+ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
+ struct wlan_network *cur_network = &(pmlmepriv->cur_network);
+ struct sta_priv *pstapriv = &padapter->stapriv;
+ struct sta_info *psta = NULL;
+ struct registry_priv *preg = &padapter->registrypriv;
+ _irqL irqL;
+ _list *phead =NULL, *plist = NULL;
+ u8 policy_index = 0;
+ u8 mcc_duration = 0;
+ u8 mcc_interval = 0;
+
+ policy_index = pmccobjpriv->policy_index;
+ mcc_duration = mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_DURATION_IDX]
+ - mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_GUARD_OFFSET0_IDX]
+ - mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_GUARD_OFFSET1_IDX];
+ mcc_interval = mcc_switch_channel_policy_table[pmccobjpriv->policy_index][MCC_INTERVAL_IDX];
+
+ if (MSTATE_AP_STARTING_NUM(&mcc_mstate) == 0
+ && MSTATE_AP_NUM(&mcc_mstate) == 0) {
+ pmccadapriv->order = order;
+
+ if (pmccadapriv->order == 0) {
+ /* setting is smiliar to GO/AP */
+ /* pmccadapriv->mcc_duration = mcc_interval - mcc_duration;*/
+ pmccadapriv->mgmt_queue_macid = MCC_ROLE_SOFTAP_GO_MGMT_QUEUE_MACID;
+ } else if (pmccadapriv->order == 1) {
+ /* pmccadapriv->mcc_duration = mcc_duration; */
+ pmccadapriv->mgmt_queue_macid = MCC_ROLE_STA_GC_MGMT_QUEUE_MACID;
+ } else {
+ RTW_INFO("[MCC] not support >= 3 interface\n");
+ rtw_warn_on(1);
+ }
- psta = rtw_get_bcmc_stainfo(padapter);
+ rtw_hal_mcc_assign_tx_threshold(padapter);
- if (psta != NULL)
- pmccadapriv->mgmt_queue_macid = psta->mac_id;
- else {
- pmccadapriv->mgmt_queue_macid = MCC_ROLE_SOFTAP_GO_MGMT_QUEUE_MACID;
- RTW_INFO(FUNC_ADPT_FMT":bcmc station is NULL, use macid %d\n"
- , FUNC_ADPT_ARG(padapter), pmccadapriv->mgmt_queue_macid);
+ psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress);
+ if (psta) {
+ /* combine AP/GO macid and mgmt queue macid to bitmap */
+ pmccadapriv->mcc_macid_bitmap = BIT(psta->cmn.mac_id) | BIT(pmccadapriv->mgmt_queue_macid);
+ } else {
+ RTW_INFO(FUNC_ADPT_FMT":AP/GO station info is NULL\n", FUNC_ADPT_ARG(padapter));
+ rtw_warn_on(1);
+ }
+ } else {
+ /* GO/AP is 1nd order GC/STA is 2nd order */
+ switch (pmccadapriv->role) {
+ case MCC_ROLE_STA:
+ case MCC_ROLE_GC:
+ pmccadapriv->order = 1;
+ pmccadapriv->mcc_duration = mcc_duration;
+
+ rtw_hal_mcc_assign_tx_threshold(padapter);
+ /* assign used mac to avoid affecting RA */
+ pmccadapriv->mgmt_queue_macid = MCC_ROLE_STA_GC_MGMT_QUEUE_MACID;
+
+ psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress);
+ if (psta) {
+ /* combine AP/GO macid and mgmt queue macid to bitmap */
+ pmccadapriv->mcc_macid_bitmap = BIT(psta->cmn.mac_id) | BIT(pmccadapriv->mgmt_queue_macid);
+ } else {
+ RTW_INFO(FUNC_ADPT_FMT":AP/GO station info is NULL\n", FUNC_ADPT_ARG(padapter));
+ rtw_warn_on(1);
+ }
+ break;
+ case MCC_ROLE_AP:
+ case MCC_ROLE_GO:
+ pmccadapriv->order = 0;
+ /* total druation value equals interval */
+ pmccadapriv->mcc_duration = mcc_interval - mcc_duration;
+ pmccadapriv->p2p_go_noa_ie_len = 0; /* not NoA attribute at init time */
+
+ rtw_hal_mcc_assign_tx_threshold(padapter);
+
+ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+
+ phead = &pstapriv->asoc_list;
+ plist = get_next(phead);
+ pmccadapriv->mcc_macid_bitmap = 0;
+
+ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) {
+ psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list);
+ plist = get_next(plist);
+ pmccadapriv->mcc_macid_bitmap |= BIT(psta->cmn.mac_id);
+ }
+
+ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL);
+
+ psta = rtw_get_bcmc_stainfo(padapter);
+
+ if (psta != NULL)
+ pmccadapriv->mgmt_queue_macid = psta->cmn.mac_id;
+ else {
+ pmccadapriv->mgmt_queue_macid = MCC_ROLE_SOFTAP_GO_MGMT_QUEUE_MACID;
+ RTW_INFO(FUNC_ADPT_FMT":bcmc station is NULL, use macid %d\n"
+ , FUNC_ADPT_ARG(padapter), pmccadapriv->mgmt_queue_macid);
+ }
+
+ /* combine client macid and mgmt queue macid to bitmap */
+ pmccadapriv->mcc_macid_bitmap |= BIT(pmccadapriv->mgmt_queue_macid);
+ break;
+ default:
+ RTW_INFO("Unknown role\n");
+ rtw_warn_on(1);
+ break;
}
- /* combine client macid and mgmt queue macid to bitmap */
- pmccadapriv->mcc_macid_bitmap = (0xff << 8) | BIT(pmccadapriv->mgmt_queue_macid);
- break;
- default:
- RTW_INFO("Unknown role\n");
- rtw_warn_on(1);
- break;
}
+ /* setting Null data parameters */
+ if (pmccadapriv->role == MCC_ROLE_STA) {
+ pmccadapriv->null_early = 3;
+ pmccadapriv->null_rty_num= 5;
+ } else if (pmccadapriv->role == MCC_ROLE_GC) {
+ pmccadapriv->null_early = 2;
+ pmccadapriv->null_rty_num= 5;
+ } else {
+ pmccadapriv->null_early = 0;
+ pmccadapriv->null_rty_num= 0;
+ }
+
+ RTW_INFO("********* "FUNC_ADPT_FMT" *********\n", FUNC_ADPT_ARG(padapter));
+ RTW_INFO("order:%d\n", pmccadapriv->order);
+ RTW_INFO("role:%d\n", pmccadapriv->role);
+ RTW_INFO("mcc duration:%d\n", pmccadapriv->mcc_duration);
+ RTW_INFO("null_early:%d\n", pmccadapriv->null_early);
+ RTW_INFO("null_rty_num:%d\n", pmccadapriv->null_rty_num);
+ RTW_INFO("mgmt queue macid:%d\n", pmccadapriv->mgmt_queue_macid);
+ RTW_INFO("bitmap:0x%02x\n", pmccadapriv->mcc_macid_bitmap);
+ RTW_INFO("target tx bytes:%d\n", pmccadapriv->mcc_target_tx_bytes_to_port);
+ RTW_INFO("**********************************\n");
+
pmccobjpriv->iface[pmccadapriv->order] = padapter;
- RTW_INFO(FUNC_ADPT_FMT": order:%d, role:%d, mcc duration:%d, target tx bytes:%d, mgmt queue macid:%d, bitmap:0x%02x\n"
- , FUNC_ADPT_ARG(padapter), pmccadapriv->order, pmccadapriv->role, pmccadapriv->mcc_duration
- , pmccadapriv->mcc_target_tx_bytes_to_port, pmccadapriv->mgmt_queue_macid, pmccadapriv->mcc_macid_bitmap);
+
}
static void rtw_hal_clear_mcc_macid(PADAPTER padapter)
{
+ u16 media_status_rpt;
struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
switch (pmccadapriv->role) {
case MCC_ROLE_STA:
case MCC_ROLE_GC:
- /* release mgmt queue macid */
- rtw_hal_set_FwMediaStatusRpt_single_cmd(padapter
- , 0, 0, 0, H2C_MSR_ROLE_AP, pmccadapriv->mgmt_queue_macid);
break;
case MCC_ROLE_AP:
case MCC_ROLE_GO:
- /* nothing to do */
+ /* nothing to do */
break;
default:
RTW_INFO("Unknown role\n");
@@ -182,6 +525,370 @@ static void rtw_hal_clear_mcc_macid(PADAPTER padapter)
break;
}
}
+
+static void rtw_hal_mcc_rqt_tsf(PADAPTER padapter)
+{
+ struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+ struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
+ u8 cmd[H2C_MCC_RQT_TSF_LEN] = {0};
+
+ rtw_sctx_init(&pmccobjpriv->mcc_tsf_req_sctx, MCC_EXPIRE_TIME);
+
+ SET_H2CCMD_MCC_RQT_TSFX(cmd, pmccobjpriv->iface[0]->hw_port);
+ SET_H2CCMD_MCC_RQT_TSFY(cmd, pmccobjpriv->iface[1]->hw_port);
+
+ rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_RQT_TSF, H2C_MCC_RQT_TSF_LEN, cmd);
+
+ if (!rtw_sctx_wait(&pmccobjpriv->mcc_tsf_req_sctx, __func__))
+ RTW_INFO(FUNC_ADPT_FMT": wait for mcc tsf req C2H time out\n", FUNC_ADPT_ARG(padapter));
+
+}
+
+static u8 rtw_hal_mcc_check_start_time_is_valid(PADAPTER padapter, u8 case_num,
+ u32 tsfdiff, s8 *upper_bound_0, s8 *lower_bound_0, s8 *upper_bound_1, s8 *lower_bound_1)
+{
+ struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+ struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
+ u8 duration_0 = 0, duration_1 = 0;
+ s8 final_upper_bound = 0, final_lower_bound = 0;
+ u8 intersection = _FALSE;
+ u8 min_start_time = 5;
+ u8 max_start_time = 95;
+
+ duration_0 = mccobjpriv->iface[0]->mcc_adapterpriv.mcc_duration;
+ duration_1 = mccobjpriv->iface[1]->mcc_adapterpriv.mcc_duration;
+
+ switch(case_num) {
+ case 1:
+ *upper_bound_0 = tsfdiff;
+ *lower_bound_0 = tsfdiff - duration_1;
+ *upper_bound_1 = 150 - duration_1;
+ *lower_bound_1= 0;
+ break;
+ case 2:
+ *upper_bound_0 = tsfdiff + 100;
+ *lower_bound_0 = tsfdiff + 100 - duration_1;
+ *upper_bound_1 = 150 - duration_1;
+ *lower_bound_1= 0;
+ break;
+ case 3:
+ *upper_bound_0 = tsfdiff + 50;
+ *lower_bound_0 = tsfdiff + 50 - duration_1;
+ *upper_bound_1 = 150 - duration_1;
+ *lower_bound_1= 0;
+ break;
+ case 4:
+ *upper_bound_0 = tsfdiff;
+ *lower_bound_0 = tsfdiff - duration_1;
+ *upper_bound_1 = 150 - duration_1;
+ *lower_bound_1= 0;
+ break;
+ case 5:
+ *upper_bound_0 = 200 - tsfdiff;
+ *lower_bound_0 = 200 - tsfdiff - duration_1;
+ *upper_bound_1 = 150 - duration_1;
+ *lower_bound_1= 0;
+ break;
+ case 6:
+ *upper_bound_0 = tsfdiff - 50;
+ *lower_bound_0 = tsfdiff - 50 - duration_1;
+ *upper_bound_1 = 150 - duration_1;
+ *lower_bound_1= 0;
+ break;
+ default:
+ RTW_ERR("[MCC] %s: error case number(%d\n)", __func__, case_num);
+ }
+
+
+ /* check Intersection or not */
+ if ((*lower_bound_1 >= *upper_bound_0) ||
+ (*lower_bound_0 >= *upper_bound_1))
+ intersection = _FALSE;
+ else
+ intersection = _TRUE;
+
+ if (intersection) {
+ if (*upper_bound_0 > *upper_bound_1)
+ final_upper_bound = *upper_bound_1;
+ else
+ final_upper_bound = *upper_bound_0;
+
+ if (*lower_bound_0 > *lower_bound_1)
+ final_lower_bound = *lower_bound_0;
+ else
+ final_lower_bound = *lower_bound_1;
+
+ mccobjpriv->start_time = (final_lower_bound + final_upper_bound) / 2;
+
+ /* check start time less than 5ms, request by Pablo@SD1 */
+ if (mccobjpriv->start_time <= min_start_time) {
+ mccobjpriv->start_time = 6;
+ if (mccobjpriv->start_time < final_lower_bound && mccobjpriv->start_time > final_upper_bound) {
+ intersection = _FALSE;
+ goto exit;
+ }
+ }
+
+ /* check start time less than 95ms */
+ if (mccobjpriv->start_time >= max_start_time) {
+ mccobjpriv->start_time = 90;
+ if (mccobjpriv->start_time < final_lower_bound && mccobjpriv->start_time > final_upper_bound) {
+ intersection = _FALSE;
+ goto exit;
+ }
+ }
+ }
+
+exit:
+ return intersection;
+}
+
+static void rtw_hal_mcc_decide_duration(PADAPTER padapter)
+{
+ struct registry_priv *registry_par = &padapter->registrypriv;
+ struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+ struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
+ struct mcc_adapter_priv *mccadapriv = NULL, *mccadapriv_order0 = NULL, *mccadapriv_order1 = NULL;
+ _adapter *iface = NULL, *iface_order0 = NULL, *iface_order1 = NULL;
+ u8 duration = 0, i = 0, duration_time;
+ u8 mcc_interval = 150;
+
+ iface_order0 = mccobjpriv->iface[0];
+ iface_order1 = mccobjpriv->iface[1];
+ mccadapriv_order0 = &iface_order0->mcc_adapterpriv;
+ mccadapriv_order1 = &iface_order1->mcc_adapterpriv;
+
+ if (mccobjpriv->duration == 0) {
+ /* default */
+ duration = 30;/*(%)*/
+ RTW_INFO("%s: mccobjpriv->duration=0, use default value(%d)\n",
+ __FUNCTION__, duration);
+ } else {
+ duration = mccobjpriv->duration;/*(%)*/
+ RTW_INFO("%s: mccobjpriv->duration=%d\n",
+ __FUNCTION__, duration);
+ }
+
+ mccobjpriv->interval = mcc_interval;
+ mccobjpriv->mcc_stop_threshold = 2000 * 4 / 300 - 6;
+ /* convert % to ms, for primary adapter */
+ duration_time = mccobjpriv->interval * duration / 100;
+
+ for (i = 0; i < dvobj->iface_nums; i++) {
+ iface = dvobj->padapters[i];
+
+ if (!iface)
+ continue;
+
+ mccadapriv = &iface->mcc_adapterpriv;
+
+ if (is_primary_adapter(iface))
+ mccadapriv->mcc_duration = duration_time;
+ else
+ mccadapriv->mcc_duration = mccobjpriv->interval - duration_time;
+ }
+
+ RTW_INFO("[MCC]" FUNC_ADPT_FMT " order 0 duration=%d\n", FUNC_ADPT_ARG(iface_order0), mccadapriv_order0->mcc_duration);
+ RTW_INFO("[MCC]" FUNC_ADPT_FMT " order 1 duration=%d\n", FUNC_ADPT_ARG(iface_order1), mccadapriv_order1->mcc_duration);
+}
+
+static u8 rtw_hal_mcc_update_timing_parameters(PADAPTER padapter, u8 force_update)
+{
+ u8 need_update = _FALSE;
+
+ /* for STA+STA, modify policy table */
+ if (MSTATE_AP_STARTING_NUM(&mcc_mstate) == 0
+ && MSTATE_AP_NUM(&mcc_mstate) == 0) {
+ struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+ struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
+ struct mcc_adapter_priv *pmccadapriv = NULL;
+ _adapter *iface = NULL;
+ u64 tsf0 = 0, tsf1 = 0;
+ u32 beaconperiod_0 = 0, beaconperiod_1 = 0, tsfdiff = 0;
+ s8 upper_bound_0 = 0, lower_bound_0 = 0;
+ s8 upper_bound_1 = 0, lower_bound_1 = 0;
+ u8 valid = _FALSE;
+ u8 case_num = 1;
+ u8 i = 0;
+
+ /* query TSF */
+ rtw_hal_mcc_rqt_tsf(padapter);
+
+ /* selecet policy table according TSF diff */
+ tsf0 = pmccobjpriv->iface[0]->mcc_adapterpriv.tsf;
+ beaconperiod_0 = pmccobjpriv->iface[0]->mlmepriv.cur_network.network.Configuration.BeaconPeriod;
+ tsf0 = rtw_modular64(tsf0, (beaconperiod_0 * TU));
+
+ tsf1 = pmccobjpriv->iface[1]->mcc_adapterpriv.tsf;
+ beaconperiod_1 = pmccobjpriv->iface[1]->mlmepriv.cur_network.network.Configuration.BeaconPeriod;
+ tsf1 = rtw_modular64(tsf1, (beaconperiod_1 * TU));
+
+ if (tsf0 > tsf1)
+ tsfdiff = tsf0- tsf1;
+ else
+ tsfdiff = (tsf0 + beaconperiod_0 * TU) - tsf1;
+
+ /* convert to ms */
+ tsfdiff = (tsfdiff / TU);
+
+ /* force update*/
+ if (force_update) {
+ RTW_INFO("orig TSF0:%lld, orig TSF1:%lld\n",
+ pmccobjpriv->iface[0]->mcc_adapterpriv.tsf, pmccobjpriv->iface[1]->mcc_adapterpriv.tsf);
+ RTW_INFO("tsf0:%lld, tsf1:%lld\n", tsf0, tsf1);
+ RTW_INFO("%s: force=%d, last_tsfdiff=%d, tsfdiff=%d, THRESHOLD=%d\n",
+ __func__, force_update, pmccobjpriv->last_tsfdiff, tsfdiff, MCC_UPDATE_PARAMETER_THRESHOLD);
+ pmccobjpriv->last_tsfdiff = tsfdiff;
+ need_update = _TRUE;
+ } else {
+ if (pmccobjpriv->last_tsfdiff > tsfdiff) {
+ /* last tsfdiff - current tsfdiff > THRESHOLD, update parameters */
+ if (pmccobjpriv->last_tsfdiff > (tsfdiff + MCC_UPDATE_PARAMETER_THRESHOLD)) {
+ RTW_INFO("orig TSF0:%lld, orig TSF1:%lld\n",
+ pmccobjpriv->iface[0]->mcc_adapterpriv.tsf, pmccobjpriv->iface[1]->mcc_adapterpriv.tsf);
+ RTW_INFO("tsf0:%lld, tsf1:%lld\n", tsf0, tsf1);
+ RTW_INFO("%s: force=%d, last_tsfdiff=%d, tsfdiff=%d, THRESHOLD=%d\n",
+ __func__, force_update, pmccobjpriv->last_tsfdiff, tsfdiff, MCC_UPDATE_PARAMETER_THRESHOLD);
+
+ pmccobjpriv->last_tsfdiff = tsfdiff;
+ need_update = _TRUE;
+ } else {
+ need_update = _FALSE;
+ }
+ } else if (tsfdiff > pmccobjpriv->last_tsfdiff){
+ /* current tsfdiff - last tsfdiff > THRESHOLD, update parameters */
+ if (tsfdiff > (pmccobjpriv->last_tsfdiff + MCC_UPDATE_PARAMETER_THRESHOLD)) {
+ RTW_INFO("orig TSF0:%lld, orig TSF1:%lld\n",
+ pmccobjpriv->iface[0]->mcc_adapterpriv.tsf, pmccobjpriv->iface[1]->mcc_adapterpriv.tsf);
+ RTW_INFO("tsf0:%lld, tsf1:%lld\n", tsf0, tsf1);
+ RTW_INFO("%s: force=%d, last_tsfdiff=%d, tsfdiff=%d, THRESHOLD=%d\n",
+ __func__, force_update, pmccobjpriv->last_tsfdiff, tsfdiff, MCC_UPDATE_PARAMETER_THRESHOLD);
+
+ pmccobjpriv->last_tsfdiff = tsfdiff;
+ need_update = _TRUE;
+ } else {
+ need_update = _FALSE;
+ }
+ } else {
+ need_update = _FALSE;
+ }
+ }
+
+ if (need_update == _FALSE)
+ goto exit;
+
+ rtw_hal_mcc_decide_duration(padapter);
+
+ if (tsfdiff <= 50) {
+
+ /* RX TBTT 0 */
+ case_num = 1;
+ valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,
+ &upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);
+
+ if (valid)
+ goto valid_result;
+
+ /* RX TBTT 1 */
+ case_num = 2;
+ valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,
+ &upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);
+
+ if (valid)
+ goto valid_result;
+
+ /* RX TBTT 2 */
+ case_num = 3;
+ valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,
+ &upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);
+
+ if (valid)
+ goto valid_result;
+
+ if (valid == _FALSE) {
+ RTW_INFO("[MCC] do not find fit start time\n");
+ RTW_INFO("[MCC] tsfdiff:%d, duration:%d(%c), interval:%d\n",
+ tsfdiff, pmccobjpriv->duration, 37, pmccobjpriv->interval);
+
+ }
+
+ } else {
+
+ /* RX TBTT 0 */
+ case_num = 4;
+ valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,
+ &upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);
+
+ if (valid)
+ goto valid_result;
+
+
+ /* RX TBTT 1 */
+ case_num = 5;
+ valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,
+ &upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);
+
+ if (valid)
+ goto valid_result;
+
+
+ /* RX TBTT 2 */
+ case_num = 6;
+ valid = rtw_hal_mcc_check_start_time_is_valid(padapter, case_num, tsfdiff,
+ &upper_bound_0, &lower_bound_0, &upper_bound_1, &lower_bound_1);
+
+ if (valid)
+ goto valid_result;
+
+ if (valid == _FALSE) {
+ RTW_INFO("[MCC] do not find fit start time\n");
+ RTW_INFO("[MCC] tsfdiff:%d, duration:%d(%c), interval:%d\n",
+ tsfdiff, pmccobjpriv->duration, 37, pmccobjpriv->interval);
+ }
+ }
+
+
+
+ valid_result:
+ RTW_INFO("********************\n");
+ RTW_INFO("%s: case_num:%d, start time:%d\n",
+ __func__, case_num, pmccobjpriv->start_time);
+ RTW_INFO("%s: upper_bound_0:%d, lower_bound_0:%d\n",
+ __func__, upper_bound_0, lower_bound_0);
+ RTW_INFO("%s: upper_bound_1:%d, lower_bound_1:%d\n",
+ __func__, upper_bound_1, lower_bound_1);
+
+ for (i = 0; i < dvobj->iface_nums; i++) {
+ iface = dvobj->padapters[i];
+ if (iface == NULL)
+ continue;
+
+ pmccadapriv = &iface->mcc_adapterpriv;
+#if 0
+ if (pmccadapriv->order == 0) {
+ pmccadapriv->mcc_duration = mcc_duration;
+ } else if (pmccadapriv->order == 1) {
+ pmccadapriv->mcc_duration = mcc_interval - mcc_duration;
+ } else {
+ RTW_INFO("[MCC] not support >= 3 interface\n");
+ rtw_warn_on(1);
+ }
+#endif
+ RTW_INFO("********************\n");
+ RTW_INFO(FUNC_ADPT_FMT": order:%d, role:%d\n",
+ FUNC_ADPT_ARG(iface), pmccadapriv->order, pmccadapriv->role);
+ RTW_INFO(FUNC_ADPT_FMT": mcc duration:%d, target tx bytes:%d\n",
+ FUNC_ADPT_ARG(iface), pmccadapriv->mcc_duration, pmccadapriv->mcc_target_tx_bytes_to_port);
+ RTW_INFO(FUNC_ADPT_FMT": mgmt queue macid:%d, bitmap:0x%02x\n",
+ FUNC_ADPT_ARG(iface), pmccadapriv->mgmt_queue_macid, pmccadapriv->mcc_macid_bitmap);
+ RTW_INFO("********************\n");
+ }
+
+ }
+exit:
+ return need_update;
+}
+
static u8 rtw_hal_decide_mcc_role(PADAPTER padapter)
{
struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
@@ -190,6 +897,7 @@ static u8 rtw_hal_decide_mcc_role(PADAPTER padapter)
struct wifidirect_info *pwdinfo = NULL;
struct mlme_priv *pmlmepriv = NULL;
u8 ret = _SUCCESS, i = 0;
+ u8 order = 1;
for (i = 0; i < dvobj->iface_nums; i++) {
iface = dvobj->padapters[i];
@@ -218,24 +926,28 @@ static u8 rtw_hal_decide_mcc_role(PADAPTER padapter)
goto exit;
}
- if (ret == _SUCCESS)
- rtw_hal_config_mcc_role_setting(iface);
+ if (ret == _SUCCESS) {
+ if (padapter == iface) {
+ /* current adapter is order 0 */
+ rtw_hal_config_mcc_role_setting(iface, 0);
+ } else {
+ rtw_hal_config_mcc_role_setting(iface, order);
+ order ++;
+ }
+ }
}
+ rtw_hal_mcc_update_timing_parameters(padapter, _TRUE);
exit:
return ret;
}
-static void rtw_hal_init_mcc_parameter(PADAPTER padapter)
-{
-}
-
static void rtw_hal_construct_CTS(PADAPTER padapter, u8 *pframe, u32 *pLength)
{
u8 broadcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
/* frame type, length = 1*/
- SetFrameSubType(pframe, WIFI_RTS);
+ set_frame_sub_type(pframe, WIFI_RTS);
/* frame control flag, length = 1 */
*(pframe + 1) = 0;
@@ -247,13 +959,73 @@ static void rtw_hal_construct_CTS(PADAPTER padapter, u8 *pframe, u32 *pLength)
/* frame recvaddr, length = 6 */
_rtw_memcpy((pframe + 4), broadcast_addr, ETH_ALEN);
_rtw_memcpy((pframe + 4 + ETH_ALEN), adapter_mac_addr(padapter), ETH_ALEN);
- _rtw_memcpy((pframe + 4 + ETH_ALEN * 2), adapter_mac_addr(padapter), ETH_ALEN);
+ _rtw_memcpy((pframe + 4 + ETH_ALEN*2), adapter_mac_addr(padapter), ETH_ALEN);
*pLength = 22;
}
+/* avoid wrong information for power limit */
+void rtw_hal_mcc_upadate_chnl_bw(_adapter *padapter, u8 ch, u8 ch_offset, u8 bw, u8 print)
+{
+
+ u8 center_ch, chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+ PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter);
+ u8 cch_160, cch_80, cch_40, cch_20;
+
+ center_ch = rtw_get_center_ch(ch, bw, ch_offset);
+
+ if (bw == CHANNEL_WIDTH_80) {
+ if (center_ch > ch)
+ chnl_offset80 = HAL_PRIME_CHNL_OFFSET_LOWER;
+ else if (center_ch < ch)
+ chnl_offset80 = HAL_PRIME_CHNL_OFFSET_UPPER;
+ else
+ chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+ }
+
+ /* set Channel */
+ /* saved channel/bw info */
+ rtw_set_oper_ch(padapter, ch);
+ rtw_set_oper_bw(padapter, bw);
+ rtw_set_oper_choffset(padapter, ch_offset);
+
+ cch_80 = bw == CHANNEL_WIDTH_80 ? center_ch : 0;
+ cch_40 = bw == CHANNEL_WIDTH_40 ? center_ch : 0;
+ cch_20 = bw == CHANNEL_WIDTH_20 ? center_ch : 0;
+
+ if (cch_80 != 0)
+ cch_40 = rtw_get_scch_by_cch_offset(cch_80, CHANNEL_WIDTH_80, chnl_offset80);
+ if (cch_40 != 0)
+ cch_20 = rtw_get_scch_by_cch_offset(cch_40, CHANNEL_WIDTH_40, ch_offset);
+
+
+ hal->cch_80 = cch_80;
+ hal->cch_40 = cch_40;
+ hal->cch_20 = cch_20;
+ hal->current_channel = center_ch;
+ hal->CurrentCenterFrequencyIndex1 = center_ch;
+ hal->current_channel_bw = bw;
+ hal->nCur40MhzPrimeSC = ch_offset;
+ hal->nCur80MhzPrimeSC = chnl_offset80;
+ hal->current_band_type = ch > 14 ? BAND_ON_5G:BAND_ON_2_4G;
+
+ if (print) {
+ RTW_INFO(FUNC_ADPT_FMT" cch:%u, %s, offset40:%u, offset80:%u (%u, %u, %u), band:%s\n"
+ , FUNC_ADPT_ARG(padapter), center_ch, ch_width_str(bw)
+ , ch_offset, chnl_offset80
+ , hal->cch_80, hal->cch_40, hal->cch_20
+ , band_str(hal->current_band_type));
+ }
+}
+
+#ifdef DBG_RSVD_PAGE_CFG
+#define RSVD_PAGE_CFG(ops, v1, v2, v3) \
+ RTW_INFO("=== [RSVD][%s]-NeedPage:%d, TotalPageNum:%d TotalPacketLen:%d ===\n", \
+ ops, v1, v2, v3)
+#endif
+
u8 rtw_hal_dl_mcc_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 *index,
- u8 tx_desc, u32 page_size, u8 *page_num, u32 *total_pkt_len,
- RSVDPAGE_LOC *rsvd_page_loc)
+ u8 tx_desc, u32 page_size, u8 *total_page_num, RSVDPAGE_LOC *rsvd_page_loc, u8 *page_num)
{
u32 len = 0;
_adapter *iface = NULL;
@@ -261,8 +1033,21 @@ u8 rtw_hal_dl_mcc_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 *index,
struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
struct mlme_ext_info *pmlmeinfo = NULL;
struct mlme_ext_priv *pmlmeext = NULL;
- u8 ret = _SUCCESS, i = 0, order = 0, CurtPktPageNum = 0;
+ struct hal_com_data *hal = GET_HAL_DATA(adapter);
+ u8 ret = _SUCCESS, i = 0, j =0, order = 0, CurtPktPageNum = 0;
u8 bssid[ETH_ALEN] = {0};
+ u8 *start = NULL;
+ u8 path = RF_PATH_A;
+
+ if (page_num) {
+#ifdef CONFIG_MCC_MODE_V2
+ if (!hal->RegIQKFWOffload)
+ RTW_WARN("[MCC] must enable FW IQK for New IC\n");
+#endif /* CONFIG_MCC_MODE_V2 */
+ /* Null data(interface number) + power index(interface number) + 1 */
+ *total_page_num += (2 * dvobj->iface_nums + 3);
+ goto exit;
+ }
/* check proccess mcc start setting */
if (!rtw_hal_check_mcc_status(adapter, MCC_STATUS_PROCESS_MCC_START_SETTING)) {
@@ -276,7 +1061,7 @@ u8 rtw_hal_dl_mcc_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 *index,
continue;
order = iface->mcc_adapterpriv.order;
- dvobj->mcc_objpriv.mcc_loc_rsvd_paga[order] = *page_num;
+ dvobj->mcc_objpriv.mcc_loc_rsvd_paga[order] = *total_page_num;
switch (iface->mcc_adapterpriv.role) {
case MCC_ROLE_STA:
@@ -289,15 +1074,18 @@ u8 rtw_hal_dl_mcc_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 *index,
pmlmeinfo = &pmlmeext->mlmext_info;
_rtw_memcpy(bssid, get_my_bssid(&pmlmeinfo->network), ETH_ALEN);
+
rtw_hal_construct_NullFunctionData(iface
, &pframe[*index], &len, bssid, _FALSE, 0, 0, _FALSE);
- rtw_hal_fill_fake_txdesc(iface, &pframe[*index - tx_desc],
- len, _FALSE, _FALSE, _FALSE);
+ rtw_hal_fill_fake_txdesc(iface, &pframe[*index-tx_desc],
+ len, _FALSE, _FALSE, _FALSE);
CurtPktPageNum = (u8)PageNum(tx_desc + len, page_size);
- *page_num += CurtPktPageNum;
+ *total_page_num += CurtPktPageNum;
*index += (CurtPktPageNum * page_size);
- *total_pkt_len = *index + len;
+ #ifdef DBG_RSVD_PAGE_CFG
+ RSVD_PAGE_CFG("LocNull", CurtPktPageNum, *total_page_num, *index);
+ #endif
break;
case MCC_ROLE_AP:
/* Bulid CTS */
@@ -306,19 +1094,315 @@ u8 rtw_hal_dl_mcc_fw_rsvd_page(_adapter *adapter, u8 *pframe, u16 *index,
len = 0;
rtw_hal_construct_CTS(iface, &pframe[*index], &len);
- rtw_hal_fill_fake_txdesc(iface, &pframe[*index - tx_desc],
- len, _FALSE, _FALSE, _FALSE);
+ rtw_hal_fill_fake_txdesc(iface, &pframe[*index-tx_desc],
+ len, _FALSE, _FALSE, _FALSE);
CurtPktPageNum = (u8)PageNum(tx_desc + len, page_size);
- *page_num += CurtPktPageNum;
+ *total_page_num += CurtPktPageNum;
*index += (CurtPktPageNum * page_size);
- *total_pkt_len = *index + len;
+ #ifdef DBG_RSVD_PAGE_CFG
+ RSVD_PAGE_CFG("LocCTS", CurtPktPageNum, *total_page_num, *index);
+ #endif
break;
case MCC_ROLE_GO:
- /* To DO */
+ /* To DO */
break;
}
}
+
+ for (i = 0; i < MAX_MCC_NUM; i++) {
+ u8 center_ch = 0, ch = 0, bw = 0, bw_offset = 0;
+ u8 power_index = 0;
+ u8 rate_array_sz = 0;
+ u8 *rates = NULL;
+ u8 rate = 0;
+ u8 shift = 0;
+ u32 power_index_4bytes = 0;
+ u8 total_rate = 0;
+ u8 *total_rate_offset = NULL;
+
+ iface = pmccobjpriv->iface[i];
+ pmlmeext = &iface->mlmeextpriv;
+ ch = pmlmeext->cur_channel;
+ bw = pmlmeext->cur_bwmode;
+ bw_offset = pmlmeext->cur_ch_offset;
+ center_ch = rtw_get_center_ch(ch, bw, bw_offset);
+ rtw_hal_mcc_upadate_chnl_bw(iface, ch, bw_offset, bw, _TRUE);
+
+ start = &pframe[*index - tx_desc];
+ _rtw_memset(start, 0, page_size);
+ pmccobjpriv->mcc_pwr_idx_rsvd_page[i] = *total_page_num;
+ RTW_INFO(ADPT_FMT" order:%d, pwr_idx_rsvd_page location[%d]: %d\n",
+ ADPT_ARG(iface), iface->mcc_adapterpriv.order,
+ i, pmccobjpriv->mcc_pwr_idx_rsvd_page[i]);
+
+ total_rate_offset = start;
+
+ for (path = RF_PATH_A; path < hal->NumTotalRFPath; ++path) {
+ total_rate = 0;
+ /* PATH A for 0~63 byte, PATH B for 64~127 byte*/
+ if (path == RF_PATH_A)
+ start = total_rate_offset + 1;
+ else if (path == RF_PATH_B)
+ start = total_rate_offset + 64;
+ else {
+ RTW_INFO("[MCC] %s: unknow RF PATH(%d)\n", __func__, path);
+ break;
+ }
+
+ /* CCK */
+ if (ch <= 14) {
+ rate_array_sz = rates_by_sections[CCK].rate_num;
+ rates = rates_by_sections[CCK].rates;
+ for (j = 0; j < rate_array_sz; ++j) {
+ power_index = rtw_hal_get_tx_power_index(iface, path, rates[j], bw, center_ch, NULL);
+ rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
+
+ shift = rate % 4;
+ if (shift == 0) {
+ *start = rate;
+ start++;
+ total_rate++;
+
+ #ifdef DBG_PWR_IDX_RSVD_PAGE
+ RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
+ ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
+ center_ch, MGN_RATE_STR(rates[j]), power_index);
+ #endif
+ }
+
+ *start = power_index;
+ start++;
+
+ #ifdef DBG_PWR_IDX_RSVD_PAGE
+ RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
+ ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
+ center_ch, MGN_RATE_STR(rates[j]), power_index);
+
+
+ shift = rate % 4;
+ power_index_4bytes |= ((power_index & 0xff) << (shift * 8));
+ if (shift == 3) {
+ rate = rate - 3;
+ RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate);
+ power_index_4bytes = 0;
+ total_rate++;
+ }
+ #endif
+
+ }
+ }
+
+ /* OFDM */
+ rate_array_sz = rates_by_sections[OFDM].rate_num;
+ rates = rates_by_sections[OFDM].rates;
+ for (j = 0; j < rate_array_sz; ++j) {
+ power_index = rtw_hal_get_tx_power_index(iface, path, rates[j], bw, center_ch, NULL);
+ rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
+
+ shift = rate % 4;
+ if (shift == 0) {
+ *start = rate;
+ start++;
+ total_rate++;
+
+ #ifdef DBG_PWR_IDX_RSVD_PAGE
+ RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
+ ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
+ center_ch, MGN_RATE_STR(rates[j]), power_index);
+ #endif
+
+ }
+
+ *start = power_index;
+ start++;
+
+ #ifdef DBG_PWR_IDX_RSVD_PAGE
+ RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
+ ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
+ center_ch, MGN_RATE_STR(rates[j]), power_index);
+
+ shift = rate % 4;
+ power_index_4bytes |= ((power_index & 0xff) << (shift * 8));
+ if (shift == 3) {
+ rate = rate - 3;
+ RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate);
+ power_index_4bytes = 0;
+ total_rate++;
+ }
+ #endif
+ }
+
+ /* HT_MCS0_MCS7 */
+ rate_array_sz = rates_by_sections[HT_MCS0_MCS7].rate_num;
+ rates = rates_by_sections[HT_MCS0_MCS7].rates;
+ for (j = 0; j < rate_array_sz; ++j) {
+ power_index = rtw_hal_get_tx_power_index(iface, path, rates[j], bw, center_ch, NULL);
+ rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
+
+ shift = rate % 4;
+ if (shift == 0) {
+ *start = rate;
+ start++;
+ total_rate++;
+
+ #ifdef DBG_PWR_IDX_RSVD_PAGE
+ RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
+ ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
+ center_ch, MGN_RATE_STR(rates[j]), power_index);
+ #endif
+
+ }
+
+ *start = power_index;
+ start++;
+
+ #ifdef DBG_PWR_IDX_RSVD_PAGE
+ RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
+ ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
+ center_ch, MGN_RATE_STR(rates[j]), power_index);
+
+ shift = rate % 4;
+ power_index_4bytes |= ((power_index & 0xff) << (shift * 8));
+ if (shift == 3) {
+ rate = rate - 3;
+ RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate);
+ power_index_4bytes = 0;
+ total_rate++;
+ }
+ #endif
+ }
+
+ /* HT_MCS8_MCS15 */
+ rate_array_sz = rates_by_sections[HT_MCS8_MCS15].rate_num;
+ rates = rates_by_sections[HT_MCS8_MCS15].rates;
+ for (j = 0; j < rate_array_sz; ++j) {
+ power_index = rtw_hal_get_tx_power_index(iface, path, rates[j], bw, center_ch, NULL);
+ rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
+
+ shift = rate % 4;
+ if (shift == 0) {
+ *start = rate;
+ start++;
+ total_rate++;
+
+ #ifdef DBG_PWR_IDX_RSVD_PAGE
+ RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
+ ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
+ center_ch, MGN_RATE_STR(rates[j]), power_index);
+ #endif
+ }
+
+ *start = power_index;
+ start++;
+
+ #ifdef DBG_PWR_IDX_RSVD_PAGE
+ RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
+ ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
+ center_ch, MGN_RATE_STR(rates[j]), power_index);
+
+ shift = rate % 4;
+ power_index_4bytes |= ((power_index & 0xff) << (shift * 8));
+ if (shift == 3) {
+ rate = rate - 3;
+ RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate);
+ power_index_4bytes = 0;
+ total_rate++;
+ }
+ #endif
+ }
+
+ /* VHT_1SSMCS0_1SSMCS9 */
+ rate_array_sz = rates_by_sections[VHT_1SSMCS0_1SSMCS9].rate_num;
+ rates = rates_by_sections[VHT_1SSMCS0_1SSMCS9].rates;
+ for (j = 0; j < rate_array_sz; ++j) {
+ power_index = rtw_hal_get_tx_power_index(iface, path, rates[j], bw, center_ch, NULL);
+ rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
+
+ shift = rate % 4;
+ if (shift == 0) {
+ *start = rate;
+ start++;
+ total_rate++;
+ #ifdef DBG_PWR_IDX_RSVD_PAGE
+ RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:0x%02x\n",
+ ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
+ center_ch, MGN_RATE_STR(rates[j]), power_index);
+ #endif
+ }
+ *start = power_index;
+ start++;
+ #ifdef DBG_PWR_IDX_RSVD_PAGE
+ RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
+ ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
+ center_ch, MGN_RATE_STR(rates[j]), power_index);
+
+ shift = rate % 4;
+ power_index_4bytes |= ((power_index & 0xff) << (shift * 8));
+ if (shift == 3) {
+ rate = rate - 3;
+ RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate);
+ power_index_4bytes = 0;
+ total_rate++;
+ }
+ #endif
+ }
+
+ /* VHT_2SSMCS0_2SSMCS9 */
+ rate_array_sz = rates_by_sections[VHT_2SSMCS0_2SSMCS9].rate_num;
+ rates = rates_by_sections[VHT_2SSMCS0_2SSMCS9].rates;
+ for (j = 0; j < rate_array_sz; ++j) {
+ power_index = rtw_hal_get_tx_power_index(iface, path, rates[j], bw, center_ch, NULL);
+ rate = PHY_GetRateIndexOfTxPowerByRate(rates[j]);
+
+ shift = rate % 4;
+ if (shift == 0) {
+ *start = rate;
+ start++;
+ total_rate++;
+ #ifdef DBG_PWR_IDX_RSVD_PAGE
+ RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
+ ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
+ center_ch, MGN_RATE_STR(rates[j]), power_index);
+ #endif
+ }
+ *start = power_index;
+ start++;
+ #ifdef DBG_PWR_IDX_RSVD_PAGE
+ RTW_INFO("TXPWR("ADPT_FMT"): [%c][%s]ch:%u, %s, pwr_idx:%u\n",
+ ADPT_ARG(iface), rf_path_char(path), ch_width_str(bw),
+ center_ch, MGN_RATE_STR(rates[j]), power_index);
+
+ shift = rate % 4;
+ power_index_4bytes |= ((power_index & 0xff) << (shift * 8));
+ if (shift == 3) {
+ rate = rate - 3;
+ RTW_INFO("(index:0x%02x, rfpath:%d, rate:0x%02x)\n", index, path, rate);
+ power_index_4bytes = 0;
+ total_rate++;
+ }
+ #endif
+ }
+
+ }
+ /* total rate store in offset 0 */
+ *total_rate_offset = total_rate;
+
+#ifdef DBG_PWR_IDX_RSVD_PAGE
+ RTW_INFO("total_rate=%d\n", total_rate);
+ RTW_INFO(" ======================="ADPT_FMT"===========================\n", ADPT_ARG(iface));
+ RTW_INFO_DUMP("\n", total_rate_offset, 128);
+ RTW_INFO(" ==================================================\n");
+#endif
+
+ CurtPktPageNum = 1;
+ *total_page_num += CurtPktPageNum;
+ *index += (CurtPktPageNum * page_size);
+ #ifdef DBG_RSVD_PAGE_CFG
+ RSVD_PAGE_CFG("mcc_pwr_idx_rsvd_page", CurtPktPageNum, *total_page_num, *index);
+ #endif
+ }
+
exit:
return ret;
}
@@ -346,7 +1430,7 @@ static void rtw_hal_set_fw_mcc_rsvd_page(PADAPTER padapter)
iface = pmccobjpriv->iface[i];
pmccadapriv = &iface->mcc_adapterpriv;
if (pmccadapriv->role == MCC_ROLE_AP
- || pmccadapriv->role == MCC_ROLE_GO)
+ || pmccadapriv->role == MCC_ROLE_GO)
tx_beacon_hdl(iface, NULL);
}
}
@@ -355,23 +1439,17 @@ static void rtw_hal_set_mcc_rsvdpage_cmd(_adapter *padapter)
{
u8 cmd[H2C_MCC_LOCATION_LEN] = {0}, i = 0, order = 0;
_adapter *iface = NULL;
+ PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter);
struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
+ SET_H2CCMD_MCC_PWRIDX_OFFLOAD_EN(cmd, _TRUE);
+ SET_H2CCMD_MCC_PWRIDX_OFFLOAD_RFNUM(cmd, hal->NumTotalRFPath);
+ for (order = 0; order < MAX_MCC_NUM; order++) {
+ iface = pmccobjpriv->iface[i];
- for (i = 0; i < dvobj->iface_nums; i++) {
- iface = dvobj->padapters[i];
- if (iface == NULL)
- continue;
-
- order = iface->mcc_adapterpriv.order;
- if (order >= H2C_MCC_LOCATION_LEN) {
- RTW_INFO(FUNC_ADPT_FMT" only support 3 interface at most(%d)\n"
- , FUNC_ADPT_ARG(padapter), order);
- continue;
- }
-
- SET_H2CCMD_MCC_RSVDPAGE_LOC((cmd + order), (pmccobjpriv->mcc_loc_rsvd_paga[order]));
+ SET_H2CCMD_MCC_RSVDPAGE_LOC((cmd + order), pmccobjpriv->mcc_loc_rsvd_paga[order]);
+ SET_H2CCMD_MCC_PWRIDX_RSVDPAGE_LOC ((cmd + order), pmccobjpriv->mcc_pwr_idx_rsvd_page[order]);
}
#ifdef CONFIG_MCC_MODE_DEBUG
@@ -386,109 +1464,146 @@ static void rtw_hal_set_mcc_rsvdpage_cmd(_adapter *padapter)
rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_LOCATION, H2C_MCC_LOCATION_LEN, cmd);
}
-static void rtw_hal_set_mcc_noa_cmd(PADAPTER padapter)
+static void rtw_hal_set_mcc_time_setting_cmd(PADAPTER padapter)
{
struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
- u8 cmd[H2C_MCC_NOA_PARAM_LEN] = {0};
- u8 noa_fw_eable = 1;
- u8 noa_tsf_sync_offset = 50;
- u8 noa_start_time = 30;
- u8 noa_interval = pmlmepriv->cur_network.network.Configuration.BeaconPeriod;
+ struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+ struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
+ u8 cmd[H2C_MCC_TIME_SETTING_LEN] = {0};
+ u8 fw_eable = 1;
u8 swchannel_early_time = MCC_SWCH_FW_EARLY_TIME;
- u8 i = 0;
+
- /* FW set NOA enable */
- SET_H2CCMD_MCC_NOA_FW_EN(cmd, noa_fw_eable);
- /* TSF Sync offset */
- SET_H2CCMD_MCC_NOA_TSF_SYNC_OFFSET(cmd, noa_tsf_sync_offset);
- /* NoA start time offset */
- SET_H2CCMD_MCC_NOA_START_TIME(cmd, noa_start_time);
- /* NoA interval */
- SET_H2CCMD_MCC_NOA_INTERVAL(cmd, noa_interval);
- /* Early time to inform driver by C2H before switch channel */
- SET_H2CCMD_MCC_EARLY_TIME(cmd, swchannel_early_time);
+ if (MSTATE_AP_STARTING_NUM(&mcc_mstate) == 0
+ && MSTATE_AP_NUM(&mcc_mstate) == 0)
+ /* For STA+GC/STA+STA, TSF of GC/STA does not need to sync from TSF of other STA/GC */
+ fw_eable = 0;
+ else
+ /* Only for STA+GO/STA+AP, TSF of AP/GO need to sync from TSF of STA */
+ fw_eable = 1;
+
+ if (fw_eable == 1) {
+ u8 policy_idx = pmccobjpriv->policy_index;
+ u8 tsf_sync_offset = mcc_switch_channel_policy_table[policy_idx][MCC_TSF_SYNC_OFFSET_IDX];
+ u8 start_time_offset = mcc_switch_channel_policy_table[policy_idx][MCC_START_TIME_OFFSET_IDX];
+ u8 interval = mcc_switch_channel_policy_table[policy_idx][MCC_INTERVAL_IDX];
+ u8 guard_offset0 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET0_IDX];
+ u8 guard_offset1 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET1_IDX];
+ /* FW set enable */
+ SET_H2CCMD_MCC_TIME_SETTING_FW_EN(cmd, fw_eable);
+ /* TSF Sync offset */
+ SET_H2CCMD_MCC_TIME_SETTING_TSF_SYNC_OFFSET(cmd, tsf_sync_offset);
+ /* start time offset */
+ SET_H2CCMD_MCC_TIME_SETTING_START_TIME(cmd, (start_time_offset + guard_offset0));
+ /* interval */
+ SET_H2CCMD_MCC_TIME_SETTING_INTERVAL(cmd, interval);
+ /* Early time to inform driver by C2H before switch channel */
+ SET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(cmd, swchannel_early_time);
+ /* Port0 sync from Port1, not support multi-port */
+ SET_H2CCMD_MCC_TIME_SETTING_ORDER_BASE(cmd, HW_PORT1);
+ SET_H2CCMD_MCC_TIME_SETTING_ORDER_SYNC(cmd, HW_PORT0);
+ } else {
+ /* start time offset */
+ SET_H2CCMD_MCC_TIME_SETTING_START_TIME(cmd, pmccobjpriv->start_time);
+ /* interval */
+ SET_H2CCMD_MCC_TIME_SETTING_INTERVAL(cmd, pmccobjpriv->interval);
+ /* Early time to inform driver by C2H before switch channel */
+ SET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(cmd, swchannel_early_time);
+ }
#ifdef CONFIG_MCC_MODE_DEBUG
- RTW_INFO("=========================\n");
- RTW_INFO("NoA:\n");
- for (i = 0; i < H2C_MCC_NOA_PARAM_LEN; i++)
- pr_dbg("0x%x ", cmd[i]);
- pr_dbg("\n");
- RTW_INFO("=========================\n");
+ {
+ u8 i = 0;
+
+ RTW_INFO("=========================\n");
+ RTW_INFO("NoA:\n");
+ for (i = 0; i < H2C_MCC_TIME_SETTING_LEN; i++)
+ pr_dbg("0x%x ", cmd[i]);
+ pr_dbg("\n");
+ RTW_INFO("=========================\n");
+ }
#endif /* CONFIG_MCC_MODE_DEBUG */
- rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_NOA_PARAM, H2C_MCC_NOA_PARAM_LEN, cmd);
+ rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_TIME_SETTING, H2C_MCC_TIME_SETTING_LEN, cmd);
}
static void rtw_hal_set_mcc_IQK_offload_cmd(PADAPTER padapter)
{
struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+ struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
struct mcc_adapter_priv *pmccadapriv = NULL;
_adapter *iface = NULL;
u8 cmd[H2C_MCC_IQK_PARAM_LEN] = {0}, bready = 0, i = 0, order = 0;
u16 TX_X = 0, TX_Y = 0, RX_X = 0, RX_Y = 0;
+ u8 total_rf_path = GET_HAL_DATA(padapter)->NumTotalRFPath;
+ u8 rf_path_idx = 0, last_order = MAX_MCC_NUM - 1, last_rf_path_index = total_rf_path - 1;
+ /* by order, last order & last_rf_path_index must set ready bit = 1 */
for (i = 0; i < dvobj->iface_nums; i++) {
- iface = dvobj->padapters[i];
+ iface = pmccobjpriv->iface[i];
if (iface == NULL)
continue;
pmccadapriv = &iface->mcc_adapterpriv;
order = pmccadapriv->order;
- /* TO DO for multi-antenna(FW not support) */
- TX_X = pmccadapriv->mcc_iqk_arr[0].TX_X & 0x7ff;/* [10:0] */
- TX_Y = pmccadapriv->mcc_iqk_arr[0].TX_Y & 0x7ff;/* [10:0] */
- RX_X = pmccadapriv->mcc_iqk_arr[0].RX_X & 0x3ff;/* [9:0] */
- RX_Y = pmccadapriv->mcc_iqk_arr[0].RX_Y & 0x3ff;/* [9:0] */
- _rtw_memset(cmd, 0, H2C_MCC_IQK_PARAM_LEN);
-
- /* ready or not */
- if (order == 1)
- bready = 1;
- else
- bready = 0;
-
- SET_H2CCMD_MCC_IQK_READY(cmd, bready);
- SET_H2CCMD_MCC_IQK_ORDER(cmd, order);
-
- /* fill RX_X[7:0] to (cmd+1)[7:0] bitlen=8 */
- SET_H2CCMD_MCC_IQK_RX_L(cmd, (u8)(RX_X & 0xff));
- /* fill RX_X[9:8] to (cmd+2)[1:0] bitlen=2 */
- SET_H2CCMD_MCC_IQK_RX_M1(cmd, (u8)((RX_X >> 8) & 0x03));
- /* fill RX_Y[5:0] to (cmd+2)[7:2] bitlen=6 */
- SET_H2CCMD_MCC_IQK_RX_M2(cmd, (u8)(RX_Y & 0x3f));
- /* fill RX_Y[9:6] to (cmd+3)[3:0] bitlen=4 */
- SET_H2CCMD_MCC_IQK_RX_H(cmd, (u8)((RX_Y >> 6) & 0x0f));
-
-
- /* fill TX_X[7:0] to (cmd+4)[7:0] bitlen=8 */
- SET_H2CCMD_MCC_IQK_TX_L(cmd, (u8)(TX_X & 0xff));
- /* fill TX_X[10:8] to (cmd+5)[2:0] bitlen=3 */
- SET_H2CCMD_MCC_IQK_TX_M1(cmd, (u8)((TX_X >> 8) & 0x07));
- /* fill TX_Y[4:0] to (cmd+5)[7:3] bitlen=5 */
- SET_H2CCMD_MCC_IQK_TX_M2(cmd, (u8)(TX_Y & 0x1f));
- /* fill TX_Y[10:5] to (cmd+6)[5:0] bitlen=6 */
- SET_H2CCMD_MCC_IQK_TX_H(cmd, (u8)((TX_Y >> 5) & 0x3f));
+
+ for (rf_path_idx = 0; rf_path_idx < total_rf_path; rf_path_idx ++) {
+
+ _rtw_memset(cmd, 0, H2C_MCC_IQK_PARAM_LEN);
+ TX_X = pmccadapriv->mcc_iqk_arr[rf_path_idx].TX_X & 0x7ff;/* [10:0] */
+ TX_Y = pmccadapriv->mcc_iqk_arr[rf_path_idx].TX_Y & 0x7ff;/* [10:0] */
+ RX_X = pmccadapriv->mcc_iqk_arr[rf_path_idx].RX_X & 0x3ff;/* [9:0] */
+ RX_Y = pmccadapriv->mcc_iqk_arr[rf_path_idx].RX_Y & 0x3ff;/* [9:0] */
+
+ /* ready or not */
+ if (order == last_order && rf_path_idx == last_rf_path_index)
+ bready = 1;
+ else
+ bready = 0;
+
+ SET_H2CCMD_MCC_IQK_READY(cmd, bready);
+ SET_H2CCMD_MCC_IQK_ORDER(cmd, order);
+ SET_H2CCMD_MCC_IQK_PATH(cmd, rf_path_idx);
+
+ /* fill RX_X[7:0] to (cmd+1)[7:0] bitlen=8 */
+ SET_H2CCMD_MCC_IQK_RX_L(cmd, (u8)(RX_X & 0xff));
+ /* fill RX_X[9:8] to (cmd+2)[1:0] bitlen=2 */
+ SET_H2CCMD_MCC_IQK_RX_M1(cmd, (u8)((RX_X >> 8) & 0x03));
+ /* fill RX_Y[5:0] to (cmd+2)[7:2] bitlen=6 */
+ SET_H2CCMD_MCC_IQK_RX_M2(cmd, (u8)(RX_Y & 0x3f));
+ /* fill RX_Y[9:6] to (cmd+3)[3:0] bitlen=4 */
+ SET_H2CCMD_MCC_IQK_RX_H(cmd, (u8)((RX_Y >> 6) & 0x0f));
+
+
+ /* fill TX_X[7:0] to (cmd+4)[7:0] bitlen=8 */
+ SET_H2CCMD_MCC_IQK_TX_L(cmd, (u8)(TX_X & 0xff));
+ /* fill TX_X[10:8] to (cmd+5)[2:0] bitlen=3 */
+ SET_H2CCMD_MCC_IQK_TX_M1(cmd, (u8)((TX_X >> 8) & 0x07));
+ /* fill TX_Y[4:0] to (cmd+5)[7:3] bitlen=5 */
+ SET_H2CCMD_MCC_IQK_TX_M2(cmd, (u8)(TX_Y & 0x1f));
+ /* fill TX_Y[10:5] to (cmd+6)[5:0] bitlen=6 */
+ SET_H2CCMD_MCC_IQK_TX_H(cmd, (u8)((TX_Y >> 5) & 0x3f));
#ifdef CONFIG_MCC_MODE_DEBUG
- RTW_INFO("=========================\n");
- RTW_INFO(FUNC_ADPT_FMT" IQK:\n", FUNC_ADPT_ARG(iface));
- RTW_INFO("TX_X: 0x%02x\n", TX_X);
- RTW_INFO("TX_Y: 0x%02x\n", TX_Y);
- RTW_INFO("RX_X: 0x%02x\n", RX_X);
- RTW_INFO("RX_Y: 0x%02x\n", RX_Y);
- RTW_INFO("cmd[0]:0x%02x\n", cmd[0]);
- RTW_INFO("cmd[1]:0x%02x\n", cmd[1]);
- RTW_INFO("cmd[2]:0x%02x\n", cmd[2]);
- RTW_INFO("cmd[3]:0x%02x\n", cmd[3]);
- RTW_INFO("cmd[4]:0x%02x\n", cmd[4]);
- RTW_INFO("cmd[5]:0x%02x\n", cmd[5]);
- RTW_INFO("cmd[6]:0x%02x\n", cmd[6]);
- RTW_INFO("=========================\n");
+ RTW_INFO("=========================\n");
+ RTW_INFO(FUNC_ADPT_FMT" IQK:\n", FUNC_ADPT_ARG(iface));
+ RTW_INFO("TX_X: 0x%02x\n", TX_X);
+ RTW_INFO("TX_Y: 0x%02x\n", TX_Y);
+ RTW_INFO("RX_X: 0x%02x\n", RX_X);
+ RTW_INFO("RX_Y: 0x%02x\n", RX_Y);
+ RTW_INFO("cmd[0]:0x%02x\n", cmd[0]);
+ RTW_INFO("cmd[1]:0x%02x\n", cmd[1]);
+ RTW_INFO("cmd[2]:0x%02x\n", cmd[2]);
+ RTW_INFO("cmd[3]:0x%02x\n", cmd[3]);
+ RTW_INFO("cmd[4]:0x%02x\n", cmd[4]);
+ RTW_INFO("cmd[5]:0x%02x\n", cmd[5]);
+ RTW_INFO("cmd[6]:0x%02x\n", cmd[6]);
+ RTW_INFO("=========================\n");
#endif /* CONFIG_MCC_MODE_DEBUG */
- rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_IQK_PARAM, H2C_MCC_IQK_PARAM_LEN, cmd);
+ rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_IQK_PARAM, H2C_MCC_IQK_PARAM_LEN, cmd);
+ }
}
}
@@ -510,9 +1625,9 @@ static void rtw_hal_set_mcc_macid_cmd(PADAPTER padapter)
order = pmccadapriv->order;
bitmap = pmccadapriv->mcc_macid_bitmap;
- if (order >= (H2C_MCC_MACID_BITMAP_LEN / 2)) {
+ if (order >= (H2C_MCC_MACID_BITMAP_LEN/2)) {
RTW_INFO(FUNC_ADPT_FMT" only support 3 interface at most(%d)\n"
- , FUNC_ADPT_ARG(padapter), order);
+ , FUNC_ADPT_ARG(padapter), order);
continue;
}
SET_H2CCMD_MCC_MACID_BITMAP_L((cmd + order * 2), (u8)(bitmap & 0xff));
@@ -523,16 +1638,161 @@ static void rtw_hal_set_mcc_macid_cmd(PADAPTER padapter)
RTW_INFO("=========================\n");
RTW_INFO("MACID BITMAP: ");
for (i = 0; i < H2C_MCC_MACID_BITMAP_LEN; i++)
- pr_dbg("0x%x ", cmd[i]);
- pr_dbg("\n");
+ printk("0x%x ", cmd[i]);
+ printk("\n");
RTW_INFO("=========================\n");
#endif /* CONFIG_MCC_MODE_DEBUG */
rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_MACID_BITMAP, H2C_MCC_MACID_BITMAP_LEN, cmd);
}
-static void rtw_hal_set_mcc_parameter_cmd(PADAPTER padapter, u8 stop)
+#ifdef CONFIG_MCC_MODE_V2
+static u8 get_pri_ch_idx_by_adapter(u8 center_ch, u8 channel, u8 bw, u8 ch_offset40)
{
- u8 cmd[H2C_MCC_INFO_LEN] = {0}, i = 0;
+ u8 pri_ch_idx = 0, chnl_offset80 = 0;
+
+ if (bw == CHANNEL_WIDTH_80) {
+ if (center_ch > channel)
+ chnl_offset80 = HAL_PRIME_CHNL_OFFSET_LOWER;
+ else if (center_ch < channel)
+ chnl_offset80 = HAL_PRIME_CHNL_OFFSET_UPPER;
+ else
+ chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+ }
+
+ if (bw == CHANNEL_WIDTH_80) {
+ /* primary channel is at lower subband of 80MHz & 40MHz */
+ if ((ch_offset40 == HAL_PRIME_CHNL_OFFSET_LOWER) && (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_LOWER))
+ pri_ch_idx = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
+ /* primary channel is at lower subband of 80MHz & upper subband of 40MHz */
+ else if ((ch_offset40 == HAL_PRIME_CHNL_OFFSET_UPPER) && (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_LOWER))
+ pri_ch_idx = VHT_DATA_SC_20_LOWER_OF_80MHZ;
+ /* primary channel is at upper subband of 80MHz & lower subband of 40MHz */
+ else if ((ch_offset40 == HAL_PRIME_CHNL_OFFSET_LOWER) && (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_UPPER))
+ pri_ch_idx = VHT_DATA_SC_20_UPPER_OF_80MHZ;
+ /* primary channel is at upper subband of 80MHz & upper subband of 40MHz */
+ else if ((ch_offset40 == HAL_PRIME_CHNL_OFFSET_UPPER) && (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_UPPER))
+ pri_ch_idx = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
+ else {
+ if (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_LOWER)
+ pri_ch_idx = VHT_DATA_SC_40_LOWER_OF_80MHZ;
+ else if (chnl_offset80 == HAL_PRIME_CHNL_OFFSET_UPPER)
+ pri_ch_idx = VHT_DATA_SC_40_UPPER_OF_80MHZ;
+ else
+ RTW_INFO("SCMapping: DONOT CARE Mode Setting\n");
+ }
+ } else if (bw == CHANNEL_WIDTH_40) {
+ /* primary channel is at upper subband of 40MHz */
+ if (ch_offset40== HAL_PRIME_CHNL_OFFSET_UPPER)
+ pri_ch_idx = VHT_DATA_SC_20_UPPER_OF_80MHZ;
+ /* primary channel is at lower subband of 40MHz */
+ else if (ch_offset40 == HAL_PRIME_CHNL_OFFSET_LOWER)
+ pri_ch_idx = VHT_DATA_SC_20_LOWER_OF_80MHZ;
+ else
+ RTW_INFO("SCMapping: DONOT CARE Mode Setting\n");
+ }
+
+ return pri_ch_idx;
+}
+
+static void rtw_hal_set_mcc_ctrl_cmd_v2(PADAPTER padapter, u8 stop)
+{
+ u8 cmd[H2C_MCC_CTRL_LEN] = {0}, i = 0;
+ u8 order = 0, totalnum = 0;
+ u8 center_ch = 0, pri_ch_idx = 0, bw = 0;
+ u8 duration = 0, role = 0, incurch = 0, rfetype = 0, distxnull = 0, c2hrpt = 0;
+ u8 dis_sw_retry = 0, null_early_time=2, tsfx = 0, update_parm = 0;
+ struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+ struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
+ struct mlme_ext_priv *pmlmeext = NULL;
+ struct mlme_ext_info *pmlmeinfo = NULL;
+ _adapter *iface = NULL;
+
+ RTW_INFO(FUNC_ADPT_FMT": stop=%d\n", FUNC_ADPT_ARG(padapter), stop);
+
+ for (i = 0; i < dvobj->iface_nums; i++) {
+ iface = pmccobjpriv->iface[i];
+ if (iface == NULL)
+ continue;
+
+ if (stop) {
+ if (iface != padapter)
+ continue;
+ }
+
+
+ order = iface->mcc_adapterpriv.order;
+ if (!stop)
+ totalnum = dvobj->iface_nums;
+ else
+ totalnum = 0xff; /* 0xff means stop */
+
+ pmlmeext = &iface->mlmeextpriv;
+ center_ch = rtw_get_center_ch(pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset);
+ pri_ch_idx = get_pri_ch_idx_by_adapter(center_ch, pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset);
+ bw = pmlmeext->cur_bwmode;
+ duration = iface->mcc_adapterpriv.mcc_duration;
+ role = iface->mcc_adapterpriv.role;
+
+ incurch = _FALSE;
+ dis_sw_retry = _TRUE;
+
+ /* STA/GC TX NULL data to inform AP/GC for ps mode */
+ switch (role) {
+ case MCC_ROLE_GO:
+ case MCC_ROLE_AP:
+ distxnull = MCC_DISABLE_TX_NULL;
+ break;
+ case MCC_ROLE_GC:
+ set_channel_bwmode(iface, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
+ distxnull = MCC_ENABLE_TX_NULL;
+ break;
+ case MCC_ROLE_STA:
+ distxnull = MCC_ENABLE_TX_NULL;
+ break;
+ }
+
+ null_early_time = iface->mcc_adapterpriv.null_early;
+
+ c2hrpt = MCC_C2H_REPORT_ALL_STATUS;
+ tsfx = iface->hw_port;
+ update_parm = 0;
+
+ SET_H2CCMD_MCC_CTRL_V2_ORDER(cmd, order);
+ SET_H2CCMD_MCC_CTRL_V2_TOTALNUM(cmd, totalnum);
+ SET_H2CCMD_MCC_CTRL_V2_CENTRAL_CH(cmd, center_ch);
+ SET_H2CCMD_MCC_CTRL_V2_PRIMARY_CH(cmd, pri_ch_idx);
+ SET_H2CCMD_MCC_CTRL_V2_BW(cmd, bw);
+ SET_H2CCMD_MCC_CTRL_V2_DURATION(cmd, duration);
+ SET_H2CCMD_MCC_CTRL_V2_ROLE(cmd, role);
+ SET_H2CCMD_MCC_CTRL_V2_INCURCH(cmd, incurch);
+ SET_H2CCMD_MCC_CTRL_V2_DIS_SW_RETRY(cmd, dis_sw_retry);
+ SET_H2CCMD_MCC_CTRL_V2_DISTXNULL(cmd, distxnull);
+ SET_H2CCMD_MCC_CTRL_V2_C2HRPT(cmd, c2hrpt);
+ SET_H2CCMD_MCC_CTRL_V2_TSFX(cmd, tsfx);
+ SET_H2CCMD_MCC_CTRL_V2_NULL_EARLY(cmd, null_early_time);
+ SET_H2CCMD_MCC_CTRL_V2_UPDATE_PARM(cmd, update_parm);
+
+#ifdef CONFIG_MCC_MODE_DEBUG
+ RTW_INFO("=========================\n");
+ RTW_INFO(FUNC_ADPT_FMT" MCC INFO:\n", FUNC_ADPT_ARG(iface));
+ RTW_INFO("cmd[0]:0x%02x\n", cmd[0]);
+ RTW_INFO("cmd[1]:0x%02x\n", cmd[1]);
+ RTW_INFO("cmd[2]:0x%02x\n", cmd[2]);
+ RTW_INFO("cmd[3]:0x%02x\n", cmd[3]);
+ RTW_INFO("cmd[4]:0x%02x\n", cmd[4]);
+ RTW_INFO("cmd[5]:0x%02x\n", cmd[5]);
+ RTW_INFO("cmd[6]:0x%02x\n", cmd[6]);
+ RTW_INFO("=========================\n");
+#endif /* CONFIG_MCC_MODE_DEBUG */
+
+ rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_CTRL_V2, H2C_MCC_CTRL_LEN, cmd);
+ }
+}
+
+#else
+static void rtw_hal_set_mcc_ctrl_cmd_v1(PADAPTER padapter, u8 stop)
+{
+ u8 cmd[H2C_MCC_CTRL_LEN] = {0}, i = 0;
u8 order = 0, totalnum = 0, chidx = 0, bw = 0, bw40sc = 0, bw80sc = 0;
u8 duration = 0, role = 0, incurch = 0, rfetype = 0, distxnull = 0, c2hrpt = 0, chscan = 0;
struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
@@ -585,7 +1845,7 @@ static void rtw_hal_set_mcc_parameter_cmd(PADAPTER padapter, u8 stop)
incurch = _FALSE;
if (IS_HARDWARE_TYPE_8812(padapter))
- rfetype = pHalData->RFEType; /* RFETYPE (only for 8812)*/
+ rfetype = pHalData->rfe_type; /* RFETYPE (only for 8812)*/
else
rfetype = 0;
@@ -604,19 +1864,19 @@ static void rtw_hal_set_mcc_parameter_cmd(PADAPTER padapter, u8 stop)
c2hrpt = MCC_C2H_REPORT_ALL_STATUS;
chscan = MCC_CHIDX;
- SET_H2CCMD_MCC_INFO_ORDER(cmd, order);
- SET_H2CCMD_MCC_INFO_TOTALNUM(cmd, totalnum);
- SET_H2CCMD_MCC_INFO_CHIDX(cmd, chidx);
- SET_H2CCMD_MCC_INFO_BW(cmd, bw);
- SET_H2CCMD_MCC_INFO_BW40SC(cmd, bw40sc);
- SET_H2CCMD_MCC_INFO_BW80SC(cmd, bw80sc);
- SET_H2CCMD_MCC_INFO_DURATION(cmd, duration);
- SET_H2CCMD_MCC_INFO_ROLE(cmd, role);
- SET_H2CCMD_MCC_INFO_INCURCH(cmd, incurch);
- SET_H2CCMD_MCC_INFO_RFETYPE(cmd, rfetype);
- SET_H2CCMD_MCC_INFO_DISTXNULL(cmd, distxnull);
- SET_H2CCMD_MCC_INFO_C2HRPT(cmd, c2hrpt);
- SET_H2CCMD_MCC_INFO_CHSCAN(cmd, chscan);
+ SET_H2CCMD_MCC_CTRL_ORDER(cmd, order);
+ SET_H2CCMD_MCC_CTRL_TOTALNUM(cmd, totalnum);
+ SET_H2CCMD_MCC_CTRL_CHIDX(cmd, chidx);
+ SET_H2CCMD_MCC_CTRL_BW(cmd, bw);
+ SET_H2CCMD_MCC_CTRL_BW40SC(cmd, bw40sc);
+ SET_H2CCMD_MCC_CTRL_BW80SC(cmd, bw80sc);
+ SET_H2CCMD_MCC_CTRL_DURATION(cmd, duration);
+ SET_H2CCMD_MCC_CTRL_ROLE(cmd, role);
+ SET_H2CCMD_MCC_CTRL_INCURCH(cmd, incurch);
+ SET_H2CCMD_MCC_CTRL_RFETYPE(cmd, rfetype);
+ SET_H2CCMD_MCC_CTRL_DISTXNULL(cmd, distxnull);
+ SET_H2CCMD_MCC_CTRL_C2HRPT(cmd, c2hrpt);
+ SET_H2CCMD_MCC_CTRL_CHSCAN(cmd, chscan);
#ifdef CONFIG_MCC_MODE_DEBUG
RTW_INFO("=========================\n");
@@ -631,13 +1891,25 @@ static void rtw_hal_set_mcc_parameter_cmd(PADAPTER padapter, u8 stop)
RTW_INFO("=========================\n");
#endif /* CONFIG_MCC_MODE_DEBUG */
- rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_INFO, H2C_MCC_INFO_LEN, cmd);
- }
+ rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_CTRL, H2C_MCC_CTRL_LEN, cmd);
+ }
+}
+#endif
+
+static void rtw_hal_set_mcc_ctrl_cmd(PADAPTER padapter, u8 stop)
+{
+ #ifdef CONFIG_MCC_MODE_V2
+ /* new cmd 0x17 */
+ rtw_hal_set_mcc_ctrl_cmd_v2(padapter, stop);
+ #else
+ /* old cmd 0x18 */
+ rtw_hal_set_mcc_ctrl_cmd_v1(padapter, stop);
+ #endif
}
static u8 rtw_hal_set_mcc_start_setting(PADAPTER padapter, u8 status)
{
- u8 ret = _SUCCESS;
+ u8 ret = _SUCCESS, enable_tsf_auto_sync = _FALSE;
struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
@@ -653,6 +1925,12 @@ static u8 rtw_hal_set_mcc_start_setting(PADAPTER padapter, u8 status)
goto exit;
}
+ /* update mi_state to decide STA+STA or AP+STA */
+ rtw_mi_status(padapter, &mcc_mstate);
+
+ /* configure mcc switch channel setting */
+ rtw_hal_config_mcc_switch_channel_setting(padapter);
+
if (rtw_hal_decide_mcc_role(padapter) == _FAIL) {
ret = _FAIL;
goto exit;
@@ -668,17 +1946,22 @@ static u8 rtw_hal_set_mcc_start_setting(PADAPTER padapter, u8 status)
rtw_hal_set_mcc_rsvdpage_cmd(padapter);
}
- /* configure NoA setting */
- rtw_hal_set_mcc_noa_cmd(padapter);
+ /* configure time setting */
+ rtw_hal_set_mcc_time_setting_cmd(padapter);
+#ifndef CONFIG_MCC_MODE_V2
/* IQK value offload */
rtw_hal_set_mcc_IQK_offload_cmd(padapter);
+#endif
/* set mac id to fw */
rtw_hal_set_mcc_macid_cmd(padapter);
- /* set mcc parameter */
- rtw_hal_set_mcc_parameter_cmd(padapter, _FALSE);
+ /* disable tsf auto sync */
+ rtw_hal_set_hwreg(padapter, HW_VAR_TSF_AUTO_SYNC, &enable_tsf_auto_sync);
+
+ /* set mcc parameter */
+ rtw_hal_set_mcc_ctrl_cmd(padapter, _FALSE);
exit:
return ret;
@@ -703,7 +1986,7 @@ static void rtw_hal_set_mcc_stop_setting(PADAPTER padapter, u8 status)
continue;
/* use other interface to set cmd */
if (iface != padapter) {
- rtw_hal_set_mcc_parameter_cmd(iface, _TRUE);
+ rtw_hal_set_mcc_ctrl_cmd(iface, _TRUE);
break;
}
}
@@ -735,8 +2018,12 @@ static void rtw_hal_mcc_status_hdl(PADAPTER padapter, u8 status)
static void rtw_hal_mcc_stop_posthdl(PADAPTER padapter)
{
struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+ struct mcc_obj_priv *mccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
_adapter *iface = NULL;
+ PHAL_DATA_TYPE hal;
+ struct dm_struct *p_dm_odm;
u8 i = 0;
+ u8 enable_rx_bar = _FALSE;
for (i = 0; i < dvobj->iface_nums; i++) {
iface = dvobj->padapters[i];
@@ -747,14 +2034,41 @@ static void rtw_hal_mcc_stop_posthdl(PADAPTER padapter)
iface->mcc_adapterpriv.mcc_tx_bytes_from_kernel = 0;
iface->mcc_adapterpriv.mcc_last_tx_bytes_from_kernel = 0;
iface->mcc_adapterpriv.mcc_tx_bytes_to_port = 0;
+
+ if (iface->mcc_adapterpriv.role == MCC_ROLE_GO)
+ rtw_hal_mcc_remove_go_p2p_ie(iface);
+
+#ifdef CONFIG_TDLS
+ if (MLME_IS_STA(iface)) {
+ if (iface->mcc_adapterpriv.backup_tdls_en) {
+ rtw_enable_tdls_func(iface);
+ RTW_INFO("%s: Disable MCC, Enable TDLS\n", __func__);
+ iface->mcc_adapterpriv.backup_tdls_en = _FALSE;
+ }
+ }
+#endif /* CONFIG_TDLS */
}
+
+ hal = GET_HAL_DATA(padapter);
+ p_dm_odm = &hal->odmpriv;
+ phydm_dm_early_init(p_dm_odm);
+
+ /* force switch channel */
+ hal->current_channel = 0;
+ hal->current_channel_bw = CHANNEL_WIDTH_MAX;
}
static void rtw_hal_mcc_start_posthdl(PADAPTER padapter)
{
struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+ struct mcc_obj_priv *mccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
_adapter *iface = NULL;
+ PHAL_DATA_TYPE hal;
+ struct dm_struct *p_dm_odm;
+ struct _hal_rf_ *p_rf;
+ u32 support_ability = 0;
u8 i = 0;
+ u8 enable_rx_bar = _TRUE;
for (i = 0; i < dvobj->iface_nums; i++) {
iface = dvobj->padapters[i];
@@ -763,7 +2077,23 @@ static void rtw_hal_mcc_start_posthdl(PADAPTER padapter)
iface->mcc_adapterpriv.mcc_tx_bytes_from_kernel = 0;
iface->mcc_adapterpriv.mcc_last_tx_bytes_from_kernel = 0;
iface->mcc_adapterpriv.mcc_tx_bytes_to_port = 0;
+
+#ifdef CONFIG_TDLS
+ if (MLME_IS_STA(iface)) {
+ if (rtw_is_tdls_enabled(iface)) {
+ iface->mcc_adapterpriv.backup_tdls_en = _TRUE;
+ rtw_disable_tdls_func(iface, _TRUE);
+ RTW_INFO("%s: Enable MCC, Disable TDLS\n", __func__);
+ }
+ }
+#endif /* CONFIG_TDLS */
}
+
+ hal = GET_HAL_DATA(padapter);
+ p_dm_odm = &hal->odmpriv;
+ p_rf = &(p_dm_odm->rf_table);
+ mccobjpriv->backup_phydm_ability = p_rf->rf_supportability;
+ p_rf->rf_supportability = p_rf->rf_supportability & (~HAL_RF_TX_PWR_TRACK) & (~HAL_RF_IQK);
}
/*
@@ -785,8 +2115,6 @@ static u8 rtw_hal_set_mcc_setting(PADAPTER padapter, u8 status)
pmccobjpriv->mcc_c2h_status = MCC_RPT_MAX;
if (stop == _FALSE) {
- pmccobjpriv->duration = MCC_DURATION;
-
/* handle mcc start */
if (rtw_hal_set_mcc_start_setting(padapter, status) == _FAIL)
goto exit;
@@ -799,6 +2127,7 @@ static u8 rtw_hal_set_mcc_setting(PADAPTER padapter, u8 status)
if (ret == _SUCCESS) {
RTW_INFO(FUNC_ADPT_FMT": mcc start sucecssfully\n", FUNC_ADPT_ARG(padapter));
+ rtw_hal_mcc_status_hdl(padapter, status);
rtw_hal_mcc_start_posthdl(padapter);
}
} else {
@@ -814,13 +2143,12 @@ static u8 rtw_hal_set_mcc_setting(PADAPTER padapter, u8 status)
RTW_INFO(FUNC_ADPT_FMT": wait for mcc stop C2H time out\n", FUNC_ADPT_ARG(padapter));
else {
ret = _SUCCESS;
+ rtw_hal_mcc_status_hdl(padapter, status);
rtw_hal_mcc_stop_posthdl(padapter);
}
}
exit:
-
- rtw_hal_mcc_status_hdl(padapter, status);
/* clear mcc status */
rtw_hal_clear_mcc_status(padapter
, MCC_STATUS_PROCESS_MCC_START_SETTING | MCC_STATUS_PROCESS_MCC_STOP_SETTING);
@@ -854,7 +2182,7 @@ static void rtw_hal_mcc_check_case_not_limit_traffic(PADAPTER cur_iface, PADAPTE
static void rtw_hal_mcc_sw_ch_fw_notify_hdl(PADAPTER padapter)
{
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
- struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
+ struct mcc_obj_priv *pmccobjpriv = &(pdvobjpriv->mcc_objpriv);
struct mcc_adapter_priv *cur_mccadapriv = NULL, *next_mccadapriv = NULL;
_adapter *iface = NULL, *cur_iface = NULL, *next_iface = NULL;
struct registry_priv *preg = &padapter->registrypriv;
@@ -876,6 +2204,12 @@ static void rtw_hal_mcc_sw_ch_fw_notify_hdl(PADAPTER padapter)
}
}
+ if (cur_iface == NULL || next_iface == NULL) {
+ RTW_ERR("cur_iface=%p,next_iface=%p\n", cur_iface, next_iface);
+ rtw_warn_on(1);
+ return;
+ }
+
/* check other interface tx busy traffic or not under every 2 switch channel notify(Mbits/100ms) */
if (cnt == 2) {
cur_mccadapriv->mcc_tp = (cur_mccadapriv->mcc_tx_bytes_from_kernel
@@ -937,6 +2271,73 @@ static void rtw_hal_mcc_sw_ch_fw_notify_hdl(PADAPTER padapter)
}
}
+static void rtw_hal_mcc_update_noa_start_time_hdl(PADAPTER padapter, u8 buflen, u8 *tmpBuf)
+{
+ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
+ struct mcc_obj_priv *pmccobjpriv = &(pdvobjpriv->mcc_objpriv);
+ struct mcc_adapter_priv *pmccadapriv = NULL;
+ PADAPTER iface = NULL;
+ u8 i = 0;
+ u8 policy_idx = pmccobjpriv->policy_index;
+ u8 noa_tsf_sync_offset = mcc_switch_channel_policy_table[policy_idx][MCC_TSF_SYNC_OFFSET_IDX];
+ u8 noa_start_time_offset = mcc_switch_channel_policy_table[policy_idx][MCC_START_TIME_OFFSET_IDX];
+
+ for (i = 0; i < pdvobjpriv->iface_nums; i++) {
+ iface = pdvobjpriv->padapters[i];
+ if (iface == NULL)
+ continue;
+
+ pmccadapriv = &iface->mcc_adapterpriv;
+ /* GO & channel match */
+ if (pmccadapriv->role == MCC_ROLE_GO) {
+ /* convert GO TBTT from FW to noa_start_time(TU convert to mircosecond) */
+ pmccadapriv->noa_start_time = RTW_GET_LE32(tmpBuf + 2) + noa_start_time_offset * TU;
+
+ if (0) {
+ RTW_INFO("TBTT:0x%02x\n", RTW_GET_LE32(tmpBuf + 2));
+ RTW_INFO("noa_tsf_sync_offset:%d, noa_start_time_offset:%d\n", noa_tsf_sync_offset, noa_start_time_offset);
+ RTW_INFO(FUNC_ADPT_FMT"buf=0x%02x:0x%02x:0x%02x:0x%02x, noa_start_time=0x%02x\n"
+ , FUNC_ADPT_ARG(iface)
+ , tmpBuf[2]
+ , tmpBuf[3]
+ , tmpBuf[4]
+ , tmpBuf[5]
+ ,pmccadapriv->noa_start_time);
+ }
+
+ rtw_hal_mcc_update_go_p2p_ie(iface);
+
+ break;
+ }
+ }
+
+}
+
+static void rtw_hal_mcc_rpt_tsf_hdl(PADAPTER padapter, u8 buflen, u8 *tmpBuf)
+{
+ struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
+ struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
+ struct submit_ctx *mcc_tsf_req_sctx = &pmccobjpriv->mcc_tsf_req_sctx;
+ struct mcc_adapter_priv *pmccadapriv = NULL;
+ u8 iface_num = pdvobjpriv->iface_nums;
+ static u8 order = 0;
+
+ pmccadapriv = &pmccobjpriv->iface[order]->mcc_adapterpriv;
+ pmccadapriv->tsf = RTW_GET_LE64(tmpBuf + 2);
+
+
+ if (0) {
+ RTW_INFO("TSF(order:%d):%llu\n", pmccadapriv->order, pmccadapriv->tsf);
+ }
+
+ if (pmccadapriv->order == (iface_num - 1)) {
+ rtw_sctx_done(&mcc_tsf_req_sctx);
+ order = 0;
+ } else
+ order ++;
+
+}
+
/**
* rtw_hal_mcc_c2h_handler - mcc c2h handler
*/
@@ -946,6 +2347,8 @@ void rtw_hal_mcc_c2h_handler(PADAPTER padapter, u8 buflen, u8 *tmpBuf)
struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
struct submit_ctx *mcc_sctx = &pmccobjpriv->mcc_sctx;
+ _adapter *cur_adapter = NULL;
+ u8 cur_ch = 0, cur_bw = 0, cur_ch_offset = 0;
_irqL irqL;
/* RTW_INFO("[length]=%d, [C2H data]="MAC_FMT"\n", buflen, MAC_ARG(tmpBuf)); */
@@ -956,19 +2359,32 @@ void rtw_hal_mcc_c2h_handler(PADAPTER padapter, u8 buflen, u8 *tmpBuf)
}
pmccobjpriv->mcc_c2h_status = tmpBuf[0];
+ pmccobjpriv->current_order = tmpBuf[1];
+ cur_adapter = pmccobjpriv->iface[pmccobjpriv->current_order];
+ cur_ch = cur_adapter->mlmeextpriv.cur_channel;
+ cur_bw = cur_adapter->mlmeextpriv.cur_bwmode;
+ cur_ch_offset = cur_adapter->mlmeextpriv.cur_ch_offset;
+ rtw_set_oper_ch(cur_adapter, cur_ch);
+ rtw_set_oper_bw(cur_adapter, cur_bw);
+ rtw_set_oper_choffset(cur_adapter, cur_ch_offset);
+
+ if (0)
+ RTW_INFO("%d,order:%d,TSF:0x%llx\n", tmpBuf[0], tmpBuf[1], RTW_GET_LE64(tmpBuf + 2));
+
switch (pmccobjpriv->mcc_c2h_status) {
case MCC_RPT_SUCCESS:
- pdvobjpriv->oper_channel = tmpBuf[1];
_enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
pmccobjpriv->cur_mcc_success_cnt++;
+ rtw_hal_mcc_upadate_chnl_bw(cur_adapter, cur_ch, cur_ch_offset, cur_bw, _FALSE);
_exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
break;
case MCC_RPT_TXNULL_FAIL:
RTW_INFO("[MCC] TXNULL FAIL\n");
break;
case MCC_RPT_STOPMCC:
- RTW_INFO("[MCC] MCC stop (time:%d)\n", rtw_get_current_time());
+ RTW_INFO("[MCC] MCC stop\n");
pmccobjpriv->mcc_c2h_status = MCC_RPT_STOPMCC;
+ rtw_hal_mcc_upadate_chnl_bw(cur_adapter, cur_ch, cur_ch_offset, cur_bw, _TRUE);
rtw_sctx_done(&mcc_sctx);
break;
case MCC_RPT_READY:
@@ -985,15 +2401,103 @@ void rtw_hal_mcc_c2h_handler(PADAPTER padapter, u8 buflen, u8 *tmpBuf)
rtw_sctx_done(&mcc_sctx);
break;
case MCC_RPT_SWICH_CHANNEL_NOTIFY:
- pdvobjpriv->oper_channel = tmpBuf[1];
rtw_hal_mcc_sw_ch_fw_notify_hdl(padapter);
break;
+ case MCC_RPT_UPDATE_NOA_START_TIME:
+ rtw_hal_mcc_update_noa_start_time_hdl(padapter, buflen, tmpBuf);
+ break;
+ case MCC_RPT_TSF:
+ _enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
+ rtw_hal_mcc_rpt_tsf_hdl(padapter, buflen, tmpBuf);
+ _exit_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
+ break;
default:
/* RTW_INFO("[MCC] Other MCC status(%d)\n", pmccobjpriv->mcc_c2h_status); */
break;
}
}
+void rtw_hal_mcc_update_parameter(PADAPTER padapter, u8 force_update)
+{
+ struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+ struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
+ u8 cmd[H2C_MCC_TIME_SETTING_LEN] = {0};
+ u8 swchannel_early_time = MCC_SWCH_FW_EARLY_TIME;
+
+ rtw_mi_status(padapter, &mcc_mstate);
+
+ if (MSTATE_AP_NUM(&mcc_mstate) == 0) {
+ u8 need_update = _FALSE;
+ u8 start_time_offset = 0, interval = 0, duration = 0;
+
+ need_update = rtw_hal_mcc_update_timing_parameters(padapter, force_update);
+
+ if (need_update == _FALSE)
+ return;
+
+ start_time_offset = pmccobjpriv->start_time;
+ interval = pmccobjpriv->interval;
+ duration = pmccobjpriv->iface[0]->mcc_adapterpriv.mcc_duration;
+
+ SET_H2CCMD_MCC_TIME_SETTING_START_TIME(cmd, start_time_offset);
+ SET_H2CCMD_MCC_TIME_SETTING_INTERVAL(cmd, interval);
+ SET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(cmd, swchannel_early_time);
+ SET_H2CCMD_MCC_TIME_SETTING_UPDATE(cmd, _TRUE);
+ SET_H2CCMD_MCC_TIME_SETTING_ORDER0_DURATION(cmd, duration);
+ } else {
+ u8 policy_idx = pmccobjpriv->policy_index;
+ u8 duration = mcc_switch_channel_policy_table[policy_idx][MCC_DURATION_IDX];
+ u8 tsf_sync_offset = mcc_switch_channel_policy_table[policy_idx][MCC_TSF_SYNC_OFFSET_IDX];
+ u8 start_time_offset = mcc_switch_channel_policy_table[policy_idx][MCC_START_TIME_OFFSET_IDX];
+ u8 interval = mcc_switch_channel_policy_table[policy_idx][MCC_INTERVAL_IDX];
+ u8 guard_offset0 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET0_IDX];
+ u8 guard_offset1 = mcc_switch_channel_policy_table[policy_idx][MCC_GUARD_OFFSET1_IDX];
+ u8 order0_duration = 0;
+ u8 i = 0;
+
+ RTW_INFO("%s: policy_idx=%d\n", __func__, policy_idx);
+
+ /* GO/AP is order 0, GC/STA is order 1 */
+ order0_duration = pmccobjpriv->iface[0]->mcc_adapterpriv.mcc_duration = interval - duration;
+ pmccobjpriv->iface[1]->mcc_adapterpriv.mcc_duration = duration;
+
+ /* update IE */
+ for (i = 0; i < dvobj->iface_nums; i++) {
+ PADAPTER iface = NULL;
+ struct mcc_adapter_priv *mccadapriv = NULL;
+
+ iface = dvobj->padapters[i];
+ if (iface == NULL)
+ continue;
+
+ mccadapriv = &iface->mcc_adapterpriv;
+ if (mccadapriv == NULL)
+ continue;
+
+ if (mccadapriv->role == MCC_ROLE_GO)
+ rtw_hal_mcc_update_go_p2p_ie(iface);
+ }
+
+ /* update H2C cmd */
+ /* FW set enable */
+ SET_H2CCMD_MCC_TIME_SETTING_FW_EN(cmd, _TRUE);
+ /* TSF Sync offset */
+ SET_H2CCMD_MCC_TIME_SETTING_TSF_SYNC_OFFSET(cmd, tsf_sync_offset);
+ /* start time offset */
+ SET_H2CCMD_MCC_TIME_SETTING_START_TIME(cmd, (start_time_offset + guard_offset0));
+ /* interval */
+ SET_H2CCMD_MCC_TIME_SETTING_INTERVAL(cmd, interval);
+ /* Early time to inform driver by C2H before switch channel */
+ SET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(cmd, swchannel_early_time);
+ /* Port0 sync from Port1, not support multi-port */
+ SET_H2CCMD_MCC_TIME_SETTING_ORDER_BASE(cmd, HW_PORT1);
+ SET_H2CCMD_MCC_TIME_SETTING_ORDER_SYNC(cmd, HW_PORT0);
+ SET_H2CCMD_MCC_TIME_SETTING_UPDATE(cmd, _TRUE);
+ SET_H2CCMD_MCC_TIME_SETTING_ORDER0_DURATION(cmd, order0_duration);
+ }
+
+ rtw_hal_fill_h2c_cmd(padapter, H2C_MCC_TIME_SETTING, H2C_MCC_TIME_SETTING_LEN, cmd);
+}
/**
* rtw_hal_mcc_sw_status_check - check mcc swich channel status
@@ -1004,18 +2508,38 @@ void rtw_hal_mcc_sw_status_check(PADAPTER padapter)
struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
- u8 cur_cnt = 0, prev_cnt = 0, diff_cnt = 0, check_ret = _FAIL;
+ _adapter *iface = NULL;
+ u8 cur_cnt = 0, prev_cnt = 0, diff_cnt = 0, check_ret = _FAIL, threshold = 0;
+ u8 policy_idx = pmccobjpriv->policy_index;
+ u8 noa_enable = _FALSE;
+ u8 i = 0;
_irqL irqL;
- /* #define MCC_RESTART 1 */
+/* #define MCC_RESTART 1 */
if (!MCC_EN(padapter))
return;
+ rtw_mi_status(padapter, &mcc_mstate);
+
_enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
+ /* check noa enable or not */
+ for (i = 0; i < dvobj->iface_nums; i++) {
+ iface = dvobj->padapters[i];
+ if (iface->wdinfo.p2p_ps_mode == P2P_PS_NOA) {
+ noa_enable = _TRUE;
+ break;
+ }
+ }
+
+ if (!noa_enable && MSTATE_AP_NUM(&mcc_mstate) == 0)
+ rtw_hal_mcc_update_parameter(padapter, _FALSE);
+
+ threshold = pmccobjpriv->mcc_stop_threshold;
+
if (pwrpriv->pwr_mode != PS_MODE_ACTIVE) {
rtw_warn_on(1);
RTW_INFO("PS mode is not active under mcc, force exit ps mode\n");
@@ -1032,7 +2556,7 @@ void rtw_hal_mcc_sw_status_check(PADAPTER padapter)
else
diff_cnt = cur_cnt - prev_cnt;
- if (diff_cnt < 30) {
+ if (diff_cnt < threshold) {
pmccobjpriv->mcc_tolerance_time--;
RTW_INFO("%s: diff_cnt:%d, tolerance_time:%d\n",
__func__, diff_cnt, pmccobjpriv->mcc_tolerance_time);
@@ -1049,10 +2573,10 @@ void rtw_hal_mcc_sw_status_check(PADAPTER padapter)
if (check_ret != _SUCCESS) {
RTW_INFO("============ MCC swich channel check fail (%d)=============\n", diff_cnt);
/* restart MCC */
-#ifdef MCC_RESTART
- rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_STOP_DISCONNECT);
- rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_CONNECT);
-#endif /* MCC_RESTART */
+ #ifdef MCC_RESTART
+ rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_STOP_DISCONNECT);
+ rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_CONNECT);
+ #endif /* MCC_RESTART */
}
} else {
_enter_critical_bh(&pmccobjpriv->mcc_lock, &irqL);
@@ -1090,7 +2614,7 @@ u8 rtw_hal_mcc_change_scan_flag(PADAPTER padapter, u8 *ch, u8 *bw, u8 *offset)
for (i = 0; i < dvobj->iface_nums; i++) {
if (!dvobj->padapters[i])
- continue;
+ continue;
pmlmeext = &dvobj->padapters[i]->mlmeextpriv;
pmccadapriv = &dvobj->padapters[i]->mcc_adapterpriv;
@@ -1106,6 +2630,12 @@ u8 rtw_hal_mcc_change_scan_flag(PADAPTER padapter, u8 *ch, u8 *bw, u8 *offset)
break;
case MCC_ROLE_STA:
case MCC_ROLE_GC:
+ if (dvobj->padapters[i] != padapter) {
+ *ch = pmlmeext->cur_channel;
+ *bw = pmlmeext->cur_bwmode;
+ *offset = pmlmeext->cur_ch_offset;
+ need_ch_setting_union = _FALSE;
+ }
break;
default:
RTW_INFO("unknown role\n");
@@ -1158,12 +2688,13 @@ inline void rtw_hal_mcc_calc_tx_bytes_to_port(PADAPTER padapter, u32 len)
struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
- if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
+ if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
pmccadapriv->mcc_tx_bytes_to_port += len;
- if (0)
- RTW_INFO("%s(order:%d): mcc tx bytes to port:%d, mcc target tx bytes to port:%d\n"
- , __func__, pmccadapriv->order, pmccadapriv->mcc_tx_bytes_to_port
- , pmccadapriv->mcc_target_tx_bytes_to_port);
+ if (0)
+ RTW_INFO("%s(order:%d): mcc tx bytes to port:%d, mcc target tx bytes to port:%d\n"
+ , __func__, pmccadapriv->order, pmccadapriv->mcc_tx_bytes_to_port
+ , pmccadapriv->mcc_target_tx_bytes_to_port);
+ }
}
}
@@ -1191,6 +2722,37 @@ inline u8 rtw_hal_mcc_stop_tx_bytes_to_port(PADAPTER padapter)
return _FALSE;
}
+static void rtw_hal_mcc_assign_scan_flag(PADAPTER padapter, u8 scan_done)
+{
+ struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+ _adapter *iface = NULL;
+ struct mlme_ext_priv *pmlmeext = NULL;
+ u8 i = 0, flags;
+
+ if (!MCC_EN(padapter))
+ return;
+
+ for (i = 0; i < dvobj->iface_nums; i++) {
+ iface = dvobj->padapters[i];
+ pmlmeext = &iface->mlmeextpriv;
+ if (is_client_associated_to_ap(iface)) {
+ flags = mlmeext_scan_backop_flags_sta(pmlmeext);
+ if (scan_done) {
+ if (mlmeext_chk_scan_backop_flags_sta(pmlmeext, SS_BACKOP_EN)) {
+ flags &= ~SS_BACKOP_EN;
+ mlmeext_assign_scan_backop_flags_sta(pmlmeext, flags);
+ }
+ } else {
+ if (!mlmeext_chk_scan_backop_flags_sta(pmlmeext, SS_BACKOP_EN)) {
+ flags |= SS_BACKOP_EN;
+ mlmeext_assign_scan_backop_flags_sta(pmlmeext, flags);
+ }
+ }
+
+ }
+ }
+}
+
/**
* rtw_hal_set_mcc_setting_scan_start - setting mcc under scan start
* @padapter: the adapter to be setted
@@ -1207,8 +2769,7 @@ u8 rtw_hal_set_mcc_setting_scan_start(PADAPTER padapter)
if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) {
if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC)) {
ret = rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_STOP_SCAN_START);
- /* issue null data to all station connected to AP before scan */
- rtw_hal_mcc_issue_null_data(padapter, 0, 1);
+ rtw_hal_mcc_assign_scan_flag(padapter, 0);
}
}
_exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
@@ -1231,9 +2792,10 @@ u8 rtw_hal_set_mcc_setting_scan_complete(PADAPTER padapter)
_enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
- if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC))
- ret = rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_SCAN_DONE);
-
+ if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_NEED_MCC)) {
+ rtw_hal_mcc_assign_scan_flag(padapter, 1);
+ ret = rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_SCAN_DONE);
+ }
_exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
}
@@ -1253,14 +2815,14 @@ u8 rtw_hal_set_mcc_setting_start_bss_network(PADAPTER padapter, u8 chbw_allow)
if (MCC_EN(padapter)) {
/* channel bw offset can not be allowed, start MCC */
if (chbw_allow == _FALSE) {
- struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
+ struct mcc_obj_priv *pmccobjpriv = &(adapter_to_dvobj(padapter)->mcc_objpriv);
- rtw_hal_mcc_backup_IQK_val(padapter);
- _enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
- ret = rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_CONNECT);
- _exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
+ rtw_hal_mcc_restore_iqk_val(padapter);
+ _enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
+ ret = rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_CONNECT);
+ _exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
+ }
}
- }
return ret;
}
@@ -1296,11 +2858,11 @@ u8 rtw_hal_set_mcc_setting_join_done_chk_ch(PADAPTER padapter)
u8 ret = _FAIL;
if (MCC_EN(padapter)) {
- u8 sta_num = 0, ld_sta_num = 0, lg_sta_num = 0, ap_num = 0, ld_ap_num = 0;
+ struct mi_state mstate;
- rtw_mi_status_no_self(padapter, &sta_num, &ld_sta_num, &lg_sta_num, &ap_num, &ld_ap_num, NULL);
+ rtw_mi_status_no_self(padapter, &mstate);
- if (ld_sta_num || lg_sta_num || ap_num) {
+ if (MSTATE_STA_LD_NUM(&mstate) || MSTATE_STA_LG_NUM(&mstate) || MSTATE_AP_NUM(&mstate)) {
bool chbw_allow = _TRUE;
u8 u_ch, u_offset, u_bw;
struct mlme_ext_priv *cur_mlmeext = &padapter->mlmeextpriv;
@@ -1310,28 +2872,29 @@ u8 rtw_hal_set_mcc_setting_join_done_chk_ch(PADAPTER padapter)
dump_adapters_status(RTW_DBGDUMP , dvobj);
rtw_warn_on(1);
}
+
RTW_INFO(FUNC_ADPT_FMT" union no self: %u,%u,%u\n"
, FUNC_ADPT_ARG(padapter), u_ch, u_bw, u_offset);
/* chbw_allow? */
chbw_allow = rtw_is_chbw_grouped(cur_mlmeext->cur_channel
, cur_mlmeext->cur_bwmode, cur_mlmeext->cur_ch_offset
- , u_ch, u_bw, u_offset);
+ , u_ch, u_bw, u_offset);
RTW_INFO(FUNC_ADPT_FMT" chbw_allow:%d\n"
- , FUNC_ADPT_ARG(padapter), chbw_allow);
+ , FUNC_ADPT_ARG(padapter), chbw_allow);
/* if chbw_allow = false, start MCC setting */
if (chbw_allow == _FALSE) {
struct mcc_obj_priv *pmccobjpriv = &dvobj->mcc_objpriv;
- rtw_hal_mcc_backup_IQK_val(padapter);
+ rtw_hal_mcc_restore_iqk_val(padapter);
_enter_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
ret = rtw_hal_set_mcc_setting(padapter, MCC_SETCMD_STATUS_START_CONNECT);
_exit_critical_mutex(&pmccobjpriv->mcc_mutex, NULL);
- }
}
}
+ }
return ret;
}
@@ -1348,19 +2911,22 @@ u8 rtw_hal_set_mcc_setting_chk_start_clnt_join(PADAPTER padapter, u8 *ch, u8 *bw
{
u8 ret = _FAIL;
- /* if chbw_allow = false under en_mcc = TRUE, we do not change channel related setting */
+ /* if chbw_allow = false under en_mcc = TRUE, we do not change channel related setting */
if (MCC_EN(padapter)) {
/* restore union channel related setting to current channel related setting */
if (chbw_allow == _FALSE) {
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
+ /* issue null data to other interface connected to AP */
+ rtw_hal_mcc_issue_null_data(padapter, chbw_allow, _TRUE);
+
*ch = pmlmeext->cur_channel;
*bw = pmlmeext->cur_bwmode;
*offset = pmlmeext->cur_ch_offset;
RTW_INFO(FUNC_ADPT_FMT" en_mcc:%d(%d,%d,%d,)\n"
- , FUNC_ADPT_ARG(padapter), padapter->registrypriv.en_mcc
- , *ch, *bw, *offset);
+ , FUNC_ADPT_ARG(padapter), MCC_EN(padapter)
+ , *ch, *bw, *offset);
ret = _SUCCESS;
}
}
@@ -1368,6 +2934,23 @@ u8 rtw_hal_set_mcc_setting_chk_start_clnt_join(PADAPTER padapter, u8 *ch, u8 *bw
return ret;
}
+static void rtw_hal_mcc_dump_noa_content(void *sel, PADAPTER padapter)
+{
+ struct mcc_adapter_priv *pmccadapriv = NULL;
+ u8 *pos = NULL;
+ pmccadapriv = &padapter->mcc_adapterpriv;
+ /* last position for NoA attribute */
+ pos = pmccadapriv->p2p_go_noa_ie + pmccadapriv->p2p_go_noa_ie_len;
+
+
+ RTW_PRINT_SEL(sel, "\nStart to dump NoA Content\n");
+ RTW_PRINT_SEL(sel, "NoA Counts:%d\n", *(pos - 13));
+ RTW_PRINT_SEL(sel, "NoA Duration(TU):%d\n", (RTW_GET_LE32(pos - 12))/TU);
+ RTW_PRINT_SEL(sel, "NoA Interval(TU):%d\n", (RTW_GET_LE32(pos - 8))/TU);
+ RTW_PRINT_SEL(sel, "NoA Start time(microseconds):0x%02x\n", RTW_GET_LE32(pos - 4));
+ RTW_PRINT_SEL(sel, "End to dump NoA Content\n");
+}
+
void rtw_hal_dump_mcc_info(void *sel, struct dvobj_priv *dvobj)
{
struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
@@ -1377,9 +2960,13 @@ void rtw_hal_dump_mcc_info(void *sel, struct dvobj_priv *dvobj)
u8 i = 0;
/* regpriv is common for all adapter */
- adapter = dvobj->padapters[IFACE_ID0];
+ adapter = dvobj_get_primary_adapter(dvobj);
RTW_PRINT_SEL(sel, "**********************************************\n");
+ RTW_PRINT_SEL(sel, "en_mcc:%d\n", MCC_EN(adapter));
+ RTW_PRINT_SEL(sel, "primary adapter("ADPT_FMT") duration:%d%c\n",
+ ADPT_ARG(dvobj_get_primary_adapter(dvobj)), pmccobjpriv->duration, 37);
+ RTW_PRINT_SEL(sel, "runtime duration:%s\n", pmccobjpriv->enable_runtime_duration ? "enable":"disable");
for (i = 0; i < dvobj->iface_nums; i++) {
iface = dvobj->padapters[i];
if (!iface)
@@ -1388,6 +2975,8 @@ void rtw_hal_dump_mcc_info(void *sel, struct dvobj_priv *dvobj)
regpriv = &iface->registrypriv;
pmccadapriv = &iface->mcc_adapterpriv;
if (pmccadapriv) {
+ u8 p2p_ps_mode = iface->wdinfo.p2p_ps_mode;
+
RTW_PRINT_SEL(sel, "adapter mcc info:\n");
RTW_PRINT_SEL(sel, "ifname:%s\n", ADPT_ARG(iface));
RTW_PRINT_SEL(sel, "order:%d\n", pmccadapriv->order);
@@ -1395,9 +2984,9 @@ void rtw_hal_dump_mcc_info(void *sel, struct dvobj_priv *dvobj)
RTW_PRINT_SEL(sel, "target tx bytes:%d\n", pmccadapriv->mcc_target_tx_bytes_to_port);
RTW_PRINT_SEL(sel, "current TP:%d\n", pmccadapriv->mcc_tp);
RTW_PRINT_SEL(sel, "mgmt queue macid:%d\n", pmccadapriv->mgmt_queue_macid);
- RTW_PRINT_SEL(sel, "macid bitmap:0x%02x\n\n", pmccadapriv->mcc_macid_bitmap);
+ RTW_PRINT_SEL(sel, "macid bitmap:0x%02x\n", pmccadapriv->mcc_macid_bitmap);
+ RTW_PRINT_SEL(sel, "P2P NoA:%s\n\n", p2p_ps_mode == P2P_PS_NOA ? "enable":"disable");
RTW_PRINT_SEL(sel, "registry data:\n");
- RTW_PRINT_SEL(sel, "en_mcc:%d\n", regpriv->en_mcc);
RTW_PRINT_SEL(sel, "ap target tx TP(BW:20M):%d Mbps\n", regpriv->rtw_mcc_ap_bw20_target_tx_tp);
RTW_PRINT_SEL(sel, "ap target tx TP(BW:40M):%d Mbps\n", regpriv->rtw_mcc_ap_bw40_target_tx_tp);
RTW_PRINT_SEL(sel, "ap target tx TP(BW:80M):%d Mbps\n", regpriv->rtw_mcc_ap_bw80_target_tx_tp);
@@ -1405,10 +2994,14 @@ void rtw_hal_dump_mcc_info(void *sel, struct dvobj_priv *dvobj)
RTW_PRINT_SEL(sel, "sta target tx TP(BW:40M ):%d Mbps\n", regpriv->rtw_mcc_sta_bw40_target_tx_tp);
RTW_PRINT_SEL(sel, "sta target tx TP(BW:80M):%d Mbps\n", regpriv->rtw_mcc_sta_bw80_target_tx_tp);
RTW_PRINT_SEL(sel, "single tx criteria:%d Mbps\n", regpriv->rtw_mcc_single_tx_cri);
+ if (MLME_IS_GO(iface))
+ rtw_hal_mcc_dump_noa_content(sel, iface);
RTW_PRINT_SEL(sel, "**********************************************\n");
}
}
RTW_PRINT_SEL(sel, "------------------------------------------\n");
+ RTW_PRINT_SEL(sel, "policy index:%d\n", pmccobjpriv->policy_index);
+ RTW_PRINT_SEL(sel, "------------------------------------------\n");
RTW_PRINT_SEL(sel, "define data:\n");
RTW_PRINT_SEL(sel, "ap target tx TP(BW:20M):%d Mbps\n", MCC_AP_BW20_TARGET_TX_TP);
RTW_PRINT_SEL(sel, "ap target tx TP(BW:40M):%d Mbps\n", MCC_AP_BW40_TARGET_TX_TP);
@@ -1446,9 +3039,9 @@ inline u8 rtw_hal_mcc_link_status_chk(_adapter *padapter, const char *msg)
iface = dvobj->padapters[i];
mlmeext = &iface->mlmeextpriv;
if (mlmeext_scan_state(mlmeext) != SCAN_DISABLE) {
-#ifdef DBG_EXPIRATION_CHK
- RTW_INFO(FUNC_ADPT_FMT" don't enter %s under scan for MCC mode\n", FUNC_ADPT_ARG(padapter), msg);
-#endif
+ #ifdef DBG_EXPIRATION_CHK
+ RTW_INFO(FUNC_ADPT_FMT" don't enter %s under scan for MCC mode\n", FUNC_ADPT_ARG(padapter), msg);
+ #endif
ret = _FALSE;
goto exit;
}
@@ -1464,27 +3057,253 @@ void rtw_hal_mcc_issue_null_data(_adapter *padapter, u8 chbw_allow, u8 ps_mode)
{
struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
_adapter *iface = NULL;
- u32 start = rtw_get_current_time();
+ systime start = rtw_get_current_time();
u8 i = 0;
- if (MCC_EN(padapter)) {
- if (chbw_allow == _FALSE) {
- for (i = 0; i < dvobj->iface_nums; i++) {
- iface = dvobj->padapters[i];
- /* issue null data to inform ap station will leave */
- if (is_client_associated_to_ap(iface)) {
- struct mlme_ext_priv *mlmeext = &iface->mlmeextpriv;
- u8 ch = mlmeext->cur_channel;
- u8 bw = mlmeext->cur_bwmode;
- u8 offset = mlmeext->cur_ch_offset;
-
- set_channel_bwmode(iface, ch, bw, offset);
- issue_nulldata(iface, NULL, ps_mode, 3, 50);
- }
- }
- RTW_INFO("%s(%d ms)\n", __func__, rtw_get_passing_time_ms(start));
+ if (!MCC_EN(padapter))
+ return;
+
+ if (rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
+ return;
+
+ if (chbw_allow == _TRUE)
+ return;
+
+ for (i = 0; i < dvobj->iface_nums; i++) {
+ iface = dvobj->padapters[i];
+ /* issue null data to inform ap station will leave */
+ if (is_client_associated_to_ap(iface)) {
+ struct mlme_ext_priv *mlmeext = &iface->mlmeextpriv;
+ struct mlme_ext_info *mlmeextinfo = &mlmeext->mlmext_info;
+ u8 ch = mlmeext->cur_channel;
+ u8 bw = mlmeext->cur_bwmode;
+ u8 offset = mlmeext->cur_ch_offset;
+ struct sta_info *sta = rtw_get_stainfo(&iface->stapriv, get_my_bssid(&(mlmeextinfo->network)));
+
+ if (!sta)
+ continue;
+
+ set_channel_bwmode(iface, ch, offset, bw);
+
+ if (ps_mode)
+ rtw_hal_macid_sleep(iface, sta->cmn.mac_id);
+ else
+ rtw_hal_macid_wakeup(iface, sta->cmn.mac_id);
+
+ issue_nulldata(iface, NULL, ps_mode, 3, 50);
+ }
+ }
+ RTW_INFO("%s(%d ms)\n", __func__, rtw_get_passing_time_ms(start));
+}
+
+u8 *rtw_hal_mcc_append_go_p2p_ie(PADAPTER padapter, u8 *pframe, u32 *len)
+{
+ struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
+
+ if (!MCC_EN(padapter))
+ return pframe;
+
+ if (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
+ return pframe;
+
+ if (pmccadapriv->p2p_go_noa_ie_len == 0)
+ return pframe;
+
+ _rtw_memcpy(pframe, pmccadapriv->p2p_go_noa_ie, pmccadapriv->p2p_go_noa_ie_len);
+ *len = *len + pmccadapriv->p2p_go_noa_ie_len;
+
+ return pframe + pmccadapriv->p2p_go_noa_ie_len;
+}
+
+void rtw_hal_dump_mcc_policy_table(void *sel)
+{
+ u8 idx = 0;
+ RTW_PRINT_SEL(sel, "duration\t,tsf sync offset\t,start time offset\t,interval\t,guard offset0\t,guard offset1\n");
+
+ for (idx = 0; idx < mcc_max_policy_num; idx ++) {
+ RTW_PRINT_SEL(sel, "%d\t\t,%d\t\t\t,%d\t\t\t,%d\t\t,%d\t\t,%d\n"
+ , mcc_switch_channel_policy_table[idx][MCC_DURATION_IDX]
+ , mcc_switch_channel_policy_table[idx][MCC_TSF_SYNC_OFFSET_IDX]
+ , mcc_switch_channel_policy_table[idx][MCC_START_TIME_OFFSET_IDX]
+ , mcc_switch_channel_policy_table[idx][MCC_INTERVAL_IDX]
+ , mcc_switch_channel_policy_table[idx][MCC_GUARD_OFFSET0_IDX]
+ , mcc_switch_channel_policy_table[idx][MCC_GUARD_OFFSET1_IDX]);
+ }
+}
+
+void rtw_hal_mcc_update_macid_bitmap(PADAPTER padapter, int mac_id, u8 add)
+{
+ struct mcc_adapter_priv *pmccadapriv = &padapter->mcc_adapterpriv;
+
+ if (!MCC_EN(padapter))
+ return;
+
+ if (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
+ return;
+
+ if (pmccadapriv->role == MCC_ROLE_GC || pmccadapriv->role == MCC_ROLE_STA)
+ return;
+
+ if (mac_id < 0) {
+ RTW_WARN("%s: mac_id < 0(%d)\n", __func__, mac_id);
+ return;
+ }
+
+ RTW_INFO(ADPT_FMT" %s macid=%d, ori mcc_macid_bitmap=0x%08x\n"
+ , ADPT_ARG(padapter), add ? "add" : "clear"
+ , mac_id, pmccadapriv->mcc_macid_bitmap);
+
+ if (add)
+ pmccadapriv->mcc_macid_bitmap |= BIT(mac_id);
+ else
+ pmccadapriv->mcc_macid_bitmap &= ~(BIT(mac_id));
+
+ rtw_hal_set_mcc_macid_cmd(padapter);
+}
+
+void rtw_hal_mcc_process_noa(PADAPTER padapter)
+{
+ struct wifidirect_info *pwdinfo = &(padapter->wdinfo);
+ struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
+ struct mcc_obj_priv *pmccobjpriv = &(dvobj->mcc_objpriv);
+
+ if (!MCC_EN(padapter))
+ return;
+
+ if (!rtw_hal_check_mcc_status(padapter, MCC_STATUS_DOING_MCC))
+ return;
+
+ if (!MLME_IS_GC(padapter))
+ return;
+
+ switch(pwdinfo->p2p_ps_mode) {
+ case P2P_PS_NONE:
+ RTW_INFO("[MCC] Disable NoA under MCC\n");
+ rtw_hal_mcc_update_parameter(padapter, _TRUE);
+ break;
+ case P2P_PS_NOA:
+ RTW_INFO("[MCC] Enable NoA under MCC\n");
+ break;
+ default:
+ break;
+
+ }
+}
+
+void rtw_hal_mcc_parameter_init(PADAPTER padapter)
+{
+ if (!padapter->registrypriv.en_mcc)
+ return;
+
+ if (is_primary_adapter(padapter)) {
+ SET_MCC_EN_FLAG(padapter, padapter->registrypriv.en_mcc);
+ SET_MCC_DURATION(padapter, padapter->registrypriv.rtw_mcc_duration);
+ SET_MCC_RUNTIME_DURATION(padapter, padapter->registrypriv.rtw_mcc_enable_runtime_duration);
+ }
+}
+
+
+u8 rtw_set_mcc_duration_hdl(PADAPTER adapter, u8 type, const u8 *val)
+{
+ struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+ struct mcc_obj_priv *mccobjpriv = &(dvobj->mcc_objpriv);
+ _adapter *iface = NULL;
+ u8 duration = 50;
+ u8 ret = _SUCCESS, noa_enable = _FALSE, i = 0;
+
+ if (!mccobjpriv->enable_runtime_duration)
+ goto exit;
+
+#ifdef CONFIG_P2P_PS
+ /* check noa enable or not */
+ for (i = 0; i < dvobj->iface_nums; i++) {
+ iface = dvobj->padapters[i];
+ if (iface->wdinfo.p2p_ps_mode == P2P_PS_NOA) {
+ noa_enable = _TRUE;
+ break;
+ }
+ }
+#endif /* CONFIG_P2P_PS */
+
+
+
+ if (type == MCC_DURATION_MAPPING) {
+ switch (*val) {
+ /* 0 = fair scheduling */
+ case 0:
+ mccobjpriv->duration= 40;
+ mccobjpriv->policy_index = 2;
+ mccobjpriv->mchan_sched_mode = MCC_FAIR_SCHEDULE;
+ break;
+ /* 1 = favor STA */
+ case 1:
+ mccobjpriv->duration= 70;
+ mccobjpriv->policy_index = 1;
+ mccobjpriv->mchan_sched_mode = MCC_FAVOE_STA;
+ break;
+ /* 2 = favor P2P*/
+ case 2:
+ default:
+ mccobjpriv->duration= 30;
+ mccobjpriv->policy_index = 0;
+ mccobjpriv->mchan_sched_mode = MCC_FAVOE_P2P;
+ break;
}
+ } else {
+ mccobjpriv->duration = *val;
+ rtw_hal_mcc_update_policy_table(adapter);
+ }
+
+ /* only update sw parameter under MCC
+ it will be force update during */
+ if (noa_enable)
+ goto exit;
+
+ if (rtw_hal_check_mcc_status(adapter, MCC_STATUS_DOING_MCC))
+ rtw_hal_mcc_update_parameter(adapter, _TRUE);
+exit:
+ return ret;
+}
+
+u8 rtw_set_mcc_duration_cmd(_adapter *adapter, u8 type, u8 val)
+{
+ struct cmd_obj *cmdobj;
+ struct drvextra_cmd_parm *pdrvextra_cmd_parm;
+ struct cmd_priv *pcmdpriv = &adapter->cmdpriv;
+ u8 *mcc_duration = NULL;
+ u8 res = _FAIL;
+
+
+ cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
+ if (cmdobj == NULL)
+ goto exit;
+
+ pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
+ if (pdrvextra_cmd_parm == NULL) {
+ rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
+ goto exit;
}
+
+ mcc_duration = rtw_zmalloc(sizeof(u8));
+ if (mcc_duration == NULL) {
+ rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj));
+ rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm));
+ res = _FAIL;
+ goto exit;
+ }
+
+ pdrvextra_cmd_parm->ec_id = MCC_SET_DURATION_WK_CID;
+ pdrvextra_cmd_parm->type = type;
+ pdrvextra_cmd_parm->size = 1;
+ pdrvextra_cmd_parm->pbuf = mcc_duration;
+
+ _rtw_memcpy(mcc_duration, &val, 1);
+
+ init_h2fwcmd_w_parm_no_rsp(cmdobj, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
+ res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
+
+exit:
+ return res;
}
#endif /* CONFIG_MCC_MODE */
diff --git a/hal/hal_mp.c b/hal/hal_mp.c
index 16fdd7f..8616dcb 100644
--- a/hal/hal_mp.c
+++ b/hal/hal_mp.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,12 +11,7 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#define _HAL_MP_C_
#include
@@ -75,57 +70,55 @@ u8 MgntQuery_NssTxRate(u16 Rate)
void hal_mpt_SwitchRfSetting(PADAPTER pAdapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
- PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
+ PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
u8 ChannelToSw = pMptCtx->MptChannelToSw;
- ULONG ulRateIdx = pMptCtx->MptRateIndex;
+ ULONG ulRateIdx = pMptCtx->mpt_rate_index;
ULONG ulbandwidth = pMptCtx->MptBandWidth;
/* <20120525, Kordan> Dynamic mechanism for APK, asked by Dennis.*/
if (IS_HARDWARE_TYPE_8188ES(pAdapter) && (1 <= ChannelToSw && ChannelToSw <= 11) &&
(ulRateIdx == MPT_RATE_MCS0 || ulRateIdx == MPT_RATE_1M || ulRateIdx == MPT_RATE_6M)) {
- pMptCtx->backup0x52_RF_A = (u1Byte)PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0);
- pMptCtx->backup0x52_RF_B = (u1Byte)PHY_QueryRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0);
+ pMptCtx->backup0x52_RF_A = (u1Byte)phy_query_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
+ pMptCtx->backup0x52_RF_B = (u1Byte)phy_query_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0);
if ((PlatformEFIORead4Byte(pAdapter, 0xF4) & BIT29) == BIT29) {
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xB);
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xB);
+ phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xB);
+ phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xB);
} else {
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xD);
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xD);
+ phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xD);
+ phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xD);
}
} else if (IS_HARDWARE_TYPE_8188EE(pAdapter)) { /* <20140903, VincentL> Asked by RF Eason and Edlu*/
if (ChannelToSw == 3 && ulbandwidth == MPT_BW_40MHZ) {
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
+ phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
+ phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/
} else {
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
+ phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
+ phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/
}
} else if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_A);
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_B);
+ phy_set_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_A);
+ phy_set_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_B);
}
}
s32 hal_mpt_SetPowerTracking(PADAPTER padapter, u8 enable)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
- PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
+ struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
if (!netif_running(padapter->pnetdev)) {
- RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: interface not opened!\n"));
return _FAIL;
}
if (check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
- RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: not in MP mode!\n"));
return _FAIL;
}
if (enable)
- pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _TRUE;
+ pDM_Odm->rf_calibrate_info.txpowertrack_control = _TRUE;
else
- pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _FALSE;
+ pDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE;
return _SUCCESS;
}
@@ -133,10 +126,10 @@ s32 hal_mpt_SetPowerTracking(PADAPTER padapter, u8 enable)
void hal_mpt_GetPowerTracking(PADAPTER padapter, u8 *enable)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
- PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
+ struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
- *enable = pDM_Odm->RFCalibrateInfo.TxPowerTrackControl;
+ *enable = pDM_Odm->rf_calibrate_info.txpowertrack_control;
}
@@ -146,20 +139,16 @@ void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
u32 CurrCCKSwingVal = 0, CCKSwingIndex = 12;
u8 i;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
- PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx);
- u1Byte u1Channel = pHalData->CurrentChannel;
- ULONG ulRateIdx = pMptCtx->MptRateIndex;
+ PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx);
+ u1Byte u1Channel = pHalData->current_channel;
+ ULONG ulRateIdx = pMptCtx->mpt_rate_index;
u1Byte DataRate = 0xFF;
- /* Suggested by BB David. 2015.04.27*/
- if(IS_HARDWARE_TYPE_8188F(Adapter))
- return;
-
/* Do not modify CCK TX filter parameters for 8822B*/
if(IS_HARDWARE_TYPE_8822B(Adapter) || IS_HARDWARE_TYPE_8821C(Adapter) || IS_HARDWARE_TYPE_8723D(Adapter))
return;
- DataRate = MptToMgntRate(ulRateIdx);
+ DataRate = mpt_to_mgnt_rate(ulRateIdx);
if (u1Channel == 14 && IS_CCK_RATE(DataRate))
pHalData->bCCKinCH14 = TRUE;
@@ -169,33 +158,89 @@ void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
if (IS_HARDWARE_TYPE_8703B(Adapter)) {
if ((u1Channel == 14) && IS_CCK_RATE(DataRate)) {
/* Channel 14 in CCK, need to set 0xA26~0xA29 to 0 for 8703B */
- PHY_SetBBReg(Adapter, rCCK0_TxFilter2, bMaskHWord, 0);
- PHY_SetBBReg(Adapter, rCCK0_DebugPort, bMaskLWord, 0);
+ phy_set_bb_reg(Adapter, rCCK0_TxFilter2, bMaskHWord, 0);
+ phy_set_bb_reg(Adapter, rCCK0_DebugPort, bMaskLWord, 0);
- RT_TRACE(_module_mp_, DBG_LOUD, ("MPT_CCKTxPowerAdjust 8703B CCK in Channel %u\n", u1Channel));
} else {
/* Normal setting for 8703B, just recover to the default setting. */
/* This hardcore values reference from the parameter which BB team gave. */
for (i = 0 ; i < 2 ; ++i)
- PHY_SetBBReg(Adapter, pHalData->RegForRecover[i].offset, bMaskDWord, pHalData->RegForRecover[i].value);
+ phy_set_bb_reg(Adapter, pHalData->RegForRecover[i].offset, bMaskDWord, pHalData->RegForRecover[i].value);
- RT_TRACE(_module_mp_, DBG_LOUD, ("MPT_CCKTxPowerAdjust 8703B in Channel %u restore to default setting\n", u1Channel));
}
} else if (IS_HARDWARE_TYPE_8723D(Adapter)) {
/* 2.4G CCK TX DFIR */
/* 2016.01.20 Suggest from RS BB mingzhi*/
if ((u1Channel == 14)) {
- PHY_SetBBReg(Adapter, rCCK0_TxFilter2, bMaskDWord, 0x0000B81C);
- PHY_SetBBReg(Adapter, rCCK0_DebugPort, bMaskDWord, 0x00000000);
- PHY_SetBBReg(Adapter, 0xAAC, bMaskDWord, 0x00003667);
+ phy_set_bb_reg(Adapter, rCCK0_TxFilter2, bMaskDWord, 0x0000B81C);
+ phy_set_bb_reg(Adapter, rCCK0_DebugPort, bMaskDWord, 0x00000000);
+ phy_set_bb_reg(Adapter, 0xAAC, bMaskDWord, 0x00003667);
} else {
for (i = 0 ; i < 3 ; ++i) {
- PHY_SetBBReg(Adapter,
+ phy_set_bb_reg(Adapter,
pHalData->RegForRecover[i].offset,
bMaskDWord,
pHalData->RegForRecover[i].value);
}
}
+ } else if (IS_HARDWARE_TYPE_8188F(Adapter)) {
+ /* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/
+ CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
+ CCKSwingIndex = 20; /* default index */
+
+ if (!pHalData->bCCKinCH14) {
+ /* Readback the current bb cck swing value and compare with the table to */
+ /* get the current swing index */
+ for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
+ if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch1_ch13_88f[i][0]) &&
+ (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch1_ch13_88f[i][1])) {
+ CCKSwingIndex = i;
+ break;
+ }
+ }
+ write_bbreg(Adapter, 0xa22, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][0]);
+ write_bbreg(Adapter, 0xa23, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][1]);
+ write_bbreg(Adapter, 0xa24, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][2]);
+ write_bbreg(Adapter, 0xa25, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][3]);
+ write_bbreg(Adapter, 0xa26, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][4]);
+ write_bbreg(Adapter, 0xa27, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][5]);
+ write_bbreg(Adapter, 0xa28, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][6]);
+ write_bbreg(Adapter, 0xa29, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][7]);
+ write_bbreg(Adapter, 0xa9a, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][8]);
+ write_bbreg(Adapter, 0xa9b, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][9]);
+ write_bbreg(Adapter, 0xa9c, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][10]);
+ write_bbreg(Adapter, 0xa9d, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][11]);
+ write_bbreg(Adapter, 0xaa0, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][12]);
+ write_bbreg(Adapter, 0xaa1, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][13]);
+ write_bbreg(Adapter, 0xaa2, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][14]);
+ write_bbreg(Adapter, 0xaa3, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][15]);
+ RTW_INFO("%s , cck_swing_table_ch1_ch13_88f[%d]\n", __func__, CCKSwingIndex);
+ } else {
+ for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
+ if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch14_88f[i][0]) &&
+ (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch14_88f[i][1])) {
+ CCKSwingIndex = i;
+ break;
+ }
+ }
+ write_bbreg(Adapter, 0xa22, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][0]);
+ write_bbreg(Adapter, 0xa23, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][1]);
+ write_bbreg(Adapter, 0xa24, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][2]);
+ write_bbreg(Adapter, 0xa25, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][3]);
+ write_bbreg(Adapter, 0xa26, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][4]);
+ write_bbreg(Adapter, 0xa27, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][5]);
+ write_bbreg(Adapter, 0xa28, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][6]);
+ write_bbreg(Adapter, 0xa29, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][7]);
+ write_bbreg(Adapter, 0xa9a, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][8]);
+ write_bbreg(Adapter, 0xa9b, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][9]);
+ write_bbreg(Adapter, 0xa9c, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][10]);
+ write_bbreg(Adapter, 0xa9d, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][11]);
+ write_bbreg(Adapter, 0xaa0, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][12]);
+ write_bbreg(Adapter, 0xaa1, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][13]);
+ write_bbreg(Adapter, 0xaa2, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][14]);
+ write_bbreg(Adapter, 0xaa3, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][15]);
+ RTW_INFO("%s , cck_swing_table_ch14_88f[%d]\n", __func__, CCKSwingIndex);
+ }
} else {
/* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/
@@ -205,57 +250,53 @@ void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
/* Readback the current bb cck swing value and compare with the table to */
/* get the current swing index */
for (i = 0; i < CCK_TABLE_SIZE; i++) {
- if (((CurrCCKSwingVal & 0xff) == (u32)CCKSwingTable_Ch1_Ch13[i][0]) &&
- (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)CCKSwingTable_Ch1_Ch13[i][1])) {
+ if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch1_ch13[i][0]) &&
+ (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch1_ch13[i][1])) {
CCKSwingIndex = i;
- RT_TRACE(_module_mp_, DBG_LOUD, ("Ch1~13, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n",
- (rCCK0_TxFilter1 + 2), CurrCCKSwingVal, CCKSwingIndex));
break;
}
}
/*Write 0xa22 0xa23*/
- TempVal = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][0] +
- (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][1] << 8);
+ TempVal = cck_swing_table_ch1_ch13[CCKSwingIndex][0] +
+ (cck_swing_table_ch1_ch13[CCKSwingIndex][1] << 8);
/*Write 0xa24 ~ 0xa27*/
TempVal2 = 0;
- TempVal2 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][2] +
- (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][3] << 8) +
- (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][4] << 16) +
- (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][5] << 24);
+ TempVal2 = cck_swing_table_ch1_ch13[CCKSwingIndex][2] +
+ (cck_swing_table_ch1_ch13[CCKSwingIndex][3] << 8) +
+ (cck_swing_table_ch1_ch13[CCKSwingIndex][4] << 16) +
+ (cck_swing_table_ch1_ch13[CCKSwingIndex][5] << 24);
/*Write 0xa28 0xa29*/
TempVal3 = 0;
- TempVal3 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][6] +
- (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][7] << 8);
+ TempVal3 = cck_swing_table_ch1_ch13[CCKSwingIndex][6] +
+ (cck_swing_table_ch1_ch13[CCKSwingIndex][7] << 8);
} else {
for (i = 0; i < CCK_TABLE_SIZE; i++) {
- if (((CurrCCKSwingVal & 0xff) == (u32)CCKSwingTable_Ch14[i][0]) &&
- (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)CCKSwingTable_Ch14[i][1])) {
+ if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch14[i][0]) &&
+ (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch14[i][1])) {
CCKSwingIndex = i;
- RT_TRACE(_module_mp_, DBG_LOUD, ("Ch14, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n",
- (rCCK0_TxFilter1 + 2), CurrCCKSwingVal, CCKSwingIndex));
break;
}
}
/*Write 0xa22 0xa23*/
- TempVal = CCKSwingTable_Ch14[CCKSwingIndex][0] +
- (CCKSwingTable_Ch14[CCKSwingIndex][1] << 8);
+ TempVal = cck_swing_table_ch14[CCKSwingIndex][0] +
+ (cck_swing_table_ch14[CCKSwingIndex][1] << 8);
/*Write 0xa24 ~ 0xa27*/
TempVal2 = 0;
- TempVal2 = CCKSwingTable_Ch14[CCKSwingIndex][2] +
- (CCKSwingTable_Ch14[CCKSwingIndex][3] << 8) +
- (CCKSwingTable_Ch14[CCKSwingIndex][4] << 16) +
- (CCKSwingTable_Ch14[CCKSwingIndex][5] << 24);
+ TempVal2 = cck_swing_table_ch14[CCKSwingIndex][2] +
+ (cck_swing_table_ch14[CCKSwingIndex][3] << 8) +
+ (cck_swing_table_ch14[CCKSwingIndex][4] << 16) +
+ (cck_swing_table_ch14[CCKSwingIndex][5] << 24);
/*Write 0xa28 0xa29*/
TempVal3 = 0;
- TempVal3 = CCKSwingTable_Ch14[CCKSwingIndex][6] +
- (CCKSwingTable_Ch14[CCKSwingIndex][7] << 8);
+ TempVal3 = cck_swing_table_ch14[CCKSwingIndex][6] +
+ (cck_swing_table_ch14[CCKSwingIndex][7] << 8);
}
write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal);
@@ -267,20 +308,25 @@ void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
void hal_mpt_SetChannel(PADAPTER pAdapter)
{
- u8 eRFPath;
+ enum rf_path eRFPath;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
- PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
+ struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
struct mp_priv *pmp = &pAdapter->mppriv;
u8 channel = pmp->channel;
u8 bandwidth = pmp->bandwidth;
hal_mpt_SwitchRfSetting(pAdapter);
- SelectChannel(pAdapter, channel);
-
pHalData->bSwChnl = _TRUE;
pHalData->bSetChnlBW = _TRUE;
- rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, 0, 0);
+
+ if (bandwidth > 0) {
+ if ((channel >= 3 && channel <= 11) || (channel >= 42 && channel <= 171))
+ rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, pmp->prime_channel_offset, pmp->prime_channel_offset);
+ else
+ rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, 0, 0);
+ } else
+ rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, 0, 0);
hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14);
@@ -298,33 +344,38 @@ void hal_mpt_SetBandwidth(PADAPTER pAdapter)
u8 channel = pmp->channel;
u8 bandwidth = pmp->bandwidth;
- SetBWMode(pAdapter, pmp->bandwidth, pmp->prime_channel_offset);
pHalData->bSwChnl = _TRUE;
pHalData->bSetChnlBW = _TRUE;
- rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, 0, 0);
+
+ if (bandwidth > 0) {
+ if ((channel >= 3 && channel <= 11) || (channel >= 42 && channel <= 171))
+ rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, pmp->prime_channel_offset, pmp->prime_channel_offset);
+ else
+ rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, 0, 0);
+ } else
+ rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, 0, 0);
hal_mpt_SwitchRfSetting(pAdapter);
}
void mpt_SetTxPower_Old(PADAPTER pAdapter, MPT_TXPWR_DEF Rate, u8 *pTxPower)
{
- RT_TRACE(_module_mp_, DBG_LOUD, ("===>mpt_SetTxPower_Old(): Case = %d\n", Rate));
switch (Rate) {
case MPT_CCK: {
u4Byte TxAGC = 0, pwr = 0;
u1Byte rf;
- pwr = pTxPower[ODM_RF_PATH_A];
+ pwr = pTxPower[RF_PATH_A];
if (pwr < 0x3f) {
TxAGC = (pwr << 16) | (pwr << 8) | (pwr);
- PHY_SetBBReg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pTxPower[ODM_RF_PATH_A]);
- PHY_SetBBReg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC);
+ phy_set_bb_reg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pTxPower[RF_PATH_A]);
+ phy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC);
}
- pwr = pTxPower[ODM_RF_PATH_B];
+ pwr = pTxPower[RF_PATH_B];
if (pwr < 0x3f) {
TxAGC = (pwr << 16) | (pwr << 8) | (pwr);
- PHY_SetBBReg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, pTxPower[ODM_RF_PATH_B]);
- PHY_SetBBReg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, TxAGC);
+ phy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, pTxPower[RF_PATH_B]);
+ phy_set_bb_reg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, TxAGC);
}
}
break;
@@ -337,24 +388,24 @@ void mpt_SetTxPower_Old(PADAPTER pAdapter, MPT_TXPWR_DEF Rate, u8 *pTxPower)
if (pwr < 0x3f) {
TxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
RTW_INFO("HT Tx-rf(A) Power = 0x%x\n", TxAGC);
- PHY_SetBBReg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);
- PHY_SetBBReg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);
- PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);
- PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);
- PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);
- PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);
+ phy_set_bb_reg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);
+ phy_set_bb_reg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);
+ phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);
+ phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);
+ phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);
+ phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);
}
TxAGC = 0;
pwr = pTxPower[1];
if (pwr < 0x3f) {
TxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr);
RTW_INFO("HT Tx-rf(B) Power = 0x%x\n", TxAGC);
- PHY_SetBBReg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC);
- PHY_SetBBReg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC);
- PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC);
- PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC);
- PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC);
- PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC);
+ phy_set_bb_reg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC);
+ phy_set_bb_reg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC);
+ phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC);
+ phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC);
+ phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC);
+ phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC);
}
}
break;
@@ -375,12 +426,12 @@ mpt_SetTxPower(
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
u1Byte path = 0 , i = 0, MaxRate = MGN_6M;
- u1Byte StartPath = ODM_RF_PATH_A, EndPath = ODM_RF_PATH_B;
+ u1Byte StartPath = RF_PATH_A, EndPath = RF_PATH_B;
if (IS_HARDWARE_TYPE_8814A(pAdapter))
- EndPath = ODM_RF_PATH_D;
+ EndPath = RF_PATH_D;
else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter))
- EndPath = ODM_RF_PATH_A;
+ EndPath = RF_PATH_A;
switch (Rate) {
case MPT_CCK: {
@@ -463,20 +514,19 @@ mpt_SetTxPower(
void hal_mpt_SetTxPower(PADAPTER pAdapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
- PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
- PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
+ PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
+ struct dm_struct *pDM_Odm = &pHalData->odmpriv;
- if (pHalData->rf_chip < RF_TYPE_MAX) {
+ if (pHalData->rf_chip < RF_CHIP_MAX) {
if (IS_HARDWARE_TYPE_8188E(pAdapter) ||
IS_HARDWARE_TYPE_8723B(pAdapter) ||
IS_HARDWARE_TYPE_8192E(pAdapter) ||
IS_HARDWARE_TYPE_8703B(pAdapter) ||
IS_HARDWARE_TYPE_8188F(pAdapter)) {
- u8 path = (pHalData->AntennaTxPath == ANTENNA_A) ? (ODM_RF_PATH_A) : (ODM_RF_PATH_B);
+ u8 path = (pHalData->antenna_tx_path == ANTENNA_A) ? (RF_PATH_A) : (RF_PATH_B);
RTW_INFO("===> MPT_ProSetTxPower: Old\n");
- RT_TRACE(_module_mp_, DBG_LOUD, ("===> MPT_ProSetTxPower[Old]:\n"));
mpt_SetTxPower_Old(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel);
mpt_SetTxPower_Old(pAdapter, MPT_OFDM_AND_HT, pMptCtx->TxPwrLevel);
@@ -489,18 +539,18 @@ void hal_mpt_SetTxPower(PADAPTER pAdapter)
}
} else
- RTW_INFO("RFChipID < RF_TYPE_MAX, the RF chip is not supported - %d\n", pHalData->rf_chip);
+ RTW_INFO("RFChipID < RF_CHIP_MAX, the RF chip is not supported - %d\n", pHalData->rf_chip);
- ODM_ClearTxPowerTrackingState(pDM_Odm);
+ odm_clear_txpowertracking_state(pDM_Odm);
}
void hal_mpt_SetDataRate(PADAPTER pAdapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
- PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
+ PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
u32 DataRate;
- DataRate = MptToMgntRate(pMptCtx->MptRateIndex);
+ DataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
hal_mpt_SwitchRfSetting(pAdapter);
@@ -508,24 +558,24 @@ void hal_mpt_SetDataRate(PADAPTER pAdapter)
#ifdef CONFIG_RTL8723B
if (IS_HARDWARE_TYPE_8723B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter)) {
if (IS_CCK_RATE(DataRate)) {
- if (pMptCtx->MptRfPath == ODM_RF_PATH_A)
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0x6);
+ if (pMptCtx->mpt_rf_path == RF_PATH_A)
+ phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0x6);
else
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0x6);
+ phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0x6);
} else {
- if (pMptCtx->MptRfPath == ODM_RF_PATH_A)
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0xE);
+ if (pMptCtx->mpt_rf_path == RF_PATH_A)
+ phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0xE);
else
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0xE);
+ phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0xE);
}
}
if ((IS_HARDWARE_TYPE_8723BS(pAdapter) &&
((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90)))) {
- if (pMptCtx->MptRfPath == ODM_RF_PATH_A)
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0xE);
+ if (pMptCtx->mpt_rf_path == RF_PATH_A)
+ phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, 0xF, 0xE);
else
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0xE);
+ phy_set_rf_reg(pAdapter, RF_PATH_A, 0x71, 0xF, 0xE);
}
#endif
}
@@ -538,15 +588,15 @@ VOID mpt_ToggleIG_8814A(PADAPTER pAdapter)
u1Byte Path = 0;
u4Byte IGReg = rA_IGI_Jaguar, IGvalue = 0;
- for (Path; Path <= ODM_RF_PATH_D; Path++) {
+ for (Path; Path <= RF_PATH_D; Path++) {
switch (Path) {
- case ODM_RF_PATH_B:
+ case RF_PATH_B:
IGReg = rB_IGI_Jaguar;
break;
- case ODM_RF_PATH_C:
+ case RF_PATH_C:
IGReg = rC_IGI_Jaguar2;
break;
- case ODM_RF_PATH_D:
+ case RF_PATH_D:
IGReg = rD_IGI_Jaguar2;
break;
default:
@@ -554,9 +604,9 @@ VOID mpt_ToggleIG_8814A(PADAPTER pAdapter)
break;
}
- IGvalue = PHY_QueryBBReg(pAdapter, IGReg, bMaskByte0);
- PHY_SetBBReg(pAdapter, IGReg, bMaskByte0, IGvalue + 2);
- PHY_SetBBReg(pAdapter, IGReg, bMaskByte0, IGvalue);
+ IGvalue = phy_query_bb_reg(pAdapter, IGReg, bMaskByte0);
+ phy_set_bb_reg(pAdapter, IGReg, bMaskByte0, IGvalue + 2);
+ phy_set_bb_reg(pAdapter, IGReg, bMaskByte0, IGvalue);
}
}
@@ -564,108 +614,85 @@ VOID mpt_SetRFPath_8814A(PADAPTER pAdapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
- PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx;
+ PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.mpt_ctx;
R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */
R_ANTENNA_SELECT_CCK *p_cck_txrx;
- u8 ForcedDataRate = MptToMgntRate(pMptCtx->MptRateIndex);
+ u8 ForcedDataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
u8 HtStbcCap = pAdapter->registrypriv.stbc_cap;
/*/PRT_HIGH_THROUGHPUT pHTInfo = GET_HT_INFO(pMgntInfo);*/
/*/PRT_VERY_HIGH_THROUGHPUT pVHTInfo = GET_VHT_INFO(pMgntInfo);*/
- u32 ulAntennaTx = pHalData->AntennaTxPath;
+ u32 ulAntennaTx = pHalData->antenna_tx_path;
u32 ulAntennaRx = pHalData->AntennaRxPath;
u8 NssforRate = MgntQuery_NssTxRate(ForcedDataRate);
- if ((NssforRate == RF_2TX) || ((NssforRate == RF_1TX) && IS_HT_RATE(ForcedDataRate)) || ((NssforRate == RF_1TX) && IS_VHT_RATE(ForcedDataRate))) {
- RTW_INFO("===> SetAntenna 2T ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
-
- switch (ulAntennaTx) {
- case ANTENNA_BC:
- pMptCtx->MptRfPath = ODM_RF_PATH_BC;
- /*pHalData->ValidTxPath = 0x06; linux no use */
- PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0000fff0, 0x106); /*/ 0x940[15:4]=12'b0000_0100_0011*/
- break;
-
- case ANTENNA_CD:
- pMptCtx->MptRfPath = ODM_RF_PATH_CD;
- /*pHalData->ValidTxPath = 0x0C;*/
- PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0000fff0, 0x40c); /*/ 0x940[15:4]=12'b0000_0100_0011*/
- break;
- case ANTENNA_AB:
- default:
- pMptCtx->MptRfPath = ODM_RF_PATH_AB;
- /*pHalData->ValidTxPath = 0x03;*/
- PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0000fff0, 0x043); /*/ 0x940[15:4]=12'b0000_0100_0011*/
- break;
- }
-
- } else if (NssforRate == RF_3TX) {
- RTW_INFO("===> SetAntenna 3T ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
+ if (NssforRate == RF_3TX) {
+ RTW_INFO("===> SetAntenna 3T Rate ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
switch (ulAntennaTx) {
case ANTENNA_BCD:
- pMptCtx->MptRfPath = ODM_RF_PATH_BCD;
+ pMptCtx->mpt_rf_path = RF_PATH_BCD;
/*pHalData->ValidTxPath = 0x0e;*/
- PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x90e); /*/ 0x940[27:16]=12'b0010_0100_0111*/
+ phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x90e); /*/ 0x940[27:16]=12'b0010_0100_0111*/
break;
case ANTENNA_ABC:
default:
- pMptCtx->MptRfPath = ODM_RF_PATH_ABC;
+ pMptCtx->mpt_rf_path = RF_PATH_ABC;
/*pHalData->ValidTxPath = 0x0d;*/
- PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x247); /*/ 0x940[27:16]=12'b0010_0100_0111*/
+ phy_set_bb_reg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x247); /*/ 0x940[27:16]=12'b0010_0100_0111*/
break;
}
} else { /*/if(NssforRate == RF_1TX)*/
- RTW_INFO("===> SetAntenna 1T ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
+ RTW_INFO("===> SetAntenna for 1T/2T Rate, ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx);
switch (ulAntennaTx) {
case ANTENNA_BCD:
- pMptCtx->MptRfPath = ODM_RF_PATH_BCD;
+ pMptCtx->mpt_rf_path = RF_PATH_BCD;
/*pHalData->ValidTxPath = 0x0e;*/
- PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x7);
- PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0xe);
- PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0xe);
+ phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x7);
+ phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0xe);
+ phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0xe);
break;
case ANTENNA_BC:
- pMptCtx->MptRfPath = ODM_RF_PATH_BC;
+ pMptCtx->mpt_rf_path = RF_PATH_BC;
/*pHalData->ValidTxPath = 0x06;*/
- PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x6);
- PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0x6);
- PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0x6);
+ phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x6);
+ phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0x000f00000, 0x6);
+ phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x6);
break;
case ANTENNA_B:
- pMptCtx->MptRfPath = ODM_RF_PATH_B;
+ pMptCtx->mpt_rf_path = RF_PATH_B;
/*pHalData->ValidTxPath = 0x02;*/
- PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x4); /*/ 0xa07[7:4] = 4'b0100*/
- PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x002); /*/ 0x93C[31:20]=12'b0000_0000_0010*/
- PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0x2); /* 0x80C[7:4] = 4'b0010*/
+ phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x4); /*/ 0xa07[7:4] = 4'b0100*/
+ phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x002); /*/ 0x93C[31:20]=12'b0000_0000_0010*/
+ phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x2); /* 0x80C[7:4] = 4'b0010*/
break;
case ANTENNA_C:
- pMptCtx->MptRfPath = ODM_RF_PATH_C;
+ pMptCtx->mpt_rf_path = RF_PATH_C;
/*pHalData->ValidTxPath = 0x04;*/
- PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x2); /*/ 0xa07[7:4] = 4'b0010*/
- PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x004); /*/ 0x93C[31:20]=12'b0000_0000_0100*/
- PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0x4); /*/ 0x80C[7:4] = 4'b0100*/
+ phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x2); /*/ 0xa07[7:4] = 4'b0010*/
+ phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x004); /*/ 0x93C[31:20]=12'b0000_0000_0100*/
+ phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x4); /*/ 0x80C[7:4] = 4'b0100*/
break;
case ANTENNA_D:
- pMptCtx->MptRfPath = ODM_RF_PATH_D;
+ pMptCtx->mpt_rf_path = RF_PATH_D;
/*pHalData->ValidTxPath = 0x08;*/
- PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x1); /*/ 0xa07[7:4] = 4'b0001*/
- PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x008); /*/ 0x93C[31:20]=12'b0000_0000_1000*/
- PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0x8); /*/ 0x80C[7:4] = 4'b1000*/
+ phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x1); /*/ 0xa07[7:4] = 4'b0001*/
+ phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x008); /*/ 0x93C[31:20]=12'b0000_0000_1000*/
+ phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x8); /*/ 0x80C[7:4] = 4'b1000*/
break;
case ANTENNA_A:
default:
- pMptCtx->MptRfPath = ODM_RF_PATH_A;
+ pMptCtx->mpt_rf_path = RF_PATH_A;
/*pHalData->ValidTxPath = 0x01;*/
- PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x8); /*/ 0xa07[7:4] = 4'b1000*/
- PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x001); /*/ 0x93C[31:20]=12'b0000_0000_0001*/
- PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0x1); /*/ 0x80C[7:4] = 4'b0001*/
+ phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x8); /*/ 0xa07[7:4] = 4'b1000*/
+ phy_set_bb_reg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x001); /*/ 0x93C[31:20]=12'b0000_0000_0001*/
+ phy_set_bb_reg(pAdapter, rTxPath_Jaguar, 0xf0, 0x1); /*/ 0x80C[7:4] = 4'b0001*/
break;
}
}
@@ -673,133 +700,147 @@ VOID mpt_SetRFPath_8814A(PADAPTER pAdapter)
switch (ulAntennaRx) {
case ANTENNA_A:
/*pHalData->ValidRxPath = 0x01;*/
- PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
- PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
- PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
- PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x0);
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
+ phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
+ phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
+ phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
+ phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
+ phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
+ phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x0);
+ phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/
+ phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
+ phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
+ phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
/*/ CCA related PD_delay_th*/
- PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
- PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
+ phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
+ phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
break;
case ANTENNA_B:
/*pHalData->ValidRxPath = 0x02;*/
- PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
- PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);
- PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
- PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x1);
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
+ phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
+ phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
+ phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);
+ phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
+ phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
+ phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x1);
+ phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
+ phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
+ phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
+ phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
/*/ CCA related PD_delay_th*/
- PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
- PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
+ phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
+ phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
break;
case ANTENNA_C:
/*pHalData->ValidRxPath = 0x04;*/
- PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
- PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x44);
- PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
- PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x2);
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
+ phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
+ phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
+ phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x44);
+ phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
+ phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
+ phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x2);
+ phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
+ phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
+ phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
+ phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
/*/ CCA related PD_delay_th*/
- PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
- PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
+ phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
+ phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
break;
case ANTENNA_D:
/*pHalData->ValidRxPath = 0x08;*/
- PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
- PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x88);
- PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
- PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x3);
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
+ phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
+ phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
+ phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x88);
+ phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
+ phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
+ phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x3);
+ phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
+ phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
+ phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/
+ phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
/*/ CCA related PD_delay_th*/
- PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
- PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
+ phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
+ phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
break;
case ANTENNA_BC:
/*pHalData->ValidRxPath = 0x06;*/
- PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
- PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x66);
- PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
- PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
+ phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
+ phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
+ phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x66);
+ phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
+ phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
+ phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);
+ phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
+ phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
+ phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/
+ phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/
/*/ CCA related PD_delay_th*/
- PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
- PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
+ phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
+ phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
break;
case ANTENNA_CD:
/*pHalData->ValidRxPath = 0x0C;*/
- PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
- PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xcc);
- PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
- PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0xB);
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
+ phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
+ phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
+ phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xcc);
+ phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
+ phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
+ phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0xB);
+ phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
+ phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
+ phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/
+ phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
/*/ CCA related PD_delay_th*/
- PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
- PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
+ phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5);
+ phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA);
break;
case ANTENNA_BCD:
/*pHalData->ValidRxPath = 0x0e;*/
- PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
- PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xee);
- PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
- PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, Rx mode*/
+ phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
+ phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
+ phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xee);
+ phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
+ phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
+ phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6);
+ phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/
+ phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
+ phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
+ phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, Rx mode*/
/*/ CCA related PD_delay_th*/
- PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);
- PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);
+ phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);
+ phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);
break;
case ANTENNA_ABCD:
/*pHalData->ValidRxPath = 0x0f;*/
- PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2);
- PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xff);
- PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3);
- PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x1);
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
+ phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1);
+ phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x2);
+ phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xff);
+ phy_set_bb_reg(pAdapter, 0x1000, bMaskByte2, 0x3);
+ phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0);
+ phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x1);
+ phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/
+ phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/
+ phy_set_rf_reg(pAdapter, RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/
+ phy_set_rf_reg(pAdapter, RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/
/*/ CCA related PD_delay_th*/
- PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);
- PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);
+ phy_set_bb_reg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3);
+ phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8);
break;
default:
- RT_TRACE(_module_mp_, _drv_warning_, ("Unknown Rx antenna.\n"));
break;
}
PHY_Set_SecCCATH_by_RXANT_8814A(pAdapter, ulAntennaRx);
mpt_ToggleIG_8814A(pAdapter);
- RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n"));
}
#endif /* CONFIG_RTL8814A */
#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
@@ -810,100 +851,100 @@ mpt_SetSingleTone_8814A(
IN BOOLEAN bEnPMacTx)
{
- PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
- u1Byte StartPath = ODM_RF_PATH_A, EndPath = ODM_RF_PATH_A;
+ PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
+ u1Byte StartPath = RF_PATH_A, EndPath = RF_PATH_A;
static u4Byte regIG0 = 0, regIG1 = 0, regIG2 = 0, regIG3 = 0;
if (bSingleTone) {
- regIG0 = PHY_QueryBBReg(pAdapter, rA_TxScale_Jaguar, bMaskDWord); /*/ 0xC1C[31:21]*/
- regIG1 = PHY_QueryBBReg(pAdapter, rB_TxScale_Jaguar, bMaskDWord); /*/ 0xE1C[31:21]*/
- regIG2 = PHY_QueryBBReg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord); /*/ 0x181C[31:21]*/
- regIG3 = PHY_QueryBBReg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord); /*/ 0x1A1C[31:21]*/
-
- switch (pMptCtx->MptRfPath) {
- case ODM_RF_PATH_A:
- case ODM_RF_PATH_B:
- case ODM_RF_PATH_C:
- case ODM_RF_PATH_D:
- StartPath = pMptCtx->MptRfPath;
- EndPath = pMptCtx->MptRfPath;
+ regIG0 = phy_query_bb_reg(pAdapter, rA_TxScale_Jaguar, bMaskDWord); /*/ 0xC1C[31:21]*/
+ regIG1 = phy_query_bb_reg(pAdapter, rB_TxScale_Jaguar, bMaskDWord); /*/ 0xE1C[31:21]*/
+ regIG2 = phy_query_bb_reg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord); /*/ 0x181C[31:21]*/
+ regIG3 = phy_query_bb_reg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord); /*/ 0x1A1C[31:21]*/
+
+ switch (pMptCtx->mpt_rf_path) {
+ case RF_PATH_A:
+ case RF_PATH_B:
+ case RF_PATH_C:
+ case RF_PATH_D:
+ StartPath = pMptCtx->mpt_rf_path;
+ EndPath = pMptCtx->mpt_rf_path;
break;
- case ODM_RF_PATH_AB:
- EndPath = ODM_RF_PATH_B;
+ case RF_PATH_AB:
+ EndPath = RF_PATH_B;
break;
- case ODM_RF_PATH_BC:
- StartPath = ODM_RF_PATH_B;
- EndPath = ODM_RF_PATH_C;
+ case RF_PATH_BC:
+ StartPath = RF_PATH_B;
+ EndPath = RF_PATH_C;
break;
- case ODM_RF_PATH_ABC:
- EndPath = ODM_RF_PATH_C;
+ case RF_PATH_ABC:
+ EndPath = RF_PATH_C;
break;
- case ODM_RF_PATH_BCD:
- StartPath = ODM_RF_PATH_B;
- EndPath = ODM_RF_PATH_D;
+ case RF_PATH_BCD:
+ StartPath = RF_PATH_B;
+ EndPath = RF_PATH_D;
break;
- case ODM_RF_PATH_ABCD:
- EndPath = ODM_RF_PATH_D;
+ case RF_PATH_ABCD:
+ EndPath = RF_PATH_D;
break;
}
if (bEnPMacTx == FALSE) {
- hal_mpt_SetOFDMContinuousTx(pAdapter, _TRUE);
+ hal_mpt_SetContinuousTx(pAdapter, _TRUE);
issue_nulldata(pAdapter, NULL, 1, 3, 500);
}
- PHY_SetBBReg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); /*/ Disable CCA*/
+ phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); /*/ Disable CCA*/
for (StartPath; StartPath <= EndPath; StartPath++) {
- PHY_SetRFReg(pAdapter, StartPath, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
- PHY_SetRFReg(pAdapter, StartPath, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
+ phy_set_rf_reg(pAdapter, StartPath, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
+ phy_set_rf_reg(pAdapter, StartPath, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
- PHY_SetRFReg(pAdapter, StartPath, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO enabled*/
+ phy_set_rf_reg(pAdapter, StartPath, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
}
- PHY_SetBBReg(pAdapter, rA_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xC1C[31:21]*/
- PHY_SetBBReg(pAdapter, rB_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xE1C[31:21]*/
- PHY_SetBBReg(pAdapter, rC_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x181C[31:21]*/
- PHY_SetBBReg(pAdapter, rD_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x1A1C[31:21]*/
+ phy_set_bb_reg(pAdapter, rA_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xC1C[31:21]*/
+ phy_set_bb_reg(pAdapter, rB_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xE1C[31:21]*/
+ phy_set_bb_reg(pAdapter, rC_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x181C[31:21]*/
+ phy_set_bb_reg(pAdapter, rD_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x1A1C[31:21]*/
} else {
- switch (pMptCtx->MptRfPath) {
- case ODM_RF_PATH_A:
- case ODM_RF_PATH_B:
- case ODM_RF_PATH_C:
- case ODM_RF_PATH_D:
- StartPath = pMptCtx->MptRfPath;
- EndPath = pMptCtx->MptRfPath;
+ switch (pMptCtx->mpt_rf_path) {
+ case RF_PATH_A:
+ case RF_PATH_B:
+ case RF_PATH_C:
+ case RF_PATH_D:
+ StartPath = pMptCtx->mpt_rf_path;
+ EndPath = pMptCtx->mpt_rf_path;
break;
- case ODM_RF_PATH_AB:
- EndPath = ODM_RF_PATH_B;
+ case RF_PATH_AB:
+ EndPath = RF_PATH_B;
break;
- case ODM_RF_PATH_BC:
- StartPath = ODM_RF_PATH_B;
- EndPath = ODM_RF_PATH_C;
+ case RF_PATH_BC:
+ StartPath = RF_PATH_B;
+ EndPath = RF_PATH_C;
break;
- case ODM_RF_PATH_ABC:
- EndPath = ODM_RF_PATH_C;
+ case RF_PATH_ABC:
+ EndPath = RF_PATH_C;
break;
- case ODM_RF_PATH_BCD:
- StartPath = ODM_RF_PATH_B;
- EndPath = ODM_RF_PATH_D;
+ case RF_PATH_BCD:
+ StartPath = RF_PATH_B;
+ EndPath = RF_PATH_D;
break;
- case ODM_RF_PATH_ABCD:
- EndPath = ODM_RF_PATH_D;
+ case RF_PATH_ABCD:
+ EndPath = RF_PATH_D;
break;
}
for (StartPath; StartPath <= EndPath; StartPath++)
- PHY_SetRFReg(pAdapter, StartPath, LNA_Low_Gain_3, BIT1, 0x0); /* RF LO disabled */
+ phy_set_rf_reg(pAdapter, StartPath, lna_low_gain_3, BIT1, 0x0); /* RF LO disabled */
- PHY_SetBBReg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); /* Enable CCA*/
+ phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); /* Enable CCA*/
if (bEnPMacTx == FALSE)
- hal_mpt_SetOFDMContinuousTx(pAdapter, _FALSE);
+ hal_mpt_SetContinuousTx(pAdapter, _FALSE);
- PHY_SetBBReg(pAdapter, rA_TxScale_Jaguar, bMaskDWord, regIG0); /* 0xC1C[31:21]*/
- PHY_SetBBReg(pAdapter, rB_TxScale_Jaguar, bMaskDWord, regIG1); /* 0xE1C[31:21]*/
- PHY_SetBBReg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord, regIG2); /* 0x181C[31:21]*/
- PHY_SetBBReg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord, regIG3); /* 0x1A1C[31:21]*/
+ phy_set_bb_reg(pAdapter, rA_TxScale_Jaguar, bMaskDWord, regIG0); /* 0xC1C[31:21]*/
+ phy_set_bb_reg(pAdapter, rB_TxScale_Jaguar, bMaskDWord, regIG1); /* 0xE1C[31:21]*/
+ phy_set_bb_reg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord, regIG2); /* 0x181C[31:21]*/
+ phy_set_bb_reg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord, regIG3); /* 0x1A1C[31:21]*/
}
}
@@ -913,37 +954,37 @@ mpt_SetSingleTone_8814A(
void mpt_SetRFPath_8812A(PADAPTER pAdapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
- PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx;
+ PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.mpt_ctx;
struct mp_priv *pmp = &pAdapter->mppriv;
u8 channel = pmp->channel;
u8 bandwidth = pmp->bandwidth;
u8 eLNA_2g = pHalData->ExternalLNA_2G;
u32 ulAntennaTx, ulAntennaRx;
- ulAntennaTx = pHalData->AntennaTxPath;
+ ulAntennaTx = pHalData->antenna_tx_path;
ulAntennaRx = pHalData->AntennaRxPath;
switch (ulAntennaTx) {
case ANTENNA_A:
- pMptCtx->MptRfPath = ODM_RF_PATH_A;
- PHY_SetBBReg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x1111);
- if (pHalData->RFEType == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
- PHY_SetBBReg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);
+ pMptCtx->mpt_rf_path = RF_PATH_A;
+ phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x1111);
+ if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
+ phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);
break;
case ANTENNA_B:
- pMptCtx->MptRfPath = ODM_RF_PATH_B;
- PHY_SetBBReg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x2222);
- if (pHalData->RFEType == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
- PHY_SetBBReg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x1);
+ pMptCtx->mpt_rf_path = RF_PATH_B;
+ phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x2222);
+ if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
+ phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x1);
break;
case ANTENNA_AB:
- pMptCtx->MptRfPath = ODM_RF_PATH_AB;
- PHY_SetBBReg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x3333);
- if (pHalData->RFEType == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
- PHY_SetBBReg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);
+ pMptCtx->mpt_rf_path = RF_PATH_AB;
+ phy_set_bb_reg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x3333);
+ if (pHalData->rfe_type == 3 && IS_HARDWARE_TYPE_8812(pAdapter))
+ phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0);
break;
default:
- pMptCtx->MptRfPath = ODM_RF_PATH_AB;
+ pMptCtx->mpt_rf_path = RF_PATH_AB;
RTW_INFO("Unknown Tx antenna.\n");
break;
}
@@ -951,15 +992,15 @@ void mpt_SetRFPath_8812A(PADAPTER pAdapter)
switch (ulAntennaRx) {
u32 reg0xC50 = 0;
case ANTENNA_A:
- PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
- PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3);
+ phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
+ phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/
+ phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
+ phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3);
/*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/
- reg0xC50 = PHY_QueryBBReg(pAdapter, rA_IGI_Jaguar, bMaskByte0);
- PHY_SetBBReg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50 + 2);
- PHY_SetBBReg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50);
+ reg0xC50 = phy_query_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0);
+ phy_set_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50 + 2);
+ phy_set_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50);
/* set PWED_TH for BB Yn user guide R29 */
if (IS_HARDWARE_TYPE_8812(pAdapter)) {
@@ -967,25 +1008,25 @@ void mpt_SetRFPath_8812A(PADAPTER pAdapter)
if (bandwidth == CHANNEL_WIDTH_20
&& eLNA_2g == 0) {
/* 0x830[3:1]=3'b010 */
- PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02);
+ phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02);
} else
/* 0x830[3:1]=3'b100 */
- PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
+ phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
} else
/* 0x830[3:1]=3'b100 for 5G */
- PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
+ phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
}
break;
case ANTENNA_B:
- PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1);/*/ RF_A_0x0[19:16] = 1, Standby mode */
- PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x1);
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3);
+ phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22);
+ phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1);/*/ RF_A_0x0[19:16] = 1, Standby mode */
+ phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x1);
+ phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, BIT19 | BIT18 | BIT17 | BIT16, 0x3);
/*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/
- reg0xC50 = PHY_QueryBBReg(pAdapter, rB_IGI_Jaguar, bMaskByte0);
- PHY_SetBBReg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50 + 2);
- PHY_SetBBReg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50);
+ reg0xC50 = phy_query_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0);
+ phy_set_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50 + 2);
+ phy_set_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50);
/* set PWED_TH for BB Yn user guide R29 */
if (IS_HARDWARE_TYPE_8812(pAdapter)) {
@@ -993,27 +1034,38 @@ void mpt_SetRFPath_8812A(PADAPTER pAdapter)
if (bandwidth == CHANNEL_WIDTH_20
&& eLNA_2g == 0) {
/* 0x830[3:1]=3'b010 */
- PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02);
+ phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x02);
} else
/* 0x830[3:1]=3'b100 */
- PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
+ phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
} else
/* 0x830[3:1]=3'b100 for 5G */
- PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
+ phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
}
break;
case ANTENNA_AB:
- PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x33);
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, Rx mode*/
- PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
+ phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x33);
+ phy_set_rf_reg(pAdapter, RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, Rx mode*/
+ phy_set_bb_reg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0);
/* set PWED_TH for BB Yn user guide R29 */
- PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
+ phy_set_bb_reg(pAdapter, rPwed_TH_Jaguar, BIT1 | BIT2 | BIT3, 0x04);
break;
default:
RTW_INFO("Unknown Rx antenna.\n");
break;
}
- RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n"));
+
+ if (pHalData->rfe_type == 5 || pHalData->rfe_type == 1) {
+ if (ulAntennaTx == ANTENNA_A || ulAntennaTx == ANTENNA_AB) {
+ /* WiFi */
+ phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(1) | BIT(0), 0x2);
+ phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(9) | BIT(8), 0x3);
+ } else {
+ /* BT */
+ phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(1) | BIT(0), 0x1);
+ phy_set_bb_reg(pAdapter, r_ANTSEL_SW_Jaguar, BIT(9) | BIT(8), 0x3);
+ }
+ }
}
#endif
@@ -1022,14 +1074,14 @@ void mpt_SetRFPath_8723B(PADAPTER pAdapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
u32 ulAntennaTx, ulAntennaRx;
- PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
- PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
- PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
+ PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
+ struct dm_struct *pDM_Odm = &pHalData->odmpriv;
+ struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
- ulAntennaTx = pHalData->AntennaTxPath;
+ ulAntennaTx = pHalData->antenna_tx_path;
ulAntennaRx = pHalData->AntennaRxPath;
- if (pHalData->rf_chip >= RF_TYPE_MAX) {
+ if (pHalData->rf_chip >= RF_CHIP_MAX) {
RTW_INFO("This RF chip ID is not supported\n");
return;
}
@@ -1037,31 +1089,25 @@ void mpt_SetRFPath_8723B(PADAPTER pAdapter)
switch (pAdapter->mppriv.antenna_tx) {
u8 p = 0, i = 0;
case ANTENNA_A: { /*/ Actually path S1 (Wi-Fi)*/
- pMptCtx->MptRfPath = ODM_RF_PATH_A;
- PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0);
- PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
-
- /*/<20130522, Kordan> 0x51 and 0x71 should be set immediately after path switched, or they might be overwritten.*/
- if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90))
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E);
- else
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E);
+ pMptCtx->mpt_rf_path = RF_PATH_A;
+ phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0);
+ phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
for (i = 0; i < 3; ++i) {
- u4Byte offset = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_A][i][0];
- u4Byte data = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_A][i][1];
+ u4Byte offset = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][0];
+ u4Byte data = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][1];
if (offset != 0) {
- PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
+ phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
RTW_INFO("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);
}
}
for (i = 0; i < 2; ++i) {
- u4Byte offset = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_A][i][0];
- u4Byte data = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_A][i][1];
+ u4Byte offset = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][0];
+ u4Byte data = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][1];
if (offset != 0) {
- PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
+ phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
RTW_INFO("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
}
}
@@ -1071,41 +1117,34 @@ void mpt_SetRFPath_8723B(PADAPTER pAdapter)
u4Byte offset;
u4Byte data;
- pMptCtx->MptRfPath = ODM_RF_PATH_B;
- PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5);
- PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x1); /*/ AGC Table Sel.*/
- /* <20130522, Kordan> 0x51 and 0x71 should be set immediately after path switched, or they might be overwritten.*/
- if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90))
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E);
- else
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E);
+ pMptCtx->mpt_rf_path = RF_PATH_B;
+ phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5);
+ phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x1); /*/ AGC Table Sel.*/
for (i = 0; i < 3; ++i) {
/*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/
- offset = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_A][i][0];
- data = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_B][i][1];
- if (pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_B][i][0] != 0) {
- PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
+ offset = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_A][i][0];
+ data = pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_B][i][1];
+ if (pRFCalibrateInfo->tx_iqc_8723b[RF_PATH_B][i][0] != 0) {
+ phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
RTW_INFO("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
}
}
/*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/
for (i = 0; i < 2; ++i) {
- offset = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_A][i][0];
- data = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_B][i][1];
- if (pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_B][i][0] != 0) {
- PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
+ offset = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_A][i][0];
+ data = pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_B][i][1];
+ if (pRFCalibrateInfo->rx_iqc_8723b[RF_PATH_B][i][0] != 0) {
+ phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
RTW_INFO("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
}
}
}
break;
default:
- pMptCtx->MptRfPath = RF_PATH_AB;
- RT_TRACE(_module_mp_, _drv_notice_, ("Unknown Tx antenna.\n"));
+ pMptCtx->mpt_rf_path = RF_PATH_AB;
break;
}
- RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n"));
}
#endif
@@ -1114,14 +1153,14 @@ void mpt_SetRFPath_8703B(PADAPTER pAdapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
u4Byte ulAntennaTx, ulAntennaRx;
- PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
- PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
- PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
+ PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
+ struct dm_struct *pDM_Odm = &pHalData->odmpriv;
+ struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
- ulAntennaTx = pHalData->AntennaTxPath;
+ ulAntennaTx = pHalData->antenna_tx_path;
ulAntennaRx = pHalData->AntennaRxPath;
- if (pHalData->rf_chip >= RF_TYPE_MAX) {
+ if (pHalData->rf_chip >= RF_CHIP_MAX) {
RTW_INFO("This RF chip ID is not supported\n");
return;
}
@@ -1130,63 +1169,61 @@ void mpt_SetRFPath_8703B(PADAPTER pAdapter)
u1Byte p = 0, i = 0;
case ANTENNA_A: { /* Actually path S1 (Wi-Fi) */
- pMptCtx->MptRfPath = ODM_RF_PATH_A;
- PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0);
- PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
+ pMptCtx->mpt_rf_path = RF_PATH_A;
+ phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x0);
+ phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/
for (i = 0; i < 3; ++i) {
- u4Byte offset = pRFCalibrateInfo->TxIQC_8703B[i][0];
- u4Byte data = pRFCalibrateInfo->TxIQC_8703B[i][1];
+ u4Byte offset = pRFCalibrateInfo->tx_iqc_8703b[i][0];
+ u4Byte data = pRFCalibrateInfo->tx_iqc_8703b[i][1];
if (offset != 0) {
- PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
+ phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
RTW_INFO("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);
}
}
for (i = 0; i < 2; ++i) {
- u4Byte offset = pRFCalibrateInfo->RxIQC_8703B[i][0];
- u4Byte data = pRFCalibrateInfo->RxIQC_8703B[i][1];
+ u4Byte offset = pRFCalibrateInfo->rx_iqc_8703b[i][0];
+ u4Byte data = pRFCalibrateInfo->rx_iqc_8703b[i][1];
if (offset != 0) {
- PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
+ phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
RTW_INFO("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
}
}
}
break;
case ANTENNA_B: { /* Actually path S0 (BT)*/
- pMptCtx->MptRfPath = ODM_RF_PATH_B;
- PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5);
- PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x1); /* AGC Table Sel */
+ pMptCtx->mpt_rf_path = RF_PATH_B;
+ phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5);
+ phy_set_bb_reg(pAdapter, 0xB2C, BIT31, 0x1); /* AGC Table Sel */
for (i = 0; i < 3; ++i) {
- u4Byte offset = pRFCalibrateInfo->TxIQC_8703B[i][0];
- u4Byte data = pRFCalibrateInfo->TxIQC_8703B[i][1];
+ u4Byte offset = pRFCalibrateInfo->tx_iqc_8703b[i][0];
+ u4Byte data = pRFCalibrateInfo->tx_iqc_8703b[i][1];
- if (pRFCalibrateInfo->TxIQC_8703B[i][0] != 0) {
- PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
+ if (pRFCalibrateInfo->tx_iqc_8703b[i][0] != 0) {
+ phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
RTW_INFO("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
}
}
for (i = 0; i < 2; ++i) {
- u4Byte offset = pRFCalibrateInfo->RxIQC_8703B[i][0];
- u4Byte data = pRFCalibrateInfo->RxIQC_8703B[i][1];
+ u4Byte offset = pRFCalibrateInfo->rx_iqc_8703b[i][0];
+ u4Byte data = pRFCalibrateInfo->rx_iqc_8703b[i][1];
- if (pRFCalibrateInfo->RxIQC_8703B[i][0] != 0) {
- PHY_SetBBReg(pAdapter, offset, bMaskDWord, data);
+ if (pRFCalibrateInfo->rx_iqc_8703b[i][0] != 0) {
+ phy_set_bb_reg(pAdapter, offset, bMaskDWord, data);
RTW_INFO("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
}
}
}
break;
default:
- pMptCtx->MptRfPath = RF_PATH_AB;
- RT_TRACE(_module_mp_, _drv_notice_, ("Unknown Tx antenna.\n"));
+ pMptCtx->mpt_rf_path = RF_PATH_AB;
break;
}
- RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n"));
}
#endif
@@ -1196,14 +1233,14 @@ void mpt_SetRFPath_8723D(PADAPTER pAdapter)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
u1Byte p = 0, i = 0;
u4Byte ulAntennaTx, ulAntennaRx, offset = 0, data = 0, val32 = 0;
- PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
- PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
- PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
+ PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
+ struct dm_struct *pDM_Odm = &pHalData->odmpriv;
+ struct dm_rf_calibration_struct *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info);
- ulAntennaTx = pHalData->AntennaTxPath;
+ ulAntennaTx = pHalData->antenna_tx_path;
ulAntennaRx = pHalData->AntennaRxPath;
- if (pHalData->rf_chip >= RF_TYPE_MAX) {
+ if (pHalData->rf_chip >= RF_CHIP_MAX) {
RTW_INFO("This RF chip ID is not supported\n");
return;
}
@@ -1211,101 +1248,28 @@ void mpt_SetRFPath_8723D(PADAPTER pAdapter)
switch (pAdapter->mppriv.antenna_tx) {
/* Actually path S1 (Wi-Fi) */
case ANTENNA_A: {
- pMptCtx->MptRfPath = ODM_RF_PATH_A;
- PHY_SetBBReg(pAdapter, rS0S1_PathSwitch,
- BIT9 | BIT8 | BIT7, 0x0);
- /* AGC Table Sel */
- PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x0);
-
- /*<20130522, Kordan> 0x51 and 0x71 should be set immediately
- after path switched, or they might be overwritten.*/
- if ((pHalData->PackageType == PACKAGE_TFBGA79) ||
- (pHalData->PackageType == PACKAGE_TFBGA90))
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A,
- 0x51, bRFRegOffsetMask, 0x6B10E);
- else
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A,
- 0x51, bRFRegOffsetMask, 0x6B04E);
-
-
- for (i = 0; i < 3; ++i) {
- offset = pRFCalibrateInfo->TxIQC_8723D[RF_PATH_A][i][0];
- data = pRFCalibrateInfo->TxIQC_8723D[RF_PATH_A][i][1];
- if (offset != 0) {
- PHY_SetBBReg(pAdapter, offset,
- bMaskDWord, data);
- RTW_INFO("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data);
- }
-
- }
- for (i = 0; i < 2; ++i) {
- offset = pRFCalibrateInfo->RxIQC_8723D[RF_PATH_A][i][0];
- data = pRFCalibrateInfo->RxIQC_8723D[RF_PATH_A][i][1];
- if (offset != 0) {
- PHY_SetBBReg(pAdapter, offset,
- bMaskDWord, data);
- RTW_INFO("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
- }
- }
+ pMptCtx->mpt_rf_path = RF_PATH_A;
+ phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7|BIT6, 0);
}
break;
/* Actually path S0 (BT) */
case ANTENNA_B: {
- pMptCtx->MptRfPath = ODM_RF_PATH_B;
- PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9 | BIT8 | BIT7, 0x5);
- /* AGC Table Sel */
- PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x1);
- /* <20130522, Kordan> 0x51 and 0x71 should be set immediately
- after path switched, or they might be overwritten.*/
- if ((pHalData->PackageType == PACKAGE_TFBGA79) ||
- (pHalData->PackageType == PACKAGE_TFBGA90))
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51,
- bRFRegOffsetMask, 0x6B10E);
- else
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51,
- bRFRegOffsetMask, 0x6B04E);
-
-
- for (i = 0; i < 3; ++i) {
- /* <20130603, Kordan> Because BB suppors only 1T1R,
- we restore IQC to S1 instead of S0.*/
- offset = pRFCalibrateInfo->TxIQC_8723D[RF_PATH_A][i][0];
- data = pRFCalibrateInfo->TxIQC_8723D[RF_PATH_B][i][1];
- val32 = pRFCalibrateInfo->TxIQC_8723D[RF_PATH_B][i][0];
- if (val32 != 0) {
- PHY_SetBBReg(pAdapter, offset,
- bMaskDWord, data);
- RTW_INFO("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
- }
- }
- for (i = 0; i < 2; ++i) {
- /* <20130603, Kordan> Because BB suppors only 1T1R, we restore
- * IQC to S1 instead of S0.*/
- offset = pRFCalibrateInfo->RxIQC_8723D[RF_PATH_A][i][0];
- data = pRFCalibrateInfo->RxIQC_8723D[RF_PATH_B][i][1];
- val32 = pRFCalibrateInfo->RxIQC_8723D[RF_PATH_B][i][0];
- if (val32 != 0) {
- PHY_SetBBReg(pAdapter, offset,
- bMaskDWord, data);
- RTW_INFO("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data);
- }
- }
+ pMptCtx->mpt_rf_path = RF_PATH_B;
+ phy_set_bb_reg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7|BIT6, 0xA);
}
break;
default:
- pMptCtx->MptRfPath = RF_PATH_AB;
- RT_TRACE(_module_mp_, _drv_notice_, ("Unknown Tx antenna.\n"));
+ pMptCtx->mpt_rf_path = RF_PATH_AB;
break;
}
- RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n"));
}
#endif
VOID mpt_SetRFPath_819X(PADAPTER pAdapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
- PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
+ PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
u4Byte ulAntennaTx, ulAntennaRx;
R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */
R_ANTENNA_SELECT_CCK *p_cck_txrx;
@@ -1313,7 +1277,7 @@ VOID mpt_SetRFPath_819X(PADAPTER pAdapter)
u1Byte chgTx = 0, chgRx = 0;
u4Byte r_ant_sel_cck_val = 0, r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0;
- ulAntennaTx = pHalData->AntennaTxPath;
+ ulAntennaTx = pHalData->antenna_tx_path;
ulAntennaRx = pHalData->AntennaRxPath;
p_ofdm_tx = (R_ANTENNA_SELECT_OFDM *)&r_ant_select_ofdm_val;
@@ -1335,21 +1299,21 @@ VOID mpt_SetRFPath_819X(PADAPTER pAdapter)
/*/ From SD3 Willis suggestion !!! Set RF A=TX and B as standby*/
/*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
{
- PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
- PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);
+ phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
+ phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);
r_ofdm_tx_en_val = 0x3;
/*/ Power save*/
/*/cosa r_ant_select_ofdm_val = 0x11111111;*/
/*/ We need to close RFB by SW control*/
if (pHalData->rf_type == RF_2T2R) {
- PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
- PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1);
- PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);
- PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
- PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0);
+ phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
+ phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1);
+ phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);
+ phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
+ phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0);
}
}
- pMptCtx->MptRfPath = ODM_RF_PATH_A;
+ pMptCtx->mpt_rf_path = RF_PATH_A;
break;
case ANTENNA_B:
p_ofdm_tx->r_tx_antenna = 0x2;
@@ -1362,21 +1326,21 @@ VOID mpt_SetRFPath_819X(PADAPTER pAdapter)
/*/ From SD3 Willis suggestion !!! Set RF A as standby*/
/*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
{
- PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
- PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
+ phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
+ phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
/*/ 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table.*/
/*/ 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control*/
if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R) {
- PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1);
- PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0);
- PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
- /*/PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/
- PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 0);
- PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
+ phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1);
+ phy_set_bb_reg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0);
+ phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
+ /*/phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/
+ phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 0);
+ phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
}
}
- pMptCtx->MptRfPath = ODM_RF_PATH_B;
+ pMptCtx->mpt_rf_path = RF_PATH_B;
break;
case ANTENNA_AB:/*/ For 8192S*/
p_ofdm_tx->r_tx_antenna = 0x3;
@@ -1389,21 +1353,21 @@ VOID mpt_SetRFPath_819X(PADAPTER pAdapter)
/*/ From SD3Willis suggestion !!! Set RF B as standby*/
/*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/
{
- PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
- PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
+ phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
+ phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
/* Disable Power save*/
/*cosa r_ant_select_ofdm_val = 0x3321333;*/
/* 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control*/
if (pHalData->rf_type == RF_2T2R) {
- PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
+ phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
- PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
- /*/PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/
- PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
- PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
+ phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
+ /*/phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/
+ phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
+ phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
}
}
- pMptCtx->MptRfPath = ODM_RF_PATH_AB;
+ pMptCtx->mpt_rf_path = RF_PATH_AB;
break;
default:
break;
@@ -1443,15 +1407,15 @@ VOID mpt_SetRFPath_819X(PADAPTER pAdapter)
case RF_8256:
case RF_6052:
/*/r_ant_sel_cck_val = r_ant_select_cck_val;*/
- PHY_SetBBReg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val); /*/OFDM Tx*/
- PHY_SetBBReg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val); /*/OFDM Tx*/
- PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /*/OFDM Rx*/
- PHY_SetBBReg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /*/OFDM Rx*/
+ phy_set_bb_reg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val); /*/OFDM Tx*/
+ phy_set_bb_reg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val); /*/OFDM Tx*/
+ phy_set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /*/OFDM Rx*/
+ phy_set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /*/OFDM Rx*/
if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
- PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm); /*/OFDM Rx*/
- PHY_SetBBReg(pAdapter, rOFDM1_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm); /*/OFDM Rx*/
+ phy_set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm); /*/OFDM Rx*/
+ phy_set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm); /*/OFDM Rx*/
}
- PHY_SetBBReg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val);/*/r_ant_sel_cck_val); /CCK TxRx*/
+ phy_set_bb_reg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val);/*/r_ant_sel_cck_val); /CCK TxRx*/
break;
default:
@@ -1525,13 +1489,11 @@ s32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther)
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
if (!netif_running(pAdapter->pnetdev)) {
- RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter! Fail: interface not opened!\n"));
return _FAIL;
}
if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
- RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter: Fail! not in MP mode!\n"));
return _FAIL;
}
@@ -1542,7 +1504,7 @@ s32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther)
else if (target_ther > 0x1d)
target_ther = 0x1d;
- pHalData->EEPROMThermalMeter = target_ther;
+ pHalData->eeprom_thermal_meter = target_ther;
return _SUCCESS;
}
@@ -1550,7 +1512,7 @@ s32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther)
void hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter)
{
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x42, BIT17 | BIT16, 0x03);
+ phy_set_rf_reg(pAdapter, RF_PATH_A, 0x42, BIT17 | BIT16, 0x03);
}
@@ -1558,11 +1520,24 @@ void hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter)
u8 hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter)
{
+ struct dm_struct *p_dm_odm = adapter_to_phydm(pAdapter);
u32 ThermalValue = 0;
+ s32 thermal_value_temp = 0;
+ s8 thermal_offset = 0;
- ThermalValue = (u1Byte)PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, 0x42, 0xfc00); /*0x42: RF Reg[15:10]*/
- return (u8)ThermalValue;
+ ThermalValue = (u1Byte)phy_query_rf_reg(pAdapter, RF_PATH_A, 0x42, 0xfc00); /*0x42: RF Reg[15:10]*/
+ thermal_offset = phydm_get_thermal_offset(p_dm_odm);
+ thermal_value_temp = ThermalValue + thermal_offset;
+
+ if (thermal_value_temp > 63)
+ ThermalValue = 63;
+ else if (thermal_value_temp < 0)
+ ThermalValue = 0;
+ else
+ ThermalValue = thermal_value_temp;
+
+ return (u8)ThermalValue;
}
@@ -1586,28 +1561,27 @@ void hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
- pAdapter->mppriv.MptCtx.bSingleCarrier = bStart;
+ pAdapter->mppriv.mpt_ctx.bSingleCarrier = bStart;
if (bStart) {/*/ Start Single Carrier.*/
- RT_TRACE(_module_mp_, _drv_alert_, ("SetSingleCarrierTx: test start\n"));
/*/ Start Single Carrier.*/
/*/ 1. if OFDM block on?*/
- if (!PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
- PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1); /*set OFDM block on*/
+ if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
+ phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1); /*set OFDM block on*/
/*/ 2. set CCK test mode off, set to CCK normal mode*/
- PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0);
+ phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0);
/*/ 3. turn on scramble setting*/
- PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 1);
+ phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 1);
/*/ 4. Turn On Continue Tx and turn off the other test modes.*/
#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter))
- PHY_SetBBReg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_SingleCarrier);
+ phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_SingleCarrier);
else
#endif /* CONFIG_RTL8812A || CONFIG_RTL8821A || CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */
- PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleCarrier);
+ phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleCarrier);
} else {
/*/ Stop Single Carrier.*/
@@ -1615,15 +1589,15 @@ void hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
/*/ Turn off all test modes.*/
#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter))
- PHY_SetBBReg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
+ phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
else
#endif /* CONFIG_RTL8812A || CONFIG_RTL8821A || CONFIG_RTL8814A || CONFIG_RTL8822B || CONFIG_RTL8821C */
- PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
+ phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
rtw_msleep_os(10);
/*/BB Reset*/
- PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
- PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
+ phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
+ phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
}
}
@@ -1631,113 +1605,138 @@ void hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
- PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
- u4Byte ulAntennaTx = pHalData->AntennaTxPath;
+ PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
+ struct dm_struct *pDM_Odm = &pHalData->odmpriv;
+ u4Byte ulAntennaTx = pHalData->antenna_tx_path;
static u4Byte regRF = 0, regBB0 = 0, regBB1 = 0, regBB2 = 0, regBB3 = 0;
u8 rfPath;
switch (ulAntennaTx) {
case ANTENNA_B:
- rfPath = ODM_RF_PATH_B;
+ rfPath = RF_PATH_B;
break;
case ANTENNA_C:
- rfPath = ODM_RF_PATH_C;
+ rfPath = RF_PATH_C;
break;
case ANTENNA_D:
- rfPath = ODM_RF_PATH_D;
+ rfPath = RF_PATH_D;
break;
case ANTENNA_A:
default:
- rfPath = ODM_RF_PATH_A;
+ rfPath = RF_PATH_A;
break;
}
- pAdapter->mppriv.MptCtx.bSingleTone = bStart;
+ pAdapter->mppriv.mpt_ctx.is_single_tone = bStart;
if (bStart) {
/*/ Start Single Tone.*/
/*/ <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu)*/
if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
- regRF = PHY_QueryRFReg(pAdapter, rfPath, LNA_Low_Gain_3, bRFRegOffsetMask);
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO enabled*/
- PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0);
- PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0);
+ regRF = phy_query_rf_reg(pAdapter, rfPath, lna_low_gain_3, bRFRegOffsetMask);
+ phy_set_rf_reg(pAdapter, RF_PATH_A, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
+ phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0);
+ phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0);
} else if (IS_HARDWARE_TYPE_8192E(pAdapter)) { /*/ USB need to do RF LO disable first, PCIE isn't required to follow this order.*/
/*/Set MAC REG 88C: Prevent SingleTone Fail*/
- PHY_SetMacReg(pAdapter, 0x88C, 0xF00000, 0xF);
- PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO disabled*/
- PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
+ phy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0xF);
+ phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO disabled*/
+ phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
} else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
- if (pMptCtx->MptRfPath == ODM_RF_PATH_A) {
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x56, 0xF, 0x1); /*/ RF LO enabled*/
+ if (pMptCtx->mpt_rf_path == RF_PATH_A) {
+ phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
+ phy_set_rf_reg(pAdapter, RF_PATH_A, 0x56, 0xF, 0x1); /*/ RF LO enabled*/
} else {
/*/ S0/S1 both use PATH A to configure*/
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x76, 0xF, 0x1); /*/ RF LO enabled*/
+ phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/
+ phy_set_rf_reg(pAdapter, RF_PATH_A, 0x76, 0xF, 0x1); /*/ RF LO enabled*/
}
} else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
- if (pMptCtx->MptRfPath == ODM_RF_PATH_A) {
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /* Tx mode */
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x53, 0xF000, 0x1); /* RF LO enabled */
+ if (pMptCtx->mpt_rf_path == RF_PATH_A) {
+ phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x2); /* Tx mode */
+ phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, 0xF000, 0x1); /* RF LO enabled */
}
} else if (IS_HARDWARE_TYPE_8188F(pAdapter)) {
/*Set BB REG 88C: Prevent SingleTone Fail*/
- PHY_SetBBReg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xF);
- PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x1);
- PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC, 0xF0000, 0x2);
+ phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xF);
+ phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1);
+ phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2);
} else if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
- if (pMptCtx->MptRfPath == ODM_RF_PATH_A) {
- PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0);
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x0);
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x53, BIT0, 0x1);
+ if (pMptCtx->mpt_rf_path == RF_PATH_A) {
+ phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0);
+ phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x0);
+ phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, BIT0, 0x1);
} else {/* S0/S1 both use PATH A to configure */
- PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0);
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x0);
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x63, BIT0, 0x1);
+ phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0);
+ phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x0);
+ phy_set_rf_reg(pAdapter, RF_PATH_A, 0x63, BIT0, 0x1);
}
- } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter)) {
+ } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) {
#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
- u1Byte p = ODM_RF_PATH_A;
+ u1Byte p = RF_PATH_A;
- regRF = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, bRFRegOffsetMask);
- regBB0 = PHY_QueryBBReg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord);
- regBB1 = PHY_QueryBBReg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord);
- regBB2 = PHY_QueryBBReg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord);
- regBB3 = PHY_QueryBBReg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord);
+ regRF = phy_query_rf_reg(pAdapter, RF_PATH_A, RF_AC_Jaguar, bRFRegOffsetMask);
+ regBB0 = phy_query_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord);
+ regBB1 = phy_query_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord);
+ regBB2 = phy_query_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord);
+ regBB3 = phy_query_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord);
- PHY_SetBBReg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x0); /*/ Disable CCK and OFDM*/
+ phy_set_bb_reg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x0); /*/ Disable CCK and OFDM*/
- if (pMptCtx->MptRfPath == ODM_RF_PATH_AB) {
- for (p = ODM_RF_PATH_A; p <= ODM_RF_PATH_B; ++p) {
- PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
- PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
- PHY_SetRFReg(pAdapter, p, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO enabled*/
+ if (pMptCtx->mpt_rf_path == RF_PATH_AB) {
+ for (p = RF_PATH_A; p <= RF_PATH_B; ++p) {
+ phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
+ phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
+ phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
}
} else {
- PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
- PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
- PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO enabled*/
+ phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */
+ phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/
+#ifdef CONFIG_RTL8821C
+ if (IS_HARDWARE_TYPE_8821C(pAdapter) && pDM_Odm->current_rf_set_8821c == SWITCH_TO_BTG)
+ phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, 0x75, BIT16, 0x1); /* RF LO (for BTG) enabled */
+ else
+#endif
+ phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/
}
-
- PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/
- PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/
-
- if (pHalData->ExternalPA_5G) {
- PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xCB4[23:16] = 0x12*/
- PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xEB4[23:16] = 0x12*/
- } else if (pHalData->ExternalPA_2G) {
- PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xCB4[23:16] = 0x11*/
- PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xEB4[23:16] = 0x11*/
+ if (IS_HARDWARE_TYPE_8822B(pAdapter)) {
+ phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, 0x77777777); /* 0xCB0=0x77777777*/
+ phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, 0x77777777); /* 0xEB0=0x77777777*/
+ phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskLWord, 0x7777); /* 0xCB4[15:0] = 0x7777*/
+ phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskLWord, 0x7777); /* 0xEB4[15:0] = 0x7777*/
+ phy_set_bb_reg(pAdapter, rA_RFE_Inverse_Jaguar, 0xFFF, 0xb); /* 0xCBC[23:16] = 0x12*/
+ phy_set_bb_reg(pAdapter, rB_RFE_Inverse_Jaguar, 0xFFF, 0x830); /* 0xEBC[23:16] = 0x12*/
+ } else if (IS_HARDWARE_TYPE_8821C(pAdapter)) {
+ phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xF0F0, 0x707); /* 0xCB0[[15:12, 7:4] = 0x707*/
+
+ if (pHalData->external_pa_5g)
+ {
+ phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xA00000, 0x1); /* 0xCB4[23, 21] = 0x1*/
+ }
+ else if (pHalData->ExternalPA_2G)
+ {
+ phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xA00000, 0x1); /* 0xCB4[23, 21] = 0x1*/
+ }
+ } else {
+ phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/
+ phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/
+
+ if (pHalData->external_pa_5g) {
+ phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xCB4[23:16] = 0x12*/
+ phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x12); /*/ 0xEB4[23:16] = 0x12*/
+ } else if (pHalData->ExternalPA_2G) {
+ phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xCB4[23:16] = 0x11*/
+ phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, 0xFF00000, 0x11); /*/ 0xEB4[23:16] = 0x11*/
+ }
}
#endif
}
-#ifdef CONFIG_RTL8814A
- else if (IS_HARDWARE_TYPE_8814A(pAdapter))
- mpt_SetSingleTone_8814A(pAdapter, TRUE, FALSE);
+#if defined(CONFIG_RTL8814A)
+ else if (IS_HARDWARE_TYPE_8814A(pAdapter))
+ mpt_SetSingleTone_8814A(pAdapter, TRUE, FALSE);
#endif
else /*/ Turn On SingleTone and turn off the other test modes.*/
- PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleTone);
+ phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleTone);
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
@@ -1745,71 +1744,82 @@ void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
} else {/*/ Stop Single Ton e.*/
if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask, regRF);
- PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1);
- PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
+ phy_set_rf_reg(pAdapter, RF_PATH_A, lna_low_gain_3, bRFRegOffsetMask, regRF);
+ phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1);
+ phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
} else if (IS_HARDWARE_TYPE_8192E(pAdapter)) {
- PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC, 0xF0000, 0x3);/*/ Tx mode*/
- PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x0);/*/ RF LO disabled */
+ phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3);/*/ Tx mode*/
+ phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0);/*/ RF LO disabled */
/*/ RESTORE MAC REG 88C: Enable RF Functions*/
- PHY_SetMacReg(pAdapter, 0x88C, 0xF00000, 0x0);
+ phy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0x0);
} else if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
- if (pMptCtx->MptRfPath == ODM_RF_PATH_A) {
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x56, 0xF, 0x0); /*/ RF LO disabled*/
+ if (pMptCtx->mpt_rf_path == RF_PATH_A) {
+ phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
+ phy_set_rf_reg(pAdapter, RF_PATH_A, 0x56, 0xF, 0x0); /*/ RF LO disabled*/
} else {
/*/ S0/S1 both use PATH A to configure*/
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x76, 0xF, 0x0); /*/ RF LO disabled*/
+ phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/
+ phy_set_rf_reg(pAdapter, RF_PATH_A, 0x76, 0xF, 0x0); /*/ RF LO disabled*/
}
} else if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
- if (pMptCtx->MptRfPath == ODM_RF_PATH_A) {
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /* Rx mode */
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x53, 0xF000, 0x0); /* RF LO disabled */
+ if (pMptCtx->mpt_rf_path == RF_PATH_A) {
+ phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, 0xF0000, 0x3); /* Rx mode */
+ phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, 0xF000, 0x0); /* RF LO disabled */
}
} else if (IS_HARDWARE_TYPE_8188F(pAdapter)) {
- PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC, 0xF0000, 0x3); /*Tx mode*/
- PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x0); /*RF LO disabled*/
+ phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3); /*Tx mode*/
+ phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0); /*RF LO disabled*/
/*Set BB REG 88C: Prevent SingleTone Fail*/
- PHY_SetBBReg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xc);
+ phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xc);
} else if (IS_HARDWARE_TYPE_8723D(pAdapter)) {
- if (pMptCtx->MptRfPath == ODM_RF_PATH_A) {
- PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3);
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x1);
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x53, BIT0, 0x0);
+ if (pMptCtx->mpt_rf_path == RF_PATH_A) {
+ phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3);
+ phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x1);
+ phy_set_rf_reg(pAdapter, RF_PATH_A, 0x53, BIT0, 0x0);
} else { /* S0/S1 both use PATH A to configure */
- PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3);
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x1);
- PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x63, BIT0, 0x0);
+ phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3);
+ phy_set_rf_reg(pAdapter, RF_PATH_A, RF_AC, BIT16, 0x1);
+ phy_set_rf_reg(pAdapter, RF_PATH_A, 0x63, BIT0, 0x0);
}
- } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter)) {
+ } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) {
#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
- u1Byte p = ODM_RF_PATH_A;
+ u1Byte p = RF_PATH_A;
- PHY_SetBBReg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x3); /*/ Disable CCK and OFDM*/
+ phy_set_bb_reg(pAdapter, rOFDMCCKEN_Jaguar, BIT29 | BIT28, 0x3); /*/ Disable CCK and OFDM*/
- if (pMptCtx->MptRfPath == ODM_RF_PATH_AB) {
- for (p = ODM_RF_PATH_A; p <= ODM_RF_PATH_B; ++p) {
- PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);
- PHY_SetRFReg(pAdapter, p, LNA_Low_Gain_3, BIT1, 0x0); /*/ RF LO disabled*/
+ if (pMptCtx->mpt_rf_path == RF_PATH_AB) {
+ for (p = RF_PATH_A; p <= RF_PATH_B; ++p) {
+ phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);
+ phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x0); /*/ RF LO disabled*/
}
} else {
- PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);
- PHY_SetRFReg(pAdapter, p, LNA_Low_Gain_3, BIT1, 0x0); /*/ RF LO disabled*/
+ p = pMptCtx->mpt_rf_path;
+ phy_set_rf_reg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF);
+
+ if (IS_HARDWARE_TYPE_8821C(pAdapter))
+ phy_set_rf_reg(pAdapter, p, 0x75, BIT16, 0x0); /* RF LO (for BTG) disabled */
+
+ phy_set_rf_reg(pAdapter, p, lna_low_gain_3, BIT1, 0x0); /*/ RF LO disabled*/
}
- PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, regBB0);
- PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, regBB1);
- PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB2);
- PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB3);
+ phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, regBB0);
+ phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, regBB1);
+ phy_set_bb_reg(pAdapter, rA_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB2);
+ phy_set_bb_reg(pAdapter, rB_RFE_Pinmux_Jaguar + 4, bMaskDWord, regBB3);
+
+ if (IS_HARDWARE_TYPE_8822B(pAdapter)) {
+ RTW_INFO("Restore RFE control Pin cbc\n");
+ phy_set_bb_reg(pAdapter, rA_RFE_Inverse_Jaguar, 0xfff, 0x0);
+ phy_set_bb_reg(pAdapter, rB_RFE_Inverse_Jaguar, 0xfff, 0x0);
+ }
#endif
}
-#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
+#if defined(CONFIG_RTL8814A)
else if (IS_HARDWARE_TYPE_8814A(pAdapter))
mpt_SetSingleTone_8814A(pAdapter, FALSE, FALSE);
else/*/ Turn off all test modes.*/
- PHY_SetBBReg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
+ phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
#endif
write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
@@ -1821,11 +1831,10 @@ void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
{
u8 Rate;
- pAdapter->mppriv.MptCtx.bCarrierSuppression = bStart;
+ pAdapter->mppriv.mpt_ctx.is_carrier_suppression = bStart;
Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx);
if (bStart) {/* Start Carrier Suppression.*/
- RT_TRACE(_module_mp_, _drv_alert_, ("SetCarrierSuppressionTx: test start\n"));
if (Rate <= MPT_RATE_11M) {
/*/ 1. if CCK block on?*/
if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
@@ -1833,9 +1842,9 @@ void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
/*/Turn Off All Test Mode*/
if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter) /*|| IS_HARDWARE_TYPE_8822B(pAdapter)*/)
- PHY_SetBBReg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); /* rSingleTone_ContTx_Jaguar*/
+ phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); /* rSingleTone_ContTx_Jaguar*/
else
- PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
+ phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*/transmit mode*/
write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0); /*/turn off scramble setting*/
@@ -1849,7 +1858,6 @@ void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
} else {/* Stop Carrier Suppression.*/
- RT_TRACE(_module_mp_, _drv_alert_, ("SetCarrierSuppressionTx: test stop\n"));
if (Rate <= MPT_RATE_11M) {
write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*normal mode*/
@@ -1866,148 +1874,16 @@ void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
RTW_INFO("\n MPT_ProSetCarrierSupp() is finished.\n");
}
-void hal_mpt_SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart)
-{
- u32 cckrate;
-
- if (bStart) {
- RT_TRACE(_module_mp_, _drv_alert_,
- ("SetCCKContinuousTx: test start\n"));
-
- /*/ 1. if CCK block on?*/
- if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
- write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/*set CCK block on*/
-
- /*/Turn Off All Test Mode*/
- if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter))
- PHY_SetBBReg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); /*rSingleTone_ContTx_Jaguar*/
- else
- PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
-
- /*/Set CCK Tx Test Rate*/
-
- cckrate = pAdapter->mppriv.rateidx;
-
- write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
- write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*/transmit mode*/
- write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); /*/turn on scramble setting*/
-
- if (!IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter)) {
- PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x3); /* rCCK0_RxHP 0xa15[1:0] = 11 force cck rxiq = 0*/
- PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /*/ 0xc08[16] = 1 force ofdm rxiq = ofdm txiq*/
- PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 1);
- PHY_SetBBReg(pAdapter, 0x0B34, BIT14, 1);
- }
-
- write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
- write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
-
- } else {
- RT_TRACE(_module_mp_, _drv_info_,
- ("SetCCKContinuousTx: test stop\n"));
-
- write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*/normal mode*/
- write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); /*/turn on scramble setting*/
-
- if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_8814A(pAdapter) /* && !IS_HARDWARE_TYPE_8822B(pAdapter) */) {
- PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x0);/* rCCK0_RxHP 0xa15[1:0] = 2b00*/
- PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /*/ 0xc08[16] = 0*/
- PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 0);
- PHY_SetBBReg(pAdapter, 0x0B34, BIT14, 0);
- }
-
- /*/BB Reset*/
- write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
- write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
-
- write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
- write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
- }
-
- pAdapter->mppriv.MptCtx.bCckContTx = bStart;
- pAdapter->mppriv.MptCtx.bOfdmContTx = _FALSE;
-}
-
-void hal_mpt_SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart)
-{
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
-
- if (bStart) {
- RT_TRACE(_module_mp_, _drv_info_, ("SetOFDMContinuousTx: test start\n"));/*/ 1. if OFDM block on?*/
- if (!PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
- PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1);/*/set OFDM block on*/
-
- /*/ 2. set CCK test mode off, set to CCK normal mode*/
- PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0);
-
- /*/ 3. turn on scramble setting*/
- PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 1);
-
- if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_8814A(pAdapter) /*&& !IS_HARDWARE_TYPE_8822B(pAdapter)*/) {
- PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x3); /* rCCK0_RxHP 0xa15[1:0] = 2b'11*/
- PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1*/
- }
-
- /*/ 4. Turn On Continue Tx and turn off the other test modes.*/
- if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter) /*|| IS_HARDWARE_TYPE_8822B(pAdapter)*/)
- PHY_SetBBReg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ContinuousTx); /*rSingleTone_ContTx_Jaguar*/
- else
- PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ContinuousTx);
-
- write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
- write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
-
- } else {
- RT_TRACE(_module_mp_, _drv_info_, ("SetOFDMContinuousTx: test stop\n"));
- if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter) /*|| IS_HARDWARE_TYPE_8822B(pAdapter)*/)
- PHY_SetBBReg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
- else
- PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
- /*/Delay 10 ms*/
- rtw_msleep_os(10);
-
- if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_8814A(pAdapter) /*&&! IS_HARDWARE_TYPE_8822B(pAdapter)*/) {
- PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x0);/*/ 0xa15[1:0] = 0*/
- PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0);/*/ 0xc08[16] = 0*/
- }
-
- /*/BB Reset*/
- PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
- PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
-
- write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
- write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
- }
-
- pAdapter->mppriv.MptCtx.bCckContTx = _FALSE;
- pAdapter->mppriv.MptCtx.bOfdmContTx = bStart;
-}
-
-void hal_mpt_SetContinuousTx(PADAPTER pAdapter, u8 bStart)
-{
- u8 Rate;
-
- RT_TRACE(_module_mp_, _drv_info_,
- ("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx));
- Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx);
- pAdapter->mppriv.MptCtx.bStartContTx = bStart;
-
- if (Rate <= MPT_RATE_11M)
- hal_mpt_SetCCKContinuousTx(pAdapter, bStart);
- else if (Rate >= MPT_RATE_6M)
- hal_mpt_SetOFDMContinuousTx(pAdapter, bStart);
-}
-
u32 hal_mpt_query_phytxok(PADAPTER pAdapter)
{
- PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
+ PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo;
u16 count = 0;
if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
- count = PHY_QueryBBReg(pAdapter, 0xF50, bMaskLWord); /* [15:0]*/
+ count = phy_query_bb_reg(pAdapter, 0xF50, bMaskLWord); /* [15:0]*/
else
- count = PHY_QueryBBReg(pAdapter, 0xF50, bMaskHWord); /* [31:16]*/
+ count = phy_query_bb_reg(pAdapter, 0xF50, bMaskHWord); /* [31:16]*/
if (count > 50000) {
rtw_reset_phy_trx_ok_counters(pAdapter);
@@ -2019,36 +1895,35 @@ u32 hal_mpt_query_phytxok(PADAPTER pAdapter)
}
-#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8821B) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
-/* for HW TX mode */
static VOID mpt_StopCckContTx(
PADAPTER pAdapter
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
- PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
+ PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
u1Byte u1bReg;
pMptCtx->bCckContTx = FALSE;
pMptCtx->bOfdmContTx = FALSE;
- PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*normal mode*/
- PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/
+ phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*normal mode*/
+ phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/
- if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) {
- PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x0); /* 0xa15[1:0] = 2b00*/
- PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /* 0xc08[16] = 0*/
+ if (!IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) {
+ phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x0); /* 0xa15[1:0] = 2b00*/
+ phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /* 0xc08[16] = 0*/
- PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 0);
- PHY_SetBBReg(pAdapter, 0x0B34, BIT14, 0);
+ phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 0);
+ phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, BIT14, 0);
+ phy_set_bb_reg(pAdapter, 0x0B34, BIT14, 0);
}
/*BB Reset*/
- PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
- PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
+ phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
+ phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
- PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
- PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
+ phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
+ phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
} /* mpt_StopCckContTx */
@@ -2058,7 +1933,7 @@ static VOID mpt_StopOfdmContTx(
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
- PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
+ PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
u1Byte u1bReg;
u4Byte data;
@@ -2066,23 +1941,23 @@ static VOID mpt_StopOfdmContTx(
pMptCtx->bOfdmContTx = FALSE;
if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_JAGUAR2(pAdapter))
- PHY_SetBBReg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
+ phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
else
- PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
+ phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
rtw_mdelay_os(10);
if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) {
- PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x0); /* 0xa15[1:0] = 0*/
- PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /* 0xc08[16] = 0*/
+ phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x0); /* 0xa15[1:0] = 0*/
+ phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /* 0xc08[16] = 0*/
}
/*BB Reset*/
- PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
- PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
+ phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
+ phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
- PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
- PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
+ phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
+ phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
} /* mpt_StopOfdmContTx */
@@ -2091,35 +1966,36 @@ static VOID mpt_StartCckContTx(
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
- PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
+ PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
u4Byte cckrate;
/* 1. if CCK block on */
- if (!PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn))
- PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn, 1);/*set CCK block on*/
+ if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn))
+ phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 1);/*set CCK block on*/
/*Turn Off All Test Mode*/
if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter))
- PHY_SetBBReg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
+ phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF);
else
- PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
+ phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF);
cckrate = pAdapter->mppriv.rateidx;
- PHY_SetBBReg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
+ phy_set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
- PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*transmit mode*/
- PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/
+ phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*transmit mode*/
+ phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/
if (!IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter)) {
- PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x3); /* 0xa15[1:0] = 11 force cck rxiq = 0*/
- PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1 force ofdm rxiq = ofdm txiq*/
- PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 1);
- PHY_SetBBReg(pAdapter, 0x0B34, BIT14, 1);
+ phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x3); /* 0xa15[1:0] = 11 force cck rxiq = 0*/
+ phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1 force ofdm rxiq = ofdm txiq*/
+ phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 1);
+ phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, BIT14, 1);
+ phy_set_bb_reg(pAdapter, 0x0B34, BIT14, 1);
}
- PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
- PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
+ phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
+ phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
pMptCtx->bCckContTx = TRUE;
pMptCtx->bOfdmContTx = FALSE;
@@ -2132,71 +2008,78 @@ static VOID mpt_StartOfdmContTx(
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
- PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
+ PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
/* 1. if OFDM block on?*/
- if (!PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
- PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1);/*set OFDM block on*/
+ if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
+ phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1);/*set OFDM block on*/
/* 2. set CCK test mode off, set to CCK normal mode*/
- PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0);
+ phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0);
/* 3. turn on scramble setting*/
- PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 1);
+ phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 1);
if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) {
- PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x3); /* 0xa15[1:0] = 2b'11*/
- PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1*/
+ phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x3); /* 0xa15[1:0] = 2b'11*/
+ phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1*/
}
/* 4. Turn On Continue Tx and turn off the other test modes.*/
if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_JAGUAR2(pAdapter))
- PHY_SetBBReg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ContinuousTx);
+ phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ContinuousTx);
else
- PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ContinuousTx);
+ phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ContinuousTx);
- PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
- PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
+ phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
+ phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
pMptCtx->bCckContTx = FALSE;
pMptCtx->bOfdmContTx = TRUE;
} /* mpt_StartOfdmContTx */
+#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8821B) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
+/* for HW TX mode */
void mpt_ProSetPMacTx(PADAPTER Adapter)
{
- PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx);
+ PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx);
+ struct mp_priv *pmppriv = &Adapter->mppriv;
RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo;
u32 u4bTmp;
- DbgPrint("SGI %d bSPreamble %d bSTBC %d bLDPC %d NDP_sound %d\n", PMacTxInfo.bSGI, PMacTxInfo.bSPreamble, PMacTxInfo.bSTBC, PMacTxInfo.bLDPC, PMacTxInfo.NDP_sound);
- DbgPrint("TXSC %d BandWidth %d PacketPeriod %d PacketCount %d PacketLength %d PacketPattern %d\n", PMacTxInfo.TX_SC, PMacTxInfo.BandWidth, PMacTxInfo.PacketPeriod, PMacTxInfo.PacketCount,
- PMacTxInfo.PacketLength, PMacTxInfo.PacketPattern);
#if 0
PRINT_DATA("LSIG ", PMacTxInfo.LSIG, 3);
PRINT_DATA("HT_SIG", PMacTxInfo.HT_SIG, 6);
PRINT_DATA("VHT_SIG_A", PMacTxInfo.VHT_SIG_A, 6);
PRINT_DATA("VHT_SIG_B", PMacTxInfo.VHT_SIG_B, 4);
- DbgPrint("VHT_SIG_B_CRC %x\n", PMacTxInfo.VHT_SIG_B_CRC);
+ dbg_print("VHT_SIG_B_CRC %x\n", PMacTxInfo.VHT_SIG_B_CRC);
PRINT_DATA("VHT_Delimiter", PMacTxInfo.VHT_Delimiter, 4);
PRINT_DATA("Src Address", Adapter->mac_addr, 6);
PRINT_DATA("Dest Address", PMacTxInfo.MacAddress, 6);
#endif
+ if (Adapter->mppriv.pktInterval != 0)
+ PMacTxInfo.PacketPeriod = Adapter->mppriv.pktInterval;
+
+ RTW_INFO("SGI %d bSPreamble %d bSTBC %d bLDPC %d NDP_sound %d\n", PMacTxInfo.bSGI, PMacTxInfo.bSPreamble, PMacTxInfo.bSTBC, PMacTxInfo.bLDPC, PMacTxInfo.NDP_sound);
+ RTW_INFO("TXSC %d BandWidth %d PacketPeriod %d PacketCount %d PacketLength %d PacketPattern %d\n", PMacTxInfo.TX_SC, PMacTxInfo.BandWidth, PMacTxInfo.PacketPeriod, PMacTxInfo.PacketCount,
+ PMacTxInfo.PacketLength, PMacTxInfo.PacketPattern);
if (PMacTxInfo.bEnPMacTx == FALSE) {
+ pmppriv->mode = MP_ON;
if (PMacTxInfo.Mode == CONTINUOUS_TX) {
- PHY_SetBBReg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/
+ phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/
if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
mpt_StopCckContTx(Adapter);
else
mpt_StopOfdmContTx(Adapter);
} else if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
- u4bTmp = PHY_QueryBBReg(Adapter, 0xf50, bMaskLWord);
- PHY_SetBBReg(Adapter, 0xb1c, bMaskLWord, u4bTmp + 50);
- PHY_SetBBReg(Adapter, 0xb04, 0xf, 2); /*TX Stop*/
+ u4bTmp = phy_query_bb_reg(Adapter, 0xf50, bMaskLWord);
+ phy_set_bb_reg(Adapter, 0xb1c, bMaskLWord, u4bTmp + 50);
+ phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /*TX Stop*/
} else
- PHY_SetBBReg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/
+ phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/
if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) {
/* Stop HW TX -> Stop Continuous TX -> Stop RF Setting*/
@@ -2212,6 +2095,7 @@ void mpt_ProSetPMacTx(PADAPTER Adapter)
}
if (PMacTxInfo.Mode == CONTINUOUS_TX) {
+ pmppriv->mode = MP_CONTINUOUS_TX;
PMacTxInfo.PacketCount = 1;
if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE))
@@ -2219,6 +2103,7 @@ void mpt_ProSetPMacTx(PADAPTER Adapter)
else
mpt_StartOfdmContTx(Adapter);
} else if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) {
+ pmppriv->mode = MP_SINGLE_TONE_TX;
/* Continuous TX -> HW TX -> RF Setting */
PMacTxInfo.PacketCount = 1;
@@ -2227,6 +2112,7 @@ void mpt_ProSetPMacTx(PADAPTER Adapter)
else
mpt_StartOfdmContTx(Adapter);
} else if (PMacTxInfo.Mode == PACKETS_TX) {
+ pmppriv->mode = MP_PACKET_TX;
if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE) && PMacTxInfo.PacketCount == 0)
PMacTxInfo.PacketCount = 0xffff;
}
@@ -2234,22 +2120,22 @@ void mpt_ProSetPMacTx(PADAPTER Adapter)
if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
/* 0xb1c[0:15] TX packet count 0xb1C[31:16] SFD*/
u4bTmp = PMacTxInfo.PacketCount | (PMacTxInfo.SFD << 16);
- PHY_SetBBReg(Adapter, 0xb1c, bMaskDWord, u4bTmp);
+ phy_set_bb_reg(Adapter, 0xb1c, bMaskDWord, u4bTmp);
/* 0xb40 7:0 SIGNAL 15:8 SERVICE 31:16 LENGTH*/
u4bTmp = PMacTxInfo.SignalField | (PMacTxInfo.ServiceField << 8) | (PMacTxInfo.LENGTH << 16);
- PHY_SetBBReg(Adapter, 0xb40, bMaskDWord, u4bTmp);
+ phy_set_bb_reg(Adapter, 0xb40, bMaskDWord, u4bTmp);
u4bTmp = PMacTxInfo.CRC16[0] | (PMacTxInfo.CRC16[1] << 8);
- PHY_SetBBReg(Adapter, 0xb44, bMaskLWord, u4bTmp);
+ phy_set_bb_reg(Adapter, 0xb44, bMaskLWord, u4bTmp);
if (PMacTxInfo.bSPreamble)
- PHY_SetBBReg(Adapter, 0xb0c, BIT27, 0);
+ phy_set_bb_reg(Adapter, 0xb0c, BIT27, 0);
else
- PHY_SetBBReg(Adapter, 0xb0c, BIT27, 1);
+ phy_set_bb_reg(Adapter, 0xb0c, BIT27, 1);
} else {
- PHY_SetBBReg(Adapter, 0xb18, 0xfffff, PMacTxInfo.PacketCount);
+ phy_set_bb_reg(Adapter, 0xb18, 0xfffff, PMacTxInfo.PacketCount);
u4bTmp = PMacTxInfo.LSIG[0] | ((PMacTxInfo.LSIG[1]) << 8) | ((PMacTxInfo.LSIG[2]) << 16) | ((PMacTxInfo.PacketPattern) << 24);
- PHY_SetBBReg(Adapter, 0xb08, bMaskDWord, u4bTmp); /* Set 0xb08[23:0] = LSIG, 0xb08[31:24] = Data init octet*/
+ phy_set_bb_reg(Adapter, 0xb08, bMaskDWord, u4bTmp); /* Set 0xb08[23:0] = LSIG, 0xb08[31:24] = Data init octet*/
if (PMacTxInfo.PacketPattern == 0x12)
u4bTmp = 0x3000000;
@@ -2259,103 +2145,126 @@ void mpt_ProSetPMacTx(PADAPTER Adapter)
if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE)) {
u4bTmp |= PMacTxInfo.HT_SIG[0] | ((PMacTxInfo.HT_SIG[1]) << 8) | ((PMacTxInfo.HT_SIG[2]) << 16);
- PHY_SetBBReg(Adapter, 0xb0c, bMaskDWord, u4bTmp);
+ phy_set_bb_reg(Adapter, 0xb0c, bMaskDWord, u4bTmp);
u4bTmp = PMacTxInfo.HT_SIG[3] | ((PMacTxInfo.HT_SIG[4]) << 8) | ((PMacTxInfo.HT_SIG[5]) << 16);
- PHY_SetBBReg(Adapter, 0xb10, 0xffffff, u4bTmp);
+ phy_set_bb_reg(Adapter, 0xb10, 0xffffff, u4bTmp);
} else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) {
u4bTmp |= PMacTxInfo.VHT_SIG_A[0] | ((PMacTxInfo.VHT_SIG_A[1]) << 8) | ((PMacTxInfo.VHT_SIG_A[2]) << 16);
- PHY_SetBBReg(Adapter, 0xb0c, bMaskDWord, u4bTmp);
+ phy_set_bb_reg(Adapter, 0xb0c, bMaskDWord, u4bTmp);
u4bTmp = PMacTxInfo.VHT_SIG_A[3] | ((PMacTxInfo.VHT_SIG_A[4]) << 8) | ((PMacTxInfo.VHT_SIG_A[5]) << 16);
- PHY_SetBBReg(Adapter, 0xb10, 0xffffff, u4bTmp);
+ phy_set_bb_reg(Adapter, 0xb10, 0xffffff, u4bTmp);
_rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_SIG_B, 4);
- PHY_SetBBReg(Adapter, 0xb14, bMaskDWord, u4bTmp);
+ phy_set_bb_reg(Adapter, 0xb14, bMaskDWord, u4bTmp);
}
if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) {
u4bTmp = (PMacTxInfo.VHT_SIG_B_CRC << 24) | PMacTxInfo.PacketPeriod; /* for TX interval */
- PHY_SetBBReg(Adapter, 0xb20, bMaskDWord, u4bTmp);
+ phy_set_bb_reg(Adapter, 0xb20, bMaskDWord, u4bTmp);
_rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_Delimiter, 4);
- PHY_SetBBReg(Adapter, 0xb24, bMaskDWord, u4bTmp);
+ phy_set_bb_reg(Adapter, 0xb24, bMaskDWord, u4bTmp);
/* 0xb28 - 0xb34 24 byte Probe Request MAC Header*/
/*& Duration & Frame control*/
- PHY_SetBBReg(Adapter, 0xb28, bMaskDWord, 0x00000040);
+ phy_set_bb_reg(Adapter, 0xb28, bMaskDWord, 0x00000040);
/* Address1 [0:3]*/
u4bTmp = PMacTxInfo.MacAddress[0] | (PMacTxInfo.MacAddress[1] << 8) | (PMacTxInfo.MacAddress[2] << 16) | (PMacTxInfo.MacAddress[3] << 24);
- PHY_SetBBReg(Adapter, 0xb2C, bMaskDWord, u4bTmp);
+ phy_set_bb_reg(Adapter, 0xb2C, bMaskDWord, u4bTmp);
/* Address3 [3:0]*/
- PHY_SetBBReg(Adapter, 0xb38, bMaskDWord, u4bTmp);
+ phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);
/* Address2[0:1] & Address1 [5:4]*/
u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8) | (Adapter->mac_addr[0] << 16) | (Adapter->mac_addr[1] << 24);
- PHY_SetBBReg(Adapter, 0xb30, bMaskDWord, u4bTmp);
+ phy_set_bb_reg(Adapter, 0xb30, bMaskDWord, u4bTmp);
/* Address2 [5:2]*/
u4bTmp = Adapter->mac_addr[2] | (Adapter->mac_addr[3] << 8) | (Adapter->mac_addr[4] << 16) | (Adapter->mac_addr[5] << 24);
- PHY_SetBBReg(Adapter, 0xb34, bMaskDWord, u4bTmp);
+ phy_set_bb_reg(Adapter, 0xb34, bMaskDWord, u4bTmp);
/* Sequence Control & Address3 [5:4]*/
/*u4bTmp = PMacTxInfo.MacAddress[4]|(PMacTxInfo.MacAddress[5] << 8) ;*/
- /*PHY_SetBBReg(Adapter, 0xb38, bMaskDWord, u4bTmp);*/
+ /*phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);*/
} else {
- PHY_SetBBReg(Adapter, 0xb20, bMaskDWord, PMacTxInfo.PacketPeriod); /* for TX interval*/
+ phy_set_bb_reg(Adapter, 0xb20, bMaskDWord, PMacTxInfo.PacketPeriod); /* for TX interval*/
/* & Duration & Frame control */
- PHY_SetBBReg(Adapter, 0xb24, bMaskDWord, 0x00000040);
+ phy_set_bb_reg(Adapter, 0xb24, bMaskDWord, 0x00000040);
/* 0xb24 - 0xb38 24 byte Probe Request MAC Header*/
/* Address1 [0:3]*/
u4bTmp = PMacTxInfo.MacAddress[0] | (PMacTxInfo.MacAddress[1] << 8) | (PMacTxInfo.MacAddress[2] << 16) | (PMacTxInfo.MacAddress[3] << 24);
- PHY_SetBBReg(Adapter, 0xb28, bMaskDWord, u4bTmp);
+ phy_set_bb_reg(Adapter, 0xb28, bMaskDWord, u4bTmp);
/* Address3 [3:0]*/
- PHY_SetBBReg(Adapter, 0xb34, bMaskDWord, u4bTmp);
+ phy_set_bb_reg(Adapter, 0xb34, bMaskDWord, u4bTmp);
/* Address2[0:1] & Address1 [5:4]*/
u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8) | (Adapter->mac_addr[0] << 16) | (Adapter->mac_addr[1] << 24);
- PHY_SetBBReg(Adapter, 0xb2c, bMaskDWord, u4bTmp);
+ phy_set_bb_reg(Adapter, 0xb2c, bMaskDWord, u4bTmp);
/* Address2 [5:2] */
u4bTmp = Adapter->mac_addr[2] | (Adapter->mac_addr[3] << 8) | (Adapter->mac_addr[4] << 16) | (Adapter->mac_addr[5] << 24);
- PHY_SetBBReg(Adapter, 0xb30, bMaskDWord, u4bTmp);
+ phy_set_bb_reg(Adapter, 0xb30, bMaskDWord, u4bTmp);
/* Sequence Control & Address3 [5:4]*/
u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8);
- PHY_SetBBReg(Adapter, 0xb38, bMaskDWord, u4bTmp);
+ phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);
}
- PHY_SetBBReg(Adapter, 0xb48, bMaskByte3, PMacTxInfo.TX_RATE_HEX);
+ phy_set_bb_reg(Adapter, 0xb48, bMaskByte3, PMacTxInfo.TX_RATE_HEX);
/* 0xb4c 3:0 TXSC 5:4 BW 7:6 m_STBC 8 NDP_Sound*/
u4bTmp = (PMacTxInfo.TX_SC) | ((PMacTxInfo.BandWidth) << 4) | ((PMacTxInfo.m_STBC - 1) << 6) | ((PMacTxInfo.NDP_sound) << 8);
- PHY_SetBBReg(Adapter, 0xb4c, 0x1ff, u4bTmp);
+ phy_set_bb_reg(Adapter, 0xb4c, 0x1ff, u4bTmp);
- if (IS_HARDWARE_TYPE_8814A(Adapter) || IS_HARDWARE_TYPE_8822B(Adapter)) {
+ if (IS_HARDWARE_TYPE_JAGUAR2(Adapter)) {
u4Byte offset = 0xb44;
if (IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE))
- PHY_SetBBReg(Adapter, offset, 0xc0000000, 0);
+ phy_set_bb_reg(Adapter, offset, 0xc0000000, 0);
else if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE))
- PHY_SetBBReg(Adapter, offset, 0xc0000000, 1);
+ phy_set_bb_reg(Adapter, offset, 0xc0000000, 1);
else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE))
- PHY_SetBBReg(Adapter, offset, 0xc0000000, 2);
+ phy_set_bb_reg(Adapter, offset, 0xc0000000, 2);
}
- PHY_SetBBReg(Adapter, 0xb00, BIT8, 1); /* Turn on PMAC*/
- /* PHY_SetBBReg(Adapter, 0xb04, 0xf, 2); */ /* TX Stop */
+ phy_set_bb_reg(Adapter, 0xb00, BIT8, 1); /* Turn on PMAC*/
+ /* phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); */ /* TX Stop */
if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) {
- PHY_SetBBReg(Adapter, 0xb04, 0xf, 8); /*TX CCK ON*/
- PHY_SetBBReg(Adapter, 0xA84, BIT31, 0);
+ phy_set_bb_reg(Adapter, 0xb04, 0xf, 8); /*TX CCK ON*/
+ phy_set_bb_reg(Adapter, 0xA84, BIT31, 0);
} else
- PHY_SetBBReg(Adapter, 0xb04, 0xf, 4); /* TX Ofdm ON */
+ phy_set_bb_reg(Adapter, 0xb04, 0xf, 4); /* TX Ofdm ON */
if (PMacTxInfo.Mode == OFDM_Single_Tone_TX)
mpt_SetSingleTone_8814A(Adapter, TRUE, TRUE);
}
+
#endif
+void hal_mpt_SetContinuousTx(PADAPTER pAdapter, u8 bStart)
+{
+ u8 Rate;
+
+ RTW_INFO("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx);
+ Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx);
+ pAdapter->mppriv.mpt_ctx.is_start_cont_tx = bStart;
+
+ if (Rate <= MPT_RATE_11M) {
+ if (bStart)
+ mpt_StartCckContTx(pAdapter);
+ else
+ mpt_StopCckContTx(pAdapter);
+
+ } else if (Rate >= MPT_RATE_6M) {
+ if (bStart)
+ mpt_StartOfdmContTx(pAdapter);
+ else
+ mpt_StopOfdmContTx(pAdapter);
+ }
+}
+
#endif /* CONFIG_MP_INCLUDE*/
diff --git a/hal/hal_phy.c b/hal/hal_phy.c
index 9d809ed..1504a73 100644
--- a/hal/hal_phy.c
+++ b/hal/hal_phy.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,22 +11,11 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#define _HAL_PHY_C_
#include
-/* ********************************************************************************
- * Constant.
- * ********************************************************************************
- * 2008/11/20 MH For Debug only, RF */
-static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG];
-
/**
* Function: PHY_CalculateBitShift
*
@@ -54,6 +43,13 @@ PHY_CalculateBitShift(
}
+#ifdef CONFIG_RF_SHADOW_RW
+/* ********************************************************************************
+ * Constant.
+ * ********************************************************************************
+ * 2008/11/20 MH For Debug only, RF */
+static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG];
+
/*
* ==> RF shadow Operation API Code Section!!!
*
@@ -85,7 +81,7 @@ PHY_CalculateBitShift(
u32
PHY_RFShadowRead(
IN PADAPTER Adapter,
- IN u8 eRFPath,
+ IN enum rf_path eRFPath,
IN u32 Offset)
{
return RF_Shadow[eRFPath][Offset].Value;
@@ -96,7 +92,7 @@ PHY_RFShadowRead(
VOID
PHY_RFShadowWrite(
IN PADAPTER Adapter,
- IN u8 eRFPath,
+ IN enum rf_path eRFPath,
IN u32 Offset,
IN u32 Data)
{
@@ -109,7 +105,7 @@ PHY_RFShadowWrite(
BOOLEAN
PHY_RFShadowCompare(
IN PADAPTER Adapter,
- IN u8 eRFPath,
+ IN enum rf_path eRFPath,
IN u32 Offset)
{
u32 reg;
@@ -120,9 +116,6 @@ PHY_RFShadowCompare(
if (RF_Shadow[eRFPath][Offset].Value != reg) {
/* Locate error position. */
RF_Shadow[eRFPath][Offset].ErrorOrNot = _TRUE;
- /* RT_TRACE(COMP_INIT, DBG_LOUD, */
- /* ("PHY_RFShadowCompare RF-%d Addr%02lx Err = %05lx\n", */
- /* eRFPath, Offset, reg)); */
}
return RF_Shadow[eRFPath][Offset].ErrorOrNot ;
}
@@ -133,7 +126,7 @@ PHY_RFShadowCompare(
VOID
PHY_RFShadowRecorver(
IN PADAPTER Adapter,
- IN u8 eRFPath,
+ IN enum rf_path eRFPath,
IN u32 Offset)
{
/* Check if the address is error */
@@ -142,9 +135,6 @@ PHY_RFShadowRecorver(
if (RF_Shadow[eRFPath][Offset].Recorver == _TRUE) {
rtw_hal_write_rfreg(Adapter, eRFPath, Offset, bRFRegOffsetMask,
RF_Shadow[eRFPath][Offset].Value);
- /* RT_TRACE(COMP_INIT, DBG_LOUD, */
- /* ("PHY_RFShadowRecorver RF-%d Addr%02lx=%05lx", */
- /* eRFPath, Offset, RF_Shadow[eRFPath][Offset].Value)); */
}
}
@@ -155,7 +145,7 @@ VOID
PHY_RFShadowCompareAll(
IN PADAPTER Adapter)
{
- u8 eRFPath = 0 ;
+ enum rf_path eRFPath = RF_PATH_A;
u32 Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter);
for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) {
@@ -170,7 +160,7 @@ VOID
PHY_RFShadowRecorverAll(
IN PADAPTER Adapter)
{
- u8 eRFPath = 0;
+ enum rf_path eRFPath = RF_PATH_A;
u32 Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter);
for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) {
@@ -184,7 +174,7 @@ PHY_RFShadowRecorverAll(
VOID
PHY_RFShadowCompareFlagSet(
IN PADAPTER Adapter,
- IN u8 eRFPath,
+ IN enum rf_path eRFPath,
IN u32 Offset,
IN u8 Type)
{
@@ -197,7 +187,7 @@ PHY_RFShadowCompareFlagSet(
VOID
PHY_RFShadowRecorverFlagSet(
IN PADAPTER Adapter,
- IN u8 eRFPath,
+ IN enum rf_path eRFPath,
IN u32 Offset,
IN u8 Type)
{
@@ -211,7 +201,7 @@ VOID
PHY_RFShadowCompareFlagSetAll(
IN PADAPTER Adapter)
{
- u8 eRFPath = 0;
+ enum rf_path eRFPath = RF_PATH_A;
u32 Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter);
for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) {
@@ -231,7 +221,7 @@ VOID
PHY_RFShadowRecorverFlagSetAll(
IN PADAPTER Adapter)
{
- u8 eRFPath = 0;
+ enum rf_path eRFPath = RF_PATH_A;
u32 Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter);
for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) {
@@ -250,7 +240,7 @@ VOID
PHY_RFShadowRefresh(
IN PADAPTER Adapter)
{
- u8 eRFPath = 0;
+ enum rf_path eRFPath = RF_PATH_A;
u32 Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter);
for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) {
@@ -264,3 +254,4 @@ PHY_RFShadowRefresh(
}
} /* PHY_RFShadowRead */
+#endif /*CONFIG_RF_SHADOW_RW*/
diff --git a/hal/halmac/halmac_2_platform.h b/hal/halmac/halmac_2_platform.h
index 2541867..44fd9a1 100644
--- a/hal/halmac/halmac_2_platform.h
+++ b/hal/halmac/halmac_2_platform.h
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2015 - 2018 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,12 +11,8 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
******************************************************************************/
+
#ifndef _HALMAC_2_PLATFORM_H_
#define _HALMAC_2_PLATFORM_H_
@@ -39,14 +35,6 @@
#define HALMAC_INLINE inline
-typedef u8 *pu8;
-typedef u16 *pu16;
-typedef u32 *pu32;
-typedef s8 *ps8;
-typedef s16 *ps16;
-typedef s32 *ps32;
-
-
#define HALMAC_PLATFORM_LITTLE_ENDIAN 1
#define HALMAC_PLATFORM_BIG_ENDIAN 0
@@ -70,8 +58,20 @@ typedef s32 *ps32;
/*[Driver] config if enable the dbg msg or notl*/
#define HALMAC_DBG_MSG_ENABLE 1
-/*[Driver] define the Platform SDIO Bus CLK */
-#define PLATFORM_SD_CLK 50000000 /*50MHz*/
+#define HALMAC_MSG_LEVEL_TRACE 3
+#define HALMAC_MSG_LEVEL_WARNING 2
+#define HALMAC_MSG_LEVEL_ERR 1
+#define HALMAC_MSG_LEVEL_NO_LOG 0
+/*[Driver] config halmac msg level
+ * Use HALMAC_MSG_LEVEL_XXXX
+ */
+#define HALMAC_MSG_LEVEL HALMAC_MSG_LEVEL_TRACE
+
+/*[Driver] define the Rx FIFO expanding mode packet size unit for 8821C and 8822B */
+/*Should be 8 Byte alignment*/
+#define HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE 80 /*Bytes*/
+
+#define HALMAC_USE_TYPEDEF 0
/*[Driver] provide the type mutex*/
/* Mutex type */
diff --git a/hal/halmac/halmac_88xx/halmac_8197f/halmac_8197f_cfg.h b/hal/halmac/halmac_88xx/halmac_8197f/halmac_8197f_cfg.h
deleted file mode 100644
index 4386ec8..0000000
--- a/hal/halmac/halmac_88xx/halmac_8197f/halmac_8197f_cfg.h
+++ /dev/null
@@ -1,112 +0,0 @@
-#ifndef _HALMAC_8197F_CFG_H_
-#define _HALMAC_8197F_CFG_H_
-
-#include "halmac_8197f_pwr_seq.h"
-#include "halmac_api_8197f.h"
-#include "halmac_api_8197f_usb.h"
-#include "halmac_api_8197f_sdio.h"
-#include "halmac_api_8197f_pcie.h"
-
-#if HALMAC_PLATFORM_TESTPROGRAM
-#include "halmisc_api_8197f.h"
-#include "halmisc_api_8197f_usb.h"
-#include "halmisc_api_8197f_sdio.h"
-#include "halmisc_api_8197f_pcie.h"
-#endif
-
-#define HALMAC_TX_FIFO_SIZE_8197F 262144 /* 64k */
-#define HALMAC_RX_FIFO_SIZE_8197F 32768 /* 32k */
-#define HALMAC_TX_PAGE_SIZE_8197F 128 /* PageSize 128Byte */
-#define HALMAC_SECURITY_CAM_ENTRY_NUM_8197F 64 /* CAM Entry Size */
-#define HALMAC_TX_DESC_SIZE_8197F 48
-#define HALMAC_RX_DESC_SIZE_8197F 24
-
-/* H2C/C2hH*/
-#define HALMAC_H2C_CMD_SIZE_8197F 32
-
-/* Efuse size */
-#define HALMAC_EFUSE_SIZE_8197F 512/* 0x2000 */
-#define HALMAC_EEPROM_SIZE_8197F 0x300
-#define HALMAC_BT_EFUSE_SIZE_8197F 128
-
-/* Rx aggregation parameters */
-typedef enum _HALMAC_NORMAL_RXAGG_TH_TO_8197F {
- HALMAC_NORMAL_RXAGG_THRESHOLD_8197F = 0xFF,
- HALMAC_NORMAL_RXAGG_TIMEOUT_8197F = 0x01,
-} HALMAC_NORMAL_RXAGG_TH_TO_8197F;
-
-typedef enum _HALMAC_LOOPBACK_RXAGG_TH_TO_8197F {
- HALMAC_LOOPBACK_RXAGG_THRESHOLD_8197F = 0xFF,
- HALMAC_LOOPBACK_RXAGG_TIMEOUT_8197F = 0x01,
-} HALMAC_LOOPBACK_RXAGG_TH_TO_8197F;
-
-/* FIFO size & packet size */
-#define HALMAC_BASIC_RXFF_SIZE_8197F 24576 /* 24K */
-#define HALMAC_WOWLAN_PATTERN_SIZE_8197F 256
-
-/* Normal mode */
-typedef enum _HALMAC_NORMAL_PAGE_NUM_8197F {
- HALMAC_NORMAL_PAGE_NUM_HPQ_8197F = 0x4C,
- HALMAC_NORMAL_PAGE_NUM_NPQ_8197F = 0x4C,
- HALMAC_NORMAL_PAGE_NUM_LPQ_8197F = 0x4C,
- HALMAC_NORMAL_PAGE_NUM_EXPQ_8197F = 0x4A,
- HALMAC_NORMAL_PAGE_NUM_PUBQ_8197F = 0x6C0,
- HALMAC_NORMAL_TX_PAGE_BOUNDARY_8197F = 2032,
-} HALMAC_NORMAL_PAGE_NUM_8197F;
-
-/* Loop back mode */
-typedef enum _HALMAC_LOOBACK_PAGE_NUM_8197F {
- HALMAC_LOOPBACK_PAGE_NUM_HPQ_8197F = 0x4C,
- HALMAC_LOOPBACK_PAGE_NUM_LPQ_8197F = 0x4C,
- HALMAC_LOOPBACK_PAGE_NUM_NPQ_8197F = 0x4C,
- HALMAC_LOOPBACK_PAGE_NUM_EXPQ_8197F = 0x4A,
- HALMAC_LOOPBACK_PAGE_NUM_PUBQ_8197F = 0x2C0,
- HALMAC_LOOPBACK_TX_PAGE_BOUNDARY_8197F = 1008,
- HALMAC_LOOPBACK_LB_BUF_PAGE_NUM_8197F = 0x600,
-} HALMAC_LOOBACK_PAGE_NUM_8197F;
-
-
-/* Normal mode */
-typedef enum _HALMAC_NORMAL_PAGE_NUM_2BULKOUT_8197F {
- HALMAC_NORMAL_PAGE_NUM_HPQ_2BULKOUT_8197F = 0x4C,
- HALMAC_NORMAL_PAGE_NUM_NPQ_2BULKOUT_8197F = 0x4C,
- HALMAC_NORMAL_PAGE_NUM_LPQ_2BULKOUT_8197F = 0x00,
- HALMAC_NORMAL_PAGE_NUM_EXPQ_2BULKOUT_8197F = 0x00,
- HALMAC_NORMAL_PAGE_NUM_PUBQ_2BULKOUT_8197F = 0x756,
- HALMAC_NORMAL_TX_PAGE_BOUNDARY_2BULKOUT_8197F = 2032,
-} HALMAC_NORMAL_PAGE_NUM_2BULKOUT_8197F;
-
-/* Loop back mode */
-typedef enum _HALMAC_LOOBACK_PAGE_NUM_2BULKOUT_8197F {
- HALMAC_LOOPBACK_PAGE_NUM_HPQ_2BULKOUT_8197F = 0x4C,
- HALMAC_LOOPBACK_PAGE_NUM_NPQ_2BULKOUT_8197F = 0x4C,
- HALMAC_LOOPBACK_PAGE_NUM_LPQ_2BULKOUT_8197F = 0x00,
- HALMAC_LOOPBACK_PAGE_NUM_EXPQ_2BULKOUT_8197F = 0x00,
- HALMAC_LOOPBACK_PAGE_NUM_PUBQ_2BULKOUT_8197F = 0x356,
- HALMAC_LOOPBACK_TX_PAGE_BOUNDARY_2BULKOUT_8197F = 1008,
- HALMAC_LOOPBACK_LB_BUF_PAGE_NUM_2BULKOUT_8197F = 0x600,
-} HALMAC_LOOBACK_PAGE_NUM_2BULKOUT_8197F;
-
-/* Normal mode */
-typedef enum _HALMAC_NORMAL_PAGE_NUM_3BULKOUT_8197F {
- HALMAC_NORMAL_PAGE_NUM_HPQ_3BULKOUT_8197F = 0x4C,
- HALMAC_NORMAL_PAGE_NUM_NPQ_3BULKOUT_8197F = 0x4C,
- HALMAC_NORMAL_PAGE_NUM_LPQ_3BULKOUT_8197F = 0x4C,
- HALMAC_NORMAL_PAGE_NUM_EXPQ_3BULKOUT_8197F = 0x00,
- HALMAC_NORMAL_PAGE_NUM_PUBQ_3BULKOUT_8197F = 0x70A,
- HALMAC_NORMAL_TX_PAGE_BOUNDARY_3BULKOUT_8197F = 2032,
-} HALMAC_NORMAL_PAGE_NUM_3BULKOUT_8197F;
-
-/* Loop back mode */
-typedef enum _HALMAC_LOOBACK_PAGE_NUM_3BULKOUT_8197F {
- HALMAC_LOOPBACK_PAGE_NUM_HPQ_3BULKOUT_8197F = 0x4C,
- HALMAC_LOOPBACK_PAGE_NUM_NPQ_3BULKOUT_8197F = 0x4C,
- HALMAC_LOOPBACK_PAGE_NUM_LPQ_3BULKOUT_8197F = 0x4C,
- HALMAC_LOOPBACK_PAGE_NUM_EXPQ_3BULKOUT_8197F = 0x00,
- HALMAC_LOOPBACK_PAGE_NUM_PUBQ_3BULKOUT_8197F = 0x30A,
- HALMAC_LOOPBACK_TX_PAGE_BOUNDARY_3BULKOUT_8197F = 1008,
- HALMAC_LOOPBACK_LB_BUF_PAGE_NUM_3BULKOUT_8197F = 0x600,
-} HALMAC_LOOBACK_PAGE_NUM_3BULKOUT_8197F;
-
-
-#endif
diff --git a/hal/halmac/halmac_88xx/halmac_8197f/halmac_8197f_pwr_seq.h b/hal/halmac/halmac_88xx/halmac_8197f/halmac_8197f_pwr_seq.h
deleted file mode 100644
index a4bb2ec..0000000
--- a/hal/halmac/halmac_88xx/halmac_8197f/halmac_8197f_pwr_seq.h
+++ /dev/null
@@ -1,161 +0,0 @@
-#ifndef HALMAC_POWER_SEQUENCE_8197F
-#define HALMAC_POWER_SEQUENCE_8197F
-
-#include "../../halmac_pwr_seq_cmd.h"
-
-/*
- * There are 6 HW Power States:
- * 0: POFF--Power Off
- * 1: PDN--Power Down
- * 2: CARDEMU--Card Emulation
- * 3: ACT--Active Mode
- * 4: LPS--Low Power State
- * 5: SUS--Suspend
- *
- * The transition from different states are defined below
- * TRANS_CARDEMU_TO_ACT
- * TRANS_ACT_TO_CARDEMU
- * TRANS_CARDEMU_TO_SUS
- * TRANS_SUS_TO_CARDEMU
- * TRANS_CARDEMU_TO_PDN
- * TRANS_ACT_TO_LPS
- * TRANS_LPS_TO_ACT
- *
- * TRANS_END
- */
-
-#define HALMAC_8197f_TRANS_CARDEMU_TO_ACT_STEPS 15
-#define HALMAC_8197f_TRANS_ACT_TO_CARDEMU_STEPS 15
-#define HALMAC_8197f_TRANS_CARDEMU_TO_SUS_STEPS 15
-#define HALMAC_8197f_TRANS_SUS_TO_CARDEMU_STEPS 15
-#define HALMAC_8197f_TRANS_CARDEMU_TO_PDN_STEPS 15
-#define HALMAC_8197f_TRANS_PDN_TO_CARDEMU_STEPS 15
-#define HALMAC_8197f_TRANS_ACT_TO_LPS_STEPS 20
-#define HALMAC_8197f_TRANS_LPS_TO_ACT_STEPS 15
-#define HALMAC_8197f_TRANS_END_STEPS 1
-
-
-#define RTL8197f_TRANS_CARDEMU_TO_ACT \
- /* format */ \
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), 0 }, /* disable SW LPS 0x04[10]=0*/ \
- { 0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1) }, /* wait till 0x04[17] = 1 power ready*/ \
- { 0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* release WLON reset 0x04[16]=1*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), 0 }, /* disable HWPDN 0x04[15]=0*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0 }, /* disable WL suspend*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* polling until return 0*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(0), 0 }, /**/ \
- { 0x0026, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4) }, /*MAC CLK = 40M*/ \
- { 0x0073, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2) }, /**/
-
-#define RTL8197f_TRANS_ACT_TO_CARDEMU \
- /* format */ \
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
- { 0x001F, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0 }, /*0x1F[7:0] = 0 turn off RF*/ \
- { 0x004E, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), 0 }, /*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1) }, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(1), 0 }, /*wait till 0x04[9] = 0 polling until return 0 to disable*/
-
-#define RTL8197f_TRANS_CARDEMU_TO_SUS \
- /* format */ \
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3)) }, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) }, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4) }, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
- { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /*Set SDIO suspend local register*/ \
- { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), 0 }, /*wait power state to suspend*/
-
-#define RTL8197f_TRANS_SUS_TO_CARDEMU \
- /* format */ \
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
- { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /*Set SDIO suspend local register*/ \
- { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1) }, /*wait power state to suspend*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), 0 }, /*0x04[12:11] = 2b'01enable WL suspend*/
-
-#define RTL8197f_TRANS_CARDEMU_TO_CARDDIS \
- /* format */ \
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
- { 0x0007, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20 }, /*0x07=0x20 , SOP option to disable BG/MB*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) }, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2) }, /*0x04[10] = 1, enable SW LPS*/ \
- { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /*Set SDIO suspend local register*/ \
- { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), 0 }, /*wait power state to suspend*/
-
-#define RTL8197f_TRANS_CARDDIS_TO_CARDEMU \
- /* format */ \
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
- { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /*Set SDIO suspend local register*/ \
- { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1) }, /*wait power state to suspend*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), 0 }, /*0x04[12:11] = 2b'01enable WL suspend*/ \
- { 0x0301, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0 }, /*PCIe DMA start*/
-
-
-#define RTL8197f_TRANS_CARDEMU_TO_PDN \
- /* format */ \
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
- { 0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /* 0x04[16] = 0*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7) }, /* 0x04[15] = 1*/
-
-#define RTL8197f_TRANS_PDN_TO_CARDEMU \
- /* format */ \
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), 0 },/* 0x04[15] = 0*/
-
-#define RTL8197f_TRANS_ACT_TO_LPS \
- /* format */ \
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
- { 0x1138, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, BIT(0) | BIT(1) }, /*set RPWM IMR*/ \
- { 0x0194, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* enable 32K CLK*/ \
- /*{0x0093, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK,HALMAC_PWR_BASEADDR_MAC,HALMAC_PWR_CMD_WRITE, 0xff, 0x42}, *//* LPS Option WL partial ON*/ \
- { 0x0093, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xff, 0x40 }, /* LPS Option WL partial ON disable*/ \
- { 0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*Tx Pause*/ \
- { 0x05F8, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0 }, /*Should be zero if no packet is transmitting*/ \
- { 0x05F9, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0 }, /*Should be zero if no packet is transmitting*/ \
- { 0x05FA, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0 }, /*Should be zero if no packet is transmitting*/ \
- { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /*CCK and OFDM are disabled,and clock are gated*/ \
- { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWRSEQ_DELAY_US }, /*Delay 1us*/ \
- { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /*Whole BB is reset*/ \
- { 0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x3F }, /*Reset MAC TRX*/ \
- { 0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /*check if removed later*/ \
- { 0x0553, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5) }, /*Respond TxOK to scheduler*/ \
- { 0x0029, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(6) | BIT(7), 0x00 }, /*gated BB clock*/ \
- { 0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4) }, /* switch TSF clock to 32K*/ \
- { 0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* enable WL_LPS_EN*/
-
-
-#define RTL8197f_TRANS_LPS_TO_ACT \
- /* format */ \
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
- /*{0x0080, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK,HALMAC_PWR_BASEADDR_SDIO,HALMAC_PWR_CMD_WRITE, 0xFF, 0x84}, *//*SDIO RPWM*/ \
- { 0x0080, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7) }, /*SDIO RPWM*/ \
- { 0x0080, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(7), 0 }, /*SDIO RPWM*/ \
- { 0xFE58, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x84 }, /*USB RPWM*/ \
- { 0x0361, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x84 }, /*PCIe RPWM*/ \
- { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWRSEQ_DELAY_MS }, /*Delay*/ \
- { 0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), 0 }, /*. 0x08[4] = 0 switch TSF to 40M*/ \
- { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWRSEQ_DELAY_MS }, /*Delay*/ \
- { 0x0109, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(7), 0 }, /*Polling 0x109[7]=0 TSF in 40M*/ \
- { 0x0029, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(6) | BIT(7), BIT(6) | BIT(7) }, /*. 0x29[7:6] = 2b'00 enable BB clock*/ \
- { 0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1) }, /*. 0x101[1] = 1*/ \
- { 0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/ \
- { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0) }, /*. 0x02[1:0] = 2b'11 enable BB macro*/ \
- { 0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0 }, /*. 0x522 = 0*/ \
- { 0x113C, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0 }, /*clear RPWM INT*/
-
-#define RTL8197f_TRANS_END \
- /* format */ \
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
- { 0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0 },
-
-
-extern HALMAC_WLAN_PWR_CFG halmac_8197f_power_on_flow[HALMAC_8197f_TRANS_CARDEMU_TO_ACT_STEPS + HALMAC_8197f_TRANS_END_STEPS];
-extern HALMAC_WLAN_PWR_CFG halmac_8197f_radio_off_flow[HALMAC_8197f_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8197f_TRANS_END_STEPS];
-extern HALMAC_WLAN_PWR_CFG halmac_8197f_card_disable_flow[HALMAC_8197f_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8197f_TRANS_CARDEMU_TO_PDN_STEPS + HALMAC_8197f_TRANS_END_STEPS];
-extern HALMAC_WLAN_PWR_CFG halmac_8197f_card_enable_flow[HALMAC_8197f_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8197f_TRANS_CARDEMU_TO_PDN_STEPS + HALMAC_8197f_TRANS_END_STEPS];
-extern HALMAC_WLAN_PWR_CFG halmac_8197f_suspend_flow[HALMAC_8197f_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8197f_TRANS_CARDEMU_TO_SUS_STEPS + HALMAC_8197f_TRANS_END_STEPS];
-extern HALMAC_WLAN_PWR_CFG halmac_8197f_resume_flow[HALMAC_8197f_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8197f_TRANS_CARDEMU_TO_SUS_STEPS + HALMAC_8197f_TRANS_END_STEPS];
-extern HALMAC_WLAN_PWR_CFG halmac_8197f_hwpdn_flow[HALMAC_8197f_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8197f_TRANS_CARDEMU_TO_PDN_STEPS + HALMAC_8197f_TRANS_END_STEPS];
-extern HALMAC_WLAN_PWR_CFG halmac_8197f_enter_lps_flow[HALMAC_8197f_TRANS_ACT_TO_LPS_STEPS + HALMAC_8197f_TRANS_END_STEPS];
-extern HALMAC_WLAN_PWR_CFG halmac_8197f_leave_lps_flow[HALMAC_8197f_TRANS_LPS_TO_ACT_STEPS + HALMAC_8197f_TRANS_END_STEPS];
-
-#endif
diff --git a/hal/halmac/halmac_88xx/halmac_8197f/halmac_api_8197f.h b/hal/halmac/halmac_88xx/halmac_8197f/halmac_api_8197f.h
deleted file mode 100644
index 5c61b41..0000000
--- a/hal/halmac/halmac_88xx/halmac_8197f/halmac_api_8197f.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef _HALMAC_API_8197F_H_
-#define _HALMAC_API_8197F_H_
-
-#include "../../halmac_2_platform.h"
-#include "../../halmac_type.h"
-
-HALMAC_RET_STATUS
-halmac_mount_api_8197f(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-#endif/* _HALMAC_API_8197F_H_ */
diff --git a/hal/halmac/halmac_88xx/halmac_8197f/halmac_api_8197f_pcie.h b/hal/halmac/halmac_88xx/halmac_8197f/halmac_api_8197f_pcie.h
deleted file mode 100644
index 1e546a6..0000000
--- a/hal/halmac/halmac_88xx/halmac_8197f/halmac_api_8197f_pcie.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef _HALMAC_API_8197F_PCIE_H_
-#define _HALMAC_API_8197F_PCIE_H_
-
-#include "../../halmac_2_platform.h"
-#include "../../halmac_type.h"
-
-
-#endif/* _HALMAC_API_8197F_PCIE_H_ */
diff --git a/hal/halmac/halmac_88xx/halmac_8197f/halmac_api_8197f_sdio.h b/hal/halmac/halmac_88xx/halmac_8197f/halmac_api_8197f_sdio.h
deleted file mode 100644
index c6e59c3..0000000
--- a/hal/halmac/halmac_88xx/halmac_8197f/halmac_api_8197f_sdio.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef _HALMAC_API_8197F_SDIO_H_
-#define _HALMAC_API_8197F_SDIO_H_
-
-#include "../../halmac_2_platform.h"
-#include "../../halmac_type.h"
-
-
-#endif/* _HALMAC_API_8197F_SDIO_H_ */
diff --git a/hal/halmac/halmac_88xx/halmac_8197f/halmac_api_8197f_usb.h b/hal/halmac/halmac_88xx/halmac_8197f/halmac_api_8197f_usb.h
deleted file mode 100644
index 4bf5779..0000000
--- a/hal/halmac/halmac_88xx/halmac_8197f/halmac_api_8197f_usb.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef _HALMAC_API_8197F_USB_H_
-#define _HALMAC_API_8197F_USB_H_
-
-#include "../../halmac_2_platform.h"
-#include "../../halmac_type.h"
-
-
-#endif/* _HALMAC_API_8197F_USB_H_ */
diff --git a/hal/halmac/halmac_88xx/halmac_8197f/halmac_func_8197f.h b/hal/halmac/halmac_88xx/halmac_8197f/halmac_func_8197f.h
deleted file mode 100644
index 1432b41..0000000
--- a/hal/halmac/halmac_88xx/halmac_8197f/halmac_func_8197f.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _HALMAC_FUNC_8197F_H_
-#define _HALMAC_FUNC_8197F_H_
-
-#include "../../halmac_type.h"
-
-#endif /* _HALMAC_FUNC_8197F_H_ */
diff --git a/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_cfg.h b/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_cfg.h
deleted file mode 100644
index 1bd24c0..0000000
--- a/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_cfg.h
+++ /dev/null
@@ -1,119 +0,0 @@
-#ifndef _HALMAC_8821C_CFG_H_
-#define _HALMAC_8821C_CFG_H_
-
-#include "halmac_8821c_pwr_seq.h"
-#include "halmac_api_8821c.h"
-#include "halmac_api_8821c_usb.h"
-#include "halmac_api_8821c_pcie.h"
-#include "halmac_api_8821c_sdio.h"
-#include "../../halmac_bit2.h"
-#include "../../halmac_reg2.h"
-#include "../../halmac_api.h"
-
-#if HALMAC_PLATFORM_TESTPROGRAM
-#include "halmisc_api_8821c.h"
-#include "halmisc_api_8821c_usb.h"
-#include "halmisc_api_8821c_sdio.h"
-#include "halmisc_api_8821c_pcie.h"
-#endif
-
-#define HALMAC_TX_FIFO_SIZE_8821C 65536 /* 64k */
-#define HALMAC_TX_FIFO_SIZE_LA_8821C 32768 /* 32k */
-#define HALMAC_RX_FIFO_SIZE_8821C 16384 /* 16k */
-#define HALMAC_TX_PAGE_SIZE_8821C 128 /* PageSize 128Byte */
-#define HALMAC_TX_PAGE_SIZE_2_POWER_8821C 7 /* 128 = 2^7 */
-#define HALMAC_SECURITY_CAM_ENTRY_NUM_8821C 64 /* CAM Entry Size */
-#define HALMAC_TX_DESC_SIZE_8821C 48
-#define HALMAC_RX_DESC_SIZE_8821C 24
-#define HALMAC_WOWLAN_PATTERN_SIZE_8821C 256
-
-#define HALMAC_EFUSE_SIZE_8821C 512 /* 0x2000 */
-#define HALMAC_EEPROM_SIZE_8821C 0x200
-#define HALMAC_BT_EFUSE_SIZE_8821C 128
-
-#define HALMAC_CR_TRX_ENABLE_8821C (BIT_HCI_TXDMA_EN | BIT_HCI_RXDMA_EN | BIT_TXDMA_EN | \
- BIT_RXDMA_EN | BIT_PROTOCOL_EN | BIT_SCHEDULE_EN | \
- BIT_MACTXEN | BIT_MACRXEN)
-
-#define HALMAC_BLK_DESC_NUM_8821C 0x3 /* Only for USB */
-
-typedef enum _HALMAC_NORMAL_RXAGG_TH_TO_8821C {
- HALMAC_NORMAL_RXAGG_THRESHOLD_8821C = 0xFF,
- HALMAC_NORMAL_RXAGG_TIMEOUT_8821C = 0x01,
-} HALMAC_NORMAL_RXAGG_TH_TO_8821C;
-
-typedef enum _HALMAC_LOOPBACK_RXAGG_TH_TO_8821C {
- HALMAC_LOOPBACK_RXAGG_THRESHOLD_8821C = 0xFF,
- HALMAC_LOOPBACK_RXAGG_TIMEOUT_8821C = 0x01,
-} HALMAC_LOOPBACK_RXAGG_TH_TO_8821C;
-
-#define HALMAC_RSVD_DRV_PGNUM_8821C 16 /*2048*/
-#define HALMAC_RSVD_H2C_EXTRAINFO_PGNUM_8821C 32 /*4096*/
-#define HALMAC_RSVD_H2C_QUEUE_PGNUM_8821C 8 /*1024*/
-#define HALMAC_RSVD_CPU_INSTRUCTION_PGNUM_8821C 0 /*0*/
-#define HALMAC_RSVD_FW_TXBUFF_PGNUM_8821C 4 /*512*/
-
-/*
- * Normal mode
- */
-#define HALMAC_NORMAL_HPQ_PGNUM_8821C 16 /*2048*/
-#define HALMAC_NORMAL_NPQ_PGNUM_8821C 16 /*2048*/
-#define HALMAC_NORMAL_LPQ_PGNUM_8821C 16 /*2048*/
-#define HALMAC_NORMAL_EXPQ_PGNUM_8821C 14 /**/
-#define HALMAC_NORMAL_GAP_PGNUM_8821C 1 /*128*/
-
-/*
- * Loopback mode
- */
-#define HALMAC_LB_HPQ_PGNUM_8821C 16 /*2048*/
-#define HALMAC_LB_NPQ_PGNUM_8821C 16 /*2048*/
-#define HALMAC_LB_LPQ_PGNUM_8821C 16 /*2048*/
-#define HALMAC_LB_EXPQ_PGNUM_8821C 14 /**/
-#define HALMAC_LB_GAP_PGNUM_8821C 256 /**/
-
-/*
- * Normal mode - 2Bulkout
- */
-#define HALMAC_NORMAL_2BULKOUT_HPQ_PGNUM_8821C 16 /*2048*/
-#define HALMAC_NORMAL_2BULKOUT_NPQ_PGNUM_8821C 16 /*2048*/
-#define HALMAC_NORMAL_2BULKOUT_LPQ_PGNUM_8821C 0 /*0*/
-#define HALMAC_NORMAL_2BULKOUT_EXPQ_PGNUM_8821C 0 /*0*/
-#define HALMAC_NORMAL_2BULKOUT_GAP_PGNUM_8821C 1 /*128*/
-
-/*
- * Loopback mode - 2Bulkout
- */
-#define HALMAC_LB_2BULKOUT_HPQ_PGNUM_8821C 16 /*2048*/
-#define HALMAC_LB_2BULKOUT_NPQ_PGNUM_8821C 16 /*2048*/
-#define HALMAC_LB_2BULKOUT_LPQ_PGNUM_8821C 0 /*0*/
-#define HALMAC_LB_2BULKOUT_EXPQ_PGNUM_8821C 0 /*0*/
-#define HALMAC_LB_2BULKOUT_GAP_PGNUM_8821C 256 /**/
-
-/*
- * Normal mode - 3BULKOUT
- */
-#define HALMAC_NORMAL_3BULKOUT_HPQ_PGNUM_8821C 16 /*2048*/
-#define HALMAC_NORMAL_3BULKOUT_NPQ_PGNUM_8821C 16 /*2048*/
-#define HALMAC_NORMAL_3BULKOUT_LPQ_PGNUM_8821C 16 /*2048*/
-#define HALMAC_NORMAL_3BULKOUT_EXPQ_PGNUM_8821C 0 /*0*/
-#define HALMAC_NORMAL_3BULKOUT_GAP_PGNUM_8821C 1 /*128*/
-
-/*
- * Loopback mode - 3BULKOUT
- */
-#define HALMAC_LB_3BULKOUT_HPQ_PGNUM_8821C 16 /*2048*/
-#define HALMAC_LB_3BULKOUT_NPQ_PGNUM_8821C 16 /*2048*/
-#define HALMAC_LB_3BULKOUT_LPQ_PGNUM_8821C 16 /*2048*/
-#define HALMAC_LB_3BULKOUT_EXPQ_PGNUM_8821C 0 /*0*/
-#define HALMAC_LB_3BULKOUT_GAP_PGNUM_8821C 256 /**/
-
-/*
- * WMM mode
- */
-#define HALMAC_WMM_HPQ_PGNUM_8821C 16 /*2048*/
-#define HALMAC_WMM_NPQ_PGNUM_8821C 16 /*2048*/
-#define HALMAC_WMM_LPQ_PGNUM_8821C 16 /*2048*/
-#define HALMAC_WMM_EXPQ_PGNUM_8821C 14 /**/
-#define HALMAC_WMM_GAP_PGNUM_8821C 1 /*128*/
-
-#endif
diff --git a/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_pwr_seq.h b/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_pwr_seq.h
deleted file mode 100644
index c813530..0000000
--- a/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_pwr_seq.h
+++ /dev/null
@@ -1,223 +0,0 @@
-#ifndef HALMAC_POWER_SEQUENCE_8821C
-#define HALMAC_POWER_SEQUENCE_8821C
-
-#include "../../halmac_pwr_seq_cmd.h"
-
-/*
- * There are 6 HW Power States:
- * 0: POFF--Power Off
- * 1: PDN--Power Down
- * 2: CARDEMU--Card Emulation
- * 3: ACT--Active Mode
- * 4: LPS--Low Power State
- * 5: SUS--Suspend
- *
- * The transition from different states are defined below
- * TRANS_CARDEMU_TO_ACT
- * TRANS_ACT_TO_CARDEMU
- * TRANS_CARDEMU_TO_SUS
- * TRANS_SUS_TO_CARDEMU
- * TRANS_CARDEMU_TO_PDN
- * TRANS_ACT_TO_LPS
- * TRANS_LPS_TO_ACT
- *
- * TRANS_END
- */
-
-#define HALMAC_8821c_TRANS_CARDEMU_TO_ACT_STEPS 25
-#define HALMAC_8821c_TRANS_ACT_TO_CARDEMU_STEPS 15
-#define HALMAC_8821c_TRANS_CARDEMU_TO_SUS_STEPS 15
-#define HALMAC_8821c_TRANS_SUS_TO_CARDEMU_STEPS 15
-#define HALMAC_8821c_TRANS_CARDEMU_TO_PDN_STEPS 15
-#define HALMAC_8821c_TRANS_PDN_TO_CARDEMU_STEPS 15
-#define HALMAC_8821c_TRANS_ACT_TO_LPS_STEPS 25
-#define HALMAC_8821c_TRANS_ACT_TO_DEEP_LPS_STEPS 25
-#define HALMAC_8821c_TRANS_LPS_TO_ACT_STEPS 20
-#define HALMAC_8821c_TRANS_END_STEPS 1
-
-
-#define HALMAC_RTL8821c_TRANS_CARDEMU_TO_ACT \
- /* format */ \
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
- { 0x0020, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \
- { 0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), 0 }, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \
- { 0x0001, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 1, HALMAC_PWRSEQ_DELAY_MS }, /*Delay 1ms*/ \
- { 0x0000, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), 0 }, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0 }, /* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[12:11]=0*/ \
- { 0x0075, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* Disable USB suspend */ \
- { 0x0004, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3) }, /* enabled usb resume */ \
- { 0x0004, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), 0 }, /* disable usb resume */ \
- { 0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1) }, /* wait till 0x04[17] = 1 power ready*/ \
- { 0x0075, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /* Enable USB suspend */ \
- { 0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* release WLON reset 0x04[16]=1*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), 0 }, /* disable HWPDN 0x04[15]=0*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0 }, /* disable WL suspend*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* polling until return 0*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(0), 0 }, /**/ \
- { 0x0020, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3) }, /*Enable XTAL_CLK*/ \
- { 0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5) }, /*0x67[5]=1 , BIT_PAPE_WLBT_SEL*/ \
-
-#define HALMAC_RTL8821c_TRANS_ACT_TO_CARDEMU \
- /* format */ \
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
- { 0x001F, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0 }, /*0x1F[7:0] = 0 turn off RF*/ \
- { 0x0049, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /*Enable rising edge triggering interrupt*/ \
- { 0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* release WLON reset 0x04[16]=1*/ \
- { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /* Whole BB is reset */ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1) }, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(1), 0 }, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
- { 0x0020, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), 0 }, /* XTAL_CLK gated*/ \
- { 0x0000, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5) }, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \
-
-#define HALMAC_RTL8821c_TRANS_CARDEMU_TO_SUS \
- /* format */ \
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3)) }, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) }, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
- { 0x0007, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20 }, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4) }, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
- { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /*Set SDIO suspend local register*/ \
- { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), 0 }, /*wait power state to suspend*/
-
-#define HALMAC_RTL8821c_TRANS_SUS_TO_CARDEMU \
- /* format */ \
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(7), 0 }, /*clear suspend enable and power down enable*/ \
- { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /*Set SDIO suspend local register*/ \
- { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1) }, /*wait power state to suspend*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), 0 }, /*0x04[12:11] = 2b'01enable WL suspend*/
-
-#define HALMAC_RTL8821c_TRANS_CARDEMU_TO_CARDDIS \
- /* format */ \
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
- { 0x0007, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20 }, /*0x07=0x20 , SOP option to disable BG/MB*/ \
- { 0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), 0 }, /*0x67[5]=0 , BIT_PAPE_WLBT_SEL*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) }, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2) }, /*0x04[10] = 1, enable SW LPS*/ \
- { 0x004A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \
- { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /*Set SDIO suspend local register*/ \
- { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), 0 }, /*wait power state to suspend*/ \
- { 0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /*0x90[1]=0 , disable 32k clock*/ \
- { 0x0044, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, 0xFF, 0 }, /*0x90[1]=0 , disable 32k clock by indirect access*/ \
- { 0x0040, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, 0xFF, 0x90 }, /*0x90[1]=0 , disable 32k clock by indirect access*/ \
- { 0x0041, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, 0xFF, 0x00 }, /*0x90[1]=0 , disable 32k clock by indirect access*/ \
- { 0x0042, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, 0xFF, 0x04 }, /*0x90[1]=0 , disable 32k clock by indirect access*/
-
-#define HALMAC_RTL8821c_TRANS_CARDDIS_TO_CARDEMU \
- /* format */ \
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(7), 0 }, /*clear suspend enable and power down enable*/ \
- { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /*Set SDIO suspend local register*/ \
- { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1) }, /*wait power state to suspend*/ \
- { 0x004A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), 0 }, /*0x04[12:11] = 2b'01enable WL suspend*/ \
- { 0x0301, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0 }, /*PCIe DMA start*/
-
-
-#define HALMAC_RTL8821c_TRANS_CARDEMU_TO_PDN \
- /* format */ \
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
- { 0x0007, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK | HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20 }, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \
- { 0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /* 0x04[16] = 0*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7) }, /* 0x04[15] = 1*/
-
-#define HALMAC_RTL8821c_TRANS_PDN_TO_CARDEMU \
- /* format */ \
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), 0 },/* 0x04[15] = 0*/
-
-#define HALMAC_RTL8821c_TRANS_ACT_TO_LPS \
- /* format */ \
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
- { 0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2) }, /*Enable 32k calibration and thermal meter*/ \
- { 0x0199, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3) }, /*Register write data of 32K calibration*/ \
- { 0x019B, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7) }, /*Enable 32k calibration reg write*/ \
- { 0x1138, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0) | BIT(1), BIT(0) | BIT(1) }, /*set RPWM IMR*/ \
- { 0x0194, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* enable 32K CLK*/ \
- { 0x0093, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x42 }, /* LPS Option MAC OFF enable*/ \
- { 0x0092, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20 }, /* LPS Option Enable memory to deep sleep mode*/ \
- { 0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1) }, /* enable reg use 32K CLK*/ \
- { 0x0301, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*PCIe DMA stop*/ \
- { 0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*Tx Pause*/ \
- { 0x05F8, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0 }, /*Should be zero if no packet is transmitting*/ \
- { 0x05F9, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0 }, /*Should be zero if no packet is transmitting*/ \
- { 0x05FA, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0 }, /*Should be zero if no packet is transmitting*/ \
- { 0x05FB, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0 }, /*Should be zero if no packet is transmitting*/ \
- { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /*CCK and OFDM are disabled,and clock are gated*/ \
- { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWRSEQ_DELAY_US }, /*Delay 1us*/ \
- { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /*Whole BB is reset*/ \
- { 0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x3F }, /*Reset MAC TRX*/ \
- { 0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /*check if removed later*/ \
- { 0x0553, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5) }, /*Respond TxOK to scheduler*/ \
- { 0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4) }, /* switch TSF clock to 32K*/ \
- { 0x0109, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(7), BIT(7) }, /*Polling 0x109[7]=0 TSF in 40M*/ \
- { 0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* enable WL_LPS_EN*/
-
-#define HALMAC_RTL8821c_TRANS_ACT_TO_DEEP_LPS \
- /* format */ \
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
- { 0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2) }, /*Enable 32k calibration and thermal meter*/ \
- { 0x0199, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3) }, /*Register write data of 32K calibration*/ \
- { 0x019B, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7) }, /*Enable 32k calibration reg write*/ \
- { 0x1138, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0) | BIT(1), BIT(0) | BIT(1) }, /*set RPWM IMR*/ \
- { 0x0194, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* enable 32K CLK*/ \
- { 0x0093, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x40 }, /* LPS Option MAC OFF enable*/ \
- { 0x0092, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20 }, /* LPS Option Enable memory to deep sleep mode*/ \
- { 0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1) }, /* enable reg use 32K CLK*/ \
- { 0x0301, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*PCIe DMA stop*/ \
- { 0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*Tx Pause*/ \
- { 0x05F8, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0 }, /*Should be zero if no packet is transmitting*/ \
- { 0x05F9, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0 }, /*Should be zero if no packet is transmitting*/ \
- { 0x05FA, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0 }, /*Should be zero if no packet is transmitting*/ \
- { 0x05FB, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0 }, /*Should be zero if no packet is transmitting*/ \
- { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /*CCK and OFDM are disabled,and clock are gated*/ \
- { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWRSEQ_DELAY_US }, /*Delay 1us*/ \
- { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /*Whole BB is reset*/ \
- { 0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x3F }, /*Reset MAC TRX*/ \
- { 0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /*check if removed later*/ \
- { 0x0553, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5) }, /*Respond TxOK to scheduler*/ \
- { 0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4) }, /* switch TSF clock to 32K*/ \
- { 0x0109, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(7), BIT(7) }, /*Polling 0x109[7]=1 TSF in 32K*/ \
- { 0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* enable WL_LPS_EN*/
-
-#define HALMAC_RTL8821c_TRANS_LPS_TO_ACT \
- /* format */ \
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
- { 0x0080, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7) }, /*SDIO RPWM*/ \
- { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWRSEQ_DELAY_MS }, /*Delay*/ \
- { 0x0080, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(7), 0 }, /*SDIO RPWM*/ \
- { 0xFE58, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x84 }, /*USB RPWM*/ \
- { 0x0361, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x84 }, /*PCIe RPWM*/ \
- { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWRSEQ_DELAY_MS }, /*Delay*/ \
- { 0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), 0 }, /*. 0x08[4] = 0 switch TSF to 40M*/ \
- { 0x0109, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(7), 0 }, /*Polling 0x109[7]=0 TSF in 40M*/ \
- { 0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1) }, /*. 0x101[1] = 1*/ \
- { 0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/ \
- { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0) }, /*. 0x02[1:0] = 2b'11 enable BB macro*/ \
- { 0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0 }, /*. 0x522 = 0*/ \
- { 0x113C, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x03 }, /*clear RPWM INT*/ \
- { 0x0124, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*clear FW INT*/ \
- { 0x0125, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*clear FW INT*/ \
- { 0x0126, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*clear FW INT*/ \
- { 0x0127, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*clear FW INT*/ \
- { 0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /* disable reg use 32K CLK*/ \
- { 0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), 0 }, /*disable 32k calibration and thermal meter*/
-
-#define HALMAC_RTL8821c_TRANS_END \
- /* format */ \
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
- { 0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0 }, /* */
-
-
-extern HALMAC_WLAN_PWR_CFG halmac_8821c_power_on_flow[HALMAC_8821c_TRANS_CARDEMU_TO_ACT_STEPS + HALMAC_8821c_TRANS_END_STEPS];
-extern HALMAC_WLAN_PWR_CFG halmac_8821c_radio_off_flow[HALMAC_8821c_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8821c_TRANS_END_STEPS];
-extern HALMAC_WLAN_PWR_CFG halmac_8821c_card_disable_flow[HALMAC_8821c_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8821c_TRANS_CARDEMU_TO_PDN_STEPS + HALMAC_8821c_TRANS_END_STEPS];
-extern HALMAC_WLAN_PWR_CFG halmac_8821c_card_enable_flow[HALMAC_8821c_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8821c_TRANS_CARDEMU_TO_PDN_STEPS + HALMAC_8821c_TRANS_END_STEPS];
-extern HALMAC_WLAN_PWR_CFG halmac_8821c_suspend_flow[HALMAC_8821c_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8821c_TRANS_CARDEMU_TO_SUS_STEPS + HALMAC_8821c_TRANS_END_STEPS];
-extern HALMAC_WLAN_PWR_CFG halmac_8821c_resume_flow[HALMAC_8821c_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8821c_TRANS_CARDEMU_TO_SUS_STEPS + HALMAC_8821c_TRANS_END_STEPS];
-extern HALMAC_WLAN_PWR_CFG halmac_8821c_hwpdn_flow[HALMAC_8821c_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8821c_TRANS_CARDEMU_TO_PDN_STEPS + HALMAC_8821c_TRANS_END_STEPS];
-extern HALMAC_WLAN_PWR_CFG halmac_8821c_enter_lps_flow[HALMAC_8821c_TRANS_ACT_TO_LPS_STEPS + HALMAC_8821c_TRANS_END_STEPS];
-extern HALMAC_WLAN_PWR_CFG halmac_8821c_enter_deep_lps_flow[HALMAC_8821c_TRANS_ACT_TO_DEEP_LPS_STEPS + HALMAC_8821c_TRANS_END_STEPS];
-extern HALMAC_WLAN_PWR_CFG halmac_8821c_leave_lps_flow[HALMAC_8821c_TRANS_LPS_TO_ACT_STEPS + HALMAC_8821c_TRANS_END_STEPS];
-
-#endif
diff --git a/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c.h b/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c.h
deleted file mode 100644
index c244cd3..0000000
--- a/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c.h
+++ /dev/null
@@ -1,23 +0,0 @@
-#ifndef _HALMAC_API_8821C_H_
-#define _HALMAC_API_8821C_H_
-
-#include "../../halmac_2_platform.h"
-#include "../../halmac_type.h"
-
-HALMAC_RET_STATUS
-halmac_mount_api_8821c(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-HALMAC_RET_STATUS
-halmac_init_trx_cfg_8821C(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_TRX_MODE halmac_trx_mode
-);
-
-HALMAC_RET_STATUS
-halmac_init_h2c_8821c(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-#endif/* _HALMAC_API_8821C_H_ */
diff --git a/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_pcie.h b/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_pcie.h
deleted file mode 100644
index 0100303..0000000
--- a/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_pcie.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef _HALMAC_API_8821C_PCIE_H_
-#define _HALMAC_API_8821C_PCIE_H_
-
-#include "../../halmac_2_platform.h"
-#include "../../halmac_type.h"
-
-HALMAC_RET_STATUS
-halmac_mac_power_switch_8821c_pcie(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_MAC_POWER halmac_power
-);
-
-#endif/* _HALMAC_API_8821C_PCIE_H_ */
diff --git a/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_sdio.h b/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_sdio.h
deleted file mode 100644
index baa7f47..0000000
--- a/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_sdio.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef _HALMAC_API_8821C_SDIO_H_
-#define _HALMAC_API_8821C_SDIO_H_
-
-#include "../../halmac_2_platform.h"
-#include "../../halmac_type.h"
-
-HALMAC_RET_STATUS
-halmac_mac_power_switch_8821c_sdio(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_MAC_POWER halmac_power
-);
-
-HALMAC_RET_STATUS
-halmac_tx_allowed_sdio_8821c(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pHalmac_buf,
- IN u32 halmac_size
-);
-
-#endif/* _HALMAC_API_8821C_SDIO_H_ */
diff --git a/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_usb.h b/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_usb.h
deleted file mode 100644
index ea1be95..0000000
--- a/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_usb.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef _HALMAC_API_8821C_USB_H_
-#define _HALMAC_API_8821C_USB_H_
-
-#include "../../halmac_2_platform.h"
-#include "../../halmac_type.h"
-
-HALMAC_RET_STATUS
-halmac_mac_power_switch_8821c_usb(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_MAC_POWER halmac_power
-);
-#endif/* _HALMAC_API_8821C_USB_H_ */
diff --git a/hal/halmac/halmac_88xx/halmac_8821c/halmac_func_8821c.h b/hal/halmac/halmac_88xx/halmac_8821c/halmac_func_8821c.h
deleted file mode 100644
index 3c0364c..0000000
--- a/hal/halmac/halmac_88xx/halmac_8821c/halmac_func_8821c.h
+++ /dev/null
@@ -1,19 +0,0 @@
-#ifndef _HALMAC_FUNC_8821C_H_
-#define _HALMAC_FUNC_8821C_H_
-
-#include "../../halmac_type.h"
-
-HALMAC_RET_STATUS
-halmac_txdma_queue_mapping_8821c(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_TRX_MODE halmac_trx_mode
-);
-
-
-HALMAC_RET_STATUS
-halmac_priority_queue_config_8821c(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_TRX_MODE halmac_trx_mode
-);
-
-#endif /* _HALMAC_FUNC_8821C_H_ */
diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_cfg.h b/hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_cfg.h
index 36537ed..b88755a 100644
--- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_cfg.h
+++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_cfg.h
@@ -1,138 +1,73 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
#ifndef _HALMAC_8822B_CFG_H_
#define _HALMAC_8822B_CFG_H_
-#include "halmac_8822b_pwr_seq.h"
-#include "halmac_api_8822b.h"
-#include "halmac_api_8822b_usb.h"
-#include "halmac_api_8822b_sdio.h"
-#include "halmac_api_8822b_pcie.h"
-#include "../../halmac_bit2.h"
-#include "../../halmac_reg2.h"
-#include "../../halmac_api.h"
-
-#if HALMAC_PLATFORM_TESTPROGRAM
-#include "halmisc_api_8822b.h"
-#include "halmisc_api_8822b_usb.h"
-#include "halmisc_api_8822b_sdio.h"
-#include "halmisc_api_8822b_pcie.h"
-#endif
-
-#define HALMAC_TX_FIFO_SIZE_8822B 262144 /* 256k */
-#define HALMAC_TX_FIFO_SIZE_LA_8822B 131072 /* 128k */
-#define HALMAC_RX_FIFO_SIZE_8822B 24320 /* 24k */
-#define HALMAC_TX_PAGE_SIZE_8822B 128 /* PageSize 128Byte */
-#define HALMAC_TX_PAGE_SIZE_2_POWER_8822B 7 /* 128 = 2^7 */
-#define HALMAC_SECURITY_CAM_ENTRY_NUM_8822B 64 /* CAM Entry Size */
-#define HALMAC_TX_AGG_ALIGNMENT_SIZE_8822B 8
-#define HALMAC_TX_DESC_SIZE_8822B 48
-#define HALMAC_RX_DESC_SIZE_8822B 24
-#define HALMAC_WOWLAN_PATTERN_SIZE_8822B 256
-
-/*
-* TXFIFO LAYOUT
-* HIGH_QUEUE
-* NORMAL_QUEUE
-* LOW_QUEUE
-* EXTRA_QUEUE
-* PUBLIC_QUEUE -- decided after all other queue are defined
-* GAP_QUEUE -- Used to separate AC queue and Rsvd page
-*
-* RSVD_DRIVER -- Driver used rsvd page area
-* RSVD_H2C_EXTRAINFO -- Extra Information for h2c
-* RSVD_H2C_QUEUE -- h2c queue in rsvd page
-* RSVD_CPU_INSTRUCTION -- extend fw code
-* RSVD_FW_TXBUFF -- fw used this area to send packet
-*
-* Symbol : HALMAC_MODE_QUEUE_UNIT_CHIP, ex: HALMAC_LB_2BULKOUT_FWCMD_PGNUM_8822B
-*/
-#define HALMAC_EXTRA_INFO_BUFF_SIZE_FULL_FIFO_8822B 16384 /*16K, only used in init case*/
-
-#define HALMAC_RSVD_DRV_PGNUM_8822B 16 /*2048*/
-#define HALMAC_RSVD_H2C_EXTRAINFO_PGNUM_8822B 32 /*4096*/
-#define HALMAC_RSVD_H2C_QUEUE_PGNUM_8822B 8 /*1024*/
-#define HALMAC_RSVD_CPU_INSTRUCTION_PGNUM_8822B 0 /*0*/
-#define HALMAC_RSVD_FW_TXBUFF_PGNUM_8822B 4 /*512*/
-
-/*
-* Normal mode
-*/
-#define HALMAC_NORMAL_HPQ_PGNUM_8822B 64 /*8192*/
-#define HALMAC_NORMAL_NPQ_PGNUM_8822B 64 /*8192*/
-#define HALMAC_NORMAL_LPQ_PGNUM_8822B 64 /*8192*/
-#define HALMAC_NORMAL_EXPQ_PGNUM_8822B 64 /*8192*/
-#define HALMAC_NORMAL_GAP_PGNUM_8822B 1 /*128*/
+#include "../../halmac_hw_cfg.h"
+#include "../halmac_88xx_cfg.h"
-/*
-* Loopback mode
-*/
-#define HALMAC_LB_HPQ_PGNUM_8822B 64 /*8192*/
-#define HALMAC_LB_NPQ_PGNUM_8822B 64 /*8192*/
-#define HALMAC_LB_LPQ_PGNUM_8822B 64 /*8192*/
-#define HALMAC_LB_EXPQ_PGNUM_8822B 64 /*8192*/
-#define HALMAC_LB_GAP_PGNUM_8822B 640 /*81920*/
+#if HALMAC_8822B_SUPPORT
-/*
-* Normal mode - 2Bulkout
-*/
-#define HALMAC_NORMAL_2BULKOUT_HPQ_PGNUM_8822B 64 /*8192*/
-#define HALMAC_NORMAL_2BULKOUT_NPQ_PGNUM_8822B 64 /*8192*/
-#define HALMAC_NORMAL_2BULKOUT_LPQ_PGNUM_8822B 0 /*0*/
-#define HALMAC_NORMAL_2BULKOUT_EXPQ_PGNUM_8822B 0 /*0*/
-#define HALMAC_NORMAL_2BULKOUT_GAP_PGNUM_8822B 1 /*128*/
+#define TX_FIFO_SIZE_8822B 262144
+#define RX_FIFO_SIZE_8822B 24576
+#define TRX_SHARE_SIZE_8822B 65536
-/*
-* Loopback mode - 2Bulkout
-*/
-#define HALMAC_LB_2BULKOUT_HPQ_PGNUM_8822B 64 /*8192*/
-#define HALMAC_LB_2BULKOUT_NPQ_PGNUM_8822B 64 /*8192*/
-#define HALMAC_LB_2BULKOUT_LPQ_PGNUM_8822B 0 /*0*/
-#define HALMAC_LB_2BULKOUT_EXPQ_PGNUM_8822B 0 /*0*/
-#define HALMAC_LB_2BULKOUT_GAP_PGNUM_8822B 1024 /*131072*/
+#define RX_DESC_DUMMY_SIZE_8822B 72 /* 8 * 9 Bytes */
+#define RX_FIFO_EXPANDING_MODE_PKT_SIZE_MAX_8822B 80 /* 8 Byte alignment*/
-/*
-* Normal mode - 3BULKOUT
-*/
-#define HALMAC_NORMAL_3BULKOUT_HPQ_PGNUM_8822B 64 /*8192*/
-#define HALMAC_NORMAL_3BULKOUT_NPQ_PGNUM_8822B 64 /*8192*/
-#define HALMAC_NORMAL_3BULKOUT_LPQ_PGNUM_8822B 64 /*8192*/
-#define HALMAC_NORMAL_3BULKOUT_EXPQ_PGNUM_8822B 0 /*0*/
-#define HALMAC_NORMAL_3BULKOUT_GAP_PGNUM_8822B 1 /*128*/
-
-/*
-* Loopback mode - 3BULKOUT
-*/
-#define HALMAC_LB_3BULKOUT_HPQ_PGNUM_8822B 64 /*8192*/
-#define HALMAC_LB_3BULKOUT_NPQ_PGNUM_8822B 64 /*8192*/
-#define HALMAC_LB_3BULKOUT_LPQ_PGNUM_8822B 64 /*8192*/
-#define HALMAC_LB_3BULKOUT_EXPQ_PGNUM_8822B 0 /*0*/
-#define HALMAC_LB_3BULKOUT_GAP_PGNUM_8822B 1024 /*131072*/
-
-/*
-* WMM mode
-*/
-#define HALMAC_WMM_HPQ_PGNUM_8822B 64 /*8192*/
-#define HALMAC_WMM_NPQ_PGNUM_8822B 64 /*8192*/
-#define HALMAC_WMM_LPQ_PGNUM_8822B 64 /*8192*/
-#define HALMAC_WMM_EXPQ_PGNUM_8822B 64 /*8192*/
-#define HALMAC_WMM_GAP_PGNUM_8822B 1 /*128*/
-
-#define HALMAC_EFUSE_SIZE_8822B 1024 /* 0x400 */
-#define HALMAC_BT_EFUSE_SIZE_8822B 128 /* 0x80 */
-#define HALMAC_EEPROM_SIZE_8822B 0x300
-#define HALMAC_CR_TRX_ENABLE_8822B (BIT_HCI_TXDMA_EN | BIT_HCI_RXDMA_EN | BIT_TXDMA_EN | \
- BIT_RXDMA_EN | BIT_PROTOCOL_EN | BIT_SCHEDULE_EN | \
- BIT_MACTXEN | BIT_MACRXEN)
-
-#define HALMAC_BLK_DESC_NUM_8822B 0x3 /* Only for USB */
-
-typedef enum _HALMAC_NORMAL_RXAGG_TH_TO_8822B {
- HALMAC_NORMAL_RXAGG_THRESHOLD_8822B = 0xFF,
- HALMAC_NORMAL_RXAGG_TIMEOUT_8822B = 0x01,
-} HALMAC_NORMAL_RXAGG_TH_TO_8822B;
+/* should be 8 Byte alignment*/
+#if (HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE <= \
+ RX_FIFO_EXPANDING_MODE_PKT_SIZE_MAX_8822B)
+#define RX_FIFO_EXPANDING_UNIT_8822B (RX_DESC_SIZE_88XX + \
+ RX_DESC_DUMMY_SIZE_8822B + HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE)
+#else
+#define RX_FIFO_EXPANDING_UNIT_8822B (RX_DESC_SIZE_88XX + \
+ RX_DESC_DUMMY_SIZE_8822B + RX_FIFO_EXPANDING_MODE_PKT_SIZE_MAX_8822B)
+#endif
-typedef enum _HALMAC_LOOPBACK_RXAGG_TH_TO_8822B {
- HALMAC_LOOPBACK_RXAGG_THRESHOLD_8822B = 0xFF,
- HALMAC_LOOPBACK_RXAGG_TIMEOUT_8822B = 0x01,
-} HALMAC_LOOPBACK_RXAGG_TH_TO_8822B;
+#define TX_FIFO_SIZE_LA_8822B (TX_FIFO_SIZE_8822B >> 1)
+#define TX_FIFO_SIZE_RX_EXPAND_1BLK_8822B \
+ (TX_FIFO_SIZE_8822B - TRX_SHARE_SIZE_8822B)
+#define RX_FIFO_SIZE_RX_EXPAND_1BLK_8822B \
+ ((((RX_FIFO_EXPANDING_UNIT_8822B << 8) - 1) >> 10) << 10)
+#define TX_FIFO_SIZE_RX_EXPAND_2BLK_8822B \
+ (TX_FIFO_SIZE_8822B - (2 * TRX_SHARE_SIZE_8822B))
+#define RX_FIFO_SIZE_RX_EXPAND_2BLK_8822B \
+ (RX_FIFO_SIZE_8822B + (2 * TRX_SHARE_SIZE_8822B))
+#define TX_FIFO_SIZE_RX_EXPAND_3BLK_8822B \
+ (TX_FIFO_SIZE_8822B - (3 * TRX_SHARE_SIZE_8822B))
+#define RX_FIFO_SIZE_RX_EXPAND_3BLK_8822B \
+ (RX_FIFO_SIZE_8822B + (3 * TRX_SHARE_SIZE_8822B))
+
+#define EFUSE_SIZE_8822B 1024
+#define EEPROM_SIZE_8822B 768
+#define BT_EFUSE_SIZE_8822B 128
+
+#define SEC_CAM_NUM_8822B 64
+
+#define OQT_ENTRY_AC_8822B 32
+#define OQT_ENTRY_NOAC_8822B 32
+#define MACID_MAX_8822B 128
+
+#define WLAN_FW_IRAM_MAX_SIZE_8822B 196608
+#define WLAN_FW_DRAM_MAX_SIZE_8822B 49152
+#define WLAN_FW_ERAM_MAX_SIZE_8822B 0
+#define WLAN_FW_MAX_SIZE_8822B (WLAN_FW_IRAM_MAX_SIZE_8822B + \
+ WLAN_FW_DRAM_MAX_SIZE_8822B + WLAN_FW_ERAM_MAX_SIZE_8822B)
+
+#endif /* HALMAC_8822B_SUPPORT*/
#endif
diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_pwr_seq.c b/hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_pwr_seq.c
deleted file mode 100644
index c26c88d..0000000
--- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_pwr_seq.c
+++ /dev/null
@@ -1,76 +0,0 @@
-#include "../halmac_88xx_cfg.h"
-#include "halmac_8822b_cfg.h"
-
-/*
- * drivers should parse below arrays and do the corresponding actions
- */
-/* 3 Power on Array */
-HALMAC_WLAN_PWR_CFG halmac_8822b_power_on_flow[] = {
- HALMAC_RTL8822B_TRANS_CARDEMU_TO_ACT
- HALMAC_RTL8822B_TRANS_END
-};
-
-/* 3 Radio off GPIO Array */
-HALMAC_WLAN_PWR_CFG halmac_8822b_radio_off_flow[] = {
- HALMAC_RTL8822B_TRANS_ACT_TO_CARDEMU
- HALMAC_RTL8822B_TRANS_END
-};
-
-/* 3 Card Disable Array */
-HALMAC_WLAN_PWR_CFG halmac_8822b_card_disable_flow[HALMAC_8822B_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8822B_TRANS_CARDEMU_TO_PDN_STEPS + HALMAC_8822B_TRANS_END_STEPS] = {
- HALMAC_RTL8822B_TRANS_ACT_TO_CARDEMU
- HALMAC_RTL8822B_TRANS_CARDEMU_TO_CARDDIS
- HALMAC_RTL8822B_TRANS_END
-};
-
-/* 3 Card Enable Array */
-HALMAC_WLAN_PWR_CFG halmac_8822b_card_enable_flow[HALMAC_8822B_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8822B_TRANS_CARDEMU_TO_PDN_STEPS + HALMAC_8822B_TRANS_END_STEPS] = {
- HALMAC_RTL8822B_TRANS_CARDDIS_TO_CARDEMU
- HALMAC_RTL8822B_TRANS_CARDEMU_TO_ACT
- HALMAC_RTL8822B_TRANS_END
-};
-
-/* 3 Suspend Array */
-HALMAC_WLAN_PWR_CFG halmac_8822b_suspend_flow[HALMAC_8822B_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8822B_TRANS_CARDEMU_TO_SUS_STEPS + HALMAC_8822B_TRANS_END_STEPS] = {
- HALMAC_RTL8822B_TRANS_ACT_TO_CARDEMU
- HALMAC_RTL8822B_TRANS_CARDEMU_TO_SUS
- HALMAC_RTL8822B_TRANS_END
-};
-
-/* 3 Resume Array */
-HALMAC_WLAN_PWR_CFG halmac_8822b_resume_flow[HALMAC_8822B_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8822B_TRANS_CARDEMU_TO_SUS_STEPS + HALMAC_8822B_TRANS_END_STEPS] = {
- HALMAC_RTL8822B_TRANS_SUS_TO_CARDEMU
- HALMAC_RTL8822B_TRANS_CARDEMU_TO_ACT
- HALMAC_RTL8822B_TRANS_END
-};
-
-
-
-/* 3HWPDN Array */
-HALMAC_WLAN_PWR_CFG halmac_8822b_hwpdn_flow[HALMAC_8822B_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8822B_TRANS_CARDEMU_TO_PDN_STEPS + HALMAC_8822B_TRANS_END_STEPS] = {
- /* TRANS_ACT_TO_CARDEMU */
- /* TRANS_CARDEMU_TO_PDN */
- /* HW behavior */
- HALMAC_RTL8822B_TRANS_END
-};
-
-/* 3 Enter LPS */
-HALMAC_WLAN_PWR_CFG halmac_8822b_enter_lps_flow[HALMAC_8822B_TRANS_ACT_TO_LPS_STEPS + HALMAC_8822B_TRANS_END_STEPS] = {
- /* FW behavior */
- HALMAC_RTL8822B_TRANS_ACT_TO_LPS
- HALMAC_RTL8822B_TRANS_END
-};
-
-/* 3 Enter Deep LPS */
-HALMAC_WLAN_PWR_CFG halmac_8822b_enter_deep_lps_flow[HALMAC_8822B_TRANS_ACT_TO_DEEP_LPS_STEPS + HALMAC_8822B_TRANS_END_STEPS] = {
- /* FW behavior */
- HALMAC_RTL8822B_TRANS_ACT_TO_DEEP_LPS
- HALMAC_RTL8822B_TRANS_END
-};
-
-/* 3 Leave LPS */
-HALMAC_WLAN_PWR_CFG halmac_8822b_leave_lps_flow[HALMAC_8822B_TRANS_LPS_TO_ACT_STEPS + HALMAC_8822B_TRANS_END_STEPS] = {
- /* FW behavior */
- HALMAC_RTL8822B_TRANS_LPS_TO_ACT
- HALMAC_RTL8822B_TRANS_END
-};
diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_pwr_seq.h b/hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_pwr_seq.h
deleted file mode 100644
index 5f97169..0000000
--- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_8822b_pwr_seq.h
+++ /dev/null
@@ -1,227 +0,0 @@
-#ifndef HALMAC_POWER_SEQUENCE_8822B
-#define HALMAC_POWER_SEQUENCE_8822B
-
-#include "../../halmac_pwr_seq_cmd.h"
-
-/*
- * Check document WM-20151103-v02-JackieLau-RTL8822B_Power_Architecture.vsd
- * There are 6 HW Power States:
- * 0: POFF--Power Off
- * 1: PDN--Power Down
- * 2: CARDEMU--Card Emulation
- * 3: ACT--Active Mode
- * 4: LPS--Low Power State
- * 5: SUS--Suspend
- *
- * The transition from different states are defined below
- * TRANS_CARDEMU_TO_ACT
- * TRANS_ACT_TO_CARDEMU
- * TRANS_CARDEMU_TO_SUS
- * TRANS_SUS_TO_CARDEMU
- * TRANS_CARDEMU_TO_PDN
- * TRANS_ACT_TO_LPS
- * TRANS_LPS_TO_ACT
- *
- * TRANS_END
- */
-
-#define HALMAC_8822B_TRANS_CARDEMU_TO_ACT_STEPS 25
-#define HALMAC_8822B_TRANS_ACT_TO_CARDEMU_STEPS 15
-#define HALMAC_8822B_TRANS_CARDEMU_TO_SUS_STEPS 15
-#define HALMAC_8822B_TRANS_SUS_TO_CARDEMU_STEPS 15
-#define HALMAC_8822B_TRANS_CARDEMU_TO_PDN_STEPS 15
-#define HALMAC_8822B_TRANS_PDN_TO_CARDEMU_STEPS 15
-#define HALMAC_8822B_TRANS_ACT_TO_LPS_STEPS 25
-#define HALMAC_8822B_TRANS_ACT_TO_DEEP_LPS_STEPS 25
-#define HALMAC_8822B_TRANS_LPS_TO_ACT_STEPS 20
-#define HALMAC_8822B_TRANS_END_STEPS 1
-
-
-#define HALMAC_RTL8822B_TRANS_CARDEMU_TO_ACT \
- /* format */ \
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
- { 0x0020, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \
- { 0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), 0 }, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \
- { 0x0001, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 1, HALMAC_PWRSEQ_DELAY_MS }, /*Delay 1ms*/ \
- { 0x0000, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), 0 }, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0 }, /* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[12:11]=0*/ \
- { 0x0075, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* Disable USB suspend */ \
- { 0x0004, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3) }, /* enabled usb resume */ \
- { 0x0004, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), 0 }, /* disable usb resume */ \
- { 0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1) }, /* wait till 0x04[17] = 1 power ready*/ \
- { 0x0075, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /* Enable USB suspend */ \
- { 0xFF1A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0 }, /*0xFF1A = 0 to release resume signals*/ \
- { 0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* release WLON reset 0x04[16]=1*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), 0 }, /* disable HWPDN 0x04[15]=0*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0 }, /* disable WL suspend*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* polling until return 0*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(0), 0 }, /**/ \
- { 0x0020, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3) }, /*Enable XTAL_CLK*/ \
- { 0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5) }, /*0x67[5]=1 , BIT_PAPE_WLBT_SEL*/ \
-
-#define HALMAC_RTL8822B_TRANS_ACT_TO_CARDEMU \
- /* format */ \
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
- { 0x001F, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0 }, /*0x1F[7:0] = 0 turn off RF*/ \
- { 0x00EF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0 }, /*0xEF[7:0] = 0 turn off RF*/ \
- { 0xFF1A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x30 }, /*0xFF1A = 0x30 to block resume signals*/ \
- { 0x0049, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /*Enable rising edge triggering interrupt*/ \
- { 0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* release WLON reset 0x04[16]=1*/ \
- { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /* Whole BB is reset */ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1) }, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(1), 0 }, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
- { 0x0020, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), 0 }, /* XTAL_CLK gated*/ \
- { 0x0000, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5) }, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \
-
-#define HALMAC_RTL8822B_TRANS_CARDEMU_TO_SUS \
- /* format */ \
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3)) }, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) }, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
- { 0x0007, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20 }, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4) }, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
- { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /*Set SDIO suspend local register*/ \
- { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), 0 }, /*wait power state to suspend*/
-
-#define HALMAC_RTL8822B_TRANS_SUS_TO_CARDEMU \
- /* format */ \
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(7), 0 }, /*clear suspend enable and power down enable*/ \
- { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /*Set SDIO suspend local register*/ \
- { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1) }, /*wait power state to suspend*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), 0 }, /*0x04[12:11] = 2b'01enable WL suspend*/
-
-#define HALMAC_RTL8822B_TRANS_CARDEMU_TO_CARDDIS \
- /* format */ \
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
- { 0x0007, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20 }, /*0x07=0x20 , SOP option to disable BG/MB*/ \
- { 0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), 0 }, /*0x67[5]=0 , BIT_PAPE_WLBT_SEL*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) }, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2) }, /*0x04[10] = 1, enable SW LPS*/ \
- { 0x004A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \
- { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /*Set SDIO suspend local register*/ \
- { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), 0 }, /*wait power state to suspend*/ \
- { 0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /*0x90[1]=0 , disable 32k clock*/ \
- { 0x0044, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, 0xFF, 0 }, /*0x90[1]=0 , disable 32k clock by indirect access*/ \
- { 0x0040, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, 0xFF, 0x90 }, /*0x90[1]=0 , disable 32k clock by indirect access*/ \
- { 0x0041, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, 0xFF, 0x00 }, /*0x90[1]=0 , disable 32k clock by indirect access*/ \
- { 0x0042, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, 0xFF, 0x04 }, /*0x90[1]=0 , disable 32k clock by indirect access*/
-
-#define HALMAC_RTL8822B_TRANS_CARDDIS_TO_CARDEMU \
- /* format */ \
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(7), 0 }, /*clear suspend enable and power down enable*/ \
- { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /*Set SDIO suspend local register*/ \
- { 0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1) }, /*wait power state to suspend*/ \
- { 0x004A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), 0 }, /*0x04[12:11] = 2b'01enable WL suspend*/ \
- { 0x0301, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0 }, /*PCIe DMA start*/
-
-
-#define HALMAC_RTL8822B_TRANS_CARDEMU_TO_PDN \
- /* format */ \
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
- { 0x0007, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK | HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20 }, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \
- { 0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /* 0x04[16] = 0*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7) }, /* 0x04[15] = 1*/
-
-#define HALMAC_RTL8822B_TRANS_PDN_TO_CARDEMU \
- /* format */ \
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
- { 0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), 0 },/* 0x04[15] = 0*/
-
-#define HALMAC_RTL8822B_TRANS_ACT_TO_LPS \
- /* format */ \
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
- { 0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2) }, /*Enable 32k calibration and thermal meter*/ \
- { 0x0199, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3) }, /*Register write data of 32K calibration*/ \
- { 0x019B, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7) }, /*Enable 32k calibration reg write*/ \
- { 0x1138, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0) | BIT(1), BIT(0) | BIT(1) }, /*set RPWM IMR*/ \
- { 0x0194, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* enable 32K CLK*/ \
- { 0x0093, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x42 }, /* LPS Option MAC OFF enable*/ \
- { 0x0092, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20 }, /* LPS Option Enable memory to deep sleep mode*/ \
- { 0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1) }, /* enable reg use 32K CLK*/ \
- { 0x0301, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*PCIe DMA stop*/ \
- { 0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*Tx Pause*/ \
- { 0x05F8, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0 }, /*Should be zero if no packet is transmitting*/ \
- { 0x05F9, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0 }, /*Should be zero if no packet is transmitting*/ \
- { 0x05FA, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0 }, /*Should be zero if no packet is transmitting*/ \
- { 0x05FB, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0 }, /*Should be zero if no packet is transmitting*/ \
- { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /*CCK and OFDM are disabled,and clock are gated*/ \
- { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWRSEQ_DELAY_US }, /*Delay 1us*/ \
- { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /*Whole BB is reset*/ \
- { 0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x3F }, /*Reset MAC TRX*/ \
- { 0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /*check if removed later*/ \
- { 0x0553, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5) }, /*Respond TxOK to scheduler*/ \
- { 0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4) }, /* switch TSF clock to 32K*/ \
- { 0x0109, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(7), BIT(7) }, /*Polling 0x109[7]=0 TSF in 40M*/ \
- { 0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* enable WL_LPS_EN*/
-
-#define HALMAC_RTL8822B_TRANS_ACT_TO_DEEP_LPS \
- /* format */ \
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
- { 0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2) }, /*Enable 32k calibration and thermal meter*/ \
- { 0x0199, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3) }, /*Register write data of 32K calibration*/ \
- { 0x019B, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7) }, /*Enable 32k calibration reg write*/ \
- { 0x1138, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0) | BIT(1), BIT(0) | BIT(1) }, /*set RPWM IMR*/ \
- { 0x0194, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* enable 32K CLK*/ \
- { 0x0093, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x40 }, /* LPS Option MAC OFF enable*/ \
- { 0x0092, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20 }, /* LPS Option Enable memory to deep sleep mode*/ \
- { 0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1) }, /* enable reg use 32K CLK*/ \
- { 0x0301, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*PCIe DMA stop*/ \
- { 0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*Tx Pause*/ \
- { 0x05F8, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0 }, /*Should be zero if no packet is transmitting*/ \
- { 0x05F9, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0 }, /*Should be zero if no packet is transmitting*/ \
- { 0x05FA, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0 }, /*Should be zero if no packet is transmitting*/ \
- { 0x05FB, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0 }, /*Should be zero if no packet is transmitting*/ \
- { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /*CCK and OFDM are disabled,and clock are gated*/ \
- { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWRSEQ_DELAY_US }, /*Delay 1us*/ \
- { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /*Whole BB is reset*/ \
- { 0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x3F }, /*Reset MAC TRX*/ \
- { 0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /*check if removed later*/ \
- { 0x0553, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5) }, /*Respond TxOK to scheduler*/ \
- { 0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4) }, /* switch TSF clock to 32K*/ \
- { 0x0109, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(7), BIT(7) }, /*Polling 0x109[7]=1 TSF in 32K*/ \
- { 0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0) }, /* enable WL_LPS_EN*/
-
-#define HALMAC_RTL8822B_TRANS_LPS_TO_ACT \
- /* format */ \
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
- { 0x0080, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7) }, /*SDIO RPWM*/ \
- { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWRSEQ_DELAY_MS }, /*Delay*/ \
- { 0x0080, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(7), 0 }, /*SDIO RPWM*/ \
- { 0xFE58, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x84 }, /*USB RPWM*/ \
- { 0x0361, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x84 }, /*PCIe RPWM*/ \
- { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWRSEQ_DELAY_MS }, /*Delay*/ \
- { 0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), 0 }, /*. 0x08[4] = 0 switch TSF to 40M*/ \
- { 0x0109, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(7), 0 }, /*Polling 0x109[7]=0 TSF in 40M*/ \
- { 0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1) }, /*. 0x101[1] = 1*/ \
- { 0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/ \
- { 0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0) }, /*. 0x02[1:0] = 2b'11 enable BB macro*/ \
- { 0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0 }, /*. 0x522 = 0*/ \
- { 0x113C, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x03 }, /*clear RPWM INT*/ \
- { 0x0124, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*clear FW INT*/ \
- { 0x0125, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*clear FW INT*/ \
- { 0x0126, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*clear FW INT*/ \
- { 0x0127, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*clear FW INT*/ \
- { 0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /* disable reg use 32K CLK*/ \
- { 0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), 0 }, /*disable 32k calibration and thermal meter*/
-
-#define HALMAC_RTL8822B_TRANS_END \
- /* format */ \
- /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
- { 0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0 }, /* */
-
-
-extern HALMAC_WLAN_PWR_CFG halmac_8822b_power_on_flow[HALMAC_8822B_TRANS_CARDEMU_TO_ACT_STEPS + HALMAC_8822B_TRANS_END_STEPS];
-extern HALMAC_WLAN_PWR_CFG halmac_8822b_radio_off_flow[HALMAC_8822B_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8822B_TRANS_END_STEPS];
-extern HALMAC_WLAN_PWR_CFG halmac_8822b_card_disable_flow[HALMAC_8822B_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8822B_TRANS_CARDEMU_TO_PDN_STEPS + HALMAC_8822B_TRANS_END_STEPS];
-extern HALMAC_WLAN_PWR_CFG halmac_8822b_card_enable_flow[HALMAC_8822B_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8822B_TRANS_CARDEMU_TO_PDN_STEPS + HALMAC_8822B_TRANS_END_STEPS];
-extern HALMAC_WLAN_PWR_CFG halmac_8822b_suspend_flow[HALMAC_8822B_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8822B_TRANS_CARDEMU_TO_SUS_STEPS + HALMAC_8822B_TRANS_END_STEPS];
-extern HALMAC_WLAN_PWR_CFG halmac_8822b_resume_flow[HALMAC_8822B_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8822B_TRANS_CARDEMU_TO_SUS_STEPS + HALMAC_8822B_TRANS_END_STEPS];
-extern HALMAC_WLAN_PWR_CFG halmac_8822b_hwpdn_flow[HALMAC_8822B_TRANS_ACT_TO_CARDEMU_STEPS + HALMAC_8822B_TRANS_CARDEMU_TO_PDN_STEPS + HALMAC_8822B_TRANS_END_STEPS];
-extern HALMAC_WLAN_PWR_CFG halmac_8822b_enter_lps_flow[HALMAC_8822B_TRANS_ACT_TO_LPS_STEPS + HALMAC_8822B_TRANS_END_STEPS];
-extern HALMAC_WLAN_PWR_CFG halmac_8822b_enter_deep_lps_flow[HALMAC_8822B_TRANS_ACT_TO_DEEP_LPS_STEPS + HALMAC_8822B_TRANS_END_STEPS];
-extern HALMAC_WLAN_PWR_CFG halmac_8822b_leave_lps_flow[HALMAC_8822B_TRANS_LPS_TO_ACT_STEPS + HALMAC_8822B_TRANS_END_STEPS];
-
-#endif
diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b.c b/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b.c
deleted file mode 100644
index 440eec1..0000000
--- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b.c
+++ /dev/null
@@ -1,218 +0,0 @@
-#include "halmac_8822b_cfg.h"
-#include "halmac_func_8822b.h"
-#include "../halmac_func_88xx.h"
-
-
-/**
- * halmac_mount_api_8822b() - attach functions to function pointer
- * @pHalmac_adapter
- *
- * SD1 internal use
- *
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_mount_api_8822b(
- IN PHALMAC_ADAPTER pHalmac_adapter
-)
-{
- PHALMAC_API pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- pHalmac_adapter->chip_id = HALMAC_CHIP_ID_8822B;
- pHalmac_adapter->hw_config_info.efuse_size = HALMAC_EFUSE_SIZE_8822B;
- pHalmac_adapter->hw_config_info.eeprom_size = HALMAC_EEPROM_SIZE_8822B;
- pHalmac_adapter->hw_config_info.bt_efuse_size = HALMAC_BT_EFUSE_SIZE_8822B;
- pHalmac_adapter->hw_config_info.cam_entry_num = HALMAC_SECURITY_CAM_ENTRY_NUM_8822B;
- pHalmac_adapter->hw_config_info.txdesc_size = HALMAC_TX_DESC_SIZE_8822B;
- pHalmac_adapter->hw_config_info.rxdesc_size = HALMAC_RX_DESC_SIZE_8822B;
- pHalmac_adapter->hw_config_info.tx_fifo_size = HALMAC_TX_FIFO_SIZE_8822B;
- pHalmac_adapter->hw_config_info.rx_fifo_size = HALMAC_RX_FIFO_SIZE_8822B;
-
- pHalmac_adapter->txff_allocation.rsvd_drv_pg_num = HALMAC_RSVD_DRV_PGNUM_8822B;
-
-#if HALMAC_8822B_SUPPORT
- pHalmac_api->halmac_init_trx_cfg = halmac_init_trx_cfg_8822b;
- pHalmac_api->halmac_init_h2c = halmac_init_h2c_8822b;
-
- if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface) {
- pHalmac_api->halmac_tx_allowed_sdio = halmac_tx_allowed_sdio_8822b;
- pHalmac_api->halmac_cfg_tx_agg_align = halmac_cfg_tx_agg_align_sdio_not_support_88xx;
- pHalmac_api->halmac_mac_power_switch = halmac_mac_power_switch_8822b_sdio;
- } else if (HALMAC_INTERFACE_USB == pHalmac_adapter->halmac_interface) {
- pHalmac_api->halmac_mac_power_switch = halmac_mac_power_switch_8822b_usb;
- pHalmac_api->halmac_cfg_tx_agg_align = halmac_cfg_tx_agg_align_usb_not_support_88xx;
- } else if (HALMAC_INTERFACE_PCIE == pHalmac_adapter->halmac_interface) {
- pHalmac_api->halmac_mac_power_switch = halmac_mac_power_switch_8822b_pcie;
- pHalmac_api->halmac_cfg_tx_agg_align = halmac_cfg_tx_agg_align_pcie_not_support_88xx;
- }
-#endif
- return HALMAC_RET_SUCCESS;
-}
-
-
-/**
- * halmac_init_trx_cfg_8822b() - config trx dma register
- * @pHalmac_adapter
- * @halmac_trx_mode
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_init_trx_cfg_8822b(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_TRX_MODE halmac_trx_mode
-)
-{
- u8 value8;
- u16 value16;
- u32 value32;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_INIT_TRX_CFG);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
- pHalmac_adapter->trx_mode = halmac_trx_mode;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_trx_cfg ==========>halmac_trx_mode = %d\n", halmac_trx_mode);
-
- status = halmac_txdma_queue_mapping_8822b(pHalmac_adapter, halmac_trx_mode);
-
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_txdma_queue_mapping fail!\n");
- return status;
- }
-
- value8 = 0;
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR, value8);
- value8 = HALMAC_CR_TRX_ENABLE_8822B;
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR, value8);
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_H2CQ_CSR, BIT(31));
- value16 = BIT_MAC_SEC_EN | BIT_32K_CAL_TMR_EN;
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_CR, (u16)(HALMAC_REG_READ_16(pHalmac_adapter, REG_CR) | value16));
-
- status = halmac_priority_queue_config_8822b(pHalmac_adapter, halmac_trx_mode);
-
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_txdma_queue_mapping fail!\n");
- return status;
- }
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Init Network type\n");
-
- value8 = (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_CR + 2) & ~BIT_MASK_NETYPE0);
- value8 = (u8)(value8 | HALMAC_NETWORK_NO_LINK);
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR + 2, value8);
-
- /* Config H2C packet buffer */
- value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_H2C_HEAD);
- value32 = (value32 & 0xFFFC0000) | (pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy << HALMAC_TX_PAGE_SIZE_2_POWER_8822B);
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_H2C_HEAD, value32);
-
- value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_H2C_READ_ADDR);
- value32 = (value32 & 0xFFFC0000) | (pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy << HALMAC_TX_PAGE_SIZE_2_POWER_8822B);
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_H2C_READ_ADDR, value32);
-
- value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_H2C_TAIL);
- value32 = (value32 & 0xFFFC0000) | ((pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy << HALMAC_TX_PAGE_SIZE_2_POWER_8822B) + (HALMAC_RSVD_H2C_QUEUE_PGNUM_8822B << HALMAC_TX_PAGE_SIZE_2_POWER_8822B));
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_H2C_TAIL, value32);
-
- value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_H2C_INFO);
- value8 = (u8)((value8 & 0xFC) | 0x01);
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_H2C_INFO, value8);
-
- value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_H2C_INFO);
- value8 = (u8)((value8 & 0xFB) | 0x04);
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_H2C_INFO, value8);
-
- value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_TXDMA_OFFSET_CHK + 1);
- value8 = (u8)((value8 & 0x7f) | 0x80);
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXDMA_OFFSET_CHK + 1, value8);
-
- pHalmac_adapter->h2c_buff_size = HALMAC_RSVD_H2C_QUEUE_PGNUM_8822B << HALMAC_TX_PAGE_SIZE_2_POWER_8822B;
- halmac_get_h2c_buff_free_space_88xx(pHalmac_adapter);
-
- if (pHalmac_adapter->h2c_buff_size != pHalmac_adapter->h2c_buf_free_space) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "get h2c free space error!\n");
- return HALMAC_RET_GET_H2C_SPACE_ERR;
- }
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_trx_cfg <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_init_h2c_8822b() - config h2c packet buffer
- * @pHalmac_adapter
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_init_h2c_8822b(
- IN PHALMAC_ADAPTER pHalmac_adapter
-)
-{
- u8 value8;
- u32 value32;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- value8 = 0;
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR, value8);
- value8 = HALMAC_CR_TRX_ENABLE_8822B;
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR, value8);
-
- value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_H2C_HEAD);
- value32 = (value32 & 0xFFFC0000) | (pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy << HALMAC_TX_PAGE_SIZE_2_POWER_8822B);
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_H2C_HEAD, value32);
-
- value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_H2C_READ_ADDR);
- value32 = (value32 & 0xFFFC0000) | (pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy << HALMAC_TX_PAGE_SIZE_2_POWER_8822B);
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_H2C_READ_ADDR, value32);
-
- value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_H2C_TAIL);
- value32 = (value32 & 0xFFFC0000) | ((pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy << HALMAC_TX_PAGE_SIZE_2_POWER_8822B) + (HALMAC_RSVD_H2C_QUEUE_PGNUM_8822B << HALMAC_TX_PAGE_SIZE_2_POWER_8822B));
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_H2C_TAIL, value32);
- value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_H2C_INFO);
- value8 = (u8)((value8 & 0xFC) | 0x01);
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_H2C_INFO, value8);
-
- value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_H2C_INFO);
- value8 = (u8)((value8 & 0xFB) | 0x04);
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_H2C_INFO, value8);
-
- value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_TXDMA_OFFSET_CHK + 1);
- value8 = (u8)((value8 & 0x7f) | 0x80);
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXDMA_OFFSET_CHK + 1, value8);
-
- pHalmac_adapter->h2c_buff_size = HALMAC_RSVD_H2C_QUEUE_PGNUM_8822B << HALMAC_TX_PAGE_SIZE_2_POWER_8822B;
- halmac_get_h2c_buff_free_space_88xx(pHalmac_adapter);
-
- if (pHalmac_adapter->h2c_buff_size != pHalmac_adapter->h2c_buf_free_space) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "get h2c free space error!\n");
- return HALMAC_RET_GET_H2C_SPACE_ERR;
- }
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "h2c free space : %d\n", pHalmac_adapter->h2c_buf_free_space);
-
- return HALMAC_RET_SUCCESS;
-}
diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b.h b/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b.h
deleted file mode 100644
index f5a5194..0000000
--- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b.h
+++ /dev/null
@@ -1,24 +0,0 @@
-#ifndef _HALMAC_API_8822B_H_
-#define _HALMAC_API_8822B_H_
-
-#include "../../halmac_2_platform.h"
-#include "../../halmac_type.h"
-
-HALMAC_RET_STATUS
-halmac_mount_api_8822b(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-HALMAC_RET_STATUS
-halmac_init_trx_cfg_8822b(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_TRX_MODE halmac_trx_mode
-);
-
-HALMAC_RET_STATUS
-halmac_init_h2c_8822b(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-
-#endif/* _HALMAC_API_8822B_H_ */
diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_pcie.c b/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_pcie.c
deleted file mode 100644
index 5b09c10..0000000
--- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_pcie.c
+++ /dev/null
@@ -1,68 +0,0 @@
-#include "../halmac_88xx_cfg.h"
-#include "halmac_8822b_cfg.h"
-
-
-/**
- * halmac_mac_power_switch_8822b_pcie() - change mac power
- * @pHalmac_adapter
- * @halmac_power
- * Author : KaiYuan Chang
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_mac_power_switch_8822b_pcie(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_MAC_POWER halmac_power
-)
-{
- u8 interface_mask;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_MAC_POWER_SWITCH);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "halmac_mac_power_switch_88xx_pcie halmac_power = %x ==========>\n", halmac_power);
- interface_mask = HALMAC_PWR_INTF_PCI_MSK;
-
- if (0xEA == HALMAC_REG_READ_8(pHalmac_adapter, REG_CR))
- pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF;
-
- /* Check if power switch is needed */
- if (halmac_power == pHalmac_adapter->halmac_state.mac_power) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_WARN, "halmac_mac_power_switch power state unchange!\n");
- } else {
- if (HALMAC_MAC_POWER_OFF == halmac_power) {
- if (HALMAC_RET_SUCCESS != halmac_pwr_seq_parser_88xx(pHalmac_adapter, HALMAC_PWR_CUT_TESTCHIP_MSK, HALMAC_PWR_FAB_TSMC_MSK,
- interface_mask, halmac_8822b_card_disable_flow)) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "Handle power off cmd error\n");
- return HALMAC_RET_POWER_OFF_FAIL;
- }
-
- pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF;
- pHalmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_UNDEFINE;
- pHalmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE;
- } else {
- if (HALMAC_RET_SUCCESS != halmac_pwr_seq_parser_88xx(pHalmac_adapter, HALMAC_PWR_CUT_TESTCHIP_MSK, HALMAC_PWR_FAB_TSMC_MSK,
- interface_mask, halmac_8822b_card_enable_flow)) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "Handle power on cmd error\n");
- return HALMAC_RET_POWER_ON_FAIL;
- }
-
- pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON;
- pHalmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_ACT;
- }
- }
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "halmac_mac_power_switch_88xx_pcie <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_pcie.h b/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_pcie.h
deleted file mode 100644
index 9c3763f..0000000
--- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_pcie.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef _HALMAC_API_8822B_PCIE_H_
-#define _HALMAC_API_8822B_PCIE_H_
-
-#include "../../halmac_2_platform.h"
-#include "../../halmac_type.h"
-
-HALMAC_RET_STATUS
-halmac_mac_power_switch_8822b_pcie(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_MAC_POWER halmac_power
-);
-
-#endif/* _HALMAC_API_8822B_PCIE_H_ */
diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_sdio.c b/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_sdio.c
deleted file mode 100644
index 63fe7c1..0000000
--- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_sdio.c
+++ /dev/null
@@ -1,212 +0,0 @@
-#include "halmac_8822b_cfg.h"
-
-/**
- * halmac_mac_power_switch_8822b_sdio() - change mac power
- * @pHalmac_adapter
- * @halmac_power
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_mac_power_switch_8822b_sdio(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_MAC_POWER halmac_power
-)
-{
- u8 interface_mask;
- u8 rpwm;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_MAC_POWER_SWITCH);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "halmac_mac_power_switch_88xx_sdio halmac_power = %x ==========>\n", halmac_power);
-
- interface_mask = HALMAC_PWR_INTF_SDIO_MSK;
-
- pHalmac_adapter->rpwm_record = HALMAC_REG_READ_8(pHalmac_adapter, REG_SDIO_HRPWM1);
-
- /* Check FW still exist or not */
- if (0xC078 == HALMAC_REG_READ_16(pHalmac_adapter, REG_MCUFW_CTRL)) {
- /* Leave 32K */
- rpwm = (u8)((pHalmac_adapter->rpwm_record ^ BIT(7)) & 0x80);
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SDIO_HRPWM1, rpwm);
- }
-
- if (0xEA == HALMAC_REG_READ_8(pHalmac_adapter, REG_CR))
- pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF;
-
- /*Check if power switch is needed*/
- if (halmac_power == pHalmac_adapter->halmac_state.mac_power) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_WARN, "halmac_mac_power_switch power state unchange!\n");
- } else {
- if (HALMAC_MAC_POWER_OFF == halmac_power) {
- if (HALMAC_RET_SUCCESS != halmac_pwr_seq_parser_88xx(pHalmac_adapter, HALMAC_PWR_CUT_TESTCHIP_MSK, HALMAC_PWR_FAB_TSMC_MSK,
- interface_mask, halmac_8822b_card_disable_flow)) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "Handle power off cmd error\n");
- return HALMAC_RET_POWER_OFF_FAIL;
- }
-
- pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF;
- pHalmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_UNDEFINE;
- pHalmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE;
- } else {
- if (HALMAC_RET_SUCCESS != halmac_pwr_seq_parser_88xx(pHalmac_adapter, HALMAC_PWR_CUT_TESTCHIP_MSK, HALMAC_PWR_FAB_TSMC_MSK,
- interface_mask, halmac_8822b_card_enable_flow)) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "Handle power on cmd error\n");
- return HALMAC_RET_POWER_ON_FAIL;
- }
-
- pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON;
- pHalmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_ACT;
- }
- }
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "halmac_mac_power_switch_88xx_sdio <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_tx_allowed_sdio_8822b() - check sdio tx reserved page
- * @pHalmac_adapter
- * @pHalmac_buf
- * @halmac_size
- * Author : Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_tx_allowed_sdio_8822b(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pHalmac_buf,
- IN u32 halmac_size
-)
-{
- u8 *pCurr_packet;
- u16 *pCurr_free_space;
- u32 i, counter;
- u32 tx_agg_num, packet_size;
- u32 tx_required_page_num, total_required_page_num = 0;
- VOID *pDriver_adapter = NULL;
- HALMAC_DMA_MAPPING dma_mapping;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_TX_ALLOWED_SDIO);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_tx_allowed_sdio_8822b ==========>\n");
-
- tx_agg_num = GET_TX_DESC_DMA_TXAGG_NUM(pHalmac_buf);
- pCurr_packet = pHalmac_buf;
-
- tx_agg_num = (tx_agg_num == 0) ? 1 : tx_agg_num;
-
- switch ((HALMAC_QUEUE_SELECT)GET_TX_DESC_QSEL(pCurr_packet)) {
- case HALMAC_QUEUE_SELECT_VO:
- case HALMAC_QUEUE_SELECT_VO_V2:
- dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO];
- break;
- case HALMAC_QUEUE_SELECT_VI:
- case HALMAC_QUEUE_SELECT_VI_V2:
- dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI];
- break;
- case HALMAC_QUEUE_SELECT_BE:
- case HALMAC_QUEUE_SELECT_BE_V2:
- dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE];
- break;
- case HALMAC_QUEUE_SELECT_BK:
- case HALMAC_QUEUE_SELECT_BK_V2:
- dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK];
- break;
- case HALMAC_QUEUE_SELECT_MGNT:
- dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG];
- break;
- case HALMAC_QUEUE_SELECT_HIGH:
- dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI];
- break;
- case HALMAC_QUEUE_SELECT_BCN:
- case HALMAC_QUEUE_SELECT_CMD:
- return HALMAC_RET_SUCCESS;
- default:
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Qsel is out of range\n");
- return HALMAC_RET_QSEL_INCORRECT;
- }
-
- switch (dma_mapping) {
- case HALMAC_DMA_MAPPING_HIGH:
- pCurr_free_space = &(pHalmac_adapter->sdio_free_space.high_queue_number);
- break;
- case HALMAC_DMA_MAPPING_NORMAL:
- pCurr_free_space = &(pHalmac_adapter->sdio_free_space.normal_queue_number);
- break;
- case HALMAC_DMA_MAPPING_LOW:
- pCurr_free_space = &(pHalmac_adapter->sdio_free_space.low_queue_number);
- break;
- case HALMAC_DMA_MAPPING_EXTRA:
- pCurr_free_space = &(pHalmac_adapter->sdio_free_space.extra_queue_number);
- break;
- default:
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "DmaMapping is out of range\n");
- return HALMAC_RET_DMA_MAP_INCORRECT;
- }
-
- for (i = 0; i < tx_agg_num; i++) {
- packet_size = GET_TX_DESC_TXPKTSIZE(pCurr_packet) + GET_TX_DESC_OFFSET(pCurr_packet);
- tx_required_page_num = (packet_size >> HALMAC_TX_PAGE_SIZE_2_POWER_8822B) + ((packet_size & (HALMAC_TX_PAGE_SIZE_8822B - 1)) ? 1 : 0);
- total_required_page_num += tx_required_page_num;
-
- packet_size = HALMAC_ALIGN(packet_size, 8);
-
- pCurr_packet += packet_size;
- }
-
- counter = 10;
- while (1) {
- if ((u32)(*pCurr_free_space + pHalmac_adapter->sdio_free_space.public_queue_number) >= total_required_page_num) {
- if (*pCurr_free_space >= total_required_page_num) {
- *pCurr_free_space -= (u16)total_required_page_num;
- } else {
- pHalmac_adapter->sdio_free_space.public_queue_number -= (u16)(total_required_page_num - *pCurr_free_space);
- *pCurr_free_space = 0;
- }
- break;
- } else {
- halmac_update_sdio_free_page_88xx(pHalmac_adapter);
- }
-
- counter--;
- if (0 == counter)
- return HALMAC_RET_FREE_SPACE_NOT_ENOUGH;
- }
-
- counter = 10;
- while (pHalmac_adapter->sdio_free_space.ac_oqt_number < tx_agg_num) {
- halmac_update_oqt_free_space_88xx(pHalmac_adapter);
-
- counter--;
- if (0 == counter)
- return HALMAC_RET_FREE_SPACE_NOT_ENOUGH;
- }
- pHalmac_adapter->sdio_free_space.ac_oqt_number -= (u8)tx_agg_num;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_tx_allowed_sdio_8822b <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-
diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_sdio.h b/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_sdio.h
deleted file mode 100644
index 5d61a8b..0000000
--- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_sdio.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef _HALMAC_API_8822B_SDIO_H_
-#define _HALMAC_API_8822B_SDIO_H_
-
-#include "../../halmac_2_platform.h"
-#include "../../halmac_type.h"
-
-HALMAC_RET_STATUS
-halmac_mac_power_switch_8822b_sdio(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_MAC_POWER halmac_power
-);
-
-HALMAC_RET_STATUS
-halmac_tx_allowed_sdio_8822b(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pHalmac_buf,
- IN u32 halmac_size
-);
-
-#endif/* _HALMAC_API_8822B_SDIO_H_ */
diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_usb.c b/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_usb.c
deleted file mode 100644
index 95f26c4..0000000
--- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_usb.c
+++ /dev/null
@@ -1,68 +0,0 @@
-#include "../halmac_88xx_cfg.h"
-#include "halmac_8822b_cfg.h"
-
-/**
- * halmac_mac_power_switch_8822b_usb() - change mac power
- * @pHalmac_adapter
- * @halmac_power
- * Author : KaiYuan Chang
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_mac_power_switch_8822b_usb(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_MAC_POWER halmac_power
-)
-{
- u8 interface_mask;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_MAC_POWER_SWITCH);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "halmac_mac_power_switch_88xx_usb halmac_power = %x ==========>\n", halmac_power);
-
- interface_mask = HALMAC_PWR_INTF_USB_MSK;
-
- if (0xEA == HALMAC_REG_READ_8(pHalmac_adapter, REG_CR))
- pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF;
-
- /*Check if power switch is needed*/
- if (halmac_power == pHalmac_adapter->halmac_state.mac_power) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_WARN, "halmac_mac_power_switch power state unchange!\n");
- } else {
- if (HALMAC_MAC_POWER_OFF == halmac_power) {
- if (HALMAC_RET_SUCCESS != halmac_pwr_seq_parser_88xx(pHalmac_adapter, HALMAC_PWR_CUT_TESTCHIP_MSK, HALMAC_PWR_FAB_TSMC_MSK,
- interface_mask, halmac_8822b_card_disable_flow)) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "Handle power off cmd error\n");
- return HALMAC_RET_POWER_OFF_FAIL;
- }
-
- pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF;
- pHalmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_UNDEFINE;
- pHalmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE;
- } else {
- if (HALMAC_RET_SUCCESS != halmac_pwr_seq_parser_88xx(pHalmac_adapter, HALMAC_PWR_CUT_TESTCHIP_MSK, HALMAC_PWR_FAB_TSMC_MSK,
- interface_mask, halmac_8822b_card_enable_flow)) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "Handle power on cmd error\n");
- return HALMAC_RET_POWER_ON_FAIL;
- }
-
- pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON;
- pHalmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_ACT;
- }
- }
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "halmac_mac_power_switch_88xx_usb <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_usb.h b/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_usb.h
deleted file mode 100644
index 7105d8d..0000000
--- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_api_8822b_usb.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef _HALMAC_API_8822B_USB_H_
-#define _HALMAC_API_8822B_USB_H_
-
-#include "../../halmac_2_platform.h"
-#include "../../halmac_type.h"
-
-HALMAC_RET_STATUS
-halmac_mac_power_switch_8822b_usb(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_MAC_POWER halmac_power
-);
-#endif/* _HALMAC_API_8822B_USB_H_ */
diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_cfg_wmac_8822b.c b/hal/halmac/halmac_88xx/halmac_8822b/halmac_cfg_wmac_8822b.c
new file mode 100644
index 0000000..fd7ea86
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_cfg_wmac_8822b.c
@@ -0,0 +1,168 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_cfg_wmac_8822b.h"
+#include "halmac_8822b_cfg.h"
+
+#if HALMAC_8822B_SUPPORT
+
+/**
+ * cfg_drv_info_8822b() - config driver info
+ * @adapter : the adapter of halmac
+ * @drv_info : driver information selection
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_drv_info_8822b(struct halmac_adapter *adapter,
+ enum halmac_drv_info drv_info)
+{
+ u8 drv_info_size = 0;
+ u8 phy_status_en = 0;
+ u8 sniffer_en = 0;
+ u8 plcp_hdr_en = 0;
+ u8 value8;
+ u32 value32;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+ struct halmac_mac_rx_ignore_cfg cfg;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+ PLTFM_MSG_TRACE("[TRACE]drv info = %d\n", drv_info);
+
+ switch (drv_info) {
+ case HALMAC_DRV_INFO_NONE:
+ drv_info_size = 0;
+ phy_status_en = 0;
+ sniffer_en = 0;
+ plcp_hdr_en = 0;
+ cfg.hdr_chk_en = _FALSE;
+ break;
+ case HALMAC_DRV_INFO_PHY_STATUS:
+ drv_info_size = 4;
+ phy_status_en = 1;
+ sniffer_en = 0;
+ plcp_hdr_en = 0;
+ cfg.hdr_chk_en = _FALSE;
+ break;
+ case HALMAC_DRV_INFO_PHY_SNIFFER:
+ drv_info_size = 5; /* phy status 4byte, sniffer info 1byte */
+ phy_status_en = 1;
+ sniffer_en = 1;
+ plcp_hdr_en = 0;
+ cfg.hdr_chk_en = _FALSE;
+ break;
+ case HALMAC_DRV_INFO_PHY_PLCP:
+ drv_info_size = 6; /* phy status 4byte, plcp header 2byte */
+ phy_status_en = 1;
+ sniffer_en = 0;
+ plcp_hdr_en = 1;
+ cfg.hdr_chk_en = _FALSE;
+ break;
+ default:
+ return HALMAC_RET_SW_CASE_NOT_SUPPORT;
+ }
+
+ if (adapter->txff_alloc.rx_fifo_exp_mode !=
+ HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE)
+ drv_info_size = RX_DESC_DUMMY_SIZE_8822B >> 3;
+
+ api->halmac_set_hw_value(adapter, HALMAC_HW_RX_IGNORE, &cfg);
+
+ HALMAC_REG_W8(REG_RX_DRVINFO_SZ, drv_info_size);
+
+ value8 = HALMAC_REG_R8(REG_TRXFF_BNDY + 1);
+ value8 &= 0xF0;
+ /* For rxdesc len = 0 issue */
+ value8 |= 0xF;
+ HALMAC_REG_W8(REG_TRXFF_BNDY + 1, value8);
+
+ adapter->drv_info_size = drv_info_size;
+
+ value32 = HALMAC_REG_R32(REG_RCR);
+ value32 = (value32 & (~BIT_APP_PHYSTS));
+ if (phy_status_en == 1)
+ value32 = value32 | BIT_APP_PHYSTS;
+ HALMAC_REG_W32(REG_RCR, value32);
+
+ value32 = HALMAC_REG_R32(REG_WMAC_OPTION_FUNCTION + 4);
+ value32 = (value32 & (~(BIT(8) | BIT(9))));
+ if (sniffer_en == 1)
+ value32 = value32 | BIT(9);
+ if (plcp_hdr_en == 1)
+ value32 = value32 | BIT(8);
+ HALMAC_REG_W32(REG_WMAC_OPTION_FUNCTION + 4, value32);
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * init_low_pwr_8822b() - config WMAC register
+ * @adapter
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+init_low_pwr_8822b(struct halmac_adapter *adapter)
+{
+ return HALMAC_RET_SUCCESS;
+}
+
+void
+cfg_rx_ignore_8822b(struct halmac_adapter *adapter,
+ struct halmac_mac_rx_ignore_cfg *cfg)
+{
+ u8 value8;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ value8 = HALMAC_REG_R8(REG_BBPSF_CTRL);
+
+ /*mac header check enable*/
+ if (cfg->hdr_chk_en == _TRUE)
+ value8 |= BIT_BBPSF_MHCHKEN | BIT_BBPSF_MPDUCHKEN;
+ else
+ value8 &= ~(BIT_BBPSF_MHCHKEN) & (~(BIT_BBPSF_MPDUCHKEN));
+
+ HALMAC_REG_W8(REG_BBPSF_CTRL, value8);
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+}
+
+enum halmac_ret_status
+cfg_ampdu_8822b(struct halmac_adapter *adapter,
+ struct halmac_ampdu_config *cfg)
+{
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ if (cfg->ht_max_len != cfg->vht_max_len) {
+ PLTFM_MSG_ERR("[ERR]max len ht != vht!!\n");
+ return HALMAC_RET_PARA_NOT_SUPPORT;
+ }
+
+ HALMAC_REG_W8(REG_PROT_MODE_CTRL + 2, cfg->max_agg_num);
+ HALMAC_REG_W8(REG_PROT_MODE_CTRL + 3, cfg->max_agg_num);
+
+ if (cfg->max_len_en == 1)
+ HALMAC_REG_W32(REG_AMPDU_MAX_LENGTH, cfg->ht_max_len);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+#endif /* HALMAC_8822B_SUPPORT */
diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_cfg_wmac_8822b.h b/hal/halmac/halmac_88xx/halmac_8822b/halmac_cfg_wmac_8822b.h
new file mode 100644
index 0000000..d383cf3
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_cfg_wmac_8822b.h
@@ -0,0 +1,40 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_CFG_WMAC_8822B_H_
+#define _HALMAC_CFG_WMAC_8822B_H_
+
+#include "../../halmac_api.h"
+
+#if HALMAC_8822B_SUPPORT
+
+enum halmac_ret_status
+cfg_drv_info_8822b(struct halmac_adapter *adapter,
+ enum halmac_drv_info drv_info);
+
+enum halmac_ret_status
+init_low_pwr_8822b(struct halmac_adapter *adapter);
+
+void
+cfg_rx_ignore_8822b(struct halmac_adapter *adapter,
+ struct halmac_mac_rx_ignore_cfg *cfg);
+
+enum halmac_ret_status
+cfg_ampdu_8822b(struct halmac_adapter *adapter,
+ struct halmac_ampdu_config *cfg);
+
+#endif/* HALMAC_8822B_SUPPORT */
+
+#endif/* _HALMAC_CFG_WMAC_8822B_H_ */
diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_common_8822b.c b/hal/halmac/halmac_88xx/halmac_8822b/halmac_common_8822b.c
new file mode 100644
index 0000000..7925aab
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_common_8822b.c
@@ -0,0 +1,168 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_8822b_cfg.h"
+#include "halmac_common_8822b.h"
+#include "../halmac_common_88xx.h"
+#include "halmac_cfg_wmac_8822b.h"
+
+#if HALMAC_8822B_SUPPORT
+
+static void
+cfg_ldo25_8822b(struct halmac_adapter *adapter, u8 enable);
+
+/**
+ * get_hw_value_8822b() -get hw config value
+ * @adapter : the adapter of halmac
+ * @hw_id : hw id for driver to query
+ * @pvalue : hw value, reference table to get data type
+ * Author : KaiYuan Chang / Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+get_hw_value_8822b(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,
+ void *value)
+{
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (!value) {
+ PLTFM_MSG_ERR("[ERR]%s (NULL ==pvalue)\n", __func__);
+ return HALMAC_RET_NULL_POINTER;
+ }
+
+ if (get_hw_value_88xx(adapter, hw_id, value) == HALMAC_RET_SUCCESS)
+ return HALMAC_RET_SUCCESS;
+
+ switch (hw_id) {
+ case HALMAC_HW_FW_MAX_SIZE:
+ *(u32 *)value = WLAN_FW_MAX_SIZE_8822B;
+ break;
+ default:
+ return HALMAC_RET_PARA_NOT_SUPPORT;
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * set_hw_value_8822b() -set hw config value
+ * @adapter : the adapter of halmac
+ * @hw_id : hw id for driver to config
+ * @pvalue : hw value, reference table to get data type
+ * Author : KaiYuan Chang / Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+set_hw_value_8822b(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,
+ void *value)
+{
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (!value) {
+ PLTFM_MSG_ERR("[ERR]null pointer\n");
+ return HALMAC_RET_NULL_POINTER;
+ }
+
+ if (set_hw_value_88xx(adapter, hw_id, value) == HALMAC_RET_SUCCESS)
+ return HALMAC_RET_SUCCESS;
+
+ switch (hw_id) {
+ case HALMAC_HW_AMPDU_CONFIG:
+ status = cfg_ampdu_8822b(adapter,
+ (struct halmac_ampdu_config *)value);
+ break;
+ case HALMAC_HW_SDIO_TX_FORMAT:
+ break;
+ case HALMAC_HW_RXGCK_FIFO:
+ break;
+ case HALMAC_HW_RX_IGNORE:
+ cfg_rx_ignore_8822b(adapter,
+ (struct halmac_mac_rx_ignore_cfg *)value);
+ break;
+ case HALMAC_HW_LDO25_EN:
+ cfg_ldo25_8822b(adapter, *(u8 *)value);
+ break;
+ case HALMAC_HW_PCIE_REF_AUTOK:
+ break;
+ default:
+ return HALMAC_RET_PARA_NOT_SUPPORT;
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return status;
+}
+
+/**
+ * halmac_fill_txdesc_check_sum_88xx() - fill in tx desc check sum
+ * @adapter : the adapter of halmac
+ * @txdesc : tx desc packet
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+fill_txdesc_check_sum_8822b(struct halmac_adapter *adapter, u8 *txdesc)
+{
+ u16 chksum = 0;
+ u16 *data = (u16 *)NULL;
+ u32 i;
+
+ if (!txdesc) {
+ PLTFM_MSG_ERR("[ERR]null pointer");
+ return HALMAC_RET_NULL_POINTER;
+ }
+
+ if (adapter->tx_desc_checksum != _TRUE)
+ PLTFM_MSG_TRACE("[TRACE]chksum disable");
+
+ SET_TX_DESC_TXDESC_CHECKSUM(txdesc, 0x0000);
+
+ data = (u16 *)(txdesc);
+
+ /* HW clculates only 32byte */
+ for (i = 0; i < 8; i++)
+ chksum ^= (*(data + 2 * i) ^ *(data + (2 * i + 1)));
+
+ /* *(data + 2 * i) & *(data + (2 * i + 1) have endain issue*/
+ /* Process eniadn issue after checksum calculation */
+ chksum = rtk_le16_to_cpu(chksum);
+
+ SET_TX_DESC_TXDESC_CHECKSUM(txdesc, chksum);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static void
+cfg_ldo25_8822b(struct halmac_adapter *adapter, u8 enable)
+{
+ u8 value8;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ value8 = HALMAC_REG_R8(REG_LDO_EFUSE_CTRL + 3);
+
+ if (enable == _TRUE)
+ HALMAC_REG_W8(REG_LDO_EFUSE_CTRL + 3, (u8)(value8 | BIT(7)));
+ else
+ HALMAC_REG_W8(REG_LDO_EFUSE_CTRL + 3, (u8)(value8 & ~BIT(7)));
+}
+
+#endif /* HALMAC_8822B_SUPPORT */
diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_common_8822b.h b/hal/halmac/halmac_88xx/halmac_8822b/halmac_common_8822b.h
new file mode 100644
index 0000000..952f929
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_common_8822b.h
@@ -0,0 +1,36 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_COMMON_8822B_H_
+#define _HALMAC_COMMON_8822B_H_
+
+#include "../../halmac_api.h"
+
+#if HALMAC_8822B_SUPPORT
+
+enum halmac_ret_status
+get_hw_value_8822b(struct halmac_adapter *adapter,
+ enum halmac_hw_id hw_id, void *value);
+
+enum halmac_ret_status
+set_hw_value_8822b(struct halmac_adapter *adapter,
+ enum halmac_hw_id hw_id, void *value);
+
+enum halmac_ret_status
+fill_txdesc_check_sum_8822b(struct halmac_adapter *adapter, u8 *txdesc);
+
+#endif/* HALMAC_8822B_SUPPORT */
+
+#endif/* _HALMAC_COMMON_8822B_H_ */
diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_func_8822b.c b/hal/halmac/halmac_88xx/halmac_8822b/halmac_func_8822b.c
deleted file mode 100644
index e2e27a1..0000000
--- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_func_8822b.c
+++ /dev/null
@@ -1,389 +0,0 @@
-#include "halmac_8822b_cfg.h"
-
-HALMAC_RET_STATUS
-halmac_txdma_queue_mapping_8822b(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_TRX_MODE halmac_trx_mode
-)
-{
- u16 value16;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- /* Default mapping (PCIE + SDIO + USB 4 bulkout) */
- switch (halmac_trx_mode) {
- case HALMAC_TRX_MODE_NORMAL:
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO] = HALMAC_DMA_MAPPING_NORMAL;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI] = HALMAC_DMA_MAPPING_NORMAL;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE] = HALMAC_DMA_MAPPING_LOW;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK] = HALMAC_DMA_MAPPING_LOW;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG] = HALMAC_DMA_MAPPING_EXTRA;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI] = HALMAC_DMA_MAPPING_HIGH;
- break;
- case HALMAC_TRX_MODE_TRXSHARE:
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO] = HALMAC_DMA_MAPPING_HIGH;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI] = HALMAC_DMA_MAPPING_HIGH;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE] = HALMAC_DMA_MAPPING_HIGH;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK] = HALMAC_DMA_MAPPING_HIGH;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG] = HALMAC_DMA_MAPPING_HIGH;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI] = HALMAC_DMA_MAPPING_HIGH;
- break;
- case HALMAC_TRX_MODE_WMM:
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO] = HALMAC_DMA_MAPPING_NORMAL;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI] = HALMAC_DMA_MAPPING_NORMAL;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE] = HALMAC_DMA_MAPPING_LOW;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK] = HALMAC_DMA_MAPPING_LOW;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG] = HALMAC_DMA_MAPPING_EXTRA;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI] = HALMAC_DMA_MAPPING_HIGH;
- break;
- case HALMAC_TRX_MODE_P2P:
- case HALMAC_TRX_MODE_LOOPBACK:
- case HALMAC_TRX_MODE_DELAY_LOOPBACK:
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO] = HALMAC_DMA_MAPPING_NORMAL;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI] = HALMAC_DMA_MAPPING_NORMAL;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE] = HALMAC_DMA_MAPPING_LOW;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK] = HALMAC_DMA_MAPPING_LOW;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG] = HALMAC_DMA_MAPPING_EXTRA;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI] = HALMAC_DMA_MAPPING_HIGH;
- break;
- default:
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_trx_cfg_8822b 0 switch case not support\n");
- return HALMAC_RET_TRX_MODE_NOT_SUPPORT;
- }
-
- /* Extra mapping */
- if (HALMAC_INTERFACE_USB == pHalmac_adapter->halmac_interface) {
- if (pHalmac_adapter->halmac_bulkout_num == 2) {
- /* In USB 2 bulkout, only High and Normal queue can be used */
- switch (halmac_trx_mode) {
- case HALMAC_TRX_MODE_NORMAL:
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO] = HALMAC_DMA_MAPPING_NORMAL;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI] = HALMAC_DMA_MAPPING_NORMAL;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE] = HALMAC_DMA_MAPPING_NORMAL;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK] = HALMAC_DMA_MAPPING_HIGH;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG] = HALMAC_DMA_MAPPING_HIGH;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI] = HALMAC_DMA_MAPPING_HIGH;
-
- break;
- case HALMAC_TRX_MODE_TRXSHARE:
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO] = HALMAC_DMA_MAPPING_HIGH;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI] = HALMAC_DMA_MAPPING_HIGH;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE] = HALMAC_DMA_MAPPING_HIGH;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK] = HALMAC_DMA_MAPPING_HIGH;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG] = HALMAC_DMA_MAPPING_HIGH;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI] = HALMAC_DMA_MAPPING_HIGH;
- break;
- case HALMAC_TRX_MODE_WMM:
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO] = HALMAC_DMA_MAPPING_NORMAL;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI] = HALMAC_DMA_MAPPING_NORMAL;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE] = HALMAC_DMA_MAPPING_NORMAL;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK] = HALMAC_DMA_MAPPING_HIGH;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG] = HALMAC_DMA_MAPPING_HIGH;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI] = HALMAC_DMA_MAPPING_HIGH;
- break;
- case HALMAC_TRX_MODE_P2P:
- case HALMAC_TRX_MODE_LOOPBACK:
- case HALMAC_TRX_MODE_DELAY_LOOPBACK:
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO] = HALMAC_DMA_MAPPING_HIGH;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI] = HALMAC_DMA_MAPPING_HIGH;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE] = HALMAC_DMA_MAPPING_HIGH;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK] = HALMAC_DMA_MAPPING_NORMAL;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG] = HALMAC_DMA_MAPPING_HIGH;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI] = HALMAC_DMA_MAPPING_HIGH;
-
- break;
- default:
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_trx_cfg_8822b 1 switch case not support\n");
- return HALMAC_RET_TRX_MODE_NOT_SUPPORT;
- }
- } else if (pHalmac_adapter->halmac_bulkout_num == 3) {
- /* in USB 3 bulkout, only High, Normal, Low queue can be used */
- switch (halmac_trx_mode) {
- case HALMAC_TRX_MODE_NORMAL:
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO] = HALMAC_DMA_MAPPING_NORMAL;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI] = HALMAC_DMA_MAPPING_NORMAL;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE] = HALMAC_DMA_MAPPING_LOW;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK] = HALMAC_DMA_MAPPING_LOW;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG] = HALMAC_DMA_MAPPING_HIGH;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI] = HALMAC_DMA_MAPPING_HIGH;
-
- break;
- case HALMAC_TRX_MODE_TRXSHARE:
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO] = HALMAC_DMA_MAPPING_HIGH;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI] = HALMAC_DMA_MAPPING_HIGH;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE] = HALMAC_DMA_MAPPING_HIGH;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK] = HALMAC_DMA_MAPPING_HIGH;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG] = HALMAC_DMA_MAPPING_HIGH;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI] = HALMAC_DMA_MAPPING_HIGH;
- break;
- case HALMAC_TRX_MODE_WMM:
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO] = HALMAC_DMA_MAPPING_HIGH;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI] = HALMAC_DMA_MAPPING_NORMAL;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE] = HALMAC_DMA_MAPPING_LOW;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK] = HALMAC_DMA_MAPPING_NORMAL;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG] = HALMAC_DMA_MAPPING_EXTRA;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI] = HALMAC_DMA_MAPPING_HIGH;
- break;
- case HALMAC_TRX_MODE_P2P:
- case HALMAC_TRX_MODE_LOOPBACK:
- case HALMAC_TRX_MODE_DELAY_LOOPBACK:
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO] = HALMAC_DMA_MAPPING_HIGH;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI] = HALMAC_DMA_MAPPING_HIGH;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE] = HALMAC_DMA_MAPPING_LOW;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK] = HALMAC_DMA_MAPPING_NORMAL;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG] = HALMAC_DMA_MAPPING_HIGH;
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI] = HALMAC_DMA_MAPPING_HIGH;
-
- break;
- default:
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_trx_cfg_8822b 2 switch case not support\n");
- return HALMAC_RET_TRX_MODE_NOT_SUPPORT;
- }
- }
- }
-
- value16 = 0;
- value16 |= BIT_TXDMA_HIQ_MAP(pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI]);
- value16 |= BIT_TXDMA_MGQ_MAP(pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG]);
- value16 |= BIT_TXDMA_BKQ_MAP(pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK]);
- value16 |= BIT_TXDMA_BEQ_MAP(pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE]);
- value16 |= BIT_TXDMA_VIQ_MAP(pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI]);
- value16 |= BIT_TXDMA_VOQ_MAP(pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO]);
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TXDMA_PQ_MAP, value16);
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_priority_queue_config_8822b(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_TRX_MODE halmac_trx_mode
-)
-{
- u8 transfer_mode = 0;
- u8 value8;
- u16 HPQ_num = 0, LPQ_Nnum = 0, NPQ_num = 0, GAPQ_num = 0;
- u16 EXPQ_num = 0, PUBQ_num = 0;
- u16 tx_page_boundary = 0, rx_f_ifo_boundary = 0;
- u16 h2c_extra_info_boundary = 0, fw_txbuff_boundary = 0;
- u32 counter;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- if (HALMAC_LA_MODE_DISABLE == pHalmac_adapter->txff_allocation.la_mode)
- pHalmac_adapter->txff_allocation.tx_fifo_pg_num = HALMAC_TX_FIFO_SIZE_8822B >> HALMAC_TX_PAGE_SIZE_2_POWER_8822B;
- else
- pHalmac_adapter->txff_allocation.tx_fifo_pg_num = HALMAC_TX_FIFO_SIZE_LA_8822B >> HALMAC_TX_PAGE_SIZE_2_POWER_8822B;
-
- pHalmac_adapter->txff_allocation.rsvd_pg_num = (pHalmac_adapter->txff_allocation.rsvd_drv_pg_num +
- HALMAC_RSVD_H2C_EXTRAINFO_PGNUM_8822B +
- HALMAC_RSVD_H2C_QUEUE_PGNUM_8822B +
- HALMAC_RSVD_CPU_INSTRUCTION_PGNUM_8822B +
- HALMAC_RSVD_FW_TXBUFF_PGNUM_8822B);
- if (pHalmac_adapter->txff_allocation.rsvd_pg_num > pHalmac_adapter->txff_allocation.tx_fifo_pg_num)
- return HALMAC_RET_CFG_TXFIFO_PAGE_FAIL;
-
- pHalmac_adapter->txff_allocation.ac_q_pg_num = pHalmac_adapter->txff_allocation.tx_fifo_pg_num - pHalmac_adapter->txff_allocation.rsvd_pg_num;
- pHalmac_adapter->txff_allocation.rsvd_pg_bndy = pHalmac_adapter->txff_allocation.tx_fifo_pg_num - pHalmac_adapter->txff_allocation.rsvd_pg_num;
- pHalmac_adapter->txff_allocation.rsvd_fw_txbuff_pg_bndy = pHalmac_adapter->txff_allocation.tx_fifo_pg_num - HALMAC_RSVD_FW_TXBUFF_PGNUM_8822B;
- pHalmac_adapter->txff_allocation.rsvd_cpu_instr_pg_bndy = pHalmac_adapter->txff_allocation.rsvd_fw_txbuff_pg_bndy - HALMAC_RSVD_CPU_INSTRUCTION_PGNUM_8822B;
- pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy = pHalmac_adapter->txff_allocation.rsvd_cpu_instr_pg_bndy - HALMAC_RSVD_H2C_QUEUE_PGNUM_8822B;
- pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy = pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy - HALMAC_RSVD_H2C_EXTRAINFO_PGNUM_8822B;
- pHalmac_adapter->txff_allocation.rsvd_drv_pg_bndy = pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy - pHalmac_adapter->txff_allocation.rsvd_drv_pg_num;
-
- /* Default setting (PCIE + SDIO + USB 4 bulkout) */
- switch (halmac_trx_mode) {
- case HALMAC_TRX_MODE_NORMAL:
- HPQ_num = HALMAC_NORMAL_HPQ_PGNUM_8822B;
- LPQ_Nnum = HALMAC_NORMAL_LPQ_PGNUM_8822B;
- NPQ_num = HALMAC_NORMAL_NPQ_PGNUM_8822B;
- EXPQ_num = HALMAC_NORMAL_EXPQ_PGNUM_8822B;
- GAPQ_num = HALMAC_NORMAL_GAP_PGNUM_8822B;
- PUBQ_num = pHalmac_adapter->txff_allocation.ac_q_pg_num - HPQ_num - LPQ_Nnum - NPQ_num - EXPQ_num - GAPQ_num;
- rx_f_ifo_boundary = HALMAC_RX_FIFO_SIZE_8822B - HALMAC_WOWLAN_PATTERN_SIZE_8822B - 1;
- transfer_mode = HALMAC_TRNSFER_NORMAL;
- break;
- case HALMAC_TRX_MODE_TRXSHARE:
- break;
- case HALMAC_TRX_MODE_WMM:
- HPQ_num = HALMAC_WMM_HPQ_PGNUM_8822B;
- LPQ_Nnum = HALMAC_WMM_LPQ_PGNUM_8822B;
- NPQ_num = HALMAC_WMM_NPQ_PGNUM_8822B;
- EXPQ_num = HALMAC_WMM_EXPQ_PGNUM_8822B;
- GAPQ_num = HALMAC_WMM_GAP_PGNUM_8822B;
- PUBQ_num = pHalmac_adapter->txff_allocation.ac_q_pg_num - HPQ_num - LPQ_Nnum - NPQ_num - EXPQ_num - GAPQ_num;
- rx_f_ifo_boundary = HALMAC_RX_FIFO_SIZE_8822B - HALMAC_WOWLAN_PATTERN_SIZE_8822B - 1;
- transfer_mode = HALMAC_TRNSFER_NORMAL;
- break;
- case HALMAC_TRX_MODE_P2P:
- case HALMAC_TRX_MODE_LOOPBACK:
- case HALMAC_TRX_MODE_DELAY_LOOPBACK:
- HPQ_num = HALMAC_LB_HPQ_PGNUM_8822B;
- LPQ_Nnum = HALMAC_LB_LPQ_PGNUM_8822B;
- NPQ_num = HALMAC_LB_NPQ_PGNUM_8822B;
- EXPQ_num = HALMAC_LB_EXPQ_PGNUM_8822B;
- GAPQ_num = HALMAC_LB_GAP_PGNUM_8822B;
- PUBQ_num = pHalmac_adapter->txff_allocation.ac_q_pg_num - HPQ_num - LPQ_Nnum - NPQ_num - EXPQ_num - GAPQ_num;
- rx_f_ifo_boundary = HALMAC_RX_FIFO_SIZE_8822B - 1;
- transfer_mode = HALMAC_TRNSFER_LOOPBACK_DIRECT;
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_WMAC_LBK_BUF_HD_V1, (u16)pHalmac_adapter->txff_allocation.rsvd_pg_bndy);
- break;
- default:
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_trx_cfg_8822b 3 switch case not support\n");
- return HALMAC_RET_TRX_MODE_NOT_SUPPORT;
- }
-
- /* Extra setting */
- if (HALMAC_INTERFACE_USB == pHalmac_adapter->halmac_interface) {
- if (pHalmac_adapter->halmac_bulkout_num == 2) {
- /* In USB 2 bulkout, only High and Normal queue can be used */
- switch (halmac_trx_mode) {
- case HALMAC_TRX_MODE_NORMAL:
- HPQ_num = HALMAC_NORMAL_2BULKOUT_HPQ_PGNUM_8822B;
- LPQ_Nnum = HALMAC_NORMAL_2BULKOUT_LPQ_PGNUM_8822B;
- NPQ_num = HALMAC_NORMAL_2BULKOUT_NPQ_PGNUM_8822B;
- EXPQ_num = HALMAC_NORMAL_2BULKOUT_EXPQ_PGNUM_8822B;
- GAPQ_num = HALMAC_NORMAL_2BULKOUT_GAP_PGNUM_8822B;
- PUBQ_num = pHalmac_adapter->txff_allocation.ac_q_pg_num - HPQ_num - LPQ_Nnum - NPQ_num - EXPQ_num - GAPQ_num;
- rx_f_ifo_boundary = HALMAC_RX_FIFO_SIZE_8822B - HALMAC_WOWLAN_PATTERN_SIZE_8822B - 1;
- transfer_mode = HALMAC_TRNSFER_NORMAL;
- break;
- case HALMAC_TRX_MODE_TRXSHARE:
- break;
- case HALMAC_TRX_MODE_WMM:
- HPQ_num = HALMAC_WMM_HPQ_PGNUM_8822B;
- LPQ_Nnum = HALMAC_WMM_LPQ_PGNUM_8822B;
- NPQ_num = HALMAC_WMM_NPQ_PGNUM_8822B;
- EXPQ_num = HALMAC_WMM_EXPQ_PGNUM_8822B;
- GAPQ_num = HALMAC_WMM_GAP_PGNUM_8822B;
- PUBQ_num = pHalmac_adapter->txff_allocation.ac_q_pg_num - HPQ_num - LPQ_Nnum - NPQ_num - EXPQ_num - GAPQ_num;
- rx_f_ifo_boundary = HALMAC_RX_FIFO_SIZE_8822B - HALMAC_WOWLAN_PATTERN_SIZE_8822B - 1;
- transfer_mode = HALMAC_TRNSFER_NORMAL;
- break;
- case HALMAC_TRX_MODE_P2P:
- case HALMAC_TRX_MODE_LOOPBACK:
- case HALMAC_TRX_MODE_DELAY_LOOPBACK:
- HPQ_num = HALMAC_LB_2BULKOUT_HPQ_PGNUM_8822B;
- LPQ_Nnum = HALMAC_LB_2BULKOUT_LPQ_PGNUM_8822B;
- NPQ_num = HALMAC_LB_2BULKOUT_NPQ_PGNUM_8822B;
- EXPQ_num = HALMAC_LB_2BULKOUT_EXPQ_PGNUM_8822B;
- GAPQ_num = HALMAC_LB_2BULKOUT_GAP_PGNUM_8822B;
- PUBQ_num = pHalmac_adapter->txff_allocation.ac_q_pg_num - HPQ_num - LPQ_Nnum - NPQ_num - EXPQ_num - GAPQ_num;
- rx_f_ifo_boundary = HALMAC_RX_FIFO_SIZE_8822B - 1;
- transfer_mode = HALMAC_TRNSFER_LOOPBACK_DIRECT;
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_WMAC_LBK_BUF_HD_V1, (u16)pHalmac_adapter->txff_allocation.rsvd_pg_bndy);
- break;
- default:
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_trx_cfg_8822b 4 switch case not support\n");
- return HALMAC_RET_TRX_MODE_NOT_SUPPORT;
- }
- } else if (pHalmac_adapter->halmac_bulkout_num == 3) {
- /* in USB 3 bulkout, only High, Normal, Low queue can be used */
- switch (halmac_trx_mode) {
- case HALMAC_TRX_MODE_NORMAL:
- HPQ_num = HALMAC_NORMAL_3BULKOUT_HPQ_PGNUM_8822B;
- LPQ_Nnum = HALMAC_NORMAL_3BULKOUT_LPQ_PGNUM_8822B;
- NPQ_num = HALMAC_NORMAL_3BULKOUT_NPQ_PGNUM_8822B;
- EXPQ_num = HALMAC_NORMAL_3BULKOUT_EXPQ_PGNUM_8822B;
- GAPQ_num = HALMAC_NORMAL_3BULKOUT_GAP_PGNUM_8822B;
- PUBQ_num = pHalmac_adapter->txff_allocation.ac_q_pg_num - HPQ_num - LPQ_Nnum - NPQ_num - EXPQ_num - GAPQ_num;
- rx_f_ifo_boundary = HALMAC_RX_FIFO_SIZE_8822B - HALMAC_WOWLAN_PATTERN_SIZE_8822B - 1;
- transfer_mode = HALMAC_TRNSFER_NORMAL;
- break;
- case HALMAC_TRX_MODE_TRXSHARE:
- break;
- case HALMAC_TRX_MODE_WMM:
- HPQ_num = HALMAC_WMM_HPQ_PGNUM_8822B;
- LPQ_Nnum = HALMAC_WMM_LPQ_PGNUM_8822B;
- NPQ_num = HALMAC_WMM_NPQ_PGNUM_8822B;
- EXPQ_num = HALMAC_WMM_EXPQ_PGNUM_8822B;
- GAPQ_num = HALMAC_WMM_GAP_PGNUM_8822B;
- PUBQ_num = pHalmac_adapter->txff_allocation.ac_q_pg_num - HPQ_num - LPQ_Nnum - NPQ_num - EXPQ_num - GAPQ_num;
- rx_f_ifo_boundary = HALMAC_RX_FIFO_SIZE_8822B - HALMAC_WOWLAN_PATTERN_SIZE_8822B - 1;
- transfer_mode = HALMAC_TRNSFER_NORMAL;
- break;
- case HALMAC_TRX_MODE_P2P:
- case HALMAC_TRX_MODE_LOOPBACK:
- case HALMAC_TRX_MODE_DELAY_LOOPBACK:
- HPQ_num = HALMAC_LB_3BULKOUT_HPQ_PGNUM_8822B;
- LPQ_Nnum = HALMAC_LB_3BULKOUT_LPQ_PGNUM_8822B;
- NPQ_num = HALMAC_LB_3BULKOUT_NPQ_PGNUM_8822B;
- EXPQ_num = HALMAC_LB_3BULKOUT_EXPQ_PGNUM_8822B;
- GAPQ_num = HALMAC_LB_3BULKOUT_GAP_PGNUM_8822B;
- PUBQ_num = pHalmac_adapter->txff_allocation.ac_q_pg_num - HPQ_num - LPQ_Nnum - NPQ_num - EXPQ_num - GAPQ_num;
- rx_f_ifo_boundary = HALMAC_RX_FIFO_SIZE_8822B - 1;
- transfer_mode = HALMAC_TRNSFER_LOOPBACK_DIRECT;
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_WMAC_LBK_BUF_HD_V1, (u16)pHalmac_adapter->txff_allocation.rsvd_pg_bndy);
- break;
- default:
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_trx_cfg_8822b 5 switch case not support\n");
- return HALMAC_RET_TRX_MODE_NOT_SUPPORT;
- }
- }
- }
-
-
- if (pHalmac_adapter->txff_allocation.ac_q_pg_num < HPQ_num + LPQ_Nnum + NPQ_num + EXPQ_num + GAPQ_num)
- return HALMAC_RET_CFG_TXFIFO_PAGE_FAIL;
-
- pHalmac_adapter->txff_allocation.high_queue_pg_num = HPQ_num;
- pHalmac_adapter->txff_allocation.low_queue_pg_num = LPQ_Nnum;
- pHalmac_adapter->txff_allocation.normal_queue_pg_num = NPQ_num;
- pHalmac_adapter->txff_allocation.extra_queue_pg_num = EXPQ_num;
- pHalmac_adapter->txff_allocation.pub_queue_pg_num = PUBQ_num;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Set FIFO page\n");
-
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_INFO_1, HPQ_num);
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_INFO_2, LPQ_Nnum);
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_INFO_3, NPQ_num);
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_INFO_4, EXPQ_num);
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_INFO_5, PUBQ_num);
-
- pHalmac_adapter->sdio_free_space.high_queue_number = HPQ_num;
- pHalmac_adapter->sdio_free_space.normal_queue_number = NPQ_num;
- pHalmac_adapter->sdio_free_space.low_queue_number = LPQ_Nnum;
- pHalmac_adapter->sdio_free_space.public_queue_number = PUBQ_num;
- pHalmac_adapter->sdio_free_space.extra_queue_number = EXPQ_num;
-
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RQPN_CTRL_2, HALMAC_REG_READ_32(pHalmac_adapter, REG_RQPN_CTRL_2) | BIT(31));
-
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1));
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_BCNQ_BDNY_V1, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCNQ_PGBNDY_V1));
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2 + 2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1));
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_BCNQ1_BDNY_V1, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCNQ_PGBNDY_V1));
-
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RXFF_BNDY, rx_f_ifo_boundary);
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Init LLT table\n");
-
- if (HALMAC_INTERFACE_USB == pHalmac_adapter->halmac_interface) {
- value8 = (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_AUTO_LLT_V1) & ~(BIT_MASK_BLK_DESC_NUM << BIT_SHIFT_BLK_DESC_NUM));
- value8 = (u8)(value8 | (HALMAC_BLK_DESC_NUM_8822B << BIT_SHIFT_BLK_DESC_NUM));
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_AUTO_LLT_V1, value8);
-
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_AUTO_LLT_V1 + 3, HALMAC_BLK_DESC_NUM_8822B);
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXDMA_OFFSET_CHK + 1, HALMAC_REG_READ_8(pHalmac_adapter, REG_TXDMA_OFFSET_CHK + 1) | BIT(1));
- }
-
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_AUTO_LLT_V1, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_AUTO_LLT_V1) | BIT_AUTO_INIT_LLT_V1));
- counter = 1000;
- while (HALMAC_REG_READ_8(pHalmac_adapter, REG_AUTO_LLT_V1) & BIT_AUTO_INIT_LLT_V1) {
- counter--;
- if (counter == 0)
- return HALMAC_RET_INIT_LLT_FAIL;
- }
-
- if (HALMAC_TRX_MODE_DELAY_LOOPBACK == halmac_trx_mode)
- transfer_mode = HALMAC_TRNSFER_LOOPBACK_DELAY;
-
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR + 3, (u8)transfer_mode);
-
- return HALMAC_RET_SUCCESS;
-}
diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_func_8822b.h b/hal/halmac/halmac_88xx/halmac_8822b/halmac_func_8822b.h
deleted file mode 100644
index 68654d9..0000000
--- a/hal/halmac/halmac_88xx/halmac_8822b/halmac_func_8822b.h
+++ /dev/null
@@ -1,18 +0,0 @@
-#ifndef _HALMAC_FUNC_8822B_H_
-#define _HALMAC_FUNC_8822B_H_
-
-#include "../../halmac_type.h"
-
-HALMAC_RET_STATUS
-halmac_txdma_queue_mapping_8822b(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_TRX_MODE halmac_trx_mode
-);
-
-HALMAC_RET_STATUS
-halmac_priority_queue_config_8822b(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_TRX_MODE halmac_trx_mode
-);
-
-#endif /* _HALMAC_FUNC_8822B_H_ */
diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_gpio_8822b.c b/hal/halmac/halmac_88xx/halmac_8822b/halmac_gpio_8822b.c
new file mode 100644
index 0000000..13f3554
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_gpio_8822b.c
@@ -0,0 +1,831 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_gpio_8822b.h"
+#include "../halmac_gpio_88xx.h"
+
+#if HALMAC_8822B_SUPPORT
+
+/* GPIO0 definition */
+#define GPIO0_BT_GPIO0_8822B \
+ {HALMAC_BT_GPIO, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \
+ 0x66, BIT(2), BIT(2)}
+#define GPIO0_BT_ACT_8822B \
+ {HALMAC_BT_PTA, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \
+ 0x41, BIT(1), 0}
+#define GPIO0_WL_ACT_8822B \
+ {HALMAC_WL_PTA, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \
+ 0x41, BIT(2), BIT(2)}
+#define GPIO0_WLMAC_DBG_GPIO0_8822B \
+ {HALMAC_WLMAC_DBG, HALMAC_GPIO0, HALMAC_GPIO_OUT, \
+ 0x40, BIT(1) | BIT(0), BIT(0)}
+#define GPIO0_WLPHY_DBG_GPIO0_8822B \
+ {HALMAC_WLPHY_DBG, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \
+ 0x40, BIT(1) | BIT(0), BIT(1)}
+#define GPIO0_BT_DBG_GPIO0_8822B \
+ {HALMAC_BT_DBG, HALMAC_GPIO0, HALMAC_GPIO_OUT, \
+ 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)}
+#define GPIO0_SW_IO_8822B \
+ {HALMAC_SW_IO, HALMAC_GPIO0, HALMAC_GPIO_IN_OUT, \
+ 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO1 definition */
+#define GPIO1_BT_GPIO1_8822B \
+ {HALMAC_BT_GPIO, HALMAC_GPIO1, HALMAC_GPIO_IN_OUT, \
+ 0x66, BIT(2), BIT(2)}
+#define GPIO1_BT_3DD_SYNC_A_8822B \
+ {HALMAC_BT_3DDLS_A, HALMAC_GPIO1, HALMAC_GPIO_IN, \
+ 0x66, BIT(2), BIT(2)}
+#define GPIO1_WL_CK_8822B \
+ {HALMAC_BT_PTA, HALMAC_GPIO1, HALMAC_GPIO_OUT, \
+ 0x41, BIT(1), 0}
+#define GPIO1_BT_CK_8822B \
+ {HALMAC_WL_PTA, HALMAC_GPIO1, HALMAC_GPIO_OUT, \
+ 0x41, BIT(2), BIT(2)}
+#define GPIO1_WLMAC_DBG_GPIO1_8822B \
+ {HALMAC_WLMAC_DBG, HALMAC_GPIO1, HALMAC_GPIO_OUT, \
+ 0x40, BIT(1) | BIT(0), BIT(0)}
+#define GPIO1_WLPHY_DBG_GPIO1_8822B \
+ {HALMAC_WLPHY_DBG, HALMAC_GPIO1, HALMAC_GPIO_IN_OUT, \
+ 0x40, BIT(1) | BIT(0), BIT(1)}
+#define GPIO1_BT_DBG_GPIO1_8822B \
+ {HALMAC_BT_DBG, HALMAC_GPIO1, HALMAC_GPIO_OUT, \
+ 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)}
+#define GPIO1_SW_IO_8822B \
+ {HALMAC_SW_IO, HALMAC_GPIO1, HALMAC_GPIO_IN_OUT, \
+ 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO2 definition */
+#define GPIO2_BT_GPIO2_8822B \
+ {HALMAC_BT_GPIO, HALMAC_GPIO2, HALMAC_GPIO_IN_OUT, \
+ 0x66, BIT(2), BIT(2)}
+#define GPIO2_WL_STATE_8822B \
+ {HALMAC_BT_PTA, HALMAC_GPIO2, HALMAC_GPIO_OUT, \
+ 0x41, BIT(1), 0}
+#define GPIO2_BT_STATE_8822B \
+ {HALMAC_WL_PTA, HALMAC_GPIO2, HALMAC_GPIO_OUT, \
+ 0x41, BIT(2), BIT(2)}
+#define GPIO2_WLMAC_DBG_GPIO2_8822B \
+ {HALMAC_WLMAC_DBG, HALMAC_GPIO2, HALMAC_GPIO_OUT, \
+ 0x40, BIT(1) | BIT(0), BIT(0)}
+#define GPIO2_WLPHY_DBG_GPIO2_8822B \
+ {HALMAC_WLPHY_DBG, HALMAC_GPIO2, HALMAC_GPIO_IN_OUT, \
+ 0x40, BIT(1) | BIT(0), BIT(1)}
+#define GPIO2_BT_DBG_GPIO2_8822B \
+ {HALMAC_BT_DBG, HALMAC_GPIO2, HALMAC_GPIO_OUT, \
+ 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)}
+#define GPIO2_RFE_CTRL_5_8822B \
+ {HALMAC_WLPHY_RFE_CTRL2GPIO, HALMAC_GPIO2, HALMAC_GPIO_IN_OUT, \
+ 0x40, BIT(2), BIT(2)}
+#define GPIO2_SW_IO_8822B \
+ {HALMAC_SW_IO, HALMAC_GPIO2, HALMAC_GPIO_IN_OUT, \
+ 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO3 definition */
+#define GPIO3_BT_GPIO3_8822B \
+ {HALMAC_BT_GPIO, HALMAC_GPIO3, HALMAC_GPIO_IN_OUT, \
+ 0x66, BIT(2), BIT(2)}
+#define GPIO3_WL_PRI_8822B \
+ {HALMAC_BT_PTA, HALMAC_GPIO3, HALMAC_GPIO_OUT, \
+ 0x41, BIT(1), 0}
+#define GPIO3_BT_PRI_8822B \
+ {HALMAC_WL_PTA, HALMAC_GPIO3, HALMAC_GPIO_OUT, \
+ 0x41, BIT(2), BIT(2)}
+#define GPIO3_WLMAC_DBG_GPIO3_8822B \
+ {HALMAC_WLMAC_DBG, HALMAC_GPIO3, HALMAC_GPIO_OUT, \
+ 0x40, BIT(1) | BIT(0), BIT(0)}
+#define GPIO3_WLPHY_DBG_GPIO3_8822B \
+ {HALMAC_WLPHY_DBG, HALMAC_GPIO3, HALMAC_GPIO_IN_OUT, \
+ 0x40, BIT(1) | BIT(0), BIT(1)}
+#define GPIO3_BT_DBG_GPIO3_8822B \
+ {HALMAC_BT_DBG, HALMAC_GPIO3, HALMAC_GPIO_OUT, \
+ 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)}
+#define GPIO3_RFE_CTRL_4_8822B \
+ {HALMAC_WLPHY_RFE_CTRL2GPIO, HALMAC_GPIO3, HALMAC_GPIO_IN_OUT, \
+ 0x40, BIT(2), BIT(2)}
+#define GPIO3_SW_IO_8822B \
+ {HALMAC_SW_IO, HALMAC_GPIO3, HALMAC_GPIO_IN_OUT, \
+ 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO4 definition */
+#define GPIO4_BT_SPI_D0_8822B \
+ {HALMAC_BT_SFLASH, HALMAC_GPIO4, HALMAC_GPIO_IN_OUT, \
+ 0x66, BIT(4), BIT(4)}
+#define GPIO4_WL_SPI_D0_8822B \
+ {HALMAC_WL_SFLASH, HALMAC_GPIO4, HALMAC_GPIO_IN_OUT, \
+ 0x42, BIT(3), BIT(3)}
+#define GPIO4_SDIO_INT_8822B \
+ {HALMAC_SDIO_INT, HALMAC_GPIO4, HALMAC_GPIO_OUT, \
+ 0x72, BIT(2), BIT(2)}
+#define GPIO4_JTAG_TRST_8822B \
+ {HALMAC_JTAG, HALMAC_GPIO4, HALMAC_GPIO_IN, \
+ 0x67, BIT(0), BIT(0)}
+#define GPIO4_DBG_GNT_WL_8822B \
+ {HALMAC_DBG_GNT_WL_BT, HALMAC_GPIO4, HALMAC_GPIO_OUT, \
+ 0x73, BIT(3), BIT(3)}
+#define GPIO4_WLMAC_DBG_GPIO4_8822B \
+ {HALMAC_WLMAC_DBG, HALMAC_GPIO4, HALMAC_GPIO_OUT, \
+ 0x40, BIT(1) | BIT(0), BIT(0)}
+#define GPIO4_WLPHY_DBG_GPIO4_8822B \
+ {HALMAC_WLPHY_DBG, HALMAC_GPIO4, HALMAC_GPIO_IN_OUT, \
+ 0x40, BIT(1) | BIT(0), BIT(1)}
+#define GPIO4_BT_DBG_GPIO4_8822B \
+ {HALMAC_BT_DBG, HALMAC_GPIO4, HALMAC_GPIO_OUT, \
+ 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)}
+#define GPIO4_SW_IO_8822B \
+ {HALMAC_SW_IO, HALMAC_GPIO4, HALMAC_GPIO_IN_OUT, \
+ 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO5 definition */
+#define GPIO5_BT_SPI_D1_8822B \
+ {HALMAC_BT_SFLASH, HALMAC_GPIO5, HALMAC_GPIO_IN_OUT, \
+ 0x66, BIT(4), BIT(4)}
+#define GPIO5_WL_SPI_D1_8822B \
+ {HALMAC_WL_SFLASH, HALMAC_GPIO5, HALMAC_GPIO_IN_OUT, \
+ 0x42, BIT(3), BIT(3)}
+#define GPIO5_JTAG_TDI_8822B \
+ {HALMAC_JTAG, HALMAC_GPIO5, HALMAC_GPIO_IN, \
+ 0x67, BIT(0), BIT(0)}
+#define GPIO5_DBG_GNT_BT_8822B \
+ {HALMAC_DBG_GNT_WL_BT, HALMAC_GPIO5, HALMAC_GPIO_OUT, \
+ 0x73, BIT(3), BIT(3)}
+#define GPIO5_WLMAC_DBG_GPIO5_8822B \
+ {HALMAC_WLMAC_DBG, HALMAC_GPIO5, HALMAC_GPIO_OUT, \
+ 0x40, BIT(1) | BIT(0), BIT(0)}
+#define GPIO5_WLPHY_DBG_GPIO5_8822B \
+ {HALMAC_WLPHY_DBG, HALMAC_GPIO5, HALMAC_GPIO_IN_OUT, \
+ 0x40, BIT(1) | BIT(0), BIT(1)}
+#define GPIO5_BT_DBG_GPIO5_8822B \
+ {HALMAC_BT_DBG, HALMAC_GPIO5, HALMAC_GPIO_OUT, \
+ 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)}
+#define GPIO5_SW_IO_8822B \
+ {HALMAC_SW_IO, HALMAC_GPIO5, HALMAC_GPIO_IN_OUT, \
+ 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO6 definition */
+#define GPIO6_BT_SPI_D2_8822B \
+ {HALMAC_BT_SFLASH, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, \
+ 0x66, BIT(4), BIT(4)}
+#define GPIO6_WL_SPI_D2_8822B \
+ {HALMAC_WL_SFLASH, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, \
+ 0x42, BIT(3), BIT(3)}
+#define GPIO6_EEDO_8822B \
+ {HALMAC_EEPROM, HALMAC_GPIO6, HALMAC_GPIO_IN, \
+ 0x40, BIT(4), BIT(4)}
+#define GPIO6_JTAG_TDO_8822B \
+ {HALMAC_JTAG, HALMAC_GPIO6, HALMAC_GPIO_OUT, \
+ 0x67, BIT(0), BIT(0)}
+#define GPIO6_BT_3DD_SYNC_B_8822B \
+ {HALMAC_BT_3DDLS_B, HALMAC_GPIO6, HALMAC_GPIO_IN, \
+ 0x67, BIT(1), BIT(1)}
+#define GPIO6_BT_GPIO18_8822B \
+ {HALMAC_BT_GPIO, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, \
+ 0x67, BIT(1), BIT(1)}
+#define GPIO6_SIN_8822B \
+ {HALMAC_WL_UART, HALMAC_GPIO6, HALMAC_GPIO_IN, \
+ 0x41, BIT(0), BIT(0)}
+#define GPIO6_WLMAC_DBG_GPIO6_8822B \
+ {HALMAC_WLMAC_DBG, HALMAC_GPIO6, HALMAC_GPIO_OUT, \
+ 0x40, BIT(1) | BIT(0), BIT(0)}
+#define GPIO6_WLPHY_DBG_GPIO6_8822B \
+ {HALMAC_WLPHY_DBG, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, \
+ 0x40, BIT(1) | BIT(0), BIT(1)}
+#define GPIO6_BT_DBG_GPIO6_8822B \
+ {HALMAC_BT_DBG, HALMAC_GPIO6, HALMAC_GPIO_OUT, \
+ 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)}
+#define GPIO6_SW_IO_8822B \
+ {HALMAC_SW_IO, HALMAC_GPIO6, HALMAC_GPIO_IN_OUT, \
+ 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO7 definition */
+#define GPIO7_BT_SPI_D3_8822B \
+ {HALMAC_BT_SFLASH, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, \
+ 0x66, BIT(4), BIT(4)}
+#define GPIO7_WL_SPI_D3_8822B \
+ {HALMAC_WL_SFLASH, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, \
+ 0x42, BIT(3), BIT(3)}
+#define GPIO7_EEDI_8822B \
+ {HALMAC_EEPROM, HALMAC_GPIO7, HALMAC_GPIO_OUT, \
+ 0x40, BIT(4), BIT(4)}
+#define GPIO7_JTAG_TMS_8822B \
+ {HALMAC_JTAG, HALMAC_GPIO7, HALMAC_GPIO_IN, \
+ 0x67, BIT(0), BIT(0)}
+#define GPIO7_BT_GPIO16_8822B \
+ {HALMAC_BT_GPIO, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, \
+ 0x67, BIT(2), BIT(2)}
+#define GPIO7_SOUT_8822B \
+ {HALMAC_WL_UART, HALMAC_GPIO7, HALMAC_GPIO_OUT, \
+ 0x41, BIT(0), BIT(0)}
+#define GPIO7_WLMAC_DBG_GPIO7_8822B \
+ {HALMAC_WLMAC_DBG, HALMAC_GPIO7, HALMAC_GPIO_OUT, \
+ 0x40, BIT(1) | BIT(0), BIT(0)}
+#define GPIO7_WLPHY_DBG_GPIO7_8822B \
+ {HALMAC_WLPHY_DBG, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, \
+ 0x40, BIT(1) | BIT(0), BIT(1)}
+#define GPIO7_BT_DBG_GPIO7_8822B \
+ {HALMAC_BT_DBG, HALMAC_GPIO7, HALMAC_GPIO_OUT, \
+ 0x40, BIT(1) | BIT(0), BIT(0) | BIT(1)}
+#define GPIO7_SW_IO_8822B \
+ {HALMAC_SW_IO, HALMAC_GPIO7, HALMAC_GPIO_IN_OUT, \
+ 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO8 definition */
+#define GPIO8_WL_EXT_WOL_8822B \
+ {HALMAC_WL_HW_EXTWOL, HALMAC_GPIO8, HALMAC_GPIO_IN, \
+ 0x4a, BIT(0) | BIT(1), BIT(0) | BIT(1)}
+#define GPIO8_WL_LED_8822B \
+ {HALMAC_WL_LED, HALMAC_GPIO8, HALMAC_GPIO_OUT, \
+ 0x4e, BIT(5), BIT(5)}
+#define GPIO8_SW_IO_8822B \
+ {HALMAC_SW_IO, HALMAC_GPIO8, HALMAC_GPIO_IN_OUT, \
+ 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO9 definition */
+#define GPIO9_DIS_WL_N_8822B \
+ {HALMAC_WL_HWPDN, HALMAC_GPIO9, HALMAC_GPIO_IN, \
+ 0x68, BIT(3) | BIT(0), BIT(3) | BIT(0)}
+#define GPIO9_WL_EXT_WOL_8822B \
+ {HALMAC_WL_HW_EXTWOL, HALMAC_GPIO9, HALMAC_GPIO_IN, \
+ 0x4a, BIT(0) | BIT(1), BIT(0)}
+#define GPIO9_USCTS0_8822B \
+ {HALMAC_UART0, HALMAC_GPIO9, HALMAC_GPIO_IN, \
+ 0x66, BIT(6), BIT(6)}
+#define GPIO9_SW_IO_8822B \
+ {HALMAC_SW_IO, HALMAC_GPIO9, HALMAC_GPIO_IN_OUT, \
+ 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO10 definition */
+#define GPIO10_SW_IO_8822B \
+ {HALMAC_SW_IO, HALMAC_GPIO10, HALMAC_GPIO_IN_OUT, \
+ 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO11 definition */
+#define GPIO11_DIS_BT_N_8822B \
+ {HALMAC_BT_HWPDN, HALMAC_GPIO11, HALMAC_GPIO_IN, \
+ 0x6a, BIT(0), BIT(0)}
+#define GPIO11_USOUT0_8822B \
+ {HALMAC_UART0, HALMAC_GPIO11, HALMAC_GPIO_OUT, \
+ 0x66, BIT(6), BIT(6)}
+#define GPIO11_SW_IO_8822B \
+ {HALMAC_SW_IO, HALMAC_GPIO11, HALMAC_GPIO_IN_OUT, \
+ 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO12 definition */
+#define GPIO12_USIN0_8822B \
+ {HALMAC_UART0, HALMAC_GPIO12, HALMAC_GPIO_IN, \
+ 0x66, BIT(6), BIT(6)}
+#define GPIO12_SW_IO_8822B \
+ {HALMAC_SW_IO, HALMAC_GPIO12, HALMAC_GPIO_IN_OUT, \
+ 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO13 definition */
+#define GPIO13_BT_WAKE_8822B \
+ {HALMAC_GPIO13_14_WL_CTRL_EN, HALMAC_GPIO13, HALMAC_GPIO_IN, \
+ 0x4e, BIT(6), BIT(6)}
+#define GPIO13_SW_IO_8822B \
+ {HALMAC_SW_IO, HALMAC_GPIO13, HALMAC_GPIO_IN_OUT, \
+ 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO14 definition */
+#define GPIO14_UART_WAKE_8822B \
+ {HALMAC_GPIO13_14_WL_CTRL_EN, HALMAC_GPIO14, HALMAC_GPIO_OUT, \
+ 0x4e, BIT(6), BIT(6)}
+#define GPIO14_SW_IO_8822B \
+ {HALMAC_SW_IO, HALMAC_GPIO14, HALMAC_GPIO_IN_OUT, \
+ 0x40, BIT(1) | BIT(0), 0}
+
+/* GPIO15 definition */
+#define GPIO15_EXT_XTAL_8822B \
+ {HALMAC_EXT_XTAL, HALMAC_GPIO15, HALMAC_GPIO_OUT, \
+ 0x66, BIT(7), BIT(7)}
+#define GPIO15_SW_IO_8822B \
+ {HALMAC_SW_IO, HALMAC_GPIO15, HALMAC_GPIO_IN_OUT, \
+ 0x40, BIT(1) | BIT(0), 0}
+
+const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO0_8822B[] = {
+ GPIO0_BT_GPIO0_8822B,
+ GPIO0_BT_ACT_8822B,
+ GPIO0_WL_ACT_8822B,
+ GPIO0_WLMAC_DBG_GPIO0_8822B,
+ GPIO0_WLPHY_DBG_GPIO0_8822B,
+ GPIO0_BT_DBG_GPIO0_8822B,
+ GPIO0_SW_IO_8822B
+};
+
+const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO1_8822B[] = {
+ GPIO1_BT_GPIO1_8822B,
+ GPIO1_BT_3DD_SYNC_A_8822B,
+ GPIO1_WL_CK_8822B,
+ GPIO1_BT_CK_8822B,
+ GPIO1_WLMAC_DBG_GPIO1_8822B,
+ GPIO1_WLPHY_DBG_GPIO1_8822B,
+ GPIO1_BT_DBG_GPIO1_8822B,
+ GPIO1_SW_IO_8822B
+};
+
+const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO2_8822B[] = {
+ GPIO2_BT_GPIO2_8822B,
+ GPIO2_WL_STATE_8822B,
+ GPIO2_BT_STATE_8822B,
+ GPIO2_WLMAC_DBG_GPIO2_8822B,
+ GPIO2_WLPHY_DBG_GPIO2_8822B,
+ GPIO2_BT_DBG_GPIO2_8822B,
+ GPIO2_RFE_CTRL_5_8822B,
+ GPIO2_SW_IO_8822B
+};
+
+const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO3_8822B[] = {
+ GPIO3_BT_GPIO3_8822B,
+ GPIO3_WL_PRI_8822B,
+ GPIO3_BT_PRI_8822B,
+ GPIO3_WLMAC_DBG_GPIO3_8822B,
+ GPIO3_WLPHY_DBG_GPIO3_8822B,
+ GPIO3_BT_DBG_GPIO3_8822B,
+ GPIO3_RFE_CTRL_4_8822B,
+ GPIO3_SW_IO_8822B
+};
+
+const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO4_8822B[] = {
+ GPIO4_BT_SPI_D0_8822B,
+ GPIO4_WL_SPI_D0_8822B,
+ GPIO4_SDIO_INT_8822B,
+ GPIO4_JTAG_TRST_8822B,
+ GPIO4_DBG_GNT_WL_8822B,
+ GPIO4_WLMAC_DBG_GPIO4_8822B,
+ GPIO4_WLPHY_DBG_GPIO4_8822B,
+ GPIO4_BT_DBG_GPIO4_8822B,
+ GPIO4_SW_IO_8822B
+};
+
+const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO5_8822B[] = {
+ GPIO5_BT_SPI_D1_8822B,
+ GPIO5_WL_SPI_D1_8822B,
+ GPIO5_JTAG_TDI_8822B,
+ GPIO5_DBG_GNT_BT_8822B,
+ GPIO5_WLMAC_DBG_GPIO5_8822B,
+ GPIO5_WLPHY_DBG_GPIO5_8822B,
+ GPIO5_BT_DBG_GPIO5_8822B,
+ GPIO5_SW_IO_8822B
+};
+
+const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO6_8822B[] = {
+ GPIO6_BT_SPI_D2_8822B,
+ GPIO6_WL_SPI_D2_8822B,
+ GPIO6_EEDO_8822B,
+ GPIO6_JTAG_TDO_8822B,
+ GPIO6_BT_3DD_SYNC_B_8822B,
+ GPIO6_BT_GPIO18_8822B,
+ GPIO6_SIN_8822B,
+ GPIO6_WLMAC_DBG_GPIO6_8822B,
+ GPIO6_WLPHY_DBG_GPIO6_8822B,
+ GPIO6_BT_DBG_GPIO6_8822B,
+ GPIO6_SW_IO_8822B
+};
+
+const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO7_8822B[] = {
+ GPIO7_BT_SPI_D3_8822B,
+ GPIO7_WL_SPI_D3_8822B,
+ GPIO7_EEDI_8822B,
+ GPIO7_JTAG_TMS_8822B,
+ GPIO7_BT_GPIO16_8822B,
+ GPIO7_SOUT_8822B,
+ GPIO7_WLMAC_DBG_GPIO7_8822B,
+ GPIO7_WLPHY_DBG_GPIO7_8822B,
+ GPIO7_BT_DBG_GPIO7_8822B,
+ GPIO7_SW_IO_8822B
+};
+
+const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO8_8822B[] = {
+ GPIO8_WL_EXT_WOL_8822B,
+ GPIO8_WL_LED_8822B,
+ GPIO8_SW_IO_8822B
+};
+
+const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO9_8822B[] = {
+ GPIO9_DIS_WL_N_8822B,
+ GPIO9_WL_EXT_WOL_8822B,
+ GPIO9_USCTS0_8822B,
+ GPIO9_SW_IO_8822B
+};
+
+const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO10_8822B[] = {
+ GPIO10_SW_IO_8822B
+};
+
+const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO11_8822B[] = {
+ GPIO11_DIS_BT_N_8822B,
+ GPIO11_USOUT0_8822B,
+ GPIO11_SW_IO_8822B
+};
+
+const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO12_8822B[] = {
+ GPIO12_USIN0_8822B,
+ GPIO12_SW_IO_8822B
+};
+
+const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO13_8822B[] = {
+ GPIO13_BT_WAKE_8822B,
+ GPIO13_SW_IO_8822B
+};
+
+const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO14_8822B[] = {
+ GPIO14_UART_WAKE_8822B,
+ GPIO14_SW_IO_8822B
+};
+
+const struct halmac_gpio_pimux_list PIMUX_LIST_GPIO15_8822B[] = {
+ GPIO15_EXT_XTAL_8822B,
+ GPIO15_SW_IO_8822B
+};
+
+static enum halmac_ret_status
+get_pinmux_list_8822b(struct halmac_adapter *adapter,
+ enum halmac_gpio_func gpio_func,
+ const struct halmac_gpio_pimux_list **list,
+ u32 *list_size, u32 *gpio_id);
+
+static enum halmac_ret_status
+chk_pinmux_valid_8822b(struct halmac_adapter *adapter,
+ enum halmac_gpio_func gpio_func);
+
+/**
+ * pinmux_get_func_8822b() -get current gpio status
+ * @adapter : the adapter of halmac
+ * @gpio_func : gpio function
+ * @enable : function is enable(1) or disable(0)
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+pinmux_get_func_8822b(struct halmac_adapter *adapter,
+ enum halmac_gpio_func gpio_func, u8 *enable)
+{
+ u32 list_size;
+ u32 cur_func;
+ u32 gpio_id;
+ enum halmac_ret_status status;
+ const struct halmac_gpio_pimux_list *list = NULL;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ status = get_pinmux_list_8822b(adapter, gpio_func, &list, &list_size,
+ &gpio_id);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+
+ status = pinmux_parser_88xx(adapter, list, list_size, gpio_id,
+ &cur_func);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+
+ switch (gpio_func) {
+ case HALMAC_GPIO_FUNC_WL_LED:
+ *enable = (cur_func == HALMAC_WL_LED) ? 1 : 0;
+ break;
+ case HALMAC_GPIO_FUNC_SDIO_INT:
+ *enable = (cur_func == HALMAC_SDIO_INT) ? 1 : 0;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_0:
+ case HALMAC_GPIO_FUNC_SW_IO_1:
+ case HALMAC_GPIO_FUNC_SW_IO_2:
+ case HALMAC_GPIO_FUNC_SW_IO_3:
+ case HALMAC_GPIO_FUNC_SW_IO_4:
+ case HALMAC_GPIO_FUNC_SW_IO_5:
+ case HALMAC_GPIO_FUNC_SW_IO_6:
+ case HALMAC_GPIO_FUNC_SW_IO_7:
+ case HALMAC_GPIO_FUNC_SW_IO_8:
+ case HALMAC_GPIO_FUNC_SW_IO_9:
+ case HALMAC_GPIO_FUNC_SW_IO_10:
+ case HALMAC_GPIO_FUNC_SW_IO_11:
+ case HALMAC_GPIO_FUNC_SW_IO_12:
+ case HALMAC_GPIO_FUNC_SW_IO_13:
+ case HALMAC_GPIO_FUNC_SW_IO_14:
+ case HALMAC_GPIO_FUNC_SW_IO_15:
+ *enable = (cur_func == HALMAC_SW_IO) ? 1 : 0;
+ break;
+ default:
+ *enable = 0;
+ return HALMAC_RET_GET_PINMUX_ERR;
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * pinmux_set_func_8822b() -set gpio function
+ * @adapter : the adapter of halmac
+ * @gpio_func : gpio function
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+pinmux_set_func_8822b(struct halmac_adapter *adapter,
+ enum halmac_gpio_func gpio_func)
+{
+ u32 list_size;
+ u32 gpio_id;
+ enum halmac_ret_status status;
+ const struct halmac_gpio_pimux_list *list = NULL;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+ PLTFM_MSG_TRACE("[TRACE]func name : %d\n", gpio_func);
+
+ status = chk_pinmux_valid_8822b(adapter, gpio_func);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+
+ status = get_pinmux_list_8822b(adapter, gpio_func, &list, &list_size,
+ &gpio_id);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+
+ status = pinmux_switch_88xx(adapter, list, list_size, gpio_id,
+ gpio_func);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+
+ status = pinmux_record_88xx(adapter, gpio_func, 1);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * pinmux_free_func_8822b() -free locked gpio function
+ * @adapter : the adapter of halmac
+ * @gpio_func : gpio function
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+pinmux_free_func_8822b(struct halmac_adapter *adapter,
+ enum halmac_gpio_func gpio_func)
+{
+ struct halmac_pinmux_info *info = &adapter->pinmux_info;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ switch (gpio_func) {
+ case HALMAC_GPIO_FUNC_SW_IO_0:
+ info->sw_io_0 = 0;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_1:
+ info->sw_io_1 = 0;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_2:
+ info->sw_io_2 = 0;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_3:
+ info->sw_io_3 = 0;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_4:
+ case HALMAC_GPIO_FUNC_SDIO_INT:
+ info->sw_io_4 = 0;
+ info->sdio_int = 0;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_5:
+ info->sw_io_5 = 0;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_6:
+ info->sw_io_6 = 0;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_7:
+ info->sw_io_7 = 0;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_8:
+ case HALMAC_GPIO_FUNC_WL_LED:
+ info->sw_io_8 = 0;
+ info->wl_led = 0;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_9:
+ info->sw_io_9 = 0;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_10:
+ info->sw_io_10 = 0;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_11:
+ info->sw_io_11 = 0;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_12:
+ info->sw_io_12 = 0;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_13:
+ info->sw_io_13 = 0;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_14:
+ info->sw_io_14 = 0;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_15:
+ info->sw_io_15 = 0;
+ break;
+ default:
+ return HALMAC_RET_SWITCH_CASE_ERROR;
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]func : %X\n", gpio_func);
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+get_pinmux_list_8822b(struct halmac_adapter *adapter,
+ enum halmac_gpio_func gpio_func,
+ const struct halmac_gpio_pimux_list **list,
+ u32 *list_size, u32 *gpio_id)
+{
+ switch (gpio_func) {
+ case HALMAC_GPIO_FUNC_SW_IO_0:
+ *list = PIMUX_LIST_GPIO0_8822B;
+ *list_size = ARRAY_SIZE(PIMUX_LIST_GPIO0_8822B);
+ *gpio_id = HALMAC_GPIO0;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_1:
+ *list = PIMUX_LIST_GPIO1_8822B;
+ *list_size = ARRAY_SIZE(PIMUX_LIST_GPIO1_8822B);
+ *gpio_id = HALMAC_GPIO1;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_2:
+ *list = PIMUX_LIST_GPIO2_8822B;
+ *list_size = ARRAY_SIZE(PIMUX_LIST_GPIO2_8822B);
+ *gpio_id = HALMAC_GPIO2;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_3:
+ *list = PIMUX_LIST_GPIO3_8822B;
+ *list_size = ARRAY_SIZE(PIMUX_LIST_GPIO3_8822B);
+ *gpio_id = HALMAC_GPIO3;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_4:
+ case HALMAC_GPIO_FUNC_SDIO_INT:
+ *list = PIMUX_LIST_GPIO4_8822B;
+ *list_size = ARRAY_SIZE(PIMUX_LIST_GPIO4_8822B);
+ *gpio_id = HALMAC_GPIO4;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_5:
+ *list = PIMUX_LIST_GPIO5_8822B;
+ *list_size = ARRAY_SIZE(PIMUX_LIST_GPIO5_8822B);
+ *gpio_id = HALMAC_GPIO5;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_6:
+ *list = PIMUX_LIST_GPIO6_8822B;
+ *list_size = ARRAY_SIZE(PIMUX_LIST_GPIO6_8822B);
+ *gpio_id = HALMAC_GPIO6;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_7:
+ *list = PIMUX_LIST_GPIO7_8822B;
+ *list_size = ARRAY_SIZE(PIMUX_LIST_GPIO7_8822B);
+ *gpio_id = HALMAC_GPIO7;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_8:
+ case HALMAC_GPIO_FUNC_WL_LED:
+ *list = PIMUX_LIST_GPIO8_8822B;
+ *list_size = ARRAY_SIZE(PIMUX_LIST_GPIO8_8822B);
+ *gpio_id = HALMAC_GPIO8;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_9:
+ *list = PIMUX_LIST_GPIO9_8822B;
+ *list_size = ARRAY_SIZE(PIMUX_LIST_GPIO9_8822B);
+ *gpio_id = HALMAC_GPIO9;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_10:
+ *list = PIMUX_LIST_GPIO10_8822B;
+ *list_size = ARRAY_SIZE(PIMUX_LIST_GPIO10_8822B);
+ *gpio_id = HALMAC_GPIO10;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_11:
+ *list = PIMUX_LIST_GPIO11_8822B;
+ *list_size = ARRAY_SIZE(PIMUX_LIST_GPIO11_8822B);
+ *gpio_id = HALMAC_GPIO11;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_12:
+ *list = PIMUX_LIST_GPIO12_8822B;
+ *list_size = ARRAY_SIZE(PIMUX_LIST_GPIO12_8822B);
+ *gpio_id = HALMAC_GPIO12;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_13:
+ *list = PIMUX_LIST_GPIO13_8822B;
+ *list_size = ARRAY_SIZE(PIMUX_LIST_GPIO13_8822B);
+ *gpio_id = HALMAC_GPIO13;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_14:
+ *list = PIMUX_LIST_GPIO14_8822B;
+ *list_size = ARRAY_SIZE(PIMUX_LIST_GPIO14_8822B);
+ *gpio_id = HALMAC_GPIO14;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_15:
+ *list = PIMUX_LIST_GPIO15_8822B;
+ *list_size = ARRAY_SIZE(PIMUX_LIST_GPIO15_8822B);
+ *gpio_id = HALMAC_GPIO15;
+ break;
+ default:
+ return HALMAC_RET_SWITCH_CASE_ERROR;
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+chk_pinmux_valid_8822b(struct halmac_adapter *adapter,
+ enum halmac_gpio_func gpio_func)
+{
+ struct halmac_pinmux_info *info = &adapter->pinmux_info;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ switch (gpio_func) {
+ case HALMAC_GPIO_FUNC_SW_IO_0:
+ if (info->sw_io_0 == 1)
+ status = HALMAC_RET_PINMUX_USED;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_1:
+ if (info->sw_io_1 == 1)
+ status = HALMAC_RET_PINMUX_USED;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_2:
+ if (info->sw_io_2 == 1)
+ status = HALMAC_RET_PINMUX_USED;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_3:
+ if (info->sw_io_3 == 1)
+ status = HALMAC_RET_PINMUX_USED;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_4:
+ case HALMAC_GPIO_FUNC_SDIO_INT:
+ if (info->sw_io_4 == 1 || info->sdio_int == 1)
+ status = HALMAC_RET_PINMUX_USED;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_5:
+ if (info->sw_io_5 == 1)
+ status = HALMAC_RET_PINMUX_USED;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_6:
+ if (info->sw_io_6 == 1)
+ status = HALMAC_RET_PINMUX_USED;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_7:
+ if (info->sw_io_7 == 1)
+ status = HALMAC_RET_PINMUX_USED;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_8:
+ case HALMAC_GPIO_FUNC_WL_LED:
+ if (info->sw_io_8 == 1 || info->wl_led == 1)
+ status = HALMAC_RET_PINMUX_USED;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_9:
+ if (info->sw_io_9 == 1)
+ status = HALMAC_RET_PINMUX_USED;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_10:
+ if (info->sw_io_10 == 1)
+ status = HALMAC_RET_PINMUX_USED;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_11:
+ if (info->sw_io_11 == 1)
+ status = HALMAC_RET_PINMUX_USED;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_12:
+ if (info->sw_io_12 == 1)
+ status = HALMAC_RET_PINMUX_USED;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_13:
+ if (info->sw_io_13 == 1)
+ status = HALMAC_RET_PINMUX_USED;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_14:
+ if (info->sw_io_14 == 1)
+ status = HALMAC_RET_PINMUX_USED;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_15:
+ if (info->sw_io_15 == 1)
+ status = HALMAC_RET_PINMUX_USED;
+ break;
+ default:
+ return HALMAC_RET_SWITCH_CASE_ERROR;
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]chk_pinmux_valid func : %X status : %X\n",
+ gpio_func, status);
+
+ return status;
+}
+
+#endif /* HALMAC_8822B_SUPPORT */
diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_gpio_8822b.h b/hal/halmac/halmac_88xx/halmac_8822b/halmac_gpio_8822b.h
new file mode 100644
index 0000000..6fa0bfa
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_gpio_8822b.h
@@ -0,0 +1,38 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_GPIO_8822B_H_
+#define _HALMAC_GPIO_8822B_H_
+
+#include "../../halmac_api.h"
+#include "../../halmac_gpio_cmd.h"
+
+#if HALMAC_8822B_SUPPORT
+
+enum halmac_ret_status
+pinmux_get_func_8822b(struct halmac_adapter *adapter,
+ enum halmac_gpio_func gpio_func, u8 *enable);
+
+enum halmac_ret_status
+pinmux_set_func_8822b(struct halmac_adapter *adapter,
+ enum halmac_gpio_func gpio_func);
+
+enum halmac_ret_status
+pinmux_free_func_8822b(struct halmac_adapter *adapter,
+ enum halmac_gpio_func gpio_func);
+
+#endif /* HALMAC_8822B_SUPPORT */
+
+#endif/* _HALMAC_GPIO_8822B_H_ */
diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_init_8822b.c b/hal/halmac/halmac_88xx/halmac_8822b/halmac_init_8822b.c
new file mode 100644
index 0000000..6ead4b5
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_init_8822b.c
@@ -0,0 +1,724 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_init_8822b.h"
+#include "halmac_8822b_cfg.h"
+#include "halmac_pcie_8822b.h"
+#include "halmac_sdio_8822b.h"
+#include "halmac_usb_8822b.h"
+#include "halmac_gpio_8822b.h"
+#include "halmac_common_8822b.h"
+#include "halmac_cfg_wmac_8822b.h"
+#include "../halmac_common_88xx.h"
+#include "../halmac_init_88xx.h"
+
+#if HALMAC_8822B_SUPPORT
+
+#define RSVD_PG_DRV_NUM 16
+#define RSVD_PG_H2C_EXTRAINFO_NUM 24
+#define RSVD_PG_H2C_STATICINFO_NUM 8
+#define RSVD_PG_H2CQ_NUM 8
+#define RSVD_PG_CPU_INSTRUCTION_NUM 0
+#define RSVD_PG_FW_TXBUF_NUM 4
+#define RSVD_PG_CSIBUF_NUM 0
+#define RSVD_PG_DLLB_NUM 32
+
+#define MAC_TRX_ENABLE (BIT_HCI_TXDMA_EN | BIT_HCI_RXDMA_EN | BIT_TXDMA_EN | \
+ BIT_RXDMA_EN | BIT_PROTOCOL_EN | BIT_SCHEDULE_EN | \
+ BIT_MACTXEN | BIT_MACRXEN)
+
+#define BLK_DESC_NUM 0x3
+
+#define WLAN_AMPDU_MAX_TIME 0x70
+#define WLAN_RTS_LEN_TH 0xFF
+#define WLAN_RTS_TX_TIME_TH 0x08
+#define WLAN_MAX_AGG_PKT_LIMIT 0x20
+#define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x20
+#define WALN_FAST_EDCA_VO_TH 0x06
+#define WLAN_FAST_EDCA_VI_TH 0x06
+#define WLAN_FAST_EDCA_BE_TH 0x06
+#define WLAN_FAST_EDCA_BK_TH 0x06
+#define WLAN_BAR_RETRY_LIMIT 0x01
+#define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08
+
+#if HALMAC_PLATFORM_WINDOWS
+/*SDIO RQPN Mapping for Windows, extra queue is not implemented in Driver code*/
+struct halmac_rqpn HALMAC_RQPN_SDIO_8822B[] = {
+ /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
+ {HALMAC_TRX_MODE_NORMAL,
+ HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+ HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+ {HALMAC_TRX_MODE_TRXSHARE,
+ HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+ HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+ {HALMAC_TRX_MODE_WMM,
+ HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ,
+ HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+ {HALMAC_TRX_MODE_P2P,
+ HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+ HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+ {HALMAC_TRX_MODE_LOOPBACK,
+ HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+ HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+ {HALMAC_TRX_MODE_DELAY_LOOPBACK,
+ HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+ HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+};
+#else
+/*SDIO RQPN Mapping*/
+struct halmac_rqpn HALMAC_RQPN_SDIO_8822B[] = {
+ /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
+ {HALMAC_TRX_MODE_NORMAL,
+ HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+ HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+ {HALMAC_TRX_MODE_TRXSHARE,
+ HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+ HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+ {HALMAC_TRX_MODE_WMM,
+ HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ,
+ HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+ {HALMAC_TRX_MODE_P2P,
+ HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+ HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+ {HALMAC_TRX_MODE_LOOPBACK,
+ HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+ HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+ {HALMAC_TRX_MODE_DELAY_LOOPBACK,
+ HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+ HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+};
+#endif
+
+/*PCIE RQPN Mapping*/
+struct halmac_rqpn HALMAC_RQPN_PCIE_8822B[] = {
+ /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
+ {HALMAC_TRX_MODE_NORMAL,
+ HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+ HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+ {HALMAC_TRX_MODE_TRXSHARE,
+ HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+ HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+ {HALMAC_TRX_MODE_WMM,
+ HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ,
+ HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+ {HALMAC_TRX_MODE_P2P,
+ HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+ HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+ {HALMAC_TRX_MODE_LOOPBACK,
+ HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+ HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+ {HALMAC_TRX_MODE_DELAY_LOOPBACK,
+ HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+ HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+};
+
+/*USB 2 Bulkout RQPN Mapping*/
+struct halmac_rqpn HALMAC_RQPN_2BULKOUT_8822B[] = {
+ /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
+ {HALMAC_TRX_MODE_NORMAL,
+ HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ,
+ HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+ {HALMAC_TRX_MODE_TRXSHARE,
+ HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ,
+ HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+ {HALMAC_TRX_MODE_WMM,
+ HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ,
+ HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+ {HALMAC_TRX_MODE_P2P,
+ HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ,
+ HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+ {HALMAC_TRX_MODE_LOOPBACK,
+ HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ,
+ HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+ {HALMAC_TRX_MODE_DELAY_LOOPBACK,
+ HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ,
+ HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+};
+
+/*USB 3 Bulkout RQPN Mapping*/
+struct halmac_rqpn HALMAC_RQPN_3BULKOUT_8822B[] = {
+ /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
+ {HALMAC_TRX_MODE_NORMAL,
+ HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+ HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+ {HALMAC_TRX_MODE_TRXSHARE,
+ HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+ HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+ {HALMAC_TRX_MODE_WMM,
+ HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ,
+ HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+ {HALMAC_TRX_MODE_P2P,
+ HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ,
+ HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+ {HALMAC_TRX_MODE_LOOPBACK,
+ HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ,
+ HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+ {HALMAC_TRX_MODE_DELAY_LOOPBACK,
+ HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ,
+ HALMAC_MAP2_HQ, HALMAC_MAP2_HQ},
+};
+
+/*USB 4 Bulkout RQPN Mapping*/
+struct halmac_rqpn HALMAC_RQPN_4BULKOUT_8822B[] = {
+ /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */
+ {HALMAC_TRX_MODE_NORMAL,
+ HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+ HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+ {HALMAC_TRX_MODE_TRXSHARE,
+ HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+ HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+ {HALMAC_TRX_MODE_WMM,
+ HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ,
+ HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+ {HALMAC_TRX_MODE_P2P,
+ HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+ HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+ {HALMAC_TRX_MODE_LOOPBACK,
+ HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+ HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+ {HALMAC_TRX_MODE_DELAY_LOOPBACK,
+ HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ,
+ HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ},
+};
+
+#if HALMAC_PLATFORM_WINDOWS
+/*SDIO Page Number*/
+struct halmac_pg_num HALMAC_PG_NUM_SDIO_8822B[] = {
+ /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
+ {HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 0, 1},
+ {HALMAC_TRX_MODE_TRXSHARE, 32, 32, 32, 0, 1},
+ {HALMAC_TRX_MODE_WMM, 64, 64, 64, 0, 1},
+ {HALMAC_TRX_MODE_P2P, 64, 64, 64, 0, 1},
+ {HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 0, 640},
+ {HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 0, 640},
+};
+#else
+/*SDIO Page Number*/
+struct halmac_pg_num HALMAC_PG_NUM_SDIO_8822B[] = {
+ /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
+ {HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 64, 1},
+ {HALMAC_TRX_MODE_TRXSHARE, 32, 32, 32, 32, 1},
+ {HALMAC_TRX_MODE_WMM, 64, 64, 64, 64, 1},
+ {HALMAC_TRX_MODE_P2P, 64, 64, 64, 64, 1},
+ {HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 640},
+ {HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 640},
+};
+#endif
+
+/*PCIE Page Number*/
+struct halmac_pg_num HALMAC_PG_NUM_PCIE_8822B[] = {
+ /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
+ {HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 64, 1},
+ {HALMAC_TRX_MODE_TRXSHARE, 64, 64, 64, 64, 1},
+ {HALMAC_TRX_MODE_WMM, 64, 64, 64, 64, 1},
+ {HALMAC_TRX_MODE_P2P, 64, 64, 64, 64, 1},
+ {HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 640},
+ {HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 640},
+};
+
+/*USB 2 Bulkout Page Number*/
+struct halmac_pg_num HALMAC_PG_NUM_2BULKOUT_8822B[] = {
+ /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
+ {HALMAC_TRX_MODE_NORMAL, 64, 64, 0, 0, 1},
+ {HALMAC_TRX_MODE_TRXSHARE, 64, 64, 0, 0, 1},
+ {HALMAC_TRX_MODE_WMM, 64, 64, 0, 0, 1},
+ {HALMAC_TRX_MODE_P2P, 64, 64, 0, 0, 1},
+ {HALMAC_TRX_MODE_LOOPBACK, 64, 64, 0, 0, 1024},
+ {HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 0, 0, 1024},
+};
+
+/*USB 3 Bulkout Page Number*/
+struct halmac_pg_num HALMAC_PG_NUM_3BULKOUT_8822B[] = {
+ /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
+ {HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 0, 1},
+ {HALMAC_TRX_MODE_TRXSHARE, 64, 64, 64, 0, 1},
+ {HALMAC_TRX_MODE_WMM, 64, 64, 64, 0, 1},
+ {HALMAC_TRX_MODE_P2P, 64, 64, 64, 0, 1},
+ {HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 0, 1024},
+ {HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 0, 1024},
+};
+
+/*USB 4 Bulkout Page Number*/
+struct halmac_pg_num HALMAC_PG_NUM_4BULKOUT_8822B[] = {
+ /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */
+ {HALMAC_TRX_MODE_NORMAL, 64, 64, 64, 64, 1},
+ {HALMAC_TRX_MODE_TRXSHARE, 64, 64, 64, 64, 1},
+ {HALMAC_TRX_MODE_WMM, 64, 64, 64, 64, 1},
+ {HALMAC_TRX_MODE_P2P, 64, 64, 64, 64, 1},
+ {HALMAC_TRX_MODE_LOOPBACK, 64, 64, 64, 64, 640},
+ {HALMAC_TRX_MODE_DELAY_LOOPBACK, 64, 64, 64, 64, 640},
+};
+
+static enum halmac_ret_status
+txdma_queue_mapping_8822b(struct halmac_adapter *adapter,
+ enum halmac_trx_mode mode);
+
+static enum halmac_ret_status
+priority_queue_cfg_8822b(struct halmac_adapter *adapter,
+ enum halmac_trx_mode mode);
+
+static enum halmac_ret_status
+set_trx_fifo_info_8822b(struct halmac_adapter *adapter,
+ enum halmac_trx_mode mode);
+enum halmac_ret_status
+mount_api_8822b(struct halmac_adapter *adapter)
+{
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ adapter->chip_id = HALMAC_CHIP_ID_8822B;
+ adapter->hw_cfg_info.efuse_size = EFUSE_SIZE_8822B;
+ adapter->hw_cfg_info.eeprom_size = EEPROM_SIZE_8822B;
+ adapter->hw_cfg_info.bt_efuse_size = BT_EFUSE_SIZE_8822B;
+ adapter->hw_cfg_info.cam_entry_num = SEC_CAM_NUM_8822B;
+ adapter->hw_cfg_info.tx_fifo_size = TX_FIFO_SIZE_8822B;
+ adapter->hw_cfg_info.rx_fifo_size = RX_FIFO_SIZE_8822B;
+ adapter->hw_cfg_info.ac_oqt_size = OQT_ENTRY_AC_8822B;
+ adapter->hw_cfg_info.non_ac_oqt_size = OQT_ENTRY_NOAC_8822B;
+ adapter->hw_cfg_info.usb_txagg_num = BLK_DESC_NUM;
+ adapter->txff_alloc.rsvd_drv_pg_num = RSVD_PG_DRV_NUM;
+
+ api->halmac_init_trx_cfg = init_trx_cfg_8822b;
+ api->halmac_init_protocol_cfg = init_protocol_cfg_8822b;
+ api->halmac_init_h2c = init_h2c_8822b;
+ api->halmac_pinmux_get_func = pinmux_get_func_8822b;
+ api->halmac_pinmux_set_func = pinmux_set_func_8822b;
+ api->halmac_pinmux_free_func = pinmux_free_func_8822b;
+ api->halmac_get_hw_value = get_hw_value_8822b;
+ api->halmac_set_hw_value = set_hw_value_8822b;
+ api->halmac_cfg_drv_info = cfg_drv_info_8822b;
+ api->halmac_fill_txdesc_checksum = fill_txdesc_check_sum_8822b;
+ api->halmac_init_low_pwr = init_low_pwr_8822b;
+
+ if (adapter->intf == HALMAC_INTERFACE_SDIO) {
+ api->halmac_mac_power_switch = mac_pwr_switch_sdio_8822b;
+ api->halmac_phy_cfg = phy_cfg_sdio_8822b;
+ api->halmac_pcie_switch = pcie_switch_sdio_8822b;
+ api->halmac_interface_integration_tuning = intf_tun_sdio_8822b;
+ api->halmac_tx_allowed_sdio = tx_allowed_sdio_8822b;
+ api->halmac_get_sdio_tx_addr = get_sdio_tx_addr_8822b;
+ api->halmac_reg_read_8 = reg_r8_sdio_8822b;
+ api->halmac_reg_write_8 = reg_w8_sdio_8822b;
+ api->halmac_reg_read_16 = reg_r16_sdio_8822b;
+ api->halmac_reg_write_16 = reg_w16_sdio_8822b;
+ api->halmac_reg_read_32 = reg_r32_sdio_8822b;
+ api->halmac_reg_write_32 = reg_w32_sdio_8822b;
+
+ adapter->sdio_fs.macid_map_size = MACID_MAX_8822B * 2;
+ if (!adapter->sdio_fs.macid_map) {
+ adapter->sdio_fs.macid_map =
+ (u8 *)PLTFM_MALLOC(adapter->sdio_fs.macid_map_size);
+ if (!adapter->sdio_fs.macid_map)
+ PLTFM_MSG_ERR("[ERR]allocate macid_map!!\n");
+ }
+ } else if (adapter->intf == HALMAC_INTERFACE_USB) {
+ api->halmac_mac_power_switch = mac_pwr_switch_usb_8822b;
+ api->halmac_phy_cfg = phy_cfg_usb_8822b;
+ api->halmac_pcie_switch = pcie_switch_usb_8822b;
+ api->halmac_interface_integration_tuning = intf_tun_usb_8822b;
+ } else if (adapter->intf == HALMAC_INTERFACE_PCIE) {
+ api->halmac_mac_power_switch = mac_pwr_switch_pcie_8822b;
+ api->halmac_phy_cfg = phy_cfg_pcie_8822b;
+ api->halmac_pcie_switch = pcie_switch_8822b;
+ api->halmac_interface_integration_tuning = intf_tun_pcie_8822b;
+ } else {
+ PLTFM_MSG_ERR("[ERR]Undefined IC\n");
+ return HALMAC_RET_CHIP_NOT_SUPPORT;
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * init_trx_cfg_8822b() - config trx dma register
+ * @adapter : the adapter of halmac
+ * @mode : trx mode selection
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+init_trx_cfg_8822b(struct halmac_adapter *adapter, enum halmac_trx_mode mode)
+{
+ u8 value8;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ adapter->trx_mode = mode;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ status = txdma_queue_mapping_8822b(adapter, mode);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]queue mapping\n");
+ return status;
+ }
+
+ value8 = 0;
+ HALMAC_REG_W8(REG_CR, value8);
+ value8 = MAC_TRX_ENABLE;
+ HALMAC_REG_W8(REG_CR, value8);
+ HALMAC_REG_W32(REG_H2CQ_CSR, BIT(31));
+
+ status = priority_queue_cfg_8822b(adapter, mode);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]halmac_txdma_queue_mapping fail!\n");
+ return status;
+ }
+
+ if (adapter->txff_alloc.rx_fifo_exp_mode !=
+ HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE)
+ HALMAC_REG_W8(REG_RX_DRVINFO_SZ, RX_DESC_DUMMY_SIZE_8822B >> 3);
+
+ status = init_h2c_8822b(adapter);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]init h2cq!\n");
+ return status;
+ }
+
+ if (adapter->intf == HALMAC_INTERFACE_USB)
+ HALMAC_REG_W8_SET(REG_TXDMA_PQ_MAP, BIT(0));
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+txdma_queue_mapping_8822b(struct halmac_adapter *adapter,
+ enum halmac_trx_mode mode)
+{
+ u16 value16;
+ struct halmac_rqpn *cur_rqpn_sel = NULL;
+ enum halmac_ret_status status;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ if (adapter->intf == HALMAC_INTERFACE_SDIO) {
+ cur_rqpn_sel = HALMAC_RQPN_SDIO_8822B;
+ } else if (adapter->intf == HALMAC_INTERFACE_PCIE) {
+ cur_rqpn_sel = HALMAC_RQPN_PCIE_8822B;
+ } else if (adapter->intf == HALMAC_INTERFACE_USB) {
+ if (adapter->bulkout_num == 2) {
+ cur_rqpn_sel = HALMAC_RQPN_2BULKOUT_8822B;
+ } else if (adapter->bulkout_num == 3) {
+ cur_rqpn_sel = HALMAC_RQPN_3BULKOUT_8822B;
+ } else if (adapter->bulkout_num == 4) {
+ cur_rqpn_sel = HALMAC_RQPN_4BULKOUT_8822B;
+ } else {
+ PLTFM_MSG_ERR("[ERR]invalid intf\n");
+ return HALMAC_RET_NOT_SUPPORT;
+ }
+ } else {
+ return HALMAC_RET_NOT_SUPPORT;
+ }
+
+ status = rqpn_parser_88xx(adapter, mode, cur_rqpn_sel);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+
+ value16 = 0;
+ value16 |= BIT_TXDMA_HIQ_MAP(adapter->pq_map[HALMAC_PQ_MAP_HI]);
+ value16 |= BIT_TXDMA_MGQ_MAP(adapter->pq_map[HALMAC_PQ_MAP_MG]);
+ value16 |= BIT_TXDMA_BKQ_MAP(adapter->pq_map[HALMAC_PQ_MAP_BK]);
+ value16 |= BIT_TXDMA_BEQ_MAP(adapter->pq_map[HALMAC_PQ_MAP_BE]);
+ value16 |= BIT_TXDMA_VIQ_MAP(adapter->pq_map[HALMAC_PQ_MAP_VI]);
+ value16 |= BIT_TXDMA_VOQ_MAP(adapter->pq_map[HALMAC_PQ_MAP_VO]);
+ HALMAC_REG_W16(REG_TXDMA_PQ_MAP, value16);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+priority_queue_cfg_8822b(struct halmac_adapter *adapter,
+ enum halmac_trx_mode mode)
+{
+ u8 transfer_mode = 0;
+ u8 value8;
+ u32 cnt;
+ struct halmac_txff_allocation *txff_info = &adapter->txff_alloc;
+ enum halmac_ret_status status;
+ struct halmac_pg_num *cur_pg_num = NULL;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ status = set_trx_fifo_info_8822b(adapter, mode);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]set trx fifo!!\n");
+ return status;
+ }
+ if (adapter->intf == HALMAC_INTERFACE_SDIO) {
+ cur_pg_num = HALMAC_PG_NUM_SDIO_8822B;
+ } else if (adapter->intf == HALMAC_INTERFACE_PCIE) {
+ cur_pg_num = HALMAC_PG_NUM_PCIE_8822B;
+ } else if (adapter->intf == HALMAC_INTERFACE_USB) {
+ if (adapter->bulkout_num == 2) {
+ cur_pg_num = HALMAC_PG_NUM_2BULKOUT_8822B;
+ } else if (adapter->bulkout_num == 3) {
+ cur_pg_num = HALMAC_PG_NUM_3BULKOUT_8822B;
+ } else if (adapter->bulkout_num == 4) {
+ cur_pg_num = HALMAC_PG_NUM_4BULKOUT_8822B;
+ } else {
+ PLTFM_MSG_ERR("[ERR]interface not support\n");
+ return HALMAC_RET_NOT_SUPPORT;
+ }
+ } else {
+ return HALMAC_RET_NOT_SUPPORT;
+ }
+
+ status = pg_num_parser_88xx(adapter, mode, cur_pg_num);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+
+ HALMAC_REG_W16(REG_FIFOPAGE_INFO_1, txff_info->high_queue_pg_num);
+ HALMAC_REG_W16(REG_FIFOPAGE_INFO_2, txff_info->low_queue_pg_num);
+ HALMAC_REG_W16(REG_FIFOPAGE_INFO_3, txff_info->normal_queue_pg_num);
+ HALMAC_REG_W16(REG_FIFOPAGE_INFO_4, txff_info->extra_queue_pg_num);
+ HALMAC_REG_W16(REG_FIFOPAGE_INFO_5, txff_info->pub_queue_pg_num);
+ HALMAC_REG_W32_SET(REG_RQPN_CTRL_2, BIT(31));
+
+ adapter->sdio_fs.hiq_pg_num = txff_info->high_queue_pg_num;
+ adapter->sdio_fs.miq_pg_num = txff_info->normal_queue_pg_num;
+ adapter->sdio_fs.lowq_pg_num = txff_info->low_queue_pg_num;
+ adapter->sdio_fs.pubq_pg_num = txff_info->pub_queue_pg_num;
+ adapter->sdio_fs.exq_pg_num = txff_info->extra_queue_pg_num;
+
+ HALMAC_REG_W16(REG_FIFOPAGE_CTRL_2, txff_info->rsvd_boundary);
+ HALMAC_REG_W8_SET(REG_FWHW_TXQ_CTRL + 2, BIT(4));
+
+ /*20170411 Soar*/
+ /* SDIO sometimes use two CMD52 to do HALMAC_REG_W16 */
+ /* and may cause a mismatch between HW status and Reg value. */
+ /* A patch is to write high byte first, suggested by Argis */
+ if (adapter->intf == HALMAC_INTERFACE_SDIO) {
+ value8 = (u8)(txff_info->rsvd_boundary >> 8 & 0xFF);
+ HALMAC_REG_W8(REG_BCNQ_BDNY_V1 + 1, value8);
+ value8 = (u8)(txff_info->rsvd_boundary & 0xFF);
+ HALMAC_REG_W8(REG_BCNQ_BDNY_V1, value8);
+ } else {
+ HALMAC_REG_W16(REG_BCNQ_BDNY_V1, txff_info->rsvd_boundary);
+ }
+
+ HALMAC_REG_W16(REG_FIFOPAGE_CTRL_2 + 2, txff_info->rsvd_boundary);
+
+ /*20170411 Soar*/
+ /* SDIO sometimes use two CMD52 to do HALMAC_REG_W16 */
+ /* and may cause a mismatch between HW status and Reg value. */
+ /* A patch is to write high byte first, suggested by Argis */
+ if (adapter->intf == HALMAC_INTERFACE_SDIO) {
+ value8 = (u8)(txff_info->rsvd_boundary >> 8 & 0xFF);
+ HALMAC_REG_W8(REG_BCNQ1_BDNY_V1 + 1, value8);
+ value8 = (u8)(txff_info->rsvd_boundary & 0xFF);
+ HALMAC_REG_W8(REG_BCNQ1_BDNY_V1, value8);
+ } else {
+ HALMAC_REG_W16(REG_BCNQ1_BDNY_V1, txff_info->rsvd_boundary);
+ }
+
+ HALMAC_REG_W32(REG_RXFF_BNDY,
+ adapter->hw_cfg_info.rx_fifo_size -
+ C2H_PKT_BUF_88XX - 1);
+
+ if (adapter->intf == HALMAC_INTERFACE_USB) {
+ value8 = HALMAC_REG_R8(REG_AUTO_LLT_V1);
+ value8 &= ~(BIT_MASK_BLK_DESC_NUM << BIT_SHIFT_BLK_DESC_NUM);
+ value8 |= (BLK_DESC_NUM << BIT_SHIFT_BLK_DESC_NUM);
+ HALMAC_REG_W8(REG_AUTO_LLT_V1, value8);
+
+ HALMAC_REG_W8(REG_AUTO_LLT_V1 + 3, BLK_DESC_NUM);
+ HALMAC_REG_W8_SET(REG_TXDMA_OFFSET_CHK + 1, BIT(1));
+ }
+
+ HALMAC_REG_W8_SET(REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1);
+ cnt = 1000;
+ while (HALMAC_REG_R8(REG_AUTO_LLT_V1) & BIT_AUTO_INIT_LLT_V1) {
+ cnt--;
+ if (cnt == 0)
+ return HALMAC_RET_INIT_LLT_FAIL;
+ }
+
+ if (mode == HALMAC_TRX_MODE_DELAY_LOOPBACK) {
+ transfer_mode = HALMAC_TRNSFER_LOOPBACK_DELAY;
+ HALMAC_REG_W16(REG_WMAC_LBK_BUF_HD_V1,
+ adapter->txff_alloc.rsvd_boundary);
+ } else if (mode == HALMAC_TRX_MODE_LOOPBACK) {
+ transfer_mode = HALMAC_TRNSFER_LOOPBACK_DIRECT;
+ } else {
+ transfer_mode = HALMAC_TRNSFER_NORMAL;
+ }
+
+ adapter->hw_cfg_info.trx_mode = transfer_mode;
+ HALMAC_REG_W8(REG_CR + 3, transfer_mode);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+set_trx_fifo_info_8822b(struct halmac_adapter *adapter,
+ enum halmac_trx_mode mode)
+{
+ u16 cur_pg_addr;
+ u32 txff_size = TX_FIFO_SIZE_8822B;
+ u32 rxff_size = RX_FIFO_SIZE_8822B;
+ struct halmac_txff_allocation *info = &adapter->txff_alloc;
+
+ if (info->rx_fifo_exp_mode == HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK) {
+ txff_size = TX_FIFO_SIZE_RX_EXPAND_1BLK_8822B;
+ rxff_size = RX_FIFO_SIZE_RX_EXPAND_1BLK_8822B;
+ }
+
+ if (info->la_mode != HALMAC_LA_MODE_DISABLE) {
+ txff_size = TX_FIFO_SIZE_LA_8822B;
+ rxff_size = RX_FIFO_SIZE_8822B;
+ }
+
+ adapter->hw_cfg_info.tx_fifo_size = txff_size;
+ adapter->hw_cfg_info.rx_fifo_size = rxff_size;
+ info->tx_fifo_pg_num = (u16)(txff_size >> TX_PAGE_SIZE_SHIFT_88XX);
+
+ info->rsvd_pg_num = info->rsvd_drv_pg_num +
+ RSVD_PG_H2C_EXTRAINFO_NUM +
+ RSVD_PG_H2C_STATICINFO_NUM +
+ RSVD_PG_H2CQ_NUM +
+ RSVD_PG_CPU_INSTRUCTION_NUM +
+ RSVD_PG_FW_TXBUF_NUM +
+ RSVD_PG_CSIBUF_NUM;
+
+ if (mode == HALMAC_TRX_MODE_DELAY_LOOPBACK)
+ info->rsvd_pg_num += RSVD_PG_DLLB_NUM;
+
+ if (info->rsvd_pg_num > info->tx_fifo_pg_num)
+ return HALMAC_RET_CFG_TXFIFO_PAGE_FAIL;
+
+ info->acq_pg_num = info->tx_fifo_pg_num - info->rsvd_pg_num;
+ info->rsvd_boundary = info->tx_fifo_pg_num - info->rsvd_pg_num;
+
+ cur_pg_addr = info->tx_fifo_pg_num;
+ cur_pg_addr -= RSVD_PG_CSIBUF_NUM;
+ info->rsvd_csibuf_addr = cur_pg_addr;
+ cur_pg_addr -= RSVD_PG_FW_TXBUF_NUM;
+ info->rsvd_fw_txbuf_addr = cur_pg_addr;
+ cur_pg_addr -= RSVD_PG_CPU_INSTRUCTION_NUM;
+ info->rsvd_cpu_instr_addr = cur_pg_addr;
+ cur_pg_addr -= RSVD_PG_H2CQ_NUM;
+ info->rsvd_h2cq_addr = cur_pg_addr;
+ cur_pg_addr -= RSVD_PG_H2C_STATICINFO_NUM;
+ info->rsvd_h2c_sta_info_addr = cur_pg_addr;
+ cur_pg_addr -= RSVD_PG_H2C_EXTRAINFO_NUM;
+ info->rsvd_h2c_info_addr = cur_pg_addr;
+ cur_pg_addr -= info->rsvd_drv_pg_num;
+ info->rsvd_drv_addr = cur_pg_addr;
+
+ if (mode == HALMAC_TRX_MODE_DELAY_LOOPBACK)
+ info->rsvd_drv_addr -= RSVD_PG_DLLB_NUM;
+
+ if (info->rsvd_boundary != info->rsvd_drv_addr)
+ return HALMAC_RET_CFG_TXFIFO_PAGE_FAIL;
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * init_protocol_cfg_8822b() - config protocol register
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+init_protocol_cfg_8822b(struct halmac_adapter *adapter)
+{
+ u32 value32;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ HALMAC_REG_W8_CLR(REG_SW_AMPDU_BURST_MODE_CTRL, BIT(6));
+
+ HALMAC_REG_W8(REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME);
+ HALMAC_REG_W8(REG_TX_HANG_CTRL, BIT_EN_EOF_V1);
+
+ value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) |
+ (WLAN_MAX_AGG_PKT_LIMIT << 16) |
+ (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24);
+ HALMAC_REG_W32(REG_PROT_MODE_CTRL, value32);
+
+ HALMAC_REG_W16(REG_BAR_MODE_CTRL + 2,
+ WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8);
+
+ HALMAC_REG_W8(REG_FAST_EDCA_VOVI_SETTING, WALN_FAST_EDCA_VO_TH);
+ HALMAC_REG_W8(REG_FAST_EDCA_VOVI_SETTING + 2, WLAN_FAST_EDCA_VI_TH);
+ HALMAC_REG_W8(REG_FAST_EDCA_BEBK_SETTING, WLAN_FAST_EDCA_BE_TH);
+ HALMAC_REG_W8(REG_FAST_EDCA_BEBK_SETTING + 2, WLAN_FAST_EDCA_BK_TH);
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * init_h2c_8822b() - config h2c packet buffer
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+init_h2c_8822b(struct halmac_adapter *adapter)
+{
+ u8 value8;
+ u32 value32;
+ u32 h2cq_addr;
+ u32 h2cq_size;
+ struct halmac_txff_allocation *txff_info = &adapter->txff_alloc;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ h2cq_addr = txff_info->rsvd_h2cq_addr << TX_PAGE_SIZE_SHIFT_88XX;
+ h2cq_size = RSVD_PG_H2CQ_NUM << TX_PAGE_SIZE_SHIFT_88XX;
+
+ value32 = HALMAC_REG_R32(REG_H2C_HEAD);
+ value32 = (value32 & 0xFFFC0000) | h2cq_addr;
+ HALMAC_REG_W32(REG_H2C_HEAD, value32);
+
+ value32 = HALMAC_REG_R32(REG_H2C_READ_ADDR);
+ value32 = (value32 & 0xFFFC0000) | h2cq_addr;
+ HALMAC_REG_W32(REG_H2C_READ_ADDR, value32);
+
+ value32 = HALMAC_REG_R32(REG_H2C_TAIL);
+ value32 &= 0xFFFC0000;
+ value32 |= (h2cq_addr + h2cq_size);
+ HALMAC_REG_W32(REG_H2C_TAIL, value32);
+
+ value8 = HALMAC_REG_R8(REG_H2C_INFO);
+ value8 = (u8)((value8 & 0xFC) | 0x01);
+ HALMAC_REG_W8(REG_H2C_INFO, value8);
+
+ value8 = HALMAC_REG_R8(REG_H2C_INFO);
+ value8 = (u8)((value8 & 0xFB) | 0x04);
+ HALMAC_REG_W8(REG_H2C_INFO, value8);
+
+ value8 = HALMAC_REG_R8(REG_TXDMA_OFFSET_CHK + 1);
+ value8 = (u8)((value8 & 0x7f) | 0x80);
+ HALMAC_REG_W8(REG_TXDMA_OFFSET_CHK + 1, value8);
+
+ adapter->h2c_info.buf_size = h2cq_size;
+ get_h2c_buf_free_space_88xx(adapter);
+
+ if (adapter->h2c_info.buf_size != adapter->h2c_info.buf_fs) {
+ PLTFM_MSG_ERR("[ERR]get h2c free space error!\n");
+ return HALMAC_RET_GET_H2C_SPACE_ERR;
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]h2c fs : %d\n", adapter->h2c_info.buf_fs);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+#endif /* HALMAC_8822B_SUPPORT */
diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_init_8822b.h b/hal/halmac/halmac_88xx/halmac_8822b/halmac_init_8822b.h
new file mode 100644
index 0000000..6c26128
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_init_8822b.h
@@ -0,0 +1,37 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_INIT_8822B_H_
+#define _HALMAC_INIT_8822B_H_
+
+#include "../../halmac_api.h"
+
+#if HALMAC_8822B_SUPPORT
+
+enum halmac_ret_status
+mount_api_8822b(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+init_trx_cfg_8822b(struct halmac_adapter *adapter, enum halmac_trx_mode mode);
+
+enum halmac_ret_status
+init_protocol_cfg_8822b(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+init_h2c_8822b(struct halmac_adapter *adapter);
+
+#endif /* HALMAC_8822B_SUPPORT */
+
+#endif/* _HALMAC_INIT_8822B_H_ */
diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_pcie_8822b.c b/hal/halmac/halmac_88xx/halmac_8822b/halmac_pcie_8822b.c
new file mode 100644
index 0000000..deb44ff
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_pcie_8822b.c
@@ -0,0 +1,214 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_pcie_8822b.h"
+#include "halmac_pwr_seq_8822b.h"
+#include "../halmac_init_88xx.h"
+#include "../halmac_common_88xx.h"
+#include "../halmac_pcie_88xx.h"
+#include "../halmac_88xx_cfg.h"
+
+#if HALMAC_8822B_SUPPORT
+
+/**
+ * mac_pwr_switch_pcie_8822b() - switch mac power
+ * @adapter : the adapter of halmac
+ * @pwr : power state
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+mac_pwr_switch_pcie_8822b(struct halmac_adapter *adapter,
+ enum halmac_mac_power pwr)
+{
+ u8 value8;
+ u8 rpwm;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+ enum halmac_ret_status status;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+ PLTFM_MSG_TRACE("[TRACE]pwr = %x\n", pwr);
+ PLTFM_MSG_TRACE("[TRACE]8822B pwr seq ver = %s\n",
+ HALMAC_8822B_PWR_SEQ_VER);
+
+ adapter->rpwm = HALMAC_REG_R8(REG_PCIE_HRPWM1_V1);
+
+ /* Check FW still exist or not */
+ if (HALMAC_REG_R16(REG_MCUFW_CTRL) == 0xC078) {
+ /* Leave 32K */
+ rpwm = (u8)((adapter->rpwm ^ BIT(7)) & 0x80);
+ HALMAC_REG_W8(REG_PCIE_HRPWM1_V1, rpwm);
+ }
+
+ value8 = HALMAC_REG_R8(REG_CR);
+ if (value8 == 0xEA)
+ adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_OFF;
+ else
+ adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_ON;
+
+ /* Check if power switch is needed */
+ if (pwr == HALMAC_MAC_POWER_ON &&
+ adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_ON) {
+ PLTFM_MSG_WARN("[WARN]power state unchange!!\n");
+ return HALMAC_RET_PWR_UNCHANGE;
+ }
+
+ if (pwr == HALMAC_MAC_POWER_OFF) {
+ status = trxdma_check_idle_88xx(adapter);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+ if (pwr_seq_parser_88xx(adapter, card_dis_flow_8822b) !=
+ HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]Handle power off cmd error\n");
+ return HALMAC_RET_POWER_OFF_FAIL;
+ }
+
+ adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_OFF;
+ adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE;
+ init_adapter_dynamic_param_88xx(adapter);
+ } else {
+ if (pwr_seq_parser_88xx(adapter, card_en_flow_8822b) !=
+ HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]Handle power on cmd error\n");
+ return HALMAC_RET_POWER_ON_FAIL;
+ }
+
+ adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_ON;
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_pcie_switch_8822b() - pcie gen1/gen2 switch
+ * @adapter : the adapter of halmac
+ * @cfg : gen1/gen2 selection
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+pcie_switch_8822b(struct halmac_adapter *adapter, enum halmac_pcie_cfg cfg)
+{
+ u8 value8;
+ u32 value32;
+ u8 speed = 0;
+ u32 cnt = 0;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (cfg == HALMAC_PCIE_GEN1) {
+ value8 = dbi_r8_88xx(adapter, LINK_CTRL2_REG_OFFSET) & 0xF0;
+ dbi_w8_88xx(adapter, LINK_CTRL2_REG_OFFSET, value8 | BIT(0));
+
+ value32 = dbi_r32_88xx(adapter, GEN2_CTRL_OFFSET);
+ dbi_w32_88xx(adapter, GEN2_CTRL_OFFSET, value32 | BIT(17));
+
+ speed = dbi_r8_88xx(adapter, LINK_STATUS_REG_OFFSET) & 0x0F;
+ cnt = 2000;
+
+ while ((speed != PCIE_GEN1_SPEED) && (cnt != 0)) {
+ PLTFM_DELAY_US(50);
+ speed = dbi_r8_88xx(adapter, LINK_STATUS_REG_OFFSET);
+ speed &= 0x0F;
+ cnt--;
+ }
+
+ if (speed != PCIE_GEN1_SPEED) {
+ PLTFM_MSG_ERR("[ERR]Speed change to GEN1 fail !\n");
+ return HALMAC_RET_FAIL;
+ }
+
+ } else if (cfg == HALMAC_PCIE_GEN2) {
+ value8 = dbi_r8_88xx(adapter, LINK_CTRL2_REG_OFFSET) & 0xF0;
+ dbi_w8_88xx(adapter, LINK_CTRL2_REG_OFFSET, value8 | BIT(1));
+
+ value32 = dbi_r32_88xx(adapter, GEN2_CTRL_OFFSET);
+ dbi_w32_88xx(adapter, GEN2_CTRL_OFFSET, value32 | BIT(17));
+
+ speed = dbi_r8_88xx(adapter, LINK_STATUS_REG_OFFSET) & 0x0F;
+ cnt = 2000;
+
+ while ((speed != PCIE_GEN2_SPEED) && (cnt != 0)) {
+ PLTFM_DELAY_US(50);
+ speed = dbi_r8_88xx(adapter, LINK_STATUS_REG_OFFSET);
+ speed &= 0x0F;
+ cnt--;
+ }
+
+ if (speed != PCIE_GEN2_SPEED) {
+ PLTFM_MSG_ERR("[ERR]Speed change to GEN1 fail !\n");
+ return HALMAC_RET_FAIL;
+ }
+
+ } else {
+ PLTFM_MSG_ERR("[ERR]Error Speed !\n");
+ return HALMAC_RET_FAIL;
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * phy_cfg_pcie_8822b() - phy config
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+phy_cfg_pcie_8822b(struct halmac_adapter *adapter,
+ enum halmac_intf_phy_platform pltfm)
+{
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ status = parse_intf_phy_88xx(adapter, pcie_gen1_phy_param_8822b, pltfm,
+ HAL_INTF_PHY_PCIE_GEN1);
+
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+
+ status = parse_intf_phy_88xx(adapter, pcie_gen2_phy_param_8822b, pltfm,
+ HAL_INTF_PHY_PCIE_GEN2);
+
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * intf_tun_pcie_8822b() - pcie interface fine tuning
+ * @adapter : the adapter of halmac
+ * Author : Rick Liu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+intf_tun_pcie_8822b(struct halmac_adapter *adapter)
+{
+ return HALMAC_RET_SUCCESS;
+}
+
+#endif /* HALMAC_8822B_SUPPORT*/
diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_pcie_8822b.h b/hal/halmac/halmac_88xx/halmac_8822b/halmac_pcie_8822b.h
new file mode 100644
index 0000000..9a4daa8
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_pcie_8822b.h
@@ -0,0 +1,42 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_API_8822B_PCIE_H_
+#define _HALMAC_API_8822B_PCIE_H_
+
+#include "../../halmac_api.h"
+
+#if HALMAC_8822B_SUPPORT
+
+extern struct halmac_intf_phy_para pcie_gen1_phy_param_8822b[];
+extern struct halmac_intf_phy_para pcie_gen2_phy_param_8822b[];
+
+enum halmac_ret_status
+mac_pwr_switch_pcie_8822b(struct halmac_adapter *adapter,
+ enum halmac_mac_power pwr);
+
+enum halmac_ret_status
+pcie_switch_8822b(struct halmac_adapter *adapter, enum halmac_pcie_cfg cfg);
+
+enum halmac_ret_status
+phy_cfg_pcie_8822b(struct halmac_adapter *adapter,
+ enum halmac_intf_phy_platform pltfm);
+
+enum halmac_ret_status
+intf_tun_pcie_8822b(struct halmac_adapter *adapter);
+
+#endif /* HALMAC_8822B_SUPPORT*/
+
+#endif/* _HALMAC_API_8822B_PCIE_H_ */
diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_phy_8822b.c b/hal/halmac/halmac_88xx/halmac_8822b/halmac_phy_8822b.c
new file mode 100644
index 0000000..03d2e1a
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_phy_8822b.c
@@ -0,0 +1,150 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "../../halmac_type.h"
+
+/**
+ * ============ip sel item list============
+ * HALMAC_IP_INTF_PHY
+ * USB2 : usb2 phy, 1byte value
+ * USB3 : usb3 phy, 2byte value
+ * PCIE1 : pcie gen1 mdio, 2byte value
+ * PCIE2 : pcie gen2 mdio, 2byte value
+ * HALMAC_IP_SEL_MAC
+ * USB2, USB3, PCIE1, PCIE2 : mac ip, 1byte value
+ * HALMAC_IP_PCIE_DBI
+ * USB2 USB3 : none
+ * PCIE1, PCIE2 : pcie dbi, 1byte value
+ */
+
+#if HALMAC_8822B_SUPPORT
+
+struct halmac_intf_phy_para usb2_phy_param_8822b[] = {
+ /* {offset, value, ip sel, cut mask, platform mask} */
+ {0xFFFF, 0x00,
+ HALMAC_IP_INTF_PHY,
+ HALMAC_INTF_PHY_CUT_ALL,
+ HALMAC_INTF_PHY_PLATFORM_ALL},
+};
+
+struct halmac_intf_phy_para usb3_phy_8822b[] = {
+ /* {offset, value, ip sel, cut mask, platform mask} */
+ {0x0001, 0xA841,
+ HALMAC_IP_INTF_PHY,
+ HALMAC_INTF_PHY_CUT_D,
+ HALMAC_INTF_PHY_PLATFORM_ALL},
+ {0xFFFF, 0x0000,
+ HALMAC_IP_INTF_PHY,
+ HALMAC_INTF_PHY_CUT_ALL,
+ HALMAC_INTF_PHY_PLATFORM_ALL},
+};
+
+struct halmac_intf_phy_para pcie_gen1_phy_param_8822b[] = {
+ /* {offset, value, ip sel, cut mask, platform mask} */
+ {0x0001, 0xA841,
+ HALMAC_IP_INTF_PHY,
+ HALMAC_INTF_PHY_CUT_C,
+ HALMAC_INTF_PHY_PLATFORM_ALL},
+ {0x0002, 0x60C6,
+ HALMAC_IP_INTF_PHY,
+ HALMAC_INTF_PHY_CUT_C,
+ HALMAC_INTF_PHY_PLATFORM_ALL},
+ {0x0008, 0x3596,
+ HALMAC_IP_INTF_PHY,
+ HALMAC_INTF_PHY_CUT_C,
+ HALMAC_INTF_PHY_PLATFORM_ALL},
+ {0x0009, 0x321C,
+ HALMAC_IP_INTF_PHY,
+ HALMAC_INTF_PHY_CUT_C,
+ HALMAC_INTF_PHY_PLATFORM_ALL},
+ {0x000A, 0x9623,
+ HALMAC_IP_INTF_PHY,
+ HALMAC_INTF_PHY_CUT_C,
+ HALMAC_INTF_PHY_PLATFORM_ALL},
+ {0x0020, 0x94FF,
+ HALMAC_IP_INTF_PHY,
+ HALMAC_INTF_PHY_CUT_C,
+ HALMAC_INTF_PHY_PLATFORM_ALL},
+ {0x0021, 0xFFCF,
+ HALMAC_IP_INTF_PHY,
+ HALMAC_INTF_PHY_CUT_C,
+ HALMAC_INTF_PHY_PLATFORM_ALL},
+ {0x0026, 0xC006,
+ HALMAC_IP_INTF_PHY,
+ HALMAC_INTF_PHY_CUT_C,
+ HALMAC_INTF_PHY_PLATFORM_ALL},
+ {0x0029, 0xFF0E,
+ HALMAC_IP_INTF_PHY,
+ HALMAC_INTF_PHY_CUT_C,
+ HALMAC_INTF_PHY_PLATFORM_ALL},
+ {0x002A, 0x1840,
+ HALMAC_IP_INTF_PHY,
+ HALMAC_INTF_PHY_CUT_C,
+ HALMAC_INTF_PHY_PLATFORM_ALL},
+ {0xFFFF, 0x0000,
+ HALMAC_IP_INTF_PHY,
+ HALMAC_INTF_PHY_CUT_ALL,
+ HALMAC_INTF_PHY_PLATFORM_ALL},
+};
+
+struct halmac_intf_phy_para pcie_gen2_phy_param_8822b[] = {
+ /* {offset, value, ip sel, cut mask, platform mask} */
+ {0x0001, 0xA841,
+ HALMAC_IP_INTF_PHY,
+ HALMAC_INTF_PHY_CUT_C,
+ HALMAC_INTF_PHY_PLATFORM_ALL},
+ {0x0002, 0x60C6,
+ HALMAC_IP_INTF_PHY,
+ HALMAC_INTF_PHY_CUT_C,
+ HALMAC_INTF_PHY_PLATFORM_ALL},
+ {0x0008, 0x3597,
+ HALMAC_IP_INTF_PHY,
+ HALMAC_INTF_PHY_CUT_C,
+ HALMAC_INTF_PHY_PLATFORM_ALL},
+ {0x0009, 0x321C,
+ HALMAC_IP_INTF_PHY,
+ HALMAC_INTF_PHY_CUT_C,
+ HALMAC_INTF_PHY_PLATFORM_ALL},
+ {0x000A, 0x9623,
+ HALMAC_IP_INTF_PHY,
+ HALMAC_INTF_PHY_CUT_C,
+ HALMAC_INTF_PHY_PLATFORM_ALL},
+ {0x0020, 0x94FF,
+ HALMAC_IP_INTF_PHY,
+ HALMAC_INTF_PHY_CUT_C,
+ HALMAC_INTF_PHY_PLATFORM_ALL},
+ {0x0021, 0xFFCF,
+ HALMAC_IP_INTF_PHY,
+ HALMAC_INTF_PHY_CUT_C,
+ HALMAC_INTF_PHY_PLATFORM_ALL},
+ {0x0026, 0xC006,
+ HALMAC_IP_INTF_PHY,
+ HALMAC_INTF_PHY_CUT_C,
+ HALMAC_INTF_PHY_PLATFORM_ALL},
+ {0x0029, 0xFF0E,
+ HALMAC_IP_INTF_PHY,
+ HALMAC_INTF_PHY_CUT_C,
+ HALMAC_INTF_PHY_PLATFORM_ALL},
+ {0x002A, 0x3040,
+ HALMAC_IP_INTF_PHY,
+ HALMAC_INTF_PHY_CUT_C,
+ HALMAC_INTF_PHY_PLATFORM_ALL},
+ {0xFFFF, 0x0000,
+ HALMAC_IP_INTF_PHY,
+ HALMAC_INTF_PHY_CUT_ALL,
+ HALMAC_INTF_PHY_PLATFORM_ALL},
+};
+
+#endif /* HALMAC_8822B_SUPPORT*/
\ No newline at end of file
diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_pwr_seq_8822b.c b/hal/halmac/halmac_88xx/halmac_8822b/halmac_pwr_seq_8822b.c
new file mode 100644
index 0000000..3ba9f79
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_pwr_seq_8822b.c
@@ -0,0 +1,914 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_pwr_seq_8822b.h"
+
+#if HALMAC_8822B_SUPPORT
+
+struct halmac_wlan_pwr_cfg TRANS_CARDDIS_TO_CARDEMU_8822B[] = {
+ /* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
+ {0x0086,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_SDIO_MSK,
+ HALMAC_PWR_ADDR_SDIO,
+ HALMAC_PWR_CMD_WRITE, BIT(0), 0},
+ {0x0086,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_SDIO_MSK,
+ HALMAC_PWR_ADDR_SDIO,
+ HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1)},
+ {0x004A,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_USB_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(0), 0},
+ {0x0005,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
+ {0x0300,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_PCI_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, 0xFF, 0},
+ {0x0301,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_PCI_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, 0xFF, 0},
+ {0xFFFF,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ 0,
+ HALMAC_PWR_CMD_END, 0, 0},
+};
+
+struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_ACT_8822B[] = {
+ /* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
+ {0x0012,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(1), 0},
+ {0x0012,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+ {0x0020,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+ {0x0001,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_DELAY, 1, HALMAC_PWR_DELAY_MS},
+ {0x0000,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(5), 0},
+ {0x0005,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
+ {0x0075,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_PCI_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+ {0x0006,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1)},
+ {0x0075,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_PCI_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(0), 0},
+ {0xFF1A,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_USB_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, 0xFF, 0},
+ {0x0006,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+ {0x0005,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(7), 0},
+ {0x0005,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
+ {0x10C3,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_USB_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+ {0x0005,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+ {0x0005,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_POLLING, BIT(0), 0},
+ {0x0020,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3)},
+ {0x10A8,
+ HALMAC_PWR_CUT_C_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, 0xFF, 0},
+ {0x10A9,
+ HALMAC_PWR_CUT_C_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, 0xFF, 0xef},
+ {0x10AA,
+ HALMAC_PWR_CUT_C_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, 0xFF, 0x0c},
+ {0x0068,
+ HALMAC_PWR_CUT_C_MSK,
+ HALMAC_PWR_INTF_SDIO_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)},
+ {0x0029,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, 0xFF, 0xF9},
+ {0x0024,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(2), 0},
+ {0x0074,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_PCI_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)},
+ {0x00AF,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)},
+ {0xFFFF,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ 0,
+ HALMAC_PWR_CMD_END, 0, 0},
+};
+
+struct halmac_wlan_pwr_cfg TRANS_ACT_TO_CARDEMU_8822B[] = {
+ /* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
+ {0x0003,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_SDIO_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(2), 0},
+ {0x0093,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(3), 0},
+ {0x001F,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, 0xFF, 0},
+ {0x00EF,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, 0xFF, 0},
+ {0xFF1A,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_USB_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, 0xFF, 0x30},
+ {0x0049,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(1), 0},
+ {0x0006,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+ {0x0002,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(1), 0},
+ {0x10C3,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_USB_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(0), 0},
+ {0x0005,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)},
+ {0x0005,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_POLLING, BIT(1), 0},
+ {0x0020,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(3), 0},
+ {0x0000,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)},
+ {0xFFFF,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ 0,
+ HALMAC_PWR_CMD_END, 0, 0},
+};
+
+struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_CARDDIS_8822B[] = {
+ /* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
+ {0x0005,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_SDIO_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)},
+ {0x0007,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, 0xFF, 0x20},
+ {0x0067,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(5), 0},
+ {0x0005,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
+ {0x0005,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_PCI_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)},
+ {0x004A,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_USB_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(0), 0},
+ {0x0067,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_SDIO_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(5), 0},
+ {0x0067,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_SDIO_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(4), 0},
+ {0x004F,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_SDIO_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(0), 0},
+ {0x0067,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_SDIO_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(1), 0},
+ {0x0046,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_SDIO_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(6), BIT(6)},
+ {0x0067,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_SDIO_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(2), 0},
+ {0x0046,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_SDIO_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)},
+ {0x0062,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_SDIO_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)},
+ {0x0081,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(7), 0},
+ {0x0086,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_SDIO_MSK,
+ HALMAC_PWR_ADDR_SDIO,
+ HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+ {0x0086,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_SDIO_MSK,
+ HALMAC_PWR_ADDR_SDIO,
+ HALMAC_PWR_CMD_POLLING, BIT(1), 0},
+ {0x0090,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_PCI_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(1), 0},
+ {0x0044,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_SDIO_MSK,
+ HALMAC_PWR_ADDR_SDIO,
+ HALMAC_PWR_CMD_WRITE, 0xFF, 0},
+ {0x0040,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_SDIO_MSK,
+ HALMAC_PWR_ADDR_SDIO,
+ HALMAC_PWR_CMD_WRITE, 0xFF, 0x90},
+ {0x0041,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_SDIO_MSK,
+ HALMAC_PWR_ADDR_SDIO,
+ HALMAC_PWR_CMD_WRITE, 0xFF, 0x00},
+ {0x0042,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_SDIO_MSK,
+ HALMAC_PWR_ADDR_SDIO,
+ HALMAC_PWR_CMD_WRITE, 0xFF, 0x04},
+ {0xFFFF,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ 0,
+ HALMAC_PWR_CMD_END, 0, 0},
+};
+
+/* Card Enable Array */
+struct halmac_wlan_pwr_cfg *card_en_flow_8822b[] = {
+ TRANS_CARDDIS_TO_CARDEMU_8822B,
+ TRANS_CARDEMU_TO_ACT_8822B,
+ NULL
+};
+
+/* Card Disable Array */
+struct halmac_wlan_pwr_cfg *card_dis_flow_8822b[] = {
+ TRANS_ACT_TO_CARDEMU_8822B,
+ TRANS_CARDEMU_TO_CARDDIS_8822B,
+ NULL
+};
+
+#if HALMAC_PLATFORM_TESTPROGRAM
+
+struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_SUS_8822B[] = {
+ /* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
+ {0x0005,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_PCI_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3))},
+ {0x0005,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
+ {0x0007,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_SDIO_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, 0xFF, 0x20},
+ {0x0005,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_PCI_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)},
+ {0x0086,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_SDIO_MSK,
+ HALMAC_PWR_ADDR_SDIO,
+ HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+ {0x0086,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_SDIO_MSK,
+ HALMAC_PWR_ADDR_SDIO,
+ HALMAC_PWR_CMD_POLLING, BIT(1), 0},
+ {0xFFFF,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ 0,
+ HALMAC_PWR_CMD_END, 0, 0},
+};
+
+struct halmac_wlan_pwr_cfg TRANS_SUS_TO_CARDEMU_8822B[] = {
+ /* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
+ {0x0005,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(7), 0},
+ {0x0086,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_SDIO_MSK,
+ HALMAC_PWR_ADDR_SDIO,
+ HALMAC_PWR_CMD_WRITE, BIT(0), 0},
+ {0x0086,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_SDIO_MSK,
+ HALMAC_PWR_ADDR_SDIO,
+ HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1)},
+ {0x0005,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), 0},
+ {0xFFFF,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ 0,
+ HALMAC_PWR_CMD_END, 0, 0},
+};
+
+struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_PDN_8822B[] = {
+ /* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
+ {0x0007,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_SDIO_MSK | HALMAC_PWR_INTF_USB_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, 0xFF, 0x20},
+ {0x0006,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(0), 0},
+ {0x0005,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)},
+ {0xFFFF,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ 0,
+ HALMAC_PWR_CMD_END, 0, 0},
+};
+
+struct halmac_wlan_pwr_cfg TRANS_PDN_TO_CARDEMU_8822B[] = {
+ /* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
+ {0x0005,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(7), 0},
+ {0xFFFF,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ 0,
+ HALMAC_PWR_CMD_END, 0, 0},
+};
+
+struct halmac_wlan_pwr_cfg TRANS_ACT_TO_LPS_8822B[] = {
+ /* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
+ {0x0101,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)},
+ {0x0199,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3)},
+ {0x019B,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)},
+ {0x1138,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(0) | BIT(1), BIT(0) | BIT(1)},
+ {0x0194,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+ {0x0093,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, 0xFF, 0x42},
+ {0x0092,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, 0xFF, 0x20},
+ {0x0090,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)},
+ {0x0301,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_PCI_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF},
+ {0x0522,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF},
+ {0x05F8,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_POLLING, 0xFF, 0},
+ {0x05F9,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_POLLING, 0xFF, 0},
+ {0x05FA,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_POLLING, 0xFF, 0},
+ {0x05FB,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_POLLING, 0xFF, 0},
+ {0x0002,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(0), 0},
+ {0x0002,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWR_DELAY_US},
+ {0x0002,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(1), 0},
+ {0x0100,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, 0xFF, 0x3F},
+ {0x0101,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(1), 0},
+ {0x0553,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)},
+ {0x0008,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)},
+ {0x0109,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_POLLING, BIT(7), BIT(7)},
+ {0x0090,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+ {0xFFFF,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ 0,
+ HALMAC_PWR_CMD_END, 0, 0},
+};
+
+struct halmac_wlan_pwr_cfg TRANS_ACT_TO_DEEP_LPS_8822B[] = {
+ /* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
+ {0x0101,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)},
+ {0x0199,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3)},
+ {0x019B,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)},
+ {0x1138,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(0) | BIT(1), BIT(0) | BIT(1)},
+ {0x0194,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+ {0x0093,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, 0xFF, 0x40},
+ {0x0092,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, 0xFF, 0x20},
+ {0x0090,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)},
+ {0x0301,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_PCI_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF},
+ {0x0522,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF},
+ {0x05F8,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_POLLING, 0xFF, 0},
+ {0x05F9,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_POLLING, 0xFF, 0},
+ {0x05FA,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_POLLING, 0xFF, 0},
+ {0x05FB,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_POLLING, 0xFF, 0},
+ {0x0002,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(0), 0},
+ {0x0002,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWR_DELAY_US},
+ {0x0002,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(1), 0},
+ {0x0100,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, 0xFF, 0x3F},
+ {0x0101,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(1), 0},
+ {0x0553,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)},
+ {0x0008,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)},
+ {0x0109,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_POLLING, BIT(7), BIT(7)},
+ {0x0090,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
+ {0xFFFF,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ 0,
+ HALMAC_PWR_CMD_END, 0, 0},
+};
+
+struct halmac_wlan_pwr_cfg TRANS_LPS_TO_ACT_8822B[] = {
+ /* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
+ {0x0080,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_SDIO_MSK,
+ HALMAC_PWR_ADDR_SDIO,
+ HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)},
+ {0x0002,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWR_DELAY_MS},
+ {0x0080,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_SDIO_MSK,
+ HALMAC_PWR_ADDR_SDIO,
+ HALMAC_PWR_CMD_WRITE, BIT(7), 0},
+ {0xFE58,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_USB_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, 0xFF, 0x84},
+ {0xFE58,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_USB_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, 0xFF, 0x04},
+ {0x03D9,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_PCI_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)},
+ {0x0002,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_PCI_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWR_DELAY_MS},
+ {0x03D9,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_PCI_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(7), 0},
+ {0x0002,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWR_DELAY_MS},
+ {0x0008,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(4), 0},
+ {0x0109,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_POLLING, BIT(7), 0},
+ {0x0101,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)},
+ {0x0100,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF},
+ {0x0002,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)},
+ {0x0522,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, 0xFF, 0},
+ {0x113C,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, 0xFF, 0x03},
+ {0x0124,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF},
+ {0x0125,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF},
+ {0x0126,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF},
+ {0x0127,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF},
+ {0x0090,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(1), 0},
+ {0x0101,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ HALMAC_PWR_ADDR_MAC,
+ HALMAC_PWR_CMD_WRITE, BIT(2), 0},
+ {0xFFFF,
+ HALMAC_PWR_CUT_ALL_MSK,
+ HALMAC_PWR_INTF_ALL_MSK,
+ 0,
+ HALMAC_PWR_CMD_END, 0, 0},
+};
+
+/* Suspend Array */
+struct halmac_wlan_pwr_cfg *suspend_flow_8822b[] = {
+ TRANS_ACT_TO_CARDEMU_8822B,
+ TRANS_CARDEMU_TO_SUS_8822B,
+ NULL
+};
+
+/* Resume Array */
+struct halmac_wlan_pwr_cfg *resume_flow_8822b[] = {
+ TRANS_SUS_TO_CARDEMU_8822B,
+ TRANS_CARDEMU_TO_ACT_8822B,
+ NULL
+};
+
+/* HWPDN Array - HW behavior */
+struct halmac_wlan_pwr_cfg *hwpdn_flow_8822b[] = {
+ NULL
+};
+
+/* Enter LPS - FW behavior */
+struct halmac_wlan_pwr_cfg *enter_lps_flow_8822b[] = {
+ TRANS_ACT_TO_LPS_8822B,
+ NULL
+};
+
+/* Enter Deep LPS - FW behavior */
+struct halmac_wlan_pwr_cfg *enter_dlps_flow_8822b[] = {
+ TRANS_ACT_TO_DEEP_LPS_8822B,
+ NULL
+};
+
+/* Leave LPS -FW behavior */
+struct halmac_wlan_pwr_cfg *leave_lps_flow_8822b[] = {
+ TRANS_LPS_TO_ACT_8822B,
+ NULL
+};
+
+#endif
+
+#endif /* HALMAC_8822B_SUPPORT*/
diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_pwr_seq_8822b.h b/hal/halmac/halmac_88xx/halmac_8822b/halmac_pwr_seq_8822b.h
new file mode 100644
index 0000000..5798bda
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_pwr_seq_8822b.h
@@ -0,0 +1,40 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef HALMAC_POWER_SEQUENCE_8822B
+#define HALMAC_POWER_SEQUENCE_8822B
+
+#include "../../halmac_pwr_seq_cmd.h"
+#include "../../halmac_hw_cfg.h"
+
+#if HALMAC_8822B_SUPPORT
+
+#define HALMAC_8822B_PWR_SEQ_VER "V24"
+
+extern struct halmac_wlan_pwr_cfg *card_en_flow_8822b[];
+extern struct halmac_wlan_pwr_cfg *card_dis_flow_8822b[];
+
+#if HALMAC_PLATFORM_TESTPROGRAM
+extern struct halmac_wlan_pwr_cfg *suspend_flow_8822b[];
+extern struct halmac_wlan_pwr_cfg *resume_flow_8822b[];
+extern struct halmac_wlan_pwr_cfg *hwpdn_flow_8822b[];
+extern struct halmac_wlan_pwr_cfg *enter_lps_flow_8822b[];
+extern struct halmac_wlan_pwr_cfg *enter_dlps_flow_8822b[];
+extern struct halmac_wlan_pwr_cfg *leave_lps_flow_8822b[];
+#endif
+
+#endif /* HALMAC_8822B_SUPPORT*/
+
+#endif
diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_sdio_8822b.c b/hal/halmac/halmac_88xx/halmac_8822b/halmac_sdio_8822b.c
new file mode 100644
index 0000000..0a691b6
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_sdio_8822b.c
@@ -0,0 +1,868 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_sdio_8822b.h"
+#include "halmac_pwr_seq_8822b.h"
+#include "../halmac_init_88xx.h"
+#include "../halmac_common_88xx.h"
+#include "../halmac_sdio_88xx.h"
+
+#if HALMAC_8822B_SUPPORT
+
+#define WLAN_ACQ_NUM_MAX 8
+
+static enum halmac_ret_status
+chk_oqt_8822b(struct halmac_adapter *adapter, u32 tx_agg_num, u8 *buf,
+ u8 macid_cnt);
+
+static enum halmac_ret_status
+update_oqt_free_space_8822b(struct halmac_adapter *adapter);
+
+static enum halmac_ret_status
+update_sdio_free_page_8822b(struct halmac_adapter *adapter);
+
+static enum halmac_ret_status
+chk_qsel_8822b(struct halmac_adapter *adapter, u8 qsel_first, u8 *pkt,
+ u8 *macid_cnt);
+
+static enum halmac_ret_status
+chk_dma_mapping_8822b(struct halmac_adapter *adapter, u16 **cur_fs,
+ u8 qsel_first);
+
+static enum halmac_ret_status
+chk_rqd_page_num_8822b(struct halmac_adapter *adapter, u8 *buf, u32 *rqd_pg_num,
+ u16 **cur_fs, u8 *macid_cnt, u32 tx_agg_num);
+
+/**
+ * mac_pwr_switch_sdio_8822b() - switch mac power
+ * @adapter : the adapter of halmac
+ * @pwr : power state
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+mac_pwr_switch_sdio_8822b(struct halmac_adapter *adapter,
+ enum halmac_mac_power pwr)
+{
+ u8 value8;
+ u8 rpwm;
+ u32 imr_backup;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+ PLTFM_MSG_TRACE("[TRACE]8822B pwr seq ver = %s\n",
+ HALMAC_8822B_PWR_SEQ_VER);
+
+ adapter->rpwm = HALMAC_REG_R8(REG_SDIO_HRPWM1);
+
+ /* Check FW still exist or not */
+ if (HALMAC_REG_R16(REG_MCUFW_CTRL) == 0xC078) {
+ /* Leave 32K */
+ rpwm = (u8)((adapter->rpwm ^ BIT(7)) & 0x80);
+ HALMAC_REG_W8(REG_SDIO_HRPWM1, rpwm);
+ }
+
+ value8 = HALMAC_REG_R8(REG_CR);
+ if (value8 == 0xEA)
+ adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_OFF;
+ else
+ adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_ON;
+
+ /*Check if power switch is needed*/
+ if (pwr == HALMAC_MAC_POWER_ON &&
+ adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_ON) {
+ PLTFM_MSG_WARN("[WARN]power state unchange!!\n");
+ return HALMAC_RET_PWR_UNCHANGE;
+ }
+
+ imr_backup = HALMAC_REG_R32(REG_SDIO_HIMR);
+ HALMAC_REG_W32(REG_SDIO_HIMR, 0);
+
+ if (pwr == HALMAC_MAC_POWER_OFF) {
+ adapter->pwr_off_flow_flag = 1;
+ if (pwr_seq_parser_88xx(adapter, card_dis_flow_8822b) !=
+ HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]Handle power off cmd error\n");
+ HALMAC_REG_W32(REG_SDIO_HIMR, imr_backup);
+ return HALMAC_RET_POWER_OFF_FAIL;
+ }
+
+ adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_OFF;
+ adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE;
+ adapter->pwr_off_flow_flag = 0;
+ init_adapter_dynamic_param_88xx(adapter);
+ } else {
+ if (pwr_seq_parser_88xx(adapter, card_en_flow_8822b) !=
+ HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]Handle power on cmd error\n");
+ HALMAC_REG_W32(REG_SDIO_HIMR, imr_backup);
+ return HALMAC_RET_POWER_ON_FAIL;
+ }
+
+ adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_ON;
+ }
+
+ HALMAC_REG_W32(REG_SDIO_HIMR, imr_backup);
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_tx_allowed_sdio_88xx() - check tx status
+ * @adapter : the adapter of halmac
+ * @buf : tx packet, include txdesc
+ * @size : tx packet size, include txdesc
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+tx_allowed_sdio_8822b(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+ u16 *cur_fs = NULL;
+ u32 cnt;
+ u32 tx_agg_num;
+ u32 rqd_pg_num = 0;
+ u8 macid_cnt = 0;
+ struct halmac_sdio_free_space *fs_info = &adapter->sdio_fs;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (!fs_info->macid_map) {
+ PLTFM_MSG_ERR("[ERR]halmac allocate Macid_map Fail!!\n");
+ return HALMAC_RET_MALLOC_FAIL;
+ }
+
+ PLTFM_MEMSET(fs_info->macid_map, 0x00, fs_info->macid_map_size);
+
+ tx_agg_num = GET_TX_DESC_DMA_TXAGG_NUM(buf);
+ tx_agg_num = (tx_agg_num == 0) ? 1 : tx_agg_num;
+
+ status = chk_rqd_page_num_8822b(adapter, buf, &rqd_pg_num, &cur_fs,
+ &macid_cnt, tx_agg_num);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+
+ cnt = 10;
+ do {
+ if ((u32)(*cur_fs + fs_info->pubq_pg_num) > rqd_pg_num) {
+ status = chk_oqt_8822b(adapter, tx_agg_num, buf,
+ macid_cnt);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_WARN("[WARN]oqt buffer full!!\n");
+ return status;
+ }
+
+ if (*cur_fs >= rqd_pg_num) {
+ *cur_fs -= (u16)rqd_pg_num;
+ } else {
+ fs_info->pubq_pg_num -=
+ (u16)(rqd_pg_num - *cur_fs);
+ *cur_fs = 0;
+ }
+
+ break;
+ }
+
+ update_sdio_free_page_8822b(adapter);
+
+ cnt--;
+ if (cnt == 0)
+ return HALMAC_RET_FREE_SPACE_NOT_ENOUGH;
+ } while (1);
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_reg_read_8_sdio_88xx() - read 1byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+u8
+reg_r8_sdio_8822b(struct halmac_adapter *adapter, u32 offset)
+{
+ u8 value8;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ if ((offset & 0xFFFF0000) == 0) {
+ value8 = (u8)r_indir_sdio_88xx(adapter, offset, HALMAC_IO_BYTE);
+ } else {
+ status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]convert offset\n");
+ return status;
+ }
+ value8 = PLTFM_SDIO_CMD52_R(offset);
+ }
+
+ return value8;
+}
+
+/**
+ * halmac_reg_write_8_sdio_88xx() - write 1byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * @value : register value
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+reg_w8_sdio_8822b(struct halmac_adapter *adapter, u32 offset, u8 value)
+{
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ if ((offset & 0xFFFF0000) == 0)
+ offset |= WLAN_IOREG_OFFSET;
+
+ status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
+
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]convert offset\n");
+ return status;
+ }
+
+ PLTFM_SDIO_CMD52_W(offset, value);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_reg_read_16_sdio_88xx() - read 2byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+u16
+reg_r16_sdio_8822b(struct halmac_adapter *adapter, u32 offset)
+{
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+ union {
+ u16 word;
+ u8 byte[2];
+ } value16 = { 0x0000 };
+
+ if ((offset & 0xFFFF0000) == 0)
+ return (u16)r_indir_sdio_88xx(adapter, offset, HALMAC_IO_WORD);
+
+ status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]convert offset\n");
+ return status;
+ }
+
+ if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF ||
+ ((offset & (2 - 1)) != 0) ||
+ adapter->sdio_cmd53_4byte == HALMAC_SDIO_CMD53_4BYTE_MODE_RW ||
+ adapter->sdio_cmd53_4byte == HALMAC_SDIO_CMD53_4BYTE_MODE_R) {
+ value16.byte[0] = PLTFM_SDIO_CMD52_R(offset);
+ value16.byte[1] = PLTFM_SDIO_CMD52_R(offset + 1);
+ value16.word = rtk_le16_to_cpu(value16.word);
+ } else {
+ value16.word = PLTFM_SDIO_CMD53_R16(offset);
+ }
+
+ return value16.word;
+}
+
+/**
+ * halmac_reg_write_16_sdio_88xx() - write 2byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * @value : register value
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+reg_w16_sdio_8822b(struct halmac_adapter *adapter, u32 offset, u16 value)
+{
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF ||
+ ((offset & (2 - 1)) != 0) ||
+ adapter->sdio_cmd53_4byte == HALMAC_SDIO_CMD53_4BYTE_MODE_RW ||
+ adapter->sdio_cmd53_4byte == HALMAC_SDIO_CMD53_4BYTE_MODE_W) {
+ if ((offset & 0xFFFF0000) == 0 && ((offset & (2 - 1)) == 0)) {
+ status = w_indir_sdio_88xx(adapter, offset, value,
+ HALMAC_IO_WORD);
+ } else {
+ if ((offset & 0xFFFF0000) == 0)
+ offset |= WLAN_IOREG_OFFSET;
+
+ status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]convert offset\n");
+ return status;
+ }
+ PLTFM_SDIO_CMD52_W(offset, (u8)(value & 0xFF));
+ PLTFM_SDIO_CMD52_W(offset + 1,
+ (u8)((value & 0xFF00) >> 8));
+ }
+ } else {
+ if ((offset & 0xFFFF0000) == 0)
+ offset |= WLAN_IOREG_OFFSET;
+
+ status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]convert offset\n");
+ return status;
+ }
+
+ PLTFM_SDIO_CMD53_W16(offset, value);
+ }
+ return status;
+}
+
+/**
+ * halmac_reg_read_32_sdio_88xx() - read 4byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+u32
+reg_r32_sdio_8822b(struct halmac_adapter *adapter, u32 offset)
+{
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+ union {
+ u32 dword;
+ u8 byte[4];
+ } value32 = { 0x00000000 };
+
+ if ((offset & 0xFFFF0000) == 0)
+ return r_indir_sdio_88xx(adapter, offset, HALMAC_IO_DWORD);
+
+ status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]convert offset\n");
+ return status;
+ }
+
+ if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF ||
+ (offset & (4 - 1)) != 0) {
+ value32.byte[0] = PLTFM_SDIO_CMD52_R(offset);
+ value32.byte[1] = PLTFM_SDIO_CMD52_R(offset + 1);
+ value32.byte[2] = PLTFM_SDIO_CMD52_R(offset + 2);
+ value32.byte[3] = PLTFM_SDIO_CMD52_R(offset + 3);
+ value32.dword = rtk_le32_to_cpu(value32.dword);
+ } else {
+ value32.dword = PLTFM_SDIO_CMD53_R32(offset);
+ }
+
+ return value32.dword;
+}
+
+/**
+ * halmac_reg_write_32_sdio_88xx() - write 4byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * @value : register value
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+reg_w32_sdio_8822b(struct halmac_adapter *adapter, u32 offset, u32 value)
+{
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF ||
+ (offset & (4 - 1)) != 0) {
+ if ((offset & 0xFFFF0000) == 0 && ((offset & (4 - 1)) == 0)) {
+ status = w_indir_sdio_88xx(adapter, offset, value,
+ HALMAC_IO_DWORD);
+ } else {
+ if ((offset & 0xFFFF0000) == 0)
+ offset |= WLAN_IOREG_OFFSET;
+
+ status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]convert offset\n");
+ return status;
+ }
+ PLTFM_SDIO_CMD52_W(offset, (u8)(value & 0xFF));
+ PLTFM_SDIO_CMD52_W(offset + 1,
+ (u8)((value >> 8) & 0xFF));
+ PLTFM_SDIO_CMD52_W(offset + 2,
+ (u8)((value >> 16) & 0xFF));
+ PLTFM_SDIO_CMD52_W(offset + 3,
+ (u8)((value >> 24) & 0xFF));
+ }
+ } else {
+ if ((offset & 0xFFFF0000) == 0)
+ offset |= WLAN_IOREG_OFFSET;
+
+ status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]convert offset\n");
+ return status;
+ }
+ PLTFM_SDIO_CMD53_W32(offset, value);
+ }
+
+ return status;
+}
+
+static enum halmac_ret_status
+chk_oqt_8822b(struct halmac_adapter *adapter, u32 tx_agg_num, u8 *buf,
+ u8 macid_cnt)
+{
+ u32 cnt = 10;
+ struct halmac_sdio_free_space *fs_info = &adapter->sdio_fs;
+
+ /*S0, S1 are not allowed to use, 0x4E4[0] should be 0. Soar 20160323*/
+ /*no need to check non_ac_oqt_number*/
+ /*HI and MGQ blocked will cause protocal issue before H_OQT being full*/
+ switch ((enum halmac_qsel)GET_TX_DESC_QSEL(buf)) {
+ case HALMAC_QSEL_VO:
+ case HALMAC_QSEL_VO_V2:
+ case HALMAC_QSEL_VI:
+ case HALMAC_QSEL_VI_V2:
+ case HALMAC_QSEL_BE:
+ case HALMAC_QSEL_BE_V2:
+ case HALMAC_QSEL_BK:
+ case HALMAC_QSEL_BK_V2:
+ if (macid_cnt > WLAN_ACQ_NUM_MAX &&
+ tx_agg_num > OQT_ENTRY_AC_8822B) {
+ PLTFM_MSG_WARN("[WARN]txagg num %d > oqt entry\n",
+ tx_agg_num);
+ PLTFM_MSG_WARN("[WARN]macid cnt %d > acq max\n",
+ macid_cnt);
+ }
+
+ cnt = 10;
+ do {
+ if (fs_info->ac_empty >= macid_cnt) {
+ fs_info->ac_empty -= macid_cnt;
+ break;
+ }
+
+ if (fs_info->ac_oqt_num >= tx_agg_num) {
+ fs_info->ac_empty = 0;
+ fs_info->ac_oqt_num -= (u8)tx_agg_num;
+ break;
+ }
+
+ update_oqt_free_space_8822b(adapter);
+
+ cnt--;
+ if (cnt == 0)
+ return HALMAC_RET_OQT_NOT_ENOUGH;
+ } while (1);
+ break;
+ case HALMAC_QSEL_MGNT:
+ case HALMAC_QSEL_HIGH:
+ if (tx_agg_num > OQT_ENTRY_NOAC_8822B)
+ PLTFM_MSG_WARN("[WARN]tx_agg_num %d > oqt entry\n",
+ tx_agg_num, OQT_ENTRY_NOAC_8822B);
+
+ cnt = 10;
+ do {
+ if (fs_info->non_ac_oqt_num >= tx_agg_num) {
+ fs_info->non_ac_oqt_num -= (u8)tx_agg_num;
+ break;
+ }
+
+ update_oqt_free_space_8822b(adapter);
+
+ cnt--;
+ if (cnt == 0)
+ return HALMAC_RET_OQT_NOT_ENOUGH;
+ } while (1);
+ break;
+ default:
+ break;
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+update_oqt_free_space_8822b(struct halmac_adapter *adapter)
+{
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+ struct halmac_sdio_free_space *fs_info = &adapter->sdio_fs;
+ u8 value;
+ u32 oqt_free_page;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ oqt_free_page = HALMAC_REG_R32(REG_SDIO_OQT_FREE_TXPG_V1);
+ fs_info->ac_oqt_num = (u8)BIT_GET_AC_OQT_FREEPG_V1(oqt_free_page);
+ fs_info->non_ac_oqt_num = (u8)BIT_GET_NOAC_OQT_FREEPG_V1(oqt_free_page);
+ fs_info->ac_empty = 0;
+ if (fs_info->ac_oqt_num == OQT_ENTRY_AC_8822B) {
+ value = HALMAC_REG_R8(REG_TXPKT_EMPTY);
+ while (value > 0) {
+ value = value & (value - 1);
+ fs_info->ac_empty++;
+ };
+ } else {
+ PLTFM_MSG_TRACE("[TRACE]free_space->ac_oqt_num %d != %d\n",
+ fs_info->ac_oqt_num, OQT_ENTRY_AC_8822B);
+ }
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+update_sdio_free_page_8822b(struct halmac_adapter *adapter)
+{
+ u32 free_page = 0;
+ u32 free_page2 = 0;
+ u32 free_page3 = 0;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+ struct halmac_sdio_free_space *fs_info = &adapter->sdio_fs;
+ u8 data[12] = {0};
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ HALMAC_REG_SDIO_RN(REG_SDIO_FREE_TXPG, 12, data);
+
+ free_page = rtk_le32_to_cpu(*(u32 *)(data + 0));
+ free_page2 = rtk_le32_to_cpu(*(u32 *)(data + 4));
+ free_page3 = rtk_le32_to_cpu(*(u32 *)(data + 8));
+
+ fs_info->hiq_pg_num = (u16)BIT_GET_HIQ_FREEPG_V1(free_page);
+ fs_info->miq_pg_num = (u16)BIT_GET_MID_FREEPG_V1(free_page);
+ fs_info->lowq_pg_num = (u16)BIT_GET_LOW_FREEPG_V1(free_page2);
+ fs_info->pubq_pg_num = (u16)BIT_GET_PUB_FREEPG_V1(free_page2);
+ fs_info->exq_pg_num = (u16)BIT_GET_EXQ_FREEPG_V1(free_page3);
+ fs_info->ac_oqt_num = (u8)BIT_GET_AC_OQT_FREEPG_V1(free_page3);
+ fs_info->non_ac_oqt_num = (u8)BIT_GET_NOAC_OQT_FREEPG_V1(free_page3);
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * phy_cfg_sdio_8822b() - phy config
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+phy_cfg_sdio_8822b(struct halmac_adapter *adapter,
+ enum halmac_intf_phy_platform pltfm)
+{
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_pcie_switch_8821c() - pcie gen1/gen2 switch
+ * @adapter : the adapter of halmac
+ * @cfg : gen1/gen2 selection
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+pcie_switch_sdio_8822b(struct halmac_adapter *adapter,
+ enum halmac_pcie_cfg cfg)
+{
+ return HALMAC_RET_NOT_SUPPORT;
+}
+
+/**
+ * intf_tun_sdio_8822b() - sdio interface fine tuning
+ * @adapter : the adapter of halmac
+ * Author : Ivan
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+intf_tun_sdio_8822b(struct halmac_adapter *adapter)
+{
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_get_sdio_tx_addr_sdio_88xx() - get CMD53 addr for the TX packet
+ * @adapter : the adapter of halmac
+ * @buf : tx packet, include txdesc
+ * @size : tx packet size
+ * @cmd53_addr : cmd53 addr value
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+get_sdio_tx_addr_8822b(struct halmac_adapter *adapter, u8 *buf, u32 size,
+ u32 *cmd53_addr)
+{
+ u32 len_unit4;
+ enum halmac_qsel queue_sel;
+ enum halmac_dma_mapping dma_mapping;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (!buf) {
+ PLTFM_MSG_ERR("[ERR]buf is NULL!!\n");
+ return HALMAC_RET_DATA_BUF_NULL;
+ }
+
+ if (size == 0) {
+ PLTFM_MSG_ERR("[ERR]size is 0!!\n");
+ return HALMAC_RET_DATA_SIZE_INCORRECT;
+ }
+
+ queue_sel = (enum halmac_qsel)GET_TX_DESC_QSEL(buf);
+
+ switch (queue_sel) {
+ case HALMAC_QSEL_VO:
+ case HALMAC_QSEL_VO_V2:
+ dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_VO];
+ break;
+ case HALMAC_QSEL_VI:
+ case HALMAC_QSEL_VI_V2:
+ dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_VI];
+ break;
+ case HALMAC_QSEL_BE:
+ case HALMAC_QSEL_BE_V2:
+ dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_BE];
+ break;
+ case HALMAC_QSEL_BK:
+ case HALMAC_QSEL_BK_V2:
+ dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_BK];
+ break;
+ case HALMAC_QSEL_MGNT:
+ dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_MG];
+ break;
+ case HALMAC_QSEL_HIGH:
+ case HALMAC_QSEL_BCN:
+ case HALMAC_QSEL_CMD:
+ dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_HI];
+ break;
+ default:
+ PLTFM_MSG_ERR("[ERR]Qsel is out of range\n");
+ return HALMAC_RET_QSEL_INCORRECT;
+ }
+
+ len_unit4 = (size >> 2) + ((size & (4 - 1)) ? 1 : 0);
+
+ switch (dma_mapping) {
+ case HALMAC_DMA_MAPPING_HIGH:
+ *cmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_HIGH;
+ break;
+ case HALMAC_DMA_MAPPING_NORMAL:
+ *cmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_NORMAL;
+ break;
+ case HALMAC_DMA_MAPPING_LOW:
+ *cmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_LOW;
+ break;
+ case HALMAC_DMA_MAPPING_EXTRA:
+ *cmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_EXTRA;
+ break;
+ default:
+ PLTFM_MSG_ERR("[ERR]DmaMapping is out of range\n");
+ return HALMAC_RET_DMA_MAP_INCORRECT;
+ }
+
+ *cmd53_addr = (*cmd53_addr << 13) |
+ (len_unit4 & HALMAC_SDIO_4BYTE_LEN_MASK);
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+chk_qsel_8822b(struct halmac_adapter *adapter, u8 qsel_first, u8 *pkt,
+ u8 *macid_cnt)
+{
+ u8 flag = 0;
+ u8 qsel_now;
+ u8 macid;
+ struct halmac_sdio_free_space *fs_info = &adapter->sdio_fs;
+
+ macid = (u8)GET_TX_DESC_MACID(pkt);
+ qsel_now = (u8)GET_TX_DESC_QSEL(pkt);
+ if (qsel_first == qsel_now) {
+ if (*(fs_info->macid_map + macid) == 0) {
+ *(fs_info->macid_map + macid) = 1;
+ (*macid_cnt)++;
+ }
+ } else {
+ switch ((enum halmac_qsel)qsel_now) {
+ case HALMAC_QSEL_VO:
+ if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_VO_V2)
+ flag = 1;
+ break;
+ case HALMAC_QSEL_VO_V2:
+ if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_VO)
+ flag = 1;
+ break;
+ case HALMAC_QSEL_VI:
+ if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_VI_V2)
+ flag = 1;
+ break;
+ case HALMAC_QSEL_VI_V2:
+ if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_VI)
+ flag = 1;
+ break;
+ case HALMAC_QSEL_BE:
+ if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_BE_V2)
+ flag = 1;
+ break;
+ case HALMAC_QSEL_BE_V2:
+ if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_BE)
+ flag = 1;
+ break;
+ case HALMAC_QSEL_BK:
+ if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_BK_V2)
+ flag = 1;
+ break;
+ case HALMAC_QSEL_BK_V2:
+ if ((enum halmac_qsel)qsel_first != HALMAC_QSEL_BK)
+ flag = 1;
+ break;
+ case HALMAC_QSEL_MGNT:
+ case HALMAC_QSEL_HIGH:
+ case HALMAC_QSEL_BCN:
+ case HALMAC_QSEL_CMD:
+ flag = 1;
+ break;
+ default:
+ PLTFM_MSG_ERR("[ERR]Qsel is out of range\n");
+ return HALMAC_RET_QSEL_INCORRECT;
+ }
+ if (flag == 1) {
+ PLTFM_MSG_ERR("[ERR]Multi-Qsel is not allowed\n");
+ PLTFM_MSG_ERR("[ERR]qsel = %d, %d\n",
+ qsel_first, qsel_now);
+ return HALMAC_RET_QSEL_INCORRECT;
+ }
+ if (*(fs_info->macid_map + macid + MACID_MAX_8822B) == 0) {
+ *(fs_info->macid_map + macid + MACID_MAX_8822B) = 1;
+ (*macid_cnt)++;
+ }
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+chk_dma_mapping_8822b(struct halmac_adapter *adapter, u16 **cur_fs,
+ u8 qsel_first)
+{
+ enum halmac_dma_mapping dma_mapping;
+
+ switch ((enum halmac_qsel)qsel_first) {
+ case HALMAC_QSEL_VO:
+ case HALMAC_QSEL_VO_V2:
+ dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_VO];
+ break;
+ case HALMAC_QSEL_VI:
+ case HALMAC_QSEL_VI_V2:
+ dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_VI];
+ break;
+ case HALMAC_QSEL_BE:
+ case HALMAC_QSEL_BE_V2:
+ dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_BE];
+ break;
+ case HALMAC_QSEL_BK:
+ case HALMAC_QSEL_BK_V2:
+ dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_BK];
+ break;
+ case HALMAC_QSEL_MGNT:
+ dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_MG];
+ break;
+ case HALMAC_QSEL_HIGH:
+ dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_HI];
+ break;
+ case HALMAC_QSEL_BCN:
+ case HALMAC_QSEL_CMD:
+ return HALMAC_RET_SUCCESS;
+ default:
+ PLTFM_MSG_ERR("[ERR]Qsel is out of range: %d\n", qsel_first);
+ return HALMAC_RET_QSEL_INCORRECT;
+ }
+
+ switch (dma_mapping) {
+ case HALMAC_DMA_MAPPING_HIGH:
+ *cur_fs = &adapter->sdio_fs.hiq_pg_num;
+ break;
+ case HALMAC_DMA_MAPPING_NORMAL:
+ *cur_fs = &adapter->sdio_fs.miq_pg_num;
+ break;
+ case HALMAC_DMA_MAPPING_LOW:
+ *cur_fs = &adapter->sdio_fs.lowq_pg_num;
+ break;
+ case HALMAC_DMA_MAPPING_EXTRA:
+ *cur_fs = &adapter->sdio_fs.exq_pg_num;
+ break;
+ default:
+ PLTFM_MSG_ERR("[ERR]DmaMapping is out of range\n");
+ return HALMAC_RET_DMA_MAP_INCORRECT;
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+chk_rqd_page_num_8822b(struct halmac_adapter *adapter, u8 *buf, u32 *rqd_pg_num,
+ u16 **cur_fs, u8 *macid_cnt, u32 tx_agg_num)
+{
+ u8 *pkt;
+ u8 qsel_first;
+ u32 i;
+ u32 pkt_size;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ pkt = buf;
+
+ qsel_first = (u8)GET_TX_DESC_QSEL(pkt);
+
+ status = chk_dma_mapping_8822b(adapter, cur_fs, qsel_first);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+
+ for (i = 0; i < tx_agg_num; i++) {
+ /*QSEL parser*/
+ status = chk_qsel_8822b(adapter, qsel_first, pkt, macid_cnt);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+
+ /*Page number parser*/
+ pkt_size = GET_TX_DESC_TXPKTSIZE(pkt) + GET_TX_DESC_OFFSET(pkt);
+ *rqd_pg_num += (pkt_size >> TX_PAGE_SIZE_SHIFT_88XX) +
+ ((pkt_size & (TX_PAGE_SIZE_88XX - 1)) ? 1 : 0);
+
+ pkt += HALMAC_ALIGN(GET_TX_DESC_TXPKTSIZE(pkt) +
+ (GET_TX_DESC_PKT_OFFSET(pkt) << 3) +
+ TX_DESC_SIZE_88XX, 8);
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+#endif /* HALMAC_8822B_SUPPORT*/
diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_sdio_8822b.h b/hal/halmac/halmac_88xx/halmac_8822b/halmac_sdio_8822b.h
new file mode 100644
index 0000000..486787d
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_sdio_8822b.h
@@ -0,0 +1,66 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_API_8822B_SDIO_H_
+#define _HALMAC_API_8822B_SDIO_H_
+
+#include "../../halmac_api.h"
+#include "halmac_8822b_cfg.h"
+
+#if HALMAC_8822B_SUPPORT
+
+enum halmac_ret_status
+mac_pwr_switch_sdio_8822b(struct halmac_adapter *adapter,
+ enum halmac_mac_power pwr);
+
+enum halmac_ret_status
+tx_allowed_sdio_8822b(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+u8
+reg_r8_sdio_8822b(struct halmac_adapter *adapter, u32 offset);
+
+enum halmac_ret_status
+reg_w8_sdio_8822b(struct halmac_adapter *adapter, u32 offset, u8 value);
+
+u16
+reg_r16_sdio_8822b(struct halmac_adapter *adapter, u32 offset);
+
+enum halmac_ret_status
+reg_w16_sdio_8822b(struct halmac_adapter *adapter, u32 offset, u16 value);
+
+u32
+reg_r32_sdio_8822b(struct halmac_adapter *adapter, u32 offset);
+
+enum halmac_ret_status
+reg_w32_sdio_8822b(struct halmac_adapter *adapter, u32 offset, u32 value);
+
+enum halmac_ret_status
+phy_cfg_sdio_8822b(struct halmac_adapter *adapter,
+ enum halmac_intf_phy_platform pltfm);
+
+enum halmac_ret_status
+pcie_switch_sdio_8822b(struct halmac_adapter *adapter,
+ enum halmac_pcie_cfg cfg);
+
+enum halmac_ret_status
+intf_tun_sdio_8822b(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+get_sdio_tx_addr_8822b(struct halmac_adapter *adapter, u8 *buf, u32 size,
+ u32 *cmd53_addr);
+
+#endif /* HALMAC_8822B_SUPPORT*/
+
+#endif/* _HALMAC_API_8822B_SDIO_H_ */
diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_usb_8822b.c b/hal/halmac/halmac_88xx/halmac_8822b/halmac_usb_8822b.c
new file mode 100644
index 0000000..6d0e2be
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_usb_8822b.c
@@ -0,0 +1,159 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_usb_8822b.h"
+#include "halmac_pwr_seq_8822b.h"
+#include "../halmac_init_88xx.h"
+#include "../halmac_common_88xx.h"
+
+#if HALMAC_8822B_SUPPORT
+
+/**
+ * mac_pwr_switch_usb_8822b() - switch mac power
+ * @adapter : the adapter of halmac
+ * @pwr : power state
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+mac_pwr_switch_usb_8822b(struct halmac_adapter *adapter,
+ enum halmac_mac_power pwr)
+{
+ u8 value8;
+ u8 rpwm;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ PLTFM_MSG_TRACE("[TRACE]%s\n", __func__);
+ PLTFM_MSG_TRACE("[TRACE]%x\n", pwr);
+ PLTFM_MSG_TRACE("[TRACE]8821C pwr seq ver = %s\n",
+ HALMAC_8822B_PWR_SEQ_VER);
+
+ adapter->rpwm = HALMAC_REG_R8(0xFE58);
+
+ /* Check FW still exist or not */
+ if (HALMAC_REG_R16(REG_MCUFW_CTRL) == 0xC078) {
+ /* Leave 32K */
+ rpwm = (u8)((adapter->rpwm ^ BIT(7)) & 0x80);
+ HALMAC_REG_W8(0xFE58, rpwm);
+ }
+
+ value8 = HALMAC_REG_R8(REG_CR);
+ if (value8 == 0xEA) {
+ adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_OFF;
+ } else {
+ if (BIT(0) == (HALMAC_REG_R8(REG_SYS_STATUS1 + 1) & BIT(0)))
+ adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_OFF;
+ else
+ adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_ON;
+ }
+
+ /*Check if power switch is needed*/
+ if (pwr == HALMAC_MAC_POWER_ON &&
+ adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_ON) {
+ PLTFM_MSG_WARN("[WARN]power state unchange!!\n");
+ return HALMAC_RET_PWR_UNCHANGE;
+ }
+
+ if (pwr == HALMAC_MAC_POWER_OFF) {
+ if (pwr_seq_parser_88xx(adapter, card_dis_flow_8822b) !=
+ HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]Handle power off cmd error\n");
+ return HALMAC_RET_POWER_OFF_FAIL;
+ }
+
+ adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_OFF;
+ adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE;
+ init_adapter_dynamic_param_88xx(adapter);
+ } else {
+ if (pwr_seq_parser_88xx(adapter, card_en_flow_8822b) !=
+ HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]Handle power on cmd error\n");
+ return HALMAC_RET_POWER_ON_FAIL;
+ }
+
+ HALMAC_REG_W8_CLR(REG_SYS_STATUS1 + 1, BIT(0));
+
+ if ((HALMAC_REG_R8(REG_SW_MDIO + 3) & BIT(0)) == BIT(0))
+ PLTFM_MSG_ALWAYS("[ALWAYS]shall R reg twice!!\n");
+
+ adapter->halmac_state.mac_pwr = HALMAC_MAC_POWER_ON;
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * phy_cfg_usb_8822b() - phy config
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+phy_cfg_usb_8822b(struct halmac_adapter *adapter,
+ enum halmac_intf_phy_platform pltfm)
+{
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ status = parse_intf_phy_88xx(adapter, usb2_phy_param_8822b, pltfm,
+ HAL_INTF_PHY_USB2);
+
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+
+ status = parse_intf_phy_88xx(adapter, usb3_phy_8822b, pltfm,
+ HAL_INTF_PHY_USB3);
+
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_pcie_switch_8822b() - pcie gen1/gen2 switch
+ * @adapter : the adapter of halmac
+ * @cfg : gen1/gen2 selection
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+pcie_switch_usb_8822b(struct halmac_adapter *adapter, enum halmac_pcie_cfg cfg)
+{
+ return HALMAC_RET_NOT_SUPPORT;
+}
+
+/**
+ * intf_tun_usb_8822b() - usb interface fine tuning
+ * @adapter : the adapter of halmac
+ * Author : Ivan
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+intf_tun_usb_8822b(struct halmac_adapter *adapter)
+{
+ return HALMAC_RET_SUCCESS;
+}
+
+#endif /* HALMAC_8822B_SUPPORT*/
\ No newline at end of file
diff --git a/hal/halmac/halmac_88xx/halmac_8822b/halmac_usb_8822b.h b/hal/halmac/halmac_88xx/halmac_8822b/halmac_usb_8822b.h
new file mode 100644
index 0000000..b55c75d
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_8822b/halmac_usb_8822b.h
@@ -0,0 +1,42 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_API_8822B_USB_H_
+#define _HALMAC_API_8822B_USB_H_
+
+#include "../../halmac_api.h"
+
+#if HALMAC_8822B_SUPPORT
+
+extern struct halmac_intf_phy_para usb2_phy_param_8822b[];
+extern struct halmac_intf_phy_para usb3_phy_8822b[];
+
+enum halmac_ret_status
+mac_pwr_switch_usb_8822b(struct halmac_adapter *adapter,
+ enum halmac_mac_power pwr);
+
+enum halmac_ret_status
+phy_cfg_usb_8822b(struct halmac_adapter *adapter,
+ enum halmac_intf_phy_platform pltfm);
+
+enum halmac_ret_status
+pcie_switch_usb_8822b(struct halmac_adapter *adapter, enum halmac_pcie_cfg cfg);
+
+enum halmac_ret_status
+intf_tun_usb_8822b(struct halmac_adapter *adapter);
+
+#endif /* HALMAC_8822B_SUPPORT*/
+
+#endif/* _HALMAC_API_8822B_USB_H_ */
diff --git a/hal/halmac/halmac_88xx/halmac_88xx_cfg.h b/hal/halmac/halmac_88xx/halmac_88xx_cfg.h
index fc53ff1..bad894c 100644
--- a/hal/halmac/halmac_88xx/halmac_88xx_cfg.h
+++ b/hal/halmac/halmac_88xx/halmac_88xx_cfg.h
@@ -1,148 +1,44 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
#ifndef _HALMAC_88XX_CFG_H_
#define _HALMAC_88XX_CFG_H_
-#include "../halmac_2_platform.h"
-#include "../halmac_type.h"
-#include "../halmac_hw_cfg.h"
#include "../halmac_api.h"
-#include "../halmac_bit2.h"
-#include "../halmac_reg2.h"
-#include "../halmac_pwr_seq_cmd.h"
-#include "halmac_func_88xx.h"
-#include "halmac_api_88xx.h"
-#include "halmac_api_88xx_usb.h"
-#include "halmac_api_88xx_pcie.h"
-#include "halmac_api_88xx_sdio.h"
-#if HALMAC_PLATFORM_TESTPROGRAM
-#include "halmisc_api_88xx.h"
-#include "halmisc_api_88xx_usb.h"
-#include "halmisc_api_88xx_pcie.h"
-#include "halmisc_api_88xx_sdio.h"
-#endif
-
-#define HALMAC_SVN_VER_88XX "11974M"
-
-/* major version, ver_1 for async_api */
-#define HALMAC_MAJOR_VER_88XX 0x0001
-/* For halmac_api num change or prototype change, increment prototype version */
-#define HALMAC_PROTOTYPE_VER_88XX 0x0002
-/* else increment minor version */
-#define HALMAC_MINOR_VER_88XX 0x0000
-
-
-
-#define HALMAC_C2H_DATA_OFFSET_88XX 10
-#define HALMAC_RX_AGG_ALIGNMENT_SIZE_88XX 8
-#define HALMAC_TX_AGG_ALIGNMENT_SIZE_88XX 8
-#define HALMAC_TX_AGG_BUFF_SIZE_88XX 32768
-#define HALMAC_EXTRA_INFO_BUFF_SIZE_88XX 4096 /*4K*/
-#define HALMAC_EXTRA_INFO_BUFF_SIZE_FULL_FIFO_88XX 16384 /*16K*/
-#define HALMAC_FW_OFFLOAD_CMD_SIZE_88XX 12 /*Fw config parameter cmd size, each 12 byte*/
+#if HALMAC_88XX_SUPPORT
-#define HALMAC_H2C_CMD_ORIGINAL_SIZE_88XX 8
-#define HALMAC_H2C_CMD_SIZE_UNIT_88XX 32 /* Only support 32 byte packet now */
+#define TX_PAGE_SIZE_88XX 128
+#define TX_PAGE_SIZE_SHIFT_88XX 7 /* 128 = 2^7 */
+#define TX_ALIGN_SIZE_88XX 8
+#define SDIO_TX_MAX_SIZE_88XX 31744
+#define RX_BUF_FW_88XX 12288
-#define HALMAC_NLO_INFO_SIZE_88XX 1024
+#define TX_DESC_SIZE_88XX 48
+#define RX_DESC_SIZE_88XX 24
-/* Download FW */
-#define HALMAC_FW_SIZE_MAX_88XX 0x40000
-#define HALMAC_FWHDR_SIZE_88XX 64
-#define HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX 8
-#define HALMAC_FW_MAX_DL_SIZE_88XX 0x2000 /* need power of 2 */
-/* Max dlfw size can not over 31K, because SDIO HW restriction */
-#define HALMAC_FW_CFG_MAX_DL_SIZE_MAX_88XX 0x7C00
-
-#define DLFW_RESTORE_REG_NUM_88XX 9
-
-/* FW header information */
-#define HALMAC_FWHDR_OFFSET_VERSION_88XX 4
-#define HALMAC_FWHDR_OFFSET_SUBVERSION_88XX 6
-#define HALMAC_FWHDR_OFFSET_SUBINDEX_88XX 7
-#define HALMAC_FWHDR_OFFSET_MEM_USAGE_88XX 24
-#define HALMAC_FWHDR_OFFSET_H2C_FORMAT_VER_88XX 28
-#define HALMAC_FWHDR_OFFSET_DMEM_ADDR_88XX 32
-#define HALMAC_FWHDR_OFFSET_DMEM_SIZE_88XX 36
-#define HALMAC_FWHDR_OFFSET_IRAM_SIZE_88XX 48
-#define HALMAC_FWHDR_OFFSET_ERAM_SIZE_88XX 52
-#define HALMAC_FWHDR_OFFSET_EMEM_ADDR_88XX 56
-#define HALMAC_FWHDR_OFFSET_IRAM_ADDR_88XX 60
+#define H2C_PKT_SIZE_88XX 32 /* Only support 32 byte packet now */
+#define H2C_PKT_HDR_SIZE_88XX 8
+#define C2H_DATA_OFFSET_88XX 10
+#define C2H_PKT_BUF_88XX 256
/* HW memory address */
-#define HALMAC_OCPBASE_TXBUF_88XX 0x18780000
-#define HALMAC_OCPBASE_DMEM_88XX 0x00200000
-#define HALMAC_OCPBASE_IMEM_88XX 0x00000000
-
-/* define the SDIO Bus CLK threshold, for avoiding CMD53 fails that result from SDIO CLK sync to ana_clk fail */
-#define HALMAC_SD_CLK_THRESHOLD_88XX 150000000 /* 150MHz */
-
-/* MAC clock */
-#define HALMAC_MAC_CLOCK_88XX 80 /* 80M */
-
-/* H2C/C2H*/
-#define HALMAC_H2C_CMD_SIZE_88XX 32
-#define HALMAC_H2C_CMD_HDR_SIZE_88XX 8
-
-#define HALMAC_RESERVED_EFUSE_SIZE_88XX 0x30
-
-/* Function enable */
-#define HALMAC_FUNCTION_ENABLE_88XX 0xDC
-
-/* FIFO size & packet size */
-/* #define HALMAC_WOWLAN_PATTERN_SIZE 256 */
-
-/* CFEND rate */
-#define HALMAC_BASIC_CFEND_RATE_88XX 0x5
-#define HALMAC_STBC_CFEND_RATE_88XX 0xF
-
-/* Response rate */
-#define HALMAC_RESPONSE_RATE_BITMAP_ALL_88XX 0xFFFFF
-#define HALMAC_RESPONSE_RATE_88XX HALMAC_RESPONSE_RATE_BITMAP_ALL_88XX
-
-/* Spec SIFS */
-#define HALMAC_SIFS_CCK_PTCL_88XX 16
-#define HALMAC_SIFS_OFDM_PTCL_88XX 16
-
-/* Retry limit */
-#define HALMAC_LONG_RETRY_LIMIT_88XX 8
-#define HALMAC_SHORT_RETRY_LIMIT_88XX 7
-
-/* Slot, SIFS, PIFS time */
-#define HALMAC_SLOT_TIME_88XX 0x05
-#define HALMAC_PIFS_TIME_88XX 0x19
-#define HALMAC_SIFS_CCK_CTX_88XX 0xA
-#define HALMAC_SIFS_OFDM_CTX_88XX 0xA
-#define HALMAC_SIFS_CCK_TRX_88XX 0x10
-#define HALMAC_SIFS_OFDM_TRX_88XX 0x10
-
-/* TXOP limit */
-#define HALMAC_VO_TXOP_LIMIT_88XX 0x186
-#define HALMAC_VI_TXOP_LIMIT_88XX 0x3BC
-
-/* NAV */
-#define HALMAC_RDG_NAV_88XX 0x05
-#define HALMAC_TXOP_NAV_88XX 0x1B
-
-/* TSF */
-#define HALMAC_CCK_RX_TSF_88XX 0x30
-#define HALMAC_OFDM_RX_TSF_88XX 0x30
-
-/* Send beacon related */
-#define HALMAC_TBTT_PROHIBIT_88XX 0x04
-#define HALMAC_TBTT_HOLD_TIME_88XX 0x064
-#define HALMAC_DRIVER_EARLY_INT_88XX 0x04
-#define HALMAC_BEACON_DMA_TIM_88XX 0x02
-
-/* RX filter */
-#define HALMAC_RX_FILTER0_RECIVE_ALL_88XX 0xFFFFFFF
-#define HALMAC_RX_FILTER0_88XX HALMAC_RX_FILTER0_RECIVE_ALL_88XX
-#define HALMAC_RX_FILTER_RECIVE_ALL_88XX 0xFFFF
-#define HALMAC_RX_FILTER_88XX HALMAC_RX_FILTER_RECIVE_ALL_88XX
-
-/* RCR */
-#define HALMAC_RCR_CONFIG_88XX 0xE400631E
+#define OCPBASE_TXBUF_88XX 0x18780000
+#define OCPBASE_DMEM_88XX 0x00200000
+#define OCPBASE_EMEM_88XX 0x00100000
-/* Security config */
-#define HALMAC_SECURITY_CONFIG_88XX 0x01CC
+#endif /* HALMAC_88XX_SUPPORT */
#endif
diff --git a/hal/halmac/halmac_88xx/halmac_api_88xx.c b/hal/halmac/halmac_88xx/halmac_api_88xx.c
deleted file mode 100644
index 75b1fc8..0000000
--- a/hal/halmac/halmac_88xx/halmac_api_88xx.c
+++ /dev/null
@@ -1,5107 +0,0 @@
-#include "halmac_88xx_cfg.h"
-
-/**
- * halmac_init_adapter_para_88xx() - int halmac adapter
- * @pHalmac_adapter
- *
- * SD1 internal use
- *
- * Author : KaiYuan Chang/Ivan Lin
- * Return : VOID
- */
-VOID
-halmac_init_adapter_para_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-)
-{
- pHalmac_adapter->api_record.array_wptr = 0;
- pHalmac_adapter->pHalAdapter_backup = pHalmac_adapter;
- pHalmac_adapter->h2c_packet_seq = 0;
- pHalmac_adapter->pHalEfuse_map = (u8 *)NULL;
- pHalmac_adapter->hal_efuse_map_valid = _FALSE;
- pHalmac_adapter->efuse_end = 0;
- pHalmac_adapter->pHal_mac_addr[0].Address_L_H.Address_Low = 0;
- pHalmac_adapter->pHal_mac_addr[0].Address_L_H.Address_High = 0;
- pHalmac_adapter->pHal_mac_addr[1].Address_L_H.Address_Low = 0;
- pHalmac_adapter->pHal_mac_addr[1].Address_L_H.Address_High = 0;
- pHalmac_adapter->pHal_bss_addr[0].Address_L_H.Address_Low = 0;
- pHalmac_adapter->pHal_bss_addr[0].Address_L_H.Address_High = 0;
- pHalmac_adapter->pHal_bss_addr[1].Address_L_H.Address_Low = 0;
- pHalmac_adapter->pHal_bss_addr[1].Address_L_H.Address_High = 0;
-
-
- pHalmac_adapter->low_clk = _FALSE;
- pHalmac_adapter->h2c_buf_free_space = 0;
- pHalmac_adapter->max_download_size = HALMAC_FW_MAX_DL_SIZE_88XX;
-
- /* Init LPS Option */
- pHalmac_adapter->fwlps_option.mode = 0x01; /*0:Active 1:LPS 2:WMMPS*/
- pHalmac_adapter->fwlps_option.awake_interval = 1;
- pHalmac_adapter->fwlps_option.enter_32K = 1;
- pHalmac_adapter->fwlps_option.clk_request = 0;
- pHalmac_adapter->fwlps_option.rlbm = 0;
- pHalmac_adapter->fwlps_option.smart_ps = 0;
- pHalmac_adapter->fwlps_option.awake_interval = 1;
- pHalmac_adapter->fwlps_option.all_queue_uapsd = 0;
- pHalmac_adapter->fwlps_option.pwr_state = 0;
- pHalmac_adapter->fwlps_option.low_pwr_rx_beacon = 0;
- pHalmac_adapter->fwlps_option.ant_auto_switch = 0;
- pHalmac_adapter->fwlps_option.ps_allow_bt_high_Priority = 0;
- pHalmac_adapter->fwlps_option.protect_bcn = 0;
- pHalmac_adapter->fwlps_option.silence_period = 0;
- pHalmac_adapter->fwlps_option.fast_bt_connect = 0;
- pHalmac_adapter->fwlps_option.two_antenna_en = 0;
- pHalmac_adapter->fwlps_option.adopt_user_Setting = 1;
- pHalmac_adapter->fwlps_option.drv_bcn_early_shift = 0;
-
- pHalmac_adapter->config_para_info.pCfg_para_buf = NULL;
- pHalmac_adapter->config_para_info.pPara_buf_w = NULL;
- pHalmac_adapter->config_para_info.para_num = 0;
- pHalmac_adapter->config_para_info.full_fifo_mode = _FALSE;
- pHalmac_adapter->config_para_info.para_buf_size = 0;
- pHalmac_adapter->config_para_info.avai_para_buf_size = 0;
- pHalmac_adapter->config_para_info.offset_accumulation = 0;
- pHalmac_adapter->config_para_info.value_accumulation = 0;
- pHalmac_adapter->config_para_info.datapack_segment = 0;
-
- pHalmac_adapter->ch_sw_info.ch_info_buf = NULL;
- pHalmac_adapter->ch_sw_info.ch_info_buf_w = NULL;
- pHalmac_adapter->ch_sw_info.extra_info_en = 0;
- pHalmac_adapter->ch_sw_info.buf_size = 0;
- pHalmac_adapter->ch_sw_info.avai_buf_size = 0;
- pHalmac_adapter->ch_sw_info.total_size = 0;
- pHalmac_adapter->ch_sw_info.ch_num = 0;
-
- pHalmac_adapter->gen_info_valid = _FALSE;
-
- PLATFORM_RTL_MEMSET(pHalmac_adapter->pDriver_adapter, pHalmac_adapter->api_record.api_array, HALMAC_API_STUFF, sizeof(pHalmac_adapter->api_record.api_array));
-
- halmac_init_state_machine_88xx(pHalmac_adapter);
-
-}
-
-/**
- * halmac_init_state_machine_88xx() - init halmac software state machine
- * @pHalmac_adapter
- *
- * SD1 internal use.
- *
- * Author : KaiYuan Chang/Ivan Lin
- * Return : VOID
- */
-VOID
-halmac_init_state_machine_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-)
-{
- PHALMAC_STATE pState = &(pHalmac_adapter->halmac_state);
-
- pState->efuse_state_set.efuse_cmd_construct_state = HALMAC_EFUSE_CMD_CONSTRUCT_IDLE;
- pState->efuse_state_set.process_status = HALMAC_CMD_PROCESS_IDLE;
- pState->efuse_state_set.seq_num = pHalmac_adapter->h2c_packet_seq;
-
- pState->cfg_para_state_set.cfg_para_cmd_construct_state = HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE;
- pState->cfg_para_state_set.process_status = HALMAC_CMD_PROCESS_IDLE;
- pState->cfg_para_state_set.seq_num = pHalmac_adapter->h2c_packet_seq;
-
- pState->scan_state_set.scan_cmd_construct_state = HALMAC_SCAN_CMD_CONSTRUCT_IDLE;
- pState->scan_state_set.process_status = HALMAC_CMD_PROCESS_IDLE;
- pState->scan_state_set.seq_num = pHalmac_adapter->h2c_packet_seq;
-
- pState->update_packet_set.process_status = HALMAC_CMD_PROCESS_IDLE;
- pState->update_packet_set.seq_num = pHalmac_adapter->h2c_packet_seq;
-
- pState->iqk_set.process_status = HALMAC_CMD_PROCESS_IDLE;
- pState->iqk_set.seq_num = pHalmac_adapter->h2c_packet_seq;
-
- pState->power_tracking_set.process_status = HALMAC_CMD_PROCESS_IDLE;
- pState->power_tracking_set.seq_num = pHalmac_adapter->h2c_packet_seq;
-
- pState->psd_set.process_status = HALMAC_CMD_PROCESS_IDLE;
- pState->psd_set.seq_num = pHalmac_adapter->h2c_packet_seq;
- pState->psd_set.data_size = 0;
- pState->psd_set.segment_size = 0;
- pState->psd_set.pData = NULL;
-
- pState->api_state = HALMAC_API_STATE_INIT;
-
- pState->dlfw_state = HALMAC_DLFW_NONE;
- pState->mac_power = HALMAC_MAC_POWER_OFF;
- pState->ps_state = HALMAC_PS_STATE_UNDEFINE;
-}
-
-/**
- * halmac_mount_api_88xx() - attach functions to function pointer
- * @pHalmac_adapter
- *
- * SD1 internal use
- *
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_mount_api_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-)
-{
- VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- PHALMAC_API pHalmac_api = (PHALMAC_API)NULL;
- u8 chip_id, chip_version;
- u32 polling_count;
-
- pHalmac_adapter->pHalmac_api = (PHALMAC_API)PLATFORM_RTL_MALLOC(pDriver_adapter, sizeof(HALMAC_API));
- if (NULL == pHalmac_adapter->pHalmac_api)
- return HALMAC_RET_MALLOC_FAIL;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, HALMAC_SVN_VER_88XX"\n");
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "HALMAC_MAJOR_VER_88XX = %x\n", HALMAC_MAJOR_VER_88XX);
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "HALMAC_PROTOTYPE_88XX = %x\n", HALMAC_PROTOTYPE_VER_88XX);
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "HALMAC_MINOR_VER_88XX = %x\n", HALMAC_MINOR_VER_88XX);
-
-
- /* Mount function pointer */
- pHalmac_api->halmac_download_firmware = halmac_download_firmware_88xx;
- pHalmac_api->halmac_get_fw_version = halmac_get_fw_version_88xx;
- pHalmac_api->halmac_cfg_mac_addr = halmac_cfg_mac_addr_88xx;
- pHalmac_api->halmac_cfg_bssid = halmac_cfg_bssid_88xx;
- pHalmac_api->halmac_cfg_multicast_addr = halmac_cfg_multicast_addr_88xx;
- pHalmac_api->halmac_pre_init_system_cfg = halmac_pre_init_system_cfg_88xx;
- pHalmac_api->halmac_init_system_cfg = halmac_init_system_cfg_88xx;
- pHalmac_api->halmac_init_protocol_cfg = halmac_init_protocol_cfg_88xx;
- pHalmac_api->halmac_init_edca_cfg = halmac_init_edca_cfg_88xx;
- pHalmac_api->halmac_cfg_operation_mode = halmac_cfg_operation_mode_88xx;
- pHalmac_api->halmac_cfg_ch_bw = halmac_cfg_ch_bw_88xx;
- pHalmac_api->halmac_cfg_bw = halmac_cfg_bw_88xx;
- pHalmac_api->halmac_init_wmac_cfg = halmac_init_wmac_cfg_88xx;
- pHalmac_api->halmac_init_mac_cfg = halmac_init_mac_cfg_88xx;
- pHalmac_api->halmac_init_sdio_cfg = halmac_init_sdio_cfg_88xx;
- pHalmac_api->halmac_init_usb_cfg = halmac_init_usb_cfg_88xx;
- pHalmac_api->halmac_init_pcie_cfg = halmac_init_pcie_cfg_88xx;
- pHalmac_api->halmac_deinit_sdio_cfg = halmac_deinit_sdio_cfg_88xx;
- pHalmac_api->halmac_deinit_usb_cfg = halmac_deinit_usb_cfg_88xx;
- pHalmac_api->halmac_deinit_pcie_cfg = halmac_deinit_pcie_cfg_88xx;
- pHalmac_api->halmac_dump_efuse_map = halmac_dump_efuse_map_88xx;
- pHalmac_api->halmac_dump_efuse_map_bt = halmac_dump_efuse_map_bt_88xx;
- pHalmac_api->halmac_write_efuse_bt = halmac_write_efuse_bt_88xx;
- pHalmac_api->halmac_dump_logical_efuse_map = halmac_dump_logical_efuse_map_88xx;
- /* pHalmac_api->halmac_write_efuse = halmac_write_efuse_88xx; */
- pHalmac_api->halmac_pg_efuse_by_map = halmac_pg_efuse_by_map_88xx;
- pHalmac_api->halmac_get_efuse_size = halmac_get_efuse_size_88xx;
- pHalmac_api->halmac_get_c2h_info = halmac_get_c2h_info_88xx;
- /* pHalmac_api->halmac_read_efuse = halmac_read_efuse_88xx; */
-
- pHalmac_api->halmac_get_logical_efuse_size = halmac_get_logical_efuse_size_88xx;
-
- pHalmac_api->halmac_write_logical_efuse = halmac_write_logical_efuse_88xx;
- pHalmac_api->halmac_read_logical_efuse = halmac_read_logical_efuse_88xx;
-
- pHalmac_api->halmac_cfg_fwlps_option = halmac_cfg_fwlps_option_88xx;
- pHalmac_api->halmac_cfg_fwips_option = halmac_cfg_fwips_option_88xx;
- pHalmac_api->halmac_enter_wowlan = halmac_enter_wowlan_88xx;
- pHalmac_api->halmac_leave_wowlan = halmac_leave_wowlan_88xx;
- pHalmac_api->halmac_enter_ps = halmac_enter_ps_88xx;
- pHalmac_api->halmac_leave_ps = halmac_leave_ps_88xx;
- pHalmac_api->halmac_h2c_lb = halmac_h2c_lb_88xx;
- pHalmac_api->halmac_debug = halmac_debug_88xx;
- pHalmac_api->halmac_cfg_parameter = halmac_cfg_parameter_88xx;
- pHalmac_api->halmac_update_datapack = halmac_update_datapack_88xx;
- pHalmac_api->halmac_run_datapack = halmac_run_datapack_88xx;
- pHalmac_api->halmac_cfg_drv_info = halmac_cfg_drv_info_88xx;
- pHalmac_api->halmac_send_bt_coex = halmac_send_bt_coex_88xx;
- pHalmac_api->halmac_verify_platform_api = halmac_verify_platform_api_88xx;
- pHalmac_api->halmac_update_packet = halmac_update_packet_88xx;
- pHalmac_api->halmac_bcn_ie_filter = halmac_bcn_ie_filter_88xx;
- pHalmac_api->halmac_cfg_txbf = halmac_cfg_txbf_88xx;
- pHalmac_api->halmac_cfg_mumimo = halmac_cfg_mumimo_88xx;
- pHalmac_api->halmac_cfg_sounding = halmac_cfg_sounding_88xx;
- pHalmac_api->halmac_del_sounding = halmac_del_sounding_88xx;
- pHalmac_api->halmac_su_bfer_entry_init = halmac_su_bfer_entry_init_88xx;
- pHalmac_api->halmac_su_bfee_entry_init = halmac_su_bfee_entry_init_88xx;
- pHalmac_api->halmac_mu_bfer_entry_init = halmac_mu_bfer_entry_init_88xx;
- pHalmac_api->halmac_mu_bfee_entry_init = halmac_mu_bfee_entry_init_88xx;
- pHalmac_api->halmac_su_bfer_entry_del = halmac_su_bfer_entry_del_88xx;
- pHalmac_api->halmac_su_bfee_entry_del = halmac_su_bfee_entry_del_88xx;
- pHalmac_api->halmac_mu_bfer_entry_del = halmac_mu_bfer_entry_del_88xx;
- pHalmac_api->halmac_mu_bfee_entry_del = halmac_mu_bfee_entry_del_88xx;
-
- pHalmac_api->halmac_add_ch_info = halmac_add_ch_info_88xx;
- pHalmac_api->halmac_add_extra_ch_info = halmac_add_extra_ch_info_88xx;
- pHalmac_api->halmac_ctrl_ch_switch = halmac_ctrl_ch_switch_88xx;
- pHalmac_api->halmac_clear_ch_info = halmac_clear_ch_info_88xx;
- pHalmac_api->halmac_send_general_info = halmac_send_general_info_88xx;
-
- pHalmac_api->halmac_start_iqk = halmac_start_iqk_88xx;
- pHalmac_api->halmac_ctrl_pwr_tracking = halmac_ctrl_pwr_tracking_88xx;
- pHalmac_api->halmac_psd = halmac_psd_88xx;
- pHalmac_api->halmac_cfg_la_mode = halmac_cfg_la_mode_88xx;
-
- pHalmac_api->halmac_get_hw_value = halmac_get_hw_value_88xx;
- pHalmac_api->halmac_set_hw_value = halmac_set_hw_value_88xx;
-
- pHalmac_api->halmac_cfg_drv_rsvd_pg_num = halmac_cfg_drv_rsvd_pg_num_88xx;
- pHalmac_api->halmac_get_chip_version = halmac_get_chip_version_88xx;
-
- pHalmac_api->halmac_query_status = halmac_query_status_88xx;
- pHalmac_api->halmac_reset_feature = halmac_reset_feature_88xx;
- pHalmac_api->halmac_check_fw_status = halmac_check_fw_status_88xx;
- pHalmac_api->halmac_dump_fw_dmem = halmac_dump_fw_dmem_88xx;
- pHalmac_api->halmac_cfg_max_dl_size = halmac_cfg_max_dl_size_88xx;
-
- pHalmac_api->halmac_dump_fifo = halmac_dump_fifo_88xx;
- pHalmac_api->halmac_get_fifo_size = halmac_get_fifo_size_88xx;
-
- pHalmac_api->halmac_chk_txdesc = halmac_chk_txdesc_88xx;
-
- if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface) {
- pHalmac_api->halmac_cfg_rx_aggregation = halmac_cfg_rx_aggregation_88xx_sdio;
- pHalmac_api->halmac_init_interface_cfg = halmac_init_sdio_cfg_88xx;
- pHalmac_api->halmac_deinit_interface_cfg = halmac_deinit_sdio_cfg_88xx;
- pHalmac_api->halmac_reg_read_8 = halmac_reg_read_8_sdio_88xx;
- pHalmac_api->halmac_reg_write_8 = halmac_reg_write_8_sdio_88xx;
- pHalmac_api->halmac_reg_read_16 = halmac_reg_read_16_sdio_88xx;
- pHalmac_api->halmac_reg_write_16 = halmac_reg_write_16_sdio_88xx;
- pHalmac_api->halmac_reg_read_32 = halmac_reg_read_32_sdio_88xx;
- pHalmac_api->halmac_reg_write_32 = halmac_reg_write_32_sdio_88xx;
- } else if (HALMAC_INTERFACE_USB == pHalmac_adapter->halmac_interface) {
- pHalmac_api->halmac_cfg_rx_aggregation = halmac_cfg_rx_aggregation_88xx_usb;
- pHalmac_api->halmac_init_interface_cfg = halmac_init_usb_cfg_88xx;
- pHalmac_api->halmac_deinit_interface_cfg = halmac_deinit_usb_cfg_88xx;
- pHalmac_api->halmac_reg_read_8 = halmac_reg_read_8_usb_88xx;
- pHalmac_api->halmac_reg_write_8 = halmac_reg_write_8_usb_88xx;
- pHalmac_api->halmac_reg_read_16 = halmac_reg_read_16_usb_88xx;
- pHalmac_api->halmac_reg_write_16 = halmac_reg_write_16_usb_88xx;
- pHalmac_api->halmac_reg_read_32 = halmac_reg_read_32_usb_88xx;
- pHalmac_api->halmac_reg_write_32 = halmac_reg_write_32_usb_88xx;
- } else if (HALMAC_INTERFACE_PCIE == pHalmac_adapter->halmac_interface) {
- pHalmac_api->halmac_cfg_rx_aggregation = halmac_cfg_rx_aggregation_88xx_pcie;
- pHalmac_api->halmac_init_interface_cfg = halmac_init_pcie_cfg_88xx;
- pHalmac_api->halmac_deinit_interface_cfg = halmac_deinit_pcie_cfg_88xx;
- pHalmac_api->halmac_reg_read_8 = halmac_reg_read_8_pcie_88xx;
- pHalmac_api->halmac_reg_write_8 = halmac_reg_write_8_pcie_88xx;
- pHalmac_api->halmac_reg_read_16 = halmac_reg_read_16_pcie_88xx;
- pHalmac_api->halmac_reg_write_16 = halmac_reg_write_16_pcie_88xx;
- pHalmac_api->halmac_reg_read_32 = halmac_reg_read_32_pcie_88xx;
- pHalmac_api->halmac_reg_write_32 = halmac_reg_write_32_pcie_88xx;
- } else {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Set halmac io function Error!!\n");
- }
-
- pHalmac_api->halmac_set_bulkout_num = halmac_set_bulkout_num_88xx;
- pHalmac_api->halmac_get_sdio_tx_addr = halmac_get_sdio_tx_addr_88xx;
- pHalmac_api->halmac_get_usb_bulkout_id = halmac_get_usb_bulkout_id_88xx;
- pHalmac_api->halmac_timer_2s = halmac_timer_2s_88xx;
- pHalmac_api->halmac_fill_txdesc_checksum = halmac_fill_txdesc_check_sum_88xx;
-
- /* Get Chip_id and Chip_version */
- chip_id = HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_CFG2);
- if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface) {
- if (chip_id == 0xEA) {
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SDIO_HSUS_CTRL, HALMAC_REG_READ_8(pHalmac_adapter, REG_SDIO_HSUS_CTRL) & ~(BIT(0)));
-
- polling_count = HALMAC_POLLING_READY_TIMEOUT_COUNT;
- while (!(HALMAC_REG_READ_8(pHalmac_adapter, REG_SDIO_HSUS_CTRL) & 0x02)) {
- polling_count--;
- if (polling_count == 0)
- return HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL;
- }
- }
- chip_id = HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_CFG2);
- }
- chip_version = (u8)HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_CFG1 + 1) >> 4;
-
- pHalmac_adapter->chip_version = (HALMAC_CHIP_VER)chip_version;
-
- if (HALMAC_CHIP_ID_HW_DEF_8822B == chip_id) {
-#if HALMAC_8822B_SUPPORT
- /*mount 8822b function and data*/
- halmac_mount_api_8822b(pHalmac_adapter);
-#endif
-
- } else if (HALMAC_CHIP_ID_HW_DEF_8821C == chip_id) {
-#if HALMAC_8821C_SUPPORT
- /*mount 8822b function and data*/
- halmac_mount_api_8821c(pHalmac_adapter);
-#endif
- } else if (HALMAC_CHIP_ID_HW_DEF_8197F == chip_id) {
-#if HALMAC_8197F_SUPPORT
- /*mount 8822b function and data*/
- halmac_mount_api_8197f(pHalmac_adapter);
-#endif
- } else {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Chip ID undefine!!\n");
- return HALMAC_RET_CHIP_NOT_SUPPORT;
- }
-
- pHalmac_adapter->txff_allocation.tx_fifo_pg_num = 0;
- pHalmac_adapter->txff_allocation.ac_q_pg_num = 0;
- pHalmac_adapter->txff_allocation.rsvd_pg_bndy = 0;
- pHalmac_adapter->txff_allocation.rsvd_drv_pg_bndy = 0;
- pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy = 0;
- pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy = 0;
- pHalmac_adapter->txff_allocation.rsvd_cpu_instr_pg_bndy = 0;
- pHalmac_adapter->txff_allocation.rsvd_fw_txbuff_pg_bndy = 0;
- pHalmac_adapter->txff_allocation.pub_queue_pg_num = 0;
- pHalmac_adapter->txff_allocation.high_queue_pg_num = 0;
- pHalmac_adapter->txff_allocation.low_queue_pg_num = 0;
- pHalmac_adapter->txff_allocation.normal_queue_pg_num = 0;
- pHalmac_adapter->txff_allocation.extra_queue_pg_num = 0;
-
- pHalmac_adapter->txff_allocation.la_mode = HALMAC_LA_MODE_DISABLE;
-
-#if HALMAC_PLATFORM_TESTPROGRAM
- pHalmac_api->halmac_write_efuse = halmac_write_efuse_88xx;
- pHalmac_api->halmac_read_efuse = halmac_read_efuse_88xx;
- pHalmac_api->halmac_switch_efuse_bank = halmac_switch_efuse_bank_88xx;
-
- pHalmac_api->halmac_gen_txdesc = halmac_gen_tx_desc_88xx;
- pHalmac_api->halmac_txdesc_parser = halmac_tx_desc_parser_88xx;
- pHalmac_api->halmac_rxdesc_parser = halmac_rx_desc_parser_88xx;
- pHalmac_api->halmac_get_txdesc_size = halmac_get_txdesc_size_88xx;
- pHalmac_api->halmac_send_packet = halmac_send_packet_88xx;
- pHalmac_api->halmac_parse_packet = halmac_parse_packet_88xx;
-
- pHalmac_api->halmac_get_pcie_packet = halmac_get_pcie_packet_88xx;
- pHalmac_api->halmac_gen_txagg_desc = halmac_gen_txagg_desc_88xx;
-
- pHalmac_api->halmac_bb_reg_read = halmac_bb_reg_read_88xx;
- pHalmac_api->halmac_bb_reg_write = halmac_bb_reg_write_88xx;
-
- pHalmac_api->halmac_rf_reg_read = halmac_rf_ac_reg_read_88xx;
- pHalmac_api->halmac_rf_reg_write = halmac_rf_ac_reg_write_88xx;
- pHalmac_api->halmac_init_antenna_selection = halmac_init_antenna_selection_88xx;
- pHalmac_api->halmac_bb_preconfig = halmac_bb_preconfig_88xx;
- pHalmac_api->halmac_init_crystal_capacity = halmac_init_crystal_capacity_88xx;
- pHalmac_api->halmac_trx_antenna_setting = halmac_trx_antenna_setting_88xx;
-
- pHalmac_api->halmac_himr_setting_sdio = halmac_himr_setting_88xx_sdio;
-
- pHalmac_api->halmac_send_beacon = halmac_send_beacon_88xx;
- pHalmac_api->halmac_stop_beacon = halmac_stop_beacon_88xx;
- pHalmac_api->halmac_check_trx_status = halmac_check_trx_status_88xx;
- pHalmac_api->halmac_set_agg_num = halmac_set_agg_num_88xx;
- pHalmac_api->halmac_get_management_txdesc = halmac_get_management_txdesc_88xx;
- pHalmac_api->halmac_send_control = halmac_send_control_88xx;
- pHalmac_api->halmac_send_hiqueue = halmac_send_hiqueue_88xx;
- pHalmac_api->halmac_media_status_rpt = halmac_media_status_rpt_88xx;
-
- pHalmac_api->halmac_timer_10ms = halmac_timer_10ms_88xx;
-
- pHalmac_api->halmac_download_firmware_fpag = halmac_download_firmware_fpga_88xx;
- pHalmac_api->halmac_download_rom_fpga = halmac_download_rom_fpga_88xx;
- pHalmac_api->halmac_download_flash = halmac_download_flash_88xx;
- pHalmac_api->halmac_erase_flash = halmac_erase_flash_88xx;
- pHalmac_api->halmac_check_flash = halmac_check_flash_88xx;
- pHalmac_api->halmac_send_nlo = halmac_send_nlo_88xx;
-
- pHalmac_api->halmac_config_security = halmac_config_security_88xx;
- pHalmac_api->halmac_read_cam = halmac_read_cam_88xx;
- pHalmac_api->halmac_write_cam = halmac_write_cam_88xx;
- pHalmac_api->halmac_dump_cam_table = halmac_dump_cam_table_88xx;
- pHalmac_api->halmac_load_cam_table = halmac_load_cam_table_88xx;
-
- pHalmac_api->halmac_get_chip_type = halmac_get_chip_type_88xx;
-
- pHalmac_api->halmac_get_rx_agg_num = halmac_get_rx_agg_num_88xx;
-
- if (pHalmac_adapter->chip_id == HALMAC_CHIP_ID_8822B)
- pHalmac_api->halmac_run_pwrseq = halmac_run_pwrseq_8822b;
- else if (pHalmac_adapter->chip_id == HALMAC_CHIP_ID_8821C)
- pHalmac_api->halmac_run_pwrseq = halmac_run_pwrseq_8821c;
-
- if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface) {
- pHalmac_api->halmac_reg_read_8 = halmac_reg_read_8_sdio_tp_88xx;
- pHalmac_api->halmac_reg_write_8 = halmac_reg_write_8_sdio_tp_88xx;
- pHalmac_api->halmac_reg_read_16 = halmac_reg_read_16_sdio_tp_88xx;
- pHalmac_api->halmac_reg_write_16 = halmac_reg_write_16_sdio_tp_88xx;
- pHalmac_api->halmac_reg_read_32 = halmac_reg_read_32_sdio_tp_88xx;
- pHalmac_api->halmac_reg_write_32 = halmac_reg_write_32_sdio_tp_88xx;
- }
-#endif
- return HALMAC_RET_SUCCESS;
-}
-
-
-/**
- * halmac_download_firmware_88xx() - download Firmware
- * @pHalmac_adapter
- * @pHamacl_fw : FW bin file
- * @halmac_fw_size
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_download_firmware_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pHamacl_fw,
- IN u32 halmac_fw_size
-)
-{
- u8 value8;
- u8 *pFile_ptr;
- u16 value16;
- u32 restore_index = 0;
- u32 halmac_h2c_ver = 0, fw_h2c_ver = 0;
- u32 iram_pkt_size, dmem_pkt_size, eram_pkt_size = 0;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
- HALMAC_RESTORE_INFO restore_info[DLFW_RESTORE_REG_NUM_88XX];
- HALMAC_RET_STATUS status;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DOWNLOAD_FIRMWARE);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_download_firmware_88xx ==========>\n");
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_download_firmware_88xx start!!\n");
-
- if (halmac_fw_size > HALMAC_FW_SIZE_MAX_88XX || halmac_fw_size < HALMAC_FWHDR_SIZE_88XX) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "FW size error!\n");
- return HALMAC_RET_FW_SIZE_ERR;
- }
-
- fw_h2c_ver = *((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_H2C_FORMAT_VER_88XX));
- halmac_h2c_ver = H2C_FORMAT_VERSION;
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac h2c/c2h format = %x, fw h2c/c2h format = %x!!\n", halmac_h2c_ver, fw_h2c_ver);
- if (fw_h2c_ver != halmac_h2c_ver)
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_WARN, "H2C/C2H version mismatch between HALMAC and FW, Offload Feature May fail!\n");
-
- pHalmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE;
-
- value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_FUNC_EN + 1);
- value8 = (u8)(value8 & ~(BIT(2)));
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SYS_FUNC_EN + 1, value8); /* Disable CPU reset */
-
-
- restore_info[restore_index].length = 1;
- restore_info[restore_index].mac_register = REG_TXDMA_PQ_MAP + 1;
- restore_info[restore_index].value = HALMAC_REG_READ_8(pHalmac_adapter, REG_TXDMA_PQ_MAP + 1);
- restore_index++;
- value8 = HALMAC_DMA_MAPPING_HIGH << 6;
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXDMA_PQ_MAP + 1, value8); /* set HIQ to hi priority */
-
- /* DLFW only use HIQ, map HIQ to hi priority */
- pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI] = HALMAC_DMA_MAPPING_HIGH;
- restore_info[restore_index].length = 1;
- restore_info[restore_index].mac_register = REG_CR;
- restore_info[restore_index].value = HALMAC_REG_READ_8(pHalmac_adapter, REG_CR);
- restore_index++;
- restore_info[restore_index].length = 4;
- restore_info[restore_index].mac_register = REG_H2CQ_CSR;
- restore_info[restore_index].value = BIT(31);
- restore_index++;
- value8 = BIT_HCI_TXDMA_EN | BIT_TXDMA_EN;
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR, value8);
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_H2CQ_CSR, BIT(31));
-
- /* Config hi priority queue and public priority queue page number (only for DLFW) */
- restore_info[restore_index].length = 2;
- restore_info[restore_index].mac_register = REG_FIFOPAGE_INFO_1;
- restore_info[restore_index].value = HALMAC_REG_READ_16(pHalmac_adapter, REG_FIFOPAGE_INFO_1);
- restore_index++;
- restore_info[restore_index].length = 4;
- restore_info[restore_index].mac_register = REG_RQPN_CTRL_2;
- restore_info[restore_index].value = HALMAC_REG_READ_32(pHalmac_adapter, REG_RQPN_CTRL_2) | BIT(31);
- restore_index++;
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_INFO_1, 0x200);
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RQPN_CTRL_2, restore_info[restore_index - 1].value);
-
- if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface) {
- HALMAC_REG_READ_32(pHalmac_adapter, REG_SDIO_FREE_TXPG);
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_SDIO_TX_CTRL, 0x00000000);
- }
-
- pHalmac_adapter->fw_version.version = rtk_le16_to_cpu(*((u16 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_VERSION_88XX)));
- pHalmac_adapter->fw_version.sub_version = *(pHamacl_fw + HALMAC_FWHDR_OFFSET_SUBVERSION_88XX);
- pHalmac_adapter->fw_version.sub_index = *(pHamacl_fw + HALMAC_FWHDR_OFFSET_SUBINDEX_88XX);
-
- dmem_pkt_size = *((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_DMEM_SIZE_88XX));
- iram_pkt_size = *((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_IRAM_SIZE_88XX));
- if (0 != ((*(pHamacl_fw + HALMAC_FWHDR_OFFSET_MEM_USAGE_88XX)) & BIT(4)))
- eram_pkt_size = *((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_ERAM_SIZE_88XX));
-
- dmem_pkt_size = rtk_le32_to_cpu(dmem_pkt_size);
- iram_pkt_size = rtk_le32_to_cpu(iram_pkt_size);
- eram_pkt_size = rtk_le32_to_cpu(eram_pkt_size);
-
- dmem_pkt_size += HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX;
- iram_pkt_size += HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX;
- if (0 != eram_pkt_size)
- eram_pkt_size += HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX;
-
- if (halmac_fw_size != (HALMAC_FWHDR_SIZE_88XX + dmem_pkt_size + iram_pkt_size + eram_pkt_size)) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "FW size mismatch the real fw size!\n");
- goto DLFW_FAIL;
- }
-
- value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_CR + 1);
- restore_info[restore_index].length = 1;
- restore_info[restore_index].mac_register = REG_CR + 1;
- restore_info[restore_index].value = value8;
- restore_index++;
- value8 = (u8)(value8 | BIT(0));
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR + 1, value8); /* Enable SW TX beacon */
-
- value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_BCN_CTRL);
- restore_info[restore_index].length = 1;
- restore_info[restore_index].mac_register = REG_BCN_CTRL;
- restore_info[restore_index].value = value8;
- restore_index++;
- value8 = (u8)((value8 & (~BIT(3))) | BIT(4));
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BCN_CTRL, value8); /* Disable beacon related functions */
-
- value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_FWHW_TXQ_CTRL + 2);
- restore_info[restore_index].length = 1;
- restore_info[restore_index].mac_register = REG_FWHW_TXQ_CTRL + 2;
- restore_info[restore_index].value = value8;
- restore_index++;
- value8 = (u8)(value8 & ~(BIT(6)));
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FWHW_TXQ_CTRL + 2, value8); /* Disable ptcl tx bcnq */
-
- restore_info[restore_index].length = 2;
- restore_info[restore_index].mac_register = REG_FIFOPAGE_CTRL_2;
- restore_info[restore_index].value = HALMAC_REG_READ_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2) | BIT(15);
- restore_index++;
- value16 = 0x8000;
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, value16); /* Set beacon header to 0 */
-
- value16 = (u16)(HALMAC_REG_READ_16(pHalmac_adapter, REG_MCUFW_CTRL) & 0x3800);
- value16 |= BIT(0);
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MCUFW_CTRL, value16); /* MCU/FW setting */
-
- value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_CPU_DMEM_CON + 2);
- value8 &= ~(BIT(0));
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CPU_DMEM_CON + 2, value8);
- value8 |= BIT(0);
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CPU_DMEM_CON + 2, value8);
-
- /* Download to DMEM */
- pFile_ptr = pHamacl_fw + HALMAC_FWHDR_SIZE_88XX;
- /* if (HALMAC_RET_SUCCESS != halmac_dlfw_to_mem_88xx(pHalmac_adapter, pFile_ptr, HALMAC_OCPBASE_DMEM_88XX, dmem_pkt_size)) */
- if (HALMAC_RET_SUCCESS != halmac_dlfw_to_mem_88xx(pHalmac_adapter, pFile_ptr,
- (*((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_DMEM_ADDR_88XX))) & ~(BIT(31)), dmem_pkt_size))
- goto DLFW_END;
-
- /* Download to IMEM */
- pFile_ptr = pHamacl_fw + HALMAC_FWHDR_SIZE_88XX + dmem_pkt_size;
- /* if (HALMAC_RET_SUCCESS != halmac_dlfw_to_mem_88xx(pHalmac_adapter, pFile_ptr, HALMAC_OCPBASE_IMEM_88XX, iram_pkt_size)) */
- if (HALMAC_RET_SUCCESS != halmac_dlfw_to_mem_88xx(pHalmac_adapter, pFile_ptr,
- (*((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_IRAM_ADDR_88XX))) & ~(BIT(31)), iram_pkt_size))
- goto DLFW_END;
-
- /* Download to EMEM */
- if (0 != eram_pkt_size) {
- pFile_ptr = pHamacl_fw + HALMAC_FWHDR_SIZE_88XX + dmem_pkt_size + iram_pkt_size;
- if (HALMAC_RET_SUCCESS != halmac_dlfw_to_mem_88xx(pHalmac_adapter, pFile_ptr,
- (*((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_EMEM_ADDR_88XX))) & ~(BIT(31)), eram_pkt_size))
- goto DLFW_END;
- }
-
-DLFW_END:
-
- halmac_restore_mac_register_88xx(pHalmac_adapter, restore_info, DLFW_RESTORE_REG_NUM_88XX);
-
- if (HALMAC_RET_SUCCESS != halmac_dlfw_end_flow_88xx(pHalmac_adapter))
- goto DLFW_FAIL;
-
- pHalmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_DONE;
-
-
- if (_TRUE == pHalmac_adapter->gen_info_valid) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Auto send halmac_send_general_info after redownload fw\n");
- status = halmac_send_general_info_88xx(pHalmac_adapter, &(pHalmac_adapter->general_info));
-
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_send_general_info error = %x\n", status);
- return status;
- }
- if (HALMAC_DLFW_DONE == pHalmac_adapter->halmac_state.dlfw_state)
- pHalmac_adapter->halmac_state.dlfw_state = HALMAC_GEN_INFO_SENT;
- }
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_download_firmware_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-
-DLFW_FAIL:
-
- /* Disable FWDL_EN */
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MCUFW_CTRL, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_MCUFW_CTRL) & ~(BIT(0))));
-
- return HALMAC_RET_DLFW_FAIL;
-}
-
-/**
- * halmac_get_fw_version_88xx() - get FW version
- * @pHalmac_adapter
- * @pFw_version
- * Author : Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_get_fw_version_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- OUT PHALMAC_FW_VERSION pFw_version
-)
-{
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (0 == pHalmac_adapter->halmac_state.dlfw_state) {
- return HALMAC_RET_DLFW_FAIL;
- } else {
- pFw_version->version = pHalmac_adapter->fw_version.version;
- pFw_version->sub_version = pHalmac_adapter->fw_version.sub_version;
- pFw_version->sub_index = pHalmac_adapter->fw_version.sub_index;
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_cfg_mac_addr_88xx() - config Mac Address
- * @pHalmac_adapter
- * @halmac_port : 0 : port0 1 : port1
- * @pHal_address : mac address
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_cfg_mac_addr_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 halmac_port,
- IN PHALMAC_WLAN_ADDR pHal_address
-)
-{
- u16 mac_address_H;
- u32 mac_address_L;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_MAC_ADDR);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_mac_addr_88xx ==========>\n");
-
- if (halmac_port > 2) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "port index > 2\n");
- return HALMAC_RET_PORT_NOT_SUPPORT;
- }
-
- mac_address_L = pHal_address->Address_L_H.Address_Low;
- mac_address_H = pHal_address->Address_L_H.Address_High;
-
- mac_address_L = rtk_le32_to_cpu(mac_address_L);
- mac_address_H = rtk_le16_to_cpu(mac_address_H);
-
- pHalmac_adapter->pHal_mac_addr[halmac_port].Address_L_H.Address_Low = mac_address_L;
- pHalmac_adapter->pHal_mac_addr[halmac_port].Address_L_H.Address_High = mac_address_H;
-
- if (0 == halmac_port) {
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MACID, mac_address_L);
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MACID + 4, mac_address_H);
- } else {
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MACID1, mac_address_L);
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MACID1 + 4, mac_address_H);
- }
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_mac_addr_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_cfg_bssid_88xx() - config BSSID
- * @pHalmac_adapter
- * @halmac_port : 0 : port0 1 : port1
- * @pHal_address : mac address
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_cfg_bssid_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 halmac_port,
- IN PHALMAC_WLAN_ADDR pHal_address
-)
-{
- u16 bssid_address_H;
- u32 bssid_address_L;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_BSSID);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_bssid_88xx ==========>\n");
-
- if (halmac_port > 2) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "port index > 2\n");
- return HALMAC_RET_PORT_NOT_SUPPORT;
- }
-
- bssid_address_L = pHal_address->Address_L_H.Address_Low;
- bssid_address_H = pHal_address->Address_L_H.Address_High;
-
- bssid_address_L = rtk_le32_to_cpu(bssid_address_L);
- bssid_address_H = rtk_le16_to_cpu(bssid_address_H);
-
- pHalmac_adapter->pHal_bss_addr[halmac_port].Address_L_H.Address_Low = bssid_address_L;
- pHalmac_adapter->pHal_bss_addr[halmac_port].Address_L_H.Address_High = bssid_address_H;
-
- if (0 == halmac_port) {
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_BSSID, bssid_address_L);
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_BSSID + 4, bssid_address_H);
- } else {
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_BSSID1, bssid_address_L);
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_BSSID1 + 4, bssid_address_H);
- }
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_bssid_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_cfg_multicast_addr_88xx() - config multicast address
- * @pHalmac_adapter
- * @pHal_address : mac address
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_cfg_multicast_addr_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_WLAN_ADDR pHal_address
-)
-{
- u16 address_H;
- u32 address_L;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_MULTICAST_ADDR);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_multicast_addr_88xx ==========>\n");
-
- address_L = pHal_address->Address_L_H.Address_Low;
- address_H = pHal_address->Address_L_H.Address_High;
-
- address_L = rtk_le32_to_cpu(address_L);
- address_H = rtk_le16_to_cpu(address_H);
-
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MAR, address_L);
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MAR + 4, address_H);
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_multicast_addr_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_pre_init_system_cfg_88xx() - config system register before power on
- * @pHalmac_adapter
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_pre_init_system_cfg_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-)
-{
- u32 value32;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
- u8 enable_bb;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_PRE_INIT_SYSTEM_CFG);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_pre_init_system_cfg ==========>\n");
-
- /* Config PIN Mux */
- value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_PAD_CTRL1);
- value32 = value32 & (~(BIT(28) | BIT(29)));
- value32 = value32 | BIT(28) | BIT(29);
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_PAD_CTRL1, value32);
-
- value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_LED_CFG);
- value32 = value32 & (~(BIT(25) | BIT(26)));
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_LED_CFG, value32);
-
- value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_GPIO_MUXCFG);
- value32 = value32 & (~(BIT(2)));
- value32 = value32 | BIT(2);
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_GPIO_MUXCFG, value32);
-
- enable_bb = _FALSE;
- halmac_set_hw_value_88xx(pHalmac_adapter, HALMAC_HW_EN_BB_RF, &enable_bb);
-
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_pre_init_system_cfg <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_init_system_cfg_88xx() - config system register after power on
- * @pHalmac_adapter
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_init_system_cfg_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_INIT_SYSTEM_CFG);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_system_cfg ==========>\n");
-
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SYS_FUNC_EN + 1, HALMAC_FUNCTION_ENABLE_88XX);
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_SYS_SDIO_CTRL, (u32)(HALMAC_REG_READ_32(pHalmac_adapter, REG_SYS_SDIO_CTRL) | BIT_LTE_MUX_CTRL_PATH));
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_CPU_DMEM_CON, (u32)(HALMAC_REG_READ_32(pHalmac_adapter, REG_CPU_DMEM_CON) | BIT_WL_PLATFORM_RST));
-
- /* pHalmac_api->halmac_init_h2c(pHalmac_adapter); */
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_system_cfg <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_init_protocol_cfg_88xx() - config protocol related register
- * @pHalmac_adapter
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_init_protocol_cfg_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-)
-{
- u16 value16;
- u32 value32;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_INIT_PROTOCOL_CFG);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_protocol_cfg_88xx ==========>\n");
-
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BASIC_CFEND_RATE, HALMAC_BASIC_CFEND_RATE_88XX);
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_STBC_CFEND_RATE, HALMAC_STBC_CFEND_RATE_88XX);
-
- value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_RRSR);
- value32 = (value32 & ~BIT_MASK_RRSC_BITMAP) | HALMAC_RESPONSE_RATE_88XX;
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RRSR, value32);
-
- value16 = HALMAC_SIFS_CCK_PTCL_88XX | (HALMAC_SIFS_OFDM_PTCL_88XX << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL);
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_SPEC_SIFS, value16);
-
- value16 = BIT_LRL(HALMAC_LONG_RETRY_LIMIT_88XX) | BIT_SRL(HALMAC_SHORT_RETRY_LIMIT_88XX);
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RETRY_LIMIT, value16);
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_protocol_cfg_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_init_edca_cfg_88xx() - config EDCA register
- * @pHalmac_adapter
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_init_edca_cfg_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-)
-{
- u8 value8;
- u32 value32;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_INIT_EDCA_CFG);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_edca_cfg_88xx ==========>\n");
-
- /* Clear TX pause */
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TXPAUSE, 0x0000);
-
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SLOT, HALMAC_SLOT_TIME_88XX);
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PIFS, HALMAC_PIFS_TIME_88XX);
- value32 = HALMAC_SIFS_CCK_CTX_88XX | (HALMAC_SIFS_OFDM_CTX_88XX << BIT_SHIFT_SIFS_OFDM_CTX) |
- (HALMAC_SIFS_CCK_TRX_88XX << BIT_SHIFT_SIFS_CCK_TRX) | (HALMAC_SIFS_OFDM_TRX_88XX << BIT_SHIFT_SIFS_OFDM_TRX);
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_SIFS, value32);
-
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_EDCA_VO_PARAM, HALMAC_REG_READ_32(pHalmac_adapter, REG_EDCA_VO_PARAM) & 0xFFFF);
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_EDCA_VO_PARAM + 2, HALMAC_VO_TXOP_LIMIT_88XX);
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_EDCA_VI_PARAM + 2, HALMAC_VI_TXOP_LIMIT_88XX);
-
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RD_NAV_NXT, HALMAC_RDG_NAV_88XX | (HALMAC_TXOP_NAV_88XX << 16));
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RXTSF_OFFSET_CCK, HALMAC_CCK_RX_TSF_88XX | (HALMAC_OFDM_RX_TSF_88XX) << 8);
-
- value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_RD_CTRL + 1);
- value8 |= (BIT_VOQ_RD_INIT_EN | BIT_VIQ_RD_INIT_EN | BIT_BEQ_RD_INIT_EN);
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RD_CTRL + 1, value8);
-
- /* Set beacon cotrol - enable TSF and other related functions */
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BCN_CTRL, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_BCN_CTRL) | BIT_EN_BCN_FUNCTION));
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BCN_CTRL_CLINT0, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_BCN_CTRL_CLINT0) | BIT_CLI0_EN_BCN_FUNCTION));
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BCN_CTRL_CLINT1, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_BCN_CTRL_CLINT1) | BIT_CLI1_EN_BCN_FUNCTION));
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BCN_CTRL_CLINT2, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_BCN_CTRL_CLINT2) | BIT_CLI2_EN_BCN_FUNCTION));
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BCN_CTRL_CLINT3, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_BCN_CTRL_CLINT3) | BIT_CLI3_EN_BCN_FUNCTION));
-
- /* Set send beacon related registers */
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_TBTT_PROHIBIT, HALMAC_TBTT_PROHIBIT_88XX | (HALMAC_TBTT_HOLD_TIME_88XX << BIT_SHIFT_TBTT_HOLD_TIME_AP));
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_DRVERLYINT, HALMAC_DRIVER_EARLY_INT_88XX);
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BCNDMATIM, HALMAC_BEACON_DMA_TIM_88XX);
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_edca_cfg_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_init_wmac_cfg_88xx() - config WMAC register
- * @pHalmac_adapter
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_init_wmac_cfg_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_INIT_WMAC_CFG);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_wmac_cfg_88xx ==========>\n");
-
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RXFLTMAP0, HALMAC_RX_FILTER0_88XX);
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RXFLTMAP, HALMAC_RX_FILTER_88XX);
-
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RCR, HALMAC_RCR_CONFIG_88XX);
-
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_SECCFG, HALMAC_SECURITY_CONFIG_88XX);
-
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TCR + 1, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_TCR + 1) | 0x30));
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TCR + 2, 0x30);
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TCR + 1, 0x00);
-
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WMAC_OPTION_FUNCTION + 8, 0x30810041);
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WMAC_OPTION_FUNCTION + 4, 0x50802080);
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1, 0xC00F0038);
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_wmac_cfg_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_init_mac_cfg_88xx() - config page1~page7 register
- * @pHalmac_adapter
- * @mode : normal, trxshare, wmm, p2p, loopback
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_init_mac_cfg_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_TRX_MODE mode
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_INIT_MAC_CFG);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_mac_cfg_88xx ==========>mode = %d\n", mode);
-
- status = pHalmac_api->halmac_init_trx_cfg(pHalmac_adapter, mode);
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_trx_cfg errorr = %x\n", status);
- return status;
- }
-#if 1
- status = halmac_init_protocol_cfg_88xx(pHalmac_adapter);
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_protocol_cfg_88xx error = %x\n", status);
- return status;
- }
-
- status = halmac_init_edca_cfg_88xx(pHalmac_adapter);
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_edca_cfg_88xx error = %x\n", status);
- return status;
- }
-
- status = halmac_init_wmac_cfg_88xx(pHalmac_adapter);
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_wmac_cfg_88xx error = %x\n", status);
- return status;
- }
-#endif
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_mac_cfg_88xx <==========\n");
-
- return status;
-}
-
-/**
- * halmac_cfg_operation_mode_88xx() - config operation mode
- * @pHalmac_adapter
- * @wireless_mode : b/g/n/ac
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_cfg_operation_mode_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_WIRELESS_MODE wireless_mode
-)
-{
- VOID *pDriver_adapter = NULL;
- HALMAC_WIRELESS_MODE wireless_mode_local = HALMAC_WIRELESS_MODE_UNDEFINE;
-
- wireless_mode_local = wireless_mode;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_OPERATION_MODE);
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_operation_mode_88xx ==========>wireless_mode = %d\n", wireless_mode);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_operation_mode_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_cfg_bw_88xx() - config channel & bandwidth
- * @pHalmac_adapter
- * @channel : WLAN channel, support 2.4G & 5G
- * @pri_ch_idx : idx1, idx2, idx3, idx4
- * @bw : 20, 40, 80, 160, 5 ,10
- * Author : KaiYuan Chang
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_cfg_ch_bw_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 channel,
- IN HALMAC_PRI_CH_IDX pri_ch_idx,
- IN HALMAC_BW bw
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_CH_BW);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_ch_bw_88xx ==========>ch = %d, idx=%d, bw=%d\n", channel, pri_ch_idx, bw);
-
- halmac_cfg_pri_ch_idx_88xx(pHalmac_adapter, pri_ch_idx);
-
- halmac_cfg_bw_88xx(pHalmac_adapter, bw);
-
- halmac_cfg_ch_88xx(pHalmac_adapter, channel);
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_ch_bw_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-
-/**
- * halmac_cfg_bw_88xx() - config channel & bandwidth
- * @pHalmac_adapter
- * @channel : WLAN channel, support 2.4G & 5G
- * @pri_ch_idx : idx1, idx2, idx3, idx4
- * @bw : 20, 40, 80, 160, 5 ,10
- * Author : KaiYuan Chang
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_cfg_ch_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 channel
-)
-{
- u8 value8;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_CH_BW);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_ch_88xx ==========>ch = %d\n", channel);
-
- value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_CCK_CHECK);
- value8 = value8 & (~(BIT(7)));
-
- if (channel > 35)
- value8 = value8 | BIT(7);
-
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CCK_CHECK, value8);
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_ch_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_cfg_bw_88xx() - config channel & bandwidth
- * @pHalmac_adapter
- * @channel : WLAN channel, support 2.4G & 5G
- * @pri_ch_idx : idx1, idx2, idx3, idx4
- * @bw : 20, 40, 80, 160, 5 ,10
- * Author : KaiYuan Chang
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_cfg_pri_ch_idx_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_PRI_CH_IDX pri_ch_idx
-)
-{
- u8 txsc_40 = 0, txsc_20 = 0;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_CH_BW);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_pri_ch_idx_88xx ==========> idx=%d\n", pri_ch_idx);
-
- txsc_20 = pri_ch_idx;
- if ((HALMAC_CH_IDX_1 == txsc_20) || (HALMAC_CH_IDX_3 == txsc_20))
- txsc_40 = 9;
- else
- txsc_40 = 10;
-
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_DATA_SC, BIT_TXSC_20M(txsc_20) | BIT_TXSC_40M(txsc_40));
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_pri_ch_idx_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-
-}
-
-/**
- * halmac_cfg_bw_88xx() - config bandwidth
- * @pHalmac_adapter
- * @bw : 20, 40, 80, 160, 5 ,10
- * Author : KaiYuan Chang
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_cfg_bw_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_BW bw
-)
-{
- u32 value32;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_BW);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_bw_88xx ==========>bw=%d\n", bw);
-
- /* RF Mode */
- value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_WMAC_TRXPTCL_CTL);
- value32 = value32 & (~(BIT(7) | BIT(8)));
-
- switch (bw) {
- case HALMAC_BW_80:
- value32 = value32 | BIT(7);
- break;
- case HALMAC_BW_40:
- value32 = value32 | BIT(8);
- break;
- case HALMAC_BW_20:
- case HALMAC_BW_10:
- case HALMAC_BW_5:
- value32 = value32;
- break;
- default:
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_cfg_bw_88xx switch case not support\n");
- break;
- }
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WMAC_TRXPTCL_CTL, value32);
-
- /* MAC CLK */
- value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_AFE_CTRL1);
- value32 = (value32 & (~(BIT(20) | BIT(21)))) | (HALMAC_MAC_CLOCK_HW_DEF_80M << BIT_SHIFT_MAC_CLK_SEL);
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_AFE_CTRL1, value32);
-
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_USTIME_TSF, HALMAC_MAC_CLOCK_88XX);
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_USTIME_EDCA, HALMAC_MAC_CLOCK_88XX);
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_bw_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_clear_security_cam_88xx() - clear security CAM
- * @pHalmac_adapter
- * Author : KaiYuan Chang
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_clear_security_cam_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-)
-{
- VOID *pDriver_adapter = NULL;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_clear_security_cam_88xx ==========>\n");
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_clear_security_cam_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_dump_efuse_map_88xx() - dump "physical" efuse map
- * @pHalmac_adapter
- * @cfg : dump with auto/driver/FW
- * Author : Ivan Lin/KaiYuan Chang
- *
- * halmac_dump_efuse_map_88xx is async architecture, user can
- * refer to DumpEfuseMap page of FlowChart.vsd.
- * dump_efuse_map page of Halmac_flow_control.vsd is halmac api control
- * flow, only for SD1 internal use.
- *
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_dump_efuse_map_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_EFUSE_READ_CFG cfg
-)
-{
- VOID *pDriver_adapter = NULL;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
- HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.efuse_state_set.process_status);
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DUMP_EFUSE_MAP);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_dump_efuse_map_88xx ==========>cfg=%d\n", cfg);
-
- if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(dump efuse)...\n");
- return HALMAC_RET_BUSY_STATE;
- }
-
- if (HALMAC_EFUSE_CMD_CONSTRUCT_IDLE != halmac_query_efuse_curr_state_88xx(pHalmac_adapter)) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(dump efuse)...\n");
- return HALMAC_RET_ERROR_STATE;
- }
-
- *pProcess_status = HALMAC_CMD_PROCESS_IDLE;
- pHalmac_adapter->event_trigger.physical_efuse_map = 1;
-
- status = halmac_func_switch_efuse_bank_88xx(pHalmac_adapter, HALMAC_EFUSE_BANK_WIFI);
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_switch_efuse_bank error = %x\n", status);
- return status;
- }
-
- status = halmac_dump_efuse_88xx(pHalmac_adapter, cfg);
-
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_read_efuse error = %x\n", status);
- return status;
- }
-
- if (_TRUE == pHalmac_adapter->hal_efuse_map_valid) {
- *pProcess_status = HALMAC_CMD_PROCESS_DONE;
-
- PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE, *pProcess_status,
- pHalmac_adapter->pHalEfuse_map, pHalmac_adapter->hw_config_info.efuse_size);
- pHalmac_adapter->event_trigger.physical_efuse_map = 0;
- }
-
- if (HALMAC_RET_SUCCESS != halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE))
- return HALMAC_RET_ERROR_STATE;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_dump_efuse_map_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_dump_efuse_map_bt_88xx() - dump "BT physical" efuse map
- * @pHalmac_adapter
- * @cfg : dump with auto/driver/FW
- * Author : Soar / Ivan Lin
- *
- * halmac_dump_efuse_map_bt_88xx is async architecture, user can
- * refer to DumpEfuseMap page of FlowChart.vsd.
- * dump_efuse_map_bt page of Halmac_flow_control.vsd is halmac api control
- * flow, only for SD1 internal use.
- *
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_dump_efuse_map_bt_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_EFUSE_BANK halmac_efuse_bank,
- IN u32 bt_efuse_map_size,
- OUT u8 *pBT_efuse_map
-)
-{
- VOID *pDriver_adapter = NULL;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
- HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.efuse_state_set.process_status);
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DUMP_EFUSE_MAP_BT);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_dump_efuse_map_bt_88xx ==========>\n");
-
- if (pHalmac_adapter->hw_config_info.bt_efuse_size != bt_efuse_map_size)
- return HALMAC_RET_EFUSE_SIZE_INCORRECT;
-
- if ((halmac_efuse_bank >= HALMAC_EFUSE_BANK_MAX) || (halmac_efuse_bank == HALMAC_EFUSE_BANK_WIFI)) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Undefined BT bank\n");
- return HALMAC_RET_EFUSE_BANK_INCORRECT;
- }
-
- if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(dump efuse)...\n");
- return HALMAC_RET_BUSY_STATE;
- }
-
- if (HALMAC_EFUSE_CMD_CONSTRUCT_IDLE != halmac_query_efuse_curr_state_88xx(pHalmac_adapter)) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(dump efuse)...\n");
- return HALMAC_RET_ERROR_STATE;
- }
-
- status = halmac_func_switch_efuse_bank_88xx(pHalmac_adapter, halmac_efuse_bank);
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_switch_efuse_bank error = %x\n", status);
- return status;
- }
-
- status = halmac_read_hw_efuse_88xx(pHalmac_adapter, 0, bt_efuse_map_size, pBT_efuse_map);
-
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_read_hw_efuse_88xx error = %x\n", status);
- return status;
- }
-
- if (HALMAC_RET_SUCCESS != halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE))
- return HALMAC_RET_ERROR_STATE;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_dump_efuse_map_bt_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_read_efuse_88xx() - read "physical" efuse offset
- * @pHalmac_adapter
- * @halmac_offset
- * @pValue
- * Author : Ivan Lin/KaiYuan Chang
- * Return : HALMAC_RET_STATUS
- */
-/*
- * HALMAC_RET_STATUS
- * halmac_read_efuse_88xx(
- * IN PHALMAC_ADAPTER pHalmac_adapter,
- * IN u32 halmac_offset,
- * OUT u8 *pValue
- *)
- */
-
-/**
- * halmac_write_efuse_88xx() - write "physical" efuse offset
- * @pHalmac_adapter
- * @halmac_offset
- * @halmac_value
- * Author : Ivan Lin/KaiYuan Chang
- * Return : HALMAC_RET_STATUS
- */
-/*
- * HALMAC_RET_STATUS
- * halmac_write_efuse_88xx(
- * IN PHALMAC_ADAPTER pHalmac_adapter,
- * IN u32 halmac_offset,
- * IN u8 halmac_value
- *)
- */
-
-/**
- * halmac_write_efuse_bt_88xx() - write "BT physical" efuse offset
- * @pHalmac_adapter
- * @halmac_offset
- * @halmac_value
- * Author : Soar
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_write_efuse_bt_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset,
- IN u8 halmac_value,
- IN HALMAC_EFUSE_BANK halmac_efuse_bank
-)
-{
- VOID *pDriver_adapter = NULL;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
-
- HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.efuse_state_set.process_status);
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_WRITE_EFUSE_BT);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_write_efuse_bt_88xx ==========>\n");
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "offset : %X value : %X Bank : %X\n", halmac_offset, halmac_value, halmac_efuse_bank);
-
- if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait/Rcvd event(dump efuse)...\n");
- return HALMAC_RET_BUSY_STATE;
- }
-
- if (HALMAC_EFUSE_CMD_CONSTRUCT_IDLE != halmac_query_efuse_curr_state_88xx(pHalmac_adapter)) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(dump efuse)...\n");
- return HALMAC_RET_ERROR_STATE;
- }
-
- if (halmac_offset >= pHalmac_adapter->hw_config_info.efuse_size) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Offset is too large\n");
- return HALMAC_RET_EFUSE_SIZE_INCORRECT;
- }
-
- if ((halmac_efuse_bank > HALMAC_EFUSE_BANK_MAX) || (halmac_efuse_bank == HALMAC_EFUSE_BANK_WIFI)) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Undefined BT bank\n");
- return HALMAC_RET_EFUSE_BANK_INCORRECT;
- }
-
- status = halmac_func_switch_efuse_bank_88xx(pHalmac_adapter, halmac_efuse_bank);
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_switch_efuse_bank error = %x\n", status);
- return status;
- }
-
- status = halmac_func_write_efuse_88xx(pHalmac_adapter, halmac_offset, halmac_value);
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_write_efuse error = %x\n", status);
- return status;
- }
-
- if (HALMAC_RET_SUCCESS != halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE))
- return HALMAC_RET_ERROR_STATE;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_write_efuse_bt_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_get_efuse_size_88xx() - get "physical" efuse size
- * @pHalmac_adapter
- * @halmac_size : Output physical efuse size
- * Author : Ivan Lin/KaiYuan Chang
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_get_efuse_size_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- OUT u32 *halmac_size
-)
-{
- VOID *pDriver_adapter = NULL;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_GET_EFUSE_SIZE);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_get_efuse_size_88xx ==========>\n");
-
- *halmac_size = pHalmac_adapter->hw_config_info.efuse_size;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_get_efuse_size_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_get_logical_efuse_size_88xx() - get "logical" efuse size
- * @pHalmac_adapter
- * @halmac_size : Output logical efuse size
- * Author : Ivan Lin/KaiYuan Chang
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_get_logical_efuse_size_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- OUT u32 *halmac_size
-)
-{
- VOID *pDriver_adapter = NULL;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_GET_LOGICAL_EFUSE_SIZE);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_get_logical_efuse_size_88xx ==========>\n");
-
- *halmac_size = pHalmac_adapter->hw_config_info.eeprom_size;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_get_logical_efuse_size_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_dump_logical_efuse_map_88xx() - dump "logical" efuse map
- * @pHalmac_adapter
- * @cfg : dump with auto/driver/FW
- * Author : Soar
- *
- * halmac_dump_logical_efuse_map_88xx is async architecture, user can
- * refer to DumpEEPROMMap page of FlowChart.vsd.
- * dump_efuse_map page of Halmac_flow_control.vsd is halmac api control
- * flow, only for SD1 internal use.
- *
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_dump_logical_efuse_map_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_EFUSE_READ_CFG cfg
-)
-{
- u8 *pEeprom_map = NULL;
- u32 eeprom_size = pHalmac_adapter->hw_config_info.eeprom_size;
- VOID *pDriver_adapter = NULL;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
- HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.efuse_state_set.process_status);
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DUMP_LOGICAL_EFUSE_MAP);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_dump_logical_efuse_map_88xx ==========>cfg = %d\n", cfg);
-
- if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait/Rcvd event(dump efuse)...\n");
- return HALMAC_RET_BUSY_STATE;
- }
-
- if (HALMAC_EFUSE_CMD_CONSTRUCT_IDLE != halmac_query_efuse_curr_state_88xx(pHalmac_adapter)) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(dump efuse)...\n");
- return HALMAC_RET_ERROR_STATE;
- }
-
- *pProcess_status = HALMAC_CMD_PROCESS_IDLE;
- pHalmac_adapter->event_trigger.logical_efuse_map = 1;
-
- status = halmac_func_switch_efuse_bank_88xx(pHalmac_adapter, HALMAC_EFUSE_BANK_WIFI);
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_switch_efuse_bank error = %x\n", status);
- return status;
- }
-
- status = halmac_dump_efuse_88xx(pHalmac_adapter, cfg);
-
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_eeprom_parser_88xx error = %x\n", status);
- return status;
- }
-
- if (_TRUE == pHalmac_adapter->hal_efuse_map_valid) {
- *pProcess_status = HALMAC_CMD_PROCESS_DONE;
-
- pEeprom_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, eeprom_size);
- if (NULL == pEeprom_map) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac allocate local eeprom map Fail!!\n");
- return HALMAC_RET_MALLOC_FAIL;
- }
- PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_map, 0xFF, eeprom_size);
-
- if (HALMAC_RET_SUCCESS != halmac_eeprom_parser_88xx(pHalmac_adapter, pHalmac_adapter->pHalEfuse_map, pEeprom_map))
- return HALMAC_RET_EEPROM_PARSING_FAIL;
-
- PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_DUMP_LOGICAL_EFUSE, *pProcess_status, pEeprom_map, eeprom_size);
- pHalmac_adapter->event_trigger.logical_efuse_map = 0;
-
- PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size);
- }
-
- if (HALMAC_RET_SUCCESS != halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE))
- return HALMAC_RET_ERROR_STATE;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_dump_logical_efuse_map_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_read_logical_efuse_88xx() - read "logical" efuse offset
- * @pHalmac_adapter
- * @halmac_offset
- * @pValue
- * Author : Soar
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_read_logical_efuse_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset,
- OUT u8 *pValue
-)
-{
- u8 *pEeprom_map = NULL;
- u32 eeprom_size = pHalmac_adapter->hw_config_info.eeprom_size;
- VOID *pDriver_adapter = NULL;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.efuse_state_set.process_status);
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_READ_LOGICAL_EFUSE);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_read_logical_efuse_88xx ==========>\n");
-
- if (halmac_offset >= eeprom_size) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Offset is too large\n");
- return HALMAC_RET_EFUSE_SIZE_INCORRECT;
- }
-
- if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait/Rcvd event(dump efuse)...\n");
- return HALMAC_RET_BUSY_STATE;
- }
- if (HALMAC_EFUSE_CMD_CONSTRUCT_IDLE != halmac_query_efuse_curr_state_88xx(pHalmac_adapter)) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(dump efuse)...\n");
- return HALMAC_RET_ERROR_STATE;
- }
-
- pEeprom_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, eeprom_size);
- if (NULL == pEeprom_map) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac allocate local eeprom map Fail!!\n");
- return HALMAC_RET_MALLOC_FAIL;
- }
- PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_map, 0xFF, eeprom_size);
-
- status = halmac_func_switch_efuse_bank_88xx(pHalmac_adapter, HALMAC_EFUSE_BANK_WIFI);
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_switch_efuse_bank error = %x\n", status);
- return status;
- }
-
- status = halmac_read_logical_efuse_map_88xx(pHalmac_adapter, pEeprom_map);
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_read_logical_efuse_map error = %x\n", status);
- return status;
- }
-
- *pValue = *(pEeprom_map + halmac_offset);
-
- if (HALMAC_RET_SUCCESS != halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE))
- return HALMAC_RET_ERROR_STATE;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_read_logical_efuse_88xx <==========\n");
-
- PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_write_logical_efuse_88xx() - write "logical" efuse offset
- * @pHalmac_adapter
- * @halmac_offset
- * @halmac_value
- * Author : Soar
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_write_logical_efuse_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset,
- IN u8 halmac_value
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.efuse_state_set.process_status);
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_WRITE_LOGICAL_EFUSE);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_write_logical_efuse_88xx ==========>\n");
-
- if (halmac_offset >= pHalmac_adapter->hw_config_info.eeprom_size) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Offset is too large\n");
- return HALMAC_RET_EFUSE_SIZE_INCORRECT;
- }
-
- if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait/Rcvd event(dump efuse)...\n");
- return HALMAC_RET_BUSY_STATE;
- }
-
- if (HALMAC_EFUSE_CMD_CONSTRUCT_IDLE != halmac_query_efuse_curr_state_88xx(pHalmac_adapter)) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(dump efuse)...\n");
- return HALMAC_RET_ERROR_STATE;
- }
-
- status = halmac_func_switch_efuse_bank_88xx(pHalmac_adapter, HALMAC_EFUSE_BANK_WIFI);
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_switch_efuse_bank error = %x\n", status);
- return status;
- }
-
- status = halmac_func_write_logical_efuse_88xx(pHalmac_adapter, halmac_offset, halmac_value);
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_write_logical_efuse error = %x\n", status);
- return status;
- }
-
- if (HALMAC_RET_SUCCESS != halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE))
- return HALMAC_RET_ERROR_STATE;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_write_logical_efuse_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_pg_efuse_by_map_88xx() - pg efuse by map
- * @pHalmac_adapter
- * @pPg_efuse_info : map, map size, mask, mask size
- * @cfg : dump with auto/driver/FW
- * Author : Soar
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_pg_efuse_by_map_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_PG_EFUSE_INFO pPg_efuse_info,
- IN HALMAC_EFUSE_READ_CFG cfg
-)
-{
- VOID *pDriver_adapter = NULL;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.efuse_state_set.process_status);
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_PG_EFUSE_BY_MAP);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_pg_efuse_by_map_88xx ==========>\n");
-
- if (pPg_efuse_info->efuse_map_size != pHalmac_adapter->hw_config_info.eeprom_size) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "efuse_map_size is incorrect, should be %d bytes\n", pHalmac_adapter->hw_config_info.eeprom_size);
- return HALMAC_RET_EFUSE_SIZE_INCORRECT;
- }
-
- if ((pPg_efuse_info->efuse_map_size & 0xF) > 0) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "efuse_map_size should be multiple of 16\n");
- return HALMAC_RET_EFUSE_SIZE_INCORRECT;
- }
-
- if (pPg_efuse_info->efuse_mask_size != pPg_efuse_info->efuse_map_size >> 4) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "efuse_mask_size is incorrect, should be %d bytes\n", pPg_efuse_info->efuse_map_size >> 4);
- return HALMAC_RET_EFUSE_SIZE_INCORRECT;
- }
-
- if (NULL == pPg_efuse_info->pEfuse_map) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "efuse_map is NULL\n");
- return HALMAC_RET_NULL_POINTER;
- }
-
- if (NULL == pPg_efuse_info->pEfuse_mask) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "efuse_mask is NULL\n");
- return HALMAC_RET_NULL_POINTER;
- }
-
- if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait/Rcvd event(dump efuse)...\n");
- return HALMAC_RET_BUSY_STATE;
- }
-
- if (HALMAC_EFUSE_CMD_CONSTRUCT_IDLE != halmac_query_efuse_curr_state_88xx(pHalmac_adapter)) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(dump efuse)...\n");
- return HALMAC_RET_ERROR_STATE;
- }
-
- status = halmac_func_switch_efuse_bank_88xx(pHalmac_adapter, HALMAC_EFUSE_BANK_WIFI);
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_switch_efuse_bank error = %x\n", status);
- return status;
- }
-
- status = halmac_func_pg_efuse_by_map_88xx(pHalmac_adapter, pPg_efuse_info, cfg);
-
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_pg_efuse_by_map error = %x\n", status);
- return status;
- }
-
- if (HALMAC_RET_SUCCESS != halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE))
- return HALMAC_RET_ERROR_STATE;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_pg_efuse_by_map_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_get_c2h_info_88xx() - process halmac C2H packet
- * @pHalmac_adapter
- * @halmac_buf
- * @halmac_size
- * Author : KaiYuan Chang/Ivan Lin
- *
- * Used to process c2h packet info from RX path. After receiving the packet,
- * user need to call this api and pass the packet pointer.
- *
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_get_c2h_info_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *halmac_buf,
- IN u32 halmac_size
-)
-{
- VOID *pDriver_adapter = NULL;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_GET_C2H_INFO);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_get_c2h_info_88xx ==========>\n"); */
-
- /* Check if it is C2H packet */
- if (_TRUE == GET_RX_DESC_C2H(halmac_buf)) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "C2H packet, start parsing!\n");
-
- status = halmac_parse_c2h_packet_88xx(pHalmac_adapter, halmac_buf, halmac_size);
-
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_parse_c2h_packet_88xx error = %x\n", status);
- return status;
- }
- }
-
- /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_get_c2h_info_88xx <==========\n"); */
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_cfg_fwlps_option_88xx() -config FW LPS option
- * @pHalmac_adapter
- * @pLps_option : refer to HALMAC_FWLPS_OPTION structure
- * Author : KaiYuan Chang/Ivan Lin
- *
- * Used to config FW LPS option. If user has called this function,
- * halmac uses this setting to run FW LPS. If user never called this function,
- * halmac uses default setting to run FW LPS
- *
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_cfg_fwlps_option_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_FWLPS_OPTION pLps_option
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_FWLPS_OPTION pHal_fwlps_option;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_FWLPS_OPTION);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHal_fwlps_option = &(pHalmac_adapter->fwlps_option);
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_cfg_fwlps_option_88xx ==========>\n");
-
- pHal_fwlps_option->mode = pLps_option->mode;
- pHal_fwlps_option->clk_request = pLps_option->clk_request;
- pHal_fwlps_option->rlbm = pLps_option->rlbm;
- pHal_fwlps_option->smart_ps = pLps_option->smart_ps;
- pHal_fwlps_option->awake_interval = pLps_option->awake_interval;
- pHal_fwlps_option->all_queue_uapsd = pLps_option->all_queue_uapsd;
- pHal_fwlps_option->pwr_state = pLps_option->pwr_state;
- pHal_fwlps_option->low_pwr_rx_beacon = pLps_option->low_pwr_rx_beacon;
- pHal_fwlps_option->ant_auto_switch = pLps_option->ant_auto_switch;
- pHal_fwlps_option->ps_allow_bt_high_Priority = pLps_option->ps_allow_bt_high_Priority;
- pHal_fwlps_option->protect_bcn = pLps_option->protect_bcn;
- pHal_fwlps_option->silence_period = pLps_option->silence_period;
- pHal_fwlps_option->fast_bt_connect = pLps_option->fast_bt_connect;
- pHal_fwlps_option->two_antenna_en = pLps_option->two_antenna_en;
- pHal_fwlps_option->adopt_user_Setting = pLps_option->adopt_user_Setting;
- pHal_fwlps_option->drv_bcn_early_shift = pLps_option->drv_bcn_early_shift;
- pHal_fwlps_option->enter_32K = pLps_option->enter_32K;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_cfg_fwlps_option_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_cfg_fwips_option_88xx() -config FW IPS option
- * @pHalmac_adapter
- * @pIps_option : refer to HALMAC_FWIPS_OPTION structure
- * Author : KaiYuan Chang/Ivan Lin
- *
- * Used to config FW IPS option. If user has called this function,
- * halmac uses this setting to run FW IPS. If user never called this function,
- * halmac uses default setting to run FW IPS
- *
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_cfg_fwips_option_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_FWIPS_OPTION pIps_option
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_FWIPS_OPTION pIps_option_local;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_FWIPS_OPTION);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_cfg_fwips_option_88xx ==========>\n");
-
- pIps_option_local = pIps_option;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_cfg_fwips_option_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_enter_wowlan_88xx() - enter wowlan
- * @pHalmac_adapter
- * @pWowlan_option
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_enter_wowlan_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_WOWLAN_OPTION pWowlan_option
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_WOWLAN_OPTION pWowlan_option_local;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_ENTER_WOWLAN);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_enter_wowlan_88xx ==========>\n");
-
- pWowlan_option_local = pWowlan_option;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_enter_wowlan_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_leave_wowlan_88xx() - leave wowlan
- * @pHalmac_adapter
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_leave_wowlan_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-)
-{
- VOID *pDriver_adapter = NULL;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_LEAVE_WOWLAN);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_leave_wowlan_88xx ==========>\n");
-
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_leave_wowlan_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_enter_ps_88xx() - enter power saving state
- * @pHalmac_adapter
- * @ps_state
- *
- * If user has called halmac_cfg_fwlps_option or
- * halmac_cfg_fwips_option, halmac uses the specified setting.
- * Otherwise, halmac uses default setting.
- *
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_enter_ps_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_PS_STATE ps_state
-)
-{
- u8 rpwm;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter))
- return HALMAC_RET_NO_DLFW;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_ENTER_PS);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_enter_ps_88xx ==========>\n");
-
- if (ps_state == pHalmac_adapter->halmac_state.ps_state) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "power state is already in PS State!!\n");
- return HALMAC_RET_SUCCESS;
- }
-
- if (HALMAC_PS_STATE_LPS == ps_state) {
- status = halmac_send_h2c_set_pwr_mode_88xx(pHalmac_adapter, &(pHalmac_adapter->fwlps_option));
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "halmac_send_h2c_set_pwr_mode_88xx error = %x!!\n", status);
- return status;
- }
- } else if (HALMAC_PS_STATE_IPS == ps_state) {
- }
-
- pHalmac_adapter->halmac_state.ps_state = ps_state;
-
- /* Enter 32K */
- if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface) {
- if (_TRUE == pHalmac_adapter->fwlps_option.enter_32K) {
- rpwm = (u8)(((pHalmac_adapter->rpwm_record ^ (BIT(7))) | (BIT(0))) & 0x81);
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SDIO_HRPWM1, rpwm);
- pHalmac_adapter->low_clk = _TRUE;
- }
- } else if (HALMAC_INTERFACE_USB == pHalmac_adapter->halmac_interface) {
- if (_TRUE == pHalmac_adapter->fwlps_option.enter_32K) {
- rpwm = (u8)(((pHalmac_adapter->rpwm_record ^ (BIT(7))) | (BIT(0))) & 0x81);
- HALMAC_REG_WRITE_8(pHalmac_adapter, 0xFE58, rpwm);
- pHalmac_adapter->low_clk = _TRUE;
- }
- }
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_enter_ps_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_leave_ps_88xx() - leave power saving state
- * @pHalmac_adapter
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_leave_ps_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-)
-{
- u8 rpwm, cpwm;
- u32 counter;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
- HALMAC_FWLPS_OPTION fw_lps_option;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter))
- return HALMAC_RET_NO_DLFW;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_LEAVE_PS);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_leave_ps_88xx ==========>\n");
-
- if (HALMAC_PS_STATE_ACT == pHalmac_adapter->halmac_state.ps_state) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "power state is already in active!!\n");
- return HALMAC_RET_SUCCESS;
- }
-
- if (_TRUE == pHalmac_adapter->low_clk) {
- cpwm = HALMAC_REG_READ_8(pHalmac_adapter, REG_SDIO_HRPWM1);
- rpwm = (u8)(((pHalmac_adapter->rpwm_record ^ (BIT(7))) | (BIT(6))) & 0xC0);
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SDIO_HRPWM1, rpwm);
-
- cpwm = (u8)((cpwm ^ BIT(7)) & BIT(7));
- counter = 100;
- while (cpwm != (HALMAC_REG_READ_8(pHalmac_adapter, REG_SDIO_HRPWM1) & BIT(7))) {
- PLATFORM_RTL_DELAY_US(pDriver_adapter, 50);
- counter--;
- if (0 == counter)
- return HALMAC_RET_CHANGE_PS_FAIL;
- }
- pHalmac_adapter->low_clk = _FALSE;
- }
-
- PLATFORM_RTL_MEMCPY(pDriver_adapter, &fw_lps_option, &(pHalmac_adapter->fwlps_option), sizeof(HALMAC_FWLPS_OPTION));
- fw_lps_option.mode = 0;
-
- status = halmac_send_h2c_set_pwr_mode_88xx(pHalmac_adapter, &(fw_lps_option));
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "halmac_send_h2c_set_pwr_mode_88xx error!!=%x\n", status);
- return status;
- }
-
- pHalmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_ACT;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_leave_ps_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_h2c_lb_88xx() - send h2c loopback packet
- * @pHalmac_adapter
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_h2c_lb_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-)
-{
- VOID *pDriver_adapter = NULL;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_H2C_LB);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_h2c_lb_88xx ==========>\n");
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_h2c_lb_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_debug_88xx() - read some registers for debug
- * @pHalmac_adapter
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_debug_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-)
-{
- u8 temp8 = 0;
- u32 i = 0, temp32 = 0;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DEBUG);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug_88xx ==========>\n");
-
- if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface) {
- /* Dump CCCR, it needs new platform api */
-
- /*Dump SDIO Local Register, use CMD52*/
- for (i = 0x10250000; i < 0x102500ff; i++) {
- temp8 = PLATFORM_SDIO_CMD52_READ(pHalmac_adapter, i);
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: sdio[%x]=%x\n", i, temp8);
- }
-
- /*Dump MAC Register*/
- for (i = 0x0000; i < 0x17ff; i++) {
- temp8 = PLATFORM_SDIO_CMD52_READ(pHalmac_adapter, i);
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp8);
- }
-
- /*Check RX Fifo status*/
- i = REG_RXFF_PTR_V1;
- temp8 = PLATFORM_SDIO_CMD52_READ(pHalmac_adapter, i);
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp8);
- i = REG_RXFF_WTR_V1;
- temp8 = PLATFORM_SDIO_CMD52_READ(pHalmac_adapter, i);
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp8);
- i = REG_RXFF_PTR_V1;
- temp8 = PLATFORM_SDIO_CMD52_READ(pHalmac_adapter, i);
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp8);
- i = REG_RXFF_WTR_V1;
- temp8 = PLATFORM_SDIO_CMD52_READ(pHalmac_adapter, i);
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp8);
- } else {
- /*Dump MAC Register*/
- for (i = 0x0000; i < 0x17fc; i += 4) {
- temp32 = HALMAC_REG_READ_32(pHalmac_adapter, i);
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp32);
- }
-
- /*Check RX Fifo status*/
- i = REG_RXFF_PTR_V1;
- temp32 = HALMAC_REG_READ_32(pHalmac_adapter, i);
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp32);
- i = REG_RXFF_WTR_V1;
- temp32 = HALMAC_REG_READ_32(pHalmac_adapter, i);
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp32);
- i = REG_RXFF_PTR_V1;
- temp32 = HALMAC_REG_READ_32(pHalmac_adapter, i);
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp32);
- i = REG_RXFF_WTR_V1;
- temp32 = HALMAC_REG_READ_32(pHalmac_adapter, i);
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp32);
- }
-
- /* TODO: Add check register code, including MAC CLK, CPU CLK */
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_cfg_parameter_88xx() - config register with register array
- * @pHalmac_adapter
- * @para_info : cmd id, content
- * @full_fifo
- *
- * If msk_en = _TRUE, the format of array is {reg_info, mask, value}.
- * If msk_en =_FAUSE, the format of array is {reg_info, value}
- * The format of reg_info is
- * reg_info[31]=rf_reg, 0: MAC_BB reg, 1: RF reg
- * reg_info[27:24]=rf_path, 0: path_A, 1: path_B
- * if rf_reg=0(MAC_BB reg), rf_path is meaningless.
- * ref_info[15:0]=offset
- *
- * Example: msk_en = _FALSE
- * {0x8100000a, 0x00001122}
- * =>Set RF register, path_B, offset 0xA to 0x00001122
- * {0x00000824, 0x11224433}
- * =>Set MAC_BB register, offset 0x800 to 0x11224433
- *
- * Note : full fifo mode only for init flow
- *
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_cfg_parameter_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_PHY_PARAMETER_INFO para_info,
- IN u8 full_fifo
-)
-{
- VOID *pDriver_adapter = NULL;
- HALMAC_RET_STATUS ret_status = HALMAC_RET_SUCCESS;
- HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.cfg_para_state_set.process_status);
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter))
- return HALMAC_RET_NO_DLFW;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_PARAMETER);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_parameter_88xx ==========>\n"); */
-
- if (HALMAC_DLFW_NONE == pHalmac_adapter->halmac_state.dlfw_state) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_cfg_parameter_88xx Fail due to DLFW NONE!!\n");
- return HALMAC_RET_DLFW_FAIL;
- }
-
- if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(cfg para)...\n");
- return HALMAC_RET_BUSY_STATE;
- }
-
- if ((HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE != halmac_query_cfg_para_curr_state_88xx(pHalmac_adapter)) &&
- (HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING != halmac_query_cfg_para_curr_state_88xx(pHalmac_adapter))) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(cfg para)...\n");
- return HALMAC_RET_BUSY_STATE;
- }
-
- *pProcess_status = HALMAC_CMD_PROCESS_IDLE;
-
- ret_status = halmac_send_h2c_phy_parameter_88xx(pHalmac_adapter, para_info, full_fifo);
-
- if (HALMAC_RET_SUCCESS != ret_status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_phy_parameter_88xx Fail!! = %x\n", ret_status);
- return ret_status;
- }
-
- /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_parameter_88xx <==========\n"); */
-
- return ret_status;
-}
-
-/**
- * halmac_update_packet_88xx() - send some specified packet to FW
- * @pHalmac_adapter
- * @pkt_id : probe request, sync beacon, discovery beacon
- * @pkt
- * @pkt_size
- *
- * Send new specified packet to FW.
- * Note : TX_DESC is not included in the @pkt
- *
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_update_packet_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_PACKET_ID pkt_id,
- IN u8 *pkt,
- IN u32 pkt_size
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
- HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.update_packet_set.process_status);
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter))
- return HALMAC_RET_NO_DLFW;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_UPDATE_PACKET);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_update_packet_88xx ==========>\n");
-
- if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(update_packet)...\n");
- return HALMAC_RET_BUSY_STATE;
- }
-
- *pProcess_status = HALMAC_CMD_PROCESS_SENDING;
-
- status = halmac_send_h2c_update_packet_88xx(pHalmac_adapter, pkt_id, pkt, pkt_size);
-
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_update_packet_88xx packet = %x, fail = %x!!\n", pkt_id, status);
- return status;
- }
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_update_packet_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_bcn_ie_filter_88xx() - filter beacon & probe response
- * @pHalmac_adapter
- * @pBcn_ie_info
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_bcn_ie_filter_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_BCN_IE_INFO pBcn_ie_info
-)
-{
- VOID *pDriver_adapter = NULL;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter))
- return HALMAC_RET_NO_DLFW;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_BCN_IE_FILTER);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_bcn_ie_filter_88xx ==========>\n");
-
- status = halmac_send_h2c_update_bcn_parse_info_88xx(pHalmac_adapter, pBcn_ie_info);
-
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_update_bcn_parse_info_88xx fail = %x\n", status);
- return status;
- }
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_bcn_ie_filter_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_update_datapack_88xx() -
- * @pHalmac_adapter
- * @halmac_data_type
- * @para_info
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_update_datapack_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_DATA_TYPE halmac_data_type,
- IN PHALMAC_PHY_PARAMETER_INFO para_info
-)
-{
- VOID *pDriver_adapter = NULL;
- HALMAC_RET_STATUS ret_status = HALMAC_RET_SUCCESS;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter))
- return HALMAC_RET_NO_DLFW;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_UPDATE_DATAPACK);
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_update_datapack_88xx ==========>\n");
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- /* ret_status = halmac_send_h2c_update_datapack_88xx(pHalmac_adapter, halmac_data_type, para_info); */
-
- if (HALMAC_RET_SUCCESS != ret_status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_update_datapack_88xx Fail, datatype = %x, status = %x\n", halmac_data_type, ret_status);
- return ret_status;
- }
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_update_datapack_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_run_datapack_88xx() -
- * @pHalmac_adapter
- * @halmac_data_type
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_run_datapack_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_DATA_TYPE halmac_data_type
-)
-{
- VOID *pDriver_adapter = NULL;
- HALMAC_RET_STATUS ret_status = HALMAC_RET_SUCCESS;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter))
- return HALMAC_RET_NO_DLFW;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_RUN_DATAPACK);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_run_datapack_88xx ==========>\n");
-
- ret_status = halmac_send_h2c_run_datapack_88xx(pHalmac_adapter, halmac_data_type);
-
- if (HALMAC_RET_SUCCESS != ret_status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_run_datapack_88xx Fail, datatype = %x, status = %x!!\n", halmac_data_type, ret_status);
- return ret_status;
- }
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_update_datapack_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_cfg_drv_info_88xx() - config driver info
- * @pHalmac_adapter
- * @halmac_drv_info : none, phy status, phy sniffer, phy plcp
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_cfg_drv_info_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_DRV_INFO halmac_drv_info
-)
-{
- u8 drv_info_size = 0;
- u8 phy_status_en = 0;
- u8 sniffer_en = 0;
- u8 plcp_hdr_en = 0;
- u32 value32;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_DRV_INFO);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_drv_info_88xx ==========>\n");
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_drv_info = %d\n", halmac_drv_info);
-
- switch (halmac_drv_info) {
- case HALMAC_DRV_INFO_NONE:
- drv_info_size = 0;
- phy_status_en = 0;
- sniffer_en = 0;
- plcp_hdr_en = 0;
- break;
- case HALMAC_DRV_INFO_PHY_STATUS:
- drv_info_size = 4;
- phy_status_en = 1;
- sniffer_en = 0;
- plcp_hdr_en = 0;
- break;
- case HALMAC_DRV_INFO_PHY_SNIFFER:
- drv_info_size = 5; /* phy status 4byte, sniffer info 1byte */
- phy_status_en = 1;
- sniffer_en = 1;
- plcp_hdr_en = 0;
- break;
- case HALMAC_DRV_INFO_PHY_PLCP:
- drv_info_size = 6; /* phy status 4byte, plcp header 2byte */
- phy_status_en = 1;
- sniffer_en = 0;
- plcp_hdr_en = 1;
- break;
- default:
- status = HALMAC_RET_SW_CASE_NOT_SUPPORT;
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_cfg_drv_info_88xx error = %x\n", status);
- return status;
- }
-
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RX_DRVINFO_SZ, drv_info_size);
-
- value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_RCR);
- value32 = (value32 & (~BIT_APP_PHYSTS));
- if (1 == phy_status_en)
- value32 = value32 | BIT_APP_PHYSTS;
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RCR, value32);
-
- value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_WMAC_OPTION_FUNCTION + 4);
- value32 = (value32 & (~(BIT(8) | BIT(9))));
- if (1 == sniffer_en)
- value32 = value32 | BIT(9);
- if (1 == plcp_hdr_en)
- value32 = value32 | BIT(8);
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WMAC_OPTION_FUNCTION + 4, value32);
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_drv_info_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_send_bt_coex_88xx() -
- * @pHalmac_adapter
- * @pBt_buf
- * @bt_size
- * @ack
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_send_bt_coex_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pBt_buf,
- IN u32 bt_size,
- IN u8 ack
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
- HALMAC_RET_STATUS ret_status = HALMAC_RET_SUCCESS;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter))
- return HALMAC_RET_NO_DLFW;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_SEND_BT_COEX);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_bt_coex_88xx ==========>\n");
-
- ret_status = halmac_send_bt_coex_cmd_88xx(pHalmac_adapter, pBt_buf, bt_size, ack);
-
- if (HALMAC_RET_SUCCESS != ret_status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_bt_coex_cmd_88xx Fail = %x!!\n", ret_status);
- return ret_status;
- }
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_bt_coex_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_verify_platform_api_88xx() - verify platform api
- * @pHalmac_adapter
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_verify_platform_api_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-)
-{
- VOID *pDriver_adapter = NULL;
- HALMAC_RET_STATUS ret_status = HALMAC_RET_SUCCESS;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_VERIFY_PLATFORM_API);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_verify_platform_api_88xx ==========>\n");
-
- ret_status = halmac_verify_io_88xx(pHalmac_adapter);
-
- if (HALMAC_RET_SUCCESS != ret_status)
- return ret_status;
-
- if (HALMAC_LA_MODE_FULL != pHalmac_adapter->txff_allocation.la_mode)
- ret_status = halmac_verify_send_rsvd_page_88xx(pHalmac_adapter);
-
- if (HALMAC_RET_SUCCESS != ret_status)
- return ret_status;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_verify_platform_api_88xx <==========\n");
-
- return ret_status;
-}
-
-/**
- * halmac_send_original_h2c_88xx() - send original format h2c packet
- * @pHalmac_adapter
- * @original_h2c
- * @seq
- * @ack
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_send_original_h2c_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *original_h2c,
- IN u16 *seq,
- IN u8 ack
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter))
- return HALMAC_RET_NO_DLFW;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_SEND_ORIGINAL_H2C);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_original_h2c_88xx ==========>\n");
-
- status = halmac_func_send_original_h2c_88xx(pHalmac_adapter, original_h2c, seq, ack);
-
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_original_h2c FAIL = %x!!\n", status);
- return status;
- }
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_original_h2c_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_timer_2s_88xx() - periodic operation
- * @pHalmac_adapter
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_timer_2s_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-)
-{
- VOID *pDriver_adapter = NULL;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_timer_2s_88xx ==========>\n");
-
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_timer_2s_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_fill_txdesc_check_sum_88xx() - fill in tx desc check sum
- * @pHalmac_adapter
- * @pCur_desc
- *
- * User input tx descriptor, halmac output tx descriptor check sum
- *
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_fill_txdesc_check_sum_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- INOUT u8 *pCur_desc
-)
-{
- u16 chk_result = 0;
- u16 *pData = (u16 *)NULL;
- u32 i;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_FILL_TXDESC_CHECKSUM);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
-
- if (NULL == pCur_desc) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_fill_txdesc_check_sum_88xx NULL PTR");
- return HALMAC_RET_NULL_POINTER;
- }
-
- SET_TX_DESC_TXDESC_CHECKSUM(pCur_desc, 0x0000);
-
- pData = (u16 *)(pCur_desc);
-
- /* HW clculates only 32byte */
- for (i = 0; i < 8; i++)
- chk_result ^= (*(pData + 2 * i) ^ *(pData + (2 * i + 1)));
-
- SET_TX_DESC_TXDESC_CHECKSUM(pCur_desc, chk_result);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_dump_fifo_88xx() - dump fifo data
- * @pHalmac_adapter
- * @halmac_fifo_sel : tx, rx, rsvd page, report buff, llt
- * @pFifo_map
- * @halmac_fifo_dump_size
- *
- * Note : before dump fifo, user need to call halmac_get_fifo_size to
- * get fifo size. Then input this size to halmac_dump_fifo.
- *
- * Author : Ivan Lin/KaiYuan Chang
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_dump_fifo_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HAL_FIFO_SEL halmac_fifo_sel,
- OUT u8 *pFifo_map,
- IN u32 halmac_fifo_dump_size
-)
-{
- VOID *pDriver_adapter = NULL;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DUMP_FIFO);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_dump_fifo_88xx ==========>\n");
-
- if (HAL_FIFO_SEL_TX == halmac_fifo_sel && halmac_fifo_dump_size > pHalmac_adapter->hw_config_info.tx_fifo_size) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "TX fifo dump size is too large\n");
- return HALMAC_RET_DUMP_FIFOSIZE_INCORRECT;
- }
-
- if (HAL_FIFO_SEL_RX == halmac_fifo_sel && halmac_fifo_dump_size > pHalmac_adapter->hw_config_info.rx_fifo_size) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "RX fifo dump size is too large\n");
- return HALMAC_RET_DUMP_FIFOSIZE_INCORRECT;
- }
-
- if (0 != (halmac_fifo_dump_size & (4 - 1))) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_fifo_dump_size shall 4byte align\n");
- return HALMAC_RET_DUMP_FIFOSIZE_INCORRECT;
- }
-
- if (NULL == pFifo_map) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "pFifo_map address is NULL\n");
- return HALMAC_RET_NULL_POINTER;
- }
-
- status = halmac_buffer_read_88xx(pHalmac_adapter, 0x00, halmac_fifo_dump_size, halmac_fifo_sel, pFifo_map);
-
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_buffer_read_88xx error = %x\n", status);
- return status;
- }
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_dump_fifo_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_get_fifo_size_88xx() - get fifo size
- * @pHalmac_adapter
- * @halmac_fifo_sel : tx, rx, rsvd page, report buff, llt
- * Author : Ivan Lin/KaiYuan Chang
- * Return : fifo size
- */
-u32
-halmac_get_fifo_size_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HAL_FIFO_SEL halmac_fifo_sel
-)
-{
- u32 fifo_size = 0;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_GET_FIFO_SIZE);
-
- if (HAL_FIFO_SEL_TX == halmac_fifo_sel)
- fifo_size = pHalmac_adapter->hw_config_info.tx_fifo_size;
- else if (HAL_FIFO_SEL_RX == halmac_fifo_sel)
- fifo_size = pHalmac_adapter->hw_config_info.rx_fifo_size;
- else if (HAL_FIFO_SEL_RSVD_PAGE == halmac_fifo_sel)
- fifo_size = ((pHalmac_adapter->hw_config_info.tx_fifo_size >> 7) - pHalmac_adapter->txff_allocation.rsvd_pg_bndy) << 7;
- else if (HAL_FIFO_SEL_REPORT == halmac_fifo_sel)
- fifo_size = 65536;
- else if (HAL_FIFO_SEL_LLT == halmac_fifo_sel)
- fifo_size = 65536;
-
- return fifo_size;
-}
-
-/**
- * halmac_cfg_txbf_88xx() - enable/disable specific user's txbf
- * @pHalmac_adapter
- * Author : chunchu
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_cfg_txbf_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 userid,
- IN HALMAC_BW bw,
- IN u8 txbf_en
-)
-{
- u16 temp42C = 0;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_TXBF);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- if (txbf_en) {
- switch (bw) {
- case HALMAC_BW_80:
- temp42C |= BIT_R_TXBF0_80M;
- case HALMAC_BW_40:
- temp42C |= BIT_R_TXBF0_40M;
- case HALMAC_BW_20:
- temp42C |= BIT_R_TXBF0_20M;
- break;
- default:
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_cfg_txbf_88xx invalid TXBF BW setting 0x%x of userid %d\n", bw, userid);
- return HALMAC_RET_INVALID_SOUNDING_SETTING;
- }
- }
-
- switch (userid) {
- case 0:
- temp42C |= HALMAC_REG_READ_16(pHalmac_adapter, REG_TXBF_CTRL) & ~(BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M);
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TXBF_CTRL, temp42C);
- break;
- case 1:
- temp42C |= HALMAC_REG_READ_16(pHalmac_adapter, REG_TXBF_CTRL + 2) & ~(BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M);
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TXBF_CTRL + 2, temp42C);
- break;
- default:
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_cfg_txbf_88xx invalid userid %d\n", userid);
- return HALMAC_RET_INVALID_SOUNDING_SETTING;
- }
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_cfg_txbf_88xx, txbf_en = %x <==========\n", txbf_en);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_cfg_mumimo_88xx() -
- * @pHalmac_adapter
- * Author : chunchu
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_cfg_mumimo_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_CFG_MUMIMO_PARA pCfgmu
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
- u8 i, idx, id0, id1, gid, mu_tab_sel;
- u8 mu_tab_valid = 0;
- u32 gid_valid[6] = {0};
- u8 temp14C0 = 0;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_MUMIMO);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- if (pCfgmu->role == HAL_BFEE) {
- /*config MU BFEE*/
- temp14C0 = HALMAC_REG_READ_8(pHalmac_adapter, REG_MU_TX_CTL) & ~BIT_MASK_R_MU_TABLE_VALID;
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MU_TX_CTL, (temp14C0|BIT(0)|BIT(1)) & ~(BIT(7))); /*enable MU table 0 and 1, disable MU TX*/
-
- /*config GID valid table and user position table*/
- mu_tab_sel = HALMAC_REG_READ_8(pHalmac_adapter, REG_MU_TX_CTL+1) & ~(BIT(0)|BIT(1)|BIT(2));
- for (i = 0; i < 2; i++) {
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MU_TX_CTL+1, mu_tab_sel | i);
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MU_STA_GID_VLD, pCfgmu->given_gid_tab[i]);
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MU_STA_USER_POS_INFO, pCfgmu->given_user_pos[i*2]);
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MU_STA_USER_POS_INFO+4, pCfgmu->given_user_pos[i*2+1]);
- }
- } else {
- /*config MU BFER*/
- if (_FALSE == pCfgmu->mu_tx_en) {
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MU_TX_CTL, HALMAC_REG_READ_8(pHalmac_adapter, REG_MU_TX_CTL) & ~(BIT(7)));
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_cfg_mumimo_88xx disable mu tx <==========\n");
- return HALMAC_RET_SUCCESS;
- }
-
- /*Transform BB grouping bitmap[14:0] to MAC GID_valid table*/
- for (idx = 0; idx < 15; idx++) {
- if (idx < 5) {
- /*grouping_bitmap bit0~4, MU_STA0 with MUSTA1~5*/
- id0 = 0;
- id1 = (u8)(idx + 1);
- } else if (idx < 9) {
- /*grouping_bitmap bit5~8, MU_STA1 with MUSTA2~5*/
- id0 = 1;
- id1 = (u8)(idx - 3);
- } else if (idx < 12) {
- /*grouping_bitmap bit9~11, MU_STA2 with MUSTA3~5*/
- id0 = 2;
- id1 = (u8)(idx - 6);
- } else if (idx < 14) {
- /*grouping_bitmap bit12~13, MU_STA3 with MUSTA4~5*/
- id0 = 3;
- id1 = (u8)(idx - 8);
- } else {
- /*grouping_bitmap bit14, MU_STA4 with MUSTA5*/
- id0 = 4;
- id1 = (u8)(idx - 9);
- }
- if (pCfgmu->grouping_bitmap & BIT(idx)) {
- /*Pair 1*/
- gid = (idx << 1) + 1;
- gid_valid[id0] |= (BIT(gid));
- gid_valid[id1] |= (BIT(gid));
- /*Pair 2*/
- gid += 1;
- gid_valid[id0] |= (BIT(gid));
- gid_valid[id1] |= (BIT(gid));
- } else {
- /*Pair 1*/
- gid = (idx << 1) + 1;
- gid_valid[id0] &= ~(BIT(gid));
- gid_valid[id1] &= ~(BIT(gid));
- /*Pair 2*/
- gid += 1;
- gid_valid[id0] &= ~(BIT(gid));
- gid_valid[id1] &= ~(BIT(gid));
- }
- }
-
- /*set MU STA GID valid TABLE*/
- mu_tab_sel = HALMAC_REG_READ_8(pHalmac_adapter, REG_MU_TX_CTL+1) & ~(BIT(0)|BIT(1)|BIT(2));
- for (idx = 0; idx < 6; idx++) {
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MU_TX_CTL+1, idx | mu_tab_sel);
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MU_STA_GID_VLD, gid_valid[idx]);
- }
-
- /*To validate the sounding successful MU STA and enable MU TX*/
- for (i = 0; i < 6; i++) {
- if (_TRUE == pCfgmu->sounding_sts[i])
- mu_tab_valid |= BIT(i);
- }
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MU_TX_CTL, mu_tab_valid | BIT(7));
- }
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_cfg_mumimo_88xx <==========\n");
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_cfg_sounding_88xx() - set general sounding control registers
- * @pHalmac_adapter
- * Author : chunchu
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_cfg_sounding_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_SND_ROLE role,
- IN HALMAC_DATA_RATE datarate
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_SOUNDING);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- switch (role) {
- case HAL_BFER:
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_TXBF_CTRL, HALMAC_REG_READ_32(pHalmac_adapter, REG_TXBF_CTRL) | BIT_R_ENABLE_NDPA
- | BIT_USE_NDPA_PARAMETER | BIT_R_EN_NDPA_INT | BIT_DIS_NDP_BFEN);
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_NDPA_RATE, datarate);
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_NDPA_OPT_CTRL, HALMAC_REG_READ_8(pHalmac_adapter, REG_NDPA_OPT_CTRL) & (~(BIT(0) | BIT(1))));
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SND_PTCL_CTRL + 1, 0x2);
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SND_PTCL_CTRL + 2, 0x2);
- break;
- case HAL_BFEE:
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SND_PTCL_CTRL, 0xDB);
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SND_PTCL_CTRL + 3, 0x50);
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BBPSF_CTRL + 3, datarate);
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RRSR, HALMAC_REG_READ_16(pHalmac_adapter, REG_RRSR) | BIT(datarate));
- break;
- default:
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_cfg_sounding_88xx invalid role \n");
- return HALMAC_RET_INVALID_SOUNDING_SETTING;
- }
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_cfg_sounding_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_del_sounding_88xx() - reset general sounding control registers
- * @pHalmac_adapter
- * Author : chunchu
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_del_sounding_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_SND_ROLE role
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DEL_SOUNDING);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- switch (role) {
- case HAL_BFER:
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXBF_CTRL + 3, 0);
- break;
- case HAL_BFEE:
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SND_PTCL_CTRL, 0);
- break;
- default:
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_del_sounding_88xx invalid role \n");
- return HALMAC_RET_INVALID_SOUNDING_SETTING;
- }
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_del_sounding_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_su_bfee_entry_init_88xx() - config SU beamformee's registers
- * @pHalmac_adapter
- * Author : chunchu
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_su_bfee_entry_init_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 userid,
- IN u16 paid
-)
-{
- u16 temp42C = 0;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_SU_BFEE_ENTRY_INIT);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- switch (userid) {
- case 0:
- temp42C = HALMAC_REG_READ_16(pHalmac_adapter, REG_TXBF_CTRL) & ~(BIT_MASK_R_TXBF0_AID | BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M);
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TXBF_CTRL, temp42C | paid);
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_ASSOCIATED_BFMEE_SEL + 3, 0x60);
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMEE_SEL, paid | BIT(9));
- break;
- case 1:
- temp42C = HALMAC_REG_READ_16(pHalmac_adapter, REG_TXBF_CTRL + 2) & ~(BIT_MASK_R_TXBF1_AID | BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M);
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TXBF_CTRL + 2, temp42C | paid);
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMEE_SEL + 2, paid | BIT(9) | 0xe000);
- break;
- default:
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_su_bfee_entry_init_88xx invalid userid %d \n", userid);
- return HALMAC_RET_INVALID_SOUNDING_SETTING;
- }
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_su_bfee_entry_init_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_su_bfee_entry_init_88xx() - config SU beamformer's registers
- * @pHalmac_adapter
- * Author : chunchu
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_su_bfer_entry_init_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_SU_BFER_INIT_PARA pSu_bfer_init
-)
-{
- u16 mac_address_H;
- u32 mac_address_L;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_SU_BFER_ENTRY_INIT);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- /* mac_address_L = bfer_address.Address_L_H.Address_Low; */
- /* mac_address_H = bfer_address.Address_L_H.Address_High; */
-
- mac_address_L = rtk_le32_to_cpu(pSu_bfer_init->pbfer_address->Address_L_H.Address_Low);
- mac_address_H = rtk_le16_to_cpu(pSu_bfer_init->pbfer_address->Address_L_H.Address_High);
-
- switch (pSu_bfer_init->userid) {
- case 0:
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO, mac_address_L);
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO + 4, mac_address_H);
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO + 6, pSu_bfer_init->paid);
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TX_CSI_RPT_PARAM_BW20, pSu_bfer_init->csi_para);
- break;
- case 1:
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_ASSOCIATED_BFMER1_INFO, mac_address_L);
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMER1_INFO + 4, mac_address_H);
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMER1_INFO + 6, pSu_bfer_init->paid);
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TX_CSI_RPT_PARAM_BW20 + 2, pSu_bfer_init->csi_para);
- break;
- default:
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_su_bfer_entry_init_88xx invalid userid %d\n", pSu_bfer_init->userid);
- return HALMAC_RET_INVALID_SOUNDING_SETTING;
- }
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_su_bfer_entry_init_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_mu_bfee_entry_init_88xx() - config MU beamformee's registers
- * @pHalmac_adapter
- * Author : chunchu
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_mu_bfee_entry_init_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_MU_BFEE_INIT_PARA pMu_bfee_init
-)
-{
- u16 temp168X = 0, temp14C0;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_MU_BFEE_ENTRY_INIT);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- temp168X |= pMu_bfee_init->paid | BIT(9);
- HALMAC_REG_WRITE_16(pHalmac_adapter, (0x1680 + pMu_bfee_init->userid * 2), temp168X);
-
- temp14C0 = HALMAC_REG_READ_16(pHalmac_adapter, REG_MU_TX_CTL) & ~(BIT(8)|BIT(9)|BIT(10));
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MU_TX_CTL, temp14C0|((pMu_bfee_init->userid-2)<<8));
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MU_STA_GID_VLD, 0);
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MU_STA_USER_POS_INFO, pMu_bfee_init->user_position_l);
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MU_STA_USER_POS_INFO+4, pMu_bfee_init->user_position_h);
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_mu_bfee_entry_init_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_mu_bfer_entry_init_88xx() - config SU beamformer's registers
- * @pHalmac_adapter
- * Author : chunchu
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_mu_bfer_entry_init_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_MU_BFER_INIT_PARA pMu_bfer_init
-)
-{
- u16 temp1680 = 0;
- u16 mac_address_H;
- u32 mac_address_L;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_MU_BFER_ENTRY_INIT);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- /* mac_address_L = pHalmac_adapter->snd_info.bfer_address.Address_L_H.Address_Low; */
- /* mac_address_H = pHalmac_adapter->snd_info.bfer_address.Address_L_H.Address_High; */
-
- mac_address_L = rtk_le32_to_cpu(pMu_bfer_init->pbfer_address->Address_L_H.Address_Low);
- mac_address_H = rtk_le16_to_cpu(pMu_bfer_init->pbfer_address->Address_L_H.Address_High);
-
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO, mac_address_L);
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO + 4, mac_address_H);
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO + 6, pMu_bfer_init->paid);
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TX_CSI_RPT_PARAM_BW20, pMu_bfer_init->csi_para);
-
- temp1680 = HALMAC_REG_READ_16(pHalmac_adapter, 0x1680) & 0xC000;
- temp1680 |= pMu_bfer_init->my_aid | (pMu_bfer_init->csi_length_sel << 12);
- HALMAC_REG_WRITE_16(pHalmac_adapter, 0x1680, temp1680);
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_mu_bfer_entry_init_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_su_bfee_entry_del_88xx() - reset SU beamformee's registers
- * @pHalmac_adapter
- * Author : chunchu
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_su_bfee_entry_del_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 userid
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_SU_BFEE_ENTRY_DEL);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- switch (userid) {
- case 0:
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TXBF_CTRL, HALMAC_REG_READ_16(pHalmac_adapter, REG_TXBF_CTRL) & \
- ~(BIT_MASK_R_TXBF0_AID | BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M));
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMEE_SEL, 0);
- break;
- case 1:
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TXBF_CTRL + 2, HALMAC_REG_READ_16(pHalmac_adapter, REG_TXBF_CTRL + 2) & \
- ~(BIT_MASK_R_TXBF1_AID | BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M));
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMEE_SEL + 2, 0);
- break;
- default:
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_su_bfee_entry_del_88xx invalid userid %d\n", userid);
- return HALMAC_RET_INVALID_SOUNDING_SETTING;
- }
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_su_bfee_entry_del_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_su_bfee_entry_del_88xx() - reset SU beamformer's registers
- * @pHalmac_adapter
- * Author : chunchu
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_su_bfer_entry_del_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 userid
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_SU_BFER_ENTRY_DEL);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- switch (userid) {
- case 0:
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO, 0);
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO + 4, 0);
- break;
- case 1:
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_ASSOCIATED_BFMER1_INFO, 0);
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_ASSOCIATED_BFMER1_INFO + 4, 0);
- break;
- default:
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_su_bfer_entry_del_88xx invalid userid %d\n", userid);
- return HALMAC_RET_INVALID_SOUNDING_SETTING;
- }
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_su_bfer_entry_del_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_mu_bfee_entry_del_88xx() - reset MU beamformee's registers
- * @pHalmac_adapter
- * Author : chunchu
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_mu_bfee_entry_del_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 userid
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_MU_BFEE_ENTRY_DEL);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- HALMAC_REG_WRITE_16(pHalmac_adapter, 0x1680 + userid * 2, 0);
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MU_TX_CTL, HALMAC_REG_READ_8(pHalmac_adapter, REG_MU_TX_CTL) & ~(BIT(userid-2)));
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_mu_bfee_entry_del_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_mu_bfer_entry_del_88xx() -reset MU beamformer's registers
- * @pHalmac_adapter
- * Author : chunchu
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_mu_bfer_entry_del_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_MU_BFER_ENTRY_DEL);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO, 0);
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO + 4, 0);
- HALMAC_REG_WRITE_16(pHalmac_adapter, 0x1680, 0);
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MU_TX_CTL, 0);
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_mu_bfer_entry_del_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_add_ch_info_88xx() -used to construct channel info
- * @pHalmac_adapter
- * @pCh_info
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_add_ch_info_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_CH_INFO pCh_info
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_CS_INFO pCh_sw_info;
- HALMAC_SCAN_CMD_CONSTRUCT_STATE state_scan;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_ADD_CH_INFO);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pCh_sw_info = &(pHalmac_adapter->ch_sw_info);
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_add_ch_info_88xx ==========>\n");
-
- if (HALMAC_GEN_INFO_SENT != pHalmac_adapter->halmac_state.dlfw_state) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_add_ch_info_88xx: gen_info is not send to FW!!!!\n");
- return HALMAC_RET_GEN_INFO_NOT_SENT;
- }
-
- state_scan = halmac_query_scan_curr_state_88xx(pHalmac_adapter);
- if ((HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED != state_scan) && (HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING != state_scan)) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Scan machine fail(add ch info)...\n");
- return HALMAC_RET_ERROR_STATE;
- }
-
- if (NULL == pCh_sw_info->ch_info_buf) {
- pCh_sw_info->ch_info_buf = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, HALMAC_EXTRA_INFO_BUFF_SIZE_88XX);
- pCh_sw_info->ch_info_buf_w = pCh_sw_info->ch_info_buf;
- pCh_sw_info->buf_size = HALMAC_EXTRA_INFO_BUFF_SIZE_88XX;
- pCh_sw_info->avai_buf_size = HALMAC_EXTRA_INFO_BUFF_SIZE_88XX;
- pCh_sw_info->total_size = 0;
- pCh_sw_info->extra_info_en = 0;
- pCh_sw_info->ch_num = 0;
- }
-
- if (1 == pCh_sw_info->extra_info_en) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_add_ch_info_88xx: construct sequence wrong!!\n");
- return HALMAC_RET_CH_SW_SEQ_WRONG;
- }
-
- if (4 > pCh_sw_info->avai_buf_size) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_add_ch_info_88xx: no availabe buffer!!\n");
- return HALMAC_RET_CH_SW_NO_BUF;
- }
-
- if (HALMAC_RET_SUCCESS != halmac_transition_scan_state_88xx(pHalmac_adapter, HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING))
- return HALMAC_RET_ERROR_STATE;
-
- CHANNEL_INFO_SET_CHANNEL(pCh_sw_info->ch_info_buf_w, pCh_info->channel);
- CHANNEL_INFO_SET_PRI_CH_IDX(pCh_sw_info->ch_info_buf_w, pCh_info->pri_ch_idx);
- CHANNEL_INFO_SET_BANDWIDTH(pCh_sw_info->ch_info_buf_w, pCh_info->bw);
- CHANNEL_INFO_SET_TIMEOUT(pCh_sw_info->ch_info_buf_w, pCh_info->timeout);
- CHANNEL_INFO_SET_ACTION_ID(pCh_sw_info->ch_info_buf_w, pCh_info->action_id);
- CHANNEL_INFO_SET_CH_EXTRA_INFO(pCh_sw_info->ch_info_buf_w, pCh_info->extra_info);
-
- pCh_sw_info->avai_buf_size = pCh_sw_info->avai_buf_size - 4;
- pCh_sw_info->total_size = pCh_sw_info->total_size + 4;
- pCh_sw_info->ch_num++;
- pCh_sw_info->extra_info_en = pCh_info->extra_info;
- pCh_sw_info->ch_info_buf_w = pCh_sw_info->ch_info_buf_w + 4;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_add_ch_info_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_add_extra_ch_info_88xx() -used to construct extra channel info
- * @pHalmac_adapter
- * @pCh_extra_info
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_add_extra_ch_info_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_CH_EXTRA_INFO pCh_extra_info
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_CS_INFO pCh_sw_info;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_ADD_EXTRA_CH_INFO);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pCh_sw_info = &(pHalmac_adapter->ch_sw_info);
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_add_extra_ch_info_88xx ==========>\n");
-
- if (NULL == pCh_sw_info->ch_info_buf) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_add_extra_ch_info_88xx: NULL==pCh_sw_info->ch_info_buf!!\n");
- return HALMAC_RET_CH_SW_SEQ_WRONG;
- }
-
- if (0 == pCh_sw_info->extra_info_en) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_add_extra_ch_info_88xx: construct sequence wrong!!\n");
- return HALMAC_RET_CH_SW_SEQ_WRONG;
- }
-
- if (pCh_sw_info->avai_buf_size < (u32)(pCh_extra_info->extra_info_size + 2)) {/* 2:ch_extra_info_id, ch_extra_info, ch_extra_info_size are totally 2Byte */
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_add_extra_ch_info_88xx: no availabe buffer!!\n");
- return HALMAC_RET_CH_SW_NO_BUF;
- }
-
- if (HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING != halmac_query_scan_curr_state_88xx(pHalmac_adapter)) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Scan machine fail(add extra ch info)...\n");
- return HALMAC_RET_ERROR_STATE;
- }
-
- if (HALMAC_RET_SUCCESS != halmac_transition_scan_state_88xx(pHalmac_adapter, HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING))
- return HALMAC_RET_ERROR_STATE;
-
- CH_EXTRA_INFO_SET_CH_EXTRA_INFO_ID(pCh_sw_info->ch_info_buf_w, pCh_extra_info->extra_action_id);
- CH_EXTRA_INFO_SET_CH_EXTRA_INFO(pCh_sw_info->ch_info_buf_w, pCh_extra_info->extra_info);
- CH_EXTRA_INFO_SET_CH_EXTRA_INFO_SIZE(pCh_sw_info->ch_info_buf_w, pCh_extra_info->extra_info_size);
- PLATFORM_RTL_MEMCPY(pDriver_adapter, pCh_sw_info->ch_info_buf_w + 2, pCh_extra_info->extra_info_data, pCh_extra_info->extra_info_size);
-
- pCh_sw_info->avai_buf_size = pCh_sw_info->avai_buf_size - (2 + pCh_extra_info->extra_info_size);
- pCh_sw_info->total_size = pCh_sw_info->total_size + (2 + pCh_extra_info->extra_info_size);
- pCh_sw_info->extra_info_en = pCh_extra_info->extra_info;
- pCh_sw_info->ch_info_buf_w = pCh_sw_info->ch_info_buf_w + (2 + pCh_extra_info->extra_info_size);
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_add_extra_ch_info_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_ctrl_ch_switch_88xx() -used to send channel switch cmd
- * @pHalmac_adapter
- * @pCs_option
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_ctrl_ch_switch_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_CH_SWITCH_OPTION pCs_option
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
- HALMAC_SCAN_CMD_CONSTRUCT_STATE state_scan;
- HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.scan_state_set.process_status);
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter))
- return HALMAC_RET_NO_DLFW;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CTRL_CH_SWITCH);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_ctrl_ch_switch_88xx pCs_option->switch_en = %d==========>\n", pCs_option->switch_en);
-
- if (_FALSE == pCs_option->switch_en)
- *pProcess_status = HALMAC_CMD_PROCESS_IDLE;
-
- if ((HALMAC_CMD_PROCESS_SENDING == *pProcess_status) || (HALMAC_CMD_PROCESS_RCVD == *pProcess_status)) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(ctrl ch switch)...\n");
- return HALMAC_RET_BUSY_STATE;
- }
-
- state_scan = halmac_query_scan_curr_state_88xx(pHalmac_adapter);
- if (_TRUE == pCs_option->switch_en) {
- if (HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING != state_scan) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_ctrl_ch_switch_88xx(on) invalid in state %x\n", state_scan);
- return HALMAC_RET_ERROR_STATE;
- }
- } else {
- if (HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED != state_scan) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_ctrl_ch_switch_88xx(off) invalid in state %x\n", state_scan);
- return HALMAC_RET_ERROR_STATE;
- }
- }
-
- status = halmac_func_ctrl_ch_switch_88xx(pHalmac_adapter, pCs_option);
-
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_ctrl_ch_switch FAIL = %x!!\n", status);
- return status;
- }
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_ctrl_ch_switch_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_clear_ch_info_88xx() -used to clear channel info
- * @pHalmac_adapter
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_clear_ch_info_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CLEAR_CH_INFO);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_clear_ch_info_88xx ==========>\n");
-
- if (HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT == halmac_query_scan_curr_state_88xx(pHalmac_adapter)) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Scan machine fail(clear ch info)...\n");
- return HALMAC_RET_ERROR_STATE;
- }
-
- if (HALMAC_RET_SUCCESS != halmac_transition_scan_state_88xx(pHalmac_adapter, HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED))
- return HALMAC_RET_ERROR_STATE;
-
- PLATFORM_RTL_FREE(pDriver_adapter, pHalmac_adapter->ch_sw_info.ch_info_buf, pHalmac_adapter->ch_sw_info.buf_size);
- pHalmac_adapter->ch_sw_info.ch_info_buf = NULL;
- pHalmac_adapter->ch_sw_info.ch_info_buf_w = NULL;
- pHalmac_adapter->ch_sw_info.extra_info_en = 0;
- pHalmac_adapter->ch_sw_info.buf_size = 0;
- pHalmac_adapter->ch_sw_info.avai_buf_size = 0;
- pHalmac_adapter->ch_sw_info.total_size = 0;
- pHalmac_adapter->ch_sw_info.ch_num = 0;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_clear_ch_info_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_send_general_info_88xx() -send general info
- * @pHalmac_adapter
- * @pGeneral_info
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_send_general_info_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_GENERAL_INFO pGeneral_info
-)
-{
- VOID *pDriver_adapter = NULL;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter))
- return HALMAC_RET_NO_DLFW;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_SEND_GENERAL_INFO);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_general_info_88xx ==========>\n");
-
- if (HALMAC_DLFW_NONE == pHalmac_adapter->halmac_state.dlfw_state) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_general_info_88xx Fail due to DLFW NONE!!\n");
- return HALMAC_RET_DLFW_FAIL;
- }
-
- status = halmac_func_send_general_info_88xx(pHalmac_adapter, pGeneral_info);
-
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_send_general_info error = %x\n", status);
- return status;
- }
-
- if (HALMAC_DLFW_DONE == pHalmac_adapter->halmac_state.dlfw_state)
- pHalmac_adapter->halmac_state.dlfw_state = HALMAC_GEN_INFO_SENT;
-
- pHalmac_adapter->gen_info_valid = _TRUE;
- PLATFORM_RTL_MEMCPY(pDriver_adapter, &(pHalmac_adapter->general_info), pGeneral_info, sizeof(HALMAC_GENERAL_INFO));
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_general_info_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_start_iqk_88xx() -start iqk
- * @pHalmac_adapter
- * @clear
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_start_iqk_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 clear
-)
-{
- u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 };
- u16 h2c_seq_num = 0;
- VOID *pDriver_adapter = NULL;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
- HALMAC_H2C_HEADER_INFO h2c_header_info;
- HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.iqk_set.process_status);
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter))
- return HALMAC_RET_NO_DLFW;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_START_IQK);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_start_iqk_88xx ==========>\n");
-
- if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(iqk)...\n");
- return HALMAC_RET_BUSY_STATE;
- }
-
- *pProcess_status = HALMAC_CMD_PROCESS_SENDING;
-
- IQK_SET_CLEAR(pH2c_buff, clear);
-
- h2c_header_info.sub_cmd_id = SUB_CMD_ID_IQK;
- h2c_header_info.content_size = 1;
- h2c_header_info.ack = _TRUE;
- halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_num);
-
- pHalmac_adapter->halmac_state.iqk_set.seq_num = h2c_seq_num;
-
- status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE);
-
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail = %x!!\n", status);
- return status;
- }
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_start_iqk_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_ctrl_pwr_tracking_88xx() -control power tracking
- * @pHalmac_adapter
- * @pPwr_tracking_opt
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_ctrl_pwr_tracking_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_PWR_TRACKING_OPTION pPwr_tracking_opt
-)
-{
- u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 };
- u16 h2c_seq_mum = 0;
- VOID *pDriver_adapter = NULL;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
- HALMAC_H2C_HEADER_INFO h2c_header_info;
- HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.power_tracking_set.process_status);
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter))
- return HALMAC_RET_NO_DLFW;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CTRL_PWR_TRACKING);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_start_iqk_88xx ==========>\n");
-
- if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(pwr tracking)...\n");
- return HALMAC_RET_BUSY_STATE;
- }
-
- *pProcess_status = HALMAC_CMD_PROCESS_SENDING;
-
- POWER_TRACKING_SET_TYPE(pH2c_buff, pPwr_tracking_opt->type);
- POWER_TRACKING_SET_BBSWING_INDEX(pH2c_buff, pPwr_tracking_opt->bbswing_index);
- POWER_TRACKING_SET_ENABLE_A(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_A].enable);
- POWER_TRACKING_SET_TX_PWR_INDEX_A(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_A].tx_pwr_index);
- POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_A(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_A].pwr_tracking_offset_value);
- POWER_TRACKING_SET_TSSI_VALUE_A(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_A].tssi_value);
- POWER_TRACKING_SET_ENABLE_B(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_B].enable);
- POWER_TRACKING_SET_TX_PWR_INDEX_B(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_B].tx_pwr_index);
- POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_B(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_B].pwr_tracking_offset_value);
- POWER_TRACKING_SET_TSSI_VALUE_B(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_B].tssi_value);
- POWER_TRACKING_SET_ENABLE_C(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_C].enable);
- POWER_TRACKING_SET_TX_PWR_INDEX_C(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_C].tx_pwr_index);
- POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_C(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_C].pwr_tracking_offset_value);
- POWER_TRACKING_SET_TSSI_VALUE_C(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_C].tssi_value);
- POWER_TRACKING_SET_ENABLE_D(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_D].enable);
- POWER_TRACKING_SET_TX_PWR_INDEX_D(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_D].tx_pwr_index);
- POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_D(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_D].pwr_tracking_offset_value);
- POWER_TRACKING_SET_TSSI_VALUE_D(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_D].tssi_value);
-
- h2c_header_info.sub_cmd_id = SUB_CMD_ID_POWER_TRACKING;
- h2c_header_info.content_size = 20;
- h2c_header_info.ack = _TRUE;
- halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum);
-
- pHalmac_adapter->halmac_state.power_tracking_set.seq_num = h2c_seq_mum;
-
- status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE);
-
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail = %x!!\n", status);
- return status;
- }
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_start_iqk_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_query_status_88xx() -query async feature status
- * @pHalmac_adapter
- * @feature_id
- * @pProcess_status
- * @data
- * @size
- *
- * Note :
- * If user wants to know the data size, use can allocate random
- * size buffer first. If this size less than the data size, halmac
- * will return HALMAC_RET_BUFFER_TOO_SMALL. User need to
- * re-allocate data buffer with correct data size.
- *
- * Author : Ivan Lin/KaiYuan Chang
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_query_status_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_FEATURE_ID feature_id,
- OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status,
- INOUT u8 *data,
- INOUT u32 *size
-)
-{
- VOID *pDriver_adapter = NULL;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_QUERY_STATE);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_query_status_88xx ==========>\n"); */
-
- if (NULL == pProcess_status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "null pointer!!\n");
- return HALMAC_RET_NULL_POINTER;
- }
-
- switch (feature_id) {
- case HALMAC_FEATURE_CFG_PARA:
- status = halmac_query_cfg_para_status_88xx(pHalmac_adapter, pProcess_status, data, size);
- break;
- case HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE:
- status = halmac_query_dump_physical_efuse_status_88xx(pHalmac_adapter, pProcess_status, data, size);
- break;
- case HALMAC_FEATURE_DUMP_LOGICAL_EFUSE:
- status = halmac_query_dump_logical_efuse_status_88xx(pHalmac_adapter, pProcess_status, data, size);
- break;
- case HALMAC_FEATURE_CHANNEL_SWITCH:
- status = halmac_query_channel_switch_status_88xx(pHalmac_adapter, pProcess_status, data, size);
- break;
- case HALMAC_FEATURE_UPDATE_PACKET:
- status = halmac_query_update_packet_status_88xx(pHalmac_adapter, pProcess_status, data, size);
- break;
- case HALMAC_FEATURE_IQK:
- status = halmac_query_iqk_status_88xx(pHalmac_adapter, pProcess_status, data, size);
- break;
- case HALMAC_FEATURE_POWER_TRACKING:
- status = halmac_query_power_tracking_status_88xx(pHalmac_adapter, pProcess_status, data, size);
- break;
- case HALMAC_FEATURE_PSD:
- status = halmac_query_psd_status_88xx(pHalmac_adapter, pProcess_status, data, size);
- break;
- default:
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_query_status_88xx invalid feature id %d\n", feature_id);
- return HALMAC_RET_INVALID_FEATURE_ID;
- }
-
- /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_query_status_88xx <==========\n"); */
-
- return status;
-}
-
-/**
- * halmac_reset_feature_88xx() -reset async feature status
- * @pHalmac_adapter
- * @feature_id
- * Author : Ivan Lin/KaiYuan Chang
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_reset_feature_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_FEATURE_ID feature_id
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_STATE pState = &(pHalmac_adapter->halmac_state);
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_RESET_FEATURE);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_reset_feature_88xx ==========>\n");
-
- switch (feature_id) {
- case HALMAC_FEATURE_CFG_PARA:
- pState->cfg_para_state_set.process_status = HALMAC_CMD_PROCESS_IDLE;
- pState->cfg_para_state_set.cfg_para_cmd_construct_state = HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE;
- break;
- case HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE:
- case HALMAC_FEATURE_DUMP_LOGICAL_EFUSE:
- pState->efuse_state_set.process_status = HALMAC_CMD_PROCESS_IDLE;
- pState->efuse_state_set.efuse_cmd_construct_state = HALMAC_EFUSE_CMD_CONSTRUCT_IDLE;
- break;
- case HALMAC_FEATURE_CHANNEL_SWITCH:
- pState->scan_state_set.process_status = HALMAC_CMD_PROCESS_IDLE;
- pState->scan_state_set.scan_cmd_construct_state = HALMAC_SCAN_CMD_CONSTRUCT_IDLE;
- break;
- case HALMAC_FEATURE_UPDATE_PACKET:
- pState->update_packet_set.process_status = HALMAC_CMD_PROCESS_IDLE;
- break;
- case HALMAC_FEATURE_ALL:
- pState->cfg_para_state_set.process_status = HALMAC_CMD_PROCESS_IDLE;
- pState->cfg_para_state_set.cfg_para_cmd_construct_state = HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE;
- pState->efuse_state_set.process_status = HALMAC_CMD_PROCESS_IDLE;
- pState->efuse_state_set.efuse_cmd_construct_state = HALMAC_EFUSE_CMD_CONSTRUCT_IDLE;
- pState->scan_state_set.process_status = HALMAC_CMD_PROCESS_IDLE;
- pState->scan_state_set.scan_cmd_construct_state = HALMAC_SCAN_CMD_CONSTRUCT_IDLE;
- pState->update_packet_set.process_status = HALMAC_CMD_PROCESS_IDLE;
- break;
- default:
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_reset_feature_88xx invalid feature id %d \n", feature_id);
- return HALMAC_RET_INVALID_FEATURE_ID;
- }
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_reset_feature_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_check_fw_status_88xx() -check fw status
- * @pHalmac_adapter
- * @fw_status
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_check_fw_status_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- OUT u8 *fw_status
-)
-{
- u32 value32 = 0, value32_backup = 0, i = 0;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CHECK_FW_STATUS);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_check_fw_status_88xx ==========>\n");
-
- value32 = PLATFORM_REG_READ_32(pDriver_adapter, REG_FW_DBG6);
-
- if (0 != value32) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_check_fw_status REG_FW_DBG6 !=0\n");
- *fw_status = _FALSE;
- return status;
- }
-
- value32_backup = PLATFORM_REG_READ_32(pDriver_adapter, REG_FW_DBG7);
-
- for (i = 0; i <= 10; i++) {
- value32 = PLATFORM_REG_READ_32(pDriver_adapter, REG_FW_DBG7);
- if (value32_backup != value32) {
- break;
- } else {
- if (10 == i) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_check_fw_status Polling FW PC fail\n");
- *fw_status = _FALSE;
- return status;
- }
- }
- }
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_check_fw_status_88xx <==========\n");
-
- return status;
-}
-
-/**
- * halmac_dump_fw_dmem_88xx() -dump dmem
- * @pHalmac_adapter
- * @dmem
- * @size
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_dump_fw_dmem_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- INOUT u8 *dmem,
- INOUT u32 *size
-)
-{
- VOID *pDriver_adapter = NULL;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DUMP_FW_DMEM);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_dump_fw_dmem_88xx ==========>\n");
-
-
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_dump_fw_dmem_88xx <==========\n");
-
- return status;
-}
-
-/**
- * halmac_cfg_max_dl_size_88xx() - config max download size
- * @pHalmac_adapter
- * @halmac_offset
- * Author : Ivan Lin/KaiYuan Chang
- *
- * Halmac uses this setting to set max packet size for
- * download FW.
- * If user has not called this API, halmac use default
- * setting for download FW
- * Note1 : size need power of 2
- * Note2 : max size is 31K
- *
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_cfg_max_dl_size_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 size
-)
-{
- VOID *pDriver_adapter = NULL;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_MAX_DL_SIZE);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_TRACE, "halmac_cfg_max_dl_size_88xx ==========>\n");
-
- if (size > HALMAC_FW_CFG_MAX_DL_SIZE_MAX_88XX) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_ERR, "size > HALMAC_FW_CFG_MAX_DL_SIZE_MAX!\n");
- return HALMAC_RET_CFG_DLFW_SIZE_FAIL;
- }
-
- if (0 != (size & (2 - 1))) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_ERR, "size is not power of 2!\n");
- return HALMAC_RET_CFG_DLFW_SIZE_FAIL;
- }
-
- pHalmac_adapter->max_download_size = size;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_TRACE, "Cfg max size is : %X\n", size);
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_TRACE, "halmac_cfg_max_dl_size_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_psd_88xx() - trigger fw offload psd
- * @pHalmac_adapter
- * @start_psd
- * @end_psd
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_psd_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u16 start_psd,
- IN u16 end_psd
-)
-{
- u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 };
- u16 h2c_seq_mum = 0;
- VOID *pDriver_adapter = NULL;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
- HALMAC_H2C_HEADER_INFO h2c_header_info;
- HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.psd_set.process_status);
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter))
- return HALMAC_RET_NO_DLFW;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_PSD);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_psd_88xx ==========>\n");
-
- if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(psd)...\n");
- return HALMAC_RET_BUSY_STATE;
- }
-
- if (NULL != pHalmac_adapter->halmac_state.psd_set.pData) {
- PLATFORM_RTL_FREE(pDriver_adapter, pHalmac_adapter->halmac_state.psd_set.pData, pHalmac_adapter->halmac_state.psd_set.data_size);
- pHalmac_adapter->halmac_state.psd_set.pData = (u8 *)NULL;
- }
-
- pHalmac_adapter->halmac_state.psd_set.data_size = 0;
- pHalmac_adapter->halmac_state.psd_set.segment_size = 0;
-
- *pProcess_status = HALMAC_CMD_PROCESS_SENDING;
-
- PSD_SET_START_PSD(pH2c_buff, start_psd);
- PSD_SET_END_PSD(pH2c_buff, end_psd);
-
- h2c_header_info.sub_cmd_id = SUB_CMD_ID_PSD;
- h2c_header_info.content_size = 4;
- h2c_header_info.ack = _TRUE;
- halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum);
-
- status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE);
-
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail = %x!!\n", status);
- return status;
- }
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_psd_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_cfg_la_mode_88xx() - config la mode
- * @pHalmac_adapter
- * @la_mode
- * Author : KaiYuan Chang
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_cfg_la_mode_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_LA_MODE la_mode
-)
-{
- VOID *pDriver_adapter = NULL;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_LA_MODE);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_la_mode_88xx ==========>la_mode = %d\n", la_mode);
-
- pHalmac_adapter->txff_allocation.la_mode = la_mode;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_la_mode_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-
-/**
- * halmac_get_hw_value_88xx() -
- * @pHalmac_adapter
- * @hw_id
- * @pvalue
- * Author : KaiYuan Chang
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_get_hw_value_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_HW_ID hw_id,
- OUT VOID *pvalue
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_RQPN_MAP pRQPN_Map;
- u32 *pEfuse_size, *pTxff_size;
- u16 *pDrv_pg_bndy;
- u16 hcpwm2 = 0;
- u8 hcpwm = 0;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_GET_HW_VALUE);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_get_hw_value_88xx ==========>\n");
-
- if (NULL == pvalue) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_get_hw_value_88xx (NULL ==pvalue)==========>\n");
- return HALMAC_RET_NULL_POINTER;
- }
- switch (hw_id) {
- case HALMAC_HW_RQPN_MAPPING:
- pRQPN_Map = (PHALMAC_RQPN_MAP)pvalue;
- pRQPN_Map->dma_map_vo = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO];
- pRQPN_Map->dma_map_vi = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI];
- pRQPN_Map->dma_map_be = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE];
- pRQPN_Map->dma_map_bk = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK];
- pRQPN_Map->dma_map_mg = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG];
- pRQPN_Map->dma_map_hi = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI];
- break;
- case HALMAC_HW_EFUSE_SIZE:
- pEfuse_size = (pu32)pvalue;
- halmac_get_efuse_size_88xx(pHalmac_adapter, pEfuse_size);
- break;
- case HALMAC_HW_EEPROM_SIZE:
- pEfuse_size = (pu32)pvalue;
- *pEfuse_size = pHalmac_adapter->hw_config_info.eeprom_size;
- halmac_get_logical_efuse_size_88xx(pHalmac_adapter, pEfuse_size);
- break;
- case HALMAC_HW_BT_BANK_EFUSE_SIZE:
- *(u32 *)pvalue = pHalmac_adapter->hw_config_info.bt_efuse_size;
- break;
- case HALMAC_HW_BT_BANK1_EFUSE_SIZE:
- case HALMAC_HW_BT_BANK2_EFUSE_SIZE:
- *(u32 *)pvalue = 0;
- break;
- case HALMAC_HW_TXFIFO_SIZE:
- pTxff_size = (pu32)pvalue;
- *pTxff_size = pHalmac_adapter->hw_config_info.tx_fifo_size;
- break;
- case HALMAC_HW_RSVD_PG_BNDY:
- pDrv_pg_bndy = (pu16)pvalue;
- *pDrv_pg_bndy = pHalmac_adapter->txff_allocation.rsvd_drv_pg_bndy;
- break;
- case HALMAC_HW_CAM_ENTRY_NUM:
- *(u8 *)pvalue = pHalmac_adapter->hw_config_info.cam_entry_num;
- break;
- case HALMAC_HW_HCPWM:
- halmac_get_hcpwm_88xx(pHalmac_adapter, &hcpwm);
- *(u8 *)pvalue = hcpwm;
- break;
- case HALMAC_HW_HCPWM2:
- halmac_get_hcpwm2_88xx(pHalmac_adapter, &hcpwm2);
- *(u16 *)pvalue = hcpwm2;
- break;
- case HALMAC_HW_WLAN_EFUSE_AVAILABLE_SIZE:
- status = halmac_dump_logical_efuse_map_88xx(pHalmac_adapter, HALMAC_EFUSE_R_DRV);
- if (HALMAC_RET_SUCCESS != status)
- return status;
- pEfuse_size = (pu32)pvalue;
- *pEfuse_size = pHalmac_adapter->hw_config_info.efuse_size - HALMAC_RESERVED_EFUSE_SIZE_88XX - pHalmac_adapter->efuse_end;
- break;
-
- case HALMAC_HW_TXFF_ALLOCATION:
- PLATFORM_RTL_MEMCPY(pDriver_adapter, pvalue, &(pHalmac_adapter->txff_allocation), sizeof(HALMAC_TXFF_ALLOCATION));
- break;
- default:
- break;
- }
-
-
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_get_hw_value_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-
-/**
- * halmac_set_hw_value_88xx() -
- * @pHalmac_adapter
- * @hw_id
- * @pvalue
- * Author : KaiYuan Chang
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_set_hw_value_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_HW_ID hw_id,
- IN void *pvalue
-)
-{
- VOID *pDriver_adapter = NULL;
- u16 hrpwm2 = 0;
- u8 hrpwm = 0, value8 = 0;
- HALMAC_USB_MODE usb_mode = HALMAC_USB_MODE_U2, current_usb_mode = HALMAC_USB_MODE_U2;
- u8 hw_seq_en = 0;
- u32 value32 = 0;
- u32 usb_temp = 0;
- HALMAC_BW bw;
- u8 channel, enable_bb;
- HALMAC_PRI_CH_IDX pri_ch_idx;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_GET_HW_VALUE);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_set_hw_value_88xx ==========>\n");
-
- if (NULL == pvalue) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_set_hw_value_88xx (NULL ==pvalue)==========>\n");
- return HALMAC_RET_NULL_POINTER;
- }
-
- switch (hw_id) {
- case HALMAC_HW_ID_UNDEFINE:
- break;
- case HALMAC_HW_HRPWM:
- hrpwm = *(u8 *)pvalue;
- halmac_set_hrpwm_88xx(pHalmac_adapter, hrpwm);
- break;
- case HALMAC_HW_HRPWM2:
- hrpwm2 = *(u16 *)pvalue;
- halmac_set_hrpwm2_88xx(pHalmac_adapter, hrpwm2);
- break;
- case HALMAC_HW_USB_MODE:
- /* Get driver config USB mode*/
- usb_mode = *(HALMAC_USB_MODE *)pvalue;
-
- /* Get current USB mode*/
- current_usb_mode = (HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_CFG2 + 3) == 0x20) ? HALMAC_USB_MODE_U3 : HALMAC_USB_MODE_U2;
-
- /*check if HW supports usb2_usb3 swtich*/
- usb_temp = HALMAC_REG_READ_32(pHalmac_adapter, REG_PAD_CTRL2);
- if (_FALSE == (BIT_GET_USB23_SW_MODE_V1(usb_temp) | (usb_temp & BIT_USB3_USB2_TRANSITION))) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "HALMAC_HW_USB_MODE usb mode HW unsupport\n");
- return HALMAC_RET_USB2_3_SWITCH_UNSUPPORT;
- }
-
- if (usb_mode == current_usb_mode) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "HALMAC_HW_USB_MODE usb mode unchange\n");
- return HALMAC_RET_USB_MODE_UNCHANGE;
- }
-
- usb_temp &= ~(BIT_USB23_SW_MODE_V1(0x3)); /* clear 0xC6[3:2] */
-
- if (HALMAC_USB_MODE_U2 == usb_mode) {
- /* usb3 to usb2 */
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_PAD_CTRL2, usb_temp | BIT_USB23_SW_MODE_V1(HALMAC_USB_MODE_U2) | BIT_RSM_EN_V1); /* set usb mode and enable timer */
- } else {
- /* usb2 to usb3 */
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_PAD_CTRL2, usb_temp | BIT_USB23_SW_MODE_V1(HALMAC_USB_MODE_U3) | BIT_RSM_EN_V1); /* set usb mode and enable timer */
- }
-
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PAD_CTRL2 + 1, 4); /* set counter down timer 4x64 ms */
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_SYS_PW_CTRL, HALMAC_REG_READ_16(pHalmac_adapter, REG_SYS_PW_CTRL) | BIT_APFM_OFFMAC); /* auto MAC off */
- PLATFORM_RTL_DELAY_US(pDriver_adapter, 1000);
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_PAD_CTRL2, HALMAC_REG_READ_32(pHalmac_adapter, REG_PAD_CTRL2) | BIT_NO_PDN_CHIPOFF_V1); /* chip off */
- break;
-
- case HALMAC_HW_SEQ_EN:
-
- hw_seq_en = *(u8 *)pvalue;
-
- break;
- case HALMAC_HW_BANDWIDTH:
-
- bw = *(HALMAC_BW *)pvalue;
- halmac_cfg_bw_88xx(pHalmac_adapter, bw);
-
- break;
- case HALMAC_HW_CHANNEL:
-
- channel = *(u8 *)pvalue;
- halmac_cfg_ch_88xx(pHalmac_adapter, channel);
-
- break;
- case HALMAC_HW_PRI_CHANNEL_IDX:
-
- pri_ch_idx = *(HALMAC_PRI_CH_IDX *)pvalue;
- halmac_cfg_pri_ch_idx_88xx(pHalmac_adapter, pri_ch_idx);
-
- break;
- case HALMAC_HW_EN_BB_RF:
-
- enable_bb = *(u8 *)pvalue;
-
- if (_TRUE == enable_bb) {
- /* enable bb, rf */
- value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_FUNC_EN);
- value8 = value8 | BIT(0) | BIT(1);
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SYS_FUNC_EN, value8);
-
- value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_RF_CTRL);
- value8 = value8 | BIT(0) | BIT(1) | BIT(2);
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RF_CTRL, value8);
-
- value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_WLRF1);
- value32 = value32 | BIT(24) | BIT(25) | BIT(26);
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WLRF1, value32);
- } else {
- value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_FUNC_EN);
- value8 = value8 & (~(BIT(0) | BIT(1)));
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SYS_FUNC_EN, value8);
-
- value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_RF_CTRL);
- value8 = value8 & (~(BIT(0) | BIT(1) | BIT(2)));
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RF_CTRL, value8);
-
- value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_WLRF1);
- value32 = value32 & (~(BIT(24) | BIT(25) | BIT(26)));
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WLRF1, value32);
- }
-
- break;
-
- default:
- break;
- }
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_set_hw_value_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-
-/**
- * halmac_cfg_drv_rsvd_pg_num_88xx() -
- * @pHalmac_adapter
- * @pg_num
- * Author : KaiYuan Chang
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_cfg_drv_rsvd_pg_num_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_DRV_RSVD_PG_NUM pg_num
-)
-{
- VOID *pDriver_adapter = NULL;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_DRV_RSVD_PG_NUM);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_drv_rsvd_pg_num_88xx ==========>pg_num = %d\n", pg_num);
-
- switch (pg_num) {
- case HALMAC_RSVD_PG_NUM16:
- pHalmac_adapter->txff_allocation.rsvd_drv_pg_num = 16;
- break;
- case HALMAC_RSVD_PG_NUM24:
- pHalmac_adapter->txff_allocation.rsvd_drv_pg_num = 24;
- break;
- case HALMAC_RSVD_PG_NUM32:
- pHalmac_adapter->txff_allocation.rsvd_drv_pg_num = 32;
- break;
- }
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_drv_rsvd_pg_num_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-
-/**
- * halmac_get_chip_version_88xx() -
- * @pHalmac_adapter
- * @version
- * Author : KaiYuan Chang
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_get_chip_version_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_VER pVersion
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_SWITCH_EFUSE_BANK);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_get_chip_version_88xx ==========>\n");
- pVersion->major_ver = (u8)HALMAC_MAJOR_VER_88XX;
- pVersion->prototype_ver = (u8)HALMAC_PROTOTYPE_VER_88XX;
- pVersion->minor_ver = (u8)HALMAC_MINOR_VER_88XX;
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_get_chip_version_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_chk_txdesc_88xx() -
- * @pHalmac_adapter
- * @halmac_buf
- * @halmac_size
- * Author : KaiYuan Chang
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_chk_txdesc_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pHalmac_buf,
- IN u32 halmac_size
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_chk_txdesc_88xx ==========>\n");
-
- if (_TRUE == GET_TX_DESC_BMC(pHalmac_buf))
- if (_TRUE == GET_TX_DESC_AGG_EN(pHalmac_buf))
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "TxDesc: Agg should not be set when BMC\n");
-
- if (halmac_size < (GET_TX_DESC_TXPKTSIZE(pHalmac_buf) + GET_TX_DESC_OFFSET(pHalmac_buf)))
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "TxDesc: PktSize too small\n");
-
- /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_WARN, "halmac_chk_txdesc_88xx <==========\n"); */
-
- return HALMAC_RET_SUCCESS;
-}
diff --git a/hal/halmac/halmac_88xx/halmac_api_88xx.h b/hal/halmac/halmac_88xx/halmac_api_88xx.h
deleted file mode 100644
index 252941a..0000000
--- a/hal/halmac/halmac_88xx/halmac_api_88xx.h
+++ /dev/null
@@ -1,525 +0,0 @@
-#ifndef _HALMAC_API_88XX_H_
-#define _HALMAC_API_88XX_H_
-
-#include "../halmac_2_platform.h"
-#include "../halmac_type.h"
-
-VOID
-halmac_init_state_machine_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-VOID
-halmac_init_adapter_para_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-HALMAC_RET_STATUS
-halmac_mount_api_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-HALMAC_RET_STATUS
-halmac_download_firmware_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pHamacl_fw,
- IN u32 halmac_fw_size
-);
-
-HALMAC_RET_STATUS
-halmac_get_fw_version_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- OUT PHALMAC_FW_VERSION pFw_version
-);
-
-HALMAC_RET_STATUS
-halmac_cfg_mac_addr_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 halmac_port,
- IN PHALMAC_WLAN_ADDR pHal_address
-);
-
-HALMAC_RET_STATUS
-halmac_cfg_bssid_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 halmac_port,
- IN PHALMAC_WLAN_ADDR pHal_address
-);
-
-HALMAC_RET_STATUS
-halmac_cfg_multicast_addr_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_WLAN_ADDR pHal_address
-);
-
-HALMAC_RET_STATUS
-halmac_pre_init_system_cfg_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-HALMAC_RET_STATUS
-halmac_init_system_cfg_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-HALMAC_RET_STATUS
-halmac_cfg_rx_aggregation_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_RXAGG_CFG halmac_rxagg_cfg
-);
-
-HALMAC_RET_STATUS
-halmac_init_protocol_cfg_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-HALMAC_RET_STATUS
-halmac_init_edca_cfg_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-HALMAC_RET_STATUS
-halmac_cfg_operation_mode_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_WIRELESS_MODE wireless_mode
-);
-
-HALMAC_RET_STATUS
-halmac_cfg_ch_bw_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 channel,
- IN HALMAC_PRI_CH_IDX pri_ch_idx,
- IN HALMAC_BW bw
-);
-
-HALMAC_RET_STATUS
-halmac_cfg_ch_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 channel
-);
-
-HALMAC_RET_STATUS
-halmac_cfg_pri_ch_idx_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_PRI_CH_IDX pri_ch_idx
-);
-
-HALMAC_RET_STATUS
-halmac_cfg_bw_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_BW bw
-);
-
-HALMAC_RET_STATUS
-halmac_init_wmac_cfg_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-HALMAC_RET_STATUS
-halmac_init_mac_cfg_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_TRX_MODE mode
-);
-
-HALMAC_RET_STATUS
-halmac_clear_security_cam_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-HALMAC_RET_STATUS
-halmac_dump_efuse_map_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_EFUSE_READ_CFG cfg
-);
-
-HALMAC_RET_STATUS
-halmac_dump_efuse_map_bt_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_EFUSE_BANK halmac_efuse_bank,
- IN u32 bt_efuse_map_size,
- OUT u8 *pBT_efuse_map
-);
-
-HALMAC_RET_STATUS
-halmac_write_efuse_bt_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset,
- IN u8 halmac_value,
- IN HALMAC_EFUSE_BANK halmac_efuse_bank
-);
-
-HALMAC_RET_STATUS
-halmac_pg_efuse_by_map_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_PG_EFUSE_INFO pPg_efuse_info,
- IN HALMAC_EFUSE_READ_CFG cfg
-);
-
-HALMAC_RET_STATUS
-halmac_get_efuse_size_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- OUT u32 *halmac_size
-);
-
-HALMAC_RET_STATUS
-halmac_get_c2h_info_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *halmac_buf,
- IN u32 halmac_size
-);
-
-HALMAC_RET_STATUS
-halmac_get_logical_efuse_size_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- OUT u32 *halmac_size
-);
-
-HALMAC_RET_STATUS
-halmac_dump_logical_efuse_map_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_EFUSE_READ_CFG cfg
-);
-
-HALMAC_RET_STATUS
-halmac_write_logical_efuse_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset,
- IN u8 halmac_value
-);
-
-HALMAC_RET_STATUS
-halmac_read_logical_efuse_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset,
- OUT u8 *pValue
-);
-
-HALMAC_RET_STATUS
-halmac_cfg_fwlps_option_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_FWLPS_OPTION pLps_option
-);
-
-HALMAC_RET_STATUS
-halmac_cfg_fwips_option_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_FWIPS_OPTION pIps_option
-);
-
-HALMAC_RET_STATUS
-halmac_enter_wowlan_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_WOWLAN_OPTION pWowlan_option
-);
-
-HALMAC_RET_STATUS
-halmac_leave_wowlan_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-HALMAC_RET_STATUS
-halmac_enter_ps_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_PS_STATE ps_state
-);
-
-HALMAC_RET_STATUS
-halmac_leave_ps_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-HALMAC_RET_STATUS
-halmac_h2c_lb_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-HALMAC_RET_STATUS
-halmac_debug_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-HALMAC_RET_STATUS
-halmac_cfg_parameter_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_PHY_PARAMETER_INFO para_info,
- IN u8 full_fifo
-);
-
-HALMAC_RET_STATUS
-halmac_update_packet_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_PACKET_ID pkt_id,
- IN u8 *pkt,
- IN u32 pkt_size
-);
-
-HALMAC_RET_STATUS
-halmac_bcn_ie_filter_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_BCN_IE_INFO pBcn_ie_info
-);
-
-HALMAC_RET_STATUS
-halmac_send_original_h2c_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *original_h2c,
- IN u16 *seq,
- IN u8 ack
-);
-
-HALMAC_RET_STATUS
-halmac_update_datapack_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_DATA_TYPE halmac_data_type,
- IN PHALMAC_PHY_PARAMETER_INFO para_info
-);
-
-HALMAC_RET_STATUS
-halmac_run_datapack_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_DATA_TYPE halmac_data_type
-);
-
-HALMAC_RET_STATUS
-halmac_cfg_drv_info_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_DRV_INFO halmac_drv_info
-);
-
-HALMAC_RET_STATUS
-halmac_send_bt_coex_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pBt_buf,
- IN u32 bt_size,
- IN u8 ack
-);
-
-HALMAC_RET_STATUS
-halmac_verify_platform_api_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-HALMAC_RET_STATUS
-halmac_timer_2s_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-HALMAC_RET_STATUS
-halmac_fill_txdesc_check_sum_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *cur_desc
-);
-
-HALMAC_RET_STATUS
-halmac_dump_fifo_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HAL_FIFO_SEL halmac_fifo_sel,
- OUT u8 *pFifo_map,
- IN u32 halmac_fifo_dump_size
-);
-
-u32
-halmac_get_fifo_size_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HAL_FIFO_SEL halmac_fifo_sel
-);
-
-HALMAC_RET_STATUS
-halmac_cfg_txbf_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 userid,
- IN HALMAC_BW bw,
- IN u8 txbf_en
-);
-
-HALMAC_RET_STATUS
-halmac_cfg_mumimo_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_CFG_MUMIMO_PARA pCfgmu
-);
-
-HALMAC_RET_STATUS
-halmac_cfg_sounding_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_SND_ROLE role,
- IN HALMAC_DATA_RATE datarate
-);
-
-HALMAC_RET_STATUS
-halmac_del_sounding_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_SND_ROLE role
-);
-
-HALMAC_RET_STATUS
-halmac_su_bfee_entry_init_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 userid,
- IN u16 paid
-);
-
-HALMAC_RET_STATUS
-halmac_su_bfer_entry_init_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_SU_BFER_INIT_PARA pSu_bfer_init
-);
-
-HALMAC_RET_STATUS
-halmac_mu_bfee_entry_init_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_MU_BFEE_INIT_PARA pMu_bfee_init
-);
-
-HALMAC_RET_STATUS
-halmac_mu_bfer_entry_init_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_MU_BFER_INIT_PARA pMu_bfer_init
-);
-
-HALMAC_RET_STATUS
-halmac_su_bfee_entry_del_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 userid
-);
-
-HALMAC_RET_STATUS
-halmac_su_bfer_entry_del_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 userid
-);
-
-HALMAC_RET_STATUS
-halmac_mu_bfee_entry_del_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 userid
-);
-
-HALMAC_RET_STATUS
-halmac_mu_bfer_entry_del_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-HALMAC_RET_STATUS
-halmac_add_ch_info_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_CH_INFO pCh_info
-);
-
-HALMAC_RET_STATUS
-halmac_add_extra_ch_info_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_CH_EXTRA_INFO pCh_extra_info
-);
-
-HALMAC_RET_STATUS
-halmac_ctrl_ch_switch_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_CH_SWITCH_OPTION pCs_option
-);
-
-HALMAC_RET_STATUS
-halmac_clear_ch_info_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-HALMAC_RET_STATUS
-halmac_send_general_info_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_GENERAL_INFO pGeneral_info
-);
-
-HALMAC_RET_STATUS
-halmac_start_iqk_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 clear
-);
-
-HALMAC_RET_STATUS
-halmac_ctrl_pwr_tracking_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_PWR_TRACKING_OPTION pPwr_tracking_opt
-);
-
-HALMAC_RET_STATUS
-halmac_query_status_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_FEATURE_ID feature_id,
- OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status,
- INOUT u8 *data,
- INOUT u32 *size
-);
-
-HALMAC_RET_STATUS
-halmac_reset_feature_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_FEATURE_ID feature_id
-);
-
-HALMAC_RET_STATUS
-halmac_check_fw_status_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- OUT u8 *fw_status
-);
-
-HALMAC_RET_STATUS
-halmac_dump_fw_dmem_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- INOUT u8 *dmem,
- INOUT u32 *size
-);
-
-HALMAC_RET_STATUS
-halmac_cfg_max_dl_size_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 size
-);
-
-
-HALMAC_RET_STATUS
-halmac_psd_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u16 start_psd,
- IN u16 end_psd
-);
-
-HALMAC_RET_STATUS
-halmac_cfg_la_mode_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_LA_MODE la_mode
-);
-
-HALMAC_RET_STATUS
-halmac_get_hw_value_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_HW_ID hw_id,
- OUT VOID *pvalue
-);
-
-HALMAC_RET_STATUS
-halmac_set_hw_value_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_HW_ID hw_id,
- IN VOID *pvalue
-);
-
-HALMAC_RET_STATUS
-halmac_cfg_drv_rsvd_pg_num_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_DRV_RSVD_PG_NUM pg_num
-);
-
-HALMAC_RET_STATUS
-halmac_get_chip_version_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_VER pVersion
-);
-
-HALMAC_RET_STATUS
-halmac_chk_txdesc_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pHalmac_buf,
- IN u32 halmac_size
-);
-
-
-#endif/* _HALMAC_API_H_ */
diff --git a/hal/halmac/halmac_88xx/halmac_api_88xx_pcie.c b/hal/halmac/halmac_88xx/halmac_api_88xx_pcie.c
deleted file mode 100644
index 76e5cd3..0000000
--- a/hal/halmac/halmac_88xx/halmac_api_88xx_pcie.c
+++ /dev/null
@@ -1,312 +0,0 @@
-#include "halmac_88xx_cfg.h"
-
-/**
- * halmac_init_pcie_cfg_88xx() - init PCIE related register
- * @pHalmac_adapter
- * Author : KaiYuan Chang
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_init_pcie_cfg_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-)
-{
- VOID *pDriver_adapter = NULL;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_INIT_PCIE_CFG);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_pcie_cfg_88xx ==========>\n");
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_pcie_cfg_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_deinit_pcie_cfg_88xx() - deinit PCIE related register
- * @pHalmac_adapter
- * Author : KaiYuan Chang
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_deinit_pcie_cfg_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-)
-{
- VOID *pDriver_adapter = NULL;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DEINIT_PCIE_CFG);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_deinit_pcie_cfg_88xx ==========>\n");
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_deinit_pcie_cfg_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_cfg_rx_aggregation_88xx_pcie() - config rx aggregation
- * @pHalmac_adapter
- * @halmac_rx_agg_mode
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_cfg_rx_aggregation_88xx_pcie(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_RXAGG_CFG phalmac_rxagg_cfg
-)
-{
- VOID *pDriver_adapter = NULL;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_RX_AGGREGATION);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_rx_aggregation_88xx_pcie ==========>\n");
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_rx_aggregation_88xx_pcie <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_reg_read_8_pcie_88xx() - read 1byte register
- * @pHalmac_adapter
- * @halmac_offset
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-u8
-halmac_reg_read_8_pcie_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- return PLATFORM_REG_READ_8(pDriver_adapter, halmac_offset);
-}
-
-/**
- * halmac_reg_write_8_pcie_88xx() - write 1byte register
- * @pHalmac_adapter
- * @halmac_offset
- * @halmac_data
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_reg_write_8_pcie_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset,
- IN u8 halmac_data
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_REG_WRITE_8(pDriver_adapter, halmac_offset, halmac_data);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_reg_read_16_pcie_88xx() - read 2byte register
- * @pHalmac_adapter
- * @halmac_offset
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-u16
-halmac_reg_read_16_pcie_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- return PLATFORM_REG_READ_16(pDriver_adapter, halmac_offset);
-}
-
-/**
- * halmac_reg_write_16_pcie_88xx() - write 2byte register
- * @pHalmac_adapter
- * @halmac_offset
- * @halmac_data
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_reg_write_16_pcie_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset,
- IN u16 halmac_data
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_REG_WRITE_16(pDriver_adapter, halmac_offset, halmac_data);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_reg_read_32_pcie_88xx() - read 4byte register
- * @pHalmac_adapter
- * @halmac_offset
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-u32
-halmac_reg_read_32_pcie_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- return PLATFORM_REG_READ_32(pDriver_adapter, halmac_offset);
-}
-
-/**
- * halmac_reg_write_32_pcie_88xx() - write 4byte register
- * @pHalmac_adapter
- * @halmac_offset
- * @halmac_data
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_reg_write_32_pcie_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset,
- IN u32 halmac_data
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_REG_WRITE_32(pDriver_adapter, halmac_offset, halmac_data);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_cfg_tx_agg_align_pcie_not_support_88xx() -
- * @pHalmac_adapter
- * @enable
- * @align_size
- * Author : Soar Tu
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_cfg_tx_agg_align_pcie_not_support_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 enable,
- IN u16 align_size
-)
-{
- PHALMAC_API pHalmac_api;
- VOID *pDriver_adapter = NULL;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_TX_AGG_ALIGN);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_tx_agg_align_pcie_not_support_88xx ==========>\n");
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_tx_agg_align_pcie_not_support_88xx not support\n");
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_tx_agg_align_pcie_not_support_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
diff --git a/hal/halmac/halmac_88xx/halmac_api_88xx_pcie.h b/hal/halmac/halmac_88xx/halmac_api_88xx_pcie.h
deleted file mode 100644
index 434d9bd..0000000
--- a/hal/halmac/halmac_88xx/halmac_api_88xx_pcie.h
+++ /dev/null
@@ -1,69 +0,0 @@
-#ifndef _HALMAC_API_88XX_PCIE_H_
-#define _HALMAC_API_88XX_PCIE_H_
-
-#include "../halmac_2_platform.h"
-#include "../halmac_type.h"
-
-HALMAC_RET_STATUS
-halmac_init_pcie_cfg_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-HALMAC_RET_STATUS
-halmac_deinit_pcie_cfg_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-HALMAC_RET_STATUS
-halmac_cfg_rx_aggregation_88xx_pcie(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_RXAGG_CFG phalmac_rxagg_cfg
-);
-
-u8
-halmac_reg_read_8_pcie_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset
-);
-
-HALMAC_RET_STATUS
-halmac_reg_write_8_pcie_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset,
- IN u8 halmac_data
-);
-
-u16
-halmac_reg_read_16_pcie_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset
-);
-
-HALMAC_RET_STATUS
-halmac_reg_write_16_pcie_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset,
- IN u16 halmac_data
-);
-
-u32
-halmac_reg_read_32_pcie_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset
-);
-
-HALMAC_RET_STATUS
-halmac_reg_write_32_pcie_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset,
- IN u32 halmac_data
-);
-
-HALMAC_RET_STATUS
-halmac_cfg_tx_agg_align_pcie_not_support_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 enable,
- IN u16 align_size
-);
-
-#endif/* _HALMAC_API_88XX_PCIE_H_ */
diff --git a/hal/halmac/halmac_88xx/halmac_api_88xx_sdio.c b/hal/halmac/halmac_88xx/halmac_api_88xx_sdio.c
deleted file mode 100644
index b5c9a8b..0000000
--- a/hal/halmac/halmac_88xx/halmac_api_88xx_sdio.c
+++ /dev/null
@@ -1,653 +0,0 @@
-#include "halmac_88xx_cfg.h"
-
-/**
- * halmac_init_sdio_cfg_88xx() - init SDIO related register
- * @pHalmac_adapter
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_init_sdio_cfg_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_INIT_SDIO_CFG);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_sdio_cfg_88xx ==========>\n");
-
- HALMAC_REG_READ_32(pHalmac_adapter, REG_SDIO_FREE_TXPG);
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_SDIO_TX_CTRL, 0x00000000);
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_sdio_cfg_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_deinit_sdio_cfg_88xx() - deinit SDIO related register
- * @pHalmac_adapter
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_deinit_sdio_cfg_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-)
-{
- VOID *pDriver_adapter = NULL;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DEINIT_SDIO_CFG);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_deinit_sdio_cfg_88xx ==========>\n");
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_deinit_sdio_cfg_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_cfg_rx_aggregation_88xx_sdio() - config rx aggregation
- * @pHalmac_adapter
- * @halmac_rx_agg_mode
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_cfg_rx_aggregation_88xx_sdio(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_RXAGG_CFG phalmac_rxagg_cfg
-)
-{
- u8 value8, dma_usb_agg = 0;
- u8 size = 0, timeout = 0, agg_enable = 0;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_RX_AGGREGATION);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_rx_aggregation_88xx_sdio ==========>\n");
-
- dma_usb_agg = HALMAC_REG_READ_8(pHalmac_adapter, REG_RXDMA_AGG_PG_TH + 3);
- agg_enable = HALMAC_REG_READ_8(pHalmac_adapter, REG_TXDMA_PQ_MAP);
-
- switch (phalmac_rxagg_cfg->mode) {
- case HALMAC_RX_AGG_MODE_NONE:
- agg_enable &= ~(BIT_RXDMA_AGG_EN);
- break;
- case HALMAC_RX_AGG_MODE_DMA:
- agg_enable |= BIT_RXDMA_AGG_EN;
- dma_usb_agg |= BIT(7);
- break;
-
- case HALMAC_RX_AGG_MODE_USB:
- agg_enable |= BIT_RXDMA_AGG_EN;
- dma_usb_agg &= ~(BIT(7));
- break;
- default:
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_cfg_rx_aggregation_88xx_usb switch case not support\n");
- agg_enable &= ~BIT_RXDMA_AGG_EN;
- break;
- }
-
- if (_FALSE == phalmac_rxagg_cfg->threshold.drv_define) {
- size = 0xFF;
- timeout = 0x01;
- } else {
- size = phalmac_rxagg_cfg->threshold.size;
- timeout = phalmac_rxagg_cfg->threshold.timeout;
- }
-
-
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXDMA_PQ_MAP, agg_enable);
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RXDMA_AGG_PG_TH + 3, dma_usb_agg);
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RXDMA_AGG_PG_TH, (u16)(size | (timeout << BIT_SHIFT_DMA_AGG_TO)));
-
- value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_RXDMA_MODE);
- if (0 != (agg_enable & BIT_RXDMA_AGG_EN))
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RXDMA_MODE, value8 | BIT_DMA_MODE);
- else
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RXDMA_MODE, value8 & ~(BIT_DMA_MODE));
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_rx_aggregation_88xx_sdio <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_reg_read_8_sdio_88xx() - read 1byte register
- * @pHalmac_adapter
- * @halmac_offset
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-u8
-halmac_reg_read_8_sdio_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset
-)
-{
- u8 value8;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- if (0 == (halmac_offset & 0xFFFF0000))
- halmac_offset |= WLAN_IOREG_OFFSET;
-
- status = halmac_convert_to_sdio_bus_offset_88xx(pHalmac_adapter, &halmac_offset);
-
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_reg_read_8_sdio_88xx error = %x\n", status);
- return status;
- }
-
- value8 = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset);
-
- return value8;
-}
-
-/**
- * halmac_reg_write_8_sdio_88xx() - write 1byte register
- * @pHalmac_adapter
- * @halmac_offset
- * @halmac_data
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_reg_write_8_sdio_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset,
- IN u8 halmac_data
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- if (0 == (halmac_offset & 0xFFFF0000))
- halmac_offset |= WLAN_IOREG_OFFSET;
-
- status = halmac_convert_to_sdio_bus_offset_88xx(pHalmac_adapter, &halmac_offset);
-
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_reg_write_8_sdio_88xx error = %x\n", status);
- return status;
- }
-
- PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset, halmac_data);
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_reg_read_16_sdio_88xx() - read 2byte register
- * @pHalmac_adapter
- * @halmac_offset
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-u16
-halmac_reg_read_16_sdio_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- union {
- u16 word;
- u8 byte[2];
- } value16 = { 0x0000 };
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- if (0 == (halmac_offset & 0xFFFF0000))
- halmac_offset |= WLAN_IOREG_OFFSET;
-
- status = halmac_convert_to_sdio_bus_offset_88xx(pHalmac_adapter, &halmac_offset);
-
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_reg_read_16_sdio_88xx error = %x\n", status);
- return status;
- }
-
- if (HALMAC_MAC_POWER_OFF == pHalmac_adapter->halmac_state.mac_power) {
- value16.byte[0] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset);
- value16.byte[1] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset + 1);
- value16.word = rtk_le16_to_cpu(value16.word);
- } else {
- if ((PLATFORM_SD_CLK > HALMAC_SD_CLK_THRESHOLD_88XX) && ((halmac_offset & 0xffffef00) == 0x00000000)) {
- value16.byte[0] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset);
- value16.byte[1] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset + 1);
- value16.word = rtk_le16_to_cpu(value16.word);
- } else {
- value16.word = PLATFORM_SDIO_CMD53_READ_16(pDriver_adapter, halmac_offset);
- }
- }
-
- return value16.word;
-}
-
-/**
- * halmac_reg_write_16_sdio_88xx() - write 2byte register
- * @pHalmac_adapter
- * @halmac_offset
- * @halmac_data
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_reg_write_16_sdio_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset,
- IN u16 halmac_data
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- if (0 == (halmac_offset & 0xFFFF0000))
- halmac_offset |= WLAN_IOREG_OFFSET;
-
- status = halmac_convert_to_sdio_bus_offset_88xx(pHalmac_adapter, &halmac_offset);
-
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_reg_write_16_sdio_88xx error = %x\n", status);
- return status;
- }
-
- if (HALMAC_MAC_POWER_OFF == pHalmac_adapter->halmac_state.mac_power) {
- PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset, (u8)(halmac_data & 0xFF));
- PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset + 1, (u8)((halmac_data & 0xFF00) >> 8));
- } else {
- PLATFORM_SDIO_CMD53_WRITE_16(pDriver_adapter, halmac_offset, halmac_data);
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_reg_read_32_sdio_88xx() - read 4byte register
- * @pHalmac_adapter
- * @halmac_offset
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-u32
-halmac_reg_read_32_sdio_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset
-)
-{
- u8 rtemp = 0xFF;
- u32 counter = 1000;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- union {
- u32 dword;
- u8 byte[4];
- } value32 = { 0x00000000 };
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- if (0 == (halmac_offset & 0xFFFF0000))
- halmac_offset |= WLAN_IOREG_OFFSET;
-
- status = halmac_convert_to_sdio_bus_offset_88xx(pHalmac_adapter, &halmac_offset);
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_reg_read_32_sdio_88xx error = %x\n", status);
- return status;
- }
-
- if (HALMAC_MAC_POWER_OFF == pHalmac_adapter->halmac_state.mac_power) {
- value32.byte[0] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset);
- value32.byte[1] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset + 1);
- value32.byte[2] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset + 2);
- value32.byte[3] = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset + 3);
- value32.dword = rtk_le32_to_cpu(value32.dword);
- } else {
- if ((PLATFORM_SD_CLK > HALMAC_SD_CLK_THRESHOLD_88XX) && ((halmac_offset & 0xffffef00) == 0x00000000)) {
- PLATFORM_SDIO_CMD53_WRITE_32(pDriver_adapter, REG_SDIO_INDIRECT_REG_CFG, halmac_offset | BIT(19) | BIT(17));
-
- do {
- rtemp = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, REG_SDIO_INDIRECT_REG_CFG + 2);
- counter--;
- } while (((rtemp & BIT(4)) != 0) && (counter > 0));
-
- value32.dword = PLATFORM_SDIO_CMD53_READ_32(pDriver_adapter, REG_SDIO_INDIRECT_REG_DATA);
- } else {
- value32.dword = PLATFORM_SDIO_CMD53_READ_32(pDriver_adapter, halmac_offset);
- }
- }
-
- return value32.dword;
-}
-
-/**
- * halmac_reg_write_32_sdio_88xx() - write 4byte register
- * @pHalmac_adapter
- * @halmac_offset
- * @halmac_data
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_reg_write_32_sdio_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset,
- IN u32 halmac_data
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- if (0 == (halmac_offset & 0xFFFF0000))
- halmac_offset |= WLAN_IOREG_OFFSET;
-
- status = halmac_convert_to_sdio_bus_offset_88xx(pHalmac_adapter, &halmac_offset);
-
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_reg_write_32_sdio_88xx error = %x\n", status);
- return status;
- }
-
- if (HALMAC_MAC_POWER_OFF == pHalmac_adapter->halmac_state.mac_power) {
- PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset, (u8)(halmac_data & 0xFF));
- PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset + 1, (u8)((halmac_data & 0xFF00) >> 8));
- PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset + 2, (u8)((halmac_data & 0xFF0000) >> 16));
- PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset + 3, (u8)((halmac_data & 0xFF000000) >> 24));
- } else {
- PLATFORM_SDIO_CMD53_WRITE_32(pDriver_adapter, halmac_offset, halmac_data);
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_get_sdio_tx_addr_88xx() - get CMD53 addr for the TX packet
- * @pHalmac_adapter
- * @halmac_buf
- * @halmac_size
- * @pcmd53_addr
- * Author : KaiYuan Chang/Ivan Lin
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_get_sdio_tx_addr_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *halmac_buf,
- IN u32 halmac_size,
- OUT u32 *pcmd53_addr
-)
-{
- u32 four_byte_len;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
- HALMAC_QUEUE_SELECT queue_sel;
- HALMAC_DMA_MAPPING dma_mapping;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_GET_SDIO_TX_ADDR);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_get_sdio_tx_addr_88xx ==========>\n");
-
- if (NULL == halmac_buf) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_buf is NULL!!\n");
- return HALMAC_RET_DATA_BUF_NULL;
- }
-
- if (0 == halmac_size) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_size is 0!!\n");
- return HALMAC_RET_DATA_SIZE_INCORRECT;
- }
-
- queue_sel = (HALMAC_QUEUE_SELECT)GET_TX_DESC_QSEL(halmac_buf);
-
- switch (queue_sel) {
- case HALMAC_QUEUE_SELECT_VO:
- case HALMAC_QUEUE_SELECT_VO_V2:
- dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO];
- break;
- case HALMAC_QUEUE_SELECT_VI:
- case HALMAC_QUEUE_SELECT_VI_V2:
- dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI];
- break;
- case HALMAC_QUEUE_SELECT_BE:
- case HALMAC_QUEUE_SELECT_BE_V2:
- dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE];
- break;
- case HALMAC_QUEUE_SELECT_BK:
- case HALMAC_QUEUE_SELECT_BK_V2:
- dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK];
- break;
- case HALMAC_QUEUE_SELECT_MGNT:
- dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG];
- break;
- case HALMAC_QUEUE_SELECT_HIGH:
- case HALMAC_QUEUE_SELECT_BCN:
- case HALMAC_QUEUE_SELECT_CMD:
- dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI];
- break;
- default:
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Qsel is out of range\n");
- return HALMAC_RET_QSEL_INCORRECT;
- }
-
- four_byte_len = (halmac_size >> 2) + ((halmac_size & (4 - 1)) ? 1 : 0);
-
- switch (dma_mapping) {
- case HALMAC_DMA_MAPPING_HIGH:
- *pcmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_HIGH;
- break;
- case HALMAC_DMA_MAPPING_NORMAL:
- *pcmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_NORMAL;
- break;
- case HALMAC_DMA_MAPPING_LOW:
- *pcmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_LOW;
- break;
- case HALMAC_DMA_MAPPING_EXTRA:
- *pcmd53_addr = HALMAC_SDIO_CMD_ADDR_TXFF_EXTRA;
- break;
- default:
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "DmaMapping is out of range\n");
- return HALMAC_RET_DMA_MAP_INCORRECT;
- }
-
- *pcmd53_addr = (*pcmd53_addr << 13) | (four_byte_len & HALMAC_SDIO_4BYTE_LEN_MASK);
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_get_sdio_tx_addr_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_cfg_tx_agg_align_sdio_88xx() -
- * @pHalmac_adapter
- * @enable
- * @align_size
- * Author : Soar Tu
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_cfg_tx_agg_align_sdio_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 enable,
- IN u16 align_size
-)
-{
- PHALMAC_API pHalmac_api;
- VOID *pDriver_adapter = NULL;
- u8 i, align_size_ok = 0;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_TX_AGG_ALIGN);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_tx_agg_align_sdio_88xx ==========>\n");
-
- if ((align_size & 0xF000) != 0) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Align size is out of range\n");
- return HALMAC_RET_FAIL;
- }
-
- for (i = 3; i <= 11; i++) {
- if (align_size == 1 << i) {
- align_size_ok = 1;
- break;
- }
- }
- if (align_size_ok == 0) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Align size is not 2^3 ~ 2^11\n");
- return HALMAC_RET_FAIL;
- }
-
- if (enable)
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RQPN_CTRL_2, 0x8000 | align_size);
- else
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RQPN_CTRL_2, align_size);
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_tx_agg_align_sdio_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_cfg_tx_agg_align_sdio_not_support_88xx() -
- * @pHalmac_adapter
- * @enable
- * @align_size
- * Author : Soar Tu
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_cfg_tx_agg_align_sdio_not_support_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 enable,
- IN u16 align_size
-)
-{
- PHALMAC_API pHalmac_api;
- VOID *pDriver_adapter = NULL;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_TX_AGG_ALIGN);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_tx_agg_align_sdio_not_support_88xx ==========>\n");
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_tx_agg_align_sdio_not_support_88xx not support\n");
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_tx_agg_align_sdio_not_support_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
diff --git a/hal/halmac/halmac_88xx/halmac_api_88xx_sdio.h b/hal/halmac/halmac_88xx/halmac_api_88xx_sdio.h
deleted file mode 100644
index dbb4a0e..0000000
--- a/hal/halmac/halmac_88xx/halmac_api_88xx_sdio.h
+++ /dev/null
@@ -1,84 +0,0 @@
-#ifndef _HALMAC_API_88XX_SDIO_H_
-#define _HALMAC_API_88XX_SDIO_H_
-
-#include "../halmac_2_platform.h"
-#include "../halmac_type.h"
-
-HALMAC_RET_STATUS
-halmac_init_sdio_cfg_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-HALMAC_RET_STATUS
-halmac_deinit_sdio_cfg_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-HALMAC_RET_STATUS
-halmac_cfg_rx_aggregation_88xx_sdio(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_RXAGG_CFG phalmac_rxagg_cfg
-);
-
-u8
-halmac_reg_read_8_sdio_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset
-);
-
-HALMAC_RET_STATUS
-halmac_reg_write_8_sdio_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset,
- IN u8 halmac_data
-);
-
-u16
-halmac_reg_read_16_sdio_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset
-);
-
-HALMAC_RET_STATUS
-halmac_reg_write_16_sdio_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset,
- IN u16 halmac_data
-);
-
-u32
-halmac_reg_read_32_sdio_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset
-);
-
-HALMAC_RET_STATUS
-halmac_reg_write_32_sdio_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset,
- IN u32 halmac_data
-);
-
-HALMAC_RET_STATUS
-halmac_get_sdio_tx_addr_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *halmac_buf,
- IN u32 halmac_size,
- OUT u32 *pcmd53_addr
-);
-
-HALMAC_RET_STATUS
-halmac_cfg_tx_agg_align_sdio_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 enable,
- IN u16 align_size
-);
-
-HALMAC_RET_STATUS
-halmac_cfg_tx_agg_align_sdio_not_support_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 enable,
- IN u16 align_size
-);
-
-#endif/* _HALMAC_API_88XX_SDIO_H_ */
diff --git a/hal/halmac/halmac_88xx/halmac_api_88xx_usb.c b/hal/halmac/halmac_88xx/halmac_api_88xx_usb.c
deleted file mode 100644
index f4a8919..0000000
--- a/hal/halmac/halmac_88xx/halmac_api_88xx_usb.c
+++ /dev/null
@@ -1,551 +0,0 @@
-#include "halmac_88xx_cfg.h"
-
-/**
- * halmac_init_usb_cfg_88xx() - init USB related register
- * @pHalmac_adapter
- * Author : KaiYuan Chang
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_init_usb_cfg_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-)
-{
- VOID *pDriver_adapter = NULL;
- u8 value8 = 0;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_INIT_USB_CFG);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_usb_cfg_88xx ==========>\n");
-
- value8 |= (BIT_DMA_MODE | (0x3 << BIT_SHIFT_BURST_CNT)); /* burst number = 4 */
-
- if (PLATFORM_REG_READ_8(pDriver_adapter, REG_SYS_CFG2 + 3) == 0x20) { /* usb3.0 */
- value8 |= (HALMAC_USB_BURST_SIZE_3_0 << BIT_SHIFT_BURST_SIZE);
- } else {
- if ((PLATFORM_REG_READ_8(pDriver_adapter, REG_USB_USBSTAT) & 0x3) == 0x1) /* usb2.0 */
- value8 |= HALMAC_USB_BURST_SIZE_2_0_HSPEED << BIT_SHIFT_BURST_SIZE;
- else /* usb1.1 */
- value8 |= HALMAC_USB_BURST_SIZE_2_0_FSPEED << BIT_SHIFT_BURST_SIZE;
- }
-
- PLATFORM_REG_WRITE_8(pDriver_adapter, REG_RXDMA_MODE, value8);
- PLATFORM_REG_WRITE_16(pDriver_adapter, REG_TXDMA_OFFSET_CHK, PLATFORM_REG_READ_16(pDriver_adapter, REG_TXDMA_OFFSET_CHK) | BIT_DROP_DATA_EN);
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_usb_cfg_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_deinit_usb_cfg_88xx() - init USB related register
- * @pHalmac_adapter
- * Author : KaiYuan Chang
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_deinit_usb_cfg_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-)
-{
- VOID *pDriver_adapter = NULL;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DEINIT_USB_CFG);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_deinit_usb_cfg_88xx ==========>\n");
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_deinit_usb_cfg_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_cfg_rx_aggregation_88xx_usb() - config rx aggregation
- * @pHalmac_adapter
- * @halmac_rx_agg_mode
- * Author : KaiYuan Chang
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_cfg_rx_aggregation_88xx_usb(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_RXAGG_CFG phalmac_rxagg_cfg
-)
-{
- u8 dma_usb_agg;
- u8 size = 0, timeout = 0, agg_enable = 0;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_RX_AGGREGATION);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_rx_aggregation_88xx_usb ==========>\n");
-
- dma_usb_agg = HALMAC_REG_READ_8(pHalmac_adapter, REG_RXDMA_AGG_PG_TH + 3);
- agg_enable = HALMAC_REG_READ_8(pHalmac_adapter, REG_TXDMA_PQ_MAP);
-
- switch (phalmac_rxagg_cfg->mode) {
- case HALMAC_RX_AGG_MODE_NONE:
- agg_enable &= ~BIT_RXDMA_AGG_EN;
- break;
- case HALMAC_RX_AGG_MODE_DMA:
- agg_enable |= BIT_RXDMA_AGG_EN;
- dma_usb_agg |= BIT(7);
- break;
-
- case HALMAC_RX_AGG_MODE_USB:
- agg_enable |= BIT_RXDMA_AGG_EN;
- dma_usb_agg &= ~BIT(7);
- break;
- default:
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_cfg_rx_aggregation_88xx_usb switch case not support\n");
- agg_enable &= ~BIT_RXDMA_AGG_EN;
- break;
- }
-
- if (_FALSE == phalmac_rxagg_cfg->threshold.drv_define) {
- if (PLATFORM_REG_READ_8(pDriver_adapter, REG_SYS_CFG2 + 3) == 0x20) {
- /* usb3.0 */
- size = 0x5;
- timeout = 0xA;
- } else {
- /* usb2.0 */
- size = 0x5;
- timeout = 0x20;
- }
- } else {
- size = phalmac_rxagg_cfg->threshold.size;
- timeout = phalmac_rxagg_cfg->threshold.timeout;
- }
-
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXDMA_PQ_MAP, agg_enable);
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RXDMA_AGG_PG_TH + 3, dma_usb_agg);
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RXDMA_AGG_PG_TH, (u16)(size | (timeout << BIT_SHIFT_DMA_AGG_TO)));
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_rx_aggregation_88xx_usb <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_reg_read_8_usb_88xx() - read 1byte register
- * @pHalmac_adapter
- * @halmac_offset
- * Author : KaiYuan Chang
- * Return : HALMAC_RET_STATUS
- */
-u8
-halmac_reg_read_8_usb_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset
-)
-{
- u8 value8;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_reg_read_8_usb_88xx ==========>\n"); */
-
- value8 = PLATFORM_REG_READ_8(pDriver_adapter, halmac_offset);
-
- /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_reg_read_8_usb_88xx <==========\n"); */
-
- return value8;
-}
-
-/**
- * halmac_reg_write_8_usb_88xx() - write 1byte register
- * @pHalmac_adapter
- * @halmac_offset
- * @halmac_data
- * Author : KaiYuan Chang
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_reg_write_8_usb_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset,
- IN u8 halmac_data
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
-
- /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_reg_write_8_usb_88xx ==========>\n"); */
-
- PLATFORM_REG_WRITE_8(pDriver_adapter, halmac_offset, halmac_data);
-
- /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_reg_write_8_usb_88xx <==========\n"); */
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_reg_read_16_usb_88xx() - read 2byte register
- * @pHalmac_adapter
- * @halmac_offset
- * Author : KaiYuan Chang
- * Return : HALMAC_RET_STATUS
- */
-u16
-halmac_reg_read_16_usb_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- union {
- u16 word;
- u8 byte[2];
- } value16 = { 0x0000 };
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_reg_read_16_usb_88xx ==========>\n"); */
-
- value16.word = PLATFORM_REG_READ_16(pDriver_adapter, halmac_offset);
-
- /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_reg_read_16_usb_88xx <==========\n"); */
-
- return value16.word;
-}
-
-/**
- * halmac_reg_write_16_usb_88xx() - write 2byte register
- * @pHalmac_adapter
- * @halmac_offset
- * @halmac_data
- * Author : KaiYuan Chang
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_reg_write_16_usb_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset,
- IN u16 halmac_data
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_reg_write_16_usb_88xx ==========>\n"); */
-
- PLATFORM_REG_WRITE_16(pDriver_adapter, halmac_offset, halmac_data);
-
- /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_reg_write_16_usb_88xx <==========\n"); */
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_reg_read_32_usb_88xx() - read 4byte register
- * @pHalmac_adapter
- * @halmac_offset
- * Author : KaiYuan Chang
- * Return : HALMAC_RET_STATUS
- */
-u32
-halmac_reg_read_32_usb_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- union {
- u32 dword;
- u8 byte[4];
- } value32 = { 0x00000000 };
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_reg_read_32_usb_88xx ==========>\n"); */
-
- value32.dword = PLATFORM_REG_READ_32(pDriver_adapter, halmac_offset);
-
- /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_reg_read_32_usb_88xx <==========\n"); */
-
- return value32.dword;
-}
-
-/**
- * halmac_reg_write_32_usb_88xx() - write 4byte register
- * @pHalmac_adapter
- * @halmac_offset
- * @halmac_data
- * Author : KaiYuan Chang
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_reg_write_32_usb_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset,
- IN u32 halmac_data
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_reg_write_32_usb_88xx ==========>\n"); */
-
- PLATFORM_REG_WRITE_32(pDriver_adapter, halmac_offset, halmac_data);
-
- /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_reg_write_32_usb_88xx <==========\n"); */
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_set_bulkout_num_88xx() - set bulk out endpoint number
- * @pHalmac_adapter
- * @bulkout_num
- * Author : KaiYuan Chang
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_set_bulkout_num_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 bulkout_num
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_SET_BULKOUT_NUM);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE,"halmac_set_bulkout_num_88xx ==========>\n"); */
- /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE,"bulkout_num = %d\n", bulkout_num); */
-
- pHalmac_adapter->halmac_bulkout_num = bulkout_num;
-
- /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE,"halmac_set_bulkout_num_88xx <==========\n"); */
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_get_usb_bulkout_id_88xx() - get bulk out id for the TX packet
- * @pHalmac_adapter
- * @halmac_buf
- * @halmac_size
- * @bulkout_id
- * Author : KaiYuan Chang
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_get_usb_bulkout_id_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *halmac_buf,
- IN u32 halmac_size,
- OUT u8 *bulkout_id
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
- HALMAC_QUEUE_SELECT queue_sel;
- HALMAC_DMA_MAPPING dma_mapping;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_GET_USB_BULKOUT_ID);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_get_usb_bulkout_id_88xx ==========>\n");
-
- if (NULL == halmac_buf) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_buf is NULL!!\n");
- return HALMAC_RET_DATA_BUF_NULL;
- }
-
- if (0 == halmac_size) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_size is 0!!\n");
- return HALMAC_RET_DATA_SIZE_INCORRECT;
- }
-
- queue_sel = (HALMAC_QUEUE_SELECT)GET_TX_DESC_QSEL(halmac_buf);
-
- switch (queue_sel) {
- case HALMAC_QUEUE_SELECT_VO:
- case HALMAC_QUEUE_SELECT_VO_V2:
- dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO];
- break;
- case HALMAC_QUEUE_SELECT_VI:
- case HALMAC_QUEUE_SELECT_VI_V2:
- dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI];
- break;
- case HALMAC_QUEUE_SELECT_BE:
- case HALMAC_QUEUE_SELECT_BE_V2:
- dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE];
- break;
- case HALMAC_QUEUE_SELECT_BK:
- case HALMAC_QUEUE_SELECT_BK_V2:
- dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK];
- break;
- case HALMAC_QUEUE_SELECT_MGNT:
- dma_mapping = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG];
- break;
- case HALMAC_QUEUE_SELECT_HIGH:
- case HALMAC_QUEUE_SELECT_BCN:
- case HALMAC_QUEUE_SELECT_CMD:
- dma_mapping = HALMAC_DMA_MAPPING_HIGH;
- break;
- default:
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Qsel is out of range\n");
- return HALMAC_RET_QSEL_INCORRECT;
- }
-
- switch (dma_mapping) {
- case HALMAC_DMA_MAPPING_HIGH:
- *bulkout_id = 0;
- break;
- case HALMAC_DMA_MAPPING_NORMAL:
- *bulkout_id = 1;
- break;
- case HALMAC_DMA_MAPPING_LOW:
- *bulkout_id = 2;
- break;
- case HALMAC_DMA_MAPPING_EXTRA:
- *bulkout_id = 3;
- break;
- default:
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "DmaMapping is out of range\n");
- return HALMAC_RET_DMA_MAP_INCORRECT;
- }
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_get_usb_bulkout_id_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-/**
- * halmac_cfg_tx_agg_align_usb_not_support_88xx() -
- * @pHalmac_adapter
- * @enable
- * @align_size
- * Author : Soar Tu
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_cfg_tx_agg_align_usb_not_support_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 enable,
- IN u16 align_size
-)
-{
- PHALMAC_API pHalmac_api;
- VOID *pDriver_adapter = NULL;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter))
- return HALMAC_RET_API_INVALID;
-
- halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_TX_AGG_ALIGN);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_tx_agg_align_usb_not_support_88xx ==========>\n");
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_tx_agg_align_usb_not_support_88xx not support\n");
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_tx_agg_align_usb_not_support_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
diff --git a/hal/halmac/halmac_88xx/halmac_api_88xx_usb.h b/hal/halmac/halmac_88xx/halmac_api_88xx_usb.h
deleted file mode 100644
index c3e9cf9..0000000
--- a/hal/halmac/halmac_88xx/halmac_api_88xx_usb.h
+++ /dev/null
@@ -1,83 +0,0 @@
-#ifndef _HALMAC_API_88XX_USB_H_
-#define _HALMAC_API_88XX_USB_H_
-
-#include "../halmac_2_platform.h"
-#include "../halmac_type.h"
-
-HALMAC_RET_STATUS
-halmac_init_usb_cfg_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-HALMAC_RET_STATUS
-halmac_deinit_usb_cfg_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-HALMAC_RET_STATUS
-halmac_cfg_rx_aggregation_88xx_usb(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_RXAGG_CFG phalmac_rxagg_cfg
-);
-
-u8
-halmac_reg_read_8_usb_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset
-);
-
-HALMAC_RET_STATUS
-halmac_reg_write_8_usb_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset,
- IN u8 halmac_data
-);
-
-u16
-halmac_reg_read_16_usb_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset
-);
-
-HALMAC_RET_STATUS
-halmac_reg_write_16_usb_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset,
- IN u16 halmac_data
-);
-
-u32
-halmac_reg_read_32_usb_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset
-);
-
-HALMAC_RET_STATUS
-halmac_reg_write_32_usb_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 halmac_offset,
- IN u32 halmac_data
-);
-
-HALMAC_RET_STATUS
-halmac_set_bulkout_num_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 bulkout_num
-);
-
-HALMAC_RET_STATUS
-halmac_get_usb_bulkout_id_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *halmac_buf,
- IN u32 halmac_size,
- OUT u8 *bulkout_id
-);
-
-HALMAC_RET_STATUS
-halmac_cfg_tx_agg_align_usb_not_support_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 enable,
- IN u16 align_size
-);
-
-#endif/* _HALMAC_API_88XX_USB_H_ */
diff --git a/hal/halmac/halmac_88xx/halmac_bb_rf_88xx.c b/hal/halmac/halmac_88xx/halmac_bb_rf_88xx.c
new file mode 100644
index 0000000..eb0085a
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_bb_rf_88xx.c
@@ -0,0 +1,392 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_bb_rf_88xx.h"
+#include "halmac_88xx_cfg.h"
+#include "halmac_common_88xx.h"
+#include "halmac_init_88xx.h"
+
+#if HALMAC_88XX_SUPPORT
+
+/**
+ * start_iqk_88xx() -trigger FW IQK
+ * @adapter : the adapter of halmac
+ * @param : IQK parameter
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+start_iqk_88xx(struct halmac_adapter *adapter, struct halmac_iqk_para *param)
+{
+ u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };
+ u16 seq_num = 0;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+ struct halmac_h2c_header_info hdr_info;
+ enum halmac_cmd_process_status *proc_status;
+
+ proc_status = &adapter->halmac_state.iqk_state.proc_status;
+
+ if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
+ return HALMAC_RET_NO_DLFW;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+ PLTFM_MSG_TRACE("[TRACE]Wait event(iqk)\n");
+ return HALMAC_RET_BUSY_STATE;
+ }
+
+ *proc_status = HALMAC_CMD_PROCESS_SENDING;
+
+ IQK_SET_CLEAR(h2c_buf, param->clear);
+ IQK_SET_SEGMENT_IQK(h2c_buf, param->segment_iqk);
+
+ hdr_info.sub_cmd_id = SUB_CMD_ID_IQK;
+ hdr_info.content_size = 1;
+ hdr_info.ack = _TRUE;
+ set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+
+ adapter->halmac_state.iqk_state.seq_num = seq_num;
+
+ status = send_h2c_pkt_88xx(adapter, h2c_buf);
+
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]send h2c pkt fail!!\n");
+ reset_ofld_feature_88xx(adapter, HALMAC_FEATURE_IQK);
+ return status;
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * ctrl_pwr_tracking_88xx() -trigger FW power tracking
+ * @adapter : the adapter of halmac
+ * @opt : power tracking option
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+ctrl_pwr_tracking_88xx(struct halmac_adapter *adapter,
+ struct halmac_pwr_tracking_option *opt)
+{
+ u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };
+ u16 seq_num = 0;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+ struct halmac_h2c_header_info hdr_info;
+ struct halmac_pwr_tracking_para *param;
+ enum halmac_cmd_process_status *proc_status;
+
+ proc_status = &adapter->halmac_state.pwr_trk_state.proc_status;
+
+ if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
+ return HALMAC_RET_NO_DLFW;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+ PLTFM_MSG_TRACE("[TRACE]Wait event(pwr tracking)...\n");
+ return HALMAC_RET_BUSY_STATE;
+ }
+
+ *proc_status = HALMAC_CMD_PROCESS_SENDING;
+
+ PWR_TRK_SET_TYPE(h2c_buf, opt->type);
+ PWR_TRK_SET_BBSWING_INDEX(h2c_buf, opt->bbswing_index);
+
+ param = &opt->pwr_tracking_para[HALMAC_RF_PATH_A];
+ PWR_TRK_SET_ENABLE_A(h2c_buf, param->enable);
+ PWR_TRK_SET_TX_PWR_INDEX_A(h2c_buf, param->tx_pwr_index);
+ PWR_TRK_SET_TSSI_VALUE_A(h2c_buf, param->tssi_value);
+ PWR_TRK_SET_OFFSET_VALUE_A(h2c_buf, param->pwr_tracking_offset_value);
+
+ PWR_TRK_SET_ENABLE_B(h2c_buf, param->enable);
+ PWR_TRK_SET_TX_PWR_INDEX_B(h2c_buf, param->tx_pwr_index);
+ PWR_TRK_SET_TSSI_VALUE_B(h2c_buf, param->tssi_value);
+ PWR_TRK_SET_OFFSET_VALUE_B(h2c_buf, param->pwr_tracking_offset_value);
+
+ PWR_TRK_SET_ENABLE_C(h2c_buf, param->enable);
+ PWR_TRK_SET_TX_PWR_INDEX_C(h2c_buf, param->tx_pwr_index);
+ PWR_TRK_SET_TSSI_VALUE_C(h2c_buf, param->tssi_value);
+ PWR_TRK_SET_OFFSET_VALUE_C(h2c_buf, param->pwr_tracking_offset_value);
+
+ PWR_TRK_SET_ENABLE_D(h2c_buf, param->enable);
+ PWR_TRK_SET_TX_PWR_INDEX_D(h2c_buf, param->tx_pwr_index);
+ PWR_TRK_SET_TSSI_VALUE_D(h2c_buf, param->tssi_value);
+ PWR_TRK_SET_OFFSET_VALUE_D(h2c_buf, param->pwr_tracking_offset_value);
+
+ hdr_info.sub_cmd_id = SUB_CMD_ID_PWR_TRK;
+ hdr_info.content_size = 20;
+ hdr_info.ack = _TRUE;
+ set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+
+ adapter->halmac_state.pwr_trk_state.seq_num = seq_num;
+
+ status = send_h2c_pkt_88xx(adapter, h2c_buf);
+
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]send h2c pkt fail!!\n");
+ reset_ofld_feature_88xx(adapter, HALMAC_FEATURE_POWER_TRACKING);
+ return status;
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+get_iqk_status_88xx(struct halmac_adapter *adapter,
+ enum halmac_cmd_process_status *proc_status)
+{
+ *proc_status = adapter->halmac_state.iqk_state.proc_status;
+
+ return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+get_pwr_trk_status_88xx(struct halmac_adapter *adapter,
+ enum halmac_cmd_process_status *proc_status)
+{
+ *proc_status = adapter->halmac_state.pwr_trk_state.proc_status;
+
+ return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+get_psd_status_88xx(struct halmac_adapter *adapter,
+ enum halmac_cmd_process_status *proc_status, u8 *data,
+ u32 *size)
+{
+ struct halmac_psd_state *state = &adapter->halmac_state.psd_state;
+
+ *proc_status = state->proc_status;
+
+ if (!data)
+ return HALMAC_RET_NULL_POINTER;
+
+ if (!size)
+ return HALMAC_RET_NULL_POINTER;
+
+ if (*proc_status == HALMAC_CMD_PROCESS_DONE) {
+ if (*size < state->data_size) {
+ *size = state->data_size;
+ return HALMAC_RET_BUFFER_TOO_SMALL;
+ }
+
+ *size = state->data_size;
+ PLTFM_MEMCPY(data, state->data, *size);
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * psd_88xx() - trigger fw psd
+ * @adapter : the adapter of halmac
+ * @start_psd : start PSD
+ * @end_psd : end PSD
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+psd_88xx(struct halmac_adapter *adapter, u16 start_psd, u16 end_psd)
+{
+ u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };
+ u16 seq_num = 0;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+ struct halmac_h2c_header_info hdr_info;
+ enum halmac_cmd_process_status *proc_status;
+
+ proc_status = &adapter->halmac_state.psd_state.proc_status;
+
+ if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
+ return HALMAC_RET_NO_DLFW;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+ PLTFM_MSG_TRACE("[TRACE]Wait event(psd)\n");
+ return HALMAC_RET_BUSY_STATE;
+ }
+
+ if (adapter->halmac_state.psd_state.data) {
+ PLTFM_FREE(adapter->halmac_state.psd_state.data,
+ adapter->halmac_state.psd_state.data_size);
+ adapter->halmac_state.psd_state.data = (u8 *)NULL;
+ }
+
+ adapter->halmac_state.psd_state.data_size = 0;
+ adapter->halmac_state.psd_state.seg_size = 0;
+
+ *proc_status = HALMAC_CMD_PROCESS_SENDING;
+
+ PSD_SET_START_PSD(h2c_buf, start_psd);
+ PSD_SET_END_PSD(h2c_buf, end_psd);
+
+ hdr_info.sub_cmd_id = SUB_CMD_ID_PSD;
+ hdr_info.content_size = 4;
+ hdr_info.ack = _TRUE;
+ set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+
+ status = send_h2c_pkt_88xx(adapter, h2c_buf);
+
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]send h2c pkt fail!!\n");
+ reset_ofld_feature_88xx(adapter, HALMAC_FEATURE_PSD);
+ return status;
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+get_h2c_ack_iqk_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+ u8 seq_num;
+ u8 fw_rc;
+ struct halmac_iqk_state *state = &adapter->halmac_state.iqk_state;
+ enum halmac_cmd_process_status proc_status;
+
+ seq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf);
+ PLTFM_MSG_TRACE("[TRACE]Seq num : h2c->%d c2h->%d\n",
+ state->seq_num, seq_num);
+ if (seq_num != state->seq_num) {
+ PLTFM_MSG_ERR("[ERR]Seq num mismatch : h2c->%d c2h->%d\n",
+ state->seq_num, seq_num);
+ return HALMAC_RET_SUCCESS;
+ }
+
+ if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) {
+ PLTFM_MSG_ERR("[ERR]not cmd sending\n");
+ return HALMAC_RET_SUCCESS;
+ }
+
+ fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf);
+ state->fw_rc = fw_rc;
+
+ if ((enum halmac_h2c_return_code)fw_rc == HALMAC_H2C_RETURN_SUCCESS) {
+ proc_status = HALMAC_CMD_PROCESS_DONE;
+ state->proc_status = proc_status;
+ PLTFM_EVENT_SIG(HALMAC_FEATURE_IQK, proc_status, NULL, 0);
+ } else {
+ proc_status = HALMAC_CMD_PROCESS_ERROR;
+ state->proc_status = proc_status;
+ PLTFM_EVENT_SIG(HALMAC_FEATURE_IQK, proc_status, &fw_rc, 1);
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+get_h2c_ack_pwr_trk_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+ u8 seq_num;
+ u8 fw_rc;
+ struct halmac_pwr_tracking_state *state;
+ enum halmac_cmd_process_status proc_status;
+
+ state = &adapter->halmac_state.pwr_trk_state;
+
+ seq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf);
+ PLTFM_MSG_TRACE("[TRACE]Seq num : h2c->%d c2h->%d\n",
+ state->seq_num, seq_num);
+ if (seq_num != state->seq_num) {
+ PLTFM_MSG_ERR("[ERR]Seq num mismatch : h2c->%d c2h->%d\n",
+ state->seq_num, seq_num);
+ return HALMAC_RET_SUCCESS;
+ }
+
+ if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) {
+ PLTFM_MSG_ERR("[ERR]not cmd sending\n");
+ return HALMAC_RET_SUCCESS;
+ }
+
+ fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf);
+ state->fw_rc = fw_rc;
+
+ if ((enum halmac_h2c_return_code)fw_rc == HALMAC_H2C_RETURN_SUCCESS) {
+ proc_status = HALMAC_CMD_PROCESS_DONE;
+ state->proc_status = proc_status;
+ PLTFM_EVENT_SIG(HALMAC_FEATURE_POWER_TRACKING, proc_status,
+ NULL, 0);
+ } else {
+ proc_status = HALMAC_CMD_PROCESS_ERROR;
+ state->proc_status = proc_status;
+ PLTFM_EVENT_SIG(HALMAC_FEATURE_POWER_TRACKING, proc_status,
+ &fw_rc, 1);
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+get_psd_data_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+ u8 seg_id;
+ u8 seg_size;
+ u8 seq_num;
+ u16 total_size;
+ enum halmac_cmd_process_status proc_status;
+ struct halmac_psd_state *state = &adapter->halmac_state.psd_state;
+
+ seq_num = (u8)PSD_DATA_GET_H2C_SEQ(buf);
+ PLTFM_MSG_TRACE("[TRACE]seq num : h2c->%d c2h->%d\n",
+ state->seq_num, seq_num);
+ if (seq_num != state->seq_num) {
+ PLTFM_MSG_ERR("[ERR]seq num mismatch : h2c->%d c2h->%d\n",
+ state->seq_num, seq_num);
+ return HALMAC_RET_SUCCESS;
+ }
+
+ if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) {
+ PLTFM_MSG_ERR("[ERR]not cmd sending\n");
+ return HALMAC_RET_SUCCESS;
+ }
+
+ total_size = (u16)PSD_DATA_GET_TOTAL_SIZE(buf);
+ seg_id = (u8)PSD_DATA_GET_SEGMENT_ID(buf);
+ seg_size = (u8)PSD_DATA_GET_SEGMENT_SIZE(buf);
+ state->data_size = total_size;
+
+ if (!state->data)
+ state->data = (u8 *)PLTFM_MALLOC(state->data_size);
+
+ if (seg_id == 0)
+ state->seg_size = seg_size;
+
+ PLTFM_MEMCPY(state->data + seg_id * state->seg_size,
+ buf + C2H_DATA_OFFSET_88XX, seg_size);
+
+ if (PSD_DATA_GET_END_SEGMENT(buf) == _FALSE)
+ return HALMAC_RET_SUCCESS;
+
+ proc_status = HALMAC_CMD_PROCESS_DONE;
+ state->proc_status = proc_status;
+
+ PLTFM_EVENT_SIG(HALMAC_FEATURE_PSD, proc_status, state->data,
+ state->data_size);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+#endif /* HALMAC_88XX_SUPPORT */
diff --git a/hal/halmac/halmac_88xx/halmac_bb_rf_88xx.h b/hal/halmac/halmac_88xx/halmac_bb_rf_88xx.h
new file mode 100644
index 0000000..bd107e6
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_bb_rf_88xx.h
@@ -0,0 +1,57 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_BB_RF_88XX_H_
+#define _HALMAC_BB_RF_88XX_H_
+
+#include "../halmac_api.h"
+
+#if HALMAC_88XX_SUPPORT
+
+enum halmac_ret_status
+start_iqk_88xx(struct halmac_adapter *adapter, struct halmac_iqk_para *param);
+
+enum halmac_ret_status
+ctrl_pwr_tracking_88xx(struct halmac_adapter *adapter,
+ struct halmac_pwr_tracking_option *opt);
+
+enum halmac_ret_status
+get_iqk_status_88xx(struct halmac_adapter *adapter,
+ enum halmac_cmd_process_status *proc_status);
+
+enum halmac_ret_status
+get_pwr_trk_status_88xx(struct halmac_adapter *adapter,
+ enum halmac_cmd_process_status *proc_status);
+
+enum halmac_ret_status
+get_psd_status_88xx(struct halmac_adapter *adapter,
+ enum halmac_cmd_process_status *proc_status, u8 *data,
+ u32 *size);
+
+enum halmac_ret_status
+psd_88xx(struct halmac_adapter *adapter, u16 start_psd, u16 end_psd);
+
+enum halmac_ret_status
+get_h2c_ack_iqk_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+enum halmac_ret_status
+get_h2c_ack_pwr_trk_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+enum halmac_ret_status
+get_psd_data_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+#endif /* HALMAC_88XX_SUPPORT */
+
+#endif/* _HALMAC_BB_RF_88XX_H_ */
diff --git a/hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.c b/hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.c
new file mode 100644
index 0000000..f598050
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.c
@@ -0,0 +1,1168 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_cfg_wmac_88xx.h"
+#include "halmac_88xx_cfg.h"
+
+#if HALMAC_88XX_SUPPORT
+
+#define MAC_CLK_SPEED 80 /* 80M */
+
+enum mac_clock_hw_def {
+ MAC_CLK_HW_DEF_80M = 0,
+ MAC_CLK_HW_DEF_40M = 1,
+ MAC_CLK_HW_DEF_20M = 2,
+};
+
+/**
+ * cfg_mac_addr_88xx() - config mac address
+ * @adapter : the adapter of halmac
+ * @port : 0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4
+ * @addr : mac address
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_mac_addr_88xx(struct halmac_adapter *adapter, u8 port,
+ union halmac_wlan_addr *addr)
+{
+ u16 mac_addr_h;
+ u32 mac_addr_l;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (port >= HALMAC_PORTID_NUM) {
+ PLTFM_MSG_ERR("[ERR]port index >= 5\n");
+ return HALMAC_RET_PORT_NOT_SUPPORT;
+ }
+
+ mac_addr_l = addr->addr_l_h.low;
+ mac_addr_h = addr->addr_l_h.high;
+
+ mac_addr_l = rtk_le32_to_cpu(mac_addr_l);
+ mac_addr_h = rtk_le16_to_cpu(mac_addr_h);
+
+ switch (port) {
+ case HALMAC_PORTID0:
+ HALMAC_REG_W32(REG_MACID, mac_addr_l);
+ HALMAC_REG_W16(REG_MACID + 4, mac_addr_h);
+ break;
+ case HALMAC_PORTID1:
+ HALMAC_REG_W32(REG_MACID1, mac_addr_l);
+ HALMAC_REG_W16(REG_MACID1 + 4, mac_addr_h);
+ break;
+ case HALMAC_PORTID2:
+ HALMAC_REG_W32(REG_MACID2, mac_addr_l);
+ HALMAC_REG_W16(REG_MACID2 + 4, mac_addr_h);
+ break;
+ case HALMAC_PORTID3:
+ HALMAC_REG_W32(REG_MACID3, mac_addr_l);
+ HALMAC_REG_W16(REG_MACID3 + 4, mac_addr_h);
+ break;
+ case HALMAC_PORTID4:
+ HALMAC_REG_W32(REG_MACID4, mac_addr_l);
+ HALMAC_REG_W16(REG_MACID4 + 4, mac_addr_h);
+ break;
+ default:
+ break;
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_bssid_88xx() - config BSSID
+ * @adapter : the adapter of halmac
+ * @port : 0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4
+ * @addr : bssid
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_bssid_88xx(struct halmac_adapter *adapter, u8 port,
+ union halmac_wlan_addr *addr)
+{
+ u16 bssid_addr_h;
+ u32 bssid_addr_l;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (port >= HALMAC_PORTID_NUM) {
+ PLTFM_MSG_ERR("[ERR]port index > 5\n");
+ return HALMAC_RET_PORT_NOT_SUPPORT;
+ }
+
+ bssid_addr_l = addr->addr_l_h.low;
+ bssid_addr_h = addr->addr_l_h.high;
+
+ bssid_addr_l = rtk_le32_to_cpu(bssid_addr_l);
+ bssid_addr_h = rtk_le16_to_cpu(bssid_addr_h);
+
+ switch (port) {
+ case HALMAC_PORTID0:
+ HALMAC_REG_W32(REG_BSSID, bssid_addr_l);
+ HALMAC_REG_W16(REG_BSSID + 4, bssid_addr_h);
+ break;
+ case HALMAC_PORTID1:
+ HALMAC_REG_W32(REG_BSSID1, bssid_addr_l);
+ HALMAC_REG_W16(REG_BSSID1 + 4, bssid_addr_h);
+ break;
+ case HALMAC_PORTID2:
+ HALMAC_REG_W32(REG_BSSID2, bssid_addr_l);
+ HALMAC_REG_W16(REG_BSSID2 + 4, bssid_addr_h);
+ break;
+ case HALMAC_PORTID3:
+ HALMAC_REG_W32(REG_BSSID3, bssid_addr_l);
+ HALMAC_REG_W16(REG_BSSID3 + 4, bssid_addr_h);
+ break;
+ case HALMAC_PORTID4:
+ HALMAC_REG_W32(REG_BSSID4, bssid_addr_l);
+ HALMAC_REG_W16(REG_BSSID4 + 4, bssid_addr_h);
+ break;
+ default:
+ break;
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_transmitter_addr_88xx() - config transmitter address
+ * @adapter : the adapter of halmac
+ * @port : 0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4
+ * @addr :
+ * Author : Alan
+ * Return : enum halmac_ret_status
+ */
+enum halmac_ret_status
+cfg_transmitter_addr_88xx(struct halmac_adapter *adapter, u8 port,
+ union halmac_wlan_addr *addr)
+{
+ u16 mac_addr_h;
+ u32 mac_addr_l;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (port >= HALMAC_PORTID_NUM) {
+ PLTFM_MSG_ERR("[ERR]port index > 5\n");
+ return HALMAC_RET_PORT_NOT_SUPPORT;
+ }
+
+ mac_addr_l = addr->addr_l_h.low;
+ mac_addr_h = addr->addr_l_h.high;
+
+ mac_addr_l = rtk_le32_to_cpu(mac_addr_l);
+ mac_addr_h = rtk_le16_to_cpu(mac_addr_h);
+
+ switch (port) {
+ case HALMAC_PORTID0:
+ HALMAC_REG_W32(REG_TRANSMIT_ADDRSS_0, mac_addr_l);
+ HALMAC_REG_W16(REG_TRANSMIT_ADDRSS_0 + 4, mac_addr_h);
+ break;
+ case HALMAC_PORTID1:
+ HALMAC_REG_W32(REG_TRANSMIT_ADDRSS_1, mac_addr_l);
+ HALMAC_REG_W16(REG_TRANSMIT_ADDRSS_1 + 4, mac_addr_h);
+ break;
+ case HALMAC_PORTID2:
+ HALMAC_REG_W32(REG_TRANSMIT_ADDRSS_2, mac_addr_l);
+ HALMAC_REG_W16(REG_TRANSMIT_ADDRSS_2 + 4, mac_addr_h);
+ break;
+ case HALMAC_PORTID3:
+ HALMAC_REG_W32(REG_TRANSMIT_ADDRSS_3, mac_addr_l);
+ HALMAC_REG_W16(REG_TRANSMIT_ADDRSS_3 + 4, mac_addr_h);
+ break;
+ case HALMAC_PORTID4:
+ HALMAC_REG_W32(REG_TRANSMIT_ADDRSS_4, mac_addr_l);
+ HALMAC_REG_W16(REG_TRANSMIT_ADDRSS_4 + 4, mac_addr_h);
+ break;
+ default:
+ break;
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_net_type_88xx() - config network type
+ * @adapter : the adapter of halmac
+ * @port : 0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4
+ * @addr : mac address
+ * Author : Alan
+ * Return : enum halmac_ret_status
+ */
+enum halmac_ret_status
+cfg_net_type_88xx(struct halmac_adapter *adapter, u8 port,
+ enum halmac_network_type_select net_type)
+{
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+ u8 value8 = 0;
+ u8 net_type_tmp = 0;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (net_type == HALMAC_NETWORK_AP) {
+ if (port >= HALMAC_PORTID1) {
+ PLTFM_MSG_ERR("[ERR]AP port > 1\n");
+ return HALMAC_RET_PORT_NOT_SUPPORT;
+ }
+ }
+
+ switch (port) {
+ case HALMAC_PORTID0:
+ net_type_tmp = net_type;
+ value8 = ((HALMAC_REG_R8(REG_CR + 2) & 0xFC) | net_type_tmp);
+ HALMAC_REG_W8(REG_CR + 2, value8);
+ break;
+ case HALMAC_PORTID1:
+ net_type_tmp = (net_type << 2);
+ value8 = ((HALMAC_REG_R8(REG_CR + 2) & 0xF3) | net_type_tmp);
+ HALMAC_REG_W8(REG_CR + 2, value8);
+ break;
+ case HALMAC_PORTID2:
+ net_type_tmp = net_type;
+ value8 = ((HALMAC_REG_R8(REG_CR_EXT) & 0xFC) | net_type_tmp);
+ HALMAC_REG_W8(REG_CR_EXT, value8);
+ break;
+ case HALMAC_PORTID3:
+ net_type_tmp = (net_type << 2);
+ value8 = ((HALMAC_REG_R8(REG_CR_EXT) & 0xF3) | net_type_tmp);
+ HALMAC_REG_W8(REG_CR_EXT, value8);
+ break;
+ case HALMAC_PORTID4:
+ net_type_tmp = (net_type << 4);
+ value8 = ((HALMAC_REG_R8(REG_CR_EXT) & 0xCF) | net_type_tmp);
+ HALMAC_REG_W8(REG_CR_EXT, value8);
+ break;
+ default:
+ break;
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_tsf_rst_88xx() - tsf reset
+ * @adapter : the adapter of halmac
+ * @port : 0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4
+ * Author : Alan
+ * Return : enum halmac_ret_status
+ */
+enum halmac_ret_status
+cfg_tsf_rst_88xx(struct halmac_adapter *adapter, u8 port)
+{
+ u8 tsf_rst = 0;
+ u8 value8;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ switch (port) {
+ case HALMAC_PORTID0:
+ tsf_rst = BIT_TSFTR_RST;
+ break;
+ case HALMAC_PORTID1:
+ tsf_rst = BIT_TSFTR_CLI0_RST;
+ break;
+ case HALMAC_PORTID2:
+ tsf_rst = BIT_TSFTR_CLI1_RST;
+ break;
+ case HALMAC_PORTID3:
+ tsf_rst = BIT_TSFTR_CLI2_RST;
+ break;
+ case HALMAC_PORTID4:
+ tsf_rst = BIT_TSFTR_CLI3_RST;
+ break;
+ default:
+ break;
+ }
+
+ value8 = HALMAC_REG_R8(REG_DUAL_TSF_RST);
+ HALMAC_REG_W8(REG_DUAL_TSF_RST, value8 | tsf_rst);
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_bcn_space_88xx() - config beacon space
+ * @adapter : the adapter of halmac
+ * @port : 0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4
+ * @bcn_space : beacon space
+ * Author : Alan
+ * Return : enum halmac_ret_status
+ */
+enum halmac_ret_status
+cfg_bcn_space_88xx(struct halmac_adapter *adapter, u8 port, u32 bcn_space)
+{
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+ u16 bcn_space_real = 0;
+ u16 value16 = 0;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ bcn_space_real = ((u16)bcn_space);
+
+ switch (port) {
+ case HALMAC_PORTID0:
+ HALMAC_REG_W16(REG_MBSSID_BCN_SPACE, bcn_space_real);
+ break;
+ case HALMAC_PORTID1:
+ value16 = HALMAC_REG_R16(REG_MBSSID_BCN_SPACE + 2) & 0xF000;
+ value16 |= bcn_space_real;
+ HALMAC_REG_W16(REG_MBSSID_BCN_SPACE + 2, value16);
+ break;
+ case HALMAC_PORTID2:
+ value16 = HALMAC_REG_R16(REG_MBSSID_BCN_SPACE2) & 0xF000;
+ value16 |= bcn_space_real;
+ HALMAC_REG_W16(REG_MBSSID_BCN_SPACE2, value16);
+ break;
+ case HALMAC_PORTID3:
+ value16 = HALMAC_REG_R16(REG_MBSSID_BCN_SPACE2 + 2) & 0xF000;
+ value16 |= bcn_space_real;
+ HALMAC_REG_W16(REG_MBSSID_BCN_SPACE2 + 2, value16);
+ break;
+ case HALMAC_PORTID4:
+ value16 = HALMAC_REG_R16(REG_MBSSID_BCN_SPACE3) & 0xF000;
+ value16 |= bcn_space_real;
+ HALMAC_REG_W16(REG_MBSSID_BCN_SPACE3, value16);
+ break;
+ default:
+ break;
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * rw_bcn_ctrl_88xx() - r/w beacon control
+ * @adapter : the adapter of halmac
+ * @port : 0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4
+ * @write_en : 1->write beacon function 0->read beacon function
+ * @pBcn_ctrl : beacon control info
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ */
+enum halmac_ret_status
+rw_bcn_ctrl_88xx(struct halmac_adapter *adapter, u8 port, u8 write_en,
+ struct halmac_bcn_ctrl *ctrl)
+{
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+ u8 ctrl_value = 0;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (write_en) {
+ if (ctrl->dis_rx_bssid_fit == _TRUE)
+ ctrl_value |= BIT_DIS_RX_BSSID_FIT;
+
+ if (ctrl->en_txbcn_rpt == _TRUE)
+ ctrl_value |= BIT_P0_EN_TXBCN_RPT;
+
+ if (ctrl->dis_tsf_udt == _TRUE)
+ ctrl_value |= BIT_DIS_TSF_UDT;
+
+ if (ctrl->en_bcn == _TRUE)
+ ctrl_value |= BIT_EN_BCN_FUNCTION;
+
+ if (ctrl->en_rxbcn_rpt == _TRUE)
+ ctrl_value |= BIT_P0_EN_RXBCN_RPT;
+
+ if (ctrl->en_p2p_ctwin == _TRUE)
+ ctrl_value |= BIT_EN_P2P_CTWINDOW;
+
+ if (ctrl->en_p2p_bcn_area == _TRUE)
+ ctrl_value |= BIT_EN_P2P_BCNQ_AREA;
+
+ switch (port) {
+ case HALMAC_PORTID0:
+ HALMAC_REG_W8(REG_BCN_CTRL, ctrl_value);
+ break;
+
+ case HALMAC_PORTID1:
+ HALMAC_REG_W8(REG_BCN_CTRL_CLINT0, ctrl_value);
+ break;
+
+ case HALMAC_PORTID2:
+ HALMAC_REG_W8(REG_BCN_CTRL_CLINT1, ctrl_value);
+ break;
+
+ case HALMAC_PORTID3:
+ HALMAC_REG_W8(REG_BCN_CTRL_CLINT2, ctrl_value);
+ break;
+
+ case HALMAC_PORTID4:
+ HALMAC_REG_W8(REG_BCN_CTRL_CLINT3, ctrl_value);
+ break;
+
+ default:
+ break;
+ }
+
+ } else {
+ switch (port) {
+ case HALMAC_PORTID0:
+ ctrl_value = HALMAC_REG_R8(REG_BCN_CTRL);
+ break;
+
+ case HALMAC_PORTID1:
+ ctrl_value = HALMAC_REG_R8(REG_BCN_CTRL_CLINT0);
+ break;
+
+ case HALMAC_PORTID2:
+ ctrl_value = HALMAC_REG_R8(REG_BCN_CTRL_CLINT1);
+ break;
+
+ case HALMAC_PORTID3:
+ ctrl_value = HALMAC_REG_R8(REG_BCN_CTRL_CLINT2);
+ break;
+
+ case HALMAC_PORTID4:
+ ctrl_value = HALMAC_REG_R8(REG_BCN_CTRL_CLINT3);
+ break;
+
+ default:
+ break;
+ }
+
+ if (ctrl_value & BIT_EN_P2P_BCNQ_AREA)
+ ctrl->en_p2p_bcn_area = _TRUE;
+ else
+ ctrl->en_p2p_bcn_area = _FALSE;
+
+ if (ctrl_value & BIT_EN_P2P_CTWINDOW)
+ ctrl->en_p2p_ctwin = _TRUE;
+ else
+ ctrl->en_p2p_ctwin = _FALSE;
+
+ if (ctrl_value & BIT_P0_EN_RXBCN_RPT)
+ ctrl->en_rxbcn_rpt = _TRUE;
+ else
+ ctrl->en_rxbcn_rpt = _FALSE;
+
+ if (ctrl_value & BIT_EN_BCN_FUNCTION)
+ ctrl->en_bcn = _TRUE;
+ else
+ ctrl->en_bcn = _FALSE;
+
+ if (ctrl_value & BIT_DIS_TSF_UDT)
+ ctrl->dis_tsf_udt = _TRUE;
+ else
+ ctrl->dis_tsf_udt = _FALSE;
+
+ if (ctrl_value & BIT_P0_EN_TXBCN_RPT)
+ ctrl->en_txbcn_rpt = _TRUE;
+ else
+ ctrl->en_txbcn_rpt = _FALSE;
+
+ if (ctrl_value & BIT_DIS_RX_BSSID_FIT)
+ ctrl->dis_rx_bssid_fit = _TRUE;
+ else
+ ctrl->dis_rx_bssid_fit = _FALSE;
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_multicast_addr_88xx() - config multicast address
+ * @adapter : the adapter of halmac
+ * @addr : multicast address
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_multicast_addr_88xx(struct halmac_adapter *adapter,
+ union halmac_wlan_addr *addr)
+{
+ u16 addr_h;
+ u32 addr_l;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ addr_l = addr->addr_l_h.low;
+ addr_h = addr->addr_l_h.high;
+
+ addr_l = rtk_le32_to_cpu(addr_l);
+ addr_h = rtk_le16_to_cpu(addr_h);
+
+ HALMAC_REG_W32(REG_MAR, addr_l);
+ HALMAC_REG_W16(REG_MAR + 4, addr_h);
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_operation_mode_88xx() - config operation mode
+ * @adapter : the adapter of halmac
+ * @mode : 802.11 standard(b/g/n/ac)
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_operation_mode_88xx(struct halmac_adapter *adapter,
+ enum halmac_wireless_mode mode)
+{
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_ch_bw_88xx() - config channel & bandwidth
+ * @adapter : the adapter of halmac
+ * @ch : WLAN channel, support 2.4G & 5G
+ * @idx : primary channel index, idx1, idx2, idx3, idx4
+ * @bw : band width, 20, 40, 80, 160, 5 ,10
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_ch_bw_88xx(struct halmac_adapter *adapter, u8 ch,
+ enum halmac_pri_ch_idx idx, enum halmac_bw bw)
+{
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ cfg_pri_ch_idx_88xx(adapter, idx);
+ cfg_bw_88xx(adapter, bw);
+ cfg_ch_88xx(adapter, ch);
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+cfg_ch_88xx(struct halmac_adapter *adapter, u8 ch)
+{
+ u8 value8;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ value8 = HALMAC_REG_R8(REG_CCK_CHECK);
+ value8 = value8 & (~(BIT(7)));
+
+ if (ch > 35)
+ value8 = value8 | BIT(7);
+
+ HALMAC_REG_W8(REG_CCK_CHECK, value8);
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+cfg_pri_ch_idx_88xx(struct halmac_adapter *adapter, enum halmac_pri_ch_idx idx)
+{
+ u8 txsc40 = 0, txsc20 = 0;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ txsc20 = idx;
+ if (txsc20 == HALMAC_CH_IDX_1 || txsc20 == HALMAC_CH_IDX_3)
+ txsc40 = 9;
+ else
+ txsc40 = 10;
+
+ HALMAC_REG_W8(REG_DATA_SC, BIT_TXSC_20M(txsc20) | BIT_TXSC_40M(txsc40));
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_bw_88xx() - config bandwidth
+ * @adapter : the adapter of halmac
+ * @bw : band width, 20, 40, 80, 160, 5 ,10
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_bw_88xx(struct halmac_adapter *adapter, enum halmac_bw bw)
+{
+ u32 value32;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ value32 = HALMAC_REG_R32(REG_WMAC_TRXPTCL_CTL);
+ value32 = value32 & (~(BIT(7) | BIT(8)));
+
+ switch (bw) {
+ case HALMAC_BW_80:
+ value32 = value32 | BIT(7);
+ break;
+ case HALMAC_BW_40:
+ value32 = value32 | BIT(8);
+ break;
+ case HALMAC_BW_20:
+ case HALMAC_BW_10:
+ case HALMAC_BW_5:
+ break;
+ default:
+ break;
+ }
+
+ HALMAC_REG_W32(REG_WMAC_TRXPTCL_CTL, value32);
+
+ /* TODO:Move to change mac clk api later... */
+ value32 = HALMAC_REG_R32(REG_AFE_CTRL1) & ~(BIT(20) | BIT(21));
+ value32 |= (MAC_CLK_HW_DEF_80M << BIT_SHIFT_MAC_CLK_SEL);
+ HALMAC_REG_W32(REG_AFE_CTRL1, value32);
+
+ HALMAC_REG_W8(REG_USTIME_TSF, MAC_CLK_SPEED);
+ HALMAC_REG_W8(REG_USTIME_EDCA, MAC_CLK_SPEED);
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+void
+enable_bb_rf_88xx(struct halmac_adapter *adapter, u8 enable)
+{
+ u8 value8;
+ u32 value32;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ if (enable == 1) {
+ value8 = HALMAC_REG_R8(REG_SYS_FUNC_EN);
+ value8 = value8 | BIT(0) | BIT(1);
+ HALMAC_REG_W8(REG_SYS_FUNC_EN, value8);
+
+ value8 = HALMAC_REG_R8(REG_RF_CTRL);
+ value8 = value8 | BIT(0) | BIT(1) | BIT(2);
+ HALMAC_REG_W8(REG_RF_CTRL, value8);
+
+ value32 = HALMAC_REG_R32(REG_WLRF1);
+ value32 = value32 | BIT(24) | BIT(25) | BIT(26);
+ HALMAC_REG_W32(REG_WLRF1, value32);
+ } else {
+ value8 = HALMAC_REG_R8(REG_SYS_FUNC_EN);
+ value8 = value8 & (~(BIT(0) | BIT(1)));
+ HALMAC_REG_W8(REG_SYS_FUNC_EN, value8);
+
+ value8 = HALMAC_REG_R8(REG_RF_CTRL);
+ value8 = value8 & (~(BIT(0) | BIT(1) | BIT(2)));
+ HALMAC_REG_W8(REG_RF_CTRL, value8);
+
+ value32 = HALMAC_REG_R32(REG_WLRF1);
+ value32 = value32 & (~(BIT(24) | BIT(25) | BIT(26)));
+ HALMAC_REG_W32(REG_WLRF1, value32);
+ }
+}
+
+/**
+ * cfg_la_mode_88xx() - config la mode
+ * @adapter : the adapter of halmac
+ * @mode :
+ * disable : no TXFF space reserved for LA debug
+ * partial : partial TXFF space is reserved for LA debug
+ * full : all TXFF space is reserved for LA debug
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_la_mode_88xx(struct halmac_adapter *adapter, enum halmac_la_mode mode)
+{
+ if (adapter->api_registry.la_mode_en == 0)
+ return HALMAC_RET_NOT_SUPPORT;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ adapter->txff_alloc.la_mode = mode;
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_rxfifo_expand_mode_88xx() - rx fifo expanding
+ * @adapter : the adapter of halmac
+ * @mode :
+ * disable : normal mode
+ * 1 block : Rx FIFO + 1 FIFO block; Tx fifo - 1 FIFO block
+ * 2 block : Rx FIFO + 2 FIFO block; Tx fifo - 2 FIFO block
+ * 3 block : Rx FIFO + 3 FIFO block; Tx fifo - 3 FIFO block
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_rxfifo_expand_mode_88xx(struct halmac_adapter *adapter,
+ enum halmac_rx_fifo_expanding_mode mode)
+{
+ if (adapter->api_registry.rx_exp_en == 0)
+ return HALMAC_RET_NOT_SUPPORT;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ adapter->txff_alloc.rx_fifo_exp_mode = mode;
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+config_security_88xx(struct halmac_adapter *adapter,
+ struct halmac_security_setting *setting)
+{
+ u8 sec_cfg;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ HALMAC_REG_W16(REG_CR, (u16)(HALMAC_REG_R16(REG_CR) | BIT_MAC_SEC_EN));
+
+ if (setting->compare_keyid == 1) {
+ sec_cfg = HALMAC_REG_R8(REG_SECCFG + 1) | BIT(0);
+ HALMAC_REG_W8(REG_SECCFG + 1, sec_cfg);
+ adapter->hw_cfg_info.chk_security_keyid = 1;
+ } else {
+ adapter->hw_cfg_info.chk_security_keyid = 0;
+ }
+
+ sec_cfg = HALMAC_REG_R8(REG_SECCFG);
+
+ /* BC/MC uses default key */
+ /* cam entry 0~3, kei id = 0 -> entry0, kei id = 1 -> entry1... */
+ sec_cfg |= (BIT_TXBCUSEDK | BIT_RXBCUSEDK);
+
+ if (setting->tx_encryption == 1)
+ sec_cfg |= BIT_TXENC;
+ else
+ sec_cfg &= ~BIT_TXENC;
+
+ if (setting->rx_decryption == 1)
+ sec_cfg |= BIT_RXDEC;
+ else
+ sec_cfg &= ~BIT_RXDEC;
+
+ HALMAC_REG_W8(REG_SECCFG, sec_cfg);
+
+ if (setting->bip_enable == 1) {
+ if (adapter->chip_id == HALMAC_CHIP_ID_8822B)
+ return HALMAC_RET_BIP_NO_SUPPORT;
+#if HALMAC_8821C_SUPPORT
+ sec_cfg = HALMAC_REG_R8(REG_WSEC_OPTION + 2);
+
+ if (setting->tx_encryption == 1)
+ sec_cfg |= (BIT(3) | BIT(5));
+ else
+ sec_cfg &= ~(BIT(3) | BIT(5));
+
+ if (setting->rx_decryption == 1)
+ sec_cfg |= (BIT(4) | BIT(6));
+ else
+ sec_cfg &= ~(BIT(4) | BIT(6));
+
+ HALMAC_REG_W8(REG_WSEC_OPTION + 2, sec_cfg);
+#endif
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+u8
+get_used_cam_entry_num_88xx(struct halmac_adapter *adapter,
+ enum hal_security_type sec_type)
+{
+ u8 entry_num;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ switch (sec_type) {
+ case HAL_SECURITY_TYPE_WEP40:
+ case HAL_SECURITY_TYPE_WEP104:
+ case HAL_SECURITY_TYPE_TKIP:
+ case HAL_SECURITY_TYPE_AES128:
+ case HAL_SECURITY_TYPE_GCMP128:
+ case HAL_SECURITY_TYPE_GCMSMS4:
+ case HAL_SECURITY_TYPE_BIP:
+ entry_num = 1;
+ break;
+ case HAL_SECURITY_TYPE_WAPI:
+ case HAL_SECURITY_TYPE_AES256:
+ case HAL_SECURITY_TYPE_GCMP256:
+ entry_num = 2;
+ break;
+ default:
+ entry_num = 0;
+ break;
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return entry_num;
+}
+
+enum halmac_ret_status
+write_cam_88xx(struct halmac_adapter *adapter, u32 idx,
+ struct halmac_cam_entry_info *info)
+{
+ u32 i;
+ u32 cmd = 0x80010000;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+ struct halmac_cam_entry_format *fmt = NULL;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (idx >= adapter->hw_cfg_info.cam_entry_num)
+ return HALMAC_RET_ENTRY_INDEX_ERROR;
+
+ if (info->key_id > 3)
+ return HALMAC_RET_FAIL;
+
+ fmt = (struct halmac_cam_entry_format *)PLTFM_MALLOC(sizeof(*fmt));
+ if (!fmt)
+ return HALMAC_RET_NULL_POINTER;
+ PLTFM_MEMSET(fmt, 0x00, sizeof(*fmt));
+
+ if (adapter->hw_cfg_info.chk_security_keyid == 1)
+ fmt->key_id = info->key_id;
+ fmt->valid = info->valid;
+ PLTFM_MEMCPY(fmt->mac_address, info->mac_address, 6);
+ PLTFM_MEMCPY(fmt->key, info->key, 16);
+
+ switch (info->security_type) {
+ case HAL_SECURITY_TYPE_NONE:
+ fmt->type = 0;
+ break;
+ case HAL_SECURITY_TYPE_WEP40:
+ fmt->type = 1;
+ break;
+ case HAL_SECURITY_TYPE_WEP104:
+ fmt->type = 5;
+ break;
+ case HAL_SECURITY_TYPE_TKIP:
+ fmt->type = 2;
+ break;
+ case HAL_SECURITY_TYPE_AES128:
+ fmt->type = 4;
+ break;
+ case HAL_SECURITY_TYPE_WAPI:
+ fmt->type = 6;
+ break;
+ case HAL_SECURITY_TYPE_AES256:
+ fmt->type = 4;
+ fmt->ext_sectype = 1;
+ break;
+ case HAL_SECURITY_TYPE_GCMP128:
+ fmt->type = 7;
+ break;
+ case HAL_SECURITY_TYPE_GCMP256:
+ case HAL_SECURITY_TYPE_GCMSMS4:
+ fmt->type = 7;
+ fmt->ext_sectype = 1;
+ break;
+ case HAL_SECURITY_TYPE_BIP:
+ fmt->type = (info->unicast == 1) ? 4 : 0;
+ fmt->mgnt = 1;
+ fmt->grp = (info->unicast == 1) ? 0 : 1;
+ break;
+ default:
+ PLTFM_FREE(fmt, sizeof(*fmt));
+ return HALMAC_RET_FAIL;
+ }
+
+ for (i = 0; i < 8; i++) {
+ HALMAC_REG_W32(REG_CAMWRITE, *((u32 *)fmt + i));
+ HALMAC_REG_W32(REG_CAMCMD, cmd | ((idx << 3) + i));
+ }
+
+ if (info->security_type == HAL_SECURITY_TYPE_WAPI ||
+ info->security_type == HAL_SECURITY_TYPE_AES256 ||
+ info->security_type == HAL_SECURITY_TYPE_GCMP256 ||
+ info->security_type == HAL_SECURITY_TYPE_GCMSMS4) {
+ fmt->mic = 1;
+ PLTFM_MEMCPY(fmt->key, info->key_ext, 16);
+ idx++;
+ for (i = 0; i < 8; i++) {
+ HALMAC_REG_W32(REG_CAMWRITE, *((u32 *)fmt + i));
+ HALMAC_REG_W32(REG_CAMCMD, cmd | ((idx << 3) + i));
+ }
+ }
+
+ PLTFM_FREE(fmt, sizeof(*fmt));
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+read_cam_entry_88xx(struct halmac_adapter *adapter, u32 idx,
+ struct halmac_cam_entry_format *content)
+{
+ u32 i;
+ u32 cmd = 0x80000000;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (idx >= adapter->hw_cfg_info.cam_entry_num)
+ return HALMAC_RET_ENTRY_INDEX_ERROR;
+
+ for (i = 0; i < 8; i++) {
+ HALMAC_REG_W32(REG_CAMCMD, cmd | ((idx << 3) + i));
+ *((u32 *)content + i) = HALMAC_REG_R32(REG_CAMREAD);
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+clear_cam_entry_88xx(struct halmac_adapter *adapter, u32 idx)
+{
+ u32 i;
+ u32 cmd = 0x80010000;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+ struct halmac_cam_entry_format *fmt = NULL;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (idx >= adapter->hw_cfg_info.cam_entry_num)
+ return HALMAC_RET_ENTRY_INDEX_ERROR;
+
+ fmt = (struct halmac_cam_entry_format *)PLTFM_MALLOC(sizeof(*fmt));
+ if (!fmt)
+ return HALMAC_RET_NULL_POINTER;
+ PLTFM_MEMSET(fmt, 0x00, sizeof(*fmt));
+
+ for (i = 0; i < 8; i++) {
+ HALMAC_REG_W32(REG_CAMWRITE, *((u32 *)fmt + i));
+ HALMAC_REG_W32(REG_CAMCMD, cmd | ((idx << 3) + i));
+ }
+
+ PLTFM_FREE(fmt, sizeof(*fmt));
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+void
+rx_shift_88xx(struct halmac_adapter *adapter, u8 enable)
+{
+ u8 value8;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ value8 = HALMAC_REG_R8(REG_TXDMA_PQ_MAP);
+
+ if (enable == 1)
+ HALMAC_REG_W8(REG_TXDMA_PQ_MAP, value8 | BIT(1));
+ else
+ HALMAC_REG_W8(REG_TXDMA_PQ_MAP, value8 & ~(BIT(1)));
+}
+
+/**
+ * cfg_edca_para_88xx() - config edca parameter
+ * @adapter : the adapter of halmac
+ * @acq_id : VO/VI/BE/BK
+ * @param : aifs, cw, txop limit
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_edca_para_88xx(struct halmac_adapter *adapter, enum halmac_acq_id acq_id,
+ struct halmac_edca_para *param)
+{
+ u32 offset;
+ u32 value32;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ switch (acq_id) {
+ case HALMAC_ACQ_ID_VO:
+ offset = REG_EDCA_VO_PARAM;
+ break;
+ case HALMAC_ACQ_ID_VI:
+ offset = REG_EDCA_VI_PARAM;
+ break;
+ case HALMAC_ACQ_ID_BE:
+ offset = REG_EDCA_BE_PARAM;
+ break;
+ case HALMAC_ACQ_ID_BK:
+ offset = REG_EDCA_BK_PARAM;
+ break;
+ default:
+ return HALMAC_RET_SWITCH_CASE_ERROR;
+ }
+
+ param->txop_limit &= 0x7FF;
+ value32 = (param->aifs) | (param->cw << 8) | (param->txop_limit << 16);
+
+ HALMAC_REG_W32(offset, value32);
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+void
+rx_clk_gate_88xx(struct halmac_adapter *adapter, u8 enable)
+{
+ u8 value8;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ value8 = HALMAC_REG_R8(REG_RCR + 2);
+
+ if (enable == _TRUE)
+ HALMAC_REG_W8(REG_RCR + 2, value8 & ~(BIT(3)));
+ else
+ HALMAC_REG_W8(REG_RCR + 2, value8 | BIT(3));
+}
+
+enum halmac_ret_status
+rx_cut_amsdu_cfg_88xx(struct halmac_adapter *adapter,
+ struct halmac_cut_amsdu_cfg *cfg)
+{
+ return HALMAC_RET_NOT_SUPPORT;
+}
+
+enum halmac_ret_status
+fast_edca_cfg_88xx(struct halmac_adapter *adapter,
+ struct halmac_fast_edca_cfg *cfg)
+{
+ u16 value16;
+ u32 offset;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ switch (cfg->acq_id) {
+ case HALMAC_ACQ_ID_VO:
+ offset = REG_FAST_EDCA_VOVI_SETTING;
+ break;
+ case HALMAC_ACQ_ID_VI:
+ offset = REG_FAST_EDCA_VOVI_SETTING + 2;
+ break;
+ case HALMAC_ACQ_ID_BE:
+ offset = REG_FAST_EDCA_BEBK_SETTING;
+ break;
+ case HALMAC_ACQ_ID_BK:
+ offset = REG_FAST_EDCA_BEBK_SETTING + 2;
+ break;
+ default:
+ return HALMAC_RET_SWITCH_CASE_ERROR;
+ }
+
+ value16 = HALMAC_REG_R16(offset);
+ value16 &= 0xFF;
+ value16 = value16 | (cfg->queue_to << 8);
+
+ HALMAC_REG_W16(offset, value16);
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * get_mac_addr_88xx() - get mac address
+ * @adapter : the adapter of halmac
+ * @port : 0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4
+ * @addr : mac address
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+get_mac_addr_88xx(struct halmac_adapter *adapter, u8 port,
+ union halmac_wlan_addr *addr)
+{
+ u16 mac_addr_h;
+ u32 mac_addr_l;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (port >= HALMAC_PORTID_NUM) {
+ PLTFM_MSG_ERR("[ERR]port index >= 5\n");
+ return HALMAC_RET_PORT_NOT_SUPPORT;
+ }
+
+ switch (port) {
+ case HALMAC_PORTID0:
+ mac_addr_l = HALMAC_REG_R32(REG_MACID);
+ mac_addr_h = HALMAC_REG_R16(REG_MACID + 4);
+ break;
+ case HALMAC_PORTID1:
+ mac_addr_l = HALMAC_REG_R32(REG_MACID1);
+ mac_addr_h = HALMAC_REG_R16(REG_MACID1 + 4);
+ break;
+ case HALMAC_PORTID2:
+ mac_addr_l = HALMAC_REG_R32(REG_MACID2);
+ mac_addr_h = HALMAC_REG_R16(REG_MACID2 + 4);
+ break;
+ case HALMAC_PORTID3:
+ mac_addr_l = HALMAC_REG_R32(REG_MACID3);
+ mac_addr_h = HALMAC_REG_R16(REG_MACID3 + 4);
+ break;
+ case HALMAC_PORTID4:
+ mac_addr_l = HALMAC_REG_R32(REG_MACID4);
+ mac_addr_h = HALMAC_REG_R16(REG_MACID4 + 4);
+ break;
+ default:
+ return HALMAC_RET_PORT_NOT_SUPPORT;
+ }
+
+ mac_addr_l = rtk_le32_to_cpu(mac_addr_l);
+ mac_addr_h = rtk_le16_to_cpu(mac_addr_h);
+
+ addr->addr_l_h.low = mac_addr_l;
+ addr->addr_l_h.high = mac_addr_h;
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+#endif /* HALMAC_88XX_SUPPORT */
diff --git a/hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.h b/hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.h
new file mode 100644
index 0000000..0a6b4e1
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_cfg_wmac_88xx.h
@@ -0,0 +1,123 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_CFG_WMAC_88XX_H_
+#define _HALMAC_CFG_WMAC_88XX_H_
+
+#include "../halmac_api.h"
+
+#if HALMAC_88XX_SUPPORT
+
+enum halmac_ret_status
+cfg_mac_addr_88xx(struct halmac_adapter *adapter, u8 port,
+ union halmac_wlan_addr *addr);
+
+enum halmac_ret_status
+cfg_bssid_88xx(struct halmac_adapter *adapter, u8 port,
+ union halmac_wlan_addr *addr);
+
+enum halmac_ret_status
+cfg_transmitter_addr_88xx(struct halmac_adapter *adapter, u8 port,
+ union halmac_wlan_addr *addr);
+
+enum halmac_ret_status
+cfg_net_type_88xx(struct halmac_adapter *adapter, u8 port,
+ enum halmac_network_type_select net_type);
+
+enum halmac_ret_status
+cfg_tsf_rst_88xx(struct halmac_adapter *adapter, u8 port);
+
+enum halmac_ret_status
+cfg_bcn_space_88xx(struct halmac_adapter *adapter, u8 port, u32 bcn_space);
+
+enum halmac_ret_status
+rw_bcn_ctrl_88xx(struct halmac_adapter *adapter, u8 port, u8 write_en,
+ struct halmac_bcn_ctrl *ctrl);
+
+enum halmac_ret_status
+cfg_multicast_addr_88xx(struct halmac_adapter *adapter,
+ union halmac_wlan_addr *addr);
+
+enum halmac_ret_status
+cfg_operation_mode_88xx(struct halmac_adapter *adapter,
+ enum halmac_wireless_mode mode);
+
+enum halmac_ret_status
+cfg_ch_bw_88xx(struct halmac_adapter *adapter, u8 ch,
+ enum halmac_pri_ch_idx idx, enum halmac_bw bw);
+
+enum halmac_ret_status
+cfg_ch_88xx(struct halmac_adapter *adapter, u8 ch);
+
+enum halmac_ret_status
+cfg_pri_ch_idx_88xx(struct halmac_adapter *adapter, enum halmac_pri_ch_idx idx);
+
+enum halmac_ret_status
+cfg_bw_88xx(struct halmac_adapter *adapter, enum halmac_bw bw);
+
+void
+enable_bb_rf_88xx(struct halmac_adapter *adapter, u8 enable);
+
+enum halmac_ret_status
+cfg_la_mode_88xx(struct halmac_adapter *adapter, enum halmac_la_mode mode);
+
+enum halmac_ret_status
+cfg_rxfifo_expand_mode_88xx(struct halmac_adapter *adapter,
+ enum halmac_rx_fifo_expanding_mode mode);
+
+enum halmac_ret_status
+config_security_88xx(struct halmac_adapter *adapter,
+ struct halmac_security_setting *setting);
+
+u8
+get_used_cam_entry_num_88xx(struct halmac_adapter *adapter,
+ enum hal_security_type sec_type);
+
+enum halmac_ret_status
+write_cam_88xx(struct halmac_adapter *adapter, u32 idx,
+ struct halmac_cam_entry_info *info);
+
+enum halmac_ret_status
+read_cam_entry_88xx(struct halmac_adapter *adapter, u32 idx,
+ struct halmac_cam_entry_format *content);
+
+enum halmac_ret_status
+clear_cam_entry_88xx(struct halmac_adapter *adapter, u32 idx);
+
+void
+rx_shift_88xx(struct halmac_adapter *adapter, u8 enable);
+
+enum halmac_ret_status
+cfg_edca_para_88xx(struct halmac_adapter *adapter, enum halmac_acq_id acq_id,
+ struct halmac_edca_para *param);
+
+void
+rx_clk_gate_88xx(struct halmac_adapter *adapter, u8 enable);
+
+enum halmac_ret_status
+rx_cut_amsdu_cfg_88xx(struct halmac_adapter *adapter,
+ struct halmac_cut_amsdu_cfg *cfg);
+
+enum halmac_ret_status
+fast_edca_cfg_88xx(struct halmac_adapter *adapter,
+ struct halmac_fast_edca_cfg *cfg);
+
+enum halmac_ret_status
+get_mac_addr_88xx(struct halmac_adapter *adapter, u8 port,
+ union halmac_wlan_addr *addr);
+
+#endif/* HALMAC_88XX_SUPPORT */
+
+#endif/* _HALMAC_CFG_WMAC_88XX_H_ */
diff --git a/hal/halmac/halmac_88xx/halmac_common_88xx.c b/hal/halmac/halmac_88xx/halmac_common_88xx.c
new file mode 100644
index 0000000..6e08060
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_common_88xx.c
@@ -0,0 +1,2858 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_common_88xx.h"
+#include "halmac_88xx_cfg.h"
+#include "halmac_init_88xx.h"
+#include "halmac_cfg_wmac_88xx.h"
+#include "halmac_efuse_88xx.h"
+#include "halmac_bb_rf_88xx.h"
+#include "halmac_usb_88xx.h"
+#include "halmac_sdio_88xx.h"
+#include "halmac_pcie_88xx.h"
+#include "halmac_mimo_88xx.h"
+
+#if HALMAC_88XX_SUPPORT
+
+#define CFG_PARAM_H2C_INFO_SIZE 12
+#define ORIGINAL_H2C_CMD_SIZE 8
+
+#define WLHDR_PROT_VER 0
+
+#define WLHDR_TYPE_MGMT 0
+#define WLHDR_TYPE_CTRL 1
+#define WLHDR_TYPE_DATA 2
+
+/* mgmt frame */
+#define WLHDR_SUB_TYPE_ASSOC_REQ 0
+#define WLHDR_SUB_TYPE_ASSOC_RSPNS 1
+#define WLHDR_SUB_TYPE_REASSOC_REQ 2
+#define WLHDR_SUB_TYPE_REASSOC_RSPNS 3
+#define WLHDR_SUB_TYPE_PROBE_REQ 4
+#define WLHDR_SUB_TYPE_PROBE_RSPNS 5
+#define WLHDR_SUB_TYPE_BCN 8
+#define WLHDR_SUB_TYPE_DISASSOC 10
+#define WLHDR_SUB_TYPE_AUTH 11
+#define WLHDR_SUB_TYPE_DEAUTH 12
+#define WLHDR_SUB_TYPE_ACTION 13
+#define WLHDR_SUB_TYPE_ACTION_NOACK 14
+
+/* ctrl frame */
+#define WLHDR_SUB_TYPE_BF_RPT_POLL 4
+#define WLHDR_SUB_TYPE_NDPA 5
+
+/* data frame */
+#define WLHDR_SUB_TYPE_DATA 0
+#define WLHDR_SUB_TYPE_NULL 4
+#define WLHDR_SUB_TYPE_QOS_DATA 8
+#define WLHDR_SUB_TYPE_QOS_NULL 12
+
+#define LTECOEX_ACCESS_CTRL REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1
+
+struct wlhdr_frame_ctrl {
+ u16 protocol:2;
+ u16 type:2;
+ u16 sub_type:4;
+ u16 to_ds:1;
+ u16 from_ds:1;
+ u16 more_frag:1;
+ u16 retry:1;
+ u16 pwr_mgmt:1;
+ u16 more_data:1;
+ u16 protect_frame:1;
+ u16 order:1;
+};
+
+static enum halmac_ret_status
+parse_c2h_pkt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+static enum halmac_ret_status
+get_c2h_dbg_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+static enum halmac_ret_status
+get_h2c_ack_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+static enum halmac_ret_status
+get_scan_rpt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+static enum halmac_ret_status
+get_h2c_ack_cfg_param_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+static enum halmac_ret_status
+get_h2c_ack_update_pkt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+static enum halmac_ret_status
+get_h2c_ack_update_datapkt_88xx(struct halmac_adapter *adapter, u8 *buf,
+ u32 size);
+
+static enum halmac_ret_status
+get_h2c_ack_run_datapkt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+static enum halmac_ret_status
+get_h2c_ack_ch_switch_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+static enum halmac_ret_status
+malloc_cfg_param_buf_88xx(struct halmac_adapter *adapter, u8 full_fifo);
+
+static enum halmac_cmd_construct_state
+cfg_param_cmd_cnstr_state_88xx(struct halmac_adapter *adapter);
+
+static enum halmac_ret_status
+proc_cfg_param_88xx(struct halmac_adapter *adapter,
+ struct halmac_phy_parameter_info *param, u8 full_fifo);
+
+static enum halmac_ret_status
+send_cfg_param_h2c_88xx(struct halmac_adapter *adapter);
+
+static enum halmac_ret_status
+cnv_cfg_param_state_88xx(struct halmac_adapter *adapter,
+ enum halmac_cmd_construct_state dest_state);
+
+static enum halmac_ret_status
+add_param_buf_88xx(struct halmac_adapter *adapter,
+ struct halmac_phy_parameter_info *param, u8 *buf,
+ u8 *end_cmd);
+
+static enum halmac_ret_status
+gen_cfg_param_h2c_88xx(struct halmac_adapter *adapter, u8 *buff);
+
+static enum halmac_ret_status
+send_h2c_update_packet_88xx(struct halmac_adapter *adapter,
+ enum halmac_packet_id pkt_id, u8 *pkt, u32 size);
+
+static enum halmac_ret_status
+send_bt_coex_cmd_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
+ u8 ack);
+
+static enum halmac_ret_status
+read_buf_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
+ enum hal_fifo_sel sel, u8 *data);
+
+static enum halmac_cmd_construct_state
+scan_cmd_cnstr_state_88xx(struct halmac_adapter *adapter);
+
+static enum halmac_ret_status
+cnv_scan_state_88xx(struct halmac_adapter *adapter,
+ enum halmac_cmd_construct_state dest_state);
+
+static enum halmac_ret_status
+proc_ctrl_ch_switch_88xx(struct halmac_adapter *adapter,
+ struct halmac_ch_switch_option *opt);
+
+static enum halmac_ret_status
+proc_p2pps_88xx(struct halmac_adapter *adapter, struct halmac_p2pps *info);
+
+static enum halmac_ret_status
+get_cfg_param_status_88xx(struct halmac_adapter *adapter,
+ enum halmac_cmd_process_status *proc_status);
+
+static enum halmac_ret_status
+get_ch_switch_status_88xx(struct halmac_adapter *adapter,
+ enum halmac_cmd_process_status *proc_status);
+
+static enum halmac_ret_status
+get_update_packet_status_88xx(struct halmac_adapter *adapter,
+ enum halmac_cmd_process_status *proc_status);
+
+static enum halmac_ret_status
+pwr_sub_seq_parser_88xx(struct halmac_adapter *adapter, u8 cut, u8 intf,
+ struct halmac_wlan_pwr_cfg *cmd);
+
+static void
+pwr_state_88xx(struct halmac_adapter *adapter, enum halmac_mac_power *state);
+
+static enum halmac_ret_status
+pwr_cmd_polling_88xx(struct halmac_adapter *adapter,
+ struct halmac_wlan_pwr_cfg *cmd);
+
+static void
+get_pq_mapping_88xx(struct halmac_adapter *adapter,
+ struct halmac_rqpn_map *mapping);
+
+static void
+dump_reg_sdio_88xx(struct halmac_adapter *adapter);
+
+static enum halmac_ret_status
+wlhdr_valid_88xx(struct halmac_adapter *adapter, u8 *buf);
+
+static u8
+wlhdr_mgmt_valid_88xx(struct halmac_adapter *adapter,
+ struct wlhdr_frame_ctrl *wlhdr);
+
+static u8
+wlhdr_ctrl_valid_88xx(struct halmac_adapter *adapter,
+ struct wlhdr_frame_ctrl *wlhdr);
+
+static u8
+wlhdr_data_valid_88xx(struct halmac_adapter *adapter,
+ struct wlhdr_frame_ctrl *wlhdr);
+
+static void
+dump_reg_88xx(struct halmac_adapter *adapter);
+
+/**
+ * ofld_func_cfg_88xx() - config offload function
+ * @adapter : the adapter of halmac
+ * @info : offload function information
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+ofld_func_cfg_88xx(struct halmac_adapter *adapter,
+ struct halmac_ofld_func_info *info)
+{
+ if (adapter->intf == HALMAC_INTERFACE_SDIO &&
+ info->rsvd_pg_drv_buf_max_sz > SDIO_TX_MAX_SIZE_88XX)
+ return HALMAC_RET_FAIL;
+
+ adapter->pltfm_info.malloc_size = info->halmac_malloc_max_sz;
+ adapter->pltfm_info.rsvd_pg_size = info->rsvd_pg_drv_buf_max_sz;
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * dl_drv_rsvd_page_88xx() - download packet to rsvd page
+ * @adapter : the adapter of halmac
+ * @pg_offset : page offset of driver's rsvd page
+ * @halmac_buf : data to be downloaded, tx_desc is not included
+ * @halmac_size : data size to be downloaded
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+dl_drv_rsvd_page_88xx(struct halmac_adapter *adapter, u8 pg_offset, u8 *buf,
+ u32 size)
+{
+ enum halmac_ret_status status;
+ u32 pg_size;
+ u32 pg_num = 0;
+ u16 pg_addr = 0;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ pg_size = adapter->hw_cfg_info.page_size;
+ pg_num = size / pg_size + ((size & (pg_size - 1)) ? 1 : 0);
+ if (pg_offset + pg_num > adapter->txff_alloc.rsvd_drv_pg_num) {
+ PLTFM_MSG_ERR("[ERR] pkt overflow!!\n");
+ return HALMAC_RET_DRV_DL_ERR;
+ }
+
+ pg_addr = adapter->txff_alloc.rsvd_drv_addr + pg_offset;
+
+ status = dl_rsvd_page_88xx(adapter, pg_addr, buf, size);
+
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]dl rsvd page fail!!\n");
+ return status;
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+dl_rsvd_page_88xx(struct halmac_adapter *adapter, u16 pg_addr, u8 *buf,
+ u32 size)
+{
+ u8 restore[2];
+ u8 value8;
+ u16 rsvd_pg_head;
+ u32 cnt;
+ enum halmac_rsvd_pg_state *state = &adapter->halmac_state.rsvd_pg_state;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ if (size == 0) {
+ PLTFM_MSG_TRACE("[TRACE]pkt size = 0\n");
+ return HALMAC_RET_ZERO_LEN_RSVD_PACKET;
+ }
+
+ if (*state == HALMAC_RSVD_PG_STATE_BUSY)
+ return HALMAC_RET_BUSY_STATE;
+
+ *state = HALMAC_RSVD_PG_STATE_BUSY;
+
+ pg_addr &= BIT_MASK_BCN_HEAD_1_V1;
+ HALMAC_REG_W16(REG_FIFOPAGE_CTRL_2, (u16)(pg_addr | BIT(15)));
+
+ value8 = HALMAC_REG_R8(REG_CR + 1);
+ restore[0] = value8;
+ value8 = (u8)(value8 | BIT(0));
+ HALMAC_REG_W8(REG_CR + 1, value8);
+
+ value8 = HALMAC_REG_R8(REG_FWHW_TXQ_CTRL + 2);
+ restore[1] = value8;
+ value8 = (u8)(value8 & ~(BIT(6)));
+ HALMAC_REG_W8(REG_FWHW_TXQ_CTRL + 2, value8);
+
+ if (PLTFM_SEND_RSVD_PAGE(buf, size) == _FALSE) {
+ PLTFM_MSG_ERR("[ERR]send rvsd pg(pltfm)!!\n");
+ status = HALMAC_RET_DL_RSVD_PAGE_FAIL;
+ goto DL_RSVD_PG_END;
+ }
+
+ cnt = 1000;
+ while (!(HALMAC_REG_R8(REG_FIFOPAGE_CTRL_2 + 1) & BIT(7))) {
+ PLTFM_DELAY_US(10);
+ cnt--;
+ if (cnt == 0) {
+ PLTFM_MSG_ERR("[ERR]bcn valid!!\n");
+ status = HALMAC_RET_POLLING_BCN_VALID_FAIL;
+ break;
+ }
+ }
+DL_RSVD_PG_END:
+ rsvd_pg_head = adapter->txff_alloc.rsvd_boundary;
+ HALMAC_REG_W16(REG_FIFOPAGE_CTRL_2, rsvd_pg_head | BIT(15));
+ HALMAC_REG_W8(REG_FWHW_TXQ_CTRL + 2, restore[1]);
+ HALMAC_REG_W8(REG_CR + 1, restore[0]);
+
+ *state = HALMAC_RSVD_PG_STATE_IDLE;
+
+ return status;
+}
+
+enum halmac_ret_status
+get_hw_value_88xx(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,
+ void *value)
+{
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ switch (hw_id) {
+ case HALMAC_HW_RQPN_MAPPING:
+ get_pq_mapping_88xx(adapter, (struct halmac_rqpn_map *)value);
+ break;
+ case HALMAC_HW_EFUSE_SIZE:
+ *(u32 *)value = adapter->hw_cfg_info.efuse_size;
+ break;
+ case HALMAC_HW_EEPROM_SIZE:
+ *(u32 *)value = adapter->hw_cfg_info.eeprom_size;
+ break;
+ case HALMAC_HW_BT_BANK_EFUSE_SIZE:
+ *(u32 *)value = adapter->hw_cfg_info.bt_efuse_size;
+ break;
+ case HALMAC_HW_BT_BANK1_EFUSE_SIZE:
+ case HALMAC_HW_BT_BANK2_EFUSE_SIZE:
+ *(u32 *)value = 0;
+ break;
+ case HALMAC_HW_TXFIFO_SIZE:
+ *(u32 *)value = adapter->hw_cfg_info.tx_fifo_size;
+ break;
+ case HALMAC_HW_RXFIFO_SIZE:
+ *(u32 *)value = adapter->hw_cfg_info.rx_fifo_size;
+ break;
+ case HALMAC_HW_RSVD_PG_BNDY:
+ *(u16 *)value = adapter->txff_alloc.rsvd_drv_addr;
+ break;
+ case HALMAC_HW_CAM_ENTRY_NUM:
+ *(u8 *)value = adapter->hw_cfg_info.cam_entry_num;
+ break;
+ case HALMAC_HW_WLAN_EFUSE_AVAILABLE_SIZE:
+ get_efuse_available_size_88xx(adapter, (u32 *)value);
+ break;
+ case HALMAC_HW_IC_VERSION:
+ *(u8 *)value = adapter->chip_ver;
+ break;
+ case HALMAC_HW_PAGE_SIZE:
+ *(u32 *)value = adapter->hw_cfg_info.page_size;
+ break;
+ case HALMAC_HW_TX_AGG_ALIGN_SIZE:
+ *(u16 *)value = adapter->hw_cfg_info.tx_align_size;
+ break;
+ case HALMAC_HW_RX_AGG_ALIGN_SIZE:
+ *(u8 *)value = 8;
+ break;
+ case HALMAC_HW_DRV_INFO_SIZE:
+ *(u8 *)value = adapter->drv_info_size;
+ break;
+ case HALMAC_HW_TXFF_ALLOCATION:
+ PLTFM_MEMCPY(value, &adapter->txff_alloc,
+ sizeof(struct halmac_txff_allocation));
+ break;
+ case HALMAC_HW_RSVD_EFUSE_SIZE:
+ *(u32 *)value = get_rsvd_efuse_size_88xx(adapter);
+ break;
+ case HALMAC_HW_FW_HDR_SIZE:
+ *(u32 *)value = WLAN_FW_HDR_SIZE;
+ break;
+ case HALMAC_HW_TX_DESC_SIZE:
+ *(u32 *)value = adapter->hw_cfg_info.txdesc_size;
+ break;
+ case HALMAC_HW_RX_DESC_SIZE:
+ *(u32 *)value = adapter->hw_cfg_info.rxdesc_size;
+ break;
+ case HALMAC_HW_ORI_H2C_SIZE:
+ *(u32 *)value = ORIGINAL_H2C_CMD_SIZE;
+ break;
+ case HALMAC_HW_RSVD_DRV_PGNUM:
+ *(u16 *)value = adapter->txff_alloc.rsvd_drv_pg_num;
+ break;
+ case HALMAC_HW_TX_PAGE_SIZE:
+ *(u16 *)value = TX_PAGE_SIZE_88XX;
+ break;
+ case HALMAC_HW_USB_TXAGG_DESC_NUM:
+ *(u8 *)value = adapter->hw_cfg_info.usb_txagg_num;
+ break;
+ case HALMAC_HW_AC_OQT_SIZE:
+ *(u8 *)value = adapter->hw_cfg_info.ac_oqt_size;
+ break;
+ case HALMAC_HW_NON_AC_OQT_SIZE:
+ *(u8 *)value = adapter->hw_cfg_info.non_ac_oqt_size;
+ break;
+ case HALMAC_HW_AC_QUEUE_NUM:
+ *(u8 *)value = adapter->hw_cfg_info.acq_num;
+ break;
+ case HALMAC_HW_PWR_STATE:
+ pwr_state_88xx(adapter, (enum halmac_mac_power *)value);
+ break;
+ default:
+ return HALMAC_RET_PARA_NOT_SUPPORT;
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static void
+get_pq_mapping_88xx(struct halmac_adapter *adapter,
+ struct halmac_rqpn_map *mapping)
+{
+ mapping->dma_map_vo = adapter->pq_map[HALMAC_PQ_MAP_VO];
+ mapping->dma_map_vi = adapter->pq_map[HALMAC_PQ_MAP_VI];
+ mapping->dma_map_be = adapter->pq_map[HALMAC_PQ_MAP_BE];
+ mapping->dma_map_bk = adapter->pq_map[HALMAC_PQ_MAP_BK];
+ mapping->dma_map_mg = adapter->pq_map[HALMAC_PQ_MAP_MG];
+ mapping->dma_map_hi = adapter->pq_map[HALMAC_PQ_MAP_HI];
+}
+
+/**
+ * set_hw_value_88xx() -set hw config value
+ * @adapter : the adapter of halmac
+ * @hw_id : hw id for driver to config
+ * @value : hw value, reference table to get data type
+ * Author : KaiYuan Chang / Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+set_hw_value_88xx(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,
+ void *value)
+{
+ enum halmac_ret_status status;
+ struct halmac_tx_page_threshold_info *tx_th_info;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (!value) {
+ PLTFM_MSG_ERR("[ERR]null ptr-set hw value\n");
+ return HALMAC_RET_NULL_POINTER;
+ }
+
+ switch (hw_id) {
+ case HALMAC_HW_USB_MODE:
+ status = set_usb_mode_88xx(adapter,
+ *(enum halmac_usb_mode *)value);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+ break;
+ case HALMAC_HW_BANDWIDTH:
+ cfg_bw_88xx(adapter, *(enum halmac_bw *)value);
+ break;
+ case HALMAC_HW_CHANNEL:
+ cfg_ch_88xx(adapter, *(u8 *)value);
+ break;
+ case HALMAC_HW_PRI_CHANNEL_IDX:
+ cfg_pri_ch_idx_88xx(adapter, *(enum halmac_pri_ch_idx *)value);
+ break;
+ case HALMAC_HW_EN_BB_RF:
+ enable_bb_rf_88xx(adapter, *(u8 *)value);
+ break;
+ case HALMAC_HW_SDIO_TX_PAGE_THRESHOLD:
+ tx_th_info = (struct halmac_tx_page_threshold_info *)value;
+ cfg_sdio_tx_page_threshold_88xx(adapter, tx_th_info);
+ break;
+ case HALMAC_HW_RX_SHIFT:
+ rx_shift_88xx(adapter, *(u8 *)value);
+ break;
+ case HALMAC_HW_TXDESC_CHECKSUM:
+ tx_desc_chksum_88xx(adapter, *(u8 *)value);
+ break;
+ case HALMAC_HW_RX_CLK_GATE:
+ rx_clk_gate_88xx(adapter, *(u8 *)value);
+ break;
+ case HALMAC_HW_FAST_EDCA:
+ fast_edca_cfg_88xx(adapter,
+ (struct halmac_fast_edca_cfg *)value);
+ break;
+ default:
+ return HALMAC_RET_PARA_NOT_SUPPORT;
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+set_h2c_pkt_hdr_88xx(struct halmac_adapter *adapter, u8 *hdr,
+ struct halmac_h2c_header_info *info, u16 *seq_num)
+{
+ u16 total_size;
+
+ PLTFM_MSG_TRACE("[TRACE]%s!!\n", __func__);
+
+ total_size = H2C_PKT_HDR_SIZE_88XX + info->content_size;
+ FW_OFFLOAD_H2C_SET_TOTAL_LEN(hdr, total_size);
+ FW_OFFLOAD_H2C_SET_SUB_CMD_ID(hdr, info->sub_cmd_id);
+
+ FW_OFFLOAD_H2C_SET_CATEGORY(hdr, 0x01);
+ FW_OFFLOAD_H2C_SET_CMD_ID(hdr, 0xFF);
+
+ PLTFM_MUTEX_LOCK(&adapter->h2c_seq_mutex);
+ FW_OFFLOAD_H2C_SET_SEQ_NUM(hdr, adapter->h2c_info.seq_num);
+ *seq_num = adapter->h2c_info.seq_num;
+ (adapter->h2c_info.seq_num)++;
+ PLTFM_MUTEX_UNLOCK(&adapter->h2c_seq_mutex);
+
+ if (info->ack == _TRUE)
+ FW_OFFLOAD_H2C_SET_ACK(hdr, _TRUE);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+send_h2c_pkt_88xx(struct halmac_adapter *adapter, u8 *pkt)
+{
+ u32 cnt = 100;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ while (adapter->h2c_info.buf_fs <= H2C_PKT_SIZE_88XX) {
+ get_h2c_buf_free_space_88xx(adapter);
+ cnt--;
+ if (cnt == 0) {
+ PLTFM_MSG_ERR("[ERR]h2c free space!!\n");
+ return HALMAC_RET_H2C_SPACE_FULL;
+ }
+ }
+
+ cnt = 100;
+ do {
+ if (PLTFM_SEND_H2C_PKT(pkt, H2C_PKT_SIZE_88XX) == _TRUE)
+ break;
+ cnt--;
+ if (cnt == 0) {
+ PLTFM_MSG_ERR("[ERR]pltfm - sned h2c pkt!!\n");
+ return HALMAC_RET_SEND_H2C_FAIL;
+ }
+ PLTFM_DELAY_US(5);
+
+ } while (1);
+
+ adapter->h2c_info.buf_fs -= H2C_PKT_SIZE_88XX;
+
+ return status;
+}
+
+enum halmac_ret_status
+get_h2c_buf_free_space_88xx(struct halmac_adapter *adapter)
+{
+ u32 hw_wptr;
+ u32 fw_rptr;
+ struct halmac_h2c_info *info = &adapter->h2c_info;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ hw_wptr = HALMAC_REG_R32(REG_H2C_PKT_WRITEADDR) & BIT_MASK_H2C_WR_ADDR;
+ fw_rptr = HALMAC_REG_R32(REG_H2C_PKT_READADDR) & BIT_MASK_H2C_READ_ADDR;
+
+ if (hw_wptr >= fw_rptr)
+ info->buf_fs = info->buf_size - (hw_wptr - fw_rptr);
+ else
+ info->buf_fs = fw_rptr - hw_wptr;
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * get_c2h_info_88xx() - process halmac C2H packet
+ * @adapter : the adapter of halmac
+ * @buf : RX Packet pointer
+ * @size : RX Packet size
+ * Author : KaiYuan Chang/Ivan Lin
+ *
+ * Used to process c2h packet info from RX path. After receiving the packet,
+ * user need to call this api and pass the packet pointer.
+ *
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+get_c2h_info_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ if (GET_RX_DESC_C2H(buf) == _TRUE) {
+ PLTFM_MSG_TRACE("[TRACE]Parse c2h pkt\n");
+
+ status = parse_c2h_pkt_88xx(adapter, buf, size);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]Parse c2h pkt\n");
+ return status;
+ }
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+parse_c2h_pkt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+ u8 cmd_id, sub_cmd_id;
+ u8 *c2h_pkt = buf + adapter->hw_cfg_info.rxdesc_size;
+ u32 c2h_size = size - adapter->hw_cfg_info.rxdesc_size;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ cmd_id = (u8)C2H_HDR_GET_CMD_ID(c2h_pkt);
+
+ if (cmd_id != 0xFF) {
+ PLTFM_MSG_TRACE("[TRACE]Not 0xFF cmd!!\n");
+ return HALMAC_RET_C2H_NOT_HANDLED;
+ }
+
+ sub_cmd_id = (u8)C2H_HDR_GET_C2H_SUB_CMD_ID(c2h_pkt);
+
+ switch (sub_cmd_id) {
+ case C2H_SUB_CMD_ID_C2H_DBG:
+ status = get_c2h_dbg_88xx(adapter, c2h_pkt, c2h_size);
+ break;
+ case C2H_SUB_CMD_ID_H2C_ACK_HDR:
+ status = get_h2c_ack_88xx(adapter, c2h_pkt, c2h_size);
+ break;
+ case C2H_SUB_CMD_ID_BT_COEX_INFO:
+ status = HALMAC_RET_C2H_NOT_HANDLED;
+ break;
+ case C2H_SUB_CMD_ID_SCAN_STATUS_RPT:
+ status = get_scan_rpt_88xx(adapter, c2h_pkt, c2h_size);
+ break;
+ case C2H_SUB_CMD_ID_PSD_DATA:
+ status = get_psd_data_88xx(adapter, c2h_pkt, c2h_size);
+ break;
+ case C2H_SUB_CMD_ID_EFUSE_DATA:
+ status = get_efuse_data_88xx(adapter, c2h_pkt, c2h_size);
+ break;
+ default:
+ PLTFM_MSG_WARN("[WARN]Sub cmd id!!\n");
+ status = HALMAC_RET_C2H_NOT_HANDLED;
+ break;
+ }
+
+ return status;
+}
+
+static enum halmac_ret_status
+get_c2h_dbg_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+ u8 i;
+ u8 next_msg = 0;
+ u8 cur_msg = 0;
+ u8 msg_len = 0;
+ char *c2h_buf = (char *)NULL;
+ u8 content_len = 0;
+ u8 seq_num = 0;
+
+ content_len = (u8)C2H_HDR_GET_LEN((u8 *)buf);
+
+ if (content_len > C2H_DBG_CONTENT_MAX_LENGTH) {
+ PLTFM_MSG_ERR("[ERR]c2h size > max len!\n");
+ return HALMAC_RET_C2H_NOT_HANDLED;
+ }
+
+ for (i = 0; i < content_len; i++) {
+ if (*(buf + C2H_DBG_HDR_LEN + i) == '\n') {
+ if ((*(buf + C2H_DBG_HDR_LEN + i + 1) == '\0') ||
+ (*(buf + C2H_DBG_HDR_LEN + i + 1) == 0xff)) {
+ next_msg = C2H_DBG_HDR_LEN + i + 1;
+ goto _ENDFOUND;
+ }
+ }
+ }
+
+_ENDFOUND:
+ msg_len = next_msg - C2H_DBG_HDR_LEN;
+
+ c2h_buf = (char *)PLTFM_MALLOC(msg_len);
+ if (!c2h_buf)
+ return HALMAC_RET_MALLOC_FAIL;
+
+ PLTFM_MEMCPY(c2h_buf, buf + C2H_DBG_HDR_LEN, msg_len);
+
+ seq_num = (u8)(*(c2h_buf));
+ *(c2h_buf + msg_len - 1) = '\0';
+ PLTFM_MSG_ALWAYS("[RTKFW, SEQ=%d]: %s\n",
+ seq_num, (char *)(c2h_buf + 1));
+ PLTFM_FREE(c2h_buf, msg_len);
+
+ while (*(buf + next_msg) != '\0') {
+ cur_msg = next_msg;
+
+ msg_len = (u8)(*(buf + cur_msg + 3)) - 1;
+ next_msg += C2H_DBG_HDR_LEN + msg_len;
+
+ c2h_buf = (char *)PLTFM_MALLOC(msg_len);
+ if (!c2h_buf)
+ return HALMAC_RET_MALLOC_FAIL;
+
+ PLTFM_MEMCPY(c2h_buf, buf + cur_msg + C2H_DBG_HDR_LEN, msg_len);
+ *(c2h_buf + msg_len - 1) = '\0';
+ seq_num = (u8)(*(c2h_buf));
+ PLTFM_MSG_ALWAYS("[RTKFW, SEQ=%d]: %s\n",
+ seq_num, (char *)(c2h_buf + 1));
+ PLTFM_FREE(c2h_buf, msg_len);
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+get_h2c_ack_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+ u8 cmd_id, sub_cmd_id;
+ u8 fw_rc;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ PLTFM_MSG_TRACE("[TRACE]Ack for C2H!!\n");
+
+ fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf);
+ if (HALMAC_H2C_RETURN_SUCCESS != (enum halmac_h2c_return_code)fw_rc)
+ PLTFM_MSG_TRACE("[TRACE]fw rc = %d\n", fw_rc);
+
+ cmd_id = (u8)H2C_ACK_HDR_GET_H2C_CMD_ID(buf);
+
+ if (cmd_id != 0xFF) {
+ PLTFM_MSG_ERR("[ERR]h2c ack cmd id!!\n");
+ return HALMAC_RET_C2H_NOT_HANDLED;
+ }
+
+ sub_cmd_id = (u8)H2C_ACK_HDR_GET_H2C_SUB_CMD_ID(buf);
+
+ switch (sub_cmd_id) {
+ case H2C_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK:
+ status = get_h2c_ack_phy_efuse_88xx(adapter, buf, size);
+ break;
+ case H2C_SUB_CMD_ID_CFG_PARAM_ACK:
+ status = get_h2c_ack_cfg_param_88xx(adapter, buf, size);
+ break;
+ case H2C_SUB_CMD_ID_UPDATE_PKT_ACK:
+ status = get_h2c_ack_update_pkt_88xx(adapter, buf, size);
+ break;
+ case H2C_SUB_CMD_ID_UPDATE_DATAPACK_ACK:
+ status = get_h2c_ack_update_datapkt_88xx(adapter, buf, size);
+ break;
+ case H2C_SUB_CMD_ID_RUN_DATAPACK_ACK:
+ status = get_h2c_ack_run_datapkt_88xx(adapter, buf, size);
+ break;
+ case H2C_SUB_CMD_ID_CH_SWITCH_ACK:
+ status = get_h2c_ack_ch_switch_88xx(adapter, buf, size);
+ break;
+ case H2C_SUB_CMD_ID_IQK_ACK:
+ status = get_h2c_ack_iqk_88xx(adapter, buf, size);
+ break;
+ case H2C_SUB_CMD_ID_PWR_TRK_ACK:
+ status = get_h2c_ack_pwr_trk_88xx(adapter, buf, size);
+ break;
+ case H2C_SUB_CMD_ID_PSD_ACK:
+ break;
+ case H2C_SUB_CMD_ID_FW_SNDING_ACK:
+ status = get_h2c_ack_fw_snding_88xx(adapter, buf, size);
+ break;
+ default:
+ status = HALMAC_RET_C2H_NOT_HANDLED;
+ break;
+ }
+
+ return status;
+}
+
+static enum halmac_ret_status
+get_scan_rpt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+ u8 fw_rc;
+ enum halmac_cmd_process_status proc_status;
+
+ fw_rc = (u8)SCAN_STATUS_RPT_GET_H2C_RETURN_CODE(buf);
+ proc_status = (HALMAC_H2C_RETURN_SUCCESS ==
+ (enum halmac_h2c_return_code)fw_rc) ?
+ HALMAC_CMD_PROCESS_DONE : HALMAC_CMD_PROCESS_ERROR;
+
+ PLTFM_EVENT_SIG(HALMAC_FEATURE_CHANNEL_SWITCH, proc_status, NULL, 0);
+
+ adapter->halmac_state.scan_state.proc_status = proc_status;
+
+ PLTFM_MSG_TRACE("[TRACE]scan : %X\n", proc_status);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+get_h2c_ack_cfg_param_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+ u8 seq_num;
+ u8 fw_rc;
+ u32 offset_accum;
+ u32 value_accum;
+ struct halmac_cfg_param_state *state =
+ &adapter->halmac_state.cfg_param_state;
+ enum halmac_cmd_process_status proc_status =
+ HALMAC_CMD_PROCESS_UNDEFINE;
+
+ seq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf);
+ PLTFM_MSG_TRACE("[TRACE]Seq num : h2c->%d c2h->%d\n",
+ state->seq_num, seq_num);
+ if (seq_num != state->seq_num) {
+ PLTFM_MSG_ERR("[ERR]Seq num mismatch : h2c->%d c2h->%d\n",
+ state->seq_num, seq_num);
+ return HALMAC_RET_SUCCESS;
+ }
+
+ if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) {
+ PLTFM_MSG_ERR("[ERR]not cmd sending\n");
+ return HALMAC_RET_SUCCESS;
+ }
+
+ fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf);
+ state->fw_rc = fw_rc;
+ offset_accum = CFG_PARAM_ACK_GET_OFFSET_ACCUMULATION(buf);
+ value_accum = CFG_PARAM_ACK_GET_VALUE_ACCUMULATION(buf);
+
+ if (offset_accum != adapter->cfg_param_info.offset_accum ||
+ value_accum != adapter->cfg_param_info.value_accum) {
+ PLTFM_MSG_ERR("[ERR][C2H]offset_accu : %x, value_accu : %xn",
+ offset_accum, value_accum);
+ PLTFM_MSG_ERR("[ERR][Ada]offset_accu : %x, value_accu : %x\n",
+ adapter->cfg_param_info.offset_accum,
+ adapter->cfg_param_info.value_accum);
+ proc_status = HALMAC_CMD_PROCESS_ERROR;
+ }
+
+ if ((enum halmac_h2c_return_code)fw_rc == HALMAC_H2C_RETURN_SUCCESS &&
+ proc_status != HALMAC_CMD_PROCESS_ERROR) {
+ proc_status = HALMAC_CMD_PROCESS_DONE;
+ state->proc_status = proc_status;
+ PLTFM_EVENT_SIG(HALMAC_FEATURE_CFG_PARA, proc_status, NULL, 0);
+ } else {
+ proc_status = HALMAC_CMD_PROCESS_ERROR;
+ state->proc_status = proc_status;
+ PLTFM_EVENT_SIG(HALMAC_FEATURE_CFG_PARA, proc_status,
+ &fw_rc, 1);
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+get_h2c_ack_update_pkt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+ u8 seq_num;
+ u8 fw_rc;
+ struct halmac_update_pkt_state *state =
+ &adapter->halmac_state.update_pkt_state;
+ enum halmac_cmd_process_status proc_status;
+
+ seq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf);
+ PLTFM_MSG_TRACE("[TRACE]Seq num : h2c->%d c2h->%d\n",
+ state->seq_num, seq_num);
+ if (seq_num != state->seq_num) {
+ PLTFM_MSG_ERR("[ERR]Seq num mismatch : h2c->%d c2h->%d\n",
+ state->seq_num, seq_num);
+ return HALMAC_RET_SUCCESS;
+ }
+
+ if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) {
+ PLTFM_MSG_ERR("[ERR]not cmd sending\n");
+ return HALMAC_RET_SUCCESS;
+ }
+
+ fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf);
+ state->fw_rc = fw_rc;
+
+ if (HALMAC_H2C_RETURN_SUCCESS == (enum halmac_h2c_return_code)fw_rc) {
+ proc_status = HALMAC_CMD_PROCESS_DONE;
+ state->proc_status = proc_status;
+ PLTFM_EVENT_SIG(HALMAC_FEATURE_UPDATE_PACKET, proc_status,
+ NULL, 0);
+ } else {
+ proc_status = HALMAC_CMD_PROCESS_ERROR;
+ state->proc_status = proc_status;
+ PLTFM_EVENT_SIG(HALMAC_FEATURE_UPDATE_PACKET, proc_status,
+ &state->fw_rc, 1);
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+get_h2c_ack_update_datapkt_88xx(struct halmac_adapter *adapter, u8 *buf,
+ u32 size)
+{
+ return HALMAC_RET_NOT_SUPPORT;
+}
+
+static enum halmac_ret_status
+get_h2c_ack_run_datapkt_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+ return HALMAC_RET_NOT_SUPPORT;
+}
+
+static enum halmac_ret_status
+get_h2c_ack_ch_switch_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+ u8 seq_num;
+ u8 fw_rc;
+ struct halmac_scan_state *state = &adapter->halmac_state.scan_state;
+ enum halmac_cmd_process_status proc_status;
+
+ seq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf);
+ PLTFM_MSG_TRACE("[TRACE]Seq num : h2c->%d c2h->%d\n",
+ state->seq_num, seq_num);
+ if (seq_num != state->seq_num) {
+ PLTFM_MSG_ERR("[ERR]Seq num mismatch : h2c->%d c2h->%d\n",
+ state->seq_num, seq_num);
+ return HALMAC_RET_SUCCESS;
+ }
+
+ if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) {
+ PLTFM_MSG_ERR("[ERR]not cmd sending\n");
+ return HALMAC_RET_SUCCESS;
+ }
+
+ fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf);
+ state->fw_rc = fw_rc;
+
+ if ((enum halmac_h2c_return_code)fw_rc == HALMAC_H2C_RETURN_SUCCESS) {
+ proc_status = HALMAC_CMD_PROCESS_RCVD;
+ state->proc_status = proc_status;
+ PLTFM_EVENT_SIG(HALMAC_FEATURE_CHANNEL_SWITCH, proc_status,
+ NULL, 0);
+ } else {
+ proc_status = HALMAC_CMD_PROCESS_ERROR;
+ state->proc_status = proc_status;
+ PLTFM_EVENT_SIG(HALMAC_FEATURE_CHANNEL_SWITCH, proc_status,
+ &fw_rc, 1);
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * mac_debug_88xx() - dump debug information
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+mac_debug_88xx(struct halmac_adapter *adapter)
+{
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (adapter->intf == HALMAC_INTERFACE_SDIO)
+ dump_reg_sdio_88xx(adapter);
+ else
+ dump_reg_88xx(adapter);
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static void
+dump_reg_sdio_88xx(struct halmac_adapter *adapter)
+{
+ u8 tmp8;
+ u32 i;
+
+ /* Dump CCCR, it needs new platform api */
+
+ /*Dump SDIO Local Register, use CMD52*/
+ for (i = 0x10250000; i < 0x102500ff; i++) {
+ tmp8 = PLTFM_SDIO_CMD52_R(i);
+ PLTFM_MSG_TRACE("[TRACE]dbg-sdio[%x]=%x\n", i, tmp8);
+ }
+
+ /*Dump MAC Register*/
+ for (i = 0x0000; i < 0x17ff; i++) {
+ tmp8 = PLTFM_SDIO_CMD52_R(i);
+ PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp8);
+ }
+
+ tmp8 = PLTFM_SDIO_CMD52_R(REG_SDIO_CRC_ERR_IDX);
+ if (tmp8)
+ PLTFM_MSG_ERR("[ERR]sdio crc=%x\n", tmp8);
+
+ /*Check RX Fifo status*/
+ i = REG_RXFF_PTR_V1;
+ tmp8 = PLTFM_SDIO_CMD52_R(i);
+ PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp8);
+ i = REG_RXFF_WTR_V1;
+ tmp8 = PLTFM_SDIO_CMD52_R(i);
+ PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp8);
+ i = REG_RXFF_PTR_V1;
+ tmp8 = PLTFM_SDIO_CMD52_R(i);
+ PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp8);
+ i = REG_RXFF_WTR_V1;
+ tmp8 = PLTFM_SDIO_CMD52_R(i);
+ PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp8);
+}
+
+static void
+dump_reg_88xx(struct halmac_adapter *adapter)
+{
+ u32 tmp32;
+ u32 i;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ /*Dump MAC Register*/
+ for (i = 0x0000; i < 0x17fc; i += 4) {
+ tmp32 = HALMAC_REG_R32(i);
+ PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp32);
+ }
+
+ /*Check RX Fifo status*/
+ i = REG_RXFF_PTR_V1;
+ tmp32 = HALMAC_REG_R32(i);
+ PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp32);
+ i = REG_RXFF_WTR_V1;
+ tmp32 = HALMAC_REG_R32(i);
+ PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp32);
+ i = REG_RXFF_PTR_V1;
+ tmp32 = HALMAC_REG_R32(i);
+ PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp32);
+ i = REG_RXFF_WTR_V1;
+ tmp32 = HALMAC_REG_R32(i);
+ PLTFM_MSG_TRACE("[TRACE]dbg-mac[%x]=%x\n", i, tmp32);
+}
+
+/**
+ * cfg_parameter_88xx() - config parameter by FW
+ * @adapter : the adapter of halmac
+ * @info : cmd id, content
+ * @full_fifo : parameter information
+ *
+ * If msk_en = _TRUE, the format of array is {reg_info, mask, value}.
+ * If msk_en =_FAUSE, the format of array is {reg_info, value}
+ * The format of reg_info is
+ * reg_info[31]=rf_reg, 0: MAC_BB reg, 1: RF reg
+ * reg_info[27:24]=rf_path, 0: path_A, 1: path_B
+ * if rf_reg=0(MAC_BB reg), rf_path is meaningless.
+ * ref_info[15:0]=offset
+ *
+ * Example: msk_en = _FALSE
+ * {0x8100000a, 0x00001122}
+ * =>Set RF register, path_B, offset 0xA to 0x00001122
+ * {0x00000824, 0x11224433}
+ * =>Set MAC_BB register, offset 0x800 to 0x11224433
+ *
+ * Note : full fifo mode only for init flow
+ *
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_parameter_88xx(struct halmac_adapter *adapter,
+ struct halmac_phy_parameter_info *info, u8 full_fifo)
+{
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+ enum halmac_cmd_process_status *proc_status;
+ enum halmac_cmd_construct_state cmd_state;
+
+ proc_status = &adapter->halmac_state.cfg_param_state.proc_status;
+
+ if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
+ return HALMAC_RET_NO_DLFW;
+
+ if (adapter->fw_ver.h2c_version < 4)
+ return HALMAC_RET_FW_NO_SUPPORT;
+
+ if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+ PLTFM_MSG_TRACE("[TRACE]Wait event(para)\n");
+ return HALMAC_RET_BUSY_STATE;
+ }
+
+ cmd_state = cfg_param_cmd_cnstr_state_88xx(adapter);
+ if (cmd_state != HALMAC_CMD_CNSTR_IDLE &&
+ cmd_state != HALMAC_CMD_CNSTR_CNSTR) {
+ PLTFM_MSG_TRACE("[TRACE]Not idle(para)\n");
+ return HALMAC_RET_BUSY_STATE;
+ }
+
+ *proc_status = HALMAC_CMD_PROCESS_IDLE;
+
+ status = proc_cfg_param_88xx(adapter, info, full_fifo);
+
+ if (status != HALMAC_RET_SUCCESS && status != HALMAC_RET_PARA_SENDING) {
+ PLTFM_MSG_ERR("[ERR]send param h2c\n");
+ return status;
+ }
+
+ return status;
+}
+
+static enum halmac_cmd_construct_state
+cfg_param_cmd_cnstr_state_88xx(struct halmac_adapter *adapter)
+{
+ return adapter->halmac_state.cfg_param_state.cmd_cnstr_state;
+}
+
+static enum halmac_ret_status
+proc_cfg_param_88xx(struct halmac_adapter *adapter,
+ struct halmac_phy_parameter_info *param, u8 full_fifo)
+{
+ u8 end_cmd = _FALSE;
+ u32 rsvd_size;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+ struct halmac_cfg_param_info *info = &adapter->cfg_param_info;
+ enum halmac_cmd_process_status *proc_status;
+
+ proc_status = &adapter->halmac_state.cfg_param_state.proc_status;
+
+ status = malloc_cfg_param_buf_88xx(adapter, full_fifo);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+
+ if (cnv_cfg_param_state_88xx(adapter, HALMAC_CMD_CNSTR_CNSTR) !=
+ HALMAC_RET_SUCCESS)
+ return HALMAC_RET_ERROR_STATE;
+
+ add_param_buf_88xx(adapter, param, info->buf_wptr, &end_cmd);
+ if (param->cmd_id != HALMAC_PARAMETER_CMD_END) {
+ info->num++;
+ info->buf_wptr += CFG_PARAM_H2C_INFO_SIZE;
+ info->avl_buf_size -= CFG_PARAM_H2C_INFO_SIZE;
+ }
+
+ rsvd_size = info->avl_buf_size - adapter->hw_cfg_info.txdesc_size;
+ if (rsvd_size > CFG_PARAM_H2C_INFO_SIZE && end_cmd == _FALSE)
+ return HALMAC_RET_SUCCESS;
+
+ if (info->num == 0) {
+ PLTFM_FREE(info->buf, info->buf_size);
+ info->buf = NULL;
+ info->buf_wptr = NULL;
+ PLTFM_MSG_TRACE("[TRACE]param num = 0!!\n");
+
+ *proc_status = HALMAC_CMD_PROCESS_DONE;
+ PLTFM_EVENT_SIG(HALMAC_FEATURE_CFG_PARA, *proc_status, NULL, 0);
+
+ reset_ofld_feature_88xx(adapter, HALMAC_FEATURE_CFG_PARA);
+
+ return HALMAC_RET_SUCCESS;
+ }
+
+ status = send_cfg_param_h2c_88xx(adapter);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+
+ if (end_cmd == _FALSE) {
+ PLTFM_MSG_TRACE("[TRACE]send h2c-buf full\n");
+ return HALMAC_RET_PARA_SENDING;
+ }
+
+ return status;
+}
+
+static enum halmac_ret_status
+send_cfg_param_h2c_88xx(struct halmac_adapter *adapter)
+{
+ u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };
+ u16 pg_addr;
+ u16 seq_num = 0;
+ u32 info_size;
+ struct halmac_h2c_header_info hdr_info;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+ struct halmac_cfg_param_info *info = &adapter->cfg_param_info;
+ enum halmac_cmd_process_status *proc_status;
+
+ proc_status = &adapter->halmac_state.cfg_param_state.proc_status;
+
+ if (cnv_cfg_param_state_88xx(adapter, HALMAC_CMD_CNSTR_H2C_SENT) !=
+ HALMAC_RET_SUCCESS)
+ return HALMAC_RET_ERROR_STATE;
+
+ *proc_status = HALMAC_CMD_PROCESS_SENDING;
+
+ if (info->full_fifo_mode == _TRUE)
+ pg_addr = 0;
+ else
+ pg_addr = adapter->txff_alloc.rsvd_h2c_info_addr;
+
+ info_size = info->num * CFG_PARAM_H2C_INFO_SIZE;
+
+ status = dl_rsvd_page_88xx(adapter, pg_addr, info->buf, info_size);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]dl rsvd pg!!\n");
+ goto CFG_PARAM_H2C_FAIL;
+ }
+
+ gen_cfg_param_h2c_88xx(adapter, h2c_buf);
+
+ hdr_info.sub_cmd_id = SUB_CMD_ID_CFG_PARAM;
+ hdr_info.content_size = 4;
+ hdr_info.ack = _TRUE;
+ set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+
+ adapter->halmac_state.cfg_param_state.seq_num = seq_num;
+
+ status = send_h2c_pkt_88xx(adapter, h2c_buf);
+
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]send h2c!!\n");
+ reset_ofld_feature_88xx(adapter, HALMAC_FEATURE_CFG_PARA);
+ }
+
+CFG_PARAM_H2C_FAIL:
+ PLTFM_FREE(info->buf, info->buf_size);
+ info->buf = NULL;
+ info->buf_wptr = NULL;
+
+ if (cnv_cfg_param_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=
+ HALMAC_RET_SUCCESS)
+ return HALMAC_RET_ERROR_STATE;
+
+ return status;
+}
+
+static enum halmac_ret_status
+cnv_cfg_param_state_88xx(struct halmac_adapter *adapter,
+ enum halmac_cmd_construct_state dest_state)
+{
+ enum halmac_cmd_construct_state *state;
+
+ state = &adapter->halmac_state.cfg_param_state.cmd_cnstr_state;
+
+ if ((*state != HALMAC_CMD_CNSTR_IDLE) &&
+ (*state != HALMAC_CMD_CNSTR_CNSTR) &&
+ (*state != HALMAC_CMD_CNSTR_H2C_SENT))
+ return HALMAC_RET_ERROR_STATE;
+
+ if (dest_state == HALMAC_CMD_CNSTR_IDLE) {
+ if (*state == HALMAC_CMD_CNSTR_CNSTR)
+ return HALMAC_RET_ERROR_STATE;
+ } else if (dest_state == HALMAC_CMD_CNSTR_CNSTR) {
+ if (*state == HALMAC_CMD_CNSTR_H2C_SENT)
+ return HALMAC_RET_ERROR_STATE;
+ } else if (dest_state == HALMAC_CMD_CNSTR_H2C_SENT) {
+ if ((*state == HALMAC_CMD_CNSTR_IDLE) ||
+ (*state == HALMAC_CMD_CNSTR_H2C_SENT))
+ return HALMAC_RET_ERROR_STATE;
+ }
+
+ *state = dest_state;
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+add_param_buf_88xx(struct halmac_adapter *adapter,
+ struct halmac_phy_parameter_info *param, u8 *buf,
+ u8 *end_cmd)
+{
+ struct halmac_cfg_param_info *info = &adapter->cfg_param_info;
+ union halmac_parameter_content *content = ¶m->content;
+
+ *end_cmd = _FALSE;
+
+ PARAM_INFO_SET_LEN(buf, CFG_PARAM_H2C_INFO_SIZE);
+ PARAM_INFO_SET_IO_CMD(buf, param->cmd_id);
+
+ switch (param->cmd_id) {
+ case HALMAC_PARAMETER_CMD_BB_W8:
+ case HALMAC_PARAMETER_CMD_BB_W16:
+ case HALMAC_PARAMETER_CMD_BB_W32:
+ case HALMAC_PARAMETER_CMD_MAC_W8:
+ case HALMAC_PARAMETER_CMD_MAC_W16:
+ case HALMAC_PARAMETER_CMD_MAC_W32:
+ PARAM_INFO_SET_IO_ADDR(buf, content->MAC_REG_W.offset);
+ PARAM_INFO_SET_DATA(buf, content->MAC_REG_W.value);
+ PARAM_INFO_SET_MASK(buf, content->MAC_REG_W.msk);
+ PARAM_INFO_SET_MSK_EN(buf, content->MAC_REG_W.msk_en);
+ info->value_accum += content->MAC_REG_W.value;
+ info->offset_accum += content->MAC_REG_W.offset;
+ break;
+ case HALMAC_PARAMETER_CMD_RF_W:
+ /*In rf register, the address is only 1 byte*/
+ PARAM_INFO_SET_RF_ADDR(buf, content->RF_REG_W.offset);
+ PARAM_INFO_SET_RF_PATH(buf, content->RF_REG_W.rf_path);
+ PARAM_INFO_SET_DATA(buf, content->RF_REG_W.value);
+ PARAM_INFO_SET_MASK(buf, content->RF_REG_W.msk);
+ PARAM_INFO_SET_MSK_EN(buf, content->RF_REG_W.msk_en);
+ info->value_accum += content->RF_REG_W.value;
+ info->offset_accum += (content->RF_REG_W.offset +
+ (content->RF_REG_W.rf_path << 8));
+ break;
+ case HALMAC_PARAMETER_CMD_DELAY_US:
+ case HALMAC_PARAMETER_CMD_DELAY_MS:
+ PARAM_INFO_SET_DELAY_VAL(buf, content->DELAY_TIME.delay_time);
+ break;
+ case HALMAC_PARAMETER_CMD_END:
+ *end_cmd = _TRUE;
+ break;
+ default:
+ PLTFM_MSG_ERR("[ERR]cmd id!!\n");
+ break;
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+gen_cfg_param_h2c_88xx(struct halmac_adapter *adapter, u8 *buff)
+{
+ struct halmac_cfg_param_info *info = &adapter->cfg_param_info;
+ u16 h2c_info_addr = adapter->txff_alloc.rsvd_h2c_info_addr;
+ u16 rsvd_pg_addr = adapter->txff_alloc.rsvd_boundary;
+
+ CFG_PARAM_SET_NUM(buff, info->num);
+
+ if (info->full_fifo_mode == _TRUE) {
+ CFG_PARAM_SET_INIT_CASE(buff, 0x1);
+ CFG_PARAM_SET_LOC(buff, 0);
+ } else {
+ CFG_PARAM_SET_INIT_CASE(buff, 0x0);
+ CFG_PARAM_SET_LOC(buff, h2c_info_addr - rsvd_pg_addr);
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+malloc_cfg_param_buf_88xx(struct halmac_adapter *adapter, u8 full_fifo)
+{
+ struct halmac_cfg_param_info *info = &adapter->cfg_param_info;
+ struct halmac_pltfm_cfg_info *pltfm_info = &adapter->pltfm_info;
+
+ if (info->buf)
+ return HALMAC_RET_SUCCESS;
+
+ if (full_fifo == _TRUE)
+ info->buf_size = pltfm_info->malloc_size;
+ else
+ info->buf_size = CFG_PARAM_RSVDPG_SIZE;
+
+ if (info->buf_size > pltfm_info->rsvd_pg_size)
+ info->buf_size = pltfm_info->rsvd_pg_size;
+
+ info->buf = smart_malloc_88xx(adapter, info->buf_size, &info->buf_size);
+ if (info->buf) {
+ PLTFM_MEMSET(info->buf, 0x00, info->buf_size);
+ info->full_fifo_mode = full_fifo;
+ info->buf_wptr = info->buf;
+ info->num = 0;
+ info->avl_buf_size = info->buf_size;
+ info->value_accum = 0;
+ info->offset_accum = 0;
+ } else {
+ return HALMAC_RET_MALLOC_FAIL;
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * update_packet_88xx() - send specific packet to FW
+ * @adapter : the adapter of halmac
+ * @pkt_id : packet id, to know the purpose of this packet
+ * @pkt : packet
+ * @size : packet size
+ *
+ * Note : TX_DESC is not included in the pkt
+ *
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+update_packet_88xx(struct halmac_adapter *adapter, enum halmac_packet_id pkt_id,
+ u8 *pkt, u32 size)
+{
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+ enum halmac_cmd_process_status *proc_status =
+ &adapter->halmac_state.update_pkt_state.proc_status;
+
+ if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
+ return HALMAC_RET_NO_DLFW;
+
+ if (adapter->fw_ver.h2c_version < 4)
+ return HALMAC_RET_FW_NO_SUPPORT;
+
+ if (size > UPDATE_PKT_RSVDPG_SIZE)
+ return HALMAC_RET_RSVD_PG_OVERFLOW_FAIL;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+ PLTFM_MSG_TRACE("[TRACE]Wait event(upd)\n");
+ return HALMAC_RET_BUSY_STATE;
+ }
+
+ *proc_status = HALMAC_CMD_PROCESS_SENDING;
+
+ status = send_h2c_update_packet_88xx(adapter, pkt_id, pkt, size);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]send h2c!!\n");
+ PLTFM_MSG_ERR("[ERR]pkt id : %X!!\n", pkt_id);
+ return status;
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+send_h2c_update_packet_88xx(struct halmac_adapter *adapter,
+ enum halmac_packet_id pkt_id, u8 *pkt, u32 size)
+{
+ u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };
+ u16 seq_num = 0;
+ u16 pg_addr = adapter->txff_alloc.rsvd_h2c_info_addr;
+ u16 pg_offset;
+ struct halmac_h2c_header_info hdr_info;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ status = dl_rsvd_page_88xx(adapter, pg_addr, pkt, size);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]dl rsvd pg!!\n");
+ return status;
+ }
+
+ pg_offset = pg_addr - adapter->txff_alloc.rsvd_boundary;
+ UPDATE_PKT_SET_SIZE(h2c_buf, size + adapter->hw_cfg_info.txdesc_size);
+ UPDATE_PKT_SET_ID(h2c_buf, pkt_id);
+ UPDATE_PKT_SET_LOC(h2c_buf, pg_offset);
+
+ hdr_info.sub_cmd_id = SUB_CMD_ID_UPDATE_PKT;
+ hdr_info.content_size = 8;
+ hdr_info.ack = _TRUE;
+ set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+ adapter->halmac_state.update_pkt_state.seq_num = seq_num;
+
+ status = send_h2c_pkt_88xx(adapter, h2c_buf);
+
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]send h2c!!\n");
+ reset_ofld_feature_88xx(adapter, HALMAC_FEATURE_UPDATE_PACKET);
+ return status;
+ }
+
+ return status;
+}
+
+enum halmac_ret_status
+bcn_ie_filter_88xx(struct halmac_adapter *adapter,
+ struct halmac_bcn_ie_info *info)
+{
+ return HALMAC_RET_NOT_SUPPORT;
+}
+
+enum halmac_ret_status
+update_datapack_88xx(struct halmac_adapter *adapter,
+ enum halmac_data_type data_type,
+ struct halmac_phy_parameter_info *info)
+{
+ return HALMAC_RET_NOT_SUPPORT;
+}
+
+enum halmac_ret_status
+run_datapack_88xx(struct halmac_adapter *adapter,
+ enum halmac_data_type data_type)
+{
+ return HALMAC_RET_NOT_SUPPORT;
+}
+
+enum halmac_ret_status
+send_bt_coex_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size, u8 ack)
+{
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
+ return HALMAC_RET_NO_DLFW;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ status = send_bt_coex_cmd_88xx(adapter, buf, size, ack);
+
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]bt coex cmd!!\n");
+ return status;
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+send_bt_coex_cmd_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
+ u8 ack)
+{
+ u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };
+ u16 seq_num = 0;
+ struct halmac_h2c_header_info hdr_info;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ PLTFM_MEMCPY(h2c_buf + 8, buf, size);
+
+ hdr_info.sub_cmd_id = SUB_CMD_ID_BT_COEX;
+ hdr_info.content_size = (u16)size;
+ hdr_info.ack = ack;
+ set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+
+ status = send_h2c_pkt_88xx(adapter, h2c_buf);
+
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]send h2c!!\n");
+ return status;
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * dump_fifo_88xx() - dump fifo data
+ * @adapter : the adapter of halmac
+ * @sel : FIFO selection
+ * @start_addr : start address of selected FIFO
+ * @size : dump size of selected FIFO
+ * @data : FIFO data
+ *
+ * Note : before dump fifo, user need to call halmac_get_fifo_size to
+ * get fifo size. Then input this size to halmac_dump_fifo.
+ *
+ * Author : Ivan Lin/KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+dump_fifo_88xx(struct halmac_adapter *adapter, enum hal_fifo_sel sel,
+ u32 start_addr, u32 size, u8 *data)
+{
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+ u8 tmp8;
+ u8 enable;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (sel == HAL_FIFO_SEL_TX &&
+ (start_addr + size) > adapter->hw_cfg_info.tx_fifo_size) {
+ PLTFM_MSG_ERR("[ERR]size overflow!!\n");
+ return HALMAC_RET_DUMP_FIFOSIZE_INCORRECT;
+ }
+
+ if (sel == HAL_FIFO_SEL_RX &&
+ (start_addr + size) > adapter->hw_cfg_info.rx_fifo_size) {
+ PLTFM_MSG_ERR("[ERR]size overflow!!\n");
+ return HALMAC_RET_DUMP_FIFOSIZE_INCORRECT;
+ }
+
+ if ((size & (4 - 1)) != 0) {
+ PLTFM_MSG_ERR("[ERR]not 4byte alignment!!\n");
+ return HALMAC_RET_DUMP_FIFOSIZE_INCORRECT;
+ }
+
+ if (!data)
+ return HALMAC_RET_NULL_POINTER;
+
+ tmp8 = HALMAC_REG_R8(REG_RCR + 2);
+ enable = _FALSE;
+ status = api->halmac_set_hw_value(adapter, HALMAC_HW_RX_CLK_GATE,
+ &enable);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+ status = read_buf_88xx(adapter, start_addr, size, sel, data);
+
+ HALMAC_REG_W8(REG_RCR + 2, tmp8);
+
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]read buf!!\n");
+ return status;
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+read_buf_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
+ enum hal_fifo_sel sel, u8 *data)
+{
+ u32 start_pg;
+ u32 value32;
+ u32 i;
+ u32 residue;
+ u32 cnt = 0;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ if (sel == HAL_FIFO_SEL_RSVD_PAGE)
+ offset += (adapter->txff_alloc.rsvd_boundary <<
+ TX_PAGE_SIZE_SHIFT_88XX);
+
+ start_pg = offset >> 12;
+ residue = offset & (4096 - 1);
+
+ if (sel == HAL_FIFO_SEL_TX || sel == HAL_FIFO_SEL_RSVD_PAGE)
+ start_pg += 0x780;
+ else if (sel == HAL_FIFO_SEL_RX)
+ start_pg += 0x700;
+ else if (sel == HAL_FIFO_SEL_REPORT)
+ start_pg += 0x660;
+ else if (sel == HAL_FIFO_SEL_LLT)
+ start_pg += 0x650;
+ else if (sel == HAL_FIFO_SEL_RXBUF_FW)
+ start_pg += 0x680;
+ else
+ return HALMAC_RET_NOT_SUPPORT;
+
+ value32 = HALMAC_REG_R16(REG_PKTBUF_DBG_CTRL) & 0xF000;
+
+ do {
+ HALMAC_REG_W16(REG_PKTBUF_DBG_CTRL, (u16)(start_pg | value32));
+
+ for (i = 0x8000 + residue; i <= 0x8FFF; i += 4) {
+ *(u32 *)(data + cnt) = HALMAC_REG_R32(i);
+ *(u32 *)(data + cnt) =
+ rtk_le32_to_cpu(*(u32 *)(data + cnt));
+ cnt += 4;
+ if (size == cnt)
+ goto HALMAC_BUF_READ_OK;
+ }
+
+ residue = 0;
+ start_pg++;
+ } while (1);
+
+HALMAC_BUF_READ_OK:
+ HALMAC_REG_W16(REG_PKTBUF_DBG_CTRL, (u16)value32);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * get_fifo_size_88xx() - get fifo size
+ * @adapter : the adapter of halmac
+ * @sel : FIFO selection
+ * Author : Ivan Lin/KaiYuan Chang
+ * Return : u32
+ * More details of status code can be found in prototype document
+ */
+u32
+get_fifo_size_88xx(struct halmac_adapter *adapter, enum hal_fifo_sel sel)
+{
+ u32 size = 0;
+
+ if (sel == HAL_FIFO_SEL_TX)
+ size = adapter->hw_cfg_info.tx_fifo_size;
+ else if (sel == HAL_FIFO_SEL_RX)
+ size = adapter->hw_cfg_info.rx_fifo_size;
+ else if (sel == HAL_FIFO_SEL_RSVD_PAGE)
+ size = adapter->hw_cfg_info.tx_fifo_size -
+ (adapter->txff_alloc.rsvd_boundary <<
+ TX_PAGE_SIZE_SHIFT_88XX);
+ else if (sel == HAL_FIFO_SEL_REPORT)
+ size = 65536;
+ else if (sel == HAL_FIFO_SEL_LLT)
+ size = 65536;
+ else if (sel == HAL_FIFO_SEL_RXBUF_FW)
+ size = RX_BUF_FW_88XX;
+
+ return size;
+}
+
+enum halmac_ret_status
+set_h2c_header_88xx(struct halmac_adapter *adapter, u8 *hdr, u16 *seq, u8 ack)
+{
+ PLTFM_MSG_TRACE("[TRACE]%s!!\n", __func__);
+
+ H2C_CMD_HEADER_SET_CATEGORY(hdr, 0x00);
+ H2C_CMD_HEADER_SET_TOTAL_LEN(hdr, 16);
+
+ PLTFM_MUTEX_LOCK(&adapter->h2c_seq_mutex);
+ H2C_CMD_HEADER_SET_SEQ_NUM(hdr, adapter->h2c_info.seq_num);
+ *seq = adapter->h2c_info.seq_num;
+ (adapter->h2c_info.seq_num)++;
+ PLTFM_MUTEX_UNLOCK(&adapter->h2c_seq_mutex);
+
+ if (ack == _TRUE)
+ H2C_CMD_HEADER_SET_ACK(hdr, _TRUE);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * add_ch_info_88xx() -add channel information
+ * @adapter : the adapter of halmac
+ * @info : channel information
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+add_ch_info_88xx(struct halmac_adapter *adapter, struct halmac_ch_info *info)
+{
+ struct halmac_ch_sw_info *ch_sw_info = &adapter->ch_sw_info;
+ enum halmac_cmd_construct_state state;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (adapter->halmac_state.dlfw_state != HALMAC_GEN_INFO_SENT) {
+ PLTFM_MSG_ERR("[ERR]gen info\n");
+ return HALMAC_RET_GEN_INFO_NOT_SENT;
+ }
+
+ state = scan_cmd_cnstr_state_88xx(adapter);
+ if (state != HALMAC_CMD_CNSTR_BUF_CLR &&
+ state != HALMAC_CMD_CNSTR_CNSTR) {
+ PLTFM_MSG_WARN("[WARN]cmd state (scan)\n");
+ return HALMAC_RET_ERROR_STATE;
+ }
+
+ if (!ch_sw_info->buf) {
+ ch_sw_info->buf = (u8 *)PLTFM_MALLOC(SCAN_INFO_RSVDPG_SIZE);
+ if (!ch_sw_info->buf)
+ return HALMAC_RET_NULL_POINTER;
+ ch_sw_info->buf_wptr = ch_sw_info->buf;
+ ch_sw_info->buf_size = SCAN_INFO_RSVDPG_SIZE;
+ ch_sw_info->avl_buf_size = SCAN_INFO_RSVDPG_SIZE;
+ ch_sw_info->total_size = 0;
+ ch_sw_info->extra_info_en = 0;
+ ch_sw_info->ch_num = 0;
+ }
+
+ if (ch_sw_info->extra_info_en == 1) {
+ PLTFM_MSG_ERR("[ERR]extra info = 1!!\n");
+ return HALMAC_RET_CH_SW_SEQ_WRONG;
+ }
+
+ if (ch_sw_info->avl_buf_size < 4) {
+ PLTFM_MSG_ERR("[ERR]buf full!!\n");
+ return HALMAC_RET_CH_SW_NO_BUF;
+ }
+
+ if (cnv_scan_state_88xx(adapter, HALMAC_CMD_CNSTR_CNSTR) !=
+ HALMAC_RET_SUCCESS)
+ return HALMAC_RET_ERROR_STATE;
+
+ CH_INFO_SET_CH(ch_sw_info->buf_wptr, info->channel);
+ CH_INFO_SET_PRI_CH_IDX(ch_sw_info->buf_wptr, info->pri_ch_idx);
+ CH_INFO_SET_BW(ch_sw_info->buf_wptr, info->bw);
+ CH_INFO_SET_TIMEOUT(ch_sw_info->buf_wptr, info->timeout);
+ CH_INFO_SET_ACTION_ID(ch_sw_info->buf_wptr, info->action_id);
+ CH_INFO_SET_EXTRA_INFO(ch_sw_info->buf_wptr, info->extra_info);
+
+ ch_sw_info->avl_buf_size = ch_sw_info->avl_buf_size - 4;
+ ch_sw_info->total_size = ch_sw_info->total_size + 4;
+ ch_sw_info->ch_num++;
+ ch_sw_info->extra_info_en = info->extra_info;
+ ch_sw_info->buf_wptr = ch_sw_info->buf_wptr + 4;
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_cmd_construct_state
+scan_cmd_cnstr_state_88xx(struct halmac_adapter *adapter)
+{
+ return adapter->halmac_state.scan_state.cmd_cnstr_state;
+}
+
+static enum halmac_ret_status
+cnv_scan_state_88xx(struct halmac_adapter *adapter,
+ enum halmac_cmd_construct_state dest_state)
+{
+ enum halmac_cmd_construct_state *state;
+
+ state = &adapter->halmac_state.scan_state.cmd_cnstr_state;
+
+ if (dest_state == HALMAC_CMD_CNSTR_IDLE) {
+ if ((*state == HALMAC_CMD_CNSTR_BUF_CLR) ||
+ (*state == HALMAC_CMD_CNSTR_CNSTR))
+ return HALMAC_RET_ERROR_STATE;
+ } else if (dest_state == HALMAC_CMD_CNSTR_BUF_CLR) {
+ if (*state == HALMAC_CMD_CNSTR_H2C_SENT)
+ return HALMAC_RET_ERROR_STATE;
+ } else if (dest_state == HALMAC_CMD_CNSTR_CNSTR) {
+ if ((*state == HALMAC_CMD_CNSTR_IDLE) ||
+ (*state == HALMAC_CMD_CNSTR_H2C_SENT))
+ return HALMAC_RET_ERROR_STATE;
+ } else if (dest_state == HALMAC_CMD_CNSTR_H2C_SENT) {
+ if ((*state != HALMAC_CMD_CNSTR_CNSTR) &&
+ (*state != HALMAC_CMD_CNSTR_BUF_CLR))
+ return HALMAC_RET_ERROR_STATE;
+ }
+
+ *state = dest_state;
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * add_extra_ch_info_88xx() -add extra channel information
+ * @adapter : the adapter of halmac
+ * @info : extra channel information
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+add_extra_ch_info_88xx(struct halmac_adapter *adapter,
+ struct halmac_ch_extra_info *info)
+{
+ struct halmac_ch_sw_info *ch_sw_info = &adapter->ch_sw_info;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (!ch_sw_info->buf) {
+ PLTFM_MSG_ERR("[ERR]buf = null!!\n");
+ return HALMAC_RET_CH_SW_SEQ_WRONG;
+ }
+
+ if (ch_sw_info->extra_info_en == 0) {
+ PLTFM_MSG_ERR("[ERR]extra info = 0!!\n");
+ return HALMAC_RET_CH_SW_SEQ_WRONG;
+ }
+
+ if (ch_sw_info->avl_buf_size < (u32)(info->extra_info_size + 2)) {
+ PLTFM_MSG_ERR("[ERR]no available buffer!!\n");
+ return HALMAC_RET_CH_SW_NO_BUF;
+ }
+
+ if (scan_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_CNSTR) {
+ PLTFM_MSG_WARN("[WARN]cmd state (ex scan)\n");
+ return HALMAC_RET_ERROR_STATE;
+ }
+
+ if (cnv_scan_state_88xx(adapter, HALMAC_CMD_CNSTR_CNSTR) !=
+ HALMAC_RET_SUCCESS)
+ return HALMAC_RET_ERROR_STATE;
+
+ CH_EXTRA_INFO_SET_ID(ch_sw_info->buf_wptr, info->extra_action_id);
+ CH_EXTRA_INFO_SET_INFO(ch_sw_info->buf_wptr, info->extra_info);
+ CH_EXTRA_INFO_SET_SIZE(ch_sw_info->buf_wptr, info->extra_info_size);
+ PLTFM_MEMCPY(ch_sw_info->buf_wptr + 2, info->extra_info_data,
+ info->extra_info_size);
+
+ ch_sw_info->avl_buf_size -= (2 + info->extra_info_size);
+ ch_sw_info->total_size += (2 + info->extra_info_size);
+ ch_sw_info->extra_info_en = info->extra_info;
+ ch_sw_info->buf_wptr += (2 + info->extra_info_size);
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * ctrl_ch_switch_88xx() -send channel switch cmd
+ * @adapter : the adapter of halmac
+ * @opt : channel switch config
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+ctrl_ch_switch_88xx(struct halmac_adapter *adapter,
+ struct halmac_ch_switch_option *opt)
+{
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+ enum halmac_cmd_construct_state state;
+ enum halmac_cmd_process_status *proc_status;
+
+ proc_status = &adapter->halmac_state.scan_state.proc_status;
+
+ if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
+ return HALMAC_RET_NO_DLFW;
+
+ if (adapter->fw_ver.h2c_version < 4)
+ return HALMAC_RET_FW_NO_SUPPORT;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (opt->switch_en == _FALSE)
+ *proc_status = HALMAC_CMD_PROCESS_IDLE;
+
+ if ((*proc_status == HALMAC_CMD_PROCESS_SENDING) ||
+ (*proc_status == HALMAC_CMD_PROCESS_RCVD)) {
+ PLTFM_MSG_TRACE("[TRACE]Wait event(scan)\n");
+ return HALMAC_RET_BUSY_STATE;
+ }
+
+ state = scan_cmd_cnstr_state_88xx(adapter);
+ if (opt->switch_en == _TRUE) {
+ if (state != HALMAC_CMD_CNSTR_CNSTR) {
+ PLTFM_MSG_ERR("[ERR]state(en = 1)\n");
+ return HALMAC_RET_ERROR_STATE;
+ }
+ } else {
+ if (state != HALMAC_CMD_CNSTR_BUF_CLR) {
+ PLTFM_MSG_ERR("[ERR]state(en = 0)\n");
+ return HALMAC_RET_ERROR_STATE;
+ }
+ }
+
+ status = proc_ctrl_ch_switch_88xx(adapter, opt);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]ctrl ch sw!!\n");
+ return status;
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+proc_ctrl_ch_switch_88xx(struct halmac_adapter *adapter,
+ struct halmac_ch_switch_option *opt)
+{
+ u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };
+ u16 seq_num = 0;
+ u16 pg_addr = adapter->txff_alloc.rsvd_h2c_info_addr;
+ struct halmac_h2c_header_info hdr_info;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+ enum halmac_cmd_process_status *proc_status;
+
+ proc_status = &adapter->halmac_state.scan_state.proc_status;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (cnv_scan_state_88xx(adapter, HALMAC_CMD_CNSTR_H2C_SENT) !=
+ HALMAC_RET_SUCCESS)
+ return HALMAC_RET_ERROR_STATE;
+
+ *proc_status = HALMAC_CMD_PROCESS_SENDING;
+
+ if (opt->switch_en != 0) {
+ status = dl_rsvd_page_88xx(adapter, pg_addr,
+ adapter->ch_sw_info.buf,
+ adapter->ch_sw_info.total_size);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]dl rsvd pg!!\n");
+ return status;
+ }
+ }
+
+ CH_SWITCH_SET_START(h2c_buf, opt->switch_en);
+ CH_SWITCH_SET_CH_NUM(h2c_buf, adapter->ch_sw_info.ch_num);
+ CH_SWITCH_SET_INFO_LOC(h2c_buf,
+ pg_addr - adapter->txff_alloc.rsvd_boundary);
+ CH_SWITCH_SET_DEST_CH_EN(h2c_buf, opt->dest_ch_en);
+ CH_SWITCH_SET_DEST_CH(h2c_buf, opt->dest_ch);
+ CH_SWITCH_SET_PRI_CH_IDX(h2c_buf, opt->dest_pri_ch_idx);
+ CH_SWITCH_SET_ABSOLUTE_TIME(h2c_buf, opt->absolute_time_en);
+ CH_SWITCH_SET_TSF_LOW(h2c_buf, opt->tsf_low);
+ CH_SWITCH_SET_PERIODIC_OPT(h2c_buf, opt->periodic_option);
+ CH_SWITCH_SET_NORMAL_CYCLE(h2c_buf, opt->normal_cycle);
+ CH_SWITCH_SET_NORMAL_PERIOD(h2c_buf, opt->normal_period);
+ CH_SWITCH_SET_SLOW_PERIOD(h2c_buf, opt->phase_2_period);
+ CH_SWITCH_SET_NORMAL_PERIOD_SEL(h2c_buf, opt->normal_period_sel);
+ CH_SWITCH_SET_SLOW_PERIOD_SEL(h2c_buf, opt->phase_2_period_sel);
+ CH_SWITCH_SET_INFO_SIZE(h2c_buf, adapter->ch_sw_info.total_size);
+
+ hdr_info.sub_cmd_id = SUB_CMD_ID_CH_SWITCH;
+ hdr_info.content_size = 20;
+ hdr_info.ack = _TRUE;
+ set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+ adapter->halmac_state.scan_state.seq_num = seq_num;
+
+ status = send_h2c_pkt_88xx(adapter, h2c_buf);
+
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]send h2c!!\n");
+ reset_ofld_feature_88xx(adapter, HALMAC_FEATURE_CHANNEL_SWITCH);
+ }
+ PLTFM_FREE(adapter->ch_sw_info.buf, adapter->ch_sw_info.buf_size);
+ adapter->ch_sw_info.buf = NULL;
+ adapter->ch_sw_info.buf_wptr = NULL;
+ adapter->ch_sw_info.extra_info_en = 0;
+ adapter->ch_sw_info.buf_size = 0;
+ adapter->ch_sw_info.avl_buf_size = 0;
+ adapter->ch_sw_info.total_size = 0;
+ adapter->ch_sw_info.ch_num = 0;
+
+ if (cnv_scan_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=
+ HALMAC_RET_SUCCESS)
+ return HALMAC_RET_ERROR_STATE;
+
+ return status;
+}
+
+/**
+ * clear_ch_info_88xx() -clear channel information
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+clear_ch_info_88xx(struct halmac_adapter *adapter)
+{
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (scan_cmd_cnstr_state_88xx(adapter) == HALMAC_CMD_CNSTR_H2C_SENT) {
+ PLTFM_MSG_WARN("[WARN]state(clear)\n");
+ return HALMAC_RET_ERROR_STATE;
+ }
+
+ if (cnv_scan_state_88xx(adapter, HALMAC_CMD_CNSTR_BUF_CLR) !=
+ HALMAC_RET_SUCCESS)
+ return HALMAC_RET_ERROR_STATE;
+
+ PLTFM_FREE(adapter->ch_sw_info.buf, adapter->ch_sw_info.buf_size);
+ adapter->ch_sw_info.buf = NULL;
+ adapter->ch_sw_info.buf_wptr = NULL;
+ adapter->ch_sw_info.extra_info_en = 0;
+ adapter->ch_sw_info.buf_size = 0;
+ adapter->ch_sw_info.avl_buf_size = 0;
+ adapter->ch_sw_info.total_size = 0;
+ adapter->ch_sw_info.ch_num = 0;
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * chk_txdesc_88xx() -check if the tx packet format is incorrect
+ * @adapter : the adapter of halmac
+ * @buf : tx Packet buffer, tx desc is included
+ * @size : tx packet size
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+chk_txdesc_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+ u32 mac_clk = 0;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (GET_TX_DESC_BMC(buf) == _TRUE && GET_TX_DESC_AGG_EN(buf) == _TRUE)
+ PLTFM_MSG_ERR("[ERR]txdesc - agg + bmc\n");
+
+ if (size < (GET_TX_DESC_TXPKTSIZE(buf) +
+ adapter->hw_cfg_info.txdesc_size +
+ (GET_TX_DESC_PKT_OFFSET(buf) << 3))) {
+ PLTFM_MSG_ERR("[ERR]txdesc - total size\n");
+ status = HALMAC_RET_TXDESC_SET_FAIL;
+ }
+
+ if (wlhdr_valid_88xx(adapter, buf) != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]wlhdr\n");
+ status = HALMAC_RET_WLHDR_FAIL;
+ }
+
+ if (GET_TX_DESC_AMSDU_PAD_EN(buf) != 0) {
+ PLTFM_MSG_ERR("[ERR]txdesc - amsdu_pad\n");
+ status = HALMAC_RET_TXDESC_SET_FAIL;
+ }
+
+ switch (BIT_GET_MAC_CLK_SEL(HALMAC_REG_R32(REG_AFE_CTRL1))) {
+ case 0x0:
+ mac_clk = 80;
+ break;
+ case 0x1:
+ mac_clk = 40;
+ break;
+ case 0x2:
+ mac_clk = 20;
+ break;
+ case 0x3:
+ mac_clk = 10;
+ break;
+ }
+
+ PLTFM_MSG_ALWAYS("MAC clock : 0x%XM\n", mac_clk);
+ PLTFM_MSG_ALWAYS("mac agg en : 0x%X\n", GET_TX_DESC_AGG_EN(buf));
+ PLTFM_MSG_ALWAYS("mac agg num : 0x%X\n", GET_TX_DESC_MAX_AGG_NUM(buf));
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return status;
+}
+
+static enum halmac_ret_status
+wlhdr_valid_88xx(struct halmac_adapter *adapter, u8 *buf)
+{
+ u32 txdesc_size = adapter->hw_cfg_info.txdesc_size +
+ GET_TX_DESC_PKT_OFFSET(buf);
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+ struct wlhdr_frame_ctrl *wlhdr;
+
+ wlhdr = (struct wlhdr_frame_ctrl *)(buf + txdesc_size);
+
+ if (wlhdr->protocol != WLHDR_PROT_VER) {
+ PLTFM_MSG_ERR("[ERR]prot ver!!\n");
+ return HALMAC_RET_WLHDR_FAIL;
+ }
+
+ switch (wlhdr->type) {
+ case WLHDR_TYPE_MGMT:
+ if (wlhdr_mgmt_valid_88xx(adapter, wlhdr) != _TRUE)
+ status = HALMAC_RET_WLHDR_FAIL;
+ break;
+ case WLHDR_TYPE_CTRL:
+ if (wlhdr_ctrl_valid_88xx(adapter, wlhdr) != _TRUE)
+ status = HALMAC_RET_WLHDR_FAIL;
+ break;
+ case WLHDR_TYPE_DATA:
+ if (wlhdr_data_valid_88xx(adapter, wlhdr) != _TRUE)
+ status = HALMAC_RET_WLHDR_FAIL;
+ break;
+ default:
+ PLTFM_MSG_ERR("[ERR]undefined type!!\n");
+ status = HALMAC_RET_WLHDR_FAIL;
+ break;
+ }
+
+ return status;
+}
+
+static u8
+wlhdr_mgmt_valid_88xx(struct halmac_adapter *adapter,
+ struct wlhdr_frame_ctrl *wlhdr)
+{
+ u8 state;
+
+ switch (wlhdr->sub_type) {
+ case WLHDR_SUB_TYPE_ASSOC_REQ:
+ case WLHDR_SUB_TYPE_ASSOC_RSPNS:
+ case WLHDR_SUB_TYPE_REASSOC_REQ:
+ case WLHDR_SUB_TYPE_REASSOC_RSPNS:
+ case WLHDR_SUB_TYPE_PROBE_REQ:
+ case WLHDR_SUB_TYPE_PROBE_RSPNS:
+ case WLHDR_SUB_TYPE_BCN:
+ case WLHDR_SUB_TYPE_DISASSOC:
+ case WLHDR_SUB_TYPE_AUTH:
+ case WLHDR_SUB_TYPE_DEAUTH:
+ case WLHDR_SUB_TYPE_ACTION:
+ case WLHDR_SUB_TYPE_ACTION_NOACK:
+ state = _TRUE;
+ break;
+ default:
+ PLTFM_MSG_ERR("[ERR]mgmt invalid!!\n");
+ state = _FALSE;
+ break;
+ }
+
+ return state;
+}
+
+static u8
+wlhdr_ctrl_valid_88xx(struct halmac_adapter *adapter,
+ struct wlhdr_frame_ctrl *wlhdr)
+{
+ u8 state;
+
+ switch (wlhdr->sub_type) {
+ case WLHDR_SUB_TYPE_BF_RPT_POLL:
+ case WLHDR_SUB_TYPE_NDPA:
+ state = _TRUE;
+ break;
+ default:
+ PLTFM_MSG_ERR("[ERR]ctrl invalid!!\n");
+ state = _FALSE;
+ break;
+ }
+
+ return state;
+}
+
+static u8
+wlhdr_data_valid_88xx(struct halmac_adapter *adapter,
+ struct wlhdr_frame_ctrl *wlhdr)
+{
+ u8 state;
+
+ switch (wlhdr->sub_type) {
+ case WLHDR_SUB_TYPE_DATA:
+ case WLHDR_SUB_TYPE_NULL:
+ case WLHDR_SUB_TYPE_QOS_DATA:
+ case WLHDR_SUB_TYPE_QOS_NULL:
+ state = _TRUE;
+ break;
+ default:
+ PLTFM_MSG_ERR("[ERR]data invalid!!\n");
+ state = _FALSE;
+ break;
+ }
+
+ return state;
+}
+
+/**
+ * halmac_get_version() - get HALMAC version
+ * @ver : return version of major, prototype and minor information
+ * Author : KaiYuan Chang / Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+get_version_88xx(struct halmac_adapter *adapter, struct halmac_ver *ver)
+{
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ ver->major_ver = (u8)HALMAC_MAJOR_VER;
+ ver->prototype_ver = (u8)HALMAC_PROTOTYPE_VER;
+ ver->minor_ver = (u8)HALMAC_MINOR_VER;
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+p2pps_88xx(struct halmac_adapter *adapter, struct halmac_p2pps *info)
+{
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
+ return HALMAC_RET_NO_DLFW;
+
+ if (adapter->fw_ver.h2c_version < 6)
+ return HALMAC_RET_FW_NO_SUPPORT;
+
+ status = proc_p2pps_88xx(adapter, info);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]p2pps!!\n");
+ return status;
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+proc_p2pps_88xx(struct halmac_adapter *adapter, struct halmac_p2pps *info)
+{
+ u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };
+ u16 seq_num = 0;
+ struct halmac_h2c_header_info hdr_info;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ P2PPS_SET_OFFLOAD_EN(h2c_buf, info->offload_en);
+ P2PPS_SET_ROLE(h2c_buf, info->role);
+ P2PPS_SET_CTWINDOW_EN(h2c_buf, info->ctwindow_en);
+ P2PPS_SET_NOA_EN(h2c_buf, info->noa_en);
+ P2PPS_SET_NOA_SEL(h2c_buf, info->noa_sel);
+ P2PPS_SET_ALLSTASLEEP(h2c_buf, info->all_sta_sleep);
+ P2PPS_SET_DISCOVERY(h2c_buf, info->discovery);
+ P2PPS_SET_DISABLE_CLOSERF(h2c_buf, info->disable_close_rf);
+ P2PPS_SET_P2P_PORT_ID(h2c_buf, info->p2p_port_id);
+ P2PPS_SET_P2P_GROUP(h2c_buf, info->p2p_group);
+ P2PPS_SET_P2P_MACID(h2c_buf, info->p2p_macid);
+
+ P2PPS_SET_CTWINDOW_LENGTH(h2c_buf, info->ctwindow_length);
+
+ P2PPS_SET_NOA_DURATION_PARA(h2c_buf, info->noa_duration_para);
+ P2PPS_SET_NOA_INTERVAL_PARA(h2c_buf, info->noa_interval_para);
+ P2PPS_SET_NOA_START_TIME_PARA(h2c_buf, info->noa_start_time_para);
+ P2PPS_SET_NOA_COUNT_PARA(h2c_buf, info->noa_count_para);
+
+ hdr_info.sub_cmd_id = SUB_CMD_ID_P2PPS;
+ hdr_info.content_size = 24;
+ hdr_info.ack = _FALSE;
+ set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+
+ status = send_h2c_pkt_88xx(adapter, h2c_buf);
+
+ if (status != HALMAC_RET_SUCCESS)
+ PLTFM_MSG_ERR("[ERR]send h2c!!\n");
+
+ return status;
+}
+
+/**
+ * query_status_88xx() -query the offload feature status
+ * @adapter : the adapter of halmac
+ * @feature_id : feature_id
+ * @proc_status : feature_status
+ * @data : data buffer
+ * @size : data size
+ *
+ * Note :
+ * If user wants to know the data size, user can allocate zero
+ * size buffer first. If this size less than the data size, halmac
+ * will return HALMAC_RET_BUFFER_TOO_SMALL. User need to
+ * re-allocate data buffer with correct data size.
+ *
+ * Author : Ivan Lin/KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+query_status_88xx(struct halmac_adapter *adapter,
+ enum halmac_feature_id feature_id,
+ enum halmac_cmd_process_status *proc_status, u8 *data,
+ u32 *size)
+{
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ if (!proc_status)
+ return HALMAC_RET_NULL_POINTER;
+
+ switch (feature_id) {
+ case HALMAC_FEATURE_CFG_PARA:
+ status = get_cfg_param_status_88xx(adapter, proc_status);
+ break;
+ case HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE:
+ status = get_dump_phy_efuse_status_88xx(adapter, proc_status,
+ data, size);
+ break;
+ case HALMAC_FEATURE_DUMP_LOGICAL_EFUSE:
+ status = get_dump_log_efuse_status_88xx(adapter, proc_status,
+ data, size);
+ break;
+ case HALMAC_FEATURE_CHANNEL_SWITCH:
+ status = get_ch_switch_status_88xx(adapter, proc_status);
+ break;
+ case HALMAC_FEATURE_UPDATE_PACKET:
+ status = get_update_packet_status_88xx(adapter, proc_status);
+ break;
+ case HALMAC_FEATURE_IQK:
+ status = get_iqk_status_88xx(adapter, proc_status);
+ break;
+ case HALMAC_FEATURE_POWER_TRACKING:
+ status = get_pwr_trk_status_88xx(adapter, proc_status);
+ break;
+ case HALMAC_FEATURE_PSD:
+ status = get_psd_status_88xx(adapter, proc_status, data, size);
+ break;
+ case HALMAC_FEATURE_FW_SNDING:
+ status = get_fw_snding_status_88xx(adapter, proc_status);
+ break;
+ default:
+ return HALMAC_RET_INVALID_FEATURE_ID;
+ }
+
+ return status;
+}
+
+static enum halmac_ret_status
+get_cfg_param_status_88xx(struct halmac_adapter *adapter,
+ enum halmac_cmd_process_status *proc_status)
+{
+ *proc_status = adapter->halmac_state.cfg_param_state.proc_status;
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+get_ch_switch_status_88xx(struct halmac_adapter *adapter,
+ enum halmac_cmd_process_status *proc_status)
+{
+ *proc_status = adapter->halmac_state.scan_state.proc_status;
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+get_update_packet_status_88xx(struct halmac_adapter *adapter,
+ enum halmac_cmd_process_status *proc_status)
+{
+ *proc_status = adapter->halmac_state.update_pkt_state.proc_status;
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_drv_rsvd_pg_num_88xx() -config reserved page number for driver
+ * @adapter : the adapter of halmac
+ * @pg_num : page number
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_drv_rsvd_pg_num_88xx(struct halmac_adapter *adapter,
+ enum halmac_drv_rsvd_pg_num pg_num)
+{
+ if (adapter->api_registry.cfg_drv_rsvd_pg_en == 0)
+ return HALMAC_RET_NOT_SUPPORT;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+ PLTFM_MSG_TRACE("[TRACE]pg_num = %d\n", pg_num);
+
+ switch (pg_num) {
+ case HALMAC_RSVD_PG_NUM8:
+ adapter->txff_alloc.rsvd_drv_pg_num = 8;
+ break;
+ case HALMAC_RSVD_PG_NUM16:
+ adapter->txff_alloc.rsvd_drv_pg_num = 16;
+ break;
+ case HALMAC_RSVD_PG_NUM24:
+ adapter->txff_alloc.rsvd_drv_pg_num = 24;
+ break;
+ case HALMAC_RSVD_PG_NUM32:
+ adapter->txff_alloc.rsvd_drv_pg_num = 32;
+ break;
+ case HALMAC_RSVD_PG_NUM64:
+ adapter->txff_alloc.rsvd_drv_pg_num = 64;
+ break;
+ case HALMAC_RSVD_PG_NUM128:
+ adapter->txff_alloc.rsvd_drv_pg_num = 128;
+ break;
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * (debug API)h2c_lb_88xx() - send h2c loopback packet
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+h2c_lb_88xx(struct halmac_adapter *adapter)
+{
+ return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+pwr_seq_parser_88xx(struct halmac_adapter *adapter,
+ struct halmac_wlan_pwr_cfg **cmd_seq)
+{
+ u8 cut;
+ u8 intf;
+ u32 idx = 0;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+ struct halmac_wlan_pwr_cfg *cmd;
+
+ switch (adapter->chip_ver) {
+ case HALMAC_CHIP_VER_A_CUT:
+ cut = HALMAC_PWR_CUT_A_MSK;
+ break;
+ case HALMAC_CHIP_VER_B_CUT:
+ cut = HALMAC_PWR_CUT_B_MSK;
+ break;
+ case HALMAC_CHIP_VER_C_CUT:
+ cut = HALMAC_PWR_CUT_C_MSK;
+ break;
+ case HALMAC_CHIP_VER_D_CUT:
+ cut = HALMAC_PWR_CUT_D_MSK;
+ break;
+ case HALMAC_CHIP_VER_E_CUT:
+ cut = HALMAC_PWR_CUT_E_MSK;
+ break;
+ case HALMAC_CHIP_VER_F_CUT:
+ cut = HALMAC_PWR_CUT_F_MSK;
+ break;
+ case HALMAC_CHIP_VER_TEST:
+ cut = HALMAC_PWR_CUT_TESTCHIP_MSK;
+ break;
+ default:
+ PLTFM_MSG_ERR("[ERR]cut version!!\n");
+ return HALMAC_RET_SWITCH_CASE_ERROR;
+ }
+
+ switch (adapter->intf) {
+ case HALMAC_INTERFACE_PCIE:
+ case HALMAC_INTERFACE_AXI:
+ intf = HALMAC_PWR_INTF_PCI_MSK;
+ break;
+ case HALMAC_INTERFACE_USB:
+ intf = HALMAC_PWR_INTF_USB_MSK;
+ break;
+ case HALMAC_INTERFACE_SDIO:
+ intf = HALMAC_PWR_INTF_SDIO_MSK;
+ break;
+ default:
+ PLTFM_MSG_ERR("[ERR]interface!!\n");
+ return HALMAC_RET_SWITCH_CASE_ERROR;
+ }
+
+ do {
+ cmd = cmd_seq[idx];
+
+ if (!cmd)
+ break;
+
+ status = pwr_sub_seq_parser_88xx(adapter, cut, intf, cmd);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]pwr sub seq!!\n");
+ return status;
+ }
+
+ idx++;
+ } while (1);
+
+ return status;
+}
+
+static enum halmac_ret_status
+pwr_sub_seq_parser_88xx(struct halmac_adapter *adapter, u8 cut, u8 intf,
+ struct halmac_wlan_pwr_cfg *cmd)
+{
+ u8 value;
+ u32 offset;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ do {
+ if ((cmd->interface_msk & intf) && (cmd->cut_msk & cut)) {
+ switch (cmd->cmd) {
+ case HALMAC_PWR_CMD_WRITE:
+ offset = cmd->offset;
+
+ if (cmd->base == HALMAC_PWR_ADDR_SDIO)
+ offset |= SDIO_LOCAL_OFFSET;
+
+ value = HALMAC_REG_R8(offset);
+ value = (u8)(value & (u8)(~(cmd->msk)));
+ value = (u8)(value | (cmd->value & cmd->msk));
+
+ HALMAC_REG_W8(offset, value);
+ break;
+ case HALMAC_PWR_CMD_POLLING:
+ if (pwr_cmd_polling_88xx(adapter, cmd) !=
+ HALMAC_RET_SUCCESS)
+ return HALMAC_RET_PWRSEQ_POLLING_FAIL;
+ break;
+ case HALMAC_PWR_CMD_DELAY:
+ if (cmd->value == HALMAC_PWR_DELAY_US)
+ PLTFM_DELAY_US(cmd->offset);
+ else
+ PLTFM_DELAY_US(1000 * cmd->offset);
+ break;
+ case HALMAC_PWR_CMD_READ:
+ break;
+ case HALMAC_PWR_CMD_END:
+ return HALMAC_RET_SUCCESS;
+ default:
+ return HALMAC_RET_PWRSEQ_CMD_INCORRECT;
+ }
+ }
+ cmd++;
+ } while (1);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+pwr_cmd_polling_88xx(struct halmac_adapter *adapter,
+ struct halmac_wlan_pwr_cfg *cmd)
+{
+ u8 value;
+ u8 flg;
+ u8 poll_bit;
+ u32 offset;
+ u32 cnt;
+ static u32 stats;
+ enum halmac_interface intf;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ poll_bit = 0;
+ cnt = HALMAC_PWR_POLLING_CNT;
+ flg = 0;
+ intf = adapter->intf;
+
+ if (cmd->base == HALMAC_PWR_ADDR_SDIO)
+ offset = cmd->offset | SDIO_LOCAL_OFFSET;
+ else
+ offset = cmd->offset;
+
+ do {
+ cnt--;
+ value = HALMAC_REG_R8(offset);
+ value = (u8)(value & cmd->msk);
+
+ if (value == (cmd->value & cmd->msk)) {
+ poll_bit = 1;
+ } else {
+ if (cnt == 0) {
+ if (intf == HALMAC_INTERFACE_PCIE && flg == 0) {
+ /* PCIE + USB package */
+ /* power bit polling timeout issue */
+ stats++;
+ PLTFM_MSG_WARN("[WARN]PCIE stats:%d\n",
+ stats);
+ value = HALMAC_REG_R8(REG_SYS_PW_CTRL);
+ value |= BIT(3);
+ HALMAC_REG_W8(REG_SYS_PW_CTRL, value);
+ value &= ~BIT(3);
+ HALMAC_REG_W8(REG_SYS_PW_CTRL, value);
+ poll_bit = 0;
+ cnt = HALMAC_PWR_POLLING_CNT;
+ flg = 1;
+ } else {
+ PLTFM_MSG_ERR("[ERR]polling to!!\n");
+ PLTFM_MSG_ERR("[ERR]cmd offset:%X\n",
+ cmd->offset);
+ PLTFM_MSG_ERR("[ERR]cmd value:%X\n",
+ cmd->value);
+ PLTFM_MSG_ERR("[ERR]cmd msk:%X\n",
+ cmd->msk);
+ PLTFM_MSG_ERR("[ERR]offset = %X\n",
+ offset);
+ PLTFM_MSG_ERR("[ERR]value = %X\n",
+ value);
+ return HALMAC_RET_PWRSEQ_POLLING_FAIL;
+ }
+ } else {
+ PLTFM_DELAY_US(50);
+ }
+ }
+ } while (!poll_bit);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+parse_intf_phy_88xx(struct halmac_adapter *adapter,
+ struct halmac_intf_phy_para *param,
+ enum halmac_intf_phy_platform pltfm,
+ enum hal_intf_phy intf_phy)
+{
+ u16 value;
+ u16 cur_cut;
+ u16 offset;
+ u16 ip_sel;
+ struct halmac_intf_phy_para *cur_param;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+ u8 result = HALMAC_RET_SUCCESS;
+
+ switch (adapter->chip_ver) {
+ case HALMAC_CHIP_VER_A_CUT:
+ cur_cut = (u16)HALMAC_INTF_PHY_CUT_A;
+ break;
+ case HALMAC_CHIP_VER_B_CUT:
+ cur_cut = (u16)HALMAC_INTF_PHY_CUT_B;
+ break;
+ case HALMAC_CHIP_VER_C_CUT:
+ cur_cut = (u16)HALMAC_INTF_PHY_CUT_C;
+ break;
+ case HALMAC_CHIP_VER_D_CUT:
+ cur_cut = (u16)HALMAC_INTF_PHY_CUT_D;
+ break;
+ case HALMAC_CHIP_VER_E_CUT:
+ cur_cut = (u16)HALMAC_INTF_PHY_CUT_E;
+ break;
+ case HALMAC_CHIP_VER_F_CUT:
+ cur_cut = (u16)HALMAC_INTF_PHY_CUT_F;
+ break;
+ case HALMAC_CHIP_VER_TEST:
+ cur_cut = (u16)HALMAC_INTF_PHY_CUT_TESTCHIP;
+ break;
+ default:
+ return HALMAC_RET_FAIL;
+ }
+
+ cur_param = param;
+
+ do {
+ if ((cur_param->cut & cur_cut) &&
+ (cur_param->plaform & (u16)pltfm)) {
+ offset = cur_param->offset;
+ value = cur_param->value;
+ ip_sel = cur_param->ip_sel;
+
+ if (offset == 0xFFFF)
+ break;
+
+ if (ip_sel == HALMAC_IP_SEL_MAC) {
+ HALMAC_REG_W8((u32)offset, (u8)value);
+ } else if (intf_phy == HAL_INTF_PHY_USB2 ||
+ intf_phy == HAL_INTF_PHY_USB3) {
+ result = usbphy_write_88xx(adapter, (u8)offset,
+ value, intf_phy);
+ if (result != HALMAC_RET_SUCCESS)
+ PLTFM_MSG_ERR("[ERR]usb phy!!\n");
+
+ } else if (intf_phy == HAL_INTF_PHY_PCIE_GEN1 ||
+ intf_phy == HAL_INTF_PHY_PCIE_GEN2) {
+ if (ip_sel == HALMAC_IP_INTF_PHY)
+ result = mdio_write_88xx(adapter,
+ (u8)offset,
+ value,
+ intf_phy);
+ else
+ result = dbi_w8_88xx(adapter, offset,
+ (u8)value);
+ if (result != HALMAC_RET_SUCCESS)
+ PLTFM_MSG_ERR("[ERR]mdio/dbi!!\n");
+
+ } else {
+ PLTFM_MSG_ERR("[ERR]intf phy sel!!\n");
+ }
+ }
+ cur_param++;
+ } while (1);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * txfifo_is_empty_88xx() -check if txfifo is empty
+ * @adapter : the adapter of halmac
+ * @chk_num : check number
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+txfifo_is_empty_88xx(struct halmac_adapter *adapter, u32 chk_num)
+{
+ u32 cnt;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ cnt = (chk_num <= 10) ? 10 : chk_num;
+ do {
+ if (HALMAC_REG_R8(REG_TXPKT_EMPTY) != 0xFF)
+ return HALMAC_RET_TXFIFO_NO_EMPTY;
+
+ if ((HALMAC_REG_R8(REG_TXPKT_EMPTY + 1) & 0x06) != 0x06)
+ return HALMAC_RET_TXFIFO_NO_EMPTY;
+ cnt--;
+
+ } while (cnt != 0);
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * (internal use)
+ * smart_malloc_88xx() - adapt malloc size
+ * @adapter : the adapter of halmac
+ * @size : expected malloc size
+ * @pNew_size : real malloc size
+ * Author : Ivan Lin
+ * Return : address pointer
+ */
+u8*
+smart_malloc_88xx(struct halmac_adapter *adapter, u32 size, u32 *new_size)
+{
+ u8 retry_num;
+ u8 *malloc_buf = NULL;
+
+ for (retry_num = 0; retry_num < 5; retry_num++) {
+ malloc_buf = (u8 *)PLTFM_MALLOC(size);
+
+ if (malloc_buf) {
+ *new_size = size;
+ return malloc_buf;
+ }
+
+ size = size >> 1;
+
+ if (size == 0)
+ break;
+ }
+
+ PLTFM_MSG_ERR("[ERR]adptive malloc!!\n");
+
+ return NULL;
+}
+
+/**
+ * (internal use)
+ * ltecoex_reg_read_88xx() - read ltecoex register
+ * @adapter : the adapter of halmac
+ * @offset : offset
+ * @pValue : value
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ */
+enum halmac_ret_status
+ltecoex_reg_read_88xx(struct halmac_adapter *adapter, u16 offset, u32 *value)
+{
+ u32 cnt;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ cnt = 10000;
+ while ((HALMAC_REG_R8(LTECOEX_ACCESS_CTRL + 3) & BIT(5)) == 0) {
+ if (cnt == 0) {
+ PLTFM_MSG_ERR("[ERR]lte ready(R)\n");
+ return HALMAC_RET_LTECOEX_READY_FAIL;
+ }
+ cnt--;
+ PLTFM_DELAY_US(50);
+ }
+
+ HALMAC_REG_W32(LTECOEX_ACCESS_CTRL, 0x800F0000 | offset);
+ *value = HALMAC_REG_R32(REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * (internal use)
+ * ltecoex_reg_write_88xx() - write ltecoex register
+ * @adapter : the adapter of halmac
+ * @offset : offset
+ * @value : value
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ */
+enum halmac_ret_status
+ltecoex_reg_write_88xx(struct halmac_adapter *adapter, u16 offset, u32 value)
+{
+ u32 cnt;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ cnt = 10000;
+ while ((HALMAC_REG_R8(LTECOEX_ACCESS_CTRL + 3) & BIT(5)) == 0) {
+ if (cnt == 0) {
+ PLTFM_MSG_ERR("[ERR]lte ready(W)\n");
+ return HALMAC_RET_LTECOEX_READY_FAIL;
+ }
+ cnt--;
+ PLTFM_DELAY_US(50);
+ }
+
+ HALMAC_REG_W32(REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1, value);
+ HALMAC_REG_W32(LTECOEX_ACCESS_CTRL, 0xC00F0000 | offset);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static void
+pwr_state_88xx(struct halmac_adapter *adapter, enum halmac_mac_power *state)
+{
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ if ((HALMAC_REG_R8(REG_SYS_FUNC_EN + 1) & BIT(3)) == 0)
+ *state = HALMAC_MAC_POWER_OFF;
+ else
+ *state = HALMAC_MAC_POWER_ON;
+}
+
+#endif /* HALMAC_88XX_SUPPORT */
diff --git a/hal/halmac/halmac_88xx/halmac_common_88xx.h b/hal/halmac/halmac_88xx/halmac_common_88xx.h
new file mode 100644
index 0000000..8b77a5d
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_common_88xx.h
@@ -0,0 +1,155 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_COMMON_88XX_H_
+#define _HALMAC_COMMON_88XX_H_
+
+#include "../halmac_api.h"
+#include "../halmac_pwr_seq_cmd.h"
+#include "../halmac_gpio_cmd.h"
+
+#if HALMAC_88XX_SUPPORT
+
+enum halmac_ret_status
+ofld_func_cfg_88xx(struct halmac_adapter *adapter,
+ struct halmac_ofld_func_info *info);
+
+enum halmac_ret_status
+dl_drv_rsvd_page_88xx(struct halmac_adapter *adapter, u8 pg_offset, u8 *buf,
+ u32 size);
+
+enum halmac_ret_status
+dl_rsvd_page_88xx(struct halmac_adapter *adapter, u16 pg_addr, u8 *buf,
+ u32 size);
+
+enum halmac_ret_status
+get_hw_value_88xx(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,
+ void *value);
+
+enum halmac_ret_status
+set_hw_value_88xx(struct halmac_adapter *adapter, enum halmac_hw_id hw_id,
+ void *value);
+
+enum halmac_ret_status
+set_h2c_pkt_hdr_88xx(struct halmac_adapter *adapter, u8 *hdr,
+ struct halmac_h2c_header_info *info, u16 *seq_num);
+
+enum halmac_ret_status
+send_h2c_pkt_88xx(struct halmac_adapter *adapter, u8 *pkt);
+
+enum halmac_ret_status
+get_h2c_buf_free_space_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+get_c2h_info_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+enum halmac_ret_status
+mac_debug_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+cfg_parameter_88xx(struct halmac_adapter *adapter,
+ struct halmac_phy_parameter_info *info, u8 full_fifo);
+
+enum halmac_ret_status
+update_packet_88xx(struct halmac_adapter *adapter, enum halmac_packet_id pkt_id,
+ u8 *pkt, u32 size);
+
+enum halmac_ret_status
+bcn_ie_filter_88xx(struct halmac_adapter *adapter,
+ struct halmac_bcn_ie_info *info);
+
+enum halmac_ret_status
+update_datapack_88xx(struct halmac_adapter *adapter,
+ enum halmac_data_type data_type,
+ struct halmac_phy_parameter_info *info);
+
+enum halmac_ret_status
+run_datapack_88xx(struct halmac_adapter *adapter,
+ enum halmac_data_type data_type);
+
+enum halmac_ret_status
+send_bt_coex_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size, u8 ack);
+
+enum halmac_ret_status
+dump_fifo_88xx(struct halmac_adapter *adapter, enum hal_fifo_sel sel,
+ u32 start_addr, u32 size, u8 *data);
+
+u32
+get_fifo_size_88xx(struct halmac_adapter *adapter, enum hal_fifo_sel sel);
+
+enum halmac_ret_status
+set_h2c_header_88xx(struct halmac_adapter *adapter, u8 *hdr, u16 *seq, u8 ack);
+
+enum halmac_ret_status
+add_ch_info_88xx(struct halmac_adapter *adapter, struct halmac_ch_info *info);
+
+enum halmac_ret_status
+add_extra_ch_info_88xx(struct halmac_adapter *adapter,
+ struct halmac_ch_extra_info *info);
+
+enum halmac_ret_status
+ctrl_ch_switch_88xx(struct halmac_adapter *adapter,
+ struct halmac_ch_switch_option *opt);
+
+enum halmac_ret_status
+clear_ch_info_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+chk_txdesc_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+enum halmac_ret_status
+get_version_88xx(struct halmac_adapter *adapter, struct halmac_ver *ver);
+
+enum halmac_ret_status
+p2pps_88xx(struct halmac_adapter *adapter, struct halmac_p2pps *info);
+
+enum halmac_ret_status
+query_status_88xx(struct halmac_adapter *adapter,
+ enum halmac_feature_id feature_id,
+ enum halmac_cmd_process_status *proc_status, u8 *data,
+ u32 *size);
+
+enum halmac_ret_status
+cfg_drv_rsvd_pg_num_88xx(struct halmac_adapter *adapter,
+ enum halmac_drv_rsvd_pg_num pg_num);
+
+enum halmac_ret_status
+h2c_lb_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+pwr_seq_parser_88xx(struct halmac_adapter *adapter,
+ struct halmac_wlan_pwr_cfg **cmd_seq);
+
+enum halmac_ret_status
+parse_intf_phy_88xx(struct halmac_adapter *adapter,
+ struct halmac_intf_phy_para *param,
+ enum halmac_intf_phy_platform pltfm,
+ enum hal_intf_phy intf_phy);
+
+enum halmac_ret_status
+txfifo_is_empty_88xx(struct halmac_adapter *adapter, u32 chk_num);
+
+u8*
+smart_malloc_88xx(struct halmac_adapter *adapter, u32 size, u32 *new_size);
+
+enum halmac_ret_status
+ltecoex_reg_read_88xx(struct halmac_adapter *adapter, u16 offset, u32 *value);
+
+enum halmac_ret_status
+ltecoex_reg_write_88xx(struct halmac_adapter *adapter, u16 offset, u32 value);
+
+#endif/* HALMAC_88XX_SUPPORT */
+
+#endif/* _HALMAC_COMMON_88XX_H_ */
diff --git a/hal/halmac/halmac_88xx/halmac_efuse_88xx.c b/hal/halmac/halmac_88xx/halmac_efuse_88xx.c
new file mode 100644
index 0000000..d271b0c
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_efuse_88xx.c
@@ -0,0 +1,1902 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_efuse_88xx.h"
+#include "halmac_88xx_cfg.h"
+#include "halmac_common_88xx.h"
+#include "halmac_init_88xx.h"
+
+#if HALMAC_88XX_SUPPORT
+
+#define RSVD_EFUSE_SIZE 16
+#define RSVD_CS_EFUSE_SIZE 24
+#define PROTECT_EFUSE_SIZE 96
+#define FEATURE_DUMP_PHY_EFUSE HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE
+#define FEATURE_DUMP_LOG_EFUSE HALMAC_FEATURE_DUMP_LOGICAL_EFUSE
+
+static enum halmac_cmd_construct_state
+efuse_cmd_cnstr_state_88xx(struct halmac_adapter *adapter);
+
+static enum halmac_ret_status
+proc_dump_efuse_88xx(struct halmac_adapter *adapter,
+ enum halmac_efuse_read_cfg cfg);
+
+static enum halmac_ret_status
+read_hw_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
+ u8 *map);
+
+static enum halmac_ret_status
+eeprom_parser_88xx(struct halmac_adapter *adapter, u8 *phy_map, u8 *log_map);
+
+static enum halmac_ret_status
+read_log_efuse_map_88xx(struct halmac_adapter *adapter, u8 *map);
+
+static enum halmac_ret_status
+proc_pg_efuse_by_map_88xx(struct halmac_adapter *adapter,
+ struct halmac_pg_efuse_info *info,
+ enum halmac_efuse_read_cfg cfg);
+
+static enum halmac_ret_status
+dump_efuse_fw_88xx(struct halmac_adapter *adapter);
+
+static enum halmac_ret_status
+dump_efuse_drv_88xx(struct halmac_adapter *adapter);
+
+static enum halmac_ret_status
+proc_write_log_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value);
+
+static enum halmac_ret_status
+update_eeprom_mask_88xx(struct halmac_adapter *adapter,
+ struct halmac_pg_efuse_info *info, u8 *updated_mask);
+
+static enum halmac_ret_status
+check_efuse_enough_88xx(struct halmac_adapter *adapter,
+ struct halmac_pg_efuse_info *info, u8 *updated_mask);
+
+static enum halmac_ret_status
+pg_extend_efuse_88xx(struct halmac_adapter *adapter,
+ struct halmac_pg_efuse_info *info, u8 word_en,
+ u8 pre_word_en, u32 eeprom_offset);
+
+static enum halmac_ret_status
+proc_pg_efuse_88xx(struct halmac_adapter *adapter,
+ struct halmac_pg_efuse_info *info, u8 word_en,
+ u8 pre_word_en, u32 eeprom_offset);
+
+static enum halmac_ret_status
+program_efuse_88xx(struct halmac_adapter *adapter,
+ struct halmac_pg_efuse_info *info, u8 *updated_mask);
+
+static void
+mask_eeprom_88xx(struct halmac_adapter *adapter,
+ struct halmac_pg_efuse_info *info);
+
+/**
+ * dump_efuse_map_88xx() - dump "physical" efuse map
+ * @adapter : the adapter of halmac
+ * @cfg : dump efuse method
+ * Author : Ivan Lin/KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+dump_efuse_map_88xx(struct halmac_adapter *adapter,
+ enum halmac_efuse_read_cfg cfg)
+{
+ u8 *map = NULL;
+ u8 *efuse_map;
+ u32 efuse_size = adapter->hw_cfg_info.efuse_size;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+ enum halmac_cmd_process_status *proc_status;
+
+ proc_status = &adapter->halmac_state.efuse_state.proc_status;
+
+ if (cfg == HALMAC_EFUSE_R_FW &&
+ halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
+ return HALMAC_RET_NO_DLFW;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+ PLTFM_MSG_TRACE("[TRACE]cfg = %d\n", cfg);
+
+ if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+ PLTFM_MSG_WARN("[WARN]Wait event(efuse)\n");
+ return HALMAC_RET_BUSY_STATE;
+ }
+
+ if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) {
+ PLTFM_MSG_WARN("[WARN]Not idle(efuse)\n");
+ return HALMAC_RET_ERROR_STATE;
+ }
+
+ if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF)
+ PLTFM_MSG_ERR("[ERR]Dump efuse in suspend\n");
+
+ *proc_status = HALMAC_CMD_PROCESS_IDLE;
+ adapter->evnt.phy_efuse_map = 1;
+
+ status = switch_efuse_bank_88xx(adapter, HALMAC_EFUSE_BANK_WIFI);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]switch efuse bank!!\n");
+ return status;
+ }
+
+ status = proc_dump_efuse_88xx(adapter, cfg);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]dump efuse!!\n");
+ return status;
+ }
+
+ if (adapter->efuse_map_valid == _TRUE) {
+ *proc_status = HALMAC_CMD_PROCESS_DONE;
+ efuse_map = adapter->efuse_map;
+
+ map = (u8 *)PLTFM_MALLOC(efuse_size);
+ if (!map) {
+ PLTFM_MSG_ERR("[ERR]malloc!!\n");
+ return HALMAC_RET_MALLOC_FAIL;
+ }
+ PLTFM_MEMSET(map, 0xFF, efuse_size);
+ PLTFM_MUTEX_LOCK(&adapter->efuse_mutex);
+ PLTFM_MEMCPY(map, efuse_map, efuse_size - PROTECT_EFUSE_SIZE);
+ PLTFM_MEMCPY(map + efuse_size - PROTECT_EFUSE_SIZE +
+ RSVD_CS_EFUSE_SIZE,
+ efuse_map + efuse_size - PROTECT_EFUSE_SIZE +
+ RSVD_CS_EFUSE_SIZE,
+ PROTECT_EFUSE_SIZE - RSVD_EFUSE_SIZE -
+ RSVD_CS_EFUSE_SIZE);
+ PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex);
+
+ PLTFM_EVENT_SIG(HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE,
+ *proc_status, map, efuse_size);
+ adapter->evnt.phy_efuse_map = 0;
+
+ PLTFM_FREE(map, efuse_size);
+ }
+
+ if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=
+ HALMAC_RET_SUCCESS)
+ return HALMAC_RET_ERROR_STATE;
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * dump_efuse_map_bt_88xx() - dump "BT physical" efuse map
+ * @adapter : the adapter of halmac
+ * @bank : bt efuse bank
+ * @size : bt efuse map size. get from halmac_get_efuse_size API
+ * @map : bt efuse map
+ * Author : Soar / Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+dump_efuse_map_bt_88xx(struct halmac_adapter *adapter,
+ enum halmac_efuse_bank bank, u32 size, u8 *map)
+{
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+ enum halmac_cmd_process_status *proc_status;
+
+ proc_status = &adapter->halmac_state.efuse_state.proc_status;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (adapter->hw_cfg_info.bt_efuse_size != size)
+ return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+
+ if (bank >= HALMAC_EFUSE_BANK_MAX || bank == HALMAC_EFUSE_BANK_WIFI) {
+ PLTFM_MSG_ERR("[ERR]Undefined BT bank\n");
+ return HALMAC_RET_EFUSE_BANK_INCORRECT;
+ }
+
+ if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+ PLTFM_MSG_WARN("[WARN]Wait event(efuse)\n");
+ return HALMAC_RET_BUSY_STATE;
+ }
+
+ if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) {
+ PLTFM_MSG_WARN("[WARN]Not idle(efuse)\n");
+ return HALMAC_RET_ERROR_STATE;
+ }
+
+ status = switch_efuse_bank_88xx(adapter, bank);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]switch efuse bank!!\n");
+ return status;
+ }
+
+ status = read_hw_efuse_88xx(adapter, 0, size, map);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]read hw efuse\n");
+ return status;
+ }
+
+ if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=
+ HALMAC_RET_SUCCESS)
+ return HALMAC_RET_ERROR_STATE;
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * write_efuse_bt_88xx() - write "BT physical" efuse offset
+ * @adapter : the adapter of halmac
+ * @offset : offset
+ * @value : Write value
+ * @map : bt efuse map
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+write_efuse_bt_88xx(struct halmac_adapter *adapter, u32 offset, u8 value,
+ enum halmac_efuse_bank bank)
+{
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+ enum halmac_cmd_process_status *proc_status;
+
+ proc_status = &adapter->halmac_state.efuse_state.proc_status;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+ PLTFM_MSG_WARN("[WARN]Wait event(efuse)\n");
+ return HALMAC_RET_BUSY_STATE;
+ }
+
+ if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) {
+ PLTFM_MSG_WARN("[WARN]Not idle(efuse)\n");
+ return HALMAC_RET_ERROR_STATE;
+ }
+
+ if (offset >= adapter->hw_cfg_info.efuse_size) {
+ PLTFM_MSG_ERR("[ERR]Offset is too large\n");
+ return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+ }
+
+ if (bank > HALMAC_EFUSE_BANK_MAX || bank == HALMAC_EFUSE_BANK_WIFI) {
+ PLTFM_MSG_ERR("[ERR]Undefined BT bank\n");
+ return HALMAC_RET_EFUSE_BANK_INCORRECT;
+ }
+
+ status = switch_efuse_bank_88xx(adapter, bank);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]switch efuse bank!!\n");
+ return status;
+ }
+
+ status = write_hw_efuse_88xx(adapter, offset, value);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]write efuse\n");
+ return status;
+ }
+
+ if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=
+ HALMAC_RET_SUCCESS)
+ return HALMAC_RET_ERROR_STATE;
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * read_efuse_bt_88xx() - read "BT physical" efuse offset
+ * @adapter : the adapter of halmac
+ * @offset : offset
+ * @value : 1 byte efuse value
+ * @bank : efuse bank
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+read_efuse_bt_88xx(struct halmac_adapter *adapter, u32 offset, u8 *value,
+ enum halmac_efuse_bank bank)
+{
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+ enum halmac_cmd_process_status *proc_status =
+ &adapter->halmac_state.efuse_state.proc_status;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+ PLTFM_MSG_WARN("[WARN]Wait event(efuse)\n");
+ return HALMAC_RET_BUSY_STATE;
+ }
+
+ if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) {
+ PLTFM_MSG_WARN("[WARN]Not idle(efuse)\n");
+ return HALMAC_RET_ERROR_STATE;
+ }
+
+ if (offset >= adapter->hw_cfg_info.efuse_size) {
+ PLTFM_MSG_ERR("[ERR]Offset is too large\n");
+ return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+ }
+
+ if (bank > HALMAC_EFUSE_BANK_MAX || bank == HALMAC_EFUSE_BANK_WIFI) {
+ PLTFM_MSG_ERR("[ERR]Undefined BT bank\n");
+ return HALMAC_RET_EFUSE_BANK_INCORRECT;
+ }
+
+ status = switch_efuse_bank_88xx(adapter, bank);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]switch efuse bank\n");
+ return status;
+ }
+
+ status = read_efuse_88xx(adapter, offset, 1, value);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]read efuse\n");
+ return status;
+ }
+
+ if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=
+ HALMAC_RET_SUCCESS)
+ return HALMAC_RET_ERROR_STATE;
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_efuse_auto_check_88xx() - check efuse after writing it
+ * @adapter : the adapter of halmac
+ * @enable : 1, enable efuse auto check. others, disable
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_efuse_auto_check_88xx(struct halmac_adapter *adapter, u8 enable)
+{
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ adapter->efuse_auto_check_en = enable;
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * get_efuse_available_size_88xx() - get efuse available size
+ * @adapter : the adapter of halmac
+ * @size : physical efuse available size
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+get_efuse_available_size_88xx(struct halmac_adapter *adapter, u32 *size)
+{
+ enum halmac_ret_status status;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ status = dump_log_efuse_map_88xx(adapter, HALMAC_EFUSE_R_DRV);
+
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+
+ *size = adapter->hw_cfg_info.efuse_size - PROTECT_EFUSE_SIZE -
+ adapter->efuse_end;
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * get_efuse_size_88xx() - get "physical" efuse size
+ * @adapter : the adapter of halmac
+ * @size : physical efuse size
+ * Author : Ivan Lin/KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+get_efuse_size_88xx(struct halmac_adapter *adapter, u32 *size)
+{
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ *size = adapter->hw_cfg_info.efuse_size;
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * get_log_efuse_size_88xx() - get "logical" efuse size
+ * @adapter : the adapter of halmac
+ * @size : logical efuse size
+ * Author : Ivan Lin/KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+get_log_efuse_size_88xx(struct halmac_adapter *adapter, u32 *size)
+{
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ *size = adapter->hw_cfg_info.eeprom_size;
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * dump_log_efuse_map_88xx() - dump "logical" efuse map
+ * @adapter : the adapter of halmac
+ * @cfg : dump efuse method
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+dump_log_efuse_map_88xx(struct halmac_adapter *adapter,
+ enum halmac_efuse_read_cfg cfg)
+{
+ u8 *map = NULL;
+ u32 size = adapter->hw_cfg_info.eeprom_size;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+ enum halmac_cmd_process_status *proc_status =
+ &adapter->halmac_state.efuse_state.proc_status;
+
+ if (cfg == HALMAC_EFUSE_R_FW &&
+ halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
+ return HALMAC_RET_NO_DLFW;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+ PLTFM_MSG_TRACE("[TRACE]cfg = %d\n", cfg);
+
+ if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+ PLTFM_MSG_WARN("[WARN]Wait event(efuse)\n");
+ return HALMAC_RET_BUSY_STATE;
+ }
+
+ if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) {
+ PLTFM_MSG_WARN("[WARN]Not idle(efuse)\n");
+ return HALMAC_RET_ERROR_STATE;
+ }
+
+ if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF)
+ PLTFM_MSG_ERR("[ERR]Dump efuse in suspend\n");
+
+ *proc_status = HALMAC_CMD_PROCESS_IDLE;
+ adapter->evnt.log_efuse_map = 1;
+
+ status = switch_efuse_bank_88xx(adapter, HALMAC_EFUSE_BANK_WIFI);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]switch efuse bank\n");
+ return status;
+ }
+
+ status = proc_dump_efuse_88xx(adapter, cfg);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]dump efuse\n");
+ return status;
+ }
+
+ if (adapter->efuse_map_valid == _TRUE) {
+ *proc_status = HALMAC_CMD_PROCESS_DONE;
+
+ map = (u8 *)PLTFM_MALLOC(size);
+ if (!map) {
+ PLTFM_MSG_ERR("[ERR]malloc map\n");
+ return HALMAC_RET_MALLOC_FAIL;
+ }
+ PLTFM_MEMSET(map, 0xFF, size);
+
+ if (eeprom_parser_88xx(adapter, adapter->efuse_map, map) !=
+ HALMAC_RET_SUCCESS) {
+ PLTFM_FREE(map, size);
+ return HALMAC_RET_EEPROM_PARSING_FAIL;
+ }
+
+ PLTFM_EVENT_SIG(HALMAC_FEATURE_DUMP_LOGICAL_EFUSE,
+ *proc_status, map, size);
+ adapter->evnt.log_efuse_map = 0;
+
+ PLTFM_FREE(map, size);
+ }
+
+ if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=
+ HALMAC_RET_SUCCESS)
+ return HALMAC_RET_ERROR_STATE;
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * read_logical_efuse_88xx() - read logical efuse map 1 byte
+ * @adapter : the adapter of halmac
+ * @offset : offset
+ * @value : 1 byte efuse value
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+read_logical_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 *value)
+{
+ u8 *map = NULL;
+ u32 size = adapter->hw_cfg_info.eeprom_size;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+ enum halmac_cmd_process_status *proc_status;
+
+ proc_status = &adapter->halmac_state.efuse_state.proc_status;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (offset >= size) {
+ PLTFM_MSG_ERR("[ERR]Offset is too large\n");
+ return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+ }
+
+ if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+ PLTFM_MSG_WARN("[WARN]Wait event(efuse)\n");
+ return HALMAC_RET_BUSY_STATE;
+ }
+ if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) {
+ PLTFM_MSG_WARN("[WARN]Not idle(efuse)\n");
+ return HALMAC_RET_ERROR_STATE;
+ }
+
+ status = switch_efuse_bank_88xx(adapter, HALMAC_EFUSE_BANK_WIFI);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]switch efuse bank\n");
+ return status;
+ }
+
+ map = (u8 *)PLTFM_MALLOC(size);
+ if (!map) {
+ PLTFM_MSG_ERR("[ERR]malloc map\n");
+ return HALMAC_RET_MALLOC_FAIL;
+ }
+ PLTFM_MEMSET(map, 0xFF, size);
+
+ status = read_log_efuse_map_88xx(adapter, map);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]read logical efuse\n");
+ PLTFM_FREE(map, size);
+ return status;
+ }
+
+ *value = *(map + offset);
+
+ if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=
+ HALMAC_RET_SUCCESS) {
+ PLTFM_FREE(map, size);
+ return HALMAC_RET_ERROR_STATE;
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ PLTFM_FREE(map, size);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * write_log_efuse_88xx() - write "logical" efuse offset
+ * @adapter : the adapter of halmac
+ * @offset : offset
+ * @value : value
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+write_log_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value)
+{
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+ enum halmac_cmd_process_status *proc_status;
+
+ proc_status = &adapter->halmac_state.efuse_state.proc_status;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (offset >= adapter->hw_cfg_info.eeprom_size) {
+ PLTFM_MSG_ERR("[ERR]Offset is too large\n");
+ return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+ }
+
+ if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+ PLTFM_MSG_WARN("[WARN]Wait event(efuse)\n");
+ return HALMAC_RET_BUSY_STATE;
+ }
+
+ if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) {
+ PLTFM_MSG_WARN("[WARN]Not idle(efuse)\n");
+ return HALMAC_RET_ERROR_STATE;
+ }
+
+ status = switch_efuse_bank_88xx(adapter, HALMAC_EFUSE_BANK_WIFI);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]switch efuse bank\n");
+ return status;
+ }
+
+ status = proc_write_log_efuse_88xx(adapter, offset, value);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]write logical efuse\n");
+ return status;
+ }
+
+ if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=
+ HALMAC_RET_SUCCESS)
+ return HALMAC_RET_ERROR_STATE;
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * pg_efuse_by_map_88xx() - pg logical efuse by map
+ * @adapter : the adapter of halmac
+ * @info : efuse map information
+ * @cfg : dump efuse method
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+pg_efuse_by_map_88xx(struct halmac_adapter *adapter,
+ struct halmac_pg_efuse_info *info,
+ enum halmac_efuse_read_cfg cfg)
+{
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+ enum halmac_cmd_process_status *proc_status;
+
+ proc_status = &adapter->halmac_state.efuse_state.proc_status;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (info->efuse_map_size != adapter->hw_cfg_info.eeprom_size) {
+ PLTFM_MSG_ERR("[ERR]map size error\n");
+ return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+ }
+
+ if ((info->efuse_map_size & 0xF) > 0) {
+ PLTFM_MSG_ERR("[ERR]not multiple of 16\n");
+ return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+ }
+
+ if (info->efuse_mask_size != info->efuse_map_size >> 4) {
+ PLTFM_MSG_ERR("[ERR]mask size error\n");
+ return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+ }
+
+ if (!info->efuse_map) {
+ PLTFM_MSG_ERR("[ERR]map is NULL\n");
+ return HALMAC_RET_NULL_POINTER;
+ }
+
+ if (!info->efuse_mask) {
+ PLTFM_MSG_ERR("[ERR]mask is NULL\n");
+ return HALMAC_RET_NULL_POINTER;
+ }
+
+ if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+ PLTFM_MSG_WARN("[WARN]Wait event(efuse)\n");
+ return HALMAC_RET_BUSY_STATE;
+ }
+
+ if (efuse_cmd_cnstr_state_88xx(adapter) != HALMAC_CMD_CNSTR_IDLE) {
+ PLTFM_MSG_WARN("[WARN]Not idle(efuse)\n");
+ return HALMAC_RET_ERROR_STATE;
+ }
+
+ status = switch_efuse_bank_88xx(adapter, HALMAC_EFUSE_BANK_WIFI);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]switch efuse bank\n");
+ return status;
+ }
+
+ status = proc_pg_efuse_by_map_88xx(adapter, info, cfg);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]pg efuse\n");
+ return status;
+ }
+
+ if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_IDLE) !=
+ HALMAC_RET_SUCCESS)
+ return HALMAC_RET_ERROR_STATE;
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * mask_log_efuse_88xx() - mask logical efuse
+ * @adapter : the adapter of halmac
+ * @info : efuse map information
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+mask_log_efuse_88xx(struct halmac_adapter *adapter,
+ struct halmac_pg_efuse_info *info)
+{
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (info->efuse_map_size != adapter->hw_cfg_info.eeprom_size) {
+ PLTFM_MSG_ERR("[ERR]map size error\n");
+ return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+ }
+
+ if ((info->efuse_map_size & 0xF) > 0) {
+ PLTFM_MSG_ERR("[ERR]not multiple of 16\n");
+ return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+ }
+
+ if (info->efuse_mask_size != info->efuse_map_size >> 4) {
+ PLTFM_MSG_ERR("[ERR]mask size error\n");
+ return HALMAC_RET_EFUSE_SIZE_INCORRECT;
+ }
+
+ if (!info->efuse_map) {
+ PLTFM_MSG_ERR("[ERR]map is NULL\n");
+ return HALMAC_RET_NULL_POINTER;
+ }
+
+ if (!info->efuse_mask) {
+ PLTFM_MSG_ERR("[ERR]mask is NULL\n");
+ return HALMAC_RET_NULL_POINTER;
+ }
+
+ mask_eeprom_88xx(adapter, info);
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_cmd_construct_state
+efuse_cmd_cnstr_state_88xx(struct halmac_adapter *adapter)
+{
+ return adapter->halmac_state.efuse_state.cmd_cnstr_state;
+}
+
+enum halmac_ret_status
+switch_efuse_bank_88xx(struct halmac_adapter *adapter,
+ enum halmac_efuse_bank bank)
+{
+ u8 reg_value;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_BUSY) !=
+ HALMAC_RET_SUCCESS)
+ return HALMAC_RET_ERROR_STATE;
+
+ reg_value = HALMAC_REG_R8(REG_LDO_EFUSE_CTRL + 1);
+
+ if (bank == (reg_value & (BIT(0) | BIT(1))))
+ return HALMAC_RET_SUCCESS;
+
+ reg_value &= ~(BIT(0) | BIT(1));
+ reg_value |= bank;
+ HALMAC_REG_W8(REG_LDO_EFUSE_CTRL + 1, reg_value);
+
+ reg_value = HALMAC_REG_R8(REG_LDO_EFUSE_CTRL + 1);
+ if ((reg_value & (BIT(0) | BIT(1))) != bank)
+ return HALMAC_RET_SWITCH_EFUSE_BANK_FAIL;
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+proc_dump_efuse_88xx(struct halmac_adapter *adapter,
+ enum halmac_efuse_read_cfg cfg)
+{
+ u32 h2c_init;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+ enum halmac_cmd_process_status *proc_status;
+
+ proc_status = &adapter->halmac_state.efuse_state.proc_status;
+
+ *proc_status = HALMAC_CMD_PROCESS_SENDING;
+
+ if (cnv_efuse_state_88xx(adapter, HALMAC_CMD_CNSTR_H2C_SENT) !=
+ HALMAC_RET_SUCCESS)
+ return HALMAC_RET_ERROR_STATE;
+
+ if (cfg == HALMAC_EFUSE_R_AUTO) {
+ h2c_init = HALMAC_REG_R32(REG_H2C_PKT_READADDR);
+ if (adapter->halmac_state.dlfw_state == HALMAC_DLFW_NONE ||
+ h2c_init == 0)
+ status = dump_efuse_drv_88xx(adapter);
+ else
+ status = dump_efuse_fw_88xx(adapter);
+ } else if (cfg == HALMAC_EFUSE_R_FW) {
+ status = dump_efuse_fw_88xx(adapter);
+ } else {
+ status = dump_efuse_drv_88xx(adapter);
+ }
+
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]dump efsue drv/fw\n");
+ return status;
+ }
+
+ return status;
+}
+
+enum halmac_ret_status
+cnv_efuse_state_88xx(struct halmac_adapter *adapter,
+ enum halmac_cmd_construct_state dest_state)
+{
+ struct halmac_efuse_state *state = &adapter->halmac_state.efuse_state;
+
+ if (state->cmd_cnstr_state != HALMAC_CMD_CNSTR_IDLE &&
+ state->cmd_cnstr_state != HALMAC_CMD_CNSTR_BUSY &&
+ state->cmd_cnstr_state != HALMAC_CMD_CNSTR_H2C_SENT)
+ return HALMAC_RET_ERROR_STATE;
+
+ if (state->cmd_cnstr_state == dest_state)
+ return HALMAC_RET_ERROR_STATE;
+
+ if (dest_state == HALMAC_CMD_CNSTR_BUSY) {
+ if (state->cmd_cnstr_state == HALMAC_CMD_CNSTR_H2C_SENT)
+ return HALMAC_RET_ERROR_STATE;
+ } else if (dest_state == HALMAC_CMD_CNSTR_H2C_SENT) {
+ if (state->cmd_cnstr_state == HALMAC_CMD_CNSTR_IDLE)
+ return HALMAC_RET_ERROR_STATE;
+ }
+
+ state->cmd_cnstr_state = dest_state;
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+read_hw_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
+ u8 *map)
+{
+ u8 enable;
+ u32 value32;
+ u32 addr;
+ u32 tmp32;
+ u32 cnt;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ /* Read efuse no need 2.5V LDO */
+ enable = _FALSE;
+ status = api->halmac_set_hw_value(adapter, HALMAC_HW_LDO25_EN, &enable);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]dis ldo25\n");
+ return status;
+ }
+ value32 = HALMAC_REG_R32(REG_EFUSE_CTRL);
+
+ for (addr = offset; addr < offset + size; addr++) {
+ value32 &= ~(BIT_MASK_EF_DATA | BITS_EF_ADDR);
+ value32 |= ((addr & BIT_MASK_EF_ADDR) << BIT_SHIFT_EF_ADDR);
+ HALMAC_REG_W32(REG_EFUSE_CTRL, value32 & (~BIT_EF_FLAG));
+
+ cnt = 1000000;
+ do {
+ PLTFM_DELAY_US(1);
+ tmp32 = HALMAC_REG_R32(REG_EFUSE_CTRL);
+ cnt--;
+ if (cnt == 0) {
+ PLTFM_MSG_ERR("[ERR]read\n");
+ return HALMAC_RET_EFUSE_R_FAIL;
+ }
+ } while ((tmp32 & BIT_EF_FLAG) == 0);
+
+ *(map + addr - offset) = (u8)(tmp32 & BIT_MASK_EF_DATA);
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+write_hw_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value)
+{
+ const u8 unlock_code = 0x69;
+ u8 value_read = 0, enable;
+ u32 value32;
+ u32 tmp32;
+ u32 cnt;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ PLTFM_MUTEX_LOCK(&adapter->efuse_mutex);
+ adapter->efuse_map_valid = _FALSE;
+ PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex);
+
+ HALMAC_REG_W8(REG_PMC_DBG_CTRL2 + 3, unlock_code);
+
+ /* Enable 2.5V LDO */
+ enable = _TRUE;
+ status = api->halmac_set_hw_value(adapter, HALMAC_HW_LDO25_EN, &enable);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]en ldo25\n");
+ return status;
+ }
+
+ value32 = HALMAC_REG_R32(REG_EFUSE_CTRL);
+ value32 &= ~(BIT_MASK_EF_DATA | BITS_EF_ADDR);
+ value32 = value32 | ((offset & BIT_MASK_EF_ADDR) << BIT_SHIFT_EF_ADDR) |
+ (value & BIT_MASK_EF_DATA);
+ HALMAC_REG_W32(REG_EFUSE_CTRL, value32 | BIT_EF_FLAG);
+
+ cnt = 1000000;
+ do {
+ PLTFM_DELAY_US(1);
+ tmp32 = HALMAC_REG_R32(REG_EFUSE_CTRL);
+ cnt--;
+ if (cnt == 0) {
+ PLTFM_MSG_ERR("[ERR]write!!\n");
+ return HALMAC_RET_EFUSE_W_FAIL;
+ }
+ } while (BIT_EF_FLAG == (tmp32 & BIT_EF_FLAG));
+
+ HALMAC_REG_W8(REG_PMC_DBG_CTRL2 + 3, 0x00);
+
+ /* Disable 2.5V LDO */
+ enable = _FALSE;
+ status = api->halmac_set_hw_value(adapter, HALMAC_HW_LDO25_EN, &enable);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]dis ldo25\n");
+ return status;
+ }
+
+ if (adapter->efuse_auto_check_en == 1) {
+ if (read_hw_efuse_88xx(adapter, offset, 1, &value_read) !=
+ HALMAC_RET_SUCCESS)
+ return HALMAC_RET_EFUSE_R_FAIL;
+ if (value_read != value) {
+ PLTFM_MSG_ERR("[ERR]efuse compare\n");
+ return HALMAC_RET_EFUSE_W_FAIL;
+ }
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+eeprom_parser_88xx(struct halmac_adapter *adapter, u8 *phy_map, u8 *log_map)
+{
+ u8 i;
+ u8 value8;
+ u8 blk_idx;
+ u8 word_en;
+ u8 valid;
+ u8 hdr;
+ u8 hdr2 = 0;
+ u32 eeprom_idx;
+ u32 efuse_idx = 0;
+ struct halmac_hw_cfg_info *hw_info = &adapter->hw_cfg_info;
+
+ PLTFM_MEMSET(log_map, 0xFF, hw_info->eeprom_size);
+
+ do {
+ value8 = *(phy_map + efuse_idx);
+ hdr = value8;
+
+ if ((hdr & 0x1f) == 0x0f) {
+ efuse_idx++;
+ value8 = *(phy_map + efuse_idx);
+ hdr2 = value8;
+ if (hdr2 == 0xff)
+ break;
+ blk_idx = ((hdr2 & 0xF0) >> 1) | ((hdr >> 5) & 0x07);
+ word_en = hdr2 & 0x0F;
+ } else {
+ blk_idx = (hdr & 0xF0) >> 4;
+ word_en = hdr & 0x0F;
+ }
+
+ if (hdr == 0xff)
+ break;
+
+ efuse_idx++;
+
+ if (efuse_idx >= hw_info->efuse_size - PROTECT_EFUSE_SIZE - 1)
+ return HALMAC_RET_EEPROM_PARSING_FAIL;
+
+ for (i = 0; i < 4; i++) {
+ valid = (u8)((~(word_en >> i)) & BIT(0));
+ if (valid == 1) {
+ eeprom_idx = (blk_idx << 3) + (i << 1);
+
+ if ((eeprom_idx + 1) > hw_info->eeprom_size) {
+ PLTFM_MSG_ERR("[ERR]efuse idx:0x%X\n",
+ efuse_idx - 1);
+
+ PLTFM_MSG_ERR("[ERR]read hdr:0x%X\n",
+ hdr);
+
+ PLTFM_MSG_ERR("[ERR]rad hdr2:0x%X\n",
+ hdr2);
+
+ return HALMAC_RET_EEPROM_PARSING_FAIL;
+ }
+
+ value8 = *(phy_map + efuse_idx);
+ *(log_map + eeprom_idx) = value8;
+
+ eeprom_idx++;
+ efuse_idx++;
+
+ if (efuse_idx > hw_info->efuse_size -
+ PROTECT_EFUSE_SIZE - 1)
+ return HALMAC_RET_EEPROM_PARSING_FAIL;
+
+ value8 = *(phy_map + efuse_idx);
+ *(log_map + eeprom_idx) = value8;
+
+ efuse_idx++;
+
+ if (efuse_idx > hw_info->efuse_size -
+ PROTECT_EFUSE_SIZE)
+ return HALMAC_RET_EEPROM_PARSING_FAIL;
+ }
+ }
+ } while (1);
+
+ adapter->efuse_end = efuse_idx;
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+read_log_efuse_map_88xx(struct halmac_adapter *adapter, u8 *map)
+{
+ u8 *local_map = NULL;
+ u32 efuse_size;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ if (adapter->efuse_map_valid == _FALSE) {
+ efuse_size = adapter->hw_cfg_info.efuse_size;
+
+ local_map = (u8 *)PLTFM_MALLOC(efuse_size);
+ if (!local_map) {
+ PLTFM_MSG_ERR("[ERR]local map\n");
+ return HALMAC_RET_MALLOC_FAIL;
+ }
+
+ status = read_efuse_88xx(adapter, 0, efuse_size, local_map);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]read efuse\n");
+ PLTFM_FREE(local_map, efuse_size);
+ return status;
+ }
+
+ if (!adapter->efuse_map) {
+ adapter->efuse_map = (u8 *)PLTFM_MALLOC(efuse_size);
+ if (!adapter->efuse_map) {
+ PLTFM_MSG_ERR("[ERR]malloc adapter map\n");
+ PLTFM_FREE(local_map, efuse_size);
+ return HALMAC_RET_MALLOC_FAIL;
+ }
+ }
+
+ PLTFM_MUTEX_LOCK(&adapter->efuse_mutex);
+ PLTFM_MEMCPY(adapter->efuse_map, local_map, efuse_size);
+ adapter->efuse_map_valid = _TRUE;
+ PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex);
+
+ PLTFM_FREE(local_map, efuse_size);
+ }
+
+ if (eeprom_parser_88xx(adapter, adapter->efuse_map, map) !=
+ HALMAC_RET_SUCCESS)
+ return HALMAC_RET_EEPROM_PARSING_FAIL;
+
+ return status;
+}
+
+static enum halmac_ret_status
+proc_pg_efuse_by_map_88xx(struct halmac_adapter *adapter,
+ struct halmac_pg_efuse_info *info,
+ enum halmac_efuse_read_cfg cfg)
+{
+ u8 *updated_mask = NULL;
+ u32 mask_size = adapter->hw_cfg_info.eeprom_size >> 4;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ updated_mask = (u8 *)PLTFM_MALLOC(mask_size);
+ if (!updated_mask) {
+ PLTFM_MSG_ERR("[ERR]malloc updated mask\n");
+ return HALMAC_RET_MALLOC_FAIL;
+ }
+ PLTFM_MEMSET(updated_mask, 0x00, mask_size);
+
+ status = update_eeprom_mask_88xx(adapter, info, updated_mask);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]update eeprom mask\n");
+ PLTFM_FREE(updated_mask, mask_size);
+ return status;
+ }
+
+ status = check_efuse_enough_88xx(adapter, info, updated_mask);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]chk efuse enough\n");
+ PLTFM_FREE(updated_mask, mask_size);
+ return status;
+ }
+
+ status = program_efuse_88xx(adapter, info, updated_mask);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]pg efuse\n");
+ PLTFM_FREE(updated_mask, mask_size);
+ return status;
+ }
+
+ PLTFM_FREE(updated_mask, mask_size);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+dump_efuse_drv_88xx(struct halmac_adapter *adapter)
+{
+ u8 *map = NULL;
+ u32 efuse_size = adapter->hw_cfg_info.efuse_size;
+
+ if (!adapter->efuse_map) {
+ adapter->efuse_map = (u8 *)PLTFM_MALLOC(efuse_size);
+ if (!adapter->efuse_map) {
+ PLTFM_MSG_ERR("[ERR]malloc adapter map!!\n");
+ reset_ofld_feature_88xx(adapter,
+ FEATURE_DUMP_PHY_EFUSE);
+ return HALMAC_RET_MALLOC_FAIL;
+ }
+ }
+
+ if (adapter->efuse_map_valid == _FALSE) {
+ map = (u8 *)PLTFM_MALLOC(efuse_size);
+ if (!map) {
+ PLTFM_MSG_ERR("[ERR]malloc map\n");
+ return HALMAC_RET_MALLOC_FAIL;
+ }
+
+ if (read_hw_efuse_88xx(adapter, 0, efuse_size, map) !=
+ HALMAC_RET_SUCCESS) {
+ PLTFM_FREE(map, efuse_size);
+ return HALMAC_RET_EFUSE_R_FAIL;
+ }
+
+ PLTFM_MUTEX_LOCK(&adapter->efuse_mutex);
+ PLTFM_MEMCPY(adapter->efuse_map, map, efuse_size);
+ adapter->efuse_map_valid = _TRUE;
+ PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex);
+
+ PLTFM_FREE(map, efuse_size);
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+dump_efuse_fw_88xx(struct halmac_adapter *adapter)
+{
+ u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };
+ u16 seq_num = 0;
+ u32 efuse_size = adapter->hw_cfg_info.efuse_size;
+ struct halmac_h2c_header_info hdr_info;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ hdr_info.sub_cmd_id = SUB_CMD_ID_DUMP_PHYSICAL_EFUSE;
+ hdr_info.content_size = 0;
+ hdr_info.ack = _TRUE;
+ set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+
+ adapter->halmac_state.efuse_state.seq_num = seq_num;
+
+ if (!adapter->efuse_map) {
+ adapter->efuse_map = (u8 *)PLTFM_MALLOC(efuse_size);
+ if (!adapter->efuse_map) {
+ PLTFM_MSG_ERR("[ERR]malloc adapter map\n");
+ reset_ofld_feature_88xx(adapter,
+ FEATURE_DUMP_PHY_EFUSE);
+ return HALMAC_RET_MALLOC_FAIL;
+ }
+ }
+
+ if (adapter->efuse_map_valid == _FALSE) {
+ status = send_h2c_pkt_88xx(adapter, h2c_buf);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]send h2c pkt\n");
+ reset_ofld_feature_88xx(adapter,
+ FEATURE_DUMP_PHY_EFUSE);
+ return status;
+ }
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+proc_write_log_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value)
+{
+ u8 byte1;
+ u8 byte2;
+ u8 blk;
+ u8 blk_idx;
+ u8 hdr;
+ u8 hdr2;
+ u8 *map = NULL;
+ u32 eeprom_size = adapter->hw_cfg_info.eeprom_size;
+ u32 end;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ map = (u8 *)PLTFM_MALLOC(eeprom_size);
+ if (!map) {
+ PLTFM_MSG_ERR("[ERR]malloc map\n");
+ return HALMAC_RET_MALLOC_FAIL;
+ }
+ PLTFM_MEMSET(map, 0xFF, eeprom_size);
+
+ status = read_log_efuse_map_88xx(adapter, map);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]read logical efuse\n");
+ PLTFM_FREE(map, eeprom_size);
+ return status;
+ }
+
+ if (*(map + offset) != value) {
+ end = adapter->efuse_end;
+ blk = (u8)(offset >> 3);
+ blk_idx = (u8)((offset & (8 - 1)) >> 1);
+
+ if (offset > 0x7f) {
+ hdr = (((blk & 0x07) << 5) & 0xE0) | 0x0F;
+ hdr2 = (u8)(((blk & 0x78) << 1) +
+ ((0x1 << blk_idx) ^ 0x0F));
+ } else {
+ hdr = (u8)((blk << 4) + ((0x01 << blk_idx) ^ 0x0F));
+ }
+
+ if ((offset & 1) == 0) {
+ byte1 = value;
+ byte2 = *(map + offset + 1);
+ } else {
+ byte1 = *(map + offset - 1);
+ byte2 = value;
+ }
+
+ if (offset > 0x7f) {
+ if (adapter->hw_cfg_info.efuse_size <=
+ 4 + PROTECT_EFUSE_SIZE + end) {
+ PLTFM_FREE(map, eeprom_size);
+ return HALMAC_RET_EFUSE_NOT_ENOUGH;
+ }
+
+ status = write_hw_efuse_88xx(adapter, end, hdr);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_FREE(map, eeprom_size);
+ return status;
+ }
+
+ status = write_hw_efuse_88xx(adapter, end + 1, hdr2);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_FREE(map, eeprom_size);
+ return status;
+ }
+
+ status = write_hw_efuse_88xx(adapter, end + 2, byte1);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_FREE(map, eeprom_size);
+ return status;
+ }
+
+ status = write_hw_efuse_88xx(adapter, end + 3, byte2);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_FREE(map, eeprom_size);
+ return status;
+ }
+ } else {
+ if (adapter->hw_cfg_info.efuse_size <=
+ 3 + PROTECT_EFUSE_SIZE + end) {
+ PLTFM_FREE(map, eeprom_size);
+ return HALMAC_RET_EFUSE_NOT_ENOUGH;
+ }
+
+ status = write_hw_efuse_88xx(adapter, end, hdr);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_FREE(map, eeprom_size);
+ return status;
+ }
+
+ status = write_hw_efuse_88xx(adapter, end + 1, byte1);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_FREE(map, eeprom_size);
+ return status;
+ }
+
+ status = write_hw_efuse_88xx(adapter, end + 2, byte2);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_FREE(map, eeprom_size);
+ return status;
+ }
+ }
+ }
+
+ PLTFM_FREE(map, eeprom_size);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+read_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u32 size, u8 *map)
+{
+ if (!map) {
+ PLTFM_MSG_ERR("[ERR]malloc map\n");
+ return HALMAC_RET_NULL_POINTER;
+ }
+
+ if (adapter->efuse_map_valid == _TRUE) {
+ PLTFM_MEMCPY(map, adapter->efuse_map + offset, size);
+ } else {
+ if (read_hw_efuse_88xx(adapter, offset, size, map) !=
+ HALMAC_RET_SUCCESS)
+ return HALMAC_RET_EFUSE_R_FAIL;
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+update_eeprom_mask_88xx(struct halmac_adapter *adapter,
+ struct halmac_pg_efuse_info *info, u8 *updated_mask)
+{
+ u8 *map = NULL;
+ u8 clr_bit = 0;
+ u32 eeprom_size = adapter->hw_cfg_info.eeprom_size;
+ u8 *map_pg;
+ u8 *efuse_mask;
+ u16 i;
+ u16 j;
+ u16 map_offset;
+ u16 mask_offset;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ map = (u8 *)PLTFM_MALLOC(eeprom_size);
+ if (!map) {
+ PLTFM_MSG_ERR("[ERR]malloc map\n");
+ return HALMAC_RET_MALLOC_FAIL;
+ }
+ PLTFM_MEMSET(map, 0xFF, eeprom_size);
+
+ PLTFM_MEMSET(updated_mask, 0x00, info->efuse_mask_size);
+
+ status = read_log_efuse_map_88xx(adapter, map);
+
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_FREE(map, eeprom_size);
+ return status;
+ }
+
+ map_pg = info->efuse_map;
+ efuse_mask = info->efuse_mask;
+
+ for (i = 0; i < info->efuse_mask_size; i++)
+ *(updated_mask + i) = *(efuse_mask + i);
+
+ for (i = 0; i < info->efuse_map_size; i += 16) {
+ for (j = 0; j < 16; j += 2) {
+ map_offset = i + j;
+ mask_offset = i >> 4;
+ if (*(u16 *)(map_pg + map_offset) ==
+ *(u16 *)(map + map_offset)) {
+ switch (j) {
+ case 0:
+ clr_bit = BIT(4);
+ break;
+ case 2:
+ clr_bit = BIT(5);
+ break;
+ case 4:
+ clr_bit = BIT(6);
+ break;
+ case 6:
+ clr_bit = BIT(7);
+ break;
+ case 8:
+ clr_bit = BIT(0);
+ break;
+ case 10:
+ clr_bit = BIT(1);
+ break;
+ case 12:
+ clr_bit = BIT(2);
+ break;
+ case 14:
+ clr_bit = BIT(3);
+ break;
+ default:
+ break;
+ }
+ *(updated_mask + mask_offset) &= ~clr_bit;
+ }
+ }
+ }
+
+ PLTFM_FREE(map, eeprom_size);
+
+ return status;
+}
+
+static enum halmac_ret_status
+check_efuse_enough_88xx(struct halmac_adapter *adapter,
+ struct halmac_pg_efuse_info *info, u8 *updated_mask)
+{
+ u8 pre_word_en;
+ u16 i;
+ u16 j;
+ u32 eeprom_offset;
+ u32 pg_num = 0;
+
+ for (i = 0; i < info->efuse_map_size; i = i + 8) {
+ eeprom_offset = i;
+
+ if ((eeprom_offset & 7) > 0)
+ pre_word_en = (*(updated_mask + (i >> 4)) & 0x0F);
+ else
+ pre_word_en = (*(updated_mask + (i >> 4)) >> 4);
+
+ if (pre_word_en > 0) {
+ if (eeprom_offset > 0x7f) {
+ pg_num += 2;
+ for (j = 0; j < 4; j++) {
+ if (((pre_word_en >> j) & 0x1) > 0)
+ pg_num += 2;
+ }
+ } else {
+ pg_num++;
+ for (j = 0; j < 4; j++) {
+ if (((pre_word_en >> j) & 0x1) > 0)
+ pg_num += 2;
+ }
+ }
+ }
+ }
+
+ if (adapter->hw_cfg_info.efuse_size <=
+ (pg_num + PROTECT_EFUSE_SIZE + adapter->efuse_end))
+ return HALMAC_RET_EFUSE_NOT_ENOUGH;
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+pg_extend_efuse_88xx(struct halmac_adapter *adapter,
+ struct halmac_pg_efuse_info *info, u8 word_en,
+ u8 pre_word_en, u32 eeprom_offset)
+{
+ u8 blk;
+ u8 hdr;
+ u8 hdr2;
+ u16 i;
+ u32 efuse_end;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ efuse_end = adapter->efuse_end;
+
+ blk = (u8)(eeprom_offset >> 3);
+ hdr = (((blk & 0x07) << 5) & 0xE0) | 0x0F;
+ hdr2 = (u8)(((blk & 0x78) << 1) + word_en);
+
+ status = write_hw_efuse_88xx(adapter, efuse_end, hdr);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]write efuse\n");
+ return status;
+ }
+
+ status = write_hw_efuse_88xx(adapter, efuse_end + 1, hdr2);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]write efuse(+1)\n");
+ return status;
+ }
+
+ efuse_end = efuse_end + 2;
+ for (i = 0; i < 4; i++) {
+ if (((pre_word_en >> i) & 0x1) > 0) {
+ status = write_hw_efuse_88xx(adapter, efuse_end,
+ *(info->efuse_map +
+ eeprom_offset +
+ (i << 1)));
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]write efuse(<<1)\n");
+ return status;
+ }
+
+ status = write_hw_efuse_88xx(adapter, efuse_end + 1,
+ *(info->efuse_map +
+ eeprom_offset + (i << 1)
+ + 1));
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]write efuse(<<1)+1\n");
+ return status;
+ }
+ efuse_end = efuse_end + 2;
+ }
+ }
+ adapter->efuse_end = efuse_end;
+ return status;
+}
+
+static enum halmac_ret_status
+proc_pg_efuse_88xx(struct halmac_adapter *adapter,
+ struct halmac_pg_efuse_info *info, u8 word_en,
+ u8 pre_word_en, u32 eeprom_offset)
+{
+ u8 blk;
+ u8 hdr;
+ u16 i;
+ u32 efuse_end;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ efuse_end = adapter->efuse_end;
+
+ blk = (u8)(eeprom_offset >> 3);
+ hdr = (u8)((blk << 4) + word_en);
+
+ status = write_hw_efuse_88xx(adapter, efuse_end, hdr);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]write efuse\n");
+ return status;
+ }
+ efuse_end = efuse_end + 1;
+ for (i = 0; i < 4; i++) {
+ if (((pre_word_en >> i) & 0x1) > 0) {
+ status = write_hw_efuse_88xx(adapter, efuse_end,
+ *(info->efuse_map +
+ eeprom_offset +
+ (i << 1)));
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]write efuse(<<1)\n");
+ return status;
+ }
+ status = write_hw_efuse_88xx(adapter, efuse_end + 1,
+ *(info->efuse_map +
+ eeprom_offset + (i << 1)
+ + 1));
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]write efuse(<<1)+1\n");
+ return status;
+ }
+ efuse_end = efuse_end + 2;
+ }
+ }
+ adapter->efuse_end = efuse_end;
+ return status;
+}
+
+static enum halmac_ret_status
+program_efuse_88xx(struct halmac_adapter *adapter,
+ struct halmac_pg_efuse_info *info, u8 *updated_mask)
+{
+ u8 pre_word_en;
+ u8 word_en;
+ u16 i;
+ u32 eeprom_offset;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ for (i = 0; i < info->efuse_map_size; i = i + 8) {
+ eeprom_offset = i;
+
+ if (((eeprom_offset >> 3) & 1) > 0) {
+ pre_word_en = (*(updated_mask + (i >> 4)) & 0x0F);
+ word_en = pre_word_en ^ 0x0F;
+ } else {
+ pre_word_en = (*(updated_mask + (i >> 4)) >> 4);
+ word_en = pre_word_en ^ 0x0F;
+ }
+
+ if (pre_word_en > 0) {
+ if (eeprom_offset > 0x7f) {
+ status = pg_extend_efuse_88xx(adapter, info,
+ word_en,
+ pre_word_en,
+ eeprom_offset);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]extend efuse\n");
+ return status;
+ }
+ } else {
+ status = proc_pg_efuse_88xx(adapter, info,
+ word_en,
+ pre_word_en,
+ eeprom_offset);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]extend efuse");
+ return status;
+ }
+ }
+ }
+ }
+
+ return status;
+}
+
+static void
+mask_eeprom_88xx(struct halmac_adapter *adapter,
+ struct halmac_pg_efuse_info *info)
+{
+ u8 pre_word_en;
+ u8 *updated_mask;
+ u8 *efuse_map;
+ u16 i;
+ u16 j;
+ u32 offset;
+
+ updated_mask = info->efuse_mask;
+ efuse_map = info->efuse_map;
+
+ for (i = 0; i < info->efuse_map_size; i = i + 8) {
+ offset = i;
+
+ if (((offset >> 3) & 1) > 0)
+ pre_word_en = (*(updated_mask + (i >> 4)) & 0x0F);
+ else
+ pre_word_en = (*(updated_mask + (i >> 4)) >> 4);
+
+ for (j = 0; j < 4; j++) {
+ if (((pre_word_en >> j) & 0x1) == 0) {
+ *(efuse_map + offset + (j << 1)) = 0xFF;
+ *(efuse_map + offset + (j << 1) + 1) = 0xFF;
+ }
+ }
+ }
+}
+
+enum halmac_ret_status
+get_efuse_data_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+ u8 seg_id;
+ u8 seg_size;
+ u8 seq_num;
+ u8 fw_rc;
+ u8 *map = NULL;
+ u32 eeprom_size = adapter->hw_cfg_info.eeprom_size;
+ struct halmac_efuse_state *state = &adapter->halmac_state.efuse_state;
+ enum halmac_cmd_process_status proc_status;
+
+ seq_num = (u8)EFUSE_DATA_GET_H2C_SEQ(buf);
+ PLTFM_MSG_TRACE("[TRACE]Seq num : h2c->%d c2h->%d\n",
+ state->seq_num, seq_num);
+ if (seq_num != state->seq_num) {
+ PLTFM_MSG_ERR("[ERR]Seq num mismatch : h2c->%d c2h->%d\n",
+ state->seq_num, seq_num);
+ return HALMAC_RET_SUCCESS;
+ }
+
+ if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) {
+ PLTFM_MSG_ERR("[ERR]not cmd sending\n");
+ return HALMAC_RET_SUCCESS;
+ }
+
+ seg_id = (u8)EFUSE_DATA_GET_SEGMENT_ID(buf);
+ seg_size = (u8)EFUSE_DATA_GET_SEGMENT_SIZE(buf);
+ if (seg_id == 0)
+ adapter->efuse_seg_size = seg_size;
+
+ map = (u8 *)PLTFM_MALLOC(eeprom_size);
+ if (!map) {
+ PLTFM_MSG_ERR("[ERR]malloc map\n");
+ return HALMAC_RET_MALLOC_FAIL;
+ }
+ PLTFM_MEMSET(map, 0xFF, eeprom_size);
+
+ PLTFM_MUTEX_LOCK(&adapter->efuse_mutex);
+ PLTFM_MEMCPY(adapter->efuse_map + seg_id * adapter->efuse_seg_size,
+ buf + C2H_DATA_OFFSET_88XX, seg_size);
+ PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex);
+
+ if (EFUSE_DATA_GET_END_SEGMENT(buf) == _FALSE) {
+ PLTFM_FREE(map, eeprom_size);
+ return HALMAC_RET_SUCCESS;
+ }
+
+ fw_rc = state->fw_rc;
+
+ if ((enum halmac_h2c_return_code)fw_rc == HALMAC_H2C_RETURN_SUCCESS) {
+ proc_status = HALMAC_CMD_PROCESS_DONE;
+ state->proc_status = proc_status;
+
+ PLTFM_MUTEX_LOCK(&adapter->efuse_mutex);
+ adapter->efuse_map_valid = _TRUE;
+ PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex);
+
+ if (adapter->evnt.phy_efuse_map == 1) {
+ PLTFM_EVENT_SIG(FEATURE_DUMP_PHY_EFUSE,
+ proc_status, adapter->efuse_map,
+ adapter->hw_cfg_info.efuse_size);
+ adapter->evnt.phy_efuse_map = 0;
+ }
+
+ if (adapter->evnt.log_efuse_map == 1) {
+ if (eeprom_parser_88xx(adapter, adapter->efuse_map,
+ map) != HALMAC_RET_SUCCESS) {
+ PLTFM_FREE(map, eeprom_size);
+ return HALMAC_RET_EEPROM_PARSING_FAIL;
+ }
+ PLTFM_EVENT_SIG(FEATURE_DUMP_LOG_EFUSE, proc_status,
+ map, eeprom_size);
+ adapter->evnt.log_efuse_map = 0;
+ }
+ } else {
+ proc_status = HALMAC_CMD_PROCESS_ERROR;
+ state->proc_status = proc_status;
+
+ if (adapter->evnt.phy_efuse_map == 1) {
+ PLTFM_EVENT_SIG(FEATURE_DUMP_PHY_EFUSE, proc_status,
+ &state->fw_rc, 1);
+ adapter->evnt.phy_efuse_map = 0;
+ }
+
+ if (adapter->evnt.log_efuse_map == 1) {
+ PLTFM_EVENT_SIG(FEATURE_DUMP_LOG_EFUSE, proc_status,
+ &state->fw_rc, 1);
+ adapter->evnt.log_efuse_map = 0;
+ }
+ }
+
+ PLTFM_FREE(map, eeprom_size);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+get_dump_phy_efuse_status_88xx(struct halmac_adapter *adapter,
+ enum halmac_cmd_process_status *proc_status,
+ u8 *data, u32 *size)
+{
+ u8 *map = NULL;
+ u32 efuse_size = adapter->hw_cfg_info.efuse_size;
+ struct halmac_efuse_state *state = &adapter->halmac_state.efuse_state;
+
+ *proc_status = state->proc_status;
+
+ if (!data)
+ return HALMAC_RET_NULL_POINTER;
+
+ if (!size)
+ return HALMAC_RET_NULL_POINTER;
+
+ if (*proc_status == HALMAC_CMD_PROCESS_DONE) {
+ if (*size < efuse_size) {
+ *size = efuse_size;
+ return HALMAC_RET_BUFFER_TOO_SMALL;
+ }
+
+ *size = efuse_size;
+
+ map = (u8 *)PLTFM_MALLOC(efuse_size);
+ if (!map) {
+ PLTFM_MSG_ERR("[ERR]malloc map\n");
+ return HALMAC_RET_MALLOC_FAIL;
+ }
+ PLTFM_MEMSET(map, 0xFF, efuse_size);
+ PLTFM_MUTEX_LOCK(&adapter->efuse_mutex);
+ PLTFM_MEMCPY(map, adapter->efuse_map,
+ efuse_size - PROTECT_EFUSE_SIZE);
+ PLTFM_MEMCPY(map + efuse_size - PROTECT_EFUSE_SIZE +
+ RSVD_CS_EFUSE_SIZE,
+ adapter->efuse_map + efuse_size -
+ PROTECT_EFUSE_SIZE + RSVD_CS_EFUSE_SIZE,
+ PROTECT_EFUSE_SIZE - RSVD_EFUSE_SIZE -
+ RSVD_CS_EFUSE_SIZE);
+ PLTFM_MUTEX_UNLOCK(&adapter->efuse_mutex);
+
+ PLTFM_MEMCPY(data, map, *size);
+
+ PLTFM_FREE(map, efuse_size);
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+get_dump_log_efuse_status_88xx(struct halmac_adapter *adapter,
+ enum halmac_cmd_process_status *proc_status,
+ u8 *data, u32 *size)
+{
+ u8 *map = NULL;
+ u32 eeprom_size = adapter->hw_cfg_info.eeprom_size;
+ struct halmac_efuse_state *state = &adapter->halmac_state.efuse_state;
+
+ *proc_status = state->proc_status;
+
+ if (!data)
+ return HALMAC_RET_NULL_POINTER;
+
+ if (!size)
+ return HALMAC_RET_NULL_POINTER;
+
+ if (*proc_status == HALMAC_CMD_PROCESS_DONE) {
+ if (*size < eeprom_size) {
+ *size = eeprom_size;
+ return HALMAC_RET_BUFFER_TOO_SMALL;
+ }
+
+ *size = eeprom_size;
+
+ map = (u8 *)PLTFM_MALLOC(eeprom_size);
+ if (!map) {
+ PLTFM_MSG_ERR("[ERR]malloc map\n");
+ return HALMAC_RET_MALLOC_FAIL;
+ }
+ PLTFM_MEMSET(map, 0xFF, eeprom_size);
+
+ if (eeprom_parser_88xx(adapter, adapter->efuse_map, map) !=
+ HALMAC_RET_SUCCESS) {
+ PLTFM_FREE(map, eeprom_size);
+ return HALMAC_RET_EEPROM_PARSING_FAIL;
+ }
+
+ PLTFM_MEMCPY(data, map, *size);
+
+ PLTFM_FREE(map, eeprom_size);
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+get_h2c_ack_phy_efuse_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+ u8 seq_num = 0;
+ u8 fw_rc;
+ struct halmac_efuse_state *state = &adapter->halmac_state.efuse_state;
+
+ seq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf);
+ PLTFM_MSG_TRACE("[TRACE]Seq num : h2c->%d c2h->%d\n",
+ state->seq_num, seq_num);
+ if (seq_num != state->seq_num) {
+ PLTFM_MSG_ERR("[ERR]Seq num mismatch : h2c->%d c2h->%d\n",
+ state->seq_num, seq_num);
+ return HALMAC_RET_SUCCESS;
+ }
+
+ if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) {
+ PLTFM_MSG_ERR("[ERR]not cmd sending\n");
+ return HALMAC_RET_SUCCESS;
+ }
+
+ fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf);
+ state->fw_rc = fw_rc;
+
+ return HALMAC_RET_SUCCESS;
+}
+
+u32
+get_rsvd_efuse_size_88xx(struct halmac_adapter *adapter)
+{
+ return PROTECT_EFUSE_SIZE;
+}
+
+#endif /* HALMAC_88XX_SUPPORT */
diff --git a/hal/halmac/halmac_88xx/halmac_efuse_88xx.h b/hal/halmac/halmac_88xx/halmac_efuse_88xx.h
new file mode 100644
index 0000000..5bf97fa
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_efuse_88xx.h
@@ -0,0 +1,105 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_EFUSE_88XX_H_
+#define _HALMAC_EFUSE_88XX_H_
+
+#include "../halmac_api.h"
+
+#if HALMAC_88XX_SUPPORT
+
+enum halmac_ret_status
+dump_efuse_map_88xx(struct halmac_adapter *adapter,
+ enum halmac_efuse_read_cfg cfg);
+
+enum halmac_ret_status
+dump_efuse_map_bt_88xx(struct halmac_adapter *adapter,
+ enum halmac_efuse_bank bank, u32 size, u8 *map);
+
+enum halmac_ret_status
+write_efuse_bt_88xx(struct halmac_adapter *adapter, u32 offset, u8 value,
+ enum halmac_efuse_bank bank);
+
+enum halmac_ret_status
+read_efuse_bt_88xx(struct halmac_adapter *adapter, u32 offset, u8 *value,
+ enum halmac_efuse_bank bank);
+
+enum halmac_ret_status
+cfg_efuse_auto_check_88xx(struct halmac_adapter *adapter, u8 enable);
+
+enum halmac_ret_status
+get_efuse_available_size_88xx(struct halmac_adapter *adapter, u32 *size);
+
+enum halmac_ret_status
+get_efuse_size_88xx(struct halmac_adapter *adapter, u32 *size);
+
+enum halmac_ret_status
+get_log_efuse_size_88xx(struct halmac_adapter *adapter, u32 *size);
+
+enum halmac_ret_status
+dump_log_efuse_map_88xx(struct halmac_adapter *adapter,
+ enum halmac_efuse_read_cfg cfg);
+
+enum halmac_ret_status
+read_logical_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 *value);
+
+enum halmac_ret_status
+write_log_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value);
+
+enum halmac_ret_status
+pg_efuse_by_map_88xx(struct halmac_adapter *adapter,
+ struct halmac_pg_efuse_info *info,
+ enum halmac_efuse_read_cfg cfg);
+
+enum halmac_ret_status
+mask_log_efuse_88xx(struct halmac_adapter *adapter,
+ struct halmac_pg_efuse_info *info);
+
+enum halmac_ret_status
+read_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u32 size, u8 *map);
+
+enum halmac_ret_status
+write_hw_efuse_88xx(struct halmac_adapter *adapter, u32 offset, u8 value);
+
+enum halmac_ret_status
+switch_efuse_bank_88xx(struct halmac_adapter *adapter,
+ enum halmac_efuse_bank bank);
+
+enum halmac_ret_status
+get_efuse_data_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+enum halmac_ret_status
+cnv_efuse_state_88xx(struct halmac_adapter *adapter,
+ enum halmac_cmd_construct_state dest_state);
+
+enum halmac_ret_status
+get_dump_phy_efuse_status_88xx(struct halmac_adapter *adapter,
+ enum halmac_cmd_process_status *proc_status,
+ u8 *data, u32 *size);
+
+enum halmac_ret_status
+get_dump_log_efuse_status_88xx(struct halmac_adapter *adapter,
+ enum halmac_cmd_process_status *proc_status,
+ u8 *data, u32 *size);
+
+enum halmac_ret_status
+get_h2c_ack_phy_efuse_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+u32
+get_rsvd_efuse_size_88xx(struct halmac_adapter *adapter);
+
+#endif /* HALMAC_88XX_SUPPORT */
+
+#endif/* _HALMAC_EFUSE_88XX_H_ */
diff --git a/hal/halmac/halmac_88xx/halmac_flash_88xx.c b/hal/halmac/halmac_88xx/halmac_flash_88xx.c
new file mode 100644
index 0000000..07b2e36
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_flash_88xx.c
@@ -0,0 +1,316 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_flash_88xx.h"
+#include "halmac_88xx_cfg.h"
+#include "halmac_common_88xx.h"
+
+#if HALMAC_88XX_SUPPORT
+
+/**
+ * download_flash_88xx() -download firmware to flash
+ * @adapter : the adapter of halmac
+ * @fw_bin : pointer to fw
+ * @size : fw size
+ * @rom_addr : flash start address where fw should be download
+ * Author : Pablo Chiu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+download_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,
+ u32 rom_addr)
+{
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+ enum halmac_ret_status rc;
+ struct halmac_h2c_header_info hdr_info;
+ u8 value8;
+ u8 restore[3];
+ u8 h2c_buf[H2C_PKT_SIZE_88XX] = {0};
+ u16 seq_num = 0;
+ u16 h2c_info_offset;
+ u32 pkt_size;
+ u32 mem_offset;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ value8 = HALMAC_REG_R8(REG_CR + 1);
+ restore[0] = value8;
+ value8 = (u8)(value8 | BIT(0));
+ HALMAC_REG_W8(REG_CR + 1, value8);
+
+ value8 = HALMAC_REG_R8(REG_BCN_CTRL);
+ restore[1] = value8;
+ value8 = (u8)((value8 & ~(BIT(3))) | BIT(4));
+ HALMAC_REG_W8(REG_BCN_CTRL, value8);
+
+ value8 = HALMAC_REG_R8(REG_FWHW_TXQ_CTRL + 2);
+ restore[2] = value8;
+ value8 = (u8)(value8 & ~(BIT(6)));
+ HALMAC_REG_W8(REG_FWHW_TXQ_CTRL + 2, value8);
+
+ /* Download FW to Flash flow */
+ h2c_info_offset = adapter->txff_alloc.rsvd_h2c_info_addr -
+ adapter->txff_alloc.rsvd_boundary;
+ mem_offset = 0;
+
+ while (size != 0) {
+ if (size >= (DL_FLASH_RSVDPG_SIZE - 48))
+ pkt_size = DL_FLASH_RSVDPG_SIZE - 48;
+ else
+ pkt_size = size;
+
+ rc = dl_rsvd_page_88xx(adapter,
+ adapter->txff_alloc.rsvd_h2c_info_addr,
+ fw_bin + mem_offset, pkt_size);
+ if (rc != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]dl rsvd pg!!\n");
+ return rc;
+ }
+
+ DOWNLOAD_FLASH_SET_SPI_CMD(h2c_buf, 0x02);
+ DOWNLOAD_FLASH_SET_LOCATION(h2c_buf, h2c_info_offset);
+ DOWNLOAD_FLASH_SET_SIZE(h2c_buf, pkt_size);
+ DOWNLOAD_FLASH_SET_START_ADDR(h2c_buf, rom_addr);
+
+ hdr_info.sub_cmd_id = SUB_CMD_ID_DOWNLOAD_FLASH;
+ hdr_info.content_size = 20;
+ hdr_info.ack = _TRUE;
+ set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+
+ rc = send_h2c_pkt_88xx(adapter, h2c_buf);
+
+ if (rc != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]send h2c!!\n");
+ return rc;
+ }
+
+ value8 = HALMAC_REG_R8(REG_MCUTST_I);
+ value8 |= BIT(0);
+ HALMAC_REG_W8(REG_MCUTST_I, value8);
+
+ rom_addr += pkt_size;
+ mem_offset += pkt_size;
+ size -= pkt_size;
+
+ while (((HALMAC_REG_R8(REG_MCUTST_I)) & BIT(0)) != 0)
+ PLTFM_DELAY_US(1000);
+
+ if (((HALMAC_REG_R8(REG_MCUTST_I)) & BIT(0)) != 0) {
+ PLTFM_MSG_ERR("[ERR]dl flash!!\n");
+ return HALMAC_RET_DLFW_FAIL;
+ }
+ }
+
+ HALMAC_REG_W8(REG_FWHW_TXQ_CTRL + 2, restore[2]);
+ HALMAC_REG_W8(REG_BCN_CTRL, restore[1]);
+ HALMAC_REG_W8(REG_CR + 1, restore[0]);
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * read_flash_88xx() -read data from flash
+ * @adapter : the adapter of halmac
+ * @addr : flash start address where fw should be read
+ * Author : Pablo Chiu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+read_flash_88xx(struct halmac_adapter *adapter, u32 addr)
+{
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+ enum halmac_ret_status status;
+ struct halmac_h2c_header_info hdr_info;
+ u8 value8;
+ u8 restore[3];
+ u8 h2c_buf[H2C_PKT_SIZE_88XX] = {0};
+ u16 seq_num = 0;
+ u16 h2c_info_addr = adapter->txff_alloc.rsvd_h2c_info_addr;
+ u16 rsvd_pg_addr = adapter->txff_alloc.rsvd_boundary;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ value8 = HALMAC_REG_R8(REG_CR + 1);
+ restore[0] = value8;
+ value8 = (u8)(value8 | BIT(0));
+ HALMAC_REG_W8(REG_CR + 1, value8);
+
+ value8 = HALMAC_REG_R8(REG_BCN_CTRL);
+ restore[1] = value8;
+ value8 = (u8)((value8 & ~(BIT(3))) | BIT(4));
+ HALMAC_REG_W8(REG_BCN_CTRL, value8);
+
+ value8 = HALMAC_REG_R8(REG_FWHW_TXQ_CTRL + 2);
+ restore[2] = value8;
+ value8 = (u8)(value8 & ~(BIT(6)));
+ HALMAC_REG_W8(REG_FWHW_TXQ_CTRL + 2, value8);
+
+ HALMAC_REG_W16(REG_FIFOPAGE_CTRL_2, h2c_info_addr);
+ value8 = HALMAC_REG_R8(REG_MCUTST_I);
+ value8 |= BIT(0);
+ HALMAC_REG_W8(REG_MCUTST_I, value8);
+
+ /* Construct H2C Content */
+ DOWNLOAD_FLASH_SET_SPI_CMD(h2c_buf, 0x03);
+ DOWNLOAD_FLASH_SET_LOCATION(h2c_buf, h2c_info_addr - rsvd_pg_addr);
+ DOWNLOAD_FLASH_SET_SIZE(h2c_buf, 4096);
+ DOWNLOAD_FLASH_SET_START_ADDR(h2c_buf, addr);
+
+ /* Fill in H2C Header */
+ hdr_info.sub_cmd_id = SUB_CMD_ID_DOWNLOAD_FLASH;
+ hdr_info.content_size = 16;
+ hdr_info.ack = _TRUE;
+ set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+
+ /* Send H2C Cmd Packet */
+ status = send_h2c_pkt_88xx(adapter, h2c_buf);
+
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]send h2c!!\n");
+ return status;
+ }
+
+ while (((HALMAC_REG_R8(REG_MCUTST_I)) & BIT(0)) != 0)
+ PLTFM_DELAY_US(1000);
+
+ HALMAC_REG_W16(REG_FIFOPAGE_CTRL_2, rsvd_pg_addr);
+ HALMAC_REG_W8(REG_FWHW_TXQ_CTRL + 2, restore[2]);
+ HALMAC_REG_W8(REG_BCN_CTRL, restore[1]);
+ HALMAC_REG_W8(REG_CR + 1, restore[0]);
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * erase_flash_88xx() -erase flash data
+ * @adapter : the adapter of halmac
+ * @erase_cmd : erase command
+ * @addr : flash start address where fw should be erased
+ * Author : Pablo Chiu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+erase_flash_88xx(struct halmac_adapter *adapter, u8 erase_cmd, u32 addr)
+{
+ enum halmac_ret_status status;
+ struct halmac_h2c_header_info hdr_info;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+ u8 value8;
+ u8 h2c_buf[H2C_PKT_SIZE_88XX] = {0};
+ u16 seq_num = 0;
+ u32 cnt;
+
+ /* Construct H2C Content */
+ DOWNLOAD_FLASH_SET_SPI_CMD(h2c_buf, erase_cmd);
+ DOWNLOAD_FLASH_SET_LOCATION(h2c_buf, 0);
+ DOWNLOAD_FLASH_SET_START_ADDR(h2c_buf, addr);
+ DOWNLOAD_FLASH_SET_SIZE(h2c_buf, 0);
+
+ value8 = HALMAC_REG_R8(REG_MCUTST_I);
+ value8 |= BIT(0);
+ HALMAC_REG_W8(REG_MCUTST_I, value8);
+
+ /* Fill in H2C Header */
+ hdr_info.sub_cmd_id = SUB_CMD_ID_DOWNLOAD_FLASH;
+ hdr_info.content_size = 16;
+ hdr_info.ack = _TRUE;
+ set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+
+ /* Send H2C Cmd Packet */
+ status = send_h2c_pkt_88xx(adapter, h2c_buf);
+
+ if (status != HALMAC_RET_SUCCESS)
+ PLTFM_MSG_ERR("[ERR]send h2c!!\n");
+
+ cnt = 5000;
+ while (((HALMAC_REG_R8(REG_MCUTST_I)) & BIT(0)) != 0 && cnt != 0) {
+ PLTFM_DELAY_US(1000);
+ cnt--;
+ }
+
+ if (cnt == 0)
+ return HALMAC_RET_FAIL;
+ else
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * check_flash_88xx() -check flash data
+ * @adapter : the adapter of halmac
+ * @fw_bin : pointer to fw
+ * @size : fw size
+ * @addr : flash start address where fw should be checked
+ * Author : Pablo Chiu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+check_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,
+ u32 addr)
+{
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+ u8 value8;
+ u16 i;
+ u16 residue;
+ u16 pg_addr;
+ u32 pkt_size;
+ u32 start_page;
+ u32 cnt;
+
+ pg_addr = adapter->txff_alloc.rsvd_h2c_info_addr;
+
+ while (size != 0) {
+ start_page = ((pg_addr << 7) >> 12) + 0x780;
+ residue = (pg_addr << 7) & (4096 - 1);
+
+ if (size >= DL_FLASH_RSVDPG_SIZE)
+ pkt_size = DL_FLASH_RSVDPG_SIZE;
+ else
+ pkt_size = size;
+
+ read_flash_88xx(adapter, addr);
+
+ cnt = 0;
+ while (cnt < pkt_size) {
+ HALMAC_REG_W16(REG_PKTBUF_DBG_CTRL, (u16)(start_page));
+ for (i = 0x8000 + residue; i <= 0x8FFF; i++) {
+ value8 = HALMAC_REG_R8(i);
+ if (*fw_bin != value8) {
+ PLTFM_MSG_ERR("[ERR]check flash!!\n");
+ return HALMAC_RET_FAIL;
+ }
+
+ fw_bin++;
+ cnt++;
+ if (cnt == pkt_size)
+ break;
+ }
+ residue = 0;
+ start_page++;
+ }
+ addr += pkt_size;
+ size -= pkt_size;
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+#endif /* HALMAC_88XX_SUPPORT */
diff --git a/hal/halmac/halmac_88xx/halmac_flash_88xx.h b/hal/halmac/halmac_88xx/halmac_flash_88xx.h
new file mode 100644
index 0000000..932ec15
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_flash_88xx.h
@@ -0,0 +1,39 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_FLASH_88XX_H_
+#define _HALMAC_FLASH_88XX_H_
+
+#include "../halmac_api.h"
+
+#if HALMAC_88XX_SUPPORT
+
+enum halmac_ret_status
+download_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,
+ u32 rom_addr);
+
+enum halmac_ret_status
+read_flash_88xx(struct halmac_adapter *adapter, u32 addr);
+
+enum halmac_ret_status
+erase_flash_88xx(struct halmac_adapter *adapter, u8 erase_cmd, u32 addr);
+
+enum halmac_ret_status
+check_flash_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,
+ u32 addr);
+
+#endif /* HALMAC_88XX_SUPPORT */
+
+#endif/* _HALMAC_FLASH_88XX_H_ */
diff --git a/hal/halmac/halmac_88xx/halmac_func_88xx.c b/hal/halmac/halmac_88xx/halmac_func_88xx.c
deleted file mode 100644
index 612cd2c..0000000
--- a/hal/halmac/halmac_88xx/halmac_func_88xx.c
+++ /dev/null
@@ -1,3423 +0,0 @@
-#include "halmac_88xx_cfg.h"
-
-HALMAC_RET_STATUS
-halmac_dump_efuse_fw_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-HALMAC_RET_STATUS
-halmac_dump_efuse_drv_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-HALMAC_RET_STATUS
-halmac_update_eeprom_mask_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- INOUT PHALMAC_PG_EFUSE_INFO pPg_efuse_info,
- OUT u8 *pEeprom_mask_updated
-);
-
-HALMAC_RET_STATUS
-halmac_check_efuse_enough_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_PG_EFUSE_INFO pPg_efuse_info,
- IN u8 *pEeprom_mask_updated
-);
-
-HALMAC_RET_STATUS
-halmac_program_efuse_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_PG_EFUSE_INFO pPg_efuse_info,
- IN u8 *pEeprom_mask_updated
-);
-
-HALMAC_RET_STATUS
-halmac_parse_c2h_debug_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pC2h_buf,
- IN u32 c2h_size
-);
-
-HALMAC_RET_STATUS
-halmac_parse_scan_status_rpt_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pC2h_buf,
- IN u32 c2h_size
-);
-
-HALMAC_RET_STATUS
-halmac_parse_psd_data_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pC2h_buf,
- IN u32 c2h_size
-);
-
-HALMAC_RET_STATUS
-halmac_parse_efuse_data_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pC2h_buf,
- IN u32 c2h_size
-);
-
-
-HALMAC_RET_STATUS
-halmac_parse_h2c_ack_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pC2h_buf,
- IN u32 c2h_size
-);
-
-HALMAC_RET_STATUS
-halmac_parse_h2c_ack_physical_efuse_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pC2h_buf,
- IN u32 c2h_size
-);
-
-HALMAC_RET_STATUS
-halmac_enqueue_para_buff_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_PHY_PARAMETER_INFO para_info,
- IN u8 *pCurr_buff_wptr,
- OUT u8 *pEnd_cmd
-);
-
-HALMAC_RET_STATUS
-halmac_parse_h2c_ack_cfg_para_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pC2h_buf,
- IN u32 c2h_size
-);
-
-HALMAC_RET_STATUS
-halmac_gen_cfg_para_h2c_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pH2c_buff
-);
-
-HALMAC_RET_STATUS
-halmac_parse_h2c_ack_update_packet_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pC2h_buf,
- IN u32 c2h_size
-);
-HALMAC_RET_STATUS
-halmac_parse_h2c_ack_update_datapack_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pC2h_buf,
- IN u32 c2h_size
-);
-
-HALMAC_RET_STATUS
-halmac_parse_h2c_ack_run_datapack_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pC2h_buf,
- IN u32 c2h_size
-);
-
-HALMAC_RET_STATUS
-halmac_parse_h2c_ack_channel_switch_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pC2h_buf,
- IN u32 c2h_size
-);
-
-HALMAC_RET_STATUS
-halmac_parse_h2c_ack_iqk_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pC2h_buf,
- IN u32 c2h_size
-);
-
-HALMAC_RET_STATUS
-halmac_parse_h2c_ack_power_tracking_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pC2h_buf,
- IN u32 c2h_size
-);
-
-HALMAC_RET_STATUS
-halmac_dump_efuse_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_EFUSE_READ_CFG cfg
-)
-{
- VOID *pDriver_adapter = NULL;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
- HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.efuse_state_set.process_status);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- *pProcess_status = HALMAC_CMD_PROCESS_SENDING;
-
- if (HALMAC_RET_SUCCESS != halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_H2C_SENT))
- return HALMAC_RET_ERROR_STATE;
-
- if (HALMAC_EFUSE_R_AUTO == cfg) {
- if (HALMAC_DLFW_NONE == pHalmac_adapter->halmac_state.dlfw_state)
- status = halmac_dump_efuse_drv_88xx(pHalmac_adapter);
- else
- status = halmac_dump_efuse_fw_88xx(pHalmac_adapter);
- } else if (HALMAC_EFUSE_R_FW == cfg) {
- status = halmac_dump_efuse_fw_88xx(pHalmac_adapter);
- } else {
- status = halmac_dump_efuse_drv_88xx(pHalmac_adapter);
- }
-
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_read_efuse error = %x\n", status);
- return status;
- }
-
- return status;
-}
-
-HALMAC_RET_STATUS
-halmac_func_read_efuse_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 offset,
- IN u32 size,
- OUT u8 *pEfuse_map
-)
-{
- VOID *pDriver_adapter = NULL;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- if (NULL == pEfuse_map) {
- PLATFORM_MSG_PRINT(pHalmac_adapter->pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Malloc for dump efuse map error\n");
- return HALMAC_RET_NULL_POINTER;
- }
-
- if (_TRUE == pHalmac_adapter->hal_efuse_map_valid)
- PLATFORM_RTL_MEMCPY(pDriver_adapter, pEfuse_map, pHalmac_adapter->pHalEfuse_map + offset, size);
- else
- if (HALMAC_RET_SUCCESS != halmac_read_hw_efuse_88xx(pHalmac_adapter, offset, size, pEfuse_map))
- return HALMAC_RET_EFUSE_R_FAIL;
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_read_hw_efuse_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 offset,
- IN u32 size,
- OUT u8 *pEfuse_map
-)
-{
- u8 value8;
- u32 value32;
- u32 address;
- u32 tmp32, counter;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- /* Read efuse no need 2.5V LDO */
- value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_LDO_EFUSE_CTRL + 3);
- if (value8 & BIT(7))
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_LDO_EFUSE_CTRL + 3, (u8)(value8 & ~(BIT(7))));
-
- value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_EFUSE_CTRL);
-
- for (address = offset; address < offset + size; address++) {
- value32 = value32 & ~((BIT_MASK_EF_DATA) | (BIT_MASK_EF_ADDR << BIT_SHIFT_EF_ADDR));
- value32 = value32 | ((address & BIT_MASK_EF_ADDR) << BIT_SHIFT_EF_ADDR);
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_EFUSE_CTRL, value32 & (~BIT_EF_FLAG));
-
- counter = 100;
- do {
- tmp32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_EFUSE_CTRL);
- counter--;
- if (0 == counter) {
- PLATFORM_MSG_PRINT(pHalmac_adapter->pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "HALMAC_RET_EFUSE_R_FAIL\n");
- return HALMAC_RET_EFUSE_R_FAIL;
- }
- } while (0 == (tmp32 & BIT_EF_FLAG));
-
- *(pEfuse_map + address - offset) = (u8)(tmp32 & BIT_MASK_EF_DATA);
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_dump_efuse_drv_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-)
-{
- u8 *pEfuse_map = NULL;
- u32 efuse_size;
- VOID *pDriver_adapter = NULL;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- efuse_size = pHalmac_adapter->hw_config_info.efuse_size;
-
- if (NULL == pHalmac_adapter->pHalEfuse_map) {
- pHalmac_adapter->pHalEfuse_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, efuse_size);
- if (NULL == pHalmac_adapter->pHalEfuse_map) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac allocate efuse map Fail!!\n");
- return HALMAC_RET_MALLOC_FAIL;
- }
- }
-
- pEfuse_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, efuse_size);
- if (NULL == pEfuse_map) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac allocate local efuse map Fail!!\n");
- return HALMAC_RET_MALLOC_FAIL;
- }
-
- if (HALMAC_RET_SUCCESS != halmac_read_hw_efuse_88xx(pHalmac_adapter, 0, efuse_size, pEfuse_map))
- return HALMAC_RET_EFUSE_R_FAIL;
-
- PLATFORM_MUTEX_LOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex));
- PLATFORM_RTL_MEMCPY(pDriver_adapter, pHalmac_adapter->pHalEfuse_map, pEfuse_map, efuse_size);
- pHalmac_adapter->hal_efuse_map_valid = _TRUE;
- PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex));
-
- PLATFORM_RTL_FREE(pDriver_adapter, pEfuse_map, efuse_size);
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_dump_efuse_fw_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-)
-{
- u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 };
- u32 eeprom_size = pHalmac_adapter->hw_config_info.eeprom_size;
- u16 h2c_seq_mum = 0;
- VOID *pDriver_adapter = NULL;
- HALMAC_H2C_HEADER_INFO h2c_header_info;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- h2c_header_info.sub_cmd_id = SUB_CMD_ID_DUMP_PHYSICAL_EFUSE;
- h2c_header_info.content_size = 0;
- h2c_header_info.ack = _TRUE;
- halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum);
- pHalmac_adapter->halmac_state.efuse_state_set.seq_num = h2c_seq_mum;
-
- if (NULL == pHalmac_adapter->pHalEfuse_map) {
- pHalmac_adapter->pHalEfuse_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, pHalmac_adapter->hw_config_info.efuse_size);
- if (NULL == pHalmac_adapter->pHalEfuse_map) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac allocate efuse map Fail!!\n");
- return HALMAC_RET_MALLOC_FAIL;
- }
- }
-
- if (_FALSE == pHalmac_adapter->hal_efuse_map_valid) {
- status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE);
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_read_efuse_fw Fail = %x!!\n", status);
- return status;
- }
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_func_write_efuse_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 offset,
- IN u8 value
-)
-{
- const u8 wite_protect_code = 0x69;
- u32 value32, tmp32, counter;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MUTEX_LOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex));
- pHalmac_adapter->hal_efuse_map_valid = _FALSE;
- PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex));
-
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PMC_DBG_CTRL2 + 3, wite_protect_code);
-
- /* Enable 2.5V LDO */
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_LDO_EFUSE_CTRL + 3, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_LDO_EFUSE_CTRL + 3) | BIT(7)));
-
- value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_EFUSE_CTRL);
- value32 = value32 & ~((BIT_MASK_EF_DATA) | (BIT_MASK_EF_ADDR << BIT_SHIFT_EF_ADDR));
- value32 = value32 | ((offset & BIT_MASK_EF_ADDR) << BIT_SHIFT_EF_ADDR) | (value & BIT_MASK_EF_DATA);
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_EFUSE_CTRL, value32 | BIT_EF_FLAG);
-
- counter = 100;
- do {
- tmp32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_EFUSE_CTRL);
- counter--;
- if (0 == counter) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_write_efuse Fail !!\n");
- return HALMAC_RET_EFUSE_W_FAIL;
- }
- } while (BIT_EF_FLAG == (tmp32 & BIT_EF_FLAG));
-
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PMC_DBG_CTRL2 + 3, 0x00);
-
- /* Disable 2.5V LDO */
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_LDO_EFUSE_CTRL + 3, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_LDO_EFUSE_CTRL + 3) & ~(BIT(7))));
-
- return HALMAC_RET_SUCCESS;
-}
-
-
-HALMAC_RET_STATUS
-halmac_func_switch_efuse_bank_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_EFUSE_BANK efuse_bank
-)
-{
- u8 reg_value;
- PHALMAC_API pHalmac_api;
-
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_BUSY))
- return HALMAC_RET_ERROR_STATE;
-
- reg_value = HALMAC_REG_READ_8(pHalmac_adapter, REG_LDO_EFUSE_CTRL + 1);
-
- if (efuse_bank == (reg_value & (BIT(0) | BIT(1))))
- return HALMAC_RET_SUCCESS;
-
- reg_value &= ~(BIT(0) | BIT(1));
- reg_value |= efuse_bank;
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_LDO_EFUSE_CTRL + 1, reg_value);
-
- if ((HALMAC_REG_READ_8(pHalmac_adapter, REG_LDO_EFUSE_CTRL + 1) & (BIT(0) | BIT(1))) != efuse_bank)
- return HALMAC_RET_SWITCH_EFUSE_BANK_FAIL;
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_eeprom_parser_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pPhysical_efuse_map,
- OUT u8 *pLogical_efuse_map
-)
-{
- u8 j;
- u8 value8;
- u8 block_index;
- u8 valid_word_enable, word_enable;
- u8 efuse_read_header, efuse_read_header2 = 0;
- u32 eeprom_index;
- u32 efuse_index = 0;
- u32 eeprom_size = pHalmac_adapter->hw_config_info.eeprom_size;
- VOID *pDriver_adapter = NULL;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_RTL_MEMSET(pDriver_adapter, pLogical_efuse_map, 0xFF, eeprom_size);
-
- while (1) {
- value8 = *(pPhysical_efuse_map + efuse_index);
- efuse_read_header = value8;
-
- if ((efuse_read_header & 0x1f) == 0x0f) {
- efuse_index++;
- value8 = *(pPhysical_efuse_map + efuse_index);
- efuse_read_header2 = value8;
- block_index = ((efuse_read_header2 & 0xF0) >> 1) | ((efuse_read_header >> 5) & 0x07);
- word_enable = efuse_read_header2 & 0x0F;
- } else {
- block_index = (efuse_read_header & 0xF0) >> 4;
- word_enable = efuse_read_header & 0x0F;
- }
-
- if (efuse_read_header == 0xff)
- break;
-
- efuse_index++;
-
- if (efuse_index >= pHalmac_adapter->hw_config_info.efuse_size - HALMAC_RESERVED_EFUSE_SIZE_88XX - 1)
- return HALMAC_RET_EEPROM_PARSING_FAIL;
-
- for (j = 0; j < 4; j++) {
- valid_word_enable = (u8)((~(word_enable >> j)) & BIT(0));
- if (valid_word_enable == 1) {
- eeprom_index = (block_index << 3) + (j << 1);
-
- if ((eeprom_index + 1) > eeprom_size) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Error: EEPROM addr exceeds eeprom_size:0x%X, at eFuse 0x%X\n", eeprom_size, efuse_index - 1);
- if ((efuse_read_header & 0x1f) == 0x0f)
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Error: EEPROM header: 0x%X, 0x%X,\n", efuse_read_header, efuse_read_header2);
- else
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Error: EEPROM header: 0x%X,\n", efuse_read_header);
- eeprom_index++;
- efuse_index = efuse_index + 2;
-
- return HALMAC_RET_EEPROM_PARSING_FAIL;
- } else {
- value8 = *(pPhysical_efuse_map + efuse_index);
- *(pLogical_efuse_map + eeprom_index) = value8;
-
- eeprom_index++;
- efuse_index++;
-
- if (efuse_index > pHalmac_adapter->hw_config_info.efuse_size - HALMAC_RESERVED_EFUSE_SIZE_88XX - 1)
- return HALMAC_RET_EEPROM_PARSING_FAIL;
-
- value8 = *(pPhysical_efuse_map + efuse_index);
- *(pLogical_efuse_map + eeprom_index) = value8;
-
- efuse_index++;
-
- if (efuse_index > pHalmac_adapter->hw_config_info.efuse_size - HALMAC_RESERVED_EFUSE_SIZE_88XX)
- return HALMAC_RET_EEPROM_PARSING_FAIL;
- }
- }
- }
- }
-
- pHalmac_adapter->efuse_end = efuse_index;
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_read_logical_efuse_map_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pMap
-)
-{
- u8 *pEfuse_map = NULL;
- u32 efuse_size;
- VOID *pDriver_adapter = NULL;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- efuse_size = pHalmac_adapter->hw_config_info.efuse_size;
-
- if (_FALSE == pHalmac_adapter->hal_efuse_map_valid) {
- pEfuse_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, efuse_size);
- if (NULL == pEfuse_map) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac allocate local efuse map Fail!!\n");
- return HALMAC_RET_MALLOC_FAIL;
- }
-
- if (NULL == pHalmac_adapter->pHalEfuse_map) {
- pHalmac_adapter->pHalEfuse_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, efuse_size);
- if (NULL == pHalmac_adapter->pHalEfuse_map) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac allocate efuse map Fail!!\n");
- return HALMAC_RET_MALLOC_FAIL;
- }
- }
-
- status = halmac_func_read_efuse_88xx(pHalmac_adapter, 0, efuse_size, pEfuse_map);
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_read_efuse error = %x\n", status);
- return status;
- }
-
- PLATFORM_MUTEX_LOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex));
- PLATFORM_RTL_MEMCPY(pDriver_adapter, pHalmac_adapter->pHalEfuse_map, pEfuse_map, efuse_size);
- pHalmac_adapter->hal_efuse_map_valid = _TRUE;
- PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex));
-
- PLATFORM_RTL_FREE(pDriver_adapter, pEfuse_map, efuse_size);
- }
-
- if (HALMAC_RET_SUCCESS != halmac_eeprom_parser_88xx(pHalmac_adapter, pHalmac_adapter->pHalEfuse_map, pMap))
- return HALMAC_RET_EEPROM_PARSING_FAIL;
-
- return status;
-}
-
-HALMAC_RET_STATUS
-halmac_func_write_logical_efuse_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 offset,
- IN u8 value
-)
-{
- u8 pg_efuse_byte1, pg_efuse_byte2;
- u8 pg_block, pg_block_index;
- u8 pg_efuse_header, pg_efuse_header2;
- u8 *pEeprom_map = NULL;
- u32 eeprom_size = pHalmac_adapter->hw_config_info.eeprom_size;
- u32 efuse_end;
- VOID *pDriver_adapter = NULL;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- pEeprom_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, eeprom_size);
- if (NULL == pEeprom_map) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac allocate local eeprom map Fail!!\n");
- return HALMAC_RET_MALLOC_FAIL;
- }
- PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_map, 0xFF, eeprom_size);
-
- status = halmac_read_logical_efuse_map_88xx(pHalmac_adapter, pEeprom_map);
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_read_logical_efuse_map_88xx error = %x\n", status);
- return status;
- }
-
- if (*(pEeprom_map + offset) != value) {
- efuse_end = pHalmac_adapter->efuse_end;
- pg_block = (u8)(offset >> 3);
- pg_block_index = (u8)((offset & (8 - 1)) >> 1);
-
- if (offset > 0x7f) {
- pg_efuse_header = (((pg_block & 0x07) << 5) & 0xE0) | 0x0F;
- pg_efuse_header2 = (u8)(((pg_block & 0x78) << 1) + ((0x1 << pg_block_index) ^ 0x0F));
- } else {
- pg_efuse_header = (u8)((pg_block << 4) + ((0x01 << pg_block_index) ^ 0x0F));
- }
-
- if ((offset & 1) == 0) {
- pg_efuse_byte1 = value;
- pg_efuse_byte2 = *(pEeprom_map + offset + 1);
- } else {
- pg_efuse_byte1 = *(pEeprom_map + offset - 1);
- pg_efuse_byte2 = value;
- }
-
- if (offset > 0x7f) {
- status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end, pg_efuse_header);
- status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 1, pg_efuse_header2);
- status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 2, pg_efuse_byte1);
- status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 3, pg_efuse_byte2);
- } else {
- status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end, pg_efuse_header);
- status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 1, pg_efuse_byte1);
- status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 2, pg_efuse_byte2);
- }
-
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_write_logical_efuse error = %x\n", status);
- return status;
- }
- }
-
- PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size);
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_func_pg_efuse_by_map_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_PG_EFUSE_INFO pPg_efuse_info,
- IN HALMAC_EFUSE_READ_CFG cfg
-)
-{
- u8 *pEeprom_mask_updated = NULL;
- u32 eeprom_mask_size = pHalmac_adapter->hw_config_info.eeprom_size >> 4;
- VOID *pDriver_adapter = NULL;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- pEeprom_mask_updated = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, eeprom_mask_size);
- if (NULL == pEeprom_mask_updated) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac allocate local eeprom map Fail!!\n");
- return HALMAC_RET_MALLOC_FAIL;
- }
- PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_mask_updated, 0x00, eeprom_mask_size);
-
- status = halmac_update_eeprom_mask_88xx(pHalmac_adapter, pPg_efuse_info, pEeprom_mask_updated);
-
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_update_eeprom_mask_88xx error = %x\n", status);
- return status;
- }
-
- status = halmac_check_efuse_enough_88xx(pHalmac_adapter, pPg_efuse_info, pEeprom_mask_updated);
-
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_check_efuse_enough_88xx error = %x\n", status);
- return status;
- }
-
- status = halmac_program_efuse_88xx(pHalmac_adapter, pPg_efuse_info, pEeprom_mask_updated);
-
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_program_efuse_88xx error = %x\n", status);
- return status;
- }
-
- PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_mask_updated, eeprom_mask_size);
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_update_eeprom_mask_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- INOUT PHALMAC_PG_EFUSE_INFO pPg_efuse_info,
- OUT u8 *pEeprom_mask_updated
-)
-{
- u8 *pEeprom_map = NULL;
- u32 eeprom_size = pHalmac_adapter->hw_config_info.eeprom_size;
- u8 *pEeprom_map_pg, *pEeprom_mask;
- u16 i, j;
- u16 map_byte_offset, mask_byte_offset;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- VOID *pDriver_adapter = NULL;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- pEeprom_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, eeprom_size);
- if (NULL == pEeprom_map) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac allocate local eeprom map Fail!!\n");
- return HALMAC_RET_MALLOC_FAIL;
- }
- PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_map, 0xFF, eeprom_size);
-
- PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_mask_updated, 0x00, pPg_efuse_info->efuse_mask_size);
-
- status = halmac_read_logical_efuse_map_88xx(pHalmac_adapter, pEeprom_map);
-
- if (HALMAC_RET_SUCCESS != status)
- return status;
-
- pEeprom_map_pg = pPg_efuse_info->pEfuse_map;
- pEeprom_mask = pPg_efuse_info->pEfuse_mask;
-
-
- for (i = 0; i < pPg_efuse_info->efuse_mask_size; i++)
- *(pEeprom_mask_updated + i) = *(pEeprom_mask + i);
-
- for (i = 0; i < pPg_efuse_info->efuse_map_size; i = i + 16) {
- for (j = 0; j < 16; j = j + 2) {
- map_byte_offset = i + j;
- mask_byte_offset = i >> 4;
- if (*(pEeprom_map_pg + map_byte_offset) == *(pEeprom_map + map_byte_offset)) {
- if (*(pEeprom_map_pg + map_byte_offset + 1) == *(pEeprom_map + map_byte_offset + 1)) {
- switch (j) {
- case 0:
- *(pEeprom_mask_updated + mask_byte_offset) = *(pEeprom_mask_updated + mask_byte_offset) & (BIT(4) ^ 0xFF);
- break;
- case 2:
- *(pEeprom_mask_updated + mask_byte_offset) = *(pEeprom_mask_updated + mask_byte_offset) & (BIT(5) ^ 0xFF);
- break;
- case 4:
- *(pEeprom_mask_updated + mask_byte_offset) = *(pEeprom_mask_updated + mask_byte_offset) & (BIT(6) ^ 0xFF);
- break;
- case 6:
- *(pEeprom_mask_updated + mask_byte_offset) = *(pEeprom_mask_updated + mask_byte_offset) & (BIT(7) ^ 0xFF);
- break;
- case 8:
- *(pEeprom_mask_updated + mask_byte_offset) = *(pEeprom_mask_updated + mask_byte_offset) & (BIT(0) ^ 0xFF);
- break;
- case 10:
- *(pEeprom_mask_updated + mask_byte_offset) = *(pEeprom_mask_updated + mask_byte_offset) & (BIT(1) ^ 0xFF);
- break;
- case 12:
- *(pEeprom_mask_updated + mask_byte_offset) = *(pEeprom_mask_updated + mask_byte_offset) & (BIT(2) ^ 0xFF);
- break;
- case 14:
- *(pEeprom_mask_updated + mask_byte_offset) = *(pEeprom_mask_updated + mask_byte_offset) & (BIT(3) ^ 0xFF);
- break;
- default:
- break;
- }
- }
- }
- }
- }
-
- PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size);
-
- return status;
-}
-
-HALMAC_RET_STATUS
-halmac_check_efuse_enough_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_PG_EFUSE_INFO pPg_efuse_info,
- IN u8 *pEeprom_mask_updated
-)
-{
- u8 pre_word_enb, word_enb;
- u8 pg_efuse_header, pg_efuse_header2;
- u8 pg_block;
- u16 i, j;
- u32 efuse_end;
- u32 tmp_eeprom_offset, pg_efuse_num = 0;
-
- efuse_end = pHalmac_adapter->efuse_end;
-
- for (i = 0; i < pPg_efuse_info->efuse_map_size; i = i + 8) {
- tmp_eeprom_offset = i;
-
- if ((tmp_eeprom_offset & 7) > 0) {
- pre_word_enb = (*(pEeprom_mask_updated + (i >> 4)) & 0x0F);
- word_enb = pre_word_enb ^ 0x0F;
- } else {
- pre_word_enb = (*(pEeprom_mask_updated + (i >> 4)) >> 4);
- word_enb = pre_word_enb ^ 0x0F;
- }
-
- pg_block = (u8)(tmp_eeprom_offset >> 3);
-
- if (pre_word_enb > 0) {
- if (tmp_eeprom_offset > 0x7f) {
- pg_efuse_header = (((pg_block & 0x07) << 5) & 0xE0) | 0x0F;
- pg_efuse_header2 = (u8)(((pg_block & 0x78) << 1) + word_enb);
- } else {
- pg_efuse_header = (u8)((pg_block << 4) + word_enb);
- }
-
- if (tmp_eeprom_offset > 0x7f) {
- pg_efuse_num++;
- pg_efuse_num++;
- efuse_end = efuse_end + 2;
- for (j = 0; j < 4; j++) {
- if (((pre_word_enb >> j) & 0x1) > 0) {
- pg_efuse_num++;
- pg_efuse_num++;
- efuse_end = efuse_end + 2;
- }
- }
- } else {
- pg_efuse_num++;
- efuse_end = efuse_end + 1;
- for (j = 0; j < 4; j++) {
- if (((pre_word_enb >> j) & 0x1) > 0) {
- pg_efuse_num++;
- pg_efuse_num++;
- efuse_end = efuse_end + 2;
- }
- }
- }
- }
- }
-
- if ((pHalmac_adapter->hw_config_info.efuse_size - pg_efuse_num - HALMAC_RESERVED_EFUSE_SIZE_88XX - pHalmac_adapter->efuse_end) <= 0)
- return HALMAC_RET_EFUSE_NOT_ENOUGH;
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_program_efuse_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_PG_EFUSE_INFO pPg_efuse_info,
- IN u8 *pEeprom_mask_updated
-)
-{
- u8 pre_word_enb, word_enb;
- u8 pg_efuse_header, pg_efuse_header2;
- u8 pg_block;
- u16 i, j;
- u32 efuse_end;
- u32 tmp_eeprom_offset;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- efuse_end = pHalmac_adapter->efuse_end;
-
- for (i = 0; i < pPg_efuse_info->efuse_map_size; i = i + 8) {
- tmp_eeprom_offset = i;
-
- if (((tmp_eeprom_offset >> 3) & 1) > 0) {
- pre_word_enb = (*(pEeprom_mask_updated + (i >> 4)) & 0x0F);
- word_enb = pre_word_enb ^ 0x0F;
- } else {
- pre_word_enb = (*(pEeprom_mask_updated + (i >> 4)) >> 4);
- word_enb = pre_word_enb ^ 0x0F;
- }
-
- pg_block = (u8)(tmp_eeprom_offset >> 3);
-
- if (pre_word_enb > 0) {
- if (tmp_eeprom_offset > 0x7f) {
- pg_efuse_header = (((pg_block & 0x07) << 5) & 0xE0) | 0x0F;
- pg_efuse_header2 = (u8)(((pg_block & 0x78) << 1) + word_enb);
- } else {
- pg_efuse_header = (u8)((pg_block << 4) + word_enb);
- }
-
- if (tmp_eeprom_offset > 0x7f) {
- status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end, pg_efuse_header);
- status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 1, pg_efuse_header2);
- efuse_end = efuse_end + 2;
- for (j = 0; j < 4; j++) {
- if (((pre_word_enb >> j) & 0x1) > 0) {
- status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end, *(pPg_efuse_info->pEfuse_map + tmp_eeprom_offset + (j << 1)));
- status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 1, *(pPg_efuse_info->pEfuse_map + tmp_eeprom_offset + (j << 1) + 1));
- efuse_end = efuse_end + 2;
- }
- }
- } else {
- status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end, pg_efuse_header);
- efuse_end = efuse_end + 1;
- for (j = 0; j < 4; j++) {
- if (((pre_word_enb >> j) & 0x1) > 0) {
- status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end, *(pPg_efuse_info->pEfuse_map + tmp_eeprom_offset + (j << 1)));
- status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 1, *(pPg_efuse_info->pEfuse_map + tmp_eeprom_offset + (j << 1) + 1));
- efuse_end = efuse_end + 2;
- }
- }
- }
- }
- }
-
- return status;
-}
-
-HALMAC_RET_STATUS
-halmac_dlfw_to_mem_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pRam_code,
- IN u32 dest,
- IN u32 code_size
-)
-{
- u8 *pCode_ptr;
- u8 first_part;
- u32 mem_offset;
- u32 pkt_size_tmp, send_pkt_size;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- pCode_ptr = pRam_code;
- mem_offset = 0;
- first_part = 1;
- pkt_size_tmp = code_size;
-
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_DDMA_CH0CTRL, HALMAC_REG_READ_32(pHalmac_adapter, REG_DDMA_CH0CTRL) | BIT_DDMACH0_RESET_CHKSUM_STS);
-
- while (0 != pkt_size_tmp) {
- if (pkt_size_tmp >= pHalmac_adapter->max_download_size)
- send_pkt_size = pHalmac_adapter->max_download_size;
- else
- send_pkt_size = pkt_size_tmp;
-
- if (HALMAC_RET_SUCCESS != halmac_send_fwpkt_88xx(pHalmac_adapter, pCode_ptr + mem_offset, send_pkt_size)) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_send_fwpkt_88xx fail!!");
- return HALMAC_RET_DLFW_FAIL;
- }
-
- if (HALMAC_RET_SUCCESS != halmac_iddma_dlfw_88xx(pHalmac_adapter, HALMAC_OCPBASE_TXBUF_88XX + pHalmac_adapter->hw_config_info.txdesc_size,
- dest + mem_offset, send_pkt_size, first_part)) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_iddma_dlfw_88xx fail!!");
- return HALMAC_RET_DLFW_FAIL;
- }
-
- first_part = 0;
- mem_offset += send_pkt_size;
- pkt_size_tmp -= send_pkt_size;
- }
-
- if (HALMAC_RET_SUCCESS != halmac_check_fw_chksum_88xx(pHalmac_adapter, dest)) {
- PLATFORM_MSG_PRINT(pHalmac_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_check_fw_chksum_88xx fail!!");
- return HALMAC_RET_DLFW_FAIL;
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_send_fwpkt_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pRam_code,
- IN u32 code_size
-)
-{
- VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- if (HALMAC_RET_SUCCESS != halmac_download_rsvd_page_88xx(pHalmac_adapter, pRam_code, code_size)) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_ERR, "PLATFORM_SEND_RSVD_PAGE 0 error!!\n");
- return HALMAC_RET_DL_RSVD_PAGE_FAIL;
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_iddma_dlfw_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 source,
- IN u32 dest,
- IN u32 length,
- IN u8 first
-)
-{
- u32 counter;
- u32 ch0_control = (u32)(BIT_DDMACH0_CHKSUM_EN | BIT_DDMACH0_OWN);
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- counter = HALMC_DDMA_POLLING_COUNT;
- while (HALMAC_REG_READ_32(pHalmac_adapter, REG_DDMA_CH0CTRL) & BIT_DDMACH0_OWN) {
- counter--;
- if (0 == counter) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_ERR, "halmac_iddma_dlfw_88xx error-1!!\n");
- return HALMAC_RET_DDMA_FAIL;
- }
- }
-
- ch0_control |= (length & BIT_MASK_DDMACH0_DLEN);
- if (0 == first)
- ch0_control |= BIT_DDMACH0_CHKSUM_CONT;
-
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_DDMA_CH0SA, source);
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_DDMA_CH0DA, dest);
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_DDMA_CH0CTRL, ch0_control);
-
- counter = HALMC_DDMA_POLLING_COUNT;
- while (HALMAC_REG_READ_32(pHalmac_adapter, REG_DDMA_CH0CTRL) & BIT_DDMACH0_OWN) {
- counter--;
- if (0 == counter) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_ERR, "halmac_iddma_dlfw_88xx error-2!!\n");
- return HALMAC_RET_DDMA_FAIL;
- }
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_check_fw_chksum_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 memory_address
-)
-{
- u8 mcu_fw_ctrl;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- mcu_fw_ctrl = HALMAC_REG_READ_8(pHalmac_adapter, REG_MCUFW_CTRL);
-
- if (HALMAC_REG_READ_32(pHalmac_adapter, REG_DDMA_CH0CTRL) & BIT_DDMACH0_CHKSUM_STS) {
- if (memory_address < HALMAC_OCPBASE_DMEM_88XX) {
- mcu_fw_ctrl |= BIT_IMEM_DW_OK;
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MCUFW_CTRL, (u8)(mcu_fw_ctrl & ~(BIT_IMEM_CHKSUM_OK)));
- } else {
- mcu_fw_ctrl |= BIT_DMEM_DW_OK;
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MCUFW_CTRL, (u8)(mcu_fw_ctrl & ~(BIT_DMEM_CHKSUM_OK)));
- }
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_ERR, "halmac_check_fw_chksum_88xx error!!\n");
-
- return HALMAC_RET_FW_CHECKSUM_FAIL;
- } else {
- if (memory_address < HALMAC_OCPBASE_DMEM_88XX) {
- mcu_fw_ctrl |= BIT_IMEM_DW_OK;
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MCUFW_CTRL, (u8)(mcu_fw_ctrl | BIT_IMEM_CHKSUM_OK));
- } else {
- mcu_fw_ctrl |= BIT_DMEM_DW_OK;
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MCUFW_CTRL, (u8)(mcu_fw_ctrl | BIT_DMEM_CHKSUM_OK));
- }
-
- return HALMAC_RET_SUCCESS;
- }
-}
-
-HALMAC_RET_STATUS
-halmac_dlfw_end_flow_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-)
-{
- u8 value8;
- u32 counter;
- VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- PHALMAC_API pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_TXDMA_STATUS, BIT(2));
-
- /* Check IMEM & DMEM checksum is OK or not */
- if (0x50 == (HALMAC_REG_READ_8(pHalmac_adapter, REG_MCUFW_CTRL) & 0x50))
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MCUFW_CTRL, (u16)(HALMAC_REG_READ_16(pHalmac_adapter, REG_MCUFW_CTRL) | BIT_FW_DW_RDY));
- else
- return HALMAC_RET_DLFW_FAIL;
-
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MCUFW_CTRL, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_MCUFW_CTRL) & ~(BIT(0))));
-
- value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_FUNC_EN + 1);
- value8 = (u8)(value8 | BIT(2));
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SYS_FUNC_EN + 1, value8); /* Release MCU reset */
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Download Finish, Reset CPU\n");
-
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_AUTO_LLT_V1, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_AUTO_LLT_V1) | BIT_AUTO_INIT_LLT_V1));
- counter = 1000;
- while (HALMAC_REG_READ_8(pHalmac_adapter, REG_AUTO_LLT_V1) & BIT_AUTO_INIT_LLT_V1) {
- counter--;
- if (counter == 0)
- return HALMAC_RET_INIT_LLT_FAIL;
- }
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Reset LLT\n");
-
- HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1, 0xC00F0038);
-
- counter = 10000;
- while (0xC078 != HALMAC_REG_READ_16(pHalmac_adapter, REG_MCUFW_CTRL)) {
- if (counter == 0) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Check 0x80 = 0xC078 fail\n");
- return HALMAC_RET_DLFW_FAIL;
- }
- counter--;
- PLATFORM_RTL_DELAY_US(pDriver_adapter, 50);
- }
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Check 0x80 = 0xC078 counter = %d\n", counter);
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_pwr_seq_parser_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 CUT,
- IN u8 FAB,
- IN u8 INTF,
- IN PHALMAC_WLAN_PWR_CFG PWR_SEQ_CFG
-)
-{
- u8 value;
- u8 PollingBit = _FALSE;
- u32 AryIdx = 0;
- u32 PollingCount;
- u32 offset;
- VOID *pDriver_adapter = NULL;
- HALMAC_WLAN_PWR_CFG PWR_SEQ_CMD;
- PHALMAC_API pHalmac_api;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- do {
- PWR_SEQ_CMD = PWR_SEQ_CFG[AryIdx];
-
- if ((PWR_SEQ_CMD.interface_msk & INTF) && (PWR_SEQ_CMD.fab_msk & FAB) && (PWR_SEQ_CMD.cut_msk & CUT)) {
- switch (PWR_SEQ_CMD.cmd) {
- case HALMAC_PWR_CMD_WRITE:
- if (PWR_SEQ_CMD.base == HALMAC_PWR_BASEADDR_SDIO)
- offset = PWR_SEQ_CMD.offset | SDIO_LOCAL_OFFSET;
- else
- offset = PWR_SEQ_CMD.offset;
-
- value = HALMAC_REG_READ_8(pHalmac_adapter, offset);
- value = (u8)(value & (u8)(~(PWR_SEQ_CMD.msk)));
- value = (u8)(value | (u8)(PWR_SEQ_CMD.value & PWR_SEQ_CMD.msk));
-
- HALMAC_REG_WRITE_8(pHalmac_adapter, offset, value);
- break;
- case HALMAC_PWR_CMD_POLLING:
- PollingBit = 0;
- PollingCount = HALMAC_POLLING_READY_TIMEOUT_COUNT;
-
- if (PWR_SEQ_CMD.base == HALMAC_PWR_BASEADDR_SDIO)
- offset = PWR_SEQ_CMD.offset | SDIO_LOCAL_OFFSET;
- else
- offset = PWR_SEQ_CMD.offset;
-
- do {
- PollingCount--;
- value = HALMAC_REG_READ_8(pHalmac_adapter, offset);
- value = (u8)(value & PWR_SEQ_CMD.msk);
-
- if (value == (PWR_SEQ_CMD.value & PWR_SEQ_CMD.msk)) {
- PollingBit = 1;
- } else {
- if (0 == PollingCount) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_pwr_seq_parser_88xx HALMAC_RET_PWRSEQ_POLLING_FAIL\n");
- return HALMAC_RET_PWRSEQ_POLLING_FAIL;
- } else {
- PLATFORM_RTL_DELAY_US(pDriver_adapter, 50);
- }
- }
- } while (!PollingBit);
- break;
- case HALMAC_PWR_CMD_DELAY:
- if (PWR_SEQ_CMD.value == HALMAC_PWRSEQ_DELAY_US)
- PLATFORM_RTL_DELAY_US(pDriver_adapter, PWR_SEQ_CMD.offset);
- else
- PLATFORM_RTL_DELAY_US(pDriver_adapter, 1000 * PWR_SEQ_CMD.offset);
- break;
- case HALMAC_PWR_CMD_READ:
- break;
- case HALMAC_PWR_CMD_END:
- return HALMAC_RET_SUCCESS;
- default:
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_pwr_seq_parser_88xx HALMAC_RET_PWRSEQ_CMD_INCORRECT\n");
- return HALMAC_RET_PWRSEQ_CMD_INCORRECT;
- }
- }
- AryIdx++;
- } while (1);
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_get_h2c_buff_free_space_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-)
-{
- u32 hw_wptr, fw_rptr;
- PHALMAC_API pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- hw_wptr = HALMAC_REG_READ_32(pHalmac_adapter, REG_H2C_PKT_WRITEADDR) & BIT_MASK_H2C_WR_ADDR;
- fw_rptr = HALMAC_REG_READ_32(pHalmac_adapter, REG_H2C_PKT_READADDR) & BIT_MASK_H2C_READ_ADDR;
-
- if (hw_wptr >= fw_rptr)
- pHalmac_adapter->h2c_buf_free_space = pHalmac_adapter->h2c_buff_size - (hw_wptr - fw_rptr);
- else
- pHalmac_adapter->h2c_buf_free_space = fw_rptr - hw_wptr;
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_send_h2c_pkt_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pHal_h2c_cmd,
- IN u32 size,
- IN u8 ack
-)
-{
- u32 counter = 100;
- VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- while (pHalmac_adapter->h2c_buf_free_space <= HALMAC_H2C_CMD_SIZE_UNIT_88XX) {
- halmac_get_h2c_buff_free_space_88xx(pHalmac_adapter);
- counter--;
- if (0 == counter) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "h2c free space is not enough!!\n");
- return HALMAC_RET_H2C_SPACE_FULL;
- }
- }
-
- /* Send TxDesc + H2C_CMD */
- if (_FALSE == PLATFORM_SEND_H2C_PKT(pDriver_adapter, pHal_h2c_cmd, size)) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Send H2C_CMD pkt error!!\n");
- return HALMAC_RET_SEND_H2C_FAIL;
- }
-
- pHalmac_adapter->h2c_buf_free_space -= HALMAC_H2C_CMD_SIZE_UNIT_88XX;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "H2C free space : %d\n", pHalmac_adapter->h2c_buf_free_space);
-
- return status;
-}
-
-HALMAC_RET_STATUS
-halmac_download_rsvd_page_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pHal_buf,
- IN u32 size
-)
-{
- u8 restore[3];
- u8 value8;
- u32 counter;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- if (0 == size) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "Rsvd page packet size is zero!!\n");
- return HALMAC_RET_ZERO_LEN_RSVD_PACKET;
- }
-
- value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_FIFOPAGE_CTRL_2 + 1);
- value8 = (u8)(value8 | BIT(7));
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FIFOPAGE_CTRL_2 + 1, value8);
-
- value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_CR + 1);
- restore[0] = value8;
- value8 = (u8)(value8 | BIT(0));
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR + 1, value8);
-
- value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_BCN_CTRL);
- restore[1] = value8;
- value8 = (u8)((value8 & ~(BIT(3))) | BIT(4));
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BCN_CTRL, value8);
-
- value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_FWHW_TXQ_CTRL + 2);
- restore[2] = value8;
- value8 = (u8)(value8 & ~(BIT(6)));
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FWHW_TXQ_CTRL + 2, value8);
-
- if (_FALSE == PLATFORM_SEND_RSVD_PAGE(pDriver_adapter, pHal_buf, size)) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "PLATFORM_SEND_RSVD_PAGE 1 error!!\n");
- status = HALMAC_RET_DL_RSVD_PAGE_FAIL;
- }
-
- /* Check Bcn_Valid_Bit */
- counter = 100;
- while (!(HALMAC_REG_READ_8(pHalmac_adapter, REG_FIFOPAGE_CTRL_2 + 1) & BIT(7))) {
- PLATFORM_RTL_DELAY_US(pDriver_adapter, 10);
- counter--;
- if (0 == counter) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Polling Bcn_Valid_Fail error!!\n");
- status = HALMAC_RET_POLLING_BCN_VALID_FAIL;
- break;
- }
- }
-
- value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_FIFOPAGE_CTRL_2 + 1);
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FIFOPAGE_CTRL_2 + 1, (value8 | BIT(7)));
-
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FWHW_TXQ_CTRL + 2, restore[2]);
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BCN_CTRL, restore[1]);
- HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR + 1, restore[0]);
-
- return status;
-}
-
-HALMAC_RET_STATUS
-halmac_set_h2c_header_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- OUT u8 *pHal_h2c_hdr,
- IN u16 *seq,
- IN u8 ack
-)
-{
- VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_set_h2c_header_88xx!!\n");
-
- H2C_CMD_HEADER_SET_CATEGORY(pHal_h2c_hdr, 0x00);
- H2C_CMD_HEADER_SET_TOTAL_LEN(pHal_h2c_hdr, 16);
-
- PLATFORM_MUTEX_LOCK(pDriver_adapter, &(pHalmac_adapter->h2c_seq_mutex));
- H2C_CMD_HEADER_SET_SEQ_NUM(pHal_h2c_hdr, pHalmac_adapter->h2c_packet_seq);
- *seq = pHalmac_adapter->h2c_packet_seq;
- pHalmac_adapter->h2c_packet_seq++;
- PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &(pHalmac_adapter->h2c_seq_mutex));
-
- if (_TRUE == ack)
- H2C_CMD_HEADER_SET_ACK(pHal_h2c_hdr, _TRUE);
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_set_fw_offload_h2c_header_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- OUT u8 *pHal_h2c_hdr,
- IN PHALMAC_H2C_HEADER_INFO pH2c_header_info,
- OUT u16 *pSeq_num
-)
-{
- VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_set_fw_offload_h2c_header_88xx!!\n");
-
- FW_OFFLOAD_H2C_SET_TOTAL_LEN(pHal_h2c_hdr, 8 + pH2c_header_info->content_size);
- FW_OFFLOAD_H2C_SET_SUB_CMD_ID(pHal_h2c_hdr, pH2c_header_info->sub_cmd_id);
-
- FW_OFFLOAD_H2C_SET_CATEGORY(pHal_h2c_hdr, 0x01);
- FW_OFFLOAD_H2C_SET_CMD_ID(pHal_h2c_hdr, 0xFF);
-
- PLATFORM_MUTEX_LOCK(pDriver_adapter, &(pHalmac_adapter->h2c_seq_mutex));
- FW_OFFLOAD_H2C_SET_SEQ_NUM(pHal_h2c_hdr, pHalmac_adapter->h2c_packet_seq);
- *pSeq_num = pHalmac_adapter->h2c_packet_seq;
- pHalmac_adapter->h2c_packet_seq++;
- PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &(pHalmac_adapter->h2c_seq_mutex));
-
- if (_TRUE == pH2c_header_info->ack)
- FW_OFFLOAD_H2C_SET_ACK(pHal_h2c_hdr, _TRUE);
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_send_h2c_set_pwr_mode_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_FWLPS_OPTION pHal_FwLps_Opt
-)
-{
- u8 h2c_buff[HALMAC_H2C_CMD_SIZE_88XX];
- u8 *pH2c_header, *pH2c_cmd;
- u16 seq = 0;
- VOID *pDriver_adapter = NULL;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_h2c_set_pwr_mode_88xx!!\n");
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pH2c_header = h2c_buff;
- pH2c_cmd = pH2c_header + HALMAC_H2C_CMD_HDR_SIZE_88XX;
-
- PLATFORM_RTL_MEMSET(pDriver_adapter, h2c_buff, 0x00, HALMAC_H2C_CMD_SIZE_88XX);
-
- SET_PWR_MODE_SET_CMD_ID(pH2c_cmd, CMD_ID_SET_PWR_MODE);
- SET_PWR_MODE_SET_CLASS(pH2c_cmd, CLASS_SET_PWR_MODE);
- SET_PWR_MODE_SET_MODE(pH2c_cmd, pHal_FwLps_Opt->mode);
- SET_PWR_MODE_SET_CLK_REQUEST(pH2c_cmd, pHal_FwLps_Opt->clk_request);
- SET_PWR_MODE_SET_RLBM(pH2c_cmd, pHal_FwLps_Opt->rlbm);
- SET_PWR_MODE_SET_SMART_PS(pH2c_cmd, pHal_FwLps_Opt->smart_ps);
- SET_PWR_MODE_SET_AWAKE_INTERVAL(pH2c_cmd, pHal_FwLps_Opt->awake_interval);
- SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD(pH2c_cmd, pHal_FwLps_Opt->all_queue_uapsd);
- SET_PWR_MODE_SET_PWR_STATE(pH2c_cmd, pHal_FwLps_Opt->pwr_state);
- SET_PWR_MODE_SET_ANT_AUTO_SWITCH(pH2c_cmd, pHal_FwLps_Opt->ant_auto_switch);
- SET_PWR_MODE_SET_PS_ALLOW_BT_HIGH_PRIORITY(pH2c_cmd, pHal_FwLps_Opt->ps_allow_bt_high_Priority);
- SET_PWR_MODE_SET_PROTECT_BCN(pH2c_cmd, pHal_FwLps_Opt->protect_bcn);
- SET_PWR_MODE_SET_SILENCE_PERIOD(pH2c_cmd, pHal_FwLps_Opt->silence_period);
- SET_PWR_MODE_SET_FAST_BT_CONNECT(pH2c_cmd, pHal_FwLps_Opt->fast_bt_connect);
- SET_PWR_MODE_SET_TWO_ANTENNA_EN(pH2c_cmd, pHal_FwLps_Opt->two_antenna_en);
- SET_PWR_MODE_SET_ADOPT_USER_SETTING(pH2c_cmd, pHal_FwLps_Opt->adopt_user_Setting);
- SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT(pH2c_cmd, pHal_FwLps_Opt->drv_bcn_early_shift);
-
- halmac_set_h2c_header_88xx(pHalmac_adapter, pH2c_header, &seq, _TRUE);
-
- status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, h2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE);
-
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_set_pwr_mode_88xx Fail = %x!!\n", status);
- return status;
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_func_send_original_h2c_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *original_h2c,
- IN u16 *seq,
- IN u8 ack
-)
-{
- u8 H2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 };
- u8 *pH2c_header, *pH2c_cmd;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_original_h2c ==========>\n");
-
- pH2c_header = H2c_buff;
- pH2c_cmd = pH2c_header + HALMAC_H2C_CMD_HDR_SIZE_88XX;
- PLATFORM_RTL_MEMCPY(pDriver_adapter, pH2c_cmd, original_h2c, 8); /* Original H2C 8 byte */
-
- halmac_set_h2c_header_88xx(pHalmac_adapter, pH2c_header, seq, ack);
-
- status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, H2c_buff, HALMAC_H2C_CMD_SIZE_88XX, ack);
-
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_original_h2c Fail = %x!!\n", status);
- return status;
- }
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_original_h2c <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_media_status_rpt_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 op_mode,
- IN u8 mac_id_ind,
- IN u8 mac_id,
- IN u8 mac_id_end
-)
-{
- u8 H2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 };
- u8 *pH2c_header, *pH2c_cmd;
- u16 seq = 0;
- VOID *pDriver_adapter = NULL;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_h2c_set_pwr_mode_88xx!!\n");
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pH2c_header = H2c_buff;
- pH2c_cmd = pH2c_header + HALMAC_H2C_CMD_HDR_SIZE_88XX;
-
- PLATFORM_RTL_MEMSET(pDriver_adapter, H2c_buff, 0x00, HALMAC_H2C_CMD_SIZE_88XX);
-
- MEDIA_STATUS_RPT_SET_CMD_ID(pH2c_cmd, CMD_ID_MEDIA_STATUS_RPT);
- MEDIA_STATUS_RPT_SET_CLASS(pH2c_cmd, CLASS_MEDIA_STATUS_RPT);
- MEDIA_STATUS_RPT_SET_OP_MODE(pH2c_cmd, op_mode);
- MEDIA_STATUS_RPT_SET_MACID_IN(pH2c_cmd, mac_id_ind);
- MEDIA_STATUS_RPT_SET_MACID(pH2c_cmd, mac_id);
- MEDIA_STATUS_RPT_SET_MACID_END(pH2c_cmd, mac_id_end);
-
- halmac_set_h2c_header_88xx(pHalmac_adapter, pH2c_header, &seq, _TRUE);
-
- status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, H2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE);
-
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_media_status_rpt_88xx Fail = %x!!\n", status);
- return status;
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_send_h2c_update_packet_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_PACKET_ID pkt_id,
- IN u8 *pkt,
- IN u32 pkt_size
-)
-{
- u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 };
- u16 h2c_seq_mum = 0;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
- HALMAC_H2C_HEADER_INFO h2c_header_info;
- HALMAC_RET_STATUS ret_status = HALMAC_RET_SUCCESS;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy & BIT_MASK_BCN_HEAD_1_V1));
-
- ret_status = halmac_download_rsvd_page_88xx(pHalmac_adapter, pkt, pkt_size);
-
- if (HALMAC_RET_SUCCESS != ret_status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_download_rsvd_page_88xx Fail = %x!!\n", ret_status);
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1));
- return ret_status;
- }
-
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1));
-
- UPDATE_PACKET_SET_SIZE(pH2c_buff, pkt_size + pHalmac_adapter->hw_config_info.txdesc_size);
- UPDATE_PACKET_SET_PACKET_ID(pH2c_buff, pkt_id);
- UPDATE_PACKET_SET_PACKET_LOC(pH2c_buff, pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy - pHalmac_adapter->txff_allocation.rsvd_pg_bndy);
-
- h2c_header_info.sub_cmd_id = SUB_CMD_ID_UPDATE_PACKET;
- h2c_header_info.content_size = 8;
- h2c_header_info.ack = _TRUE;
- halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum);
- pHalmac_adapter->halmac_state.update_packet_set.seq_num = h2c_seq_mum;
-
- ret_status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE);
-
- if (HALMAC_RET_SUCCESS != ret_status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_update_packet_88xx Fail = %x!!\n", ret_status);
- return ret_status;
- }
-
- return ret_status;
-}
-
-HALMAC_RET_STATUS
-halmac_send_h2c_phy_parameter_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_PHY_PARAMETER_INFO para_info,
- IN u8 full_fifo
-)
-{
- u8 drv_trigger_send = _FALSE;
- u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 };
- u16 h2c_seq_mum = 0;
- u32 info_size = 0;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
- HALMAC_H2C_HEADER_INFO h2c_header_info;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
- PHALMAC_CONFIG_PARA_INFO pConfig_para_info;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
- pConfig_para_info = &(pHalmac_adapter->config_para_info);
-
- /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_h2c_phy_parameter_88xx!!\n"); */
-
- if (NULL == pConfig_para_info->pCfg_para_buf) {
- if (_TRUE == full_fifo)
- pConfig_para_info->para_buf_size = HALMAC_EXTRA_INFO_BUFF_SIZE_FULL_FIFO_88XX;
- else
- pConfig_para_info->para_buf_size = HALMAC_EXTRA_INFO_BUFF_SIZE_88XX;
-
- pConfig_para_info->pCfg_para_buf = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, pConfig_para_info->para_buf_size);
-
- if (NULL != pConfig_para_info->pCfg_para_buf) {
- PLATFORM_RTL_MEMSET(pDriver_adapter, pConfig_para_info->pCfg_para_buf, 0x00, pConfig_para_info->para_buf_size);
- pConfig_para_info->full_fifo_mode = full_fifo;
- pConfig_para_info->pPara_buf_w = pConfig_para_info->pCfg_para_buf;
- pConfig_para_info->para_num = 0;
- pConfig_para_info->avai_para_buf_size = pConfig_para_info->para_buf_size;
- pConfig_para_info->value_accumulation = 0;
- pConfig_para_info->offset_accumulation = 0;
- } else {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "Allocate pCfg_para_buf fail!!\n");
- return HALMAC_RET_MALLOC_FAIL;
- }
- }
-
- if (HALMAC_RET_SUCCESS != halmac_transition_cfg_para_state_88xx(pHalmac_adapter, HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING))
- return HALMAC_RET_ERROR_STATE;
-
- halmac_enqueue_para_buff_88xx(pHalmac_adapter, para_info, pConfig_para_info->pPara_buf_w, &drv_trigger_send);
-
- if (HALMAC_PARAMETER_CMD_END != para_info->cmd_id) {
- pConfig_para_info->para_num++;
- pConfig_para_info->pPara_buf_w += HALMAC_FW_OFFLOAD_CMD_SIZE_88XX;
- pConfig_para_info->avai_para_buf_size = pConfig_para_info->avai_para_buf_size - HALMAC_FW_OFFLOAD_CMD_SIZE_88XX;
- }
-
- if (((pConfig_para_info->avai_para_buf_size - pHalmac_adapter->hw_config_info.txdesc_size) > HALMAC_FW_OFFLOAD_CMD_SIZE_88XX) &&
- (_FALSE == drv_trigger_send)) {
- return HALMAC_RET_SUCCESS;
- } else {
- if (0 == pConfig_para_info->para_num) {
- PLATFORM_RTL_FREE(pDriver_adapter, pConfig_para_info->pCfg_para_buf, pConfig_para_info->para_buf_size);
- pConfig_para_info->pCfg_para_buf = NULL;
- pConfig_para_info->pPara_buf_w = NULL;
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "no cfg parameter element!!\n");
-
- if (HALMAC_RET_SUCCESS != halmac_transition_cfg_para_state_88xx(pHalmac_adapter, HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE))
- return HALMAC_RET_ERROR_STATE;
-
- return HALMAC_RET_SUCCESS;
- }
-
- if (HALMAC_RET_SUCCESS != halmac_transition_cfg_para_state_88xx(pHalmac_adapter, HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT))
- return HALMAC_RET_ERROR_STATE;
-
- pHalmac_adapter->halmac_state.cfg_para_state_set.process_status = HALMAC_CMD_PROCESS_SENDING;
-
- if (_TRUE == pConfig_para_info->full_fifo_mode)
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, 0);
- else
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy & BIT_MASK_BCN_HEAD_1_V1));
-
- info_size = pConfig_para_info->para_num * HALMAC_FW_OFFLOAD_CMD_SIZE_88XX;
-
- status = halmac_download_rsvd_page_88xx(pHalmac_adapter, (u8 *)pConfig_para_info->pCfg_para_buf, info_size);
-
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_download_rsvd_page_88xx Fail!!\n");
- } else {
- halmac_gen_cfg_para_h2c_88xx(pHalmac_adapter, pH2c_buff);
-
- h2c_header_info.sub_cmd_id = SUB_CMD_ID_CFG_PARAMETER;
- h2c_header_info.content_size = 4;
- h2c_header_info.ack = _TRUE;
- halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum);
-
- pHalmac_adapter->halmac_state.cfg_para_state_set.seq_num = h2c_seq_mum;
-
- status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE);
-
- if (HALMAC_RET_SUCCESS != status)
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail!!\n");
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "config parameter time = %d\n", HALMAC_REG_READ_32(pHalmac_adapter, REG_FW_DBG6));
- }
-
- PLATFORM_RTL_FREE(pDriver_adapter, pConfig_para_info->pCfg_para_buf, pConfig_para_info->para_buf_size);
- pConfig_para_info->pCfg_para_buf = NULL;
- pConfig_para_info->pPara_buf_w = NULL;
-
- /* Restore bcn head */
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1));
-
- if (HALMAC_RET_SUCCESS != halmac_transition_cfg_para_state_88xx(pHalmac_adapter, HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE))
- return HALMAC_RET_ERROR_STATE;
- }
-
- if (_FALSE == drv_trigger_send) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Buffer full trigger sending H2C!!\n");
- return HALMAC_RET_PARA_SENDING;
- }
-
- return status;
-}
-
-HALMAC_RET_STATUS
-halmac_enqueue_para_buff_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_PHY_PARAMETER_INFO para_info,
- IN u8 *pCurr_buff_wptr,
- OUT u8 *pEnd_cmd
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_CONFIG_PARA_INFO pConfig_para_info = &(pHalmac_adapter->config_para_info);
-
- *pEnd_cmd = _FALSE;
-
- PHY_PARAMETER_INFO_SET_LENGTH(pCurr_buff_wptr, HALMAC_FW_OFFLOAD_CMD_SIZE_88XX);
- PHY_PARAMETER_INFO_SET_IO_CMD(pCurr_buff_wptr, para_info->cmd_id);
-
- switch (para_info->cmd_id) {
- case HALMAC_PARAMETER_CMD_BB_W8:
- case HALMAC_PARAMETER_CMD_BB_W16:
- case HALMAC_PARAMETER_CMD_BB_W32:
- case HALMAC_PARAMETER_CMD_MAC_W8:
- case HALMAC_PARAMETER_CMD_MAC_W16:
- case HALMAC_PARAMETER_CMD_MAC_W32:
- PHY_PARAMETER_INFO_SET_IO_ADDR(pCurr_buff_wptr, para_info->content.MAC_REG_W.offset);
- PHY_PARAMETER_INFO_SET_DATA(pCurr_buff_wptr, para_info->content.MAC_REG_W.value);
- PHY_PARAMETER_INFO_SET_MASK(pCurr_buff_wptr, para_info->content.MAC_REG_W.msk);
- PHY_PARAMETER_INFO_SET_MSK_EN(pCurr_buff_wptr, para_info->content.MAC_REG_W.msk_en);
- pConfig_para_info->value_accumulation += para_info->content.MAC_REG_W.value;
- pConfig_para_info->offset_accumulation += para_info->content.MAC_REG_W.offset;
- break;
- case HALMAC_PARAMETER_CMD_RF_W:
- PHY_PARAMETER_INFO_SET_RF_ADDR(pCurr_buff_wptr, para_info->content.RF_REG_W.offset); /*In rf register, the address is only 1 byte*/
- PHY_PARAMETER_INFO_SET_RF_PATH(pCurr_buff_wptr, para_info->content.RF_REG_W.rf_path);
- PHY_PARAMETER_INFO_SET_DATA(pCurr_buff_wptr, para_info->content.RF_REG_W.value);
- PHY_PARAMETER_INFO_SET_MASK(pCurr_buff_wptr, para_info->content.RF_REG_W.msk);
- PHY_PARAMETER_INFO_SET_MSK_EN(pCurr_buff_wptr, para_info->content.RF_REG_W.msk_en);
- pConfig_para_info->value_accumulation += para_info->content.RF_REG_W.value;
- pConfig_para_info->offset_accumulation += (para_info->content.RF_REG_W.offset + (para_info->content.RF_REG_W.rf_path << 8));
- break;
- case HALMAC_PARAMETER_CMD_DELAY_US:
- case HALMAC_PARAMETER_CMD_DELAY_MS:
- PHY_PARAMETER_INFO_SET_DELAY_VALUE(pCurr_buff_wptr, para_info->content.DELAY_TIME.delay_time);
- break;
- case HALMAC_PARAMETER_CMD_END:
- *pEnd_cmd = _TRUE;
- break;
- default:
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, " halmac_send_h2c_phy_parameter_88xx illegal cmd_id!!\n");
- break;
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_gen_cfg_para_h2c_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pH2c_buff
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_CONFIG_PARA_INFO pConfig_para_info = &(pHalmac_adapter->config_para_info);
-
- CFG_PARAMETER_SET_NUM(pH2c_buff, pConfig_para_info->para_num);
-
- if (_TRUE == pConfig_para_info->full_fifo_mode) {
- CFG_PARAMETER_SET_INIT_CASE(pH2c_buff, 0x1);
- CFG_PARAMETER_SET_PHY_PARAMETER_LOC(pH2c_buff, 0);
- } else {
- CFG_PARAMETER_SET_INIT_CASE(pH2c_buff, 0x0);
- CFG_PARAMETER_SET_PHY_PARAMETER_LOC(pH2c_buff, pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy - pHalmac_adapter->txff_allocation.rsvd_pg_bndy);
- }
-
- return HALMAC_RET_SUCCESS;
-}
-#if 0
-HALMAC_RET_STATUS
-halmac_send_h2c_update_datapack_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_DATA_TYPE halmac_data_type,
- IN PHALMAC_PHY_PARAMETER_INFO para_info
-)
-{
- u8 drv_trigger_send = _FALSE;
- u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 };
- u8 *pCurr_buf_w;
- u16 h2c_seq_mum = 0;
- u32 info_size = 0;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
- PHALMAC_CONFIG_PARA_INFO pConfig_para_info;
- HALMAC_H2C_HEADER_INFO h2c_header_info;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
- pConfig_para_info = &(pHalmac_adapter->config_para_info);
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_h2c_phy_parameter_88xx!!\n");
-
- if (NULL == pConfig_para_info->pCfg_para_buf) {/*Buff null, allocate memory according to use mode*/
- /*else, only 4k reserved page is used*/
- pConfig_para_info->para_buf_size = HALMAC_EXTRA_INFO_BUFF_SIZE_88XX;
- /* pConfig_para_info->datapack_segment =0; */
-
-
- pConfig_para_info->pCfg_para_buf = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, pConfig_para_info->para_buf_size);
- if (NULL != pConfig_para_info->pCfg_para_buf) {
- /*Reset buffer parameter*/
- PLATFORM_RTL_MEMSET(pDriver_adapter, pConfig_para_info->pCfg_para_buf, 0x00, pConfig_para_info->para_buf_size);
- /* pConfig_para_info->full_fifo_mode = full_fifo; */
- pConfig_para_info->data_type = halmac_data_type;
- pConfig_para_info->pPara_buf_w = pConfig_para_info->pCfg_para_buf;
- pConfig_para_info->para_num = 0;
- pConfig_para_info->avai_para_buf_size = pConfig_para_info->para_buf_size;
- } else {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Allocate pCfg_para_buf fail!!\n");
- return HALMAC_RET_MALLOC_FAIL;
- }
- }
-
- pCurr_buf_w = pConfig_para_info->pPara_buf_w;
-
- /*Start fill buffer content*/
- PHY_PARAMETER_INFO_SET_LENGTH(pCurr_buf_w, HALMAC_FW_OFFLOAD_CMD_SIZE_88XX);/* Each element is 12 Byte */
- PHY_PARAMETER_INFO_SET_IO_CMD(pCurr_buf_w, para_info->cmd_id);
-
- switch (para_info->cmd_id) {
- case HALMAC_PARAMETER_CMD_BB_W8:
- case HALMAC_PARAMETER_CMD_BB_W16:
- case HALMAC_PARAMETER_CMD_BB_W32:
- case HALMAC_PARAMETER_CMD_MAC_W8:
- case HALMAC_PARAMETER_CMD_MAC_W16:
- case HALMAC_PARAMETER_CMD_MAC_W32:
- PHY_PARAMETER_INFO_SET_IO_ADDR(pCurr_buf_w, para_info->content.MAC_REG_W.offset);
- PHY_PARAMETER_INFO_SET_DATA(pCurr_buf_w, para_info->content.MAC_REG_W.value);
- PHY_PARAMETER_INFO_SET_MASK(pCurr_buf_w, para_info->content.MAC_REG_W.msk);
- PHY_PARAMETER_INFO_SET_MSK_EN(pCurr_buf_w, para_info->content.MAC_REG_W.msk_en);
- break;
- case HALMAC_PARAMETER_CMD_RF_W:
- PHY_PARAMETER_INFO_SET_RF_ADDR(pCurr_buf_w, para_info->content.RF_REG_W.offset); /* In rf register, the address is only 1 byte */
- PHY_PARAMETER_INFO_SET_RF_PATH(pCurr_buf_w, para_info->content.RF_REG_W.rf_path);
- PHY_PARAMETER_INFO_SET_DATA(pCurr_buf_w, para_info->content.RF_REG_W.value);
- PHY_PARAMETER_INFO_SET_MASK(pCurr_buf_w, para_info->content.RF_REG_W.msk);
- PHY_PARAMETER_INFO_SET_MSK_EN(pCurr_buf_w, para_info->content.MAC_REG_W.msk_en);
- break;
- case HALMAC_PARAMETER_CMD_DELAY_US:
- case HALMAC_PARAMETER_CMD_DELAY_MS:
- PHY_PARAMETER_INFO_SET_DELAY_VALUE(pCurr_buf_w, para_info->content.DELAY_TIME.delay_time);
- break;
-
- case HALMAC_PARAMETER_CMD_END:
- /* PHY_PARAMETER_INFO_SET_MSK_EN(pHalmac_adapter->pPara_buf_w, 1); */
- drv_trigger_send = _TRUE;
- break;
- default:
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "illegal cmd_id!!\n");
- /* return _FALSE; */
- break;
- }
-
- /*Update parameter buffer variable*/
- if (HALMAC_PARAMETER_CMD_END != para_info->cmd_id) {
- pConfig_para_info->para_num++;
- pConfig_para_info->pPara_buf_w += HALMAC_FW_OFFLOAD_CMD_SIZE_88XX;
- pConfig_para_info->avai_para_buf_size = pConfig_para_info->avai_para_buf_size - HALMAC_FW_OFFLOAD_CMD_SIZE_88XX;
- }
-
- if (((pConfig_para_info->avai_para_buf_size - pHalmac_adapter->hw_config_info.txdesc_size) > HALMAC_FW_OFFLOAD_CMD_SIZE_88XX) && (_FALSE == drv_trigger_send)) {
- /*There are still space for parameter cmd, and driver does not trigger it to send, so keep it in buffer temporarily*/
- return HALMAC_RET_SUCCESS_ENQUEUE;
- } else {
- /*There is no space or driver trigger it to send*/
-
- /*Update the bcn head(dma)*/
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->h2c_extra_info_boundary & BIT_MASK_BCN_HEAD_1_V1));
-
- /* Download to reserved page */
- info_size = pConfig_para_info->para_num * HALMAC_FW_OFFLOAD_CMD_SIZE_88XX;
- status = halmac_download_rsvd_page_88xx(pHalmac_adapter, (u8 *)pConfig_para_info->pCfg_para_buf, info_size);
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_download_rsvd_page_88xx Fail!!\n");
- } else {/*download rsvd page ok, send h2c packet to fw*/
- /* Construct H2C Content */
- UPDATE_DATAPACK_SET_SIZE(pH2c_buff, pConfig_para_info->para_num * HALMAC_FW_OFFLOAD_CMD_SIZE_88XX);
- UPDATE_DATAPACK_SET_DATAPACK_ID(pH2c_buff, pConfig_para_info->data_type);
- UPDATE_DATAPACK_SET_DATAPACK_LOC(pH2c_buff, pHalmac_adapter->h2c_extra_info_boundary - pHalmac_adapter->Tx_boundary);
- UPDATE_DATAPACK_SET_DATAPACK_SEGMENT(pH2c_buff, pConfig_para_info->datapack_segment);
- UPDATE_DATAPACK_SET_END_SEGMENT(pH2c_buff, drv_trigger_send);
-
- /* Fill in H2C Header */
- h2c_header_info.sub_cmd_id = SUB_CMD_ID_UPDATE_DATAPACK;
- h2c_header_info.content_size = 8;
- h2c_header_info.ack = _TRUE;
- halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum);
-
- /* Send H2C Cmd Packet */
- status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE);
- if (HALMAC_RET_SUCCESS != status)
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail!!\n");
- }
-
- PLATFORM_RTL_FREE(pDriver_adapter, pConfig_para_info->pCfg_para_buf, pConfig_para_info->para_buf_size);
- if (_TRUE == drv_trigger_send)
- pConfig_para_info->datapack_segment = 0;
- else
- pConfig_para_info->datapack_segment++;
-
- pConfig_para_info->pCfg_para_buf = NULL;
- pConfig_para_info->pPara_buf_w = NULL;
- pConfig_para_info->para_num = 0;
- pConfig_para_info->avai_para_buf_size = 0;
-
- /*Restore Register after FW handle the H2C packet*/
-
- /*only set bcn head back*/
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->Tx_boundary & BIT_MASK_BCN_HEAD_1_V1));
- }
-
- return status;
-}
-#endif
-HALMAC_RET_STATUS
-halmac_send_h2c_run_datapack_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_DATA_TYPE halmac_data_type
-)
-{
- u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 };
- u16 h2c_seq_mum = 0;
- VOID *pDriver_adapter = NULL;
- HALMAC_H2C_HEADER_INFO h2c_header_info;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_h2c_run_datapack_88xx!!\n");
-
- RUN_DATAPACK_SET_DATAPACK_ID(pH2c_buff, halmac_data_type);
-
- h2c_header_info.sub_cmd_id = SUB_CMD_ID_RUN_DATAPACK;
- h2c_header_info.content_size = 4;
- h2c_header_info.ack = _TRUE;
- halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum);
-
- status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE);
-
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail = %x!!\n", status);
- return status;
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_send_bt_coex_cmd_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pBt_buf,
- IN u32 bt_size,
- IN u8 ack
-)
-{
- u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 };
- u16 h2c_seq_mum = 0;
- VOID *pDriver_adapter = NULL;
- HALMAC_H2C_HEADER_INFO h2c_header_info;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_bt_coex_cmd_88xx!!\n");
-
- PLATFORM_RTL_MEMCPY(pDriver_adapter, pH2c_buff + 8, pBt_buf, bt_size);
-
- h2c_header_info.sub_cmd_id = SUB_CMD_ID_BT_COEX;
- h2c_header_info.content_size = (u16)bt_size;
- h2c_header_info.ack = ack;
- halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum);
-
- status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, ack);
-
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail = %x!!\n", status);
- return status;
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-
-HALMAC_RET_STATUS
-halmac_func_ctrl_ch_switch_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_CH_SWITCH_OPTION pCs_option
-)
-{
- u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 };
- u16 h2c_seq_mum = 0;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
- HALMAC_H2C_HEADER_INFO h2c_header_info;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
- HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.scan_state_set.process_status);
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_ctrl_ch_switch!!\n");
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- if (HALMAC_RET_SUCCESS != halmac_transition_scan_state_88xx(pHalmac_adapter, HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT))
- return HALMAC_RET_ERROR_STATE;
-
- *pProcess_status = HALMAC_CMD_PROCESS_SENDING;
-
- if (0 != pCs_option->switch_en) {
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy & BIT_MASK_BCN_HEAD_1_V1));
-
- status = halmac_download_rsvd_page_88xx(pHalmac_adapter, pHalmac_adapter->ch_sw_info.ch_info_buf, pHalmac_adapter->ch_sw_info.total_size);
-
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_download_rsvd_page_88xx Fail = %x!!\n", status);
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1));
- return status;
- }
-
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1));
- }
-
- CHANNEL_SWITCH_SET_SWITCH_START(pH2c_buff, pCs_option->switch_en);
- CHANNEL_SWITCH_SET_CHANNEL_NUM(pH2c_buff, pHalmac_adapter->ch_sw_info.ch_num);
- CHANNEL_SWITCH_SET_CHANNEL_INFO_LOC(pH2c_buff, pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy - pHalmac_adapter->txff_allocation.rsvd_pg_bndy);
- CHANNEL_SWITCH_SET_DEST_CH_EN(pH2c_buff, pCs_option->dest_ch_en);
- CHANNEL_SWITCH_SET_DEST_CH(pH2c_buff, pCs_option->dest_ch);
- CHANNEL_SWITCH_SET_PRI_CH_IDX(pH2c_buff, pCs_option->dest_pri_ch_idx);
- CHANNEL_SWITCH_SET_ABSOLUTE_TIME(pH2c_buff, pCs_option->absolute_time_en);
- CHANNEL_SWITCH_SET_TSF_LOW(pH2c_buff, pCs_option->tsf_low);
- CHANNEL_SWITCH_SET_PERIODIC_OPTION(pH2c_buff, pCs_option->periodic_option);
- CHANNEL_SWITCH_SET_NORMAL_CYCLE(pH2c_buff, pCs_option->normal_cycle);
- CHANNEL_SWITCH_SET_NORMAL_PERIOD(pH2c_buff, pCs_option->normal_period);
- CHANNEL_SWITCH_SET_SLOW_PERIOD(pH2c_buff, pCs_option->phase_2_period);
- CHANNEL_SWITCH_SET_CHANNEL_INFO_SIZE(pH2c_buff, pHalmac_adapter->ch_sw_info.total_size);
-
- h2c_header_info.sub_cmd_id = SUB_CMD_ID_CHANNEL_SWITCH;
- h2c_header_info.content_size = 20;
- h2c_header_info.ack = _TRUE;
- halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum);
- pHalmac_adapter->halmac_state.scan_state_set.seq_num = h2c_seq_mum;
-
- status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE);
-
- if (HALMAC_RET_SUCCESS != status)
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail = %x!!\n", status);
-
- PLATFORM_RTL_FREE(pDriver_adapter, pHalmac_adapter->ch_sw_info.ch_info_buf, pHalmac_adapter->ch_sw_info.buf_size);
- pHalmac_adapter->ch_sw_info.ch_info_buf = NULL;
- pHalmac_adapter->ch_sw_info.ch_info_buf_w = NULL;
- pHalmac_adapter->ch_sw_info.extra_info_en = 0;
- pHalmac_adapter->ch_sw_info.buf_size = 0;
- pHalmac_adapter->ch_sw_info.avai_buf_size = 0;
- pHalmac_adapter->ch_sw_info.total_size = 0;
- pHalmac_adapter->ch_sw_info.ch_num = 0;
-
- if (HALMAC_RET_SUCCESS != halmac_transition_scan_state_88xx(pHalmac_adapter, HALMAC_SCAN_CMD_CONSTRUCT_IDLE))
- return HALMAC_RET_ERROR_STATE;
-
- return status;
-}
-
-HALMAC_RET_STATUS
-halmac_func_send_general_info_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_GENERAL_INFO pGeneral_info
-)
-{
- u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 };
- u16 h2c_seq_mum = 0;
- VOID *pDriver_adapter = NULL;
- HALMAC_H2C_HEADER_INFO h2c_header_info;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_general_info!!\n");
-
- GENERAL_INFO_SET_REF_TYPE(pH2c_buff, pGeneral_info->rfe_type);
- GENERAL_INFO_SET_RF_TYPE(pH2c_buff, pGeneral_info->rf_type);
- GENERAL_INFO_SET_FW_TX_BOUNDARY(pH2c_buff, pHalmac_adapter->txff_allocation.rsvd_fw_txbuff_pg_bndy - pHalmac_adapter->txff_allocation.rsvd_pg_bndy);
-
- h2c_header_info.sub_cmd_id = SUB_CMD_ID_GENERAL_INFO;
- h2c_header_info.content_size = 4;
- h2c_header_info.ack = _FALSE;
- halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum);
-
- status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE);
-
- if (HALMAC_RET_SUCCESS != status)
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail = %x!!\n", status);
-
- return status;
-}
-
-HALMAC_RET_STATUS
-halmac_send_h2c_update_bcn_parse_info_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_BCN_IE_INFO pBcn_ie_info
-)
-{
- u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 };
- u16 h2c_seq_mum = 0;
- VOID *pDriver_adapter = NULL;
- HALMAC_H2C_HEADER_INFO h2c_header_info;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_h2c_update_bcn_parse_info_88xx!!\n");
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- UPDATE_BEACON_PARSING_INFO_SET_FUNC_EN(pH2c_buff, pBcn_ie_info->func_en);
- UPDATE_BEACON_PARSING_INFO_SET_SIZE_TH(pH2c_buff, pBcn_ie_info->size_th);
- UPDATE_BEACON_PARSING_INFO_SET_TIMEOUT(pH2c_buff, pBcn_ie_info->timeout);
-
- UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_0(pH2c_buff, (u32)(pBcn_ie_info->ie_bmp[0]));
- UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_1(pH2c_buff, (u32)(pBcn_ie_info->ie_bmp[1]));
- UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_2(pH2c_buff, (u32)(pBcn_ie_info->ie_bmp[2]));
- UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_3(pH2c_buff, (u32)(pBcn_ie_info->ie_bmp[3]));
- UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_4(pH2c_buff, (u32)(pBcn_ie_info->ie_bmp[4]));
-
- h2c_header_info.sub_cmd_id = SUB_CMD_ID_UPDATE_BEACON_PARSING_INFO;
- h2c_header_info.content_size = 24;
- h2c_header_info.ack = _TRUE;
- halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum);
-
- status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE);
-
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail =%x !!\n", status);
- return status;
- }
-
- return status;
-}
-
-HALMAC_RET_STATUS
-halmac_send_h2c_ps_tuning_para_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-)
-{
- u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 };
- u8 *pH2c_header, *pH2c_cmd;
- u16 seq = 0;
- VOID *pDriver_adapter = NULL;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_h2c_ps_tuning_para_88xx!!\n");
-
- pH2c_header = pH2c_buff;
- pH2c_cmd = pH2c_header + HALMAC_H2C_CMD_HDR_SIZE_88XX;
-
- halmac_set_h2c_header_88xx(pHalmac_adapter, pH2c_header, &seq, _FALSE);
-
- status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _FALSE);
-
- if (HALMAC_RET_SUCCESS != status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail = %x!!\n", status);
- return status;
- }
-
- return status;
-}
-
-HALMAC_RET_STATUS
-halmac_parse_c2h_packet_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *halmac_buf,
- IN u32 halmac_size
-)
-{
- u8 c2h_cmd, c2h_sub_cmd_id;
- u8 *pC2h_buf = halmac_buf + pHalmac_adapter->hw_config_info.rxdesc_size;
- u32 c2h_size = halmac_size - pHalmac_adapter->hw_config_info.rxdesc_size;
- VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
- /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_parse_c2h_packet_88xx!!\n"); */
-
- c2h_cmd = (u8)C2H_HDR_GET_CMD_ID(pC2h_buf);
-
- /* FW offload C2H cmd is 0xFF */
- if (0xFF != c2h_cmd) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "C2H_PKT not for FwOffloadC2HFormat!!\n");
- return HALMAC_RET_C2H_NOT_HANDLED;
- }
-
- /* Get C2H sub cmd ID */
- c2h_sub_cmd_id = (u8)C2H_HDR_GET_C2H_SUB_CMD_ID(pC2h_buf);
-
- switch (c2h_sub_cmd_id) {
- case C2H_SUB_CMD_ID_C2H_DBG:
- status = halmac_parse_c2h_debug_88xx(pHalmac_adapter, pC2h_buf, c2h_size);
- break;
- case C2H_SUB_CMD_ID_H2C_ACK_HDR:
- status = halmac_parse_h2c_ack_88xx(pHalmac_adapter, pC2h_buf, c2h_size);
- break;
- case C2H_SUB_CMD_ID_BT_COEX_INFO:
- status = HALMAC_RET_C2H_NOT_HANDLED;
- break;
- case C2H_SUB_CMD_ID_SCAN_STATUS_RPT:
- status = halmac_parse_scan_status_rpt_88xx(pHalmac_adapter, pC2h_buf, c2h_size);
- break;
- case C2H_SUB_CMD_ID_PSD_DATA:
- status = halmac_parse_psd_data_88xx(pHalmac_adapter, pC2h_buf, c2h_size);
- break;
-
- case C2H_SUB_CMD_ID_EFUSE_DATA:
- status = halmac_parse_efuse_data_88xx(pHalmac_adapter, pC2h_buf, c2h_size);
- break;
- default:
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "c2h_sub_cmd_id switch case out of boundary!!\n");
- status = HALMAC_RET_C2H_NOT_HANDLED;
- break;
- }
-
- return status;
-}
-
-HALMAC_RET_STATUS
-halmac_parse_c2h_debug_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pC2h_buf,
- IN u32 c2h_size
-)
-{
- VOID *pDriver_adapter = NULL;
- u8 *pC2h_buf_local = (u8 *)NULL;
- u32 c2h_size_local = 0;
- u8 dbg_content_length = 0;
- u8 dbg_seq_num = 0;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pC2h_buf_local = pC2h_buf;
- c2h_size_local = c2h_size;
-
- dbg_content_length = (u8)C2H_HDR_GET_LEN((u8 *)pC2h_buf_local);
-
- if (dbg_content_length > C2H_DBG_CONTENT_MAX_LENGTH) {
- return HALMAC_RET_SUCCESS;
- } else {
- *(pC2h_buf_local + C2H_DBG_HEADER_LENGTH + dbg_content_length - 2) = '\n';
- dbg_seq_num = (u8)(*(pC2h_buf_local + C2H_DBG_HEADER_LENGTH));
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[RTKFW, SEQ=%d]: %s", dbg_seq_num, (char *)(pC2h_buf_local + C2H_DBG_HEADER_LENGTH + 1));
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-
-HALMAC_RET_STATUS
-halmac_parse_scan_status_rpt_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pC2h_buf,
- IN u32 c2h_size
-)
-{
- u8 h2c_return_code;
- VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- HALMAC_CMD_PROCESS_STATUS process_status = HALMAC_CMD_PROCESS_UNDEFINE;
-
- h2c_return_code = (u8)SCAN_STATUS_RPT_GET_H2C_RETURN_CODE(pC2h_buf);
- process_status = (HALMAC_H2C_RETURN_SUCCESS == (HALMAC_H2C_RETURN_CODE)h2c_return_code) ? HALMAC_CMD_PROCESS_DONE : HALMAC_CMD_PROCESS_ERROR;
-
- PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_CHANNEL_SWITCH, process_status, NULL, 0);
-
- pHalmac_adapter->halmac_state.scan_state_set.process_status = process_status;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "scan status : %X\n", process_status);
-
- return HALMAC_RET_SUCCESS;
-}
-
-
-HALMAC_RET_STATUS
-halmac_parse_psd_data_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pC2h_buf,
- IN u32 c2h_size
-)
-{
- u8 segment_id = 0, segment_size = 0, h2c_seq = 0;
- u16 total_size;
- VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- HALMAC_CMD_PROCESS_STATUS process_status = HALMAC_CMD_PROCESS_UNDEFINE;
- PHALMAC_PSD_STATE_SET pPsd_set = &(pHalmac_adapter->halmac_state.psd_set);
-
- h2c_seq = (u8)PSD_DATA_GET_H2C_SEQ(pC2h_buf);
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "Seq num : h2c -> %d c2h -> %d\n", pPsd_set->seq_num, h2c_seq);
- if (h2c_seq != pPsd_set->seq_num) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Seq num mismactch : h2c -> %d c2h -> %d\n", pPsd_set->seq_num, h2c_seq);
- return HALMAC_RET_SUCCESS;
- }
-
- if (HALMAC_CMD_PROCESS_SENDING != pPsd_set->process_status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Not in HALMAC_CMD_PROCESS_SENDING\n");
- return HALMAC_RET_SUCCESS;
- }
-
- total_size = (u16)PSD_DATA_GET_TOTAL_SIZE(pC2h_buf);
- segment_id = (u8)PSD_DATA_GET_SEGMENT_ID(pC2h_buf);
- segment_size = (u8)PSD_DATA_GET_SEGMENT_SIZE(pC2h_buf);
- pPsd_set->data_size = total_size;
-
- if (NULL == pPsd_set->pData)
- pPsd_set->pData = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, pPsd_set->data_size);
-
- if (0 == segment_id)
- pPsd_set->segment_size = segment_size;
-
- PLATFORM_RTL_MEMCPY(pDriver_adapter, pPsd_set->pData + segment_id * pPsd_set->segment_size, pC2h_buf + HALMAC_C2H_DATA_OFFSET_88XX, segment_size);
-
- if (_FALSE == PSD_DATA_GET_END_SEGMENT(pC2h_buf))
- return HALMAC_RET_SUCCESS;
-
- process_status = HALMAC_CMD_PROCESS_DONE;
- pPsd_set->process_status = process_status;
-
- PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_PSD, process_status, pPsd_set->pData, pPsd_set->data_size);
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_parse_efuse_data_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pC2h_buf,
- IN u32 c2h_size
-)
-{
- u8 segment_id = 0, segment_size = 0, h2c_seq = 0;
- u8 *pEeprom_map = NULL;
- u32 eeprom_size = pHalmac_adapter->hw_config_info.eeprom_size;
- u8 h2c_return_code = 0;
- VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- HALMAC_CMD_PROCESS_STATUS process_status = HALMAC_CMD_PROCESS_UNDEFINE;
-
- pEeprom_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, eeprom_size);
- if (NULL == pEeprom_map) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac allocate local eeprom map Fail!!\n");
- return HALMAC_RET_MALLOC_FAIL;
- }
- PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_map, 0xFF, eeprom_size);
-
- h2c_seq = (u8)EFUSE_DATA_GET_H2C_SEQ(pC2h_buf);
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "Seq num : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.efuse_state_set.seq_num, h2c_seq);
- if (h2c_seq != pHalmac_adapter->halmac_state.efuse_state_set.seq_num) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Seq num mismactch : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.efuse_state_set.seq_num, h2c_seq);
- return HALMAC_RET_SUCCESS;
- }
-
- if (HALMAC_CMD_PROCESS_SENDING != pHalmac_adapter->halmac_state.efuse_state_set.process_status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Not in HALMAC_CMD_PROCESS_SENDING\n");
- return HALMAC_RET_SUCCESS;
- }
-
- pHalmac_adapter->halmac_state.efuse_state_set.fw_return_code = h2c_return_code;
- segment_id = (u8)EFUSE_DATA_GET_SEGMENT_ID(pC2h_buf);
- segment_size = (u8)EFUSE_DATA_GET_SEGMENT_SIZE(pC2h_buf);
- if (0 == segment_id)
- pHalmac_adapter->efuse_segment_size = segment_size;
-
- PLATFORM_MUTEX_LOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex));
- PLATFORM_RTL_MEMCPY(pDriver_adapter, pHalmac_adapter->pHalEfuse_map + segment_id * pHalmac_adapter->efuse_segment_size, \
- pC2h_buf + HALMAC_C2H_DATA_OFFSET_88XX, segment_size);
- PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex));
-
- if (_FALSE == EFUSE_DATA_GET_END_SEGMENT(pC2h_buf))
- return HALMAC_RET_SUCCESS;
-
- if (HALMAC_H2C_RETURN_SUCCESS == (HALMAC_H2C_RETURN_CODE)h2c_return_code) {
- process_status = HALMAC_CMD_PROCESS_DONE;
- pHalmac_adapter->halmac_state.efuse_state_set.process_status = process_status;
-
- PLATFORM_MUTEX_LOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex));
- pHalmac_adapter->hal_efuse_map_valid = _TRUE;
- PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex));
-
- if (1 == pHalmac_adapter->event_trigger.physical_efuse_map) {
- PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE, process_status, pHalmac_adapter->pHalEfuse_map, pHalmac_adapter->hw_config_info.efuse_size);
- pHalmac_adapter->event_trigger.physical_efuse_map = 0;
- }
-
- if (1 == pHalmac_adapter->event_trigger.logical_efuse_map) {
- if (HALMAC_RET_SUCCESS != halmac_eeprom_parser_88xx(pHalmac_adapter, pHalmac_adapter->pHalEfuse_map, pEeprom_map))
- return HALMAC_RET_EEPROM_PARSING_FAIL;
- PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_DUMP_LOGICAL_EFUSE, process_status, pEeprom_map, eeprom_size);
- pHalmac_adapter->event_trigger.logical_efuse_map = 0;
- }
- } else {
- process_status = HALMAC_CMD_PROCESS_ERROR;
- pHalmac_adapter->halmac_state.efuse_state_set.process_status = process_status;
-
- if (1 == pHalmac_adapter->event_trigger.physical_efuse_map) {
- PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE, process_status, &(pHalmac_adapter->halmac_state.efuse_state_set.fw_return_code), 1);
- pHalmac_adapter->event_trigger.physical_efuse_map = 0;
- }
-
- if (1 == pHalmac_adapter->event_trigger.logical_efuse_map) {
- if (HALMAC_RET_SUCCESS != halmac_eeprom_parser_88xx(pHalmac_adapter, pHalmac_adapter->pHalEfuse_map, pEeprom_map))
- return HALMAC_RET_EEPROM_PARSING_FAIL;
- PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_DUMP_LOGICAL_EFUSE, process_status, &(pHalmac_adapter->halmac_state.efuse_state_set.fw_return_code), 1);
- pHalmac_adapter->event_trigger.logical_efuse_map = 0;
- }
- }
-
- PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size);
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_parse_h2c_ack_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pC2h_buf,
- IN u32 c2h_size
-)
-{
- u8 h2c_cmd_id, h2c_sub_cmd_id;
- u8 h2c_seq = 0, offset = 0, shift = 0;
- u8 h2c_return_code;
- VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- HALMAC_CMD_PROCESS_STATUS process_status = HALMAC_CMD_PROCESS_UNDEFINE;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
-
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "Ack for C2H!!\n");
-
- h2c_return_code = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(pC2h_buf);
- if (HALMAC_H2C_RETURN_SUCCESS != (HALMAC_H2C_RETURN_CODE)h2c_return_code)
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "C2H_PKT Status Error!! Status = %d\n", h2c_return_code);
-
- h2c_cmd_id = (u8)H2C_ACK_HDR_GET_H2C_CMD_ID(pC2h_buf);
-
- if (0xFF != h2c_cmd_id) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "original h2c ack is not handled!!\n");
- status = HALMAC_RET_C2H_NOT_HANDLED;
- } else {
- h2c_sub_cmd_id = (u8)H2C_ACK_HDR_GET_H2C_SUB_CMD_ID(pC2h_buf);
-
- switch (h2c_sub_cmd_id) {
- case H2C_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK:
- break;
- case H2C_SUB_CMD_ID_CFG_PARAMETER_ACK:
- status = halmac_parse_h2c_ack_cfg_para_88xx(pHalmac_adapter, pC2h_buf, c2h_size);
- break;
- case H2C_SUB_CMD_ID_UPDATE_PACKET_ACK:
- status = halmac_parse_h2c_ack_update_packet_88xx(pHalmac_adapter, pC2h_buf, c2h_size);
- break;
- case H2C_SUB_CMD_ID_UPDATE_DATAPACK_ACK:
- status = halmac_parse_h2c_ack_update_datapack_88xx(pHalmac_adapter, pC2h_buf, c2h_size);
- break;
- case H2C_SUB_CMD_ID_RUN_DATAPACK_ACK:
- status = halmac_parse_h2c_ack_run_datapack_88xx(pHalmac_adapter, pC2h_buf, c2h_size);
- break;
- case H2C_SUB_CMD_ID_CHANNEL_SWITCH_ACK:
- status = halmac_parse_h2c_ack_channel_switch_88xx(pHalmac_adapter, pC2h_buf, c2h_size);
- break;
- case H2C_SUB_CMD_ID_IQK_ACK:
- status = halmac_parse_h2c_ack_iqk_88xx(pHalmac_adapter, pC2h_buf, c2h_size);
- break;
- case H2C_SUB_CMD_ID_POWER_TRACKING_ACK:
- status = halmac_parse_h2c_ack_power_tracking_88xx(pHalmac_adapter, pC2h_buf, c2h_size);
- break;
- case H2C_SUB_CMD_ID_PSD_ACK:
- break;
- default:
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "h2c_sub_cmd_id switch case out of boundary!!\n");
- status = HALMAC_RET_C2H_NOT_HANDLED;
- break;
- }
- }
-
- return status;
-}
-
-HALMAC_RET_STATUS
-halmac_parse_h2c_ack_cfg_para_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pC2h_buf,
- IN u32 c2h_size
-)
-{
- u8 h2c_seq = 0;
- u8 h2c_return_code;
- u32 offset_accu = 0, value_accu = 0;
- VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- HALMAC_CMD_PROCESS_STATUS process_status = HALMAC_CMD_PROCESS_UNDEFINE;
-
- h2c_seq = (u8)H2C_ACK_HDR_GET_H2C_SEQ(pC2h_buf);
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "Seq num : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.cfg_para_state_set.seq_num, h2c_seq);
- if (h2c_seq != pHalmac_adapter->halmac_state.cfg_para_state_set.seq_num) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Seq num mismactch : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.cfg_para_state_set.seq_num, h2c_seq);
- return HALMAC_RET_SUCCESS;
- }
-
- if (HALMAC_CMD_PROCESS_SENDING != pHalmac_adapter->halmac_state.cfg_para_state_set.process_status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Not in HALMAC_CMD_PROCESS_SENDING\n");
- return HALMAC_RET_SUCCESS;
- }
-
- h2c_return_code = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(pC2h_buf);
- pHalmac_adapter->halmac_state.cfg_para_state_set.fw_return_code = h2c_return_code;
- offset_accu = CFG_PARAMETER_ACK_GET_OFFSET_ACCUMULATION(pC2h_buf);
- value_accu = CFG_PARAMETER_ACK_GET_VALUE_ACCUMULATION(pC2h_buf);
-
- if ((offset_accu != pHalmac_adapter->config_para_info.offset_accumulation) || (value_accu != pHalmac_adapter->config_para_info.value_accumulation)) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[C2H]offset_accu : %x, value_accu : %x!!\n", offset_accu, value_accu);
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[Adapter]offset_accu : %x, value_accu : %x!!\n", pHalmac_adapter->config_para_info.offset_accumulation, pHalmac_adapter->config_para_info.value_accumulation);
- process_status = HALMAC_CMD_PROCESS_ERROR;
- }
-
- if ((HALMAC_H2C_RETURN_SUCCESS == (HALMAC_H2C_RETURN_CODE)h2c_return_code) && (HALMAC_CMD_PROCESS_ERROR != process_status)) {
- process_status = HALMAC_CMD_PROCESS_DONE;
- pHalmac_adapter->halmac_state.cfg_para_state_set.process_status = process_status;
- PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_CFG_PARA, process_status, NULL, 0);
- } else {
- process_status = HALMAC_CMD_PROCESS_ERROR;
- pHalmac_adapter->halmac_state.cfg_para_state_set.process_status = process_status;
- PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_CFG_PARA, process_status, &(pHalmac_adapter->halmac_state.cfg_para_state_set.fw_return_code), 1);
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-
-HALMAC_RET_STATUS
-halmac_parse_h2c_ack_update_packet_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pC2h_buf,
- IN u32 c2h_size
-)
-{
- u8 h2c_seq = 0;
- u8 h2c_return_code;
- VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- HALMAC_CMD_PROCESS_STATUS process_status = HALMAC_CMD_PROCESS_UNDEFINE;
-
- h2c_seq = (u8)H2C_ACK_HDR_GET_H2C_SEQ(pC2h_buf);
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "Seq num : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.update_packet_set.seq_num, h2c_seq);
- if (h2c_seq != pHalmac_adapter->halmac_state.update_packet_set.seq_num) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Seq num mismactch : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.update_packet_set.seq_num, h2c_seq);
- return HALMAC_RET_SUCCESS;
- }
-
- if (HALMAC_CMD_PROCESS_SENDING != pHalmac_adapter->halmac_state.update_packet_set.process_status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Not in HALMAC_CMD_PROCESS_SENDING\n");
- return HALMAC_RET_SUCCESS;
- }
-
- h2c_return_code = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(pC2h_buf);
- pHalmac_adapter->halmac_state.update_packet_set.fw_return_code = h2c_return_code;
-
- if (HALMAC_H2C_RETURN_SUCCESS == (HALMAC_H2C_RETURN_CODE)h2c_return_code) {
- process_status = HALMAC_CMD_PROCESS_DONE;
- pHalmac_adapter->halmac_state.update_packet_set.process_status = process_status;
- PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_UPDATE_PACKET, process_status, NULL, 0);
- } else {
- process_status = HALMAC_CMD_PROCESS_ERROR;
- pHalmac_adapter->halmac_state.update_packet_set.process_status = process_status;
- PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_UPDATE_PACKET, process_status, &(pHalmac_adapter->halmac_state.update_packet_set.fw_return_code), 1);
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_parse_h2c_ack_update_datapack_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pC2h_buf,
- IN u32 c2h_size
-)
-{
- VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- HALMAC_CMD_PROCESS_STATUS process_status = HALMAC_CMD_PROCESS_UNDEFINE;
-
- PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_UPDATE_DATAPACK, process_status, NULL, 0);
-
- return HALMAC_RET_SUCCESS;
-}
-
-
-HALMAC_RET_STATUS
-halmac_parse_h2c_ack_run_datapack_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pC2h_buf,
- IN u32 c2h_size
-)
-{
- VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- HALMAC_CMD_PROCESS_STATUS process_status = HALMAC_CMD_PROCESS_UNDEFINE;
-
- PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_RUN_DATAPACK, process_status, NULL, 0);
-
- return HALMAC_RET_SUCCESS;
-}
-
-
-HALMAC_RET_STATUS
-halmac_parse_h2c_ack_channel_switch_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pC2h_buf,
- IN u32 c2h_size
-)
-{
- u8 h2c_seq = 0;
- u8 h2c_return_code;
- VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- HALMAC_CMD_PROCESS_STATUS process_status = HALMAC_CMD_PROCESS_UNDEFINE;
-
- h2c_seq = (u8)H2C_ACK_HDR_GET_H2C_SEQ(pC2h_buf);
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "Seq num : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.scan_state_set.seq_num, h2c_seq);
- if (h2c_seq != pHalmac_adapter->halmac_state.scan_state_set.seq_num) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Seq num mismactch : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.scan_state_set.seq_num, h2c_seq);
- return HALMAC_RET_SUCCESS;
- }
-
- if (HALMAC_CMD_PROCESS_SENDING != pHalmac_adapter->halmac_state.scan_state_set.process_status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Not in HALMAC_CMD_PROCESS_SENDING\n");
- return HALMAC_RET_SUCCESS;
- }
-
- h2c_return_code = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(pC2h_buf);
- pHalmac_adapter->halmac_state.scan_state_set.fw_return_code = h2c_return_code;
-
- if (HALMAC_H2C_RETURN_SUCCESS == (HALMAC_H2C_RETURN_CODE)h2c_return_code) {
- process_status = HALMAC_CMD_PROCESS_RCVD;
- pHalmac_adapter->halmac_state.scan_state_set.process_status = process_status;
- PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_CHANNEL_SWITCH, process_status, NULL, 0);
- } else {
- process_status = HALMAC_CMD_PROCESS_ERROR;
- pHalmac_adapter->halmac_state.scan_state_set.process_status = process_status;
- PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_CHANNEL_SWITCH, process_status, &(pHalmac_adapter->halmac_state.scan_state_set.fw_return_code), 1);
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_parse_h2c_ack_iqk_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pC2h_buf,
- IN u32 c2h_size
-)
-{
- u8 h2c_seq = 0;
- u8 h2c_return_code;
- VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- HALMAC_CMD_PROCESS_STATUS process_status = HALMAC_CMD_PROCESS_UNDEFINE;
-
- h2c_seq = (u8)H2C_ACK_HDR_GET_H2C_SEQ(pC2h_buf);
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "Seq num : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.iqk_set.seq_num, h2c_seq);
- if (h2c_seq != pHalmac_adapter->halmac_state.iqk_set.seq_num) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Seq num mismactch : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.iqk_set.seq_num, h2c_seq);
- return HALMAC_RET_SUCCESS;
- }
-
- if (HALMAC_CMD_PROCESS_SENDING != pHalmac_adapter->halmac_state.iqk_set.process_status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Not in HALMAC_CMD_PROCESS_SENDING\n");
- return HALMAC_RET_SUCCESS;
- }
-
- h2c_return_code = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(pC2h_buf);
- pHalmac_adapter->halmac_state.iqk_set.fw_return_code = h2c_return_code;
-
- if (HALMAC_H2C_RETURN_SUCCESS == (HALMAC_H2C_RETURN_CODE)h2c_return_code) {
- process_status = HALMAC_CMD_PROCESS_DONE;
- pHalmac_adapter->halmac_state.iqk_set.process_status = process_status;
- PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_IQK, process_status, NULL, 0);
- } else {
- process_status = HALMAC_CMD_PROCESS_ERROR;
- pHalmac_adapter->halmac_state.iqk_set.process_status = process_status;
- PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_IQK, process_status, &(pHalmac_adapter->halmac_state.iqk_set.fw_return_code), 1);
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_parse_h2c_ack_power_tracking_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pC2h_buf,
- IN u32 c2h_size
-)
-{
- u8 h2c_seq = 0;
- u8 h2c_return_code;
- VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- HALMAC_CMD_PROCESS_STATUS process_status = HALMAC_CMD_PROCESS_UNDEFINE;
-
- h2c_seq = (u8)H2C_ACK_HDR_GET_H2C_SEQ(pC2h_buf);
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "Seq num : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.power_tracking_set.seq_num, h2c_seq);
- if (h2c_seq != pHalmac_adapter->halmac_state.power_tracking_set.seq_num) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Seq num mismactch : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.power_tracking_set.seq_num, h2c_seq);
- return HALMAC_RET_SUCCESS;
- }
-
- if (HALMAC_CMD_PROCESS_SENDING != pHalmac_adapter->halmac_state.power_tracking_set.process_status) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Not in HALMAC_CMD_PROCESS_SENDING\n");
- return HALMAC_RET_SUCCESS;
- }
-
- h2c_return_code = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(pC2h_buf);
- pHalmac_adapter->halmac_state.power_tracking_set.fw_return_code = h2c_return_code;
-
- if (HALMAC_H2C_RETURN_SUCCESS == (HALMAC_H2C_RETURN_CODE)h2c_return_code) {
- process_status = HALMAC_CMD_PROCESS_DONE;
- pHalmac_adapter->halmac_state.power_tracking_set.process_status = process_status;
- PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_POWER_TRACKING, process_status, NULL, 0);
- } else {
- process_status = HALMAC_CMD_PROCESS_ERROR;
- pHalmac_adapter->halmac_state.power_tracking_set.process_status = process_status;
- PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_POWER_TRACKING, process_status, &(pHalmac_adapter->halmac_state.power_tracking_set.fw_return_code), 1);
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_convert_to_sdio_bus_offset_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- INOUT u32 *halmac_offset
-)
-{
- VOID *pDriver_adapter = NULL;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- switch ((*halmac_offset) & 0xFFFF0000) {
- case WLAN_IOREG_OFFSET:
- *halmac_offset = (WLAN_IOREG_DEVICE_ID << 13) | (*halmac_offset & HALMAC_WLAN_IOREG_MSK);
- break;
- case SDIO_LOCAL_OFFSET:
- *halmac_offset = (SDIO_LOCAL_DEVICE_ID << 13) | (*halmac_offset & HALMAC_SDIO_LOCAL_MSK);
- break;
- default:
- *halmac_offset = 0xFFFFFFFF;
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Unknown base address!!\n");
- return HALMAC_RET_CONVERT_SDIO_OFFSET_FAIL;
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_update_sdio_free_page_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-)
-{
- u32 free_page = 0, free_page2 = 0, oqt_free_page = 0;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
- PHALMAC_SDIO_FREE_SPACE pSdio_free_space;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_update_sdio_free_page_88xx ==========>\n");
-
- pSdio_free_space = &(pHalmac_adapter->sdio_free_space);
-
- free_page = HALMAC_REG_READ_32(pHalmac_adapter, REG_SDIO_FREE_TXPG);
- free_page2 = HALMAC_REG_READ_32(pHalmac_adapter, REG_SDIO_FREE_TXPG2);
-
- pSdio_free_space->high_queue_number = (u16)BIT_GET_HIQ_FREEPG_V1(free_page);
- pSdio_free_space->normal_queue_number = (u16)BIT_GET_MID_FREEPG_V1(free_page);
- pSdio_free_space->low_queue_number = (u16)BIT_GET_LOW_FREEPG_V1(free_page2);
- pSdio_free_space->public_queue_number = (u16)BIT_GET_PUB_FREEPG_V1(free_page2);
- pSdio_free_space->extra_queue_number = (u16)BIT_GET_EXQ_FREEPG_V1(oqt_free_page);
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_update_sdio_free_page_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_update_oqt_free_space_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
- PHALMAC_SDIO_FREE_SPACE pSdio_free_space;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_update_oqt_free_space_88xx ==========>\n");
-
- pSdio_free_space = &(pHalmac_adapter->sdio_free_space);
-
- pSdio_free_space->ac_oqt_number = HALMAC_REG_READ_8(pHalmac_adapter, REG_SDIO_OQT_FREE_TXPG_V1 + 2);
- /* pSdio_free_space->non_ac_oqt_number = (u8)BIT_GET_NOAC_OQT_FREEPG_V1(oqt_free_page); */
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_update_oqt_free_space_88xx <==========\n");
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_EFUSE_CMD_CONSTRUCT_STATE
-halmac_query_efuse_curr_state_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-)
-{
- return pHalmac_adapter->halmac_state.efuse_state_set.efuse_cmd_construct_state;
-}
-
-HALMAC_RET_STATUS
-halmac_transition_efuse_state_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_EFUSE_CMD_CONSTRUCT_STATE dest_state
-)
-{
- PHALMAC_EFUSE_STATE_SET pEfuse_state = &(pHalmac_adapter->halmac_state.efuse_state_set);
-
- if ((HALMAC_EFUSE_CMD_CONSTRUCT_IDLE != pEfuse_state->efuse_cmd_construct_state) \
- && (HALMAC_EFUSE_CMD_CONSTRUCT_BUSY != pEfuse_state->efuse_cmd_construct_state) \
- && (HALMAC_EFUSE_CMD_CONSTRUCT_H2C_SENT != pEfuse_state->efuse_cmd_construct_state))
- return HALMAC_RET_ERROR_STATE;
-
- if (pEfuse_state->efuse_cmd_construct_state == dest_state)
- return HALMAC_RET_ERROR_STATE;
-
- if (HALMAC_EFUSE_CMD_CONSTRUCT_BUSY == dest_state) {
- if (HALMAC_EFUSE_CMD_CONSTRUCT_H2C_SENT == pEfuse_state->efuse_cmd_construct_state)
- return HALMAC_RET_ERROR_STATE;
- } else if (HALMAC_EFUSE_CMD_CONSTRUCT_H2C_SENT == dest_state) {
- if (HALMAC_EFUSE_CMD_CONSTRUCT_IDLE == pEfuse_state->efuse_cmd_construct_state)
- return HALMAC_RET_ERROR_STATE;
- }
-
- pEfuse_state->efuse_cmd_construct_state = dest_state;
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_CFG_PARA_CMD_CONSTRUCT_STATE
-halmac_query_cfg_para_curr_state_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-)
-{
- return pHalmac_adapter->halmac_state.cfg_para_state_set.cfg_para_cmd_construct_state;
-}
-
-HALMAC_RET_STATUS
-halmac_transition_cfg_para_state_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_CFG_PARA_CMD_CONSTRUCT_STATE dest_state
-)
-{
- PHALMAC_CFG_PARA_STATE_SET pCfg_para = &(pHalmac_adapter->halmac_state.cfg_para_state_set);
-
- if ((HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE != pCfg_para->cfg_para_cmd_construct_state) && \
- (HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING != pCfg_para->cfg_para_cmd_construct_state) && \
- (HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT != pCfg_para->cfg_para_cmd_construct_state))
- return HALMAC_RET_ERROR_STATE;
-
- if (HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE == dest_state) {
- if (HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING == pCfg_para->cfg_para_cmd_construct_state)
- return HALMAC_RET_ERROR_STATE;
- } else if (HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING == dest_state) {
- if (HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT == pCfg_para->cfg_para_cmd_construct_state)
- return HALMAC_RET_ERROR_STATE;
- } else if (HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT == dest_state) {
- if ((HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE == pCfg_para->cfg_para_cmd_construct_state) \
- || (HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT == pCfg_para->cfg_para_cmd_construct_state))
- return HALMAC_RET_ERROR_STATE;
- }
-
- pCfg_para->cfg_para_cmd_construct_state = dest_state;
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_SCAN_CMD_CONSTRUCT_STATE
-halmac_query_scan_curr_state_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-)
-{
- return pHalmac_adapter->halmac_state.scan_state_set.scan_cmd_construct_state;
-}
-
-HALMAC_RET_STATUS
-halmac_transition_scan_state_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_SCAN_CMD_CONSTRUCT_STATE dest_state
-)
-{
- PHALMAC_SCAN_STATE_SET pScan = &(pHalmac_adapter->halmac_state.scan_state_set);
-
- if ((pScan->scan_cmd_construct_state > HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT) || (pScan->scan_cmd_construct_state < HALMAC_SCAN_CMD_CONSTRUCT_IDLE))
- return HALMAC_RET_ERROR_STATE;
-
- if (HALMAC_SCAN_CMD_CONSTRUCT_IDLE == dest_state) {
- if ((HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED == pScan->scan_cmd_construct_state) ||
- (HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING == pScan->scan_cmd_construct_state))
- return HALMAC_RET_ERROR_STATE;
- } else if (HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED == dest_state) {
- if (HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT == pScan->scan_cmd_construct_state)
- return HALMAC_RET_ERROR_STATE;
- } else if (HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING == dest_state) {
- if ((HALMAC_SCAN_CMD_CONSTRUCT_IDLE == pScan->scan_cmd_construct_state) ||
- (HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT == pScan->scan_cmd_construct_state))
- return HALMAC_RET_ERROR_STATE;
- } else if (HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT == dest_state) {
- if ((HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING != pScan->scan_cmd_construct_state) &&
- (HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED != pScan->scan_cmd_construct_state))
- return HALMAC_RET_ERROR_STATE;
- }
-
- pScan->scan_cmd_construct_state = dest_state;
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_query_cfg_para_status_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status,
- INOUT u8 *data,
- INOUT u32 *size
-)
-{
- PHALMAC_CFG_PARA_STATE_SET pCfg_para_state_set = &(pHalmac_adapter->halmac_state.cfg_para_state_set);
-
- *pProcess_status = pCfg_para_state_set->process_status;
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_query_dump_physical_efuse_status_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status,
- INOUT u8 *data,
- INOUT u32 *size
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_EFUSE_STATE_SET pEfuse_state_set = &(pHalmac_adapter->halmac_state.efuse_state_set);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- *pProcess_status = pEfuse_state_set->process_status;
-
- if (NULL == data)
- return HALMAC_RET_NULL_POINTER;
-
- if (NULL == size)
- return HALMAC_RET_NULL_POINTER;
-
- if (HALMAC_CMD_PROCESS_DONE == *pProcess_status) {
- if (*size < pHalmac_adapter->hw_config_info.efuse_size) {
- *size = pHalmac_adapter->hw_config_info.efuse_size;
- return HALMAC_RET_BUFFER_TOO_SMALL;
- }
-
- *size = pHalmac_adapter->hw_config_info.efuse_size;
- PLATFORM_RTL_MEMCPY(pDriver_adapter, data, pHalmac_adapter->pHalEfuse_map, *size);
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_query_dump_logical_efuse_status_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status,
- INOUT u8 *data,
- INOUT u32 *size
-)
-{
- u8 *pEeprom_map = NULL;
- u32 eeprom_size = pHalmac_adapter->hw_config_info.eeprom_size;
- VOID *pDriver_adapter = NULL;
- PHALMAC_EFUSE_STATE_SET pEfuse_state_set = &(pHalmac_adapter->halmac_state.efuse_state_set);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- *pProcess_status = pEfuse_state_set->process_status;
-
- pEeprom_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, eeprom_size);
- if (NULL == pEeprom_map) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac allocate local eeprom map Fail!!\n");
- return HALMAC_RET_MALLOC_FAIL;
- }
- PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_map, 0xFF, eeprom_size);
-
- if (NULL == data)
- return HALMAC_RET_NULL_POINTER;
-
- if (NULL == size)
- return HALMAC_RET_NULL_POINTER;
-
- if (HALMAC_CMD_PROCESS_DONE == *pProcess_status) {
- if (*size < eeprom_size) {
- *size = eeprom_size;
- return HALMAC_RET_BUFFER_TOO_SMALL;
- }
-
- *size = eeprom_size;
- if (HALMAC_RET_SUCCESS != halmac_eeprom_parser_88xx(pHalmac_adapter, pHalmac_adapter->pHalEfuse_map, pEeprom_map))
- return HALMAC_RET_EEPROM_PARSING_FAIL;
- PLATFORM_RTL_MEMCPY(pDriver_adapter, data, pEeprom_map, *size);
- }
-
- PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size);
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_query_channel_switch_status_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status,
- INOUT u8 *data,
- INOUT u32 *size
-)
-{
- PHALMAC_SCAN_STATE_SET pScan_state_set = &(pHalmac_adapter->halmac_state.scan_state_set);
-
- *pProcess_status = pScan_state_set->process_status;
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_query_update_packet_status_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status,
- INOUT u8 *data,
- INOUT u32 *size
-)
-{
- PHALMAC_UPDATE_PACKET_STATE_SET pUpdate_packet_set = &(pHalmac_adapter->halmac_state.update_packet_set);
-
- *pProcess_status = pUpdate_packet_set->process_status;
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_query_iqk_status_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status,
- INOUT u8 *data,
- INOUT u32 *size
-)
-{
- PHALMAC_IQK_STATE_SET pIqk_set = &(pHalmac_adapter->halmac_state.iqk_set);
-
- *pProcess_status = pIqk_set->process_status;
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_query_power_tracking_status_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status,
- INOUT u8 *data,
- INOUT u32 *size
-)
-{
- PHALMAC_POWER_TRACKING_STATE_SET pPower_tracking_state_set = &(pHalmac_adapter->halmac_state.power_tracking_set);;
-
- *pProcess_status = pPower_tracking_state_set->process_status;
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_query_psd_status_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status,
- INOUT u8 *data,
- INOUT u32 *size
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_PSD_STATE_SET pPsd_set = &(pHalmac_adapter->halmac_state.psd_set);
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- *pProcess_status = pPsd_set->process_status;
-
- if (NULL == data)
- return HALMAC_RET_NULL_POINTER;
-
- if (NULL == size)
- return HALMAC_RET_NULL_POINTER;
-
- if (HALMAC_CMD_PROCESS_DONE == *pProcess_status) {
- if (*size < pPsd_set->data_size) {
- *size = pPsd_set->data_size;
- return HALMAC_RET_BUFFER_TOO_SMALL;
- }
-
- *size = pPsd_set->data_size;
- PLATFORM_RTL_MEMCPY(pDriver_adapter, data, pPsd_set->pData, *size);
- }
-
- return HALMAC_RET_SUCCESS;
-}
-
-HALMAC_RET_STATUS
-halmac_verify_io_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-)
-{
- u8 value8, wvalue8;
- u32 value32, value32_2, wvalue32;
- u32 halmac_offset;
- VOID *pDriver_adapter = NULL;
- HALMAC_RET_STATUS ret_status = HALMAC_RET_SUCCESS;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface) {
- halmac_offset = REG_PAGE5_DUMMY;
- if (0 == (halmac_offset & 0xFFFF0000))
- halmac_offset |= WLAN_IOREG_OFFSET;
-
- halmac_convert_to_sdio_bus_offset_88xx(pHalmac_adapter, &halmac_offset);
-
- /* Verify CMD52 R/W */
- wvalue8 = 0xab;
- PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset, wvalue8);
-
- value8 = PLATFORM_SDIO_CMD52_READ(pDriver_adapter, halmac_offset);
-
- if (value8 != wvalue8) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "cmd52 r/w fail write = %X read = %X\n", wvalue8, value8);
- ret_status = HALMAC_RET_PLATFORM_API_INCORRECT;
- } else {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "cmd52 r/w ok\n");
- }
-
- /* Verify CMD53 R/W */
- PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset, 0xaa);
- PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset + 1, 0xbb);
- PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset + 2, 0xcc);
- PLATFORM_SDIO_CMD52_WRITE(pDriver_adapter, halmac_offset + 3, 0xdd);
-
- value32 = PLATFORM_SDIO_CMD53_READ_32(pDriver_adapter, halmac_offset);
-
- if (0xddccbbaa != value32) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "cmd53 r fail : read = %X\n");
- ret_status = HALMAC_RET_PLATFORM_API_INCORRECT;
- } else {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "cmd53 r ok\n");
- }
-
- wvalue32 = 0x11223344;
- PLATFORM_SDIO_CMD53_WRITE_32(pDriver_adapter, halmac_offset, wvalue32);
-
- value32 = PLATFORM_SDIO_CMD53_READ_32(pDriver_adapter, halmac_offset);
-
- if (value32 != wvalue32) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "cmd53 w fail\n");
- ret_status = HALMAC_RET_PLATFORM_API_INCORRECT;
- } else {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "cmd53 w ok\n");
- }
-
- value32 = PLATFORM_SDIO_CMD53_READ_32(pDriver_adapter, halmac_offset + 2); /* value32 should be 0x33441122 */
-
- wvalue32 = 0x11225566;
- PLATFORM_SDIO_CMD53_WRITE_32(pDriver_adapter, halmac_offset, wvalue32);
-
- value32_2 = PLATFORM_SDIO_CMD53_READ_32(pDriver_adapter, halmac_offset + 2); /* value32 should be 0x55661122 */
- if (value32_2 == value32) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "cmd52 is used for HAL_SDIO_CMD53_READ_32\n");
- ret_status = HALMAC_RET_PLATFORM_API_INCORRECT;
- } else {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "cmd53 is correctly used\n");
- }
- } else {
- wvalue32 = 0x77665511;
- PLATFORM_REG_WRITE_32(pDriver_adapter, REG_PAGE5_DUMMY, wvalue32);
-
- value32 = PLATFORM_REG_READ_32(pDriver_adapter, REG_PAGE5_DUMMY);
- if (value32 != wvalue32) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "reg rw\n");
- ret_status = HALMAC_RET_PLATFORM_API_INCORRECT;
- } else {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "reg rw ok\n");
- }
- }
-
- return ret_status;
-}
-
-HALMAC_RET_STATUS
-halmac_verify_send_rsvd_page_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-)
-{
- u8 *rsvd_buf = NULL;
- u8 *rsvd_page = NULL;
- u32 i;
- u32 h2c_pkt_verify_size = 64, h2c_pkt_verify_payload = 0xab;
- VOID *pDriver_adapter = NULL;
- PHALMAC_API pHalmac_api;
- HALMAC_RET_STATUS ret_status = HALMAC_RET_SUCCESS;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- rsvd_buf = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, h2c_pkt_verify_size);
-
- if (NULL == rsvd_buf) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "rsvd buffer malloc fail!!\n");
- return HALMAC_RET_MALLOC_FAIL;
- }
-
- rsvd_page = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, h2c_pkt_verify_size + pHalmac_adapter->hw_config_info.txdesc_size);
-
- if (NULL == rsvd_page) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "rsvd page malloc fail!!\n");
- return HALMAC_RET_MALLOC_FAIL;
- }
-
- PLATFORM_RTL_MEMSET(pDriver_adapter, rsvd_buf, (u8)h2c_pkt_verify_payload, h2c_pkt_verify_size);
-
- ret_status = halmac_download_rsvd_page_88xx(pHalmac_adapter, rsvd_buf, h2c_pkt_verify_size);
-
- if (HALMAC_RET_SUCCESS != ret_status)
- return ret_status;
-
- PLATFORM_RTL_MEMSET(pDriver_adapter, rsvd_page, 0x00, h2c_pkt_verify_size + pHalmac_adapter->hw_config_info.txdesc_size);
-
- ret_status = halmac_dump_fifo_88xx(pHalmac_adapter, HAL_FIFO_SEL_RSVD_PAGE, rsvd_page, h2c_pkt_verify_size + pHalmac_adapter->hw_config_info.txdesc_size);
-
- if (HALMAC_RET_SUCCESS != ret_status)
- return ret_status;
-
- for (i = 0; i < h2c_pkt_verify_size; i++) {
- if (*(rsvd_buf + i) != *(rsvd_page + (i + pHalmac_adapter->hw_config_info.txdesc_size))) {
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Compare RSVD page Fail\n");
- ret_status = HALMAC_RET_PLATFORM_API_INCORRECT;
- }
- }
-
- PLATFORM_RTL_FREE(pDriver_adapter, rsvd_buf, h2c_pkt_verify_size);
- PLATFORM_RTL_FREE(pDriver_adapter, rsvd_page, h2c_pkt_verify_size + pHalmac_adapter->hw_config_info.txdesc_size);
- rsvd_buf = NULL;
- rsvd_page = NULL;
-
- return ret_status;
-}
-
-VOID
-halmac_power_save_cb_88xx(
- IN VOID *CbData
-)
-{
- VOID *pDriver_adapter = NULL;
- PHALMAC_ADAPTER pHalmac_adapter = (PHALMAC_ADAPTER)NULL;
-
- pHalmac_adapter = (PHALMAC_ADAPTER)CbData;
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
-
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_power_save_cb_88xx\n");
-}
-
-HALMAC_RET_STATUS
-halmac_buffer_read_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 offset,
- IN u32 size,
- IN HAL_FIFO_SEL halmac_fifo_sel,
- OUT u8 *pFifo_map
-)
-{
- u32 start_page, value_read;
- u32 i, counter = 0, residue;
- PHALMAC_API pHalmac_api;
-
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- if (HAL_FIFO_SEL_RSVD_PAGE == halmac_fifo_sel)
- offset = offset + (pHalmac_adapter->txff_allocation.rsvd_pg_bndy << 7);
-
- start_page = offset >> 12;
- residue = offset & (4096 - 1);
-
- if ((HAL_FIFO_SEL_TX == halmac_fifo_sel) || (HAL_FIFO_SEL_RSVD_PAGE == halmac_fifo_sel))
- start_page += 0x780;
- else if (HAL_FIFO_SEL_RX == halmac_fifo_sel)
- start_page += 0x700;
- else if (HAL_FIFO_SEL_REPORT == halmac_fifo_sel)
- start_page += 0x660;
- else if (HAL_FIFO_SEL_LLT == halmac_fifo_sel)
- start_page += 0x650;
-
- value_read = HALMAC_REG_READ_16(pHalmac_adapter, REG_PKTBUF_DBG_CTRL);
-
- while (1) {
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_PKTBUF_DBG_CTRL, (u16)(start_page | (value_read & 0xF000)));
-
- for (i = 0x8000 + residue; i <= 0x8FFF; i += 4) {
- *(u32 *)(pFifo_map + counter) = HALMAC_REG_READ_32(pHalmac_adapter, i);
- *(u32 *)(pFifo_map + counter) = rtk_le32_to_cpu(*(u32 *)(pFifo_map + counter));
- counter += 4;
- if (size == counter)
- goto HALMAC_BUF_READ_OK;
- }
-
- residue = 0;
- start_page++;
- }
-
-HALMAC_BUF_READ_OK:
- HALMAC_REG_WRITE_16(pHalmac_adapter, REG_PKTBUF_DBG_CTRL, (u16)value_read);
-
- return HALMAC_RET_SUCCESS;
-}
-
-VOID
-halmac_restore_mac_register_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_RESTORE_INFO pRestore_info,
- IN u32 restore_num
-)
-{
- u8 value_length;
- u32 i;
- u32 mac_register;
- u32 mac_value;
- PHALMAC_API pHalmac_api;
- PHALMAC_RESTORE_INFO pCurr_restore_info = pRestore_info;
-
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- for (i = 0; i < restore_num; i++) {
- mac_register = pCurr_restore_info->mac_register;
- mac_value = pCurr_restore_info->value;
- value_length = pCurr_restore_info->length;
-
- if (1 == value_length)
- HALMAC_REG_WRITE_8(pHalmac_adapter, mac_register, (u8)mac_value);
- else if (2 == value_length)
- HALMAC_REG_WRITE_16(pHalmac_adapter, mac_register, (u16)mac_value);
- else if (4 == value_length)
- HALMAC_REG_WRITE_32(pHalmac_adapter, mac_register, mac_value);
-
- pCurr_restore_info++;
- }
-}
-
-VOID
-halmac_api_record_id_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_API_ID api_id
-)
-{
- u8 array_wptr_last;
-
- array_wptr_last = pHalmac_adapter->api_record.array_wptr;
-
- if (array_wptr_last == API_ARRAY_SIZE - 1)
- array_wptr_last = 0;
- else if (HALMAC_API_STUFF == pHalmac_adapter->api_record.api_array[0])
- array_wptr_last = array_wptr_last;
- else
- array_wptr_last = array_wptr_last + 1;
-
- pHalmac_adapter->api_record.api_array[array_wptr_last] = api_id;
- pHalmac_adapter->api_record.array_wptr = array_wptr_last;
-}
-
-VOID
-halmac_get_hcpwm_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- OUT u8 *pHcpwm
-)
-{
- PHALMAC_API pHalmac_api;
- u32 hcpwm_offset = 0;
-
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- if (HALMAC_INTERFACE_PCIE == pHalmac_adapter->halmac_interface)
- hcpwm_offset = REG_PCIE_HCPWM1_V1;
- else if (HALMAC_INTERFACE_USB == pHalmac_adapter->halmac_interface)
- hcpwm_offset = 0xFE57;
- else if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface)
- hcpwm_offset = REG_SDIO_HCPWM1_V2;
-
- *pHcpwm = HALMAC_REG_READ_8(pHalmac_adapter, hcpwm_offset);
-}
-
-VOID
-halmac_get_hcpwm2_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- OUT u16 *pHcpwm2
-)
-{
- PHALMAC_API pHalmac_api;
- u32 hcpwm2_offset = 0;
-
-
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- if (HALMAC_INTERFACE_PCIE == pHalmac_adapter->halmac_interface)
- hcpwm2_offset = REG_PCIE_HCPWM2_V1;
- else if (HALMAC_INTERFACE_USB == pHalmac_adapter->halmac_interface)
- hcpwm2_offset = 0xFE34;
- else if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface)
- hcpwm2_offset = REG_SDIO_HCPWM2_V2;
-
- *pHcpwm2 = HALMAC_REG_READ_16(pHalmac_adapter, hcpwm2_offset);
-}
-
-VOID
-halmac_set_hrpwm_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 hrpwm
-)
-{
- PHALMAC_API pHalmac_api;
- u32 hrpwm_offset = 0;
- u8 hrpwm_original = 0;
-
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- if (HALMAC_INTERFACE_PCIE == pHalmac_adapter->halmac_interface)
- hrpwm_offset = REG_PCIE_HRPWM1_V1;
- else if (HALMAC_INTERFACE_USB == pHalmac_adapter->halmac_interface)
- hrpwm_offset = 0xFE58;
- else if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface)
- hrpwm_offset = REG_SDIO_HRPWM1;
-
- hrpwm_original = HALMAC_REG_READ_8(pHalmac_adapter, hrpwm_offset);
- hrpwm = (hrpwm & 0x7F) | ((~hrpwm_original) & 0x80);
-
- HALMAC_REG_WRITE_8(pHalmac_adapter, hrpwm_offset, hrpwm);
-}
-
-VOID
-halmac_set_hrpwm2_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u16 hrpwm2
-)
-{
- PHALMAC_API pHalmac_api;
- u32 hrpwm2_offset = 0;
- u16 hrpwm2_original = 0;
-
- pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
-
- if (HALMAC_INTERFACE_PCIE == pHalmac_adapter->halmac_interface)
- hrpwm2_offset = REG_PCIE_HRPWM2_V1;
- else if (HALMAC_INTERFACE_USB == pHalmac_adapter->halmac_interface)
- hrpwm2_offset = 0xFE36;
- else if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface)
- hrpwm2_offset = REG_SDIO_HRPWM2;
-
- hrpwm2_original = HALMAC_REG_READ_16(pHalmac_adapter, hrpwm2_offset);
- hrpwm2 = (hrpwm2 & 0x7FFF) | ((~hrpwm2_original) & 0x8000);
-
- HALMAC_REG_WRITE_16(pHalmac_adapter, hrpwm2_offset, hrpwm2);
-}
diff --git a/hal/halmac/halmac_88xx/halmac_func_88xx.h b/hal/halmac/halmac_88xx/halmac_func_88xx.h
deleted file mode 100644
index b085ed7..0000000
--- a/hal/halmac/halmac_88xx/halmac_func_88xx.h
+++ /dev/null
@@ -1,420 +0,0 @@
-#ifndef _HALMAC_FUNC_88XX_H_
-#define _HALMAC_FUNC_88XX_H_
-
-#include "../halmac_type.h"
-
-
-HALMAC_RET_STATUS
-halmac_send_h2c_pkt_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pHal_buff,
- IN u32 size,
- IN u8 ack
-);
-
-HALMAC_RET_STATUS
-halmac_download_rsvd_page_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pHal_buf,
- IN u32 size
-);
-
-HALMAC_RET_STATUS
-halmac_set_h2c_header_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- OUT u8 *pHal_h2c_hdr,
- IN u16 *seq,
- IN u8 ack
-);
-
-HALMAC_RET_STATUS
-halmac_set_fw_offload_h2c_header_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- OUT u8 *pHal_h2c_hdr,
- IN PHALMAC_H2C_HEADER_INFO pH2c_header_info,
- OUT u16 *pSeq_num
-);
-
-HALMAC_RET_STATUS
-halmac_dump_efuse_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_EFUSE_READ_CFG cfg
-);
-
-HALMAC_RET_STATUS
-halmac_func_read_efuse_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 offset,
- IN u32 size,
- OUT u8 *pEfuse_map
-);
-
-HALMAC_RET_STATUS
-halmac_func_write_efuse_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 offset,
- IN u8 value
-);
-
-HALMAC_RET_STATUS
-halmac_func_switch_efuse_bank_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_EFUSE_BANK efuse_bank
-);
-
-HALMAC_RET_STATUS
-halmac_read_logical_efuse_map_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pMap
-);
-
-HALMAC_RET_STATUS
-halmac_func_write_logical_efuse_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 offset,
- IN u8 value
-);
-
-HALMAC_RET_STATUS
-halmac_func_pg_efuse_by_map_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_PG_EFUSE_INFO pPg_efuse_info,
- IN HALMAC_EFUSE_READ_CFG cfg
-);
-
-HALMAC_RET_STATUS
-halmac_eeprom_parser_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pPhysical_efuse_map,
- OUT u8 *pLogical_efuse_map
-);
-
-HALMAC_RET_STATUS
-halmac_read_hw_efuse_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 offset,
- IN u32 size,
- OUT u8 *pEfuse_map
-);
-
-HALMAC_RET_STATUS
-halmac_dlfw_to_mem_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pRam_code,
- IN u32 dest,
- IN u32 code_size
-);
-
-HALMAC_RET_STATUS
-halmac_send_fwpkt_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pRam_code,
- IN u32 code_size
-);
-
-HALMAC_RET_STATUS
-halmac_iddma_dlfw_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 source,
- IN u32 dest,
- IN u32 length,
- IN u8 first
-);
-
-HALMAC_RET_STATUS
-halmac_check_fw_chksum_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 memory_address
-);
-
-HALMAC_RET_STATUS
-halmac_dlfw_end_flow_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-HALMAC_RET_STATUS
-halmac_pwr_seq_parser_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 CUT,
- IN u8 FAB,
- IN u8 INTF,
- IN PHALMAC_WLAN_PWR_CFG PWR_SEQ_CFG
-);
-
-HALMAC_RET_STATUS
-halmac_get_h2c_buff_free_space_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-HALMAC_RET_STATUS
-halmac_send_h2c_set_pwr_mode_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_FWLPS_OPTION pHal_FwLps_Opt
-);
-
-HALMAC_RET_STATUS
-halmac_func_send_original_h2c_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *original_h2c,
- IN u16 *seq,
- IN u8 ack
-);
-
-HALMAC_RET_STATUS
-halmac_media_status_rpt_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 op_mode,
- IN u8 mac_id_ind,
- IN u8 mac_id,
- IN u8 mac_id_end
-);
-
-HALMAC_RET_STATUS
-halmac_send_h2c_update_datapack_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_DATA_TYPE halmac_data_type,
- IN PHALMAC_PHY_PARAMETER_INFO para_info
-);
-
-HALMAC_RET_STATUS
-halmac_send_h2c_run_datapack_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_DATA_TYPE halmac_data_type
-);
-
-HALMAC_RET_STATUS
-halmac_send_bt_coex_cmd_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *pBt_buf,
- IN u32 bt_size,
- IN u8 ack
-);
-
-HALMAC_RET_STATUS
-halmac_func_ctrl_ch_switch_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_CH_SWITCH_OPTION pCs_option
-);
-
-HALMAC_RET_STATUS
-halmac_func_send_general_info_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_GENERAL_INFO pGeneral_info
-);
-
-HALMAC_RET_STATUS
-halmac_send_h2c_ps_tuning_para_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-HALMAC_RET_STATUS
-halmac_parse_c2h_packet_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 *halmac_buf,
- IN u32 halmac_size
-);
-
-HALMAC_RET_STATUS
-halmac_send_h2c_update_packet_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_PACKET_ID pkt_id,
- IN u8 *pkt,
- IN u32 pkt_size
-);
-
-HALMAC_RET_STATUS
-halmac_send_h2c_phy_parameter_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_PHY_PARAMETER_INFO para_info,
- IN u8 full_fifo
-);
-
-HALMAC_RET_STATUS
-halmac_dump_physical_efuse_fw_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 offset,
- IN u32 Size,
- OUT u8 *pEfuse_map
-);
-
-HALMAC_RET_STATUS
-halmac_send_h2c_update_bcn_parse_info_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_BCN_IE_INFO pBcn_ie_info
-);
-
-HALMAC_RET_STATUS
-halmac_convert_to_sdio_bus_offset_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- INOUT u32 *halmac_offset
-);
-
-HALMAC_RET_STATUS
-halmac_update_sdio_free_page_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-HALMAC_RET_STATUS
-halmac_update_oqt_free_space_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-HALMAC_EFUSE_CMD_CONSTRUCT_STATE
-halmac_query_efuse_curr_state_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-HALMAC_RET_STATUS
-halmac_transition_efuse_state_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_EFUSE_CMD_CONSTRUCT_STATE dest_state
-);
-
-HALMAC_CFG_PARA_CMD_CONSTRUCT_STATE
-halmac_query_cfg_para_curr_state_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-HALMAC_RET_STATUS
-halmac_transition_cfg_para_state_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_CFG_PARA_CMD_CONSTRUCT_STATE dest_state
-);
-
-HALMAC_SCAN_CMD_CONSTRUCT_STATE
-halmac_query_scan_curr_state_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-HALMAC_RET_STATUS
-halmac_transition_scan_state_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_SCAN_CMD_CONSTRUCT_STATE dest_state
-);
-
-HALMAC_RET_STATUS
-halmac_query_cfg_para_status_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status,
- INOUT u8 *data,
- INOUT u32 *size
-);
-
-HALMAC_RET_STATUS
-halmac_query_dump_physical_efuse_status_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status,
- INOUT u8 *data,
- INOUT u32 *size
-);
-
-HALMAC_RET_STATUS
-halmac_query_dump_logical_efuse_status_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status,
- INOUT u8 *data,
- INOUT u32 *size
-);
-
-HALMAC_RET_STATUS
-halmac_query_channel_switch_status_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status,
- INOUT u8 *data,
- INOUT u32 *size
-);
-
-HALMAC_RET_STATUS
-halmac_query_update_packet_status_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status,
- INOUT u8 *data,
- INOUT u32 *size
-);
-
-HALMAC_RET_STATUS
-halmac_query_iqk_status_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status,
- INOUT u8 *data,
- INOUT u32 *size
-);
-
-HALMAC_RET_STATUS
-halmac_query_power_tracking_status_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status,
- INOUT u8 *data,
- INOUT u32 *size
-);
-
-HALMAC_RET_STATUS
-halmac_query_psd_status_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status,
- INOUT u8 *data,
- INOUT u32 *size
-);
-
-HALMAC_RET_STATUS
-halmac_verify_io_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-HALMAC_RET_STATUS
-halmac_verify_send_rsvd_page_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-VOID
-halmac_power_save_cb_88xx(
- IN VOID *CbData
-);
-
-HALMAC_RET_STATUS
-halmac_buffer_read_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u32 offset,
- IN u32 size,
- IN HAL_FIFO_SEL halmac_fifo_sel,
- OUT u8 *pFifo_map
-);
-
-VOID
-halmac_restore_mac_register_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN PHALMAC_RESTORE_INFO pRestore_info,
- IN u32 restore_num
-);
-
-VOID
-halmac_api_record_id_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN HALMAC_API_ID api_id
-);
-
-VOID
-halmac_get_hcpwm_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- OUT u8 *pHcpwm
-);
-
-VOID
-halmac_get_hcpwm2_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- OUT u16 *pHcpwm2
-);
-
-VOID
-halmac_set_hrpwm_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u8 hrpwm
-);
-
-VOID
-halmac_set_hrpwm2_88xx(
- IN PHALMAC_ADAPTER pHalmac_adapter,
- IN u16 hrpwm2
-);
-
-#endif /* _HALMAC_FUNC_88XX_H_ */
diff --git a/hal/halmac/halmac_88xx/halmac_fw_88xx.c b/hal/halmac/halmac_88xx/halmac_fw_88xx.c
new file mode 100644
index 0000000..1a6d44e
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_fw_88xx.c
@@ -0,0 +1,1134 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_fw_88xx.h"
+#include "halmac_88xx_cfg.h"
+#include "halmac_common_88xx.h"
+#include "halmac_init_88xx.h"
+
+#if HALMAC_88XX_SUPPORT
+
+#define DLFW_RESTORE_REG_NUM 6
+#define ILLEGAL_KEY_GROUP 0xFAAAAA00
+
+/* Max dlfw size can not over 31K, due to SDIO HW limitation */
+#define DLFW_PKT_SIZE_LIMIT 31744
+
+#define ID_INFORM_DLEMEM_RDY 0x80
+#define ID_INFORM_ENETR_CPU_SLEEP 0x20
+#define ID_CHECK_DLEMEM_RDY 0x80
+#define ID_CHECK_ENETR_CPU_SLEEP 0x05
+
+#define FW_STATUS_CHK_FATAL (BIT(1) | BIT(20))
+#define FW_STATUS_CHK_ERR (BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | \
+ BIT(9) | BIT(12) | BIT(14) | BIT(15) | \
+ BIT(16) | BIT(17) | BIT(18) | BIT(19) | \
+ BIT(21) | BIT(22) | BIT(25))
+#define FW_STATUS_CHK_WARN ~(FW_STATUS_CHK_FATAL | FW_STATUS_CHK_ERR)
+
+struct halmac_backup_info {
+ u32 mac_register;
+ u32 value;
+ u8 length;
+};
+
+static enum halmac_ret_status
+update_fw_info_88xx(struct halmac_adapter *adapter, u8 *fw_bin);
+
+static void
+restore_mac_reg_88xx(struct halmac_adapter *adapter,
+ struct halmac_backup_info *info, u32 num);
+
+static enum halmac_ret_status
+dlfw_to_mem_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 src, u32 dest,
+ u32 size);
+
+static enum halmac_ret_status
+dlfw_end_flow_88xx(struct halmac_adapter *adapter);
+
+static enum halmac_ret_status
+free_dl_fw_end_flow_88xx(struct halmac_adapter *adapter);
+
+static enum halmac_ret_status
+send_fwpkt_88xx(struct halmac_adapter *adapter, u16 pg_addr, u8 *fw_bin,
+ u32 size);
+
+static enum halmac_ret_status
+iddma_dlfw_88xx(struct halmac_adapter *adapter, u32 src, u32 dest, u32 len,
+ u8 first);
+
+static enum halmac_ret_status
+iddma_en_88xx(struct halmac_adapter *adapter, u32 src, u32 dest, u32 ctrl);
+
+static enum halmac_ret_status
+check_fw_chksum_88xx(struct halmac_adapter *adapter, u32 mem_addr);
+
+static void
+fw_fatal_status_debug_88xx(struct halmac_adapter *adapter);
+
+static enum halmac_ret_status
+start_dlfw_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,
+ u32 dl_addr, u8 emem_only);
+
+static enum halmac_ret_status
+chk_fw_size_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size);
+
+static void
+chk_h2c_ver_88xx(struct halmac_adapter *adapter, u8 *fw_bin);
+
+static void
+wlan_cpu_en_88xx(struct halmac_adapter *adapter, u8 enable);
+
+static void
+pltfm_reset_88xx(struct halmac_adapter *adapter);
+
+static enum halmac_ret_status
+proc_send_general_info_88xx(struct halmac_adapter *adapter,
+ struct halmac_general_info *info);
+
+static enum halmac_ret_status
+proc_send_phydm_info_88xx(struct halmac_adapter *adapter,
+ struct halmac_general_info *info);
+
+/**
+ * download_firmware_88xx() - download Firmware
+ * @adapter : the adapter of halmac
+ * @fw_bin : firmware bin
+ * @size : firmware size
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+download_firmware_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size)
+{
+ u8 value8;
+ u32 bckp_idx = 0;
+ u32 lte_coex_backup = 0;
+ struct halmac_backup_info bckp[DLFW_RESTORE_REG_NUM];
+ enum halmac_ret_status status;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF)
+ return HALMAC_RET_POWER_STATE_INVALID;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ status = chk_fw_size_88xx(adapter, fw_bin, size);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+
+ chk_h2c_ver_88xx(adapter, fw_bin);
+
+ if (adapter->halmac_state.wlcpu_mode == HALMAC_WLCPU_ENTER_SLEEP)
+ PLTFM_MSG_WARN("[WARN]Enter Sleep..zZZ\n");
+
+ adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE;
+
+ status = ltecoex_reg_read_88xx(adapter, 0x38, <e_coex_backup);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+
+ wlan_cpu_en_88xx(adapter, 0);
+
+ /* set HIQ to hi priority */
+ bckp[bckp_idx].length = 1;
+ bckp[bckp_idx].mac_register = REG_TXDMA_PQ_MAP + 1;
+ bckp[bckp_idx].value = HALMAC_REG_R8(REG_TXDMA_PQ_MAP + 1);
+ bckp_idx++;
+ value8 = HALMAC_DMA_MAPPING_HIGH << 6;
+ HALMAC_REG_W8(REG_TXDMA_PQ_MAP + 1, value8);
+
+ /* DLFW only use HIQ, map HIQ to hi priority */
+ adapter->pq_map[HALMAC_PQ_MAP_HI] = HALMAC_DMA_MAPPING_HIGH;
+ bckp[bckp_idx].length = 1;
+ bckp[bckp_idx].mac_register = REG_CR;
+ bckp[bckp_idx].value = HALMAC_REG_R8(REG_CR);
+ bckp_idx++;
+ bckp[bckp_idx].length = 4;
+ bckp[bckp_idx].mac_register = REG_H2CQ_CSR;
+ bckp[bckp_idx].value = BIT(31);
+ bckp_idx++;
+ value8 = BIT_HCI_TXDMA_EN | BIT_TXDMA_EN;
+ HALMAC_REG_W8(REG_CR, value8);
+ HALMAC_REG_W32(REG_H2CQ_CSR, BIT(31));
+
+ /* Config hi priority queue and public priority queue page number */
+ bckp[bckp_idx].length = 2;
+ bckp[bckp_idx].mac_register = REG_FIFOPAGE_INFO_1;
+ bckp[bckp_idx].value = HALMAC_REG_R16(REG_FIFOPAGE_INFO_1);
+ bckp_idx++;
+ bckp[bckp_idx].length = 4;
+ bckp[bckp_idx].mac_register = REG_RQPN_CTRL_2;
+ bckp[bckp_idx].value = HALMAC_REG_R32(REG_RQPN_CTRL_2) | BIT(31);
+ bckp_idx++;
+ HALMAC_REG_W16(REG_FIFOPAGE_INFO_1, 0x200);
+ HALMAC_REG_W32(REG_RQPN_CTRL_2, bckp[bckp_idx - 1].value);
+
+ /* Disable beacon related functions */
+ value8 = HALMAC_REG_R8(REG_BCN_CTRL);
+ bckp[bckp_idx].length = 1;
+ bckp[bckp_idx].mac_register = REG_BCN_CTRL;
+ bckp[bckp_idx].value = value8;
+ bckp_idx++;
+ value8 = (u8)((value8 & (~BIT(3))) | BIT(4));
+ HALMAC_REG_W8(REG_BCN_CTRL, value8);
+
+ if (adapter->intf == HALMAC_INTERFACE_SDIO)
+ HALMAC_REG_R32(REG_SDIO_FREE_TXPG);
+
+ pltfm_reset_88xx(adapter);
+
+ status = start_dlfw_88xx(adapter, fw_bin, size, 0, 0);
+
+ restore_mac_reg_88xx(adapter, bckp, DLFW_RESTORE_REG_NUM);
+
+ if (status != HALMAC_RET_SUCCESS)
+ goto DLFW_FAIL;
+
+ status = dlfw_end_flow_88xx(adapter);
+ if (status != HALMAC_RET_SUCCESS)
+ goto DLFW_FAIL;
+
+ status = ltecoex_reg_write_88xx(adapter, 0x38, lte_coex_backup);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+
+ adapter->halmac_state.dlfw_state = HALMAC_DLFW_DONE;
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+
+DLFW_FAIL:
+
+ /* Disable FWDL_EN */
+ value8 = HALMAC_REG_R8(REG_MCUFW_CTRL);
+ value8 &= ~BIT(0);
+ HALMAC_REG_W8(REG_MCUFW_CTRL, value8);
+
+ value8 = HALMAC_REG_R8(REG_SYS_FUNC_EN + 1);
+ value8 |= BIT(2);
+ HALMAC_REG_W8(REG_SYS_FUNC_EN + 1, value8);
+
+ if (ltecoex_reg_write_88xx(adapter, 0x38, lte_coex_backup) !=
+ HALMAC_RET_SUCCESS)
+ return HALMAC_RET_LTECOEX_READY_FAIL;
+
+ return status;
+}
+
+static enum halmac_ret_status
+start_dlfw_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size,
+ u32 dl_addr, u8 emem_only)
+{
+ u8 *cur_fw;
+ u16 value16;
+ u32 imem_size;
+ u32 dmem_size;
+ u32 emem_size = 0;
+ u32 addr;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+ enum halmac_ret_status status;
+
+ dmem_size = *((u32 *)(fw_bin + WLAN_FW_HDR_DMEM_SIZE));
+ imem_size = *((u32 *)(fw_bin + WLAN_FW_HDR_IMEM_SIZE));
+ if (0 != ((*(fw_bin + WLAN_FW_HDR_MEM_USAGE)) & BIT(4)))
+ emem_size = *((u32 *)(fw_bin + WLAN_FW_HDR_EMEM_SIZE));
+
+ dmem_size = rtk_le32_to_cpu(dmem_size);
+ imem_size = rtk_le32_to_cpu(imem_size);
+ emem_size = rtk_le32_to_cpu(emem_size);
+
+ dmem_size += WLAN_FW_HDR_CHKSUM_SIZE;
+ imem_size += WLAN_FW_HDR_CHKSUM_SIZE;
+ if (emem_size != 0)
+ emem_size += WLAN_FW_HDR_CHKSUM_SIZE;
+
+ if (emem_only == 1) {
+ if (!emem_size)
+ return HALMAC_RET_SUCCESS;
+ goto DLFW_EMEM;
+ }
+
+ value16 = (u16)(HALMAC_REG_R16(REG_MCUFW_CTRL) & 0x3800);
+ value16 |= BIT(0);
+ HALMAC_REG_W16(REG_MCUFW_CTRL, value16);
+
+ cur_fw = fw_bin + WLAN_FW_HDR_SIZE;
+ addr = *((u32 *)(fw_bin + WLAN_FW_HDR_DMEM_ADDR));
+ addr = rtk_le32_to_cpu(addr) & ~BIT(31);
+ status = dlfw_to_mem_88xx(adapter, cur_fw, 0, addr, dmem_size);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+
+ cur_fw = fw_bin + WLAN_FW_HDR_SIZE + dmem_size;
+ addr = *((u32 *)(fw_bin + WLAN_FW_HDR_IMEM_ADDR));
+ addr = rtk_le32_to_cpu(addr) & ~BIT(31);
+ status = dlfw_to_mem_88xx(adapter, cur_fw, 0, addr, imem_size);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+
+DLFW_EMEM:
+ if (emem_size) {
+ cur_fw = fw_bin + WLAN_FW_HDR_SIZE +
+ dmem_size + imem_size;
+ addr = *((u32 *)(fw_bin + WLAN_FW_HDR_EMEM_ADDR));
+ addr = rtk_le32_to_cpu(addr) & ~BIT(31);
+ status = dlfw_to_mem_88xx(adapter, cur_fw, dl_addr << 7, addr,
+ emem_size);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+
+ if (emem_only == 1)
+ return HALMAC_RET_SUCCESS;
+ }
+
+ update_fw_info_88xx(adapter, fw_bin);
+ init_ofld_feature_state_machine_88xx(adapter);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static void
+chk_h2c_ver_88xx(struct halmac_adapter *adapter, u8 *fw_bin)
+{
+ u16 halmac_h2c_ver;
+ u16 fw_h2c_ver;
+
+ fw_h2c_ver = *((u16 *)(fw_bin + WLAN_FW_HDR_H2C_FMT_VER));
+ fw_h2c_ver = rtk_le16_to_cpu(fw_h2c_ver);
+ halmac_h2c_ver = H2C_FORMAT_VERSION;
+
+ PLTFM_MSG_TRACE("[TRACE]halmac h2c ver = %x, fw h2c ver = %x!!\n",
+ halmac_h2c_ver, fw_h2c_ver);
+
+ if (fw_h2c_ver != halmac_h2c_ver)
+ PLTFM_MSG_WARN("[WARN]H2C/C2H ver is compatible!!\n");
+}
+
+static enum halmac_ret_status
+chk_fw_size_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size)
+{
+ u32 imem_size;
+ u32 dmem_size;
+ u32 emem_size = 0;
+ u32 real_size;
+
+ if (size < WLAN_FW_HDR_SIZE) {
+ PLTFM_MSG_ERR("[ERR]FW size error!\n");
+ return HALMAC_RET_FW_SIZE_ERR;
+ }
+
+ dmem_size = *((u32 *)(fw_bin + WLAN_FW_HDR_DMEM_SIZE));
+ imem_size = *((u32 *)(fw_bin + WLAN_FW_HDR_IMEM_SIZE));
+ if (0 != ((*(fw_bin + WLAN_FW_HDR_MEM_USAGE)) & BIT(4)))
+ emem_size = *((u32 *)(fw_bin + WLAN_FW_HDR_EMEM_SIZE));
+
+ dmem_size = rtk_le32_to_cpu(dmem_size);
+ imem_size = rtk_le32_to_cpu(imem_size);
+ emem_size = rtk_le32_to_cpu(emem_size);
+
+ dmem_size += WLAN_FW_HDR_CHKSUM_SIZE;
+ imem_size += WLAN_FW_HDR_CHKSUM_SIZE;
+ if (emem_size != 0)
+ emem_size += WLAN_FW_HDR_CHKSUM_SIZE;
+
+ real_size = WLAN_FW_HDR_SIZE + dmem_size + imem_size + emem_size;
+ if (size != real_size) {
+ PLTFM_MSG_ERR("[ERR]size != real size!\n");
+ return HALMAC_RET_FW_SIZE_ERR;
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static void
+wlan_cpu_en_88xx(struct halmac_adapter *adapter, u8 enable)
+{
+ u8 value8;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ if (enable == 1) {
+ /* cpu io interface enable or disable */
+ value8 = HALMAC_REG_R8(REG_RSV_CTRL + 1);
+ value8 |= BIT(0);
+ HALMAC_REG_W8(REG_RSV_CTRL + 1, value8);
+
+ /* cpu enable or disable */
+ value8 = HALMAC_REG_R8(REG_SYS_FUNC_EN + 1);
+ value8 |= BIT(2);
+ HALMAC_REG_W8(REG_SYS_FUNC_EN + 1, value8);
+
+ } else {
+ /* cpu enable or disable */
+ value8 = HALMAC_REG_R8(REG_SYS_FUNC_EN + 1);
+ value8 &= ~BIT(2);
+ HALMAC_REG_W8(REG_SYS_FUNC_EN + 1, value8);
+
+ /* cpu io interface enable or disable */
+ value8 = HALMAC_REG_R8(REG_RSV_CTRL + 1);
+ value8 &= ~BIT(0);
+ HALMAC_REG_W8(REG_RSV_CTRL + 1, value8);
+ }
+}
+
+static void
+pltfm_reset_88xx(struct halmac_adapter *adapter)
+{
+ u8 value8;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ value8 = HALMAC_REG_R8(REG_CPU_DMEM_CON + 2) & ~BIT(0);
+ HALMAC_REG_W8(REG_CPU_DMEM_CON + 2, value8);
+
+ /* For 8822B & 8821C clock sync issue */
+ if (adapter->chip_id == HALMAC_CHIP_ID_8821C ||
+ adapter->chip_id == HALMAC_CHIP_ID_8822B) {
+ value8 = HALMAC_REG_R8(REG_SYS_CLK_CTRL + 1) & ~BIT(6);
+ HALMAC_REG_W8(REG_SYS_CLK_CTRL + 1, value8);
+ }
+
+ value8 = HALMAC_REG_R8(REG_CPU_DMEM_CON + 2) | BIT(0);
+ HALMAC_REG_W8(REG_CPU_DMEM_CON + 2, value8);
+
+ if (adapter->chip_id == HALMAC_CHIP_ID_8821C ||
+ adapter->chip_id == HALMAC_CHIP_ID_8822B) {
+ value8 = HALMAC_REG_R8(REG_SYS_CLK_CTRL + 1) | BIT(6);
+ HALMAC_REG_W8(REG_SYS_CLK_CTRL + 1, value8);
+ }
+}
+
+/**
+ * free_download_firmware_88xx() - download specific memory firmware
+ * @adapter
+ * @mem_sel : memory selection
+ * @fw_bin : firmware bin
+ * @size : firmware size
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ */
+enum halmac_ret_status
+free_download_firmware_88xx(struct halmac_adapter *adapter,
+ enum halmac_dlfw_mem mem_sel, u8 *fw_bin, u32 size)
+{
+ u8 tx_pause_bckp;
+ u32 dl_addr;
+ u32 dlfw_size_bckp;
+ enum halmac_ret_status status;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
+ return HALMAC_RET_NO_DLFW;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ status = chk_fw_size_88xx(adapter, fw_bin, size);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+
+ if (((*(fw_bin + WLAN_FW_HDR_MEM_USAGE)) & BIT(4)) == 0)
+ return HALMAC_RET_SUCCESS;
+
+ dlfw_size_bckp = adapter->dlfw_pkt_size;
+ if (mem_sel == HALMAC_DLFW_MEM_EMEM) {
+ dl_addr = 0;
+ } else {
+ dl_addr = adapter->txff_alloc.rsvd_h2c_info_addr;
+ adapter->dlfw_pkt_size = (dlfw_size_bckp > DLFW_RSVDPG_SIZE) ?
+ DLFW_RSVDPG_SIZE : dlfw_size_bckp;
+ }
+
+ tx_pause_bckp = HALMAC_REG_R8(REG_TXPAUSE);
+ HALMAC_REG_W8(REG_TXPAUSE, tx_pause_bckp | BIT(7));
+
+ status = start_dlfw_88xx(adapter, fw_bin, size, dl_addr, 1);
+ if (status != HALMAC_RET_SUCCESS)
+ goto DL_FREE_FW_END;
+
+ status = free_dl_fw_end_flow_88xx(adapter);
+
+DL_FREE_FW_END:
+ HALMAC_REG_W8(REG_TXPAUSE, tx_pause_bckp);
+ adapter->dlfw_pkt_size = dlfw_size_bckp;
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return status;
+}
+
+/**
+ * get_fw_version_88xx() - get FW version
+ * @adapter : the adapter of halmac
+ * @ver : fw version info
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+get_fw_version_88xx(struct halmac_adapter *adapter,
+ struct halmac_fw_version *ver)
+{
+ struct halmac_fw_version *info = &adapter->fw_ver;
+
+ if (!ver)
+ return HALMAC_RET_NULL_POINTER;
+
+ if (adapter->halmac_state.dlfw_state == HALMAC_DLFW_NONE)
+ return HALMAC_RET_NO_DLFW;
+
+ ver->version = info->version;
+ ver->sub_version = info->sub_version;
+ ver->sub_index = info->sub_index;
+ ver->h2c_version = info->h2c_version;
+ ver->build_time.month = info->build_time.month;
+ ver->build_time.date = info->build_time.date;
+ ver->build_time.hour = info->build_time.hour;
+ ver->build_time.min = info->build_time.min;
+ ver->build_time.year = info->build_time.year;
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+update_fw_info_88xx(struct halmac_adapter *adapter, u8 *fw_bin)
+{
+ struct halmac_fw_version *info = &adapter->fw_ver;
+
+ info->version = *((u16 *)(fw_bin + WLAN_FW_HDR_VERSION));
+ info->version = rtk_le16_to_cpu(info->version);
+ info->sub_version = *(fw_bin + WLAN_FW_HDR_SUBVERSION);
+ info->sub_index = *(fw_bin + WLAN_FW_HDR_SUBINDEX);
+ info->h2c_version = *((u16 *)(fw_bin + WLAN_FW_HDR_H2C_FMT_VER));
+ info->h2c_version = rtk_le16_to_cpu(info->h2c_version);
+ info->build_time.month = *(fw_bin + WLAN_FW_HDR_MONTH);
+ info->build_time.date = *(fw_bin + WLAN_FW_HDR_DATE);
+ info->build_time.hour = *(fw_bin + WLAN_FW_HDR_HOUR);
+ info->build_time.min = *(fw_bin + WLAN_FW_HDR_MIN);
+ info->build_time.year = *((u16 *)(fw_bin + WLAN_FW_HDR_YEAR));
+ info->build_time.year = rtk_le16_to_cpu(info->build_time.year);
+
+ PLTFM_MSG_TRACE("[TRACE]=== FW info ===\n");
+ PLTFM_MSG_TRACE("[TRACE]ver : %X\n", info->version);
+ PLTFM_MSG_TRACE("[TRACE]sub-ver : %X\n",
+ info->sub_version);
+ PLTFM_MSG_TRACE("[TRACE]sub-idx : %X\n",
+ info->sub_index);
+ PLTFM_MSG_TRACE("[TRACE]build : %d/%d/%d %d:%d\n",
+ info->build_time.year, info->build_time.month,
+ info->build_time.date, info->build_time.hour,
+ info->build_time.min);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+dlfw_to_mem_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 src, u32 dest,
+ u32 size)
+{
+ u8 first_part;
+ u32 mem_offset;
+ u32 residue_size;
+ u32 pkt_size;
+ enum halmac_ret_status status;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ mem_offset = 0;
+ first_part = 1;
+ residue_size = size;
+
+ HALMAC_REG_W32_SET(REG_DDMA_CH0CTRL, BIT_DDMACH0_RESET_CHKSUM_STS);
+
+ while (residue_size != 0) {
+ if (residue_size >= adapter->dlfw_pkt_size)
+ pkt_size = adapter->dlfw_pkt_size;
+ else
+ pkt_size = residue_size;
+
+ status = send_fwpkt_88xx(adapter, (u16)(src >> 7),
+ fw_bin + mem_offset, pkt_size);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]send fw pkt!!");
+ return status;
+ }
+
+ status = iddma_dlfw_88xx(adapter,
+ OCPBASE_TXBUF_88XX +
+ src + adapter->hw_cfg_info.txdesc_size,
+ dest + mem_offset, pkt_size,
+ first_part);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]iddma dlfw!!");
+ return status;
+ }
+
+ first_part = 0;
+ mem_offset += pkt_size;
+ residue_size -= pkt_size;
+ }
+
+ status = check_fw_chksum_88xx(adapter, dest);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]chk fw chksum!!");
+ return status;
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static void
+restore_mac_reg_88xx(struct halmac_adapter *adapter,
+ struct halmac_backup_info *info, u32 num)
+{
+ u8 len;
+ u32 i;
+ u32 reg;
+ u32 value;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+ struct halmac_backup_info *curr_info = info;
+
+ for (i = 0; i < num; i++) {
+ reg = curr_info->mac_register;
+ value = curr_info->value;
+ len = curr_info->length;
+
+ if (len == 1)
+ HALMAC_REG_W8(reg, (u8)value);
+ else if (len == 2)
+ HALMAC_REG_W16(reg, (u16)value);
+ else if (len == 4)
+ HALMAC_REG_W32(reg, value);
+
+ curr_info++;
+ }
+}
+
+static enum halmac_ret_status
+dlfw_end_flow_88xx(struct halmac_adapter *adapter)
+{
+ u16 fw_ctrl;
+ u32 cnt;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ HALMAC_REG_W32(REG_TXDMA_STATUS, BIT(2));
+
+ /* Check IMEM & DMEM checksum is OK or not */
+ fw_ctrl = HALMAC_REG_R16(REG_MCUFW_CTRL);
+ if ((fw_ctrl & 0x50) != 0x50)
+ return HALMAC_RET_IDMEM_CHKSUM_FAIL;
+
+ HALMAC_REG_W16(REG_MCUFW_CTRL, (fw_ctrl | BIT_FW_DW_RDY) & ~BIT(0));
+
+ wlan_cpu_en_88xx(adapter, 1);
+ PLTFM_MSG_TRACE("[TRACE]Dlfw OK, enable CPU\n");
+
+ cnt = 5000;
+ while (HALMAC_REG_R16(REG_MCUFW_CTRL) != 0xC078) {
+ if (cnt == 0) {
+ PLTFM_MSG_ERR("[ERR]Check 0x80 = 0xC078 fail\n");
+ if ((HALMAC_REG_R32(REG_FW_DBG7) & 0xFFFFFF00) ==
+ ILLEGAL_KEY_GROUP) {
+ PLTFM_MSG_ERR("[ERR]Key!!\n");
+ return HALMAC_RET_ILLEGAL_KEY_FAIL;
+ }
+ return HALMAC_RET_FW_READY_CHK_FAIL;
+ }
+ cnt--;
+ PLTFM_DELAY_US(50);
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]0x80=0xC078, cnt=%d\n", cnt);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+free_dl_fw_end_flow_88xx(struct halmac_adapter *adapter)
+{
+ u32 cnt;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ cnt = 100;
+ while (HALMAC_REG_R8(REG_HMETFR + 3) != 0) {
+ cnt--;
+ if (cnt == 0) {
+ PLTFM_MSG_ERR("[ERR]0x1CF != 0\n");
+ return HALMAC_RET_DLFW_FAIL;
+ }
+ PLTFM_DELAY_US(50);
+ }
+
+ HALMAC_REG_W8(REG_HMETFR + 3, ID_INFORM_DLEMEM_RDY);
+
+ cnt = 10000;
+ while (HALMAC_REG_R8(REG_MCU_TST_CFG) != ID_CHECK_DLEMEM_RDY) {
+ cnt--;
+ if (cnt == 0) {
+ PLTFM_MSG_ERR("[ERR]0x84 != 0x80\n");
+ return HALMAC_RET_DLFW_FAIL;
+ }
+ PLTFM_DELAY_US(50);
+ }
+
+ HALMAC_REG_W8(REG_MCU_TST_CFG, 0);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+send_fwpkt_88xx(struct halmac_adapter *adapter, u16 pg_addr, u8 *fw_bin,
+ u32 size)
+{
+ enum halmac_ret_status status;
+
+ status = dl_rsvd_page_88xx(adapter, pg_addr, fw_bin, size);
+ if (status != HALMAC_RET_SUCCESS)
+ PLTFM_MSG_ERR("[ERR]dl rsvd page!!\n");
+
+ return status;
+}
+
+static enum halmac_ret_status
+iddma_dlfw_88xx(struct halmac_adapter *adapter, u32 src, u32 dest, u32 len,
+ u8 first)
+{
+ u32 cnt;
+ u32 ch0_ctrl = (u32)(BIT_DDMACH0_CHKSUM_EN | BIT_DDMACH0_OWN);
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ cnt = HALMC_DDMA_POLLING_COUNT;
+ while (HALMAC_REG_R32(REG_DDMA_CH0CTRL) & BIT_DDMACH0_OWN) {
+ cnt--;
+ if (cnt == 0) {
+ PLTFM_MSG_ERR("[ERR]ch0 ready!!\n");
+ return HALMAC_RET_DDMA_FAIL;
+ }
+ }
+
+ ch0_ctrl |= (len & BIT_MASK_DDMACH0_DLEN);
+ if (first == 0)
+ ch0_ctrl |= BIT_DDMACH0_CHKSUM_CONT;
+
+ if (iddma_en_88xx(adapter, src, dest, ch0_ctrl) !=
+ HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]iddma en!!\n");
+ return HALMAC_RET_DDMA_FAIL;
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+iddma_en_88xx(struct halmac_adapter *adapter, u32 src, u32 dest, u32 ctrl)
+{
+ u32 cnt = HALMC_DDMA_POLLING_COUNT;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ HALMAC_REG_W32(REG_DDMA_CH0SA, src);
+ HALMAC_REG_W32(REG_DDMA_CH0DA, dest);
+ HALMAC_REG_W32(REG_DDMA_CH0CTRL, ctrl);
+
+ while (HALMAC_REG_R32(REG_DDMA_CH0CTRL) & BIT_DDMACH0_OWN) {
+ cnt--;
+ if (cnt == 0)
+ return HALMAC_RET_DDMA_FAIL;
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+check_fw_chksum_88xx(struct halmac_adapter *adapter, u32 mem_addr)
+{
+ u8 fw_ctrl;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ fw_ctrl = HALMAC_REG_R8(REG_MCUFW_CTRL);
+
+ if (HALMAC_REG_R32(REG_DDMA_CH0CTRL) & BIT_DDMACH0_CHKSUM_STS) {
+ if (mem_addr < OCPBASE_DMEM_88XX) {
+ fw_ctrl |= BIT_IMEM_DW_OK;
+ fw_ctrl &= ~BIT_IMEM_CHKSUM_OK;
+ HALMAC_REG_W8(REG_MCUFW_CTRL, fw_ctrl);
+ } else {
+ fw_ctrl |= BIT_DMEM_DW_OK;
+ fw_ctrl &= ~BIT_DMEM_CHKSUM_OK;
+ HALMAC_REG_W8(REG_MCUFW_CTRL, fw_ctrl);
+ }
+
+ PLTFM_MSG_ERR("[ERR]fw chksum!!\n");
+
+ return HALMAC_RET_FW_CHECKSUM_FAIL;
+ }
+
+ if (mem_addr < OCPBASE_DMEM_88XX) {
+ fw_ctrl |= (BIT_IMEM_DW_OK | BIT_IMEM_CHKSUM_OK);
+ HALMAC_REG_W8(REG_MCUFW_CTRL, fw_ctrl);
+ } else {
+ fw_ctrl |= (BIT_DMEM_DW_OK | BIT_DMEM_CHKSUM_OK);
+ HALMAC_REG_W8(REG_MCUFW_CTRL, fw_ctrl);
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * check_fw_status_88xx() -check fw status
+ * @adapter : the adapter of halmac
+ * @status : fw status
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+check_fw_status_88xx(struct halmac_adapter *adapter, u8 *fw_status)
+{
+ u32 cnt;
+ u32 fw_dbg6;
+ u32 fw_pc;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ *fw_status = _TRUE;
+
+ fw_dbg6 = HALMAC_REG_R32(REG_FW_DBG6);
+
+ if (fw_dbg6 != 0) {
+ PLTFM_MSG_ERR("[ERR]REG_FW_DBG6 !=0\n");
+ if ((fw_dbg6 & FW_STATUS_CHK_WARN) != 0)
+ PLTFM_MSG_WARN("[WARN]fw status(warn):%X\n", fw_dbg6);
+
+ if ((fw_dbg6 & FW_STATUS_CHK_ERR) != 0)
+ PLTFM_MSG_ERR("[ERR]fw status(err):%X\n", fw_dbg6);
+
+ if ((fw_dbg6 & FW_STATUS_CHK_FATAL) != 0) {
+ PLTFM_MSG_ERR("[ERR]fw status(fatal):%X\n", fw_dbg6);
+ fw_fatal_status_debug_88xx(adapter);
+ *fw_status = _FALSE;
+ return status;
+ }
+ }
+
+ fw_pc = HALMAC_REG_R32(REG_FW_DBG7);
+ cnt = 10;
+ while (HALMAC_REG_R32(REG_FW_DBG7) == fw_pc) {
+ cnt--;
+ if (cnt == 0)
+ break;
+ }
+
+ if (cnt == 0) {
+ cnt = 200;
+ while (HALMAC_REG_R32(REG_FW_DBG7) == fw_pc) {
+ cnt--;
+ if (cnt == 0) {
+ PLTFM_MSG_ERR("[ERR]fw pc\n");
+ *fw_status = _FALSE;
+ return status;
+ }
+ PLTFM_DELAY_US(50);
+ }
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return status;
+}
+
+static void
+fw_fatal_status_debug_88xx(struct halmac_adapter *adapter)
+{
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ PLTFM_MSG_ERR("[ERR]0x%X = %X\n",
+ REG_FW_DBG6, HALMAC_REG_R32(REG_FW_DBG6));
+
+ PLTFM_MSG_ERR("[ERR]0x%X = %X\n",
+ REG_ARFR5, HALMAC_REG_R32(REG_ARFR5));
+
+ PLTFM_MSG_ERR("[ERR]0x%X = %X\n",
+ REG_MCUTST_I, HALMAC_REG_R32(REG_MCUTST_I));
+}
+
+enum halmac_ret_status
+dump_fw_dmem_88xx(struct halmac_adapter *adapter, u8 *dmem, u32 *size)
+{
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_max_dl_size_88xx() - config max download FW size
+ * @adapter : the adapter of halmac
+ * @size : max download fw size
+ *
+ * Halmac uses this setting to set max packet size for
+ * download FW.
+ * If user has not called this API, halmac use default
+ * setting for download FW
+ * Note1 : size need multiple of 2
+ * Note2 : max size is 31K
+ *
+ * Author : Ivan Lin/KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_max_dl_size_88xx(struct halmac_adapter *adapter, u32 size)
+{
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (size > DLFW_PKT_SIZE_LIMIT) {
+ PLTFM_MSG_ERR("[ERR]size > max dl size!\n");
+ return HALMAC_RET_CFG_DLFW_SIZE_FAIL;
+ }
+
+ if ((size & (2 - 1)) != 0) {
+ PLTFM_MSG_ERR("[ERR]not multiple of 2!\n");
+ return HALMAC_RET_CFG_DLFW_SIZE_FAIL;
+ }
+
+ adapter->dlfw_pkt_size = size;
+
+ PLTFM_MSG_TRACE("[TRACE]Cfg max size:%X\n", size);
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * enter_cpu_sleep_mode_88xx() -wlan cpu enter sleep mode
+ * @adapter : the adapter of halmac
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+enter_cpu_sleep_mode_88xx(struct halmac_adapter *adapter)
+{
+ u32 cnt;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+ enum halmac_wlcpu_mode *cur_mode = &adapter->halmac_state.wlcpu_mode;
+
+ if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
+ return HALMAC_RET_NO_DLFW;
+
+ if (*cur_mode != HALMAC_WLCPU_ACTIVE)
+ return HALMAC_RET_ERROR_STATE;
+
+ cnt = 100;
+ while (HALMAC_REG_R8(REG_HMETFR + 3) != 0) {
+ cnt--;
+ if (cnt == 0) {
+ PLTFM_MSG_ERR("[ERR]0x1CF != 0\n");
+ return HALMAC_RET_STATE_INCORRECT;
+ }
+ PLTFM_DELAY_US(50);
+ }
+
+ HALMAC_REG_W8(REG_HMETFR + 3, ID_INFORM_ENETR_CPU_SLEEP);
+
+ *cur_mode = HALMAC_WLCPU_ENTER_SLEEP;
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * get_cpu_mode_88xx() -get wlcpu mode
+ * @adapter : the adapter of halmac
+ * @mode : cpu mode
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+get_cpu_mode_88xx(struct halmac_adapter *adapter,
+ enum halmac_wlcpu_mode *mode)
+{
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+ enum halmac_wlcpu_mode *cur_mode = &adapter->halmac_state.wlcpu_mode;
+
+ if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
+ return HALMAC_RET_NO_DLFW;
+
+ if (*cur_mode == HALMAC_WLCPU_ACTIVE) {
+ *mode = HALMAC_WLCPU_ACTIVE;
+ return HALMAC_RET_SUCCESS;
+ }
+
+ if (*cur_mode == HALMAC_WLCPU_SLEEP) {
+ *mode = HALMAC_WLCPU_SLEEP;
+ return HALMAC_RET_SUCCESS;
+ }
+
+ if (HALMAC_REG_R8(REG_MCU_TST_CFG) == ID_CHECK_ENETR_CPU_SLEEP) {
+ *mode = HALMAC_WLCPU_SLEEP;
+ HALMAC_REG_W8(REG_MCU_TST_CFG, 0);
+ } else {
+ *mode = HALMAC_WLCPU_ENTER_SLEEP;
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * send_general_info_88xx() -send general information to FW
+ * @adapter : the adapter of halmac
+ * @info : general information
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+send_general_info_88xx(struct halmac_adapter *adapter,
+ struct halmac_general_info *info)
+{
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
+ return HALMAC_RET_NO_DLFW;
+
+ if (adapter->fw_ver.h2c_version < 4)
+ return HALMAC_RET_FW_NO_SUPPORT;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (adapter->halmac_state.dlfw_state == HALMAC_DLFW_NONE) {
+ PLTFM_MSG_ERR("[ERR]no dl fw!!\n");
+ return HALMAC_RET_NO_DLFW;
+ }
+
+ status = proc_send_general_info_88xx(adapter, info);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]send gen info!!\n");
+ return status;
+ }
+
+ status = proc_send_phydm_info_88xx(adapter, info);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]send phydm info\n");
+ return status;
+ }
+
+ if (adapter->halmac_state.dlfw_state == HALMAC_DLFW_DONE)
+ adapter->halmac_state.dlfw_state = HALMAC_GEN_INFO_SENT;
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+proc_send_general_info_88xx(struct halmac_adapter *adapter,
+ struct halmac_general_info *info)
+{
+ u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };
+ u16 seq_num = 0;
+ struct halmac_h2c_header_info hdr_info;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ PLTFM_MSG_TRACE("[TRACE]%s\n", __func__);
+
+ GENERAL_INFO_SET_FW_TX_BOUNDARY(h2c_buf,
+ adapter->txff_alloc.rsvd_fw_txbuf_addr -
+ adapter->txff_alloc.rsvd_boundary);
+
+ hdr_info.sub_cmd_id = SUB_CMD_ID_GENERAL_INFO;
+ hdr_info.content_size = 4;
+ hdr_info.ack = _FALSE;
+ set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+
+ status = send_h2c_pkt_88xx(adapter, h2c_buf);
+
+ if (status != HALMAC_RET_SUCCESS)
+ PLTFM_MSG_ERR("[ERR]send h2c!!\n");
+
+ return status;
+}
+
+static enum halmac_ret_status
+proc_send_phydm_info_88xx(struct halmac_adapter *adapter,
+ struct halmac_general_info *info)
+{
+ u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };
+ u16 seq_num = 0;
+ struct halmac_h2c_header_info hdr_info;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ PLTFM_MSG_TRACE("[TRACE]%s\n", __func__);
+
+ PHYDM_INFO_SET_REF_TYPE(h2c_buf, info->rfe_type);
+ PHYDM_INFO_SET_RF_TYPE(h2c_buf, info->rf_type);
+ PHYDM_INFO_SET_CUT_VER(h2c_buf, adapter->chip_ver);
+ PHYDM_INFO_SET_RX_ANT_STATUS(h2c_buf, info->rx_ant_status);
+ PHYDM_INFO_SET_TX_ANT_STATUS(h2c_buf, info->tx_ant_status);
+
+ hdr_info.sub_cmd_id = SUB_CMD_ID_PHYDM_INFO;
+ hdr_info.content_size = 8;
+ hdr_info.ack = _FALSE;
+ set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+
+ status = send_h2c_pkt_88xx(adapter, h2c_buf);
+
+ if (status != HALMAC_RET_SUCCESS)
+ PLTFM_MSG_ERR("[ERR]send h2c!!\n");
+
+ return status;
+}
+
+/**
+ * drv_fwctrl_88xx() - send drv-defined h2c pkt
+ * @adapter : the adapter of halmac
+ * @payload : no include offload pkt h2c header
+ * @size : no include offload pkt h2c header
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+drv_fwctrl_88xx(struct halmac_adapter *adapter, u8 *payload, u32 size, u8 ack)
+{
+ u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };
+ u16 seq_num = 0;
+ struct halmac_h2c_header_info hdr_info;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (!payload)
+ return HALMAC_RET_DATA_BUF_NULL;
+
+ if (size > H2C_PKT_SIZE_88XX - H2C_PKT_HDR_SIZE_88XX)
+ return HALMAC_RET_DATA_SIZE_INCORRECT;
+
+ PLTFM_MEMCPY(h2c_buf + H2C_PKT_HDR_SIZE_88XX, payload, size);
+
+ hdr_info.sub_cmd_id = SUB_CMD_ID_FW_FWCTRL;
+ hdr_info.content_size = (u16)size;
+ hdr_info.ack = ack;
+ set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+
+ status = send_h2c_pkt_88xx(adapter, h2c_buf);
+
+ if (status != HALMAC_RET_SUCCESS)
+ PLTFM_MSG_ERR("[ERR]send h2c!!\n");
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return status;
+}
+
+#endif /* HALMAC_88XX_SUPPORT */
diff --git a/hal/halmac/halmac_88xx/halmac_fw_88xx.h b/hal/halmac/halmac_88xx/halmac_fw_88xx.h
new file mode 100644
index 0000000..f7015f6
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_fw_88xx.h
@@ -0,0 +1,61 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_FW_88XX_H_
+#define _HALMAC_FW_88XX_H_
+
+#include "../halmac_api.h"
+
+#if HALMAC_88XX_SUPPORT
+
+#define HALMC_DDMA_POLLING_COUNT 1000
+
+#endif /* HALMAC_88XX_SUPPORT */
+
+enum halmac_ret_status
+download_firmware_88xx(struct halmac_adapter *adapter, u8 *fw_bin, u32 size);
+
+enum halmac_ret_status
+free_download_firmware_88xx(struct halmac_adapter *adapter,
+ enum halmac_dlfw_mem mem_sel, u8 *fw_bin, u32 size);
+
+enum halmac_ret_status
+get_fw_version_88xx(struct halmac_adapter *adapter,
+ struct halmac_fw_version *ver);
+
+enum halmac_ret_status
+check_fw_status_88xx(struct halmac_adapter *adapter, u8 *fw_status);
+
+enum halmac_ret_status
+dump_fw_dmem_88xx(struct halmac_adapter *adapter, u8 *dmem, u32 *size);
+
+enum halmac_ret_status
+cfg_max_dl_size_88xx(struct halmac_adapter *adapter, u32 size);
+
+enum halmac_ret_status
+enter_cpu_sleep_mode_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+get_cpu_mode_88xx(struct halmac_adapter *adapter,
+ enum halmac_wlcpu_mode *mode);
+
+enum halmac_ret_status
+send_general_info_88xx(struct halmac_adapter *adapter,
+ struct halmac_general_info *info);
+
+enum halmac_ret_status
+drv_fwctrl_88xx(struct halmac_adapter *adapter, u8 *payload, u32 size, u8 ack);
+
+#endif/* _HALMAC_FW_88XX_H_ */
diff --git a/hal/halmac/halmac_88xx/halmac_gpio_88xx.c b/hal/halmac/halmac_88xx/halmac_gpio_88xx.c
new file mode 100644
index 0000000..5ed94e3
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_gpio_88xx.c
@@ -0,0 +1,411 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_gpio_88xx.h"
+
+#if HALMAC_88XX_SUPPORT
+
+/**
+ * pinmux_wl_led_mode_88xx() -control wlan led gpio function
+ * @adapter : the adapter of halmac
+ * @mode : wlan led mode
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+pinmux_wl_led_mode_88xx(struct halmac_adapter *adapter,
+ enum halmac_wlled_mode mode)
+{
+ u8 value8;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ value8 = HALMAC_REG_R8(REG_LED_CFG + 2);
+ value8 &= ~(BIT(6));
+ value8 |= BIT(3);
+ value8 &= ~(BIT(0) | BIT(1) | BIT(2));
+
+ switch (mode) {
+ case HALMAC_WLLED_MODE_TRX:
+ value8 |= 2;
+ break;
+ case HALMAC_WLLED_MODE_TX:
+ value8 |= 4;
+ break;
+ case HALMAC_WLLED_MODE_RX:
+ value8 |= 6;
+ break;
+ case HALMAC_WLLED_MODE_SW_CTRL:
+ value8 |= 0;
+ break;
+ default:
+ return HALMAC_RET_SWITCH_CASE_ERROR;
+ }
+
+ HALMAC_REG_W8(REG_LED_CFG + 2, value8);
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * pinmux_wl_led_sw_ctrl_88xx() -control wlan led on/off
+ * @adapter : the adapter of halmac
+ * @on : on(1), off(0)
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+void
+pinmux_wl_led_sw_ctrl_88xx(struct halmac_adapter *adapter, u8 on)
+{
+ u8 value8;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ value8 = HALMAC_REG_R8(REG_LED_CFG + 2);
+ value8 = (on == 0) ? value8 | BIT(3) : value8 & ~(BIT(3));
+
+ HALMAC_REG_W8(REG_LED_CFG + 2, value8);
+}
+
+/**
+ * pinmux_sdio_int_polarity_88xx() -control sdio int polarity
+ * @adapter : the adapter of halmac
+ * @low_active : low active(1), high active(0)
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+void
+pinmux_sdio_int_polarity_88xx(struct halmac_adapter *adapter, u8 low_active)
+{
+ u8 value8;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ value8 = HALMAC_REG_R8(REG_SYS_SDIO_CTRL + 2);
+ value8 = (low_active == 0) ? value8 | BIT(3) : value8 & ~(BIT(3));
+
+ HALMAC_REG_W8(REG_SYS_SDIO_CTRL + 2, value8);
+}
+
+/**
+ * pinmux_gpio_mode_88xx() -control gpio io mode
+ * @adapter : the adapter of halmac
+ * @gpio_id : gpio0~15(0~15)
+ * @output : output(1), input(0)
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+pinmux_gpio_mode_88xx(struct halmac_adapter *adapter, u8 gpio_id, u8 output)
+{
+ u16 value16;
+ u8 in_out;
+ u32 offset;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ if (gpio_id <= 7)
+ offset = REG_GPIO_PIN_CTRL + 2;
+ else if (gpio_id >= 8 && gpio_id <= 15)
+ offset = REG_GPIO_EXT_CTRL + 2;
+ else
+ return HALMAC_RET_WRONG_GPIO;
+
+ in_out = (output == 0) ? 0 : 1;
+ gpio_id &= (8 - 1);
+
+ value16 = HALMAC_REG_R16(offset);
+ value16 &= ~((1 << gpio_id) | (1 << gpio_id << 8));
+ value16 |= (in_out << gpio_id);
+ HALMAC_REG_W16(offset, value16);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * pinmux_gpio_output_88xx() -control gpio output high/low
+ * @adapter : the adapter of halmac
+ * @gpio_id : gpio0~15(0~15)
+ * @high : high(1), low(0)
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+pinmux_gpio_output_88xx(struct halmac_adapter *adapter, u8 gpio_id, u8 high)
+{
+ u8 value8;
+ u8 hi_low;
+ u32 offset;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ if (gpio_id <= 7)
+ offset = REG_GPIO_PIN_CTRL + 1;
+ else if (gpio_id >= 8 && gpio_id <= 15)
+ offset = REG_GPIO_EXT_CTRL + 1;
+ else
+ return HALMAC_RET_WRONG_GPIO;
+
+ hi_low = (high == 0) ? 0 : 1;
+ gpio_id &= (8 - 1);
+
+ value8 = HALMAC_REG_R8(offset);
+ value8 &= ~(1 << gpio_id);
+ value8 |= (hi_low << gpio_id);
+ HALMAC_REG_W8(offset, value8);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * halmac_pinmux_status_88xx() -get current gpio status(high/low)
+ * @adapter : the adapter of halmac
+ * @pin_id : 0~15(0~15)
+ * @phigh : high(1), low(0)
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+pinmux_pin_status_88xx(struct halmac_adapter *adapter, u8 pin_id, u8 *high)
+{
+ u8 value8;
+ u32 offset;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ if (pin_id <= 7)
+ offset = REG_GPIO_PIN_CTRL;
+ else if (pin_id >= 8 && pin_id <= 15)
+ offset = REG_GPIO_EXT_CTRL;
+ else
+ return HALMAC_RET_WRONG_GPIO;
+
+ pin_id &= (8 - 1);
+
+ value8 = HALMAC_REG_R8(offset);
+ *high = (value8 & (1 << pin_id)) >> pin_id;
+
+ return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+pinmux_parser_88xx(struct halmac_adapter *adapter,
+ const struct halmac_gpio_pimux_list *list, u32 size,
+ u32 gpio_id, u32 *cur_func)
+{
+ u32 i;
+ u8 value8;
+ const struct halmac_gpio_pimux_list *cur_list = list;
+ enum halmac_gpio_cfg_state *state;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ state = &adapter->halmac_state.gpio_cfg_state;
+
+ if (*state == HALMAC_GPIO_CFG_STATE_BUSY)
+ return HALMAC_RET_BUSY_STATE;
+
+ *state = HALMAC_GPIO_CFG_STATE_BUSY;
+
+ for (i = 0; i < size; i++) {
+ if (gpio_id != cur_list->id) {
+ PLTFM_MSG_ERR("[ERR]offset:%X, value:%X, func:%X\n",
+ cur_list->offset, cur_list->value,
+ cur_list->func);
+ PLTFM_MSG_ERR("[ERR]id1 : %X, id2 : %X\n",
+ gpio_id, cur_list->id);
+ *state = HALMAC_GPIO_CFG_STATE_IDLE;
+ return HALMAC_RET_GET_PINMUX_ERR;
+ }
+ value8 = HALMAC_REG_R8(cur_list->offset);
+ value8 &= cur_list->msk;
+ if (value8 == cur_list->value) {
+ *cur_func = cur_list->func;
+ break;
+ }
+ cur_list++;
+ }
+
+ *state = HALMAC_GPIO_CFG_STATE_IDLE;
+
+ if (i == size)
+ return HALMAC_RET_GET_PINMUX_ERR;
+
+ return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+pinmux_switch_88xx(struct halmac_adapter *adapter,
+ const struct halmac_gpio_pimux_list *list, u32 size,
+ u32 gpio_id, enum halmac_gpio_func gpio_func)
+{
+ u32 i;
+ u8 value8;
+ u16 switch_func;
+ const struct halmac_gpio_pimux_list *cur_list = list;
+ enum halmac_gpio_cfg_state *state;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ state = &adapter->halmac_state.gpio_cfg_state;
+
+ if (*state == HALMAC_GPIO_CFG_STATE_BUSY)
+ return HALMAC_RET_BUSY_STATE;
+
+ switch (gpio_func) {
+ case HALMAC_GPIO_FUNC_WL_LED:
+ switch_func = HALMAC_WL_LED;
+ break;
+ case HALMAC_GPIO_FUNC_SDIO_INT:
+ switch_func = HALMAC_SDIO_INT;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_0:
+ case HALMAC_GPIO_FUNC_SW_IO_1:
+ case HALMAC_GPIO_FUNC_SW_IO_2:
+ case HALMAC_GPIO_FUNC_SW_IO_3:
+ case HALMAC_GPIO_FUNC_SW_IO_4:
+ case HALMAC_GPIO_FUNC_SW_IO_5:
+ case HALMAC_GPIO_FUNC_SW_IO_6:
+ case HALMAC_GPIO_FUNC_SW_IO_7:
+ case HALMAC_GPIO_FUNC_SW_IO_8:
+ case HALMAC_GPIO_FUNC_SW_IO_9:
+ case HALMAC_GPIO_FUNC_SW_IO_10:
+ case HALMAC_GPIO_FUNC_SW_IO_11:
+ case HALMAC_GPIO_FUNC_SW_IO_12:
+ case HALMAC_GPIO_FUNC_SW_IO_13:
+ case HALMAC_GPIO_FUNC_SW_IO_14:
+ case HALMAC_GPIO_FUNC_SW_IO_15:
+ switch_func = HALMAC_SW_IO;
+ break;
+ default:
+ return HALMAC_RET_SWITCH_CASE_ERROR;
+ }
+
+ for (i = 0; i < size; i++) {
+ if (gpio_id != cur_list->id) {
+ PLTFM_MSG_ERR("[ERR]offset:%X, value:%X, func:%X\n",
+ cur_list->offset, cur_list->value,
+ cur_list->func);
+ PLTFM_MSG_ERR("[ERR]id1 : %X, id2 : %X\n",
+ gpio_id, cur_list->id);
+ return HALMAC_RET_GET_PINMUX_ERR;
+ }
+
+ if (switch_func == cur_list->func)
+ break;
+
+ cur_list++;
+ }
+
+ if (i == size) {
+ PLTFM_MSG_ERR("[ERR]gpio func error:%X %X\n",
+ gpio_id, cur_list->id);
+ return HALMAC_RET_GET_PINMUX_ERR;
+ }
+
+ *state = HALMAC_GPIO_CFG_STATE_BUSY;
+
+ cur_list = list;
+ for (i = 0; i < size; i++) {
+ value8 = HALMAC_REG_R8(cur_list->offset);
+ value8 &= ~(cur_list->msk);
+
+ if (switch_func == cur_list->func) {
+ value8 |= (cur_list->value & cur_list->msk);
+ HALMAC_REG_W8(cur_list->offset, value8);
+ break;
+ }
+
+ value8 |= (~cur_list->value & cur_list->msk);
+ HALMAC_REG_W8(cur_list->offset, value8);
+
+ cur_list++;
+ }
+
+ *state = HALMAC_GPIO_CFG_STATE_IDLE;
+
+ return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+pinmux_record_88xx(struct halmac_adapter *adapter,
+ enum halmac_gpio_func gpio_func, u8 val)
+{
+ switch (gpio_func) {
+ case HALMAC_GPIO_FUNC_WL_LED:
+ adapter->pinmux_info.wl_led = val;
+ break;
+ case HALMAC_GPIO_FUNC_SDIO_INT:
+ adapter->pinmux_info.sdio_int = val;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_0:
+ adapter->pinmux_info.sw_io_0 = val;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_1:
+ adapter->pinmux_info.sw_io_1 = val;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_2:
+ adapter->pinmux_info.sw_io_2 = val;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_3:
+ adapter->pinmux_info.sw_io_3 = val;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_4:
+ adapter->pinmux_info.sw_io_4 = val;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_5:
+ adapter->pinmux_info.sw_io_5 = val;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_6:
+ adapter->pinmux_info.sw_io_6 = val;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_7:
+ adapter->pinmux_info.sw_io_7 = val;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_8:
+ adapter->pinmux_info.sw_io_8 = val;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_9:
+ adapter->pinmux_info.sw_io_9 = val;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_10:
+ adapter->pinmux_info.sw_io_10 = val;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_11:
+ adapter->pinmux_info.sw_io_11 = val;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_12:
+ adapter->pinmux_info.sw_io_12 = val;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_13:
+ adapter->pinmux_info.sw_io_13 = val;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_14:
+ adapter->pinmux_info.sw_io_14 = val;
+ break;
+ case HALMAC_GPIO_FUNC_SW_IO_15:
+ adapter->pinmux_info.sw_io_15 = val;
+ break;
+ default:
+ return HALMAC_RET_GET_PINMUX_ERR;
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+#endif /* HALMAC_88XX_SUPPORT */
+
diff --git a/hal/halmac/halmac_88xx/halmac_gpio_88xx.h b/hal/halmac/halmac_88xx/halmac_gpio_88xx.h
new file mode 100644
index 0000000..63ffac4
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_gpio_88xx.h
@@ -0,0 +1,59 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_GPIO_88XX_H_
+#define _HALMAC_GPIO_88XX_H_
+
+#include "../halmac_api.h"
+#include "../halmac_gpio_cmd.h"
+
+#if HALMAC_88XX_SUPPORT
+
+enum halmac_ret_status
+pinmux_wl_led_mode_88xx(struct halmac_adapter *adapter,
+ enum halmac_wlled_mode mode);
+
+void
+pinmux_wl_led_sw_ctrl_88xx(struct halmac_adapter *adapter, u8 on);
+
+void
+pinmux_sdio_int_polarity_88xx(struct halmac_adapter *adapter, u8 low_active);
+
+enum halmac_ret_status
+pinmux_gpio_mode_88xx(struct halmac_adapter *adapter, u8 gpio_id, u8 output);
+
+enum halmac_ret_status
+pinmux_gpio_output_88xx(struct halmac_adapter *adapter, u8 gpio_id, u8 high);
+
+enum halmac_ret_status
+pinmux_pin_status_88xx(struct halmac_adapter *adapter, u8 pin_id, u8 *high);
+
+enum halmac_ret_status
+pinmux_parser_88xx(struct halmac_adapter *adapter,
+ const struct halmac_gpio_pimux_list *list, u32 size,
+ u32 gpio_id, u32 *cur_func);
+
+enum halmac_ret_status
+pinmux_switch_88xx(struct halmac_adapter *adapter,
+ const struct halmac_gpio_pimux_list *list, u32 size,
+ u32 gpio_id, enum halmac_gpio_func gpio_func);
+
+enum halmac_ret_status
+pinmux_record_88xx(struct halmac_adapter *adapter,
+ enum halmac_gpio_func gpio_func, u8 val);
+
+#endif /* HALMAC_88XX_SUPPORT */
+
+#endif/* _HALMAC_GPIO_88XX_H_ */
diff --git a/hal/halmac/halmac_88xx/halmac_init_88xx.c b/hal/halmac/halmac_88xx/halmac_init_88xx.c
new file mode 100644
index 0000000..93fbcf7
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_init_88xx.c
@@ -0,0 +1,1081 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_init_88xx.h"
+#include "halmac_88xx_cfg.h"
+#include "halmac_fw_88xx.h"
+#include "halmac_common_88xx.h"
+#include "halmac_cfg_wmac_88xx.h"
+#include "halmac_efuse_88xx.h"
+#include "halmac_mimo_88xx.h"
+#include "halmac_bb_rf_88xx.h"
+#include "halmac_sdio_88xx.h"
+#include "halmac_usb_88xx.h"
+#include "halmac_pcie_88xx.h"
+#include "halmac_gpio_88xx.h"
+#include "halmac_flash_88xx.h"
+
+#if HALMAC_8822B_SUPPORT
+#include "halmac_8822b/halmac_init_8822b.h"
+#endif
+
+#if HALMAC_8821C_SUPPORT
+#include "halmac_8821c/halmac_init_8821c.h"
+#endif
+
+#if HALMAC_8822C_SUPPORT
+#include "halmac_8822c/halmac_init_8822c.h"
+#endif
+
+#if HALMAC_PLATFORM_TESTPROGRAM
+#include "halmisc_api_88xx.h"
+#endif
+
+#if HALMAC_88XX_SUPPORT
+
+#define PLTFM_INFO_MALLOC_MAX_SIZE 16384
+#define PLTFM_INFO_RSVD_PG_SIZE 16384
+#define DLFW_PKT_MAX_SIZE 8192 /* need multiple of 2 */
+
+#define SYS_FUNC_EN 0xDC
+#define WLAN_SLOT_TIME 0x05
+#define WLAN_PIFS_TIME 0x19
+#define WLAN_SIFS_CCK_CONT_TX 0xA
+#define WLAN_SIFS_OFDM_CONT_TX 0xA
+#define WLAN_SIFS_CCK_TRX 0x10
+#define WLAN_SIFS_OFDM_TRX 0x10
+#define WLAN_VO_TXOP_LIMIT 0x186 /* unit : 32us */
+#define WLAN_VI_TXOP_LIMIT 0x3BC /* unit : 32us */
+#define WLAN_RDG_NAV 0x05
+#define WLAN_TXOP_NAV 0x1B
+#define WLAN_CCK_RX_TSF 0x30
+#define WLAN_OFDM_RX_TSF 0x30
+#define WLAN_TBTT_PROHIBIT 0x04 /* unit : 32us */
+#define WLAN_TBTT_HOLD_TIME 0x064 /* unit : 32us */
+#define WLAN_DRV_EARLY_INT 0x04
+#define WLAN_BCN_DMA_TIME 0x02
+#define WLAN_ACK_TO_CCK 0x40
+
+#define WLAN_RX_FILTER0 0x0FFFFFFF
+#define WLAN_RX_FILTER2 0xFFFF
+#define WLAN_RCR_CFG 0xE400220E
+#define WLAN_RXPKT_MAX_SZ 12288
+#define WLAN_RXPKT_MAX_SZ_512 (WLAN_RXPKT_MAX_SZ >> 9)
+
+#define WLAN_TX_FUNC_CFG1 0x30
+#define WLAN_TX_FUNC_CFG2 0x30
+#define WLAN_MAC_OPT_NORM_FUNC1 0x98
+#define WLAN_MAC_OPT_LB_FUNC1 0x80
+#define WLAN_MAC_OPT_FUNC2 0x30810041
+
+#define WLAN_SIFS_CFG (WLAN_SIFS_CCK_CONT_TX | \
+ (WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \
+ (WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \
+ (WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX))
+
+#define WLAN_TBTT_TIME (WLAN_TBTT_PROHIBIT |\
+ (WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP))
+
+#define WLAN_NAV_CFG (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16))
+#define WLAN_RX_TSF_CFG (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8)
+
+static void
+init_state_machine_88xx(struct halmac_adapter *adapter);
+
+static enum halmac_ret_status
+verify_io_88xx(struct halmac_adapter *adapter);
+
+static enum halmac_ret_status
+verify_send_rsvd_page_88xx(struct halmac_adapter *adapter);
+
+void
+init_adapter_param_88xx(struct halmac_adapter *adapter)
+{
+ adapter->api_registry.rx_exp_en = 1;
+ adapter->api_registry.la_mode_en = 1;
+ adapter->api_registry.cfg_drv_rsvd_pg_en = 1;
+ adapter->api_registry.sdio_cmd53_4byte_en = 1;
+
+ adapter->efuse_map = (u8 *)NULL;
+ adapter->efuse_map_valid = _FALSE;
+ adapter->efuse_end = 0;
+
+ adapter->dlfw_pkt_size = DLFW_PKT_MAX_SIZE;
+ adapter->pltfm_info.malloc_size = PLTFM_INFO_MALLOC_MAX_SIZE;
+ adapter->pltfm_info.rsvd_pg_size = PLTFM_INFO_RSVD_PG_SIZE;
+
+ adapter->cfg_param_info.buf = NULL;
+ adapter->cfg_param_info.buf_wptr = NULL;
+ adapter->cfg_param_info.num = 0;
+ adapter->cfg_param_info.full_fifo_mode = _FALSE;
+ adapter->cfg_param_info.buf_size = 0;
+ adapter->cfg_param_info.avl_buf_size = 0;
+ adapter->cfg_param_info.offset_accum = 0;
+ adapter->cfg_param_info.value_accum = 0;
+
+ adapter->ch_sw_info.buf = NULL;
+ adapter->ch_sw_info.buf_wptr = NULL;
+ adapter->ch_sw_info.extra_info_en = 0;
+ adapter->ch_sw_info.buf_size = 0;
+ adapter->ch_sw_info.avl_buf_size = 0;
+ adapter->ch_sw_info.total_size = 0;
+ adapter->ch_sw_info.ch_num = 0;
+
+ adapter->drv_info_size = 0;
+ adapter->tx_desc_transfer = _FALSE;
+
+ adapter->txff_alloc.tx_fifo_pg_num = 0;
+ adapter->txff_alloc.acq_pg_num = 0;
+ adapter->txff_alloc.rsvd_boundary = 0;
+ adapter->txff_alloc.rsvd_drv_addr = 0;
+ adapter->txff_alloc.rsvd_h2c_info_addr = 0;
+ adapter->txff_alloc.rsvd_h2cq_addr = 0;
+ adapter->txff_alloc.rsvd_cpu_instr_addr = 0;
+ adapter->txff_alloc.rsvd_fw_txbuf_addr = 0;
+ adapter->txff_alloc.pub_queue_pg_num = 0;
+ adapter->txff_alloc.high_queue_pg_num = 0;
+ adapter->txff_alloc.low_queue_pg_num = 0;
+ adapter->txff_alloc.normal_queue_pg_num = 0;
+ adapter->txff_alloc.extra_queue_pg_num = 0;
+
+ adapter->txff_alloc.la_mode = HALMAC_LA_MODE_DISABLE;
+ adapter->txff_alloc.rx_fifo_exp_mode =
+ HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE;
+
+ adapter->hw_cfg_info.chk_security_keyid = 0;
+ adapter->hw_cfg_info.acq_num = 8;
+ adapter->hw_cfg_info.page_size = TX_PAGE_SIZE_88XX;
+ adapter->hw_cfg_info.tx_align_size = TX_ALIGN_SIZE_88XX;
+ adapter->hw_cfg_info.txdesc_size = TX_DESC_SIZE_88XX;
+ adapter->hw_cfg_info.rxdesc_size = RX_DESC_SIZE_88XX;
+ adapter->hw_cfg_info.rx_desc_fifo_size = 0;
+
+ adapter->sdio_cmd53_4byte = HALMAC_SDIO_CMD53_4BYTE_MODE_DISABLE;
+ adapter->sdio_hw_info.io_hi_speed_flag = 0;
+ adapter->sdio_hw_info.io_indir_flag = 0;
+ adapter->sdio_hw_info.spec_ver = HALMAC_SDIO_SPEC_VER_2_00;
+ adapter->sdio_hw_info.clock_speed = 50;
+ adapter->sdio_hw_info.block_size = 512;
+ adapter->sdio_hw_info.tx_seq = 1;
+ adapter->sdio_fs.macid_map = (u8 *)NULL;
+
+ adapter->pinmux_info.wl_led = 0;
+ adapter->pinmux_info.sdio_int = 0;
+ adapter->pinmux_info.sw_io_0 = 0;
+ adapter->pinmux_info.sw_io_1 = 0;
+ adapter->pinmux_info.sw_io_2 = 0;
+ adapter->pinmux_info.sw_io_3 = 0;
+ adapter->pinmux_info.sw_io_4 = 0;
+ adapter->pinmux_info.sw_io_5 = 0;
+ adapter->pinmux_info.sw_io_6 = 0;
+ adapter->pinmux_info.sw_io_7 = 0;
+ adapter->pinmux_info.sw_io_8 = 0;
+ adapter->pinmux_info.sw_io_9 = 0;
+ adapter->pinmux_info.sw_io_10 = 0;
+ adapter->pinmux_info.sw_io_11 = 0;
+ adapter->pinmux_info.sw_io_12 = 0;
+ adapter->pinmux_info.sw_io_13 = 0;
+ adapter->pinmux_info.sw_io_14 = 0;
+ adapter->pinmux_info.sw_io_15 = 0;
+
+ adapter->pcie_refautok_en = 1;
+ adapter->pwr_off_flow_flag = 0;
+
+ init_adapter_dynamic_param_88xx(adapter);
+ init_state_machine_88xx(adapter);
+}
+
+void
+init_adapter_dynamic_param_88xx(struct halmac_adapter *adapter)
+{
+ adapter->h2c_info.seq_num = 0;
+ adapter->h2c_info.buf_fs = 0;
+}
+
+enum halmac_ret_status
+mount_api_88xx(struct halmac_adapter *adapter)
+{
+ struct halmac_api *api = NULL;
+
+ adapter->halmac_api =
+ (struct halmac_api *)PLTFM_MALLOC(sizeof(struct halmac_api));
+ if (!adapter->halmac_api)
+ return HALMAC_RET_MALLOC_FAIL;
+
+ api = (struct halmac_api *)adapter->halmac_api;
+
+ api->halmac_read_efuse = NULL;
+ api->halmac_write_efuse = NULL;
+
+ /* Mount function pointer */
+ api->halmac_register_api = register_api_88xx;
+ api->halmac_download_firmware = download_firmware_88xx;
+ api->halmac_free_download_firmware = free_download_firmware_88xx;
+ api->halmac_get_fw_version = get_fw_version_88xx;
+ api->halmac_cfg_mac_addr = cfg_mac_addr_88xx;
+ api->halmac_cfg_bssid = cfg_bssid_88xx;
+ api->halmac_cfg_transmitter_addr = cfg_transmitter_addr_88xx;
+ api->halmac_cfg_net_type = cfg_net_type_88xx;
+ api->halmac_cfg_tsf_rst = cfg_tsf_rst_88xx;
+ api->halmac_cfg_bcn_space = cfg_bcn_space_88xx;
+ api->halmac_rw_bcn_ctrl = rw_bcn_ctrl_88xx;
+ api->halmac_cfg_multicast_addr = cfg_multicast_addr_88xx;
+ api->halmac_pre_init_system_cfg = pre_init_system_cfg_88xx;
+ api->halmac_init_system_cfg = init_system_cfg_88xx;
+ api->halmac_init_edca_cfg = init_edca_cfg_88xx;
+ api->halmac_cfg_operation_mode = cfg_operation_mode_88xx;
+ api->halmac_cfg_ch_bw = cfg_ch_bw_88xx;
+ api->halmac_cfg_bw = cfg_bw_88xx;
+ api->halmac_init_wmac_cfg = init_wmac_cfg_88xx;
+ api->halmac_init_mac_cfg = init_mac_cfg_88xx;
+ api->halmac_dump_efuse_map = dump_efuse_map_88xx;
+ api->halmac_dump_efuse_map_bt = dump_efuse_map_bt_88xx;
+ api->halmac_write_efuse_bt = write_efuse_bt_88xx;
+ api->halmac_read_efuse_bt = read_efuse_bt_88xx;
+ api->halmac_cfg_efuse_auto_check = cfg_efuse_auto_check_88xx;
+ api->halmac_dump_logical_efuse_map = dump_log_efuse_map_88xx;
+ api->halmac_pg_efuse_by_map = pg_efuse_by_map_88xx;
+ api->halmac_mask_logical_efuse = mask_log_efuse_88xx;
+ api->halmac_get_efuse_size = get_efuse_size_88xx;
+ api->halmac_get_efuse_available_size = get_efuse_available_size_88xx;
+ api->halmac_get_c2h_info = get_c2h_info_88xx;
+
+ api->halmac_get_logical_efuse_size = get_log_efuse_size_88xx;
+
+ api->halmac_write_logical_efuse = write_log_efuse_88xx;
+ api->halmac_read_logical_efuse = read_logical_efuse_88xx;
+
+ api->halmac_ofld_func_cfg = ofld_func_cfg_88xx;
+ api->halmac_h2c_lb = h2c_lb_88xx;
+ api->halmac_debug = mac_debug_88xx;
+ api->halmac_cfg_parameter = cfg_parameter_88xx;
+ api->halmac_update_datapack = update_datapack_88xx;
+ api->halmac_run_datapack = run_datapack_88xx;
+ api->halmac_send_bt_coex = send_bt_coex_88xx;
+ api->halmac_verify_platform_api = verify_platform_api_88xx;
+ api->halmac_update_packet = update_packet_88xx;
+ api->halmac_bcn_ie_filter = bcn_ie_filter_88xx;
+ api->halmac_cfg_txbf = cfg_txbf_88xx;
+ api->halmac_cfg_mumimo = cfg_mumimo_88xx;
+ api->halmac_cfg_sounding = cfg_sounding_88xx;
+ api->halmac_del_sounding = del_sounding_88xx;
+ api->halmac_su_bfer_entry_init = su_bfer_entry_init_88xx;
+ api->halmac_su_bfee_entry_init = su_bfee_entry_init_88xx;
+ api->halmac_mu_bfer_entry_init = mu_bfer_entry_init_88xx;
+ api->halmac_mu_bfee_entry_init = mu_bfee_entry_init_88xx;
+ api->halmac_su_bfer_entry_del = su_bfer_entry_del_88xx;
+ api->halmac_su_bfee_entry_del = su_bfee_entry_del_88xx;
+ api->halmac_mu_bfer_entry_del = mu_bfer_entry_del_88xx;
+ api->halmac_mu_bfee_entry_del = mu_bfee_entry_del_88xx;
+
+ api->halmac_add_ch_info = add_ch_info_88xx;
+ api->halmac_add_extra_ch_info = add_extra_ch_info_88xx;
+ api->halmac_ctrl_ch_switch = ctrl_ch_switch_88xx;
+ api->halmac_p2pps = p2pps_88xx;
+ api->halmac_clear_ch_info = clear_ch_info_88xx;
+ api->halmac_send_general_info = send_general_info_88xx;
+
+ api->halmac_start_iqk = start_iqk_88xx;
+ api->halmac_ctrl_pwr_tracking = ctrl_pwr_tracking_88xx;
+ api->halmac_psd = psd_88xx;
+ api->halmac_cfg_la_mode = cfg_la_mode_88xx;
+ api->halmac_cfg_rxff_expand_mode = cfg_rxfifo_expand_mode_88xx;
+
+ api->halmac_config_security = config_security_88xx;
+ api->halmac_get_used_cam_entry_num = get_used_cam_entry_num_88xx;
+ api->halmac_read_cam_entry = read_cam_entry_88xx;
+ api->halmac_write_cam = write_cam_88xx;
+ api->halmac_clear_cam_entry = clear_cam_entry_88xx;
+
+ api->halmac_cfg_drv_rsvd_pg_num = cfg_drv_rsvd_pg_num_88xx;
+ api->halmac_get_chip_version = get_version_88xx;
+
+ api->halmac_query_status = query_status_88xx;
+ api->halmac_reset_feature = reset_ofld_feature_88xx;
+ api->halmac_check_fw_status = check_fw_status_88xx;
+ api->halmac_dump_fw_dmem = dump_fw_dmem_88xx;
+ api->halmac_cfg_max_dl_size = cfg_max_dl_size_88xx;
+
+ api->halmac_dump_fifo = dump_fifo_88xx;
+ api->halmac_get_fifo_size = get_fifo_size_88xx;
+
+ api->halmac_chk_txdesc = chk_txdesc_88xx;
+ api->halmac_dl_drv_rsvd_page = dl_drv_rsvd_page_88xx;
+ api->halmac_cfg_csi_rate = cfg_csi_rate_88xx;
+
+ api->halmac_sdio_cmd53_4byte = sdio_cmd53_4byte_88xx;
+ api->halmac_sdio_hw_info = sdio_hw_info_88xx;
+
+ api->halmac_init_sdio_cfg = init_sdio_cfg_88xx;
+ api->halmac_init_usb_cfg = init_usb_cfg_88xx;
+ api->halmac_init_pcie_cfg = init_pcie_cfg_88xx;
+ api->halmac_deinit_sdio_cfg = deinit_sdio_cfg_88xx;
+ api->halmac_deinit_usb_cfg = deinit_usb_cfg_88xx;
+ api->halmac_deinit_pcie_cfg = deinit_pcie_cfg_88xx;
+ api->halmac_txfifo_is_empty = txfifo_is_empty_88xx;
+ api->halmac_download_flash = download_flash_88xx;
+ api->halmac_read_flash = read_flash_88xx;
+ api->halmac_erase_flash = erase_flash_88xx;
+ api->halmac_check_flash = check_flash_88xx;
+ api->halmac_cfg_edca_para = cfg_edca_para_88xx;
+ api->halmac_pinmux_wl_led_mode = pinmux_wl_led_mode_88xx;
+ api->halmac_pinmux_wl_led_sw_ctrl = pinmux_wl_led_sw_ctrl_88xx;
+ api->halmac_pinmux_sdio_int_polarity = pinmux_sdio_int_polarity_88xx;
+ api->halmac_pinmux_gpio_mode = pinmux_gpio_mode_88xx;
+ api->halmac_pinmux_gpio_output = pinmux_gpio_output_88xx;
+ api->halmac_pinmux_pin_status = pinmux_pin_status_88xx;
+
+ api->halmac_rx_cut_amsdu_cfg = rx_cut_amsdu_cfg_88xx;
+ api->halmac_fw_snding = fw_snding_88xx;
+ api->halmac_get_mac_addr = get_mac_addr_88xx;
+
+ api->halmac_enter_cpu_sleep_mode = enter_cpu_sleep_mode_88xx;
+ api->halmac_get_cpu_mode = get_cpu_mode_88xx;
+ api->halmac_drv_fwctrl = drv_fwctrl_88xx;
+ api->halmac_en_ref_autok_pcie = en_ref_autok_88xx;
+
+ if (adapter->intf == HALMAC_INTERFACE_SDIO) {
+ api->halmac_cfg_rx_aggregation = cfg_sdio_rx_agg_88xx;
+ api->halmac_init_interface_cfg = init_sdio_cfg_88xx;
+ api->halmac_deinit_interface_cfg = deinit_sdio_cfg_88xx;
+ api->halmac_cfg_tx_agg_align = cfg_txagg_sdio_align_88xx;
+ api->halmac_set_bulkout_num = set_sdio_bulkout_num_88xx;
+ api->halmac_get_usb_bulkout_id = get_sdio_bulkout_id_88xx;
+ api->halmac_reg_read_indirect_32 = sdio_indirect_reg_r32_88xx;
+ api->halmac_reg_sdio_cmd53_read_n = sdio_reg_rn_88xx;
+ } else if (adapter->intf == HALMAC_INTERFACE_USB) {
+ api->halmac_cfg_rx_aggregation = cfg_usb_rx_agg_88xx;
+ api->halmac_init_interface_cfg = init_usb_cfg_88xx;
+ api->halmac_deinit_interface_cfg = deinit_usb_cfg_88xx;
+ api->halmac_cfg_tx_agg_align = cfg_txagg_usb_align_88xx;
+ api->halmac_tx_allowed_sdio = tx_allowed_usb_88xx;
+ api->halmac_set_bulkout_num = set_usb_bulkout_num_88xx;
+ api->halmac_get_sdio_tx_addr = get_usb_tx_addr_88xx;
+ api->halmac_get_usb_bulkout_id = get_usb_bulkout_id_88xx;
+ api->halmac_reg_read_8 = reg_r8_usb_88xx;
+ api->halmac_reg_write_8 = reg_w8_usb_88xx;
+ api->halmac_reg_read_16 = reg_r16_usb_88xx;
+ api->halmac_reg_write_16 = reg_w16_usb_88xx;
+ api->halmac_reg_read_32 = reg_r32_usb_88xx;
+ api->halmac_reg_write_32 = reg_w32_usb_88xx;
+ api->halmac_reg_read_indirect_32 = usb_indirect_reg_r32_88xx;
+ api->halmac_reg_sdio_cmd53_read_n = usb_reg_rn_88xx;
+ } else if (adapter->intf == HALMAC_INTERFACE_PCIE) {
+ api->halmac_cfg_rx_aggregation = cfg_pcie_rx_agg_88xx;
+ api->halmac_init_interface_cfg = init_pcie_cfg_88xx;
+ api->halmac_deinit_interface_cfg = deinit_pcie_cfg_88xx;
+ api->halmac_cfg_tx_agg_align = cfg_txagg_pcie_align_88xx;
+ api->halmac_tx_allowed_sdio = tx_allowed_pcie_88xx;
+ api->halmac_set_bulkout_num = set_pcie_bulkout_num_88xx;
+ api->halmac_get_sdio_tx_addr = get_pcie_tx_addr_88xx;
+ api->halmac_get_usb_bulkout_id = get_pcie_bulkout_id_88xx;
+ api->halmac_reg_read_8 = reg_r8_pcie_88xx;
+ api->halmac_reg_write_8 = reg_w8_pcie_88xx;
+ api->halmac_reg_read_16 = reg_r16_pcie_88xx;
+ api->halmac_reg_write_16 = reg_w16_pcie_88xx;
+ api->halmac_reg_read_32 = reg_r32_pcie_88xx;
+ api->halmac_reg_write_32 = reg_w32_pcie_88xx;
+ api->halmac_reg_read_indirect_32 = pcie_indirect_reg_r32_88xx;
+ api->halmac_reg_sdio_cmd53_read_n = pcie_reg_rn_88xx;
+ } else {
+ PLTFM_MSG_ERR("[ERR]Set halmac io function Error!!\n");
+ }
+
+ if (adapter->chip_id == HALMAC_CHIP_ID_8822B) {
+#if HALMAC_8822B_SUPPORT
+ mount_api_8822b(adapter);
+#endif
+ } else if (adapter->chip_id == HALMAC_CHIP_ID_8821C) {
+#if HALMAC_8821C_SUPPORT
+ mount_api_8821c(adapter);
+#endif
+ } else if (adapter->chip_id == HALMAC_CHIP_ID_8822C) {
+#if HALMAC_8822C_SUPPORT
+ mount_api_8822c(adapter);
+#endif
+ } else {
+ PLTFM_MSG_ERR("[ERR]Chip ID undefine!!\n");
+ return HALMAC_RET_CHIP_NOT_SUPPORT;
+ }
+
+#if HALMAC_PLATFORM_TESTPROGRAM
+ halmac_mount_misc_api_88xx(adapter);
+#endif
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static void
+init_state_machine_88xx(struct halmac_adapter *adapter)
+{
+ struct halmac_state *state = &adapter->halmac_state;
+
+ init_ofld_feature_state_machine_88xx(adapter);
+
+ state->api_state = HALMAC_API_STATE_INIT;
+
+ state->dlfw_state = HALMAC_DLFW_NONE;
+ state->mac_pwr = HALMAC_MAC_POWER_OFF;
+ state->gpio_cfg_state = HALMAC_GPIO_CFG_STATE_IDLE;
+ state->rsvd_pg_state = HALMAC_RSVD_PG_STATE_IDLE;
+}
+
+void
+init_ofld_feature_state_machine_88xx(struct halmac_adapter *adapter)
+{
+ struct halmac_state *state = &adapter->halmac_state;
+
+ state->efuse_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;
+ state->efuse_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+ state->efuse_state.seq_num = adapter->h2c_info.seq_num;
+
+ state->cfg_param_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;
+ state->cfg_param_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+ state->cfg_param_state.seq_num = adapter->h2c_info.seq_num;
+
+ state->scan_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;
+ state->scan_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+ state->scan_state.seq_num = adapter->h2c_info.seq_num;
+
+ state->update_pkt_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+ state->update_pkt_state.seq_num = adapter->h2c_info.seq_num;
+
+ state->iqk_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+ state->iqk_state.seq_num = adapter->h2c_info.seq_num;
+
+ state->pwr_trk_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+ state->pwr_trk_state.seq_num = adapter->h2c_info.seq_num;
+
+ state->psd_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+ state->psd_state.seq_num = adapter->h2c_info.seq_num;
+ state->psd_state.data_size = 0;
+ state->psd_state.seg_size = 0;
+ state->psd_state.data = NULL;
+
+ state->fw_snding_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;
+ state->fw_snding_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+ state->fw_snding_state.seq_num = adapter->h2c_info.seq_num;
+
+ state->wlcpu_mode = HALMAC_WLCPU_ACTIVE;
+}
+
+/**
+ * register_api_88xx() - register feature list
+ * @adapter
+ * @registry : feature list, 1->enable 0->disable
+ * Author : Ivan Lin
+ *
+ * Default is enable all api registry
+ *
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+register_api_88xx(struct halmac_adapter *adapter,
+ struct halmac_api_registry *registry)
+{
+ if (!registry)
+ return HALMAC_RET_NULL_POINTER;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ PLTFM_MEMCPY(&adapter->api_registry, registry, sizeof(*registry));
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * pre_init_system_cfg_88xx() - pre-init system config
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+pre_init_system_cfg_88xx(struct halmac_adapter *adapter)
+{
+ u32 value32;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+ u8 enable_bb;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ HALMAC_REG_W8(REG_RSV_CTRL, 0);
+
+ if (adapter->intf == HALMAC_INTERFACE_SDIO) {
+ if (leave_sdio_suspend_88xx(adapter) != HALMAC_RET_SUCCESS)
+ return HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL;
+ } else if (adapter->intf == HALMAC_INTERFACE_USB) {
+ if (HALMAC_REG_R8(REG_SYS_CFG2 + 3) == 0x20)
+ HALMAC_REG_W8(0xFE5B, HALMAC_REG_R8(0xFE5B) | BIT(4));
+ } else if (adapter->intf == HALMAC_INTERFACE_PCIE) {
+ /* For PCIE power on fail issue */
+ HALMAC_REG_W8(REG_HCI_OPT_CTRL + 1,
+ HALMAC_REG_R8(REG_HCI_OPT_CTRL + 1) | BIT(0));
+ }
+
+ /* Config PIN Mux */
+ value32 = HALMAC_REG_R32(REG_PAD_CTRL1);
+ value32 = value32 & (~(BIT(28) | BIT(29)));
+ value32 = value32 | BIT(28) | BIT(29);
+ HALMAC_REG_W32(REG_PAD_CTRL1, value32);
+
+ value32 = HALMAC_REG_R32(REG_LED_CFG);
+ value32 = value32 & (~(BIT(25) | BIT(26)));
+ HALMAC_REG_W32(REG_LED_CFG, value32);
+
+ value32 = HALMAC_REG_R32(REG_GPIO_MUXCFG);
+ value32 = value32 & (~(BIT(2)));
+ value32 = value32 | BIT(2);
+ HALMAC_REG_W32(REG_GPIO_MUXCFG, value32);
+
+ enable_bb = _FALSE;
+ set_hw_value_88xx(adapter, HALMAC_HW_EN_BB_RF, &enable_bb);
+
+ if (HALMAC_REG_R8(REG_SYS_CFG1 + 2) & BIT(4)) {
+ PLTFM_MSG_ERR("[ERR]test mode!!\n");
+ return HALMAC_RET_WLAN_MODE_FAIL;
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * init_system_cfg_88xx() - init system config
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+init_system_cfg_88xx(struct halmac_adapter *adapter)
+{
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+ u32 tmp = 0;
+ u32 value32;
+ enum halmac_ret_status status;
+ u8 hwval;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (adapter->intf == HALMAC_INTERFACE_PCIE) {
+ hwval = 1;
+ status = api->halmac_set_hw_value(adapter,
+ HALMAC_HW_PCIE_REF_AUTOK,
+ &hwval);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+ }
+
+ HALMAC_REG_W8(REG_SYS_FUNC_EN + 1, SYS_FUNC_EN);
+
+ value32 = HALMAC_REG_R32(REG_SYS_SDIO_CTRL) | BIT_LTE_MUX_CTRL_PATH;
+ HALMAC_REG_W32(REG_SYS_SDIO_CTRL, value32);
+
+ value32 = HALMAC_REG_R32(REG_CPU_DMEM_CON) | BIT_WL_PLATFORM_RST;
+#if HALMAC_8822C_SUPPORT
+ if (adapter->chip_id != HALMAC_CHIP_ID_8822B &&
+ adapter->chip_id != HALMAC_CHIP_ID_8821C)
+ value32 |= BIT_DDMA_EN;
+#endif
+ HALMAC_REG_W32(REG_CPU_DMEM_CON, value32);
+
+ /*disable boot-from-flash for driver's DL FW*/
+ tmp = HALMAC_REG_R32(REG_MCUFW_CTRL);
+ if (tmp & BIT_BOOT_FSPI_EN) {
+ HALMAC_REG_W32(REG_MCUFW_CTRL, tmp & (~BIT_BOOT_FSPI_EN));
+ value32 = HALMAC_REG_R32(REG_GPIO_MUXCFG) & (~BIT_FSPI_EN);
+ HALMAC_REG_W32(REG_GPIO_MUXCFG, value32);
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * init_edca_cfg_88xx() - init EDCA config
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+init_edca_cfg_88xx(struct halmac_adapter *adapter)
+{
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ /* Clear TX pause */
+ HALMAC_REG_W16(REG_TXPAUSE, 0x0000);
+
+ HALMAC_REG_W8(REG_SLOT, WLAN_SLOT_TIME);
+ HALMAC_REG_W8(REG_PIFS, WLAN_PIFS_TIME);
+ HALMAC_REG_W32(REG_SIFS, WLAN_SIFS_CFG);
+
+ HALMAC_REG_W16(REG_EDCA_VO_PARAM + 2, WLAN_VO_TXOP_LIMIT);
+ HALMAC_REG_W16(REG_EDCA_VI_PARAM + 2, WLAN_VI_TXOP_LIMIT);
+
+ HALMAC_REG_W32(REG_RD_NAV_NXT, WLAN_NAV_CFG);
+ HALMAC_REG_W16(REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG);
+
+ /* Set beacon cotnrol - enable TSF and other related functions */
+ HALMAC_REG_W8(REG_BCN_CTRL, (u8)(HALMAC_REG_R8(REG_BCN_CTRL) |
+ BIT_EN_BCN_FUNCTION));
+
+ /* Set send beacon related registers */
+ HALMAC_REG_W32(REG_TBTT_PROHIBIT, WLAN_TBTT_TIME);
+ HALMAC_REG_W8(REG_DRVERLYINT, WLAN_DRV_EARLY_INT);
+ HALMAC_REG_W8(REG_BCNDMATIM, WLAN_BCN_DMA_TIME);
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * init_wmac_cfg_88xx() - init wmac config
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+init_wmac_cfg_88xx(struct halmac_adapter *adapter)
+{
+ u8 value8;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ HALMAC_REG_W32(REG_RXFLTMAP0, WLAN_RX_FILTER0);
+ HALMAC_REG_W16(REG_RXFLTMAP2, WLAN_RX_FILTER2);
+
+ HALMAC_REG_W32(REG_RCR, WLAN_RCR_CFG);
+
+ HALMAC_REG_W8(REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512);
+
+ HALMAC_REG_W8(REG_TCR + 2, WLAN_TX_FUNC_CFG2);
+ HALMAC_REG_W8(REG_TCR + 1, WLAN_TX_FUNC_CFG1);
+
+#if HALMAC_8821C_SUPPORT
+ if (adapter->chip_id == HALMAC_CHIP_ID_8821C)
+ HALMAC_REG_W8(REG_ACKTO_CCK, WLAN_ACK_TO_CCK);
+#endif
+ HALMAC_REG_W32(REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2);
+
+ if (adapter->hw_cfg_info.trx_mode == HALMAC_TRNSFER_NORMAL)
+ value8 = WLAN_MAC_OPT_NORM_FUNC1;
+ else
+ value8 = WLAN_MAC_OPT_LB_FUNC1;
+
+ HALMAC_REG_W8(REG_WMAC_OPTION_FUNCTION + 4, value8);
+
+ status = api->halmac_init_low_pwr(adapter);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * init_mac_cfg_88xx() - config page1~page7 register
+ * @adapter : the adapter of halmac
+ * @mode : trx mode
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+init_mac_cfg_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode)
+{
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__, mode);
+
+ status = api->halmac_init_trx_cfg(adapter, mode);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]init trx %x\n", status);
+ return status;
+ }
+
+ status = api->halmac_init_protocol_cfg(adapter);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]init ptcl %x\n", status);
+ return status;
+ }
+
+ status = init_edca_cfg_88xx(adapter);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]init edca %x\n", status);
+ return status;
+ }
+
+ status = init_wmac_cfg_88xx(adapter);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]init wmac %x\n", status);
+ return status;
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return status;
+}
+
+/**
+ * reset_ofld_feature_88xx() -reset async api cmd status
+ * @adapter : the adapter of halmac
+ * @feature_id : feature_id
+ * Author : Ivan Lin/KaiYuan Chang
+ * Return : enum halmac_ret_status.
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+reset_ofld_feature_88xx(struct halmac_adapter *adapter,
+ enum halmac_feature_id feature_id)
+{
+ struct halmac_state *state = &adapter->halmac_state;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ switch (feature_id) {
+ case HALMAC_FEATURE_CFG_PARA:
+ state->cfg_param_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+ state->cfg_param_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;
+ break;
+ case HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE:
+ case HALMAC_FEATURE_DUMP_LOGICAL_EFUSE:
+ state->efuse_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+ state->efuse_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;
+ break;
+ case HALMAC_FEATURE_CHANNEL_SWITCH:
+ state->scan_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+ state->scan_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;
+ break;
+ case HALMAC_FEATURE_UPDATE_PACKET:
+ state->update_pkt_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+ break;
+ case HALMAC_FEATURE_IQK:
+ state->iqk_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+ break;
+ case HALMAC_FEATURE_POWER_TRACKING:
+ state->pwr_trk_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+ break;
+ case HALMAC_FEATURE_PSD:
+ state->psd_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+ break;
+ case HALMAC_FEATURE_FW_SNDING:
+ state->fw_snding_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+ state->fw_snding_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;
+ break;
+ case HALMAC_FEATURE_ALL:
+ state->cfg_param_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+ state->cfg_param_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;
+ state->efuse_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+ state->efuse_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;
+ state->scan_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+ state->scan_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;
+ state->update_pkt_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+ state->iqk_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+ state->pwr_trk_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+ state->psd_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+ state->fw_snding_state.proc_status = HALMAC_CMD_PROCESS_IDLE;
+ state->fw_snding_state.cmd_cnstr_state = HALMAC_CMD_CNSTR_IDLE;
+ break;
+ default:
+ PLTFM_MSG_ERR("[ERR]invalid feature id\n");
+ return HALMAC_RET_INVALID_FEATURE_ID;
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * (debug API)verify_platform_api_88xx() - verify platform api
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+verify_platform_api_88xx(struct halmac_adapter *adapter)
+{
+ enum halmac_ret_status ret_status = HALMAC_RET_SUCCESS;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ ret_status = verify_io_88xx(adapter);
+
+ if (ret_status != HALMAC_RET_SUCCESS)
+ return ret_status;
+
+ if (adapter->txff_alloc.la_mode != HALMAC_LA_MODE_FULL)
+ ret_status = verify_send_rsvd_page_88xx(adapter);
+
+ if (ret_status != HALMAC_RET_SUCCESS)
+ return ret_status;
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return ret_status;
+}
+
+void
+tx_desc_chksum_88xx(struct halmac_adapter *adapter, u8 enable)
+{
+ u16 value16;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ adapter->tx_desc_checksum = enable;
+
+ value16 = HALMAC_REG_R16(REG_TXDMA_OFFSET_CHK);
+ if (enable == _TRUE)
+ HALMAC_REG_W16(REG_TXDMA_OFFSET_CHK, value16 | BIT(13));
+ else
+ HALMAC_REG_W16(REG_TXDMA_OFFSET_CHK, value16 & ~BIT(13));
+}
+
+static enum halmac_ret_status
+verify_io_88xx(struct halmac_adapter *adapter)
+{
+ u8 value8;
+ u8 wvalue8;
+ u32 value32;
+ u32 value32_2;
+ u32 wvalue32;
+ u32 offset;
+ enum halmac_ret_status ret_status = HALMAC_RET_SUCCESS;
+
+ if (adapter->intf == HALMAC_INTERFACE_SDIO) {
+ offset = REG_PAGE5_DUMMY;
+ if (0 == (offset & 0xFFFF0000))
+ offset |= WLAN_IOREG_OFFSET;
+
+ ret_status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
+
+ /* Verify CMD52 R/W */
+ wvalue8 = 0xab;
+ PLTFM_SDIO_CMD52_W(offset, wvalue8);
+
+ value8 = PLTFM_SDIO_CMD52_R(offset);
+
+ if (value8 != wvalue8) {
+ PLTFM_MSG_ERR("[ERR]cmd52 r/w\n");
+ ret_status = HALMAC_RET_PLATFORM_API_INCORRECT;
+ }
+
+ /* Verify CMD53 R/W */
+ PLTFM_SDIO_CMD52_W(offset, 0xaa);
+ PLTFM_SDIO_CMD52_W(offset + 1, 0xbb);
+ PLTFM_SDIO_CMD52_W(offset + 2, 0xcc);
+ PLTFM_SDIO_CMD52_W(offset + 3, 0xdd);
+
+ value32 = PLTFM_SDIO_CMD53_R32(offset);
+
+ if (value32 != 0xddccbbaa) {
+ PLTFM_MSG_ERR("[ERR]cmd53 r\n");
+ ret_status = HALMAC_RET_PLATFORM_API_INCORRECT;
+ }
+
+ wvalue32 = 0x11223344;
+ PLTFM_SDIO_CMD53_W32(offset, wvalue32);
+
+ value32 = PLTFM_SDIO_CMD53_R32(offset);
+
+ if (value32 != wvalue32) {
+ PLTFM_MSG_ERR("[ERR]cmd53 w\n");
+ ret_status = HALMAC_RET_PLATFORM_API_INCORRECT;
+ }
+
+ /* value32 should be 0x33441122 */
+ value32 = PLTFM_SDIO_CMD53_R32(offset + 2);
+
+ wvalue32 = 0x11225566;
+ PLTFM_SDIO_CMD53_W32(offset, wvalue32);
+
+ /* value32 should be 0x55661122 */
+ value32_2 = PLTFM_SDIO_CMD53_R32(offset + 2);
+ if (value32_2 == value32) {
+ PLTFM_MSG_ERR("[ERR]cmd52 is used\n");
+ ret_status = HALMAC_RET_PLATFORM_API_INCORRECT;
+ }
+ } else {
+ wvalue32 = 0x77665511;
+ PLTFM_REG_W32(REG_PAGE5_DUMMY, wvalue32);
+
+ value32 = PLTFM_REG_R32(REG_PAGE5_DUMMY);
+ if (value32 != wvalue32) {
+ PLTFM_MSG_ERR("[ERR]reg rw\n");
+ ret_status = HALMAC_RET_PLATFORM_API_INCORRECT;
+ }
+ }
+
+ return ret_status;
+}
+
+static enum halmac_ret_status
+verify_send_rsvd_page_88xx(struct halmac_adapter *adapter)
+{
+ u8 txdesc_size = adapter->hw_cfg_info.txdesc_size;
+ u8 *rsvd_buf = NULL;
+ u8 *rsvd_page = NULL;
+ u32 i;
+ u32 pkt_size = 64, payload = 0xab;
+ enum halmac_ret_status ret_status = HALMAC_RET_SUCCESS;
+
+ rsvd_buf = (u8 *)PLTFM_MALLOC(pkt_size);
+
+ if (!rsvd_buf) {
+ PLTFM_MSG_ERR("[ERR]rsvd buf malloc!!\n");
+ return HALMAC_RET_MALLOC_FAIL;
+ }
+
+ PLTFM_MEMSET(rsvd_buf, (u8)payload, pkt_size);
+
+ ret_status = dl_rsvd_page_88xx(adapter,
+ adapter->txff_alloc.rsvd_boundary,
+ rsvd_buf, pkt_size);
+ if (ret_status != HALMAC_RET_SUCCESS) {
+ PLTFM_FREE(rsvd_buf, pkt_size);
+ return ret_status;
+ }
+
+ rsvd_page = (u8 *)PLTFM_MALLOC(pkt_size + txdesc_size);
+
+ if (!rsvd_page) {
+ PLTFM_MSG_ERR("[ERR]rsvd page malloc!!\n");
+ PLTFM_FREE(rsvd_buf, pkt_size);
+ return HALMAC_RET_MALLOC_FAIL;
+ }
+
+ PLTFM_MEMSET(rsvd_page, 0x00, pkt_size + txdesc_size);
+
+ ret_status = dump_fifo_88xx(adapter, HAL_FIFO_SEL_RSVD_PAGE, 0,
+ pkt_size + txdesc_size, rsvd_page);
+
+ if (ret_status != HALMAC_RET_SUCCESS) {
+ PLTFM_FREE(rsvd_buf, pkt_size);
+ PLTFM_FREE(rsvd_page, pkt_size + txdesc_size);
+ return ret_status;
+ }
+
+ for (i = 0; i < pkt_size; i++) {
+ if (*(rsvd_buf + i) != *(rsvd_page + (i + txdesc_size))) {
+ PLTFM_MSG_ERR("[ERR]Compare RSVD page Fail\n");
+ ret_status = HALMAC_RET_PLATFORM_API_INCORRECT;
+ }
+ }
+
+ PLTFM_FREE(rsvd_buf, pkt_size);
+ PLTFM_FREE(rsvd_page, pkt_size + txdesc_size);
+
+ return ret_status;
+}
+
+enum halmac_ret_status
+pg_num_parser_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode,
+ struct halmac_pg_num *tbl)
+{
+ u8 flag;
+ u16 hpq_num = 0, lpq_num = 0, npq_num = 0, gapq_num = 0;
+ u16 expq_num = 0, pubq_num = 0;
+ u32 i = 0;
+
+ flag = 0;
+ for (i = 0; i < HALMAC_TRX_MODE_MAX; i++) {
+ if (mode == tbl[i].mode) {
+ hpq_num = tbl[i].hq_num;
+ lpq_num = tbl[i].lq_num;
+ npq_num = tbl[i].nq_num;
+ expq_num = tbl[i].exq_num;
+ gapq_num = tbl[i].gap_num;
+ pubq_num = adapter->txff_alloc.acq_pg_num - hpq_num -
+ lpq_num - npq_num - expq_num - gapq_num;
+ flag = 1;
+ PLTFM_MSG_TRACE("[TRACE]%s done\n", __func__);
+ break;
+ }
+ }
+
+ if (flag == 0) {
+ PLTFM_MSG_ERR("[ERR]trx mode!!\n");
+ return HALMAC_RET_TRX_MODE_NOT_SUPPORT;
+ }
+
+ if (adapter->txff_alloc.acq_pg_num <
+ hpq_num + lpq_num + npq_num + expq_num + gapq_num) {
+ PLTFM_MSG_ERR("[ERR]acqnum = %d\n",
+ adapter->txff_alloc.acq_pg_num);
+ PLTFM_MSG_ERR("[ERR]hpq_num = %d\n", hpq_num);
+ PLTFM_MSG_ERR("[ERR]LPQ_num = %d\n", lpq_num);
+ PLTFM_MSG_ERR("[ERR]npq_num = %d\n", npq_num);
+ PLTFM_MSG_ERR("[ERR]EPQ_num = %d\n", expq_num);
+ PLTFM_MSG_ERR("[ERR]gapq_num = %d\n", gapq_num);
+ return HALMAC_RET_CFG_TXFIFO_PAGE_FAIL;
+ }
+
+ adapter->txff_alloc.high_queue_pg_num = hpq_num;
+ adapter->txff_alloc.low_queue_pg_num = lpq_num;
+ adapter->txff_alloc.normal_queue_pg_num = npq_num;
+ adapter->txff_alloc.extra_queue_pg_num = expq_num;
+ adapter->txff_alloc.pub_queue_pg_num = pubq_num;
+
+ return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+rqpn_parser_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode,
+ struct halmac_rqpn *tbl)
+{
+ u8 flag;
+ u32 i;
+
+ flag = 0;
+ for (i = 0; i < HALMAC_TRX_MODE_MAX; i++) {
+ if (mode == tbl[i].mode) {
+ adapter->pq_map[HALMAC_PQ_MAP_VO] = tbl[i].dma_map_vo;
+ adapter->pq_map[HALMAC_PQ_MAP_VI] = tbl[i].dma_map_vi;
+ adapter->pq_map[HALMAC_PQ_MAP_BE] = tbl[i].dma_map_be;
+ adapter->pq_map[HALMAC_PQ_MAP_BK] = tbl[i].dma_map_bk;
+ adapter->pq_map[HALMAC_PQ_MAP_MG] = tbl[i].dma_map_mg;
+ adapter->pq_map[HALMAC_PQ_MAP_HI] = tbl[i].dma_map_hi;
+ flag = 1;
+ PLTFM_MSG_TRACE("[TRACE]%s done\n", __func__);
+ break;
+ }
+ }
+
+ if (flag == 0) {
+ PLTFM_MSG_ERR("[ERR]trx mdoe!!\n");
+ return HALMAC_RET_TRX_MODE_NOT_SUPPORT;
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+#endif /* HALMAC_88XX_SUPPORT */
diff --git a/hal/halmac/halmac_88xx/halmac_init_88xx.h b/hal/halmac/halmac_88xx/halmac_init_88xx.h
new file mode 100644
index 0000000..3fa4623
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_init_88xx.h
@@ -0,0 +1,74 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_INIT_88XX_H_
+#define _HALMAC_INIT_88XX_H_
+
+#include "../halmac_api.h"
+
+#if HALMAC_88XX_SUPPORT
+
+enum halmac_ret_status
+register_api_88xx(struct halmac_adapter *adapter,
+ struct halmac_api_registry *registry);
+
+void
+init_adapter_param_88xx(struct halmac_adapter *adapter);
+
+void
+init_adapter_dynamic_param_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+mount_api_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+pre_init_system_cfg_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+init_system_cfg_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+init_edca_cfg_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+init_wmac_cfg_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+init_mac_cfg_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode);
+
+enum halmac_ret_status
+reset_ofld_feature_88xx(struct halmac_adapter *adapter,
+ enum halmac_feature_id feature_id);
+
+enum halmac_ret_status
+verify_platform_api_88xx(struct halmac_adapter *adapter);
+
+void
+tx_desc_chksum_88xx(struct halmac_adapter *adapter, u8 enable);
+
+enum halmac_ret_status
+pg_num_parser_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode,
+ struct halmac_pg_num *tbl);
+
+enum halmac_ret_status
+rqpn_parser_88xx(struct halmac_adapter *adapter, enum halmac_trx_mode mode,
+ struct halmac_rqpn *tbl);
+
+void
+init_ofld_feature_state_machine_88xx(struct halmac_adapter *adapter);
+
+#endif /* HALMAC_88XX_SUPPORT */
+
+#endif/* _HALMAC_INIT_88XX_H_ */
diff --git a/hal/halmac/halmac_88xx/halmac_mimo_88xx.c b/hal/halmac/halmac_88xx/halmac_mimo_88xx.c
new file mode 100644
index 0000000..dfd78c0
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_mimo_88xx.c
@@ -0,0 +1,878 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_mimo_88xx.h"
+#include "halmac_88xx_cfg.h"
+#include "halmac_common_88xx.h"
+#include "halmac_init_88xx.h"
+
+#if HALMAC_88XX_SUPPORT
+
+#define TXBF_CTRL_CFG (BIT_R_ENABLE_NDPA | BIT_USE_NDPA_PARAMETER | \
+ BIT_R_EN_NDPA_INT | BIT_DIS_NDP_BFEN)
+
+static void
+cfg_mu_bfee_88xx(struct halmac_adapter *adapter,
+ struct halmac_cfg_mumimo_para *param);
+
+static void
+cfg_mu_bfer_88xx(struct halmac_adapter *adapter,
+ struct halmac_cfg_mumimo_para *param);
+
+static enum halmac_cmd_construct_state
+fw_snding_cmd_cnstr_state_88xx(struct halmac_adapter *adapter);
+
+static enum halmac_ret_status
+cnv_fw_snding_state_88xx(struct halmac_adapter *adapter,
+ enum halmac_cmd_construct_state dest_state);
+
+static u8
+snding_pkt_chk_88xx(struct halmac_adapter *adapter, u8 *pkt);
+
+/**
+ * cfg_txbf_88xx() - enable/disable specific user's txbf
+ * @adapter : the adapter of halmac
+ * @userid : su bfee userid = 0 or 1 to apply TXBF
+ * @bw : the sounding bandwidth
+ * @txbf_en : 0: disable TXBF, 1: enable TXBF
+ * Author : chunchu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_txbf_88xx(struct halmac_adapter *adapter, u8 userid, enum halmac_bw bw,
+ u8 txbf_en)
+{
+ u16 tmp42c = 0;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ if (txbf_en) {
+ switch (bw) {
+ case HALMAC_BW_80:
+ tmp42c |= BIT_R_TXBF0_80M;
+ // fallthrough
+ case HALMAC_BW_40:
+ tmp42c |= BIT_R_TXBF0_40M;
+ // fallthrough
+ case HALMAC_BW_20:
+ tmp42c |= BIT_R_TXBF0_20M;
+ break;
+ default:
+ return HALMAC_RET_INVALID_SOUNDING_SETTING;
+ }
+ }
+
+ switch (userid) {
+ case 0:
+ tmp42c |= HALMAC_REG_R16(REG_TXBF_CTRL) &
+ ~(BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M);
+ HALMAC_REG_W16(REG_TXBF_CTRL, tmp42c);
+ break;
+ case 1:
+ tmp42c |= HALMAC_REG_R16(REG_TXBF_CTRL + 2) &
+ ~(BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M);
+ HALMAC_REG_W16(REG_TXBF_CTRL + 2, tmp42c);
+ break;
+ default:
+ return HALMAC_RET_INVALID_SOUNDING_SETTING;
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_mumimo_88xx() -config mumimo
+ * @adapter : the adapter of halmac
+ * @param : parameters to configure MU PPDU Tx/Rx
+ * Author : chunchu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_mumimo_88xx(struct halmac_adapter *adapter,
+ struct halmac_cfg_mumimo_para *param)
+{
+ if (param->role == HAL_BFEE)
+ cfg_mu_bfee_88xx(adapter, param);
+ else
+ cfg_mu_bfer_88xx(adapter, param);
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static void
+cfg_mu_bfee_88xx(struct halmac_adapter *adapter,
+ struct halmac_cfg_mumimo_para *param)
+{
+ u8 mu_tbl_sel;
+ u8 tmp14c0;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ tmp14c0 = HALMAC_REG_R8(REG_MU_TX_CTL) & ~BIT_MASK_R_MU_TABLE_VALID;
+ HALMAC_REG_W8(REG_MU_TX_CTL, (tmp14c0 | BIT(0) | BIT(1)) & ~(BIT(7)));
+
+ /*config GID valid table and user position table*/
+ mu_tbl_sel = HALMAC_REG_R8(REG_MU_TX_CTL + 1) & 0xF8;
+
+ HALMAC_REG_W8(REG_MU_TX_CTL + 1, mu_tbl_sel);
+ HALMAC_REG_W32(REG_MU_STA_GID_VLD, param->given_gid_tab[0]);
+ HALMAC_REG_W32(REG_MU_STA_USER_POS_INFO, param->given_user_pos[0]);
+ HALMAC_REG_W32(REG_MU_STA_USER_POS_INFO + 4, param->given_user_pos[1]);
+
+ HALMAC_REG_W8(REG_MU_TX_CTL + 1, mu_tbl_sel | 1);
+ HALMAC_REG_W32(REG_MU_STA_GID_VLD, param->given_gid_tab[1]);
+ HALMAC_REG_W32(REG_MU_STA_USER_POS_INFO, param->given_user_pos[2]);
+ HALMAC_REG_W32(REG_MU_STA_USER_POS_INFO + 4, param->given_user_pos[3]);
+}
+
+static void
+cfg_mu_bfer_88xx(struct halmac_adapter *adapter,
+ struct halmac_cfg_mumimo_para *param)
+{
+ u8 i;
+ u8 idx;
+ u8 id0;
+ u8 id1;
+ u8 gid;
+ u8 mu_tbl_sel;
+ u8 mu_tbl_valid = 0;
+ u32 gid_valid[6] = {0};
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ if (param->mu_tx_en == _FALSE) {
+ HALMAC_REG_W8(REG_MU_TX_CTL,
+ HALMAC_REG_R8(REG_MU_TX_CTL) & ~(BIT(7)));
+ return;
+ }
+
+ for (idx = 0; idx < 15; idx++) {
+ if (idx < 5) {
+ /*grouping_bitmap bit0~4, MU_STA0 with MUSTA1~5*/
+ id0 = 0;
+ id1 = (u8)(idx + 1);
+ } else if (idx < 9) {
+ /*grouping_bitmap bit5~8, MU_STA1 with MUSTA2~5*/
+ id0 = 1;
+ id1 = (u8)(idx - 3);
+ } else if (idx < 12) {
+ /*grouping_bitmap bit9~11, MU_STA2 with MUSTA3~5*/
+ id0 = 2;
+ id1 = (u8)(idx - 6);
+ } else if (idx < 14) {
+ /*grouping_bitmap bit12~13, MU_STA3 with MUSTA4~5*/
+ id0 = 3;
+ id1 = (u8)(idx - 8);
+ } else {
+ /*grouping_bitmap bit14, MU_STA4 with MUSTA5*/
+ id0 = 4;
+ id1 = (u8)(idx - 9);
+ }
+ if (param->grouping_bitmap & BIT(idx)) {
+ /*Pair 1*/
+ gid = (idx << 1) + 1;
+ gid_valid[id0] |= (BIT(gid));
+ gid_valid[id1] |= (BIT(gid));
+ /*Pair 2*/
+ gid += 1;
+ gid_valid[id0] |= (BIT(gid));
+ gid_valid[id1] |= (BIT(gid));
+ } else {
+ /*Pair 1*/
+ gid = (idx << 1) + 1;
+ gid_valid[id0] &= ~(BIT(gid));
+ gid_valid[id1] &= ~(BIT(gid));
+ /*Pair 2*/
+ gid += 1;
+ gid_valid[id0] &= ~(BIT(gid));
+ gid_valid[id1] &= ~(BIT(gid));
+ }
+ }
+
+ /*set MU STA GID valid TABLE*/
+ mu_tbl_sel = HALMAC_REG_R8(REG_MU_TX_CTL + 1) & 0xF8;
+ for (idx = 0; idx < 6; idx++) {
+ HALMAC_REG_W8(REG_MU_TX_CTL + 1, idx | mu_tbl_sel);
+ HALMAC_REG_W32(REG_MU_STA_GID_VLD, gid_valid[idx]);
+ }
+
+ /*To validate the sounding successful MU STA and enable MU TX*/
+ for (i = 0; i < 6; i++) {
+ if (param->sounding_sts[i] == _TRUE)
+ mu_tbl_valid |= BIT(i);
+ }
+ HALMAC_REG_W8(REG_MU_TX_CTL, mu_tbl_valid | BIT(7));
+}
+
+/**
+ * cfg_sounding_88xx() - configure general sounding
+ * @adapter : the adapter of halmac
+ * @role : driver's role, BFer or BFee
+ * @rate : set ndpa tx rate if driver is BFer,
+ * or set csi response rate if driver is BFee
+ * Author : chunchu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_sounding_88xx(struct halmac_adapter *adapter, enum halmac_snd_role role,
+ enum halmac_data_rate rate)
+{
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+ u32 tmp6dc = 0;
+ u8 csi_rsc = 0x1;
+
+ /*use ndpa rx rate to decide csi rate*/
+ tmp6dc = HALMAC_REG_R32(REG_BBPSF_CTRL) | BIT_WMAC_USE_NDPARATE
+ | (csi_rsc << 13);
+
+ switch (role) {
+ case HAL_BFER:
+ HALMAC_REG_W32_SET(REG_TXBF_CTRL, TXBF_CTRL_CFG);
+ HALMAC_REG_W8(REG_NDPA_RATE, rate);
+ HALMAC_REG_W8_CLR(REG_NDPA_OPT_CTRL, BIT(0) | BIT(1));
+ HALMAC_REG_W8(REG_SND_PTCL_CTRL + 1, 0x2 | BIT(7));
+ HALMAC_REG_W8(REG_SND_PTCL_CTRL + 2, 0x2);
+ break;
+ case HAL_BFEE:
+ HALMAC_REG_W8(REG_SND_PTCL_CTRL, 0xDB);
+ HALMAC_REG_W8(REG_SND_PTCL_CTRL + 3, 0x26);
+ HALMAC_REG_W8_CLR(REG_RXFLTMAP1, BIT(4));
+ HALMAC_REG_W8_CLR(REG_RXFLTMAP4, BIT(4));
+ break;
+ default:
+ return HALMAC_RET_INVALID_SOUNDING_SETTING;
+ }
+
+ /*AP mode set tx gid to 63*/
+ /*STA mode set tx gid to 0*/
+ if (BIT_GET_NETYPE0(HALMAC_REG_R32(REG_CR)) == 0x3)
+ HALMAC_REG_W32(REG_BBPSF_CTRL, tmp6dc | BIT(12));
+ else
+ HALMAC_REG_W32(REG_BBPSF_CTRL, tmp6dc & ~(BIT(12)));
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * del_sounding_88xx() - reset general sounding
+ * @adapter : the adapter of halmac
+ * @role : driver's role, BFer or BFee
+ * Author : chunchu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+del_sounding_88xx(struct halmac_adapter *adapter, enum halmac_snd_role role)
+{
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ switch (role) {
+ case HAL_BFER:
+ HALMAC_REG_W8(REG_TXBF_CTRL + 3, 0);
+ break;
+ case HAL_BFEE:
+ HALMAC_REG_W8(REG_SND_PTCL_CTRL, 0);
+ break;
+ default:
+ return HALMAC_RET_INVALID_SOUNDING_SETTING;
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * su_bfee_entry_init_88xx() - config SU beamformee's registers
+ * @adapter : the adapter of halmac
+ * @userid : SU bfee userid = 0 or 1 to be added
+ * @paid : partial AID of this bfee
+ * Author : chunchu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+su_bfee_entry_init_88xx(struct halmac_adapter *adapter, u8 userid, u16 paid)
+{
+ u16 tmp42c = 0;
+ u16 tmp168x = 0;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ switch (userid) {
+ case 0:
+ tmp42c = HALMAC_REG_R16(REG_TXBF_CTRL) &
+ ~(BIT_MASK_R_TXBF0_AID | BIT_R_TXBF0_20M |
+ BIT_R_TXBF0_40M | BIT_R_TXBF0_80M);
+ HALMAC_REG_W16(REG_TXBF_CTRL, tmp42c | paid);
+ HALMAC_REG_W16(REG_ASSOCIATED_BFMEE_SEL, paid);
+ #if HALMAC_8822C_SUPPORT
+ if (adapter->chip_id == HALMAC_CHIP_ID_8822C)
+ HALMAC_REG_W16(REG_ASSOCIATED_BFMEE_SEL, paid | BIT(9));
+ #endif
+ break;
+ case 1:
+ tmp42c = HALMAC_REG_R16(REG_TXBF_CTRL + 2) &
+ ~(BIT_MASK_R_TXBF1_AID | BIT_R_TXBF0_20M |
+ BIT_R_TXBF0_40M | BIT_R_TXBF0_80M);
+ HALMAC_REG_W16(REG_TXBF_CTRL + 2, tmp42c | paid);
+ HALMAC_REG_W16(REG_ASSOCIATED_BFMEE_SEL + 2, paid | BIT(9));
+ break;
+ case 2:
+ tmp168x = HALMAC_REG_R16(REG_WMAC_ASSOCIATED_MU_BFMEE2);
+ tmp168x = BIT_CLEAR_WMAC_MU_BFEE2_AID(tmp168x);
+ tmp168x |= (paid | BIT(9));
+ HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE2, tmp168x);
+ break;
+ case 3:
+ tmp168x = HALMAC_REG_R16(REG_WMAC_ASSOCIATED_MU_BFMEE3);
+ tmp168x = BIT_CLEAR_WMAC_MU_BFEE3_AID(tmp168x);
+ tmp168x |= (paid | BIT(9));
+ HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE3, tmp168x);
+ break;
+ case 4:
+ tmp168x = HALMAC_REG_R16(REG_WMAC_ASSOCIATED_MU_BFMEE4);
+ tmp168x = BIT_CLEAR_WMAC_MU_BFEE4_AID(tmp168x);
+ tmp168x |= (paid | BIT(9));
+ HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE4, tmp168x);
+ break;
+ case 5:
+ tmp168x = HALMAC_REG_R16(REG_WMAC_ASSOCIATED_MU_BFMEE5);
+ tmp168x = BIT_CLEAR_WMAC_MU_BFEE5_AID(tmp168x);
+ tmp168x |= (paid | BIT(9));
+ HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE5, tmp168x);
+ break;
+ default:
+ return HALMAC_RET_INVALID_SOUNDING_SETTING;
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * su_bfee_entry_init_88xx() - config SU beamformer's registers
+ * @adapter : the adapter of halmac
+ * @param : parameters to configure SU BFER entry
+ * Author : chunchu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+su_bfer_entry_init_88xx(struct halmac_adapter *adapter,
+ struct halmac_su_bfer_init_para *param)
+{
+ u16 mac_addr_h;
+ u32 mac_addr_l;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ mac_addr_l = rtk_le32_to_cpu(param->bfer_address.addr_l_h.low);
+ mac_addr_h = rtk_le16_to_cpu(param->bfer_address.addr_l_h.high);
+
+ switch (param->userid) {
+ case 0:
+ HALMAC_REG_W32(REG_ASSOCIATED_BFMER0_INFO, mac_addr_l);
+ HALMAC_REG_W16(REG_ASSOCIATED_BFMER0_INFO + 4, mac_addr_h);
+ HALMAC_REG_W16(REG_ASSOCIATED_BFMER0_INFO + 6, param->paid);
+ HALMAC_REG_W16(REG_TX_CSI_RPT_PARAM_BW20, param->csi_para);
+ break;
+ case 1:
+ HALMAC_REG_W32(REG_ASSOCIATED_BFMER1_INFO, mac_addr_l);
+ HALMAC_REG_W16(REG_ASSOCIATED_BFMER1_INFO + 4, mac_addr_h);
+ HALMAC_REG_W16(REG_ASSOCIATED_BFMER1_INFO + 6, param->paid);
+ HALMAC_REG_W16(REG_TX_CSI_RPT_PARAM_BW20 + 2, param->csi_para);
+ break;
+ default:
+ return HALMAC_RET_INVALID_SOUNDING_SETTING;
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * mu_bfee_entry_init_88xx() - config MU beamformee's registers
+ * @adapter : the adapter of halmac
+ * @param : parameters to configure MU BFEE entry
+ * Author : chunchu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+mu_bfee_entry_init_88xx(struct halmac_adapter *adapter,
+ struct halmac_mu_bfee_init_para *param)
+{
+ u16 tmp168x = 0;
+ u16 tmp14c0;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ tmp168x |= param->paid | BIT(9);
+ HALMAC_REG_W16((0x1680 + param->userid * 2), tmp168x);
+
+ tmp14c0 = HALMAC_REG_R16(REG_MU_TX_CTL) & ~(BIT(8) | BIT(9) | BIT(10));
+ HALMAC_REG_W16(REG_MU_TX_CTL, tmp14c0 | ((param->userid - 2) << 8));
+ HALMAC_REG_W32(REG_MU_STA_GID_VLD, 0);
+ HALMAC_REG_W32(REG_MU_STA_USER_POS_INFO, param->user_position_l);
+ HALMAC_REG_W32(REG_MU_STA_USER_POS_INFO + 4, param->user_position_h);
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * mu_bfer_entry_init_88xx() - config MU beamformer's registers
+ * @adapter : the adapter of halmac
+ * @param : parameters to configure MU BFER entry
+ * Author : chunchu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+mu_bfer_entry_init_88xx(struct halmac_adapter *adapter,
+ struct halmac_mu_bfer_init_para *param)
+{
+ u16 tmp1680 = 0;
+ u16 mac_addr_h;
+ u32 mac_addr_l;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ mac_addr_l = rtk_le32_to_cpu(param->bfer_address.addr_l_h.low);
+ mac_addr_h = rtk_le16_to_cpu(param->bfer_address.addr_l_h.high);
+
+ HALMAC_REG_W32(REG_ASSOCIATED_BFMER0_INFO, mac_addr_l);
+ HALMAC_REG_W16(REG_ASSOCIATED_BFMER0_INFO + 4, mac_addr_h);
+ HALMAC_REG_W16(REG_ASSOCIATED_BFMER0_INFO + 6, param->paid);
+ HALMAC_REG_W16(REG_TX_CSI_RPT_PARAM_BW20, param->csi_para);
+
+ tmp1680 = HALMAC_REG_R16(0x1680) & 0xC000;
+ tmp1680 |= param->my_aid | (param->csi_length_sel << 12);
+ HALMAC_REG_W16(0x1680, tmp1680);
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * su_bfee_entry_del_88xx() - reset SU beamformee's registers
+ * @adapter : the adapter of halmac
+ * @userid : the SU BFee userid to be deleted
+ * Author : chunchu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+su_bfee_entry_del_88xx(struct halmac_adapter *adapter, u8 userid)
+{
+ u16 value16;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ switch (userid) {
+ case 0:
+ value16 = HALMAC_REG_R16(REG_TXBF_CTRL);
+ value16 &= ~(BIT_MASK_R_TXBF0_AID | BIT_R_TXBF0_20M |
+ BIT_R_TXBF0_40M | BIT_R_TXBF0_80M);
+ HALMAC_REG_W16(REG_TXBF_CTRL, value16);
+ HALMAC_REG_W16(REG_ASSOCIATED_BFMEE_SEL, 0);
+ break;
+ case 1:
+ value16 = HALMAC_REG_R16(REG_TXBF_CTRL + 2);
+ value16 &= ~(BIT_MASK_R_TXBF1_AID | BIT_R_TXBF0_20M |
+ BIT_R_TXBF0_40M | BIT_R_TXBF0_80M);
+ HALMAC_REG_W16(REG_TXBF_CTRL + 2, value16);
+ HALMAC_REG_W16(REG_ASSOCIATED_BFMEE_SEL + 2, 0);
+ break;
+ case 2:
+ HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE2, 0);
+ break;
+ case 3:
+ HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE3, 0);
+ break;
+ case 4:
+ HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE4, 0);
+ break;
+ case 5:
+ HALMAC_REG_W16(REG_WMAC_ASSOCIATED_MU_BFMEE5, 0);
+ break;
+ default:
+ return HALMAC_RET_INVALID_SOUNDING_SETTING;
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * su_bfee_entry_del_88xx() - reset SU beamformer's registers
+ * @adapter : the adapter of halmac
+ * @userid : the SU BFer userid to be deleted
+ * Author : chunchu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+su_bfer_entry_del_88xx(struct halmac_adapter *adapter, u8 userid)
+{
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ switch (userid) {
+ case 0:
+ HALMAC_REG_W32(REG_ASSOCIATED_BFMER0_INFO, 0);
+ HALMAC_REG_W32(REG_ASSOCIATED_BFMER0_INFO + 4, 0);
+ break;
+ case 1:
+ HALMAC_REG_W32(REG_ASSOCIATED_BFMER1_INFO, 0);
+ HALMAC_REG_W32(REG_ASSOCIATED_BFMER1_INFO + 4, 0);
+ break;
+ default:
+ return HALMAC_RET_INVALID_SOUNDING_SETTING;
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * mu_bfee_entry_del_88xx() - reset MU beamformee's registers
+ * @adapter : the adapter of halmac
+ * @userid : the MU STA userid to be deleted
+ * Author : chunchu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+mu_bfee_entry_del_88xx(struct halmac_adapter *adapter, u8 userid)
+{
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ HALMAC_REG_W16(0x1680 + userid * 2, 0);
+ HALMAC_REG_W8_CLR(REG_MU_TX_CTL, BIT(userid - 2));
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * mu_bfer_entry_del_88xx() -reset MU beamformer's registers
+ * @adapter : the adapter of halmac
+ * Author : chunchu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+mu_bfer_entry_del_88xx(struct halmac_adapter *adapter)
+{
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ HALMAC_REG_W32(REG_ASSOCIATED_BFMER0_INFO, 0);
+ HALMAC_REG_W32(REG_ASSOCIATED_BFMER0_INFO + 4, 0);
+ HALMAC_REG_W16(0x1680, 0);
+ HALMAC_REG_W8(REG_MU_TX_CTL, 0);
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_csi_rate_88xx() - config CSI frame Tx rate
+ * @adapter : the adapter of halmac
+ * @rssi : rssi in decimal value
+ * @cur_rate : current CSI frame rate
+ * @fixrate_en : enable to fix CSI frame in VHT rate, otherwise legacy OFDM rate
+ * @new_rate : API returns the final CSI frame rate
+ * Author : chunchu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_csi_rate_88xx(struct halmac_adapter *adapter, u8 rssi, u8 cur_rate,
+ u8 fixrate_en, u8 *new_rate)
+{
+ u32 csi_cfg;
+ u16 cur_rrsr;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+#if HALMAC_8821C_SUPPORT
+ if (adapter->chip_id == HALMAC_CHIP_ID_8821C && fixrate_en) {
+ csi_cfg = HALMAC_REG_R32(REG_BBPSF_CTRL) & ~BITS_WMAC_CSI_RATE;
+ HALMAC_REG_W32(REG_BBPSF_CTRL,
+ csi_cfg | BIT_CSI_FORCE_RATE_EN |
+ BIT_CSI_RSC(1) |
+ BIT_WMAC_CSI_RATE(HALMAC_VHT_NSS1_MCS3));
+ *new_rate = HALMAC_VHT_NSS1_MCS3;
+ return HALMAC_RET_SUCCESS;
+ }
+ csi_cfg = HALMAC_REG_R32(REG_BBPSF_CTRL) & ~BITS_WMAC_CSI_RATE &
+ ~BIT_CSI_FORCE_RATE_EN;
+#else
+ csi_cfg = HALMAC_REG_R32(REG_BBPSF_CTRL) & ~BITS_WMAC_CSI_RATE;
+#endif
+
+ cur_rrsr = HALMAC_REG_R16(REG_RRSR);
+
+ if (rssi >= 40) {
+ if (cur_rate != HALMAC_OFDM54) {
+ cur_rrsr |= BIT(HALMAC_OFDM54);
+ csi_cfg |= BIT_WMAC_CSI_RATE(HALMAC_OFDM54);
+ HALMAC_REG_W16(REG_RRSR, cur_rrsr);
+ HALMAC_REG_W32(REG_BBPSF_CTRL, csi_cfg);
+ }
+ *new_rate = HALMAC_OFDM54;
+ } else {
+ if (cur_rate != HALMAC_OFDM24) {
+ cur_rrsr &= ~(BIT(HALMAC_OFDM54));
+ csi_cfg |= BIT_WMAC_CSI_RATE(HALMAC_OFDM24);
+ HALMAC_REG_W16(REG_RRSR, cur_rrsr);
+ HALMAC_REG_W32(REG_BBPSF_CTRL, csi_cfg);
+ }
+ *new_rate = HALMAC_OFDM24;
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * fw_snding_88xx() - fw sounding control
+ * @adapter : the adapter of halmac
+ * @su_info :
+ * su0_en : enable/disable fw sounding
+ * su0_ndpa_pkt : ndpa pkt, shall include txdesc
+ * su0_pkt_sz : ndpa pkt size, shall include txdesc
+ * @mu_info : currently not in use, input NULL is acceptable
+ * @period : sounding period, unit is 5ms
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+fw_snding_88xx(struct halmac_adapter *adapter,
+ struct halmac_su_snding_info *su_info,
+ struct halmac_mu_snding_info *mu_info, u8 period)
+{
+ u8 h2c_buf[H2C_PKT_SIZE_88XX] = { 0 };
+ u16 seq_num;
+ u16 snding_info_addr;
+ struct halmac_h2c_header_info hdr_info;
+ enum halmac_cmd_process_status *proc_status;
+ enum halmac_ret_status status;
+
+ proc_status = &adapter->halmac_state.fw_snding_state.proc_status;
+
+ if (adapter->chip_id == HALMAC_CHIP_ID_8821C)
+ return HALMAC_RET_NOT_SUPPORT;
+
+ if (halmac_fw_validate(adapter) != HALMAC_RET_SUCCESS)
+ return HALMAC_RET_NO_DLFW;
+
+ if (adapter->fw_ver.h2c_version < 9)
+ return HALMAC_RET_FW_NO_SUPPORT;
+
+ if (*proc_status == HALMAC_CMD_PROCESS_SENDING) {
+ PLTFM_MSG_TRACE("[TRACE]Wait event(snd)\n");
+ return HALMAC_RET_BUSY_STATE;
+ }
+
+ if (su_info->su0_en == 1) {
+ if (!su_info->su0_ndpa_pkt)
+ return HALMAC_RET_NULL_POINTER;
+
+ if (su_info->su0_pkt_sz > (u32)SU0_SNDING_PKT_RSVDPG_SIZE -
+ adapter->hw_cfg_info.txdesc_size)
+ return HALMAC_RET_DATA_SIZE_INCORRECT;
+
+ if (!snding_pkt_chk_88xx(adapter, su_info->su0_ndpa_pkt))
+ return HALMAC_RET_TXDESC_SET_FAIL;
+
+ if (fw_snding_cmd_cnstr_state_88xx(adapter) !=
+ HALMAC_CMD_CNSTR_IDLE) {
+ PLTFM_MSG_ERR("[ERR]Not idle(snd)\n");
+ return HALMAC_RET_ERROR_STATE;
+ }
+
+ snding_info_addr = adapter->txff_alloc.rsvd_h2c_sta_info_addr +
+ SU0_SNDING_PKT_OFFSET;
+ status = dl_rsvd_page_88xx(adapter, snding_info_addr,
+ su_info->su0_ndpa_pkt,
+ su_info->su0_pkt_sz);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]dl rsvd page\n");
+ return status;
+ }
+
+ FW_SNDING_SET_SU0(h2c_buf, 1);
+ FW_SNDING_SET_PERIOD(h2c_buf, period);
+ FW_SNDING_SET_NDPA0_HEAD_PG(h2c_buf, snding_info_addr -
+ adapter->txff_alloc.rsvd_boundary);
+ } else {
+ if (fw_snding_cmd_cnstr_state_88xx(adapter) !=
+ HALMAC_CMD_CNSTR_BUSY) {
+ PLTFM_MSG_ERR("[ERR]Not snd(snd)\n");
+ return HALMAC_RET_ERROR_STATE;
+ }
+ FW_SNDING_SET_SU0(h2c_buf, 0);
+ }
+
+ *proc_status = HALMAC_CMD_PROCESS_SENDING;
+
+ hdr_info.sub_cmd_id = SUB_CMD_ID_FW_SNDING;
+ hdr_info.content_size = 8;
+ hdr_info.ack = _TRUE;
+ set_h2c_pkt_hdr_88xx(adapter, h2c_buf, &hdr_info, &seq_num);
+ adapter->halmac_state.fw_snding_state.seq_num = seq_num;
+
+ status = send_h2c_pkt_88xx(adapter, h2c_buf);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]send h2c\n");
+ reset_ofld_feature_88xx(adapter, HALMAC_FEATURE_FW_SNDING);
+ return status;
+ }
+
+ if (cnv_fw_snding_state_88xx(adapter, su_info->su0_en == 1 ?
+ HALMAC_CMD_CNSTR_BUSY :
+ HALMAC_CMD_CNSTR_IDLE)
+ != HALMAC_RET_SUCCESS)
+ return HALMAC_RET_ERROR_STATE;
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static u8
+snding_pkt_chk_88xx(struct halmac_adapter *adapter, u8 *pkt)
+{
+ u8 data_rate;
+
+ if (GET_TX_DESC_NDPA(pkt) == 0) {
+ PLTFM_MSG_ERR("[ERR]txdesc ndpa = 0\n");
+ return _FALSE;
+ }
+
+ data_rate = (u8)GET_TX_DESC_DATARATE(pkt);
+ if (!(data_rate >= HALMAC_VHT_NSS2_MCS0 &&
+ data_rate <= HALMAC_VHT_NSS2_MCS9)) {
+ if (!(data_rate >= HALMAC_MCS8 && data_rate <= HALMAC_MCS15)) {
+ PLTFM_MSG_ERR("[ERR]txdesc rate\n");
+ return _FALSE;
+ }
+ }
+
+ if (GET_TX_DESC_NAVUSEHDR(pkt) == 0) {
+ PLTFM_MSG_ERR("[ERR]txdesc navusehdr = 0\n");
+ return _FALSE;
+ }
+
+ if (GET_TX_DESC_USE_RATE(pkt) == 0) {
+ PLTFM_MSG_ERR("[ERR]txdesc userate = 0\n");
+ return _FALSE;
+ }
+
+ return _TRUE;
+}
+
+static enum halmac_cmd_construct_state
+fw_snding_cmd_cnstr_state_88xx(struct halmac_adapter *adapter)
+{
+ return adapter->halmac_state.fw_snding_state.cmd_cnstr_state;
+}
+
+enum halmac_ret_status
+get_h2c_ack_fw_snding_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+ u8 seq_num = 0;
+ u8 fw_rc;
+ struct halmac_fw_snding_state *state;
+ enum halmac_cmd_process_status proc_status;
+
+ state = &adapter->halmac_state.fw_snding_state;
+
+ seq_num = (u8)H2C_ACK_HDR_GET_H2C_SEQ(buf);
+ PLTFM_MSG_TRACE("[TRACE]Seq num:h2c->%d c2h->%d\n",
+ state->seq_num, seq_num);
+ if (seq_num != state->seq_num) {
+ PLTFM_MSG_ERR("[ERR]Seq num mismatch:h2c->%d c2h->%d\n",
+ state->seq_num, seq_num);
+ return HALMAC_RET_SUCCESS;
+ }
+
+ if (state->proc_status != HALMAC_CMD_PROCESS_SENDING) {
+ PLTFM_MSG_ERR("[ERR]not sending(snd)\n");
+ return HALMAC_RET_SUCCESS;
+ }
+
+ fw_rc = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(buf);
+ state->fw_rc = fw_rc;
+
+ if ((enum halmac_h2c_return_code)fw_rc == HALMAC_H2C_RETURN_SUCCESS) {
+ proc_status = HALMAC_CMD_PROCESS_DONE;
+ state->proc_status = proc_status;
+ PLTFM_EVENT_SIG(HALMAC_FEATURE_FW_SNDING, proc_status,
+ NULL, 0);
+ } else {
+ proc_status = HALMAC_CMD_PROCESS_ERROR;
+ state->proc_status = proc_status;
+ PLTFM_EVENT_SIG(HALMAC_FEATURE_FW_SNDING, proc_status,
+ &fw_rc, 1);
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+get_fw_snding_status_88xx(struct halmac_adapter *adapter,
+ enum halmac_cmd_process_status *proc_status)
+{
+ *proc_status = adapter->halmac_state.fw_snding_state.proc_status;
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static enum halmac_ret_status
+cnv_fw_snding_state_88xx(struct halmac_adapter *adapter,
+ enum halmac_cmd_construct_state dest_state)
+{
+ struct halmac_fw_snding_state *state;
+
+ state = &adapter->halmac_state.fw_snding_state;
+
+ if (state->cmd_cnstr_state != HALMAC_CMD_CNSTR_IDLE &&
+ state->cmd_cnstr_state != HALMAC_CMD_CNSTR_BUSY)
+ return HALMAC_RET_ERROR_STATE;
+
+ if (dest_state == HALMAC_CMD_CNSTR_IDLE) {
+ if (state->cmd_cnstr_state == HALMAC_CMD_CNSTR_IDLE)
+ return HALMAC_RET_ERROR_STATE;
+ } else if (dest_state == HALMAC_CMD_CNSTR_BUSY) {
+ if (state->cmd_cnstr_state == HALMAC_CMD_CNSTR_BUSY)
+ return HALMAC_RET_ERROR_STATE;
+ }
+
+ state->cmd_cnstr_state = dest_state;
+
+ return HALMAC_RET_SUCCESS;
+}
+#endif /* HALMAC_88XX_SUPPORT */
diff --git a/hal/halmac/halmac_88xx/halmac_mimo_88xx.h b/hal/halmac/halmac_88xx/halmac_mimo_88xx.h
new file mode 100644
index 0000000..95d0372
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_mimo_88xx.h
@@ -0,0 +1,83 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_MIMO_88XX_H_
+#define _HALMAC_MIMO_88XX_H_
+
+#include "../halmac_api.h"
+
+#if HALMAC_88XX_SUPPORT
+
+enum halmac_ret_status
+cfg_txbf_88xx(struct halmac_adapter *adapter, u8 userid, enum halmac_bw bw,
+ u8 txbf_en);
+
+enum halmac_ret_status
+cfg_mumimo_88xx(struct halmac_adapter *adapter,
+ struct halmac_cfg_mumimo_para *param);
+
+enum halmac_ret_status
+cfg_sounding_88xx(struct halmac_adapter *adapter, enum halmac_snd_role role,
+ enum halmac_data_rate rate);
+
+enum halmac_ret_status
+del_sounding_88xx(struct halmac_adapter *adapter, enum halmac_snd_role role);
+
+enum halmac_ret_status
+su_bfee_entry_init_88xx(struct halmac_adapter *adapter, u8 userid, u16 paid);
+
+enum halmac_ret_status
+su_bfer_entry_init_88xx(struct halmac_adapter *adapter,
+ struct halmac_su_bfer_init_para *param);
+
+enum halmac_ret_status
+mu_bfee_entry_init_88xx(struct halmac_adapter *adapter,
+ struct halmac_mu_bfee_init_para *param);
+
+enum halmac_ret_status
+mu_bfer_entry_init_88xx(struct halmac_adapter *adapter,
+ struct halmac_mu_bfer_init_para *param);
+
+enum halmac_ret_status
+su_bfee_entry_del_88xx(struct halmac_adapter *adapter, u8 userid);
+
+enum halmac_ret_status
+su_bfer_entry_del_88xx(struct halmac_adapter *adapter, u8 userid);
+
+enum halmac_ret_status
+mu_bfee_entry_del_88xx(struct halmac_adapter *adapter, u8 userid);
+
+enum halmac_ret_status
+mu_bfer_entry_del_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+cfg_csi_rate_88xx(struct halmac_adapter *adapter, u8 rssi, u8 cur_rate,
+ u8 fixrate_en, u8 *new_rate);
+
+enum halmac_ret_status
+fw_snding_88xx(struct halmac_adapter *adapter,
+ struct halmac_su_snding_info *su_info,
+ struct halmac_mu_snding_info *mu_info, u8 period);
+
+enum halmac_ret_status
+get_h2c_ack_fw_snding_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+enum halmac_ret_status
+get_fw_snding_status_88xx(struct halmac_adapter *adapter,
+ enum halmac_cmd_process_status *proc_status);
+
+#endif /* HALMAC_88XX_SUPPORT */
+
+#endif/* _HALMAC_MIMO_88XX_H_ */
diff --git a/hal/halmac/halmac_88xx/halmac_pcie_88xx.c b/hal/halmac/halmac_88xx/halmac_pcie_88xx.c
new file mode 100644
index 0000000..4842325
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_pcie_88xx.c
@@ -0,0 +1,543 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_pcie_88xx.h"
+
+#if HALMAC_88XX_SUPPORT
+
+/**
+ * init_pcie_cfg_88xx() - init PCIe
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+init_pcie_cfg_88xx(struct halmac_adapter *adapter)
+{
+ if (adapter->intf != HALMAC_INTERFACE_PCIE)
+ return HALMAC_RET_WRONG_INTF;
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * deinit_pcie_cfg_88xx() - deinit PCIE
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+deinit_pcie_cfg_88xx(struct halmac_adapter *adapter)
+{
+ if (adapter->intf != HALMAC_INTERFACE_PCIE)
+ return HALMAC_RET_WRONG_INTF;
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_pcie_rx_agg_88xx() - config rx aggregation
+ * @adapter : the adapter of halmac
+ * @halmac_rx_agg_mode
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_pcie_rx_agg_88xx(struct halmac_adapter *adapter,
+ struct halmac_rxagg_cfg *cfg)
+{
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * reg_r8_pcie_88xx() - read 1byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+u8
+reg_r8_pcie_88xx(struct halmac_adapter *adapter, u32 offset)
+{
+ return PLTFM_REG_R8(offset);
+}
+
+/**
+ * reg_w8_pcie_88xx() - write 1byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * @value : register value
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+reg_w8_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u8 value)
+{
+ PLTFM_REG_W8(offset, value);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * reg_r16_pcie_88xx() - read 2byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+u16
+reg_r16_pcie_88xx(struct halmac_adapter *adapter, u32 offset)
+{
+ return PLTFM_REG_R16(offset);
+}
+
+/**
+ * reg_w16_pcie_88xx() - write 2byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * @value : register value
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+reg_w16_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u16 value)
+{
+ PLTFM_REG_W16(offset, value);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * reg_r32_pcie_88xx() - read 4byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+u32
+reg_r32_pcie_88xx(struct halmac_adapter *adapter, u32 offset)
+{
+ return PLTFM_REG_R32(offset);
+}
+
+/**
+ * reg_w32_pcie_88xx() - write 4byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * @value : register value
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+reg_w32_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u32 value)
+{
+ PLTFM_REG_W32(offset, value);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_txagg_pcie_align_88xx() -config sdio bus tx agg alignment
+ * @adapter : the adapter of halmac
+ * @enable : function enable(1)/disable(0)
+ * @align_size : sdio bus tx agg alignment size (2^n, n = 3~11)
+ * Author : Soar Tu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_txagg_pcie_align_88xx(struct halmac_adapter *adapter, u8 enable,
+ u16 align_size)
+{
+ return HALMAC_RET_NOT_SUPPORT;
+}
+
+/**
+ * tx_allowed_pcie_88xx() - check tx status
+ * @adapter : the adapter of halmac
+ * @buf : tx packet, include txdesc
+ * @size : tx packet size, include txdesc
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+tx_allowed_pcie_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+ return HALMAC_RET_NOT_SUPPORT;
+}
+
+/**
+ * pcie_indirect_reg_r32_88xx() - read MAC reg by SDIO reg
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+u32
+pcie_indirect_reg_r32_88xx(struct halmac_adapter *adapter, u32 offset)
+{
+ return 0xFFFFFFFF;
+}
+
+/**
+ * pcie_reg_rn_88xx() - read n byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * @size : register value size
+ * @value : register value
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+pcie_reg_rn_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
+ u8 *value)
+{
+ return HALMAC_RET_NOT_SUPPORT;
+}
+
+/**
+ * set_pcie_bulkout_num_88xx() - inform bulk-out num
+ * @adapter : the adapter of halmac
+ * @num : usb bulk-out number
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+set_pcie_bulkout_num_88xx(struct halmac_adapter *adapter, u8 num)
+{
+ return HALMAC_RET_NOT_SUPPORT;
+}
+
+/**
+ * get_pcie_tx_addr_88xx() - get CMD53 addr for the TX packet
+ * @adapter : the adapter of halmac
+ * @buf : tx packet, include txdesc
+ * @size : tx packet size
+ * @cmd53_addr : cmd53 addr value
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+get_pcie_tx_addr_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
+ u32 *cmd53_addr)
+{
+ return HALMAC_RET_NOT_SUPPORT;
+}
+
+/**
+ * get_pcie_bulkout_id_88xx() - get bulk out id for the TX packet
+ * @adapter : the adapter of halmac
+ * @buf : tx packet, include txdesc
+ * @size : tx packet size
+ * @id : usb bulk-out id
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+get_pcie_bulkout_id_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
+ u8 *id)
+{
+ return HALMAC_RET_NOT_SUPPORT;
+}
+
+enum halmac_ret_status
+mdio_write_88xx(struct halmac_adapter *adapter, u8 addr, u16 data, u8 speed)
+{
+ u8 tmp_u1b = 0;
+ u32 cnt = 0;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+ u8 real_addr = 0;
+
+ HALMAC_REG_W16(REG_MDIO_V1, data);
+
+ real_addr = (addr & 0x1F);
+ HALMAC_REG_W8(REG_PCIE_MIX_CFG, real_addr);
+
+ if (speed == HAL_INTF_PHY_PCIE_GEN1) {
+ if (addr < 0x20)
+ HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x00);
+ else
+ HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x01);
+ } else if (speed == HAL_INTF_PHY_PCIE_GEN2) {
+ if (addr < 0x20)
+ HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x02);
+ else
+ HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x03);
+ } else {
+ PLTFM_MSG_ERR("[ERR]Error Speed !\n");
+ }
+
+ HALMAC_REG_W8_SET(REG_PCIE_MIX_CFG, BIT_MDIO_WFLAG_V1);
+
+ tmp_u1b = HALMAC_REG_R8(REG_PCIE_MIX_CFG) & BIT_MDIO_WFLAG_V1;
+ cnt = 20;
+
+ while (tmp_u1b && (cnt != 0)) {
+ PLTFM_DELAY_US(10);
+ tmp_u1b = HALMAC_REG_R8(REG_PCIE_MIX_CFG) & BIT_MDIO_WFLAG_V1;
+ cnt--;
+ }
+
+ if (tmp_u1b) {
+ PLTFM_MSG_ERR("[ERR]MDIO write fail!\n");
+ return HALMAC_RET_FAIL;
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+u16
+mdio_read_88xx(struct halmac_adapter *adapter, u8 addr, u8 speed)
+{
+ u16 ret = 0;
+ u8 tmp_u1b = 0;
+ u32 cnt = 0;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+ u8 real_addr = 0;
+
+ real_addr = (addr & 0x1F);
+ HALMAC_REG_W8(REG_PCIE_MIX_CFG, real_addr);
+
+ if (speed == HAL_INTF_PHY_PCIE_GEN1) {
+ if (addr < 0x20)
+ HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x00);
+ else
+ HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x01);
+ } else if (speed == HAL_INTF_PHY_PCIE_GEN2) {
+ if (addr < 0x20)
+ HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x02);
+ else
+ HALMAC_REG_W8(REG_PCIE_MIX_CFG + 3, 0x03);
+ } else {
+ PLTFM_MSG_ERR("[ERR]Error Speed !\n");
+ }
+
+ HALMAC_REG_W8_SET(REG_PCIE_MIX_CFG, BIT_MDIO_RFLAG_V1);
+
+ tmp_u1b = HALMAC_REG_R8(REG_PCIE_MIX_CFG) & BIT_MDIO_RFLAG_V1;
+ cnt = 20;
+ while (tmp_u1b && (cnt != 0)) {
+ PLTFM_DELAY_US(10);
+ tmp_u1b = HALMAC_REG_R8(REG_PCIE_MIX_CFG) & BIT_MDIO_RFLAG_V1;
+ cnt--;
+ }
+
+ if (tmp_u1b) {
+ ret = 0xFFFF;
+ PLTFM_MSG_ERR("[ERR]MDIO read fail!\n");
+ } else {
+ ret = HALMAC_REG_R16(REG_MDIO_V1 + 2);
+ PLTFM_MSG_TRACE("[TRACE]Value-R = %x\n", ret);
+ }
+
+ return ret;
+}
+
+enum halmac_ret_status
+dbi_w32_88xx(struct halmac_adapter *adapter, u16 addr, u32 data)
+{
+ u8 tmp_u1b = 0;
+ u32 cnt = 0;
+ u16 write_addr = 0;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ HALMAC_REG_W32(REG_DBI_WDATA_V1, data);
+
+ write_addr = ((addr & 0x0ffc) | (0x000F << 12));
+ HALMAC_REG_W16(REG_DBI_FLAG_V1, write_addr);
+
+ PLTFM_MSG_TRACE("[TRACE]Addr-W = %x\n", write_addr);
+
+ HALMAC_REG_W8(REG_DBI_FLAG_V1 + 2, 0x01);
+ tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
+
+ cnt = 20;
+ while (tmp_u1b && (cnt != 0)) {
+ PLTFM_DELAY_US(10);
+ tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
+ cnt--;
+ }
+
+ if (tmp_u1b) {
+ PLTFM_MSG_ERR("[ERR]DBI write fail!\n");
+ return HALMAC_RET_FAIL;
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+u32
+dbi_r32_88xx(struct halmac_adapter *adapter, u16 addr)
+{
+ u16 read_addr = addr & 0x0ffc;
+ u8 tmp_u1b = 0;
+ u32 cnt = 0;
+ u32 ret = 0;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ HALMAC_REG_W16(REG_DBI_FLAG_V1, read_addr);
+
+ HALMAC_REG_W8(REG_DBI_FLAG_V1 + 2, 0x2);
+ tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
+
+ cnt = 20;
+ while (tmp_u1b && (cnt != 0)) {
+ PLTFM_DELAY_US(10);
+ tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
+ cnt--;
+ }
+
+ if (tmp_u1b) {
+ ret = 0xFFFF;
+ PLTFM_MSG_ERR("[ERR]DBI read fail!\n");
+ } else {
+ ret = HALMAC_REG_R32(REG_DBI_RDATA_V1);
+ PLTFM_MSG_TRACE("[TRACE]Value-R = %x\n", ret);
+ }
+
+ return ret;
+}
+
+enum halmac_ret_status
+dbi_w8_88xx(struct halmac_adapter *adapter, u16 addr, u8 data)
+{
+ u8 tmp_u1b = 0;
+ u32 cnt = 0;
+ u16 write_addr = 0;
+ u16 remainder = addr & (4 - 1);
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ HALMAC_REG_W8(REG_DBI_WDATA_V1 + remainder, data);
+
+ write_addr = ((addr & 0x0ffc) | (BIT(0) << (remainder + 12)));
+
+ HALMAC_REG_W16(REG_DBI_FLAG_V1, write_addr);
+
+ PLTFM_MSG_TRACE("[TRACE]Addr-W = %x\n", write_addr);
+
+ HALMAC_REG_W8(REG_DBI_FLAG_V1 + 2, 0x01);
+
+ tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
+
+ cnt = 20;
+ while (tmp_u1b && (cnt != 0)) {
+ PLTFM_DELAY_US(10);
+ tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
+ cnt--;
+ }
+
+ if (tmp_u1b) {
+ PLTFM_MSG_ERR("[ERR]DBI write fail!\n");
+ return HALMAC_RET_FAIL;
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+u8
+dbi_r8_88xx(struct halmac_adapter *adapter, u16 addr)
+{
+ u16 read_addr = addr & 0x0ffc;
+ u8 tmp_u1b = 0;
+ u32 cnt = 0;
+ u8 ret = 0;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ HALMAC_REG_W16(REG_DBI_FLAG_V1, read_addr);
+ HALMAC_REG_W8(REG_DBI_FLAG_V1 + 2, 0x2);
+
+ tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
+
+ cnt = 20;
+ while (tmp_u1b && (cnt != 0)) {
+ PLTFM_DELAY_US(10);
+ tmp_u1b = HALMAC_REG_R8(REG_DBI_FLAG_V1 + 2);
+ cnt--;
+ }
+
+ if (tmp_u1b) {
+ ret = 0xFF;
+ PLTFM_MSG_ERR("[ERR]DBI read fail!\n");
+ } else {
+ ret = HALMAC_REG_R8(REG_DBI_RDATA_V1 + (addr & (4 - 1)));
+ PLTFM_MSG_TRACE("[TRACE]Value-R = %x\n", ret);
+ }
+
+ return ret;
+}
+
+enum halmac_ret_status
+trxdma_check_idle_88xx(struct halmac_adapter *adapter)
+{
+ u32 cnt = 0;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ /* Stop Tx & Rx DMA */
+ HALMAC_REG_W32_SET(REG_RXPKT_NUM, BIT(18));
+ HALMAC_REG_W16_SET(REG_PCIE_CTRL, ~(BIT(15) | BIT(8)));
+
+ /* Stop FW */
+ HALMAC_REG_W16_CLR(REG_SYS_FUNC_EN, BIT(10));
+
+ /* Check Tx DMA is idle */
+ cnt = 20;
+ while ((HALMAC_REG_R8(REG_SYS_CFG5) & BIT(2)) == BIT(2)) {
+ PLTFM_DELAY_US(10);
+ cnt--;
+ if (cnt == 0) {
+ PLTFM_MSG_ERR("[ERR]Chk tx idle\n");
+ return HALMAC_RET_POWER_OFF_FAIL;
+ }
+ }
+
+ /* Check Rx DMA is idle */
+ cnt = 20;
+ while ((HALMAC_REG_R32(REG_RXPKT_NUM) & BIT(17)) != BIT(17)) {
+ PLTFM_DELAY_US(10);
+ cnt--;
+ if (cnt == 0) {
+ PLTFM_MSG_ERR("[ERR]Chk rx idle\n");
+ return HALMAC_RET_POWER_OFF_FAIL;
+ }
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+void
+en_ref_autok_88xx(struct halmac_adapter *adapter, u8 en)
+{
+ if (en == 1)
+ adapter->pcie_refautok_en = 1;
+ else
+ adapter->pcie_refautok_en = 0;
+}
+
+#endif /* HALMAC_88XX_SUPPORT */
diff --git a/hal/halmac/halmac_88xx/halmac_pcie_88xx.h b/hal/halmac/halmac_88xx/halmac_pcie_88xx.h
new file mode 100644
index 0000000..c3956b9
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_pcie_88xx.h
@@ -0,0 +1,102 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_PCIE_88XX_H_
+#define _HALMAC_PCIE_88XX_H_
+
+#include "../halmac_api.h"
+
+#if HALMAC_88XX_SUPPORT
+
+enum halmac_ret_status
+init_pcie_cfg_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+deinit_pcie_cfg_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+cfg_pcie_rx_agg_88xx(struct halmac_adapter *adapter,
+ struct halmac_rxagg_cfg *cfg);
+
+u8
+reg_r8_pcie_88xx(struct halmac_adapter *adapter, u32 offset);
+
+enum halmac_ret_status
+reg_w8_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u8 value);
+
+u16
+reg_r16_pcie_88xx(struct halmac_adapter *adapter, u32 offset);
+
+enum halmac_ret_status
+reg_w16_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u16 value);
+
+u32
+reg_r32_pcie_88xx(struct halmac_adapter *adapter, u32 offset);
+
+enum halmac_ret_status
+reg_w32_pcie_88xx(struct halmac_adapter *adapter, u32 offset, u32 value);
+
+enum halmac_ret_status
+cfg_txagg_pcie_align_88xx(struct halmac_adapter *adapter, u8 enable,
+ u16 align_size);
+
+enum halmac_ret_status
+tx_allowed_pcie_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+u32
+pcie_indirect_reg_r32_88xx(struct halmac_adapter *adapter, u32 offset);
+
+enum halmac_ret_status
+pcie_reg_rn_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
+ u8 *value);
+
+enum halmac_ret_status
+set_pcie_bulkout_num_88xx(struct halmac_adapter *adapter, u8 num);
+
+enum halmac_ret_status
+get_pcie_tx_addr_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
+ u32 *cmd53_addr);
+
+enum halmac_ret_status
+get_pcie_bulkout_id_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
+ u8 *id);
+
+enum halmac_ret_status
+mdio_write_88xx(struct halmac_adapter *adapter, u8 addr, u16 data, u8 speed);
+
+u16
+mdio_read_88xx(struct halmac_adapter *adapter, u8 addr, u8 speed);
+
+enum halmac_ret_status
+dbi_w32_88xx(struct halmac_adapter *adapter, u16 addr, u32 data);
+
+u32
+dbi_r32_88xx(struct halmac_adapter *adapter, u16 addr);
+
+enum halmac_ret_status
+dbi_w8_88xx(struct halmac_adapter *adapter, u16 addr, u8 data);
+
+u8
+dbi_r8_88xx(struct halmac_adapter *adapter, u16 addr);
+
+enum halmac_ret_status
+trxdma_check_idle_88xx(struct halmac_adapter *adapter);
+
+void
+en_ref_autok_88xx(struct halmac_adapter *dapter, u8 en);
+
+#endif /* HALMAC_88XX_SUPPORT */
+
+#endif/* _HALMAC_PCIE_88XX_H_ */
diff --git a/hal/halmac/halmac_88xx/halmac_sdio_88xx.c b/hal/halmac/halmac_88xx/halmac_sdio_88xx.c
new file mode 100644
index 0000000..ef9fb89
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_sdio_88xx.c
@@ -0,0 +1,892 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_sdio_88xx.h"
+#include "halmac_88xx_cfg.h"
+
+#if HALMAC_88XX_SUPPORT
+
+/* define the SDIO Bus CLK threshold */
+/* for avoiding CMD53 fails that result from SDIO CLK sync to ana_clk fail */
+#define SDIO_CLK_HIGH_SPEED_TH 50 /* 50MHz */
+#define SDIO_CLK_SPEED_MAX 208 /* 208MHz */
+
+/*only for r_indir_sdio_88xx !!, Soar 20171222*/
+static u8
+r_indir_cmd52_88xx(struct halmac_adapter *adapter, u32 offset);
+
+/*only for r_indir_sdio_88xx !!, Soar 20171222*/
+static u32
+r_indir_cmd53_88xx(struct halmac_adapter *adapter, u32 offset);
+
+/*only for r_indir_sdio_88xx !!, Soar 20171222*/
+static u32
+r8_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr);
+
+/*only for r_indir_sdio_88xx !!, Soar 20171222*/
+static u32
+r16_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr);
+
+/*only for r_indir_sdio_88xx !!, Soar 20171222*/
+static u32
+r32_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr);
+
+/*only for w_indir_sdio_88xx !!, Soar 20171222*/
+static enum halmac_ret_status
+w_indir_cmd52_88xx(struct halmac_adapter *adapter, u32 adr, u32 val,
+ enum halmac_io_size size);
+
+/*only for w_indir_sdio_88xx !!, Soar 20171222*/
+static enum halmac_ret_status
+w_indir_cmd53_88xx(struct halmac_adapter *adapter, u32 adr, u32 val,
+ enum halmac_io_size size);
+
+/*only for w_indir_sdio_88xx !!, Soar 20171222*/
+static enum halmac_ret_status
+w8_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val);
+
+/*only for w_indir_sdio_88xx !!, Soar 20171222*/
+static enum halmac_ret_status
+w16_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val);
+
+/*only for w_indir_sdio_88xx !!, Soar 20171222*/
+static enum halmac_ret_status
+w32_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val);
+
+/**
+ * init_sdio_cfg_88xx() - init SDIO
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+init_sdio_cfg_88xx(struct halmac_adapter *adapter)
+{
+ u32 value32;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ if (adapter->intf != HALMAC_INTERFACE_SDIO)
+ return HALMAC_RET_WRONG_INTF;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ HALMAC_REG_R32(REG_SDIO_FREE_TXPG);
+
+ value32 = HALMAC_REG_R32(REG_SDIO_TX_CTRL) & 0xFFFF;
+ value32 &= ~(BIT_CMD_ERR_STOP_INT_EN | BIT_EN_MASK_TIMER |
+ BIT_EN_RXDMA_MASK_INT);
+ HALMAC_REG_W32(REG_SDIO_TX_CTRL, value32);
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * deinit_sdio_cfg_88xx() - deinit SDIO
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+deinit_sdio_cfg_88xx(struct halmac_adapter *adapter)
+{
+ if (adapter->intf != HALMAC_INTERFACE_SDIO)
+ return HALMAC_RET_WRONG_INTF;
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_sdio_rx_agg_88xx() - config rx aggregation
+ * @adapter : the adapter of halmac
+ * @halmac_rx_agg_mode
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_sdio_rx_agg_88xx(struct halmac_adapter *adapter,
+ struct halmac_rxagg_cfg *cfg)
+{
+ u8 value8;
+ u8 size;
+ u8 timeout;
+ u8 agg_enable;
+ u32 value32;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ agg_enable = HALMAC_REG_R8(REG_TXDMA_PQ_MAP);
+
+ switch (cfg->mode) {
+ case HALMAC_RX_AGG_MODE_NONE:
+ agg_enable &= ~(BIT_RXDMA_AGG_EN);
+ break;
+ case HALMAC_RX_AGG_MODE_DMA:
+ case HALMAC_RX_AGG_MODE_USB:
+ agg_enable |= BIT_RXDMA_AGG_EN;
+ break;
+ default:
+ PLTFM_MSG_ERR("[ERR]unsupported mode\n");
+ agg_enable &= ~BIT_RXDMA_AGG_EN;
+ break;
+ }
+
+ if (cfg->threshold.drv_define == _FALSE) {
+ size = 0xFF;
+ timeout = 0x01;
+ } else {
+ size = cfg->threshold.size;
+ timeout = cfg->threshold.timeout;
+ }
+
+ value32 = HALMAC_REG_R32(REG_RXDMA_AGG_PG_TH);
+ if (cfg->threshold.size_limit_en == _FALSE)
+ HALMAC_REG_W32(REG_RXDMA_AGG_PG_TH, value32 & ~BIT_EN_PRE_CALC);
+ else
+ HALMAC_REG_W32(REG_RXDMA_AGG_PG_TH, value32 | BIT_EN_PRE_CALC);
+
+ HALMAC_REG_W8(REG_TXDMA_PQ_MAP, agg_enable);
+ HALMAC_REG_W16(REG_RXDMA_AGG_PG_TH,
+ (u16)(size | (timeout << BIT_SHIFT_DMA_AGG_TO_V1)));
+
+ value8 = HALMAC_REG_R8(REG_RXDMA_MODE);
+ if (0 != (agg_enable & BIT_RXDMA_AGG_EN))
+ HALMAC_REG_W8(REG_RXDMA_MODE, value8 | BIT_DMA_MODE);
+ else
+ HALMAC_REG_W8(REG_RXDMA_MODE, value8 & ~(BIT_DMA_MODE));
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * sdio_reg_rn_88xx() - read n byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * @halmac_size : register value size
+ * @value : register value
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+sdio_reg_rn_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
+ u8 *value)
+{
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ if (0 == (offset & 0xFFFF0000)) {
+ PLTFM_MSG_ERR("[ERR]offset 0x%x\n", offset);
+ return HALMAC_RET_FAIL;
+ }
+
+ status = cnv_to_sdio_bus_offset_88xx(adapter, &offset);
+ if (status != HALMAC_RET_SUCCESS) {
+ PLTFM_MSG_ERR("[ERR]convert offset\n");
+ return status;
+ }
+
+ if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) {
+ PLTFM_MSG_ERR("[ERR]power off\n");
+ return HALMAC_RET_FAIL;
+ }
+
+ PLTFM_SDIO_CMD53_RN(offset, size, value);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_txagg_sdio_align_88xx() -config sdio bus tx agg alignment
+ * @adapter : the adapter of halmac
+ * @enable : function enable(1)/disable(0)
+ * @align_size : sdio bus tx agg alignment size (2^n, n = 3~11)
+ * Author : Soar Tu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_txagg_sdio_align_88xx(struct halmac_adapter *adapter, u8 enable,
+ u16 align_size)
+{
+ u8 i;
+ u8 flag = 0;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (adapter->chip_id == HALMAC_CHIP_ID_8822B)
+ return HALMAC_RET_NOT_SUPPORT;
+
+ if ((align_size & 0xF000) != 0) {
+ PLTFM_MSG_ERR("[ERR]out of range\n");
+ return HALMAC_RET_FAIL;
+ }
+
+ for (i = 3; i <= 11; i++) {
+ if (align_size == 1 << i) {
+ flag = 1;
+ break;
+ }
+ }
+
+ if (flag == 0) {
+ PLTFM_MSG_ERR("[ERR]not 2^3 ~ 2^11\n");
+ return HALMAC_RET_FAIL;
+ }
+
+ adapter->hw_cfg_info.tx_align_size = align_size;
+
+ if (enable)
+ HALMAC_REG_W16(REG_RQPN_CTRL_2, 0x8000 | align_size);
+ else
+ HALMAC_REG_W16(REG_RQPN_CTRL_2, align_size);
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * sdio_indirect_reg_r32_88xx() - read MAC reg by SDIO reg
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+u32
+sdio_indirect_reg_r32_88xx(struct halmac_adapter *adapter, u32 offset)
+{
+ return r_indir_sdio_88xx(adapter, offset, HALMAC_IO_DWORD);
+}
+
+/**
+ * set_sdio_bulkout_num_88xx() - inform bulk-out num
+ * @adapter : the adapter of halmac
+ * @bulkout_num : usb bulk-out number
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+set_sdio_bulkout_num_88xx(struct halmac_adapter *adapter, u8 num)
+{
+ return HALMAC_RET_NOT_SUPPORT;
+}
+
+/**
+ * get_sdio_bulkout_id_88xx() - get bulk out id for the TX packet
+ * @adapter : the adapter of halmac
+ * @halmac_buf : tx packet, include txdesc
+ * @halmac_size : tx packet size
+ * @bulkout_id : usb bulk-out id
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+get_sdio_bulkout_id_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
+ u8 *id)
+{
+ return HALMAC_RET_NOT_SUPPORT;
+}
+
+/**
+ * sdio_cmd53_4byte_88xx() - cmd53 only for 4byte len register IO
+ * @adapter : the adapter of halmac
+ * @enable : 1->CMD53 only use in 4byte reg, 0 : No limitation
+ * Author : Ivan Lin/KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+sdio_cmd53_4byte_88xx(struct halmac_adapter *adapter,
+ enum halmac_sdio_cmd53_4byte_mode mode)
+{
+ if (adapter->intf != HALMAC_INTERFACE_SDIO)
+ return HALMAC_RET_WRONG_INTF;
+
+ if (adapter->api_registry.sdio_cmd53_4byte_en == 0)
+ return HALMAC_RET_NOT_SUPPORT;
+
+ adapter->sdio_cmd53_4byte = mode;
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * sdio_hw_info_88xx() - info sdio hw info
+ * @adapter : the adapter of halmac
+ * @HALMAC_SDIO_CMD53_4BYTE_MODE :
+ * clock_speed : sdio bus clock. Unit -> MHz
+ * spec_ver : sdio spec version
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+sdio_hw_info_88xx(struct halmac_adapter *adapter,
+ struct halmac_sdio_hw_info *info)
+{
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (adapter->intf != HALMAC_INTERFACE_SDIO)
+ return HALMAC_RET_WRONG_INTF;
+
+ PLTFM_MSG_TRACE("[TRACE]SDIO clock:%d, spec:%d\n",
+ info->clock_speed, info->spec_ver);
+
+ if (info->clock_speed > SDIO_CLK_SPEED_MAX)
+ return HALMAC_RET_SDIO_CLOCK_ERR;
+
+ if (info->clock_speed > SDIO_CLK_HIGH_SPEED_TH)
+ adapter->sdio_hw_info.io_hi_speed_flag = 1;
+
+ adapter->sdio_hw_info.io_indir_flag = info->io_indir_flag;
+ if (info->clock_speed > SDIO_CLK_HIGH_SPEED_TH &&
+ adapter->sdio_hw_info.io_indir_flag == 0)
+ PLTFM_MSG_WARN("[WARN]SDIO clock:%d, indir access is better\n",
+ info->clock_speed);
+
+ adapter->sdio_hw_info.clock_speed = info->clock_speed;
+ adapter->sdio_hw_info.spec_ver = info->spec_ver;
+ adapter->sdio_hw_info.block_size = info->block_size;
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+void
+cfg_sdio_tx_page_threshold_88xx(struct halmac_adapter *adapter,
+ struct halmac_tx_page_threshold_info *info)
+{
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+ u32 threshold = info->threshold;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (info->enable == 1) {
+ threshold = BIT(31) | threshold;
+ PLTFM_MSG_TRACE("[TRACE]enable\n");
+ } else {
+ threshold = ~(BIT(31)) & threshold;
+ PLTFM_MSG_TRACE("[TRACE]disable\n");
+ }
+
+ switch (info->dma_queue_sel) {
+ case HALMAC_MAP2_HQ:
+ HALMAC_REG_W32(REG_TQPNT1, threshold);
+ break;
+ case HALMAC_MAP2_NQ:
+ HALMAC_REG_W32(REG_TQPNT2, threshold);
+ break;
+ case HALMAC_MAP2_LQ:
+ HALMAC_REG_W32(REG_TQPNT3, threshold);
+ break;
+ case HALMAC_MAP2_EXQ:
+ HALMAC_REG_W32(REG_TQPNT4, threshold);
+ break;
+ default:
+ break;
+ }
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+}
+
+enum halmac_ret_status
+cnv_to_sdio_bus_offset_88xx(struct halmac_adapter *adapter, u32 *offset)
+{
+ switch ((*offset) & 0xFFFF0000) {
+ case WLAN_IOREG_OFFSET:
+ *offset &= HALMAC_WLAN_MAC_REG_MSK;
+ *offset |= HALMAC_SDIO_CMD_ADDR_MAC_REG << 13;
+ break;
+ case SDIO_LOCAL_OFFSET:
+ *offset &= HALMAC_SDIO_LOCAL_MSK;
+ *offset |= HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13;
+ break;
+ default:
+ *offset = 0xFFFFFFFF;
+ PLTFM_MSG_ERR("[ERR]base address!!\n");
+ return HALMAC_RET_CONVERT_SDIO_OFFSET_FAIL;
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+leave_sdio_suspend_88xx(struct halmac_adapter *adapter)
+{
+ u8 value8;
+ u32 cnt;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ value8 = HALMAC_REG_R8(REG_SDIO_HSUS_CTRL);
+ HALMAC_REG_W8(REG_SDIO_HSUS_CTRL, value8 & ~(BIT(0)));
+
+ cnt = 10000;
+ while (!(HALMAC_REG_R8(REG_SDIO_HSUS_CTRL) & 0x02)) {
+ cnt--;
+ if (cnt == 0)
+ return HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL;
+ }
+
+ value8 = HALMAC_REG_R8(REG_HCI_OPT_CTRL + 2);
+ if (adapter->sdio_hw_info.spec_ver == HALMAC_SDIO_SPEC_VER_3_00)
+ HALMAC_REG_W8(REG_HCI_OPT_CTRL + 2, value8 | BIT(2));
+ else
+ HALMAC_REG_W8(REG_HCI_OPT_CTRL + 2, value8 & ~(BIT(2)));
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/*only for r_indir_sdio_88xx !!, Soar 20171222*/
+static u8
+r_indir_cmd52_88xx(struct halmac_adapter *adapter, u32 offset)
+{
+ u8 value8, tmp, cnt = 50;
+ u32 reg_cfg = REG_SDIO_INDIRECT_REG_CFG;
+ u32 reg_data = REG_SDIO_INDIRECT_REG_DATA;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ status = cnv_to_sdio_bus_offset_88xx(adapter, ®_cfg);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+ status = cnv_to_sdio_bus_offset_88xx(adapter, ®_data);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+
+ PLTFM_SDIO_CMD52_W(reg_cfg, (u8)offset);
+ PLTFM_SDIO_CMD52_W(reg_cfg + 1, (u8)(offset >> 8));
+ PLTFM_SDIO_CMD52_W(reg_cfg + 2, (u8)(BIT(3) | BIT(4)));
+
+ do {
+ tmp = PLTFM_SDIO_CMD52_R(reg_cfg + 2);
+ cnt--;
+ } while (((tmp & BIT(4)) == 0) && (cnt > 0));
+
+ if (((cnt & BIT(4)) == 0) && cnt == 0)
+ PLTFM_MSG_ERR("[ERR]sdio indirect CMD52 read\n");
+
+ value8 = PLTFM_SDIO_CMD52_R(reg_data);
+
+ return value8;
+}
+
+/*only for r_indir_sdio_88xx !!, Soar 20171222*/
+static u32
+r_indir_cmd53_88xx(struct halmac_adapter *adapter, u32 offset)
+{
+ u8 tmp, cnt = 50;
+ u32 reg_cfg = REG_SDIO_INDIRECT_REG_CFG;
+ u32 reg_data = REG_SDIO_INDIRECT_REG_DATA;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ union {
+ u32 dword;
+ u8 byte[4];
+ } value32 = { 0x00000000 };
+
+ status = cnv_to_sdio_bus_offset_88xx(adapter, ®_cfg);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+ status = cnv_to_sdio_bus_offset_88xx(adapter, ®_data);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+
+ PLTFM_SDIO_CMD53_W32(reg_cfg, offset | BIT(19) | BIT(20));
+
+ do {
+ tmp = PLTFM_SDIO_CMD52_R(reg_cfg + 2);
+ cnt--;
+ } while (((tmp & BIT(4)) == 0) && (cnt > 0));
+
+ if (((cnt & BIT(4)) == 0) && cnt == 0)
+ PLTFM_MSG_ERR("[ERR]sdio indirect CMD53 read\n");
+
+ value32.dword = PLTFM_SDIO_CMD53_R32(reg_data);
+
+ return value32.dword;
+}
+
+/*only for r_indir_sdio_88xx !!, Soar 20171222*/
+static u32
+r8_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr)
+{
+ union {
+ u32 dword;
+ u8 byte[4];
+ } val = { 0x00000000 };
+
+ if (adapter->pwr_off_flow_flag == 1 ||
+ adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) {
+ val.byte[0] = r_indir_cmd52_88xx(adapter, adr);
+ val.dword = rtk_le32_to_cpu(val.dword);
+ } else {
+ val.dword = r_indir_cmd53_88xx(adapter, adr);
+ }
+
+ return val.dword;
+}
+
+/*only for r_indir_sdio_88xx !!, Soar 20171222*/
+static u32
+r16_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr)
+{
+ u32 reg_data = REG_SDIO_INDIRECT_REG_DATA;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ union {
+ u32 dword;
+ u8 byte[4];
+ } val = { 0x00000000 };
+
+ status = cnv_to_sdio_bus_offset_88xx(adapter, ®_data);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+
+ if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) {
+ if (0 != (adr & (2 - 1))) {
+ val.byte[0] = r_indir_cmd52_88xx(adapter, adr);
+ val.byte[1] = r_indir_cmd52_88xx(adapter, adr + 1);
+ } else {
+ val.byte[0] = r_indir_cmd52_88xx(adapter, adr);
+ val.byte[1] = PLTFM_SDIO_CMD52_R(reg_data + 1);
+ }
+ val.dword = rtk_le32_to_cpu(val.dword);
+ } else {
+ if (0 != (adr & (2 - 1))) {
+ val.byte[0] = (u8)r_indir_cmd53_88xx(adapter, adr);
+ val.byte[1] = (u8)r_indir_cmd53_88xx(adapter, adr + 1);
+ val.dword = rtk_le32_to_cpu(val.dword);
+ } else {
+ val.dword = r_indir_cmd53_88xx(adapter, adr);
+ }
+ }
+ return val.dword;
+}
+
+/*only for r_indir_sdio_88xx !!, Soar 20171222*/
+static u32
+r32_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr)
+{
+ u32 reg_data = REG_SDIO_INDIRECT_REG_DATA;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ union {
+ u32 dword;
+ u8 byte[4];
+ } val = { 0x00000000 };
+
+ status = cnv_to_sdio_bus_offset_88xx(adapter, ®_data);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+
+ if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) {
+ if (0 != (adr & (4 - 1))) {
+ val.byte[0] = r_indir_cmd52_88xx(adapter, adr);
+ val.byte[1] = r_indir_cmd52_88xx(adapter, adr + 1);
+ val.byte[2] = r_indir_cmd52_88xx(adapter, adr + 2);
+ val.byte[3] = r_indir_cmd52_88xx(adapter, adr + 3);
+ } else {
+ val.byte[0] = r_indir_cmd52_88xx(adapter, adr);
+ val.byte[1] = PLTFM_SDIO_CMD52_R(reg_data + 1);
+ val.byte[2] = PLTFM_SDIO_CMD52_R(reg_data + 2);
+ val.byte[3] = PLTFM_SDIO_CMD52_R(reg_data + 3);
+ }
+ val.dword = rtk_le32_to_cpu(val.dword);
+ } else {
+ if (0 != (adr & (4 - 1))) {
+ val.byte[0] = (u8)r_indir_cmd53_88xx(adapter, adr);
+ val.byte[1] = (u8)r_indir_cmd53_88xx(adapter, adr + 1);
+ val.byte[2] = (u8)r_indir_cmd53_88xx(adapter, adr + 2);
+ val.byte[3] = (u8)r_indir_cmd53_88xx(adapter, adr + 3);
+ val.dword = rtk_le32_to_cpu(val.dword);
+ } else {
+ val.dword = r_indir_cmd53_88xx(adapter, adr);
+ }
+ }
+ return val.dword;
+}
+
+u32
+r_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr,
+ enum halmac_io_size size)
+{
+ u32 reg_data = REG_SDIO_INDIRECT_REG_DATA;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ union {
+ u32 dword;
+ u8 byte[4];
+ } val = { 0x00000000 };
+
+ status = cnv_to_sdio_bus_offset_88xx(adapter, ®_data);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+
+ PLTFM_MUTEX_LOCK(&adapter->sdio_indir_mutex);
+
+ switch (size) {
+ case HALMAC_IO_BYTE:
+ val.dword = r8_indir_sdio_88xx(adapter, adr);
+ break;
+ case HALMAC_IO_WORD:
+ val.dword = r16_indir_sdio_88xx(adapter, adr);
+ break;
+ case HALMAC_IO_DWORD:
+ val.dword = r32_indir_sdio_88xx(adapter, adr);
+ break;
+ default:
+ break;
+ }
+
+ PLTFM_MUTEX_UNLOCK(&adapter->sdio_indir_mutex);
+
+ return val.dword;
+}
+
+/*only for w_indir_sdio_88xx !!, Soar 20171222*/
+static enum halmac_ret_status
+w_indir_cmd52_88xx(struct halmac_adapter *adapter, u32 adr, u32 val,
+ enum halmac_io_size size)
+{
+ u8 tmp, cnt = 50;
+ u32 reg_cfg = REG_SDIO_INDIRECT_REG_CFG;
+ u32 reg_data = REG_SDIO_INDIRECT_REG_DATA;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ status = cnv_to_sdio_bus_offset_88xx(adapter, ®_cfg);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+ status = cnv_to_sdio_bus_offset_88xx(adapter, ®_data);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+
+ PLTFM_SDIO_CMD52_W(reg_cfg, (u8)adr);
+ PLTFM_SDIO_CMD52_W(reg_cfg + 1, (u8)(adr >> 8));
+ switch (size) {
+ case HALMAC_IO_BYTE:
+ PLTFM_SDIO_CMD52_W(reg_data, (u8)val);
+ PLTFM_SDIO_CMD52_W(reg_cfg + 2, (u8)(BIT(2) | BIT(4)));
+ break;
+ case HALMAC_IO_WORD:
+ PLTFM_SDIO_CMD52_W(reg_data, (u8)val);
+ PLTFM_SDIO_CMD52_W(reg_data + 1, (u8)(val >> 8));
+ PLTFM_SDIO_CMD52_W(reg_cfg + 2,
+ (u8)(BIT(0) | BIT(2) | BIT(4)));
+ break;
+ case HALMAC_IO_DWORD:
+ PLTFM_SDIO_CMD52_W(reg_data, (u8)val);
+ PLTFM_SDIO_CMD52_W(reg_data + 1, (u8)(val >> 8));
+ PLTFM_SDIO_CMD52_W(reg_data + 2, (u8)(val >> 16));
+ PLTFM_SDIO_CMD52_W(reg_data + 3, (u8)(val >> 24));
+ PLTFM_SDIO_CMD52_W(reg_cfg + 2,
+ (u8)(BIT(1) | BIT(2) | BIT(4)));
+ break;
+ default:
+ break;
+ }
+
+ do {
+ tmp = PLTFM_SDIO_CMD52_R(reg_cfg + 2);
+ cnt--;
+ } while (((tmp & BIT(4)) == 0) && (cnt > 0));
+
+ if (((cnt & BIT(4)) == 0) && cnt == 0)
+ PLTFM_MSG_ERR("[ERR]sdio indirect CMD52 write\n");
+
+ return status;
+}
+
+/*only for w_indir_sdio_88xx !!, Soar 20171222*/
+static enum halmac_ret_status
+w_indir_cmd53_88xx(struct halmac_adapter *adapter, u32 adr, u32 val,
+ enum halmac_io_size size)
+{
+ u8 tmp, cnt = 50;
+ u32 reg_cfg = REG_SDIO_INDIRECT_REG_CFG;
+ u32 reg_data = REG_SDIO_INDIRECT_REG_DATA;
+ u32 value32 = 0;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ status = cnv_to_sdio_bus_offset_88xx(adapter, ®_cfg);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+ status = cnv_to_sdio_bus_offset_88xx(adapter, ®_data);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+
+ switch (size) {
+ case HALMAC_IO_BYTE:
+ value32 = adr | BIT(18) | BIT(20);
+ break;
+ case HALMAC_IO_WORD:
+ value32 = adr | BIT(16) | BIT(18) | BIT(20);
+ break;
+ case HALMAC_IO_DWORD:
+ value32 = adr | BIT(17) | BIT(18) | BIT(20);
+ break;
+ default:
+ return HALMAC_RET_FAIL;
+ }
+
+ PLTFM_SDIO_CMD53_W32(reg_data, val);
+ PLTFM_SDIO_CMD53_W32(reg_cfg, value32);
+
+ do {
+ tmp = PLTFM_SDIO_CMD52_R(reg_cfg + 2);
+ cnt--;
+ } while (((tmp & BIT(4)) == 0) && (cnt > 0));
+
+ if (((cnt & BIT(4)) == 0) && cnt == 0)
+ PLTFM_MSG_ERR("[ERR]sdio indirect CMD53 read\n");
+
+ return status;
+}
+
+/*only for w_indir_sdio_88xx !!, Soar 20171222*/
+static enum halmac_ret_status
+w8_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val)
+{
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ if (adapter->pwr_off_flow_flag == 1 ||
+ adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF)
+ status = w_indir_cmd52_88xx(adapter, adr, val, HALMAC_IO_BYTE);
+ else
+ status = w_indir_cmd53_88xx(adapter, adr, val, HALMAC_IO_BYTE);
+ return status;
+}
+
+/*only for w_indir_sdio_88xx !!, Soar 20171222*/
+static enum halmac_ret_status
+w16_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val)
+{
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) {
+ if (0 != (adr & (2 - 1))) {
+ status = w_indir_cmd52_88xx(adapter, adr, val,
+ HALMAC_IO_BYTE);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+ status = w_indir_cmd52_88xx(adapter, adr + 1, val >> 8,
+ HALMAC_IO_BYTE);
+ } else {
+ status = w_indir_cmd52_88xx(adapter, adr, val,
+ HALMAC_IO_WORD);
+ }
+ } else {
+ if (0 != (adr & (2 - 1))) {
+ status = w_indir_cmd53_88xx(adapter, adr, val,
+ HALMAC_IO_BYTE);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+ status = w_indir_cmd53_88xx(adapter, adr + 1, val >> 8,
+ HALMAC_IO_BYTE);
+ } else {
+ status = w_indir_cmd53_88xx(adapter, adr, val,
+ HALMAC_IO_WORD);
+ }
+ }
+ return status;
+}
+
+/*only for w_indir_sdio_88xx !!, Soar 20171222*/
+static enum halmac_ret_status
+w32_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val)
+{
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ if (adapter->halmac_state.mac_pwr == HALMAC_MAC_POWER_OFF) {
+ if (0 != (adr & (4 - 1))) {
+ status = w_indir_cmd52_88xx(adapter, adr, val,
+ HALMAC_IO_BYTE);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+ status = w_indir_cmd52_88xx(adapter, adr + 1, val >> 8,
+ HALMAC_IO_BYTE);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+ status = w_indir_cmd52_88xx(adapter, adr + 2, val >> 16,
+ HALMAC_IO_BYTE);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+ status = w_indir_cmd52_88xx(adapter, adr + 3, val >> 24,
+ HALMAC_IO_BYTE);
+ } else {
+ status = w_indir_cmd52_88xx(adapter, adr, val,
+ HALMAC_IO_DWORD);
+ }
+ } else {
+ if (0 != (adr & (4 - 1))) {
+ status = w_indir_cmd53_88xx(adapter, adr, val,
+ HALMAC_IO_BYTE);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+ status = w_indir_cmd53_88xx(adapter, adr + 1, val >> 8,
+ HALMAC_IO_BYTE);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+ status = w_indir_cmd53_88xx(adapter, adr + 2, val >> 16,
+ HALMAC_IO_BYTE);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+ status = w_indir_cmd53_88xx(adapter, adr + 3, val >> 24,
+ HALMAC_IO_BYTE);
+ } else {
+ status = w_indir_cmd53_88xx(adapter, adr, val,
+ HALMAC_IO_DWORD);
+ }
+ }
+ return status;
+}
+
+enum halmac_ret_status
+w_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val,
+ enum halmac_io_size size)
+{
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ PLTFM_MUTEX_LOCK(&adapter->sdio_indir_mutex);
+
+ switch (size) {
+ case HALMAC_IO_BYTE:
+ status = w8_indir_sdio_88xx(adapter, adr, val);
+ break;
+ case HALMAC_IO_WORD:
+ status = w16_indir_sdio_88xx(adapter, adr, val);
+ break;
+ case HALMAC_IO_DWORD:
+ status = w32_indir_sdio_88xx(adapter, adr, val);
+ break;
+ default:
+ break;
+ }
+
+ PLTFM_MUTEX_UNLOCK(&adapter->sdio_indir_mutex);
+
+ return status;
+}
+
+#endif /* HALMAC_88XX_SUPPORT */
diff --git a/hal/halmac/halmac_88xx/halmac_sdio_88xx.h b/hal/halmac/halmac_88xx/halmac_sdio_88xx.h
new file mode 100644
index 0000000..0d89156
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_sdio_88xx.h
@@ -0,0 +1,79 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_SDIO_88XX_H_
+#define _HALMAC_SDIO_88XX_H_
+
+#include "../halmac_api.h"
+
+#if HALMAC_88XX_SUPPORT
+
+enum halmac_ret_status
+init_sdio_cfg_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+deinit_sdio_cfg_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+cfg_sdio_rx_agg_88xx(struct halmac_adapter *adapter,
+ struct halmac_rxagg_cfg *cfg);
+
+enum halmac_ret_status
+cfg_txagg_sdio_align_88xx(struct halmac_adapter *adapter, u8 enable,
+ u16 align_size);
+
+u32
+sdio_indirect_reg_r32_88xx(struct halmac_adapter *adapter, u32 offset);
+
+enum halmac_ret_status
+sdio_reg_rn_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
+ u8 *value);
+
+enum halmac_ret_status
+set_sdio_bulkout_num_88xx(struct halmac_adapter *adapter, u8 num);
+
+enum halmac_ret_status
+get_sdio_bulkout_id_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
+ u8 *id);
+
+enum halmac_ret_status
+sdio_cmd53_4byte_88xx(struct halmac_adapter *adapter,
+ enum halmac_sdio_cmd53_4byte_mode mode);
+
+enum halmac_ret_status
+sdio_hw_info_88xx(struct halmac_adapter *adapter,
+ struct halmac_sdio_hw_info *info);
+
+void
+cfg_sdio_tx_page_threshold_88xx(struct halmac_adapter *adapter,
+ struct halmac_tx_page_threshold_info *info);
+
+enum halmac_ret_status
+cnv_to_sdio_bus_offset_88xx(struct halmac_adapter *adapter, u32 *offset);
+
+enum halmac_ret_status
+leave_sdio_suspend_88xx(struct halmac_adapter *adapter);
+
+u32
+r_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr,
+ enum halmac_io_size size);
+
+enum halmac_ret_status
+w_indir_sdio_88xx(struct halmac_adapter *adapter, u32 adr, u32 val,
+ enum halmac_io_size size);
+
+#endif /* HALMAC_88XX_SUPPORT */
+
+#endif/* _HALMAC_SDIO_88XX_H_ */
diff --git a/hal/halmac/halmac_88xx/halmac_usb_88xx.c b/hal/halmac/halmac_88xx/halmac_usb_88xx.c
new file mode 100644
index 0000000..ca3003f
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_usb_88xx.c
@@ -0,0 +1,533 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#include "halmac_usb_88xx.h"
+
+#if HALMAC_88XX_SUPPORT
+
+enum usb_burst_size {
+ USB_BURST_SIZE_3_0 = 0x0,
+ USB_BURST_SIZE_2_0_HS = 0x1,
+ USB_BURST_SIZE_2_0_FS = 0x2,
+ USB_BURST_SIZE_2_0_OTHERS = 0x3,
+ USB_BURST_SIZE_UNDEFINE = 0x7F,
+};
+
+/**
+ * init_usb_cfg_88xx() - init USB
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+init_usb_cfg_88xx(struct halmac_adapter *adapter)
+{
+ u8 value8 = 0;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ value8 |= (BIT_DMA_MODE | (0x3 << BIT_SHIFT_BURST_CNT));
+
+ if (HALMAC_REG_R8(REG_SYS_CFG2 + 3) == 0x20) {
+ /* usb3.0 */
+ value8 |= (USB_BURST_SIZE_3_0 << BIT_SHIFT_BURST_SIZE);
+ } else {
+ if ((HALMAC_REG_R8(REG_USB_USBSTAT) & 0x3) == 0x1)/* usb2.0 */
+ value8 |= USB_BURST_SIZE_2_0_HS << BIT_SHIFT_BURST_SIZE;
+ else /* usb1.1 */
+ value8 |= USB_BURST_SIZE_2_0_FS << BIT_SHIFT_BURST_SIZE;
+ }
+
+ HALMAC_REG_W8(REG_RXDMA_MODE, value8);
+ HALMAC_REG_W16(REG_TXDMA_OFFSET_CHK,
+ HALMAC_REG_R16(REG_TXDMA_OFFSET_CHK) | BIT_DROP_DATA_EN);
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * deinit_usb_cfg_88xx() - deinit USB
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+deinit_usb_cfg_88xx(struct halmac_adapter *adapter)
+{
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_usb_rx_agg_88xx() - config rx aggregation
+ * @adapter : the adapter of halmac
+ * @halmac_rx_agg_mode
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_usb_rx_agg_88xx(struct halmac_adapter *adapter,
+ struct halmac_rxagg_cfg *cfg)
+{
+ u8 dma_usb_agg;
+ u8 size;
+ u8 timeout;
+ u8 agg_enable;
+ u32 value32;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ dma_usb_agg = HALMAC_REG_R8(REG_RXDMA_AGG_PG_TH + 3);
+ agg_enable = HALMAC_REG_R8(REG_TXDMA_PQ_MAP);
+
+ switch (cfg->mode) {
+ case HALMAC_RX_AGG_MODE_NONE:
+ agg_enable &= ~BIT_RXDMA_AGG_EN;
+ break;
+ case HALMAC_RX_AGG_MODE_DMA:
+ agg_enable |= BIT_RXDMA_AGG_EN;
+ dma_usb_agg |= BIT(7);
+ break;
+
+ case HALMAC_RX_AGG_MODE_USB:
+ agg_enable |= BIT_RXDMA_AGG_EN;
+ dma_usb_agg &= ~BIT(7);
+ break;
+ default:
+ PLTFM_MSG_ERR("[ERR]unsupported mode\n");
+ agg_enable &= ~BIT_RXDMA_AGG_EN;
+ break;
+ }
+
+ if (cfg->threshold.drv_define == _FALSE) {
+ if (HALMAC_REG_R8(REG_SYS_CFG2 + 3) == 0x20) {
+ /* usb3.0 */
+ size = 0x5;
+ timeout = 0xA;
+ } else {
+ /* usb2.0 */
+ size = 0x5;
+ timeout = 0x20;
+ }
+ } else {
+ size = cfg->threshold.size;
+ timeout = cfg->threshold.timeout;
+ }
+
+ value32 = HALMAC_REG_R32(REG_RXDMA_AGG_PG_TH);
+ if (cfg->threshold.size_limit_en == _FALSE)
+ HALMAC_REG_W32(REG_RXDMA_AGG_PG_TH, value32 & ~BIT_EN_PRE_CALC);
+ else
+ HALMAC_REG_W32(REG_RXDMA_AGG_PG_TH, value32 | BIT_EN_PRE_CALC);
+
+ HALMAC_REG_W8(REG_TXDMA_PQ_MAP, agg_enable);
+ HALMAC_REG_W8(REG_RXDMA_AGG_PG_TH + 3, dma_usb_agg);
+ HALMAC_REG_W16(REG_RXDMA_AGG_PG_TH,
+ (u16)(size | (timeout << BIT_SHIFT_DMA_AGG_TO_V1)));
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * reg_r8_usb_88xx() - read 1byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+u8
+reg_r8_usb_88xx(struct halmac_adapter *adapter, u32 offset)
+{
+ u8 value8;
+
+ value8 = PLTFM_REG_R8(offset);
+
+ return value8;
+}
+
+/**
+ * reg_w8_usb_88xx() - write 1byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * @value : register value
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+reg_w8_usb_88xx(struct halmac_adapter *adapter, u32 offset, u8 value)
+{
+ PLTFM_REG_W8(offset, value);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * reg_r16_usb_88xx() - read 2byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+u16
+reg_r16_usb_88xx(struct halmac_adapter *adapter, u32 offset)
+{
+ u16 value16;
+
+ value16 = PLTFM_REG_R16(offset);
+
+ return value16;
+}
+
+/**
+ * reg_w16_usb_88xx() - write 2byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * @value : register value
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+reg_w16_usb_88xx(struct halmac_adapter *adapter, u32 offset, u16 value)
+{
+ PLTFM_REG_W16(offset, value);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * reg_r32_usb_88xx() - read 4byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+u32
+reg_r32_usb_88xx(struct halmac_adapter *adapter, u32 offset)
+{
+ u32 value32;
+
+ value32 = PLTFM_REG_R32(offset);
+
+ return value32;
+}
+
+/**
+ * reg_w32_usb_88xx() - write 4byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * @value : register value
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+reg_w32_usb_88xx(struct halmac_adapter *adapter, u32 offset, u32 value)
+{
+ PLTFM_REG_W32(offset, value);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * set_usb_bulkout_num_88xx() - inform bulk-out num
+ * @adapter : the adapter of halmac
+ * @bulkout_num : usb bulk-out number
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+set_usb_bulkout_num_88xx(struct halmac_adapter *adapter, u8 num)
+{
+ adapter->bulkout_num = num;
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * get_usb_bulkout_id_88xx() - get bulk out id for the TX packet
+ * @adapter : the adapter of halmac
+ * @buf : tx packet, include txdesc
+ * @size : tx packet size
+ * @id : usb bulk-out id
+ * Author : KaiYuan Chang
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+get_usb_bulkout_id_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
+ u8 *id)
+{
+ enum halmac_qsel queue_sel;
+ enum halmac_dma_mapping dma_mapping;
+
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
+
+ if (!buf) {
+ PLTFM_MSG_ERR("[ERR]buf is NULL!!\n");
+ return HALMAC_RET_DATA_BUF_NULL;
+ }
+
+ if (size == 0) {
+ PLTFM_MSG_ERR("[ERR]size is 0!!\n");
+ return HALMAC_RET_DATA_SIZE_INCORRECT;
+ }
+
+ queue_sel = (enum halmac_qsel)GET_TX_DESC_QSEL(buf);
+
+ switch (queue_sel) {
+ case HALMAC_QSEL_VO:
+ case HALMAC_QSEL_VO_V2:
+ dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_VO];
+ break;
+ case HALMAC_QSEL_VI:
+ case HALMAC_QSEL_VI_V2:
+ dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_VI];
+ break;
+ case HALMAC_QSEL_BE:
+ case HALMAC_QSEL_BE_V2:
+ dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_BE];
+ break;
+ case HALMAC_QSEL_BK:
+ case HALMAC_QSEL_BK_V2:
+ dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_BK];
+ break;
+ case HALMAC_QSEL_MGNT:
+ dma_mapping = adapter->pq_map[HALMAC_PQ_MAP_MG];
+ break;
+ case HALMAC_QSEL_HIGH:
+ case HALMAC_QSEL_BCN:
+ case HALMAC_QSEL_CMD:
+ dma_mapping = HALMAC_DMA_MAPPING_HIGH;
+ break;
+ default:
+ PLTFM_MSG_ERR("[ERR]Qsel is out of range\n");
+ return HALMAC_RET_QSEL_INCORRECT;
+ }
+
+ switch (dma_mapping) {
+ case HALMAC_DMA_MAPPING_HIGH:
+ *id = 0;
+ break;
+ case HALMAC_DMA_MAPPING_NORMAL:
+ *id = 1;
+ break;
+ case HALMAC_DMA_MAPPING_LOW:
+ *id = 2;
+ break;
+ case HALMAC_DMA_MAPPING_EXTRA:
+ *id = 3;
+ break;
+ default:
+ PLTFM_MSG_ERR("[ERR]out of range\n");
+ return HALMAC_RET_DMA_MAP_INCORRECT;
+ }
+
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+/**
+ * cfg_txagg_usb_align_88xx() -config sdio bus tx agg alignment
+ * @adapter : the adapter of halmac
+ * @enable : function enable(1)/disable(0)
+ * @align_size : sdio bus tx agg alignment size (2^n, n = 3~11)
+ * Author : Soar Tu
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+cfg_txagg_usb_align_88xx(struct halmac_adapter *adapter, u8 enable,
+ u16 align_size)
+{
+ return HALMAC_RET_NOT_SUPPORT;
+}
+
+/**
+ * tx_allowed_usb_88xx() - check tx status
+ * @adapter : the adapter of halmac
+ * @buf : tx packet, include txdesc
+ * @size : tx packet size, include txdesc
+ * Author : Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+tx_allowed_usb_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size)
+{
+ return HALMAC_RET_NOT_SUPPORT;
+}
+
+/**
+ * usb_indirect_reg_r32_88xx() - read MAC reg by SDIO reg
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+u32
+usb_indirect_reg_r32_88xx(struct halmac_adapter *adapter, u32 offset)
+{
+ return 0xFFFFFFFF;
+}
+
+/**
+ * usb_reg_rn_88xx() - read n byte register
+ * @adapter : the adapter of halmac
+ * @offset : register offset
+ * @size : register value size
+ * @value : register value
+ * Author : Soar
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+usb_reg_rn_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
+ u8 *value)
+{
+ return HALMAC_RET_NOT_SUPPORT;
+}
+
+/**
+ * get_usb_tx_addr_88xx() - get CMD53 addr for the TX packet
+ * @adapter : the adapter of halmac
+ * @buf : tx packet, include txdesc
+ * @size : tx packet size
+ * @pcmd53_addr : cmd53 addr value
+ * Author : KaiYuan Chang/Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+get_usb_tx_addr_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
+ u32 *cmd53_addr)
+{
+ return HALMAC_RET_NOT_SUPPORT;
+}
+
+enum halmac_ret_status
+set_usb_mode_88xx(struct halmac_adapter *adapter, enum halmac_usb_mode mode)
+{
+ u32 usb_tmp;
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+ enum halmac_usb_mode cur_mode;
+
+ cur_mode = (HALMAC_REG_R8(REG_SYS_CFG2 + 3) == 0x20) ?
+ HALMAC_USB_MODE_U3 : HALMAC_USB_MODE_U2;
+
+ /*check if HW supports usb2_usb3 switch*/
+ usb_tmp = HALMAC_REG_R32(REG_PAD_CTRL2);
+ if (_FALSE == (BIT_GET_USB23_SW_MODE_V1(usb_tmp) |
+ (usb_tmp & BIT_USB3_USB2_TRANSITION))) {
+ PLTFM_MSG_ERR("[ERR]u2/u3 switch\n");
+ return HALMAC_RET_USB2_3_SWITCH_UNSUPPORT;
+ }
+
+ if (mode == cur_mode) {
+ PLTFM_MSG_ERR("[ERR]u2/u3 unchange\n");
+ return HALMAC_RET_USB_MODE_UNCHANGE;
+ }
+
+ /* Enable IO wrapper timeout */
+ if (adapter->chip_id == HALMAC_CHIP_ID_8822B ||
+ adapter->chip_id == HALMAC_CHIP_ID_8821C)
+ HALMAC_REG_W8_CLR(REG_SW_MDIO + 3, BIT(0));
+
+ usb_tmp &= ~(BIT_USB23_SW_MODE_V1(0x3));
+
+ if (mode == HALMAC_USB_MODE_U2)
+ HALMAC_REG_W32(REG_PAD_CTRL2,
+ usb_tmp |
+ BIT_USB23_SW_MODE_V1(HALMAC_USB_MODE_U2) |
+ BIT_RSM_EN_V1);
+ else
+ HALMAC_REG_W32(REG_PAD_CTRL2,
+ usb_tmp |
+ BIT_USB23_SW_MODE_V1(HALMAC_USB_MODE_U3) |
+ BIT_RSM_EN_V1);
+
+ HALMAC_REG_W8(REG_PAD_CTRL2 + 1, 4);
+ HALMAC_REG_W16_SET(REG_SYS_PW_CTRL, BIT_APFM_OFFMAC);
+ PLTFM_DELAY_US(1000);
+ HALMAC_REG_W32_SET(REG_PAD_CTRL2, BIT_NO_PDN_CHIPOFF_V1);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+enum halmac_ret_status
+usbphy_write_88xx(struct halmac_adapter *adapter, u8 addr, u16 data, u8 speed)
+{
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+
+ if (speed == HAL_INTF_PHY_USB3) {
+ HALMAC_REG_W8(0xff0d, (u8)data);
+ HALMAC_REG_W8(0xff0e, (u8)(data >> 8));
+ HALMAC_REG_W8(0xff0c, addr | BIT(7));
+ } else if (speed == HAL_INTF_PHY_USB2) {
+ HALMAC_REG_W8(0xfe41, (u8)data);
+ HALMAC_REG_W8(0xfe40, addr);
+ HALMAC_REG_W8(0xfe42, 0x81);
+ } else {
+ PLTFM_MSG_ERR("[ERR]Error USB Speed !\n");
+ return HALMAC_RET_NOT_SUPPORT;
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+u16
+usbphy_read_88xx(struct halmac_adapter *adapter, u8 addr, u8 speed)
+{
+ struct halmac_api *api = (struct halmac_api *)adapter->halmac_api;
+ u16 value = 0;
+
+ if (speed == HAL_INTF_PHY_USB3) {
+ HALMAC_REG_W8(0xff0c, addr | BIT(6));
+ value = (u16)(HALMAC_REG_R32(0xff0c) >> 8);
+ } else if (speed == HAL_INTF_PHY_USB2) {
+ if (addr >= 0xE0 && addr <= 0xFF)
+ addr -= 0x20;
+ if (addr >= 0xC0 && addr <= 0xDF) {
+ HALMAC_REG_W8(0xfe40, addr);
+ HALMAC_REG_W8(0xfe42, 0x81);
+ value = HALMAC_REG_R8(0xfe43);
+ } else {
+ PLTFM_MSG_ERR("[ERR]phy offset\n");
+ return HALMAC_RET_NOT_SUPPORT;
+ }
+ } else {
+ PLTFM_MSG_ERR("[ERR]usb speed !\n");
+ return HALMAC_RET_NOT_SUPPORT;
+ }
+
+ return value;
+}
+
+#endif /* HALMAC_88XX_SUPPORT */
diff --git a/hal/halmac/halmac_88xx/halmac_usb_88xx.h b/hal/halmac/halmac_88xx/halmac_usb_88xx.h
new file mode 100644
index 0000000..64ae09a
--- /dev/null
+++ b/hal/halmac/halmac_88xx/halmac_usb_88xx.h
@@ -0,0 +1,87 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_USB_88XX_H_
+#define _HALMAC_USB_88XX_H_
+
+#include "../halmac_api.h"
+
+#if HALMAC_88XX_SUPPORT
+
+enum halmac_ret_status
+init_usb_cfg_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+deinit_usb_cfg_88xx(struct halmac_adapter *adapter);
+
+enum halmac_ret_status
+cfg_usb_rx_agg_88xx(struct halmac_adapter *adapter,
+ struct halmac_rxagg_cfg *cfg);
+
+u8
+reg_r8_usb_88xx(struct halmac_adapter *adapter, u32 offset);
+
+enum halmac_ret_status
+reg_w8_usb_88xx(struct halmac_adapter *adapter, u32 offset, u8 value);
+
+u16
+reg_r16_usb_88xx(struct halmac_adapter *adapter, u32 offset);
+
+enum halmac_ret_status
+reg_w16_usb_88xx(struct halmac_adapter *adapter, u32 offset, u16 value);
+
+u32
+reg_r32_usb_88xx(struct halmac_adapter *adapter, u32 offset);
+
+enum halmac_ret_status
+reg_w32_usb_88xx(struct halmac_adapter *adapter, u32 offset, u32 value);
+
+enum halmac_ret_status
+set_usb_bulkout_num_88xx(struct halmac_adapter *adapter, u8 num);
+
+enum halmac_ret_status
+get_usb_bulkout_id_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
+ u8 *id);
+
+enum halmac_ret_status
+cfg_txagg_usb_align_88xx(struct halmac_adapter *adapter, u8 enable,
+ u16 align_size);
+
+enum halmac_ret_status
+tx_allowed_usb_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size);
+
+u32
+usb_indirect_reg_r32_88xx(struct halmac_adapter *adapter, u32 offset);
+
+enum halmac_ret_status
+usb_reg_rn_88xx(struct halmac_adapter *adapter, u32 offset, u32 size,
+ u8 *value);
+
+enum halmac_ret_status
+get_usb_tx_addr_88xx(struct halmac_adapter *adapter, u8 *buf, u32 size,
+ u32 *cmd53_addr);
+
+enum halmac_ret_status
+set_usb_mode_88xx(struct halmac_adapter *adapter, enum halmac_usb_mode mode);
+
+enum halmac_ret_status
+usbphy_write_88xx(struct halmac_adapter *adapter, u8 addr, u16 data, u8 speed);
+
+u16
+usbphy_read_88xx(struct halmac_adapter *adapter, u8 addr, u8 speed);
+
+#endif /* HALMAC_88XX_SUPPORT */
+
+#endif/* _HALMAC_API_88XX_USB_H_ */
diff --git a/hal/halmac/halmac_api.c b/hal/halmac/halmac_api.c
index 93b7b48..6bf40b8 100644
--- a/hal/halmac/halmac_api.c
+++ b/hal/halmac/halmac_api.c
@@ -1,359 +1,449 @@
-#include "halmac_2_platform.h"
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
#include "halmac_type.h"
-#if HALMAC_PLATFORM_WINDOWS == 1
-#include "halmac_88xx/halmac_api_win8822b.h"
-#include "halmac_88xx/halmac_win8822b_cfg.h"
-#include "halmac_88xx/halmac_api_win8821c.h"
-#include "halmac_88xx/halmac_win8821c_cfg.h"
-#include "halmac_88xx/halmac_api_win8197f.h"
-#include "halmac_88xx/halmac_win8197f_cfg.h"
-#else
-#include "halmac_88xx/halmac_api_88xx.h"
-#include "halmac_88xx/halmac_88xx_cfg.h"
+#include "halmac_api.h"
+
+#if (HALMAC_PLATFORM_WINDOWS)
+
+#if HALMAC_8822B_SUPPORT
+#include "halmac_88xx/halmac_init_win8822b.h"
#endif
-#include "halmac_88xx/halmac_8822b/halmac_8822b_cfg.h"
-#include "halmac_88xx/halmac_8821c/halmac_8821c_cfg.h"
-#include "halmac_88xx/halmac_8197f/halmac_8197f_cfg.h"
+#if HALMAC_8821C_SUPPORT
+#include "halmac_88xx/halmac_init_win8821c.h"
+#endif
-HALMAC_RET_STATUS
-halmac_check_platform_api(
- IN VOID *pDriver_adapter,
- IN HALMAC_INTERFACE halmac_interface,
- IN PHALMAC_PLATFORM_API pHalmac_platform_api
-);
+#if HALMAC_8814B_SUPPORT
+#include "halmac_88xx_v1/halmac_init_win8814b_v1.h"
+#endif
+
+#if HALMAC_8822C_SUPPORT
+#include "halmac_88xx/halmac_init_win8822c.h"
+#endif
+
+#else
+
+#if HALMAC_88XX_SUPPORT
+#include "halmac_88xx/halmac_init_88xx.h"
+#endif
+#if HALMAC_88XX_V1_SUPPORT
+#include "halmac_88xx_v1/halmac_init_88xx_v1.h"
+#endif
+
+#endif
+/* Remove halmac_*/
+enum chip_id_hw_def {
+ CHIP_ID_HW_DEF_8723A = 0x01,
+ CHIP_ID_HW_DEF_8188E = 0x02,
+ CHIP_ID_HW_DEF_8881A = 0x03,
+ CHIP_ID_HW_DEF_8812A = 0x04,
+ CHIP_ID_HW_DEF_8821A = 0x05,
+ CHIP_ID_HW_DEF_8723B = 0x06,
+ CHIP_ID_HW_DEF_8192E = 0x07,
+ CHIP_ID_HW_DEF_8814A = 0x08,
+ CHIP_ID_HW_DEF_8821C = 0x09,
+ CHIP_ID_HW_DEF_8822B = 0x0A,
+ CHIP_ID_HW_DEF_8703B = 0x0B,
+ CHIP_ID_HW_DEF_8188F = 0x0C,
+ CHIP_ID_HW_DEF_8192F = 0x0D,
+ CHIP_ID_HW_DEF_8197F = 0x0E,
+ CHIP_ID_HW_DEF_8723D = 0x0F,
+ CHIP_ID_HW_DEF_8814B = 0x11,
+ CHIP_ID_HW_DEF_8822C = 0x13,
+ CHIP_ID_HW_DEF_UNDEFINE = 0x7F,
+ CHIP_ID_HW_DEF_PS = 0xEA,
+};
+
+static enum halmac_ret_status
+chk_pltfm_api(void *drv_adapter, enum halmac_interface intf,
+ struct halmac_platform_api *pltfm_api);
+
+static enum halmac_ret_status
+get_chip_info(void *drv_adapter, struct halmac_platform_api *pltfm_api,
+ enum halmac_interface intf, struct halmac_adapter *adapter);
+
+static u8
+pltfm_reg_r8_sdio(void *drv_adapter, struct halmac_platform_api *pltfm_api,
+ u32 offset);
+
+static enum halmac_ret_status
+pltfm_reg_w8_sdio(void *drv_adapter, struct halmac_platform_api *pltfm_api,
+ u32 offset, u8 data);
+
+static u8
+pltfm_reg_r_indir_sdio(VOID *drv_adapter, struct halmac_platform_api *pltfm_api,
+ u32 offset);
+
+static enum halmac_ret_status
+cnv_to_sdio_bus_offset(u32 *offset);
/**
* halmac_init_adapter() - init halmac_adapter
- * @pDriver_adapter
- * @pHalmac_platform_api : platform api for halmac used
- * @halmac_interface : PCIE, USB, or SDIO
- * @ppHalmac_adapter
- * @ppHalmac_api
- * Author : KaiYuan Chang
- * Return : HALMAC_RET_STATUS
+ * @drv_adapter : the adapter of caller
+ * @pltfm_api : the platform APIs which is used in halmac
+ * @intf : bus interface
+ * @halmac_adapter : the adapter of halmac
+ * @halmac_api : the function pointer of APIs
+ * Author : KaiYuan Chang / Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
*/
-HALMAC_RET_STATUS
-halmac_init_adapter(
- IN VOID *pDriver_adapter,
- IN PHALMAC_PLATFORM_API pHalmac_platform_api,
- IN HALMAC_INTERFACE halmac_interface,
- OUT PHALMAC_ADAPTER *ppHalmac_adapter,
- OUT PHALMAC_API *ppHalmac_api
-)
+enum halmac_ret_status
+halmac_init_adapter(void *drv_adapter, struct halmac_platform_api *pltfm_api,
+ enum halmac_interface intf,
+ struct halmac_adapter **halmac_adapter,
+ struct halmac_api **halmac_api)
{
- PHALMAC_ADAPTER pHalmac_adapter = (PHALMAC_ADAPTER)NULL;
- HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS;
+ struct halmac_adapter *adapter = NULL;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+ u8 *buf = NULL;
-#if HALMAC_PLATFORM_WINDOWS == 1
- u8 chip_id = 0;
- u32 polling_count;
-#endif
union {
- u32 i;
- u8 x[4];
+ u32 i;
+ u8 x[4];
} ENDIAN_CHECK = { 0x01000000 };
- status = halmac_check_platform_api(pDriver_adapter, halmac_interface, pHalmac_platform_api);
- if (HALMAC_RET_SUCCESS != status)
+ status = chk_pltfm_api(drv_adapter, intf, pltfm_api);
+ if (status != HALMAC_RET_SUCCESS)
return status;
- pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, HALMAC_SVN_VER "\n");
- pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "HALMAC_MAJOR_VER = %x\n", HALMAC_MAJOR_VER);
- pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "HALMAC_PROTOTYPE_VER = %x\n", HALMAC_PROTOTYPE_VER);
- pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "HALMAC_MINOR_VER = %x\n", HALMAC_MINOR_VER);
-
- pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_adapter_88xx ==========>\n");
- /* Check endian setting - Little endian : 1, Big endian : 0*/
- if (HALMAC_SYSTEM_ENDIAN == ENDIAN_CHECK.x[0]) {
- pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Endian setting Err!!\n");
- pHalmac_adapter = (PHALMAC_ADAPTER)NULL;
+ pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS,
+ HALMAC_SVN_VER "\n"
+ "HALMAC_MAJOR_VER = %x\n"
+ "HALMAC_PROTOTYPE_VER = %x\n"
+ "HALMAC_MINOR_VER = %x\n"
+ "HALMAC_PATCH_VER = %x\n",
+ HALMAC_MAJOR_VER, HALMAC_PROTOTYPE_VER,
+ HALMAC_MINOR_VER, HALMAC_PATCH_VER);
+
+ if (ENDIAN_CHECK.x[0] == HALMAC_SYSTEM_ENDIAN) {
+ pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+ HALMAC_DBG_ERR,
+ "[ERR]Endian setting err!!\n");
return HALMAC_RET_ENDIAN_ERR;
}
- pHalmac_adapter = (PHALMAC_ADAPTER)pHalmac_platform_api->RTL_MALLOC(pDriver_adapter, sizeof(HALMAC_ADAPTER));
- if (NULL == pHalmac_adapter) {
- pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Malloc HAL Adapter Err!!\n");
+ buf = (u8 *)pltfm_api->RTL_MALLOC(drv_adapter, sizeof(*adapter));
+
+ if (!buf) {
+ pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+ HALMAC_DBG_ERR,
+ "[ERR]Malloc HAL adapter err!!\n");
return HALMAC_RET_MALLOC_FAIL;
}
+ pltfm_api->RTL_MEMSET(drv_adapter, buf, 0x00, sizeof(*adapter));
+ adapter = (struct halmac_adapter *)buf;
- /* return halmac adapter address to caller */
- *ppHalmac_adapter = pHalmac_adapter;
+ *halmac_adapter = adapter;
- /* Record caller info */
- pHalmac_adapter->pHalmac_platform_api = pHalmac_platform_api;
- pHalmac_adapter->pDriver_adapter = pDriver_adapter;
- pHalmac_adapter->halmac_interface = halmac_interface;
+ adapter->pltfm_api = pltfm_api;
+ adapter->drv_adapter = drv_adapter;
+ intf = (intf == HALMAC_INTERFACE_AXI) ? HALMAC_INTERFACE_PCIE : intf;
+ adapter->intf = intf;
- PLATFORM_MUTEX_INIT(pDriver_adapter, &(pHalmac_adapter->EfuseMutex));
- PLATFORM_MUTEX_INIT(pDriver_adapter, &(pHalmac_adapter->h2c_seq_mutex));
+ if (get_chip_info(drv_adapter, pltfm_api, intf, adapter)
+ != HALMAC_RET_SUCCESS) {
+ PLTFM_FREE(*halmac_adapter, sizeof(**halmac_adapter));
+ *halmac_adapter = NULL;
+ return HALMAC_RET_CHIP_NOT_SUPPORT;
+ }
- /* Assign function pointer to halmac API */
-#if HALMAC_PLATFORM_WINDOWS == 0
- halmac_init_adapter_para_88xx(pHalmac_adapter);
- status = halmac_mount_api_88xx(pHalmac_adapter);
-#else
- /* Get Chip_id and Chip_version */
- if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface) {
- chip_id = pHalmac_platform_api->SDIO_CMD52_READ(pDriver_adapter, REG_SYS_CFG2);
- if (chip_id == 0xEA)
- pHalmac_platform_api->SDIO_CMD52_WRITE(pDriver_adapter, REG_SDIO_HSUS_CTRL, pHalmac_platform_api->SDIO_CMD52_READ(pHalmac_adapter, REG_SDIO_HSUS_CTRL) & ~(BIT(0)));
-
- polling_count = HALMAC_POLLING_READY_TIMEOUT_COUNT;
- while (!(pHalmac_platform_api->SDIO_CMD52_READ(pDriver_adapter, REG_SDIO_HSUS_CTRL) & 0x02)) {
- polling_count--;
- if (polling_count == 0)
- return HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL;
- }
+ PLTFM_MUTEX_INIT(&adapter->efuse_mutex);
+ PLTFM_MUTEX_INIT(&adapter->h2c_seq_mutex);
+ PLTFM_MUTEX_INIT(&adapter->sdio_indir_mutex);
- chip_id = pHalmac_platform_api->SDIO_CMD52_READ(pDriver_adapter, REG_SYS_CFG2);
- } else {
- chip_id = pHalmac_platform_api->REG_READ_8(pDriver_adapter, REG_SYS_CFG2);
+#if (HALMAC_PLATFORM_WINDOWS == 0)
+
+#if HALMAC_88XX_SUPPORT
+ if (adapter->chip_id == HALMAC_CHIP_ID_8822B ||
+ adapter->chip_id == HALMAC_CHIP_ID_8821C ||
+ adapter->chip_id == HALMAC_CHIP_ID_8822C) {
+ init_adapter_param_88xx(adapter);
+ status = mount_api_88xx(adapter);
+ }
+#endif
+
+#if HALMAC_88XX_V1_SUPPORT
+ if (adapter->chip_id == HALMAC_CHIP_ID_8814B) {
+ init_adapter_param_88xx_v1(adapter);
+ status = mount_api_88xx_v1(adapter);
}
+#endif
+
+#else
#if HALMAC_8822B_SUPPORT
- if (HALMAC_CHIP_ID_HW_DEF_8822B == chip_id) {
- halmac_init_adapter_para_win8822b(pHalmac_adapter);
- status = halmac_mount_api_win8822b(pHalmac_adapter);
+ if (adapter->chip_id == HALMAC_CHIP_ID_8822B) {
+ init_adapter_param_win8822b(adapter);
+ status = mount_api_win8822b(adapter);
}
#endif
+
#if HALMAC_8821C_SUPPORT
- if (HALMAC_CHIP_ID_HW_DEF_8821C == chip_id) {
- halmac_init_adapter_para_win8821c(pHalmac_adapter);
- status = halmac_mount_api_win8821c(pHalmac_adapter);
+ if (adapter->chip_id == HALMAC_CHIP_ID_8821C) {
+ init_adapter_param_win8821c(adapter);
+ status = mount_api_win8821c(adapter);
}
#endif
-#if HALMAC_8197F_SUPPORT
- if (HALMAC_CHIP_ID_HW_DEF_8197F == chip_id) {
- halmac_init_adapter_para_win8197f(pHalmac_adapter);
- status = halmac_mount_api_win8197f(pHalmac_adapter);
+
+#if HALMAC_8814B_SUPPORT
+ if (adapter->chip_id == HALMAC_CHIP_ID_8814B) {
+ init_adapter_param_win8814b_v1(adapter);
+ status = mount_api_win8814b_v1(adapter);
}
#endif
+#if HALMAC_8822C_SUPPORT
+ if (adapter->chip_id == HALMAC_CHIP_ID_8822C) {
+ init_adapter_param_win8822c(adapter);
+ status = mount_api_win8822c(adapter);
+ }
#endif
- /* Return halmac API function pointer */
- *ppHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api;
+#endif
+ *halmac_api = (struct halmac_api *)adapter->halmac_api;
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_adapter_88xx <==========\n");
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
return status;
}
/**
- * halmac_halt_api() - halt all halmac api
- * @pHalmac_adapter
+ * halmac_halt_api() - stop halmac_api action
+ * @adapter : the adapter of halmac
* Author : Ivan Lin
- * Return : HALMAC_RET_STATUS
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
*/
-HALMAC_RET_STATUS
-halmac_halt_api(
- IN PHALMAC_ADAPTER pHalmac_adapter
-)
+enum halmac_ret_status
+halmac_halt_api(struct halmac_adapter *adapter)
{
- VOID *pDriver_adapter = NULL;
- PHALMAC_PLATFORM_API pHalmac_platform_api = (PHALMAC_PLATFORM_API)NULL;
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
+ adapter->halmac_state.api_state = HALMAC_API_STATE_HALT;
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_platform_api = pHalmac_adapter->pHalmac_platform_api;
+ PLTFM_MSG_TRACE("[TRACE]%s <===\n", __func__);
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_halt_api ==========>\n");
- pHalmac_adapter->halmac_state.api_state = HALMAC_API_STATE_HALT;
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_halt_api ==========>\n");
return HALMAC_RET_SUCCESS;
}
/**
* halmac_deinit_adapter() - deinit halmac adapter
- * @pHalmac_adapter
- * Author : KaiYuan Chang
- * Return : HALMAC_RET_STATUS
+ * @adapter : the adapter of halmac
+ * Author : KaiYuan Chang / Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
*/
-HALMAC_RET_STATUS
-halmac_deinit_adapter(
- IN PHALMAC_ADAPTER pHalmac_adapter
-)
+enum halmac_ret_status
+halmac_deinit_adapter(struct halmac_adapter *adapter)
{
- VOID *pDriver_adapter = NULL;
- PHALMAC_PLATFORM_API pHalmac_platform_api = (PHALMAC_PLATFORM_API)NULL;
-
- if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- pDriver_adapter = pHalmac_adapter->pDriver_adapter;
- pHalmac_platform_api = pHalmac_adapter->pHalmac_platform_api;
+ PLTFM_MSG_TRACE("[TRACE]%s ===>\n", __func__);
- PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_deinit_adapter_88xx ==========>\n");
+ PLTFM_MUTEX_DEINIT(&adapter->efuse_mutex);
+ PLTFM_MUTEX_DEINIT(&adapter->h2c_seq_mutex);
+ PLTFM_MUTEX_DEINIT(&adapter->sdio_indir_mutex);
- PLATFORM_MUTEX_DEINIT(pDriver_adapter, &(pHalmac_adapter->EfuseMutex));
- PLATFORM_MUTEX_DEINIT(pDriver_adapter, &(pHalmac_adapter->h2c_seq_mutex));
-
- if (NULL != pHalmac_adapter->pHalEfuse_map) {
- PLATFORM_RTL_FREE(pDriver_adapter, pHalmac_adapter->pHalEfuse_map, pHalmac_adapter->hw_config_info.efuse_size);
- pHalmac_adapter->pHalEfuse_map = (u8 *)NULL;
+ if (adapter->efuse_map) {
+ PLTFM_FREE(adapter->efuse_map, adapter->hw_cfg_info.efuse_size);
+ adapter->efuse_map = (u8 *)NULL;
}
- if (NULL != pHalmac_adapter->halmac_state.psd_set.pData) {
- PLATFORM_RTL_FREE(pDriver_adapter, pHalmac_adapter->halmac_state.psd_set.pData, pHalmac_adapter->halmac_state.psd_set.data_size);
- pHalmac_adapter->halmac_state.psd_set.pData = (u8 *)NULL;
+ if (adapter->sdio_fs.macid_map) {
+ PLTFM_FREE(adapter->sdio_fs.macid_map,
+ adapter->sdio_fs.macid_map_size);
+ adapter->sdio_fs.macid_map = (u8 *)NULL;
}
- if (NULL != pHalmac_adapter->pHalmac_api) {
- PLATFORM_RTL_FREE(pDriver_adapter, pHalmac_adapter->pHalmac_api, sizeof(HALMAC_API));
- pHalmac_adapter->pHalmac_api = NULL;
+ if (adapter->halmac_state.psd_state.data) {
+ PLTFM_FREE(adapter->halmac_state.psd_state.data,
+ adapter->halmac_state.psd_state.data_size);
+ adapter->halmac_state.psd_state.data = (u8 *)NULL;
}
- if (NULL != pHalmac_adapter) {
- pHalmac_adapter->pHalAdapter_backup = NULL;
- PLATFORM_RTL_FREE(pDriver_adapter, pHalmac_adapter, sizeof(HALMAC_ADAPTER));
- pHalmac_adapter = (PHALMAC_ADAPTER)NULL;
+ if (adapter->halmac_api) {
+ PLTFM_FREE(adapter->halmac_api, sizeof(struct halmac_api));
+ adapter->halmac_api = NULL;
}
+ PLTFM_FREE(adapter, sizeof(*adapter));
+
return HALMAC_RET_SUCCESS;
}
-/**
- * halmac_check_platform_api() - check platform api pointers
- * @pDriver_adapter
- * @halmac_interface : PCIE, USB or SDIO
- * @pHalmac_platform_api
- * Author : KaiYuan Chang
- * Return : HALMAC_RET_STATUS
- */
-HALMAC_RET_STATUS
-halmac_check_platform_api(
- IN VOID *pDriver_adapter,
- IN HALMAC_INTERFACE halmac_interface,
- IN PHALMAC_PLATFORM_API pHalmac_platform_api
-)
+static enum halmac_ret_status
+chk_pltfm_api(void *drv_adapter, enum halmac_interface intf,
+ struct halmac_platform_api *pltfm_api)
{
- VOID *pAdapter_Local = NULL;
-
- pAdapter_Local = pDriver_adapter;
-
- if (NULL == pHalmac_platform_api)
+ if (!pltfm_api)
return HALMAC_RET_PLATFORM_API_NULL;
- if (NULL == pHalmac_platform_api->MSG_PRINT)
+ if (!pltfm_api->MSG_PRINT)
return HALMAC_RET_PLATFORM_API_NULL;
- if (HALMAC_INTERFACE_SDIO == halmac_interface) {
- if (NULL == pHalmac_platform_api->SDIO_CMD52_READ) {
- pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD52_READ)\n");
+ if (intf == HALMAC_INTERFACE_SDIO) {
+ if (!pltfm_api->SDIO_CMD52_READ) {
+ pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+ HALMAC_DBG_ERR, "[ERR]sdio-r\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
- if (NULL == pHalmac_platform_api->SDIO_CMD53_READ_8) {
- pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD53_READ_8)\n");
+ if (!pltfm_api->SDIO_CMD53_READ_8) {
+ pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+ HALMAC_DBG_ERR, "[ERR]sdio-r8\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
- if (NULL == pHalmac_platform_api->SDIO_CMD53_READ_16) {
- pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD53_READ_16)\n");
+ if (!pltfm_api->SDIO_CMD53_READ_16) {
+ pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+ HALMAC_DBG_ERR, "[ERR]sdio-r16\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
- if (NULL == pHalmac_platform_api->SDIO_CMD53_READ_32) {
- pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD53_READ_32)\n");
+ if (!pltfm_api->SDIO_CMD53_READ_32) {
+ pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+ HALMAC_DBG_ERR, "[ERR]sdio-r32\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
- if (NULL == pHalmac_platform_api->SDIO_CMD52_WRITE) {
- pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD52_WRITE)\n");
+ if (!pltfm_api->SDIO_CMD53_READ_N) {
+ pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+ HALMAC_DBG_ERR, "[ERR]sdio-rn\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
- if (NULL == pHalmac_platform_api->SDIO_CMD53_WRITE_8) {
- pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD53_WRITE_8)\n");
+ if (!pltfm_api->SDIO_CMD52_WRITE) {
+ pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+ HALMAC_DBG_ERR, "[ERR]sdio-w\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
- if (NULL == pHalmac_platform_api->SDIO_CMD53_WRITE_16) {
- pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD53_WRITE_16)\n");
+ if (!pltfm_api->SDIO_CMD53_WRITE_8) {
+ pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+ HALMAC_DBG_ERR, "[ERR]sdio-w8\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
- if (NULL == pHalmac_platform_api->SDIO_CMD53_WRITE_32) {
- pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD53_WRITE_32)\n");
+ if (!pltfm_api->SDIO_CMD53_WRITE_16) {
+ pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+ HALMAC_DBG_ERR, "[ERR]sdio-w16\n");
+ return HALMAC_RET_PLATFORM_API_NULL;
+ }
+ if (!pltfm_api->SDIO_CMD53_WRITE_32) {
+ pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+ HALMAC_DBG_ERR, "[ERR]sdio-w32\n");
+ return HALMAC_RET_PLATFORM_API_NULL;
+ }
+ if (!pltfm_api->SDIO_CMD52_CIA_READ) {
+ pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+ HALMAC_DBG_ERR, "[ERR]sdio-cia\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
}
- if ((HALMAC_INTERFACE_USB == halmac_interface) || (HALMAC_INTERFACE_PCIE == halmac_interface)) {
- if (NULL == pHalmac_platform_api->REG_READ_8) {
- pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->REG_READ_8)\n");
+ if (intf == HALMAC_INTERFACE_USB || intf == HALMAC_INTERFACE_PCIE) {
+ if (!pltfm_api->REG_READ_8) {
+ pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+ HALMAC_DBG_ERR, "[ERR]reg-r8\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
- if (NULL == pHalmac_platform_api->REG_READ_16) {
- pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->REG_READ_16)\n");
+ if (!pltfm_api->REG_READ_16) {
+ pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+ HALMAC_DBG_ERR, "[ERR]reg-r16\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
- if (NULL == pHalmac_platform_api->REG_READ_32) {
- pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->REG_READ_32)\n");
+ if (!pltfm_api->REG_READ_32) {
+ pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+ HALMAC_DBG_ERR, "[ERR]reg-r32\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
- if (NULL == pHalmac_platform_api->REG_WRITE_8) {
- pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->REG_WRITE_8)\n");
+ if (!pltfm_api->REG_WRITE_8) {
+ pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+ HALMAC_DBG_ERR, "[ERR]reg-w8\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
- if (NULL == pHalmac_platform_api->REG_WRITE_16) {
- pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->REG_WRITE_16)\n");
+ if (!pltfm_api->REG_WRITE_16) {
+ pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+ HALMAC_DBG_ERR, "[ERR]reg-w16\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
- if (NULL == pHalmac_platform_api->REG_WRITE_32) {
- pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->REG_WRITE_32)\n");
+ if (!pltfm_api->REG_WRITE_32) {
+ pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+ HALMAC_DBG_ERR, "[ERR]reg-w32\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
}
- if (NULL == pHalmac_platform_api->RTL_FREE) {
- pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->RTL_FREE)\n");
+ if (!pltfm_api->RTL_FREE) {
+ pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+ HALMAC_DBG_ERR, "[ERR]mem-free\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
- if (NULL == pHalmac_platform_api->RTL_MALLOC) {
- pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->RTL_MALLOC)\n");
+ if (!pltfm_api->RTL_MALLOC) {
+ pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+ HALMAC_DBG_ERR, "[ERR]mem-malloc\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
- if (NULL == pHalmac_platform_api->RTL_MEMCPY) {
- pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->RTL_MEMCPY)\n");
+ if (!pltfm_api->RTL_MEMCPY) {
+ pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+ HALMAC_DBG_ERR, "[ERR]mem-cpy\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
- if (NULL == pHalmac_platform_api->RTL_MEMSET) {
- pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->RTL_MEMSET)\n");
+ if (!pltfm_api->RTL_MEMSET) {
+ pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+ HALMAC_DBG_ERR, "[ERR]mem-set\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
- if (NULL == pHalmac_platform_api->RTL_DELAY_US) {
- pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->RTL_DELAY_US)\n");
+ if (!pltfm_api->RTL_DELAY_US) {
+ pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+ HALMAC_DBG_ERR, "[ERR]time-delay\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
- if (NULL == pHalmac_platform_api->MUTEX_INIT) {
- pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->MUTEX_INIT)\n");
+ if (!pltfm_api->MUTEX_INIT) {
+ pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+ HALMAC_DBG_ERR, "[ERR]mutex-init\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
- if (NULL == pHalmac_platform_api->MUTEX_DEINIT) {
- pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->MUTEX_DEINIT)\n");
+ if (!pltfm_api->MUTEX_DEINIT) {
+ pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+ HALMAC_DBG_ERR, "[ERR]mutex-deinit\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
- if (NULL == pHalmac_platform_api->MUTEX_LOCK) {
- pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->MUTEX_LOCK)\n");
+ if (!pltfm_api->MUTEX_LOCK) {
+ pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+ HALMAC_DBG_ERR, "[ERR]mutex-lock\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
- if (NULL == pHalmac_platform_api->MUTEX_UNLOCK) {
- pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->MUTEX_UNLOCK)\n");
+ if (!pltfm_api->MUTEX_UNLOCK) {
+ pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+ HALMAC_DBG_ERR, "[ERR]mutex-unlock\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
- if (NULL == pHalmac_platform_api->EVENT_INDICATION) {
- pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->EVENT_INDICATION)\n");
+ if (!pltfm_api->EVENT_INDICATION) {
+ pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+ HALMAC_DBG_ERR, "[ERR]event-indication\n");
return HALMAC_RET_PLATFORM_API_NULL;
}
- pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_check_platform_api ==========>\n");
-
return HALMAC_RET_SUCCESS;
}
-HALMAC_RET_STATUS
-halmac_get_version(
- OUT HALMAC_VER * version
-)
+/**
+ * halmac_get_version() - get HALMAC version
+ * @version : return version of major, prototype and minor information
+ * Author : KaiYuan Chang / Ivan Lin
+ * Return : enum halmac_ret_status
+ * More details of status code can be found in prototype document
+ */
+enum halmac_ret_status
+halmac_get_version(struct halmac_ver *version)
{
version->major_ver = (u8)HALMAC_MAJOR_VER;
version->prototype_ver = (u8)HALMAC_PROTOTYPE_VER;
@@ -361,3 +451,152 @@ halmac_get_version(
return HALMAC_RET_SUCCESS;
}
+
+static enum halmac_ret_status
+get_chip_info(void *drv_adapter, struct halmac_platform_api *pltfm_api,
+ enum halmac_interface intf, struct halmac_adapter *adapter)
+{
+ u8 chip_id;
+ u8 chip_ver;
+ u32 cnt;
+
+ if (adapter->intf == HALMAC_INTERFACE_SDIO) {
+ pltfm_reg_w8_sdio(drv_adapter, pltfm_api, REG_SDIO_HSUS_CTRL,
+ pltfm_reg_r8_sdio(drv_adapter, pltfm_api,
+ REG_SDIO_HSUS_CTRL) &
+ ~(BIT(0)));
+
+ cnt = 10000;
+ while (!(pltfm_reg_r8_sdio(drv_adapter, pltfm_api,
+ REG_SDIO_HSUS_CTRL) & BIT(1))) {
+ cnt--;
+ if (cnt == 0)
+ return HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL;
+ }
+
+ chip_id = pltfm_reg_r_indir_sdio(drv_adapter, pltfm_api,
+ REG_SYS_CFG2);
+ chip_ver = pltfm_reg_r_indir_sdio(drv_adapter, pltfm_api,
+ REG_SYS_CFG1 + 1) >> 4;
+ } else {
+ chip_id = pltfm_api->REG_READ_8(drv_adapter, REG_SYS_CFG2);
+ chip_ver = pltfm_api->REG_READ_8(drv_adapter,
+ REG_SYS_CFG1 + 1) >> 4;
+ }
+
+ adapter->chip_ver = (enum halmac_chip_ver)chip_ver;
+
+ if (chip_id == CHIP_ID_HW_DEF_8822B) {
+ adapter->chip_id = HALMAC_CHIP_ID_8822B;
+ } else if (chip_id == CHIP_ID_HW_DEF_8821C) {
+ adapter->chip_id = HALMAC_CHIP_ID_8821C;
+ } else if (chip_id == CHIP_ID_HW_DEF_8814B) {
+ adapter->chip_id = HALMAC_CHIP_ID_8814B;
+ } else if (chip_id == CHIP_ID_HW_DEF_8197F) {
+ adapter->chip_id = HALMAC_CHIP_ID_8197F;
+ } else if (chip_id == CHIP_ID_HW_DEF_8822C) {
+ adapter->chip_id = HALMAC_CHIP_ID_8822C;
+ } else {
+ adapter->chip_id = HALMAC_CHIP_ID_UNDEFINE;
+ PLTFM_MSG_ERR("[ERR]Chip id is undefined\n");
+ return HALMAC_RET_CHIP_NOT_SUPPORT;
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static u8
+pltfm_reg_r8_sdio(void *drv_adapter, struct halmac_platform_api *pltfm_api,
+ u32 offset)
+{
+ u8 value8;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ if (0 == (offset & 0xFFFF0000))
+ offset |= WLAN_IOREG_OFFSET;
+
+ status = cnv_to_sdio_bus_offset(&offset);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+
+ value8 = pltfm_api->SDIO_CMD52_READ(drv_adapter, offset);
+
+ return value8;
+}
+
+static enum halmac_ret_status
+pltfm_reg_w8_sdio(void *drv_adapter, struct halmac_platform_api *pltfm_api,
+ u32 offset, u8 data)
+{
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ if (0 == (offset & 0xFFFF0000))
+ offset |= WLAN_IOREG_OFFSET;
+
+ status = cnv_to_sdio_bus_offset(&offset);
+
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+
+ pltfm_api->SDIO_CMD52_WRITE(drv_adapter, offset, data);
+
+ return HALMAC_RET_SUCCESS;
+}
+
+static u8
+pltfm_reg_r_indir_sdio(VOID *drv_adapter, struct halmac_platform_api *pltfm_api,
+ u32 offset)
+{
+ u8 value8, tmp, cnt = 50;
+ u32 reg_cfg = REG_SDIO_INDIRECT_REG_CFG;
+ u32 reg_data = REG_SDIO_INDIRECT_REG_DATA;
+ enum halmac_ret_status status = HALMAC_RET_SUCCESS;
+
+ status = cnv_to_sdio_bus_offset(®_cfg);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+ status = cnv_to_sdio_bus_offset(®_data);
+ if (status != HALMAC_RET_SUCCESS)
+ return status;
+
+ pltfm_api->SDIO_CMD52_WRITE(drv_adapter, reg_cfg, (u8)offset);
+ pltfm_api->SDIO_CMD52_WRITE(drv_adapter, reg_cfg + 1,
+ (u8)(offset >> 8));
+ pltfm_api->SDIO_CMD52_WRITE(drv_adapter, reg_cfg + 2,
+ (u8)(BIT(3) | BIT(4)));
+
+ do {
+ tmp = pltfm_api->SDIO_CMD52_READ(drv_adapter, reg_cfg + 2);
+ cnt--;
+ } while (((tmp & BIT(4)) == 0) && (cnt > 0));
+
+ if (((cnt & BIT(4)) == 0) && cnt == 0)
+ pltfm_api->MSG_PRINT(drv_adapter, HALMAC_MSG_INIT,
+ HALMAC_DBG_ERR, "[ERR]sdio indir read\n");
+
+ value8 = pltfm_api->SDIO_CMD52_READ(drv_adapter, reg_data);
+
+ return value8;
+}
+
+/*Note: copy from cnv_to_sdio_bus_offset_88xx*/
+static enum halmac_ret_status
+cnv_to_sdio_bus_offset(u32 *offset)
+{
+ switch ((*offset) & 0xFFFF0000) {
+ case WLAN_IOREG_OFFSET:
+ *offset &= HALMAC_WLAN_MAC_REG_MSK;
+ *offset |= HALMAC_SDIO_CMD_ADDR_MAC_REG << 13;
+ break;
+ case SDIO_LOCAL_OFFSET:
+ *offset &= HALMAC_SDIO_LOCAL_MSK;
+ *offset |= HALMAC_SDIO_CMD_ADDR_SDIO_REG << 13;
+ break;
+ default:
+ *offset = 0xFFFFFFFF;
+ return HALMAC_RET_CONVERT_SDIO_OFFSET_FAIL;
+ }
+
+ return HALMAC_RET_SUCCESS;
+}
+
diff --git a/hal/halmac/halmac_api.h b/hal/halmac/halmac_api.h
index a10436e..219bf60 100644
--- a/hal/halmac/halmac_api.h
+++ b/hal/halmac/halmac_api.h
@@ -1,28 +1,79 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
#ifndef _HALMAC_API_H_
#define _HALMAC_API_H_
-#define HALMAC_SVN_VER "11974M"
+#define HALMAC_SVN_VER "11692M"
-/* major version, ver_1 for async_api */
#define HALMAC_MAJOR_VER 0x0001
-/* For halmac_api num change or prototype change, increment prototype version */
-#define HALMAC_PROTOTYPE_VER 0x0002
-/* else increment minor version */
-#define HALMAC_MINOR_VER 0x0000
+#define HALMAC_PROTOTYPE_VER 0x0004
+#define HALMAC_MINOR_VER 0x0008
+#define HALMAC_PATCH_VER 0x0003
+
+#define HALMAC_88XX_SUPPORT (HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define HALMAC_88XX_V1_SUPPORT HALMAC_8814B_SUPPORT
#include "halmac_2_platform.h"
-#include "halmac_hw_cfg.h"
#include "halmac_type.h"
-
+#include "halmac_hw_cfg.h"
#include "halmac_usb_reg.h"
#include "halmac_sdio_reg.h"
#include "halmac_pcie_reg.h"
-
#include "halmac_bit2.h"
#include "halmac_reg2.h"
+#if HALMAC_PLATFORM_TESTPROGRAM
+#include "halmac_type_testprogram.h"
+#endif
+
+#ifndef HALMAC_USE_TYPEDEF
+#define HALMAC_USE_TYPEDEF 1
+#endif
+
+#if HALMAC_USE_TYPEDEF
+#include "halmac_typedef.h"
+#endif
+
+#if HALMAC_8822B_SUPPORT
+#include "halmac_reg_8822b.h"
+#include "halmac_bit_8822b.h"
+#endif
+
+#if HALMAC_8821C_SUPPORT
+#include "halmac_reg_8821c.h"
+#include "halmac_bit_8821c.h"
+#endif
+
+#if HALMAC_8814B_SUPPORT
+#include "halmac_reg_8814b.h"
+#include "halmac_bit_8814b.h"
+#endif
+
+#if HALMAC_8822C_SUPPORT
+#include "halmac_reg_8822c.h"
+#include "halmac_bit_8822c.h"
+#endif
+
#if (HALMAC_PLATFORM_WINDOWS || HALMAC_PLATFORM_LINUX)
#include "halmac_tx_desc_nic.h"
+#include "halmac_tx_desc_buffer_nic.h"
+#include "halmac_tx_desc_ie_nic.h"
#include "halmac_rx_desc_nic.h"
#include "halmac_tx_bd_nic.h"
#include "halmac_rx_bd_nic.h"
@@ -36,8 +87,8 @@
#if (HALMAC_PLATFORM_AP)
#include "halmac_rx_desc_ap.h"
#include "halmac_tx_desc_ap.h"
-#include "halmac_rx_bd_ap.h"
-#include "halmac_tx_bd_ap.h"
+#include "halmac_tx_desc_buffer_ap.h"
+#include "halmac_tx_desc_ie_ap.h"
#include "halmac_fw_offload_c2h_ap.h"
#include "halmac_fw_offload_h2c_ap.h"
#include "halmac_h2c_extra_info_ap.h"
@@ -47,47 +98,22 @@
#include "halmac_tx_desc_chip.h"
#include "halmac_rx_desc_chip.h"
-#include "halmac_tx_bd_chip.h"
-#include "halmac_rx_bd_chip.h"
-#if HALMAC_PLATFORM_WINDOWS == 1
-#include "halmac_88xx/halmac_win8822b_cfg.h"
-#include "halmac_88xx/halmac_win8821c_cfg.h"
-#include "halmac_88xx/halmac_win8197f_cfg.h"
-#else
-#include "halmac_88xx/halmac_88xx_cfg.h"
-#endif
+#include "halmac_tx_desc_buffer_chip.h"
+#include "halmac_tx_desc_ie_chip.h"
-#include "halmac_88xx/halmac_8822b/halmac_8822b_cfg.h"
-#include "halmac_88xx/halmac_8821c/halmac_8821c_cfg.h"
-#include "halmac_88xx/halmac_8197f/halmac_8197f_cfg.h"
-#include "halmac_reg_8822b.h"
-#include "halmac_bit_8822b.h"
-#include "halmac_reg_8821c.h"
-#include "halmac_bit_8821c.h"
+enum halmac_ret_status
+halmac_init_adapter(void *drv_adapter, struct halmac_platform_api *pltfm_api,
+ enum halmac_interface intf,
+ struct halmac_adapter **halmac_adapter,
+ struct halmac_api **halmac_api);
+
+enum halmac_ret_status
+halmac_deinit_adapter(struct halmac_adapter *adapter);
+enum halmac_ret_status
+halmac_halt_api(struct halmac_adapter *adapter);
-HALMAC_RET_STATUS
-halmac_init_adapter(
- IN VOID *pDriver_adapter,
- IN PHALMAC_PLATFORM_API pHalmac_platform_api,
- IN HALMAC_INTERFACE halmac_interface,
- OUT PHALMAC_ADAPTER *ppHalmac_adapter,
- OUT PHALMAC_API *ppHalmac_api
-);
-
-HALMAC_RET_STATUS
-halmac_deinit_adapter(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-HALMAC_RET_STATUS
-halmac_halt_api(
- IN PHALMAC_ADAPTER pHalmac_adapter
-);
-
-HALMAC_RET_STATUS
-halmac_get_version(
- OUT HALMAC_VER * version
-);
+enum halmac_ret_status
+halmac_get_version(struct halmac_ver *version);
#endif
diff --git a/hal/halmac/halmac_bit2.h b/hal/halmac/halmac_bit2.h
index e5191d8..d54ba86 100644
--- a/hal/halmac/halmac_bit2.h
+++ b/hal/halmac/halmac_bit2.h
@@ -1,34158 +1,63930 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
#ifndef __RTL_WLAN_BITDEF_H__
#define __RTL_WLAN_BITDEF_H__
-/*-------------------------Modification Log-----------------------------------
- Base on MAC_Register.doc SVN391
--------------------------Modification Log-----------------------------------*/
-
-/*--------------------------Include File--------------------------------------*/
#include "halmac_hw_cfg.h"
-/*--------------------------Include File--------------------------------------*/
-/* 3 ============Programming guide Start===================== */
-/*
- 1. For all bit define, it should be prefixed by "BIT_"
- 2. For all bit mask, it should be prefixed by "BIT_MASK_"
- 3. For all bit shift, it should be prefixed by "BIT_SHIFT_"
- 4. For other case, prefix is not needed
+#define CPU_OPT_WIDTH 0x1F
-Example:
-#define BIT_SHIFT_MAX_TXDMA 16
-#define BIT_MASK_MAX_TXDMA 0x7
-#define BIT_MAX_TXDMA(x) (((x) & BIT_MASK_MAX_TXDMA)<> BIT_SHIFT_MAX_TXDMA) & BIT_MASK_MAX_TXDMA)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME BIT(31)
-*/
-/* 3 ============Programming guide End===================== */
+#define BIT_SHIFT_GTAB_ID 28
+#define BIT_MASK_GTAB_ID 0x7
+#define BIT_GTAB_ID(x) (((x) & BIT_MASK_GTAB_ID) << BIT_SHIFT_GTAB_ID)
+#define BITS_GTAB_ID (BIT_MASK_GTAB_ID << BIT_SHIFT_GTAB_ID)
+#define BIT_CLEAR_GTAB_ID(x) ((x) & (~BITS_GTAB_ID))
+#define BIT_GET_GTAB_ID(x) (((x) >> BIT_SHIFT_GTAB_ID) & BIT_MASK_GTAB_ID)
+#define BIT_SET_GTAB_ID(x, v) (BIT_CLEAR_GTAB_ID(x) | BIT_GTAB_ID(v))
-#define CPU_OPT_WIDTH 0x1F
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#define BIT_MULRW BIT(27)
+
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)
+#define BIT_CPRST BIT(23)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_WATCH_DOG_RECORD_V1 10
-#define BIT_MASK_WATCH_DOG_RECORD_V1 0x3fff
-#define BIT_WATCH_DOG_RECORD_V1(x) (((x) & BIT_MASK_WATCH_DOG_RECORD_V1) << BIT_SHIFT_WATCH_DOG_RECORD_V1)
-#define BIT_GET_WATCH_DOG_RECORD_V1(x) (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1) & BIT_MASK_WATCH_DOG_RECORD_V1)
+#define BIT_SHIFT_COUNTER_BASE 16
+#define BIT_MASK_COUNTER_BASE 0x1fff
+#define BIT_COUNTER_BASE(x) \
+ (((x) & BIT_MASK_COUNTER_BASE) << BIT_SHIFT_COUNTER_BASE)
+#define BITS_COUNTER_BASE (BIT_MASK_COUNTER_BASE << BIT_SHIFT_COUNTER_BASE)
+#define BIT_CLEAR_COUNTER_BASE(x) ((x) & (~BITS_COUNTER_BASE))
+#define BIT_GET_COUNTER_BASE(x) \
+ (((x) >> BIT_SHIFT_COUNTER_BASE) & BIT_MASK_COUNTER_BASE)
+#define BIT_SET_COUNTER_BASE(x, v) \
+ (BIT_CLEAR_COUNTER_BASE(x) | BIT_COUNTER_BASE(v))
-#define BIT_R_IO_TIMEOUT_FLAG_V1 BIT(9)
+#define BIT_SHIFT_AGG_VALUE2 16
+#define BIT_MASK_AGG_VALUE2 0x7f
+#define BIT_AGG_VALUE2(x) (((x) & BIT_MASK_AGG_VALUE2) << BIT_SHIFT_AGG_VALUE2)
+#define BITS_AGG_VALUE2 (BIT_MASK_AGG_VALUE2 << BIT_SHIFT_AGG_VALUE2)
+#define BIT_CLEAR_AGG_VALUE2(x) ((x) & (~BITS_AGG_VALUE2))
+#define BIT_GET_AGG_VALUE2(x) \
+ (((x) >> BIT_SHIFT_AGG_VALUE2) & BIT_MASK_AGG_VALUE2)
+#define BIT_SET_AGG_VALUE2(x, v) (BIT_CLEAR_AGG_VALUE2(x) | BIT_AGG_VALUE2(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8881A_SUPPORT)
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1 BIT(15)
+#endif
-#define BIT_SHIFT_NPQ_AVAL_PG 8
-#define BIT_MASK_NPQ_AVAL_PG 0xff
-#define BIT_NPQ_AVAL_PG(x) (((x) & BIT_MASK_NPQ_AVAL_PG) << BIT_SHIFT_NPQ_AVAL_PG)
-#define BIT_GET_NPQ_AVAL_PG(x) (((x) >> BIT_SHIFT_NPQ_AVAL_PG) & BIT_MASK_NPQ_AVAL_PG)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+#define BIT_SHIFT_XTAL_DRV_RF1 13
+#define BIT_MASK_XTAL_DRV_RF1 0x3
+#define BIT_XTAL_DRV_RF1(x) \
+ (((x) & BIT_MASK_XTAL_DRV_RF1) << BIT_SHIFT_XTAL_DRV_RF1)
+#define BITS_XTAL_DRV_RF1 (BIT_MASK_XTAL_DRV_RF1 << BIT_SHIFT_XTAL_DRV_RF1)
+#define BIT_CLEAR_XTAL_DRV_RF1(x) ((x) & (~BITS_XTAL_DRV_RF1))
+#define BIT_GET_XTAL_DRV_RF1(x) \
+ (((x) >> BIT_SHIFT_XTAL_DRV_RF1) & BIT_MASK_XTAL_DRV_RF1)
+#define BIT_SET_XTAL_DRV_RF1(x, v) \
+ (BIT_CLEAR_XTAL_DRV_RF1(x) | BIT_XTAL_DRV_RF1(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define BIT_EN_WATCH_DOG_V1 BIT(8)
+#define BIT_ATIMEND BIT(12)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8881A_SUPPORT)
-
-#define BIT_AFE_MBIAS BIT(1)
+#define BIT_SHIFT_GTAB_ID_V1 12
+#define BIT_MASK_GTAB_ID_V1 0x7
+#define BIT_GTAB_ID_V1(x) (((x) & BIT_MASK_GTAB_ID_V1) << BIT_SHIFT_GTAB_ID_V1)
+#define BITS_GTAB_ID_V1 (BIT_MASK_GTAB_ID_V1 << BIT_SHIFT_GTAB_ID_V1)
+#define BIT_CLEAR_GTAB_ID_V1(x) ((x) & (~BITS_GTAB_ID_V1))
+#define BIT_GET_GTAB_ID_V1(x) \
+ (((x) >> BIT_SHIFT_GTAB_ID_V1) & BIT_MASK_GTAB_ID_V1)
+#define BIT_SET_GTAB_ID_V1(x, v) (BIT_CLEAR_GTAB_ID_V1(x) | BIT_GTAB_ID_V1(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#define BIT_SHIFT_WATCH_DOG_RECORD_V1 10
+#define BIT_MASK_WATCH_DOG_RECORD_V1 0x3fff
+#define BIT_WATCH_DOG_RECORD_V1(x) \
+ (((x) & BIT_MASK_WATCH_DOG_RECORD_V1) << BIT_SHIFT_WATCH_DOG_RECORD_V1)
+#define BITS_WATCH_DOG_RECORD_V1 \
+ (BIT_MASK_WATCH_DOG_RECORD_V1 << BIT_SHIFT_WATCH_DOG_RECORD_V1)
+#define BIT_CLEAR_WATCH_DOG_RECORD_V1(x) ((x) & (~BITS_WATCH_DOG_RECORD_V1))
+#define BIT_GET_WATCH_DOG_RECORD_V1(x) \
+ (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1) & BIT_MASK_WATCH_DOG_RECORD_V1)
+#define BIT_SET_WATCH_DOG_RECORD_V1(x, v) \
+ (BIT_CLEAR_WATCH_DOG_RECORD_V1(x) | BIT_WATCH_DOG_RECORD_V1(v))
-#define BIT_ISO_MD2PP BIT(0)
+#endif
-/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT)
+#define BIT_R_8051_SPD BIT(9)
-#define BIT_SHIFT_SDIO_INT_TIMEOUT 16
-#define BIT_MASK_SDIO_INT_TIMEOUT 0xffff
-#define BIT_SDIO_INT_TIMEOUT(x) (((x) & BIT_MASK_SDIO_INT_TIMEOUT) << BIT_SHIFT_SDIO_INT_TIMEOUT)
-#define BIT_GET_SDIO_INT_TIMEOUT(x) (((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT) & BIT_MASK_SDIO_INT_TIMEOUT)
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+#define BIT_EN_RTS_REQ BIT(9)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#define BIT_R_IO_TIMEOUT_FLAG_V1 BIT(9)
+#endif
-/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_PWC_EV12V BIT(15)
+#define BIT_EN_EDCA_REQ BIT(8)
+
+#define BIT_SHIFT_AGG_VALUE1 8
+#define BIT_MASK_AGG_VALUE1 0x7f
+#define BIT_AGG_VALUE1(x) (((x) & BIT_MASK_AGG_VALUE1) << BIT_SHIFT_AGG_VALUE1)
+#define BITS_AGG_VALUE1 (BIT_MASK_AGG_VALUE1 << BIT_SHIFT_AGG_VALUE1)
+#define BIT_CLEAR_AGG_VALUE1(x) ((x) & (~BITS_AGG_VALUE1))
+#define BIT_GET_AGG_VALUE1(x) \
+ (((x) >> BIT_SHIFT_AGG_VALUE1) & BIT_MASK_AGG_VALUE1)
+#define BIT_SET_AGG_VALUE1(x, v) (BIT_CLEAR_AGG_VALUE1(x) | BIT_AGG_VALUE1(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+#define BIT_EN_WATCH_DOG_V1 BIT(8)
+#endif
-/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_PWC_EBCOEB BIT(15)
+#define BIT_DIS_TXDMA_PRE BIT(7)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#define BIT_RAM_DL_SEL BIT(7)
+#endif
-/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_IO_ERR_STATUS BIT(15)
+#define BIT_EN_PTCL_REQ BIT(7)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#define BIT_DIS_RXDMA_PRE BIT(6)
+#endif
-/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_PWC_EV25V BIT(14)
+#define BIT_WINTINI_RDY BIT(6)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#define BIT_EN_SCH_REQ BIT(6)
+#endif
-/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
+#if (HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_PA33V_EN BIT(13)
-#define BIT_PA12V_EN BIT(12)
+#define BIT_CLR_HGQ_REQ_BLOCK BIT(5)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+#define BIT_TXFLAG_EXIT_L1_EN BIT(2)
+#endif
-/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
+#if (HALMAC_8881A_SUPPORT)
-#define BIT_PC_A15V BIT(12)
+#define BIT_AFE_MBIAS BIT(1)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#define BIT_MCUFWDL_EN BIT(0)
+#endif
-/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_UA33V_EN BIT(11)
-#define BIT_UA12V_EN BIT(10)
+#define BIT_SHIFT_AGG_VALUE0 0
+#define BIT_MASK_AGG_VALUE0 0x7f
+#define BIT_AGG_VALUE0(x) (((x) & BIT_MASK_AGG_VALUE0) << BIT_SHIFT_AGG_VALUE0)
+#define BITS_AGG_VALUE0 (BIT_MASK_AGG_VALUE0 << BIT_SHIFT_AGG_VALUE0)
+#define BIT_CLEAR_AGG_VALUE0(x) ((x) & (~BITS_AGG_VALUE0))
+#define BIT_GET_AGG_VALUE0(x) \
+ (((x) >> BIT_SHIFT_AGG_VALUE0) & BIT_MASK_AGG_VALUE0)
+#define BIT_SET_AGG_VALUE0(x, v) (BIT_CLEAR_AGG_VALUE0(x) | BIT_AGG_VALUE0(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+#define BIT_SHIFT_MDIO_REG_ADDR 0
+#define BIT_MASK_MDIO_REG_ADDR 0x1f
+#define BIT_MDIO_REG_ADDR(x) \
+ (((x) & BIT_MASK_MDIO_REG_ADDR) << BIT_SHIFT_MDIO_REG_ADDR)
+#define BITS_MDIO_REG_ADDR (BIT_MASK_MDIO_REG_ADDR << BIT_SHIFT_MDIO_REG_ADDR)
+#define BIT_CLEAR_MDIO_REG_ADDR(x) ((x) & (~BITS_MDIO_REG_ADDR))
+#define BIT_GET_MDIO_REG_ADDR(x) \
+ (((x) >> BIT_SHIFT_MDIO_REG_ADDR) & BIT_MASK_MDIO_REG_ADDR)
+#define BIT_SET_MDIO_REG_ADDR(x, v) \
+ (BIT_CLEAR_MDIO_REG_ADDR(x) | BIT_MDIO_REG_ADDR(v))
+#endif
-/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
-#define BIT_ISO_AFE_OUTPUT_SIGNAL BIT(10)
+#define BIT_ISO_MD2PP BIT(0)
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */
+
+#define BIT_SHIFT_SDIO_INT_TIMEOUT 16
+#define BIT_MASK_SDIO_INT_TIMEOUT 0xffff
+#define BIT_SDIO_INT_TIMEOUT(x) \
+ (((x) & BIT_MASK_SDIO_INT_TIMEOUT) << BIT_SHIFT_SDIO_INT_TIMEOUT)
+#define BITS_SDIO_INT_TIMEOUT \
+ (BIT_MASK_SDIO_INT_TIMEOUT << BIT_SHIFT_SDIO_INT_TIMEOUT)
+#define BIT_CLEAR_SDIO_INT_TIMEOUT(x) ((x) & (~BITS_SDIO_INT_TIMEOUT))
+#define BIT_GET_SDIO_INT_TIMEOUT(x) \
+ (((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT) & BIT_MASK_SDIO_INT_TIMEOUT)
+#define BIT_SET_SDIO_INT_TIMEOUT(x, v) \
+ (BIT_CLEAR_SDIO_INT_TIMEOUT(x) | BIT_SDIO_INT_TIMEOUT(v))
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
-#define BIT_ISO_RFDIO BIT(9)
+#define BIT_PWC_EV12V BIT(15)
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
+#define BIT_PWC_EBCOEB BIT(15)
-/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */
+#endif
-#define BIT_REPLY_ERRCRC_IN_DATA BIT(9)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */
+#define BIT_IO_ERR_STATUS BIT(15)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
-#define BIT_ISO_EB2CORE BIT(8)
+#define BIT_PWC_EV25V BIT(14)
#endif
-
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */
-#define BIT_EN_CMD53_OVERLAP BIT(8)
+#define BIT_CMD53_W_MIX BIT(14)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
-#define BIT_ISO_DIOE BIT(7)
+#define BIT_PA33V_EN BIT(13)
#endif
-
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */
-#define BIT_REPLY_ERR_IN_R5 BIT(7)
+#define BIT_CMD53_TX_FORMAT BIT(13)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
+#define BIT_PA12V_EN BIT(12)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
-#define BIT_ISO_DIOP BIT(6)
+#define BIT_PC_A15V BIT(12)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */
+
+#define BIT_CMD53_R_TIMEOUT_MASK BIT(12)
+
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
-#define BIT_ISO_WLPON2PP BIT(6)
+#define BIT_UA33V_EN BIT(11)
+#define BIT_UA12V_EN BIT(10)
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
+#define BIT_ISO_AFE_OUTPUT_SIGNAL BIT(10)
-/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */
+#endif
-#define BIT_R18A_EN BIT(6)
+#if (HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */
+#define BIT_SHIFT_CMD53_R_TIMEOUT_UNIT 10
+#define BIT_MASK_CMD53_R_TIMEOUT_UNIT 0x3
+#define BIT_CMD53_R_TIMEOUT_UNIT(x) \
+ (((x) & BIT_MASK_CMD53_R_TIMEOUT_UNIT) \
+ << BIT_SHIFT_CMD53_R_TIMEOUT_UNIT)
+#define BITS_CMD53_R_TIMEOUT_UNIT \
+ (BIT_MASK_CMD53_R_TIMEOUT_UNIT << BIT_SHIFT_CMD53_R_TIMEOUT_UNIT)
+#define BIT_CLEAR_CMD53_R_TIMEOUT_UNIT(x) ((x) & (~BITS_CMD53_R_TIMEOUT_UNIT))
+#define BIT_GET_CMD53_R_TIMEOUT_UNIT(x) \
+ (((x) >> BIT_SHIFT_CMD53_R_TIMEOUT_UNIT) & \
+ BIT_MASK_CMD53_R_TIMEOUT_UNIT)
+#define BIT_SET_CMD53_R_TIMEOUT_UNIT(x, v) \
+ (BIT_CLEAR_CMD53_R_TIMEOUT_UNIT(x) | BIT_CMD53_R_TIMEOUT_UNIT(v))
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
-#define BIT_ISO_IP2MAC_WA2PP BIT(5)
+#define BIT_ISO_RFDIO BIT(9)
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */
-#define BIT_INIT_CMD_EN BIT(5)
+#define BIT_REPLY_ERRCRC_IN_DATA BIT(9)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
-#define BIT_ISO_PD2CORE BIT(4)
+#define BIT_ISO_EB2CORE BIT(8)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */
+#define BIT_EN_CMD53_OVERLAP BIT(8)
-/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
+#endif
-#define BIT_ISO_PA2PCIE BIT(3)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
+#define BIT_ISO_DIOE BIT(7)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */
-#define BIT_EN_32K_TRANS BIT(3)
+#define BIT_REPLY_ERR_IN_R5 BIT(7)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
+
+#define BIT_ISO_DIOP BIT(6)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
-#define BIT_ISO_UD2CORE BIT(2)
+#define BIT_ISO_WLPON2PP BIT(6)
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */
+#define BIT_R18A_EN BIT(6)
-/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_EN_RXDMA_MASK_INT BIT(2)
+/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
+
+#define BIT_ISO_IP2MAC_WA2PP BIT(5)
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */
+#define BIT_SDIO_CMD_FORCE_VLD BIT(5)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
-#define BIT_ISO_HD2CORE BIT(2)
+#define BIT_ISO_PD2CORE BIT(4)
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */
+
+#define BIT_INIT_CMD_EN BIT(4)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
-#define BIT_ISO_UA2USB BIT(1)
+#define BIT_ISO_PA2PCIE BIT(3)
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */
+
+#define BIT_EN_32K_TRANS BIT(3)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */
-#define BIT_EN_MASK_TIMER BIT(1)
+#define BIT_RXINT_READ_MASK_DIS BIT(3)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
+
+#define BIT_ISO_UD2CORE BIT(2)
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */
+
+#define BIT_EN_RXDMA_MASK_INT BIT(2)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
-#define BIT_ISO_WD2PP BIT(0)
+#define BIT_ISO_HD2CORE BIT(2)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
+
+#define BIT_ISO_UA2USB BIT(1)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */
-#define BIT_CMD_ERR_STOP_INT_EN BIT(0)
+#define BIT_EN_MASK_TIMER BIT(1)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */
+#define BIT_ISO_WD2PP BIT(0)
-/* 2 REG_SYS_FUNC_EN (Offset 0x0002) */
+#endif
-#define BIT_FEN_MREGEN BIT(15)
-#define BIT_FEN_HWPDN BIT(14)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */
+#define BIT_CMD_ERR_STOP_INT_EN BIT(0)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_FUNC_EN (Offset 0x0002) */
-#define BIT_EN_25_1 BIT(13)
+#define BIT_FEN_MREGEN BIT(15)
+#define BIT_FEN_HWPDN BIT(14)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_FUNC_EN (Offset 0x0002) */
-#define BIT_FEN_ELDR BIT(12)
-#define BIT_FEN_DCORE BIT(11)
-#define BIT_FEN_CPUEN BIT(10)
-#define BIT_FEN_DIOE BIT(9)
-#define BIT_FEN_PCIED BIT(8)
-#define BIT_FEN_PPLL BIT(7)
-#define BIT_FEN_PCIEA BIT(6)
-#define BIT_FEN_DIO_PCIE BIT(5)
-#define BIT_FEN_USBD BIT(4)
-#define BIT_FEN_UPLL BIT(3)
-#define BIT_FEN_USBA BIT(2)
+#define BIT_EN_25_1 BIT(13)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SYS_FUNC_EN (Offset 0x0002) */
+
+#define BIT_FEN_ELDR BIT(12)
+#define BIT_FEN_DCORE BIT(11)
+#define BIT_FEN_CPUEN BIT(10)
+#define BIT_FEN_DIOE BIT(9)
+#define BIT_FEN_PCIED BIT(8)
+#define BIT_FEN_PPLL BIT(7)
+#define BIT_FEN_PCIEA BIT(6)
+#define BIT_FEN_DIO_PCIE BIT(5)
+#define BIT_FEN_USBD BIT(4)
+#define BIT_FEN_UPLL BIT(3)
+#define BIT_FEN_USBA BIT(2)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_FUNC_EN (Offset 0x0002) */
-#define BIT_FEN_BB_GLB_RSTN BIT(1)
-#define BIT_FEN_BBRSTB BIT(0)
+#define BIT_FEN_BB_GLB_RSTN BIT(1)
+#define BIT_FEN_BBRSTB BIT(0)
/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-#define BIT_SOP_EABM BIT(31)
+#define BIT_SOP_EABM BIT(31)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-#define BIT_SKP_ALD BIT(31)
+#define BIT_SKP_ALD BIT(31)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-#define BIT_SOP_ACKF BIT(30)
-#define BIT_SOP_ERCK BIT(29)
+#define BIT_SOP_ACKF BIT(30)
+#define BIT_SOP_ERCK BIT(29)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-#define BIT_SOP_ESWR BIT(28)
+#define BIT_SOP_ESWR BIT(28)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-#define BIT_SOP_AFEP BIT(28)
+#define BIT_SOP_AFEP BIT(28)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-#define BIT_SOP_PWMM BIT(27)
+#define BIT_SOP_PWMM BIT(27)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-#define BIT_SOP_EPWM BIT(27)
+#define BIT_SOP_EPWM BIT(27)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-#define BIT_SOP_EECK BIT(26)
+#define BIT_SOP_EECK BIT(26)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-#define BIT_ROP_ENXT BIT(25)
+#define BIT_ROP_ENXT BIT(25)
#endif
+#if (HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
+
+#define BIT_SOP_ANA_CLK_DIVISION_2 BIT(25)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-#define BIT_SOP_EXTL BIT(24)
+#define BIT_SOP_EXTL BIT(24)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-#define BIT_CHIPOFF_EN BIT(23)
+#define BIT_CHIPOFF_EN BIT(23)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-#define BIT_SYM_OP_RING_12M BIT(22)
+#define BIT_SYM_OP_RING_12M BIT(22)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-#define BIT_DIS_USB3_SUS_ALD BIT(22)
+#define BIT_DIS_USB3_SUS_ALD BIT(22)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-#define BIT_ROP_SWPR BIT(21)
+#define BIT_ROP_SWPR BIT(21)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-#define BIT_DIS_HW_LPLDM BIT(20)
+#define BIT_DIS_HW_LPLDM BIT(20)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-#define BIT_SOP_ALD BIT(20)
+#define BIT_SOP_ALD BIT(20)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-#define BIT_OPT_SWRST_WLMCU BIT(19)
-#define BIT_RDY_SYSPWR BIT(17)
+#define BIT_OPT_SWRST_WLMCU BIT(19)
+#define BIT_RDY_SYSPWR BIT(17)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-#define BIT_EN_WLON BIT(16)
+#define BIT_EN_WLON BIT(16)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-#define BIT_APDM_HPDN BIT(15)
+#define BIT_APDM_HPDN BIT(15)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-#define BIT_HSUS BIT(14)
-#define BIT_PDN_SEL BIT(13)
+#define BIT_HSUS BIT(14)
+#define BIT_PDN_SEL BIT(13)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-#define BIT_AFSM_PCIE_SUS_EN BIT(12)
+#define BIT_AFSM_PCIE_SUS_EN BIT(12)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-#define BIT_AFSM_WLSUS_EN BIT(11)
+#define BIT_AFSM_WLSUS_EN BIT(11)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-#define BIT_APFM_SWLPS BIT(10)
+#define BIT_APFM_SWLPS BIT(10)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-#define BIT_APFM_SWLPS_EN BIT(10)
+#define BIT_APFM_SWLPS_EN BIT(10)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-#define BIT_APFM_OFFMAC BIT(9)
-#define BIT_APFN_ONMAC BIT(8)
+#define BIT_APFM_OFFMAC BIT(9)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8822C_SUPPORT)
/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-#define BIT_CHIP_PDN_EN BIT(7)
+#define BIT_HW_AUTO_CTRL_EXT_SWR BIT(9)
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-#define BIT_BT_SUSEN BIT(7)
+#define BIT_APFN_ONMAC BIT(8)
#endif
+#if (HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
+
+#define BIT_USE_INTERNAL_SWR_AND_LDO BIT(8)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-#define BIT_RDY_MACDIS BIT(6)
+#define BIT_CHIP_PDN_EN BIT(7)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-#define BIT_PD_RF BIT(5)
+#define BIT_BT_SUSEN BIT(7)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-#define BIT_RING_CLK_12M_EN BIT(4)
+#define BIT_RDY_MACDIS BIT(6)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-#define BIT_ENPDN BIT(4)
+#define BIT_PD_RF BIT(5)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-#define BIT_PFM_WOWL BIT(3)
+#define BIT_RING_CLK_12M_EN BIT(4)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-#define BIT_SW_WAKE BIT(3)
+#define BIT_ENPDN BIT(4)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_SDIO_CMD11_VOL_SWITCH (Offset 0x10250004) */
-
-/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-
-#define BIT_PFM_LDKP BIT(2)
+#define BIT_SHIFT_CMD11_SEQ_END_DELAY 4
+#define BIT_MASK_CMD11_SEQ_END_DELAY 0xf
+#define BIT_CMD11_SEQ_END_DELAY(x) \
+ (((x) & BIT_MASK_CMD11_SEQ_END_DELAY) << BIT_SHIFT_CMD11_SEQ_END_DELAY)
+#define BITS_CMD11_SEQ_END_DELAY \
+ (BIT_MASK_CMD11_SEQ_END_DELAY << BIT_SHIFT_CMD11_SEQ_END_DELAY)
+#define BIT_CLEAR_CMD11_SEQ_END_DELAY(x) ((x) & (~BITS_CMD11_SEQ_END_DELAY))
+#define BIT_GET_CMD11_SEQ_END_DELAY(x) \
+ (((x) >> BIT_SHIFT_CMD11_SEQ_END_DELAY) & BIT_MASK_CMD11_SEQ_END_DELAY)
+#define BIT_SET_CMD11_SEQ_END_DELAY(x, v) \
+ (BIT_CLEAR_CMD11_SEQ_END_DELAY(x) | BIT_CMD11_SEQ_END_DELAY(v))
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-#define BIT_WL_HCI_ALD BIT(1)
+#define BIT_PFM_WOWL BIT(3)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-#define BIT_PFM_ALDN BIT(1)
+#define BIT_SW_WAKE BIT(3)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-#define BIT_PFM_LDALL BIT(0)
+#define BIT_PFM_LDKP BIT(2)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-
-/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
+/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-#define BIT_LDO_DUMMY BIT(15)
+#define BIT_WL_HCI_ALD BIT(1)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
-
-#define BIT_ANA_CLK_EN BIT(15)
+#define BIT_PFM_ALDN BIT(1)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
-/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
+#define BIT_ANA_CLK_DIVISION_2 BIT(1)
-#define BIT_CPU_CLK_EN BIT(14)
+#define BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL 1
+#define BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL 0x7
+#define BIT_CMD11_SEQ_SAMPLE_INTERVAL(x) \
+ (((x) & BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL) \
+ << BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL)
+#define BITS_CMD11_SEQ_SAMPLE_INTERVAL \
+ (BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL \
+ << BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL)
+#define BIT_CLEAR_CMD11_SEQ_SAMPLE_INTERVAL(x) \
+ ((x) & (~BITS_CMD11_SEQ_SAMPLE_INTERVAL))
+#define BIT_GET_CMD11_SEQ_SAMPLE_INTERVAL(x) \
+ (((x) >> BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL) & \
+ BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL)
+#define BIT_SET_CMD11_SEQ_SAMPLE_INTERVAL(x, v) \
+ (BIT_CLEAR_CMD11_SEQ_SAMPLE_INTERVAL(x) | \
+ BIT_CMD11_SEQ_SAMPLE_INTERVAL(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_SYS_PW_CTRL (Offset 0x0004) */
+#define BIT_PFM_LDALL BIT(0)
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_CMD11_VOL_SWITCH (Offset 0x10250004) */
+
+#define BIT_CMD11_SEQ_EN BIT(0)
+
+/* 2 REG_SDIO_DRIVING (Offset 0x10250006) */
+
+#define BIT_SHIFT_SDIO_DRV_TYPE_D 12
+#define BIT_MASK_SDIO_DRV_TYPE_D 0xf
+#define BIT_SDIO_DRV_TYPE_D(x) \
+ (((x) & BIT_MASK_SDIO_DRV_TYPE_D) << BIT_SHIFT_SDIO_DRV_TYPE_D)
+#define BITS_SDIO_DRV_TYPE_D \
+ (BIT_MASK_SDIO_DRV_TYPE_D << BIT_SHIFT_SDIO_DRV_TYPE_D)
+#define BIT_CLEAR_SDIO_DRV_TYPE_D(x) ((x) & (~BITS_SDIO_DRV_TYPE_D))
+#define BIT_GET_SDIO_DRV_TYPE_D(x) \
+ (((x) >> BIT_SHIFT_SDIO_DRV_TYPE_D) & BIT_MASK_SDIO_DRV_TYPE_D)
+#define BIT_SET_SDIO_DRV_TYPE_D(x, v) \
+ (BIT_CLEAR_SDIO_DRV_TYPE_D(x) | BIT_SDIO_DRV_TYPE_D(v))
+
+#define BIT_SHIFT_SDIO_DRV_TYPE_C 8
+#define BIT_MASK_SDIO_DRV_TYPE_C 0xf
+#define BIT_SDIO_DRV_TYPE_C(x) \
+ (((x) & BIT_MASK_SDIO_DRV_TYPE_C) << BIT_SHIFT_SDIO_DRV_TYPE_C)
+#define BITS_SDIO_DRV_TYPE_C \
+ (BIT_MASK_SDIO_DRV_TYPE_C << BIT_SHIFT_SDIO_DRV_TYPE_C)
+#define BIT_CLEAR_SDIO_DRV_TYPE_C(x) ((x) & (~BITS_SDIO_DRV_TYPE_C))
+#define BIT_GET_SDIO_DRV_TYPE_C(x) \
+ (((x) >> BIT_SHIFT_SDIO_DRV_TYPE_C) & BIT_MASK_SDIO_DRV_TYPE_C)
+#define BIT_SET_SDIO_DRV_TYPE_C(x, v) \
+ (BIT_CLEAR_SDIO_DRV_TYPE_C(x) | BIT_SDIO_DRV_TYPE_C(v))
+
+#define BIT_SHIFT_SDIO_DRV_TYPE_B 4
+#define BIT_MASK_SDIO_DRV_TYPE_B 0xf
+#define BIT_SDIO_DRV_TYPE_B(x) \
+ (((x) & BIT_MASK_SDIO_DRV_TYPE_B) << BIT_SHIFT_SDIO_DRV_TYPE_B)
+#define BITS_SDIO_DRV_TYPE_B \
+ (BIT_MASK_SDIO_DRV_TYPE_B << BIT_SHIFT_SDIO_DRV_TYPE_B)
+#define BIT_CLEAR_SDIO_DRV_TYPE_B(x) ((x) & (~BITS_SDIO_DRV_TYPE_B))
+#define BIT_GET_SDIO_DRV_TYPE_B(x) \
+ (((x) >> BIT_SHIFT_SDIO_DRV_TYPE_B) & BIT_MASK_SDIO_DRV_TYPE_B)
+#define BIT_SET_SDIO_DRV_TYPE_B(x, v) \
+ (BIT_CLEAR_SDIO_DRV_TYPE_B(x) | BIT_SDIO_DRV_TYPE_B(v))
+
+#define BIT_SHIFT_SDIO_DRV_TYPE_A 0
+#define BIT_MASK_SDIO_DRV_TYPE_A 0xf
+#define BIT_SDIO_DRV_TYPE_A(x) \
+ (((x) & BIT_MASK_SDIO_DRV_TYPE_A) << BIT_SHIFT_SDIO_DRV_TYPE_A)
+#define BITS_SDIO_DRV_TYPE_A \
+ (BIT_MASK_SDIO_DRV_TYPE_A << BIT_SHIFT_SDIO_DRV_TYPE_A)
+#define BIT_CLEAR_SDIO_DRV_TYPE_A(x) ((x) & (~BITS_SDIO_DRV_TYPE_A))
+#define BIT_GET_SDIO_DRV_TYPE_A(x) \
+ (((x) >> BIT_SHIFT_SDIO_DRV_TYPE_A) & BIT_MASK_SDIO_DRV_TYPE_A)
+#define BIT_SET_SDIO_DRV_TYPE_A(x, v) \
+ (BIT_CLEAR_SDIO_DRV_TYPE_A(x) | BIT_SDIO_DRV_TYPE_A(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
-#define BIT_SYMREG_CLK_EN BIT(13)
+#define BIT_CPHY_LDO_CL_EN BIT(19)
+#define BIT_CPHY_LDO_OK BIT(18)
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
-#define BIT_RING_CLK_EN BIT(13)
+#define BIT_LDO_DUMMY BIT(15)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
-#define BIT_HCI_CLK_EN BIT(12)
+#define BIT_ANA_CLK_EN BIT(15)
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
-#define BIT_SYS_CLK_EN BIT(12)
+#define BIT_DATA_CPU_CLK_EN BIT(15)
+#define BIT_DATA_CPU_PWC BIT(15)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
-#define BIT_MAC_CLK_EN BIT(11)
-#define BIT_SEC_CLK_EN BIT(10)
+#define BIT_CPU_CLK_EN BIT(14)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
-#define BIT_PHY_SSC_RSTB BIT(9)
-#define BIT_EXT_32K_EN BIT(8)
+#define BIT_SYMREG_CLK_EN BIT(13)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
-#define BIT_EXT32K_EN BIT(8)
+#define BIT_RING_CLK_EN BIT(13)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
-#define BIT_WL_CLK_TEST BIT(7)
-#define BIT_OP_SPS_PWM_EN BIT(6)
+#define BIT_HCI_CLK_EN BIT(12)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
+#define BIT_SYS_CLK_EN BIT(12)
-#define BIT_SHIFT_MAC_CLK_SEL_V1 6
-#define BIT_MASK_MAC_CLK_SEL_V1 0x3
-#define BIT_MAC_CLK_SEL_V1(x) (((x) & BIT_MASK_MAC_CLK_SEL_V1) << BIT_SHIFT_MAC_CLK_SEL_V1)
-#define BIT_GET_MAC_CLK_SEL_V1(x) (((x) >> BIT_SHIFT_MAC_CLK_SEL_V1) & BIT_MASK_MAC_CLK_SEL_V1)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
+#define BIT_MAC_CLK_EN BIT(11)
+#define BIT_SEC_CLK_EN BIT(10)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
-#define BIT_LOADER_CLK_EN BIT(5)
-#define BIT_MACSLP BIT(4)
-#define BIT_WAKEPAD_EN BIT(3)
-#define BIT_ROMD16V_EN BIT(2)
+#define BIT_CTRL_SPS_PWM_FREQ BIT(10)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
-#define BIT_CKANA8M_EN BIT(1)
+#define BIT_PHY_SSC_RSTB BIT(9)
+#define BIT_EXT_32K_EN BIT(8)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
-#define BIT_CKANA12M_EN BIT(1)
+#define BIT_EXT32K_EN BIT(8)
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
-#define BIT_ANA8M_EN BIT(1)
+#define BIT_DISABLE_OPEN_SPS_LDO BIT(8)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
-#define BIT_CNTD16V_EN BIT(0)
+#define BIT_WL_CLK_TEST BIT(7)
+#define BIT_OP_SPS_PWM_EN BIT(6)
-/* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define BIT_SHIFT_VPDIDX 8
-#define BIT_MASK_VPDIDX 0xff
-#define BIT_VPDIDX(x) (((x) & BIT_MASK_VPDIDX) << BIT_SHIFT_VPDIDX)
-#define BIT_GET_VPDIDX(x) (((x) >> BIT_SHIFT_VPDIDX) & BIT_MASK_VPDIDX)
+/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
+#define BIT_SHIFT_MAC_CLK_SEL_V1 6
+#define BIT_MASK_MAC_CLK_SEL_V1 0x3
+#define BIT_MAC_CLK_SEL_V1(x) \
+ (((x) & BIT_MASK_MAC_CLK_SEL_V1) << BIT_SHIFT_MAC_CLK_SEL_V1)
+#define BITS_MAC_CLK_SEL_V1 \
+ (BIT_MASK_MAC_CLK_SEL_V1 << BIT_SHIFT_MAC_CLK_SEL_V1)
+#define BIT_CLEAR_MAC_CLK_SEL_V1(x) ((x) & (~BITS_MAC_CLK_SEL_V1))
+#define BIT_GET_MAC_CLK_SEL_V1(x) \
+ (((x) >> BIT_SHIFT_MAC_CLK_SEL_V1) & BIT_MASK_MAC_CLK_SEL_V1)
+#define BIT_SET_MAC_CLK_SEL_V1(x, v) \
+ (BIT_CLEAR_MAC_CLK_SEL_V1(x) | BIT_MAC_CLK_SEL_V1(v))
-#define BIT_SHIFT_EEM1_0 6
-#define BIT_MASK_EEM1_0 0x3
-#define BIT_EEM1_0(x) (((x) & BIT_MASK_EEM1_0) << BIT_SHIFT_EEM1_0)
-#define BIT_GET_EEM1_0(x) (((x) >> BIT_SHIFT_EEM1_0) & BIT_MASK_EEM1_0)
+#endif
-#define BIT_AUTOLOAD_SUS BIT(5)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
+#define BIT_LOADER_CLK_EN BIT(5)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */
+/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
-#define BIT_EERPOMSEL BIT(4)
+#define BIT_POW_PC_LDO3 BIT(5)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
+#define BIT_MACSLP BIT(4)
-/* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */
+#endif
-#define BIT_EEPROMSEL BIT(4)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
+#define BIT_POW_PC_LDO2 BIT(4)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-/* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */
+/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
-#define BIT_EECS_V1 BIT(3)
-#define BIT_EESK_V1 BIT(2)
-#define BIT_EEDI_V1 BIT(1)
-#define BIT_EEDO_V1 BIT(0)
+#define BIT_WAKEPAD_EN BIT(3)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
+#define BIT_ENB_LDO_DIODE_L BIT(3)
+#define BIT_POW_PC_LDO1 BIT(3)
-/* 2 REG_EE_VPD (Offset 0x000C) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_VPD_DATA 0
-#define BIT_MASK_VPD_DATA 0xffffffffL
-#define BIT_VPD_DATA(x) (((x) & BIT_MASK_VPD_DATA) << BIT_SHIFT_VPD_DATA)
-#define BIT_GET_VPD_DATA(x) (((x) >> BIT_SHIFT_VPD_DATA) & BIT_MASK_VPD_DATA)
+/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
+#define BIT_ROMD16V_EN BIT(2)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
+#define BIT_AFE_BGEN_PCIE_OP BIT(2)
+#define BIT_POW_PC_LDO0 BIT(2)
-/* 2 REG_EE_VPD (Offset 0x000C) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_VDP_DATA 0
-#define BIT_MASK_VDP_DATA 0xffffffffL
-#define BIT_VDP_DATA(x) (((x) & BIT_MASK_VDP_DATA) << BIT_SHIFT_VDP_DATA)
-#define BIT_GET_VDP_DATA(x) (((x) >> BIT_SHIFT_VDP_DATA) & BIT_MASK_VDP_DATA)
+/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
+#define BIT_CKANA8M_EN BIT(1)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
+#define BIT_CKANA12M_EN BIT(1)
-/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
+#endif
-#define BIT_SW18_C2_BIT0 BIT(31)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#endif
+/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
+#define BIT_ANA8M_EN BIT(1)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
+/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
-#define BIT_C2_L_BIT0 BIT(31)
+#define BIT_CNTD16V_EN BIT(0)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */
+#define BIT_POW_POWER_CUT BIT(0)
-/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
+#endif
+#if (HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_R1_L1_V1 30
-#define BIT_MASK_R1_L1_V1 0x3
-#define BIT_R1_L1_V1(x) (((x) & BIT_MASK_R1_L1_V1) << BIT_SHIFT_R1_L1_V1)
-#define BIT_GET_R1_L1_V1(x) (((x) >> BIT_SHIFT_R1_L1_V1) & BIT_MASK_R1_L1_V1)
+/* 2 REG_SDIO_MONITOR (Offset 0x10250008) */
+#define BIT_SHIFT_SDIO_INT_START 0
+#define BIT_MASK_SDIO_INT_START 0xffffffffL
+#define BIT_SDIO_INT_START(x) \
+ (((x) & BIT_MASK_SDIO_INT_START) << BIT_SHIFT_SDIO_INT_START)
+#define BITS_SDIO_INT_START \
+ (BIT_MASK_SDIO_INT_START << BIT_SHIFT_SDIO_INT_START)
+#define BIT_CLEAR_SDIO_INT_START(x) ((x) & (~BITS_SDIO_INT_START))
+#define BIT_GET_SDIO_INT_START(x) \
+ (((x) >> BIT_SHIFT_SDIO_INT_START) & BIT_MASK_SDIO_INT_START)
+#define BIT_SET_SDIO_INT_START(x, v) \
+ (BIT_CLEAR_SDIO_INT_START(x) | BIT_SDIO_INT_START(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT)
-
-
-/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
+/* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */
+#define BIT_SHIFT_VPDIDX 8
+#define BIT_MASK_VPDIDX 0xff
+#define BIT_VPDIDX(x) (((x) & BIT_MASK_VPDIDX) << BIT_SHIFT_VPDIDX)
+#define BITS_VPDIDX (BIT_MASK_VPDIDX << BIT_SHIFT_VPDIDX)
+#define BIT_CLEAR_VPDIDX(x) ((x) & (~BITS_VPDIDX))
+#define BIT_GET_VPDIDX(x) (((x) >> BIT_SHIFT_VPDIDX) & BIT_MASK_VPDIDX)
+#define BIT_SET_VPDIDX(x, v) (BIT_CLEAR_VPDIDX(x) | BIT_VPDIDX(v))
-#define BIT_SHIFT_SW18_C1 29
-#define BIT_MASK_SW18_C1 0x3
-#define BIT_SW18_C1(x) (((x) & BIT_MASK_SW18_C1) << BIT_SHIFT_SW18_C1)
-#define BIT_GET_SW18_C1(x) (((x) >> BIT_SHIFT_SW18_C1) & BIT_MASK_SW18_C1)
+#define BIT_SHIFT_EEM1_0 6
+#define BIT_MASK_EEM1_0 0x3
+#define BIT_EEM1_0(x) (((x) & BIT_MASK_EEM1_0) << BIT_SHIFT_EEM1_0)
+#define BITS_EEM1_0 (BIT_MASK_EEM1_0 << BIT_SHIFT_EEM1_0)
+#define BIT_CLEAR_EEM1_0(x) ((x) & (~BITS_EEM1_0))
+#define BIT_GET_EEM1_0(x) (((x) >> BIT_SHIFT_EEM1_0) & BIT_MASK_EEM1_0)
+#define BIT_SET_EEM1_0(x, v) (BIT_CLEAR_EEM1_0(x) | BIT_EEM1_0(v))
+#define BIT_AUTOLOAD_SUS BIT(5)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */
+#define BIT_EERPOMSEL BIT(4)
-/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define BIT_SHIFT_C1_L 29
-#define BIT_MASK_C1_L 0x3
-#define BIT_C1_L(x) (((x) & BIT_MASK_C1_L) << BIT_SHIFT_C1_L)
-#define BIT_GET_C1_L(x) (((x) >> BIT_SHIFT_C1_L) & BIT_MASK_C1_L)
+/* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */
+#define BIT_EEPROMSEL BIT(4)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
+/* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */
-/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
+#define BIT_EECS_V1 BIT(3)
+#define BIT_EESK_V1 BIT(2)
+#define BIT_EEDI_V1 BIT(1)
+#define BIT_EEDO_V1 BIT(0)
+#endif
-#define BIT_SHIFT_C3_L1_V1 28
-#define BIT_MASK_C3_L1_V1 0x3
-#define BIT_C3_L1_V1(x) (((x) & BIT_MASK_C3_L1_V1) << BIT_SHIFT_C3_L1_V1)
-#define BIT_GET_C3_L1_V1(x) (((x) >> BIT_SHIFT_C3_L1_V1) & BIT_MASK_C3_L1_V1)
+#if (HALMAC_8822C_SUPPORT)
+/* 2 REG_SDIO_MONITOR_2 (Offset 0x1025000C) */
-#define BIT_SHIFT_C2_L1_V1 26
-#define BIT_MASK_C2_L1_V1 0x3
-#define BIT_C2_L1_V1(x) (((x) & BIT_MASK_C2_L1_V1) << BIT_SHIFT_C2_L1_V1)
-#define BIT_GET_C2_L1_V1(x) (((x) >> BIT_SHIFT_C2_L1_V1) & BIT_MASK_C2_L1_V1)
+#define BIT_CMD53_WT_EN BIT(23)
+#define BIT_SHIFT_SDIO_CLK_MONITOR 21
+#define BIT_MASK_SDIO_CLK_MONITOR 0x3
+#define BIT_SDIO_CLK_MONITOR(x) \
+ (((x) & BIT_MASK_SDIO_CLK_MONITOR) << BIT_SHIFT_SDIO_CLK_MONITOR)
+#define BITS_SDIO_CLK_MONITOR \
+ (BIT_MASK_SDIO_CLK_MONITOR << BIT_SHIFT_SDIO_CLK_MONITOR)
+#define BIT_CLEAR_SDIO_CLK_MONITOR(x) ((x) & (~BITS_SDIO_CLK_MONITOR))
+#define BIT_GET_SDIO_CLK_MONITOR(x) \
+ (((x) >> BIT_SHIFT_SDIO_CLK_MONITOR) & BIT_MASK_SDIO_CLK_MONITOR)
+#define BIT_SET_SDIO_CLK_MONITOR(x, v) \
+ (BIT_CLEAR_SDIO_CLK_MONITOR(x) | BIT_SDIO_CLK_MONITOR(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_EE_VPD (Offset 0x000C) */
+#define BIT_SHIFT_VPD_DATA 0
+#define BIT_MASK_VPD_DATA 0xffffffffL
+#define BIT_VPD_DATA(x) (((x) & BIT_MASK_VPD_DATA) << BIT_SHIFT_VPD_DATA)
+#define BITS_VPD_DATA (BIT_MASK_VPD_DATA << BIT_SHIFT_VPD_DATA)
+#define BIT_CLEAR_VPD_DATA(x) ((x) & (~BITS_VPD_DATA))
+#define BIT_GET_VPD_DATA(x) (((x) >> BIT_SHIFT_VPD_DATA) & BIT_MASK_VPD_DATA)
+#define BIT_SET_VPD_DATA(x, v) (BIT_CLEAR_VPD_DATA(x) | BIT_VPD_DATA(v))
-/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define BIT_SHIFT_REG_FREQ_L 25
-#define BIT_MASK_REG_FREQ_L 0x7
-#define BIT_REG_FREQ_L(x) (((x) & BIT_MASK_REG_FREQ_L) << BIT_SHIFT_REG_FREQ_L)
-#define BIT_GET_REG_FREQ_L(x) (((x) >> BIT_SHIFT_REG_FREQ_L) & BIT_MASK_REG_FREQ_L)
+/* 2 REG_EE_VPD (Offset 0x000C) */
-#define BIT_REG_EN_DUTY BIT(24)
+#define BIT_SHIFT_VDP_DATA 0
+#define BIT_MASK_VDP_DATA 0xffffffffL
+#define BIT_VDP_DATA(x) (((x) & BIT_MASK_VDP_DATA) << BIT_SHIFT_VDP_DATA)
+#define BITS_VDP_DATA (BIT_MASK_VDP_DATA << BIT_SHIFT_VDP_DATA)
+#define BIT_CLEAR_VDP_DATA(x) ((x) & (~BITS_VDP_DATA))
+#define BIT_GET_VDP_DATA(x) (((x) >> BIT_SHIFT_VDP_DATA) & BIT_MASK_VDP_DATA)
+#define BIT_SET_VDP_DATA(x, v) (BIT_CLEAR_VDP_DATA(x) | BIT_VDP_DATA(v))
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_SDIO_MONITOR_2 (Offset 0x1025000C) */
+#define BIT_SHIFT_SDIO_CLK_CNT 0
+#define BIT_MASK_SDIO_CLK_CNT 0x1fffff
+#define BIT_SDIO_CLK_CNT(x) \
+ (((x) & BIT_MASK_SDIO_CLK_CNT) << BIT_SHIFT_SDIO_CLK_CNT)
+#define BITS_SDIO_CLK_CNT (BIT_MASK_SDIO_CLK_CNT << BIT_SHIFT_SDIO_CLK_CNT)
+#define BIT_CLEAR_SDIO_CLK_CNT(x) ((x) & (~BITS_SDIO_CLK_CNT))
+#define BIT_GET_SDIO_CLK_CNT(x) \
+ (((x) >> BIT_SHIFT_SDIO_CLK_CNT) & BIT_MASK_SDIO_CLK_CNT)
+#define BIT_SET_SDIO_CLK_CNT(x, v) \
+ (BIT_CLEAR_SDIO_CLK_CNT(x) | BIT_SDIO_CLK_CNT(v))
-/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_C1_L1_V1 24
-#define BIT_MASK_C1_L1_V1 0x3
-#define BIT_C1_L1_V1(x) (((x) & BIT_MASK_C1_L1_V1) << BIT_SHIFT_C1_L1_V1)
-#define BIT_GET_C1_L1_V1(x) (((x) >> BIT_SHIFT_C1_L1_V1) & BIT_MASK_C1_L1_V1)
+/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
-#define BIT_REG_TYPE_L_V3 BIT(23)
+#define BIT_SW18_C2_BIT0 BIT(31)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
-
-#define BIT_SHIFT_REG_MODE 22
-#define BIT_MASK_REG_MODE 0x3
-#define BIT_REG_MODE(x) (((x) & BIT_MASK_REG_MODE) << BIT_SHIFT_REG_MODE)
-#define BIT_GET_REG_MODE(x) (((x) >> BIT_SHIFT_REG_MODE) & BIT_MASK_REG_MODE)
-
+#define BIT_C2_L_BIT0 BIT(31)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
-#define BIT_FPWM_L1_V1 BIT(22)
+#define BIT_SHIFT_R1_L1_V1 30
+#define BIT_MASK_R1_L1_V1 0x3
+#define BIT_R1_L1_V1(x) (((x) & BIT_MASK_R1_L1_V1) << BIT_SHIFT_R1_L1_V1)
+#define BITS_R1_L1_V1 (BIT_MASK_R1_L1_V1 << BIT_SHIFT_R1_L1_V1)
+#define BIT_CLEAR_R1_L1_V1(x) ((x) & (~BITS_R1_L1_V1))
+#define BIT_GET_R1_L1_V1(x) (((x) >> BIT_SHIFT_R1_L1_V1) & BIT_MASK_R1_L1_V1)
+#define BIT_SET_R1_L1_V1(x, v) (BIT_CLEAR_R1_L1_V1(x) | BIT_R1_L1_V1(v))
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
-#define BIT_REG_EN_SP BIT(21)
-#define BIT_REG_AUTO_L BIT(20)
+#define BIT_SHIFT_SW18_C1 29
+#define BIT_MASK_SW18_C1 0x3
+#define BIT_SW18_C1(x) (((x) & BIT_MASK_SW18_C1) << BIT_SHIFT_SW18_C1)
+#define BITS_SW18_C1 (BIT_MASK_SW18_C1 << BIT_SHIFT_SW18_C1)
+#define BIT_CLEAR_SW18_C1(x) ((x) & (~BITS_SW18_C1))
+#define BIT_GET_SW18_C1(x) (((x) >> BIT_SHIFT_SW18_C1) & BIT_MASK_SW18_C1)
+#define BIT_SET_SW18_C1(x, v) (BIT_CLEAR_SW18_C1(x) | BIT_SW18_C1(v))
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
-#define BIT_SW18_SELD_BIT0 BIT(19)
+#define BIT_SHIFT_C1_L 29
+#define BIT_MASK_C1_L 0x3
+#define BIT_C1_L(x) (((x) & BIT_MASK_C1_L) << BIT_SHIFT_C1_L)
+#define BITS_C1_L (BIT_MASK_C1_L << BIT_SHIFT_C1_L)
+#define BIT_CLEAR_C1_L(x) ((x) & (~BITS_C1_L))
+#define BIT_GET_C1_L(x) (((x) >> BIT_SHIFT_C1_L) & BIT_MASK_C1_L)
+#define BIT_SET_C1_L(x, v) (BIT_CLEAR_C1_L(x) | BIT_C1_L(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
+#define BIT_SHIFT_C3_L1_V1 28
+#define BIT_MASK_C3_L1_V1 0x3
+#define BIT_C3_L1_V1(x) (((x) & BIT_MASK_C3_L1_V1) << BIT_SHIFT_C3_L1_V1)
+#define BITS_C3_L1_V1 (BIT_MASK_C3_L1_V1 << BIT_SHIFT_C3_L1_V1)
+#define BIT_CLEAR_C3_L1_V1(x) ((x) & (~BITS_C3_L1_V1))
+#define BIT_GET_C3_L1_V1(x) (((x) >> BIT_SHIFT_C3_L1_V1) & BIT_MASK_C3_L1_V1)
+#define BIT_SET_C3_L1_V1(x, v) (BIT_CLEAR_C3_L1_V1(x) | BIT_C3_L1_V1(v))
-#define BIT_SHIFT_V15ADJ_L1 19
-#define BIT_MASK_V15ADJ_L1 0x7
-#define BIT_V15ADJ_L1(x) (((x) & BIT_MASK_V15ADJ_L1) << BIT_SHIFT_V15ADJ_L1)
-#define BIT_GET_V15ADJ_L1(x) (((x) >> BIT_SHIFT_V15ADJ_L1) & BIT_MASK_V15ADJ_L1)
-
+#define BIT_SHIFT_C2_L1_V1 26
+#define BIT_MASK_C2_L1_V1 0x3
+#define BIT_C2_L1_V1(x) (((x) & BIT_MASK_C2_L1_V1) << BIT_SHIFT_C2_L1_V1)
+#define BITS_C2_L1_V1 (BIT_MASK_C2_L1_V1 << BIT_SHIFT_C2_L1_V1)
+#define BIT_CLEAR_C2_L1_V1(x) ((x) & (~BITS_C2_L1_V1))
+#define BIT_GET_C2_L1_V1(x) (((x) >> BIT_SHIFT_C2_L1_V1) & BIT_MASK_C2_L1_V1)
+#define BIT_SET_C2_L1_V1(x, v) (BIT_CLEAR_C2_L1_V1(x) | BIT_C2_L1_V1(v))
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
-#define BIT_SW18_POWOCP BIT(18)
+#define BIT_SHIFT_REG_FREQ_L 25
+#define BIT_MASK_REG_FREQ_L 0x7
+#define BIT_REG_FREQ_L(x) (((x) & BIT_MASK_REG_FREQ_L) << BIT_SHIFT_REG_FREQ_L)
+#define BITS_REG_FREQ_L (BIT_MASK_REG_FREQ_L << BIT_SHIFT_REG_FREQ_L)
+#define BIT_CLEAR_REG_FREQ_L(x) ((x) & (~BITS_REG_FREQ_L))
+#define BIT_GET_REG_FREQ_L(x) \
+ (((x) >> BIT_SHIFT_REG_FREQ_L) & BIT_MASK_REG_FREQ_L)
+#define BIT_SET_REG_FREQ_L(x, v) (BIT_CLEAR_REG_FREQ_L(x) | BIT_REG_FREQ_L(v))
-#endif
+#define BIT_REG_EN_DUTY BIT(24)
+#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
+#define BIT_SHIFT_C1_L1_V1 24
+#define BIT_MASK_C1_L1_V1 0x3
+#define BIT_C1_L1_V1(x) (((x) & BIT_MASK_C1_L1_V1) << BIT_SHIFT_C1_L1_V1)
+#define BITS_C1_L1_V1 (BIT_MASK_C1_L1_V1 << BIT_SHIFT_C1_L1_V1)
+#define BIT_CLEAR_C1_L1_V1(x) ((x) & (~BITS_C1_L1_V1))
+#define BIT_GET_C1_L1_V1(x) (((x) >> BIT_SHIFT_C1_L1_V1) & BIT_MASK_C1_L1_V1)
+#define BIT_SET_C1_L1_V1(x, v) (BIT_CLEAR_C1_L1_V1(x) | BIT_C1_L1_V1(v))
-#define BIT_SHIFT_IN_L1 16
-#define BIT_MASK_IN_L1 0x7
-#define BIT_IN_L1(x) (((x) & BIT_MASK_IN_L1) << BIT_SHIFT_IN_L1)
-#define BIT_GET_IN_L1(x) (((x) >> BIT_SHIFT_IN_L1) & BIT_MASK_IN_L1)
-
+#define BIT_REG_TYPE_L_V3 BIT(23)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
+#define BIT_SHIFT_REG_MODE 22
+#define BIT_MASK_REG_MODE 0x3
+#define BIT_REG_MODE(x) (((x) & BIT_MASK_REG_MODE) << BIT_SHIFT_REG_MODE)
+#define BITS_REG_MODE (BIT_MASK_REG_MODE << BIT_SHIFT_REG_MODE)
+#define BIT_CLEAR_REG_MODE(x) ((x) & (~BITS_REG_MODE))
+#define BIT_GET_REG_MODE(x) (((x) >> BIT_SHIFT_REG_MODE) & BIT_MASK_REG_MODE)
+#define BIT_SET_REG_MODE(x, v) (BIT_CLEAR_REG_MODE(x) | BIT_REG_MODE(v))
-/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define BIT_SHIFT_SW18_OCP 15
-#define BIT_MASK_SW18_OCP 0x7
-#define BIT_SW18_OCP(x) (((x) & BIT_MASK_SW18_OCP) << BIT_SHIFT_SW18_OCP)
-#define BIT_GET_SW18_OCP(x) (((x) >> BIT_SHIFT_SW18_OCP) & BIT_MASK_SW18_OCP)
+/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
+#define BIT_FPWM_L1_V1 BIT(22)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
+#define BIT_REG_EN_SP BIT(21)
+#define BIT_REG_AUTO_L BIT(20)
-/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_OCP_L1 15
-#define BIT_MASK_OCP_L1 0x7
-#define BIT_OCP_L1(x) (((x) & BIT_MASK_OCP_L1) << BIT_SHIFT_OCP_L1)
-#define BIT_GET_OCP_L1(x) (((x) >> BIT_SHIFT_OCP_L1) & BIT_MASK_OCP_L1)
+/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
+#define BIT_SW18_SELD_BIT0 BIT(19)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
+#define BIT_SHIFT_V15ADJ_L1 19
+#define BIT_MASK_V15ADJ_L1 0x7
+#define BIT_V15ADJ_L1(x) (((x) & BIT_MASK_V15ADJ_L1) << BIT_SHIFT_V15ADJ_L1)
+#define BITS_V15ADJ_L1 (BIT_MASK_V15ADJ_L1 << BIT_SHIFT_V15ADJ_L1)
+#define BIT_CLEAR_V15ADJ_L1(x) ((x) & (~BITS_V15ADJ_L1))
+#define BIT_GET_V15ADJ_L1(x) (((x) >> BIT_SHIFT_V15ADJ_L1) & BIT_MASK_V15ADJ_L1)
+#define BIT_SET_V15ADJ_L1(x, v) (BIT_CLEAR_V15ADJ_L1(x) | BIT_V15ADJ_L1(v))
-#define BIT_SHIFT_STD_L1 14
-#define BIT_MASK_STD_L1 0x3
-#define BIT_STD_L1(x) (((x) & BIT_MASK_STD_L1) << BIT_SHIFT_STD_L1)
-#define BIT_GET_STD_L1(x) (((x) >> BIT_SHIFT_STD_L1) & BIT_MASK_STD_L1)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
+#define BIT_SW18_POWOCP BIT(18)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
+#define BIT_SHIFT_IN_L1 16
+#define BIT_MASK_IN_L1 0x7
+#define BIT_IN_L1(x) (((x) & BIT_MASK_IN_L1) << BIT_SHIFT_IN_L1)
+#define BITS_IN_L1 (BIT_MASK_IN_L1 << BIT_SHIFT_IN_L1)
+#define BIT_CLEAR_IN_L1(x) ((x) & (~BITS_IN_L1))
+#define BIT_GET_IN_L1(x) (((x) >> BIT_SHIFT_IN_L1) & BIT_MASK_IN_L1)
+#define BIT_SET_IN_L1(x, v) (BIT_CLEAR_IN_L1(x) | BIT_IN_L1(v))
-#define BIT_SHIFT_CF_L_BIT0_TO_1 13
-#define BIT_MASK_CF_L_BIT0_TO_1 0x3
-#define BIT_CF_L_BIT0_TO_1(x) (((x) & BIT_MASK_CF_L_BIT0_TO_1) << BIT_SHIFT_CF_L_BIT0_TO_1)
-#define BIT_GET_CF_L_BIT0_TO_1(x) (((x) >> BIT_SHIFT_CF_L_BIT0_TO_1) & BIT_MASK_CF_L_BIT0_TO_1)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
+#define BIT_SHIFT_SW18_OCP 15
+#define BIT_MASK_SW18_OCP 0x7
+#define BIT_SW18_OCP(x) (((x) & BIT_MASK_SW18_OCP) << BIT_SHIFT_SW18_OCP)
+#define BITS_SW18_OCP (BIT_MASK_SW18_OCP << BIT_SHIFT_SW18_OCP)
+#define BIT_CLEAR_SW18_OCP(x) ((x) & (~BITS_SW18_OCP))
+#define BIT_GET_SW18_OCP(x) (((x) >> BIT_SHIFT_SW18_OCP) & BIT_MASK_SW18_OCP)
+#define BIT_SET_SW18_OCP(x, v) (BIT_CLEAR_SW18_OCP(x) | BIT_SW18_OCP(v))
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
+#define BIT_SHIFT_OCP_L1 15
+#define BIT_MASK_OCP_L1 0x7
+#define BIT_OCP_L1(x) (((x) & BIT_MASK_OCP_L1) << BIT_SHIFT_OCP_L1)
+#define BITS_OCP_L1 (BIT_MASK_OCP_L1 << BIT_SHIFT_OCP_L1)
+#define BIT_CLEAR_OCP_L1(x) ((x) & (~BITS_OCP_L1))
+#define BIT_GET_OCP_L1(x) (((x) >> BIT_SHIFT_OCP_L1) & BIT_MASK_OCP_L1)
+#define BIT_SET_OCP_L1(x, v) (BIT_CLEAR_OCP_L1(x) | BIT_OCP_L1(v))
-#define BIT_SHIFT_CF_L 13
-#define BIT_MASK_CF_L 0x3
-#define BIT_CF_L(x) (((x) & BIT_MASK_CF_L) << BIT_SHIFT_CF_L)
-#define BIT_GET_CF_L(x) (((x) >> BIT_SHIFT_CF_L) & BIT_MASK_CF_L)
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#endif
+/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
+#define BIT_SHIFT_STD_L1 14
+#define BIT_MASK_STD_L1 0x3
+#define BIT_STD_L1(x) (((x) & BIT_MASK_STD_L1) << BIT_SHIFT_STD_L1)
+#define BITS_STD_L1 (BIT_MASK_STD_L1 << BIT_SHIFT_STD_L1)
+#define BIT_CLEAR_STD_L1(x) ((x) & (~BITS_STD_L1))
+#define BIT_GET_STD_L1(x) (((x) >> BIT_SHIFT_STD_L1) & BIT_MASK_STD_L1)
+#define BIT_SET_STD_L1(x, v) (BIT_CLEAR_STD_L1(x) | BIT_STD_L1(v))
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
-#define BIT_SW18_FPWM BIT(11)
+#define BIT_SHIFT_CF_L_BIT0_TO_1 13
+#define BIT_MASK_CF_L_BIT0_TO_1 0x3
+#define BIT_CF_L_BIT0_TO_1(x) \
+ (((x) & BIT_MASK_CF_L_BIT0_TO_1) << BIT_SHIFT_CF_L_BIT0_TO_1)
+#define BITS_CF_L_BIT0_TO_1 \
+ (BIT_MASK_CF_L_BIT0_TO_1 << BIT_SHIFT_CF_L_BIT0_TO_1)
+#define BIT_CLEAR_CF_L_BIT0_TO_1(x) ((x) & (~BITS_CF_L_BIT0_TO_1))
+#define BIT_GET_CF_L_BIT0_TO_1(x) \
+ (((x) >> BIT_SHIFT_CF_L_BIT0_TO_1) & BIT_MASK_CF_L_BIT0_TO_1)
+#define BIT_SET_CF_L_BIT0_TO_1(x, v) \
+ (BIT_CLEAR_CF_L_BIT0_TO_1(x) | BIT_CF_L_BIT0_TO_1(v))
#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
+
+#define BIT_SHIFT_CF_L 13
+#define BIT_MASK_CF_L 0x3
+#define BIT_CF_L(x) (((x) & BIT_MASK_CF_L) << BIT_SHIFT_CF_L)
+#define BITS_CF_L (BIT_MASK_CF_L << BIT_SHIFT_CF_L)
+#define BIT_CLEAR_CF_L(x) ((x) & (~BITS_CF_L))
+#define BIT_GET_CF_L(x) (((x) >> BIT_SHIFT_CF_L) & BIT_MASK_CF_L)
+#define BIT_SET_CF_L(x, v) (BIT_CLEAR_CF_L(x) | BIT_CF_L(v))
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
+#define BIT_SW18_FPWM BIT(11)
-#define BIT_SHIFT_VOL_L1 10
-#define BIT_MASK_VOL_L1 0xf
-#define BIT_VOL_L1(x) (((x) & BIT_MASK_VOL_L1) << BIT_SHIFT_VOL_L1)
-#define BIT_GET_VOL_L1(x) (((x) >> BIT_SHIFT_VOL_L1) & BIT_MASK_VOL_L1)
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#endif
+/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
+#define BIT_SHIFT_VOL_L1 10
+#define BIT_MASK_VOL_L1 0xf
+#define BIT_VOL_L1(x) (((x) & BIT_MASK_VOL_L1) << BIT_SHIFT_VOL_L1)
+#define BITS_VOL_L1 (BIT_MASK_VOL_L1 << BIT_SHIFT_VOL_L1)
+#define BIT_CLEAR_VOL_L1(x) ((x) & (~BITS_VOL_L1))
+#define BIT_GET_VOL_L1(x) (((x) >> BIT_SHIFT_VOL_L1) & BIT_MASK_VOL_L1)
+#define BIT_SET_VOL_L1(x, v) (BIT_CLEAR_VOL_L1(x) | BIT_VOL_L1(v))
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
-#define BIT_SW18_SWEN BIT(9)
-#define BIT_SW18_LDEN BIT(8)
-#define BIT_MAC_ID_EN BIT(7)
+#define BIT_SW18_SWEN BIT(9)
+#define BIT_SW18_LDEN BIT(8)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
+#define BIT_MAC_ID_EN BIT(7)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
-#define BIT_WL_CTRL_XTAL_CADJ BIT(6)
+#define BIT_WL_CTRL_XTAL_CADJ BIT(6)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
-#define BIT_LDO11_EN BIT(6)
-#define BIT_AFE_P3_PC BIT(5)
-#define BIT_AFE_P2_PC BIT(4)
-#define BIT_AFE_P1_PC BIT(3)
-#define BIT_AFE_P0_PC BIT(2)
+#define BIT_LDO11_EN BIT(6)
+#define BIT_AFE_P3_PC BIT(5)
+#define BIT_AFE_P2_PC BIT(4)
+#define BIT_AFE_P1_PC BIT(3)
+#define BIT_AFE_P0_PC BIT(2)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */
-#define BIT_AFE_BGEN BIT(0)
+#define BIT_AFE_BGEN BIT(0)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-#define BIT_POW_ZCD_L BIT(31)
+#define BIT_POW_ZCD_L BIT(31)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-#define BIT_IO_READY_SIGNAL_ERR_MSK BIT(31)
+#define BIT_IO_READY_SIGNAL_ERR_MSK BIT(31)
#endif
-
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-#define BIT_SDIO_CRCERR_MSK BIT(31)
+#define BIT_SDIO_CRCERR_MSK BIT(31)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-#define BIT_ENABLE_ZCDOUT_L BIT(30)
+#define BIT_ENABLE_ZCDOUT_L BIT(30)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-#define BIT_SDIO_TX_CRC__MSK BIT(30)
+#define BIT_SDIO_TX_CRC__MSK BIT(30)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
+#define BIT_SDIO_HSISR3_IND_MSK BIT(30)
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-#define BIT_AUTOZCD_L BIT(30)
-#define BIT_SDIO_HSISR3_IND_MSK BIT(30)
-#define BIT_SDIO_HSISR2_IND_MSK BIT(29)
+#define BIT_AUTOZCD_L BIT(30)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
+#define BIT_SDIO_HSISR2_IND_MSK BIT(29)
-/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_REG_DELAY 28
-#define BIT_MASK_REG_DELAY 0x3
-#define BIT_REG_DELAY(x) (((x) & BIT_MASK_REG_DELAY) << BIT_SHIFT_REG_DELAY)
-#define BIT_GET_REG_DELAY(x) (((x) >> BIT_SHIFT_REG_DELAY) & BIT_MASK_REG_DELAY)
+/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
+#define BIT_SHIFT_REG_DELAY 28
+#define BIT_MASK_REG_DELAY 0x3
+#define BIT_REG_DELAY(x) (((x) & BIT_MASK_REG_DELAY) << BIT_SHIFT_REG_DELAY)
+#define BITS_REG_DELAY (BIT_MASK_REG_DELAY << BIT_SHIFT_REG_DELAY)
+#define BIT_CLEAR_REG_DELAY(x) ((x) & (~BITS_REG_DELAY))
+#define BIT_GET_REG_DELAY(x) (((x) >> BIT_SHIFT_REG_DELAY) & BIT_MASK_REG_DELAY)
+#define BIT_SET_REG_DELAY(x, v) (BIT_CLEAR_REG_DELAY(x) | BIT_REG_DELAY(v))
#endif
-
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-#define BIT_SDIO_HEISR_IND_MSK BIT(28)
+#define BIT_SDIO_HEISR_IND_MSK BIT(28)
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-#define BIT_SDIO_CTWEND_MSK BIT(27)
-#define BIT_SDIO_ATIMEND_E_MSK BIT(26)
+#define BIT_SDIO_CTWEND_MSK BIT(27)
+#define BIT_SDIO_ATIMEND_E_MSK BIT(26)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-#define BIT_SDIO_ATIMEND_MSK BIT(25)
+#define BIT_SDIO_ATIMEND_MSK BIT(25)
#endif
-
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-#define BIT_SDIIO_ATIMEND_MSK BIT(25)
+#define BIT_SDIIO_ATIMEND_MSK BIT(25)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-
-#define BIT_SHIFT_SW18_V15ADJ 24
-#define BIT_MASK_SW18_V15ADJ 0x7
-#define BIT_SW18_V15ADJ(x) (((x) & BIT_MASK_SW18_V15ADJ) << BIT_SHIFT_SW18_V15ADJ)
-#define BIT_GET_SW18_V15ADJ(x) (((x) >> BIT_SHIFT_SW18_V15ADJ) & BIT_MASK_SW18_V15ADJ)
-
+#define BIT_SHIFT_SW18_V15ADJ 24
+#define BIT_MASK_SW18_V15ADJ 0x7
+#define BIT_SW18_V15ADJ(x) \
+ (((x) & BIT_MASK_SW18_V15ADJ) << BIT_SHIFT_SW18_V15ADJ)
+#define BITS_SW18_V15ADJ (BIT_MASK_SW18_V15ADJ << BIT_SHIFT_SW18_V15ADJ)
+#define BIT_CLEAR_SW18_V15ADJ(x) ((x) & (~BITS_SW18_V15ADJ))
+#define BIT_GET_SW18_V15ADJ(x) \
+ (((x) >> BIT_SHIFT_SW18_V15ADJ) & BIT_MASK_SW18_V15ADJ)
+#define BIT_SET_SW18_V15ADJ(x, v) \
+ (BIT_CLEAR_SW18_V15ADJ(x) | BIT_SW18_V15ADJ(v))
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-#define BIT_SDIO_OCPINT_MSK BIT(24)
+#define BIT_SDIO_OCPINT_MSK BIT(24)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-#define BIT_OCPSL BIT(24)
+#define BIT_OCPSL BIT(24)
#endif
-
#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-
-#define BIT_SHIFT_V15ADJ_L1_V1 24
-#define BIT_MASK_V15ADJ_L1_V1 0x7
-#define BIT_V15ADJ_L1_V1(x) (((x) & BIT_MASK_V15ADJ_L1_V1) << BIT_SHIFT_V15ADJ_L1_V1)
-#define BIT_GET_V15ADJ_L1_V1(x) (((x) >> BIT_SHIFT_V15ADJ_L1_V1) & BIT_MASK_V15ADJ_L1_V1)
-
+#define BIT_SHIFT_V15ADJ_L1_V1 24
+#define BIT_MASK_V15ADJ_L1_V1 0x7
+#define BIT_V15ADJ_L1_V1(x) \
+ (((x) & BIT_MASK_V15ADJ_L1_V1) << BIT_SHIFT_V15ADJ_L1_V1)
+#define BITS_V15ADJ_L1_V1 (BIT_MASK_V15ADJ_L1_V1 << BIT_SHIFT_V15ADJ_L1_V1)
+#define BIT_CLEAR_V15ADJ_L1_V1(x) ((x) & (~BITS_V15ADJ_L1_V1))
+#define BIT_GET_V15ADJ_L1_V1(x) \
+ (((x) >> BIT_SHIFT_V15ADJ_L1_V1) & BIT_MASK_V15ADJ_L1_V1)
+#define BIT_SET_V15ADJ_L1_V1(x, v) \
+ (BIT_CLEAR_V15ADJ_L1_V1(x) | BIT_V15ADJ_L1_V1(v))
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-#define BIT_SDIO_PSTIMEOUT_MSK BIT(23)
+#define BIT_SDIO_PSTIMEOUT_MSK BIT(23)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-#define BIT_REG_LDOF_L_V1 BIT(23)
+#define BIT_REG_LDOF_L_V1 BIT(23)
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-#define BIT_SDIO_GTINT4_MSK BIT(22)
+#define BIT_SDIO_GTINT4_MSK BIT(22)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-#define BIT_PARSW_DUMMY BIT(22)
+#define BIT_PARSW_DUMMY BIT(22)
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-#define BIT_SDIO_GTINT3_MSK BIT(21)
+#define BIT_SDIO_GTINT3_MSK BIT(21)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-#define BIT_CLAMP_MAX_DUTY BIT(21)
+#define BIT_CLAMP_MAX_DUTY BIT(21)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-
-#define BIT_SHIFT_SW18_VOL 20
-#define BIT_MASK_SW18_VOL 0xf
-#define BIT_SW18_VOL(x) (((x) & BIT_MASK_SW18_VOL) << BIT_SHIFT_SW18_VOL)
-#define BIT_GET_SW18_VOL(x) (((x) >> BIT_SHIFT_SW18_VOL) & BIT_MASK_SW18_VOL)
-
+#define BIT_SHIFT_SW18_VOL 20
+#define BIT_MASK_SW18_VOL 0xf
+#define BIT_SW18_VOL(x) (((x) & BIT_MASK_SW18_VOL) << BIT_SHIFT_SW18_VOL)
+#define BITS_SW18_VOL (BIT_MASK_SW18_VOL << BIT_SHIFT_SW18_VOL)
+#define BIT_CLEAR_SW18_VOL(x) ((x) & (~BITS_SW18_VOL))
+#define BIT_GET_SW18_VOL(x) (((x) >> BIT_SHIFT_SW18_VOL) & BIT_MASK_SW18_VOL)
+#define BIT_SET_SW18_VOL(x, v) (BIT_CLEAR_SW18_VOL(x) | BIT_SW18_VOL(v))
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-#define BIT_SDIO_HSISR_IND_MSK BIT(20)
+#define BIT_SDIO_HSISR_IND_MSK BIT(20)
#endif
-
#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-
-#define BIT_SHIFT_VOL_L1_V1 20
-#define BIT_MASK_VOL_L1_V1 0xf
-#define BIT_VOL_L1_V1(x) (((x) & BIT_MASK_VOL_L1_V1) << BIT_SHIFT_VOL_L1_V1)
-#define BIT_GET_VOL_L1_V1(x) (((x) >> BIT_SHIFT_VOL_L1_V1) & BIT_MASK_VOL_L1_V1)
-
+#define BIT_SHIFT_VOL_L1_V1 20
+#define BIT_MASK_VOL_L1_V1 0xf
+#define BIT_VOL_L1_V1(x) (((x) & BIT_MASK_VOL_L1_V1) << BIT_SHIFT_VOL_L1_V1)
+#define BITS_VOL_L1_V1 (BIT_MASK_VOL_L1_V1 << BIT_SHIFT_VOL_L1_V1)
+#define BIT_CLEAR_VOL_L1_V1(x) ((x) & (~BITS_VOL_L1_V1))
+#define BIT_GET_VOL_L1_V1(x) (((x) >> BIT_SHIFT_VOL_L1_V1) & BIT_MASK_VOL_L1_V1)
+#define BIT_SET_VOL_L1_V1(x, v) (BIT_CLEAR_VOL_L1_V1(x) | BIT_VOL_L1_V1(v))
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-#define BIT_SDIO_CPWM2_MSK BIT(19)
+#define BIT_SDIO_CPWM2_MSK BIT(19)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-
-#define BIT_SHIFT_TBOX_L1_V1 19
-#define BIT_MASK_TBOX_L1_V1 0x3
-#define BIT_TBOX_L1_V1(x) (((x) & BIT_MASK_TBOX_L1_V1) << BIT_SHIFT_TBOX_L1_V1)
-#define BIT_GET_TBOX_L1_V1(x) (((x) >> BIT_SHIFT_TBOX_L1_V1) & BIT_MASK_TBOX_L1_V1)
-
+#define BIT_SHIFT_TBOX_L1_V1 19
+#define BIT_MASK_TBOX_L1_V1 0x3
+#define BIT_TBOX_L1_V1(x) (((x) & BIT_MASK_TBOX_L1_V1) << BIT_SHIFT_TBOX_L1_V1)
+#define BITS_TBOX_L1_V1 (BIT_MASK_TBOX_L1_V1 << BIT_SHIFT_TBOX_L1_V1)
+#define BIT_CLEAR_TBOX_L1_V1(x) ((x) & (~BITS_TBOX_L1_V1))
+#define BIT_GET_TBOX_L1_V1(x) \
+ (((x) >> BIT_SHIFT_TBOX_L1_V1) & BIT_MASK_TBOX_L1_V1)
+#define BIT_SET_TBOX_L1_V1(x, v) (BIT_CLEAR_TBOX_L1_V1(x) | BIT_TBOX_L1_V1(v))
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-#define BIT_SDIO_CPWM1_MSK BIT(18)
+#define BIT_SDIO_CPWM1_MSK BIT(18)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-
-#define BIT_SHIFT_SW18_IN 17
-#define BIT_MASK_SW18_IN 0x7
-#define BIT_SW18_IN(x) (((x) & BIT_MASK_SW18_IN) << BIT_SHIFT_SW18_IN)
-#define BIT_GET_SW18_IN(x) (((x) >> BIT_SHIFT_SW18_IN) & BIT_MASK_SW18_IN)
-
+#define BIT_SHIFT_SW18_IN 17
+#define BIT_MASK_SW18_IN 0x7
+#define BIT_SW18_IN(x) (((x) & BIT_MASK_SW18_IN) << BIT_SHIFT_SW18_IN)
+#define BITS_SW18_IN (BIT_MASK_SW18_IN << BIT_SHIFT_SW18_IN)
+#define BIT_CLEAR_SW18_IN(x) ((x) & (~BITS_SW18_IN))
+#define BIT_GET_SW18_IN(x) (((x) >> BIT_SHIFT_SW18_IN) & BIT_MASK_SW18_IN)
+#define BIT_SET_SW18_IN(x, v) (BIT_CLEAR_SW18_IN(x) | BIT_SW18_IN(v))
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-#define BIT_SDIO_C2HCMD_INT_MSK BIT(17)
+#define BIT_SDIO_C2HCMD_INT_MSK BIT(17)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-
-#define BIT_SHIFT_REG_DELAY_V3 17
-#define BIT_MASK_REG_DELAY_V3 0x3
-#define BIT_REG_DELAY_V3(x) (((x) & BIT_MASK_REG_DELAY_V3) << BIT_SHIFT_REG_DELAY_V3)
-#define BIT_GET_REG_DELAY_V3(x) (((x) >> BIT_SHIFT_REG_DELAY_V3) & BIT_MASK_REG_DELAY_V3)
-
+#define BIT_SHIFT_REG_DELAY_V3 17
+#define BIT_MASK_REG_DELAY_V3 0x3
+#define BIT_REG_DELAY_V3(x) \
+ (((x) & BIT_MASK_REG_DELAY_V3) << BIT_SHIFT_REG_DELAY_V3)
+#define BITS_REG_DELAY_V3 (BIT_MASK_REG_DELAY_V3 << BIT_SHIFT_REG_DELAY_V3)
+#define BIT_CLEAR_REG_DELAY_V3(x) ((x) & (~BITS_REG_DELAY_V3))
+#define BIT_GET_REG_DELAY_V3(x) \
+ (((x) >> BIT_SHIFT_REG_DELAY_V3) & BIT_MASK_REG_DELAY_V3)
+#define BIT_SET_REG_DELAY_V3(x, v) \
+ (BIT_CLEAR_REG_DELAY_V3(x) | BIT_REG_DELAY_V3(v))
#endif
-
#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-
-#define BIT_SHIFT_IN_L1_V1 17
-#define BIT_MASK_IN_L1_V1 0x7
-#define BIT_IN_L1_V1(x) (((x) & BIT_MASK_IN_L1_V1) << BIT_SHIFT_IN_L1_V1)
-#define BIT_GET_IN_L1_V1(x) (((x) >> BIT_SHIFT_IN_L1_V1) & BIT_MASK_IN_L1_V1)
-
+#define BIT_SHIFT_IN_L1_V1 17
+#define BIT_MASK_IN_L1_V1 0x7
+#define BIT_IN_L1_V1(x) (((x) & BIT_MASK_IN_L1_V1) << BIT_SHIFT_IN_L1_V1)
+#define BITS_IN_L1_V1 (BIT_MASK_IN_L1_V1 << BIT_SHIFT_IN_L1_V1)
+#define BIT_CLEAR_IN_L1_V1(x) ((x) & (~BITS_IN_L1_V1))
+#define BIT_GET_IN_L1_V1(x) (((x) >> BIT_SHIFT_IN_L1_V1) & BIT_MASK_IN_L1_V1)
+#define BIT_SET_IN_L1_V1(x, v) (BIT_CLEAR_IN_L1_V1(x) | BIT_IN_L1_V1(v))
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-#define BIT_SDIO_BCNERLY_INT_MSK BIT(16)
+#define BIT_SDIO_BCNERLY_INT_MSK BIT(16)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-#define BIT_REG_CLAMP_D_L_V2 BIT(16)
+#define BIT_REG_CLAMP_D_L_V2 BIT(16)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-
-#define BIT_SHIFT_SW18_TBOX 15
-#define BIT_MASK_SW18_TBOX 0x3
-#define BIT_SW18_TBOX(x) (((x) & BIT_MASK_SW18_TBOX) << BIT_SHIFT_SW18_TBOX)
-#define BIT_GET_SW18_TBOX(x) (((x) >> BIT_SHIFT_SW18_TBOX) & BIT_MASK_SW18_TBOX)
-
+#define BIT_SHIFT_SW18_TBOX 15
+#define BIT_MASK_SW18_TBOX 0x3
+#define BIT_SW18_TBOX(x) (((x) & BIT_MASK_SW18_TBOX) << BIT_SHIFT_SW18_TBOX)
+#define BITS_SW18_TBOX (BIT_MASK_SW18_TBOX << BIT_SHIFT_SW18_TBOX)
+#define BIT_CLEAR_SW18_TBOX(x) ((x) & (~BITS_SW18_TBOX))
+#define BIT_GET_SW18_TBOX(x) (((x) >> BIT_SHIFT_SW18_TBOX) & BIT_MASK_SW18_TBOX)
+#define BIT_SET_SW18_TBOX(x, v) (BIT_CLEAR_SW18_TBOX(x) | BIT_SW18_TBOX(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-#define BIT_REG_BYPASS_L_V3 BIT(15)
+#define BIT_REG_BYPASS_L_V3 BIT(15)
#endif
-
#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-
-#define BIT_SHIFT_TBOX_L1 15
-#define BIT_MASK_TBOX_L1 0x3
-#define BIT_TBOX_L1(x) (((x) & BIT_MASK_TBOX_L1) << BIT_SHIFT_TBOX_L1)
-#define BIT_GET_TBOX_L1(x) (((x) >> BIT_SHIFT_TBOX_L1) & BIT_MASK_TBOX_L1)
-
+#define BIT_SHIFT_TBOX_L1 15
+#define BIT_MASK_TBOX_L1 0x3
+#define BIT_TBOX_L1(x) (((x) & BIT_MASK_TBOX_L1) << BIT_SHIFT_TBOX_L1)
+#define BITS_TBOX_L1 (BIT_MASK_TBOX_L1 << BIT_SHIFT_TBOX_L1)
+#define BIT_CLEAR_TBOX_L1(x) ((x) & (~BITS_TBOX_L1))
+#define BIT_GET_TBOX_L1(x) (((x) >> BIT_SHIFT_TBOX_L1) & BIT_MASK_TBOX_L1)
+#define BIT_SET_TBOX_L1(x, v) (BIT_CLEAR_TBOX_L1(x) | BIT_TBOX_L1(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-#define BIT_ENABLE_ZCDOUT_L_V3 BIT(14)
+#define BIT_ENABLE_ZCDOUT_L_V3 BIT(14)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-#define BIT_SW18_SEL BIT(13)
+#define BIT_SW18_SEL BIT(13)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-#define BIT_POW_ZCD_L_V3 BIT(13)
-#define BIT_AREN_L1_V1 BIT(12)
+#define BIT_POW_ZCD_L_V3 BIT(13)
+#define BIT_AREN_L1_V1 BIT(12)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-
-#define BIT_SHIFT_SW18_STD 11
-#define BIT_MASK_SW18_STD 0x3
-#define BIT_SW18_STD(x) (((x) & BIT_MASK_SW18_STD) << BIT_SHIFT_SW18_STD)
-#define BIT_GET_SW18_STD(x) (((x) >> BIT_SHIFT_SW18_STD) & BIT_MASK_SW18_STD)
-
+#define BIT_SHIFT_SW18_STD 11
+#define BIT_MASK_SW18_STD 0x3
+#define BIT_SW18_STD(x) (((x) & BIT_MASK_SW18_STD) << BIT_SHIFT_SW18_STD)
+#define BITS_SW18_STD (BIT_MASK_SW18_STD << BIT_SHIFT_SW18_STD)
+#define BIT_CLEAR_SW18_STD(x) ((x) & (~BITS_SW18_STD))
+#define BIT_GET_SW18_STD(x) (((x) >> BIT_SHIFT_SW18_STD) & BIT_MASK_SW18_STD)
+#define BIT_SET_SW18_STD(x, v) (BIT_CLEAR_SW18_STD(x) | BIT_SW18_STD(v))
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-#define BIT_SW18_SD BIT(10)
+#define BIT_SW18_SD BIT(10)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-#define BIT_SW18_AREN BIT(9)
+#define BIT_SW18_AREN BIT(9)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
+#define BIT_SHIFT_OCP_V3 9
+#define BIT_MASK_OCP_V3 0x7
+#define BIT_OCP_V3(x) (((x) & BIT_MASK_OCP_V3) << BIT_SHIFT_OCP_V3)
+#define BITS_OCP_V3 (BIT_MASK_OCP_V3 << BIT_SHIFT_OCP_V3)
+#define BIT_CLEAR_OCP_V3(x) ((x) & (~BITS_OCP_V3))
+#define BIT_GET_OCP_V3(x) (((x) >> BIT_SHIFT_OCP_V3) & BIT_MASK_OCP_V3)
+#define BIT_SET_OCP_V3(x, v) (BIT_CLEAR_OCP_V3(x) | BIT_OCP_V3(v))
-#define BIT_SHIFT_OCP_V3 9
-#define BIT_MASK_OCP_V3 0x7
-#define BIT_OCP_V3(x) (((x) & BIT_MASK_OCP_V3) << BIT_SHIFT_OCP_V3)
-#define BIT_GET_OCP_V3(x) (((x) >> BIT_SHIFT_OCP_V3) & BIT_MASK_OCP_V3)
-
-#define BIT_POWOCP_V3 BIT(8)
+#define BIT_POWOCP_V3 BIT(8)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-
-#define BIT_SHIFT_SW18_R3 7
-#define BIT_MASK_SW18_R3 0x3
-#define BIT_SW18_R3(x) (((x) & BIT_MASK_SW18_R3) << BIT_SHIFT_SW18_R3)
-#define BIT_GET_SW18_R3(x) (((x) >> BIT_SHIFT_SW18_R3) & BIT_MASK_SW18_R3)
-
+#define BIT_SHIFT_SW18_R3 7
+#define BIT_MASK_SW18_R3 0x3
+#define BIT_SW18_R3(x) (((x) & BIT_MASK_SW18_R3) << BIT_SHIFT_SW18_R3)
+#define BITS_SW18_R3 (BIT_MASK_SW18_R3 << BIT_SHIFT_SW18_R3)
+#define BIT_CLEAR_SW18_R3(x) ((x) & (~BITS_SW18_R3))
+#define BIT_GET_SW18_R3(x) (((x) >> BIT_SHIFT_SW18_R3) & BIT_MASK_SW18_R3)
+#define BIT_SET_SW18_R3(x, v) (BIT_CLEAR_SW18_R3(x) | BIT_SW18_R3(v))
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-#define BIT_SDIO_TXBCNERR_MSK BIT(7)
+#define BIT_SDIO_TXBCNERR_MSK BIT(7)
#endif
-
#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-
-#define BIT_SHIFT_R3_L 7
-#define BIT_MASK_R3_L 0x3
-#define BIT_R3_L(x) (((x) & BIT_MASK_R3_L) << BIT_SHIFT_R3_L)
-#define BIT_GET_R3_L(x) (((x) >> BIT_SHIFT_R3_L) & BIT_MASK_R3_L)
-
+#define BIT_SHIFT_R3_L 7
+#define BIT_MASK_R3_L 0x3
+#define BIT_R3_L(x) (((x) & BIT_MASK_R3_L) << BIT_SHIFT_R3_L)
+#define BITS_R3_L (BIT_MASK_R3_L << BIT_SHIFT_R3_L)
+#define BIT_CLEAR_R3_L(x) ((x) & (~BITS_R3_L))
+#define BIT_GET_R3_L(x) (((x) >> BIT_SHIFT_R3_L) & BIT_MASK_R3_L)
+#define BIT_SET_R3_L(x, v) (BIT_CLEAR_R3_L(x) | BIT_R3_L(v))
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-#define BIT_SDIO_TXBCNOK_MSK BIT(6)
+#define BIT_SDIO_TXBCNOK_MSK BIT(6)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-
-#define BIT_SHIFT_CF_L_V3 6
-#define BIT_MASK_CF_L_V3 0x3
-#define BIT_CF_L_V3(x) (((x) & BIT_MASK_CF_L_V3) << BIT_SHIFT_CF_L_V3)
-#define BIT_GET_CF_L_V3(x) (((x) >> BIT_SHIFT_CF_L_V3) & BIT_MASK_CF_L_V3)
-
+#define BIT_SHIFT_CF_L_V3 6
+#define BIT_MASK_CF_L_V3 0x3
+#define BIT_CF_L_V3(x) (((x) & BIT_MASK_CF_L_V3) << BIT_SHIFT_CF_L_V3)
+#define BITS_CF_L_V3 (BIT_MASK_CF_L_V3 << BIT_SHIFT_CF_L_V3)
+#define BIT_CLEAR_CF_L_V3(x) ((x) & (~BITS_CF_L_V3))
+#define BIT_GET_CF_L_V3(x) (((x) >> BIT_SHIFT_CF_L_V3) & BIT_MASK_CF_L_V3)
+#define BIT_SET_CF_L_V3(x, v) (BIT_CLEAR_CF_L_V3(x) | BIT_CF_L_V3(v))
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-
-#define BIT_SHIFT_SW18_R2 5
-#define BIT_MASK_SW18_R2 0x3
-#define BIT_SW18_R2(x) (((x) & BIT_MASK_SW18_R2) << BIT_SHIFT_SW18_R2)
-#define BIT_GET_SW18_R2(x) (((x) >> BIT_SHIFT_SW18_R2) & BIT_MASK_SW18_R2)
-
+#define BIT_SHIFT_SW18_R2 5
+#define BIT_MASK_SW18_R2 0x3
+#define BIT_SW18_R2(x) (((x) & BIT_MASK_SW18_R2) << BIT_SHIFT_SW18_R2)
+#define BITS_SW18_R2 (BIT_MASK_SW18_R2 << BIT_SHIFT_SW18_R2)
+#define BIT_CLEAR_SW18_R2(x) ((x) & (~BITS_SW18_R2))
+#define BIT_GET_SW18_R2(x) (((x) >> BIT_SHIFT_SW18_R2) & BIT_MASK_SW18_R2)
+#define BIT_SET_SW18_R2(x, v) (BIT_CLEAR_SW18_R2(x) | BIT_SW18_R2(v))
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-#define BIT_SDIO_RXFOVW_MSK BIT(5)
-#define BIT_SDIO_TXFOVW_MSK BIT(4)
+#define BIT_SDIO_RXFOVW_MSK BIT(5)
+#define BIT_SDIO_TXFOVW_MSK BIT(4)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-
-#define BIT_SHIFT_CFC_L_BIT0_TO_1_V1 4
-#define BIT_MASK_CFC_L_BIT0_TO_1_V1 0x3
-#define BIT_CFC_L_BIT0_TO_1_V1(x) (((x) & BIT_MASK_CFC_L_BIT0_TO_1_V1) << BIT_SHIFT_CFC_L_BIT0_TO_1_V1)
-#define BIT_GET_CFC_L_BIT0_TO_1_V1(x) (((x) >> BIT_SHIFT_CFC_L_BIT0_TO_1_V1) & BIT_MASK_CFC_L_BIT0_TO_1_V1)
-
+#define BIT_SHIFT_CFC_L_BIT0_TO_1_V1 4
+#define BIT_MASK_CFC_L_BIT0_TO_1_V1 0x3
+#define BIT_CFC_L_BIT0_TO_1_V1(x) \
+ (((x) & BIT_MASK_CFC_L_BIT0_TO_1_V1) << BIT_SHIFT_CFC_L_BIT0_TO_1_V1)
+#define BITS_CFC_L_BIT0_TO_1_V1 \
+ (BIT_MASK_CFC_L_BIT0_TO_1_V1 << BIT_SHIFT_CFC_L_BIT0_TO_1_V1)
+#define BIT_CLEAR_CFC_L_BIT0_TO_1_V1(x) ((x) & (~BITS_CFC_L_BIT0_TO_1_V1))
+#define BIT_GET_CFC_L_BIT0_TO_1_V1(x) \
+ (((x) >> BIT_SHIFT_CFC_L_BIT0_TO_1_V1) & BIT_MASK_CFC_L_BIT0_TO_1_V1)
+#define BIT_SET_CFC_L_BIT0_TO_1_V1(x, v) \
+ (BIT_CLEAR_CFC_L_BIT0_TO_1_V1(x) | BIT_CFC_L_BIT0_TO_1_V1(v))
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-
-#define BIT_SHIFT_SW18_R1 3
-#define BIT_MASK_SW18_R1 0x3
-#define BIT_SW18_R1(x) (((x) & BIT_MASK_SW18_R1) << BIT_SHIFT_SW18_R1)
-#define BIT_GET_SW18_R1(x) (((x) >> BIT_SHIFT_SW18_R1) & BIT_MASK_SW18_R1)
-
+#define BIT_SHIFT_SW18_R1 3
+#define BIT_MASK_SW18_R1 0x3
+#define BIT_SW18_R1(x) (((x) & BIT_MASK_SW18_R1) << BIT_SHIFT_SW18_R1)
+#define BITS_SW18_R1 (BIT_MASK_SW18_R1 << BIT_SHIFT_SW18_R1)
+#define BIT_CLEAR_SW18_R1(x) ((x) & (~BITS_SW18_R1))
+#define BIT_GET_SW18_R1(x) (((x) >> BIT_SHIFT_SW18_R1) & BIT_MASK_SW18_R1)
+#define BIT_SET_SW18_R1(x, v) (BIT_CLEAR_SW18_R1(x) | BIT_SW18_R1(v))
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-#define BIT_SDIO_RXERR_MSK BIT(3)
-#define BIT_SDIO_TXERR_MSK BIT(2)
+#define BIT_SDIO_RXERR_MSK BIT(3)
+#define BIT_SDIO_TXERR_MSK BIT(2)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-
-#define BIT_SHIFT_R3_L1_V1 2
-#define BIT_MASK_R3_L1_V1 0x3
-#define BIT_R3_L1_V1(x) (((x) & BIT_MASK_R3_L1_V1) << BIT_SHIFT_R3_L1_V1)
-#define BIT_GET_R3_L1_V1(x) (((x) >> BIT_SHIFT_R3_L1_V1) & BIT_MASK_R3_L1_V1)
-
+#define BIT_SHIFT_R3_L1_V1 2
+#define BIT_MASK_R3_L1_V1 0x3
+#define BIT_R3_L1_V1(x) (((x) & BIT_MASK_R3_L1_V1) << BIT_SHIFT_R3_L1_V1)
+#define BITS_R3_L1_V1 (BIT_MASK_R3_L1_V1 << BIT_SHIFT_R3_L1_V1)
+#define BIT_CLEAR_R3_L1_V1(x) ((x) & (~BITS_R3_L1_V1))
+#define BIT_GET_R3_L1_V1(x) (((x) >> BIT_SHIFT_R3_L1_V1) & BIT_MASK_R3_L1_V1)
+#define BIT_SET_R3_L1_V1(x, v) (BIT_CLEAR_R3_L1_V1(x) | BIT_R3_L1_V1(v))
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-
-#define BIT_SHIFT_SW18_C3 1
-#define BIT_MASK_SW18_C3 0x3
-#define BIT_SW18_C3(x) (((x) & BIT_MASK_SW18_C3) << BIT_SHIFT_SW18_C3)
-#define BIT_GET_SW18_C3(x) (((x) >> BIT_SHIFT_SW18_C3) & BIT_MASK_SW18_C3)
-
+#define BIT_SHIFT_SW18_C3 1
+#define BIT_MASK_SW18_C3 0x3
+#define BIT_SW18_C3(x) (((x) & BIT_MASK_SW18_C3) << BIT_SHIFT_SW18_C3)
+#define BITS_SW18_C3 (BIT_MASK_SW18_C3 << BIT_SHIFT_SW18_C3)
+#define BIT_CLEAR_SW18_C3(x) ((x) & (~BITS_SW18_C3))
+#define BIT_GET_SW18_C3(x) (((x) >> BIT_SHIFT_SW18_C3) & BIT_MASK_SW18_C3)
+#define BIT_SET_SW18_C3(x, v) (BIT_CLEAR_SW18_C3(x) | BIT_SW18_C3(v))
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-#define BIT_SDIO_AVAL_MSK BIT(1)
+#define BIT_SDIO_AVAL_MSK BIT(1)
#endif
-
#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-
-#define BIT_SHIFT_C3_L_C3 1
-#define BIT_MASK_C3_L_C3 0x3
-#define BIT_C3_L_C3(x) (((x) & BIT_MASK_C3_L_C3) << BIT_SHIFT_C3_L_C3)
-#define BIT_GET_C3_L_C3(x) (((x) >> BIT_SHIFT_C3_L_C3) & BIT_MASK_C3_L_C3)
-
+#define BIT_SHIFT_C3_L_C3 1
+#define BIT_MASK_C3_L_C3 0x3
+#define BIT_C3_L_C3(x) (((x) & BIT_MASK_C3_L_C3) << BIT_SHIFT_C3_L_C3)
+#define BITS_C3_L_C3 (BIT_MASK_C3_L_C3 << BIT_SHIFT_C3_L_C3)
+#define BIT_CLEAR_C3_L_C3(x) ((x) & (~BITS_C3_L_C3))
+#define BIT_GET_C3_L_C3(x) (((x) >> BIT_SHIFT_C3_L_C3) & BIT_MASK_C3_L_C3)
+#define BIT_SET_C3_L_C3(x, v) (BIT_CLEAR_C3_L_C3(x) | BIT_C3_L_C3(v))
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-#define BIT_SW18_C2_BIT1 BIT(0)
+#define BIT_SW18_C2_BIT1 BIT(0)
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_HIMR (Offset 0x10250014) */
-#define BIT_RX_REQUEST_MSK BIT(0)
+#define BIT_RX_REQUEST_MSK BIT(0)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-
-#define BIT_SHIFT_R2_L1_V1 0
-#define BIT_MASK_R2_L1_V1 0x3
-#define BIT_R2_L1_V1(x) (((x) & BIT_MASK_R2_L1_V1) << BIT_SHIFT_R2_L1_V1)
-#define BIT_GET_R2_L1_V1(x) (((x) >> BIT_SHIFT_R2_L1_V1) & BIT_MASK_R2_L1_V1)
-
+#define BIT_SHIFT_R2_L1_V1 0
+#define BIT_MASK_R2_L1_V1 0x3
+#define BIT_R2_L1_V1(x) (((x) & BIT_MASK_R2_L1_V1) << BIT_SHIFT_R2_L1_V1)
+#define BITS_R2_L1_V1 (BIT_MASK_R2_L1_V1 << BIT_SHIFT_R2_L1_V1)
+#define BIT_CLEAR_R2_L1_V1(x) ((x) & (~BITS_R2_L1_V1))
+#define BIT_GET_R2_L1_V1(x) (((x) >> BIT_SHIFT_R2_L1_V1) & BIT_MASK_R2_L1_V1)
+#define BIT_SET_R2_L1_V1(x, v) (BIT_CLEAR_R2_L1_V1(x) | BIT_R2_L1_V1(v))
#endif
-
#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
/* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */
-#define BIT_C2_L_BIT1 BIT(0)
+#define BIT_C2_L_BIT1 BIT(0)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_SWR_CTRL3 (Offset 0x0018) */
-#define BIT_SPS18_OCP_DIS BIT(31)
+#define BIT_SPS18_OCP_DIS BIT(31)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SDIO_HISR (Offset 0x10250018) */
-#define BIT_IO_READY_SIGNAL_ERR BIT(31)
+#define BIT_IO_READY_SIGNAL_ERR BIT(31)
#endif
-
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_HISR (Offset 0x10250018) */
-#define BIT_SDIO_CRCERR BIT(31)
+#define BIT_SDIO_CRCERR BIT(31)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SDIO_HISR (Offset 0x10250018) */
-#define BIT_TX_CRC BIT(30)
+#define BIT_TX_CRC BIT(30)
#endif
-
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_HISR (Offset 0x10250018) */
-#define BIT_SDIO_HSISR3_IND BIT(30)
-#define BIT_SDIO_HSISR2_IND BIT(29)
-#define BIT_SDIO_HEISR_IND BIT(28)
+#define BIT_SDIO_HSISR3_IND BIT(30)
+#define BIT_SDIO_HSISR2_IND BIT(29)
+#define BIT_SDIO_HEISR_IND BIT(28)
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_HISR (Offset 0x10250018) */
-#define BIT_SDIO_CTWEND BIT(27)
-#define BIT_SDIO_ATIMEND_E BIT(26)
-#define BIT_SDIO_ATIMEND BIT(25)
-#define BIT_SDIO_OCPINT BIT(24)
-#define BIT_SDIO_PSTIMEOUT BIT(23)
-#define BIT_SDIO_GTINT4 BIT(22)
-#define BIT_SDIO_GTINT3 BIT(21)
-#define BIT_SDIO_HSISR_IND BIT(20)
-#define BIT_SDIO_CPWM2 BIT(19)
-#define BIT_SDIO_CPWM1 BIT(18)
-#define BIT_SDIO_C2HCMD_INT BIT(17)
+#define BIT_SDIO_CTWEND BIT(27)
+#define BIT_SDIO_ATIMEND_E BIT(26)
+#define BIT_SDIO_ATIMEND BIT(25)
+#define BIT_SDIO_OCPINT BIT(24)
+#define BIT_SDIO_PSTIMEOUT BIT(23)
+#define BIT_SDIO_GTINT4 BIT(22)
+#define BIT_SDIO_GTINT3 BIT(21)
+#define BIT_SDIO_HSISR_IND BIT(20)
+#define BIT_SDIO_CPWM2 BIT(19)
+#define BIT_SDIO_CPWM1 BIT(18)
+#define BIT_SDIO_C2HCMD_INT BIT(17)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_SWR_CTRL3 (Offset 0x0018) */
-
-#define BIT_SHIFT_SPS18_OCP_TH 16
-#define BIT_MASK_SPS18_OCP_TH 0x7fff
-#define BIT_SPS18_OCP_TH(x) (((x) & BIT_MASK_SPS18_OCP_TH) << BIT_SHIFT_SPS18_OCP_TH)
-#define BIT_GET_SPS18_OCP_TH(x) (((x) >> BIT_SHIFT_SPS18_OCP_TH) & BIT_MASK_SPS18_OCP_TH)
-
+#define BIT_SHIFT_SPS18_OCP_TH 16
+#define BIT_MASK_SPS18_OCP_TH 0x7fff
+#define BIT_SPS18_OCP_TH(x) \
+ (((x) & BIT_MASK_SPS18_OCP_TH) << BIT_SHIFT_SPS18_OCP_TH)
+#define BITS_SPS18_OCP_TH (BIT_MASK_SPS18_OCP_TH << BIT_SHIFT_SPS18_OCP_TH)
+#define BIT_CLEAR_SPS18_OCP_TH(x) ((x) & (~BITS_SPS18_OCP_TH))
+#define BIT_GET_SPS18_OCP_TH(x) \
+ (((x) >> BIT_SHIFT_SPS18_OCP_TH) & BIT_MASK_SPS18_OCP_TH)
+#define BIT_SET_SPS18_OCP_TH(x, v) \
+ (BIT_CLEAR_SPS18_OCP_TH(x) | BIT_SPS18_OCP_TH(v))
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_HISR (Offset 0x10250018) */
-#define BIT_SDIO_BCNERLY_INT BIT(16)
-#define BIT_SDIO_TXBCNERR BIT(7)
-#define BIT_SDIO_TXBCNOK BIT(6)
-#define BIT_SDIO_RXFOVW BIT(5)
-#define BIT_SDIO_TXFOVW BIT(4)
-#define BIT_SDIO_RXERR BIT(3)
-#define BIT_SDIO_TXERR BIT(2)
-#define BIT_SDIO_AVAL BIT(1)
+#define BIT_SDIO_BCNERLY_INT BIT(16)
+#define BIT_SDIO_TXBCNERR BIT(7)
+#define BIT_SDIO_TXBCNOK BIT(6)
+#define BIT_SDIO_RXFOVW BIT(5)
+#define BIT_SDIO_TXFOVW BIT(4)
+#define BIT_SDIO_RXERR BIT(3)
+#define BIT_SDIO_TXERR BIT(2)
+#define BIT_SDIO_AVAL BIT(1)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_SWR_CTRL3 (Offset 0x0018) */
-
-#define BIT_SHIFT_OCP_WINDOW 0
-#define BIT_MASK_OCP_WINDOW 0xffff
-#define BIT_OCP_WINDOW(x) (((x) & BIT_MASK_OCP_WINDOW) << BIT_SHIFT_OCP_WINDOW)
-#define BIT_GET_OCP_WINDOW(x) (((x) >> BIT_SHIFT_OCP_WINDOW) & BIT_MASK_OCP_WINDOW)
-
+#define BIT_SHIFT_OCP_WINDOW 0
+#define BIT_MASK_OCP_WINDOW 0xffff
+#define BIT_OCP_WINDOW(x) (((x) & BIT_MASK_OCP_WINDOW) << BIT_SHIFT_OCP_WINDOW)
+#define BITS_OCP_WINDOW (BIT_MASK_OCP_WINDOW << BIT_SHIFT_OCP_WINDOW)
+#define BIT_CLEAR_OCP_WINDOW(x) ((x) & (~BITS_OCP_WINDOW))
+#define BIT_GET_OCP_WINDOW(x) \
+ (((x) >> BIT_SHIFT_OCP_WINDOW) & BIT_MASK_OCP_WINDOW)
+#define BIT_SET_OCP_WINDOW(x, v) (BIT_CLEAR_OCP_WINDOW(x) | BIT_OCP_WINDOW(v))
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_HISR (Offset 0x10250018) */
-#define BIT_RX_REQUEST BIT(0)
+#define BIT_RX_REQUEST BIT(0)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_RSV_CTRL (Offset 0x001C) */
-#define BIT_HREG_DBG BIT(23)
+#define BIT_HREG_DBG BIT(23)
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT)
/* 2 REG_RSV_CTRL (Offset 0x001C) */
+#define BIT_SHIFT_HREG_DBG_V1 12
+#define BIT_MASK_HREG_DBG_V1 0xfff
+#define BIT_HREG_DBG_V1(x) \
+ (((x) & BIT_MASK_HREG_DBG_V1) << BIT_SHIFT_HREG_DBG_V1)
+#define BITS_HREG_DBG_V1 (BIT_MASK_HREG_DBG_V1 << BIT_SHIFT_HREG_DBG_V1)
+#define BIT_CLEAR_HREG_DBG_V1(x) ((x) & (~BITS_HREG_DBG_V1))
+#define BIT_GET_HREG_DBG_V1(x) \
+ (((x) >> BIT_SHIFT_HREG_DBG_V1) & BIT_MASK_HREG_DBG_V1)
+#define BIT_SET_HREG_DBG_V1(x, v) \
+ (BIT_CLEAR_HREG_DBG_V1(x) | BIT_HREG_DBG_V1(v))
-#define BIT_SHIFT_HREG_DBG_V1 12
-#define BIT_MASK_HREG_DBG_V1 0xfff
-#define BIT_HREG_DBG_V1(x) (((x) & BIT_MASK_HREG_DBG_V1) << BIT_SHIFT_HREG_DBG_V1)
-#define BIT_GET_HREG_DBG_V1(x) (((x) >> BIT_SHIFT_HREG_DBG_V1) & BIT_MASK_HREG_DBG_V1)
+#endif
-#define BIT_MCU_RST BIT(11)
-#define BIT_WLOCK_90 BIT(10)
-#define BIT_WLOCK_70 BIT(9)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#endif
+/* 2 REG_RSV_CTRL (Offset 0x001C) */
+#define BIT_MCU_RST BIT(11)
+#define BIT_WLOCK_90 BIT(10)
+#define BIT_WLOCK_70 BIT(9)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_RSV_CTRL (Offset 0x001C) */
-#define BIT_WLMCUIOIF BIT(8)
+#define BIT_WLMCUIOIF BIT(8)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_RSV_CTRL (Offset 0x001C) */
-#define BIT_WLOCK_78 BIT(8)
+#define BIT_WLOCK_78 BIT(8)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_RSV_CTRL (Offset 0x001C) */
-#define BIT_LOCK_ALL_EN BIT(7)
+#define BIT_LOCK_ALL_EN BIT(7)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_RSV_CTRL (Offset 0x001C) */
-#define BIT_R_DIS_PRST BIT(6)
+#define BIT_R_DIS_PRST BIT(6)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_RSV_CTRL (Offset 0x001C) */
-#define BIT_R_DIS_PRST_1 BIT(6)
+#define BIT_R_DIS_PRST_1 BIT(6)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_RSV_CTRL (Offset 0x001C) */
-#define BIT_WLOCK_1C_B6 BIT(5)
+#define BIT_WLOCK_1C_B6 BIT(5)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_RSV_CTRL (Offset 0x001C) */
-#define BIT_R_DIS_PRST_0 BIT(5)
+#define BIT_R_DIS_PRST_0 BIT(5)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_RSV_CTRL (Offset 0x001C) */
-#define BIT_WLOCK_40 BIT(4)
-#define BIT_WLOCK_08 BIT(3)
-#define BIT_WLOCK_04 BIT(2)
-#define BIT_WLOCK_00 BIT(1)
-#define BIT_WLOCK_ALL BIT(0)
+#define BIT_WLOCK_40 BIT(4)
+#define BIT_WLOCK_08 BIT(3)
+#define BIT_WLOCK_04 BIT(2)
+#define BIT_WLOCK_00 BIT(1)
+#define BIT_WLOCK_ALL BIT(0)
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_RX_REQ_LEN (Offset 0x1025001C) */
-
-#define BIT_SHIFT_RX_REQ_LEN_V1 0
-#define BIT_MASK_RX_REQ_LEN_V1 0x3ffff
-#define BIT_RX_REQ_LEN_V1(x) (((x) & BIT_MASK_RX_REQ_LEN_V1) << BIT_SHIFT_RX_REQ_LEN_V1)
-#define BIT_GET_RX_REQ_LEN_V1(x) (((x) >> BIT_SHIFT_RX_REQ_LEN_V1) & BIT_MASK_RX_REQ_LEN_V1)
-
+#define BIT_SHIFT_RX_REQ_LEN_V1 0
+#define BIT_MASK_RX_REQ_LEN_V1 0x3ffff
+#define BIT_RX_REQ_LEN_V1(x) \
+ (((x) & BIT_MASK_RX_REQ_LEN_V1) << BIT_SHIFT_RX_REQ_LEN_V1)
+#define BITS_RX_REQ_LEN_V1 (BIT_MASK_RX_REQ_LEN_V1 << BIT_SHIFT_RX_REQ_LEN_V1)
+#define BIT_CLEAR_RX_REQ_LEN_V1(x) ((x) & (~BITS_RX_REQ_LEN_V1))
+#define BIT_GET_RX_REQ_LEN_V1(x) \
+ (((x) >> BIT_SHIFT_RX_REQ_LEN_V1) & BIT_MASK_RX_REQ_LEN_V1)
+#define BIT_SET_RX_REQ_LEN_V1(x, v) \
+ (BIT_CLEAR_RX_REQ_LEN_V1(x) | BIT_RX_REQ_LEN_V1(v))
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_RF_CTRL (Offset 0x001F) */
-#define BIT_RF_SDMRSTB BIT(2)
+#define BIT_RF_SDMRSTB BIT(2)
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_RF0_CTRL (Offset 0x001F) */
-#define BIT_RF0_SDMRSTB BIT(2)
+#define BIT_RF0_SDMRSTB BIT(2)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_RF_CTRL (Offset 0x001F) */
-#define BIT_RF_RSTB BIT(1)
+#define BIT_RF_RSTB BIT(1)
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_RF0_CTRL (Offset 0x001F) */
-#define BIT_RF0_RSTB BIT(1)
+#define BIT_RF0_RSTB BIT(1)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_RF_CTRL (Offset 0x001F) */
-#define BIT_RF_EN BIT(0)
+#define BIT_RF_EN BIT(0)
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_RF0_CTRL (Offset 0x001F) */
-#define BIT_RF0_EN BIT(0)
+#define BIT_RF0_EN BIT(0)
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_FREE_TXPG_SEQ_V1 (Offset 0x1025001F) */
-
-#define BIT_SHIFT_FREE_TXPG_SEQ 0
-#define BIT_MASK_FREE_TXPG_SEQ 0xff
-#define BIT_FREE_TXPG_SEQ(x) (((x) & BIT_MASK_FREE_TXPG_SEQ) << BIT_SHIFT_FREE_TXPG_SEQ)
-#define BIT_GET_FREE_TXPG_SEQ(x) (((x) >> BIT_SHIFT_FREE_TXPG_SEQ) & BIT_MASK_FREE_TXPG_SEQ)
-
+#define BIT_SHIFT_FREE_TXPG_SEQ 0
+#define BIT_MASK_FREE_TXPG_SEQ 0xff
+#define BIT_FREE_TXPG_SEQ(x) \
+ (((x) & BIT_MASK_FREE_TXPG_SEQ) << BIT_SHIFT_FREE_TXPG_SEQ)
+#define BITS_FREE_TXPG_SEQ (BIT_MASK_FREE_TXPG_SEQ << BIT_SHIFT_FREE_TXPG_SEQ)
+#define BIT_CLEAR_FREE_TXPG_SEQ(x) ((x) & (~BITS_FREE_TXPG_SEQ))
+#define BIT_GET_FREE_TXPG_SEQ(x) \
+ (((x) >> BIT_SHIFT_FREE_TXPG_SEQ) & BIT_MASK_FREE_TXPG_SEQ)
+#define BIT_SET_FREE_TXPG_SEQ(x, v) \
+ (BIT_CLEAR_FREE_TXPG_SEQ(x) | BIT_FREE_TXPG_SEQ(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
-#define BIT_LPLDH12_RSV1 BIT(31)
-#define BIT_LPLDH12_RSV0 BIT(30)
+#define BIT_LPLDH12_RSV1 BIT(31)
+#define BIT_LPLDH12_RSV0 BIT(30)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
+#define BIT_SHIFT_LPLDH12_RSV 29
+#define BIT_MASK_LPLDH12_RSV 0x7
+#define BIT_LPLDH12_RSV(x) \
+ (((x) & BIT_MASK_LPLDH12_RSV) << BIT_SHIFT_LPLDH12_RSV)
+#define BITS_LPLDH12_RSV (BIT_MASK_LPLDH12_RSV << BIT_SHIFT_LPLDH12_RSV)
+#define BIT_CLEAR_LPLDH12_RSV(x) ((x) & (~BITS_LPLDH12_RSV))
+#define BIT_GET_LPLDH12_RSV(x) \
+ (((x) >> BIT_SHIFT_LPLDH12_RSV) & BIT_MASK_LPLDH12_RSV)
+#define BIT_SET_LPLDH12_RSV(x, v) \
+ (BIT_CLEAR_LPLDH12_RSV(x) | BIT_LPLDH12_RSV(v))
-/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
-#define BIT_SHIFT_LPLDH12_RSV 29
-#define BIT_MASK_LPLDH12_RSV 0x7
-#define BIT_LPLDH12_RSV(x) (((x) & BIT_MASK_LPLDH12_RSV) << BIT_SHIFT_LPLDH12_RSV)
-#define BIT_GET_LPLDH12_RSV(x) (((x) >> BIT_SHIFT_LPLDH12_RSV) & BIT_MASK_LPLDH12_RSV)
+#define BIT_LPLDH12_SLP BIT(28)
+#define BIT_SHIFT_LPLDH12_VADJ 24
+#define BIT_MASK_LPLDH12_VADJ 0xf
+#define BIT_LPLDH12_VADJ(x) \
+ (((x) & BIT_MASK_LPLDH12_VADJ) << BIT_SHIFT_LPLDH12_VADJ)
+#define BITS_LPLDH12_VADJ (BIT_MASK_LPLDH12_VADJ << BIT_SHIFT_LPLDH12_VADJ)
+#define BIT_CLEAR_LPLDH12_VADJ(x) ((x) & (~BITS_LPLDH12_VADJ))
+#define BIT_GET_LPLDH12_VADJ(x) \
+ (((x) >> BIT_SHIFT_LPLDH12_VADJ) & BIT_MASK_LPLDH12_VADJ)
+#define BIT_SET_LPLDH12_VADJ(x, v) \
+ (BIT_CLEAR_LPLDH12_VADJ(x) | BIT_LPLDH12_VADJ(v))
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
+#define BIT_PCIE_CALIB_EN BIT(17)
-/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
+#endif
-#define BIT_LPLDH12_SLP BIT(28)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_LPLDH12_VADJ 24
-#define BIT_MASK_LPLDH12_VADJ 0xf
-#define BIT_LPLDH12_VADJ(x) (((x) & BIT_MASK_LPLDH12_VADJ) << BIT_SHIFT_LPLDH12_VADJ)
-#define BIT_GET_LPLDH12_VADJ(x) (((x) >> BIT_SHIFT_LPLDH12_VADJ) & BIT_MASK_LPLDH12_VADJ)
+/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
+#define BIT_LDH12_EN BIT(16)
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT)
+/* 2 REG_SDIO_FREE_TXPG (Offset 0x10250020) */
+
+#define BIT_SHIFT_MID_FREEPG_V1 16
+#define BIT_MASK_MID_FREEPG_V1 0xfff
+#define BIT_MID_FREEPG_V1(x) \
+ (((x) & BIT_MASK_MID_FREEPG_V1) << BIT_SHIFT_MID_FREEPG_V1)
+#define BITS_MID_FREEPG_V1 (BIT_MASK_MID_FREEPG_V1 << BIT_SHIFT_MID_FREEPG_V1)
+#define BIT_CLEAR_MID_FREEPG_V1(x) ((x) & (~BITS_MID_FREEPG_V1))
+#define BIT_GET_MID_FREEPG_V1(x) \
+ (((x) >> BIT_SHIFT_MID_FREEPG_V1) & BIT_MASK_MID_FREEPG_V1)
+#define BIT_SET_MID_FREEPG_V1(x, v) \
+ (BIT_CLEAR_MID_FREEPG_V1(x) | BIT_MID_FREEPG_V1(v))
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
-#define BIT_PCIE_CALIB_EN BIT(17)
+#define BIT_WLBBOFF_BIG_PWC_EN BIT(14)
+#define BIT_WLBBOFF_SMALL_PWC_EN BIT(13)
#endif
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
+
+#define BIT_POW_REGU_P3 BIT(12)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
-#define BIT_LDH12_EN BIT(16)
+#define BIT_WLMACOFF_BIG_PWC_EN BIT(12)
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
+#define BIT_POW_REGU_P2 BIT(11)
-/* 2 REG_SDIO_FREE_TXPG (Offset 0x10250020) */
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_MID_FREEPG_V1 16
-#define BIT_MASK_MID_FREEPG_V1 0xfff
-#define BIT_MID_FREEPG_V1(x) (((x) & BIT_MASK_MID_FREEPG_V1) << BIT_SHIFT_MID_FREEPG_V1)
-#define BIT_GET_MID_FREEPG_V1(x) (((x) >> BIT_SHIFT_MID_FREEPG_V1) & BIT_MASK_MID_FREEPG_V1)
+/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
+#define BIT_WLPON_PWC_EN BIT(11)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
+#define BIT_POW_REGU_P1 BIT(10)
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
-#define BIT_WLBBOFF_BIG_PWC_EN BIT(14)
-#define BIT_WLBBOFF_SMALL_PWC_EN BIT(13)
-#define BIT_WLMACOFF_BIG_PWC_EN BIT(12)
-#define BIT_WLPON_PWC_EN BIT(11)
+#define BIT_R_SYM_WLBBOFF1_P4_EN BIT(9)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
+
+#define BIT_LDOV12W_EN BIT(8)
+
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
-#define BIT_POW_REGU_P1 BIT(10)
+#define BIT_SHIFT_ANAPAR_RFC2 8
+#define BIT_MASK_ANAPAR_RFC2 0xff
+#define BIT_ANAPAR_RFC2(x) \
+ (((x) & BIT_MASK_ANAPAR_RFC2) << BIT_SHIFT_ANAPAR_RFC2)
+#define BITS_ANAPAR_RFC2 (BIT_MASK_ANAPAR_RFC2 << BIT_SHIFT_ANAPAR_RFC2)
+#define BIT_CLEAR_ANAPAR_RFC2(x) ((x) & (~BITS_ANAPAR_RFC2))
+#define BIT_GET_ANAPAR_RFC2(x) \
+ (((x) >> BIT_SHIFT_ANAPAR_RFC2) & BIT_MASK_ANAPAR_RFC2)
+#define BIT_SET_ANAPAR_RFC2(x, v) \
+ (BIT_CLEAR_ANAPAR_RFC2(x) | BIT_ANAPAR_RFC2(v))
#endif
+#if (HALMAC_8822C_SUPPORT)
+
+/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
+
+#define BIT_R_SYM_WLBBOFF1_P3_EN BIT(8)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
-#define BIT_LDOV12W_EN BIT(8)
+#define BIT_EX_XTAL_DRV_DIGI BIT(7)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
+#define BIT_R_SYM_WLBBOFF1_P2_EN BIT(7)
-/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_ANAPAR_RFC2 8
-#define BIT_MASK_ANAPAR_RFC2 0xff
-#define BIT_ANAPAR_RFC2(x) (((x) & BIT_MASK_ANAPAR_RFC2) << BIT_SHIFT_ANAPAR_RFC2)
-#define BIT_GET_ANAPAR_RFC2(x) (((x) >> BIT_SHIFT_ANAPAR_RFC2) & BIT_MASK_ANAPAR_RFC2)
+/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
+#define BIT_EX_XTAL_DRV_USB BIT(6)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
+#define BIT_R_SYM_WLBBOFF1_P1_EN BIT(6)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
-#define BIT_EX_XTAL_DRV_DIGI BIT(7)
-#define BIT_EX_XTAL_DRV_USB BIT(6)
-#define BIT_EX_XTAL_DRV_AFE BIT(5)
+#define BIT_EX_XTAL_DRV_AFE BIT(5)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
+#define BIT_SHIFT_LDA12_VOADJ 4
+#define BIT_MASK_LDA12_VOADJ 0xf
+#define BIT_LDA12_VOADJ(x) \
+ (((x) & BIT_MASK_LDA12_VOADJ) << BIT_SHIFT_LDA12_VOADJ)
+#define BITS_LDA12_VOADJ (BIT_MASK_LDA12_VOADJ << BIT_SHIFT_LDA12_VOADJ)
+#define BIT_CLEAR_LDA12_VOADJ(x) ((x) & (~BITS_LDA12_VOADJ))
+#define BIT_GET_LDA12_VOADJ(x) \
+ (((x) >> BIT_SHIFT_LDA12_VOADJ) & BIT_MASK_LDA12_VOADJ)
+#define BIT_SET_LDA12_VOADJ(x, v) \
+ (BIT_CLEAR_LDA12_VOADJ(x) | BIT_LDA12_VOADJ(v))
-#define BIT_SHIFT_LDA12_VOADJ 4
-#define BIT_MASK_LDA12_VOADJ 0xf
-#define BIT_LDA12_VOADJ(x) (((x) & BIT_MASK_LDA12_VOADJ) << BIT_SHIFT_LDA12_VOADJ)
-#define BIT_GET_LDA12_VOADJ(x) (((x) >> BIT_SHIFT_LDA12_VOADJ) & BIT_MASK_LDA12_VOADJ)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
-#endif
+/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
+#define BIT_EX_XTAL_DRV_RF2 BIT(4)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8822C_SUPPORT)
/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
-#define BIT_EX_XTAL_DRV_RF2 BIT(4)
+#define BIT_R_SYM_WLBBOFF_P4_EN BIT(4)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
-#define BIT_REG_VOS BIT(3)
+#define BIT_REG_VOS BIT(3)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
-#define BIT_EX_XTAL_DRV_RF1 BIT(3)
-#define BIT_POW_REGU_P0 BIT(2)
+#define BIT_EX_XTAL_DRV_RF1 BIT(3)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
+
+#define BIT_R_SYM_WLBBOFF_P3_EN BIT(3)
+
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
-#define BIT_LDA12_EN BIT(0)
+#define BIT_POW_REGU_P0 BIT(2)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
+
+#define BIT_R_SYM_WLBBOFF_P2_EN BIT(2)
+#define BIT_R_SYM_WLBBOFF_P1_EN BIT(1)
+
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
-#define BIT_POW_PLL_LDO BIT(0)
+#define BIT_LDA12_EN BIT(0)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
+#define BIT_POW_PLL_LDO BIT(0)
-/* 2 REG_SDIO_FREE_TXPG (Offset 0x10250020) */
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_HIQ_FREEPG_V1 0
-#define BIT_MASK_HIQ_FREEPG_V1 0xfff
-#define BIT_HIQ_FREEPG_V1(x) (((x) & BIT_MASK_HIQ_FREEPG_V1) << BIT_SHIFT_HIQ_FREEPG_V1)
-#define BIT_GET_HIQ_FREEPG_V1(x) (((x) >> BIT_SHIFT_HIQ_FREEPG_V1) & BIT_MASK_HIQ_FREEPG_V1)
+/* 2 REG_SDIO_FREE_TXPG (Offset 0x10250020) */
+#define BIT_SHIFT_HIQ_FREEPG_V1 0
+#define BIT_MASK_HIQ_FREEPG_V1 0xfff
+#define BIT_HIQ_FREEPG_V1(x) \
+ (((x) & BIT_MASK_HIQ_FREEPG_V1) << BIT_SHIFT_HIQ_FREEPG_V1)
+#define BITS_HIQ_FREEPG_V1 (BIT_MASK_HIQ_FREEPG_V1 << BIT_SHIFT_HIQ_FREEPG_V1)
+#define BIT_CLEAR_HIQ_FREEPG_V1(x) ((x) & (~BITS_HIQ_FREEPG_V1))
+#define BIT_GET_HIQ_FREEPG_V1(x) \
+ (((x) >> BIT_SHIFT_HIQ_FREEPG_V1) & BIT_MASK_HIQ_FREEPG_V1)
+#define BIT_SET_HIQ_FREEPG_V1(x, v) \
+ (BIT_CLEAR_HIQ_FREEPG_V1(x) | BIT_HIQ_FREEPG_V1(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
+#define BIT_SHIFT_ANAPAR_RFC1 0
+#define BIT_MASK_ANAPAR_RFC1 0xff
+#define BIT_ANAPAR_RFC1(x) \
+ (((x) & BIT_MASK_ANAPAR_RFC1) << BIT_SHIFT_ANAPAR_RFC1)
+#define BITS_ANAPAR_RFC1 (BIT_MASK_ANAPAR_RFC1 << BIT_SHIFT_ANAPAR_RFC1)
+#define BIT_CLEAR_ANAPAR_RFC1(x) ((x) & (~BITS_ANAPAR_RFC1))
+#define BIT_GET_ANAPAR_RFC1(x) \
+ (((x) >> BIT_SHIFT_ANAPAR_RFC1) & BIT_MASK_ANAPAR_RFC1)
+#define BIT_SET_ANAPAR_RFC1(x, v) \
+ (BIT_CLEAR_ANAPAR_RFC1(x) | BIT_ANAPAR_RFC1(v))
-#define BIT_SHIFT_ANAPAR_RFC1 0
-#define BIT_MASK_ANAPAR_RFC1 0xff
-#define BIT_ANAPAR_RFC1(x) (((x) & BIT_MASK_ANAPAR_RFC1) << BIT_SHIFT_ANAPAR_RFC1)
-#define BIT_GET_ANAPAR_RFC1(x) (((x) >> BIT_SHIFT_ANAPAR_RFC1) & BIT_MASK_ANAPAR_RFC1)
+#endif
+#if (HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */
+#define BIT_R_SYM_WLBBOFF_EN BIT(0)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-#define BIT_AGPIO_GPE BIT(31)
+#define BIT_AGPIO_GPE BIT(31)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-#define BIT_XQSEL_V3 BIT(31)
+#define BIT_XQSEL_V3 BIT(31)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_SHIFT_REG_CC 30
-#define BIT_MASK_REG_CC 0x3
-#define BIT_REG_CC(x) (((x) & BIT_MASK_REG_CC) << BIT_SHIFT_REG_CC)
-#define BIT_GET_REG_CC(x) (((x) >> BIT_SHIFT_REG_CC) & BIT_MASK_REG_CC)
-
+#define BIT_SHIFT_REG_CC 30
+#define BIT_MASK_REG_CC 0x3
+#define BIT_REG_CC(x) (((x) & BIT_MASK_REG_CC) << BIT_SHIFT_REG_CC)
+#define BITS_REG_CC (BIT_MASK_REG_CC << BIT_SHIFT_REG_CC)
+#define BIT_CLEAR_REG_CC(x) ((x) & (~BITS_REG_CC))
+#define BIT_GET_REG_CC(x) (((x) >> BIT_SHIFT_REG_CC) & BIT_MASK_REG_CC)
+#define BIT_SET_REG_CC(x, v) (BIT_CLEAR_REG_CC(x) | BIT_REG_CC(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-#define BIT_CKDELAY_AFE_V1 BIT(30)
+#define BIT_CKDELAY_AFE_V1 BIT(30)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-#define BIT_CKDLY_DIG BIT(28)
-#define BIT_CKDLY_USB BIT(27)
+#define BIT_CKDLY_DIG BIT(28)
+#define BIT_CKDLY_USB BIT(27)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_SHIFT_XTAL_GPIO_V1 27
-#define BIT_MASK_XTAL_GPIO_V1 0x7
-#define BIT_XTAL_GPIO_V1(x) (((x) & BIT_MASK_XTAL_GPIO_V1) << BIT_SHIFT_XTAL_GPIO_V1)
-#define BIT_GET_XTAL_GPIO_V1(x) (((x) >> BIT_SHIFT_XTAL_GPIO_V1) & BIT_MASK_XTAL_GPIO_V1)
-
+#define BIT_SHIFT_XTAL_GPIO_V1 27
+#define BIT_MASK_XTAL_GPIO_V1 0x7
+#define BIT_XTAL_GPIO_V1(x) \
+ (((x) & BIT_MASK_XTAL_GPIO_V1) << BIT_SHIFT_XTAL_GPIO_V1)
+#define BITS_XTAL_GPIO_V1 (BIT_MASK_XTAL_GPIO_V1 << BIT_SHIFT_XTAL_GPIO_V1)
+#define BIT_CLEAR_XTAL_GPIO_V1(x) ((x) & (~BITS_XTAL_GPIO_V1))
+#define BIT_GET_XTAL_GPIO_V1(x) \
+ (((x) >> BIT_SHIFT_XTAL_GPIO_V1) & BIT_MASK_XTAL_GPIO_V1)
+#define BIT_SET_XTAL_GPIO_V1(x, v) \
+ (BIT_CLEAR_XTAL_GPIO_V1(x) | BIT_XTAL_GPIO_V1(v))
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-#define BIT_CKDLY_AFE BIT(26)
+#define BIT_CKDLY_AFE BIT(26)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_SHIFT_XTAL_CAP_XI 25
-#define BIT_MASK_XTAL_CAP_XI 0x3f
-#define BIT_XTAL_CAP_XI(x) (((x) & BIT_MASK_XTAL_CAP_XI) << BIT_SHIFT_XTAL_CAP_XI)
-#define BIT_GET_XTAL_CAP_XI(x) (((x) >> BIT_SHIFT_XTAL_CAP_XI) & BIT_MASK_XTAL_CAP_XI)
-
+#define BIT_SHIFT_XTAL_CAP_XI 25
+#define BIT_MASK_XTAL_CAP_XI 0x3f
+#define BIT_XTAL_CAP_XI(x) \
+ (((x) & BIT_MASK_XTAL_CAP_XI) << BIT_SHIFT_XTAL_CAP_XI)
+#define BITS_XTAL_CAP_XI (BIT_MASK_XTAL_CAP_XI << BIT_SHIFT_XTAL_CAP_XI)
+#define BIT_CLEAR_XTAL_CAP_XI(x) ((x) & (~BITS_XTAL_CAP_XI))
+#define BIT_GET_XTAL_CAP_XI(x) \
+ (((x) >> BIT_SHIFT_XTAL_CAP_XI) & BIT_MASK_XTAL_CAP_XI)
+#define BIT_SET_XTAL_CAP_XI(x, v) \
+ (BIT_CLEAR_XTAL_CAP_XI(x) | BIT_XTAL_CAP_XI(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
+#define BIT_SHIFT_XTAL_DIG_DRV_1_TO_0 25
+#define BIT_MASK_XTAL_DIG_DRV_1_TO_0 0x3
+#define BIT_XTAL_DIG_DRV_1_TO_0(x) \
+ (((x) & BIT_MASK_XTAL_DIG_DRV_1_TO_0) << BIT_SHIFT_XTAL_DIG_DRV_1_TO_0)
+#define BITS_XTAL_DIG_DRV_1_TO_0 \
+ (BIT_MASK_XTAL_DIG_DRV_1_TO_0 << BIT_SHIFT_XTAL_DIG_DRV_1_TO_0)
+#define BIT_CLEAR_XTAL_DIG_DRV_1_TO_0(x) ((x) & (~BITS_XTAL_DIG_DRV_1_TO_0))
+#define BIT_GET_XTAL_DIG_DRV_1_TO_0(x) \
+ (((x) >> BIT_SHIFT_XTAL_DIG_DRV_1_TO_0) & BIT_MASK_XTAL_DIG_DRV_1_TO_0)
+#define BIT_SET_XTAL_DIG_DRV_1_TO_0(x, v) \
+ (BIT_CLEAR_XTAL_DIG_DRV_1_TO_0(x) | BIT_XTAL_DIG_DRV_1_TO_0(v))
-#define BIT_SHIFT_XTAL_DIG_DRV_1_TO_0 25
-#define BIT_MASK_XTAL_DIG_DRV_1_TO_0 0x3
-#define BIT_XTAL_DIG_DRV_1_TO_0(x) (((x) & BIT_MASK_XTAL_DIG_DRV_1_TO_0) << BIT_SHIFT_XTAL_DIG_DRV_1_TO_0)
-#define BIT_GET_XTAL_DIG_DRV_1_TO_0(x) (((x) >> BIT_SHIFT_XTAL_DIG_DRV_1_TO_0) & BIT_MASK_XTAL_DIG_DRV_1_TO_0)
-
-#define BIT_XTAL_GDIG BIT(24)
+#define BIT_XTAL_GDIG BIT(24)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
+#define BIT_SHIFT_XTAL_GPIO 23
+#define BIT_MASK_XTAL_GPIO 0x7
+#define BIT_XTAL_GPIO(x) (((x) & BIT_MASK_XTAL_GPIO) << BIT_SHIFT_XTAL_GPIO)
+#define BITS_XTAL_GPIO (BIT_MASK_XTAL_GPIO << BIT_SHIFT_XTAL_GPIO)
+#define BIT_CLEAR_XTAL_GPIO(x) ((x) & (~BITS_XTAL_GPIO))
+#define BIT_GET_XTAL_GPIO(x) (((x) >> BIT_SHIFT_XTAL_GPIO) & BIT_MASK_XTAL_GPIO)
+#define BIT_SET_XTAL_GPIO(x, v) (BIT_CLEAR_XTAL_GPIO(x) | BIT_XTAL_GPIO(v))
-#define BIT_SHIFT_XTAL_GPIO 23
-#define BIT_MASK_XTAL_GPIO 0x7
-#define BIT_XTAL_GPIO(x) (((x) & BIT_MASK_XTAL_GPIO) << BIT_SHIFT_XTAL_GPIO)
-#define BIT_GET_XTAL_GPIO(x) (((x) >> BIT_SHIFT_XTAL_GPIO) & BIT_MASK_XTAL_GPIO)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
-#endif
-
+/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#define BIT_SHIFT_XTAL_DRV_DIGI 23
+#define BIT_MASK_XTAL_DRV_DIGI 0x3
+#define BIT_XTAL_DRV_DIGI(x) \
+ (((x) & BIT_MASK_XTAL_DRV_DIGI) << BIT_SHIFT_XTAL_DRV_DIGI)
+#define BITS_XTAL_DRV_DIGI (BIT_MASK_XTAL_DRV_DIGI << BIT_SHIFT_XTAL_DRV_DIGI)
+#define BIT_CLEAR_XTAL_DRV_DIGI(x) ((x) & (~BITS_XTAL_DRV_DIGI))
+#define BIT_GET_XTAL_DRV_DIGI(x) \
+ (((x) >> BIT_SHIFT_XTAL_DRV_DIGI) & BIT_MASK_XTAL_DRV_DIGI)
+#define BIT_SET_XTAL_DRV_DIGI(x, v) \
+ (BIT_CLEAR_XTAL_DRV_DIGI(x) | BIT_XTAL_DRV_DIGI(v))
+#define BIT_XTAL_DRV_USB_BIT1 BIT(22)
-/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
+#endif
+#if (HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_XTAL_DRV_DIGI 23
-#define BIT_MASK_XTAL_DRV_DIGI 0x3
-#define BIT_XTAL_DRV_DIGI(x) (((x) & BIT_MASK_XTAL_DRV_DIGI) << BIT_SHIFT_XTAL_DRV_DIGI)
-#define BIT_GET_XTAL_DRV_DIGI(x) (((x) >> BIT_SHIFT_XTAL_DRV_DIGI) & BIT_MASK_XTAL_DRV_DIGI)
+/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-#define BIT_XTAL_DRV_USB_BIT1 BIT(22)
+#define BIT_XTAL_DRV_RF_LATCH_V2 BIT(22)
#endif
-
#if (HALMAC_8814A_SUPPORT)
-
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_SHIFT_XTAL_RDRV_RF2_1_TO_0 22
-#define BIT_MASK_XTAL_RDRV_RF2_1_TO_0 0x3
-#define BIT_XTAL_RDRV_RF2_1_TO_0(x) (((x) & BIT_MASK_XTAL_RDRV_RF2_1_TO_0) << BIT_SHIFT_XTAL_RDRV_RF2_1_TO_0)
-#define BIT_GET_XTAL_RDRV_RF2_1_TO_0(x) (((x) >> BIT_SHIFT_XTAL_RDRV_RF2_1_TO_0) & BIT_MASK_XTAL_RDRV_RF2_1_TO_0)
-
+#define BIT_SHIFT_XTAL_RDRV_RF2_1_TO_0 22
+#define BIT_MASK_XTAL_RDRV_RF2_1_TO_0 0x3
+#define BIT_XTAL_RDRV_RF2_1_TO_0(x) \
+ (((x) & BIT_MASK_XTAL_RDRV_RF2_1_TO_0) \
+ << BIT_SHIFT_XTAL_RDRV_RF2_1_TO_0)
+#define BITS_XTAL_RDRV_RF2_1_TO_0 \
+ (BIT_MASK_XTAL_RDRV_RF2_1_TO_0 << BIT_SHIFT_XTAL_RDRV_RF2_1_TO_0)
+#define BIT_CLEAR_XTAL_RDRV_RF2_1_TO_0(x) ((x) & (~BITS_XTAL_RDRV_RF2_1_TO_0))
+#define BIT_GET_XTAL_RDRV_RF2_1_TO_0(x) \
+ (((x) >> BIT_SHIFT_XTAL_RDRV_RF2_1_TO_0) & \
+ BIT_MASK_XTAL_RDRV_RF2_1_TO_0)
+#define BIT_SET_XTAL_RDRV_RF2_1_TO_0(x, v) \
+ (BIT_CLEAR_XTAL_RDRV_RF2_1_TO_0(x) | BIT_XTAL_RDRV_RF2_1_TO_0(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-#define BIT_XTAL_GMN_4 BIT(21)
+#define BIT_XTAL_GMN_4 BIT(21)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_SHIFT_MAC_CLK_SEL 20
-#define BIT_MASK_MAC_CLK_SEL 0x3
-#define BIT_MAC_CLK_SEL(x) (((x) & BIT_MASK_MAC_CLK_SEL) << BIT_SHIFT_MAC_CLK_SEL)
-#define BIT_GET_MAC_CLK_SEL(x) (((x) >> BIT_SHIFT_MAC_CLK_SEL) & BIT_MASK_MAC_CLK_SEL)
-
+#define BIT_SHIFT_MAC_CLK_SEL 20
+#define BIT_MASK_MAC_CLK_SEL 0x3
+#define BIT_MAC_CLK_SEL(x) \
+ (((x) & BIT_MASK_MAC_CLK_SEL) << BIT_SHIFT_MAC_CLK_SEL)
+#define BITS_MAC_CLK_SEL (BIT_MASK_MAC_CLK_SEL << BIT_SHIFT_MAC_CLK_SEL)
+#define BIT_CLEAR_MAC_CLK_SEL(x) ((x) & (~BITS_MAC_CLK_SEL))
+#define BIT_GET_MAC_CLK_SEL(x) \
+ (((x) >> BIT_SHIFT_MAC_CLK_SEL) & BIT_MASK_MAC_CLK_SEL)
+#define BIT_SET_MAC_CLK_SEL(x, v) \
+ (BIT_CLEAR_MAC_CLK_SEL(x) | BIT_MAC_CLK_SEL(v))
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-#define BIT_XTAL_DRV_USB_BIT0 BIT(19)
+#define BIT_XTAL_DRV_USB_BIT0 BIT(19)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_SHIFT_XTAL_RDRV_1_TO_0 19
-#define BIT_MASK_XTAL_RDRV_1_TO_0 0x3
-#define BIT_XTAL_RDRV_1_TO_0(x) (((x) & BIT_MASK_XTAL_RDRV_1_TO_0) << BIT_SHIFT_XTAL_RDRV_1_TO_0)
-#define BIT_GET_XTAL_RDRV_1_TO_0(x) (((x) >> BIT_SHIFT_XTAL_RDRV_1_TO_0) & BIT_MASK_XTAL_RDRV_1_TO_0)
-
+#define BIT_SHIFT_XTAL_RDRV_1_TO_0 19
+#define BIT_MASK_XTAL_RDRV_1_TO_0 0x3
+#define BIT_XTAL_RDRV_1_TO_0(x) \
+ (((x) & BIT_MASK_XTAL_RDRV_1_TO_0) << BIT_SHIFT_XTAL_RDRV_1_TO_0)
+#define BITS_XTAL_RDRV_1_TO_0 \
+ (BIT_MASK_XTAL_RDRV_1_TO_0 << BIT_SHIFT_XTAL_RDRV_1_TO_0)
+#define BIT_CLEAR_XTAL_RDRV_1_TO_0(x) ((x) & (~BITS_XTAL_RDRV_1_TO_0))
+#define BIT_GET_XTAL_RDRV_1_TO_0(x) \
+ (((x) >> BIT_SHIFT_XTAL_RDRV_1_TO_0) & BIT_MASK_XTAL_RDRV_1_TO_0)
+#define BIT_SET_XTAL_RDRV_1_TO_0(x, v) \
+ (BIT_CLEAR_XTAL_RDRV_1_TO_0(x) | BIT_XTAL_RDRV_1_TO_0(v))
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_SHIFT_XTAL_DIG_DRV 18
-#define BIT_MASK_XTAL_DIG_DRV 0x3
-#define BIT_XTAL_DIG_DRV(x) (((x) & BIT_MASK_XTAL_DIG_DRV) << BIT_SHIFT_XTAL_DIG_DRV)
-#define BIT_GET_XTAL_DIG_DRV(x) (((x) >> BIT_SHIFT_XTAL_DIG_DRV) & BIT_MASK_XTAL_DIG_DRV)
-
+#define BIT_SHIFT_XTAL_DIG_DRV 18
+#define BIT_MASK_XTAL_DIG_DRV 0x3
+#define BIT_XTAL_DIG_DRV(x) \
+ (((x) & BIT_MASK_XTAL_DIG_DRV) << BIT_SHIFT_XTAL_DIG_DRV)
+#define BITS_XTAL_DIG_DRV (BIT_MASK_XTAL_DIG_DRV << BIT_SHIFT_XTAL_DIG_DRV)
+#define BIT_CLEAR_XTAL_DIG_DRV(x) ((x) & (~BITS_XTAL_DIG_DRV))
+#define BIT_GET_XTAL_DIG_DRV(x) \
+ (((x) >> BIT_SHIFT_XTAL_DIG_DRV) & BIT_MASK_XTAL_DIG_DRV)
+#define BIT_SET_XTAL_DIG_DRV(x, v) \
+ (BIT_CLEAR_XTAL_DIG_DRV(x) | BIT_XTAL_DIG_DRV(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-#define BIT_XTAL_GMP_4 BIT(18)
+#define BIT_XTAL_GMP_4 BIT(18)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-#define BIT_XTAL_GATE_DIG BIT(17)
+#define BIT_XTAL_GATE_DIG BIT(17)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_SHIFT_XTAL_DRV_AFE 17
-#define BIT_MASK_XTAL_DRV_AFE 0x3
-#define BIT_XTAL_DRV_AFE(x) (((x) & BIT_MASK_XTAL_DRV_AFE) << BIT_SHIFT_XTAL_DRV_AFE)
-#define BIT_GET_XTAL_DRV_AFE(x) (((x) >> BIT_SHIFT_XTAL_DRV_AFE) & BIT_MASK_XTAL_DRV_AFE)
-
+#define BIT_SHIFT_XTAL_DRV_AFE 17
+#define BIT_MASK_XTAL_DRV_AFE 0x3
+#define BIT_XTAL_DRV_AFE(x) \
+ (((x) & BIT_MASK_XTAL_DRV_AFE) << BIT_SHIFT_XTAL_DRV_AFE)
+#define BITS_XTAL_DRV_AFE (BIT_MASK_XTAL_DRV_AFE << BIT_SHIFT_XTAL_DRV_AFE)
+#define BIT_CLEAR_XTAL_DRV_AFE(x) ((x) & (~BITS_XTAL_DRV_AFE))
+#define BIT_GET_XTAL_DRV_AFE(x) \
+ (((x) >> BIT_SHIFT_XTAL_DRV_AFE) & BIT_MASK_XTAL_DRV_AFE)
+#define BIT_SET_XTAL_DRV_AFE(x, v) \
+ (BIT_CLEAR_XTAL_DRV_AFE(x) | BIT_XTAL_DRV_AFE(v))
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_FREE_TXPG2 (Offset 0x10250024) */
-
-#define BIT_SHIFT_PUB_FREEPG_V1 16
-#define BIT_MASK_PUB_FREEPG_V1 0xfff
-#define BIT_PUB_FREEPG_V1(x) (((x) & BIT_MASK_PUB_FREEPG_V1) << BIT_SHIFT_PUB_FREEPG_V1)
-#define BIT_GET_PUB_FREEPG_V1(x) (((x) >> BIT_SHIFT_PUB_FREEPG_V1) & BIT_MASK_PUB_FREEPG_V1)
-
+#define BIT_SHIFT_PUB_FREEPG_V1 16
+#define BIT_MASK_PUB_FREEPG_V1 0xfff
+#define BIT_PUB_FREEPG_V1(x) \
+ (((x) & BIT_MASK_PUB_FREEPG_V1) << BIT_SHIFT_PUB_FREEPG_V1)
+#define BITS_PUB_FREEPG_V1 (BIT_MASK_PUB_FREEPG_V1 << BIT_SHIFT_PUB_FREEPG_V1)
+#define BIT_CLEAR_PUB_FREEPG_V1(x) ((x) & (~BITS_PUB_FREEPG_V1))
+#define BIT_GET_PUB_FREEPG_V1(x) \
+ (((x) >> BIT_SHIFT_PUB_FREEPG_V1) & BIT_MASK_PUB_FREEPG_V1)
+#define BIT_SET_PUB_FREEPG_V1(x, v) \
+ (BIT_CLEAR_PUB_FREEPG_V1(x) | BIT_PUB_FREEPG_V1(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_SHIFT_XTAL_ADRV_1_TO_0 16
-#define BIT_MASK_XTAL_ADRV_1_TO_0 0x3
-#define BIT_XTAL_ADRV_1_TO_0(x) (((x) & BIT_MASK_XTAL_ADRV_1_TO_0) << BIT_SHIFT_XTAL_ADRV_1_TO_0)
-#define BIT_GET_XTAL_ADRV_1_TO_0(x) (((x) >> BIT_SHIFT_XTAL_ADRV_1_TO_0) & BIT_MASK_XTAL_ADRV_1_TO_0)
-
+#define BIT_SHIFT_XTAL_ADRV_1_TO_0 16
+#define BIT_MASK_XTAL_ADRV_1_TO_0 0x3
+#define BIT_XTAL_ADRV_1_TO_0(x) \
+ (((x) & BIT_MASK_XTAL_ADRV_1_TO_0) << BIT_SHIFT_XTAL_ADRV_1_TO_0)
+#define BITS_XTAL_ADRV_1_TO_0 \
+ (BIT_MASK_XTAL_ADRV_1_TO_0 << BIT_SHIFT_XTAL_ADRV_1_TO_0)
+#define BIT_CLEAR_XTAL_ADRV_1_TO_0(x) ((x) & (~BITS_XTAL_ADRV_1_TO_0))
+#define BIT_GET_XTAL_ADRV_1_TO_0(x) \
+ (((x) >> BIT_SHIFT_XTAL_ADRV_1_TO_0) & BIT_MASK_XTAL_ADRV_1_TO_0)
+#define BIT_SET_XTAL_ADRV_1_TO_0(x, v) \
+ (BIT_CLEAR_XTAL_ADRV_1_TO_0(x) | BIT_XTAL_ADRV_1_TO_0(v))
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_SHIFT_XTAL_RF_DRV 15
-#define BIT_MASK_XTAL_RF_DRV 0x3
-#define BIT_XTAL_RF_DRV(x) (((x) & BIT_MASK_XTAL_RF_DRV) << BIT_SHIFT_XTAL_RF_DRV)
-#define BIT_GET_XTAL_RF_DRV(x) (((x) >> BIT_SHIFT_XTAL_RF_DRV) & BIT_MASK_XTAL_RF_DRV)
-
+#define BIT_SHIFT_XTAL_RF_DRV 15
+#define BIT_MASK_XTAL_RF_DRV 0x3
+#define BIT_XTAL_RF_DRV(x) \
+ (((x) & BIT_MASK_XTAL_RF_DRV) << BIT_SHIFT_XTAL_RF_DRV)
+#define BITS_XTAL_RF_DRV (BIT_MASK_XTAL_RF_DRV << BIT_SHIFT_XTAL_RF_DRV)
+#define BIT_CLEAR_XTAL_RF_DRV(x) ((x) & (~BITS_XTAL_RF_DRV))
+#define BIT_GET_XTAL_RF_DRV(x) \
+ (((x) >> BIT_SHIFT_XTAL_RF_DRV) & BIT_MASK_XTAL_RF_DRV)
+#define BIT_SET_XTAL_RF_DRV(x, v) \
+ (BIT_CLEAR_XTAL_RF_DRV(x) | BIT_XTAL_RF_DRV(v))
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_SHIFT_XTAL_DRV_RF2 15
-#define BIT_MASK_XTAL_DRV_RF2 0x3
-#define BIT_XTAL_DRV_RF2(x) (((x) & BIT_MASK_XTAL_DRV_RF2) << BIT_SHIFT_XTAL_DRV_RF2)
-#define BIT_GET_XTAL_DRV_RF2(x) (((x) >> BIT_SHIFT_XTAL_DRV_RF2) & BIT_MASK_XTAL_DRV_RF2)
-
+#define BIT_SHIFT_XTAL_DRV_RF2 15
+#define BIT_MASK_XTAL_DRV_RF2 0x3
+#define BIT_XTAL_DRV_RF2(x) \
+ (((x) & BIT_MASK_XTAL_DRV_RF2) << BIT_SHIFT_XTAL_DRV_RF2)
+#define BITS_XTAL_DRV_RF2 (BIT_MASK_XTAL_DRV_RF2 << BIT_SHIFT_XTAL_DRV_RF2)
+#define BIT_CLEAR_XTAL_DRV_RF2(x) ((x) & (~BITS_XTAL_DRV_RF2))
+#define BIT_GET_XTAL_DRV_RF2(x) \
+ (((x) >> BIT_SHIFT_XTAL_DRV_RF2) & BIT_MASK_XTAL_DRV_RF2)
+#define BIT_SET_XTAL_DRV_RF2(x, v) \
+ (BIT_CLEAR_XTAL_DRV_RF2(x) | BIT_XTAL_DRV_RF2(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-#define BIT_XTAL_GAFE BIT(15)
+#define BIT_XTAL_GAFE BIT(15)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_XTAL_RF_GATE BIT(14)
-
-#endif
-
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_SHIFT_XTAL_DRV_RF1 13
-#define BIT_MASK_XTAL_DRV_RF1 0x3
-#define BIT_XTAL_DRV_RF1(x) (((x) & BIT_MASK_XTAL_DRV_RF1) << BIT_SHIFT_XTAL_DRV_RF1)
-#define BIT_GET_XTAL_DRV_RF1(x) (((x) >> BIT_SHIFT_XTAL_DRV_RF1) & BIT_MASK_XTAL_DRV_RF1)
-
+#define BIT_XTAL_RF_GATE BIT(14)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_SHIFT_XTAL_DDRV_1_TO_0 13
-#define BIT_MASK_XTAL_DDRV_1_TO_0 0x3
-#define BIT_XTAL_DDRV_1_TO_0(x) (((x) & BIT_MASK_XTAL_DDRV_1_TO_0) << BIT_SHIFT_XTAL_DDRV_1_TO_0)
-#define BIT_GET_XTAL_DDRV_1_TO_0(x) (((x) >> BIT_SHIFT_XTAL_DDRV_1_TO_0) & BIT_MASK_XTAL_DDRV_1_TO_0)
-
+#define BIT_SHIFT_XTAL_DDRV_1_TO_0 13
+#define BIT_MASK_XTAL_DDRV_1_TO_0 0x3
+#define BIT_XTAL_DDRV_1_TO_0(x) \
+ (((x) & BIT_MASK_XTAL_DDRV_1_TO_0) << BIT_SHIFT_XTAL_DDRV_1_TO_0)
+#define BITS_XTAL_DDRV_1_TO_0 \
+ (BIT_MASK_XTAL_DDRV_1_TO_0 << BIT_SHIFT_XTAL_DDRV_1_TO_0)
+#define BIT_CLEAR_XTAL_DDRV_1_TO_0(x) ((x) & (~BITS_XTAL_DDRV_1_TO_0))
+#define BIT_GET_XTAL_DDRV_1_TO_0(x) \
+ (((x) >> BIT_SHIFT_XTAL_DDRV_1_TO_0) & BIT_MASK_XTAL_DDRV_1_TO_0)
+#define BIT_SET_XTAL_DDRV_1_TO_0(x, v) \
+ (BIT_CLEAR_XTAL_DDRV_1_TO_0(x) | BIT_XTAL_DDRV_1_TO_0(v))
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_SHIFT_XTAL_AFE_DRV 12
-#define BIT_MASK_XTAL_AFE_DRV 0x3
-#define BIT_XTAL_AFE_DRV(x) (((x) & BIT_MASK_XTAL_AFE_DRV) << BIT_SHIFT_XTAL_AFE_DRV)
-#define BIT_GET_XTAL_AFE_DRV(x) (((x) >> BIT_SHIFT_XTAL_AFE_DRV) & BIT_MASK_XTAL_AFE_DRV)
-
+#define BIT_SHIFT_XTAL_AFE_DRV 12
+#define BIT_MASK_XTAL_AFE_DRV 0x3
+#define BIT_XTAL_AFE_DRV(x) \
+ (((x) & BIT_MASK_XTAL_AFE_DRV) << BIT_SHIFT_XTAL_AFE_DRV)
+#define BITS_XTAL_AFE_DRV (BIT_MASK_XTAL_AFE_DRV << BIT_SHIFT_XTAL_AFE_DRV)
+#define BIT_CLEAR_XTAL_AFE_DRV(x) ((x) & (~BITS_XTAL_AFE_DRV))
+#define BIT_GET_XTAL_AFE_DRV(x) \
+ (((x) >> BIT_SHIFT_XTAL_AFE_DRV) & BIT_MASK_XTAL_AFE_DRV)
+#define BIT_SET_XTAL_AFE_DRV(x, v) \
+ (BIT_CLEAR_XTAL_AFE_DRV(x) | BIT_XTAL_AFE_DRV(v))
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-#define BIT_XTAL_DELAY_DIGI BIT(12)
+#define BIT_XTAL_DELAY_DIGI BIT(12)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-#define BIT_XTAL_GUSB BIT(12)
+#define BIT_XTAL_GUSB BIT(12)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-#define BIT_XTAL_GATE_AFE BIT(11)
+#define BIT_XTAL_GATE_AFE BIT(11)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-#define BIT_XTAL_DELAY_USB BIT(11)
-#define BIT_XTAL_DELAY_AFE BIT(10)
+#define BIT_XTAL_DELAY_USB BIT(11)
+#define BIT_XTAL_DELAY_AFE BIT(10)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_SHIFT_XTAL_USB_DRV 9
-#define BIT_MASK_XTAL_USB_DRV 0x3
-#define BIT_XTAL_USB_DRV(x) (((x) & BIT_MASK_XTAL_USB_DRV) << BIT_SHIFT_XTAL_USB_DRV)
-#define BIT_GET_XTAL_USB_DRV(x) (((x) >> BIT_SHIFT_XTAL_USB_DRV) & BIT_MASK_XTAL_USB_DRV)
-
+#define BIT_SHIFT_XTAL_USB_DRV 9
+#define BIT_MASK_XTAL_USB_DRV 0x3
+#define BIT_XTAL_USB_DRV(x) \
+ (((x) & BIT_MASK_XTAL_USB_DRV) << BIT_SHIFT_XTAL_USB_DRV)
+#define BITS_XTAL_USB_DRV (BIT_MASK_XTAL_USB_DRV << BIT_SHIFT_XTAL_USB_DRV)
+#define BIT_CLEAR_XTAL_USB_DRV(x) ((x) & (~BITS_XTAL_USB_DRV))
+#define BIT_GET_XTAL_USB_DRV(x) \
+ (((x) >> BIT_SHIFT_XTAL_USB_DRV) & BIT_MASK_XTAL_USB_DRV)
+#define BIT_SET_XTAL_USB_DRV(x, v) \
+ (BIT_CLEAR_XTAL_USB_DRV(x) | BIT_XTAL_USB_DRV(v))
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-#define BIT_XTAL_LP_V1 BIT(9)
+#define BIT_XTAL_LP_V1 BIT(9)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-#define BIT_XTAL_GATE_USB BIT(8)
+#define BIT_XTAL_GATE_USB BIT(8)
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-#define BIT_XTAL_GM_SEP_V1 BIT(8)
+#define BIT_XTAL_GM_SEP_V1 BIT(8)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_SHIFT_XTAL_GMN_3_TO_0 8
-#define BIT_MASK_XTAL_GMN_3_TO_0 0xf
-#define BIT_XTAL_GMN_3_TO_0(x) (((x) & BIT_MASK_XTAL_GMN_3_TO_0) << BIT_SHIFT_XTAL_GMN_3_TO_0)
-#define BIT_GET_XTAL_GMN_3_TO_0(x) (((x) >> BIT_SHIFT_XTAL_GMN_3_TO_0) & BIT_MASK_XTAL_GMN_3_TO_0)
-
+#define BIT_SHIFT_XTAL_GMN_3_TO_0 8
+#define BIT_MASK_XTAL_GMN_3_TO_0 0xf
+#define BIT_XTAL_GMN_3_TO_0(x) \
+ (((x) & BIT_MASK_XTAL_GMN_3_TO_0) << BIT_SHIFT_XTAL_GMN_3_TO_0)
+#define BITS_XTAL_GMN_3_TO_0 \
+ (BIT_MASK_XTAL_GMN_3_TO_0 << BIT_SHIFT_XTAL_GMN_3_TO_0)
+#define BIT_CLEAR_XTAL_GMN_3_TO_0(x) ((x) & (~BITS_XTAL_GMN_3_TO_0))
+#define BIT_GET_XTAL_GMN_3_TO_0(x) \
+ (((x) >> BIT_SHIFT_XTAL_GMN_3_TO_0) & BIT_MASK_XTAL_GMN_3_TO_0)
+#define BIT_SET_XTAL_GMN_3_TO_0(x, v) \
+ (BIT_CLEAR_XTAL_GMN_3_TO_0(x) | BIT_XTAL_GMN_3_TO_0(v))
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-#define BIT_XTAL_LDO_VREF_V1 BIT(7)
+#define BIT_XTAL_LDO_VREF_V1 BIT(7)
#endif
-
#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_SHIFT_XTAL_LDO_VREF 7
-#define BIT_MASK_XTAL_LDO_VREF 0x7
-#define BIT_XTAL_LDO_VREF(x) (((x) & BIT_MASK_XTAL_LDO_VREF) << BIT_SHIFT_XTAL_LDO_VREF)
-#define BIT_GET_XTAL_LDO_VREF(x) (((x) >> BIT_SHIFT_XTAL_LDO_VREF) & BIT_MASK_XTAL_LDO_VREF)
-
+#define BIT_SHIFT_XTAL_LDO_VREF 7
+#define BIT_MASK_XTAL_LDO_VREF 0x7
+#define BIT_XTAL_LDO_VREF(x) \
+ (((x) & BIT_MASK_XTAL_LDO_VREF) << BIT_SHIFT_XTAL_LDO_VREF)
+#define BITS_XTAL_LDO_VREF (BIT_MASK_XTAL_LDO_VREF << BIT_SHIFT_XTAL_LDO_VREF)
+#define BIT_CLEAR_XTAL_LDO_VREF(x) ((x) & (~BITS_XTAL_LDO_VREF))
+#define BIT_GET_XTAL_LDO_VREF(x) \
+ (((x) >> BIT_SHIFT_XTAL_LDO_VREF) & BIT_MASK_XTAL_LDO_VREF)
+#define BIT_SET_XTAL_LDO_VREF(x, v) \
+ (BIT_CLEAR_XTAL_LDO_VREF(x) | BIT_XTAL_LDO_VREF(v))
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-#define BIT_XTAL_XQSEL_RF BIT(6)
-#define BIT_XTAL_XQSEL BIT(5)
+#define BIT_XTAL_XQSEL_RF BIT(6)
+#define BIT_XTAL_XQSEL BIT(5)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_SHIFT_XTAL_GMP 4
-#define BIT_MASK_XTAL_GMP 0xf
-#define BIT_XTAL_GMP(x) (((x) & BIT_MASK_XTAL_GMP) << BIT_SHIFT_XTAL_GMP)
-#define BIT_GET_XTAL_GMP(x) (((x) >> BIT_SHIFT_XTAL_GMP) & BIT_MASK_XTAL_GMP)
-
+#define BIT_SHIFT_XTAL_GMP 4
+#define BIT_MASK_XTAL_GMP 0xf
+#define BIT_XTAL_GMP(x) (((x) & BIT_MASK_XTAL_GMP) << BIT_SHIFT_XTAL_GMP)
+#define BITS_XTAL_GMP (BIT_MASK_XTAL_GMP << BIT_SHIFT_XTAL_GMP)
+#define BIT_CLEAR_XTAL_GMP(x) ((x) & (~BITS_XTAL_GMP))
+#define BIT_GET_XTAL_GMP(x) (((x) >> BIT_SHIFT_XTAL_GMP) & BIT_MASK_XTAL_GMP)
+#define BIT_SET_XTAL_GMP(x, v) (BIT_CLEAR_XTAL_GMP(x) | BIT_XTAL_GMP(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_SHIFT_XTAL_GMP_3_TO_0 4
-#define BIT_MASK_XTAL_GMP_3_TO_0 0xf
-#define BIT_XTAL_GMP_3_TO_0(x) (((x) & BIT_MASK_XTAL_GMP_3_TO_0) << BIT_SHIFT_XTAL_GMP_3_TO_0)
-#define BIT_GET_XTAL_GMP_3_TO_0(x) (((x) >> BIT_SHIFT_XTAL_GMP_3_TO_0) & BIT_MASK_XTAL_GMP_3_TO_0)
-
+#define BIT_SHIFT_XTAL_GMP_3_TO_0 4
+#define BIT_MASK_XTAL_GMP_3_TO_0 0xf
+#define BIT_XTAL_GMP_3_TO_0(x) \
+ (((x) & BIT_MASK_XTAL_GMP_3_TO_0) << BIT_SHIFT_XTAL_GMP_3_TO_0)
+#define BITS_XTAL_GMP_3_TO_0 \
+ (BIT_MASK_XTAL_GMP_3_TO_0 << BIT_SHIFT_XTAL_GMP_3_TO_0)
+#define BIT_CLEAR_XTAL_GMP_3_TO_0(x) ((x) & (~BITS_XTAL_GMP_3_TO_0))
+#define BIT_GET_XTAL_GMP_3_TO_0(x) \
+ (((x) >> BIT_SHIFT_XTAL_GMP_3_TO_0) & BIT_MASK_XTAL_GMP_3_TO_0)
+#define BIT_SET_XTAL_GMP_3_TO_0(x, v) \
+ (BIT_CLEAR_XTAL_GMP_3_TO_0(x) | BIT_XTAL_GMP_3_TO_0(v))
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_SHIFT_XTAL_GMN_V1 3
-#define BIT_MASK_XTAL_GMN_V1 0x3
-#define BIT_XTAL_GMN_V1(x) (((x) & BIT_MASK_XTAL_GMN_V1) << BIT_SHIFT_XTAL_GMN_V1)
-#define BIT_GET_XTAL_GMN_V1(x) (((x) >> BIT_SHIFT_XTAL_GMN_V1) & BIT_MASK_XTAL_GMN_V1)
-
+#define BIT_SHIFT_XTAL_GMN_V1 3
+#define BIT_MASK_XTAL_GMN_V1 0x3
+#define BIT_XTAL_GMN_V1(x) \
+ (((x) & BIT_MASK_XTAL_GMN_V1) << BIT_SHIFT_XTAL_GMN_V1)
+#define BITS_XTAL_GMN_V1 (BIT_MASK_XTAL_GMN_V1 << BIT_SHIFT_XTAL_GMN_V1)
+#define BIT_CLEAR_XTAL_GMN_V1(x) ((x) & (~BITS_XTAL_GMN_V1))
+#define BIT_GET_XTAL_GMN_V1(x) \
+ (((x) >> BIT_SHIFT_XTAL_GMN_V1) & BIT_MASK_XTAL_GMN_V1)
+#define BIT_SET_XTAL_GMN_V1(x, v) \
+ (BIT_CLEAR_XTAL_GMN_V1(x) | BIT_XTAL_GMN_V1(v))
#endif
-
#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_SHIFT_XTAL_GMN_V2 3
-#define BIT_MASK_XTAL_GMN_V2 0x3
-#define BIT_XTAL_GMN_V2(x) (((x) & BIT_MASK_XTAL_GMN_V2) << BIT_SHIFT_XTAL_GMN_V2)
-#define BIT_GET_XTAL_GMN_V2(x) (((x) >> BIT_SHIFT_XTAL_GMN_V2) & BIT_MASK_XTAL_GMN_V2)
-
+#define BIT_SHIFT_XTAL_GMN_V2 3
+#define BIT_MASK_XTAL_GMN_V2 0x3
+#define BIT_XTAL_GMN_V2(x) \
+ (((x) & BIT_MASK_XTAL_GMN_V2) << BIT_SHIFT_XTAL_GMN_V2)
+#define BITS_XTAL_GMN_V2 (BIT_MASK_XTAL_GMN_V2 << BIT_SHIFT_XTAL_GMN_V2)
+#define BIT_CLEAR_XTAL_GMN_V2(x) ((x) & (~BITS_XTAL_GMN_V2))
+#define BIT_GET_XTAL_GMN_V2(x) \
+ (((x) >> BIT_SHIFT_XTAL_GMN_V2) & BIT_MASK_XTAL_GMN_V2)
+#define BIT_SET_XTAL_GMN_V2(x, v) \
+ (BIT_CLEAR_XTAL_GMN_V2(x) | BIT_XTAL_GMN_V2(v))
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_SHIFT_XTAL_LDO_VCM 2
-#define BIT_MASK_XTAL_LDO_VCM 0x3
-#define BIT_XTAL_LDO_VCM(x) (((x) & BIT_MASK_XTAL_LDO_VCM) << BIT_SHIFT_XTAL_LDO_VCM)
-#define BIT_GET_XTAL_LDO_VCM(x) (((x) >> BIT_SHIFT_XTAL_LDO_VCM) & BIT_MASK_XTAL_LDO_VCM)
-
+#define BIT_SHIFT_XTAL_LDO_VCM 2
+#define BIT_MASK_XTAL_LDO_VCM 0x3
+#define BIT_XTAL_LDO_VCM(x) \
+ (((x) & BIT_MASK_XTAL_LDO_VCM) << BIT_SHIFT_XTAL_LDO_VCM)
+#define BITS_XTAL_LDO_VCM (BIT_MASK_XTAL_LDO_VCM << BIT_SHIFT_XTAL_LDO_VCM)
+#define BIT_CLEAR_XTAL_LDO_VCM(x) ((x) & (~BITS_XTAL_LDO_VCM))
+#define BIT_GET_XTAL_LDO_VCM(x) \
+ (((x) >> BIT_SHIFT_XTAL_LDO_VCM) & BIT_MASK_XTAL_LDO_VCM)
+#define BIT_SET_XTAL_LDO_VCM(x, v) \
+ (BIT_CLEAR_XTAL_LDO_VCM(x) | BIT_XTAL_LDO_VCM(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_SHIFT_DRV_LDO_VCM_1_TO_0 2
-#define BIT_MASK_DRV_LDO_VCM_1_TO_0 0x3
-#define BIT_DRV_LDO_VCM_1_TO_0(x) (((x) & BIT_MASK_DRV_LDO_VCM_1_TO_0) << BIT_SHIFT_DRV_LDO_VCM_1_TO_0)
-#define BIT_GET_DRV_LDO_VCM_1_TO_0(x) (((x) >> BIT_SHIFT_DRV_LDO_VCM_1_TO_0) & BIT_MASK_DRV_LDO_VCM_1_TO_0)
-
+#define BIT_SHIFT_DRV_LDO_VCM_1_TO_0 2
+#define BIT_MASK_DRV_LDO_VCM_1_TO_0 0x3
+#define BIT_DRV_LDO_VCM_1_TO_0(x) \
+ (((x) & BIT_MASK_DRV_LDO_VCM_1_TO_0) << BIT_SHIFT_DRV_LDO_VCM_1_TO_0)
+#define BITS_DRV_LDO_VCM_1_TO_0 \
+ (BIT_MASK_DRV_LDO_VCM_1_TO_0 << BIT_SHIFT_DRV_LDO_VCM_1_TO_0)
+#define BIT_CLEAR_DRV_LDO_VCM_1_TO_0(x) ((x) & (~BITS_DRV_LDO_VCM_1_TO_0))
+#define BIT_GET_DRV_LDO_VCM_1_TO_0(x) \
+ (((x) >> BIT_SHIFT_DRV_LDO_VCM_1_TO_0) & BIT_MASK_DRV_LDO_VCM_1_TO_0)
+#define BIT_SET_DRV_LDO_VCM_1_TO_0(x, v) \
+ (BIT_CLEAR_DRV_LDO_VCM_1_TO_0(x) | BIT_DRV_LDO_VCM_1_TO_0(v))
#endif
-
#if (HALMAC_8192E_SUPPORT)
-
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-#define BIT_XTAL_DUMMY BIT(1)
+#define BIT_XTAL_DUMMY BIT(1)
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_SHIFT_XTAL_GMP_V1 1
-#define BIT_MASK_XTAL_GMP_V1 0x3
-#define BIT_XTAL_GMP_V1(x) (((x) & BIT_MASK_XTAL_GMP_V1) << BIT_SHIFT_XTAL_GMP_V1)
-#define BIT_GET_XTAL_GMP_V1(x) (((x) >> BIT_SHIFT_XTAL_GMP_V1) & BIT_MASK_XTAL_GMP_V1)
-
+#define BIT_SHIFT_XTAL_GMP_V1 1
+#define BIT_MASK_XTAL_GMP_V1 0x3
+#define BIT_XTAL_GMP_V1(x) \
+ (((x) & BIT_MASK_XTAL_GMP_V1) << BIT_SHIFT_XTAL_GMP_V1)
+#define BITS_XTAL_GMP_V1 (BIT_MASK_XTAL_GMP_V1 << BIT_SHIFT_XTAL_GMP_V1)
+#define BIT_CLEAR_XTAL_GMP_V1(x) ((x) & (~BITS_XTAL_GMP_V1))
+#define BIT_GET_XTAL_GMP_V1(x) \
+ (((x) >> BIT_SHIFT_XTAL_GMP_V1) & BIT_MASK_XTAL_GMP_V1)
+#define BIT_SET_XTAL_GMP_V1(x, v) \
+ (BIT_CLEAR_XTAL_GMP_V1(x) | BIT_XTAL_GMP_V1(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-#define BIT_XQSEL_RF_INITIAL_V1 BIT(1)
+#define BIT_XQSEL_RF_INITIAL_V1 BIT(1)
#endif
-
#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-
-#define BIT_SHIFT_XTAL_GMP_V2 1
-#define BIT_MASK_XTAL_GMP_V2 0x3
-#define BIT_XTAL_GMP_V2(x) (((x) & BIT_MASK_XTAL_GMP_V2) << BIT_SHIFT_XTAL_GMP_V2)
-#define BIT_GET_XTAL_GMP_V2(x) (((x) >> BIT_SHIFT_XTAL_GMP_V2) & BIT_MASK_XTAL_GMP_V2)
-
+#define BIT_SHIFT_XTAL_GMP_V2 1
+#define BIT_MASK_XTAL_GMP_V2 0x3
+#define BIT_XTAL_GMP_V2(x) \
+ (((x) & BIT_MASK_XTAL_GMP_V2) << BIT_SHIFT_XTAL_GMP_V2)
+#define BITS_XTAL_GMP_V2 (BIT_MASK_XTAL_GMP_V2 << BIT_SHIFT_XTAL_GMP_V2)
+#define BIT_CLEAR_XTAL_GMP_V2(x) ((x) & (~BITS_XTAL_GMP_V2))
+#define BIT_GET_XTAL_GMP_V2(x) \
+ (((x) >> BIT_SHIFT_XTAL_GMP_V2) & BIT_MASK_XTAL_GMP_V2)
+#define BIT_SET_XTAL_GMP_V2(x, v) \
+ (BIT_CLEAR_XTAL_GMP_V2(x) | BIT_XTAL_GMP_V2(v))
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_AFE_CTRL1 (Offset 0x0024) */
-#define BIT_XTAL_EN BIT(0)
+#define BIT_XTAL_EN BIT(0)
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_FREE_TXPG2 (Offset 0x10250024) */
-
-#define BIT_SHIFT_LOW_FREEPG_V1 0
-#define BIT_MASK_LOW_FREEPG_V1 0xfff
-#define BIT_LOW_FREEPG_V1(x) (((x) & BIT_MASK_LOW_FREEPG_V1) << BIT_SHIFT_LOW_FREEPG_V1)
-#define BIT_GET_LOW_FREEPG_V1(x) (((x) >> BIT_SHIFT_LOW_FREEPG_V1) & BIT_MASK_LOW_FREEPG_V1)
-
+#define BIT_SHIFT_LOW_FREEPG_V1 0
+#define BIT_MASK_LOW_FREEPG_V1 0xfff
+#define BIT_LOW_FREEPG_V1(x) \
+ (((x) & BIT_MASK_LOW_FREEPG_V1) << BIT_SHIFT_LOW_FREEPG_V1)
+#define BITS_LOW_FREEPG_V1 (BIT_MASK_LOW_FREEPG_V1 << BIT_SHIFT_LOW_FREEPG_V1)
+#define BIT_CLEAR_LOW_FREEPG_V1(x) ((x) & (~BITS_LOW_FREEPG_V1))
+#define BIT_GET_LOW_FREEPG_V1(x) \
+ (((x) >> BIT_SHIFT_LOW_FREEPG_V1) & BIT_MASK_LOW_FREEPG_V1)
+#define BIT_SET_LOW_FREEPG_V1(x, v) \
+ (BIT_CLEAR_LOW_FREEPG_V1(x) | BIT_LOW_FREEPG_V1(v))
#endif
-
#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
+#define BIT_SHIFT_REG_C3_V4 30
+#define BIT_MASK_REG_C3_V4 0x3
+#define BIT_REG_C3_V4(x) (((x) & BIT_MASK_REG_C3_V4) << BIT_SHIFT_REG_C3_V4)
+#define BITS_REG_C3_V4 (BIT_MASK_REG_C3_V4 << BIT_SHIFT_REG_C3_V4)
+#define BIT_CLEAR_REG_C3_V4(x) ((x) & (~BITS_REG_C3_V4))
+#define BIT_GET_REG_C3_V4(x) (((x) >> BIT_SHIFT_REG_C3_V4) & BIT_MASK_REG_C3_V4)
+#define BIT_SET_REG_C3_V4(x, v) (BIT_CLEAR_REG_C3_V4(x) | BIT_REG_C3_V4(v))
-#define BIT_SHIFT_REG_C3_V4 30
-#define BIT_MASK_REG_C3_V4 0x3
-#define BIT_REG_C3_V4(x) (((x) & BIT_MASK_REG_C3_V4) << BIT_SHIFT_REG_C3_V4)
-#define BIT_GET_REG_C3_V4(x) (((x) >> BIT_SHIFT_REG_C3_V4) & BIT_MASK_REG_C3_V4)
-
-#define BIT_REG_CP_BIT1 BIT(29)
+#define BIT_REG_CP_BIT1 BIT(29)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-
-#define BIT_SHIFT_XTAL_GMN 28
-#define BIT_MASK_XTAL_GMN 0xf
-#define BIT_XTAL_GMN(x) (((x) & BIT_MASK_XTAL_GMN) << BIT_SHIFT_XTAL_GMN)
-#define BIT_GET_XTAL_GMN(x) (((x) >> BIT_SHIFT_XTAL_GMN) & BIT_MASK_XTAL_GMN)
-
+#define BIT_SHIFT_XTAL_GMN 28
+#define BIT_MASK_XTAL_GMN 0xf
+#define BIT_XTAL_GMN(x) (((x) & BIT_MASK_XTAL_GMN) << BIT_SHIFT_XTAL_GMN)
+#define BITS_XTAL_GMN (BIT_MASK_XTAL_GMN << BIT_SHIFT_XTAL_GMN)
+#define BIT_CLEAR_XTAL_GMN(x) ((x) & (~BITS_XTAL_GMN))
+#define BIT_GET_XTAL_GMN(x) (((x) >> BIT_SHIFT_XTAL_GMN) & BIT_MASK_XTAL_GMN)
+#define BIT_SET_XTAL_GMN(x, v) (BIT_CLEAR_XTAL_GMN(x) | BIT_XTAL_GMN(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
+#define BIT_SHIFT_IOOFFSET_3_TO_0 28
+#define BIT_MASK_IOOFFSET_3_TO_0 0xf
+#define BIT_IOOFFSET_3_TO_0(x) \
+ (((x) & BIT_MASK_IOOFFSET_3_TO_0) << BIT_SHIFT_IOOFFSET_3_TO_0)
+#define BITS_IOOFFSET_3_TO_0 \
+ (BIT_MASK_IOOFFSET_3_TO_0 << BIT_SHIFT_IOOFFSET_3_TO_0)
+#define BIT_CLEAR_IOOFFSET_3_TO_0(x) ((x) & (~BITS_IOOFFSET_3_TO_0))
+#define BIT_GET_IOOFFSET_3_TO_0(x) \
+ (((x) >> BIT_SHIFT_IOOFFSET_3_TO_0) & BIT_MASK_IOOFFSET_3_TO_0)
+#define BIT_SET_IOOFFSET_3_TO_0(x, v) \
+ (BIT_CLEAR_IOOFFSET_3_TO_0(x) | BIT_IOOFFSET_3_TO_0(v))
-#define BIT_SHIFT_IOOFFSET_3_TO_0 28
-#define BIT_MASK_IOOFFSET_3_TO_0 0xf
-#define BIT_IOOFFSET_3_TO_0(x) (((x) & BIT_MASK_IOOFFSET_3_TO_0) << BIT_SHIFT_IOOFFSET_3_TO_0)
-#define BIT_GET_IOOFFSET_3_TO_0(x) (((x) >> BIT_SHIFT_IOOFFSET_3_TO_0) & BIT_MASK_IOOFFSET_3_TO_0)
-
-#define BIT_REG_FREF_SEL_BIT3_V1 BIT(27)
+#define BIT_REG_FREF_SEL_BIT3_V1 BIT(27)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-
-#define BIT_SHIFT_REG_VO_AD 26
-#define BIT_MASK_REG_VO_AD 0x3
-#define BIT_REG_VO_AD(x) (((x) & BIT_MASK_REG_VO_AD) << BIT_SHIFT_REG_VO_AD)
-#define BIT_GET_REG_VO_AD(x) (((x) >> BIT_SHIFT_REG_VO_AD) & BIT_MASK_REG_VO_AD)
-
+#define BIT_SHIFT_REG_VO_AD 26
+#define BIT_MASK_REG_VO_AD 0x3
+#define BIT_REG_VO_AD(x) (((x) & BIT_MASK_REG_VO_AD) << BIT_SHIFT_REG_VO_AD)
+#define BITS_REG_VO_AD (BIT_MASK_REG_VO_AD << BIT_SHIFT_REG_VO_AD)
+#define BIT_CLEAR_REG_VO_AD(x) ((x) & (~BITS_REG_VO_AD))
+#define BIT_GET_REG_VO_AD(x) (((x) >> BIT_SHIFT_REG_VO_AD) & BIT_MASK_REG_VO_AD)
+#define BIT_SET_REG_VO_AD(x, v) (BIT_CLEAR_REG_VO_AD(x) | BIT_REG_VO_AD(v))
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-
-#define BIT_SHIFT_RS_SET_V2 26
-#define BIT_MASK_RS_SET_V2 0x7
-#define BIT_RS_SET_V2(x) (((x) & BIT_MASK_RS_SET_V2) << BIT_SHIFT_RS_SET_V2)
-#define BIT_GET_RS_SET_V2(x) (((x) >> BIT_SHIFT_RS_SET_V2) & BIT_MASK_RS_SET_V2)
-
+#define BIT_SHIFT_RS_SET_V2 26
+#define BIT_MASK_RS_SET_V2 0x7
+#define BIT_RS_SET_V2(x) (((x) & BIT_MASK_RS_SET_V2) << BIT_SHIFT_RS_SET_V2)
+#define BITS_RS_SET_V2 (BIT_MASK_RS_SET_V2 << BIT_SHIFT_RS_SET_V2)
+#define BIT_CLEAR_RS_SET_V2(x) ((x) & (~BITS_RS_SET_V2))
+#define BIT_GET_RS_SET_V2(x) (((x) >> BIT_SHIFT_RS_SET_V2) & BIT_MASK_RS_SET_V2)
+#define BIT_SET_RS_SET_V2(x, v) (BIT_CLEAR_RS_SET_V2(x) | BIT_RS_SET_V2(v))
#endif
-
#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-
-#define BIT_SHIFT_REG_RS_V4 26
-#define BIT_MASK_REG_RS_V4 0x7
-#define BIT_REG_RS_V4(x) (((x) & BIT_MASK_REG_RS_V4) << BIT_SHIFT_REG_RS_V4)
-#define BIT_GET_REG_RS_V4(x) (((x) >> BIT_SHIFT_REG_RS_V4) & BIT_MASK_REG_RS_V4)
-
+#define BIT_SHIFT_REG_RS_V4 26
+#define BIT_MASK_REG_RS_V4 0x7
+#define BIT_REG_RS_V4(x) (((x) & BIT_MASK_REG_RS_V4) << BIT_SHIFT_REG_RS_V4)
+#define BITS_REG_RS_V4 (BIT_MASK_REG_RS_V4 << BIT_SHIFT_REG_RS_V4)
+#define BIT_CLEAR_REG_RS_V4(x) ((x) & (~BITS_REG_RS_V4))
+#define BIT_GET_REG_RS_V4(x) (((x) >> BIT_SHIFT_REG_RS_V4) & BIT_MASK_REG_RS_V4)
+#define BIT_SET_REG_RS_V4(x, v) (BIT_CLEAR_REG_RS_V4(x) | BIT_REG_RS_V4(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-
-#define BIT_SHIFT_V12ADJ_V1 25
-#define BIT_MASK_V12ADJ_V1 0x3
-#define BIT_V12ADJ_V1(x) (((x) & BIT_MASK_V12ADJ_V1) << BIT_SHIFT_V12ADJ_V1)
-#define BIT_GET_V12ADJ_V1(x) (((x) >> BIT_SHIFT_V12ADJ_V1) & BIT_MASK_V12ADJ_V1)
-
+#define BIT_SHIFT_V12ADJ_V1 25
+#define BIT_MASK_V12ADJ_V1 0x3
+#define BIT_V12ADJ_V1(x) (((x) & BIT_MASK_V12ADJ_V1) << BIT_SHIFT_V12ADJ_V1)
+#define BITS_V12ADJ_V1 (BIT_MASK_V12ADJ_V1 << BIT_SHIFT_V12ADJ_V1)
+#define BIT_CLEAR_V12ADJ_V1(x) ((x) & (~BITS_V12ADJ_V1))
+#define BIT_GET_V12ADJ_V1(x) (((x) >> BIT_SHIFT_V12ADJ_V1) & BIT_MASK_V12ADJ_V1)
+#define BIT_SET_V12ADJ_V1(x, v) (BIT_CLEAR_V12ADJ_V1(x) | BIT_V12ADJ_V1(v))
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_OQT_FREE_TXPG_V1 (Offset 0x10250028) */
-
-#define BIT_SHIFT_NOAC_OQT_FREEPG_V1 24
-#define BIT_MASK_NOAC_OQT_FREEPG_V1 0xff
-#define BIT_NOAC_OQT_FREEPG_V1(x) (((x) & BIT_MASK_NOAC_OQT_FREEPG_V1) << BIT_SHIFT_NOAC_OQT_FREEPG_V1)
-#define BIT_GET_NOAC_OQT_FREEPG_V1(x) (((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1) & BIT_MASK_NOAC_OQT_FREEPG_V1)
-
+#define BIT_SHIFT_NOAC_OQT_FREEPG_V1 24
+#define BIT_MASK_NOAC_OQT_FREEPG_V1 0xff
+#define BIT_NOAC_OQT_FREEPG_V1(x) \
+ (((x) & BIT_MASK_NOAC_OQT_FREEPG_V1) << BIT_SHIFT_NOAC_OQT_FREEPG_V1)
+#define BITS_NOAC_OQT_FREEPG_V1 \
+ (BIT_MASK_NOAC_OQT_FREEPG_V1 << BIT_SHIFT_NOAC_OQT_FREEPG_V1)
+#define BIT_CLEAR_NOAC_OQT_FREEPG_V1(x) ((x) & (~BITS_NOAC_OQT_FREEPG_V1))
+#define BIT_GET_NOAC_OQT_FREEPG_V1(x) \
+ (((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1) & BIT_MASK_NOAC_OQT_FREEPG_V1)
+#define BIT_SET_NOAC_OQT_FREEPG_V1(x, v) \
+ (BIT_CLEAR_NOAC_OQT_FREEPG_V1(x) | BIT_NOAC_OQT_FREEPG_V1(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-#define BIT_PS_EN BIT(24)
+#define BIT_PS_EN BIT(24)
#endif
-
#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-
-#define BIT_SHIFT_REG__CS 24
-#define BIT_MASK_REG__CS 0x3
-#define BIT_REG__CS(x) (((x) & BIT_MASK_REG__CS) << BIT_SHIFT_REG__CS)
-#define BIT_GET_REG__CS(x) (((x) >> BIT_SHIFT_REG__CS) & BIT_MASK_REG__CS)
-
+#define BIT_SHIFT_REG__CS 24
+#define BIT_MASK_REG__CS 0x3
+#define BIT_REG__CS(x) (((x) & BIT_MASK_REG__CS) << BIT_SHIFT_REG__CS)
+#define BITS_REG__CS (BIT_MASK_REG__CS << BIT_SHIFT_REG__CS)
+#define BIT_CLEAR_REG__CS(x) ((x) & (~BITS_REG__CS))
+#define BIT_GET_REG__CS(x) (((x) >> BIT_SHIFT_REG__CS) & BIT_MASK_REG__CS)
+#define BIT_SET_REG__CS(x, v) (BIT_CLEAR_REG__CS(x) | BIT_REG__CS(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-#define BIT_EN_CK320M_V1 BIT(23)
-#define BIT_AGPIO BIT(22)
-#define BIT_REG_EDGE_SEL_V1 BIT(21)
+#define BIT_EN_CK320M_V1 BIT(23)
+#define BIT_AGPIO BIT(22)
+#define BIT_REG_EDGE_SEL_V1 BIT(21)
#endif
-
#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-
-#define BIT_SHIFT_REG_CP_OFFSET 21
-#define BIT_MASK_REG_CP_OFFSET 0x7
-#define BIT_REG_CP_OFFSET(x) (((x) & BIT_MASK_REG_CP_OFFSET) << BIT_SHIFT_REG_CP_OFFSET)
-#define BIT_GET_REG_CP_OFFSET(x) (((x) >> BIT_SHIFT_REG_CP_OFFSET) & BIT_MASK_REG_CP_OFFSET)
-
+#define BIT_SHIFT_REG_CP_OFFSET 21
+#define BIT_MASK_REG_CP_OFFSET 0x7
+#define BIT_REG_CP_OFFSET(x) \
+ (((x) & BIT_MASK_REG_CP_OFFSET) << BIT_SHIFT_REG_CP_OFFSET)
+#define BITS_REG_CP_OFFSET (BIT_MASK_REG_CP_OFFSET << BIT_SHIFT_REG_CP_OFFSET)
+#define BIT_CLEAR_REG_CP_OFFSET(x) ((x) & (~BITS_REG_CP_OFFSET))
+#define BIT_GET_REG_CP_OFFSET(x) \
+ (((x) >> BIT_SHIFT_REG_CP_OFFSET) & BIT_MASK_REG_CP_OFFSET)
+#define BIT_SET_REG_CP_OFFSET(x, v) \
+ (BIT_CLEAR_REG_CP_OFFSET(x) | BIT_REG_CP_OFFSET(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-#define BIT_REG_VCO_BIAS_0 BIT(20)
+#define BIT_REG_VCO_BIAS_0 BIT(20)
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-
-#define BIT_SHIFT_CP_BIAS_V2 18
-#define BIT_MASK_CP_BIAS_V2 0x7
-#define BIT_CP_BIAS_V2(x) (((x) & BIT_MASK_CP_BIAS_V2) << BIT_SHIFT_CP_BIAS_V2)
-#define BIT_GET_CP_BIAS_V2(x) (((x) >> BIT_SHIFT_CP_BIAS_V2) & BIT_MASK_CP_BIAS_V2)
-
+#define BIT_SHIFT_CP_BIAS_V2 18
+#define BIT_MASK_CP_BIAS_V2 0x7
+#define BIT_CP_BIAS_V2(x) (((x) & BIT_MASK_CP_BIAS_V2) << BIT_SHIFT_CP_BIAS_V2)
+#define BITS_CP_BIAS_V2 (BIT_MASK_CP_BIAS_V2 << BIT_SHIFT_CP_BIAS_V2)
+#define BIT_CLEAR_CP_BIAS_V2(x) ((x) & (~BITS_CP_BIAS_V2))
+#define BIT_GET_CP_BIAS_V2(x) \
+ (((x) >> BIT_SHIFT_CP_BIAS_V2) & BIT_MASK_CP_BIAS_V2)
+#define BIT_SET_CP_BIAS_V2(x, v) (BIT_CLEAR_CP_BIAS_V2(x) | BIT_CP_BIAS_V2(v))
#endif
-
#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-
-#define BIT_SHIFT_CP_BIAS 18
-#define BIT_MASK_CP_BIAS 0x7
-#define BIT_CP_BIAS(x) (((x) & BIT_MASK_CP_BIAS) << BIT_SHIFT_CP_BIAS)
-#define BIT_GET_CP_BIAS(x) (((x) >> BIT_SHIFT_CP_BIAS) & BIT_MASK_CP_BIAS)
-
+#define BIT_SHIFT_CP_BIAS 18
+#define BIT_MASK_CP_BIAS 0x7
+#define BIT_CP_BIAS(x) (((x) & BIT_MASK_CP_BIAS) << BIT_SHIFT_CP_BIAS)
+#define BITS_CP_BIAS (BIT_MASK_CP_BIAS << BIT_SHIFT_CP_BIAS)
+#define BIT_CLEAR_CP_BIAS(x) ((x) & (~BITS_CP_BIAS))
+#define BIT_GET_CP_BIAS(x) (((x) >> BIT_SHIFT_CP_BIAS) & BIT_MASK_CP_BIAS)
+#define BIT_SET_CP_BIAS(x, v) (BIT_CLEAR_CP_BIAS(x) | BIT_CP_BIAS(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-
-#define BIT_SHIFT_REG_PLLBIAS_2_TO_0_V1 17
-#define BIT_MASK_REG_PLLBIAS_2_TO_0_V1 0x7
-#define BIT_REG_PLLBIAS_2_TO_0_V1(x) (((x) & BIT_MASK_REG_PLLBIAS_2_TO_0_V1) << BIT_SHIFT_REG_PLLBIAS_2_TO_0_V1)
-#define BIT_GET_REG_PLLBIAS_2_TO_0_V1(x) (((x) >> BIT_SHIFT_REG_PLLBIAS_2_TO_0_V1) & BIT_MASK_REG_PLLBIAS_2_TO_0_V1)
-
+#define BIT_SHIFT_REG_PLLBIAS_2_TO_0_V1 17
+#define BIT_MASK_REG_PLLBIAS_2_TO_0_V1 0x7
+#define BIT_REG_PLLBIAS_2_TO_0_V1(x) \
+ (((x) & BIT_MASK_REG_PLLBIAS_2_TO_0_V1) \
+ << BIT_SHIFT_REG_PLLBIAS_2_TO_0_V1)
+#define BITS_REG_PLLBIAS_2_TO_0_V1 \
+ (BIT_MASK_REG_PLLBIAS_2_TO_0_V1 << BIT_SHIFT_REG_PLLBIAS_2_TO_0_V1)
+#define BIT_CLEAR_REG_PLLBIAS_2_TO_0_V1(x) ((x) & (~BITS_REG_PLLBIAS_2_TO_0_V1))
+#define BIT_GET_REG_PLLBIAS_2_TO_0_V1(x) \
+ (((x) >> BIT_SHIFT_REG_PLLBIAS_2_TO_0_V1) & \
+ BIT_MASK_REG_PLLBIAS_2_TO_0_V1)
+#define BIT_SET_REG_PLLBIAS_2_TO_0_V1(x, v) \
+ (BIT_CLEAR_REG_PLLBIAS_2_TO_0_V1(x) | BIT_REG_PLLBIAS_2_TO_0_V1(v))
#endif
-
#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-#define BIT_REG_IDOUBLE_V2 BIT(17)
+#define BIT_REG_IDOUBLE_V2 BIT(17)
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-#define BIT_FREF_SEL BIT(16)
+#define BIT_FREF_SEL BIT(16)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-#define BIT_REG_IDOUBLE_V1 BIT(16)
-
-#define BIT_SHIFT_AC_OQT__FREEPG_V1 16
-#define BIT_MASK_AC_OQT__FREEPG_V1 0xff
-#define BIT_AC_OQT__FREEPG_V1(x) (((x) & BIT_MASK_AC_OQT__FREEPG_V1) << BIT_SHIFT_AC_OQT__FREEPG_V1)
-#define BIT_GET_AC_OQT__FREEPG_V1(x) (((x) >> BIT_SHIFT_AC_OQT__FREEPG_V1) & BIT_MASK_AC_OQT__FREEPG_V1)
+#define BIT_REG_IDOUBLE_V1 BIT(16)
+#define BIT_SHIFT_AC_OQT__FREEPG_V1 16
+#define BIT_MASK_AC_OQT__FREEPG_V1 0xff
+#define BIT_AC_OQT__FREEPG_V1(x) \
+ (((x) & BIT_MASK_AC_OQT__FREEPG_V1) << BIT_SHIFT_AC_OQT__FREEPG_V1)
+#define BITS_AC_OQT__FREEPG_V1 \
+ (BIT_MASK_AC_OQT__FREEPG_V1 << BIT_SHIFT_AC_OQT__FREEPG_V1)
+#define BIT_CLEAR_AC_OQT__FREEPG_V1(x) ((x) & (~BITS_AC_OQT__FREEPG_V1))
+#define BIT_GET_AC_OQT__FREEPG_V1(x) \
+ (((x) >> BIT_SHIFT_AC_OQT__FREEPG_V1) & BIT_MASK_AC_OQT__FREEPG_V1)
+#define BIT_SET_AC_OQT__FREEPG_V1(x, v) \
+ (BIT_CLEAR_AC_OQT__FREEPG_V1(x) | BIT_AC_OQT__FREEPG_V1(v))
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_SDIO_OQT_FREE_TXPG_V1 (Offset 0x10250028) */
+#define BIT_SHIFT_AC_OQT_FREEPG_V1 16
+#define BIT_MASK_AC_OQT_FREEPG_V1 0xff
+#define BIT_AC_OQT_FREEPG_V1(x) \
+ (((x) & BIT_MASK_AC_OQT_FREEPG_V1) << BIT_SHIFT_AC_OQT_FREEPG_V1)
+#define BITS_AC_OQT_FREEPG_V1 \
+ (BIT_MASK_AC_OQT_FREEPG_V1 << BIT_SHIFT_AC_OQT_FREEPG_V1)
+#define BIT_CLEAR_AC_OQT_FREEPG_V1(x) ((x) & (~BITS_AC_OQT_FREEPG_V1))
+#define BIT_GET_AC_OQT_FREEPG_V1(x) \
+ (((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1) & BIT_MASK_AC_OQT_FREEPG_V1)
+#define BIT_SET_AC_OQT_FREEPG_V1(x, v) \
+ (BIT_CLEAR_AC_OQT_FREEPG_V1(x) | BIT_AC_OQT_FREEPG_V1(v))
-/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
+#endif
-#define BIT_EN_SYN BIT(16)
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_AC_OQT_FREEPG_V1 16
-#define BIT_MASK_AC_OQT_FREEPG_V1 0xff
-#define BIT_AC_OQT_FREEPG_V1(x) (((x) & BIT_MASK_AC_OQT_FREEPG_V1) << BIT_SHIFT_AC_OQT_FREEPG_V1)
-#define BIT_GET_AC_OQT_FREEPG_V1(x) (((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1) & BIT_MASK_AC_OQT_FREEPG_V1)
+/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
+#define BIT_EN_SYN BIT(16)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-#define BIT_REG_KVCO_V1 BIT(15)
+#define BIT_REG_KVCO_V1 BIT(15)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-#define BIT_APLL_320_GATEB BIT(14)
+#define BIT_APLL_320_GATEB BIT(14)
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-
-#define BIT_SHIFT_MCCO_V2 14
-#define BIT_MASK_MCCO_V2 0x3
-#define BIT_MCCO_V2(x) (((x) & BIT_MASK_MCCO_V2) << BIT_SHIFT_MCCO_V2)
-#define BIT_GET_MCCO_V2(x) (((x) >> BIT_SHIFT_MCCO_V2) & BIT_MASK_MCCO_V2)
-
+#define BIT_SHIFT_MCCO_V2 14
+#define BIT_MASK_MCCO_V2 0x3
+#define BIT_MCCO_V2(x) (((x) & BIT_MASK_MCCO_V2) << BIT_SHIFT_MCCO_V2)
+#define BITS_MCCO_V2 (BIT_MASK_MCCO_V2 << BIT_SHIFT_MCCO_V2)
+#define BIT_CLEAR_MCCO_V2(x) ((x) & (~BITS_MCCO_V2))
+#define BIT_GET_MCCO_V2(x) (((x) >> BIT_SHIFT_MCCO_V2) & BIT_MASK_MCCO_V2)
+#define BIT_SET_MCCO_V2(x, v) (BIT_CLEAR_MCCO_V2(x) | BIT_MCCO_V2(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-#define BIT_REG_VCO_BIAS_1_V1 BIT(14)
+#define BIT_REG_VCO_BIAS_1_V1 BIT(14)
#endif
-
#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-
-#define BIT_SHIFT_MCCO 14
-#define BIT_MASK_MCCO 0x3
-#define BIT_MCCO(x) (((x) & BIT_MASK_MCCO) << BIT_SHIFT_MCCO)
-#define BIT_GET_MCCO(x) (((x) >> BIT_SHIFT_MCCO) & BIT_MASK_MCCO)
-
+#define BIT_SHIFT_MCCO 14
+#define BIT_MASK_MCCO 0x3
+#define BIT_MCCO(x) (((x) & BIT_MASK_MCCO) << BIT_SHIFT_MCCO)
+#define BITS_MCCO (BIT_MASK_MCCO << BIT_SHIFT_MCCO)
+#define BIT_CLEAR_MCCO(x) ((x) & (~BITS_MCCO))
+#define BIT_GET_MCCO(x) (((x) >> BIT_SHIFT_MCCO) & BIT_MASK_MCCO)
+#define BIT_SET_MCCO(x, v) (BIT_CLEAR_MCCO(x) | BIT_MCCO(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-#define BIT_REG_DOGB_V1 BIT(13)
+#define BIT_REG_DOGB_V1 BIT(13)
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-
-#define BIT_SHIFT_CK320_EN 12
-#define BIT_MASK_CK320_EN 0x3
-#define BIT_CK320_EN(x) (((x) & BIT_MASK_CK320_EN) << BIT_SHIFT_CK320_EN)
-#define BIT_GET_CK320_EN(x) (((x) >> BIT_SHIFT_CK320_EN) & BIT_MASK_CK320_EN)
-
+#define BIT_SHIFT_CK320_EN 12
+#define BIT_MASK_CK320_EN 0x3
+#define BIT_CK320_EN(x) (((x) & BIT_MASK_CK320_EN) << BIT_SHIFT_CK320_EN)
+#define BITS_CK320_EN (BIT_MASK_CK320_EN << BIT_SHIFT_CK320_EN)
+#define BIT_CLEAR_CK320_EN(x) ((x) & (~BITS_CK320_EN))
+#define BIT_GET_CK320_EN(x) (((x) >> BIT_SHIFT_CK320_EN) & BIT_MASK_CK320_EN)
+#define BIT_SET_CK320_EN(x, v) (BIT_CLEAR_CK320_EN(x) | BIT_CK320_EN(v))
#endif
-
#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
+#define BIT_SHIFT_REG_LDO_SEL 12
+#define BIT_MASK_REG_LDO_SEL 0x3
+#define BIT_REG_LDO_SEL(x) \
+ (((x) & BIT_MASK_REG_LDO_SEL) << BIT_SHIFT_REG_LDO_SEL)
+#define BITS_REG_LDO_SEL (BIT_MASK_REG_LDO_SEL << BIT_SHIFT_REG_LDO_SEL)
+#define BIT_CLEAR_REG_LDO_SEL(x) ((x) & (~BITS_REG_LDO_SEL))
+#define BIT_GET_REG_LDO_SEL(x) \
+ (((x) >> BIT_SHIFT_REG_LDO_SEL) & BIT_MASK_REG_LDO_SEL)
+#define BIT_SET_REG_LDO_SEL(x, v) \
+ (BIT_CLEAR_REG_LDO_SEL(x) | BIT_REG_LDO_SEL(v))
-#define BIT_SHIFT_REG_LDO_SEL 12
-#define BIT_MASK_REG_LDO_SEL 0x3
-#define BIT_REG_LDO_SEL(x) (((x) & BIT_MASK_REG_LDO_SEL) << BIT_SHIFT_REG_LDO_SEL)
-#define BIT_GET_REG_LDO_SEL(x) (((x) >> BIT_SHIFT_REG_LDO_SEL) & BIT_MASK_REG_LDO_SEL)
-
-#define BIT_REG_KVCO_V2 BIT(10)
+#define BIT_REG_KVCO_V2 BIT(10)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-
-/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-
-#define BIT_AGPIO_GPO BIT(9)
+#define BIT_AGPIO_GPO BIT(9)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-
-#define BIT_SHIFT_APLL_BIAS 8
-#define BIT_MASK_APLL_BIAS 0x7
-#define BIT_APLL_BIAS(x) (((x) & BIT_MASK_APLL_BIAS) << BIT_SHIFT_APLL_BIAS)
-#define BIT_GET_APLL_BIAS(x) (((x) >> BIT_SHIFT_APLL_BIAS) & BIT_MASK_APLL_BIAS)
-
+#define BIT_SHIFT_APLL_BIAS 8
+#define BIT_MASK_APLL_BIAS 0x7
+#define BIT_APLL_BIAS(x) (((x) & BIT_MASK_APLL_BIAS) << BIT_SHIFT_APLL_BIAS)
+#define BITS_APLL_BIAS (BIT_MASK_APLL_BIAS << BIT_SHIFT_APLL_BIAS)
+#define BIT_CLEAR_APLL_BIAS(x) ((x) & (~BITS_APLL_BIAS))
+#define BIT_GET_APLL_BIAS(x) (((x) >> BIT_SHIFT_APLL_BIAS) & BIT_MASK_APLL_BIAS)
+#define BIT_SET_APLL_BIAS(x, v) (BIT_CLEAR_APLL_BIAS(x) | BIT_APLL_BIAS(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
+#define BIT_SHIFT_AGPIO_DRV 7
+#define BIT_MASK_AGPIO_DRV 0x3
+#define BIT_AGPIO_DRV(x) (((x) & BIT_MASK_AGPIO_DRV) << BIT_SHIFT_AGPIO_DRV)
+#define BITS_AGPIO_DRV (BIT_MASK_AGPIO_DRV << BIT_SHIFT_AGPIO_DRV)
+#define BIT_CLEAR_AGPIO_DRV(x) ((x) & (~BITS_AGPIO_DRV))
+#define BIT_GET_AGPIO_DRV(x) (((x) >> BIT_SHIFT_AGPIO_DRV) & BIT_MASK_AGPIO_DRV)
+#define BIT_SET_AGPIO_DRV(x, v) (BIT_CLEAR_AGPIO_DRV(x) | BIT_AGPIO_DRV(v))
-/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define BIT_SHIFT_AGPIO_DRV 7
-#define BIT_MASK_AGPIO_DRV 0x3
-#define BIT_AGPIO_DRV(x) (((x) & BIT_MASK_AGPIO_DRV) << BIT_SHIFT_AGPIO_DRV)
-#define BIT_GET_AGPIO_DRV(x) (((x) >> BIT_SHIFT_AGPIO_DRV) & BIT_MASK_AGPIO_DRV)
+/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
+#define BIT_SHIFT_REG_V15_3_TO_0_V1 7
+#define BIT_MASK_REG_V15_3_TO_0_V1 0xf
+#define BIT_REG_V15_3_TO_0_V1(x) \
+ (((x) & BIT_MASK_REG_V15_3_TO_0_V1) << BIT_SHIFT_REG_V15_3_TO_0_V1)
+#define BITS_REG_V15_3_TO_0_V1 \
+ (BIT_MASK_REG_V15_3_TO_0_V1 << BIT_SHIFT_REG_V15_3_TO_0_V1)
+#define BIT_CLEAR_REG_V15_3_TO_0_V1(x) ((x) & (~BITS_REG_V15_3_TO_0_V1))
+#define BIT_GET_REG_V15_3_TO_0_V1(x) \
+ (((x) >> BIT_SHIFT_REG_V15_3_TO_0_V1) & BIT_MASK_REG_V15_3_TO_0_V1)
+#define BIT_SET_REG_V15_3_TO_0_V1(x, v) \
+ (BIT_CLEAR_REG_V15_3_TO_0_V1(x) | BIT_REG_V15_3_TO_0_V1(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
+#define BIT_APLL_KVCO BIT(6)
-/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define BIT_SHIFT_REG_V15_3_TO_0_V1 7
-#define BIT_MASK_REG_V15_3_TO_0_V1 0xf
-#define BIT_REG_V15_3_TO_0_V1(x) (((x) & BIT_MASK_REG_V15_3_TO_0_V1) << BIT_SHIFT_REG_V15_3_TO_0_V1)
-#define BIT_GET_REG_V15_3_TO_0_V1(x) (((x) >> BIT_SHIFT_REG_V15_3_TO_0_V1) & BIT_MASK_REG_V15_3_TO_0_V1)
+/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
+#define BIT_REG_SEL_LDO_PC BIT(6)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-#define BIT_APLL_KVCO BIT(6)
+#define BIT_APLL_WDOGB BIT(4)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-#define BIT_REG_SEL_LDO_PC BIT(6)
+#define BIT_SHIFT_REG_CC_1_TO_0_V1 4
+#define BIT_MASK_REG_CC_1_TO_0_V1 0x3
+#define BIT_REG_CC_1_TO_0_V1(x) \
+ (((x) & BIT_MASK_REG_CC_1_TO_0_V1) << BIT_SHIFT_REG_CC_1_TO_0_V1)
+#define BITS_REG_CC_1_TO_0_V1 \
+ (BIT_MASK_REG_CC_1_TO_0_V1 << BIT_SHIFT_REG_CC_1_TO_0_V1)
+#define BIT_CLEAR_REG_CC_1_TO_0_V1(x) ((x) & (~BITS_REG_CC_1_TO_0_V1))
+#define BIT_GET_REG_CC_1_TO_0_V1(x) \
+ (((x) >> BIT_SHIFT_REG_CC_1_TO_0_V1) & BIT_MASK_REG_CC_1_TO_0_V1)
+#define BIT_SET_REG_CC_1_TO_0_V1(x, v) \
+ (BIT_CLEAR_REG_CC_1_TO_0_V1(x) | BIT_REG_CC_1_TO_0_V1(v))
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-#define BIT_APLL_WDOGB BIT(4)
+#define BIT_APLL_EDGE_SEL BIT(3)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-
-#define BIT_SHIFT_REG_CC_1_TO_0_V1 4
-#define BIT_MASK_REG_CC_1_TO_0_V1 0x3
-#define BIT_REG_CC_1_TO_0_V1(x) (((x) & BIT_MASK_REG_CC_1_TO_0_V1) << BIT_SHIFT_REG_CC_1_TO_0_V1)
-#define BIT_GET_REG_CC_1_TO_0_V1(x) (((x) >> BIT_SHIFT_REG_CC_1_TO_0_V1) & BIT_MASK_REG_CC_1_TO_0_V1)
-
+#define BIT_CKDELAY_USB_V1 BIT(3)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-#define BIT_APLL_EDGE_SEL BIT(3)
+#define BIT_APLL_FREF_SEL_BIT0 BIT(2)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-#define BIT_CKDELAY_USB_V1 BIT(3)
+#define BIT_CKDELAY_DIG_V1 BIT(2)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_ANAPARSW_POW_MAC (Offset 0x0028) */
+
+#define BIT_POW_LDO15 BIT(2)
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-#define BIT_APLL_FREF_SEL_BIT0 BIT(2)
+#define BIT_SHIFT_XTAL_CAP_XO 1
+#define BIT_MASK_XTAL_CAP_XO 0x3f
+#define BIT_XTAL_CAP_XO(x) \
+ (((x) & BIT_MASK_XTAL_CAP_XO) << BIT_SHIFT_XTAL_CAP_XO)
+#define BITS_XTAL_CAP_XO (BIT_MASK_XTAL_CAP_XO << BIT_SHIFT_XTAL_CAP_XO)
+#define BIT_CLEAR_XTAL_CAP_XO(x) ((x) & (~BITS_XTAL_CAP_XO))
+#define BIT_GET_XTAL_CAP_XO(x) \
+ (((x) >> BIT_SHIFT_XTAL_CAP_XO) & BIT_MASK_XTAL_CAP_XO)
+#define BIT_SET_XTAL_CAP_XO(x, v) \
+ (BIT_CLEAR_XTAL_CAP_XO(x) | BIT_XTAL_CAP_XO(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-#define BIT_CKDELAY_DIG_V1 BIT(2)
+#define BIT_MPLL_EN BIT(1)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ANAPARSW_POW_MAC (Offset 0x0028) */
+#define BIT_POW_SW BIT(1)
-/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_XTAL_CAP_XO 1
-#define BIT_MASK_XTAL_CAP_XO 0x3f
-#define BIT_XTAL_CAP_XO(x) (((x) & BIT_MASK_XTAL_CAP_XO) << BIT_SHIFT_XTAL_CAP_XO)
-#define BIT_GET_XTAL_CAP_XO(x) (((x) >> BIT_SHIFT_XTAL_CAP_XO) & BIT_MASK_XTAL_CAP_XO)
+/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
+#define BIT_APLL_EN BIT(0)
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
-#define BIT_MPLL_EN BIT(1)
+#define BIT_POW_PLL BIT(0)
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SDIO_OQT_FREE_TXPG_V1 (Offset 0x10250028) */
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)
+#define BIT_SHIFT_EXQ__FREEPG_V1 0
+#define BIT_MASK_EXQ__FREEPG_V1 0xfff
+#define BIT_EXQ__FREEPG_V1(x) \
+ (((x) & BIT_MASK_EXQ__FREEPG_V1) << BIT_SHIFT_EXQ__FREEPG_V1)
+#define BITS_EXQ__FREEPG_V1 \
+ (BIT_MASK_EXQ__FREEPG_V1 << BIT_SHIFT_EXQ__FREEPG_V1)
+#define BIT_CLEAR_EXQ__FREEPG_V1(x) ((x) & (~BITS_EXQ__FREEPG_V1))
+#define BIT_GET_EXQ__FREEPG_V1(x) \
+ (((x) >> BIT_SHIFT_EXQ__FREEPG_V1) & BIT_MASK_EXQ__FREEPG_V1)
+#define BIT_SET_EXQ__FREEPG_V1(x, v) \
+ (BIT_CLEAR_EXQ__FREEPG_V1(x) | BIT_EXQ__FREEPG_V1(v))
+#endif
-/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_APLL_EN BIT(0)
+/* 2 REG_SDIO_OQT_FREE_TXPG_V1 (Offset 0x10250028) */
+
+#define BIT_SHIFT_EXQ_FREEPG_V1 0
+#define BIT_MASK_EXQ_FREEPG_V1 0xfff
+#define BIT_EXQ_FREEPG_V1(x) \
+ (((x) & BIT_MASK_EXQ_FREEPG_V1) << BIT_SHIFT_EXQ_FREEPG_V1)
+#define BITS_EXQ_FREEPG_V1 (BIT_MASK_EXQ_FREEPG_V1 << BIT_SHIFT_EXQ_FREEPG_V1)
+#define BIT_CLEAR_EXQ_FREEPG_V1(x) ((x) & (~BITS_EXQ_FREEPG_V1))
+#define BIT_GET_EXQ_FREEPG_V1(x) \
+ (((x) >> BIT_SHIFT_EXQ_FREEPG_V1) & BIT_MASK_EXQ_FREEPG_V1)
+#define BIT_SET_EXQ_FREEPG_V1(x, v) \
+ (BIT_CLEAR_EXQ_FREEPG_V1(x) | BIT_EXQ_FREEPG_V1(v))
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ANAPARSW_POW_MAC (Offset 0x0028) */
+#define BIT_POW_LDO14 BIT(0)
-/* 2 REG_AFE_CTRL2 (Offset 0x0028) */
+/* 2 REG_ANAPARLDO_POW_MAC (Offset 0x0029) */
-#define BIT_POW_PLL BIT(0)
+#define BIT_LDOE25_POW_L BIT(0)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_ANAPAR_POW_MAC (Offset 0x002A) */
+#define BIT_REG_STANDBY_L BIT(19)
+#define BIT_PD_REGU_L BIT(18)
+#define BIT_EN_PC_BT_L BIT(17)
-/* 2 REG_SDIO_OQT_FREE_TXPG_V1 (Offset 0x10250028) */
+#define BIT_SHIFT_REG_LDOADJ_L 13
+#define BIT_MASK_REG_LDOADJ_L 0xf
+#define BIT_REG_LDOADJ_L(x) \
+ (((x) & BIT_MASK_REG_LDOADJ_L) << BIT_SHIFT_REG_LDOADJ_L)
+#define BITS_REG_LDOADJ_L (BIT_MASK_REG_LDOADJ_L << BIT_SHIFT_REG_LDOADJ_L)
+#define BIT_CLEAR_REG_LDOADJ_L(x) ((x) & (~BITS_REG_LDOADJ_L))
+#define BIT_GET_REG_LDOADJ_L(x) \
+ (((x) >> BIT_SHIFT_REG_LDOADJ_L) & BIT_MASK_REG_LDOADJ_L)
+#define BIT_SET_REG_LDOADJ_L(x, v) \
+ (BIT_CLEAR_REG_LDOADJ_L(x) | BIT_REG_LDOADJ_L(v))
+#define BIT_CK12M_EN BIT(11)
+#define BIT_CK12M_SEL BIT(10)
+#define BIT_EN_25_L BIT(9)
+#define BIT_EN_SLEEP BIT(8)
+#define BIT_DUMMY_V4 BIT(7)
+#define BIT_DUMMY_V3 BIT(6)
+#define BIT_DUMMY_V2 BIT(5)
+#define BIT_DUMMY_V1 BIT(4)
-#define BIT_SHIFT_EXQ__FREEPG_V1 0
-#define BIT_MASK_EXQ__FREEPG_V1 0xfff
-#define BIT_EXQ__FREEPG_V1(x) (((x) & BIT_MASK_EXQ__FREEPG_V1) << BIT_SHIFT_EXQ__FREEPG_V1)
-#define BIT_GET_EXQ__FREEPG_V1(x) (((x) >> BIT_SHIFT_EXQ__FREEPG_V1) & BIT_MASK_EXQ__FREEPG_V1)
+#define BIT_SHIFT_LDOH12_V12ADJ_L 4
+#define BIT_MASK_LDOH12_V12ADJ_L 0xf
+#define BIT_LDOH12_V12ADJ_L(x) \
+ (((x) & BIT_MASK_LDOH12_V12ADJ_L) << BIT_SHIFT_LDOH12_V12ADJ_L)
+#define BITS_LDOH12_V12ADJ_L \
+ (BIT_MASK_LDOH12_V12ADJ_L << BIT_SHIFT_LDOH12_V12ADJ_L)
+#define BIT_CLEAR_LDOH12_V12ADJ_L(x) ((x) & (~BITS_LDOH12_V12ADJ_L))
+#define BIT_GET_LDOH12_V12ADJ_L(x) \
+ (((x) >> BIT_SHIFT_LDOH12_V12ADJ_L) & BIT_MASK_LDOH12_V12ADJ_L)
+#define BIT_SET_LDOH12_V12ADJ_L(x, v) \
+ (BIT_CLEAR_LDOH12_V12ADJ_L(x) | BIT_LDOH12_V12ADJ_L(v))
+#define BIT_POW_PC_LDO_PORT1 BIT(3)
+#define BIT_POW_PC_LDO_PORT0 BIT(2)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ANAPAR_POW_MAC (Offset 0x002A) */
+#define BIT_POW_PLL_V1 BIT(1)
-/* 2 REG_SDIO_OQT_FREE_TXPG_V1 (Offset 0x10250028) */
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+/* 2 REG_ANAPAR_POW_MAC (Offset 0x002A) */
-#define BIT_SHIFT_EXQ_FREEPG_V1 0
-#define BIT_MASK_EXQ_FREEPG_V1 0xfff
-#define BIT_EXQ_FREEPG_V1(x) (((x) & BIT_MASK_EXQ_FREEPG_V1) << BIT_SHIFT_EXQ_FREEPG_V1)
-#define BIT_GET_EXQ_FREEPG_V1(x) (((x) >> BIT_SHIFT_EXQ_FREEPG_V1) & BIT_MASK_EXQ_FREEPG_V1)
+#define BIT_POW_POWER_CUT_POW_LDO BIT(0)
+#define BIT_SHIFT_LDOE25_V12ADJ_L_V1 0
+#define BIT_MASK_LDOE25_V12ADJ_L_V1 0xf
+#define BIT_LDOE25_V12ADJ_L_V1(x) \
+ (((x) & BIT_MASK_LDOE25_V12ADJ_L_V1) << BIT_SHIFT_LDOE25_V12ADJ_L_V1)
+#define BITS_LDOE25_V12ADJ_L_V1 \
+ (BIT_MASK_LDOE25_V12ADJ_L_V1 << BIT_SHIFT_LDOE25_V12ADJ_L_V1)
+#define BIT_CLEAR_LDOE25_V12ADJ_L_V1(x) ((x) & (~BITS_LDOE25_V12ADJ_L_V1))
+#define BIT_GET_LDOE25_V12ADJ_L_V1(x) \
+ (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_V1) & BIT_MASK_LDOE25_V12ADJ_L_V1)
+#define BIT_SET_LDOE25_V12ADJ_L_V1(x, v) \
+ (BIT_CLEAR_LDOE25_V12ADJ_L_V1(x) | BIT_LDOE25_V12ADJ_L_V1(v))
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_ANAPAR_POW_XTAL (Offset 0x002B) */
+#define BIT_PSTIMER_2 BIT(31)
+#define BIT_PSTIMER_1 BIT(30)
+#define BIT_PSTIMER_0 BIT(29)
+#define BIT_TXDMA_START_INT BIT(23)
+#define BIT_TXDMA_STOP_INT BIT(22)
+#define BIT_HISR7_IND BIT(21)
+#define BIT_HISR6_IND BIT(19)
+#define BIT_HISR5_IND BIT(18)
+#define BIT_HISR4_IND BIT(17)
+#define BIT_HISR3_IND BIT(14)
+#define BIT_HISR2_IND BIT(13)
+#define BIT_POW_XTAL BIT(1)
+#define BIT_POW_BG BIT(0)
-/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_XTAL_RF2_DRV 30
-#define BIT_MASK_XTAL_RF2_DRV 0x3
-#define BIT_XTAL_RF2_DRV(x) (((x) & BIT_MASK_XTAL_RF2_DRV) << BIT_SHIFT_XTAL_RF2_DRV)
-#define BIT_GET_XTAL_RF2_DRV(x) (((x) >> BIT_SHIFT_XTAL_RF2_DRV) & BIT_MASK_XTAL_RF2_DRV)
+/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
+#define BIT_SHIFT_XTAL_RF2_DRV 30
+#define BIT_MASK_XTAL_RF2_DRV 0x3
+#define BIT_XTAL_RF2_DRV(x) \
+ (((x) & BIT_MASK_XTAL_RF2_DRV) << BIT_SHIFT_XTAL_RF2_DRV)
+#define BITS_XTAL_RF2_DRV (BIT_MASK_XTAL_RF2_DRV << BIT_SHIFT_XTAL_RF2_DRV)
+#define BIT_CLEAR_XTAL_RF2_DRV(x) ((x) & (~BITS_XTAL_RF2_DRV))
+#define BIT_GET_XTAL_RF2_DRV(x) \
+ (((x) >> BIT_SHIFT_XTAL_RF2_DRV) & BIT_MASK_XTAL_RF2_DRV)
+#define BIT_SET_XTAL_RF2_DRV(x, v) \
+ (BIT_CLEAR_XTAL_RF2_DRV(x) | BIT_XTAL_RF2_DRV(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
-#define BIT_REG_REF_SEL_V3 BIT(30)
+#define BIT_REG_REF_SEL_V3 BIT(30)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
-#define BIT_XTAL_GMN_BIT4 BIT(29)
-#define BIT_XTAL_GMP_BIT4 BIT(28)
+#define BIT_XTAL_GMN_BIT4 BIT(29)
+#define BIT_XTAL_GMP_BIT4 BIT(28)
#endif
-
#if (HALMAC_8192E_SUPPORT)
-
/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
-#define BIT_XQSEL BIT(27)
+#define BIT_XQSEL BIT(27)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
-
-#define BIT_SHIFT_REG_FREF_SEL_2_TO_0 27
-#define BIT_MASK_REG_FREF_SEL_2_TO_0 0x7
-#define BIT_REG_FREF_SEL_2_TO_0(x) (((x) & BIT_MASK_REG_FREF_SEL_2_TO_0) << BIT_SHIFT_REG_FREF_SEL_2_TO_0)
-#define BIT_GET_REG_FREF_SEL_2_TO_0(x) (((x) >> BIT_SHIFT_REG_FREF_SEL_2_TO_0) & BIT_MASK_REG_FREF_SEL_2_TO_0)
-
+#define BIT_SHIFT_REG_FREF_SEL_2_TO_0 27
+#define BIT_MASK_REG_FREF_SEL_2_TO_0 0x7
+#define BIT_REG_FREF_SEL_2_TO_0(x) \
+ (((x) & BIT_MASK_REG_FREF_SEL_2_TO_0) << BIT_SHIFT_REG_FREF_SEL_2_TO_0)
+#define BITS_REG_FREF_SEL_2_TO_0 \
+ (BIT_MASK_REG_FREF_SEL_2_TO_0 << BIT_SHIFT_REG_FREF_SEL_2_TO_0)
+#define BIT_CLEAR_REG_FREF_SEL_2_TO_0(x) ((x) & (~BITS_REG_FREF_SEL_2_TO_0))
+#define BIT_GET_REG_FREF_SEL_2_TO_0(x) \
+ (((x) >> BIT_SHIFT_REG_FREF_SEL_2_TO_0) & BIT_MASK_REG_FREF_SEL_2_TO_0)
+#define BIT_SET_REG_FREF_SEL_2_TO_0(x, v) \
+ (BIT_CLEAR_REG_FREF_SEL_2_TO_0(x) | BIT_REG_FREF_SEL_2_TO_0(v))
#endif
-
#if (HALMAC_8881A_SUPPORT)
-
/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
-#define BIT_XQSEL_BIT0 BIT(27)
+#define BIT_XQSEL_BIT0 BIT(27)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
-#define BIT_APLL_DUMMY BIT(26)
+#define BIT_APLL_DUMMY BIT(26)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
-
-#define BIT_SHIFT_XTAL_CADJ_XOUT_5_TO_0_V1 21
-#define BIT_MASK_XTAL_CADJ_XOUT_5_TO_0_V1 0x3f
-#define BIT_XTAL_CADJ_XOUT_5_TO_0_V1(x) (((x) & BIT_MASK_XTAL_CADJ_XOUT_5_TO_0_V1) << BIT_SHIFT_XTAL_CADJ_XOUT_5_TO_0_V1)
-#define BIT_GET_XTAL_CADJ_XOUT_5_TO_0_V1(x) (((x) >> BIT_SHIFT_XTAL_CADJ_XOUT_5_TO_0_V1) & BIT_MASK_XTAL_CADJ_XOUT_5_TO_0_V1)
-
+#define BIT_SHIFT_XTAL_CADJ_XOUT_5_TO_0_V1 21
+#define BIT_MASK_XTAL_CADJ_XOUT_5_TO_0_V1 0x3f
+#define BIT_XTAL_CADJ_XOUT_5_TO_0_V1(x) \
+ (((x) & BIT_MASK_XTAL_CADJ_XOUT_5_TO_0_V1) \
+ << BIT_SHIFT_XTAL_CADJ_XOUT_5_TO_0_V1)
+#define BITS_XTAL_CADJ_XOUT_5_TO_0_V1 \
+ (BIT_MASK_XTAL_CADJ_XOUT_5_TO_0_V1 \
+ << BIT_SHIFT_XTAL_CADJ_XOUT_5_TO_0_V1)
+#define BIT_CLEAR_XTAL_CADJ_XOUT_5_TO_0_V1(x) \
+ ((x) & (~BITS_XTAL_CADJ_XOUT_5_TO_0_V1))
+#define BIT_GET_XTAL_CADJ_XOUT_5_TO_0_V1(x) \
+ (((x) >> BIT_SHIFT_XTAL_CADJ_XOUT_5_TO_0_V1) & \
+ BIT_MASK_XTAL_CADJ_XOUT_5_TO_0_V1)
+#define BIT_SET_XTAL_CADJ_XOUT_5_TO_0_V1(x, v) \
+ (BIT_CLEAR_XTAL_CADJ_XOUT_5_TO_0_V1(x) | \
+ BIT_XTAL_CADJ_XOUT_5_TO_0_V1(v))
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
-
-#define BIT_SHIFT_XTAL_CADJ_XOUT 18
-#define BIT_MASK_XTAL_CADJ_XOUT 0x3f
-#define BIT_XTAL_CADJ_XOUT(x) (((x) & BIT_MASK_XTAL_CADJ_XOUT) << BIT_SHIFT_XTAL_CADJ_XOUT)
-#define BIT_GET_XTAL_CADJ_XOUT(x) (((x) >> BIT_SHIFT_XTAL_CADJ_XOUT) & BIT_MASK_XTAL_CADJ_XOUT)
-
+#define BIT_SHIFT_XTAL_CADJ_XOUT 18
+#define BIT_MASK_XTAL_CADJ_XOUT 0x3f
+#define BIT_XTAL_CADJ_XOUT(x) \
+ (((x) & BIT_MASK_XTAL_CADJ_XOUT) << BIT_SHIFT_XTAL_CADJ_XOUT)
+#define BITS_XTAL_CADJ_XOUT \
+ (BIT_MASK_XTAL_CADJ_XOUT << BIT_SHIFT_XTAL_CADJ_XOUT)
+#define BIT_CLEAR_XTAL_CADJ_XOUT(x) ((x) & (~BITS_XTAL_CADJ_XOUT))
+#define BIT_GET_XTAL_CADJ_XOUT(x) \
+ (((x) >> BIT_SHIFT_XTAL_CADJ_XOUT) & BIT_MASK_XTAL_CADJ_XOUT)
+#define BIT_SET_XTAL_CADJ_XOUT(x, v) \
+ (BIT_CLEAR_XTAL_CADJ_XOUT(x) | BIT_XTAL_CADJ_XOUT(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
-
-#define BIT_SHIFT_XTAL_CADJ_XIN_V2 15
-#define BIT_MASK_XTAL_CADJ_XIN_V2 0x3f
-#define BIT_XTAL_CADJ_XIN_V2(x) (((x) & BIT_MASK_XTAL_CADJ_XIN_V2) << BIT_SHIFT_XTAL_CADJ_XIN_V2)
-#define BIT_GET_XTAL_CADJ_XIN_V2(x) (((x) >> BIT_SHIFT_XTAL_CADJ_XIN_V2) & BIT_MASK_XTAL_CADJ_XIN_V2)
-
+#define BIT_SHIFT_XTAL_CADJ_XIN_V2 15
+#define BIT_MASK_XTAL_CADJ_XIN_V2 0x3f
+#define BIT_XTAL_CADJ_XIN_V2(x) \
+ (((x) & BIT_MASK_XTAL_CADJ_XIN_V2) << BIT_SHIFT_XTAL_CADJ_XIN_V2)
+#define BITS_XTAL_CADJ_XIN_V2 \
+ (BIT_MASK_XTAL_CADJ_XIN_V2 << BIT_SHIFT_XTAL_CADJ_XIN_V2)
+#define BIT_CLEAR_XTAL_CADJ_XIN_V2(x) ((x) & (~BITS_XTAL_CADJ_XIN_V2))
+#define BIT_GET_XTAL_CADJ_XIN_V2(x) \
+ (((x) >> BIT_SHIFT_XTAL_CADJ_XIN_V2) & BIT_MASK_XTAL_CADJ_XIN_V2)
+#define BIT_SET_XTAL_CADJ_XIN_V2(x, v) \
+ (BIT_CLEAR_XTAL_CADJ_XIN_V2(x) | BIT_XTAL_CADJ_XIN_V2(v))
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
-
-#define BIT_SHIFT_XTAL_CADJ_XIN 12
-#define BIT_MASK_XTAL_CADJ_XIN 0x3f
-#define BIT_XTAL_CADJ_XIN(x) (((x) & BIT_MASK_XTAL_CADJ_XIN) << BIT_SHIFT_XTAL_CADJ_XIN)
-#define BIT_GET_XTAL_CADJ_XIN(x) (((x) >> BIT_SHIFT_XTAL_CADJ_XIN) & BIT_MASK_XTAL_CADJ_XIN)
-
+#define BIT_SHIFT_XTAL_CADJ_XIN 12
+#define BIT_MASK_XTAL_CADJ_XIN 0x3f
+#define BIT_XTAL_CADJ_XIN(x) \
+ (((x) & BIT_MASK_XTAL_CADJ_XIN) << BIT_SHIFT_XTAL_CADJ_XIN)
+#define BITS_XTAL_CADJ_XIN (BIT_MASK_XTAL_CADJ_XIN << BIT_SHIFT_XTAL_CADJ_XIN)
+#define BIT_CLEAR_XTAL_CADJ_XIN(x) ((x) & (~BITS_XTAL_CADJ_XIN))
+#define BIT_GET_XTAL_CADJ_XIN(x) \
+ (((x) >> BIT_SHIFT_XTAL_CADJ_XIN) & BIT_MASK_XTAL_CADJ_XIN)
+#define BIT_SET_XTAL_CADJ_XIN(x, v) \
+ (BIT_CLEAR_XTAL_CADJ_XIN(x) | BIT_XTAL_CADJ_XIN(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
-
-#define BIT_SHIFT_REG_RS_V3 12
-#define BIT_MASK_REG_RS_V3 0x7
-#define BIT_REG_RS_V3(x) (((x) & BIT_MASK_REG_RS_V3) << BIT_SHIFT_REG_RS_V3)
-#define BIT_GET_REG_RS_V3(x) (((x) >> BIT_SHIFT_REG_RS_V3) & BIT_MASK_REG_RS_V3)
-
+#define BIT_SHIFT_REG_RS_V3 12
+#define BIT_MASK_REG_RS_V3 0x7
+#define BIT_REG_RS_V3(x) (((x) & BIT_MASK_REG_RS_V3) << BIT_SHIFT_REG_RS_V3)
+#define BITS_REG_RS_V3 (BIT_MASK_REG_RS_V3 << BIT_SHIFT_REG_RS_V3)
+#define BIT_CLEAR_REG_RS_V3(x) ((x) & (~BITS_REG_RS_V3))
+#define BIT_GET_REG_RS_V3(x) (((x) >> BIT_SHIFT_REG_RS_V3) & BIT_MASK_REG_RS_V3)
+#define BIT_SET_REG_RS_V3(x, v) (BIT_CLEAR_REG_RS_V3(x) | BIT_REG_RS_V3(v))
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */
+#define BIT_SDIO_BCNQ_EMPTY BIT(11)
+#define BIT_SDIO_HQQ_EMPTY BIT(10)
-/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_REG_RS 9
-#define BIT_MASK_REG_RS 0x7
-#define BIT_REG_RS(x) (((x) & BIT_MASK_REG_RS) << BIT_SHIFT_REG_RS)
-#define BIT_GET_REG_RS(x) (((x) >> BIT_SHIFT_REG_RS) & BIT_MASK_REG_RS)
+/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
+#define BIT_SHIFT_REG_RS 9
+#define BIT_MASK_REG_RS 0x7
+#define BIT_REG_RS(x) (((x) & BIT_MASK_REG_RS) << BIT_SHIFT_REG_RS)
+#define BITS_REG_RS (BIT_MASK_REG_RS << BIT_SHIFT_REG_RS)
+#define BIT_CLEAR_REG_RS(x) ((x) & (~BITS_REG_RS))
+#define BIT_GET_REG_RS(x) (((x) >> BIT_SHIFT_REG_RS) & BIT_MASK_REG_RS)
+#define BIT_SET_REG_RS(x, v) (BIT_CLEAR_REG_RS(x) | BIT_REG_RS(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
-
-#define BIT_SHIFT_REG_R3_V3 9
-#define BIT_MASK_REG_R3_V3 0x7
-#define BIT_REG_R3_V3(x) (((x) & BIT_MASK_REG_R3_V3) << BIT_SHIFT_REG_R3_V3)
-#define BIT_GET_REG_R3_V3(x) (((x) >> BIT_SHIFT_REG_R3_V3) & BIT_MASK_REG_R3_V3)
-
+#define BIT_SHIFT_REG_R3_V3 9
+#define BIT_MASK_REG_R3_V3 0x7
+#define BIT_REG_R3_V3(x) (((x) & BIT_MASK_REG_R3_V3) << BIT_SHIFT_REG_R3_V3)
+#define BITS_REG_R3_V3 (BIT_MASK_REG_R3_V3 << BIT_SHIFT_REG_R3_V3)
+#define BIT_CLEAR_REG_R3_V3(x) ((x) & (~BITS_REG_R3_V3))
+#define BIT_GET_REG_R3_V3(x) (((x) >> BIT_SHIFT_REG_R3_V3) & BIT_MASK_REG_R3_V3)
+#define BIT_SET_REG_R3_V3(x, v) (BIT_CLEAR_REG_R3_V3(x) | BIT_REG_R3_V3(v))
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */
+#define BIT_SDIO_MQQ_EMPTY BIT(9)
+#define BIT_SDIO_MGQ_CPU_EMPTY BIT(8)
-/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_PS_V2 7
-#define BIT_MASK_PS_V2 0x7
-#define BIT_PS_V2(x) (((x) & BIT_MASK_PS_V2) << BIT_SHIFT_PS_V2)
-#define BIT_GET_PS_V2(x) (((x) >> BIT_SHIFT_PS_V2) & BIT_MASK_PS_V2)
+/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
+#define BIT_SHIFT_PS_V2 7
+#define BIT_MASK_PS_V2 0x7
+#define BIT_PS_V2(x) (((x) & BIT_MASK_PS_V2) << BIT_SHIFT_PS_V2)
+#define BITS_PS_V2 (BIT_MASK_PS_V2 << BIT_SHIFT_PS_V2)
+#define BIT_CLEAR_PS_V2(x) ((x) & (~BITS_PS_V2))
+#define BIT_GET_PS_V2(x) (((x) >> BIT_SHIFT_PS_V2) & BIT_MASK_PS_V2)
+#define BIT_SET_PS_V2(x, v) (BIT_CLEAR_PS_V2(x) | BIT_PS_V2(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
-
-#define BIT_SHIFT_REG_CS_V3 7
-#define BIT_MASK_REG_CS_V3 0x3
-#define BIT_REG_CS_V3(x) (((x) & BIT_MASK_REG_CS_V3) << BIT_SHIFT_REG_CS_V3)
-#define BIT_GET_REG_CS_V3(x) (((x) >> BIT_SHIFT_REG_CS_V3) & BIT_MASK_REG_CS_V3)
-
+#define BIT_SHIFT_REG_CS_V3 7
+#define BIT_MASK_REG_CS_V3 0x3
+#define BIT_REG_CS_V3(x) (((x) & BIT_MASK_REG_CS_V3) << BIT_SHIFT_REG_CS_V3)
+#define BITS_REG_CS_V3 (BIT_MASK_REG_CS_V3 << BIT_SHIFT_REG_CS_V3)
+#define BIT_CLEAR_REG_CS_V3(x) ((x) & (~BITS_REG_CS_V3))
+#define BIT_GET_REG_CS_V3(x) (((x) >> BIT_SHIFT_REG_CS_V3) & BIT_MASK_REG_CS_V3)
+#define BIT_SET_REG_CS_V3(x, v) (BIT_CLEAR_REG_CS_V3(x) | BIT_REG_CS_V3(v))
#endif
-
#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
+#define BIT_SHIFT_PS 7
+#define BIT_MASK_PS 0x7
+#define BIT_PS(x) (((x) & BIT_MASK_PS) << BIT_SHIFT_PS)
+#define BITS_PS (BIT_MASK_PS << BIT_SHIFT_PS)
+#define BIT_CLEAR_PS(x) ((x) & (~BITS_PS))
+#define BIT_GET_PS(x) (((x) >> BIT_SHIFT_PS) & BIT_MASK_PS)
+#define BIT_SET_PS(x, v) (BIT_CLEAR_PS(x) | BIT_PS(v))
-#define BIT_SHIFT_PS 7
-#define BIT_MASK_PS 0x7
-#define BIT_PS(x) (((x) & BIT_MASK_PS) << BIT_SHIFT_PS)
-#define BIT_GET_PS(x) (((x) >> BIT_SHIFT_PS) & BIT_MASK_PS)
+#endif
+#if (HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */
+#define BIT_SDIO_AC7Q_EMPTY BIT(7)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
+#define BIT_SHIFT_REG_R3 6
+#define BIT_MASK_REG_R3 0x7
+#define BIT_REG_R3(x) (((x) & BIT_MASK_REG_R3) << BIT_SHIFT_REG_R3)
+#define BITS_REG_R3 (BIT_MASK_REG_R3 << BIT_SHIFT_REG_R3)
+#define BIT_CLEAR_REG_R3(x) ((x) & (~BITS_REG_R3))
+#define BIT_GET_REG_R3(x) (((x) >> BIT_SHIFT_REG_R3) & BIT_MASK_REG_R3)
+#define BIT_SET_REG_R3(x, v) (BIT_CLEAR_REG_R3(x) | BIT_REG_R3(v))
-#define BIT_SHIFT_REG_R3 6
-#define BIT_MASK_REG_R3 0x7
-#define BIT_REG_R3(x) (((x) & BIT_MASK_REG_R3) << BIT_SHIFT_REG_R3)
-#define BIT_GET_REG_R3(x) (((x) >> BIT_SHIFT_REG_R3) & BIT_MASK_REG_R3)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
-#endif
+/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
+#define BIT_PSEN BIT(6)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8822C_SUPPORT)
-/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
+/* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */
-#define BIT_PSEN BIT(6)
-#define BIT_DOGENB BIT(5)
+#define BIT_SDIO_AC6Q_EMPTY BIT(6)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
-#if (HALMAC_8814A_SUPPORT)
+/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
+#define BIT_DOGENB BIT(5)
-/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
+#endif
+#if (HALMAC_8814A_SUPPORT)
-#define BIT_SHIFT_REG_CP_V3 5
-#define BIT_MASK_REG_CP_V3 0x3
-#define BIT_REG_CP_V3(x) (((x) & BIT_MASK_REG_CP_V3) << BIT_SHIFT_REG_CP_V3)
-#define BIT_GET_REG_CP_V3(x) (((x) >> BIT_SHIFT_REG_CP_V3) & BIT_MASK_REG_CP_V3)
+/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
+#define BIT_SHIFT_REG_CP_V3 5
+#define BIT_MASK_REG_CP_V3 0x3
+#define BIT_REG_CP_V3(x) (((x) & BIT_MASK_REG_CP_V3) << BIT_SHIFT_REG_CP_V3)
+#define BITS_REG_CP_V3 (BIT_MASK_REG_CP_V3 << BIT_SHIFT_REG_CP_V3)
+#define BIT_CLEAR_REG_CP_V3(x) ((x) & (~BITS_REG_CP_V3))
+#define BIT_GET_REG_CP_V3(x) (((x) >> BIT_SHIFT_REG_CP_V3) & BIT_MASK_REG_CP_V3)
+#define BIT_SET_REG_CP_V3(x, v) (BIT_CLEAR_REG_CP_V3(x) | BIT_REG_CP_V3(v))
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */
+#define BIT_SDIO_AC5Q_EMPTY BIT(5)
-/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_REG_CS 4
-#define BIT_MASK_REG_CS 0x3
-#define BIT_REG_CS(x) (((x) & BIT_MASK_REG_CS) << BIT_SHIFT_REG_CS)
-#define BIT_GET_REG_CS(x) (((x) >> BIT_SHIFT_REG_CS) & BIT_MASK_REG_CS)
+/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
+#define BIT_SHIFT_REG_CS 4
+#define BIT_MASK_REG_CS 0x3
+#define BIT_REG_CS(x) (((x) & BIT_MASK_REG_CS) << BIT_SHIFT_REG_CS)
+#define BITS_REG_CS (BIT_MASK_REG_CS << BIT_SHIFT_REG_CS)
+#define BIT_CLEAR_REG_CS(x) ((x) & (~BITS_REG_CS))
+#define BIT_GET_REG_CS(x) (((x) >> BIT_SHIFT_REG_CS) & BIT_MASK_REG_CS)
+#define BIT_SET_REG_CS(x, v) (BIT_CLEAR_REG_CS(x) | BIT_REG_CS(v))
#endif
-
#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
-#define BIT_REG_MBIAS BIT(4)
+#define BIT_REG_MBIAS BIT(4)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT)
+/* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */
+#define BIT_SDIO_AC4Q_EMPTY BIT(4)
-/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
+#endif
+#if (HALMAC_8814A_SUPPORT)
-#define BIT_SHIFT_REG_C3_V3 3
-#define BIT_MASK_REG_C3_V3 0x3
-#define BIT_REG_C3_V3(x) (((x) & BIT_MASK_REG_C3_V3) << BIT_SHIFT_REG_C3_V3)
-#define BIT_GET_REG_C3_V3(x) (((x) >> BIT_SHIFT_REG_C3_V3) & BIT_MASK_REG_C3_V3)
+/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
+#define BIT_SHIFT_REG_C3_V3 3
+#define BIT_MASK_REG_C3_V3 0x3
+#define BIT_REG_C3_V3(x) (((x) & BIT_MASK_REG_C3_V3) << BIT_SHIFT_REG_C3_V3)
+#define BITS_REG_C3_V3 (BIT_MASK_REG_C3_V3 << BIT_SHIFT_REG_C3_V3)
+#define BIT_CLEAR_REG_C3_V3(x) ((x) & (~BITS_REG_C3_V3))
+#define BIT_GET_REG_C3_V3(x) (((x) >> BIT_SHIFT_REG_C3_V3) & BIT_MASK_REG_C3_V3)
+#define BIT_SET_REG_C3_V3(x, v) (BIT_CLEAR_REG_C3_V3(x) | BIT_REG_C3_V3(v))
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */
+#define BIT_SDIO_AC3Q_EMPTY BIT(3)
-/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_REG_CP 2
-#define BIT_MASK_REG_CP 0x3
-#define BIT_REG_CP(x) (((x) & BIT_MASK_REG_CP) << BIT_SHIFT_REG_CP)
-#define BIT_GET_REG_CP(x) (((x) >> BIT_SHIFT_REG_CP) & BIT_MASK_REG_CP)
+/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
+#define BIT_SHIFT_REG_CP 2
+#define BIT_MASK_REG_CP 0x3
+#define BIT_REG_CP(x) (((x) & BIT_MASK_REG_CP) << BIT_SHIFT_REG_CP)
+#define BITS_REG_CP (BIT_MASK_REG_CP << BIT_SHIFT_REG_CP)
+#define BIT_CLEAR_REG_CP(x) ((x) & (~BITS_REG_CP))
+#define BIT_GET_REG_CP(x) (((x) >> BIT_SHIFT_REG_CP) & BIT_MASK_REG_CP)
+#define BIT_SET_REG_CP(x, v) (BIT_CLEAR_REG_CP(x) | BIT_REG_CP(v))
#endif
-
#if (HALMAC_8814A_SUPPORT)
-
/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
-#define BIT_REG_320_SEL_V3 BIT(2)
+#define BIT_REG_320_SEL_V3 BIT(2)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */
+
+#define BIT_SDIO_AC2Q_EMPTY BIT(2)
+
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
-#define BIT_EN_SYN_V1 BIT(1)
+#define BIT_EN_SYN_V1 BIT(1)
#endif
-
#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
-
-#define BIT_SHIFT_REG_R3_V4 1
-#define BIT_MASK_REG_R3_V4 0x7
-#define BIT_REG_R3_V4(x) (((x) & BIT_MASK_REG_R3_V4) << BIT_SHIFT_REG_R3_V4)
-#define BIT_GET_REG_R3_V4(x) (((x) >> BIT_SHIFT_REG_R3_V4) & BIT_MASK_REG_R3_V4)
-
+#define BIT_SHIFT_REG_R3_V4 1
+#define BIT_MASK_REG_R3_V4 0x7
+#define BIT_REG_R3_V4(x) (((x) & BIT_MASK_REG_R3_V4) << BIT_SHIFT_REG_R3_V4)
+#define BITS_REG_R3_V4 (BIT_MASK_REG_R3_V4 << BIT_SHIFT_REG_R3_V4)
+#define BIT_CLEAR_REG_R3_V4(x) ((x) & (~BITS_REG_R3_V4))
+#define BIT_GET_REG_R3_V4(x) (((x) >> BIT_SHIFT_REG_R3_V4) & BIT_MASK_REG_R3_V4)
+#define BIT_SET_REG_R3_V4(x, v) (BIT_CLEAR_REG_R3_V4(x) | BIT_REG_R3_V4(v))
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */
+#define BIT_SDIO_AC1Q_EMPTY BIT(1)
-/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_REG_C3 0
-#define BIT_MASK_REG_C3 0x3
-#define BIT_REG_C3(x) (((x) & BIT_MASK_REG_C3) << BIT_SHIFT_REG_C3)
-#define BIT_GET_REG_C3(x) (((x) >> BIT_SHIFT_REG_C3) & BIT_MASK_REG_C3)
+/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
+#define BIT_SHIFT_REG_C3 0
+#define BIT_MASK_REG_C3 0x3
+#define BIT_REG_C3(x) (((x) & BIT_MASK_REG_C3) << BIT_SHIFT_REG_C3)
+#define BITS_REG_C3 (BIT_MASK_REG_C3 << BIT_SHIFT_REG_C3)
+#define BIT_CLEAR_REG_C3(x) ((x) & (~BITS_REG_C3))
+#define BIT_GET_REG_C3(x) (((x) >> BIT_SHIFT_REG_C3) & BIT_MASK_REG_C3)
+#define BIT_SET_REG_C3(x, v) (BIT_CLEAR_REG_C3(x) | BIT_REG_C3(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
-#define BIT_IOOFFSET_BIT4 BIT(0)
+#define BIT_IOOFFSET_BIT4 BIT(0)
#endif
-
#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
/* 2 REG_AFE_CTRL3 (Offset 0x002C) */
-#define BIT_REG_CP_BIT0 BIT(0)
+#define BIT_REG_CP_BIT0 BIT(0)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_SDIO_TXPKT_EMPTY (Offset 0x1025002C) */
+#define BIT_SDIO_AC0Q_EMPTY BIT(0)
-/* 2 REG_EFUSE_CTRL (Offset 0x0030) */
-
-#define BIT_EF_FLAG BIT(31)
+#endif
-#define BIT_SHIFT_EF_PGPD 28
-#define BIT_MASK_EF_PGPD 0x7
-#define BIT_EF_PGPD(x) (((x) & BIT_MASK_EF_PGPD) << BIT_SHIFT_EF_PGPD)
-#define BIT_GET_EF_PGPD(x) (((x) >> BIT_SHIFT_EF_PGPD) & BIT_MASK_EF_PGPD)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+/* 2 REG_EFUSE_CTRL (Offset 0x0030) */
-#define BIT_SHIFT_EF_RDT 24
-#define BIT_MASK_EF_RDT 0xf
-#define BIT_EF_RDT(x) (((x) & BIT_MASK_EF_RDT) << BIT_SHIFT_EF_RDT)
-#define BIT_GET_EF_RDT(x) (((x) >> BIT_SHIFT_EF_RDT) & BIT_MASK_EF_RDT)
+#define BIT_EF_FLAG BIT(31)
+#define BIT_SHIFT_EF_PGPD 28
+#define BIT_MASK_EF_PGPD 0x7
+#define BIT_EF_PGPD(x) (((x) & BIT_MASK_EF_PGPD) << BIT_SHIFT_EF_PGPD)
+#define BITS_EF_PGPD (BIT_MASK_EF_PGPD << BIT_SHIFT_EF_PGPD)
+#define BIT_CLEAR_EF_PGPD(x) ((x) & (~BITS_EF_PGPD))
+#define BIT_GET_EF_PGPD(x) (((x) >> BIT_SHIFT_EF_PGPD) & BIT_MASK_EF_PGPD)
+#define BIT_SET_EF_PGPD(x, v) (BIT_CLEAR_EF_PGPD(x) | BIT_EF_PGPD(v))
-#define BIT_SHIFT_EF_PGTS 20
-#define BIT_MASK_EF_PGTS 0xf
-#define BIT_EF_PGTS(x) (((x) & BIT_MASK_EF_PGTS) << BIT_SHIFT_EF_PGTS)
-#define BIT_GET_EF_PGTS(x) (((x) >> BIT_SHIFT_EF_PGTS) & BIT_MASK_EF_PGTS)
+#define BIT_SHIFT_EF_RDT 24
+#define BIT_MASK_EF_RDT 0xf
+#define BIT_EF_RDT(x) (((x) & BIT_MASK_EF_RDT) << BIT_SHIFT_EF_RDT)
+#define BITS_EF_RDT (BIT_MASK_EF_RDT << BIT_SHIFT_EF_RDT)
+#define BIT_CLEAR_EF_RDT(x) ((x) & (~BITS_EF_RDT))
+#define BIT_GET_EF_RDT(x) (((x) >> BIT_SHIFT_EF_RDT) & BIT_MASK_EF_RDT)
+#define BIT_SET_EF_RDT(x, v) (BIT_CLEAR_EF_RDT(x) | BIT_EF_RDT(v))
+#define BIT_SHIFT_EF_PGTS 20
+#define BIT_MASK_EF_PGTS 0xf
+#define BIT_EF_PGTS(x) (((x) & BIT_MASK_EF_PGTS) << BIT_SHIFT_EF_PGTS)
+#define BITS_EF_PGTS (BIT_MASK_EF_PGTS << BIT_SHIFT_EF_PGTS)
+#define BIT_CLEAR_EF_PGTS(x) ((x) & (~BITS_EF_PGTS))
+#define BIT_GET_EF_PGTS(x) (((x) >> BIT_SHIFT_EF_PGTS) & BIT_MASK_EF_PGTS)
+#define BIT_SET_EF_PGTS(x, v) (BIT_CLEAR_EF_PGTS(x) | BIT_EF_PGTS(v))
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_EFUSE_CTRL (Offset 0x0030) */
-#define BIT_EF_PDWN BIT(19)
+#define BIT_EF_PDWN BIT(19)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_EFUSE_CTRL (Offset 0x0030) */
-#define BIT_EF_ALDEN BIT(18)
+#define BIT_EF_ALDEN BIT(18)
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_HTSFR_INFO (Offset 0x10250030) */
-
-#define BIT_SHIFT_HTSFR1 16
-#define BIT_MASK_HTSFR1 0xffff
-#define BIT_HTSFR1(x) (((x) & BIT_MASK_HTSFR1) << BIT_SHIFT_HTSFR1)
-#define BIT_GET_HTSFR1(x) (((x) >> BIT_SHIFT_HTSFR1) & BIT_MASK_HTSFR1)
-
+#define BIT_SHIFT_HTSFR1 16
+#define BIT_MASK_HTSFR1 0xffff
+#define BIT_HTSFR1(x) (((x) & BIT_MASK_HTSFR1) << BIT_SHIFT_HTSFR1)
+#define BITS_HTSFR1 (BIT_MASK_HTSFR1 << BIT_SHIFT_HTSFR1)
+#define BIT_CLEAR_HTSFR1(x) ((x) & (~BITS_HTSFR1))
+#define BIT_GET_HTSFR1(x) (((x) >> BIT_SHIFT_HTSFR1) & BIT_MASK_HTSFR1)
+#define BIT_SET_HTSFR1(x, v) (BIT_CLEAR_HTSFR1(x) | BIT_HTSFR1(v))
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_EFUSE_CTRL (Offset 0x0030) */
+#define BIT_SHIFT_EF_ADDR 8
+#define BIT_MASK_EF_ADDR 0x3ff
+#define BIT_EF_ADDR(x) (((x) & BIT_MASK_EF_ADDR) << BIT_SHIFT_EF_ADDR)
+#define BITS_EF_ADDR (BIT_MASK_EF_ADDR << BIT_SHIFT_EF_ADDR)
+#define BIT_CLEAR_EF_ADDR(x) ((x) & (~BITS_EF_ADDR))
+#define BIT_GET_EF_ADDR(x) (((x) >> BIT_SHIFT_EF_ADDR) & BIT_MASK_EF_ADDR)
+#define BIT_SET_EF_ADDR(x, v) (BIT_CLEAR_EF_ADDR(x) | BIT_EF_ADDR(v))
-#define BIT_SHIFT_EF_ADDR 8
-#define BIT_MASK_EF_ADDR 0x3ff
-#define BIT_EF_ADDR(x) (((x) & BIT_MASK_EF_ADDR) << BIT_SHIFT_EF_ADDR)
-#define BIT_GET_EF_ADDR(x) (((x) >> BIT_SHIFT_EF_ADDR) & BIT_MASK_EF_ADDR)
-
-
-#define BIT_SHIFT_EF_DATA 0
-#define BIT_MASK_EF_DATA 0xff
-#define BIT_EF_DATA(x) (((x) & BIT_MASK_EF_DATA) << BIT_SHIFT_EF_DATA)
-#define BIT_GET_EF_DATA(x) (((x) >> BIT_SHIFT_EF_DATA) & BIT_MASK_EF_DATA)
-
+#define BIT_SHIFT_EF_DATA 0
+#define BIT_MASK_EF_DATA 0xff
+#define BIT_EF_DATA(x) (((x) & BIT_MASK_EF_DATA) << BIT_SHIFT_EF_DATA)
+#define BITS_EF_DATA (BIT_MASK_EF_DATA << BIT_SHIFT_EF_DATA)
+#define BIT_CLEAR_EF_DATA(x) ((x) & (~BITS_EF_DATA))
+#define BIT_GET_EF_DATA(x) (((x) >> BIT_SHIFT_EF_DATA) & BIT_MASK_EF_DATA)
+#define BIT_SET_EF_DATA(x, v) (BIT_CLEAR_EF_DATA(x) | BIT_EF_DATA(v))
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_HTSFR_INFO (Offset 0x10250030) */
-
-#define BIT_SHIFT_HTSFR0 0
-#define BIT_MASK_HTSFR0 0xffff
-#define BIT_HTSFR0(x) (((x) & BIT_MASK_HTSFR0) << BIT_SHIFT_HTSFR0)
-#define BIT_GET_HTSFR0(x) (((x) >> BIT_SHIFT_HTSFR0) & BIT_MASK_HTSFR0)
-
+#define BIT_SHIFT_HTSFR0 0
+#define BIT_MASK_HTSFR0 0xffff
+#define BIT_HTSFR0(x) (((x) & BIT_MASK_HTSFR0) << BIT_SHIFT_HTSFR0)
+#define BITS_HTSFR0 (BIT_MASK_HTSFR0 << BIT_SHIFT_HTSFR0)
+#define BIT_CLEAR_HTSFR0(x) ((x) & (~BITS_HTSFR0))
+#define BIT_GET_HTSFR0(x) (((x) >> BIT_SHIFT_HTSFR0) & BIT_MASK_HTSFR0)
+#define BIT_SET_HTSFR0(x, v) (BIT_CLEAR_HTSFR0(x) | BIT_HTSFR0(v))
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */
-#define BIT_LDOE25_EN BIT(31)
+#define BIT_LDOE25_EN BIT(31)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */
+#define BIT_SHIFT_LDOE25_VADJ_BIT0_TO_2 28
+#define BIT_MASK_LDOE25_VADJ_BIT0_TO_2 0x7
+#define BIT_LDOE25_VADJ_BIT0_TO_2(x) \
+ (((x) & BIT_MASK_LDOE25_VADJ_BIT0_TO_2) \
+ << BIT_SHIFT_LDOE25_VADJ_BIT0_TO_2)
+#define BITS_LDOE25_VADJ_BIT0_TO_2 \
+ (BIT_MASK_LDOE25_VADJ_BIT0_TO_2 << BIT_SHIFT_LDOE25_VADJ_BIT0_TO_2)
+#define BIT_CLEAR_LDOE25_VADJ_BIT0_TO_2(x) ((x) & (~BITS_LDOE25_VADJ_BIT0_TO_2))
+#define BIT_GET_LDOE25_VADJ_BIT0_TO_2(x) \
+ (((x) >> BIT_SHIFT_LDOE25_VADJ_BIT0_TO_2) & \
+ BIT_MASK_LDOE25_VADJ_BIT0_TO_2)
+#define BIT_SET_LDOE25_VADJ_BIT0_TO_2(x, v) \
+ (BIT_CLEAR_LDOE25_VADJ_BIT0_TO_2(x) | BIT_LDOE25_VADJ_BIT0_TO_2(v))
-#define BIT_SHIFT_LDOE25_VADJ_BIT0_TO_2 28
-#define BIT_MASK_LDOE25_VADJ_BIT0_TO_2 0x7
-#define BIT_LDOE25_VADJ_BIT0_TO_2(x) (((x) & BIT_MASK_LDOE25_VADJ_BIT0_TO_2) << BIT_SHIFT_LDOE25_VADJ_BIT0_TO_2)
-#define BIT_GET_LDOE25_VADJ_BIT0_TO_2(x) (((x) >> BIT_SHIFT_LDOE25_VADJ_BIT0_TO_2) & BIT_MASK_LDOE25_VADJ_BIT0_TO_2)
-
-#define BIT_LDOE25_VADJ_BIT3 BIT(27)
+#define BIT_LDOE25_VADJ_BIT3 BIT(27)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
/* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */
-
-#define BIT_SHIFT_LDOE25_V12ADJ_L 27
-#define BIT_MASK_LDOE25_V12ADJ_L 0xf
-#define BIT_LDOE25_V12ADJ_L(x) (((x) & BIT_MASK_LDOE25_V12ADJ_L) << BIT_SHIFT_LDOE25_V12ADJ_L)
-#define BIT_GET_LDOE25_V12ADJ_L(x) (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L) & BIT_MASK_LDOE25_V12ADJ_L)
-
+#define BIT_SHIFT_LDOE25_V12ADJ_L 27
+#define BIT_MASK_LDOE25_V12ADJ_L 0xf
+#define BIT_LDOE25_V12ADJ_L(x) \
+ (((x) & BIT_MASK_LDOE25_V12ADJ_L) << BIT_SHIFT_LDOE25_V12ADJ_L)
+#define BITS_LDOE25_V12ADJ_L \
+ (BIT_MASK_LDOE25_V12ADJ_L << BIT_SHIFT_LDOE25_V12ADJ_L)
+#define BIT_CLEAR_LDOE25_V12ADJ_L(x) ((x) & (~BITS_LDOE25_V12ADJ_L))
+#define BIT_GET_LDOE25_V12ADJ_L(x) \
+ (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L) & BIT_MASK_LDOE25_V12ADJ_L)
+#define BIT_SET_LDOE25_V12ADJ_L(x, v) \
+ (BIT_CLEAR_LDOE25_V12ADJ_L(x) | BIT_LDOE25_V12ADJ_L(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */
-
-#define BIT_SHIFT_LDOE25_VADJ_3_TO_0 27
-#define BIT_MASK_LDOE25_VADJ_3_TO_0 0xf
-#define BIT_LDOE25_VADJ_3_TO_0(x) (((x) & BIT_MASK_LDOE25_VADJ_3_TO_0) << BIT_SHIFT_LDOE25_VADJ_3_TO_0)
-#define BIT_GET_LDOE25_VADJ_3_TO_0(x) (((x) >> BIT_SHIFT_LDOE25_VADJ_3_TO_0) & BIT_MASK_LDOE25_VADJ_3_TO_0)
-
+#define BIT_SHIFT_LDOE25_VADJ_3_TO_0 27
+#define BIT_MASK_LDOE25_VADJ_3_TO_0 0xf
+#define BIT_LDOE25_VADJ_3_TO_0(x) \
+ (((x) & BIT_MASK_LDOE25_VADJ_3_TO_0) << BIT_SHIFT_LDOE25_VADJ_3_TO_0)
+#define BITS_LDOE25_VADJ_3_TO_0 \
+ (BIT_MASK_LDOE25_VADJ_3_TO_0 << BIT_SHIFT_LDOE25_VADJ_3_TO_0)
+#define BIT_CLEAR_LDOE25_VADJ_3_TO_0(x) ((x) & (~BITS_LDOE25_VADJ_3_TO_0))
+#define BIT_GET_LDOE25_VADJ_3_TO_0(x) \
+ (((x) >> BIT_SHIFT_LDOE25_VADJ_3_TO_0) & BIT_MASK_LDOE25_VADJ_3_TO_0)
+#define BIT_SET_LDOE25_VADJ_3_TO_0(x, v) \
+ (BIT_CLEAR_LDOE25_VADJ_3_TO_0(x) | BIT_LDOE25_VADJ_3_TO_0(v))
#endif
-
#if (HALMAC_8192E_SUPPORT)
-
/* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */
-#define BIT_EFCRES_SEL BIT(26)
+#define BIT_EFCRES_SEL BIT(26)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */
-#define BIT_EF_CSER BIT(26)
+#define BIT_EF_CSER BIT(26)
#endif
-
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */
-#define BIT_EF_CRES_SEL BIT(26)
+#define BIT_EF_CRES_SEL BIT(26)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */
-
-#define BIT_SHIFT_EF_SCAN_START 16
-#define BIT_MASK_EF_SCAN_START 0x1ff
-#define BIT_EF_SCAN_START(x) (((x) & BIT_MASK_EF_SCAN_START) << BIT_SHIFT_EF_SCAN_START)
-#define BIT_GET_EF_SCAN_START(x) (((x) >> BIT_SHIFT_EF_SCAN_START) & BIT_MASK_EF_SCAN_START)
-
+#define BIT_SHIFT_EF_SCAN_START 16
+#define BIT_MASK_EF_SCAN_START 0x1ff
+#define BIT_EF_SCAN_START(x) \
+ (((x) & BIT_MASK_EF_SCAN_START) << BIT_SHIFT_EF_SCAN_START)
+#define BITS_EF_SCAN_START (BIT_MASK_EF_SCAN_START << BIT_SHIFT_EF_SCAN_START)
+#define BIT_CLEAR_EF_SCAN_START(x) ((x) & (~BITS_EF_SCAN_START))
+#define BIT_GET_EF_SCAN_START(x) \
+ (((x) >> BIT_SHIFT_EF_SCAN_START) & BIT_MASK_EF_SCAN_START)
+#define BIT_SET_EF_SCAN_START(x, v) \
+ (BIT_CLEAR_EF_SCAN_START(x) | BIT_EF_SCAN_START(v))
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */
-
-#define BIT_SHIFT_EF_SCAN_START_V1 16
-#define BIT_MASK_EF_SCAN_START_V1 0x3ff
-#define BIT_EF_SCAN_START_V1(x) (((x) & BIT_MASK_EF_SCAN_START_V1) << BIT_SHIFT_EF_SCAN_START_V1)
-#define BIT_GET_EF_SCAN_START_V1(x) (((x) >> BIT_SHIFT_EF_SCAN_START_V1) & BIT_MASK_EF_SCAN_START_V1)
-
+#define BIT_SHIFT_EF_SCAN_START_V1 16
+#define BIT_MASK_EF_SCAN_START_V1 0x3ff
+#define BIT_EF_SCAN_START_V1(x) \
+ (((x) & BIT_MASK_EF_SCAN_START_V1) << BIT_SHIFT_EF_SCAN_START_V1)
+#define BITS_EF_SCAN_START_V1 \
+ (BIT_MASK_EF_SCAN_START_V1 << BIT_SHIFT_EF_SCAN_START_V1)
+#define BIT_CLEAR_EF_SCAN_START_V1(x) ((x) & (~BITS_EF_SCAN_START_V1))
+#define BIT_GET_EF_SCAN_START_V1(x) \
+ (((x) >> BIT_SHIFT_EF_SCAN_START_V1) & BIT_MASK_EF_SCAN_START_V1)
+#define BIT_SET_EF_SCAN_START_V1(x, v) \
+ (BIT_CLEAR_EF_SCAN_START_V1(x) | BIT_EF_SCAN_START_V1(v))
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */
-
-#define BIT_SHIFT_EF_SCAN_END 12
-#define BIT_MASK_EF_SCAN_END 0xf
-#define BIT_EF_SCAN_END(x) (((x) & BIT_MASK_EF_SCAN_END) << BIT_SHIFT_EF_SCAN_END)
-#define BIT_GET_EF_SCAN_END(x) (((x) >> BIT_SHIFT_EF_SCAN_END) & BIT_MASK_EF_SCAN_END)
-
+#define BIT_SHIFT_EF_SCAN_END 12
+#define BIT_MASK_EF_SCAN_END 0xf
+#define BIT_EF_SCAN_END(x) \
+ (((x) & BIT_MASK_EF_SCAN_END) << BIT_SHIFT_EF_SCAN_END)
+#define BITS_EF_SCAN_END (BIT_MASK_EF_SCAN_END << BIT_SHIFT_EF_SCAN_END)
+#define BIT_CLEAR_EF_SCAN_END(x) ((x) & (~BITS_EF_SCAN_END))
+#define BIT_GET_EF_SCAN_END(x) \
+ (((x) >> BIT_SHIFT_EF_SCAN_END) & BIT_MASK_EF_SCAN_END)
+#define BIT_SET_EF_SCAN_END(x, v) \
+ (BIT_CLEAR_EF_SCAN_END(x) | BIT_EF_SCAN_END(v))
#endif
-
#if (HALMAC_8192E_SUPPORT)
-
/* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */
-#define BIT_EF_FORCE_PGMEN BIT(11)
+#define BIT_EF_FORCE_PGMEN BIT(11)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */
-#define BIT_SCAN_EN BIT(11)
+#define BIT_SCAN_EN BIT(11)
#endif
-
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */
-#define BIT_EF_PD_DIS BIT(11)
+#define BIT_EF_PD_DIS BIT(11)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */
-#define BIT_SW_PG_EN BIT(10)
+#define BIT_SW_PG_EN BIT(10)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */
-
-#define BIT_SHIFT_EF_CELL_SEL 8
-#define BIT_MASK_EF_CELL_SEL 0x3
-#define BIT_EF_CELL_SEL(x) (((x) & BIT_MASK_EF_CELL_SEL) << BIT_SHIFT_EF_CELL_SEL)
-#define BIT_GET_EF_CELL_SEL(x) (((x) >> BIT_SHIFT_EF_CELL_SEL) & BIT_MASK_EF_CELL_SEL)
-
+#define BIT_SHIFT_EF_CELL_SEL 8
+#define BIT_MASK_EF_CELL_SEL 0x3
+#define BIT_EF_CELL_SEL(x) \
+ (((x) & BIT_MASK_EF_CELL_SEL) << BIT_SHIFT_EF_CELL_SEL)
+#define BITS_EF_CELL_SEL (BIT_MASK_EF_CELL_SEL << BIT_SHIFT_EF_CELL_SEL)
+#define BIT_CLEAR_EF_CELL_SEL(x) ((x) & (~BITS_EF_CELL_SEL))
+#define BIT_GET_EF_CELL_SEL(x) \
+ (((x) >> BIT_SHIFT_EF_CELL_SEL) & BIT_MASK_EF_CELL_SEL)
+#define BIT_SET_EF_CELL_SEL(x, v) \
+ (BIT_CLEAR_EF_CELL_SEL(x) | BIT_EF_CELL_SEL(v))
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */
-#define BIT_EF_TRPT BIT(7)
-
-#define BIT_SHIFT_EF_TTHD 0
-#define BIT_MASK_EF_TTHD 0x7f
-#define BIT_EF_TTHD(x) (((x) & BIT_MASK_EF_TTHD) << BIT_SHIFT_EF_TTHD)
-#define BIT_GET_EF_TTHD(x) (((x) >> BIT_SHIFT_EF_TTHD) & BIT_MASK_EF_TTHD)
+#define BIT_EF_TRPT BIT(7)
+#define BIT_SHIFT_EF_TTHD 0
+#define BIT_MASK_EF_TTHD 0x7f
+#define BIT_EF_TTHD(x) (((x) & BIT_MASK_EF_TTHD) << BIT_SHIFT_EF_TTHD)
+#define BITS_EF_TTHD (BIT_MASK_EF_TTHD << BIT_SHIFT_EF_TTHD)
+#define BIT_CLEAR_EF_TTHD(x) ((x) & (~BITS_EF_TTHD))
+#define BIT_GET_EF_TTHD(x) (((x) >> BIT_SHIFT_EF_TTHD) & BIT_MASK_EF_TTHD)
+#define BIT_SET_EF_TTHD(x, v) (BIT_CLEAR_EF_TTHD(x) | BIT_EF_TTHD(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
+
+#define BIT_SHIFT_AFE_USB_CURRENT_SEL 26
+#define BIT_MASK_AFE_USB_CURRENT_SEL 0x7
+#define BIT_AFE_USB_CURRENT_SEL(x) \
+ (((x) & BIT_MASK_AFE_USB_CURRENT_SEL) << BIT_SHIFT_AFE_USB_CURRENT_SEL)
+#define BITS_AFE_USB_CURRENT_SEL \
+ (BIT_MASK_AFE_USB_CURRENT_SEL << BIT_SHIFT_AFE_USB_CURRENT_SEL)
+#define BIT_CLEAR_AFE_USB_CURRENT_SEL(x) ((x) & (~BITS_AFE_USB_CURRENT_SEL))
+#define BIT_GET_AFE_USB_CURRENT_SEL(x) \
+ (((x) >> BIT_SHIFT_AFE_USB_CURRENT_SEL) & BIT_MASK_AFE_USB_CURRENT_SEL)
+#define BIT_SET_AFE_USB_CURRENT_SEL(x, v) \
+ (BIT_CLEAR_AFE_USB_CURRENT_SEL(x) | BIT_AFE_USB_CURRENT_SEL(v))
+
+#define BIT_SHIFT_AFE_USB_PATH_SEL 24
+#define BIT_MASK_AFE_USB_PATH_SEL 0x3
+#define BIT_AFE_USB_PATH_SEL(x) \
+ (((x) & BIT_MASK_AFE_USB_PATH_SEL) << BIT_SHIFT_AFE_USB_PATH_SEL)
+#define BITS_AFE_USB_PATH_SEL \
+ (BIT_MASK_AFE_USB_PATH_SEL << BIT_SHIFT_AFE_USB_PATH_SEL)
+#define BIT_CLEAR_AFE_USB_PATH_SEL(x) ((x) & (~BITS_AFE_USB_PATH_SEL))
+#define BIT_GET_AFE_USB_PATH_SEL(x) \
+ (((x) >> BIT_SHIFT_AFE_USB_PATH_SEL) & BIT_MASK_AFE_USB_PATH_SEL)
+#define BIT_SET_AFE_USB_PATH_SEL(x, v) \
+ (BIT_CLEAR_AFE_USB_PATH_SEL(x) | BIT_AFE_USB_PATH_SEL(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
+#define BIT_SHIFT_DBG_SEL_V1 16
+#define BIT_MASK_DBG_SEL_V1 0xff
+#define BIT_DBG_SEL_V1(x) (((x) & BIT_MASK_DBG_SEL_V1) << BIT_SHIFT_DBG_SEL_V1)
+#define BITS_DBG_SEL_V1 (BIT_MASK_DBG_SEL_V1 << BIT_SHIFT_DBG_SEL_V1)
+#define BIT_CLEAR_DBG_SEL_V1(x) ((x) & (~BITS_DBG_SEL_V1))
+#define BIT_GET_DBG_SEL_V1(x) \
+ (((x) >> BIT_SHIFT_DBG_SEL_V1) & BIT_MASK_DBG_SEL_V1)
+#define BIT_SET_DBG_SEL_V1(x, v) (BIT_CLEAR_DBG_SEL_V1(x) | BIT_DBG_SEL_V1(v))
-#define BIT_SHIFT_AFE_USB_CURRENT_SEL 26
-#define BIT_MASK_AFE_USB_CURRENT_SEL 0x7
-#define BIT_AFE_USB_CURRENT_SEL(x) (((x) & BIT_MASK_AFE_USB_CURRENT_SEL) << BIT_SHIFT_AFE_USB_CURRENT_SEL)
-#define BIT_GET_AFE_USB_CURRENT_SEL(x) (((x) >> BIT_SHIFT_AFE_USB_CURRENT_SEL) & BIT_MASK_AFE_USB_CURRENT_SEL)
+#endif
+#if (HALMAC_8192E_SUPPORT)
-#define BIT_SHIFT_AFE_USB_PATH_SEL 24
-#define BIT_MASK_AFE_USB_PATH_SEL 0x3
-#define BIT_AFE_USB_PATH_SEL(x) (((x) & BIT_MASK_AFE_USB_PATH_SEL) << BIT_SHIFT_AFE_USB_PATH_SEL)
-#define BIT_GET_AFE_USB_PATH_SEL(x) (((x) >> BIT_SHIFT_AFE_USB_PATH_SEL) & BIT_MASK_AFE_USB_PATH_SEL)
+/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
+#define BIT_CLK_REQ_INPUT BIT(15)
+#define BIT_USB_XTAL_CLK_SEL BIT(14)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
+#define BIT_SHIFT_DBG_SEL_BYTE 14
+#define BIT_MASK_DBG_SEL_BYTE 0x3
+#define BIT_DBG_SEL_BYTE(x) \
+ (((x) & BIT_MASK_DBG_SEL_BYTE) << BIT_SHIFT_DBG_SEL_BYTE)
+#define BITS_DBG_SEL_BYTE (BIT_MASK_DBG_SEL_BYTE << BIT_SHIFT_DBG_SEL_BYTE)
+#define BIT_CLEAR_DBG_SEL_BYTE(x) ((x) & (~BITS_DBG_SEL_BYTE))
+#define BIT_GET_DBG_SEL_BYTE(x) \
+ (((x) >> BIT_SHIFT_DBG_SEL_BYTE) & BIT_MASK_DBG_SEL_BYTE)
+#define BIT_SET_DBG_SEL_BYTE(x, v) \
+ (BIT_CLEAR_DBG_SEL_BYTE(x) | BIT_DBG_SEL_BYTE(v))
-/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define BIT_SHIFT_DBG_SEL_V1 16
-#define BIT_MASK_DBG_SEL_V1 0xff
-#define BIT_DBG_SEL_V1(x) (((x) & BIT_MASK_DBG_SEL_V1) << BIT_SHIFT_DBG_SEL_V1)
-#define BIT_GET_DBG_SEL_V1(x) (((x) >> BIT_SHIFT_DBG_SEL_V1) & BIT_MASK_DBG_SEL_V1)
+/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
+#define BIT_USB_REG_XTAL_SEL BIT(14)
+#define BIT_SYSON_BTIO1POW_PAD_E2 BIT(13)
#endif
-
#if (HALMAC_8192E_SUPPORT)
-
/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
-#define BIT_CLK_REQ_INPUT BIT(15)
-#define BIT_USB_XTAL_CLK_SEL BIT(14)
+#define BIT_SHIFT_SYSON_SPS0_STD_L1 12
+#define BIT_MASK_SYSON_SPS0_STD_L1 0x3
+#define BIT_SYSON_SPS0_STD_L1(x) \
+ (((x) & BIT_MASK_SYSON_SPS0_STD_L1) << BIT_SHIFT_SYSON_SPS0_STD_L1)
+#define BITS_SYSON_SPS0_STD_L1 \
+ (BIT_MASK_SYSON_SPS0_STD_L1 << BIT_SHIFT_SYSON_SPS0_STD_L1)
+#define BIT_CLEAR_SYSON_SPS0_STD_L1(x) ((x) & (~BITS_SYSON_SPS0_STD_L1))
+#define BIT_GET_SYSON_SPS0_STD_L1(x) \
+ (((x) >> BIT_SHIFT_SYSON_SPS0_STD_L1) & BIT_MASK_SYSON_SPS0_STD_L1)
+#define BIT_SET_SYSON_SPS0_STD_L1(x, v) \
+ (BIT_CLEAR_SYSON_SPS0_STD_L1(x) | BIT_SYSON_SPS0_STD_L1(v))
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
+#define BIT_SHIFT_STD_L1_V1 12
+#define BIT_MASK_STD_L1_V1 0x3
+#define BIT_STD_L1_V1(x) (((x) & BIT_MASK_STD_L1_V1) << BIT_SHIFT_STD_L1_V1)
+#define BITS_STD_L1_V1 (BIT_MASK_STD_L1_V1 << BIT_SHIFT_STD_L1_V1)
+#define BIT_CLEAR_STD_L1_V1(x) ((x) & (~BITS_STD_L1_V1))
+#define BIT_GET_STD_L1_V1(x) (((x) >> BIT_SHIFT_STD_L1_V1) & BIT_MASK_STD_L1_V1)
+#define BIT_SET_STD_L1_V1(x, v) (BIT_CLEAR_STD_L1_V1(x) | BIT_STD_L1_V1(v))
-#define BIT_SHIFT_DBG_SEL_BYTE 14
-#define BIT_MASK_DBG_SEL_BYTE 0x3
-#define BIT_DBG_SEL_BYTE(x) (((x) & BIT_MASK_DBG_SEL_BYTE) << BIT_SHIFT_DBG_SEL_BYTE)
-#define BIT_GET_DBG_SEL_BYTE(x) (((x) >> BIT_SHIFT_DBG_SEL_BYTE) & BIT_MASK_DBG_SEL_BYTE)
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#endif
+/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
+#define BIT_SYSON_BTIOPOW_PAD_E2 BIT(12)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+#endif
+#if (HALMAC_8881A_SUPPORT)
/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
-#define BIT_USB_REG_XTAL_SEL BIT(14)
-#define BIT_SYSON_BTIO1POW_PAD_E2 BIT(13)
+#define BIT_SHIFT_SYSON_LDOA12V_WT 12
+#define BIT_MASK_SYSON_LDOA12V_WT 0x3
+#define BIT_SYSON_LDOA12V_WT(x) \
+ (((x) & BIT_MASK_SYSON_LDOA12V_WT) << BIT_SHIFT_SYSON_LDOA12V_WT)
+#define BITS_SYSON_LDOA12V_WT \
+ (BIT_MASK_SYSON_LDOA12V_WT << BIT_SHIFT_SYSON_LDOA12V_WT)
+#define BIT_CLEAR_SYSON_LDOA12V_WT(x) ((x) & (~BITS_SYSON_LDOA12V_WT))
+#define BIT_GET_SYSON_LDOA12V_WT(x) \
+ (((x) >> BIT_SHIFT_SYSON_LDOA12V_WT) & BIT_MASK_SYSON_LDOA12V_WT)
+#define BIT_SET_SYSON_LDOA12V_WT(x, v) \
+ (BIT_CLEAR_SYSON_LDOA12V_WT(x) | BIT_SYSON_LDOA12V_WT(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT)
+/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
+#define BIT_SYSON_DBG_PAD_E2 BIT(11)
-/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define BIT_SHIFT_SYSON_SPS0_STD_L1 12
-#define BIT_MASK_SYSON_SPS0_STD_L1 0x3
-#define BIT_SYSON_SPS0_STD_L1(x) (((x) & BIT_MASK_SYSON_SPS0_STD_L1) << BIT_SHIFT_SYSON_SPS0_STD_L1)
-#define BIT_GET_SYSON_SPS0_STD_L1(x) (((x) >> BIT_SHIFT_SYSON_SPS0_STD_L1) & BIT_MASK_SYSON_SPS0_STD_L1)
+/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
+#define BIT_SYSON_SDIOPOW_PAD_E2 BIT(11)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
+#define BIT_SYSON_LED_PAD_E2 BIT(10)
-/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_STD_L1_V1 12
-#define BIT_MASK_STD_L1_V1 0x3
-#define BIT_STD_L1_V1(x) (((x) & BIT_MASK_STD_L1_V1) << BIT_SHIFT_STD_L1_V1)
-#define BIT_GET_STD_L1_V1(x) (((x) >> BIT_SHIFT_STD_L1_V1) & BIT_MASK_STD_L1_V1)
+/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
+#define BIT_SYSON_GPEE_PAD_E2 BIT(9)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
-#define BIT_SYSON_BTIOPOW_PAD_E2 BIT(12)
+#define BIT_SYSON_GPEE_PAD_E2_V33 BIT(9)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8881A_SUPPORT)
+/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
+#define BIT_SYSON_PCI_PAD_E2 BIT(8)
-/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
+#define BIT_SHIFT_MATCH_CNT 8
+#define BIT_MASK_MATCH_CNT 0xff
+#define BIT_MATCH_CNT(x) (((x) & BIT_MASK_MATCH_CNT) << BIT_SHIFT_MATCH_CNT)
+#define BITS_MATCH_CNT (BIT_MASK_MATCH_CNT << BIT_SHIFT_MATCH_CNT)
+#define BIT_CLEAR_MATCH_CNT(x) ((x) & (~BITS_MATCH_CNT))
+#define BIT_GET_MATCH_CNT(x) (((x) >> BIT_SHIFT_MATCH_CNT) & BIT_MASK_MATCH_CNT)
+#define BIT_SET_MATCH_CNT(x, v) (BIT_CLEAR_MATCH_CNT(x) | BIT_MATCH_CNT(v))
+
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_SYSON_LDOA12V_WT 12
-#define BIT_MASK_SYSON_LDOA12V_WT 0x3
-#define BIT_SYSON_LDOA12V_WT(x) (((x) & BIT_MASK_SYSON_LDOA12V_WT) << BIT_SHIFT_SYSON_LDOA12V_WT)
-#define BIT_GET_SYSON_LDOA12V_WT(x) (((x) >> BIT_SHIFT_SYSON_LDOA12V_WT) & BIT_MASK_SYSON_LDOA12V_WT)
+/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
+#define BIT_AUTO_SW_LDO_VOL_EN BIT(7)
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SDIO_HCPWM1_V2 (Offset 0x10250038) */
+
+#define BIT_TOGGLE BIT(7)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT)
/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
-#define BIT_SYSON_DBG_PAD_E2 BIT(11)
+#define BIT_AUTO_SW_LDO_VOL_EN_V1 BIT(6)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
-#define BIT_SYSON_SDIOPOW_PAD_E2 BIT(11)
+#define BIT_ADJ_LDO_VOLT BIT(6)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8881A_SUPPORT)
/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
-#define BIT_SYSON_LED_PAD_E2 BIT(10)
+#define BIT_SHIFT_SYSON_LDOHCI12_WT 6
+#define BIT_MASK_SYSON_LDOHCI12_WT 0x3
+#define BIT_SYSON_LDOHCI12_WT(x) \
+ (((x) & BIT_MASK_SYSON_LDOHCI12_WT) << BIT_SHIFT_SYSON_LDOHCI12_WT)
+#define BITS_SYSON_LDOHCI12_WT \
+ (BIT_MASK_SYSON_LDOHCI12_WT << BIT_SHIFT_SYSON_LDOHCI12_WT)
+#define BIT_CLEAR_SYSON_LDOHCI12_WT(x) ((x) & (~BITS_SYSON_LDOHCI12_WT))
+#define BIT_GET_SYSON_LDOHCI12_WT(x) \
+ (((x) >> BIT_SHIFT_SYSON_LDOHCI12_WT) & BIT_MASK_SYSON_LDOHCI12_WT)
+#define BIT_SET_SYSON_LDOHCI12_WT(x, v) \
+ (BIT_CLEAR_SYSON_LDOHCI12_WT(x) | BIT_SYSON_LDOHCI12_WT(v))
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
-#define BIT_SYSON_GPEE_PAD_E2 BIT(9)
+#define BIT_SHIFT_SYSON_SPS0WWV_WT 4
+#define BIT_MASK_SYSON_SPS0WWV_WT 0x3
+#define BIT_SYSON_SPS0WWV_WT(x) \
+ (((x) & BIT_MASK_SYSON_SPS0WWV_WT) << BIT_SHIFT_SYSON_SPS0WWV_WT)
+#define BITS_SYSON_SPS0WWV_WT \
+ (BIT_MASK_SYSON_SPS0WWV_WT << BIT_SHIFT_SYSON_SPS0WWV_WT)
+#define BIT_CLEAR_SYSON_SPS0WWV_WT(x) ((x) & (~BITS_SYSON_SPS0WWV_WT))
+#define BIT_GET_SYSON_SPS0WWV_WT(x) \
+ (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT) & BIT_MASK_SYSON_SPS0WWV_WT)
+#define BIT_SET_SYSON_SPS0WWV_WT(x, v) \
+ (BIT_CLEAR_SYSON_SPS0WWV_WT(x) | BIT_SYSON_SPS0WWV_WT(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
-#define BIT_SYSON_GPEE_PAD_E2_V33 BIT(9)
+#define BIT_SHIFT_SYSON_SPS0SPS_WT 4
+#define BIT_MASK_SYSON_SPS0SPS_WT 0x3
+#define BIT_SYSON_SPS0SPS_WT(x) \
+ (((x) & BIT_MASK_SYSON_SPS0SPS_WT) << BIT_SHIFT_SYSON_SPS0SPS_WT)
+#define BITS_SYSON_SPS0SPS_WT \
+ (BIT_MASK_SYSON_SPS0SPS_WT << BIT_SHIFT_SYSON_SPS0SPS_WT)
+#define BIT_CLEAR_SYSON_SPS0SPS_WT(x) ((x) & (~BITS_SYSON_SPS0SPS_WT))
+#define BIT_GET_SYSON_SPS0SPS_WT(x) \
+ (((x) >> BIT_SHIFT_SYSON_SPS0SPS_WT) & BIT_MASK_SYSON_SPS0SPS_WT)
+#define BIT_SET_SYSON_SPS0SPS_WT(x, v) \
+ (BIT_CLEAR_SYSON_SPS0SPS_WT(x) | BIT_SYSON_SPS0SPS_WT(v))
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
-#define BIT_SYSON_PCI_PAD_E2 BIT(8)
+#define BIT_SHIFT_SYSON_SPS0LDO_WT 2
+#define BIT_MASK_SYSON_SPS0LDO_WT 0x3
+#define BIT_SYSON_SPS0LDO_WT(x) \
+ (((x) & BIT_MASK_SYSON_SPS0LDO_WT) << BIT_SHIFT_SYSON_SPS0LDO_WT)
+#define BITS_SYSON_SPS0LDO_WT \
+ (BIT_MASK_SYSON_SPS0LDO_WT << BIT_SHIFT_SYSON_SPS0LDO_WT)
+#define BIT_CLEAR_SYSON_SPS0LDO_WT(x) ((x) & (~BITS_SYSON_SPS0LDO_WT))
+#define BIT_GET_SYSON_SPS0LDO_WT(x) \
+ (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT) & BIT_MASK_SYSON_SPS0LDO_WT)
+#define BIT_SET_SYSON_SPS0LDO_WT(x, v) \
+ (BIT_CLEAR_SYSON_SPS0LDO_WT(x) | BIT_SYSON_SPS0LDO_WT(v))
-#define BIT_SHIFT_MATCH_CNT 8
-#define BIT_MASK_MATCH_CNT 0xff
-#define BIT_MATCH_CNT(x) (((x) & BIT_MASK_MATCH_CNT) << BIT_SHIFT_MATCH_CNT)
-#define BIT_GET_MATCH_CNT(x) (((x) >> BIT_SHIFT_MATCH_CNT) & BIT_MASK_MATCH_CNT)
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#endif
+/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
+#define BIT_SHIFT_SYSON_SPS11VLDO_WT 2
+#define BIT_MASK_SYSON_SPS11VLDO_WT 0x3
+#define BIT_SYSON_SPS11VLDO_WT(x) \
+ (((x) & BIT_MASK_SYSON_SPS11VLDO_WT) << BIT_SHIFT_SYSON_SPS11VLDO_WT)
+#define BITS_SYSON_SPS11VLDO_WT \
+ (BIT_MASK_SYSON_SPS11VLDO_WT << BIT_SHIFT_SYSON_SPS11VLDO_WT)
+#define BIT_CLEAR_SYSON_SPS11VLDO_WT(x) ((x) & (~BITS_SYSON_SPS11VLDO_WT))
+#define BIT_GET_SYSON_SPS11VLDO_WT(x) \
+ (((x) >> BIT_SHIFT_SYSON_SPS11VLDO_WT) & BIT_MASK_SYSON_SPS11VLDO_WT)
+#define BIT_SET_SYSON_SPS11VLDO_WT(x, v) \
+ (BIT_CLEAR_SYSON_SPS11VLDO_WT(x) | BIT_SYSON_SPS11VLDO_WT(v))
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
-#define BIT_AUTO_SW_LDO_VOL_EN BIT(7)
+#define BIT_SHIFT_SYSON_RCLK_SCALE 0
+#define BIT_MASK_SYSON_RCLK_SCALE 0x3
+#define BIT_SYSON_RCLK_SCALE(x) \
+ (((x) & BIT_MASK_SYSON_RCLK_SCALE) << BIT_SHIFT_SYSON_RCLK_SCALE)
+#define BITS_SYSON_RCLK_SCALE \
+ (BIT_MASK_SYSON_RCLK_SCALE << BIT_SHIFT_SYSON_RCLK_SCALE)
+#define BIT_CLEAR_SYSON_RCLK_SCALE(x) ((x) & (~BITS_SYSON_RCLK_SCALE))
+#define BIT_GET_SYSON_RCLK_SCALE(x) \
+ (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE) & BIT_MASK_SYSON_RCLK_SCALE)
+#define BIT_SET_SYSON_RCLK_SCALE(x, v) \
+ (BIT_CLEAR_SYSON_RCLK_SCALE(x) | BIT_SYSON_RCLK_SCALE(v))
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT)
-
-
-/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
+/* 2 REG_SDIO_HCPWM1_V2 (Offset 0x10250038) */
-#define BIT_AUTO_SW_LDO_VOL_EN_V1 BIT(6)
+#define BIT_CUR_PS BIT(0)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
+/* 2 REG_CAL_TIMER (Offset 0x003C) */
-/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
+#define BIT_SHIFT_CAL_SCAL 0
+#define BIT_MASK_CAL_SCAL 0xff
+#define BIT_CAL_SCAL(x) (((x) & BIT_MASK_CAL_SCAL) << BIT_SHIFT_CAL_SCAL)
+#define BITS_CAL_SCAL (BIT_MASK_CAL_SCAL << BIT_SHIFT_CAL_SCAL)
+#define BIT_CLEAR_CAL_SCAL(x) ((x) & (~BITS_CAL_SCAL))
+#define BIT_GET_CAL_SCAL(x) (((x) >> BIT_SHIFT_CAL_SCAL) & BIT_MASK_CAL_SCAL)
+#define BIT_SET_CAL_SCAL(x, v) (BIT_CLEAR_CAL_SCAL(x) | BIT_CAL_SCAL(v))
-#define BIT_ADJ_LDO_VOLT BIT(6)
+/* 2 REG_ACLK_MON (Offset 0x003E) */
-#endif
+#define BIT_SHIFT_RCLK_MON 5
+#define BIT_MASK_RCLK_MON 0x7ff
+#define BIT_RCLK_MON(x) (((x) & BIT_MASK_RCLK_MON) << BIT_SHIFT_RCLK_MON)
+#define BITS_RCLK_MON (BIT_MASK_RCLK_MON << BIT_SHIFT_RCLK_MON)
+#define BIT_CLEAR_RCLK_MON(x) ((x) & (~BITS_RCLK_MON))
+#define BIT_GET_RCLK_MON(x) (((x) >> BIT_SHIFT_RCLK_MON) & BIT_MASK_RCLK_MON)
+#define BIT_SET_RCLK_MON(x, v) (BIT_CLEAR_RCLK_MON(x) | BIT_RCLK_MON(v))
+#define BIT_CAL_EN BIT(4)
-#if (HALMAC_8881A_SUPPORT)
+#define BIT_SHIFT_DPSTU 2
+#define BIT_MASK_DPSTU 0x3
+#define BIT_DPSTU(x) (((x) & BIT_MASK_DPSTU) << BIT_SHIFT_DPSTU)
+#define BITS_DPSTU (BIT_MASK_DPSTU << BIT_SHIFT_DPSTU)
+#define BIT_CLEAR_DPSTU(x) ((x) & (~BITS_DPSTU))
+#define BIT_GET_DPSTU(x) (((x) >> BIT_SHIFT_DPSTU) & BIT_MASK_DPSTU)
+#define BIT_SET_DPSTU(x, v) (BIT_CLEAR_DPSTU(x) | BIT_DPSTU(v))
+#define BIT_SUS_16X BIT(1)
-/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_SYSON_LDOHCI12_WT 6
-#define BIT_MASK_SYSON_LDOHCI12_WT 0x3
-#define BIT_SYSON_LDOHCI12_WT(x) (((x) & BIT_MASK_SYSON_LDOHCI12_WT) << BIT_SHIFT_SYSON_LDOHCI12_WT)
-#define BIT_GET_SYSON_LDOHCI12_WT(x) (((x) >> BIT_SHIFT_SYSON_LDOHCI12_WT) & BIT_MASK_SYSON_LDOHCI12_WT)
+/* 2 REG_ACLK_MON (Offset 0x003E) */
+#define BIT_RSM_EN BIT(0)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_GPIO_MUXCFG_2 (Offset 0x003F) */
+#define BIT_SOUT_GPIO8 BIT(7)
+#define BIT_SOUT_GPIO5 BIT(6)
+#define BIT_RFE_CTRL_5_GPIO14_V1 BIT(5)
+#define BIT_RFE_CTRL_10_GPIO13_V1 BIT(4)
+#define BIT_RFE_CTRL_11_GPIO4_V1 BIT(3)
+#define BIT_RFE_CTRL_5_GPIO14 BIT(2)
+#define BIT_RFE_CTRL_10_GPIO13 BIT(1)
+#define BIT_RFE_CTRL_11_GPIO4 BIT(0)
-/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define BIT_SHIFT_SYSON_SPS0WWV_WT 4
-#define BIT_MASK_SYSON_SPS0WWV_WT 0x3
-#define BIT_SYSON_SPS0WWV_WT(x) (((x) & BIT_MASK_SYSON_SPS0WWV_WT) << BIT_SHIFT_SYSON_SPS0WWV_WT)
-#define BIT_GET_SYSON_SPS0WWV_WT(x) (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT) & BIT_MASK_SYSON_SPS0WWV_WT)
+/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
+#define BIT_PAD_D_PAPE_2G_E BIT(31)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
+#define BIT_RFE_CTRL_3_GPIO12 BIT(31)
-/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define BIT_SHIFT_SYSON_SPS0SPS_WT 4
-#define BIT_MASK_SYSON_SPS0SPS_WT 0x3
-#define BIT_SYSON_SPS0SPS_WT(x) (((x) & BIT_MASK_SYSON_SPS0SPS_WT) << BIT_SHIFT_SYSON_SPS0SPS_WT)
-#define BIT_GET_SYSON_SPS0SPS_WT(x) (((x) >> BIT_SHIFT_SYSON_SPS0SPS_WT) & BIT_MASK_SYSON_SPS0SPS_WT)
+/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
+#define BIT_PAD_D_PAPE_5G_E BIT(30)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
+#define BIT_BT_RFE_CTRL_5_GPIO12 BIT(30)
-/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define BIT_SHIFT_SYSON_SPS0LDO_WT 2
-#define BIT_MASK_SYSON_SPS0LDO_WT 0x3
-#define BIT_SYSON_SPS0LDO_WT(x) (((x) & BIT_MASK_SYSON_SPS0LDO_WT) << BIT_SHIFT_SYSON_SPS0LDO_WT)
-#define BIT_GET_SYSON_SPS0LDO_WT(x) (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT) & BIT_MASK_SYSON_SPS0LDO_WT)
+/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
+#define BIT_PAD_D_TRSW_E BIT(29)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
+#define BIT_S0_TRSW_GPIO12 BIT(29)
-/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_SYSON_SPS11VLDO_WT 2
-#define BIT_MASK_SYSON_SPS11VLDO_WT 0x3
-#define BIT_SYSON_SPS11VLDO_WT(x) (((x) & BIT_MASK_SYSON_SPS11VLDO_WT) << BIT_SHIFT_SYSON_SPS11VLDO_WT)
-#define BIT_GET_SYSON_SPS11VLDO_WT(x) (((x) >> BIT_SHIFT_SYSON_SPS11VLDO_WT) & BIT_MASK_SYSON_SPS11VLDO_WT)
+/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
+#define BIT_SIC_LOWEST_PRIORITY BIT(28)
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
+#define BIT_PAD_D_TRSWB_E BIT(28)
-/* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */
+#endif
+#if (HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_SYSON_RCLK_SCALE 0
-#define BIT_MASK_SYSON_RCLK_SCALE 0x3
-#define BIT_SYSON_RCLK_SCALE(x) (((x) & BIT_MASK_SYSON_RCLK_SCALE) << BIT_SHIFT_SYSON_RCLK_SCALE)
-#define BIT_GET_SYSON_RCLK_SCALE(x) (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE) & BIT_MASK_SYSON_RCLK_SCALE)
+/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
+#define BIT_RFE_CTRL_9_GPIO13 BIT(28)
-/* 2 REG_CAL_TIMER (Offset 0x003C) */
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define BIT_SHIFT_CAL_SCAL 0
-#define BIT_MASK_CAL_SCAL 0xff
-#define BIT_CAL_SCAL(x) (((x) & BIT_MASK_CAL_SCAL) << BIT_SHIFT_CAL_SCAL)
-#define BIT_GET_CAL_SCAL(x) (((x) >> BIT_SHIFT_CAL_SCAL) & BIT_MASK_CAL_SCAL)
+/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
+#define BIT_PAD_D_PAPE_2G_O BIT(27)
-/* 2 REG_ACLK_MON (Offset 0x003E) */
+#endif
+#if (HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_RCLK_MON 5
-#define BIT_MASK_RCLK_MON 0x7ff
-#define BIT_RCLK_MON(x) (((x) & BIT_MASK_RCLK_MON) << BIT_SHIFT_RCLK_MON)
-#define BIT_GET_RCLK_MON(x) (((x) >> BIT_SHIFT_RCLK_MON) & BIT_MASK_RCLK_MON)
+/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
-#define BIT_CAL_EN BIT(4)
+#define BIT_RFE_CTRL_9_GPIO12 BIT(27)
-#define BIT_SHIFT_DPSTU 2
-#define BIT_MASK_DPSTU 0x3
-#define BIT_DPSTU(x) (((x) & BIT_MASK_DPSTU) << BIT_SHIFT_DPSTU)
-#define BIT_GET_DPSTU(x) (((x) >> BIT_SHIFT_DPSTU) & BIT_MASK_DPSTU)
+#endif
-#define BIT_SUS_16X BIT(1)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#endif
+/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
+#define BIT_PAD_D_PAPE_5G_O BIT(26)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8822C_SUPPORT)
-/* 2 REG_ACLK_MON (Offset 0x003E) */
+/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
-#define BIT_RSM_EN BIT(0)
+#define BIT_RFE_CTRL_8_GPIO4 BIT(26)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
-#define BIT_PAD_D_PAPE_2G_E BIT(31)
-#define BIT_PAD_D_PAPE_5G_E BIT(30)
-#define BIT_PAD_D_TRSW_E BIT(29)
+#define BIT_PAD_D_TRSW_O BIT(25)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
+
+#define BIT_BT_RFE_CTRL_1_GPIO13 BIT(25)
+
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
-#define BIT_SIC_LOWEST_PRIORITY BIT(28)
+#define BIT_SHIFT_PIN_USECASE 24
+#define BIT_MASK_PIN_USECASE 0xf
+#define BIT_PIN_USECASE(x) \
+ (((x) & BIT_MASK_PIN_USECASE) << BIT_SHIFT_PIN_USECASE)
+#define BITS_PIN_USECASE (BIT_MASK_PIN_USECASE << BIT_SHIFT_PIN_USECASE)
+#define BIT_CLEAR_PIN_USECASE(x) ((x) & (~BITS_PIN_USECASE))
+#define BIT_GET_PIN_USECASE(x) \
+ (((x) >> BIT_SHIFT_PIN_USECASE) & BIT_MASK_PIN_USECASE)
+#define BIT_SET_PIN_USECASE(x, v) \
+ (BIT_CLEAR_PIN_USECASE(x) | BIT_PIN_USECASE(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
-#define BIT_PAD_D_TRSWB_E BIT(28)
-#define BIT_PAD_D_PAPE_2G_O BIT(27)
-#define BIT_PAD_D_PAPE_5G_O BIT(26)
-#define BIT_PAD_D_TRSW_O BIT(25)
+#define BIT_PAD_D_TRSWB_O BIT(24)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
+#define BIT_EN_DATACPU_GPIO2 BIT(24)
-/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
+#endif
+#if (HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_PIN_USECASE 24
-#define BIT_MASK_PIN_USECASE 0xf
-#define BIT_PIN_USECASE(x) (((x) & BIT_MASK_PIN_USECASE) << BIT_SHIFT_PIN_USECASE)
-#define BIT_GET_PIN_USECASE(x) (((x) >> BIT_SHIFT_PIN_USECASE) & BIT_MASK_PIN_USECASE)
+/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
+#define BIT_BT_RFE_CTRL_1_GPIO12 BIT(24)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
-#define BIT_PAD_D_TRSWB_O BIT(24)
-#define BIT_EN_A_ANTSEL BIT(23)
-#define BIT_EN_A_ANTSELB BIT(22)
-#define BIT_EN_D_PAPE_2G BIT(21)
+#define BIT_EN_A_ANTSEL BIT(23)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
+#define BIT_EN_DATACPU_GPIO BIT(23)
-/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */
+#endif
-#define BIT_INDIRECT_REG_RDY BIT(20)
+#if (HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
+#define BIT_BT_RFE_CTRL_0_GPIO4 BIT(23)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
-#define BIT_EN_D_PAPE_5G BIT(20)
+#define BIT_EN_A_ANTSELB BIT(22)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
-#define BIT_FSPI_EN BIT(19)
+#define BIT_EN_DATACPU_UART BIT(22)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
+#define BIT_ANTSW_GPIO13 BIT(22)
-/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */
+#endif
-#define BIT_INDIRECT_REG_R BIT(19)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#endif
+/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
+#define BIT_EN_D_PAPE_2G BIT(21)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
-#define BIT_WL_RTS_EXT_32K_SEL BIT(18)
+#define BIT_DATACPU_FSPI_EN BIT(21)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
+#define BIT_ANTSW_GPIO12 BIT(21)
-/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */
+#endif
-#define BIT_INDIRECT_REG_W BIT(18)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */
+#define BIT_INDIRECT_REG_RDY BIT(20)
-#if (HALMAC_8192E_SUPPORT)
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
-#define BIT_CKOUT33_EN BIT(17)
+#define BIT_EN_D_PAPE_5G BIT(20)
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
-#define BIT_XTAL_OUT_EN BIT(17)
+#define BIT_EN_GPIO8_UART_OUT BIT(20)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8822C_SUPPORT)
/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
-#define BIT_WLGP_SPI_EN BIT(16)
+#define BIT_ANTSWB_GPIO4 BIT(20)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
+#define BIT_FSPI_EN BIT(19)
-/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_INDIRECT_REG_SIZE 16
-#define BIT_MASK_INDIRECT_REG_SIZE 0x3
-#define BIT_INDIRECT_REG_SIZE(x) (((x) & BIT_MASK_INDIRECT_REG_SIZE) << BIT_SHIFT_INDIRECT_REG_SIZE)
-#define BIT_GET_INDIRECT_REG_SIZE(x) (((x) >> BIT_SHIFT_INDIRECT_REG_SIZE) & BIT_MASK_INDIRECT_REG_SIZE)
+/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */
+#define BIT_INDIRECT_REG_R BIT(19)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
-#define BIT_SIC_LBK BIT(15)
-#define BIT_ENHTP BIT(14)
+#define BIT_WL_RTS_EXT_32K_SEL BIT(18)
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */
+
+#define BIT_INDIRECT_REG_W BIT(18)
+
+#endif
+#if (HALMAC_8192E_SUPPORT)
/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
-#define BIT_WLPHY_DBG_EN BIT(13)
+#define BIT_CKOUT33_EN BIT(17)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
-#define BIT_SIC_23 BIT(13)
+#define BIT_XTAL_OUT_EN BIT(17)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8822C_SUPPORT)
/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
-#define BIT_ENSIC BIT(12)
-#define BIT_SIC_SWRST BIT(11)
+#define BIT_WLBT_DPDT_SEL_EN BIT(17)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
-#define BIT_PO_WIFI_PTA_PINS BIT(10)
+#define BIT_WLGP_SPI_EN BIT(16)
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */
+#define BIT_SHIFT_INDIRECT_REG_SIZE 16
+#define BIT_MASK_INDIRECT_REG_SIZE 0x3
+#define BIT_INDIRECT_REG_SIZE(x) \
+ (((x) & BIT_MASK_INDIRECT_REG_SIZE) << BIT_SHIFT_INDIRECT_REG_SIZE)
+#define BITS_INDIRECT_REG_SIZE \
+ (BIT_MASK_INDIRECT_REG_SIZE << BIT_SHIFT_INDIRECT_REG_SIZE)
+#define BIT_CLEAR_INDIRECT_REG_SIZE(x) ((x) & (~BITS_INDIRECT_REG_SIZE))
+#define BIT_GET_INDIRECT_REG_SIZE(x) \
+ (((x) >> BIT_SHIFT_INDIRECT_REG_SIZE) & BIT_MASK_INDIRECT_REG_SIZE)
+#define BIT_SET_INDIRECT_REG_SIZE(x, v) \
+ (BIT_CLEAR_INDIRECT_REG_SIZE(x) | BIT_INDIRECT_REG_SIZE(v))
-/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
+#endif
-#define BIT_ENPMAC BIT(10)
+#if (HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
+#define BIT_WLBT_LNAON_SEL_EN BIT(16)
-#if (HALMAC_8192E_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
-#define BIT_ENBTCMD BIT(9)
+#define BIT_SIC_LBK BIT(15)
+#define BIT_ENHTP BIT(14)
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
-#define BIT_BTCOEX_MBOX_EN BIT(9)
+#define BIT_WLPHY_DBG_EN BIT(13)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
-#define BIT_BTCMD_OUT_EN BIT(9)
+#define BIT_SIC_23 BIT(13)
#endif
-
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8822C_SUPPORT)
/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
-#define BIT_PO_BT_PTA_PINS BIT(9)
+#define BIT_BT_AOD_GPIO3 BIT(13)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
-#define BIT_ENUART BIT(8)
-
-#define BIT_SHIFT_BTMODE 6
-#define BIT_MASK_BTMODE 0x3
-#define BIT_BTMODE(x) (((x) & BIT_MASK_BTMODE) << BIT_SHIFT_BTMODE)
-#define BIT_GET_BTMODE(x) (((x) >> BIT_SHIFT_BTMODE) & BIT_MASK_BTMODE)
-
-#define BIT_ENBT BIT(5)
-#define BIT_EROM_EN BIT(4)
+#define BIT_ENSIC BIT(12)
+#define BIT_SIC_SWRST BIT(11)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
-#define BIT_WLRFE_6_7_EN BIT(3)
+#define BIT_PO_WIFI_PTA_PINS BIT(10)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
-#define BIT_EN_D_TRSW BIT(3)
+#define BIT_ENPMAC BIT(10)
#endif
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
+
+#define BIT_ENBTCMD BIT(9)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
-#define BIT_WLRFE_4_5_EN BIT(2)
+#define BIT_BTCOEX_MBOX_EN BIT(9)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
-#define BIT_EN_D_TRSWB BIT(2)
+#define BIT_BTCMD_OUT_EN BIT(9)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
+
+#define BIT_PO_BT_PTA_PINS BIT(9)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
+#define BIT_ENUART BIT(8)
-#define BIT_SHIFT_GPIOSEL 0
-#define BIT_MASK_GPIOSEL 0x3
-#define BIT_GPIOSEL(x) (((x) & BIT_MASK_GPIOSEL) << BIT_SHIFT_GPIOSEL)
-#define BIT_GET_GPIOSEL(x) (((x) >> BIT_SHIFT_GPIOSEL) & BIT_MASK_GPIOSEL)
+#define BIT_SHIFT_BTMODE 6
+#define BIT_MASK_BTMODE 0x3
+#define BIT_BTMODE(x) (((x) & BIT_MASK_BTMODE) << BIT_SHIFT_BTMODE)
+#define BITS_BTMODE (BIT_MASK_BTMODE << BIT_SHIFT_BTMODE)
+#define BIT_CLEAR_BTMODE(x) ((x) & (~BITS_BTMODE))
+#define BIT_GET_BTMODE(x) (((x) >> BIT_SHIFT_BTMODE) & BIT_MASK_BTMODE)
+#define BIT_SET_BTMODE(x, v) (BIT_CLEAR_BTMODE(x) | BIT_BTMODE(v))
+#define BIT_ENBT BIT(5)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
+#define BIT_GEN1GEN2_SWITCH BIT(5)
-/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_INDIRECT_REG_ADDR 0
-#define BIT_MASK_INDIRECT_REG_ADDR 0xffff
-#define BIT_INDIRECT_REG_ADDR(x) (((x) & BIT_MASK_INDIRECT_REG_ADDR) << BIT_SHIFT_INDIRECT_REG_ADDR)
-#define BIT_GET_INDIRECT_REG_ADDR(x) (((x) >> BIT_SHIFT_INDIRECT_REG_ADDR) & BIT_MASK_INDIRECT_REG_ADDR)
+/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
+#define BIT_EROM_EN BIT(4)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-
-/* 2 REG_GPIO_PIN_CTRL (Offset 0x0044) */
+/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
+#define BIT_WLRFE_6_7_EN BIT(3)
-#define BIT_SHIFT_GPIO_MOD_7_TO_0 24
-#define BIT_MASK_GPIO_MOD_7_TO_0 0xff
-#define BIT_GPIO_MOD_7_TO_0(x) (((x) & BIT_MASK_GPIO_MOD_7_TO_0) << BIT_SHIFT_GPIO_MOD_7_TO_0)
-#define BIT_GET_GPIO_MOD_7_TO_0(x) (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0) & BIT_MASK_GPIO_MOD_7_TO_0)
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define BIT_SHIFT_GPIO_IO_SEL_7_TO_0 16
-#define BIT_MASK_GPIO_IO_SEL_7_TO_0 0xff
-#define BIT_GPIO_IO_SEL_7_TO_0(x) (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0) << BIT_SHIFT_GPIO_IO_SEL_7_TO_0)
-#define BIT_GET_GPIO_IO_SEL_7_TO_0(x) (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0) & BIT_MASK_GPIO_IO_SEL_7_TO_0)
+/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
+#define BIT_EN_D_TRSW BIT(3)
-#define BIT_SHIFT_GPIO_OUT_7_TO_0 8
-#define BIT_MASK_GPIO_OUT_7_TO_0 0xff
-#define BIT_GPIO_OUT_7_TO_0(x) (((x) & BIT_MASK_GPIO_OUT_7_TO_0) << BIT_SHIFT_GPIO_OUT_7_TO_0)
-#define BIT_GET_GPIO_OUT_7_TO_0(x) (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0) & BIT_MASK_GPIO_OUT_7_TO_0)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_GPIO_IN_7_TO_0 0
-#define BIT_MASK_GPIO_IN_7_TO_0 0xff
-#define BIT_GPIO_IN_7_TO_0(x) (((x) & BIT_MASK_GPIO_IN_7_TO_0) << BIT_SHIFT_GPIO_IN_7_TO_0)
-#define BIT_GET_GPIO_IN_7_TO_0(x) (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0) & BIT_MASK_GPIO_IN_7_TO_0)
+/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
+#define BIT_WLRFE_4_5_EN BIT(2)
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
+#define BIT_EN_D_TRSWB BIT(2)
-/* 2 REG_SDIO_INDIRECT_REG_DATA (Offset 0x10250044) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_INDIRECT_REG_DATA 0
-#define BIT_MASK_INDIRECT_REG_DATA 0xffffffffL
-#define BIT_INDIRECT_REG_DATA(x) (((x) & BIT_MASK_INDIRECT_REG_DATA) << BIT_SHIFT_INDIRECT_REG_DATA)
-#define BIT_GET_INDIRECT_REG_DATA(x) (((x) >> BIT_SHIFT_INDIRECT_REG_DATA) & BIT_MASK_INDIRECT_REG_DATA)
+/* 2 REG_GPIO_MUXCFG (Offset 0x0040) */
+#define BIT_SHIFT_GPIOSEL 0
+#define BIT_MASK_GPIOSEL 0x3
+#define BIT_GPIOSEL(x) (((x) & BIT_MASK_GPIOSEL) << BIT_SHIFT_GPIOSEL)
+#define BITS_GPIOSEL (BIT_MASK_GPIOSEL << BIT_SHIFT_GPIOSEL)
+#define BIT_CLEAR_GPIOSEL(x) ((x) & (~BITS_GPIOSEL))
+#define BIT_GET_GPIOSEL(x) (((x) >> BIT_SHIFT_GPIOSEL) & BIT_MASK_GPIOSEL)
+#define BIT_SET_GPIOSEL(x, v) (BIT_CLEAR_GPIOSEL(x) | BIT_GPIOSEL(v))
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */
+#define BIT_SHIFT_INDIRECT_REG_ADDR 0
+#define BIT_MASK_INDIRECT_REG_ADDR 0xffff
+#define BIT_INDIRECT_REG_ADDR(x) \
+ (((x) & BIT_MASK_INDIRECT_REG_ADDR) << BIT_SHIFT_INDIRECT_REG_ADDR)
+#define BITS_INDIRECT_REG_ADDR \
+ (BIT_MASK_INDIRECT_REG_ADDR << BIT_SHIFT_INDIRECT_REG_ADDR)
+#define BIT_CLEAR_INDIRECT_REG_ADDR(x) ((x) & (~BITS_INDIRECT_REG_ADDR))
+#define BIT_GET_INDIRECT_REG_ADDR(x) \
+ (((x) >> BIT_SHIFT_INDIRECT_REG_ADDR) & BIT_MASK_INDIRECT_REG_ADDR)
+#define BIT_SET_INDIRECT_REG_ADDR(x, v) \
+ (BIT_CLEAR_INDIRECT_REG_ADDR(x) | BIT_INDIRECT_REG_ADDR(v))
-/* 2 REG_GPIO_INTM (Offset 0x0048) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_MUXDBG_SEL 30
-#define BIT_MASK_MUXDBG_SEL 0x3
-#define BIT_MUXDBG_SEL(x) (((x) & BIT_MASK_MUXDBG_SEL) << BIT_SHIFT_MUXDBG_SEL)
-#define BIT_GET_MUXDBG_SEL(x) (((x) >> BIT_SHIFT_MUXDBG_SEL) & BIT_MASK_MUXDBG_SEL)
+/* 2 REG_GPIO_PIN_CTRL (Offset 0x0044) */
+#define BIT_SHIFT_GPIO_MOD_7_TO_0 24
+#define BIT_MASK_GPIO_MOD_7_TO_0 0xff
+#define BIT_GPIO_MOD_7_TO_0(x) \
+ (((x) & BIT_MASK_GPIO_MOD_7_TO_0) << BIT_SHIFT_GPIO_MOD_7_TO_0)
+#define BITS_GPIO_MOD_7_TO_0 \
+ (BIT_MASK_GPIO_MOD_7_TO_0 << BIT_SHIFT_GPIO_MOD_7_TO_0)
+#define BIT_CLEAR_GPIO_MOD_7_TO_0(x) ((x) & (~BITS_GPIO_MOD_7_TO_0))
+#define BIT_GET_GPIO_MOD_7_TO_0(x) \
+ (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0) & BIT_MASK_GPIO_MOD_7_TO_0)
+#define BIT_SET_GPIO_MOD_7_TO_0(x, v) \
+ (BIT_CLEAR_GPIO_MOD_7_TO_0(x) | BIT_GPIO_MOD_7_TO_0(v))
+
+#define BIT_SHIFT_GPIO_IO_SEL_7_TO_0 16
+#define BIT_MASK_GPIO_IO_SEL_7_TO_0 0xff
+#define BIT_GPIO_IO_SEL_7_TO_0(x) \
+ (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0) << BIT_SHIFT_GPIO_IO_SEL_7_TO_0)
+#define BITS_GPIO_IO_SEL_7_TO_0 \
+ (BIT_MASK_GPIO_IO_SEL_7_TO_0 << BIT_SHIFT_GPIO_IO_SEL_7_TO_0)
+#define BIT_CLEAR_GPIO_IO_SEL_7_TO_0(x) ((x) & (~BITS_GPIO_IO_SEL_7_TO_0))
+#define BIT_GET_GPIO_IO_SEL_7_TO_0(x) \
+ (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0) & BIT_MASK_GPIO_IO_SEL_7_TO_0)
+#define BIT_SET_GPIO_IO_SEL_7_TO_0(x, v) \
+ (BIT_CLEAR_GPIO_IO_SEL_7_TO_0(x) | BIT_GPIO_IO_SEL_7_TO_0(v))
+
+#define BIT_SHIFT_GPIO_OUT_7_TO_0 8
+#define BIT_MASK_GPIO_OUT_7_TO_0 0xff
+#define BIT_GPIO_OUT_7_TO_0(x) \
+ (((x) & BIT_MASK_GPIO_OUT_7_TO_0) << BIT_SHIFT_GPIO_OUT_7_TO_0)
+#define BITS_GPIO_OUT_7_TO_0 \
+ (BIT_MASK_GPIO_OUT_7_TO_0 << BIT_SHIFT_GPIO_OUT_7_TO_0)
+#define BIT_CLEAR_GPIO_OUT_7_TO_0(x) ((x) & (~BITS_GPIO_OUT_7_TO_0))
+#define BIT_GET_GPIO_OUT_7_TO_0(x) \
+ (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0) & BIT_MASK_GPIO_OUT_7_TO_0)
+#define BIT_SET_GPIO_OUT_7_TO_0(x, v) \
+ (BIT_CLEAR_GPIO_OUT_7_TO_0(x) | BIT_GPIO_OUT_7_TO_0(v))
+
+#define BIT_SHIFT_GPIO_IN_7_TO_0 0
+#define BIT_MASK_GPIO_IN_7_TO_0 0xff
+#define BIT_GPIO_IN_7_TO_0(x) \
+ (((x) & BIT_MASK_GPIO_IN_7_TO_0) << BIT_SHIFT_GPIO_IN_7_TO_0)
+#define BITS_GPIO_IN_7_TO_0 \
+ (BIT_MASK_GPIO_IN_7_TO_0 << BIT_SHIFT_GPIO_IN_7_TO_0)
+#define BIT_CLEAR_GPIO_IN_7_TO_0(x) ((x) & (~BITS_GPIO_IN_7_TO_0))
+#define BIT_GET_GPIO_IN_7_TO_0(x) \
+ (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0) & BIT_MASK_GPIO_IN_7_TO_0)
+#define BIT_SET_GPIO_IN_7_TO_0(x, v) \
+ (BIT_CLEAR_GPIO_IN_7_TO_0(x) | BIT_GPIO_IN_7_TO_0(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_SDIO_INDIRECT_REG_DATA (Offset 0x10250044) */
+#define BIT_SHIFT_INDIRECT_REG_DATA 0
+#define BIT_MASK_INDIRECT_REG_DATA 0xffffffffL
+#define BIT_INDIRECT_REG_DATA(x) \
+ (((x) & BIT_MASK_INDIRECT_REG_DATA) << BIT_SHIFT_INDIRECT_REG_DATA)
+#define BITS_INDIRECT_REG_DATA \
+ (BIT_MASK_INDIRECT_REG_DATA << BIT_SHIFT_INDIRECT_REG_DATA)
+#define BIT_CLEAR_INDIRECT_REG_DATA(x) ((x) & (~BITS_INDIRECT_REG_DATA))
+#define BIT_GET_INDIRECT_REG_DATA(x) \
+ (((x) >> BIT_SHIFT_INDIRECT_REG_DATA) & BIT_MASK_INDIRECT_REG_DATA)
+#define BIT_SET_INDIRECT_REG_DATA(x, v) \
+ (BIT_CLEAR_INDIRECT_REG_DATA(x) | BIT_INDIRECT_REG_DATA(v))
-#if (HALMAC_8192E_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_GPIO_INTM (Offset 0x0048) */
+#define BIT_SHIFT_MUXDBG_SEL 30
+#define BIT_MASK_MUXDBG_SEL 0x3
+#define BIT_MUXDBG_SEL(x) (((x) & BIT_MASK_MUXDBG_SEL) << BIT_SHIFT_MUXDBG_SEL)
+#define BITS_MUXDBG_SEL (BIT_MASK_MUXDBG_SEL << BIT_SHIFT_MUXDBG_SEL)
+#define BIT_CLEAR_MUXDBG_SEL(x) ((x) & (~BITS_MUXDBG_SEL))
+#define BIT_GET_MUXDBG_SEL(x) \
+ (((x) >> BIT_SHIFT_MUXDBG_SEL) & BIT_MASK_MUXDBG_SEL)
+#define BIT_SET_MUXDBG_SEL(x, v) (BIT_CLEAR_MUXDBG_SEL(x) | BIT_MUXDBG_SEL(v))
-#define BIT_SHIFT_MUXDBG_SEL2 28
-#define BIT_MASK_MUXDBG_SEL2 0x3
-#define BIT_MUXDBG_SEL2(x) (((x) & BIT_MASK_MUXDBG_SEL2) << BIT_SHIFT_MUXDBG_SEL2)
-#define BIT_GET_MUXDBG_SEL2(x) (((x) >> BIT_SHIFT_MUXDBG_SEL2) & BIT_MASK_MUXDBG_SEL2)
+#endif
+#if (HALMAC_8192E_SUPPORT)
-#endif
+/* 2 REG_GPIO_INTM (Offset 0x0048) */
+#define BIT_SHIFT_MUXDBG_SEL2 28
+#define BIT_MASK_MUXDBG_SEL2 0x3
+#define BIT_MUXDBG_SEL2(x) \
+ (((x) & BIT_MASK_MUXDBG_SEL2) << BIT_SHIFT_MUXDBG_SEL2)
+#define BITS_MUXDBG_SEL2 (BIT_MASK_MUXDBG_SEL2 << BIT_SHIFT_MUXDBG_SEL2)
+#define BIT_CLEAR_MUXDBG_SEL2(x) ((x) & (~BITS_MUXDBG_SEL2))
+#define BIT_GET_MUXDBG_SEL2(x) \
+ (((x) >> BIT_SHIFT_MUXDBG_SEL2) & BIT_MASK_MUXDBG_SEL2)
+#define BIT_SET_MUXDBG_SEL2(x, v) \
+ (BIT_CLEAR_MUXDBG_SEL2(x) | BIT_MUXDBG_SEL2(v))
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
/* 2 REG_GPIO_INTM (Offset 0x0048) */
-#define BIT_GPIO_EXT_EN BIT(20)
+#define BIT_GPIO_EXT_EN BIT(20)
#endif
-
#if (HALMAC_8192E_SUPPORT)
-
/* 2 REG_GPIO_INTM (Offset 0x0048) */
-#define BIT_EXTWOL1_SEL BIT(19)
-#define BIT_EXTWOL1_EN BIT(18)
+#define BIT_EXTWOL1_SEL BIT(19)
+#define BIT_EXTWOL1_EN BIT(18)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_GPIO_INTM (Offset 0x0048) */
-#define BIT_EXTWOL0_SEL BIT(17)
+#define BIT_EXTWOL0_SEL BIT(17)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_GPIO_INTM (Offset 0x0048) */
-#define BIT_EXTWOL_SEL BIT(17)
+#define BIT_EXTWOL_SEL BIT(17)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_GPIO_INTM (Offset 0x0048) */
-#define BIT_EXTWOL0_EN BIT(16)
+#define BIT_EXTWOL0_EN BIT(16)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_GPIO_INTM (Offset 0x0048) */
-#define BIT_EXTWOL_EN BIT(16)
+#define BIT_EXTWOL_EN BIT(16)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_GPIO_INTM (Offset 0x0048) */
-
-#define BIT_SHIFT_GPIO_EXT_WOL_V1 16
-#define BIT_MASK_GPIO_EXT_WOL_V1 0xf
-#define BIT_GPIO_EXT_WOL_V1(x) (((x) & BIT_MASK_GPIO_EXT_WOL_V1) << BIT_SHIFT_GPIO_EXT_WOL_V1)
-#define BIT_GET_GPIO_EXT_WOL_V1(x) (((x) >> BIT_SHIFT_GPIO_EXT_WOL_V1) & BIT_MASK_GPIO_EXT_WOL_V1)
-
+#define BIT_SHIFT_GPIO_EXT_WOL_V1 16
+#define BIT_MASK_GPIO_EXT_WOL_V1 0xf
+#define BIT_GPIO_EXT_WOL_V1(x) \
+ (((x) & BIT_MASK_GPIO_EXT_WOL_V1) << BIT_SHIFT_GPIO_EXT_WOL_V1)
+#define BITS_GPIO_EXT_WOL_V1 \
+ (BIT_MASK_GPIO_EXT_WOL_V1 << BIT_SHIFT_GPIO_EXT_WOL_V1)
+#define BIT_CLEAR_GPIO_EXT_WOL_V1(x) ((x) & (~BITS_GPIO_EXT_WOL_V1))
+#define BIT_GET_GPIO_EXT_WOL_V1(x) \
+ (((x) >> BIT_SHIFT_GPIO_EXT_WOL_V1) & BIT_MASK_GPIO_EXT_WOL_V1)
+#define BIT_SET_GPIO_EXT_WOL_V1(x, v) \
+ (BIT_CLEAR_GPIO_EXT_WOL_V1(x) | BIT_GPIO_EXT_WOL_V1(v))
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_GPIO_INTM (Offset 0x0048) */
-#define BIT_GPIOF_INT_MD BIT(15)
-#define BIT_GPIOE_INT_MD BIT(14)
-#define BIT_GPIOD_INT_MD BIT(13)
-#define BIT_GPIOC_INT_MD BIT(12)
-#define BIT_GPIOB_INT_MD BIT(11)
-#define BIT_GPIOA_INT_MD BIT(10)
-#define BIT_GPIO9_INT_MD BIT(9)
-#define BIT_GPIO8_INT_MD BIT(8)
-#define BIT_GPIO7_INT_MD BIT(7)
-#define BIT_GPIO6_INT_MD BIT(6)
-#define BIT_GPIO5_INT_MD BIT(5)
-#define BIT_GPIO4_INT_MD BIT(4)
-#define BIT_GPIO3_INT_MD BIT(3)
-#define BIT_GPIO2_INT_MD BIT(2)
-#define BIT_GPIO1_INT_MD BIT(1)
-#define BIT_GPIO0_INT_MD BIT(0)
+#define BIT_GPIOF_INT_MD BIT(15)
+#define BIT_GPIOE_INT_MD BIT(14)
+#define BIT_GPIOD_INT_MD BIT(13)
+#define BIT_GPIOC_INT_MD BIT(12)
+#define BIT_GPIOB_INT_MD BIT(11)
+#define BIT_GPIOA_INT_MD BIT(10)
+#define BIT_GPIO9_INT_MD BIT(9)
+#define BIT_GPIO8_INT_MD BIT(8)
+#define BIT_GPIO7_INT_MD BIT(7)
+#define BIT_GPIO6_INT_MD BIT(6)
+#define BIT_GPIO5_INT_MD BIT(5)
+#define BIT_GPIO4_INT_MD BIT(4)
+#define BIT_GPIO3_INT_MD BIT(3)
+#define BIT_GPIO2_INT_MD BIT(2)
+#define BIT_GPIO1_INT_MD BIT(1)
+#define BIT_GPIO0_INT_MD BIT(0)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_LED_CFG (Offset 0x004C) */
-#define BIT_PAD_ANTSEL_I BIT(31)
+#define BIT_PAD_ANTSEL_I BIT(31)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT)
+/* 2 REG_LED_CFG (Offset 0x004C) */
+
+#define BIT_MAILBOX_1WIRE_GPIO_CFG BIT(31)
+
+#endif
+#if (HALMAC_8192E_SUPPORT)
/* 2 REG_LED_CFG (Offset 0x004C) */
-#define BIT_ANT_SEL7_EN BIT(30)
+#define BIT_ANT_SEL7_EN BIT(30)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_LED_CFG (Offset 0x004C) */
-#define BIT_PAD_ANTSELB_I BIT(30)
+#define BIT_PAD_ANTSELB_I BIT(30)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT)
+/* 2 REG_LED_CFG (Offset 0x004C) */
+
+#define BIT_BT_RF_GPIO_CFG BIT(30)
+
+#endif
+#if (HALMAC_8192E_SUPPORT)
/* 2 REG_LED_CFG (Offset 0x004C) */
-#define BIT_ANT_SEL46_EN BIT(29)
+#define BIT_ANT_SEL46_EN BIT(29)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_LED_CFG (Offset 0x004C) */
-#define BIT_PAD_D_PAPE_2G_I BIT(29)
+#define BIT_PAD_D_PAPE_2G_I BIT(29)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT)
+/* 2 REG_LED_CFG (Offset 0x004C) */
+
+#define BIT_BT_SDIO_INT_GPIO_CFG BIT(29)
+
+#endif
+#if (HALMAC_8192E_SUPPORT)
/* 2 REG_LED_CFG (Offset 0x004C) */
-#define BIT_ANT_SEL3_EN BIT(28)
+#define BIT_ANT_SEL3_EN BIT(28)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_LED_CFG (Offset 0x004C) */
-#define BIT_PAD_D_PAPE_5G_I BIT(28)
+#define BIT_PAD_D_PAPE_5G_I BIT(28)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT)
+/* 2 REG_LED_CFG (Offset 0x004C) */
+
+#define BIT_MAILBOX_3WIRE_GPIO_CFG BIT(28)
+
+#endif
+#if (HALMAC_8192E_SUPPORT)
/* 2 REG_LED_CFG (Offset 0x004C) */
-#define BIT_TRSW_SEL_EN BIT(27)
+#define BIT_TRSW_SEL_EN BIT(27)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_LED_CFG (Offset 0x004C) */
-#define BIT_PAD_D_TRSW_I BIT(27)
+#define BIT_PAD_D_TRSW_I BIT(27)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_LED_CFG (Offset 0x004C) */
+
+#define BIT_GPIO3_WL_CTRL_EN BIT(27)
+
+#endif
+#if (HALMAC_8822C_SUPPORT)
/* 2 REG_LED_CFG (Offset 0x004C) */
-#define BIT_GPIO3_WL_CTRL_EN BIT(27)
+#define BIT_WLBT_PAPE_SEL_EN BIT(27)
#endif
-
#if (HALMAC_8192E_SUPPORT)
-
/* 2 REG_LED_CFG (Offset 0x004C) */
-#define BIT_PAPE1_SEL_EN BIT(26)
+#define BIT_PAPE1_SEL_EN BIT(26)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_LED_CFG (Offset 0x004C) */
-#define BIT_LNAON_SEL_EN BIT(26)
+#define BIT_LNAON_SEL_EN BIT(26)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_LED_CFG (Offset 0x004C) */
-#define BIT_PAD_D_TRSWB_I BIT(26)
+#define BIT_PAD_D_TRSWB_I BIT(26)
#endif
-
#if (HALMAC_8192E_SUPPORT)
-
/* 2 REG_LED_CFG (Offset 0x004C) */
-#define BIT_PAPE0_SEL_EN BIT(25)
+#define BIT_PAPE0_SEL_EN BIT(25)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_LED_CFG (Offset 0x004C) */
-#define BIT_PAPE_SEL_EN BIT(25)
+#define BIT_PAPE_SEL_EN BIT(25)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_LED_CFG (Offset 0x004C) */
-#define BIT_DWH_EN BIT(25)
+#define BIT_DWH_EN BIT(25)
#endif
-
#if (HALMAC_8192E_SUPPORT)
-
/* 2 REG_LED_CFG (Offset 0x004C) */
-#define BIT_ANTSEL2_EN BIT(24)
+#define BIT_ANTSEL2_EN BIT(24)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_LED_CFG (Offset 0x004C) */
-#define BIT_DPDT_WLBT_SEL BIT(24)
+#define BIT_DPDT_WLBT_SEL BIT(24)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_LED_CFG (Offset 0x004C) */
-#define BIT_DHW_EN BIT(24)
+#define BIT_DHW_EN BIT(24)
#endif
-
#if (HALMAC_8881A_SUPPORT)
-
/* 2 REG_LED_CFG (Offset 0x004C) */
-#define BIT_RFE_ANT_EXT_SEL BIT(24)
+#define BIT_RFE_ANT_EXT_SEL BIT(24)
#endif
-
#if (HALMAC_8192E_SUPPORT)
-
/* 2 REG_LED_CFG (Offset 0x004C) */
-#define BIT_ANTSEL_EN BIT(23)
+#define BIT_ANTSEL_EN BIT(23)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_LED_CFG (Offset 0x004C) */
-#define BIT_DPDT_SEL_EN BIT(23)
+#define BIT_DPDT_SEL_EN BIT(23)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_LED_CFG (Offset 0x004C) */
-#define BIT_GPIO13_14_WL_CTRL_EN BIT(22)
+#define BIT_GPIO13_14_WL_CTRL_EN BIT(22)
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_LED_CFG (Offset 0x004C) */
-#define BIT_LED2DIS_V1 BIT(22)
+#define BIT_LED2DIS_V1 BIT(22)
#endif
-
#if (HALMAC_8881A_SUPPORT)
-
/* 2 REG_LED_CFG (Offset 0x004C) */
-#define BIT_TRXIQ_DBG_EN BIT(22)
+#define BIT_TRXIQ_DBG_EN BIT(22)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_LED_CFG (Offset 0x004C) */
-#define BIT_LED2DIS BIT(21)
+#define BIT_LED2DIS BIT(21)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT)
/* 2 REG_LED_CFG (Offset 0x004C) */
-#define BIT_LED2EN BIT(21)
+#define BIT_LED2EN BIT(21)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_LED_CFG (Offset 0x004C) */
-#define BIT_LED2PL BIT(20)
-#define BIT_LED2SV BIT(19)
+#define BIT_LED2PL BIT(20)
+#define BIT_LED2SV BIT(19)
-#define BIT_SHIFT_LED2CM 16
-#define BIT_MASK_LED2CM 0x7
-#define BIT_LED2CM(x) (((x) & BIT_MASK_LED2CM) << BIT_SHIFT_LED2CM)
-#define BIT_GET_LED2CM(x) (((x) >> BIT_SHIFT_LED2CM) & BIT_MASK_LED2CM)
+#define BIT_SHIFT_LED2CM 16
+#define BIT_MASK_LED2CM 0x7
+#define BIT_LED2CM(x) (((x) & BIT_MASK_LED2CM) << BIT_SHIFT_LED2CM)
+#define BITS_LED2CM (BIT_MASK_LED2CM << BIT_SHIFT_LED2CM)
+#define BIT_CLEAR_LED2CM(x) ((x) & (~BITS_LED2CM))
+#define BIT_GET_LED2CM(x) (((x) >> BIT_SHIFT_LED2CM) & BIT_MASK_LED2CM)
+#define BIT_SET_LED2CM(x, v) (BIT_CLEAR_LED2CM(x) | BIT_LED2CM(v))
-#define BIT_LED1DIS BIT(15)
-#define BIT_LED1PL BIT(12)
-#define BIT_LED1SV BIT(11)
+#define BIT_LED1DIS BIT(15)
+#define BIT_LED1PL BIT(12)
+#define BIT_LED1SV BIT(11)
-#define BIT_SHIFT_LED1CM 8
-#define BIT_MASK_LED1CM 0x7
-#define BIT_LED1CM(x) (((x) & BIT_MASK_LED1CM) << BIT_SHIFT_LED1CM)
-#define BIT_GET_LED1CM(x) (((x) >> BIT_SHIFT_LED1CM) & BIT_MASK_LED1CM)
+#define BIT_SHIFT_LED1CM 8
+#define BIT_MASK_LED1CM 0x7
+#define BIT_LED1CM(x) (((x) & BIT_MASK_LED1CM) << BIT_SHIFT_LED1CM)
+#define BITS_LED1CM (BIT_MASK_LED1CM << BIT_SHIFT_LED1CM)
+#define BIT_CLEAR_LED1CM(x) ((x) & (~BITS_LED1CM))
+#define BIT_GET_LED1CM(x) (((x) >> BIT_SHIFT_LED1CM) & BIT_MASK_LED1CM)
+#define BIT_SET_LED1CM(x, v) (BIT_CLEAR_LED1CM(x) | BIT_LED1CM(v))
-#define BIT_LED0DIS BIT(7)
+#define BIT_LED0DIS BIT(7)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_LED_CFG (Offset 0x004C) */
-
-#define BIT_SHIFT_AFE_LDO_SWR_CHECK 5
-#define BIT_MASK_AFE_LDO_SWR_CHECK 0x3
-#define BIT_AFE_LDO_SWR_CHECK(x) (((x) & BIT_MASK_AFE_LDO_SWR_CHECK) << BIT_SHIFT_AFE_LDO_SWR_CHECK)
-#define BIT_GET_AFE_LDO_SWR_CHECK(x) (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK) & BIT_MASK_AFE_LDO_SWR_CHECK)
-
+#define BIT_SHIFT_AFE_LDO_SWR_CHECK 5
+#define BIT_MASK_AFE_LDO_SWR_CHECK 0x3
+#define BIT_AFE_LDO_SWR_CHECK(x) \
+ (((x) & BIT_MASK_AFE_LDO_SWR_CHECK) << BIT_SHIFT_AFE_LDO_SWR_CHECK)
+#define BITS_AFE_LDO_SWR_CHECK \
+ (BIT_MASK_AFE_LDO_SWR_CHECK << BIT_SHIFT_AFE_LDO_SWR_CHECK)
+#define BIT_CLEAR_AFE_LDO_SWR_CHECK(x) ((x) & (~BITS_AFE_LDO_SWR_CHECK))
+#define BIT_GET_AFE_LDO_SWR_CHECK(x) \
+ (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK) & BIT_MASK_AFE_LDO_SWR_CHECK)
+#define BIT_SET_AFE_LDO_SWR_CHECK(x, v) \
+ (BIT_CLEAR_AFE_LDO_SWR_CHECK(x) | BIT_AFE_LDO_SWR_CHECK(v))
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_LED_CFG (Offset 0x004C) */
-#define BIT_LED0PL BIT(4)
-#define BIT_LED0SV BIT(3)
-
-#define BIT_SHIFT_LED0CM 0
-#define BIT_MASK_LED0CM 0x7
-#define BIT_LED0CM(x) (((x) & BIT_MASK_LED0CM) << BIT_SHIFT_LED0CM)
-#define BIT_GET_LED0CM(x) (((x) >> BIT_SHIFT_LED0CM) & BIT_MASK_LED0CM)
+#define BIT_LED0PL BIT(4)
+#define BIT_LED0SV BIT(3)
+#define BIT_SHIFT_LED0CM 0
+#define BIT_MASK_LED0CM 0x7
+#define BIT_LED0CM(x) (((x) & BIT_MASK_LED0CM) << BIT_SHIFT_LED0CM)
+#define BITS_LED0CM (BIT_MASK_LED0CM << BIT_SHIFT_LED0CM)
+#define BIT_CLEAR_LED0CM(x) ((x) & (~BITS_LED0CM))
+#define BIT_GET_LED0CM(x) (((x) >> BIT_SHIFT_LED0CM) & BIT_MASK_LED0CM)
+#define BIT_SET_LED0CM(x, v) (BIT_CLEAR_LED0CM(x) | BIT_LED0CM(v))
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_PDNINT_EN BIT(31)
+#define BIT_FS_PDNINT_EN BIT(31)
#endif
-
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_NFC_INT_PAD_EN BIT(30)
+#define BIT_NFC_INT_PAD_EN BIT(30)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_SPS_OCP_INT_EN BIT(29)
+#define BIT_FS_SPS_OCP_INT_EN BIT(29)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_SW_SPS_OCP_INT_EN BIT(29)
+#define BIT_SW_SPS_OCP_INT_EN BIT(29)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_PWMERR_INT_EN BIT(28)
+#define BIT_FS_PWMERR_INT_EN BIT(28)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_PWM_HW_ERR_EN BIT(28)
+#define BIT_FS_PWM_HW_ERR_EN BIT(28)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_GPIOF_INT_EN BIT(27)
-#define BIT_FS_GPIOE_INT_EN BIT(26)
-#define BIT_FS_GPIOD_INT_EN BIT(25)
-#define BIT_FS_GPIOC_INT_EN BIT(24)
+#define BIT_FS_GPIOF_INT_EN BIT(27)
+#define BIT_FS_GPIOE_INT_EN BIT(26)
+#define BIT_FS_GPIOD_INT_EN BIT(25)
+#define BIT_FS_GPIOC_INT_EN BIT(24)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_ACT2RECOVERY_INT_EN BIT(24)
+#define BIT_ACT2RECOVERY_INT_EN BIT(24)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_GPIOB_INT_EN BIT(23)
+#define BIT_FS_GPIOB_INT_EN BIT(23)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_PCIE_GEN12_SWITH_EN BIT(23)
+#define BIT_PCIE_GEN12_SWITCH_EN BIT(23)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_GPIOA_INT_EN BIT(22)
+#define BIT_FS_GPIOA_INT_EN BIT(22)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_HCI_SUS_EN_V1 BIT(22)
+#define BIT_FS_HCI_SUS_EN_V1 BIT(22)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_GPIO9_INT_EN BIT(21)
+#define BIT_FS_GPIO9_INT_EN BIT(21)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_HCI_RES_EN_V1 BIT(21)
+#define BIT_FS_HCI_RES_EN_V1 BIT(21)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_GPIO8_INT_EN BIT(20)
+#define BIT_FS_GPIO8_INT_EN BIT(20)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_HCI_RESET_EN_V1 BIT(20)
+#define BIT_FS_HCI_RESET_EN_V1 BIT(20)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_GPIO7_INT_EN BIT(19)
+#define BIT_FS_GPIO7_INT_EN BIT(19)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_32K_LEAVE_SETTING_EN BIT(19)
+#define BIT_FS_32K_LEAVE_SETTING_EN BIT(19)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_GPIO6_INT_EN BIT(18)
+#define BIT_FS_GPIO6_INT_EN BIT(18)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_32K_ENTER_SETTING_EN BIT(18)
+#define BIT_FS_32K_ENTER_SETTING_EN BIT(18)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_GPIO5_INT_EN BIT(17)
+#define BIT_FS_GPIO5_INT_EN BIT(17)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_SIE_LPM_RSM_EN_V1 BIT(17)
+#define BIT_FS_SIE_LPM_RSM_EN_V1 BIT(17)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_GPIO4_INT_EN BIT(16)
+#define BIT_FS_GPIO4_INT_EN BIT(16)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_SIE_LPM_ACT_EN_V1 BIT(16)
+#define BIT_FS_SIE_LPM_ACT_EN_V1 BIT(16)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_GPIO3_INT_EN BIT(15)
+#define BIT_FS_GPIO3_INT_EN BIT(15)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_GPIOF_INT_EN_V1 BIT(15)
+#define BIT_FS_GPIOF_INT_EN_V1 BIT(15)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_GPIO2_INT_EN BIT(14)
+#define BIT_FS_GPIO2_INT_EN BIT(14)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_GPIOE_INT_EN_V1 BIT(14)
+#define BIT_FS_GPIOE_INT_EN_V1 BIT(14)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_GPIO1_INT_EN BIT(13)
+#define BIT_FS_GPIO1_INT_EN BIT(13)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_GPIOD_INT_EN_V1 BIT(13)
+#define BIT_FS_GPIOD_INT_EN_V1 BIT(13)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_GPIO0_INT_EN BIT(12)
+#define BIT_FS_GPIO0_INT_EN BIT(12)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_GPIOC_INT_EN_V1 BIT(12)
+#define BIT_FS_GPIOC_INT_EN_V1 BIT(12)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_HCI_SUS_EN BIT(11)
+#define BIT_FS_HCI_SUS_EN BIT(11)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_GPIOB_INT_EN_V1 BIT(11)
+#define BIT_FS_GPIOB_INT_EN_V1 BIT(11)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_HCI_RES_EN BIT(10)
+#define BIT_FS_HCI_RES_EN BIT(10)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_GPIOA_INT_EN_V1 BIT(10)
+#define BIT_FS_GPIOA_INT_EN_V1 BIT(10)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_HCI_RESET_EN BIT(9)
+#define BIT_FS_HCI_RESET_EN BIT(9)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_GPIO9_INT_EN_V1 BIT(9)
+#define BIT_FS_GPIO9_INT_EN_V1 BIT(9)
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_AXI_EXCEPT_FINT_EN BIT(8)
+#define BIT_AXI_EXCEPT_FINT_EN BIT(8)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_GPIO8_INT_EN_V1 BIT(8)
+#define BIT_FS_GPIO8_INT_EN_V1 BIT(8)
#endif
-
-#if (HALMAC_8821C_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_USB_SCSI_CMD_EN BIT(8)
+#define BIT_USB_SCSI_CMD_EN BIT(8)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_BTON_STS_UPDATE_MSK_EN BIT(7)
+#define BIT_FS_BTON_STS_UPDATE_MSK_EN BIT(7)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_GPIO7_INT_EN_V1 BIT(7)
+#define BIT_FS_GPIO7_INT_EN_V1 BIT(7)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_ACT2RECOVERY_INT_EN_V1 BIT(6)
+#define BIT_ACT2RECOVERY_INT_EN_V1 BIT(6)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_GPIO6_INT_EN_V1 BIT(6)
+#define BIT_FS_GPIO6_INT_EN_V1 BIT(6)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_TRPC_TO_INT_EN BIT(5)
+#define BIT_FS_TRPC_TO_INT_EN BIT(5)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
-/* 2 REG_FSIMR (Offset 0x0050) */
-
-#define BIT_FS_GPIO5_INT_EN_V1 BIT(5)
-
-#endif
-
-
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_GEN1GEN2_SWITCH BIT(5)
+#define BIT_FS_GPIO5_INT_EN_V1 BIT(5)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_RPC_O_T_INT_EN BIT(4)
+#define BIT_FS_RPC_O_T_INT_EN BIT(4)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_GPIO4_INT_EN_V1 BIT(4)
+#define BIT_FS_GPIO4_INT_EN_V1 BIT(4)
#endif
-
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_HCI_TXDMA_REQ_HIMR BIT(4)
+#define BIT_HCI_TXDMA_REQ_HIMR BIT(4)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_32K_LEAVE_SETTING_MAK BIT(3)
+#define BIT_FS_32K_LEAVE_SETTING_MAK BIT(3)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_GPIO3_INT_EN_V1 BIT(3)
+#define BIT_FS_GPIO3_INT_EN_V1 BIT(3)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_32K_ENTER_SETTING_MAK BIT(2)
+#define BIT_FS_32K_ENTER_SETTING_MAK BIT(2)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_GPIO2_INT_EN_V1 BIT(2)
+#define BIT_FS_GPIO2_INT_EN_V1 BIT(2)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_USB_LPMRSM_MSK BIT(1)
+#define BIT_FS_USB_LPMRSM_MSK BIT(1)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_GPIO1_INT_EN_V1 BIT(1)
+#define BIT_FS_GPIO1_INT_EN_V1 BIT(1)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_USB_LPMINT_MSK BIT(0)
+#define BIT_FS_USB_LPMINT_MSK BIT(0)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSIMR (Offset 0x0050) */
-#define BIT_FS_GPIO0_INT_EN_V1 BIT(0)
+#define BIT_FS_GPIO0_INT_EN_V1 BIT(0)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_PDNINT BIT(31)
+#define BIT_FS_PDNINT BIT(31)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_SPS_OCP_INT BIT(29)
+#define BIT_FS_SPS_OCP_INT BIT(29)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_SW_SPS_OCP_INT BIT(29)
+#define BIT_SW_SPS_OCP_INT BIT(29)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_PWMERR_INT BIT(28)
+#define BIT_FS_PWMERR_INT BIT(28)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_PWM_HW_ERR BIT(28)
+#define BIT_FS_PWM_HW_ERR BIT(28)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_GPIOF_INT BIT(27)
-#define BIT_FS_GPIOE_INT BIT(26)
-#define BIT_FS_GPIOD_INT BIT(25)
-#define BIT_FS_GPIOC_INT BIT(24)
+#define BIT_FS_GPIOF_INT BIT(27)
+#define BIT_FS_GPIOE_INT BIT(26)
+#define BIT_FS_GPIOD_INT BIT(25)
+#define BIT_FS_GPIOC_INT BIT(24)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_ACT2RECOVERY_INT BIT(24)
+#define BIT_ACT2RECOVERY_INT BIT(24)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_GPIOB_INT BIT(23)
+#define BIT_FS_GPIOB_INT BIT(23)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_PCIE_GEN12_SWITH BIT(23)
+#define BIT_PCIE_GEN12_SWITCH BIT(23)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_GPIOA_INT BIT(22)
+#define BIT_FS_GPIOA_INT BIT(22)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_HCI_SUS_V1 BIT(22)
+#define BIT_FS_HCI_SUS_V1 BIT(22)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_GPIO9_INT BIT(21)
+#define BIT_FS_GPIO9_INT BIT(21)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_HCI_RES_V1 BIT(21)
+#define BIT_FS_HCI_RES_V1 BIT(21)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_GPIO8_INT BIT(20)
+#define BIT_FS_GPIO8_INT BIT(20)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_HCI_RESET_V1 BIT(20)
+#define BIT_FS_HCI_RESET_V1 BIT(20)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_GPIO7_INT BIT(19)
+#define BIT_FS_GPIO7_INT BIT(19)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_32K_LEAVE_SETTING BIT(19)
+#define BIT_FS_32K_LEAVE_SETTING BIT(19)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_GPIO6_INT BIT(18)
+#define BIT_FS_GPIO6_INT BIT(18)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_32K_ENTER_SETTING BIT(18)
+#define BIT_FS_32K_ENTER_SETTING BIT(18)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_GPIO5_INT BIT(17)
+#define BIT_FS_GPIO5_INT BIT(17)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_SIE_LPM_RSM_V1 BIT(17)
+#define BIT_FS_SIE_LPM_RSM_V1 BIT(17)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_GPIO4_INT BIT(16)
+#define BIT_FS_GPIO4_INT BIT(16)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_SIE_LPM_ACT_V1 BIT(16)
+#define BIT_FS_SIE_LPM_ACT_V1 BIT(16)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_GPIO3_INT BIT(15)
+#define BIT_FS_GPIO3_INT BIT(15)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_GPIOF_INT_V1 BIT(15)
+#define BIT_FS_GPIOF_INT_V1 BIT(15)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_GPIO2_INT BIT(14)
+#define BIT_FS_GPIO2_INT BIT(14)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_GPIOE_INT_V1 BIT(14)
+#define BIT_FS_GPIOE_INT_V1 BIT(14)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_GPIO1_INT BIT(13)
+#define BIT_FS_GPIO1_INT BIT(13)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_GPIOD_INT_V1 BIT(13)
+#define BIT_FS_GPIOD_INT_V1 BIT(13)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_GPIO0_INT BIT(12)
+#define BIT_FS_GPIO0_INT BIT(12)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_GPIOC_INT_V1 BIT(12)
+#define BIT_FS_GPIOC_INT_V1 BIT(12)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_HCI_SUS_INT BIT(11)
+#define BIT_FS_HCI_SUS_INT BIT(11)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_GPIOB_INT_V1 BIT(11)
+#define BIT_FS_GPIOB_INT_V1 BIT(11)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_HCI_RES_INT BIT(10)
+#define BIT_FS_HCI_RES_INT BIT(10)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_GPIOA_INT_V1 BIT(10)
+#define BIT_FS_GPIOA_INT_V1 BIT(10)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-
-/* 2 REG_FSISR (Offset 0x0054) */
-
-#define BIT_FS_HCI_RESET_INT BIT(9)
-
-#endif
-
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_R_8051_SPD BIT(9)
+#define BIT_FS_HCI_RESET_INT BIT(9)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_GPIO9_INT_V1 BIT(9)
+#define BIT_FS_GPIO9_INT_V1 BIT(9)
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_AXI_EXCEPT_FINT BIT(8)
+#define BIT_AXI_EXCEPT_FINT BIT(8)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
-/* 2 REG_FSISR (Offset 0x0054) */
-
-#define BIT_FS_GPIO8_INT_V1 BIT(8)
-
-#endif
-
-
-#if (HALMAC_8821C_SUPPORT)
-
-
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_USB_SCSI_CMD_INT BIT(8)
+#define BIT_FS_GPIO8_INT_V1 BIT(8)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_RAM_DL_SEL BIT(7)
+#define BIT_USB_SCSI_CMD_INT BIT(8)
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_BTON_STS_UPDATE_INT BIT(7)
+#define BIT_FS_BTON_STS_UPDATE_INT BIT(7)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
-/* 2 REG_FSISR (Offset 0x0054) */
-
-#define BIT_FS_GPIO7_INT_V1 BIT(7)
-
-#endif
-
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT)
-
-
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_WINTINI_RDY BIT(6)
+#define BIT_FS_GPIO7_INT_V1 BIT(7)
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_ACT2RECOVERY_INT_V1 BIT(6)
+#define BIT_ACT2RECOVERY_INT_V1 BIT(6)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_GPIO6_INT_V1 BIT(6)
+#define BIT_FS_GPIO6_INT_V1 BIT(6)
#endif
-
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_ACT2RECOVERY BIT(6)
+#define BIT_ACT2RECOVERY BIT(6)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_TRPC_TO_INT_INT BIT(5)
+#define BIT_FS_TRPC_TO_INT_INT BIT(5)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_GPIO5_INT_V1 BIT(5)
+#define BIT_FS_GPIO5_INT_V1 BIT(5)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_RPC_O_T_INT_INT BIT(4)
+#define BIT_FS_RPC_O_T_INT_INT BIT(4)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_GPIO4_INT_V1 BIT(4)
+#define BIT_FS_GPIO4_INT_V1 BIT(4)
#endif
-
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_HCI_TXDMA_REQ_HISR BIT(4)
+#define BIT_HCI_TXDMA_REQ_HISR BIT(4)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_32K_LEAVE_SETTING_INT BIT(3)
+#define BIT_FS_32K_LEAVE_SETTING_INT BIT(3)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_GPIO3_INT_V1 BIT(3)
+#define BIT_FS_GPIO3_INT_V1 BIT(3)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_32K_ENTER_SETTING_INT BIT(2)
+#define BIT_FS_32K_ENTER_SETTING_INT BIT(2)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_GPIO2_INT_V1 BIT(2)
+#define BIT_FS_GPIO2_INT_V1 BIT(2)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_USB_LPMRSM_INT BIT(1)
+#define BIT_FS_USB_LPMRSM_INT BIT(1)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_GPIO1_INT_V1 BIT(1)
+#define BIT_FS_GPIO1_INT_V1 BIT(1)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_USB_LPMINT_INT BIT(0)
+#define BIT_FS_USB_LPMINT_INT BIT(0)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_FSISR (Offset 0x0054) */
-#define BIT_FS_GPIO0_INT_V1 BIT(0)
+#define BIT_FS_GPIO0_INT_V1 BIT(0)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_HSIMR (Offset 0x0058) */
-#define BIT_GPIOF_INT_EN BIT(31)
-#define BIT_GPIOE_INT_EN BIT(30)
-#define BIT_GPIOD_INT_EN BIT(29)
-#define BIT_GPIOC_INT_EN BIT(28)
-#define BIT_GPIOB_INT_EN BIT(27)
-#define BIT_GPIOA_INT_EN BIT(26)
-#define BIT_GPIO9_INT_EN BIT(25)
-#define BIT_GPIO8_INT_EN BIT(24)
-#define BIT_GPIO7_INT_EN BIT(23)
-#define BIT_GPIO6_INT_EN BIT(22)
-#define BIT_GPIO5_INT_EN BIT(21)
-#define BIT_GPIO4_INT_EN BIT(20)
-#define BIT_GPIO3_INT_EN BIT(19)
+#define BIT_GPIOF_INT_EN BIT(31)
+#define BIT_GPIOE_INT_EN BIT(30)
+#define BIT_GPIOD_INT_EN BIT(29)
+#define BIT_GPIOC_INT_EN BIT(28)
+#define BIT_GPIOB_INT_EN BIT(27)
+#define BIT_GPIOA_INT_EN BIT(26)
+#define BIT_GPIO9_INT_EN BIT(25)
+#define BIT_GPIO8_INT_EN BIT(24)
+#define BIT_GPIO7_INT_EN BIT(23)
+#define BIT_GPIO6_INT_EN BIT(22)
+#define BIT_GPIO5_INT_EN BIT(21)
+#define BIT_GPIO4_INT_EN BIT(20)
+#define BIT_GPIO3_INT_EN BIT(19)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_HSIMR (Offset 0x0058) */
-#define BIT_GPIO2_INT_EN BIT(18)
+#define BIT_GPIO2_INT_EN BIT(18)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_HSIMR (Offset 0x0058) */
-#define BIT_GPIO1_INT_EN BIT(17)
-#define BIT_GPIO0_INT_EN BIT(16)
+#define BIT_GPIO2_INT_EN_V1 BIT(18)
#endif
-
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_HSIMR (Offset 0x0058) */
-#define BIT_GPIO2_INT_EN_V1 BIT(16)
+#define BIT_GPIO1_INT_EN BIT(17)
+#define BIT_GPIO0_INT_EN BIT(16)
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_HSIMR (Offset 0x0058) */
-#define BIT_AXI_EXCEPT_HINT_EN BIT(9)
-#define BIT_PDNINT_EN_V2 BIT(8)
+#define BIT_AXI_EXCEPT_HINT_EN BIT(9)
+#define BIT_PDNINT_EN_V2 BIT(8)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_HSIMR (Offset 0x0058) */
-#define BIT_PDNINT_EN BIT(7)
+#define BIT_PDNINT_EN BIT(7)
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_HSIMR (Offset 0x0058) */
-#define BIT_PDNINT_EN_V1 BIT(7)
+#define BIT_PDNINT_EN_V1 BIT(7)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_HSIMR (Offset 0x0058) */
-#define BIT_PDN_INT_EN BIT(7)
+#define BIT_PDN_INT_EN BIT(7)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_HSIMR (Offset 0x0058) */
-#define BIT_RON_INT_EN BIT(6)
+#define BIT_RON_INT_EN BIT(6)
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_HSIMR (Offset 0x0058) */
-#define BIT_RON_INT_EN_V1 BIT(6)
+#define BIT_RON_INT_EN_V1 BIT(6)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_HSIMR (Offset 0x0058) */
-#define BIT_SPS_OCP_INT_EN BIT(5)
+#define BIT_SPS_OCP_INT_EN BIT(5)
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_HSIMR (Offset 0x0058) */
-#define BIT_SPS_OCP_INT_EN_V1 BIT(5)
+#define BIT_SPS_OCP_INT_EN_V1 BIT(5)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_HSIMR (Offset 0x0058) */
-#define BIT_GPIO15_0_INT_EN BIT(0)
+#define BIT_GPIO15_0_INT_EN BIT(0)
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_HSIMR (Offset 0x0058) */
-#define BIT_GPIO15_0_INT_EN_V1 BIT(0)
+#define BIT_GPIO15_0_INT_EN_V1 BIT(0)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_HSISR (Offset 0x005C) */
-#define BIT_GPIOF_INT BIT(31)
-#define BIT_GPIOE_INT BIT(30)
-#define BIT_GPIOD_INT BIT(29)
-#define BIT_GPIOC_INT BIT(28)
-#define BIT_GPIOB_INT BIT(27)
-#define BIT_GPIOA_INT BIT(26)
-#define BIT_GPIO9_INT BIT(25)
-#define BIT_GPIO8_INT BIT(24)
-#define BIT_GPIO7_INT BIT(23)
+#define BIT_GPIOF_INT BIT(31)
+#define BIT_GPIOE_INT BIT(30)
+#define BIT_GPIOD_INT BIT(29)
+#define BIT_GPIOC_INT BIT(28)
+#define BIT_GPIOB_INT BIT(27)
+#define BIT_GPIOA_INT BIT(26)
+#define BIT_GPIO9_INT BIT(25)
+#define BIT_GPIO8_INT BIT(24)
+#define BIT_GPIO7_INT BIT(23)
+#define BIT_GPIO6_INT BIT(22)
+#define BIT_GPIO5_INT BIT(21)
+#define BIT_GPIO4_INT BIT(20)
+#define BIT_GPIO3_INT BIT(19)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_HSISR (Offset 0x005C) */
-#define BIT_CPRST BIT(23)
+#define BIT_GPIO2_INT BIT(18)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_HSISR (Offset 0x005C) */
-#define BIT_GPIO6_INT BIT(22)
-#define BIT_GPIO5_INT BIT(21)
-#define BIT_GPIO4_INT BIT(20)
-#define BIT_GPIO3_INT BIT(19)
+#define BIT_GPIO2_INT_V1 BIT(18)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_HSISR (Offset 0x005C) */
-#define BIT_GPIO2_INT BIT(18)
+#define BIT_GPIO1_INT BIT(17)
+#define BIT_GPIO0_INT BIT(16)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_HSISR (Offset 0x005C) */
-#define BIT_GPIO1_INT BIT(17)
-#define BIT_GPIO0_INT BIT(16)
+#define BIT_AXI_EXCEPT_HINT BIT(8)
#endif
-
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_HSISR (Offset 0x005C) */
-#define BIT_GPIO2_INT_V1 BIT(16)
+#define BIT_PDNINT BIT(7)
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_HSISR (Offset 0x005C) */
-#define BIT_AXI_EXCEPT_HINT BIT(8)
+#define BIT_PDNINT_V1 BIT(7)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
/* 2 REG_HSISR (Offset 0x005C) */
-#define BIT_PDNINT BIT(7)
+#define BIT_PDN_INT BIT(7)
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_HSISR (Offset 0x005C) */
-#define BIT_PDNINT_V1 BIT(7)
+#define BIT_RON_INT BIT(6)
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_HSISR (Offset 0x005C) */
-#define BIT_PDN_INT BIT(7)
+#define BIT_RON_INT_V1 BIT(6)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_HSISR (Offset 0x005C) */
-#define BIT_RON_INT BIT(6)
+#define BIT_SPS_OCP_INT BIT(5)
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_HSISR (Offset 0x005C) */
-#define BIT_RON_INT_V1 BIT(6)
+#define BIT_SPS_OCP_INT_V1 BIT(5)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_HSISR (Offset 0x005C) */
-#define BIT_SPS_OCP_INT BIT(5)
+#define BIT_GPIO15_0_INT BIT(0)
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_HSISR (Offset 0x005C) */
-#define BIT_SPS_OCP_INT_V1 BIT(5)
+#define BIT_GPIO15_0_INT_V1 BIT(0)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_GPIO_EXT_CTRL (Offset 0x0060) */
+#define BIT_SHIFT_GPIO_MOD_15_TO_8 24
+#define BIT_MASK_GPIO_MOD_15_TO_8 0xff
+#define BIT_GPIO_MOD_15_TO_8(x) \
+ (((x) & BIT_MASK_GPIO_MOD_15_TO_8) << BIT_SHIFT_GPIO_MOD_15_TO_8)
+#define BITS_GPIO_MOD_15_TO_8 \
+ (BIT_MASK_GPIO_MOD_15_TO_8 << BIT_SHIFT_GPIO_MOD_15_TO_8)
+#define BIT_CLEAR_GPIO_MOD_15_TO_8(x) ((x) & (~BITS_GPIO_MOD_15_TO_8))
+#define BIT_GET_GPIO_MOD_15_TO_8(x) \
+ (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8) & BIT_MASK_GPIO_MOD_15_TO_8)
+#define BIT_SET_GPIO_MOD_15_TO_8(x, v) \
+ (BIT_CLEAR_GPIO_MOD_15_TO_8(x) | BIT_GPIO_MOD_15_TO_8(v))
+
+#define BIT_SHIFT_GPIO_IO_SEL_15_TO_8 16
+#define BIT_MASK_GPIO_IO_SEL_15_TO_8 0xff
+#define BIT_GPIO_IO_SEL_15_TO_8(x) \
+ (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8) << BIT_SHIFT_GPIO_IO_SEL_15_TO_8)
+#define BITS_GPIO_IO_SEL_15_TO_8 \
+ (BIT_MASK_GPIO_IO_SEL_15_TO_8 << BIT_SHIFT_GPIO_IO_SEL_15_TO_8)
+#define BIT_CLEAR_GPIO_IO_SEL_15_TO_8(x) ((x) & (~BITS_GPIO_IO_SEL_15_TO_8))
+#define BIT_GET_GPIO_IO_SEL_15_TO_8(x) \
+ (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8) & BIT_MASK_GPIO_IO_SEL_15_TO_8)
+#define BIT_SET_GPIO_IO_SEL_15_TO_8(x, v) \
+ (BIT_CLEAR_GPIO_IO_SEL_15_TO_8(x) | BIT_GPIO_IO_SEL_15_TO_8(v))
+
+#define BIT_SHIFT_GPIO_OUT_15_TO_8 8
+#define BIT_MASK_GPIO_OUT_15_TO_8 0xff
+#define BIT_GPIO_OUT_15_TO_8(x) \
+ (((x) & BIT_MASK_GPIO_OUT_15_TO_8) << BIT_SHIFT_GPIO_OUT_15_TO_8)
+#define BITS_GPIO_OUT_15_TO_8 \
+ (BIT_MASK_GPIO_OUT_15_TO_8 << BIT_SHIFT_GPIO_OUT_15_TO_8)
+#define BIT_CLEAR_GPIO_OUT_15_TO_8(x) ((x) & (~BITS_GPIO_OUT_15_TO_8))
+#define BIT_GET_GPIO_OUT_15_TO_8(x) \
+ (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8) & BIT_MASK_GPIO_OUT_15_TO_8)
+#define BIT_SET_GPIO_OUT_15_TO_8(x, v) \
+ (BIT_CLEAR_GPIO_OUT_15_TO_8(x) | BIT_GPIO_OUT_15_TO_8(v))
+
+#define BIT_SHIFT_GPIO_IN_15_TO_8 0
+#define BIT_MASK_GPIO_IN_15_TO_8 0xff
+#define BIT_GPIO_IN_15_TO_8(x) \
+ (((x) & BIT_MASK_GPIO_IN_15_TO_8) << BIT_SHIFT_GPIO_IN_15_TO_8)
+#define BITS_GPIO_IN_15_TO_8 \
+ (BIT_MASK_GPIO_IN_15_TO_8 << BIT_SHIFT_GPIO_IN_15_TO_8)
+#define BIT_CLEAR_GPIO_IN_15_TO_8(x) ((x) & (~BITS_GPIO_IN_15_TO_8))
+#define BIT_GET_GPIO_IN_15_TO_8(x) \
+ (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8) & BIT_MASK_GPIO_IN_15_TO_8)
+#define BIT_SET_GPIO_IN_15_TO_8(x, v) \
+ (BIT_CLEAR_GPIO_IN_15_TO_8(x) | BIT_GPIO_IN_15_TO_8(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-/* 2 REG_HSISR (Offset 0x005C) */
+/* 2 REG_SDIO_H2C (Offset 0x10250060) */
-#define BIT_GPIO15_0_INT BIT(0)
-#define BIT_MCUFWDL_EN BIT(0)
+#define BIT_SHIFT_SDIO_H2C_MSG 0
+#define BIT_MASK_SDIO_H2C_MSG 0xffffffffL
+#define BIT_SDIO_H2C_MSG(x) \
+ (((x) & BIT_MASK_SDIO_H2C_MSG) << BIT_SHIFT_SDIO_H2C_MSG)
+#define BITS_SDIO_H2C_MSG (BIT_MASK_SDIO_H2C_MSG << BIT_SHIFT_SDIO_H2C_MSG)
+#define BIT_CLEAR_SDIO_H2C_MSG(x) ((x) & (~BITS_SDIO_H2C_MSG))
+#define BIT_GET_SDIO_H2C_MSG(x) \
+ (((x) >> BIT_SHIFT_SDIO_H2C_MSG) & BIT_MASK_SDIO_H2C_MSG)
+#define BIT_SET_SDIO_H2C_MSG(x, v) \
+ (BIT_CLEAR_SDIO_H2C_MSG(x) | BIT_SDIO_H2C_MSG(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
+#define BIT_DATA_CPU_JTAG BIT(30)
-/* 2 REG_HSISR (Offset 0x005C) */
+#endif
-#define BIT_GPIO15_0_INT_V1 BIT(0)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
+#define BIT_PAPE_WLBT_SEL BIT(29)
+#define BIT_LNAON_WLBT_SEL BIT(28)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-/* 2 REG_GPIO_EXT_CTRL (Offset 0x0060) */
+/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
+#define BIT_BDEN BIT(28)
-#define BIT_SHIFT_GPIO_MOD_15_TO_8 24
-#define BIT_MASK_GPIO_MOD_15_TO_8 0xff
-#define BIT_GPIO_MOD_15_TO_8(x) (((x) & BIT_MASK_GPIO_MOD_15_TO_8) << BIT_SHIFT_GPIO_MOD_15_TO_8)
-#define BIT_GET_GPIO_MOD_15_TO_8(x) (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8) & BIT_MASK_GPIO_MOD_15_TO_8)
+#endif
+#if (HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_GPIO_IO_SEL_15_TO_8 16
-#define BIT_MASK_GPIO_IO_SEL_15_TO_8 0xff
-#define BIT_GPIO_IO_SEL_15_TO_8(x) (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8) << BIT_SHIFT_GPIO_IO_SEL_15_TO_8)
-#define BIT_GET_GPIO_IO_SEL_15_TO_8(x) (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8) & BIT_MASK_GPIO_IO_SEL_15_TO_8)
+/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
+#define BIT_BT_BQB_GPIO_SEL BIT(27)
-#define BIT_SHIFT_GPIO_OUT_15_TO_8 8
-#define BIT_MASK_GPIO_OUT_15_TO_8 0xff
-#define BIT_GPIO_OUT_15_TO_8(x) (((x) & BIT_MASK_GPIO_OUT_15_TO_8) << BIT_SHIFT_GPIO_OUT_15_TO_8)
-#define BIT_GET_GPIO_OUT_15_TO_8(x) (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8) & BIT_MASK_GPIO_OUT_15_TO_8)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_GPIO_IN_15_TO_8 0
-#define BIT_MASK_GPIO_IN_15_TO_8 0xff
-#define BIT_GPIO_IN_15_TO_8(x) (((x) & BIT_MASK_GPIO_IN_15_TO_8) << BIT_SHIFT_GPIO_IN_15_TO_8)
-#define BIT_GET_GPIO_IN_15_TO_8(x) (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8) & BIT_MASK_GPIO_IN_15_TO_8)
+/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
+#define BIT_BTGP_GPG3_FEN BIT(26)
+#define BIT_BTGP_GPG2_FEN BIT(25)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
+#define BIT_BTGP_JTAG_EN BIT(24)
-/* 2 REG_SDIO_H2C (Offset 0x10250060) */
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define BIT_SHIFT_SDIO_H2C_MSG 0
-#define BIT_MASK_SDIO_H2C_MSG 0xffffffffL
-#define BIT_SDIO_H2C_MSG(x) (((x) & BIT_MASK_SDIO_H2C_MSG) << BIT_SHIFT_SDIO_H2C_MSG)
-#define BIT_GET_SDIO_H2C_MSG(x) (((x) >> BIT_SHIFT_SDIO_H2C_MSG) & BIT_MASK_SDIO_H2C_MSG)
+/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
+#define BIT_BB2PP_ISO BIT(24)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_PAPE_WLBT_SEL BIT(29)
-#define BIT_LNAON_WLBT_SEL BIT(28)
+#define BIT_XTAL_CLK_EXTARNAL_EN BIT(23)
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_BDEN BIT(28)
+#define BIT_BTBRI_UART_EN BIT(22)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_BTGP_GPG3_FEN BIT(26)
-#define BIT_BTGP_GPG2_FEN BIT(25)
+#define BIT_BTGP_UART0_EN BIT(22)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_BTGP_JTAG_EN BIT(24)
+#define BIT_BTGP_UART1_EN BIT(21)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_BB2PP_ISO BIT(24)
+#define BIT_BTCOEX_PU BIT(21)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_XTAL_CLK_EXTARNAL_EN BIT(23)
+#define BIT_BTGP_SPI_EN BIT(20)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_BTBRI_UART_EN BIT(22)
+#define BIT_EEPROM_SEL_PD BIT(20)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_BTGP_UART0_EN BIT(22)
+#define BIT_BTGP_GPIO_E2 BIT(19)
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
+
+#define BIT_TST_MOD_PD BIT(19)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_BTGP_UART1_EN BIT(21)
+#define BIT_BTGP_GPIO_EN BIT(18)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_BTCOEX_PU BIT(21)
+#define BIT_BOOT_FLUSH_PD BIT(18)
+#define BIT_USB_XTAL_SEL1_PD BIT(17)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_BTGP_SPI_EN BIT(20)
+#define BIT_SHIFT_BTGP_GPIO_SL 16
+#define BIT_MASK_BTGP_GPIO_SL 0x3
+#define BIT_BTGP_GPIO_SL(x) \
+ (((x) & BIT_MASK_BTGP_GPIO_SL) << BIT_SHIFT_BTGP_GPIO_SL)
+#define BITS_BTGP_GPIO_SL (BIT_MASK_BTGP_GPIO_SL << BIT_SHIFT_BTGP_GPIO_SL)
+#define BIT_CLEAR_BTGP_GPIO_SL(x) ((x) & (~BITS_BTGP_GPIO_SL))
+#define BIT_GET_BTGP_GPIO_SL(x) \
+ (((x) >> BIT_SHIFT_BTGP_GPIO_SL) & BIT_MASK_BTGP_GPIO_SL)
+#define BIT_SET_BTGP_GPIO_SL(x, v) \
+ (BIT_CLEAR_BTGP_GPIO_SL(x) | BIT_BTGP_GPIO_SL(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_EEPROM_SEL_PD BIT(20)
+#define BIT_USB_XTAL_SEL0_PD BIT(16)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT)
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_BTGP_GPIO_E2 BIT(19)
+#define BIT_HST_WKE_DEV_SL BIT(15)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_TST_MOD_PD BIT(19)
+#define BIT_BTSUSB_PL BIT(15)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_BTGP_GPIO_EN BIT(18)
+#define BIT_WL_JTAG BIT(15)
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_BOOT_FLUSH_PD BIT(18)
-#define BIT_USB_XTAL_SEL1_PD BIT(17)
+#define BIT_PAD_SDIO_SR BIT(14)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-
-#define BIT_SHIFT_BTGP_GPIO_SL 16
-#define BIT_MASK_BTGP_GPIO_SL 0x3
-#define BIT_BTGP_GPIO_SL(x) (((x) & BIT_MASK_BTGP_GPIO_SL) << BIT_SHIFT_BTGP_GPIO_SL)
-#define BIT_GET_BTGP_GPIO_SL(x) (((x) >> BIT_SHIFT_BTGP_GPIO_SL) & BIT_MASK_BTGP_GPIO_SL)
-
+#define BIT_GPIO14_OUTPUT_PL BIT(13)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_USB_XTAL_SEL0_PD BIT(16)
+#define BIT_SW_DEVWHOST_POLARITY BIT(13)
#endif
-
-#if (HALMAC_8192E_SUPPORT)
-
-
-/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-
-#define BIT_HST_WKE_DEV_SL BIT(15)
-
-#endif
-
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
-
-/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-
-#define BIT_BTSUSB_PL BIT(15)
-
-#endif
-
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-
-/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-
-#define BIT_PAD_SDIO_SR BIT(14)
-
-#endif
-
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-
-#define BIT_GPIO14_OUTPUT_PL BIT(13)
-
-#endif
-
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
-
-/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-
-#define BIT_SW_DEVWHOST_POLARITY BIT(13)
-
-#endif
-
-
-#if (HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8881A_SUPPORT)
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_GPIO15_OUTPUT_PL BIT(13)
+#define BIT_GPIO15_OUTPUT_PL BIT(13)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_HOST_WAKE_PAD_PULL_EN BIT(12)
+#define BIT_HOST_WAKE_PAD_PULL_EN BIT(12)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_HOST_WAKE_DEV_PLL_EN BIT(12)
+#define BIT_HOST_WAKE_DEV_PLL_EN BIT(12)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_HOST_WAKE_PAD_SL BIT(11)
+#define BIT_HOST_WAKE_PAD_SL BIT(11)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_HOST_WAKE_DEV_POLARITY BIT(11)
+#define BIT_HOST_WAKE_DEV_POLARITY BIT(11)
#endif
-
#if (HALMAC_8192E_SUPPORT)
-
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_PAD_TRSW_SR BIT(10)
+#define BIT_PAD_TRSW_SR BIT(10)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_PAD_LNAON_SR BIT(10)
+#define BIT_PAD_LNAON_SR BIT(10)
#endif
-
#if (HALMAC_8192E_SUPPORT)
-
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_PAD_TRSW_E2 BIT(9)
+#define BIT_PAD_TRSW_E2 BIT(9)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_PAD_LNAON_E2 BIT(9)
+#define BIT_PAD_LNAON_E2 BIT(9)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_A_ANTSEL_SR BIT(9)
+#define BIT_A_ANTSEL_SR BIT(9)
#endif
-
#if (HALMAC_8192E_SUPPORT)
-
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_SW_TRSW_P_SEL_DATA BIT(8)
+#define BIT_SW_TRSW_P_SEL_DATA BIT(8)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_SW_LNAON_G_SEL_DATA BIT(8)
+#define BIT_SW_LNAON_G_SEL_DATA BIT(8)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_A_ANTSEL_E2 BIT(8)
+#define BIT_A_ANTSEL_E2 BIT(8)
#endif
-
#if (HALMAC_8192E_SUPPORT)
-
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_SW_TRSW_N_SEL_DATA BIT(7)
+#define BIT_SW_TRSW_N_SEL_DATA BIT(7)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_SW_LNAON_A_SEL_DATA BIT(7)
+#define BIT_SW_LNAON_A_SEL_DATA BIT(7)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_D_PAPE_2G_SR BIT(7)
+#define BIT_D_PAPE_2G_SR BIT(7)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_PAD_PAPE_SR BIT(6)
+#define BIT_PAD_PAPE_SR BIT(6)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_D_PAPE_5G_SR BIT(6)
+#define BIT_D_PAPE_5G_SR BIT(6)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_PAD_PAPE_E2 BIT(5)
+#define BIT_PAD_PAPE_E2 BIT(5)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_D_TRSW_SR BIT(5)
+#define BIT_D_TRSW_SR BIT(5)
#endif
-
#if (HALMAC_8192E_SUPPORT)
-
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_SW_PAPE_1_SEL_DATA BIT(4)
+#define BIT_SW_PAPE_1_SEL_DATA BIT(4)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_SW_PAPE_G_SEL_DATA BIT(4)
+#define BIT_SW_PAPE_G_SEL_DATA BIT(4)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_D_TRSWB_SR BIT(4)
+#define BIT_D_TRSWB_SR BIT(4)
#endif
-
#if (HALMAC_8192E_SUPPORT)
-
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_SW_PAPE_0_SEL_DATA BIT(3)
+#define BIT_SW_PAPE_0_SEL_DATA BIT(3)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_SW_PAPE_A_SEL_DATA BIT(3)
+#define BIT_SW_PAPE_A_SEL_DATA BIT(3)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_D_PAPE_2G_E2 BIT(3)
+#define BIT_D_PAPE_2G_E2 BIT(3)
#endif
-
#if (HALMAC_8192E_SUPPORT)
-
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_SW_ANTSEL_2_SEL_DATA BIT(2)
+#define BIT_SW_ANTSEL_2_SEL_DATA BIT(2)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_PAD_DPDT_SR BIT(2)
+#define BIT_PAD_DPDT_SR BIT(2)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_D_PAPE_5G_E2 BIT(2)
+#define BIT_D_PAPE_5G_E2 BIT(2)
#endif
-
#if (HALMAC_8192E_SUPPORT)
-
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_SW_ANTSEL_N_SEL_DATA BIT(1)
+#define BIT_SW_ANTSEL_N_SEL_DATA BIT(1)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_PAD_DPDT_PAD_E2 BIT(1)
+#define BIT_PAD_DPDT_PAD_E2 BIT(1)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_D_TRSW_E2 BIT(1)
+#define BIT_D_TRSW_E2 BIT(1)
#endif
-
#if (HALMAC_8881A_SUPPORT)
-
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_PAD_DPDT_E2 BIT(1)
+#define BIT_PAD_DPDT_E2 BIT(1)
#endif
-
#if (HALMAC_8192E_SUPPORT)
-
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_SW_ANTSEL_P_SEL_DATA BIT(0)
+#define BIT_SW_ANTSEL_P_SEL_DATA BIT(0)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_SW_DPDT_SEL_DATA BIT(0)
+#define BIT_SW_DPDT_SEL_DATA BIT(0)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_PAD_CTRL1 (Offset 0x0064) */
-#define BIT_D_TRSWB_E2 BIT(0)
+#define BIT_D_TRSWB_E2 BIT(0)
#endif
-
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_C2H (Offset 0x10250064) */
-
-#define BIT_SHIFT_SDIO_C2H_MSG 0
-#define BIT_MASK_SDIO_C2H_MSG 0xffffffffL
-#define BIT_SDIO_C2H_MSG(x) (((x) & BIT_MASK_SDIO_C2H_MSG) << BIT_SHIFT_SDIO_C2H_MSG)
-#define BIT_GET_SDIO_C2H_MSG(x) (((x) >> BIT_SHIFT_SDIO_C2H_MSG) & BIT_MASK_SDIO_C2H_MSG)
-
+#define BIT_SHIFT_SDIO_C2H_MSG 0
+#define BIT_MASK_SDIO_C2H_MSG 0xffffffffL
+#define BIT_SDIO_C2H_MSG(x) \
+ (((x) & BIT_MASK_SDIO_C2H_MSG) << BIT_SHIFT_SDIO_C2H_MSG)
+#define BITS_SDIO_C2H_MSG (BIT_MASK_SDIO_C2H_MSG << BIT_SHIFT_SDIO_C2H_MSG)
+#define BIT_CLEAR_SDIO_C2H_MSG(x) ((x) & (~BITS_SDIO_C2H_MSG))
+#define BIT_GET_SDIO_C2H_MSG(x) \
+ (((x) >> BIT_SHIFT_SDIO_C2H_MSG) & BIT_MASK_SDIO_C2H_MSG)
+#define BIT_SET_SDIO_C2H_MSG(x, v) \
+ (BIT_CLEAR_SDIO_C2H_MSG(x) | BIT_SDIO_C2H_MSG(v))
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_ISO_BD2PP BIT(31)
-#define BIT_LDOV12B_EN BIT(30)
-#define BIT_CKEN_BTGPS BIT(29)
-#define BIT_FEN_BTGPS BIT(28)
+#define BIT_ISO_BD2PP BIT(31)
+#define BIT_LDOV12B_EN BIT(30)
+#define BIT_CKEN_BTGPS BIT(29)
+#define BIT_FEN_BTGPS BIT(28)
+#define BIT_BTCPU_BOOTSEL BIT(27)
+#define BIT_SPI_SPEEDUP BIT(26)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_MULRW BIT(27)
+#define BIT_BT_SUS BIT(25)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8822C_SUPPORT)
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_BTCPU_BOOTSEL BIT(27)
-#define BIT_SPI_SPEEDUP BIT(26)
+#define BIT_BT_LDO_MODE BIT(25)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_DEVWAKE_PAD_TYPE_SEL BIT(24)
-#define BIT_CLKREQ_PAD_TYPE_SEL BIT(23)
+#define BIT_DEVWAKE_PAD_TYPE_SEL BIT(24)
+#define BIT_CLKREQ_PAD_TYPE_SEL BIT(23)
#endif
-
#if (HALMAC_8881A_SUPPORT)
-
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_CKSL_BZSLP BIT(23)
+#define BIT_CKSL_BZSLP BIT(23)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_EN_CPL_TIMEOUT_PS BIT(22)
+#define BIT_EN_CPL_TIMEOUT_PS BIT(22)
#endif
-
#if (HALMAC_8192E_SUPPORT)
-
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_BT_WAKE_HST_EN BIT(22)
+#define BIT_BT_WAKE_HST_EN BIT(22)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
+
+#define BIT_ISO_BTPON2PP BIT(22)
+
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_ISO_BTPON2PP BIT(22)
+#define BIT_REG_TXDMA_FAIL_PS BIT(21)
#endif
+#if (HALMAC_8192E_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
+
+#define BIT_WAKE_BT_EN BIT(21)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_REG_TXDMA_FAIL_PS BIT(21)
+#define BIT_BTCOEX_CMD BIT(21)
#endif
-
#if (HALMAC_8192E_SUPPORT)
-
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_WAKE_BT_EN BIT(21)
-#define BIT_EN_BT BIT(20)
+#define BIT_EN_BT BIT(20)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
+
+#define BIT_BT_UART_INTF BIT(20)
+
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_EN_HWENTR_L1 BIT(19)
+#define BIT_EN_HWENTR_L1 BIT(19)
#endif
-
#if (HALMAC_8192E_SUPPORT)
-
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_BT_SUSN_EN BIT(19)
+#define BIT_BT_SUSN_EN BIT(19)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_BT_HWROF_EN BIT(19)
+#define BIT_BT_HWROF_EN BIT(19)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_S3_RF_HW_EN BIT(19)
+#define BIT_S3_RF_HW_EN BIT(19)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_EN_ADV_CLKGATE BIT(18)
+#define BIT_EN_ADV_CLKGATE BIT(18)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_BT_FUNC_EN BIT(18)
+#define BIT_BT_FUNC_EN BIT(18)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_S2_RF_HW_EN BIT(18)
+#define BIT_S2_RF_HW_EN BIT(18)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_BT_HWPDN_SL BIT(17)
+#define BIT_BT_HWPDN_SL BIT(17)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_S1_RF_HW_EN BIT(17)
+#define BIT_S1_RF_HW_EN BIT(17)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_BT_DISN_EN BIT(16)
+#define BIT_BT_DISN_EN BIT(16)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_S0_RF_HW_EN BIT(16)
+#define BIT_S0_RF_HW_EN BIT(16)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_BT_PDN_PULL_EN BIT(15)
+#define BIT_BT_PDN_PULL_EN BIT(15)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_WL_PDN_PULL_EN BIT(14)
-#define BIT_EXTERNAL_REQUEST_PL BIT(13)
+#define BIT_WL_PDN_PULL_EN BIT(14)
+#define BIT_EXTERNAL_REQUEST_PL BIT(13)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_GPIO0_2_3_PULL_LOW_EN BIT(12)
+#define BIT_GPIO0_2_3_PULL_LOW_EN BIT(12)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_ISO_BA2PP BIT(11)
-#define BIT_BT_AFE_LDO_EN BIT(10)
+#define BIT_ISO_BA2PP BIT(11)
+#define BIT_BT_AFE_LDO_EN BIT(10)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_PDN_PIN_SEL BIT(10)
+#define BIT_PDN_PIN_SEL BIT(10)
#endif
-
#if (HALMAC_8192E_SUPPORT)
-
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_GPIO11_PULL_LOW_EN BIT(9)
+#define BIT_GPIO11_PULL_LOW_EN BIT(9)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_BT_AFE_PLL_EN BIT(9)
+#define BIT_BT_AFE_PLL_EN BIT(9)
#endif
-
#if (HALMAC_8192E_SUPPORT)
-
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_GPIO4_PULL_LOW_EN BIT(8)
+#define BIT_GPIO4_PULL_LOW_EN BIT(8)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_BT_DIG_CLK_EN BIT(8)
+#define BIT_BT_DIG_CLK_EN BIT(8)
#endif
-
#if (HALMAC_8192E_SUPPORT)
-
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_BT_WAKE_HST_SL BIT(7)
+#define BIT_BT_WAKE_HST_SL BIT(7)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_ASSERT_SPS_EN BIT(7)
+#define BIT_ASSERT_SPS_EN BIT(7)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT)
+/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
+#define BIT_UART_BRIDGE BIT(7)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_WAKE_BT_SL BIT(6)
+#define BIT_WAKE_BT_SL BIT(6)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_MASK_CHIPEN BIT(6)
+#define BIT_MASK_CHIPEN BIT(6)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_WL_DRV_EXIST_IDX BIT(5)
+#define BIT_OSC32K_CTRL_SEL BIT(6)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
+
+#define BIT_WLAN_32K_SEL BIT(6)
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_ASSERT_RF_EN BIT(5)
+#define BIT_WL_DRV_EXIST_IDX BIT(5)
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
+
+#define BIT_ASSERT_RF_EN BIT(5)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_DOP_EHPAD BIT(4)
+#define BIT_DOP_EHPAD BIT(4)
#endif
-
#if (HALMAC_8881A_SUPPORT)
-
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_BIT_DOP_EHPAD BIT(4)
+#define BIT_BIT_DOP_EHPAD BIT(4)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_WL_HWROF_EN BIT(3)
+#define BIT_WL_HWROF_EN BIT(3)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_SDIO_PAD_SHUTDOWNB BIT(3)
+#define BIT_SDIO_PAD_SHUTDOWNB BIT(3)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_WL_FUNC_EN BIT(2)
+#define BIT_WL_FUNC_EN BIT(2)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_SDIO_CLK_SMT BIT(2)
+#define BIT_SDIO_CLK_SMT BIT(2)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */
-#define BIT_WL_HWPDN_SL BIT(1)
-#define BIT_WL_HWPDN_EN BIT(0)
+#define BIT_WL_HWPDN_SL BIT(1)
+#define BIT_WL_HWPDN_EN BIT(0)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_SDM_DEBUG (Offset 0x006C) */
-
-#define BIT_SHIFT_F0N 23
-#define BIT_MASK_F0N 0x7
-#define BIT_F0N(x) (((x) & BIT_MASK_F0N) << BIT_SHIFT_F0N)
-#define BIT_GET_F0N(x) (((x) >> BIT_SHIFT_F0N) & BIT_MASK_F0N)
-
+#define BIT_SHIFT_F0N 23
+#define BIT_MASK_F0N 0x7
+#define BIT_F0N(x) (((x) & BIT_MASK_F0N) << BIT_SHIFT_F0N)
+#define BITS_F0N (BIT_MASK_F0N << BIT_SHIFT_F0N)
+#define BIT_CLEAR_F0N(x) ((x) & (~BITS_F0N))
+#define BIT_GET_F0N(x) (((x) >> BIT_SHIFT_F0N) & BIT_MASK_F0N)
+#define BIT_SET_F0N(x, v) (BIT_CLEAR_F0N(x) | BIT_F0N(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_SDM_DEBUG (Offset 0x006C) */
+#define BIT_BT_WAKE_DEV_EN_V1 BIT(19)
+#define BIT_BT_WAKE_HST_EN_V1 BIT(18)
+#define BIT_BT_WAKE_HST_PL_V1 BIT(17)
-/* 2 REG_GSSR (Offset 0x006C) */
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define BIT_SHIFT_GPIO_15_TO_0_VAL 16
-#define BIT_MASK_GPIO_15_TO_0_VAL 0xffff
-#define BIT_GPIO_15_TO_0_VAL(x) (((x) & BIT_MASK_GPIO_15_TO_0_VAL) << BIT_SHIFT_GPIO_15_TO_0_VAL)
-#define BIT_GET_GPIO_15_TO_0_VAL(x) (((x) >> BIT_SHIFT_GPIO_15_TO_0_VAL) & BIT_MASK_GPIO_15_TO_0_VAL)
+/* 2 REG_GSSR (Offset 0x006C) */
+#define BIT_SHIFT_GPIO_15_TO_0_VAL 16
+#define BIT_MASK_GPIO_15_TO_0_VAL 0xffff
+#define BIT_GPIO_15_TO_0_VAL(x) \
+ (((x) & BIT_MASK_GPIO_15_TO_0_VAL) << BIT_SHIFT_GPIO_15_TO_0_VAL)
+#define BITS_GPIO_15_TO_0_VAL \
+ (BIT_MASK_GPIO_15_TO_0_VAL << BIT_SHIFT_GPIO_15_TO_0_VAL)
+#define BIT_CLEAR_GPIO_15_TO_0_VAL(x) ((x) & (~BITS_GPIO_15_TO_0_VAL))
+#define BIT_GET_GPIO_15_TO_0_VAL(x) \
+ (((x) >> BIT_SHIFT_GPIO_15_TO_0_VAL) & BIT_MASK_GPIO_15_TO_0_VAL)
+#define BIT_SET_GPIO_15_TO_0_VAL(x, v) \
+ (BIT_CLEAR_GPIO_15_TO_0_VAL(x) | BIT_GPIO_15_TO_0_VAL(v))
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_SDM_DEBUG (Offset 0x006C) */
+#define BIT_BT_CLKREQ_EN_V1 BIT(16)
-#define BIT_SHIFT_F0F 10
-#define BIT_MASK_F0F 0x1fff
-#define BIT_F0F(x) (((x) & BIT_MASK_F0F) << BIT_SHIFT_F0F)
-#define BIT_GET_F0F(x) (((x) >> BIT_SHIFT_F0F) & BIT_MASK_F0F)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_DIVN 4
-#define BIT_MASK_DIVN 0x3f
-#define BIT_DIVN(x) (((x) & BIT_MASK_DIVN) << BIT_SHIFT_DIVN)
-#define BIT_GET_DIVN(x) (((x) >> BIT_SHIFT_DIVN) & BIT_MASK_DIVN)
+/* 2 REG_SDM_DEBUG (Offset 0x006C) */
+#define BIT_SHIFT_F0F 10
+#define BIT_MASK_F0F 0x1fff
+#define BIT_F0F(x) (((x) & BIT_MASK_F0F) << BIT_SHIFT_F0F)
+#define BITS_F0F (BIT_MASK_F0F << BIT_SHIFT_F0F)
+#define BIT_CLEAR_F0F(x) ((x) & (~BITS_F0F))
+#define BIT_GET_F0F(x) (((x) >> BIT_SHIFT_F0F) & BIT_MASK_F0F)
+#define BIT_SET_F0F(x, v) (BIT_CLEAR_F0F(x) | BIT_F0F(v))
-#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM 0
-#define BIT_MASK_BB_DBG_SEL_AFE_SDM 0xf
-#define BIT_BB_DBG_SEL_AFE_SDM(x) (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM) << BIT_SHIFT_BB_DBG_SEL_AFE_SDM)
-#define BIT_GET_BB_DBG_SEL_AFE_SDM(x) (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM) & BIT_MASK_BB_DBG_SEL_AFE_SDM)
+#endif
+#if (HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_SDM_DEBUG (Offset 0x006C) */
+#define BIT_GPIO_IE_V18 BIT(10)
+#define BIT_PCIE_IE_V18 BIT(9)
+#define BIT_UART_IE_V18 BIT(8)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SDM_DEBUG (Offset 0x006C) */
+#define BIT_SHIFT_DIVN 4
+#define BIT_MASK_DIVN 0x3f
+#define BIT_DIVN(x) (((x) & BIT_MASK_DIVN) << BIT_SHIFT_DIVN)
+#define BITS_DIVN (BIT_MASK_DIVN << BIT_SHIFT_DIVN)
+#define BIT_CLEAR_DIVN(x) ((x) & (~BITS_DIVN))
+#define BIT_GET_DIVN(x) (((x) >> BIT_SHIFT_DIVN) & BIT_MASK_DIVN)
+#define BIT_SET_DIVN(x, v) (BIT_CLEAR_DIVN(x) | BIT_DIVN(v))
-#define BIT_SHIFT_WLCLK_PHASE 0
-#define BIT_MASK_WLCLK_PHASE 0x1f
-#define BIT_WLCLK_PHASE(x) (((x) & BIT_MASK_WLCLK_PHASE) << BIT_SHIFT_WLCLK_PHASE)
-#define BIT_GET_WLCLK_PHASE(x) (((x) >> BIT_SHIFT_WLCLK_PHASE) & BIT_MASK_WLCLK_PHASE)
-
+#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM 0
+#define BIT_MASK_BB_DBG_SEL_AFE_SDM 0xf
+#define BIT_BB_DBG_SEL_AFE_SDM(x) \
+ (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM) << BIT_SHIFT_BB_DBG_SEL_AFE_SDM)
+#define BITS_BB_DBG_SEL_AFE_SDM \
+ (BIT_MASK_BB_DBG_SEL_AFE_SDM << BIT_SHIFT_BB_DBG_SEL_AFE_SDM)
+#define BIT_CLEAR_BB_DBG_SEL_AFE_SDM(x) ((x) & (~BITS_BB_DBG_SEL_AFE_SDM))
+#define BIT_GET_BB_DBG_SEL_AFE_SDM(x) \
+ (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM) & BIT_MASK_BB_DBG_SEL_AFE_SDM)
+#define BIT_SET_BB_DBG_SEL_AFE_SDM(x, v) \
+ (BIT_CLEAR_BB_DBG_SEL_AFE_SDM(x) | BIT_BB_DBG_SEL_AFE_SDM(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_SDM_DEBUG (Offset 0x006C) */
+#define BIT_SHIFT_WLCLK_PHASE 0
+#define BIT_MASK_WLCLK_PHASE 0x1f
+#define BIT_WLCLK_PHASE(x) \
+ (((x) & BIT_MASK_WLCLK_PHASE) << BIT_SHIFT_WLCLK_PHASE)
+#define BITS_WLCLK_PHASE (BIT_MASK_WLCLK_PHASE << BIT_SHIFT_WLCLK_PHASE)
+#define BIT_CLEAR_WLCLK_PHASE(x) ((x) & (~BITS_WLCLK_PHASE))
+#define BIT_GET_WLCLK_PHASE(x) \
+ (((x) >> BIT_SHIFT_WLCLK_PHASE) & BIT_MASK_WLCLK_PHASE)
+#define BIT_SET_WLCLK_PHASE(x, v) \
+ (BIT_CLEAR_WLCLK_PHASE(x) | BIT_WLCLK_PHASE(v))
-/* 2 REG_GSSR (Offset 0x006C) */
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define BIT_SHIFT_GPIO_15_TO_0_EN 0
-#define BIT_MASK_GPIO_15_TO_0_EN 0xffff
-#define BIT_GPIO_15_TO_0_EN(x) (((x) & BIT_MASK_GPIO_15_TO_0_EN) << BIT_SHIFT_GPIO_15_TO_0_EN)
-#define BIT_GET_GPIO_15_TO_0_EN(x) (((x) >> BIT_SHIFT_GPIO_15_TO_0_EN) & BIT_MASK_GPIO_15_TO_0_EN)
+/* 2 REG_GSSR (Offset 0x006C) */
+#define BIT_SHIFT_GPIO_15_TO_0_EN 0
+#define BIT_MASK_GPIO_15_TO_0_EN 0xffff
+#define BIT_GPIO_15_TO_0_EN(x) \
+ (((x) & BIT_MASK_GPIO_15_TO_0_EN) << BIT_SHIFT_GPIO_15_TO_0_EN)
+#define BITS_GPIO_15_TO_0_EN \
+ (BIT_MASK_GPIO_15_TO_0_EN << BIT_SHIFT_GPIO_15_TO_0_EN)
+#define BIT_CLEAR_GPIO_15_TO_0_EN(x) ((x) & (~BITS_GPIO_15_TO_0_EN))
+#define BIT_GET_GPIO_15_TO_0_EN(x) \
+ (((x) >> BIT_SHIFT_GPIO_15_TO_0_EN) & BIT_MASK_GPIO_15_TO_0_EN)
+#define BIT_SET_GPIO_15_TO_0_EN(x, v) \
+ (BIT_CLEAR_GPIO_15_TO_0_EN(x) | BIT_GPIO_15_TO_0_EN(v))
/* 2 REG_SYS_CLKR (Offset 0x0070) */
-#define BIT_BBRSTB_STANDBY_V1 BIT(28)
+#define BIT_BBRSTB_STANDBY_V1 BIT(28)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */
-#define BIT_DBG_GNT_WL_BT BIT(27)
+#define BIT_DBG_GNT_WL_BT BIT(27)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_CLKR (Offset 0x0070) */
-#define BIT_AFE_PORT3_ISO BIT(27)
+#define BIT_AFE_PORT3_ISO BIT(27)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */
-#define BIT_LTE_MUX_CTRL_PATH BIT(26)
+#define BIT_LTE_MUX_CTRL_PATH BIT(26)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_CLKR (Offset 0x0070) */
-#define BIT_AFE_PORT2_ISO BIT(26)
-#define BIT_AFE_PORT1_ISO BIT(25)
+#define BIT_AFE_PORT2_ISO BIT(26)
+#define BIT_AFE_PORT1_ISO BIT(25)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */
+#define BIT_LTE_COEX_UART BIT(25)
-/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define BIT_LTE_COEX_UART BIT(25)
+/* 2 REG_SYS_CLKR (Offset 0x0070) */
+
+#define BIT_AFE_PORT0_ISO BIT(24)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */
+#define BIT_3W_LTE_WL_GPIO BIT(24)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
/* 2 REG_SYS_CLKR (Offset 0x0070) */
-#define BIT_AFE_PORT0_ISO BIT(24)
+#define BIT_USB_PWR_OFF_SEL BIT(23)
+#define BIT_USB_HOST_PWR_OFF_EN_V1 BIT(22)
+#define BIT_SYM_LPS_BLOCK_EN_V1 BIT(21)
+#define BIT_USB_LPM_ACT_EN_V1 BIT(20)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */
+
+#define BIT_SDIO_INT_POLARITY BIT(19)
+#define BIT_SDIO_INT BIT(18)
+
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */
-#define BIT_3W_LTE_WL_GPIO BIT(24)
+#define BIT_SDIO_OFF_EN BIT(17)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_CLKR (Offset 0x0070) */
-#define BIT_USB_PWR_OFF_SEL BIT(23)
-#define BIT_USB_HOST_PWR_OFF_EN_V1 BIT(22)
-#define BIT_SYM_LPS_BLOCK_EN_V1 BIT(21)
-#define BIT_USB_LPM_ACT_EN_V1 BIT(20)
+#define BIT_SDIO_OFF_EN_V1 BIT(17)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */
-#define BIT_SDIO_INT_POLARITY BIT(19)
-#define BIT_SDIO_INT BIT(18)
+#define BIT_SDIO_ON_EN BIT(16)
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CLKR (Offset 0x0070) */
+
+#define BIT_SDIO_ON_EN_V1 BIT(16)
+#define BIT_DIS_U3MB_INU2 BIT(13)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8822C_SUPPORT)
/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */
-#define BIT_SDIO_OFF_EN BIT(17)
+#define BIT_PCIE_FORCE_PWR_NGAT BIT(13)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_CLKR (Offset 0x0070) */
-#define BIT_SDIO_OFF_EN_V1 BIT(17)
+#define BIT_USB3_MDIO_EN BIT(12)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */
+#define BIT_PCIE_CALIB_EN_V1 BIT(12)
-/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CLKR (Offset 0x0070) */
-#define BIT_SDIO_ON_EN BIT(16)
+#define BIT_USB3_BG_EN BIT(11)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */
+
+#define BIT_PAGE3_AUXCLK_GATE BIT(11)
+
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
/* 2 REG_SYS_CLKR (Offset 0x0070) */
-#define BIT_SDIO_ON_EN_V1 BIT(16)
-#define BIT_DIS_U3MB_INU2 BIT(13)
-#define BIT_USB3_MDIO_EN BIT(12)
-#define BIT_USB3_BG_EN BIT(11)
-#define BIT_USB3_MB_EN BIT(10)
+#define BIT_USB3_MB_EN BIT(10)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */
+#define BIT_PCIE_WAIT_TIMEOUT_EVENT BIT(10)
+#define BIT_PCIE_WAIT_TIME BIT(9)
-/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define BIT_PCIE_WAIT_TIMEOUT_EVENT BIT(10)
-#define BIT_PCIE_WAIT_TIME BIT(9)
+/* 2 REG_SYS_CLKR (Offset 0x0070) */
+
+#define BIT_SHIFT_USB3_CK_MD 8
+#define BIT_MASK_USB3_CK_MD 0x3
+#define BIT_USB3_CK_MD(x) (((x) & BIT_MASK_USB3_CK_MD) << BIT_SHIFT_USB3_CK_MD)
+#define BITS_USB3_CK_MD (BIT_MASK_USB3_CK_MD << BIT_SHIFT_USB3_CK_MD)
+#define BIT_CLEAR_USB3_CK_MD(x) ((x) & (~BITS_USB3_CK_MD))
+#define BIT_GET_USB3_CK_MD(x) \
+ (((x) >> BIT_SHIFT_USB3_CK_MD) & BIT_MASK_USB3_CK_MD)
+#define BIT_SET_USB3_CK_MD(x, v) (BIT_CLEAR_USB3_CK_MD(x) | BIT_USB3_CK_MD(v))
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */
+#define BIT_MPCIE_REFCLK_XTAL_SEL BIT(8)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
/* 2 REG_SYS_CLKR (Offset 0x0070) */
+#define BIT_USB3_CKBUF BIT(7)
+#define BIT_USB3_IBX_EN BIT(6)
-#define BIT_SHIFT_USB3_CK_MD 8
-#define BIT_MASK_USB3_CK_MD 0x3
-#define BIT_USB3_CK_MD(x) (((x) & BIT_MASK_USB3_CK_MD) << BIT_SHIFT_USB3_CK_MD)
-#define BIT_GET_USB3_CK_MD(x) (((x) >> BIT_SHIFT_USB3_CK_MD) & BIT_MASK_USB3_CK_MD)
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */
+#define BIT_BT_CLKREQ_EN BIT(6)
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_SYS_CLKR (Offset 0x0070) */
+
+#define BIT_U3_MB_MASK BIT(5)
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */
-#define BIT_MPCIE_REFCLK_XTAL_SEL BIT(8)
+#define BIT_BT_CTRL_USB_PWR_BACKDOOR BIT(5)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_CLKR (Offset 0x0070) */
-#define BIT_USB3_CKBUF BIT(7)
-#define BIT_USB3_IBX_EN BIT(6)
-#define BIT_U3_MB_MASK BIT(5)
-#define BIT_U3_BG_MASK BIT(4)
-#define BIT_DIS_USB3_MB_POLLING BIT(3)
-#define BIT_PDN_MASK BIT(2)
-#define BIT_NO_PDN_CHIPOFF BIT(1)
+#define BIT_U3_BG_MASK BIT(4)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8821C_SUPPORT)
+/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */
+
+#define BIT_SHIFT_USB_CKREF_CML_R 4
+#define BIT_MASK_USB_CKREF_CML_R 0x3
+#define BIT_USB_CKREF_CML_R(x) \
+ (((x) & BIT_MASK_USB_CKREF_CML_R) << BIT_SHIFT_USB_CKREF_CML_R)
+#define BITS_USB_CKREF_CML_R \
+ (BIT_MASK_USB_CKREF_CML_R << BIT_SHIFT_USB_CKREF_CML_R)
+#define BIT_CLEAR_USB_CKREF_CML_R(x) ((x) & (~BITS_USB_CKREF_CML_R))
+#define BIT_GET_USB_CKREF_CML_R(x) \
+ (((x) >> BIT_SHIFT_USB_CKREF_CML_R) & BIT_MASK_USB_CKREF_CML_R)
+#define BIT_SET_USB_CKREF_CML_R(x, v) \
+ (BIT_CLEAR_USB_CKREF_CML_R(x) | BIT_USB_CKREF_CML_R(v))
+
+#endif
+#if (HALMAC_8822C_SUPPORT)
/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */
-#define BIT_RES_USB_MASS_STORAGE_DESC BIT(1)
+#define BIT_USB_D_STATE_HOLD BIT(4)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_CLKR (Offset 0x0070) */
-#define BIT_PDN_HCOUNT BIT(0)
+#define BIT_DIS_USB3_MB_POLLING BIT(3)
#endif
-
-#if (HALMAC_8821C_SUPPORT)
-
+#if (HALMAC_8822C_SUPPORT)
/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */
-#define BIT_USB_WAIT_TIME BIT(0)
+#define BIT_REG_FORCE_DP BIT(3)
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_SYS_CLKR (Offset 0x0070) */
+#define BIT_PDN_MASK BIT(2)
-/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_TSFT_SEL 29
-#define BIT_MASK_TSFT_SEL 0x7
-#define BIT_TSFT_SEL(x) (((x) & BIT_MASK_TSFT_SEL) << BIT_SHIFT_TSFT_SEL)
-#define BIT_GET_TSFT_SEL(x) (((x) >> BIT_SHIFT_TSFT_SEL) & BIT_MASK_TSFT_SEL)
+/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */
+#define BIT_SHIFT_USB_CKREF_D2S_I 2
+#define BIT_MASK_USB_CKREF_D2S_I 0x3
+#define BIT_USB_CKREF_D2S_I(x) \
+ (((x) & BIT_MASK_USB_CKREF_D2S_I) << BIT_SHIFT_USB_CKREF_D2S_I)
+#define BITS_USB_CKREF_D2S_I \
+ (BIT_MASK_USB_CKREF_D2S_I << BIT_SHIFT_USB_CKREF_D2S_I)
+#define BIT_CLEAR_USB_CKREF_D2S_I(x) ((x) & (~BITS_USB_CKREF_D2S_I))
+#define BIT_GET_USB_CKREF_D2S_I(x) \
+ (((x) >> BIT_SHIFT_USB_CKREF_D2S_I) & BIT_MASK_USB_CKREF_D2S_I)
+#define BIT_SET_USB_CKREF_D2S_I(x, v) \
+ (BIT_CLEAR_USB_CKREF_D2S_I(x) | BIT_USB_CKREF_D2S_I(v))
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814AMP_SUPPORT)
+/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */
+#define BIT_REG_DP_MODE BIT(2)
-/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define BIT_SHIFT_XTAL_SEL_0_V1 28
-#define BIT_MASK_XTAL_SEL_0_V1 0xf
-#define BIT_XTAL_SEL_0_V1(x) (((x) & BIT_MASK_XTAL_SEL_0_V1) << BIT_SHIFT_XTAL_SEL_0_V1)
-#define BIT_GET_XTAL_SEL_0_V1(x) (((x) >> BIT_SHIFT_XTAL_SEL_0_V1) & BIT_MASK_XTAL_SEL_0_V1)
+/* 2 REG_SYS_CLKR (Offset 0x0070) */
-#define BIT_ISO_RFC2RF_3 BIT(27)
-#define BIT_ISO_RFC2RF_2 BIT(26)
+#define BIT_NO_PDN_CHIPOFF BIT(1)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */
+#define BIT_RES_USB_MASS_STORAGE_DESC BIT(1)
-/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_SYS_CLKR (Offset 0x0070) */
+#define BIT_PDN_HCOUNT BIT(0)
-#define BIT_SHIFT_RPWM 24
-#define BIT_MASK_RPWM 0xff
-#define BIT_RPWM(x) (((x) & BIT_MASK_RPWM) << BIT_SHIFT_RPWM)
-#define BIT_GET_RPWM(x) (((x) >> BIT_SHIFT_RPWM) & BIT_MASK_RPWM)
+#endif
-#define BIT_ROM_DLEN BIT(19)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_ROM_PGE 16
-#define BIT_MASK_ROM_PGE 0x7
-#define BIT_ROM_PGE(x) (((x) & BIT_MASK_ROM_PGE) << BIT_SHIFT_ROM_PGE)
-#define BIT_GET_ROM_PGE(x) (((x) >> BIT_SHIFT_ROM_PGE) & BIT_MASK_ROM_PGE)
+/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */
+#define BIT_USB_WAIT_TIME BIT(0)
#endif
+#if (HALMAC_8822B_SUPPORT)
+
+/* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */
+
+#define BIT_SHIFT_SI_AUTHORIZATION 0
+#define BIT_MASK_SI_AUTHORIZATION 0xff
+#define BIT_SI_AUTHORIZATION(x) \
+ (((x) & BIT_MASK_SI_AUTHORIZATION) << BIT_SHIFT_SI_AUTHORIZATION)
+#define BITS_SI_AUTHORIZATION \
+ (BIT_MASK_SI_AUTHORIZATION << BIT_SHIFT_SI_AUTHORIZATION)
+#define BIT_CLEAR_SI_AUTHORIZATION(x) ((x) & (~BITS_SI_AUTHORIZATION))
+#define BIT_GET_SI_AUTHORIZATION(x) \
+ (((x) >> BIT_SHIFT_SI_AUTHORIZATION) & BIT_MASK_SI_AUTHORIZATION)
+#define BIT_SET_SI_AUTHORIZATION(x, v) \
+ (BIT_CLEAR_SI_AUTHORIZATION(x) | BIT_SI_AUTHORIZATION(v))
-#if (HALMAC_8814A_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
-#define BIT_R_FORCE_CLK_U3 BIT(13)
+#define BIT_SHIFT_TSFT_SEL 29
+#define BIT_MASK_TSFT_SEL 0x7
+#define BIT_TSFT_SEL(x) (((x) & BIT_MASK_TSFT_SEL) << BIT_SHIFT_TSFT_SEL)
+#define BITS_TSFT_SEL (BIT_MASK_TSFT_SEL << BIT_SHIFT_TSFT_SEL)
+#define BIT_CLEAR_TSFT_SEL(x) ((x) & (~BITS_TSFT_SEL))
+#define BIT_GET_TSFT_SEL(x) (((x) >> BIT_SHIFT_TSFT_SEL) & BIT_MASK_TSFT_SEL)
+#define BIT_SET_TSFT_SEL(x, v) (BIT_CLEAR_TSFT_SEL(x) | BIT_TSFT_SEL(v))
#endif
+#if (HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
+
+#define BIT_SHIFT_XTAL_SEL_0_V1 28
+#define BIT_MASK_XTAL_SEL_0_V1 0xf
+#define BIT_XTAL_SEL_0_V1(x) \
+ (((x) & BIT_MASK_XTAL_SEL_0_V1) << BIT_SHIFT_XTAL_SEL_0_V1)
+#define BITS_XTAL_SEL_0_V1 (BIT_MASK_XTAL_SEL_0_V1 << BIT_SHIFT_XTAL_SEL_0_V1)
+#define BIT_CLEAR_XTAL_SEL_0_V1(x) ((x) & (~BITS_XTAL_SEL_0_V1))
+#define BIT_GET_XTAL_SEL_0_V1(x) \
+ (((x) >> BIT_SHIFT_XTAL_SEL_0_V1) & BIT_MASK_XTAL_SEL_0_V1)
+#define BIT_SET_XTAL_SEL_0_V1(x, v) \
+ (BIT_CLEAR_XTAL_SEL_0_V1(x) | BIT_XTAL_SEL_0_V1(v))
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
-#define BIT_USB_HOST_PWR_OFF_EN BIT(12)
+#define BIT_TSFT_BAND_SEL BIT(28)
#endif
+#if (HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8814A_SUPPORT)
+/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
+
+#define BIT_ISO_RFC2RF_3 BIT(27)
+#define BIT_ISO_RFC2RF_2 BIT(26)
+
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
-#define BIT_R_USB2_AUTOLOAD BIT(12)
+#define BIT_SHIFT_RPWM 24
+#define BIT_MASK_RPWM 0xff
+#define BIT_RPWM(x) (((x) & BIT_MASK_RPWM) << BIT_SHIFT_RPWM)
+#define BITS_RPWM (BIT_MASK_RPWM << BIT_SHIFT_RPWM)
+#define BIT_CLEAR_RPWM(x) ((x) & (~BITS_RPWM))
+#define BIT_GET_RPWM(x) (((x) >> BIT_SHIFT_RPWM) & BIT_MASK_RPWM)
+#define BIT_SET_RPWM(x, v) (BIT_CLEAR_RPWM(x) | BIT_RPWM(v))
+
+#define BIT_ROM_DLEN BIT(19)
#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
+
+#define BIT_SDIO_PAD_E5 BIT(18)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
-#define BIT_SYM_LPS_BLOCK_EN BIT(11)
+#define BIT_SHIFT_ROM_PGE 16
+#define BIT_MASK_ROM_PGE 0x7
+#define BIT_ROM_PGE(x) (((x) & BIT_MASK_ROM_PGE) << BIT_SHIFT_ROM_PGE)
+#define BITS_ROM_PGE (BIT_MASK_ROM_PGE << BIT_SHIFT_ROM_PGE)
+#define BIT_CLEAR_ROM_PGE(x) ((x) & (~BITS_ROM_PGE))
+#define BIT_GET_ROM_PGE(x) (((x) >> BIT_SHIFT_ROM_PGE) & BIT_MASK_ROM_PGE)
+#define BIT_SET_ROM_PGE(x, v) (BIT_CLEAR_ROM_PGE(x) | BIT_ROM_PGE(v))
#endif
-
#if (HALMAC_8814A_SUPPORT)
-
/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
-#define BIT_FORCE_U2CK BIT(11)
+#define BIT_R_FORCE_CLK_U3 BIT(13)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
+
+#define BIT_USB_HOST_PWR_OFF_EN BIT(12)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8814A_SUPPORT)
/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
-#define BIT_USB_LPM_ACT_EN BIT(10)
+#define BIT_R_USB2_AUTOLOAD BIT(12)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
+
+#define BIT_SYM_LPS_BLOCK_EN BIT(11)
+
+#endif
+#if (HALMAC_8814A_SUPPORT)
/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
-#define BIT_FORCE_CLK BIT(10)
+#define BIT_FORCE_U2CK BIT(11)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
+
+#define BIT_USB_LPM_ACT_EN BIT(10)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
-#define BIT_USB_LPM_NY BIT(9)
+#define BIT_FORCE_CLK BIT(10)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
+
+#define BIT_USB_LPM_NY BIT(9)
+
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
-#define BIT_U2_FORCE BIT(9)
+#define BIT_U2_FORCE BIT(9)
#endif
+#if (HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
+
+#define BIT_IBX_EN_VALUE BIT(9)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
-#define BIT_USB_SUS_DIS BIT(8)
+#define BIT_USB_SUS_DIS BIT(8)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
-#define BIT_U3_FORCE BIT(8)
+#define BIT_U3_FORCE BIT(8)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
+#define BIT_IB_EN_VALUE BIT(8)
+#define BIT_EN_LW_PWR BIT(6)
-/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_SDIO_PAD_E 5
-#define BIT_MASK_SDIO_PAD_E 0x7
-#define BIT_SDIO_PAD_E(x) (((x) & BIT_MASK_SDIO_PAD_E) << BIT_SHIFT_SDIO_PAD_E)
-#define BIT_GET_SDIO_PAD_E(x) (((x) >> BIT_SHIFT_SDIO_PAD_E) & BIT_MASK_SDIO_PAD_E)
+/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
+#define BIT_SHIFT_SDIO_PAD_E 5
+#define BIT_MASK_SDIO_PAD_E 0x7
+#define BIT_SDIO_PAD_E(x) (((x) & BIT_MASK_SDIO_PAD_E) << BIT_SHIFT_SDIO_PAD_E)
+#define BITS_SDIO_PAD_E (BIT_MASK_SDIO_PAD_E << BIT_SHIFT_SDIO_PAD_E)
+#define BIT_CLEAR_SDIO_PAD_E(x) ((x) & (~BITS_SDIO_PAD_E))
+#define BIT_GET_SDIO_PAD_E(x) \
+ (((x) >> BIT_SHIFT_SDIO_PAD_E) & BIT_MASK_SDIO_PAD_E)
+#define BIT_SET_SDIO_PAD_E(x, v) (BIT_CLEAR_SDIO_PAD_E(x) | BIT_SDIO_PAD_E(v))
#endif
+#if (HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
+
+#define BIT_EN_REGU BIT(5)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
-#define BIT_USB_LPPLL_EN BIT(4)
+#define BIT_USB_LPPLL_EN BIT(4)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
-#define BIT_SDIO_H3L1 BIT(4)
+#define BIT_SDIO_H3L1 BIT(4)
#endif
+#if (HALMAC_8822C_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
+
+#define BIT_FORCED_IB_EN BIT(4)
+#define BIT_EN_PC BIT(4)
+#define BIT_USB1_1_USB2_0_DECISION BIT(3)
+#define BIT_EN_REGBG BIT(3)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
-#define BIT_ROP_SW15 BIT(2)
+#define BIT_ROP_SW15 BIT(2)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
+#define BIT_SHIFT_USB23_SW_MODE 2
+#define BIT_MASK_USB23_SW_MODE 0x3
+#define BIT_USB23_SW_MODE(x) \
+ (((x) & BIT_MASK_USB23_SW_MODE) << BIT_SHIFT_USB23_SW_MODE)
+#define BITS_USB23_SW_MODE (BIT_MASK_USB23_SW_MODE << BIT_SHIFT_USB23_SW_MODE)
+#define BIT_CLEAR_USB23_SW_MODE(x) ((x) & (~BITS_USB23_SW_MODE))
+#define BIT_GET_USB23_SW_MODE(x) \
+ (((x) >> BIT_SHIFT_USB23_SW_MODE) & BIT_MASK_USB23_SW_MODE)
+#define BIT_SET_USB23_SW_MODE(x, v) \
+ (BIT_CLEAR_USB23_SW_MODE(x) | BIT_USB23_SW_MODE(v))
-#define BIT_SHIFT_USB23_SW_MODE 2
-#define BIT_MASK_USB23_SW_MODE 0x3
-#define BIT_USB23_SW_MODE(x) (((x) & BIT_MASK_USB23_SW_MODE) << BIT_SHIFT_USB23_SW_MODE)
-#define BIT_GET_USB23_SW_MODE(x) (((x) >> BIT_SHIFT_USB23_SW_MODE) & BIT_MASK_USB23_SW_MODE)
+#endif
+#if (HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
+#define BIT_REG_BG_LPF BIT(2)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
-#define BIT_PCI_CKRDY_OPT BIT(1)
+#define BIT_PCI_CKRDY_OPT BIT(1)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
-#define BIT_PCLK_VLD_SEL BIT(1)
+#define BIT_PCLK_VLD_SEL BIT(1)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
+
+#define BIT_PCI_VAUX_EN BIT(0)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
-#define BIT_PCI_VAUX_EN BIT(0)
+#define BIT_VAUX_EN BIT(0)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
+#define BIT_SHIFT_REG_BG 0
+#define BIT_MASK_REG_BG 0x3
+#define BIT_REG_BG(x) (((x) & BIT_MASK_REG_BG) << BIT_SHIFT_REG_BG)
+#define BITS_REG_BG (BIT_MASK_REG_BG << BIT_SHIFT_REG_BG)
+#define BIT_CLEAR_REG_BG(x) ((x) & (~BITS_REG_BG))
+#define BIT_GET_REG_BG(x) (((x) >> BIT_SHIFT_REG_BG) & BIT_MASK_REG_BG)
+#define BIT_SET_REG_BG(x, v) (BIT_CLEAR_REG_BG(x) | BIT_REG_BG(v))
-/* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */
+#define BIT_SHIFT_REG_VADJ 0
+#define BIT_MASK_REG_VADJ 0xf
+#define BIT_REG_VADJ(x) (((x) & BIT_MASK_REG_VADJ) << BIT_SHIFT_REG_VADJ)
+#define BITS_REG_VADJ (BIT_MASK_REG_VADJ << BIT_SHIFT_REG_VADJ)
+#define BIT_CLEAR_REG_VADJ(x) ((x) & (~BITS_REG_VADJ))
+#define BIT_GET_REG_VADJ(x) (((x) >> BIT_SHIFT_REG_VADJ) & BIT_MASK_REG_VADJ)
+#define BIT_SET_REG_VADJ(x, v) (BIT_CLEAR_REG_VADJ(x) | BIT_REG_VADJ(v))
+
+#endif
-#define BIT_VAUX_EN BIT(0)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
/* 2 REG_AFE_XTAL_CTRL_EXT (Offset 0x0078) */
-#define BIT_SDM_ORDER BIT(30)
-#define BIT_XTAL_DRV_RF_LATCH_V1 BIT(29)
-#define BIT_XTAL_VDD_SEL_V1 BIT(28)
+#define BIT_SDM_ORDER BIT(30)
+#define BIT_XTAL_DRV_RF_LATCH_V1 BIT(29)
+#define BIT_XTAL_VDD_SEL_V1 BIT(28)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_AFE_CTRL4 (Offset 0x0078) */
-#define BIT_XTAL_DRV_RF_LATCH BIT(27)
+#define BIT_XTAL_DRV_RF_LATCH BIT(27)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_XTAL_CTRL_EXT (Offset 0x0078) */
-#define BIT_XQSEL_RF_AWAKE_V1 BIT(27)
+#define BIT_XQSEL_RF_AWAKE_V1 BIT(27)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_AFE_CTRL4 (Offset 0x0078) */
-#define BIT_XTAL_VDD_SEL BIT(26)
+#define BIT_XTAL_VDD_SEL BIT(26)
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_AFE_CTRL4 (Offset 0x0078) */
-#define BIT_RF1_SDMRSTB BIT(26)
+#define BIT_RF1_SDMRSTB BIT(26)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_AFE_XTAL_CTRL_EXT (Offset 0x0078) */
-#define BIT_GATED_XTAL_OK0_V1 BIT(26)
+#define BIT_GATED_XTAL_OK0_V1 BIT(26)
#endif
-
#if (HALMAC_8192E_SUPPORT)
-
/* 2 REG_AFE_CTRL4 (Offset 0x0078) */
-#define BIT_XQSEL_RF BIT(25)
+#define BIT_XQSEL_RF BIT(25)
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_AFE_CTRL4 (Offset 0x0078) */
-#define BIT_RF1_RSTB BIT(25)
+#define BIT_RF1_RSTB BIT(25)
#endif
-
#if (HALMAC_8881A_SUPPORT)
-
/* 2 REG_AFE_CTRL4 (Offset 0x0078) */
-#define BIT_XQSEL_RF_AWAKE BIT(25)
+#define BIT_XQSEL_RF_AWAKE BIT(25)
#endif
-
#if (HALMAC_8192E_SUPPORT)
-
/* 2 REG_AFE_CTRL4 (Offset 0x0078) */
-#define BIT_XQSEL_RF_INITIAL BIT(24)
+#define BIT_XQSEL_RF_INITIAL BIT(24)
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_AFE_CTRL4 (Offset 0x0078) */
-#define BIT_RF1_EN BIT(24)
+#define BIT_RF1_EN BIT(24)
#endif
-
#if (HALMAC_8881A_SUPPORT)
-
/* 2 REG_AFE_CTRL4 (Offset 0x0078) */
-#define BIT_XQSEL_BIT1 BIT(24)
+#define BIT_XQSEL_BIT1 BIT(24)
#endif
-
#if (HALMAC_8192E_SUPPORT)
-
/* 2 REG_AFE_CTRL4 (Offset 0x0078) */
-#define BIT_REG_VREF_SEL BIT(23)
+#define BIT_REG_VREF_SEL BIT(23)
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_AFE_CTRL4 (Offset 0x0078) */
+#define BIT_DITHER_SDM_BIT3 BIT(23)
-/* 2 REG_AFE_XTAL_CTRL_EXT (Offset 0x0078) */
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define BIT_SHIFT_F0N_2_TO_0 23
-#define BIT_MASK_F0N_2_TO_0 0x7
-#define BIT_F0N_2_TO_0(x) (((x) & BIT_MASK_F0N_2_TO_0) << BIT_SHIFT_F0N_2_TO_0)
-#define BIT_GET_F0N_2_TO_0(x) (((x) >> BIT_SHIFT_F0N_2_TO_0) & BIT_MASK_F0N_2_TO_0)
+/* 2 REG_AFE_XTAL_CTRL_EXT (Offset 0x0078) */
+#define BIT_SHIFT_F0N_2_TO_0 23
+#define BIT_MASK_F0N_2_TO_0 0x7
+#define BIT_F0N_2_TO_0(x) (((x) & BIT_MASK_F0N_2_TO_0) << BIT_SHIFT_F0N_2_TO_0)
+#define BITS_F0N_2_TO_0 (BIT_MASK_F0N_2_TO_0 << BIT_SHIFT_F0N_2_TO_0)
+#define BIT_CLEAR_F0N_2_TO_0(x) ((x) & (~BITS_F0N_2_TO_0))
+#define BIT_GET_F0N_2_TO_0(x) \
+ (((x) >> BIT_SHIFT_F0N_2_TO_0) & BIT_MASK_F0N_2_TO_0)
+#define BIT_SET_F0N_2_TO_0(x, v) (BIT_CLEAR_F0N_2_TO_0(x) | BIT_F0N_2_TO_0(v))
#endif
-
#if (HALMAC_8192E_SUPPORT)
-
/* 2 REG_AFE_CTRL4 (Offset 0x0078) */
-#define BIT_REG_LPFEN BIT(22)
-#define BIT_REG_KVCO BIT(21)
-#define BIT_XTAL_DRV_AGPIO_BIT1 BIT(20)
+#define BIT_REG_LPFEN BIT(22)
+#define BIT_REG_KVCO BIT(21)
+#define BIT_XTAL_DRV_AGPIO_BIT1 BIT(20)
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_AFE_CTRL4 (Offset 0x0078) */
-
-#define BIT_SHIFT_XTAL_LDO 20
-#define BIT_MASK_XTAL_LDO 0x7
-#define BIT_XTAL_LDO(x) (((x) & BIT_MASK_XTAL_LDO) << BIT_SHIFT_XTAL_LDO)
-#define BIT_GET_XTAL_LDO(x) (((x) >> BIT_SHIFT_XTAL_LDO) & BIT_MASK_XTAL_LDO)
-
+#define BIT_SHIFT_XTAL_LDO 20
+#define BIT_MASK_XTAL_LDO 0x7
+#define BIT_XTAL_LDO(x) (((x) & BIT_MASK_XTAL_LDO) << BIT_SHIFT_XTAL_LDO)
+#define BITS_XTAL_LDO (BIT_MASK_XTAL_LDO << BIT_SHIFT_XTAL_LDO)
+#define BIT_CLEAR_XTAL_LDO(x) ((x) & (~BITS_XTAL_LDO))
+#define BIT_GET_XTAL_LDO(x) (((x) >> BIT_SHIFT_XTAL_LDO) & BIT_MASK_XTAL_LDO)
+#define BIT_SET_XTAL_LDO(x, v) (BIT_CLEAR_XTAL_LDO(x) | BIT_XTAL_LDO(v))
#endif
-
#if (HALMAC_8192E_SUPPORT)
-
/* 2 REG_AFE_CTRL4 (Offset 0x0078) */
-#define BIT_XTAL_DRV_AGPIO_BIT0 BIT(19)
+#define BIT_XTAL_DRV_AGPIO_BIT0 BIT(19)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_AFE_CTRL4 (Offset 0x0078) */
-#define BIT_XTAL_GRF2 BIT(18)
-#define BIT_REG_REF_SEL BIT(17)
-#define BIT_REG_320_SEL BIT(16)
+#define BIT_XTAL_GRF2 BIT(18)
+#define BIT_REG_REF_SEL BIT(17)
+#define BIT_REG_320_SEL BIT(16)
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_AFE_CTRL4 (Offset 0x0078) */
-#define BIT_ADC_CK_SYNC_EN BIT(16)
+#define BIT_ADC_CK_SYNC_EN BIT(16)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_AFE_CTRL4 (Offset 0x0078) */
-#define BIT_EN_SYM BIT(15)
-
-#define BIT_SHIFT_IOFFSET 10
-#define BIT_MASK_IOFFSET 0x1f
-#define BIT_IOFFSET(x) (((x) & BIT_MASK_IOFFSET) << BIT_SHIFT_IOFFSET)
-#define BIT_GET_IOFFSET(x) (((x) >> BIT_SHIFT_IOFFSET) & BIT_MASK_IOFFSET)
+#define BIT_EN_SYM BIT(15)
+#define BIT_SHIFT_IOFFSET 10
+#define BIT_MASK_IOFFSET 0x1f
+#define BIT_IOFFSET(x) (((x) & BIT_MASK_IOFFSET) << BIT_SHIFT_IOFFSET)
+#define BITS_IOFFSET (BIT_MASK_IOFFSET << BIT_SHIFT_IOFFSET)
+#define BIT_CLEAR_IOFFSET(x) ((x) & (~BITS_IOFFSET))
+#define BIT_GET_IOFFSET(x) (((x) >> BIT_SHIFT_IOFFSET) & BIT_MASK_IOFFSET)
+#define BIT_SET_IOFFSET(x, v) (BIT_CLEAR_IOFFSET(x) | BIT_IOFFSET(v))
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_AFE_CTRL4 (Offset 0x0078) */
+#define BIT_RF2_SDMRSTB BIT(10)
-/* 2 REG_AFE_XTAL_CTRL_EXT (Offset 0x0078) */
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define BIT_SHIFT_F0F_12_TO_0 10
-#define BIT_MASK_F0F_12_TO_0 0x1fff
-#define BIT_F0F_12_TO_0(x) (((x) & BIT_MASK_F0F_12_TO_0) << BIT_SHIFT_F0F_12_TO_0)
-#define BIT_GET_F0F_12_TO_0(x) (((x) >> BIT_SHIFT_F0F_12_TO_0) & BIT_MASK_F0F_12_TO_0)
+/* 2 REG_AFE_XTAL_CTRL_EXT (Offset 0x0078) */
+#define BIT_SHIFT_F0F_12_TO_0 10
+#define BIT_MASK_F0F_12_TO_0 0x1fff
+#define BIT_F0F_12_TO_0(x) \
+ (((x) & BIT_MASK_F0F_12_TO_0) << BIT_SHIFT_F0F_12_TO_0)
+#define BITS_F0F_12_TO_0 (BIT_MASK_F0F_12_TO_0 << BIT_SHIFT_F0F_12_TO_0)
+#define BIT_CLEAR_F0F_12_TO_0(x) ((x) & (~BITS_F0F_12_TO_0))
+#define BIT_GET_F0F_12_TO_0(x) \
+ (((x) >> BIT_SHIFT_F0F_12_TO_0) & BIT_MASK_F0F_12_TO_0)
+#define BIT_SET_F0F_12_TO_0(x, v) \
+ (BIT_CLEAR_F0F_12_TO_0(x) | BIT_F0F_12_TO_0(v))
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8198F_SUPPORT)
/* 2 REG_AFE_CTRL4 (Offset 0x0078) */
+#define BIT_RF2_RSTB BIT(9)
-#define BIT_SHIFT_APLL_FREF_SEL_BIT_2_TO_1 8
-#define BIT_MASK_APLL_FREF_SEL_BIT_2_TO_1 0x3
-#define BIT_APLL_FREF_SEL_BIT_2_TO_1(x) (((x) & BIT_MASK_APLL_FREF_SEL_BIT_2_TO_1) << BIT_SHIFT_APLL_FREF_SEL_BIT_2_TO_1)
-#define BIT_GET_APLL_FREF_SEL_BIT_2_TO_1(x) (((x) >> BIT_SHIFT_APLL_FREF_SEL_BIT_2_TO_1) & BIT_MASK_APLL_FREF_SEL_BIT_2_TO_1)
+#endif
-#define BIT_APLL_FREF_SEL_BIT3 BIT(7)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_APLL_LDO_V12ADJ 5
-#define BIT_MASK_APLL_LDO_V12ADJ 0x3
-#define BIT_APLL_LDO_V12ADJ(x) (((x) & BIT_MASK_APLL_LDO_V12ADJ) << BIT_SHIFT_APLL_LDO_V12ADJ)
-#define BIT_GET_APLL_LDO_V12ADJ(x) (((x) >> BIT_SHIFT_APLL_LDO_V12ADJ) & BIT_MASK_APLL_LDO_V12ADJ)
+/* 2 REG_AFE_CTRL4 (Offset 0x0078) */
-#define BIT_APLL_160_GATEB BIT(4)
+#define BIT_SHIFT_APLL_FREF_SEL_BIT_2_TO_1 8
+#define BIT_MASK_APLL_FREF_SEL_BIT_2_TO_1 0x3
+#define BIT_APLL_FREF_SEL_BIT_2_TO_1(x) \
+ (((x) & BIT_MASK_APLL_FREF_SEL_BIT_2_TO_1) \
+ << BIT_SHIFT_APLL_FREF_SEL_BIT_2_TO_1)
+#define BITS_APLL_FREF_SEL_BIT_2_TO_1 \
+ (BIT_MASK_APLL_FREF_SEL_BIT_2_TO_1 \
+ << BIT_SHIFT_APLL_FREF_SEL_BIT_2_TO_1)
+#define BIT_CLEAR_APLL_FREF_SEL_BIT_2_TO_1(x) \
+ ((x) & (~BITS_APLL_FREF_SEL_BIT_2_TO_1))
+#define BIT_GET_APLL_FREF_SEL_BIT_2_TO_1(x) \
+ (((x) >> BIT_SHIFT_APLL_FREF_SEL_BIT_2_TO_1) & \
+ BIT_MASK_APLL_FREF_SEL_BIT_2_TO_1)
+#define BIT_SET_APLL_FREF_SEL_BIT_2_TO_1(x, v) \
+ (BIT_CLEAR_APLL_FREF_SEL_BIT_2_TO_1(x) | \
+ BIT_APLL_FREF_SEL_BIT_2_TO_1(v))
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
-
-/* 2 REG_AFE_XTAL_CTRL_EXT (Offset 0x0078) */
-
-
-#define BIT_SHIFT_DIVN_5_TO_0 4
-#define BIT_MASK_DIVN_5_TO_0 0x3f
-#define BIT_DIVN_5_TO_0(x) (((x) & BIT_MASK_DIVN_5_TO_0) << BIT_SHIFT_DIVN_5_TO_0)
-#define BIT_GET_DIVN_5_TO_0(x) (((x) >> BIT_SHIFT_DIVN_5_TO_0) & BIT_MASK_DIVN_5_TO_0)
+/* 2 REG_AFE_CTRL4 (Offset 0x0078) */
+#define BIT_RF2_EN BIT(8)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_AFE_CTRL4 (Offset 0x0078) */
-#define BIT_AFE_DUMMY BIT(3)
-#define BIT_REG_IDOUBLE BIT(2)
-#define BIT_REG_VCO_BIAS_BIT0 BIT(1)
-#define BIT_REG_VCO_BIAS_BIT1 BIT(0)
+#define BIT_APLL_FREF_SEL_BIT3 BIT(7)
-#endif
+#define BIT_SHIFT_APLL_LDO_V12ADJ 5
+#define BIT_MASK_APLL_LDO_V12ADJ 0x3
+#define BIT_APLL_LDO_V12ADJ(x) \
+ (((x) & BIT_MASK_APLL_LDO_V12ADJ) << BIT_SHIFT_APLL_LDO_V12ADJ)
+#define BITS_APLL_LDO_V12ADJ \
+ (BIT_MASK_APLL_LDO_V12ADJ << BIT_SHIFT_APLL_LDO_V12ADJ)
+#define BIT_CLEAR_APLL_LDO_V12ADJ(x) ((x) & (~BITS_APLL_LDO_V12ADJ))
+#define BIT_GET_APLL_LDO_V12ADJ(x) \
+ (((x) >> BIT_SHIFT_APLL_LDO_V12ADJ) & BIT_MASK_APLL_LDO_V12ADJ)
+#define BIT_SET_APLL_LDO_V12ADJ(x, v) \
+ (BIT_CLEAR_APLL_LDO_V12ADJ(x) | BIT_APLL_LDO_V12ADJ(v))
+#define BIT_APLL_160_GATEB BIT(4)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
/* 2 REG_AFE_XTAL_CTRL_EXT (Offset 0x0078) */
+#define BIT_SHIFT_DIVN_5_TO_0 4
+#define BIT_MASK_DIVN_5_TO_0 0x3f
+#define BIT_DIVN_5_TO_0(x) \
+ (((x) & BIT_MASK_DIVN_5_TO_0) << BIT_SHIFT_DIVN_5_TO_0)
+#define BITS_DIVN_5_TO_0 (BIT_MASK_DIVN_5_TO_0 << BIT_SHIFT_DIVN_5_TO_0)
+#define BIT_CLEAR_DIVN_5_TO_0(x) ((x) & (~BITS_DIVN_5_TO_0))
+#define BIT_GET_DIVN_5_TO_0(x) \
+ (((x) >> BIT_SHIFT_DIVN_5_TO_0) & BIT_MASK_DIVN_5_TO_0)
+#define BIT_SET_DIVN_5_TO_0(x, v) \
+ (BIT_CLEAR_DIVN_5_TO_0(x) | BIT_DIVN_5_TO_0(v))
-#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_3_TO_0 0
-#define BIT_MASK_BB_DBG_SEL_AFE_SDM_3_TO_0 0xf
-#define BIT_BB_DBG_SEL_AFE_SDM_3_TO_0(x) (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_3_TO_0) << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_3_TO_0)
-#define BIT_GET_BB_DBG_SEL_AFE_SDM_3_TO_0(x) (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_3_TO_0) & BIT_MASK_BB_DBG_SEL_AFE_SDM_3_TO_0)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
+/* 2 REG_AFE_CTRL4 (Offset 0x0078) */
-#define BIT_REF_FREF_EDGE BIT(29)
-#define BIT_REG_VREF_SEL_V1 BIT(28)
+#define BIT_AFE_DUMMY BIT(3)
+#define BIT_REG_IDOUBLE BIT(2)
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_AFE_CTRL4 (Offset 0x0078) */
+#define BIT_RF3_SDMRSTB BIT(2)
-/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_AFE_CTRL4 (Offset 0x0078) */
-#define BIT_ZCD_HW_AUTO_EN BIT(27)
-#define BIT_ZCD_REGSEL BIT(26)
+#define BIT_REG_VCO_BIAS_BIT0 BIT(1)
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_AFE_CTRL4 (Offset 0x0078) */
+#define BIT_RF3_RSTB BIT(1)
-/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_REG_CP_OFFSET_4_TO_0 23
-#define BIT_MASK_REG_CP_OFFSET_4_TO_0 0x1f
-#define BIT_REG_CP_OFFSET_4_TO_0(x) (((x) & BIT_MASK_REG_CP_OFFSET_4_TO_0) << BIT_SHIFT_REG_CP_OFFSET_4_TO_0)
-#define BIT_GET_REG_CP_OFFSET_4_TO_0(x) (((x) >> BIT_SHIFT_REG_CP_OFFSET_4_TO_0) & BIT_MASK_REG_CP_OFFSET_4_TO_0)
+/* 2 REG_AFE_CTRL4 (Offset 0x0078) */
+#define BIT_REG_VCO_BIAS_BIT1 BIT(0)
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_AFE_CTRL4 (Offset 0x0078) */
+#define BIT_RF3_EN BIT(0)
-/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define BIT_SHIFT_AUTO_ZCD_IN_CODE 21
-#define BIT_MASK_AUTO_ZCD_IN_CODE 0x1f
-#define BIT_AUTO_ZCD_IN_CODE(x) (((x) & BIT_MASK_AUTO_ZCD_IN_CODE) << BIT_SHIFT_AUTO_ZCD_IN_CODE)
-#define BIT_GET_AUTO_ZCD_IN_CODE(x) (((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE) & BIT_MASK_AUTO_ZCD_IN_CODE)
+/* 2 REG_AFE_XTAL_CTRL_EXT (Offset 0x0078) */
+#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_3_TO_0 0
+#define BIT_MASK_BB_DBG_SEL_AFE_SDM_3_TO_0 0xf
+#define BIT_BB_DBG_SEL_AFE_SDM_3_TO_0(x) \
+ (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_3_TO_0) \
+ << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_3_TO_0)
+#define BITS_BB_DBG_SEL_AFE_SDM_3_TO_0 \
+ (BIT_MASK_BB_DBG_SEL_AFE_SDM_3_TO_0 \
+ << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_3_TO_0)
+#define BIT_CLEAR_BB_DBG_SEL_AFE_SDM_3_TO_0(x) \
+ ((x) & (~BITS_BB_DBG_SEL_AFE_SDM_3_TO_0))
+#define BIT_GET_BB_DBG_SEL_AFE_SDM_3_TO_0(x) \
+ (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_3_TO_0) & \
+ BIT_MASK_BB_DBG_SEL_AFE_SDM_3_TO_0)
+#define BIT_SET_BB_DBG_SEL_AFE_SDM_3_TO_0(x, v) \
+ (BIT_CLEAR_BB_DBG_SEL_AFE_SDM_3_TO_0(x) | \
+ BIT_BB_DBG_SEL_AFE_SDM_3_TO_0(v))
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
+#define BIT_EXT_SWR_CTRL_EN BIT(31)
-/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define BIT_SHIFT_REG_RS_SET_2_TO_0 20
-#define BIT_MASK_REG_RS_SET_2_TO_0 0x7
-#define BIT_REG_RS_SET_2_TO_0(x) (((x) & BIT_MASK_REG_RS_SET_2_TO_0) << BIT_SHIFT_REG_RS_SET_2_TO_0)
-#define BIT_GET_REG_RS_SET_2_TO_0(x) (((x) >> BIT_SHIFT_REG_RS_SET_2_TO_0) & BIT_MASK_REG_RS_SET_2_TO_0)
+/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
+#define BIT_REF_FREF_EDGE BIT(29)
+#define BIT_REG_VREF_SEL_V1 BIT(28)
-#define BIT_SHIFT_REG_CS_SET_1_TO_0 18
-#define BIT_MASK_REG_CS_SET_1_TO_0 0x3
-#define BIT_REG_CS_SET_1_TO_0(x) (((x) & BIT_MASK_REG_CS_SET_1_TO_0) << BIT_SHIFT_REG_CS_SET_1_TO_0)
-#define BIT_GET_REG_CS_SET_1_TO_0(x) (((x) >> BIT_SHIFT_REG_CS_SET_1_TO_0) & BIT_MASK_REG_CS_SET_1_TO_0)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_REG_CP_SET_1_TO_0 16
-#define BIT_MASK_REG_CP_SET_1_TO_0 0x3
-#define BIT_REG_CP_SET_1_TO_0(x) (((x) & BIT_MASK_REG_CP_SET_1_TO_0) << BIT_SHIFT_REG_CP_SET_1_TO_0)
-#define BIT_GET_REG_CP_SET_1_TO_0(x) (((x) >> BIT_SHIFT_REG_CP_SET_1_TO_0) & BIT_MASK_REG_CP_SET_1_TO_0)
+/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
+#define BIT_ZCD_HW_AUTO_EN BIT(27)
+#define BIT_ZCD_REGSEL BIT(26)
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
+#define BIT_SHIFT_REG_CP_OFFSET_4_TO_0 23
+#define BIT_MASK_REG_CP_OFFSET_4_TO_0 0x1f
+#define BIT_REG_CP_OFFSET_4_TO_0(x) \
+ (((x) & BIT_MASK_REG_CP_OFFSET_4_TO_0) \
+ << BIT_SHIFT_REG_CP_OFFSET_4_TO_0)
+#define BITS_REG_CP_OFFSET_4_TO_0 \
+ (BIT_MASK_REG_CP_OFFSET_4_TO_0 << BIT_SHIFT_REG_CP_OFFSET_4_TO_0)
+#define BIT_CLEAR_REG_CP_OFFSET_4_TO_0(x) ((x) & (~BITS_REG_CP_OFFSET_4_TO_0))
+#define BIT_GET_REG_CP_OFFSET_4_TO_0(x) \
+ (((x) >> BIT_SHIFT_REG_CP_OFFSET_4_TO_0) & \
+ BIT_MASK_REG_CP_OFFSET_4_TO_0)
+#define BIT_SET_REG_CP_OFFSET_4_TO_0(x, v) \
+ (BIT_CLEAR_REG_CP_OFFSET_4_TO_0(x) | BIT_REG_CP_OFFSET_4_TO_0(v))
-/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_ZCD_CODE_IN_L 16
-#define BIT_MASK_ZCD_CODE_IN_L 0x1f
-#define BIT_ZCD_CODE_IN_L(x) (((x) & BIT_MASK_ZCD_CODE_IN_L) << BIT_SHIFT_ZCD_CODE_IN_L)
-#define BIT_GET_ZCD_CODE_IN_L(x) (((x) >> BIT_SHIFT_ZCD_CODE_IN_L) & BIT_MASK_ZCD_CODE_IN_L)
+/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
+#define BIT_SHIFT_AUTO_ZCD_IN_CODE 21
+#define BIT_MASK_AUTO_ZCD_IN_CODE 0x1f
+#define BIT_AUTO_ZCD_IN_CODE(x) \
+ (((x) & BIT_MASK_AUTO_ZCD_IN_CODE) << BIT_SHIFT_AUTO_ZCD_IN_CODE)
+#define BITS_AUTO_ZCD_IN_CODE \
+ (BIT_MASK_AUTO_ZCD_IN_CODE << BIT_SHIFT_AUTO_ZCD_IN_CODE)
+#define BIT_CLEAR_AUTO_ZCD_IN_CODE(x) ((x) & (~BITS_AUTO_ZCD_IN_CODE))
+#define BIT_GET_AUTO_ZCD_IN_CODE(x) \
+ (((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE) & BIT_MASK_AUTO_ZCD_IN_CODE)
+#define BIT_SET_AUTO_ZCD_IN_CODE(x, v) \
+ (BIT_CLEAR_AUTO_ZCD_IN_CODE(x) | BIT_AUTO_ZCD_IN_CODE(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
+
+#define BIT_SHIFT_REG_RS_SET_2_TO_0 20
+#define BIT_MASK_REG_RS_SET_2_TO_0 0x7
+#define BIT_REG_RS_SET_2_TO_0(x) \
+ (((x) & BIT_MASK_REG_RS_SET_2_TO_0) << BIT_SHIFT_REG_RS_SET_2_TO_0)
+#define BITS_REG_RS_SET_2_TO_0 \
+ (BIT_MASK_REG_RS_SET_2_TO_0 << BIT_SHIFT_REG_RS_SET_2_TO_0)
+#define BIT_CLEAR_REG_RS_SET_2_TO_0(x) ((x) & (~BITS_REG_RS_SET_2_TO_0))
+#define BIT_GET_REG_RS_SET_2_TO_0(x) \
+ (((x) >> BIT_SHIFT_REG_RS_SET_2_TO_0) & BIT_MASK_REG_RS_SET_2_TO_0)
+#define BIT_SET_REG_RS_SET_2_TO_0(x, v) \
+ (BIT_CLEAR_REG_RS_SET_2_TO_0(x) | BIT_REG_RS_SET_2_TO_0(v))
+
+#define BIT_SHIFT_REG_CS_SET_1_TO_0 18
+#define BIT_MASK_REG_CS_SET_1_TO_0 0x3
+#define BIT_REG_CS_SET_1_TO_0(x) \
+ (((x) & BIT_MASK_REG_CS_SET_1_TO_0) << BIT_SHIFT_REG_CS_SET_1_TO_0)
+#define BITS_REG_CS_SET_1_TO_0 \
+ (BIT_MASK_REG_CS_SET_1_TO_0 << BIT_SHIFT_REG_CS_SET_1_TO_0)
+#define BIT_CLEAR_REG_CS_SET_1_TO_0(x) ((x) & (~BITS_REG_CS_SET_1_TO_0))
+#define BIT_GET_REG_CS_SET_1_TO_0(x) \
+ (((x) >> BIT_SHIFT_REG_CS_SET_1_TO_0) & BIT_MASK_REG_CS_SET_1_TO_0)
+#define BIT_SET_REG_CS_SET_1_TO_0(x, v) \
+ (BIT_CLEAR_REG_CS_SET_1_TO_0(x) | BIT_REG_CS_SET_1_TO_0(v))
+
+#define BIT_SHIFT_REG_CP_SET_1_TO_0 16
+#define BIT_MASK_REG_CP_SET_1_TO_0 0x3
+#define BIT_REG_CP_SET_1_TO_0(x) \
+ (((x) & BIT_MASK_REG_CP_SET_1_TO_0) << BIT_SHIFT_REG_CP_SET_1_TO_0)
+#define BITS_REG_CP_SET_1_TO_0 \
+ (BIT_MASK_REG_CP_SET_1_TO_0 << BIT_SHIFT_REG_CP_SET_1_TO_0)
+#define BIT_CLEAR_REG_CP_SET_1_TO_0(x) ((x) & (~BITS_REG_CP_SET_1_TO_0))
+#define BIT_GET_REG_CP_SET_1_TO_0(x) \
+ (((x) >> BIT_SHIFT_REG_CP_SET_1_TO_0) & BIT_MASK_REG_CP_SET_1_TO_0)
+#define BIT_SET_REG_CP_SET_1_TO_0(x, v) \
+ (BIT_CLEAR_REG_CP_SET_1_TO_0(x) | BIT_REG_CP_SET_1_TO_0(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
-#define BIT_LPFEN BIT(15)
+#define BIT_SHIFT_ZCD_CODE_IN_L 16
+#define BIT_MASK_ZCD_CODE_IN_L 0x1f
+#define BIT_ZCD_CODE_IN_L(x) \
+ (((x) & BIT_MASK_ZCD_CODE_IN_L) << BIT_SHIFT_ZCD_CODE_IN_L)
+#define BITS_ZCD_CODE_IN_L (BIT_MASK_ZCD_CODE_IN_L << BIT_SHIFT_ZCD_CODE_IN_L)
+#define BIT_CLEAR_ZCD_CODE_IN_L(x) ((x) & (~BITS_ZCD_CODE_IN_L))
+#define BIT_GET_ZCD_CODE_IN_L(x) \
+ (((x) >> BIT_SHIFT_ZCD_CODE_IN_L) & BIT_MASK_ZCD_CODE_IN_L)
+#define BIT_SET_ZCD_CODE_IN_L(x, v) \
+ (BIT_CLEAR_ZCD_CODE_IN_L(x) | BIT_ZCD_CODE_IN_L(v))
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
+#define BIT_LPFEN BIT(15)
-/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_LDO_HV5_DUMMY 14
-#define BIT_MASK_LDO_HV5_DUMMY 0x3
-#define BIT_LDO_HV5_DUMMY(x) (((x) & BIT_MASK_LDO_HV5_DUMMY) << BIT_SHIFT_LDO_HV5_DUMMY)
-#define BIT_GET_LDO_HV5_DUMMY(x) (((x) >> BIT_SHIFT_LDO_HV5_DUMMY) & BIT_MASK_LDO_HV5_DUMMY)
+/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
+#define BIT_SHIFT_LDO_HV5_DUMMY 14
+#define BIT_MASK_LDO_HV5_DUMMY 0x3
+#define BIT_LDO_HV5_DUMMY(x) \
+ (((x) & BIT_MASK_LDO_HV5_DUMMY) << BIT_SHIFT_LDO_HV5_DUMMY)
+#define BITS_LDO_HV5_DUMMY (BIT_MASK_LDO_HV5_DUMMY << BIT_SHIFT_LDO_HV5_DUMMY)
+#define BIT_CLEAR_LDO_HV5_DUMMY(x) ((x) & (~BITS_LDO_HV5_DUMMY))
+#define BIT_GET_LDO_HV5_DUMMY(x) \
+ (((x) >> BIT_SHIFT_LDO_HV5_DUMMY) & BIT_MASK_LDO_HV5_DUMMY)
+#define BIT_SET_LDO_HV5_DUMMY(x, v) \
+ (BIT_CLEAR_LDO_HV5_DUMMY(x) | BIT_LDO_HV5_DUMMY(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
-#define BIT_REG_DOGENB BIT(14)
-#define BIT_REG_TEST_EN BIT(13)
+#define BIT_REG_DOGENB BIT(14)
+#define BIT_REG_TEST_EN BIT(13)
#endif
-
#if (HALMAC_8192E_SUPPORT)
-
/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
-
-#define BIT_SHIFT_REG_VTUNE33 12
-#define BIT_MASK_REG_VTUNE33 0x3
-#define BIT_REG_VTUNE33(x) (((x) & BIT_MASK_REG_VTUNE33) << BIT_SHIFT_REG_VTUNE33)
-#define BIT_GET_REG_VTUNE33(x) (((x) >> BIT_SHIFT_REG_VTUNE33) & BIT_MASK_REG_VTUNE33)
-
+#define BIT_SHIFT_REG_VTUNE33 12
+#define BIT_MASK_REG_VTUNE33 0x3
+#define BIT_REG_VTUNE33(x) \
+ (((x) & BIT_MASK_REG_VTUNE33) << BIT_SHIFT_REG_VTUNE33)
+#define BITS_REG_VTUNE33 (BIT_MASK_REG_VTUNE33 << BIT_SHIFT_REG_VTUNE33)
+#define BIT_CLEAR_REG_VTUNE33(x) ((x) & (~BITS_REG_VTUNE33))
+#define BIT_GET_REG_VTUNE33(x) \
+ (((x) >> BIT_SHIFT_REG_VTUNE33) & BIT_MASK_REG_VTUNE33)
+#define BIT_SET_REG_VTUNE33(x, v) \
+ (BIT_CLEAR_REG_VTUNE33(x) | BIT_REG_VTUNE33(v))
#endif
-
#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
-
-#define BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1 12
-#define BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1 0x3
-#define BIT_REG_VTUNE33_BIT0_TO_BIT1(x) (((x) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1) << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1)
-#define BIT_GET_REG_VTUNE33_BIT0_TO_BIT1(x) (((x) >> BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1)
-
+#define BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1 12
+#define BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1 0x3
+#define BIT_REG_VTUNE33_BIT0_TO_BIT1(x) \
+ (((x) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1) \
+ << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1)
+#define BITS_REG_VTUNE33_BIT0_TO_BIT1 \
+ (BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1 \
+ << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1)
+#define BIT_CLEAR_REG_VTUNE33_BIT0_TO_BIT1(x) \
+ ((x) & (~BITS_REG_VTUNE33_BIT0_TO_BIT1))
+#define BIT_GET_REG_VTUNE33_BIT0_TO_BIT1(x) \
+ (((x) >> BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1) & \
+ BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1)
+#define BIT_SET_REG_VTUNE33_BIT0_TO_BIT1(x, v) \
+ (BIT_CLEAR_REG_VTUNE33_BIT0_TO_BIT1(x) | \
+ BIT_REG_VTUNE33_BIT0_TO_BIT1(v))
#endif
-
#if (HALMAC_8192E_SUPPORT)
-
/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
-
-#define BIT_SHIFT_REG_STANDBY33 10
-#define BIT_MASK_REG_STANDBY33 0x3
-#define BIT_REG_STANDBY33(x) (((x) & BIT_MASK_REG_STANDBY33) << BIT_SHIFT_REG_STANDBY33)
-#define BIT_GET_REG_STANDBY33(x) (((x) >> BIT_SHIFT_REG_STANDBY33) & BIT_MASK_REG_STANDBY33)
-
+#define BIT_SHIFT_REG_STANDBY33 10
+#define BIT_MASK_REG_STANDBY33 0x3
+#define BIT_REG_STANDBY33(x) \
+ (((x) & BIT_MASK_REG_STANDBY33) << BIT_SHIFT_REG_STANDBY33)
+#define BITS_REG_STANDBY33 (BIT_MASK_REG_STANDBY33 << BIT_SHIFT_REG_STANDBY33)
+#define BIT_CLEAR_REG_STANDBY33(x) ((x) & (~BITS_REG_STANDBY33))
+#define BIT_GET_REG_STANDBY33(x) \
+ (((x) >> BIT_SHIFT_REG_STANDBY33) & BIT_MASK_REG_STANDBY33)
+#define BIT_SET_REG_STANDBY33(x, v) \
+ (BIT_CLEAR_REG_STANDBY33(x) | BIT_REG_STANDBY33(v))
#endif
-
#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
-
-#define BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1 10
-#define BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1 0x3
-#define BIT_REG_STANDBY33_BIT0_TO_BIT1(x) (((x) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1) << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1)
-#define BIT_GET_REG_STANDBY33_BIT0_TO_BIT1(x) (((x) >> BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1)
-
+#define BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1 10
+#define BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1 0x3
+#define BIT_REG_STANDBY33_BIT0_TO_BIT1(x) \
+ (((x) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1) \
+ << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1)
+#define BITS_REG_STANDBY33_BIT0_TO_BIT1 \
+ (BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1 \
+ << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1)
+#define BIT_CLEAR_REG_STANDBY33_BIT0_TO_BIT1(x) \
+ ((x) & (~BITS_REG_STANDBY33_BIT0_TO_BIT1))
+#define BIT_GET_REG_STANDBY33_BIT0_TO_BIT1(x) \
+ (((x) >> BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1) & \
+ BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1)
+#define BIT_SET_REG_STANDBY33_BIT0_TO_BIT1(x, v) \
+ (BIT_CLEAR_REG_STANDBY33_BIT0_TO_BIT1(x) | \
+ BIT_REG_STANDBY33_BIT0_TO_BIT1(v))
#endif
-
#if (HALMAC_8192E_SUPPORT)
-
/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
-
-#define BIT_SHIFT_REG_LOAD33 8
-#define BIT_MASK_REG_LOAD33 0x3
-#define BIT_REG_LOAD33(x) (((x) & BIT_MASK_REG_LOAD33) << BIT_SHIFT_REG_LOAD33)
-#define BIT_GET_REG_LOAD33(x) (((x) >> BIT_SHIFT_REG_LOAD33) & BIT_MASK_REG_LOAD33)
-
+#define BIT_SHIFT_REG_LOAD33 8
+#define BIT_MASK_REG_LOAD33 0x3
+#define BIT_REG_LOAD33(x) (((x) & BIT_MASK_REG_LOAD33) << BIT_SHIFT_REG_LOAD33)
+#define BITS_REG_LOAD33 (BIT_MASK_REG_LOAD33 << BIT_SHIFT_REG_LOAD33)
+#define BIT_CLEAR_REG_LOAD33(x) ((x) & (~BITS_REG_LOAD33))
+#define BIT_GET_REG_LOAD33(x) \
+ (((x) >> BIT_SHIFT_REG_LOAD33) & BIT_MASK_REG_LOAD33)
+#define BIT_SET_REG_LOAD33(x, v) (BIT_CLEAR_REG_LOAD33(x) | BIT_REG_LOAD33(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
-
-#define BIT_SHIFT_REG_DIV_SEL 8
-#define BIT_MASK_REG_DIV_SEL 0x1f
-#define BIT_REG_DIV_SEL(x) (((x) & BIT_MASK_REG_DIV_SEL) << BIT_SHIFT_REG_DIV_SEL)
-#define BIT_GET_REG_DIV_SEL(x) (((x) >> BIT_SHIFT_REG_DIV_SEL) & BIT_MASK_REG_DIV_SEL)
-
+#define BIT_SHIFT_REG_DIV_SEL 8
+#define BIT_MASK_REG_DIV_SEL 0x1f
+#define BIT_REG_DIV_SEL(x) \
+ (((x) & BIT_MASK_REG_DIV_SEL) << BIT_SHIFT_REG_DIV_SEL)
+#define BITS_REG_DIV_SEL (BIT_MASK_REG_DIV_SEL << BIT_SHIFT_REG_DIV_SEL)
+#define BIT_CLEAR_REG_DIV_SEL(x) ((x) & (~BITS_REG_DIV_SEL))
+#define BIT_GET_REG_DIV_SEL(x) \
+ (((x) >> BIT_SHIFT_REG_DIV_SEL) & BIT_MASK_REG_DIV_SEL)
+#define BIT_SET_REG_DIV_SEL(x, v) \
+ (BIT_CLEAR_REG_DIV_SEL(x) | BIT_REG_DIV_SEL(v))
#endif
-
#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
-
-#define BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1 8
-#define BIT_MASK_REG_LOAD33_BIT0_TO_BIT1 0x3
-#define BIT_REG_LOAD33_BIT0_TO_BIT1(x) (((x) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1) << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1)
-#define BIT_GET_REG_LOAD33_BIT0_TO_BIT1(x) (((x) >> BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1)
-
+#define BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1 8
+#define BIT_MASK_REG_LOAD33_BIT0_TO_BIT1 0x3
+#define BIT_REG_LOAD33_BIT0_TO_BIT1(x) \
+ (((x) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1) \
+ << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1)
+#define BITS_REG_LOAD33_BIT0_TO_BIT1 \
+ (BIT_MASK_REG_LOAD33_BIT0_TO_BIT1 << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1)
+#define BIT_CLEAR_REG_LOAD33_BIT0_TO_BIT1(x) \
+ ((x) & (~BITS_REG_LOAD33_BIT0_TO_BIT1))
+#define BIT_GET_REG_LOAD33_BIT0_TO_BIT1(x) \
+ (((x) >> BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1) & \
+ BIT_MASK_REG_LOAD33_BIT0_TO_BIT1)
+#define BIT_SET_REG_LOAD33_BIT0_TO_BIT1(x, v) \
+ (BIT_CLEAR_REG_LOAD33_BIT0_TO_BIT1(x) | BIT_REG_LOAD33_BIT0_TO_BIT1(v))
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
-#define BIT_REG_BYPASS_L BIT(7)
+#define BIT_REG_BYPASS_L BIT(7)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
-#define BIT_EN_CK200M BIT(7)
+#define BIT_EN_CK200M BIT(7)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
-#define BIT_REG_LDOF_L BIT(6)
+#define BIT_REG_LDOF_L BIT(6)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
-#define BIT_REG_OCPS_L BIT(5)
+#define BIT_REG_OCPS_L BIT(5)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
-
-#define BIT_SHIFT_REG_KVCO_200M_1_TO_0 5
-#define BIT_MASK_REG_KVCO_200M_1_TO_0 0x3
-#define BIT_REG_KVCO_200M_1_TO_0(x) (((x) & BIT_MASK_REG_KVCO_200M_1_TO_0) << BIT_SHIFT_REG_KVCO_200M_1_TO_0)
-#define BIT_GET_REG_KVCO_200M_1_TO_0(x) (((x) >> BIT_SHIFT_REG_KVCO_200M_1_TO_0) & BIT_MASK_REG_KVCO_200M_1_TO_0)
-
+#define BIT_SHIFT_REG_KVCO_200M_1_TO_0 5
+#define BIT_MASK_REG_KVCO_200M_1_TO_0 0x3
+#define BIT_REG_KVCO_200M_1_TO_0(x) \
+ (((x) & BIT_MASK_REG_KVCO_200M_1_TO_0) \
+ << BIT_SHIFT_REG_KVCO_200M_1_TO_0)
+#define BITS_REG_KVCO_200M_1_TO_0 \
+ (BIT_MASK_REG_KVCO_200M_1_TO_0 << BIT_SHIFT_REG_KVCO_200M_1_TO_0)
+#define BIT_CLEAR_REG_KVCO_200M_1_TO_0(x) ((x) & (~BITS_REG_KVCO_200M_1_TO_0))
+#define BIT_GET_REG_KVCO_200M_1_TO_0(x) \
+ (((x) >> BIT_SHIFT_REG_KVCO_200M_1_TO_0) & \
+ BIT_MASK_REG_KVCO_200M_1_TO_0)
+#define BIT_SET_REG_KVCO_200M_1_TO_0(x, v) \
+ (BIT_CLEAR_REG_KVCO_200M_1_TO_0(x) | BIT_REG_KVCO_200M_1_TO_0(v))
#endif
-
#if (HALMAC_8822B_SUPPORT)
-
/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
-#define BIT_REG_TYPE_L_V1 BIT(5)
+#define BIT_REG_TYPE_L_V1 BIT(5)
#endif
-
#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
-#define BIT_ARENB_L BIT(3)
+#define BIT_ARENB_L BIT(3)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
-
-#define BIT_SHIFT_REG_CP_BIAS_200M_2_TO_0 2
-#define BIT_MASK_REG_CP_BIAS_200M_2_TO_0 0x7
-#define BIT_REG_CP_BIAS_200M_2_TO_0(x) (((x) & BIT_MASK_REG_CP_BIAS_200M_2_TO_0) << BIT_SHIFT_REG_CP_BIAS_200M_2_TO_0)
-#define BIT_GET_REG_CP_BIAS_200M_2_TO_0(x) (((x) >> BIT_SHIFT_REG_CP_BIAS_200M_2_TO_0) & BIT_MASK_REG_CP_BIAS_200M_2_TO_0)
-
+#define BIT_SHIFT_REG_CP_BIAS_200M_2_TO_0 2
+#define BIT_MASK_REG_CP_BIAS_200M_2_TO_0 0x7
+#define BIT_REG_CP_BIAS_200M_2_TO_0(x) \
+ (((x) & BIT_MASK_REG_CP_BIAS_200M_2_TO_0) \
+ << BIT_SHIFT_REG_CP_BIAS_200M_2_TO_0)
+#define BITS_REG_CP_BIAS_200M_2_TO_0 \
+ (BIT_MASK_REG_CP_BIAS_200M_2_TO_0 << BIT_SHIFT_REG_CP_BIAS_200M_2_TO_0)
+#define BIT_CLEAR_REG_CP_BIAS_200M_2_TO_0(x) \
+ ((x) & (~BITS_REG_CP_BIAS_200M_2_TO_0))
+#define BIT_GET_REG_CP_BIAS_200M_2_TO_0(x) \
+ (((x) >> BIT_SHIFT_REG_CP_BIAS_200M_2_TO_0) & \
+ BIT_MASK_REG_CP_BIAS_200M_2_TO_0)
+#define BIT_SET_REG_CP_BIAS_200M_2_TO_0(x, v) \
+ (BIT_CLEAR_REG_CP_BIAS_200M_2_TO_0(x) | BIT_REG_CP_BIAS_200M_2_TO_0(v))
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
-
-#define BIT_SHIFT_CFC_L_BIT_1_TO_0 1
-#define BIT_MASK_CFC_L_BIT_1_TO_0 0x3
-#define BIT_CFC_L_BIT_1_TO_0(x) (((x) & BIT_MASK_CFC_L_BIT_1_TO_0) << BIT_SHIFT_CFC_L_BIT_1_TO_0)
-#define BIT_GET_CFC_L_BIT_1_TO_0(x) (((x) >> BIT_SHIFT_CFC_L_BIT_1_TO_0) & BIT_MASK_CFC_L_BIT_1_TO_0)
-
+#define BIT_SHIFT_CFC_L_BIT_1_TO_0 1
+#define BIT_MASK_CFC_L_BIT_1_TO_0 0x3
+#define BIT_CFC_L_BIT_1_TO_0(x) \
+ (((x) & BIT_MASK_CFC_L_BIT_1_TO_0) << BIT_SHIFT_CFC_L_BIT_1_TO_0)
+#define BITS_CFC_L_BIT_1_TO_0 \
+ (BIT_MASK_CFC_L_BIT_1_TO_0 << BIT_SHIFT_CFC_L_BIT_1_TO_0)
+#define BIT_CLEAR_CFC_L_BIT_1_TO_0(x) ((x) & (~BITS_CFC_L_BIT_1_TO_0))
+#define BIT_GET_CFC_L_BIT_1_TO_0(x) \
+ (((x) >> BIT_SHIFT_CFC_L_BIT_1_TO_0) & BIT_MASK_CFC_L_BIT_1_TO_0)
+#define BIT_SET_CFC_L_BIT_1_TO_0(x, v) \
+ (BIT_CLEAR_CFC_L_BIT_1_TO_0(x) | BIT_CFC_L_BIT_1_TO_0(v))
#endif
-
#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
-
-#define BIT_SHIFT_CFC_L 1
-#define BIT_MASK_CFC_L 0x3
-#define BIT_CFC_L(x) (((x) & BIT_MASK_CFC_L) << BIT_SHIFT_CFC_L)
-#define BIT_GET_CFC_L(x) (((x) >> BIT_SHIFT_CFC_L) & BIT_MASK_CFC_L)
-
+#define BIT_SHIFT_CFC_L 1
+#define BIT_MASK_CFC_L 0x3
+#define BIT_CFC_L(x) (((x) & BIT_MASK_CFC_L) << BIT_SHIFT_CFC_L)
+#define BITS_CFC_L (BIT_MASK_CFC_L << BIT_SHIFT_CFC_L)
+#define BIT_CLEAR_CFC_L(x) ((x) & (~BITS_CFC_L))
+#define BIT_GET_CFC_L(x) (((x) >> BIT_SHIFT_CFC_L) & BIT_MASK_CFC_L)
+#define BIT_SET_CFC_L(x, v) (BIT_CLEAR_CFC_L(x) | BIT_CFC_L(v))
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
-#define BIT_REG_TYPE_L BIT(0)
+#define BIT_REG_TYPE_L BIT(0)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
-#define BIT_XCK_OUT_EN BIT(0)
+#define BIT_XCK_OUT_EN BIT(0)
#endif
-
#if (HALMAC_8822B_SUPPORT)
-
/* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */
-#define BIT_REG_OCPS_L_V1 BIT(0)
+#define BIT_REG_OCPS_L_V1 BIT(0)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_MCUFW_CTRL (Offset 0x0080) */
-#define BIT_ANA_PORT_EN BIT(22)
-#define BIT_MAC_PORT_EN BIT(21)
-#define BIT_BOOT_FSPI_EN BIT(20)
-#define BIT_FW_INIT_RDY BIT(15)
-#define BIT_FW_DW_RDY BIT(14)
+#define BIT_ANA_PORT_EN BIT(22)
+#define BIT_MAC_PORT_EN BIT(21)
+#define BIT_BOOT_FSPI_EN BIT(20)
+#define BIT_FW_INIT_RDY BIT(15)
+#define BIT_FW_DW_RDY BIT(14)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_8051FW_CTRL (Offset 0x0080) */
-#define BIT_FWDL_RSVDPAGE_RDY BIT(12)
+#define BIT_FWDL_RSVDPAGE_RDY BIT(12)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_MCUFW_CTRL (Offset 0x0080) */
-
-#define BIT_SHIFT_CPU_CLK_SEL 12
-#define BIT_MASK_CPU_CLK_SEL 0x3
-#define BIT_CPU_CLK_SEL(x) (((x) & BIT_MASK_CPU_CLK_SEL) << BIT_SHIFT_CPU_CLK_SEL)
-#define BIT_GET_CPU_CLK_SEL(x) (((x) >> BIT_SHIFT_CPU_CLK_SEL) & BIT_MASK_CPU_CLK_SEL)
-
+#define BIT_SHIFT_CPU_CLK_SEL 12
+#define BIT_MASK_CPU_CLK_SEL 0x3
+#define BIT_CPU_CLK_SEL(x) \
+ (((x) & BIT_MASK_CPU_CLK_SEL) << BIT_SHIFT_CPU_CLK_SEL)
+#define BITS_CPU_CLK_SEL (BIT_MASK_CPU_CLK_SEL << BIT_SHIFT_CPU_CLK_SEL)
+#define BIT_CLEAR_CPU_CLK_SEL(x) ((x) & (~BITS_CPU_CLK_SEL))
+#define BIT_GET_CPU_CLK_SEL(x) \
+ (((x) >> BIT_SHIFT_CPU_CLK_SEL) & BIT_MASK_CPU_CLK_SEL)
+#define BIT_SET_CPU_CLK_SEL(x, v) \
+ (BIT_CLEAR_CPU_CLK_SEL(x) | BIT_CPU_CLK_SEL(v))
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_8051FW_CTRL (Offset 0x0080) */
-#define BIT_R_8051_ROMDLFW_EN BIT(11)
+#define BIT_R_8051_ROMDLFW_EN BIT(11)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_MCUFW_CTRL (Offset 0x0080) */
-#define BIT_CCLK_CHG_MASK BIT(11)
+#define BIT_CCLK_CHG_MASK BIT(11)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_8051FW_CTRL (Offset 0x0080) */
-#define BIT_R_8051_INIT_RDY BIT(10)
+#define BIT_R_8051_INIT_RDY BIT(10)
#endif
-
#if (HALMAC_8197F_SUPPORT)
-
/* 2 REG_MCUFW_CTRL (Offset 0x0080) */
-#define BIT_FW_INIT_RDY_V1 BIT(10)
+#define BIT_FW_INIT_RDY_V1 BIT(10)
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_MCUFW_CTRL (Offset 0x0080) */
-#define BIT_EMEM_TXBUF_CHKSUM_OK BIT(10)
+#define BIT_EMEM__TXBUF_CHKSUM_OK BIT(10)
#endif
-
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
/* 2 REG_MCUFW_CTRL (Offset 0x0080) */
-#define BIT_EMEM__TXBUF_CHKSUM_OK BIT(10)
+#define BIT_EMEM_TXBUF_CHKSUM_OK BIT(10)
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_MCUFW_CTRL (Offset 0x0080) */
-#define BIT_EMEM_TXBUF_DW_RDY BIT(9)
+#define BIT_EMEM_TXBUF_DW_RDY BIT(9)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_8051FW_CTRL (Offset 0x0080) */
-#define BIT_R_8051_GAT BIT(8)
+#define BIT_R_8051_GAT BIT(8)
#endif
-
#if (HALMAC_8197F_SUPPORT)
-
/* 2 REG_MCUFW_CTRL (Offset 0x0080) */
-#define BIT_MCU_CLK_EN BIT(8)
+#define BIT_MCU_CLK_EN BIT(8)
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_MCUFW_CTRL (Offset 0x0080) */
-#define BIT_EMEM_CHKSUM_OK BIT(8)
-#define BIT_EMEM_DW_OK BIT(7)
-#define BIT_TOGGLING BIT(7)
-#define BIT_DMEM_CHKSUM_OK BIT(6)
+#define BIT_EMEM_CHKSUM_OK BIT(8)
+#define BIT_EMEM_DW_OK BIT(7)
+#define BIT_DMEM_CHKSUM_OK BIT(6)
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_SDIO_HRPWM1 (Offset 0x10250080) */
+#define BIT_ACK BIT(6)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_8051FW_CTRL (Offset 0x0080) */
-#define BIT_RFINI_RDY BIT(5)
+#define BIT_RFINI_RDY BIT(5)
#endif
-
#if (HALMAC_8197F_SUPPORT)
-
/* 2 REG_MCUFW_CTRL (Offset 0x0080) */
-#define BIT_RF_INIT_RDY BIT(5)
+#define BIT_RF_INIT_RDY BIT(5)
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_MCUFW_CTRL (Offset 0x0080) */
-#define BIT_DMEM_DW_OK BIT(5)
+#define BIT_DMEM_DW_OK BIT(5)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_8051FW_CTRL (Offset 0x0080) */
-#define BIT_BBINI_RDY BIT(4)
+#define BIT_BBINI_RDY BIT(4)
#endif
-
#if (HALMAC_8197F_SUPPORT)
-
/* 2 REG_MCUFW_CTRL (Offset 0x0080) */
-#define BIT_BB_INIT_RDY BIT(4)
+#define BIT_BB_INIT_RDY BIT(4)
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_MCUFW_CTRL (Offset 0x0080) */
-#define BIT_IMEM_CHKSUM_OK BIT(4)
+#define BIT_IMEM_CHKSUM_OK BIT(4)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_8051FW_CTRL (Offset 0x0080) */
-#define BIT_MACINI_RDY BIT(3)
+#define BIT_MACINI_RDY BIT(3)
#endif
-
#if (HALMAC_8197F_SUPPORT)
-
/* 2 REG_MCUFW_CTRL (Offset 0x0080) */
-#define BIT_MAC_INIT_RDY BIT(3)
+#define BIT_MAC_INIT_RDY BIT(3)
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_MCUFW_CTRL (Offset 0x0080) */
-#define BIT_IMEM_DW_OK BIT(3)
-#define BIT_WWLAN BIT(3)
+#define BIT_IMEM_DW_OK BIT(3)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_8051FW_CTRL (Offset 0x0080) */
-#define BIT_FWDL_CHK_RPT BIT(2)
+#define BIT_FWDL_CHK_RPT BIT(2)
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_MCUFW_CTRL (Offset 0x0080) */
-#define BIT_IMEM_BOOT_LOAD_CHKSUM_OK BIT(2)
-#define BIT_RPS_ST BIT(2)
+#define BIT_IMEM_BOOT_LOAD_CHKSUM_OK BIT(2)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_8051FW_CTRL (Offset 0x0080) */
-#define BIT_MCUFWDL_RDY BIT(1)
+#define BIT_MCUFWDL_RDY BIT(1)
#endif
-
#if (HALMAC_8197F_SUPPORT)
-
/* 2 REG_MCUFW_CTRL (Offset 0x0080) */
-#define BIT_MCU_FWDL_RDY BIT(1)
+#define BIT_MCU_FWDL_RDY BIT(1)
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_MCUFW_CTRL (Offset 0x0080) */
-#define BIT_IMEM_BOOT_LOAD_DW_OK BIT(1)
-#define BIT_WLAN_TRX BIT(1)
+#define BIT_IMEM_BOOT_LOAD_DW_OK BIT(1)
#endif
-
#if (HALMAC_8197F_SUPPORT)
-
/* 2 REG_MCUFW_CTRL (Offset 0x0080) */
-#define BIT_MCU_FWDL_EN BIT(0)
+#define BIT_MCU_FWDL_EN BIT(0)
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_HRPWM1 (Offset 0x10250080) */
-#define BIT_SYS_CLK BIT(0)
+#define BIT_REQ_PS BIT(0)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_MCU_TST_CFG (Offset 0x0084) */
-
-#define BIT_SHIFT_LBKTST 0
-#define BIT_MASK_LBKTST 0xffff
-#define BIT_LBKTST(x) (((x) & BIT_MASK_LBKTST) << BIT_SHIFT_LBKTST)
-#define BIT_GET_LBKTST(x) (((x) >> BIT_SHIFT_LBKTST) & BIT_MASK_LBKTST)
-
+#define BIT_SHIFT_LBKTST 0
+#define BIT_MASK_LBKTST 0xffff
+#define BIT_LBKTST(x) (((x) & BIT_MASK_LBKTST) << BIT_SHIFT_LBKTST)
+#define BITS_LBKTST (BIT_MASK_LBKTST << BIT_SHIFT_LBKTST)
+#define BIT_CLEAR_LBKTST(x) ((x) & (~BITS_LBKTST))
+#define BIT_GET_LBKTST(x) (((x) >> BIT_SHIFT_LBKTST) & BIT_MASK_LBKTST)
+#define BIT_SET_LBKTST(x, v) (BIT_CLEAR_LBKTST(x) | BIT_LBKTST(v))
#endif
+#if (HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_MCU_TST_CFG (Offset 0x0084) */
+#define BIT_SHIFT_C2H_MSG 0
+#define BIT_MASK_C2H_MSG 0xffff
+#define BIT_C2H_MSG(x) (((x) & BIT_MASK_C2H_MSG) << BIT_SHIFT_C2H_MSG)
+#define BITS_C2H_MSG (BIT_MASK_C2H_MSG << BIT_SHIFT_C2H_MSG)
+#define BIT_CLEAR_C2H_MSG(x) ((x) & (~BITS_C2H_MSG))
+#define BIT_GET_C2H_MSG(x) (((x) >> BIT_SHIFT_C2H_MSG) & BIT_MASK_C2H_MSG)
+#define BIT_SET_C2H_MSG(x, v) (BIT_CLEAR_C2H_MSG(x) | BIT_C2H_MSG(v))
-/* 2 REG_SDIO_BUS_CTRL (Offset 0x10250085) */
+#endif
-#define BIT_PAD_CLK_XHGE_EN BIT(3)
-#define BIT_INTER_CLK_EN BIT(2)
-#define BIT_EN_RPT_TXCRC BIT(1)
-#define BIT_DIS_RXDMA_STS BIT(0)
+#if (HALMAC_8822C_SUPPORT)
-/* 2 REG_SDIO_HSUS_CTRL (Offset 0x10250086) */
+/* 2 REG_SDIO_BUS_CTRL (Offset 0x10250085) */
-#define BIT_INTR_CTRL BIT(4)
-#define BIT_SDIO_VOLTAGE BIT(3)
-#define BIT_BYPASS_INIT BIT(2)
+#define BIT_INT_MASK_DIS BIT(4)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_SDIO_BUS_CTRL (Offset 0x10250085) */
+#define BIT_PAD_CLK_XHGE_EN BIT(3)
+#define BIT_INTER_CLK_EN BIT(2)
+#define BIT_EN_RPT_TXCRC BIT(1)
+#define BIT_DIS_RXDMA_STS BIT(0)
/* 2 REG_SDIO_HSUS_CTRL (Offset 0x10250086) */
-#define BIT_HCI_RESUME_RDY BIT(1)
-#define BIT_HCI_SUS_REQ BIT(0)
+#define BIT_INTR_CTRL BIT(4)
+#define BIT_SDIO_VOLTAGE BIT(3)
+#define BIT_BYPASS_INIT BIT(2)
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-
-/* 2 REG_HMEBOX_E0_E1 (Offset 0x0088) */
-
-
-#define BIT_SHIFT_HOST_MSG_E1 16
-#define BIT_MASK_HOST_MSG_E1 0xffff
-#define BIT_HOST_MSG_E1(x) (((x) & BIT_MASK_HOST_MSG_E1) << BIT_SHIFT_HOST_MSG_E1)
-#define BIT_GET_HOST_MSG_E1(x) (((x) >> BIT_SHIFT_HOST_MSG_E1) & BIT_MASK_HOST_MSG_E1)
-
-
-#define BIT_SHIFT_HOST_MSG_E0 0
-#define BIT_MASK_HOST_MSG_E0 0xffff
-#define BIT_HOST_MSG_E0(x) (((x) & BIT_MASK_HOST_MSG_E0) << BIT_SHIFT_HOST_MSG_E0)
-#define BIT_GET_HOST_MSG_E0(x) (((x) >> BIT_SHIFT_HOST_MSG_E0) & BIT_MASK_HOST_MSG_E0)
+/* 2 REG_SDIO_HSUS_CTRL (Offset 0x10250086) */
+#define BIT_HCI_RESUME_RDY BIT(1)
+#define BIT_HCI_SUS_REQ BIT(0)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_HMEBOX_E0_E1 (Offset 0x0088) */
+#define BIT_SHIFT_HOST_MSG_E1 16
+#define BIT_MASK_HOST_MSG_E1 0xffff
+#define BIT_HOST_MSG_E1(x) \
+ (((x) & BIT_MASK_HOST_MSG_E1) << BIT_SHIFT_HOST_MSG_E1)
+#define BITS_HOST_MSG_E1 (BIT_MASK_HOST_MSG_E1 << BIT_SHIFT_HOST_MSG_E1)
+#define BIT_CLEAR_HOST_MSG_E1(x) ((x) & (~BITS_HOST_MSG_E1))
+#define BIT_GET_HOST_MSG_E1(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_E1) & BIT_MASK_HOST_MSG_E1)
+#define BIT_SET_HOST_MSG_E1(x, v) \
+ (BIT_CLEAR_HOST_MSG_E1(x) | BIT_HOST_MSG_E1(v))
+
+#define BIT_SHIFT_HOST_MSG_E0 0
+#define BIT_MASK_HOST_MSG_E0 0xffff
+#define BIT_HOST_MSG_E0(x) \
+ (((x) & BIT_MASK_HOST_MSG_E0) << BIT_SHIFT_HOST_MSG_E0)
+#define BITS_HOST_MSG_E0 (BIT_MASK_HOST_MSG_E0 << BIT_SHIFT_HOST_MSG_E0)
+#define BIT_CLEAR_HOST_MSG_E0(x) ((x) & (~BITS_HOST_MSG_E0))
+#define BIT_GET_HOST_MSG_E0(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_E0) & BIT_MASK_HOST_MSG_E0)
+#define BIT_SET_HOST_MSG_E0(x, v) \
+ (BIT_CLEAR_HOST_MSG_E0(x) | BIT_HOST_MSG_E0(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_RESPONSE_TIMER (Offset 0x10250088) */
-
-#define BIT_SHIFT_CMDIN_2RESP_TIMER 0
-#define BIT_MASK_CMDIN_2RESP_TIMER 0xffff
-#define BIT_CMDIN_2RESP_TIMER(x) (((x) & BIT_MASK_CMDIN_2RESP_TIMER) << BIT_SHIFT_CMDIN_2RESP_TIMER)
-#define BIT_GET_CMDIN_2RESP_TIMER(x) (((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER) & BIT_MASK_CMDIN_2RESP_TIMER)
-
+#define BIT_SHIFT_CMDIN_2RESP_TIMER 0
+#define BIT_MASK_CMDIN_2RESP_TIMER 0xffff
+#define BIT_CMDIN_2RESP_TIMER(x) \
+ (((x) & BIT_MASK_CMDIN_2RESP_TIMER) << BIT_SHIFT_CMDIN_2RESP_TIMER)
+#define BITS_CMDIN_2RESP_TIMER \
+ (BIT_MASK_CMDIN_2RESP_TIMER << BIT_SHIFT_CMDIN_2RESP_TIMER)
+#define BIT_CLEAR_CMDIN_2RESP_TIMER(x) ((x) & (~BITS_CMDIN_2RESP_TIMER))
+#define BIT_GET_CMDIN_2RESP_TIMER(x) \
+ (((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER) & BIT_MASK_CMDIN_2RESP_TIMER)
+#define BIT_SET_CMDIN_2RESP_TIMER(x, v) \
+ (BIT_CLEAR_CMDIN_2RESP_TIMER(x) | BIT_CMDIN_2RESP_TIMER(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SDIO_CMD_CRC (Offset 0x1025008A) */
+#define BIT_SHIFT_SDIO_CMD_CRC 1
+#define BIT_MASK_SDIO_CMD_CRC 0x7f
+#define BIT_SDIO_CMD_CRC(x) \
+ (((x) & BIT_MASK_SDIO_CMD_CRC) << BIT_SHIFT_SDIO_CMD_CRC)
+#define BITS_SDIO_CMD_CRC (BIT_MASK_SDIO_CMD_CRC << BIT_SHIFT_SDIO_CMD_CRC)
+#define BIT_CLEAR_SDIO_CMD_CRC(x) ((x) & (~BITS_SDIO_CMD_CRC))
+#define BIT_GET_SDIO_CMD_CRC(x) \
+ (((x) >> BIT_SHIFT_SDIO_CMD_CRC) & BIT_MASK_SDIO_CMD_CRC)
+#define BIT_SET_SDIO_CMD_CRC(x, v) \
+ (BIT_CLEAR_SDIO_CMD_CRC(x) | BIT_SDIO_CMD_CRC(v))
-#define BIT_SHIFT_SDIO_CMD_CRC 1
-#define BIT_MASK_SDIO_CMD_CRC 0x7f
-#define BIT_SDIO_CMD_CRC(x) (((x) & BIT_MASK_SDIO_CMD_CRC) << BIT_SHIFT_SDIO_CMD_CRC)
-#define BIT_GET_SDIO_CMD_CRC(x) (((x) >> BIT_SHIFT_SDIO_CMD_CRC) & BIT_MASK_SDIO_CMD_CRC)
-
-#define BIT_SDIO_CMD_E_BIT BIT(0)
+#define BIT_SDIO_CMD_E_BIT BIT(0)
#endif
-
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_CMD_CRC (Offset 0x1025008A) */
-
-#define BIT_SHIFT_SDIO_CMD_CRC_V1 0
-#define BIT_MASK_SDIO_CMD_CRC_V1 0xff
-#define BIT_SDIO_CMD_CRC_V1(x) (((x) & BIT_MASK_SDIO_CMD_CRC_V1) << BIT_SHIFT_SDIO_CMD_CRC_V1)
-#define BIT_GET_SDIO_CMD_CRC_V1(x) (((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1) & BIT_MASK_SDIO_CMD_CRC_V1)
-
+#define BIT_SHIFT_SDIO_CMD_CRC_V1 0
+#define BIT_MASK_SDIO_CMD_CRC_V1 0xff
+#define BIT_SDIO_CMD_CRC_V1(x) \
+ (((x) & BIT_MASK_SDIO_CMD_CRC_V1) << BIT_SHIFT_SDIO_CMD_CRC_V1)
+#define BITS_SDIO_CMD_CRC_V1 \
+ (BIT_MASK_SDIO_CMD_CRC_V1 << BIT_SHIFT_SDIO_CMD_CRC_V1)
+#define BIT_CLEAR_SDIO_CMD_CRC_V1(x) ((x) & (~BITS_SDIO_CMD_CRC_V1))
+#define BIT_GET_SDIO_CMD_CRC_V1(x) \
+ (((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1) & BIT_MASK_SDIO_CMD_CRC_V1)
+#define BIT_SET_SDIO_CMD_CRC_V1(x, v) \
+ (BIT_CLEAR_SDIO_CMD_CRC_V1(x) | BIT_SDIO_CMD_CRC_V1(v))
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_HMEBOX_E2_E3 (Offset 0x008C) */
+#define BIT_SHIFT_HOST_MSG_E3 16
+#define BIT_MASK_HOST_MSG_E3 0xffff
+#define BIT_HOST_MSG_E3(x) \
+ (((x) & BIT_MASK_HOST_MSG_E3) << BIT_SHIFT_HOST_MSG_E3)
+#define BITS_HOST_MSG_E3 (BIT_MASK_HOST_MSG_E3 << BIT_SHIFT_HOST_MSG_E3)
+#define BIT_CLEAR_HOST_MSG_E3(x) ((x) & (~BITS_HOST_MSG_E3))
+#define BIT_GET_HOST_MSG_E3(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_E3) & BIT_MASK_HOST_MSG_E3)
+#define BIT_SET_HOST_MSG_E3(x, v) \
+ (BIT_CLEAR_HOST_MSG_E3(x) | BIT_HOST_MSG_E3(v))
+
+#define BIT_SHIFT_HOST_MSG_E2 0
+#define BIT_MASK_HOST_MSG_E2 0xffff
+#define BIT_HOST_MSG_E2(x) \
+ (((x) & BIT_MASK_HOST_MSG_E2) << BIT_SHIFT_HOST_MSG_E2)
+#define BITS_HOST_MSG_E2 (BIT_MASK_HOST_MSG_E2 << BIT_SHIFT_HOST_MSG_E2)
+#define BIT_CLEAR_HOST_MSG_E2(x) ((x) & (~BITS_HOST_MSG_E2))
+#define BIT_GET_HOST_MSG_E2(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_E2) & BIT_MASK_HOST_MSG_E2)
+#define BIT_SET_HOST_MSG_E2(x, v) \
+ (BIT_CLEAR_HOST_MSG_E2(x) | BIT_HOST_MSG_E2(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_HOST_MSG_E3 16
-#define BIT_MASK_HOST_MSG_E3 0xffff
-#define BIT_HOST_MSG_E3(x) (((x) & BIT_MASK_HOST_MSG_E3) << BIT_SHIFT_HOST_MSG_E3)
-#define BIT_GET_HOST_MSG_E3(x) (((x) >> BIT_SHIFT_HOST_MSG_E3) & BIT_MASK_HOST_MSG_E3)
-
-
-#define BIT_SHIFT_HOST_MSG_E2 0
-#define BIT_MASK_HOST_MSG_E2 0xffff
-#define BIT_HOST_MSG_E2(x) (((x) & BIT_MASK_HOST_MSG_E2) << BIT_SHIFT_HOST_MSG_E2)
-#define BIT_GET_HOST_MSG_E2(x) (((x) >> BIT_SHIFT_HOST_MSG_E2) & BIT_MASK_HOST_MSG_E2)
+/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
+#define BIT_WLLPSOP_EABM BIT(31)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
-#define BIT_WLLPSOP_EABM BIT(31)
+#define BIT_WLLPSOP_ACKF BIT(30)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
-#define BIT_WLLPSOP_ACKF BIT(30)
+#define BIT_TXFIFO_TH_INT BIT(30)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
-#define BIT_WLLPSOP_DLDM BIT(29)
+#define BIT_WLLPSOP_DLDM BIT(29)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
-#define BIT_WLLPSOP_AFEP BIT(29)
+#define BIT_WLLPSOP_AFEP BIT(29)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
-#define BIT_WLLPSOP_ESWR BIT(28)
+#define BIT_WLLPSOP_ESWR BIT(28)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
-#define BIT_LPS_DIS_SW BIT(28)
+#define BIT_LPS_DIS_SW BIT(28)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
-#define BIT_WLLPSOP_PWMM BIT(27)
-#define BIT_WLLPSOP_EECK BIT(26)
+#define BIT_WLLPSOP_PWMM BIT(27)
+#define BIT_WLLPSOP_EECK BIT(26)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
-#define BIT_WLLPSOP_ELDO BIT(25)
+#define BIT_WLLPSOP_ELDO BIT(25)
#endif
-
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
-#define BIT_WLLPSOP_WLMACOFF BIT(25)
+#define BIT_WLLPSOP_WLMACOFF BIT(25)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
-#define BIT_WLLPSOP_EXTAL BIT(24)
+#define BIT_WLLPSOP_EXTAL BIT(24)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
-#define BIT_LPS_BB_REG_EN BIT(23)
+#define BIT_LPS_BB_REG_EN BIT(23)
#endif
-
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
-#define BIT_WL_SYNPON_VOLTSPDN BIT(23)
+#define BIT_WL_SYNPON_VOLTSPDN BIT(23)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
-#define BIT_LPS_BB_PWR_EN BIT(22)
+#define BIT_LPS_BB_PWR_EN BIT(22)
#endif
-
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
-#define BIT_WLLPSOP_WLBBOFF BIT(22)
+#define BIT_WLLPSOP_WLBBOFF BIT(22)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
-#define BIT_LPS_BB_GLB_EN BIT(21)
+#define BIT_LPS_BB_GLB_EN BIT(21)
#endif
-
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
-#define BIT_WLLPSOP_WLMEM_DS BIT(21)
+#define BIT_WLLPSOP_WLMEM_DS BIT(21)
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
+#if (HALMAC_8822C_SUPPORT)
/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
-#define BIT_SUS_DIS_SW BIT(15)
-#define BIT_SUS_SKP_PAGE0_ALD BIT(14)
-#define BIT_SUS_LDO_SLEEP BIT(13)
-#define BIT_PFM_EN_ZCD BIT(12)
+#define BIT_WLLPSOP_LDO_WAIT_TIME BIT(20)
+#define BIT_WLLPSOP_ANA_CLK_DIVISION_2 BIT(19)
+#define BIT_AFE_BCN BIT(18)
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
+#define BIT_SUS_DIS_SW BIT(15)
+#define BIT_SUS_SKP_PAGE0_ALD BIT(14)
+#define BIT_SUS_LDO_SLEEP BIT(13)
+#define BIT_PFM_EN_ZCD BIT(12)
-/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_LPLDH12_VADJ_STEP_DN 12
-#define BIT_MASK_LPLDH12_VADJ_STEP_DN 0xf
-#define BIT_LPLDH12_VADJ_STEP_DN(x) (((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN) << BIT_SHIFT_LPLDH12_VADJ_STEP_DN)
-#define BIT_GET_LPLDH12_VADJ_STEP_DN(x) (((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN) & BIT_MASK_LPLDH12_VADJ_STEP_DN)
+/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
+#define BIT_SHIFT_LPLDH12_VADJ_STEP_DN 12
+#define BIT_MASK_LPLDH12_VADJ_STEP_DN 0xf
+#define BIT_LPLDH12_VADJ_STEP_DN(x) \
+ (((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN) \
+ << BIT_SHIFT_LPLDH12_VADJ_STEP_DN)
+#define BITS_LPLDH12_VADJ_STEP_DN \
+ (BIT_MASK_LPLDH12_VADJ_STEP_DN << BIT_SHIFT_LPLDH12_VADJ_STEP_DN)
+#define BIT_CLEAR_LPLDH12_VADJ_STEP_DN(x) ((x) & (~BITS_LPLDH12_VADJ_STEP_DN))
+#define BIT_GET_LPLDH12_VADJ_STEP_DN(x) \
+ (((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN) & \
+ BIT_MASK_LPLDH12_VADJ_STEP_DN)
+#define BIT_SET_LPLDH12_VADJ_STEP_DN(x, v) \
+ (BIT_CLEAR_LPLDH12_VADJ_STEP_DN(x) | BIT_LPLDH12_VADJ_STEP_DN(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
-#define BIT_KEEP_RFC_EN BIT(11)
-#define BIT_MACON_NO_RFCISO_RELEASE BIT(10)
-#define BIT_MACON_NO_AFEPORT_PWR BIT(9)
-#define BIT_MACON_NO_CPU_EN BIT(8)
+#define BIT_KEEP_RFC_EN BIT(11)
+#define BIT_MACON_NO_RFCISO_RELEASE BIT(10)
+#define BIT_MACON_NO_AFEPORT_PWR BIT(9)
+#define BIT_MACON_NO_CPU_EN BIT(8)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
+#define BIT_SHIFT_V15ADJ_L1_STEP_DN 8
+#define BIT_MASK_V15ADJ_L1_STEP_DN 0x7
+#define BIT_V15ADJ_L1_STEP_DN(x) \
+ (((x) & BIT_MASK_V15ADJ_L1_STEP_DN) << BIT_SHIFT_V15ADJ_L1_STEP_DN)
+#define BITS_V15ADJ_L1_STEP_DN \
+ (BIT_MASK_V15ADJ_L1_STEP_DN << BIT_SHIFT_V15ADJ_L1_STEP_DN)
+#define BIT_CLEAR_V15ADJ_L1_STEP_DN(x) ((x) & (~BITS_V15ADJ_L1_STEP_DN))
+#define BIT_GET_V15ADJ_L1_STEP_DN(x) \
+ (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN) & BIT_MASK_V15ADJ_L1_STEP_DN)
+#define BIT_SET_V15ADJ_L1_STEP_DN(x, v) \
+ (BIT_CLEAR_V15ADJ_L1_STEP_DN(x) | BIT_V15ADJ_L1_STEP_DN(v))
-/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
-#define BIT_SHIFT_V15ADJ_L1_STEP_DN 8
-#define BIT_MASK_V15ADJ_L1_STEP_DN 0x7
-#define BIT_V15ADJ_L1_STEP_DN(x) (((x) & BIT_MASK_V15ADJ_L1_STEP_DN) << BIT_SHIFT_V15ADJ_L1_STEP_DN)
-#define BIT_GET_V15ADJ_L1_STEP_DN(x) (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN) & BIT_MASK_V15ADJ_L1_STEP_DN)
+#define BIT_SHIFT_V15ADJ_L1_STEP_DN_V1 8
+#define BIT_MASK_V15ADJ_L1_STEP_DN_V1 0xf
+#define BIT_V15ADJ_L1_STEP_DN_V1(x) \
+ (((x) & BIT_MASK_V15ADJ_L1_STEP_DN_V1) \
+ << BIT_SHIFT_V15ADJ_L1_STEP_DN_V1)
+#define BITS_V15ADJ_L1_STEP_DN_V1 \
+ (BIT_MASK_V15ADJ_L1_STEP_DN_V1 << BIT_SHIFT_V15ADJ_L1_STEP_DN_V1)
+#define BIT_CLEAR_V15ADJ_L1_STEP_DN_V1(x) ((x) & (~BITS_V15ADJ_L1_STEP_DN_V1))
+#define BIT_GET_V15ADJ_L1_STEP_DN_V1(x) \
+ (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN_V1) & \
+ BIT_MASK_V15ADJ_L1_STEP_DN_V1)
+#define BIT_SET_V15ADJ_L1_STEP_DN_V1(x, v) \
+ (BIT_CLEAR_V15ADJ_L1_STEP_DN_V1(x) | BIT_V15ADJ_L1_STEP_DN_V1(v))
-#define BIT_REGU_32K_CLK_EN BIT(1)
-#define BIT_DRV_WLAN_INT_CLR BIT(1)
+#define BIT_FORCE_LEAVE_LPS BIT(3)
+#define BIT_SW_AFE_MODE BIT(2)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
+
+#define BIT_REGU_32K_CLK_EN BIT(1)
+#define BIT_DRV_WLAN_INT_CLR BIT(1)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_WLLPS_CTRL (Offset 0x0090) */
-#define BIT_WL_LPS_EN BIT(0)
+#define BIT_WL_LPS_EN BIT(0)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_SDIO_HSISR (Offset 0x10250090) */
+#define BIT_DRV_WLAN_INT BIT(0)
-/* 2 REG_SDIO_HSISR (Offset 0x10250090) */
+#endif
-#define BIT_DRV_WLAN_INT BIT(0)
+#if (HALMAC_8822C_SUPPORT)
/* 2 REG_SDIO_HSIMR (Offset 0x10250091) */
-#define BIT_HISR_MASK BIT(0)
+#define BIT_HISR_MASK BIT(0)
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_AFE_CTRL5 (Offset 0x0094) */
-#define BIT_BB_DBG_SEL_AFE_SDM_V3 BIT(31)
+#define BIT_BB_DBG_SEL_AFE_SDM_V3 BIT(31)
#endif
-
#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
/* 2 REG_AFE_CTRL5 (Offset 0x0094) */
-#define BIT_BB_DBG_SEL_AFE_SDM_BIT0 BIT(31)
+#define BIT_BB_DBG_SEL_AFE_SDM_BIT0 BIT(31)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
/* 2 REG_AFE_CTRL5 (Offset 0x0094) */
-#define BIT_ORDER_SDM BIT(30)
-#define BIT_RFE_SEL_SDM BIT(29)
-
-#define BIT_SHIFT_REF_SEL 25
-#define BIT_MASK_REF_SEL 0xf
-#define BIT_REF_SEL(x) (((x) & BIT_MASK_REF_SEL) << BIT_SHIFT_REF_SEL)
-#define BIT_GET_REF_SEL(x) (((x) >> BIT_SHIFT_REF_SEL) & BIT_MASK_REF_SEL)
+#define BIT_ORDER_SDM BIT(30)
+#define BIT_RFE_SEL_SDM BIT(29)
+#define BIT_SHIFT_REF_SEL 25
+#define BIT_MASK_REF_SEL 0xf
+#define BIT_REF_SEL(x) (((x) & BIT_MASK_REF_SEL) << BIT_SHIFT_REF_SEL)
+#define BITS_REF_SEL (BIT_MASK_REF_SEL << BIT_SHIFT_REF_SEL)
+#define BIT_CLEAR_REF_SEL(x) ((x) & (~BITS_REF_SEL))
+#define BIT_GET_REF_SEL(x) (((x) >> BIT_SHIFT_REF_SEL) & BIT_MASK_REF_SEL)
+#define BIT_SET_REF_SEL(x, v) (BIT_CLEAR_REF_SEL(x) | BIT_REF_SEL(v))
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_AFE_CTRL5 (Offset 0x0094) */
-
-#define BIT_SHIFT_F0F_SDM_V2 12
-#define BIT_MASK_F0F_SDM_V2 0x1fff
-#define BIT_F0F_SDM_V2(x) (((x) & BIT_MASK_F0F_SDM_V2) << BIT_SHIFT_F0F_SDM_V2)
-#define BIT_GET_F0F_SDM_V2(x) (((x) >> BIT_SHIFT_F0F_SDM_V2) & BIT_MASK_F0F_SDM_V2)
-
+#define BIT_SHIFT_F0F_SDM_V2 12
+#define BIT_MASK_F0F_SDM_V2 0x1fff
+#define BIT_F0F_SDM_V2(x) (((x) & BIT_MASK_F0F_SDM_V2) << BIT_SHIFT_F0F_SDM_V2)
+#define BITS_F0F_SDM_V2 (BIT_MASK_F0F_SDM_V2 << BIT_SHIFT_F0F_SDM_V2)
+#define BIT_CLEAR_F0F_SDM_V2(x) ((x) & (~BITS_F0F_SDM_V2))
+#define BIT_GET_F0F_SDM_V2(x) \
+ (((x) >> BIT_SHIFT_F0F_SDM_V2) & BIT_MASK_F0F_SDM_V2)
+#define BIT_SET_F0F_SDM_V2(x, v) (BIT_CLEAR_F0F_SDM_V2(x) | BIT_F0F_SDM_V2(v))
#endif
-
#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
/* 2 REG_AFE_CTRL5 (Offset 0x0094) */
+#define BIT_SHIFT_F0F_SDM 12
+#define BIT_MASK_F0F_SDM 0x1fff
+#define BIT_F0F_SDM(x) (((x) & BIT_MASK_F0F_SDM) << BIT_SHIFT_F0F_SDM)
+#define BITS_F0F_SDM (BIT_MASK_F0F_SDM << BIT_SHIFT_F0F_SDM)
+#define BIT_CLEAR_F0F_SDM(x) ((x) & (~BITS_F0F_SDM))
+#define BIT_GET_F0F_SDM(x) (((x) >> BIT_SHIFT_F0F_SDM) & BIT_MASK_F0F_SDM)
+#define BIT_SET_F0F_SDM(x, v) (BIT_CLEAR_F0F_SDM(x) | BIT_F0F_SDM(v))
-#define BIT_SHIFT_F0F_SDM 12
-#define BIT_MASK_F0F_SDM 0x1fff
-#define BIT_F0F_SDM(x) (((x) & BIT_MASK_F0F_SDM) << BIT_SHIFT_F0F_SDM)
-#define BIT_GET_F0F_SDM(x) (((x) >> BIT_SHIFT_F0F_SDM) & BIT_MASK_F0F_SDM)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#endif
+/* 2 REG_AFE_CTRL5 (Offset 0x0094) */
+#define BIT_SHIFT_F0N_SDM_V2 9
+#define BIT_MASK_F0N_SDM_V2 0x7
+#define BIT_F0N_SDM_V2(x) (((x) & BIT_MASK_F0N_SDM_V2) << BIT_SHIFT_F0N_SDM_V2)
+#define BITS_F0N_SDM_V2 (BIT_MASK_F0N_SDM_V2 << BIT_SHIFT_F0N_SDM_V2)
+#define BIT_CLEAR_F0N_SDM_V2(x) ((x) & (~BITS_F0N_SDM_V2))
+#define BIT_GET_F0N_SDM_V2(x) \
+ (((x) >> BIT_SHIFT_F0N_SDM_V2) & BIT_MASK_F0N_SDM_V2)
+#define BIT_SET_F0N_SDM_V2(x, v) (BIT_CLEAR_F0N_SDM_V2(x) | BIT_F0N_SDM_V2(v))
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
/* 2 REG_AFE_CTRL5 (Offset 0x0094) */
+#define BIT_SHIFT_F0N_SDM 9
+#define BIT_MASK_F0N_SDM 0x7
+#define BIT_F0N_SDM(x) (((x) & BIT_MASK_F0N_SDM) << BIT_SHIFT_F0N_SDM)
+#define BITS_F0N_SDM (BIT_MASK_F0N_SDM << BIT_SHIFT_F0N_SDM)
+#define BIT_CLEAR_F0N_SDM(x) ((x) & (~BITS_F0N_SDM))
+#define BIT_GET_F0N_SDM(x) (((x) >> BIT_SHIFT_F0N_SDM) & BIT_MASK_F0N_SDM)
+#define BIT_SET_F0N_SDM(x, v) (BIT_CLEAR_F0N_SDM(x) | BIT_F0N_SDM(v))
-#define BIT_SHIFT_F0N_SDM_V2 9
-#define BIT_MASK_F0N_SDM_V2 0x7
-#define BIT_F0N_SDM_V2(x) (((x) & BIT_MASK_F0N_SDM_V2) << BIT_SHIFT_F0N_SDM_V2)
-#define BIT_GET_F0N_SDM_V2(x) (((x) >> BIT_SHIFT_F0N_SDM_V2) & BIT_MASK_F0N_SDM_V2)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#endif
+/* 2 REG_AFE_CTRL5 (Offset 0x0094) */
+#define BIT_SHIFT_DIVN_SDM_V2 3
+#define BIT_MASK_DIVN_SDM_V2 0x3f
+#define BIT_DIVN_SDM_V2(x) \
+ (((x) & BIT_MASK_DIVN_SDM_V2) << BIT_SHIFT_DIVN_SDM_V2)
+#define BITS_DIVN_SDM_V2 (BIT_MASK_DIVN_SDM_V2 << BIT_SHIFT_DIVN_SDM_V2)
+#define BIT_CLEAR_DIVN_SDM_V2(x) ((x) & (~BITS_DIVN_SDM_V2))
+#define BIT_GET_DIVN_SDM_V2(x) \
+ (((x) >> BIT_SHIFT_DIVN_SDM_V2) & BIT_MASK_DIVN_SDM_V2)
+#define BIT_SET_DIVN_SDM_V2(x, v) \
+ (BIT_CLEAR_DIVN_SDM_V2(x) | BIT_DIVN_SDM_V2(v))
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
/* 2 REG_AFE_CTRL5 (Offset 0x0094) */
+#define BIT_SHIFT_DIVN_SDM 3
+#define BIT_MASK_DIVN_SDM 0x3f
+#define BIT_DIVN_SDM(x) (((x) & BIT_MASK_DIVN_SDM) << BIT_SHIFT_DIVN_SDM)
+#define BITS_DIVN_SDM (BIT_MASK_DIVN_SDM << BIT_SHIFT_DIVN_SDM)
+#define BIT_CLEAR_DIVN_SDM(x) ((x) & (~BITS_DIVN_SDM))
+#define BIT_GET_DIVN_SDM(x) (((x) >> BIT_SHIFT_DIVN_SDM) & BIT_MASK_DIVN_SDM)
+#define BIT_SET_DIVN_SDM(x, v) (BIT_CLEAR_DIVN_SDM(x) | BIT_DIVN_SDM(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_F0N_SDM 9
-#define BIT_MASK_F0N_SDM 0x7
-#define BIT_F0N_SDM(x) (((x) & BIT_MASK_F0N_SDM) << BIT_SHIFT_F0N_SDM)
-#define BIT_GET_F0N_SDM(x) (((x) >> BIT_SHIFT_F0N_SDM) & BIT_MASK_F0N_SDM)
+/* 2 REG_AFE_CTRL5 (Offset 0x0094) */
+#define BIT_SHIFT_DITHER_SDM_V2 0
+#define BIT_MASK_DITHER_SDM_V2 0x7
+#define BIT_DITHER_SDM_V2(x) \
+ (((x) & BIT_MASK_DITHER_SDM_V2) << BIT_SHIFT_DITHER_SDM_V2)
+#define BITS_DITHER_SDM_V2 (BIT_MASK_DITHER_SDM_V2 << BIT_SHIFT_DITHER_SDM_V2)
+#define BIT_CLEAR_DITHER_SDM_V2(x) ((x) & (~BITS_DITHER_SDM_V2))
+#define BIT_GET_DITHER_SDM_V2(x) \
+ (((x) >> BIT_SHIFT_DITHER_SDM_V2) & BIT_MASK_DITHER_SDM_V2)
+#define BIT_SET_DITHER_SDM_V2(x, v) \
+ (BIT_CLEAR_DITHER_SDM_V2(x) | BIT_DITHER_SDM_V2(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
+/* 2 REG_GPIO_DEBOUNCE_CTRL (Offset 0x0098) */
-/* 2 REG_AFE_CTRL5 (Offset 0x0094) */
+#define BIT_WLGP_DBC1EN BIT(15)
+#define BIT_SHIFT_WLGP_DBC1 8
+#define BIT_MASK_WLGP_DBC1 0xf
+#define BIT_WLGP_DBC1(x) (((x) & BIT_MASK_WLGP_DBC1) << BIT_SHIFT_WLGP_DBC1)
+#define BITS_WLGP_DBC1 (BIT_MASK_WLGP_DBC1 << BIT_SHIFT_WLGP_DBC1)
+#define BIT_CLEAR_WLGP_DBC1(x) ((x) & (~BITS_WLGP_DBC1))
+#define BIT_GET_WLGP_DBC1(x) (((x) >> BIT_SHIFT_WLGP_DBC1) & BIT_MASK_WLGP_DBC1)
+#define BIT_SET_WLGP_DBC1(x, v) (BIT_CLEAR_WLGP_DBC1(x) | BIT_WLGP_DBC1(v))
-#define BIT_SHIFT_DIVN_SDM_V2 3
-#define BIT_MASK_DIVN_SDM_V2 0x3f
-#define BIT_DIVN_SDM_V2(x) (((x) & BIT_MASK_DIVN_SDM_V2) << BIT_SHIFT_DIVN_SDM_V2)
-#define BIT_GET_DIVN_SDM_V2(x) (((x) >> BIT_SHIFT_DIVN_SDM_V2) & BIT_MASK_DIVN_SDM_V2)
+#define BIT_WLGP_DBC0EN BIT(7)
+#define BIT_SHIFT_WLGP_DBC0 0
+#define BIT_MASK_WLGP_DBC0 0xf
+#define BIT_WLGP_DBC0(x) (((x) & BIT_MASK_WLGP_DBC0) << BIT_SHIFT_WLGP_DBC0)
+#define BITS_WLGP_DBC0 (BIT_MASK_WLGP_DBC0 << BIT_SHIFT_WLGP_DBC0)
+#define BIT_CLEAR_WLGP_DBC0(x) ((x) & (~BITS_WLGP_DBC0))
+#define BIT_GET_WLGP_DBC0(x) (((x) >> BIT_SHIFT_WLGP_DBC0) & BIT_MASK_WLGP_DBC0)
+#define BIT_SET_WLGP_DBC0(x, v) (BIT_CLEAR_WLGP_DBC0(x) | BIT_WLGP_DBC0(v))
-#endif
+/* 2 REG_RPWM2 (Offset 0x009C) */
+#define BIT_SHIFT_RPWM2 16
+#define BIT_MASK_RPWM2 0xffff
+#define BIT_RPWM2(x) (((x) & BIT_MASK_RPWM2) << BIT_SHIFT_RPWM2)
+#define BITS_RPWM2 (BIT_MASK_RPWM2 << BIT_SHIFT_RPWM2)
+#define BIT_CLEAR_RPWM2(x) ((x) & (~BITS_RPWM2))
+#define BIT_GET_RPWM2(x) (((x) >> BIT_SHIFT_RPWM2) & BIT_MASK_RPWM2)
+#define BIT_SET_RPWM2(x, v) (BIT_CLEAR_RPWM2(x) | BIT_RPWM2(v))
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_AFE_CTRL5 (Offset 0x0094) */
+/* 2 REG_SYSON_FSM_MON (Offset 0x00A0) */
+#define BIT_SHIFT_FSM_MON_SEL 24
+#define BIT_MASK_FSM_MON_SEL 0x7
+#define BIT_FSM_MON_SEL(x) \
+ (((x) & BIT_MASK_FSM_MON_SEL) << BIT_SHIFT_FSM_MON_SEL)
+#define BITS_FSM_MON_SEL (BIT_MASK_FSM_MON_SEL << BIT_SHIFT_FSM_MON_SEL)
+#define BIT_CLEAR_FSM_MON_SEL(x) ((x) & (~BITS_FSM_MON_SEL))
+#define BIT_GET_FSM_MON_SEL(x) \
+ (((x) >> BIT_SHIFT_FSM_MON_SEL) & BIT_MASK_FSM_MON_SEL)
+#define BIT_SET_FSM_MON_SEL(x, v) \
+ (BIT_CLEAR_FSM_MON_SEL(x) | BIT_FSM_MON_SEL(v))
-#define BIT_SHIFT_DIVN_SDM 3
-#define BIT_MASK_DIVN_SDM 0x3f
-#define BIT_DIVN_SDM(x) (((x) & BIT_MASK_DIVN_SDM) << BIT_SHIFT_DIVN_SDM)
-#define BIT_GET_DIVN_SDM(x) (((x) >> BIT_SHIFT_DIVN_SDM) & BIT_MASK_DIVN_SDM)
+#define BIT_DOP_ELDO BIT(23)
+#define BIT_FSM_MON_UPD BIT(15)
+#define BIT_SHIFT_FSM_PAR 0
+#define BIT_MASK_FSM_PAR 0x7fff
+#define BIT_FSM_PAR(x) (((x) & BIT_MASK_FSM_PAR) << BIT_SHIFT_FSM_PAR)
+#define BITS_FSM_PAR (BIT_MASK_FSM_PAR << BIT_SHIFT_FSM_PAR)
+#define BIT_CLEAR_FSM_PAR(x) ((x) & (~BITS_FSM_PAR))
+#define BIT_GET_FSM_PAR(x) (((x) >> BIT_SHIFT_FSM_PAR) & BIT_MASK_FSM_PAR)
+#define BIT_SET_FSM_PAR(x, v) (BIT_CLEAR_FSM_PAR(x) | BIT_FSM_PAR(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_AFE_CTRL6 (Offset 0x00A4) */
+#define BIT_SHIFT_TSFT_SEL_V1 0
+#define BIT_MASK_TSFT_SEL_V1 0x7
+#define BIT_TSFT_SEL_V1(x) \
+ (((x) & BIT_MASK_TSFT_SEL_V1) << BIT_SHIFT_TSFT_SEL_V1)
+#define BITS_TSFT_SEL_V1 (BIT_MASK_TSFT_SEL_V1 << BIT_SHIFT_TSFT_SEL_V1)
+#define BIT_CLEAR_TSFT_SEL_V1(x) ((x) & (~BITS_TSFT_SEL_V1))
+#define BIT_GET_TSFT_SEL_V1(x) \
+ (((x) >> BIT_SHIFT_TSFT_SEL_V1) & BIT_MASK_TSFT_SEL_V1)
+#define BIT_SET_TSFT_SEL_V1(x, v) \
+ (BIT_CLEAR_TSFT_SEL_V1(x) | BIT_TSFT_SEL_V1(v))
-/* 2 REG_AFE_CTRL5 (Offset 0x0094) */
+#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_DITHER_SDM_V2 0
-#define BIT_MASK_DITHER_SDM_V2 0x7
-#define BIT_DITHER_SDM_V2(x) (((x) & BIT_MASK_DITHER_SDM_V2) << BIT_SHIFT_DITHER_SDM_V2)
-#define BIT_GET_DITHER_SDM_V2(x) (((x) >> BIT_SHIFT_DITHER_SDM_V2) & BIT_MASK_DITHER_SDM_V2)
+/* 2 REG_AFE_CTRL6 (Offset 0x00A4) */
+#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1 0
+#define BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1 0x7
+#define BIT_BB_DBG_SEL_AFE_SDM_BIT3_1(x) \
+ (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1) \
+ << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1)
+#define BITS_BB_DBG_SEL_AFE_SDM_BIT3_1 \
+ (BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1 \
+ << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1)
+#define BIT_CLEAR_BB_DBG_SEL_AFE_SDM_BIT3_1(x) \
+ ((x) & (~BITS_BB_DBG_SEL_AFE_SDM_BIT3_1))
+#define BIT_GET_BB_DBG_SEL_AFE_SDM_BIT3_1(x) \
+ (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1) & \
+ BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1)
+#define BIT_SET_BB_DBG_SEL_AFE_SDM_BIT3_1(x, v) \
+ (BIT_CLEAR_BB_DBG_SEL_AFE_SDM_BIT3_1(x) | \
+ BIT_BB_DBG_SEL_AFE_SDM_BIT3_1(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_PMC_DBG_CTRL1 (Offset 0x00A8) */
+#define BIT_BT_INT_EN BIT(31)
-/* 2 REG_GPIO_DEBOUNCE_CTRL (Offset 0x0098) */
+#define BIT_SHIFT_RD_WR_WIFI_BT_INFO 16
+#define BIT_MASK_RD_WR_WIFI_BT_INFO 0x7fff
+#define BIT_RD_WR_WIFI_BT_INFO(x) \
+ (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO) << BIT_SHIFT_RD_WR_WIFI_BT_INFO)
+#define BITS_RD_WR_WIFI_BT_INFO \
+ (BIT_MASK_RD_WR_WIFI_BT_INFO << BIT_SHIFT_RD_WR_WIFI_BT_INFO)
+#define BIT_CLEAR_RD_WR_WIFI_BT_INFO(x) ((x) & (~BITS_RD_WR_WIFI_BT_INFO))
+#define BIT_GET_RD_WR_WIFI_BT_INFO(x) \
+ (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO) & BIT_MASK_RD_WR_WIFI_BT_INFO)
+#define BIT_SET_RD_WR_WIFI_BT_INFO(x, v) \
+ (BIT_CLEAR_RD_WR_WIFI_BT_INFO(x) | BIT_RD_WR_WIFI_BT_INFO(v))
-#define BIT_WLGP_DBC1EN BIT(15)
+#endif
-#define BIT_SHIFT_WLGP_DBC1 8
-#define BIT_MASK_WLGP_DBC1 0xf
-#define BIT_WLGP_DBC1(x) (((x) & BIT_MASK_WLGP_DBC1) << BIT_SHIFT_WLGP_DBC1)
-#define BIT_GET_WLGP_DBC1(x) (((x) >> BIT_SHIFT_WLGP_DBC1) & BIT_MASK_WLGP_DBC1)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_WLGP_DBC0EN BIT(7)
+/* 2 REG_PMC_DBG_CTRL1 (Offset 0x00A8) */
-#define BIT_SHIFT_WLGP_DBC0 0
-#define BIT_MASK_WLGP_DBC0 0xf
-#define BIT_WLGP_DBC0(x) (((x) & BIT_MASK_WLGP_DBC0) << BIT_SHIFT_WLGP_DBC0)
-#define BIT_GET_WLGP_DBC0(x) (((x) >> BIT_SHIFT_WLGP_DBC0) & BIT_MASK_WLGP_DBC0)
+#define BIT_PMC_WR_OVF BIT(8)
+#define BIT_SHIFT_WLPMC_ERRINT 0
+#define BIT_MASK_WLPMC_ERRINT 0xff
+#define BIT_WLPMC_ERRINT(x) \
+ (((x) & BIT_MASK_WLPMC_ERRINT) << BIT_SHIFT_WLPMC_ERRINT)
+#define BITS_WLPMC_ERRINT (BIT_MASK_WLPMC_ERRINT << BIT_SHIFT_WLPMC_ERRINT)
+#define BIT_CLEAR_WLPMC_ERRINT(x) ((x) & (~BITS_WLPMC_ERRINT))
+#define BIT_GET_WLPMC_ERRINT(x) \
+ (((x) >> BIT_SHIFT_WLPMC_ERRINT) & BIT_MASK_WLPMC_ERRINT)
+#define BIT_SET_WLPMC_ERRINT(x, v) \
+ (BIT_CLEAR_WLPMC_ERRINT(x) | BIT_WLPMC_ERRINT(v))
-/* 2 REG_RPWM2 (Offset 0x009C) */
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
+/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */
-#define BIT_SHIFT_RPWM2 16
-#define BIT_MASK_RPWM2 0xffff
-#define BIT_RPWM2(x) (((x) & BIT_MASK_RPWM2) << BIT_SHIFT_RPWM2)
-#define BIT_GET_RPWM2(x) (((x) >> BIT_SHIFT_RPWM2) & BIT_MASK_RPWM2)
+#define BIT_SHIFT_SEL_V 30
+#define BIT_MASK_SEL_V 0x3
+#define BIT_SEL_V(x) (((x) & BIT_MASK_SEL_V) << BIT_SHIFT_SEL_V)
+#define BITS_SEL_V (BIT_MASK_SEL_V << BIT_SHIFT_SEL_V)
+#define BIT_CLEAR_SEL_V(x) ((x) & (~BITS_SEL_V))
+#define BIT_GET_SEL_V(x) (((x) >> BIT_SHIFT_SEL_V) & BIT_MASK_SEL_V)
+#define BIT_SET_SEL_V(x, v) (BIT_CLEAR_SEL_V(x) | BIT_SEL_V(v))
+#define BIT_SEL_LDO_PC BIT(29)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#define BIT_SHIFT_CK_MON_SEL_V2 26
+#define BIT_MASK_CK_MON_SEL_V2 0x7
+#define BIT_CK_MON_SEL_V2(x) \
+ (((x) & BIT_MASK_CK_MON_SEL_V2) << BIT_SHIFT_CK_MON_SEL_V2)
+#define BITS_CK_MON_SEL_V2 (BIT_MASK_CK_MON_SEL_V2 << BIT_SHIFT_CK_MON_SEL_V2)
+#define BIT_CLEAR_CK_MON_SEL_V2(x) ((x) & (~BITS_CK_MON_SEL_V2))
+#define BIT_GET_CK_MON_SEL_V2(x) \
+ (((x) >> BIT_SHIFT_CK_MON_SEL_V2) & BIT_MASK_CK_MON_SEL_V2)
+#define BIT_SET_CK_MON_SEL_V2(x, v) \
+ (BIT_CLEAR_CK_MON_SEL_V2(x) | BIT_CK_MON_SEL_V2(v))
+#endif
-/* 2 REG_SYSON_FSM_MON (Offset 0x00A0) */
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */
+
+#define BIT_SHIFT_CK_MON_SEL 26
+#define BIT_MASK_CK_MON_SEL 0x7
+#define BIT_CK_MON_SEL(x) (((x) & BIT_MASK_CK_MON_SEL) << BIT_SHIFT_CK_MON_SEL)
+#define BITS_CK_MON_SEL (BIT_MASK_CK_MON_SEL << BIT_SHIFT_CK_MON_SEL)
+#define BIT_CLEAR_CK_MON_SEL(x) ((x) & (~BITS_CK_MON_SEL))
+#define BIT_GET_CK_MON_SEL(x) \
+ (((x) >> BIT_SHIFT_CK_MON_SEL) & BIT_MASK_CK_MON_SEL)
+#define BIT_SET_CK_MON_SEL(x, v) (BIT_CLEAR_CK_MON_SEL(x) | BIT_CK_MON_SEL(v))
-#define BIT_SHIFT_FSM_MON_SEL 24
-#define BIT_MASK_FSM_MON_SEL 0x7
-#define BIT_FSM_MON_SEL(x) (((x) & BIT_MASK_FSM_MON_SEL) << BIT_SHIFT_FSM_MON_SEL)
-#define BIT_GET_FSM_MON_SEL(x) (((x) >> BIT_SHIFT_FSM_MON_SEL) & BIT_MASK_FSM_MON_SEL)
+#endif
-#define BIT_DOP_ELDO BIT(23)
-#define BIT_FSM_MON_UPD BIT(15)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_FSM_PAR 0
-#define BIT_MASK_FSM_PAR 0x7fff
-#define BIT_FSM_PAR(x) (((x) & BIT_MASK_FSM_PAR) << BIT_SHIFT_FSM_PAR)
-#define BIT_GET_FSM_PAR(x) (((x) >> BIT_SHIFT_FSM_PAR) & BIT_MASK_FSM_PAR)
+/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */
+#define BIT_CK_MON_EN BIT(25)
+#define BIT_FREF_EDGE BIT(24)
+#define BIT_CK320M_EN BIT(23)
+#define BIT_CK_5M_EN BIT(22)
+#define BIT_TESTEN BIT(21)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_HIMR0 (Offset 0x00B0) */
+#define BIT_TIMEOUT_INTERRUPT2_MASK BIT(31)
-/* 2 REG_AFE_CTRL6 (Offset 0x00A4) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_TSFT_SEL_V1 0
-#define BIT_MASK_TSFT_SEL_V1 0x7
-#define BIT_TSFT_SEL_V1(x) (((x) & BIT_MASK_TSFT_SEL_V1) << BIT_SHIFT_TSFT_SEL_V1)
-#define BIT_GET_TSFT_SEL_V1(x) (((x) >> BIT_SHIFT_TSFT_SEL_V1) & BIT_MASK_TSFT_SEL_V1)
+/* 2 REG_HIMR0 (Offset 0x00B0) */
+#define BIT_PSTIMER_2_MSK BIT(31)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_HIMR0 (Offset 0x00B0) */
+#define BIT_TIMEOUT_INTERRUTP1_MASK BIT(30)
-/* 2 REG_AFE_CTRL6 (Offset 0x00A4) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1 0
-#define BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1 0x7
-#define BIT_BB_DBG_SEL_AFE_SDM_BIT3_1(x) (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1) << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1)
-#define BIT_GET_BB_DBG_SEL_AFE_SDM_BIT3_1(x) (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1)
+/* 2 REG_HIMR0 (Offset 0x00B0) */
+#define BIT_PSTIMER_1_MSK BIT(30)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_HIMR0 (Offset 0x00B0) */
+#define BIT_PSTIMEOUT_MSK BIT(29)
-/* 2 REG_PMC_DBG_CTRL1 (Offset 0x00A8) */
+#endif
-#define BIT_BT_INT_EN BIT(31)
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_RD_WR_WIFI_BT_INFO 16
-#define BIT_MASK_RD_WR_WIFI_BT_INFO 0x7fff
-#define BIT_RD_WR_WIFI_BT_INFO(x) (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO) << BIT_SHIFT_RD_WR_WIFI_BT_INFO)
-#define BIT_GET_RD_WR_WIFI_BT_INFO(x) (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO) & BIT_MASK_RD_WR_WIFI_BT_INFO)
+/* 2 REG_HIMR0 (Offset 0x00B0) */
+#define BIT_PSTIMER_0_MSK BIT(29)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_HIMR0 (Offset 0x00B0) */
+#define BIT_GTINT4_MSK BIT(28)
+#define BIT_GTINT4 BIT(28)
+#define BIT_GTINT3_MSK BIT(27)
+#define BIT_GTINT3 BIT(27)
+#define BIT_TXBCN0ERR_MSK BIT(26)
+#define BIT_TXBCN0ERR BIT(26)
+#define BIT_TXBCN0OK_MSK BIT(25)
+#define BIT_TXBCN0OK BIT(25)
+#define BIT_TSF_BIT32_TOGGLE_MSK BIT(24)
+#define BIT_TSF_BIT32_TOGGLE BIT(24)
-/* 2 REG_PMC_DBG_CTRL1 (Offset 0x00A8) */
+#endif
-#define BIT_PMC_WR_OVF BIT(8)
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_WLPMC_ERRINT 0
-#define BIT_MASK_WLPMC_ERRINT 0xff
-#define BIT_WLPMC_ERRINT(x) (((x) & BIT_MASK_WLPMC_ERRINT) << BIT_SHIFT_WLPMC_ERRINT)
-#define BIT_GET_WLPMC_ERRINT(x) (((x) >> BIT_SHIFT_WLPMC_ERRINT) & BIT_MASK_WLPMC_ERRINT)
+/* 2 REG_HIMR0 (Offset 0x00B0) */
+#define BIT_TXDMA_START_INT_MSK BIT(23)
+#define BIT_TXDMA_STOP_INT_MSK BIT(22)
+#define BIT_HISR7_IND_MSK BIT(21)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_HIMR0 (Offset 0x00B0) */
+#define BIT_BCNDMAINT0_MSK BIT(20)
+#define BIT_BCNDMAINT0 BIT(20)
-/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_SEL_V 30
-#define BIT_MASK_SEL_V 0x3
-#define BIT_SEL_V(x) (((x) & BIT_MASK_SEL_V) << BIT_SHIFT_SEL_V)
-#define BIT_GET_SEL_V(x) (((x) >> BIT_SHIFT_SEL_V) & BIT_MASK_SEL_V)
+/* 2 REG_HIMR0 (Offset 0x00B0) */
+#define BIT_HISR6_IND_MSK BIT(19)
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_HIMR0 (Offset 0x00B0) */
+#define BIT_HISR5_MSK BIT(18)
-/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */
+#endif
-#define BIT_TXFIFO_TH_INT BIT(30)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_HIMR0 (Offset 0x00B0) */
+#define BIT_HISR5_IND_MSK BIT(18)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8198F_SUPPORT)
-/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */
+/* 2 REG_HIMR0 (Offset 0x00B0) */
-#define BIT_SEL_LDO_PC BIT(29)
+#define BIT_HISR4_MSK BIT(17)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_HIMR0 (Offset 0x00B0) */
+#define BIT_HISR4_IND_MSK BIT(17)
-/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_CK_MON_SEL_V2 26
-#define BIT_MASK_CK_MON_SEL_V2 0x7
-#define BIT_CK_MON_SEL_V2(x) (((x) & BIT_MASK_CK_MON_SEL_V2) << BIT_SHIFT_CK_MON_SEL_V2)
-#define BIT_GET_CK_MON_SEL_V2(x) (((x) >> BIT_SHIFT_CK_MON_SEL_V2) & BIT_MASK_CK_MON_SEL_V2)
+/* 2 REG_HIMR0 (Offset 0x00B0) */
+#define BIT_BCNDERR0_MSK BIT(16)
+#define BIT_BCNDERR0 BIT(16)
+#define BIT_HSISR_IND_ON_INT_MSK BIT(15)
+#define BIT_HSISR_IND_ON_INT BIT(15)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_HIMR0 (Offset 0x00B0) */
+#define BIT_BCNDMAINT_E_MSK BIT(14)
-/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_CK_MON_SEL 26
-#define BIT_MASK_CK_MON_SEL 0x7
-#define BIT_CK_MON_SEL(x) (((x) & BIT_MASK_CK_MON_SEL) << BIT_SHIFT_CK_MON_SEL)
-#define BIT_GET_CK_MON_SEL(x) (((x) >> BIT_SHIFT_CK_MON_SEL) & BIT_MASK_CK_MON_SEL)
+/* 2 REG_HIMR0 (Offset 0x00B0) */
+#define BIT_HISR3_IND_INT_MSK BIT(14)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_HIMR0 (Offset 0x00B0) */
+#define BIT_HISR3_IND_MSK BIT(14)
-/* 2 REG_AFE_CTRL7 (Offset 0x00AC) */
+#endif
-#define BIT_CK_MON_EN BIT(25)
-#define BIT_FREF_EDGE BIT(24)
-#define BIT_CK320M_EN BIT(23)
-#define BIT_CK_5M_EN BIT(22)
-#define BIT_TESTEN BIT(21)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
-#endif
+/* 2 REG_HIMR0 (Offset 0x00B0) */
+#define BIT_HISR2_IND_INT_MSK BIT(13)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_HIMR0 (Offset 0x00B0) */
-#define BIT_TIMEOUT_INTERRUPT2_MASK BIT(31)
-#define BIT_TIMEOUT_INTERRUTP1_MASK BIT(30)
-#define BIT_PSTIMEOUT_MSK BIT(29)
-#define BIT_GTINT4_MSK BIT(28)
-#define BIT_GTINT3_MSK BIT(27)
-#define BIT_TXBCN0ERR_MSK BIT(26)
-#define BIT_TXBCN0OK_MSK BIT(25)
-#define BIT_TSF_BIT32_TOGGLE_MSK BIT(24)
-#define BIT_BCNDMAINT0_MSK BIT(20)
-#define BIT_BCNDERR0_MSK BIT(16)
-#define BIT_HSISR_IND_ON_INT_MSK BIT(15)
+#define BIT_HISR2_IND_MSK BIT(13)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HIMR0 (Offset 0x00B0) */
+
+#define BIT_CTWEND_MSK BIT(12)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_HIMR0 (Offset 0x00B0) */
-#define BIT_BCNDMAINT_E_MSK BIT(14)
+#define BIT_HISR1_IND_MSK BIT(11)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_HIMR0 (Offset 0x00B0) */
-#define BIT_HISR3_IND_INT_MSK BIT(14)
-#define BIT_HISR2_IND_INT_MSK BIT(13)
+#define BIT_HISR1_IND_INT_MSK BIT(11)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HIMR0 (Offset 0x00B0) */
+
+#define BIT_C2HCMD_MSK BIT(10)
+#define BIT_C2HCMD BIT(10)
+#define BIT_CPWM2_MSK BIT(9)
+#define BIT_CPWM2 BIT(9)
+#define BIT_CPWM_MSK BIT(8)
+#define BIT_CPWM BIT(8)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_HIMR0 (Offset 0x00B0) */
-#define BIT_CTWEND_MSK BIT(12)
-#define BIT_HISR1_IND_MSK BIT(11)
+#define BIT_HIGHDOK_MSK BIT(7)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_HIMR0 (Offset 0x00B0) */
+
+#define BIT_TXDMAOK_CHANNEL15_MSK BIT(7)
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_HIMR0 (Offset 0x00B0) */
-#define BIT_HISR1_IND_INT_MSK BIT(11)
+#define BIT_MGTDOK_MSK BIT(6)
#endif
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIMR0 (Offset 0x00B0) */
+
+#define BIT_TXDMAOK_CHANNEL14_MSK BIT(6)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_HIMR0 (Offset 0x00B0) */
-#define BIT_C2HCMD_MSK BIT(10)
-#define BIT_CPWM2_MSK BIT(9)
-#define BIT_CPWM_MSK BIT(8)
-#define BIT_HIGHDOK_MSK BIT(7)
-#define BIT_MGTDOK_MSK BIT(6)
-#define BIT_BKDOK_MSK BIT(5)
-#define BIT_BEDOK_MSK BIT(4)
-#define BIT_VIDOK_MSK BIT(3)
-#define BIT_VODOK_MSK BIT(2)
-#define BIT_RDU_MSK BIT(1)
-#define BIT_RXOK_MSK BIT(0)
+#define BIT_BKDOK_MSK BIT(5)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_HIMR0 (Offset 0x00B0) */
+#define BIT_TXDMAOK_CHANNEL3_MSK BIT(5)
-/* 2 REG_HISR0 (Offset 0x00B4) */
+#endif
-#define BIT_PSTIMEOUT2 BIT(31)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_HIMR0 (Offset 0x00B0) */
+#define BIT_BEDOK_MSK BIT(4)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_HISR0 (Offset 0x00B4) */
+/* 2 REG_HIMR0 (Offset 0x00B0) */
-#define BIT_TIMEOUT_INTERRUPT2 BIT(31)
+#define BIT_TXDMAOK_CHANNEL2_MSK BIT(4)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_HIMR0 (Offset 0x00B0) */
+#define BIT_VIDOK_MSK BIT(3)
-/* 2 REG_HISR0 (Offset 0x00B4) */
+#endif
-#define BIT_PSTIMEOUT1 BIT(30)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_HIMR0 (Offset 0x00B0) */
+#define BIT_TXDMAOK_CHANNEL1_MSK BIT(3)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_HISR0 (Offset 0x00B4) */
+/* 2 REG_HIMR0 (Offset 0x00B0) */
-#define BIT_TIMEOUT_INTERRUTP1 BIT(30)
+#define BIT_VODOK_MSK BIT(2)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_HIMR0 (Offset 0x00B0) */
+#define BIT_TXDMAOK_CHANNEL0_MSK BIT(2)
-/* 2 REG_HISR0 (Offset 0x00B4) */
+#endif
-#define BIT_PSTIMEOUT BIT(29)
-#define BIT_GTINT4 BIT(28)
-#define BIT_GTINT3 BIT(27)
-#define BIT_TXBCN0ERR BIT(26)
-#define BIT_TXBCN0OK BIT(25)
-#define BIT_TSF_BIT32_TOGGLE BIT(24)
-#define BIT_BCNDMAINT0 BIT(20)
-#define BIT_BCNDERR0 BIT(16)
-#define BIT_HSISR_IND_ON_INT BIT(15)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_HIMR0 (Offset 0x00B0) */
+#define BIT_RDU_MSK BIT(1)
+#define BIT_RDU BIT(1)
+#define BIT_RXOK_MSK BIT(0)
+#define BIT_RXOK BIT(0)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_HISR0 (Offset 0x00B4) */
-#define BIT_BCNDMAINT_E BIT(14)
+#define BIT_PSTIMEOUT2 BIT(31)
+#define BIT_PSTIMEOUT1 BIT(30)
+#define BIT_PSTIMEOUT BIT(29)
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
+#if (HALMAC_8198F_SUPPORT)
/* 2 REG_HISR0 (Offset 0x00B4) */
-#define BIT_HISR3_IND_INT BIT(14)
-#define BIT_HISR2_IND_INT BIT(13)
+#define BIT_HISR5_IND_INT BIT(18)
+#define BIT_HISR4_IND_INT BIT(17)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_HISR0 (Offset 0x00B4) */
-#define BIT_CTWEND BIT(12)
+#define BIT_BCNDMAINT_E BIT(14)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
/* 2 REG_HISR0 (Offset 0x00B4) */
-#define BIT_HISR1_IND_INT BIT(11)
-#define BIT_C2HCMD BIT(10)
-#define BIT_CPWM2 BIT(9)
-#define BIT_CPWM BIT(8)
-#define BIT_HIGHDOK BIT(7)
-#define BIT_MGTDOK BIT(6)
-#define BIT_BKDOK BIT(5)
-#define BIT_BEDOK BIT(4)
-#define BIT_VIDOK BIT(3)
-#define BIT_VODOK BIT(2)
-#define BIT_RDU BIT(1)
-#define BIT_RXOK BIT(0)
+#define BIT_HISR3_IND_INT BIT(14)
+#define BIT_HISR2_IND_INT BIT(13)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_HISR0 (Offset 0x00B4) */
+#define BIT_CTWEND BIT(12)
-/* 2 REG_HIMR1 (Offset 0x00B8) */
+#endif
-#define BIT_BTON_STS_UPDATE_MSK BIT(29)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_HISR0 (Offset 0x00B4) */
+#define BIT_HISR1_IND_INT BIT(11)
+#define BIT_HIGHDOK BIT(7)
+#define BIT_MGTDOK BIT(6)
+#define BIT_BKDOK BIT(5)
+#define BIT_BEDOK BIT(4)
+#define BIT_VIDOK BIT(3)
+#define BIT_VODOK BIT(2)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8198F_SUPPORT)
/* 2 REG_HIMR1 (Offset 0x00B8) */
-#define BIT_BTON_STS_UPDATE_MASK BIT(29)
+#define BIT_PRETXERR_HANDLE_MSK BIT(31)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_HIMR1 (Offset 0x00B8) */
-#define BIT_MCU_ERR_MASK BIT(28)
+#define BIT_PRE_TX_ERR_INT_MSK BIT(31)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_HIMR1 (Offset 0x00B8) */
-#define BIT_BCNDMAINT7_MSK BIT(27)
+#define BIT_BTON_STS_UPDATE_INT BIT(29)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_HIMR1 (Offset 0x00B8) */
-#define BIT_BCNDMAINT7__MSK BIT(27)
+#define BIT_BTON_STS_UPDATE_MSK BIT(29)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_HIMR1 (Offset 0x00B8) */
-#define BIT_BCNDMAINT6_MSK BIT(26)
+#define BIT_BTON_STS_UPDATE_MASK BIT(29)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_HIMR1 (Offset 0x00B8) */
-#define BIT_BCNDMAINT6__MSK BIT(26)
+#define BIT_MCU_ERR_MASK BIT(28)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_HIMR1 (Offset 0x00B8) */
-#define BIT_BCNDMAINT5_MSK BIT(25)
+#define BIT_BCNDMAINT7 BIT(27)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_HIMR1 (Offset 0x00B8) */
-#define BIT_BCNDMAINT5__MSK BIT(25)
+#define BIT_BCNDMAINT7_MSK BIT(27)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_HIMR1 (Offset 0x00B8) */
-#define BIT_BCNDMAINT4_MSK BIT(24)
+#define BIT_BCNDMAINT7__MSK BIT(27)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_HIMR1 (Offset 0x00B8) */
-#define BIT_BCNDMAINT4__MSK BIT(24)
+#define BIT_BCNDMAINT6 BIT(26)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_HIMR1 (Offset 0x00B8) */
-#define BIT_BCNDMAINT3_MSK BIT(23)
-#define BIT_BCNDMAINT2_MSK BIT(22)
-#define BIT_BCNDMAINT1_MSK BIT(21)
-#define BIT_BCNDERR7_MSK BIT(20)
-#define BIT_BCNDERR6_MSK BIT(19)
-#define BIT_BCNDERR5_MSK BIT(18)
-#define BIT_BCNDERR4_MSK BIT(17)
-#define BIT_BCNDERR3_MSK BIT(16)
-#define BIT_BCNDERR2_MSK BIT(15)
-#define BIT_BCNDERR1_MSK BIT(14)
+#define BIT_BCNDMAINT6_MSK BIT(26)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_HIMR1 (Offset 0x00B8) */
-#define BIT_ATIMEND_E_MSK BIT(13)
+#define BIT_BCNDMAINT6__MSK BIT(26)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_HIMR1 (Offset 0x00B8) */
-#define BIT_ATIMEND_MSK BIT(12)
+#define BIT_BCNDMAINT5 BIT(25)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_HIMR1 (Offset 0x00B8) */
-#define BIT_ATIMEND__MSK BIT(12)
+#define BIT_BCNDMAINT5_MSK BIT(25)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_HIMR1 (Offset 0x00B8) */
-#define BIT_TXERR_MSK BIT(11)
-#define BIT_RXERR_MSK BIT(10)
-#define BIT_TXFOVW_MSK BIT(9)
-#define BIT_FOVW_MSK BIT(8)
+#define BIT_BCNDMAINT5__MSK BIT(25)
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_HIMR1 (Offset 0x00B8) */
-#define BIT_LD_B12V_EN_V1 BIT(7)
+#define BIT_BCNDMAINT4 BIT(24)
#endif
-
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_HIMR1 (Offset 0x00B8) */
-#define BIT_CPU_MGQ_TXDONE_MSK BIT(5)
-#define BIT_PS_TIMER_C_MSK BIT(4)
-#define BIT_PS_TIMER_B_MSK BIT(3)
-#define BIT_PS_TIMER_A_MSK BIT(2)
-#define BIT_CPUMGQ_TX_TIMER_MSK BIT(1)
+#define BIT_BCNDMAINT4_MSK BIT(24)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_HISR1 (Offset 0x00BC) */
+/* 2 REG_HIMR1 (Offset 0x00B8) */
-#define BIT_BTON_STS_UPDATE_INT BIT(29)
+#define BIT_BCNDMAINT4__MSK BIT(24)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_HIMR1 (Offset 0x00B8) */
+#define BIT_BCNDMAINT3_MSK BIT(23)
+#define BIT_BCNDMAINT3 BIT(23)
+#define BIT_BCNDMAINT2_MSK BIT(22)
+#define BIT_BCNDMAINT2 BIT(22)
+#define BIT_BCNDMAINT1_MSK BIT(21)
+#define BIT_BCNDMAINT1 BIT(21)
+#define BIT_BCNDERR7_MSK BIT(20)
+#define BIT_BCNDERR7 BIT(20)
+#define BIT_BCNDERR6_MSK BIT(19)
+#define BIT_BCNDERR6 BIT(19)
+#define BIT_BCNDERR5_MSK BIT(18)
+#define BIT_BCNDERR5 BIT(18)
+#define BIT_BCNDERR4_MSK BIT(17)
+#define BIT_BCNDERR4 BIT(17)
+#define BIT_BCNDERR3_MSK BIT(16)
+#define BIT_BCNDERR3 BIT(16)
+#define BIT_BCNDERR2_MSK BIT(15)
+#define BIT_BCNDERR2 BIT(15)
+#define BIT_BCNDERR1_MSK BIT(14)
+#define BIT_BCNDERR1 BIT(14)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_HISR1 (Offset 0x00BC) */
+/* 2 REG_HIMR1 (Offset 0x00B8) */
-#define BIT_MCU_ERR BIT(28)
+#define BIT_ATIMEND_E_MSK BIT(13)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_HIMR1 (Offset 0x00B8) */
+#define BIT_ATIMEND_MSK BIT(12)
-/* 2 REG_HISR1 (Offset 0x00BC) */
+#endif
-#define BIT_BCNDMAINT7 BIT(27)
-#define BIT_BCNDMAINT6 BIT(26)
-#define BIT_BCNDMAINT5 BIT(25)
-#define BIT_BCNDMAINT4 BIT(24)
-#define BIT_BCNDMAINT3 BIT(23)
-#define BIT_BCNDMAINT2 BIT(22)
-#define BIT_BCNDMAINT1 BIT(21)
-#define BIT_BCNDERR7 BIT(20)
-#define BIT_BCNDERR6 BIT(19)
-#define BIT_BCNDERR5 BIT(18)
-#define BIT_BCNDERR4 BIT(17)
-#define BIT_BCNDERR3 BIT(16)
-#define BIT_BCNDERR2 BIT(15)
-#define BIT_BCNDERR1 BIT(14)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_HIMR1 (Offset 0x00B8) */
+#define BIT_ATIMEND__MSK BIT(12)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8822B_SUPPORT)
-/* 2 REG_HISR1 (Offset 0x00BC) */
+/* 2 REG_HIMR1 (Offset 0x00B8) */
-#define BIT_ATIMEND_E BIT(13)
+#define BIT_ATIMEND_E_V1_MSK BIT(12)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_HIMR1 (Offset 0x00B8) */
+#define BIT_TXERR_MSK BIT(11)
+#define BIT_TXERR_INT BIT(11)
+#define BIT_RXERR_MSK BIT(10)
+#define BIT_RXERR_INT BIT(10)
+#define BIT_TXFOVW_MSK BIT(9)
+#define BIT_TXFOVW BIT(9)
+#define BIT_FOVW_MSK BIT(8)
+#define BIT_FOVW BIT(8)
-/* 2 REG_HISR1 (Offset 0x00BC) */
+#endif
-#define BIT_ATIMEND BIT(12)
-#define BIT_TXERR_INT BIT(11)
-#define BIT_RXERR_INT BIT(10)
-#define BIT_TXFOVW BIT(9)
-#define BIT_FOVW BIT(8)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#endif
+/* 2 REG_HIMR1 (Offset 0x00B8) */
+#define BIT_LD_B12V_EN_V1 BIT(7)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_HISR1 (Offset 0x00BC) */
+/* 2 REG_HIMR1 (Offset 0x00B8) */
-#define BIT_CPU_MGQ_TXDONE BIT(5)
-#define BIT_PS_TIMER_C BIT(4)
-#define BIT_PS_TIMER_B BIT(3)
-#define BIT_PS_TIMER_A BIT(2)
-#define BIT_CPUMGQ_TX_TIMER BIT(1)
+#define BIT_CPU_MGQ_EARLY_INT_MSK BIT(6)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_HIMR1 (Offset 0x00B8) */
+#define BIT_CPU_MGQ_TXDONE_MSK BIT(5)
+#define BIT_CPU_MGQ_TXDONE BIT(5)
-/* 2 REG_SDIO_ERR_RPT (Offset 0x102500C0) */
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIMR1 (Offset 0x00B8) */
-#define BIT_HR_FF_OVF BIT(6)
-#define BIT_HR_FF_UDN BIT(5)
-#define BIT_TXDMA_BUSY_ERR BIT(4)
-#define BIT_TXDMA_VLD_ERR BIT(3)
-#define BIT_QSEL_UNKOWN_ERR BIT(2)
-#define BIT_QSEL_MIS_ERR BIT(1)
+#define BIT_PSTIMER_5_MSK BIT(4)
#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_HIMR1 (Offset 0x00B8) */
+#define BIT_PS_TIMER_C_MSK BIT(4)
-/* 2 REG_DBG_PORT_SEL (Offset 0x00C0) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_DEBUG_ST 0
-#define BIT_MASK_DEBUG_ST 0xffffffffL
-#define BIT_DEBUG_ST(x) (((x) & BIT_MASK_DEBUG_ST) << BIT_SHIFT_DEBUG_ST)
-#define BIT_GET_DEBUG_ST(x) (((x) >> BIT_SHIFT_DEBUG_ST) & BIT_MASK_DEBUG_ST)
+/* 2 REG_HIMR1 (Offset 0x00B8) */
+#define BIT_PSTIMER_4_MSK BIT(3)
#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_HIMR1 (Offset 0x00B8) */
+#define BIT_PS_TIMER_B_MSK BIT(3)
-/* 2 REG_SDIO_ERR_RPT (Offset 0x102500C0) */
+#endif
-#define BIT_SDIO_OVERRD_ERR BIT(0)
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_SDIO_CMD_ERRCNT (Offset 0x102500C1) */
+/* 2 REG_HIMR1 (Offset 0x00B8) */
+#define BIT_PSTIMER_3_MSK BIT(2)
-#define BIT_SHIFT_CMD_CRC_ERR_CNT 0
-#define BIT_MASK_CMD_CRC_ERR_CNT 0xff
-#define BIT_CMD_CRC_ERR_CNT(x) (((x) & BIT_MASK_CMD_CRC_ERR_CNT) << BIT_SHIFT_CMD_CRC_ERR_CNT)
-#define BIT_GET_CMD_CRC_ERR_CNT(x) (((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT) & BIT_MASK_CMD_CRC_ERR_CNT)
+#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_SDIO_DATA_ERRCNT (Offset 0x102500C2) */
+/* 2 REG_HIMR1 (Offset 0x00B8) */
+#define BIT_PS_TIMER_A_MSK BIT(2)
-#define BIT_SHIFT_DATA_CRC_ERR_CNT 0
-#define BIT_MASK_DATA_CRC_ERR_CNT 0xff
-#define BIT_DATA_CRC_ERR_CNT(x) (((x) & BIT_MASK_DATA_CRC_ERR_CNT) << BIT_SHIFT_DATA_CRC_ERR_CNT)
-#define BIT_GET_DATA_CRC_ERR_CNT(x) (((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT) & BIT_MASK_DATA_CRC_ERR_CNT)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_HIMR1 (Offset 0x00B8) */
+#define BIT_CPUMGQ_TX_TIMER_MSK BIT(1)
+#define BIT_CPUMGQ_TX_TIMER BIT(1)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
+/* 2 REG_HIMR1 (Offset 0x00B8) */
-#define BIT_MAC_SOP BIT(25)
-#define BIT_LDO11_ST_EXT BIT(24)
-#define BIT_ANTSELB_S2 BIT(23)
-#define BIT_ANTSELB_S1 BIT(22)
-#define BIT_ANTSEL_S3 BIT(21)
-#define BIT_ANTSEL_S2 BIT(20)
+#define BIT_BB_STOPRX_INT_MSK BIT(0)
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_HISR1 (Offset 0x00BC) */
+#define BIT_PRETXERR_HANDLE_INT BIT(31)
-/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
+#endif
-#define BIT_USB3_USB2_TRANSITION BIT(20)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_HISR1 (Offset 0x00BC) */
+#define BIT_MCU_ERR BIT(28)
+#define BIT_ATIMEND_E BIT(13)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+#endif
+#if (HALMAC_8822B_SUPPORT)
-/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
+/* 2 REG_HISR1 (Offset 0x00BC) */
-#define BIT_ANTSEL_S1 BIT(19)
-#define BIT_FCSN_PU BIT(18)
+#define BIT_ATIMEND_E_V1_INT BIT(12)
#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_HISR1 (Offset 0x00BC) */
+#define BIT_PS_TIMER_C BIT(4)
+#define BIT_PS_TIMER_B BIT(3)
+#define BIT_PS_TIMER_A BIT(2)
-/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_USB23_SW_MODE_V1 18
-#define BIT_MASK_USB23_SW_MODE_V1 0x3
-#define BIT_USB23_SW_MODE_V1(x) (((x) & BIT_MASK_USB23_SW_MODE_V1) << BIT_SHIFT_USB23_SW_MODE_V1)
-#define BIT_GET_USB23_SW_MODE_V1(x) (((x) >> BIT_SHIFT_USB23_SW_MODE_V1) & BIT_MASK_USB23_SW_MODE_V1)
+/* 2 REG_SDIO_ERR_RPT (Offset 0x102500C0) */
+#define BIT_HR_FF_OVF BIT(6)
+#define BIT_HR_FF_UDN BIT(5)
+#define BIT_TXDMA_BUSY_ERR BIT(4)
+#define BIT_TXDMA_VLD_ERR BIT(3)
+#define BIT_QSEL_UNKNOWN_ERR BIT(2)
+#define BIT_QSEL_MIS_ERR BIT(1)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_DBG_PORT_SEL (Offset 0x00C0) */
+#define BIT_SHIFT_DEBUG_ST 0
+#define BIT_MASK_DEBUG_ST 0xffffffffL
+#define BIT_DEBUG_ST(x) (((x) & BIT_MASK_DEBUG_ST) << BIT_SHIFT_DEBUG_ST)
+#define BITS_DEBUG_ST (BIT_MASK_DEBUG_ST << BIT_SHIFT_DEBUG_ST)
+#define BIT_CLEAR_DEBUG_ST(x) ((x) & (~BITS_DEBUG_ST))
+#define BIT_GET_DEBUG_ST(x) (((x) >> BIT_SHIFT_DEBUG_ST) & BIT_MASK_DEBUG_ST)
+#define BIT_SET_DEBUG_ST(x, v) (BIT_CLEAR_DEBUG_ST(x) | BIT_DEBUG_ST(v))
-/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
+#endif
-#define BIT_KEEP_PAD BIT(17)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-#endif
+/* 2 REG_SDIO_ERR_RPT (Offset 0x102500C0) */
+#define BIT_SDIO_OVERRD_ERR BIT(0)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#define BIT_SHIFT_SDIO_DATA_REPLY_TIME 0
+#define BIT_MASK_SDIO_DATA_REPLY_TIME 0x7
+#define BIT_SDIO_DATA_REPLY_TIME(x) \
+ (((x) & BIT_MASK_SDIO_DATA_REPLY_TIME) \
+ << BIT_SHIFT_SDIO_DATA_REPLY_TIME)
+#define BITS_SDIO_DATA_REPLY_TIME \
+ (BIT_MASK_SDIO_DATA_REPLY_TIME << BIT_SHIFT_SDIO_DATA_REPLY_TIME)
+#define BIT_CLEAR_SDIO_DATA_REPLY_TIME(x) ((x) & (~BITS_SDIO_DATA_REPLY_TIME))
+#define BIT_GET_SDIO_DATA_REPLY_TIME(x) \
+ (((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME) & \
+ BIT_MASK_SDIO_DATA_REPLY_TIME)
+#define BIT_SET_SDIO_DATA_REPLY_TIME(x, v) \
+ (BIT_CLEAR_SDIO_DATA_REPLY_TIME(x) | BIT_SDIO_DATA_REPLY_TIME(v))
+#endif
-/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
+#if (HALMAC_8822C_SUPPORT)
-#define BIT_NO_PDN_CHIPOFF_V1 BIT(17)
+/* 2 REG_SDIO_DIOERR_RPT (Offset 0x102500C0) */
+
+#define BIT_SDIO_PAGE_ERR BIT(0)
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_SDIO_CMD_ERRCNT (Offset 0x102500C2) */
+#define BIT_SHIFT_CMD_CRC_ERR_CNT 0
+#define BIT_MASK_CMD_CRC_ERR_CNT 0xff
+#define BIT_CMD_CRC_ERR_CNT(x) \
+ (((x) & BIT_MASK_CMD_CRC_ERR_CNT) << BIT_SHIFT_CMD_CRC_ERR_CNT)
+#define BITS_CMD_CRC_ERR_CNT \
+ (BIT_MASK_CMD_CRC_ERR_CNT << BIT_SHIFT_CMD_CRC_ERR_CNT)
+#define BIT_CLEAR_CMD_CRC_ERR_CNT(x) ((x) & (~BITS_CMD_CRC_ERR_CNT))
+#define BIT_GET_CMD_CRC_ERR_CNT(x) \
+ (((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT) & BIT_MASK_CMD_CRC_ERR_CNT)
+#define BIT_SET_CMD_CRC_ERR_CNT(x, v) \
+ (BIT_CLEAR_CMD_CRC_ERR_CNT(x) | BIT_CMD_CRC_ERR_CNT(v))
-/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
+/* 2 REG_SDIO_DATA_ERRCNT (Offset 0x102500C3) */
-#define BIT_PAD_ALD_SKP BIT(16)
+#define BIT_SHIFT_DATA_CRC_ERR_CNT 0
+#define BIT_MASK_DATA_CRC_ERR_CNT 0xff
+#define BIT_DATA_CRC_ERR_CNT(x) \
+ (((x) & BIT_MASK_DATA_CRC_ERR_CNT) << BIT_SHIFT_DATA_CRC_ERR_CNT)
+#define BITS_DATA_CRC_ERR_CNT \
+ (BIT_MASK_DATA_CRC_ERR_CNT << BIT_SHIFT_DATA_CRC_ERR_CNT)
+#define BIT_CLEAR_DATA_CRC_ERR_CNT(x) ((x) & (~BITS_DATA_CRC_ERR_CNT))
+#define BIT_GET_DATA_CRC_ERR_CNT(x) \
+ (((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT) & BIT_MASK_DATA_CRC_ERR_CNT)
+#define BIT_SET_DATA_CRC_ERR_CNT(x, v) \
+ (BIT_CLEAR_DATA_CRC_ERR_CNT(x) | BIT_DATA_CRC_ERR_CNT(v))
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
+#define BIT_MAC_SOP BIT(25)
+#define BIT_LDO11_ST_EXT BIT(24)
+#define BIT_ANTSELB_S2 BIT(23)
+#define BIT_ANTSELB_S1 BIT(22)
+#define BIT_ANTSEL_S3 BIT(21)
+#define BIT_ANTSEL_S2 BIT(20)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
-#define BIT_RSM_EN_V1 BIT(16)
+#define BIT_USB3_USB2_TRANSITION BIT(20)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
-#define BIT_PAD_A_ANTSEL_E BIT(11)
-#define BIT_PAD_A_ANTSELB_E BIT(10)
-#define BIT_PAD_A_ANTSEL_O BIT(9)
-#define BIT_PAD_A_ANTSELB_O BIT(8)
+#define BIT_ANTSEL_S1 BIT(19)
+#define BIT_FCSN_PU BIT(18)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
-#define BIT_LD_B12V_EN BIT(7)
+#define BIT_SHIFT_USB23_SW_MODE_V1 18
+#define BIT_MASK_USB23_SW_MODE_V1 0x3
+#define BIT_USB23_SW_MODE_V1(x) \
+ (((x) & BIT_MASK_USB23_SW_MODE_V1) << BIT_SHIFT_USB23_SW_MODE_V1)
+#define BITS_USB23_SW_MODE_V1 \
+ (BIT_MASK_USB23_SW_MODE_V1 << BIT_SHIFT_USB23_SW_MODE_V1)
+#define BIT_CLEAR_USB23_SW_MODE_V1(x) ((x) & (~BITS_USB23_SW_MODE_V1))
+#define BIT_GET_USB23_SW_MODE_V1(x) \
+ (((x) >> BIT_SHIFT_USB23_SW_MODE_V1) & BIT_MASK_USB23_SW_MODE_V1)
+#define BIT_SET_USB23_SW_MODE_V1(x, v) \
+ (BIT_CLEAR_USB23_SW_MODE_V1(x) | BIT_USB23_SW_MODE_V1(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
-#define BIT_B15V_EN BIT(7)
+#define BIT_KEEP_PAD BIT(17)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
-#define BIT_EESK_IOSEL BIT(6)
+#define BIT_NO_PDN_CHIPOFF_V1 BIT(17)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
-#define BIT_EECS_IOSEL_V1 BIT(6)
+#define BIT_PAD_ALD_SKP BIT(16)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
-#define BIT_EESK_DATA_O BIT(5)
+#define BIT_RSM_EN_V1 BIT(16)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
-#define BIT_EECS_DATA_O_V1 BIT(5)
+#define BIT_PAD_A_ANTSEL_E BIT(11)
+#define BIT_PAD_A_ANTSELB_E BIT(10)
+#define BIT_PAD_A_ANTSEL_O BIT(9)
+#define BIT_PAD_A_ANTSELB_O BIT(8)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
-#define BIT_EESK_DATA_I BIT(4)
+#define BIT_LD_B12V_EN BIT(7)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
-#define BIT_EECS_DATA_I_V1 BIT(4)
+#define BIT_B15V_EN BIT(7)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
-#define BIT_EECS_IOSEL BIT(2)
+#define BIT_EESK_IOSEL BIT(6)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
-#define BIT_EESK_IOSEL_V1 BIT(2)
+#define BIT_EECS_IOSEL_V1 BIT(6)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
-#define BIT_EECS_DATA_O BIT(1)
+#define BIT_EESK_DATA_O BIT(5)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
-#define BIT_EESK_DATA_O_V1 BIT(1)
+#define BIT_EECS_DATA_O_V1 BIT(5)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
-#define BIT_EECS_DATA_I BIT(0)
+#define BIT_EESK_DATA_I BIT(4)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
-#define BIT_EESK_DATA_I_V1 BIT(0)
+#define BIT_EECS_DATA_I_V1 BIT(4)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
+#define BIT_EECS_IOSEL BIT(2)
-/* 2 REG_SDIO_CMD_ERR_CONTENT (Offset 0x102500C4) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_SDIO_CMD_ERR_CONTENT 0
-#define BIT_MASK_SDIO_CMD_ERR_CONTENT 0xffffffffffL
-#define BIT_SDIO_CMD_ERR_CONTENT(x) (((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT) << BIT_SHIFT_SDIO_CMD_ERR_CONTENT)
-#define BIT_GET_SDIO_CMD_ERR_CONTENT(x) (((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT) & BIT_MASK_SDIO_CMD_ERR_CONTENT)
+/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
+#define BIT_EESK_IOSEL_V1 BIT(2)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
+#define BIT_EECS_DATA_O BIT(1)
-/* 2 REG_MEM_RMC (Offset 0x00C8) */
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_MEM_RMV_SIGN BIT(31)
-#define BIT_MEM_RMV_2PRF1 BIT(29)
-#define BIT_MEM_RMV_2PRF0 BIT(28)
-#define BIT_MEM_RMV_1PRF1 BIT(27)
-#define BIT_MEM_RMV_1PRF0 BIT(26)
-#define BIT_MEM_RMV_1PSR BIT(25)
-#define BIT_MEM_RMV_ROM BIT(24)
+/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
+
+#define BIT_EESK_DATA_O_V1 BIT(1)
-#define BIT_SHIFT_MEM_RME_WL_V2 4
-#define BIT_MASK_MEM_RME_WL_V2 0x3f
-#define BIT_MEM_RME_WL_V2(x) (((x) & BIT_MASK_MEM_RME_WL_V2) << BIT_SHIFT_MEM_RME_WL_V2)
-#define BIT_GET_MEM_RME_WL_V2(x) (((x) >> BIT_SHIFT_MEM_RME_WL_V2) & BIT_MASK_MEM_RME_WL_V2)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_MEM_RME_HCI_V2 0
-#define BIT_MASK_MEM_RME_HCI_V2 0x1f
-#define BIT_MEM_RME_HCI_V2(x) (((x) & BIT_MASK_MEM_RME_HCI_V2) << BIT_SHIFT_MEM_RME_HCI_V2)
-#define BIT_GET_MEM_RME_HCI_V2(x) (((x) >> BIT_SHIFT_MEM_RME_HCI_V2) & BIT_MASK_MEM_RME_HCI_V2)
+/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
+#define BIT_EECS_DATA_I BIT(0)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_PAD_CTRL2 (Offset 0x00C4) */
+#define BIT_EESK_DATA_I_V1 BIT(0)
-/* 2 REG_SDIO_CRC_ERR_IDX (Offset 0x102500C9) */
+#endif
-#define BIT_D3_CRC_ERR BIT(4)
-#define BIT_D2_CRC_ERR BIT(3)
-#define BIT_D1_CRC_ERR BIT(2)
-#define BIT_D0_CRC_ERR BIT(1)
-#define BIT_CMD_CRC_ERR BIT(0)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_SDIO_DATA_CRC (Offset 0x102500CA) */
+/* 2 REG_SDIO_CMD_ERR_CONTENT (Offset 0x102500C4) */
+#define BIT_SHIFT_SDIO_CMD_ERR_CONTENT 0
+#define BIT_MASK_SDIO_CMD_ERR_CONTENT 0xffffffffffL
+#define BIT_SDIO_CMD_ERR_CONTENT(x) \
+ (((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT) \
+ << BIT_SHIFT_SDIO_CMD_ERR_CONTENT)
+#define BITS_SDIO_CMD_ERR_CONTENT \
+ (BIT_MASK_SDIO_CMD_ERR_CONTENT << BIT_SHIFT_SDIO_CMD_ERR_CONTENT)
+#define BIT_CLEAR_SDIO_CMD_ERR_CONTENT(x) ((x) & (~BITS_SDIO_CMD_ERR_CONTENT))
+#define BIT_GET_SDIO_CMD_ERR_CONTENT(x) \
+ (((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT) & \
+ BIT_MASK_SDIO_CMD_ERR_CONTENT)
+#define BIT_SET_SDIO_CMD_ERR_CONTENT(x, v) \
+ (BIT_CLEAR_SDIO_CMD_ERR_CONTENT(x) | BIT_SDIO_CMD_ERR_CONTENT(v))
-#define BIT_SHIFT_SDIO_DATA_CRC 0
-#define BIT_MASK_SDIO_DATA_CRC 0xff
-#define BIT_SDIO_DATA_CRC(x) (((x) & BIT_MASK_SDIO_DATA_CRC) << BIT_SHIFT_SDIO_DATA_CRC)
-#define BIT_GET_SDIO_DATA_CRC(x) (((x) >> BIT_SHIFT_SDIO_DATA_CRC) & BIT_MASK_SDIO_DATA_CRC)
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-/* 2 REG_SDIO_DATA_REPLY_TIME (Offset 0x102500CB) */
+/* 2 REG_MEM_RMC (Offset 0x00C8) */
+#define BIT_MEM_RMV_SIGN BIT(31)
+#define BIT_MEM_RMV_2PRF1 BIT(29)
+#define BIT_MEM_RMV_2PRF0 BIT(28)
+#define BIT_MEM_RMV_1PRF1 BIT(27)
+#define BIT_MEM_RMV_1PRF0 BIT(26)
+#define BIT_MEM_RMV_1PSR BIT(25)
+#define BIT_MEM_RMV_ROM BIT(24)
+
+#define BIT_SHIFT_MEM_RME_WL_V2 4
+#define BIT_MASK_MEM_RME_WL_V2 0x3f
+#define BIT_MEM_RME_WL_V2(x) \
+ (((x) & BIT_MASK_MEM_RME_WL_V2) << BIT_SHIFT_MEM_RME_WL_V2)
+#define BITS_MEM_RME_WL_V2 (BIT_MASK_MEM_RME_WL_V2 << BIT_SHIFT_MEM_RME_WL_V2)
+#define BIT_CLEAR_MEM_RME_WL_V2(x) ((x) & (~BITS_MEM_RME_WL_V2))
+#define BIT_GET_MEM_RME_WL_V2(x) \
+ (((x) >> BIT_SHIFT_MEM_RME_WL_V2) & BIT_MASK_MEM_RME_WL_V2)
+#define BIT_SET_MEM_RME_WL_V2(x, v) \
+ (BIT_CLEAR_MEM_RME_WL_V2(x) | BIT_MEM_RME_WL_V2(v))
+
+#define BIT_SHIFT_MEM_RME_HCI_V2 0
+#define BIT_MASK_MEM_RME_HCI_V2 0x1f
+#define BIT_MEM_RME_HCI_V2(x) \
+ (((x) & BIT_MASK_MEM_RME_HCI_V2) << BIT_SHIFT_MEM_RME_HCI_V2)
+#define BITS_MEM_RME_HCI_V2 \
+ (BIT_MASK_MEM_RME_HCI_V2 << BIT_SHIFT_MEM_RME_HCI_V2)
+#define BIT_CLEAR_MEM_RME_HCI_V2(x) ((x) & (~BITS_MEM_RME_HCI_V2))
+#define BIT_GET_MEM_RME_HCI_V2(x) \
+ (((x) >> BIT_SHIFT_MEM_RME_HCI_V2) & BIT_MASK_MEM_RME_HCI_V2)
+#define BIT_SET_MEM_RME_HCI_V2(x, v) \
+ (BIT_CLEAR_MEM_RME_HCI_V2(x) | BIT_MEM_RME_HCI_V2(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_SDIO_DATA_REPLY_TIME 0
-#define BIT_MASK_SDIO_DATA_REPLY_TIME 0x7
-#define BIT_SDIO_DATA_REPLY_TIME(x) (((x) & BIT_MASK_SDIO_DATA_REPLY_TIME) << BIT_SHIFT_SDIO_DATA_REPLY_TIME)
-#define BIT_GET_SDIO_DATA_REPLY_TIME(x) (((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME) & BIT_MASK_SDIO_DATA_REPLY_TIME)
+/* 2 REG_SDIO_CRC_ERR_IDX (Offset 0x102500C9) */
+#define BIT_D3_CRC_ERR BIT(4)
+#define BIT_D2_CRC_ERR BIT(3)
+#define BIT_D1_CRC_ERR BIT(2)
+#define BIT_D0_CRC_ERR BIT(1)
+#define BIT_CMD_CRC_ERR BIT(0)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_SDIO_DATA_CRC (Offset 0x102500CA) */
+#define BIT_SHIFT_SDIO_DATA_CRC 0
+#define BIT_MASK_SDIO_DATA_CRC 0xffff
+#define BIT_SDIO_DATA_CRC(x) \
+ (((x) & BIT_MASK_SDIO_DATA_CRC) << BIT_SHIFT_SDIO_DATA_CRC)
+#define BITS_SDIO_DATA_CRC (BIT_MASK_SDIO_DATA_CRC << BIT_SHIFT_SDIO_DATA_CRC)
+#define BIT_CLEAR_SDIO_DATA_CRC(x) ((x) & (~BITS_SDIO_DATA_CRC))
+#define BIT_GET_SDIO_DATA_CRC(x) \
+ (((x) >> BIT_SHIFT_SDIO_DATA_CRC) & BIT_MASK_SDIO_DATA_CRC)
+#define BIT_SET_SDIO_DATA_CRC(x, v) \
+ (BIT_CLEAR_SDIO_DATA_CRC(x) | BIT_SDIO_DATA_CRC(v))
-/* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_EFUSE_BURN_GNT 24
-#define BIT_MASK_EFUSE_BURN_GNT 0xff
-#define BIT_EFUSE_BURN_GNT(x) (((x) & BIT_MASK_EFUSE_BURN_GNT) << BIT_SHIFT_EFUSE_BURN_GNT)
-#define BIT_GET_EFUSE_BURN_GNT(x) (((x) >> BIT_SHIFT_EFUSE_BURN_GNT) & BIT_MASK_EFUSE_BURN_GNT)
+/* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */
+#define BIT_SHIFT_EFUSE_BURN_GNT 24
+#define BIT_MASK_EFUSE_BURN_GNT 0xff
+#define BIT_EFUSE_BURN_GNT(x) \
+ (((x) & BIT_MASK_EFUSE_BURN_GNT) << BIT_SHIFT_EFUSE_BURN_GNT)
+#define BITS_EFUSE_BURN_GNT \
+ (BIT_MASK_EFUSE_BURN_GNT << BIT_SHIFT_EFUSE_BURN_GNT)
+#define BIT_CLEAR_EFUSE_BURN_GNT(x) ((x) & (~BITS_EFUSE_BURN_GNT))
+#define BIT_GET_EFUSE_BURN_GNT(x) \
+ (((x) >> BIT_SHIFT_EFUSE_BURN_GNT) & BIT_MASK_EFUSE_BURN_GNT)
+#define BIT_SET_EFUSE_BURN_GNT(x, v) \
+ (BIT_CLEAR_EFUSE_BURN_GNT(x) | BIT_EFUSE_BURN_GNT(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */
+#define BIT_SHIFT_EFUSE_PG_PWD 24
+#define BIT_MASK_EFUSE_PG_PWD 0xff
+#define BIT_EFUSE_PG_PWD(x) \
+ (((x) & BIT_MASK_EFUSE_PG_PWD) << BIT_SHIFT_EFUSE_PG_PWD)
+#define BITS_EFUSE_PG_PWD (BIT_MASK_EFUSE_PG_PWD << BIT_SHIFT_EFUSE_PG_PWD)
+#define BIT_CLEAR_EFUSE_PG_PWD(x) ((x) & (~BITS_EFUSE_PG_PWD))
+#define BIT_GET_EFUSE_PG_PWD(x) \
+ (((x) >> BIT_SHIFT_EFUSE_PG_PWD) & BIT_MASK_EFUSE_PG_PWD)
+#define BIT_SET_EFUSE_PG_PWD(x, v) \
+ (BIT_CLEAR_EFUSE_PG_PWD(x) | BIT_EFUSE_PG_PWD(v))
-#define BIT_SHIFT_EFUSE_PG_PWD 24
-#define BIT_MASK_EFUSE_PG_PWD 0xff
-#define BIT_EFUSE_PG_PWD(x) (((x) & BIT_MASK_EFUSE_PG_PWD) << BIT_SHIFT_EFUSE_PG_PWD)
-#define BIT_GET_EFUSE_PG_PWD(x) (((x) >> BIT_SHIFT_EFUSE_PG_PWD) & BIT_MASK_EFUSE_PG_PWD)
-
-#define BIT_DBG_READ_EN BIT(16)
+#define BIT_DBG_READ_EN BIT(16)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */
-#define BIT_STOP_WL_PMC BIT(9)
-#define BIT_STOP_SYM_PMC BIT(8)
+#define BIT_STOP_WL_PMC BIT(9)
+#define BIT_STOP_SYM_PMC BIT(8)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */
+#define BIT_SHIFT_EDATA1_V1 8
+#define BIT_MASK_EDATA1_V1 0xff
+#define BIT_EDATA1_V1(x) (((x) & BIT_MASK_EDATA1_V1) << BIT_SHIFT_EDATA1_V1)
+#define BITS_EDATA1_V1 (BIT_MASK_EDATA1_V1 << BIT_SHIFT_EDATA1_V1)
+#define BIT_CLEAR_EDATA1_V1(x) ((x) & (~BITS_EDATA1_V1))
+#define BIT_GET_EDATA1_V1(x) (((x) >> BIT_SHIFT_EDATA1_V1) & BIT_MASK_EDATA1_V1)
+#define BIT_SET_EDATA1_V1(x, v) (BIT_CLEAR_EDATA1_V1(x) | BIT_EDATA1_V1(v))
-#define BIT_SHIFT_EDATA1_V1 8
-#define BIT_MASK_EDATA1_V1 0xff
-#define BIT_EDATA1_V1(x) (((x) & BIT_MASK_EDATA1_V1) << BIT_SHIFT_EDATA1_V1)
-#define BIT_GET_EDATA1_V1(x) (((x) >> BIT_SHIFT_EDATA1_V1) & BIT_MASK_EDATA1_V1)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */
+#define BIT_BT_ACCESS_WL_PAGE0 BIT(6)
-#if (HALMAC_8821C_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */
-#define BIT_BT_ACCESS_WL_PAGE0 BIT(6)
+#define BIT_REG_RST_WLPMC BIT(5)
+#define BIT_REG_RST_PD12N BIT(4)
+#define BIT_SYSON_DIS_WLREG_WRMSK BIT(3)
+#define BIT_SYSON_DIS_PMCREG_WRMSK BIT(2)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_SDIO_TRANS_FIFO_STATUS (Offset 0x102500CC) */
+#define BIT_TRANS_FIFO_UNDERFLOW BIT(1)
-/* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */
+#endif
-#define BIT_REG_RST_WLPMC BIT(5)
-#define BIT_REG_RST_PD12N BIT(4)
-#define BIT_SYSON_DIS_WLREG_WRMSK BIT(3)
-#define BIT_SYSON_DIS_PMCREG_WRMSK BIT(2)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_SYSON_REG_ARB 0
-#define BIT_MASK_SYSON_REG_ARB 0x3
-#define BIT_SYSON_REG_ARB(x) (((x) & BIT_MASK_SYSON_REG_ARB) << BIT_SHIFT_SYSON_REG_ARB)
-#define BIT_GET_SYSON_REG_ARB(x) (((x) >> BIT_SHIFT_SYSON_REG_ARB) & BIT_MASK_SYSON_REG_ARB)
+/* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */
+#define BIT_SHIFT_SYSON_REG_ARB 0
+#define BIT_MASK_SYSON_REG_ARB 0x3
+#define BIT_SYSON_REG_ARB(x) \
+ (((x) & BIT_MASK_SYSON_REG_ARB) << BIT_SHIFT_SYSON_REG_ARB)
+#define BITS_SYSON_REG_ARB (BIT_MASK_SYSON_REG_ARB << BIT_SHIFT_SYSON_REG_ARB)
+#define BIT_CLEAR_SYSON_REG_ARB(x) ((x) & (~BITS_SYSON_REG_ARB))
+#define BIT_GET_SYSON_REG_ARB(x) \
+ (((x) >> BIT_SHIFT_SYSON_REG_ARB) & BIT_MASK_SYSON_REG_ARB)
+#define BIT_SET_SYSON_REG_ARB(x, v) \
+ (BIT_CLEAR_SYSON_REG_ARB(x) | BIT_SYSON_REG_ARB(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */
+#define BIT_SHIFT_EDATA0_V1 0
+#define BIT_MASK_EDATA0_V1 0xff
+#define BIT_EDATA0_V1(x) (((x) & BIT_MASK_EDATA0_V1) << BIT_SHIFT_EDATA0_V1)
+#define BITS_EDATA0_V1 (BIT_MASK_EDATA0_V1 << BIT_SHIFT_EDATA0_V1)
+#define BIT_CLEAR_EDATA0_V1(x) ((x) & (~BITS_EDATA0_V1))
+#define BIT_GET_EDATA0_V1(x) (((x) >> BIT_SHIFT_EDATA0_V1) & BIT_MASK_EDATA0_V1)
+#define BIT_SET_EDATA0_V1(x, v) (BIT_CLEAR_EDATA0_V1(x) | BIT_EDATA0_V1(v))
-#define BIT_SHIFT_EDATA0_V1 0
-#define BIT_MASK_EDATA0_V1 0xff
-#define BIT_EDATA0_V1(x) (((x) & BIT_MASK_EDATA0_V1) << BIT_SHIFT_EDATA0_V1)
-#define BIT_GET_EDATA0_V1(x) (((x) >> BIT_SHIFT_EDATA0_V1) & BIT_MASK_EDATA0_V1)
+#endif
+#if (HALMAC_8822C_SUPPORT)
-/* 2 REG_BIST_CTRL (Offset 0x00D0) */
+/* 2 REG_SDIO_TRANS_FIFO_STATUS (Offset 0x102500CC) */
-#define BIT_SCAN_PLL_BYPASS BIT(30)
-#define BIT_DRF_BIST_FAIL_V1 BIT(28)
+#define BIT_TRANS_FIFO_OVERFLOW BIT(0)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_BIST_CTRL (Offset 0x00D0) */
-#define BIT_BIST_USB_DIS BIT(27)
+#define BIT_LD_RQPN BIT(31)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_BIST_CTRL (Offset 0x00D0) */
-#define BIT_DRF_BIST_READY_V1 BIT(27)
+#define BIT_SCAN_PLL_BYPASS BIT(30)
+#define BIT_DRF_BIST_FAIL_V1 BIT(28)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_BIST_CTRL (Offset 0x00D0) */
-#define BIT_BIST_PCI_DIS BIT(26)
+#define BIT_BIST_USB_DIS BIT(27)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_BIST_CTRL (Offset 0x00D0) */
-#define BIT_BIST_FAIL_V1 BIT(26)
+#define BIT_DRF_BIST_READY_V1 BIT(27)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_BIST_CTRL (Offset 0x00D0) */
-#define BIT_BIST_BT_DIS BIT(25)
+#define BIT_BIST_PCI_DIS BIT(26)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_BIST_CTRL (Offset 0x00D0) */
-#define BIT_BIST_READY_V1 BIT(25)
+#define BIT_BIST_FAIL_V1 BIT(26)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_BIST_CTRL (Offset 0x00D0) */
-#define BIT_BIST_WL_DIS BIT(24)
+#define BIT_BIST_BT_DIS BIT(25)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_BIST_CTRL (Offset 0x00D0) */
-#define BIT_BIST_START_PAUSE_V1 BIT(24)
+#define BIT_BIST_READY_V1 BIT(25)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_BIST_CTRL (Offset 0x00D0) */
-
-#define BIT_SHIFT_BIST_RPT_SEL 16
-#define BIT_MASK_BIST_RPT_SEL 0xf
-#define BIT_BIST_RPT_SEL(x) (((x) & BIT_MASK_BIST_RPT_SEL) << BIT_SHIFT_BIST_RPT_SEL)
-#define BIT_GET_BIST_RPT_SEL(x) (((x) >> BIT_SHIFT_BIST_RPT_SEL) & BIT_MASK_BIST_RPT_SEL)
-
+#define BIT_BIST_WL_DIS BIT(24)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_BIST_CTRL (Offset 0x00D0) */
-
-#define BIT_SHIFT_MBIST_RSTNI 8
-#define BIT_MASK_MBIST_RSTNI 0x3ff
-#define BIT_MBIST_RSTNI(x) (((x) & BIT_MASK_MBIST_RSTNI) << BIT_SHIFT_MBIST_RSTNI)
-#define BIT_GET_MBIST_RSTNI(x) (((x) >> BIT_SHIFT_MBIST_RSTNI) & BIT_MASK_MBIST_RSTNI)
-
-#define BIT_BIST_RESUME_PS_V1 BIT(5)
+#define BIT_BIST_START_PAUSE_V1 BIT(24)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_BIST_CTRL (Offset 0x00D0) */
-#define BIT_BIST_RESUME_PS BIT(4)
+#define BIT_SHIFT_BIST_RPT_SEL 16
+#define BIT_MASK_BIST_RPT_SEL 0xf
+#define BIT_BIST_RPT_SEL(x) \
+ (((x) & BIT_MASK_BIST_RPT_SEL) << BIT_SHIFT_BIST_RPT_SEL)
+#define BITS_BIST_RPT_SEL (BIT_MASK_BIST_RPT_SEL << BIT_SHIFT_BIST_RPT_SEL)
+#define BIT_CLEAR_BIST_RPT_SEL(x) ((x) & (~BITS_BIST_RPT_SEL))
+#define BIT_GET_BIST_RPT_SEL(x) \
+ (((x) >> BIT_SHIFT_BIST_RPT_SEL) & BIT_MASK_BIST_RPT_SEL)
+#define BIT_SET_BIST_RPT_SEL(x, v) \
+ (BIT_CLEAR_BIST_RPT_SEL(x) | BIT_BIST_RPT_SEL(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_BIST_CTRL (Offset 0x00D0) */
-#define BIT_BIST_RESUME_V1 BIT(4)
-
-#endif
+#define BIT_SHIFT_MBIST_RSTNI 8
+#define BIT_MASK_MBIST_RSTNI 0x3ff
+#define BIT_MBIST_RSTNI(x) \
+ (((x) & BIT_MASK_MBIST_RSTNI) << BIT_SHIFT_MBIST_RSTNI)
+#define BITS_MBIST_RSTNI (BIT_MASK_MBIST_RSTNI << BIT_SHIFT_MBIST_RSTNI)
+#define BIT_CLEAR_MBIST_RSTNI(x) ((x) & (~BITS_MBIST_RSTNI))
+#define BIT_GET_MBIST_RSTNI(x) \
+ (((x) >> BIT_SHIFT_MBIST_RSTNI) & BIT_MASK_MBIST_RSTNI)
+#define BIT_SET_MBIST_RSTNI(x, v) \
+ (BIT_CLEAR_MBIST_RSTNI(x) | BIT_MBIST_RSTNI(v))
+#define BIT_BIST_RESUME_PS_V1 BIT(5)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_BIST_CTRL (Offset 0x00D0) */
-#define BIT_BIST_RESUME BIT(3)
-#define BIT_BIST_NORMAL BIT(2)
+#define BIT_BIST_RESUME_PS BIT(4)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_BIST_CTRL (Offset 0x00D0) */
+#define BIT_BIST_RESUME_V1 BIT(4)
-#define BIT_SHIFT_BIST_MODE 2
-#define BIT_MASK_BIST_MODE 0x3
-#define BIT_BIST_MODE(x) (((x) & BIT_MASK_BIST_MODE) << BIT_SHIFT_BIST_MODE)
-#define BIT_GET_BIST_MODE(x) (((x) >> BIT_SHIFT_BIST_MODE) & BIT_MASK_BIST_MODE)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_BIST_CTRL (Offset 0x00D0) */
+#define BIT_BIST_RESUME BIT(3)
+#define BIT_BIST_NORMAL BIT(2)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
/* 2 REG_BIST_CTRL (Offset 0x00D0) */
-#define BIT_BIST_RSTN BIT(1)
-#define BIT_BIST_CLK_EN BIT(0)
+#define BIT_SHIFT_BIST_MODE 2
+#define BIT_MASK_BIST_MODE 0x3
+#define BIT_BIST_MODE(x) (((x) & BIT_MASK_BIST_MODE) << BIT_SHIFT_BIST_MODE)
+#define BITS_BIST_MODE (BIT_MASK_BIST_MODE << BIT_SHIFT_BIST_MODE)
+#define BIT_CLEAR_BIST_MODE(x) ((x) & (~BITS_BIST_MODE))
+#define BIT_GET_BIST_MODE(x) (((x) >> BIT_SHIFT_BIST_MODE) & BIT_MASK_BIST_MODE)
+#define BIT_SET_BIST_MODE(x, v) (BIT_CLEAR_BIST_MODE(x) | BIT_BIST_MODE(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_BIST_CTRL (Offset 0x00D0) */
+#define BIT_BIST_RSTN BIT(1)
+#define BIT_BIST_CLK_EN BIT(0)
-/* 2 REG_BIST_RPT (Offset 0x00D4) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_MBIST_REPORT 0
-#define BIT_MASK_MBIST_REPORT 0xffffffffL
-#define BIT_MBIST_REPORT(x) (((x) & BIT_MASK_MBIST_REPORT) << BIT_SHIFT_MBIST_REPORT)
-#define BIT_GET_MBIST_REPORT(x) (((x) >> BIT_SHIFT_MBIST_REPORT) & BIT_MASK_MBIST_REPORT)
+/* 2 REG_BIST_RPT (Offset 0x00D4) */
+#define BIT_SHIFT_MBIST_REPORT 0
+#define BIT_MASK_MBIST_REPORT 0xffffffffL
+#define BIT_MBIST_REPORT(x) \
+ (((x) & BIT_MASK_MBIST_REPORT) << BIT_SHIFT_MBIST_REPORT)
+#define BITS_MBIST_REPORT (BIT_MASK_MBIST_REPORT << BIT_SHIFT_MBIST_REPORT)
+#define BIT_CLEAR_MBIST_REPORT(x) ((x) & (~BITS_MBIST_REPORT))
+#define BIT_GET_MBIST_REPORT(x) \
+ (((x) >> BIT_SHIFT_MBIST_REPORT) & BIT_MASK_MBIST_REPORT)
+#define BIT_SET_MBIST_REPORT(x, v) \
+ (BIT_CLEAR_MBIST_REPORT(x) | BIT_MBIST_REPORT(v))
#endif
-
#if (HALMAC_8192E_SUPPORT)
-
/* 2 REG_MEM_CTRL (Offset 0x00D8) */
-#define BIT_RMV_SIGN BIT(31)
+#define BIT_RMV_SIGN BIT(31)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_MEM_CTRL (Offset 0x00D8) */
-#define BIT_UMEM_RME BIT(31)
+#define BIT_UMEM_RME BIT(31)
#endif
-
#if (HALMAC_8192E_SUPPORT)
-
/* 2 REG_MEM_CTRL (Offset 0x00D8) */
-#define BIT_RMV_2PRF1 BIT(29)
-#define BIT_RMV_2PRF0 BIT(28)
+#define BIT_RMV_2PRF1 BIT(29)
+#define BIT_RMV_2PRF0 BIT(28)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_MEM_CTRL (Offset 0x00D8) */
-
-#define BIT_SHIFT_BT_SPRAM 28
-#define BIT_MASK_BT_SPRAM 0x3
-#define BIT_BT_SPRAM(x) (((x) & BIT_MASK_BT_SPRAM) << BIT_SHIFT_BT_SPRAM)
-#define BIT_GET_BT_SPRAM(x) (((x) >> BIT_SHIFT_BT_SPRAM) & BIT_MASK_BT_SPRAM)
-
+#define BIT_SHIFT_BT_SPRAM 28
+#define BIT_MASK_BT_SPRAM 0x3
+#define BIT_BT_SPRAM(x) (((x) & BIT_MASK_BT_SPRAM) << BIT_SHIFT_BT_SPRAM)
+#define BITS_BT_SPRAM (BIT_MASK_BT_SPRAM << BIT_SHIFT_BT_SPRAM)
+#define BIT_CLEAR_BT_SPRAM(x) ((x) & (~BITS_BT_SPRAM))
+#define BIT_GET_BT_SPRAM(x) (((x) >> BIT_SHIFT_BT_SPRAM) & BIT_MASK_BT_SPRAM)
+#define BIT_SET_BT_SPRAM(x, v) (BIT_CLEAR_BT_SPRAM(x) | BIT_BT_SPRAM(v))
#endif
-
#if (HALMAC_8192E_SUPPORT)
-
/* 2 REG_MEM_CTRL (Offset 0x00D8) */
-#define BIT_RMV_1PRF1 BIT(27)
-#define BIT_RMV_1PRF0 BIT(26)
-#define BIT_RMV_1PSR BIT(25)
-#define BIT_RMV_ROM BIT(24)
+#define BIT_RMV_1PRF1 BIT(27)
+#define BIT_RMV_1PRF0 BIT(26)
+#define BIT_RMV_1PSR BIT(25)
+#define BIT_RMV_ROM BIT(24)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MEM_CTRL (Offset 0x00D8) */
+
+#define BIT_SHIFT_BT_ROM 24
+#define BIT_MASK_BT_ROM 0xf
+#define BIT_BT_ROM(x) (((x) & BIT_MASK_BT_ROM) << BIT_SHIFT_BT_ROM)
+#define BITS_BT_ROM (BIT_MASK_BT_ROM << BIT_SHIFT_BT_ROM)
+#define BIT_CLEAR_BT_ROM(x) ((x) & (~BITS_BT_ROM))
+#define BIT_GET_BT_ROM(x) (((x) >> BIT_SHIFT_BT_ROM) & BIT_MASK_BT_ROM)
+#define BIT_SET_BT_ROM(x, v) (BIT_CLEAR_BT_ROM(x) | BIT_BT_ROM(v))
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#define BIT_SHIFT_PCI_DPRAM 10
+#define BIT_MASK_PCI_DPRAM 0x3
+#define BIT_PCI_DPRAM(x) (((x) & BIT_MASK_PCI_DPRAM) << BIT_SHIFT_PCI_DPRAM)
+#define BITS_PCI_DPRAM (BIT_MASK_PCI_DPRAM << BIT_SHIFT_PCI_DPRAM)
+#define BIT_CLEAR_PCI_DPRAM(x) ((x) & (~BITS_PCI_DPRAM))
+#define BIT_GET_PCI_DPRAM(x) (((x) >> BIT_SHIFT_PCI_DPRAM) & BIT_MASK_PCI_DPRAM)
+#define BIT_SET_PCI_DPRAM(x, v) (BIT_CLEAR_PCI_DPRAM(x) | BIT_PCI_DPRAM(v))
+
+#endif
+#if (HALMAC_8192E_SUPPORT)
/* 2 REG_MEM_CTRL (Offset 0x00D8) */
+#define BIT_SHIFT_MEM_RME_BT 8
+#define BIT_MASK_MEM_RME_BT 0xf
+#define BIT_MEM_RME_BT(x) (((x) & BIT_MASK_MEM_RME_BT) << BIT_SHIFT_MEM_RME_BT)
+#define BITS_MEM_RME_BT (BIT_MASK_MEM_RME_BT << BIT_SHIFT_MEM_RME_BT)
+#define BIT_CLEAR_MEM_RME_BT(x) ((x) & (~BITS_MEM_RME_BT))
+#define BIT_GET_MEM_RME_BT(x) \
+ (((x) >> BIT_SHIFT_MEM_RME_BT) & BIT_MASK_MEM_RME_BT)
+#define BIT_SET_MEM_RME_BT(x, v) (BIT_CLEAR_MEM_RME_BT(x) | BIT_MEM_RME_BT(v))
-#define BIT_SHIFT_BT_ROM 24
-#define BIT_MASK_BT_ROM 0xf
-#define BIT_BT_ROM(x) (((x) & BIT_MASK_BT_ROM) << BIT_SHIFT_BT_ROM)
-#define BIT_GET_BT_ROM(x) (((x) >> BIT_SHIFT_BT_ROM) & BIT_MASK_BT_ROM)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_PCI_DPRAM 10
-#define BIT_MASK_PCI_DPRAM 0x3
-#define BIT_PCI_DPRAM(x) (((x) & BIT_MASK_PCI_DPRAM) << BIT_SHIFT_PCI_DPRAM)
-#define BIT_GET_PCI_DPRAM(x) (((x) >> BIT_SHIFT_PCI_DPRAM) & BIT_MASK_PCI_DPRAM)
+/* 2 REG_MEM_CTRL (Offset 0x00D8) */
+#define BIT_SHIFT_PCI_SPRAM 8
+#define BIT_MASK_PCI_SPRAM 0x3
+#define BIT_PCI_SPRAM(x) (((x) & BIT_MASK_PCI_SPRAM) << BIT_SHIFT_PCI_SPRAM)
+#define BITS_PCI_SPRAM (BIT_MASK_PCI_SPRAM << BIT_SHIFT_PCI_SPRAM)
+#define BIT_CLEAR_PCI_SPRAM(x) ((x) & (~BITS_PCI_SPRAM))
+#define BIT_GET_PCI_SPRAM(x) (((x) >> BIT_SHIFT_PCI_SPRAM) & BIT_MASK_PCI_SPRAM)
+#define BIT_SET_PCI_SPRAM(x, v) (BIT_CLEAR_PCI_SPRAM(x) | BIT_PCI_SPRAM(v))
-#endif
+#define BIT_SHIFT_USB_SPRAM 6
+#define BIT_MASK_USB_SPRAM 0x3
+#define BIT_USB_SPRAM(x) (((x) & BIT_MASK_USB_SPRAM) << BIT_SHIFT_USB_SPRAM)
+#define BITS_USB_SPRAM (BIT_MASK_USB_SPRAM << BIT_SHIFT_USB_SPRAM)
+#define BIT_CLEAR_USB_SPRAM(x) ((x) & (~BITS_USB_SPRAM))
+#define BIT_GET_USB_SPRAM(x) (((x) >> BIT_SHIFT_USB_SPRAM) & BIT_MASK_USB_SPRAM)
+#define BIT_SET_USB_SPRAM(x, v) (BIT_CLEAR_USB_SPRAM(x) | BIT_USB_SPRAM(v))
+#endif
#if (HALMAC_8192E_SUPPORT)
-
/* 2 REG_MEM_CTRL (Offset 0x00D8) */
+#define BIT_SHIFT_MEM_RME_WL 4
+#define BIT_MASK_MEM_RME_WL 0xf
+#define BIT_MEM_RME_WL(x) (((x) & BIT_MASK_MEM_RME_WL) << BIT_SHIFT_MEM_RME_WL)
+#define BITS_MEM_RME_WL (BIT_MASK_MEM_RME_WL << BIT_SHIFT_MEM_RME_WL)
+#define BIT_CLEAR_MEM_RME_WL(x) ((x) & (~BITS_MEM_RME_WL))
+#define BIT_GET_MEM_RME_WL(x) \
+ (((x) >> BIT_SHIFT_MEM_RME_WL) & BIT_MASK_MEM_RME_WL)
+#define BIT_SET_MEM_RME_WL(x, v) (BIT_CLEAR_MEM_RME_WL(x) | BIT_MEM_RME_WL(v))
-#define BIT_SHIFT_MEM_RME_BT 8
-#define BIT_MASK_MEM_RME_BT 0xf
-#define BIT_MEM_RME_BT(x) (((x) & BIT_MASK_MEM_RME_BT) << BIT_SHIFT_MEM_RME_BT)
-#define BIT_GET_MEM_RME_BT(x) (((x) >> BIT_SHIFT_MEM_RME_BT) & BIT_MASK_MEM_RME_BT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_MEM_CTRL (Offset 0x00D8) */
+#define BIT_SHIFT_USB_SPRF 4
+#define BIT_MASK_USB_SPRF 0x3
+#define BIT_USB_SPRF(x) (((x) & BIT_MASK_USB_SPRF) << BIT_SHIFT_USB_SPRF)
+#define BITS_USB_SPRF (BIT_MASK_USB_SPRF << BIT_SHIFT_USB_SPRF)
+#define BIT_CLEAR_USB_SPRF(x) ((x) & (~BITS_USB_SPRF))
+#define BIT_GET_USB_SPRF(x) (((x) >> BIT_SHIFT_USB_SPRF) & BIT_MASK_USB_SPRF)
+#define BIT_SET_USB_SPRF(x, v) (BIT_CLEAR_USB_SPRF(x) | BIT_USB_SPRF(v))
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT)
/* 2 REG_MEM_CTRL (Offset 0x00D8) */
+#define BIT_SHIFT_MEM_RME_HCI 0
+#define BIT_MASK_MEM_RME_HCI 0xf
+#define BIT_MEM_RME_HCI(x) \
+ (((x) & BIT_MASK_MEM_RME_HCI) << BIT_SHIFT_MEM_RME_HCI)
+#define BITS_MEM_RME_HCI (BIT_MASK_MEM_RME_HCI << BIT_SHIFT_MEM_RME_HCI)
+#define BIT_CLEAR_MEM_RME_HCI(x) ((x) & (~BITS_MEM_RME_HCI))
+#define BIT_GET_MEM_RME_HCI(x) \
+ (((x) >> BIT_SHIFT_MEM_RME_HCI) & BIT_MASK_MEM_RME_HCI)
+#define BIT_SET_MEM_RME_HCI(x, v) \
+ (BIT_CLEAR_MEM_RME_HCI(x) | BIT_MEM_RME_HCI(v))
-#define BIT_SHIFT_PCI_SPRAM 8
-#define BIT_MASK_PCI_SPRAM 0x3
-#define BIT_PCI_SPRAM(x) (((x) & BIT_MASK_PCI_SPRAM) << BIT_SHIFT_PCI_SPRAM)
-#define BIT_GET_PCI_SPRAM(x) (((x) >> BIT_SHIFT_PCI_SPRAM) & BIT_MASK_PCI_SPRAM)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_USB_SPRAM 6
-#define BIT_MASK_USB_SPRAM 0x3
-#define BIT_USB_SPRAM(x) (((x) & BIT_MASK_USB_SPRAM) << BIT_SHIFT_USB_SPRAM)
-#define BIT_GET_USB_SPRAM(x) (((x) >> BIT_SHIFT_USB_SPRAM) & BIT_MASK_USB_SPRAM)
+/* 2 REG_MEM_CTRL (Offset 0x00D8) */
+#define BIT_SHIFT_MCU_ROM 0
+#define BIT_MASK_MCU_ROM 0xf
+#define BIT_MCU_ROM(x) (((x) & BIT_MASK_MCU_ROM) << BIT_SHIFT_MCU_ROM)
+#define BITS_MCU_ROM (BIT_MASK_MCU_ROM << BIT_SHIFT_MCU_ROM)
+#define BIT_CLEAR_MCU_ROM(x) ((x) & (~BITS_MCU_ROM))
+#define BIT_GET_MCU_ROM(x) (((x) >> BIT_SHIFT_MCU_ROM) & BIT_MASK_MCU_ROM)
+#define BIT_SET_MCU_ROM(x, v) (BIT_CLEAR_MCU_ROM(x) | BIT_MCU_ROM(v))
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8192E_SUPPORT)
+/* 2 REG_MEM_CTRL (Offset 0x00D8) */
+#define BIT_SHIFT_BIST_ROM 0
+#define BIT_MASK_BIST_ROM 0xffffffffL
+#define BIT_BIST_ROM(x) (((x) & BIT_MASK_BIST_ROM) << BIT_SHIFT_BIST_ROM)
+#define BITS_BIST_ROM (BIT_MASK_BIST_ROM << BIT_SHIFT_BIST_ROM)
+#define BIT_CLEAR_BIST_ROM(x) ((x) & (~BITS_BIST_ROM))
+#define BIT_GET_BIST_ROM(x) (((x) >> BIT_SHIFT_BIST_ROM) & BIT_MASK_BIST_ROM)
+#define BIT_SET_BIST_ROM(x, v) (BIT_CLEAR_BIST_ROM(x) | BIT_BIST_ROM(v))
-/* 2 REG_MEM_CTRL (Offset 0x00D8) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_MEM_RME_WL 4
-#define BIT_MASK_MEM_RME_WL 0xf
-#define BIT_MEM_RME_WL(x) (((x) & BIT_MASK_MEM_RME_WL) << BIT_SHIFT_MEM_RME_WL)
-#define BIT_GET_MEM_RME_WL(x) (((x) >> BIT_SHIFT_MEM_RME_WL) & BIT_MASK_MEM_RME_WL)
+/* 2 REG_AFE_CTRL8 (Offset 0x00DC) */
+#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4 26
+#define BIT_MASK_BB_DBG_SEL_AFE_SDM_V4 0x7
+#define BIT_BB_DBG_SEL_AFE_SDM_V4(x) \
+ (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_V4) \
+ << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4)
+#define BITS_BB_DBG_SEL_AFE_SDM_V4 \
+ (BIT_MASK_BB_DBG_SEL_AFE_SDM_V4 << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4)
+#define BIT_CLEAR_BB_DBG_SEL_AFE_SDM_V4(x) ((x) & (~BITS_BB_DBG_SEL_AFE_SDM_V4))
+#define BIT_GET_BB_DBG_SEL_AFE_SDM_V4(x) \
+ (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4) & \
+ BIT_MASK_BB_DBG_SEL_AFE_SDM_V4)
+#define BIT_SET_BB_DBG_SEL_AFE_SDM_V4(x, v) \
+ (BIT_CLEAR_BB_DBG_SEL_AFE_SDM_V4(x) | BIT_BB_DBG_SEL_AFE_SDM_V4(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_AFE_CTRL8 (Offset 0x00DC) */
+#define BIT_SYN_AGPIO BIT(20)
-/* 2 REG_MEM_CTRL (Offset 0x00D8) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_USB_SPRF 4
-#define BIT_MASK_USB_SPRF 0x3
-#define BIT_USB_SPRF(x) (((x) & BIT_MASK_USB_SPRF) << BIT_SHIFT_USB_SPRF)
-#define BIT_GET_USB_SPRF(x) (((x) >> BIT_SHIFT_USB_SPRF) & BIT_MASK_USB_SPRF)
+/* 2 REG_SYN_RFC_CTRL (Offset 0x00DC) */
+#define BIT_SHIFT_SYN_RF1_CTRL 8
+#define BIT_MASK_SYN_RF1_CTRL 0xff
+#define BIT_SYN_RF1_CTRL(x) \
+ (((x) & BIT_MASK_SYN_RF1_CTRL) << BIT_SHIFT_SYN_RF1_CTRL)
+#define BITS_SYN_RF1_CTRL (BIT_MASK_SYN_RF1_CTRL << BIT_SHIFT_SYN_RF1_CTRL)
+#define BIT_CLEAR_SYN_RF1_CTRL(x) ((x) & (~BITS_SYN_RF1_CTRL))
+#define BIT_GET_SYN_RF1_CTRL(x) \
+ (((x) >> BIT_SHIFT_SYN_RF1_CTRL) & BIT_MASK_SYN_RF1_CTRL)
+#define BIT_SET_SYN_RF1_CTRL(x, v) \
+ (BIT_CLEAR_SYN_RF1_CTRL(x) | BIT_SYN_RF1_CTRL(v))
#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT)
+/* 2 REG_AFE_CTRL8 (Offset 0x00DC) */
+#define BIT_XTAL_LP BIT(4)
+#define BIT_XTAL_GM_SEP BIT(3)
-/* 2 REG_MEM_CTRL (Offset 0x00D8) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_MEM_RME_HCI 0
-#define BIT_MASK_MEM_RME_HCI 0xf
-#define BIT_MEM_RME_HCI(x) (((x) & BIT_MASK_MEM_RME_HCI) << BIT_SHIFT_MEM_RME_HCI)
-#define BIT_GET_MEM_RME_HCI(x) (((x) >> BIT_SHIFT_MEM_RME_HCI) & BIT_MASK_MEM_RME_HCI)
+/* 2 REG_AFE_CTRL8 (Offset 0x00DC) */
+#define BIT_SHIFT_XTAL_SEL_TOK_V2 0
+#define BIT_MASK_XTAL_SEL_TOK_V2 0x7
+#define BIT_XTAL_SEL_TOK_V2(x) \
+ (((x) & BIT_MASK_XTAL_SEL_TOK_V2) << BIT_SHIFT_XTAL_SEL_TOK_V2)
+#define BITS_XTAL_SEL_TOK_V2 \
+ (BIT_MASK_XTAL_SEL_TOK_V2 << BIT_SHIFT_XTAL_SEL_TOK_V2)
+#define BIT_CLEAR_XTAL_SEL_TOK_V2(x) ((x) & (~BITS_XTAL_SEL_TOK_V2))
+#define BIT_GET_XTAL_SEL_TOK_V2(x) \
+ (((x) >> BIT_SHIFT_XTAL_SEL_TOK_V2) & BIT_MASK_XTAL_SEL_TOK_V2)
+#define BIT_SET_XTAL_SEL_TOK_V2(x, v) \
+ (BIT_CLEAR_XTAL_SEL_TOK_V2(x) | BIT_XTAL_SEL_TOK_V2(v))
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_WLAN_DBG (Offset 0x00DC) */
+#define BIT_SHIFT_WLAN_DBG 0
+#define BIT_MASK_WLAN_DBG 0xffffffffL
+#define BIT_WLAN_DBG(x) (((x) & BIT_MASK_WLAN_DBG) << BIT_SHIFT_WLAN_DBG)
+#define BITS_WLAN_DBG (BIT_MASK_WLAN_DBG << BIT_SHIFT_WLAN_DBG)
+#define BIT_CLEAR_WLAN_DBG(x) ((x) & (~BITS_WLAN_DBG))
+#define BIT_GET_WLAN_DBG(x) (((x) >> BIT_SHIFT_WLAN_DBG) & BIT_MASK_WLAN_DBG)
+#define BIT_SET_WLAN_DBG(x, v) (BIT_CLEAR_WLAN_DBG(x) | BIT_WLAN_DBG(v))
-/* 2 REG_MEM_CTRL (Offset 0x00D8) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_MCU_ROM 0
-#define BIT_MASK_MCU_ROM 0xf
-#define BIT_MCU_ROM(x) (((x) & BIT_MASK_MCU_ROM) << BIT_SHIFT_MCU_ROM)
-#define BIT_GET_MCU_ROM(x) (((x) >> BIT_SHIFT_MCU_ROM) & BIT_MASK_MCU_ROM)
+/* 2 REG_SYN_RFC_CTRL (Offset 0x00DC) */
+#define BIT_SHIFT_SYN_RF0_CTRL 0
+#define BIT_MASK_SYN_RF0_CTRL 0xff
+#define BIT_SYN_RF0_CTRL(x) \
+ (((x) & BIT_MASK_SYN_RF0_CTRL) << BIT_SHIFT_SYN_RF0_CTRL)
+#define BITS_SYN_RF0_CTRL (BIT_MASK_SYN_RF0_CTRL << BIT_SHIFT_SYN_RF0_CTRL)
+#define BIT_CLEAR_SYN_RF0_CTRL(x) ((x) & (~BITS_SYN_RF0_CTRL))
+#define BIT_GET_SYN_RF0_CTRL(x) \
+ (((x) >> BIT_SHIFT_SYN_RF0_CTRL) & BIT_MASK_SYN_RF0_CTRL)
+#define BIT_SET_SYN_RF0_CTRL(x, v) \
+ (BIT_CLEAR_SYN_RF0_CTRL(x) | BIT_SYN_RF0_CTRL(v))
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
-
-/* 2 REG_MEM_CTRL (Offset 0x00D8) */
-
-
-#define BIT_SHIFT_BIST_ROM 0
-#define BIT_MASK_BIST_ROM 0xffffffffL
-#define BIT_BIST_ROM(x) (((x) & BIT_MASK_BIST_ROM) << BIT_SHIFT_BIST_ROM)
-#define BIT_GET_BIST_ROM(x) (((x) >> BIT_SHIFT_BIST_ROM) & BIT_MASK_BIST_ROM)
-
-
-#endif
-
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
/* 2 REG_AFE_CTRL8 (Offset 0x00DC) */
-
-#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4 26
-#define BIT_MASK_BB_DBG_SEL_AFE_SDM_V4 0x7
-#define BIT_BB_DBG_SEL_AFE_SDM_V4(x) (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_V4) << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4)
-#define BIT_GET_BB_DBG_SEL_AFE_SDM_V4(x) (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4) & BIT_MASK_BB_DBG_SEL_AFE_SDM_V4)
-
+#define BIT_SHIFT_XTAL_SEL_TOK 0
+#define BIT_MASK_XTAL_SEL_TOK 0x7
+#define BIT_XTAL_SEL_TOK(x) \
+ (((x) & BIT_MASK_XTAL_SEL_TOK) << BIT_SHIFT_XTAL_SEL_TOK)
+#define BITS_XTAL_SEL_TOK (BIT_MASK_XTAL_SEL_TOK << BIT_SHIFT_XTAL_SEL_TOK)
+#define BIT_CLEAR_XTAL_SEL_TOK(x) ((x) & (~BITS_XTAL_SEL_TOK))
+#define BIT_GET_XTAL_SEL_TOK(x) \
+ (((x) >> BIT_SHIFT_XTAL_SEL_TOK) & BIT_MASK_XTAL_SEL_TOK)
+#define BIT_SET_XTAL_SEL_TOK(x, v) \
+ (BIT_CLEAR_XTAL_SEL_TOK(x) | BIT_XTAL_SEL_TOK(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_AFE_CTRL8 (Offset 0x00DC) */
+/* 2 REG_USB_SIE_INTF (Offset 0x00E0) */
-#define BIT_SYN_AGPIO BIT(20)
+#define BIT_RD_SEL BIT(31)
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_AFE_CTRL8 (Offset 0x00DC) */
+/* 2 REG_USB_SIE_INTF (Offset 0x00E0) */
-#define BIT_XTAL_LP BIT(4)
-#define BIT_XTAL_GM_SEP BIT(3)
+#define BIT_CPU_REG_SEL BIT(31)
+#define BIT_USB3_REG_SEL BIT(30)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
-
-/* 2 REG_AFE_CTRL8 (Offset 0x00DC) */
-
-
-#define BIT_SHIFT_XTAL_SEL_TOK_V2 0
-#define BIT_MASK_XTAL_SEL_TOK_V2 0x7
-#define BIT_XTAL_SEL_TOK_V2(x) (((x) & BIT_MASK_XTAL_SEL_TOK_V2) << BIT_SHIFT_XTAL_SEL_TOK_V2)
-#define BIT_GET_XTAL_SEL_TOK_V2(x) (((x) >> BIT_SHIFT_XTAL_SEL_TOK_V2) & BIT_MASK_XTAL_SEL_TOK_V2)
+/* 2 REG_USB_SIE_INTF (Offset 0x00E0) */
+#define BIT_USB_SIE_INTF_WE_V1 BIT(30)
+#define BIT_USB_SIE_INTF_BYIOREG_V1 BIT(29)
+#define BIT_USB_SIE_SELECT BIT(28)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
-
-/* 2 REG_WLAN_DBG (Offset 0x00DC) */
-
+/* 2 REG_USB_SIE_INTF (Offset 0x00E0) */
-#define BIT_SHIFT_WLAN_DBG 0
-#define BIT_MASK_WLAN_DBG 0xffffffffL
-#define BIT_WLAN_DBG(x) (((x) & BIT_MASK_WLAN_DBG) << BIT_SHIFT_WLAN_DBG)
-#define BIT_GET_WLAN_DBG(x) (((x) >> BIT_SHIFT_WLAN_DBG) & BIT_MASK_WLAN_DBG)
+#define BIT_USB_SIE_INTF_WE BIT(25)
+#define BIT_USB_SIE_INTF_BYIOREG BIT(24)
+#define BIT_SHIFT_USB_SIE_INTF_ADDR 16
+#define BIT_MASK_USB_SIE_INTF_ADDR 0xff
+#define BIT_USB_SIE_INTF_ADDR(x) \
+ (((x) & BIT_MASK_USB_SIE_INTF_ADDR) << BIT_SHIFT_USB_SIE_INTF_ADDR)
+#define BITS_USB_SIE_INTF_ADDR \
+ (BIT_MASK_USB_SIE_INTF_ADDR << BIT_SHIFT_USB_SIE_INTF_ADDR)
+#define BIT_CLEAR_USB_SIE_INTF_ADDR(x) ((x) & (~BITS_USB_SIE_INTF_ADDR))
+#define BIT_GET_USB_SIE_INTF_ADDR(x) \
+ (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR) & BIT_MASK_USB_SIE_INTF_ADDR)
+#define BIT_SET_USB_SIE_INTF_ADDR(x, v) \
+ (BIT_CLEAR_USB_SIE_INTF_ADDR(x) | BIT_USB_SIE_INTF_ADDR(v))
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_AFE_CTRL8 (Offset 0x00DC) */
-
-
-#define BIT_SHIFT_XTAL_SEL_TOK 0
-#define BIT_MASK_XTAL_SEL_TOK 0x7
-#define BIT_XTAL_SEL_TOK(x) (((x) & BIT_MASK_XTAL_SEL_TOK) << BIT_SHIFT_XTAL_SEL_TOK)
-#define BIT_GET_XTAL_SEL_TOK(x) (((x) >> BIT_SHIFT_XTAL_SEL_TOK) & BIT_MASK_XTAL_SEL_TOK)
+/* 2 REG_USB_SIE_INTF (Offset 0x00E0) */
+#define BIT_SHIFT_USB_SIE_INTF_ADDR_V1 16
+#define BIT_MASK_USB_SIE_INTF_ADDR_V1 0x1ff
+#define BIT_USB_SIE_INTF_ADDR_V1(x) \
+ (((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1) \
+ << BIT_SHIFT_USB_SIE_INTF_ADDR_V1)
+#define BITS_USB_SIE_INTF_ADDR_V1 \
+ (BIT_MASK_USB_SIE_INTF_ADDR_V1 << BIT_SHIFT_USB_SIE_INTF_ADDR_V1)
+#define BIT_CLEAR_USB_SIE_INTF_ADDR_V1(x) ((x) & (~BITS_USB_SIE_INTF_ADDR_V1))
+#define BIT_GET_USB_SIE_INTF_ADDR_V1(x) \
+ (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1) & \
+ BIT_MASK_USB_SIE_INTF_ADDR_V1)
+#define BIT_SET_USB_SIE_INTF_ADDR_V1(x, v) \
+ (BIT_CLEAR_USB_SIE_INTF_ADDR_V1(x) | BIT_USB_SIE_INTF_ADDR_V1(v))
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_USB_SIE_INTF (Offset 0x00E0) */
-#define BIT_RD_SEL BIT(31)
+#define BIT_SHIFT_USB_SIE_INTF_RD 8
+#define BIT_MASK_USB_SIE_INTF_RD 0xff
+#define BIT_USB_SIE_INTF_RD(x) \
+ (((x) & BIT_MASK_USB_SIE_INTF_RD) << BIT_SHIFT_USB_SIE_INTF_RD)
+#define BITS_USB_SIE_INTF_RD \
+ (BIT_MASK_USB_SIE_INTF_RD << BIT_SHIFT_USB_SIE_INTF_RD)
+#define BIT_CLEAR_USB_SIE_INTF_RD(x) ((x) & (~BITS_USB_SIE_INTF_RD))
+#define BIT_GET_USB_SIE_INTF_RD(x) \
+ (((x) >> BIT_SHIFT_USB_SIE_INTF_RD) & BIT_MASK_USB_SIE_INTF_RD)
+#define BIT_SET_USB_SIE_INTF_RD(x, v) \
+ (BIT_CLEAR_USB_SIE_INTF_RD(x) | BIT_USB_SIE_INTF_RD(v))
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_USB_SIE_INTF (Offset 0x00E0) */
-#define BIT_CPU_REG_SEL BIT(31)
-#define BIT_USB3_REG_SEL BIT(30)
+#define BIT_SHIFT_NPQ_AVAL_PG 8
+#define BIT_MASK_NPQ_AVAL_PG 0xff
+#define BIT_NPQ_AVAL_PG(x) \
+ (((x) & BIT_MASK_NPQ_AVAL_PG) << BIT_SHIFT_NPQ_AVAL_PG)
+#define BITS_NPQ_AVAL_PG (BIT_MASK_NPQ_AVAL_PG << BIT_SHIFT_NPQ_AVAL_PG)
+#define BIT_CLEAR_NPQ_AVAL_PG(x) ((x) & (~BITS_NPQ_AVAL_PG))
+#define BIT_GET_NPQ_AVAL_PG(x) \
+ (((x) >> BIT_SHIFT_NPQ_AVAL_PG) & BIT_MASK_NPQ_AVAL_PG)
+#define BIT_SET_NPQ_AVAL_PG(x, v) \
+ (BIT_CLEAR_NPQ_AVAL_PG(x) | BIT_NPQ_AVAL_PG(v))
#endif
-
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_USB_SIE_INTF (Offset 0x00E0) */
-#define BIT_USB_SIE_INTF_WE_V1 BIT(30)
-#define BIT_USB_SIE_INTF_BYIOREG_V1 BIT(29)
-#define BIT_USB_SIE_SELECT BIT(28)
+#define BIT_SHIFT_USB_SIE_INTF_WD 0
+#define BIT_MASK_USB_SIE_INTF_WD 0xff
+#define BIT_USB_SIE_INTF_WD(x) \
+ (((x) & BIT_MASK_USB_SIE_INTF_WD) << BIT_SHIFT_USB_SIE_INTF_WD)
+#define BITS_USB_SIE_INTF_WD \
+ (BIT_MASK_USB_SIE_INTF_WD << BIT_SHIFT_USB_SIE_INTF_WD)
+#define BIT_CLEAR_USB_SIE_INTF_WD(x) ((x) & (~BITS_USB_SIE_INTF_WD))
+#define BIT_GET_USB_SIE_INTF_WD(x) \
+ (((x) >> BIT_SHIFT_USB_SIE_INTF_WD) & BIT_MASK_USB_SIE_INTF_WD)
+#define BIT_SET_USB_SIE_INTF_WD(x, v) \
+ (BIT_CLEAR_USB_SIE_INTF_WD(x) | BIT_USB_SIE_INTF_WD(v))
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_PCIE_MIO_INTF (Offset 0x00E4) */
+#define BIT_PCIE_MIO_EXIT_L1 BIT(19)
+#define BIT_PCIE_MIO_EXT BIT(18)
+#define BIT_PCIE_MIO_ACK BIT(17)
+#define BIT_PCIE_MIO_IOREG BIT(16)
-/* 2 REG_USB_SIE_INTF (Offset 0x00E0) */
+#endif
-#define BIT_USB_SIE_INTF_WE BIT(25)
-#define BIT_USB_SIE_INTF_BYIOREG BIT(24)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_USB_SIE_INTF_ADDR 16
-#define BIT_MASK_USB_SIE_INTF_ADDR 0xff
-#define BIT_USB_SIE_INTF_ADDR(x) (((x) & BIT_MASK_USB_SIE_INTF_ADDR) << BIT_SHIFT_USB_SIE_INTF_ADDR)
-#define BIT_GET_USB_SIE_INTF_ADDR(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR) & BIT_MASK_USB_SIE_INTF_ADDR)
+/* 2 REG_PCIE_MIO_INTF (Offset 0x00E4) */
+#define BIT_SHIFT_PCIE_MIO_ADDR_PAGE 16
+#define BIT_MASK_PCIE_MIO_ADDR_PAGE 0x3
+#define BIT_PCIE_MIO_ADDR_PAGE(x) \
+ (((x) & BIT_MASK_PCIE_MIO_ADDR_PAGE) << BIT_SHIFT_PCIE_MIO_ADDR_PAGE)
+#define BITS_PCIE_MIO_ADDR_PAGE \
+ (BIT_MASK_PCIE_MIO_ADDR_PAGE << BIT_SHIFT_PCIE_MIO_ADDR_PAGE)
+#define BIT_CLEAR_PCIE_MIO_ADDR_PAGE(x) ((x) & (~BITS_PCIE_MIO_ADDR_PAGE))
+#define BIT_GET_PCIE_MIO_ADDR_PAGE(x) \
+ (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_PAGE) & BIT_MASK_PCIE_MIO_ADDR_PAGE)
+#define BIT_SET_PCIE_MIO_ADDR_PAGE(x, v) \
+ (BIT_CLEAR_PCIE_MIO_ADDR_PAGE(x) | BIT_PCIE_MIO_ADDR_PAGE(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_USB_SIE_INTF (Offset 0x00E0) */
+/* 2 REG_PCIE_MIO_INTF (Offset 0x00E4) */
+#define BIT_PCIE_MIO_BYIOREG BIT(13)
+#define BIT_PCIE_MIO_RE BIT(12)
+
+#define BIT_SHIFT_PCIE_MIO_WE 8
+#define BIT_MASK_PCIE_MIO_WE 0xf
+#define BIT_PCIE_MIO_WE(x) \
+ (((x) & BIT_MASK_PCIE_MIO_WE) << BIT_SHIFT_PCIE_MIO_WE)
+#define BITS_PCIE_MIO_WE (BIT_MASK_PCIE_MIO_WE << BIT_SHIFT_PCIE_MIO_WE)
+#define BIT_CLEAR_PCIE_MIO_WE(x) ((x) & (~BITS_PCIE_MIO_WE))
+#define BIT_GET_PCIE_MIO_WE(x) \
+ (((x) >> BIT_SHIFT_PCIE_MIO_WE) & BIT_MASK_PCIE_MIO_WE)
+#define BIT_SET_PCIE_MIO_WE(x, v) \
+ (BIT_CLEAR_PCIE_MIO_WE(x) | BIT_PCIE_MIO_WE(v))
+
+#define BIT_SHIFT_PCIE_MIO_ADDR 0
+#define BIT_MASK_PCIE_MIO_ADDR 0xff
+#define BIT_PCIE_MIO_ADDR(x) \
+ (((x) & BIT_MASK_PCIE_MIO_ADDR) << BIT_SHIFT_PCIE_MIO_ADDR)
+#define BITS_PCIE_MIO_ADDR (BIT_MASK_PCIE_MIO_ADDR << BIT_SHIFT_PCIE_MIO_ADDR)
+#define BIT_CLEAR_PCIE_MIO_ADDR(x) ((x) & (~BITS_PCIE_MIO_ADDR))
+#define BIT_GET_PCIE_MIO_ADDR(x) \
+ (((x) >> BIT_SHIFT_PCIE_MIO_ADDR) & BIT_MASK_PCIE_MIO_ADDR)
+#define BIT_SET_PCIE_MIO_ADDR(x, v) \
+ (BIT_CLEAR_PCIE_MIO_ADDR(x) | BIT_PCIE_MIO_ADDR(v))
-#define BIT_SHIFT_USB_SIE_INTF_ADDR_V1 16
-#define BIT_MASK_USB_SIE_INTF_ADDR_V1 0x1ff
-#define BIT_USB_SIE_INTF_ADDR_V1(x) (((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1) << BIT_SHIFT_USB_SIE_INTF_ADDR_V1)
-#define BIT_GET_USB_SIE_INTF_ADDR_V1(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1) & BIT_MASK_USB_SIE_INTF_ADDR_V1)
+/* 2 REG_PCIE_MIO_INTD (Offset 0x00E8) */
+#define BIT_SHIFT_PCIE_MIO_DATA 0
+#define BIT_MASK_PCIE_MIO_DATA 0xffffffffL
+#define BIT_PCIE_MIO_DATA(x) \
+ (((x) & BIT_MASK_PCIE_MIO_DATA) << BIT_SHIFT_PCIE_MIO_DATA)
+#define BITS_PCIE_MIO_DATA (BIT_MASK_PCIE_MIO_DATA << BIT_SHIFT_PCIE_MIO_DATA)
+#define BIT_CLEAR_PCIE_MIO_DATA(x) ((x) & (~BITS_PCIE_MIO_DATA))
+#define BIT_GET_PCIE_MIO_DATA(x) \
+ (((x) >> BIT_SHIFT_PCIE_MIO_DATA) & BIT_MASK_PCIE_MIO_DATA)
+#define BIT_SET_PCIE_MIO_DATA(x, v) \
+ (BIT_CLEAR_PCIE_MIO_DATA(x) | BIT_PCIE_MIO_DATA(v))
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+/* 2 REG_HPON_FSM (Offset 0x00EC) */
-/* 2 REG_USB_SIE_INTF (Offset 0x00E0) */
+#define BIT_SUSPEND_V1 BIT(31)
+#define BIT_FSM_RESUME_V1 BIT(30)
+#define BIT_HOST_RESUME_SYNC_V1 BIT(29)
+#define BIT_CHIP_PDNB_V1 BIT(28)
+#define BIT_SHIFT_FSM_SUSPEND_V1 25
+#define BIT_MASK_FSM_SUSPEND_V1 0x7
+#define BIT_FSM_SUSPEND_V1(x) \
+ (((x) & BIT_MASK_FSM_SUSPEND_V1) << BIT_SHIFT_FSM_SUSPEND_V1)
+#define BITS_FSM_SUSPEND_V1 \
+ (BIT_MASK_FSM_SUSPEND_V1 << BIT_SHIFT_FSM_SUSPEND_V1)
+#define BIT_CLEAR_FSM_SUSPEND_V1(x) ((x) & (~BITS_FSM_SUSPEND_V1))
+#define BIT_GET_FSM_SUSPEND_V1(x) \
+ (((x) >> BIT_SHIFT_FSM_SUSPEND_V1) & BIT_MASK_FSM_SUSPEND_V1)
+#define BIT_SET_FSM_SUSPEND_V1(x, v) \
+ (BIT_CLEAR_FSM_SUSPEND_V1(x) | BIT_FSM_SUSPEND_V1(v))
-#define BIT_SHIFT_USB_SIE_INTF_RD 8
-#define BIT_MASK_USB_SIE_INTF_RD 0xff
-#define BIT_USB_SIE_INTF_RD(x) (((x) & BIT_MASK_USB_SIE_INTF_RD) << BIT_SHIFT_USB_SIE_INTF_RD)
-#define BIT_GET_USB_SIE_INTF_RD(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_RD) & BIT_MASK_USB_SIE_INTF_RD)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_USB_SIE_INTF_WD 0
-#define BIT_MASK_USB_SIE_INTF_WD 0xff
-#define BIT_USB_SIE_INTF_WD(x) (((x) & BIT_MASK_USB_SIE_INTF_WD) << BIT_SHIFT_USB_SIE_INTF_WD)
-#define BIT_GET_USB_SIE_INTF_WD(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_WD) & BIT_MASK_USB_SIE_INTF_WD)
+/* 2 REG_WLRF1 (Offset 0x00EC) */
+#define BIT_SHIFT_XTAL_SEL 25
+#define BIT_MASK_XTAL_SEL 0x3
+#define BIT_XTAL_SEL(x) (((x) & BIT_MASK_XTAL_SEL) << BIT_SHIFT_XTAL_SEL)
+#define BITS_XTAL_SEL (BIT_MASK_XTAL_SEL << BIT_SHIFT_XTAL_SEL)
+#define BIT_CLEAR_XTAL_SEL(x) ((x) & (~BITS_XTAL_SEL))
+#define BIT_GET_XTAL_SEL(x) (((x) >> BIT_SHIFT_XTAL_SEL) & BIT_MASK_XTAL_SEL)
+#define BIT_SET_XTAL_SEL(x, v) (BIT_CLEAR_XTAL_SEL(x) | BIT_XTAL_SEL(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_HPON_FSM (Offset 0x00EC) */
-/* 2 REG_PCIE_MIO_INTF (Offset 0x00E4) */
-
-#define BIT_PCIE_MIO_EXIT_L1 BIT(19)
-#define BIT_PCIE_MIO_EXT BIT(18)
-#define BIT_PCIE_MIO_ACK BIT(17)
-#define BIT_PCIE_MIO_IOREG BIT(16)
+#define BIT_PMC_ALD_V1 BIT(24)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+/* 2 REG_WLRF1 (Offset 0x00EC) */
-/* 2 REG_PCIE_MIO_INTF (Offset 0x00E4) */
+#define BIT_SHIFT_WLRF1_CTRL 24
+#define BIT_MASK_WLRF1_CTRL 0xff
+#define BIT_WLRF1_CTRL(x) (((x) & BIT_MASK_WLRF1_CTRL) << BIT_SHIFT_WLRF1_CTRL)
+#define BITS_WLRF1_CTRL (BIT_MASK_WLRF1_CTRL << BIT_SHIFT_WLRF1_CTRL)
+#define BIT_CLEAR_WLRF1_CTRL(x) ((x) & (~BITS_WLRF1_CTRL))
+#define BIT_GET_WLRF1_CTRL(x) \
+ (((x) >> BIT_SHIFT_WLRF1_CTRL) & BIT_MASK_WLRF1_CTRL)
+#define BIT_SET_WLRF1_CTRL(x, v) (BIT_CLEAR_WLRF1_CTRL(x) | BIT_WLRF1_CTRL(v))
-#define BIT_PCIE_MIO_BYIOREG BIT(13)
-#define BIT_PCIE_MIO_RE BIT(12)
+#endif
-#define BIT_SHIFT_PCIE_MIO_WE 8
-#define BIT_MASK_PCIE_MIO_WE 0xf
-#define BIT_PCIE_MIO_WE(x) (((x) & BIT_MASK_PCIE_MIO_WE) << BIT_SHIFT_PCIE_MIO_WE)
-#define BIT_GET_PCIE_MIO_WE(x) (((x) >> BIT_SHIFT_PCIE_MIO_WE) & BIT_MASK_PCIE_MIO_WE)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_HPON_FSM (Offset 0x00EC) */
-#define BIT_SHIFT_PCIE_MIO_ADDR 0
-#define BIT_MASK_PCIE_MIO_ADDR 0xff
-#define BIT_PCIE_MIO_ADDR(x) (((x) & BIT_MASK_PCIE_MIO_ADDR) << BIT_SHIFT_PCIE_MIO_ADDR)
-#define BIT_GET_PCIE_MIO_ADDR(x) (((x) >> BIT_SHIFT_PCIE_MIO_ADDR) & BIT_MASK_PCIE_MIO_ADDR)
+#define BIT_SHIFT_HCI_SEL_1 22
+#define BIT_MASK_HCI_SEL_1 0x3
+#define BIT_HCI_SEL_1(x) (((x) & BIT_MASK_HCI_SEL_1) << BIT_SHIFT_HCI_SEL_1)
+#define BITS_HCI_SEL_1 (BIT_MASK_HCI_SEL_1 << BIT_SHIFT_HCI_SEL_1)
+#define BIT_CLEAR_HCI_SEL_1(x) ((x) & (~BITS_HCI_SEL_1))
+#define BIT_GET_HCI_SEL_1(x) (((x) >> BIT_SHIFT_HCI_SEL_1) & BIT_MASK_HCI_SEL_1)
+#define BIT_SET_HCI_SEL_1(x, v) (BIT_CLEAR_HCI_SEL_1(x) | BIT_HCI_SEL_1(v))
+#define BIT_LOAD_DONE_V1 BIT(21)
+#define BIT_CNT_MATCH BIT(20)
+#define BIT_TIMEUP_V1 BIT(19)
+#define BIT_SPS_12V_VLD BIT(18)
+#define BIT_PCIERST_V1 BIT(17)
+#define BIT_HOST_CLK_VLD BIT(16)
-/* 2 REG_PCIE_MIO_INTD (Offset 0x00E8) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_PCIE_MIO_DATA 0
-#define BIT_MASK_PCIE_MIO_DATA 0xffffffffL
-#define BIT_PCIE_MIO_DATA(x) (((x) & BIT_MASK_PCIE_MIO_DATA) << BIT_SHIFT_PCIE_MIO_DATA)
-#define BIT_GET_PCIE_MIO_DATA(x) (((x) >> BIT_SHIFT_PCIE_MIO_DATA) & BIT_MASK_PCIE_MIO_DATA)
+/* 2 REG_WLRF1 (Offset 0x00EC) */
+#define BIT_SHIFT_WLRF2_CTRL 16
+#define BIT_MASK_WLRF2_CTRL 0xff
+#define BIT_WLRF2_CTRL(x) (((x) & BIT_MASK_WLRF2_CTRL) << BIT_SHIFT_WLRF2_CTRL)
+#define BITS_WLRF2_CTRL (BIT_MASK_WLRF2_CTRL << BIT_SHIFT_WLRF2_CTRL)
+#define BIT_CLEAR_WLRF2_CTRL(x) ((x) & (~BITS_WLRF2_CTRL))
+#define BIT_GET_WLRF2_CTRL(x) \
+ (((x) >> BIT_SHIFT_WLRF2_CTRL) & BIT_MASK_WLRF2_CTRL)
+#define BIT_SET_WLRF2_CTRL(x, v) (BIT_CLEAR_WLRF2_CTRL(x) | BIT_WLRF2_CTRL(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_HPON_FSM (Offset 0x00EC) */
-#define BIT_SUSPEND_V1 BIT(31)
-#define BIT_FSM_RESUME_V1 BIT(30)
-#define BIT_HOST_RESUME_SYNC_V1 BIT(29)
-#define BIT_CHIP_PDNB_V1 BIT(28)
+#define BIT_PMC_WR_V1 BIT(15)
+#define BIT_PMC_DATA_V1 BIT(14)
-#define BIT_SHIFT_FSM_SUSPEND_V1 25
-#define BIT_MASK_FSM_SUSPEND_V1 0x7
-#define BIT_FSM_SUSPEND_V1(x) (((x) & BIT_MASK_FSM_SUSPEND_V1) << BIT_SHIFT_FSM_SUSPEND_V1)
-#define BIT_GET_FSM_SUSPEND_V1(x) (((x) >> BIT_SHIFT_FSM_SUSPEND_V1) & BIT_MASK_FSM_SUSPEND_V1)
-
-#define BIT_PMC_ALD_V1 BIT(24)
+#define BIT_SHIFT_PMC_ADDR_V1 8
+#define BIT_MASK_PMC_ADDR_V1 0x3f
+#define BIT_PMC_ADDR_V1(x) \
+ (((x) & BIT_MASK_PMC_ADDR_V1) << BIT_SHIFT_PMC_ADDR_V1)
+#define BITS_PMC_ADDR_V1 (BIT_MASK_PMC_ADDR_V1 << BIT_SHIFT_PMC_ADDR_V1)
+#define BIT_CLEAR_PMC_ADDR_V1(x) ((x) & (~BITS_PMC_ADDR_V1))
+#define BIT_GET_PMC_ADDR_V1(x) \
+ (((x) >> BIT_SHIFT_PMC_ADDR_V1) & BIT_MASK_PMC_ADDR_V1)
+#define BIT_SET_PMC_ADDR_V1(x, v) \
+ (BIT_CLEAR_PMC_ADDR_V1(x) | BIT_PMC_ADDR_V1(v))
#endif
-
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_WLRF1 (Offset 0x00EC) */
-
-#define BIT_SHIFT_WLRF1_CTRL 24
-#define BIT_MASK_WLRF1_CTRL 0xff
-#define BIT_WLRF1_CTRL(x) (((x) & BIT_MASK_WLRF1_CTRL) << BIT_SHIFT_WLRF1_CTRL)
-#define BIT_GET_WLRF1_CTRL(x) (((x) >> BIT_SHIFT_WLRF1_CTRL) & BIT_MASK_WLRF1_CTRL)
-
+#define BIT_SHIFT_WLRF3_CTRL 8
+#define BIT_MASK_WLRF3_CTRL 0xff
+#define BIT_WLRF3_CTRL(x) (((x) & BIT_MASK_WLRF3_CTRL) << BIT_SHIFT_WLRF3_CTRL)
+#define BITS_WLRF3_CTRL (BIT_MASK_WLRF3_CTRL << BIT_SHIFT_WLRF3_CTRL)
+#define BIT_CLEAR_WLRF3_CTRL(x) ((x) & (~BITS_WLRF3_CTRL))
+#define BIT_GET_WLRF3_CTRL(x) \
+ (((x) >> BIT_SHIFT_WLRF3_CTRL) & BIT_MASK_WLRF3_CTRL)
+#define BIT_SET_WLRF3_CTRL(x, v) (BIT_CLEAR_WLRF3_CTRL(x) | BIT_WLRF3_CTRL(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_HPON_FSM (Offset 0x00EC) */
+#define BIT_PMC_COUNT_EN_V1 BIT(7)
-#define BIT_SHIFT_HCI_SEL_1 22
-#define BIT_MASK_HCI_SEL_1 0x3
-#define BIT_HCI_SEL_1(x) (((x) & BIT_MASK_HCI_SEL_1) << BIT_SHIFT_HCI_SEL_1)
-#define BIT_GET_HCI_SEL_1(x) (((x) >> BIT_SHIFT_HCI_SEL_1) & BIT_MASK_HCI_SEL_1)
-
-#define BIT_LOAD_DONE_V1 BIT(21)
-#define BIT_CNT_MATCH BIT(20)
-#define BIT_TIMEUP_V1 BIT(19)
-#define BIT_SPS_12V_VLD BIT(18)
-#define BIT_PCIERST_V1 BIT(17)
-#define BIT_HOST_CLK_VLD BIT(16)
-#define BIT_PMC_WR_V1 BIT(15)
-#define BIT_PMC_DATA_V1 BIT(14)
-
-#define BIT_SHIFT_PMC_ADDR_V1 8
-#define BIT_MASK_PMC_ADDR_V1 0x3f
-#define BIT_PMC_ADDR_V1(x) (((x) & BIT_MASK_PMC_ADDR_V1) << BIT_SHIFT_PMC_ADDR_V1)
-#define BIT_GET_PMC_ADDR_V1(x) (((x) >> BIT_SHIFT_PMC_ADDR_V1) & BIT_MASK_PMC_ADDR_V1)
-
-#define BIT_PMC_COUNT_EN_V1 BIT(7)
-
-#define BIT_SHIFT_FSM_STATE_V1 0
-#define BIT_MASK_FSM_STATE_V1 0x7f
-#define BIT_FSM_STATE_V1(x) (((x) & BIT_MASK_FSM_STATE_V1) << BIT_SHIFT_FSM_STATE_V1)
-#define BIT_GET_FSM_STATE_V1(x) (((x) >> BIT_SHIFT_FSM_STATE_V1) & BIT_MASK_FSM_STATE_V1)
-
+#define BIT_SHIFT_FSM_STATE_V1 0
+#define BIT_MASK_FSM_STATE_V1 0x7f
+#define BIT_FSM_STATE_V1(x) \
+ (((x) & BIT_MASK_FSM_STATE_V1) << BIT_SHIFT_FSM_STATE_V1)
+#define BITS_FSM_STATE_V1 (BIT_MASK_FSM_STATE_V1 << BIT_SHIFT_FSM_STATE_V1)
+#define BIT_CLEAR_FSM_STATE_V1(x) ((x) & (~BITS_FSM_STATE_V1))
+#define BIT_GET_FSM_STATE_V1(x) \
+ (((x) >> BIT_SHIFT_FSM_STATE_V1) & BIT_MASK_FSM_STATE_V1)
+#define BIT_SET_FSM_STATE_V1(x, v) \
+ (BIT_CLEAR_FSM_STATE_V1(x) | BIT_FSM_STATE_V1(v))
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-
-#define BIT_SHIFT_TRP_ICFG 28
-#define BIT_MASK_TRP_ICFG 0xf
-#define BIT_TRP_ICFG(x) (((x) & BIT_MASK_TRP_ICFG) << BIT_SHIFT_TRP_ICFG)
-#define BIT_GET_TRP_ICFG(x) (((x) >> BIT_SHIFT_TRP_ICFG) & BIT_MASK_TRP_ICFG)
-
+#define BIT_SHIFT_TRP_ICFG 28
+#define BIT_MASK_TRP_ICFG 0xf
+#define BIT_TRP_ICFG(x) (((x) & BIT_MASK_TRP_ICFG) << BIT_SHIFT_TRP_ICFG)
+#define BITS_TRP_ICFG (BIT_MASK_TRP_ICFG << BIT_SHIFT_TRP_ICFG)
+#define BIT_CLEAR_TRP_ICFG(x) ((x) & (~BITS_TRP_ICFG))
+#define BIT_GET_TRP_ICFG(x) (((x) >> BIT_SHIFT_TRP_ICFG) & BIT_MASK_TRP_ICFG)
+#define BIT_SET_TRP_ICFG(x, v) (BIT_CLEAR_TRP_ICFG(x) | BIT_TRP_ICFG(v))
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-#define BIT_RF_TYPE_ID BIT(27)
-#define BIT_BD_HCI_SEL BIT(26)
+#define BIT_RF_TYPE_ID BIT(27)
+#define BIT_BD_HCI_SEL BIT(26)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-
-#define BIT_SHIFT_BD_HCI_SEL 26
-#define BIT_MASK_BD_HCI_SEL 0x3
-#define BIT_BD_HCI_SEL(x) (((x) & BIT_MASK_BD_HCI_SEL) << BIT_SHIFT_BD_HCI_SEL)
-#define BIT_GET_BD_HCI_SEL(x) (((x) >> BIT_SHIFT_BD_HCI_SEL) & BIT_MASK_BD_HCI_SEL)
-
+#define BIT_SHIFT_BD_HCI_SEL_V1 26
+#define BIT_MASK_BD_HCI_SEL_V1 0x3
+#define BIT_BD_HCI_SEL_V1(x) \
+ (((x) & BIT_MASK_BD_HCI_SEL_V1) << BIT_SHIFT_BD_HCI_SEL_V1)
+#define BITS_BD_HCI_SEL_V1 (BIT_MASK_BD_HCI_SEL_V1 << BIT_SHIFT_BD_HCI_SEL_V1)
+#define BIT_CLEAR_BD_HCI_SEL_V1(x) ((x) & (~BITS_BD_HCI_SEL_V1))
+#define BIT_GET_BD_HCI_SEL_V1(x) \
+ (((x) >> BIT_SHIFT_BD_HCI_SEL_V1) & BIT_MASK_BD_HCI_SEL_V1)
+#define BIT_SET_BD_HCI_SEL_V1(x, v) \
+ (BIT_CLEAR_BD_HCI_SEL_V1(x) | BIT_BD_HCI_SEL_V1(v))
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-#define BIT_BD_PKG_SEL BIT(25)
+#define BIT_BD_PKG_SEL BIT(25)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-#define BIT_SPSLDO_SEL BIT(24)
+#define BIT_SPSLDO_SEL BIT(24)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-#define BIT_LDO_SPS_SEL BIT(24)
+#define BIT_LDO_SPS_SEL BIT(24)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8822C_SUPPORT)
/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-#define BIT_RTL_ID BIT(23)
-#define BIT_PAD_HWPD_IDN BIT(22)
+#define BIT_INTERNAL_EXTERNAL_SWR BIT(24)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-#define BIT_TESTMODE BIT(20)
+#define BIT_RTL_ID BIT(23)
+#define BIT_PAD_HWPD_IDN BIT(22)
#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-
-#define BIT_SHIFT_PSC_TESTCFG 20
-#define BIT_MASK_PSC_TESTCFG 0x3
-#define BIT_PSC_TESTCFG(x) (((x) & BIT_MASK_PSC_TESTCFG) << BIT_SHIFT_PSC_TESTCFG)
-#define BIT_GET_PSC_TESTCFG(x) (((x) >> BIT_SHIFT_PSC_TESTCFG) & BIT_MASK_PSC_TESTCFG)
-
+#define BIT_TESTMODE BIT(20)
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
+#define BIT_SHIFT_PSC_TESTCFG 20
+#define BIT_MASK_PSC_TESTCFG 0x3
+#define BIT_PSC_TESTCFG(x) \
+ (((x) & BIT_MASK_PSC_TESTCFG) << BIT_SHIFT_PSC_TESTCFG)
+#define BITS_PSC_TESTCFG (BIT_MASK_PSC_TESTCFG << BIT_SHIFT_PSC_TESTCFG)
+#define BIT_CLEAR_PSC_TESTCFG(x) ((x) & (~BITS_PSC_TESTCFG))
+#define BIT_GET_PSC_TESTCFG(x) \
+ (((x) >> BIT_SHIFT_PSC_TESTCFG) & BIT_MASK_PSC_TESTCFG)
+#define BIT_SET_PSC_TESTCFG(x, v) \
+ (BIT_CLEAR_PSC_TESTCFG(x) | BIT_PSC_TESTCFG(v))
-/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_VENDOR_ID 16
-#define BIT_MASK_VENDOR_ID 0xf
-#define BIT_VENDOR_ID(x) (((x) & BIT_MASK_VENDOR_ID) << BIT_SHIFT_VENDOR_ID)
-#define BIT_GET_VENDOR_ID(x) (((x) >> BIT_SHIFT_VENDOR_ID) & BIT_MASK_VENDOR_ID)
+/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
+#define BIT_SHIFT_VENDOR_ID 16
+#define BIT_MASK_VENDOR_ID 0xf
+#define BIT_VENDOR_ID(x) (((x) & BIT_MASK_VENDOR_ID) << BIT_SHIFT_VENDOR_ID)
+#define BITS_VENDOR_ID (BIT_MASK_VENDOR_ID << BIT_SHIFT_VENDOR_ID)
+#define BIT_CLEAR_VENDOR_ID(x) ((x) & (~BITS_VENDOR_ID))
+#define BIT_GET_VENDOR_ID(x) (((x) >> BIT_SHIFT_VENDOR_ID) & BIT_MASK_VENDOR_ID)
+#define BIT_SET_VENDOR_ID(x, v) (BIT_CLEAR_VENDOR_ID(x) | BIT_VENDOR_ID(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-
-#define BIT_SHIFT_CHIP_VER_V2 16
-#define BIT_MASK_CHIP_VER_V2 0xf
-#define BIT_CHIP_VER_V2(x) (((x) & BIT_MASK_CHIP_VER_V2) << BIT_SHIFT_CHIP_VER_V2)
-#define BIT_GET_CHIP_VER_V2(x) (((x) >> BIT_SHIFT_CHIP_VER_V2) & BIT_MASK_CHIP_VER_V2)
-
+#define BIT_SHIFT_CHIP_VER_V2 16
+#define BIT_MASK_CHIP_VER_V2 0xf
+#define BIT_CHIP_VER_V2(x) \
+ (((x) & BIT_MASK_CHIP_VER_V2) << BIT_SHIFT_CHIP_VER_V2)
+#define BITS_CHIP_VER_V2 (BIT_MASK_CHIP_VER_V2 << BIT_SHIFT_CHIP_VER_V2)
+#define BIT_CLEAR_CHIP_VER_V2(x) ((x) & (~BITS_CHIP_VER_V2))
+#define BIT_GET_CHIP_VER_V2(x) \
+ (((x) >> BIT_SHIFT_CHIP_VER_V2) & BIT_MASK_CHIP_VER_V2)
+#define BIT_SET_CHIP_VER_V2(x, v) \
+ (BIT_CLEAR_CHIP_VER_V2(x) | BIT_CHIP_VER_V2(v))
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-
-#define BIT_SHIFT_CHIP_VER 12
-#define BIT_MASK_CHIP_VER 0xf
-#define BIT_CHIP_VER(x) (((x) & BIT_MASK_CHIP_VER) << BIT_SHIFT_CHIP_VER)
-#define BIT_GET_CHIP_VER(x) (((x) >> BIT_SHIFT_CHIP_VER) & BIT_MASK_CHIP_VER)
-
+#define BIT_SHIFT_CHIP_VER 12
+#define BIT_MASK_CHIP_VER 0xf
+#define BIT_CHIP_VER(x) (((x) & BIT_MASK_CHIP_VER) << BIT_SHIFT_CHIP_VER)
+#define BITS_CHIP_VER (BIT_MASK_CHIP_VER << BIT_SHIFT_CHIP_VER)
+#define BIT_CLEAR_CHIP_VER(x) ((x) & (~BITS_CHIP_VER))
+#define BIT_GET_CHIP_VER(x) (((x) >> BIT_SHIFT_CHIP_VER) & BIT_MASK_CHIP_VER)
+#define BIT_SET_CHIP_VER(x, v) (BIT_CLEAR_CHIP_VER(x) | BIT_CHIP_VER(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-#define BIT_IC_MACPHY_MODE BIT(11)
+#define BIT_IC_MACPHY_MODE BIT(11)
#endif
-
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-#define BIT_BD_MAC3 BIT(11)
+#define BIT_BD_MAC3 BIT(11)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-#define BIT_BD_MAC1 BIT(10)
-#define BIT_BD_MAC2 BIT(9)
-#define BIT_SIC_IDLE BIT(8)
-#define BIT_SW_OFFLOAD_EN BIT(7)
+#define BIT_BD_MAC1 BIT(10)
+#define BIT_BD_MAC2 BIT(9)
+#define BIT_SIC_IDLE BIT(8)
+#define BIT_SW_OFFLOAD_EN BIT(7)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-#define BIT_OCP_SHUTDN BIT(6)
+#define BIT_OCP_SHUTDN BIT(6)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-#define BIT_OCP_SHUTDN_1 BIT(6)
+#define BIT_OCP_SHUTDN_1 BIT(6)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-#define BIT_V15_VLD BIT(5)
+#define BIT_V15_VLD BIT(5)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-#define BIT_V12_VLD BIT(5)
+#define BIT_V12_VLD BIT(5)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-#define BIT_PCIRSTB BIT(4)
+#define BIT_PCIRSTB BIT(4)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-#define BIT_PCLK_VLD BIT(3)
+#define BIT_PCLK_VLD BIT(3)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-#define BIT_PCLK_VLD_1 BIT(3)
+#define BIT_PCLK_VLD_1 BIT(3)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-#define BIT_UCLK_VLD BIT(2)
+#define BIT_UCLK_VLD BIT(2)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-#define BIT_ACLK_VLD BIT(1)
+#define BIT_ACLK_VLD BIT(1)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-#define BIT_M200CLK_VLD_V1 BIT(1)
+#define BIT_M200CLK_VLD_V1 BIT(1)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_CFG1 (Offset 0x00F0) */
-#define BIT_XCLK_VLD BIT(0)
+#define BIT_XCLK_VLD BIT(0)
/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */
-
-#define BIT_SHIFT_RF_RL_ID 28
-#define BIT_MASK_RF_RL_ID 0xf
-#define BIT_RF_RL_ID(x) (((x) & BIT_MASK_RF_RL_ID) << BIT_SHIFT_RF_RL_ID)
-#define BIT_GET_RF_RL_ID(x) (((x) >> BIT_SHIFT_RF_RL_ID) & BIT_MASK_RF_RL_ID)
-
+#define BIT_SHIFT_RF_RL_ID 28
+#define BIT_MASK_RF_RL_ID 0xf
+#define BIT_RF_RL_ID(x) (((x) & BIT_MASK_RF_RL_ID) << BIT_SHIFT_RF_RL_ID)
+#define BITS_RF_RL_ID (BIT_MASK_RF_RL_ID << BIT_SHIFT_RF_RL_ID)
+#define BIT_CLEAR_RF_RL_ID(x) ((x) & (~BITS_RF_RL_ID))
+#define BIT_GET_RF_RL_ID(x) (((x) >> BIT_SHIFT_RF_RL_ID) & BIT_MASK_RF_RL_ID)
+#define BIT_SET_RF_RL_ID(x, v) (BIT_CLEAR_RF_RL_ID(x) | BIT_RF_RL_ID(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */
-#define BIT_U3_CLK_VLD BIT(27)
-#define BIT_PRST_VLD_V1 BIT(26)
-#define BIT_PDN BIT(25)
-#define BIT_OCP_SHUTDN_V1 BIT(24)
-#define BIT_PCLK_VLD_V1 BIT(23)
-#define BIT_U2_CLK_VLD BIT(22)
-#define BIT_PLL_CLK_VLD BIT(21)
-#define BIT_XCK_VLD BIT(20)
+#define BIT_U3_CLK_VLD BIT(27)
+#define BIT_PRST_VLD_V1 BIT(26)
+#define BIT_PDN BIT(25)
+#define BIT_OCP_SHUTDN_V1 BIT(24)
+#define BIT_PCLK_VLD_V1 BIT(23)
+#define BIT_U2_CLK_VLD BIT(22)
+#define BIT_PLL_CLK_VLD BIT(21)
+#define BIT_XCK_VLD BIT(20)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */
-#define BIT_HPHY_ICFG BIT(19)
+#define BIT_HPHY_ICFG BIT(19)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */
-#define BIT_CK200M_VLD BIT(19)
-#define BIT_BTEN_TRAP BIT(18)
-#define BIT_PKG_EN_V1 BIT(17)
+#define BIT_CK200M_VLD BIT(19)
+#define BIT_BTEN_TRAP BIT(18)
+#define BIT_PKG_EN_V1 BIT(17)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */
-
-#define BIT_SHIFT_SEL_0XC0 16
-#define BIT_MASK_SEL_0XC0 0x3
-#define BIT_SEL_0XC0(x) (((x) & BIT_MASK_SEL_0XC0) << BIT_SHIFT_SEL_0XC0)
-#define BIT_GET_SEL_0XC0(x) (((x) >> BIT_SHIFT_SEL_0XC0) & BIT_MASK_SEL_0XC0)
-
+#define BIT_SHIFT_SEL_0XC0 16
+#define BIT_MASK_SEL_0XC0 0x3
+#define BIT_SEL_0XC0(x) (((x) & BIT_MASK_SEL_0XC0) << BIT_SHIFT_SEL_0XC0)
+#define BITS_SEL_0XC0 (BIT_MASK_SEL_0XC0 << BIT_SHIFT_SEL_0XC0)
+#define BIT_CLEAR_SEL_0XC0(x) ((x) & (~BITS_SEL_0XC0))
+#define BIT_GET_SEL_0XC0(x) (((x) >> BIT_SHIFT_SEL_0XC0) & BIT_MASK_SEL_0XC0)
+#define BIT_SET_SEL_0XC0(x, v) (BIT_CLEAR_SEL_0XC0(x) | BIT_SEL_0XC0(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */
-#define BIT_TRAP_LDO_SPS_V1 BIT(16)
-#define BIT_MACRDY BIT(15)
-#define BIT_12V_VLD BIT(14)
-#define BIT_U3PHY_RST BIT(13)
-#define BIT_USB2_SEL_V1 BIT(12)
+#define BIT_TRAP_LDO_SPS_V1 BIT(16)
+#define BIT_MACRDY BIT(15)
+#define BIT_12V_VLD BIT(14)
+#define BIT_U3PHY_RST BIT(13)
+#define BIT_USB2_SEL_V1 BIT(12)
#endif
-
-#if (HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */
+#define BIT_SHIFT_HCI_SEL_V4 12
+#define BIT_MASK_HCI_SEL_V4 0x3
+#define BIT_HCI_SEL_V4(x) (((x) & BIT_MASK_HCI_SEL_V4) << BIT_SHIFT_HCI_SEL_V4)
+#define BITS_HCI_SEL_V4 (BIT_MASK_HCI_SEL_V4 << BIT_SHIFT_HCI_SEL_V4)
+#define BIT_CLEAR_HCI_SEL_V4(x) ((x) & (~BITS_HCI_SEL_V4))
+#define BIT_GET_HCI_SEL_V4(x) \
+ (((x) >> BIT_SHIFT_HCI_SEL_V4) & BIT_MASK_HCI_SEL_V4)
+#define BIT_SET_HCI_SEL_V4(x, v) (BIT_CLEAR_HCI_SEL_V4(x) | BIT_HCI_SEL_V4(v))
-#define BIT_SHIFT_HCI_SEL_V3 12
-#define BIT_MASK_HCI_SEL_V3 0x7
-#define BIT_HCI_SEL_V3(x) (((x) & BIT_MASK_HCI_SEL_V3) << BIT_SHIFT_HCI_SEL_V3)
-#define BIT_GET_HCI_SEL_V3(x) (((x) >> BIT_SHIFT_HCI_SEL_V3) & BIT_MASK_HCI_SEL_V3)
+#endif
+#if (HALMAC_8822B_SUPPORT)
-#endif
+/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */
+#define BIT_SHIFT_HCI_SEL_V3 12
+#define BIT_MASK_HCI_SEL_V3 0x7
+#define BIT_HCI_SEL_V3(x) (((x) & BIT_MASK_HCI_SEL_V3) << BIT_SHIFT_HCI_SEL_V3)
+#define BITS_HCI_SEL_V3 (BIT_MASK_HCI_SEL_V3 << BIT_SHIFT_HCI_SEL_V3)
+#define BIT_CLEAR_HCI_SEL_V3(x) ((x) & (~BITS_HCI_SEL_V3))
+#define BIT_GET_HCI_SEL_V3(x) \
+ (((x) >> BIT_SHIFT_HCI_SEL_V3) & BIT_MASK_HCI_SEL_V3)
+#define BIT_SET_HCI_SEL_V3(x, v) (BIT_CLEAR_HCI_SEL_V3(x) | BIT_HCI_SEL_V3(v))
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */
-#define BIT_USB_OPERATION_MODE BIT(10)
-#define BIT_BT_PDN BIT(9)
-#define BIT_AUTO_WLPON BIT(8)
+#define BIT_USB_OPERATION_MODE BIT(10)
+#define BIT_BT_PDN BIT(9)
+#define BIT_AUTO_WLPON BIT(8)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */
-
-#define BIT_SHIFT_TRAP_ICFG 8
-#define BIT_MASK_TRAP_ICFG 0xf
-#define BIT_TRAP_ICFG(x) (((x) & BIT_MASK_TRAP_ICFG) << BIT_SHIFT_TRAP_ICFG)
-#define BIT_GET_TRAP_ICFG(x) (((x) >> BIT_SHIFT_TRAP_ICFG) & BIT_MASK_TRAP_ICFG)
-
+#define BIT_SHIFT_TRAP_ICFG 8
+#define BIT_MASK_TRAP_ICFG 0xf
+#define BIT_TRAP_ICFG(x) (((x) & BIT_MASK_TRAP_ICFG) << BIT_SHIFT_TRAP_ICFG)
+#define BITS_TRAP_ICFG (BIT_MASK_TRAP_ICFG << BIT_SHIFT_TRAP_ICFG)
+#define BIT_CLEAR_TRAP_ICFG(x) ((x) & (~BITS_TRAP_ICFG))
+#define BIT_GET_TRAP_ICFG(x) (((x) >> BIT_SHIFT_TRAP_ICFG) & BIT_MASK_TRAP_ICFG)
+#define BIT_SET_TRAP_ICFG(x, v) (BIT_CLEAR_TRAP_ICFG(x) | BIT_TRAP_ICFG(v))
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */
-#define BIT_WL_MODE BIT(7)
+#define BIT_WL_MODE BIT(7)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */
-#define BIT_WLAN_ID BIT(7)
+#define BIT_WLAN_ID BIT(7)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */
-#define BIT_PKG_SEL_HCI BIT(6)
+#define BIT_PKG_SEL_HCI BIT(6)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */
-#define BIT_ALDN BIT(6)
-#define BIT_BTCOEX_CMDEN BIT(5)
+#define BIT_ALDN BIT(6)
+#define BIT_BTCOEX_CMDEN BIT(5)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */
-
-#define BIT_SHIFT_HCI_SEL 4
-#define BIT_MASK_HCI_SEL 0x3
-#define BIT_HCI_SEL(x) (((x) & BIT_MASK_HCI_SEL) << BIT_SHIFT_HCI_SEL)
-#define BIT_GET_HCI_SEL(x) (((x) >> BIT_SHIFT_HCI_SEL) & BIT_MASK_HCI_SEL)
-
+#define BIT_SHIFT_HCI_SEL 4
+#define BIT_MASK_HCI_SEL 0x3
+#define BIT_HCI_SEL(x) (((x) & BIT_MASK_HCI_SEL) << BIT_SHIFT_HCI_SEL)
+#define BITS_HCI_SEL (BIT_MASK_HCI_SEL << BIT_SHIFT_HCI_SEL)
+#define BIT_CLEAR_HCI_SEL(x) ((x) & (~BITS_HCI_SEL))
+#define BIT_GET_HCI_SEL(x) (((x) >> BIT_SHIFT_HCI_SEL) & BIT_MASK_HCI_SEL)
+#define BIT_SET_HCI_SEL(x, v) (BIT_CLEAR_HCI_SEL(x) | BIT_HCI_SEL(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */
-#define BIT_BT_EN BIT(4)
+#define BIT_BT_EN BIT(4)
#endif
-
-#if (HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */
-
-#define BIT_SHIFT_PAD_HCI_SEL_V1 3
-#define BIT_MASK_PAD_HCI_SEL_V1 0x7
-#define BIT_PAD_HCI_SEL_V1(x) (((x) & BIT_MASK_PAD_HCI_SEL_V1) << BIT_SHIFT_PAD_HCI_SEL_V1)
-#define BIT_GET_PAD_HCI_SEL_V1(x) (((x) >> BIT_SHIFT_PAD_HCI_SEL_V1) & BIT_MASK_PAD_HCI_SEL_V1)
-
+#define BIT_SHIFT_PAD_HCI_SEL_V2 3
+#define BIT_MASK_PAD_HCI_SEL_V2 0x3
+#define BIT_PAD_HCI_SEL_V2(x) \
+ (((x) & BIT_MASK_PAD_HCI_SEL_V2) << BIT_SHIFT_PAD_HCI_SEL_V2)
+#define BITS_PAD_HCI_SEL_V2 \
+ (BIT_MASK_PAD_HCI_SEL_V2 << BIT_SHIFT_PAD_HCI_SEL_V2)
+#define BIT_CLEAR_PAD_HCI_SEL_V2(x) ((x) & (~BITS_PAD_HCI_SEL_V2))
+#define BIT_GET_PAD_HCI_SEL_V2(x) \
+ (((x) >> BIT_SHIFT_PAD_HCI_SEL_V2) & BIT_MASK_PAD_HCI_SEL_V2)
+#define BIT_SET_PAD_HCI_SEL_V2(x, v) \
+ (BIT_CLEAR_PAD_HCI_SEL_V2(x) | BIT_PAD_HCI_SEL_V2(v))
#endif
+#if (HALMAC_8822B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */
+#define BIT_SHIFT_PAD_HCI_SEL_V1 3
+#define BIT_MASK_PAD_HCI_SEL_V1 0x7
+#define BIT_PAD_HCI_SEL_V1(x) \
+ (((x) & BIT_MASK_PAD_HCI_SEL_V1) << BIT_SHIFT_PAD_HCI_SEL_V1)
+#define BITS_PAD_HCI_SEL_V1 \
+ (BIT_MASK_PAD_HCI_SEL_V1 << BIT_SHIFT_PAD_HCI_SEL_V1)
+#define BIT_CLEAR_PAD_HCI_SEL_V1(x) ((x) & (~BITS_PAD_HCI_SEL_V1))
+#define BIT_GET_PAD_HCI_SEL_V1(x) \
+ (((x) >> BIT_SHIFT_PAD_HCI_SEL_V1) & BIT_MASK_PAD_HCI_SEL_V1)
+#define BIT_SET_PAD_HCI_SEL_V1(x, v) \
+ (BIT_CLEAR_PAD_HCI_SEL_V1(x) | BIT_PAD_HCI_SEL_V1(v))
-/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_PAD_HCI_SEL 2
-#define BIT_MASK_PAD_HCI_SEL 0x3
-#define BIT_PAD_HCI_SEL(x) (((x) & BIT_MASK_PAD_HCI_SEL) << BIT_SHIFT_PAD_HCI_SEL)
-#define BIT_GET_PAD_HCI_SEL(x) (((x) >> BIT_SHIFT_PAD_HCI_SEL) & BIT_MASK_PAD_HCI_SEL)
+/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */
+#define BIT_SHIFT_PAD_HCI_SEL 2
+#define BIT_MASK_PAD_HCI_SEL 0x3
+#define BIT_PAD_HCI_SEL(x) \
+ (((x) & BIT_MASK_PAD_HCI_SEL) << BIT_SHIFT_PAD_HCI_SEL)
+#define BITS_PAD_HCI_SEL (BIT_MASK_PAD_HCI_SEL << BIT_SHIFT_PAD_HCI_SEL)
+#define BIT_CLEAR_PAD_HCI_SEL(x) ((x) & (~BITS_PAD_HCI_SEL))
+#define BIT_GET_PAD_HCI_SEL(x) \
+ (((x) >> BIT_SHIFT_PAD_HCI_SEL) & BIT_MASK_PAD_HCI_SEL)
+#define BIT_SET_PAD_HCI_SEL(x, v) \
+ (BIT_CLEAR_PAD_HCI_SEL(x) | BIT_PAD_HCI_SEL(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */
+#define BIT_SHIFT_HCI_SEL_V2 2
+#define BIT_MASK_HCI_SEL_V2 0x3
+#define BIT_HCI_SEL_V2(x) (((x) & BIT_MASK_HCI_SEL_V2) << BIT_SHIFT_HCI_SEL_V2)
+#define BITS_HCI_SEL_V2 (BIT_MASK_HCI_SEL_V2 << BIT_SHIFT_HCI_SEL_V2)
+#define BIT_CLEAR_HCI_SEL_V2(x) ((x) & (~BITS_HCI_SEL_V2))
+#define BIT_GET_HCI_SEL_V2(x) \
+ (((x) >> BIT_SHIFT_HCI_SEL_V2) & BIT_MASK_HCI_SEL_V2)
+#define BIT_SET_HCI_SEL_V2(x, v) (BIT_CLEAR_HCI_SEL_V2(x) | BIT_HCI_SEL_V2(v))
-#define BIT_SHIFT_HCI_SEL_V2 2
-#define BIT_MASK_HCI_SEL_V2 0x3
-#define BIT_HCI_SEL_V2(x) (((x) & BIT_MASK_HCI_SEL_V2) << BIT_SHIFT_HCI_SEL_V2)
-#define BIT_GET_HCI_SEL_V2(x) (((x) >> BIT_SHIFT_HCI_SEL_V2) & BIT_MASK_HCI_SEL_V2)
-
-#define BIT_TST_MOD_SEL BIT(1)
+#define BIT_TST_MOD_SEL BIT(1)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */
-
-#define BIT_SHIFT_EFS_HCI_SEL 0
-#define BIT_MASK_EFS_HCI_SEL 0x3
-#define BIT_EFS_HCI_SEL(x) (((x) & BIT_MASK_EFS_HCI_SEL) << BIT_SHIFT_EFS_HCI_SEL)
-#define BIT_GET_EFS_HCI_SEL(x) (((x) >> BIT_SHIFT_EFS_HCI_SEL) & BIT_MASK_EFS_HCI_SEL)
-
+#define BIT_SHIFT_EFS_HCI_SEL 0
+#define BIT_MASK_EFS_HCI_SEL 0x3
+#define BIT_EFS_HCI_SEL(x) \
+ (((x) & BIT_MASK_EFS_HCI_SEL) << BIT_SHIFT_EFS_HCI_SEL)
+#define BITS_EFS_HCI_SEL (BIT_MASK_EFS_HCI_SEL << BIT_SHIFT_EFS_HCI_SEL)
+#define BIT_CLEAR_EFS_HCI_SEL(x) ((x) & (~BITS_EFS_HCI_SEL))
+#define BIT_GET_EFS_HCI_SEL(x) \
+ (((x) >> BIT_SHIFT_EFS_HCI_SEL) & BIT_MASK_EFS_HCI_SEL)
+#define BIT_SET_EFS_HCI_SEL(x, v) \
+ (BIT_CLEAR_EFS_HCI_SEL(x) | BIT_EFS_HCI_SEL(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */
-#define BIT_PAD_HWPDB BIT(0)
+#define BIT_PAD_HWPDB BIT(0)
#endif
-
-#if (HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_SYS_STATUS1 (Offset 0x00F4) */
-
-#define BIT_SHIFT_EFS_HCI_SEL_V1 0
-#define BIT_MASK_EFS_HCI_SEL_V1 0x7
-#define BIT_EFS_HCI_SEL_V1(x) (((x) & BIT_MASK_EFS_HCI_SEL_V1) << BIT_SHIFT_EFS_HCI_SEL_V1)
-#define BIT_GET_EFS_HCI_SEL_V1(x) (((x) >> BIT_SHIFT_EFS_HCI_SEL_V1) & BIT_MASK_EFS_HCI_SEL_V1)
-
+#define BIT_SHIFT_EFS_HCI_SEL_V1 0
+#define BIT_MASK_EFS_HCI_SEL_V1 0x7
+#define BIT_EFS_HCI_SEL_V1(x) \
+ (((x) & BIT_MASK_EFS_HCI_SEL_V1) << BIT_SHIFT_EFS_HCI_SEL_V1)
+#define BITS_EFS_HCI_SEL_V1 \
+ (BIT_MASK_EFS_HCI_SEL_V1 << BIT_SHIFT_EFS_HCI_SEL_V1)
+#define BIT_CLEAR_EFS_HCI_SEL_V1(x) ((x) & (~BITS_EFS_HCI_SEL_V1))
+#define BIT_GET_EFS_HCI_SEL_V1(x) \
+ (((x) >> BIT_SHIFT_EFS_HCI_SEL_V1) & BIT_MASK_EFS_HCI_SEL_V1)
+#define BIT_SET_EFS_HCI_SEL_V1(x, v) \
+ (BIT_CLEAR_EFS_HCI_SEL_V1(x) | BIT_EFS_HCI_SEL_V1(v))
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_SYS_STATUS2 (Offset 0x00F8) */
+#define BIT_HIOE_ON_TIMEOUT BIT(23)
+#define BIT_SIC_ON_TIMEOUT BIT(22)
+#define BIT_CPU_ON_TIMEOUT BIT(21)
+#define BIT_HCI_ON_TIMEOUT BIT(20)
-/* 2 REG_SYS_STATUS2 (Offset 0x00F8) */
+#endif
-#define BIT_SIO_ALDN BIT(19)
-#define BIT_USB_ALDN BIT(18)
-#define BIT_PCI_ALDN BIT(17)
-#define BIT_SYS_ALDN BIT(16)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_EPVID1 8
-#define BIT_MASK_EPVID1 0xff
-#define BIT_EPVID1(x) (((x) & BIT_MASK_EPVID1) << BIT_SHIFT_EPVID1)
-#define BIT_GET_EPVID1(x) (((x) >> BIT_SHIFT_EPVID1) & BIT_MASK_EPVID1)
+/* 2 REG_SYS_STATUS2 (Offset 0x00F8) */
+#define BIT_SIO_ALDN BIT(19)
+#define BIT_USB_ALDN BIT(18)
+#define BIT_PCI_ALDN BIT(17)
+#define BIT_SYS_ALDN BIT(16)
-#define BIT_SHIFT_EPVID0 0
-#define BIT_MASK_EPVID0 0xff
-#define BIT_EPVID0(x) (((x) & BIT_MASK_EPVID0) << BIT_SHIFT_EPVID0)
-#define BIT_GET_EPVID0(x) (((x) >> BIT_SHIFT_EPVID0) & BIT_MASK_EPVID0)
+#define BIT_SHIFT_EPVID1 8
+#define BIT_MASK_EPVID1 0xff
+#define BIT_EPVID1(x) (((x) & BIT_MASK_EPVID1) << BIT_SHIFT_EPVID1)
+#define BITS_EPVID1 (BIT_MASK_EPVID1 << BIT_SHIFT_EPVID1)
+#define BIT_CLEAR_EPVID1(x) ((x) & (~BITS_EPVID1))
+#define BIT_GET_EPVID1(x) (((x) >> BIT_SHIFT_EPVID1) & BIT_MASK_EPVID1)
+#define BIT_SET_EPVID1(x, v) (BIT_CLEAR_EPVID1(x) | BIT_EPVID1(v))
+#define BIT_SHIFT_EPVID0 0
+#define BIT_MASK_EPVID0 0xff
+#define BIT_EPVID0(x) (((x) & BIT_MASK_EPVID0) << BIT_SHIFT_EPVID0)
+#define BITS_EPVID0 (BIT_MASK_EPVID0 << BIT_SHIFT_EPVID0)
+#define BIT_CLEAR_EPVID0(x) ((x) & (~BITS_EPVID0))
+#define BIT_GET_EPVID0(x) (((x) >> BIT_SHIFT_EPVID0) & BIT_MASK_EPVID0)
+#define BIT_SET_EPVID0(x, v) (BIT_CLEAR_EPVID0(x) | BIT_EPVID0(v))
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_CFG2 (Offset 0x00FC) */
-#define BIT_USB2_SEL_1 BIT(31)
-#define BIT_USB3PHY_RST BIT(30)
-#define BIT_U3_TERM_DET BIT(29)
-#define BIT_USB23_DBG_SEL BIT(24)
+#define BIT_USB2_SEL_1 BIT(31)
#endif
-
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_SYS_CFG2 (Offset 0x00FC) */
-#define BIT_HCI_SEL_EMBEDED BIT(8)
+#define BIT_USB2_SEL BIT(31)
+#define BIT_FEN_WLMAC_OFF BIT(31)
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_SYS_CFG2 (Offset 0x00FC) */
+#define BIT_USB3PHY_RST BIT(30)
-/* 2 REG_SYS_CFG2 (Offset 0x00FC) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_HW_ID 0
-#define BIT_MASK_HW_ID 0xff
-#define BIT_HW_ID(x) (((x) & BIT_MASK_HW_ID) << BIT_SHIFT_HW_ID)
-#define BIT_GET_HW_ID(x) (((x) >> BIT_SHIFT_HW_ID) & BIT_MASK_HW_ID)
+/* 2 REG_SYS_CFG2 (Offset 0x00FC) */
+#define BIT_U3PHY_RST_V1 BIT(30)
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_SYS_CFG2 (Offset 0x00FC) */
+#define BIT_U3_TERM_DET BIT(29)
-#define BIT_SHIFT_CHIPID 0
-#define BIT_MASK_CHIPID 0xff
-#define BIT_CHIPID(x) (((x) & BIT_MASK_CHIPID) << BIT_SHIFT_CHIPID)
-#define BIT_GET_CHIPID(x) (((x) >> BIT_SHIFT_CHIPID) & BIT_MASK_CHIPID)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_SYS_CFG2 (Offset 0x00FC) */
+#define BIT_U3_TERM_DETECT BIT(29)
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-/* 2 REG_CR (Offset 0x0100) */
+/* 2 REG_SYS_CFG2 (Offset 0x00FC) */
-#define BIT_MACIO_TIMEOUT_EN BIT(29)
+#define BIT_USB23_DBG_SEL BIT(24)
#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_SYS_CFG2 (Offset 0x00FC) */
+#define BIT_HCI_SEL_EMBEDDED BIT(8)
-/* 2 REG_CR (Offset 0x0100) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_LBMODE 24
-#define BIT_MASK_LBMODE 0x1f
-#define BIT_LBMODE(x) (((x) & BIT_MASK_LBMODE) << BIT_SHIFT_LBMODE)
-#define BIT_GET_LBMODE(x) (((x) >> BIT_SHIFT_LBMODE) & BIT_MASK_LBMODE)
+/* 2 REG_SYS_CFG2 (Offset 0x00FC) */
+#define BIT_ISO_BB2PP BIT(7)
+#define BIT_ISO_DENG2PP BIT(6)
-#define BIT_SHIFT_NETYPE1 18
-#define BIT_MASK_NETYPE1 0x3
-#define BIT_NETYPE1(x) (((x) & BIT_MASK_NETYPE1) << BIT_SHIFT_NETYPE1)
-#define BIT_GET_NETYPE1(x) (((x) >> BIT_SHIFT_NETYPE1) & BIT_MASK_NETYPE1)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_NETYPE0 16
-#define BIT_MASK_NETYPE0 0x3
-#define BIT_NETYPE0(x) (((x) & BIT_MASK_NETYPE0) << BIT_SHIFT_NETYPE0)
-#define BIT_GET_NETYPE0(x) (((x) >> BIT_SHIFT_NETYPE0) & BIT_MASK_NETYPE0)
+/* 2 REG_SYS_CFG2 (Offset 0x00FC) */
+#define BIT_SHIFT_HW_ID 0
+#define BIT_MASK_HW_ID 0xff
+#define BIT_HW_ID(x) (((x) & BIT_MASK_HW_ID) << BIT_SHIFT_HW_ID)
+#define BITS_HW_ID (BIT_MASK_HW_ID << BIT_SHIFT_HW_ID)
+#define BIT_CLEAR_HW_ID(x) ((x) & (~BITS_HW_ID))
+#define BIT_GET_HW_ID(x) (((x) >> BIT_SHIFT_HW_ID) & BIT_MASK_HW_ID)
+#define BIT_SET_HW_ID(x, v) (BIT_CLEAR_HW_ID(x) | BIT_HW_ID(v))
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_SYS_CFG2 (Offset 0x00FC) */
+
+#define BIT_SHIFT_CHIPID 0
+#define BIT_MASK_CHIPID 0xff
+#define BIT_CHIPID(x) (((x) & BIT_MASK_CHIPID) << BIT_SHIFT_CHIPID)
+#define BITS_CHIPID (BIT_MASK_CHIPID << BIT_SHIFT_CHIPID)
+#define BIT_CLEAR_CHIPID(x) ((x) & (~BITS_CHIPID))
+#define BIT_GET_CHIPID(x) (((x) >> BIT_SHIFT_CHIPID) & BIT_MASK_CHIPID)
+#define BIT_SET_CHIPID(x, v) (BIT_CLEAR_CHIPID(x) | BIT_CHIPID(v))
+
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_CR (Offset 0x0100) */
-#define BIT_STAT_FUNC_RST BIT(13)
+#define BIT_MACIO_TIMEOUT_EN BIT(29)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_CR (Offset 0x0100) */
+#define BIT_SHIFT_LBMODE 24
+#define BIT_MASK_LBMODE 0x1f
+#define BIT_LBMODE(x) (((x) & BIT_MASK_LBMODE) << BIT_SHIFT_LBMODE)
+#define BITS_LBMODE (BIT_MASK_LBMODE << BIT_SHIFT_LBMODE)
+#define BIT_CLEAR_LBMODE(x) ((x) & (~BITS_LBMODE))
+#define BIT_GET_LBMODE(x) (((x) >> BIT_SHIFT_LBMODE) & BIT_MASK_LBMODE)
+#define BIT_SET_LBMODE(x, v) (BIT_CLEAR_LBMODE(x) | BIT_LBMODE(v))
-/* 2 REG_CR (Offset 0x0100) */
+#define BIT_SHIFT_NETYPE1 18
+#define BIT_MASK_NETYPE1 0x3
+#define BIT_NETYPE1(x) (((x) & BIT_MASK_NETYPE1) << BIT_SHIFT_NETYPE1)
+#define BITS_NETYPE1 (BIT_MASK_NETYPE1 << BIT_SHIFT_NETYPE1)
+#define BIT_CLEAR_NETYPE1(x) ((x) & (~BITS_NETYPE1))
+#define BIT_GET_NETYPE1(x) (((x) >> BIT_SHIFT_NETYPE1) & BIT_MASK_NETYPE1)
+#define BIT_SET_NETYPE1(x, v) (BIT_CLEAR_NETYPE1(x) | BIT_NETYPE1(v))
-#define BIT_PTA_I2C_MBOX_EN BIT(12)
+#define BIT_SHIFT_NETYPE0 16
+#define BIT_MASK_NETYPE0 0x3
+#define BIT_NETYPE0(x) (((x) & BIT_MASK_NETYPE0) << BIT_SHIFT_NETYPE0)
+#define BITS_NETYPE0 (BIT_MASK_NETYPE0 << BIT_SHIFT_NETYPE0)
+#define BIT_CLEAR_NETYPE0(x) ((x) & (~BITS_NETYPE0))
+#define BIT_GET_NETYPE0(x) (((x) >> BIT_SHIFT_NETYPE0) & BIT_MASK_NETYPE0)
+#define BIT_SET_NETYPE0(x, v) (BIT_CLEAR_NETYPE0(x) | BIT_NETYPE0(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_CR (Offset 0x0100) */
+
+#define BIT_STAT_FUNC_RST BIT(13)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_CR (Offset 0x0100) */
-#define BIT_I2C_MAILBOX_EN BIT(12)
-#define BIT_SHCUT_EN BIT(11)
+#define BIT_COUNTER_STS_EN BIT(13)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_CR (Offset 0x0100) */
+
+#define BIT_PTA_I2C_MBOX_EN BIT(12)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_CR (Offset 0x0100) */
-#define BIT_32K_CAL_TMR_EN BIT(10)
-#define BIT_MAC_SEC_EN BIT(9)
-#define BIT_ENSWBCN BIT(8)
-#define BIT_MACRXEN BIT(7)
-#define BIT_MACTXEN BIT(6)
-#define BIT_SCHEDULE_EN BIT(5)
-#define BIT_PROTOCOL_EN BIT(4)
-#define BIT_RXDMA_EN BIT(3)
-#define BIT_TXDMA_EN BIT(2)
-#define BIT_HCI_RXDMA_EN BIT(1)
-#define BIT_HCI_TXDMA_EN BIT(0)
+#define BIT_I2C_MAILBOX_EN BIT(12)
+#define BIT_SHCUT_EN BIT(11)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_CR (Offset 0x0100) */
+#define BIT_32K_CAL_TMR_EN BIT(10)
+#define BIT_MAC_SEC_EN BIT(9)
+#define BIT_ENSWBCN BIT(8)
+#define BIT_MACRXEN BIT(7)
+#define BIT_MACTXEN BIT(6)
+#define BIT_SCHEDULE_EN BIT(5)
+#define BIT_PROTOCOL_EN BIT(4)
+#define BIT_RXDMA_EN BIT(3)
+#define BIT_TXDMA_EN BIT(2)
+#define BIT_HCI_RXDMA_EN BIT(1)
+#define BIT_HCI_TXDMA_EN BIT(0)
-/* 2 REG_PKT_BUFF_ACCESS_CTRL (Offset 0x0106) */
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_PKT_BUFF_ACCESS_CTRL 0
-#define BIT_MASK_PKT_BUFF_ACCESS_CTRL 0xff
-#define BIT_PKT_BUFF_ACCESS_CTRL(x) (((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL) << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL)
-#define BIT_GET_PKT_BUFF_ACCESS_CTRL(x) (((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL) & BIT_MASK_PKT_BUFF_ACCESS_CTRL)
+/* 2 REG_PG_SIZE (Offset 0x0104) */
+#define BIT_SHIFT_DBG_FIFO_SEL 16
+#define BIT_MASK_DBG_FIFO_SEL 0xff
+#define BIT_DBG_FIFO_SEL(x) \
+ (((x) & BIT_MASK_DBG_FIFO_SEL) << BIT_SHIFT_DBG_FIFO_SEL)
+#define BITS_DBG_FIFO_SEL (BIT_MASK_DBG_FIFO_SEL << BIT_SHIFT_DBG_FIFO_SEL)
+#define BIT_CLEAR_DBG_FIFO_SEL(x) ((x) & (~BITS_DBG_FIFO_SEL))
+#define BIT_GET_DBG_FIFO_SEL(x) \
+ (((x) >> BIT_SHIFT_DBG_FIFO_SEL) & BIT_MASK_DBG_FIFO_SEL)
+#define BIT_SET_DBG_FIFO_SEL(x, v) \
+ (BIT_CLEAR_DBG_FIFO_SEL(x) | BIT_DBG_FIFO_SEL(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_PKT_BUFF_ACCESS_CTRL (Offset 0x0106) */
+#define BIT_SHIFT_PKT_BUFF_ACCESS_CTRL 0
+#define BIT_MASK_PKT_BUFF_ACCESS_CTRL 0xff
+#define BIT_PKT_BUFF_ACCESS_CTRL(x) \
+ (((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL) \
+ << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL)
+#define BITS_PKT_BUFF_ACCESS_CTRL \
+ (BIT_MASK_PKT_BUFF_ACCESS_CTRL << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL)
+#define BIT_CLEAR_PKT_BUFF_ACCESS_CTRL(x) ((x) & (~BITS_PKT_BUFF_ACCESS_CTRL))
+#define BIT_GET_PKT_BUFF_ACCESS_CTRL(x) \
+ (((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL) & \
+ BIT_MASK_PKT_BUFF_ACCESS_CTRL)
+#define BIT_SET_PKT_BUFF_ACCESS_CTRL(x, v) \
+ (BIT_CLEAR_PKT_BUFF_ACCESS_CTRL(x) | BIT_PKT_BUFF_ACCESS_CTRL(v))
-/* 2 REG_TSF_CLK_STATE (Offset 0x0108) */
+#endif
-#define BIT_TSF_CLK_IDX BIT(15)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_TSF_CLK_STATE (Offset 0x0108) */
+#define BIT_TSF_CLK_IDX BIT(15)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_TSF_CLK_STATE (Offset 0x0108) */
-#define BIT_TSF_CLK_STABLE BIT(15)
+#define BIT_TSF_CLK_STABLE BIT(15)
-#define BIT_SHIFT_I2C_M_BUS_GNT_FW 4
-#define BIT_MASK_I2C_M_BUS_GNT_FW 0x7
-#define BIT_I2C_M_BUS_GNT_FW(x) (((x) & BIT_MASK_I2C_M_BUS_GNT_FW) << BIT_SHIFT_I2C_M_BUS_GNT_FW)
-#define BIT_GET_I2C_M_BUS_GNT_FW(x) (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW) & BIT_MASK_I2C_M_BUS_GNT_FW)
+#define BIT_SHIFT_I2C_M_BUS_GNT_FW 4
+#define BIT_MASK_I2C_M_BUS_GNT_FW 0x7
+#define BIT_I2C_M_BUS_GNT_FW(x) \
+ (((x) & BIT_MASK_I2C_M_BUS_GNT_FW) << BIT_SHIFT_I2C_M_BUS_GNT_FW)
+#define BITS_I2C_M_BUS_GNT_FW \
+ (BIT_MASK_I2C_M_BUS_GNT_FW << BIT_SHIFT_I2C_M_BUS_GNT_FW)
+#define BIT_CLEAR_I2C_M_BUS_GNT_FW(x) ((x) & (~BITS_I2C_M_BUS_GNT_FW))
+#define BIT_GET_I2C_M_BUS_GNT_FW(x) \
+ (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW) & BIT_MASK_I2C_M_BUS_GNT_FW)
+#define BIT_SET_I2C_M_BUS_GNT_FW(x, v) \
+ (BIT_CLEAR_I2C_M_BUS_GNT_FW(x) | BIT_I2C_M_BUS_GNT_FW(v))
-#define BIT_I2C_M_GNT_FW BIT(3)
+#define BIT_I2C_M_GNT_FW BIT(3)
-#define BIT_SHIFT_I2C_M_SPEED 1
-#define BIT_MASK_I2C_M_SPEED 0x3
-#define BIT_I2C_M_SPEED(x) (((x) & BIT_MASK_I2C_M_SPEED) << BIT_SHIFT_I2C_M_SPEED)
-#define BIT_GET_I2C_M_SPEED(x) (((x) >> BIT_SHIFT_I2C_M_SPEED) & BIT_MASK_I2C_M_SPEED)
+#define BIT_SHIFT_I2C_M_SPEED 1
+#define BIT_MASK_I2C_M_SPEED 0x3
+#define BIT_I2C_M_SPEED(x) \
+ (((x) & BIT_MASK_I2C_M_SPEED) << BIT_SHIFT_I2C_M_SPEED)
+#define BITS_I2C_M_SPEED (BIT_MASK_I2C_M_SPEED << BIT_SHIFT_I2C_M_SPEED)
+#define BIT_CLEAR_I2C_M_SPEED(x) ((x) & (~BITS_I2C_M_SPEED))
+#define BIT_GET_I2C_M_SPEED(x) \
+ (((x) >> BIT_SHIFT_I2C_M_SPEED) & BIT_MASK_I2C_M_SPEED)
+#define BIT_SET_I2C_M_SPEED(x, v) \
+ (BIT_CLEAR_I2C_M_SPEED(x) | BIT_I2C_M_SPEED(v))
-#define BIT_I2C_M_UNLOCK BIT(0)
+#define BIT_I2C_M_UNLOCK BIT(0)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */
+#define BIT_CSI_BW_EN BIT(31)
-/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */
+#endif
+#if (HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_TXDMA_CMQ_MAP 16
-#define BIT_MASK_TXDMA_CMQ_MAP 0x3
-#define BIT_TXDMA_CMQ_MAP(x) (((x) & BIT_MASK_TXDMA_CMQ_MAP) << BIT_SHIFT_TXDMA_CMQ_MAP)
-#define BIT_GET_TXDMA_CMQ_MAP(x) (((x) >> BIT_SHIFT_TXDMA_CMQ_MAP) & BIT_MASK_TXDMA_CMQ_MAP)
+/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */
+#define BIT_SHIFT_TXDMA_HIQ_MAP_V1 19
+#define BIT_MASK_TXDMA_HIQ_MAP_V1 0x7
+#define BIT_TXDMA_HIQ_MAP_V1(x) \
+ (((x) & BIT_MASK_TXDMA_HIQ_MAP_V1) << BIT_SHIFT_TXDMA_HIQ_MAP_V1)
+#define BITS_TXDMA_HIQ_MAP_V1 \
+ (BIT_MASK_TXDMA_HIQ_MAP_V1 << BIT_SHIFT_TXDMA_HIQ_MAP_V1)
+#define BIT_CLEAR_TXDMA_HIQ_MAP_V1(x) ((x) & (~BITS_TXDMA_HIQ_MAP_V1))
+#define BIT_GET_TXDMA_HIQ_MAP_V1(x) \
+ (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_V1) & BIT_MASK_TXDMA_HIQ_MAP_V1)
+#define BIT_SET_TXDMA_HIQ_MAP_V1(x, v) \
+ (BIT_CLEAR_TXDMA_HIQ_MAP_V1(x) | BIT_TXDMA_HIQ_MAP_V1(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */
+
+#define BIT_SHIFT_TXDMA_CMQ_MAP 16
+#define BIT_MASK_TXDMA_CMQ_MAP 0x3
+#define BIT_TXDMA_CMQ_MAP(x) \
+ (((x) & BIT_MASK_TXDMA_CMQ_MAP) << BIT_SHIFT_TXDMA_CMQ_MAP)
+#define BITS_TXDMA_CMQ_MAP (BIT_MASK_TXDMA_CMQ_MAP << BIT_SHIFT_TXDMA_CMQ_MAP)
+#define BIT_CLEAR_TXDMA_CMQ_MAP(x) ((x) & (~BITS_TXDMA_CMQ_MAP))
+#define BIT_GET_TXDMA_CMQ_MAP(x) \
+ (((x) >> BIT_SHIFT_TXDMA_CMQ_MAP) & BIT_MASK_TXDMA_CMQ_MAP)
+#define BIT_SET_TXDMA_CMQ_MAP(x, v) \
+ (BIT_CLEAR_TXDMA_CMQ_MAP(x) | BIT_TXDMA_CMQ_MAP(v))
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8198F_SUPPORT)
/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */
+#define BIT_SHIFT_TXDMA_MGQ_MAP_V1 16
+#define BIT_MASK_TXDMA_MGQ_MAP_V1 0x7
+#define BIT_TXDMA_MGQ_MAP_V1(x) \
+ (((x) & BIT_MASK_TXDMA_MGQ_MAP_V1) << BIT_SHIFT_TXDMA_MGQ_MAP_V1)
+#define BITS_TXDMA_MGQ_MAP_V1 \
+ (BIT_MASK_TXDMA_MGQ_MAP_V1 << BIT_SHIFT_TXDMA_MGQ_MAP_V1)
+#define BIT_CLEAR_TXDMA_MGQ_MAP_V1(x) ((x) & (~BITS_TXDMA_MGQ_MAP_V1))
+#define BIT_GET_TXDMA_MGQ_MAP_V1(x) \
+ (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_V1) & BIT_MASK_TXDMA_MGQ_MAP_V1)
+#define BIT_SET_TXDMA_MGQ_MAP_V1(x, v) \
+ (BIT_CLEAR_TXDMA_MGQ_MAP_V1(x) | BIT_TXDMA_MGQ_MAP_V1(v))
-#define BIT_SHIFT_TXDMA_HIQ_MAP 14
-#define BIT_MASK_TXDMA_HIQ_MAP 0x3
-#define BIT_TXDMA_HIQ_MAP(x) (((x) & BIT_MASK_TXDMA_HIQ_MAP) << BIT_SHIFT_TXDMA_HIQ_MAP)
-#define BIT_GET_TXDMA_HIQ_MAP(x) (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP) & BIT_MASK_TXDMA_HIQ_MAP)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_TXDMA_MGQ_MAP 12
-#define BIT_MASK_TXDMA_MGQ_MAP 0x3
-#define BIT_TXDMA_MGQ_MAP(x) (((x) & BIT_MASK_TXDMA_MGQ_MAP) << BIT_SHIFT_TXDMA_MGQ_MAP)
-#define BIT_GET_TXDMA_MGQ_MAP(x) (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP) & BIT_MASK_TXDMA_MGQ_MAP)
+/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */
+#define BIT_SHIFT_TXDMA_H2C_MAP 16
+#define BIT_MASK_TXDMA_H2C_MAP 0x3
+#define BIT_TXDMA_H2C_MAP(x) \
+ (((x) & BIT_MASK_TXDMA_H2C_MAP) << BIT_SHIFT_TXDMA_H2C_MAP)
+#define BITS_TXDMA_H2C_MAP (BIT_MASK_TXDMA_H2C_MAP << BIT_SHIFT_TXDMA_H2C_MAP)
+#define BIT_CLEAR_TXDMA_H2C_MAP(x) ((x) & (~BITS_TXDMA_H2C_MAP))
+#define BIT_GET_TXDMA_H2C_MAP(x) \
+ (((x) >> BIT_SHIFT_TXDMA_H2C_MAP) & BIT_MASK_TXDMA_H2C_MAP)
+#define BIT_SET_TXDMA_H2C_MAP(x, v) \
+ (BIT_CLEAR_TXDMA_H2C_MAP(x) | BIT_TXDMA_H2C_MAP(v))
-#define BIT_SHIFT_TXDMA_BKQ_MAP 10
-#define BIT_MASK_TXDMA_BKQ_MAP 0x3
-#define BIT_TXDMA_BKQ_MAP(x) (((x) & BIT_MASK_TXDMA_BKQ_MAP) << BIT_SHIFT_TXDMA_BKQ_MAP)
-#define BIT_GET_TXDMA_BKQ_MAP(x) (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP) & BIT_MASK_TXDMA_BKQ_MAP)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_TXDMA_BEQ_MAP 8
-#define BIT_MASK_TXDMA_BEQ_MAP 0x3
-#define BIT_TXDMA_BEQ_MAP(x) (((x) & BIT_MASK_TXDMA_BEQ_MAP) << BIT_SHIFT_TXDMA_BEQ_MAP)
-#define BIT_GET_TXDMA_BEQ_MAP(x) (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP) & BIT_MASK_TXDMA_BEQ_MAP)
+/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */
+#define BIT_SHIFT_TXDMA_HIQ_MAP 14
+#define BIT_MASK_TXDMA_HIQ_MAP 0x3
+#define BIT_TXDMA_HIQ_MAP(x) \
+ (((x) & BIT_MASK_TXDMA_HIQ_MAP) << BIT_SHIFT_TXDMA_HIQ_MAP)
+#define BITS_TXDMA_HIQ_MAP (BIT_MASK_TXDMA_HIQ_MAP << BIT_SHIFT_TXDMA_HIQ_MAP)
+#define BIT_CLEAR_TXDMA_HIQ_MAP(x) ((x) & (~BITS_TXDMA_HIQ_MAP))
+#define BIT_GET_TXDMA_HIQ_MAP(x) \
+ (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP) & BIT_MASK_TXDMA_HIQ_MAP)
+#define BIT_SET_TXDMA_HIQ_MAP(x, v) \
+ (BIT_CLEAR_TXDMA_HIQ_MAP(x) | BIT_TXDMA_HIQ_MAP(v))
-#define BIT_SHIFT_TXDMA_VIQ_MAP 6
-#define BIT_MASK_TXDMA_VIQ_MAP 0x3
-#define BIT_TXDMA_VIQ_MAP(x) (((x) & BIT_MASK_TXDMA_VIQ_MAP) << BIT_SHIFT_TXDMA_VIQ_MAP)
-#define BIT_GET_TXDMA_VIQ_MAP(x) (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP) & BIT_MASK_TXDMA_VIQ_MAP)
+#endif
+#if (HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_TXDMA_VOQ_MAP 4
-#define BIT_MASK_TXDMA_VOQ_MAP 0x3
-#define BIT_TXDMA_VOQ_MAP(x) (((x) & BIT_MASK_TXDMA_VOQ_MAP) << BIT_SHIFT_TXDMA_VOQ_MAP)
-#define BIT_GET_TXDMA_VOQ_MAP(x) (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP) & BIT_MASK_TXDMA_VOQ_MAP)
+/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */
-#define BIT_RXDMA_AGG_EN BIT(2)
-#define BIT_RXSHFT_EN BIT(1)
-#define BIT_RXDMA_ARBBW_EN BIT(0)
+#define BIT_SHIFT_TXDMA_BKQ_MAP_V1 13
+#define BIT_MASK_TXDMA_BKQ_MAP_V1 0x7
+#define BIT_TXDMA_BKQ_MAP_V1(x) \
+ (((x) & BIT_MASK_TXDMA_BKQ_MAP_V1) << BIT_SHIFT_TXDMA_BKQ_MAP_V1)
+#define BITS_TXDMA_BKQ_MAP_V1 \
+ (BIT_MASK_TXDMA_BKQ_MAP_V1 << BIT_SHIFT_TXDMA_BKQ_MAP_V1)
+#define BIT_CLEAR_TXDMA_BKQ_MAP_V1(x) ((x) & (~BITS_TXDMA_BKQ_MAP_V1))
+#define BIT_GET_TXDMA_BKQ_MAP_V1(x) \
+ (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_V1) & BIT_MASK_TXDMA_BKQ_MAP_V1)
+#define BIT_SET_TXDMA_BKQ_MAP_V1(x, v) \
+ (BIT_CLEAR_TXDMA_BKQ_MAP_V1(x) | BIT_TXDMA_BKQ_MAP_V1(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8814A_SUPPORT)
+/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */
+#define BIT_SHIFT_TXDMA_MGQ_MAP 12
+#define BIT_MASK_TXDMA_MGQ_MAP 0x3
+#define BIT_TXDMA_MGQ_MAP(x) \
+ (((x) & BIT_MASK_TXDMA_MGQ_MAP) << BIT_SHIFT_TXDMA_MGQ_MAP)
+#define BITS_TXDMA_MGQ_MAP (BIT_MASK_TXDMA_MGQ_MAP << BIT_SHIFT_TXDMA_MGQ_MAP)
+#define BIT_CLEAR_TXDMA_MGQ_MAP(x) ((x) & (~BITS_TXDMA_MGQ_MAP))
+#define BIT_GET_TXDMA_MGQ_MAP(x) \
+ (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP) & BIT_MASK_TXDMA_MGQ_MAP)
+#define BIT_SET_TXDMA_MGQ_MAP(x, v) \
+ (BIT_CLEAR_TXDMA_MGQ_MAP(x) | BIT_TXDMA_MGQ_MAP(v))
-/* 2 REG_TRXFF_BNDY (Offset 0x0114) */
+#define BIT_SHIFT_TXDMA_BKQ_MAP 10
+#define BIT_MASK_TXDMA_BKQ_MAP 0x3
+#define BIT_TXDMA_BKQ_MAP(x) \
+ (((x) & BIT_MASK_TXDMA_BKQ_MAP) << BIT_SHIFT_TXDMA_BKQ_MAP)
+#define BITS_TXDMA_BKQ_MAP (BIT_MASK_TXDMA_BKQ_MAP << BIT_SHIFT_TXDMA_BKQ_MAP)
+#define BIT_CLEAR_TXDMA_BKQ_MAP(x) ((x) & (~BITS_TXDMA_BKQ_MAP))
+#define BIT_GET_TXDMA_BKQ_MAP(x) \
+ (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP) & BIT_MASK_TXDMA_BKQ_MAP)
+#define BIT_SET_TXDMA_BKQ_MAP(x, v) \
+ (BIT_CLEAR_TXDMA_BKQ_MAP(x) | BIT_TXDMA_BKQ_MAP(v))
+
+#endif
+#if (HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_RXFFOVFL_RSV_V1 28
-#define BIT_MASK_RXFFOVFL_RSV_V1 0xf
-#define BIT_RXFFOVFL_RSV_V1(x) (((x) & BIT_MASK_RXFFOVFL_RSV_V1) << BIT_SHIFT_RXFFOVFL_RSV_V1)
-#define BIT_GET_RXFFOVFL_RSV_V1(x) (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V1) & BIT_MASK_RXFFOVFL_RSV_V1)
+/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */
+#define BIT_SHIFT_TXDMA_BEQ_MAP_V1 10
+#define BIT_MASK_TXDMA_BEQ_MAP_V1 0x7
+#define BIT_TXDMA_BEQ_MAP_V1(x) \
+ (((x) & BIT_MASK_TXDMA_BEQ_MAP_V1) << BIT_SHIFT_TXDMA_BEQ_MAP_V1)
+#define BITS_TXDMA_BEQ_MAP_V1 \
+ (BIT_MASK_TXDMA_BEQ_MAP_V1 << BIT_SHIFT_TXDMA_BEQ_MAP_V1)
+#define BIT_CLEAR_TXDMA_BEQ_MAP_V1(x) ((x) & (~BITS_TXDMA_BEQ_MAP_V1))
+#define BIT_GET_TXDMA_BEQ_MAP_V1(x) \
+ (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_V1) & BIT_MASK_TXDMA_BEQ_MAP_V1)
+#define BIT_SET_TXDMA_BEQ_MAP_V1(x, v) \
+ (BIT_CLEAR_TXDMA_BEQ_MAP_V1(x) | BIT_TXDMA_BEQ_MAP_V1(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */
+#define BIT_SHIFT_TXDMA_BEQ_MAP 8
+#define BIT_MASK_TXDMA_BEQ_MAP 0x3
+#define BIT_TXDMA_BEQ_MAP(x) \
+ (((x) & BIT_MASK_TXDMA_BEQ_MAP) << BIT_SHIFT_TXDMA_BEQ_MAP)
+#define BITS_TXDMA_BEQ_MAP (BIT_MASK_TXDMA_BEQ_MAP << BIT_SHIFT_TXDMA_BEQ_MAP)
+#define BIT_CLEAR_TXDMA_BEQ_MAP(x) ((x) & (~BITS_TXDMA_BEQ_MAP))
+#define BIT_GET_TXDMA_BEQ_MAP(x) \
+ (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP) & BIT_MASK_TXDMA_BEQ_MAP)
+#define BIT_SET_TXDMA_BEQ_MAP(x, v) \
+ (BIT_CLEAR_TXDMA_BEQ_MAP(x) | BIT_TXDMA_BEQ_MAP(v))
-/* 2 REG_TRXFF_BNDY (Offset 0x0114) */
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */
+#define BIT_SHIFT_TXDMA_VIQ_MAP_V1 7
+#define BIT_MASK_TXDMA_VIQ_MAP_V1 0x7
+#define BIT_TXDMA_VIQ_MAP_V1(x) \
+ (((x) & BIT_MASK_TXDMA_VIQ_MAP_V1) << BIT_SHIFT_TXDMA_VIQ_MAP_V1)
+#define BITS_TXDMA_VIQ_MAP_V1 \
+ (BIT_MASK_TXDMA_VIQ_MAP_V1 << BIT_SHIFT_TXDMA_VIQ_MAP_V1)
+#define BIT_CLEAR_TXDMA_VIQ_MAP_V1(x) ((x) & (~BITS_TXDMA_VIQ_MAP_V1))
+#define BIT_GET_TXDMA_VIQ_MAP_V1(x) \
+ (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_V1) & BIT_MASK_TXDMA_VIQ_MAP_V1)
+#define BIT_SET_TXDMA_VIQ_MAP_V1(x, v) \
+ (BIT_CLEAR_TXDMA_VIQ_MAP_V1(x) | BIT_TXDMA_VIQ_MAP_V1(v))
-#define BIT_SHIFT_RXFF0_BNDY 16
-#define BIT_MASK_RXFF0_BNDY 0xffff
-#define BIT_RXFF0_BNDY(x) (((x) & BIT_MASK_RXFF0_BNDY) << BIT_SHIFT_RXFF0_BNDY)
-#define BIT_GET_RXFF0_BNDY(x) (((x) >> BIT_SHIFT_RXFF0_BNDY) & BIT_MASK_RXFF0_BNDY)
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */
-#define BIT_SHIFT_RXFFOVFL_RSV 8
-#define BIT_MASK_RXFFOVFL_RSV 0xf
-#define BIT_RXFFOVFL_RSV(x) (((x) & BIT_MASK_RXFFOVFL_RSV) << BIT_SHIFT_RXFFOVFL_RSV)
-#define BIT_GET_RXFFOVFL_RSV(x) (((x) >> BIT_SHIFT_RXFFOVFL_RSV) & BIT_MASK_RXFFOVFL_RSV)
+#define BIT_SHIFT_TXDMA_VIQ_MAP 6
+#define BIT_MASK_TXDMA_VIQ_MAP 0x3
+#define BIT_TXDMA_VIQ_MAP(x) \
+ (((x) & BIT_MASK_TXDMA_VIQ_MAP) << BIT_SHIFT_TXDMA_VIQ_MAP)
+#define BITS_TXDMA_VIQ_MAP (BIT_MASK_TXDMA_VIQ_MAP << BIT_SHIFT_TXDMA_VIQ_MAP)
+#define BIT_CLEAR_TXDMA_VIQ_MAP(x) ((x) & (~BITS_TXDMA_VIQ_MAP))
+#define BIT_GET_TXDMA_VIQ_MAP(x) \
+ (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP) & BIT_MASK_TXDMA_VIQ_MAP)
+#define BIT_SET_TXDMA_VIQ_MAP(x, v) \
+ (BIT_CLEAR_TXDMA_VIQ_MAP(x) | BIT_TXDMA_VIQ_MAP(v))
+#define BIT_SHIFT_TXDMA_VOQ_MAP 4
+#define BIT_MASK_TXDMA_VOQ_MAP 0x3
+#define BIT_TXDMA_VOQ_MAP(x) \
+ (((x) & BIT_MASK_TXDMA_VOQ_MAP) << BIT_SHIFT_TXDMA_VOQ_MAP)
+#define BITS_TXDMA_VOQ_MAP (BIT_MASK_TXDMA_VOQ_MAP << BIT_SHIFT_TXDMA_VOQ_MAP)
+#define BIT_CLEAR_TXDMA_VOQ_MAP(x) ((x) & (~BITS_TXDMA_VOQ_MAP))
+#define BIT_GET_TXDMA_VOQ_MAP(x) \
+ (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP) & BIT_MASK_TXDMA_VOQ_MAP)
+#define BIT_SET_TXDMA_VOQ_MAP(x, v) \
+ (BIT_CLEAR_TXDMA_VOQ_MAP(x) | BIT_TXDMA_VOQ_MAP(v))
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */
+#define BIT_SHIFT_TXDMA_VOQ_MAP_V1 4
+#define BIT_MASK_TXDMA_VOQ_MAP_V1 0x7
+#define BIT_TXDMA_VOQ_MAP_V1(x) \
+ (((x) & BIT_MASK_TXDMA_VOQ_MAP_V1) << BIT_SHIFT_TXDMA_VOQ_MAP_V1)
+#define BITS_TXDMA_VOQ_MAP_V1 \
+ (BIT_MASK_TXDMA_VOQ_MAP_V1 << BIT_SHIFT_TXDMA_VOQ_MAP_V1)
+#define BIT_CLEAR_TXDMA_VOQ_MAP_V1(x) ((x) & (~BITS_TXDMA_VOQ_MAP_V1))
+#define BIT_GET_TXDMA_VOQ_MAP_V1(x) \
+ (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_V1) & BIT_MASK_TXDMA_VOQ_MAP_V1)
+#define BIT_SET_TXDMA_VOQ_MAP_V1(x, v) \
+ (BIT_CLEAR_TXDMA_VOQ_MAP_V1(x) | BIT_TXDMA_VOQ_MAP_V1(v))
-/* 2 REG_TRXFF_BNDY (Offset 0x0114) */
+#endif
+#if (HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_RXFFOVFL_RSV_V2 8
-#define BIT_MASK_RXFFOVFL_RSV_V2 0xf
-#define BIT_RXFFOVFL_RSV_V2(x) (((x) & BIT_MASK_RXFFOVFL_RSV_V2) << BIT_SHIFT_RXFFOVFL_RSV_V2)
-#define BIT_GET_RXFFOVFL_RSV_V2(x) (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2) & BIT_MASK_RXFFOVFL_RSV_V2)
+/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */
+#define BIT_TXDMA_BW_EN BIT(3)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8814A_SUPPORT)
+/* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */
+#define BIT_RXDMA_AGG_EN BIT(2)
+#define BIT_RXSHFT_EN BIT(1)
+#define BIT_RXDMA_ARBBW_EN BIT(0)
-/* 2 REG_TRXFF_BNDY (Offset 0x0114) */
+#endif
+#if (HALMAC_8814A_SUPPORT)
-#define BIT_SHIFT_RXFF0_BNDY_V1 8
-#define BIT_MASK_RXFF0_BNDY_V1 0x3ffff
-#define BIT_RXFF0_BNDY_V1(x) (((x) & BIT_MASK_RXFF0_BNDY_V1) << BIT_SHIFT_RXFF0_BNDY_V1)
-#define BIT_GET_RXFF0_BNDY_V1(x) (((x) >> BIT_SHIFT_RXFF0_BNDY_V1) & BIT_MASK_RXFF0_BNDY_V1)
+/* 2 REG_TRXFF_BNDY (Offset 0x0114) */
+#define BIT_SHIFT_RXFFOVFL_RSV_V1 28
+#define BIT_MASK_RXFFOVFL_RSV_V1 0xf
+#define BIT_RXFFOVFL_RSV_V1(x) \
+ (((x) & BIT_MASK_RXFFOVFL_RSV_V1) << BIT_SHIFT_RXFFOVFL_RSV_V1)
+#define BITS_RXFFOVFL_RSV_V1 \
+ (BIT_MASK_RXFFOVFL_RSV_V1 << BIT_SHIFT_RXFFOVFL_RSV_V1)
+#define BIT_CLEAR_RXFFOVFL_RSV_V1(x) ((x) & (~BITS_RXFFOVFL_RSV_V1))
+#define BIT_GET_RXFFOVFL_RSV_V1(x) \
+ (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V1) & BIT_MASK_RXFFOVFL_RSV_V1)
+#define BIT_SET_RXFFOVFL_RSV_V1(x, v) \
+ (BIT_CLEAR_RXFFOVFL_RSV_V1(x) | BIT_RXFFOVFL_RSV_V1(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_TRXFF_BNDY (Offset 0x0114) */
+#define BIT_SHIFT_RXFF0_BNDY 16
+#define BIT_MASK_RXFF0_BNDY 0xffff
+#define BIT_RXFF0_BNDY(x) (((x) & BIT_MASK_RXFF0_BNDY) << BIT_SHIFT_RXFF0_BNDY)
+#define BITS_RXFF0_BNDY (BIT_MASK_RXFF0_BNDY << BIT_SHIFT_RXFF0_BNDY)
+#define BIT_CLEAR_RXFF0_BNDY(x) ((x) & (~BITS_RXFF0_BNDY))
+#define BIT_GET_RXFF0_BNDY(x) \
+ (((x) >> BIT_SHIFT_RXFF0_BNDY) & BIT_MASK_RXFF0_BNDY)
+#define BIT_SET_RXFF0_BNDY(x, v) (BIT_CLEAR_RXFF0_BNDY(x) | BIT_RXFF0_BNDY(v))
-/* 2 REG_TRXFF_BNDY (Offset 0x0114) */
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_TXPKTBUF_PGBNDY 0
-#define BIT_MASK_TXPKTBUF_PGBNDY 0xff
-#define BIT_TXPKTBUF_PGBNDY(x) (((x) & BIT_MASK_TXPKTBUF_PGBNDY) << BIT_SHIFT_TXPKTBUF_PGBNDY)
-#define BIT_GET_TXPKTBUF_PGBNDY(x) (((x) >> BIT_SHIFT_TXPKTBUF_PGBNDY) & BIT_MASK_TXPKTBUF_PGBNDY)
+/* 2 REG_TRXFF_BNDY (Offset 0x0114) */
+#define BIT_SHIFT_FWFFOVFL_RSV 16
+#define BIT_MASK_FWFFOVFL_RSV 0xf
+#define BIT_FWFFOVFL_RSV(x) \
+ (((x) & BIT_MASK_FWFFOVFL_RSV) << BIT_SHIFT_FWFFOVFL_RSV)
+#define BITS_FWFFOVFL_RSV (BIT_MASK_FWFFOVFL_RSV << BIT_SHIFT_FWFFOVFL_RSV)
+#define BIT_CLEAR_FWFFOVFL_RSV(x) ((x) & (~BITS_FWFFOVFL_RSV))
+#define BIT_GET_FWFFOVFL_RSV(x) \
+ (((x) >> BIT_SHIFT_FWFFOVFL_RSV) & BIT_MASK_FWFFOVFL_RSV)
+#define BIT_SET_FWFFOVFL_RSV(x, v) \
+ (BIT_CLEAR_FWFFOVFL_RSV(x) | BIT_FWFFOVFL_RSV(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_TRXFF_BNDY (Offset 0x0114) */
+#define BIT_SHIFT_RXFFOVFL_RSV 8
+#define BIT_MASK_RXFFOVFL_RSV 0xf
+#define BIT_RXFFOVFL_RSV(x) \
+ (((x) & BIT_MASK_RXFFOVFL_RSV) << BIT_SHIFT_RXFFOVFL_RSV)
+#define BITS_RXFFOVFL_RSV (BIT_MASK_RXFFOVFL_RSV << BIT_SHIFT_RXFFOVFL_RSV)
+#define BIT_CLEAR_RXFFOVFL_RSV(x) ((x) & (~BITS_RXFFOVFL_RSV))
+#define BIT_GET_RXFFOVFL_RSV(x) \
+ (((x) >> BIT_SHIFT_RXFFOVFL_RSV) & BIT_MASK_RXFFOVFL_RSV)
+#define BIT_SET_RXFFOVFL_RSV(x, v) \
+ (BIT_CLEAR_RXFFOVFL_RSV(x) | BIT_RXFFOVFL_RSV(v))
-/* 2 REG_TRXFF_BNDY (Offset 0x0114) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_RXFF0_BNDY_V2 0
-#define BIT_MASK_RXFF0_BNDY_V2 0x3ffff
-#define BIT_RXFF0_BNDY_V2(x) (((x) & BIT_MASK_RXFF0_BNDY_V2) << BIT_SHIFT_RXFF0_BNDY_V2)
-#define BIT_GET_RXFF0_BNDY_V2(x) (((x) >> BIT_SHIFT_RXFF0_BNDY_V2) & BIT_MASK_RXFF0_BNDY_V2)
+/* 2 REG_TRXFF_BNDY (Offset 0x0114) */
+#define BIT_SHIFT_RXFFOVFL_RSV_V2 8
+#define BIT_MASK_RXFFOVFL_RSV_V2 0xf
+#define BIT_RXFFOVFL_RSV_V2(x) \
+ (((x) & BIT_MASK_RXFFOVFL_RSV_V2) << BIT_SHIFT_RXFFOVFL_RSV_V2)
+#define BITS_RXFFOVFL_RSV_V2 \
+ (BIT_MASK_RXFFOVFL_RSV_V2 << BIT_SHIFT_RXFFOVFL_RSV_V2)
+#define BIT_CLEAR_RXFFOVFL_RSV_V2(x) ((x) & (~BITS_RXFFOVFL_RSV_V2))
+#define BIT_GET_RXFFOVFL_RSV_V2(x) \
+ (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2) & BIT_MASK_RXFFOVFL_RSV_V2)
+#define BIT_SET_RXFFOVFL_RSV_V2(x, v) \
+ (BIT_CLEAR_RXFFOVFL_RSV_V2(x) | BIT_RXFFOVFL_RSV_V2(v))
-#define BIT_SHIFT_RXFF0_RDPTR_V2 0
-#define BIT_MASK_RXFF0_RDPTR_V2 0x3ffff
-#define BIT_RXFF0_RDPTR_V2(x) (((x) & BIT_MASK_RXFF0_RDPTR_V2) << BIT_SHIFT_RXFF0_RDPTR_V2)
-#define BIT_GET_RXFF0_RDPTR_V2(x) (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2) & BIT_MASK_RXFF0_RDPTR_V2)
+#endif
+#if (HALMAC_8814A_SUPPORT)
-#define BIT_SHIFT_RXFF0_WTPTR_V2 0
-#define BIT_MASK_RXFF0_WTPTR_V2 0x3ffff
-#define BIT_RXFF0_WTPTR_V2(x) (((x) & BIT_MASK_RXFF0_WTPTR_V2) << BIT_SHIFT_RXFF0_WTPTR_V2)
-#define BIT_GET_RXFF0_WTPTR_V2(x) (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2) & BIT_MASK_RXFF0_WTPTR_V2)
+/* 2 REG_TRXFF_BNDY (Offset 0x0114) */
+#define BIT_SHIFT_RXFF0_BNDY_V1 8
+#define BIT_MASK_RXFF0_BNDY_V1 0x3ffff
+#define BIT_RXFF0_BNDY_V1(x) \
+ (((x) & BIT_MASK_RXFF0_BNDY_V1) << BIT_SHIFT_RXFF0_BNDY_V1)
+#define BITS_RXFF0_BNDY_V1 (BIT_MASK_RXFF0_BNDY_V1 << BIT_SHIFT_RXFF0_BNDY_V1)
+#define BIT_CLEAR_RXFF0_BNDY_V1(x) ((x) & (~BITS_RXFF0_BNDY_V1))
+#define BIT_GET_RXFF0_BNDY_V1(x) \
+ (((x) >> BIT_SHIFT_RXFF0_BNDY_V1) & BIT_MASK_RXFF0_BNDY_V1)
+#define BIT_SET_RXFF0_BNDY_V1(x, v) \
+ (BIT_CLEAR_RXFF0_BNDY_V1(x) | BIT_RXFF0_BNDY_V1(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8814A_SUPPORT)
+/* 2 REG_TRXFF_BNDY (Offset 0x0114) */
+#define BIT_SHIFT_TXPKTBUF_PGBNDY 0
+#define BIT_MASK_TXPKTBUF_PGBNDY 0xff
+#define BIT_TXPKTBUF_PGBNDY(x) \
+ (((x) & BIT_MASK_TXPKTBUF_PGBNDY) << BIT_SHIFT_TXPKTBUF_PGBNDY)
+#define BITS_TXPKTBUF_PGBNDY \
+ (BIT_MASK_TXPKTBUF_PGBNDY << BIT_SHIFT_TXPKTBUF_PGBNDY)
+#define BIT_CLEAR_TXPKTBUF_PGBNDY(x) ((x) & (~BITS_TXPKTBUF_PGBNDY))
+#define BIT_GET_TXPKTBUF_PGBNDY(x) \
+ (((x) >> BIT_SHIFT_TXPKTBUF_PGBNDY) & BIT_MASK_TXPKTBUF_PGBNDY)
+#define BIT_SET_TXPKTBUF_PGBNDY(x, v) \
+ (BIT_CLEAR_TXPKTBUF_PGBNDY(x) | BIT_TXPKTBUF_PGBNDY(v))
-/* 2 REG_FF_STATUS (Offset 0x0118) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_RXFF0_RDPTR_V1 13
-#define BIT_MASK_RXFF0_RDPTR_V1 0x3ffff
-#define BIT_RXFF0_RDPTR_V1(x) (((x) & BIT_MASK_RXFF0_RDPTR_V1) << BIT_SHIFT_RXFF0_RDPTR_V1)
-#define BIT_GET_RXFF0_RDPTR_V1(x) (((x) >> BIT_SHIFT_RXFF0_RDPTR_V1) & BIT_MASK_RXFF0_RDPTR_V1)
+/* 2 REG_TRXFF_BNDY (Offset 0x0114) */
+#define BIT_SHIFT_RXFF0_BNDY_V2 0
+#define BIT_MASK_RXFF0_BNDY_V2 0x3ffff
+#define BIT_RXFF0_BNDY_V2(x) \
+ (((x) & BIT_MASK_RXFF0_BNDY_V2) << BIT_SHIFT_RXFF0_BNDY_V2)
+#define BITS_RXFF0_BNDY_V2 (BIT_MASK_RXFF0_BNDY_V2 << BIT_SHIFT_RXFF0_BNDY_V2)
+#define BIT_CLEAR_RXFF0_BNDY_V2(x) ((x) & (~BITS_RXFF0_BNDY_V2))
+#define BIT_GET_RXFF0_BNDY_V2(x) \
+ (((x) >> BIT_SHIFT_RXFF0_BNDY_V2) & BIT_MASK_RXFF0_BNDY_V2)
+#define BIT_SET_RXFF0_BNDY_V2(x, v) \
+ (BIT_CLEAR_RXFF0_BNDY_V2(x) | BIT_RXFF0_BNDY_V2(v))
+
+#define BIT_SHIFT_RXFF0_RDPTR_V2 0
+#define BIT_MASK_RXFF0_RDPTR_V2 0x3ffff
+#define BIT_RXFF0_RDPTR_V2(x) \
+ (((x) & BIT_MASK_RXFF0_RDPTR_V2) << BIT_SHIFT_RXFF0_RDPTR_V2)
+#define BITS_RXFF0_RDPTR_V2 \
+ (BIT_MASK_RXFF0_RDPTR_V2 << BIT_SHIFT_RXFF0_RDPTR_V2)
+#define BIT_CLEAR_RXFF0_RDPTR_V2(x) ((x) & (~BITS_RXFF0_RDPTR_V2))
+#define BIT_GET_RXFF0_RDPTR_V2(x) \
+ (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2) & BIT_MASK_RXFF0_RDPTR_V2)
+#define BIT_SET_RXFF0_RDPTR_V2(x, v) \
+ (BIT_CLEAR_RXFF0_RDPTR_V2(x) | BIT_RXFF0_RDPTR_V2(v))
+
+#define BIT_SHIFT_RXFF0_WTPTR_V2 0
+#define BIT_MASK_RXFF0_WTPTR_V2 0x3ffff
+#define BIT_RXFF0_WTPTR_V2(x) \
+ (((x) & BIT_MASK_RXFF0_WTPTR_V2) << BIT_SHIFT_RXFF0_WTPTR_V2)
+#define BITS_RXFF0_WTPTR_V2 \
+ (BIT_MASK_RXFF0_WTPTR_V2 << BIT_SHIFT_RXFF0_WTPTR_V2)
+#define BIT_CLEAR_RXFF0_WTPTR_V2(x) ((x) & (~BITS_RXFF0_WTPTR_V2))
+#define BIT_GET_RXFF0_WTPTR_V2(x) \
+ (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2) & BIT_MASK_RXFF0_WTPTR_V2)
+#define BIT_SET_RXFF0_WTPTR_V2(x, v) \
+ (BIT_CLEAR_RXFF0_WTPTR_V2(x) | BIT_RXFF0_WTPTR_V2(v))
#endif
+#if (HALMAC_8814A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_FF_STATUS (Offset 0x0118) */
+#define BIT_SHIFT_RXFF0_RDPTR_V1 13
+#define BIT_MASK_RXFF0_RDPTR_V1 0x3ffff
+#define BIT_RXFF0_RDPTR_V1(x) \
+ (((x) & BIT_MASK_RXFF0_RDPTR_V1) << BIT_SHIFT_RXFF0_RDPTR_V1)
+#define BITS_RXFF0_RDPTR_V1 \
+ (BIT_MASK_RXFF0_RDPTR_V1 << BIT_SHIFT_RXFF0_RDPTR_V1)
+#define BIT_CLEAR_RXFF0_RDPTR_V1(x) ((x) & (~BITS_RXFF0_RDPTR_V1))
+#define BIT_GET_RXFF0_RDPTR_V1(x) \
+ (((x) >> BIT_SHIFT_RXFF0_RDPTR_V1) & BIT_MASK_RXFF0_RDPTR_V1)
+#define BIT_SET_RXFF0_RDPTR_V1(x, v) \
+ (BIT_CLEAR_RXFF0_RDPTR_V1(x) | BIT_RXFF0_RDPTR_V1(v))
-/* 2 REG_PTA_I2C_MBOX (Offset 0x0118) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_I2C_M_STATUS 8
-#define BIT_MASK_I2C_M_STATUS 0xf
-#define BIT_I2C_M_STATUS(x) (((x) & BIT_MASK_I2C_M_STATUS) << BIT_SHIFT_I2C_M_STATUS)
-#define BIT_GET_I2C_M_STATUS(x) (((x) >> BIT_SHIFT_I2C_M_STATUS) & BIT_MASK_I2C_M_STATUS)
+/* 2 REG_PTA_I2C_MBOX (Offset 0x0118) */
+#define BIT_SHIFT_I2C_M_STATUS 8
+#define BIT_MASK_I2C_M_STATUS 0xf
+#define BIT_I2C_M_STATUS(x) \
+ (((x) & BIT_MASK_I2C_M_STATUS) << BIT_SHIFT_I2C_M_STATUS)
+#define BITS_I2C_M_STATUS (BIT_MASK_I2C_M_STATUS << BIT_SHIFT_I2C_M_STATUS)
+#define BIT_CLEAR_I2C_M_STATUS(x) ((x) & (~BITS_I2C_M_STATUS))
+#define BIT_GET_I2C_M_STATUS(x) \
+ (((x) >> BIT_SHIFT_I2C_M_STATUS) & BIT_MASK_I2C_M_STATUS)
+#define BIT_SET_I2C_M_STATUS(x, v) \
+ (BIT_CLEAR_I2C_M_STATUS(x) | BIT_I2C_M_STATUS(v))
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_PTA_I2C_MBOX (Offset 0x0118) */
+#define BIT_SHIFT_I2C_M_BUS_GNT 4
+#define BIT_MASK_I2C_M_BUS_GNT 0x7
+#define BIT_I2C_M_BUS_GNT(x) \
+ (((x) & BIT_MASK_I2C_M_BUS_GNT) << BIT_SHIFT_I2C_M_BUS_GNT)
+#define BITS_I2C_M_BUS_GNT (BIT_MASK_I2C_M_BUS_GNT << BIT_SHIFT_I2C_M_BUS_GNT)
+#define BIT_CLEAR_I2C_M_BUS_GNT(x) ((x) & (~BITS_I2C_M_BUS_GNT))
+#define BIT_GET_I2C_M_BUS_GNT(x) \
+ (((x) >> BIT_SHIFT_I2C_M_BUS_GNT) & BIT_MASK_I2C_M_BUS_GNT)
+#define BIT_SET_I2C_M_BUS_GNT(x, v) \
+ (BIT_CLEAR_I2C_M_BUS_GNT(x) | BIT_I2C_M_BUS_GNT(v))
-#define BIT_SHIFT_I2C_M_BUS_GNT 4
-#define BIT_MASK_I2C_M_BUS_GNT 0x7
-#define BIT_I2C_M_BUS_GNT(x) (((x) & BIT_MASK_I2C_M_BUS_GNT) << BIT_SHIFT_I2C_M_BUS_GNT)
-#define BIT_GET_I2C_M_BUS_GNT(x) (((x) >> BIT_SHIFT_I2C_M_BUS_GNT) & BIT_MASK_I2C_M_BUS_GNT)
+#define BIT_I2C_GNT_FW BIT(3)
-#define BIT_I2C_GNT_FW BIT(3)
+#define BIT_SHIFT_I2C_DATA_RATE 1
+#define BIT_MASK_I2C_DATA_RATE 0x3
+#define BIT_I2C_DATA_RATE(x) \
+ (((x) & BIT_MASK_I2C_DATA_RATE) << BIT_SHIFT_I2C_DATA_RATE)
+#define BITS_I2C_DATA_RATE (BIT_MASK_I2C_DATA_RATE << BIT_SHIFT_I2C_DATA_RATE)
+#define BIT_CLEAR_I2C_DATA_RATE(x) ((x) & (~BITS_I2C_DATA_RATE))
+#define BIT_GET_I2C_DATA_RATE(x) \
+ (((x) >> BIT_SHIFT_I2C_DATA_RATE) & BIT_MASK_I2C_DATA_RATE)
+#define BIT_SET_I2C_DATA_RATE(x, v) \
+ (BIT_CLEAR_I2C_DATA_RATE(x) | BIT_I2C_DATA_RATE(v))
-#define BIT_SHIFT_I2C_DATA_RATE 1
-#define BIT_MASK_I2C_DATA_RATE 0x3
-#define BIT_I2C_DATA_RATE(x) (((x) & BIT_MASK_I2C_DATA_RATE) << BIT_SHIFT_I2C_DATA_RATE)
-#define BIT_GET_I2C_DATA_RATE(x) (((x) >> BIT_SHIFT_I2C_DATA_RATE) & BIT_MASK_I2C_DATA_RATE)
-
-#define BIT_I2C_SW_CONTROL_UNLOCK BIT(0)
+#define BIT_I2C_SW_CONTROL_UNLOCK BIT(0)
#endif
-
#if (HALMAC_8814A_SUPPORT)
-
/* 2 REG_FF_STATUS (Offset 0x0118) */
-
-#define BIT_SHIFT_RXFF0_WTPTR_V1 0
-#define BIT_MASK_RXFF0_WTPTR_V1 0x3ffff
-#define BIT_RXFF0_WTPTR_V1(x) (((x) & BIT_MASK_RXFF0_WTPTR_V1) << BIT_SHIFT_RXFF0_WTPTR_V1)
-#define BIT_GET_RXFF0_WTPTR_V1(x) (((x) >> BIT_SHIFT_RXFF0_WTPTR_V1) & BIT_MASK_RXFF0_WTPTR_V1)
-
+#define BIT_SHIFT_RXFF0_WTPTR_V1 0
+#define BIT_MASK_RXFF0_WTPTR_V1 0x3ffff
+#define BIT_RXFF0_WTPTR_V1(x) \
+ (((x) & BIT_MASK_RXFF0_WTPTR_V1) << BIT_SHIFT_RXFF0_WTPTR_V1)
+#define BITS_RXFF0_WTPTR_V1 \
+ (BIT_MASK_RXFF0_WTPTR_V1 << BIT_SHIFT_RXFF0_WTPTR_V1)
+#define BIT_CLEAR_RXFF0_WTPTR_V1(x) ((x) & (~BITS_RXFF0_WTPTR_V1))
+#define BIT_GET_RXFF0_WTPTR_V1(x) \
+ (((x) >> BIT_SHIFT_RXFF0_WTPTR_V1) & BIT_MASK_RXFF0_WTPTR_V1)
+#define BIT_SET_RXFF0_WTPTR_V1(x, v) \
+ (BIT_CLEAR_RXFF0_WTPTR_V1(x) | BIT_RXFF0_WTPTR_V1(v))
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_RXFF_PTR (Offset 0x011C) */
+#define BIT_SHIFT_RXFF0_RDPTR 16
+#define BIT_MASK_RXFF0_RDPTR 0xffff
+#define BIT_RXFF0_RDPTR(x) \
+ (((x) & BIT_MASK_RXFF0_RDPTR) << BIT_SHIFT_RXFF0_RDPTR)
+#define BITS_RXFF0_RDPTR (BIT_MASK_RXFF0_RDPTR << BIT_SHIFT_RXFF0_RDPTR)
+#define BIT_CLEAR_RXFF0_RDPTR(x) ((x) & (~BITS_RXFF0_RDPTR))
+#define BIT_GET_RXFF0_RDPTR(x) \
+ (((x) >> BIT_SHIFT_RXFF0_RDPTR) & BIT_MASK_RXFF0_RDPTR)
+#define BIT_SET_RXFF0_RDPTR(x, v) \
+ (BIT_CLEAR_RXFF0_RDPTR(x) | BIT_RXFF0_RDPTR(v))
+
+#define BIT_SHIFT_RXFF0_WTPTR 0
+#define BIT_MASK_RXFF0_WTPTR 0xffff
+#define BIT_RXFF0_WTPTR(x) \
+ (((x) & BIT_MASK_RXFF0_WTPTR) << BIT_SHIFT_RXFF0_WTPTR)
+#define BITS_RXFF0_WTPTR (BIT_MASK_RXFF0_WTPTR << BIT_SHIFT_RXFF0_WTPTR)
+#define BIT_CLEAR_RXFF0_WTPTR(x) ((x) & (~BITS_RXFF0_WTPTR))
+#define BIT_GET_RXFF0_WTPTR(x) \
+ (((x) >> BIT_SHIFT_RXFF0_WTPTR) & BIT_MASK_RXFF0_WTPTR)
+#define BIT_SET_RXFF0_WTPTR(x, v) \
+ (BIT_CLEAR_RXFF0_WTPTR(x) | BIT_RXFF0_WTPTR(v))
-#define BIT_SHIFT_RXFF0_RDPTR 16
-#define BIT_MASK_RXFF0_RDPTR 0xffff
-#define BIT_RXFF0_RDPTR(x) (((x) & BIT_MASK_RXFF0_RDPTR) << BIT_SHIFT_RXFF0_RDPTR)
-#define BIT_GET_RXFF0_RDPTR(x) (((x) >> BIT_SHIFT_RXFF0_RDPTR) & BIT_MASK_RXFF0_RDPTR)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_RXFF0_WTPTR 0
-#define BIT_MASK_RXFF0_WTPTR 0xffff
-#define BIT_RXFF0_WTPTR(x) (((x) & BIT_MASK_RXFF0_WTPTR) << BIT_SHIFT_RXFF0_WTPTR)
-#define BIT_GET_RXFF0_WTPTR(x) (((x) >> BIT_SHIFT_RXFF0_WTPTR) & BIT_MASK_RXFF0_WTPTR)
+/* 2 REG_FE1IMR (Offset 0x0120) */
+#define BIT_CPUMGQ_DROP_BY_HOLD_TIME_INT_EN BIT(31)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_FE1IMR (Offset 0x0120) */
+
+#define BIT_FS_SW_PLL_LEAVE_32K_INT_EN BIT(31)
+
+#endif
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_FE1IMR (Offset 0x0120) */
-#define BIT_BB_STOP_RX_INT_EN BIT(29)
+#define BIT_FWFF_FULL_INT_EN BIT(30)
#endif
+#if (HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1IMR (Offset 0x0120) */
+
+#define BIT_FS_FWFF_FULL_INT_EN BIT(30)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
/* 2 REG_FE1IMR (Offset 0x0120) */
-#define BIT_FS_RXDMA2_DONE_INT_EN BIT(28)
-#define BIT_FS_RXDONE3_INT_EN BIT(27)
-#define BIT_FS_RXDONE2_INT_EN BIT(26)
-#define BIT_FS_RX_BCN_P4_INT_EN BIT(25)
-#define BIT_FS_RX_BCN_P3_INT_EN BIT(24)
-#define BIT_FS_RX_BCN_P2_INT_EN BIT(23)
-#define BIT_FS_RX_BCN_P1_INT_EN BIT(22)
-#define BIT_FS_RX_BCN_P0_INT_EN BIT(21)
-#define BIT_FS_RX_UMD0_INT_EN BIT(20)
-#define BIT_FS_RX_UMD1_INT_EN BIT(19)
-#define BIT_FS_RX_BMD0_INT_EN BIT(18)
-#define BIT_FS_RX_BMD1_INT_EN BIT(17)
-#define BIT_FS_RXDONE_INT_EN BIT(16)
-#define BIT_FS_WWLAN_INT_EN BIT(15)
-#define BIT_FS_SOUND_DONE_INT_EN BIT(14)
-#define BIT_FS_LP_STBY_INT_EN BIT(13)
-#define BIT_FS_TRL_MTR_INT_EN BIT(12)
-#define BIT_FS_BF1_PRETO_INT_EN BIT(11)
-#define BIT_FS_BF0_PRETO_INT_EN BIT(10)
-#define BIT_FS_PTCL_RELEASE_MACID_INT_EN BIT(9)
+#define BIT_BB_STOP_RX_INT_EN BIT(29)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FE1IMR (Offset 0x0120) */
+
+#define BIT_FS_BB_STOP_RX_INT_EN BIT(29)
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FE1IMR (Offset 0x0120) */
-#define BIT_FS_LTE_COEX_EN BIT(6)
+#define BIT_FS_RXDMA2_DONE_INT_EN BIT(28)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
+
+/* 2 REG_FE1IMR (Offset 0x0120) */
+
+#define BIT_FS_RXDONE3_INT_EN BIT(27)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FE1IMR (Offset 0x0120) */
-#define BIT_FS_WLACTOFF_INT_EN BIT(5)
-#define BIT_FS_WLACTON_INT_EN BIT(4)
-#define BIT_FS_BTCMD_INT_EN BIT(3)
+#define BIT_FS_RXDONE2_INT_EN BIT(26)
+#define BIT_FS_RX_BCN_P4_INT_EN BIT(25)
+#define BIT_FS_RX_BCN_P3_INT_EN BIT(24)
+#define BIT_FS_RX_BCN_P2_INT_EN BIT(23)
+#define BIT_FS_RX_BCN_P1_INT_EN BIT(22)
+#define BIT_FS_RX_BCN_P0_INT_EN BIT(21)
+#define BIT_FS_RX_UMD0_INT_EN BIT(20)
+#define BIT_FS_RX_UMD1_INT_EN BIT(19)
+#define BIT_FS_RX_BMD0_INT_EN BIT(18)
+#define BIT_FS_RX_BMD1_INT_EN BIT(17)
+#define BIT_FS_RXDONE_INT_EN BIT(16)
+#define BIT_FS_WWLAN_INT_EN BIT(15)
+#define BIT_FS_SOUND_DONE_INT_EN BIT(14)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT)
+/* 2 REG_FE1IMR (Offset 0x0120) */
+#define BIT_FS_LP_STBY_INT_EN BIT(13)
-/* 2 REG_FEIMR (Offset 0x0120) */
+#endif
-#define BIT_REG_MAILBOX_TO_I2C_INT BIT(2)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
-#endif
+/* 2 REG_FE1IMR (Offset 0x0120) */
+#define BIT_FS_TRL_MTR_INT_EN BIT(12)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FE1IMR (Offset 0x0120) */
-#define BIT_FS_REG_MAILBOX_TO_I2C_INT_EN BIT(2)
+#define BIT_FS_BF1_PRETO_INT_EN BIT(11)
+#define BIT_FS_BF0_PRETO_INT_EN BIT(10)
+#define BIT_FS_PTCL_RELEASE_MACID_INT_EN BIT(9)
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_FE1IMR (Offset 0x0120) */
+#define BIT_PRETXERR_HANDLE_FSIMR BIT(8)
-/* 2 REG_FEIMR (Offset 0x0120) */
+#endif
-#define BIT_TRPC_TO_INT_EN BIT(1)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_FE1IMR (Offset 0x0120) */
+#define BIT_PRETX_ERRHLD_INT_EN BIT(8)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8822C_SUPPORT)
/* 2 REG_FE1IMR (Offset 0x0120) */
-#define BIT_FS_TRPC_TO_INT_EN_V1 BIT(1)
+#define BIT_FS_PRETX_ERRHLD_INT_EN BIT(8)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_FE1IMR (Offset 0x0120) */
+#define BIT_FS_GTRD_INT_EN BIT(7)
-/* 2 REG_FEIMR (Offset 0x0120) */
+#endif
-#define BIT_BIT_RPC_O_T_INT_EN BIT(0)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_FE1IMR (Offset 0x0120) */
+#define BIT_FS_LTE_COEX_EN BIT(6)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FE1IMR (Offset 0x0120) */
-#define BIT_FS_RPC_O_T_INT_EN_V1 BIT(0)
+#define BIT_FS_WLACTOFF_INT_EN BIT(5)
+#define BIT_FS_WLACTON_INT_EN BIT(4)
+#define BIT_FS_BTCMD_INT_EN BIT(3)
#endif
+#if (HALMAC_8192E_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_FEIMR (Offset 0x0120) */
+#define BIT_REG_MAILBOX_TO_I2C_INT BIT(2)
-/* 2 REG_FE1ISR (Offset 0x0124) */
+#endif
-#define BIT_BB_STOP_RX_INT BIT(29)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_FE1IMR (Offset 0x0120) */
+#define BIT_FS_REG_MAILBOX_TO_I2C_INT_EN BIT(2)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_FE1ISR (Offset 0x0124) */
+/* 2 REG_FEIMR (Offset 0x0120) */
-#define BIT_FS_RXDMA2_DONE_INT BIT(28)
-#define BIT_FS_RXDONE3_INT BIT(27)
-#define BIT_FS_RXDONE2_INT BIT(26)
-#define BIT_FS_RX_BCN_P4_INT BIT(25)
-#define BIT_FS_RX_BCN_P3_INT BIT(24)
-#define BIT_FS_RX_BCN_P2_INT BIT(23)
-#define BIT_FS_RX_BCN_P1_INT BIT(22)
-#define BIT_FS_RX_BCN_P0_INT BIT(21)
-#define BIT_FS_RX_UMD0_INT BIT(20)
-#define BIT_FS_RX_UMD1_INT BIT(19)
-#define BIT_FS_RX_BMD0_INT BIT(18)
-#define BIT_FS_RX_BMD1_INT BIT(17)
-#define BIT_FS_RXDONE_INT BIT(16)
-#define BIT_FS_WWLAN_INT BIT(15)
-#define BIT_FS_SOUND_DONE_INT BIT(14)
-#define BIT_FS_LP_STBY_INT BIT(13)
-#define BIT_FS_TRL_MTR_INT BIT(12)
-#define BIT_FS_BF1_PRETO_INT BIT(11)
-#define BIT_FS_BF0_PRETO_INT BIT(10)
-#define BIT_FS_PTCL_RELEASE_MACID_INT BIT(9)
+#define BIT_TRPC_TO_INT_EN BIT(1)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FE1IMR (Offset 0x0120) */
+#define BIT_FS_TRPC_TO_INT_EN_V1 BIT(1)
-/* 2 REG_FE1ISR (Offset 0x0124) */
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_FS_LTE_COEX_INT BIT(6)
+/* 2 REG_FEIMR (Offset 0x0120) */
+
+#define BIT_BIT_RPC_O_T_INT_EN BIT(0)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE1IMR (Offset 0x0120) */
+
+#define BIT_FS_RPC_O_T_INT_EN_V1 BIT(0)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_FE1ISR (Offset 0x0124) */
-#define BIT_FS_WLACTOFF_INT BIT(5)
-#define BIT_FS_WLACTON_INT BIT(4)
-#define BIT_FS_BCN_RX_INT_INT BIT(3)
+#define BIT_CPUMGQ_DROP_BY_HOLD_TIME_INT BIT(31)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT)
+/* 2 REG_FE1ISR (Offset 0x0124) */
+#define BIT_FS_SW_PLL_LEAVE_32K_INT BIT(31)
-/* 2 REG_FEISR (Offset 0x0124) */
+#endif
-#define BIT_MAILBOX_TO_I2C BIT(2)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_FE1ISR (Offset 0x0124) */
+#define BIT_FWFF_FULL_INT BIT(30)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8822C_SUPPORT)
/* 2 REG_FE1ISR (Offset 0x0124) */
-#define BIT_FS_MAILBOX_TO_I2C_INT BIT(2)
+#define BIT_FS_FS_FWFF_FULL_INT BIT(30)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_FE1ISR (Offset 0x0124) */
+#define BIT_BB_STOP_RX_INT BIT(29)
-/* 2 REG_FEISR (Offset 0x0124) */
+#endif
-#define BIT_TRPC_TO_INT BIT(1)
+#if (HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_FE1ISR (Offset 0x0124) */
+#define BIT_FS_BB_STOP_RX_INT BIT(29)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FE1ISR (Offset 0x0124) */
-#define BIT_FS_TRPC_TO_INT BIT(1)
+#define BIT_FS_RXDMA2_DONE_INT BIT(28)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_FE1ISR (Offset 0x0124) */
+#define BIT_FS_RXDONE3_INT BIT(27)
-/* 2 REG_FEISR (Offset 0x0124) */
+#endif
-#define BIT_RPC_O_T_INT BIT(0)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_FE1ISR (Offset 0x0124) */
+#define BIT_FS_RXDONE3_INT_INT BIT(27)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FE1ISR (Offset 0x0124) */
-#define BIT_FS_RPC_O_T_INT BIT(0)
+#define BIT_FS_RXDONE2_INT BIT(26)
+#define BIT_FS_RX_BCN_P4_INT BIT(25)
+#define BIT_FS_RX_BCN_P3_INT BIT(24)
+#define BIT_FS_RX_BCN_P2_INT BIT(23)
+#define BIT_FS_RX_BCN_P1_INT BIT(22)
+#define BIT_FS_RX_BCN_P0_INT BIT(21)
+#define BIT_FS_RX_UMD0_INT BIT(20)
+#define BIT_FS_RX_UMD1_INT BIT(19)
+#define BIT_FS_RX_BMD0_INT BIT(18)
+#define BIT_FS_RX_BMD1_INT BIT(17)
+#define BIT_FS_RXDONE_INT BIT(16)
+#define BIT_FS_WWLAN_INT BIT(15)
+#define BIT_FS_SOUND_DONE_INT BIT(14)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_FE1ISR (Offset 0x0124) */
+#define BIT_FS_LP_STBY_INT BIT(13)
-/* 2 REG_CPWM (Offset 0x012C) */
+#endif
-#define BIT_CPWM_TOGGLING BIT(31)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_CPWM_MOD 24
-#define BIT_MASK_CPWM_MOD 0x7f
-#define BIT_CPWM_MOD(x) (((x) & BIT_MASK_CPWM_MOD) << BIT_SHIFT_CPWM_MOD)
-#define BIT_GET_CPWM_MOD(x) (((x) >> BIT_SHIFT_CPWM_MOD) & BIT_MASK_CPWM_MOD)
+/* 2 REG_FE1ISR (Offset 0x0124) */
+#define BIT_FS_TRL_MTR_INT BIT(12)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FE1ISR (Offset 0x0124) */
+#define BIT_FS_BF1_PRETO_INT BIT(11)
+#define BIT_FS_BF0_PRETO_INT BIT(10)
+#define BIT_FS_PTCL_RELEASE_MACID_INT BIT(9)
-/* 2 REG_FWIMR (Offset 0x0130) */
+#endif
-#define BIT_FS_TXBCNOK_MB7_INT_EN BIT(31)
+#if (HALMAC_8198F_SUPPORT)
-#endif
+/* 2 REG_FE1ISR (Offset 0x0124) */
+#define BIT_PRETXERR_HANDLE_FSISR BIT(8)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_FWIMR (Offset 0x0130) */
+/* 2 REG_FE1ISR (Offset 0x0124) */
-#define BIT_SOUND_DONE_MSK BIT(30)
+#define BIT_PRETX_ERRHLD_INT BIT(8)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FE1ISR (Offset 0x0124) */
+#define BIT_FS_PRETX_ERRHLD_INT BIT(8)
-/* 2 REG_FWIMR (Offset 0x0130) */
+#endif
-#define BIT_FS_TXBCNOK_MB6_INT_EN BIT(30)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_FE1ISR (Offset 0x0124) */
+#define BIT_SND_RDY_INT BIT(7)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_FWIMR (Offset 0x0130) */
+/* 2 REG_FE1ISR (Offset 0x0124) */
-#define BIT_TRY_DONE_MSK BIT(29)
+#define BIT_FS_LTE_COEX_INT BIT(6)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FE1ISR (Offset 0x0124) */
+#define BIT_FS_WLACTOFF_INT BIT(5)
+#define BIT_FS_WLACTON_INT BIT(4)
-/* 2 REG_FWIMR (Offset 0x0130) */
+#endif
-#define BIT_FS_TXBCNOK_MB5_INT_EN BIT(29)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_FE1ISR (Offset 0x0124) */
+#define BIT_FS_BCN_RX_INT_INT BIT(3)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_FWIMR (Offset 0x0130) */
+/* 2 REG_FE1ISR (Offset 0x0124) */
-#define BIT_TXRPT_CNT_FULL_MSK BIT(28)
+#define BIT_BT_CMD_INT BIT(3)
#endif
+#if (HALMAC_8192E_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FEISR (Offset 0x0124) */
+#define BIT_MAILBOX_TO_I2C BIT(2)
-/* 2 REG_FWIMR (Offset 0x0130) */
+#endif
-#define BIT_FS_TXBCNOK_MB4_INT_EN BIT(28)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_FE1ISR (Offset 0x0124) */
+#define BIT_FS_MAILBOX_TO_I2C_INT BIT(2)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_FWIMR (Offset 0x0130) */
+/* 2 REG_FEISR (Offset 0x0124) */
-#define BIT_WLACTOFF_INT_EN BIT(27)
+#define BIT_TRPC_TO_INT BIT(1)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FE1ISR (Offset 0x0124) */
+#define BIT_FS_TRPC_TO_INT BIT(1)
-/* 2 REG_FWIMR (Offset 0x0130) */
+#endif
-#define BIT_FS_TXBCNOK_MB3_INT_EN BIT(27)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_FEISR (Offset 0x0124) */
+#define BIT_RPC_O_T_INT BIT(0)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_FWIMR (Offset 0x0130) */
+/* 2 REG_FE1ISR (Offset 0x0124) */
-#define BIT_WLACTON_INT_EN BIT(26)
+#define BIT_FS_RPC_O_T_INT BIT(0)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+/* 2 REG_CPWM (Offset 0x012C) */
+
+#define BIT_CPWM_TOGGLING BIT(31)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#define BIT_SHIFT_CPWM_MOD 24
+#define BIT_MASK_CPWM_MOD 0x7f
+#define BIT_CPWM_MOD(x) (((x) & BIT_MASK_CPWM_MOD) << BIT_SHIFT_CPWM_MOD)
+#define BITS_CPWM_MOD (BIT_MASK_CPWM_MOD << BIT_SHIFT_CPWM_MOD)
+#define BIT_CLEAR_CPWM_MOD(x) ((x) & (~BITS_CPWM_MOD))
+#define BIT_GET_CPWM_MOD(x) (((x) >> BIT_SHIFT_CPWM_MOD) & BIT_MASK_CPWM_MOD)
+#define BIT_SET_CPWM_MOD(x, v) (BIT_CLEAR_CPWM_MOD(x) | BIT_CPWM_MOD(v))
+
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_FS_TXBCNOK_MB2_INT_EN BIT(26)
+#define BIT_FS_TXBCNOK_MB7_INT_EN BIT(31)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_TXPKTIN_INT_EN BIT(25)
+#define BIT_SOUND_DONE_MSK BIT(30)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_FS_TXBCNOK_MB1_INT_EN BIT(25)
+#define BIT_FS_TXBCNOK_MB6_INT_EN BIT(30)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_TXBCNOK_MSK BIT(24)
+#define BIT_TRY_DONE_MSK BIT(29)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_FS_TXBCNOK_MB0_INT_EN BIT(24)
+#define BIT_FS_TXBCNOK_MB5_INT_EN BIT(29)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_TXBCNERR_MSK BIT(23)
+#define BIT_TXRPT_CNT_FULL_MSK BIT(28)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_FS_TXBCNERR_MB7_INT_EN BIT(23)
+#define BIT_FS_TXBCNOK_MB4_INT_EN BIT(28)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_RX_UMD0_EN BIT(22)
+#define BIT_WLACTOFF_INT_EN BIT(27)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_FS_TXBCNERR_MB6_INT_EN BIT(22)
+#define BIT_FS_TXBCNOK_MB3_INT_EN BIT(27)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_RX_UMD1_EN BIT(21)
+#define BIT_WLACTON_INT_EN BIT(26)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_FS_TXBCNERR_MB5_INT_EN BIT(21)
+#define BIT_FS_TXBCNOK_MB2_INT_EN BIT(26)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_RX_BMD0_EN BIT(20)
+#define BIT_TXPKTIN_INT_EN BIT(25)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_FS_TXBCNERR_MB4_INT_EN BIT(20)
+#define BIT_FS_TXBCNOK_MB1_INT_EN BIT(25)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_RX_BMD1_EN BIT(19)
+#define BIT_TXBCNOK_MSK BIT(24)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_FS_TXBCNERR_MB3_INT_EN BIT(19)
+#define BIT_FS_TXBCNOK_MB0_INT_EN BIT(24)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_BCN_RX_INT_EN BIT(18)
+#define BIT_TXBCNERR_MSK BIT(23)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_FS_TXBCNERR_MB2_INT_EN BIT(18)
+#define BIT_FS_TXBCNERR_MB7_INT_EN BIT(23)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_TBTTINT_MSK BIT(17)
+#define BIT_RX_UMD0_EN BIT(22)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_FS_TXBCNERR_MB1_INT_EN BIT(17)
+#define BIT_FS_TXBCNERR_MB6_INT_EN BIT(22)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_BCNERLY_MSK BIT(16)
+#define BIT_RX_UMD1_EN BIT(21)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWIMR (Offset 0x0130) */
+
+#define BIT_FS_TXBCNERR_MB5_INT_EN BIT(21)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_FS_TXBCNERR_MB0_INT_EN BIT(16)
+#define BIT_RX_BMD0_EN BIT(20)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_FWIMR (Offset 0x0130) */
+
+#define BIT_FS_TXBCNERR_MB4_INT_EN BIT(20)
+
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_BCNDMA7_MSK BIT(15)
+#define BIT_RX_BMD1_EN BIT(19)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_FWIMR (Offset 0x0130) */
+
+#define BIT_FS_TXBCNERR_MB3_INT_EN BIT(19)
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_CPUMGN_POLLED_PKT_DONE_INT_EN BIT(15)
+#define BIT_BCN_RX_INT_EN BIT(18)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FWIMR (Offset 0x0130) */
+
+#define BIT_FS_TXBCNERR_MB2_INT_EN BIT(18)
+
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_CPU_MGQ_TXDONE_INT_EN BIT(15)
+#define BIT_TBTTINT_MSK BIT(17)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_FWIMR (Offset 0x0130) */
+
+#define BIT_FS_TXBCNERR_MB1_INT_EN BIT(17)
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_BCNDMA6_MSK BIT(14)
+#define BIT_BCNERLY_MSK BIT(16)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FWIMR (Offset 0x0130) */
+
+#define BIT_FS_TXBCNERR_MB0_INT_EN BIT(16)
+
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_SIFS_OVERSPEC_INT_EN BIT(14)
+#define BIT_BCNDMA7_MSK BIT(15)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_FWIMR (Offset 0x0130) */
+
+#define BIT_CPUMGN_POLLED_PKT_DONE_INT_EN BIT(15)
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_BCNDMA5_MSK BIT(13)
+#define BIT_CPU_MGQ_TXDONE_INT_EN BIT(15)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_FWIMR (Offset 0x0130) */
+
+#define BIT_BCNDMA6_MSK BIT(14)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_EN BIT(13)
+#define BIT_SIFS_OVERSPEC_INT_EN BIT(14)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_BCNDMA4_MSK BIT(12)
+#define BIT_BCNDMA5_MSK BIT(13)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWIMR (Offset 0x0130) */
+
+#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_EN BIT(13)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_FS_MGNTQFF_TO_INT_EN BIT(12)
+#define BIT_BCNDMA4_MSK BIT(12)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_FWIMR (Offset 0x0130) */
+#define BIT_FS_MGNTQFF_TO_INT_EN BIT(12)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_BCNDMA3_MSK BIT(11)
+#define BIT_BCNDMA3_MSK BIT(11)
#endif
-
#if (HALMAC_8197F_SUPPORT)
-
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_FS_DDMA1_LP_INT_ENBIT_CPUMGN_POLLED_PKT_BUSY_ERR_INT_EN BIT(11)
+#define BIT_FS_DDMA1_LP_INT_ENBIT_CPUMGN_POLLED_PKT_BUSY_ERR_INT_EN BIT(11)
#endif
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWIMR (Offset 0x0130) */
+
+#define BIT_FS_CPUMGQ_ERR_INT_EN BIT(11)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT)
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_FS_DDMA1_LP_INT_EN BIT(11)
+#define BIT_FS_DDMA1_LP_INT_EN BIT(11)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_BCNDMA2_MSK BIT(10)
+#define BIT_BCNDMA2_MSK BIT(10)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT)
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_FS_DDMA1_HP_INT_EN BIT(10)
+#define BIT_FS_DDMA1_HP_INT_EN BIT(10)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_BCNDMA1_MSK BIT(9)
+#define BIT_BCNDMA1_MSK BIT(9)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_FS_DDMA0_LP_INT_EN BIT(9)
+#define BIT_FS_DDMA0_LP_INT_EN BIT(9)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_BCNDMA0_MSK BIT(8)
+#define BIT_BCNDMA0_MSK BIT(8)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_FS_DDMA0_HP_INT_EN BIT(8)
+#define BIT_FS_DDMA0_HP_INT_EN BIT(8)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_LP_STBY_MSK BIT(7)
+#define BIT_LP_STBY_MSK BIT(7)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_FS_TRXRPT_INT_EN BIT(7)
+#define BIT_FS_TRXRPT_INT_EN BIT(7)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_CTWENDINT_MSK BIT(6)
+#define BIT_CTWENDINT_MSK BIT(6)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_FS_C2H_W_READY_INT_EN BIT(6)
+#define BIT_FS_C2H_W_READY_INT_EN BIT(6)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_HRCV_MSK BIT(5)
+#define BIT_HRCV_MSK BIT(5)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_FS_HRCV_INT_EN BIT(5)
+#define BIT_FS_HRCV_INT_EN BIT(5)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_H2CCMD_MSK BIT(4)
+#define BIT_H2CCMD_MSK BIT(4)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_FS_H2CCMD_INT_EN BIT(4)
+#define BIT_FS_H2CCMD_INT_EN BIT(4)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_RXDONE_MSK BIT(3)
+#define BIT_RXDONE_MSK BIT(3)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_FS_TXPKTIN_INT_EN BIT(3)
+#define BIT_FS_TXPKTIN_INT_EN BIT(3)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_ERRORHDL_MSK BIT(2)
+#define BIT_ERRORHDL_MSK BIT(2)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_FS_ERRORHDL_INT_EN BIT(2)
+#define BIT_FS_ERRORHDL_INT_EN BIT(2)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_TXCCX_MSK_FW BIT(1)
+#define BIT_TXCCX_MSK_FW BIT(1)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_FS_TXCCX_INT_EN BIT(1)
+#define BIT_FS_TXCCX_INT_EN BIT(1)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_TXCLOSE_MSK BIT(0)
+#define BIT_TXCLOSE_MSK BIT(0)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWIMR (Offset 0x0130) */
-#define BIT_FS_TXCLOSE_INT_EN BIT(0)
+#define BIT_FS_TXCLOSE_INT_EN BIT(0)
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_FS_TXBCNOK_MB7_INT BIT(31)
+#define BIT_FS_TXBCNOK_MB7_INT BIT(31)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_SOUND_DONE_INT BIT(30)
+#define BIT_SOUND_DONE_INT BIT(30)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_FS_TXBCNOK_MB6_INT BIT(30)
+#define BIT_FS_TXBCNOK_MB6_INT BIT(30)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_TRY_DONE_INT BIT(29)
+#define BIT_TRY_DONE_INT BIT(29)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_FS_TXBCNOK_MB5_INT BIT(29)
+#define BIT_FS_TXBCNOK_MB5_INT BIT(29)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_TXRPT_CNT_FULL_INT BIT(28)
+#define BIT_TXRPT_CNT_FULL_INT BIT(28)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_FS_TXBCNOK_MB4_INT BIT(28)
+#define BIT_FS_TXBCNOK_MB4_INT BIT(28)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_WLACTOFF_INT BIT(27)
+#define BIT_WLACTOFF_INT BIT(27)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_FS_TXBCNOK_MB3_INT BIT(27)
+#define BIT_FS_TXBCNOK_MB3_INT BIT(27)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_WLACTON_INT BIT(26)
+#define BIT_WLACTON_INT BIT(26)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_FS_TXBCNOK_MB2_INT BIT(26)
+#define BIT_FS_TXBCNOK_MB2_INT BIT(26)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_TXPKTIN_INT BIT(25)
+#define BIT_TXPKTIN_INT BIT(25)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_FS_TXBCNOK_MB1_INT BIT(25)
+#define BIT_FS_TXBCNOK_MB1_INT BIT(25)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_TXBCNOK_INT BIT(24)
+#define BIT_TXBCNOK_INT BIT(24)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_FS_TXBCNOK_MB0_INT BIT(24)
+#define BIT_FS_TXBCNOK_MB0_INT BIT(24)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_TXBCNERR_INT BIT(23)
+#define BIT_TXBCNERR_INT BIT(23)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_FS_TXBCNERR_MB7_INT BIT(23)
+#define BIT_FS_TXBCNERR_MB7_INT BIT(23)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_RX_UMD0_INT BIT(22)
+#define BIT_RX_UMD0_INT BIT(22)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_FS_TXBCNERR_MB6_INT BIT(22)
+#define BIT_FS_TXBCNERR_MB6_INT BIT(22)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_RX_UMD1_INT BIT(21)
+#define BIT_RX_UMD1_INT BIT(21)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_FS_TXBCNERR_MB5_INT BIT(21)
+#define BIT_FS_TXBCNERR_MB5_INT BIT(21)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_RX_BMD0_INT BIT(20)
+#define BIT_RX_BMD0_INT BIT(20)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_FS_TXBCNERR_MB4_INT BIT(20)
+#define BIT_FS_TXBCNERR_MB4_INT BIT(20)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_RX_BMD1_INT BIT(19)
+#define BIT_RX_BMD1_INT BIT(19)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_FS_TXBCNERR_MB3_INT BIT(19)
+#define BIT_FS_TXBCNERR_MB3_INT BIT(19)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_BCN_RX_INT_INT BIT(18)
+#define BIT_BCN_RX_INT_INT BIT(18)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_FS_TXBCNERR_MB2_INT BIT(18)
+#define BIT_FS_TXBCNERR_MB2_INT BIT(18)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_TBTTINT_INT BIT(17)
+#define BIT_TBTTINT_INT BIT(17)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_FS_TXBCNERR_MB1_INT BIT(17)
+#define BIT_FS_TXBCNERR_MB1_INT BIT(17)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_BCNERLY_INT BIT(16)
+#define BIT_BCNERLY_INT BIT(16)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_FS_TXBCNERR_MB0_INT BIT(16)
+#define BIT_FS_TXBCNERR_MB0_INT BIT(16)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_BCNDMA7_INT BIT(15)
+#define BIT_BCNDMA7_INT BIT(15)
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_CPUMGN_POLLED_PKT_DONE_INT BIT(15)
+#define BIT_CPUMGN_POLLED_PKT_DONE_INT BIT(15)
#endif
-
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_CPU_MGQ_TXDONE_INT BIT(15)
+#define BIT_CPU_MGQ_TXDONE_INT BIT(15)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_BCNDMA6_INT BIT(14)
+#define BIT_BCNDMA6_INT BIT(14)
#endif
-
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_SIFS_OVERSPEC_INT BIT(14)
+#define BIT_SIFS_OVERSPEC_INT BIT(14)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_BCNDMA5_INT BIT(13)
+#define BIT_BCNDMA5_INT BIT(13)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_FS_MGNTQ_RPTR_RELEASE_INT BIT(13)
+#define BIT_FS_MGNTQ_RPTR_RELEASE_INT BIT(13)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_BCNDMA4_INT BIT(12)
+#define BIT_BCNDMA4_INT BIT(12)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_FS_MGNTQFF_TO_INT BIT(12)
+#define BIT_FS_MGNTQFF_TO_INT BIT(12)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_BCNDMA3_INT BIT(11)
+#define BIT_BCNDMA3_INT BIT(11)
#endif
-
#if (HALMAC_8197F_SUPPORT)
-
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_FS_DDMA1_LP_INTBIT_CPUMGN_POLLED_PKT_BUSY_ERR_INT BIT(11)
+#define BIT_FS_DDMA1_LP_INTBIT_CPUMGN_POLLED_PKT_BUSY_ERR_INT BIT(11)
#endif
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FWISR (Offset 0x0134) */
+
+#define BIT_FS_CPUMGQ_ERR_INT BIT(11)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT)
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_FS_DDMA1_LP_INT BIT(11)
+#define BIT_FS_DDMA1_LP_INT BIT(11)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_BCNDMA2_INT BIT(10)
+#define BIT_BCNDMA2_INT BIT(10)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT)
+
+/* 2 REG_FWISR (Offset 0x0134) */
+
+#define BIT_FS_DDMA1_HP_INT BIT(10)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_FS_DDMA1_HP_INT BIT(10)
+#define BIT_FWCMD_PKTIN_INT BIT(10)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_BCNDMA1_INT BIT(9)
+#define BIT_BCNDMA1_INT BIT(9)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_FS_DDMA0_LP_INT BIT(9)
+#define BIT_FS_DDMA0_LP_INT BIT(9)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_BCNDMA0_INT BIT(8)
+#define BIT_BCNDMA0_INT BIT(8)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_FS_DDMA0_HP_INT BIT(8)
+#define BIT_FS_DDMA0_HP_INT BIT(8)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_LP_STBY_INT BIT(7)
+#define BIT_LP_STBY_INT BIT(7)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_FS_TRXRPT_INT BIT(7)
+#define BIT_FS_TRXRPT_INT BIT(7)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_CTWENDINT_INT BIT(6)
+#define BIT_CTWENDINT_INT BIT(6)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_FS_C2H_W_READY_INT BIT(6)
+#define BIT_FS_C2H_W_READY_INT BIT(6)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_HRCV_INT BIT(5)
+#define BIT_HRCV_INT BIT(5)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FWISR (Offset 0x0134) */
-
-/* 2 REG_FWISR (Offset 0x0134) */
-
-#define BIT_FS_HRCV_INT BIT(5)
+#define BIT_FS_HRCV_INT BIT(5)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_H2CCMD_INT BIT(4)
+#define BIT_H2CCMD_INT BIT(4)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_FS_H2CCMD_INT BIT(4)
+#define BIT_FS_H2CCMD_INT BIT(4)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_RXDONE_INT BIT(3)
+#define BIT_RXDONE_INT BIT(3)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_FS_TXPKTIN_INT BIT(3)
+#define BIT_FS_TXPKTIN_INT BIT(3)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_ERRORHDL_INT BIT(2)
+#define BIT_ERRORHDL_INT BIT(2)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_FS_ERRORHDL_INT BIT(2)
+#define BIT_FS_ERRORHDL_INT BIT(2)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_TXCCX_INT BIT(1)
+#define BIT_TXCCX_INT BIT(1)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_FS_TXCCX_INT BIT(1)
+#define BIT_FS_TXCCX_INT BIT(1)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_TXCLOSE_INT BIT(0)
+#define BIT_TXCLOSE_INT BIT(0)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FWISR (Offset 0x0134) */
-#define BIT_FS_TXCLOSE_INT BIT(0)
+#define BIT_FS_TXCLOSE_INT BIT(0)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_GTINT6_MSK BIT(31)
-#define BIT_TX_NULL1_INT_MSK BIT(30)
-#define BIT_TX_NULL0_INT_MSK BIT(29)
-#define BIT_MTI_BCNIVLEAR_INT_MSK BIT(28)
-#define BIT_ATIMINT_MSK BIT(27)
-#define BIT_WWLAN_INT_EN BIT(26)
-#define BIT_C2H_W_READY_EN BIT(25)
-#define BIT_TRL_MTR_EN BIT(24)
-#define BIT_CLR_PS_STATUS_MSK BIT(23)
+#define BIT_GTINT6_MSK BIT(31)
+#define BIT_TX_NULL1_INT_MSK BIT(30)
+#define BIT_TX_NULL0_INT_MSK BIT(29)
+#define BIT_MTI_BCNIVLEAR_INT_MSK BIT(28)
+#define BIT_ATIMINT_MSK BIT(27)
+#define BIT_WWLAN_INT_EN BIT(26)
+#define BIT_C2H_W_READY_EN BIT(25)
+#define BIT_TRL_MTR_EN BIT(24)
+#define BIT_CLR_PS_STATUS_MSK BIT(23)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_PS_TIMER_C_EARLY_INT_EN BIT(23)
+#define BIT_PS_TIMER_C_EARLY_INT_EN BIT(23)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_RETRIVE_BUFFERED_MSK BIT(22)
+#define BIT_RETRIEVE_BUFFERED_MSK BIT(22)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_PS_TIMER_B_EARLY_INT_EN BIT(22)
+#define BIT_PS_TIMER_B_EARLY_INT_EN BIT(22)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_RPWMINT2_MSK BIT(21)
+#define BIT_RPWMINT2_MSK BIT(21)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_PS_TIMER_A_EARLY_INT_EN BIT(21)
+#define BIT_PS_TIMER_A_EARLY_INT_EN BIT(21)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_TSF_BIT32_TOGGLE_MSK_V1 BIT(20)
+#define BIT_TSF_BIT32_TOGGLE_MSK_V1 BIT(20)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_EN BIT(20)
+#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_EN BIT(20)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_TRIGGER_PKT_MSK BIT(19)
+#define BIT_TRIGGER_PKT_MSK BIT(19)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_PS_TIMER_C_INT_EN BIT(19)
+#define BIT_PS_TIMER_C_INT_EN BIT(19)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_FW_BTCMD_INTMSK BIT(18)
+#define BIT_FW_BTCMD_INTMSK BIT(18)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_PS_TIMER_B_INT_EN BIT(18)
+#define BIT_PS_TIMER_B_INT_EN BIT(18)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_P2P_RFOFF_INTMSK BIT(17)
+#define BIT_P2P_RFOFF_INTMSK BIT(17)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_PS_TIMER_A_INT_EN BIT(17)
+#define BIT_PS_TIMER_A_INT_EN BIT(17)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_P2P_RFON_INTMSK BIT(16)
+#define BIT_P2P_RFON_INTMSK BIT(16)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_CPUMGQ_TX_TIMER_INT_EN BIT(16)
+#define BIT_CPUMGQ_TX_TIMER_INT_EN BIT(16)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_TXBCN1ERR_MSK BIT(15)
+#define BIT_TXBCN1ERR_MSK BIT(15)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_FS_PS_TIMEOUT2_EN BIT(15)
+#define BIT_FS_PS_TIMEOUT2_EN BIT(15)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_TXBCN1OK_MSK BIT(14)
+#define BIT_TXBCN1OK_MSK BIT(14)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_FS_PS_TIMEOUT1_EN BIT(14)
+#define BIT_FS_PS_TIMEOUT1_EN BIT(14)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_FT_ATIMEND_EMSK BIT(13)
+#define BIT_FT_ATIMEND_EMSK BIT(13)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_FS_PS_TIMEOUT0_EN BIT(13)
+#define BIT_FS_PS_TIMEOUT0_EN BIT(13)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_BCNDMAINT_EMSK BIT(12)
-#define BIT_GTINT5_MSK BIT(11)
-#define BIT_EOSP_INT_MSK BIT(10)
-#define BIT_RX_BCN_E_MSK BIT(9)
-#define BIT_RPWM_INT_EN BIT(8)
+#define BIT_BCNDMAINT_EMSK BIT(12)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_FS_GTINT8_EN BIT(8)
+#define BIT_FS_GTINT12_EN BIT(12)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_PSTIMER_MSK BIT(7)
+#define BIT_GTINT5_MSK BIT(11)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_FS_GTINT7_EN BIT(7)
+#define BIT_FS_GTINT11_EN BIT(11)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_TIMEOUT1_MSK BIT(6)
+#define BIT_EOSP_INT_MSK BIT(10)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_FS_GTINT6_EN BIT(6)
+#define BIT_FS_GTINT10_EN BIT(10)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_TIMEOUT0_MSK BIT(5)
+#define BIT_RX_BCN_E_MSK BIT(9)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_FS_GTINT5_EN BIT(5)
+#define BIT_FS_GTINT9_EN BIT(9)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_FT_GTINT4_MSK BIT(4)
+#define BIT_RPWM_INT_EN BIT(8)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_FS_GTINT4_EN BIT(4)
+#define BIT_FS_GTINT8_EN BIT(8)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_FT_GTINT3_MSK BIT(3)
+#define BIT_PSTIMER_MSK BIT(7)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_FS_GTINT3_EN BIT(3)
+#define BIT_FS_GTINT7_EN BIT(7)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_GTINT2_MSK BIT(2)
+#define BIT_TIMEOUT1_MSK BIT(6)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_FS_GTINT2_EN BIT(2)
+#define BIT_FS_GTINT6_EN BIT(6)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_GTINT1_MSK BIT(1)
+#define BIT_TIMEOUT0_MSK BIT(5)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_FS_GTINT1_EN BIT(1)
+#define BIT_FS_GTINT5_EN BIT(5)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_GTINT0_MSK BIT(0)
+#define BIT_FT_GTINT4_MSK BIT(4)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTIMR (Offset 0x0138) */
+
+#define BIT_FS_GTINT4_EN BIT(4)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_FS_GTINT0_EN BIT(0)
+#define BIT_FT_GTINT3_MSK BIT(3)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_FTIMR (Offset 0x0138) */
+#define BIT_FS_GTINT3_EN BIT(3)
-/* 2 REG_FTISR (Offset 0x013C) */
+#endif
-#define BIT_GT6INT BIT(31)
-#define BIT_TX_NULL1_INT BIT(30)
-#define BIT_TX_NULL0_INT BIT(29)
-#define BIT_MTI_BCNIVLEAR_INT BIT(28)
-#define BIT_ATIM_INT BIT(27)
-#define BIT_WWLAN_INT BIT(26)
-#define BIT_C2H_W_READY BIT(25)
-#define BIT_TRL_MTR_INT BIT(24)
-#define BIT_CLR_PS_STATUS BIT(23)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_FTIMR (Offset 0x0138) */
+#define BIT_GTINT2_MSK BIT(2)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_FTISR (Offset 0x013C) */
+/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_PS_TIMER_C_EARLY__INT BIT(23)
+#define BIT_FS_GTINT2_EN BIT(2)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_FTIMR (Offset 0x0138) */
-/* 2 REG_FTISR (Offset 0x013C) */
-
-#define BIT_RETRIVE_BUFFERED_INT BIT(22)
+#define BIT_GTINT1_MSK BIT(1)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FTIMR (Offset 0x0138) */
+#define BIT_FS_GTINT1_EN BIT(1)
-/* 2 REG_FTISR (Offset 0x013C) */
+#endif
-#define BIT_PS_TIMER_B_EARLY__INT BIT(22)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_FTIMR (Offset 0x0138) */
+#define BIT_GTINT0_MSK BIT(0)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_FTISR (Offset 0x013C) */
+/* 2 REG_FTIMR (Offset 0x0138) */
-#define BIT_RPWM2INT BIT(21)
+#define BIT_FS_GTINT0_EN BIT(0)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FTISR (Offset 0x013C) */
+
+#define BIT_GT6INT BIT(31)
+#define BIT_TX_NULL1_INT BIT(30)
+#define BIT_TX_NULL0_INT BIT(29)
+#define BIT_MTI_BCNIVLEAR_INT BIT(28)
+#define BIT_ATIM_INT BIT(27)
+#define BIT_WWLAN_INT BIT(26)
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_FTISR (Offset 0x013C) */
-#define BIT_PS_TIMER_A_EARLY__INT BIT(21)
+#define BIT_PS_TIMER_5_EARLY__INT BIT(26)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FTISR (Offset 0x013C) */
-#define BIT_TSF_BIT32_TOGGLE_INT_V1 BIT(20)
+#define BIT_C2H_W_READY BIT(25)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_FTISR (Offset 0x013C) */
-#define BIT_CPUMGQ_TX_TIMER_EARLY_INT BIT(20)
+#define BIT_PS_TIMER_4_EARLY__INT BIT(25)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FTISR (Offset 0x013C) */
-#define BIT_TRIGGER_PKT BIT(19)
+#define BIT_TRL_MTR_INT BIT(24)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_FTISR (Offset 0x013C) */
-#define BIT_PS_TIMER_C_INT BIT(19)
+#define BIT_PS_TIMER_3_EARLY__INT BIT(24)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FTISR (Offset 0x013C) */
-#define BIT_FW_BTCMD_INT BIT(18)
+#define BIT_CLR_PS_STATUS BIT(23)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FTISR (Offset 0x013C) */
+#define BIT_PS_TIMER_C_EARLY__INT BIT(23)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_FTISR (Offset 0x013C) */
-#define BIT_PS_TIMER_B_INT BIT(18)
+#define BIT_PS_TIMER_2_EARLY__INT BIT(23)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FTISR (Offset 0x013C) */
-#define BIT_P2P_RFOFF_INT BIT(17)
+#define BIT_RETRIEVE_BUFFERED_INT BIT(22)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FTISR (Offset 0x013C) */
+
+#define BIT_PS_TIMER_B_EARLY__INT BIT(22)
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_FTISR (Offset 0x013C) */
-#define BIT_PS_TIMER_A_INT BIT(17)
+#define BIT_PS_TIMER_1_EARLY__INT BIT(22)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FTISR (Offset 0x013C) */
-#define BIT_P2P_RFON_INT BIT(16)
+#define BIT_RPWM2INT BIT(21)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FTISR (Offset 0x013C) */
+
+#define BIT_PS_TIMER_A_EARLY__INT BIT(21)
+
+#endif
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_FTISR (Offset 0x013C) */
-#define BIT_CPUMGQ_TX_TIMER_INT BIT(16)
+#define BIT_PS_TIMER_0_EARLY__INT BIT(21)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FTISR (Offset 0x013C) */
-#define BIT_TX_BCN1ERR_INT BIT(15)
+#define BIT_TSF_BIT32_TOGGLE_INT_V1 BIT(20)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FTISR (Offset 0x013C) */
-#define BIT_FS_PS_TIMEOUT2_INT BIT(15)
+#define BIT_CPUMGQ_TX_TIMER_EARLY_INT BIT(20)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FTISR (Offset 0x013C) */
-#define BIT_TX_BCN1OK_INT BIT(14)
+#define BIT_TRIGGER_PKT BIT(19)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTISR (Offset 0x013C) */
+
+#define BIT_PS_TIMER_C_INT BIT(19)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_FTISR (Offset 0x013C) */
-#define BIT_FS_PS_TIMEOUT1_INT BIT(14)
+#define BIT_PS_TIMER_5_INT BIT(19)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FTISR (Offset 0x013C) */
-#define BIT_FT_ATIMEND_E BIT(13)
+#define BIT_FW_BTCMD_INT BIT(18)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTISR (Offset 0x013C) */
+
+#define BIT_PS_TIMER_B_INT BIT(18)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_FTISR (Offset 0x013C) */
-#define BIT_FS_PS_TIMEOUT0_INT BIT(13)
+#define BIT_PS_TIMER_4_INT BIT(18)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FTISR (Offset 0x013C) */
-#define BIT_BCNDMAINT_E_V1 BIT(12)
-#define BIT_GT5INT BIT(11)
-#define BIT_EOSP_INT BIT(10)
-#define BIT_RX_BCN_E_INT BIT(9)
-#define BIT_RPWMINT BIT(8)
+#define BIT_P2P_RFOFF_INT BIT(17)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTISR (Offset 0x013C) */
+
+#define BIT_PS_TIMER_A_INT BIT(17)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_FTISR (Offset 0x013C) */
-#define BIT_FS_GTINT8_INT BIT(8)
+#define BIT_PS_TIMER_3_INT BIT(17)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FTISR (Offset 0x013C) */
-#define BIT_PSTIMER_INT BIT(7)
+#define BIT_P2P_RFON_INT BIT(16)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_FTISR (Offset 0x013C) */
-#define BIT_FS_GTINT7_INT BIT(7)
+#define BIT_CPUMGQ_TX_TIMER_INT BIT(16)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FTISR (Offset 0x013C) */
-#define BIT_TIMEOUT1_INT BIT(6)
+#define BIT_TX_BCN1ERR_INT BIT(15)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTISR (Offset 0x013C) */
+
+#define BIT_FS_PS_TIMEOUT2_INT BIT(15)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_FTISR (Offset 0x013C) */
-#define BIT_FS_GTINT6_INT BIT(6)
+#define BIT_PS_TIMER_2_INT BIT(15)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FTISR (Offset 0x013C) */
-#define BIT_TIMEOUT0_INT BIT(5)
+#define BIT_TX_BCN1OK_INT BIT(14)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTISR (Offset 0x013C) */
+
+#define BIT_FS_PS_TIMEOUT1_INT BIT(14)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_FTISR (Offset 0x013C) */
-#define BIT_FS_GTINT5_INT BIT(5)
+#define BIT_PS_TIMER_1_INT BIT(14)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FTISR (Offset 0x013C) */
-#define BIT_FT_GT4INT BIT(4)
+#define BIT_FT_ATIMEND_E BIT(13)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FTISR (Offset 0x013C) */
+
+#define BIT_FS_PS_TIMEOUT0_INT BIT(13)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_FTISR (Offset 0x013C) */
-#define BIT_FS_GTINT4_INT BIT(4)
+#define BIT_PS_TIMER_0_INT BIT(13)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FTISR (Offset 0x013C) */
-#define BIT_FT_GT3INT BIT(3)
+#define BIT_BCNDMAINT_E_V1 BIT(12)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_FTISR (Offset 0x013C) */
-#define BIT_FS_GTINT3_INT BIT(3)
+#define BIT_FS_GTINT12_INT BIT(12)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FTISR (Offset 0x013C) */
-#define BIT_GT2INT BIT(2)
+#define BIT_GT5INT BIT(11)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_FTISR (Offset 0x013C) */
-#define BIT_FS_GTINT2_INT BIT(2)
+#define BIT_FS_GTINT11_INT BIT(11)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FTISR (Offset 0x013C) */
-#define BIT_GT1INT BIT(1)
+#define BIT_EOSP_INT BIT(10)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_FTISR (Offset 0x013C) */
-#define BIT_FS_GTINT1_INT BIT(1)
+#define BIT_FS_GTINT10_INT BIT(10)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FTISR (Offset 0x013C) */
-#define BIT_GT0INT BIT(0)
+#define BIT_RX_BCN_E_INT BIT(9)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_FTISR (Offset 0x013C) */
-#define BIT_FS_GTINT0_INT BIT(0)
+#define BIT_FS_GTINT9_INT BIT(9)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_FTISR (Offset 0x013C) */
+#define BIT_RPWMINT BIT(8)
-/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_PKTBUF_WRITE_EN 24
-#define BIT_MASK_PKTBUF_WRITE_EN 0xff
-#define BIT_PKTBUF_WRITE_EN(x) (((x) & BIT_MASK_PKTBUF_WRITE_EN) << BIT_SHIFT_PKTBUF_WRITE_EN)
-#define BIT_GET_PKTBUF_WRITE_EN(x) (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN) & BIT_MASK_PKTBUF_WRITE_EN)
+/* 2 REG_FTISR (Offset 0x013C) */
+#define BIT_FS_GTINT8_INT BIT(8)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_FTISR (Offset 0x013C) */
-/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */
-
-#define BIT_TXPKT_BUF_READ_EN BIT(23)
+#define BIT_PSTIMER_INT BIT(7)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */
+/* 2 REG_FTISR (Offset 0x013C) */
-#define BIT_TXRPTBUF_DBG BIT(23)
+#define BIT_FS_GTINT7_INT BIT(7)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_FTISR (Offset 0x013C) */
-/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */
-
-#define BIT_TXRPT_BUF_READ_EN BIT(20)
+#define BIT_TIMEOUT1_INT BIT(6)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FTISR (Offset 0x013C) */
+#define BIT_FS_GTINT6_INT BIT(6)
-/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */
+#endif
-#define BIT_TXPKTBUF_DBG_V2 BIT(20)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_FTISR (Offset 0x013C) */
+#define BIT_TIMEOUT0_INT BIT(5)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */
+/* 2 REG_FTISR (Offset 0x013C) */
-#define BIT_RXPKT_BUF_READ_EN BIT(16)
+#define BIT_FS_GTINT5_INT BIT(5)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FTISR (Offset 0x013C) */
+#define BIT_FT_GT4INT BIT(4)
-/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */
+#endif
-#define BIT_RXPKTBUF_DBG BIT(16)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_FTISR (Offset 0x013C) */
+#define BIT_FS_GTINT4_INT BIT(4)
+
+#endif
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_FTISR (Offset 0x013C) */
-/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */
+#define BIT_FT_GT3INT BIT(3)
+
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_PKTBUF_ADDR 0
-#define BIT_MASK_PKTBUF_ADDR 0x1fff
-#define BIT_PKTBUF_ADDR(x) (((x) & BIT_MASK_PKTBUF_ADDR) << BIT_SHIFT_PKTBUF_ADDR)
-#define BIT_GET_PKTBUF_ADDR(x) (((x) >> BIT_SHIFT_PKTBUF_ADDR) & BIT_MASK_PKTBUF_ADDR)
+/* 2 REG_FTISR (Offset 0x013C) */
+#define BIT_FS_GTINT3_INT BIT(3)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FTISR (Offset 0x013C) */
+#define BIT_GT2INT BIT(2)
-/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_PKTBUF_DBG_ADDR 0
-#define BIT_MASK_PKTBUF_DBG_ADDR 0x1fff
-#define BIT_PKTBUF_DBG_ADDR(x) (((x) & BIT_MASK_PKTBUF_DBG_ADDR) << BIT_SHIFT_PKTBUF_DBG_ADDR)
-#define BIT_GET_PKTBUF_DBG_ADDR(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR) & BIT_MASK_PKTBUF_DBG_ADDR)
+/* 2 REG_FTISR (Offset 0x013C) */
+#define BIT_FS_GTINT2_INT BIT(2)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_FTISR (Offset 0x013C) */
+#define BIT_GT1INT BIT(1)
-/* 2 REG_PKTBUF_DBG_DATA_L (Offset 0x0144) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_PKTBUF_DBG_DATA_L 0
-#define BIT_MASK_PKTBUF_DBG_DATA_L 0xffffffffL
-#define BIT_PKTBUF_DBG_DATA_L(x) (((x) & BIT_MASK_PKTBUF_DBG_DATA_L) << BIT_SHIFT_PKTBUF_DBG_DATA_L)
-#define BIT_GET_PKTBUF_DBG_DATA_L(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L) & BIT_MASK_PKTBUF_DBG_DATA_L)
+/* 2 REG_FTISR (Offset 0x013C) */
+#define BIT_FS_GTINT1_INT BIT(1)
-/* 2 REG_PKTBUF_DBG_DATA_H (Offset 0x0148) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_PKTBUF_DBG_DATA_H 0
-#define BIT_MASK_PKTBUF_DBG_DATA_H 0xffffffffL
-#define BIT_PKTBUF_DBG_DATA_H(x) (((x) & BIT_MASK_PKTBUF_DBG_DATA_H) << BIT_SHIFT_PKTBUF_DBG_DATA_H)
-#define BIT_GET_PKTBUF_DBG_DATA_H(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H) & BIT_MASK_PKTBUF_DBG_DATA_H)
+/* 2 REG_FTISR (Offset 0x013C) */
+#define BIT_GT0INT BIT(0)
-/* 2 REG_CPWM2 (Offset 0x014C) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_L0S_TO_RCVY_NUM 16
-#define BIT_MASK_L0S_TO_RCVY_NUM 0xff
-#define BIT_L0S_TO_RCVY_NUM(x) (((x) & BIT_MASK_L0S_TO_RCVY_NUM) << BIT_SHIFT_L0S_TO_RCVY_NUM)
-#define BIT_GET_L0S_TO_RCVY_NUM(x) (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM) & BIT_MASK_L0S_TO_RCVY_NUM)
+/* 2 REG_FTISR (Offset 0x013C) */
-#define BIT_CPWM2_TOGGLING BIT(15)
+#define BIT_FS_GTINT0_INT BIT(0)
-#define BIT_SHIFT_CPWM2_MOD 0
-#define BIT_MASK_CPWM2_MOD 0x7fff
-#define BIT_CPWM2_MOD(x) (((x) & BIT_MASK_CPWM2_MOD) << BIT_SHIFT_CPWM2_MOD)
-#define BIT_GET_CPWM2_MOD(x) (((x) >> BIT_SHIFT_CPWM2_MOD) & BIT_MASK_CPWM2_MOD)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-/* 2 REG_TC0_CTRL (Offset 0x0150) */
+/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */
-#define BIT_TC0INT_EN BIT(26)
-#define BIT_TC0MODE BIT(25)
-#define BIT_TC0EN BIT(24)
+#define BIT_SHIFT_PKTBUF_WRITE_EN 24
+#define BIT_MASK_PKTBUF_WRITE_EN 0xff
+#define BIT_PKTBUF_WRITE_EN(x) \
+ (((x) & BIT_MASK_PKTBUF_WRITE_EN) << BIT_SHIFT_PKTBUF_WRITE_EN)
+#define BITS_PKTBUF_WRITE_EN \
+ (BIT_MASK_PKTBUF_WRITE_EN << BIT_SHIFT_PKTBUF_WRITE_EN)
+#define BIT_CLEAR_PKTBUF_WRITE_EN(x) ((x) & (~BITS_PKTBUF_WRITE_EN))
+#define BIT_GET_PKTBUF_WRITE_EN(x) \
+ (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN) & BIT_MASK_PKTBUF_WRITE_EN)
+#define BIT_SET_PKTBUF_WRITE_EN(x, v) \
+ (BIT_CLEAR_PKTBUF_WRITE_EN(x) | BIT_PKTBUF_WRITE_EN(v))
-#define BIT_SHIFT_TC0DATA 0
-#define BIT_MASK_TC0DATA 0xffffff
-#define BIT_TC0DATA(x) (((x) & BIT_MASK_TC0DATA) << BIT_SHIFT_TC0DATA)
-#define BIT_GET_TC0DATA(x) (((x) >> BIT_SHIFT_TC0DATA) & BIT_MASK_TC0DATA)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_TC1_CTRL (Offset 0x0154) */
+/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */
-#define BIT_TC1INT_EN BIT(26)
-#define BIT_TC1MODE BIT(25)
-#define BIT_TC1EN BIT(24)
+#define BIT_TXPKT_BUF_READ_EN BIT(23)
-#define BIT_SHIFT_TC1DATA 0
-#define BIT_MASK_TC1DATA 0xffffff
-#define BIT_TC1DATA(x) (((x) & BIT_MASK_TC1DATA) << BIT_SHIFT_TC1DATA)
-#define BIT_GET_TC1DATA(x) (((x) >> BIT_SHIFT_TC1DATA) & BIT_MASK_TC1DATA)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_TC2_CTRL (Offset 0x0158) */
+/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */
-#define BIT_TC2INT_EN BIT(26)
-#define BIT_TC2MODE BIT(25)
-#define BIT_TC2EN BIT(24)
+#define BIT_TXRPTBUF_DBG BIT(23)
-#define BIT_SHIFT_TC2DATA 0
-#define BIT_MASK_TC2DATA 0xffffff
-#define BIT_TC2DATA(x) (((x) & BIT_MASK_TC2DATA) << BIT_SHIFT_TC2DATA)
-#define BIT_GET_TC2DATA(x) (((x) >> BIT_SHIFT_TC2DATA) & BIT_MASK_TC2DATA)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_TC3_CTRL (Offset 0x015C) */
+/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */
-#define BIT_TC3INT_EN BIT(26)
-#define BIT_TC3MODE BIT(25)
-#define BIT_TC3EN BIT(24)
+#define BIT_TXRPT_BUF_READ_EN BIT(20)
-#define BIT_SHIFT_TC3DATA 0
-#define BIT_MASK_TC3DATA 0xffffff
-#define BIT_TC3DATA(x) (((x) & BIT_MASK_TC3DATA) << BIT_SHIFT_TC3DATA)
-#define BIT_GET_TC3DATA(x) (((x) >> BIT_SHIFT_TC3DATA) & BIT_MASK_TC3DATA)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_TC4_CTRL (Offset 0x0160) */
+/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */
-#define BIT_TC4INT_EN BIT(26)
-#define BIT_TC4MODE BIT(25)
-#define BIT_TC4EN BIT(24)
+#define BIT_TXPKTBUF_DBG_V2 BIT(20)
-#define BIT_SHIFT_TC4DATA 0
-#define BIT_MASK_TC4DATA 0xffffff
-#define BIT_TC4DATA(x) (((x) & BIT_MASK_TC4DATA) << BIT_SHIFT_TC4DATA)
-#define BIT_GET_TC4DATA(x) (((x) >> BIT_SHIFT_TC4DATA) & BIT_MASK_TC4DATA)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_TCUNIT_BASE (Offset 0x0164) */
+/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */
+#define BIT_RXPKT_BUF_READ_EN BIT(16)
-#define BIT_SHIFT_TCUNIT_BASE 0
-#define BIT_MASK_TCUNIT_BASE 0x3fff
-#define BIT_TCUNIT_BASE(x) (((x) & BIT_MASK_TCUNIT_BASE) << BIT_SHIFT_TCUNIT_BASE)
-#define BIT_GET_TCUNIT_BASE(x) (((x) >> BIT_SHIFT_TCUNIT_BASE) & BIT_MASK_TCUNIT_BASE)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */
+#define BIT_RXPKTBUF_DBG BIT(16)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_TC5_CTRL (Offset 0x0168) */
+/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */
-#define BIT_TC50INT_EN BIT(26)
+#define BIT_SHIFT_PKTBUF_ADDR 0
+#define BIT_MASK_PKTBUF_ADDR 0x1fff
+#define BIT_PKTBUF_ADDR(x) \
+ (((x) & BIT_MASK_PKTBUF_ADDR) << BIT_SHIFT_PKTBUF_ADDR)
+#define BITS_PKTBUF_ADDR (BIT_MASK_PKTBUF_ADDR << BIT_SHIFT_PKTBUF_ADDR)
+#define BIT_CLEAR_PKTBUF_ADDR(x) ((x) & (~BITS_PKTBUF_ADDR))
+#define BIT_GET_PKTBUF_ADDR(x) \
+ (((x) >> BIT_SHIFT_PKTBUF_ADDR) & BIT_MASK_PKTBUF_ADDR)
+#define BIT_SET_PKTBUF_ADDR(x, v) \
+ (BIT_CLEAR_PKTBUF_ADDR(x) | BIT_PKTBUF_ADDR(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */
+#define BIT_SHIFT_PKTBUF_DBG_ADDR 0
+#define BIT_MASK_PKTBUF_DBG_ADDR 0x1fff
+#define BIT_PKTBUF_DBG_ADDR(x) \
+ (((x) & BIT_MASK_PKTBUF_DBG_ADDR) << BIT_SHIFT_PKTBUF_DBG_ADDR)
+#define BITS_PKTBUF_DBG_ADDR \
+ (BIT_MASK_PKTBUF_DBG_ADDR << BIT_SHIFT_PKTBUF_DBG_ADDR)
+#define BIT_CLEAR_PKTBUF_DBG_ADDR(x) ((x) & (~BITS_PKTBUF_DBG_ADDR))
+#define BIT_GET_PKTBUF_DBG_ADDR(x) \
+ (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR) & BIT_MASK_PKTBUF_DBG_ADDR)
+#define BIT_SET_PKTBUF_DBG_ADDR(x, v) \
+ (BIT_CLEAR_PKTBUF_DBG_ADDR(x) | BIT_PKTBUF_DBG_ADDR(v))
-/* 2 REG_TC5_CTRL (Offset 0x0168) */
+#endif
-#define BIT_TC5INT_EN BIT(26)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_PKTBUF_DBG_DATA_L (Offset 0x0144) */
+#define BIT_SHIFT_PKTBUF_DBG_DATA_L 0
+#define BIT_MASK_PKTBUF_DBG_DATA_L 0xffffffffL
+#define BIT_PKTBUF_DBG_DATA_L(x) \
+ (((x) & BIT_MASK_PKTBUF_DBG_DATA_L) << BIT_SHIFT_PKTBUF_DBG_DATA_L)
+#define BITS_PKTBUF_DBG_DATA_L \
+ (BIT_MASK_PKTBUF_DBG_DATA_L << BIT_SHIFT_PKTBUF_DBG_DATA_L)
+#define BIT_CLEAR_PKTBUF_DBG_DATA_L(x) ((x) & (~BITS_PKTBUF_DBG_DATA_L))
+#define BIT_GET_PKTBUF_DBG_DATA_L(x) \
+ (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L) & BIT_MASK_PKTBUF_DBG_DATA_L)
+#define BIT_SET_PKTBUF_DBG_DATA_L(x, v) \
+ (BIT_CLEAR_PKTBUF_DBG_DATA_L(x) | BIT_PKTBUF_DBG_DATA_L(v))
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_PKTBUF_DBG_DATA_H (Offset 0x0148) */
+#define BIT_SHIFT_PKTBUF_DBG_DATA_H 0
+#define BIT_MASK_PKTBUF_DBG_DATA_H 0xffffffffL
+#define BIT_PKTBUF_DBG_DATA_H(x) \
+ (((x) & BIT_MASK_PKTBUF_DBG_DATA_H) << BIT_SHIFT_PKTBUF_DBG_DATA_H)
+#define BITS_PKTBUF_DBG_DATA_H \
+ (BIT_MASK_PKTBUF_DBG_DATA_H << BIT_SHIFT_PKTBUF_DBG_DATA_H)
+#define BIT_CLEAR_PKTBUF_DBG_DATA_H(x) ((x) & (~BITS_PKTBUF_DBG_DATA_H))
+#define BIT_GET_PKTBUF_DBG_DATA_H(x) \
+ (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H) & BIT_MASK_PKTBUF_DBG_DATA_H)
+#define BIT_SET_PKTBUF_DBG_DATA_H(x, v) \
+ (BIT_CLEAR_PKTBUF_DBG_DATA_H(x) | BIT_PKTBUF_DBG_DATA_H(v))
-/* 2 REG_TC5_CTRL (Offset 0x0168) */
+/* 2 REG_CPWM2 (Offset 0x014C) */
-#define BIT_TC5MODE BIT(25)
-#define BIT_TC5EN BIT(24)
+#define BIT_SHIFT_L0S_TO_RCVY_NUM 16
+#define BIT_MASK_L0S_TO_RCVY_NUM 0xff
+#define BIT_L0S_TO_RCVY_NUM(x) \
+ (((x) & BIT_MASK_L0S_TO_RCVY_NUM) << BIT_SHIFT_L0S_TO_RCVY_NUM)
+#define BITS_L0S_TO_RCVY_NUM \
+ (BIT_MASK_L0S_TO_RCVY_NUM << BIT_SHIFT_L0S_TO_RCVY_NUM)
+#define BIT_CLEAR_L0S_TO_RCVY_NUM(x) ((x) & (~BITS_L0S_TO_RCVY_NUM))
+#define BIT_GET_L0S_TO_RCVY_NUM(x) \
+ (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM) & BIT_MASK_L0S_TO_RCVY_NUM)
+#define BIT_SET_L0S_TO_RCVY_NUM(x, v) \
+ (BIT_CLEAR_L0S_TO_RCVY_NUM(x) | BIT_L0S_TO_RCVY_NUM(v))
+
+#define BIT_CPWM2_TOGGLING BIT(15)
+
+#define BIT_SHIFT_CPWM2_MOD 0
+#define BIT_MASK_CPWM2_MOD 0x7fff
+#define BIT_CPWM2_MOD(x) (((x) & BIT_MASK_CPWM2_MOD) << BIT_SHIFT_CPWM2_MOD)
+#define BITS_CPWM2_MOD (BIT_MASK_CPWM2_MOD << BIT_SHIFT_CPWM2_MOD)
+#define BIT_CLEAR_CPWM2_MOD(x) ((x) & (~BITS_CPWM2_MOD))
+#define BIT_GET_CPWM2_MOD(x) (((x) >> BIT_SHIFT_CPWM2_MOD) & BIT_MASK_CPWM2_MOD)
+#define BIT_SET_CPWM2_MOD(x, v) (BIT_CLEAR_CPWM2_MOD(x) | BIT_CPWM2_MOD(v))
-#define BIT_SHIFT_TC5DATA 0
-#define BIT_MASK_TC5DATA 0xffffff
-#define BIT_TC5DATA(x) (((x) & BIT_MASK_TC5DATA) << BIT_SHIFT_TC5DATA)
-#define BIT_GET_TC5DATA(x) (((x) >> BIT_SHIFT_TC5DATA) & BIT_MASK_TC5DATA)
+/* 2 REG_TC0_CTRL (Offset 0x0150) */
+#define BIT_TC0INT_EN BIT(26)
+#define BIT_TC0MODE BIT(25)
+#define BIT_TC0EN BIT(24)
-#endif
+#define BIT_SHIFT_TC0DATA 0
+#define BIT_MASK_TC0DATA 0xffffff
+#define BIT_TC0DATA(x) (((x) & BIT_MASK_TC0DATA) << BIT_SHIFT_TC0DATA)
+#define BITS_TC0DATA (BIT_MASK_TC0DATA << BIT_SHIFT_TC0DATA)
+#define BIT_CLEAR_TC0DATA(x) ((x) & (~BITS_TC0DATA))
+#define BIT_GET_TC0DATA(x) (((x) >> BIT_SHIFT_TC0DATA) & BIT_MASK_TC0DATA)
+#define BIT_SET_TC0DATA(x, v) (BIT_CLEAR_TC0DATA(x) | BIT_TC0DATA(v))
+/* 2 REG_TC1_CTRL (Offset 0x0154) */
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+#define BIT_TC1INT_EN BIT(26)
+#define BIT_TC1MODE BIT(25)
+#define BIT_TC1EN BIT(24)
+#define BIT_SHIFT_TC1DATA 0
+#define BIT_MASK_TC1DATA 0xffffff
+#define BIT_TC1DATA(x) (((x) & BIT_MASK_TC1DATA) << BIT_SHIFT_TC1DATA)
+#define BITS_TC1DATA (BIT_MASK_TC1DATA << BIT_SHIFT_TC1DATA)
+#define BIT_CLEAR_TC1DATA(x) ((x) & (~BITS_TC1DATA))
+#define BIT_GET_TC1DATA(x) (((x) >> BIT_SHIFT_TC1DATA) & BIT_MASK_TC1DATA)
+#define BIT_SET_TC1DATA(x, v) (BIT_CLEAR_TC1DATA(x) | BIT_TC1DATA(v))
-/* 2 REG_TC6_CTRL (Offset 0x016C) */
+/* 2 REG_TC2_CTRL (Offset 0x0158) */
-#define BIT_TC60INT_EN BIT(26)
+#define BIT_TC2INT_EN BIT(26)
+#define BIT_TC2MODE BIT(25)
+#define BIT_TC2EN BIT(24)
-#endif
+#define BIT_SHIFT_TC2DATA 0
+#define BIT_MASK_TC2DATA 0xffffff
+#define BIT_TC2DATA(x) (((x) & BIT_MASK_TC2DATA) << BIT_SHIFT_TC2DATA)
+#define BITS_TC2DATA (BIT_MASK_TC2DATA << BIT_SHIFT_TC2DATA)
+#define BIT_CLEAR_TC2DATA(x) ((x) & (~BITS_TC2DATA))
+#define BIT_GET_TC2DATA(x) (((x) >> BIT_SHIFT_TC2DATA) & BIT_MASK_TC2DATA)
+#define BIT_SET_TC2DATA(x, v) (BIT_CLEAR_TC2DATA(x) | BIT_TC2DATA(v))
+/* 2 REG_TC3_CTRL (Offset 0x015C) */
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#define BIT_TC3INT_EN BIT(26)
+#define BIT_TC3MODE BIT(25)
+#define BIT_TC3EN BIT(24)
+#define BIT_SHIFT_TC3DATA 0
+#define BIT_MASK_TC3DATA 0xffffff
+#define BIT_TC3DATA(x) (((x) & BIT_MASK_TC3DATA) << BIT_SHIFT_TC3DATA)
+#define BITS_TC3DATA (BIT_MASK_TC3DATA << BIT_SHIFT_TC3DATA)
+#define BIT_CLEAR_TC3DATA(x) ((x) & (~BITS_TC3DATA))
+#define BIT_GET_TC3DATA(x) (((x) >> BIT_SHIFT_TC3DATA) & BIT_MASK_TC3DATA)
+#define BIT_SET_TC3DATA(x, v) (BIT_CLEAR_TC3DATA(x) | BIT_TC3DATA(v))
-/* 2 REG_TC6_CTRL (Offset 0x016C) */
+/* 2 REG_TC4_CTRL (Offset 0x0160) */
-#define BIT_TC6INT_EN BIT(26)
+#define BIT_TC4INT_EN BIT(26)
+#define BIT_TC4MODE BIT(25)
+#define BIT_TC4EN BIT(24)
-#endif
+#define BIT_SHIFT_TC4DATA 0
+#define BIT_MASK_TC4DATA 0xffffff
+#define BIT_TC4DATA(x) (((x) & BIT_MASK_TC4DATA) << BIT_SHIFT_TC4DATA)
+#define BITS_TC4DATA (BIT_MASK_TC4DATA << BIT_SHIFT_TC4DATA)
+#define BIT_CLEAR_TC4DATA(x) ((x) & (~BITS_TC4DATA))
+#define BIT_GET_TC4DATA(x) (((x) >> BIT_SHIFT_TC4DATA) & BIT_MASK_TC4DATA)
+#define BIT_SET_TC4DATA(x, v) (BIT_CLEAR_TC4DATA(x) | BIT_TC4DATA(v))
+/* 2 REG_TCUNIT_BASE (Offset 0x0164) */
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#define BIT_SHIFT_TCUNIT_BASE 0
+#define BIT_MASK_TCUNIT_BASE 0x3fff
+#define BIT_TCUNIT_BASE(x) \
+ (((x) & BIT_MASK_TCUNIT_BASE) << BIT_SHIFT_TCUNIT_BASE)
+#define BITS_TCUNIT_BASE (BIT_MASK_TCUNIT_BASE << BIT_SHIFT_TCUNIT_BASE)
+#define BIT_CLEAR_TCUNIT_BASE(x) ((x) & (~BITS_TCUNIT_BASE))
+#define BIT_GET_TCUNIT_BASE(x) \
+ (((x) >> BIT_SHIFT_TCUNIT_BASE) & BIT_MASK_TCUNIT_BASE)
+#define BIT_SET_TCUNIT_BASE(x, v) \
+ (BIT_CLEAR_TCUNIT_BASE(x) | BIT_TCUNIT_BASE(v))
+#endif
-/* 2 REG_TC6_CTRL (Offset 0x016C) */
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_TC6MODE BIT(25)
-#define BIT_TC6EN BIT(24)
+/* 2 REG_TC5_CTRL (Offset 0x0168) */
-#define BIT_SHIFT_TC6DATA 0
-#define BIT_MASK_TC6DATA 0xffffff
-#define BIT_TC6DATA(x) (((x) & BIT_MASK_TC6DATA) << BIT_SHIFT_TC6DATA)
-#define BIT_GET_TC6DATA(x) (((x) >> BIT_SHIFT_TC6DATA) & BIT_MASK_TC6DATA)
+#define BIT_TC50INT_EN BIT(26)
+#endif
-/* 2 REG_MBIST_FAIL (Offset 0x0170) */
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+/* 2 REG_TC5_CTRL (Offset 0x0168) */
-#define BIT_SHIFT_8051_MBIST_FAIL 26
-#define BIT_MASK_8051_MBIST_FAIL 0x7
-#define BIT_8051_MBIST_FAIL(x) (((x) & BIT_MASK_8051_MBIST_FAIL) << BIT_SHIFT_8051_MBIST_FAIL)
-#define BIT_GET_8051_MBIST_FAIL(x) (((x) >> BIT_SHIFT_8051_MBIST_FAIL) & BIT_MASK_8051_MBIST_FAIL)
+#define BIT_TC5INT_EN BIT(26)
+#endif
-#define BIT_SHIFT_USB_MBIST_FAIL 24
-#define BIT_MASK_USB_MBIST_FAIL 0x3
-#define BIT_USB_MBIST_FAIL(x) (((x) & BIT_MASK_USB_MBIST_FAIL) << BIT_SHIFT_USB_MBIST_FAIL)
-#define BIT_GET_USB_MBIST_FAIL(x) (((x) >> BIT_SHIFT_USB_MBIST_FAIL) & BIT_MASK_USB_MBIST_FAIL)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+/* 2 REG_TC5_CTRL (Offset 0x0168) */
-#define BIT_SHIFT_PCIE_MBIST_FAIL 16
-#define BIT_MASK_PCIE_MBIST_FAIL 0x3f
-#define BIT_PCIE_MBIST_FAIL(x) (((x) & BIT_MASK_PCIE_MBIST_FAIL) << BIT_SHIFT_PCIE_MBIST_FAIL)
-#define BIT_GET_PCIE_MBIST_FAIL(x) (((x) >> BIT_SHIFT_PCIE_MBIST_FAIL) & BIT_MASK_PCIE_MBIST_FAIL)
+#define BIT_TC5MODE BIT(25)
+#define BIT_TC5EN BIT(24)
+#define BIT_SHIFT_TC5DATA 0
+#define BIT_MASK_TC5DATA 0xffffff
+#define BIT_TC5DATA(x) (((x) & BIT_MASK_TC5DATA) << BIT_SHIFT_TC5DATA)
+#define BITS_TC5DATA (BIT_MASK_TC5DATA << BIT_SHIFT_TC5DATA)
+#define BIT_CLEAR_TC5DATA(x) ((x) & (~BITS_TC5DATA))
+#define BIT_GET_TC5DATA(x) (((x) >> BIT_SHIFT_TC5DATA) & BIT_MASK_TC5DATA)
+#define BIT_SET_TC5DATA(x, v) (BIT_CLEAR_TC5DATA(x) | BIT_TC5DATA(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_TC6_CTRL (Offset 0x016C) */
+#define BIT_TC60INT_EN BIT(26)
-/* 2 REG_MBIST_FAIL (Offset 0x0170) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_MAC_MBIST_FAIL 0
-#define BIT_MASK_MAC_MBIST_FAIL 0xfff
-#define BIT_MAC_MBIST_FAIL(x) (((x) & BIT_MASK_MAC_MBIST_FAIL) << BIT_SHIFT_MAC_MBIST_FAIL)
-#define BIT_GET_MAC_MBIST_FAIL(x) (((x) >> BIT_SHIFT_MAC_MBIST_FAIL) & BIT_MASK_MAC_MBIST_FAIL)
+/* 2 REG_TC6_CTRL (Offset 0x016C) */
+#define BIT_TC6INT_EN BIT(26)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
+/* 2 REG_TC6_CTRL (Offset 0x016C) */
-/* 2 REG_MBIST_FAIL (Offset 0x0170) */
+#define BIT_TC6MODE BIT(25)
+#define BIT_TC6EN BIT(24)
+#define BIT_SHIFT_TC6DATA 0
+#define BIT_MASK_TC6DATA 0xffffff
+#define BIT_TC6DATA(x) (((x) & BIT_MASK_TC6DATA) << BIT_SHIFT_TC6DATA)
+#define BITS_TC6DATA (BIT_MASK_TC6DATA << BIT_SHIFT_TC6DATA)
+#define BIT_CLEAR_TC6DATA(x) ((x) & (~BITS_TC6DATA))
+#define BIT_GET_TC6DATA(x) (((x) >> BIT_SHIFT_TC6DATA) & BIT_MASK_TC6DATA)
+#define BIT_SET_TC6DATA(x, v) (BIT_CLEAR_TC6DATA(x) | BIT_TC6DATA(v))
-#define BIT_SHIFT_MAC_MBIST_FAIL_DRF 0
-#define BIT_MASK_MAC_MBIST_FAIL_DRF 0x3ffff
-#define BIT_MAC_MBIST_FAIL_DRF(x) (((x) & BIT_MASK_MAC_MBIST_FAIL_DRF) << BIT_SHIFT_MAC_MBIST_FAIL_DRF)
-#define BIT_GET_MAC_MBIST_FAIL_DRF(x) (((x) >> BIT_SHIFT_MAC_MBIST_FAIL_DRF) & BIT_MASK_MAC_MBIST_FAIL_DRF)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_MBIST_FAIL (Offset 0x0170) */
+#define BIT_SHIFT_8051_MBIST_FAIL 26
+#define BIT_MASK_8051_MBIST_FAIL 0x7
+#define BIT_8051_MBIST_FAIL(x) \
+ (((x) & BIT_MASK_8051_MBIST_FAIL) << BIT_SHIFT_8051_MBIST_FAIL)
+#define BITS_8051_MBIST_FAIL \
+ (BIT_MASK_8051_MBIST_FAIL << BIT_SHIFT_8051_MBIST_FAIL)
+#define BIT_CLEAR_8051_MBIST_FAIL(x) ((x) & (~BITS_8051_MBIST_FAIL))
+#define BIT_GET_8051_MBIST_FAIL(x) \
+ (((x) >> BIT_SHIFT_8051_MBIST_FAIL) & BIT_MASK_8051_MBIST_FAIL)
+#define BIT_SET_8051_MBIST_FAIL(x, v) \
+ (BIT_CLEAR_8051_MBIST_FAIL(x) | BIT_8051_MBIST_FAIL(v))
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */
+/* 2 REG_MBIST_DRF_FAIL (Offset 0x0170) */
+#define BIT_SHIFT_8051_MBIST_DRF_FAIL 26
+#define BIT_MASK_8051_MBIST_DRF_FAIL 0x3f
+#define BIT_8051_MBIST_DRF_FAIL(x) \
+ (((x) & BIT_MASK_8051_MBIST_DRF_FAIL) << BIT_SHIFT_8051_MBIST_DRF_FAIL)
+#define BITS_8051_MBIST_DRF_FAIL \
+ (BIT_MASK_8051_MBIST_DRF_FAIL << BIT_SHIFT_8051_MBIST_DRF_FAIL)
+#define BIT_CLEAR_8051_MBIST_DRF_FAIL(x) ((x) & (~BITS_8051_MBIST_DRF_FAIL))
+#define BIT_GET_8051_MBIST_DRF_FAIL(x) \
+ (((x) >> BIT_SHIFT_8051_MBIST_DRF_FAIL) & BIT_MASK_8051_MBIST_DRF_FAIL)
+#define BIT_SET_8051_MBIST_DRF_FAIL(x, v) \
+ (BIT_CLEAR_8051_MBIST_DRF_FAIL(x) | BIT_8051_MBIST_DRF_FAIL(v))
-#define BIT_SHIFT_8051_MBIST_START_PAUSE 26
-#define BIT_MASK_8051_MBIST_START_PAUSE 0x7
-#define BIT_8051_MBIST_START_PAUSE(x) (((x) & BIT_MASK_8051_MBIST_START_PAUSE) << BIT_SHIFT_8051_MBIST_START_PAUSE)
-#define BIT_GET_8051_MBIST_START_PAUSE(x) (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE) & BIT_MASK_8051_MBIST_START_PAUSE)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_USB_MBIST_START_PAUSE 24
-#define BIT_MASK_USB_MBIST_START_PAUSE 0x3
-#define BIT_USB_MBIST_START_PAUSE(x) (((x) & BIT_MASK_USB_MBIST_START_PAUSE) << BIT_SHIFT_USB_MBIST_START_PAUSE)
-#define BIT_GET_USB_MBIST_START_PAUSE(x) (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE) & BIT_MASK_USB_MBIST_START_PAUSE)
+/* 2 REG_MBIST_FAIL (Offset 0x0170) */
+#define BIT_SHIFT_USB_MBIST_FAIL 24
+#define BIT_MASK_USB_MBIST_FAIL 0x3
+#define BIT_USB_MBIST_FAIL(x) \
+ (((x) & BIT_MASK_USB_MBIST_FAIL) << BIT_SHIFT_USB_MBIST_FAIL)
+#define BITS_USB_MBIST_FAIL \
+ (BIT_MASK_USB_MBIST_FAIL << BIT_SHIFT_USB_MBIST_FAIL)
+#define BIT_CLEAR_USB_MBIST_FAIL(x) ((x) & (~BITS_USB_MBIST_FAIL))
+#define BIT_GET_USB_MBIST_FAIL(x) \
+ (((x) >> BIT_SHIFT_USB_MBIST_FAIL) & BIT_MASK_USB_MBIST_FAIL)
+#define BIT_SET_USB_MBIST_FAIL(x, v) \
+ (BIT_CLEAR_USB_MBIST_FAIL(x) | BIT_USB_MBIST_FAIL(v))
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MBIST_DRF_FAIL (Offset 0x0170) */
+
+#define BIT_SHIFT_USB_MBIST_DRF_FAIL 24
+#define BIT_MASK_USB_MBIST_DRF_FAIL 0x3
+#define BIT_USB_MBIST_DRF_FAIL(x) \
+ (((x) & BIT_MASK_USB_MBIST_DRF_FAIL) << BIT_SHIFT_USB_MBIST_DRF_FAIL)
+#define BITS_USB_MBIST_DRF_FAIL \
+ (BIT_MASK_USB_MBIST_DRF_FAIL << BIT_SHIFT_USB_MBIST_DRF_FAIL)
+#define BIT_CLEAR_USB_MBIST_DRF_FAIL(x) ((x) & (~BITS_USB_MBIST_DRF_FAIL))
+#define BIT_GET_USB_MBIST_DRF_FAIL(x) \
+ (((x) >> BIT_SHIFT_USB_MBIST_DRF_FAIL) & BIT_MASK_USB_MBIST_DRF_FAIL)
+#define BIT_SET_USB_MBIST_DRF_FAIL(x, v) \
+ (BIT_CLEAR_USB_MBIST_DRF_FAIL(x) | BIT_USB_MBIST_DRF_FAIL(v))
+
+#define BIT_SHIFT_PCIE_MBIST_DRF_FAIL 18
+#define BIT_MASK_PCIE_MBIST_DRF_FAIL 0x3f
+#define BIT_PCIE_MBIST_DRF_FAIL(x) \
+ (((x) & BIT_MASK_PCIE_MBIST_DRF_FAIL) << BIT_SHIFT_PCIE_MBIST_DRF_FAIL)
+#define BITS_PCIE_MBIST_DRF_FAIL \
+ (BIT_MASK_PCIE_MBIST_DRF_FAIL << BIT_SHIFT_PCIE_MBIST_DRF_FAIL)
+#define BIT_CLEAR_PCIE_MBIST_DRF_FAIL(x) ((x) & (~BITS_PCIE_MBIST_DRF_FAIL))
+#define BIT_GET_PCIE_MBIST_DRF_FAIL(x) \
+ (((x) >> BIT_SHIFT_PCIE_MBIST_DRF_FAIL) & BIT_MASK_PCIE_MBIST_DRF_FAIL)
+#define BIT_SET_PCIE_MBIST_DRF_FAIL(x, v) \
+ (BIT_CLEAR_PCIE_MBIST_DRF_FAIL(x) | BIT_PCIE_MBIST_DRF_FAIL(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_PCIE_MBIST_START_PAUSE 16
-#define BIT_MASK_PCIE_MBIST_START_PAUSE 0x3f
-#define BIT_PCIE_MBIST_START_PAUSE(x) (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE) << BIT_SHIFT_PCIE_MBIST_START_PAUSE)
-#define BIT_GET_PCIE_MBIST_START_PAUSE(x) (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE) & BIT_MASK_PCIE_MBIST_START_PAUSE)
+/* 2 REG_MBIST_FAIL (Offset 0x0170) */
+#define BIT_SHIFT_PCIE_MBIST_FAIL 16
+#define BIT_MASK_PCIE_MBIST_FAIL 0x3f
+#define BIT_PCIE_MBIST_FAIL(x) \
+ (((x) & BIT_MASK_PCIE_MBIST_FAIL) << BIT_SHIFT_PCIE_MBIST_FAIL)
+#define BITS_PCIE_MBIST_FAIL \
+ (BIT_MASK_PCIE_MBIST_FAIL << BIT_SHIFT_PCIE_MBIST_FAIL)
+#define BIT_CLEAR_PCIE_MBIST_FAIL(x) ((x) & (~BITS_PCIE_MBIST_FAIL))
+#define BIT_GET_PCIE_MBIST_FAIL(x) \
+ (((x) >> BIT_SHIFT_PCIE_MBIST_FAIL) & BIT_MASK_PCIE_MBIST_FAIL)
+#define BIT_SET_PCIE_MBIST_FAIL(x, v) \
+ (BIT_CLEAR_PCIE_MBIST_FAIL(x) | BIT_PCIE_MBIST_FAIL(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_MBIST_FAIL (Offset 0x0170) */
+#define BIT_SHIFT_MAC_MBIST_FAIL 0
+#define BIT_MASK_MAC_MBIST_FAIL 0xfff
+#define BIT_MAC_MBIST_FAIL(x) \
+ (((x) & BIT_MASK_MAC_MBIST_FAIL) << BIT_SHIFT_MAC_MBIST_FAIL)
+#define BITS_MAC_MBIST_FAIL \
+ (BIT_MASK_MAC_MBIST_FAIL << BIT_SHIFT_MAC_MBIST_FAIL)
+#define BIT_CLEAR_MAC_MBIST_FAIL(x) ((x) & (~BITS_MAC_MBIST_FAIL))
+#define BIT_GET_MAC_MBIST_FAIL(x) \
+ (((x) >> BIT_SHIFT_MAC_MBIST_FAIL) & BIT_MASK_MAC_MBIST_FAIL)
+#define BIT_SET_MAC_MBIST_FAIL(x, v) \
+ (BIT_CLEAR_MAC_MBIST_FAIL(x) | BIT_MAC_MBIST_FAIL(v))
-/* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_MAC_MBIST_START_PAUSE 0
-#define BIT_MASK_MAC_MBIST_START_PAUSE 0xfff
-#define BIT_MAC_MBIST_START_PAUSE(x) (((x) & BIT_MASK_MAC_MBIST_START_PAUSE) << BIT_SHIFT_MAC_MBIST_START_PAUSE)
-#define BIT_GET_MAC_MBIST_START_PAUSE(x) (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE) & BIT_MASK_MAC_MBIST_START_PAUSE)
+/* 2 REG_MBIST_FAIL (Offset 0x0170) */
+#define BIT_SHIFT_MAC_MBIST_FAIL_DRF 0
+#define BIT_MASK_MAC_MBIST_FAIL_DRF 0x3ffff
+#define BIT_MAC_MBIST_FAIL_DRF(x) \
+ (((x) & BIT_MASK_MAC_MBIST_FAIL_DRF) << BIT_SHIFT_MAC_MBIST_FAIL_DRF)
+#define BITS_MAC_MBIST_FAIL_DRF \
+ (BIT_MASK_MAC_MBIST_FAIL_DRF << BIT_SHIFT_MAC_MBIST_FAIL_DRF)
+#define BIT_CLEAR_MAC_MBIST_FAIL_DRF(x) ((x) & (~BITS_MAC_MBIST_FAIL_DRF))
+#define BIT_GET_MAC_MBIST_FAIL_DRF(x) \
+ (((x) >> BIT_SHIFT_MAC_MBIST_FAIL_DRF) & BIT_MASK_MAC_MBIST_FAIL_DRF)
+#define BIT_SET_MAC_MBIST_FAIL_DRF(x, v) \
+ (BIT_CLEAR_MAC_MBIST_FAIL_DRF(x) | BIT_MAC_MBIST_FAIL_DRF(v))
#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_MBIST_DRF_FAIL (Offset 0x0170) */
+#define BIT_SHIFT_MAC_MBIST_DRF_FAIL 0
+#define BIT_MASK_MAC_MBIST_DRF_FAIL 0x3ffff
+#define BIT_MAC_MBIST_DRF_FAIL(x) \
+ (((x) & BIT_MASK_MAC_MBIST_DRF_FAIL) << BIT_SHIFT_MAC_MBIST_DRF_FAIL)
+#define BITS_MAC_MBIST_DRF_FAIL \
+ (BIT_MASK_MAC_MBIST_DRF_FAIL << BIT_SHIFT_MAC_MBIST_DRF_FAIL)
+#define BIT_CLEAR_MAC_MBIST_DRF_FAIL(x) ((x) & (~BITS_MAC_MBIST_DRF_FAIL))
+#define BIT_GET_MAC_MBIST_DRF_FAIL(x) \
+ (((x) >> BIT_SHIFT_MAC_MBIST_DRF_FAIL) & BIT_MASK_MAC_MBIST_DRF_FAIL)
+#define BIT_SET_MAC_MBIST_DRF_FAIL(x, v) \
+ (BIT_CLEAR_MAC_MBIST_DRF_FAIL(x) | BIT_MAC_MBIST_DRF_FAIL(v))
-/* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_MAC_MBIST_START_PAUSE_V1 0
-#define BIT_MASK_MAC_MBIST_START_PAUSE_V1 0x3ffff
-#define BIT_MAC_MBIST_START_PAUSE_V1(x) (((x) & BIT_MASK_MAC_MBIST_START_PAUSE_V1) << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1)
-#define BIT_GET_MAC_MBIST_START_PAUSE_V1(x) (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_V1) & BIT_MASK_MAC_MBIST_START_PAUSE_V1)
+/* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */
+#define BIT_SHIFT_8051_MBIST_START_PAUSE 26
+#define BIT_MASK_8051_MBIST_START_PAUSE 0x7
+#define BIT_8051_MBIST_START_PAUSE(x) \
+ (((x) & BIT_MASK_8051_MBIST_START_PAUSE) \
+ << BIT_SHIFT_8051_MBIST_START_PAUSE)
+#define BITS_8051_MBIST_START_PAUSE \
+ (BIT_MASK_8051_MBIST_START_PAUSE << BIT_SHIFT_8051_MBIST_START_PAUSE)
+#define BIT_CLEAR_8051_MBIST_START_PAUSE(x) \
+ ((x) & (~BITS_8051_MBIST_START_PAUSE))
+#define BIT_GET_8051_MBIST_START_PAUSE(x) \
+ (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE) & \
+ BIT_MASK_8051_MBIST_START_PAUSE)
+#define BIT_SET_8051_MBIST_START_PAUSE(x, v) \
+ (BIT_CLEAR_8051_MBIST_START_PAUSE(x) | BIT_8051_MBIST_START_PAUSE(v))
#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */
+#define BIT_SHIFT_8051_MBIST_START_PAUSE_V1 26
+#define BIT_MASK_8051_MBIST_START_PAUSE_V1 0x3f
+#define BIT_8051_MBIST_START_PAUSE_V1(x) \
+ (((x) & BIT_MASK_8051_MBIST_START_PAUSE_V1) \
+ << BIT_SHIFT_8051_MBIST_START_PAUSE_V1)
+#define BITS_8051_MBIST_START_PAUSE_V1 \
+ (BIT_MASK_8051_MBIST_START_PAUSE_V1 \
+ << BIT_SHIFT_8051_MBIST_START_PAUSE_V1)
+#define BIT_CLEAR_8051_MBIST_START_PAUSE_V1(x) \
+ ((x) & (~BITS_8051_MBIST_START_PAUSE_V1))
+#define BIT_GET_8051_MBIST_START_PAUSE_V1(x) \
+ (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_V1) & \
+ BIT_MASK_8051_MBIST_START_PAUSE_V1)
+#define BIT_SET_8051_MBIST_START_PAUSE_V1(x, v) \
+ (BIT_CLEAR_8051_MBIST_START_PAUSE_V1(x) | \
+ BIT_8051_MBIST_START_PAUSE_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-/* 2 REG_MBIST_DONE (Offset 0x0178) */
+/* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */
+#define BIT_SHIFT_USB_MBIST_START_PAUSE 24
+#define BIT_MASK_USB_MBIST_START_PAUSE 0x3
+#define BIT_USB_MBIST_START_PAUSE(x) \
+ (((x) & BIT_MASK_USB_MBIST_START_PAUSE) \
+ << BIT_SHIFT_USB_MBIST_START_PAUSE)
+#define BITS_USB_MBIST_START_PAUSE \
+ (BIT_MASK_USB_MBIST_START_PAUSE << BIT_SHIFT_USB_MBIST_START_PAUSE)
+#define BIT_CLEAR_USB_MBIST_START_PAUSE(x) ((x) & (~BITS_USB_MBIST_START_PAUSE))
+#define BIT_GET_USB_MBIST_START_PAUSE(x) \
+ (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE) & \
+ BIT_MASK_USB_MBIST_START_PAUSE)
+#define BIT_SET_USB_MBIST_START_PAUSE(x, v) \
+ (BIT_CLEAR_USB_MBIST_START_PAUSE(x) | BIT_USB_MBIST_START_PAUSE(v))
-#define BIT_SHIFT_8051_MBIST_DONE 26
-#define BIT_MASK_8051_MBIST_DONE 0x7
-#define BIT_8051_MBIST_DONE(x) (((x) & BIT_MASK_8051_MBIST_DONE) << BIT_SHIFT_8051_MBIST_DONE)
-#define BIT_GET_8051_MBIST_DONE(x) (((x) >> BIT_SHIFT_8051_MBIST_DONE) & BIT_MASK_8051_MBIST_DONE)
+#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_USB_MBIST_DONE 24
-#define BIT_MASK_USB_MBIST_DONE 0x3
-#define BIT_USB_MBIST_DONE(x) (((x) & BIT_MASK_USB_MBIST_DONE) << BIT_SHIFT_USB_MBIST_DONE)
-#define BIT_GET_USB_MBIST_DONE(x) (((x) >> BIT_SHIFT_USB_MBIST_DONE) & BIT_MASK_USB_MBIST_DONE)
+/* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */
+#define BIT_SHIFT_USB_MBIST_START_PAUSE_V1 24
+#define BIT_MASK_USB_MBIST_START_PAUSE_V1 0x3
+#define BIT_USB_MBIST_START_PAUSE_V1(x) \
+ (((x) & BIT_MASK_USB_MBIST_START_PAUSE_V1) \
+ << BIT_SHIFT_USB_MBIST_START_PAUSE_V1)
+#define BITS_USB_MBIST_START_PAUSE_V1 \
+ (BIT_MASK_USB_MBIST_START_PAUSE_V1 \
+ << BIT_SHIFT_USB_MBIST_START_PAUSE_V1)
+#define BIT_CLEAR_USB_MBIST_START_PAUSE_V1(x) \
+ ((x) & (~BITS_USB_MBIST_START_PAUSE_V1))
+#define BIT_GET_USB_MBIST_START_PAUSE_V1(x) \
+ (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_V1) & \
+ BIT_MASK_USB_MBIST_START_PAUSE_V1)
+#define BIT_SET_USB_MBIST_START_PAUSE_V1(x, v) \
+ (BIT_CLEAR_USB_MBIST_START_PAUSE_V1(x) | \
+ BIT_USB_MBIST_START_PAUSE_V1(v))
+
+#define BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1 18
+#define BIT_MASK_PCIE_MBIST_START_PAUSE_V1 0x3f
+#define BIT_PCIE_MBIST_START_PAUSE_V1(x) \
+ (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_V1) \
+ << BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1)
+#define BITS_PCIE_MBIST_START_PAUSE_V1 \
+ (BIT_MASK_PCIE_MBIST_START_PAUSE_V1 \
+ << BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1)
+#define BIT_CLEAR_PCIE_MBIST_START_PAUSE_V1(x) \
+ ((x) & (~BITS_PCIE_MBIST_START_PAUSE_V1))
+#define BIT_GET_PCIE_MBIST_START_PAUSE_V1(x) \
+ (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1) & \
+ BIT_MASK_PCIE_MBIST_START_PAUSE_V1)
+#define BIT_SET_PCIE_MBIST_START_PAUSE_V1(x, v) \
+ (BIT_CLEAR_PCIE_MBIST_START_PAUSE_V1(x) | \
+ BIT_PCIE_MBIST_START_PAUSE_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_PCIE_MBIST_DONE 16
-#define BIT_MASK_PCIE_MBIST_DONE 0x3f
-#define BIT_PCIE_MBIST_DONE(x) (((x) & BIT_MASK_PCIE_MBIST_DONE) << BIT_SHIFT_PCIE_MBIST_DONE)
-#define BIT_GET_PCIE_MBIST_DONE(x) (((x) >> BIT_SHIFT_PCIE_MBIST_DONE) & BIT_MASK_PCIE_MBIST_DONE)
+/* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */
+#define BIT_SHIFT_PCIE_MBIST_START_PAUSE 16
+#define BIT_MASK_PCIE_MBIST_START_PAUSE 0x3f
+#define BIT_PCIE_MBIST_START_PAUSE(x) \
+ (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE) \
+ << BIT_SHIFT_PCIE_MBIST_START_PAUSE)
+#define BITS_PCIE_MBIST_START_PAUSE \
+ (BIT_MASK_PCIE_MBIST_START_PAUSE << BIT_SHIFT_PCIE_MBIST_START_PAUSE)
+#define BIT_CLEAR_PCIE_MBIST_START_PAUSE(x) \
+ ((x) & (~BITS_PCIE_MBIST_START_PAUSE))
+#define BIT_GET_PCIE_MBIST_START_PAUSE(x) \
+ (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE) & \
+ BIT_MASK_PCIE_MBIST_START_PAUSE)
+#define BIT_SET_PCIE_MBIST_START_PAUSE(x, v) \
+ (BIT_CLEAR_PCIE_MBIST_START_PAUSE(x) | BIT_PCIE_MBIST_START_PAUSE(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */
+#define BIT_SHIFT_MAC_MBIST_START_PAUSE 0
+#define BIT_MASK_MAC_MBIST_START_PAUSE 0xfff
+#define BIT_MAC_MBIST_START_PAUSE(x) \
+ (((x) & BIT_MASK_MAC_MBIST_START_PAUSE) \
+ << BIT_SHIFT_MAC_MBIST_START_PAUSE)
+#define BITS_MAC_MBIST_START_PAUSE \
+ (BIT_MASK_MAC_MBIST_START_PAUSE << BIT_SHIFT_MAC_MBIST_START_PAUSE)
+#define BIT_CLEAR_MAC_MBIST_START_PAUSE(x) ((x) & (~BITS_MAC_MBIST_START_PAUSE))
+#define BIT_GET_MAC_MBIST_START_PAUSE(x) \
+ (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE) & \
+ BIT_MASK_MAC_MBIST_START_PAUSE)
+#define BIT_SET_MAC_MBIST_START_PAUSE(x, v) \
+ (BIT_CLEAR_MAC_MBIST_START_PAUSE(x) | BIT_MAC_MBIST_START_PAUSE(v))
-/* 2 REG_MBIST_DONE (Offset 0x0178) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_MAC_MBIST_DONE 0
-#define BIT_MASK_MAC_MBIST_DONE 0xfff
-#define BIT_MAC_MBIST_DONE(x) (((x) & BIT_MASK_MAC_MBIST_DONE) << BIT_SHIFT_MAC_MBIST_DONE)
-#define BIT_GET_MAC_MBIST_DONE(x) (((x) >> BIT_SHIFT_MAC_MBIST_DONE) & BIT_MASK_MAC_MBIST_DONE)
+/* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */
+#define BIT_SHIFT_MAC_MBIST_START_PAUSE_V1 0
+#define BIT_MASK_MAC_MBIST_START_PAUSE_V1 0x3ffff
+#define BIT_MAC_MBIST_START_PAUSE_V1(x) \
+ (((x) & BIT_MASK_MAC_MBIST_START_PAUSE_V1) \
+ << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1)
+#define BITS_MAC_MBIST_START_PAUSE_V1 \
+ (BIT_MASK_MAC_MBIST_START_PAUSE_V1 \
+ << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1)
+#define BIT_CLEAR_MAC_MBIST_START_PAUSE_V1(x) \
+ ((x) & (~BITS_MAC_MBIST_START_PAUSE_V1))
+#define BIT_GET_MAC_MBIST_START_PAUSE_V1(x) \
+ (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_V1) & \
+ BIT_MASK_MAC_MBIST_START_PAUSE_V1)
+#define BIT_SET_MAC_MBIST_START_PAUSE_V1(x, v) \
+ (BIT_CLEAR_MAC_MBIST_START_PAUSE_V1(x) | \
+ BIT_MAC_MBIST_START_PAUSE_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_MBIST_DONE (Offset 0x0178) */
+#define BIT_SHIFT_8051_MBIST_DONE 26
+#define BIT_MASK_8051_MBIST_DONE 0x7
+#define BIT_8051_MBIST_DONE(x) \
+ (((x) & BIT_MASK_8051_MBIST_DONE) << BIT_SHIFT_8051_MBIST_DONE)
+#define BITS_8051_MBIST_DONE \
+ (BIT_MASK_8051_MBIST_DONE << BIT_SHIFT_8051_MBIST_DONE)
+#define BIT_CLEAR_8051_MBIST_DONE(x) ((x) & (~BITS_8051_MBIST_DONE))
+#define BIT_GET_8051_MBIST_DONE(x) \
+ (((x) >> BIT_SHIFT_8051_MBIST_DONE) & BIT_MASK_8051_MBIST_DONE)
+#define BIT_SET_8051_MBIST_DONE(x, v) \
+ (BIT_CLEAR_8051_MBIST_DONE(x) | BIT_8051_MBIST_DONE(v))
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_MBIST_DONE (Offset 0x0178) */
+#define BIT_SHIFT_8051_MBIST_DONE_V1 26
+#define BIT_MASK_8051_MBIST_DONE_V1 0x3f
+#define BIT_8051_MBIST_DONE_V1(x) \
+ (((x) & BIT_MASK_8051_MBIST_DONE_V1) << BIT_SHIFT_8051_MBIST_DONE_V1)
+#define BITS_8051_MBIST_DONE_V1 \
+ (BIT_MASK_8051_MBIST_DONE_V1 << BIT_SHIFT_8051_MBIST_DONE_V1)
+#define BIT_CLEAR_8051_MBIST_DONE_V1(x) ((x) & (~BITS_8051_MBIST_DONE_V1))
+#define BIT_GET_8051_MBIST_DONE_V1(x) \
+ (((x) >> BIT_SHIFT_8051_MBIST_DONE_V1) & BIT_MASK_8051_MBIST_DONE_V1)
+#define BIT_SET_8051_MBIST_DONE_V1(x, v) \
+ (BIT_CLEAR_8051_MBIST_DONE_V1(x) | BIT_8051_MBIST_DONE_V1(v))
-#define BIT_SHIFT_MAC_MBIST_DONE_V1 0
-#define BIT_MASK_MAC_MBIST_DONE_V1 0x3ffff
-#define BIT_MAC_MBIST_DONE_V1(x) (((x) & BIT_MASK_MAC_MBIST_DONE_V1) << BIT_SHIFT_MAC_MBIST_DONE_V1)
-#define BIT_GET_MAC_MBIST_DONE_V1(x) (((x) >> BIT_SHIFT_MAC_MBIST_DONE_V1) & BIT_MASK_MAC_MBIST_DONE_V1)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_MBIST_DONE (Offset 0x0178) */
+#define BIT_SHIFT_USB_MBIST_DONE 24
+#define BIT_MASK_USB_MBIST_DONE 0x3
+#define BIT_USB_MBIST_DONE(x) \
+ (((x) & BIT_MASK_USB_MBIST_DONE) << BIT_SHIFT_USB_MBIST_DONE)
+#define BITS_USB_MBIST_DONE \
+ (BIT_MASK_USB_MBIST_DONE << BIT_SHIFT_USB_MBIST_DONE)
+#define BIT_CLEAR_USB_MBIST_DONE(x) ((x) & (~BITS_USB_MBIST_DONE))
+#define BIT_GET_USB_MBIST_DONE(x) \
+ (((x) >> BIT_SHIFT_USB_MBIST_DONE) & BIT_MASK_USB_MBIST_DONE)
+#define BIT_SET_USB_MBIST_DONE(x, v) \
+ (BIT_CLEAR_USB_MBIST_DONE(x) | BIT_USB_MBIST_DONE(v))
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_MBIST_ROM_CRC_DATA (Offset 0x017C) */
+/* 2 REG_MBIST_DONE (Offset 0x0178) */
+#define BIT_SHIFT_USB_MBIST_DONE_V1 24
+#define BIT_MASK_USB_MBIST_DONE_V1 0x3
+#define BIT_USB_MBIST_DONE_V1(x) \
+ (((x) & BIT_MASK_USB_MBIST_DONE_V1) << BIT_SHIFT_USB_MBIST_DONE_V1)
+#define BITS_USB_MBIST_DONE_V1 \
+ (BIT_MASK_USB_MBIST_DONE_V1 << BIT_SHIFT_USB_MBIST_DONE_V1)
+#define BIT_CLEAR_USB_MBIST_DONE_V1(x) ((x) & (~BITS_USB_MBIST_DONE_V1))
+#define BIT_GET_USB_MBIST_DONE_V1(x) \
+ (((x) >> BIT_SHIFT_USB_MBIST_DONE_V1) & BIT_MASK_USB_MBIST_DONE_V1)
+#define BIT_SET_USB_MBIST_DONE_V1(x, v) \
+ (BIT_CLEAR_USB_MBIST_DONE_V1(x) | BIT_USB_MBIST_DONE_V1(v))
+
+#define BIT_SHIFT_PCIE_MBIST_DONE_V1 18
+#define BIT_MASK_PCIE_MBIST_DONE_V1 0x3f
+#define BIT_PCIE_MBIST_DONE_V1(x) \
+ (((x) & BIT_MASK_PCIE_MBIST_DONE_V1) << BIT_SHIFT_PCIE_MBIST_DONE_V1)
+#define BITS_PCIE_MBIST_DONE_V1 \
+ (BIT_MASK_PCIE_MBIST_DONE_V1 << BIT_SHIFT_PCIE_MBIST_DONE_V1)
+#define BIT_CLEAR_PCIE_MBIST_DONE_V1(x) ((x) & (~BITS_PCIE_MBIST_DONE_V1))
+#define BIT_GET_PCIE_MBIST_DONE_V1(x) \
+ (((x) >> BIT_SHIFT_PCIE_MBIST_DONE_V1) & BIT_MASK_PCIE_MBIST_DONE_V1)
+#define BIT_SET_PCIE_MBIST_DONE_V1(x, v) \
+ (BIT_CLEAR_PCIE_MBIST_DONE_V1(x) | BIT_PCIE_MBIST_DONE_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_MBIST_ROM_CRC_DATA 0
-#define BIT_MASK_MBIST_ROM_CRC_DATA 0xffffffffL
-#define BIT_MBIST_ROM_CRC_DATA(x) (((x) & BIT_MASK_MBIST_ROM_CRC_DATA) << BIT_SHIFT_MBIST_ROM_CRC_DATA)
-#define BIT_GET_MBIST_ROM_CRC_DATA(x) (((x) >> BIT_SHIFT_MBIST_ROM_CRC_DATA) & BIT_MASK_MBIST_ROM_CRC_DATA)
+/* 2 REG_MBIST_DONE (Offset 0x0178) */
+#define BIT_SHIFT_PCIE_MBIST_DONE 16
+#define BIT_MASK_PCIE_MBIST_DONE 0x3f
+#define BIT_PCIE_MBIST_DONE(x) \
+ (((x) & BIT_MASK_PCIE_MBIST_DONE) << BIT_SHIFT_PCIE_MBIST_DONE)
+#define BITS_PCIE_MBIST_DONE \
+ (BIT_MASK_PCIE_MBIST_DONE << BIT_SHIFT_PCIE_MBIST_DONE)
+#define BIT_CLEAR_PCIE_MBIST_DONE(x) ((x) & (~BITS_PCIE_MBIST_DONE))
+#define BIT_GET_PCIE_MBIST_DONE(x) \
+ (((x) >> BIT_SHIFT_PCIE_MBIST_DONE) & BIT_MASK_PCIE_MBIST_DONE)
+#define BIT_SET_PCIE_MBIST_DONE(x, v) \
+ (BIT_CLEAR_PCIE_MBIST_DONE(x) | BIT_PCIE_MBIST_DONE(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_MBIST_DONE (Offset 0x0178) */
+#define BIT_SHIFT_MAC_MBIST_DONE 0
+#define BIT_MASK_MAC_MBIST_DONE 0xfff
+#define BIT_MAC_MBIST_DONE(x) \
+ (((x) & BIT_MASK_MAC_MBIST_DONE) << BIT_SHIFT_MAC_MBIST_DONE)
+#define BITS_MAC_MBIST_DONE \
+ (BIT_MASK_MAC_MBIST_DONE << BIT_SHIFT_MAC_MBIST_DONE)
+#define BIT_CLEAR_MAC_MBIST_DONE(x) ((x) & (~BITS_MAC_MBIST_DONE))
+#define BIT_GET_MAC_MBIST_DONE(x) \
+ (((x) >> BIT_SHIFT_MAC_MBIST_DONE) & BIT_MASK_MAC_MBIST_DONE)
+#define BIT_SET_MAC_MBIST_DONE(x, v) \
+ (BIT_CLEAR_MAC_MBIST_DONE(x) | BIT_MAC_MBIST_DONE(v))
-/* 2 REG_MBIST_FAIL_NRML (Offset 0x017C) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_MBIST_FAIL_NRML_V1 0
-#define BIT_MASK_MBIST_FAIL_NRML_V1 0x3ffff
-#define BIT_MBIST_FAIL_NRML_V1(x) (((x) & BIT_MASK_MBIST_FAIL_NRML_V1) << BIT_SHIFT_MBIST_FAIL_NRML_V1)
-#define BIT_GET_MBIST_FAIL_NRML_V1(x) (((x) >> BIT_SHIFT_MBIST_FAIL_NRML_V1) & BIT_MASK_MBIST_FAIL_NRML_V1)
+/* 2 REG_MBIST_DONE (Offset 0x0178) */
+#define BIT_SHIFT_MAC_MBIST_DONE_V1 0
+#define BIT_MASK_MAC_MBIST_DONE_V1 0x3ffff
+#define BIT_MAC_MBIST_DONE_V1(x) \
+ (((x) & BIT_MASK_MAC_MBIST_DONE_V1) << BIT_SHIFT_MAC_MBIST_DONE_V1)
+#define BITS_MAC_MBIST_DONE_V1 \
+ (BIT_MASK_MAC_MBIST_DONE_V1 << BIT_SHIFT_MAC_MBIST_DONE_V1)
+#define BIT_CLEAR_MAC_MBIST_DONE_V1(x) ((x) & (~BITS_MAC_MBIST_DONE_V1))
+#define BIT_GET_MAC_MBIST_DONE_V1(x) \
+ (((x) >> BIT_SHIFT_MAC_MBIST_DONE_V1) & BIT_MASK_MAC_MBIST_DONE_V1)
+#define BIT_SET_MAC_MBIST_DONE_V1(x, v) \
+ (BIT_CLEAR_MAC_MBIST_DONE_V1(x) | BIT_MAC_MBIST_DONE_V1(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_MBIST_ROM_CRC_DATA (Offset 0x017C) */
+#define BIT_SHIFT_MBIST_ROM_CRC_DATA 0
+#define BIT_MASK_MBIST_ROM_CRC_DATA 0xffffffffL
+#define BIT_MBIST_ROM_CRC_DATA(x) \
+ (((x) & BIT_MASK_MBIST_ROM_CRC_DATA) << BIT_SHIFT_MBIST_ROM_CRC_DATA)
+#define BITS_MBIST_ROM_CRC_DATA \
+ (BIT_MASK_MBIST_ROM_CRC_DATA << BIT_SHIFT_MBIST_ROM_CRC_DATA)
+#define BIT_CLEAR_MBIST_ROM_CRC_DATA(x) ((x) & (~BITS_MBIST_ROM_CRC_DATA))
+#define BIT_GET_MBIST_ROM_CRC_DATA(x) \
+ (((x) >> BIT_SHIFT_MBIST_ROM_CRC_DATA) & BIT_MASK_MBIST_ROM_CRC_DATA)
+#define BIT_SET_MBIST_ROM_CRC_DATA(x, v) \
+ (BIT_CLEAR_MBIST_ROM_CRC_DATA(x) | BIT_MBIST_ROM_CRC_DATA(v))
-/* 2 REG_MBIST_FAIL_NRML (Offset 0x017C) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_MBIST_FAIL_NRML 0
-#define BIT_MASK_MBIST_FAIL_NRML 0xffffffffL
-#define BIT_MBIST_FAIL_NRML(x) (((x) & BIT_MASK_MBIST_FAIL_NRML) << BIT_SHIFT_MBIST_FAIL_NRML)
-#define BIT_GET_MBIST_FAIL_NRML(x) (((x) >> BIT_SHIFT_MBIST_FAIL_NRML) & BIT_MASK_MBIST_FAIL_NRML)
+/* 2 REG_MBIST_FAIL_NRML (Offset 0x017C) */
+#define BIT_SHIFT_MBIST_FAIL_NRML_V1 0
+#define BIT_MASK_MBIST_FAIL_NRML_V1 0x3ffff
+#define BIT_MBIST_FAIL_NRML_V1(x) \
+ (((x) & BIT_MASK_MBIST_FAIL_NRML_V1) << BIT_SHIFT_MBIST_FAIL_NRML_V1)
+#define BITS_MBIST_FAIL_NRML_V1 \
+ (BIT_MASK_MBIST_FAIL_NRML_V1 << BIT_SHIFT_MBIST_FAIL_NRML_V1)
+#define BIT_CLEAR_MBIST_FAIL_NRML_V1(x) ((x) & (~BITS_MBIST_FAIL_NRML_V1))
+#define BIT_GET_MBIST_FAIL_NRML_V1(x) \
+ (((x) >> BIT_SHIFT_MBIST_FAIL_NRML_V1) & BIT_MASK_MBIST_FAIL_NRML_V1)
+#define BIT_SET_MBIST_FAIL_NRML_V1(x, v) \
+ (BIT_CLEAR_MBIST_FAIL_NRML_V1(x) | BIT_MBIST_FAIL_NRML_V1(v))
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_MBIST_FAIL_NRML (Offset 0x017C) */
+#define BIT_SHIFT_MBIST_FAIL_NRML 0
+#define BIT_MASK_MBIST_FAIL_NRML 0xffffffffL
+#define BIT_MBIST_FAIL_NRML(x) \
+ (((x) & BIT_MASK_MBIST_FAIL_NRML) << BIT_SHIFT_MBIST_FAIL_NRML)
+#define BITS_MBIST_FAIL_NRML \
+ (BIT_MASK_MBIST_FAIL_NRML << BIT_SHIFT_MBIST_FAIL_NRML)
+#define BIT_CLEAR_MBIST_FAIL_NRML(x) ((x) & (~BITS_MBIST_FAIL_NRML))
+#define BIT_GET_MBIST_FAIL_NRML(x) \
+ (((x) >> BIT_SHIFT_MBIST_FAIL_NRML) & BIT_MASK_MBIST_FAIL_NRML)
+#define BIT_SET_MBIST_FAIL_NRML(x, v) \
+ (BIT_CLEAR_MBIST_FAIL_NRML(x) | BIT_MBIST_FAIL_NRML(v))
+
+#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD 0
+#define BIT_MASK_R_WMAC_IPV6_MYIPAD 0xffffffffffffffffffffffffffffffffL
+#define BIT_R_WMAC_IPV6_MYIPAD(x) \
+ (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD)
+#define BITS_R_WMAC_IPV6_MYIPAD \
+ (BIT_MASK_R_WMAC_IPV6_MYIPAD << BIT_SHIFT_R_WMAC_IPV6_MYIPAD)
+#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD(x) ((x) & (~BITS_R_WMAC_IPV6_MYIPAD))
+#define BIT_GET_R_WMAC_IPV6_MYIPAD(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD) & BIT_MASK_R_WMAC_IPV6_MYIPAD)
+#define BIT_SET_R_WMAC_IPV6_MYIPAD(x, v) \
+ (BIT_CLEAR_R_WMAC_IPV6_MYIPAD(x) | BIT_R_WMAC_IPV6_MYIPAD(v))
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MBIST_READ_BIST_RPT (Offset 0x017C) */
+
+#define BIT_SHIFT_MBIST_READ_BIST_RPT 0
+#define BIT_MASK_MBIST_READ_BIST_RPT 0xffffffffL
+#define BIT_MBIST_READ_BIST_RPT(x) \
+ (((x) & BIT_MASK_MBIST_READ_BIST_RPT) << BIT_SHIFT_MBIST_READ_BIST_RPT)
+#define BITS_MBIST_READ_BIST_RPT \
+ (BIT_MASK_MBIST_READ_BIST_RPT << BIT_SHIFT_MBIST_READ_BIST_RPT)
+#define BIT_CLEAR_MBIST_READ_BIST_RPT(x) ((x) & (~BITS_MBIST_READ_BIST_RPT))
+#define BIT_GET_MBIST_READ_BIST_RPT(x) \
+ (((x) >> BIT_SHIFT_MBIST_READ_BIST_RPT) & BIT_MASK_MBIST_READ_BIST_RPT)
+#define BIT_SET_MBIST_READ_BIST_RPT(x, v) \
+ (BIT_CLEAR_MBIST_READ_BIST_RPT(x) | BIT_MBIST_READ_BIST_RPT(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_AES_DECRPT_DATA (Offset 0x0180) */
+#define BIT_SHIFT_IPS_CFG_ADDR 0
+#define BIT_MASK_IPS_CFG_ADDR 0xff
+#define BIT_IPS_CFG_ADDR(x) \
+ (((x) & BIT_MASK_IPS_CFG_ADDR) << BIT_SHIFT_IPS_CFG_ADDR)
+#define BITS_IPS_CFG_ADDR (BIT_MASK_IPS_CFG_ADDR << BIT_SHIFT_IPS_CFG_ADDR)
+#define BIT_CLEAR_IPS_CFG_ADDR(x) ((x) & (~BITS_IPS_CFG_ADDR))
+#define BIT_GET_IPS_CFG_ADDR(x) \
+ (((x) >> BIT_SHIFT_IPS_CFG_ADDR) & BIT_MASK_IPS_CFG_ADDR)
+#define BIT_SET_IPS_CFG_ADDR(x, v) \
+ (BIT_CLEAR_IPS_CFG_ADDR(x) | BIT_IPS_CFG_ADDR(v))
-#define BIT_SHIFT_IPS_CFG_ADDR 0
-#define BIT_MASK_IPS_CFG_ADDR 0xff
-#define BIT_IPS_CFG_ADDR(x) (((x) & BIT_MASK_IPS_CFG_ADDR) << BIT_SHIFT_IPS_CFG_ADDR)
-#define BIT_GET_IPS_CFG_ADDR(x) (((x) >> BIT_SHIFT_IPS_CFG_ADDR) & BIT_MASK_IPS_CFG_ADDR)
+/* 2 REG_AES_DECRPT_CFG (Offset 0x0184) */
+#define BIT_SHIFT_IPS_CFG_DATA 0
+#define BIT_MASK_IPS_CFG_DATA 0xffffffffL
+#define BIT_IPS_CFG_DATA(x) \
+ (((x) & BIT_MASK_IPS_CFG_DATA) << BIT_SHIFT_IPS_CFG_DATA)
+#define BITS_IPS_CFG_DATA (BIT_MASK_IPS_CFG_DATA << BIT_SHIFT_IPS_CFG_DATA)
+#define BIT_CLEAR_IPS_CFG_DATA(x) ((x) & (~BITS_IPS_CFG_DATA))
+#define BIT_GET_IPS_CFG_DATA(x) \
+ (((x) >> BIT_SHIFT_IPS_CFG_DATA) & BIT_MASK_IPS_CFG_DATA)
+#define BIT_SET_IPS_CFG_DATA(x, v) \
+ (BIT_CLEAR_IPS_CFG_DATA(x) | BIT_IPS_CFG_DATA(v))
-/* 2 REG_AES_DECRPT_CFG (Offset 0x0184) */
+#endif
+#if (HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_IPS_CFG_DATA 0
-#define BIT_MASK_IPS_CFG_DATA 0xffffffffL
-#define BIT_IPS_CFG_DATA(x) (((x) & BIT_MASK_IPS_CFG_DATA) << BIT_SHIFT_IPS_CFG_DATA)
-#define BIT_GET_IPS_CFG_DATA(x) (((x) >> BIT_SHIFT_IPS_CFG_DATA) & BIT_MASK_IPS_CFG_DATA)
+/* 2 REG_HIOE_CTRL (Offset 0x0188) */
+#define BIT_HIOE_CFG_FILE_LOC_SEL BIT(31)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_HIOE_CTRL (Offset 0x0188) */
+#define BIT_HIOE_WRITE_REQ BIT(30)
+#define BIT_HIOE_READ_REQ BIT(29)
+#define BIT_INST_FORMAT_ERR BIT(25)
+#define BIT_OP_TIMEOUT_ERR BIT(24)
-/* 2 REG_MACCLKFRQ (Offset 0x018C) */
+#define BIT_SHIFT_HIOE_OP_TIMEOUT 16
+#define BIT_MASK_HIOE_OP_TIMEOUT 0xff
+#define BIT_HIOE_OP_TIMEOUT(x) \
+ (((x) & BIT_MASK_HIOE_OP_TIMEOUT) << BIT_SHIFT_HIOE_OP_TIMEOUT)
+#define BITS_HIOE_OP_TIMEOUT \
+ (BIT_MASK_HIOE_OP_TIMEOUT << BIT_SHIFT_HIOE_OP_TIMEOUT)
+#define BIT_CLEAR_HIOE_OP_TIMEOUT(x) ((x) & (~BITS_HIOE_OP_TIMEOUT))
+#define BIT_GET_HIOE_OP_TIMEOUT(x) \
+ (((x) >> BIT_SHIFT_HIOE_OP_TIMEOUT) & BIT_MASK_HIOE_OP_TIMEOUT)
+#define BIT_SET_HIOE_OP_TIMEOUT(x, v) \
+ (BIT_CLEAR_HIOE_OP_TIMEOUT(x) | BIT_HIOE_OP_TIMEOUT(v))
+#define BIT_SHIFT_BITDATA_CHECKSUM 0
+#define BIT_MASK_BITDATA_CHECKSUM 0xffff
+#define BIT_BITDATA_CHECKSUM(x) \
+ (((x) & BIT_MASK_BITDATA_CHECKSUM) << BIT_SHIFT_BITDATA_CHECKSUM)
+#define BITS_BITDATA_CHECKSUM \
+ (BIT_MASK_BITDATA_CHECKSUM << BIT_SHIFT_BITDATA_CHECKSUM)
+#define BIT_CLEAR_BITDATA_CHECKSUM(x) ((x) & (~BITS_BITDATA_CHECKSUM))
+#define BIT_GET_BITDATA_CHECKSUM(x) \
+ (((x) >> BIT_SHIFT_BITDATA_CHECKSUM) & BIT_MASK_BITDATA_CHECKSUM)
+#define BIT_SET_BITDATA_CHECKSUM(x, v) \
+ (BIT_CLEAR_BITDATA_CHECKSUM(x) | BIT_BITDATA_CHECKSUM(v))
-#define BIT_SHIFT_MACCLK_FREQ_LOW32 0
-#define BIT_MASK_MACCLK_FREQ_LOW32 0xffffffffL
-#define BIT_MACCLK_FREQ_LOW32(x) (((x) & BIT_MASK_MACCLK_FREQ_LOW32) << BIT_SHIFT_MACCLK_FREQ_LOW32)
-#define BIT_GET_MACCLK_FREQ_LOW32(x) (((x) >> BIT_SHIFT_MACCLK_FREQ_LOW32) & BIT_MASK_MACCLK_FREQ_LOW32)
+/* 2 REG_HIOE_CFG_FILE (Offset 0x018C) */
+#define BIT_SHIFT_TXBF_END_ADDR 16
+#define BIT_MASK_TXBF_END_ADDR 0xffff
+#define BIT_TXBF_END_ADDR(x) \
+ (((x) & BIT_MASK_TXBF_END_ADDR) << BIT_SHIFT_TXBF_END_ADDR)
+#define BITS_TXBF_END_ADDR (BIT_MASK_TXBF_END_ADDR << BIT_SHIFT_TXBF_END_ADDR)
+#define BIT_CLEAR_TXBF_END_ADDR(x) ((x) & (~BITS_TXBF_END_ADDR))
+#define BIT_GET_TXBF_END_ADDR(x) \
+ (((x) >> BIT_SHIFT_TXBF_END_ADDR) & BIT_MASK_TXBF_END_ADDR)
+#define BIT_SET_TXBF_END_ADDR(x, v) \
+ (BIT_CLEAR_TXBF_END_ADDR(x) | BIT_TXBF_END_ADDR(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_MACCLKFRQ (Offset 0x018C) */
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#define BIT_SHIFT_MACCLK_FREQ_LOW32 0
+#define BIT_MASK_MACCLK_FREQ_LOW32 0xffffffffL
+#define BIT_MACCLK_FREQ_LOW32(x) \
+ (((x) & BIT_MASK_MACCLK_FREQ_LOW32) << BIT_SHIFT_MACCLK_FREQ_LOW32)
+#define BITS_MACCLK_FREQ_LOW32 \
+ (BIT_MASK_MACCLK_FREQ_LOW32 << BIT_SHIFT_MACCLK_FREQ_LOW32)
+#define BIT_CLEAR_MACCLK_FREQ_LOW32(x) ((x) & (~BITS_MACCLK_FREQ_LOW32))
+#define BIT_GET_MACCLK_FREQ_LOW32(x) \
+ (((x) >> BIT_SHIFT_MACCLK_FREQ_LOW32) & BIT_MASK_MACCLK_FREQ_LOW32)
+#define BIT_SET_MACCLK_FREQ_LOW32(x, v) \
+ (BIT_CLEAR_MACCLK_FREQ_LOW32(x) | BIT_MACCLK_FREQ_LOW32(v))
+#endif
-/* 2 REG_TMETER (Offset 0x0190) */
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_TEMP_VALID BIT(31)
+/* 2 REG_HIOE_CFG_FILE (Offset 0x018C) */
-#define BIT_SHIFT_TEMP_VALUE 24
-#define BIT_MASK_TEMP_VALUE 0x3f
-#define BIT_TEMP_VALUE(x) (((x) & BIT_MASK_TEMP_VALUE) << BIT_SHIFT_TEMP_VALUE)
-#define BIT_GET_TEMP_VALUE(x) (((x) >> BIT_SHIFT_TEMP_VALUE) & BIT_MASK_TEMP_VALUE)
+#define BIT_SHIFT_TXBF_STR_ADDR 0
+#define BIT_MASK_TXBF_STR_ADDR 0xffff
+#define BIT_TXBF_STR_ADDR(x) \
+ (((x) & BIT_MASK_TXBF_STR_ADDR) << BIT_SHIFT_TXBF_STR_ADDR)
+#define BITS_TXBF_STR_ADDR (BIT_MASK_TXBF_STR_ADDR << BIT_SHIFT_TXBF_STR_ADDR)
+#define BIT_CLEAR_TXBF_STR_ADDR(x) ((x) & (~BITS_TXBF_STR_ADDR))
+#define BIT_GET_TXBF_STR_ADDR(x) \
+ (((x) >> BIT_SHIFT_TXBF_STR_ADDR) & BIT_MASK_TXBF_STR_ADDR)
+#define BIT_SET_TXBF_STR_ADDR(x, v) \
+ (BIT_CLEAR_TXBF_STR_ADDR(x) | BIT_TXBF_STR_ADDR(v))
+#endif
-#define BIT_SHIFT_REG_TMETER_TIMER 8
-#define BIT_MASK_REG_TMETER_TIMER 0xfff
-#define BIT_REG_TMETER_TIMER(x) (((x) & BIT_MASK_REG_TMETER_TIMER) << BIT_SHIFT_REG_TMETER_TIMER)
-#define BIT_GET_REG_TMETER_TIMER(x) (((x) >> BIT_SHIFT_REG_TMETER_TIMER) & BIT_MASK_REG_TMETER_TIMER)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_TMETER (Offset 0x0190) */
-#define BIT_SHIFT_REG_TEMP_DELTA 2
-#define BIT_MASK_REG_TEMP_DELTA 0x3f
-#define BIT_REG_TEMP_DELTA(x) (((x) & BIT_MASK_REG_TEMP_DELTA) << BIT_SHIFT_REG_TEMP_DELTA)
-#define BIT_GET_REG_TEMP_DELTA(x) (((x) >> BIT_SHIFT_REG_TEMP_DELTA) & BIT_MASK_REG_TEMP_DELTA)
+#define BIT_TEMP_VALID BIT(31)
-#define BIT_REG_TMETER_EN BIT(0)
+#define BIT_SHIFT_TEMP_VALUE 24
+#define BIT_MASK_TEMP_VALUE 0x3f
+#define BIT_TEMP_VALUE(x) (((x) & BIT_MASK_TEMP_VALUE) << BIT_SHIFT_TEMP_VALUE)
+#define BITS_TEMP_VALUE (BIT_MASK_TEMP_VALUE << BIT_SHIFT_TEMP_VALUE)
+#define BIT_CLEAR_TEMP_VALUE(x) ((x) & (~BITS_TEMP_VALUE))
+#define BIT_GET_TEMP_VALUE(x) \
+ (((x) >> BIT_SHIFT_TEMP_VALUE) & BIT_MASK_TEMP_VALUE)
+#define BIT_SET_TEMP_VALUE(x, v) (BIT_CLEAR_TEMP_VALUE(x) | BIT_TEMP_VALUE(v))
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_TMETER (Offset 0x0190) */
+
+#define BIT_SHIFT_NCO_OUTCLK_FREQ 12
+#define BIT_MASK_NCO_OUTCLK_FREQ 0xfffff
+#define BIT_NCO_OUTCLK_FREQ(x) \
+ (((x) & BIT_MASK_NCO_OUTCLK_FREQ) << BIT_SHIFT_NCO_OUTCLK_FREQ)
+#define BITS_NCO_OUTCLK_FREQ \
+ (BIT_MASK_NCO_OUTCLK_FREQ << BIT_SHIFT_NCO_OUTCLK_FREQ)
+#define BIT_CLEAR_NCO_OUTCLK_FREQ(x) ((x) & (~BITS_NCO_OUTCLK_FREQ))
+#define BIT_GET_NCO_OUTCLK_FREQ(x) \
+ (((x) >> BIT_SHIFT_NCO_OUTCLK_FREQ) & BIT_MASK_NCO_OUTCLK_FREQ)
+#define BIT_SET_NCO_OUTCLK_FREQ(x, v) \
+ (BIT_CLEAR_NCO_OUTCLK_FREQ(x) | BIT_NCO_OUTCLK_FREQ(v))
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_TMETER (Offset 0x0190) */
+#define BIT_SHIFT_REG_TMETER_TIMER 8
+#define BIT_MASK_REG_TMETER_TIMER 0xfff
+#define BIT_REG_TMETER_TIMER(x) \
+ (((x) & BIT_MASK_REG_TMETER_TIMER) << BIT_SHIFT_REG_TMETER_TIMER)
+#define BITS_REG_TMETER_TIMER \
+ (BIT_MASK_REG_TMETER_TIMER << BIT_SHIFT_REG_TMETER_TIMER)
+#define BIT_CLEAR_REG_TMETER_TIMER(x) ((x) & (~BITS_REG_TMETER_TIMER))
+#define BIT_GET_REG_TMETER_TIMER(x) \
+ (((x) >> BIT_SHIFT_REG_TMETER_TIMER) & BIT_MASK_REG_TMETER_TIMER)
+#define BIT_SET_REG_TMETER_TIMER(x, v) \
+ (BIT_CLEAR_REG_TMETER_TIMER(x) | BIT_REG_TMETER_TIMER(v))
-#define BIT_SHIFT_MACCLK_FREQ_HIGH10 0
-#define BIT_MASK_MACCLK_FREQ_HIGH10 0x3ff
-#define BIT_MACCLK_FREQ_HIGH10(x) (((x) & BIT_MASK_MACCLK_FREQ_HIGH10) << BIT_SHIFT_MACCLK_FREQ_HIGH10)
-#define BIT_GET_MACCLK_FREQ_HIGH10(x) (((x) >> BIT_SHIFT_MACCLK_FREQ_HIGH10) & BIT_MASK_MACCLK_FREQ_HIGH10)
+#define BIT_SHIFT_REG_TEMP_DELTA 2
+#define BIT_MASK_REG_TEMP_DELTA 0x3f
+#define BIT_REG_TEMP_DELTA(x) \
+ (((x) & BIT_MASK_REG_TEMP_DELTA) << BIT_SHIFT_REG_TEMP_DELTA)
+#define BITS_REG_TEMP_DELTA \
+ (BIT_MASK_REG_TEMP_DELTA << BIT_SHIFT_REG_TEMP_DELTA)
+#define BIT_CLEAR_REG_TEMP_DELTA(x) ((x) & (~BITS_REG_TEMP_DELTA))
+#define BIT_GET_REG_TEMP_DELTA(x) \
+ (((x) >> BIT_SHIFT_REG_TEMP_DELTA) & BIT_MASK_REG_TEMP_DELTA)
+#define BIT_SET_REG_TEMP_DELTA(x, v) \
+ (BIT_CLEAR_REG_TEMP_DELTA(x) | BIT_REG_TEMP_DELTA(v))
+#define BIT_REG_TMETER_EN BIT(0)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_TMETER (Offset 0x0190) */
+#define BIT_SHIFT_MACCLK_FREQ_HIGH10 0
+#define BIT_MASK_MACCLK_FREQ_HIGH10 0x3ff
+#define BIT_MACCLK_FREQ_HIGH10(x) \
+ (((x) & BIT_MASK_MACCLK_FREQ_HIGH10) << BIT_SHIFT_MACCLK_FREQ_HIGH10)
+#define BITS_MACCLK_FREQ_HIGH10 \
+ (BIT_MASK_MACCLK_FREQ_HIGH10 << BIT_SHIFT_MACCLK_FREQ_HIGH10)
+#define BIT_CLEAR_MACCLK_FREQ_HIGH10(x) ((x) & (~BITS_MACCLK_FREQ_HIGH10))
+#define BIT_GET_MACCLK_FREQ_HIGH10(x) \
+ (((x) >> BIT_SHIFT_MACCLK_FREQ_HIGH10) & BIT_MASK_MACCLK_FREQ_HIGH10)
+#define BIT_SET_MACCLK_FREQ_HIGH10(x, v) \
+ (BIT_CLEAR_MACCLK_FREQ_HIGH10(x) | BIT_MACCLK_FREQ_HIGH10(v))
-/* 2 REG_OSC_32K_CTRL (Offset 0x0194) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_OSC_32K_CLKGEN_0 16
-#define BIT_MASK_OSC_32K_CLKGEN_0 0xffff
-#define BIT_OSC_32K_CLKGEN_0(x) (((x) & BIT_MASK_OSC_32K_CLKGEN_0) << BIT_SHIFT_OSC_32K_CLKGEN_0)
-#define BIT_GET_OSC_32K_CLKGEN_0(x) (((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0) & BIT_MASK_OSC_32K_CLKGEN_0)
+/* 2 REG_OSC_32K_CTRL (Offset 0x0194) */
+#define BIT_SHIFT_OSC_32K_CLKGEN_0 16
+#define BIT_MASK_OSC_32K_CLKGEN_0 0xffff
+#define BIT_OSC_32K_CLKGEN_0(x) \
+ (((x) & BIT_MASK_OSC_32K_CLKGEN_0) << BIT_SHIFT_OSC_32K_CLKGEN_0)
+#define BITS_OSC_32K_CLKGEN_0 \
+ (BIT_MASK_OSC_32K_CLKGEN_0 << BIT_SHIFT_OSC_32K_CLKGEN_0)
+#define BIT_CLEAR_OSC_32K_CLKGEN_0(x) ((x) & (~BITS_OSC_32K_CLKGEN_0))
+#define BIT_GET_OSC_32K_CLKGEN_0(x) \
+ (((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0) & BIT_MASK_OSC_32K_CLKGEN_0)
+#define BIT_SET_OSC_32K_CLKGEN_0(x, v) \
+ (BIT_CLEAR_OSC_32K_CLKGEN_0(x) | BIT_OSC_32K_CLKGEN_0(v))
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_OSC_32K_CTRL (Offset 0x0194) */
-#define BIT_32K_CLK_OUT_RDY BIT(12)
-
-#define BIT_SHIFT_MONITOR_CYCLE_LOG2 8
-#define BIT_MASK_MONITOR_CYCLE_LOG2 0xf
-#define BIT_MONITOR_CYCLE_LOG2(x) (((x) & BIT_MASK_MONITOR_CYCLE_LOG2) << BIT_SHIFT_MONITOR_CYCLE_LOG2)
-#define BIT_GET_MONITOR_CYCLE_LOG2(x) (((x) >> BIT_SHIFT_MONITOR_CYCLE_LOG2) & BIT_MASK_MONITOR_CYCLE_LOG2)
+#define BIT_32K_CLK_OUT_RDY BIT(12)
+#define BIT_SHIFT_MONITOR_CYCLE_LOG2 8
+#define BIT_MASK_MONITOR_CYCLE_LOG2 0xf
+#define BIT_MONITOR_CYCLE_LOG2(x) \
+ (((x) & BIT_MASK_MONITOR_CYCLE_LOG2) << BIT_SHIFT_MONITOR_CYCLE_LOG2)
+#define BITS_MONITOR_CYCLE_LOG2 \
+ (BIT_MASK_MONITOR_CYCLE_LOG2 << BIT_SHIFT_MONITOR_CYCLE_LOG2)
+#define BIT_CLEAR_MONITOR_CYCLE_LOG2(x) ((x) & (~BITS_MONITOR_CYCLE_LOG2))
+#define BIT_GET_MONITOR_CYCLE_LOG2(x) \
+ (((x) >> BIT_SHIFT_MONITOR_CYCLE_LOG2) & BIT_MASK_MONITOR_CYCLE_LOG2)
+#define BIT_SET_MONITOR_CYCLE_LOG2(x, v) \
+ (BIT_CLEAR_MONITOR_CYCLE_LOG2(x) | BIT_MONITOR_CYCLE_LOG2(v))
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_OSC_32K_CTRL (Offset 0x0194) */
+#define BIT_SHIFT_OSC_32K_RES_COMP 4
+#define BIT_MASK_OSC_32K_RES_COMP 0x3
+#define BIT_OSC_32K_RES_COMP(x) \
+ (((x) & BIT_MASK_OSC_32K_RES_COMP) << BIT_SHIFT_OSC_32K_RES_COMP)
+#define BITS_OSC_32K_RES_COMP \
+ (BIT_MASK_OSC_32K_RES_COMP << BIT_SHIFT_OSC_32K_RES_COMP)
+#define BIT_CLEAR_OSC_32K_RES_COMP(x) ((x) & (~BITS_OSC_32K_RES_COMP))
+#define BIT_GET_OSC_32K_RES_COMP(x) \
+ (((x) >> BIT_SHIFT_OSC_32K_RES_COMP) & BIT_MASK_OSC_32K_RES_COMP)
+#define BIT_SET_OSC_32K_RES_COMP(x, v) \
+ (BIT_CLEAR_OSC_32K_RES_COMP(x) | BIT_OSC_32K_RES_COMP(v))
-#define BIT_SHIFT_OSC_32K_RES_COMP 4
-#define BIT_MASK_OSC_32K_RES_COMP 0x3
-#define BIT_OSC_32K_RES_COMP(x) (((x) & BIT_MASK_OSC_32K_RES_COMP) << BIT_SHIFT_OSC_32K_RES_COMP)
-#define BIT_GET_OSC_32K_RES_COMP(x) (((x) >> BIT_SHIFT_OSC_32K_RES_COMP) & BIT_MASK_OSC_32K_RES_COMP)
-
-#define BIT_OSC_32K_OUT_SEL BIT(3)
+#define BIT_OSC_32K_OUT_SEL BIT(3)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_OSC_32K_CTRL (Offset 0x0194) */
+
+#define BIT_ISO_WL_2_OSC_32K BIT(1)
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_OSC_32K_CTRL (Offset 0x0194) */
-#define BIT_ISO_WL_2_OSC_32K BIT(1)
+#define BIT_POW_CKGEN BIT(0)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+/* 2 REG_32K_CAL_REG1 (Offset 0x0198) */
-/* 2 REG_OSC_32K_CTRL (Offset 0x0194) */
+#define BIT_CAL_32K_REG_WR BIT(31)
+#define BIT_CAL_32K_DBG_SEL BIT(22)
-#define BIT_POW_CKGEN BIT(0)
+#define BIT_SHIFT_CAL_32K_REG_ADDR 16
+#define BIT_MASK_CAL_32K_REG_ADDR 0x3f
+#define BIT_CAL_32K_REG_ADDR(x) \
+ (((x) & BIT_MASK_CAL_32K_REG_ADDR) << BIT_SHIFT_CAL_32K_REG_ADDR)
+#define BITS_CAL_32K_REG_ADDR \
+ (BIT_MASK_CAL_32K_REG_ADDR << BIT_SHIFT_CAL_32K_REG_ADDR)
+#define BIT_CLEAR_CAL_32K_REG_ADDR(x) ((x) & (~BITS_CAL_32K_REG_ADDR))
+#define BIT_GET_CAL_32K_REG_ADDR(x) \
+ (((x) >> BIT_SHIFT_CAL_32K_REG_ADDR) & BIT_MASK_CAL_32K_REG_ADDR)
+#define BIT_SET_CAL_32K_REG_ADDR(x, v) \
+ (BIT_CLEAR_CAL_32K_REG_ADDR(x) | BIT_CAL_32K_REG_ADDR(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_32K_CAL_REG1 (Offset 0x0198) */
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#define BIT_SHIFT_FREQVALUE_UNREGCLK 8
+#define BIT_MASK_FREQVALUE_UNREGCLK 0xffffff
+#define BIT_FREQVALUE_UNREGCLK(x) \
+ (((x) & BIT_MASK_FREQVALUE_UNREGCLK) << BIT_SHIFT_FREQVALUE_UNREGCLK)
+#define BITS_FREQVALUE_UNREGCLK \
+ (BIT_MASK_FREQVALUE_UNREGCLK << BIT_SHIFT_FREQVALUE_UNREGCLK)
+#define BIT_CLEAR_FREQVALUE_UNREGCLK(x) ((x) & (~BITS_FREQVALUE_UNREGCLK))
+#define BIT_GET_FREQVALUE_UNREGCLK(x) \
+ (((x) >> BIT_SHIFT_FREQVALUE_UNREGCLK) & BIT_MASK_FREQVALUE_UNREGCLK)
+#define BIT_SET_FREQVALUE_UNREGCLK(x, v) \
+ (BIT_CLEAR_FREQVALUE_UNREGCLK(x) | BIT_FREQVALUE_UNREGCLK(v))
+#define BIT_CAL32K_DBGMOD BIT(7)
-/* 2 REG_32K_CAL_REG1 (Offset 0x0198) */
+#endif
-#define BIT_CAL_32K_REG_WR BIT(31)
-#define BIT_CAL_32K_DBG_SEL BIT(22)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_CAL_32K_REG_ADDR 16
-#define BIT_MASK_CAL_32K_REG_ADDR 0x3f
-#define BIT_CAL_32K_REG_ADDR(x) (((x) & BIT_MASK_CAL_32K_REG_ADDR) << BIT_SHIFT_CAL_32K_REG_ADDR)
-#define BIT_GET_CAL_32K_REG_ADDR(x) (((x) >> BIT_SHIFT_CAL_32K_REG_ADDR) & BIT_MASK_CAL_32K_REG_ADDR)
+/* 2 REG_32K_CAL_REG1 (Offset 0x0198) */
+#define BIT_SHIFT_CAL_32K_REG_DATA 0
+#define BIT_MASK_CAL_32K_REG_DATA 0xffff
+#define BIT_CAL_32K_REG_DATA(x) \
+ (((x) & BIT_MASK_CAL_32K_REG_DATA) << BIT_SHIFT_CAL_32K_REG_DATA)
+#define BITS_CAL_32K_REG_DATA \
+ (BIT_MASK_CAL_32K_REG_DATA << BIT_SHIFT_CAL_32K_REG_DATA)
+#define BIT_CLEAR_CAL_32K_REG_DATA(x) ((x) & (~BITS_CAL_32K_REG_DATA))
+#define BIT_GET_CAL_32K_REG_DATA(x) \
+ (((x) >> BIT_SHIFT_CAL_32K_REG_DATA) & BIT_MASK_CAL_32K_REG_DATA)
+#define BIT_SET_CAL_32K_REG_DATA(x, v) \
+ (BIT_CLEAR_CAL_32K_REG_DATA(x) | BIT_CAL_32K_REG_DATA(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_32K_CAL_REG1 (Offset 0x0198) */
+#define BIT_SHIFT_NCO_THRS 0
+#define BIT_MASK_NCO_THRS 0x7f
+#define BIT_NCO_THRS(x) (((x) & BIT_MASK_NCO_THRS) << BIT_SHIFT_NCO_THRS)
+#define BITS_NCO_THRS (BIT_MASK_NCO_THRS << BIT_SHIFT_NCO_THRS)
+#define BIT_CLEAR_NCO_THRS(x) ((x) & (~BITS_NCO_THRS))
+#define BIT_GET_NCO_THRS(x) (((x) >> BIT_SHIFT_NCO_THRS) & BIT_MASK_NCO_THRS)
+#define BIT_SET_NCO_THRS(x, v) (BIT_CLEAR_NCO_THRS(x) | BIT_NCO_THRS(v))
-/* 2 REG_32K_CAL_REG1 (Offset 0x0198) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_FREQVALUE_UNREGCLK 8
-#define BIT_MASK_FREQVALUE_UNREGCLK 0xffffff
-#define BIT_FREQVALUE_UNREGCLK(x) (((x) & BIT_MASK_FREQVALUE_UNREGCLK) << BIT_SHIFT_FREQVALUE_UNREGCLK)
-#define BIT_GET_FREQVALUE_UNREGCLK(x) (((x) >> BIT_SHIFT_FREQVALUE_UNREGCLK) & BIT_MASK_FREQVALUE_UNREGCLK)
+/* 2 REG_C2HEVT (Offset 0x01A0) */
-#define BIT_CAL32K_DBGMOD BIT(7)
+#define BIT_SHIFT_C2HEVT_MSG 0
+#define BIT_MASK_C2HEVT_MSG 0xffffffffffffffffffffffffffffffffL
+#define BIT_C2HEVT_MSG(x) (((x) & BIT_MASK_C2HEVT_MSG) << BIT_SHIFT_C2HEVT_MSG)
+#define BITS_C2HEVT_MSG (BIT_MASK_C2HEVT_MSG << BIT_SHIFT_C2HEVT_MSG)
+#define BIT_CLEAR_C2HEVT_MSG(x) ((x) & (~BITS_C2HEVT_MSG))
+#define BIT_GET_C2HEVT_MSG(x) \
+ (((x) >> BIT_SHIFT_C2HEVT_MSG) & BIT_MASK_C2HEVT_MSG)
+#define BIT_SET_C2HEVT_MSG(x, v) (BIT_CLEAR_C2HEVT_MSG(x) | BIT_C2HEVT_MSG(v))
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+/* 2 REG_C2HEVT (Offset 0x01A0) */
-/* 2 REG_32K_CAL_REG1 (Offset 0x0198) */
+#define BIT_SHIFT_C2HEVT_MSG_V1 0
+#define BIT_MASK_C2HEVT_MSG_V1 0xffffffffL
+#define BIT_C2HEVT_MSG_V1(x) \
+ (((x) & BIT_MASK_C2HEVT_MSG_V1) << BIT_SHIFT_C2HEVT_MSG_V1)
+#define BITS_C2HEVT_MSG_V1 (BIT_MASK_C2HEVT_MSG_V1 << BIT_SHIFT_C2HEVT_MSG_V1)
+#define BIT_CLEAR_C2HEVT_MSG_V1(x) ((x) & (~BITS_C2HEVT_MSG_V1))
+#define BIT_GET_C2HEVT_MSG_V1(x) \
+ (((x) >> BIT_SHIFT_C2HEVT_MSG_V1) & BIT_MASK_C2HEVT_MSG_V1)
+#define BIT_SET_C2HEVT_MSG_V1(x, v) \
+ (BIT_CLEAR_C2HEVT_MSG_V1(x) | BIT_C2HEVT_MSG_V1(v))
+
+/* 2 REG_C2HEVT_1 (Offset 0x01A4) */
+#define BIT_SHIFT_C2HEVT_MSG_1 0
+#define BIT_MASK_C2HEVT_MSG_1 0xffffffffL
+#define BIT_C2HEVT_MSG_1(x) \
+ (((x) & BIT_MASK_C2HEVT_MSG_1) << BIT_SHIFT_C2HEVT_MSG_1)
+#define BITS_C2HEVT_MSG_1 (BIT_MASK_C2HEVT_MSG_1 << BIT_SHIFT_C2HEVT_MSG_1)
+#define BIT_CLEAR_C2HEVT_MSG_1(x) ((x) & (~BITS_C2HEVT_MSG_1))
+#define BIT_GET_C2HEVT_MSG_1(x) \
+ (((x) >> BIT_SHIFT_C2HEVT_MSG_1) & BIT_MASK_C2HEVT_MSG_1)
+#define BIT_SET_C2HEVT_MSG_1(x, v) \
+ (BIT_CLEAR_C2HEVT_MSG_1(x) | BIT_C2HEVT_MSG_1(v))
+
+/* 2 REG_C2HEVT_2 (Offset 0x01A8) */
+
+#define BIT_SHIFT_C2HEVT_MSG_2 0
+#define BIT_MASK_C2HEVT_MSG_2 0xffffffffL
+#define BIT_C2HEVT_MSG_2(x) \
+ (((x) & BIT_MASK_C2HEVT_MSG_2) << BIT_SHIFT_C2HEVT_MSG_2)
+#define BITS_C2HEVT_MSG_2 (BIT_MASK_C2HEVT_MSG_2 << BIT_SHIFT_C2HEVT_MSG_2)
+#define BIT_CLEAR_C2HEVT_MSG_2(x) ((x) & (~BITS_C2HEVT_MSG_2))
+#define BIT_GET_C2HEVT_MSG_2(x) \
+ (((x) >> BIT_SHIFT_C2HEVT_MSG_2) & BIT_MASK_C2HEVT_MSG_2)
+#define BIT_SET_C2HEVT_MSG_2(x, v) \
+ (BIT_CLEAR_C2HEVT_MSG_2(x) | BIT_C2HEVT_MSG_2(v))
-#define BIT_SHIFT_CAL_32K_REG_DATA 0
-#define BIT_MASK_CAL_32K_REG_DATA 0xffff
-#define BIT_CAL_32K_REG_DATA(x) (((x) & BIT_MASK_CAL_32K_REG_DATA) << BIT_SHIFT_CAL_32K_REG_DATA)
-#define BIT_GET_CAL_32K_REG_DATA(x) (((x) >> BIT_SHIFT_CAL_32K_REG_DATA) & BIT_MASK_CAL_32K_REG_DATA)
+/* 2 REG_C2HEVT_3 (Offset 0x01AC) */
+#define BIT_SHIFT_C2HEVT_MSG_3 0
+#define BIT_MASK_C2HEVT_MSG_3 0xffffffffL
+#define BIT_C2HEVT_MSG_3(x) \
+ (((x) & BIT_MASK_C2HEVT_MSG_3) << BIT_SHIFT_C2HEVT_MSG_3)
+#define BITS_C2HEVT_MSG_3 (BIT_MASK_C2HEVT_MSG_3 << BIT_SHIFT_C2HEVT_MSG_3)
+#define BIT_CLEAR_C2HEVT_MSG_3(x) ((x) & (~BITS_C2HEVT_MSG_3))
+#define BIT_GET_C2HEVT_MSG_3(x) \
+ (((x) >> BIT_SHIFT_C2HEVT_MSG_3) & BIT_MASK_C2HEVT_MSG_3)
+#define BIT_SET_C2HEVT_MSG_3(x, v) \
+ (BIT_CLEAR_C2HEVT_MSG_3(x) | BIT_C2HEVT_MSG_3(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_TC7_CTRL (Offset 0x01B0) */
+#define BIT_TC7INT_EN BIT(26)
+#define BIT_TC7MODE BIT(25)
+#define BIT_TC7EN BIT(24)
-/* 2 REG_32K_CAL_REG1 (Offset 0x0198) */
+#define BIT_SHIFT_TC7DATA 0
+#define BIT_MASK_TC7DATA 0xffffff
+#define BIT_TC7DATA(x) (((x) & BIT_MASK_TC7DATA) << BIT_SHIFT_TC7DATA)
+#define BITS_TC7DATA (BIT_MASK_TC7DATA << BIT_SHIFT_TC7DATA)
+#define BIT_CLEAR_TC7DATA(x) ((x) & (~BITS_TC7DATA))
+#define BIT_GET_TC7DATA(x) (((x) >> BIT_SHIFT_TC7DATA) & BIT_MASK_TC7DATA)
+#define BIT_SET_TC7DATA(x, v) (BIT_CLEAR_TC7DATA(x) | BIT_TC7DATA(v))
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_NCO_THRS 0
-#define BIT_MASK_NCO_THRS 0x7f
-#define BIT_NCO_THRS(x) (((x) & BIT_MASK_NCO_THRS) << BIT_SHIFT_NCO_THRS)
-#define BIT_GET_NCO_THRS(x) (((x) >> BIT_SHIFT_NCO_THRS) & BIT_MASK_NCO_THRS)
+/* 2 REG_RXDESC_BUFF_RPTR (Offset 0x01B0) */
+#define BIT_SHIFT_RXDESC_BUFF_RPTR 0
+#define BIT_MASK_RXDESC_BUFF_RPTR 0xffffffffL
+#define BIT_RXDESC_BUFF_RPTR(x) \
+ (((x) & BIT_MASK_RXDESC_BUFF_RPTR) << BIT_SHIFT_RXDESC_BUFF_RPTR)
+#define BITS_RXDESC_BUFF_RPTR \
+ (BIT_MASK_RXDESC_BUFF_RPTR << BIT_SHIFT_RXDESC_BUFF_RPTR)
+#define BIT_CLEAR_RXDESC_BUFF_RPTR(x) ((x) & (~BITS_RXDESC_BUFF_RPTR))
+#define BIT_GET_RXDESC_BUFF_RPTR(x) \
+ (((x) >> BIT_SHIFT_RXDESC_BUFF_RPTR) & BIT_MASK_RXDESC_BUFF_RPTR)
+#define BIT_SET_RXDESC_BUFF_RPTR(x, v) \
+ (BIT_CLEAR_RXDESC_BUFF_RPTR(x) | BIT_RXDESC_BUFF_RPTR(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_TC8_CTRL (Offset 0x01B4) */
+#define BIT_TC8INT_EN BIT(26)
+#define BIT_TC8MODE BIT(25)
+#define BIT_TC8EN BIT(24)
-/* 2 REG_C2HEVT (Offset 0x01A0) */
+#define BIT_SHIFT_TC8DATA 0
+#define BIT_MASK_TC8DATA 0xffffff
+#define BIT_TC8DATA(x) (((x) & BIT_MASK_TC8DATA) << BIT_SHIFT_TC8DATA)
+#define BITS_TC8DATA (BIT_MASK_TC8DATA << BIT_SHIFT_TC8DATA)
+#define BIT_CLEAR_TC8DATA(x) ((x) & (~BITS_TC8DATA))
+#define BIT_GET_TC8DATA(x) (((x) >> BIT_SHIFT_TC8DATA) & BIT_MASK_TC8DATA)
+#define BIT_SET_TC8DATA(x, v) (BIT_CLEAR_TC8DATA(x) | BIT_TC8DATA(v))
+
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_C2HEVT_MSG 0
-#define BIT_MASK_C2HEVT_MSG 0xffffffffffffffffffffffffffffffffL
-#define BIT_C2HEVT_MSG(x) (((x) & BIT_MASK_C2HEVT_MSG) << BIT_SHIFT_C2HEVT_MSG)
-#define BIT_GET_C2HEVT_MSG(x) (((x) >> BIT_SHIFT_C2HEVT_MSG) & BIT_MASK_C2HEVT_MSG)
+/* 2 REG_RXDESC_BUFF_WPTR (Offset 0x01B4) */
+#define BIT_SHIFT_RXDESC_BUFF_WPTR 0
+#define BIT_MASK_RXDESC_BUFF_WPTR 0xffffffffL
+#define BIT_RXDESC_BUFF_WPTR(x) \
+ (((x) & BIT_MASK_RXDESC_BUFF_WPTR) << BIT_SHIFT_RXDESC_BUFF_WPTR)
+#define BITS_RXDESC_BUFF_WPTR \
+ (BIT_MASK_RXDESC_BUFF_WPTR << BIT_SHIFT_RXDESC_BUFF_WPTR)
+#define BIT_CLEAR_RXDESC_BUFF_WPTR(x) ((x) & (~BITS_RXDESC_BUFF_WPTR))
+#define BIT_GET_RXDESC_BUFF_WPTR(x) \
+ (((x) >> BIT_SHIFT_RXDESC_BUFF_WPTR) & BIT_MASK_RXDESC_BUFF_WPTR)
+#define BIT_SET_RXDESC_BUFF_WPTR(x, v) \
+ (BIT_CLEAR_RXDESC_BUFF_WPTR(x) | BIT_RXDESC_BUFF_WPTR(v))
-/* 2 REG_SW_DEFINED_PAGE1 (Offset 0x01B8) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_SW_DEFINED_PAGE1 0
-#define BIT_MASK_SW_DEFINED_PAGE1 0xffffffffffffffffL
-#define BIT_SW_DEFINED_PAGE1(x) (((x) & BIT_MASK_SW_DEFINED_PAGE1) << BIT_SHIFT_SW_DEFINED_PAGE1)
-#define BIT_GET_SW_DEFINED_PAGE1(x) (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1) & BIT_MASK_SW_DEFINED_PAGE1)
+/* 2 REG_SW_DEFINED_PAGE1 (Offset 0x01B8) */
+#define BIT_SHIFT_SW_DEFINED_PAGE1 0
+#define BIT_MASK_SW_DEFINED_PAGE1 0xffffffffffffffffL
+#define BIT_SW_DEFINED_PAGE1(x) \
+ (((x) & BIT_MASK_SW_DEFINED_PAGE1) << BIT_SHIFT_SW_DEFINED_PAGE1)
+#define BITS_SW_DEFINED_PAGE1 \
+ (BIT_MASK_SW_DEFINED_PAGE1 << BIT_SHIFT_SW_DEFINED_PAGE1)
+#define BIT_CLEAR_SW_DEFINED_PAGE1(x) ((x) & (~BITS_SW_DEFINED_PAGE1))
+#define BIT_GET_SW_DEFINED_PAGE1(x) \
+ (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1) & BIT_MASK_SW_DEFINED_PAGE1)
+#define BIT_SET_SW_DEFINED_PAGE1(x, v) \
+ (BIT_CLEAR_SW_DEFINED_PAGE1(x) | BIT_SW_DEFINED_PAGE1(v))
-/* 2 REG_MCUTST_I (Offset 0x01C0) */
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_MCUDMSG_I 0
-#define BIT_MASK_MCUDMSG_I 0xffffffffL
-#define BIT_MCUDMSG_I(x) (((x) & BIT_MASK_MCUDMSG_I) << BIT_SHIFT_MCUDMSG_I)
-#define BIT_GET_MCUDMSG_I(x) (((x) >> BIT_SHIFT_MCUDMSG_I) & BIT_MASK_MCUDMSG_I)
+/* 2 REG_SW_DEFINED_PAGE1 (Offset 0x01B8) */
+#define BIT_SHIFT_SW_DEFINED_PAGE1_V1 0
+#define BIT_MASK_SW_DEFINED_PAGE1_V1 0xffffffffL
+#define BIT_SW_DEFINED_PAGE1_V1(x) \
+ (((x) & BIT_MASK_SW_DEFINED_PAGE1_V1) << BIT_SHIFT_SW_DEFINED_PAGE1_V1)
+#define BITS_SW_DEFINED_PAGE1_V1 \
+ (BIT_MASK_SW_DEFINED_PAGE1_V1 << BIT_SHIFT_SW_DEFINED_PAGE1_V1)
+#define BIT_CLEAR_SW_DEFINED_PAGE1_V1(x) ((x) & (~BITS_SW_DEFINED_PAGE1_V1))
+#define BIT_GET_SW_DEFINED_PAGE1_V1(x) \
+ (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_V1) & BIT_MASK_SW_DEFINED_PAGE1_V1)
+#define BIT_SET_SW_DEFINED_PAGE1_V1(x, v) \
+ (BIT_CLEAR_SW_DEFINED_PAGE1_V1(x) | BIT_SW_DEFINED_PAGE1_V1(v))
+
+/* 2 REG_SW_DEFINED_PAGE2 (Offset 0x01BC) */
+
+#define BIT_SHIFT_SW_DEFINED_PAGE2 0
+#define BIT_MASK_SW_DEFINED_PAGE2 0xffffffffL
+#define BIT_SW_DEFINED_PAGE2(x) \
+ (((x) & BIT_MASK_SW_DEFINED_PAGE2) << BIT_SHIFT_SW_DEFINED_PAGE2)
+#define BITS_SW_DEFINED_PAGE2 \
+ (BIT_MASK_SW_DEFINED_PAGE2 << BIT_SHIFT_SW_DEFINED_PAGE2)
+#define BIT_CLEAR_SW_DEFINED_PAGE2(x) ((x) & (~BITS_SW_DEFINED_PAGE2))
+#define BIT_GET_SW_DEFINED_PAGE2(x) \
+ (((x) >> BIT_SHIFT_SW_DEFINED_PAGE2) & BIT_MASK_SW_DEFINED_PAGE2)
+#define BIT_SET_SW_DEFINED_PAGE2(x, v) \
+ (BIT_CLEAR_SW_DEFINED_PAGE2(x) | BIT_SW_DEFINED_PAGE2(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-/* 2 REG_MCUTST_II (Offset 0x01C4) */
+/* 2 REG_MCUTST_I (Offset 0x01C0) */
+#define BIT_SHIFT_MCUDMSG_I 0
+#define BIT_MASK_MCUDMSG_I 0xffffffffL
+#define BIT_MCUDMSG_I(x) (((x) & BIT_MASK_MCUDMSG_I) << BIT_SHIFT_MCUDMSG_I)
+#define BITS_MCUDMSG_I (BIT_MASK_MCUDMSG_I << BIT_SHIFT_MCUDMSG_I)
+#define BIT_CLEAR_MCUDMSG_I(x) ((x) & (~BITS_MCUDMSG_I))
+#define BIT_GET_MCUDMSG_I(x) (((x) >> BIT_SHIFT_MCUDMSG_I) & BIT_MASK_MCUDMSG_I)
+#define BIT_SET_MCUDMSG_I(x, v) (BIT_CLEAR_MCUDMSG_I(x) | BIT_MCUDMSG_I(v))
-#define BIT_SHIFT_MCUDMSG_II 0
-#define BIT_MASK_MCUDMSG_II 0xffffffffL
-#define BIT_MCUDMSG_II(x) (((x) & BIT_MASK_MCUDMSG_II) << BIT_SHIFT_MCUDMSG_II)
-#define BIT_GET_MCUDMSG_II(x) (((x) >> BIT_SHIFT_MCUDMSG_II) & BIT_MASK_MCUDMSG_II)
+/* 2 REG_MCUTST_II (Offset 0x01C4) */
+#define BIT_SHIFT_MCUDMSG_II 0
+#define BIT_MASK_MCUDMSG_II 0xffffffffL
+#define BIT_MCUDMSG_II(x) (((x) & BIT_MASK_MCUDMSG_II) << BIT_SHIFT_MCUDMSG_II)
+#define BITS_MCUDMSG_II (BIT_MASK_MCUDMSG_II << BIT_SHIFT_MCUDMSG_II)
+#define BIT_CLEAR_MCUDMSG_II(x) ((x) & (~BITS_MCUDMSG_II))
+#define BIT_GET_MCUDMSG_II(x) \
+ (((x) >> BIT_SHIFT_MCUDMSG_II) & BIT_MASK_MCUDMSG_II)
+#define BIT_SET_MCUDMSG_II(x, v) (BIT_CLEAR_MCUDMSG_II(x) | BIT_MCUDMSG_II(v))
/* 2 REG_FMETHR (Offset 0x01C8) */
-#define BIT_FMSG_INT BIT(31)
-
-#define BIT_SHIFT_FW_MSG 0
-#define BIT_MASK_FW_MSG 0xffffffffL
-#define BIT_FW_MSG(x) (((x) & BIT_MASK_FW_MSG) << BIT_SHIFT_FW_MSG)
-#define BIT_GET_FW_MSG(x) (((x) >> BIT_SHIFT_FW_MSG) & BIT_MASK_FW_MSG)
+#define BIT_FMSG_INT BIT(31)
+#define BIT_SHIFT_FW_MSG 0
+#define BIT_MASK_FW_MSG 0xffffffffL
+#define BIT_FW_MSG(x) (((x) & BIT_MASK_FW_MSG) << BIT_SHIFT_FW_MSG)
+#define BITS_FW_MSG (BIT_MASK_FW_MSG << BIT_SHIFT_FW_MSG)
+#define BIT_CLEAR_FW_MSG(x) ((x) & (~BITS_FW_MSG))
+#define BIT_GET_FW_MSG(x) (((x) >> BIT_SHIFT_FW_MSG) & BIT_MASK_FW_MSG)
+#define BIT_SET_FW_MSG(x, v) (BIT_CLEAR_FW_MSG(x) | BIT_FW_MSG(v))
/* 2 REG_HMETFR (Offset 0x01CC) */
+#define BIT_SHIFT_HRCV_MSG 24
+#define BIT_MASK_HRCV_MSG 0xff
+#define BIT_HRCV_MSG(x) (((x) & BIT_MASK_HRCV_MSG) << BIT_SHIFT_HRCV_MSG)
+#define BITS_HRCV_MSG (BIT_MASK_HRCV_MSG << BIT_SHIFT_HRCV_MSG)
+#define BIT_CLEAR_HRCV_MSG(x) ((x) & (~BITS_HRCV_MSG))
+#define BIT_GET_HRCV_MSG(x) (((x) >> BIT_SHIFT_HRCV_MSG) & BIT_MASK_HRCV_MSG)
+#define BIT_SET_HRCV_MSG(x, v) (BIT_CLEAR_HRCV_MSG(x) | BIT_HRCV_MSG(v))
-#define BIT_SHIFT_HRCV_MSG 24
-#define BIT_MASK_HRCV_MSG 0xff
-#define BIT_HRCV_MSG(x) (((x) & BIT_MASK_HRCV_MSG) << BIT_SHIFT_HRCV_MSG)
-#define BIT_GET_HRCV_MSG(x) (((x) >> BIT_SHIFT_HRCV_MSG) & BIT_MASK_HRCV_MSG)
-
-#define BIT_INT_BOX3 BIT(3)
-#define BIT_INT_BOX2 BIT(2)
-#define BIT_INT_BOX1 BIT(1)
-#define BIT_INT_BOX0 BIT(0)
+#define BIT_INT_BOX3 BIT(3)
+#define BIT_INT_BOX2 BIT(2)
+#define BIT_INT_BOX1 BIT(1)
+#define BIT_INT_BOX0 BIT(0)
/* 2 REG_HMEBOX0 (Offset 0x01D0) */
-
-#define BIT_SHIFT_HOST_MSG_0 0
-#define BIT_MASK_HOST_MSG_0 0xffffffffL
-#define BIT_HOST_MSG_0(x) (((x) & BIT_MASK_HOST_MSG_0) << BIT_SHIFT_HOST_MSG_0)
-#define BIT_GET_HOST_MSG_0(x) (((x) >> BIT_SHIFT_HOST_MSG_0) & BIT_MASK_HOST_MSG_0)
-
+#define BIT_SHIFT_HOST_MSG_0 0
+#define BIT_MASK_HOST_MSG_0 0xffffffffL
+#define BIT_HOST_MSG_0(x) (((x) & BIT_MASK_HOST_MSG_0) << BIT_SHIFT_HOST_MSG_0)
+#define BITS_HOST_MSG_0 (BIT_MASK_HOST_MSG_0 << BIT_SHIFT_HOST_MSG_0)
+#define BIT_CLEAR_HOST_MSG_0(x) ((x) & (~BITS_HOST_MSG_0))
+#define BIT_GET_HOST_MSG_0(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_0) & BIT_MASK_HOST_MSG_0)
+#define BIT_SET_HOST_MSG_0(x, v) (BIT_CLEAR_HOST_MSG_0(x) | BIT_HOST_MSG_0(v))
/* 2 REG_HMEBOX1 (Offset 0x01D4) */
-
-#define BIT_SHIFT_HOST_MSG_1 0
-#define BIT_MASK_HOST_MSG_1 0xffffffffL
-#define BIT_HOST_MSG_1(x) (((x) & BIT_MASK_HOST_MSG_1) << BIT_SHIFT_HOST_MSG_1)
-#define BIT_GET_HOST_MSG_1(x) (((x) >> BIT_SHIFT_HOST_MSG_1) & BIT_MASK_HOST_MSG_1)
-
+#define BIT_SHIFT_HOST_MSG_1 0
+#define BIT_MASK_HOST_MSG_1 0xffffffffL
+#define BIT_HOST_MSG_1(x) (((x) & BIT_MASK_HOST_MSG_1) << BIT_SHIFT_HOST_MSG_1)
+#define BITS_HOST_MSG_1 (BIT_MASK_HOST_MSG_1 << BIT_SHIFT_HOST_MSG_1)
+#define BIT_CLEAR_HOST_MSG_1(x) ((x) & (~BITS_HOST_MSG_1))
+#define BIT_GET_HOST_MSG_1(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_1) & BIT_MASK_HOST_MSG_1)
+#define BIT_SET_HOST_MSG_1(x, v) (BIT_CLEAR_HOST_MSG_1(x) | BIT_HOST_MSG_1(v))
/* 2 REG_HMEBOX2 (Offset 0x01D8) */
-
-#define BIT_SHIFT_HOST_MSG_2 0
-#define BIT_MASK_HOST_MSG_2 0xffffffffL
-#define BIT_HOST_MSG_2(x) (((x) & BIT_MASK_HOST_MSG_2) << BIT_SHIFT_HOST_MSG_2)
-#define BIT_GET_HOST_MSG_2(x) (((x) >> BIT_SHIFT_HOST_MSG_2) & BIT_MASK_HOST_MSG_2)
-
+#define BIT_SHIFT_HOST_MSG_2 0
+#define BIT_MASK_HOST_MSG_2 0xffffffffL
+#define BIT_HOST_MSG_2(x) (((x) & BIT_MASK_HOST_MSG_2) << BIT_SHIFT_HOST_MSG_2)
+#define BITS_HOST_MSG_2 (BIT_MASK_HOST_MSG_2 << BIT_SHIFT_HOST_MSG_2)
+#define BIT_CLEAR_HOST_MSG_2(x) ((x) & (~BITS_HOST_MSG_2))
+#define BIT_GET_HOST_MSG_2(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_2) & BIT_MASK_HOST_MSG_2)
+#define BIT_SET_HOST_MSG_2(x, v) (BIT_CLEAR_HOST_MSG_2(x) | BIT_HOST_MSG_2(v))
/* 2 REG_HMEBOX3 (Offset 0x01DC) */
+#define BIT_SHIFT_HOST_MSG_3 0
+#define BIT_MASK_HOST_MSG_3 0xffffffffL
+#define BIT_HOST_MSG_3(x) (((x) & BIT_MASK_HOST_MSG_3) << BIT_SHIFT_HOST_MSG_3)
+#define BITS_HOST_MSG_3 (BIT_MASK_HOST_MSG_3 << BIT_SHIFT_HOST_MSG_3)
+#define BIT_CLEAR_HOST_MSG_3(x) ((x) & (~BITS_HOST_MSG_3))
+#define BIT_GET_HOST_MSG_3(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_3) & BIT_MASK_HOST_MSG_3)
+#define BIT_SET_HOST_MSG_3(x, v) (BIT_CLEAR_HOST_MSG_3(x) | BIT_HOST_MSG_3(v))
-#define BIT_SHIFT_HOST_MSG_3 0
-#define BIT_MASK_HOST_MSG_3 0xffffffffL
-#define BIT_HOST_MSG_3(x) (((x) & BIT_MASK_HOST_MSG_3) << BIT_SHIFT_HOST_MSG_3)
-#define BIT_GET_HOST_MSG_3(x) (((x) >> BIT_SHIFT_HOST_MSG_3) & BIT_MASK_HOST_MSG_3)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_LLT_INIT (Offset 0x01E0) */
-
-#define BIT_SHIFT_LLTE_RWM 30
-#define BIT_MASK_LLTE_RWM 0x3
-#define BIT_LLTE_RWM(x) (((x) & BIT_MASK_LLTE_RWM) << BIT_SHIFT_LLTE_RWM)
-#define BIT_GET_LLTE_RWM(x) (((x) >> BIT_SHIFT_LLTE_RWM) & BIT_MASK_LLTE_RWM)
-
+#define BIT_SHIFT_LLTE_RWM 30
+#define BIT_MASK_LLTE_RWM 0x3
+#define BIT_LLTE_RWM(x) (((x) & BIT_MASK_LLTE_RWM) << BIT_SHIFT_LLTE_RWM)
+#define BITS_LLTE_RWM (BIT_MASK_LLTE_RWM << BIT_SHIFT_LLTE_RWM)
+#define BIT_CLEAR_LLTE_RWM(x) ((x) & (~BITS_LLTE_RWM))
+#define BIT_GET_LLTE_RWM(x) (((x) >> BIT_SHIFT_LLTE_RWM) & BIT_MASK_LLTE_RWM)
+#define BIT_SET_LLTE_RWM(x, v) (BIT_CLEAR_LLTE_RWM(x) | BIT_LLTE_RWM(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_RXDESC_BUFF_BNDY (Offset 0x01E0) */
+#define BIT_FW_FIFO_PTR_RST BIT(18)
+#define BIT_PHY_FIFO_PTR_RST BIT(17)
-/* 2 REG_LLT_INIT (Offset 0x01E0) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_LLTINI_PDATA 16
-#define BIT_MASK_LLTINI_PDATA 0xff
-#define BIT_LLTINI_PDATA(x) (((x) & BIT_MASK_LLTINI_PDATA) << BIT_SHIFT_LLTINI_PDATA)
-#define BIT_GET_LLTINI_PDATA(x) (((x) >> BIT_SHIFT_LLTINI_PDATA) & BIT_MASK_LLTINI_PDATA)
+/* 2 REG_LLT_INIT (Offset 0x01E0) */
+#define BIT_SHIFT_LLTINI_PDATA 16
+#define BIT_MASK_LLTINI_PDATA 0xff
+#define BIT_LLTINI_PDATA(x) \
+ (((x) & BIT_MASK_LLTINI_PDATA) << BIT_SHIFT_LLTINI_PDATA)
+#define BITS_LLTINI_PDATA (BIT_MASK_LLTINI_PDATA << BIT_SHIFT_LLTINI_PDATA)
+#define BIT_CLEAR_LLTINI_PDATA(x) ((x) & (~BITS_LLTINI_PDATA))
+#define BIT_GET_LLTINI_PDATA(x) \
+ (((x) >> BIT_SHIFT_LLTINI_PDATA) & BIT_MASK_LLTINI_PDATA)
+#define BIT_SET_LLTINI_PDATA(x, v) \
+ (BIT_CLEAR_LLTINI_PDATA(x) | BIT_LLTINI_PDATA(v))
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
/* 2 REG_LLT_INIT (Offset 0x01E0) */
-
-#define BIT_SHIFT_LLTINI_PDATA_V1 16
-#define BIT_MASK_LLTINI_PDATA_V1 0xfff
-#define BIT_LLTINI_PDATA_V1(x) (((x) & BIT_MASK_LLTINI_PDATA_V1) << BIT_SHIFT_LLTINI_PDATA_V1)
-#define BIT_GET_LLTINI_PDATA_V1(x) (((x) >> BIT_SHIFT_LLTINI_PDATA_V1) & BIT_MASK_LLTINI_PDATA_V1)
-
+#define BIT_SHIFT_LLTINI_PDATA_V1 16
+#define BIT_MASK_LLTINI_PDATA_V1 0xfff
+#define BIT_LLTINI_PDATA_V1(x) \
+ (((x) & BIT_MASK_LLTINI_PDATA_V1) << BIT_SHIFT_LLTINI_PDATA_V1)
+#define BITS_LLTINI_PDATA_V1 \
+ (BIT_MASK_LLTINI_PDATA_V1 << BIT_SHIFT_LLTINI_PDATA_V1)
+#define BIT_CLEAR_LLTINI_PDATA_V1(x) ((x) & (~BITS_LLTINI_PDATA_V1))
+#define BIT_GET_LLTINI_PDATA_V1(x) \
+ (((x) >> BIT_SHIFT_LLTINI_PDATA_V1) & BIT_MASK_LLTINI_PDATA_V1)
+#define BIT_SET_LLTINI_PDATA_V1(x, v) \
+ (BIT_CLEAR_LLTINI_PDATA_V1(x) | BIT_LLTINI_PDATA_V1(v))
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_LLT_INIT (Offset 0x01E0) */
+
+#define BIT_SHIFT_LLTINI_ADDR 8
+#define BIT_MASK_LLTINI_ADDR 0xff
+#define BIT_LLTINI_ADDR(x) \
+ (((x) & BIT_MASK_LLTINI_ADDR) << BIT_SHIFT_LLTINI_ADDR)
+#define BITS_LLTINI_ADDR (BIT_MASK_LLTINI_ADDR << BIT_SHIFT_LLTINI_ADDR)
+#define BIT_CLEAR_LLTINI_ADDR(x) ((x) & (~BITS_LLTINI_ADDR))
+#define BIT_GET_LLTINI_ADDR(x) \
+ (((x) >> BIT_SHIFT_LLTINI_ADDR) & BIT_MASK_LLTINI_ADDR)
+#define BIT_SET_LLTINI_ADDR(x, v) \
+ (BIT_CLEAR_LLTINI_ADDR(x) | BIT_LLTINI_ADDR(v))
+
+#define BIT_SHIFT_LLTINI_HDATA 0
+#define BIT_MASK_LLTINI_HDATA 0xff
+#define BIT_LLTINI_HDATA(x) \
+ (((x) & BIT_MASK_LLTINI_HDATA) << BIT_SHIFT_LLTINI_HDATA)
+#define BITS_LLTINI_HDATA (BIT_MASK_LLTINI_HDATA << BIT_SHIFT_LLTINI_HDATA)
+#define BIT_CLEAR_LLTINI_HDATA(x) ((x) & (~BITS_LLTINI_HDATA))
+#define BIT_GET_LLTINI_HDATA(x) \
+ (((x) >> BIT_SHIFT_LLTINI_HDATA) & BIT_MASK_LLTINI_HDATA)
+#define BIT_SET_LLTINI_HDATA(x, v) \
+ (BIT_CLEAR_LLTINI_HDATA(x) | BIT_LLTINI_HDATA(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
/* 2 REG_LLT_INIT (Offset 0x01E0) */
+#define BIT_SHIFT_LLTINI_HDATA_V1 0
+#define BIT_MASK_LLTINI_HDATA_V1 0xfff
+#define BIT_LLTINI_HDATA_V1(x) \
+ (((x) & BIT_MASK_LLTINI_HDATA_V1) << BIT_SHIFT_LLTINI_HDATA_V1)
+#define BITS_LLTINI_HDATA_V1 \
+ (BIT_MASK_LLTINI_HDATA_V1 << BIT_SHIFT_LLTINI_HDATA_V1)
+#define BIT_CLEAR_LLTINI_HDATA_V1(x) ((x) & (~BITS_LLTINI_HDATA_V1))
+#define BIT_GET_LLTINI_HDATA_V1(x) \
+ (((x) >> BIT_SHIFT_LLTINI_HDATA_V1) & BIT_MASK_LLTINI_HDATA_V1)
+#define BIT_SET_LLTINI_HDATA_V1(x, v) \
+ (BIT_CLEAR_LLTINI_HDATA_V1(x) | BIT_LLTINI_HDATA_V1(v))
-#define BIT_SHIFT_LLTINI_ADDR 8
-#define BIT_MASK_LLTINI_ADDR 0xff
-#define BIT_LLTINI_ADDR(x) (((x) & BIT_MASK_LLTINI_ADDR) << BIT_SHIFT_LLTINI_ADDR)
-#define BIT_GET_LLTINI_ADDR(x) (((x) >> BIT_SHIFT_LLTINI_ADDR) & BIT_MASK_LLTINI_ADDR)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_LLTINI_HDATA 0
-#define BIT_MASK_LLTINI_HDATA 0xff
-#define BIT_LLTINI_HDATA(x) (((x) & BIT_MASK_LLTINI_HDATA) << BIT_SHIFT_LLTINI_HDATA)
-#define BIT_GET_LLTINI_HDATA(x) (((x) >> BIT_SHIFT_LLTINI_HDATA) & BIT_MASK_LLTINI_HDATA)
+/* 2 REG_RXDESC_BUFF_BNDY (Offset 0x01E0) */
+#define BIT_SHIFT_RXDESC_BUFF_BNDY 0
+#define BIT_MASK_RXDESC_BUFF_BNDY 0xffffffffL
+#define BIT_RXDESC_BUFF_BNDY(x) \
+ (((x) & BIT_MASK_RXDESC_BUFF_BNDY) << BIT_SHIFT_RXDESC_BUFF_BNDY)
+#define BITS_RXDESC_BUFF_BNDY \
+ (BIT_MASK_RXDESC_BUFF_BNDY << BIT_SHIFT_RXDESC_BUFF_BNDY)
+#define BIT_CLEAR_RXDESC_BUFF_BNDY(x) ((x) & (~BITS_RXDESC_BUFF_BNDY))
+#define BIT_GET_RXDESC_BUFF_BNDY(x) \
+ (((x) >> BIT_SHIFT_RXDESC_BUFF_BNDY) & BIT_MASK_RXDESC_BUFF_BNDY)
+#define BIT_SET_RXDESC_BUFF_BNDY(x, v) \
+ (BIT_CLEAR_RXDESC_BUFF_BNDY(x) | BIT_RXDESC_BUFF_BNDY(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_GENTST (Offset 0x01E4) */
+#define BIT_SHIFT_GENTST 0
+#define BIT_MASK_GENTST 0xffffffffL
+#define BIT_GENTST(x) (((x) & BIT_MASK_GENTST) << BIT_SHIFT_GENTST)
+#define BITS_GENTST (BIT_MASK_GENTST << BIT_SHIFT_GENTST)
+#define BIT_CLEAR_GENTST(x) ((x) & (~BITS_GENTST))
+#define BIT_GET_GENTST(x) (((x) >> BIT_SHIFT_GENTST) & BIT_MASK_GENTST)
+#define BIT_SET_GENTST(x, v) (BIT_CLEAR_GENTST(x) | BIT_GENTST(v))
-/* 2 REG_LLT_INIT (Offset 0x01E0) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_LLTINI_HDATA_V1 0
-#define BIT_MASK_LLTINI_HDATA_V1 0xfff
-#define BIT_LLTINI_HDATA_V1(x) (((x) & BIT_MASK_LLTINI_HDATA_V1) << BIT_SHIFT_LLTINI_HDATA_V1)
-#define BIT_GET_LLTINI_HDATA_V1(x) (((x) >> BIT_SHIFT_LLTINI_HDATA_V1) & BIT_MASK_LLTINI_HDATA_V1)
+/* 2 REG_LLT_INIT_ADDR (Offset 0x01E4) */
+#define BIT_SHIFT_LLTINI_ADDR_V1 0
+#define BIT_MASK_LLTINI_ADDR_V1 0xfff
+#define BIT_LLTINI_ADDR_V1(x) \
+ (((x) & BIT_MASK_LLTINI_ADDR_V1) << BIT_SHIFT_LLTINI_ADDR_V1)
+#define BITS_LLTINI_ADDR_V1 \
+ (BIT_MASK_LLTINI_ADDR_V1 << BIT_SHIFT_LLTINI_ADDR_V1)
+#define BIT_CLEAR_LLTINI_ADDR_V1(x) ((x) & (~BITS_LLTINI_ADDR_V1))
+#define BIT_GET_LLTINI_ADDR_V1(x) \
+ (((x) >> BIT_SHIFT_LLTINI_ADDR_V1) & BIT_MASK_LLTINI_ADDR_V1)
+#define BIT_SET_LLTINI_ADDR_V1(x, v) \
+ (BIT_CLEAR_LLTINI_ADDR_V1(x) | BIT_LLTINI_ADDR_V1(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */
+#define BIT_SHIFT_BB_WRITE_READ 30
+#define BIT_MASK_BB_WRITE_READ 0x3
+#define BIT_BB_WRITE_READ(x) \
+ (((x) & BIT_MASK_BB_WRITE_READ) << BIT_SHIFT_BB_WRITE_READ)
+#define BITS_BB_WRITE_READ (BIT_MASK_BB_WRITE_READ << BIT_SHIFT_BB_WRITE_READ)
+#define BIT_CLEAR_BB_WRITE_READ(x) ((x) & (~BITS_BB_WRITE_READ))
+#define BIT_GET_BB_WRITE_READ(x) \
+ (((x) >> BIT_SHIFT_BB_WRITE_READ) & BIT_MASK_BB_WRITE_READ)
+#define BIT_SET_BB_WRITE_READ(x, v) \
+ (BIT_CLEAR_BB_WRITE_READ(x) | BIT_BB_WRITE_READ(v))
-/* 2 REG_GENTST (Offset 0x01E4) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_GENTST 0
-#define BIT_MASK_GENTST 0xffffffffL
-#define BIT_GENTST(x) (((x) & BIT_MASK_GENTST) << BIT_SHIFT_GENTST)
-#define BIT_GET_GENTST(x) (((x) >> BIT_SHIFT_GENTST) & BIT_MASK_GENTST)
+/* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */
+#define BIT_SHIFT_BB_WRITE_EN_V1 16
+#define BIT_MASK_BB_WRITE_EN_V1 0xf
+#define BIT_BB_WRITE_EN_V1(x) \
+ (((x) & BIT_MASK_BB_WRITE_EN_V1) << BIT_SHIFT_BB_WRITE_EN_V1)
+#define BITS_BB_WRITE_EN_V1 \
+ (BIT_MASK_BB_WRITE_EN_V1 << BIT_SHIFT_BB_WRITE_EN_V1)
+#define BIT_CLEAR_BB_WRITE_EN_V1(x) ((x) & (~BITS_BB_WRITE_EN_V1))
+#define BIT_GET_BB_WRITE_EN_V1(x) \
+ (((x) >> BIT_SHIFT_BB_WRITE_EN_V1) & BIT_MASK_BB_WRITE_EN_V1)
+#define BIT_SET_BB_WRITE_EN_V1(x, v) \
+ (BIT_CLEAR_BB_WRITE_EN_V1(x) | BIT_BB_WRITE_EN_V1(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */
+#define BIT_SHIFT_BB_WRITE_EN 12
+#define BIT_MASK_BB_WRITE_EN 0xf
+#define BIT_BB_WRITE_EN(x) \
+ (((x) & BIT_MASK_BB_WRITE_EN) << BIT_SHIFT_BB_WRITE_EN)
+#define BITS_BB_WRITE_EN (BIT_MASK_BB_WRITE_EN << BIT_SHIFT_BB_WRITE_EN)
+#define BIT_CLEAR_BB_WRITE_EN(x) ((x) & (~BITS_BB_WRITE_EN))
+#define BIT_GET_BB_WRITE_EN(x) \
+ (((x) >> BIT_SHIFT_BB_WRITE_EN) & BIT_MASK_BB_WRITE_EN)
+#define BIT_SET_BB_WRITE_EN(x, v) \
+ (BIT_CLEAR_BB_WRITE_EN(x) | BIT_BB_WRITE_EN(v))
-/* 2 REG_LLT_INIT_ADDR (Offset 0x01E4) */
+#define BIT_SHIFT_BB_ADDR 2
+#define BIT_MASK_BB_ADDR 0x1ff
+#define BIT_BB_ADDR(x) (((x) & BIT_MASK_BB_ADDR) << BIT_SHIFT_BB_ADDR)
+#define BITS_BB_ADDR (BIT_MASK_BB_ADDR << BIT_SHIFT_BB_ADDR)
+#define BIT_CLEAR_BB_ADDR(x) ((x) & (~BITS_BB_ADDR))
+#define BIT_GET_BB_ADDR(x) (((x) >> BIT_SHIFT_BB_ADDR) & BIT_MASK_BB_ADDR)
+#define BIT_SET_BB_ADDR(x, v) (BIT_CLEAR_BB_ADDR(x) | BIT_BB_ADDR(v))
+#endif
-#define BIT_SHIFT_LLTINI_ADDR_V1 0
-#define BIT_MASK_LLTINI_ADDR_V1 0xfff
-#define BIT_LLTINI_ADDR_V1(x) (((x) & BIT_MASK_LLTINI_ADDR_V1) << BIT_SHIFT_LLTINI_ADDR_V1)
-#define BIT_GET_LLTINI_ADDR_V1(x) (((x) >> BIT_SHIFT_LLTINI_ADDR_V1) & BIT_MASK_LLTINI_ADDR_V1)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+/* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */
-#endif
-
+#define BIT_SHIFT_BB_ADDR_V1 2
+#define BIT_MASK_BB_ADDR_V1 0xfff
+#define BIT_BB_ADDR_V1(x) (((x) & BIT_MASK_BB_ADDR_V1) << BIT_SHIFT_BB_ADDR_V1)
+#define BITS_BB_ADDR_V1 (BIT_MASK_BB_ADDR_V1 << BIT_SHIFT_BB_ADDR_V1)
+#define BIT_CLEAR_BB_ADDR_V1(x) ((x) & (~BITS_BB_ADDR_V1))
+#define BIT_GET_BB_ADDR_V1(x) \
+ (((x) >> BIT_SHIFT_BB_ADDR_V1) & BIT_MASK_BB_ADDR_V1)
+#define BIT_SET_BB_ADDR_V1(x, v) (BIT_CLEAR_BB_ADDR_V1(x) | BIT_BB_ADDR_V1(v))
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */
+#define BIT_BB_ERRACC BIT(0)
-#define BIT_SHIFT_BB_WRITE_READ 30
-#define BIT_MASK_BB_WRITE_READ 0x3
-#define BIT_BB_WRITE_READ(x) (((x) & BIT_MASK_BB_WRITE_READ) << BIT_SHIFT_BB_WRITE_READ)
-#define BIT_GET_BB_WRITE_READ(x) (((x) >> BIT_SHIFT_BB_WRITE_READ) & BIT_MASK_BB_WRITE_READ)
+/* 2 REG_BB_ACCESS_DATA (Offset 0x01EC) */
+#define BIT_SHIFT_BB_DATA 0
+#define BIT_MASK_BB_DATA 0xffffffffL
+#define BIT_BB_DATA(x) (((x) & BIT_MASK_BB_DATA) << BIT_SHIFT_BB_DATA)
+#define BITS_BB_DATA (BIT_MASK_BB_DATA << BIT_SHIFT_BB_DATA)
+#define BIT_CLEAR_BB_DATA(x) ((x) & (~BITS_BB_DATA))
+#define BIT_GET_BB_DATA(x) (((x) >> BIT_SHIFT_BB_DATA) & BIT_MASK_BB_DATA)
+#define BIT_SET_BB_DATA(x, v) (BIT_CLEAR_BB_DATA(x) | BIT_BB_DATA(v))
-#endif
+/* 2 REG_HMEBOX_E0 (Offset 0x01F0) */
+#define BIT_SHIFT_HMEBOX_E0 0
+#define BIT_MASK_HMEBOX_E0 0xffffffffL
+#define BIT_HMEBOX_E0(x) (((x) & BIT_MASK_HMEBOX_E0) << BIT_SHIFT_HMEBOX_E0)
+#define BITS_HMEBOX_E0 (BIT_MASK_HMEBOX_E0 << BIT_SHIFT_HMEBOX_E0)
+#define BIT_CLEAR_HMEBOX_E0(x) ((x) & (~BITS_HMEBOX_E0))
+#define BIT_GET_HMEBOX_E0(x) (((x) >> BIT_SHIFT_HMEBOX_E0) & BIT_MASK_HMEBOX_E0)
+#define BIT_SET_HMEBOX_E0(x, v) (BIT_CLEAR_HMEBOX_E0(x) | BIT_HMEBOX_E0(v))
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_HMEBOX_E1 (Offset 0x01F4) */
+#define BIT_SHIFT_HMEBOX_E1 0
+#define BIT_MASK_HMEBOX_E1 0xffffffffL
+#define BIT_HMEBOX_E1(x) (((x) & BIT_MASK_HMEBOX_E1) << BIT_SHIFT_HMEBOX_E1)
+#define BITS_HMEBOX_E1 (BIT_MASK_HMEBOX_E1 << BIT_SHIFT_HMEBOX_E1)
+#define BIT_CLEAR_HMEBOX_E1(x) ((x) & (~BITS_HMEBOX_E1))
+#define BIT_GET_HMEBOX_E1(x) (((x) >> BIT_SHIFT_HMEBOX_E1) & BIT_MASK_HMEBOX_E1)
+#define BIT_SET_HMEBOX_E1(x, v) (BIT_CLEAR_HMEBOX_E1(x) | BIT_HMEBOX_E1(v))
-/* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */
+/* 2 REG_HMEBOX_E2 (Offset 0x01F8) */
+#define BIT_SHIFT_HMEBOX_E2 0
+#define BIT_MASK_HMEBOX_E2 0xffffffffL
+#define BIT_HMEBOX_E2(x) (((x) & BIT_MASK_HMEBOX_E2) << BIT_SHIFT_HMEBOX_E2)
+#define BITS_HMEBOX_E2 (BIT_MASK_HMEBOX_E2 << BIT_SHIFT_HMEBOX_E2)
+#define BIT_CLEAR_HMEBOX_E2(x) ((x) & (~BITS_HMEBOX_E2))
+#define BIT_GET_HMEBOX_E2(x) (((x) >> BIT_SHIFT_HMEBOX_E2) & BIT_MASK_HMEBOX_E2)
+#define BIT_SET_HMEBOX_E2(x, v) (BIT_CLEAR_HMEBOX_E2(x) | BIT_HMEBOX_E2(v))
-#define BIT_SHIFT_BB_WRITE_EN_V1 16
-#define BIT_MASK_BB_WRITE_EN_V1 0xf
-#define BIT_BB_WRITE_EN_V1(x) (((x) & BIT_MASK_BB_WRITE_EN_V1) << BIT_SHIFT_BB_WRITE_EN_V1)
-#define BIT_GET_BB_WRITE_EN_V1(x) (((x) >> BIT_SHIFT_BB_WRITE_EN_V1) & BIT_MASK_BB_WRITE_EN_V1)
+/* 2 REG_HMEBOX_E3 (Offset 0x01FC) */
+#define BIT_SHIFT_HMEBOX_E3 0
+#define BIT_MASK_HMEBOX_E3 0xffffffffL
+#define BIT_HMEBOX_E3(x) (((x) & BIT_MASK_HMEBOX_E3) << BIT_SHIFT_HMEBOX_E3)
+#define BITS_HMEBOX_E3 (BIT_MASK_HMEBOX_E3 << BIT_SHIFT_HMEBOX_E3)
+#define BIT_CLEAR_HMEBOX_E3(x) ((x) & (~BITS_HMEBOX_E3))
+#define BIT_GET_HMEBOX_E3(x) (((x) >> BIT_SHIFT_HMEBOX_E3) & BIT_MASK_HMEBOX_E3)
+#define BIT_SET_HMEBOX_E3(x, v) (BIT_CLEAR_HMEBOX_E3(x) | BIT_HMEBOX_E3(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+/* 2 REG_BCN_CTRL_0 (Offset 0x0200) */
-/* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */
+#define BIT_BCN1_VALID BIT(31)
+#endif
-#define BIT_SHIFT_BB_WRITE_EN 12
-#define BIT_MASK_BB_WRITE_EN 0xf
-#define BIT_BB_WRITE_EN(x) (((x) & BIT_MASK_BB_WRITE_EN) << BIT_SHIFT_BB_WRITE_EN)
-#define BIT_GET_BB_WRITE_EN(x) (((x) >> BIT_SHIFT_BB_WRITE_EN) & BIT_MASK_BB_WRITE_EN)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_RQPN_CTRL_HLPQ (Offset 0x0200) */
-#define BIT_SHIFT_BB_ADDR 2
-#define BIT_MASK_BB_ADDR 0x1ff
-#define BIT_BB_ADDR(x) (((x) & BIT_MASK_BB_ADDR) << BIT_SHIFT_BB_ADDR)
-#define BIT_GET_BB_ADDR(x) (((x) >> BIT_SHIFT_BB_ADDR) & BIT_MASK_BB_ADDR)
+#define BIT_EPQ_PUBLIC_DIS BIT(27)
+#define BIT_NPQ_PUBLIC_DIS BIT(26)
+#define BIT_LPQ_PUBLIC_DIS BIT(25)
+#define BIT_HPQ_PUBLIC_DIS BIT(24)
+#define BIT_SHIFT_PUBQ 16
+#define BIT_MASK_PUBQ 0xff
+#define BIT_PUBQ(x) (((x) & BIT_MASK_PUBQ) << BIT_SHIFT_PUBQ)
+#define BITS_PUBQ (BIT_MASK_PUBQ << BIT_SHIFT_PUBQ)
+#define BIT_CLEAR_PUBQ(x) ((x) & (~BITS_PUBQ))
+#define BIT_GET_PUBQ(x) (((x) >> BIT_SHIFT_PUBQ) & BIT_MASK_PUBQ)
+#define BIT_SET_PUBQ(x, v) (BIT_CLEAR_PUBQ(x) | BIT_PUBQ(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
-
-/* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */
-
-
-#define BIT_SHIFT_BB_ADDR_V1 2
-#define BIT_MASK_BB_ADDR_V1 0xfff
-#define BIT_BB_ADDR_V1(x) (((x) & BIT_MASK_BB_ADDR_V1) << BIT_SHIFT_BB_ADDR_V1)
-#define BIT_GET_BB_ADDR_V1(x) (((x) >> BIT_SHIFT_BB_ADDR_V1) & BIT_MASK_BB_ADDR_V1)
+/* 2 REG_FIFOPAGE_CTRL_1 (Offset 0x0200) */
+#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1 16
+#define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1 0xff
+#define BIT_TX_OQT_HE_FREE_SPACE_V1(x) \
+ (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1) \
+ << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1)
+#define BITS_TX_OQT_HE_FREE_SPACE_V1 \
+ (BIT_MASK_TX_OQT_HE_FREE_SPACE_V1 << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1)
+#define BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1(x) \
+ ((x) & (~BITS_TX_OQT_HE_FREE_SPACE_V1))
+#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1(x) \
+ (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1) & \
+ BIT_MASK_TX_OQT_HE_FREE_SPACE_V1)
+#define BIT_SET_TX_OQT_HE_FREE_SPACE_V1(x, v) \
+ (BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1(x) | BIT_TX_OQT_HE_FREE_SPACE_V1(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_BCN_CTRL_0 (Offset 0x0200) */
+#define BIT_SHIFT_BCN1_HEAD 16
+#define BIT_MASK_BCN1_HEAD 0xfff
+#define BIT_BCN1_HEAD(x) (((x) & BIT_MASK_BCN1_HEAD) << BIT_SHIFT_BCN1_HEAD)
+#define BITS_BCN1_HEAD (BIT_MASK_BCN1_HEAD << BIT_SHIFT_BCN1_HEAD)
+#define BIT_CLEAR_BCN1_HEAD(x) ((x) & (~BITS_BCN1_HEAD))
+#define BIT_GET_BCN1_HEAD(x) (((x) >> BIT_SHIFT_BCN1_HEAD) & BIT_MASK_BCN1_HEAD)
+#define BIT_SET_BCN1_HEAD(x, v) (BIT_CLEAR_BCN1_HEAD(x) | BIT_BCN1_HEAD(v))
-/* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */
+#define BIT_BCN0_VALID BIT(15)
-#define BIT_BB_ERRACC BIT(0)
+#endif
-/* 2 REG_BB_ACCESS_DATA (Offset 0x01EC) */
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_RQPN_CTRL_HLPQ (Offset 0x0200) */
-#define BIT_SHIFT_BB_DATA 0
-#define BIT_MASK_BB_DATA 0xffffffffL
-#define BIT_BB_DATA(x) (((x) & BIT_MASK_BB_DATA) << BIT_SHIFT_BB_DATA)
-#define BIT_GET_BB_DATA(x) (((x) >> BIT_SHIFT_BB_DATA) & BIT_MASK_BB_DATA)
+#define BIT_SHIFT_LPQ 8
+#define BIT_MASK_LPQ 0xff
+#define BIT_LPQ(x) (((x) & BIT_MASK_LPQ) << BIT_SHIFT_LPQ)
+#define BITS_LPQ (BIT_MASK_LPQ << BIT_SHIFT_LPQ)
+#define BIT_CLEAR_LPQ(x) ((x) & (~BITS_LPQ))
+#define BIT_GET_LPQ(x) (((x) >> BIT_SHIFT_LPQ) & BIT_MASK_LPQ)
+#define BIT_SET_LPQ(x, v) (BIT_CLEAR_LPQ(x) | BIT_LPQ(v))
+#define BIT_SHIFT_HPQ 0
+#define BIT_MASK_HPQ 0xff
+#define BIT_HPQ(x) (((x) & BIT_MASK_HPQ) << BIT_SHIFT_HPQ)
+#define BITS_HPQ (BIT_MASK_HPQ << BIT_SHIFT_HPQ)
+#define BIT_CLEAR_HPQ(x) ((x) & (~BITS_HPQ))
+#define BIT_GET_HPQ(x) (((x) >> BIT_SHIFT_HPQ) & BIT_MASK_HPQ)
+#define BIT_SET_HPQ(x, v) (BIT_CLEAR_HPQ(x) | BIT_HPQ(v))
-/* 2 REG_HMEBOX_E0 (Offset 0x01F0) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_HMEBOX_E0 0
-#define BIT_MASK_HMEBOX_E0 0xffffffffL
-#define BIT_HMEBOX_E0(x) (((x) & BIT_MASK_HMEBOX_E0) << BIT_SHIFT_HMEBOX_E0)
-#define BIT_GET_HMEBOX_E0(x) (((x) >> BIT_SHIFT_HMEBOX_E0) & BIT_MASK_HMEBOX_E0)
+/* 2 REG_FIFOPAGE_CTRL_1 (Offset 0x0200) */
+#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1 0
+#define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1 0xff
+#define BIT_TX_OQT_NL_FREE_SPACE_V1(x) \
+ (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1) \
+ << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1)
+#define BITS_TX_OQT_NL_FREE_SPACE_V1 \
+ (BIT_MASK_TX_OQT_NL_FREE_SPACE_V1 << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1)
+#define BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1(x) \
+ ((x) & (~BITS_TX_OQT_NL_FREE_SPACE_V1))
+#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1(x) \
+ (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1) & \
+ BIT_MASK_TX_OQT_NL_FREE_SPACE_V1)
+#define BIT_SET_TX_OQT_NL_FREE_SPACE_V1(x, v) \
+ (BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1(x) | BIT_TX_OQT_NL_FREE_SPACE_V1(v))
-/* 2 REG_HMEBOX_E1 (Offset 0x01F4) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_HMEBOX_E1 0
-#define BIT_MASK_HMEBOX_E1 0xffffffffL
-#define BIT_HMEBOX_E1(x) (((x) & BIT_MASK_HMEBOX_E1) << BIT_SHIFT_HMEBOX_E1)
-#define BIT_GET_HMEBOX_E1(x) (((x) >> BIT_SHIFT_HMEBOX_E1) & BIT_MASK_HMEBOX_E1)
+/* 2 REG_BCN_CTRL_0 (Offset 0x0200) */
+#define BIT_SHIFT_BCN0_HEAD 0
+#define BIT_MASK_BCN0_HEAD 0xfff
+#define BIT_BCN0_HEAD(x) (((x) & BIT_MASK_BCN0_HEAD) << BIT_SHIFT_BCN0_HEAD)
+#define BITS_BCN0_HEAD (BIT_MASK_BCN0_HEAD << BIT_SHIFT_BCN0_HEAD)
+#define BIT_CLEAR_BCN0_HEAD(x) ((x) & (~BITS_BCN0_HEAD))
+#define BIT_GET_BCN0_HEAD(x) (((x) >> BIT_SHIFT_BCN0_HEAD) & BIT_MASK_BCN0_HEAD)
+#define BIT_SET_BCN0_HEAD(x, v) (BIT_CLEAR_BCN0_HEAD(x) | BIT_BCN0_HEAD(v))
-/* 2 REG_HMEBOX_E2 (Offset 0x01F8) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_HMEBOX_E2 0
-#define BIT_MASK_HMEBOX_E2 0xffffffffL
-#define BIT_HMEBOX_E2(x) (((x) & BIT_MASK_HMEBOX_E2) << BIT_SHIFT_HMEBOX_E2)
-#define BIT_GET_HMEBOX_E2(x) (((x) >> BIT_SHIFT_HMEBOX_E2) & BIT_MASK_HMEBOX_E2)
+/* 2 REG_FIFOPAGE_CTRL_2 (Offset 0x0204) */
+#define BIT_BCN_VALID_1_V1 BIT(31)
-/* 2 REG_HMEBOX_E3 (Offset 0x01FC) */
+#endif
-#define BIT_LD_RQPN BIT(31)
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_HMEBOX_E3 0
-#define BIT_MASK_HMEBOX_E3 0xffffffffL
-#define BIT_HMEBOX_E3(x) (((x) & BIT_MASK_HMEBOX_E3) << BIT_SHIFT_HMEBOX_E3)
-#define BIT_GET_HMEBOX_E3(x) (((x) >> BIT_SHIFT_HMEBOX_E3) & BIT_MASK_HMEBOX_E3)
+/* 2 REG_BCN_CTRL_1 (Offset 0x0204) */
+#define BIT_BCN3_VALID BIT(31)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_FIFOPAGE_INFO (Offset 0x0204) */
+
+#define BIT_SHIFT_TXPKTNUM 24
+#define BIT_MASK_TXPKTNUM 0xff
+#define BIT_TXPKTNUM(x) (((x) & BIT_MASK_TXPKTNUM) << BIT_SHIFT_TXPKTNUM)
+#define BITS_TXPKTNUM (BIT_MASK_TXPKTNUM << BIT_SHIFT_TXPKTNUM)
+#define BIT_CLEAR_TXPKTNUM(x) ((x) & (~BITS_TXPKTNUM))
+#define BIT_GET_TXPKTNUM(x) (((x) >> BIT_SHIFT_TXPKTNUM) & BIT_MASK_TXPKTNUM)
+#define BIT_SET_TXPKTNUM(x, v) (BIT_CLEAR_TXPKTNUM(x) | BIT_TXPKTNUM(v))
-/* 2 REG_RQPN_CTRL_HLPQ (Offset 0x0200) */
+#endif
-#define BIT_EPQ_PUBLIC_DIS BIT(27)
-#define BIT_NPQ_PUBLIC_DIS BIT(26)
-#define BIT_LPQ_PUBLIC_DIS BIT(25)
-#define BIT_HPQ_PUBLIC_DIS BIT(24)
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_PUBQ 16
-#define BIT_MASK_PUBQ 0xff
-#define BIT_PUBQ(x) (((x) & BIT_MASK_PUBQ) << BIT_SHIFT_PUBQ)
-#define BIT_GET_PUBQ(x) (((x) >> BIT_SHIFT_PUBQ) & BIT_MASK_PUBQ)
+/* 2 REG_BCN_CTRL_1 (Offset 0x0204) */
+#define BIT_SHIFT_R_BCN_HEAD_SEL_V1 20
+#define BIT_MASK_R_BCN_HEAD_SEL_V1 0x7
+#define BIT_R_BCN_HEAD_SEL_V1(x) \
+ (((x) & BIT_MASK_R_BCN_HEAD_SEL_V1) << BIT_SHIFT_R_BCN_HEAD_SEL_V1)
+#define BITS_R_BCN_HEAD_SEL_V1 \
+ (BIT_MASK_R_BCN_HEAD_SEL_V1 << BIT_SHIFT_R_BCN_HEAD_SEL_V1)
+#define BIT_CLEAR_R_BCN_HEAD_SEL_V1(x) ((x) & (~BITS_R_BCN_HEAD_SEL_V1))
+#define BIT_GET_R_BCN_HEAD_SEL_V1(x) \
+ (((x) >> BIT_SHIFT_R_BCN_HEAD_SEL_V1) & BIT_MASK_R_BCN_HEAD_SEL_V1)
+#define BIT_SET_R_BCN_HEAD_SEL_V1(x, v) \
+ (BIT_CLEAR_R_BCN_HEAD_SEL_V1(x) | BIT_R_BCN_HEAD_SEL_V1(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FIFOPAGE_INFO (Offset 0x0204) */
+#define BIT_SHIFT_PUBQ_AVAL_PG 16
+#define BIT_MASK_PUBQ_AVAL_PG 0xff
+#define BIT_PUBQ_AVAL_PG(x) \
+ (((x) & BIT_MASK_PUBQ_AVAL_PG) << BIT_SHIFT_PUBQ_AVAL_PG)
+#define BITS_PUBQ_AVAL_PG (BIT_MASK_PUBQ_AVAL_PG << BIT_SHIFT_PUBQ_AVAL_PG)
+#define BIT_CLEAR_PUBQ_AVAL_PG(x) ((x) & (~BITS_PUBQ_AVAL_PG))
+#define BIT_GET_PUBQ_AVAL_PG(x) \
+ (((x) >> BIT_SHIFT_PUBQ_AVAL_PG) & BIT_MASK_PUBQ_AVAL_PG)
+#define BIT_SET_PUBQ_AVAL_PG(x, v) \
+ (BIT_CLEAR_PUBQ_AVAL_PG(x) | BIT_PUBQ_AVAL_PG(v))
-/* 2 REG_FIFOPAGE_CTRL_1 (Offset 0x0200) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1 16
-#define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1 0xff
-#define BIT_TX_OQT_HE_FREE_SPACE_V1(x) (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1) << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1)
-#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1(x) (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1)
+/* 2 REG_FIFOPAGE_CTRL_2 (Offset 0x0204) */
+#define BIT_SHIFT_BCN_HEAD_1_V1 16
+#define BIT_MASK_BCN_HEAD_1_V1 0xfff
+#define BIT_BCN_HEAD_1_V1(x) \
+ (((x) & BIT_MASK_BCN_HEAD_1_V1) << BIT_SHIFT_BCN_HEAD_1_V1)
+#define BITS_BCN_HEAD_1_V1 (BIT_MASK_BCN_HEAD_1_V1 << BIT_SHIFT_BCN_HEAD_1_V1)
+#define BIT_CLEAR_BCN_HEAD_1_V1(x) ((x) & (~BITS_BCN_HEAD_1_V1))
+#define BIT_GET_BCN_HEAD_1_V1(x) \
+ (((x) >> BIT_SHIFT_BCN_HEAD_1_V1) & BIT_MASK_BCN_HEAD_1_V1)
+#define BIT_SET_BCN_HEAD_1_V1(x, v) \
+ (BIT_CLEAR_BCN_HEAD_1_V1(x) | BIT_BCN_HEAD_1_V1(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_BCN_CTRL_1 (Offset 0x0204) */
+#define BIT_SHIFT_BCN3_HEAD 16
+#define BIT_MASK_BCN3_HEAD 0xfff
+#define BIT_BCN3_HEAD(x) (((x) & BIT_MASK_BCN3_HEAD) << BIT_SHIFT_BCN3_HEAD)
+#define BITS_BCN3_HEAD (BIT_MASK_BCN3_HEAD << BIT_SHIFT_BCN3_HEAD)
+#define BIT_CLEAR_BCN3_HEAD(x) ((x) & (~BITS_BCN3_HEAD))
+#define BIT_GET_BCN3_HEAD(x) (((x) >> BIT_SHIFT_BCN3_HEAD) & BIT_MASK_BCN3_HEAD)
+#define BIT_SET_BCN3_HEAD(x, v) (BIT_CLEAR_BCN3_HEAD(x) | BIT_BCN3_HEAD(v))
-/* 2 REG_RQPN_CTRL_HLPQ (Offset 0x0200) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_LPQ 8
-#define BIT_MASK_LPQ 0xff
-#define BIT_LPQ(x) (((x) & BIT_MASK_LPQ) << BIT_SHIFT_LPQ)
-#define BIT_GET_LPQ(x) (((x) >> BIT_SHIFT_LPQ) & BIT_MASK_LPQ)
+/* 2 REG_FIFOPAGE_CTRL_2 (Offset 0x0204) */
+#define BIT_BCN_VALID_V1 BIT(15)
-#define BIT_SHIFT_HPQ 0
-#define BIT_MASK_HPQ 0xff
-#define BIT_HPQ(x) (((x) & BIT_MASK_HPQ) << BIT_SHIFT_HPQ)
-#define BIT_GET_HPQ(x) (((x) >> BIT_SHIFT_HPQ) & BIT_MASK_HPQ)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_BCN_CTRL_1 (Offset 0x0204) */
+#define BIT_BCN2_VALID BIT(15)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_FIFOPAGE_CTRL_1 (Offset 0x0200) */
+/* 2 REG_FIFOPAGE_INFO (Offset 0x0204) */
+#define BIT_SHIFT_LPQ_AVAL_PG 8
+#define BIT_MASK_LPQ_AVAL_PG 0xff
+#define BIT_LPQ_AVAL_PG(x) \
+ (((x) & BIT_MASK_LPQ_AVAL_PG) << BIT_SHIFT_LPQ_AVAL_PG)
+#define BITS_LPQ_AVAL_PG (BIT_MASK_LPQ_AVAL_PG << BIT_SHIFT_LPQ_AVAL_PG)
+#define BIT_CLEAR_LPQ_AVAL_PG(x) ((x) & (~BITS_LPQ_AVAL_PG))
+#define BIT_GET_LPQ_AVAL_PG(x) \
+ (((x) >> BIT_SHIFT_LPQ_AVAL_PG) & BIT_MASK_LPQ_AVAL_PG)
+#define BIT_SET_LPQ_AVAL_PG(x, v) \
+ (BIT_CLEAR_LPQ_AVAL_PG(x) | BIT_LPQ_AVAL_PG(v))
-#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1 0
-#define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1 0xff
-#define BIT_TX_OQT_NL_FREE_SPACE_V1(x) (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1) << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1)
-#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1(x) (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_FIFOPAGE_CTRL_2 (Offset 0x0204) */
+/* 2 REG_BCN_CTRL_1 (Offset 0x0204) */
-#define BIT_BCN_VALID_1_V1 BIT(31)
+#define BIT_TDE_ERROR_STOP BIT(3)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_FIFOPAGE_INFO (Offset 0x0204) */
-
-#define BIT_SHIFT_TXPKTNUM 24
-#define BIT_MASK_TXPKTNUM 0xff
-#define BIT_TXPKTNUM(x) (((x) & BIT_MASK_TXPKTNUM) << BIT_SHIFT_TXPKTNUM)
-#define BIT_GET_TXPKTNUM(x) (((x) >> BIT_SHIFT_TXPKTNUM) & BIT_MASK_TXPKTNUM)
-
-
-#define BIT_SHIFT_PUBQ_AVAL_PG 16
-#define BIT_MASK_PUBQ_AVAL_PG 0xff
-#define BIT_PUBQ_AVAL_PG(x) (((x) & BIT_MASK_PUBQ_AVAL_PG) << BIT_SHIFT_PUBQ_AVAL_PG)
-#define BIT_GET_PUBQ_AVAL_PG(x) (((x) >> BIT_SHIFT_PUBQ_AVAL_PG) & BIT_MASK_PUBQ_AVAL_PG)
-
+#define BIT_SHIFT_HPQ_AVAL_PG 0
+#define BIT_MASK_HPQ_AVAL_PG 0xff
+#define BIT_HPQ_AVAL_PG(x) \
+ (((x) & BIT_MASK_HPQ_AVAL_PG) << BIT_SHIFT_HPQ_AVAL_PG)
+#define BITS_HPQ_AVAL_PG (BIT_MASK_HPQ_AVAL_PG << BIT_SHIFT_HPQ_AVAL_PG)
+#define BIT_CLEAR_HPQ_AVAL_PG(x) ((x) & (~BITS_HPQ_AVAL_PG))
+#define BIT_GET_HPQ_AVAL_PG(x) \
+ (((x) >> BIT_SHIFT_HPQ_AVAL_PG) & BIT_MASK_HPQ_AVAL_PG)
+#define BIT_SET_HPQ_AVAL_PG(x, v) \
+ (BIT_CLEAR_HPQ_AVAL_PG(x) | BIT_HPQ_AVAL_PG(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FIFOPAGE_CTRL_2 (Offset 0x0204) */
+#define BIT_SHIFT_BCN_HEAD_V1 0
+#define BIT_MASK_BCN_HEAD_V1 0xfff
+#define BIT_BCN_HEAD_V1(x) \
+ (((x) & BIT_MASK_BCN_HEAD_V1) << BIT_SHIFT_BCN_HEAD_V1)
+#define BITS_BCN_HEAD_V1 (BIT_MASK_BCN_HEAD_V1 << BIT_SHIFT_BCN_HEAD_V1)
+#define BIT_CLEAR_BCN_HEAD_V1(x) ((x) & (~BITS_BCN_HEAD_V1))
+#define BIT_GET_BCN_HEAD_V1(x) \
+ (((x) >> BIT_SHIFT_BCN_HEAD_V1) & BIT_MASK_BCN_HEAD_V1)
+#define BIT_SET_BCN_HEAD_V1(x, v) \
+ (BIT_CLEAR_BCN_HEAD_V1(x) | BIT_BCN_HEAD_V1(v))
-/* 2 REG_FIFOPAGE_CTRL_2 (Offset 0x0204) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_BCN_HEAD_1_V1 16
-#define BIT_MASK_BCN_HEAD_1_V1 0xfff
-#define BIT_BCN_HEAD_1_V1(x) (((x) & BIT_MASK_BCN_HEAD_1_V1) << BIT_SHIFT_BCN_HEAD_1_V1)
-#define BIT_GET_BCN_HEAD_1_V1(x) (((x) >> BIT_SHIFT_BCN_HEAD_1_V1) & BIT_MASK_BCN_HEAD_1_V1)
+/* 2 REG_BCN_CTRL_1 (Offset 0x0204) */
-#define BIT_BCN_VALID_V1 BIT(15)
+#define BIT_SHIFT_BCN2_HEAD 0
+#define BIT_MASK_BCN2_HEAD 0xfff
+#define BIT_BCN2_HEAD(x) (((x) & BIT_MASK_BCN2_HEAD) << BIT_SHIFT_BCN2_HEAD)
+#define BITS_BCN2_HEAD (BIT_MASK_BCN2_HEAD << BIT_SHIFT_BCN2_HEAD)
+#define BIT_CLEAR_BCN2_HEAD(x) ((x) & (~BITS_BCN2_HEAD))
+#define BIT_GET_BCN2_HEAD(x) (((x) >> BIT_SHIFT_BCN2_HEAD) & BIT_MASK_BCN2_HEAD)
+#define BIT_SET_BCN2_HEAD(x, v) (BIT_CLEAR_BCN2_HEAD(x) | BIT_BCN2_HEAD(v))
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_DWBCN0_CTRL (Offset 0x0208) */
-/* 2 REG_FIFOPAGE_INFO (Offset 0x0204) */
-
+#define BIT_SHIFT_LLT_FREE_PAGE 24
+#define BIT_MASK_LLT_FREE_PAGE 0xff
+#define BIT_LLT_FREE_PAGE(x) \
+ (((x) & BIT_MASK_LLT_FREE_PAGE) << BIT_SHIFT_LLT_FREE_PAGE)
+#define BITS_LLT_FREE_PAGE (BIT_MASK_LLT_FREE_PAGE << BIT_SHIFT_LLT_FREE_PAGE)
+#define BIT_CLEAR_LLT_FREE_PAGE(x) ((x) & (~BITS_LLT_FREE_PAGE))
+#define BIT_GET_LLT_FREE_PAGE(x) \
+ (((x) >> BIT_SHIFT_LLT_FREE_PAGE) & BIT_MASK_LLT_FREE_PAGE)
+#define BIT_SET_LLT_FREE_PAGE(x, v) \
+ (BIT_CLEAR_LLT_FREE_PAGE(x) | BIT_LLT_FREE_PAGE(v))
-#define BIT_SHIFT_LPQ_AVAL_PG 8
-#define BIT_MASK_LPQ_AVAL_PG 0xff
-#define BIT_LPQ_AVAL_PG(x) (((x) & BIT_MASK_LPQ_AVAL_PG) << BIT_SHIFT_LPQ_AVAL_PG)
-#define BIT_GET_LPQ_AVAL_PG(x) (((x) >> BIT_SHIFT_LPQ_AVAL_PG) & BIT_MASK_LPQ_AVAL_PG)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_HPQ_AVAL_PG 0
-#define BIT_MASK_HPQ_AVAL_PG 0xff
-#define BIT_HPQ_AVAL_PG(x) (((x) & BIT_MASK_HPQ_AVAL_PG) << BIT_SHIFT_HPQ_AVAL_PG)
-#define BIT_GET_HPQ_AVAL_PG(x) (((x) >> BIT_SHIFT_HPQ_AVAL_PG) & BIT_MASK_HPQ_AVAL_PG)
+/* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */
+#define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1 24
+#define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1 0xff
+#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x) \
+ (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1) \
+ << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1)
+#define BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1 \
+ (BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1 \
+ << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1)
+#define BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x) \
+ ((x) & (~BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1))
+#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x) \
+ (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1) & \
+ BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1)
+#define BIT_SET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x, v) \
+ (BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x) | \
+ BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(v))
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */
+#define BIT_SHIFT_MAX_TX_PKT_V1 24
+#define BIT_MASK_MAX_TX_PKT_V1 0xff
+#define BIT_MAX_TX_PKT_V1(x) \
+ (((x) & BIT_MASK_MAX_TX_PKT_V1) << BIT_SHIFT_MAX_TX_PKT_V1)
+#define BITS_MAX_TX_PKT_V1 (BIT_MASK_MAX_TX_PKT_V1 << BIT_SHIFT_MAX_TX_PKT_V1)
+#define BIT_CLEAR_MAX_TX_PKT_V1(x) ((x) & (~BITS_MAX_TX_PKT_V1))
+#define BIT_GET_MAX_TX_PKT_V1(x) \
+ (((x) >> BIT_SHIFT_MAX_TX_PKT_V1) & BIT_MASK_MAX_TX_PKT_V1)
+#define BIT_SET_MAX_TX_PKT_V1(x, v) \
+ (BIT_CLEAR_MAX_TX_PKT_V1(x) | BIT_MAX_TX_PKT_V1(v))
-/* 2 REG_FIFOPAGE_CTRL_2 (Offset 0x0204) */
+#endif
+#if (HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_BCN_HEAD_V1 0
-#define BIT_MASK_BCN_HEAD_V1 0xfff
-#define BIT_BCN_HEAD_V1(x) (((x) & BIT_MASK_BCN_HEAD_V1) << BIT_SHIFT_BCN_HEAD_V1)
-#define BIT_GET_BCN_HEAD_V1(x) (((x) >> BIT_SHIFT_BCN_HEAD_V1) & BIT_MASK_BCN_HEAD_V1)
+/* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */
+#define BIT_TDE_ERROR_STOP_V1 BIT(23)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_DWBCN0_CTRL (Offset 0x0208) */
+#define BIT_BCN_VALID BIT(16)
-#define BIT_SHIFT_LLT_FREE_PAGE 24
-#define BIT_MASK_LLT_FREE_PAGE 0xff
-#define BIT_LLT_FREE_PAGE(x) (((x) & BIT_MASK_LLT_FREE_PAGE) << BIT_SHIFT_LLT_FREE_PAGE)
-#define BIT_GET_LLT_FREE_PAGE(x) (((x) >> BIT_SHIFT_LLT_FREE_PAGE) & BIT_MASK_LLT_FREE_PAGE)
-
+#define BIT_SHIFT_BCN_HEAD 8
+#define BIT_MASK_BCN_HEAD 0xff
+#define BIT_BCN_HEAD(x) (((x) & BIT_MASK_BCN_HEAD) << BIT_SHIFT_BCN_HEAD)
+#define BITS_BCN_HEAD (BIT_MASK_BCN_HEAD << BIT_SHIFT_BCN_HEAD)
+#define BIT_CLEAR_BCN_HEAD(x) ((x) & (~BITS_BCN_HEAD))
+#define BIT_GET_BCN_HEAD(x) (((x) >> BIT_SHIFT_BCN_HEAD) & BIT_MASK_BCN_HEAD)
+#define BIT_SET_BCN_HEAD(x, v) (BIT_CLEAR_BCN_HEAD(x) | BIT_BCN_HEAD(v))
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
/* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */
-
-#define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1 24
-#define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1 0xff
-#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x) (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1) << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1)
-#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x) (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1)
-
+#define BIT_SHIFT_LLT_FREE_PAGE_V1 8
+#define BIT_MASK_LLT_FREE_PAGE_V1 0xffff
+#define BIT_LLT_FREE_PAGE_V1(x) \
+ (((x) & BIT_MASK_LLT_FREE_PAGE_V1) << BIT_SHIFT_LLT_FREE_PAGE_V1)
+#define BITS_LLT_FREE_PAGE_V1 \
+ (BIT_MASK_LLT_FREE_PAGE_V1 << BIT_SHIFT_LLT_FREE_PAGE_V1)
+#define BIT_CLEAR_LLT_FREE_PAGE_V1(x) ((x) & (~BITS_LLT_FREE_PAGE_V1))
+#define BIT_GET_LLT_FREE_PAGE_V1(x) \
+ (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1) & BIT_MASK_LLT_FREE_PAGE_V1)
+#define BIT_SET_LLT_FREE_PAGE_V1(x, v) \
+ (BIT_CLEAR_LLT_FREE_PAGE_V1(x) | BIT_LLT_FREE_PAGE_V1(v))
#endif
+#if (HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */
+#define BIT_SHIFT_LLT_FREE_PAGE_V2 8
+#define BIT_MASK_LLT_FREE_PAGE_V2 0xfff
+#define BIT_LLT_FREE_PAGE_V2(x) \
+ (((x) & BIT_MASK_LLT_FREE_PAGE_V2) << BIT_SHIFT_LLT_FREE_PAGE_V2)
+#define BITS_LLT_FREE_PAGE_V2 \
+ (BIT_MASK_LLT_FREE_PAGE_V2 << BIT_SHIFT_LLT_FREE_PAGE_V2)
+#define BIT_CLEAR_LLT_FREE_PAGE_V2(x) ((x) & (~BITS_LLT_FREE_PAGE_V2))
+#define BIT_GET_LLT_FREE_PAGE_V2(x) \
+ (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V2) & BIT_MASK_LLT_FREE_PAGE_V2)
+#define BIT_SET_LLT_FREE_PAGE_V2(x, v) \
+ (BIT_CLEAR_LLT_FREE_PAGE_V2(x) | BIT_LLT_FREE_PAGE_V2(v))
-/* 2 REG_DWBCN0_CTRL (Offset 0x0208) */
+#endif
-#define BIT_BCN_VALID BIT(16)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_BCN_HEAD 8
-#define BIT_MASK_BCN_HEAD 0xff
-#define BIT_BCN_HEAD(x) (((x) & BIT_MASK_BCN_HEAD) << BIT_SHIFT_BCN_HEAD)
-#define BIT_GET_BCN_HEAD(x) (((x) >> BIT_SHIFT_BCN_HEAD) & BIT_MASK_BCN_HEAD)
+/* 2 REG_DWBCN0_CTRL (Offset 0x0208) */
+#define BIT_SHIFT_BLK_DESC_NUM 4
+#define BIT_MASK_BLK_DESC_NUM 0xf
+#define BIT_BLK_DESC_NUM(x) \
+ (((x) & BIT_MASK_BLK_DESC_NUM) << BIT_SHIFT_BLK_DESC_NUM)
+#define BITS_BLK_DESC_NUM (BIT_MASK_BLK_DESC_NUM << BIT_SHIFT_BLK_DESC_NUM)
+#define BIT_CLEAR_BLK_DESC_NUM(x) ((x) & (~BITS_BLK_DESC_NUM))
+#define BIT_GET_BLK_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_BLK_DESC_NUM) & BIT_MASK_BLK_DESC_NUM)
+#define BIT_SET_BLK_DESC_NUM(x, v) \
+ (BIT_CLEAR_BLK_DESC_NUM(x) | BIT_BLK_DESC_NUM(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */
+#define BIT_R_BCN_HEAD_SEL BIT(3)
-/* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_LLT_FREE_PAGE_V1 8
-#define BIT_MASK_LLT_FREE_PAGE_V1 0xffff
-#define BIT_LLT_FREE_PAGE_V1(x) (((x) & BIT_MASK_LLT_FREE_PAGE_V1) << BIT_SHIFT_LLT_FREE_PAGE_V1)
-#define BIT_GET_LLT_FREE_PAGE_V1(x) (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1) & BIT_MASK_LLT_FREE_PAGE_V1)
+/* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */
+#define BIT_R_EN_BCN_SW_HEAD_SEL BIT(2)
+#define BIT_LLT_DBG_SEL BIT(1)
+#define BIT_AUTO_INIT_LLT_V1 BIT(0)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8814AMP_SUPPORT)
+/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */
+#define BIT_EM_CHKSUM_FIN BIT(31)
+#define BIT_EMN_PCIE_DMA_MOD BIT(30)
-/* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_LLT_FREE_PAGE_V2 8
-#define BIT_MASK_LLT_FREE_PAGE_V2 0xfff
-#define BIT_LLT_FREE_PAGE_V2(x) (((x) & BIT_MASK_LLT_FREE_PAGE_V2) << BIT_SHIFT_LLT_FREE_PAGE_V2)
-#define BIT_GET_LLT_FREE_PAGE_V2(x) (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V2) & BIT_MASK_LLT_FREE_PAGE_V2)
+/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */
+#define BIT_EN_TXQUE_CLR BIT(29)
+#define BIT_EN_PCIE_FIFO_MODE BIT(28)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */
+#define BIT_SHIFT_PG_UNDER_TH 16
+#define BIT_MASK_PG_UNDER_TH 0xff
+#define BIT_PG_UNDER_TH(x) \
+ (((x) & BIT_MASK_PG_UNDER_TH) << BIT_SHIFT_PG_UNDER_TH)
+#define BITS_PG_UNDER_TH (BIT_MASK_PG_UNDER_TH << BIT_SHIFT_PG_UNDER_TH)
+#define BIT_CLEAR_PG_UNDER_TH(x) ((x) & (~BITS_PG_UNDER_TH))
+#define BIT_GET_PG_UNDER_TH(x) \
+ (((x) >> BIT_SHIFT_PG_UNDER_TH) & BIT_MASK_PG_UNDER_TH)
+#define BIT_SET_PG_UNDER_TH(x, v) \
+ (BIT_CLEAR_PG_UNDER_TH(x) | BIT_PG_UNDER_TH(v))
-/* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_BLK_DESC_NUM 4
-#define BIT_MASK_BLK_DESC_NUM 0xf
-#define BIT_BLK_DESC_NUM(x) (((x) & BIT_MASK_BLK_DESC_NUM) << BIT_SHIFT_BLK_DESC_NUM)
-#define BIT_GET_BLK_DESC_NUM(x) (((x) >> BIT_SHIFT_BLK_DESC_NUM) & BIT_MASK_BLK_DESC_NUM)
+/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */
+#define BIT_SHIFT_PG_UNDER_TH_V1 16
+#define BIT_MASK_PG_UNDER_TH_V1 0xfff
+#define BIT_PG_UNDER_TH_V1(x) \
+ (((x) & BIT_MASK_PG_UNDER_TH_V1) << BIT_SHIFT_PG_UNDER_TH_V1)
+#define BITS_PG_UNDER_TH_V1 \
+ (BIT_MASK_PG_UNDER_TH_V1 << BIT_SHIFT_PG_UNDER_TH_V1)
+#define BIT_CLEAR_PG_UNDER_TH_V1(x) ((x) & (~BITS_PG_UNDER_TH_V1))
+#define BIT_GET_PG_UNDER_TH_V1(x) \
+ (((x) >> BIT_SHIFT_PG_UNDER_TH_V1) & BIT_MASK_PG_UNDER_TH_V1)
+#define BIT_SET_PG_UNDER_TH_V1(x, v) \
+ (BIT_CLEAR_PG_UNDER_TH_V1(x) | BIT_PG_UNDER_TH_V1(v))
#endif
+#if (HALMAC_8197F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */
+#define BIT_EN_RESET_RESTORE_H2C BIT(15)
-/* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */
+#endif
-#define BIT_R_BCN_HEAD_SEL BIT(3)
-#define BIT_R_EN_BCN_SW_HEAD_SEL BIT(2)
-#define BIT_LLT_DBG_SEL BIT(1)
-#define BIT_AUTO_INIT_LLT_V1 BIT(0)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */
+#define BIT_R_EN_RESET_RESTORE_H2C BIT(15)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8822B_SUPPORT)
/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */
-#define BIT_EM_CHKSUM_FIN BIT(31)
-#define BIT_EMN_PCIE_DMA_MOD BIT(30)
+#define BIT_RESTORE_H2C_ADDRESS BIT(15)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */
-#define BIT_EN_TXQUE_CLR BIT(29)
-#define BIT_EN_PCIE_FIFO_MODE BIT(28)
+#define BIT_SDIO_TDE_FINISH BIT(14)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */
+#define BIT_SDIO_TXDESC_CHKSUM_EN BIT(13)
+#define BIT_RST_RDPTR BIT(12)
+#define BIT_RST_WRPTR BIT(11)
+#define BIT_CHK_PG_TH_EN BIT(10)
+#define BIT_DROP_DATA_EN BIT(9)
+#define BIT_CHECK_OFFSET_EN BIT(8)
-#define BIT_SHIFT_PG_UNDER_TH 16
-#define BIT_MASK_PG_UNDER_TH 0xff
-#define BIT_PG_UNDER_TH(x) (((x) & BIT_MASK_PG_UNDER_TH) << BIT_SHIFT_PG_UNDER_TH)
-#define BIT_GET_PG_UNDER_TH(x) (((x) >> BIT_SHIFT_PG_UNDER_TH) & BIT_MASK_PG_UNDER_TH)
-
+#define BIT_SHIFT_CHECK_OFFSET 0
+#define BIT_MASK_CHECK_OFFSET 0xff
+#define BIT_CHECK_OFFSET(x) \
+ (((x) & BIT_MASK_CHECK_OFFSET) << BIT_SHIFT_CHECK_OFFSET)
+#define BITS_CHECK_OFFSET (BIT_MASK_CHECK_OFFSET << BIT_SHIFT_CHECK_OFFSET)
+#define BIT_CLEAR_CHECK_OFFSET(x) ((x) & (~BITS_CHECK_OFFSET))
+#define BIT_GET_CHECK_OFFSET(x) \
+ (((x) >> BIT_SHIFT_CHECK_OFFSET) & BIT_MASK_CHECK_OFFSET)
+#define BIT_SET_CHECK_OFFSET(x, v) \
+ (BIT_CLEAR_CHECK_OFFSET(x) | BIT_CHECK_OFFSET(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_TXDMA_STATUS (Offset 0x0210) */
+#define BIT_AMSDU_PKT_SIZE_ERR BIT(31)
+#define BIT_AMSDU_EN_ERR BIT(30)
+#define BIT_CHKSUM_AMSDU_EN_ERR BIT(29)
+#define BIT_TXPKTBF_REQ_ERR BIT(28)
+#define BIT_OQT_UDN_16 BIT(27)
+#define BIT_OQT_OVF_16 BIT(26)
+#define BIT_OQT_UDN_14_15 BIT(25)
+#define BIT_OQT_OVF_14_15 BIT(24)
+#define BIT_OQT_UDN_13 BIT(23)
+#define BIT_OQT_OVF_13 BIT(22)
+#define BIT_OQT_UDN_12 BIT(21)
+#define BIT_OQT_OVF_12 BIT(20)
+#define BIT_OQT_UDN_8_11 BIT(19)
+#define BIT_OQT_OVF_8_11 BIT(18)
-/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */
+#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_PG_UNDER_TH_V1 16
-#define BIT_MASK_PG_UNDER_TH_V1 0xfff
-#define BIT_PG_UNDER_TH_V1(x) (((x) & BIT_MASK_PG_UNDER_TH_V1) << BIT_SHIFT_PG_UNDER_TH_V1)
-#define BIT_GET_PG_UNDER_TH_V1(x) (((x) >> BIT_SHIFT_PG_UNDER_TH_V1) & BIT_MASK_PG_UNDER_TH_V1)
+/* 2 REG_TXDMA_STATUS (Offset 0x0210) */
+#define BIT_TXPKTBUF_REQ_ERR BIT(18)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
-
-/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */
+/* 2 REG_TXDMA_STATUS (Offset 0x0210) */
-#define BIT_EN_RESET_RESTORE_H2C BIT(15)
+#define BIT_HI_OQT_UDN BIT(17)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8822B_SUPPORT)
+/* 2 REG_TXDMA_STATUS (Offset 0x0210) */
+#define BIT_OQT_UDN_4_7 BIT(17)
-/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */
+#endif
-#define BIT_RESTORE_H2C_ADDRESS BIT(15)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_TXDMA_STATUS (Offset 0x0210) */
+#define BIT_HI_OQT_OVF BIT(16)
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */
+/* 2 REG_TXDMA_STATUS (Offset 0x0210) */
-#define BIT_SDIO_TDE_FINISH BIT(14)
+#define BIT_OQT_OVF_4_7 BIT(16)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_TXDMA_STATUS (Offset 0x0210) */
+#define BIT_PAYLOAD_CHKSUM_ERR BIT(15)
-/* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */
+#endif
-#define BIT_SDIO_TXDESC_CHKSUM_EN BIT(13)
-#define BIT_RST_RDPTR BIT(12)
-#define BIT_RST_WRPTR BIT(11)
-#define BIT_CHK_PG_TH_EN BIT(10)
-#define BIT_DROP_DATA_EN BIT(9)
-#define BIT_CHECK_OFFSET_EN BIT(8)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_CHECK_OFFSET 0
-#define BIT_MASK_CHECK_OFFSET 0xff
-#define BIT_CHECK_OFFSET(x) (((x) & BIT_MASK_CHECK_OFFSET) << BIT_SHIFT_CHECK_OFFSET)
-#define BIT_GET_CHECK_OFFSET(x) (((x) >> BIT_SHIFT_CHECK_OFFSET) & BIT_MASK_CHECK_OFFSET)
+/* 2 REG_TXDMA_STATUS (Offset 0x0210) */
+#define BIT_RX_CLOSE_EN BIT(15)
#endif
-
-#if (HALMAC_8821C_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_TXDMA_STATUS (Offset 0x0210) */
-#define BIT_TXPKTBUF_REQ_ERR BIT(18)
+#define BIT_PAYLOAD_UDN BIT(14)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_TXDMA_STATUS (Offset 0x0210) */
-#define BIT_HI_OQT_UDN BIT(17)
-#define BIT_HI_OQT_OVF BIT(16)
-#define BIT_PAYLOAD_CHKSUM_ERR BIT(15)
-#define BIT_PAYLOAD_UDN BIT(14)
-#define BIT_PAYLOAD_OVF BIT(13)
-#define BIT_DSC_CHKSUM_FAIL BIT(12)
-#define BIT_UNKNOWN_QSEL BIT(11)
-#define BIT_EP_QSEL_DIFF BIT(10)
-#define BIT_TX_OFFS_UNMATCH BIT(9)
-#define BIT_TXOQT_UDN BIT(8)
-#define BIT_TXOQT_OVF BIT(7)
-#define BIT_TXDMA_SFF_UDN BIT(6)
-#define BIT_TXDMA_SFF_OVF BIT(5)
-#define BIT_LLT_NULL_PG BIT(4)
-#define BIT_PAGE_UDN BIT(3)
-#define BIT_PAGE_OVF BIT(2)
-#define BIT_TXFF_PG_UDN BIT(1)
-#define BIT_TXFF_PG_OVF BIT(0)
+#define BIT_STOP_BCNQ BIT(14)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-
-/* 2 REG_RQPN_NPQ (Offset 0x0214) */
+/* 2 REG_TXDMA_STATUS (Offset 0x0210) */
+#define BIT_PAYLOAD_OVF BIT(13)
-#define BIT_SHIFT_EXQ_AVAL_PG 24
-#define BIT_MASK_EXQ_AVAL_PG 0xff
-#define BIT_EXQ_AVAL_PG(x) (((x) & BIT_MASK_EXQ_AVAL_PG) << BIT_SHIFT_EXQ_AVAL_PG)
-#define BIT_GET_EXQ_AVAL_PG(x) (((x) >> BIT_SHIFT_EXQ_AVAL_PG) & BIT_MASK_EXQ_AVAL_PG)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_EXQ 16
-#define BIT_MASK_EXQ 0xff
-#define BIT_EXQ(x) (((x) & BIT_MASK_EXQ) << BIT_SHIFT_EXQ)
-#define BIT_GET_EXQ(x) (((x) >> BIT_SHIFT_EXQ) & BIT_MASK_EXQ)
+/* 2 REG_TXDMA_STATUS (Offset 0x0210) */
+#define BIT_STOP_MGQ BIT(13)
-#define BIT_SHIFT_NPQ 0
-#define BIT_MASK_NPQ 0xff
-#define BIT_NPQ(x) (((x) & BIT_MASK_NPQ) << BIT_SHIFT_NPQ)
-#define BIT_GET_NPQ(x) (((x) >> BIT_SHIFT_NPQ) & BIT_MASK_NPQ)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-/* 2 REG_TQPNT1 (Offset 0x0218) */
+/* 2 REG_TXDMA_STATUS (Offset 0x0210) */
+#define BIT_DSC_CHKSUM_FAIL BIT(12)
-#define BIT_SHIFT_NPQ_HIGH_TH 24
-#define BIT_MASK_NPQ_HIGH_TH 0xff
-#define BIT_NPQ_HIGH_TH(x) (((x) & BIT_MASK_NPQ_HIGH_TH) << BIT_SHIFT_NPQ_HIGH_TH)
-#define BIT_GET_NPQ_HIGH_TH(x) (((x) >> BIT_SHIFT_NPQ_HIGH_TH) & BIT_MASK_NPQ_HIGH_TH)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_NPQ_LOW_TH 16
-#define BIT_MASK_NPQ_LOW_TH 0xff
-#define BIT_NPQ_LOW_TH(x) (((x) & BIT_MASK_NPQ_LOW_TH) << BIT_SHIFT_NPQ_LOW_TH)
-#define BIT_GET_NPQ_LOW_TH(x) (((x) >> BIT_SHIFT_NPQ_LOW_TH) & BIT_MASK_NPQ_LOW_TH)
+/* 2 REG_TXDMA_STATUS (Offset 0x0210) */
+#define BIT_STOP_VOQ BIT(12)
+#define BIT_UNKNOWN_QSEL BIT(11)
+#define BIT_STOP_VIQ BIT(11)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_TXDMA_STATUS (Offset 0x0210) */
+#define BIT_EP_QSEL_DIFF BIT(10)
-/* 2 REG_TQPNT1 (Offset 0x0218) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_HPQ_HIGH_TH_V1 16
-#define BIT_MASK_HPQ_HIGH_TH_V1 0xfff
-#define BIT_HPQ_HIGH_TH_V1(x) (((x) & BIT_MASK_HPQ_HIGH_TH_V1) << BIT_SHIFT_HPQ_HIGH_TH_V1)
-#define BIT_GET_HPQ_HIGH_TH_V1(x) (((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1) & BIT_MASK_HPQ_HIGH_TH_V1)
+/* 2 REG_TXDMA_STATUS (Offset 0x0210) */
+#define BIT_STOP_BEQ BIT(10)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-
-/* 2 REG_TQPNT1 (Offset 0x0218) */
+/* 2 REG_TXDMA_STATUS (Offset 0x0210) */
+#define BIT_TX_OFFS_UNMATCH BIT(9)
-#define BIT_SHIFT_HPQ_HIGH_TH 8
-#define BIT_MASK_HPQ_HIGH_TH 0xff
-#define BIT_HPQ_HIGH_TH(x) (((x) & BIT_MASK_HPQ_HIGH_TH) << BIT_SHIFT_HPQ_HIGH_TH)
-#define BIT_GET_HPQ_HIGH_TH(x) (((x) >> BIT_SHIFT_HPQ_HIGH_TH) & BIT_MASK_HPQ_HIGH_TH)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_HPQ_LOW_TH 0
-#define BIT_MASK_HPQ_LOW_TH 0xff
-#define BIT_HPQ_LOW_TH(x) (((x) & BIT_MASK_HPQ_LOW_TH) << BIT_SHIFT_HPQ_LOW_TH)
-#define BIT_GET_HPQ_LOW_TH(x) (((x) >> BIT_SHIFT_HPQ_LOW_TH) & BIT_MASK_HPQ_LOW_TH)
+/* 2 REG_TXDMA_STATUS (Offset 0x0210) */
+#define BIT_STOP_BKQ BIT(9)
+#define BIT_TXOQT_UDN BIT(8)
+#define BIT_STOP_RXQ BIT(8)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_TXDMA_STATUS (Offset 0x0210) */
+#define BIT_TXOQT_UDN_0_3 BIT(8)
-/* 2 REG_TQPNT1 (Offset 0x0218) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_HPQ_LOW_TH_V1 0
-#define BIT_MASK_HPQ_LOW_TH_V1 0xfff
-#define BIT_HPQ_LOW_TH_V1(x) (((x) & BIT_MASK_HPQ_LOW_TH_V1) << BIT_SHIFT_HPQ_LOW_TH_V1)
-#define BIT_GET_HPQ_LOW_TH_V1(x) (((x) >> BIT_SHIFT_HPQ_LOW_TH_V1) & BIT_MASK_HPQ_LOW_TH_V1)
+/* 2 REG_TXDMA_STATUS (Offset 0x0210) */
+#define BIT_TXOQT_OVF BIT(7)
+#define BIT_STOP_HI7Q BIT(7)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-
-/* 2 REG_TQPNT2 (Offset 0x021C) */
+/* 2 REG_TXDMA_STATUS (Offset 0x0210) */
+#define BIT_TXOQT_OVF_0_3 BIT(7)
-#define BIT_SHIFT_EXQ_HIGH_TH 24
-#define BIT_MASK_EXQ_HIGH_TH 0xff
-#define BIT_EXQ_HIGH_TH(x) (((x) & BIT_MASK_EXQ_HIGH_TH) << BIT_SHIFT_EXQ_HIGH_TH)
-#define BIT_GET_EXQ_HIGH_TH(x) (((x) >> BIT_SHIFT_EXQ_HIGH_TH) & BIT_MASK_EXQ_HIGH_TH)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_EXQ_LOW_TH 16
-#define BIT_MASK_EXQ_LOW_TH 0xff
-#define BIT_EXQ_LOW_TH(x) (((x) & BIT_MASK_EXQ_LOW_TH) << BIT_SHIFT_EXQ_LOW_TH)
-#define BIT_GET_EXQ_LOW_TH(x) (((x) >> BIT_SHIFT_EXQ_LOW_TH) & BIT_MASK_EXQ_LOW_TH)
+/* 2 REG_TXDMA_STATUS (Offset 0x0210) */
+#define BIT_TXDMA_SFF_UDN BIT(6)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_TXDMA_STATUS (Offset 0x0210) */
+#define BIT_STOP_HI6Q BIT(6)
-/* 2 REG_TQPNT2 (Offset 0x021C) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_NPQ_HIGH_TH_V1 16
-#define BIT_MASK_NPQ_HIGH_TH_V1 0xfff
-#define BIT_NPQ_HIGH_TH_V1(x) (((x) & BIT_MASK_NPQ_HIGH_TH_V1) << BIT_SHIFT_NPQ_HIGH_TH_V1)
-#define BIT_GET_NPQ_HIGH_TH_V1(x) (((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1) & BIT_MASK_NPQ_HIGH_TH_V1)
+/* 2 REG_TXDMA_STATUS (Offset 0x0210) */
+#define BIT_TXDMA_SFF_OVF BIT(5)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-
-/* 2 REG_TQPNT2 (Offset 0x021C) */
+/* 2 REG_TXDMA_STATUS (Offset 0x0210) */
+#define BIT_STOP_HI5Q BIT(5)
-#define BIT_SHIFT_LPQ_HIGH_TH 8
-#define BIT_MASK_LPQ_HIGH_TH 0xff
-#define BIT_LPQ_HIGH_TH(x) (((x) & BIT_MASK_LPQ_HIGH_TH) << BIT_SHIFT_LPQ_HIGH_TH)
-#define BIT_GET_LPQ_HIGH_TH(x) (((x) >> BIT_SHIFT_LPQ_HIGH_TH) & BIT_MASK_LPQ_HIGH_TH)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_LPQ_LOW_TH 0
-#define BIT_MASK_LPQ_LOW_TH 0xff
-#define BIT_LPQ_LOW_TH(x) (((x) & BIT_MASK_LPQ_LOW_TH) << BIT_SHIFT_LPQ_LOW_TH)
-#define BIT_GET_LPQ_LOW_TH(x) (((x) >> BIT_SHIFT_LPQ_LOW_TH) & BIT_MASK_LPQ_LOW_TH)
+/* 2 REG_TXDMA_STATUS (Offset 0x0210) */
+#define BIT_LLT_NULL_PG BIT(4)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_TXDMA_STATUS (Offset 0x0210) */
+#define BIT_STOP_HI4Q BIT(4)
-/* 2 REG_TQPNT2 (Offset 0x021C) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_NPQ_LOW_TH_V1 0
-#define BIT_MASK_NPQ_LOW_TH_V1 0xfff
-#define BIT_NPQ_LOW_TH_V1(x) (((x) & BIT_MASK_NPQ_LOW_TH_V1) << BIT_SHIFT_NPQ_LOW_TH_V1)
-#define BIT_GET_NPQ_LOW_TH_V1(x) (((x) >> BIT_SHIFT_NPQ_LOW_TH_V1) & BIT_MASK_NPQ_LOW_TH_V1)
+/* 2 REG_TXDMA_STATUS (Offset 0x0210) */
+#define BIT_PAGE_UDN BIT(3)
-/* 2 REG_TQPNT3 (Offset 0x0220) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_LPQ_HIGH_TH_V1 16
-#define BIT_MASK_LPQ_HIGH_TH_V1 0xfff
-#define BIT_LPQ_HIGH_TH_V1(x) (((x) & BIT_MASK_LPQ_HIGH_TH_V1) << BIT_SHIFT_LPQ_HIGH_TH_V1)
-#define BIT_GET_LPQ_HIGH_TH_V1(x) (((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1) & BIT_MASK_LPQ_HIGH_TH_V1)
+/* 2 REG_TXDMA_STATUS (Offset 0x0210) */
+#define BIT_STOP_HI3Q BIT(3)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_TXDMA_STATUS (Offset 0x0210) */
+#define BIT_PAGE_OVF BIT(2)
-/* 2 REG_TDE_DEBUG (Offset 0x0220) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_TDE_DEBUG 0
-#define BIT_MASK_TDE_DEBUG 0xffffffffL
-#define BIT_TDE_DEBUG(x) (((x) & BIT_MASK_TDE_DEBUG) << BIT_SHIFT_TDE_DEBUG)
-#define BIT_GET_TDE_DEBUG(x) (((x) >> BIT_SHIFT_TDE_DEBUG) & BIT_MASK_TDE_DEBUG)
+/* 2 REG_TXDMA_STATUS (Offset 0x0210) */
+#define BIT_STOP_HI2Q BIT(2)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_TXDMA_STATUS (Offset 0x0210) */
+#define BIT_TXFF_PG_UDN BIT(1)
-/* 2 REG_TQPNT3 (Offset 0x0220) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_LPQ_LOW_TH_V1 0
-#define BIT_MASK_LPQ_LOW_TH_V1 0xfff
-#define BIT_LPQ_LOW_TH_V1(x) (((x) & BIT_MASK_LPQ_LOW_TH_V1) << BIT_SHIFT_LPQ_LOW_TH_V1)
-#define BIT_GET_LPQ_LOW_TH_V1(x) (((x) >> BIT_SHIFT_LPQ_LOW_TH_V1) & BIT_MASK_LPQ_LOW_TH_V1)
+/* 2 REG_TXDMA_STATUS (Offset 0x0210) */
+#define BIT_STOP_HI1Q BIT(1)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_TXDMA_STATUS (Offset 0x0210) */
+#define BIT_TXFF_PG_OVF BIT(0)
-/* 2 REG_AUTO_LLT (Offset 0x0224) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_TXPKTNUM_V1 24
-#define BIT_MASK_TXPKTNUM_V1 0xff
-#define BIT_TXPKTNUM_V1(x) (((x) & BIT_MASK_TXPKTNUM_V1) << BIT_SHIFT_TXPKTNUM_V1)
-#define BIT_GET_TXPKTNUM_V1(x) (((x) >> BIT_SHIFT_TXPKTNUM_V1) & BIT_MASK_TXPKTNUM_V1)
+/* 2 REG_TXDMA_STATUS (Offset 0x0210) */
-#define BIT_TDE_DBG_SEL BIT(23)
-#define BIT_AUTO_INIT_LLT BIT(16)
+#define BIT_STOP_HI0Q BIT(0)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_TQPNT4 (Offset 0x0224) */
+/* 2 REG_RQPN_NPQ (Offset 0x0214) */
+#define BIT_SHIFT_EXQ_AVAL_PG 24
+#define BIT_MASK_EXQ_AVAL_PG 0xff
+#define BIT_EXQ_AVAL_PG(x) \
+ (((x) & BIT_MASK_EXQ_AVAL_PG) << BIT_SHIFT_EXQ_AVAL_PG)
+#define BITS_EXQ_AVAL_PG (BIT_MASK_EXQ_AVAL_PG << BIT_SHIFT_EXQ_AVAL_PG)
+#define BIT_CLEAR_EXQ_AVAL_PG(x) ((x) & (~BITS_EXQ_AVAL_PG))
+#define BIT_GET_EXQ_AVAL_PG(x) \
+ (((x) >> BIT_SHIFT_EXQ_AVAL_PG) & BIT_MASK_EXQ_AVAL_PG)
+#define BIT_SET_EXQ_AVAL_PG(x, v) \
+ (BIT_CLEAR_EXQ_AVAL_PG(x) | BIT_EXQ_AVAL_PG(v))
+
+#define BIT_SHIFT_EXQ 16
+#define BIT_MASK_EXQ 0xff
+#define BIT_EXQ(x) (((x) & BIT_MASK_EXQ) << BIT_SHIFT_EXQ)
+#define BITS_EXQ (BIT_MASK_EXQ << BIT_SHIFT_EXQ)
+#define BIT_CLEAR_EXQ(x) ((x) & (~BITS_EXQ))
+#define BIT_GET_EXQ(x) (((x) >> BIT_SHIFT_EXQ) & BIT_MASK_EXQ)
+#define BIT_SET_EXQ(x, v) (BIT_CLEAR_EXQ(x) | BIT_EXQ(v))
+
+#define BIT_SHIFT_NPQ 0
+#define BIT_MASK_NPQ 0xff
+#define BIT_NPQ(x) (((x) & BIT_MASK_NPQ) << BIT_SHIFT_NPQ)
+#define BITS_NPQ (BIT_MASK_NPQ << BIT_SHIFT_NPQ)
+#define BIT_CLEAR_NPQ(x) ((x) & (~BITS_NPQ))
+#define BIT_GET_NPQ(x) (((x) >> BIT_SHIFT_NPQ) & BIT_MASK_NPQ)
+#define BIT_SET_NPQ(x, v) (BIT_CLEAR_NPQ(x) | BIT_NPQ(v))
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_EXQ_HIGH_TH_V1 16
-#define BIT_MASK_EXQ_HIGH_TH_V1 0xfff
-#define BIT_EXQ_HIGH_TH_V1(x) (((x) & BIT_MASK_EXQ_HIGH_TH_V1) << BIT_SHIFT_EXQ_HIGH_TH_V1)
-#define BIT_GET_EXQ_HIGH_TH_V1(x) (((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1) & BIT_MASK_EXQ_HIGH_TH_V1)
+/* 2 REG_TQPNT1 (Offset 0x0218) */
+#define BIT_HPQ_INT_EN BIT(31)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_TQPNT1 (Offset 0x0218) */
-/* 2 REG_AUTO_LLT (Offset 0x0224) */
+#define BIT_SHIFT_NPQ_HIGH_TH 24
+#define BIT_MASK_NPQ_HIGH_TH 0xff
+#define BIT_NPQ_HIGH_TH(x) \
+ (((x) & BIT_MASK_NPQ_HIGH_TH) << BIT_SHIFT_NPQ_HIGH_TH)
+#define BITS_NPQ_HIGH_TH (BIT_MASK_NPQ_HIGH_TH << BIT_SHIFT_NPQ_HIGH_TH)
+#define BIT_CLEAR_NPQ_HIGH_TH(x) ((x) & (~BITS_NPQ_HIGH_TH))
+#define BIT_GET_NPQ_HIGH_TH(x) \
+ (((x) >> BIT_SHIFT_NPQ_HIGH_TH) & BIT_MASK_NPQ_HIGH_TH)
+#define BIT_SET_NPQ_HIGH_TH(x, v) \
+ (BIT_CLEAR_NPQ_HIGH_TH(x) | BIT_NPQ_HIGH_TH(v))
+#define BIT_SHIFT_NPQ_LOW_TH 16
+#define BIT_MASK_NPQ_LOW_TH 0xff
+#define BIT_NPQ_LOW_TH(x) (((x) & BIT_MASK_NPQ_LOW_TH) << BIT_SHIFT_NPQ_LOW_TH)
+#define BITS_NPQ_LOW_TH (BIT_MASK_NPQ_LOW_TH << BIT_SHIFT_NPQ_LOW_TH)
+#define BIT_CLEAR_NPQ_LOW_TH(x) ((x) & (~BITS_NPQ_LOW_TH))
+#define BIT_GET_NPQ_LOW_TH(x) \
+ (((x) >> BIT_SHIFT_NPQ_LOW_TH) & BIT_MASK_NPQ_LOW_TH)
+#define BIT_SET_NPQ_LOW_TH(x, v) (BIT_CLEAR_NPQ_LOW_TH(x) | BIT_NPQ_LOW_TH(v))
-#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE 8
-#define BIT_MASK_TX_OQT_HE_FREE_SPACE 0xff
-#define BIT_TX_OQT_HE_FREE_SPACE(x) (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE) << BIT_SHIFT_TX_OQT_HE_FREE_SPACE)
-#define BIT_GET_TX_OQT_HE_FREE_SPACE(x) (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE) & BIT_MASK_TX_OQT_HE_FREE_SPACE)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE 0
-#define BIT_MASK_TX_OQT_NL_FREE_SPACE 0xff
-#define BIT_TX_OQT_NL_FREE_SPACE(x) (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE) << BIT_SHIFT_TX_OQT_NL_FREE_SPACE)
-#define BIT_GET_TX_OQT_NL_FREE_SPACE(x) (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE) & BIT_MASK_TX_OQT_NL_FREE_SPACE)
+/* 2 REG_TQPNT1 (Offset 0x0218) */
+#define BIT_SHIFT_HPQ_HIGH_TH_V1 16
+#define BIT_MASK_HPQ_HIGH_TH_V1 0xfff
+#define BIT_HPQ_HIGH_TH_V1(x) \
+ (((x) & BIT_MASK_HPQ_HIGH_TH_V1) << BIT_SHIFT_HPQ_HIGH_TH_V1)
+#define BITS_HPQ_HIGH_TH_V1 \
+ (BIT_MASK_HPQ_HIGH_TH_V1 << BIT_SHIFT_HPQ_HIGH_TH_V1)
+#define BIT_CLEAR_HPQ_HIGH_TH_V1(x) ((x) & (~BITS_HPQ_HIGH_TH_V1))
+#define BIT_GET_HPQ_HIGH_TH_V1(x) \
+ (((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1) & BIT_MASK_HPQ_HIGH_TH_V1)
+#define BIT_SET_HPQ_HIGH_TH_V1(x, v) \
+ (BIT_CLEAR_HPQ_HIGH_TH_V1(x) | BIT_HPQ_HIGH_TH_V1(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_DMA_RQPN_INFO_PUB (Offset 0x0218) */
+#define BIT_SHIFT_PUB_AVAL_PG 16
+#define BIT_MASK_PUB_AVAL_PG 0xfff
+#define BIT_PUB_AVAL_PG(x) \
+ (((x) & BIT_MASK_PUB_AVAL_PG) << BIT_SHIFT_PUB_AVAL_PG)
+#define BITS_PUB_AVAL_PG (BIT_MASK_PUB_AVAL_PG << BIT_SHIFT_PUB_AVAL_PG)
+#define BIT_CLEAR_PUB_AVAL_PG(x) ((x) & (~BITS_PUB_AVAL_PG))
+#define BIT_GET_PUB_AVAL_PG(x) \
+ (((x) >> BIT_SHIFT_PUB_AVAL_PG) & BIT_MASK_PUB_AVAL_PG)
+#define BIT_SET_PUB_AVAL_PG(x, v) \
+ (BIT_CLEAR_PUB_AVAL_PG(x) | BIT_PUB_AVAL_PG(v))
-/* 2 REG_TQPNT4 (Offset 0x0224) */
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_TQPNT1 (Offset 0x0218) */
-#define BIT_SHIFT_EXQ_LOW_TH_V1 0
-#define BIT_MASK_EXQ_LOW_TH_V1 0xfff
-#define BIT_EXQ_LOW_TH_V1(x) (((x) & BIT_MASK_EXQ_LOW_TH_V1) << BIT_SHIFT_EXQ_LOW_TH_V1)
-#define BIT_GET_EXQ_LOW_TH_V1(x) (((x) >> BIT_SHIFT_EXQ_LOW_TH_V1) & BIT_MASK_EXQ_LOW_TH_V1)
+#define BIT_SHIFT_HPQ_HIGH_TH 8
+#define BIT_MASK_HPQ_HIGH_TH 0xff
+#define BIT_HPQ_HIGH_TH(x) \
+ (((x) & BIT_MASK_HPQ_HIGH_TH) << BIT_SHIFT_HPQ_HIGH_TH)
+#define BITS_HPQ_HIGH_TH (BIT_MASK_HPQ_HIGH_TH << BIT_SHIFT_HPQ_HIGH_TH)
+#define BIT_CLEAR_HPQ_HIGH_TH(x) ((x) & (~BITS_HPQ_HIGH_TH))
+#define BIT_GET_HPQ_HIGH_TH(x) \
+ (((x) >> BIT_SHIFT_HPQ_HIGH_TH) & BIT_MASK_HPQ_HIGH_TH)
+#define BIT_SET_HPQ_HIGH_TH(x, v) \
+ (BIT_CLEAR_HPQ_HIGH_TH(x) | BIT_HPQ_HIGH_TH(v))
+#define BIT_SHIFT_HPQ_LOW_TH 0
+#define BIT_MASK_HPQ_LOW_TH 0xff
+#define BIT_HPQ_LOW_TH(x) (((x) & BIT_MASK_HPQ_LOW_TH) << BIT_SHIFT_HPQ_LOW_TH)
+#define BITS_HPQ_LOW_TH (BIT_MASK_HPQ_LOW_TH << BIT_SHIFT_HPQ_LOW_TH)
+#define BIT_CLEAR_HPQ_LOW_TH(x) ((x) & (~BITS_HPQ_LOW_TH))
+#define BIT_GET_HPQ_LOW_TH(x) \
+ (((x) >> BIT_SHIFT_HPQ_LOW_TH) & BIT_MASK_HPQ_LOW_TH)
+#define BIT_SET_HPQ_LOW_TH(x, v) (BIT_CLEAR_HPQ_LOW_TH(x) | BIT_HPQ_LOW_TH(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_TQPNT1 (Offset 0x0218) */
+#define BIT_SHIFT_HPQ_LOW_TH_V1 0
+#define BIT_MASK_HPQ_LOW_TH_V1 0xfff
+#define BIT_HPQ_LOW_TH_V1(x) \
+ (((x) & BIT_MASK_HPQ_LOW_TH_V1) << BIT_SHIFT_HPQ_LOW_TH_V1)
+#define BITS_HPQ_LOW_TH_V1 (BIT_MASK_HPQ_LOW_TH_V1 << BIT_SHIFT_HPQ_LOW_TH_V1)
+#define BIT_CLEAR_HPQ_LOW_TH_V1(x) ((x) & (~BITS_HPQ_LOW_TH_V1))
+#define BIT_GET_HPQ_LOW_TH_V1(x) \
+ (((x) >> BIT_SHIFT_HPQ_LOW_TH_V1) & BIT_MASK_HPQ_LOW_TH_V1)
+#define BIT_SET_HPQ_LOW_TH_V1(x, v) \
+ (BIT_CLEAR_HPQ_LOW_TH_V1(x) | BIT_HPQ_LOW_TH_V1(v))
-/* 2 REG_DWBCN1_CTRL (Offset 0x0228) */
+#endif
-#define BIT_SW_BCN_SEL BIT(20)
-#define BIT_SW_BCN_SEL_EN BIT(17)
-#define BIT_BCN_VALID_1 BIT(16)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_DMA_RQPN_INFO_PUB (Offset 0x0218) */
+#define BIT_SHIFT_PUB_RSVD_PG 0
+#define BIT_MASK_PUB_RSVD_PG 0xfff
+#define BIT_PUB_RSVD_PG(x) \
+ (((x) & BIT_MASK_PUB_RSVD_PG) << BIT_SHIFT_PUB_RSVD_PG)
+#define BITS_PUB_RSVD_PG (BIT_MASK_PUB_RSVD_PG << BIT_SHIFT_PUB_RSVD_PG)
+#define BIT_CLEAR_PUB_RSVD_PG(x) ((x) & (~BITS_PUB_RSVD_PG))
+#define BIT_GET_PUB_RSVD_PG(x) \
+ (((x) >> BIT_SHIFT_PUB_RSVD_PG) & BIT_MASK_PUB_RSVD_PG)
+#define BIT_SET_PUB_RSVD_PG(x, v) \
+ (BIT_CLEAR_PUB_RSVD_PG(x) | BIT_PUB_RSVD_PG(v))
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_RQPN_CTRL_2_V1 (Offset 0x021C) */
+#define BIT_LD_RQPN_V1 BIT(31)
-/* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */
+#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_TXPKTNUM_H 16
-#define BIT_MASK_TXPKTNUM_H 0xffff
-#define BIT_TXPKTNUM_H(x) (((x) & BIT_MASK_TXPKTNUM_H) << BIT_SHIFT_TXPKTNUM_H)
-#define BIT_GET_TXPKTNUM_H(x) (((x) >> BIT_SHIFT_TXPKTNUM_H) & BIT_MASK_TXPKTNUM_H)
+/* 2 REG_TQPNT2 (Offset 0x021C) */
+#define BIT_NPQ_INT_EN BIT(31)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_TQPNT2 (Offset 0x021C) */
-/* 2 REG_DWBCN1_CTRL (Offset 0x0228) */
+#define BIT_SHIFT_EXQ_HIGH_TH 24
+#define BIT_MASK_EXQ_HIGH_TH 0xff
+#define BIT_EXQ_HIGH_TH(x) \
+ (((x) & BIT_MASK_EXQ_HIGH_TH) << BIT_SHIFT_EXQ_HIGH_TH)
+#define BITS_EXQ_HIGH_TH (BIT_MASK_EXQ_HIGH_TH << BIT_SHIFT_EXQ_HIGH_TH)
+#define BIT_CLEAR_EXQ_HIGH_TH(x) ((x) & (~BITS_EXQ_HIGH_TH))
+#define BIT_GET_EXQ_HIGH_TH(x) \
+ (((x) >> BIT_SHIFT_EXQ_HIGH_TH) & BIT_MASK_EXQ_HIGH_TH)
+#define BIT_SET_EXQ_HIGH_TH(x, v) \
+ (BIT_CLEAR_EXQ_HIGH_TH(x) | BIT_EXQ_HIGH_TH(v))
+#define BIT_SHIFT_EXQ_LOW_TH 16
+#define BIT_MASK_EXQ_LOW_TH 0xff
+#define BIT_EXQ_LOW_TH(x) (((x) & BIT_MASK_EXQ_LOW_TH) << BIT_SHIFT_EXQ_LOW_TH)
+#define BITS_EXQ_LOW_TH (BIT_MASK_EXQ_LOW_TH << BIT_SHIFT_EXQ_LOW_TH)
+#define BIT_CLEAR_EXQ_LOW_TH(x) ((x) & (~BITS_EXQ_LOW_TH))
+#define BIT_GET_EXQ_LOW_TH(x) \
+ (((x) >> BIT_SHIFT_EXQ_LOW_TH) & BIT_MASK_EXQ_LOW_TH)
+#define BIT_SET_EXQ_LOW_TH(x, v) (BIT_CLEAR_EXQ_LOW_TH(x) | BIT_EXQ_LOW_TH(v))
-#define BIT_SHIFT_BCN_HEAD_1 8
-#define BIT_MASK_BCN_HEAD_1 0xff
-#define BIT_BCN_HEAD_1(x) (((x) & BIT_MASK_BCN_HEAD_1) << BIT_SHIFT_BCN_HEAD_1)
-#define BIT_GET_BCN_HEAD_1(x) (((x) >> BIT_SHIFT_BCN_HEAD_1) & BIT_MASK_BCN_HEAD_1)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO 0
-#define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO 0xff
-#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO(x) (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO) << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO)
-#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO(x) (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO)
+/* 2 REG_TQPNT2 (Offset 0x021C) */
+#define BIT_SHIFT_NPQ_HIGH_TH_V1 16
+#define BIT_MASK_NPQ_HIGH_TH_V1 0xfff
+#define BIT_NPQ_HIGH_TH_V1(x) \
+ (((x) & BIT_MASK_NPQ_HIGH_TH_V1) << BIT_SHIFT_NPQ_HIGH_TH_V1)
+#define BITS_NPQ_HIGH_TH_V1 \
+ (BIT_MASK_NPQ_HIGH_TH_V1 << BIT_SHIFT_NPQ_HIGH_TH_V1)
+#define BIT_CLEAR_NPQ_HIGH_TH_V1(x) ((x) & (~BITS_NPQ_HIGH_TH_V1))
+#define BIT_GET_NPQ_HIGH_TH_V1(x) \
+ (((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1) & BIT_MASK_NPQ_HIGH_TH_V1)
+#define BIT_SET_NPQ_HIGH_TH_V1(x, v) \
+ (BIT_CLEAR_NPQ_HIGH_TH_V1(x) | BIT_NPQ_HIGH_TH_V1(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_RQPN_CTRL_2_V1 (Offset 0x021C) */
+#define BIT_CH16_PUBLIC_DIS BIT(16)
+#define BIT_CH15_PUBLIC_DIS BIT(15)
+#define BIT_CH14_PUBLIC_DIS BIT(14)
+#define BIT_CH13_PUBLIC_DIS BIT(13)
+#define BIT_CH12_PUBLIC_DIS BIT(12)
+#define BIT_CH11_PUBLIC_DIS BIT(11)
+#define BIT_CH10_PUBLIC_DIS BIT(10)
+#define BIT_CH9_PUBLIC_DIS BIT(9)
-/* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_TXPKTNUM_H_V1 0
-#define BIT_MASK_TXPKTNUM_H_V1 0xffff
-#define BIT_TXPKTNUM_H_V1(x) (((x) & BIT_MASK_TXPKTNUM_H_V1) << BIT_SHIFT_TXPKTNUM_H_V1)
-#define BIT_GET_TXPKTNUM_H_V1(x) (((x) >> BIT_SHIFT_TXPKTNUM_H_V1) & BIT_MASK_TXPKTNUM_H_V1)
+/* 2 REG_TQPNT2 (Offset 0x021C) */
+#define BIT_SHIFT_LPQ_HIGH_TH 8
+#define BIT_MASK_LPQ_HIGH_TH 0xff
+#define BIT_LPQ_HIGH_TH(x) \
+ (((x) & BIT_MASK_LPQ_HIGH_TH) << BIT_SHIFT_LPQ_HIGH_TH)
+#define BITS_LPQ_HIGH_TH (BIT_MASK_LPQ_HIGH_TH << BIT_SHIFT_LPQ_HIGH_TH)
+#define BIT_CLEAR_LPQ_HIGH_TH(x) ((x) & (~BITS_LPQ_HIGH_TH))
+#define BIT_GET_LPQ_HIGH_TH(x) \
+ (((x) >> BIT_SHIFT_LPQ_HIGH_TH) & BIT_MASK_LPQ_HIGH_TH)
+#define BIT_SET_LPQ_HIGH_TH(x, v) \
+ (BIT_CLEAR_LPQ_HIGH_TH(x) | BIT_LPQ_HIGH_TH(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_RQPN_CTRL_2_V1 (Offset 0x021C) */
+#define BIT_CH8_PUBLIC_DIS BIT(8)
+#define BIT_CH7_PUBLIC_DIS BIT(7)
+#define BIT_CH6_PUBLIC_DIS BIT(6)
+#define BIT_CH5_PUBLIC_DIS BIT(5)
+#define BIT_CH4_PUBLIC_DIS BIT(4)
+#define BIT_CH3_PUBLIC_DIS BIT(3)
+#define BIT_CH2_PUBLIC_DIS BIT(2)
+#define BIT_CH1_PUBLIC_DIS BIT(1)
-/* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_TXPKTNUM_V2 0
-#define BIT_MASK_TXPKTNUM_V2 0xffff
-#define BIT_TXPKTNUM_V2(x) (((x) & BIT_MASK_TXPKTNUM_V2) << BIT_SHIFT_TXPKTNUM_V2)
-#define BIT_GET_TXPKTNUM_V2(x) (((x) >> BIT_SHIFT_TXPKTNUM_V2) & BIT_MASK_TXPKTNUM_V2)
+/* 2 REG_TQPNT2 (Offset 0x021C) */
+#define BIT_SHIFT_LPQ_LOW_TH 0
+#define BIT_MASK_LPQ_LOW_TH 0xff
+#define BIT_LPQ_LOW_TH(x) (((x) & BIT_MASK_LPQ_LOW_TH) << BIT_SHIFT_LPQ_LOW_TH)
+#define BITS_LPQ_LOW_TH (BIT_MASK_LPQ_LOW_TH << BIT_SHIFT_LPQ_LOW_TH)
+#define BIT_CLEAR_LPQ_LOW_TH(x) ((x) & (~BITS_LPQ_LOW_TH))
+#define BIT_GET_LPQ_LOW_TH(x) \
+ (((x) >> BIT_SHIFT_LPQ_LOW_TH) & BIT_MASK_LPQ_LOW_TH)
+#define BIT_SET_LPQ_LOW_TH(x, v) (BIT_CLEAR_LPQ_LOW_TH(x) | BIT_LPQ_LOW_TH(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_TQPNT2 (Offset 0x021C) */
+#define BIT_SHIFT_NPQ_LOW_TH_V1 0
+#define BIT_MASK_NPQ_LOW_TH_V1 0xfff
+#define BIT_NPQ_LOW_TH_V1(x) \
+ (((x) & BIT_MASK_NPQ_LOW_TH_V1) << BIT_SHIFT_NPQ_LOW_TH_V1)
+#define BITS_NPQ_LOW_TH_V1 (BIT_MASK_NPQ_LOW_TH_V1 << BIT_SHIFT_NPQ_LOW_TH_V1)
+#define BIT_CLEAR_NPQ_LOW_TH_V1(x) ((x) & (~BITS_NPQ_LOW_TH_V1))
+#define BIT_GET_NPQ_LOW_TH_V1(x) \
+ (((x) >> BIT_SHIFT_NPQ_LOW_TH_V1) & BIT_MASK_NPQ_LOW_TH_V1)
+#define BIT_SET_NPQ_LOW_TH_V1(x, v) \
+ (BIT_CLEAR_NPQ_LOW_TH_V1(x) | BIT_NPQ_LOW_TH_V1(v))
-/* 2 REG_RQPN_CTRL_2 (Offset 0x022C) */
+#endif
-#define BIT_EXQ_PUBLIC_DIS_V1 BIT(19)
-#define BIT_NPQ_PUBLIC_DIS_V1 BIT(18)
-#define BIT_LPQ_PUBLIC_DIS_V1 BIT(17)
-#define BIT_HPQ_PUBLIC_DIS_V1 BIT(16)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_RQPN_CTRL_2_V1 (Offset 0x021C) */
+#define BIT_CH0_PUBLIC_DIS BIT(0)
-#if (HALMAC_8821C_SUPPORT)
+/* 2 REG_BCN_CTRL_2 (Offset 0x0220) */
+#define BIT_BCN0_EXT_VALID BIT(31)
-/* 2 REG_RQPN_CTRL_2 (Offset 0x022C) */
+#endif
-#define BIT_SDIO_TXAGG_ALIGN_ADJUST_EN BIT(15)
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE 0
-#define BIT_MASK_SDIO_TXAGG_ALIGN_SIZE 0xfff
-#define BIT_SDIO_TXAGG_ALIGN_SIZE(x) (((x) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE) << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE)
-#define BIT_GET_SDIO_TXAGG_ALIGN_SIZE(x) (((x) >> BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE)
+/* 2 REG_TQPNT3 (Offset 0x0220) */
+#define BIT_LPQ_INT_EN BIT(31)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_FIFOPAGE_INFO_1 (Offset 0x0230) */
+/* 2 REG_TQPNT3 (Offset 0x0220) */
+#define BIT_SHIFT_LPQ_HIGH_TH_V1 16
+#define BIT_MASK_LPQ_HIGH_TH_V1 0xfff
+#define BIT_LPQ_HIGH_TH_V1(x) \
+ (((x) & BIT_MASK_LPQ_HIGH_TH_V1) << BIT_SHIFT_LPQ_HIGH_TH_V1)
+#define BITS_LPQ_HIGH_TH_V1 \
+ (BIT_MASK_LPQ_HIGH_TH_V1 << BIT_SHIFT_LPQ_HIGH_TH_V1)
+#define BIT_CLEAR_LPQ_HIGH_TH_V1(x) ((x) & (~BITS_LPQ_HIGH_TH_V1))
+#define BIT_GET_LPQ_HIGH_TH_V1(x) \
+ (((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1) & BIT_MASK_LPQ_HIGH_TH_V1)
+#define BIT_SET_LPQ_HIGH_TH_V1(x, v) \
+ (BIT_CLEAR_LPQ_HIGH_TH_V1(x) | BIT_LPQ_HIGH_TH_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_BCN_CTRL_2 (Offset 0x0220) */
+
+#define BIT_SHIFT_BCN0_EXT_HEAD 16
+#define BIT_MASK_BCN0_EXT_HEAD 0xfff
+#define BIT_BCN0_EXT_HEAD(x) \
+ (((x) & BIT_MASK_BCN0_EXT_HEAD) << BIT_SHIFT_BCN0_EXT_HEAD)
+#define BITS_BCN0_EXT_HEAD (BIT_MASK_BCN0_EXT_HEAD << BIT_SHIFT_BCN0_EXT_HEAD)
+#define BIT_CLEAR_BCN0_EXT_HEAD(x) ((x) & (~BITS_BCN0_EXT_HEAD))
+#define BIT_GET_BCN0_EXT_HEAD(x) \
+ (((x) >> BIT_SHIFT_BCN0_EXT_HEAD) & BIT_MASK_BCN0_EXT_HEAD)
+#define BIT_SET_BCN0_EXT_HEAD(x, v) \
+ (BIT_CLEAR_BCN0_EXT_HEAD(x) | BIT_BCN0_EXT_HEAD(v))
+
+#define BIT_SHIFT_TXPKTNUM_CH4_7 16
+#define BIT_MASK_TXPKTNUM_CH4_7 0xfff
+#define BIT_TXPKTNUM_CH4_7(x) \
+ (((x) & BIT_MASK_TXPKTNUM_CH4_7) << BIT_SHIFT_TXPKTNUM_CH4_7)
+#define BITS_TXPKTNUM_CH4_7 \
+ (BIT_MASK_TXPKTNUM_CH4_7 << BIT_SHIFT_TXPKTNUM_CH4_7)
+#define BIT_CLEAR_TXPKTNUM_CH4_7(x) ((x) & (~BITS_TXPKTNUM_CH4_7))
+#define BIT_GET_TXPKTNUM_CH4_7(x) \
+ (((x) >> BIT_SHIFT_TXPKTNUM_CH4_7) & BIT_MASK_TXPKTNUM_CH4_7)
+#define BIT_SET_TXPKTNUM_CH4_7(x, v) \
+ (BIT_CLEAR_TXPKTNUM_CH4_7(x) | BIT_TXPKTNUM_CH4_7(v))
+
+#define BIT_SHIFT_TXPKTNUM_CH12 16
+#define BIT_MASK_TXPKTNUM_CH12 0xfff
+#define BIT_TXPKTNUM_CH12(x) \
+ (((x) & BIT_MASK_TXPKTNUM_CH12) << BIT_SHIFT_TXPKTNUM_CH12)
+#define BITS_TXPKTNUM_CH12 (BIT_MASK_TXPKTNUM_CH12 << BIT_SHIFT_TXPKTNUM_CH12)
+#define BIT_CLEAR_TXPKTNUM_CH12(x) ((x) & (~BITS_TXPKTNUM_CH12))
+#define BIT_GET_TXPKTNUM_CH12(x) \
+ (((x) >> BIT_SHIFT_TXPKTNUM_CH12) & BIT_MASK_TXPKTNUM_CH12)
+#define BIT_SET_TXPKTNUM_CH12(x, v) \
+ (BIT_CLEAR_TXPKTNUM_CH12(x) | BIT_TXPKTNUM_CH12(v))
+
+#define BIT_SHIFT_TXPKTNUM_CH14_15 16
+#define BIT_MASK_TXPKTNUM_CH14_15 0xfff
+#define BIT_TXPKTNUM_CH14_15(x) \
+ (((x) & BIT_MASK_TXPKTNUM_CH14_15) << BIT_SHIFT_TXPKTNUM_CH14_15)
+#define BITS_TXPKTNUM_CH14_15 \
+ (BIT_MASK_TXPKTNUM_CH14_15 << BIT_SHIFT_TXPKTNUM_CH14_15)
+#define BIT_CLEAR_TXPKTNUM_CH14_15(x) ((x) & (~BITS_TXPKTNUM_CH14_15))
+#define BIT_GET_TXPKTNUM_CH14_15(x) \
+ (((x) >> BIT_SHIFT_TXPKTNUM_CH14_15) & BIT_MASK_TXPKTNUM_CH14_15)
+#define BIT_SET_TXPKTNUM_CH14_15(x, v) \
+ (BIT_CLEAR_TXPKTNUM_CH14_15(x) | BIT_TXPKTNUM_CH14_15(v))
+
+#define BIT_BCN4_VALID BIT(15)
-#define BIT_SHIFT_HPQ_AVAL_PG_V1 16
-#define BIT_MASK_HPQ_AVAL_PG_V1 0xfff
-#define BIT_HPQ_AVAL_PG_V1(x) (((x) & BIT_MASK_HPQ_AVAL_PG_V1) << BIT_SHIFT_HPQ_AVAL_PG_V1)
-#define BIT_GET_HPQ_AVAL_PG_V1(x) (((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1) & BIT_MASK_HPQ_AVAL_PG_V1)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_HPQ_V1 0
-#define BIT_MASK_HPQ_V1 0xfff
-#define BIT_HPQ_V1(x) (((x) & BIT_MASK_HPQ_V1) << BIT_SHIFT_HPQ_V1)
-#define BIT_GET_HPQ_V1(x) (((x) >> BIT_SHIFT_HPQ_V1) & BIT_MASK_HPQ_V1)
+/* 2 REG_TDE_DEBUG (Offset 0x0220) */
+#define BIT_SHIFT_TDE_DEBUG 0
+#define BIT_MASK_TDE_DEBUG 0xffffffffL
+#define BIT_TDE_DEBUG(x) (((x) & BIT_MASK_TDE_DEBUG) << BIT_SHIFT_TDE_DEBUG)
+#define BITS_TDE_DEBUG (BIT_MASK_TDE_DEBUG << BIT_SHIFT_TDE_DEBUG)
+#define BIT_CLEAR_TDE_DEBUG(x) ((x) & (~BITS_TDE_DEBUG))
+#define BIT_GET_TDE_DEBUG(x) (((x) >> BIT_SHIFT_TDE_DEBUG) & BIT_MASK_TDE_DEBUG)
+#define BIT_SET_TDE_DEBUG(x, v) (BIT_CLEAR_TDE_DEBUG(x) | BIT_TDE_DEBUG(v))
-/* 2 REG_FIFOPAGE_INFO_2 (Offset 0x0234) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_LPQ_AVAL_PG_V1 16
-#define BIT_MASK_LPQ_AVAL_PG_V1 0xfff
-#define BIT_LPQ_AVAL_PG_V1(x) (((x) & BIT_MASK_LPQ_AVAL_PG_V1) << BIT_SHIFT_LPQ_AVAL_PG_V1)
-#define BIT_GET_LPQ_AVAL_PG_V1(x) (((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1) & BIT_MASK_LPQ_AVAL_PG_V1)
+/* 2 REG_TQPNT3 (Offset 0x0220) */
+#define BIT_SHIFT_LPQ_LOW_TH_V1 0
+#define BIT_MASK_LPQ_LOW_TH_V1 0xfff
+#define BIT_LPQ_LOW_TH_V1(x) \
+ (((x) & BIT_MASK_LPQ_LOW_TH_V1) << BIT_SHIFT_LPQ_LOW_TH_V1)
+#define BITS_LPQ_LOW_TH_V1 (BIT_MASK_LPQ_LOW_TH_V1 << BIT_SHIFT_LPQ_LOW_TH_V1)
+#define BIT_CLEAR_LPQ_LOW_TH_V1(x) ((x) & (~BITS_LPQ_LOW_TH_V1))
+#define BIT_GET_LPQ_LOW_TH_V1(x) \
+ (((x) >> BIT_SHIFT_LPQ_LOW_TH_V1) & BIT_MASK_LPQ_LOW_TH_V1)
+#define BIT_SET_LPQ_LOW_TH_V1(x, v) \
+ (BIT_CLEAR_LPQ_LOW_TH_V1(x) | BIT_LPQ_LOW_TH_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_BCN_CTRL_2 (Offset 0x0220) */
+
+#define BIT_SHIFT_BCN4_HEAD 0
+#define BIT_MASK_BCN4_HEAD 0xfff
+#define BIT_BCN4_HEAD(x) (((x) & BIT_MASK_BCN4_HEAD) << BIT_SHIFT_BCN4_HEAD)
+#define BITS_BCN4_HEAD (BIT_MASK_BCN4_HEAD << BIT_SHIFT_BCN4_HEAD)
+#define BIT_CLEAR_BCN4_HEAD(x) ((x) & (~BITS_BCN4_HEAD))
+#define BIT_GET_BCN4_HEAD(x) (((x) >> BIT_SHIFT_BCN4_HEAD) & BIT_MASK_BCN4_HEAD)
+#define BIT_SET_BCN4_HEAD(x, v) (BIT_CLEAR_BCN4_HEAD(x) | BIT_BCN4_HEAD(v))
+
+#define BIT_SHIFT_TXPKTNUM_CH0_3 0
+#define BIT_MASK_TXPKTNUM_CH0_3 0xfff
+#define BIT_TXPKTNUM_CH0_3(x) \
+ (((x) & BIT_MASK_TXPKTNUM_CH0_3) << BIT_SHIFT_TXPKTNUM_CH0_3)
+#define BITS_TXPKTNUM_CH0_3 \
+ (BIT_MASK_TXPKTNUM_CH0_3 << BIT_SHIFT_TXPKTNUM_CH0_3)
+#define BIT_CLEAR_TXPKTNUM_CH0_3(x) ((x) & (~BITS_TXPKTNUM_CH0_3))
+#define BIT_GET_TXPKTNUM_CH0_3(x) \
+ (((x) >> BIT_SHIFT_TXPKTNUM_CH0_3) & BIT_MASK_TXPKTNUM_CH0_3)
+#define BIT_SET_TXPKTNUM_CH0_3(x, v) \
+ (BIT_CLEAR_TXPKTNUM_CH0_3(x) | BIT_TXPKTNUM_CH0_3(v))
+
+#define BIT_SHIFT_TXPKTNUM_CH8_11 0
+#define BIT_MASK_TXPKTNUM_CH8_11 0xfff
+#define BIT_TXPKTNUM_CH8_11(x) \
+ (((x) & BIT_MASK_TXPKTNUM_CH8_11) << BIT_SHIFT_TXPKTNUM_CH8_11)
+#define BITS_TXPKTNUM_CH8_11 \
+ (BIT_MASK_TXPKTNUM_CH8_11 << BIT_SHIFT_TXPKTNUM_CH8_11)
+#define BIT_CLEAR_TXPKTNUM_CH8_11(x) ((x) & (~BITS_TXPKTNUM_CH8_11))
+#define BIT_GET_TXPKTNUM_CH8_11(x) \
+ (((x) >> BIT_SHIFT_TXPKTNUM_CH8_11) & BIT_MASK_TXPKTNUM_CH8_11)
+#define BIT_SET_TXPKTNUM_CH8_11(x, v) \
+ (BIT_CLEAR_TXPKTNUM_CH8_11(x) | BIT_TXPKTNUM_CH8_11(v))
+
+#define BIT_SHIFT_TXPKTNUM_CH13 0
+#define BIT_MASK_TXPKTNUM_CH13 0xfff
+#define BIT_TXPKTNUM_CH13(x) \
+ (((x) & BIT_MASK_TXPKTNUM_CH13) << BIT_SHIFT_TXPKTNUM_CH13)
+#define BITS_TXPKTNUM_CH13 (BIT_MASK_TXPKTNUM_CH13 << BIT_SHIFT_TXPKTNUM_CH13)
+#define BIT_CLEAR_TXPKTNUM_CH13(x) ((x) & (~BITS_TXPKTNUM_CH13))
+#define BIT_GET_TXPKTNUM_CH13(x) \
+ (((x) >> BIT_SHIFT_TXPKTNUM_CH13) & BIT_MASK_TXPKTNUM_CH13)
+#define BIT_SET_TXPKTNUM_CH13(x, v) \
+ (BIT_CLEAR_TXPKTNUM_CH13(x) | BIT_TXPKTNUM_CH13(v))
+
+#define BIT_SHIFT_TXPKTNUM_CH16 0
+#define BIT_MASK_TXPKTNUM_CH16 0xfff
+#define BIT_TXPKTNUM_CH16(x) \
+ (((x) & BIT_MASK_TXPKTNUM_CH16) << BIT_SHIFT_TXPKTNUM_CH16)
+#define BITS_TXPKTNUM_CH16 (BIT_MASK_TXPKTNUM_CH16 << BIT_SHIFT_TXPKTNUM_CH16)
+#define BIT_CLEAR_TXPKTNUM_CH16(x) ((x) & (~BITS_TXPKTNUM_CH16))
+#define BIT_GET_TXPKTNUM_CH16(x) \
+ (((x) >> BIT_SHIFT_TXPKTNUM_CH16) & BIT_MASK_TXPKTNUM_CH16)
+#define BIT_SET_TXPKTNUM_CH16(x, v) \
+ (BIT_CLEAR_TXPKTNUM_CH16(x) | BIT_TXPKTNUM_CH16(v))
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_LPQ_V1 0
-#define BIT_MASK_LPQ_V1 0xfff
-#define BIT_LPQ_V1(x) (((x) & BIT_MASK_LPQ_V1) << BIT_SHIFT_LPQ_V1)
-#define BIT_GET_LPQ_V1(x) (((x) >> BIT_SHIFT_LPQ_V1) & BIT_MASK_LPQ_V1)
+/* 2 REG_TQPNT4 (Offset 0x0224) */
+#define BIT_EXQ_INT_EN BIT(31)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_FIFOPAGE_INFO_3 (Offset 0x0238) */
-
+/* 2 REG_AUTO_LLT (Offset 0x0224) */
-#define BIT_SHIFT_NPQ_AVAL_PG_V1 16
-#define BIT_MASK_NPQ_AVAL_PG_V1 0xfff
-#define BIT_NPQ_AVAL_PG_V1(x) (((x) & BIT_MASK_NPQ_AVAL_PG_V1) << BIT_SHIFT_NPQ_AVAL_PG_V1)
-#define BIT_GET_NPQ_AVAL_PG_V1(x) (((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1) & BIT_MASK_NPQ_AVAL_PG_V1)
+#define BIT_SHIFT_TXPKTNUM_V1 24
+#define BIT_MASK_TXPKTNUM_V1 0xff
+#define BIT_TXPKTNUM_V1(x) \
+ (((x) & BIT_MASK_TXPKTNUM_V1) << BIT_SHIFT_TXPKTNUM_V1)
+#define BITS_TXPKTNUM_V1 (BIT_MASK_TXPKTNUM_V1 << BIT_SHIFT_TXPKTNUM_V1)
+#define BIT_CLEAR_TXPKTNUM_V1(x) ((x) & (~BITS_TXPKTNUM_V1))
+#define BIT_GET_TXPKTNUM_V1(x) \
+ (((x) >> BIT_SHIFT_TXPKTNUM_V1) & BIT_MASK_TXPKTNUM_V1)
+#define BIT_SET_TXPKTNUM_V1(x, v) \
+ (BIT_CLEAR_TXPKTNUM_V1(x) | BIT_TXPKTNUM_V1(v))
+#define BIT_TDE_DBG_SEL BIT(23)
+#define BIT_AUTO_INIT_LLT BIT(16)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_FIFOPAGE_INFO_3 (Offset 0x0238) */
+/* 2 REG_TQPNT4 (Offset 0x0224) */
+#define BIT_SHIFT_EXQ_HIGH_TH_V1 16
+#define BIT_MASK_EXQ_HIGH_TH_V1 0xfff
+#define BIT_EXQ_HIGH_TH_V1(x) \
+ (((x) & BIT_MASK_EXQ_HIGH_TH_V1) << BIT_SHIFT_EXQ_HIGH_TH_V1)
+#define BITS_EXQ_HIGH_TH_V1 \
+ (BIT_MASK_EXQ_HIGH_TH_V1 << BIT_SHIFT_EXQ_HIGH_TH_V1)
+#define BIT_CLEAR_EXQ_HIGH_TH_V1(x) ((x) & (~BITS_EXQ_HIGH_TH_V1))
+#define BIT_GET_EXQ_HIGH_TH_V1(x) \
+ (((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1) & BIT_MASK_EXQ_HIGH_TH_V1)
+#define BIT_SET_EXQ_HIGH_TH_V1(x, v) \
+ (BIT_CLEAR_EXQ_HIGH_TH_V1(x) | BIT_EXQ_HIGH_TH_V1(v))
-#define BIT_SHIFT_NPQ_V1 0
-#define BIT_MASK_NPQ_V1 0xfff
-#define BIT_NPQ_V1(x) (((x) & BIT_MASK_NPQ_V1) << BIT_SHIFT_NPQ_V1)
-#define BIT_GET_NPQ_V1(x) (((x) >> BIT_SHIFT_NPQ_V1) & BIT_MASK_NPQ_V1)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_FIFOPAGE_INFO_4 (Offset 0x023C) */
+/* 2 REG_AUTO_LLT (Offset 0x0224) */
+#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE 8
+#define BIT_MASK_TX_OQT_HE_FREE_SPACE 0xff
+#define BIT_TX_OQT_HE_FREE_SPACE(x) \
+ (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE) \
+ << BIT_SHIFT_TX_OQT_HE_FREE_SPACE)
+#define BITS_TX_OQT_HE_FREE_SPACE \
+ (BIT_MASK_TX_OQT_HE_FREE_SPACE << BIT_SHIFT_TX_OQT_HE_FREE_SPACE)
+#define BIT_CLEAR_TX_OQT_HE_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_HE_FREE_SPACE))
+#define BIT_GET_TX_OQT_HE_FREE_SPACE(x) \
+ (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE) & \
+ BIT_MASK_TX_OQT_HE_FREE_SPACE)
+#define BIT_SET_TX_OQT_HE_FREE_SPACE(x, v) \
+ (BIT_CLEAR_TX_OQT_HE_FREE_SPACE(x) | BIT_TX_OQT_HE_FREE_SPACE(v))
+
+#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE 0
+#define BIT_MASK_TX_OQT_NL_FREE_SPACE 0xff
+#define BIT_TX_OQT_NL_FREE_SPACE(x) \
+ (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE) \
+ << BIT_SHIFT_TX_OQT_NL_FREE_SPACE)
+#define BITS_TX_OQT_NL_FREE_SPACE \
+ (BIT_MASK_TX_OQT_NL_FREE_SPACE << BIT_SHIFT_TX_OQT_NL_FREE_SPACE)
+#define BIT_CLEAR_TX_OQT_NL_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_NL_FREE_SPACE))
+#define BIT_GET_TX_OQT_NL_FREE_SPACE(x) \
+ (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE) & \
+ BIT_MASK_TX_OQT_NL_FREE_SPACE)
+#define BIT_SET_TX_OQT_NL_FREE_SPACE(x, v) \
+ (BIT_CLEAR_TX_OQT_NL_FREE_SPACE(x) | BIT_TX_OQT_NL_FREE_SPACE(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_EXQ_AVAL_PG_V1 16
-#define BIT_MASK_EXQ_AVAL_PG_V1 0xfff
-#define BIT_EXQ_AVAL_PG_V1(x) (((x) & BIT_MASK_EXQ_AVAL_PG_V1) << BIT_SHIFT_EXQ_AVAL_PG_V1)
-#define BIT_GET_EXQ_AVAL_PG_V1(x) (((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1) & BIT_MASK_EXQ_AVAL_PG_V1)
+/* 2 REG_TQPNT4 (Offset 0x0224) */
+#define BIT_SHIFT_EXQ_LOW_TH_V1 0
+#define BIT_MASK_EXQ_LOW_TH_V1 0xfff
+#define BIT_EXQ_LOW_TH_V1(x) \
+ (((x) & BIT_MASK_EXQ_LOW_TH_V1) << BIT_SHIFT_EXQ_LOW_TH_V1)
+#define BITS_EXQ_LOW_TH_V1 (BIT_MASK_EXQ_LOW_TH_V1 << BIT_SHIFT_EXQ_LOW_TH_V1)
+#define BIT_CLEAR_EXQ_LOW_TH_V1(x) ((x) & (~BITS_EXQ_LOW_TH_V1))
+#define BIT_GET_EXQ_LOW_TH_V1(x) \
+ (((x) >> BIT_SHIFT_EXQ_LOW_TH_V1) & BIT_MASK_EXQ_LOW_TH_V1)
+#define BIT_SET_EXQ_LOW_TH_V1(x, v) \
+ (BIT_CLEAR_EXQ_LOW_TH_V1(x) | BIT_EXQ_LOW_TH_V1(v))
-#define BIT_SHIFT_EXQ_V1 0
-#define BIT_MASK_EXQ_V1 0xfff
-#define BIT_EXQ_V1(x) (((x) & BIT_MASK_EXQ_V1) << BIT_SHIFT_EXQ_V1)
-#define BIT_GET_EXQ_V1(x) (((x) >> BIT_SHIFT_EXQ_V1) & BIT_MASK_EXQ_V1)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_FIFOPAGE_INFO_5 (Offset 0x0240) */
+/* 2 REG_DWBCN1_CTRL (Offset 0x0228) */
+#define BIT_SW_BCN_SEL BIT(20)
+#define BIT_SW_BCN_SEL_EN BIT(17)
+#define BIT_BCN_VALID_1 BIT(16)
-#define BIT_SHIFT_PUBQ_AVAL_PG_V1 16
-#define BIT_MASK_PUBQ_AVAL_PG_V1 0xfff
-#define BIT_PUBQ_AVAL_PG_V1(x) (((x) & BIT_MASK_PUBQ_AVAL_PG_V1) << BIT_SHIFT_PUBQ_AVAL_PG_V1)
-#define BIT_GET_PUBQ_AVAL_PG_V1(x) (((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1) & BIT_MASK_PUBQ_AVAL_PG_V1)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_PUBQ_V1 0
-#define BIT_MASK_PUBQ_V1 0xfff
-#define BIT_PUBQ_V1(x) (((x) & BIT_MASK_PUBQ_V1) << BIT_SHIFT_PUBQ_V1)
-#define BIT_GET_PUBQ_V1(x) (((x) >> BIT_SHIFT_PUBQ_V1) & BIT_MASK_PUBQ_V1)
+/* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */
+#define BIT_SHIFT_TXPKTNUM_H 16
+#define BIT_MASK_TXPKTNUM_H 0xffff
+#define BIT_TXPKTNUM_H(x) (((x) & BIT_MASK_TXPKTNUM_H) << BIT_SHIFT_TXPKTNUM_H)
+#define BITS_TXPKTNUM_H (BIT_MASK_TXPKTNUM_H << BIT_SHIFT_TXPKTNUM_H)
+#define BIT_CLEAR_TXPKTNUM_H(x) ((x) & (~BITS_TXPKTNUM_H))
+#define BIT_GET_TXPKTNUM_H(x) \
+ (((x) >> BIT_SHIFT_TXPKTNUM_H) & BIT_MASK_TXPKTNUM_H)
+#define BIT_SET_TXPKTNUM_H(x, v) (BIT_CLEAR_TXPKTNUM_H(x) | BIT_TXPKTNUM_H(v))
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */
+#define BIT_SHIFT_TXPKTNUM_H_V2 16
+#define BIT_MASK_TXPKTNUM_H_V2 0xfff
+#define BIT_TXPKTNUM_H_V2(x) \
+ (((x) & BIT_MASK_TXPKTNUM_H_V2) << BIT_SHIFT_TXPKTNUM_H_V2)
+#define BITS_TXPKTNUM_H_V2 (BIT_MASK_TXPKTNUM_H_V2 << BIT_SHIFT_TXPKTNUM_H_V2)
+#define BIT_CLEAR_TXPKTNUM_H_V2(x) ((x) & (~BITS_TXPKTNUM_H_V2))
+#define BIT_GET_TXPKTNUM_H_V2(x) \
+ (((x) >> BIT_SHIFT_TXPKTNUM_H_V2) & BIT_MASK_TXPKTNUM_H_V2)
+#define BIT_SET_TXPKTNUM_H_V2(x, v) \
+ (BIT_CLEAR_TXPKTNUM_H_V2(x) | BIT_TXPKTNUM_H_V2(v))
-/* 2 REG_H2C_HEAD (Offset 0x0244) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_H2C_HEAD 0
-#define BIT_MASK_H2C_HEAD 0x3ffff
-#define BIT_H2C_HEAD(x) (((x) & BIT_MASK_H2C_HEAD) << BIT_SHIFT_H2C_HEAD)
-#define BIT_GET_H2C_HEAD(x) (((x) >> BIT_SHIFT_H2C_HEAD) & BIT_MASK_H2C_HEAD)
+/* 2 REG_DWBCN1_CTRL (Offset 0x0228) */
+#define BIT_SHIFT_BCN_HEAD_1 8
+#define BIT_MASK_BCN_HEAD_1 0xff
+#define BIT_BCN_HEAD_1(x) (((x) & BIT_MASK_BCN_HEAD_1) << BIT_SHIFT_BCN_HEAD_1)
+#define BITS_BCN_HEAD_1 (BIT_MASK_BCN_HEAD_1 << BIT_SHIFT_BCN_HEAD_1)
+#define BIT_CLEAR_BCN_HEAD_1(x) ((x) & (~BITS_BCN_HEAD_1))
+#define BIT_GET_BCN_HEAD_1(x) \
+ (((x) >> BIT_SHIFT_BCN_HEAD_1) & BIT_MASK_BCN_HEAD_1)
+#define BIT_SET_BCN_HEAD_1(x, v) (BIT_CLEAR_BCN_HEAD_1(x) | BIT_BCN_HEAD_1(v))
-/* 2 REG_H2C_TAIL (Offset 0x0248) */
+#endif
+#if (HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_H2C_TAIL 0
-#define BIT_MASK_H2C_TAIL 0x3ffff
-#define BIT_H2C_TAIL(x) (((x) & BIT_MASK_H2C_TAIL) << BIT_SHIFT_H2C_TAIL)
-#define BIT_GET_H2C_TAIL(x) (((x) >> BIT_SHIFT_H2C_TAIL) & BIT_MASK_H2C_TAIL)
+/* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */
+#define BIT_RST_PGSUB_CNT BIT(1)
-/* 2 REG_H2C_READ_ADDR (Offset 0x024C) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_H2C_READ_ADDR 0
-#define BIT_MASK_H2C_READ_ADDR 0x3ffff
-#define BIT_H2C_READ_ADDR(x) (((x) & BIT_MASK_H2C_READ_ADDR) << BIT_SHIFT_H2C_READ_ADDR)
-#define BIT_GET_H2C_READ_ADDR(x) (((x) >> BIT_SHIFT_H2C_READ_ADDR) & BIT_MASK_H2C_READ_ADDR)
+/* 2 REG_DWBCN1_CTRL (Offset 0x0228) */
+#define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO 0
+#define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO 0xff
+#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO(x) \
+ (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO) \
+ << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO)
+#define BITS_MAX_TX_PKT_FOR_USB_AND_SDIO \
+ (BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO \
+ << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO)
+#define BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO(x) \
+ ((x) & (~BITS_MAX_TX_PKT_FOR_USB_AND_SDIO))
+#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO(x) \
+ (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO) & \
+ BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO)
+#define BIT_SET_MAX_TX_PKT_FOR_USB_AND_SDIO(x, v) \
+ (BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO(x) | \
+ BIT_MAX_TX_PKT_FOR_USB_AND_SDIO(v))
-/* 2 REG_H2C_WR_ADDR (Offset 0x0250) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_H2C_WR_ADDR 0
-#define BIT_MASK_H2C_WR_ADDR 0x3ffff
-#define BIT_H2C_WR_ADDR(x) (((x) & BIT_MASK_H2C_WR_ADDR) << BIT_SHIFT_H2C_WR_ADDR)
-#define BIT_GET_H2C_WR_ADDR(x) (((x) >> BIT_SHIFT_H2C_WR_ADDR) & BIT_MASK_H2C_WR_ADDR)
+/* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */
+#define BIT_SHIFT_TXPKTNUM_H_V1 0
+#define BIT_MASK_TXPKTNUM_H_V1 0xffff
+#define BIT_TXPKTNUM_H_V1(x) \
+ (((x) & BIT_MASK_TXPKTNUM_H_V1) << BIT_SHIFT_TXPKTNUM_H_V1)
+#define BITS_TXPKTNUM_H_V1 (BIT_MASK_TXPKTNUM_H_V1 << BIT_SHIFT_TXPKTNUM_H_V1)
+#define BIT_CLEAR_TXPKTNUM_H_V1(x) ((x) & (~BITS_TXPKTNUM_H_V1))
+#define BIT_GET_TXPKTNUM_H_V1(x) \
+ (((x) >> BIT_SHIFT_TXPKTNUM_H_V1) & BIT_MASK_TXPKTNUM_H_V1)
+#define BIT_SET_TXPKTNUM_H_V1(x, v) \
+ (BIT_CLEAR_TXPKTNUM_H_V1(x) | BIT_TXPKTNUM_H_V1(v))
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
+/* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */
-/* 2 REG_H2C_INFO (Offset 0x0254) */
+#define BIT_SHIFT_TXPKTNUM_V2 0
+#define BIT_MASK_TXPKTNUM_V2 0xffff
+#define BIT_TXPKTNUM_V2(x) \
+ (((x) & BIT_MASK_TXPKTNUM_V2) << BIT_SHIFT_TXPKTNUM_V2)
+#define BITS_TXPKTNUM_V2 (BIT_MASK_TXPKTNUM_V2 << BIT_SHIFT_TXPKTNUM_V2)
+#define BIT_CLEAR_TXPKTNUM_V2(x) ((x) & (~BITS_TXPKTNUM_V2))
+#define BIT_GET_TXPKTNUM_V2(x) \
+ (((x) >> BIT_SHIFT_TXPKTNUM_V2) & BIT_MASK_TXPKTNUM_V2)
+#define BIT_SET_TXPKTNUM_V2(x, v) \
+ (BIT_CLEAR_TXPKTNUM_V2(x) | BIT_TXPKTNUM_V2(v))
+#endif
-#define BIT_SHIFT_VI_PUB_LIMIT 16
-#define BIT_MASK_VI_PUB_LIMIT 0xfff
-#define BIT_VI_PUB_LIMIT(x) (((x) & BIT_MASK_VI_PUB_LIMIT) << BIT_SHIFT_VI_PUB_LIMIT)
-#define BIT_GET_VI_PUB_LIMIT(x) (((x) >> BIT_SHIFT_VI_PUB_LIMIT) & BIT_MASK_VI_PUB_LIMIT)
+#if (HALMAC_8822C_SUPPORT)
+/* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */
-#define BIT_SHIFT_BK_PUB_LIMIT 16
-#define BIT_MASK_BK_PUB_LIMIT 0xfff
-#define BIT_BK_PUB_LIMIT(x) (((x) & BIT_MASK_BK_PUB_LIMIT) << BIT_SHIFT_BK_PUB_LIMIT)
-#define BIT_GET_BK_PUB_LIMIT(x) (((x) >> BIT_SHIFT_BK_PUB_LIMIT) & BIT_MASK_BK_PUB_LIMIT)
+#define BIT_SHIFT_TXPKTNUM_V3 0
+#define BIT_MASK_TXPKTNUM_V3 0xfff
+#define BIT_TXPKTNUM_V3(x) \
+ (((x) & BIT_MASK_TXPKTNUM_V3) << BIT_SHIFT_TXPKTNUM_V3)
+#define BITS_TXPKTNUM_V3 (BIT_MASK_TXPKTNUM_V3 << BIT_SHIFT_TXPKTNUM_V3)
+#define BIT_CLEAR_TXPKTNUM_V3(x) ((x) & (~BITS_TXPKTNUM_V3))
+#define BIT_GET_TXPKTNUM_V3(x) \
+ (((x) >> BIT_SHIFT_TXPKTNUM_V3) & BIT_MASK_TXPKTNUM_V3)
+#define BIT_SET_TXPKTNUM_V3(x, v) \
+ (BIT_CLEAR_TXPKTNUM_V3(x) | BIT_TXPKTNUM_V3(v))
-#define BIT_EXQ_EN_PUBLIC_LIMIT BIT(11)
-#define BIT_NPQ_EN_PUBLIC_LIMIT BIT(10)
-#define BIT_LPQ_EN_PUBLIC_LIMIT BIT(9)
-#define BIT_HPQ_EN_PUBLIC_LIMIT BIT(8)
+#define BIT_PGSUB_CNT_EN BIT(0)
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_RQPN_CTRL_2 (Offset 0x022C) */
+#define BIT_EX2Q_PUBLIC_DIS_V1 BIT(21)
+#define BIT_EX1Q_PUBLIC_DIS_V1 BIT(20)
-/* 2 REG_H2C_INFO (Offset 0x0254) */
+#endif
-#define BIT_H2C_SPACE_VLD BIT(3)
-#define BIT_H2C_WR_ADDR_RST BIT(2)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_H2C_LEN_SEL 0
-#define BIT_MASK_H2C_LEN_SEL 0x3
-#define BIT_H2C_LEN_SEL(x) (((x) & BIT_MASK_H2C_LEN_SEL) << BIT_SHIFT_H2C_LEN_SEL)
-#define BIT_GET_H2C_LEN_SEL(x) (((x) >> BIT_SHIFT_H2C_LEN_SEL) & BIT_MASK_H2C_LEN_SEL)
+/* 2 REG_RQPN_CTRL_2 (Offset 0x022C) */
+#define BIT_EXQ_PUBLIC_DIS_V1 BIT(19)
+#define BIT_NPQ_PUBLIC_DIS_V1 BIT(18)
+#define BIT_LPQ_PUBLIC_DIS_V1 BIT(17)
+#define BIT_HPQ_PUBLIC_DIS_V1 BIT(16)
#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_RQPN_CTRL_2 (Offset 0x022C) */
+#define BIT_SDIO_TXAGG_ALIGN_ADJUST_EN BIT(15)
-/* 2 REG_H2C_INFO (Offset 0x0254) */
+#define BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE 0
+#define BIT_MASK_SDIO_TXAGG_ALIGN_SIZE 0xfff
+#define BIT_SDIO_TXAGG_ALIGN_SIZE(x) \
+ (((x) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE) \
+ << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE)
+#define BITS_SDIO_TXAGG_ALIGN_SIZE \
+ (BIT_MASK_SDIO_TXAGG_ALIGN_SIZE << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE)
+#define BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE(x) ((x) & (~BITS_SDIO_TXAGG_ALIGN_SIZE))
+#define BIT_GET_SDIO_TXAGG_ALIGN_SIZE(x) \
+ (((x) >> BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE) & \
+ BIT_MASK_SDIO_TXAGG_ALIGN_SIZE)
+#define BIT_SET_SDIO_TXAGG_ALIGN_SIZE(x, v) \
+ (BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE(x) | BIT_SDIO_TXAGG_ALIGN_SIZE(v))
+#endif
-#define BIT_SHIFT_VO_PUB_LIMIT 0
-#define BIT_MASK_VO_PUB_LIMIT 0xfff
-#define BIT_VO_PUB_LIMIT(x) (((x) & BIT_MASK_VO_PUB_LIMIT) << BIT_SHIFT_VO_PUB_LIMIT)
-#define BIT_GET_VO_PUB_LIMIT(x) (((x) >> BIT_SHIFT_VO_PUB_LIMIT) & BIT_MASK_VO_PUB_LIMIT)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+/* 2 REG_FIFOPAGE_INFO_1 (Offset 0x0230) */
-#define BIT_SHIFT_BE_PUB_LIMIT 0
-#define BIT_MASK_BE_PUB_LIMIT 0xfff
-#define BIT_BE_PUB_LIMIT(x) (((x) & BIT_MASK_BE_PUB_LIMIT) << BIT_SHIFT_BE_PUB_LIMIT)
-#define BIT_GET_BE_PUB_LIMIT(x) (((x) >> BIT_SHIFT_BE_PUB_LIMIT) & BIT_MASK_BE_PUB_LIMIT)
+#define BIT_SHIFT_HPQ_AVAL_PG_V1 16
+#define BIT_MASK_HPQ_AVAL_PG_V1 0xfff
+#define BIT_HPQ_AVAL_PG_V1(x) \
+ (((x) & BIT_MASK_HPQ_AVAL_PG_V1) << BIT_SHIFT_HPQ_AVAL_PG_V1)
+#define BITS_HPQ_AVAL_PG_V1 \
+ (BIT_MASK_HPQ_AVAL_PG_V1 << BIT_SHIFT_HPQ_AVAL_PG_V1)
+#define BIT_CLEAR_HPQ_AVAL_PG_V1(x) ((x) & (~BITS_HPQ_AVAL_PG_V1))
+#define BIT_GET_HPQ_AVAL_PG_V1(x) \
+ (((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1) & BIT_MASK_HPQ_AVAL_PG_V1)
+#define BIT_SET_HPQ_AVAL_PG_V1(x, v) \
+ (BIT_CLEAR_HPQ_AVAL_PG_V1(x) | BIT_HPQ_AVAL_PG_V1(v))
+
+#define BIT_SHIFT_HPQ_V1 0
+#define BIT_MASK_HPQ_V1 0xfff
+#define BIT_HPQ_V1(x) (((x) & BIT_MASK_HPQ_V1) << BIT_SHIFT_HPQ_V1)
+#define BITS_HPQ_V1 (BIT_MASK_HPQ_V1 << BIT_SHIFT_HPQ_V1)
+#define BIT_CLEAR_HPQ_V1(x) ((x) & (~BITS_HPQ_V1))
+#define BIT_GET_HPQ_V1(x) (((x) >> BIT_SHIFT_HPQ_V1) & BIT_MASK_HPQ_V1)
+#define BIT_SET_HPQ_V1(x, v) (BIT_CLEAR_HPQ_V1(x) | BIT_HPQ_V1(v))
+/* 2 REG_FIFOPAGE_INFO_2 (Offset 0x0234) */
-#endif
+#define BIT_SHIFT_LPQ_AVAL_PG_V1 16
+#define BIT_MASK_LPQ_AVAL_PG_V1 0xfff
+#define BIT_LPQ_AVAL_PG_V1(x) \
+ (((x) & BIT_MASK_LPQ_AVAL_PG_V1) << BIT_SHIFT_LPQ_AVAL_PG_V1)
+#define BITS_LPQ_AVAL_PG_V1 \
+ (BIT_MASK_LPQ_AVAL_PG_V1 << BIT_SHIFT_LPQ_AVAL_PG_V1)
+#define BIT_CLEAR_LPQ_AVAL_PG_V1(x) ((x) & (~BITS_LPQ_AVAL_PG_V1))
+#define BIT_GET_LPQ_AVAL_PG_V1(x) \
+ (((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1) & BIT_MASK_LPQ_AVAL_PG_V1)
+#define BIT_SET_LPQ_AVAL_PG_V1(x, v) \
+ (BIT_CLEAR_LPQ_AVAL_PG_V1(x) | BIT_LPQ_AVAL_PG_V1(v))
+#define BIT_SHIFT_LPQ_V1 0
+#define BIT_MASK_LPQ_V1 0xfff
+#define BIT_LPQ_V1(x) (((x) & BIT_MASK_LPQ_V1) << BIT_SHIFT_LPQ_V1)
+#define BITS_LPQ_V1 (BIT_MASK_LPQ_V1 << BIT_SHIFT_LPQ_V1)
+#define BIT_CLEAR_LPQ_V1(x) ((x) & (~BITS_LPQ_V1))
+#define BIT_GET_LPQ_V1(x) (((x) >> BIT_SHIFT_LPQ_V1) & BIT_MASK_LPQ_V1)
+#define BIT_SET_LPQ_V1(x, v) (BIT_CLEAR_LPQ_V1(x) | BIT_LPQ_V1(v))
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */
+/* 2 REG_FIFOPAGE_INFO_3 (Offset 0x0238) */
-#define BIT_USB_RXDMA_AGG_EN BIT(31)
+#define BIT_SHIFT_NPQ_AVAL_PG_V1 16
+#define BIT_MASK_NPQ_AVAL_PG_V1 0xfff
+#define BIT_NPQ_AVAL_PG_V1(x) \
+ (((x) & BIT_MASK_NPQ_AVAL_PG_V1) << BIT_SHIFT_NPQ_AVAL_PG_V1)
+#define BITS_NPQ_AVAL_PG_V1 \
+ (BIT_MASK_NPQ_AVAL_PG_V1 << BIT_SHIFT_NPQ_AVAL_PG_V1)
+#define BIT_CLEAR_NPQ_AVAL_PG_V1(x) ((x) & (~BITS_NPQ_AVAL_PG_V1))
+#define BIT_GET_NPQ_AVAL_PG_V1(x) \
+ (((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1) & BIT_MASK_NPQ_AVAL_PG_V1)
+#define BIT_SET_NPQ_AVAL_PG_V1(x, v) \
+ (BIT_CLEAR_NPQ_AVAL_PG_V1(x) | BIT_NPQ_AVAL_PG_V1(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
+/* 2 REG_FIFOPAGE_INFO_3 (Offset 0x0238) */
-/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */
+#define BIT_SHIFT_NPQ_V1 0
+#define BIT_MASK_NPQ_V1 0xfff
+#define BIT_NPQ_V1(x) (((x) & BIT_MASK_NPQ_V1) << BIT_SHIFT_NPQ_V1)
+#define BITS_NPQ_V1 (BIT_MASK_NPQ_V1 << BIT_SHIFT_NPQ_V1)
+#define BIT_CLEAR_NPQ_V1(x) ((x) & (~BITS_NPQ_V1))
+#define BIT_GET_NPQ_V1(x) (((x) >> BIT_SHIFT_NPQ_V1) & BIT_MASK_NPQ_V1)
+#define BIT_SET_NPQ_V1(x, v) (BIT_CLEAR_NPQ_V1(x) | BIT_NPQ_V1(v))
-#define BIT_DMA_STORE_MODE BIT(31)
-#define BIT_EN_FW_ADD BIT(30)
-#define BIT_EN_PRE_CALC BIT(29)
-#define BIT_RXAGG_SW_EN BIT(28)
+/* 2 REG_FIFOPAGE_INFO_4 (Offset 0x023C) */
-#endif
+#define BIT_SHIFT_EXQ_AVAL_PG_V1 16
+#define BIT_MASK_EXQ_AVAL_PG_V1 0xfff
+#define BIT_EXQ_AVAL_PG_V1(x) \
+ (((x) & BIT_MASK_EXQ_AVAL_PG_V1) << BIT_SHIFT_EXQ_AVAL_PG_V1)
+#define BITS_EXQ_AVAL_PG_V1 \
+ (BIT_MASK_EXQ_AVAL_PG_V1 << BIT_SHIFT_EXQ_AVAL_PG_V1)
+#define BIT_CLEAR_EXQ_AVAL_PG_V1(x) ((x) & (~BITS_EXQ_AVAL_PG_V1))
+#define BIT_GET_EXQ_AVAL_PG_V1(x) \
+ (((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1) & BIT_MASK_EXQ_AVAL_PG_V1)
+#define BIT_SET_EXQ_AVAL_PG_V1(x, v) \
+ (BIT_CLEAR_EXQ_AVAL_PG_V1(x) | BIT_EXQ_AVAL_PG_V1(v))
+
+#define BIT_SHIFT_EXQ_V1 0
+#define BIT_MASK_EXQ_V1 0xfff
+#define BIT_EXQ_V1(x) (((x) & BIT_MASK_EXQ_V1) << BIT_SHIFT_EXQ_V1)
+#define BITS_EXQ_V1 (BIT_MASK_EXQ_V1 << BIT_SHIFT_EXQ_V1)
+#define BIT_CLEAR_EXQ_V1(x) ((x) & (~BITS_EXQ_V1))
+#define BIT_GET_EXQ_V1(x) (((x) >> BIT_SHIFT_EXQ_V1) & BIT_MASK_EXQ_V1)
+#define BIT_SET_EXQ_V1(x, v) (BIT_CLEAR_EXQ_V1(x) | BIT_EXQ_V1(v))
+/* 2 REG_FIFOPAGE_INFO_5 (Offset 0x0240) */
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#define BIT_SHIFT_PUBQ_AVAL_PG_V1 16
+#define BIT_MASK_PUBQ_AVAL_PG_V1 0xfff
+#define BIT_PUBQ_AVAL_PG_V1(x) \
+ (((x) & BIT_MASK_PUBQ_AVAL_PG_V1) << BIT_SHIFT_PUBQ_AVAL_PG_V1)
+#define BITS_PUBQ_AVAL_PG_V1 \
+ (BIT_MASK_PUBQ_AVAL_PG_V1 << BIT_SHIFT_PUBQ_AVAL_PG_V1)
+#define BIT_CLEAR_PUBQ_AVAL_PG_V1(x) ((x) & (~BITS_PUBQ_AVAL_PG_V1))
+#define BIT_GET_PUBQ_AVAL_PG_V1(x) \
+ (((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1) & BIT_MASK_PUBQ_AVAL_PG_V1)
+#define BIT_SET_PUBQ_AVAL_PG_V1(x, v) \
+ (BIT_CLEAR_PUBQ_AVAL_PG_V1(x) | BIT_PUBQ_AVAL_PG_V1(v))
+#endif
-/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */
+#if (HALMAC_8814B_SUPPORT)
+/* 2 REG_TX_AGG_ALIGN (Offset 0x0240) */
-#define BIT_SHIFT_RXDMA_AGG_OLD_MOD 24
-#define BIT_MASK_RXDMA_AGG_OLD_MOD 0xff
-#define BIT_RXDMA_AGG_OLD_MOD(x) (((x) & BIT_MASK_RXDMA_AGG_OLD_MOD) << BIT_SHIFT_RXDMA_AGG_OLD_MOD)
-#define BIT_GET_RXDMA_AGG_OLD_MOD(x) (((x) >> BIT_SHIFT_RXDMA_AGG_OLD_MOD) & BIT_MASK_RXDMA_AGG_OLD_MOD)
+#define BIT_SHIFT_HW_FLOW_CTL_EN 16
+#define BIT_MASK_HW_FLOW_CTL_EN 0xffff
+#define BIT_HW_FLOW_CTL_EN(x) \
+ (((x) & BIT_MASK_HW_FLOW_CTL_EN) << BIT_SHIFT_HW_FLOW_CTL_EN)
+#define BITS_HW_FLOW_CTL_EN \
+ (BIT_MASK_HW_FLOW_CTL_EN << BIT_SHIFT_HW_FLOW_CTL_EN)
+#define BIT_CLEAR_HW_FLOW_CTL_EN(x) ((x) & (~BITS_HW_FLOW_CTL_EN))
+#define BIT_GET_HW_FLOW_CTL_EN(x) \
+ (((x) >> BIT_SHIFT_HW_FLOW_CTL_EN) & BIT_MASK_HW_FLOW_CTL_EN)
+#define BIT_SET_HW_FLOW_CTL_EN(x, v) \
+ (BIT_CLEAR_HW_FLOW_CTL_EN(x) | BIT_HW_FLOW_CTL_EN(v))
+#define BIT_SDIO_TXAGG_ALIGN_ADJUST_EN_V1 BIT(15)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_FIFOPAGE_INFO_5 (Offset 0x0240) */
+#define BIT_SHIFT_PUBQ_V1 0
+#define BIT_MASK_PUBQ_V1 0xfff
+#define BIT_PUBQ_V1(x) (((x) & BIT_MASK_PUBQ_V1) << BIT_SHIFT_PUBQ_V1)
+#define BITS_PUBQ_V1 (BIT_MASK_PUBQ_V1 << BIT_SHIFT_PUBQ_V1)
+#define BIT_CLEAR_PUBQ_V1(x) ((x) & (~BITS_PUBQ_V1))
+#define BIT_GET_PUBQ_V1(x) (((x) >> BIT_SHIFT_PUBQ_V1) & BIT_MASK_PUBQ_V1)
+#define BIT_SET_PUBQ_V1(x, v) (BIT_CLEAR_PUBQ_V1(x) | BIT_PUBQ_V1(v))
-/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_PKT_NUM_WOL 16
-#define BIT_MASK_PKT_NUM_WOL 0xff
-#define BIT_PKT_NUM_WOL(x) (((x) & BIT_MASK_PKT_NUM_WOL) << BIT_SHIFT_PKT_NUM_WOL)
-#define BIT_GET_PKT_NUM_WOL(x) (((x) >> BIT_SHIFT_PKT_NUM_WOL) & BIT_MASK_PKT_NUM_WOL)
+/* 2 REG_TX_AGG_ALIGN (Offset 0x0240) */
+#define BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1 0
+#define BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1 0xfff
+#define BIT_SDIO_TXAGG_ALIGN_SIZE_V1(x) \
+ (((x) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1) \
+ << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1)
+#define BITS_SDIO_TXAGG_ALIGN_SIZE_V1 \
+ (BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1 \
+ << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1)
+#define BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_V1(x) \
+ ((x) & (~BITS_SDIO_TXAGG_ALIGN_SIZE_V1))
+#define BIT_GET_SDIO_TXAGG_ALIGN_SIZE_V1(x) \
+ (((x) >> BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1) & \
+ BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1)
+#define BIT_SET_SDIO_TXAGG_ALIGN_SIZE_V1(x, v) \
+ (BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_V1(x) | \
+ BIT_SDIO_TXAGG_ALIGN_SIZE_V1(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_H2C_HEAD (Offset 0x0244) */
+#define BIT_SHIFT_H2C_HEAD 0
+#define BIT_MASK_H2C_HEAD 0x3ffff
+#define BIT_H2C_HEAD(x) (((x) & BIT_MASK_H2C_HEAD) << BIT_SHIFT_H2C_HEAD)
+#define BITS_H2C_HEAD (BIT_MASK_H2C_HEAD << BIT_SHIFT_H2C_HEAD)
+#define BIT_CLEAR_H2C_HEAD(x) ((x) & (~BITS_H2C_HEAD))
+#define BIT_GET_H2C_HEAD(x) (((x) >> BIT_SHIFT_H2C_HEAD) & BIT_MASK_H2C_HEAD)
+#define BIT_SET_H2C_HEAD(x, v) (BIT_CLEAR_H2C_HEAD(x) | BIT_H2C_HEAD(v))
-/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_DMA_AGG_TO_V1 8
-#define BIT_MASK_DMA_AGG_TO_V1 0xff
-#define BIT_DMA_AGG_TO_V1(x) (((x) & BIT_MASK_DMA_AGG_TO_V1) << BIT_SHIFT_DMA_AGG_TO_V1)
-#define BIT_GET_DMA_AGG_TO_V1(x) (((x) >> BIT_SHIFT_DMA_AGG_TO_V1) & BIT_MASK_DMA_AGG_TO_V1)
+/* 2 REG_H2C_HEAD (Offset 0x0244) */
+#define BIT_SHIFT_H2C_HEAD_V1 0
+#define BIT_MASK_H2C_HEAD_V1 0x7ffff
+#define BIT_H2C_HEAD_V1(x) \
+ (((x) & BIT_MASK_H2C_HEAD_V1) << BIT_SHIFT_H2C_HEAD_V1)
+#define BITS_H2C_HEAD_V1 (BIT_MASK_H2C_HEAD_V1 << BIT_SHIFT_H2C_HEAD_V1)
+#define BIT_CLEAR_H2C_HEAD_V1(x) ((x) & (~BITS_H2C_HEAD_V1))
+#define BIT_GET_H2C_HEAD_V1(x) \
+ (((x) >> BIT_SHIFT_H2C_HEAD_V1) & BIT_MASK_H2C_HEAD_V1)
+#define BIT_SET_H2C_HEAD_V1(x, v) \
+ (BIT_CLEAR_H2C_HEAD_V1(x) | BIT_H2C_HEAD_V1(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_H2C_TAIL (Offset 0x0248) */
+#define BIT_SHIFT_H2C_TAIL 0
+#define BIT_MASK_H2C_TAIL 0x3ffff
+#define BIT_H2C_TAIL(x) (((x) & BIT_MASK_H2C_TAIL) << BIT_SHIFT_H2C_TAIL)
+#define BITS_H2C_TAIL (BIT_MASK_H2C_TAIL << BIT_SHIFT_H2C_TAIL)
+#define BIT_CLEAR_H2C_TAIL(x) ((x) & (~BITS_H2C_TAIL))
+#define BIT_GET_H2C_TAIL(x) (((x) >> BIT_SHIFT_H2C_TAIL) & BIT_MASK_H2C_TAIL)
+#define BIT_SET_H2C_TAIL(x, v) (BIT_CLEAR_H2C_TAIL(x) | BIT_H2C_TAIL(v))
-/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_RXDMA_AGG_TIMEOUT_TH 8
-#define BIT_MASK_RXDMA_AGG_TIMEOUT_TH 0xff
-#define BIT_RXDMA_AGG_TIMEOUT_TH(x) (((x) & BIT_MASK_RXDMA_AGG_TIMEOUT_TH) << BIT_SHIFT_RXDMA_AGG_TIMEOUT_TH)
-#define BIT_GET_RXDMA_AGG_TIMEOUT_TH(x) (((x) >> BIT_SHIFT_RXDMA_AGG_TIMEOUT_TH) & BIT_MASK_RXDMA_AGG_TIMEOUT_TH)
+/* 2 REG_H2C_TAIL (Offset 0x0248) */
+#define BIT_SHIFT_H2C_TAIL_V1 0
+#define BIT_MASK_H2C_TAIL_V1 0x7ffff
+#define BIT_H2C_TAIL_V1(x) \
+ (((x) & BIT_MASK_H2C_TAIL_V1) << BIT_SHIFT_H2C_TAIL_V1)
+#define BITS_H2C_TAIL_V1 (BIT_MASK_H2C_TAIL_V1 << BIT_SHIFT_H2C_TAIL_V1)
+#define BIT_CLEAR_H2C_TAIL_V1(x) ((x) & (~BITS_H2C_TAIL_V1))
+#define BIT_GET_H2C_TAIL_V1(x) \
+ (((x) >> BIT_SHIFT_H2C_TAIL_V1) & BIT_MASK_H2C_TAIL_V1)
+#define BIT_SET_H2C_TAIL_V1(x, v) \
+ (BIT_CLEAR_H2C_TAIL_V1(x) | BIT_H2C_TAIL_V1(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_H2C_READ_ADDR (Offset 0x024C) */
+#define BIT_SHIFT_H2C_READ_ADDR 0
+#define BIT_MASK_H2C_READ_ADDR 0x3ffff
+#define BIT_H2C_READ_ADDR(x) \
+ (((x) & BIT_MASK_H2C_READ_ADDR) << BIT_SHIFT_H2C_READ_ADDR)
+#define BITS_H2C_READ_ADDR (BIT_MASK_H2C_READ_ADDR << BIT_SHIFT_H2C_READ_ADDR)
+#define BIT_CLEAR_H2C_READ_ADDR(x) ((x) & (~BITS_H2C_READ_ADDR))
+#define BIT_GET_H2C_READ_ADDR(x) \
+ (((x) >> BIT_SHIFT_H2C_READ_ADDR) & BIT_MASK_H2C_READ_ADDR)
+#define BIT_SET_H2C_READ_ADDR(x, v) \
+ (BIT_CLEAR_H2C_READ_ADDR(x) | BIT_H2C_READ_ADDR(v))
-/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_DMA_AGG_TO 8
-#define BIT_MASK_DMA_AGG_TO 0xf
-#define BIT_DMA_AGG_TO(x) (((x) & BIT_MASK_DMA_AGG_TO) << BIT_SHIFT_DMA_AGG_TO)
-#define BIT_GET_DMA_AGG_TO(x) (((x) >> BIT_SHIFT_DMA_AGG_TO) & BIT_MASK_DMA_AGG_TO)
+/* 2 REG_H2C_READ_ADDR (Offset 0x024C) */
+#define BIT_SHIFT_H2C_READ_ADDR_V1 0
+#define BIT_MASK_H2C_READ_ADDR_V1 0x7ffff
+#define BIT_H2C_READ_ADDR_V1(x) \
+ (((x) & BIT_MASK_H2C_READ_ADDR_V1) << BIT_SHIFT_H2C_READ_ADDR_V1)
+#define BITS_H2C_READ_ADDR_V1 \
+ (BIT_MASK_H2C_READ_ADDR_V1 << BIT_SHIFT_H2C_READ_ADDR_V1)
+#define BIT_CLEAR_H2C_READ_ADDR_V1(x) ((x) & (~BITS_H2C_READ_ADDR_V1))
+#define BIT_GET_H2C_READ_ADDR_V1(x) \
+ (((x) >> BIT_SHIFT_H2C_READ_ADDR_V1) & BIT_MASK_H2C_READ_ADDR_V1)
+#define BIT_SET_H2C_READ_ADDR_V1(x, v) \
+ (BIT_CLEAR_H2C_READ_ADDR_V1(x) | BIT_H2C_READ_ADDR_V1(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_H2C_WR_ADDR (Offset 0x0250) */
+#define BIT_SHIFT_H2C_WR_ADDR 0
+#define BIT_MASK_H2C_WR_ADDR 0x3ffff
+#define BIT_H2C_WR_ADDR(x) \
+ (((x) & BIT_MASK_H2C_WR_ADDR) << BIT_SHIFT_H2C_WR_ADDR)
+#define BITS_H2C_WR_ADDR (BIT_MASK_H2C_WR_ADDR << BIT_SHIFT_H2C_WR_ADDR)
+#define BIT_CLEAR_H2C_WR_ADDR(x) ((x) & (~BITS_H2C_WR_ADDR))
+#define BIT_GET_H2C_WR_ADDR(x) \
+ (((x) >> BIT_SHIFT_H2C_WR_ADDR) & BIT_MASK_H2C_WR_ADDR)
+#define BIT_SET_H2C_WR_ADDR(x, v) \
+ (BIT_CLEAR_H2C_WR_ADDR(x) | BIT_H2C_WR_ADDR(v))
-/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_RXDMA_AGG_PG_TH_V1 0
-#define BIT_MASK_RXDMA_AGG_PG_TH_V1 0xf
-#define BIT_RXDMA_AGG_PG_TH_V1(x) (((x) & BIT_MASK_RXDMA_AGG_PG_TH_V1) << BIT_SHIFT_RXDMA_AGG_PG_TH_V1)
-#define BIT_GET_RXDMA_AGG_PG_TH_V1(x) (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_V1) & BIT_MASK_RXDMA_AGG_PG_TH_V1)
+/* 2 REG_H2C_WR_ADDR (Offset 0x0250) */
+#define BIT_SHIFT_H2C_WR_ADDR_V1 0
+#define BIT_MASK_H2C_WR_ADDR_V1 0x7ffff
+#define BIT_H2C_WR_ADDR_V1(x) \
+ (((x) & BIT_MASK_H2C_WR_ADDR_V1) << BIT_SHIFT_H2C_WR_ADDR_V1)
+#define BITS_H2C_WR_ADDR_V1 \
+ (BIT_MASK_H2C_WR_ADDR_V1 << BIT_SHIFT_H2C_WR_ADDR_V1)
+#define BIT_CLEAR_H2C_WR_ADDR_V1(x) ((x) & (~BITS_H2C_WR_ADDR_V1))
+#define BIT_GET_H2C_WR_ADDR_V1(x) \
+ (((x) >> BIT_SHIFT_H2C_WR_ADDR_V1) & BIT_MASK_H2C_WR_ADDR_V1)
+#define BIT_SET_H2C_WR_ADDR_V1(x, v) \
+ (BIT_CLEAR_H2C_WR_ADDR_V1(x) | BIT_H2C_WR_ADDR_V1(v))
#endif
-
#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_H2C_INFO (Offset 0x0254) */
+
+#define BIT_SHIFT_VI_PUB_LIMIT 16
+#define BIT_MASK_VI_PUB_LIMIT 0xfff
+#define BIT_VI_PUB_LIMIT(x) \
+ (((x) & BIT_MASK_VI_PUB_LIMIT) << BIT_SHIFT_VI_PUB_LIMIT)
+#define BITS_VI_PUB_LIMIT (BIT_MASK_VI_PUB_LIMIT << BIT_SHIFT_VI_PUB_LIMIT)
+#define BIT_CLEAR_VI_PUB_LIMIT(x) ((x) & (~BITS_VI_PUB_LIMIT))
+#define BIT_GET_VI_PUB_LIMIT(x) \
+ (((x) >> BIT_SHIFT_VI_PUB_LIMIT) & BIT_MASK_VI_PUB_LIMIT)
+#define BIT_SET_VI_PUB_LIMIT(x, v) \
+ (BIT_CLEAR_VI_PUB_LIMIT(x) | BIT_VI_PUB_LIMIT(v))
-/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */
+#define BIT_SHIFT_BK_PUB_LIMIT 16
+#define BIT_MASK_BK_PUB_LIMIT 0xfff
+#define BIT_BK_PUB_LIMIT(x) \
+ (((x) & BIT_MASK_BK_PUB_LIMIT) << BIT_SHIFT_BK_PUB_LIMIT)
+#define BITS_BK_PUB_LIMIT (BIT_MASK_BK_PUB_LIMIT << BIT_SHIFT_BK_PUB_LIMIT)
+#define BIT_CLEAR_BK_PUB_LIMIT(x) ((x) & (~BITS_BK_PUB_LIMIT))
+#define BIT_GET_BK_PUB_LIMIT(x) \
+ (((x) >> BIT_SHIFT_BK_PUB_LIMIT) & BIT_MASK_BK_PUB_LIMIT)
+#define BIT_SET_BK_PUB_LIMIT(x, v) \
+ (BIT_CLEAR_BK_PUB_LIMIT(x) | BIT_BK_PUB_LIMIT(v))
+
+#endif
+#if (HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_RXDMA_AGG_PG_TH 0
-#define BIT_MASK_RXDMA_AGG_PG_TH 0xff
-#define BIT_RXDMA_AGG_PG_TH(x) (((x) & BIT_MASK_RXDMA_AGG_PG_TH) << BIT_SHIFT_RXDMA_AGG_PG_TH)
-#define BIT_GET_RXDMA_AGG_PG_TH(x) (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH) & BIT_MASK_RXDMA_AGG_PG_TH)
+/* 2 REG_H2C_INFO (Offset 0x0254) */
+#define BIT_EX2Q_EN_PUBLIC_LIMIT BIT(13)
+#define BIT_EX1Q_EN_PUBLIC_LIMIT BIT(12)
#endif
+#if (HALMAC_8197F_SUPPORT)
-#if (HALMAC_8814AMP_SUPPORT)
+/* 2 REG_H2C_INFO (Offset 0x0254) */
+#define BIT_EXQ_EN_PUBLIC_LIMIT BIT(11)
-/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */
+#endif
+#if (HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_RXDMA_AGG_PG_TH_V2 0
-#define BIT_MASK_RXDMA_AGG_PG_TH_V2 0xff
-#define BIT_RXDMA_AGG_PG_TH_V2(x) (((x) & BIT_MASK_RXDMA_AGG_PG_TH_V2) << BIT_SHIFT_RXDMA_AGG_PG_TH_V2)
-#define BIT_GET_RXDMA_AGG_PG_TH_V2(x) (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_V2) & BIT_MASK_RXDMA_AGG_PG_TH_V2)
+/* 2 REG_H2C_INFO (Offset 0x0254) */
+#define BIT_EQ_EN_PUBLIC_LIMIT BIT(11)
#endif
+#if (HALMAC_8197F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_H2C_INFO (Offset 0x0254) */
+#define BIT_NPQ_EN_PUBLIC_LIMIT BIT(10)
-/* 2 REG_RXPKT_NUM (Offset 0x0284) */
+#endif
+#if (HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_RXPKT_NUM 24
-#define BIT_MASK_RXPKT_NUM 0xff
-#define BIT_RXPKT_NUM(x) (((x) & BIT_MASK_RXPKT_NUM) << BIT_SHIFT_RXPKT_NUM)
-#define BIT_GET_RXPKT_NUM(x) (((x) >> BIT_SHIFT_RXPKT_NUM) & BIT_MASK_RXPKT_NUM)
+/* 2 REG_H2C_INFO (Offset 0x0254) */
+#define BIT_NQ_EN_PUBLIC_LIMIT BIT(10)
#endif
+#if (HALMAC_8197F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_H2C_INFO (Offset 0x0254) */
+#define BIT_LPQ_EN_PUBLIC_LIMIT BIT(9)
-/* 2 REG_RXPKT_NUM (Offset 0x0284) */
+#endif
+#if (HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_FW_UPD_RDPTR19_TO_16 20
-#define BIT_MASK_FW_UPD_RDPTR19_TO_16 0xf
-#define BIT_FW_UPD_RDPTR19_TO_16(x) (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16) << BIT_SHIFT_FW_UPD_RDPTR19_TO_16)
-#define BIT_GET_FW_UPD_RDPTR19_TO_16(x) (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16) & BIT_MASK_FW_UPD_RDPTR19_TO_16)
+/* 2 REG_H2C_INFO (Offset 0x0254) */
+#define BIT_LQ_EN_PUBLIC_LIMIT BIT(9)
#endif
+#if (HALMAC_8197F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_H2C_INFO (Offset 0x0254) */
+#define BIT_HPQ_EN_PUBLIC_LIMIT BIT(8)
-/* 2 REG_RXPKT_NUM (Offset 0x0284) */
+#endif
-#define BIT_RXDMA_REQ BIT(19)
-#define BIT_RW_RELEASE_EN BIT(18)
-#define BIT_RXDMA_IDLE BIT(17)
-#define BIT_RXPKT_RELEASE_POLL BIT(16)
+#if (HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_FW_UPD_RDPTR 0
-#define BIT_MASK_FW_UPD_RDPTR 0xffff
-#define BIT_FW_UPD_RDPTR(x) (((x) & BIT_MASK_FW_UPD_RDPTR) << BIT_SHIFT_FW_UPD_RDPTR)
-#define BIT_GET_FW_UPD_RDPTR(x) (((x) >> BIT_SHIFT_FW_UPD_RDPTR) & BIT_MASK_FW_UPD_RDPTR)
+/* 2 REG_H2C_INFO (Offset 0x0254) */
+#define BIT_HQ_EN_PUBLIC_LIMIT BIT(8)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
+/* 2 REG_H2C_INFO (Offset 0x0254) */
-/* 2 REG_RXDMA_STATUS (Offset 0x0288) */
+#define BIT_H2C_SPACE_VLD BIT(3)
+#define BIT_H2C_WR_ADDR_RST BIT(2)
-#define BIT_FC2H_PKT_OVERFLOW BIT(8)
+#define BIT_SHIFT_H2C_LEN_SEL 0
+#define BIT_MASK_H2C_LEN_SEL 0x3
+#define BIT_H2C_LEN_SEL(x) \
+ (((x) & BIT_MASK_H2C_LEN_SEL) << BIT_SHIFT_H2C_LEN_SEL)
+#define BITS_H2C_LEN_SEL (BIT_MASK_H2C_LEN_SEL << BIT_SHIFT_H2C_LEN_SEL)
+#define BIT_CLEAR_H2C_LEN_SEL(x) ((x) & (~BITS_H2C_LEN_SEL))
+#define BIT_GET_H2C_LEN_SEL(x) \
+ (((x) >> BIT_SHIFT_H2C_LEN_SEL) & BIT_MASK_H2C_LEN_SEL)
+#define BIT_SET_H2C_LEN_SEL(x, v) \
+ (BIT_CLEAR_H2C_LEN_SEL(x) | BIT_H2C_LEN_SEL(v))
#endif
+#if (HALMAC_8197F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_H2C_INFO (Offset 0x0254) */
+#define BIT_SHIFT_VO_PUB_LIMIT 0
+#define BIT_MASK_VO_PUB_LIMIT 0xfff
+#define BIT_VO_PUB_LIMIT(x) \
+ (((x) & BIT_MASK_VO_PUB_LIMIT) << BIT_SHIFT_VO_PUB_LIMIT)
+#define BITS_VO_PUB_LIMIT (BIT_MASK_VO_PUB_LIMIT << BIT_SHIFT_VO_PUB_LIMIT)
+#define BIT_CLEAR_VO_PUB_LIMIT(x) ((x) & (~BITS_VO_PUB_LIMIT))
+#define BIT_GET_VO_PUB_LIMIT(x) \
+ (((x) >> BIT_SHIFT_VO_PUB_LIMIT) & BIT_MASK_VO_PUB_LIMIT)
+#define BIT_SET_VO_PUB_LIMIT(x, v) \
+ (BIT_CLEAR_VO_PUB_LIMIT(x) | BIT_VO_PUB_LIMIT(v))
+
+#define BIT_SHIFT_BE_PUB_LIMIT 0
+#define BIT_MASK_BE_PUB_LIMIT 0xfff
+#define BIT_BE_PUB_LIMIT(x) \
+ (((x) & BIT_MASK_BE_PUB_LIMIT) << BIT_SHIFT_BE_PUB_LIMIT)
+#define BITS_BE_PUB_LIMIT (BIT_MASK_BE_PUB_LIMIT << BIT_SHIFT_BE_PUB_LIMIT)
+#define BIT_CLEAR_BE_PUB_LIMIT(x) ((x) & (~BITS_BE_PUB_LIMIT))
+#define BIT_GET_BE_PUB_LIMIT(x) \
+ (((x) >> BIT_SHIFT_BE_PUB_LIMIT) & BIT_MASK_BE_PUB_LIMIT)
+#define BIT_SET_BE_PUB_LIMIT(x, v) \
+ (BIT_CLEAR_BE_PUB_LIMIT(x) | BIT_BE_PUB_LIMIT(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_DMA_OQT_0 (Offset 0x0260) */
+
+#define BIT_SHIFT_TX_OQT_12_FREE_SPACE 24
+#define BIT_MASK_TX_OQT_12_FREE_SPACE 0xff
+#define BIT_TX_OQT_12_FREE_SPACE(x) \
+ (((x) & BIT_MASK_TX_OQT_12_FREE_SPACE) \
+ << BIT_SHIFT_TX_OQT_12_FREE_SPACE)
+#define BITS_TX_OQT_12_FREE_SPACE \
+ (BIT_MASK_TX_OQT_12_FREE_SPACE << BIT_SHIFT_TX_OQT_12_FREE_SPACE)
+#define BIT_CLEAR_TX_OQT_12_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_12_FREE_SPACE))
+#define BIT_GET_TX_OQT_12_FREE_SPACE(x) \
+ (((x) >> BIT_SHIFT_TX_OQT_12_FREE_SPACE) & \
+ BIT_MASK_TX_OQT_12_FREE_SPACE)
+#define BIT_SET_TX_OQT_12_FREE_SPACE(x, v) \
+ (BIT_CLEAR_TX_OQT_12_FREE_SPACE(x) | BIT_TX_OQT_12_FREE_SPACE(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_TQPNT5 (Offset 0x0260) */
+
+#define BIT_SHIFT_EX1Q_HIGH_TH_V1 16
+#define BIT_MASK_EX1Q_HIGH_TH_V1 0xfff
+#define BIT_EX1Q_HIGH_TH_V1(x) \
+ (((x) & BIT_MASK_EX1Q_HIGH_TH_V1) << BIT_SHIFT_EX1Q_HIGH_TH_V1)
+#define BITS_EX1Q_HIGH_TH_V1 \
+ (BIT_MASK_EX1Q_HIGH_TH_V1 << BIT_SHIFT_EX1Q_HIGH_TH_V1)
+#define BIT_CLEAR_EX1Q_HIGH_TH_V1(x) ((x) & (~BITS_EX1Q_HIGH_TH_V1))
+#define BIT_GET_EX1Q_HIGH_TH_V1(x) \
+ (((x) >> BIT_SHIFT_EX1Q_HIGH_TH_V1) & BIT_MASK_EX1Q_HIGH_TH_V1)
+#define BIT_SET_EX1Q_HIGH_TH_V1(x, v) \
+ (BIT_CLEAR_EX1Q_HIGH_TH_V1(x) | BIT_EX1Q_HIGH_TH_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_DMA_OQT_0 (Offset 0x0260) */
+
+#define BIT_SHIFT_TX_OQT_8_11_FREE_SPACE 16
+#define BIT_MASK_TX_OQT_8_11_FREE_SPACE 0xff
+#define BIT_TX_OQT_8_11_FREE_SPACE(x) \
+ (((x) & BIT_MASK_TX_OQT_8_11_FREE_SPACE) \
+ << BIT_SHIFT_TX_OQT_8_11_FREE_SPACE)
+#define BITS_TX_OQT_8_11_FREE_SPACE \
+ (BIT_MASK_TX_OQT_8_11_FREE_SPACE << BIT_SHIFT_TX_OQT_8_11_FREE_SPACE)
+#define BIT_CLEAR_TX_OQT_8_11_FREE_SPACE(x) \
+ ((x) & (~BITS_TX_OQT_8_11_FREE_SPACE))
+#define BIT_GET_TX_OQT_8_11_FREE_SPACE(x) \
+ (((x) >> BIT_SHIFT_TX_OQT_8_11_FREE_SPACE) & \
+ BIT_MASK_TX_OQT_8_11_FREE_SPACE)
+#define BIT_SET_TX_OQT_8_11_FREE_SPACE(x, v) \
+ (BIT_CLEAR_TX_OQT_8_11_FREE_SPACE(x) | BIT_TX_OQT_8_11_FREE_SPACE(v))
+
+#define BIT_SHIFT_TX_OQT_16_FREE_SPACE 16
+#define BIT_MASK_TX_OQT_16_FREE_SPACE 0xff
+#define BIT_TX_OQT_16_FREE_SPACE(x) \
+ (((x) & BIT_MASK_TX_OQT_16_FREE_SPACE) \
+ << BIT_SHIFT_TX_OQT_16_FREE_SPACE)
+#define BITS_TX_OQT_16_FREE_SPACE \
+ (BIT_MASK_TX_OQT_16_FREE_SPACE << BIT_SHIFT_TX_OQT_16_FREE_SPACE)
+#define BIT_CLEAR_TX_OQT_16_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_16_FREE_SPACE))
+#define BIT_GET_TX_OQT_16_FREE_SPACE(x) \
+ (((x) >> BIT_SHIFT_TX_OQT_16_FREE_SPACE) & \
+ BIT_MASK_TX_OQT_16_FREE_SPACE)
+#define BIT_SET_TX_OQT_16_FREE_SPACE(x, v) \
+ (BIT_CLEAR_TX_OQT_16_FREE_SPACE(x) | BIT_TX_OQT_16_FREE_SPACE(v))
+
+#define BIT_SHIFT_TX_OQT_4_7_FREE_SPACE 8
+#define BIT_MASK_TX_OQT_4_7_FREE_SPACE 0xff
+#define BIT_TX_OQT_4_7_FREE_SPACE(x) \
+ (((x) & BIT_MASK_TX_OQT_4_7_FREE_SPACE) \
+ << BIT_SHIFT_TX_OQT_4_7_FREE_SPACE)
+#define BITS_TX_OQT_4_7_FREE_SPACE \
+ (BIT_MASK_TX_OQT_4_7_FREE_SPACE << BIT_SHIFT_TX_OQT_4_7_FREE_SPACE)
+#define BIT_CLEAR_TX_OQT_4_7_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_4_7_FREE_SPACE))
+#define BIT_GET_TX_OQT_4_7_FREE_SPACE(x) \
+ (((x) >> BIT_SHIFT_TX_OQT_4_7_FREE_SPACE) & \
+ BIT_MASK_TX_OQT_4_7_FREE_SPACE)
+#define BIT_SET_TX_OQT_4_7_FREE_SPACE(x, v) \
+ (BIT_CLEAR_TX_OQT_4_7_FREE_SPACE(x) | BIT_TX_OQT_4_7_FREE_SPACE(v))
+
+#define BIT_SHIFT_TX_OQT_14_15_FREE_SPACE 8
+#define BIT_MASK_TX_OQT_14_15_FREE_SPACE 0xff
+#define BIT_TX_OQT_14_15_FREE_SPACE(x) \
+ (((x) & BIT_MASK_TX_OQT_14_15_FREE_SPACE) \
+ << BIT_SHIFT_TX_OQT_14_15_FREE_SPACE)
+#define BITS_TX_OQT_14_15_FREE_SPACE \
+ (BIT_MASK_TX_OQT_14_15_FREE_SPACE << BIT_SHIFT_TX_OQT_14_15_FREE_SPACE)
+#define BIT_CLEAR_TX_OQT_14_15_FREE_SPACE(x) \
+ ((x) & (~BITS_TX_OQT_14_15_FREE_SPACE))
+#define BIT_GET_TX_OQT_14_15_FREE_SPACE(x) \
+ (((x) >> BIT_SHIFT_TX_OQT_14_15_FREE_SPACE) & \
+ BIT_MASK_TX_OQT_14_15_FREE_SPACE)
+#define BIT_SET_TX_OQT_14_15_FREE_SPACE(x, v) \
+ (BIT_CLEAR_TX_OQT_14_15_FREE_SPACE(x) | BIT_TX_OQT_14_15_FREE_SPACE(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_TQPNT5 (Offset 0x0260) */
+
+#define BIT_SHIFT_EX1Q_LOW_TH_V1 0
+#define BIT_MASK_EX1Q_LOW_TH_V1 0xfff
+#define BIT_EX1Q_LOW_TH_V1(x) \
+ (((x) & BIT_MASK_EX1Q_LOW_TH_V1) << BIT_SHIFT_EX1Q_LOW_TH_V1)
+#define BITS_EX1Q_LOW_TH_V1 \
+ (BIT_MASK_EX1Q_LOW_TH_V1 << BIT_SHIFT_EX1Q_LOW_TH_V1)
+#define BIT_CLEAR_EX1Q_LOW_TH_V1(x) ((x) & (~BITS_EX1Q_LOW_TH_V1))
+#define BIT_GET_EX1Q_LOW_TH_V1(x) \
+ (((x) >> BIT_SHIFT_EX1Q_LOW_TH_V1) & BIT_MASK_EX1Q_LOW_TH_V1)
+#define BIT_SET_EX1Q_LOW_TH_V1(x, v) \
+ (BIT_CLEAR_EX1Q_LOW_TH_V1(x) | BIT_EX1Q_LOW_TH_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_DMA_OQT_0 (Offset 0x0260) */
+
+#define BIT_SHIFT_TX_OQT_0_3_FREE_SPACE 0
+#define BIT_MASK_TX_OQT_0_3_FREE_SPACE 0xff
+#define BIT_TX_OQT_0_3_FREE_SPACE(x) \
+ (((x) & BIT_MASK_TX_OQT_0_3_FREE_SPACE) \
+ << BIT_SHIFT_TX_OQT_0_3_FREE_SPACE)
+#define BITS_TX_OQT_0_3_FREE_SPACE \
+ (BIT_MASK_TX_OQT_0_3_FREE_SPACE << BIT_SHIFT_TX_OQT_0_3_FREE_SPACE)
+#define BIT_CLEAR_TX_OQT_0_3_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_0_3_FREE_SPACE))
+#define BIT_GET_TX_OQT_0_3_FREE_SPACE(x) \
+ (((x) >> BIT_SHIFT_TX_OQT_0_3_FREE_SPACE) & \
+ BIT_MASK_TX_OQT_0_3_FREE_SPACE)
+#define BIT_SET_TX_OQT_0_3_FREE_SPACE(x, v) \
+ (BIT_CLEAR_TX_OQT_0_3_FREE_SPACE(x) | BIT_TX_OQT_0_3_FREE_SPACE(v))
+
+#define BIT_SHIFT_TX_OQT_13_FREE_SPACE 0
+#define BIT_MASK_TX_OQT_13_FREE_SPACE 0xff
+#define BIT_TX_OQT_13_FREE_SPACE(x) \
+ (((x) & BIT_MASK_TX_OQT_13_FREE_SPACE) \
+ << BIT_SHIFT_TX_OQT_13_FREE_SPACE)
+#define BITS_TX_OQT_13_FREE_SPACE \
+ (BIT_MASK_TX_OQT_13_FREE_SPACE << BIT_SHIFT_TX_OQT_13_FREE_SPACE)
+#define BIT_CLEAR_TX_OQT_13_FREE_SPACE(x) ((x) & (~BITS_TX_OQT_13_FREE_SPACE))
+#define BIT_GET_TX_OQT_13_FREE_SPACE(x) \
+ (((x) >> BIT_SHIFT_TX_OQT_13_FREE_SPACE) & \
+ BIT_MASK_TX_OQT_13_FREE_SPACE)
+#define BIT_SET_TX_OQT_13_FREE_SPACE(x, v) \
+ (BIT_CLEAR_TX_OQT_13_FREE_SPACE(x) | BIT_TX_OQT_13_FREE_SPACE(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_TQPNT6 (Offset 0x0264) */
+
+#define BIT_SHIFT_EX2Q_HIGH_TH_V1 16
+#define BIT_MASK_EX2Q_HIGH_TH_V1 0xfff
+#define BIT_EX2Q_HIGH_TH_V1(x) \
+ (((x) & BIT_MASK_EX2Q_HIGH_TH_V1) << BIT_SHIFT_EX2Q_HIGH_TH_V1)
+#define BITS_EX2Q_HIGH_TH_V1 \
+ (BIT_MASK_EX2Q_HIGH_TH_V1 << BIT_SHIFT_EX2Q_HIGH_TH_V1)
+#define BIT_CLEAR_EX2Q_HIGH_TH_V1(x) ((x) & (~BITS_EX2Q_HIGH_TH_V1))
+#define BIT_GET_EX2Q_HIGH_TH_V1(x) \
+ (((x) >> BIT_SHIFT_EX2Q_HIGH_TH_V1) & BIT_MASK_EX2Q_HIGH_TH_V1)
+#define BIT_SET_EX2Q_HIGH_TH_V1(x, v) \
+ (BIT_CLEAR_EX2Q_HIGH_TH_V1(x) | BIT_EX2Q_HIGH_TH_V1(v))
+
+#define BIT_SHIFT_EX2Q_LOW_TH_V1 0
+#define BIT_MASK_EX2Q_LOW_TH_V1 0xfff
+#define BIT_EX2Q_LOW_TH_V1(x) \
+ (((x) & BIT_MASK_EX2Q_LOW_TH_V1) << BIT_SHIFT_EX2Q_LOW_TH_V1)
+#define BITS_EX2Q_LOW_TH_V1 \
+ (BIT_MASK_EX2Q_LOW_TH_V1 << BIT_SHIFT_EX2Q_LOW_TH_V1)
+#define BIT_CLEAR_EX2Q_LOW_TH_V1(x) ((x) & (~BITS_EX2Q_LOW_TH_V1))
+#define BIT_GET_EX2Q_LOW_TH_V1(x) \
+ (((x) >> BIT_SHIFT_EX2Q_LOW_TH_V1) & BIT_MASK_EX2Q_LOW_TH_V1)
+#define BIT_SET_EX2Q_LOW_TH_V1(x, v) \
+ (BIT_CLEAR_EX2Q_LOW_TH_V1(x) | BIT_EX2Q_LOW_TH_V1(v))
+
+/* 2 REG_FIFOPAGE_INFO_6 (Offset 0x0268) */
+
+#define BIT_SHIFT_EX1Q_AVAL_PG_V1 16
+#define BIT_MASK_EX1Q_AVAL_PG_V1 0xfff
+#define BIT_EX1Q_AVAL_PG_V1(x) \
+ (((x) & BIT_MASK_EX1Q_AVAL_PG_V1) << BIT_SHIFT_EX1Q_AVAL_PG_V1)
+#define BITS_EX1Q_AVAL_PG_V1 \
+ (BIT_MASK_EX1Q_AVAL_PG_V1 << BIT_SHIFT_EX1Q_AVAL_PG_V1)
+#define BIT_CLEAR_EX1Q_AVAL_PG_V1(x) ((x) & (~BITS_EX1Q_AVAL_PG_V1))
+#define BIT_GET_EX1Q_AVAL_PG_V1(x) \
+ (((x) >> BIT_SHIFT_EX1Q_AVAL_PG_V1) & BIT_MASK_EX1Q_AVAL_PG_V1)
+#define BIT_SET_EX1Q_AVAL_PG_V1(x, v) \
+ (BIT_CLEAR_EX1Q_AVAL_PG_V1(x) | BIT_EX1Q_AVAL_PG_V1(v))
+
+#define BIT_SHIFT_EX1Q_V1 0
+#define BIT_MASK_EX1Q_V1 0xfff
+#define BIT_EX1Q_V1(x) (((x) & BIT_MASK_EX1Q_V1) << BIT_SHIFT_EX1Q_V1)
+#define BITS_EX1Q_V1 (BIT_MASK_EX1Q_V1 << BIT_SHIFT_EX1Q_V1)
+#define BIT_CLEAR_EX1Q_V1(x) ((x) & (~BITS_EX1Q_V1))
+#define BIT_GET_EX1Q_V1(x) (((x) >> BIT_SHIFT_EX1Q_V1) & BIT_MASK_EX1Q_V1)
+#define BIT_SET_EX1Q_V1(x, v) (BIT_CLEAR_EX1Q_V1(x) | BIT_EX1Q_V1(v))
+
+/* 2 REG_FIFOPAGE_INFO_7 (Offset 0x026C) */
+
+#define BIT_SHIFT_EX2Q_AVAL_PG_V1 16
+#define BIT_MASK_EX2Q_AVAL_PG_V1 0xfff
+#define BIT_EX2Q_AVAL_PG_V1(x) \
+ (((x) & BIT_MASK_EX2Q_AVAL_PG_V1) << BIT_SHIFT_EX2Q_AVAL_PG_V1)
+#define BITS_EX2Q_AVAL_PG_V1 \
+ (BIT_MASK_EX2Q_AVAL_PG_V1 << BIT_SHIFT_EX2Q_AVAL_PG_V1)
+#define BIT_CLEAR_EX2Q_AVAL_PG_V1(x) ((x) & (~BITS_EX2Q_AVAL_PG_V1))
+#define BIT_GET_EX2Q_AVAL_PG_V1(x) \
+ (((x) >> BIT_SHIFT_EX2Q_AVAL_PG_V1) & BIT_MASK_EX2Q_AVAL_PG_V1)
+#define BIT_SET_EX2Q_AVAL_PG_V1(x, v) \
+ (BIT_CLEAR_EX2Q_AVAL_PG_V1(x) | BIT_EX2Q_AVAL_PG_V1(v))
+
+#define BIT_SHIFT_EX2Q_V1 0
+#define BIT_MASK_EX2Q_V1 0xfff
+#define BIT_EX2Q_V1(x) (((x) & BIT_MASK_EX2Q_V1) << BIT_SHIFT_EX2Q_V1)
+#define BITS_EX2Q_V1 (BIT_MASK_EX2Q_V1 << BIT_SHIFT_EX2Q_V1)
+#define BIT_CLEAR_EX2Q_V1(x) ((x) & (~BITS_EX2Q_V1))
+#define BIT_GET_EX2Q_V1(x) (((x) >> BIT_SHIFT_EX2Q_V1) & BIT_MASK_EX2Q_V1)
+#define BIT_SET_EX2Q_V1(x, v) (BIT_CLEAR_EX2Q_V1(x) | BIT_EX2Q_V1(v))
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PGSUB_H (Offset 0x0270) */
+
+#define BIT_SHIFT_HPQ_PGSUB_CNT 0
+#define BIT_MASK_HPQ_PGSUB_CNT 0xffffffffL
+#define BIT_HPQ_PGSUB_CNT(x) \
+ (((x) & BIT_MASK_HPQ_PGSUB_CNT) << BIT_SHIFT_HPQ_PGSUB_CNT)
+#define BITS_HPQ_PGSUB_CNT (BIT_MASK_HPQ_PGSUB_CNT << BIT_SHIFT_HPQ_PGSUB_CNT)
+#define BIT_CLEAR_HPQ_PGSUB_CNT(x) ((x) & (~BITS_HPQ_PGSUB_CNT))
+#define BIT_GET_HPQ_PGSUB_CNT(x) \
+ (((x) >> BIT_SHIFT_HPQ_PGSUB_CNT) & BIT_MASK_HPQ_PGSUB_CNT)
+#define BIT_SET_HPQ_PGSUB_CNT(x, v) \
+ (BIT_CLEAR_HPQ_PGSUB_CNT(x) | BIT_HPQ_PGSUB_CNT(v))
+
+/* 2 REG_PGSUB_N (Offset 0x0274) */
+
+#define BIT_SHIFT_NPQ_PGSUB_CNT 0
+#define BIT_MASK_NPQ_PGSUB_CNT 0xffffffffL
+#define BIT_NPQ_PGSUB_CNT(x) \
+ (((x) & BIT_MASK_NPQ_PGSUB_CNT) << BIT_SHIFT_NPQ_PGSUB_CNT)
+#define BITS_NPQ_PGSUB_CNT (BIT_MASK_NPQ_PGSUB_CNT << BIT_SHIFT_NPQ_PGSUB_CNT)
+#define BIT_CLEAR_NPQ_PGSUB_CNT(x) ((x) & (~BITS_NPQ_PGSUB_CNT))
+#define BIT_GET_NPQ_PGSUB_CNT(x) \
+ (((x) >> BIT_SHIFT_NPQ_PGSUB_CNT) & BIT_MASK_NPQ_PGSUB_CNT)
+#define BIT_SET_NPQ_PGSUB_CNT(x, v) \
+ (BIT_CLEAR_NPQ_PGSUB_CNT(x) | BIT_NPQ_PGSUB_CNT(v))
+
+/* 2 REG_PGSUB_L (Offset 0x0278) */
+
+#define BIT_SHIFT_LPQ_PGSUB_CNT 0
+#define BIT_MASK_LPQ_PGSUB_CNT 0xffffffffL
+#define BIT_LPQ_PGSUB_CNT(x) \
+ (((x) & BIT_MASK_LPQ_PGSUB_CNT) << BIT_SHIFT_LPQ_PGSUB_CNT)
+#define BITS_LPQ_PGSUB_CNT (BIT_MASK_LPQ_PGSUB_CNT << BIT_SHIFT_LPQ_PGSUB_CNT)
+#define BIT_CLEAR_LPQ_PGSUB_CNT(x) ((x) & (~BITS_LPQ_PGSUB_CNT))
+#define BIT_GET_LPQ_PGSUB_CNT(x) \
+ (((x) >> BIT_SHIFT_LPQ_PGSUB_CNT) & BIT_MASK_LPQ_PGSUB_CNT)
+#define BIT_SET_LPQ_PGSUB_CNT(x, v) \
+ (BIT_CLEAR_LPQ_PGSUB_CNT(x) | BIT_LPQ_PGSUB_CNT(v))
+
+/* 2 REG_PGSUB_E (Offset 0x027C) */
+
+#define BIT_SHIFT_EPQ_PGSUB_CNT 0
+#define BIT_MASK_EPQ_PGSUB_CNT 0xffffffffL
+#define BIT_EPQ_PGSUB_CNT(x) \
+ (((x) & BIT_MASK_EPQ_PGSUB_CNT) << BIT_SHIFT_EPQ_PGSUB_CNT)
+#define BITS_EPQ_PGSUB_CNT (BIT_MASK_EPQ_PGSUB_CNT << BIT_SHIFT_EPQ_PGSUB_CNT)
+#define BIT_CLEAR_EPQ_PGSUB_CNT(x) ((x) & (~BITS_EPQ_PGSUB_CNT))
+#define BIT_GET_EPQ_PGSUB_CNT(x) \
+ (((x) >> BIT_SHIFT_EPQ_PGSUB_CNT) & BIT_MASK_EPQ_PGSUB_CNT)
+#define BIT_SET_EPQ_PGSUB_CNT(x, v) \
+ (BIT_CLEAR_EPQ_PGSUB_CNT(x) | BIT_EPQ_PGSUB_CNT(v))
+
+#define BIT_SHIFT_FWFF_PKT_STR_ADDR_V2 0
+#define BIT_MASK_FWFF_PKT_STR_ADDR_V2 0x3fff
+#define BIT_FWFF_PKT_STR_ADDR_V2(x) \
+ (((x) & BIT_MASK_FWFF_PKT_STR_ADDR_V2) \
+ << BIT_SHIFT_FWFF_PKT_STR_ADDR_V2)
+#define BITS_FWFF_PKT_STR_ADDR_V2 \
+ (BIT_MASK_FWFF_PKT_STR_ADDR_V2 << BIT_SHIFT_FWFF_PKT_STR_ADDR_V2)
+#define BIT_CLEAR_FWFF_PKT_STR_ADDR_V2(x) ((x) & (~BITS_FWFF_PKT_STR_ADDR_V2))
+#define BIT_GET_FWFF_PKT_STR_ADDR_V2(x) \
+ (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_V2) & \
+ BIT_MASK_FWFF_PKT_STR_ADDR_V2)
+#define BIT_SET_FWFF_PKT_STR_ADDR_V2(x, v) \
+ (BIT_CLEAR_FWFF_PKT_STR_ADDR_V2(x) | BIT_FWFF_PKT_STR_ADDR_V2(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_RXDMA_STATUS (Offset 0x0288) */
+/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */
-#define BIT_C2H_PKT_OVF BIT(7)
+#define BIT_USB_RXDMA_AGG_EN BIT(31)
#endif
+#if (HALMAC_8197F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */
+#define BIT_DMA_STORE_MODE BIT(31)
-/* 2 REG_RXDMA_STATUS (Offset 0x0288) */
+#endif
-#define BIT_AGG_CFG_ISSUE BIT(6)
+#if (HALMAC_8198F_SUPPORT)
-#endif
+/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */
+#define BIT_RXDMA_AGG_OLD_MOD_V1 BIT(31)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_RXDMA_STATUS (Offset 0x0288) */
+/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */
-#define BIT_AGG_CONFGI_ISSUE BIT(6)
+#define BIT_DMA_STORE BIT(31)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */
+#define BIT_EN_FW_ADD BIT(30)
-/* 2 REG_RXDMA_STATUS (Offset 0x0288) */
+#endif
-#define BIT_FW_POLL_ISSUE BIT(5)
-#define BIT_RX_DATA_UDN BIT(4)
-#define BIT_RX_SFF_UDN BIT(3)
-#define BIT_RX_SFF_OVF BIT(2)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */
+#define BIT_EN_PRE_CALC BIT(29)
+#define BIT_RXAGG_SW_EN BIT(28)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-/* 2 REG_RXDMA_STATUS (Offset 0x0288) */
+/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */
-#define BIT_USB_REQ_LEN_OVF BIT(1)
+#define BIT_RXAGG_SW_TRIG BIT(27)
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */
+#define BIT_SHIFT_RXDMA_AGG_OLD_MOD 24
+#define BIT_MASK_RXDMA_AGG_OLD_MOD 0xff
+#define BIT_RXDMA_AGG_OLD_MOD(x) \
+ (((x) & BIT_MASK_RXDMA_AGG_OLD_MOD) << BIT_SHIFT_RXDMA_AGG_OLD_MOD)
+#define BITS_RXDMA_AGG_OLD_MOD \
+ (BIT_MASK_RXDMA_AGG_OLD_MOD << BIT_SHIFT_RXDMA_AGG_OLD_MOD)
+#define BIT_CLEAR_RXDMA_AGG_OLD_MOD(x) ((x) & (~BITS_RXDMA_AGG_OLD_MOD))
+#define BIT_GET_RXDMA_AGG_OLD_MOD(x) \
+ (((x) >> BIT_SHIFT_RXDMA_AGG_OLD_MOD) & BIT_MASK_RXDMA_AGG_OLD_MOD)
+#define BIT_SET_RXDMA_AGG_OLD_MOD(x, v) \
+ (BIT_CLEAR_RXDMA_AGG_OLD_MOD(x) | BIT_RXDMA_AGG_OLD_MOD(v))
-/* 2 REG_RXDMA_STATUS (Offset 0x0288) */
+#endif
-#define BIT_DMA_MODE BIT(1)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */
+#define BIT_SHIFT_PKT_NUM_WOL 16
+#define BIT_MASK_PKT_NUM_WOL 0xff
+#define BIT_PKT_NUM_WOL(x) \
+ (((x) & BIT_MASK_PKT_NUM_WOL) << BIT_SHIFT_PKT_NUM_WOL)
+#define BITS_PKT_NUM_WOL (BIT_MASK_PKT_NUM_WOL << BIT_SHIFT_PKT_NUM_WOL)
+#define BIT_CLEAR_PKT_NUM_WOL(x) ((x) & (~BITS_PKT_NUM_WOL))
+#define BIT_GET_PKT_NUM_WOL(x) \
+ (((x) >> BIT_SHIFT_PKT_NUM_WOL) & BIT_MASK_PKT_NUM_WOL)
+#define BIT_SET_PKT_NUM_WOL(x, v) \
+ (BIT_CLEAR_PKT_NUM_WOL(x) | BIT_PKT_NUM_WOL(v))
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_RXDMA_STATUS (Offset 0x0288) */
+/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */
-#define BIT_RXPKT_OVF BIT(0)
+#define BIT_SHIFT_DMA_AGG_TO_V1 8
+#define BIT_MASK_DMA_AGG_TO_V1 0xff
+#define BIT_DMA_AGG_TO_V1(x) \
+ (((x) & BIT_MASK_DMA_AGG_TO_V1) << BIT_SHIFT_DMA_AGG_TO_V1)
+#define BITS_DMA_AGG_TO_V1 (BIT_MASK_DMA_AGG_TO_V1 << BIT_SHIFT_DMA_AGG_TO_V1)
+#define BIT_CLEAR_DMA_AGG_TO_V1(x) ((x) & (~BITS_DMA_AGG_TO_V1))
+#define BIT_GET_DMA_AGG_TO_V1(x) \
+ (((x) >> BIT_SHIFT_DMA_AGG_TO_V1) & BIT_MASK_DMA_AGG_TO_V1)
+#define BIT_SET_DMA_AGG_TO_V1(x, v) \
+ (BIT_CLEAR_DMA_AGG_TO_V1(x) | BIT_DMA_AGG_TO_V1(v))
-/* 2 REG_RXDMA_DPR (Offset 0x028C) */
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define BIT_SHIFT_RDE_DEBUG 0
-#define BIT_MASK_RDE_DEBUG 0xffffffffL
-#define BIT_RDE_DEBUG(x) (((x) & BIT_MASK_RDE_DEBUG) << BIT_SHIFT_RDE_DEBUG)
-#define BIT_GET_RDE_DEBUG(x) (((x) >> BIT_SHIFT_RDE_DEBUG) & BIT_MASK_RDE_DEBUG)
+/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */
+#define BIT_SHIFT_DMA_AGG_TO 8
+#define BIT_MASK_DMA_AGG_TO 0xf
+#define BIT_DMA_AGG_TO(x) (((x) & BIT_MASK_DMA_AGG_TO) << BIT_SHIFT_DMA_AGG_TO)
+#define BITS_DMA_AGG_TO (BIT_MASK_DMA_AGG_TO << BIT_SHIFT_DMA_AGG_TO)
+#define BIT_CLEAR_DMA_AGG_TO(x) ((x) & (~BITS_DMA_AGG_TO))
+#define BIT_GET_DMA_AGG_TO(x) \
+ (((x) >> BIT_SHIFT_DMA_AGG_TO) & BIT_MASK_DMA_AGG_TO)
+#define BIT_SET_DMA_AGG_TO(x, v) (BIT_CLEAR_DMA_AGG_TO(x) | BIT_DMA_AGG_TO(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */
+#define BIT_SHIFT_RXDMA_AGG_PG_TH_V1 0
+#define BIT_MASK_RXDMA_AGG_PG_TH_V1 0xf
+#define BIT_RXDMA_AGG_PG_TH_V1(x) \
+ (((x) & BIT_MASK_RXDMA_AGG_PG_TH_V1) << BIT_SHIFT_RXDMA_AGG_PG_TH_V1)
+#define BITS_RXDMA_AGG_PG_TH_V1 \
+ (BIT_MASK_RXDMA_AGG_PG_TH_V1 << BIT_SHIFT_RXDMA_AGG_PG_TH_V1)
+#define BIT_CLEAR_RXDMA_AGG_PG_TH_V1(x) ((x) & (~BITS_RXDMA_AGG_PG_TH_V1))
+#define BIT_GET_RXDMA_AGG_PG_TH_V1(x) \
+ (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_V1) & BIT_MASK_RXDMA_AGG_PG_TH_V1)
+#define BIT_SET_RXDMA_AGG_PG_TH_V1(x, v) \
+ (BIT_CLEAR_RXDMA_AGG_PG_TH_V1(x) | BIT_RXDMA_AGG_PG_TH_V1(v))
-/* 2 REG_RXDMA_MODE (Offset 0x0290) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_PKTNUM_TH_V2 24
-#define BIT_MASK_PKTNUM_TH_V2 0x1f
-#define BIT_PKTNUM_TH_V2(x) (((x) & BIT_MASK_PKTNUM_TH_V2) << BIT_SHIFT_PKTNUM_TH_V2)
-#define BIT_GET_PKTNUM_TH_V2(x) (((x) >> BIT_SHIFT_PKTNUM_TH_V2) & BIT_MASK_PKTNUM_TH_V2)
+/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */
-#define BIT_TXBA_BREAK_USBAGG BIT(23)
+#define BIT_SHIFT_RXDMA_AGG_PG_TH 0
+#define BIT_MASK_RXDMA_AGG_PG_TH 0xff
+#define BIT_RXDMA_AGG_PG_TH(x) \
+ (((x) & BIT_MASK_RXDMA_AGG_PG_TH) << BIT_SHIFT_RXDMA_AGG_PG_TH)
+#define BITS_RXDMA_AGG_PG_TH \
+ (BIT_MASK_RXDMA_AGG_PG_TH << BIT_SHIFT_RXDMA_AGG_PG_TH)
+#define BIT_CLEAR_RXDMA_AGG_PG_TH(x) ((x) & (~BITS_RXDMA_AGG_PG_TH))
+#define BIT_GET_RXDMA_AGG_PG_TH(x) \
+ (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH) & BIT_MASK_RXDMA_AGG_PG_TH)
+#define BIT_SET_RXDMA_AGG_PG_TH(x, v) \
+ (BIT_CLEAR_RXDMA_AGG_PG_TH(x) | BIT_RXDMA_AGG_PG_TH(v))
-#define BIT_SHIFT_PKTLEN_PARA 16
-#define BIT_MASK_PKTLEN_PARA 0x7
-#define BIT_PKTLEN_PARA(x) (((x) & BIT_MASK_PKTLEN_PARA) << BIT_SHIFT_PKTLEN_PARA)
-#define BIT_GET_PKTLEN_PARA(x) (((x) >> BIT_SHIFT_PKTLEN_PARA) & BIT_MASK_PKTLEN_PARA)
+#endif
+#if (HALMAC_8814AMP_SUPPORT)
-#endif
+/* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */
+#define BIT_SHIFT_RXDMA_AGG_PG_TH_V2 0
+#define BIT_MASK_RXDMA_AGG_PG_TH_V2 0xff
+#define BIT_RXDMA_AGG_PG_TH_V2(x) \
+ (((x) & BIT_MASK_RXDMA_AGG_PG_TH_V2) << BIT_SHIFT_RXDMA_AGG_PG_TH_V2)
+#define BITS_RXDMA_AGG_PG_TH_V2 \
+ (BIT_MASK_RXDMA_AGG_PG_TH_V2 << BIT_SHIFT_RXDMA_AGG_PG_TH_V2)
+#define BIT_CLEAR_RXDMA_AGG_PG_TH_V2(x) ((x) & (~BITS_RXDMA_AGG_PG_TH_V2))
+#define BIT_GET_RXDMA_AGG_PG_TH_V2(x) \
+ (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_V2) & BIT_MASK_RXDMA_AGG_PG_TH_V2)
+#define BIT_SET_RXDMA_AGG_PG_TH_V2(x, v) \
+ (BIT_CLEAR_RXDMA_AGG_PG_TH_V2(x) | BIT_RXDMA_AGG_PG_TH_V2(v))
-#if (HALMAC_8814AMP_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_RXDMA_MODE (Offset 0x0290) */
+/* 2 REG_RXPKT_NUM (Offset 0x0284) */
-#define BIT_GRAYCODE_SYNC_WITH_BIN BIT(8)
+#define BIT_SHIFT_RXPKT_NUM 24
+#define BIT_MASK_RXPKT_NUM 0xff
+#define BIT_RXPKT_NUM(x) (((x) & BIT_MASK_RXPKT_NUM) << BIT_SHIFT_RXPKT_NUM)
+#define BITS_RXPKT_NUM (BIT_MASK_RXPKT_NUM << BIT_SHIFT_RXPKT_NUM)
+#define BIT_CLEAR_RXPKT_NUM(x) ((x) & (~BITS_RXPKT_NUM))
+#define BIT_GET_RXPKT_NUM(x) (((x) >> BIT_SHIFT_RXPKT_NUM) & BIT_MASK_RXPKT_NUM)
+#define BIT_SET_RXPKT_NUM(x, v) (BIT_CLEAR_RXPKT_NUM(x) | BIT_RXPKT_NUM(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+/* 2 REG_RXPKT_NUM (Offset 0x0284) */
-/* 2 REG_RXDMA_MODE (Offset 0x0290) */
+#define BIT_SHIFT_FW_UPD_RDPTR19_TO_16 20
+#define BIT_MASK_FW_UPD_RDPTR19_TO_16 0xf
+#define BIT_FW_UPD_RDPTR19_TO_16(x) \
+ (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16) \
+ << BIT_SHIFT_FW_UPD_RDPTR19_TO_16)
+#define BITS_FW_UPD_RDPTR19_TO_16 \
+ (BIT_MASK_FW_UPD_RDPTR19_TO_16 << BIT_SHIFT_FW_UPD_RDPTR19_TO_16)
+#define BIT_CLEAR_FW_UPD_RDPTR19_TO_16(x) ((x) & (~BITS_FW_UPD_RDPTR19_TO_16))
+#define BIT_GET_FW_UPD_RDPTR19_TO_16(x) \
+ (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16) & \
+ BIT_MASK_FW_UPD_RDPTR19_TO_16)
+#define BIT_SET_FW_UPD_RDPTR19_TO_16(x, v) \
+ (BIT_CLEAR_FW_UPD_RDPTR19_TO_16(x) | BIT_FW_UPD_RDPTR19_TO_16(v))
+#endif
-#define BIT_SHIFT_BURST_SIZE 4
-#define BIT_MASK_BURST_SIZE 0x3
-#define BIT_BURST_SIZE(x) (((x) & BIT_MASK_BURST_SIZE) << BIT_SHIFT_BURST_SIZE)
-#define BIT_GET_BURST_SIZE(x) (((x) >> BIT_SHIFT_BURST_SIZE) & BIT_MASK_BURST_SIZE)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+/* 2 REG_RXPKT_NUM (Offset 0x0284) */
-#define BIT_SHIFT_BURST_CNT 2
-#define BIT_MASK_BURST_CNT 0x3
-#define BIT_BURST_CNT(x) (((x) & BIT_MASK_BURST_CNT) << BIT_SHIFT_BURST_CNT)
-#define BIT_GET_BURST_CNT(x) (((x) >> BIT_SHIFT_BURST_CNT) & BIT_MASK_BURST_CNT)
+#define BIT_RXDMA_REQ BIT(19)
+#define BIT_RW_RELEASE_EN BIT(18)
+#define BIT_RXDMA_IDLE BIT(17)
+#define BIT_RXPKT_RELEASE_POLL BIT(16)
+#define BIT_SHIFT_FW_UPD_RDPTR 0
+#define BIT_MASK_FW_UPD_RDPTR 0xffff
+#define BIT_FW_UPD_RDPTR(x) \
+ (((x) & BIT_MASK_FW_UPD_RDPTR) << BIT_SHIFT_FW_UPD_RDPTR)
+#define BITS_FW_UPD_RDPTR (BIT_MASK_FW_UPD_RDPTR << BIT_SHIFT_FW_UPD_RDPTR)
+#define BIT_CLEAR_FW_UPD_RDPTR(x) ((x) & (~BITS_FW_UPD_RDPTR))
+#define BIT_GET_FW_UPD_RDPTR(x) \
+ (((x) >> BIT_SHIFT_FW_UPD_RDPTR) & BIT_MASK_FW_UPD_RDPTR)
+#define BIT_SET_FW_UPD_RDPTR(x, v) \
+ (BIT_CLEAR_FW_UPD_RDPTR(x) | BIT_FW_UPD_RDPTR(v))
#endif
+#if (HALMAC_8197F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_RXDMA_STATUS (Offset 0x0288) */
+#define BIT_FC2H_PKT_OVERFLOW BIT(8)
-/* 2 REG_RXDMA_MODE (Offset 0x0290) */
+#endif
-#define BIT_DAM_MODE BIT(1)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_RXDMA_STATUS (Offset 0x0288) */
+#define BIT_C2H_PKT_OVF BIT(7)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_C2H_PKT (Offset 0x0294) */
+/* 2 REG_RXDMA_STATUS (Offset 0x0288) */
+#define BIT_AGG_CFG_ISSUE BIT(6)
-#define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19 24
-#define BIT_MASK_R_C2H_STR_ADDR_16_TO_19 0xf
-#define BIT_R_C2H_STR_ADDR_16_TO_19(x) (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19) << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19)
-#define BIT_GET_R_C2H_STR_ADDR_16_TO_19(x) (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_MDIO_PHY_ADDR 24
-#define BIT_MASK_MDIO_PHY_ADDR 0x1f
-#define BIT_MDIO_PHY_ADDR(x) (((x) & BIT_MASK_MDIO_PHY_ADDR) << BIT_SHIFT_MDIO_PHY_ADDR)
-#define BIT_GET_MDIO_PHY_ADDR(x) (((x) >> BIT_SHIFT_MDIO_PHY_ADDR) & BIT_MASK_MDIO_PHY_ADDR)
+/* 2 REG_RXDMA_STATUS (Offset 0x0288) */
+#define BIT_AGG_CONFGI_ISSUE BIT(6)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_RXDMA_STATUS (Offset 0x0288) */
+#define BIT_FW_POLL_ISSUE BIT(5)
+#define BIT_RX_DATA_UDN BIT(4)
+#define BIT_RX_SFF_UDN BIT(3)
+#define BIT_RX_SFF_OVF BIT(2)
-/* 2 REG_C2H_PKT (Offset 0x0294) */
+#endif
-#define BIT_R_C2H_PKT_REQ BIT(16)
-#define BIT_RX_CLOSE_EN BIT(15)
-#define BIT_STOP_BCNQ BIT(14)
-#define BIT_STOP_MGQ BIT(13)
-#define BIT_STOP_VOQ BIT(12)
-#define BIT_STOP_VIQ BIT(11)
-#define BIT_STOP_BEQ BIT(10)
-#define BIT_STOP_BKQ BIT(9)
-#define BIT_STOP_RXQ BIT(8)
-#define BIT_STOP_HI7Q BIT(7)
-#define BIT_STOP_HI6Q BIT(6)
-#define BIT_STOP_HI5Q BIT(5)
-#define BIT_STOP_HI4Q BIT(4)
-#define BIT_STOP_HI3Q BIT(3)
-#define BIT_STOP_HI2Q BIT(2)
-#define BIT_STOP_HI1Q BIT(1)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_R_C2H_STR_ADDR 0
-#define BIT_MASK_R_C2H_STR_ADDR 0xffff
-#define BIT_R_C2H_STR_ADDR(x) (((x) & BIT_MASK_R_C2H_STR_ADDR) << BIT_SHIFT_R_C2H_STR_ADDR)
-#define BIT_GET_R_C2H_STR_ADDR(x) (((x) >> BIT_SHIFT_R_C2H_STR_ADDR) & BIT_MASK_R_C2H_STR_ADDR)
+/* 2 REG_RXDMA_STATUS (Offset 0x0288) */
-#define BIT_STOP_HI0Q BIT(0)
+#define BIT_USB_REQ_LEN_OVF BIT(1)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_RXDMA_STATUS (Offset 0x0288) */
+#define BIT_RXPKT_OVF BIT(0)
-/* 2 REG_FWFF_C2H (Offset 0x0298) */
+/* 2 REG_RXDMA_DPR (Offset 0x028C) */
+#define BIT_SHIFT_RDE_DEBUG 0
+#define BIT_MASK_RDE_DEBUG 0xffffffffL
+#define BIT_RDE_DEBUG(x) (((x) & BIT_MASK_RDE_DEBUG) << BIT_SHIFT_RDE_DEBUG)
+#define BITS_RDE_DEBUG (BIT_MASK_RDE_DEBUG << BIT_SHIFT_RDE_DEBUG)
+#define BIT_CLEAR_RDE_DEBUG(x) ((x) & (~BITS_RDE_DEBUG))
+#define BIT_GET_RDE_DEBUG(x) (((x) >> BIT_SHIFT_RDE_DEBUG) & BIT_MASK_RDE_DEBUG)
+#define BIT_SET_RDE_DEBUG(x, v) (BIT_CLEAR_RDE_DEBUG(x) | BIT_RDE_DEBUG(v))
-#define BIT_SHIFT_C2H_DMA_ADDR 0
-#define BIT_MASK_C2H_DMA_ADDR 0x3ffff
-#define BIT_C2H_DMA_ADDR(x) (((x) & BIT_MASK_C2H_DMA_ADDR) << BIT_SHIFT_C2H_DMA_ADDR)
-#define BIT_GET_C2H_DMA_ADDR(x) (((x) >> BIT_SHIFT_C2H_DMA_ADDR) & BIT_MASK_C2H_DMA_ADDR)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-/* 2 REG_FWFF_CTRL (Offset 0x029C) */
+/* 2 REG_RXDMA_MODE (Offset 0x0290) */
-#define BIT_FWFF_DMAPKT_REQ BIT(31)
+#define BIT_SHIFT_PKTNUM_TH_V2 24
+#define BIT_MASK_PKTNUM_TH_V2 0x1f
+#define BIT_PKTNUM_TH_V2(x) \
+ (((x) & BIT_MASK_PKTNUM_TH_V2) << BIT_SHIFT_PKTNUM_TH_V2)
+#define BITS_PKTNUM_TH_V2 (BIT_MASK_PKTNUM_TH_V2 << BIT_SHIFT_PKTNUM_TH_V2)
+#define BIT_CLEAR_PKTNUM_TH_V2(x) ((x) & (~BITS_PKTNUM_TH_V2))
+#define BIT_GET_PKTNUM_TH_V2(x) \
+ (((x) >> BIT_SHIFT_PKTNUM_TH_V2) & BIT_MASK_PKTNUM_TH_V2)
+#define BIT_SET_PKTNUM_TH_V2(x, v) \
+ (BIT_CLEAR_PKTNUM_TH_V2(x) | BIT_PKTNUM_TH_V2(v))
-#define BIT_SHIFT_FWFF_DMA_PKT_NUM 16
-#define BIT_MASK_FWFF_DMA_PKT_NUM 0xff
-#define BIT_FWFF_DMA_PKT_NUM(x) (((x) & BIT_MASK_FWFF_DMA_PKT_NUM) << BIT_SHIFT_FWFF_DMA_PKT_NUM)
-#define BIT_GET_FWFF_DMA_PKT_NUM(x) (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM) & BIT_MASK_FWFF_DMA_PKT_NUM)
+#define BIT_TXBA_BREAK_USBAGG BIT(23)
+#define BIT_SHIFT_PKTLEN_PARA 16
+#define BIT_MASK_PKTLEN_PARA 0x7
+#define BIT_PKTLEN_PARA(x) \
+ (((x) & BIT_MASK_PKTLEN_PARA) << BIT_SHIFT_PKTLEN_PARA)
+#define BITS_PKTLEN_PARA (BIT_MASK_PKTLEN_PARA << BIT_SHIFT_PKTLEN_PARA)
+#define BIT_CLEAR_PKTLEN_PARA(x) ((x) & (~BITS_PKTLEN_PARA))
+#define BIT_GET_PKTLEN_PARA(x) \
+ (((x) >> BIT_SHIFT_PKTLEN_PARA) & BIT_MASK_PKTLEN_PARA)
+#define BIT_SET_PKTLEN_PARA(x, v) \
+ (BIT_CLEAR_PKTLEN_PARA(x) | BIT_PKTLEN_PARA(v))
-#define BIT_SHIFT_FWFF_STR_ADDR 0
-#define BIT_MASK_FWFF_STR_ADDR 0xffff
-#define BIT_FWFF_STR_ADDR(x) (((x) & BIT_MASK_FWFF_STR_ADDR) << BIT_SHIFT_FWFF_STR_ADDR)
-#define BIT_GET_FWFF_STR_ADDR(x) (((x) >> BIT_SHIFT_FWFF_STR_ADDR) & BIT_MASK_FWFF_STR_ADDR)
+#endif
+#if (HALMAC_8198F_SUPPORT)
-/* 2 REG_FWFF_PKT_INFO (Offset 0x02A0) */
+/* 2 REG_RXDMA_MODE (Offset 0x0290) */
+
+#define BIT_EN_SDIO_FAIL BIT(9)
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define BIT_SHIFT_FWFF_PKT_QUEUED 16
-#define BIT_MASK_FWFF_PKT_QUEUED 0xff
-#define BIT_FWFF_PKT_QUEUED(x) (((x) & BIT_MASK_FWFF_PKT_QUEUED) << BIT_SHIFT_FWFF_PKT_QUEUED)
-#define BIT_GET_FWFF_PKT_QUEUED(x) (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED) & BIT_MASK_FWFF_PKT_QUEUED)
+/* 2 REG_RXDMA_MODE (Offset 0x0290) */
+#define BIT_GRAYCODE_SYNC_WITH_BIN BIT(8)
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_RXDMA_MODE (Offset 0x0290) */
+#define BIT_RXDMA_DBD_SEL BIT(7)
-/* 2 REG_FWFF_PKT_INFO (Offset 0x02A0) */
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_FWFF_PKT_STR_ADDR 0
-#define BIT_MASK_FWFF_PKT_STR_ADDR 0xffff
-#define BIT_FWFF_PKT_STR_ADDR(x) (((x) & BIT_MASK_FWFF_PKT_STR_ADDR) << BIT_SHIFT_FWFF_PKT_STR_ADDR)
-#define BIT_GET_FWFF_PKT_STR_ADDR(x) (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR) & BIT_MASK_FWFF_PKT_STR_ADDR)
+/* 2 REG_RXDMA_MODE (Offset 0x0290) */
+#define BIT_RX_DBG_SEL BIT(7)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814AMP_SUPPORT)
+/* 2 REG_RXDMA_MODE (Offset 0x0290) */
+#define BIT_EN_SPD BIT(6)
-/* 2 REG_FWFF_PKT_INFO (Offset 0x02A0) */
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+/* 2 REG_RXDMA_MODE (Offset 0x0290) */
-#define BIT_SHIFT_FWFF_PKT_STR_ADDR_V1 0
-#define BIT_MASK_FWFF_PKT_STR_ADDR_V1 0x7ff
-#define BIT_FWFF_PKT_STR_ADDR_V1(x) (((x) & BIT_MASK_FWFF_PKT_STR_ADDR_V1) << BIT_SHIFT_FWFF_PKT_STR_ADDR_V1)
-#define BIT_GET_FWFF_PKT_STR_ADDR_V1(x) (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_V1) & BIT_MASK_FWFF_PKT_STR_ADDR_V1)
+#define BIT_SHIFT_BURST_SIZE 4
+#define BIT_MASK_BURST_SIZE 0x3
+#define BIT_BURST_SIZE(x) (((x) & BIT_MASK_BURST_SIZE) << BIT_SHIFT_BURST_SIZE)
+#define BITS_BURST_SIZE (BIT_MASK_BURST_SIZE << BIT_SHIFT_BURST_SIZE)
+#define BIT_CLEAR_BURST_SIZE(x) ((x) & (~BITS_BURST_SIZE))
+#define BIT_GET_BURST_SIZE(x) \
+ (((x) >> BIT_SHIFT_BURST_SIZE) & BIT_MASK_BURST_SIZE)
+#define BIT_SET_BURST_SIZE(x, v) (BIT_CLEAR_BURST_SIZE(x) | BIT_BURST_SIZE(v))
+#define BIT_SHIFT_BURST_CNT 2
+#define BIT_MASK_BURST_CNT 0x3
+#define BIT_BURST_CNT(x) (((x) & BIT_MASK_BURST_CNT) << BIT_SHIFT_BURST_CNT)
+#define BITS_BURST_CNT (BIT_MASK_BURST_CNT << BIT_SHIFT_BURST_CNT)
+#define BIT_CLEAR_BURST_CNT(x) ((x) & (~BITS_BURST_CNT))
+#define BIT_GET_BURST_CNT(x) (((x) >> BIT_SHIFT_BURST_CNT) & BIT_MASK_BURST_CNT)
+#define BIT_SET_BURST_CNT(x, v) (BIT_CLEAR_BURST_CNT(x) | BIT_BURST_CNT(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_RXDMA_MODE (Offset 0x0290) */
+#define BIT_DAM_MODE BIT(1)
-/* 2 REG_FC2H_INFO (Offset 0x02A6) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_FC2H_STR_ADDR 17
-#define BIT_MASK_FC2H_STR_ADDR 0x7fff
-#define BIT_FC2H_STR_ADDR(x) (((x) & BIT_MASK_FC2H_STR_ADDR) << BIT_SHIFT_FC2H_STR_ADDR)
-#define BIT_GET_FC2H_STR_ADDR(x) (((x) >> BIT_SHIFT_FC2H_STR_ADDR) & BIT_MASK_FC2H_STR_ADDR)
+/* 2 REG_RXDMA_MODE (Offset 0x0290) */
-#define BIT_FC2H_PKT_REQ BIT(16)
+#define BIT_DMA_MODE BIT(1)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_C2H_PKT (Offset 0x0294) */
+#define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19 24
+#define BIT_MASK_R_C2H_STR_ADDR_16_TO_19 0xf
+#define BIT_R_C2H_STR_ADDR_16_TO_19(x) \
+ (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19) \
+ << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19)
+#define BITS_R_C2H_STR_ADDR_16_TO_19 \
+ (BIT_MASK_R_C2H_STR_ADDR_16_TO_19 << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19)
+#define BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19(x) \
+ ((x) & (~BITS_R_C2H_STR_ADDR_16_TO_19))
+#define BIT_GET_R_C2H_STR_ADDR_16_TO_19(x) \
+ (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19) & \
+ BIT_MASK_R_C2H_STR_ADDR_16_TO_19)
+#define BIT_SET_R_C2H_STR_ADDR_16_TO_19(x, v) \
+ (BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19(x) | BIT_R_C2H_STR_ADDR_16_TO_19(v))
+
+#define BIT_SHIFT_MDIO_PHY_ADDR 24
+#define BIT_MASK_MDIO_PHY_ADDR 0x1f
+#define BIT_MDIO_PHY_ADDR(x) \
+ (((x) & BIT_MASK_MDIO_PHY_ADDR) << BIT_SHIFT_MDIO_PHY_ADDR)
+#define BITS_MDIO_PHY_ADDR (BIT_MASK_MDIO_PHY_ADDR << BIT_SHIFT_MDIO_PHY_ADDR)
+#define BIT_CLEAR_MDIO_PHY_ADDR(x) ((x) & (~BITS_MDIO_PHY_ADDR))
+#define BIT_GET_MDIO_PHY_ADDR(x) \
+ (((x) >> BIT_SHIFT_MDIO_PHY_ADDR) & BIT_MASK_MDIO_PHY_ADDR)
+#define BIT_SET_MDIO_PHY_ADDR(x, v) \
+ (BIT_CLEAR_MDIO_PHY_ADDR(x) | BIT_MDIO_PHY_ADDR(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-/* 2 REG_PCIE_CTRL (Offset 0x0300) */
+/* 2 REG_C2H_PKT (Offset 0x0294) */
+
+#define BIT_R_C2H_PKT_REQ BIT(16)
-#define BIT_PCIEIO_PERSTB_SEL BIT(31)
+#define BIT_SHIFT_R_C2H_STR_ADDR 0
+#define BIT_MASK_R_C2H_STR_ADDR 0xffff
+#define BIT_R_C2H_STR_ADDR(x) \
+ (((x) & BIT_MASK_R_C2H_STR_ADDR) << BIT_SHIFT_R_C2H_STR_ADDR)
+#define BITS_R_C2H_STR_ADDR \
+ (BIT_MASK_R_C2H_STR_ADDR << BIT_SHIFT_R_C2H_STR_ADDR)
+#define BIT_CLEAR_R_C2H_STR_ADDR(x) ((x) & (~BITS_R_C2H_STR_ADDR))
+#define BIT_GET_R_C2H_STR_ADDR(x) \
+ (((x) >> BIT_SHIFT_R_C2H_STR_ADDR) & BIT_MASK_R_C2H_STR_ADDR)
+#define BIT_SET_R_C2H_STR_ADDR(x, v) \
+ (BIT_CLEAR_R_C2H_STR_ADDR(x) | BIT_R_C2H_STR_ADDR(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_FWFF_C2H (Offset 0x0298) */
+#define BIT_SHIFT_C2H_DMA_ADDR 0
+#define BIT_MASK_C2H_DMA_ADDR 0x3ffff
+#define BIT_C2H_DMA_ADDR(x) \
+ (((x) & BIT_MASK_C2H_DMA_ADDR) << BIT_SHIFT_C2H_DMA_ADDR)
+#define BITS_C2H_DMA_ADDR (BIT_MASK_C2H_DMA_ADDR << BIT_SHIFT_C2H_DMA_ADDR)
+#define BIT_CLEAR_C2H_DMA_ADDR(x) ((x) & (~BITS_C2H_DMA_ADDR))
+#define BIT_GET_C2H_DMA_ADDR(x) \
+ (((x) >> BIT_SHIFT_C2H_DMA_ADDR) & BIT_MASK_C2H_DMA_ADDR)
+#define BIT_SET_C2H_DMA_ADDR(x, v) \
+ (BIT_CLEAR_C2H_DMA_ADDR(x) | BIT_C2H_DMA_ADDR(v))
-/* 2 REG_HCI_CTRL (Offset 0x0300) */
+/* 2 REG_FWFF_CTRL (Offset 0x029C) */
-#define BIT_HCIIO_PERSTB_SEL BIT(31)
+#define BIT_FWFF_DMAPKT_REQ BIT(31)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FWFF_CTRL (Offset 0x029C) */
+#define BIT_SHIFT_FWFF_DMA_PKT_NUM 16
+#define BIT_MASK_FWFF_DMA_PKT_NUM 0xff
+#define BIT_FWFF_DMA_PKT_NUM(x) \
+ (((x) & BIT_MASK_FWFF_DMA_PKT_NUM) << BIT_SHIFT_FWFF_DMA_PKT_NUM)
+#define BITS_FWFF_DMA_PKT_NUM \
+ (BIT_MASK_FWFF_DMA_PKT_NUM << BIT_SHIFT_FWFF_DMA_PKT_NUM)
+#define BIT_CLEAR_FWFF_DMA_PKT_NUM(x) ((x) & (~BITS_FWFF_DMA_PKT_NUM))
+#define BIT_GET_FWFF_DMA_PKT_NUM(x) \
+ (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM) & BIT_MASK_FWFF_DMA_PKT_NUM)
+#define BIT_SET_FWFF_DMA_PKT_NUM(x, v) \
+ (BIT_CLEAR_FWFF_DMA_PKT_NUM(x) | BIT_FWFF_DMA_PKT_NUM(v))
-/* 2 REG_PCIE_CTRL (Offset 0x0300) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_PCIE_MAX_RXDMA 28
-#define BIT_MASK_PCIE_MAX_RXDMA 0x7
-#define BIT_PCIE_MAX_RXDMA(x) (((x) & BIT_MASK_PCIE_MAX_RXDMA) << BIT_SHIFT_PCIE_MAX_RXDMA)
-#define BIT_GET_PCIE_MAX_RXDMA(x) (((x) >> BIT_SHIFT_PCIE_MAX_RXDMA) & BIT_MASK_PCIE_MAX_RXDMA)
+/* 2 REG_FWFF_CTRL (Offset 0x029C) */
+#define BIT_SHIFT_FWFF_DMA_PKT_NUM_V1 16
+#define BIT_MASK_FWFF_DMA_PKT_NUM_V1 0x7fff
+#define BIT_FWFF_DMA_PKT_NUM_V1(x) \
+ (((x) & BIT_MASK_FWFF_DMA_PKT_NUM_V1) << BIT_SHIFT_FWFF_DMA_PKT_NUM_V1)
+#define BITS_FWFF_DMA_PKT_NUM_V1 \
+ (BIT_MASK_FWFF_DMA_PKT_NUM_V1 << BIT_SHIFT_FWFF_DMA_PKT_NUM_V1)
+#define BIT_CLEAR_FWFF_DMA_PKT_NUM_V1(x) ((x) & (~BITS_FWFF_DMA_PKT_NUM_V1))
+#define BIT_GET_FWFF_DMA_PKT_NUM_V1(x) \
+ (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_V1) & BIT_MASK_FWFF_DMA_PKT_NUM_V1)
+#define BIT_SET_FWFF_DMA_PKT_NUM_V1(x, v) \
+ (BIT_CLEAR_FWFF_DMA_PKT_NUM_V1(x) | BIT_FWFF_DMA_PKT_NUM_V1(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_FWFF_CTRL (Offset 0x029C) */
+#define BIT_SHIFT_FWFF_STR_ADDR 0
+#define BIT_MASK_FWFF_STR_ADDR 0xffff
+#define BIT_FWFF_STR_ADDR(x) \
+ (((x) & BIT_MASK_FWFF_STR_ADDR) << BIT_SHIFT_FWFF_STR_ADDR)
+#define BITS_FWFF_STR_ADDR (BIT_MASK_FWFF_STR_ADDR << BIT_SHIFT_FWFF_STR_ADDR)
+#define BIT_CLEAR_FWFF_STR_ADDR(x) ((x) & (~BITS_FWFF_STR_ADDR))
+#define BIT_GET_FWFF_STR_ADDR(x) \
+ (((x) >> BIT_SHIFT_FWFF_STR_ADDR) & BIT_MASK_FWFF_STR_ADDR)
+#define BIT_SET_FWFF_STR_ADDR(x, v) \
+ (BIT_CLEAR_FWFF_STR_ADDR(x) | BIT_FWFF_STR_ADDR(v))
-/* 2 REG_HCI_CTRL (Offset 0x0300) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_HCI_MAX_RXDMA 28
-#define BIT_MASK_HCI_MAX_RXDMA 0x7
-#define BIT_HCI_MAX_RXDMA(x) (((x) & BIT_MASK_HCI_MAX_RXDMA) << BIT_SHIFT_HCI_MAX_RXDMA)
-#define BIT_GET_HCI_MAX_RXDMA(x) (((x) >> BIT_SHIFT_HCI_MAX_RXDMA) & BIT_MASK_HCI_MAX_RXDMA)
+/* 2 REG_FWFF_PKT_INFO (Offset 0x02A0) */
+#define BIT_SHIFT_FWFF_PKT_QUEUED 16
+#define BIT_MASK_FWFF_PKT_QUEUED 0xff
+#define BIT_FWFF_PKT_QUEUED(x) \
+ (((x) & BIT_MASK_FWFF_PKT_QUEUED) << BIT_SHIFT_FWFF_PKT_QUEUED)
+#define BITS_FWFF_PKT_QUEUED \
+ (BIT_MASK_FWFF_PKT_QUEUED << BIT_SHIFT_FWFF_PKT_QUEUED)
+#define BIT_CLEAR_FWFF_PKT_QUEUED(x) ((x) & (~BITS_FWFF_PKT_QUEUED))
+#define BIT_GET_FWFF_PKT_QUEUED(x) \
+ (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED) & BIT_MASK_FWFF_PKT_QUEUED)
+#define BIT_SET_FWFF_PKT_QUEUED(x, v) \
+ (BIT_CLEAR_FWFF_PKT_QUEUED(x) | BIT_FWFF_PKT_QUEUED(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8881A_SUPPORT)
-
-
-/* 2 REG_LX_CTRL1 (Offset 0x0300) */
+/* 2 REG_FWFF_PKT_INFO (Offset 0x02A0) */
-#define BIT_RX_LIT_EDN_SEL BIT(27)
-#define BIT_TX_LIT_EDN_SEL BIT(26)
-#define BIT_WT_LIT_EDN BIT(25)
+#define BIT_SHIFT_FWFF_PKT_READ_ADDR 16
+#define BIT_MASK_FWFF_PKT_READ_ADDR 0xffff
+#define BIT_FWFF_PKT_READ_ADDR(x) \
+ (((x) & BIT_MASK_FWFF_PKT_READ_ADDR) << BIT_SHIFT_FWFF_PKT_READ_ADDR)
+#define BITS_FWFF_PKT_READ_ADDR \
+ (BIT_MASK_FWFF_PKT_READ_ADDR << BIT_SHIFT_FWFF_PKT_READ_ADDR)
+#define BIT_CLEAR_FWFF_PKT_READ_ADDR(x) ((x) & (~BITS_FWFF_PKT_READ_ADDR))
+#define BIT_GET_FWFF_PKT_READ_ADDR(x) \
+ (((x) >> BIT_SHIFT_FWFF_PKT_READ_ADDR) & BIT_MASK_FWFF_PKT_READ_ADDR)
+#define BIT_SET_FWFF_PKT_READ_ADDR(x, v) \
+ (BIT_CLEAR_FWFF_PKT_READ_ADDR(x) | BIT_FWFF_PKT_READ_ADDR(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FWFF_PKT_INFO (Offset 0x02A0) */
+#define BIT_ECRC_EN_V1 BIT(7)
+#define BIT_MDIO_RFLAG_V1 BIT(6)
+#define BIT_MDIO_WFLAG_V1 BIT(5)
-/* 2 REG_PCIE_CTRL (Offset 0x0300) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_PCIE_MAX_TXDMA 24
-#define BIT_MASK_PCIE_MAX_TXDMA 0x7
-#define BIT_PCIE_MAX_TXDMA(x) (((x) & BIT_MASK_PCIE_MAX_TXDMA) << BIT_SHIFT_PCIE_MAX_TXDMA)
-#define BIT_GET_PCIE_MAX_TXDMA(x) (((x) >> BIT_SHIFT_PCIE_MAX_TXDMA) & BIT_MASK_PCIE_MAX_TXDMA)
+/* 2 REG_FWFF_PKT_INFO (Offset 0x02A0) */
+#define BIT_SHIFT_FWFF_PKT_STR_ADDR 0
+#define BIT_MASK_FWFF_PKT_STR_ADDR 0xffff
+#define BIT_FWFF_PKT_STR_ADDR(x) \
+ (((x) & BIT_MASK_FWFF_PKT_STR_ADDR) << BIT_SHIFT_FWFF_PKT_STR_ADDR)
+#define BITS_FWFF_PKT_STR_ADDR \
+ (BIT_MASK_FWFF_PKT_STR_ADDR << BIT_SHIFT_FWFF_PKT_STR_ADDR)
+#define BIT_CLEAR_FWFF_PKT_STR_ADDR(x) ((x) & (~BITS_FWFF_PKT_STR_ADDR))
+#define BIT_GET_FWFF_PKT_STR_ADDR(x) \
+ (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR) & BIT_MASK_FWFF_PKT_STR_ADDR)
+#define BIT_SET_FWFF_PKT_STR_ADDR(x, v) \
+ (BIT_CLEAR_FWFF_PKT_STR_ADDR(x) | BIT_FWFF_PKT_STR_ADDR(v))
#endif
+#if (HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_FWFF_PKT_INFO (Offset 0x02A0) */
+#define BIT_SHIFT_FWFF_PKT_STR_ADDR_V1 0
+#define BIT_MASK_FWFF_PKT_STR_ADDR_V1 0x7ff
+#define BIT_FWFF_PKT_STR_ADDR_V1(x) \
+ (((x) & BIT_MASK_FWFF_PKT_STR_ADDR_V1) \
+ << BIT_SHIFT_FWFF_PKT_STR_ADDR_V1)
+#define BITS_FWFF_PKT_STR_ADDR_V1 \
+ (BIT_MASK_FWFF_PKT_STR_ADDR_V1 << BIT_SHIFT_FWFF_PKT_STR_ADDR_V1)
+#define BIT_CLEAR_FWFF_PKT_STR_ADDR_V1(x) ((x) & (~BITS_FWFF_PKT_STR_ADDR_V1))
+#define BIT_GET_FWFF_PKT_STR_ADDR_V1(x) \
+ (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_V1) & \
+ BIT_MASK_FWFF_PKT_STR_ADDR_V1)
+#define BIT_SET_FWFF_PKT_STR_ADDR_V1(x, v) \
+ (BIT_CLEAR_FWFF_PKT_STR_ADDR_V1(x) | BIT_FWFF_PKT_STR_ADDR_V1(v))
-/* 2 REG_HCI_CTRL (Offset 0x0300) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_HCI_MAX_TXDMA 24
-#define BIT_MASK_HCI_MAX_TXDMA 0x7
-#define BIT_HCI_MAX_TXDMA(x) (((x) & BIT_MASK_HCI_MAX_TXDMA) << BIT_SHIFT_HCI_MAX_TXDMA)
-#define BIT_GET_HCI_MAX_TXDMA(x) (((x) >> BIT_SHIFT_HCI_MAX_TXDMA) & BIT_MASK_HCI_MAX_TXDMA)
+/* 2 REG_FWFF_PKT_INFO (Offset 0x02A0) */
+#define BIT_SHIFT_FWFF_PKT_WRITE_ADDR 0
+#define BIT_MASK_FWFF_PKT_WRITE_ADDR 0xffff
+#define BIT_FWFF_PKT_WRITE_ADDR(x) \
+ (((x) & BIT_MASK_FWFF_PKT_WRITE_ADDR) << BIT_SHIFT_FWFF_PKT_WRITE_ADDR)
+#define BITS_FWFF_PKT_WRITE_ADDR \
+ (BIT_MASK_FWFF_PKT_WRITE_ADDR << BIT_SHIFT_FWFF_PKT_WRITE_ADDR)
+#define BIT_CLEAR_FWFF_PKT_WRITE_ADDR(x) ((x) & (~BITS_FWFF_PKT_WRITE_ADDR))
+#define BIT_GET_FWFF_PKT_WRITE_ADDR(x) \
+ (((x) >> BIT_SHIFT_FWFF_PKT_WRITE_ADDR) & BIT_MASK_FWFF_PKT_WRITE_ADDR)
+#define BIT_SET_FWFF_PKT_WRITE_ADDR(x, v) \
+ (BIT_CLEAR_FWFF_PKT_WRITE_ADDR(x) | BIT_FWFF_PKT_WRITE_ADDR(v))
#endif
+#if (HALMAC_8197F_SUPPORT)
-#if (HALMAC_8881A_SUPPORT)
-
-
-/* 2 REG_LX_CTRL1 (Offset 0x0300) */
+/* 2 REG_FC2H_INFO (Offset 0x02A4) */
-#define BIT_RD_LITT_EDN BIT(24)
+#define BIT_FC2H_PKT_REQ BIT(16)
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+/* 2 REG_FC2H_INFO (Offset 0x02A4) */
-/* 2 REG_PCIE_CTRL (Offset 0x0300) */
-
-#define BIT_PCIE_RST_TRXDMA_INTF BIT(20)
+#define BIT_FC2H_DMAPKT_REQ BIT(16)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
-
-/* 2 REG_HCI_CTRL (Offset 0x0300) */
+/* 2 REG_FC2H_INFO (Offset 0x02A4) */
-#define BIT_HCI_RST_TRXDMA_INTF BIT(20)
+#define BIT_SHIFT_FC2H_STR_ADDR 0
+#define BIT_MASK_FC2H_STR_ADDR 0xffff
+#define BIT_FC2H_STR_ADDR(x) \
+ (((x) & BIT_MASK_FC2H_STR_ADDR) << BIT_SHIFT_FC2H_STR_ADDR)
+#define BITS_FC2H_STR_ADDR (BIT_MASK_FC2H_STR_ADDR << BIT_SHIFT_FC2H_STR_ADDR)
+#define BIT_CLEAR_FC2H_STR_ADDR(x) ((x) & (~BITS_FC2H_STR_ADDR))
+#define BIT_GET_FC2H_STR_ADDR(x) \
+ (((x) >> BIT_SHIFT_FC2H_STR_ADDR) & BIT_MASK_FC2H_STR_ADDR)
+#define BIT_SET_FC2H_STR_ADDR(x, v) \
+ (BIT_CLEAR_FC2H_STR_ADDR(x) | BIT_FC2H_STR_ADDR(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8881A_SUPPORT)
-
-
-/* 2 REG_LX_CTRL1 (Offset 0x0300) */
+/* 2 REG_FWFF_PKT_INFO2 (Offset 0x02A4) */
+#define BIT_SHIFT_FWFF_PKT_QUEUED_V1 0
+#define BIT_MASK_FWFF_PKT_QUEUED_V1 0xffff
+#define BIT_FWFF_PKT_QUEUED_V1(x) \
+ (((x) & BIT_MASK_FWFF_PKT_QUEUED_V1) << BIT_SHIFT_FWFF_PKT_QUEUED_V1)
+#define BITS_FWFF_PKT_QUEUED_V1 \
+ (BIT_MASK_FWFF_PKT_QUEUED_V1 << BIT_SHIFT_FWFF_PKT_QUEUED_V1)
+#define BIT_CLEAR_FWFF_PKT_QUEUED_V1(x) ((x) & (~BITS_FWFF_PKT_QUEUED_V1))
+#define BIT_GET_FWFF_PKT_QUEUED_V1(x) \
+ (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_V1) & BIT_MASK_FWFF_PKT_QUEUED_V1)
+#define BIT_SET_FWFF_PKT_QUEUED_V1(x, v) \
+ (BIT_CLEAR_FWFF_PKT_QUEUED_V1(x) | BIT_FWFF_PKT_QUEUED_V1(v))
+
+#define BIT_SHIFT_FW_UPD_RXDES_RD_PTR 0
+#define BIT_MASK_FW_UPD_RXDES_RD_PTR 0x3ffff
+#define BIT_FW_UPD_RXDES_RD_PTR(x) \
+ (((x) & BIT_MASK_FW_UPD_RXDES_RD_PTR) << BIT_SHIFT_FW_UPD_RXDES_RD_PTR)
+#define BITS_FW_UPD_RXDES_RD_PTR \
+ (BIT_MASK_FW_UPD_RXDES_RD_PTR << BIT_SHIFT_FW_UPD_RXDES_RD_PTR)
+#define BIT_CLEAR_FW_UPD_RXDES_RD_PTR(x) ((x) & (~BITS_FW_UPD_RXDES_RD_PTR))
+#define BIT_GET_FW_UPD_RXDES_RD_PTR(x) \
+ (((x) >> BIT_SHIFT_FW_UPD_RXDES_RD_PTR) & BIT_MASK_FW_UPD_RXDES_RD_PTR)
+#define BIT_SET_FW_UPD_RXDES_RD_PTR(x, v) \
+ (BIT_CLEAR_FW_UPD_RXDES_RD_PTR(x) | BIT_FW_UPD_RXDES_RD_PTR(v))
+
+#endif
-#define BIT_SHIFT_MAX_RXDMA 20
-#define BIT_MASK_MAX_RXDMA 0x7
-#define BIT_MAX_RXDMA(x) (((x) & BIT_MASK_MAX_RXDMA) << BIT_SHIFT_MAX_RXDMA)
-#define BIT_GET_MAX_RXDMA(x) (((x) >> BIT_SHIFT_MAX_RXDMA) & BIT_MASK_MAX_RXDMA)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+/* 2 REG_RXPKTNUM (Offset 0x02B0) */
-#endif
+#define BIT_SHIFT_PKT_NUM_WOL_V1 16
+#define BIT_MASK_PKT_NUM_WOL_V1 0xffff
+#define BIT_PKT_NUM_WOL_V1(x) \
+ (((x) & BIT_MASK_PKT_NUM_WOL_V1) << BIT_SHIFT_PKT_NUM_WOL_V1)
+#define BITS_PKT_NUM_WOL_V1 \
+ (BIT_MASK_PKT_NUM_WOL_V1 << BIT_SHIFT_PKT_NUM_WOL_V1)
+#define BIT_CLEAR_PKT_NUM_WOL_V1(x) ((x) & (~BITS_PKT_NUM_WOL_V1))
+#define BIT_GET_PKT_NUM_WOL_V1(x) \
+ (((x) >> BIT_SHIFT_PKT_NUM_WOL_V1) & BIT_MASK_PKT_NUM_WOL_V1)
+#define BIT_SET_PKT_NUM_WOL_V1(x, v) \
+ (BIT_CLEAR_PKT_NUM_WOL_V1(x) | BIT_PKT_NUM_WOL_V1(v))
+#define BIT_SHIFT_RXPKT_NUM_V1 0
+#define BIT_MASK_RXPKT_NUM_V1 0xffff
+#define BIT_RXPKT_NUM_V1(x) \
+ (((x) & BIT_MASK_RXPKT_NUM_V1) << BIT_SHIFT_RXPKT_NUM_V1)
+#define BITS_RXPKT_NUM_V1 (BIT_MASK_RXPKT_NUM_V1 << BIT_SHIFT_RXPKT_NUM_V1)
+#define BIT_CLEAR_RXPKT_NUM_V1(x) ((x) & (~BITS_RXPKT_NUM_V1))
+#define BIT_GET_RXPKT_NUM_V1(x) \
+ (((x) >> BIT_SHIFT_RXPKT_NUM_V1) & BIT_MASK_RXPKT_NUM_V1)
+#define BIT_SET_RXPKT_NUM_V1(x, v) \
+ (BIT_CLEAR_RXPKT_NUM_V1(x) | BIT_RXPKT_NUM_V1(v))
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#define BIT_SHIFT_RXPKT_NUM_TH 0
+#define BIT_MASK_RXPKT_NUM_TH 0xff
+#define BIT_RXPKT_NUM_TH(x) \
+ (((x) & BIT_MASK_RXPKT_NUM_TH) << BIT_SHIFT_RXPKT_NUM_TH)
+#define BITS_RXPKT_NUM_TH (BIT_MASK_RXPKT_NUM_TH << BIT_SHIFT_RXPKT_NUM_TH)
+#define BIT_CLEAR_RXPKT_NUM_TH(x) ((x) & (~BITS_RXPKT_NUM_TH))
+#define BIT_GET_RXPKT_NUM_TH(x) \
+ (((x) >> BIT_SHIFT_RXPKT_NUM_TH) & BIT_MASK_RXPKT_NUM_TH)
+#define BIT_SET_RXPKT_NUM_TH(x, v) \
+ (BIT_CLEAR_RXPKT_NUM_TH(x) | BIT_RXPKT_NUM_TH(v))
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FW_MSG1 (Offset 0x02E0) */
+
+#define BIT_SHIFT_FW_MSG_REG1 0
+#define BIT_MASK_FW_MSG_REG1 0xffffffffL
+#define BIT_FW_MSG_REG1(x) \
+ (((x) & BIT_MASK_FW_MSG_REG1) << BIT_SHIFT_FW_MSG_REG1)
+#define BITS_FW_MSG_REG1 (BIT_MASK_FW_MSG_REG1 << BIT_SHIFT_FW_MSG_REG1)
+#define BIT_CLEAR_FW_MSG_REG1(x) ((x) & (~BITS_FW_MSG_REG1))
+#define BIT_GET_FW_MSG_REG1(x) \
+ (((x) >> BIT_SHIFT_FW_MSG_REG1) & BIT_MASK_FW_MSG_REG1)
+#define BIT_SET_FW_MSG_REG1(x, v) \
+ (BIT_CLEAR_FW_MSG_REG1(x) | BIT_FW_MSG_REG1(v))
+
+/* 2 REG_FW_MSG2 (Offset 0x02E4) */
+
+#define BIT_SHIFT_FW_MSG_REG2 0
+#define BIT_MASK_FW_MSG_REG2 0xffffffffL
+#define BIT_FW_MSG_REG2(x) \
+ (((x) & BIT_MASK_FW_MSG_REG2) << BIT_SHIFT_FW_MSG_REG2)
+#define BITS_FW_MSG_REG2 (BIT_MASK_FW_MSG_REG2 << BIT_SHIFT_FW_MSG_REG2)
+#define BIT_CLEAR_FW_MSG_REG2(x) ((x) & (~BITS_FW_MSG_REG2))
+#define BIT_GET_FW_MSG_REG2(x) \
+ (((x) >> BIT_SHIFT_FW_MSG_REG2) & BIT_MASK_FW_MSG_REG2)
+#define BIT_SET_FW_MSG_REG2(x, v) \
+ (BIT_CLEAR_FW_MSG_REG2(x) | BIT_FW_MSG_REG2(v))
+
+/* 2 REG_FW_MSG3 (Offset 0x02E8) */
+
+#define BIT_SHIFT_FW_MSG_REG3 0
+#define BIT_MASK_FW_MSG_REG3 0xffffffffL
+#define BIT_FW_MSG_REG3(x) \
+ (((x) & BIT_MASK_FW_MSG_REG3) << BIT_SHIFT_FW_MSG_REG3)
+#define BITS_FW_MSG_REG3 (BIT_MASK_FW_MSG_REG3 << BIT_SHIFT_FW_MSG_REG3)
+#define BIT_CLEAR_FW_MSG_REG3(x) ((x) & (~BITS_FW_MSG_REG3))
+#define BIT_GET_FW_MSG_REG3(x) \
+ (((x) >> BIT_SHIFT_FW_MSG_REG3) & BIT_MASK_FW_MSG_REG3)
+#define BIT_SET_FW_MSG_REG3(x, v) \
+ (BIT_CLEAR_FW_MSG_REG3(x) | BIT_FW_MSG_REG3(v))
+
+/* 2 REG_FW_MSG4 (Offset 0x02EC) */
+
+#define BIT_SHIFT_FW_MSG_REG4 0
+#define BIT_MASK_FW_MSG_REG4 0xffffffffL
+#define BIT_FW_MSG_REG4(x) \
+ (((x) & BIT_MASK_FW_MSG_REG4) << BIT_SHIFT_FW_MSG_REG4)
+#define BITS_FW_MSG_REG4 (BIT_MASK_FW_MSG_REG4 << BIT_SHIFT_FW_MSG_REG4)
+#define BIT_CLEAR_FW_MSG_REG4(x) ((x) & (~BITS_FW_MSG_REG4))
+#define BIT_GET_FW_MSG_REG4(x) \
+ (((x) >> BIT_SHIFT_FW_MSG_REG4) & BIT_MASK_FW_MSG_REG4)
+#define BIT_SET_FW_MSG_REG4(x, v) \
+ (BIT_CLEAR_FW_MSG_REG4(x) | BIT_FW_MSG_REG4(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_PCIE_CTRL (Offset 0x0300) */
-#define BIT_PCIE_EN_SWENT_L23 BIT(17)
+#define BIT_PCIEIO_PERSTB_SEL BIT(31)
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_HCI_CTRL (Offset 0x0300) */
-#define BIT_HCI_EN_SWENT_L23 BIT(17)
+#define BIT_HCIIO_PERSTB_SEL BIT(31)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_PCIE_CTRL (Offset 0x0300) */
-#define BIT_PCIE_EN_HWEXT_L1 BIT(16)
+#define BIT_SHIFT_PCIE_MAX_RXDMA 28
+#define BIT_MASK_PCIE_MAX_RXDMA 0x7
+#define BIT_PCIE_MAX_RXDMA(x) \
+ (((x) & BIT_MASK_PCIE_MAX_RXDMA) << BIT_SHIFT_PCIE_MAX_RXDMA)
+#define BITS_PCIE_MAX_RXDMA \
+ (BIT_MASK_PCIE_MAX_RXDMA << BIT_SHIFT_PCIE_MAX_RXDMA)
+#define BIT_CLEAR_PCIE_MAX_RXDMA(x) ((x) & (~BITS_PCIE_MAX_RXDMA))
+#define BIT_GET_PCIE_MAX_RXDMA(x) \
+ (((x) >> BIT_SHIFT_PCIE_MAX_RXDMA) & BIT_MASK_PCIE_MAX_RXDMA)
+#define BIT_SET_PCIE_MAX_RXDMA(x, v) \
+ (BIT_CLEAR_PCIE_MAX_RXDMA(x) | BIT_PCIE_MAX_RXDMA(v))
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_HCI_CTRL (Offset 0x0300) */
-#define BIT_HCI_EN_HWEXT_L1 BIT(16)
+#define BIT_SHIFT_HCI_MAX_RXDMA 28
+#define BIT_MASK_HCI_MAX_RXDMA 0x7
+#define BIT_HCI_MAX_RXDMA(x) \
+ (((x) & BIT_MASK_HCI_MAX_RXDMA) << BIT_SHIFT_HCI_MAX_RXDMA)
+#define BITS_HCI_MAX_RXDMA (BIT_MASK_HCI_MAX_RXDMA << BIT_SHIFT_HCI_MAX_RXDMA)
+#define BIT_CLEAR_HCI_MAX_RXDMA(x) ((x) & (~BITS_HCI_MAX_RXDMA))
+#define BIT_GET_HCI_MAX_RXDMA(x) \
+ (((x) >> BIT_SHIFT_HCI_MAX_RXDMA) & BIT_MASK_HCI_MAX_RXDMA)
+#define BIT_SET_HCI_MAX_RXDMA(x, v) \
+ (BIT_CLEAR_HCI_MAX_RXDMA(x) | BIT_HCI_MAX_RXDMA(v))
#endif
-
#if (HALMAC_8881A_SUPPORT)
-
/* 2 REG_LX_CTRL1 (Offset 0x0300) */
-
-#define BIT_SHIFT_MAX_TXDMA 16
-#define BIT_MASK_MAX_TXDMA 0x7
-#define BIT_MAX_TXDMA(x) (((x) & BIT_MASK_MAX_TXDMA) << BIT_SHIFT_MAX_TXDMA)
-#define BIT_GET_MAX_TXDMA(x) (((x) >> BIT_SHIFT_MAX_TXDMA) & BIT_MASK_MAX_TXDMA)
-
+#define BIT_RX_LIT_EDN_SEL BIT(27)
+#define BIT_TX_LIT_EDN_SEL BIT(26)
+#define BIT_WT_LIT_EDN BIT(25)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_PCIE_CTRL (Offset 0x0300) */
+#define BIT_SHIFT_PCIE_MAX_TXDMA 24
+#define BIT_MASK_PCIE_MAX_TXDMA 0x7
+#define BIT_PCIE_MAX_TXDMA(x) \
+ (((x) & BIT_MASK_PCIE_MAX_TXDMA) << BIT_SHIFT_PCIE_MAX_TXDMA)
+#define BITS_PCIE_MAX_TXDMA \
+ (BIT_MASK_PCIE_MAX_TXDMA << BIT_SHIFT_PCIE_MAX_TXDMA)
+#define BIT_CLEAR_PCIE_MAX_TXDMA(x) ((x) & (~BITS_PCIE_MAX_TXDMA))
+#define BIT_GET_PCIE_MAX_TXDMA(x) \
+ (((x) >> BIT_SHIFT_PCIE_MAX_TXDMA) & BIT_MASK_PCIE_MAX_TXDMA)
+#define BIT_SET_PCIE_MAX_TXDMA(x, v) \
+ (BIT_CLEAR_PCIE_MAX_TXDMA(x) | BIT_PCIE_MAX_TXDMA(v))
-/* 2 REG_INT_MIG (Offset 0x0304) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_TXTTIMER_MATCH_NUM 28
-#define BIT_MASK_TXTTIMER_MATCH_NUM 0xf
-#define BIT_TXTTIMER_MATCH_NUM(x) (((x) & BIT_MASK_TXTTIMER_MATCH_NUM) << BIT_SHIFT_TXTTIMER_MATCH_NUM)
-#define BIT_GET_TXTTIMER_MATCH_NUM(x) (((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM) & BIT_MASK_TXTTIMER_MATCH_NUM)
+/* 2 REG_HCI_CTRL (Offset 0x0300) */
+#define BIT_SHIFT_HCI_MAX_TXDMA 24
+#define BIT_MASK_HCI_MAX_TXDMA 0x7
+#define BIT_HCI_MAX_TXDMA(x) \
+ (((x) & BIT_MASK_HCI_MAX_TXDMA) << BIT_SHIFT_HCI_MAX_TXDMA)
+#define BITS_HCI_MAX_TXDMA (BIT_MASK_HCI_MAX_TXDMA << BIT_SHIFT_HCI_MAX_TXDMA)
+#define BIT_CLEAR_HCI_MAX_TXDMA(x) ((x) & (~BITS_HCI_MAX_TXDMA))
+#define BIT_GET_HCI_MAX_TXDMA(x) \
+ (((x) >> BIT_SHIFT_HCI_MAX_TXDMA) & BIT_MASK_HCI_MAX_TXDMA)
+#define BIT_SET_HCI_MAX_TXDMA(x, v) \
+ (BIT_CLEAR_HCI_MAX_TXDMA(x) | BIT_HCI_MAX_TXDMA(v))
-#define BIT_SHIFT_TXPKT_NUM_MATCH 24
-#define BIT_MASK_TXPKT_NUM_MATCH 0xf
-#define BIT_TXPKT_NUM_MATCH(x) (((x) & BIT_MASK_TXPKT_NUM_MATCH) << BIT_SHIFT_TXPKT_NUM_MATCH)
-#define BIT_GET_TXPKT_NUM_MATCH(x) (((x) >> BIT_SHIFT_TXPKT_NUM_MATCH) & BIT_MASK_TXPKT_NUM_MATCH)
+#endif
+#if (HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_RXTTIMER_MATCH_NUM 20
-#define BIT_MASK_RXTTIMER_MATCH_NUM 0xf
-#define BIT_RXTTIMER_MATCH_NUM(x) (((x) & BIT_MASK_RXTTIMER_MATCH_NUM) << BIT_SHIFT_RXTTIMER_MATCH_NUM)
-#define BIT_GET_RXTTIMER_MATCH_NUM(x) (((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM) & BIT_MASK_RXTTIMER_MATCH_NUM)
+/* 2 REG_LX_CTRL1 (Offset 0x0300) */
+#define BIT_RD_LITT_EDN BIT(24)
-#define BIT_SHIFT_RXPKT_NUM_MATCH 16
-#define BIT_MASK_RXPKT_NUM_MATCH 0xf
-#define BIT_RXPKT_NUM_MATCH(x) (((x) & BIT_MASK_RXPKT_NUM_MATCH) << BIT_SHIFT_RXPKT_NUM_MATCH)
-#define BIT_GET_RXPKT_NUM_MATCH(x) (((x) >> BIT_SHIFT_RXPKT_NUM_MATCH) & BIT_MASK_RXPKT_NUM_MATCH)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_MIGRATE_TIMER 0
-#define BIT_MASK_MIGRATE_TIMER 0xffff
-#define BIT_MIGRATE_TIMER(x) (((x) & BIT_MASK_MIGRATE_TIMER) << BIT_SHIFT_MIGRATE_TIMER)
-#define BIT_GET_MIGRATE_TIMER(x) (((x) >> BIT_SHIFT_MIGRATE_TIMER) & BIT_MASK_MIGRATE_TIMER)
+/* 2 REG_PCIE_CTRL (Offset 0x0300) */
+#define BIT_PWR_SCALE_START_PS BIT(23)
-/* 2 REG_BCNQ_TXBD_DESA (Offset 0x0308) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_BCNQ_TXBD_DESA 0
-#define BIT_MASK_BCNQ_TXBD_DESA 0xffffffffffffffffL
-#define BIT_BCNQ_TXBD_DESA(x) (((x) & BIT_MASK_BCNQ_TXBD_DESA) << BIT_SHIFT_BCNQ_TXBD_DESA)
-#define BIT_GET_BCNQ_TXBD_DESA(x) (((x) >> BIT_SHIFT_BCNQ_TXBD_DESA) & BIT_MASK_BCNQ_TXBD_DESA)
+/* 2 REG_PCIE_CTRL (Offset 0x0300) */
+#define BIT_PCIE_RST_TRXDMA_INTF BIT(20)
-/* 2 REG_MGQ_TXBD_DESA (Offset 0x0310) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_MGQ_TXBD_DESA 0
-#define BIT_MASK_MGQ_TXBD_DESA 0xffffffffffffffffL
-#define BIT_MGQ_TXBD_DESA(x) (((x) & BIT_MASK_MGQ_TXBD_DESA) << BIT_SHIFT_MGQ_TXBD_DESA)
-#define BIT_GET_MGQ_TXBD_DESA(x) (((x) >> BIT_SHIFT_MGQ_TXBD_DESA) & BIT_MASK_MGQ_TXBD_DESA)
+/* 2 REG_HCI_CTRL (Offset 0x0300) */
+#define BIT_HCI_RST_TRXDMA_INTF BIT(20)
-/* 2 REG_VOQ_TXBD_DESA (Offset 0x0318) */
+#endif
+#if (HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_VOQ_TXBD_DESA 0
-#define BIT_MASK_VOQ_TXBD_DESA 0xffffffffffffffffL
-#define BIT_VOQ_TXBD_DESA(x) (((x) & BIT_MASK_VOQ_TXBD_DESA) << BIT_SHIFT_VOQ_TXBD_DESA)
-#define BIT_GET_VOQ_TXBD_DESA(x) (((x) >> BIT_SHIFT_VOQ_TXBD_DESA) & BIT_MASK_VOQ_TXBD_DESA)
+/* 2 REG_LX_CTRL1 (Offset 0x0300) */
+#define BIT_SHIFT_MAX_RXDMA 20
+#define BIT_MASK_MAX_RXDMA 0x7
+#define BIT_MAX_RXDMA(x) (((x) & BIT_MASK_MAX_RXDMA) << BIT_SHIFT_MAX_RXDMA)
+#define BITS_MAX_RXDMA (BIT_MASK_MAX_RXDMA << BIT_SHIFT_MAX_RXDMA)
+#define BIT_CLEAR_MAX_RXDMA(x) ((x) & (~BITS_MAX_RXDMA))
+#define BIT_GET_MAX_RXDMA(x) (((x) >> BIT_SHIFT_MAX_RXDMA) & BIT_MASK_MAX_RXDMA)
+#define BIT_SET_MAX_RXDMA(x, v) (BIT_CLEAR_MAX_RXDMA(x) | BIT_MAX_RXDMA(v))
-/* 2 REG_VIQ_TXBD_DESA (Offset 0x0320) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_VIQ_TXBD_DESA 0
-#define BIT_MASK_VIQ_TXBD_DESA 0xffffffffffffffffL
-#define BIT_VIQ_TXBD_DESA(x) (((x) & BIT_MASK_VIQ_TXBD_DESA) << BIT_SHIFT_VIQ_TXBD_DESA)
-#define BIT_GET_VIQ_TXBD_DESA(x) (((x) >> BIT_SHIFT_VIQ_TXBD_DESA) & BIT_MASK_VIQ_TXBD_DESA)
+/* 2 REG_PCIE_CTRL (Offset 0x0300) */
+#define BIT_PCIE_EN_SWENT_L23 BIT(17)
-/* 2 REG_BEQ_TXBD_DESA (Offset 0x0328) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_BEQ_TXBD_DESA 0
-#define BIT_MASK_BEQ_TXBD_DESA 0xffffffffffffffffL
-#define BIT_BEQ_TXBD_DESA(x) (((x) & BIT_MASK_BEQ_TXBD_DESA) << BIT_SHIFT_BEQ_TXBD_DESA)
-#define BIT_GET_BEQ_TXBD_DESA(x) (((x) >> BIT_SHIFT_BEQ_TXBD_DESA) & BIT_MASK_BEQ_TXBD_DESA)
+/* 2 REG_HCI_CTRL (Offset 0x0300) */
+#define BIT_HCI_EN_SWENT_L23 BIT(17)
-/* 2 REG_BKQ_TXBD_DESA (Offset 0x0330) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_BKQ_TXBD_DESA 0
-#define BIT_MASK_BKQ_TXBD_DESA 0xffffffffffffffffL
-#define BIT_BKQ_TXBD_DESA(x) (((x) & BIT_MASK_BKQ_TXBD_DESA) << BIT_SHIFT_BKQ_TXBD_DESA)
-#define BIT_GET_BKQ_TXBD_DESA(x) (((x) >> BIT_SHIFT_BKQ_TXBD_DESA) & BIT_MASK_BKQ_TXBD_DESA)
+/* 2 REG_PCIE_CTRL (Offset 0x0300) */
+#define BIT_PCIE_EN_HWEXT_L1 BIT(16)
-/* 2 REG_RXQ_RXBD_DESA (Offset 0x0338) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_RXQ_RXBD_DESA 0
-#define BIT_MASK_RXQ_RXBD_DESA 0xffffffffffffffffL
-#define BIT_RXQ_RXBD_DESA(x) (((x) & BIT_MASK_RXQ_RXBD_DESA) << BIT_SHIFT_RXQ_RXBD_DESA)
-#define BIT_GET_RXQ_RXBD_DESA(x) (((x) >> BIT_SHIFT_RXQ_RXBD_DESA) & BIT_MASK_RXQ_RXBD_DESA)
+/* 2 REG_HCI_CTRL (Offset 0x0300) */
+#define BIT_HCI_EN_HWEXT_L1 BIT(16)
-/* 2 REG_HI0Q_TXBD_DESA (Offset 0x0340) */
+#endif
+#if (HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_HI0Q_TXBD_DESA 0
-#define BIT_MASK_HI0Q_TXBD_DESA 0xffffffffffffffffL
-#define BIT_HI0Q_TXBD_DESA(x) (((x) & BIT_MASK_HI0Q_TXBD_DESA) << BIT_SHIFT_HI0Q_TXBD_DESA)
-#define BIT_GET_HI0Q_TXBD_DESA(x) (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA) & BIT_MASK_HI0Q_TXBD_DESA)
+/* 2 REG_LX_CTRL1 (Offset 0x0300) */
+#define BIT_SHIFT_MAX_TXDMA 16
+#define BIT_MASK_MAX_TXDMA 0x7
+#define BIT_MAX_TXDMA(x) (((x) & BIT_MASK_MAX_TXDMA) << BIT_SHIFT_MAX_TXDMA)
+#define BITS_MAX_TXDMA (BIT_MASK_MAX_TXDMA << BIT_SHIFT_MAX_TXDMA)
+#define BIT_CLEAR_MAX_TXDMA(x) ((x) & (~BITS_MAX_TXDMA))
+#define BIT_GET_MAX_TXDMA(x) (((x) >> BIT_SHIFT_MAX_TXDMA) & BIT_MASK_MAX_TXDMA)
+#define BIT_SET_MAX_TXDMA(x, v) (BIT_CLEAR_MAX_TXDMA(x) | BIT_MAX_TXDMA(v))
-/* 2 REG_HI1Q_TXBD_DESA (Offset 0x0348) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_HI1Q_TXBD_DESA 0
-#define BIT_MASK_HI1Q_TXBD_DESA 0xffffffffffffffffL
-#define BIT_HI1Q_TXBD_DESA(x) (((x) & BIT_MASK_HI1Q_TXBD_DESA) << BIT_SHIFT_HI1Q_TXBD_DESA)
-#define BIT_GET_HI1Q_TXBD_DESA(x) (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA) & BIT_MASK_HI1Q_TXBD_DESA)
+/* 2 REG_PCIE_CTRL (Offset 0x0300) */
+#define BIT_STOP_P0_MPRT_BCNQ4 BIT(6)
+#define BIT_STOP_P0_MPRT_BCNQ3 BIT(4)
+#define BIT_STOP_P0_MPRT_BCNQ2 BIT(2)
+#define BIT_STOP_P0_MPRT_BCNQ1 BIT(0)
-/* 2 REG_HI2Q_TXBD_DESA (Offset 0x0350) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_HI2Q_TXBD_DESA 0
-#define BIT_MASK_HI2Q_TXBD_DESA 0xffffffffffffffffL
-#define BIT_HI2Q_TXBD_DESA(x) (((x) & BIT_MASK_HI2Q_TXBD_DESA) << BIT_SHIFT_HI2Q_TXBD_DESA)
-#define BIT_GET_HI2Q_TXBD_DESA(x) (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA) & BIT_MASK_HI2Q_TXBD_DESA)
+/* 2 REG_INT_MIG (Offset 0x0304) */
+#define BIT_SHIFT_TXTTIMER_MATCH_NUM 28
+#define BIT_MASK_TXTTIMER_MATCH_NUM 0xf
+#define BIT_TXTTIMER_MATCH_NUM(x) \
+ (((x) & BIT_MASK_TXTTIMER_MATCH_NUM) << BIT_SHIFT_TXTTIMER_MATCH_NUM)
+#define BITS_TXTTIMER_MATCH_NUM \
+ (BIT_MASK_TXTTIMER_MATCH_NUM << BIT_SHIFT_TXTTIMER_MATCH_NUM)
+#define BIT_CLEAR_TXTTIMER_MATCH_NUM(x) ((x) & (~BITS_TXTTIMER_MATCH_NUM))
+#define BIT_GET_TXTTIMER_MATCH_NUM(x) \
+ (((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM) & BIT_MASK_TXTTIMER_MATCH_NUM)
+#define BIT_SET_TXTTIMER_MATCH_NUM(x, v) \
+ (BIT_CLEAR_TXTTIMER_MATCH_NUM(x) | BIT_TXTTIMER_MATCH_NUM(v))
-/* 2 REG_HI3Q_TXBD_DESA (Offset 0x0358) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_HI3Q_TXBD_DESA 0
-#define BIT_MASK_HI3Q_TXBD_DESA 0xffffffffffffffffL
-#define BIT_HI3Q_TXBD_DESA(x) (((x) & BIT_MASK_HI3Q_TXBD_DESA) << BIT_SHIFT_HI3Q_TXBD_DESA)
-#define BIT_GET_HI3Q_TXBD_DESA(x) (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA) & BIT_MASK_HI3Q_TXBD_DESA)
+/* 2 REG_ACH_CTRL (Offset 0x0304) */
+#define BIT_STOP_P0HIQ19 BIT(27)
+#define BIT_STOP_P0HIQ18 BIT(26)
+#define BIT_STOP_P0HIQ17 BIT(25)
-/* 2 REG_HI4Q_TXBD_DESA (Offset 0x0360) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_HI4Q_TXBD_DESA 0
-#define BIT_MASK_HI4Q_TXBD_DESA 0xffffffffffffffffL
-#define BIT_HI4Q_TXBD_DESA(x) (((x) & BIT_MASK_HI4Q_TXBD_DESA) << BIT_SHIFT_HI4Q_TXBD_DESA)
-#define BIT_GET_HI4Q_TXBD_DESA(x) (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA) & BIT_MASK_HI4Q_TXBD_DESA)
+/* 2 REG_INT_MIG (Offset 0x0304) */
+#define BIT_SHIFT_TXPKT_NUM_MATCH 24
+#define BIT_MASK_TXPKT_NUM_MATCH 0xf
+#define BIT_TXPKT_NUM_MATCH(x) \
+ (((x) & BIT_MASK_TXPKT_NUM_MATCH) << BIT_SHIFT_TXPKT_NUM_MATCH)
+#define BITS_TXPKT_NUM_MATCH \
+ (BIT_MASK_TXPKT_NUM_MATCH << BIT_SHIFT_TXPKT_NUM_MATCH)
+#define BIT_CLEAR_TXPKT_NUM_MATCH(x) ((x) & (~BITS_TXPKT_NUM_MATCH))
+#define BIT_GET_TXPKT_NUM_MATCH(x) \
+ (((x) >> BIT_SHIFT_TXPKT_NUM_MATCH) & BIT_MASK_TXPKT_NUM_MATCH)
+#define BIT_SET_TXPKT_NUM_MATCH(x, v) \
+ (BIT_CLEAR_TXPKT_NUM_MATCH(x) | BIT_TXPKT_NUM_MATCH(v))
-/* 2 REG_HI5Q_TXBD_DESA (Offset 0x0368) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_HI5Q_TXBD_DESA 0
-#define BIT_MASK_HI5Q_TXBD_DESA 0xffffffffffffffffL
-#define BIT_HI5Q_TXBD_DESA(x) (((x) & BIT_MASK_HI5Q_TXBD_DESA) << BIT_SHIFT_HI5Q_TXBD_DESA)
-#define BIT_GET_HI5Q_TXBD_DESA(x) (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA) & BIT_MASK_HI5Q_TXBD_DESA)
+/* 2 REG_ACH_CTRL (Offset 0x0304) */
+#define BIT_STOP_P0HIQ16 BIT(24)
-/* 2 REG_HI6Q_TXBD_DESA (Offset 0x0370) */
+#endif
+#if (HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_HI6Q_TXBD_DESA 0
-#define BIT_MASK_HI6Q_TXBD_DESA 0xffffffffffffffffL
-#define BIT_HI6Q_TXBD_DESA(x) (((x) & BIT_MASK_HI6Q_TXBD_DESA) << BIT_SHIFT_HI6Q_TXBD_DESA)
-#define BIT_GET_HI6Q_TXBD_DESA(x) (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA) & BIT_MASK_HI6Q_TXBD_DESA)
+/* 2 REG_INT_MIG (Offset 0x0304) */
+#define BIT_SHIFT_TRXCOUNTER_MATCH 24
+#define BIT_MASK_TRXCOUNTER_MATCH 0xff
+#define BIT_TRXCOUNTER_MATCH(x) \
+ (((x) & BIT_MASK_TRXCOUNTER_MATCH) << BIT_SHIFT_TRXCOUNTER_MATCH)
+#define BITS_TRXCOUNTER_MATCH \
+ (BIT_MASK_TRXCOUNTER_MATCH << BIT_SHIFT_TRXCOUNTER_MATCH)
+#define BIT_CLEAR_TRXCOUNTER_MATCH(x) ((x) & (~BITS_TRXCOUNTER_MATCH))
+#define BIT_GET_TRXCOUNTER_MATCH(x) \
+ (((x) >> BIT_SHIFT_TRXCOUNTER_MATCH) & BIT_MASK_TRXCOUNTER_MATCH)
+#define BIT_SET_TRXCOUNTER_MATCH(x, v) \
+ (BIT_CLEAR_TRXCOUNTER_MATCH(x) | BIT_TRXCOUNTER_MATCH(v))
-/* 2 REG_HI7Q_TXBD_DESA (Offset 0x0378) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_HI7Q_TXBD_DESA 0
-#define BIT_MASK_HI7Q_TXBD_DESA 0xffffffffffffffffL
-#define BIT_HI7Q_TXBD_DESA(x) (((x) & BIT_MASK_HI7Q_TXBD_DESA) << BIT_SHIFT_HI7Q_TXBD_DESA)
-#define BIT_GET_HI7Q_TXBD_DESA(x) (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA) & BIT_MASK_HI7Q_TXBD_DESA)
+/* 2 REG_ACH_CTRL (Offset 0x0304) */
+#define BIT_RX_CLOSE_EN_V1 BIT(21)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-
-/* 2 REG_MGQ_TXBD_NUM (Offset 0x0380) */
+/* 2 REG_INT_MIG (Offset 0x0304) */
-#define BIT_PCIE_MGQ_FLAG BIT(14)
+#define BIT_SHIFT_RXTTIMER_MATCH_NUM 20
+#define BIT_MASK_RXTTIMER_MATCH_NUM 0xf
+#define BIT_RXTTIMER_MATCH_NUM(x) \
+ (((x) & BIT_MASK_RXTTIMER_MATCH_NUM) << BIT_SHIFT_RXTTIMER_MATCH_NUM)
+#define BITS_RXTTIMER_MATCH_NUM \
+ (BIT_MASK_RXTTIMER_MATCH_NUM << BIT_SHIFT_RXTTIMER_MATCH_NUM)
+#define BIT_CLEAR_RXTTIMER_MATCH_NUM(x) ((x) & (~BITS_RXTTIMER_MATCH_NUM))
+#define BIT_GET_RXTTIMER_MATCH_NUM(x) \
+ (((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM) & BIT_MASK_RXTTIMER_MATCH_NUM)
+#define BIT_SET_RXTTIMER_MATCH_NUM(x, v) \
+ (BIT_CLEAR_RXTTIMER_MATCH_NUM(x) | BIT_RXTTIMER_MATCH_NUM(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_ACH_CTRL (Offset 0x0304) */
+#define BIT_STOP_FWCMDQ BIT(20)
+#define BIT_STOP_P0BCNQ BIT(18)
-/* 2 REG_MGQ_TXBD_NUM (Offset 0x0380) */
+#endif
-#define BIT_HCI_MGQ_FLAG BIT(14)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_INT_MIG (Offset 0x0304) */
+#define BIT_SHIFT_RXPKT_NUM_MATCH 16
+#define BIT_MASK_RXPKT_NUM_MATCH 0xf
+#define BIT_RXPKT_NUM_MATCH(x) \
+ (((x) & BIT_MASK_RXPKT_NUM_MATCH) << BIT_SHIFT_RXPKT_NUM_MATCH)
+#define BITS_RXPKT_NUM_MATCH \
+ (BIT_MASK_RXPKT_NUM_MATCH << BIT_SHIFT_RXPKT_NUM_MATCH)
+#define BIT_CLEAR_RXPKT_NUM_MATCH(x) ((x) & (~BITS_RXPKT_NUM_MATCH))
+#define BIT_GET_RXPKT_NUM_MATCH(x) \
+ (((x) >> BIT_SHIFT_RXPKT_NUM_MATCH) & BIT_MASK_RXPKT_NUM_MATCH)
+#define BIT_SET_RXPKT_NUM_MATCH(x, v) \
+ (BIT_CLEAR_RXPKT_NUM_MATCH(x) | BIT_RXPKT_NUM_MATCH(v))
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_MGQ_TXBD_NUM (Offset 0x0380) */
+/* 2 REG_ACH_CTRL (Offset 0x0304) */
+#define BIT_STOP_P0MGQ BIT(16)
-#define BIT_SHIFT_MGQ_DESC_MODE 12
-#define BIT_MASK_MGQ_DESC_MODE 0x3
-#define BIT_MGQ_DESC_MODE(x) (((x) & BIT_MASK_MGQ_DESC_MODE) << BIT_SHIFT_MGQ_DESC_MODE)
-#define BIT_GET_MGQ_DESC_MODE(x) (((x) >> BIT_SHIFT_MGQ_DESC_MODE) & BIT_MASK_MGQ_DESC_MODE)
+#endif
+#if (HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_MGQ_DESC_NUM 0
-#define BIT_MASK_MGQ_DESC_NUM 0xfff
-#define BIT_MGQ_DESC_NUM(x) (((x) & BIT_MASK_MGQ_DESC_NUM) << BIT_SHIFT_MGQ_DESC_NUM)
-#define BIT_GET_MGQ_DESC_NUM(x) (((x) >> BIT_SHIFT_MGQ_DESC_NUM) & BIT_MASK_MGQ_DESC_NUM)
+/* 2 REG_INT_MIG (Offset 0x0304) */
+#define BIT_SHIFT_TRXTIMER_MATCH 16
+#define BIT_MASK_TRXTIMER_MATCH 0xff
+#define BIT_TRXTIMER_MATCH(x) \
+ (((x) & BIT_MASK_TRXTIMER_MATCH) << BIT_SHIFT_TRXTIMER_MATCH)
+#define BITS_TRXTIMER_MATCH \
+ (BIT_MASK_TRXTIMER_MATCH << BIT_SHIFT_TRXTIMER_MATCH)
+#define BIT_CLEAR_TRXTIMER_MATCH(x) ((x) & (~BITS_TRXTIMER_MATCH))
+#define BIT_GET_TRXTIMER_MATCH(x) \
+ (((x) >> BIT_SHIFT_TRXTIMER_MATCH) & BIT_MASK_TRXTIMER_MATCH)
+#define BIT_SET_TRXTIMER_MATCH(x, v) \
+ (BIT_CLEAR_TRXTIMER_MATCH(x) | BIT_TRXTIMER_MATCH(v))
-/* 2 REG_RX_RXBD_NUM (Offset 0x0382) */
+#endif
-#define BIT_SYS_32_64 BIT(15)
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_BCNQ_DESC_MODE 13
-#define BIT_MASK_BCNQ_DESC_MODE 0x3
-#define BIT_BCNQ_DESC_MODE(x) (((x) & BIT_MASK_BCNQ_DESC_MODE) << BIT_SHIFT_BCNQ_DESC_MODE)
-#define BIT_GET_BCNQ_DESC_MODE(x) (((x) >> BIT_SHIFT_BCNQ_DESC_MODE) & BIT_MASK_BCNQ_DESC_MODE)
+/* 2 REG_ACH_CTRL (Offset 0x0304) */
+#define BIT_STOP_ACH13 BIT(15)
+#define BIT_STOP_ACH12 BIT(14)
+#define BIT_STOP_ACH11 BIT(13)
+#define BIT_STOP_ACH10 BIT(12)
+#define BIT_STOP_ACH9 BIT(11)
+#define BIT_STOP_ACH8 BIT(10)
+#define BIT_STOP_ACH7 BIT(9)
+#define BIT_STOP_ACH6 BIT(8)
+#define BIT_STOP_ACH5 BIT(7)
+#define BIT_STOP_ACH4 BIT(6)
+#define BIT_STOP_ACH3 BIT(5)
+#define BIT_STOP_ACH2 BIT(4)
+#define BIT_STOP_ACH1 BIT(3)
+#define BIT_STOP_ACH0 BIT(2)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_INT_MIG (Offset 0x0304) */
+#define BIT_SHIFT_MIGRATE_TIMER 0
+#define BIT_MASK_MIGRATE_TIMER 0xffff
+#define BIT_MIGRATE_TIMER(x) \
+ (((x) & BIT_MASK_MIGRATE_TIMER) << BIT_SHIFT_MIGRATE_TIMER)
+#define BITS_MIGRATE_TIMER (BIT_MASK_MIGRATE_TIMER << BIT_SHIFT_MIGRATE_TIMER)
+#define BIT_CLEAR_MIGRATE_TIMER(x) ((x) & (~BITS_MIGRATE_TIMER))
+#define BIT_GET_MIGRATE_TIMER(x) \
+ (((x) >> BIT_SHIFT_MIGRATE_TIMER) & BIT_MASK_MIGRATE_TIMER)
+#define BIT_SET_MIGRATE_TIMER(x, v) \
+ (BIT_CLEAR_MIGRATE_TIMER(x) | BIT_MIGRATE_TIMER(v))
-/* 2 REG_RX_RXBD_NUM (Offset 0x0382) */
+#endif
-#define BIT_PCIE_BCNQ_FLAG BIT(12)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_ACH_CTRL (Offset 0x0304) */
+#define BIT_STOP_P0RX BIT(0)
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8822C_SUPPORT)
-/* 2 REG_RX_RXBD_NUM (Offset 0x0382) */
+/* 2 REG_INT_MIG (Offset 0x0304) */
-#define BIT_HCI_BCNQ_FLAG BIT(12)
+#define BIT_SHIFT_TRXTIMER_UNIT 0
+#define BIT_MASK_TRXTIMER_UNIT 0x3
+#define BIT_TRXTIMER_UNIT(x) \
+ (((x) & BIT_MASK_TRXTIMER_UNIT) << BIT_SHIFT_TRXTIMER_UNIT)
+#define BITS_TRXTIMER_UNIT (BIT_MASK_TRXTIMER_UNIT << BIT_SHIFT_TRXTIMER_UNIT)
+#define BIT_CLEAR_TRXTIMER_UNIT(x) ((x) & (~BITS_TRXTIMER_UNIT))
+#define BIT_GET_TRXTIMER_UNIT(x) \
+ (((x) >> BIT_SHIFT_TRXTIMER_UNIT) & BIT_MASK_TRXTIMER_UNIT)
+#define BIT_SET_TRXTIMER_UNIT(x, v) \
+ (BIT_CLEAR_TRXTIMER_UNIT(x) | BIT_TRXTIMER_UNIT(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_HIQ_CTRL (Offset 0x0308) */
+#define BIT_STOP_P0HIQ15 BIT(15)
+#define BIT_STOP_P0HIQ14 BIT(14)
+#define BIT_STOP_P0HIQ13 BIT(13)
+#define BIT_STOP_P0HIQ12 BIT(12)
+#define BIT_STOP_P0HIQ11 BIT(11)
+#define BIT_STOP_P0HIQ10 BIT(10)
+#define BIT_STOP_P0HIQ9 BIT(9)
+#define BIT_STOP_P0HIQ8 BIT(8)
+#define BIT_STOP_P0HIQ7 BIT(7)
+#define BIT_STOP_P0HIQ6 BIT(6)
+#define BIT_STOP_P0HIQ5 BIT(5)
+#define BIT_STOP_P0HIQ4 BIT(4)
+#define BIT_STOP_P0HIQ3 BIT(3)
+#define BIT_STOP_P0HIQ2 BIT(2)
+#define BIT_STOP_P0HIQ1 BIT(1)
-/* 2 REG_RX_RXBD_NUM (Offset 0x0382) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_RXQ_DESC_NUM 0
-#define BIT_MASK_RXQ_DESC_NUM 0xfff
-#define BIT_RXQ_DESC_NUM(x) (((x) & BIT_MASK_RXQ_DESC_NUM) << BIT_SHIFT_RXQ_DESC_NUM)
-#define BIT_GET_RXQ_DESC_NUM(x) (((x) >> BIT_SHIFT_RXQ_DESC_NUM) & BIT_MASK_RXQ_DESC_NUM)
+/* 2 REG_BCNQ_TXBD_DESA (Offset 0x0308) */
+#define BIT_SHIFT_BCNQ_TXBD_DESA 0
+#define BIT_MASK_BCNQ_TXBD_DESA 0xffffffffffffffffL
+#define BIT_BCNQ_TXBD_DESA(x) \
+ (((x) & BIT_MASK_BCNQ_TXBD_DESA) << BIT_SHIFT_BCNQ_TXBD_DESA)
+#define BITS_BCNQ_TXBD_DESA \
+ (BIT_MASK_BCNQ_TXBD_DESA << BIT_SHIFT_BCNQ_TXBD_DESA)
+#define BIT_CLEAR_BCNQ_TXBD_DESA(x) ((x) & (~BITS_BCNQ_TXBD_DESA))
+#define BIT_GET_BCNQ_TXBD_DESA(x) \
+ (((x) >> BIT_SHIFT_BCNQ_TXBD_DESA) & BIT_MASK_BCNQ_TXBD_DESA)
+#define BIT_SET_BCNQ_TXBD_DESA(x, v) \
+ (BIT_CLEAR_BCNQ_TXBD_DESA(x) | BIT_BCNQ_TXBD_DESA(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+/* 2 REG_HIQ_CTRL (Offset 0x0308) */
-/* 2 REG_VOQ_TXBD_NUM (Offset 0x0384) */
-
-#define BIT_PCIE_VOQ_FLAG BIT(14)
+#define BIT_STOP_P0HIQ0 BIT(0)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_MGQ_TXBD_DESA (Offset 0x0310) */
+#define BIT_SHIFT_MGQ_TXBD_DESA 0
+#define BIT_MASK_MGQ_TXBD_DESA 0xffffffffffffffffL
+#define BIT_MGQ_TXBD_DESA(x) \
+ (((x) & BIT_MASK_MGQ_TXBD_DESA) << BIT_SHIFT_MGQ_TXBD_DESA)
+#define BITS_MGQ_TXBD_DESA (BIT_MASK_MGQ_TXBD_DESA << BIT_SHIFT_MGQ_TXBD_DESA)
+#define BIT_CLEAR_MGQ_TXBD_DESA(x) ((x) & (~BITS_MGQ_TXBD_DESA))
+#define BIT_GET_MGQ_TXBD_DESA(x) \
+ (((x) >> BIT_SHIFT_MGQ_TXBD_DESA) & BIT_MASK_MGQ_TXBD_DESA)
+#define BIT_SET_MGQ_TXBD_DESA(x, v) \
+ (BIT_CLEAR_MGQ_TXBD_DESA(x) | BIT_MGQ_TXBD_DESA(v))
-/* 2 REG_VOQ_TXBD_NUM (Offset 0x0384) */
+/* 2 REG_VOQ_TXBD_DESA (Offset 0x0318) */
-#define BIT_HCI_VOQ_FLAG BIT(14)
+#define BIT_SHIFT_VOQ_TXBD_DESA 0
+#define BIT_MASK_VOQ_TXBD_DESA 0xffffffffffffffffL
+#define BIT_VOQ_TXBD_DESA(x) \
+ (((x) & BIT_MASK_VOQ_TXBD_DESA) << BIT_SHIFT_VOQ_TXBD_DESA)
+#define BITS_VOQ_TXBD_DESA (BIT_MASK_VOQ_TXBD_DESA << BIT_SHIFT_VOQ_TXBD_DESA)
+#define BIT_CLEAR_VOQ_TXBD_DESA(x) ((x) & (~BITS_VOQ_TXBD_DESA))
+#define BIT_GET_VOQ_TXBD_DESA(x) \
+ (((x) >> BIT_SHIFT_VOQ_TXBD_DESA) & BIT_MASK_VOQ_TXBD_DESA)
+#define BIT_SET_VOQ_TXBD_DESA(x, v) \
+ (BIT_CLEAR_VOQ_TXBD_DESA(x) | BIT_VOQ_TXBD_DESA(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_ACH0_TXBD_DESA_L (Offset 0x0318) */
+#define BIT_SHIFT_ACH0_TXBD_DESA_L 0
+#define BIT_MASK_ACH0_TXBD_DESA_L 0xffffffffL
+#define BIT_ACH0_TXBD_DESA_L(x) \
+ (((x) & BIT_MASK_ACH0_TXBD_DESA_L) << BIT_SHIFT_ACH0_TXBD_DESA_L)
+#define BITS_ACH0_TXBD_DESA_L \
+ (BIT_MASK_ACH0_TXBD_DESA_L << BIT_SHIFT_ACH0_TXBD_DESA_L)
+#define BIT_CLEAR_ACH0_TXBD_DESA_L(x) ((x) & (~BITS_ACH0_TXBD_DESA_L))
+#define BIT_GET_ACH0_TXBD_DESA_L(x) \
+ (((x) >> BIT_SHIFT_ACH0_TXBD_DESA_L) & BIT_MASK_ACH0_TXBD_DESA_L)
+#define BIT_SET_ACH0_TXBD_DESA_L(x, v) \
+ (BIT_CLEAR_ACH0_TXBD_DESA_L(x) | BIT_ACH0_TXBD_DESA_L(v))
-/* 2 REG_VOQ_TXBD_NUM (Offset 0x0384) */
+/* 2 REG_ACH0_TXBD_DESA_H (Offset 0x031C) */
+#define BIT_SHIFT_ACH0_TXBD_DESA_H 0
+#define BIT_MASK_ACH0_TXBD_DESA_H 0xffffffffL
+#define BIT_ACH0_TXBD_DESA_H(x) \
+ (((x) & BIT_MASK_ACH0_TXBD_DESA_H) << BIT_SHIFT_ACH0_TXBD_DESA_H)
+#define BITS_ACH0_TXBD_DESA_H \
+ (BIT_MASK_ACH0_TXBD_DESA_H << BIT_SHIFT_ACH0_TXBD_DESA_H)
+#define BIT_CLEAR_ACH0_TXBD_DESA_H(x) ((x) & (~BITS_ACH0_TXBD_DESA_H))
+#define BIT_GET_ACH0_TXBD_DESA_H(x) \
+ (((x) >> BIT_SHIFT_ACH0_TXBD_DESA_H) & BIT_MASK_ACH0_TXBD_DESA_H)
+#define BIT_SET_ACH0_TXBD_DESA_H(x, v) \
+ (BIT_CLEAR_ACH0_TXBD_DESA_H(x) | BIT_ACH0_TXBD_DESA_H(v))
-#define BIT_SHIFT_VOQ_DESC_MODE 12
-#define BIT_MASK_VOQ_DESC_MODE 0x3
-#define BIT_VOQ_DESC_MODE(x) (((x) & BIT_MASK_VOQ_DESC_MODE) << BIT_SHIFT_VOQ_DESC_MODE)
-#define BIT_GET_VOQ_DESC_MODE(x) (((x) >> BIT_SHIFT_VOQ_DESC_MODE) & BIT_MASK_VOQ_DESC_MODE)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_VOQ_DESC_NUM 0
-#define BIT_MASK_VOQ_DESC_NUM 0xfff
-#define BIT_VOQ_DESC_NUM(x) (((x) & BIT_MASK_VOQ_DESC_NUM) << BIT_SHIFT_VOQ_DESC_NUM)
-#define BIT_GET_VOQ_DESC_NUM(x) (((x) >> BIT_SHIFT_VOQ_DESC_NUM) & BIT_MASK_VOQ_DESC_NUM)
+/* 2 REG_VIQ_TXBD_DESA (Offset 0x0320) */
+#define BIT_SHIFT_VIQ_TXBD_DESA 0
+#define BIT_MASK_VIQ_TXBD_DESA 0xffffffffffffffffL
+#define BIT_VIQ_TXBD_DESA(x) \
+ (((x) & BIT_MASK_VIQ_TXBD_DESA) << BIT_SHIFT_VIQ_TXBD_DESA)
+#define BITS_VIQ_TXBD_DESA (BIT_MASK_VIQ_TXBD_DESA << BIT_SHIFT_VIQ_TXBD_DESA)
+#define BIT_CLEAR_VIQ_TXBD_DESA(x) ((x) & (~BITS_VIQ_TXBD_DESA))
+#define BIT_GET_VIQ_TXBD_DESA(x) \
+ (((x) >> BIT_SHIFT_VIQ_TXBD_DESA) & BIT_MASK_VIQ_TXBD_DESA)
+#define BIT_SET_VIQ_TXBD_DESA(x, v) \
+ (BIT_CLEAR_VIQ_TXBD_DESA(x) | BIT_VIQ_TXBD_DESA(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_ACH1_TXBD_DESA_L (Offset 0x0320) */
+#define BIT_SHIFT_ACH1_TXBD_DESA_L 0
+#define BIT_MASK_ACH1_TXBD_DESA_L 0xffffffffL
+#define BIT_ACH1_TXBD_DESA_L(x) \
+ (((x) & BIT_MASK_ACH1_TXBD_DESA_L) << BIT_SHIFT_ACH1_TXBD_DESA_L)
+#define BITS_ACH1_TXBD_DESA_L \
+ (BIT_MASK_ACH1_TXBD_DESA_L << BIT_SHIFT_ACH1_TXBD_DESA_L)
+#define BIT_CLEAR_ACH1_TXBD_DESA_L(x) ((x) & (~BITS_ACH1_TXBD_DESA_L))
+#define BIT_GET_ACH1_TXBD_DESA_L(x) \
+ (((x) >> BIT_SHIFT_ACH1_TXBD_DESA_L) & BIT_MASK_ACH1_TXBD_DESA_L)
+#define BIT_SET_ACH1_TXBD_DESA_L(x, v) \
+ (BIT_CLEAR_ACH1_TXBD_DESA_L(x) | BIT_ACH1_TXBD_DESA_L(v))
-/* 2 REG_VIQ_TXBD_NUM (Offset 0x0386) */
+/* 2 REG_ACH1_TXBD_DESA_H (Offset 0x0324) */
-#define BIT_PCIE_VIQ_FLAG BIT(14)
+#define BIT_SHIFT_ACH1_TXBD_DESA_H 0
+#define BIT_MASK_ACH1_TXBD_DESA_H 0xffffffffL
+#define BIT_ACH1_TXBD_DESA_H(x) \
+ (((x) & BIT_MASK_ACH1_TXBD_DESA_H) << BIT_SHIFT_ACH1_TXBD_DESA_H)
+#define BITS_ACH1_TXBD_DESA_H \
+ (BIT_MASK_ACH1_TXBD_DESA_H << BIT_SHIFT_ACH1_TXBD_DESA_H)
+#define BIT_CLEAR_ACH1_TXBD_DESA_H(x) ((x) & (~BITS_ACH1_TXBD_DESA_H))
+#define BIT_GET_ACH1_TXBD_DESA_H(x) \
+ (((x) >> BIT_SHIFT_ACH1_TXBD_DESA_H) & BIT_MASK_ACH1_TXBD_DESA_H)
+#define BIT_SET_ACH1_TXBD_DESA_H(x, v) \
+ (BIT_CLEAR_ACH1_TXBD_DESA_H(x) | BIT_ACH1_TXBD_DESA_H(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
-
-/* 2 REG_VIQ_TXBD_NUM (Offset 0x0386) */
+/* 2 REG_BEQ_TXBD_DESA (Offset 0x0328) */
-#define BIT_HCI_VIQ_FLAG BIT(14)
+#define BIT_SHIFT_BEQ_TXBD_DESA 0
+#define BIT_MASK_BEQ_TXBD_DESA 0xffffffffffffffffL
+#define BIT_BEQ_TXBD_DESA(x) \
+ (((x) & BIT_MASK_BEQ_TXBD_DESA) << BIT_SHIFT_BEQ_TXBD_DESA)
+#define BITS_BEQ_TXBD_DESA (BIT_MASK_BEQ_TXBD_DESA << BIT_SHIFT_BEQ_TXBD_DESA)
+#define BIT_CLEAR_BEQ_TXBD_DESA(x) ((x) & (~BITS_BEQ_TXBD_DESA))
+#define BIT_GET_BEQ_TXBD_DESA(x) \
+ (((x) >> BIT_SHIFT_BEQ_TXBD_DESA) & BIT_MASK_BEQ_TXBD_DESA)
+#define BIT_SET_BEQ_TXBD_DESA(x, v) \
+ (BIT_CLEAR_BEQ_TXBD_DESA(x) | BIT_BEQ_TXBD_DESA(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_ACH2_TXBD_DESA_L (Offset 0x0328) */
+#define BIT_SHIFT_ACH2_TXBD_DESA_L 0
+#define BIT_MASK_ACH2_TXBD_DESA_L 0xffffffffL
+#define BIT_ACH2_TXBD_DESA_L(x) \
+ (((x) & BIT_MASK_ACH2_TXBD_DESA_L) << BIT_SHIFT_ACH2_TXBD_DESA_L)
+#define BITS_ACH2_TXBD_DESA_L \
+ (BIT_MASK_ACH2_TXBD_DESA_L << BIT_SHIFT_ACH2_TXBD_DESA_L)
+#define BIT_CLEAR_ACH2_TXBD_DESA_L(x) ((x) & (~BITS_ACH2_TXBD_DESA_L))
+#define BIT_GET_ACH2_TXBD_DESA_L(x) \
+ (((x) >> BIT_SHIFT_ACH2_TXBD_DESA_L) & BIT_MASK_ACH2_TXBD_DESA_L)
+#define BIT_SET_ACH2_TXBD_DESA_L(x, v) \
+ (BIT_CLEAR_ACH2_TXBD_DESA_L(x) | BIT_ACH2_TXBD_DESA_L(v))
-/* 2 REG_VIQ_TXBD_NUM (Offset 0x0386) */
+/* 2 REG_ACH2_TXBD_DESA_H (Offset 0x032C) */
+#define BIT_SHIFT_ACH2_TXBD_DESA_H 0
+#define BIT_MASK_ACH2_TXBD_DESA_H 0xffffffffL
+#define BIT_ACH2_TXBD_DESA_H(x) \
+ (((x) & BIT_MASK_ACH2_TXBD_DESA_H) << BIT_SHIFT_ACH2_TXBD_DESA_H)
+#define BITS_ACH2_TXBD_DESA_H \
+ (BIT_MASK_ACH2_TXBD_DESA_H << BIT_SHIFT_ACH2_TXBD_DESA_H)
+#define BIT_CLEAR_ACH2_TXBD_DESA_H(x) ((x) & (~BITS_ACH2_TXBD_DESA_H))
+#define BIT_GET_ACH2_TXBD_DESA_H(x) \
+ (((x) >> BIT_SHIFT_ACH2_TXBD_DESA_H) & BIT_MASK_ACH2_TXBD_DESA_H)
+#define BIT_SET_ACH2_TXBD_DESA_H(x, v) \
+ (BIT_CLEAR_ACH2_TXBD_DESA_H(x) | BIT_ACH2_TXBD_DESA_H(v))
-#define BIT_SHIFT_VIQ_DESC_MODE 12
-#define BIT_MASK_VIQ_DESC_MODE 0x3
-#define BIT_VIQ_DESC_MODE(x) (((x) & BIT_MASK_VIQ_DESC_MODE) << BIT_SHIFT_VIQ_DESC_MODE)
-#define BIT_GET_VIQ_DESC_MODE(x) (((x) >> BIT_SHIFT_VIQ_DESC_MODE) & BIT_MASK_VIQ_DESC_MODE)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_VIQ_DESC_NUM 0
-#define BIT_MASK_VIQ_DESC_NUM 0xfff
-#define BIT_VIQ_DESC_NUM(x) (((x) & BIT_MASK_VIQ_DESC_NUM) << BIT_SHIFT_VIQ_DESC_NUM)
-#define BIT_GET_VIQ_DESC_NUM(x) (((x) >> BIT_SHIFT_VIQ_DESC_NUM) & BIT_MASK_VIQ_DESC_NUM)
+/* 2 REG_BKQ_TXBD_DESA (Offset 0x0330) */
+#define BIT_SHIFT_BKQ_TXBD_DESA 0
+#define BIT_MASK_BKQ_TXBD_DESA 0xffffffffffffffffL
+#define BIT_BKQ_TXBD_DESA(x) \
+ (((x) & BIT_MASK_BKQ_TXBD_DESA) << BIT_SHIFT_BKQ_TXBD_DESA)
+#define BITS_BKQ_TXBD_DESA (BIT_MASK_BKQ_TXBD_DESA << BIT_SHIFT_BKQ_TXBD_DESA)
+#define BIT_CLEAR_BKQ_TXBD_DESA(x) ((x) & (~BITS_BKQ_TXBD_DESA))
+#define BIT_GET_BKQ_TXBD_DESA(x) \
+ (((x) >> BIT_SHIFT_BKQ_TXBD_DESA) & BIT_MASK_BKQ_TXBD_DESA)
+#define BIT_SET_BKQ_TXBD_DESA(x, v) \
+ (BIT_CLEAR_BKQ_TXBD_DESA(x) | BIT_BKQ_TXBD_DESA(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_ACH3_TXBD_DESA_L (Offset 0x0330) */
+#define BIT_SHIFT_ACH3_TXBD_DESA_L 0
+#define BIT_MASK_ACH3_TXBD_DESA_L 0xffffffffL
+#define BIT_ACH3_TXBD_DESA_L(x) \
+ (((x) & BIT_MASK_ACH3_TXBD_DESA_L) << BIT_SHIFT_ACH3_TXBD_DESA_L)
+#define BITS_ACH3_TXBD_DESA_L \
+ (BIT_MASK_ACH3_TXBD_DESA_L << BIT_SHIFT_ACH3_TXBD_DESA_L)
+#define BIT_CLEAR_ACH3_TXBD_DESA_L(x) ((x) & (~BITS_ACH3_TXBD_DESA_L))
+#define BIT_GET_ACH3_TXBD_DESA_L(x) \
+ (((x) >> BIT_SHIFT_ACH3_TXBD_DESA_L) & BIT_MASK_ACH3_TXBD_DESA_L)
+#define BIT_SET_ACH3_TXBD_DESA_L(x, v) \
+ (BIT_CLEAR_ACH3_TXBD_DESA_L(x) | BIT_ACH3_TXBD_DESA_L(v))
-/* 2 REG_BEQ_TXBD_NUM (Offset 0x0388) */
+/* 2 REG_ACH3_TXBD_DESA_H (Offset 0x0334) */
-#define BIT_PCIE_BEQ_FLAG BIT(14)
+#define BIT_SHIFT_ACH3_TXBD_DESA_H 0
+#define BIT_MASK_ACH3_TXBD_DESA_H 0xffffffffL
+#define BIT_ACH3_TXBD_DESA_H(x) \
+ (((x) & BIT_MASK_ACH3_TXBD_DESA_H) << BIT_SHIFT_ACH3_TXBD_DESA_H)
+#define BITS_ACH3_TXBD_DESA_H \
+ (BIT_MASK_ACH3_TXBD_DESA_H << BIT_SHIFT_ACH3_TXBD_DESA_H)
+#define BIT_CLEAR_ACH3_TXBD_DESA_H(x) ((x) & (~BITS_ACH3_TXBD_DESA_H))
+#define BIT_GET_ACH3_TXBD_DESA_H(x) \
+ (((x) >> BIT_SHIFT_ACH3_TXBD_DESA_H) & BIT_MASK_ACH3_TXBD_DESA_H)
+#define BIT_SET_ACH3_TXBD_DESA_H(x, v) \
+ (BIT_CLEAR_ACH3_TXBD_DESA_H(x) | BIT_ACH3_TXBD_DESA_H(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
-
-/* 2 REG_BEQ_TXBD_NUM (Offset 0x0388) */
+/* 2 REG_RXQ_RXBD_DESA (Offset 0x0338) */
-#define BIT_HCI_BEQ_FLAG BIT(14)
+#define BIT_SHIFT_RXQ_RXBD_DESA 0
+#define BIT_MASK_RXQ_RXBD_DESA 0xffffffffffffffffL
+#define BIT_RXQ_RXBD_DESA(x) \
+ (((x) & BIT_MASK_RXQ_RXBD_DESA) << BIT_SHIFT_RXQ_RXBD_DESA)
+#define BITS_RXQ_RXBD_DESA (BIT_MASK_RXQ_RXBD_DESA << BIT_SHIFT_RXQ_RXBD_DESA)
+#define BIT_CLEAR_RXQ_RXBD_DESA(x) ((x) & (~BITS_RXQ_RXBD_DESA))
+#define BIT_GET_RXQ_RXBD_DESA(x) \
+ (((x) >> BIT_SHIFT_RXQ_RXBD_DESA) & BIT_MASK_RXQ_RXBD_DESA)
+#define BIT_SET_RXQ_RXBD_DESA(x, v) \
+ (BIT_CLEAR_RXQ_RXBD_DESA(x) | BIT_RXQ_RXBD_DESA(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_P0RXQ_RXBD_DESA_L (Offset 0x0338) */
+#define BIT_SHIFT_P0RXQ_RXBD_DESA_L 0
+#define BIT_MASK_P0RXQ_RXBD_DESA_L 0xffffffffL
+#define BIT_P0RXQ_RXBD_DESA_L(x) \
+ (((x) & BIT_MASK_P0RXQ_RXBD_DESA_L) << BIT_SHIFT_P0RXQ_RXBD_DESA_L)
+#define BITS_P0RXQ_RXBD_DESA_L \
+ (BIT_MASK_P0RXQ_RXBD_DESA_L << BIT_SHIFT_P0RXQ_RXBD_DESA_L)
+#define BIT_CLEAR_P0RXQ_RXBD_DESA_L(x) ((x) & (~BITS_P0RXQ_RXBD_DESA_L))
+#define BIT_GET_P0RXQ_RXBD_DESA_L(x) \
+ (((x) >> BIT_SHIFT_P0RXQ_RXBD_DESA_L) & BIT_MASK_P0RXQ_RXBD_DESA_L)
+#define BIT_SET_P0RXQ_RXBD_DESA_L(x, v) \
+ (BIT_CLEAR_P0RXQ_RXBD_DESA_L(x) | BIT_P0RXQ_RXBD_DESA_L(v))
-/* 2 REG_BEQ_TXBD_NUM (Offset 0x0388) */
+/* 2 REG_P0RXQ_RXBD_DESA_H (Offset 0x033C) */
+#define BIT_SHIFT_P0RXQ_RXBD_DESA_H 0
+#define BIT_MASK_P0RXQ_RXBD_DESA_H 0xffffffffL
+#define BIT_P0RXQ_RXBD_DESA_H(x) \
+ (((x) & BIT_MASK_P0RXQ_RXBD_DESA_H) << BIT_SHIFT_P0RXQ_RXBD_DESA_H)
+#define BITS_P0RXQ_RXBD_DESA_H \
+ (BIT_MASK_P0RXQ_RXBD_DESA_H << BIT_SHIFT_P0RXQ_RXBD_DESA_H)
+#define BIT_CLEAR_P0RXQ_RXBD_DESA_H(x) ((x) & (~BITS_P0RXQ_RXBD_DESA_H))
+#define BIT_GET_P0RXQ_RXBD_DESA_H(x) \
+ (((x) >> BIT_SHIFT_P0RXQ_RXBD_DESA_H) & BIT_MASK_P0RXQ_RXBD_DESA_H)
+#define BIT_SET_P0RXQ_RXBD_DESA_H(x, v) \
+ (BIT_CLEAR_P0RXQ_RXBD_DESA_H(x) | BIT_P0RXQ_RXBD_DESA_H(v))
-#define BIT_SHIFT_BEQ_DESC_MODE 12
-#define BIT_MASK_BEQ_DESC_MODE 0x3
-#define BIT_BEQ_DESC_MODE(x) (((x) & BIT_MASK_BEQ_DESC_MODE) << BIT_SHIFT_BEQ_DESC_MODE)
-#define BIT_GET_BEQ_DESC_MODE(x) (((x) >> BIT_SHIFT_BEQ_DESC_MODE) & BIT_MASK_BEQ_DESC_MODE)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_BEQ_DESC_NUM 0
-#define BIT_MASK_BEQ_DESC_NUM 0xfff
-#define BIT_BEQ_DESC_NUM(x) (((x) & BIT_MASK_BEQ_DESC_NUM) << BIT_SHIFT_BEQ_DESC_NUM)
-#define BIT_GET_BEQ_DESC_NUM(x) (((x) >> BIT_SHIFT_BEQ_DESC_NUM) & BIT_MASK_BEQ_DESC_NUM)
+/* 2 REG_HI0Q_TXBD_DESA (Offset 0x0340) */
+#define BIT_SHIFT_HI0Q_TXBD_DESA 0
+#define BIT_MASK_HI0Q_TXBD_DESA 0xffffffffffffffffL
+#define BIT_HI0Q_TXBD_DESA(x) \
+ (((x) & BIT_MASK_HI0Q_TXBD_DESA) << BIT_SHIFT_HI0Q_TXBD_DESA)
+#define BITS_HI0Q_TXBD_DESA \
+ (BIT_MASK_HI0Q_TXBD_DESA << BIT_SHIFT_HI0Q_TXBD_DESA)
+#define BIT_CLEAR_HI0Q_TXBD_DESA(x) ((x) & (~BITS_HI0Q_TXBD_DESA))
+#define BIT_GET_HI0Q_TXBD_DESA(x) \
+ (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA) & BIT_MASK_HI0Q_TXBD_DESA)
+#define BIT_SET_HI0Q_TXBD_DESA(x, v) \
+ (BIT_CLEAR_HI0Q_TXBD_DESA(x) | BIT_HI0Q_TXBD_DESA(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_P0BCNQ_TXBD_DESA_L (Offset 0x0340) */
+#define BIT_SHIFT_P0BCNQ_TXBD_DESA_L 0
+#define BIT_MASK_P0BCNQ_TXBD_DESA_L 0xffffffffL
+#define BIT_P0BCNQ_TXBD_DESA_L(x) \
+ (((x) & BIT_MASK_P0BCNQ_TXBD_DESA_L) << BIT_SHIFT_P0BCNQ_TXBD_DESA_L)
+#define BITS_P0BCNQ_TXBD_DESA_L \
+ (BIT_MASK_P0BCNQ_TXBD_DESA_L << BIT_SHIFT_P0BCNQ_TXBD_DESA_L)
+#define BIT_CLEAR_P0BCNQ_TXBD_DESA_L(x) ((x) & (~BITS_P0BCNQ_TXBD_DESA_L))
+#define BIT_GET_P0BCNQ_TXBD_DESA_L(x) \
+ (((x) >> BIT_SHIFT_P0BCNQ_TXBD_DESA_L) & BIT_MASK_P0BCNQ_TXBD_DESA_L)
+#define BIT_SET_P0BCNQ_TXBD_DESA_L(x, v) \
+ (BIT_CLEAR_P0BCNQ_TXBD_DESA_L(x) | BIT_P0BCNQ_TXBD_DESA_L(v))
-/* 2 REG_BKQ_TXBD_NUM (Offset 0x038A) */
+/* 2 REG_P0BCNQ_TXBD_DESA_H (Offset 0x0344) */
-#define BIT_PCIE_BKQ_FLAG BIT(14)
+#define BIT_SHIFT_P0BCNQ_TXBD_DESA_H 0
+#define BIT_MASK_P0BCNQ_TXBD_DESA_H 0xffffffffL
+#define BIT_P0BCNQ_TXBD_DESA_H(x) \
+ (((x) & BIT_MASK_P0BCNQ_TXBD_DESA_H) << BIT_SHIFT_P0BCNQ_TXBD_DESA_H)
+#define BITS_P0BCNQ_TXBD_DESA_H \
+ (BIT_MASK_P0BCNQ_TXBD_DESA_H << BIT_SHIFT_P0BCNQ_TXBD_DESA_H)
+#define BIT_CLEAR_P0BCNQ_TXBD_DESA_H(x) ((x) & (~BITS_P0BCNQ_TXBD_DESA_H))
+#define BIT_GET_P0BCNQ_TXBD_DESA_H(x) \
+ (((x) >> BIT_SHIFT_P0BCNQ_TXBD_DESA_H) & BIT_MASK_P0BCNQ_TXBD_DESA_H)
+#define BIT_SET_P0BCNQ_TXBD_DESA_H(x, v) \
+ (BIT_CLEAR_P0BCNQ_TXBD_DESA_H(x) | BIT_P0BCNQ_TXBD_DESA_H(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
-
-/* 2 REG_BKQ_TXBD_NUM (Offset 0x038A) */
+/* 2 REG_HI1Q_TXBD_DESA (Offset 0x0348) */
-#define BIT_HCI_BKQ_FLAG BIT(14)
+#define BIT_SHIFT_HI1Q_TXBD_DESA 0
+#define BIT_MASK_HI1Q_TXBD_DESA 0xffffffffffffffffL
+#define BIT_HI1Q_TXBD_DESA(x) \
+ (((x) & BIT_MASK_HI1Q_TXBD_DESA) << BIT_SHIFT_HI1Q_TXBD_DESA)
+#define BITS_HI1Q_TXBD_DESA \
+ (BIT_MASK_HI1Q_TXBD_DESA << BIT_SHIFT_HI1Q_TXBD_DESA)
+#define BIT_CLEAR_HI1Q_TXBD_DESA(x) ((x) & (~BITS_HI1Q_TXBD_DESA))
+#define BIT_GET_HI1Q_TXBD_DESA(x) \
+ (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA) & BIT_MASK_HI1Q_TXBD_DESA)
+#define BIT_SET_HI1Q_TXBD_DESA(x, v) \
+ (BIT_CLEAR_HI1Q_TXBD_DESA(x) | BIT_HI1Q_TXBD_DESA(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+/* 2 REG_FWCMDQ_TXBD_DESA_L (Offset 0x0348) */
-/* 2 REG_BKQ_TXBD_NUM (Offset 0x038A) */
+#define BIT_SHIFT_FWCMDQ_TXBD_DESA_L 0
+#define BIT_MASK_FWCMDQ_TXBD_DESA_L 0xffffffffL
+#define BIT_FWCMDQ_TXBD_DESA_L(x) \
+ (((x) & BIT_MASK_FWCMDQ_TXBD_DESA_L) << BIT_SHIFT_FWCMDQ_TXBD_DESA_L)
+#define BITS_FWCMDQ_TXBD_DESA_L \
+ (BIT_MASK_FWCMDQ_TXBD_DESA_L << BIT_SHIFT_FWCMDQ_TXBD_DESA_L)
+#define BIT_CLEAR_FWCMDQ_TXBD_DESA_L(x) ((x) & (~BITS_FWCMDQ_TXBD_DESA_L))
+#define BIT_GET_FWCMDQ_TXBD_DESA_L(x) \
+ (((x) >> BIT_SHIFT_FWCMDQ_TXBD_DESA_L) & BIT_MASK_FWCMDQ_TXBD_DESA_L)
+#define BIT_SET_FWCMDQ_TXBD_DESA_L(x, v) \
+ (BIT_CLEAR_FWCMDQ_TXBD_DESA_L(x) | BIT_FWCMDQ_TXBD_DESA_L(v))
+/* 2 REG_FWCMDQ_TXBD_DESA_H (Offset 0x034C) */
-#define BIT_SHIFT_BKQ_DESC_MODE 12
-#define BIT_MASK_BKQ_DESC_MODE 0x3
-#define BIT_BKQ_DESC_MODE(x) (((x) & BIT_MASK_BKQ_DESC_MODE) << BIT_SHIFT_BKQ_DESC_MODE)
-#define BIT_GET_BKQ_DESC_MODE(x) (((x) >> BIT_SHIFT_BKQ_DESC_MODE) & BIT_MASK_BKQ_DESC_MODE)
+#define BIT_SHIFT_FWCMDQ_TXBD_DESA_H 0
+#define BIT_MASK_FWCMDQ_TXBD_DESA_H 0xffffffffL
+#define BIT_FWCMDQ_TXBD_DESA_H(x) \
+ (((x) & BIT_MASK_FWCMDQ_TXBD_DESA_H) << BIT_SHIFT_FWCMDQ_TXBD_DESA_H)
+#define BITS_FWCMDQ_TXBD_DESA_H \
+ (BIT_MASK_FWCMDQ_TXBD_DESA_H << BIT_SHIFT_FWCMDQ_TXBD_DESA_H)
+#define BIT_CLEAR_FWCMDQ_TXBD_DESA_H(x) ((x) & (~BITS_FWCMDQ_TXBD_DESA_H))
+#define BIT_GET_FWCMDQ_TXBD_DESA_H(x) \
+ (((x) >> BIT_SHIFT_FWCMDQ_TXBD_DESA_H) & BIT_MASK_FWCMDQ_TXBD_DESA_H)
+#define BIT_SET_FWCMDQ_TXBD_DESA_H(x, v) \
+ (BIT_CLEAR_FWCMDQ_TXBD_DESA_H(x) | BIT_FWCMDQ_TXBD_DESA_H(v))
+#endif
-#define BIT_SHIFT_BKQ_DESC_NUM 0
-#define BIT_MASK_BKQ_DESC_NUM 0xfff
-#define BIT_BKQ_DESC_NUM(x) (((x) & BIT_MASK_BKQ_DESC_NUM) << BIT_SHIFT_BKQ_DESC_NUM)
-#define BIT_GET_BKQ_DESC_NUM(x) (((x) >> BIT_SHIFT_BKQ_DESC_NUM) & BIT_MASK_BKQ_DESC_NUM)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_HI2Q_TXBD_DESA (Offset 0x0350) */
-/* 2 REG_HI0Q_TXBD_NUM (Offset 0x038C) */
+#define BIT_SHIFT_HI2Q_TXBD_DESA 0
+#define BIT_MASK_HI2Q_TXBD_DESA 0xffffffffffffffffL
+#define BIT_HI2Q_TXBD_DESA(x) \
+ (((x) & BIT_MASK_HI2Q_TXBD_DESA) << BIT_SHIFT_HI2Q_TXBD_DESA)
+#define BITS_HI2Q_TXBD_DESA \
+ (BIT_MASK_HI2Q_TXBD_DESA << BIT_SHIFT_HI2Q_TXBD_DESA)
+#define BIT_CLEAR_HI2Q_TXBD_DESA(x) ((x) & (~BITS_HI2Q_TXBD_DESA))
+#define BIT_GET_HI2Q_TXBD_DESA(x) \
+ (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA) & BIT_MASK_HI2Q_TXBD_DESA)
+#define BIT_SET_HI2Q_TXBD_DESA(x, v) \
+ (BIT_CLEAR_HI2Q_TXBD_DESA(x) | BIT_HI2Q_TXBD_DESA(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_PCIE_HRPWM1_HCPWM1_DCPU (Offset 0x0354) */
+
+#define BIT_SHIFT_PCIE_HCPWM1_DCPU 16
+#define BIT_MASK_PCIE_HCPWM1_DCPU 0xff
+#define BIT_PCIE_HCPWM1_DCPU(x) \
+ (((x) & BIT_MASK_PCIE_HCPWM1_DCPU) << BIT_SHIFT_PCIE_HCPWM1_DCPU)
+#define BITS_PCIE_HCPWM1_DCPU \
+ (BIT_MASK_PCIE_HCPWM1_DCPU << BIT_SHIFT_PCIE_HCPWM1_DCPU)
+#define BIT_CLEAR_PCIE_HCPWM1_DCPU(x) ((x) & (~BITS_PCIE_HCPWM1_DCPU))
+#define BIT_GET_PCIE_HCPWM1_DCPU(x) \
+ (((x) >> BIT_SHIFT_PCIE_HCPWM1_DCPU) & BIT_MASK_PCIE_HCPWM1_DCPU)
+#define BIT_SET_PCIE_HCPWM1_DCPU(x, v) \
+ (BIT_CLEAR_PCIE_HCPWM1_DCPU(x) | BIT_PCIE_HCPWM1_DCPU(v))
+
+#define BIT_SHIFT_PCIE_HRPWM1_DCPU 8
+#define BIT_MASK_PCIE_HRPWM1_DCPU 0xff
+#define BIT_PCIE_HRPWM1_DCPU(x) \
+ (((x) & BIT_MASK_PCIE_HRPWM1_DCPU) << BIT_SHIFT_PCIE_HRPWM1_DCPU)
+#define BITS_PCIE_HRPWM1_DCPU \
+ (BIT_MASK_PCIE_HRPWM1_DCPU << BIT_SHIFT_PCIE_HRPWM1_DCPU)
+#define BIT_CLEAR_PCIE_HRPWM1_DCPU(x) ((x) & (~BITS_PCIE_HRPWM1_DCPU))
+#define BIT_GET_PCIE_HRPWM1_DCPU(x) \
+ (((x) >> BIT_SHIFT_PCIE_HRPWM1_DCPU) & BIT_MASK_PCIE_HRPWM1_DCPU)
+#define BIT_SET_PCIE_HRPWM1_DCPU(x, v) \
+ (BIT_CLEAR_PCIE_HRPWM1_DCPU(x) | BIT_PCIE_HRPWM1_DCPU(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_HI0Q_FLAG BIT(14)
+/* 2 REG_HI3Q_TXBD_DESA (Offset 0x0358) */
-#define BIT_SHIFT_HI0Q_DESC_MODE 12
-#define BIT_MASK_HI0Q_DESC_MODE 0x3
-#define BIT_HI0Q_DESC_MODE(x) (((x) & BIT_MASK_HI0Q_DESC_MODE) << BIT_SHIFT_HI0Q_DESC_MODE)
-#define BIT_GET_HI0Q_DESC_MODE(x) (((x) >> BIT_SHIFT_HI0Q_DESC_MODE) & BIT_MASK_HI0Q_DESC_MODE)
+#define BIT_SHIFT_HI3Q_TXBD_DESA 0
+#define BIT_MASK_HI3Q_TXBD_DESA 0xffffffffffffffffL
+#define BIT_HI3Q_TXBD_DESA(x) \
+ (((x) & BIT_MASK_HI3Q_TXBD_DESA) << BIT_SHIFT_HI3Q_TXBD_DESA)
+#define BITS_HI3Q_TXBD_DESA \
+ (BIT_MASK_HI3Q_TXBD_DESA << BIT_SHIFT_HI3Q_TXBD_DESA)
+#define BIT_CLEAR_HI3Q_TXBD_DESA(x) ((x) & (~BITS_HI3Q_TXBD_DESA))
+#define BIT_GET_HI3Q_TXBD_DESA(x) \
+ (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA) & BIT_MASK_HI3Q_TXBD_DESA)
+#define BIT_SET_HI3Q_TXBD_DESA(x, v) \
+ (BIT_CLEAR_HI3Q_TXBD_DESA(x) | BIT_HI3Q_TXBD_DESA(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0_MPRT_BCNQ_TXBD_DESA_L (Offset 0x0358) */
+
+#define BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L 0
+#define BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L 0xffffffffL
+#define BIT_P0_MPRT_BCNQ_TXBD_DESA_L(x) \
+ (((x) & BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L) \
+ << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L)
+#define BITS_P0_MPRT_BCNQ_TXBD_DESA_L \
+ (BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L \
+ << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L)
+#define BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_L(x) \
+ ((x) & (~BITS_P0_MPRT_BCNQ_TXBD_DESA_L))
+#define BIT_GET_P0_MPRT_BCNQ_TXBD_DESA_L(x) \
+ (((x) >> BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L) & \
+ BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L)
+#define BIT_SET_P0_MPRT_BCNQ_TXBD_DESA_L(x, v) \
+ (BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_L(x) | \
+ BIT_P0_MPRT_BCNQ_TXBD_DESA_L(v))
+
+/* 2 REG_P0_MPRT_BCNQ_TXBD_DESA_H (Offset 0x035C) */
+
+#define BIT_CLR_P0HI15Q_HW_IDX BIT(29)
+#define BIT_CLR_P0HI14Q_HW_IDX BIT(28)
+#define BIT_CLR_P0HI13Q_HW_IDX BIT(27)
+#define BIT_CLR_P0HI12Q_HW_IDX BIT(26)
+#define BIT_CLR_P0HI11Q_HW_IDX BIT(25)
+#define BIT_CLR_P0HI10Q_HW_IDX BIT(24)
+#define BIT_CLR_P0HI9Q_HW_IDX BIT(23)
+#define BIT_CLR_P0HI8Q_HW_IDX BIT(22)
+#define BIT_CLR_ACH7_HW_IDX BIT(21)
+#define BIT_CLR_ACH13_HW_IDX BIT(21)
+#define BIT_CLR_ACH6_HW_IDX BIT(20)
+#define BIT_CLR_ACH12_HW_IDX BIT(20)
+#define BIT_CLR_ACH5_HW_IDX BIT(19)
+#define BIT_CLR_ACH11_HW_IDX BIT(19)
+#define BIT_CLR_ACH4_HW_IDX BIT(18)
+#define BIT_CLR_ACH10_HW_IDX BIT(18)
+#define BIT_CLR_ACH9_HW_IDX BIT(17)
+#define BIT_CLR_ACH8_HW_IDX BIT(16)
+
+#define BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE 13
+#define BIT_MASK_P0_MPRT_BCNQ_DESC_MODE 0x3
+#define BIT_P0_MPRT_BCNQ_DESC_MODE(x) \
+ (((x) & BIT_MASK_P0_MPRT_BCNQ_DESC_MODE) \
+ << BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE)
+#define BITS_P0_MPRT_BCNQ_DESC_MODE \
+ (BIT_MASK_P0_MPRT_BCNQ_DESC_MODE << BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE)
+#define BIT_CLEAR_P0_MPRT_BCNQ_DESC_MODE(x) \
+ ((x) & (~BITS_P0_MPRT_BCNQ_DESC_MODE))
+#define BIT_GET_P0_MPRT_BCNQ_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE) & \
+ BIT_MASK_P0_MPRT_BCNQ_DESC_MODE)
+#define BIT_SET_P0_MPRT_BCNQ_DESC_MODE(x, v) \
+ (BIT_CLEAR_P0_MPRT_BCNQ_DESC_MODE(x) | BIT_P0_MPRT_BCNQ_DESC_MODE(v))
+
+#define BIT_CLR_P0HI15Q_HOST_IDX BIT(13)
+#define BIT_CLR_P0HI14Q_HOST_IDX BIT(12)
+#define BIT_PCIE_P0MPRT_BCNQ4_FLAG BIT(11)
+#define BIT_CLR_P0HI13Q_HOST_IDX BIT(11)
+#define BIT_PCIE_P0MPRT_BCNQ3_FLAG BIT(10)
+#define BIT_CLR_P0HI12Q_HOST_IDX BIT(10)
+#define BIT_PCIE_P0MPRT_BCNQ2_FLAG BIT(9)
+#define BIT_CLR_P0HI11Q_HOST_IDX BIT(9)
+#define BIT_PCIE_P0MPRT_BCNQ1_FLAG BIT(8)
+#define BIT_CLR_P0HI10Q_HOST_IDX BIT(8)
+#define BIT_CLR_P0HI9Q_HOST_IDX BIT(7)
+#define BIT_CLR_P0HI8Q_HOST_IDX BIT(6)
+#define BIT_CLR_ACH7_HOST_IDX BIT(5)
+#define BIT_CLR_ACH13_HOST_IDX BIT(5)
+#define BIT_CLR_ACH6_HOST_IDX BIT(4)
+#define BIT_CLR_ACH12_HOST_IDX BIT(4)
+#define BIT_CLR_ACH5_HOST_IDX BIT(3)
+#define BIT_CLR_ACH11_HOST_IDX BIT(3)
+#define BIT_CLR_ACH4_HOST_IDX BIT(2)
+#define BIT_CLR_ACH10_HOST_IDX BIT(2)
+#define BIT_EPHY_CAL_DONE BIT(1)
+#define BIT_CLR_ACH9_HOST_IDX BIT(1)
+
+#define BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H 0
+#define BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H 0xffffffffL
+#define BIT_P0_MPRT_BCNQ_TXBD_DESA_H(x) \
+ (((x) & BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H) \
+ << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H)
+#define BITS_P0_MPRT_BCNQ_TXBD_DESA_H \
+ (BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H \
+ << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H)
+#define BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_H(x) \
+ ((x) & (~BITS_P0_MPRT_BCNQ_TXBD_DESA_H))
+#define BIT_GET_P0_MPRT_BCNQ_TXBD_DESA_H(x) \
+ (((x) >> BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H) & \
+ BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H)
+#define BIT_SET_P0_MPRT_BCNQ_TXBD_DESA_H(x, v) \
+ (BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_H(x) | \
+ BIT_P0_MPRT_BCNQ_TXBD_DESA_H(v))
+
+#define BIT_RESET_APHY BIT(0)
+#define BIT_CLR_ACH8_HOST_IDX BIT(0)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_HI4Q_TXBD_DESA (Offset 0x0360) */
-#define BIT_SHIFT_HI0Q_DESC_NUM 0
-#define BIT_MASK_HI0Q_DESC_NUM 0xfff
-#define BIT_HI0Q_DESC_NUM(x) (((x) & BIT_MASK_HI0Q_DESC_NUM) << BIT_SHIFT_HI0Q_DESC_NUM)
-#define BIT_GET_HI0Q_DESC_NUM(x) (((x) >> BIT_SHIFT_HI0Q_DESC_NUM) & BIT_MASK_HI0Q_DESC_NUM)
+#define BIT_SHIFT_HI4Q_TXBD_DESA 0
+#define BIT_MASK_HI4Q_TXBD_DESA 0xffffffffffffffffL
+#define BIT_HI4Q_TXBD_DESA(x) \
+ (((x) & BIT_MASK_HI4Q_TXBD_DESA) << BIT_SHIFT_HI4Q_TXBD_DESA)
+#define BITS_HI4Q_TXBD_DESA \
+ (BIT_MASK_HI4Q_TXBD_DESA << BIT_SHIFT_HI4Q_TXBD_DESA)
+#define BIT_CLEAR_HI4Q_TXBD_DESA(x) ((x) & (~BITS_HI4Q_TXBD_DESA))
+#define BIT_GET_HI4Q_TXBD_DESA(x) \
+ (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA) & BIT_MASK_HI4Q_TXBD_DESA)
+#define BIT_SET_HI4Q_TXBD_DESA(x, v) \
+ (BIT_CLEAR_HI4Q_TXBD_DESA(x) | BIT_HI4Q_TXBD_DESA(v))
+/* 2 REG_HI5Q_TXBD_DESA (Offset 0x0368) */
-/* 2 REG_HI1Q_TXBD_NUM (Offset 0x038E) */
+#define BIT_SHIFT_HI5Q_TXBD_DESA 0
+#define BIT_MASK_HI5Q_TXBD_DESA 0xffffffffffffffffL
+#define BIT_HI5Q_TXBD_DESA(x) \
+ (((x) & BIT_MASK_HI5Q_TXBD_DESA) << BIT_SHIFT_HI5Q_TXBD_DESA)
+#define BITS_HI5Q_TXBD_DESA \
+ (BIT_MASK_HI5Q_TXBD_DESA << BIT_SHIFT_HI5Q_TXBD_DESA)
+#define BIT_CLEAR_HI5Q_TXBD_DESA(x) ((x) & (~BITS_HI5Q_TXBD_DESA))
+#define BIT_GET_HI5Q_TXBD_DESA(x) \
+ (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA) & BIT_MASK_HI5Q_TXBD_DESA)
+#define BIT_SET_HI5Q_TXBD_DESA(x, v) \
+ (BIT_CLEAR_HI5Q_TXBD_DESA(x) | BIT_HI5Q_TXBD_DESA(v))
-#define BIT_HI1Q_FLAG BIT(14)
+/* 2 REG_HI6Q_TXBD_DESA (Offset 0x0370) */
-#define BIT_SHIFT_HI1Q_DESC_MODE 12
-#define BIT_MASK_HI1Q_DESC_MODE 0x3
-#define BIT_HI1Q_DESC_MODE(x) (((x) & BIT_MASK_HI1Q_DESC_MODE) << BIT_SHIFT_HI1Q_DESC_MODE)
-#define BIT_GET_HI1Q_DESC_MODE(x) (((x) >> BIT_SHIFT_HI1Q_DESC_MODE) & BIT_MASK_HI1Q_DESC_MODE)
+#define BIT_SHIFT_HI6Q_TXBD_DESA 0
+#define BIT_MASK_HI6Q_TXBD_DESA 0xffffffffffffffffL
+#define BIT_HI6Q_TXBD_DESA(x) \
+ (((x) & BIT_MASK_HI6Q_TXBD_DESA) << BIT_SHIFT_HI6Q_TXBD_DESA)
+#define BITS_HI6Q_TXBD_DESA \
+ (BIT_MASK_HI6Q_TXBD_DESA << BIT_SHIFT_HI6Q_TXBD_DESA)
+#define BIT_CLEAR_HI6Q_TXBD_DESA(x) ((x) & (~BITS_HI6Q_TXBD_DESA))
+#define BIT_GET_HI6Q_TXBD_DESA(x) \
+ (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA) & BIT_MASK_HI6Q_TXBD_DESA)
+#define BIT_SET_HI6Q_TXBD_DESA(x, v) \
+ (BIT_CLEAR_HI6Q_TXBD_DESA(x) | BIT_HI6Q_TXBD_DESA(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0MGQ_RXQ_TXRXBD_NUM (Offset 0x0378) */
+
+#define BIT_SYS_32_64_V1 BIT(31)
+
+#define BIT_SHIFT_P0BCNQ_DESC_MODE 29
+#define BIT_MASK_P0BCNQ_DESC_MODE 0x3
+#define BIT_P0BCNQ_DESC_MODE(x) \
+ (((x) & BIT_MASK_P0BCNQ_DESC_MODE) << BIT_SHIFT_P0BCNQ_DESC_MODE)
+#define BITS_P0BCNQ_DESC_MODE \
+ (BIT_MASK_P0BCNQ_DESC_MODE << BIT_SHIFT_P0BCNQ_DESC_MODE)
+#define BIT_CLEAR_P0BCNQ_DESC_MODE(x) ((x) & (~BITS_P0BCNQ_DESC_MODE))
+#define BIT_GET_P0BCNQ_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_P0BCNQ_DESC_MODE) & BIT_MASK_P0BCNQ_DESC_MODE)
+#define BIT_SET_P0BCNQ_DESC_MODE(x, v) \
+ (BIT_CLEAR_P0BCNQ_DESC_MODE(x) | BIT_P0BCNQ_DESC_MODE(v))
+
+#define BIT_PCIE_P0BCNQ_FLAG BIT(28)
+
+#define BIT_SHIFT_P0RXQ_DESC_NUM 16
+#define BIT_MASK_P0RXQ_DESC_NUM 0xfff
+#define BIT_P0RXQ_DESC_NUM(x) \
+ (((x) & BIT_MASK_P0RXQ_DESC_NUM) << BIT_SHIFT_P0RXQ_DESC_NUM)
+#define BITS_P0RXQ_DESC_NUM \
+ (BIT_MASK_P0RXQ_DESC_NUM << BIT_SHIFT_P0RXQ_DESC_NUM)
+#define BIT_CLEAR_P0RXQ_DESC_NUM(x) ((x) & (~BITS_P0RXQ_DESC_NUM))
+#define BIT_GET_P0RXQ_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_P0RXQ_DESC_NUM) & BIT_MASK_P0RXQ_DESC_NUM)
+#define BIT_SET_P0RXQ_DESC_NUM(x, v) \
+ (BIT_CLEAR_P0RXQ_DESC_NUM(x) | BIT_P0RXQ_DESC_NUM(v))
+
+#define BIT_PCIE_P0MGQ_FLAG BIT(14)
+
+#define BIT_SHIFT_P0MGQ_DESC_MODE 12
+#define BIT_MASK_P0MGQ_DESC_MODE 0x3
+#define BIT_P0MGQ_DESC_MODE(x) \
+ (((x) & BIT_MASK_P0MGQ_DESC_MODE) << BIT_SHIFT_P0MGQ_DESC_MODE)
+#define BITS_P0MGQ_DESC_MODE \
+ (BIT_MASK_P0MGQ_DESC_MODE << BIT_SHIFT_P0MGQ_DESC_MODE)
+#define BIT_CLEAR_P0MGQ_DESC_MODE(x) ((x) & (~BITS_P0MGQ_DESC_MODE))
+#define BIT_GET_P0MGQ_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_P0MGQ_DESC_MODE) & BIT_MASK_P0MGQ_DESC_MODE)
+#define BIT_SET_P0MGQ_DESC_MODE(x, v) \
+ (BIT_CLEAR_P0MGQ_DESC_MODE(x) | BIT_P0MGQ_DESC_MODE(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_HI7Q_TXBD_DESA (Offset 0x0378) */
-#define BIT_SHIFT_HI1Q_DESC_NUM 0
-#define BIT_MASK_HI1Q_DESC_NUM 0xfff
-#define BIT_HI1Q_DESC_NUM(x) (((x) & BIT_MASK_HI1Q_DESC_NUM) << BIT_SHIFT_HI1Q_DESC_NUM)
-#define BIT_GET_HI1Q_DESC_NUM(x) (((x) >> BIT_SHIFT_HI1Q_DESC_NUM) & BIT_MASK_HI1Q_DESC_NUM)
+#define BIT_SHIFT_HI7Q_TXBD_DESA 0
+#define BIT_MASK_HI7Q_TXBD_DESA 0xffffffffffffffffL
+#define BIT_HI7Q_TXBD_DESA(x) \
+ (((x) & BIT_MASK_HI7Q_TXBD_DESA) << BIT_SHIFT_HI7Q_TXBD_DESA)
+#define BITS_HI7Q_TXBD_DESA \
+ (BIT_MASK_HI7Q_TXBD_DESA << BIT_SHIFT_HI7Q_TXBD_DESA)
+#define BIT_CLEAR_HI7Q_TXBD_DESA(x) ((x) & (~BITS_HI7Q_TXBD_DESA))
+#define BIT_GET_HI7Q_TXBD_DESA(x) \
+ (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA) & BIT_MASK_HI7Q_TXBD_DESA)
+#define BIT_SET_HI7Q_TXBD_DESA(x, v) \
+ (BIT_CLEAR_HI7Q_TXBD_DESA(x) | BIT_HI7Q_TXBD_DESA(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0MGQ_RXQ_TXRXBD_NUM (Offset 0x0378) */
+
+#define BIT_SHIFT_P0MGQ_DESC_NUM 0
+#define BIT_MASK_P0MGQ_DESC_NUM 0xfff
+#define BIT_P0MGQ_DESC_NUM(x) \
+ (((x) & BIT_MASK_P0MGQ_DESC_NUM) << BIT_SHIFT_P0MGQ_DESC_NUM)
+#define BITS_P0MGQ_DESC_NUM \
+ (BIT_MASK_P0MGQ_DESC_NUM << BIT_SHIFT_P0MGQ_DESC_NUM)
+#define BIT_CLEAR_P0MGQ_DESC_NUM(x) ((x) & (~BITS_P0MGQ_DESC_NUM))
+#define BIT_GET_P0MGQ_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_P0MGQ_DESC_NUM) & BIT_MASK_P0MGQ_DESC_NUM)
+#define BIT_SET_P0MGQ_DESC_NUM(x, v) \
+ (BIT_CLEAR_P0MGQ_DESC_NUM(x) | BIT_P0MGQ_DESC_NUM(v))
+
+/* 2 REG_CHNL_DMA_CFG (Offset 0x037C) */
+
+#define BIT_TXHCI_EN BIT(26)
+#define BIT_TXHCI_IDLE BIT(25)
+#define BIT_DMA_PRI_EN BIT(24)
+#define BIT_PCIE_FWCMDQ_FLAG BIT(14)
+
+#define BIT_SHIFT_FWCMDQ_DESC_MODE 12
+#define BIT_MASK_FWCMDQ_DESC_MODE 0x3
+#define BIT_FWCMDQ_DESC_MODE(x) \
+ (((x) & BIT_MASK_FWCMDQ_DESC_MODE) << BIT_SHIFT_FWCMDQ_DESC_MODE)
+#define BITS_FWCMDQ_DESC_MODE \
+ (BIT_MASK_FWCMDQ_DESC_MODE << BIT_SHIFT_FWCMDQ_DESC_MODE)
+#define BIT_CLEAR_FWCMDQ_DESC_MODE(x) ((x) & (~BITS_FWCMDQ_DESC_MODE))
+#define BIT_GET_FWCMDQ_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_FWCMDQ_DESC_MODE) & BIT_MASK_FWCMDQ_DESC_MODE)
+#define BIT_SET_FWCMDQ_DESC_MODE(x, v) \
+ (BIT_CLEAR_FWCMDQ_DESC_MODE(x) | BIT_FWCMDQ_DESC_MODE(v))
+
+#define BIT_SHIFT_FWCMDQ_DESC_NUM 0
+#define BIT_MASK_FWCMDQ_DESC_NUM 0xfff
+#define BIT_FWCMDQ_DESC_NUM(x) \
+ (((x) & BIT_MASK_FWCMDQ_DESC_NUM) << BIT_SHIFT_FWCMDQ_DESC_NUM)
+#define BITS_FWCMDQ_DESC_NUM \
+ (BIT_MASK_FWCMDQ_DESC_NUM << BIT_SHIFT_FWCMDQ_DESC_NUM)
+#define BIT_CLEAR_FWCMDQ_DESC_NUM(x) ((x) & (~BITS_FWCMDQ_DESC_NUM))
+#define BIT_GET_FWCMDQ_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_FWCMDQ_DESC_NUM) & BIT_MASK_FWCMDQ_DESC_NUM)
+#define BIT_SET_FWCMDQ_DESC_NUM(x, v) \
+ (BIT_CLEAR_FWCMDQ_DESC_NUM(x) | BIT_FWCMDQ_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+/* 2 REG_MGQ_TXBD_NUM (Offset 0x0380) */
-/* 2 REG_HI2Q_TXBD_NUM (Offset 0x0390) */
+#define BIT_PCIE_MGQ_FLAG BIT(14)
-#define BIT_HI2Q_FLAG BIT(14)
+#endif
-#define BIT_SHIFT_HI2Q_DESC_MODE 12
-#define BIT_MASK_HI2Q_DESC_MODE 0x3
-#define BIT_HI2Q_DESC_MODE(x) (((x) & BIT_MASK_HI2Q_DESC_MODE) << BIT_SHIFT_HI2Q_DESC_MODE)
-#define BIT_GET_HI2Q_DESC_MODE(x) (((x) >> BIT_SHIFT_HI2Q_DESC_MODE) & BIT_MASK_HI2Q_DESC_MODE)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+/* 2 REG_MGQ_TXBD_NUM (Offset 0x0380) */
-#define BIT_SHIFT_HI2Q_DESC_NUM 0
-#define BIT_MASK_HI2Q_DESC_NUM 0xfff
-#define BIT_HI2Q_DESC_NUM(x) (((x) & BIT_MASK_HI2Q_DESC_NUM) << BIT_SHIFT_HI2Q_DESC_NUM)
-#define BIT_GET_HI2Q_DESC_NUM(x) (((x) >> BIT_SHIFT_HI2Q_DESC_NUM) & BIT_MASK_HI2Q_DESC_NUM)
+#define BIT_HCI_MGQ_FLAG BIT(14)
+#endif
-/* 2 REG_HI3Q_TXBD_NUM (Offset 0x0392) */
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_HI3Q_FLAG BIT(14)
+/* 2 REG_MGQ_TXBD_NUM (Offset 0x0380) */
-#define BIT_SHIFT_HI3Q_DESC_MODE 12
-#define BIT_MASK_HI3Q_DESC_MODE 0x3
-#define BIT_HI3Q_DESC_MODE(x) (((x) & BIT_MASK_HI3Q_DESC_MODE) << BIT_SHIFT_HI3Q_DESC_MODE)
-#define BIT_GET_HI3Q_DESC_MODE(x) (((x) >> BIT_SHIFT_HI3Q_DESC_MODE) & BIT_MASK_HI3Q_DESC_MODE)
+#define BIT_SHIFT_MGQ_DESC_MODE 12
+#define BIT_MASK_MGQ_DESC_MODE 0x3
+#define BIT_MGQ_DESC_MODE(x) \
+ (((x) & BIT_MASK_MGQ_DESC_MODE) << BIT_SHIFT_MGQ_DESC_MODE)
+#define BITS_MGQ_DESC_MODE (BIT_MASK_MGQ_DESC_MODE << BIT_SHIFT_MGQ_DESC_MODE)
+#define BIT_CLEAR_MGQ_DESC_MODE(x) ((x) & (~BITS_MGQ_DESC_MODE))
+#define BIT_GET_MGQ_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_MGQ_DESC_MODE) & BIT_MASK_MGQ_DESC_MODE)
+#define BIT_SET_MGQ_DESC_MODE(x, v) \
+ (BIT_CLEAR_MGQ_DESC_MODE(x) | BIT_MGQ_DESC_MODE(v))
+
+#define BIT_SHIFT_MGQ_DESC_NUM 0
+#define BIT_MASK_MGQ_DESC_NUM 0xfff
+#define BIT_MGQ_DESC_NUM(x) \
+ (((x) & BIT_MASK_MGQ_DESC_NUM) << BIT_SHIFT_MGQ_DESC_NUM)
+#define BITS_MGQ_DESC_NUM (BIT_MASK_MGQ_DESC_NUM << BIT_SHIFT_MGQ_DESC_NUM)
+#define BIT_CLEAR_MGQ_DESC_NUM(x) ((x) & (~BITS_MGQ_DESC_NUM))
+#define BIT_GET_MGQ_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_MGQ_DESC_NUM) & BIT_MASK_MGQ_DESC_NUM)
+#define BIT_SET_MGQ_DESC_NUM(x, v) \
+ (BIT_CLEAR_MGQ_DESC_NUM(x) | BIT_MGQ_DESC_NUM(v))
+/* 2 REG_RX_RXBD_NUM (Offset 0x0382) */
-#define BIT_SHIFT_HI3Q_DESC_NUM 0
-#define BIT_MASK_HI3Q_DESC_NUM 0xfff
-#define BIT_HI3Q_DESC_NUM(x) (((x) & BIT_MASK_HI3Q_DESC_NUM) << BIT_SHIFT_HI3Q_DESC_NUM)
-#define BIT_GET_HI3Q_DESC_NUM(x) (((x) >> BIT_SHIFT_HI3Q_DESC_NUM) & BIT_MASK_HI3Q_DESC_NUM)
+#define BIT_SYS_32_64 BIT(15)
+#define BIT_SHIFT_BCNQ_DESC_MODE 13
+#define BIT_MASK_BCNQ_DESC_MODE 0x3
+#define BIT_BCNQ_DESC_MODE(x) \
+ (((x) & BIT_MASK_BCNQ_DESC_MODE) << BIT_SHIFT_BCNQ_DESC_MODE)
+#define BITS_BCNQ_DESC_MODE \
+ (BIT_MASK_BCNQ_DESC_MODE << BIT_SHIFT_BCNQ_DESC_MODE)
+#define BIT_CLEAR_BCNQ_DESC_MODE(x) ((x) & (~BITS_BCNQ_DESC_MODE))
+#define BIT_GET_BCNQ_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_BCNQ_DESC_MODE) & BIT_MASK_BCNQ_DESC_MODE)
+#define BIT_SET_BCNQ_DESC_MODE(x, v) \
+ (BIT_CLEAR_BCNQ_DESC_MODE(x) | BIT_BCNQ_DESC_MODE(v))
-/* 2 REG_HI4Q_TXBD_NUM (Offset 0x0394) */
+#endif
-#define BIT_HI4Q_FLAG BIT(14)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_HI4Q_DESC_MODE 12
-#define BIT_MASK_HI4Q_DESC_MODE 0x3
-#define BIT_HI4Q_DESC_MODE(x) (((x) & BIT_MASK_HI4Q_DESC_MODE) << BIT_SHIFT_HI4Q_DESC_MODE)
-#define BIT_GET_HI4Q_DESC_MODE(x) (((x) >> BIT_SHIFT_HI4Q_DESC_MODE) & BIT_MASK_HI4Q_DESC_MODE)
+/* 2 REG_RX_RXBD_NUM (Offset 0x0382) */
+#define BIT_PCIE_BCNQ_FLAG BIT(12)
-#define BIT_SHIFT_HI4Q_DESC_NUM 0
-#define BIT_MASK_HI4Q_DESC_NUM 0xfff
-#define BIT_HI4Q_DESC_NUM(x) (((x) & BIT_MASK_HI4Q_DESC_NUM) << BIT_SHIFT_HI4Q_DESC_NUM)
-#define BIT_GET_HI4Q_DESC_NUM(x) (((x) >> BIT_SHIFT_HI4Q_DESC_NUM) & BIT_MASK_HI4Q_DESC_NUM)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-/* 2 REG_HI5Q_TXBD_NUM (Offset 0x0396) */
+/* 2 REG_RX_RXBD_NUM (Offset 0x0382) */
-#define BIT_HI5Q_FLAG BIT(14)
+#define BIT_HCI_BCNQ_FLAG BIT(12)
-#define BIT_SHIFT_HI5Q_DESC_MODE 12
-#define BIT_MASK_HI5Q_DESC_MODE 0x3
-#define BIT_HI5Q_DESC_MODE(x) (((x) & BIT_MASK_HI5Q_DESC_MODE) << BIT_SHIFT_HI5Q_DESC_MODE)
-#define BIT_GET_HI5Q_DESC_MODE(x) (((x) >> BIT_SHIFT_HI5Q_DESC_MODE) & BIT_MASK_HI5Q_DESC_MODE)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_HI5Q_DESC_NUM 0
-#define BIT_MASK_HI5Q_DESC_NUM 0xfff
-#define BIT_HI5Q_DESC_NUM(x) (((x) & BIT_MASK_HI5Q_DESC_NUM) << BIT_SHIFT_HI5Q_DESC_NUM)
-#define BIT_GET_HI5Q_DESC_NUM(x) (((x) >> BIT_SHIFT_HI5Q_DESC_NUM) & BIT_MASK_HI5Q_DESC_NUM)
+/* 2 REG_RX_RXBD_NUM (Offset 0x0382) */
+#define BIT_SHIFT_RXQ_DESC_NUM 0
+#define BIT_MASK_RXQ_DESC_NUM 0xfff
+#define BIT_RXQ_DESC_NUM(x) \
+ (((x) & BIT_MASK_RXQ_DESC_NUM) << BIT_SHIFT_RXQ_DESC_NUM)
+#define BITS_RXQ_DESC_NUM (BIT_MASK_RXQ_DESC_NUM << BIT_SHIFT_RXQ_DESC_NUM)
+#define BIT_CLEAR_RXQ_DESC_NUM(x) ((x) & (~BITS_RXQ_DESC_NUM))
+#define BIT_GET_RXQ_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_RXQ_DESC_NUM) & BIT_MASK_RXQ_DESC_NUM)
+#define BIT_SET_RXQ_DESC_NUM(x, v) \
+ (BIT_CLEAR_RXQ_DESC_NUM(x) | BIT_RXQ_DESC_NUM(v))
-/* 2 REG_HI6Q_TXBD_NUM (Offset 0x0398) */
+#endif
-#define BIT_HI6Q_FLAG BIT(14)
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_HI6Q_DESC_MODE 12
-#define BIT_MASK_HI6Q_DESC_MODE 0x3
-#define BIT_HI6Q_DESC_MODE(x) (((x) & BIT_MASK_HI6Q_DESC_MODE) << BIT_SHIFT_HI6Q_DESC_MODE)
-#define BIT_GET_HI6Q_DESC_MODE(x) (((x) >> BIT_SHIFT_HI6Q_DESC_MODE) & BIT_MASK_HI6Q_DESC_MODE)
+/* 2 REG_ACH0_ACH1_TXBD_NUM (Offset 0x0384) */
+#define BIT_PCIE_ACH1_FLAG_V1 BIT(30)
-#define BIT_SHIFT_HI6Q_DESC_NUM 0
-#define BIT_MASK_HI6Q_DESC_NUM 0xfff
-#define BIT_HI6Q_DESC_NUM(x) (((x) & BIT_MASK_HI6Q_DESC_NUM) << BIT_SHIFT_HI6Q_DESC_NUM)
-#define BIT_GET_HI6Q_DESC_NUM(x) (((x) >> BIT_SHIFT_HI6Q_DESC_NUM) & BIT_MASK_HI6Q_DESC_NUM)
+#define BIT_SHIFT_ACH1_DESC_MODE_V1 28
+#define BIT_MASK_ACH1_DESC_MODE_V1 0x3
+#define BIT_ACH1_DESC_MODE_V1(x) \
+ (((x) & BIT_MASK_ACH1_DESC_MODE_V1) << BIT_SHIFT_ACH1_DESC_MODE_V1)
+#define BITS_ACH1_DESC_MODE_V1 \
+ (BIT_MASK_ACH1_DESC_MODE_V1 << BIT_SHIFT_ACH1_DESC_MODE_V1)
+#define BIT_CLEAR_ACH1_DESC_MODE_V1(x) ((x) & (~BITS_ACH1_DESC_MODE_V1))
+#define BIT_GET_ACH1_DESC_MODE_V1(x) \
+ (((x) >> BIT_SHIFT_ACH1_DESC_MODE_V1) & BIT_MASK_ACH1_DESC_MODE_V1)
+#define BIT_SET_ACH1_DESC_MODE_V1(x, v) \
+ (BIT_CLEAR_ACH1_DESC_MODE_V1(x) | BIT_ACH1_DESC_MODE_V1(v))
+#define BIT_SHIFT_ACH1_DESC_NUM_V1 16
+#define BIT_MASK_ACH1_DESC_NUM_V1 0xfff
+#define BIT_ACH1_DESC_NUM_V1(x) \
+ (((x) & BIT_MASK_ACH1_DESC_NUM_V1) << BIT_SHIFT_ACH1_DESC_NUM_V1)
+#define BITS_ACH1_DESC_NUM_V1 \
+ (BIT_MASK_ACH1_DESC_NUM_V1 << BIT_SHIFT_ACH1_DESC_NUM_V1)
+#define BIT_CLEAR_ACH1_DESC_NUM_V1(x) ((x) & (~BITS_ACH1_DESC_NUM_V1))
+#define BIT_GET_ACH1_DESC_NUM_V1(x) \
+ (((x) >> BIT_SHIFT_ACH1_DESC_NUM_V1) & BIT_MASK_ACH1_DESC_NUM_V1)
+#define BIT_SET_ACH1_DESC_NUM_V1(x, v) \
+ (BIT_CLEAR_ACH1_DESC_NUM_V1(x) | BIT_ACH1_DESC_NUM_V1(v))
-/* 2 REG_HI7Q_TXBD_NUM (Offset 0x039A) */
+#endif
-#define BIT_HI7Q_FLAG BIT(14)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_HI7Q_DESC_MODE 12
-#define BIT_MASK_HI7Q_DESC_MODE 0x3
-#define BIT_HI7Q_DESC_MODE(x) (((x) & BIT_MASK_HI7Q_DESC_MODE) << BIT_SHIFT_HI7Q_DESC_MODE)
-#define BIT_GET_HI7Q_DESC_MODE(x) (((x) >> BIT_SHIFT_HI7Q_DESC_MODE) & BIT_MASK_HI7Q_DESC_MODE)
+/* 2 REG_VOQ_TXBD_NUM (Offset 0x0384) */
+#define BIT_PCIE_VOQ_FLAG BIT(14)
-#define BIT_SHIFT_HI7Q_DESC_NUM 0
-#define BIT_MASK_HI7Q_DESC_NUM 0xfff
-#define BIT_HI7Q_DESC_NUM(x) (((x) & BIT_MASK_HI7Q_DESC_NUM) << BIT_SHIFT_HI7Q_DESC_NUM)
-#define BIT_GET_HI7Q_DESC_NUM(x) (((x) >> BIT_SHIFT_HI7Q_DESC_NUM) & BIT_MASK_HI7Q_DESC_NUM)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+/* 2 REG_VOQ_TXBD_NUM (Offset 0x0384) */
-#define BIT_CLR_HI7Q_HW_IDX BIT(29)
-#define BIT_CLR_HI6Q_HW_IDX BIT(28)
-#define BIT_CLR_HI5Q_HW_IDX BIT(27)
-#define BIT_CLR_HI4Q_HW_IDX BIT(26)
-#define BIT_CLR_HI3Q_HW_IDX BIT(25)
-#define BIT_CLR_HI2Q_HW_IDX BIT(24)
-#define BIT_CLR_HI1Q_HW_IDX BIT(23)
+#define BIT_HCI_VOQ_FLAG BIT(14)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8881A_SUPPORT)
-
-
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+/* 2 REG_ACH0_ACH1_TXBD_NUM (Offset 0x0384) */
-#define BIT_BCN7DOK BIT(23)
-#define BIT_BCN7DOKM BIT(23)
+#define BIT_PCIE_ACH0_FLAG BIT(14)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_VOQ_TXBD_NUM (Offset 0x0384) */
+#define BIT_SHIFT_VOQ_DESC_MODE 12
+#define BIT_MASK_VOQ_DESC_MODE 0x3
+#define BIT_VOQ_DESC_MODE(x) \
+ (((x) & BIT_MASK_VOQ_DESC_MODE) << BIT_SHIFT_VOQ_DESC_MODE)
+#define BITS_VOQ_DESC_MODE (BIT_MASK_VOQ_DESC_MODE << BIT_SHIFT_VOQ_DESC_MODE)
+#define BIT_CLEAR_VOQ_DESC_MODE(x) ((x) & (~BITS_VOQ_DESC_MODE))
+#define BIT_GET_VOQ_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_VOQ_DESC_MODE) & BIT_MASK_VOQ_DESC_MODE)
+#define BIT_SET_VOQ_DESC_MODE(x, v) \
+ (BIT_CLEAR_VOQ_DESC_MODE(x) | BIT_VOQ_DESC_MODE(v))
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+#endif
-#define BIT_CLR_HI0Q_HW_IDX BIT(22)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_ACH0_ACH1_TXBD_NUM (Offset 0x0384) */
+#define BIT_SHIFT_ACH0_DESC_MODE 12
+#define BIT_MASK_ACH0_DESC_MODE 0x3
+#define BIT_ACH0_DESC_MODE(x) \
+ (((x) & BIT_MASK_ACH0_DESC_MODE) << BIT_SHIFT_ACH0_DESC_MODE)
+#define BITS_ACH0_DESC_MODE \
+ (BIT_MASK_ACH0_DESC_MODE << BIT_SHIFT_ACH0_DESC_MODE)
+#define BIT_CLEAR_ACH0_DESC_MODE(x) ((x) & (~BITS_ACH0_DESC_MODE))
+#define BIT_GET_ACH0_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_ACH0_DESC_MODE) & BIT_MASK_ACH0_DESC_MODE)
+#define BIT_SET_ACH0_DESC_MODE(x, v) \
+ (BIT_CLEAR_ACH0_DESC_MODE(x) | BIT_ACH0_DESC_MODE(v))
-#if (HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+/* 2 REG_VOQ_TXBD_NUM (Offset 0x0384) */
-#define BIT_BCN6DOK BIT(22)
-#define BIT_BCN6DOKM BIT(22)
+#define BIT_SHIFT_VOQ_DESC_NUM 0
+#define BIT_MASK_VOQ_DESC_NUM 0xfff
+#define BIT_VOQ_DESC_NUM(x) \
+ (((x) & BIT_MASK_VOQ_DESC_NUM) << BIT_SHIFT_VOQ_DESC_NUM)
+#define BITS_VOQ_DESC_NUM (BIT_MASK_VOQ_DESC_NUM << BIT_SHIFT_VOQ_DESC_NUM)
+#define BIT_CLEAR_VOQ_DESC_NUM(x) ((x) & (~BITS_VOQ_DESC_NUM))
+#define BIT_GET_VOQ_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_VOQ_DESC_NUM) & BIT_MASK_VOQ_DESC_NUM)
+#define BIT_SET_VOQ_DESC_NUM(x, v) \
+ (BIT_CLEAR_VOQ_DESC_NUM(x) | BIT_VOQ_DESC_NUM(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_ACH0_ACH1_TXBD_NUM (Offset 0x0384) */
+#define BIT_SHIFT_ACH0_DESC_NUM 0
+#define BIT_MASK_ACH0_DESC_NUM 0xfff
+#define BIT_ACH0_DESC_NUM(x) \
+ (((x) & BIT_MASK_ACH0_DESC_NUM) << BIT_SHIFT_ACH0_DESC_NUM)
+#define BITS_ACH0_DESC_NUM (BIT_MASK_ACH0_DESC_NUM << BIT_SHIFT_ACH0_DESC_NUM)
+#define BIT_CLEAR_ACH0_DESC_NUM(x) ((x) & (~BITS_ACH0_DESC_NUM))
+#define BIT_GET_ACH0_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_ACH0_DESC_NUM) & BIT_MASK_ACH0_DESC_NUM)
+#define BIT_SET_ACH0_DESC_NUM(x, v) \
+ (BIT_CLEAR_ACH0_DESC_NUM(x) | BIT_ACH0_DESC_NUM(v))
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+#endif
-#define BIT_CLR_BKQ_HW_IDX BIT(21)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_VIQ_TXBD_NUM (Offset 0x0386) */
+#define BIT_PCIE_VIQ_FLAG BIT(14)
-#if (HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+/* 2 REG_VIQ_TXBD_NUM (Offset 0x0386) */
-#define BIT_BCN5DOK BIT(21)
-#define BIT_BCN5DOKM BIT(21)
+#define BIT_HCI_VIQ_FLAG BIT(14)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_VIQ_TXBD_NUM (Offset 0x0386) */
+#define BIT_SHIFT_VIQ_DESC_MODE 12
+#define BIT_MASK_VIQ_DESC_MODE 0x3
+#define BIT_VIQ_DESC_MODE(x) \
+ (((x) & BIT_MASK_VIQ_DESC_MODE) << BIT_SHIFT_VIQ_DESC_MODE)
+#define BITS_VIQ_DESC_MODE (BIT_MASK_VIQ_DESC_MODE << BIT_SHIFT_VIQ_DESC_MODE)
+#define BIT_CLEAR_VIQ_DESC_MODE(x) ((x) & (~BITS_VIQ_DESC_MODE))
+#define BIT_GET_VIQ_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_VIQ_DESC_MODE) & BIT_MASK_VIQ_DESC_MODE)
+#define BIT_SET_VIQ_DESC_MODE(x, v) \
+ (BIT_CLEAR_VIQ_DESC_MODE(x) | BIT_VIQ_DESC_MODE(v))
+
+#define BIT_SHIFT_VIQ_DESC_NUM 0
+#define BIT_MASK_VIQ_DESC_NUM 0xfff
+#define BIT_VIQ_DESC_NUM(x) \
+ (((x) & BIT_MASK_VIQ_DESC_NUM) << BIT_SHIFT_VIQ_DESC_NUM)
+#define BITS_VIQ_DESC_NUM (BIT_MASK_VIQ_DESC_NUM << BIT_SHIFT_VIQ_DESC_NUM)
+#define BIT_CLEAR_VIQ_DESC_NUM(x) ((x) & (~BITS_VIQ_DESC_NUM))
+#define BIT_GET_VIQ_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_VIQ_DESC_NUM) & BIT_MASK_VIQ_DESC_NUM)
+#define BIT_SET_VIQ_DESC_NUM(x, v) \
+ (BIT_CLEAR_VIQ_DESC_NUM(x) | BIT_VIQ_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH2_ACH3_TXBD_NUM (Offset 0x0388) */
+
+#define BIT_PCIE_ACH3_FLAG_V1 BIT(30)
+
+#define BIT_SHIFT_ACH3_DESC_MODE_V1 28
+#define BIT_MASK_ACH3_DESC_MODE_V1 0x3
+#define BIT_ACH3_DESC_MODE_V1(x) \
+ (((x) & BIT_MASK_ACH3_DESC_MODE_V1) << BIT_SHIFT_ACH3_DESC_MODE_V1)
+#define BITS_ACH3_DESC_MODE_V1 \
+ (BIT_MASK_ACH3_DESC_MODE_V1 << BIT_SHIFT_ACH3_DESC_MODE_V1)
+#define BIT_CLEAR_ACH3_DESC_MODE_V1(x) ((x) & (~BITS_ACH3_DESC_MODE_V1))
+#define BIT_GET_ACH3_DESC_MODE_V1(x) \
+ (((x) >> BIT_SHIFT_ACH3_DESC_MODE_V1) & BIT_MASK_ACH3_DESC_MODE_V1)
+#define BIT_SET_ACH3_DESC_MODE_V1(x, v) \
+ (BIT_CLEAR_ACH3_DESC_MODE_V1(x) | BIT_ACH3_DESC_MODE_V1(v))
+
+#define BIT_SHIFT_ACH3_DESC_NUM_V1 16
+#define BIT_MASK_ACH3_DESC_NUM_V1 0xfff
+#define BIT_ACH3_DESC_NUM_V1(x) \
+ (((x) & BIT_MASK_ACH3_DESC_NUM_V1) << BIT_SHIFT_ACH3_DESC_NUM_V1)
+#define BITS_ACH3_DESC_NUM_V1 \
+ (BIT_MASK_ACH3_DESC_NUM_V1 << BIT_SHIFT_ACH3_DESC_NUM_V1)
+#define BIT_CLEAR_ACH3_DESC_NUM_V1(x) ((x) & (~BITS_ACH3_DESC_NUM_V1))
+#define BIT_GET_ACH3_DESC_NUM_V1(x) \
+ (((x) >> BIT_SHIFT_ACH3_DESC_NUM_V1) & BIT_MASK_ACH3_DESC_NUM_V1)
+#define BIT_SET_ACH3_DESC_NUM_V1(x, v) \
+ (BIT_CLEAR_ACH3_DESC_NUM_V1(x) | BIT_ACH3_DESC_NUM_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+/* 2 REG_BEQ_TXBD_NUM (Offset 0x0388) */
-#define BIT_CLR_BEQ_HW_IDX BIT(20)
+#define BIT_PCIE_BEQ_FLAG BIT(14)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8881A_SUPPORT)
+/* 2 REG_BEQ_TXBD_NUM (Offset 0x0388) */
+#define BIT_HCI_BEQ_FLAG BIT(14)
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+#endif
-#define BIT_BCN4DOK BIT(20)
-#define BIT_BCN4DOKM BIT(20)
-#define BIT_RX_OVER_RD_ERR BIT(20)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_ACH2_ACH3_TXBD_NUM (Offset 0x0388) */
+#define BIT_PCIE_ACH2_FLAG BIT(14)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+/* 2 REG_BEQ_TXBD_NUM (Offset 0x0388) */
-#define BIT_CLR_VIQ_HW_IDX BIT(19)
+#define BIT_SHIFT_BEQ_DESC_MODE 12
+#define BIT_MASK_BEQ_DESC_MODE 0x3
+#define BIT_BEQ_DESC_MODE(x) \
+ (((x) & BIT_MASK_BEQ_DESC_MODE) << BIT_SHIFT_BEQ_DESC_MODE)
+#define BITS_BEQ_DESC_MODE (BIT_MASK_BEQ_DESC_MODE << BIT_SHIFT_BEQ_DESC_MODE)
+#define BIT_CLEAR_BEQ_DESC_MODE(x) ((x) & (~BITS_BEQ_DESC_MODE))
+#define BIT_GET_BEQ_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_BEQ_DESC_MODE) & BIT_MASK_BEQ_DESC_MODE)
+#define BIT_SET_BEQ_DESC_MODE(x, v) \
+ (BIT_CLEAR_BEQ_DESC_MODE(x) | BIT_BEQ_DESC_MODE(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8881A_SUPPORT)
+/* 2 REG_ACH2_ACH3_TXBD_NUM (Offset 0x0388) */
+#define BIT_SHIFT_ACH2_DESC_MODE 12
+#define BIT_MASK_ACH2_DESC_MODE 0x3
+#define BIT_ACH2_DESC_MODE(x) \
+ (((x) & BIT_MASK_ACH2_DESC_MODE) << BIT_SHIFT_ACH2_DESC_MODE)
+#define BITS_ACH2_DESC_MODE \
+ (BIT_MASK_ACH2_DESC_MODE << BIT_SHIFT_ACH2_DESC_MODE)
+#define BIT_CLEAR_ACH2_DESC_MODE(x) ((x) & (~BITS_ACH2_DESC_MODE))
+#define BIT_GET_ACH2_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_ACH2_DESC_MODE) & BIT_MASK_ACH2_DESC_MODE)
+#define BIT_SET_ACH2_DESC_MODE(x, v) \
+ (BIT_CLEAR_ACH2_DESC_MODE(x) | BIT_ACH2_DESC_MODE(v))
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+#endif
-#define BIT_BCN3DOK BIT(19)
-#define BIT_BCN3DOKM BIT(19)
-#define BIT_RXDMA_STUCK BIT(19)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_BEQ_TXBD_NUM (Offset 0x0388) */
+#define BIT_SHIFT_BEQ_DESC_NUM 0
+#define BIT_MASK_BEQ_DESC_NUM 0xfff
+#define BIT_BEQ_DESC_NUM(x) \
+ (((x) & BIT_MASK_BEQ_DESC_NUM) << BIT_SHIFT_BEQ_DESC_NUM)
+#define BITS_BEQ_DESC_NUM (BIT_MASK_BEQ_DESC_NUM << BIT_SHIFT_BEQ_DESC_NUM)
+#define BIT_CLEAR_BEQ_DESC_NUM(x) ((x) & (~BITS_BEQ_DESC_NUM))
+#define BIT_GET_BEQ_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_BEQ_DESC_NUM) & BIT_MASK_BEQ_DESC_NUM)
+#define BIT_SET_BEQ_DESC_NUM(x, v) \
+ (BIT_CLEAR_BEQ_DESC_NUM(x) | BIT_BEQ_DESC_NUM(v))
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+/* 2 REG_ACH2_ACH3_TXBD_NUM (Offset 0x0388) */
-#define BIT_CLR_VOQ_HW_IDX BIT(18)
+#define BIT_SHIFT_ACH2_DESC_NUM 0
+#define BIT_MASK_ACH2_DESC_NUM 0xfff
+#define BIT_ACH2_DESC_NUM(x) \
+ (((x) & BIT_MASK_ACH2_DESC_NUM) << BIT_SHIFT_ACH2_DESC_NUM)
+#define BITS_ACH2_DESC_NUM (BIT_MASK_ACH2_DESC_NUM << BIT_SHIFT_ACH2_DESC_NUM)
+#define BIT_CLEAR_ACH2_DESC_NUM(x) ((x) & (~BITS_ACH2_DESC_NUM))
+#define BIT_GET_ACH2_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_ACH2_DESC_NUM) & BIT_MASK_ACH2_DESC_NUM)
+#define BIT_SET_ACH2_DESC_NUM(x, v) \
+ (BIT_CLEAR_ACH2_DESC_NUM(x) | BIT_ACH2_DESC_NUM(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8881A_SUPPORT)
+/* 2 REG_BKQ_TXBD_NUM (Offset 0x038A) */
+#define BIT_PCIE_BKQ_FLAG BIT(14)
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+#endif
-#define BIT_BCN2DOK BIT(18)
-#define BIT_BCN2DOKM BIT(18)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#endif
+/* 2 REG_BKQ_TXBD_NUM (Offset 0x038A) */
+#define BIT_HCI_BKQ_FLAG BIT(14)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+/* 2 REG_BKQ_TXBD_NUM (Offset 0x038A) */
-#define BIT_CLR_MGQ_HW_IDX BIT(17)
+#define BIT_SHIFT_BKQ_DESC_MODE 12
+#define BIT_MASK_BKQ_DESC_MODE 0x3
+#define BIT_BKQ_DESC_MODE(x) \
+ (((x) & BIT_MASK_BKQ_DESC_MODE) << BIT_SHIFT_BKQ_DESC_MODE)
+#define BITS_BKQ_DESC_MODE (BIT_MASK_BKQ_DESC_MODE << BIT_SHIFT_BKQ_DESC_MODE)
+#define BIT_CLEAR_BKQ_DESC_MODE(x) ((x) & (~BITS_BKQ_DESC_MODE))
+#define BIT_GET_BKQ_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_BKQ_DESC_MODE) & BIT_MASK_BKQ_DESC_MODE)
+#define BIT_SET_BKQ_DESC_MODE(x, v) \
+ (BIT_CLEAR_BKQ_DESC_MODE(x) | BIT_BKQ_DESC_MODE(v))
+
+#define BIT_SHIFT_BKQ_DESC_NUM 0
+#define BIT_MASK_BKQ_DESC_NUM 0xfff
+#define BIT_BKQ_DESC_NUM(x) \
+ (((x) & BIT_MASK_BKQ_DESC_NUM) << BIT_SHIFT_BKQ_DESC_NUM)
+#define BITS_BKQ_DESC_NUM (BIT_MASK_BKQ_DESC_NUM << BIT_SHIFT_BKQ_DESC_NUM)
+#define BIT_CLEAR_BKQ_DESC_NUM(x) ((x) & (~BITS_BKQ_DESC_NUM))
+#define BIT_GET_BKQ_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_BKQ_DESC_NUM) & BIT_MASK_BKQ_DESC_NUM)
+#define BIT_SET_BKQ_DESC_NUM(x, v) \
+ (BIT_CLEAR_BKQ_DESC_NUM(x) | BIT_BKQ_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI0Q_HI1Q_TXBD_NUM (Offset 0x038C) */
+
+#define BIT_P0HI1Q_FLAG BIT(30)
+
+#define BIT_SHIFT_P0HI1Q_DESC_MODE 28
+#define BIT_MASK_P0HI1Q_DESC_MODE 0x3
+#define BIT_P0HI1Q_DESC_MODE(x) \
+ (((x) & BIT_MASK_P0HI1Q_DESC_MODE) << BIT_SHIFT_P0HI1Q_DESC_MODE)
+#define BITS_P0HI1Q_DESC_MODE \
+ (BIT_MASK_P0HI1Q_DESC_MODE << BIT_SHIFT_P0HI1Q_DESC_MODE)
+#define BIT_CLEAR_P0HI1Q_DESC_MODE(x) ((x) & (~BITS_P0HI1Q_DESC_MODE))
+#define BIT_GET_P0HI1Q_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_P0HI1Q_DESC_MODE) & BIT_MASK_P0HI1Q_DESC_MODE)
+#define BIT_SET_P0HI1Q_DESC_MODE(x, v) \
+ (BIT_CLEAR_P0HI1Q_DESC_MODE(x) | BIT_P0HI1Q_DESC_MODE(v))
+
+#define BIT_SHIFT_P0HI1Q_DESC_NUM 16
+#define BIT_MASK_P0HI1Q_DESC_NUM 0xfff
+#define BIT_P0HI1Q_DESC_NUM(x) \
+ (((x) & BIT_MASK_P0HI1Q_DESC_NUM) << BIT_SHIFT_P0HI1Q_DESC_NUM)
+#define BITS_P0HI1Q_DESC_NUM \
+ (BIT_MASK_P0HI1Q_DESC_NUM << BIT_SHIFT_P0HI1Q_DESC_NUM)
+#define BIT_CLEAR_P0HI1Q_DESC_NUM(x) ((x) & (~BITS_P0HI1Q_DESC_NUM))
+#define BIT_GET_P0HI1Q_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_P0HI1Q_DESC_NUM) & BIT_MASK_P0HI1Q_DESC_NUM)
+#define BIT_SET_P0HI1Q_DESC_NUM(x, v) \
+ (BIT_CLEAR_P0HI1Q_DESC_NUM(x) | BIT_P0HI1Q_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_HI0Q_TXBD_NUM (Offset 0x038C) */
+#define BIT_HI0Q_FLAG BIT(14)
-#if (HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+/* 2 REG_P0HI0Q_HI1Q_TXBD_NUM (Offset 0x038C) */
-#define BIT_BCN1DOK BIT(17)
-#define BIT_BCN1DOKM BIT(17)
+#define BIT_P0HI0Q_FLAG BIT(14)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_HI0Q_TXBD_NUM (Offset 0x038C) */
+#define BIT_SHIFT_HI0Q_DESC_MODE 12
+#define BIT_MASK_HI0Q_DESC_MODE 0x3
+#define BIT_HI0Q_DESC_MODE(x) \
+ (((x) & BIT_MASK_HI0Q_DESC_MODE) << BIT_SHIFT_HI0Q_DESC_MODE)
+#define BITS_HI0Q_DESC_MODE \
+ (BIT_MASK_HI0Q_DESC_MODE << BIT_SHIFT_HI0Q_DESC_MODE)
+#define BIT_CLEAR_HI0Q_DESC_MODE(x) ((x) & (~BITS_HI0Q_DESC_MODE))
+#define BIT_GET_HI0Q_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_HI0Q_DESC_MODE) & BIT_MASK_HI0Q_DESC_MODE)
+#define BIT_SET_HI0Q_DESC_MODE(x, v) \
+ (BIT_CLEAR_HI0Q_DESC_MODE(x) | BIT_HI0Q_DESC_MODE(v))
-/* 2 REG_TSFTIMER_HCI (Offset 0x039C) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_TSFT2_HCI 16
-#define BIT_MASK_TSFT2_HCI 0xffff
-#define BIT_TSFT2_HCI(x) (((x) & BIT_MASK_TSFT2_HCI) << BIT_SHIFT_TSFT2_HCI)
-#define BIT_GET_TSFT2_HCI(x) (((x) >> BIT_SHIFT_TSFT2_HCI) & BIT_MASK_TSFT2_HCI)
+/* 2 REG_P0HI0Q_HI1Q_TXBD_NUM (Offset 0x038C) */
-#define BIT_CLR_RXQ_HW_IDX BIT(16)
+#define BIT_SHIFT_P0HI0Q_DESC_MODE 12
+#define BIT_MASK_P0HI0Q_DESC_MODE 0x3
+#define BIT_P0HI0Q_DESC_MODE(x) \
+ (((x) & BIT_MASK_P0HI0Q_DESC_MODE) << BIT_SHIFT_P0HI0Q_DESC_MODE)
+#define BITS_P0HI0Q_DESC_MODE \
+ (BIT_MASK_P0HI0Q_DESC_MODE << BIT_SHIFT_P0HI0Q_DESC_MODE)
+#define BIT_CLEAR_P0HI0Q_DESC_MODE(x) ((x) & (~BITS_P0HI0Q_DESC_MODE))
+#define BIT_GET_P0HI0Q_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_P0HI0Q_DESC_MODE) & BIT_MASK_P0HI0Q_DESC_MODE)
+#define BIT_SET_P0HI0Q_DESC_MODE(x, v) \
+ (BIT_CLEAR_P0HI0Q_DESC_MODE(x) | BIT_P0HI0Q_DESC_MODE(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8881A_SUPPORT)
+/* 2 REG_HI0Q_TXBD_NUM (Offset 0x038C) */
+#define BIT_SHIFT_HI0Q_DESC_NUM 0
+#define BIT_MASK_HI0Q_DESC_NUM 0xfff
+#define BIT_HI0Q_DESC_NUM(x) \
+ (((x) & BIT_MASK_HI0Q_DESC_NUM) << BIT_SHIFT_HI0Q_DESC_NUM)
+#define BITS_HI0Q_DESC_NUM (BIT_MASK_HI0Q_DESC_NUM << BIT_SHIFT_HI0Q_DESC_NUM)
+#define BIT_CLEAR_HI0Q_DESC_NUM(x) ((x) & (~BITS_HI0Q_DESC_NUM))
+#define BIT_GET_HI0Q_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_HI0Q_DESC_NUM) & BIT_MASK_HI0Q_DESC_NUM)
+#define BIT_SET_HI0Q_DESC_NUM(x, v) \
+ (BIT_CLEAR_HI0Q_DESC_NUM(x) | BIT_HI0Q_DESC_NUM(v))
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+#endif
-#define BIT_BCN0DOK BIT(16)
-#define BIT_BCN0DOKM BIT(16)
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_RX_STATE 16
-#define BIT_MASK_RX_STATE 0x7
-#define BIT_RX_STATE(x) (((x) & BIT_MASK_RX_STATE) << BIT_SHIFT_RX_STATE)
-#define BIT_GET_RX_STATE(x) (((x) >> BIT_SHIFT_RX_STATE) & BIT_MASK_RX_STATE)
+/* 2 REG_P0HI0Q_HI1Q_TXBD_NUM (Offset 0x038C) */
-#define BIT_SRST_TX BIT(15)
-#define BIT_M7DOK BIT(15)
-#define BIT_M7DOKM BIT(15)
-#define BIT_TDE_NO_IDLE BIT(15)
-#define BIT_SRST_RX BIT(14)
-#define BIT_M6DOK BIT(14)
-#define BIT_M6DOKM BIT(14)
-#define BIT_TXDMA_STUCK BIT(14)
+#define BIT_SHIFT_P0HI0Q_DESC_NUM 0
+#define BIT_MASK_P0HI0Q_DESC_NUM 0xfff
+#define BIT_P0HI0Q_DESC_NUM(x) \
+ (((x) & BIT_MASK_P0HI0Q_DESC_NUM) << BIT_SHIFT_P0HI0Q_DESC_NUM)
+#define BITS_P0HI0Q_DESC_NUM \
+ (BIT_MASK_P0HI0Q_DESC_NUM << BIT_SHIFT_P0HI0Q_DESC_NUM)
+#define BIT_CLEAR_P0HI0Q_DESC_NUM(x) ((x) & (~BITS_P0HI0Q_DESC_NUM))
+#define BIT_GET_P0HI0Q_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_P0HI0Q_DESC_NUM) & BIT_MASK_P0HI0Q_DESC_NUM)
+#define BIT_SET_P0HI0Q_DESC_NUM(x, v) \
+ (BIT_CLEAR_P0HI0Q_DESC_NUM(x) | BIT_P0HI0Q_DESC_NUM(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_HI1Q_TXBD_NUM (Offset 0x038E) */
+#define BIT_HI1Q_FLAG BIT(14)
+
+#define BIT_SHIFT_HI1Q_DESC_MODE 12
+#define BIT_MASK_HI1Q_DESC_MODE 0x3
+#define BIT_HI1Q_DESC_MODE(x) \
+ (((x) & BIT_MASK_HI1Q_DESC_MODE) << BIT_SHIFT_HI1Q_DESC_MODE)
+#define BITS_HI1Q_DESC_MODE \
+ (BIT_MASK_HI1Q_DESC_MODE << BIT_SHIFT_HI1Q_DESC_MODE)
+#define BIT_CLEAR_HI1Q_DESC_MODE(x) ((x) & (~BITS_HI1Q_DESC_MODE))
+#define BIT_GET_HI1Q_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_HI1Q_DESC_MODE) & BIT_MASK_HI1Q_DESC_MODE)
+#define BIT_SET_HI1Q_DESC_MODE(x, v) \
+ (BIT_CLEAR_HI1Q_DESC_MODE(x) | BIT_HI1Q_DESC_MODE(v))
+
+#define BIT_SHIFT_HI1Q_DESC_NUM 0
+#define BIT_MASK_HI1Q_DESC_NUM 0xfff
+#define BIT_HI1Q_DESC_NUM(x) \
+ (((x) & BIT_MASK_HI1Q_DESC_NUM) << BIT_SHIFT_HI1Q_DESC_NUM)
+#define BITS_HI1Q_DESC_NUM (BIT_MASK_HI1Q_DESC_NUM << BIT_SHIFT_HI1Q_DESC_NUM)
+#define BIT_CLEAR_HI1Q_DESC_NUM(x) ((x) & (~BITS_HI1Q_DESC_NUM))
+#define BIT_GET_HI1Q_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_HI1Q_DESC_NUM) & BIT_MASK_HI1Q_DESC_NUM)
+#define BIT_SET_HI1Q_DESC_NUM(x, v) \
+ (BIT_CLEAR_HI1Q_DESC_NUM(x) | BIT_HI1Q_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI2Q_HI3Q_TXBD_NUM (Offset 0x0390) */
+
+#define BIT_P0HI3Q_FLAG BIT(30)
+
+#define BIT_SHIFT_P0HI3Q_DESC_MODE 28
+#define BIT_MASK_P0HI3Q_DESC_MODE 0x3
+#define BIT_P0HI3Q_DESC_MODE(x) \
+ (((x) & BIT_MASK_P0HI3Q_DESC_MODE) << BIT_SHIFT_P0HI3Q_DESC_MODE)
+#define BITS_P0HI3Q_DESC_MODE \
+ (BIT_MASK_P0HI3Q_DESC_MODE << BIT_SHIFT_P0HI3Q_DESC_MODE)
+#define BIT_CLEAR_P0HI3Q_DESC_MODE(x) ((x) & (~BITS_P0HI3Q_DESC_MODE))
+#define BIT_GET_P0HI3Q_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_P0HI3Q_DESC_MODE) & BIT_MASK_P0HI3Q_DESC_MODE)
+#define BIT_SET_P0HI3Q_DESC_MODE(x, v) \
+ (BIT_CLEAR_P0HI3Q_DESC_MODE(x) | BIT_P0HI3Q_DESC_MODE(v))
+
+#define BIT_SHIFT_P0HI3Q_DESC_NUM 16
+#define BIT_MASK_P0HI3Q_DESC_NUM 0xfff
+#define BIT_P0HI3Q_DESC_NUM(x) \
+ (((x) & BIT_MASK_P0HI3Q_DESC_NUM) << BIT_SHIFT_P0HI3Q_DESC_NUM)
+#define BITS_P0HI3Q_DESC_NUM \
+ (BIT_MASK_P0HI3Q_DESC_NUM << BIT_SHIFT_P0HI3Q_DESC_NUM)
+#define BIT_CLEAR_P0HI3Q_DESC_NUM(x) ((x) & (~BITS_P0HI3Q_DESC_NUM))
+#define BIT_GET_P0HI3Q_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_P0HI3Q_DESC_NUM) & BIT_MASK_P0HI3Q_DESC_NUM)
+#define BIT_SET_P0HI3Q_DESC_NUM(x, v) \
+ (BIT_CLEAR_P0HI3Q_DESC_NUM(x) | BIT_P0HI3Q_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+/* 2 REG_HI2Q_TXBD_NUM (Offset 0x0390) */
-#define BIT_CLR_HI7Q_HOST_IDX BIT(13)
+#define BIT_HI2Q_FLAG BIT(14)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8881A_SUPPORT)
+/* 2 REG_P0HI2Q_HI3Q_TXBD_NUM (Offset 0x0390) */
+#define BIT_P0HI2Q_FLAG BIT(14)
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI2Q_TXBD_NUM (Offset 0x0390) */
-#define BIT_M5DOK BIT(13)
-#define BIT_M5DOKM BIT(13)
-#define BIT_TDE_FULL_ERR BIT(13)
+#define BIT_SHIFT_HI2Q_DESC_MODE 12
+#define BIT_MASK_HI2Q_DESC_MODE 0x3
+#define BIT_HI2Q_DESC_MODE(x) \
+ (((x) & BIT_MASK_HI2Q_DESC_MODE) << BIT_SHIFT_HI2Q_DESC_MODE)
+#define BITS_HI2Q_DESC_MODE \
+ (BIT_MASK_HI2Q_DESC_MODE << BIT_SHIFT_HI2Q_DESC_MODE)
+#define BIT_CLEAR_HI2Q_DESC_MODE(x) ((x) & (~BITS_HI2Q_DESC_MODE))
+#define BIT_GET_HI2Q_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_HI2Q_DESC_MODE) & BIT_MASK_HI2Q_DESC_MODE)
+#define BIT_SET_HI2Q_DESC_MODE(x, v) \
+ (BIT_CLEAR_HI2Q_DESC_MODE(x) | BIT_HI2Q_DESC_MODE(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_P0HI2Q_HI3Q_TXBD_NUM (Offset 0x0390) */
+#define BIT_SHIFT_P0HI2Q_DESC_MODE 12
+#define BIT_MASK_P0HI2Q_DESC_MODE 0x3
+#define BIT_P0HI2Q_DESC_MODE(x) \
+ (((x) & BIT_MASK_P0HI2Q_DESC_MODE) << BIT_SHIFT_P0HI2Q_DESC_MODE)
+#define BITS_P0HI2Q_DESC_MODE \
+ (BIT_MASK_P0HI2Q_DESC_MODE << BIT_SHIFT_P0HI2Q_DESC_MODE)
+#define BIT_CLEAR_P0HI2Q_DESC_MODE(x) ((x) & (~BITS_P0HI2Q_DESC_MODE))
+#define BIT_GET_P0HI2Q_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_P0HI2Q_DESC_MODE) & BIT_MASK_P0HI2Q_DESC_MODE)
+#define BIT_SET_P0HI2Q_DESC_MODE(x, v) \
+ (BIT_CLEAR_P0HI2Q_DESC_MODE(x) | BIT_P0HI2Q_DESC_MODE(v))
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+#endif
-#define BIT_CLR_HI6Q_HOST_IDX BIT(12)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_HI2Q_TXBD_NUM (Offset 0x0390) */
+#define BIT_SHIFT_HI2Q_DESC_NUM 0
+#define BIT_MASK_HI2Q_DESC_NUM 0xfff
+#define BIT_HI2Q_DESC_NUM(x) \
+ (((x) & BIT_MASK_HI2Q_DESC_NUM) << BIT_SHIFT_HI2Q_DESC_NUM)
+#define BITS_HI2Q_DESC_NUM (BIT_MASK_HI2Q_DESC_NUM << BIT_SHIFT_HI2Q_DESC_NUM)
+#define BIT_CLEAR_HI2Q_DESC_NUM(x) ((x) & (~BITS_HI2Q_DESC_NUM))
+#define BIT_GET_HI2Q_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_HI2Q_DESC_NUM) & BIT_MASK_HI2Q_DESC_NUM)
+#define BIT_SET_HI2Q_DESC_NUM(x, v) \
+ (BIT_CLEAR_HI2Q_DESC_NUM(x) | BIT_HI2Q_DESC_NUM(v))
-#if (HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+/* 2 REG_P0HI2Q_HI3Q_TXBD_NUM (Offset 0x0390) */
-#define BIT_M4DOK BIT(12)
-#define BIT_M4DOKM BIT(12)
-#define BIT_HD_SIZE_ERR BIT(12)
+#define BIT_SHIFT_P0HI2Q_DESC_NUM 0
+#define BIT_MASK_P0HI2Q_DESC_NUM 0xfff
+#define BIT_P0HI2Q_DESC_NUM(x) \
+ (((x) & BIT_MASK_P0HI2Q_DESC_NUM) << BIT_SHIFT_P0HI2Q_DESC_NUM)
+#define BITS_P0HI2Q_DESC_NUM \
+ (BIT_MASK_P0HI2Q_DESC_NUM << BIT_SHIFT_P0HI2Q_DESC_NUM)
+#define BIT_CLEAR_P0HI2Q_DESC_NUM(x) ((x) & (~BITS_P0HI2Q_DESC_NUM))
+#define BIT_GET_P0HI2Q_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_P0HI2Q_DESC_NUM) & BIT_MASK_P0HI2Q_DESC_NUM)
+#define BIT_SET_P0HI2Q_DESC_NUM(x, v) \
+ (BIT_CLEAR_P0HI2Q_DESC_NUM(x) | BIT_P0HI2Q_DESC_NUM(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_HI3Q_TXBD_NUM (Offset 0x0392) */
+#define BIT_HI3Q_FLAG BIT(14)
+
+#define BIT_SHIFT_HI3Q_DESC_MODE 12
+#define BIT_MASK_HI3Q_DESC_MODE 0x3
+#define BIT_HI3Q_DESC_MODE(x) \
+ (((x) & BIT_MASK_HI3Q_DESC_MODE) << BIT_SHIFT_HI3Q_DESC_MODE)
+#define BITS_HI3Q_DESC_MODE \
+ (BIT_MASK_HI3Q_DESC_MODE << BIT_SHIFT_HI3Q_DESC_MODE)
+#define BIT_CLEAR_HI3Q_DESC_MODE(x) ((x) & (~BITS_HI3Q_DESC_MODE))
+#define BIT_GET_HI3Q_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_HI3Q_DESC_MODE) & BIT_MASK_HI3Q_DESC_MODE)
+#define BIT_SET_HI3Q_DESC_MODE(x, v) \
+ (BIT_CLEAR_HI3Q_DESC_MODE(x) | BIT_HI3Q_DESC_MODE(v))
+
+#define BIT_SHIFT_HI3Q_DESC_NUM 0
+#define BIT_MASK_HI3Q_DESC_NUM 0xfff
+#define BIT_HI3Q_DESC_NUM(x) \
+ (((x) & BIT_MASK_HI3Q_DESC_NUM) << BIT_SHIFT_HI3Q_DESC_NUM)
+#define BITS_HI3Q_DESC_NUM (BIT_MASK_HI3Q_DESC_NUM << BIT_SHIFT_HI3Q_DESC_NUM)
+#define BIT_CLEAR_HI3Q_DESC_NUM(x) ((x) & (~BITS_HI3Q_DESC_NUM))
+#define BIT_GET_HI3Q_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_HI3Q_DESC_NUM) & BIT_MASK_HI3Q_DESC_NUM)
+#define BIT_SET_HI3Q_DESC_NUM(x, v) \
+ (BIT_CLEAR_HI3Q_DESC_NUM(x) | BIT_HI3Q_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI4Q_HI5Q_TXBD_NUM (Offset 0x0394) */
+
+#define BIT_P0HI5Q_FLAG BIT(30)
+
+#define BIT_SHIFT_P0HI5Q_DESC_MODE 28
+#define BIT_MASK_P0HI5Q_DESC_MODE 0x3
+#define BIT_P0HI5Q_DESC_MODE(x) \
+ (((x) & BIT_MASK_P0HI5Q_DESC_MODE) << BIT_SHIFT_P0HI5Q_DESC_MODE)
+#define BITS_P0HI5Q_DESC_MODE \
+ (BIT_MASK_P0HI5Q_DESC_MODE << BIT_SHIFT_P0HI5Q_DESC_MODE)
+#define BIT_CLEAR_P0HI5Q_DESC_MODE(x) ((x) & (~BITS_P0HI5Q_DESC_MODE))
+#define BIT_GET_P0HI5Q_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_P0HI5Q_DESC_MODE) & BIT_MASK_P0HI5Q_DESC_MODE)
+#define BIT_SET_P0HI5Q_DESC_MODE(x, v) \
+ (BIT_CLEAR_P0HI5Q_DESC_MODE(x) | BIT_P0HI5Q_DESC_MODE(v))
+
+#define BIT_SHIFT_P0HI5Q_DESC_NUM 16
+#define BIT_MASK_P0HI5Q_DESC_NUM 0xfff
+#define BIT_P0HI5Q_DESC_NUM(x) \
+ (((x) & BIT_MASK_P0HI5Q_DESC_NUM) << BIT_SHIFT_P0HI5Q_DESC_NUM)
+#define BITS_P0HI5Q_DESC_NUM \
+ (BIT_MASK_P0HI5Q_DESC_NUM << BIT_SHIFT_P0HI5Q_DESC_NUM)
+#define BIT_CLEAR_P0HI5Q_DESC_NUM(x) ((x) & (~BITS_P0HI5Q_DESC_NUM))
+#define BIT_GET_P0HI5Q_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_P0HI5Q_DESC_NUM) & BIT_MASK_P0HI5Q_DESC_NUM)
+#define BIT_SET_P0HI5Q_DESC_NUM(x, v) \
+ (BIT_CLEAR_P0HI5Q_DESC_NUM(x) | BIT_P0HI5Q_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+/* 2 REG_HI4Q_TXBD_NUM (Offset 0x0394) */
-#define BIT_CLR_HI5Q_HOST_IDX BIT(11)
+#define BIT_HI4Q_FLAG BIT(14)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8881A_SUPPORT)
-
-
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+/* 2 REG_P0HI4Q_HI5Q_TXBD_NUM (Offset 0x0394) */
-#define BIT_M3DOK BIT(11)
-#define BIT_M3DOKM BIT(11)
+#define BIT_P0HI4Q_FLAG BIT(14)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+/* 2 REG_HI4Q_TXBD_NUM (Offset 0x0394) */
-#define BIT_CLR_HI4Q_HOST_IDX BIT(10)
+#define BIT_SHIFT_HI4Q_DESC_MODE 12
+#define BIT_MASK_HI4Q_DESC_MODE 0x3
+#define BIT_HI4Q_DESC_MODE(x) \
+ (((x) & BIT_MASK_HI4Q_DESC_MODE) << BIT_SHIFT_HI4Q_DESC_MODE)
+#define BITS_HI4Q_DESC_MODE \
+ (BIT_MASK_HI4Q_DESC_MODE << BIT_SHIFT_HI4Q_DESC_MODE)
+#define BIT_CLEAR_HI4Q_DESC_MODE(x) ((x) & (~BITS_HI4Q_DESC_MODE))
+#define BIT_GET_HI4Q_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_HI4Q_DESC_MODE) & BIT_MASK_HI4Q_DESC_MODE)
+#define BIT_SET_HI4Q_DESC_MODE(x, v) \
+ (BIT_CLEAR_HI4Q_DESC_MODE(x) | BIT_HI4Q_DESC_MODE(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8881A_SUPPORT)
+/* 2 REG_P0HI4Q_HI5Q_TXBD_NUM (Offset 0x0394) */
+#define BIT_SHIFT_P0HI4Q_DESC_MODE 12
+#define BIT_MASK_P0HI4Q_DESC_MODE 0x3
+#define BIT_P0HI4Q_DESC_MODE(x) \
+ (((x) & BIT_MASK_P0HI4Q_DESC_MODE) << BIT_SHIFT_P0HI4Q_DESC_MODE)
+#define BITS_P0HI4Q_DESC_MODE \
+ (BIT_MASK_P0HI4Q_DESC_MODE << BIT_SHIFT_P0HI4Q_DESC_MODE)
+#define BIT_CLEAR_P0HI4Q_DESC_MODE(x) ((x) & (~BITS_P0HI4Q_DESC_MODE))
+#define BIT_GET_P0HI4Q_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_P0HI4Q_DESC_MODE) & BIT_MASK_P0HI4Q_DESC_MODE)
+#define BIT_SET_P0HI4Q_DESC_MODE(x, v) \
+ (BIT_CLEAR_P0HI4Q_DESC_MODE(x) | BIT_P0HI4Q_DESC_MODE(v))
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+#endif
-#define BIT_M2DOK BIT(10)
-#define BIT_M2DOKM BIT(10)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_HI4Q_TXBD_NUM (Offset 0x0394) */
+#define BIT_SHIFT_HI4Q_DESC_NUM 0
+#define BIT_MASK_HI4Q_DESC_NUM 0xfff
+#define BIT_HI4Q_DESC_NUM(x) \
+ (((x) & BIT_MASK_HI4Q_DESC_NUM) << BIT_SHIFT_HI4Q_DESC_NUM)
+#define BITS_HI4Q_DESC_NUM (BIT_MASK_HI4Q_DESC_NUM << BIT_SHIFT_HI4Q_DESC_NUM)
+#define BIT_CLEAR_HI4Q_DESC_NUM(x) ((x) & (~BITS_HI4Q_DESC_NUM))
+#define BIT_GET_HI4Q_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_HI4Q_DESC_NUM) & BIT_MASK_HI4Q_DESC_NUM)
+#define BIT_SET_HI4Q_DESC_NUM(x, v) \
+ (BIT_CLEAR_HI4Q_DESC_NUM(x) | BIT_HI4Q_DESC_NUM(v))
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+/* 2 REG_P0HI4Q_HI5Q_TXBD_NUM (Offset 0x0394) */
-#define BIT_CLR_HI3Q_HOST_IDX BIT(9)
+#define BIT_SHIFT_P0HI4Q_DESC_NUM 0
+#define BIT_MASK_P0HI4Q_DESC_NUM 0xfff
+#define BIT_P0HI4Q_DESC_NUM(x) \
+ (((x) & BIT_MASK_P0HI4Q_DESC_NUM) << BIT_SHIFT_P0HI4Q_DESC_NUM)
+#define BITS_P0HI4Q_DESC_NUM \
+ (BIT_MASK_P0HI4Q_DESC_NUM << BIT_SHIFT_P0HI4Q_DESC_NUM)
+#define BIT_CLEAR_P0HI4Q_DESC_NUM(x) ((x) & (~BITS_P0HI4Q_DESC_NUM))
+#define BIT_GET_P0HI4Q_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_P0HI4Q_DESC_NUM) & BIT_MASK_P0HI4Q_DESC_NUM)
+#define BIT_SET_P0HI4Q_DESC_NUM(x, v) \
+ (BIT_CLEAR_P0HI4Q_DESC_NUM(x) | BIT_P0HI4Q_DESC_NUM(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8881A_SUPPORT)
+/* 2 REG_HI5Q_TXBD_NUM (Offset 0x0396) */
+#define BIT_HI5Q_FLAG BIT(14)
+
+#define BIT_SHIFT_HI5Q_DESC_MODE 12
+#define BIT_MASK_HI5Q_DESC_MODE 0x3
+#define BIT_HI5Q_DESC_MODE(x) \
+ (((x) & BIT_MASK_HI5Q_DESC_MODE) << BIT_SHIFT_HI5Q_DESC_MODE)
+#define BITS_HI5Q_DESC_MODE \
+ (BIT_MASK_HI5Q_DESC_MODE << BIT_SHIFT_HI5Q_DESC_MODE)
+#define BIT_CLEAR_HI5Q_DESC_MODE(x) ((x) & (~BITS_HI5Q_DESC_MODE))
+#define BIT_GET_HI5Q_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_HI5Q_DESC_MODE) & BIT_MASK_HI5Q_DESC_MODE)
+#define BIT_SET_HI5Q_DESC_MODE(x, v) \
+ (BIT_CLEAR_HI5Q_DESC_MODE(x) | BIT_HI5Q_DESC_MODE(v))
+
+#define BIT_SHIFT_HI5Q_DESC_NUM 0
+#define BIT_MASK_HI5Q_DESC_NUM 0xfff
+#define BIT_HI5Q_DESC_NUM(x) \
+ (((x) & BIT_MASK_HI5Q_DESC_NUM) << BIT_SHIFT_HI5Q_DESC_NUM)
+#define BITS_HI5Q_DESC_NUM (BIT_MASK_HI5Q_DESC_NUM << BIT_SHIFT_HI5Q_DESC_NUM)
+#define BIT_CLEAR_HI5Q_DESC_NUM(x) ((x) & (~BITS_HI5Q_DESC_NUM))
+#define BIT_GET_HI5Q_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_HI5Q_DESC_NUM) & BIT_MASK_HI5Q_DESC_NUM)
+#define BIT_SET_HI5Q_DESC_NUM(x, v) \
+ (BIT_CLEAR_HI5Q_DESC_NUM(x) | BIT_HI5Q_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI6Q_HI7Q_TXBD_NUM (Offset 0x0398) */
+
+#define BIT_P0HI7Q_FLAG BIT(30)
+#define BIT_CLR_FWCMDQ_HW_IDX BIT(30)
+#define BIT_CLR_P0HI7Q_HW_IDX BIT(29)
+
+#define BIT_SHIFT_P0HI7Q_DESC_MODE 28
+#define BIT_MASK_P0HI7Q_DESC_MODE 0x3
+#define BIT_P0HI7Q_DESC_MODE(x) \
+ (((x) & BIT_MASK_P0HI7Q_DESC_MODE) << BIT_SHIFT_P0HI7Q_DESC_MODE)
+#define BITS_P0HI7Q_DESC_MODE \
+ (BIT_MASK_P0HI7Q_DESC_MODE << BIT_SHIFT_P0HI7Q_DESC_MODE)
+#define BIT_CLEAR_P0HI7Q_DESC_MODE(x) ((x) & (~BITS_P0HI7Q_DESC_MODE))
+#define BIT_GET_P0HI7Q_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_P0HI7Q_DESC_MODE) & BIT_MASK_P0HI7Q_DESC_MODE)
+#define BIT_SET_P0HI7Q_DESC_MODE(x, v) \
+ (BIT_CLEAR_P0HI7Q_DESC_MODE(x) | BIT_P0HI7Q_DESC_MODE(v))
+
+#define BIT_CLR_P0HI6Q_HW_IDX BIT(28)
+#define BIT_CLR_P0HI5Q_HW_IDX BIT(27)
+#define BIT_CLR_P0HI4Q_HW_IDX BIT(26)
+#define BIT_CLR_P0HI3Q_HW_IDX BIT(25)
+#define BIT_CLR_P0HI2Q_HW_IDX BIT(24)
+#define BIT_CLR_P0HI1Q_HW_IDX BIT(23)
+#define BIT_CLR_P0HI0Q_HW_IDX BIT(22)
+#define BIT_CLR_ACH3_HW_IDX BIT(21)
+#define BIT_CLR_ACH2_HW_IDX BIT(20)
+#define BIT_CLR_ACH1_HW_IDX BIT(19)
+#define BIT_CLR_ACH0_HW_IDX BIT(18)
+#define BIT_CLR_P0MGQ_HW_IDX BIT(17)
+
+#define BIT_SHIFT_P0HI7Q_DESC_NUM 16
+#define BIT_MASK_P0HI7Q_DESC_NUM 0xfff
+#define BIT_P0HI7Q_DESC_NUM(x) \
+ (((x) & BIT_MASK_P0HI7Q_DESC_NUM) << BIT_SHIFT_P0HI7Q_DESC_NUM)
+#define BITS_P0HI7Q_DESC_NUM \
+ (BIT_MASK_P0HI7Q_DESC_NUM << BIT_SHIFT_P0HI7Q_DESC_NUM)
+#define BIT_CLEAR_P0HI7Q_DESC_NUM(x) ((x) & (~BITS_P0HI7Q_DESC_NUM))
+#define BIT_GET_P0HI7Q_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_P0HI7Q_DESC_NUM) & BIT_MASK_P0HI7Q_DESC_NUM)
+#define BIT_SET_P0HI7Q_DESC_NUM(x, v) \
+ (BIT_CLEAR_P0HI7Q_DESC_NUM(x) | BIT_P0HI7Q_DESC_NUM(v))
+
+#define BIT_CLR_P0RXQ_HW_IDX BIT(16)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+/* 2 REG_HI6Q_TXBD_NUM (Offset 0x0398) */
-#define BIT_M1DOK BIT(9)
-#define BIT_M1DOKM BIT(9)
+#define BIT_HI6Q_FLAG BIT(14)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_P0HI6Q_HI7Q_TXBD_NUM (Offset 0x0398) */
+#define BIT_P0HI6Q_FLAG BIT(14)
+#define BIT_CLR_PFWCMDQ_HOST_IDX BIT(14)
+#define BIT_CLR_P0HI7Q_HOST_IDX BIT(13)
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+#endif
-#define BIT_CLR_HI2Q_HOST_IDX BIT(8)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_HI6Q_TXBD_NUM (Offset 0x0398) */
+#define BIT_SHIFT_HI6Q_DESC_MODE 12
+#define BIT_MASK_HI6Q_DESC_MODE 0x3
+#define BIT_HI6Q_DESC_MODE(x) \
+ (((x) & BIT_MASK_HI6Q_DESC_MODE) << BIT_SHIFT_HI6Q_DESC_MODE)
+#define BITS_HI6Q_DESC_MODE \
+ (BIT_MASK_HI6Q_DESC_MODE << BIT_SHIFT_HI6Q_DESC_MODE)
+#define BIT_CLEAR_HI6Q_DESC_MODE(x) ((x) & (~BITS_HI6Q_DESC_MODE))
+#define BIT_GET_HI6Q_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_HI6Q_DESC_MODE) & BIT_MASK_HI6Q_DESC_MODE)
+#define BIT_SET_HI6Q_DESC_MODE(x, v) \
+ (BIT_CLEAR_HI6Q_DESC_MODE(x) | BIT_HI6Q_DESC_MODE(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI6Q_HI7Q_TXBD_NUM (Offset 0x0398) */
+
+#define BIT_SHIFT_P0HI6Q_DESC_MODE 12
+#define BIT_MASK_P0HI6Q_DESC_MODE 0x3
+#define BIT_P0HI6Q_DESC_MODE(x) \
+ (((x) & BIT_MASK_P0HI6Q_DESC_MODE) << BIT_SHIFT_P0HI6Q_DESC_MODE)
+#define BITS_P0HI6Q_DESC_MODE \
+ (BIT_MASK_P0HI6Q_DESC_MODE << BIT_SHIFT_P0HI6Q_DESC_MODE)
+#define BIT_CLEAR_P0HI6Q_DESC_MODE(x) ((x) & (~BITS_P0HI6Q_DESC_MODE))
+#define BIT_GET_P0HI6Q_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_P0HI6Q_DESC_MODE) & BIT_MASK_P0HI6Q_DESC_MODE)
+#define BIT_SET_P0HI6Q_DESC_MODE(x, v) \
+ (BIT_CLEAR_P0HI6Q_DESC_MODE(x) | BIT_P0HI6Q_DESC_MODE(v))
+
+#define BIT_CLR_P0HI6Q_HOST_IDX BIT(12)
+#define BIT_CLR_P0HI5Q_HOST_IDX BIT(11)
+#define BIT_CLR_P0HI4Q_HOST_IDX BIT(10)
+#define BIT_CLR_P0HI3Q_HOST_IDX BIT(9)
+#define BIT_CLR_P0HI2Q_HOST_IDX BIT(8)
+#define BIT_CLR_P0HI1Q_HOST_IDX BIT(7)
+#define BIT_CLR_P0HI0Q_HOST_IDX BIT(6)
+#define BIT_CLR_ACH3_HOST_IDX BIT(5)
+#define BIT_CLR_ACH2_HOST_IDX BIT(4)
+#define BIT_CLR_ACH1_HOST_IDX BIT(3)
+#define BIT_CLR_ACH0_HOST_IDX BIT(2)
+#define BIT_CLR_P0MGQ_HOST_IDX BIT(1)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8881A_SUPPORT)
+/* 2 REG_HI6Q_TXBD_NUM (Offset 0x0398) */
+#define BIT_SHIFT_HI6Q_DESC_NUM 0
+#define BIT_MASK_HI6Q_DESC_NUM 0xfff
+#define BIT_HI6Q_DESC_NUM(x) \
+ (((x) & BIT_MASK_HI6Q_DESC_NUM) << BIT_SHIFT_HI6Q_DESC_NUM)
+#define BITS_HI6Q_DESC_NUM (BIT_MASK_HI6Q_DESC_NUM << BIT_SHIFT_HI6Q_DESC_NUM)
+#define BIT_CLEAR_HI6Q_DESC_NUM(x) ((x) & (~BITS_HI6Q_DESC_NUM))
+#define BIT_GET_HI6Q_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_HI6Q_DESC_NUM) & BIT_MASK_HI6Q_DESC_NUM)
+#define BIT_SET_HI6Q_DESC_NUM(x, v) \
+ (BIT_CLEAR_HI6Q_DESC_NUM(x) | BIT_HI6Q_DESC_NUM(v))
-/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_M0DOK BIT(8)
-#define BIT_M0DOKM BIT(8)
+/* 2 REG_P0HI6Q_HI7Q_TXBD_NUM (Offset 0x0398) */
-#define BIT_SHIFT_TX_STATE 8
-#define BIT_MASK_TX_STATE 0xf
-#define BIT_TX_STATE(x) (((x) & BIT_MASK_TX_STATE) << BIT_SHIFT_TX_STATE)
-#define BIT_GET_TX_STATE(x) (((x) >> BIT_SHIFT_TX_STATE) & BIT_MASK_TX_STATE)
+#define BIT_SHIFT_P0HI6Q_DESC_NUM 0
+#define BIT_MASK_P0HI6Q_DESC_NUM 0xfff
+#define BIT_P0HI6Q_DESC_NUM(x) \
+ (((x) & BIT_MASK_P0HI6Q_DESC_NUM) << BIT_SHIFT_P0HI6Q_DESC_NUM)
+#define BITS_P0HI6Q_DESC_NUM \
+ (BIT_MASK_P0HI6Q_DESC_NUM << BIT_SHIFT_P0HI6Q_DESC_NUM)
+#define BIT_CLEAR_P0HI6Q_DESC_NUM(x) ((x) & (~BITS_P0HI6Q_DESC_NUM))
+#define BIT_GET_P0HI6Q_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_P0HI6Q_DESC_NUM) & BIT_MASK_P0HI6Q_DESC_NUM)
+#define BIT_SET_P0HI6Q_DESC_NUM(x, v) \
+ (BIT_CLEAR_P0HI6Q_DESC_NUM(x) | BIT_P0HI6Q_DESC_NUM(v))
+#define BIT_CLR_P0RXQ_HOST_IDX BIT(0)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_HI7Q_TXBD_NUM (Offset 0x039A) */
+#define BIT_HI7Q_FLAG BIT(14)
+
+#define BIT_SHIFT_HI7Q_DESC_MODE 12
+#define BIT_MASK_HI7Q_DESC_MODE 0x3
+#define BIT_HI7Q_DESC_MODE(x) \
+ (((x) & BIT_MASK_HI7Q_DESC_MODE) << BIT_SHIFT_HI7Q_DESC_MODE)
+#define BITS_HI7Q_DESC_MODE \
+ (BIT_MASK_HI7Q_DESC_MODE << BIT_SHIFT_HI7Q_DESC_MODE)
+#define BIT_CLEAR_HI7Q_DESC_MODE(x) ((x) & (~BITS_HI7Q_DESC_MODE))
+#define BIT_GET_HI7Q_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_HI7Q_DESC_MODE) & BIT_MASK_HI7Q_DESC_MODE)
+#define BIT_SET_HI7Q_DESC_MODE(x, v) \
+ (BIT_CLEAR_HI7Q_DESC_MODE(x) | BIT_HI7Q_DESC_MODE(v))
+
+#define BIT_SHIFT_HI7Q_DESC_NUM 0
+#define BIT_MASK_HI7Q_DESC_NUM 0xfff
+#define BIT_HI7Q_DESC_NUM(x) \
+ (((x) & BIT_MASK_HI7Q_DESC_NUM) << BIT_SHIFT_HI7Q_DESC_NUM)
+#define BITS_HI7Q_DESC_NUM (BIT_MASK_HI7Q_DESC_NUM << BIT_SHIFT_HI7Q_DESC_NUM)
+#define BIT_CLEAR_HI7Q_DESC_NUM(x) ((x) & (~BITS_HI7Q_DESC_NUM))
+#define BIT_GET_HI7Q_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_HI7Q_DESC_NUM) & BIT_MASK_HI7Q_DESC_NUM)
+#define BIT_SET_HI7Q_DESC_NUM(x, v) \
+ (BIT_CLEAR_HI7Q_DESC_NUM(x) | BIT_HI7Q_DESC_NUM(v))
/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
-#define BIT_CLR_HI1Q_HOST_IDX BIT(7)
-#define BIT_CLR_HI0Q_HOST_IDX BIT(6)
+#define BIT_CLR_HI7Q_HW_IDX BIT(29)
+#define BIT_CLR_HI6Q_HW_IDX BIT(28)
+#define BIT_CLR_HI5Q_HW_IDX BIT(27)
+#define BIT_CLR_HI4Q_HW_IDX BIT(26)
+#define BIT_CLR_HI3Q_HW_IDX BIT(25)
+#define BIT_CLR_HI2Q_HW_IDX BIT(24)
+#define BIT_CLR_HI1Q_HW_IDX BIT(23)
#endif
-
#if (HALMAC_8881A_SUPPORT)
-
/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
-#define BIT_MGQDOK BIT(6)
-#define BIT_MGQDOKM BIT(6)
+#define BIT_BCN7DOK BIT(23)
+#define BIT_BCN7DOKM BIT(23)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
-#define BIT_CLR_BKQ_HOST_IDX BIT(5)
+#define BIT_CLR_HI0Q_HW_IDX BIT(22)
#endif
-
#if (HALMAC_8881A_SUPPORT)
-
/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
-#define BIT_BKQDOK BIT(5)
-#define BIT_BKQDOKM BIT(5)
+#define BIT_BCN6DOK BIT(22)
+#define BIT_BCN6DOKM BIT(22)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
-#define BIT_CLR_BEQ_HOST_IDX BIT(4)
+#define BIT_CLR_BKQ_HW_IDX BIT(21)
#endif
-
#if (HALMAC_8881A_SUPPORT)
-
/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
-
-#define BIT_SHIFT_HPS_CLKR 4
-#define BIT_MASK_HPS_CLKR 0x3
-#define BIT_HPS_CLKR(x) (((x) & BIT_MASK_HPS_CLKR) << BIT_SHIFT_HPS_CLKR)
-#define BIT_GET_HPS_CLKR(x) (((x) >> BIT_SHIFT_HPS_CLKR) & BIT_MASK_HPS_CLKR)
-
-#define BIT_BEQDOK BIT(4)
-#define BIT_BEQDOKM BIT(4)
+#define BIT_BCN5DOK BIT(21)
+#define BIT_BCN5DOKM BIT(21)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
-#define BIT_CLR_VIQ_HOST_IDX BIT(3)
+#define BIT_CLR_BEQ_HW_IDX BIT(20)
#endif
-
#if (HALMAC_8881A_SUPPORT)
-
/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
-#define BIT_LX_INT BIT(3)
-#define BIT_VIQDOK BIT(3)
-#define BIT_VIQDOKM BIT(3)
-#define BIT_MST_BUSY BIT(3)
+#define BIT_BCN4DOK BIT(20)
+#define BIT_BCN4DOKM BIT(20)
+#define BIT_RX_OVER_RD_ERR BIT(20)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
-#define BIT_CLR_VOQ_HOST_IDX BIT(2)
+#define BIT_CLR_VIQ_HW_IDX BIT(19)
#endif
-
#if (HALMAC_8881A_SUPPORT)
-
/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
-#define BIT_VOQDOK BIT(2)
-#define BIT_VOQDOKM BIT(2)
-#define BIT_SLV_BUSY BIT(2)
+#define BIT_BCN3DOK BIT(19)
+#define BIT_BCN3DOKM BIT(19)
+#define BIT_RXDMA_STUCK BIT(19)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
-#define BIT_CLR_MGQ_HOST_IDX BIT(1)
+#define BIT_CLR_VOQ_HW_IDX BIT(18)
#endif
-
#if (HALMAC_8881A_SUPPORT)
-
/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
-#define BIT_RDUM BIT(1)
-#define BIT_RXDES_UNAVAIL BIT(1)
+#define BIT_BCN2DOK BIT(18)
+#define BIT_BCN2DOKM BIT(18)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+#define BIT_CLR_MGQ_HW_IDX BIT(17)
-/* 2 REG_TSFTIMER_HCI (Offset 0x039C) */
+#endif
+#if (HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_TSFT1_HCI 0
-#define BIT_MASK_TSFT1_HCI 0xffff
-#define BIT_TSFT1_HCI(x) (((x) & BIT_MASK_TSFT1_HCI) << BIT_SHIFT_TSFT1_HCI)
-#define BIT_GET_TSFT1_HCI(x) (((x) >> BIT_SHIFT_TSFT1_HCI) & BIT_MASK_TSFT1_HCI)
+/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
-#define BIT_CLR_RXQ_HOST_IDX BIT(0)
+#define BIT_BCN1DOK BIT(17)
+#define BIT_BCN1DOKM BIT(17)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8881A_SUPPORT)
+/* 2 REG_TSFTIMER_HCI (Offset 0x039C) */
+
+#define BIT_SHIFT_TSFT2_HCI 16
+#define BIT_MASK_TSFT2_HCI 0xffff
+#define BIT_TSFT2_HCI(x) (((x) & BIT_MASK_TSFT2_HCI) << BIT_SHIFT_TSFT2_HCI)
+#define BITS_TSFT2_HCI (BIT_MASK_TSFT2_HCI << BIT_SHIFT_TSFT2_HCI)
+#define BIT_CLEAR_TSFT2_HCI(x) ((x) & (~BITS_TSFT2_HCI))
+#define BIT_GET_TSFT2_HCI(x) (((x) >> BIT_SHIFT_TSFT2_HCI) & BIT_MASK_TSFT2_HCI)
+#define BIT_SET_TSFT2_HCI(x, v) (BIT_CLEAR_TSFT2_HCI(x) | BIT_TSFT2_HCI(v))
+
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
-#define BIT_RXDOK BIT(0)
-#define BIT_RXDOKM BIT(0)
-#define BIT_EN_DBG_STUCK BIT(0)
+#define BIT_CLR_RXQ_HW_IDX BIT(16)
#endif
+#if (HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+#define BIT_BCN0DOK BIT(16)
+#define BIT_BCN0DOKM BIT(16)
-/* 2 REG_VOQ_TXBD_IDX (Offset 0x03A0) */
+#define BIT_SHIFT_RX_STATE 16
+#define BIT_MASK_RX_STATE 0x7
+#define BIT_RX_STATE(x) (((x) & BIT_MASK_RX_STATE) << BIT_SHIFT_RX_STATE)
+#define BITS_RX_STATE (BIT_MASK_RX_STATE << BIT_SHIFT_RX_STATE)
+#define BIT_CLEAR_RX_STATE(x) ((x) & (~BITS_RX_STATE))
+#define BIT_GET_RX_STATE(x) (((x) >> BIT_SHIFT_RX_STATE) & BIT_MASK_RX_STATE)
+#define BIT_SET_RX_STATE(x, v) (BIT_CLEAR_RX_STATE(x) | BIT_RX_STATE(v))
+#define BIT_SRST_TX BIT(15)
+#define BIT_M7DOK BIT(15)
+#define BIT_M7DOKM BIT(15)
+#define BIT_TDE_NO_IDLE BIT(15)
+#define BIT_SRST_RX BIT(14)
+#define BIT_M6DOK BIT(14)
+#define BIT_M6DOKM BIT(14)
+#define BIT_TXDMA_STUCK BIT(14)
-#define BIT_SHIFT_VOQ_HW_IDX 16
-#define BIT_MASK_VOQ_HW_IDX 0xfff
-#define BIT_VOQ_HW_IDX(x) (((x) & BIT_MASK_VOQ_HW_IDX) << BIT_SHIFT_VOQ_HW_IDX)
-#define BIT_GET_VOQ_HW_IDX(x) (((x) >> BIT_SHIFT_VOQ_HW_IDX) & BIT_MASK_VOQ_HW_IDX)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_VOQ_HOST_IDX 0
-#define BIT_MASK_VOQ_HOST_IDX 0xfff
-#define BIT_VOQ_HOST_IDX(x) (((x) & BIT_MASK_VOQ_HOST_IDX) << BIT_SHIFT_VOQ_HOST_IDX)
-#define BIT_GET_VOQ_HOST_IDX(x) (((x) >> BIT_SHIFT_VOQ_HOST_IDX) & BIT_MASK_VOQ_HOST_IDX)
+/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+#define BIT_CLR_HI7Q_HOST_IDX BIT(13)
-/* 2 REG_VIQ_TXBD_IDX (Offset 0x03A4) */
+#endif
+#if (HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_VIQ_HW_IDX 16
-#define BIT_MASK_VIQ_HW_IDX 0xfff
-#define BIT_VIQ_HW_IDX(x) (((x) & BIT_MASK_VIQ_HW_IDX) << BIT_SHIFT_VIQ_HW_IDX)
-#define BIT_GET_VIQ_HW_IDX(x) (((x) >> BIT_SHIFT_VIQ_HW_IDX) & BIT_MASK_VIQ_HW_IDX)
+/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+#define BIT_M5DOK BIT(13)
+#define BIT_M5DOKM BIT(13)
+#define BIT_TDE_FULL_ERR BIT(13)
-#define BIT_SHIFT_VIQ_HOST_IDX 0
-#define BIT_MASK_VIQ_HOST_IDX 0xfff
-#define BIT_VIQ_HOST_IDX(x) (((x) & BIT_MASK_VIQ_HOST_IDX) << BIT_SHIFT_VIQ_HOST_IDX)
-#define BIT_GET_VIQ_HOST_IDX(x) (((x) >> BIT_SHIFT_VIQ_HOST_IDX) & BIT_MASK_VIQ_HOST_IDX)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_BEQ_TXBD_IDX (Offset 0x03A8) */
+/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+#define BIT_CLR_HI6Q_HOST_IDX BIT(12)
-#define BIT_SHIFT_BEQ_HW_IDX 16
-#define BIT_MASK_BEQ_HW_IDX 0xfff
-#define BIT_BEQ_HW_IDX(x) (((x) & BIT_MASK_BEQ_HW_IDX) << BIT_SHIFT_BEQ_HW_IDX)
-#define BIT_GET_BEQ_HW_IDX(x) (((x) >> BIT_SHIFT_BEQ_HW_IDX) & BIT_MASK_BEQ_HW_IDX)
+#endif
+#if (HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_BEQ_HOST_IDX 0
-#define BIT_MASK_BEQ_HOST_IDX 0xfff
-#define BIT_BEQ_HOST_IDX(x) (((x) & BIT_MASK_BEQ_HOST_IDX) << BIT_SHIFT_BEQ_HOST_IDX)
-#define BIT_GET_BEQ_HOST_IDX(x) (((x) >> BIT_SHIFT_BEQ_HOST_IDX) & BIT_MASK_BEQ_HOST_IDX)
+/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+#define BIT_M4DOK BIT(12)
+#define BIT_M4DOKM BIT(12)
+#define BIT_HD_SIZE_ERR BIT(12)
-/* 2 REG_BKQ_TXBD_IDX (Offset 0x03AC) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_BKQ_HW_IDX 16
-#define BIT_MASK_BKQ_HW_IDX 0xfff
-#define BIT_BKQ_HW_IDX(x) (((x) & BIT_MASK_BKQ_HW_IDX) << BIT_SHIFT_BKQ_HW_IDX)
-#define BIT_GET_BKQ_HW_IDX(x) (((x) >> BIT_SHIFT_BKQ_HW_IDX) & BIT_MASK_BKQ_HW_IDX)
+/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+#define BIT_CLR_HI5Q_HOST_IDX BIT(11)
-#define BIT_SHIFT_BKQ_HOST_IDX 0
-#define BIT_MASK_BKQ_HOST_IDX 0xfff
-#define BIT_BKQ_HOST_IDX(x) (((x) & BIT_MASK_BKQ_HOST_IDX) << BIT_SHIFT_BKQ_HOST_IDX)
-#define BIT_GET_BKQ_HOST_IDX(x) (((x) >> BIT_SHIFT_BKQ_HOST_IDX) & BIT_MASK_BKQ_HOST_IDX)
+#endif
+#if (HALMAC_8881A_SUPPORT)
-/* 2 REG_MGQ_TXBD_IDX (Offset 0x03B0) */
+/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+#define BIT_M3DOK BIT(11)
+#define BIT_M3DOKM BIT(11)
-#define BIT_SHIFT_MGQ_HW_IDX 16
-#define BIT_MASK_MGQ_HW_IDX 0xfff
-#define BIT_MGQ_HW_IDX(x) (((x) & BIT_MASK_MGQ_HW_IDX) << BIT_SHIFT_MGQ_HW_IDX)
-#define BIT_GET_MGQ_HW_IDX(x) (((x) >> BIT_SHIFT_MGQ_HW_IDX) & BIT_MASK_MGQ_HW_IDX)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_MGQ_HOST_IDX 0
-#define BIT_MASK_MGQ_HOST_IDX 0xfff
-#define BIT_MGQ_HOST_IDX(x) (((x) & BIT_MASK_MGQ_HOST_IDX) << BIT_SHIFT_MGQ_HOST_IDX)
-#define BIT_GET_MGQ_HOST_IDX(x) (((x) >> BIT_SHIFT_MGQ_HOST_IDX) & BIT_MASK_MGQ_HOST_IDX)
+/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+#define BIT_CLR_HI4Q_HOST_IDX BIT(10)
-/* 2 REG_RXQ_RXBD_IDX (Offset 0x03B4) */
+#endif
+#if (HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_RXQ_HW_IDX 16
-#define BIT_MASK_RXQ_HW_IDX 0xfff
-#define BIT_RXQ_HW_IDX(x) (((x) & BIT_MASK_RXQ_HW_IDX) << BIT_SHIFT_RXQ_HW_IDX)
-#define BIT_GET_RXQ_HW_IDX(x) (((x) >> BIT_SHIFT_RXQ_HW_IDX) & BIT_MASK_RXQ_HW_IDX)
+/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+#define BIT_M2DOK BIT(10)
+#define BIT_M2DOKM BIT(10)
-#define BIT_SHIFT_RXQ_HOST_IDX 0
-#define BIT_MASK_RXQ_HOST_IDX 0xfff
-#define BIT_RXQ_HOST_IDX(x) (((x) & BIT_MASK_RXQ_HOST_IDX) << BIT_SHIFT_RXQ_HOST_IDX)
-#define BIT_GET_RXQ_HOST_IDX(x) (((x) >> BIT_SHIFT_RXQ_HOST_IDX) & BIT_MASK_RXQ_HOST_IDX)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_HI0Q_TXBD_IDX (Offset 0x03B8) */
+/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+#define BIT_CLR_HI3Q_HOST_IDX BIT(9)
-#define BIT_SHIFT_HI0Q_HW_IDX 16
-#define BIT_MASK_HI0Q_HW_IDX 0xfff
-#define BIT_HI0Q_HW_IDX(x) (((x) & BIT_MASK_HI0Q_HW_IDX) << BIT_SHIFT_HI0Q_HW_IDX)
-#define BIT_GET_HI0Q_HW_IDX(x) (((x) >> BIT_SHIFT_HI0Q_HW_IDX) & BIT_MASK_HI0Q_HW_IDX)
+#endif
+#if (HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_HI0Q_HOST_IDX 0
-#define BIT_MASK_HI0Q_HOST_IDX 0xfff
-#define BIT_HI0Q_HOST_IDX(x) (((x) & BIT_MASK_HI0Q_HOST_IDX) << BIT_SHIFT_HI0Q_HOST_IDX)
-#define BIT_GET_HI0Q_HOST_IDX(x) (((x) >> BIT_SHIFT_HI0Q_HOST_IDX) & BIT_MASK_HI0Q_HOST_IDX)
+/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+#define BIT_M1DOK BIT(9)
+#define BIT_M1DOKM BIT(9)
-/* 2 REG_HI1Q_TXBD_IDX (Offset 0x03BC) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_HI1Q_HW_IDX 16
-#define BIT_MASK_HI1Q_HW_IDX 0xfff
-#define BIT_HI1Q_HW_IDX(x) (((x) & BIT_MASK_HI1Q_HW_IDX) << BIT_SHIFT_HI1Q_HW_IDX)
-#define BIT_GET_HI1Q_HW_IDX(x) (((x) >> BIT_SHIFT_HI1Q_HW_IDX) & BIT_MASK_HI1Q_HW_IDX)
+/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+#define BIT_CLR_HI2Q_HOST_IDX BIT(8)
-#define BIT_SHIFT_HI1Q_HOST_IDX 0
-#define BIT_MASK_HI1Q_HOST_IDX 0xfff
-#define BIT_HI1Q_HOST_IDX(x) (((x) & BIT_MASK_HI1Q_HOST_IDX) << BIT_SHIFT_HI1Q_HOST_IDX)
-#define BIT_GET_HI1Q_HOST_IDX(x) (((x) >> BIT_SHIFT_HI1Q_HOST_IDX) & BIT_MASK_HI1Q_HOST_IDX)
+#endif
+#if (HALMAC_8881A_SUPPORT)
-/* 2 REG_HI2Q_TXBD_IDX (Offset 0x03C0) */
+/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+#define BIT_M0DOK BIT(8)
+#define BIT_M0DOKM BIT(8)
-#define BIT_SHIFT_HI2Q_HW_IDX 16
-#define BIT_MASK_HI2Q_HW_IDX 0xfff
-#define BIT_HI2Q_HW_IDX(x) (((x) & BIT_MASK_HI2Q_HW_IDX) << BIT_SHIFT_HI2Q_HW_IDX)
-#define BIT_GET_HI2Q_HW_IDX(x) (((x) >> BIT_SHIFT_HI2Q_HW_IDX) & BIT_MASK_HI2Q_HW_IDX)
+#define BIT_SHIFT_TX_STATE 8
+#define BIT_MASK_TX_STATE 0xf
+#define BIT_TX_STATE(x) (((x) & BIT_MASK_TX_STATE) << BIT_SHIFT_TX_STATE)
+#define BITS_TX_STATE (BIT_MASK_TX_STATE << BIT_SHIFT_TX_STATE)
+#define BIT_CLEAR_TX_STATE(x) ((x) & (~BITS_TX_STATE))
+#define BIT_GET_TX_STATE(x) (((x) >> BIT_SHIFT_TX_STATE) & BIT_MASK_TX_STATE)
+#define BIT_SET_TX_STATE(x, v) (BIT_CLEAR_TX_STATE(x) | BIT_TX_STATE(v))
+#endif
-#define BIT_SHIFT_HI2Q_HOST_IDX 0
-#define BIT_MASK_HI2Q_HOST_IDX 0xfff
-#define BIT_HI2Q_HOST_IDX(x) (((x) & BIT_MASK_HI2Q_HOST_IDX) << BIT_SHIFT_HI2Q_HOST_IDX)
-#define BIT_GET_HI2Q_HOST_IDX(x) (((x) >> BIT_SHIFT_HI2Q_HOST_IDX) & BIT_MASK_HI2Q_HOST_IDX)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
-/* 2 REG_HI3Q_TXBD_IDX (Offset 0x03C4) */
+#define BIT_CLR_HI1Q_HOST_IDX BIT(7)
+#define BIT_CLR_HI0Q_HOST_IDX BIT(6)
+#endif
-#define BIT_SHIFT_HI3Q_HW_IDX 16
-#define BIT_MASK_HI3Q_HW_IDX 0xfff
-#define BIT_HI3Q_HW_IDX(x) (((x) & BIT_MASK_HI3Q_HW_IDX) << BIT_SHIFT_HI3Q_HW_IDX)
-#define BIT_GET_HI3Q_HW_IDX(x) (((x) >> BIT_SHIFT_HI3Q_HW_IDX) & BIT_MASK_HI3Q_HW_IDX)
+#if (HALMAC_8881A_SUPPORT)
+/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
-#define BIT_SHIFT_HI3Q_HOST_IDX 0
-#define BIT_MASK_HI3Q_HOST_IDX 0xfff
-#define BIT_HI3Q_HOST_IDX(x) (((x) & BIT_MASK_HI3Q_HOST_IDX) << BIT_SHIFT_HI3Q_HOST_IDX)
-#define BIT_GET_HI3Q_HOST_IDX(x) (((x) >> BIT_SHIFT_HI3Q_HOST_IDX) & BIT_MASK_HI3Q_HOST_IDX)
+#define BIT_MGQDOK BIT(6)
+#define BIT_MGQDOKM BIT(6)
+#endif
-/* 2 REG_HI4Q_TXBD_IDX (Offset 0x03C8) */
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
-#define BIT_SHIFT_HI4Q_HW_IDX 16
-#define BIT_MASK_HI4Q_HW_IDX 0xfff
-#define BIT_HI4Q_HW_IDX(x) (((x) & BIT_MASK_HI4Q_HW_IDX) << BIT_SHIFT_HI4Q_HW_IDX)
-#define BIT_GET_HI4Q_HW_IDX(x) (((x) >> BIT_SHIFT_HI4Q_HW_IDX) & BIT_MASK_HI4Q_HW_IDX)
+#define BIT_CLR_BKQ_HOST_IDX BIT(5)
+#endif
-#define BIT_SHIFT_HI4Q_HOST_IDX 0
-#define BIT_MASK_HI4Q_HOST_IDX 0xfff
-#define BIT_HI4Q_HOST_IDX(x) (((x) & BIT_MASK_HI4Q_HOST_IDX) << BIT_SHIFT_HI4Q_HOST_IDX)
-#define BIT_GET_HI4Q_HOST_IDX(x) (((x) >> BIT_SHIFT_HI4Q_HOST_IDX) & BIT_MASK_HI4Q_HOST_IDX)
+#if (HALMAC_8881A_SUPPORT)
+/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
-/* 2 REG_HI5Q_TXBD_IDX (Offset 0x03CC) */
+#define BIT_BKQDOK BIT(5)
+#define BIT_BKQDOKM BIT(5)
+#endif
-#define BIT_SHIFT_HI5Q_HW_IDX 16
-#define BIT_MASK_HI5Q_HW_IDX 0xfff
-#define BIT_HI5Q_HW_IDX(x) (((x) & BIT_MASK_HI5Q_HW_IDX) << BIT_SHIFT_HI5Q_HW_IDX)
-#define BIT_GET_HI5Q_HW_IDX(x) (((x) >> BIT_SHIFT_HI5Q_HW_IDX) & BIT_MASK_HI5Q_HW_IDX)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
-#define BIT_SHIFT_HI5Q_HOST_IDX 0
-#define BIT_MASK_HI5Q_HOST_IDX 0xfff
-#define BIT_HI5Q_HOST_IDX(x) (((x) & BIT_MASK_HI5Q_HOST_IDX) << BIT_SHIFT_HI5Q_HOST_IDX)
-#define BIT_GET_HI5Q_HOST_IDX(x) (((x) >> BIT_SHIFT_HI5Q_HOST_IDX) & BIT_MASK_HI5Q_HOST_IDX)
+#define BIT_CLR_BEQ_HOST_IDX BIT(4)
+#endif
-/* 2 REG_HI6Q_TXBD_IDX (Offset 0x03D0) */
+#if (HALMAC_8881A_SUPPORT)
+/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
-#define BIT_SHIFT_HI6Q_HW_IDX 16
-#define BIT_MASK_HI6Q_HW_IDX 0xfff
-#define BIT_HI6Q_HW_IDX(x) (((x) & BIT_MASK_HI6Q_HW_IDX) << BIT_SHIFT_HI6Q_HW_IDX)
-#define BIT_GET_HI6Q_HW_IDX(x) (((x) >> BIT_SHIFT_HI6Q_HW_IDX) & BIT_MASK_HI6Q_HW_IDX)
+#define BIT_SHIFT_HPS_CLKR 4
+#define BIT_MASK_HPS_CLKR 0x3
+#define BIT_HPS_CLKR(x) (((x) & BIT_MASK_HPS_CLKR) << BIT_SHIFT_HPS_CLKR)
+#define BITS_HPS_CLKR (BIT_MASK_HPS_CLKR << BIT_SHIFT_HPS_CLKR)
+#define BIT_CLEAR_HPS_CLKR(x) ((x) & (~BITS_HPS_CLKR))
+#define BIT_GET_HPS_CLKR(x) (((x) >> BIT_SHIFT_HPS_CLKR) & BIT_MASK_HPS_CLKR)
+#define BIT_SET_HPS_CLKR(x, v) (BIT_CLEAR_HPS_CLKR(x) | BIT_HPS_CLKR(v))
+#define BIT_BEQDOK BIT(4)
+#define BIT_BEQDOKM BIT(4)
-#define BIT_SHIFT_HI6Q_HOST_IDX 0
-#define BIT_MASK_HI6Q_HOST_IDX 0xfff
-#define BIT_HI6Q_HOST_IDX(x) (((x) & BIT_MASK_HI6Q_HOST_IDX) << BIT_SHIFT_HI6Q_HOST_IDX)
-#define BIT_GET_HI6Q_HOST_IDX(x) (((x) >> BIT_SHIFT_HI6Q_HOST_IDX) & BIT_MASK_HI6Q_HOST_IDX)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_HI7Q_TXBD_IDX (Offset 0x03D4) */
+/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+#define BIT_CLR_VIQ_HOST_IDX BIT(3)
-#define BIT_SHIFT_HI7Q_HW_IDX 16
-#define BIT_MASK_HI7Q_HW_IDX 0xfff
-#define BIT_HI7Q_HW_IDX(x) (((x) & BIT_MASK_HI7Q_HW_IDX) << BIT_SHIFT_HI7Q_HW_IDX)
-#define BIT_GET_HI7Q_HW_IDX(x) (((x) >> BIT_SHIFT_HI7Q_HW_IDX) & BIT_MASK_HI7Q_HW_IDX)
+#endif
+#if (HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_HI7Q_HOST_IDX 0
-#define BIT_MASK_HI7Q_HOST_IDX 0xfff
-#define BIT_HI7Q_HOST_IDX(x) (((x) & BIT_MASK_HI7Q_HOST_IDX) << BIT_SHIFT_HI7Q_HOST_IDX)
-#define BIT_GET_HI7Q_HOST_IDX(x) (((x) >> BIT_SHIFT_HI7Q_HOST_IDX) & BIT_MASK_HI7Q_HOST_IDX)
+/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+#define BIT_LX_INT BIT(3)
+#define BIT_VIQDOK BIT(3)
+#define BIT_VIQDOKM BIT(3)
+#define BIT_MST_BUSY BIT(3)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+#define BIT_CLR_VOQ_HOST_IDX BIT(2)
-/* 2 REG_DBG_SEL_V1 (Offset 0x03D8) */
+#endif
-#define BIT_DIS_TXDMA_PRE BIT(7)
-#define BIT_DIS_RXDMA_PRE BIT(6)
-#define BIT_TXFLAG_EXIT_L1_EN BIT(2)
+#if (HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_DBG_SEL 0
-#define BIT_MASK_DBG_SEL 0xff
-#define BIT_DBG_SEL(x) (((x) & BIT_MASK_DBG_SEL) << BIT_SHIFT_DBG_SEL)
-#define BIT_GET_DBG_SEL(x) (((x) >> BIT_SHIFT_DBG_SEL) & BIT_MASK_DBG_SEL)
+/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+#define BIT_VOQDOK BIT(2)
+#define BIT_VOQDOKM BIT(2)
+#define BIT_SLV_BUSY BIT(2)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+#define BIT_CLR_MGQ_HOST_IDX BIT(1)
-/* 2 REG_PCIE_HRPWM1_V1 (Offset 0x03D9) */
+#endif
+#if (HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_PCIE_HRPWM 0
-#define BIT_MASK_PCIE_HRPWM 0xff
-#define BIT_PCIE_HRPWM(x) (((x) & BIT_MASK_PCIE_HRPWM) << BIT_SHIFT_PCIE_HRPWM)
-#define BIT_GET_PCIE_HRPWM(x) (((x) >> BIT_SHIFT_PCIE_HRPWM) & BIT_MASK_PCIE_HRPWM)
+/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+#define BIT_RDUM BIT(1)
+#define BIT_RXDES_UNAVAIL BIT(1)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_TSFTIMER_HCI (Offset 0x039C) */
+#define BIT_SHIFT_TSFT1_HCI 0
+#define BIT_MASK_TSFT1_HCI 0xffff
+#define BIT_TSFT1_HCI(x) (((x) & BIT_MASK_TSFT1_HCI) << BIT_SHIFT_TSFT1_HCI)
+#define BITS_TSFT1_HCI (BIT_MASK_TSFT1_HCI << BIT_SHIFT_TSFT1_HCI)
+#define BIT_CLEAR_TSFT1_HCI(x) ((x) & (~BITS_TSFT1_HCI))
+#define BIT_GET_TSFT1_HCI(x) (((x) >> BIT_SHIFT_TSFT1_HCI) & BIT_MASK_TSFT1_HCI)
+#define BIT_SET_TSFT1_HCI(x, v) (BIT_CLEAR_TSFT1_HCI(x) | BIT_TSFT1_HCI(v))
-/* 2 REG_HCI_HRPWM1_V1 (Offset 0x03D9) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_HCI_HRPWM 0
-#define BIT_MASK_HCI_HRPWM 0xff
-#define BIT_HCI_HRPWM(x) (((x) & BIT_MASK_HCI_HRPWM) << BIT_SHIFT_HCI_HRPWM)
-#define BIT_GET_HCI_HRPWM(x) (((x) >> BIT_SHIFT_HCI_HRPWM) & BIT_MASK_HCI_HRPWM)
+/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+#define BIT_CLR_RXQ_HOST_IDX BIT(0)
#endif
+#if (HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */
+#define BIT_RXDOK BIT(0)
+#define BIT_RXDOKM BIT(0)
+#define BIT_EN_DBG_STUCK BIT(0)
-/* 2 REG_PCIE_HCPWM1_V1 (Offset 0x03DA) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_PCIE_HCPWM 0
-#define BIT_MASK_PCIE_HCPWM 0xff
-#define BIT_PCIE_HCPWM(x) (((x) & BIT_MASK_PCIE_HCPWM) << BIT_SHIFT_PCIE_HCPWM)
-#define BIT_GET_PCIE_HCPWM(x) (((x) >> BIT_SHIFT_PCIE_HCPWM) & BIT_MASK_PCIE_HCPWM)
+/* 2 REG_VOQ_TXBD_IDX (Offset 0x03A0) */
+#define BIT_SHIFT_VOQ_HW_IDX 16
+#define BIT_MASK_VOQ_HW_IDX 0xfff
+#define BIT_VOQ_HW_IDX(x) (((x) & BIT_MASK_VOQ_HW_IDX) << BIT_SHIFT_VOQ_HW_IDX)
+#define BITS_VOQ_HW_IDX (BIT_MASK_VOQ_HW_IDX << BIT_SHIFT_VOQ_HW_IDX)
+#define BIT_CLEAR_VOQ_HW_IDX(x) ((x) & (~BITS_VOQ_HW_IDX))
+#define BIT_GET_VOQ_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_VOQ_HW_IDX) & BIT_MASK_VOQ_HW_IDX)
+#define BIT_SET_VOQ_HW_IDX(x, v) (BIT_CLEAR_VOQ_HW_IDX(x) | BIT_VOQ_HW_IDX(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_ACH0_TXBD_IDX (Offset 0x03A0) */
+#define BIT_SHIFT_ACH0_HW_IDX 16
+#define BIT_MASK_ACH0_HW_IDX 0xfff
+#define BIT_ACH0_HW_IDX(x) \
+ (((x) & BIT_MASK_ACH0_HW_IDX) << BIT_SHIFT_ACH0_HW_IDX)
+#define BITS_ACH0_HW_IDX (BIT_MASK_ACH0_HW_IDX << BIT_SHIFT_ACH0_HW_IDX)
+#define BIT_CLEAR_ACH0_HW_IDX(x) ((x) & (~BITS_ACH0_HW_IDX))
+#define BIT_GET_ACH0_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_ACH0_HW_IDX) & BIT_MASK_ACH0_HW_IDX)
+#define BIT_SET_ACH0_HW_IDX(x, v) \
+ (BIT_CLEAR_ACH0_HW_IDX(x) | BIT_ACH0_HW_IDX(v))
-/* 2 REG_HCI_HCPWM1_V1 (Offset 0x03DA) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_HCI_HCPWM 0
-#define BIT_MASK_HCI_HCPWM 0xff
-#define BIT_HCI_HCPWM(x) (((x) & BIT_MASK_HCI_HCPWM) << BIT_SHIFT_HCI_HCPWM)
-#define BIT_GET_HCI_HCPWM(x) (((x) >> BIT_SHIFT_HCI_HCPWM) & BIT_MASK_HCI_HCPWM)
+/* 2 REG_VOQ_TXBD_IDX (Offset 0x03A0) */
+#define BIT_SHIFT_VOQ_HOST_IDX 0
+#define BIT_MASK_VOQ_HOST_IDX 0xfff
+#define BIT_VOQ_HOST_IDX(x) \
+ (((x) & BIT_MASK_VOQ_HOST_IDX) << BIT_SHIFT_VOQ_HOST_IDX)
+#define BITS_VOQ_HOST_IDX (BIT_MASK_VOQ_HOST_IDX << BIT_SHIFT_VOQ_HOST_IDX)
+#define BIT_CLEAR_VOQ_HOST_IDX(x) ((x) & (~BITS_VOQ_HOST_IDX))
+#define BIT_GET_VOQ_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_VOQ_HOST_IDX) & BIT_MASK_VOQ_HOST_IDX)
+#define BIT_SET_VOQ_HOST_IDX(x, v) \
+ (BIT_CLEAR_VOQ_HOST_IDX(x) | BIT_VOQ_HOST_IDX(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ACH0_TXBD_IDX (Offset 0x03A0) */
+#define BIT_SHIFT_ACH0_HOST_IDX 0
+#define BIT_MASK_ACH0_HOST_IDX 0xfff
+#define BIT_ACH0_HOST_IDX(x) \
+ (((x) & BIT_MASK_ACH0_HOST_IDX) << BIT_SHIFT_ACH0_HOST_IDX)
+#define BITS_ACH0_HOST_IDX (BIT_MASK_ACH0_HOST_IDX << BIT_SHIFT_ACH0_HOST_IDX)
+#define BIT_CLEAR_ACH0_HOST_IDX(x) ((x) & (~BITS_ACH0_HOST_IDX))
+#define BIT_GET_ACH0_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_ACH0_HOST_IDX) & BIT_MASK_ACH0_HOST_IDX)
+#define BIT_SET_ACH0_HOST_IDX(x, v) \
+ (BIT_CLEAR_ACH0_HOST_IDX(x) | BIT_ACH0_HOST_IDX(v))
-/* 2 REG_PCIE_CTRL2 (Offset 0x03DB) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_HPS_CLKR_PCIE 4
-#define BIT_MASK_HPS_CLKR_PCIE 0x3
-#define BIT_HPS_CLKR_PCIE(x) (((x) & BIT_MASK_HPS_CLKR_PCIE) << BIT_SHIFT_HPS_CLKR_PCIE)
-#define BIT_GET_HPS_CLKR_PCIE(x) (((x) >> BIT_SHIFT_HPS_CLKR_PCIE) & BIT_MASK_HPS_CLKR_PCIE)
+/* 2 REG_VIQ_TXBD_IDX (Offset 0x03A4) */
+#define BIT_SHIFT_VIQ_HW_IDX 16
+#define BIT_MASK_VIQ_HW_IDX 0xfff
+#define BIT_VIQ_HW_IDX(x) (((x) & BIT_MASK_VIQ_HW_IDX) << BIT_SHIFT_VIQ_HW_IDX)
+#define BITS_VIQ_HW_IDX (BIT_MASK_VIQ_HW_IDX << BIT_SHIFT_VIQ_HW_IDX)
+#define BIT_CLEAR_VIQ_HW_IDX(x) ((x) & (~BITS_VIQ_HW_IDX))
+#define BIT_GET_VIQ_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_VIQ_HW_IDX) & BIT_MASK_VIQ_HW_IDX)
+#define BIT_SET_VIQ_HW_IDX(x, v) (BIT_CLEAR_VIQ_HW_IDX(x) | BIT_VIQ_HW_IDX(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_ACH1_TXBD_IDX (Offset 0x03A4) */
+#define BIT_SHIFT_ACH1_HW_IDX 16
+#define BIT_MASK_ACH1_HW_IDX 0xfff
+#define BIT_ACH1_HW_IDX(x) \
+ (((x) & BIT_MASK_ACH1_HW_IDX) << BIT_SHIFT_ACH1_HW_IDX)
+#define BITS_ACH1_HW_IDX (BIT_MASK_ACH1_HW_IDX << BIT_SHIFT_ACH1_HW_IDX)
+#define BIT_CLEAR_ACH1_HW_IDX(x) ((x) & (~BITS_ACH1_HW_IDX))
+#define BIT_GET_ACH1_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_ACH1_HW_IDX) & BIT_MASK_ACH1_HW_IDX)
+#define BIT_SET_ACH1_HW_IDX(x, v) \
+ (BIT_CLEAR_ACH1_HW_IDX(x) | BIT_ACH1_HW_IDX(v))
-/* 2 REG_HCI_CTRL2 (Offset 0x03DB) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_HPS_CLKR_HCI 4
-#define BIT_MASK_HPS_CLKR_HCI 0x3
-#define BIT_HPS_CLKR_HCI(x) (((x) & BIT_MASK_HPS_CLKR_HCI) << BIT_SHIFT_HPS_CLKR_HCI)
-#define BIT_GET_HPS_CLKR_HCI(x) (((x) >> BIT_SHIFT_HPS_CLKR_HCI) & BIT_MASK_HPS_CLKR_HCI)
+/* 2 REG_VIQ_TXBD_IDX (Offset 0x03A4) */
+#define BIT_SHIFT_VIQ_HOST_IDX 0
+#define BIT_MASK_VIQ_HOST_IDX 0xfff
+#define BIT_VIQ_HOST_IDX(x) \
+ (((x) & BIT_MASK_VIQ_HOST_IDX) << BIT_SHIFT_VIQ_HOST_IDX)
+#define BITS_VIQ_HOST_IDX (BIT_MASK_VIQ_HOST_IDX << BIT_SHIFT_VIQ_HOST_IDX)
+#define BIT_CLEAR_VIQ_HOST_IDX(x) ((x) & (~BITS_VIQ_HOST_IDX))
+#define BIT_GET_VIQ_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_VIQ_HOST_IDX) & BIT_MASK_VIQ_HOST_IDX)
+#define BIT_SET_VIQ_HOST_IDX(x, v) \
+ (BIT_CLEAR_VIQ_HOST_IDX(x) | BIT_VIQ_HOST_IDX(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_PCIE_CTRL2 (Offset 0x03DB) */
+/* 2 REG_ACH1_TXBD_IDX (Offset 0x03A4) */
-#define BIT_PCIE_INT BIT(3)
+#define BIT_SHIFT_ACH1_HOST_IDX 0
+#define BIT_MASK_ACH1_HOST_IDX 0xfff
+#define BIT_ACH1_HOST_IDX(x) \
+ (((x) & BIT_MASK_ACH1_HOST_IDX) << BIT_SHIFT_ACH1_HOST_IDX)
+#define BITS_ACH1_HOST_IDX (BIT_MASK_ACH1_HOST_IDX << BIT_SHIFT_ACH1_HOST_IDX)
+#define BIT_CLEAR_ACH1_HOST_IDX(x) ((x) & (~BITS_ACH1_HOST_IDX))
+#define BIT_GET_ACH1_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_ACH1_HOST_IDX) & BIT_MASK_ACH1_HOST_IDX)
+#define BIT_SET_ACH1_HOST_IDX(x, v) \
+ (BIT_CLEAR_ACH1_HOST_IDX(x) | BIT_ACH1_HOST_IDX(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_BEQ_TXBD_IDX (Offset 0x03A8) */
+#define BIT_SHIFT_BEQ_HW_IDX 16
+#define BIT_MASK_BEQ_HW_IDX 0xfff
+#define BIT_BEQ_HW_IDX(x) (((x) & BIT_MASK_BEQ_HW_IDX) << BIT_SHIFT_BEQ_HW_IDX)
+#define BITS_BEQ_HW_IDX (BIT_MASK_BEQ_HW_IDX << BIT_SHIFT_BEQ_HW_IDX)
+#define BIT_CLEAR_BEQ_HW_IDX(x) ((x) & (~BITS_BEQ_HW_IDX))
+#define BIT_GET_BEQ_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_BEQ_HW_IDX) & BIT_MASK_BEQ_HW_IDX)
+#define BIT_SET_BEQ_HW_IDX(x, v) (BIT_CLEAR_BEQ_HW_IDX(x) | BIT_BEQ_HW_IDX(v))
-/* 2 REG_HCI_CTRL2 (Offset 0x03DB) */
+#endif
-#define BIT_HCI_INT BIT(3)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_ACH2_TXBD_IDX (Offset 0x03A8) */
+#define BIT_SHIFT_ACH2_HW_IDX 16
+#define BIT_MASK_ACH2_HW_IDX 0xfff
+#define BIT_ACH2_HW_IDX(x) \
+ (((x) & BIT_MASK_ACH2_HW_IDX) << BIT_SHIFT_ACH2_HW_IDX)
+#define BITS_ACH2_HW_IDX (BIT_MASK_ACH2_HW_IDX << BIT_SHIFT_ACH2_HW_IDX)
+#define BIT_CLEAR_ACH2_HW_IDX(x) ((x) & (~BITS_ACH2_HW_IDX))
+#define BIT_GET_ACH2_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_ACH2_HW_IDX) & BIT_MASK_ACH2_HW_IDX)
+#define BIT_SET_ACH2_HW_IDX(x, v) \
+ (BIT_CLEAR_ACH2_HW_IDX(x) | BIT_ACH2_HW_IDX(v))
-#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_PCIE_CTRL2 (Offset 0x03DB) */
+/* 2 REG_BEQ_TXBD_IDX (Offset 0x03A8) */
-#define BIT_EN_RXDMA_ALIGN BIT(1)
-#define BIT_EN_TXDMA_ALIGN BIT(0)
+#define BIT_SHIFT_BEQ_HOST_IDX 0
+#define BIT_MASK_BEQ_HOST_IDX 0xfff
+#define BIT_BEQ_HOST_IDX(x) \
+ (((x) & BIT_MASK_BEQ_HOST_IDX) << BIT_SHIFT_BEQ_HOST_IDX)
+#define BITS_BEQ_HOST_IDX (BIT_MASK_BEQ_HOST_IDX << BIT_SHIFT_BEQ_HOST_IDX)
+#define BIT_CLEAR_BEQ_HOST_IDX(x) ((x) & (~BITS_BEQ_HOST_IDX))
+#define BIT_GET_BEQ_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_BEQ_HOST_IDX) & BIT_MASK_BEQ_HOST_IDX)
+#define BIT_SET_BEQ_HOST_IDX(x, v) \
+ (BIT_CLEAR_BEQ_HOST_IDX(x) | BIT_BEQ_HOST_IDX(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_ACH2_TXBD_IDX (Offset 0x03A8) */
+#define BIT_SHIFT_ACH2_HOST_IDX 0
+#define BIT_MASK_ACH2_HOST_IDX 0xfff
+#define BIT_ACH2_HOST_IDX(x) \
+ (((x) & BIT_MASK_ACH2_HOST_IDX) << BIT_SHIFT_ACH2_HOST_IDX)
+#define BITS_ACH2_HOST_IDX (BIT_MASK_ACH2_HOST_IDX << BIT_SHIFT_ACH2_HOST_IDX)
+#define BIT_CLEAR_ACH2_HOST_IDX(x) ((x) & (~BITS_ACH2_HOST_IDX))
+#define BIT_GET_ACH2_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_ACH2_HOST_IDX) & BIT_MASK_ACH2_HOST_IDX)
+#define BIT_SET_ACH2_HOST_IDX(x, v) \
+ (BIT_CLEAR_ACH2_HOST_IDX(x) | BIT_ACH2_HOST_IDX(v))
-/* 2 REG_PCIE_HRPWM2_V1 (Offset 0x03DC) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_PCIE_HRPWM2 0
-#define BIT_MASK_PCIE_HRPWM2 0xffff
-#define BIT_PCIE_HRPWM2(x) (((x) & BIT_MASK_PCIE_HRPWM2) << BIT_SHIFT_PCIE_HRPWM2)
-#define BIT_GET_PCIE_HRPWM2(x) (((x) >> BIT_SHIFT_PCIE_HRPWM2) & BIT_MASK_PCIE_HRPWM2)
+/* 2 REG_BKQ_TXBD_IDX (Offset 0x03AC) */
+#define BIT_SHIFT_BKQ_HW_IDX 16
+#define BIT_MASK_BKQ_HW_IDX 0xfff
+#define BIT_BKQ_HW_IDX(x) (((x) & BIT_MASK_BKQ_HW_IDX) << BIT_SHIFT_BKQ_HW_IDX)
+#define BITS_BKQ_HW_IDX (BIT_MASK_BKQ_HW_IDX << BIT_SHIFT_BKQ_HW_IDX)
+#define BIT_CLEAR_BKQ_HW_IDX(x) ((x) & (~BITS_BKQ_HW_IDX))
+#define BIT_GET_BKQ_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_BKQ_HW_IDX) & BIT_MASK_BKQ_HW_IDX)
+#define BIT_SET_BKQ_HW_IDX(x, v) (BIT_CLEAR_BKQ_HW_IDX(x) | BIT_BKQ_HW_IDX(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_ACH3_TXBD_IDX (Offset 0x03AC) */
+#define BIT_SHIFT_ACH3_HW_IDX 16
+#define BIT_MASK_ACH3_HW_IDX 0xfff
+#define BIT_ACH3_HW_IDX(x) \
+ (((x) & BIT_MASK_ACH3_HW_IDX) << BIT_SHIFT_ACH3_HW_IDX)
+#define BITS_ACH3_HW_IDX (BIT_MASK_ACH3_HW_IDX << BIT_SHIFT_ACH3_HW_IDX)
+#define BIT_CLEAR_ACH3_HW_IDX(x) ((x) & (~BITS_ACH3_HW_IDX))
+#define BIT_GET_ACH3_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_ACH3_HW_IDX) & BIT_MASK_ACH3_HW_IDX)
+#define BIT_SET_ACH3_HW_IDX(x, v) \
+ (BIT_CLEAR_ACH3_HW_IDX(x) | BIT_ACH3_HW_IDX(v))
-/* 2 REG_HCI_HRPWM2_V1 (Offset 0x03DC) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_HCI_HRPWM2 0
-#define BIT_MASK_HCI_HRPWM2 0xffff
-#define BIT_HCI_HRPWM2(x) (((x) & BIT_MASK_HCI_HRPWM2) << BIT_SHIFT_HCI_HRPWM2)
-#define BIT_GET_HCI_HRPWM2(x) (((x) >> BIT_SHIFT_HCI_HRPWM2) & BIT_MASK_HCI_HRPWM2)
+/* 2 REG_BKQ_TXBD_IDX (Offset 0x03AC) */
+#define BIT_SHIFT_BKQ_HOST_IDX 0
+#define BIT_MASK_BKQ_HOST_IDX 0xfff
+#define BIT_BKQ_HOST_IDX(x) \
+ (((x) & BIT_MASK_BKQ_HOST_IDX) << BIT_SHIFT_BKQ_HOST_IDX)
+#define BITS_BKQ_HOST_IDX (BIT_MASK_BKQ_HOST_IDX << BIT_SHIFT_BKQ_HOST_IDX)
+#define BIT_CLEAR_BKQ_HOST_IDX(x) ((x) & (~BITS_BKQ_HOST_IDX))
+#define BIT_GET_BKQ_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_BKQ_HOST_IDX) & BIT_MASK_BKQ_HOST_IDX)
+#define BIT_SET_BKQ_HOST_IDX(x, v) \
+ (BIT_CLEAR_BKQ_HOST_IDX(x) | BIT_BKQ_HOST_IDX(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_ACH3_TXBD_IDX (Offset 0x03AC) */
+#define BIT_SHIFT_ACH3_HOST_IDX 0
+#define BIT_MASK_ACH3_HOST_IDX 0xfff
+#define BIT_ACH3_HOST_IDX(x) \
+ (((x) & BIT_MASK_ACH3_HOST_IDX) << BIT_SHIFT_ACH3_HOST_IDX)
+#define BITS_ACH3_HOST_IDX (BIT_MASK_ACH3_HOST_IDX << BIT_SHIFT_ACH3_HOST_IDX)
+#define BIT_CLEAR_ACH3_HOST_IDX(x) ((x) & (~BITS_ACH3_HOST_IDX))
+#define BIT_GET_ACH3_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_ACH3_HOST_IDX) & BIT_MASK_ACH3_HOST_IDX)
+#define BIT_SET_ACH3_HOST_IDX(x, v) \
+ (BIT_CLEAR_ACH3_HOST_IDX(x) | BIT_ACH3_HOST_IDX(v))
-/* 2 REG_PCIE_HCPWM2_V1 (Offset 0x03DE) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_PCIE_HCPWM2 0
-#define BIT_MASK_PCIE_HCPWM2 0xffff
-#define BIT_PCIE_HCPWM2(x) (((x) & BIT_MASK_PCIE_HCPWM2) << BIT_SHIFT_PCIE_HCPWM2)
-#define BIT_GET_PCIE_HCPWM2(x) (((x) >> BIT_SHIFT_PCIE_HCPWM2) & BIT_MASK_PCIE_HCPWM2)
+/* 2 REG_MGQ_TXBD_IDX (Offset 0x03B0) */
+#define BIT_SHIFT_MGQ_HW_IDX 16
+#define BIT_MASK_MGQ_HW_IDX 0xfff
+#define BIT_MGQ_HW_IDX(x) (((x) & BIT_MASK_MGQ_HW_IDX) << BIT_SHIFT_MGQ_HW_IDX)
+#define BITS_MGQ_HW_IDX (BIT_MASK_MGQ_HW_IDX << BIT_SHIFT_MGQ_HW_IDX)
+#define BIT_CLEAR_MGQ_HW_IDX(x) ((x) & (~BITS_MGQ_HW_IDX))
+#define BIT_GET_MGQ_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_MGQ_HW_IDX) & BIT_MASK_MGQ_HW_IDX)
+#define BIT_SET_MGQ_HW_IDX(x, v) (BIT_CLEAR_MGQ_HW_IDX(x) | BIT_MGQ_HW_IDX(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_P0MGQ_TXBD_IDX (Offset 0x03B0) */
+#define BIT_SHIFT_P0MGQ_HW_IDX 16
+#define BIT_MASK_P0MGQ_HW_IDX 0xfff
+#define BIT_P0MGQ_HW_IDX(x) \
+ (((x) & BIT_MASK_P0MGQ_HW_IDX) << BIT_SHIFT_P0MGQ_HW_IDX)
+#define BITS_P0MGQ_HW_IDX (BIT_MASK_P0MGQ_HW_IDX << BIT_SHIFT_P0MGQ_HW_IDX)
+#define BIT_CLEAR_P0MGQ_HW_IDX(x) ((x) & (~BITS_P0MGQ_HW_IDX))
+#define BIT_GET_P0MGQ_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_P0MGQ_HW_IDX) & BIT_MASK_P0MGQ_HW_IDX)
+#define BIT_SET_P0MGQ_HW_IDX(x, v) \
+ (BIT_CLEAR_P0MGQ_HW_IDX(x) | BIT_P0MGQ_HW_IDX(v))
-/* 2 REG_HCI_HCPWM2_V1 (Offset 0x03DE) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_HCI_HCPWM2 0
-#define BIT_MASK_HCI_HCPWM2 0xffff
-#define BIT_HCI_HCPWM2(x) (((x) & BIT_MASK_HCI_HCPWM2) << BIT_SHIFT_HCI_HCPWM2)
-#define BIT_GET_HCI_HCPWM2(x) (((x) >> BIT_SHIFT_HCI_HCPWM2) & BIT_MASK_HCI_HCPWM2)
+/* 2 REG_MGQ_TXBD_IDX (Offset 0x03B0) */
+#define BIT_SHIFT_MGQ_HOST_IDX 0
+#define BIT_MASK_MGQ_HOST_IDX 0xfff
+#define BIT_MGQ_HOST_IDX(x) \
+ (((x) & BIT_MASK_MGQ_HOST_IDX) << BIT_SHIFT_MGQ_HOST_IDX)
+#define BITS_MGQ_HOST_IDX (BIT_MASK_MGQ_HOST_IDX << BIT_SHIFT_MGQ_HOST_IDX)
+#define BIT_CLEAR_MGQ_HOST_IDX(x) ((x) & (~BITS_MGQ_HOST_IDX))
+#define BIT_GET_MGQ_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_MGQ_HOST_IDX) & BIT_MASK_MGQ_HOST_IDX)
+#define BIT_SET_MGQ_HOST_IDX(x, v) \
+ (BIT_CLEAR_MGQ_HOST_IDX(x) | BIT_MGQ_HOST_IDX(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_P0MGQ_TXBD_IDX (Offset 0x03B0) */
+#define BIT_SHIFT_P0MGQ_HOST_IDX 0
+#define BIT_MASK_P0MGQ_HOST_IDX 0xfff
+#define BIT_P0MGQ_HOST_IDX(x) \
+ (((x) & BIT_MASK_P0MGQ_HOST_IDX) << BIT_SHIFT_P0MGQ_HOST_IDX)
+#define BITS_P0MGQ_HOST_IDX \
+ (BIT_MASK_P0MGQ_HOST_IDX << BIT_SHIFT_P0MGQ_HOST_IDX)
+#define BIT_CLEAR_P0MGQ_HOST_IDX(x) ((x) & (~BITS_P0MGQ_HOST_IDX))
+#define BIT_GET_P0MGQ_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_P0MGQ_HOST_IDX) & BIT_MASK_P0MGQ_HOST_IDX)
+#define BIT_SET_P0MGQ_HOST_IDX(x, v) \
+ (BIT_CLEAR_P0MGQ_HOST_IDX(x) | BIT_P0MGQ_HOST_IDX(v))
-/* 2 REG_PCIE_H2C_MSG_V1 (Offset 0x03E0) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_DRV2FW_INFO 0
-#define BIT_MASK_DRV2FW_INFO 0xffffffffL
-#define BIT_DRV2FW_INFO(x) (((x) & BIT_MASK_DRV2FW_INFO) << BIT_SHIFT_DRV2FW_INFO)
-#define BIT_GET_DRV2FW_INFO(x) (((x) >> BIT_SHIFT_DRV2FW_INFO) & BIT_MASK_DRV2FW_INFO)
+/* 2 REG_RXQ_RXBD_IDX (Offset 0x03B4) */
+#define BIT_SHIFT_RXQ_HW_IDX 16
+#define BIT_MASK_RXQ_HW_IDX 0xfff
+#define BIT_RXQ_HW_IDX(x) (((x) & BIT_MASK_RXQ_HW_IDX) << BIT_SHIFT_RXQ_HW_IDX)
+#define BITS_RXQ_HW_IDX (BIT_MASK_RXQ_HW_IDX << BIT_SHIFT_RXQ_HW_IDX)
+#define BIT_CLEAR_RXQ_HW_IDX(x) ((x) & (~BITS_RXQ_HW_IDX))
+#define BIT_GET_RXQ_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_RXQ_HW_IDX) & BIT_MASK_RXQ_HW_IDX)
+#define BIT_SET_RXQ_HW_IDX(x, v) (BIT_CLEAR_RXQ_HW_IDX(x) | BIT_RXQ_HW_IDX(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_P0RXQ_RXBD_IDX (Offset 0x03B4) */
+#define BIT_SHIFT_P0RXQ_HW_IDX 16
+#define BIT_MASK_P0RXQ_HW_IDX 0xfff
+#define BIT_P0RXQ_HW_IDX(x) \
+ (((x) & BIT_MASK_P0RXQ_HW_IDX) << BIT_SHIFT_P0RXQ_HW_IDX)
+#define BITS_P0RXQ_HW_IDX (BIT_MASK_P0RXQ_HW_IDX << BIT_SHIFT_P0RXQ_HW_IDX)
+#define BIT_CLEAR_P0RXQ_HW_IDX(x) ((x) & (~BITS_P0RXQ_HW_IDX))
+#define BIT_GET_P0RXQ_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_P0RXQ_HW_IDX) & BIT_MASK_P0RXQ_HW_IDX)
+#define BIT_SET_P0RXQ_HW_IDX(x, v) \
+ (BIT_CLEAR_P0RXQ_HW_IDX(x) | BIT_P0RXQ_HW_IDX(v))
-/* 2 REG_PCIE_C2H_MSG_V1 (Offset 0x03E4) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_HCI_PCIE_C2H_MSG 0
-#define BIT_MASK_HCI_PCIE_C2H_MSG 0xffffffffL
-#define BIT_HCI_PCIE_C2H_MSG(x) (((x) & BIT_MASK_HCI_PCIE_C2H_MSG) << BIT_SHIFT_HCI_PCIE_C2H_MSG)
-#define BIT_GET_HCI_PCIE_C2H_MSG(x) (((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG) & BIT_MASK_HCI_PCIE_C2H_MSG)
+/* 2 REG_RXQ_RXBD_IDX (Offset 0x03B4) */
+#define BIT_SHIFT_RXQ_HOST_IDX 0
+#define BIT_MASK_RXQ_HOST_IDX 0xfff
+#define BIT_RXQ_HOST_IDX(x) \
+ (((x) & BIT_MASK_RXQ_HOST_IDX) << BIT_SHIFT_RXQ_HOST_IDX)
+#define BITS_RXQ_HOST_IDX (BIT_MASK_RXQ_HOST_IDX << BIT_SHIFT_RXQ_HOST_IDX)
+#define BIT_CLEAR_RXQ_HOST_IDX(x) ((x) & (~BITS_RXQ_HOST_IDX))
+#define BIT_GET_RXQ_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_RXQ_HOST_IDX) & BIT_MASK_RXQ_HOST_IDX)
+#define BIT_SET_RXQ_HOST_IDX(x, v) \
+ (BIT_CLEAR_RXQ_HOST_IDX(x) | BIT_RXQ_HOST_IDX(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_P0RXQ_RXBD_IDX (Offset 0x03B4) */
+#define BIT_SHIFT_P0RXQ_HOST_IDX 0
+#define BIT_MASK_P0RXQ_HOST_IDX 0xfff
+#define BIT_P0RXQ_HOST_IDX(x) \
+ (((x) & BIT_MASK_P0RXQ_HOST_IDX) << BIT_SHIFT_P0RXQ_HOST_IDX)
+#define BITS_P0RXQ_HOST_IDX \
+ (BIT_MASK_P0RXQ_HOST_IDX << BIT_SHIFT_P0RXQ_HOST_IDX)
+#define BIT_CLEAR_P0RXQ_HOST_IDX(x) ((x) & (~BITS_P0RXQ_HOST_IDX))
+#define BIT_GET_P0RXQ_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_P0RXQ_HOST_IDX) & BIT_MASK_P0RXQ_HOST_IDX)
+#define BIT_SET_P0RXQ_HOST_IDX(x, v) \
+ (BIT_CLEAR_P0RXQ_HOST_IDX(x) | BIT_P0RXQ_HOST_IDX(v))
-/* 2 REG_HCI_C2H_MSG_V1 (Offset 0x03E4) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_HCI_C2H_MSG 0
-#define BIT_MASK_HCI_C2H_MSG 0xffffffffL
-#define BIT_HCI_C2H_MSG(x) (((x) & BIT_MASK_HCI_C2H_MSG) << BIT_SHIFT_HCI_C2H_MSG)
-#define BIT_GET_HCI_C2H_MSG(x) (((x) >> BIT_SHIFT_HCI_C2H_MSG) & BIT_MASK_HCI_C2H_MSG)
+/* 2 REG_HI0Q_TXBD_IDX (Offset 0x03B8) */
+#define BIT_SHIFT_HI0Q_HW_IDX 16
+#define BIT_MASK_HI0Q_HW_IDX 0xfff
+#define BIT_HI0Q_HW_IDX(x) \
+ (((x) & BIT_MASK_HI0Q_HW_IDX) << BIT_SHIFT_HI0Q_HW_IDX)
+#define BITS_HI0Q_HW_IDX (BIT_MASK_HI0Q_HW_IDX << BIT_SHIFT_HI0Q_HW_IDX)
+#define BIT_CLEAR_HI0Q_HW_IDX(x) ((x) & (~BITS_HI0Q_HW_IDX))
+#define BIT_GET_HI0Q_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_HI0Q_HW_IDX) & BIT_MASK_HI0Q_HW_IDX)
+#define BIT_SET_HI0Q_HW_IDX(x, v) \
+ (BIT_CLEAR_HI0Q_HW_IDX(x) | BIT_HI0Q_HW_IDX(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_DBI_WDATA_V1 (Offset 0x03E8) */
+/* 2 REG_P0HI0Q_TXBD_IDX (Offset 0x03B8) */
+#define BIT_SHIFT_P0HI0Q_HW_IDX 16
+#define BIT_MASK_P0HI0Q_HW_IDX 0xfff
+#define BIT_P0HI0Q_HW_IDX(x) \
+ (((x) & BIT_MASK_P0HI0Q_HW_IDX) << BIT_SHIFT_P0HI0Q_HW_IDX)
+#define BITS_P0HI0Q_HW_IDX (BIT_MASK_P0HI0Q_HW_IDX << BIT_SHIFT_P0HI0Q_HW_IDX)
+#define BIT_CLEAR_P0HI0Q_HW_IDX(x) ((x) & (~BITS_P0HI0Q_HW_IDX))
+#define BIT_GET_P0HI0Q_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI0Q_HW_IDX) & BIT_MASK_P0HI0Q_HW_IDX)
+#define BIT_SET_P0HI0Q_HW_IDX(x, v) \
+ (BIT_CLEAR_P0HI0Q_HW_IDX(x) | BIT_P0HI0Q_HW_IDX(v))
-#define BIT_SHIFT_DBI_WDATA 0
-#define BIT_MASK_DBI_WDATA 0xffffffffL
-#define BIT_DBI_WDATA(x) (((x) & BIT_MASK_DBI_WDATA) << BIT_SHIFT_DBI_WDATA)
-#define BIT_GET_DBI_WDATA(x) (((x) >> BIT_SHIFT_DBI_WDATA) & BIT_MASK_DBI_WDATA)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_DBI_RDATA_V1 (Offset 0x03EC) */
+/* 2 REG_HI0Q_TXBD_IDX (Offset 0x03B8) */
+#define BIT_SHIFT_HI0Q_HOST_IDX 0
+#define BIT_MASK_HI0Q_HOST_IDX 0xfff
+#define BIT_HI0Q_HOST_IDX(x) \
+ (((x) & BIT_MASK_HI0Q_HOST_IDX) << BIT_SHIFT_HI0Q_HOST_IDX)
+#define BITS_HI0Q_HOST_IDX (BIT_MASK_HI0Q_HOST_IDX << BIT_SHIFT_HI0Q_HOST_IDX)
+#define BIT_CLEAR_HI0Q_HOST_IDX(x) ((x) & (~BITS_HI0Q_HOST_IDX))
+#define BIT_GET_HI0Q_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_HI0Q_HOST_IDX) & BIT_MASK_HI0Q_HOST_IDX)
+#define BIT_SET_HI0Q_HOST_IDX(x, v) \
+ (BIT_CLEAR_HI0Q_HOST_IDX(x) | BIT_HI0Q_HOST_IDX(v))
-#define BIT_SHIFT_DBI_RDATA 0
-#define BIT_MASK_DBI_RDATA 0xffffffffL
-#define BIT_DBI_RDATA(x) (((x) & BIT_MASK_DBI_RDATA) << BIT_SHIFT_DBI_RDATA)
-#define BIT_GET_DBI_RDATA(x) (((x) >> BIT_SHIFT_DBI_RDATA) & BIT_MASK_DBI_RDATA)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_DBI_FLAG_V1 (Offset 0x03F0) */
+/* 2 REG_P0HI0Q_TXBD_IDX (Offset 0x03B8) */
-#define BIT_EN_STUCK_DBG BIT(26)
-#define BIT_RX_STUCK BIT(25)
-#define BIT_TX_STUCK BIT(24)
-#define BIT_DBI_RFLAG BIT(17)
-#define BIT_DBI_WFLAG BIT(16)
+#define BIT_SHIFT_P0HI0Q_HOST_IDX 0
+#define BIT_MASK_P0HI0Q_HOST_IDX 0xfff
+#define BIT_P0HI0Q_HOST_IDX(x) \
+ (((x) & BIT_MASK_P0HI0Q_HOST_IDX) << BIT_SHIFT_P0HI0Q_HOST_IDX)
+#define BITS_P0HI0Q_HOST_IDX \
+ (BIT_MASK_P0HI0Q_HOST_IDX << BIT_SHIFT_P0HI0Q_HOST_IDX)
+#define BIT_CLEAR_P0HI0Q_HOST_IDX(x) ((x) & (~BITS_P0HI0Q_HOST_IDX))
+#define BIT_GET_P0HI0Q_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI0Q_HOST_IDX) & BIT_MASK_P0HI0Q_HOST_IDX)
+#define BIT_SET_P0HI0Q_HOST_IDX(x, v) \
+ (BIT_CLEAR_P0HI0Q_HOST_IDX(x) | BIT_P0HI0Q_HOST_IDX(v))
-#define BIT_SHIFT_DBI_WREN 12
-#define BIT_MASK_DBI_WREN 0xf
-#define BIT_DBI_WREN(x) (((x) & BIT_MASK_DBI_WREN) << BIT_SHIFT_DBI_WREN)
-#define BIT_GET_DBI_WREN(x) (((x) >> BIT_SHIFT_DBI_WREN) & BIT_MASK_DBI_WREN)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_DBI_ADDR 0
-#define BIT_MASK_DBI_ADDR 0xfff
-#define BIT_DBI_ADDR(x) (((x) & BIT_MASK_DBI_ADDR) << BIT_SHIFT_DBI_ADDR)
-#define BIT_GET_DBI_ADDR(x) (((x) >> BIT_SHIFT_DBI_ADDR) & BIT_MASK_DBI_ADDR)
+/* 2 REG_HI1Q_TXBD_IDX (Offset 0x03BC) */
+#define BIT_SHIFT_HI1Q_HW_IDX 16
+#define BIT_MASK_HI1Q_HW_IDX 0xfff
+#define BIT_HI1Q_HW_IDX(x) \
+ (((x) & BIT_MASK_HI1Q_HW_IDX) << BIT_SHIFT_HI1Q_HW_IDX)
+#define BITS_HI1Q_HW_IDX (BIT_MASK_HI1Q_HW_IDX << BIT_SHIFT_HI1Q_HW_IDX)
+#define BIT_CLEAR_HI1Q_HW_IDX(x) ((x) & (~BITS_HI1Q_HW_IDX))
+#define BIT_GET_HI1Q_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_HI1Q_HW_IDX) & BIT_MASK_HI1Q_HW_IDX)
+#define BIT_SET_HI1Q_HW_IDX(x, v) \
+ (BIT_CLEAR_HI1Q_HW_IDX(x) | BIT_HI1Q_HW_IDX(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT)
+/* 2 REG_P0HI1Q_TXBD_IDX (Offset 0x03BC) */
+#define BIT_SHIFT_P0HI1Q_HW_IDX 16
+#define BIT_MASK_P0HI1Q_HW_IDX 0xfff
+#define BIT_P0HI1Q_HW_IDX(x) \
+ (((x) & BIT_MASK_P0HI1Q_HW_IDX) << BIT_SHIFT_P0HI1Q_HW_IDX)
+#define BITS_P0HI1Q_HW_IDX (BIT_MASK_P0HI1Q_HW_IDX << BIT_SHIFT_P0HI1Q_HW_IDX)
+#define BIT_CLEAR_P0HI1Q_HW_IDX(x) ((x) & (~BITS_P0HI1Q_HW_IDX))
+#define BIT_GET_P0HI1Q_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI1Q_HW_IDX) & BIT_MASK_P0HI1Q_HW_IDX)
+#define BIT_SET_P0HI1Q_HW_IDX(x, v) \
+ (BIT_CLEAR_P0HI1Q_HW_IDX(x) | BIT_P0HI1Q_HW_IDX(v))
-/* 2 REG_MDIO_V1 (Offset 0x03F4) */
+#endif
-#define BIT_ECRC_EN BIT(39)
-#define BIT_MDIO_RFLAG BIT(38)
-#define BIT_MDIO_WFLAG BIT(37)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_MDIO_ADDR (32 & CPU_OPT_WIDTH)
-#define BIT_MASK_MDIO_ADDR 0x1f
-#define BIT_MDIO_ADDR(x) (((x) & BIT_MASK_MDIO_ADDR) << BIT_SHIFT_MDIO_ADDR)
-#define BIT_GET_MDIO_ADDR(x) (((x) >> BIT_SHIFT_MDIO_ADDR) & BIT_MASK_MDIO_ADDR)
+/* 2 REG_HI1Q_TXBD_IDX (Offset 0x03BC) */
+#define BIT_SHIFT_HI1Q_HOST_IDX 0
+#define BIT_MASK_HI1Q_HOST_IDX 0xfff
+#define BIT_HI1Q_HOST_IDX(x) \
+ (((x) & BIT_MASK_HI1Q_HOST_IDX) << BIT_SHIFT_HI1Q_HOST_IDX)
+#define BITS_HI1Q_HOST_IDX (BIT_MASK_HI1Q_HOST_IDX << BIT_SHIFT_HI1Q_HOST_IDX)
+#define BIT_CLEAR_HI1Q_HOST_IDX(x) ((x) & (~BITS_HI1Q_HOST_IDX))
+#define BIT_GET_HI1Q_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_HI1Q_HOST_IDX) & BIT_MASK_HI1Q_HOST_IDX)
+#define BIT_SET_HI1Q_HOST_IDX(x, v) \
+ (BIT_CLEAR_HI1Q_HOST_IDX(x) | BIT_HI1Q_HOST_IDX(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_P0HI1Q_TXBD_IDX (Offset 0x03BC) */
+#define BIT_SHIFT_P0HI1Q_HOST_IDX 0
+#define BIT_MASK_P0HI1Q_HOST_IDX 0xfff
+#define BIT_P0HI1Q_HOST_IDX(x) \
+ (((x) & BIT_MASK_P0HI1Q_HOST_IDX) << BIT_SHIFT_P0HI1Q_HOST_IDX)
+#define BITS_P0HI1Q_HOST_IDX \
+ (BIT_MASK_P0HI1Q_HOST_IDX << BIT_SHIFT_P0HI1Q_HOST_IDX)
+#define BIT_CLEAR_P0HI1Q_HOST_IDX(x) ((x) & (~BITS_P0HI1Q_HOST_IDX))
+#define BIT_GET_P0HI1Q_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI1Q_HOST_IDX) & BIT_MASK_P0HI1Q_HOST_IDX)
+#define BIT_SET_P0HI1Q_HOST_IDX(x, v) \
+ (BIT_CLEAR_P0HI1Q_HOST_IDX(x) | BIT_P0HI1Q_HOST_IDX(v))
-/* 2 REG_MDIO_V1 (Offset 0x03F4) */
-
-
-#define BIT_SHIFT_MDIO_RDATA 16
-#define BIT_MASK_MDIO_RDATA 0xffff
-#define BIT_MDIO_RDATA(x) (((x) & BIT_MASK_MDIO_RDATA) << BIT_SHIFT_MDIO_RDATA)
-#define BIT_GET_MDIO_RDATA(x) (((x) >> BIT_SHIFT_MDIO_RDATA) & BIT_MASK_MDIO_RDATA)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_MDIO_WDATA 0
-#define BIT_MASK_MDIO_WDATA 0xffff
-#define BIT_MDIO_WDATA(x) (((x) & BIT_MASK_MDIO_WDATA) << BIT_SHIFT_MDIO_WDATA)
-#define BIT_GET_MDIO_WDATA(x) (((x) >> BIT_SHIFT_MDIO_WDATA) & BIT_MASK_MDIO_WDATA)
+/* 2 REG_HI2Q_TXBD_IDX (Offset 0x03C0) */
+#define BIT_SHIFT_HI2Q_HW_IDX 16
+#define BIT_MASK_HI2Q_HW_IDX 0xfff
+#define BIT_HI2Q_HW_IDX(x) \
+ (((x) & BIT_MASK_HI2Q_HW_IDX) << BIT_SHIFT_HI2Q_HW_IDX)
+#define BITS_HI2Q_HW_IDX (BIT_MASK_HI2Q_HW_IDX << BIT_SHIFT_HI2Q_HW_IDX)
+#define BIT_CLEAR_HI2Q_HW_IDX(x) ((x) & (~BITS_HI2Q_HW_IDX))
+#define BIT_GET_HI2Q_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_HI2Q_HW_IDX) & BIT_MASK_HI2Q_HW_IDX)
+#define BIT_SET_HI2Q_HW_IDX(x, v) \
+ (BIT_CLEAR_HI2Q_HW_IDX(x) | BIT_HI2Q_HW_IDX(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8881A_SUPPORT)
+/* 2 REG_P0HI2Q_TXBD_IDX (Offset 0x03C0) */
+#define BIT_SHIFT_P0HI2Q_HW_IDX 16
+#define BIT_MASK_P0HI2Q_HW_IDX 0xfff
+#define BIT_P0HI2Q_HW_IDX(x) \
+ (((x) & BIT_MASK_P0HI2Q_HW_IDX) << BIT_SHIFT_P0HI2Q_HW_IDX)
+#define BITS_P0HI2Q_HW_IDX (BIT_MASK_P0HI2Q_HW_IDX << BIT_SHIFT_P0HI2Q_HW_IDX)
+#define BIT_CLEAR_P0HI2Q_HW_IDX(x) ((x) & (~BITS_P0HI2Q_HW_IDX))
+#define BIT_GET_P0HI2Q_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI2Q_HW_IDX) & BIT_MASK_P0HI2Q_HW_IDX)
+#define BIT_SET_P0HI2Q_HW_IDX(x, v) \
+ (BIT_CLEAR_P0HI2Q_HW_IDX(x) | BIT_P0HI2Q_HW_IDX(v))
-/* 2 REG_BUS_MIX_CFG (Offset 0x03F8) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_DELAY_TIME 24
-#define BIT_MASK_DELAY_TIME 0xff
-#define BIT_DELAY_TIME(x) (((x) & BIT_MASK_DELAY_TIME) << BIT_SHIFT_DELAY_TIME)
-#define BIT_GET_DELAY_TIME(x) (((x) >> BIT_SHIFT_DELAY_TIME) & BIT_MASK_DELAY_TIME)
+/* 2 REG_HI2Q_TXBD_IDX (Offset 0x03C0) */
-#define BIT_RX_TIMER_DELAY_EN BIT(17)
+#define BIT_SHIFT_HI2Q_HOST_IDX 0
+#define BIT_MASK_HI2Q_HOST_IDX 0xfff
+#define BIT_HI2Q_HOST_IDX(x) \
+ (((x) & BIT_MASK_HI2Q_HOST_IDX) << BIT_SHIFT_HI2Q_HOST_IDX)
+#define BITS_HI2Q_HOST_IDX (BIT_MASK_HI2Q_HOST_IDX << BIT_SHIFT_HI2Q_HOST_IDX)
+#define BIT_CLEAR_HI2Q_HOST_IDX(x) ((x) & (~BITS_HI2Q_HOST_IDX))
+#define BIT_GET_HI2Q_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_HI2Q_HOST_IDX) & BIT_MASK_HI2Q_HOST_IDX)
+#define BIT_SET_HI2Q_HOST_IDX(x, v) \
+ (BIT_CLEAR_HI2Q_HOST_IDX(x) | BIT_HI2Q_HOST_IDX(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_P0HI2Q_TXBD_IDX (Offset 0x03C0) */
+#define BIT_SHIFT_P0HI2Q_HOST_IDX 0
+#define BIT_MASK_P0HI2Q_HOST_IDX 0xfff
+#define BIT_P0HI2Q_HOST_IDX(x) \
+ (((x) & BIT_MASK_P0HI2Q_HOST_IDX) << BIT_SHIFT_P0HI2Q_HOST_IDX)
+#define BITS_P0HI2Q_HOST_IDX \
+ (BIT_MASK_P0HI2Q_HOST_IDX << BIT_SHIFT_P0HI2Q_HOST_IDX)
+#define BIT_CLEAR_P0HI2Q_HOST_IDX(x) ((x) & (~BITS_P0HI2Q_HOST_IDX))
+#define BIT_GET_P0HI2Q_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI2Q_HOST_IDX) & BIT_MASK_P0HI2Q_HOST_IDX)
+#define BIT_SET_P0HI2Q_HOST_IDX(x, v) \
+ (BIT_CLEAR_P0HI2Q_HOST_IDX(x) | BIT_P0HI2Q_HOST_IDX(v))
-/* 2 REG_PCIE_MIX_CFG (Offset 0x03F8) */
+#endif
-#define BIT_EN_WATCH_DOG BIT(8)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_MDIO_REG_ADDR_V1 0
-#define BIT_MASK_MDIO_REG_ADDR_V1 0x1f
-#define BIT_MDIO_REG_ADDR_V1(x) (((x) & BIT_MASK_MDIO_REG_ADDR_V1) << BIT_SHIFT_MDIO_REG_ADDR_V1)
-#define BIT_GET_MDIO_REG_ADDR_V1(x) (((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1) & BIT_MASK_MDIO_REG_ADDR_V1)
+/* 2 REG_HI3Q_TXBD_IDX (Offset 0x03C4) */
+#define BIT_SHIFT_HI3Q_HW_IDX 16
+#define BIT_MASK_HI3Q_HW_IDX 0xfff
+#define BIT_HI3Q_HW_IDX(x) \
+ (((x) & BIT_MASK_HI3Q_HW_IDX) << BIT_SHIFT_HI3Q_HW_IDX)
+#define BITS_HI3Q_HW_IDX (BIT_MASK_HI3Q_HW_IDX << BIT_SHIFT_HI3Q_HW_IDX)
+#define BIT_CLEAR_HI3Q_HW_IDX(x) ((x) & (~BITS_HI3Q_HW_IDX))
+#define BIT_GET_HI3Q_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_HI3Q_HW_IDX) & BIT_MASK_HI3Q_HW_IDX)
+#define BIT_SET_HI3Q_HW_IDX(x, v) \
+ (BIT_CLEAR_HI3Q_HW_IDX(x) | BIT_HI3Q_HW_IDX(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_P0HI3Q_TXBD_IDX (Offset 0x03C4) */
+#define BIT_SHIFT_P0HI3Q_HW_IDX 16
+#define BIT_MASK_P0HI3Q_HW_IDX 0xfff
+#define BIT_P0HI3Q_HW_IDX(x) \
+ (((x) & BIT_MASK_P0HI3Q_HW_IDX) << BIT_SHIFT_P0HI3Q_HW_IDX)
+#define BITS_P0HI3Q_HW_IDX (BIT_MASK_P0HI3Q_HW_IDX << BIT_SHIFT_P0HI3Q_HW_IDX)
+#define BIT_CLEAR_P0HI3Q_HW_IDX(x) ((x) & (~BITS_P0HI3Q_HW_IDX))
+#define BIT_GET_P0HI3Q_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI3Q_HW_IDX) & BIT_MASK_P0HI3Q_HW_IDX)
+#define BIT_SET_P0HI3Q_HW_IDX(x, v) \
+ (BIT_CLEAR_P0HI3Q_HW_IDX(x) | BIT_P0HI3Q_HW_IDX(v))
-/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */
+#endif
-#define BIT_RXRST_BACKDOOR BIT(31)
-#define BIT_TXRST_BACKDOOR BIT(30)
-#define BIT_RXIDX_RSTB BIT(29)
-#define BIT_TXIDX_RSTB BIT(28)
-#define BIT_DROP_NEXT_RXPKT BIT(27)
-#define BIT_SHORT_CORE_RST_SEL BIT(26)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_HI3Q_TXBD_IDX (Offset 0x03C4) */
+#define BIT_SHIFT_HI3Q_HOST_IDX 0
+#define BIT_MASK_HI3Q_HOST_IDX 0xfff
+#define BIT_HI3Q_HOST_IDX(x) \
+ (((x) & BIT_MASK_HI3Q_HOST_IDX) << BIT_SHIFT_HI3Q_HOST_IDX)
+#define BITS_HI3Q_HOST_IDX (BIT_MASK_HI3Q_HOST_IDX << BIT_SHIFT_HI3Q_HOST_IDX)
+#define BIT_CLEAR_HI3Q_HOST_IDX(x) ((x) & (~BITS_HI3Q_HOST_IDX))
+#define BIT_GET_HI3Q_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_HI3Q_HOST_IDX) & BIT_MASK_HI3Q_HOST_IDX)
+#define BIT_SET_HI3Q_HOST_IDX(x, v) \
+ (BIT_CLEAR_HI3Q_HOST_IDX(x) | BIT_HI3Q_HOST_IDX(v))
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */
+/* 2 REG_P0HI3Q_TXBD_IDX (Offset 0x03C4) */
-#define BIT_EXCEPT_RESUME_EN BIT(25)
-#define BIT_EXCEPT_RESUME_FLAG BIT(24)
+#define BIT_SHIFT_P0HI3Q_HOST_IDX 0
+#define BIT_MASK_P0HI3Q_HOST_IDX 0xfff
+#define BIT_P0HI3Q_HOST_IDX(x) \
+ (((x) & BIT_MASK_P0HI3Q_HOST_IDX) << BIT_SHIFT_P0HI3Q_HOST_IDX)
+#define BITS_P0HI3Q_HOST_IDX \
+ (BIT_MASK_P0HI3Q_HOST_IDX << BIT_SHIFT_P0HI3Q_HOST_IDX)
+#define BIT_CLEAR_P0HI3Q_HOST_IDX(x) ((x) & (~BITS_P0HI3Q_HOST_IDX))
+#define BIT_GET_P0HI3Q_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI3Q_HOST_IDX) & BIT_MASK_P0HI3Q_HOST_IDX)
+#define BIT_SET_P0HI3Q_HOST_IDX(x, v) \
+ (BIT_CLEAR_P0HI3Q_HOST_IDX(x) | BIT_P0HI3Q_HOST_IDX(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_HI4Q_TXBD_IDX (Offset 0x03C8) */
+#define BIT_SHIFT_HI4Q_HW_IDX 16
+#define BIT_MASK_HI4Q_HW_IDX 0xfff
+#define BIT_HI4Q_HW_IDX(x) \
+ (((x) & BIT_MASK_HI4Q_HW_IDX) << BIT_SHIFT_HI4Q_HW_IDX)
+#define BITS_HI4Q_HW_IDX (BIT_MASK_HI4Q_HW_IDX << BIT_SHIFT_HI4Q_HW_IDX)
+#define BIT_CLEAR_HI4Q_HW_IDX(x) ((x) & (~BITS_HI4Q_HW_IDX))
+#define BIT_GET_HI4Q_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_HI4Q_HW_IDX) & BIT_MASK_HI4Q_HW_IDX)
+#define BIT_SET_HI4Q_HW_IDX(x, v) \
+ (BIT_CLEAR_HI4Q_HW_IDX(x) | BIT_HI4Q_HW_IDX(v))
-/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */
+#endif
-#define BIT_ALIGN_MTU BIT(23)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_P0HI4Q_TXBD_IDX (Offset 0x03C8) */
+#define BIT_SHIFT_P0HI4Q_HW_IDX 16
+#define BIT_MASK_P0HI4Q_HW_IDX 0xfff
+#define BIT_P0HI4Q_HW_IDX(x) \
+ (((x) & BIT_MASK_P0HI4Q_HW_IDX) << BIT_SHIFT_P0HI4Q_HW_IDX)
+#define BITS_P0HI4Q_HW_IDX (BIT_MASK_P0HI4Q_HW_IDX << BIT_SHIFT_P0HI4Q_HW_IDX)
+#define BIT_CLEAR_P0HI4Q_HW_IDX(x) ((x) & (~BITS_P0HI4Q_HW_IDX))
+#define BIT_GET_P0HI4Q_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI4Q_HW_IDX) & BIT_MASK_P0HI4Q_HW_IDX)
+#define BIT_SET_P0HI4Q_HW_IDX(x, v) \
+ (BIT_CLEAR_P0HI4Q_HW_IDX(x) | BIT_P0HI4Q_HW_IDX(v))
-#if (HALMAC_8814AMP_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */
+/* 2 REG_HI4Q_TXBD_IDX (Offset 0x03C8) */
-#define BIT_EARLY_TAG_RETURN BIT(22)
+#define BIT_SHIFT_HI4Q_HOST_IDX 0
+#define BIT_MASK_HI4Q_HOST_IDX 0xfff
+#define BIT_HI4Q_HOST_IDX(x) \
+ (((x) & BIT_MASK_HI4Q_HOST_IDX) << BIT_SHIFT_HI4Q_HOST_IDX)
+#define BITS_HI4Q_HOST_IDX (BIT_MASK_HI4Q_HOST_IDX << BIT_SHIFT_HI4Q_HOST_IDX)
+#define BIT_CLEAR_HI4Q_HOST_IDX(x) ((x) & (~BITS_HI4Q_HOST_IDX))
+#define BIT_GET_HI4Q_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_HI4Q_HOST_IDX) & BIT_MASK_HI4Q_HOST_IDX)
+#define BIT_SET_HI4Q_HOST_IDX(x, v) \
+ (BIT_CLEAR_HI4Q_HOST_IDX(x) | BIT_HI4Q_HOST_IDX(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_P0HI4Q_TXBD_IDX (Offset 0x03C8) */
+#define BIT_SHIFT_P0HI4Q_HOST_IDX 0
+#define BIT_MASK_P0HI4Q_HOST_IDX 0xfff
+#define BIT_P0HI4Q_HOST_IDX(x) \
+ (((x) & BIT_MASK_P0HI4Q_HOST_IDX) << BIT_SHIFT_P0HI4Q_HOST_IDX)
+#define BITS_P0HI4Q_HOST_IDX \
+ (BIT_MASK_P0HI4Q_HOST_IDX << BIT_SHIFT_P0HI4Q_HOST_IDX)
+#define BIT_CLEAR_P0HI4Q_HOST_IDX(x) ((x) & (~BITS_P0HI4Q_HOST_IDX))
+#define BIT_GET_P0HI4Q_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI4Q_HOST_IDX) & BIT_MASK_P0HI4Q_HOST_IDX)
+#define BIT_SET_P0HI4Q_HOST_IDX(x, v) \
+ (BIT_CLEAR_P0HI4Q_HOST_IDX(x) | BIT_P0HI4Q_HOST_IDX(v))
-/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */
+#endif
-#define BIT_HOST_GEN2_SUPPORT BIT(20)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_TXDMA_ERR_FLAG 16
-#define BIT_MASK_TXDMA_ERR_FLAG 0xf
-#define BIT_TXDMA_ERR_FLAG(x) (((x) & BIT_MASK_TXDMA_ERR_FLAG) << BIT_SHIFT_TXDMA_ERR_FLAG)
-#define BIT_GET_TXDMA_ERR_FLAG(x) (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG) & BIT_MASK_TXDMA_ERR_FLAG)
+/* 2 REG_HI5Q_TXBD_IDX (Offset 0x03CC) */
+#define BIT_SHIFT_HI5Q_HW_IDX 16
+#define BIT_MASK_HI5Q_HW_IDX 0xfff
+#define BIT_HI5Q_HW_IDX(x) \
+ (((x) & BIT_MASK_HI5Q_HW_IDX) << BIT_SHIFT_HI5Q_HW_IDX)
+#define BITS_HI5Q_HW_IDX (BIT_MASK_HI5Q_HW_IDX << BIT_SHIFT_HI5Q_HW_IDX)
+#define BIT_CLEAR_HI5Q_HW_IDX(x) ((x) & (~BITS_HI5Q_HW_IDX))
+#define BIT_GET_HI5Q_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_HI5Q_HW_IDX) & BIT_MASK_HI5Q_HW_IDX)
+#define BIT_SET_HI5Q_HW_IDX(x, v) \
+ (BIT_CLEAR_HI5Q_HW_IDX(x) | BIT_HI5Q_HW_IDX(v))
-#define BIT_SHIFT_EARLY_MODE_SEL 12
-#define BIT_MASK_EARLY_MODE_SEL 0xf
-#define BIT_EARLY_MODE_SEL(x) (((x) & BIT_MASK_EARLY_MODE_SEL) << BIT_SHIFT_EARLY_MODE_SEL)
-#define BIT_GET_EARLY_MODE_SEL(x) (((x) >> BIT_SHIFT_EARLY_MODE_SEL) & BIT_MASK_EARLY_MODE_SEL)
+#endif
-#define BIT_EPHY_RX50_EN BIT(11)
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_MSI_TIMEOUT_ID_V1 8
-#define BIT_MASK_MSI_TIMEOUT_ID_V1 0x7
-#define BIT_MSI_TIMEOUT_ID_V1(x) (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1) << BIT_SHIFT_MSI_TIMEOUT_ID_V1)
-#define BIT_GET_MSI_TIMEOUT_ID_V1(x) (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1) & BIT_MASK_MSI_TIMEOUT_ID_V1)
+/* 2 REG_P0HI5Q_TXBD_IDX (Offset 0x03CC) */
-#define BIT_RADDR_RD BIT(7)
-#define BIT_EN_MUL_TAG BIT(6)
-#define BIT_EN_EARLY_MODE BIT(5)
-#define BIT_L0S_LINK_OFF BIT(4)
-#define BIT_ACT_LINK_OFF BIT(3)
+#define BIT_SHIFT_P0HI5Q_HW_IDX 16
+#define BIT_MASK_P0HI5Q_HW_IDX 0xfff
+#define BIT_P0HI5Q_HW_IDX(x) \
+ (((x) & BIT_MASK_P0HI5Q_HW_IDX) << BIT_SHIFT_P0HI5Q_HW_IDX)
+#define BITS_P0HI5Q_HW_IDX (BIT_MASK_P0HI5Q_HW_IDX << BIT_SHIFT_P0HI5Q_HW_IDX)
+#define BIT_CLEAR_P0HI5Q_HW_IDX(x) ((x) & (~BITS_P0HI5Q_HW_IDX))
+#define BIT_GET_P0HI5Q_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI5Q_HW_IDX) & BIT_MASK_P0HI5Q_HW_IDX)
+#define BIT_SET_P0HI5Q_HW_IDX(x, v) \
+ (BIT_CLEAR_P0HI5Q_HW_IDX(x) | BIT_P0HI5Q_HW_IDX(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_HI5Q_TXBD_IDX (Offset 0x03CC) */
+#define BIT_SHIFT_HI5Q_HOST_IDX 0
+#define BIT_MASK_HI5Q_HOST_IDX 0xfff
+#define BIT_HI5Q_HOST_IDX(x) \
+ (((x) & BIT_MASK_HI5Q_HOST_IDX) << BIT_SHIFT_HI5Q_HOST_IDX)
+#define BITS_HI5Q_HOST_IDX (BIT_MASK_HI5Q_HOST_IDX << BIT_SHIFT_HI5Q_HOST_IDX)
+#define BIT_CLEAR_HI5Q_HOST_IDX(x) ((x) & (~BITS_HI5Q_HOST_IDX))
+#define BIT_GET_HI5Q_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_HI5Q_HOST_IDX) & BIT_MASK_HI5Q_HOST_IDX)
+#define BIT_SET_HI5Q_HOST_IDX(x, v) \
+ (BIT_CLEAR_HI5Q_HOST_IDX(x) | BIT_HI5Q_HOST_IDX(v))
-/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */
+#endif
-#define BIT_EN_SLOW_MAC_TX BIT(2)
-#define BIT_EN_SLOW_MAC_RX BIT(1)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_P0HI5Q_TXBD_IDX (Offset 0x03CC) */
+#define BIT_SHIFT_P0HI5Q_HOST_IDX 0
+#define BIT_MASK_P0HI5Q_HOST_IDX 0xfff
+#define BIT_P0HI5Q_HOST_IDX(x) \
+ (((x) & BIT_MASK_P0HI5Q_HOST_IDX) << BIT_SHIFT_P0HI5Q_HOST_IDX)
+#define BITS_P0HI5Q_HOST_IDX \
+ (BIT_MASK_P0HI5Q_HOST_IDX << BIT_SHIFT_P0HI5Q_HOST_IDX)
+#define BIT_CLEAR_P0HI5Q_HOST_IDX(x) ((x) & (~BITS_P0HI5Q_HOST_IDX))
+#define BIT_GET_P0HI5Q_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI5Q_HOST_IDX) & BIT_MASK_P0HI5Q_HOST_IDX)
+#define BIT_SET_P0HI5Q_HOST_IDX(x, v) \
+ (BIT_CLEAR_P0HI5Q_HOST_IDX(x) | BIT_P0HI5Q_HOST_IDX(v))
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_Q0_INFO (Offset 0x0400) */
+/* 2 REG_HI6Q_TXBD_IDX (Offset 0x03D0) */
+#define BIT_SHIFT_HI6Q_HW_IDX 16
+#define BIT_MASK_HI6Q_HW_IDX 0xfff
+#define BIT_HI6Q_HW_IDX(x) \
+ (((x) & BIT_MASK_HI6Q_HW_IDX) << BIT_SHIFT_HI6Q_HW_IDX)
+#define BITS_HI6Q_HW_IDX (BIT_MASK_HI6Q_HW_IDX << BIT_SHIFT_HI6Q_HW_IDX)
+#define BIT_CLEAR_HI6Q_HW_IDX(x) ((x) & (~BITS_HI6Q_HW_IDX))
+#define BIT_GET_HI6Q_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_HI6Q_HW_IDX) & BIT_MASK_HI6Q_HW_IDX)
+#define BIT_SET_HI6Q_HW_IDX(x, v) \
+ (BIT_CLEAR_HI6Q_HW_IDX(x) | BIT_HI6Q_HW_IDX(v))
-#define BIT_SHIFT_QUEUEMACID_Q0_V1 25
-#define BIT_MASK_QUEUEMACID_Q0_V1 0x7f
-#define BIT_QUEUEMACID_Q0_V1(x) (((x) & BIT_MASK_QUEUEMACID_Q0_V1) << BIT_SHIFT_QUEUEMACID_Q0_V1)
-#define BIT_GET_QUEUEMACID_Q0_V1(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1) & BIT_MASK_QUEUEMACID_Q0_V1)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_QUEUEAC_Q0_V1 23
-#define BIT_MASK_QUEUEAC_Q0_V1 0x3
-#define BIT_QUEUEAC_Q0_V1(x) (((x) & BIT_MASK_QUEUEAC_Q0_V1) << BIT_SHIFT_QUEUEAC_Q0_V1)
-#define BIT_GET_QUEUEAC_Q0_V1(x) (((x) >> BIT_SHIFT_QUEUEAC_Q0_V1) & BIT_MASK_QUEUEAC_Q0_V1)
+/* 2 REG_P0HI6Q_TXBD_IDX (Offset 0x03D0) */
+#define BIT_SHIFT_P0HI6Q_HW_IDX 16
+#define BIT_MASK_P0HI6Q_HW_IDX 0xfff
+#define BIT_P0HI6Q_HW_IDX(x) \
+ (((x) & BIT_MASK_P0HI6Q_HW_IDX) << BIT_SHIFT_P0HI6Q_HW_IDX)
+#define BITS_P0HI6Q_HW_IDX (BIT_MASK_P0HI6Q_HW_IDX << BIT_SHIFT_P0HI6Q_HW_IDX)
+#define BIT_CLEAR_P0HI6Q_HW_IDX(x) ((x) & (~BITS_P0HI6Q_HW_IDX))
+#define BIT_GET_P0HI6Q_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI6Q_HW_IDX) & BIT_MASK_P0HI6Q_HW_IDX)
+#define BIT_SET_P0HI6Q_HW_IDX(x, v) \
+ (BIT_CLEAR_P0HI6Q_HW_IDX(x) | BIT_P0HI6Q_HW_IDX(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_HI6Q_TXBD_IDX (Offset 0x03D0) */
+
+#define BIT_SHIFT_HI6Q_HOST_IDX 0
+#define BIT_MASK_HI6Q_HOST_IDX 0xfff
+#define BIT_HI6Q_HOST_IDX(x) \
+ (((x) & BIT_MASK_HI6Q_HOST_IDX) << BIT_SHIFT_HI6Q_HOST_IDX)
+#define BITS_HI6Q_HOST_IDX (BIT_MASK_HI6Q_HOST_IDX << BIT_SHIFT_HI6Q_HOST_IDX)
+#define BIT_CLEAR_HI6Q_HOST_IDX(x) ((x) & (~BITS_HI6Q_HOST_IDX))
+#define BIT_GET_HI6Q_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_HI6Q_HOST_IDX) & BIT_MASK_HI6Q_HOST_IDX)
+#define BIT_SET_HI6Q_HOST_IDX(x, v) \
+ (BIT_CLEAR_HI6Q_HOST_IDX(x) | BIT_HI6Q_HOST_IDX(v))
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_Q0_INFO (Offset 0x0400) */
+/* 2 REG_P0HI6Q_TXBD_IDX (Offset 0x03D0) */
-#define BIT_TIDEMPTY_Q0_V1 BIT(22)
+#define BIT_SHIFT_P0HI6Q_HOST_IDX 0
+#define BIT_MASK_P0HI6Q_HOST_IDX 0xfff
+#define BIT_P0HI6Q_HOST_IDX(x) \
+ (((x) & BIT_MASK_P0HI6Q_HOST_IDX) << BIT_SHIFT_P0HI6Q_HOST_IDX)
+#define BITS_P0HI6Q_HOST_IDX \
+ (BIT_MASK_P0HI6Q_HOST_IDX << BIT_SHIFT_P0HI6Q_HOST_IDX)
+#define BIT_CLEAR_P0HI6Q_HOST_IDX(x) ((x) & (~BITS_P0HI6Q_HOST_IDX))
+#define BIT_GET_P0HI6Q_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI6Q_HOST_IDX) & BIT_MASK_P0HI6Q_HOST_IDX)
+#define BIT_SET_P0HI6Q_HOST_IDX(x, v) \
+ (BIT_CLEAR_P0HI6Q_HOST_IDX(x) | BIT_P0HI6Q_HOST_IDX(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_HI7Q_TXBD_IDX (Offset 0x03D4) */
+#define BIT_SHIFT_HI7Q_HW_IDX 16
+#define BIT_MASK_HI7Q_HW_IDX 0xfff
+#define BIT_HI7Q_HW_IDX(x) \
+ (((x) & BIT_MASK_HI7Q_HW_IDX) << BIT_SHIFT_HI7Q_HW_IDX)
+#define BITS_HI7Q_HW_IDX (BIT_MASK_HI7Q_HW_IDX << BIT_SHIFT_HI7Q_HW_IDX)
+#define BIT_CLEAR_HI7Q_HW_IDX(x) ((x) & (~BITS_HI7Q_HW_IDX))
+#define BIT_GET_HI7Q_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_HI7Q_HW_IDX) & BIT_MASK_HI7Q_HW_IDX)
+#define BIT_SET_HI7Q_HW_IDX(x, v) \
+ (BIT_CLEAR_HI7Q_HW_IDX(x) | BIT_HI7Q_HW_IDX(v))
-/* 2 REG_Q0_INFO (Offset 0x0400) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_TAIL_PKT_Q0_V1 15
-#define BIT_MASK_TAIL_PKT_Q0_V1 0xff
-#define BIT_TAIL_PKT_Q0_V1(x) (((x) & BIT_MASK_TAIL_PKT_Q0_V1) << BIT_SHIFT_TAIL_PKT_Q0_V1)
-#define BIT_GET_TAIL_PKT_Q0_V1(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V1) & BIT_MASK_TAIL_PKT_Q0_V1)
+/* 2 REG_P0HI7Q_TXBD_IDX (Offset 0x03D4) */
+#define BIT_SHIFT_P0HI7Q_HW_IDX 16
+#define BIT_MASK_P0HI7Q_HW_IDX 0xfff
+#define BIT_P0HI7Q_HW_IDX(x) \
+ (((x) & BIT_MASK_P0HI7Q_HW_IDX) << BIT_SHIFT_P0HI7Q_HW_IDX)
+#define BITS_P0HI7Q_HW_IDX (BIT_MASK_P0HI7Q_HW_IDX << BIT_SHIFT_P0HI7Q_HW_IDX)
+#define BIT_CLEAR_P0HI7Q_HW_IDX(x) ((x) & (~BITS_P0HI7Q_HW_IDX))
+#define BIT_GET_P0HI7Q_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI7Q_HW_IDX) & BIT_MASK_P0HI7Q_HW_IDX)
+#define BIT_SET_P0HI7Q_HW_IDX(x, v) \
+ (BIT_CLEAR_P0HI7Q_HW_IDX(x) | BIT_P0HI7Q_HW_IDX(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_HI7Q_TXBD_IDX (Offset 0x03D4) */
+#define BIT_SHIFT_HI7Q_HOST_IDX 0
+#define BIT_MASK_HI7Q_HOST_IDX 0xfff
+#define BIT_HI7Q_HOST_IDX(x) \
+ (((x) & BIT_MASK_HI7Q_HOST_IDX) << BIT_SHIFT_HI7Q_HOST_IDX)
+#define BITS_HI7Q_HOST_IDX (BIT_MASK_HI7Q_HOST_IDX << BIT_SHIFT_HI7Q_HOST_IDX)
+#define BIT_CLEAR_HI7Q_HOST_IDX(x) ((x) & (~BITS_HI7Q_HOST_IDX))
+#define BIT_GET_HI7Q_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_HI7Q_HOST_IDX) & BIT_MASK_HI7Q_HOST_IDX)
+#define BIT_SET_HI7Q_HOST_IDX(x, v) \
+ (BIT_CLEAR_HI7Q_HOST_IDX(x) | BIT_HI7Q_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI7Q_TXBD_IDX (Offset 0x03D4) */
+
+#define BIT_SHIFT_P0HI7Q_HOST_IDX 0
+#define BIT_MASK_P0HI7Q_HOST_IDX 0xfff
+#define BIT_P0HI7Q_HOST_IDX(x) \
+ (((x) & BIT_MASK_P0HI7Q_HOST_IDX) << BIT_SHIFT_P0HI7Q_HOST_IDX)
+#define BITS_P0HI7Q_HOST_IDX \
+ (BIT_MASK_P0HI7Q_HOST_IDX << BIT_SHIFT_P0HI7Q_HOST_IDX)
+#define BIT_CLEAR_P0HI7Q_HOST_IDX(x) ((x) & (~BITS_P0HI7Q_HOST_IDX))
+#define BIT_GET_P0HI7Q_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI7Q_HOST_IDX) & BIT_MASK_P0HI7Q_HOST_IDX)
+#define BIT_SET_P0HI7Q_HOST_IDX(x, v) \
+ (BIT_CLEAR_P0HI7Q_HOST_IDX(x) | BIT_P0HI7Q_HOST_IDX(v))
+
+/* 2 REG_DBGSEL_PCIE_HRPWM1_HCPWM1_V1 (Offset 0x03D8) */
+
+#define BIT_DIS_TXDMA_PRE_V1 BIT(31)
+#define BIT_DIS_RXDMA_PRE_V1 BIT(30)
+
+#define BIT_SHIFT_HPS_CLKR_PCIE_V1 28
+#define BIT_MASK_HPS_CLKR_PCIE_V1 0x3
+#define BIT_HPS_CLKR_PCIE_V1(x) \
+ (((x) & BIT_MASK_HPS_CLKR_PCIE_V1) << BIT_SHIFT_HPS_CLKR_PCIE_V1)
+#define BITS_HPS_CLKR_PCIE_V1 \
+ (BIT_MASK_HPS_CLKR_PCIE_V1 << BIT_SHIFT_HPS_CLKR_PCIE_V1)
+#define BIT_CLEAR_HPS_CLKR_PCIE_V1(x) ((x) & (~BITS_HPS_CLKR_PCIE_V1))
+#define BIT_GET_HPS_CLKR_PCIE_V1(x) \
+ (((x) >> BIT_SHIFT_HPS_CLKR_PCIE_V1) & BIT_MASK_HPS_CLKR_PCIE_V1)
+#define BIT_SET_HPS_CLKR_PCIE_V1(x, v) \
+ (BIT_CLEAR_HPS_CLKR_PCIE_V1(x) | BIT_HPS_CLKR_PCIE_V1(v))
+
+#define BIT_PCIE_INT_V1 BIT(27)
+#define BIT_TXFLAG_EXIT_L1_EN_V1 BIT(26)
+#define BIT_EN_RXDMA_ALIGN_V2 BIT(25)
+#define BIT_EN_TXDMA_ALIGN_V2 BIT(24)
+
+#define BIT_SHIFT_PCIE_HCPWM_V1 16
+#define BIT_MASK_PCIE_HCPWM_V1 0xff
+#define BIT_PCIE_HCPWM_V1(x) \
+ (((x) & BIT_MASK_PCIE_HCPWM_V1) << BIT_SHIFT_PCIE_HCPWM_V1)
+#define BITS_PCIE_HCPWM_V1 (BIT_MASK_PCIE_HCPWM_V1 << BIT_SHIFT_PCIE_HCPWM_V1)
+#define BIT_CLEAR_PCIE_HCPWM_V1(x) ((x) & (~BITS_PCIE_HCPWM_V1))
+#define BIT_GET_PCIE_HCPWM_V1(x) \
+ (((x) >> BIT_SHIFT_PCIE_HCPWM_V1) & BIT_MASK_PCIE_HCPWM_V1)
+#define BIT_SET_PCIE_HCPWM_V1(x, v) \
+ (BIT_CLEAR_PCIE_HCPWM_V1(x) | BIT_PCIE_HCPWM_V1(v))
+
+#define BIT_SHIFT_PCIE_HRPWM_V1 8
+#define BIT_MASK_PCIE_HRPWM_V1 0xff
+#define BIT_PCIE_HRPWM_V1(x) \
+ (((x) & BIT_MASK_PCIE_HRPWM_V1) << BIT_SHIFT_PCIE_HRPWM_V1)
+#define BITS_PCIE_HRPWM_V1 (BIT_MASK_PCIE_HRPWM_V1 << BIT_SHIFT_PCIE_HRPWM_V1)
+#define BIT_CLEAR_PCIE_HRPWM_V1(x) ((x) & (~BITS_PCIE_HRPWM_V1))
+#define BIT_GET_PCIE_HRPWM_V1(x) \
+ (((x) >> BIT_SHIFT_PCIE_HRPWM_V1) & BIT_MASK_PCIE_HRPWM_V1)
+#define BIT_SET_PCIE_HRPWM_V1(x, v) \
+ (BIT_CLEAR_PCIE_HRPWM_V1(x) | BIT_PCIE_HRPWM_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_Q0_INFO (Offset 0x0400) */
+/* 2 REG_DBG_SEL_V1 (Offset 0x03D8) */
+#define BIT_SHIFT_DBG_SEL 0
+#define BIT_MASK_DBG_SEL 0xff
+#define BIT_DBG_SEL(x) (((x) & BIT_MASK_DBG_SEL) << BIT_SHIFT_DBG_SEL)
+#define BITS_DBG_SEL (BIT_MASK_DBG_SEL << BIT_SHIFT_DBG_SEL)
+#define BIT_CLEAR_DBG_SEL(x) ((x) & (~BITS_DBG_SEL))
+#define BIT_GET_DBG_SEL(x) (((x) >> BIT_SHIFT_DBG_SEL) & BIT_MASK_DBG_SEL)
+#define BIT_SET_DBG_SEL(x, v) (BIT_CLEAR_DBG_SEL(x) | BIT_DBG_SEL(v))
-#define BIT_SHIFT_TAIL_PKT_Q0_V2 11
-#define BIT_MASK_TAIL_PKT_Q0_V2 0x7ff
-#define BIT_TAIL_PKT_Q0_V2(x) (((x) & BIT_MASK_TAIL_PKT_Q0_V2) << BIT_SHIFT_TAIL_PKT_Q0_V2)
-#define BIT_GET_TAIL_PKT_Q0_V2(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2) & BIT_MASK_TAIL_PKT_Q0_V2)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_PCIE_HRPWM1_V1 (Offset 0x03D9) */
+#define BIT_SHIFT_PCIE_HRPWM 0
+#define BIT_MASK_PCIE_HRPWM 0xff
+#define BIT_PCIE_HRPWM(x) (((x) & BIT_MASK_PCIE_HRPWM) << BIT_SHIFT_PCIE_HRPWM)
+#define BITS_PCIE_HRPWM (BIT_MASK_PCIE_HRPWM << BIT_SHIFT_PCIE_HRPWM)
+#define BIT_CLEAR_PCIE_HRPWM(x) ((x) & (~BITS_PCIE_HRPWM))
+#define BIT_GET_PCIE_HRPWM(x) \
+ (((x) >> BIT_SHIFT_PCIE_HRPWM) & BIT_MASK_PCIE_HRPWM)
+#define BIT_SET_PCIE_HRPWM(x, v) (BIT_CLEAR_PCIE_HRPWM(x) | BIT_PCIE_HRPWM(v))
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-/* 2 REG_Q0_INFO (Offset 0x0400) */
+/* 2 REG_HCI_HRPWM1_V1 (Offset 0x03D9) */
+#define BIT_SHIFT_HCI_HRPWM 0
+#define BIT_MASK_HCI_HRPWM 0xff
+#define BIT_HCI_HRPWM(x) (((x) & BIT_MASK_HCI_HRPWM) << BIT_SHIFT_HCI_HRPWM)
+#define BITS_HCI_HRPWM (BIT_MASK_HCI_HRPWM << BIT_SHIFT_HCI_HRPWM)
+#define BIT_CLEAR_HCI_HRPWM(x) ((x) & (~BITS_HCI_HRPWM))
+#define BIT_GET_HCI_HRPWM(x) (((x) >> BIT_SHIFT_HCI_HRPWM) & BIT_MASK_HCI_HRPWM)
+#define BIT_SET_HCI_HRPWM(x, v) (BIT_CLEAR_HCI_HRPWM(x) | BIT_HCI_HRPWM(v))
-#define BIT_SHIFT_PKT_NUM_Q0_V1 8
-#define BIT_MASK_PKT_NUM_Q0_V1 0x7f
-#define BIT_PKT_NUM_Q0_V1(x) (((x) & BIT_MASK_PKT_NUM_Q0_V1) << BIT_SHIFT_PKT_NUM_Q0_V1)
-#define BIT_GET_PKT_NUM_Q0_V1(x) (((x) >> BIT_SHIFT_PKT_NUM_Q0_V1) & BIT_MASK_PKT_NUM_Q0_V1)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_HEAD_PKT_Q0 0
-#define BIT_MASK_HEAD_PKT_Q0 0xff
-#define BIT_HEAD_PKT_Q0(x) (((x) & BIT_MASK_HEAD_PKT_Q0) << BIT_SHIFT_HEAD_PKT_Q0)
-#define BIT_GET_HEAD_PKT_Q0(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q0) & BIT_MASK_HEAD_PKT_Q0)
+/* 2 REG_PCIE_HCPWM1_V1 (Offset 0x03DA) */
+#define BIT_SHIFT_PCIE_HCPWM 0
+#define BIT_MASK_PCIE_HCPWM 0xff
+#define BIT_PCIE_HCPWM(x) (((x) & BIT_MASK_PCIE_HCPWM) << BIT_SHIFT_PCIE_HCPWM)
+#define BITS_PCIE_HCPWM (BIT_MASK_PCIE_HCPWM << BIT_SHIFT_PCIE_HCPWM)
+#define BIT_CLEAR_PCIE_HCPWM(x) ((x) & (~BITS_PCIE_HCPWM))
+#define BIT_GET_PCIE_HCPWM(x) \
+ (((x) >> BIT_SHIFT_PCIE_HCPWM) & BIT_MASK_PCIE_HCPWM)
+#define BIT_SET_PCIE_HCPWM(x, v) (BIT_CLEAR_PCIE_HCPWM(x) | BIT_PCIE_HCPWM(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_HCI_HCPWM1_V1 (Offset 0x03DA) */
+#define BIT_SHIFT_HCI_HCPWM 0
+#define BIT_MASK_HCI_HCPWM 0xff
+#define BIT_HCI_HCPWM(x) (((x) & BIT_MASK_HCI_HCPWM) << BIT_SHIFT_HCI_HCPWM)
+#define BITS_HCI_HCPWM (BIT_MASK_HCI_HCPWM << BIT_SHIFT_HCI_HCPWM)
+#define BIT_CLEAR_HCI_HCPWM(x) ((x) & (~BITS_HCI_HCPWM))
+#define BIT_GET_HCI_HCPWM(x) (((x) >> BIT_SHIFT_HCI_HCPWM) & BIT_MASK_HCI_HCPWM)
+#define BIT_SET_HCI_HCPWM(x, v) (BIT_CLEAR_HCI_HCPWM(x) | BIT_HCI_HCPWM(v))
-/* 2 REG_Q0_INFO (Offset 0x0400) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_HEAD_PKT_Q0_V1 0
-#define BIT_MASK_HEAD_PKT_Q0_V1 0x7ff
-#define BIT_HEAD_PKT_Q0_V1(x) (((x) & BIT_MASK_HEAD_PKT_Q0_V1) << BIT_SHIFT_HEAD_PKT_Q0_V1)
-#define BIT_GET_HEAD_PKT_Q0_V1(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1) & BIT_MASK_HEAD_PKT_Q0_V1)
+/* 2 REG_PCIE_CTRL2 (Offset 0x03DB) */
+#define BIT_SHIFT_HPS_CLKR_PCIE 4
+#define BIT_MASK_HPS_CLKR_PCIE 0x3
+#define BIT_HPS_CLKR_PCIE(x) \
+ (((x) & BIT_MASK_HPS_CLKR_PCIE) << BIT_SHIFT_HPS_CLKR_PCIE)
+#define BITS_HPS_CLKR_PCIE (BIT_MASK_HPS_CLKR_PCIE << BIT_SHIFT_HPS_CLKR_PCIE)
+#define BIT_CLEAR_HPS_CLKR_PCIE(x) ((x) & (~BITS_HPS_CLKR_PCIE))
+#define BIT_GET_HPS_CLKR_PCIE(x) \
+ (((x) >> BIT_SHIFT_HPS_CLKR_PCIE) & BIT_MASK_HPS_CLKR_PCIE)
+#define BIT_SET_HPS_CLKR_PCIE(x, v) \
+ (BIT_CLEAR_HPS_CLKR_PCIE(x) | BIT_HPS_CLKR_PCIE(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_HCI_CTRL2 (Offset 0x03DB) */
+#define BIT_SHIFT_HPS_CLKR_HCI 4
+#define BIT_MASK_HPS_CLKR_HCI 0x3
+#define BIT_HPS_CLKR_HCI(x) \
+ (((x) & BIT_MASK_HPS_CLKR_HCI) << BIT_SHIFT_HPS_CLKR_HCI)
+#define BITS_HPS_CLKR_HCI (BIT_MASK_HPS_CLKR_HCI << BIT_SHIFT_HPS_CLKR_HCI)
+#define BIT_CLEAR_HPS_CLKR_HCI(x) ((x) & (~BITS_HPS_CLKR_HCI))
+#define BIT_GET_HPS_CLKR_HCI(x) \
+ (((x) >> BIT_SHIFT_HPS_CLKR_HCI) & BIT_MASK_HPS_CLKR_HCI)
+#define BIT_SET_HPS_CLKR_HCI(x, v) \
+ (BIT_CLEAR_HPS_CLKR_HCI(x) | BIT_HPS_CLKR_HCI(v))
-/* 2 REG_Q1_INFO (Offset 0x0404) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_QUEUEMACID_Q1_V1 25
-#define BIT_MASK_QUEUEMACID_Q1_V1 0x7f
-#define BIT_QUEUEMACID_Q1_V1(x) (((x) & BIT_MASK_QUEUEMACID_Q1_V1) << BIT_SHIFT_QUEUEMACID_Q1_V1)
-#define BIT_GET_QUEUEMACID_Q1_V1(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1) & BIT_MASK_QUEUEMACID_Q1_V1)
+/* 2 REG_PCIE_CTRL2 (Offset 0x03DB) */
+#define BIT_PCIE_INT BIT(3)
-#define BIT_SHIFT_QUEUEAC_Q1_V1 23
-#define BIT_MASK_QUEUEAC_Q1_V1 0x3
-#define BIT_QUEUEAC_Q1_V1(x) (((x) & BIT_MASK_QUEUEAC_Q1_V1) << BIT_SHIFT_QUEUEAC_Q1_V1)
-#define BIT_GET_QUEUEAC_Q1_V1(x) (((x) >> BIT_SHIFT_QUEUEAC_Q1_V1) & BIT_MASK_QUEUEAC_Q1_V1)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#endif
+/* 2 REG_HCI_CTRL2 (Offset 0x03DB) */
+#define BIT_HCI_INT BIT(3)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-/* 2 REG_Q1_INFO (Offset 0x0404) */
+/* 2 REG_PCIE_CTRL2 (Offset 0x03DB) */
-#define BIT_TIDEMPTY_Q1_V1 BIT(22)
+#define BIT_EN_RXDMA_ALIGN BIT(1)
+#define BIT_EN_TXDMA_ALIGN BIT(0)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_PCIE_HRPWM2_HCPWM2_V1 (Offset 0x03DC) */
+#define BIT_SHIFT_PCIE_HCPWM2_V1 16
+#define BIT_MASK_PCIE_HCPWM2_V1 0xffff
+#define BIT_PCIE_HCPWM2_V1(x) \
+ (((x) & BIT_MASK_PCIE_HCPWM2_V1) << BIT_SHIFT_PCIE_HCPWM2_V1)
+#define BITS_PCIE_HCPWM2_V1 \
+ (BIT_MASK_PCIE_HCPWM2_V1 << BIT_SHIFT_PCIE_HCPWM2_V1)
+#define BIT_CLEAR_PCIE_HCPWM2_V1(x) ((x) & (~BITS_PCIE_HCPWM2_V1))
+#define BIT_GET_PCIE_HCPWM2_V1(x) \
+ (((x) >> BIT_SHIFT_PCIE_HCPWM2_V1) & BIT_MASK_PCIE_HCPWM2_V1)
+#define BIT_SET_PCIE_HCPWM2_V1(x, v) \
+ (BIT_CLEAR_PCIE_HCPWM2_V1(x) | BIT_PCIE_HCPWM2_V1(v))
-/* 2 REG_Q1_INFO (Offset 0x0404) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_TAIL_PKT_Q1_V1 15
-#define BIT_MASK_TAIL_PKT_Q1_V1 0xff
-#define BIT_TAIL_PKT_Q1_V1(x) (((x) & BIT_MASK_TAIL_PKT_Q1_V1) << BIT_SHIFT_TAIL_PKT_Q1_V1)
-#define BIT_GET_TAIL_PKT_Q1_V1(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V1) & BIT_MASK_TAIL_PKT_Q1_V1)
+/* 2 REG_PCIE_HRPWM2_V1 (Offset 0x03DC) */
+#define BIT_SHIFT_PCIE_HRPWM2 0
+#define BIT_MASK_PCIE_HRPWM2 0xffff
+#define BIT_PCIE_HRPWM2(x) \
+ (((x) & BIT_MASK_PCIE_HRPWM2) << BIT_SHIFT_PCIE_HRPWM2)
+#define BITS_PCIE_HRPWM2 (BIT_MASK_PCIE_HRPWM2 << BIT_SHIFT_PCIE_HRPWM2)
+#define BIT_CLEAR_PCIE_HRPWM2(x) ((x) & (~BITS_PCIE_HRPWM2))
+#define BIT_GET_PCIE_HRPWM2(x) \
+ (((x) >> BIT_SHIFT_PCIE_HRPWM2) & BIT_MASK_PCIE_HRPWM2)
+#define BIT_SET_PCIE_HRPWM2(x, v) \
+ (BIT_CLEAR_PCIE_HRPWM2(x) | BIT_PCIE_HRPWM2(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_HCI_HRPWM2_V1 (Offset 0x03DC) */
+#define BIT_SHIFT_HCI_HRPWM2 0
+#define BIT_MASK_HCI_HRPWM2 0xffff
+#define BIT_HCI_HRPWM2(x) (((x) & BIT_MASK_HCI_HRPWM2) << BIT_SHIFT_HCI_HRPWM2)
+#define BITS_HCI_HRPWM2 (BIT_MASK_HCI_HRPWM2 << BIT_SHIFT_HCI_HRPWM2)
+#define BIT_CLEAR_HCI_HRPWM2(x) ((x) & (~BITS_HCI_HRPWM2))
+#define BIT_GET_HCI_HRPWM2(x) \
+ (((x) >> BIT_SHIFT_HCI_HRPWM2) & BIT_MASK_HCI_HRPWM2)
+#define BIT_SET_HCI_HRPWM2(x, v) (BIT_CLEAR_HCI_HRPWM2(x) | BIT_HCI_HRPWM2(v))
-/* 2 REG_Q1_INFO (Offset 0x0404) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_TAIL_PKT_Q1_V2 11
-#define BIT_MASK_TAIL_PKT_Q1_V2 0x7ff
-#define BIT_TAIL_PKT_Q1_V2(x) (((x) & BIT_MASK_TAIL_PKT_Q1_V2) << BIT_SHIFT_TAIL_PKT_Q1_V2)
-#define BIT_GET_TAIL_PKT_Q1_V2(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2) & BIT_MASK_TAIL_PKT_Q1_V2)
+/* 2 REG_PCIE_HCPWM2_V1 (Offset 0x03DE) */
+#define BIT_SHIFT_PCIE_HCPWM2 0
+#define BIT_MASK_PCIE_HCPWM2 0xffff
+#define BIT_PCIE_HCPWM2(x) \
+ (((x) & BIT_MASK_PCIE_HCPWM2) << BIT_SHIFT_PCIE_HCPWM2)
+#define BITS_PCIE_HCPWM2 (BIT_MASK_PCIE_HCPWM2 << BIT_SHIFT_PCIE_HCPWM2)
+#define BIT_CLEAR_PCIE_HCPWM2(x) ((x) & (~BITS_PCIE_HCPWM2))
+#define BIT_GET_PCIE_HCPWM2(x) \
+ (((x) >> BIT_SHIFT_PCIE_HCPWM2) & BIT_MASK_PCIE_HCPWM2)
+#define BIT_SET_PCIE_HCPWM2(x, v) \
+ (BIT_CLEAR_PCIE_HCPWM2(x) | BIT_PCIE_HCPWM2(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_HCI_HCPWM2_V1 (Offset 0x03DE) */
+#define BIT_SHIFT_HCI_HCPWM2 0
+#define BIT_MASK_HCI_HCPWM2 0xffff
+#define BIT_HCI_HCPWM2(x) (((x) & BIT_MASK_HCI_HCPWM2) << BIT_SHIFT_HCI_HCPWM2)
+#define BITS_HCI_HCPWM2 (BIT_MASK_HCI_HCPWM2 << BIT_SHIFT_HCI_HCPWM2)
+#define BIT_CLEAR_HCI_HCPWM2(x) ((x) & (~BITS_HCI_HCPWM2))
+#define BIT_GET_HCI_HCPWM2(x) \
+ (((x) >> BIT_SHIFT_HCI_HCPWM2) & BIT_MASK_HCI_HCPWM2)
+#define BIT_SET_HCI_HCPWM2(x, v) (BIT_CLEAR_HCI_HCPWM2(x) | BIT_HCI_HCPWM2(v))
-/* 2 REG_Q1_INFO (Offset 0x0404) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_PKT_NUM_Q1_V1 8
-#define BIT_MASK_PKT_NUM_Q1_V1 0x7f
-#define BIT_PKT_NUM_Q1_V1(x) (((x) & BIT_MASK_PKT_NUM_Q1_V1) << BIT_SHIFT_PKT_NUM_Q1_V1)
-#define BIT_GET_PKT_NUM_Q1_V1(x) (((x) >> BIT_SHIFT_PKT_NUM_Q1_V1) & BIT_MASK_PKT_NUM_Q1_V1)
+/* 2 REG_PCIE_H2C_MSG_V1 (Offset 0x03E0) */
+#define BIT_AC7Q_EMPTY BIT(7)
+#define BIT_AC6Q_EMPTY BIT(6)
+#define BIT_AC5Q_EMPTY BIT(5)
+#define BIT_AC4Q_EMPTY BIT(4)
+#define BIT_AC3Q_EMPTY BIT(3)
+#define BIT_AC2Q_EMPTY BIT(2)
+#define BIT_AC1Q_EMPTY BIT(1)
-#define BIT_SHIFT_HEAD_PKT_Q1 0
-#define BIT_MASK_HEAD_PKT_Q1 0xff
-#define BIT_HEAD_PKT_Q1(x) (((x) & BIT_MASK_HEAD_PKT_Q1) << BIT_SHIFT_HEAD_PKT_Q1)
-#define BIT_GET_HEAD_PKT_Q1(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q1) & BIT_MASK_HEAD_PKT_Q1)
+#define BIT_SHIFT_DRV2FW_INFO 0
+#define BIT_MASK_DRV2FW_INFO 0xffffffffL
+#define BIT_DRV2FW_INFO(x) \
+ (((x) & BIT_MASK_DRV2FW_INFO) << BIT_SHIFT_DRV2FW_INFO)
+#define BITS_DRV2FW_INFO (BIT_MASK_DRV2FW_INFO << BIT_SHIFT_DRV2FW_INFO)
+#define BIT_CLEAR_DRV2FW_INFO(x) ((x) & (~BITS_DRV2FW_INFO))
+#define BIT_GET_DRV2FW_INFO(x) \
+ (((x) >> BIT_SHIFT_DRV2FW_INFO) & BIT_MASK_DRV2FW_INFO)
+#define BIT_SET_DRV2FW_INFO(x, v) \
+ (BIT_CLEAR_DRV2FW_INFO(x) | BIT_DRV2FW_INFO(v))
+#define BIT_AC0Q_EMPTY BIT(0)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_PCIE_C2H_MSG_V1 (Offset 0x03E4) */
+#define BIT_SHIFT_HCI_PCIE_C2H_MSG 0
+#define BIT_MASK_HCI_PCIE_C2H_MSG 0xffffffffL
+#define BIT_HCI_PCIE_C2H_MSG(x) \
+ (((x) & BIT_MASK_HCI_PCIE_C2H_MSG) << BIT_SHIFT_HCI_PCIE_C2H_MSG)
+#define BITS_HCI_PCIE_C2H_MSG \
+ (BIT_MASK_HCI_PCIE_C2H_MSG << BIT_SHIFT_HCI_PCIE_C2H_MSG)
+#define BIT_CLEAR_HCI_PCIE_C2H_MSG(x) ((x) & (~BITS_HCI_PCIE_C2H_MSG))
+#define BIT_GET_HCI_PCIE_C2H_MSG(x) \
+ (((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG) & BIT_MASK_HCI_PCIE_C2H_MSG)
+#define BIT_SET_HCI_PCIE_C2H_MSG(x, v) \
+ (BIT_CLEAR_HCI_PCIE_C2H_MSG(x) | BIT_HCI_PCIE_C2H_MSG(v))
-/* 2 REG_Q1_INFO (Offset 0x0404) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_HEAD_PKT_Q1_V1 0
-#define BIT_MASK_HEAD_PKT_Q1_V1 0x7ff
-#define BIT_HEAD_PKT_Q1_V1(x) (((x) & BIT_MASK_HEAD_PKT_Q1_V1) << BIT_SHIFT_HEAD_PKT_Q1_V1)
-#define BIT_GET_HEAD_PKT_Q1_V1(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1) & BIT_MASK_HEAD_PKT_Q1_V1)
+/* 2 REG_HCI_C2H_MSG_V1 (Offset 0x03E4) */
+#define BIT_SHIFT_HCI_C2H_MSG 0
+#define BIT_MASK_HCI_C2H_MSG 0xffffffffL
+#define BIT_HCI_C2H_MSG(x) \
+ (((x) & BIT_MASK_HCI_C2H_MSG) << BIT_SHIFT_HCI_C2H_MSG)
+#define BITS_HCI_C2H_MSG (BIT_MASK_HCI_C2H_MSG << BIT_SHIFT_HCI_C2H_MSG)
+#define BIT_CLEAR_HCI_C2H_MSG(x) ((x) & (~BITS_HCI_C2H_MSG))
+#define BIT_GET_HCI_C2H_MSG(x) \
+ (((x) >> BIT_SHIFT_HCI_C2H_MSG) & BIT_MASK_HCI_C2H_MSG)
+#define BIT_SET_HCI_C2H_MSG(x, v) \
+ (BIT_CLEAR_HCI_C2H_MSG(x) | BIT_HCI_C2H_MSG(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_DBI_WDATA_V1 (Offset 0x03E8) */
+#define BIT_SHIFT_DBI_WDATA 0
+#define BIT_MASK_DBI_WDATA 0xffffffffL
+#define BIT_DBI_WDATA(x) (((x) & BIT_MASK_DBI_WDATA) << BIT_SHIFT_DBI_WDATA)
+#define BITS_DBI_WDATA (BIT_MASK_DBI_WDATA << BIT_SHIFT_DBI_WDATA)
+#define BIT_CLEAR_DBI_WDATA(x) ((x) & (~BITS_DBI_WDATA))
+#define BIT_GET_DBI_WDATA(x) (((x) >> BIT_SHIFT_DBI_WDATA) & BIT_MASK_DBI_WDATA)
+#define BIT_SET_DBI_WDATA(x, v) (BIT_CLEAR_DBI_WDATA(x) | BIT_DBI_WDATA(v))
-/* 2 REG_Q2_INFO (Offset 0x0408) */
+/* 2 REG_DBI_RDATA_V1 (Offset 0x03EC) */
+#define BIT_SHIFT_DBI_RDATA 0
+#define BIT_MASK_DBI_RDATA 0xffffffffL
+#define BIT_DBI_RDATA(x) (((x) & BIT_MASK_DBI_RDATA) << BIT_SHIFT_DBI_RDATA)
+#define BITS_DBI_RDATA (BIT_MASK_DBI_RDATA << BIT_SHIFT_DBI_RDATA)
+#define BIT_CLEAR_DBI_RDATA(x) ((x) & (~BITS_DBI_RDATA))
+#define BIT_GET_DBI_RDATA(x) (((x) >> BIT_SHIFT_DBI_RDATA) & BIT_MASK_DBI_RDATA)
+#define BIT_SET_DBI_RDATA(x, v) (BIT_CLEAR_DBI_RDATA(x) | BIT_DBI_RDATA(v))
-#define BIT_SHIFT_QUEUEMACID_Q2_V1 25
-#define BIT_MASK_QUEUEMACID_Q2_V1 0x7f
-#define BIT_QUEUEMACID_Q2_V1(x) (((x) & BIT_MASK_QUEUEMACID_Q2_V1) << BIT_SHIFT_QUEUEMACID_Q2_V1)
-#define BIT_GET_QUEUEMACID_Q2_V1(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1) & BIT_MASK_QUEUEMACID_Q2_V1)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_QUEUEAC_Q2_V1 23
-#define BIT_MASK_QUEUEAC_Q2_V1 0x3
-#define BIT_QUEUEAC_Q2_V1(x) (((x) & BIT_MASK_QUEUEAC_Q2_V1) << BIT_SHIFT_QUEUEAC_Q2_V1)
-#define BIT_GET_QUEUEAC_Q2_V1(x) (((x) >> BIT_SHIFT_QUEUEAC_Q2_V1) & BIT_MASK_QUEUEAC_Q2_V1)
+/* 2 REG_DBI_FLAG_V1 (Offset 0x03F0) */
+#define BIT_SHIFT_LOOPBACK_DBG_SEL 28
+#define BIT_MASK_LOOPBACK_DBG_SEL 0xf
+#define BIT_LOOPBACK_DBG_SEL(x) \
+ (((x) & BIT_MASK_LOOPBACK_DBG_SEL) << BIT_SHIFT_LOOPBACK_DBG_SEL)
+#define BITS_LOOPBACK_DBG_SEL \
+ (BIT_MASK_LOOPBACK_DBG_SEL << BIT_SHIFT_LOOPBACK_DBG_SEL)
+#define BIT_CLEAR_LOOPBACK_DBG_SEL(x) ((x) & (~BITS_LOOPBACK_DBG_SEL))
+#define BIT_GET_LOOPBACK_DBG_SEL(x) \
+ (((x) >> BIT_SHIFT_LOOPBACK_DBG_SEL) & BIT_MASK_LOOPBACK_DBG_SEL)
+#define BIT_SET_LOOPBACK_DBG_SEL(x, v) \
+ (BIT_CLEAR_LOOPBACK_DBG_SEL(x) | BIT_LOOPBACK_DBG_SEL(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_DBI_FLAG_V1 (Offset 0x03F0) */
+#define BIT_EN_STUCK_DBG BIT(26)
+#define BIT_RX_STUCK BIT(25)
+#define BIT_TX_STUCK BIT(24)
+#define BIT_DBI_RFLAG BIT(17)
+#define BIT_DBI_WFLAG BIT(16)
+
+#define BIT_SHIFT_DBI_WREN 12
+#define BIT_MASK_DBI_WREN 0xf
+#define BIT_DBI_WREN(x) (((x) & BIT_MASK_DBI_WREN) << BIT_SHIFT_DBI_WREN)
+#define BITS_DBI_WREN (BIT_MASK_DBI_WREN << BIT_SHIFT_DBI_WREN)
+#define BIT_CLEAR_DBI_WREN(x) ((x) & (~BITS_DBI_WREN))
+#define BIT_GET_DBI_WREN(x) (((x) >> BIT_SHIFT_DBI_WREN) & BIT_MASK_DBI_WREN)
+#define BIT_SET_DBI_WREN(x, v) (BIT_CLEAR_DBI_WREN(x) | BIT_DBI_WREN(v))
+
+#define BIT_SHIFT_DBI_ADDR 0
+#define BIT_MASK_DBI_ADDR 0xfff
+#define BIT_DBI_ADDR(x) (((x) & BIT_MASK_DBI_ADDR) << BIT_SHIFT_DBI_ADDR)
+#define BITS_DBI_ADDR (BIT_MASK_DBI_ADDR << BIT_SHIFT_DBI_ADDR)
+#define BIT_CLEAR_DBI_ADDR(x) ((x) & (~BITS_DBI_ADDR))
+#define BIT_GET_DBI_ADDR(x) (((x) >> BIT_SHIFT_DBI_ADDR) & BIT_MASK_DBI_ADDR)
+#define BIT_SET_DBI_ADDR(x, v) (BIT_CLEAR_DBI_ADDR(x) | BIT_DBI_ADDR(v))
-/* 2 REG_Q2_INFO (Offset 0x0408) */
+/* 2 REG_MDIO_V1 (Offset 0x03F4) */
+
+#define BIT_SHIFT_MDIO_RDATA 16
+#define BIT_MASK_MDIO_RDATA 0xffff
+#define BIT_MDIO_RDATA(x) (((x) & BIT_MASK_MDIO_RDATA) << BIT_SHIFT_MDIO_RDATA)
+#define BITS_MDIO_RDATA (BIT_MASK_MDIO_RDATA << BIT_SHIFT_MDIO_RDATA)
+#define BIT_CLEAR_MDIO_RDATA(x) ((x) & (~BITS_MDIO_RDATA))
+#define BIT_GET_MDIO_RDATA(x) \
+ (((x) >> BIT_SHIFT_MDIO_RDATA) & BIT_MASK_MDIO_RDATA)
+#define BIT_SET_MDIO_RDATA(x, v) (BIT_CLEAR_MDIO_RDATA(x) | BIT_MDIO_RDATA(v))
-#define BIT_TIDEMPTY_Q2_V1 BIT(22)
+#define BIT_SHIFT_MDIO_WDATA 0
+#define BIT_MASK_MDIO_WDATA 0xffff
+#define BIT_MDIO_WDATA(x) (((x) & BIT_MASK_MDIO_WDATA) << BIT_SHIFT_MDIO_WDATA)
+#define BITS_MDIO_WDATA (BIT_MASK_MDIO_WDATA << BIT_SHIFT_MDIO_WDATA)
+#define BIT_CLEAR_MDIO_WDATA(x) ((x) & (~BITS_MDIO_WDATA))
+#define BIT_GET_MDIO_WDATA(x) \
+ (((x) >> BIT_SHIFT_MDIO_WDATA) & BIT_MASK_MDIO_WDATA)
+#define BIT_SET_MDIO_WDATA(x, v) (BIT_CLEAR_MDIO_WDATA(x) | BIT_MDIO_WDATA(v))
#endif
+#if (HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_BUS_MIX_CFG (Offset 0x03F8) */
+#define BIT_SHIFT_DELAY_TIME 24
+#define BIT_MASK_DELAY_TIME 0xff
+#define BIT_DELAY_TIME(x) (((x) & BIT_MASK_DELAY_TIME) << BIT_SHIFT_DELAY_TIME)
+#define BITS_DELAY_TIME (BIT_MASK_DELAY_TIME << BIT_SHIFT_DELAY_TIME)
+#define BIT_CLEAR_DELAY_TIME(x) ((x) & (~BITS_DELAY_TIME))
+#define BIT_GET_DELAY_TIME(x) \
+ (((x) >> BIT_SHIFT_DELAY_TIME) & BIT_MASK_DELAY_TIME)
+#define BIT_SET_DELAY_TIME(x, v) (BIT_CLEAR_DELAY_TIME(x) | BIT_DELAY_TIME(v))
-/* 2 REG_Q2_INFO (Offset 0x0408) */
+#define BIT_RX_TIMER_DELAY_EN BIT(17)
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_TAIL_PKT_Q2_V1 15
-#define BIT_MASK_TAIL_PKT_Q2_V1 0xff
-#define BIT_TAIL_PKT_Q2_V1(x) (((x) & BIT_MASK_TAIL_PKT_Q2_V1) << BIT_SHIFT_TAIL_PKT_Q2_V1)
-#define BIT_GET_TAIL_PKT_Q2_V1(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V1) & BIT_MASK_TAIL_PKT_Q2_V1)
+/* 2 REG_PCIE_MIX_CFG (Offset 0x03F8) */
+#define BIT_EN_WATCH_DOG BIT(8)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+/* 2 REG_MDIO2_V1 (Offset 0x03F8) */
-/* 2 REG_Q2_INFO (Offset 0x0408) */
+#define BIT_ECRC_EN BIT(7)
+#define BIT_MDIO_RFLAG BIT(6)
+#define BIT_MDIO_WFLAG BIT(5)
+#endif
-#define BIT_SHIFT_TAIL_PKT_Q2_V2 11
-#define BIT_MASK_TAIL_PKT_Q2_V2 0x7ff
-#define BIT_TAIL_PKT_Q2_V2(x) (((x) & BIT_MASK_TAIL_PKT_Q2_V2) << BIT_SHIFT_TAIL_PKT_Q2_V2)
-#define BIT_GET_TAIL_PKT_Q2_V2(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2) & BIT_MASK_TAIL_PKT_Q2_V2)
+#if (HALMAC_8192E_SUPPORT)
+/* 2 REG_MDIO2_V1 (Offset 0x03F8) */
-#endif
+#define BIT_SHIFT_MDIO_ADDR 0
+#define BIT_MASK_MDIO_ADDR 0x1f
+#define BIT_MDIO_ADDR(x) (((x) & BIT_MASK_MDIO_ADDR) << BIT_SHIFT_MDIO_ADDR)
+#define BITS_MDIO_ADDR (BIT_MASK_MDIO_ADDR << BIT_SHIFT_MDIO_ADDR)
+#define BIT_CLEAR_MDIO_ADDR(x) ((x) & (~BITS_MDIO_ADDR))
+#define BIT_GET_MDIO_ADDR(x) (((x) >> BIT_SHIFT_MDIO_ADDR) & BIT_MASK_MDIO_ADDR)
+#define BIT_SET_MDIO_ADDR(x, v) (BIT_CLEAR_MDIO_ADDR(x) | BIT_MDIO_ADDR(v))
+#define BIT_SHIFT_TXFAIL_DROPCNT 0
+#define BIT_MASK_TXFAIL_DROPCNT 0xffff
+#define BIT_TXFAIL_DROPCNT(x) \
+ (((x) & BIT_MASK_TXFAIL_DROPCNT) << BIT_SHIFT_TXFAIL_DROPCNT)
+#define BITS_TXFAIL_DROPCNT \
+ (BIT_MASK_TXFAIL_DROPCNT << BIT_SHIFT_TXFAIL_DROPCNT)
+#define BIT_CLEAR_TXFAIL_DROPCNT(x) ((x) & (~BITS_TXFAIL_DROPCNT))
+#define BIT_GET_TXFAIL_DROPCNT(x) \
+ (((x) >> BIT_SHIFT_TXFAIL_DROPCNT) & BIT_MASK_TXFAIL_DROPCNT)
+#define BIT_SET_TXFAIL_DROPCNT(x, v) \
+ (BIT_CLEAR_TXFAIL_DROPCNT(x) | BIT_TXFAIL_DROPCNT(v))
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_Q2_INFO (Offset 0x0408) */
+/* 2 REG_PCIE_MIX_CFG (Offset 0x03F8) */
+#define BIT_SHIFT_MDIO_REG_ADDR_V1 0
+#define BIT_MASK_MDIO_REG_ADDR_V1 0x1f
+#define BIT_MDIO_REG_ADDR_V1(x) \
+ (((x) & BIT_MASK_MDIO_REG_ADDR_V1) << BIT_SHIFT_MDIO_REG_ADDR_V1)
+#define BITS_MDIO_REG_ADDR_V1 \
+ (BIT_MASK_MDIO_REG_ADDR_V1 << BIT_SHIFT_MDIO_REG_ADDR_V1)
+#define BIT_CLEAR_MDIO_REG_ADDR_V1(x) ((x) & (~BITS_MDIO_REG_ADDR_V1))
+#define BIT_GET_MDIO_REG_ADDR_V1(x) \
+ (((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1) & BIT_MASK_MDIO_REG_ADDR_V1)
+#define BIT_SET_MDIO_REG_ADDR_V1(x, v) \
+ (BIT_CLEAR_MDIO_REG_ADDR_V1(x) | BIT_MDIO_REG_ADDR_V1(v))
-#define BIT_SHIFT_PKT_NUM_Q2_V1 8
-#define BIT_MASK_PKT_NUM_Q2_V1 0x7f
-#define BIT_PKT_NUM_Q2_V1(x) (((x) & BIT_MASK_PKT_NUM_Q2_V1) << BIT_SHIFT_PKT_NUM_Q2_V1)
-#define BIT_GET_PKT_NUM_Q2_V1(x) (((x) >> BIT_SHIFT_PKT_NUM_Q2_V1) & BIT_MASK_PKT_NUM_Q2_V1)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define BIT_SHIFT_HEAD_PKT_Q2 0
-#define BIT_MASK_HEAD_PKT_Q2 0xff
-#define BIT_HEAD_PKT_Q2(x) (((x) & BIT_MASK_HEAD_PKT_Q2) << BIT_SHIFT_HEAD_PKT_Q2)
-#define BIT_GET_HEAD_PKT_Q2(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q2) & BIT_MASK_HEAD_PKT_Q2)
+/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */
+#define BIT_RXRST_BACKDOOR BIT(31)
+#define BIT_TXRST_BACKDOOR BIT(30)
+#define BIT_RXIDX_RSTB BIT(29)
+#define BIT_TXIDX_RSTB BIT(28)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */
+#define BIT_SHIFT_WATCH_DOG_TIMER 28
+#define BIT_MASK_WATCH_DOG_TIMER 0xf
+#define BIT_WATCH_DOG_TIMER(x) \
+ (((x) & BIT_MASK_WATCH_DOG_TIMER) << BIT_SHIFT_WATCH_DOG_TIMER)
+#define BITS_WATCH_DOG_TIMER \
+ (BIT_MASK_WATCH_DOG_TIMER << BIT_SHIFT_WATCH_DOG_TIMER)
+#define BIT_CLEAR_WATCH_DOG_TIMER(x) ((x) & (~BITS_WATCH_DOG_TIMER))
+#define BIT_GET_WATCH_DOG_TIMER(x) \
+ (((x) >> BIT_SHIFT_WATCH_DOG_TIMER) & BIT_MASK_WATCH_DOG_TIMER)
+#define BIT_SET_WATCH_DOG_TIMER(x, v) \
+ (BIT_CLEAR_WATCH_DOG_TIMER(x) | BIT_WATCH_DOG_TIMER(v))
-/* 2 REG_Q2_INFO (Offset 0x0408) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define BIT_SHIFT_HEAD_PKT_Q2_V1 0
-#define BIT_MASK_HEAD_PKT_Q2_V1 0x7ff
-#define BIT_HEAD_PKT_Q2_V1(x) (((x) & BIT_MASK_HEAD_PKT_Q2_V1) << BIT_SHIFT_HEAD_PKT_Q2_V1)
-#define BIT_GET_HEAD_PKT_Q2_V1(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1) & BIT_MASK_HEAD_PKT_Q2_V1)
+/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */
+#define BIT_DROP_NEXT_RXPKT BIT(27)
+#define BIT_SHORT_CORE_RST_SEL BIT(26)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */
+#define BIT_EXCEPT_RESUME_EN BIT(25)
+#define BIT_EXCEPT_RESUME_FLAG BIT(24)
-/* 2 REG_Q3_INFO (Offset 0x040C) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define BIT_SHIFT_QUEUEMACID_Q3_V1 25
-#define BIT_MASK_QUEUEMACID_Q3_V1 0x7f
-#define BIT_QUEUEMACID_Q3_V1(x) (((x) & BIT_MASK_QUEUEMACID_Q3_V1) << BIT_SHIFT_QUEUEMACID_Q3_V1)
-#define BIT_GET_QUEUEMACID_Q3_V1(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1) & BIT_MASK_QUEUEMACID_Q3_V1)
+/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */
+#define BIT_ALIGN_MTU BIT(23)
-#define BIT_SHIFT_QUEUEAC_Q3_V1 23
-#define BIT_MASK_QUEUEAC_Q3_V1 0x3
-#define BIT_QUEUEAC_Q3_V1(x) (((x) & BIT_MASK_QUEUEAC_Q3_V1) << BIT_SHIFT_QUEUEAC_Q3_V1)
-#define BIT_GET_QUEUEAC_Q3_V1(x) (((x) >> BIT_SHIFT_QUEUEAC_Q3_V1) & BIT_MASK_QUEUEAC_Q3_V1)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */
+#define BIT_EN_ALIGN_MTU BIT(23)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814AMP_SUPPORT)
-/* 2 REG_Q3_INFO (Offset 0x040C) */
+/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */
-#define BIT_TIDEMPTY_Q3_V1 BIT(22)
+#define BIT_EARLY_TAG_RETURN BIT(22)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */
+#define BIT_SHIFT_LATENCY_CONTROL 21
+#define BIT_MASK_LATENCY_CONTROL 0x3
+#define BIT_LATENCY_CONTROL(x) \
+ (((x) & BIT_MASK_LATENCY_CONTROL) << BIT_SHIFT_LATENCY_CONTROL)
+#define BITS_LATENCY_CONTROL \
+ (BIT_MASK_LATENCY_CONTROL << BIT_SHIFT_LATENCY_CONTROL)
+#define BIT_CLEAR_LATENCY_CONTROL(x) ((x) & (~BITS_LATENCY_CONTROL))
+#define BIT_GET_LATENCY_CONTROL(x) \
+ (((x) >> BIT_SHIFT_LATENCY_CONTROL) & BIT_MASK_LATENCY_CONTROL)
+#define BIT_SET_LATENCY_CONTROL(x, v) \
+ (BIT_CLEAR_LATENCY_CONTROL(x) | BIT_LATENCY_CONTROL(v))
-/* 2 REG_Q3_INFO (Offset 0x040C) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_TAIL_PKT_Q3_V1 15
-#define BIT_MASK_TAIL_PKT_Q3_V1 0xff
-#define BIT_TAIL_PKT_Q3_V1(x) (((x) & BIT_MASK_TAIL_PKT_Q3_V1) << BIT_SHIFT_TAIL_PKT_Q3_V1)
-#define BIT_GET_TAIL_PKT_Q3_V1(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V1) & BIT_MASK_TAIL_PKT_Q3_V1)
+/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */
+#define BIT_HOST_GEN2_SUPPORT BIT(20)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */
+#define BIT_SHIFT_TXDMA_ERR_FLAG 16
+#define BIT_MASK_TXDMA_ERR_FLAG 0xf
+#define BIT_TXDMA_ERR_FLAG(x) \
+ (((x) & BIT_MASK_TXDMA_ERR_FLAG) << BIT_SHIFT_TXDMA_ERR_FLAG)
+#define BITS_TXDMA_ERR_FLAG \
+ (BIT_MASK_TXDMA_ERR_FLAG << BIT_SHIFT_TXDMA_ERR_FLAG)
+#define BIT_CLEAR_TXDMA_ERR_FLAG(x) ((x) & (~BITS_TXDMA_ERR_FLAG))
+#define BIT_GET_TXDMA_ERR_FLAG(x) \
+ (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG) & BIT_MASK_TXDMA_ERR_FLAG)
+#define BIT_SET_TXDMA_ERR_FLAG(x, v) \
+ (BIT_CLEAR_TXDMA_ERR_FLAG(x) | BIT_TXDMA_ERR_FLAG(v))
-/* 2 REG_Q3_INFO (Offset 0x040C) */
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_TAIL_PKT_Q3_V2 11
-#define BIT_MASK_TAIL_PKT_Q3_V2 0x7ff
-#define BIT_TAIL_PKT_Q3_V2(x) (((x) & BIT_MASK_TAIL_PKT_Q3_V2) << BIT_SHIFT_TAIL_PKT_Q3_V2)
-#define BIT_GET_TAIL_PKT_Q3_V2(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2) & BIT_MASK_TAIL_PKT_Q3_V2)
+/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */
+#define BIT_SHIFT_TXDMA_ERR_FLAG_V1 15
+#define BIT_MASK_TXDMA_ERR_FLAG_V1 0x1f
+#define BIT_TXDMA_ERR_FLAG_V1(x) \
+ (((x) & BIT_MASK_TXDMA_ERR_FLAG_V1) << BIT_SHIFT_TXDMA_ERR_FLAG_V1)
+#define BITS_TXDMA_ERR_FLAG_V1 \
+ (BIT_MASK_TXDMA_ERR_FLAG_V1 << BIT_SHIFT_TXDMA_ERR_FLAG_V1)
+#define BIT_CLEAR_TXDMA_ERR_FLAG_V1(x) ((x) & (~BITS_TXDMA_ERR_FLAG_V1))
+#define BIT_GET_TXDMA_ERR_FLAG_V1(x) \
+ (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_V1) & BIT_MASK_TXDMA_ERR_FLAG_V1)
+#define BIT_SET_TXDMA_ERR_FLAG_V1(x, v) \
+ (BIT_CLEAR_TXDMA_ERR_FLAG_V1(x) | BIT_TXDMA_ERR_FLAG_V1(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
+/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */
-/* 2 REG_Q3_INFO (Offset 0x040C) */
+#define BIT_SHIFT_EARLY_MODE_SEL 12
+#define BIT_MASK_EARLY_MODE_SEL 0xf
+#define BIT_EARLY_MODE_SEL(x) \
+ (((x) & BIT_MASK_EARLY_MODE_SEL) << BIT_SHIFT_EARLY_MODE_SEL)
+#define BITS_EARLY_MODE_SEL \
+ (BIT_MASK_EARLY_MODE_SEL << BIT_SHIFT_EARLY_MODE_SEL)
+#define BIT_CLEAR_EARLY_MODE_SEL(x) ((x) & (~BITS_EARLY_MODE_SEL))
+#define BIT_GET_EARLY_MODE_SEL(x) \
+ (((x) >> BIT_SHIFT_EARLY_MODE_SEL) & BIT_MASK_EARLY_MODE_SEL)
+#define BIT_SET_EARLY_MODE_SEL(x, v) \
+ (BIT_CLEAR_EARLY_MODE_SEL(x) | BIT_EARLY_MODE_SEL(v))
+#endif
-#define BIT_SHIFT_PKT_NUM_Q3_V1 8
-#define BIT_MASK_PKT_NUM_Q3_V1 0x7f
-#define BIT_PKT_NUM_Q3_V1(x) (((x) & BIT_MASK_PKT_NUM_Q3_V1) << BIT_SHIFT_PKT_NUM_Q3_V1)
-#define BIT_GET_PKT_NUM_Q3_V1(x) (((x) >> BIT_SHIFT_PKT_NUM_Q3_V1) & BIT_MASK_PKT_NUM_Q3_V1)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */
-#define BIT_SHIFT_HEAD_PKT_Q3 0
-#define BIT_MASK_HEAD_PKT_Q3 0xff
-#define BIT_HEAD_PKT_Q3(x) (((x) & BIT_MASK_HEAD_PKT_Q3) << BIT_SHIFT_HEAD_PKT_Q3)
-#define BIT_GET_HEAD_PKT_Q3(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q3) & BIT_MASK_HEAD_PKT_Q3)
+#define BIT_EPHY_RX50_EN BIT(11)
+#define BIT_SHIFT_MSI_TIMEOUT_ID_V1 8
+#define BIT_MASK_MSI_TIMEOUT_ID_V1 0x7
+#define BIT_MSI_TIMEOUT_ID_V1(x) \
+ (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1) << BIT_SHIFT_MSI_TIMEOUT_ID_V1)
+#define BITS_MSI_TIMEOUT_ID_V1 \
+ (BIT_MASK_MSI_TIMEOUT_ID_V1 << BIT_SHIFT_MSI_TIMEOUT_ID_V1)
+#define BIT_CLEAR_MSI_TIMEOUT_ID_V1(x) ((x) & (~BITS_MSI_TIMEOUT_ID_V1))
+#define BIT_GET_MSI_TIMEOUT_ID_V1(x) \
+ (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1) & BIT_MASK_MSI_TIMEOUT_ID_V1)
+#define BIT_SET_MSI_TIMEOUT_ID_V1(x, v) \
+ (BIT_CLEAR_MSI_TIMEOUT_ID_V1(x) | BIT_MSI_TIMEOUT_ID_V1(v))
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */
+#define BIT_SHIFT_RXDMA_ERR_CNT 8
+#define BIT_MASK_RXDMA_ERR_CNT 0xff
+#define BIT_RXDMA_ERR_CNT(x) \
+ (((x) & BIT_MASK_RXDMA_ERR_CNT) << BIT_SHIFT_RXDMA_ERR_CNT)
+#define BITS_RXDMA_ERR_CNT (BIT_MASK_RXDMA_ERR_CNT << BIT_SHIFT_RXDMA_ERR_CNT)
+#define BIT_CLEAR_RXDMA_ERR_CNT(x) ((x) & (~BITS_RXDMA_ERR_CNT))
+#define BIT_GET_RXDMA_ERR_CNT(x) \
+ (((x) >> BIT_SHIFT_RXDMA_ERR_CNT) & BIT_MASK_RXDMA_ERR_CNT)
+#define BIT_SET_RXDMA_ERR_CNT(x, v) \
+ (BIT_CLEAR_RXDMA_ERR_CNT(x) | BIT_RXDMA_ERR_CNT(v))
-/* 2 REG_Q3_INFO (Offset 0x040C) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_HEAD_PKT_Q3_V1 0
-#define BIT_MASK_HEAD_PKT_Q3_V1 0x7ff
-#define BIT_HEAD_PKT_Q3_V1(x) (((x) & BIT_MASK_HEAD_PKT_Q3_V1) << BIT_SHIFT_HEAD_PKT_Q3_V1)
-#define BIT_GET_HEAD_PKT_Q3_V1(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1) & BIT_MASK_HEAD_PKT_Q3_V1)
+/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */
+#define BIT_RADDR_RD BIT(7)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */
+#define BIT_TXDMA_ERR_HANDLE_REQ BIT(7)
-/* 2 REG_MGQ_INFO (Offset 0x0410) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_QUEUEMACID_MGQ_V1 25
-#define BIT_MASK_QUEUEMACID_MGQ_V1 0x7f
-#define BIT_QUEUEMACID_MGQ_V1(x) (((x) & BIT_MASK_QUEUEMACID_MGQ_V1) << BIT_SHIFT_QUEUEMACID_MGQ_V1)
-#define BIT_GET_QUEUEMACID_MGQ_V1(x) (((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1) & BIT_MASK_QUEUEMACID_MGQ_V1)
+/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */
+#define BIT_EN_MUL_TAG BIT(6)
-#define BIT_SHIFT_QUEUEAC_MGQ_V1 23
-#define BIT_MASK_QUEUEAC_MGQ_V1 0x3
-#define BIT_QUEUEAC_MGQ_V1(x) (((x) & BIT_MASK_QUEUEAC_MGQ_V1) << BIT_SHIFT_QUEUEAC_MGQ_V1)
-#define BIT_GET_QUEUEAC_MGQ_V1(x) (((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1) & BIT_MASK_QUEUEAC_MGQ_V1)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */
+#define BIT_TXDMA_ERROR_PS BIT(6)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8822C_SUPPORT)
-/* 2 REG_MGQ_INFO (Offset 0x0410) */
+/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */
-#define BIT_TIDEMPTY_MGQ_V1 BIT(22)
+#define BIT_L1OFF_PWR_OFF_EN BIT(6)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */
+#define BIT_EN_EARLY_MODE BIT(5)
-/* 2 REG_MGQ_INFO (Offset 0x0410) */
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_TAIL_PKT_MGQ_V1 15
-#define BIT_MASK_TAIL_PKT_MGQ_V1 0xff
-#define BIT_TAIL_PKT_MGQ_V1(x) (((x) & BIT_MASK_TAIL_PKT_MGQ_V1) << BIT_SHIFT_TAIL_PKT_MGQ_V1)
-#define BIT_GET_TAIL_PKT_MGQ_V1(x) (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V1) & BIT_MASK_TAIL_PKT_MGQ_V1)
+/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */
+#define BIT_EN_TXDMA_STUCK_ERR_HANDLE BIT(5)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */
+#define BIT_L0S_LINK_OFF BIT(4)
-/* 2 REG_MGQ_INFO (Offset 0x0410) */
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_TAIL_PKT_MGQ_V2 11
-#define BIT_MASK_TAIL_PKT_MGQ_V2 0x7ff
-#define BIT_TAIL_PKT_MGQ_V2(x) (((x) & BIT_MASK_TAIL_PKT_MGQ_V2) << BIT_SHIFT_TAIL_PKT_MGQ_V2)
-#define BIT_GET_TAIL_PKT_MGQ_V2(x) (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2) & BIT_MASK_TAIL_PKT_MGQ_V2)
+/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */
+#define BIT_EN_TXDMA_RTN_ERR_HANDLE BIT(4)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */
+#define BIT_ACT_LINK_OFF BIT(3)
-/* 2 REG_MGQ_INFO (Offset 0x0410) */
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */
+
+#define BIT_RXDMA_ERR_HANDLE_REQ BIT(3)
-#define BIT_SHIFT_PKT_NUM_MGQ_V1 8
-#define BIT_MASK_PKT_NUM_MGQ_V1 0x7f
-#define BIT_PKT_NUM_MGQ_V1(x) (((x) & BIT_MASK_PKT_NUM_MGQ_V1) << BIT_SHIFT_PKT_NUM_MGQ_V1)
-#define BIT_GET_PKT_NUM_MGQ_V1(x) (((x) >> BIT_SHIFT_PKT_NUM_MGQ_V1) & BIT_MASK_PKT_NUM_MGQ_V1)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_HEAD_PKT_MGQ 0
-#define BIT_MASK_HEAD_PKT_MGQ 0xff
-#define BIT_HEAD_PKT_MGQ(x) (((x) & BIT_MASK_HEAD_PKT_MGQ) << BIT_SHIFT_HEAD_PKT_MGQ)
-#define BIT_GET_HEAD_PKT_MGQ(x) (((x) >> BIT_SHIFT_HEAD_PKT_MGQ) & BIT_MASK_HEAD_PKT_MGQ)
+/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */
+#define BIT_EN_SLOW_MAC_TX BIT(2)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */
+#define BIT_RXDMA_ERROR_PS BIT(2)
-/* 2 REG_MGQ_INFO (Offset 0x0410) */
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_HEAD_PKT_MGQ_V1 0
-#define BIT_MASK_HEAD_PKT_MGQ_V1 0x7ff
-#define BIT_HEAD_PKT_MGQ_V1(x) (((x) & BIT_MASK_HEAD_PKT_MGQ_V1) << BIT_SHIFT_HEAD_PKT_MGQ_V1)
-#define BIT_GET_HEAD_PKT_MGQ_V1(x) (((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1) & BIT_MASK_HEAD_PKT_MGQ_V1)
+/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */
+#define BIT_EN_SLOW_MAC_RX BIT(1)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */
+#define BIT_EN_RXDMA_STUCK_ERR_HANDLE BIT(1)
+#define BIT_EN_SLOW_MAC_HW BIT(0)
+#define BIT_EN_RXDMA_RTN_ERR_HANDLE BIT(0)
-/* 2 REG_HIQ_INFO (Offset 0x0414) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_QUEUEMACID_HIQ_V1 25
-#define BIT_MASK_QUEUEMACID_HIQ_V1 0x7f
-#define BIT_QUEUEMACID_HIQ_V1(x) (((x) & BIT_MASK_QUEUEMACID_HIQ_V1) << BIT_SHIFT_QUEUEMACID_HIQ_V1)
-#define BIT_GET_QUEUEMACID_HIQ_V1(x) (((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1) & BIT_MASK_QUEUEMACID_HIQ_V1)
+/* 2 REG_Q0_INFO (Offset 0x0400) */
+#define BIT_SHIFT_QUEUEMACID_Q0_V1 25
+#define BIT_MASK_QUEUEMACID_Q0_V1 0x7f
+#define BIT_QUEUEMACID_Q0_V1(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q0_V1) << BIT_SHIFT_QUEUEMACID_Q0_V1)
+#define BITS_QUEUEMACID_Q0_V1 \
+ (BIT_MASK_QUEUEMACID_Q0_V1 << BIT_SHIFT_QUEUEMACID_Q0_V1)
+#define BIT_CLEAR_QUEUEMACID_Q0_V1(x) ((x) & (~BITS_QUEUEMACID_Q0_V1))
+#define BIT_GET_QUEUEMACID_Q0_V1(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1) & BIT_MASK_QUEUEMACID_Q0_V1)
+#define BIT_SET_QUEUEMACID_Q0_V1(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q0_V1(x) | BIT_QUEUEMACID_Q0_V1(v))
-#define BIT_SHIFT_QUEUEAC_HIQ_V1 23
-#define BIT_MASK_QUEUEAC_HIQ_V1 0x3
-#define BIT_QUEUEAC_HIQ_V1(x) (((x) & BIT_MASK_QUEUEAC_HIQ_V1) << BIT_SHIFT_QUEUEAC_HIQ_V1)
-#define BIT_GET_QUEUEAC_HIQ_V1(x) (((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1) & BIT_MASK_QUEUEAC_HIQ_V1)
+#endif
+#if (HALMAC_8198F_SUPPORT)
-#endif
+/* 2 REG_QUEUE_INFO1 (Offset 0x0400) */
+#define BIT_SHIFT_QUEUEMACID 25
+#define BIT_MASK_QUEUEMACID 0x7f
+#define BIT_QUEUEMACID(x) (((x) & BIT_MASK_QUEUEMACID) << BIT_SHIFT_QUEUEMACID)
+#define BITS_QUEUEMACID (BIT_MASK_QUEUEMACID << BIT_SHIFT_QUEUEMACID)
+#define BIT_CLEAR_QUEUEMACID(x) ((x) & (~BITS_QUEUEMACID))
+#define BIT_GET_QUEUEMACID(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID) & BIT_MASK_QUEUEMACID)
+#define BIT_SET_QUEUEMACID(x, v) (BIT_CLEAR_QUEUEMACID(x) | BIT_QUEUEMACID(v))
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#define BIT_DONE BIT(24)
+#endif
-/* 2 REG_HIQ_INFO (Offset 0x0414) */
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_TIDEMPTY_HIQ_V1 BIT(22)
+/* 2 REG_Q0_INFO (Offset 0x0400) */
+
+#define BIT_SHIFT_QUEUEAC_Q0_V1 23
+#define BIT_MASK_QUEUEAC_Q0_V1 0x3
+#define BIT_QUEUEAC_Q0_V1(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q0_V1) << BIT_SHIFT_QUEUEAC_Q0_V1)
+#define BITS_QUEUEAC_Q0_V1 (BIT_MASK_QUEUEAC_Q0_V1 << BIT_SHIFT_QUEUEAC_Q0_V1)
+#define BIT_CLEAR_QUEUEAC_Q0_V1(x) ((x) & (~BITS_QUEUEAC_Q0_V1))
+#define BIT_GET_QUEUEAC_Q0_V1(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q0_V1) & BIT_MASK_QUEUEAC_Q0_V1)
+#define BIT_SET_QUEUEAC_Q0_V1(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q0_V1(x) | BIT_QUEUEAC_Q0_V1(v))
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_QUEUE_INFO1 (Offset 0x0400) */
+#define BIT_SHIFT_QUEUEAC 23
+#define BIT_MASK_QUEUEAC 0x3
+#define BIT_QUEUEAC(x) (((x) & BIT_MASK_QUEUEAC) << BIT_SHIFT_QUEUEAC)
+#define BITS_QUEUEAC (BIT_MASK_QUEUEAC << BIT_SHIFT_QUEUEAC)
+#define BIT_CLEAR_QUEUEAC(x) ((x) & (~BITS_QUEUEAC))
+#define BIT_GET_QUEUEAC(x) (((x) >> BIT_SHIFT_QUEUEAC) & BIT_MASK_QUEUEAC)
+#define BIT_SET_QUEUEAC(x, v) (BIT_CLEAR_QUEUEAC(x) | BIT_QUEUEAC(v))
-/* 2 REG_HIQ_INFO (Offset 0x0414) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_TAIL_PKT_HIQ_V1 15
-#define BIT_MASK_TAIL_PKT_HIQ_V1 0xff
-#define BIT_TAIL_PKT_HIQ_V1(x) (((x) & BIT_MASK_TAIL_PKT_HIQ_V1) << BIT_SHIFT_TAIL_PKT_HIQ_V1)
-#define BIT_GET_TAIL_PKT_HIQ_V1(x) (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V1) & BIT_MASK_TAIL_PKT_HIQ_V1)
+/* 2 REG_Q0_INFO (Offset 0x0400) */
+#define BIT_TIDEMPTY_Q0_V1 BIT(22)
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_QUEUE_INFO1 (Offset 0x0400) */
+#define BIT_TIDEMPTY BIT(22)
-/* 2 REG_HIQ_INFO (Offset 0x0414) */
+#define BIT_SHIFT_ACCWBITEN 20
+#define BIT_MASK_ACCWBITEN 0xf
+#define BIT_ACCWBITEN(x) (((x) & BIT_MASK_ACCWBITEN) << BIT_SHIFT_ACCWBITEN)
+#define BITS_ACCWBITEN (BIT_MASK_ACCWBITEN << BIT_SHIFT_ACCWBITEN)
+#define BIT_CLEAR_ACCWBITEN(x) ((x) & (~BITS_ACCWBITEN))
+#define BIT_GET_ACCWBITEN(x) (((x) >> BIT_SHIFT_ACCWBITEN) & BIT_MASK_ACCWBITEN)
+#define BIT_SET_ACCWBITEN(x, v) (BIT_CLEAR_ACCWBITEN(x) | BIT_ACCWBITEN(v))
+#define BIT_BCNQ_EMPTY_V1 BIT(19)
+#define BIT_HIQ_EMPTY_V1 BIT(18)
+#define BIT_MQQ_EMPTY_V1 BIT(17)
-#define BIT_SHIFT_TAIL_PKT_HIQ_V2 11
-#define BIT_MASK_TAIL_PKT_HIQ_V2 0x7ff
-#define BIT_TAIL_PKT_HIQ_V2(x) (((x) & BIT_MASK_TAIL_PKT_HIQ_V2) << BIT_SHIFT_TAIL_PKT_HIQ_V2)
-#define BIT_GET_TAIL_PKT_HIQ_V2(x) (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2) & BIT_MASK_TAIL_PKT_HIQ_V2)
+#define BIT_SHIFT_COL_CNT 16
+#define BIT_MASK_COL_CNT 0xf
+#define BIT_COL_CNT(x) (((x) & BIT_MASK_COL_CNT) << BIT_SHIFT_COL_CNT)
+#define BITS_COL_CNT (BIT_MASK_COL_CNT << BIT_SHIFT_COL_CNT)
+#define BIT_CLEAR_COL_CNT(x) ((x) & (~BITS_COL_CNT))
+#define BIT_GET_COL_CNT(x) (((x) >> BIT_SHIFT_COL_CNT) & BIT_MASK_COL_CNT)
+#define BIT_SET_COL_CNT(x, v) (BIT_CLEAR_COL_CNT(x) | BIT_COL_CNT(v))
+#define BIT_CPU_MGT_EMPTY BIT(16)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_Q0_INFO (Offset 0x0400) */
-/* 2 REG_HIQ_INFO (Offset 0x0414) */
+#define BIT_SHIFT_TAIL_PKT_Q0_V1 15
+#define BIT_MASK_TAIL_PKT_Q0_V1 0xff
+#define BIT_TAIL_PKT_Q0_V1(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q0_V1) << BIT_SHIFT_TAIL_PKT_Q0_V1)
+#define BITS_TAIL_PKT_Q0_V1 \
+ (BIT_MASK_TAIL_PKT_Q0_V1 << BIT_SHIFT_TAIL_PKT_Q0_V1)
+#define BIT_CLEAR_TAIL_PKT_Q0_V1(x) ((x) & (~BITS_TAIL_PKT_Q0_V1))
+#define BIT_GET_TAIL_PKT_Q0_V1(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V1) & BIT_MASK_TAIL_PKT_Q0_V1)
+#define BIT_SET_TAIL_PKT_Q0_V1(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q0_V1(x) | BIT_TAIL_PKT_Q0_V1(v))
+#endif
-#define BIT_SHIFT_PKT_NUM_HIQ_V1 8
-#define BIT_MASK_PKT_NUM_HIQ_V1 0x7f
-#define BIT_PKT_NUM_HIQ_V1(x) (((x) & BIT_MASK_PKT_NUM_HIQ_V1) << BIT_SHIFT_PKT_NUM_HIQ_V1)
-#define BIT_GET_PKT_NUM_HIQ_V1(x) (((x) >> BIT_SHIFT_PKT_NUM_HIQ_V1) & BIT_MASK_PKT_NUM_HIQ_V1)
+#if (HALMAC_8198F_SUPPORT)
+/* 2 REG_QUEUE_INFO1 (Offset 0x0400) */
-#define BIT_SHIFT_HEAD_PKT_HIQ 0
-#define BIT_MASK_HEAD_PKT_HIQ 0xff
-#define BIT_HEAD_PKT_HIQ(x) (((x) & BIT_MASK_HEAD_PKT_HIQ) << BIT_SHIFT_HEAD_PKT_HIQ)
-#define BIT_GET_HEAD_PKT_HIQ(x) (((x) >> BIT_SHIFT_HEAD_PKT_HIQ) & BIT_MASK_HEAD_PKT_HIQ)
+#define BIT_AC_MACID_NOT_SAME BIT(15)
+#define BIT_SHIFT_GROUP_TABLE_ID 12
+#define BIT_MASK_GROUP_TABLE_ID 0x7
+#define BIT_GROUP_TABLE_ID(x) \
+ (((x) & BIT_MASK_GROUP_TABLE_ID) << BIT_SHIFT_GROUP_TABLE_ID)
+#define BITS_GROUP_TABLE_ID \
+ (BIT_MASK_GROUP_TABLE_ID << BIT_SHIFT_GROUP_TABLE_ID)
+#define BIT_CLEAR_GROUP_TABLE_ID(x) ((x) & (~BITS_GROUP_TABLE_ID))
+#define BIT_GET_GROUP_TABLE_ID(x) \
+ (((x) >> BIT_SHIFT_GROUP_TABLE_ID) & BIT_MASK_GROUP_TABLE_ID)
+#define BIT_SET_GROUP_TABLE_ID(x, v) \
+ (BIT_CLEAR_GROUP_TABLE_ID(x) | BIT_GROUP_TABLE_ID(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_Q0_INFO (Offset 0x0400) */
+#define BIT_SHIFT_TAIL_PKT_Q0_V2 11
+#define BIT_MASK_TAIL_PKT_Q0_V2 0x7ff
+#define BIT_TAIL_PKT_Q0_V2(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q0_V2) << BIT_SHIFT_TAIL_PKT_Q0_V2)
+#define BITS_TAIL_PKT_Q0_V2 \
+ (BIT_MASK_TAIL_PKT_Q0_V2 << BIT_SHIFT_TAIL_PKT_Q0_V2)
+#define BIT_CLEAR_TAIL_PKT_Q0_V2(x) ((x) & (~BITS_TAIL_PKT_Q0_V2))
+#define BIT_GET_TAIL_PKT_Q0_V2(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2) & BIT_MASK_TAIL_PKT_Q0_V2)
+#define BIT_SET_TAIL_PKT_Q0_V2(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q0_V2(x) | BIT_TAIL_PKT_Q0_V2(v))
-/* 2 REG_HIQ_INFO (Offset 0x0414) */
+#endif
+#if (HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_HEAD_PKT_HIQ_V1 0
-#define BIT_MASK_HEAD_PKT_HIQ_V1 0x7ff
-#define BIT_HEAD_PKT_HIQ_V1(x) (((x) & BIT_MASK_HEAD_PKT_HIQ_V1) << BIT_SHIFT_HEAD_PKT_HIQ_V1)
-#define BIT_GET_HEAD_PKT_HIQ_V1(x) (((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1) & BIT_MASK_HEAD_PKT_HIQ_V1)
+/* 2 REG_QUEUE_INFO1 (Offset 0x0400) */
+#define BIT_SHIFT_TAIL_PKT 11
+#define BIT_MASK_TAIL_PKT 0x7ff
+#define BIT_TAIL_PKT(x) (((x) & BIT_MASK_TAIL_PKT) << BIT_SHIFT_TAIL_PKT)
+#define BITS_TAIL_PKT (BIT_MASK_TAIL_PKT << BIT_SHIFT_TAIL_PKT)
+#define BIT_CLEAR_TAIL_PKT(x) ((x) & (~BITS_TAIL_PKT))
+#define BIT_GET_TAIL_PKT(x) (((x) >> BIT_SHIFT_TAIL_PKT) & BIT_MASK_TAIL_PKT)
+#define BIT_SET_TAIL_PKT(x, v) (BIT_CLEAR_TAIL_PKT(x) | BIT_TAIL_PKT(v))
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_Q0_INFO (Offset 0x0400) */
-/* 2 REG_BCNQ_INFO (Offset 0x0418) */
+#define BIT_SHIFT_PKT_NUM_Q0_V1 8
+#define BIT_MASK_PKT_NUM_Q0_V1 0x7f
+#define BIT_PKT_NUM_Q0_V1(x) \
+ (((x) & BIT_MASK_PKT_NUM_Q0_V1) << BIT_SHIFT_PKT_NUM_Q0_V1)
+#define BITS_PKT_NUM_Q0_V1 (BIT_MASK_PKT_NUM_Q0_V1 << BIT_SHIFT_PKT_NUM_Q0_V1)
+#define BIT_CLEAR_PKT_NUM_Q0_V1(x) ((x) & (~BITS_PKT_NUM_Q0_V1))
+#define BIT_GET_PKT_NUM_Q0_V1(x) \
+ (((x) >> BIT_SHIFT_PKT_NUM_Q0_V1) & BIT_MASK_PKT_NUM_Q0_V1)
+#define BIT_SET_PKT_NUM_Q0_V1(x, v) \
+ (BIT_CLEAR_PKT_NUM_Q0_V1(x) | BIT_PKT_NUM_Q0_V1(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q0 0
+#define BIT_MASK_HEAD_PKT_Q0 0xff
+#define BIT_HEAD_PKT_Q0(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q0) << BIT_SHIFT_HEAD_PKT_Q0)
+#define BITS_HEAD_PKT_Q0 (BIT_MASK_HEAD_PKT_Q0 << BIT_SHIFT_HEAD_PKT_Q0)
+#define BIT_CLEAR_HEAD_PKT_Q0(x) ((x) & (~BITS_HEAD_PKT_Q0))
+#define BIT_GET_HEAD_PKT_Q0(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q0) & BIT_MASK_HEAD_PKT_Q0)
+#define BIT_SET_HEAD_PKT_Q0(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q0(x) | BIT_HEAD_PKT_Q0(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+/* 2 REG_Q0_INFO (Offset 0x0400) */
-#define BIT_SHIFT_PKT_NUM_BCNQ 8
-#define BIT_MASK_PKT_NUM_BCNQ 0xff
-#define BIT_PKT_NUM_BCNQ(x) (((x) & BIT_MASK_PKT_NUM_BCNQ) << BIT_SHIFT_PKT_NUM_BCNQ)
-#define BIT_GET_PKT_NUM_BCNQ(x) (((x) >> BIT_SHIFT_PKT_NUM_BCNQ) & BIT_MASK_PKT_NUM_BCNQ)
+#define BIT_SHIFT_HEAD_PKT_Q0_V1 0
+#define BIT_MASK_HEAD_PKT_Q0_V1 0x7ff
+#define BIT_HEAD_PKT_Q0_V1(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q0_V1) << BIT_SHIFT_HEAD_PKT_Q0_V1)
+#define BITS_HEAD_PKT_Q0_V1 \
+ (BIT_MASK_HEAD_PKT_Q0_V1 << BIT_SHIFT_HEAD_PKT_Q0_V1)
+#define BIT_CLEAR_HEAD_PKT_Q0_V1(x) ((x) & (~BITS_HEAD_PKT_Q0_V1))
+#define BIT_GET_HEAD_PKT_Q0_V1(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1) & BIT_MASK_HEAD_PKT_Q0_V1)
+#define BIT_SET_HEAD_PKT_Q0_V1(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q0_V1(x) | BIT_HEAD_PKT_Q0_V1(v))
+#endif
-#define BIT_SHIFT_BCNQ_HEAD_PG 0
-#define BIT_MASK_BCNQ_HEAD_PG 0xff
-#define BIT_BCNQ_HEAD_PG(x) (((x) & BIT_MASK_BCNQ_HEAD_PG) << BIT_SHIFT_BCNQ_HEAD_PG)
-#define BIT_GET_BCNQ_HEAD_PG(x) (((x) >> BIT_SHIFT_BCNQ_HEAD_PG) & BIT_MASK_BCNQ_HEAD_PG)
+#if (HALMAC_8198F_SUPPORT)
+/* 2 REG_QUEUE_INFO1 (Offset 0x0400) */
-#endif
+#define BIT_SHIFT_HEAD_PKT 0
+#define BIT_MASK_HEAD_PKT 0x7ff
+#define BIT_HEAD_PKT(x) (((x) & BIT_MASK_HEAD_PKT) << BIT_SHIFT_HEAD_PKT)
+#define BITS_HEAD_PKT (BIT_MASK_HEAD_PKT << BIT_SHIFT_HEAD_PKT)
+#define BIT_CLEAR_HEAD_PKT(x) ((x) & (~BITS_HEAD_PKT))
+#define BIT_GET_HEAD_PKT(x) (((x) >> BIT_SHIFT_HEAD_PKT) & BIT_MASK_HEAD_PKT)
+#define BIT_SET_HEAD_PKT(x, v) (BIT_CLEAR_HEAD_PKT(x) | BIT_HEAD_PKT(v))
+#define BIT_SHIFT_PKT_NUMBER 0
+#define BIT_MASK_PKT_NUMBER 0xfff
+#define BIT_PKT_NUMBER(x) (((x) & BIT_MASK_PKT_NUMBER) << BIT_SHIFT_PKT_NUMBER)
+#define BITS_PKT_NUMBER (BIT_MASK_PKT_NUMBER << BIT_SHIFT_PKT_NUMBER)
+#define BIT_CLEAR_PKT_NUMBER(x) ((x) & (~BITS_PKT_NUMBER))
+#define BIT_GET_PKT_NUMBER(x) \
+ (((x) >> BIT_SHIFT_PKT_NUMBER) & BIT_MASK_PKT_NUMBER)
+#define BIT_SET_PKT_NUMBER(x, v) (BIT_CLEAR_PKT_NUMBER(x) | BIT_PKT_NUMBER(v))
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#define BIT_SHIFT_ACCW 0
+#define BIT_MASK_ACCW 0x3ff
+#define BIT_ACCW(x) (((x) & BIT_MASK_ACCW) << BIT_SHIFT_ACCW)
+#define BITS_ACCW (BIT_MASK_ACCW << BIT_SHIFT_ACCW)
+#define BIT_CLEAR_ACCW(x) ((x) & (~BITS_ACCW))
+#define BIT_GET_ACCW(x) (((x) >> BIT_SHIFT_ACCW) & BIT_MASK_ACCW)
+#define BIT_SET_ACCW(x, v) (BIT_CLEAR_ACCW(x) | BIT_ACCW(v))
+#define BIT_SHIFT_QINFO_INDEX 0
+#define BIT_MASK_QINFO_INDEX 0x1f
+#define BIT_QINFO_INDEX(x) \
+ (((x) & BIT_MASK_QINFO_INDEX) << BIT_SHIFT_QINFO_INDEX)
+#define BITS_QINFO_INDEX (BIT_MASK_QINFO_INDEX << BIT_SHIFT_QINFO_INDEX)
+#define BIT_CLEAR_QINFO_INDEX(x) ((x) & (~BITS_QINFO_INDEX))
+#define BIT_GET_QINFO_INDEX(x) \
+ (((x) >> BIT_SHIFT_QINFO_INDEX) & BIT_MASK_QINFO_INDEX)
+#define BIT_SET_QINFO_INDEX(x, v) \
+ (BIT_CLEAR_QINFO_INDEX(x) | BIT_QINFO_INDEX(v))
-/* 2 REG_BCNQ_INFO (Offset 0x0418) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_BCNQ_HEAD_PG_V1 0
-#define BIT_MASK_BCNQ_HEAD_PG_V1 0xfff
-#define BIT_BCNQ_HEAD_PG_V1(x) (((x) & BIT_MASK_BCNQ_HEAD_PG_V1) << BIT_SHIFT_BCNQ_HEAD_PG_V1)
-#define BIT_GET_BCNQ_HEAD_PG_V1(x) (((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1) & BIT_MASK_BCNQ_HEAD_PG_V1)
+/* 2 REG_QUEUELIST_INFO0 (Offset 0x0400) */
+#define BIT_SHIFT_QINFO0 0
+#define BIT_MASK_QINFO0 0xffffffffL
+#define BIT_QINFO0(x) (((x) & BIT_MASK_QINFO0) << BIT_SHIFT_QINFO0)
+#define BITS_QINFO0 (BIT_MASK_QINFO0 << BIT_SHIFT_QINFO0)
+#define BIT_CLEAR_QINFO0(x) ((x) & (~BITS_QINFO0))
+#define BIT_GET_QINFO0(x) (((x) >> BIT_SHIFT_QINFO0) & BIT_MASK_QINFO0)
+#define BIT_SET_QINFO0(x, v) (BIT_CLEAR_QINFO0(x) | BIT_QINFO0(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_Q1_INFO (Offset 0x0404) */
+#define BIT_SHIFT_QUEUEMACID_Q1_V1 25
+#define BIT_MASK_QUEUEMACID_Q1_V1 0x7f
+#define BIT_QUEUEMACID_Q1_V1(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q1_V1) << BIT_SHIFT_QUEUEMACID_Q1_V1)
+#define BITS_QUEUEMACID_Q1_V1 \
+ (BIT_MASK_QUEUEMACID_Q1_V1 << BIT_SHIFT_QUEUEMACID_Q1_V1)
+#define BIT_CLEAR_QUEUEMACID_Q1_V1(x) ((x) & (~BITS_QUEUEMACID_Q1_V1))
+#define BIT_GET_QUEUEMACID_Q1_V1(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1) & BIT_MASK_QUEUEMACID_Q1_V1)
+#define BIT_SET_QUEUEMACID_Q1_V1(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q1_V1(x) | BIT_QUEUEMACID_Q1_V1(v))
+
+#define BIT_SHIFT_QUEUEAC_Q1_V1 23
+#define BIT_MASK_QUEUEAC_Q1_V1 0x3
+#define BIT_QUEUEAC_Q1_V1(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q1_V1) << BIT_SHIFT_QUEUEAC_Q1_V1)
+#define BITS_QUEUEAC_Q1_V1 (BIT_MASK_QUEUEAC_Q1_V1 << BIT_SHIFT_QUEUEAC_Q1_V1)
+#define BIT_CLEAR_QUEUEAC_Q1_V1(x) ((x) & (~BITS_QUEUEAC_Q1_V1))
+#define BIT_GET_QUEUEAC_Q1_V1(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q1_V1) & BIT_MASK_QUEUEAC_Q1_V1)
+#define BIT_SET_QUEUEAC_Q1_V1(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q1_V1(x) | BIT_QUEUEAC_Q1_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_TXPKT_EMPTY (Offset 0x041A) */
+/* 2 REG_Q1_INFO (Offset 0x0404) */
-#define BIT_BCNQ_EMPTY BIT(11)
-#define BIT_HQQ_EMPTY BIT(10)
-#define BIT_MQQ_EMPTY BIT(9)
-#define BIT_MGQ_CPU_EMPTY BIT(8)
-#define BIT_AC7Q_EMPTY BIT(7)
-#define BIT_AC6Q_EMPTY BIT(6)
-#define BIT_AC5Q_EMPTY BIT(5)
-#define BIT_AC4Q_EMPTY BIT(4)
-#define BIT_AC3Q_EMPTY BIT(3)
-#define BIT_AC2Q_EMPTY BIT(2)
-#define BIT_AC1Q_EMPTY BIT(1)
-#define BIT_AC0Q_EMPTY BIT(0)
+#define BIT_TIDEMPTY_Q1_V1 BIT(22)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */
+/* 2 REG_Q1_INFO (Offset 0x0404) */
-#define BIT_BCN1_POLL BIT(30)
+#define BIT_SHIFT_TAIL_PKT_Q1_V1 15
+#define BIT_MASK_TAIL_PKT_Q1_V1 0xff
+#define BIT_TAIL_PKT_Q1_V1(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q1_V1) << BIT_SHIFT_TAIL_PKT_Q1_V1)
+#define BITS_TAIL_PKT_Q1_V1 \
+ (BIT_MASK_TAIL_PKT_Q1_V1 << BIT_SHIFT_TAIL_PKT_Q1_V1)
+#define BIT_CLEAR_TAIL_PKT_Q1_V1(x) ((x) & (~BITS_TAIL_PKT_Q1_V1))
+#define BIT_GET_TAIL_PKT_Q1_V1(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V1) & BIT_MASK_TAIL_PKT_Q1_V1)
+#define BIT_SET_TAIL_PKT_Q1_V1(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q1_V1(x) | BIT_TAIL_PKT_Q1_V1(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-
-/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */
+/* 2 REG_Q1_INFO (Offset 0x0404) */
-#define BIT_CPUMGT_POLL BIT(29)
-#define BIT_BCN_POLL BIT(28)
+#define BIT_SHIFT_TAIL_PKT_Q1_V2 11
+#define BIT_MASK_TAIL_PKT_Q1_V2 0x7ff
+#define BIT_TAIL_PKT_Q1_V2(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q1_V2) << BIT_SHIFT_TAIL_PKT_Q1_V2)
+#define BITS_TAIL_PKT_Q1_V2 \
+ (BIT_MASK_TAIL_PKT_Q1_V2 << BIT_SHIFT_TAIL_PKT_Q1_V2)
+#define BIT_CLEAR_TAIL_PKT_Q1_V2(x) ((x) & (~BITS_TAIL_PKT_Q1_V2))
+#define BIT_GET_TAIL_PKT_Q1_V2(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2) & BIT_MASK_TAIL_PKT_Q1_V2)
+#define BIT_SET_TAIL_PKT_Q1_V2(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q1_V2(x) | BIT_TAIL_PKT_Q1_V2(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_Q1_INFO (Offset 0x0404) */
+#define BIT_SHIFT_PKT_NUM_Q1_V1 8
+#define BIT_MASK_PKT_NUM_Q1_V1 0x7f
+#define BIT_PKT_NUM_Q1_V1(x) \
+ (((x) & BIT_MASK_PKT_NUM_Q1_V1) << BIT_SHIFT_PKT_NUM_Q1_V1)
+#define BITS_PKT_NUM_Q1_V1 (BIT_MASK_PKT_NUM_Q1_V1 << BIT_SHIFT_PKT_NUM_Q1_V1)
+#define BIT_CLEAR_PKT_NUM_Q1_V1(x) ((x) & (~BITS_PKT_NUM_Q1_V1))
+#define BIT_GET_PKT_NUM_Q1_V1(x) \
+ (((x) >> BIT_SHIFT_PKT_NUM_Q1_V1) & BIT_MASK_PKT_NUM_Q1_V1)
+#define BIT_SET_PKT_NUM_Q1_V1(x, v) \
+ (BIT_CLEAR_PKT_NUM_Q1_V1(x) | BIT_PKT_NUM_Q1_V1(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q1 0
+#define BIT_MASK_HEAD_PKT_Q1 0xff
+#define BIT_HEAD_PKT_Q1(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q1) << BIT_SHIFT_HEAD_PKT_Q1)
+#define BITS_HEAD_PKT_Q1 (BIT_MASK_HEAD_PKT_Q1 << BIT_SHIFT_HEAD_PKT_Q1)
+#define BIT_CLEAR_HEAD_PKT_Q1(x) ((x) & (~BITS_HEAD_PKT_Q1))
+#define BIT_GET_HEAD_PKT_Q1(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q1) & BIT_MASK_HEAD_PKT_Q1)
+#define BIT_SET_HEAD_PKT_Q1(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q1(x) | BIT_HEAD_PKT_Q1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */
+/* 2 REG_Q1_INFO (Offset 0x0404) */
-#define BIT_CPUMGQ_FW_NUM_V1 BIT(12)
+#define BIT_SHIFT_HEAD_PKT_Q1_V1 0
+#define BIT_MASK_HEAD_PKT_Q1_V1 0x7ff
+#define BIT_HEAD_PKT_Q1_V1(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q1_V1) << BIT_SHIFT_HEAD_PKT_Q1_V1)
+#define BITS_HEAD_PKT_Q1_V1 \
+ (BIT_MASK_HEAD_PKT_Q1_V1 << BIT_SHIFT_HEAD_PKT_Q1_V1)
+#define BIT_CLEAR_HEAD_PKT_Q1_V1(x) ((x) & (~BITS_HEAD_PKT_Q1_V1))
+#define BIT_GET_HEAD_PKT_Q1_V1(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1) & BIT_MASK_HEAD_PKT_Q1_V1)
+#define BIT_SET_HEAD_PKT_Q1_V1(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q1_V1(x) | BIT_HEAD_PKT_Q1_V1(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-
-/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */
+/* 2 REG_QUEUELIST_INFO1 (Offset 0x0404) */
-#define BIT_CPUMGQ_FW_NUM BIT(8)
+#define BIT_SHIFT_QINFO1 0
+#define BIT_MASK_QINFO1 0xffffffffL
+#define BIT_QINFO1(x) (((x) & BIT_MASK_QINFO1) << BIT_SHIFT_QINFO1)
+#define BITS_QINFO1 (BIT_MASK_QINFO1 << BIT_SHIFT_QINFO1)
+#define BIT_CLEAR_QINFO1(x) ((x) & (~BITS_QINFO1))
+#define BIT_GET_QINFO1(x) (((x) >> BIT_SHIFT_QINFO1) & BIT_MASK_QINFO1)
+#define BIT_SET_QINFO1(x, v) (BIT_CLEAR_QINFO1(x) | BIT_QINFO1(v))
-#define BIT_SHIFT_CPUMGQ_HEAD_PG 0
-#define BIT_MASK_CPUMGQ_HEAD_PG 0xff
-#define BIT_CPUMGQ_HEAD_PG(x) (((x) & BIT_MASK_CPUMGQ_HEAD_PG) << BIT_SHIFT_CPUMGQ_HEAD_PG)
-#define BIT_GET_CPUMGQ_HEAD_PG(x) (((x) >> BIT_SHIFT_CPUMGQ_HEAD_PG) & BIT_MASK_CPUMGQ_HEAD_PG)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_Q2_INFO (Offset 0x0408) */
+#define BIT_SHIFT_QUEUEMACID_Q2_V1 25
+#define BIT_MASK_QUEUEMACID_Q2_V1 0x7f
+#define BIT_QUEUEMACID_Q2_V1(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q2_V1) << BIT_SHIFT_QUEUEMACID_Q2_V1)
+#define BITS_QUEUEMACID_Q2_V1 \
+ (BIT_MASK_QUEUEMACID_Q2_V1 << BIT_SHIFT_QUEUEMACID_Q2_V1)
+#define BIT_CLEAR_QUEUEMACID_Q2_V1(x) ((x) & (~BITS_QUEUEMACID_Q2_V1))
+#define BIT_GET_QUEUEMACID_Q2_V1(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1) & BIT_MASK_QUEUEMACID_Q2_V1)
+#define BIT_SET_QUEUEMACID_Q2_V1(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q2_V1(x) | BIT_QUEUEMACID_Q2_V1(v))
+
+#define BIT_SHIFT_QUEUEAC_Q2_V1 23
+#define BIT_MASK_QUEUEAC_Q2_V1 0x3
+#define BIT_QUEUEAC_Q2_V1(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q2_V1) << BIT_SHIFT_QUEUEAC_Q2_V1)
+#define BITS_QUEUEAC_Q2_V1 (BIT_MASK_QUEUEAC_Q2_V1 << BIT_SHIFT_QUEUEAC_Q2_V1)
+#define BIT_CLEAR_QUEUEAC_Q2_V1(x) ((x) & (~BITS_QUEUEAC_Q2_V1))
+#define BIT_GET_QUEUEAC_Q2_V1(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q2_V1) & BIT_MASK_QUEUEAC_Q2_V1)
+#define BIT_SET_QUEUEAC_Q2_V1(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q2_V1(x) | BIT_QUEUEAC_Q2_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_Q2_INFO (Offset 0x0408) */
+#define BIT_TIDEMPTY_Q2_V1 BIT(22)
-/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_FW_FREE_TAIL_V1 0
-#define BIT_MASK_FW_FREE_TAIL_V1 0xfff
-#define BIT_FW_FREE_TAIL_V1(x) (((x) & BIT_MASK_FW_FREE_TAIL_V1) << BIT_SHIFT_FW_FREE_TAIL_V1)
-#define BIT_GET_FW_FREE_TAIL_V1(x) (((x) >> BIT_SHIFT_FW_FREE_TAIL_V1) & BIT_MASK_FW_FREE_TAIL_V1)
+/* 2 REG_Q2_INFO (Offset 0x0408) */
+#define BIT_SHIFT_TAIL_PKT_Q2_V1 15
+#define BIT_MASK_TAIL_PKT_Q2_V1 0xff
+#define BIT_TAIL_PKT_Q2_V1(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q2_V1) << BIT_SHIFT_TAIL_PKT_Q2_V1)
+#define BITS_TAIL_PKT_Q2_V1 \
+ (BIT_MASK_TAIL_PKT_Q2_V1 << BIT_SHIFT_TAIL_PKT_Q2_V1)
+#define BIT_CLEAR_TAIL_PKT_Q2_V1(x) ((x) & (~BITS_TAIL_PKT_Q2_V1))
+#define BIT_GET_TAIL_PKT_Q2_V1(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V1) & BIT_MASK_TAIL_PKT_Q2_V1)
+#define BIT_SET_TAIL_PKT_Q2_V1(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q2_V1(x) | BIT_TAIL_PKT_Q2_V1(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_Q2_INFO (Offset 0x0408) */
+#define BIT_SHIFT_TAIL_PKT_Q2_V2 11
+#define BIT_MASK_TAIL_PKT_Q2_V2 0x7ff
+#define BIT_TAIL_PKT_Q2_V2(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q2_V2) << BIT_SHIFT_TAIL_PKT_Q2_V2)
+#define BITS_TAIL_PKT_Q2_V2 \
+ (BIT_MASK_TAIL_PKT_Q2_V2 << BIT_SHIFT_TAIL_PKT_Q2_V2)
+#define BIT_CLEAR_TAIL_PKT_Q2_V2(x) ((x) & (~BITS_TAIL_PKT_Q2_V2))
+#define BIT_GET_TAIL_PKT_Q2_V2(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2) & BIT_MASK_TAIL_PKT_Q2_V2)
+#define BIT_SET_TAIL_PKT_Q2_V2(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q2_V2(x) | BIT_TAIL_PKT_Q2_V2(v))
-/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */
+#endif
-#define BIT_RTS_LIMIT_IN_OFDM BIT(23)
-#define BIT_EN_BCNQ_DL BIT(22)
-#define BIT_EN_RD_RESP_NAV_BK BIT(21)
-#define BIT_EN_WR_FREE_TAIL BIT(20)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_EN_QUEUE_RPT 8
-#define BIT_MASK_EN_QUEUE_RPT 0xff
-#define BIT_EN_QUEUE_RPT(x) (((x) & BIT_MASK_EN_QUEUE_RPT) << BIT_SHIFT_EN_QUEUE_RPT)
-#define BIT_GET_EN_QUEUE_RPT(x) (((x) >> BIT_SHIFT_EN_QUEUE_RPT) & BIT_MASK_EN_QUEUE_RPT)
+/* 2 REG_Q2_INFO (Offset 0x0408) */
-#define BIT_EN_RTY_BK BIT(7)
-#define BIT_EN_USE_INI_RAT BIT(6)
-#define BIT_EN_RTS_NAV_BK BIT(5)
-#define BIT_DIS_SSN_CHECK BIT(4)
-#define BIT_MACID_MATCH_RTS BIT(3)
+#define BIT_SHIFT_PKT_NUM_Q2_V1 8
+#define BIT_MASK_PKT_NUM_Q2_V1 0x7f
+#define BIT_PKT_NUM_Q2_V1(x) \
+ (((x) & BIT_MASK_PKT_NUM_Q2_V1) << BIT_SHIFT_PKT_NUM_Q2_V1)
+#define BITS_PKT_NUM_Q2_V1 (BIT_MASK_PKT_NUM_Q2_V1 << BIT_SHIFT_PKT_NUM_Q2_V1)
+#define BIT_CLEAR_PKT_NUM_Q2_V1(x) ((x) & (~BITS_PKT_NUM_Q2_V1))
+#define BIT_GET_PKT_NUM_Q2_V1(x) \
+ (((x) >> BIT_SHIFT_PKT_NUM_Q2_V1) & BIT_MASK_PKT_NUM_Q2_V1)
+#define BIT_SET_PKT_NUM_Q2_V1(x, v) \
+ (BIT_CLEAR_PKT_NUM_Q2_V1(x) | BIT_PKT_NUM_Q2_V1(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q2 0
+#define BIT_MASK_HEAD_PKT_Q2 0xff
+#define BIT_HEAD_PKT_Q2(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q2) << BIT_SHIFT_HEAD_PKT_Q2)
+#define BITS_HEAD_PKT_Q2 (BIT_MASK_HEAD_PKT_Q2 << BIT_SHIFT_HEAD_PKT_Q2)
+#define BIT_CLEAR_HEAD_PKT_Q2(x) ((x) & (~BITS_HEAD_PKT_Q2))
+#define BIT_GET_HEAD_PKT_Q2(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q2) & BIT_MASK_HEAD_PKT_Q2)
+#define BIT_SET_HEAD_PKT_Q2(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q2(x) | BIT_HEAD_PKT_Q2(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_Q2_INFO (Offset 0x0408) */
+#define BIT_SHIFT_HEAD_PKT_Q2_V1 0
+#define BIT_MASK_HEAD_PKT_Q2_V1 0x7ff
+#define BIT_HEAD_PKT_Q2_V1(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q2_V1) << BIT_SHIFT_HEAD_PKT_Q2_V1)
+#define BITS_HEAD_PKT_Q2_V1 \
+ (BIT_MASK_HEAD_PKT_Q2_V1 << BIT_SHIFT_HEAD_PKT_Q2_V1)
+#define BIT_CLEAR_HEAD_PKT_Q2_V1(x) ((x) & (~BITS_HEAD_PKT_Q2_V1))
+#define BIT_GET_HEAD_PKT_Q2_V1(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1) & BIT_MASK_HEAD_PKT_Q2_V1)
+#define BIT_SET_HEAD_PKT_Q2_V1(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q2_V1(x) | BIT_HEAD_PKT_Q2_V1(v))
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */
+/* 2 REG_QUEUELIST_INFO2 (Offset 0x0408) */
-#define BIT_EN_BCN_TRXRPT_V1 BIT(2)
+#define BIT_SHIFT_QINFO2 0
+#define BIT_MASK_QINFO2 0xffffffffL
+#define BIT_QINFO2(x) (((x) & BIT_MASK_QINFO2) << BIT_SHIFT_QINFO2)
+#define BITS_QINFO2 (BIT_MASK_QINFO2 << BIT_SHIFT_QINFO2)
+#define BIT_CLEAR_QINFO2(x) ((x) & (~BITS_QINFO2))
+#define BIT_GET_QINFO2(x) (((x) >> BIT_SHIFT_QINFO2) & BIT_MASK_QINFO2)
+#define BIT_SET_QINFO2(x, v) (BIT_CLEAR_QINFO2(x) | BIT_QINFO2(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+/* 2 REG_Q3_INFO (Offset 0x040C) */
+#define BIT_SHIFT_QUEUEMACID_Q3_V1 25
+#define BIT_MASK_QUEUEMACID_Q3_V1 0x7f
+#define BIT_QUEUEMACID_Q3_V1(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q3_V1) << BIT_SHIFT_QUEUEMACID_Q3_V1)
+#define BITS_QUEUEMACID_Q3_V1 \
+ (BIT_MASK_QUEUEMACID_Q3_V1 << BIT_SHIFT_QUEUEMACID_Q3_V1)
+#define BIT_CLEAR_QUEUEMACID_Q3_V1(x) ((x) & (~BITS_QUEUEMACID_Q3_V1))
+#define BIT_GET_QUEUEMACID_Q3_V1(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1) & BIT_MASK_QUEUEMACID_Q3_V1)
+#define BIT_SET_QUEUEMACID_Q3_V1(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q3_V1(x) | BIT_QUEUEMACID_Q3_V1(v))
+
+#define BIT_SHIFT_QUEUEAC_Q3_V1 23
+#define BIT_MASK_QUEUEAC_Q3_V1 0x3
+#define BIT_QUEUEAC_Q3_V1(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q3_V1) << BIT_SHIFT_QUEUEAC_Q3_V1)
+#define BITS_QUEUEAC_Q3_V1 (BIT_MASK_QUEUEAC_Q3_V1 << BIT_SHIFT_QUEUEAC_Q3_V1)
+#define BIT_CLEAR_QUEUEAC_Q3_V1(x) ((x) & (~BITS_QUEUEAC_Q3_V1))
+#define BIT_GET_QUEUEAC_Q3_V1(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q3_V1) & BIT_MASK_QUEUEAC_Q3_V1)
+#define BIT_SET_QUEUEAC_Q3_V1(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q3_V1(x) | BIT_QUEUEAC_Q3_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */
+/* 2 REG_Q3_INFO (Offset 0x040C) */
-#define BIT_R_EN_FTMRPT BIT(1)
+#define BIT_TIDEMPTY_Q3_V1 BIT(22)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_Q3_INFO (Offset 0x040C) */
+
+#define BIT_SHIFT_TAIL_PKT_Q3_V1 15
+#define BIT_MASK_TAIL_PKT_Q3_V1 0xff
+#define BIT_TAIL_PKT_Q3_V1(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q3_V1) << BIT_SHIFT_TAIL_PKT_Q3_V1)
+#define BITS_TAIL_PKT_Q3_V1 \
+ (BIT_MASK_TAIL_PKT_Q3_V1 << BIT_SHIFT_TAIL_PKT_Q3_V1)
+#define BIT_CLEAR_TAIL_PKT_Q3_V1(x) ((x) & (~BITS_TAIL_PKT_Q3_V1))
+#define BIT_GET_TAIL_PKT_Q3_V1(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V1) & BIT_MASK_TAIL_PKT_Q3_V1)
+#define BIT_SET_TAIL_PKT_Q3_V1(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q3_V1(x) | BIT_TAIL_PKT_Q3_V1(v))
-#if (HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */
+/* 2 REG_Q3_INFO (Offset 0x040C) */
-#define BIT_EN_FTMACKRPT BIT(1)
+#define BIT_SHIFT_TAIL_PKT_Q3_V2 11
+#define BIT_MASK_TAIL_PKT_Q3_V2 0x7ff
+#define BIT_TAIL_PKT_Q3_V2(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q3_V2) << BIT_SHIFT_TAIL_PKT_Q3_V2)
+#define BITS_TAIL_PKT_Q3_V2 \
+ (BIT_MASK_TAIL_PKT_Q3_V2 << BIT_SHIFT_TAIL_PKT_Q3_V2)
+#define BIT_CLEAR_TAIL_PKT_Q3_V2(x) ((x) & (~BITS_TAIL_PKT_Q3_V2))
+#define BIT_GET_TAIL_PKT_Q3_V2(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2) & BIT_MASK_TAIL_PKT_Q3_V2)
+#define BIT_SET_TAIL_PKT_Q3_V2(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q3_V2(x) | BIT_TAIL_PKT_Q3_V2(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+/* 2 REG_Q3_INFO (Offset 0x040C) */
+#define BIT_SHIFT_PKT_NUM_Q3_V1 8
+#define BIT_MASK_PKT_NUM_Q3_V1 0x7f
+#define BIT_PKT_NUM_Q3_V1(x) \
+ (((x) & BIT_MASK_PKT_NUM_Q3_V1) << BIT_SHIFT_PKT_NUM_Q3_V1)
+#define BITS_PKT_NUM_Q3_V1 (BIT_MASK_PKT_NUM_Q3_V1 << BIT_SHIFT_PKT_NUM_Q3_V1)
+#define BIT_CLEAR_PKT_NUM_Q3_V1(x) ((x) & (~BITS_PKT_NUM_Q3_V1))
+#define BIT_GET_PKT_NUM_Q3_V1(x) \
+ (((x) >> BIT_SHIFT_PKT_NUM_Q3_V1) & BIT_MASK_PKT_NUM_Q3_V1)
+#define BIT_SET_PKT_NUM_Q3_V1(x, v) \
+ (BIT_CLEAR_PKT_NUM_Q3_V1(x) | BIT_PKT_NUM_Q3_V1(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q3 0
+#define BIT_MASK_HEAD_PKT_Q3 0xff
+#define BIT_HEAD_PKT_Q3(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q3) << BIT_SHIFT_HEAD_PKT_Q3)
+#define BITS_HEAD_PKT_Q3 (BIT_MASK_HEAD_PKT_Q3 << BIT_SHIFT_HEAD_PKT_Q3)
+#define BIT_CLEAR_HEAD_PKT_Q3(x) ((x) & (~BITS_HEAD_PKT_Q3))
+#define BIT_GET_HEAD_PKT_Q3(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q3) & BIT_MASK_HEAD_PKT_Q3)
+#define BIT_SET_HEAD_PKT_Q3(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q3(x) | BIT_HEAD_PKT_Q3(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */
+/* 2 REG_Q3_INFO (Offset 0x040C) */
-#define BIT_R_BMC_NAV_PROTECT BIT(0)
+#define BIT_SHIFT_HEAD_PKT_Q3_V1 0
+#define BIT_MASK_HEAD_PKT_Q3_V1 0x7ff
+#define BIT_HEAD_PKT_Q3_V1(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q3_V1) << BIT_SHIFT_HEAD_PKT_Q3_V1)
+#define BITS_HEAD_PKT_Q3_V1 \
+ (BIT_MASK_HEAD_PKT_Q3_V1 << BIT_SHIFT_HEAD_PKT_Q3_V1)
+#define BIT_CLEAR_HEAD_PKT_Q3_V1(x) ((x) & (~BITS_HEAD_PKT_Q3_V1))
+#define BIT_GET_HEAD_PKT_Q3_V1(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1) & BIT_MASK_HEAD_PKT_Q3_V1)
+#define BIT_SET_HEAD_PKT_Q3_V1(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q3_V1(x) | BIT_HEAD_PKT_Q3_V1(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8822B_SUPPORT)
+/* 2 REG_QUEUELIST_INFO3 (Offset 0x040C) */
+#define BIT_SHIFT_QINFO3 0
+#define BIT_MASK_QINFO3 0xffffffffL
+#define BIT_QINFO3(x) (((x) & BIT_MASK_QINFO3) << BIT_SHIFT_QINFO3)
+#define BITS_QINFO3 (BIT_MASK_QINFO3 << BIT_SHIFT_QINFO3)
+#define BIT_CLEAR_QINFO3(x) ((x) & (~BITS_QINFO3))
+#define BIT_GET_QINFO3(x) (((x) >> BIT_SHIFT_QINFO3) & BIT_MASK_QINFO3)
+#define BIT_SET_QINFO3(x, v) (BIT_CLEAR_QINFO3(x) | BIT_QINFO3(v))
-/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */
+/* 2 REG_QUEUELIST_INFO_EMPTY (Offset 0x0410) */
-#define BIT_EN_FTMRPT BIT(0)
+#define BIT_FWCMDQ_EMPTY BIT(31)
+#define BIT_MGQ_CPU_EMPTY_V1 BIT(30)
+#define BIT_BCNQ_EMPTY_EXTP0 BIT(29)
+#define BIT_BCNQ_EMPTY_PORT4 BIT(28)
+#define BIT_BCNQ_EMPTY_PORT3 BIT(27)
+#define BIT_BCNQ_EMPTY_PORT2 BIT(26)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-
-/* 2 REG_HWSEQ_CTRL (Offset 0x0423) */
+/* 2 REG_MGQ_INFO (Offset 0x0410) */
-#define BIT_HWSEQ_CPUM_EN BIT(7)
-#define BIT_HWSEQ_BCN_EN BIT(6)
-#define BIT_HWSEQ_HI_EN BIT(5)
-#define BIT_HWSEQ_MGT_EN BIT(4)
-#define BIT_HWSEQ_BK_EN BIT(3)
-#define BIT_HWSEQ_BE_EN BIT(2)
+#define BIT_SHIFT_QUEUEMACID_MGQ_V1 25
+#define BIT_MASK_QUEUEMACID_MGQ_V1 0x7f
+#define BIT_QUEUEMACID_MGQ_V1(x) \
+ (((x) & BIT_MASK_QUEUEMACID_MGQ_V1) << BIT_SHIFT_QUEUEMACID_MGQ_V1)
+#define BITS_QUEUEMACID_MGQ_V1 \
+ (BIT_MASK_QUEUEMACID_MGQ_V1 << BIT_SHIFT_QUEUEMACID_MGQ_V1)
+#define BIT_CLEAR_QUEUEMACID_MGQ_V1(x) ((x) & (~BITS_QUEUEMACID_MGQ_V1))
+#define BIT_GET_QUEUEMACID_MGQ_V1(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1) & BIT_MASK_QUEUEMACID_MGQ_V1)
+#define BIT_SET_QUEUEMACID_MGQ_V1(x, v) \
+ (BIT_CLEAR_QUEUEMACID_MGQ_V1(x) | BIT_QUEUEMACID_MGQ_V1(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_QUEUELIST_INFO_EMPTY (Offset 0x0410) */
+#define BIT_BCNQ_EMPTY_PORT1 BIT(25)
+#define BIT_BCNQ_EMPTY_PORT0 BIT(24)
-/* 2 REG_DATAFB_SEL (Offset 0x0423) */
+#endif
-#define BIT__R_EN_RTY_BK_COD BIT(2)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_MGQ_INFO (Offset 0x0410) */
+#define BIT_SHIFT_QUEUEAC_MGQ_V1 23
+#define BIT_MASK_QUEUEAC_MGQ_V1 0x3
+#define BIT_QUEUEAC_MGQ_V1(x) \
+ (((x) & BIT_MASK_QUEUEAC_MGQ_V1) << BIT_SHIFT_QUEUEAC_MGQ_V1)
+#define BITS_QUEUEAC_MGQ_V1 \
+ (BIT_MASK_QUEUEAC_MGQ_V1 << BIT_SHIFT_QUEUEAC_MGQ_V1)
+#define BIT_CLEAR_QUEUEAC_MGQ_V1(x) ((x) & (~BITS_QUEUEAC_MGQ_V1))
+#define BIT_GET_QUEUEAC_MGQ_V1(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1) & BIT_MASK_QUEUEAC_MGQ_V1)
+#define BIT_SET_QUEUEAC_MGQ_V1(x, v) \
+ (BIT_CLEAR_QUEUEAC_MGQ_V1(x) | BIT_QUEUEAC_MGQ_V1(v))
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_HWSEQ_CTRL (Offset 0x0423) */
+/* 2 REG_QUEUELIST_INFO_EMPTY (Offset 0x0410) */
-#define BIT_HWSEQ_VI_EN BIT(1)
-#define BIT_HWSEQ_VO_EN BIT(0)
+#define BIT_HQQ_EMPTY_V1 BIT(23)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_MGQ_INFO (Offset 0x0410) */
+#define BIT_TIDEMPTY_MGQ_V1 BIT(22)
-/* 2 REG_DATAFB_SEL (Offset 0x0423) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT__R_DATA_FALLBACK_SEL 0
-#define BIT_MASK__R_DATA_FALLBACK_SEL 0x3
-#define BIT__R_DATA_FALLBACK_SEL(x) (((x) & BIT_MASK__R_DATA_FALLBACK_SEL) << BIT_SHIFT__R_DATA_FALLBACK_SEL)
-#define BIT_GET__R_DATA_FALLBACK_SEL(x) (((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL) & BIT_MASK__R_DATA_FALLBACK_SEL)
+/* 2 REG_QUEUELIST_INFO_EMPTY (Offset 0x0410) */
+#define BIT_MQQ_EMPTY_V2 BIT(22)
+#define BIT_S1_EMPTY BIT(21)
+#define BIT_S0_EMPTY BIT(20)
+#define BIT_AC19Q_EMPTY BIT(19)
+#define BIT_AC18Q_EMPTY BIT(18)
+#define BIT_AC17Q_EMPTY BIT(17)
+#define BIT_AC16Q_EMPTY BIT(16)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_MGQ_INFO (Offset 0x0410) */
-/* 2 REG_BCNQ_BDNY (Offset 0x0424) */
+#define BIT_SHIFT_TAIL_PKT_MGQ_V1 15
+#define BIT_MASK_TAIL_PKT_MGQ_V1 0xff
+#define BIT_TAIL_PKT_MGQ_V1(x) \
+ (((x) & BIT_MASK_TAIL_PKT_MGQ_V1) << BIT_SHIFT_TAIL_PKT_MGQ_V1)
+#define BITS_TAIL_PKT_MGQ_V1 \
+ (BIT_MASK_TAIL_PKT_MGQ_V1 << BIT_SHIFT_TAIL_PKT_MGQ_V1)
+#define BIT_CLEAR_TAIL_PKT_MGQ_V1(x) ((x) & (~BITS_TAIL_PKT_MGQ_V1))
+#define BIT_GET_TAIL_PKT_MGQ_V1(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V1) & BIT_MASK_TAIL_PKT_MGQ_V1)
+#define BIT_SET_TAIL_PKT_MGQ_V1(x, v) \
+ (BIT_CLEAR_TAIL_PKT_MGQ_V1(x) | BIT_TAIL_PKT_MGQ_V1(v))
+
+#endif
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_BCNQ_PGBNDY 0
-#define BIT_MASK_BCNQ_PGBNDY 0xff
-#define BIT_BCNQ_PGBNDY(x) (((x) & BIT_MASK_BCNQ_PGBNDY) << BIT_SHIFT_BCNQ_PGBNDY)
-#define BIT_GET_BCNQ_PGBNDY(x) (((x) >> BIT_SHIFT_BCNQ_PGBNDY) & BIT_MASK_BCNQ_PGBNDY)
+/* 2 REG_QUEUELIST_INFO_EMPTY (Offset 0x0410) */
+#define BIT_AC15Q_EMPTY BIT(15)
+#define BIT_AC14Q_EMPTY BIT(14)
+#define BIT_AC13Q_EMPTY BIT(13)
+#define BIT_AC12Q_EMPTY BIT(12)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_MGQ_INFO (Offset 0x0410) */
+#define BIT_SHIFT_TAIL_PKT_MGQ_V2 11
+#define BIT_MASK_TAIL_PKT_MGQ_V2 0x7ff
+#define BIT_TAIL_PKT_MGQ_V2(x) \
+ (((x) & BIT_MASK_TAIL_PKT_MGQ_V2) << BIT_SHIFT_TAIL_PKT_MGQ_V2)
+#define BITS_TAIL_PKT_MGQ_V2 \
+ (BIT_MASK_TAIL_PKT_MGQ_V2 << BIT_SHIFT_TAIL_PKT_MGQ_V2)
+#define BIT_CLEAR_TAIL_PKT_MGQ_V2(x) ((x) & (~BITS_TAIL_PKT_MGQ_V2))
+#define BIT_GET_TAIL_PKT_MGQ_V2(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2) & BIT_MASK_TAIL_PKT_MGQ_V2)
+#define BIT_SET_TAIL_PKT_MGQ_V2(x, v) \
+ (BIT_CLEAR_TAIL_PKT_MGQ_V2(x) | BIT_TAIL_PKT_MGQ_V2(v))
-/* 2 REG_BCNQ_BDNY_V1 (Offset 0x0424) */
+#endif
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_BCNQ_PGBNDY_V1 0
-#define BIT_MASK_BCNQ_PGBNDY_V1 0xfff
-#define BIT_BCNQ_PGBNDY_V1(x) (((x) & BIT_MASK_BCNQ_PGBNDY_V1) << BIT_SHIFT_BCNQ_PGBNDY_V1)
-#define BIT_GET_BCNQ_PGBNDY_V1(x) (((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1) & BIT_MASK_BCNQ_PGBNDY_V1)
+/* 2 REG_QUEUELIST_INFO_EMPTY (Offset 0x0410) */
+#define BIT_AC11Q_EMPTY BIT(11)
+#define BIT_AC10Q_EMPTY BIT(10)
+#define BIT_AC9Q_EMPTY BIT(9)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_MGQ_INFO (Offset 0x0410) */
-/* 2 REG_MGQ_BDNY (Offset 0x0425) */
+#define BIT_SHIFT_PKT_NUM_MGQ_V1 8
+#define BIT_MASK_PKT_NUM_MGQ_V1 0x7f
+#define BIT_PKT_NUM_MGQ_V1(x) \
+ (((x) & BIT_MASK_PKT_NUM_MGQ_V1) << BIT_SHIFT_PKT_NUM_MGQ_V1)
+#define BITS_PKT_NUM_MGQ_V1 \
+ (BIT_MASK_PKT_NUM_MGQ_V1 << BIT_SHIFT_PKT_NUM_MGQ_V1)
+#define BIT_CLEAR_PKT_NUM_MGQ_V1(x) ((x) & (~BITS_PKT_NUM_MGQ_V1))
+#define BIT_GET_PKT_NUM_MGQ_V1(x) \
+ (((x) >> BIT_SHIFT_PKT_NUM_MGQ_V1) & BIT_MASK_PKT_NUM_MGQ_V1)
+#define BIT_SET_PKT_NUM_MGQ_V1(x, v) \
+ (BIT_CLEAR_PKT_NUM_MGQ_V1(x) | BIT_PKT_NUM_MGQ_V1(v))
+
+#endif
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_MGQ_PGBNDY 0
-#define BIT_MASK_MGQ_PGBNDY 0xff
-#define BIT_MGQ_PGBNDY(x) (((x) & BIT_MASK_MGQ_PGBNDY) << BIT_SHIFT_MGQ_PGBNDY)
-#define BIT_GET_MGQ_PGBNDY(x) (((x) >> BIT_SHIFT_MGQ_PGBNDY) & BIT_MASK_MGQ_PGBNDY)
+/* 2 REG_QUEUELIST_INFO_EMPTY (Offset 0x0410) */
+#define BIT_AC8Q_EMPTY BIT(8)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_MGQ_INFO (Offset 0x0410) */
+#define BIT_SHIFT_HEAD_PKT_MGQ 0
+#define BIT_MASK_HEAD_PKT_MGQ 0xff
+#define BIT_HEAD_PKT_MGQ(x) \
+ (((x) & BIT_MASK_HEAD_PKT_MGQ) << BIT_SHIFT_HEAD_PKT_MGQ)
+#define BITS_HEAD_PKT_MGQ (BIT_MASK_HEAD_PKT_MGQ << BIT_SHIFT_HEAD_PKT_MGQ)
+#define BIT_CLEAR_HEAD_PKT_MGQ(x) ((x) & (~BITS_HEAD_PKT_MGQ))
+#define BIT_GET_HEAD_PKT_MGQ(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_MGQ) & BIT_MASK_HEAD_PKT_MGQ)
+#define BIT_SET_HEAD_PKT_MGQ(x, v) \
+ (BIT_CLEAR_HEAD_PKT_MGQ(x) | BIT_HEAD_PKT_MGQ(v))
-/* 2 REG_LIFETIME_EN (Offset 0x0426) */
+#endif
-#define BIT_BT_INT_CPU BIT(7)
-#define BIT_BT_INT_PTA BIT(6)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_MGQ_INFO (Offset 0x0410) */
+#define BIT_SHIFT_HEAD_PKT_MGQ_V1 0
+#define BIT_MASK_HEAD_PKT_MGQ_V1 0x7ff
+#define BIT_HEAD_PKT_MGQ_V1(x) \
+ (((x) & BIT_MASK_HEAD_PKT_MGQ_V1) << BIT_SHIFT_HEAD_PKT_MGQ_V1)
+#define BITS_HEAD_PKT_MGQ_V1 \
+ (BIT_MASK_HEAD_PKT_MGQ_V1 << BIT_SHIFT_HEAD_PKT_MGQ_V1)
+#define BIT_CLEAR_HEAD_PKT_MGQ_V1(x) ((x) & (~BITS_HEAD_PKT_MGQ_V1))
+#define BIT_GET_HEAD_PKT_MGQ_V1(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1) & BIT_MASK_HEAD_PKT_MGQ_V1)
+#define BIT_SET_HEAD_PKT_MGQ_V1(x, v) \
+ (BIT_CLEAR_HEAD_PKT_MGQ_V1(x) | BIT_HEAD_PKT_MGQ_V1(v))
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_LIFETIME_EN (Offset 0x0426) */
+/* 2 REG_HIQ_INFO (Offset 0x0414) */
-#define BIT_SPERPT_ENTRY BIT(5)
-#define BIT_RTYCNT_FB BIT(4)
+#define BIT_SHIFT_QUEUEMACID_HIQ_V1 25
+#define BIT_MASK_QUEUEMACID_HIQ_V1 0x7f
+#define BIT_QUEUEMACID_HIQ_V1(x) \
+ (((x) & BIT_MASK_QUEUEMACID_HIQ_V1) << BIT_SHIFT_QUEUEMACID_HIQ_V1)
+#define BITS_QUEUEMACID_HIQ_V1 \
+ (BIT_MASK_QUEUEMACID_HIQ_V1 << BIT_SHIFT_QUEUEMACID_HIQ_V1)
+#define BIT_CLEAR_QUEUEMACID_HIQ_V1(x) ((x) & (~BITS_QUEUEMACID_HIQ_V1))
+#define BIT_GET_QUEUEMACID_HIQ_V1(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1) & BIT_MASK_QUEUEMACID_HIQ_V1)
+#define BIT_SET_QUEUEMACID_HIQ_V1(x, v) \
+ (BIT_CLEAR_QUEUEMACID_HIQ_V1(x) | BIT_QUEUEMACID_HIQ_V1(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_QUEUELIST_ACQ_EN (Offset 0x0414) */
+#define BIT_SHIFT_QINFO_CTRL 24
+#define BIT_MASK_QINFO_CTRL 0x3f
+#define BIT_QINFO_CTRL(x) (((x) & BIT_MASK_QINFO_CTRL) << BIT_SHIFT_QINFO_CTRL)
+#define BITS_QINFO_CTRL (BIT_MASK_QINFO_CTRL << BIT_SHIFT_QINFO_CTRL)
+#define BIT_CLEAR_QINFO_CTRL(x) ((x) & (~BITS_QINFO_CTRL))
+#define BIT_GET_QINFO_CTRL(x) \
+ (((x) >> BIT_SHIFT_QINFO_CTRL) & BIT_MASK_QINFO_CTRL)
+#define BIT_SET_QINFO_CTRL(x, v) (BIT_CLEAR_QINFO_CTRL(x) | BIT_QINFO_CTRL(v))
-/* 2 REG_LIFETIME_EN (Offset 0x0426) */
+#endif
-#define BIT_EN_CTRL_RTYBIT BIT(4)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_HIQ_INFO (Offset 0x0414) */
+#define BIT_SHIFT_QUEUEAC_HIQ_V1 23
+#define BIT_MASK_QUEUEAC_HIQ_V1 0x3
+#define BIT_QUEUEAC_HIQ_V1(x) \
+ (((x) & BIT_MASK_QUEUEAC_HIQ_V1) << BIT_SHIFT_QUEUEAC_HIQ_V1)
+#define BITS_QUEUEAC_HIQ_V1 \
+ (BIT_MASK_QUEUEAC_HIQ_V1 << BIT_SHIFT_QUEUEAC_HIQ_V1)
+#define BIT_CLEAR_QUEUEAC_HIQ_V1(x) ((x) & (~BITS_QUEUEAC_HIQ_V1))
+#define BIT_GET_QUEUEAC_HIQ_V1(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1) & BIT_MASK_QUEUEAC_HIQ_V1)
+#define BIT_SET_QUEUEAC_HIQ_V1(x, v) \
+ (BIT_CLEAR_QUEUEAC_HIQ_V1(x) | BIT_QUEUEAC_HIQ_V1(v))
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_LIFETIME_EN (Offset 0x0426) */
+/* 2 REG_HIQ_INFO (Offset 0x0414) */
-#define BIT_LIFETIME_BK_EN BIT(3)
-#define BIT_LIFETIME_BE_EN BIT(2)
-#define BIT_LIFETIME_VI_EN BIT(1)
-#define BIT_LIFETIME_VO_EN BIT(0)
+#define BIT_TIDEMPTY_HIQ_V1 BIT(22)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_QUEUELIST_ACQ_EN (Offset 0x0414) */
+#define BIT_SHIFT_QINFO_MODE_BAND 20
+#define BIT_MASK_QINFO_MODE_BAND 0x7
+#define BIT_QINFO_MODE_BAND(x) \
+ (((x) & BIT_MASK_QINFO_MODE_BAND) << BIT_SHIFT_QINFO_MODE_BAND)
+#define BITS_QINFO_MODE_BAND \
+ (BIT_MASK_QINFO_MODE_BAND << BIT_SHIFT_QINFO_MODE_BAND)
+#define BIT_CLEAR_QINFO_MODE_BAND(x) ((x) & (~BITS_QINFO_MODE_BAND))
+#define BIT_GET_QINFO_MODE_BAND(x) \
+ (((x) >> BIT_SHIFT_QINFO_MODE_BAND) & BIT_MASK_QINFO_MODE_BAND)
+#define BIT_SET_QINFO_MODE_BAND(x, v) \
+ (BIT_CLEAR_QINFO_MODE_BAND(x) | BIT_QINFO_MODE_BAND(v))
-/* 2 REG_FW_FREE_TAIL (Offset 0x0427) */
+#define BIT_ACQ19_ENABLE BIT(19)
+#define BIT_ACQ18_ENABLE BIT(18)
+#define BIT_ACQ17_ENABLE BIT(17)
+#define BIT_ACQ16_ENABLE BIT(16)
+
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_FW_FREE_TAIL 0
-#define BIT_MASK_FW_FREE_TAIL 0xff
-#define BIT_FW_FREE_TAIL(x) (((x) & BIT_MASK_FW_FREE_TAIL) << BIT_SHIFT_FW_FREE_TAIL)
-#define BIT_GET_FW_FREE_TAIL(x) (((x) >> BIT_SHIFT_FW_FREE_TAIL) & BIT_MASK_FW_FREE_TAIL)
+/* 2 REG_HIQ_INFO (Offset 0x0414) */
+#define BIT_SHIFT_TAIL_PKT_HIQ_V1 15
+#define BIT_MASK_TAIL_PKT_HIQ_V1 0xff
+#define BIT_TAIL_PKT_HIQ_V1(x) \
+ (((x) & BIT_MASK_TAIL_PKT_HIQ_V1) << BIT_SHIFT_TAIL_PKT_HIQ_V1)
+#define BITS_TAIL_PKT_HIQ_V1 \
+ (BIT_MASK_TAIL_PKT_HIQ_V1 << BIT_SHIFT_TAIL_PKT_HIQ_V1)
+#define BIT_CLEAR_TAIL_PKT_HIQ_V1(x) ((x) & (~BITS_TAIL_PKT_HIQ_V1))
+#define BIT_GET_TAIL_PKT_HIQ_V1(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V1) & BIT_MASK_TAIL_PKT_HIQ_V1)
+#define BIT_SET_TAIL_PKT_HIQ_V1(x, v) \
+ (BIT_CLEAR_TAIL_PKT_HIQ_V1(x) | BIT_TAIL_PKT_HIQ_V1(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_QUEUELIST_ACQ_EN (Offset 0x0414) */
+#define BIT_ACQ15_ENABLE BIT(15)
+#define BIT_ACQ14_ENABLE BIT(14)
+#define BIT_ACQ13_ENABLE BIT(13)
+#define BIT_ACQ12_ENABLE BIT(12)
-/* 2 REG_SPEC_SIFS (Offset 0x0428) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL 8
-#define BIT_MASK_SPEC_SIFS_OFDM_PTCL 0xff
-#define BIT_SPEC_SIFS_OFDM_PTCL(x) (((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL) << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL)
-#define BIT_GET_SPEC_SIFS_OFDM_PTCL(x) (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL) & BIT_MASK_SPEC_SIFS_OFDM_PTCL)
+/* 2 REG_HIQ_INFO (Offset 0x0414) */
+#define BIT_SHIFT_TAIL_PKT_HIQ_V2 11
+#define BIT_MASK_TAIL_PKT_HIQ_V2 0x7ff
+#define BIT_TAIL_PKT_HIQ_V2(x) \
+ (((x) & BIT_MASK_TAIL_PKT_HIQ_V2) << BIT_SHIFT_TAIL_PKT_HIQ_V2)
+#define BITS_TAIL_PKT_HIQ_V2 \
+ (BIT_MASK_TAIL_PKT_HIQ_V2 << BIT_SHIFT_TAIL_PKT_HIQ_V2)
+#define BIT_CLEAR_TAIL_PKT_HIQ_V2(x) ((x) & (~BITS_TAIL_PKT_HIQ_V2))
+#define BIT_GET_TAIL_PKT_HIQ_V2(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2) & BIT_MASK_TAIL_PKT_HIQ_V2)
+#define BIT_SET_TAIL_PKT_HIQ_V2(x, v) \
+ (BIT_CLEAR_TAIL_PKT_HIQ_V2(x) | BIT_TAIL_PKT_HIQ_V2(v))
-#define BIT_SHIFT_SPEC_SIFS_CCK_PTCL 0
-#define BIT_MASK_SPEC_SIFS_CCK_PTCL 0xff
-#define BIT_SPEC_SIFS_CCK_PTCL(x) (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL) << BIT_SHIFT_SPEC_SIFS_CCK_PTCL)
-#define BIT_GET_SPEC_SIFS_CCK_PTCL(x) (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL) & BIT_MASK_SPEC_SIFS_CCK_PTCL)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_RETRY_LIMIT (Offset 0x042A) */
+/* 2 REG_QUEUELIST_ACQ_EN (Offset 0x0414) */
+#define BIT_ACQ11_ENABLE BIT(11)
+#define BIT_ACQ10_ENABLE BIT(10)
+#define BIT_ACQ9_ENABLE BIT(9)
-#define BIT_SHIFT_SRL 8
-#define BIT_MASK_SRL 0x3f
-#define BIT_SRL(x) (((x) & BIT_MASK_SRL) << BIT_SHIFT_SRL)
-#define BIT_GET_SRL(x) (((x) >> BIT_SHIFT_SRL) & BIT_MASK_SRL)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_LRL 0
-#define BIT_MASK_LRL 0x3f
-#define BIT_LRL(x) (((x) & BIT_MASK_LRL) << BIT_SHIFT_LRL)
-#define BIT_GET_LRL(x) (((x) >> BIT_SHIFT_LRL) & BIT_MASK_LRL)
+/* 2 REG_HIQ_INFO (Offset 0x0414) */
+#define BIT_SHIFT_PKT_NUM_HIQ_V1 8
+#define BIT_MASK_PKT_NUM_HIQ_V1 0x7f
+#define BIT_PKT_NUM_HIQ_V1(x) \
+ (((x) & BIT_MASK_PKT_NUM_HIQ_V1) << BIT_SHIFT_PKT_NUM_HIQ_V1)
+#define BITS_PKT_NUM_HIQ_V1 \
+ (BIT_MASK_PKT_NUM_HIQ_V1 << BIT_SHIFT_PKT_NUM_HIQ_V1)
+#define BIT_CLEAR_PKT_NUM_HIQ_V1(x) ((x) & (~BITS_PKT_NUM_HIQ_V1))
+#define BIT_GET_PKT_NUM_HIQ_V1(x) \
+ (((x) >> BIT_SHIFT_PKT_NUM_HIQ_V1) & BIT_MASK_PKT_NUM_HIQ_V1)
+#define BIT_SET_PKT_NUM_HIQ_V1(x, v) \
+ (BIT_CLEAR_PKT_NUM_HIQ_V1(x) | BIT_PKT_NUM_HIQ_V1(v))
-/* 2 REG_TXBF_CTRL (Offset 0x042C) */
+#endif
-#define BIT_R_ENABLE_NDPA BIT(31)
-#define BIT_USE_NDPA_PARAMETER BIT(30)
-#define BIT_R_PROP_TXBF BIT(29)
-#define BIT_R_EN_NDPA_INT BIT(28)
-#define BIT_R_TXBF1_80M BIT(27)
-#define BIT_R_TXBF1_40M BIT(26)
-#define BIT_R_TXBF1_20M BIT(25)
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_R_TXBF1_AID 16
-#define BIT_MASK_R_TXBF1_AID 0x1ff
-#define BIT_R_TXBF1_AID(x) (((x) & BIT_MASK_R_TXBF1_AID) << BIT_SHIFT_R_TXBF1_AID)
-#define BIT_GET_R_TXBF1_AID(x) (((x) >> BIT_SHIFT_R_TXBF1_AID) & BIT_MASK_R_TXBF1_AID)
+/* 2 REG_QUEUELIST_ACQ_EN (Offset 0x0414) */
+#define BIT_ACQ8_ENABLE BIT(8)
+#define BIT_ACQ7_ENABLE BIT(7)
+#define BIT_ACQ6_ENABLE BIT(6)
+#define BIT_ACQ5_ENABLE BIT(5)
+#define BIT_ACQ4_ENABLE BIT(4)
+#define BIT_ACQ3_ENABLE BIT(3)
+#define BIT_ACQ2_ENABLE BIT(2)
+#define BIT_ACQ1_ENABLE BIT(1)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_HIQ_INFO (Offset 0x0414) */
+#define BIT_SHIFT_HEAD_PKT_HIQ 0
+#define BIT_MASK_HEAD_PKT_HIQ 0xff
+#define BIT_HEAD_PKT_HIQ(x) \
+ (((x) & BIT_MASK_HEAD_PKT_HIQ) << BIT_SHIFT_HEAD_PKT_HIQ)
+#define BITS_HEAD_PKT_HIQ (BIT_MASK_HEAD_PKT_HIQ << BIT_SHIFT_HEAD_PKT_HIQ)
+#define BIT_CLEAR_HEAD_PKT_HIQ(x) ((x) & (~BITS_HEAD_PKT_HIQ))
+#define BIT_GET_HEAD_PKT_HIQ(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_HIQ) & BIT_MASK_HEAD_PKT_HIQ)
+#define BIT_SET_HEAD_PKT_HIQ(x, v) \
+ (BIT_CLEAR_HEAD_PKT_HIQ(x) | BIT_HEAD_PKT_HIQ(v))
-/* 2 REG_TXBF_CTRL (Offset 0x042C) */
+#endif
-#define BIT_DIS_NDP_BFEN BIT(15)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_HIQ_INFO (Offset 0x0414) */
+#define BIT_SHIFT_HEAD_PKT_HIQ_V1 0
+#define BIT_MASK_HEAD_PKT_HIQ_V1 0x7ff
+#define BIT_HEAD_PKT_HIQ_V1(x) \
+ (((x) & BIT_MASK_HEAD_PKT_HIQ_V1) << BIT_SHIFT_HEAD_PKT_HIQ_V1)
+#define BITS_HEAD_PKT_HIQ_V1 \
+ (BIT_MASK_HEAD_PKT_HIQ_V1 << BIT_SHIFT_HEAD_PKT_HIQ_V1)
+#define BIT_CLEAR_HEAD_PKT_HIQ_V1(x) ((x) & (~BITS_HEAD_PKT_HIQ_V1))
+#define BIT_GET_HEAD_PKT_HIQ_V1(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1) & BIT_MASK_HEAD_PKT_HIQ_V1)
+#define BIT_SET_HEAD_PKT_HIQ_V1(x, v) \
+ (BIT_CLEAR_HEAD_PKT_HIQ_V1(x) | BIT_HEAD_PKT_HIQ_V1(v))
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_TXBF_CTRL (Offset 0x042C) */
+/* 2 REG_QUEUELIST_ACQ_EN (Offset 0x0414) */
-#define BIT_R_TXBCN_NOBLOCK_NDP BIT(14)
+#define BIT_ACQ0_ENABLE BIT(0)
-#endif
+/* 2 REG_BCNQ_BDNY_V2 (Offset 0x0418) */
+
+#define BIT_SHIFT_BCNQ_PGBNDY_WSEL 28
+#define BIT_MASK_BCNQ_PGBNDY_WSEL 0x7
+#define BIT_BCNQ_PGBNDY_WSEL(x) \
+ (((x) & BIT_MASK_BCNQ_PGBNDY_WSEL) << BIT_SHIFT_BCNQ_PGBNDY_WSEL)
+#define BITS_BCNQ_PGBNDY_WSEL \
+ (BIT_MASK_BCNQ_PGBNDY_WSEL << BIT_SHIFT_BCNQ_PGBNDY_WSEL)
+#define BIT_CLEAR_BCNQ_PGBNDY_WSEL(x) ((x) & (~BITS_BCNQ_PGBNDY_WSEL))
+#define BIT_GET_BCNQ_PGBNDY_WSEL(x) \
+ (((x) >> BIT_SHIFT_BCNQ_PGBNDY_WSEL) & BIT_MASK_BCNQ_PGBNDY_WSEL)
+#define BIT_SET_BCNQ_PGBNDY_WSEL(x, v) \
+ (BIT_CLEAR_BCNQ_PGBNDY_WSEL(x) | BIT_BCNQ_PGBNDY_WSEL(v))
+#define BIT_SHIFT_BCNQ_PGBNDY_RCONTENT 12
+#define BIT_MASK_BCNQ_PGBNDY_RCONTENT 0xfff
+#define BIT_BCNQ_PGBNDY_RCONTENT(x) \
+ (((x) & BIT_MASK_BCNQ_PGBNDY_RCONTENT) \
+ << BIT_SHIFT_BCNQ_PGBNDY_RCONTENT)
+#define BITS_BCNQ_PGBNDY_RCONTENT \
+ (BIT_MASK_BCNQ_PGBNDY_RCONTENT << BIT_SHIFT_BCNQ_PGBNDY_RCONTENT)
+#define BIT_CLEAR_BCNQ_PGBNDY_RCONTENT(x) ((x) & (~BITS_BCNQ_PGBNDY_RCONTENT))
+#define BIT_GET_BCNQ_PGBNDY_RCONTENT(x) \
+ (((x) >> BIT_SHIFT_BCNQ_PGBNDY_RCONTENT) & \
+ BIT_MASK_BCNQ_PGBNDY_RCONTENT)
+#define BIT_SET_BCNQ_PGBNDY_RCONTENT(x, v) \
+ (BIT_CLEAR_BCNQ_PGBNDY_RCONTENT(x) | BIT_BCNQ_PGBNDY_RCONTENT(v))
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_TXBF_CTRL (Offset 0x042C) */
+/* 2 REG_BCNQ_INFO (Offset 0x0418) */
-#define BIT_R_TXBF0_80M BIT(11)
-#define BIT_R_TXBF0_40M BIT(10)
-#define BIT_R_TXBF0_20M BIT(9)
+#define BIT_SHIFT_PKT_NUM_BCNQ 8
+#define BIT_MASK_PKT_NUM_BCNQ 0xff
+#define BIT_PKT_NUM_BCNQ(x) \
+ (((x) & BIT_MASK_PKT_NUM_BCNQ) << BIT_SHIFT_PKT_NUM_BCNQ)
+#define BITS_PKT_NUM_BCNQ (BIT_MASK_PKT_NUM_BCNQ << BIT_SHIFT_PKT_NUM_BCNQ)
+#define BIT_CLEAR_PKT_NUM_BCNQ(x) ((x) & (~BITS_PKT_NUM_BCNQ))
+#define BIT_GET_PKT_NUM_BCNQ(x) \
+ (((x) >> BIT_SHIFT_PKT_NUM_BCNQ) & BIT_MASK_PKT_NUM_BCNQ)
+#define BIT_SET_PKT_NUM_BCNQ(x, v) \
+ (BIT_CLEAR_PKT_NUM_BCNQ(x) | BIT_PKT_NUM_BCNQ(v))
+
+#define BIT_SHIFT_BCNQ_HEAD_PG 0
+#define BIT_MASK_BCNQ_HEAD_PG 0xff
+#define BIT_BCNQ_HEAD_PG(x) \
+ (((x) & BIT_MASK_BCNQ_HEAD_PG) << BIT_SHIFT_BCNQ_HEAD_PG)
+#define BITS_BCNQ_HEAD_PG (BIT_MASK_BCNQ_HEAD_PG << BIT_SHIFT_BCNQ_HEAD_PG)
+#define BIT_CLEAR_BCNQ_HEAD_PG(x) ((x) & (~BITS_BCNQ_HEAD_PG))
+#define BIT_GET_BCNQ_HEAD_PG(x) \
+ (((x) >> BIT_SHIFT_BCNQ_HEAD_PG) & BIT_MASK_BCNQ_HEAD_PG)
+#define BIT_SET_BCNQ_HEAD_PG(x, v) \
+ (BIT_CLEAR_BCNQ_HEAD_PG(x) | BIT_BCNQ_HEAD_PG(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_R_TXBF0_AID 0
-#define BIT_MASK_R_TXBF0_AID 0x1ff
-#define BIT_R_TXBF0_AID(x) (((x) & BIT_MASK_R_TXBF0_AID) << BIT_SHIFT_R_TXBF0_AID)
-#define BIT_GET_R_TXBF0_AID(x) (((x) >> BIT_SHIFT_R_TXBF0_AID) & BIT_MASK_R_TXBF0_AID)
+/* 2 REG_BCNQ_INFO (Offset 0x0418) */
+#define BIT_SHIFT_BCNQ_HEAD_PG_V1 0
+#define BIT_MASK_BCNQ_HEAD_PG_V1 0xfff
+#define BIT_BCNQ_HEAD_PG_V1(x) \
+ (((x) & BIT_MASK_BCNQ_HEAD_PG_V1) << BIT_SHIFT_BCNQ_HEAD_PG_V1)
+#define BITS_BCNQ_HEAD_PG_V1 \
+ (BIT_MASK_BCNQ_HEAD_PG_V1 << BIT_SHIFT_BCNQ_HEAD_PG_V1)
+#define BIT_CLEAR_BCNQ_HEAD_PG_V1(x) ((x) & (~BITS_BCNQ_HEAD_PG_V1))
+#define BIT_GET_BCNQ_HEAD_PG_V1(x) \
+ (((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1) & BIT_MASK_BCNQ_HEAD_PG_V1)
+#define BIT_SET_BCNQ_HEAD_PG_V1(x, v) \
+ (BIT_CLEAR_BCNQ_HEAD_PG_V1(x) | BIT_BCNQ_HEAD_PG_V1(v))
-/* 2 REG_DARFRC (Offset 0x0430) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_DARF_RC8 (56 & CPU_OPT_WIDTH)
-#define BIT_MASK_DARF_RC8 0x1f
-#define BIT_DARF_RC8(x) (((x) & BIT_MASK_DARF_RC8) << BIT_SHIFT_DARF_RC8)
-#define BIT_GET_DARF_RC8(x) (((x) >> BIT_SHIFT_DARF_RC8) & BIT_MASK_DARF_RC8)
+/* 2 REG_BCNQ_BDNY_V2 (Offset 0x0418) */
+#define BIT_SHIFT_BCNQ_PGBNDY_WCONTENT 0
+#define BIT_MASK_BCNQ_PGBNDY_WCONTENT 0xfff
+#define BIT_BCNQ_PGBNDY_WCONTENT(x) \
+ (((x) & BIT_MASK_BCNQ_PGBNDY_WCONTENT) \
+ << BIT_SHIFT_BCNQ_PGBNDY_WCONTENT)
+#define BITS_BCNQ_PGBNDY_WCONTENT \
+ (BIT_MASK_BCNQ_PGBNDY_WCONTENT << BIT_SHIFT_BCNQ_PGBNDY_WCONTENT)
+#define BIT_CLEAR_BCNQ_PGBNDY_WCONTENT(x) ((x) & (~BITS_BCNQ_PGBNDY_WCONTENT))
+#define BIT_GET_BCNQ_PGBNDY_WCONTENT(x) \
+ (((x) >> BIT_SHIFT_BCNQ_PGBNDY_WCONTENT) & \
+ BIT_MASK_BCNQ_PGBNDY_WCONTENT)
+#define BIT_SET_BCNQ_PGBNDY_WCONTENT(x, v) \
+ (BIT_CLEAR_BCNQ_PGBNDY_WCONTENT(x) | BIT_BCNQ_PGBNDY_WCONTENT(v))
-#define BIT_SHIFT_DARF_RC7 (48 & CPU_OPT_WIDTH)
-#define BIT_MASK_DARF_RC7 0x1f
-#define BIT_DARF_RC7(x) (((x) & BIT_MASK_DARF_RC7) << BIT_SHIFT_DARF_RC7)
-#define BIT_GET_DARF_RC7(x) (((x) >> BIT_SHIFT_DARF_RC7) & BIT_MASK_DARF_RC7)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_DARF_RC6 (40 & CPU_OPT_WIDTH)
-#define BIT_MASK_DARF_RC6 0x1f
-#define BIT_DARF_RC6(x) (((x) & BIT_MASK_DARF_RC6) << BIT_SHIFT_DARF_RC6)
-#define BIT_GET_DARF_RC6(x) (((x) >> BIT_SHIFT_DARF_RC6) & BIT_MASK_DARF_RC6)
+/* 2 REG_TXPKT_EMPTY (Offset 0x041A) */
+#define BIT_BCNQ_EMPTY BIT(11)
+#define BIT_HQQ_EMPTY BIT(10)
+#define BIT_MQQ_EMPTY BIT(9)
+#define BIT_MGQ_CPU_EMPTY BIT(8)
-#define BIT_SHIFT_DARF_RC5 (32 & CPU_OPT_WIDTH)
-#define BIT_MASK_DARF_RC5 0x1f
-#define BIT_DARF_RC5(x) (((x) & BIT_MASK_DARF_RC5) << BIT_SHIFT_DARF_RC5)
-#define BIT_GET_DARF_RC5(x) (((x) >> BIT_SHIFT_DARF_RC5) & BIT_MASK_DARF_RC5)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_DARF_RC4 24
-#define BIT_MASK_DARF_RC4 0x1f
-#define BIT_DARF_RC4(x) (((x) & BIT_MASK_DARF_RC4) << BIT_SHIFT_DARF_RC4)
-#define BIT_GET_DARF_RC4(x) (((x) >> BIT_SHIFT_DARF_RC4) & BIT_MASK_DARF_RC4)
+/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */
+#define BIT_BCN1_POLL BIT(30)
-#define BIT_SHIFT_DARF_RC3 16
-#define BIT_MASK_DARF_RC3 0x1f
-#define BIT_DARF_RC3(x) (((x) & BIT_MASK_DARF_RC3) << BIT_SHIFT_DARF_RC3)
-#define BIT_GET_DARF_RC3(x) (((x) >> BIT_SHIFT_DARF_RC3) & BIT_MASK_DARF_RC3)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_DARF_RC2 8
-#define BIT_MASK_DARF_RC2 0x1f
-#define BIT_DARF_RC2(x) (((x) & BIT_MASK_DARF_RC2) << BIT_SHIFT_DARF_RC2)
-#define BIT_GET_DARF_RC2(x) (((x) >> BIT_SHIFT_DARF_RC2) & BIT_MASK_DARF_RC2)
+/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */
+#define BIT_CPUMGT_CLR_V1 BIT(30)
-#define BIT_SHIFT_DARF_RC1 0
-#define BIT_MASK_DARF_RC1 0x1f
-#define BIT_DARF_RC1(x) (((x) & BIT_MASK_DARF_RC1) << BIT_SHIFT_DARF_RC1)
-#define BIT_GET_DARF_RC1(x) (((x) >> BIT_SHIFT_DARF_RC1) & BIT_MASK_DARF_RC1)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-/* 2 REG_RARFRC (Offset 0x0438) */
+/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */
+#define BIT_CPUMGT_POLL BIT(29)
-#define BIT_SHIFT_RARF_RC8 (56 & CPU_OPT_WIDTH)
-#define BIT_MASK_RARF_RC8 0x1f
-#define BIT_RARF_RC8(x) (((x) & BIT_MASK_RARF_RC8) << BIT_SHIFT_RARF_RC8)
-#define BIT_GET_RARF_RC8(x) (((x) >> BIT_SHIFT_RARF_RC8) & BIT_MASK_RARF_RC8)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_RARF_RC7 (48 & CPU_OPT_WIDTH)
-#define BIT_MASK_RARF_RC7 0x1f
-#define BIT_RARF_RC7(x) (((x) & BIT_MASK_RARF_RC7) << BIT_SHIFT_RARF_RC7)
-#define BIT_GET_RARF_RC7(x) (((x) >> BIT_SHIFT_RARF_RC7) & BIT_MASK_RARF_RC7)
+/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */
+#define BIT_BCN_POLL BIT(28)
-#define BIT_SHIFT_RARF_RC6 (40 & CPU_OPT_WIDTH)
-#define BIT_MASK_RARF_RC6 0x1f
-#define BIT_RARF_RC6(x) (((x) & BIT_MASK_RARF_RC6) << BIT_SHIFT_RARF_RC6)
-#define BIT_GET_RARF_RC6(x) (((x) >> BIT_SHIFT_RARF_RC6) & BIT_MASK_RARF_RC6)
+#endif
+#if (HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_RARF_RC5 (32 & CPU_OPT_WIDTH)
-#define BIT_MASK_RARF_RC5 0x1f
-#define BIT_RARF_RC5(x) (((x) & BIT_MASK_RARF_RC5) << BIT_SHIFT_RARF_RC5)
-#define BIT_GET_RARF_RC5(x) (((x) >> BIT_SHIFT_RARF_RC5) & BIT_MASK_RARF_RC5)
+/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */
+#define BIT_CPUMGT_CLR BIT(27)
-#define BIT_SHIFT_RARF_RC4 24
-#define BIT_MASK_RARF_RC4 0x1f
-#define BIT_RARF_RC4(x) (((x) & BIT_MASK_RARF_RC4) << BIT_SHIFT_RARF_RC4)
-#define BIT_GET_RARF_RC4(x) (((x) >> BIT_SHIFT_RARF_RC4) & BIT_MASK_RARF_RC4)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_RARF_RC3 16
-#define BIT_MASK_RARF_RC3 0x1f
-#define BIT_RARF_RC3(x) (((x) & BIT_MASK_RARF_RC3) << BIT_SHIFT_RARF_RC3)
-#define BIT_GET_RARF_RC3(x) (((x) >> BIT_SHIFT_RARF_RC3) & BIT_MASK_RARF_RC3)
+/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */
+#define BIT_BCN_EXT_POLL BIT(21)
+#define BIT_BCN4_POLL BIT(20)
+#define BIT_BCN3_POLL BIT(19)
+#define BIT_BCN2_POLL BIT(18)
+#define BIT_BCN1_POLL_V1 BIT(17)
+#define BIT_BCN_POLL_V1 BIT(16)
-#define BIT_SHIFT_RARF_RC2 8
-#define BIT_MASK_RARF_RC2 0x1f
-#define BIT_RARF_RC2(x) (((x) & BIT_MASK_RARF_RC2) << BIT_SHIFT_RARF_RC2)
-#define BIT_GET_RARF_RC2(x) (((x) >> BIT_SHIFT_RARF_RC2) & BIT_MASK_RARF_RC2)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_RARF_RC1 0
-#define BIT_MASK_RARF_RC1 0x1f
-#define BIT_RARF_RC1(x) (((x) & BIT_MASK_RARF_RC1) << BIT_SHIFT_RARF_RC1)
-#define BIT_GET_RARF_RC1(x) (((x) >> BIT_SHIFT_RARF_RC1) & BIT_MASK_RARF_RC1)
+/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */
+#define BIT_CPUMGQ_FW_NUM_V1 BIT(12)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
+/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */
-/* 2 REG_RRSR (Offset 0x0440) */
+#define BIT_CPUMGQ_FW_NUM BIT(8)
-#define BIT_EN_VHTBW_FALL BIT(31)
-#define BIT_EN_HTBW_FALL BIT(30)
+#define BIT_SHIFT_CPUMGQ_HEAD_PG 0
+#define BIT_MASK_CPUMGQ_HEAD_PG 0xff
+#define BIT_CPUMGQ_HEAD_PG(x) \
+ (((x) & BIT_MASK_CPUMGQ_HEAD_PG) << BIT_SHIFT_CPUMGQ_HEAD_PG)
+#define BITS_CPUMGQ_HEAD_PG \
+ (BIT_MASK_CPUMGQ_HEAD_PG << BIT_SHIFT_CPUMGQ_HEAD_PG)
+#define BIT_CLEAR_CPUMGQ_HEAD_PG(x) ((x) & (~BITS_CPUMGQ_HEAD_PG))
+#define BIT_GET_CPUMGQ_HEAD_PG(x) \
+ (((x) >> BIT_SHIFT_CPUMGQ_HEAD_PG) & BIT_MASK_CPUMGQ_HEAD_PG)
+#define BIT_SET_CPUMGQ_HEAD_PG(x, v) \
+ (BIT_CLEAR_CPUMGQ_HEAD_PG(x) | BIT_CPUMGQ_HEAD_PG(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */
+#define BIT_SHIFT_FW_FREE_TAIL_V1 0
+#define BIT_MASK_FW_FREE_TAIL_V1 0xfff
+#define BIT_FW_FREE_TAIL_V1(x) \
+ (((x) & BIT_MASK_FW_FREE_TAIL_V1) << BIT_SHIFT_FW_FREE_TAIL_V1)
+#define BITS_FW_FREE_TAIL_V1 \
+ (BIT_MASK_FW_FREE_TAIL_V1 << BIT_SHIFT_FW_FREE_TAIL_V1)
+#define BIT_CLEAR_FW_FREE_TAIL_V1(x) ((x) & (~BITS_FW_FREE_TAIL_V1))
+#define BIT_GET_FW_FREE_TAIL_V1(x) \
+ (((x) >> BIT_SHIFT_FW_FREE_TAIL_V1) & BIT_MASK_FW_FREE_TAIL_V1)
+#define BIT_SET_FW_FREE_TAIL_V1(x, v) \
+ (BIT_CLEAR_FW_FREE_TAIL_V1(x) | BIT_FW_FREE_TAIL_V1(v))
-/* 2 REG_RRSR (Offset 0x0440) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_RRSR_RSC 21
-#define BIT_MASK_RRSR_RSC 0x3
-#define BIT_RRSR_RSC(x) (((x) & BIT_MASK_RRSR_RSC) << BIT_SHIFT_RRSR_RSC)
-#define BIT_GET_RRSR_RSC(x) (((x) >> BIT_SHIFT_RRSR_RSC) & BIT_MASK_RRSR_RSC)
+/* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */
-#define BIT_RRSR_BW BIT(20)
+#define BIT_SHIFT_FREE_TAIL_PAGE 0
+#define BIT_MASK_FREE_TAIL_PAGE 0xfff
+#define BIT_FREE_TAIL_PAGE(x) \
+ (((x) & BIT_MASK_FREE_TAIL_PAGE) << BIT_SHIFT_FREE_TAIL_PAGE)
+#define BITS_FREE_TAIL_PAGE \
+ (BIT_MASK_FREE_TAIL_PAGE << BIT_SHIFT_FREE_TAIL_PAGE)
+#define BIT_CLEAR_FREE_TAIL_PAGE(x) ((x) & (~BITS_FREE_TAIL_PAGE))
+#define BIT_GET_FREE_TAIL_PAGE(x) \
+ (((x) >> BIT_SHIFT_FREE_TAIL_PAGE) & BIT_MASK_FREE_TAIL_PAGE)
+#define BIT_SET_FREE_TAIL_PAGE(x, v) \
+ (BIT_CLEAR_FREE_TAIL_PAGE(x) | BIT_FREE_TAIL_PAGE(v))
-#define BIT_SHIFT_RRSC_BITMAP 0
-#define BIT_MASK_RRSC_BITMAP 0xfffff
-#define BIT_RRSC_BITMAP(x) (((x) & BIT_MASK_RRSC_BITMAP) << BIT_SHIFT_RRSC_BITMAP)
-#define BIT_GET_RRSC_BITMAP(x) (((x) >> BIT_SHIFT_RRSC_BITMAP) & BIT_MASK_RRSC_BITMAP)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-/* 2 REG_ARFR0 (Offset 0x0444) */
+/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */
+#define BIT_RTS_LIMIT_IN_OFDM BIT(23)
-#define BIT_SHIFT_ARFR0_V1 0
-#define BIT_MASK_ARFR0_V1 0xffffffffffffffffL
-#define BIT_ARFR0_V1(x) (((x) & BIT_MASK_ARFR0_V1) << BIT_SHIFT_ARFR0_V1)
-#define BIT_GET_ARFR0_V1(x) (((x) >> BIT_SHIFT_ARFR0_V1) & BIT_MASK_ARFR0_V1)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_ARFR1_V1 (Offset 0x044C) */
+/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */
+#define BIT_EN_BCNQ_DL BIT(22)
-#define BIT_SHIFT_ARFR1_V1 0
-#define BIT_MASK_ARFR1_V1 0xffffffffffffffffL
-#define BIT_ARFR1_V1(x) (((x) & BIT_MASK_ARFR1_V1) << BIT_SHIFT_ARFR1_V1)
-#define BIT_GET_ARFR1_V1(x) (((x) >> BIT_SHIFT_ARFR1_V1) & BIT_MASK_ARFR1_V1)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-/* 2 REG_CCK_CHECK (Offset 0x0454) */
+/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */
-#define BIT_CHECK_CCK_EN BIT(7)
-#define BIT_EN_BCN_PKT_REL BIT(6)
-#define BIT_BCN_PORT_SEL BIT(5)
-#define BIT_MOREDATA_BYPASS BIT(4)
-#define BIT_EN_CLR_CMD_REL_BCN_PKT BIT(3)
+#define BIT_EN_RD_RESP_NAV_BK BIT(21)
+#define BIT_EN_WR_FREE_TAIL BIT(20)
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */
+#define BIT_TXRPT_DIS BIT(19)
-/* 2 REG_CCK_CHECK (Offset 0x0454) */
+#endif
-#define BIT_R_EN_SET_MOREDATA BIT(2)
-#define BIT__R_DIS_CLEAR_MACID_RELEASE BIT(1)
-#define BIT__R_MACID_RELEASE_EN BIT(0)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */
+#define BIT_NOTXRPT_USERATE_EN BIT(19)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_AMPDU_BURST_CTRL (Offset 0x0455) */
+/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */
-#define BIT_AMPDU_BURST_GLOBAL_EN BIT(0)
+#define BIT_DIS_TXFAIL_RPT BIT(18)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */
+#define BIT_FTM_TIMEOUT_BYPASS BIT(16)
-/* 2 REG_AMPDU_MAX_TIME (Offset 0x0456) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_AMPDU_MAX_TIME 0
-#define BIT_MASK_AMPDU_MAX_TIME 0xff
-#define BIT_AMPDU_MAX_TIME(x) (((x) & BIT_MASK_AMPDU_MAX_TIME) << BIT_SHIFT_AMPDU_MAX_TIME)
-#define BIT_GET_AMPDU_MAX_TIME(x) (((x) >> BIT_SHIFT_AMPDU_MAX_TIME) & BIT_MASK_AMPDU_MAX_TIME)
+/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */
+#define BIT_EN_BCNQ_DL5 BIT(13)
+#define BIT_EN_BCNQ_DL4 BIT(12)
+#define BIT_EN_BCNQ_DL3 BIT(11)
+#define BIT_EN_BCNQ_DL2 BIT(10)
+#define BIT_EN_BCNQ_DL1 BIT(9)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */
+#define BIT_SHIFT_EN_QUEUE_RPT 8
+#define BIT_MASK_EN_QUEUE_RPT 0xff
+#define BIT_EN_QUEUE_RPT(x) \
+ (((x) & BIT_MASK_EN_QUEUE_RPT) << BIT_SHIFT_EN_QUEUE_RPT)
+#define BITS_EN_QUEUE_RPT (BIT_MASK_EN_QUEUE_RPT << BIT_SHIFT_EN_QUEUE_RPT)
+#define BIT_CLEAR_EN_QUEUE_RPT(x) ((x) & (~BITS_EN_QUEUE_RPT))
+#define BIT_GET_EN_QUEUE_RPT(x) \
+ (((x) >> BIT_SHIFT_EN_QUEUE_RPT) & BIT_MASK_EN_QUEUE_RPT)
+#define BIT_SET_EN_QUEUE_RPT(x, v) \
+ (BIT_CLEAR_EN_QUEUE_RPT(x) | BIT_EN_QUEUE_RPT(v))
-/* 2 REG_BCNQ1_BDNY_V1 (Offset 0x0456) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_BCNQ1_PGBNDY_V1 0
-#define BIT_MASK_BCNQ1_PGBNDY_V1 0xfff
-#define BIT_BCNQ1_PGBNDY_V1(x) (((x) & BIT_MASK_BCNQ1_PGBNDY_V1) << BIT_SHIFT_BCNQ1_PGBNDY_V1)
-#define BIT_GET_BCNQ1_PGBNDY_V1(x) (((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1) & BIT_MASK_BCNQ1_PGBNDY_V1)
+/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */
+#define BIT_EN_BCNQ_DL0 BIT(8)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */
+#define BIT_EN_RTY_BK BIT(7)
+#define BIT_EN_USE_INI_RAT BIT(6)
+#define BIT_EN_RTS_NAV_BK BIT(5)
+#define BIT_DIS_SSN_CHECK BIT(4)
+#define BIT_MACID_MATCH_RTS BIT(3)
-/* 2 REG_BCNQ1_BDNY (Offset 0x0457) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_BCNQ1_PGBNDY 0
-#define BIT_MASK_BCNQ1_PGBNDY 0xff
-#define BIT_BCNQ1_PGBNDY(x) (((x) & BIT_MASK_BCNQ1_PGBNDY) << BIT_SHIFT_BCNQ1_PGBNDY)
-#define BIT_GET_BCNQ1_PGBNDY(x) (((x) >> BIT_SHIFT_BCNQ1_PGBNDY) & BIT_MASK_BCNQ1_PGBNDY)
+/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */
+#define BIT_EN_BCN_TRXRPT_V1 BIT(2)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-
-/* 2 REG_AMPDU_MAX_LENGTH (Offset 0x0458) */
+/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */
+#define BIT_R_EN_FTMRPT BIT(1)
-#define BIT_SHIFT_AMPDU_MAX_LENGTH 0
-#define BIT_MASK_AMPDU_MAX_LENGTH 0xffffffffL
-#define BIT_AMPDU_MAX_LENGTH(x) (((x) & BIT_MASK_AMPDU_MAX_LENGTH) << BIT_SHIFT_AMPDU_MAX_LENGTH)
-#define BIT_GET_AMPDU_MAX_LENGTH(x) (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH) & BIT_MASK_AMPDU_MAX_LENGTH)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_ACQ_STOP (Offset 0x045C) */
+/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */
-#define BIT_AC7Q_STOP BIT(7)
-#define BIT_AC6Q_STOP BIT(6)
-#define BIT_AC5Q_STOP BIT(5)
-#define BIT_AC4Q_STOP BIT(4)
-#define BIT_AC3Q_STOP BIT(3)
-#define BIT_AC2Q_STOP BIT(2)
-#define BIT_AC1Q_STOP BIT(1)
-#define BIT_AC0Q_STOP BIT(0)
+#define BIT_EN_FTMRPT_V1 BIT(1)
#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */
+#define BIT_R_EN_FTMRPT_V1 BIT(1)
-/* 2 REG_WMAC_LBK_BUF_HD (Offset 0x045D) */
+#endif
+#if (HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_WMAC_LBK_BUF_HEAD 0
-#define BIT_MASK_WMAC_LBK_BUF_HEAD 0xff
-#define BIT_WMAC_LBK_BUF_HEAD(x) (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD) << BIT_SHIFT_WMAC_LBK_BUF_HEAD)
-#define BIT_GET_WMAC_LBK_BUF_HEAD(x) (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD) & BIT_MASK_WMAC_LBK_BUF_HEAD)
+/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */
+#define BIT_EN_FTMACKRPT BIT(1)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */
+#define BIT_R_BMC_NAV_PROTECT BIT(0)
-/* 2 REG_NDPA_RATE (Offset 0x045D) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_R_NDPA_RATE_V1 0
-#define BIT_MASK_R_NDPA_RATE_V1 0xff
-#define BIT_R_NDPA_RATE_V1(x) (((x) & BIT_MASK_R_NDPA_RATE_V1) << BIT_SHIFT_R_NDPA_RATE_V1)
-#define BIT_GET_R_NDPA_RATE_V1(x) (((x) >> BIT_SHIFT_R_NDPA_RATE_V1) & BIT_MASK_R_NDPA_RATE_V1)
+/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */
+#define BIT_BMC_NAV_PROTECT BIT(0)
#endif
+#if (HALMAC_8822B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */
+#define BIT_EN_FTMRPT BIT(0)
-/* 2 REG_TX_HANG_CTRL (Offset 0x045E) */
+#endif
-#define BIT_R_EN_GNT_BT_AWAKE BIT(3)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_HWSEQ_CTRL (Offset 0x0423) */
+#define BIT_HWSEQ_CPUM_EN BIT(7)
+#define BIT_HWSEQ_BCN_EN BIT(6)
+#define BIT_HWSEQ_HI_EN BIT(5)
+#define BIT_HWSEQ_MGT_EN BIT(4)
+#define BIT_HWSEQ_BK_EN BIT(3)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8198F_SUPPORT)
-/* 2 REG_TX_HANG_CTRL (Offset 0x045E) */
+/* 2 REG_DATAFB_SEL (Offset 0x0423) */
-#define BIT_EN_EOF_V1 BIT(2)
+#define BIT_R_BROADCAST_RETRY_EN BIT(3)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_DATAFB_SEL (Offset 0x0423) */
+#define BIT_BROADCAST_RTY_EN BIT(3)
-/* 2 REG_TX_HANG_CTRL (Offset 0x045E) */
+#endif
-#define BIT_DIS_OQT_BLOCK BIT(1)
-#define BIT_SEARCH_QUEUE_EN BIT(0)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_HWSEQ_CTRL (Offset 0x0423) */
+#define BIT_HWSEQ_BE_EN BIT(2)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */
+/* 2 REG_DATAFB_SEL (Offset 0x0423) */
-#define BIT_R_DIS_MACID_RELEASE_RTY BIT(5)
+#define BIT__R_EN_RTY_BK_COD BIT(2)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_DATAFB_SEL (Offset 0x0423) */
+#define BIT_EN_RTY_BK_COD BIT(2)
-/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_BW_SIGTA 3
-#define BIT_MASK_BW_SIGTA 0x3
-#define BIT_BW_SIGTA(x) (((x) & BIT_MASK_BW_SIGTA) << BIT_SHIFT_BW_SIGTA)
-#define BIT_GET_BW_SIGTA(x) (((x) >> BIT_SHIFT_BW_SIGTA) & BIT_MASK_BW_SIGTA)
+/* 2 REG_HWSEQ_CTRL (Offset 0x0423) */
+#define BIT_HWSEQ_VI_EN BIT(1)
+#define BIT_HWSEQ_VO_EN BIT(0)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_DATAFB_SEL (Offset 0x0423) */
+#define BIT_SHIFT__R_DATA_FALLBACK_SEL 0
+#define BIT_MASK__R_DATA_FALLBACK_SEL 0x3
+#define BIT__R_DATA_FALLBACK_SEL(x) \
+ (((x) & BIT_MASK__R_DATA_FALLBACK_SEL) \
+ << BIT_SHIFT__R_DATA_FALLBACK_SEL)
+#define BITS__R_DATA_FALLBACK_SEL \
+ (BIT_MASK__R_DATA_FALLBACK_SEL << BIT_SHIFT__R_DATA_FALLBACK_SEL)
+#define BIT_CLEAR__R_DATA_FALLBACK_SEL(x) ((x) & (~BITS__R_DATA_FALLBACK_SEL))
+#define BIT_GET__R_DATA_FALLBACK_SEL(x) \
+ (((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL) & \
+ BIT_MASK__R_DATA_FALLBACK_SEL)
+#define BIT_SET__R_DATA_FALLBACK_SEL(x, v) \
+ (BIT_CLEAR__R_DATA_FALLBACK_SEL(x) | BIT__R_DATA_FALLBACK_SEL(v))
-/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_R_NDPA_RATE 2
-#define BIT_MASK_R_NDPA_RATE 0x3f
-#define BIT_R_NDPA_RATE(x) (((x) & BIT_MASK_R_NDPA_RATE) << BIT_SHIFT_R_NDPA_RATE)
-#define BIT_GET_R_NDPA_RATE(x) (((x) >> BIT_SHIFT_R_NDPA_RATE) & BIT_MASK_R_NDPA_RATE)
+/* 2 REG_DATAFB_SEL (Offset 0x0423) */
+#define BIT_SHIFT__DATA_FALLBACK_SEL 0
+#define BIT_MASK__DATA_FALLBACK_SEL 0x3
+#define BIT__DATA_FALLBACK_SEL(x) \
+ (((x) & BIT_MASK__DATA_FALLBACK_SEL) << BIT_SHIFT__DATA_FALLBACK_SEL)
+#define BITS__DATA_FALLBACK_SEL \
+ (BIT_MASK__DATA_FALLBACK_SEL << BIT_SHIFT__DATA_FALLBACK_SEL)
+#define BIT_CLEAR__DATA_FALLBACK_SEL(x) ((x) & (~BITS__DATA_FALLBACK_SEL))
+#define BIT_GET__DATA_FALLBACK_SEL(x) \
+ (((x) >> BIT_SHIFT__DATA_FALLBACK_SEL) & BIT_MASK__DATA_FALLBACK_SEL)
+#define BIT_SET__DATA_FALLBACK_SEL(x, v) \
+ (BIT_CLEAR__DATA_FALLBACK_SEL(x) | BIT__DATA_FALLBACK_SEL(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_BCNQ_BDNY (Offset 0x0424) */
+#define BIT_SHIFT_BCNQ_PGBNDY 0
+#define BIT_MASK_BCNQ_PGBNDY 0xff
+#define BIT_BCNQ_PGBNDY(x) \
+ (((x) & BIT_MASK_BCNQ_PGBNDY) << BIT_SHIFT_BCNQ_PGBNDY)
+#define BITS_BCNQ_PGBNDY (BIT_MASK_BCNQ_PGBNDY << BIT_SHIFT_BCNQ_PGBNDY)
+#define BIT_CLEAR_BCNQ_PGBNDY(x) ((x) & (~BITS_BCNQ_PGBNDY))
+#define BIT_GET_BCNQ_PGBNDY(x) \
+ (((x) >> BIT_SHIFT_BCNQ_PGBNDY) & BIT_MASK_BCNQ_PGBNDY)
+#define BIT_SET_BCNQ_PGBNDY(x, v) \
+ (BIT_CLEAR_BCNQ_PGBNDY(x) | BIT_BCNQ_PGBNDY(v))
-/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BCNQ_BDNY_V1 (Offset 0x0424) */
-#define BIT_EN_BAR_SIGTA BIT(2)
+#define BIT_SHIFT_BCNQ_PGBNDY_V1 0
+#define BIT_MASK_BCNQ_PGBNDY_V1 0xfff
+#define BIT_BCNQ_PGBNDY_V1(x) \
+ (((x) & BIT_MASK_BCNQ_PGBNDY_V1) << BIT_SHIFT_BCNQ_PGBNDY_V1)
+#define BITS_BCNQ_PGBNDY_V1 \
+ (BIT_MASK_BCNQ_PGBNDY_V1 << BIT_SHIFT_BCNQ_PGBNDY_V1)
+#define BIT_CLEAR_BCNQ_PGBNDY_V1(x) ((x) & (~BITS_BCNQ_PGBNDY_V1))
+#define BIT_GET_BCNQ_PGBNDY_V1(x) \
+ (((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1) & BIT_MASK_BCNQ_PGBNDY_V1)
+#define BIT_SET_BCNQ_PGBNDY_V1(x, v) \
+ (BIT_CLEAR_BCNQ_PGBNDY_V1(x) | BIT_BCNQ_PGBNDY_V1(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_TXBDNY (Offset 0x0424) */
+#define BIT_SHIFT_TXBNDY 0
+#define BIT_MASK_TXBNDY 0xfff
+#define BIT_TXBNDY(x) (((x) & BIT_MASK_TXBNDY) << BIT_SHIFT_TXBNDY)
+#define BITS_TXBNDY (BIT_MASK_TXBNDY << BIT_SHIFT_TXBNDY)
+#define BIT_CLEAR_TXBNDY(x) ((x) & (~BITS_TXBNDY))
+#define BIT_GET_TXBNDY(x) (((x) >> BIT_SHIFT_TXBNDY) & BIT_MASK_TXBNDY)
+#define BIT_SET_TXBNDY(x, v) (BIT_CLEAR_TXBNDY(x) | BIT_TXBNDY(v))
-/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_R_NDPA_BW 0
-#define BIT_MASK_R_NDPA_BW 0x3
-#define BIT_R_NDPA_BW(x) (((x) & BIT_MASK_R_NDPA_BW) << BIT_SHIFT_R_NDPA_BW)
-#define BIT_GET_R_NDPA_BW(x) (((x) >> BIT_SHIFT_R_NDPA_BW) & BIT_MASK_R_NDPA_BW)
+/* 2 REG_MGQ_BDNY (Offset 0x0425) */
+#define BIT_SHIFT_MGQ_PGBNDY 0
+#define BIT_MASK_MGQ_PGBNDY 0xff
+#define BIT_MGQ_PGBNDY(x) (((x) & BIT_MASK_MGQ_PGBNDY) << BIT_SHIFT_MGQ_PGBNDY)
+#define BITS_MGQ_PGBNDY (BIT_MASK_MGQ_PGBNDY << BIT_SHIFT_MGQ_PGBNDY)
+#define BIT_CLEAR_MGQ_PGBNDY(x) ((x) & (~BITS_MGQ_PGBNDY))
+#define BIT_GET_MGQ_PGBNDY(x) \
+ (((x) >> BIT_SHIFT_MGQ_PGBNDY) & BIT_MASK_MGQ_PGBNDY)
+#define BIT_SET_MGQ_PGBNDY(x, v) (BIT_CLEAR_MGQ_PGBNDY(x) | BIT_MGQ_PGBNDY(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_LIFETIME_EN (Offset 0x0426) */
+#define BIT_BT_INT_CPU BIT(7)
+#define BIT_BT_INT_PTA BIT(6)
-/* 2 REG_FAST_EDCA_CTRL (Offset 0x0460) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_FAST_EDCA_TO_V1 16
-#define BIT_MASK_FAST_EDCA_TO_V1 0xff
-#define BIT_FAST_EDCA_TO_V1(x) (((x) & BIT_MASK_FAST_EDCA_TO_V1) << BIT_SHIFT_FAST_EDCA_TO_V1)
-#define BIT_GET_FAST_EDCA_TO_V1(x) (((x) >> BIT_SHIFT_FAST_EDCA_TO_V1) & BIT_MASK_FAST_EDCA_TO_V1)
+/* 2 REG_LIFETIME_EN (Offset 0x0426) */
+#define BIT_SPERPT_ENTRY BIT(5)
+#define BIT_RTYCNT_FB BIT(4)
-#define BIT_SHIFT_AC3_AC7_FAST_EDCA_PKT_TH 12
-#define BIT_MASK_AC3_AC7_FAST_EDCA_PKT_TH 0xf
-#define BIT_AC3_AC7_FAST_EDCA_PKT_TH(x) (((x) & BIT_MASK_AC3_AC7_FAST_EDCA_PKT_TH) << BIT_SHIFT_AC3_AC7_FAST_EDCA_PKT_TH)
-#define BIT_GET_AC3_AC7_FAST_EDCA_PKT_TH(x) (((x) >> BIT_SHIFT_AC3_AC7_FAST_EDCA_PKT_TH) & BIT_MASK_AC3_AC7_FAST_EDCA_PKT_TH)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_AC2_FAST_EDCA_PKT_TH 8
-#define BIT_MASK_AC2_FAST_EDCA_PKT_TH 0xf
-#define BIT_AC2_FAST_EDCA_PKT_TH(x) (((x) & BIT_MASK_AC2_FAST_EDCA_PKT_TH) << BIT_SHIFT_AC2_FAST_EDCA_PKT_TH)
-#define BIT_GET_AC2_FAST_EDCA_PKT_TH(x) (((x) >> BIT_SHIFT_AC2_FAST_EDCA_PKT_TH) & BIT_MASK_AC2_FAST_EDCA_PKT_TH)
+/* 2 REG_LIFETIME_EN (Offset 0x0426) */
+#define BIT_EN_CTRL_RTYBIT BIT(4)
-#define BIT_SHIFT_AC1_FAST_EDCA_PKT_TH 4
-#define BIT_MASK_AC1_FAST_EDCA_PKT_TH 0xf
-#define BIT_AC1_FAST_EDCA_PKT_TH(x) (((x) & BIT_MASK_AC1_FAST_EDCA_PKT_TH) << BIT_SHIFT_AC1_FAST_EDCA_PKT_TH)
-#define BIT_GET_AC1_FAST_EDCA_PKT_TH(x) (((x) >> BIT_SHIFT_AC1_FAST_EDCA_PKT_TH) & BIT_MASK_AC1_FAST_EDCA_PKT_TH)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_AC0_FAST_EDCA_PKT_TH 0
-#define BIT_MASK_AC0_FAST_EDCA_PKT_TH 0xf
-#define BIT_AC0_FAST_EDCA_PKT_TH(x) (((x) & BIT_MASK_AC0_FAST_EDCA_PKT_TH) << BIT_SHIFT_AC0_FAST_EDCA_PKT_TH)
-#define BIT_GET_AC0_FAST_EDCA_PKT_TH(x) (((x) >> BIT_SHIFT_AC0_FAST_EDCA_PKT_TH) & BIT_MASK_AC0_FAST_EDCA_PKT_TH)
+/* 2 REG_LIFETIME_EN (Offset 0x0426) */
+#define BIT_LIFETIME_BK_EN BIT(3)
+#define BIT_LIFETIME_BE_EN BIT(2)
+#define BIT_LIFETIME_VI_EN BIT(1)
+#define BIT_LIFETIME_VO_EN BIT(0)
-/* 2 REG_RD_RESP_PKT_TH (Offset 0x0463) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_RD_RESP_PKT_TH 0
-#define BIT_MASK_RD_RESP_PKT_TH 0x1f
-#define BIT_RD_RESP_PKT_TH(x) (((x) & BIT_MASK_RD_RESP_PKT_TH) << BIT_SHIFT_RD_RESP_PKT_TH)
-#define BIT_GET_RD_RESP_PKT_TH(x) (((x) >> BIT_SHIFT_RD_RESP_PKT_TH) & BIT_MASK_RD_RESP_PKT_TH)
+/* 2 REG_FW_FREE_TAIL (Offset 0x0427) */
+#define BIT_SHIFT_FW_FREE_TAIL 0
+#define BIT_MASK_FW_FREE_TAIL 0xff
+#define BIT_FW_FREE_TAIL(x) \
+ (((x) & BIT_MASK_FW_FREE_TAIL) << BIT_SHIFT_FW_FREE_TAIL)
+#define BITS_FW_FREE_TAIL (BIT_MASK_FW_FREE_TAIL << BIT_SHIFT_FW_FREE_TAIL)
+#define BIT_CLEAR_FW_FREE_TAIL(x) ((x) & (~BITS_FW_FREE_TAIL))
+#define BIT_GET_FW_FREE_TAIL(x) \
+ (((x) >> BIT_SHIFT_FW_FREE_TAIL) & BIT_MASK_FW_FREE_TAIL)
+#define BIT_SET_FW_FREE_TAIL(x, v) \
+ (BIT_CLEAR_FW_FREE_TAIL(x) | BIT_FW_FREE_TAIL(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+/* 2 REG_SPEC_SIFS (Offset 0x0428) */
-/* 2 REG_RD_RESP_PKT_TH (Offset 0x0463) */
+#define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL 8
+#define BIT_MASK_SPEC_SIFS_OFDM_PTCL 0xff
+#define BIT_SPEC_SIFS_OFDM_PTCL(x) \
+ (((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL) << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL)
+#define BITS_SPEC_SIFS_OFDM_PTCL \
+ (BIT_MASK_SPEC_SIFS_OFDM_PTCL << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL)
+#define BIT_CLEAR_SPEC_SIFS_OFDM_PTCL(x) ((x) & (~BITS_SPEC_SIFS_OFDM_PTCL))
+#define BIT_GET_SPEC_SIFS_OFDM_PTCL(x) \
+ (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL) & BIT_MASK_SPEC_SIFS_OFDM_PTCL)
+#define BIT_SET_SPEC_SIFS_OFDM_PTCL(x, v) \
+ (BIT_CLEAR_SPEC_SIFS_OFDM_PTCL(x) | BIT_SPEC_SIFS_OFDM_PTCL(v))
+
+#define BIT_SHIFT_SPEC_SIFS_CCK_PTCL 0
+#define BIT_MASK_SPEC_SIFS_CCK_PTCL 0xff
+#define BIT_SPEC_SIFS_CCK_PTCL(x) \
+ (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL) << BIT_SHIFT_SPEC_SIFS_CCK_PTCL)
+#define BITS_SPEC_SIFS_CCK_PTCL \
+ (BIT_MASK_SPEC_SIFS_CCK_PTCL << BIT_SHIFT_SPEC_SIFS_CCK_PTCL)
+#define BIT_CLEAR_SPEC_SIFS_CCK_PTCL(x) ((x) & (~BITS_SPEC_SIFS_CCK_PTCL))
+#define BIT_GET_SPEC_SIFS_CCK_PTCL(x) \
+ (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL) & BIT_MASK_SPEC_SIFS_CCK_PTCL)
+#define BIT_SET_SPEC_SIFS_CCK_PTCL(x, v) \
+ (BIT_CLEAR_SPEC_SIFS_CCK_PTCL(x) | BIT_SPEC_SIFS_CCK_PTCL(v))
+/* 2 REG_RETRY_LIMIT (Offset 0x042A) */
-#define BIT_SHIFT_RD_RESP_PKT_TH_V1 0
-#define BIT_MASK_RD_RESP_PKT_TH_V1 0x3f
-#define BIT_RD_RESP_PKT_TH_V1(x) (((x) & BIT_MASK_RD_RESP_PKT_TH_V1) << BIT_SHIFT_RD_RESP_PKT_TH_V1)
-#define BIT_GET_RD_RESP_PKT_TH_V1(x) (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1) & BIT_MASK_RD_RESP_PKT_TH_V1)
+#define BIT_SHIFT_SRL 8
+#define BIT_MASK_SRL 0x3f
+#define BIT_SRL(x) (((x) & BIT_MASK_SRL) << BIT_SHIFT_SRL)
+#define BITS_SRL (BIT_MASK_SRL << BIT_SHIFT_SRL)
+#define BIT_CLEAR_SRL(x) ((x) & (~BITS_SRL))
+#define BIT_GET_SRL(x) (((x) >> BIT_SHIFT_SRL) & BIT_MASK_SRL)
+#define BIT_SET_SRL(x, v) (BIT_CLEAR_SRL(x) | BIT_SRL(v))
+#define BIT_SHIFT_LRL 0
+#define BIT_MASK_LRL 0x3f
+#define BIT_LRL(x) (((x) & BIT_MASK_LRL) << BIT_SHIFT_LRL)
+#define BITS_LRL (BIT_MASK_LRL << BIT_SHIFT_LRL)
+#define BIT_CLEAR_LRL(x) ((x) & (~BITS_LRL))
+#define BIT_GET_LRL(x) (((x) >> BIT_SHIFT_LRL) & BIT_MASK_LRL)
+#define BIT_SET_LRL(x, v) (BIT_CLEAR_LRL(x) | BIT_LRL(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_TXBF_CTRL (Offset 0x042C) */
+#define BIT_R_ENABLE_NDPA BIT(31)
-/* 2 REG_CMDQ_INFO (Offset 0x0464) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_QUEUEMACID_CMDQ_V1 25
-#define BIT_MASK_QUEUEMACID_CMDQ_V1 0x7f
-#define BIT_QUEUEMACID_CMDQ_V1(x) (((x) & BIT_MASK_QUEUEMACID_CMDQ_V1) << BIT_SHIFT_QUEUEMACID_CMDQ_V1)
-#define BIT_GET_QUEUEMACID_CMDQ_V1(x) (((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1) & BIT_MASK_QUEUEMACID_CMDQ_V1)
+/* 2 REG_TXBF_CTRL (Offset 0x042C) */
+#define BIT_ENABLE_NDPA BIT(31)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_TXBF_CTRL (Offset 0x042C) */
+#define BIT_USE_NDPA_PARAMETER BIT(30)
-/* 2 REG_CMDQ_INFO (Offset 0x0464) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_PKT_NUM_CMDQ_V2 24
-#define BIT_MASK_PKT_NUM_CMDQ_V2 0xff
-#define BIT_PKT_NUM_CMDQ_V2(x) (((x) & BIT_MASK_PKT_NUM_CMDQ_V2) << BIT_SHIFT_PKT_NUM_CMDQ_V2)
-#define BIT_GET_PKT_NUM_CMDQ_V2(x) (((x) >> BIT_SHIFT_PKT_NUM_CMDQ_V2) & BIT_MASK_PKT_NUM_CMDQ_V2)
+/* 2 REG_TXBF_CTRL (Offset 0x042C) */
+#define BIT_NDPA_PARA BIT(30)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_TXBF_CTRL (Offset 0x042C) */
+#define BIT_R_PROP_TXBF BIT(29)
-/* 2 REG_CMDQ_INFO (Offset 0x0464) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_PKT_NUM 23
-#define BIT_MASK_PKT_NUM 0x1ff
-#define BIT_PKT_NUM(x) (((x) & BIT_MASK_PKT_NUM) << BIT_SHIFT_PKT_NUM)
-#define BIT_GET_PKT_NUM(x) (((x) >> BIT_SHIFT_PKT_NUM) & BIT_MASK_PKT_NUM)
+/* 2 REG_TXBF_CTRL (Offset 0x042C) */
+#define BIT_PROP_TXBF BIT(29)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_TXBF_CTRL (Offset 0x042C) */
+#define BIT_R_EN_NDPA_INT BIT(28)
-/* 2 REG_CMDQ_INFO (Offset 0x0464) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_QUEUEAC_CMDQ_V1 23
-#define BIT_MASK_QUEUEAC_CMDQ_V1 0x3
-#define BIT_QUEUEAC_CMDQ_V1(x) (((x) & BIT_MASK_QUEUEAC_CMDQ_V1) << BIT_SHIFT_QUEUEAC_CMDQ_V1)
-#define BIT_GET_QUEUEAC_CMDQ_V1(x) (((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1) & BIT_MASK_QUEUEAC_CMDQ_V1)
+/* 2 REG_TXBF_CTRL (Offset 0x042C) */
+#define BIT_EN_NDPA_INT BIT(28)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_CMDQ_INFO (Offset 0x0464) */
+/* 2 REG_TXBF_CTRL (Offset 0x042C) */
-#define BIT_TIDEMPTY_CMDQ_V1 BIT(22)
+#define BIT_R_TXBF1_80M BIT(27)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_TXBF_CTRL (Offset 0x042C) */
+#define BIT_TXBF1_80M_160M BIT(27)
-/* 2 REG_CMDQ_INFO (Offset 0x0464) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_TAIL_PKT_CMDQ 16
-#define BIT_MASK_TAIL_PKT_CMDQ 0xff
-#define BIT_TAIL_PKT_CMDQ(x) (((x) & BIT_MASK_TAIL_PKT_CMDQ) << BIT_SHIFT_TAIL_PKT_CMDQ)
-#define BIT_GET_TAIL_PKT_CMDQ(x) (((x) >> BIT_SHIFT_TAIL_PKT_CMDQ) & BIT_MASK_TAIL_PKT_CMDQ)
+/* 2 REG_TXBF_CTRL (Offset 0x042C) */
+#define BIT_R_TXBF1_40M BIT(26)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_TXBF_CTRL (Offset 0x042C) */
+#define BIT_TXBF1_40M BIT(26)
-/* 2 REG_CMDQ_INFO (Offset 0x0464) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_TAIL_PKT_CMDQ_V2 11
-#define BIT_MASK_TAIL_PKT_CMDQ_V2 0x7ff
-#define BIT_TAIL_PKT_CMDQ_V2(x) (((x) & BIT_MASK_TAIL_PKT_CMDQ_V2) << BIT_SHIFT_TAIL_PKT_CMDQ_V2)
-#define BIT_GET_TAIL_PKT_CMDQ_V2(x) (((x) >> BIT_SHIFT_TAIL_PKT_CMDQ_V2) & BIT_MASK_TAIL_PKT_CMDQ_V2)
+/* 2 REG_TXBF_CTRL (Offset 0x042C) */
+#define BIT_R_TXBF1_20M BIT(25)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-
-/* 2 REG_CMDQ_INFO (Offset 0x0464) */
+/* 2 REG_TXBF_CTRL (Offset 0x042C) */
+#define BIT_TXBF1_20M BIT(25)
-#define BIT_SHIFT_PKT_NUM_CMDQ 8
-#define BIT_MASK_PKT_NUM_CMDQ 0xff
-#define BIT_PKT_NUM_CMDQ(x) (((x) & BIT_MASK_PKT_NUM_CMDQ) << BIT_SHIFT_PKT_NUM_CMDQ)
-#define BIT_GET_PKT_NUM_CMDQ(x) (((x) >> BIT_SHIFT_PKT_NUM_CMDQ) & BIT_MASK_PKT_NUM_CMDQ)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_HEAD_PKT_CMDQ 0
-#define BIT_MASK_HEAD_PKT_CMDQ 0xff
-#define BIT_HEAD_PKT_CMDQ(x) (((x) & BIT_MASK_HEAD_PKT_CMDQ) << BIT_SHIFT_HEAD_PKT_CMDQ)
-#define BIT_GET_HEAD_PKT_CMDQ(x) (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ) & BIT_MASK_HEAD_PKT_CMDQ)
+/* 2 REG_TXBF_CTRL (Offset 0x042C) */
+#define BIT_SHIFT_R_TXBF1_AID 16
+#define BIT_MASK_R_TXBF1_AID 0x1ff
+#define BIT_R_TXBF1_AID(x) \
+ (((x) & BIT_MASK_R_TXBF1_AID) << BIT_SHIFT_R_TXBF1_AID)
+#define BITS_R_TXBF1_AID (BIT_MASK_R_TXBF1_AID << BIT_SHIFT_R_TXBF1_AID)
+#define BIT_CLEAR_R_TXBF1_AID(x) ((x) & (~BITS_R_TXBF1_AID))
+#define BIT_GET_R_TXBF1_AID(x) \
+ (((x) >> BIT_SHIFT_R_TXBF1_AID) & BIT_MASK_R_TXBF1_AID)
+#define BIT_SET_R_TXBF1_AID(x, v) \
+ (BIT_CLEAR_R_TXBF1_AID(x) | BIT_R_TXBF1_AID(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_TXBF_CTRL (Offset 0x042C) */
+#define BIT_SHIFT_TXBF1_AID 16
+#define BIT_MASK_TXBF1_AID 0x1ff
+#define BIT_TXBF1_AID(x) (((x) & BIT_MASK_TXBF1_AID) << BIT_SHIFT_TXBF1_AID)
+#define BITS_TXBF1_AID (BIT_MASK_TXBF1_AID << BIT_SHIFT_TXBF1_AID)
+#define BIT_CLEAR_TXBF1_AID(x) ((x) & (~BITS_TXBF1_AID))
+#define BIT_GET_TXBF1_AID(x) (((x) >> BIT_SHIFT_TXBF1_AID) & BIT_MASK_TXBF1_AID)
+#define BIT_SET_TXBF1_AID(x, v) (BIT_CLEAR_TXBF1_AID(x) | BIT_TXBF1_AID(v))
-/* 2 REG_CMDQ_INFO (Offset 0x0464) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_HEAD_PKT_CMDQ_V1 0
-#define BIT_MASK_HEAD_PKT_CMDQ_V1 0x7ff
-#define BIT_HEAD_PKT_CMDQ_V1(x) (((x) & BIT_MASK_HEAD_PKT_CMDQ_V1) << BIT_SHIFT_HEAD_PKT_CMDQ_V1)
-#define BIT_GET_HEAD_PKT_CMDQ_V1(x) (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1) & BIT_MASK_HEAD_PKT_CMDQ_V1)
+/* 2 REG_TXBF_CTRL (Offset 0x042C) */
+#define BIT_DIS_NDP_BFEN BIT(15)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_TXBF_CTRL (Offset 0x042C) */
+#define BIT_R_TXBCN_NOBLOCK_NDP BIT(14)
-/* 2 REG_Q4_INFO (Offset 0x0468) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_QUEUEMACID_Q4_V1 25
-#define BIT_MASK_QUEUEMACID_Q4_V1 0x7f
-#define BIT_QUEUEMACID_Q4_V1(x) (((x) & BIT_MASK_QUEUEMACID_Q4_V1) << BIT_SHIFT_QUEUEMACID_Q4_V1)
-#define BIT_GET_QUEUEMACID_Q4_V1(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1) & BIT_MASK_QUEUEMACID_Q4_V1)
+/* 2 REG_TXBF_CTRL (Offset 0x042C) */
+#define BIT_TXBCN_NOBLOCK_NDP BIT(14)
-#define BIT_SHIFT_QUEUEAC_Q4_V1 23
-#define BIT_MASK_QUEUEAC_Q4_V1 0x3
-#define BIT_QUEUEAC_Q4_V1(x) (((x) & BIT_MASK_QUEUEAC_Q4_V1) << BIT_SHIFT_QUEUEAC_Q4_V1)
-#define BIT_GET_QUEUEAC_Q4_V1(x) (((x) >> BIT_SHIFT_QUEUEAC_Q4_V1) & BIT_MASK_QUEUEAC_Q4_V1)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_TXBF_CTRL (Offset 0x042C) */
+#define BIT_R_TXBF0_80M BIT(11)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_Q4_INFO (Offset 0x0468) */
+/* 2 REG_TXBF_CTRL (Offset 0x042C) */
-#define BIT_TIDEMPTY_Q4_V1 BIT(22)
+#define BIT_TXBF0_80M_160M BIT(11)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_TXBF_CTRL (Offset 0x042C) */
+#define BIT_R_TXBF0_40M BIT(10)
-/* 2 REG_Q4_INFO (Offset 0x0468) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_TAIL_PKT_Q4_V1 15
-#define BIT_MASK_TAIL_PKT_Q4_V1 0xff
-#define BIT_TAIL_PKT_Q4_V1(x) (((x) & BIT_MASK_TAIL_PKT_Q4_V1) << BIT_SHIFT_TAIL_PKT_Q4_V1)
-#define BIT_GET_TAIL_PKT_Q4_V1(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V1) & BIT_MASK_TAIL_PKT_Q4_V1)
+/* 2 REG_TXBF_CTRL (Offset 0x042C) */
+#define BIT_TXBF0_40M BIT(10)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_TXBF_CTRL (Offset 0x042C) */
+#define BIT_R_TXBF0_20M BIT(9)
-/* 2 REG_Q4_INFO (Offset 0x0468) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_TAIL_PKT_Q4_V2 11
-#define BIT_MASK_TAIL_PKT_Q4_V2 0x7ff
-#define BIT_TAIL_PKT_Q4_V2(x) (((x) & BIT_MASK_TAIL_PKT_Q4_V2) << BIT_SHIFT_TAIL_PKT_Q4_V2)
-#define BIT_GET_TAIL_PKT_Q4_V2(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2) & BIT_MASK_TAIL_PKT_Q4_V2)
+/* 2 REG_TXBF_CTRL (Offset 0x042C) */
+#define BIT_TXBF0_20M BIT(9)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-
-/* 2 REG_Q4_INFO (Offset 0x0468) */
+/* 2 REG_TXBF_CTRL (Offset 0x042C) */
+#define BIT_SHIFT_R_TXBF0_AID 0
+#define BIT_MASK_R_TXBF0_AID 0x1ff
+#define BIT_R_TXBF0_AID(x) \
+ (((x) & BIT_MASK_R_TXBF0_AID) << BIT_SHIFT_R_TXBF0_AID)
+#define BITS_R_TXBF0_AID (BIT_MASK_R_TXBF0_AID << BIT_SHIFT_R_TXBF0_AID)
+#define BIT_CLEAR_R_TXBF0_AID(x) ((x) & (~BITS_R_TXBF0_AID))
+#define BIT_GET_R_TXBF0_AID(x) \
+ (((x) >> BIT_SHIFT_R_TXBF0_AID) & BIT_MASK_R_TXBF0_AID)
+#define BIT_SET_R_TXBF0_AID(x, v) \
+ (BIT_CLEAR_R_TXBF0_AID(x) | BIT_R_TXBF0_AID(v))
-#define BIT_SHIFT_PKT_NUM_Q4_V1 8
-#define BIT_MASK_PKT_NUM_Q4_V1 0x7f
-#define BIT_PKT_NUM_Q4_V1(x) (((x) & BIT_MASK_PKT_NUM_Q4_V1) << BIT_SHIFT_PKT_NUM_Q4_V1)
-#define BIT_GET_PKT_NUM_Q4_V1(x) (((x) >> BIT_SHIFT_PKT_NUM_Q4_V1) & BIT_MASK_PKT_NUM_Q4_V1)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_HEAD_PKT_Q4 0
-#define BIT_MASK_HEAD_PKT_Q4 0xff
-#define BIT_HEAD_PKT_Q4(x) (((x) & BIT_MASK_HEAD_PKT_Q4) << BIT_SHIFT_HEAD_PKT_Q4)
-#define BIT_GET_HEAD_PKT_Q4(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q4) & BIT_MASK_HEAD_PKT_Q4)
+/* 2 REG_TXBF_CTRL (Offset 0x042C) */
+#define BIT_SHIFT_TXBF0_AID 0
+#define BIT_MASK_TXBF0_AID 0x1ff
+#define BIT_TXBF0_AID(x) (((x) & BIT_MASK_TXBF0_AID) << BIT_SHIFT_TXBF0_AID)
+#define BITS_TXBF0_AID (BIT_MASK_TXBF0_AID << BIT_SHIFT_TXBF0_AID)
+#define BIT_CLEAR_TXBF0_AID(x) ((x) & (~BITS_TXBF0_AID))
+#define BIT_GET_TXBF0_AID(x) (((x) >> BIT_SHIFT_TXBF0_AID) & BIT_MASK_TXBF0_AID)
+#define BIT_SET_TXBF0_AID(x, v) (BIT_CLEAR_TXBF0_AID(x) | BIT_TXBF0_AID(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_Q4_INFO (Offset 0x0468) */
+/* 2 REG_DARFRC (Offset 0x0430) */
+#define BIT_SHIFT_DARF_RC8 (56 & CPU_OPT_WIDTH)
+#define BIT_MASK_DARF_RC8 0x1f
+#define BIT_DARF_RC8(x) (((x) & BIT_MASK_DARF_RC8) << BIT_SHIFT_DARF_RC8)
+#define BITS_DARF_RC8 (BIT_MASK_DARF_RC8 << BIT_SHIFT_DARF_RC8)
+#define BIT_CLEAR_DARF_RC8(x) ((x) & (~BITS_DARF_RC8))
+#define BIT_GET_DARF_RC8(x) (((x) >> BIT_SHIFT_DARF_RC8) & BIT_MASK_DARF_RC8)
+#define BIT_SET_DARF_RC8(x, v) (BIT_CLEAR_DARF_RC8(x) | BIT_DARF_RC8(v))
+
+#define BIT_SHIFT_DARF_RC7 (48 & CPU_OPT_WIDTH)
+#define BIT_MASK_DARF_RC7 0x1f
+#define BIT_DARF_RC7(x) (((x) & BIT_MASK_DARF_RC7) << BIT_SHIFT_DARF_RC7)
+#define BITS_DARF_RC7 (BIT_MASK_DARF_RC7 << BIT_SHIFT_DARF_RC7)
+#define BIT_CLEAR_DARF_RC7(x) ((x) & (~BITS_DARF_RC7))
+#define BIT_GET_DARF_RC7(x) (((x) >> BIT_SHIFT_DARF_RC7) & BIT_MASK_DARF_RC7)
+#define BIT_SET_DARF_RC7(x, v) (BIT_CLEAR_DARF_RC7(x) | BIT_DARF_RC7(v))
+
+#define BIT_SHIFT_DARF_RC6 (40 & CPU_OPT_WIDTH)
+#define BIT_MASK_DARF_RC6 0x1f
+#define BIT_DARF_RC6(x) (((x) & BIT_MASK_DARF_RC6) << BIT_SHIFT_DARF_RC6)
+#define BITS_DARF_RC6 (BIT_MASK_DARF_RC6 << BIT_SHIFT_DARF_RC6)
+#define BIT_CLEAR_DARF_RC6(x) ((x) & (~BITS_DARF_RC6))
+#define BIT_GET_DARF_RC6(x) (((x) >> BIT_SHIFT_DARF_RC6) & BIT_MASK_DARF_RC6)
+#define BIT_SET_DARF_RC6(x, v) (BIT_CLEAR_DARF_RC6(x) | BIT_DARF_RC6(v))
+
+#define BIT_SHIFT_DARF_RC5 (32 & CPU_OPT_WIDTH)
+#define BIT_MASK_DARF_RC5 0x1f
+#define BIT_DARF_RC5(x) (((x) & BIT_MASK_DARF_RC5) << BIT_SHIFT_DARF_RC5)
+#define BITS_DARF_RC5 (BIT_MASK_DARF_RC5 << BIT_SHIFT_DARF_RC5)
+#define BIT_CLEAR_DARF_RC5(x) ((x) & (~BITS_DARF_RC5))
+#define BIT_GET_DARF_RC5(x) (((x) >> BIT_SHIFT_DARF_RC5) & BIT_MASK_DARF_RC5)
+#define BIT_SET_DARF_RC5(x, v) (BIT_CLEAR_DARF_RC5(x) | BIT_DARF_RC5(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_HEAD_PKT_Q4_V1 0
-#define BIT_MASK_HEAD_PKT_Q4_V1 0x7ff
-#define BIT_HEAD_PKT_Q4_V1(x) (((x) & BIT_MASK_HEAD_PKT_Q4_V1) << BIT_SHIFT_HEAD_PKT_Q4_V1)
-#define BIT_GET_HEAD_PKT_Q4_V1(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1) & BIT_MASK_HEAD_PKT_Q4_V1)
+/* 2 REG_DARFRC (Offset 0x0430) */
+#define BIT_SHIFT_DARF_RC4 24
+#define BIT_MASK_DARF_RC4 0x1f
+#define BIT_DARF_RC4(x) (((x) & BIT_MASK_DARF_RC4) << BIT_SHIFT_DARF_RC4)
+#define BITS_DARF_RC4 (BIT_MASK_DARF_RC4 << BIT_SHIFT_DARF_RC4)
+#define BIT_CLEAR_DARF_RC4(x) ((x) & (~BITS_DARF_RC4))
+#define BIT_GET_DARF_RC4(x) (((x) >> BIT_SHIFT_DARF_RC4) & BIT_MASK_DARF_RC4)
+#define BIT_SET_DARF_RC4(x, v) (BIT_CLEAR_DARF_RC4(x) | BIT_DARF_RC4(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-
-/* 2 REG_Q5_INFO (Offset 0x046C) */
+/* 2 REG_DARFRC (Offset 0x0430) */
+#define BIT_SHIFT_DARF_RC4_V1 24
+#define BIT_MASK_DARF_RC4_V1 0x3f
+#define BIT_DARF_RC4_V1(x) \
+ (((x) & BIT_MASK_DARF_RC4_V1) << BIT_SHIFT_DARF_RC4_V1)
+#define BITS_DARF_RC4_V1 (BIT_MASK_DARF_RC4_V1 << BIT_SHIFT_DARF_RC4_V1)
+#define BIT_CLEAR_DARF_RC4_V1(x) ((x) & (~BITS_DARF_RC4_V1))
+#define BIT_GET_DARF_RC4_V1(x) \
+ (((x) >> BIT_SHIFT_DARF_RC4_V1) & BIT_MASK_DARF_RC4_V1)
+#define BIT_SET_DARF_RC4_V1(x, v) \
+ (BIT_CLEAR_DARF_RC4_V1(x) | BIT_DARF_RC4_V1(v))
-#define BIT_SHIFT_QUEUEMACID_Q5_V1 25
-#define BIT_MASK_QUEUEMACID_Q5_V1 0x7f
-#define BIT_QUEUEMACID_Q5_V1(x) (((x) & BIT_MASK_QUEUEMACID_Q5_V1) << BIT_SHIFT_QUEUEMACID_Q5_V1)
-#define BIT_GET_QUEUEMACID_Q5_V1(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1) & BIT_MASK_QUEUEMACID_Q5_V1)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_QUEUEAC_Q5_V1 23
-#define BIT_MASK_QUEUEAC_Q5_V1 0x3
-#define BIT_QUEUEAC_Q5_V1(x) (((x) & BIT_MASK_QUEUEAC_Q5_V1) << BIT_SHIFT_QUEUEAC_Q5_V1)
-#define BIT_GET_QUEUEAC_Q5_V1(x) (((x) >> BIT_SHIFT_QUEUEAC_Q5_V1) & BIT_MASK_QUEUEAC_Q5_V1)
+/* 2 REG_DARFRC (Offset 0x0430) */
+#define BIT_SHIFT_DARF_RC3 16
+#define BIT_MASK_DARF_RC3 0x1f
+#define BIT_DARF_RC3(x) (((x) & BIT_MASK_DARF_RC3) << BIT_SHIFT_DARF_RC3)
+#define BITS_DARF_RC3 (BIT_MASK_DARF_RC3 << BIT_SHIFT_DARF_RC3)
+#define BIT_CLEAR_DARF_RC3(x) ((x) & (~BITS_DARF_RC3))
+#define BIT_GET_DARF_RC3(x) (((x) >> BIT_SHIFT_DARF_RC3) & BIT_MASK_DARF_RC3)
+#define BIT_SET_DARF_RC3(x, v) (BIT_CLEAR_DARF_RC3(x) | BIT_DARF_RC3(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_Q5_INFO (Offset 0x046C) */
+/* 2 REG_DARFRC (Offset 0x0430) */
-#define BIT_TIDEMPTY_Q5_V1 BIT(22)
+#define BIT_SHIFT_DARF_RC3_V1 16
+#define BIT_MASK_DARF_RC3_V1 0x3f
+#define BIT_DARF_RC3_V1(x) \
+ (((x) & BIT_MASK_DARF_RC3_V1) << BIT_SHIFT_DARF_RC3_V1)
+#define BITS_DARF_RC3_V1 (BIT_MASK_DARF_RC3_V1 << BIT_SHIFT_DARF_RC3_V1)
+#define BIT_CLEAR_DARF_RC3_V1(x) ((x) & (~BITS_DARF_RC3_V1))
+#define BIT_GET_DARF_RC3_V1(x) \
+ (((x) >> BIT_SHIFT_DARF_RC3_V1) & BIT_MASK_DARF_RC3_V1)
+#define BIT_SET_DARF_RC3_V1(x, v) \
+ (BIT_CLEAR_DARF_RC3_V1(x) | BIT_DARF_RC3_V1(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_DARFRC (Offset 0x0430) */
+#define BIT_SHIFT_DARF_RC2 8
+#define BIT_MASK_DARF_RC2 0x1f
+#define BIT_DARF_RC2(x) (((x) & BIT_MASK_DARF_RC2) << BIT_SHIFT_DARF_RC2)
+#define BITS_DARF_RC2 (BIT_MASK_DARF_RC2 << BIT_SHIFT_DARF_RC2)
+#define BIT_CLEAR_DARF_RC2(x) ((x) & (~BITS_DARF_RC2))
+#define BIT_GET_DARF_RC2(x) (((x) >> BIT_SHIFT_DARF_RC2) & BIT_MASK_DARF_RC2)
+#define BIT_SET_DARF_RC2(x, v) (BIT_CLEAR_DARF_RC2(x) | BIT_DARF_RC2(v))
-/* 2 REG_Q5_INFO (Offset 0x046C) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_TAIL_PKT_Q5_V1 15
-#define BIT_MASK_TAIL_PKT_Q5_V1 0xff
-#define BIT_TAIL_PKT_Q5_V1(x) (((x) & BIT_MASK_TAIL_PKT_Q5_V1) << BIT_SHIFT_TAIL_PKT_Q5_V1)
-#define BIT_GET_TAIL_PKT_Q5_V1(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V1) & BIT_MASK_TAIL_PKT_Q5_V1)
+/* 2 REG_DARFRC (Offset 0x0430) */
+#define BIT_SHIFT_DARF_RC2_V1 8
+#define BIT_MASK_DARF_RC2_V1 0x3f
+#define BIT_DARF_RC2_V1(x) \
+ (((x) & BIT_MASK_DARF_RC2_V1) << BIT_SHIFT_DARF_RC2_V1)
+#define BITS_DARF_RC2_V1 (BIT_MASK_DARF_RC2_V1 << BIT_SHIFT_DARF_RC2_V1)
+#define BIT_CLEAR_DARF_RC2_V1(x) ((x) & (~BITS_DARF_RC2_V1))
+#define BIT_GET_DARF_RC2_V1(x) \
+ (((x) >> BIT_SHIFT_DARF_RC2_V1) & BIT_MASK_DARF_RC2_V1)
+#define BIT_SET_DARF_RC2_V1(x, v) \
+ (BIT_CLEAR_DARF_RC2_V1(x) | BIT_DARF_RC2_V1(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_DARFRC (Offset 0x0430) */
+#define BIT_SHIFT_DARF_RC1 0
+#define BIT_MASK_DARF_RC1 0x1f
+#define BIT_DARF_RC1(x) (((x) & BIT_MASK_DARF_RC1) << BIT_SHIFT_DARF_RC1)
+#define BITS_DARF_RC1 (BIT_MASK_DARF_RC1 << BIT_SHIFT_DARF_RC1)
+#define BIT_CLEAR_DARF_RC1(x) ((x) & (~BITS_DARF_RC1))
+#define BIT_GET_DARF_RC1(x) (((x) >> BIT_SHIFT_DARF_RC1) & BIT_MASK_DARF_RC1)
+#define BIT_SET_DARF_RC1(x, v) (BIT_CLEAR_DARF_RC1(x) | BIT_DARF_RC1(v))
-/* 2 REG_Q5_INFO (Offset 0x046C) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_TAIL_PKT_Q5_V2 11
-#define BIT_MASK_TAIL_PKT_Q5_V2 0x7ff
-#define BIT_TAIL_PKT_Q5_V2(x) (((x) & BIT_MASK_TAIL_PKT_Q5_V2) << BIT_SHIFT_TAIL_PKT_Q5_V2)
-#define BIT_GET_TAIL_PKT_Q5_V2(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2) & BIT_MASK_TAIL_PKT_Q5_V2)
+/* 2 REG_DARFRC (Offset 0x0430) */
+#define BIT_SHIFT_DARF_RC1_V1 0
+#define BIT_MASK_DARF_RC1_V1 0x3f
+#define BIT_DARF_RC1_V1(x) \
+ (((x) & BIT_MASK_DARF_RC1_V1) << BIT_SHIFT_DARF_RC1_V1)
+#define BITS_DARF_RC1_V1 (BIT_MASK_DARF_RC1_V1 << BIT_SHIFT_DARF_RC1_V1)
+#define BIT_CLEAR_DARF_RC1_V1(x) ((x) & (~BITS_DARF_RC1_V1))
+#define BIT_GET_DARF_RC1_V1(x) \
+ (((x) >> BIT_SHIFT_DARF_RC1_V1) & BIT_MASK_DARF_RC1_V1)
+#define BIT_SET_DARF_RC1_V1(x, v) \
+ (BIT_CLEAR_DARF_RC1_V1(x) | BIT_DARF_RC1_V1(v))
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DARFRCH (Offset 0x0434) */
+
+#define BIT_SHIFT_DARF_RC8_V1 24
+#define BIT_MASK_DARF_RC8_V1 0x1f
+#define BIT_DARF_RC8_V1(x) \
+ (((x) & BIT_MASK_DARF_RC8_V1) << BIT_SHIFT_DARF_RC8_V1)
+#define BITS_DARF_RC8_V1 (BIT_MASK_DARF_RC8_V1 << BIT_SHIFT_DARF_RC8_V1)
+#define BIT_CLEAR_DARF_RC8_V1(x) ((x) & (~BITS_DARF_RC8_V1))
+#define BIT_GET_DARF_RC8_V1(x) \
+ (((x) >> BIT_SHIFT_DARF_RC8_V1) & BIT_MASK_DARF_RC8_V1)
+#define BIT_SET_DARF_RC8_V1(x, v) \
+ (BIT_CLEAR_DARF_RC8_V1(x) | BIT_DARF_RC8_V1(v))
+
+#define BIT_SHIFT_DARF_RC7_V1 16
+#define BIT_MASK_DARF_RC7_V1 0x1f
+#define BIT_DARF_RC7_V1(x) \
+ (((x) & BIT_MASK_DARF_RC7_V1) << BIT_SHIFT_DARF_RC7_V1)
+#define BITS_DARF_RC7_V1 (BIT_MASK_DARF_RC7_V1 << BIT_SHIFT_DARF_RC7_V1)
+#define BIT_CLEAR_DARF_RC7_V1(x) ((x) & (~BITS_DARF_RC7_V1))
+#define BIT_GET_DARF_RC7_V1(x) \
+ (((x) >> BIT_SHIFT_DARF_RC7_V1) & BIT_MASK_DARF_RC7_V1)
+#define BIT_SET_DARF_RC7_V1(x, v) \
+ (BIT_CLEAR_DARF_RC7_V1(x) | BIT_DARF_RC7_V1(v))
+
+#define BIT_SHIFT_DARF_RC6_V1 8
+#define BIT_MASK_DARF_RC6_V1 0x1f
+#define BIT_DARF_RC6_V1(x) \
+ (((x) & BIT_MASK_DARF_RC6_V1) << BIT_SHIFT_DARF_RC6_V1)
+#define BITS_DARF_RC6_V1 (BIT_MASK_DARF_RC6_V1 << BIT_SHIFT_DARF_RC6_V1)
+#define BIT_CLEAR_DARF_RC6_V1(x) ((x) & (~BITS_DARF_RC6_V1))
+#define BIT_GET_DARF_RC6_V1(x) \
+ (((x) >> BIT_SHIFT_DARF_RC6_V1) & BIT_MASK_DARF_RC6_V1)
+#define BIT_SET_DARF_RC6_V1(x, v) \
+ (BIT_CLEAR_DARF_RC6_V1(x) | BIT_DARF_RC6_V1(v))
+
+#define BIT_SHIFT_DARF_RC5_V1 0
+#define BIT_MASK_DARF_RC5_V1 0x1f
+#define BIT_DARF_RC5_V1(x) \
+ (((x) & BIT_MASK_DARF_RC5_V1) << BIT_SHIFT_DARF_RC5_V1)
+#define BITS_DARF_RC5_V1 (BIT_MASK_DARF_RC5_V1 << BIT_SHIFT_DARF_RC5_V1)
+#define BIT_CLEAR_DARF_RC5_V1(x) ((x) & (~BITS_DARF_RC5_V1))
+#define BIT_GET_DARF_RC5_V1(x) \
+ (((x) >> BIT_SHIFT_DARF_RC5_V1) & BIT_MASK_DARF_RC5_V1)
+#define BIT_SET_DARF_RC5_V1(x, v) \
+ (BIT_CLEAR_DARF_RC5_V1(x) | BIT_DARF_RC5_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_RARFRC (Offset 0x0438) */
+#define BIT_SHIFT_RARF_RC8 (56 & CPU_OPT_WIDTH)
+#define BIT_MASK_RARF_RC8 0x1f
+#define BIT_RARF_RC8(x) (((x) & BIT_MASK_RARF_RC8) << BIT_SHIFT_RARF_RC8)
+#define BITS_RARF_RC8 (BIT_MASK_RARF_RC8 << BIT_SHIFT_RARF_RC8)
+#define BIT_CLEAR_RARF_RC8(x) ((x) & (~BITS_RARF_RC8))
+#define BIT_GET_RARF_RC8(x) (((x) >> BIT_SHIFT_RARF_RC8) & BIT_MASK_RARF_RC8)
+#define BIT_SET_RARF_RC8(x, v) (BIT_CLEAR_RARF_RC8(x) | BIT_RARF_RC8(v))
+
+#define BIT_SHIFT_RARF_RC7 (48 & CPU_OPT_WIDTH)
+#define BIT_MASK_RARF_RC7 0x1f
+#define BIT_RARF_RC7(x) (((x) & BIT_MASK_RARF_RC7) << BIT_SHIFT_RARF_RC7)
+#define BITS_RARF_RC7 (BIT_MASK_RARF_RC7 << BIT_SHIFT_RARF_RC7)
+#define BIT_CLEAR_RARF_RC7(x) ((x) & (~BITS_RARF_RC7))
+#define BIT_GET_RARF_RC7(x) (((x) >> BIT_SHIFT_RARF_RC7) & BIT_MASK_RARF_RC7)
+#define BIT_SET_RARF_RC7(x, v) (BIT_CLEAR_RARF_RC7(x) | BIT_RARF_RC7(v))
+
+#define BIT_SHIFT_RARF_RC6 (40 & CPU_OPT_WIDTH)
+#define BIT_MASK_RARF_RC6 0x1f
+#define BIT_RARF_RC6(x) (((x) & BIT_MASK_RARF_RC6) << BIT_SHIFT_RARF_RC6)
+#define BITS_RARF_RC6 (BIT_MASK_RARF_RC6 << BIT_SHIFT_RARF_RC6)
+#define BIT_CLEAR_RARF_RC6(x) ((x) & (~BITS_RARF_RC6))
+#define BIT_GET_RARF_RC6(x) (((x) >> BIT_SHIFT_RARF_RC6) & BIT_MASK_RARF_RC6)
+#define BIT_SET_RARF_RC6(x, v) (BIT_CLEAR_RARF_RC6(x) | BIT_RARF_RC6(v))
+
+#define BIT_SHIFT_RARF_RC5 (32 & CPU_OPT_WIDTH)
+#define BIT_MASK_RARF_RC5 0x1f
+#define BIT_RARF_RC5(x) (((x) & BIT_MASK_RARF_RC5) << BIT_SHIFT_RARF_RC5)
+#define BITS_RARF_RC5 (BIT_MASK_RARF_RC5 << BIT_SHIFT_RARF_RC5)
+#define BIT_CLEAR_RARF_RC5(x) ((x) & (~BITS_RARF_RC5))
+#define BIT_GET_RARF_RC5(x) (((x) >> BIT_SHIFT_RARF_RC5) & BIT_MASK_RARF_RC5)
+#define BIT_SET_RARF_RC5(x, v) (BIT_CLEAR_RARF_RC5(x) | BIT_RARF_RC5(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_RARFRC (Offset 0x0438) */
+#define BIT_SHIFT_RARF_RC4 24
+#define BIT_MASK_RARF_RC4 0x1f
+#define BIT_RARF_RC4(x) (((x) & BIT_MASK_RARF_RC4) << BIT_SHIFT_RARF_RC4)
+#define BITS_RARF_RC4 (BIT_MASK_RARF_RC4 << BIT_SHIFT_RARF_RC4)
+#define BIT_CLEAR_RARF_RC4(x) ((x) & (~BITS_RARF_RC4))
+#define BIT_GET_RARF_RC4(x) (((x) >> BIT_SHIFT_RARF_RC4) & BIT_MASK_RARF_RC4)
+#define BIT_SET_RARF_RC4(x, v) (BIT_CLEAR_RARF_RC4(x) | BIT_RARF_RC4(v))
+
+#define BIT_SHIFT_RARF_RC3 16
+#define BIT_MASK_RARF_RC3 0x1f
+#define BIT_RARF_RC3(x) (((x) & BIT_MASK_RARF_RC3) << BIT_SHIFT_RARF_RC3)
+#define BITS_RARF_RC3 (BIT_MASK_RARF_RC3 << BIT_SHIFT_RARF_RC3)
+#define BIT_CLEAR_RARF_RC3(x) ((x) & (~BITS_RARF_RC3))
+#define BIT_GET_RARF_RC3(x) (((x) >> BIT_SHIFT_RARF_RC3) & BIT_MASK_RARF_RC3)
+#define BIT_SET_RARF_RC3(x, v) (BIT_CLEAR_RARF_RC3(x) | BIT_RARF_RC3(v))
+
+#define BIT_SHIFT_RARF_RC2 8
+#define BIT_MASK_RARF_RC2 0x1f
+#define BIT_RARF_RC2(x) (((x) & BIT_MASK_RARF_RC2) << BIT_SHIFT_RARF_RC2)
+#define BITS_RARF_RC2 (BIT_MASK_RARF_RC2 << BIT_SHIFT_RARF_RC2)
+#define BIT_CLEAR_RARF_RC2(x) ((x) & (~BITS_RARF_RC2))
+#define BIT_GET_RARF_RC2(x) (((x) >> BIT_SHIFT_RARF_RC2) & BIT_MASK_RARF_RC2)
+#define BIT_SET_RARF_RC2(x, v) (BIT_CLEAR_RARF_RC2(x) | BIT_RARF_RC2(v))
+
+#define BIT_SHIFT_RARF_RC1 0
+#define BIT_MASK_RARF_RC1 0x1f
+#define BIT_RARF_RC1(x) (((x) & BIT_MASK_RARF_RC1) << BIT_SHIFT_RARF_RC1)
+#define BITS_RARF_RC1 (BIT_MASK_RARF_RC1 << BIT_SHIFT_RARF_RC1)
+#define BIT_CLEAR_RARF_RC1(x) ((x) & (~BITS_RARF_RC1))
+#define BIT_GET_RARF_RC1(x) (((x) >> BIT_SHIFT_RARF_RC1) & BIT_MASK_RARF_RC1)
+#define BIT_SET_RARF_RC1(x, v) (BIT_CLEAR_RARF_RC1(x) | BIT_RARF_RC1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RARFRCH (Offset 0x043C) */
+
+#define BIT_SHIFT_RARF_RC8_V1 24
+#define BIT_MASK_RARF_RC8_V1 0x1f
+#define BIT_RARF_RC8_V1(x) \
+ (((x) & BIT_MASK_RARF_RC8_V1) << BIT_SHIFT_RARF_RC8_V1)
+#define BITS_RARF_RC8_V1 (BIT_MASK_RARF_RC8_V1 << BIT_SHIFT_RARF_RC8_V1)
+#define BIT_CLEAR_RARF_RC8_V1(x) ((x) & (~BITS_RARF_RC8_V1))
+#define BIT_GET_RARF_RC8_V1(x) \
+ (((x) >> BIT_SHIFT_RARF_RC8_V1) & BIT_MASK_RARF_RC8_V1)
+#define BIT_SET_RARF_RC8_V1(x, v) \
+ (BIT_CLEAR_RARF_RC8_V1(x) | BIT_RARF_RC8_V1(v))
+
+#define BIT_SHIFT_RARF_RC7_V1 16
+#define BIT_MASK_RARF_RC7_V1 0x1f
+#define BIT_RARF_RC7_V1(x) \
+ (((x) & BIT_MASK_RARF_RC7_V1) << BIT_SHIFT_RARF_RC7_V1)
+#define BITS_RARF_RC7_V1 (BIT_MASK_RARF_RC7_V1 << BIT_SHIFT_RARF_RC7_V1)
+#define BIT_CLEAR_RARF_RC7_V1(x) ((x) & (~BITS_RARF_RC7_V1))
+#define BIT_GET_RARF_RC7_V1(x) \
+ (((x) >> BIT_SHIFT_RARF_RC7_V1) & BIT_MASK_RARF_RC7_V1)
+#define BIT_SET_RARF_RC7_V1(x, v) \
+ (BIT_CLEAR_RARF_RC7_V1(x) | BIT_RARF_RC7_V1(v))
+
+#define BIT_SHIFT_RARF_RC6_V1 8
+#define BIT_MASK_RARF_RC6_V1 0x1f
+#define BIT_RARF_RC6_V1(x) \
+ (((x) & BIT_MASK_RARF_RC6_V1) << BIT_SHIFT_RARF_RC6_V1)
+#define BITS_RARF_RC6_V1 (BIT_MASK_RARF_RC6_V1 << BIT_SHIFT_RARF_RC6_V1)
+#define BIT_CLEAR_RARF_RC6_V1(x) ((x) & (~BITS_RARF_RC6_V1))
+#define BIT_GET_RARF_RC6_V1(x) \
+ (((x) >> BIT_SHIFT_RARF_RC6_V1) & BIT_MASK_RARF_RC6_V1)
+#define BIT_SET_RARF_RC6_V1(x, v) \
+ (BIT_CLEAR_RARF_RC6_V1(x) | BIT_RARF_RC6_V1(v))
+
+#define BIT_SHIFT_RARF_RC5_V1 0
+#define BIT_MASK_RARF_RC5_V1 0x1f
+#define BIT_RARF_RC5_V1(x) \
+ (((x) & BIT_MASK_RARF_RC5_V1) << BIT_SHIFT_RARF_RC5_V1)
+#define BITS_RARF_RC5_V1 (BIT_MASK_RARF_RC5_V1 << BIT_SHIFT_RARF_RC5_V1)
+#define BIT_CLEAR_RARF_RC5_V1(x) ((x) & (~BITS_RARF_RC5_V1))
+#define BIT_GET_RARF_RC5_V1(x) \
+ (((x) >> BIT_SHIFT_RARF_RC5_V1) & BIT_MASK_RARF_RC5_V1)
+#define BIT_SET_RARF_RC5_V1(x, v) \
+ (BIT_CLEAR_RARF_RC5_V1(x) | BIT_RARF_RC5_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-/* 2 REG_Q5_INFO (Offset 0x046C) */
+/* 2 REG_RRSR (Offset 0x0440) */
+#define BIT_EN_VHTBW_FALL BIT(31)
+#define BIT_EN_HTBW_FALL BIT(30)
-#define BIT_SHIFT_PKT_NUM_Q5_V1 8
-#define BIT_MASK_PKT_NUM_Q5_V1 0x7f
-#define BIT_PKT_NUM_Q5_V1(x) (((x) & BIT_MASK_PKT_NUM_Q5_V1) << BIT_SHIFT_PKT_NUM_Q5_V1)
-#define BIT_GET_PKT_NUM_Q5_V1(x) (((x) >> BIT_SHIFT_PKT_NUM_Q5_V1) & BIT_MASK_PKT_NUM_Q5_V1)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_HEAD_PKT_Q5 0
-#define BIT_MASK_HEAD_PKT_Q5 0xff
-#define BIT_HEAD_PKT_Q5(x) (((x) & BIT_MASK_HEAD_PKT_Q5) << BIT_SHIFT_HEAD_PKT_Q5)
-#define BIT_GET_HEAD_PKT_Q5(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q5) & BIT_MASK_HEAD_PKT_Q5)
+/* 2 REG_RRSR (Offset 0x0440) */
+#define BIT_SHIFT_RRSR_RSC 21
+#define BIT_MASK_RRSR_RSC 0x3
+#define BIT_RRSR_RSC(x) (((x) & BIT_MASK_RRSR_RSC) << BIT_SHIFT_RRSR_RSC)
+#define BITS_RRSR_RSC (BIT_MASK_RRSR_RSC << BIT_SHIFT_RRSR_RSC)
+#define BIT_CLEAR_RRSR_RSC(x) ((x) & (~BITS_RRSR_RSC))
+#define BIT_GET_RRSR_RSC(x) (((x) >> BIT_SHIFT_RRSR_RSC) & BIT_MASK_RRSR_RSC)
+#define BIT_SET_RRSR_RSC(x, v) (BIT_CLEAR_RRSR_RSC(x) | BIT_RRSR_RSC(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_RRSR (Offset 0x0440) */
+#define BIT_RRSR_BW BIT(20)
-/* 2 REG_Q5_INFO (Offset 0x046C) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_HEAD_PKT_Q5_V1 0
-#define BIT_MASK_HEAD_PKT_Q5_V1 0x7ff
-#define BIT_HEAD_PKT_Q5_V1(x) (((x) & BIT_MASK_HEAD_PKT_Q5_V1) << BIT_SHIFT_HEAD_PKT_Q5_V1)
-#define BIT_GET_HEAD_PKT_Q5_V1(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1) & BIT_MASK_HEAD_PKT_Q5_V1)
+/* 2 REG_RRSR (Offset 0x0440) */
+#define BIT_SHIFT_RRSC_BITMAP 0
+#define BIT_MASK_RRSC_BITMAP 0xfffff
+#define BIT_RRSC_BITMAP(x) \
+ (((x) & BIT_MASK_RRSC_BITMAP) << BIT_SHIFT_RRSC_BITMAP)
+#define BITS_RRSC_BITMAP (BIT_MASK_RRSC_BITMAP << BIT_SHIFT_RRSC_BITMAP)
+#define BIT_CLEAR_RRSC_BITMAP(x) ((x) & (~BITS_RRSC_BITMAP))
+#define BIT_GET_RRSC_BITMAP(x) \
+ (((x) >> BIT_SHIFT_RRSC_BITMAP) & BIT_MASK_RRSC_BITMAP)
+#define BIT_SET_RRSC_BITMAP(x, v) \
+ (BIT_CLEAR_RRSC_BITMAP(x) | BIT_RRSC_BITMAP(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_ARFR0 (Offset 0x0444) */
+#define BIT_SHIFT_ARFR0_V1 0
+#define BIT_MASK_ARFR0_V1 0xffffffffffffffffL
+#define BIT_ARFR0_V1(x) (((x) & BIT_MASK_ARFR0_V1) << BIT_SHIFT_ARFR0_V1)
+#define BITS_ARFR0_V1 (BIT_MASK_ARFR0_V1 << BIT_SHIFT_ARFR0_V1)
+#define BIT_CLEAR_ARFR0_V1(x) ((x) & (~BITS_ARFR0_V1))
+#define BIT_GET_ARFR0_V1(x) (((x) >> BIT_SHIFT_ARFR0_V1) & BIT_MASK_ARFR0_V1)
+#define BIT_SET_ARFR0_V1(x, v) (BIT_CLEAR_ARFR0_V1(x) | BIT_ARFR0_V1(v))
-/* 2 REG_Q6_INFO (Offset 0x0470) */
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_QUEUEMACID_Q6_V1 25
-#define BIT_MASK_QUEUEMACID_Q6_V1 0x7f
-#define BIT_QUEUEMACID_Q6_V1(x) (((x) & BIT_MASK_QUEUEMACID_Q6_V1) << BIT_SHIFT_QUEUEMACID_Q6_V1)
-#define BIT_GET_QUEUEMACID_Q6_V1(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1) & BIT_MASK_QUEUEMACID_Q6_V1)
+/* 2 REG_ARFR0 (Offset 0x0444) */
+#define BIT_SHIFT_ARFRL0 0
+#define BIT_MASK_ARFRL0 0xffffffffL
+#define BIT_ARFRL0(x) (((x) & BIT_MASK_ARFRL0) << BIT_SHIFT_ARFRL0)
+#define BITS_ARFRL0 (BIT_MASK_ARFRL0 << BIT_SHIFT_ARFRL0)
+#define BIT_CLEAR_ARFRL0(x) ((x) & (~BITS_ARFRL0))
+#define BIT_GET_ARFRL0(x) (((x) >> BIT_SHIFT_ARFRL0) & BIT_MASK_ARFRL0)
+#define BIT_SET_ARFRL0(x, v) (BIT_CLEAR_ARFRL0(x) | BIT_ARFRL0(v))
+
+/* 2 REG_ARFRH0 (Offset 0x0448) */
+
+#define BIT_SHIFT_ARFRH0 0
+#define BIT_MASK_ARFRH0 0xffffffffL
+#define BIT_ARFRH0(x) (((x) & BIT_MASK_ARFRH0) << BIT_SHIFT_ARFRH0)
+#define BITS_ARFRH0 (BIT_MASK_ARFRH0 << BIT_SHIFT_ARFRH0)
+#define BIT_CLEAR_ARFRH0(x) ((x) & (~BITS_ARFRH0))
+#define BIT_GET_ARFRH0(x) (((x) >> BIT_SHIFT_ARFRH0) & BIT_MASK_ARFRH0)
+#define BIT_SET_ARFRH0(x, v) (BIT_CLEAR_ARFRH0(x) | BIT_ARFRH0(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_REG_ARFR_WT0 (Offset 0x044C) */
+
+#define BIT_SHIFT_RATE7_WEIGHTING 28
+#define BIT_MASK_RATE7_WEIGHTING 0xf
+#define BIT_RATE7_WEIGHTING(x) \
+ (((x) & BIT_MASK_RATE7_WEIGHTING) << BIT_SHIFT_RATE7_WEIGHTING)
+#define BITS_RATE7_WEIGHTING \
+ (BIT_MASK_RATE7_WEIGHTING << BIT_SHIFT_RATE7_WEIGHTING)
+#define BIT_CLEAR_RATE7_WEIGHTING(x) ((x) & (~BITS_RATE7_WEIGHTING))
+#define BIT_GET_RATE7_WEIGHTING(x) \
+ (((x) >> BIT_SHIFT_RATE7_WEIGHTING) & BIT_MASK_RATE7_WEIGHTING)
+#define BIT_SET_RATE7_WEIGHTING(x, v) \
+ (BIT_CLEAR_RATE7_WEIGHTING(x) | BIT_RATE7_WEIGHTING(v))
+
+#define BIT_SHIFT_RATE6_WEIGHTING 24
+#define BIT_MASK_RATE6_WEIGHTING 0xf
+#define BIT_RATE6_WEIGHTING(x) \
+ (((x) & BIT_MASK_RATE6_WEIGHTING) << BIT_SHIFT_RATE6_WEIGHTING)
+#define BITS_RATE6_WEIGHTING \
+ (BIT_MASK_RATE6_WEIGHTING << BIT_SHIFT_RATE6_WEIGHTING)
+#define BIT_CLEAR_RATE6_WEIGHTING(x) ((x) & (~BITS_RATE6_WEIGHTING))
+#define BIT_GET_RATE6_WEIGHTING(x) \
+ (((x) >> BIT_SHIFT_RATE6_WEIGHTING) & BIT_MASK_RATE6_WEIGHTING)
+#define BIT_SET_RATE6_WEIGHTING(x, v) \
+ (BIT_CLEAR_RATE6_WEIGHTING(x) | BIT_RATE6_WEIGHTING(v))
+
+#define BIT_SHIFT_RATE5_WEIGHTING 20
+#define BIT_MASK_RATE5_WEIGHTING 0xf
+#define BIT_RATE5_WEIGHTING(x) \
+ (((x) & BIT_MASK_RATE5_WEIGHTING) << BIT_SHIFT_RATE5_WEIGHTING)
+#define BITS_RATE5_WEIGHTING \
+ (BIT_MASK_RATE5_WEIGHTING << BIT_SHIFT_RATE5_WEIGHTING)
+#define BIT_CLEAR_RATE5_WEIGHTING(x) ((x) & (~BITS_RATE5_WEIGHTING))
+#define BIT_GET_RATE5_WEIGHTING(x) \
+ (((x) >> BIT_SHIFT_RATE5_WEIGHTING) & BIT_MASK_RATE5_WEIGHTING)
+#define BIT_SET_RATE5_WEIGHTING(x, v) \
+ (BIT_CLEAR_RATE5_WEIGHTING(x) | BIT_RATE5_WEIGHTING(v))
+
+#define BIT_SHIFT_RATE4_WEIGHTING 16
+#define BIT_MASK_RATE4_WEIGHTING 0xf
+#define BIT_RATE4_WEIGHTING(x) \
+ (((x) & BIT_MASK_RATE4_WEIGHTING) << BIT_SHIFT_RATE4_WEIGHTING)
+#define BITS_RATE4_WEIGHTING \
+ (BIT_MASK_RATE4_WEIGHTING << BIT_SHIFT_RATE4_WEIGHTING)
+#define BIT_CLEAR_RATE4_WEIGHTING(x) ((x) & (~BITS_RATE4_WEIGHTING))
+#define BIT_GET_RATE4_WEIGHTING(x) \
+ (((x) >> BIT_SHIFT_RATE4_WEIGHTING) & BIT_MASK_RATE4_WEIGHTING)
+#define BIT_SET_RATE4_WEIGHTING(x, v) \
+ (BIT_CLEAR_RATE4_WEIGHTING(x) | BIT_RATE4_WEIGHTING(v))
+
+#define BIT_SHIFT_RATE3_WEIGHTING 12
+#define BIT_MASK_RATE3_WEIGHTING 0xf
+#define BIT_RATE3_WEIGHTING(x) \
+ (((x) & BIT_MASK_RATE3_WEIGHTING) << BIT_SHIFT_RATE3_WEIGHTING)
+#define BITS_RATE3_WEIGHTING \
+ (BIT_MASK_RATE3_WEIGHTING << BIT_SHIFT_RATE3_WEIGHTING)
+#define BIT_CLEAR_RATE3_WEIGHTING(x) ((x) & (~BITS_RATE3_WEIGHTING))
+#define BIT_GET_RATE3_WEIGHTING(x) \
+ (((x) >> BIT_SHIFT_RATE3_WEIGHTING) & BIT_MASK_RATE3_WEIGHTING)
+#define BIT_SET_RATE3_WEIGHTING(x, v) \
+ (BIT_CLEAR_RATE3_WEIGHTING(x) | BIT_RATE3_WEIGHTING(v))
+
+#define BIT_SHIFT_RATE2_WEIGHTING 8
+#define BIT_MASK_RATE2_WEIGHTING 0xf
+#define BIT_RATE2_WEIGHTING(x) \
+ (((x) & BIT_MASK_RATE2_WEIGHTING) << BIT_SHIFT_RATE2_WEIGHTING)
+#define BITS_RATE2_WEIGHTING \
+ (BIT_MASK_RATE2_WEIGHTING << BIT_SHIFT_RATE2_WEIGHTING)
+#define BIT_CLEAR_RATE2_WEIGHTING(x) ((x) & (~BITS_RATE2_WEIGHTING))
+#define BIT_GET_RATE2_WEIGHTING(x) \
+ (((x) >> BIT_SHIFT_RATE2_WEIGHTING) & BIT_MASK_RATE2_WEIGHTING)
+#define BIT_SET_RATE2_WEIGHTING(x, v) \
+ (BIT_CLEAR_RATE2_WEIGHTING(x) | BIT_RATE2_WEIGHTING(v))
+
+#define BIT_SHIFT_RATE1_WEIGHTING 4
+#define BIT_MASK_RATE1_WEIGHTING 0xf
+#define BIT_RATE1_WEIGHTING(x) \
+ (((x) & BIT_MASK_RATE1_WEIGHTING) << BIT_SHIFT_RATE1_WEIGHTING)
+#define BITS_RATE1_WEIGHTING \
+ (BIT_MASK_RATE1_WEIGHTING << BIT_SHIFT_RATE1_WEIGHTING)
+#define BIT_CLEAR_RATE1_WEIGHTING(x) ((x) & (~BITS_RATE1_WEIGHTING))
+#define BIT_GET_RATE1_WEIGHTING(x) \
+ (((x) >> BIT_SHIFT_RATE1_WEIGHTING) & BIT_MASK_RATE1_WEIGHTING)
+#define BIT_SET_RATE1_WEIGHTING(x, v) \
+ (BIT_CLEAR_RATE1_WEIGHTING(x) | BIT_RATE1_WEIGHTING(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_QUEUEAC_Q6_V1 23
-#define BIT_MASK_QUEUEAC_Q6_V1 0x3
-#define BIT_QUEUEAC_Q6_V1(x) (((x) & BIT_MASK_QUEUEAC_Q6_V1) << BIT_SHIFT_QUEUEAC_Q6_V1)
-#define BIT_GET_QUEUEAC_Q6_V1(x) (((x) >> BIT_SHIFT_QUEUEAC_Q6_V1) & BIT_MASK_QUEUEAC_Q6_V1)
+/* 2 REG_ARFR1_V1 (Offset 0x044C) */
+#define BIT_SHIFT_ARFR1_V1 0
+#define BIT_MASK_ARFR1_V1 0xffffffffffffffffL
+#define BIT_ARFR1_V1(x) (((x) & BIT_MASK_ARFR1_V1) << BIT_SHIFT_ARFR1_V1)
+#define BITS_ARFR1_V1 (BIT_MASK_ARFR1_V1 << BIT_SHIFT_ARFR1_V1)
+#define BIT_CLEAR_ARFR1_V1(x) ((x) & (~BITS_ARFR1_V1))
+#define BIT_GET_ARFR1_V1(x) (((x) >> BIT_SHIFT_ARFR1_V1) & BIT_MASK_ARFR1_V1)
+#define BIT_SET_ARFR1_V1(x, v) (BIT_CLEAR_ARFR1_V1(x) | BIT_ARFR1_V1(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+/* 2 REG_REG_ARFR_WT0 (Offset 0x044C) */
-/* 2 REG_Q6_INFO (Offset 0x0470) */
-
-#define BIT_TIDEMPTY_Q6_V1 BIT(22)
+#define BIT_SHIFT_RATE0_WEIGHTING 0
+#define BIT_MASK_RATE0_WEIGHTING 0xf
+#define BIT_RATE0_WEIGHTING(x) \
+ (((x) & BIT_MASK_RATE0_WEIGHTING) << BIT_SHIFT_RATE0_WEIGHTING)
+#define BITS_RATE0_WEIGHTING \
+ (BIT_MASK_RATE0_WEIGHTING << BIT_SHIFT_RATE0_WEIGHTING)
+#define BIT_CLEAR_RATE0_WEIGHTING(x) ((x) & (~BITS_RATE0_WEIGHTING))
+#define BIT_GET_RATE0_WEIGHTING(x) \
+ (((x) >> BIT_SHIFT_RATE0_WEIGHTING) & BIT_MASK_RATE0_WEIGHTING)
+#define BIT_SET_RATE0_WEIGHTING(x, v) \
+ (BIT_CLEAR_RATE0_WEIGHTING(x) | BIT_RATE0_WEIGHTING(v))
#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-
-/* 2 REG_Q6_INFO (Offset 0x0470) */
+/* 2 REG_ARFR1_V1 (Offset 0x044C) */
+#define BIT_SHIFT_ARFRL1 0
+#define BIT_MASK_ARFRL1 0xffffffffL
+#define BIT_ARFRL1(x) (((x) & BIT_MASK_ARFRL1) << BIT_SHIFT_ARFRL1)
+#define BITS_ARFRL1 (BIT_MASK_ARFRL1 << BIT_SHIFT_ARFRL1)
+#define BIT_CLEAR_ARFRL1(x) ((x) & (~BITS_ARFRL1))
+#define BIT_GET_ARFRL1(x) (((x) >> BIT_SHIFT_ARFRL1) & BIT_MASK_ARFRL1)
+#define BIT_SET_ARFRL1(x, v) (BIT_CLEAR_ARFRL1(x) | BIT_ARFRL1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_REG_ARFR_WT1 (Offset 0x0450) */
+
+#define BIT_SHIFT_RATE15_WEIGHTING 28
+#define BIT_MASK_RATE15_WEIGHTING 0xf
+#define BIT_RATE15_WEIGHTING(x) \
+ (((x) & BIT_MASK_RATE15_WEIGHTING) << BIT_SHIFT_RATE15_WEIGHTING)
+#define BITS_RATE15_WEIGHTING \
+ (BIT_MASK_RATE15_WEIGHTING << BIT_SHIFT_RATE15_WEIGHTING)
+#define BIT_CLEAR_RATE15_WEIGHTING(x) ((x) & (~BITS_RATE15_WEIGHTING))
+#define BIT_GET_RATE15_WEIGHTING(x) \
+ (((x) >> BIT_SHIFT_RATE15_WEIGHTING) & BIT_MASK_RATE15_WEIGHTING)
+#define BIT_SET_RATE15_WEIGHTING(x, v) \
+ (BIT_CLEAR_RATE15_WEIGHTING(x) | BIT_RATE15_WEIGHTING(v))
+
+#define BIT_SHIFT_RATE14_WEIGHTING 24
+#define BIT_MASK_RATE14_WEIGHTING 0xf
+#define BIT_RATE14_WEIGHTING(x) \
+ (((x) & BIT_MASK_RATE14_WEIGHTING) << BIT_SHIFT_RATE14_WEIGHTING)
+#define BITS_RATE14_WEIGHTING \
+ (BIT_MASK_RATE14_WEIGHTING << BIT_SHIFT_RATE14_WEIGHTING)
+#define BIT_CLEAR_RATE14_WEIGHTING(x) ((x) & (~BITS_RATE14_WEIGHTING))
+#define BIT_GET_RATE14_WEIGHTING(x) \
+ (((x) >> BIT_SHIFT_RATE14_WEIGHTING) & BIT_MASK_RATE14_WEIGHTING)
+#define BIT_SET_RATE14_WEIGHTING(x, v) \
+ (BIT_CLEAR_RATE14_WEIGHTING(x) | BIT_RATE14_WEIGHTING(v))
+
+#define BIT_SHIFT_RATE13_WEIGHTING 20
+#define BIT_MASK_RATE13_WEIGHTING 0xf
+#define BIT_RATE13_WEIGHTING(x) \
+ (((x) & BIT_MASK_RATE13_WEIGHTING) << BIT_SHIFT_RATE13_WEIGHTING)
+#define BITS_RATE13_WEIGHTING \
+ (BIT_MASK_RATE13_WEIGHTING << BIT_SHIFT_RATE13_WEIGHTING)
+#define BIT_CLEAR_RATE13_WEIGHTING(x) ((x) & (~BITS_RATE13_WEIGHTING))
+#define BIT_GET_RATE13_WEIGHTING(x) \
+ (((x) >> BIT_SHIFT_RATE13_WEIGHTING) & BIT_MASK_RATE13_WEIGHTING)
+#define BIT_SET_RATE13_WEIGHTING(x, v) \
+ (BIT_CLEAR_RATE13_WEIGHTING(x) | BIT_RATE13_WEIGHTING(v))
+
+#define BIT_SHIFT_RATE12_WEIGHTING 16
+#define BIT_MASK_RATE12_WEIGHTING 0xf
+#define BIT_RATE12_WEIGHTING(x) \
+ (((x) & BIT_MASK_RATE12_WEIGHTING) << BIT_SHIFT_RATE12_WEIGHTING)
+#define BITS_RATE12_WEIGHTING \
+ (BIT_MASK_RATE12_WEIGHTING << BIT_SHIFT_RATE12_WEIGHTING)
+#define BIT_CLEAR_RATE12_WEIGHTING(x) ((x) & (~BITS_RATE12_WEIGHTING))
+#define BIT_GET_RATE12_WEIGHTING(x) \
+ (((x) >> BIT_SHIFT_RATE12_WEIGHTING) & BIT_MASK_RATE12_WEIGHTING)
+#define BIT_SET_RATE12_WEIGHTING(x, v) \
+ (BIT_CLEAR_RATE12_WEIGHTING(x) | BIT_RATE12_WEIGHTING(v))
+
+#define BIT_SHIFT_RATE11_WEIGHTING 12
+#define BIT_MASK_RATE11_WEIGHTING 0xf
+#define BIT_RATE11_WEIGHTING(x) \
+ (((x) & BIT_MASK_RATE11_WEIGHTING) << BIT_SHIFT_RATE11_WEIGHTING)
+#define BITS_RATE11_WEIGHTING \
+ (BIT_MASK_RATE11_WEIGHTING << BIT_SHIFT_RATE11_WEIGHTING)
+#define BIT_CLEAR_RATE11_WEIGHTING(x) ((x) & (~BITS_RATE11_WEIGHTING))
+#define BIT_GET_RATE11_WEIGHTING(x) \
+ (((x) >> BIT_SHIFT_RATE11_WEIGHTING) & BIT_MASK_RATE11_WEIGHTING)
+#define BIT_SET_RATE11_WEIGHTING(x, v) \
+ (BIT_CLEAR_RATE11_WEIGHTING(x) | BIT_RATE11_WEIGHTING(v))
+
+#define BIT_SHIFT_RATE10_WEIGHTING 8
+#define BIT_MASK_RATE10_WEIGHTING 0xf
+#define BIT_RATE10_WEIGHTING(x) \
+ (((x) & BIT_MASK_RATE10_WEIGHTING) << BIT_SHIFT_RATE10_WEIGHTING)
+#define BITS_RATE10_WEIGHTING \
+ (BIT_MASK_RATE10_WEIGHTING << BIT_SHIFT_RATE10_WEIGHTING)
+#define BIT_CLEAR_RATE10_WEIGHTING(x) ((x) & (~BITS_RATE10_WEIGHTING))
+#define BIT_GET_RATE10_WEIGHTING(x) \
+ (((x) >> BIT_SHIFT_RATE10_WEIGHTING) & BIT_MASK_RATE10_WEIGHTING)
+#define BIT_SET_RATE10_WEIGHTING(x, v) \
+ (BIT_CLEAR_RATE10_WEIGHTING(x) | BIT_RATE10_WEIGHTING(v))
+
+#define BIT_SHIFT_RATE9_WEIGHTING 4
+#define BIT_MASK_RATE9_WEIGHTING 0xf
+#define BIT_RATE9_WEIGHTING(x) \
+ (((x) & BIT_MASK_RATE9_WEIGHTING) << BIT_SHIFT_RATE9_WEIGHTING)
+#define BITS_RATE9_WEIGHTING \
+ (BIT_MASK_RATE9_WEIGHTING << BIT_SHIFT_RATE9_WEIGHTING)
+#define BIT_CLEAR_RATE9_WEIGHTING(x) ((x) & (~BITS_RATE9_WEIGHTING))
+#define BIT_GET_RATE9_WEIGHTING(x) \
+ (((x) >> BIT_SHIFT_RATE9_WEIGHTING) & BIT_MASK_RATE9_WEIGHTING)
+#define BIT_SET_RATE9_WEIGHTING(x, v) \
+ (BIT_CLEAR_RATE9_WEIGHTING(x) | BIT_RATE9_WEIGHTING(v))
+
+#define BIT_SHIFT_RATE8_WEIGHTING 0
+#define BIT_MASK_RATE8_WEIGHTING 0xf
+#define BIT_RATE8_WEIGHTING(x) \
+ (((x) & BIT_MASK_RATE8_WEIGHTING) << BIT_SHIFT_RATE8_WEIGHTING)
+#define BITS_RATE8_WEIGHTING \
+ (BIT_MASK_RATE8_WEIGHTING << BIT_SHIFT_RATE8_WEIGHTING)
+#define BIT_CLEAR_RATE8_WEIGHTING(x) ((x) & (~BITS_RATE8_WEIGHTING))
+#define BIT_GET_RATE8_WEIGHTING(x) \
+ (((x) >> BIT_SHIFT_RATE8_WEIGHTING) & BIT_MASK_RATE8_WEIGHTING)
+#define BIT_SET_RATE8_WEIGHTING(x, v) \
+ (BIT_CLEAR_RATE8_WEIGHTING(x) | BIT_RATE8_WEIGHTING(v))
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ARFRH1_V1 (Offset 0x0450) */
+
+#define BIT_SHIFT_ARFRH1 0
+#define BIT_MASK_ARFRH1 0xffffffffL
+#define BIT_ARFRH1(x) (((x) & BIT_MASK_ARFRH1) << BIT_SHIFT_ARFRH1)
+#define BITS_ARFRH1 (BIT_MASK_ARFRH1 << BIT_SHIFT_ARFRH1)
+#define BIT_CLEAR_ARFRH1(x) ((x) & (~BITS_ARFRH1))
+#define BIT_GET_ARFRH1(x) (((x) >> BIT_SHIFT_ARFRH1) & BIT_MASK_ARFRH1)
+#define BIT_SET_ARFRH1(x, v) (BIT_CLEAR_ARFRH1(x) | BIT_ARFRH1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_TAIL_PKT_Q6_V1 15
-#define BIT_MASK_TAIL_PKT_Q6_V1 0xff
-#define BIT_TAIL_PKT_Q6_V1(x) (((x) & BIT_MASK_TAIL_PKT_Q6_V1) << BIT_SHIFT_TAIL_PKT_Q6_V1)
-#define BIT_GET_TAIL_PKT_Q6_V1(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V1) & BIT_MASK_TAIL_PKT_Q6_V1)
+/* 2 REG_CCK_CHECK (Offset 0x0454) */
+#define BIT_CHECK_CCK_EN BIT(7)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_CCK_CHECK (Offset 0x0454) */
+#define BIT_EN_BCN_PKT_REL BIT(6)
-/* 2 REG_Q6_INFO (Offset 0x0470) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_TAIL_PKT_Q6_V2 11
-#define BIT_MASK_TAIL_PKT_Q6_V2 0x7ff
-#define BIT_TAIL_PKT_Q6_V2(x) (((x) & BIT_MASK_TAIL_PKT_Q6_V2) << BIT_SHIFT_TAIL_PKT_Q6_V2)
-#define BIT_GET_TAIL_PKT_Q6_V2(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2) & BIT_MASK_TAIL_PKT_Q6_V2)
+/* 2 REG_CCK_CHECK (Offset 0x0454) */
+#define BIT_EN_BCN_PKT_REL_P0 BIT(6)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-
-/* 2 REG_Q6_INFO (Offset 0x0470) */
+/* 2 REG_CCK_CHECK (Offset 0x0454) */
+#define BIT_BCN_PORT_SEL BIT(5)
+#define BIT_MOREDATA_BYPASS BIT(4)
-#define BIT_SHIFT_PKT_NUM_Q6_V1 8
-#define BIT_MASK_PKT_NUM_Q6_V1 0x7f
-#define BIT_PKT_NUM_Q6_V1(x) (((x) & BIT_MASK_PKT_NUM_Q6_V1) << BIT_SHIFT_PKT_NUM_Q6_V1)
-#define BIT_GET_PKT_NUM_Q6_V1(x) (((x) >> BIT_SHIFT_PKT_NUM_Q6_V1) & BIT_MASK_PKT_NUM_Q6_V1)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_HEAD_PKT_Q6 0
-#define BIT_MASK_HEAD_PKT_Q6 0xff
-#define BIT_HEAD_PKT_Q6(x) (((x) & BIT_MASK_HEAD_PKT_Q6) << BIT_SHIFT_HEAD_PKT_Q6)
-#define BIT_GET_HEAD_PKT_Q6(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q6) & BIT_MASK_HEAD_PKT_Q6)
+/* 2 REG_CCK_CHECK (Offset 0x0454) */
+#define BIT_EN_CLR_CMD_REL_BCN_PKT BIT(3)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_CCK_CHECK (Offset 0x0454) */
+#define BIT_EN_CLR_CMD_REL_BCN_PKT_P0 BIT(3)
-/* 2 REG_Q6_INFO (Offset 0x0470) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_HEAD_PKT_Q6_V1 0
-#define BIT_MASK_HEAD_PKT_Q6_V1 0x7ff
-#define BIT_HEAD_PKT_Q6_V1(x) (((x) & BIT_MASK_HEAD_PKT_Q6_V1) << BIT_SHIFT_HEAD_PKT_Q6_V1)
-#define BIT_GET_HEAD_PKT_Q6_V1(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1) & BIT_MASK_HEAD_PKT_Q6_V1)
+/* 2 REG_CCK_CHECK (Offset 0x0454) */
+#define BIT_R_EN_SET_MOREDATA BIT(2)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-
-/* 2 REG_Q7_INFO (Offset 0x0474) */
+/* 2 REG_CCK_CHECK (Offset 0x0454) */
+#define BIT_EN_SET_MOREDATA BIT(2)
-#define BIT_SHIFT_QUEUEMACID_Q7_V1 25
-#define BIT_MASK_QUEUEMACID_Q7_V1 0x7f
-#define BIT_QUEUEMACID_Q7_V1(x) (((x) & BIT_MASK_QUEUEMACID_Q7_V1) << BIT_SHIFT_QUEUEMACID_Q7_V1)
-#define BIT_GET_QUEUEMACID_Q7_V1(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1) & BIT_MASK_QUEUEMACID_Q7_V1)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_QUEUEAC_Q7_V1 23
-#define BIT_MASK_QUEUEAC_Q7_V1 0x3
-#define BIT_QUEUEAC_Q7_V1(x) (((x) & BIT_MASK_QUEUEAC_Q7_V1) << BIT_SHIFT_QUEUEAC_Q7_V1)
-#define BIT_GET_QUEUEAC_Q7_V1(x) (((x) >> BIT_SHIFT_QUEUEAC_Q7_V1) & BIT_MASK_QUEUEAC_Q7_V1)
+/* 2 REG_CCK_CHECK (Offset 0x0454) */
+#define BIT__R_DIS_CLEAR_MACID_RELEASE BIT(1)
+#define BIT__R_MACID_RELEASE_EN BIT(0)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_Q7_INFO (Offset 0x0474) */
+/* 2 REG_AMPDU_BURST_CTRL (Offset 0x0455) */
-#define BIT_TIDEMPTY_Q7_V1 BIT(22)
+#define BIT_AMPDU_BURST_GLOBAL_EN BIT(0)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_AMPDU_MAX_TIME (Offset 0x0456) */
+#define BIT_SHIFT_AMPDU_MAX_TIME 0
+#define BIT_MASK_AMPDU_MAX_TIME 0xff
+#define BIT_AMPDU_MAX_TIME(x) \
+ (((x) & BIT_MASK_AMPDU_MAX_TIME) << BIT_SHIFT_AMPDU_MAX_TIME)
+#define BITS_AMPDU_MAX_TIME \
+ (BIT_MASK_AMPDU_MAX_TIME << BIT_SHIFT_AMPDU_MAX_TIME)
+#define BIT_CLEAR_AMPDU_MAX_TIME(x) ((x) & (~BITS_AMPDU_MAX_TIME))
+#define BIT_GET_AMPDU_MAX_TIME(x) \
+ (((x) >> BIT_SHIFT_AMPDU_MAX_TIME) & BIT_MASK_AMPDU_MAX_TIME)
+#define BIT_SET_AMPDU_MAX_TIME(x, v) \
+ (BIT_CLEAR_AMPDU_MAX_TIME(x) | BIT_AMPDU_MAX_TIME(v))
-/* 2 REG_Q7_INFO (Offset 0x0474) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_TAIL_PKT_Q7_V1 15
-#define BIT_MASK_TAIL_PKT_Q7_V1 0xff
-#define BIT_TAIL_PKT_Q7_V1(x) (((x) & BIT_MASK_TAIL_PKT_Q7_V1) << BIT_SHIFT_TAIL_PKT_Q7_V1)
-#define BIT_GET_TAIL_PKT_Q7_V1(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V1) & BIT_MASK_TAIL_PKT_Q7_V1)
+/* 2 REG_BCNQ1_BDNY_V1 (Offset 0x0456) */
+#define BIT_SHIFT_BCNQ1_PGBNDY_V1 0
+#define BIT_MASK_BCNQ1_PGBNDY_V1 0xfff
+#define BIT_BCNQ1_PGBNDY_V1(x) \
+ (((x) & BIT_MASK_BCNQ1_PGBNDY_V1) << BIT_SHIFT_BCNQ1_PGBNDY_V1)
+#define BITS_BCNQ1_PGBNDY_V1 \
+ (BIT_MASK_BCNQ1_PGBNDY_V1 << BIT_SHIFT_BCNQ1_PGBNDY_V1)
+#define BIT_CLEAR_BCNQ1_PGBNDY_V1(x) ((x) & (~BITS_BCNQ1_PGBNDY_V1))
+#define BIT_GET_BCNQ1_PGBNDY_V1(x) \
+ (((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1) & BIT_MASK_BCNQ1_PGBNDY_V1)
+#define BIT_SET_BCNQ1_PGBNDY_V1(x, v) \
+ (BIT_CLEAR_BCNQ1_PGBNDY_V1(x) | BIT_BCNQ1_PGBNDY_V1(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_TAB_SEL (Offset 0x0456) */
+#define BIT_SHIFT_RATE_SEL 0
+#define BIT_MASK_RATE_SEL 0xf
+#define BIT_RATE_SEL(x) (((x) & BIT_MASK_RATE_SEL) << BIT_SHIFT_RATE_SEL)
+#define BITS_RATE_SEL (BIT_MASK_RATE_SEL << BIT_SHIFT_RATE_SEL)
+#define BIT_CLEAR_RATE_SEL(x) ((x) & (~BITS_RATE_SEL))
+#define BIT_GET_RATE_SEL(x) (((x) >> BIT_SHIFT_RATE_SEL) & BIT_MASK_RATE_SEL)
+#define BIT_SET_RATE_SEL(x, v) (BIT_CLEAR_RATE_SEL(x) | BIT_RATE_SEL(v))
-/* 2 REG_Q7_INFO (Offset 0x0474) */
+/* 2 REG_BCN_INVALID_CTRL (Offset 0x0457) */
+#define BIT_EN_CLR_CMD_REL_BCN_PKT_P4 BIT(7)
+#define BIT_EN_BCN_PKT_REL_P4 BIT(6)
+#define BIT_EN_CLR_CMD_REL_BCN_PKT_P3 BIT(5)
+#define BIT_EN_BCN_PKT_REL_P3 BIT(4)
+#define BIT_EN_CLR_CMD_REL_BCN_PKT_P2 BIT(3)
+#define BIT_EN_BCN_PKT_REL_P2 BIT(2)
+#define BIT_EN_CLR_CMD_REL_BCN_PKT_P1 BIT(1)
-#define BIT_SHIFT_TAIL_PKT_Q7_V2 11
-#define BIT_MASK_TAIL_PKT_Q7_V2 0x7ff
-#define BIT_TAIL_PKT_Q7_V2(x) (((x) & BIT_MASK_TAIL_PKT_Q7_V2) << BIT_SHIFT_TAIL_PKT_Q7_V2)
-#define BIT_GET_TAIL_PKT_Q7_V2(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2) & BIT_MASK_TAIL_PKT_Q7_V2)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_BCNQ1_BDNY (Offset 0x0457) */
+#define BIT_SHIFT_BCNQ1_PGBNDY 0
+#define BIT_MASK_BCNQ1_PGBNDY 0xff
+#define BIT_BCNQ1_PGBNDY(x) \
+ (((x) & BIT_MASK_BCNQ1_PGBNDY) << BIT_SHIFT_BCNQ1_PGBNDY)
+#define BITS_BCNQ1_PGBNDY (BIT_MASK_BCNQ1_PGBNDY << BIT_SHIFT_BCNQ1_PGBNDY)
+#define BIT_CLEAR_BCNQ1_PGBNDY(x) ((x) & (~BITS_BCNQ1_PGBNDY))
+#define BIT_GET_BCNQ1_PGBNDY(x) \
+ (((x) >> BIT_SHIFT_BCNQ1_PGBNDY) & BIT_MASK_BCNQ1_PGBNDY)
+#define BIT_SET_BCNQ1_PGBNDY(x, v) \
+ (BIT_CLEAR_BCNQ1_PGBNDY(x) | BIT_BCNQ1_PGBNDY(v))
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_Q7_INFO (Offset 0x0474) */
+/* 2 REG_BCN_INVALID_CTRL (Offset 0x0457) */
+#define BIT_EN_BCN_PKT_REL_P1 BIT(0)
-#define BIT_SHIFT_PKT_NUM_Q7_V1 8
-#define BIT_MASK_PKT_NUM_Q7_V1 0x7f
-#define BIT_PKT_NUM_Q7_V1(x) (((x) & BIT_MASK_PKT_NUM_Q7_V1) << BIT_SHIFT_PKT_NUM_Q7_V1)
-#define BIT_GET_PKT_NUM_Q7_V1(x) (((x) >> BIT_SHIFT_PKT_NUM_Q7_V1) & BIT_MASK_PKT_NUM_Q7_V1)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_HEAD_PKT_Q7 0
-#define BIT_MASK_HEAD_PKT_Q7 0xff
-#define BIT_HEAD_PKT_Q7(x) (((x) & BIT_MASK_HEAD_PKT_Q7) << BIT_SHIFT_HEAD_PKT_Q7)
-#define BIT_GET_HEAD_PKT_Q7(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q7) & BIT_MASK_HEAD_PKT_Q7)
+/* 2 REG_AMPDU_MAX_LENGTH (Offset 0x0458) */
+#define BIT_SHIFT_AMPDU_MAX_LENGTH 0
+#define BIT_MASK_AMPDU_MAX_LENGTH 0xffffffffL
+#define BIT_AMPDU_MAX_LENGTH(x) \
+ (((x) & BIT_MASK_AMPDU_MAX_LENGTH) << BIT_SHIFT_AMPDU_MAX_LENGTH)
+#define BITS_AMPDU_MAX_LENGTH \
+ (BIT_MASK_AMPDU_MAX_LENGTH << BIT_SHIFT_AMPDU_MAX_LENGTH)
+#define BIT_CLEAR_AMPDU_MAX_LENGTH(x) ((x) & (~BITS_AMPDU_MAX_LENGTH))
+#define BIT_GET_AMPDU_MAX_LENGTH(x) \
+ (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH) & BIT_MASK_AMPDU_MAX_LENGTH)
+#define BIT_SET_AMPDU_MAX_LENGTH(x, v) \
+ (BIT_CLEAR_AMPDU_MAX_LENGTH(x) | BIT_AMPDU_MAX_LENGTH(v))
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_AMPDU_MAX_LENGTH_HT (Offset 0x0458) */
+#define BIT_SHIFT_AMPDU_MAX_LENGTH_HT 0
+#define BIT_MASK_AMPDU_MAX_LENGTH_HT 0xffff
+#define BIT_AMPDU_MAX_LENGTH_HT(x) \
+ (((x) & BIT_MASK_AMPDU_MAX_LENGTH_HT) << BIT_SHIFT_AMPDU_MAX_LENGTH_HT)
+#define BITS_AMPDU_MAX_LENGTH_HT \
+ (BIT_MASK_AMPDU_MAX_LENGTH_HT << BIT_SHIFT_AMPDU_MAX_LENGTH_HT)
+#define BIT_CLEAR_AMPDU_MAX_LENGTH_HT(x) ((x) & (~BITS_AMPDU_MAX_LENGTH_HT))
+#define BIT_GET_AMPDU_MAX_LENGTH_HT(x) \
+ (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_HT) & BIT_MASK_AMPDU_MAX_LENGTH_HT)
+#define BIT_SET_AMPDU_MAX_LENGTH_HT(x, v) \
+ (BIT_CLEAR_AMPDU_MAX_LENGTH_HT(x) | BIT_AMPDU_MAX_LENGTH_HT(v))
-/* 2 REG_Q7_INFO (Offset 0x0474) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_HEAD_PKT_Q7_V1 0
-#define BIT_MASK_HEAD_PKT_Q7_V1 0x7ff
-#define BIT_HEAD_PKT_Q7_V1(x) (((x) & BIT_MASK_HEAD_PKT_Q7_V1) << BIT_SHIFT_HEAD_PKT_Q7_V1)
-#define BIT_GET_HEAD_PKT_Q7_V1(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1) & BIT_MASK_HEAD_PKT_Q7_V1)
+/* 2 REG_ACQ_STOP (Offset 0x045C) */
+#define BIT_AC7Q_STOP BIT(7)
+#define BIT_AC6Q_STOP BIT(6)
+#define BIT_AC5Q_STOP BIT(5)
+#define BIT_AC4Q_STOP BIT(4)
+#define BIT_AC3Q_STOP BIT(3)
+#define BIT_AC2Q_STOP BIT(2)
+#define BIT_AC1Q_STOP BIT(1)
+#define BIT_AC0Q_STOP BIT(0)
-/* 2 REG_WMAC_LBK_BUF_HD_V1 (Offset 0x0478) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1 0
-#define BIT_MASK_WMAC_LBK_BUF_HEAD_V1 0xfff
-#define BIT_WMAC_LBK_BUF_HEAD_V1(x) (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1) << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1)
-#define BIT_GET_WMAC_LBK_BUF_HEAD_V1(x) (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1)
+/* 2 REG_WMAC_LBK_BUF_HD (Offset 0x045D) */
+#define BIT_SHIFT_WMAC_LBK_BUF_HEAD 0
+#define BIT_MASK_WMAC_LBK_BUF_HEAD 0xff
+#define BIT_WMAC_LBK_BUF_HEAD(x) \
+ (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD) << BIT_SHIFT_WMAC_LBK_BUF_HEAD)
+#define BITS_WMAC_LBK_BUF_HEAD \
+ (BIT_MASK_WMAC_LBK_BUF_HEAD << BIT_SHIFT_WMAC_LBK_BUF_HEAD)
+#define BIT_CLEAR_WMAC_LBK_BUF_HEAD(x) ((x) & (~BITS_WMAC_LBK_BUF_HEAD))
+#define BIT_GET_WMAC_LBK_BUF_HEAD(x) \
+ (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD) & BIT_MASK_WMAC_LBK_BUF_HEAD)
+#define BIT_SET_WMAC_LBK_BUF_HEAD(x, v) \
+ (BIT_CLEAR_WMAC_LBK_BUF_HEAD(x) | BIT_WMAC_LBK_BUF_HEAD(v))
-/* 2 REG_MGQ_BDNY_V1 (Offset 0x047A) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_MGQ_PGBNDY_V1 0
-#define BIT_MASK_MGQ_PGBNDY_V1 0xfff
-#define BIT_MGQ_PGBNDY_V1(x) (((x) & BIT_MASK_MGQ_PGBNDY_V1) << BIT_SHIFT_MGQ_PGBNDY_V1)
-#define BIT_GET_MGQ_PGBNDY_V1(x) (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1) & BIT_MASK_MGQ_PGBNDY_V1)
+/* 2 REG_NDPA_RATE (Offset 0x045D) */
+#define BIT_SHIFT_R_NDPA_RATE_V1 0
+#define BIT_MASK_R_NDPA_RATE_V1 0xff
+#define BIT_R_NDPA_RATE_V1(x) \
+ (((x) & BIT_MASK_R_NDPA_RATE_V1) << BIT_SHIFT_R_NDPA_RATE_V1)
+#define BITS_R_NDPA_RATE_V1 \
+ (BIT_MASK_R_NDPA_RATE_V1 << BIT_SHIFT_R_NDPA_RATE_V1)
+#define BIT_CLEAR_R_NDPA_RATE_V1(x) ((x) & (~BITS_R_NDPA_RATE_V1))
+#define BIT_GET_R_NDPA_RATE_V1(x) \
+ (((x) >> BIT_SHIFT_R_NDPA_RATE_V1) & BIT_MASK_R_NDPA_RATE_V1)
+#define BIT_SET_R_NDPA_RATE_V1(x, v) \
+ (BIT_CLEAR_R_NDPA_RATE_V1(x) | BIT_R_NDPA_RATE_V1(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_TX_HANG_CTRL (Offset 0x045E) */
+#define BIT_R_EN_GNT_BT_AWAKE BIT(3)
-/* 2 REG_TXRPT_CTRL (Offset 0x047C) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_SPC_READ_PTR 24
-#define BIT_MASK_SPC_READ_PTR 0xf
-#define BIT_SPC_READ_PTR(x) (((x) & BIT_MASK_SPC_READ_PTR) << BIT_SHIFT_SPC_READ_PTR)
-#define BIT_GET_SPC_READ_PTR(x) (((x) >> BIT_SHIFT_SPC_READ_PTR) & BIT_MASK_SPC_READ_PTR)
+/* 2 REG_TX_HANG_CTRL (Offset 0x045E) */
+#define BIT_EN_GNT_BT_AWAKE BIT(3)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_TX_HANG_CTRL (Offset 0x045E) */
+#define BIT_EN_EOF_V1 BIT(2)
-/* 2 REG_TXRPT_CTRL (Offset 0x047C) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_TRXRPT_TIMER_TH 24
-#define BIT_MASK_TRXRPT_TIMER_TH 0xff
-#define BIT_TRXRPT_TIMER_TH(x) (((x) & BIT_MASK_TRXRPT_TIMER_TH) << BIT_SHIFT_TRXRPT_TIMER_TH)
-#define BIT_GET_TRXRPT_TIMER_TH(x) (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH) & BIT_MASK_TRXRPT_TIMER_TH)
+/* 2 REG_TX_HANG_CTRL (Offset 0x045E) */
+#define BIT_DIS_OQT_BLOCK BIT(1)
+#define BIT_SEARCH_QUEUE_EN BIT(0)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */
+#define BIT_R_DIS_MACID_RELEASE_RTY BIT(5)
-/* 2 REG_TXRPT_CTRL (Offset 0x047C) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_SPC_WRITE_PTR 16
-#define BIT_MASK_SPC_WRITE_PTR 0xf
-#define BIT_SPC_WRITE_PTR(x) (((x) & BIT_MASK_SPC_WRITE_PTR) << BIT_SHIFT_SPC_WRITE_PTR)
-#define BIT_GET_SPC_WRITE_PTR(x) (((x) >> BIT_SHIFT_SPC_WRITE_PTR) & BIT_MASK_SPC_WRITE_PTR)
+/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */
+#define BIT_DIS_MACID_RELEASE_RTY BIT(5)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */
+#define BIT_SHIFT_BW_SIGTA 3
+#define BIT_MASK_BW_SIGTA 0x3
+#define BIT_BW_SIGTA(x) (((x) & BIT_MASK_BW_SIGTA) << BIT_SHIFT_BW_SIGTA)
+#define BITS_BW_SIGTA (BIT_MASK_BW_SIGTA << BIT_SHIFT_BW_SIGTA)
+#define BIT_CLEAR_BW_SIGTA(x) ((x) & (~BITS_BW_SIGTA))
+#define BIT_GET_BW_SIGTA(x) (((x) >> BIT_SHIFT_BW_SIGTA) & BIT_MASK_BW_SIGTA)
+#define BIT_SET_BW_SIGTA(x, v) (BIT_CLEAR_BW_SIGTA(x) | BIT_BW_SIGTA(v))
-/* 2 REG_TXRPT_CTRL (Offset 0x047C) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_TRXRPT_LEN_TH 16
-#define BIT_MASK_TRXRPT_LEN_TH 0xff
-#define BIT_TRXRPT_LEN_TH(x) (((x) & BIT_MASK_TRXRPT_LEN_TH) << BIT_SHIFT_TRXRPT_LEN_TH)
-#define BIT_GET_TRXRPT_LEN_TH(x) (((x) >> BIT_SHIFT_TRXRPT_LEN_TH) & BIT_MASK_TRXRPT_LEN_TH)
+/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */
+#define BIT_SHIFT_R_NDPA_RATE 2
+#define BIT_MASK_R_NDPA_RATE 0x3f
+#define BIT_R_NDPA_RATE(x) \
+ (((x) & BIT_MASK_R_NDPA_RATE) << BIT_SHIFT_R_NDPA_RATE)
+#define BITS_R_NDPA_RATE (BIT_MASK_R_NDPA_RATE << BIT_SHIFT_R_NDPA_RATE)
+#define BIT_CLEAR_R_NDPA_RATE(x) ((x) & (~BITS_R_NDPA_RATE))
+#define BIT_GET_R_NDPA_RATE(x) \
+ (((x) >> BIT_SHIFT_R_NDPA_RATE) & BIT_MASK_R_NDPA_RATE)
+#define BIT_SET_R_NDPA_RATE(x, v) \
+ (BIT_CLEAR_R_NDPA_RATE(x) | BIT_R_NDPA_RATE(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */
+#define BIT_EN_BAR_SIGTA BIT(2)
-/* 2 REG_TXRPT_CTRL (Offset 0x047C) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_AC_READ_PTR 8
-#define BIT_MASK_AC_READ_PTR 0xf
-#define BIT_AC_READ_PTR(x) (((x) & BIT_MASK_AC_READ_PTR) << BIT_SHIFT_AC_READ_PTR)
-#define BIT_GET_AC_READ_PTR(x) (((x) >> BIT_SHIFT_AC_READ_PTR) & BIT_MASK_AC_READ_PTR)
+/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */
+#define BIT_SHIFT_R_NDPA_BW 0
+#define BIT_MASK_R_NDPA_BW 0x3
+#define BIT_R_NDPA_BW(x) (((x) & BIT_MASK_R_NDPA_BW) << BIT_SHIFT_R_NDPA_BW)
+#define BITS_R_NDPA_BW (BIT_MASK_R_NDPA_BW << BIT_SHIFT_R_NDPA_BW)
+#define BIT_CLEAR_R_NDPA_BW(x) ((x) & (~BITS_R_NDPA_BW))
+#define BIT_GET_R_NDPA_BW(x) (((x) >> BIT_SHIFT_R_NDPA_BW) & BIT_MASK_R_NDPA_BW)
+#define BIT_SET_R_NDPA_BW(x, v) (BIT_CLEAR_R_NDPA_BW(x) | BIT_R_NDPA_BW(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */
+#define BIT_SHIFT_NDPA_BW 0
+#define BIT_MASK_NDPA_BW 0x3
+#define BIT_NDPA_BW(x) (((x) & BIT_MASK_NDPA_BW) << BIT_SHIFT_NDPA_BW)
+#define BITS_NDPA_BW (BIT_MASK_NDPA_BW << BIT_SHIFT_NDPA_BW)
+#define BIT_CLEAR_NDPA_BW(x) ((x) & (~BITS_NDPA_BW))
+#define BIT_GET_NDPA_BW(x) (((x) >> BIT_SHIFT_NDPA_BW) & BIT_MASK_NDPA_BW)
+#define BIT_SET_NDPA_BW(x, v) (BIT_CLEAR_NDPA_BW(x) | BIT_NDPA_BW(v))
-/* 2 REG_TXRPT_CTRL (Offset 0x047C) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_TRXRPT_READ_PTR 8
-#define BIT_MASK_TRXRPT_READ_PTR 0xff
-#define BIT_TRXRPT_READ_PTR(x) (((x) & BIT_MASK_TRXRPT_READ_PTR) << BIT_SHIFT_TRXRPT_READ_PTR)
-#define BIT_GET_TRXRPT_READ_PTR(x) (((x) >> BIT_SHIFT_TRXRPT_READ_PTR) & BIT_MASK_TRXRPT_READ_PTR)
+/* 2 REG_FAST_EDCA_CTRL (Offset 0x0460) */
+#define BIT_SHIFT_FAST_EDCA_TO_V1 16
+#define BIT_MASK_FAST_EDCA_TO_V1 0xff
+#define BIT_FAST_EDCA_TO_V1(x) \
+ (((x) & BIT_MASK_FAST_EDCA_TO_V1) << BIT_SHIFT_FAST_EDCA_TO_V1)
+#define BITS_FAST_EDCA_TO_V1 \
+ (BIT_MASK_FAST_EDCA_TO_V1 << BIT_SHIFT_FAST_EDCA_TO_V1)
+#define BIT_CLEAR_FAST_EDCA_TO_V1(x) ((x) & (~BITS_FAST_EDCA_TO_V1))
+#define BIT_GET_FAST_EDCA_TO_V1(x) \
+ (((x) >> BIT_SHIFT_FAST_EDCA_TO_V1) & BIT_MASK_FAST_EDCA_TO_V1)
+#define BIT_SET_FAST_EDCA_TO_V1(x, v) \
+ (BIT_CLEAR_FAST_EDCA_TO_V1(x) | BIT_FAST_EDCA_TO_V1(v))
+
+#define BIT_SHIFT_AC3_AC7_FAST_EDCA_PKT_TH 12
+#define BIT_MASK_AC3_AC7_FAST_EDCA_PKT_TH 0xf
+#define BIT_AC3_AC7_FAST_EDCA_PKT_TH(x) \
+ (((x) & BIT_MASK_AC3_AC7_FAST_EDCA_PKT_TH) \
+ << BIT_SHIFT_AC3_AC7_FAST_EDCA_PKT_TH)
+#define BITS_AC3_AC7_FAST_EDCA_PKT_TH \
+ (BIT_MASK_AC3_AC7_FAST_EDCA_PKT_TH \
+ << BIT_SHIFT_AC3_AC7_FAST_EDCA_PKT_TH)
+#define BIT_CLEAR_AC3_AC7_FAST_EDCA_PKT_TH(x) \
+ ((x) & (~BITS_AC3_AC7_FAST_EDCA_PKT_TH))
+#define BIT_GET_AC3_AC7_FAST_EDCA_PKT_TH(x) \
+ (((x) >> BIT_SHIFT_AC3_AC7_FAST_EDCA_PKT_TH) & \
+ BIT_MASK_AC3_AC7_FAST_EDCA_PKT_TH)
+#define BIT_SET_AC3_AC7_FAST_EDCA_PKT_TH(x, v) \
+ (BIT_CLEAR_AC3_AC7_FAST_EDCA_PKT_TH(x) | \
+ BIT_AC3_AC7_FAST_EDCA_PKT_TH(v))
+
+#define BIT_SHIFT_AC2_FAST_EDCA_PKT_TH 8
+#define BIT_MASK_AC2_FAST_EDCA_PKT_TH 0xf
+#define BIT_AC2_FAST_EDCA_PKT_TH(x) \
+ (((x) & BIT_MASK_AC2_FAST_EDCA_PKT_TH) \
+ << BIT_SHIFT_AC2_FAST_EDCA_PKT_TH)
+#define BITS_AC2_FAST_EDCA_PKT_TH \
+ (BIT_MASK_AC2_FAST_EDCA_PKT_TH << BIT_SHIFT_AC2_FAST_EDCA_PKT_TH)
+#define BIT_CLEAR_AC2_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_AC2_FAST_EDCA_PKT_TH))
+#define BIT_GET_AC2_FAST_EDCA_PKT_TH(x) \
+ (((x) >> BIT_SHIFT_AC2_FAST_EDCA_PKT_TH) & \
+ BIT_MASK_AC2_FAST_EDCA_PKT_TH)
+#define BIT_SET_AC2_FAST_EDCA_PKT_TH(x, v) \
+ (BIT_CLEAR_AC2_FAST_EDCA_PKT_TH(x) | BIT_AC2_FAST_EDCA_PKT_TH(v))
+
+#define BIT_SHIFT_AC1_FAST_EDCA_PKT_TH 4
+#define BIT_MASK_AC1_FAST_EDCA_PKT_TH 0xf
+#define BIT_AC1_FAST_EDCA_PKT_TH(x) \
+ (((x) & BIT_MASK_AC1_FAST_EDCA_PKT_TH) \
+ << BIT_SHIFT_AC1_FAST_EDCA_PKT_TH)
+#define BITS_AC1_FAST_EDCA_PKT_TH \
+ (BIT_MASK_AC1_FAST_EDCA_PKT_TH << BIT_SHIFT_AC1_FAST_EDCA_PKT_TH)
+#define BIT_CLEAR_AC1_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_AC1_FAST_EDCA_PKT_TH))
+#define BIT_GET_AC1_FAST_EDCA_PKT_TH(x) \
+ (((x) >> BIT_SHIFT_AC1_FAST_EDCA_PKT_TH) & \
+ BIT_MASK_AC1_FAST_EDCA_PKT_TH)
+#define BIT_SET_AC1_FAST_EDCA_PKT_TH(x, v) \
+ (BIT_CLEAR_AC1_FAST_EDCA_PKT_TH(x) | BIT_AC1_FAST_EDCA_PKT_TH(v))
+
+#define BIT_SHIFT_AC0_FAST_EDCA_PKT_TH 0
+#define BIT_MASK_AC0_FAST_EDCA_PKT_TH 0xf
+#define BIT_AC0_FAST_EDCA_PKT_TH(x) \
+ (((x) & BIT_MASK_AC0_FAST_EDCA_PKT_TH) \
+ << BIT_SHIFT_AC0_FAST_EDCA_PKT_TH)
+#define BITS_AC0_FAST_EDCA_PKT_TH \
+ (BIT_MASK_AC0_FAST_EDCA_PKT_TH << BIT_SHIFT_AC0_FAST_EDCA_PKT_TH)
+#define BIT_CLEAR_AC0_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_AC0_FAST_EDCA_PKT_TH))
+#define BIT_GET_AC0_FAST_EDCA_PKT_TH(x) \
+ (((x) >> BIT_SHIFT_AC0_FAST_EDCA_PKT_TH) & \
+ BIT_MASK_AC0_FAST_EDCA_PKT_TH)
+#define BIT_SET_AC0_FAST_EDCA_PKT_TH(x, v) \
+ (BIT_CLEAR_AC0_FAST_EDCA_PKT_TH(x) | BIT_AC0_FAST_EDCA_PKT_TH(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_AMPDU_MAX_LENGTH_VHT (Offset 0x0460) */
+
+#define BIT_SHIFT_AMPDU_MAX_LENGTH_VHT 0
+#define BIT_MASK_AMPDU_MAX_LENGTH_VHT 0x3ffff
+#define BIT_AMPDU_MAX_LENGTH_VHT(x) \
+ (((x) & BIT_MASK_AMPDU_MAX_LENGTH_VHT) \
+ << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT)
+#define BITS_AMPDU_MAX_LENGTH_VHT \
+ (BIT_MASK_AMPDU_MAX_LENGTH_VHT << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT)
+#define BIT_CLEAR_AMPDU_MAX_LENGTH_VHT(x) ((x) & (~BITS_AMPDU_MAX_LENGTH_VHT))
+#define BIT_GET_AMPDU_MAX_LENGTH_VHT(x) \
+ (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_VHT) & \
+ BIT_MASK_AMPDU_MAX_LENGTH_VHT)
+#define BIT_SET_AMPDU_MAX_LENGTH_VHT(x, v) \
+ (BIT_CLEAR_AMPDU_MAX_LENGTH_VHT(x) | BIT_AMPDU_MAX_LENGTH_VHT(v))
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+/* 2 REG_AMPDU_MAX_LENGTH_VHT (Offset 0x0460) */
+
+#define BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1 0
+#define BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1 0xfffff
+#define BIT_AMPDU_MAX_LENGTH_VHT_V1(x) \
+ (((x) & BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1) \
+ << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1)
+#define BITS_AMPDU_MAX_LENGTH_VHT_V1 \
+ (BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1 << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1)
+#define BIT_CLEAR_AMPDU_MAX_LENGTH_VHT_V1(x) \
+ ((x) & (~BITS_AMPDU_MAX_LENGTH_VHT_V1))
+#define BIT_GET_AMPDU_MAX_LENGTH_VHT_V1(x) \
+ (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1) & \
+ BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1)
+#define BIT_SET_AMPDU_MAX_LENGTH_VHT_V1(x, v) \
+ (BIT_CLEAR_AMPDU_MAX_LENGTH_VHT_V1(x) | BIT_AMPDU_MAX_LENGTH_VHT_V1(v))
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_RD_RESP_PKT_TH (Offset 0x0463) */
+
+#define BIT_SHIFT_RD_RESP_PKT_TH 0
+#define BIT_MASK_RD_RESP_PKT_TH 0x1f
+#define BIT_RD_RESP_PKT_TH(x) \
+ (((x) & BIT_MASK_RD_RESP_PKT_TH) << BIT_SHIFT_RD_RESP_PKT_TH)
+#define BITS_RD_RESP_PKT_TH \
+ (BIT_MASK_RD_RESP_PKT_TH << BIT_SHIFT_RD_RESP_PKT_TH)
+#define BIT_CLEAR_RD_RESP_PKT_TH(x) ((x) & (~BITS_RD_RESP_PKT_TH))
+#define BIT_GET_RD_RESP_PKT_TH(x) \
+ (((x) >> BIT_SHIFT_RD_RESP_PKT_TH) & BIT_MASK_RD_RESP_PKT_TH)
+#define BIT_SET_RD_RESP_PKT_TH(x, v) \
+ (BIT_CLEAR_RD_RESP_PKT_TH(x) | BIT_RD_RESP_PKT_TH(v))
-/* 2 REG_TXRPT_CTRL (Offset 0x047C) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_AC_WRITE_PTR 0
-#define BIT_MASK_AC_WRITE_PTR 0xf
-#define BIT_AC_WRITE_PTR(x) (((x) & BIT_MASK_AC_WRITE_PTR) << BIT_SHIFT_AC_WRITE_PTR)
-#define BIT_GET_AC_WRITE_PTR(x) (((x) >> BIT_SHIFT_AC_WRITE_PTR) & BIT_MASK_AC_WRITE_PTR)
+/* 2 REG_RD_RESP_PKT_TH (Offset 0x0463) */
+#define BIT_SHIFT_RD_RESP_PKT_TH_V1 0
+#define BIT_MASK_RD_RESP_PKT_TH_V1 0x3f
+#define BIT_RD_RESP_PKT_TH_V1(x) \
+ (((x) & BIT_MASK_RD_RESP_PKT_TH_V1) << BIT_SHIFT_RD_RESP_PKT_TH_V1)
+#define BITS_RD_RESP_PKT_TH_V1 \
+ (BIT_MASK_RD_RESP_PKT_TH_V1 << BIT_SHIFT_RD_RESP_PKT_TH_V1)
+#define BIT_CLEAR_RD_RESP_PKT_TH_V1(x) ((x) & (~BITS_RD_RESP_PKT_TH_V1))
+#define BIT_GET_RD_RESP_PKT_TH_V1(x) \
+ (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1) & BIT_MASK_RD_RESP_PKT_TH_V1)
+#define BIT_SET_RD_RESP_PKT_TH_V1(x, v) \
+ (BIT_CLEAR_RD_RESP_PKT_TH_V1(x) | BIT_RD_RESP_PKT_TH_V1(v))
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_CMDQ_INFO (Offset 0x0464) */
+#define BIT_SHIFT_QUEUEMACID_CMDQ_V1 25
+#define BIT_MASK_QUEUEMACID_CMDQ_V1 0x7f
+#define BIT_QUEUEMACID_CMDQ_V1(x) \
+ (((x) & BIT_MASK_QUEUEMACID_CMDQ_V1) << BIT_SHIFT_QUEUEMACID_CMDQ_V1)
+#define BITS_QUEUEMACID_CMDQ_V1 \
+ (BIT_MASK_QUEUEMACID_CMDQ_V1 << BIT_SHIFT_QUEUEMACID_CMDQ_V1)
+#define BIT_CLEAR_QUEUEMACID_CMDQ_V1(x) ((x) & (~BITS_QUEUEMACID_CMDQ_V1))
+#define BIT_GET_QUEUEMACID_CMDQ_V1(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1) & BIT_MASK_QUEUEMACID_CMDQ_V1)
+#define BIT_SET_QUEUEMACID_CMDQ_V1(x, v) \
+ (BIT_CLEAR_QUEUEMACID_CMDQ_V1(x) | BIT_QUEUEMACID_CMDQ_V1(v))
-/* 2 REG_TXRPT_CTRL (Offset 0x047C) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_TRXRPT_WRITE_PTR 0
-#define BIT_MASK_TRXRPT_WRITE_PTR 0xff
-#define BIT_TRXRPT_WRITE_PTR(x) (((x) & BIT_MASK_TRXRPT_WRITE_PTR) << BIT_SHIFT_TRXRPT_WRITE_PTR)
-#define BIT_GET_TRXRPT_WRITE_PTR(x) (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR) & BIT_MASK_TRXRPT_WRITE_PTR)
+/* 2 REG_CMDQ_INFO (Offset 0x0464) */
+#define BIT_SHIFT_PKT_NUM_CMDQ_V2 24
+#define BIT_MASK_PKT_NUM_CMDQ_V2 0xff
+#define BIT_PKT_NUM_CMDQ_V2(x) \
+ (((x) & BIT_MASK_PKT_NUM_CMDQ_V2) << BIT_SHIFT_PKT_NUM_CMDQ_V2)
+#define BITS_PKT_NUM_CMDQ_V2 \
+ (BIT_MASK_PKT_NUM_CMDQ_V2 << BIT_SHIFT_PKT_NUM_CMDQ_V2)
+#define BIT_CLEAR_PKT_NUM_CMDQ_V2(x) ((x) & (~BITS_PKT_NUM_CMDQ_V2))
+#define BIT_GET_PKT_NUM_CMDQ_V2(x) \
+ (((x) >> BIT_SHIFT_PKT_NUM_CMDQ_V2) & BIT_MASK_PKT_NUM_CMDQ_V2)
+#define BIT_SET_PKT_NUM_CMDQ_V2(x, v) \
+ (BIT_CLEAR_PKT_NUM_CMDQ_V2(x) | BIT_PKT_NUM_CMDQ_V2(v))
#endif
+#if (HALMAC_8197F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_CMDQ_INFO (Offset 0x0464) */
+#define BIT_SHIFT_PKT_NUM 23
+#define BIT_MASK_PKT_NUM 0x1ff
+#define BIT_PKT_NUM(x) (((x) & BIT_MASK_PKT_NUM) << BIT_SHIFT_PKT_NUM)
+#define BITS_PKT_NUM (BIT_MASK_PKT_NUM << BIT_SHIFT_PKT_NUM)
+#define BIT_CLEAR_PKT_NUM(x) ((x) & (~BITS_PKT_NUM))
+#define BIT_GET_PKT_NUM(x) (((x) >> BIT_SHIFT_PKT_NUM) & BIT_MASK_PKT_NUM)
+#define BIT_SET_PKT_NUM(x, v) (BIT_CLEAR_PKT_NUM(x) | BIT_PKT_NUM(v))
-/* 2 REG_INIRTS_RATE_SEL (Offset 0x0480) */
+#endif
-#define BIT_LEAG_RTS_BW_DUP BIT(5)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_BASIC_CFEND_RATE (Offset 0x0481) */
+/* 2 REG_CMDQ_INFO (Offset 0x0464) */
+#define BIT_SHIFT_QUEUEAC_CMDQ_V1 23
+#define BIT_MASK_QUEUEAC_CMDQ_V1 0x3
+#define BIT_QUEUEAC_CMDQ_V1(x) \
+ (((x) & BIT_MASK_QUEUEAC_CMDQ_V1) << BIT_SHIFT_QUEUEAC_CMDQ_V1)
+#define BITS_QUEUEAC_CMDQ_V1 \
+ (BIT_MASK_QUEUEAC_CMDQ_V1 << BIT_SHIFT_QUEUEAC_CMDQ_V1)
+#define BIT_CLEAR_QUEUEAC_CMDQ_V1(x) ((x) & (~BITS_QUEUEAC_CMDQ_V1))
+#define BIT_GET_QUEUEAC_CMDQ_V1(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1) & BIT_MASK_QUEUEAC_CMDQ_V1)
+#define BIT_SET_QUEUEAC_CMDQ_V1(x, v) \
+ (BIT_CLEAR_QUEUEAC_CMDQ_V1(x) | BIT_QUEUEAC_CMDQ_V1(v))
-#define BIT_SHIFT_BASIC_CFEND_RATE 0
-#define BIT_MASK_BASIC_CFEND_RATE 0x1f
-#define BIT_BASIC_CFEND_RATE(x) (((x) & BIT_MASK_BASIC_CFEND_RATE) << BIT_SHIFT_BASIC_CFEND_RATE)
-#define BIT_GET_BASIC_CFEND_RATE(x) (((x) >> BIT_SHIFT_BASIC_CFEND_RATE) & BIT_MASK_BASIC_CFEND_RATE)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_STBC_CFEND_RATE (Offset 0x0482) */
+/* 2 REG_CMDQ_INFO (Offset 0x0464) */
+#define BIT_TIDEMPTY_CMDQ_V1 BIT(22)
-#define BIT_SHIFT_STBC_CFEND_RATE 0
-#define BIT_MASK_STBC_CFEND_RATE 0x1f
-#define BIT_STBC_CFEND_RATE(x) (((x) & BIT_MASK_STBC_CFEND_RATE) << BIT_SHIFT_STBC_CFEND_RATE)
-#define BIT_GET_STBC_CFEND_RATE(x) (((x) >> BIT_SHIFT_STBC_CFEND_RATE) & BIT_MASK_STBC_CFEND_RATE)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_DATA_SC (Offset 0x0483) */
+/* 2 REG_CMDQ_INFO (Offset 0x0464) */
+#define BIT_SHIFT_TAIL_PKT_CMDQ 16
+#define BIT_MASK_TAIL_PKT_CMDQ 0xff
+#define BIT_TAIL_PKT_CMDQ(x) \
+ (((x) & BIT_MASK_TAIL_PKT_CMDQ) << BIT_SHIFT_TAIL_PKT_CMDQ)
+#define BITS_TAIL_PKT_CMDQ (BIT_MASK_TAIL_PKT_CMDQ << BIT_SHIFT_TAIL_PKT_CMDQ)
+#define BIT_CLEAR_TAIL_PKT_CMDQ(x) ((x) & (~BITS_TAIL_PKT_CMDQ))
+#define BIT_GET_TAIL_PKT_CMDQ(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_CMDQ) & BIT_MASK_TAIL_PKT_CMDQ)
+#define BIT_SET_TAIL_PKT_CMDQ(x, v) \
+ (BIT_CLEAR_TAIL_PKT_CMDQ(x) | BIT_TAIL_PKT_CMDQ(v))
-#define BIT_SHIFT_TXSC_40M 4
-#define BIT_MASK_TXSC_40M 0xf
-#define BIT_TXSC_40M(x) (((x) & BIT_MASK_TXSC_40M) << BIT_SHIFT_TXSC_40M)
-#define BIT_GET_TXSC_40M(x) (((x) >> BIT_SHIFT_TXSC_40M) & BIT_MASK_TXSC_40M)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_TXSC_20M 0
-#define BIT_MASK_TXSC_20M 0xf
-#define BIT_TXSC_20M(x) (((x) & BIT_MASK_TXSC_20M) << BIT_SHIFT_TXSC_20M)
-#define BIT_GET_TXSC_20M(x) (((x) >> BIT_SHIFT_TXSC_20M) & BIT_MASK_TXSC_20M)
+/* 2 REG_CMDQ_INFO (Offset 0x0464) */
+#define BIT_SHIFT_TAIL_PKT_CMDQ_V2 11
+#define BIT_MASK_TAIL_PKT_CMDQ_V2 0x7ff
+#define BIT_TAIL_PKT_CMDQ_V2(x) \
+ (((x) & BIT_MASK_TAIL_PKT_CMDQ_V2) << BIT_SHIFT_TAIL_PKT_CMDQ_V2)
+#define BITS_TAIL_PKT_CMDQ_V2 \
+ (BIT_MASK_TAIL_PKT_CMDQ_V2 << BIT_SHIFT_TAIL_PKT_CMDQ_V2)
+#define BIT_CLEAR_TAIL_PKT_CMDQ_V2(x) ((x) & (~BITS_TAIL_PKT_CMDQ_V2))
+#define BIT_GET_TAIL_PKT_CMDQ_V2(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_CMDQ_V2) & BIT_MASK_TAIL_PKT_CMDQ_V2)
+#define BIT_SET_TAIL_PKT_CMDQ_V2(x, v) \
+ (BIT_CLEAR_TAIL_PKT_CMDQ_V2(x) | BIT_TAIL_PKT_CMDQ_V2(v))
-/* 2 REG_MACID_SLEEP3 (Offset 0x0484) */
+#endif
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_MACID127_96_PKTSLEEP 0
-#define BIT_MASK_MACID127_96_PKTSLEEP 0xffffffffL
-#define BIT_MACID127_96_PKTSLEEP(x) (((x) & BIT_MASK_MACID127_96_PKTSLEEP) << BIT_SHIFT_MACID127_96_PKTSLEEP)
-#define BIT_GET_MACID127_96_PKTSLEEP(x) (((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP) & BIT_MASK_MACID127_96_PKTSLEEP)
+/* 2 REG_NEW_EDCA_CTRL_V1 (Offset 0x0464) */
+#define BIT_SHIFT_RANDOM_VALUE_SHIFT 9
+#define BIT_MASK_RANDOM_VALUE_SHIFT 0x7
+#define BIT_RANDOM_VALUE_SHIFT(x) \
+ (((x) & BIT_MASK_RANDOM_VALUE_SHIFT) << BIT_SHIFT_RANDOM_VALUE_SHIFT)
+#define BITS_RANDOM_VALUE_SHIFT \
+ (BIT_MASK_RANDOM_VALUE_SHIFT << BIT_SHIFT_RANDOM_VALUE_SHIFT)
+#define BIT_CLEAR_RANDOM_VALUE_SHIFT(x) ((x) & (~BITS_RANDOM_VALUE_SHIFT))
+#define BIT_GET_RANDOM_VALUE_SHIFT(x) \
+ (((x) >> BIT_SHIFT_RANDOM_VALUE_SHIFT) & BIT_MASK_RANDOM_VALUE_SHIFT)
+#define BIT_SET_RANDOM_VALUE_SHIFT(x, v) \
+ (BIT_CLEAR_RANDOM_VALUE_SHIFT(x) | BIT_RANDOM_VALUE_SHIFT(v))
-/* 2 REG_MACID_SLEEP1 (Offset 0x0488) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_MACID63_32_PKTSLEEP 0
-#define BIT_MASK_MACID63_32_PKTSLEEP 0xffffffffL
-#define BIT_MACID63_32_PKTSLEEP(x) (((x) & BIT_MASK_MACID63_32_PKTSLEEP) << BIT_SHIFT_MACID63_32_PKTSLEEP)
-#define BIT_GET_MACID63_32_PKTSLEEP(x) (((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP) & BIT_MASK_MACID63_32_PKTSLEEP)
+/* 2 REG_CMDQ_INFO (Offset 0x0464) */
+#define BIT_SHIFT_PKT_NUM_CMDQ 8
+#define BIT_MASK_PKT_NUM_CMDQ 0xff
+#define BIT_PKT_NUM_CMDQ(x) \
+ (((x) & BIT_MASK_PKT_NUM_CMDQ) << BIT_SHIFT_PKT_NUM_CMDQ)
+#define BITS_PKT_NUM_CMDQ (BIT_MASK_PKT_NUM_CMDQ << BIT_SHIFT_PKT_NUM_CMDQ)
+#define BIT_CLEAR_PKT_NUM_CMDQ(x) ((x) & (~BITS_PKT_NUM_CMDQ))
+#define BIT_GET_PKT_NUM_CMDQ(x) \
+ (((x) >> BIT_SHIFT_PKT_NUM_CMDQ) & BIT_MASK_PKT_NUM_CMDQ)
+#define BIT_SET_PKT_NUM_CMDQ(x, v) \
+ (BIT_CLEAR_PKT_NUM_CMDQ(x) | BIT_PKT_NUM_CMDQ(v))
-/* 2 REG_ARFR2_V1 (Offset 0x048C) */
+#endif
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_ARFR2_V1 0
-#define BIT_MASK_ARFR2_V1 0xffffffffffffffffL
-#define BIT_ARFR2_V1(x) (((x) & BIT_MASK_ARFR2_V1) << BIT_SHIFT_ARFR2_V1)
-#define BIT_GET_ARFR2_V1(x) (((x) >> BIT_SHIFT_ARFR2_V1) & BIT_MASK_ARFR2_V1)
+/* 2 REG_NEW_EDCA_CTRL_V1 (Offset 0x0464) */
+#define BIT_ENABLE_NEW_EDCA BIT(8)
-/* 2 REG_ARFR3_V1 (Offset 0x0494) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_ARFR3_V1 0
-#define BIT_MASK_ARFR3_V1 0xffffffffffffffffL
-#define BIT_ARFR3_V1(x) (((x) & BIT_MASK_ARFR3_V1) << BIT_SHIFT_ARFR3_V1)
-#define BIT_GET_ARFR3_V1(x) (((x) >> BIT_SHIFT_ARFR3_V1) & BIT_MASK_ARFR3_V1)
+/* 2 REG_CMDQ_INFO (Offset 0x0464) */
+#define BIT_SHIFT_HEAD_PKT_CMDQ 0
+#define BIT_MASK_HEAD_PKT_CMDQ 0xff
+#define BIT_HEAD_PKT_CMDQ(x) \
+ (((x) & BIT_MASK_HEAD_PKT_CMDQ) << BIT_SHIFT_HEAD_PKT_CMDQ)
+#define BITS_HEAD_PKT_CMDQ (BIT_MASK_HEAD_PKT_CMDQ << BIT_SHIFT_HEAD_PKT_CMDQ)
+#define BIT_CLEAR_HEAD_PKT_CMDQ(x) ((x) & (~BITS_HEAD_PKT_CMDQ))
+#define BIT_GET_HEAD_PKT_CMDQ(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ) & BIT_MASK_HEAD_PKT_CMDQ)
+#define BIT_SET_HEAD_PKT_CMDQ(x, v) \
+ (BIT_CLEAR_HEAD_PKT_CMDQ(x) | BIT_HEAD_PKT_CMDQ(v))
-/* 2 REG_ARFR4 (Offset 0x049C) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_ARFR4 0
-#define BIT_MASK_ARFR4 0xffffffffffffffffL
-#define BIT_ARFR4(x) (((x) & BIT_MASK_ARFR4) << BIT_SHIFT_ARFR4)
-#define BIT_GET_ARFR4(x) (((x) >> BIT_SHIFT_ARFR4) & BIT_MASK_ARFR4)
+/* 2 REG_CMDQ_INFO (Offset 0x0464) */
+#define BIT_SHIFT_HEAD_PKT_CMDQ_V1 0
+#define BIT_MASK_HEAD_PKT_CMDQ_V1 0x7ff
+#define BIT_HEAD_PKT_CMDQ_V1(x) \
+ (((x) & BIT_MASK_HEAD_PKT_CMDQ_V1) << BIT_SHIFT_HEAD_PKT_CMDQ_V1)
+#define BITS_HEAD_PKT_CMDQ_V1 \
+ (BIT_MASK_HEAD_PKT_CMDQ_V1 << BIT_SHIFT_HEAD_PKT_CMDQ_V1)
+#define BIT_CLEAR_HEAD_PKT_CMDQ_V1(x) ((x) & (~BITS_HEAD_PKT_CMDQ_V1))
+#define BIT_GET_HEAD_PKT_CMDQ_V1(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1) & BIT_MASK_HEAD_PKT_CMDQ_V1)
+#define BIT_SET_HEAD_PKT_CMDQ_V1(x, v) \
+ (BIT_CLEAR_HEAD_PKT_CMDQ_V1(x) | BIT_HEAD_PKT_CMDQ_V1(v))
-/* 2 REG_ARFR5 (Offset 0x04A4) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_ARFR5 0
-#define BIT_MASK_ARFR5 0xffffffffffffffffL
-#define BIT_ARFR5(x) (((x) & BIT_MASK_ARFR5) << BIT_SHIFT_ARFR5)
-#define BIT_GET_ARFR5(x) (((x) >> BIT_SHIFT_ARFR5) & BIT_MASK_ARFR5)
+/* 2 REG_NEW_EDCA_CTRL_V1 (Offset 0x0464) */
+#define BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER 0
+#define BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER 0xff
+#define BIT_MEDIUM_HAS_IDKE_TRIGGER(x) \
+ (((x) & BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER) \
+ << BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER)
+#define BITS_MEDIUM_HAS_IDKE_TRIGGER \
+ (BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER << BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER)
+#define BIT_CLEAR_MEDIUM_HAS_IDKE_TRIGGER(x) \
+ ((x) & (~BITS_MEDIUM_HAS_IDKE_TRIGGER))
+#define BIT_GET_MEDIUM_HAS_IDKE_TRIGGER(x) \
+ (((x) >> BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER) & \
+ BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER)
+#define BIT_SET_MEDIUM_HAS_IDKE_TRIGGER(x, v) \
+ (BIT_CLEAR_MEDIUM_HAS_IDKE_TRIGGER(x) | BIT_MEDIUM_HAS_IDKE_TRIGGER(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_Q4_INFO (Offset 0x0468) */
+#define BIT_SHIFT_QUEUEMACID_Q4_V1 25
+#define BIT_MASK_QUEUEMACID_Q4_V1 0x7f
+#define BIT_QUEUEMACID_Q4_V1(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q4_V1) << BIT_SHIFT_QUEUEMACID_Q4_V1)
+#define BITS_QUEUEMACID_Q4_V1 \
+ (BIT_MASK_QUEUEMACID_Q4_V1 << BIT_SHIFT_QUEUEMACID_Q4_V1)
+#define BIT_CLEAR_QUEUEMACID_Q4_V1(x) ((x) & (~BITS_QUEUEMACID_Q4_V1))
+#define BIT_GET_QUEUEMACID_Q4_V1(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1) & BIT_MASK_QUEUEMACID_Q4_V1)
+#define BIT_SET_QUEUEMACID_Q4_V1(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q4_V1(x) | BIT_QUEUEMACID_Q4_V1(v))
+
+#define BIT_SHIFT_QUEUEAC_Q4_V1 23
+#define BIT_MASK_QUEUEAC_Q4_V1 0x3
+#define BIT_QUEUEAC_Q4_V1(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q4_V1) << BIT_SHIFT_QUEUEAC_Q4_V1)
+#define BITS_QUEUEAC_Q4_V1 (BIT_MASK_QUEUEAC_Q4_V1 << BIT_SHIFT_QUEUEAC_Q4_V1)
+#define BIT_CLEAR_QUEUEAC_Q4_V1(x) ((x) & (~BITS_QUEUEAC_Q4_V1))
+#define BIT_GET_QUEUEAC_Q4_V1(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q4_V1) & BIT_MASK_QUEUEAC_Q4_V1)
+#define BIT_SET_QUEUEAC_Q4_V1(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q4_V1(x) | BIT_QUEUEAC_Q4_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */
+/* 2 REG_Q4_INFO (Offset 0x0468) */
-#define BIT_SHCUT_PARSE_DASA BIT(25)
+#define BIT_TIDEMPTY_Q4_V1 BIT(22)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_ACQ_STOP_V2 (Offset 0x0468) */
+#define BIT_AC19Q_STOP BIT(19)
+#define BIT_AC18Q_STOP BIT(18)
+#define BIT_AC17Q_STOP BIT(17)
+#define BIT_AC16Q_STOP BIT(16)
-/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_LOC_AMPDU_BURST_CTRL 24
-#define BIT_MASK_LOC_AMPDU_BURST_CTRL 0xff
-#define BIT_LOC_AMPDU_BURST_CTRL(x) (((x) & BIT_MASK_LOC_AMPDU_BURST_CTRL) << BIT_SHIFT_LOC_AMPDU_BURST_CTRL)
-#define BIT_GET_LOC_AMPDU_BURST_CTRL(x) (((x) >> BIT_SHIFT_LOC_AMPDU_BURST_CTRL) & BIT_MASK_LOC_AMPDU_BURST_CTRL)
+/* 2 REG_Q4_INFO (Offset 0x0468) */
+#define BIT_SHIFT_TAIL_PKT_Q4_V1 15
+#define BIT_MASK_TAIL_PKT_Q4_V1 0xff
+#define BIT_TAIL_PKT_Q4_V1(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q4_V1) << BIT_SHIFT_TAIL_PKT_Q4_V1)
+#define BITS_TAIL_PKT_Q4_V1 \
+ (BIT_MASK_TAIL_PKT_Q4_V1 << BIT_SHIFT_TAIL_PKT_Q4_V1)
+#define BIT_CLEAR_TAIL_PKT_Q4_V1(x) ((x) & (~BITS_TAIL_PKT_Q4_V1))
+#define BIT_GET_TAIL_PKT_Q4_V1(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V1) & BIT_MASK_TAIL_PKT_Q4_V1)
+#define BIT_SET_TAIL_PKT_Q4_V1(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q4_V1(x) | BIT_TAIL_PKT_Q4_V1(v))
#endif
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
+/* 2 REG_ACQ_STOP_V2 (Offset 0x0468) */
-/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */
-
-#define BIT_SHCUT_BYPASS BIT(24)
+#define BIT_AC15Q_STOP BIT(15)
+#define BIT_AC14Q_STOP BIT(14)
+#define BIT_AC13Q_STOP BIT(13)
+#define BIT_AC12Q_STOP BIT(12)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT)
+/* 2 REG_Q4_INFO (Offset 0x0468) */
+#define BIT_SHIFT_TAIL_PKT_Q4_V2 11
+#define BIT_MASK_TAIL_PKT_Q4_V2 0x7ff
+#define BIT_TAIL_PKT_Q4_V2(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q4_V2) << BIT_SHIFT_TAIL_PKT_Q4_V2)
+#define BITS_TAIL_PKT_Q4_V2 \
+ (BIT_MASK_TAIL_PKT_Q4_V2 << BIT_SHIFT_TAIL_PKT_Q4_V2)
+#define BIT_CLEAR_TAIL_PKT_Q4_V2(x) ((x) & (~BITS_TAIL_PKT_Q4_V2))
+#define BIT_GET_TAIL_PKT_Q4_V2(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2) & BIT_MASK_TAIL_PKT_Q4_V2)
+#define BIT_SET_TAIL_PKT_Q4_V2(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q4_V2(x) | BIT_TAIL_PKT_Q4_V2(v))
-/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */
+#endif
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_R_MUTAB_TXRPT_OFFSET 24
-#define BIT_MASK_R_MUTAB_TXRPT_OFFSET 0xff
-#define BIT_R_MUTAB_TXRPT_OFFSET(x) (((x) & BIT_MASK_R_MUTAB_TXRPT_OFFSET) << BIT_SHIFT_R_MUTAB_TXRPT_OFFSET)
-#define BIT_GET_R_MUTAB_TXRPT_OFFSET(x) (((x) >> BIT_SHIFT_R_MUTAB_TXRPT_OFFSET) & BIT_MASK_R_MUTAB_TXRPT_OFFSET)
+/* 2 REG_ACQ_STOP_V2 (Offset 0x0468) */
+#define BIT_AC11Q_STOP BIT(11)
+#define BIT_AC10Q_STOP BIT(10)
+#define BIT_AC9Q_STOP BIT(9)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8822B_SUPPORT)
+/* 2 REG_Q4_INFO (Offset 0x0468) */
+#define BIT_SHIFT_PKT_NUM_Q4_V1 8
+#define BIT_MASK_PKT_NUM_Q4_V1 0x7f
+#define BIT_PKT_NUM_Q4_V1(x) \
+ (((x) & BIT_MASK_PKT_NUM_Q4_V1) << BIT_SHIFT_PKT_NUM_Q4_V1)
+#define BITS_PKT_NUM_Q4_V1 (BIT_MASK_PKT_NUM_Q4_V1 << BIT_SHIFT_PKT_NUM_Q4_V1)
+#define BIT_CLEAR_PKT_NUM_Q4_V1(x) ((x) & (~BITS_PKT_NUM_Q4_V1))
+#define BIT_GET_PKT_NUM_Q4_V1(x) \
+ (((x) >> BIT_SHIFT_PKT_NUM_Q4_V1) & BIT_MASK_PKT_NUM_Q4_V1)
+#define BIT_SET_PKT_NUM_Q4_V1(x, v) \
+ (BIT_CLEAR_PKT_NUM_Q4_V1(x) | BIT_PKT_NUM_Q4_V1(v))
-/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */
+#endif
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_MACID_MURATE_OFFSET 24
-#define BIT_MASK_MACID_MURATE_OFFSET 0xff
-#define BIT_MACID_MURATE_OFFSET(x) (((x) & BIT_MASK_MACID_MURATE_OFFSET) << BIT_SHIFT_MACID_MURATE_OFFSET)
-#define BIT_GET_MACID_MURATE_OFFSET(x) (((x) >> BIT_SHIFT_MACID_MURATE_OFFSET) & BIT_MASK_MACID_MURATE_OFFSET)
+/* 2 REG_ACQ_STOP_V2 (Offset 0x0468) */
+#define BIT_AC8Q_STOP BIT(8)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_Q4_INFO (Offset 0x0468) */
-/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */
+#define BIT_SHIFT_HEAD_PKT_Q4 0
+#define BIT_MASK_HEAD_PKT_Q4 0xff
+#define BIT_HEAD_PKT_Q4(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q4) << BIT_SHIFT_HEAD_PKT_Q4)
+#define BITS_HEAD_PKT_Q4 (BIT_MASK_HEAD_PKT_Q4 << BIT_SHIFT_HEAD_PKT_Q4)
+#define BIT_CLEAR_HEAD_PKT_Q4(x) ((x) & (~BITS_HEAD_PKT_Q4))
+#define BIT_GET_HEAD_PKT_Q4(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q4) & BIT_MASK_HEAD_PKT_Q4)
+#define BIT_SET_HEAD_PKT_Q4(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q4(x) | BIT_HEAD_PKT_Q4(v))
+
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_LOC_BCN_RPT 16
-#define BIT_MASK_LOC_BCN_RPT 0xff
-#define BIT_LOC_BCN_RPT(x) (((x) & BIT_MASK_LOC_BCN_RPT) << BIT_SHIFT_LOC_BCN_RPT)
-#define BIT_GET_LOC_BCN_RPT(x) (((x) >> BIT_SHIFT_LOC_BCN_RPT) & BIT_MASK_LOC_BCN_RPT)
+/* 2 REG_Q4_INFO (Offset 0x0468) */
+#define BIT_SHIFT_HEAD_PKT_Q4_V1 0
+#define BIT_MASK_HEAD_PKT_Q4_V1 0x7ff
+#define BIT_HEAD_PKT_Q4_V1(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q4_V1) << BIT_SHIFT_HEAD_PKT_Q4_V1)
+#define BITS_HEAD_PKT_Q4_V1 \
+ (BIT_MASK_HEAD_PKT_Q4_V1 << BIT_SHIFT_HEAD_PKT_Q4_V1)
+#define BIT_CLEAR_HEAD_PKT_Q4_V1(x) ((x) & (~BITS_HEAD_PKT_Q4_V1))
+#define BIT_GET_HEAD_PKT_Q4_V1(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1) & BIT_MASK_HEAD_PKT_Q4_V1)
+#define BIT_SET_HEAD_PKT_Q4_V1(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q4_V1(x) | BIT_HEAD_PKT_Q4_V1(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+/* 2 REG_Q5_INFO (Offset 0x046C) */
+#define BIT_SHIFT_QUEUEMACID_Q5_V1 25
+#define BIT_MASK_QUEUEMACID_Q5_V1 0x7f
+#define BIT_QUEUEMACID_Q5_V1(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q5_V1) << BIT_SHIFT_QUEUEMACID_Q5_V1)
+#define BITS_QUEUEMACID_Q5_V1 \
+ (BIT_MASK_QUEUEMACID_Q5_V1 << BIT_SHIFT_QUEUEMACID_Q5_V1)
+#define BIT_CLEAR_QUEUEMACID_Q5_V1(x) ((x) & (~BITS_QUEUEMACID_Q5_V1))
+#define BIT_GET_QUEUEMACID_Q5_V1(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1) & BIT_MASK_QUEUEMACID_Q5_V1)
+#define BIT_SET_QUEUEMACID_Q5_V1(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q5_V1(x) | BIT_QUEUEMACID_Q5_V1(v))
+
+#define BIT_SHIFT_QUEUEAC_Q5_V1 23
+#define BIT_MASK_QUEUEAC_Q5_V1 0x3
+#define BIT_QUEUEAC_Q5_V1(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q5_V1) << BIT_SHIFT_QUEUEAC_Q5_V1)
+#define BITS_QUEUEAC_Q5_V1 (BIT_MASK_QUEUEAC_Q5_V1 << BIT_SHIFT_QUEUEAC_Q5_V1)
+#define BIT_CLEAR_QUEUEAC_Q5_V1(x) ((x) & (~BITS_QUEUEAC_Q5_V1))
+#define BIT_GET_QUEUEAC_Q5_V1(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q5_V1) & BIT_MASK_QUEUEAC_Q5_V1)
+#define BIT_SET_QUEUEAC_Q5_V1(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q5_V1(x) | BIT_QUEUEAC_Q5_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */
+/* 2 REG_Q5_INFO (Offset 0x046C) */
-#define BIT__R_RPTFIFO_1K BIT(16)
+#define BIT_TIDEMPTY_Q5_V1 BIT(22)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_Q5_INFO (Offset 0x046C) */
+#define BIT_SHIFT_TAIL_PKT_Q5_V1 15
+#define BIT_MASK_TAIL_PKT_Q5_V1 0xff
+#define BIT_TAIL_PKT_Q5_V1(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q5_V1) << BIT_SHIFT_TAIL_PKT_Q5_V1)
+#define BITS_TAIL_PKT_Q5_V1 \
+ (BIT_MASK_TAIL_PKT_Q5_V1 << BIT_SHIFT_TAIL_PKT_Q5_V1)
+#define BIT_CLEAR_TAIL_PKT_Q5_V1(x) ((x) & (~BITS_TAIL_PKT_Q5_V1))
+#define BIT_GET_TAIL_PKT_Q5_V1(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V1) & BIT_MASK_TAIL_PKT_Q5_V1)
+#define BIT_SET_TAIL_PKT_Q5_V1(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q5_V1(x) | BIT_TAIL_PKT_Q5_V1(v))
-/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_MACID_SHCUT_OFFSET 16
-#define BIT_MASK_MACID_SHCUT_OFFSET 0xff
-#define BIT_MACID_SHCUT_OFFSET(x) (((x) & BIT_MASK_MACID_SHCUT_OFFSET) << BIT_SHIFT_MACID_SHCUT_OFFSET)
-#define BIT_GET_MACID_SHCUT_OFFSET(x) (((x) >> BIT_SHIFT_MACID_SHCUT_OFFSET) & BIT_MASK_MACID_SHCUT_OFFSET)
+/* 2 REG_Q5_INFO (Offset 0x046C) */
+#define BIT_SHIFT_TAIL_PKT_Q5_V2 11
+#define BIT_MASK_TAIL_PKT_Q5_V2 0x7ff
+#define BIT_TAIL_PKT_Q5_V2(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q5_V2) << BIT_SHIFT_TAIL_PKT_Q5_V2)
+#define BITS_TAIL_PKT_Q5_V2 \
+ (BIT_MASK_TAIL_PKT_Q5_V2 << BIT_SHIFT_TAIL_PKT_Q5_V2)
+#define BIT_CLEAR_TAIL_PKT_Q5_V2(x) ((x) & (~BITS_TAIL_PKT_Q5_V2))
+#define BIT_GET_TAIL_PKT_Q5_V2(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2) & BIT_MASK_TAIL_PKT_Q5_V2)
+#define BIT_SET_TAIL_PKT_Q5_V2(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q5_V2(x) | BIT_TAIL_PKT_Q5_V2(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8822B_SUPPORT)
+/* 2 REG_Q5_INFO (Offset 0x046C) */
+#define BIT_SHIFT_PKT_NUM_Q5_V1 8
+#define BIT_MASK_PKT_NUM_Q5_V1 0x7f
+#define BIT_PKT_NUM_Q5_V1(x) \
+ (((x) & BIT_MASK_PKT_NUM_Q5_V1) << BIT_SHIFT_PKT_NUM_Q5_V1)
+#define BITS_PKT_NUM_Q5_V1 (BIT_MASK_PKT_NUM_Q5_V1 << BIT_SHIFT_PKT_NUM_Q5_V1)
+#define BIT_CLEAR_PKT_NUM_Q5_V1(x) ((x) & (~BITS_PKT_NUM_Q5_V1))
+#define BIT_GET_PKT_NUM_Q5_V1(x) \
+ (((x) >> BIT_SHIFT_PKT_NUM_Q5_V1) & BIT_MASK_PKT_NUM_Q5_V1)
+#define BIT_SET_PKT_NUM_Q5_V1(x, v) \
+ (BIT_CLEAR_PKT_NUM_Q5_V1(x) | BIT_PKT_NUM_Q5_V1(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q5 0
+#define BIT_MASK_HEAD_PKT_Q5 0xff
+#define BIT_HEAD_PKT_Q5(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q5) << BIT_SHIFT_HEAD_PKT_Q5)
+#define BITS_HEAD_PKT_Q5 (BIT_MASK_HEAD_PKT_Q5 << BIT_SHIFT_HEAD_PKT_Q5)
+#define BIT_CLEAR_HEAD_PKT_Q5(x) ((x) & (~BITS_HEAD_PKT_Q5))
+#define BIT_GET_HEAD_PKT_Q5(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q5) & BIT_MASK_HEAD_PKT_Q5)
+#define BIT_SET_HEAD_PKT_Q5(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q5(x) | BIT_HEAD_PKT_Q5(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */
+/* 2 REG_Q5_INFO (Offset 0x046C) */
-#define BIT_RPTFIFO_SIZE_OPT BIT(16)
+#define BIT_SHIFT_HEAD_PKT_Q5_V1 0
+#define BIT_MASK_HEAD_PKT_Q5_V1 0x7ff
+#define BIT_HEAD_PKT_Q5_V1(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q5_V1) << BIT_SHIFT_HEAD_PKT_Q5_V1)
+#define BITS_HEAD_PKT_Q5_V1 \
+ (BIT_MASK_HEAD_PKT_Q5_V1 << BIT_SHIFT_HEAD_PKT_Q5_V1)
+#define BIT_CLEAR_HEAD_PKT_Q5_V1(x) ((x) & (~BITS_HEAD_PKT_Q5_V1))
+#define BIT_GET_HEAD_PKT_Q5_V1(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1) & BIT_MASK_HEAD_PKT_Q5_V1)
+#define BIT_SET_HEAD_PKT_Q5_V1(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q5_V1(x) | BIT_HEAD_PKT_Q5_V1(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-
-/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */
+/* 2 REG_Q6_INFO (Offset 0x0470) */
+#define BIT_SHIFT_QUEUEMACID_Q6_V1 25
+#define BIT_MASK_QUEUEMACID_Q6_V1 0x7f
+#define BIT_QUEUEMACID_Q6_V1(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q6_V1) << BIT_SHIFT_QUEUEMACID_Q6_V1)
+#define BITS_QUEUEMACID_Q6_V1 \
+ (BIT_MASK_QUEUEMACID_Q6_V1 << BIT_SHIFT_QUEUEMACID_Q6_V1)
+#define BIT_CLEAR_QUEUEMACID_Q6_V1(x) ((x) & (~BITS_QUEUEMACID_Q6_V1))
+#define BIT_GET_QUEUEMACID_Q6_V1(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1) & BIT_MASK_QUEUEMACID_Q6_V1)
+#define BIT_SET_QUEUEMACID_Q6_V1(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q6_V1(x) | BIT_QUEUEMACID_Q6_V1(v))
+
+#define BIT_SHIFT_QUEUEAC_Q6_V1 23
+#define BIT_MASK_QUEUEAC_Q6_V1 0x3
+#define BIT_QUEUEAC_Q6_V1(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q6_V1) << BIT_SHIFT_QUEUEAC_Q6_V1)
+#define BITS_QUEUEAC_Q6_V1 (BIT_MASK_QUEUEAC_Q6_V1 << BIT_SHIFT_QUEUEAC_Q6_V1)
+#define BIT_CLEAR_QUEUEAC_Q6_V1(x) ((x) & (~BITS_QUEUEAC_Q6_V1))
+#define BIT_GET_QUEUEAC_Q6_V1(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q6_V1) & BIT_MASK_QUEUEAC_Q6_V1)
+#define BIT_SET_QUEUEAC_Q6_V1(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q6_V1(x) | BIT_QUEUEAC_Q6_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_LOC_TXRPT 8
-#define BIT_MASK_LOC_TXRPT 0xff
-#define BIT_LOC_TXRPT(x) (((x) & BIT_MASK_LOC_TXRPT) << BIT_SHIFT_LOC_TXRPT)
-#define BIT_GET_LOC_TXRPT(x) (((x) >> BIT_SHIFT_LOC_TXRPT) & BIT_MASK_LOC_TXRPT)
+/* 2 REG_Q6_INFO (Offset 0x0470) */
+#define BIT_TIDEMPTY_Q6_V1 BIT(22)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_Q6_INFO (Offset 0x0470) */
+#define BIT_SHIFT_TAIL_PKT_Q6_V1 15
+#define BIT_MASK_TAIL_PKT_Q6_V1 0xff
+#define BIT_TAIL_PKT_Q6_V1(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q6_V1) << BIT_SHIFT_TAIL_PKT_Q6_V1)
+#define BITS_TAIL_PKT_Q6_V1 \
+ (BIT_MASK_TAIL_PKT_Q6_V1 << BIT_SHIFT_TAIL_PKT_Q6_V1)
+#define BIT_CLEAR_TAIL_PKT_Q6_V1(x) ((x) & (~BITS_TAIL_PKT_Q6_V1))
+#define BIT_GET_TAIL_PKT_Q6_V1(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V1) & BIT_MASK_TAIL_PKT_Q6_V1)
+#define BIT_SET_TAIL_PKT_Q6_V1(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q6_V1(x) | BIT_TAIL_PKT_Q6_V1(v))
-/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_MACID_CTRL_OFFSET 8
-#define BIT_MASK_MACID_CTRL_OFFSET 0xff
-#define BIT_MACID_CTRL_OFFSET(x) (((x) & BIT_MASK_MACID_CTRL_OFFSET) << BIT_SHIFT_MACID_CTRL_OFFSET)
-#define BIT_GET_MACID_CTRL_OFFSET(x) (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET) & BIT_MASK_MACID_CTRL_OFFSET)
+/* 2 REG_Q6_INFO (Offset 0x0470) */
+#define BIT_SHIFT_TAIL_PKT_Q6_V2 11
+#define BIT_MASK_TAIL_PKT_Q6_V2 0x7ff
+#define BIT_TAIL_PKT_Q6_V2(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q6_V2) << BIT_SHIFT_TAIL_PKT_Q6_V2)
+#define BITS_TAIL_PKT_Q6_V2 \
+ (BIT_MASK_TAIL_PKT_Q6_V2 << BIT_SHIFT_TAIL_PKT_Q6_V2)
+#define BIT_CLEAR_TAIL_PKT_Q6_V2(x) ((x) & (~BITS_TAIL_PKT_Q6_V2))
+#define BIT_GET_TAIL_PKT_Q6_V2(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2) & BIT_MASK_TAIL_PKT_Q6_V2)
+#define BIT_SET_TAIL_PKT_Q6_V2(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q6_V2(x) | BIT_TAIL_PKT_Q6_V2(v))
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_Q6_INFO (Offset 0x0470) */
-/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */
-
+#define BIT_SHIFT_PKT_NUM_Q6_V1 8
+#define BIT_MASK_PKT_NUM_Q6_V1 0x7f
+#define BIT_PKT_NUM_Q6_V1(x) \
+ (((x) & BIT_MASK_PKT_NUM_Q6_V1) << BIT_SHIFT_PKT_NUM_Q6_V1)
+#define BITS_PKT_NUM_Q6_V1 (BIT_MASK_PKT_NUM_Q6_V1 << BIT_SHIFT_PKT_NUM_Q6_V1)
+#define BIT_CLEAR_PKT_NUM_Q6_V1(x) ((x) & (~BITS_PKT_NUM_Q6_V1))
+#define BIT_GET_PKT_NUM_Q6_V1(x) \
+ (((x) >> BIT_SHIFT_PKT_NUM_Q6_V1) & BIT_MASK_PKT_NUM_Q6_V1)
+#define BIT_SET_PKT_NUM_Q6_V1(x, v) \
+ (BIT_CLEAR_PKT_NUM_Q6_V1(x) | BIT_PKT_NUM_Q6_V1(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q6 0
+#define BIT_MASK_HEAD_PKT_Q6 0xff
+#define BIT_HEAD_PKT_Q6(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q6) << BIT_SHIFT_HEAD_PKT_Q6)
+#define BITS_HEAD_PKT_Q6 (BIT_MASK_HEAD_PKT_Q6 << BIT_SHIFT_HEAD_PKT_Q6)
+#define BIT_CLEAR_HEAD_PKT_Q6(x) ((x) & (~BITS_HEAD_PKT_Q6))
+#define BIT_GET_HEAD_PKT_Q6(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q6) & BIT_MASK_HEAD_PKT_Q6)
+#define BIT_SET_HEAD_PKT_Q6(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q6(x) | BIT_HEAD_PKT_Q6(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_LOC_SRFF 0
-#define BIT_MASK_LOC_SRFF 0xff
-#define BIT_LOC_SRFF(x) (((x) & BIT_MASK_LOC_SRFF) << BIT_SHIFT_LOC_SRFF)
-#define BIT_GET_LOC_SRFF(x) (((x) >> BIT_SHIFT_LOC_SRFF) & BIT_MASK_LOC_SRFF)
+/* 2 REG_Q6_INFO (Offset 0x0470) */
+#define BIT_SHIFT_HEAD_PKT_Q6_V1 0
+#define BIT_MASK_HEAD_PKT_Q6_V1 0x7ff
+#define BIT_HEAD_PKT_Q6_V1(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q6_V1) << BIT_SHIFT_HEAD_PKT_Q6_V1)
+#define BITS_HEAD_PKT_Q6_V1 \
+ (BIT_MASK_HEAD_PKT_Q6_V1 << BIT_SHIFT_HEAD_PKT_Q6_V1)
+#define BIT_CLEAR_HEAD_PKT_Q6_V1(x) ((x) & (~BITS_HEAD_PKT_Q6_V1))
+#define BIT_GET_HEAD_PKT_Q6_V1(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1) & BIT_MASK_HEAD_PKT_Q6_V1)
+#define BIT_SET_HEAD_PKT_Q6_V1(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q6_V1(x) | BIT_HEAD_PKT_Q6_V1(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */
+/* 2 REG_Q7_INFO (Offset 0x0474) */
+#define BIT_SHIFT_QUEUEMACID_Q7_V1 25
+#define BIT_MASK_QUEUEMACID_Q7_V1 0x7f
+#define BIT_QUEUEMACID_Q7_V1(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q7_V1) << BIT_SHIFT_QUEUEMACID_Q7_V1)
+#define BITS_QUEUEMACID_Q7_V1 \
+ (BIT_MASK_QUEUEMACID_Q7_V1 << BIT_SHIFT_QUEUEMACID_Q7_V1)
+#define BIT_CLEAR_QUEUEMACID_Q7_V1(x) ((x) & (~BITS_QUEUEMACID_Q7_V1))
+#define BIT_GET_QUEUEMACID_Q7_V1(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1) & BIT_MASK_QUEUEMACID_Q7_V1)
+#define BIT_SET_QUEUEMACID_Q7_V1(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q7_V1(x) | BIT_QUEUEMACID_Q7_V1(v))
+
+#define BIT_SHIFT_QUEUEAC_Q7_V1 23
+#define BIT_MASK_QUEUEAC_Q7_V1 0x3
+#define BIT_QUEUEAC_Q7_V1(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q7_V1) << BIT_SHIFT_QUEUEAC_Q7_V1)
+#define BITS_QUEUEAC_Q7_V1 (BIT_MASK_QUEUEAC_Q7_V1 << BIT_SHIFT_QUEUEAC_Q7_V1)
+#define BIT_CLEAR_QUEUEAC_Q7_V1(x) ((x) & (~BITS_QUEUEAC_Q7_V1))
+#define BIT_GET_QUEUEAC_Q7_V1(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q7_V1) & BIT_MASK_QUEUEAC_Q7_V1)
+#define BIT_SET_QUEUEAC_Q7_V1(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q7_V1(x) | BIT_QUEUEAC_Q7_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_AMPDU_TXRPT_OFFSET 0
-#define BIT_MASK_AMPDU_TXRPT_OFFSET 0xff
-#define BIT_AMPDU_TXRPT_OFFSET(x) (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET) << BIT_SHIFT_AMPDU_TXRPT_OFFSET)
-#define BIT_GET_AMPDU_TXRPT_OFFSET(x) (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET) & BIT_MASK_AMPDU_TXRPT_OFFSET)
+/* 2 REG_Q7_INFO (Offset 0x0474) */
+#define BIT_TIDEMPTY_Q7_V1 BIT(22)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_Q7_INFO (Offset 0x0474) */
-/* 2 REG_TRYING_CNT_TH (Offset 0x04B0) */
-
+#define BIT_SHIFT_TAIL_PKT_Q7_V1 15
+#define BIT_MASK_TAIL_PKT_Q7_V1 0xff
+#define BIT_TAIL_PKT_Q7_V1(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q7_V1) << BIT_SHIFT_TAIL_PKT_Q7_V1)
+#define BITS_TAIL_PKT_Q7_V1 \
+ (BIT_MASK_TAIL_PKT_Q7_V1 << BIT_SHIFT_TAIL_PKT_Q7_V1)
+#define BIT_CLEAR_TAIL_PKT_Q7_V1(x) ((x) & (~BITS_TAIL_PKT_Q7_V1))
+#define BIT_GET_TAIL_PKT_Q7_V1(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V1) & BIT_MASK_TAIL_PKT_Q7_V1)
+#define BIT_SET_TAIL_PKT_Q7_V1(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q7_V1(x) | BIT_TAIL_PKT_Q7_V1(v))
-#define BIT_SHIFT_INDEX_15 24
-#define BIT_MASK_INDEX_15 0xff
-#define BIT_INDEX_15(x) (((x) & BIT_MASK_INDEX_15) << BIT_SHIFT_INDEX_15)
-#define BIT_GET_INDEX_15(x) (((x) >> BIT_SHIFT_INDEX_15) & BIT_MASK_INDEX_15)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_INDEX_14 16
-#define BIT_MASK_INDEX_14 0xff
-#define BIT_INDEX_14(x) (((x) & BIT_MASK_INDEX_14) << BIT_SHIFT_INDEX_14)
-#define BIT_GET_INDEX_14(x) (((x) >> BIT_SHIFT_INDEX_14) & BIT_MASK_INDEX_14)
+/* 2 REG_Q7_INFO (Offset 0x0474) */
+#define BIT_SHIFT_TAIL_PKT_Q7_V2 11
+#define BIT_MASK_TAIL_PKT_Q7_V2 0x7ff
+#define BIT_TAIL_PKT_Q7_V2(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q7_V2) << BIT_SHIFT_TAIL_PKT_Q7_V2)
+#define BITS_TAIL_PKT_Q7_V2 \
+ (BIT_MASK_TAIL_PKT_Q7_V2 << BIT_SHIFT_TAIL_PKT_Q7_V2)
+#define BIT_CLEAR_TAIL_PKT_Q7_V2(x) ((x) & (~BITS_TAIL_PKT_Q7_V2))
+#define BIT_GET_TAIL_PKT_Q7_V2(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2) & BIT_MASK_TAIL_PKT_Q7_V2)
+#define BIT_SET_TAIL_PKT_Q7_V2(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q7_V2(x) | BIT_TAIL_PKT_Q7_V2(v))
-#define BIT_SHIFT_INDEX_13 8
-#define BIT_MASK_INDEX_13 0xff
-#define BIT_INDEX_13(x) (((x) & BIT_MASK_INDEX_13) << BIT_SHIFT_INDEX_13)
-#define BIT_GET_INDEX_13(x) (((x) >> BIT_SHIFT_INDEX_13) & BIT_MASK_INDEX_13)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_INDEX_12 0
-#define BIT_MASK_INDEX_12 0xff
-#define BIT_INDEX_12(x) (((x) & BIT_MASK_INDEX_12) << BIT_SHIFT_INDEX_12)
-#define BIT_GET_INDEX_12(x) (((x) >> BIT_SHIFT_INDEX_12) & BIT_MASK_INDEX_12)
+/* 2 REG_Q7_INFO (Offset 0x0474) */
+#define BIT_SHIFT_PKT_NUM_Q7_V1 8
+#define BIT_MASK_PKT_NUM_Q7_V1 0x7f
+#define BIT_PKT_NUM_Q7_V1(x) \
+ (((x) & BIT_MASK_PKT_NUM_Q7_V1) << BIT_SHIFT_PKT_NUM_Q7_V1)
+#define BITS_PKT_NUM_Q7_V1 (BIT_MASK_PKT_NUM_Q7_V1 << BIT_SHIFT_PKT_NUM_Q7_V1)
+#define BIT_CLEAR_PKT_NUM_Q7_V1(x) ((x) & (~BITS_PKT_NUM_Q7_V1))
+#define BIT_GET_PKT_NUM_Q7_V1(x) \
+ (((x) >> BIT_SHIFT_PKT_NUM_Q7_V1) & BIT_MASK_PKT_NUM_Q7_V1)
+#define BIT_SET_PKT_NUM_Q7_V1(x, v) \
+ (BIT_CLEAR_PKT_NUM_Q7_V1(x) | BIT_PKT_NUM_Q7_V1(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q7 0
+#define BIT_MASK_HEAD_PKT_Q7 0xff
+#define BIT_HEAD_PKT_Q7(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q7) << BIT_SHIFT_HEAD_PKT_Q7)
+#define BITS_HEAD_PKT_Q7 (BIT_MASK_HEAD_PKT_Q7 << BIT_SHIFT_HEAD_PKT_Q7)
+#define BIT_CLEAR_HEAD_PKT_Q7(x) ((x) & (~BITS_HEAD_PKT_Q7))
+#define BIT_GET_HEAD_PKT_Q7(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q7) & BIT_MASK_HEAD_PKT_Q7)
+#define BIT_SET_HEAD_PKT_Q7(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q7(x) | BIT_HEAD_PKT_Q7(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT 0
-#define BIT_MASK_RA_TRY_RATE_AGG_LMT 0x1f
-#define BIT_RA_TRY_RATE_AGG_LMT(x) (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT) << BIT_SHIFT_RA_TRY_RATE_AGG_LMT)
-#define BIT_GET_RA_TRY_RATE_AGG_LMT(x) (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT) & BIT_MASK_RA_TRY_RATE_AGG_LMT)
+/* 2 REG_Q7_INFO (Offset 0x0474) */
+#define BIT_SHIFT_HEAD_PKT_Q7_V1 0
+#define BIT_MASK_HEAD_PKT_Q7_V1 0x7ff
+#define BIT_HEAD_PKT_Q7_V1(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q7_V1) << BIT_SHIFT_HEAD_PKT_Q7_V1)
+#define BITS_HEAD_PKT_Q7_V1 \
+ (BIT_MASK_HEAD_PKT_Q7_V1 << BIT_SHIFT_HEAD_PKT_Q7_V1)
+#define BIT_CLEAR_HEAD_PKT_Q7_V1(x) ((x) & (~BITS_HEAD_PKT_Q7_V1))
+#define BIT_GET_HEAD_PKT_Q7_V1(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1) & BIT_MASK_HEAD_PKT_Q7_V1)
+#define BIT_SET_HEAD_PKT_Q7_V1(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q7_V1(x) | BIT_HEAD_PKT_Q7_V1(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_WMAC_LBK_BUF_HD_V1 (Offset 0x0478) */
+#define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1 0
+#define BIT_MASK_WMAC_LBK_BUF_HEAD_V1 0xfff
+#define BIT_WMAC_LBK_BUF_HEAD_V1(x) \
+ (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1) \
+ << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1)
+#define BITS_WMAC_LBK_BUF_HEAD_V1 \
+ (BIT_MASK_WMAC_LBK_BUF_HEAD_V1 << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1)
+#define BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1(x) ((x) & (~BITS_WMAC_LBK_BUF_HEAD_V1))
+#define BIT_GET_WMAC_LBK_BUF_HEAD_V1(x) \
+ (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1) & \
+ BIT_MASK_WMAC_LBK_BUF_HEAD_V1)
+#define BIT_SET_WMAC_LBK_BUF_HEAD_V1(x, v) \
+ (BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1(x) | BIT_WMAC_LBK_BUF_HEAD_V1(v))
-/* 2 REG_POWER_STAGE1 (Offset 0x04B4) */
+/* 2 REG_MGQ_BDNY_V1 (Offset 0x047A) */
-#define BIT_PTA_WL_PRI_MASK_CPU_MGQ BIT(31)
-#define BIT_PTA_WL_PRI_MASK_BCNQ BIT(30)
-#define BIT_PTA_WL_PRI_MASK_HIQ BIT(29)
-#define BIT_PTA_WL_PRI_MASK_MGQ BIT(28)
-#define BIT_PTA_WL_PRI_MASK_BK BIT(27)
-#define BIT_PTA_WL_PRI_MASK_BE BIT(26)
-#define BIT_PTA_WL_PRI_MASK_VI BIT(25)
-#define BIT_PTA_WL_PRI_MASK_VO BIT(24)
+#define BIT_SHIFT_MGQ_PGBNDY_V1 0
+#define BIT_MASK_MGQ_PGBNDY_V1 0xfff
+#define BIT_MGQ_PGBNDY_V1(x) \
+ (((x) & BIT_MASK_MGQ_PGBNDY_V1) << BIT_SHIFT_MGQ_PGBNDY_V1)
+#define BITS_MGQ_PGBNDY_V1 (BIT_MASK_MGQ_PGBNDY_V1 << BIT_SHIFT_MGQ_PGBNDY_V1)
+#define BIT_CLEAR_MGQ_PGBNDY_V1(x) ((x) & (~BITS_MGQ_PGBNDY_V1))
+#define BIT_GET_MGQ_PGBNDY_V1(x) \
+ (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1) & BIT_MASK_MGQ_PGBNDY_V1)
+#define BIT_SET_MGQ_PGBNDY_V1(x, v) \
+ (BIT_CLEAR_MGQ_PGBNDY_V1(x) | BIT_MGQ_PGBNDY_V1(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_TXRPT_CTRL (Offset 0x047C) */
+#define BIT_SHIFT_SPC_READ_PTR 24
+#define BIT_MASK_SPC_READ_PTR 0xf
+#define BIT_SPC_READ_PTR(x) \
+ (((x) & BIT_MASK_SPC_READ_PTR) << BIT_SHIFT_SPC_READ_PTR)
+#define BITS_SPC_READ_PTR (BIT_MASK_SPC_READ_PTR << BIT_SHIFT_SPC_READ_PTR)
+#define BIT_CLEAR_SPC_READ_PTR(x) ((x) & (~BITS_SPC_READ_PTR))
+#define BIT_GET_SPC_READ_PTR(x) \
+ (((x) >> BIT_SHIFT_SPC_READ_PTR) & BIT_MASK_SPC_READ_PTR)
+#define BIT_SET_SPC_READ_PTR(x, v) \
+ (BIT_CLEAR_SPC_READ_PTR(x) | BIT_SPC_READ_PTR(v))
-/* 2 REG_POWER_STAGE1 (Offset 0x04B4) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_POWER_STAGE1 0
-#define BIT_MASK_POWER_STAGE1 0xffffff
-#define BIT_POWER_STAGE1(x) (((x) & BIT_MASK_POWER_STAGE1) << BIT_SHIFT_POWER_STAGE1)
-#define BIT_GET_POWER_STAGE1(x) (((x) >> BIT_SHIFT_POWER_STAGE1) & BIT_MASK_POWER_STAGE1)
+/* 2 REG_TXRPT_CTRL (Offset 0x047C) */
+#define BIT_SHIFT_TRXRPT_TIMER_TH 24
+#define BIT_MASK_TRXRPT_TIMER_TH 0xff
+#define BIT_TRXRPT_TIMER_TH(x) \
+ (((x) & BIT_MASK_TRXRPT_TIMER_TH) << BIT_SHIFT_TRXRPT_TIMER_TH)
+#define BITS_TRXRPT_TIMER_TH \
+ (BIT_MASK_TRXRPT_TIMER_TH << BIT_SHIFT_TRXRPT_TIMER_TH)
+#define BIT_CLEAR_TRXRPT_TIMER_TH(x) ((x) & (~BITS_TRXRPT_TIMER_TH))
+#define BIT_GET_TRXRPT_TIMER_TH(x) \
+ (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH) & BIT_MASK_TRXRPT_TIMER_TH)
+#define BIT_SET_TRXRPT_TIMER_TH(x, v) \
+ (BIT_CLEAR_TRXRPT_TIMER_TH(x) | BIT_TRXRPT_TIMER_TH(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_TXRPT_CTRL (Offset 0x047C) */
+#define BIT_SHIFT_SPC_WRITE_PTR 16
+#define BIT_MASK_SPC_WRITE_PTR 0xf
+#define BIT_SPC_WRITE_PTR(x) \
+ (((x) & BIT_MASK_SPC_WRITE_PTR) << BIT_SHIFT_SPC_WRITE_PTR)
+#define BITS_SPC_WRITE_PTR (BIT_MASK_SPC_WRITE_PTR << BIT_SHIFT_SPC_WRITE_PTR)
+#define BIT_CLEAR_SPC_WRITE_PTR(x) ((x) & (~BITS_SPC_WRITE_PTR))
+#define BIT_GET_SPC_WRITE_PTR(x) \
+ (((x) >> BIT_SHIFT_SPC_WRITE_PTR) & BIT_MASK_SPC_WRITE_PTR)
+#define BIT_SET_SPC_WRITE_PTR(x, v) \
+ (BIT_CLEAR_SPC_WRITE_PTR(x) | BIT_SPC_WRITE_PTR(v))
-/* 2 REG_POWER_STAGE2 (Offset 0x04B8) */
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TXRPT_CTRL (Offset 0x047C) */
-#define BIT__R_CTRL_PKT_POW_ADJ BIT(24)
+#define BIT_SHIFT_TRXRPT_LEN_TH 16
+#define BIT_MASK_TRXRPT_LEN_TH 0xff
+#define BIT_TRXRPT_LEN_TH(x) \
+ (((x) & BIT_MASK_TRXRPT_LEN_TH) << BIT_SHIFT_TRXRPT_LEN_TH)
+#define BITS_TRXRPT_LEN_TH (BIT_MASK_TRXRPT_LEN_TH << BIT_SHIFT_TRXRPT_LEN_TH)
+#define BIT_CLEAR_TRXRPT_LEN_TH(x) ((x) & (~BITS_TRXRPT_LEN_TH))
+#define BIT_GET_TRXRPT_LEN_TH(x) \
+ (((x) >> BIT_SHIFT_TRXRPT_LEN_TH) & BIT_MASK_TRXRPT_LEN_TH)
+#define BIT_SET_TRXRPT_LEN_TH(x, v) \
+ (BIT_CLEAR_TRXRPT_LEN_TH(x) | BIT_TRXRPT_LEN_TH(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_TXRPT_CTRL (Offset 0x047C) */
+#define BIT_SHIFT_AC_READ_PTR 8
+#define BIT_MASK_AC_READ_PTR 0xf
+#define BIT_AC_READ_PTR(x) \
+ (((x) & BIT_MASK_AC_READ_PTR) << BIT_SHIFT_AC_READ_PTR)
+#define BITS_AC_READ_PTR (BIT_MASK_AC_READ_PTR << BIT_SHIFT_AC_READ_PTR)
+#define BIT_CLEAR_AC_READ_PTR(x) ((x) & (~BITS_AC_READ_PTR))
+#define BIT_GET_AC_READ_PTR(x) \
+ (((x) >> BIT_SHIFT_AC_READ_PTR) & BIT_MASK_AC_READ_PTR)
+#define BIT_SET_AC_READ_PTR(x, v) \
+ (BIT_CLEAR_AC_READ_PTR(x) | BIT_AC_READ_PTR(v))
-/* 2 REG_POWER_STAGE2 (Offset 0x04B8) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_POWER_STAGE2 0
-#define BIT_MASK_POWER_STAGE2 0xffffff
-#define BIT_POWER_STAGE2(x) (((x) & BIT_MASK_POWER_STAGE2) << BIT_SHIFT_POWER_STAGE2)
-#define BIT_GET_POWER_STAGE2(x) (((x) >> BIT_SHIFT_POWER_STAGE2) & BIT_MASK_POWER_STAGE2)
+/* 2 REG_TXRPT_CTRL (Offset 0x047C) */
+#define BIT_SHIFT_TRXRPT_READ_PTR 8
+#define BIT_MASK_TRXRPT_READ_PTR 0xff
+#define BIT_TRXRPT_READ_PTR(x) \
+ (((x) & BIT_MASK_TRXRPT_READ_PTR) << BIT_SHIFT_TRXRPT_READ_PTR)
+#define BITS_TRXRPT_READ_PTR \
+ (BIT_MASK_TRXRPT_READ_PTR << BIT_SHIFT_TRXRPT_READ_PTR)
+#define BIT_CLEAR_TRXRPT_READ_PTR(x) ((x) & (~BITS_TRXRPT_READ_PTR))
+#define BIT_GET_TRXRPT_READ_PTR(x) \
+ (((x) >> BIT_SHIFT_TRXRPT_READ_PTR) & BIT_MASK_TRXRPT_READ_PTR)
+#define BIT_SET_TRXRPT_READ_PTR(x, v) \
+ (BIT_CLEAR_TRXRPT_READ_PTR(x) | BIT_TRXRPT_READ_PTR(v))
-/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_PAD_NUM_THRES 24
-#define BIT_MASK_PAD_NUM_THRES 0x3f
-#define BIT_PAD_NUM_THRES(x) (((x) & BIT_MASK_PAD_NUM_THRES) << BIT_SHIFT_PAD_NUM_THRES)
-#define BIT_GET_PAD_NUM_THRES(x) (((x) >> BIT_SHIFT_PAD_NUM_THRES) & BIT_MASK_PAD_NUM_THRES)
+/* 2 REG_TXRPT_CTRL (Offset 0x047C) */
+#define BIT_SHIFT_AC_WRITE_PTR 0
+#define BIT_MASK_AC_WRITE_PTR 0xf
+#define BIT_AC_WRITE_PTR(x) \
+ (((x) & BIT_MASK_AC_WRITE_PTR) << BIT_SHIFT_AC_WRITE_PTR)
+#define BITS_AC_WRITE_PTR (BIT_MASK_AC_WRITE_PTR << BIT_SHIFT_AC_WRITE_PTR)
+#define BIT_CLEAR_AC_WRITE_PTR(x) ((x) & (~BITS_AC_WRITE_PTR))
+#define BIT_GET_AC_WRITE_PTR(x) \
+ (((x) >> BIT_SHIFT_AC_WRITE_PTR) & BIT_MASK_AC_WRITE_PTR)
+#define BIT_SET_AC_WRITE_PTR(x, v) \
+ (BIT_CLEAR_AC_WRITE_PTR(x) | BIT_AC_WRITE_PTR(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_TXRPT_CTRL (Offset 0x047C) */
+#define BIT_SHIFT_TRXRPT_WRITE_PTR 0
+#define BIT_MASK_TRXRPT_WRITE_PTR 0xff
+#define BIT_TRXRPT_WRITE_PTR(x) \
+ (((x) & BIT_MASK_TRXRPT_WRITE_PTR) << BIT_SHIFT_TRXRPT_WRITE_PTR)
+#define BITS_TRXRPT_WRITE_PTR \
+ (BIT_MASK_TRXRPT_WRITE_PTR << BIT_SHIFT_TRXRPT_WRITE_PTR)
+#define BIT_CLEAR_TRXRPT_WRITE_PTR(x) ((x) & (~BITS_TRXRPT_WRITE_PTR))
+#define BIT_GET_TRXRPT_WRITE_PTR(x) \
+ (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR) & BIT_MASK_TRXRPT_WRITE_PTR)
+#define BIT_SET_TRXRPT_WRITE_PTR(x, v) \
+ (BIT_CLEAR_TRXRPT_WRITE_PTR(x) | BIT_TRXRPT_WRITE_PTR(v))
-/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */
+#endif
-#define BIT_R_DMA_THIS_QUEUE_BK BIT(23)
-#define BIT_R_DMA_THIS_QUEUE_BE BIT(22)
-#define BIT_R_DMA_THIS_QUEUE_VI BIT(21)
-#define BIT_R_DMA_THIS_QUEUE_VO BIT(20)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_R_TOTAL_LEN_TH 8
-#define BIT_MASK_R_TOTAL_LEN_TH 0xfff
-#define BIT_R_TOTAL_LEN_TH(x) (((x) & BIT_MASK_R_TOTAL_LEN_TH) << BIT_SHIFT_R_TOTAL_LEN_TH)
-#define BIT_GET_R_TOTAL_LEN_TH(x) (((x) >> BIT_SHIFT_R_TOTAL_LEN_TH) & BIT_MASK_R_TOTAL_LEN_TH)
+/* 2 REG_INIRTS_RATE_SEL (Offset 0x0480) */
+#define BIT_LEAG_RTS_BW_DUP BIT(5)
-#endif
+/* 2 REG_BASIC_CFEND_RATE (Offset 0x0481) */
+
+#define BIT_SHIFT_BASIC_CFEND_RATE 0
+#define BIT_MASK_BASIC_CFEND_RATE 0x1f
+#define BIT_BASIC_CFEND_RATE(x) \
+ (((x) & BIT_MASK_BASIC_CFEND_RATE) << BIT_SHIFT_BASIC_CFEND_RATE)
+#define BITS_BASIC_CFEND_RATE \
+ (BIT_MASK_BASIC_CFEND_RATE << BIT_SHIFT_BASIC_CFEND_RATE)
+#define BIT_CLEAR_BASIC_CFEND_RATE(x) ((x) & (~BITS_BASIC_CFEND_RATE))
+#define BIT_GET_BASIC_CFEND_RATE(x) \
+ (((x) >> BIT_SHIFT_BASIC_CFEND_RATE) & BIT_MASK_BASIC_CFEND_RATE)
+#define BIT_SET_BASIC_CFEND_RATE(x, v) \
+ (BIT_CLEAR_BASIC_CFEND_RATE(x) | BIT_BASIC_CFEND_RATE(v))
+/* 2 REG_STBC_CFEND_RATE (Offset 0x0482) */
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#define BIT_SHIFT_STBC_CFEND_RATE 0
+#define BIT_MASK_STBC_CFEND_RATE 0x1f
+#define BIT_STBC_CFEND_RATE(x) \
+ (((x) & BIT_MASK_STBC_CFEND_RATE) << BIT_SHIFT_STBC_CFEND_RATE)
+#define BITS_STBC_CFEND_RATE \
+ (BIT_MASK_STBC_CFEND_RATE << BIT_SHIFT_STBC_CFEND_RATE)
+#define BIT_CLEAR_STBC_CFEND_RATE(x) ((x) & (~BITS_STBC_CFEND_RATE))
+#define BIT_GET_STBC_CFEND_RATE(x) \
+ (((x) >> BIT_SHIFT_STBC_CFEND_RATE) & BIT_MASK_STBC_CFEND_RATE)
+#define BIT_SET_STBC_CFEND_RATE(x, v) \
+ (BIT_CLEAR_STBC_CFEND_RATE(x) | BIT_STBC_CFEND_RATE(v))
+/* 2 REG_DATA_SC (Offset 0x0483) */
-/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */
+#define BIT_SHIFT_TXSC_40M 4
+#define BIT_MASK_TXSC_40M 0xf
+#define BIT_TXSC_40M(x) (((x) & BIT_MASK_TXSC_40M) << BIT_SHIFT_TXSC_40M)
+#define BITS_TXSC_40M (BIT_MASK_TXSC_40M << BIT_SHIFT_TXSC_40M)
+#define BIT_CLEAR_TXSC_40M(x) ((x) & (~BITS_TXSC_40M))
+#define BIT_GET_TXSC_40M(x) (((x) >> BIT_SHIFT_TXSC_40M) & BIT_MASK_TXSC_40M)
+#define BIT_SET_TXSC_40M(x, v) (BIT_CLEAR_TXSC_40M(x) | BIT_TXSC_40M(v))
-#define BIT_EN_NEW_EARLY BIT(7)
+#define BIT_SHIFT_TXSC_20M 0
+#define BIT_MASK_TXSC_20M 0xf
+#define BIT_TXSC_20M(x) (((x) & BIT_MASK_TXSC_20M) << BIT_SHIFT_TXSC_20M)
+#define BITS_TXSC_20M (BIT_MASK_TXSC_20M << BIT_SHIFT_TXSC_20M)
+#define BIT_CLEAR_TXSC_20M(x) ((x) & (~BITS_TXSC_20M))
+#define BIT_GET_TXSC_20M(x) (((x) >> BIT_SHIFT_TXSC_20M) & BIT_MASK_TXSC_20M)
+#define BIT_SET_TXSC_20M(x, v) (BIT_CLEAR_TXSC_20M(x) | BIT_TXSC_20M(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MACID_SLEEP3 (Offset 0x0484) */
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#define BIT_SHIFT_MACID127_96_PKTSLEEP 0
+#define BIT_MASK_MACID127_96_PKTSLEEP 0xffffffffL
+#define BIT_MACID127_96_PKTSLEEP(x) \
+ (((x) & BIT_MASK_MACID127_96_PKTSLEEP) \
+ << BIT_SHIFT_MACID127_96_PKTSLEEP)
+#define BITS_MACID127_96_PKTSLEEP \
+ (BIT_MASK_MACID127_96_PKTSLEEP << BIT_SHIFT_MACID127_96_PKTSLEEP)
+#define BIT_CLEAR_MACID127_96_PKTSLEEP(x) ((x) & (~BITS_MACID127_96_PKTSLEEP))
+#define BIT_GET_MACID127_96_PKTSLEEP(x) \
+ (((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP) & \
+ BIT_MASK_MACID127_96_PKTSLEEP)
+#define BIT_SET_MACID127_96_PKTSLEEP(x, v) \
+ (BIT_CLEAR_MACID127_96_PKTSLEEP(x) | BIT_MACID127_96_PKTSLEEP(v))
+#endif
-/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_PRE_TX_CMD BIT(6)
+/* 2 REG_DATA_SC1 (Offset 0x0487) */
-#define BIT_SHIFT_NUM_SCL_EN 4
-#define BIT_MASK_NUM_SCL_EN 0x3
-#define BIT_NUM_SCL_EN(x) (((x) & BIT_MASK_NUM_SCL_EN) << BIT_SHIFT_NUM_SCL_EN)
-#define BIT_GET_NUM_SCL_EN(x) (((x) >> BIT_SHIFT_NUM_SCL_EN) & BIT_MASK_NUM_SCL_EN)
+#define BIT_SHIFT_TXSC_160M 4
+#define BIT_MASK_TXSC_160M 0xf
+#define BIT_TXSC_160M(x) (((x) & BIT_MASK_TXSC_160M) << BIT_SHIFT_TXSC_160M)
+#define BITS_TXSC_160M (BIT_MASK_TXSC_160M << BIT_SHIFT_TXSC_160M)
+#define BIT_CLEAR_TXSC_160M(x) ((x) & (~BITS_TXSC_160M))
+#define BIT_GET_TXSC_160M(x) (((x) >> BIT_SHIFT_TXSC_160M) & BIT_MASK_TXSC_160M)
+#define BIT_SET_TXSC_160M(x, v) (BIT_CLEAR_TXSC_160M(x) | BIT_TXSC_160M(v))
-#define BIT_BK_EN BIT(3)
-#define BIT_BE_EN BIT(2)
-#define BIT_VI_EN BIT(1)
-#define BIT_VO_EN BIT(0)
+#define BIT_SHIFT_TXSC_80M 0
+#define BIT_MASK_TXSC_80M 0xf
+#define BIT_TXSC_80M(x) (((x) & BIT_MASK_TXSC_80M) << BIT_SHIFT_TXSC_80M)
+#define BITS_TXSC_80M (BIT_MASK_TXSC_80M << BIT_SHIFT_TXSC_80M)
+#define BIT_CLEAR_TXSC_80M(x) ((x) & (~BITS_TXSC_80M))
+#define BIT_GET_TXSC_80M(x) (((x) >> BIT_SHIFT_TXSC_80M) & BIT_MASK_TXSC_80M)
+#define BIT_SET_TXSC_80M(x, v) (BIT_CLEAR_TXSC_80M(x) | BIT_TXSC_80M(v))
-/* 2 REG_PKT_LIFE_TIME (Offset 0x04C0) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_PKT_LIFTIME_BEBK 16
-#define BIT_MASK_PKT_LIFTIME_BEBK 0xffff
-#define BIT_PKT_LIFTIME_BEBK(x) (((x) & BIT_MASK_PKT_LIFTIME_BEBK) << BIT_SHIFT_PKT_LIFTIME_BEBK)
-#define BIT_GET_PKT_LIFTIME_BEBK(x) (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK) & BIT_MASK_PKT_LIFTIME_BEBK)
+/* 2 REG_MACID_SLEEP1 (Offset 0x0488) */
+#define BIT_SHIFT_MACID63_32_PKTSLEEP 0
+#define BIT_MASK_MACID63_32_PKTSLEEP 0xffffffffL
+#define BIT_MACID63_32_PKTSLEEP(x) \
+ (((x) & BIT_MASK_MACID63_32_PKTSLEEP) << BIT_SHIFT_MACID63_32_PKTSLEEP)
+#define BITS_MACID63_32_PKTSLEEP \
+ (BIT_MASK_MACID63_32_PKTSLEEP << BIT_SHIFT_MACID63_32_PKTSLEEP)
+#define BIT_CLEAR_MACID63_32_PKTSLEEP(x) ((x) & (~BITS_MACID63_32_PKTSLEEP))
+#define BIT_GET_MACID63_32_PKTSLEEP(x) \
+ (((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP) & BIT_MASK_MACID63_32_PKTSLEEP)
+#define BIT_SET_MACID63_32_PKTSLEEP(x, v) \
+ (BIT_CLEAR_MACID63_32_PKTSLEEP(x) | BIT_MACID63_32_PKTSLEEP(v))
-#define BIT_SHIFT_PKT_LIFTIME_VOVI 0
-#define BIT_MASK_PKT_LIFTIME_VOVI 0xffff
-#define BIT_PKT_LIFTIME_VOVI(x) (((x) & BIT_MASK_PKT_LIFTIME_VOVI) << BIT_SHIFT_PKT_LIFTIME_VOVI)
-#define BIT_GET_PKT_LIFTIME_VOVI(x) (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI) & BIT_MASK_PKT_LIFTIME_VOVI)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-/* 2 REG_STBC_SETTING (Offset 0x04C4) */
+/* 2 REG_ARFR2_V1 (Offset 0x048C) */
+#define BIT_SHIFT_ARFR2_V1 0
+#define BIT_MASK_ARFR2_V1 0xffffffffffffffffL
+#define BIT_ARFR2_V1(x) (((x) & BIT_MASK_ARFR2_V1) << BIT_SHIFT_ARFR2_V1)
+#define BITS_ARFR2_V1 (BIT_MASK_ARFR2_V1 << BIT_SHIFT_ARFR2_V1)
+#define BIT_CLEAR_ARFR2_V1(x) ((x) & (~BITS_ARFR2_V1))
+#define BIT_GET_ARFR2_V1(x) (((x) >> BIT_SHIFT_ARFR2_V1) & BIT_MASK_ARFR2_V1)
+#define BIT_SET_ARFR2_V1(x, v) (BIT_CLEAR_ARFR2_V1(x) | BIT_ARFR2_V1(v))
-#define BIT_SHIFT_CDEND_TXTIME_L 4
-#define BIT_MASK_CDEND_TXTIME_L 0xf
-#define BIT_CDEND_TXTIME_L(x) (((x) & BIT_MASK_CDEND_TXTIME_L) << BIT_SHIFT_CDEND_TXTIME_L)
-#define BIT_GET_CDEND_TXTIME_L(x) (((x) >> BIT_SHIFT_CDEND_TXTIME_L) & BIT_MASK_CDEND_TXTIME_L)
+#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_NESS 2
-#define BIT_MASK_NESS 0x3
-#define BIT_NESS(x) (((x) & BIT_MASK_NESS) << BIT_SHIFT_NESS)
-#define BIT_GET_NESS(x) (((x) >> BIT_SHIFT_NESS) & BIT_MASK_NESS)
+/* 2 REG_ARFR2_V1 (Offset 0x048C) */
+#define BIT_SHIFT_ARFRL2 0
+#define BIT_MASK_ARFRL2 0xffffffffL
+#define BIT_ARFRL2(x) (((x) & BIT_MASK_ARFRL2) << BIT_SHIFT_ARFRL2)
+#define BITS_ARFRL2 (BIT_MASK_ARFRL2 << BIT_SHIFT_ARFRL2)
+#define BIT_CLEAR_ARFRL2(x) ((x) & (~BITS_ARFRL2))
+#define BIT_GET_ARFRL2(x) (((x) >> BIT_SHIFT_ARFRL2) & BIT_MASK_ARFRL2)
+#define BIT_SET_ARFRL2(x, v) (BIT_CLEAR_ARFRL2(x) | BIT_ARFRL2(v))
-#define BIT_SHIFT_STBC_CFEND 0
-#define BIT_MASK_STBC_CFEND 0x3
-#define BIT_STBC_CFEND(x) (((x) & BIT_MASK_STBC_CFEND) << BIT_SHIFT_STBC_CFEND)
-#define BIT_GET_STBC_CFEND(x) (((x) >> BIT_SHIFT_STBC_CFEND) & BIT_MASK_STBC_CFEND)
+/* 2 REG_ARFRH2_V1 (Offset 0x0490) */
+#define BIT_SHIFT_ARFRH2 0
+#define BIT_MASK_ARFRH2 0xffffffffL
+#define BIT_ARFRH2(x) (((x) & BIT_MASK_ARFRH2) << BIT_SHIFT_ARFRH2)
+#define BITS_ARFRH2 (BIT_MASK_ARFRH2 << BIT_SHIFT_ARFRH2)
+#define BIT_CLEAR_ARFRH2(x) ((x) & (~BITS_ARFRH2))
+#define BIT_GET_ARFRH2(x) (((x) >> BIT_SHIFT_ARFRH2) & BIT_MASK_ARFRH2)
+#define BIT_SET_ARFRH2(x, v) (BIT_CLEAR_ARFRH2(x) | BIT_ARFRH2(v))
-/* 2 REG_STBC_SETTING2 (Offset 0x04C5) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_CDEND_TXTIME_H 0
-#define BIT_MASK_CDEND_TXTIME_H 0x1f
-#define BIT_CDEND_TXTIME_H(x) (((x) & BIT_MASK_CDEND_TXTIME_H) << BIT_SHIFT_CDEND_TXTIME_H)
-#define BIT_GET_CDEND_TXTIME_H(x) (((x) >> BIT_SHIFT_CDEND_TXTIME_H) & BIT_MASK_CDEND_TXTIME_H)
+/* 2 REG_ARFR3_V1 (Offset 0x0494) */
+#define BIT_SHIFT_ARFR3_V1 0
+#define BIT_MASK_ARFR3_V1 0xffffffffffffffffL
+#define BIT_ARFR3_V1(x) (((x) & BIT_MASK_ARFR3_V1) << BIT_SHIFT_ARFR3_V1)
+#define BITS_ARFR3_V1 (BIT_MASK_ARFR3_V1 << BIT_SHIFT_ARFR3_V1)
+#define BIT_CLEAR_ARFR3_V1(x) ((x) & (~BITS_ARFR3_V1))
+#define BIT_GET_ARFR3_V1(x) (((x) >> BIT_SHIFT_ARFR3_V1) & BIT_MASK_ARFR3_V1)
+#define BIT_SET_ARFR3_V1(x, v) (BIT_CLEAR_ARFR3_V1(x) | BIT_ARFR3_V1(v))
#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ARFR3_V1 (Offset 0x0494) */
+#define BIT_SHIFT_ARFRL3 0
+#define BIT_MASK_ARFRL3 0xffffffffL
+#define BIT_ARFRL3(x) (((x) & BIT_MASK_ARFRL3) << BIT_SHIFT_ARFRL3)
+#define BITS_ARFRL3 (BIT_MASK_ARFRL3 << BIT_SHIFT_ARFRL3)
+#define BIT_CLEAR_ARFRL3(x) ((x) & (~BITS_ARFRL3))
+#define BIT_GET_ARFRL3(x) (((x) >> BIT_SHIFT_ARFRL3) & BIT_MASK_ARFRL3)
+#define BIT_SET_ARFRL3(x, v) (BIT_CLEAR_ARFRL3(x) | BIT_ARFRL3(v))
-/* 2 REG_QUEUE_CTRL (Offset 0x04C6) */
+/* 2 REG_ARFRH3_V1 (Offset 0x0498) */
-#define BIT_PTA_EDCCA_EN BIT(5)
-#define BIT_PTA_WL_TX_EN BIT(4)
+#define BIT_SHIFT_ARFRH3 0
+#define BIT_MASK_ARFRH3 0xffffffffL
+#define BIT_ARFRH3(x) (((x) & BIT_MASK_ARFRH3) << BIT_SHIFT_ARFRH3)
+#define BITS_ARFRH3 (BIT_MASK_ARFRH3 << BIT_SHIFT_ARFRH3)
+#define BIT_CLEAR_ARFRH3(x) ((x) & (~BITS_ARFRH3))
+#define BIT_GET_ARFRH3(x) (((x) >> BIT_SHIFT_ARFRH3) & BIT_MASK_ARFRH3)
+#define BIT_SET_ARFRH3(x, v) (BIT_CLEAR_ARFRH3(x) | BIT_ARFRH3(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+/* 2 REG_ARFR4 (Offset 0x049C) */
-/* 2 REG_QUEUE_CTRL (Offset 0x04C6) */
+#define BIT_SHIFT_ARFR4 0
+#define BIT_MASK_ARFR4 0xffffffffffffffffL
+#define BIT_ARFR4(x) (((x) & BIT_MASK_ARFR4) << BIT_SHIFT_ARFR4)
+#define BITS_ARFR4 (BIT_MASK_ARFR4 << BIT_SHIFT_ARFR4)
+#define BIT_CLEAR_ARFR4(x) ((x) & (~BITS_ARFR4))
+#define BIT_GET_ARFR4(x) (((x) >> BIT_SHIFT_ARFR4) & BIT_MASK_ARFR4)
+#define BIT_SET_ARFR4(x, v) (BIT_CLEAR_ARFR4(x) | BIT_ARFR4(v))
-#define BIT_R_USE_DATA_BW BIT(3)
-#define BIT_TRI_PKT_INT_MODE1 BIT(2)
-#define BIT_TRI_PKT_INT_MODE0 BIT(1)
-#define BIT_ACQ_MODE_SEL BIT(0)
+#endif
-/* 2 REG_SINGLE_AMPDU_CTRL (Offset 0x04C7) */
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_EN_SINGLE_APMDU BIT(7)
+/* 2 REG_ARFR4 (Offset 0x049C) */
-/* 2 REG_PROT_MODE_CTRL (Offset 0x04C8) */
+#define BIT_SHIFT_ARFRL4 0
+#define BIT_MASK_ARFRL4 0xffffffffL
+#define BIT_ARFRL4(x) (((x) & BIT_MASK_ARFRL4) << BIT_SHIFT_ARFRL4)
+#define BITS_ARFRL4 (BIT_MASK_ARFRL4 << BIT_SHIFT_ARFRL4)
+#define BIT_CLEAR_ARFRL4(x) ((x) & (~BITS_ARFRL4))
+#define BIT_GET_ARFRL4(x) (((x) >> BIT_SHIFT_ARFRL4) & BIT_MASK_ARFRL4)
+#define BIT_SET_ARFRL4(x, v) (BIT_CLEAR_ARFRL4(x) | BIT_ARFRL4(v))
+/* 2 REG_ARFRH4 (Offset 0x04A0) */
-#define BIT_SHIFT_RTS_MAX_AGG_NUM 24
-#define BIT_MASK_RTS_MAX_AGG_NUM 0x3f
-#define BIT_RTS_MAX_AGG_NUM(x) (((x) & BIT_MASK_RTS_MAX_AGG_NUM) << BIT_SHIFT_RTS_MAX_AGG_NUM)
-#define BIT_GET_RTS_MAX_AGG_NUM(x) (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM) & BIT_MASK_RTS_MAX_AGG_NUM)
+#define BIT_SHIFT_ARFRH4 0
+#define BIT_MASK_ARFRH4 0xffffffffL
+#define BIT_ARFRH4(x) (((x) & BIT_MASK_ARFRH4) << BIT_SHIFT_ARFRH4)
+#define BITS_ARFRH4 (BIT_MASK_ARFRH4 << BIT_SHIFT_ARFRH4)
+#define BIT_CLEAR_ARFRH4(x) ((x) & (~BITS_ARFRH4))
+#define BIT_GET_ARFRH4(x) (((x) >> BIT_SHIFT_ARFRH4) & BIT_MASK_ARFRH4)
+#define BIT_SET_ARFRH4(x, v) (BIT_CLEAR_ARFRH4(x) | BIT_ARFRH4(v))
+#endif
-#define BIT_SHIFT_MAX_AGG_NUM 16
-#define BIT_MASK_MAX_AGG_NUM 0x3f
-#define BIT_MAX_AGG_NUM(x) (((x) & BIT_MASK_MAX_AGG_NUM) << BIT_SHIFT_MAX_AGG_NUM)
-#define BIT_GET_MAX_AGG_NUM(x) (((x) >> BIT_SHIFT_MAX_AGG_NUM) & BIT_MASK_MAX_AGG_NUM)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+/* 2 REG_ARFR5 (Offset 0x04A4) */
-#define BIT_SHIFT_RTS_TXTIME_TH 8
-#define BIT_MASK_RTS_TXTIME_TH 0xff
-#define BIT_RTS_TXTIME_TH(x) (((x) & BIT_MASK_RTS_TXTIME_TH) << BIT_SHIFT_RTS_TXTIME_TH)
-#define BIT_GET_RTS_TXTIME_TH(x) (((x) >> BIT_SHIFT_RTS_TXTIME_TH) & BIT_MASK_RTS_TXTIME_TH)
+#define BIT_SHIFT_ARFR5 0
+#define BIT_MASK_ARFR5 0xffffffffffffffffL
+#define BIT_ARFR5(x) (((x) & BIT_MASK_ARFR5) << BIT_SHIFT_ARFR5)
+#define BITS_ARFR5 (BIT_MASK_ARFR5 << BIT_SHIFT_ARFR5)
+#define BIT_CLEAR_ARFR5(x) ((x) & (~BITS_ARFR5))
+#define BIT_GET_ARFR5(x) (((x) >> BIT_SHIFT_ARFR5) & BIT_MASK_ARFR5)
+#define BIT_SET_ARFR5(x, v) (BIT_CLEAR_ARFR5(x) | BIT_ARFR5(v))
+#endif
-#define BIT_SHIFT_RTS_LEN_TH 0
-#define BIT_MASK_RTS_LEN_TH 0xff
-#define BIT_RTS_LEN_TH(x) (((x) & BIT_MASK_RTS_LEN_TH) << BIT_SHIFT_RTS_LEN_TH)
-#define BIT_GET_RTS_LEN_TH(x) (((x) >> BIT_SHIFT_RTS_LEN_TH) & BIT_MASK_RTS_LEN_TH)
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+/* 2 REG_ARFR5 (Offset 0x04A4) */
-/* 2 REG_BAR_MODE_CTRL (Offset 0x04CC) */
+#define BIT_SHIFT_ARFRL5 0
+#define BIT_MASK_ARFRL5 0xffffffffL
+#define BIT_ARFRL5(x) (((x) & BIT_MASK_ARFRL5) << BIT_SHIFT_ARFRL5)
+#define BITS_ARFRL5 (BIT_MASK_ARFRL5 << BIT_SHIFT_ARFRL5)
+#define BIT_CLEAR_ARFRL5(x) ((x) & (~BITS_ARFRL5))
+#define BIT_GET_ARFRL5(x) (((x) >> BIT_SHIFT_ARFRL5) & BIT_MASK_ARFRL5)
+#define BIT_SET_ARFRL5(x, v) (BIT_CLEAR_ARFRL5(x) | BIT_ARFRL5(v))
+/* 2 REG_ARFRH5 (Offset 0x04A8) */
-#define BIT_SHIFT_BAR_RTY_LMT 16
-#define BIT_MASK_BAR_RTY_LMT 0x3
-#define BIT_BAR_RTY_LMT(x) (((x) & BIT_MASK_BAR_RTY_LMT) << BIT_SHIFT_BAR_RTY_LMT)
-#define BIT_GET_BAR_RTY_LMT(x) (((x) >> BIT_SHIFT_BAR_RTY_LMT) & BIT_MASK_BAR_RTY_LMT)
+#define BIT_SHIFT_ARFRH5 0
+#define BIT_MASK_ARFRH5 0xffffffffL
+#define BIT_ARFRH5(x) (((x) & BIT_MASK_ARFRH5) << BIT_SHIFT_ARFRH5)
+#define BITS_ARFRH5 (BIT_MASK_ARFRH5 << BIT_SHIFT_ARFRH5)
+#define BIT_CLEAR_ARFRH5(x) ((x) & (~BITS_ARFRH5))
+#define BIT_GET_ARFRH5(x) (((x) >> BIT_SHIFT_ARFRH5) & BIT_MASK_ARFRH5)
+#define BIT_SET_ARFRH5(x, v) (BIT_CLEAR_ARFRH5(x) | BIT_ARFRH5(v))
+#endif
-#define BIT_SHIFT_BAR_PKT_TXTIME_TH 8
-#define BIT_MASK_BAR_PKT_TXTIME_TH 0xff
-#define BIT_BAR_PKT_TXTIME_TH(x) (((x) & BIT_MASK_BAR_PKT_TXTIME_TH) << BIT_SHIFT_BAR_PKT_TXTIME_TH)
-#define BIT_GET_BAR_PKT_TXTIME_TH(x) (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH) & BIT_MASK_BAR_PKT_TXTIME_TH)
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_BAR_EN_V1 BIT(6)
+/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */
-#define BIT_SHIFT_BAR_PKTNUM_TH_V1 0
-#define BIT_MASK_BAR_PKTNUM_TH_V1 0x3f
-#define BIT_BAR_PKTNUM_TH_V1(x) (((x) & BIT_MASK_BAR_PKTNUM_TH_V1) << BIT_SHIFT_BAR_PKTNUM_TH_V1)
-#define BIT_GET_BAR_PKTNUM_TH_V1(x) (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1) & BIT_MASK_BAR_PKTNUM_TH_V1)
+#define BIT_RPTFIFO_RPTNUM_OPT BIT(31)
+#define BIT_SHIFT_MISSED_RPT_NUM 28
+#define BIT_MASK_MISSED_RPT_NUM 0x7
+#define BIT_MISSED_RPT_NUM(x) \
+ (((x) & BIT_MASK_MISSED_RPT_NUM) << BIT_SHIFT_MISSED_RPT_NUM)
+#define BITS_MISSED_RPT_NUM \
+ (BIT_MASK_MISSED_RPT_NUM << BIT_SHIFT_MISSED_RPT_NUM)
+#define BIT_CLEAR_MISSED_RPT_NUM(x) ((x) & (~BITS_MISSED_RPT_NUM))
+#define BIT_GET_MISSED_RPT_NUM(x) \
+ (((x) >> BIT_SHIFT_MISSED_RPT_NUM) & BIT_MASK_MISSED_RPT_NUM)
+#define BIT_SET_MISSED_RPT_NUM(x, v) \
+ (BIT_CLEAR_MISSED_RPT_NUM(x) | BIT_MISSED_RPT_NUM(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */
+#define BIT_SHCUT_PARSE_DASA BIT(25)
-/* 2 REG_RA_TRY_RATE_AGG_LMT (Offset 0x04CF) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1 0
-#define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1 0x3f
-#define BIT_RA_TRY_RATE_AGG_LMT_V1(x) (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1) << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1)
-#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1(x) (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1)
+/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */
+#define BIT_SHIFT_LOC_AMPDU_BURST_CTRL 24
+#define BIT_MASK_LOC_AMPDU_BURST_CTRL 0xff
+#define BIT_LOC_AMPDU_BURST_CTRL(x) \
+ (((x) & BIT_MASK_LOC_AMPDU_BURST_CTRL) \
+ << BIT_SHIFT_LOC_AMPDU_BURST_CTRL)
+#define BITS_LOC_AMPDU_BURST_CTRL \
+ (BIT_MASK_LOC_AMPDU_BURST_CTRL << BIT_SHIFT_LOC_AMPDU_BURST_CTRL)
+#define BIT_CLEAR_LOC_AMPDU_BURST_CTRL(x) ((x) & (~BITS_LOC_AMPDU_BURST_CTRL))
+#define BIT_GET_LOC_AMPDU_BURST_CTRL(x) \
+ (((x) >> BIT_SHIFT_LOC_AMPDU_BURST_CTRL) & \
+ BIT_MASK_LOC_AMPDU_BURST_CTRL)
+#define BIT_SET_LOC_AMPDU_BURST_CTRL(x, v) \
+ (BIT_CLEAR_LOC_AMPDU_BURST_CTRL(x) | BIT_LOC_AMPDU_BURST_CTRL(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */
+#define BIT_SHCUT_BYPASS BIT(24)
-/* 2 REG_MACID_SLEEP2 (Offset 0x04D0) */
+#endif
+#if (HALMAC_8821C_SUPPORT)
-#define BIT_SHIFT_MACID95_64PKTSLEEP 0
-#define BIT_MASK_MACID95_64PKTSLEEP 0xffffffffL
-#define BIT_MACID95_64PKTSLEEP(x) (((x) & BIT_MASK_MACID95_64PKTSLEEP) << BIT_SHIFT_MACID95_64PKTSLEEP)
-#define BIT_GET_MACID95_64PKTSLEEP(x) (((x) >> BIT_SHIFT_MACID95_64PKTSLEEP) & BIT_MASK_MACID95_64PKTSLEEP)
+/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */
+#define BIT_SHIFT_R_MUTAB_TXRPT_OFFSET 24
+#define BIT_MASK_R_MUTAB_TXRPT_OFFSET 0xff
+#define BIT_R_MUTAB_TXRPT_OFFSET(x) \
+ (((x) & BIT_MASK_R_MUTAB_TXRPT_OFFSET) \
+ << BIT_SHIFT_R_MUTAB_TXRPT_OFFSET)
+#define BITS_R_MUTAB_TXRPT_OFFSET \
+ (BIT_MASK_R_MUTAB_TXRPT_OFFSET << BIT_SHIFT_R_MUTAB_TXRPT_OFFSET)
+#define BIT_CLEAR_R_MUTAB_TXRPT_OFFSET(x) ((x) & (~BITS_R_MUTAB_TXRPT_OFFSET))
+#define BIT_GET_R_MUTAB_TXRPT_OFFSET(x) \
+ (((x) >> BIT_SHIFT_R_MUTAB_TXRPT_OFFSET) & \
+ BIT_MASK_R_MUTAB_TXRPT_OFFSET)
+#define BIT_SET_R_MUTAB_TXRPT_OFFSET(x, v) \
+ (BIT_CLEAR_R_MUTAB_TXRPT_OFFSET(x) | BIT_R_MUTAB_TXRPT_OFFSET(v))
-/* 2 REG_MACID_SLEEP (Offset 0x04D4) */
+#endif
+#if (HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_MACID31_0_PKTSLEEP 0
-#define BIT_MASK_MACID31_0_PKTSLEEP 0xffffffffL
-#define BIT_MACID31_0_PKTSLEEP(x) (((x) & BIT_MASK_MACID31_0_PKTSLEEP) << BIT_SHIFT_MACID31_0_PKTSLEEP)
-#define BIT_GET_MACID31_0_PKTSLEEP(x) (((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP) & BIT_MASK_MACID31_0_PKTSLEEP)
+/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */
+#define BIT_SHIFT_MACID_MURATE_OFFSET 24
+#define BIT_MASK_MACID_MURATE_OFFSET 0xff
+#define BIT_MACID_MURATE_OFFSET(x) \
+ (((x) & BIT_MASK_MACID_MURATE_OFFSET) << BIT_SHIFT_MACID_MURATE_OFFSET)
+#define BITS_MACID_MURATE_OFFSET \
+ (BIT_MASK_MACID_MURATE_OFFSET << BIT_SHIFT_MACID_MURATE_OFFSET)
+#define BIT_CLEAR_MACID_MURATE_OFFSET(x) ((x) & (~BITS_MACID_MURATE_OFFSET))
+#define BIT_GET_MACID_MURATE_OFFSET(x) \
+ (((x) >> BIT_SHIFT_MACID_MURATE_OFFSET) & BIT_MASK_MACID_MURATE_OFFSET)
+#define BIT_SET_MACID_MURATE_OFFSET(x, v) \
+ (BIT_CLEAR_MACID_MURATE_OFFSET(x) | BIT_MACID_MURATE_OFFSET(v))
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */
+#define BIT_SHIFT_TXRPT_MISS_COUNT 17
+#define BIT_MASK_TXRPT_MISS_COUNT 0x7
+#define BIT_TXRPT_MISS_COUNT(x) \
+ (((x) & BIT_MASK_TXRPT_MISS_COUNT) << BIT_SHIFT_TXRPT_MISS_COUNT)
+#define BITS_TXRPT_MISS_COUNT \
+ (BIT_MASK_TXRPT_MISS_COUNT << BIT_SHIFT_TXRPT_MISS_COUNT)
+#define BIT_CLEAR_TXRPT_MISS_COUNT(x) ((x) & (~BITS_TXRPT_MISS_COUNT))
+#define BIT_GET_TXRPT_MISS_COUNT(x) \
+ (((x) >> BIT_SHIFT_TXRPT_MISS_COUNT) & BIT_MASK_TXRPT_MISS_COUNT)
+#define BIT_SET_TXRPT_MISS_COUNT(x, v) \
+ (BIT_CLEAR_TXRPT_MISS_COUNT(x) | BIT_TXRPT_MISS_COUNT(v))
-/* 2 REG_HW_SEQ0 (Offset 0x04D8) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_HW_SSN_SEQ0 0
-#define BIT_MASK_HW_SSN_SEQ0 0xfff
-#define BIT_HW_SSN_SEQ0(x) (((x) & BIT_MASK_HW_SSN_SEQ0) << BIT_SHIFT_HW_SSN_SEQ0)
-#define BIT_GET_HW_SSN_SEQ0(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ0) & BIT_MASK_HW_SSN_SEQ0)
+/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */
+#define BIT_SHIFT_LOC_BCN_RPT 16
+#define BIT_MASK_LOC_BCN_RPT 0xff
+#define BIT_LOC_BCN_RPT(x) \
+ (((x) & BIT_MASK_LOC_BCN_RPT) << BIT_SHIFT_LOC_BCN_RPT)
+#define BITS_LOC_BCN_RPT (BIT_MASK_LOC_BCN_RPT << BIT_SHIFT_LOC_BCN_RPT)
+#define BIT_CLEAR_LOC_BCN_RPT(x) ((x) & (~BITS_LOC_BCN_RPT))
+#define BIT_GET_LOC_BCN_RPT(x) \
+ (((x) >> BIT_SHIFT_LOC_BCN_RPT) & BIT_MASK_LOC_BCN_RPT)
+#define BIT_SET_LOC_BCN_RPT(x, v) \
+ (BIT_CLEAR_LOC_BCN_RPT(x) | BIT_LOC_BCN_RPT(v))
-/* 2 REG_HW_SEQ1 (Offset 0x04DA) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT)
-#define BIT_SHIFT_HW_SSN_SEQ1 0
-#define BIT_MASK_HW_SSN_SEQ1 0xfff
-#define BIT_HW_SSN_SEQ1(x) (((x) & BIT_MASK_HW_SSN_SEQ1) << BIT_SHIFT_HW_SSN_SEQ1)
-#define BIT_GET_HW_SSN_SEQ1(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ1) & BIT_MASK_HW_SSN_SEQ1)
+/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */
+#define BIT__R_RPTFIFO_1K BIT(16)
-/* 2 REG_HW_SEQ2 (Offset 0x04DC) */
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define BIT_SHIFT_HW_SSN_SEQ2 0
-#define BIT_MASK_HW_SSN_SEQ2 0xfff
-#define BIT_HW_SSN_SEQ2(x) (((x) & BIT_MASK_HW_SSN_SEQ2) << BIT_SHIFT_HW_SSN_SEQ2)
-#define BIT_GET_HW_SSN_SEQ2(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ2) & BIT_MASK_HW_SSN_SEQ2)
+/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */
+#define BIT_SHIFT_MACID_SHCUT_OFFSET 16
+#define BIT_MASK_MACID_SHCUT_OFFSET 0xff
+#define BIT_MACID_SHCUT_OFFSET(x) \
+ (((x) & BIT_MASK_MACID_SHCUT_OFFSET) << BIT_SHIFT_MACID_SHCUT_OFFSET)
+#define BITS_MACID_SHCUT_OFFSET \
+ (BIT_MASK_MACID_SHCUT_OFFSET << BIT_SHIFT_MACID_SHCUT_OFFSET)
+#define BIT_CLEAR_MACID_SHCUT_OFFSET(x) ((x) & (~BITS_MACID_SHCUT_OFFSET))
+#define BIT_GET_MACID_SHCUT_OFFSET(x) \
+ (((x) >> BIT_SHIFT_MACID_SHCUT_OFFSET) & BIT_MASK_MACID_SHCUT_OFFSET)
+#define BIT_SET_MACID_SHCUT_OFFSET(x, v) \
+ (BIT_CLEAR_MACID_SHCUT_OFFSET(x) | BIT_MACID_SHCUT_OFFSET(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */
+#define BIT_SHIFT_MACID_CTRL_OFFSET_V1 16
+#define BIT_MASK_MACID_CTRL_OFFSET_V1 0x1ff
+#define BIT_MACID_CTRL_OFFSET_V1(x) \
+ (((x) & BIT_MASK_MACID_CTRL_OFFSET_V1) \
+ << BIT_SHIFT_MACID_CTRL_OFFSET_V1)
+#define BITS_MACID_CTRL_OFFSET_V1 \
+ (BIT_MASK_MACID_CTRL_OFFSET_V1 << BIT_SHIFT_MACID_CTRL_OFFSET_V1)
+#define BIT_CLEAR_MACID_CTRL_OFFSET_V1(x) ((x) & (~BITS_MACID_CTRL_OFFSET_V1))
+#define BIT_GET_MACID_CTRL_OFFSET_V1(x) \
+ (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_V1) & \
+ BIT_MASK_MACID_CTRL_OFFSET_V1)
+#define BIT_SET_MACID_CTRL_OFFSET_V1(x, v) \
+ (BIT_CLEAR_MACID_CTRL_OFFSET_V1(x) | BIT_MACID_CTRL_OFFSET_V1(v))
-/* 2 REG_HW_SEQ3 (Offset 0x04DE) */
+#endif
+#if (HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_CSI_HWSSN_SEL 12
-#define BIT_MASK_CSI_HWSSN_SEL 0x3
-#define BIT_CSI_HWSSN_SEL(x) (((x) & BIT_MASK_CSI_HWSSN_SEL) << BIT_SHIFT_CSI_HWSSN_SEL)
-#define BIT_GET_CSI_HWSSN_SEL(x) (((x) >> BIT_SHIFT_CSI_HWSSN_SEL) & BIT_MASK_CSI_HWSSN_SEL)
+/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */
+#define BIT_RPTFIFO_SIZE_OPT BIT(16)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */
+#define BIT_SHIFT_LOC_TXRPT 8
+#define BIT_MASK_LOC_TXRPT 0xff
+#define BIT_LOC_TXRPT(x) (((x) & BIT_MASK_LOC_TXRPT) << BIT_SHIFT_LOC_TXRPT)
+#define BITS_LOC_TXRPT (BIT_MASK_LOC_TXRPT << BIT_SHIFT_LOC_TXRPT)
+#define BIT_CLEAR_LOC_TXRPT(x) ((x) & (~BITS_LOC_TXRPT))
+#define BIT_GET_LOC_TXRPT(x) (((x) >> BIT_SHIFT_LOC_TXRPT) & BIT_MASK_LOC_TXRPT)
+#define BIT_SET_LOC_TXRPT(x, v) (BIT_CLEAR_LOC_TXRPT(x) | BIT_LOC_TXRPT(v))
-/* 2 REG_HW_SEQ3 (Offset 0x04DE) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_HW_SSN_SEQ3 0
-#define BIT_MASK_HW_SSN_SEQ3 0xfff
-#define BIT_HW_SSN_SEQ3(x) (((x) & BIT_MASK_HW_SSN_SEQ3) << BIT_SHIFT_HW_SSN_SEQ3)
-#define BIT_GET_HW_SSN_SEQ3(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ3) & BIT_MASK_HW_SSN_SEQ3)
+/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */
+#define BIT_SHIFT_MACID_CTRL_OFFSET 8
+#define BIT_MASK_MACID_CTRL_OFFSET 0xff
+#define BIT_MACID_CTRL_OFFSET(x) \
+ (((x) & BIT_MASK_MACID_CTRL_OFFSET) << BIT_SHIFT_MACID_CTRL_OFFSET)
+#define BITS_MACID_CTRL_OFFSET \
+ (BIT_MASK_MACID_CTRL_OFFSET << BIT_SHIFT_MACID_CTRL_OFFSET)
+#define BIT_CLEAR_MACID_CTRL_OFFSET(x) ((x) & (~BITS_MACID_CTRL_OFFSET))
+#define BIT_GET_MACID_CTRL_OFFSET(x) \
+ (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET) & BIT_MASK_MACID_CTRL_OFFSET)
+#define BIT_SET_MACID_CTRL_OFFSET(x, v) \
+ (BIT_CLEAR_MACID_CTRL_OFFSET(x) | BIT_MACID_CTRL_OFFSET(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */
+#define BIT_SHIFT_LOC_SRFF 0
+#define BIT_MASK_LOC_SRFF 0xff
+#define BIT_LOC_SRFF(x) (((x) & BIT_MASK_LOC_SRFF) << BIT_SHIFT_LOC_SRFF)
+#define BITS_LOC_SRFF (BIT_MASK_LOC_SRFF << BIT_SHIFT_LOC_SRFF)
+#define BIT_CLEAR_LOC_SRFF(x) ((x) & (~BITS_LOC_SRFF))
+#define BIT_GET_LOC_SRFF(x) (((x) >> BIT_SHIFT_LOC_SRFF) & BIT_MASK_LOC_SRFF)
+#define BIT_SET_LOC_SRFF(x, v) (BIT_CLEAR_LOC_SRFF(x) | BIT_LOC_SRFF(v))
-/* 2 REG_CSI_SEQ (Offset 0x04DE) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_HW_CSI_SEQ 0
-#define BIT_MASK_HW_CSI_SEQ 0xfff
-#define BIT_HW_CSI_SEQ(x) (((x) & BIT_MASK_HW_CSI_SEQ) << BIT_SHIFT_HW_CSI_SEQ)
-#define BIT_GET_HW_CSI_SEQ(x) (((x) >> BIT_SHIFT_HW_CSI_SEQ) & BIT_MASK_HW_CSI_SEQ)
+/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */
+#define BIT_SHIFT_AMPDU_TXRPT_OFFSET 0
+#define BIT_MASK_AMPDU_TXRPT_OFFSET 0xff
+#define BIT_AMPDU_TXRPT_OFFSET(x) \
+ (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET) << BIT_SHIFT_AMPDU_TXRPT_OFFSET)
+#define BITS_AMPDU_TXRPT_OFFSET \
+ (BIT_MASK_AMPDU_TXRPT_OFFSET << BIT_SHIFT_AMPDU_TXRPT_OFFSET)
+#define BIT_CLEAR_AMPDU_TXRPT_OFFSET(x) ((x) & (~BITS_AMPDU_TXRPT_OFFSET))
+#define BIT_GET_AMPDU_TXRPT_OFFSET(x) \
+ (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET) & BIT_MASK_AMPDU_TXRPT_OFFSET)
+#define BIT_SET_AMPDU_TXRPT_OFFSET(x, v) \
+ (BIT_CLEAR_AMPDU_TXRPT_OFFSET(x) | BIT_AMPDU_TXRPT_OFFSET(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */
+#define BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1 0
+#define BIT_MASK_AMPDU_TXRPT_OFFSET_V1 0x1ff
+#define BIT_AMPDU_TXRPT_OFFSET_V1(x) \
+ (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_V1) \
+ << BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1)
+#define BITS_AMPDU_TXRPT_OFFSET_V1 \
+ (BIT_MASK_AMPDU_TXRPT_OFFSET_V1 << BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1)
+#define BIT_CLEAR_AMPDU_TXRPT_OFFSET_V1(x) ((x) & (~BITS_AMPDU_TXRPT_OFFSET_V1))
+#define BIT_GET_AMPDU_TXRPT_OFFSET_V1(x) \
+ (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1) & \
+ BIT_MASK_AMPDU_TXRPT_OFFSET_V1)
+#define BIT_SET_AMPDU_TXRPT_OFFSET_V1(x, v) \
+ (BIT_CLEAR_AMPDU_TXRPT_OFFSET_V1(x) | BIT_AMPDU_TXRPT_OFFSET_V1(v))
-/* 2 REG_NULL_PKT_STATUS_V1 (Offset 0x04E0) */
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TRYING_CNT_TH (Offset 0x04B0) */
+#define BIT_SHIFT_INDEX_15 24
+#define BIT_MASK_INDEX_15 0xff
+#define BIT_INDEX_15(x) (((x) & BIT_MASK_INDEX_15) << BIT_SHIFT_INDEX_15)
+#define BITS_INDEX_15 (BIT_MASK_INDEX_15 << BIT_SHIFT_INDEX_15)
+#define BIT_CLEAR_INDEX_15(x) ((x) & (~BITS_INDEX_15))
+#define BIT_GET_INDEX_15(x) (((x) >> BIT_SHIFT_INDEX_15) & BIT_MASK_INDEX_15)
+#define BIT_SET_INDEX_15(x, v) (BIT_CLEAR_INDEX_15(x) | BIT_INDEX_15(v))
+
+#define BIT_SHIFT_INDEX_14 16
+#define BIT_MASK_INDEX_14 0xff
+#define BIT_INDEX_14(x) (((x) & BIT_MASK_INDEX_14) << BIT_SHIFT_INDEX_14)
+#define BITS_INDEX_14 (BIT_MASK_INDEX_14 << BIT_SHIFT_INDEX_14)
+#define BIT_CLEAR_INDEX_14(x) ((x) & (~BITS_INDEX_14))
+#define BIT_GET_INDEX_14(x) (((x) >> BIT_SHIFT_INDEX_14) & BIT_MASK_INDEX_14)
+#define BIT_SET_INDEX_14(x, v) (BIT_CLEAR_INDEX_14(x) | BIT_INDEX_14(v))
+
+#define BIT_SHIFT_INDEX_13 8
+#define BIT_MASK_INDEX_13 0xff
+#define BIT_INDEX_13(x) (((x) & BIT_MASK_INDEX_13) << BIT_SHIFT_INDEX_13)
+#define BITS_INDEX_13 (BIT_MASK_INDEX_13 << BIT_SHIFT_INDEX_13)
+#define BIT_CLEAR_INDEX_13(x) ((x) & (~BITS_INDEX_13))
+#define BIT_GET_INDEX_13(x) (((x) >> BIT_SHIFT_INDEX_13) & BIT_MASK_INDEX_13)
+#define BIT_SET_INDEX_13(x, v) (BIT_CLEAR_INDEX_13(x) | BIT_INDEX_13(v))
+
+#define BIT_SHIFT_INDEX_12 0
+#define BIT_MASK_INDEX_12 0xff
+#define BIT_INDEX_12(x) (((x) & BIT_MASK_INDEX_12) << BIT_SHIFT_INDEX_12)
+#define BITS_INDEX_12 (BIT_MASK_INDEX_12 << BIT_SHIFT_INDEX_12)
+#define BIT_CLEAR_INDEX_12(x) ((x) & (~BITS_INDEX_12))
+#define BIT_GET_INDEX_12(x) (((x) >> BIT_SHIFT_INDEX_12) & BIT_MASK_INDEX_12)
+#define BIT_SET_INDEX_12(x, v) (BIT_CLEAR_INDEX_12(x) | BIT_INDEX_12(v))
+
+#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT 0
+#define BIT_MASK_RA_TRY_RATE_AGG_LMT 0x1f
+#define BIT_RA_TRY_RATE_AGG_LMT(x) \
+ (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT) << BIT_SHIFT_RA_TRY_RATE_AGG_LMT)
+#define BITS_RA_TRY_RATE_AGG_LMT \
+ (BIT_MASK_RA_TRY_RATE_AGG_LMT << BIT_SHIFT_RA_TRY_RATE_AGG_LMT)
+#define BIT_CLEAR_RA_TRY_RATE_AGG_LMT(x) ((x) & (~BITS_RA_TRY_RATE_AGG_LMT))
+#define BIT_GET_RA_TRY_RATE_AGG_LMT(x) \
+ (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT) & BIT_MASK_RA_TRY_RATE_AGG_LMT)
+#define BIT_SET_RA_TRY_RATE_AGG_LMT(x, v) \
+ (BIT_CLEAR_RA_TRY_RATE_AGG_LMT(x) | BIT_RA_TRY_RATE_AGG_LMT(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_PTCL_TOTAL_PG_V1 2
-#define BIT_MASK_PTCL_TOTAL_PG_V1 0x1fff
-#define BIT_PTCL_TOTAL_PG_V1(x) (((x) & BIT_MASK_PTCL_TOTAL_PG_V1) << BIT_SHIFT_PTCL_TOTAL_PG_V1)
-#define BIT_GET_PTCL_TOTAL_PG_V1(x) (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V1) & BIT_MASK_PTCL_TOTAL_PG_V1)
+/* 2 REG_POWER_STAGE1 (Offset 0x04B4) */
+#define BIT_PTA_WL_PRI_MASK_CPU_MGQ BIT(31)
+#define BIT_PTA_WL_PRI_MASK_BCNQ BIT(30)
+#define BIT_PTA_WL_PRI_MASK_HIQ BIT(29)
+#define BIT_PTA_WL_PRI_MASK_MGQ BIT(28)
+#define BIT_PTA_WL_PRI_MASK_BK BIT(27)
+#define BIT_PTA_WL_PRI_MASK_BE BIT(26)
+#define BIT_PTA_WL_PRI_MASK_VI BIT(25)
+#define BIT_PTA_WL_PRI_MASK_VO BIT(24)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_POWER_STAGE1 (Offset 0x04B4) */
+#define BIT_SHIFT_POWER_STAGE1 0
+#define BIT_MASK_POWER_STAGE1 0xffffff
+#define BIT_POWER_STAGE1(x) \
+ (((x) & BIT_MASK_POWER_STAGE1) << BIT_SHIFT_POWER_STAGE1)
+#define BITS_POWER_STAGE1 (BIT_MASK_POWER_STAGE1 << BIT_SHIFT_POWER_STAGE1)
+#define BIT_CLEAR_POWER_STAGE1(x) ((x) & (~BITS_POWER_STAGE1))
+#define BIT_GET_POWER_STAGE1(x) \
+ (((x) >> BIT_SHIFT_POWER_STAGE1) & BIT_MASK_POWER_STAGE1)
+#define BIT_SET_POWER_STAGE1(x, v) \
+ (BIT_CLEAR_POWER_STAGE1(x) | BIT_POWER_STAGE1(v))
-/* 2 REG_NULL_PKT_STATUS_V1 (Offset 0x04E0) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_PTCL_TOTAL_PG_V2 2
-#define BIT_MASK_PTCL_TOTAL_PG_V2 0x3fff
-#define BIT_PTCL_TOTAL_PG_V2(x) (((x) & BIT_MASK_PTCL_TOTAL_PG_V2) << BIT_SHIFT_PTCL_TOTAL_PG_V2)
-#define BIT_GET_PTCL_TOTAL_PG_V2(x) (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2) & BIT_MASK_PTCL_TOTAL_PG_V2)
+/* 2 REG_POWER_STAGE2 (Offset 0x04B8) */
+#define BIT__R_CTRL_PKT_POW_ADJ BIT(24)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_POWER_STAGE2 (Offset 0x04B8) */
+#define BIT__CTRL_PKT_POW_ADJ BIT(24)
-/* 2 REG_NULL_PKT_STATUS (Offset 0x04E0) */
+#endif
-#define BIT_TX_NULL_1 BIT(1)
-#define BIT_TX_NULL_0 BIT(0)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_POWER_STAGE2 (Offset 0x04B8) */
+#define BIT_SHIFT_POWER_STAGE2 0
+#define BIT_MASK_POWER_STAGE2 0xffffff
+#define BIT_POWER_STAGE2(x) \
+ (((x) & BIT_MASK_POWER_STAGE2) << BIT_SHIFT_POWER_STAGE2)
+#define BITS_POWER_STAGE2 (BIT_MASK_POWER_STAGE2 << BIT_SHIFT_POWER_STAGE2)
+#define BIT_CLEAR_POWER_STAGE2(x) ((x) & (~BITS_POWER_STAGE2))
+#define BIT_GET_POWER_STAGE2(x) \
+ (((x) >> BIT_SHIFT_POWER_STAGE2) & BIT_MASK_POWER_STAGE2)
+#define BIT_SET_POWER_STAGE2(x, v) \
+ (BIT_CLEAR_POWER_STAGE2(x) | BIT_POWER_STAGE2(v))
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-/* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */
+/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */
-#define BIT_PTCL_RATE_TABLE_INVALID BIT(7)
-#define BIT_FTM_T2R_ERROR BIT(6)
+#define BIT_SHIFT_PAD_NUM_THRES 24
+#define BIT_MASK_PAD_NUM_THRES 0x3f
+#define BIT_PAD_NUM_THRES(x) \
+ (((x) & BIT_MASK_PAD_NUM_THRES) << BIT_SHIFT_PAD_NUM_THRES)
+#define BITS_PAD_NUM_THRES (BIT_MASK_PAD_NUM_THRES << BIT_SHIFT_PAD_NUM_THRES)
+#define BIT_CLEAR_PAD_NUM_THRES(x) ((x) & (~BITS_PAD_NUM_THRES))
+#define BIT_GET_PAD_NUM_THRES(x) \
+ (((x) >> BIT_SHIFT_PAD_NUM_THRES) & BIT_MASK_PAD_NUM_THRES)
+#define BIT_SET_PAD_NUM_THRES(x, v) \
+ (BIT_CLEAR_PAD_NUM_THRES(x) | BIT_PAD_NUM_THRES(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */
+#define BIT_R_DMA_THIS_QUEUE_BK BIT(23)
-/* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */
+#endif
-#define BIT_PTCL_ERR0 BIT(5)
-#define BIT_PTCL_ERR1 BIT(4)
-#define BIT_PTCL_ERR2 BIT(3)
-#define BIT_PTCL_ERR3 BIT(2)
-#define BIT_PTCL_ERR4 BIT(1)
-#define BIT_PTCL_ERR5 BIT(0)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */
+#define BIT_DMA_THIS_QUEUE_BK BIT(23)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_NULL_PKT_STATUS_EXTEND (Offset 0x04E3) */
+/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */
-#define BIT_CLI3_TX_NULL_1 BIT(7)
-#define BIT_CLI3_TX_NULL_0 BIT(6)
-#define BIT_CLI2_TX_NULL_1 BIT(5)
-#define BIT_CLI2_TX_NULL_0 BIT(4)
-#define BIT_CLI1_TX_NULL_1 BIT(3)
-#define BIT_CLI1_TX_NULL_0 BIT(2)
-#define BIT_CLI0_TX_NULL_1 BIT(1)
+#define BIT_R_DMA_THIS_QUEUE_BE BIT(22)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */
+#define BIT_DMA_THIS_QUEUE_BE BIT(22)
-/* 2 REG_PTCL_PKT_NUM (Offset 0x04E3) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_PTCL_TOTAL_PG 0
-#define BIT_MASK_PTCL_TOTAL_PG 0xff
-#define BIT_PTCL_TOTAL_PG(x) (((x) & BIT_MASK_PTCL_TOTAL_PG) << BIT_SHIFT_PTCL_TOTAL_PG)
-#define BIT_GET_PTCL_TOTAL_PG(x) (((x) >> BIT_SHIFT_PTCL_TOTAL_PG) & BIT_MASK_PTCL_TOTAL_PG)
+/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */
+#define BIT_R_DMA_THIS_QUEUE_VI BIT(21)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */
+#define BIT_DMA_THIS_QUEUE_VI BIT(21)
-/* 2 REG_NULL_PKT_STATUS_EXTEND (Offset 0x04E3) */
+#endif
-#define BIT_CLI0_TX_NULL_0 BIT(0)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */
+
+#define BIT_R_DMA_THIS_QUEUE_VO BIT(20)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */
+#define BIT_DMA_THIS_QUEUE_VO BIT(20)
-/* 2 REG_TRXRPT_MISS_CNT (Offset 0x04E3) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_TRXRPT_MISS_CNT 0
-#define BIT_MASK_TRXRPT_MISS_CNT 0x7
-#define BIT_TRXRPT_MISS_CNT(x) (((x) & BIT_MASK_TRXRPT_MISS_CNT) << BIT_SHIFT_TRXRPT_MISS_CNT)
-#define BIT_GET_TRXRPT_MISS_CNT(x) (((x) >> BIT_SHIFT_TRXRPT_MISS_CNT) & BIT_MASK_TRXRPT_MISS_CNT)
+/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */
+#define BIT_SHIFT_R_TOTAL_LEN_TH 8
+#define BIT_MASK_R_TOTAL_LEN_TH 0xfff
+#define BIT_R_TOTAL_LEN_TH(x) \
+ (((x) & BIT_MASK_R_TOTAL_LEN_TH) << BIT_SHIFT_R_TOTAL_LEN_TH)
+#define BITS_R_TOTAL_LEN_TH \
+ (BIT_MASK_R_TOTAL_LEN_TH << BIT_SHIFT_R_TOTAL_LEN_TH)
+#define BIT_CLEAR_R_TOTAL_LEN_TH(x) ((x) & (~BITS_R_TOTAL_LEN_TH))
+#define BIT_GET_R_TOTAL_LEN_TH(x) \
+ (((x) >> BIT_SHIFT_R_TOTAL_LEN_TH) & BIT_MASK_R_TOTAL_LEN_TH)
+#define BIT_SET_R_TOTAL_LEN_TH(x, v) \
+ (BIT_CLEAR_R_TOTAL_LEN_TH(x) | BIT_R_TOTAL_LEN_TH(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */
+#define BIT_SHIFT_TOTAL_LEN_TH 8
+#define BIT_MASK_TOTAL_LEN_TH 0xfff
+#define BIT_TOTAL_LEN_TH(x) \
+ (((x) & BIT_MASK_TOTAL_LEN_TH) << BIT_SHIFT_TOTAL_LEN_TH)
+#define BITS_TOTAL_LEN_TH (BIT_MASK_TOTAL_LEN_TH << BIT_SHIFT_TOTAL_LEN_TH)
+#define BIT_CLEAR_TOTAL_LEN_TH(x) ((x) & (~BITS_TOTAL_LEN_TH))
+#define BIT_GET_TOTAL_LEN_TH(x) \
+ (((x) >> BIT_SHIFT_TOTAL_LEN_TH) & BIT_MASK_TOTAL_LEN_TH)
+#define BIT_SET_TOTAL_LEN_TH(x, v) \
+ (BIT_CLEAR_TOTAL_LEN_TH(x) | BIT_TOTAL_LEN_TH(v))
-/* 2 REG_VIDEO_ENHANCEMENT_FUN (Offset 0x04E4) */
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_VIDEO_JUST_DROP BIT(1)
-#define BIT_VIDEO_ENHANCEMENT_FUN_EN BIT(0)
+/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */
+
+#define BIT_EN_NEW_EARLY BIT(7)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */
+#define BIT_PRE_TX_CMD BIT(6)
-/* 2 REG_BT_POLLUTE_PKT_CNT (Offset 0x04E8) */
+#define BIT_SHIFT_NUM_SCL_EN 4
+#define BIT_MASK_NUM_SCL_EN 0x3
+#define BIT_NUM_SCL_EN(x) (((x) & BIT_MASK_NUM_SCL_EN) << BIT_SHIFT_NUM_SCL_EN)
+#define BITS_NUM_SCL_EN (BIT_MASK_NUM_SCL_EN << BIT_SHIFT_NUM_SCL_EN)
+#define BIT_CLEAR_NUM_SCL_EN(x) ((x) & (~BITS_NUM_SCL_EN))
+#define BIT_GET_NUM_SCL_EN(x) \
+ (((x) >> BIT_SHIFT_NUM_SCL_EN) & BIT_MASK_NUM_SCL_EN)
+#define BIT_SET_NUM_SCL_EN(x, v) (BIT_CLEAR_NUM_SCL_EN(x) | BIT_NUM_SCL_EN(v))
+#define BIT_BK_EN BIT(3)
+#define BIT_BE_EN BIT(2)
+#define BIT_VI_EN BIT(1)
+#define BIT_VO_EN BIT(0)
-#define BIT_SHIFT_BT_POLLUTE_PKT_CNT 0
-#define BIT_MASK_BT_POLLUTE_PKT_CNT 0xffff
-#define BIT_BT_POLLUTE_PKT_CNT(x) (((x) & BIT_MASK_BT_POLLUTE_PKT_CNT) << BIT_SHIFT_BT_POLLUTE_PKT_CNT)
-#define BIT_GET_BT_POLLUTE_PKT_CNT(x) (((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT) & BIT_MASK_BT_POLLUTE_PKT_CNT)
+/* 2 REG_PKT_LIFE_TIME (Offset 0x04C0) */
+#define BIT_SHIFT_PKT_LIFTIME_BEBK 16
+#define BIT_MASK_PKT_LIFTIME_BEBK 0xffff
+#define BIT_PKT_LIFTIME_BEBK(x) \
+ (((x) & BIT_MASK_PKT_LIFTIME_BEBK) << BIT_SHIFT_PKT_LIFTIME_BEBK)
+#define BITS_PKT_LIFTIME_BEBK \
+ (BIT_MASK_PKT_LIFTIME_BEBK << BIT_SHIFT_PKT_LIFTIME_BEBK)
+#define BIT_CLEAR_PKT_LIFTIME_BEBK(x) ((x) & (~BITS_PKT_LIFTIME_BEBK))
+#define BIT_GET_PKT_LIFTIME_BEBK(x) \
+ (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK) & BIT_MASK_PKT_LIFTIME_BEBK)
+#define BIT_SET_PKT_LIFTIME_BEBK(x, v) \
+ (BIT_CLEAR_PKT_LIFTIME_BEBK(x) | BIT_PKT_LIFTIME_BEBK(v))
+
+#define BIT_SHIFT_PKT_LIFTIME_VOVI 0
+#define BIT_MASK_PKT_LIFTIME_VOVI 0xffff
+#define BIT_PKT_LIFTIME_VOVI(x) \
+ (((x) & BIT_MASK_PKT_LIFTIME_VOVI) << BIT_SHIFT_PKT_LIFTIME_VOVI)
+#define BITS_PKT_LIFTIME_VOVI \
+ (BIT_MASK_PKT_LIFTIME_VOVI << BIT_SHIFT_PKT_LIFTIME_VOVI)
+#define BIT_CLEAR_PKT_LIFTIME_VOVI(x) ((x) & (~BITS_PKT_LIFTIME_VOVI))
+#define BIT_GET_PKT_LIFTIME_VOVI(x) \
+ (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI) & BIT_MASK_PKT_LIFTIME_VOVI)
+#define BIT_SET_PKT_LIFTIME_VOVI(x, v) \
+ (BIT_CLEAR_PKT_LIFTIME_VOVI(x) | BIT_PKT_LIFTIME_VOVI(v))
-/* 2 REG_PTCL_DBG (Offset 0x04EC) */
+/* 2 REG_STBC_SETTING (Offset 0x04C4) */
+#define BIT_SHIFT_CDEND_TXTIME_L 4
+#define BIT_MASK_CDEND_TXTIME_L 0xf
+#define BIT_CDEND_TXTIME_L(x) \
+ (((x) & BIT_MASK_CDEND_TXTIME_L) << BIT_SHIFT_CDEND_TXTIME_L)
+#define BITS_CDEND_TXTIME_L \
+ (BIT_MASK_CDEND_TXTIME_L << BIT_SHIFT_CDEND_TXTIME_L)
+#define BIT_CLEAR_CDEND_TXTIME_L(x) ((x) & (~BITS_CDEND_TXTIME_L))
+#define BIT_GET_CDEND_TXTIME_L(x) \
+ (((x) >> BIT_SHIFT_CDEND_TXTIME_L) & BIT_MASK_CDEND_TXTIME_L)
+#define BIT_SET_CDEND_TXTIME_L(x, v) \
+ (BIT_CLEAR_CDEND_TXTIME_L(x) | BIT_CDEND_TXTIME_L(v))
+
+#define BIT_SHIFT_NESS 2
+#define BIT_MASK_NESS 0x3
+#define BIT_NESS(x) (((x) & BIT_MASK_NESS) << BIT_SHIFT_NESS)
+#define BITS_NESS (BIT_MASK_NESS << BIT_SHIFT_NESS)
+#define BIT_CLEAR_NESS(x) ((x) & (~BITS_NESS))
+#define BIT_GET_NESS(x) (((x) >> BIT_SHIFT_NESS) & BIT_MASK_NESS)
+#define BIT_SET_NESS(x, v) (BIT_CLEAR_NESS(x) | BIT_NESS(v))
+
+#define BIT_SHIFT_STBC_CFEND 0
+#define BIT_MASK_STBC_CFEND 0x3
+#define BIT_STBC_CFEND(x) (((x) & BIT_MASK_STBC_CFEND) << BIT_SHIFT_STBC_CFEND)
+#define BITS_STBC_CFEND (BIT_MASK_STBC_CFEND << BIT_SHIFT_STBC_CFEND)
+#define BIT_CLEAR_STBC_CFEND(x) ((x) & (~BITS_STBC_CFEND))
+#define BIT_GET_STBC_CFEND(x) \
+ (((x) >> BIT_SHIFT_STBC_CFEND) & BIT_MASK_STBC_CFEND)
+#define BIT_SET_STBC_CFEND(x, v) (BIT_CLEAR_STBC_CFEND(x) | BIT_STBC_CFEND(v))
-#define BIT_SHIFT_PTCL_DBG 0
-#define BIT_MASK_PTCL_DBG 0xffffffffL
-#define BIT_PTCL_DBG(x) (((x) & BIT_MASK_PTCL_DBG) << BIT_SHIFT_PTCL_DBG)
-#define BIT_GET_PTCL_DBG(x) (((x) >> BIT_SHIFT_PTCL_DBG) & BIT_MASK_PTCL_DBG)
+/* 2 REG_STBC_SETTING2 (Offset 0x04C5) */
+#define BIT_SHIFT_CDEND_TXTIME_H 0
+#define BIT_MASK_CDEND_TXTIME_H 0x1f
+#define BIT_CDEND_TXTIME_H(x) \
+ (((x) & BIT_MASK_CDEND_TXTIME_H) << BIT_SHIFT_CDEND_TXTIME_H)
+#define BITS_CDEND_TXTIME_H \
+ (BIT_MASK_CDEND_TXTIME_H << BIT_SHIFT_CDEND_TXTIME_H)
+#define BIT_CLEAR_CDEND_TXTIME_H(x) ((x) & (~BITS_CDEND_TXTIME_H))
+#define BIT_GET_CDEND_TXTIME_H(x) \
+ (((x) >> BIT_SHIFT_CDEND_TXTIME_H) & BIT_MASK_CDEND_TXTIME_H)
+#define BIT_SET_CDEND_TXTIME_H(x, v) \
+ (BIT_CLEAR_CDEND_TXTIME_H(x) | BIT_CDEND_TXTIME_H(v))
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_QUEUE_CTRL (Offset 0x04C6) */
+#define BIT_FORCE_RND_PRI BIT(6)
-/* 2 REG_PTCL_TX_RPT (Offset 0x04F0) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_AC_TX_RPT_INFO 0
-#define BIT_MASK_AC_TX_RPT_INFO 0xffffffffffffffffL
-#define BIT_AC_TX_RPT_INFO(x) (((x) & BIT_MASK_AC_TX_RPT_INFO) << BIT_SHIFT_AC_TX_RPT_INFO)
-#define BIT_GET_AC_TX_RPT_INFO(x) (((x) >> BIT_SHIFT_AC_TX_RPT_INFO) & BIT_MASK_AC_TX_RPT_INFO)
+/* 2 REG_QUEUE_CTRL (Offset 0x04C6) */
+#define BIT_PTA_EDCCA_EN BIT(5)
+#define BIT_PTA_WL_TX_EN BIT(4)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
-
-/* 2 REG_TXOP_EXTRA_CTRL (Offset 0x04F0) */
+/* 2 REG_QUEUE_CTRL (Offset 0x04C6) */
-#define BIT_TXOP_EFFICIENCY_EN BIT(0)
+#define BIT_R_USE_DATA_BW BIT(3)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_QUEUE_CTRL (Offset 0x04C6) */
+#define BIT_USE_DATA_BW BIT(3)
-/* 2 REG_CPUMGQ_TIMER_CTRL2 (Offset 0x04F4) */
+#endif
-#define BIT_QUEUE_MACID_AC_NOT_THE_SAME BIT(31)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_GTAB_ID 28
-#define BIT_MASK_GTAB_ID 0x7
-#define BIT_GTAB_ID(x) (((x) & BIT_MASK_GTAB_ID) << BIT_SHIFT_GTAB_ID)
-#define BIT_GET_GTAB_ID(x) (((x) >> BIT_SHIFT_GTAB_ID) & BIT_MASK_GTAB_ID)
+/* 2 REG_QUEUE_CTRL (Offset 0x04C6) */
+#define BIT_TRI_PKT_INT_MODE1 BIT(2)
+#define BIT_TRI_PKT_INT_MODE0 BIT(1)
+#define BIT_ACQ_MODE_SEL BIT(0)
-#define BIT_SHIFT_TRI_HEAD_ADDR 16
-#define BIT_MASK_TRI_HEAD_ADDR 0xfff
-#define BIT_TRI_HEAD_ADDR(x) (((x) & BIT_MASK_TRI_HEAD_ADDR) << BIT_SHIFT_TRI_HEAD_ADDR)
-#define BIT_GET_TRI_HEAD_ADDR(x) (((x) >> BIT_SHIFT_TRI_HEAD_ADDR) & BIT_MASK_TRI_HEAD_ADDR)
+/* 2 REG_SINGLE_AMPDU_CTRL (Offset 0x04C7) */
-#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1 BIT(15)
+#define BIT_EN_SINGLE_APMDU BIT(7)
-#define BIT_SHIFT_GTAB_ID_V1 12
-#define BIT_MASK_GTAB_ID_V1 0x7
-#define BIT_GTAB_ID_V1(x) (((x) & BIT_MASK_GTAB_ID_V1) << BIT_SHIFT_GTAB_ID_V1)
-#define BIT_GET_GTAB_ID_V1(x) (((x) >> BIT_SHIFT_GTAB_ID_V1) & BIT_MASK_GTAB_ID_V1)
+#endif
-#define BIT_DROP_TH_EN BIT(8)
+#if (HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_DROP_TH 0
-#define BIT_MASK_DROP_TH 0xff
-#define BIT_DROP_TH(x) (((x) & BIT_MASK_DROP_TH) << BIT_SHIFT_DROP_TH)
-#define BIT_GET_DROP_TH(x) (((x) >> BIT_SHIFT_DROP_TH) & BIT_MASK_DROP_TH)
+/* 2 REG_PROT_MODE_CTRL (Offset 0x04C8) */
+#define BIT_SND_SIFS_TXDATA BIT(31)
+#define BIT_TX_SND_MATCH_MACID BIT(30)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT)
+/* 2 REG_PROT_MODE_CTRL (Offset 0x04C8) */
+#define BIT_SHIFT_RTS_MAX_AGG_NUM 24
+#define BIT_MASK_RTS_MAX_AGG_NUM 0x3f
+#define BIT_RTS_MAX_AGG_NUM(x) \
+ (((x) & BIT_MASK_RTS_MAX_AGG_NUM) << BIT_SHIFT_RTS_MAX_AGG_NUM)
+#define BITS_RTS_MAX_AGG_NUM \
+ (BIT_MASK_RTS_MAX_AGG_NUM << BIT_SHIFT_RTS_MAX_AGG_NUM)
+#define BIT_CLEAR_RTS_MAX_AGG_NUM(x) ((x) & (~BITS_RTS_MAX_AGG_NUM))
+#define BIT_GET_RTS_MAX_AGG_NUM(x) \
+ (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM) & BIT_MASK_RTS_MAX_AGG_NUM)
+#define BIT_SET_RTS_MAX_AGG_NUM(x, v) \
+ (BIT_CLEAR_RTS_MAX_AGG_NUM(x) | BIT_RTS_MAX_AGG_NUM(v))
+
+#define BIT_SHIFT_MAX_AGG_NUM 16
+#define BIT_MASK_MAX_AGG_NUM 0x3f
+#define BIT_MAX_AGG_NUM(x) \
+ (((x) & BIT_MASK_MAX_AGG_NUM) << BIT_SHIFT_MAX_AGG_NUM)
+#define BITS_MAX_AGG_NUM (BIT_MASK_MAX_AGG_NUM << BIT_SHIFT_MAX_AGG_NUM)
+#define BIT_CLEAR_MAX_AGG_NUM(x) ((x) & (~BITS_MAX_AGG_NUM))
+#define BIT_GET_MAX_AGG_NUM(x) \
+ (((x) >> BIT_SHIFT_MAX_AGG_NUM) & BIT_MASK_MAX_AGG_NUM)
+#define BIT_SET_MAX_AGG_NUM(x, v) \
+ (BIT_CLEAR_MAX_AGG_NUM(x) | BIT_MAX_AGG_NUM(v))
+
+#define BIT_SHIFT_RTS_TXTIME_TH 8
+#define BIT_MASK_RTS_TXTIME_TH 0xff
+#define BIT_RTS_TXTIME_TH(x) \
+ (((x) & BIT_MASK_RTS_TXTIME_TH) << BIT_SHIFT_RTS_TXTIME_TH)
+#define BITS_RTS_TXTIME_TH (BIT_MASK_RTS_TXTIME_TH << BIT_SHIFT_RTS_TXTIME_TH)
+#define BIT_CLEAR_RTS_TXTIME_TH(x) ((x) & (~BITS_RTS_TXTIME_TH))
+#define BIT_GET_RTS_TXTIME_TH(x) \
+ (((x) >> BIT_SHIFT_RTS_TXTIME_TH) & BIT_MASK_RTS_TXTIME_TH)
+#define BIT_SET_RTS_TXTIME_TH(x, v) \
+ (BIT_CLEAR_RTS_TXTIME_TH(x) | BIT_RTS_TXTIME_TH(v))
+
+#define BIT_SHIFT_RTS_LEN_TH 0
+#define BIT_MASK_RTS_LEN_TH 0xff
+#define BIT_RTS_LEN_TH(x) (((x) & BIT_MASK_RTS_LEN_TH) << BIT_SHIFT_RTS_LEN_TH)
+#define BITS_RTS_LEN_TH (BIT_MASK_RTS_LEN_TH << BIT_SHIFT_RTS_LEN_TH)
+#define BIT_CLEAR_RTS_LEN_TH(x) ((x) & (~BITS_RTS_LEN_TH))
+#define BIT_GET_RTS_LEN_TH(x) \
+ (((x) >> BIT_SHIFT_RTS_LEN_TH) & BIT_MASK_RTS_LEN_TH)
+#define BIT_SET_RTS_LEN_TH(x, v) (BIT_CLEAR_RTS_LEN_TH(x) | BIT_RTS_LEN_TH(v))
-/* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */
+/* 2 REG_BAR_MODE_CTRL (Offset 0x04CC) */
-#define BIT_MOREDATA_CTRL2_EN BIT(19)
+#define BIT_SHIFT_BAR_RTY_LMT 16
+#define BIT_MASK_BAR_RTY_LMT 0x3
+#define BIT_BAR_RTY_LMT(x) \
+ (((x) & BIT_MASK_BAR_RTY_LMT) << BIT_SHIFT_BAR_RTY_LMT)
+#define BITS_BAR_RTY_LMT (BIT_MASK_BAR_RTY_LMT << BIT_SHIFT_BAR_RTY_LMT)
+#define BIT_CLEAR_BAR_RTY_LMT(x) ((x) & (~BITS_BAR_RTY_LMT))
+#define BIT_GET_BAR_RTY_LMT(x) \
+ (((x) >> BIT_SHIFT_BAR_RTY_LMT) & BIT_MASK_BAR_RTY_LMT)
+#define BIT_SET_BAR_RTY_LMT(x, v) \
+ (BIT_CLEAR_BAR_RTY_LMT(x) | BIT_BAR_RTY_LMT(v))
+
+#define BIT_SHIFT_BAR_PKT_TXTIME_TH 8
+#define BIT_MASK_BAR_PKT_TXTIME_TH 0xff
+#define BIT_BAR_PKT_TXTIME_TH(x) \
+ (((x) & BIT_MASK_BAR_PKT_TXTIME_TH) << BIT_SHIFT_BAR_PKT_TXTIME_TH)
+#define BITS_BAR_PKT_TXTIME_TH \
+ (BIT_MASK_BAR_PKT_TXTIME_TH << BIT_SHIFT_BAR_PKT_TXTIME_TH)
+#define BIT_CLEAR_BAR_PKT_TXTIME_TH(x) ((x) & (~BITS_BAR_PKT_TXTIME_TH))
+#define BIT_GET_BAR_PKT_TXTIME_TH(x) \
+ (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH) & BIT_MASK_BAR_PKT_TXTIME_TH)
+#define BIT_SET_BAR_PKT_TXTIME_TH(x, v) \
+ (BIT_CLEAR_BAR_PKT_TXTIME_TH(x) | BIT_BAR_PKT_TXTIME_TH(v))
+
+#define BIT_BAR_EN_V1 BIT(6)
+
+#define BIT_SHIFT_BAR_PKTNUM_TH_V1 0
+#define BIT_MASK_BAR_PKTNUM_TH_V1 0x3f
+#define BIT_BAR_PKTNUM_TH_V1(x) \
+ (((x) & BIT_MASK_BAR_PKTNUM_TH_V1) << BIT_SHIFT_BAR_PKTNUM_TH_V1)
+#define BITS_BAR_PKTNUM_TH_V1 \
+ (BIT_MASK_BAR_PKTNUM_TH_V1 << BIT_SHIFT_BAR_PKTNUM_TH_V1)
+#define BIT_CLEAR_BAR_PKTNUM_TH_V1(x) ((x) & (~BITS_BAR_PKTNUM_TH_V1))
+#define BIT_GET_BAR_PKTNUM_TH_V1(x) \
+ (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1) & BIT_MASK_BAR_PKTNUM_TH_V1)
+#define BIT_SET_BAR_PKTNUM_TH_V1(x, v) \
+ (BIT_CLEAR_BAR_PKTNUM_TH_V1(x) | BIT_BAR_PKTNUM_TH_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_RA_TRY_RATE_AGG_LMT (Offset 0x04CF) */
+#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1 0
+#define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1 0x3f
+#define BIT_RA_TRY_RATE_AGG_LMT_V1(x) \
+ (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1) \
+ << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1)
+#define BITS_RA_TRY_RATE_AGG_LMT_V1 \
+ (BIT_MASK_RA_TRY_RATE_AGG_LMT_V1 << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1)
+#define BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1(x) \
+ ((x) & (~BITS_RA_TRY_RATE_AGG_LMT_V1))
+#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1(x) \
+ (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1) & \
+ BIT_MASK_RA_TRY_RATE_AGG_LMT_V1)
+#define BIT_SET_RA_TRY_RATE_AGG_LMT_V1(x, v) \
+ (BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1(x) | BIT_RA_TRY_RATE_AGG_LMT_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_MACID_SLEEP_CTRL (Offset 0x04D0) */
+
+#define BIT_SHIFT_DEBUG_PROTOCOL 24
+#define BIT_MASK_DEBUG_PROTOCOL 0xff
+#define BIT_DEBUG_PROTOCOL(x) \
+ (((x) & BIT_MASK_DEBUG_PROTOCOL) << BIT_SHIFT_DEBUG_PROTOCOL)
+#define BITS_DEBUG_PROTOCOL \
+ (BIT_MASK_DEBUG_PROTOCOL << BIT_SHIFT_DEBUG_PROTOCOL)
+#define BIT_CLEAR_DEBUG_PROTOCOL(x) ((x) & (~BITS_DEBUG_PROTOCOL))
+#define BIT_GET_DEBUG_PROTOCOL(x) \
+ (((x) >> BIT_SHIFT_DEBUG_PROTOCOL) & BIT_MASK_DEBUG_PROTOCOL)
+#define BIT_SET_DEBUG_PROTOCOL(x, v) \
+ (BIT_CLEAR_DEBUG_PROTOCOL(x) | BIT_DEBUG_PROTOCOL(v))
+
+#define BIT_SHIFT_BCNQ_PGBNDY_RSEL 16
+#define BIT_MASK_BCNQ_PGBNDY_RSEL 0x7
+#define BIT_BCNQ_PGBNDY_RSEL(x) \
+ (((x) & BIT_MASK_BCNQ_PGBNDY_RSEL) << BIT_SHIFT_BCNQ_PGBNDY_RSEL)
+#define BITS_BCNQ_PGBNDY_RSEL \
+ (BIT_MASK_BCNQ_PGBNDY_RSEL << BIT_SHIFT_BCNQ_PGBNDY_RSEL)
+#define BIT_CLEAR_BCNQ_PGBNDY_RSEL(x) ((x) & (~BITS_BCNQ_PGBNDY_RSEL))
+#define BIT_GET_BCNQ_PGBNDY_RSEL(x) \
+ (((x) >> BIT_SHIFT_BCNQ_PGBNDY_RSEL) & BIT_MASK_BCNQ_PGBNDY_RSEL)
+#define BIT_SET_BCNQ_PGBNDY_RSEL(x, v) \
+ (BIT_CLEAR_BCNQ_PGBNDY_RSEL(x) | BIT_BCNQ_PGBNDY_RSEL(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_MACID_SLEEP2 (Offset 0x04D0) */
+#define BIT_SHIFT_MACID95_64PKTSLEEP 0
+#define BIT_MASK_MACID95_64PKTSLEEP 0xffffffffL
+#define BIT_MACID95_64PKTSLEEP(x) \
+ (((x) & BIT_MASK_MACID95_64PKTSLEEP) << BIT_SHIFT_MACID95_64PKTSLEEP)
+#define BITS_MACID95_64PKTSLEEP \
+ (BIT_MASK_MACID95_64PKTSLEEP << BIT_SHIFT_MACID95_64PKTSLEEP)
+#define BIT_CLEAR_MACID95_64PKTSLEEP(x) ((x) & (~BITS_MACID95_64PKTSLEEP))
+#define BIT_GET_MACID95_64PKTSLEEP(x) \
+ (((x) >> BIT_SHIFT_MACID95_64PKTSLEEP) & BIT_MASK_MACID95_64PKTSLEEP)
+#define BIT_SET_MACID95_64PKTSLEEP(x, v) \
+ (BIT_CLEAR_MACID95_64PKTSLEEP(x) | BIT_MACID95_64PKTSLEEP(v))
-/* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */
+#endif
-#define BIT_MOREDATA_CTRL2_EN_V2 BIT(19)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_MACID_SLEEP_CTRL (Offset 0x04D0) */
+#define BIT_SHIFT_MACID_SLEEP_SEL 0
+#define BIT_MASK_MACID_SLEEP_SEL 0x7
+#define BIT_MACID_SLEEP_SEL(x) \
+ (((x) & BIT_MASK_MACID_SLEEP_SEL) << BIT_SHIFT_MACID_SLEEP_SEL)
+#define BITS_MACID_SLEEP_SEL \
+ (BIT_MASK_MACID_SLEEP_SEL << BIT_SHIFT_MACID_SLEEP_SEL)
+#define BIT_CLEAR_MACID_SLEEP_SEL(x) ((x) & (~BITS_MACID_SLEEP_SEL))
+#define BIT_GET_MACID_SLEEP_SEL(x) \
+ (((x) >> BIT_SHIFT_MACID_SLEEP_SEL) & BIT_MASK_MACID_SLEEP_SEL)
+#define BIT_SET_MACID_SLEEP_SEL(x, v) \
+ (BIT_CLEAR_MACID_SLEEP_SEL(x) | BIT_MACID_SLEEP_SEL(v))
-#if (HALMAC_8192E_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */
+/* 2 REG_MACID_SLEEP (Offset 0x04D4) */
-#define BIT_MOREDATA_CTRL1_EN BIT(18)
+#define BIT_SHIFT_MACID31_0_PKTSLEEP 0
+#define BIT_MASK_MACID31_0_PKTSLEEP 0xffffffffL
+#define BIT_MACID31_0_PKTSLEEP(x) \
+ (((x) & BIT_MASK_MACID31_0_PKTSLEEP) << BIT_SHIFT_MACID31_0_PKTSLEEP)
+#define BITS_MACID31_0_PKTSLEEP \
+ (BIT_MASK_MACID31_0_PKTSLEEP << BIT_SHIFT_MACID31_0_PKTSLEEP)
+#define BIT_CLEAR_MACID31_0_PKTSLEEP(x) ((x) & (~BITS_MACID31_0_PKTSLEEP))
+#define BIT_GET_MACID31_0_PKTSLEEP(x) \
+ (((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP) & BIT_MASK_MACID31_0_PKTSLEEP)
+#define BIT_SET_MACID31_0_PKTSLEEP(x, v) \
+ (BIT_CLEAR_MACID31_0_PKTSLEEP(x) | BIT_MACID31_0_PKTSLEEP(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_MACID_SLEEP_INFO (Offset 0x04D4) */
+
+#define BIT_SHIFT_MACID_SLEEP_INFO 0
+#define BIT_MASK_MACID_SLEEP_INFO 0xffffffffL
+#define BIT_MACID_SLEEP_INFO(x) \
+ (((x) & BIT_MASK_MACID_SLEEP_INFO) << BIT_SHIFT_MACID_SLEEP_INFO)
+#define BITS_MACID_SLEEP_INFO \
+ (BIT_MASK_MACID_SLEEP_INFO << BIT_SHIFT_MACID_SLEEP_INFO)
+#define BIT_CLEAR_MACID_SLEEP_INFO(x) ((x) & (~BITS_MACID_SLEEP_INFO))
+#define BIT_GET_MACID_SLEEP_INFO(x) \
+ (((x) >> BIT_SHIFT_MACID_SLEEP_INFO) & BIT_MASK_MACID_SLEEP_INFO)
+#define BIT_SET_MACID_SLEEP_INFO(x, v) \
+ (BIT_CLEAR_MACID_SLEEP_INFO(x) | BIT_MACID_SLEEP_INFO(v))
+
+#define BIT_SHIFT_PTCL_TOTAL_PG_V3 0
+#define BIT_MASK_PTCL_TOTAL_PG_V3 0x1fff
+#define BIT_PTCL_TOTAL_PG_V3(x) \
+ (((x) & BIT_MASK_PTCL_TOTAL_PG_V3) << BIT_SHIFT_PTCL_TOTAL_PG_V3)
+#define BITS_PTCL_TOTAL_PG_V3 \
+ (BIT_MASK_PTCL_TOTAL_PG_V3 << BIT_SHIFT_PTCL_TOTAL_PG_V3)
+#define BIT_CLEAR_PTCL_TOTAL_PG_V3(x) ((x) & (~BITS_PTCL_TOTAL_PG_V3))
+#define BIT_GET_PTCL_TOTAL_PG_V3(x) \
+ (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V3) & BIT_MASK_PTCL_TOTAL_PG_V3)
+#define BIT_SET_PTCL_TOTAL_PG_V3(x, v) \
+ (BIT_CLEAR_PTCL_TOTAL_PG_V3(x) | BIT_PTCL_TOTAL_PG_V3(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_HW_SEQ0 (Offset 0x04D8) */
+#define BIT_SHIFT_HW_SSN_SEQ0 0
+#define BIT_MASK_HW_SSN_SEQ0 0xfff
+#define BIT_HW_SSN_SEQ0(x) \
+ (((x) & BIT_MASK_HW_SSN_SEQ0) << BIT_SHIFT_HW_SSN_SEQ0)
+#define BITS_HW_SSN_SEQ0 (BIT_MASK_HW_SSN_SEQ0 << BIT_SHIFT_HW_SSN_SEQ0)
+#define BIT_CLEAR_HW_SSN_SEQ0(x) ((x) & (~BITS_HW_SSN_SEQ0))
+#define BIT_GET_HW_SSN_SEQ0(x) \
+ (((x) >> BIT_SHIFT_HW_SSN_SEQ0) & BIT_MASK_HW_SSN_SEQ0)
+#define BIT_SET_HW_SSN_SEQ0(x, v) \
+ (BIT_CLEAR_HW_SSN_SEQ0(x) | BIT_HW_SSN_SEQ0(v))
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_HW_SEQ1 (Offset 0x04DA) */
+#define BIT_SHIFT_HW_SSN_SEQ1 0
+#define BIT_MASK_HW_SSN_SEQ1 0xfff
+#define BIT_HW_SSN_SEQ1(x) \
+ (((x) & BIT_MASK_HW_SSN_SEQ1) << BIT_SHIFT_HW_SSN_SEQ1)
+#define BITS_HW_SSN_SEQ1 (BIT_MASK_HW_SSN_SEQ1 << BIT_SHIFT_HW_SSN_SEQ1)
+#define BIT_CLEAR_HW_SSN_SEQ1(x) ((x) & (~BITS_HW_SSN_SEQ1))
+#define BIT_GET_HW_SSN_SEQ1(x) \
+ (((x) >> BIT_SHIFT_HW_SSN_SEQ1) & BIT_MASK_HW_SSN_SEQ1)
+#define BIT_SET_HW_SSN_SEQ1(x, v) \
+ (BIT_CLEAR_HW_SSN_SEQ1(x) | BIT_HW_SSN_SEQ1(v))
-/* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */
+/* 2 REG_HW_SEQ2 (Offset 0x04DC) */
-#define BIT_MOREDATA_CTRL1_EN_V2 BIT(18)
+#define BIT_SHIFT_HW_SSN_SEQ2 0
+#define BIT_MASK_HW_SSN_SEQ2 0xfff
+#define BIT_HW_SSN_SEQ2(x) \
+ (((x) & BIT_MASK_HW_SSN_SEQ2) << BIT_SHIFT_HW_SSN_SEQ2)
+#define BITS_HW_SSN_SEQ2 (BIT_MASK_HW_SSN_SEQ2 << BIT_SHIFT_HW_SSN_SEQ2)
+#define BIT_CLEAR_HW_SSN_SEQ2(x) ((x) & (~BITS_HW_SSN_SEQ2))
+#define BIT_GET_HW_SSN_SEQ2(x) \
+ (((x) >> BIT_SHIFT_HW_SSN_SEQ2) & BIT_MASK_HW_SSN_SEQ2)
+#define BIT_SET_HW_SSN_SEQ2(x, v) \
+ (BIT_CLEAR_HW_SSN_SEQ2(x) | BIT_HW_SSN_SEQ2(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_HW_SEQ3 (Offset 0x04DE) */
+#define BIT_SHIFT_CSI_HWSSN_SEL 12
+#define BIT_MASK_CSI_HWSSN_SEL 0x3
+#define BIT_CSI_HWSSN_SEL(x) \
+ (((x) & BIT_MASK_CSI_HWSSN_SEL) << BIT_SHIFT_CSI_HWSSN_SEL)
+#define BITS_CSI_HWSSN_SEL (BIT_MASK_CSI_HWSSN_SEL << BIT_SHIFT_CSI_HWSSN_SEL)
+#define BIT_CLEAR_CSI_HWSSN_SEL(x) ((x) & (~BITS_CSI_HWSSN_SEL))
+#define BIT_GET_CSI_HWSSN_SEL(x) \
+ (((x) >> BIT_SHIFT_CSI_HWSSN_SEL) & BIT_MASK_CSI_HWSSN_SEL)
+#define BIT_SET_CSI_HWSSN_SEL(x, v) \
+ (BIT_CLEAR_CSI_HWSSN_SEL(x) | BIT_CSI_HWSSN_SEL(v))
-/* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */
+#endif
-#define BIT_EN_BCN_TRXRPT BIT(17)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_HW_SEQ3 (Offset 0x04DE) */
+#define BIT_SHIFT_CSI_HWSEQ_SEL 12
+#define BIT_MASK_CSI_HWSEQ_SEL 0x3
+#define BIT_CSI_HWSEQ_SEL(x) \
+ (((x) & BIT_MASK_CSI_HWSEQ_SEL) << BIT_SHIFT_CSI_HWSEQ_SEL)
+#define BITS_CSI_HWSEQ_SEL (BIT_MASK_CSI_HWSEQ_SEL << BIT_SHIFT_CSI_HWSEQ_SEL)
+#define BIT_CLEAR_CSI_HWSEQ_SEL(x) ((x) & (~BITS_CSI_HWSEQ_SEL))
+#define BIT_GET_CSI_HWSEQ_SEL(x) \
+ (((x) >> BIT_SHIFT_CSI_HWSEQ_SEL) & BIT_MASK_CSI_HWSEQ_SEL)
+#define BIT_SET_CSI_HWSEQ_SEL(x, v) \
+ (BIT_CLEAR_CSI_HWSEQ_SEL(x) | BIT_CSI_HWSEQ_SEL(v))
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */
+/* 2 REG_HW_SEQ3 (Offset 0x04DE) */
-#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE BIT(16)
+#define BIT_SHIFT_HW_SSN_SEQ3 0
+#define BIT_MASK_HW_SSN_SEQ3 0xfff
+#define BIT_HW_SSN_SEQ3(x) \
+ (((x) & BIT_MASK_HW_SSN_SEQ3) << BIT_SHIFT_HW_SSN_SEQ3)
+#define BITS_HW_SSN_SEQ3 (BIT_MASK_HW_SSN_SEQ3 << BIT_SHIFT_HW_SSN_SEQ3)
+#define BIT_CLEAR_HW_SSN_SEQ3(x) ((x) & (~BITS_HW_SSN_SEQ3))
+#define BIT_GET_HW_SSN_SEQ3(x) \
+ (((x) >> BIT_SHIFT_HW_SSN_SEQ3) & BIT_MASK_HW_SSN_SEQ3)
+#define BIT_SET_HW_SSN_SEQ3(x, v) \
+ (BIT_CLEAR_HW_SSN_SEQ3(x) | BIT_HW_SSN_SEQ3(v))
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8822B_SUPPORT)
+/* 2 REG_CSI_SEQ (Offset 0x04DE) */
+#define BIT_SHIFT_HW_CSI_SEQ 0
+#define BIT_MASK_HW_CSI_SEQ 0xfff
+#define BIT_HW_CSI_SEQ(x) (((x) & BIT_MASK_HW_CSI_SEQ) << BIT_SHIFT_HW_CSI_SEQ)
+#define BITS_HW_CSI_SEQ (BIT_MASK_HW_CSI_SEQ << BIT_SHIFT_HW_CSI_SEQ)
+#define BIT_CLEAR_HW_CSI_SEQ(x) ((x) & (~BITS_HW_CSI_SEQ))
+#define BIT_GET_HW_CSI_SEQ(x) \
+ (((x) >> BIT_SHIFT_HW_CSI_SEQ) & BIT_MASK_HW_CSI_SEQ)
+#define BIT_SET_HW_CSI_SEQ(x, v) (BIT_CLEAR_HW_CSI_SEQ(x) | BIT_HW_CSI_SEQ(v))
-/* 2 REG_DUMMY_PAGE4_V1 (Offset 0x04FC) */
+#endif
-#define BIT_BCN_EN_EXTHWSEQ BIT(1)
-#define BIT_BCN_EN_HWSEQ BIT(0)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT)
-#endif
+/* 2 REG_NULL_PKT_STATUS_V1 (Offset 0x04E0) */
+#define BIT_SHIFT_PTCL_TOTAL_PG_V1 2
+#define BIT_MASK_PTCL_TOTAL_PG_V1 0x1fff
+#define BIT_PTCL_TOTAL_PG_V1(x) \
+ (((x) & BIT_MASK_PTCL_TOTAL_PG_V1) << BIT_SHIFT_PTCL_TOTAL_PG_V1)
+#define BITS_PTCL_TOTAL_PG_V1 \
+ (BIT_MASK_PTCL_TOTAL_PG_V1 << BIT_SHIFT_PTCL_TOTAL_PG_V1)
+#define BIT_CLEAR_PTCL_TOTAL_PG_V1(x) ((x) & (~BITS_PTCL_TOTAL_PG_V1))
+#define BIT_GET_PTCL_TOTAL_PG_V1(x) \
+ (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V1) & BIT_MASK_PTCL_TOTAL_PG_V1)
+#define BIT_SET_PTCL_TOTAL_PG_V1(x, v) \
+ (BIT_CLEAR_PTCL_TOTAL_PG_V1(x) | BIT_PTCL_TOTAL_PG_V1(v))
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_MOREDATA (Offset 0x04FE) */
+/* 2 REG_NULL_PKT_STATUS_V1 (Offset 0x04E0) */
-#define BIT_MOREDATA_CTRL2_EN_V1 BIT(3)
-#define BIT_MOREDATA_CTRL1_EN_V1 BIT(2)
-#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE_V1 BIT(0)
+#define BIT_SHIFT_PTCL_TOTAL_PG_V2 2
+#define BIT_MASK_PTCL_TOTAL_PG_V2 0x3fff
+#define BIT_PTCL_TOTAL_PG_V2(x) \
+ (((x) & BIT_MASK_PTCL_TOTAL_PG_V2) << BIT_SHIFT_PTCL_TOTAL_PG_V2)
+#define BITS_PTCL_TOTAL_PG_V2 \
+ (BIT_MASK_PTCL_TOTAL_PG_V2 << BIT_SHIFT_PTCL_TOTAL_PG_V2)
+#define BIT_CLEAR_PTCL_TOTAL_PG_V2(x) ((x) & (~BITS_PTCL_TOTAL_PG_V2))
+#define BIT_GET_PTCL_TOTAL_PG_V2(x) \
+ (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2) & BIT_MASK_PTCL_TOTAL_PG_V2)
+#define BIT_SET_PTCL_TOTAL_PG_V2(x, v) \
+ (BIT_CLEAR_PTCL_TOTAL_PG_V2(x) | BIT_PTCL_TOTAL_PG_V2(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_NULL_PKT_STATUS (Offset 0x04E0) */
+#define BIT_TX_NULL_1 BIT(1)
+#define BIT_TX_NULL_0 BIT(0)
-/* 2 REG_EDCA_VO_PARAM (Offset 0x0500) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_TXOPLIMIT 16
-#define BIT_MASK_TXOPLIMIT 0x7ff
-#define BIT_TXOPLIMIT(x) (((x) & BIT_MASK_TXOPLIMIT) << BIT_SHIFT_TXOPLIMIT)
-#define BIT_GET_TXOPLIMIT(x) (((x) >> BIT_SHIFT_TXOPLIMIT) & BIT_MASK_TXOPLIMIT)
+/* 2 REG_PTCL_ERR_STATUS_V1 (Offset 0x04E2) */
+#define BIT_MUARB_SEARCH_ERR BIT(14)
+#define BIT_MU_BFEN_ERR BIT(12)
+#define BIT_NDPA_DROPNULL_ERR BIT(11)
+#define BIT_NDPA_DROPPKT_ERR BIT(10)
+#define BIT_PTCL_PKYIN_ERR BIT(9)
+#define BIT_PTCL_QSELCNL_ERR BIT(8)
-#define BIT_SHIFT_CW 8
-#define BIT_MASK_CW 0xff
-#define BIT_CW(x) (((x) & BIT_MASK_CW) << BIT_SHIFT_CW)
-#define BIT_GET_CW(x) (((x) >> BIT_SHIFT_CW) & BIT_MASK_CW)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_AIFS 0
-#define BIT_MASK_AIFS 0xff
-#define BIT_AIFS(x) (((x) & BIT_MASK_AIFS) << BIT_SHIFT_AIFS)
-#define BIT_GET_AIFS(x) (((x) >> BIT_SHIFT_AIFS) & BIT_MASK_AIFS)
+/* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */
+#define BIT_PTCL_RATE_TABLE_INVALID BIT(7)
+#define BIT_FTM_T2R_ERROR BIT(6)
-/* 2 REG_BCNTCFG (Offset 0x0510) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_BCNCW_MAX 12
-#define BIT_MASK_BCNCW_MAX 0xf
-#define BIT_BCNCW_MAX(x) (((x) & BIT_MASK_BCNCW_MAX) << BIT_SHIFT_BCNCW_MAX)
-#define BIT_GET_BCNCW_MAX(x) (((x) >> BIT_SHIFT_BCNCW_MAX) & BIT_MASK_BCNCW_MAX)
+/* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */
+#define BIT_PTCL_ERR0 BIT(5)
-#define BIT_SHIFT_BCNCW_MIN 8
-#define BIT_MASK_BCNCW_MIN 0xf
-#define BIT_BCNCW_MIN(x) (((x) & BIT_MASK_BCNCW_MIN) << BIT_SHIFT_BCNCW_MIN)
-#define BIT_GET_BCNCW_MIN(x) (((x) >> BIT_SHIFT_BCNCW_MIN) & BIT_MASK_BCNCW_MIN)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_BCNIFS 0
-#define BIT_MASK_BCNIFS 0xff
-#define BIT_BCNIFS(x) (((x) & BIT_MASK_BCNIFS) << BIT_SHIFT_BCNIFS)
-#define BIT_GET_BCNIFS(x) (((x) >> BIT_SHIFT_BCNIFS) & BIT_MASK_BCNIFS)
+/* 2 REG_PTCL_ERR_STATUS_V1 (Offset 0x04E2) */
+#define BIT_TXTIMEOUT_ERR BIT(5)
-/* 2 REG_PIFS (Offset 0x0512) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_PIFS 0
-#define BIT_MASK_PIFS 0xff
-#define BIT_PIFS(x) (((x) & BIT_MASK_PIFS) << BIT_SHIFT_PIFS)
-#define BIT_GET_PIFS(x) (((x) >> BIT_SHIFT_PIFS) & BIT_MASK_PIFS)
+/* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */
+#define BIT_PTCL_ERR1 BIT(4)
-/* 2 REG_RDG_PIFS (Offset 0x0513) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_RDG_PIFS 0
-#define BIT_MASK_RDG_PIFS 0xff
-#define BIT_RDG_PIFS(x) (((x) & BIT_MASK_RDG_PIFS) << BIT_SHIFT_RDG_PIFS)
-#define BIT_GET_RDG_PIFS(x) (((x) >> BIT_SHIFT_RDG_PIFS) & BIT_MASK_RDG_PIFS)
+/* 2 REG_PTCL_ERR_STATUS_V1 (Offset 0x04E2) */
+#define BIT_NULLPAGE_ERR BIT(4)
-/* 2 REG_SIFS (Offset 0x0514) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_SIFS_OFDM_TRX 24
-#define BIT_MASK_SIFS_OFDM_TRX 0xff
-#define BIT_SIFS_OFDM_TRX(x) (((x) & BIT_MASK_SIFS_OFDM_TRX) << BIT_SHIFT_SIFS_OFDM_TRX)
-#define BIT_GET_SIFS_OFDM_TRX(x) (((x) >> BIT_SHIFT_SIFS_OFDM_TRX) & BIT_MASK_SIFS_OFDM_TRX)
+/* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */
+#define BIT_PTCL_ERR2 BIT(3)
-#define BIT_SHIFT_SIFS_CCK_TRX 16
-#define BIT_MASK_SIFS_CCK_TRX 0xff
-#define BIT_SIFS_CCK_TRX(x) (((x) & BIT_MASK_SIFS_CCK_TRX) << BIT_SHIFT_SIFS_CCK_TRX)
-#define BIT_GET_SIFS_CCK_TRX(x) (((x) >> BIT_SHIFT_SIFS_CCK_TRX) & BIT_MASK_SIFS_CCK_TRX)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_SIFS_OFDM_CTX 8
-#define BIT_MASK_SIFS_OFDM_CTX 0xff
-#define BIT_SIFS_OFDM_CTX(x) (((x) & BIT_MASK_SIFS_OFDM_CTX) << BIT_SHIFT_SIFS_OFDM_CTX)
-#define BIT_GET_SIFS_OFDM_CTX(x) (((x) >> BIT_SHIFT_SIFS_OFDM_CTX) & BIT_MASK_SIFS_OFDM_CTX)
+/* 2 REG_PTCL_ERR_STATUS_V1 (Offset 0x04E2) */
+#define BIT_CONTENTION_ERR BIT(3)
-#define BIT_SHIFT_SIFS_CCK_CTX 0
-#define BIT_MASK_SIFS_CCK_CTX 0xff
-#define BIT_SIFS_CCK_CTX(x) (((x) & BIT_MASK_SIFS_CCK_CTX) << BIT_SHIFT_SIFS_CCK_CTX)
-#define BIT_GET_SIFS_CCK_CTX(x) (((x) >> BIT_SHIFT_SIFS_CCK_CTX) & BIT_MASK_SIFS_CCK_CTX)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_TSFTR_SYN_OFFSET (Offset 0x0518) */
+/* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */
+#define BIT_PTCL_ERR3 BIT(2)
-#define BIT_SHIFT_TSFTR_SNC_OFFSET 0
-#define BIT_MASK_TSFTR_SNC_OFFSET 0xffff
-#define BIT_TSFTR_SNC_OFFSET(x) (((x) & BIT_MASK_TSFTR_SNC_OFFSET) << BIT_SHIFT_TSFTR_SNC_OFFSET)
-#define BIT_GET_TSFTR_SNC_OFFSET(x) (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET) & BIT_MASK_TSFTR_SNC_OFFSET)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_AGGR_BREAK_TIME (Offset 0x051A) */
+/* 2 REG_PTCL_ERR_STATUS_V1 (Offset 0x04E2) */
+#define BIT_HEADNULL_ERR BIT(2)
-#define BIT_SHIFT_AGGR_BK_TIME 0
-#define BIT_MASK_AGGR_BK_TIME 0xff
-#define BIT_AGGR_BK_TIME(x) (((x) & BIT_MASK_AGGR_BK_TIME) << BIT_SHIFT_AGGR_BK_TIME)
-#define BIT_GET_AGGR_BK_TIME(x) (((x) >> BIT_SHIFT_AGGR_BK_TIME) & BIT_MASK_AGGR_BK_TIME)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_SLOT (Offset 0x051B) */
+/* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */
+#define BIT_PTCL_ERR4 BIT(1)
-#define BIT_SHIFT_SLOT 0
-#define BIT_MASK_SLOT 0xff
-#define BIT_SLOT(x) (((x) & BIT_MASK_SLOT) << BIT_SHIFT_SLOT)
-#define BIT_GET_SLOT(x) (((x) >> BIT_SHIFT_SLOT) & BIT_MASK_SLOT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_TX_PTCL_CTRL (Offset 0x0520) */
+/* 2 REG_PTCL_ERR_STATUS_V1 (Offset 0x04E2) */
-#define BIT_DIS_EDCCA BIT(15)
-#define BIT_DIS_CCA BIT(14)
-#define BIT_LSIG_TXOP_TXCMD_NAV BIT(13)
-#define BIT_SIFS_BK_EN BIT(12)
-
-#define BIT_SHIFT_TXQ_NAV_MSK 8
-#define BIT_MASK_TXQ_NAV_MSK 0xf
-#define BIT_TXQ_NAV_MSK(x) (((x) & BIT_MASK_TXQ_NAV_MSK) << BIT_SHIFT_TXQ_NAV_MSK)
-#define BIT_GET_TXQ_NAV_MSK(x) (((x) >> BIT_SHIFT_TXQ_NAV_MSK) & BIT_MASK_TXQ_NAV_MSK)
-
-#define BIT_DIS_CW BIT(7)
-#define BIT_NAV_END_TXOP BIT(6)
-#define BIT_RDG_END_TXOP BIT(5)
-#define BIT_AC_INBCN_HOLD BIT(4)
-#define BIT_MGTQ_TXOP_EN BIT(3)
-#define BIT_MGTQ_RTSMF_EN BIT(2)
-#define BIT_HIQ_RTSMF_EN BIT(1)
-#define BIT_BCN_RTSMF_EN BIT(0)
+#define BIT_OVERFLOW_ERR BIT(1)
-/* 2 REG_TXPAUSE (Offset 0x0522) */
+#endif
-#define BIT_STOP_BCN_HI_MGT BIT(7)
-#define BIT_MAC_STOPBCNQ BIT(6)
-#define BIT_MAC_STOPHIQ BIT(5)
-#define BIT_MAC_STOPMGQ BIT(4)
-#define BIT_MAC_STOPBK BIT(3)
-#define BIT_MAC_STOPBE BIT(2)
-#define BIT_MAC_STOPVI BIT(1)
-#define BIT_MAC_STOPVO BIT(0)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_DIS_TXREQ_CLR (Offset 0x0523) */
+/* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */
-#define BIT_DIS_BT_CCA BIT(7)
+#define BIT_PTCL_ERR5 BIT(0)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
-
-/* 2 REG_DIS_TXREQ_CLR (Offset 0x0523) */
+/* 2 REG_PTCL_ERR_STATUS_V1 (Offset 0x04E2) */
-#define BIT_DIS_TXREQ_CLR_CPUMGQ BIT(6)
+#define BIT_QUEUE_INDEX_ERR BIT(0)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_NULL_PKT_STATUS_EXTEND (Offset 0x04E3) */
+#define BIT_CLI3_TX_NULL_1 BIT(7)
+#define BIT_CLI3_TX_NULL_0 BIT(6)
+#define BIT_CLI2_TX_NULL_1 BIT(5)
+#define BIT_CLI2_TX_NULL_0 BIT(4)
+#define BIT_CLI1_TX_NULL_1 BIT(3)
+#define BIT_CLI1_TX_NULL_0 BIT(2)
+#define BIT_CLI0_TX_NULL_1 BIT(1)
-/* 2 REG_DIS_TXREQ_CLR (Offset 0x0523) */
+#endif
-#define BIT_DIS_TXREQ_CLR_HI BIT(5)
-#define BIT_DIS_TXREQ_CLR_MGQ BIT(4)
-#define BIT_DIS_TXREQ_CLR_VO BIT(3)
-#define BIT_DIS_TXREQ_CLR_VI BIT(2)
-#define BIT_DIS_TXREQ_CLR_BE BIT(1)
-#define BIT_DIS_TXREQ_CLR_BK BIT(0)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_RD_CTRL (Offset 0x0524) */
+/* 2 REG_PTCL_PKT_NUM (Offset 0x04E3) */
-#define BIT_EN_CLR_TXREQ_INCCA BIT(15)
-#define BIT_DIS_TX_OVER_BCNQ BIT(14)
+#define BIT_SHIFT_PTCL_TOTAL_PG 0
+#define BIT_MASK_PTCL_TOTAL_PG 0xff
+#define BIT_PTCL_TOTAL_PG(x) \
+ (((x) & BIT_MASK_PTCL_TOTAL_PG) << BIT_SHIFT_PTCL_TOTAL_PG)
+#define BITS_PTCL_TOTAL_PG (BIT_MASK_PTCL_TOTAL_PG << BIT_SHIFT_PTCL_TOTAL_PG)
+#define BIT_CLEAR_PTCL_TOTAL_PG(x) ((x) & (~BITS_PTCL_TOTAL_PG))
+#define BIT_GET_PTCL_TOTAL_PG(x) \
+ (((x) >> BIT_SHIFT_PTCL_TOTAL_PG) & BIT_MASK_PTCL_TOTAL_PG)
+#define BIT_SET_PTCL_TOTAL_PG(x, v) \
+ (BIT_CLEAR_PTCL_TOTAL_PG(x) | BIT_PTCL_TOTAL_PG(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-
-/* 2 REG_RD_CTRL (Offset 0x0524) */
+/* 2 REG_NULL_PKT_STATUS_EXTEND (Offset 0x04E3) */
-#define BIT_EN_BCNERR_INCCCA BIT(13)
+#define BIT_CLI0_TX_NULL_0 BIT(0)
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
-
-/* 2 REG_RD_CTRL (Offset 0x0524) */
+/* 2 REG_TRXRPT_MISS_CNT (Offset 0x04E3) */
-#define BIT_EN_BCNERR_INCCA BIT(13)
-#define BIT_EN_BCNERR_INEDCCA BIT(12)
+#define BIT_SHIFT_TRXRPT_MISS_CNT 0
+#define BIT_MASK_TRXRPT_MISS_CNT 0x7
+#define BIT_TRXRPT_MISS_CNT(x) \
+ (((x) & BIT_MASK_TRXRPT_MISS_CNT) << BIT_SHIFT_TRXRPT_MISS_CNT)
+#define BITS_TRXRPT_MISS_CNT \
+ (BIT_MASK_TRXRPT_MISS_CNT << BIT_SHIFT_TRXRPT_MISS_CNT)
+#define BIT_CLEAR_TRXRPT_MISS_CNT(x) ((x) & (~BITS_TRXRPT_MISS_CNT))
+#define BIT_GET_TRXRPT_MISS_CNT(x) \
+ (((x) >> BIT_SHIFT_TRXRPT_MISS_CNT) & BIT_MASK_TRXRPT_MISS_CNT)
+#define BIT_SET_TRXRPT_MISS_CNT(x, v) \
+ (BIT_CLEAR_TRXRPT_MISS_CNT(x) | BIT_TRXRPT_MISS_CNT(v))
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_VIDEO_ENHANCEMENT_FUN (Offset 0x04E4) */
+#define BIT_MAX_PRETX_AGGR_EN BIT(19)
-/* 2 REG_RD_CTRL (Offset 0x0524) */
+#define BIT_SHIFT_MAX_PRETX_AGGR_TIME 8
+#define BIT_MASK_MAX_PRETX_AGGR_TIME 0x7ff
+#define BIT_MAX_PRETX_AGGR_TIME(x) \
+ (((x) & BIT_MASK_MAX_PRETX_AGGR_TIME) << BIT_SHIFT_MAX_PRETX_AGGR_TIME)
+#define BITS_MAX_PRETX_AGGR_TIME \
+ (BIT_MASK_MAX_PRETX_AGGR_TIME << BIT_SHIFT_MAX_PRETX_AGGR_TIME)
+#define BIT_CLEAR_MAX_PRETX_AGGR_TIME(x) ((x) & (~BITS_MAX_PRETX_AGGR_TIME))
+#define BIT_GET_MAX_PRETX_AGGR_TIME(x) \
+ (((x) >> BIT_SHIFT_MAX_PRETX_AGGR_TIME) & BIT_MASK_MAX_PRETX_AGGR_TIME)
+#define BIT_SET_MAX_PRETX_AGGR_TIME(x, v) \
+ (BIT_CLEAR_MAX_PRETX_AGGR_TIME(x) | BIT_MAX_PRETX_AGGR_TIME(v))
-#define BIT_EDCCA_MSK_CNTDOWN_EN BIT(11)
-#define BIT_DIS_TXOP_CFE BIT(10)
-#define BIT_DIS_LSIG_CFE BIT(9)
-#define BIT_DIS_STBC_CFE BIT(8)
-#define BIT_BKQ_RD_INIT_EN BIT(7)
-#define BIT_BEQ_RD_INIT_EN BIT(6)
-#define BIT_VIQ_RD_INIT_EN BIT(5)
-#define BIT_VOQ_RD_INIT_EN BIT(4)
-#define BIT_BKQ_RD_RESP_EN BIT(3)
-#define BIT_BEQ_RD_RESP_EN BIT(2)
-#define BIT_VIQ_RD_RESP_EN BIT(1)
-#define BIT_VOQ_RD_RESP_EN BIT(0)
+#define BIT_HGQ_DEL_EN BIT(7)
-/* 2 REG_MBSSID_CTRL (Offset 0x0526) */
+#endif
-#define BIT_MBID_BCNQ7_EN BIT(7)
-#define BIT_MBID_BCNQ6_EN BIT(6)
-#define BIT_MBID_BCNQ5_EN BIT(5)
-#define BIT_MBID_BCNQ4_EN BIT(4)
-#define BIT_MBID_BCNQ3_EN BIT(3)
-#define BIT_MBID_BCNQ2_EN BIT(2)
-#define BIT_MBID_BCNQ1_EN BIT(1)
-#define BIT_MBID_BCNQ0_EN BIT(0)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_P2PPS_CTRL (Offset 0x0527) */
+/* 2 REG_VIDEO_ENHANCEMENT_FUN (Offset 0x04E4) */
-#define BIT_P2P_CTW_ALLSTASLEEP BIT(7)
-#define BIT_P2P_OFF_DISTX_EN BIT(6)
-#define BIT_PWR_MGT_EN BIT(5)
+#define BIT_HIQ_DROP BIT(7)
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_VIDEO_ENHANCEMENT_FUN (Offset 0x04E4) */
+#define BIT_MGQ_DEL_EN BIT(6)
-/* 2 REG_P2PPS_CTRL (Offset 0x0527) */
+#endif
-#define BIT_P2P_BCN_AREA_EN BIT(4)
-#define BIT_P2P_CTWND_EN BIT(3)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_VIDEO_ENHANCEMENT_FUN (Offset 0x04E4) */
+#define BIT_MGQ_DROP BIT(6)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-/* 2 REG_P2PPS_CTRL (Offset 0x0527) */
+/* 2 REG_VIDEO_ENHANCEMENT_FUN (Offset 0x04E4) */
-#define BIT_P2P_NOA1_EN BIT(2)
-#define BIT_P2P_NOA0_EN BIT(1)
+#define BIT_VIDEO_JUST_DROP BIT(1)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_NULL_PKT_STATUS_V2 (Offset 0x04E4) */
+#define BIT_TX_NULL_1_V1 BIT(1)
-/* 2 REG_P2PPS_CTRL (Offset 0x0527) */
+#endif
-#define BIT_P2P_BCN_SEL BIT(0)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-#endif
+/* 2 REG_VIDEO_ENHANCEMENT_FUN (Offset 0x04E4) */
+#define BIT_VIDEO_ENHANCEMENT_FUN_EN BIT(0)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_PKT_LIFETIME_CTRL (Offset 0x0528) */
+/* 2 REG_NULL_PKT_STATUS_V2 (Offset 0x04E4) */
-#define BIT_EN_P2P_CTWND1 BIT(23)
+#define BIT_TX_NULL_0_V1 BIT(0)
#endif
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_PRECNT_CTRL (Offset 0x04E5) */
+#define BIT_EN_PRECNT BIT(11)
+#define BIT_DATA_FW_STS_FILTER BIT(2)
+#define BIT_CTRL_FW_STS_FILTER BIT(1)
-/* 2 REG_PKT_LIFETIME_CTRL (Offset 0x0528) */
+#define BIT_SHIFT_PRECNT_TH 0
+#define BIT_MASK_PRECNT_TH 0x7ff
+#define BIT_PRECNT_TH(x) (((x) & BIT_MASK_PRECNT_TH) << BIT_SHIFT_PRECNT_TH)
+#define BITS_PRECNT_TH (BIT_MASK_PRECNT_TH << BIT_SHIFT_PRECNT_TH)
+#define BIT_CLEAR_PRECNT_TH(x) ((x) & (~BITS_PRECNT_TH))
+#define BIT_GET_PRECNT_TH(x) (((x) >> BIT_SHIFT_PRECNT_TH) & BIT_MASK_PRECNT_TH)
+#define BIT_SET_PRECNT_TH(x, v) (BIT_CLEAR_PRECNT_TH(x) | BIT_PRECNT_TH(v))
-#define BIT_EN_TBTT_AREA_FOR_BB BIT(23)
+#define BIT_MGNT_FW_STS_FILTER BIT(0)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_NULL_PKT_STATUS_EXTEND_V1 (Offset 0x04E7) */
+#define BIT_CLI3_TX_NULL_1_V1 BIT(7)
+#define BIT_CLI3_TX_NULL_0_V1 BIT(6)
+#define BIT_CLI2_TX_NULL_1_V1 BIT(5)
+#define BIT_CLI2_TX_NULL_0_V1 BIT(4)
+#define BIT_CLI1_TX_NULL_1_V1 BIT(3)
+#define BIT_CLI1_TX_NULL_0_V1 BIT(2)
+#define BIT_CLI0_TX_NULL_1_V1 BIT(1)
+#define BIT_CLI0_TX_NULL_0_V1 BIT(0)
-/* 2 REG_PKT_LIFETIME_CTRL (Offset 0x0528) */
+#endif
-#define BIT_EN_BKF_CLR_TXREQ BIT(22)
-#define BIT_EN_TSFBIT32_RST_P2P BIT(21)
-#define BIT_EN_BCN_TX_BTCCA BIT(20)
-#define BIT_DIS_PKT_TX_ATIM BIT(19)
-#define BIT_DIS_BCN_DIS_CTN BIT(18)
-#define BIT_EN_NAVEND_RST_TXOP BIT(17)
-#define BIT_EN_FILTER_CCA BIT(16)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_CCA_FILTER_THRS 8
-#define BIT_MASK_CCA_FILTER_THRS 0xff
-#define BIT_CCA_FILTER_THRS(x) (((x) & BIT_MASK_CCA_FILTER_THRS) << BIT_SHIFT_CCA_FILTER_THRS)
-#define BIT_GET_CCA_FILTER_THRS(x) (((x) >> BIT_SHIFT_CCA_FILTER_THRS) & BIT_MASK_CCA_FILTER_THRS)
+/* 2 REG_BT_POLLUTE_PKT_CNT (Offset 0x04E8) */
+#define BIT_SHIFT_BT_POLLUTE_PKT_CNT 0
+#define BIT_MASK_BT_POLLUTE_PKT_CNT 0xffff
+#define BIT_BT_POLLUTE_PKT_CNT(x) \
+ (((x) & BIT_MASK_BT_POLLUTE_PKT_CNT) << BIT_SHIFT_BT_POLLUTE_PKT_CNT)
+#define BITS_BT_POLLUTE_PKT_CNT \
+ (BIT_MASK_BT_POLLUTE_PKT_CNT << BIT_SHIFT_BT_POLLUTE_PKT_CNT)
+#define BIT_CLEAR_BT_POLLUTE_PKT_CNT(x) ((x) & (~BITS_BT_POLLUTE_PKT_CNT))
+#define BIT_GET_BT_POLLUTE_PKT_CNT(x) \
+ (((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT) & BIT_MASK_BT_POLLUTE_PKT_CNT)
+#define BIT_SET_BT_POLLUTE_PKT_CNT(x, v) \
+ (BIT_CLEAR_BT_POLLUTE_PKT_CNT(x) | BIT_BT_POLLUTE_PKT_CNT(v))
-#define BIT_SHIFT_EDCCA_THRS 0
-#define BIT_MASK_EDCCA_THRS 0xff
-#define BIT_EDCCA_THRS(x) (((x) & BIT_MASK_EDCCA_THRS) << BIT_SHIFT_EDCCA_THRS)
-#define BIT_GET_EDCCA_THRS(x) (((x) >> BIT_SHIFT_EDCCA_THRS) & BIT_MASK_EDCCA_THRS)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_P2PPS_SPEC_STATE (Offset 0x052B) */
+/* 2 REG_PTCL_DBG (Offset 0x04EC) */
-#define BIT_SPEC_POWER_STATE BIT(7)
-#define BIT_SPEC_CTWINDOW_ON BIT(6)
-#define BIT_SPEC_BEACON_AREA_ON BIT(5)
-#define BIT_SPEC_CTWIN_EARLY_DISTX BIT(4)
-#define BIT_SPEC_NOA1_OFF_PERIOD BIT(3)
-#define BIT_SPEC_FORCE_DOZE1 BIT(2)
-#define BIT_SPEC_NOA0_OFF_PERIOD BIT(1)
-#define BIT_SPEC_FORCE_DOZE0 BIT(0)
+#define BIT_SHIFT_PTCL_DBG 0
+#define BIT_MASK_PTCL_DBG 0xffffffffL
+#define BIT_PTCL_DBG(x) (((x) & BIT_MASK_PTCL_DBG) << BIT_SHIFT_PTCL_DBG)
+#define BITS_PTCL_DBG (BIT_MASK_PTCL_DBG << BIT_SHIFT_PTCL_DBG)
+#define BIT_CLEAR_PTCL_DBG(x) ((x) & (~BITS_PTCL_DBG))
+#define BIT_GET_PTCL_DBG(x) (((x) >> BIT_SHIFT_PTCL_DBG) & BIT_MASK_PTCL_DBG)
+#define BIT_SET_PTCL_DBG(x, v) (BIT_CLEAR_PTCL_DBG(x) | BIT_PTCL_DBG(v))
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_DROP_NUM (Offset 0x04EC) */
+#define BIT_SHIFT_DROP_PKT_NUM 0
+#define BIT_MASK_DROP_PKT_NUM 0xffff
+#define BIT_DROP_PKT_NUM(x) \
+ (((x) & BIT_MASK_DROP_PKT_NUM) << BIT_SHIFT_DROP_PKT_NUM)
+#define BITS_DROP_PKT_NUM (BIT_MASK_DROP_PKT_NUM << BIT_SHIFT_DROP_PKT_NUM)
+#define BIT_CLEAR_DROP_PKT_NUM(x) ((x) & (~BITS_DROP_PKT_NUM))
+#define BIT_GET_DROP_PKT_NUM(x) \
+ (((x) >> BIT_SHIFT_DROP_PKT_NUM) & BIT_MASK_DROP_PKT_NUM)
+#define BIT_SET_DROP_PKT_NUM(x, v) \
+ (BIT_CLEAR_DROP_PKT_NUM(x) | BIT_DROP_PKT_NUM(v))
-/* 2 REG_QUEUE_INCOL_THR (Offset 0x0538) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_BK_QUEUE_THR 24
-#define BIT_MASK_BK_QUEUE_THR 0xff
-#define BIT_BK_QUEUE_THR(x) (((x) & BIT_MASK_BK_QUEUE_THR) << BIT_SHIFT_BK_QUEUE_THR)
-#define BIT_GET_BK_QUEUE_THR(x) (((x) >> BIT_SHIFT_BK_QUEUE_THR) & BIT_MASK_BK_QUEUE_THR)
+/* 2 REG_PTCL_TX_RPT (Offset 0x04F0) */
+#define BIT_SHIFT_AC_TX_RPT_INFO 0
+#define BIT_MASK_AC_TX_RPT_INFO 0xffffffffffffffffL
+#define BIT_AC_TX_RPT_INFO(x) \
+ (((x) & BIT_MASK_AC_TX_RPT_INFO) << BIT_SHIFT_AC_TX_RPT_INFO)
+#define BITS_AC_TX_RPT_INFO \
+ (BIT_MASK_AC_TX_RPT_INFO << BIT_SHIFT_AC_TX_RPT_INFO)
+#define BIT_CLEAR_AC_TX_RPT_INFO(x) ((x) & (~BITS_AC_TX_RPT_INFO))
+#define BIT_GET_AC_TX_RPT_INFO(x) \
+ (((x) >> BIT_SHIFT_AC_TX_RPT_INFO) & BIT_MASK_AC_TX_RPT_INFO)
+#define BIT_SET_AC_TX_RPT_INFO(x, v) \
+ (BIT_CLEAR_AC_TX_RPT_INFO(x) | BIT_AC_TX_RPT_INFO(v))
-#define BIT_SHIFT_BE_QUEUE_THR 16
-#define BIT_MASK_BE_QUEUE_THR 0xff
-#define BIT_BE_QUEUE_THR(x) (((x) & BIT_MASK_BE_QUEUE_THR) << BIT_SHIFT_BE_QUEUE_THR)
-#define BIT_GET_BE_QUEUE_THR(x) (((x) >> BIT_SHIFT_BE_QUEUE_THR) & BIT_MASK_BE_QUEUE_THR)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_VI_QUEUE_THR 8
-#define BIT_MASK_VI_QUEUE_THR 0xff
-#define BIT_VI_QUEUE_THR(x) (((x) & BIT_MASK_VI_QUEUE_THR) << BIT_SHIFT_VI_QUEUE_THR)
-#define BIT_GET_VI_QUEUE_THR(x) (((x) >> BIT_SHIFT_VI_QUEUE_THR) & BIT_MASK_VI_QUEUE_THR)
+/* 2 REG_TXOP_EXTRA_CTRL (Offset 0x04F0) */
+#define BIT_TXOP_EFFICIENCY_EN BIT(0)
-#define BIT_SHIFT_VO_QUEUE_THR 0
-#define BIT_MASK_VO_QUEUE_THR 0xff
-#define BIT_VO_QUEUE_THR(x) (((x) & BIT_MASK_VO_QUEUE_THR) << BIT_SHIFT_VO_QUEUE_THR)
-#define BIT_GET_VO_QUEUE_THR(x) (((x) >> BIT_SHIFT_VO_QUEUE_THR) & BIT_MASK_VO_QUEUE_THR)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */
+/* 2 REG_BT_POLLUTE_PKTCNT (Offset 0x04F0) */
-#define BIT_QUEUE_INCOL_EN BIT(16)
+#define BIT_SHIFT_BT_POLLUTE_PKTCNT 0
+#define BIT_MASK_BT_POLLUTE_PKTCNT 0xffff
+#define BIT_BT_POLLUTE_PKTCNT(x) \
+ (((x) & BIT_MASK_BT_POLLUTE_PKTCNT) << BIT_SHIFT_BT_POLLUTE_PKTCNT)
+#define BITS_BT_POLLUTE_PKTCNT \
+ (BIT_MASK_BT_POLLUTE_PKTCNT << BIT_SHIFT_BT_POLLUTE_PKTCNT)
+#define BIT_CLEAR_BT_POLLUTE_PKTCNT(x) ((x) & (~BITS_BT_POLLUTE_PKTCNT))
+#define BIT_GET_BT_POLLUTE_PKTCNT(x) \
+ (((x) >> BIT_SHIFT_BT_POLLUTE_PKTCNT) & BIT_MASK_BT_POLLUTE_PKTCNT)
+#define BIT_SET_BT_POLLUTE_PKTCNT(x, v) \
+ (BIT_CLEAR_BT_POLLUTE_PKTCNT(x) | BIT_BT_POLLUTE_PKTCNT(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
-
-/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */
+/* 2 REG_CPUMGQ_TIMER_CTRL2 (Offset 0x04F4) */
+#define BIT_SHIFT_TRI_HEAD_ADDR 16
+#define BIT_MASK_TRI_HEAD_ADDR 0xfff
+#define BIT_TRI_HEAD_ADDR(x) \
+ (((x) & BIT_MASK_TRI_HEAD_ADDR) << BIT_SHIFT_TRI_HEAD_ADDR)
+#define BITS_TRI_HEAD_ADDR (BIT_MASK_TRI_HEAD_ADDR << BIT_SHIFT_TRI_HEAD_ADDR)
+#define BIT_CLEAR_TRI_HEAD_ADDR(x) ((x) & (~BITS_TRI_HEAD_ADDR))
+#define BIT_GET_TRI_HEAD_ADDR(x) \
+ (((x) >> BIT_SHIFT_TRI_HEAD_ADDR) & BIT_MASK_TRI_HEAD_ADDR)
+#define BIT_SET_TRI_HEAD_ADDR(x, v) \
+ (BIT_CLEAR_TRI_HEAD_ADDR(x) | BIT_TRI_HEAD_ADDR(v))
-#define BIT_SHIFT_BK_TRIGGER_NUM_V1 12
-#define BIT_MASK_BK_TRIGGER_NUM_V1 0xf
-#define BIT_BK_TRIGGER_NUM_V1(x) (((x) & BIT_MASK_BK_TRIGGER_NUM_V1) << BIT_SHIFT_BK_TRIGGER_NUM_V1)
-#define BIT_GET_BK_TRIGGER_NUM_V1(x) (((x) >> BIT_SHIFT_BK_TRIGGER_NUM_V1) & BIT_MASK_BK_TRIGGER_NUM_V1)
+#define BIT_DROP_TH_EN BIT(8)
+#define BIT_SHIFT_DROP_TH 0
+#define BIT_MASK_DROP_TH 0xff
+#define BIT_DROP_TH(x) (((x) & BIT_MASK_DROP_TH) << BIT_SHIFT_DROP_TH)
+#define BITS_DROP_TH (BIT_MASK_DROP_TH << BIT_SHIFT_DROP_TH)
+#define BIT_CLEAR_DROP_TH(x) ((x) & (~BITS_DROP_TH))
+#define BIT_GET_DROP_TH(x) (((x) >> BIT_SHIFT_DROP_TH) & BIT_MASK_DROP_TH)
+#define BIT_SET_DROP_TH(x, v) (BIT_CLEAR_DROP_TH(x) | BIT_DROP_TH(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8822B_SUPPORT)
+/* 2 REG_PTCL_DBG_OUT (Offset 0x04F8) */
+#define BIT_SHIFT_PTCL_DBG_OUT 0
+#define BIT_MASK_PTCL_DBG_OUT 0xffffffffL
+#define BIT_PTCL_DBG_OUT(x) \
+ (((x) & BIT_MASK_PTCL_DBG_OUT) << BIT_SHIFT_PTCL_DBG_OUT)
+#define BITS_PTCL_DBG_OUT (BIT_MASK_PTCL_DBG_OUT << BIT_SHIFT_PTCL_DBG_OUT)
+#define BIT_CLEAR_PTCL_DBG_OUT(x) ((x) & (~BITS_PTCL_DBG_OUT))
+#define BIT_GET_PTCL_DBG_OUT(x) \
+ (((x) >> BIT_SHIFT_PTCL_DBG_OUT) & BIT_MASK_PTCL_DBG_OUT)
+#define BIT_SET_PTCL_DBG_OUT(x, v) \
+ (BIT_CLEAR_PTCL_DBG_OUT(x) | BIT_PTCL_DBG_OUT(v))
-/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */
+#endif
+#if (HALMAC_8192E_SUPPORT)
-#define BIT_SHIFT_BE_TRIGGER_NUM 12
-#define BIT_MASK_BE_TRIGGER_NUM 0xf
-#define BIT_BE_TRIGGER_NUM(x) (((x) & BIT_MASK_BE_TRIGGER_NUM) << BIT_SHIFT_BE_TRIGGER_NUM)
-#define BIT_GET_BE_TRIGGER_NUM(x) (((x) >> BIT_SHIFT_BE_TRIGGER_NUM) & BIT_MASK_BE_TRIGGER_NUM)
+/* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */
+#define BIT_MOREDATA_CTRL2_EN BIT(19)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */
+#define BIT_MOREDATA_CTRL2_EN_V2 BIT(19)
-/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */
+#endif
+#if (HALMAC_8192E_SUPPORT)
-#define BIT_SHIFT_BE_TRIGGER_NUM_V1 8
-#define BIT_MASK_BE_TRIGGER_NUM_V1 0xf
-#define BIT_BE_TRIGGER_NUM_V1(x) (((x) & BIT_MASK_BE_TRIGGER_NUM_V1) << BIT_SHIFT_BE_TRIGGER_NUM_V1)
-#define BIT_GET_BE_TRIGGER_NUM_V1(x) (((x) >> BIT_SHIFT_BE_TRIGGER_NUM_V1) & BIT_MASK_BE_TRIGGER_NUM_V1)
+/* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */
+#define BIT_MOREDATA_CTRL1_EN BIT(18)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8822B_SUPPORT)
+/* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */
+#define BIT_MOREDATA_CTRL1_EN_V2 BIT(18)
-/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_BK_TRIGGER_NUM 8
-#define BIT_MASK_BK_TRIGGER_NUM 0xf
-#define BIT_BK_TRIGGER_NUM(x) (((x) & BIT_MASK_BK_TRIGGER_NUM) << BIT_SHIFT_BK_TRIGGER_NUM)
-#define BIT_GET_BK_TRIGGER_NUM(x) (((x) >> BIT_SHIFT_BK_TRIGGER_NUM) & BIT_MASK_BK_TRIGGER_NUM)
+/* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */
+#define BIT_EN_BCN_TRXRPT BIT(17)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8822B_SUPPORT)
-
+/* 2 REG_DUMMY_PAGE4 (Offset 0x04FC) */
-/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */
+#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE BIT(16)
+#endif
-#define BIT_SHIFT_VI_TRIGGER_NUM 4
-#define BIT_MASK_VI_TRIGGER_NUM 0xf
-#define BIT_VI_TRIGGER_NUM(x) (((x) & BIT_MASK_VI_TRIGGER_NUM) << BIT_SHIFT_VI_TRIGGER_NUM)
-#define BIT_GET_VI_TRIGGER_NUM(x) (((x) >> BIT_SHIFT_VI_TRIGGER_NUM) & BIT_MASK_VI_TRIGGER_NUM)
+#if (HALMAC_8822B_SUPPORT)
+/* 2 REG_DUMMY_PAGE4_V1 (Offset 0x04FC) */
-#define BIT_SHIFT_VO_TRIGGER_NUM 0
-#define BIT_MASK_VO_TRIGGER_NUM 0xf
-#define BIT_VO_TRIGGER_NUM(x) (((x) & BIT_MASK_VO_TRIGGER_NUM) << BIT_SHIFT_VO_TRIGGER_NUM)
-#define BIT_GET_VO_TRIGGER_NUM(x) (((x) >> BIT_SHIFT_VO_TRIGGER_NUM) & BIT_MASK_VO_TRIGGER_NUM)
+#define BIT_BCN_EN_EXTHWSEQ BIT(1)
+#define BIT_BCN_EN_HWSEQ BIT(0)
+#define BIT_SHIFT_R_MU_STA_GTAB_POSITION 0
+#define BIT_MASK_R_MU_STA_GTAB_POSITION 0xffffffffffffffffL
+#define BIT_R_MU_STA_GTAB_POSITION(x) \
+ (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION) \
+ << BIT_SHIFT_R_MU_STA_GTAB_POSITION)
+#define BITS_R_MU_STA_GTAB_POSITION \
+ (BIT_MASK_R_MU_STA_GTAB_POSITION << BIT_SHIFT_R_MU_STA_GTAB_POSITION)
+#define BIT_CLEAR_R_MU_STA_GTAB_POSITION(x) \
+ ((x) & (~BITS_R_MU_STA_GTAB_POSITION))
+#define BIT_GET_R_MU_STA_GTAB_POSITION(x) \
+ (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION) & \
+ BIT_MASK_R_MU_STA_GTAB_POSITION)
+#define BIT_SET_R_MU_STA_GTAB_POSITION(x, v) \
+ (BIT_CLEAR_R_MU_STA_GTAB_POSITION(x) | BIT_R_MU_STA_GTAB_POSITION(v))
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_MOREDATA (Offset 0x04FE) */
+#define BIT_MOREDATA_CTRL2_EN_V1 BIT(3)
+#define BIT_MOREDATA_CTRL1_EN_V1 BIT(2)
+#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE_V1 BIT(0)
-/* 2 REG_TBTT_PROHIBIT (Offset 0x0540) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_TBTT_HOLD_TIME_AP 8
-#define BIT_MASK_TBTT_HOLD_TIME_AP 0xfff
-#define BIT_TBTT_HOLD_TIME_AP(x) (((x) & BIT_MASK_TBTT_HOLD_TIME_AP) << BIT_SHIFT_TBTT_HOLD_TIME_AP)
-#define BIT_GET_TBTT_HOLD_TIME_AP(x) (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP) & BIT_MASK_TBTT_HOLD_TIME_AP)
+/* 2 REG_EDCA_VO_PARAM (Offset 0x0500) */
+#define BIT_SHIFT_TXOPLIMIT 16
+#define BIT_MASK_TXOPLIMIT 0x7ff
+#define BIT_TXOPLIMIT(x) (((x) & BIT_MASK_TXOPLIMIT) << BIT_SHIFT_TXOPLIMIT)
+#define BITS_TXOPLIMIT (BIT_MASK_TXOPLIMIT << BIT_SHIFT_TXOPLIMIT)
+#define BIT_CLEAR_TXOPLIMIT(x) ((x) & (~BITS_TXOPLIMIT))
+#define BIT_GET_TXOPLIMIT(x) (((x) >> BIT_SHIFT_TXOPLIMIT) & BIT_MASK_TXOPLIMIT)
+#define BIT_SET_TXOPLIMIT(x, v) (BIT_CLEAR_TXOPLIMIT(x) | BIT_TXOPLIMIT(v))
+
+#define BIT_SHIFT_CW 8
+#define BIT_MASK_CW 0xff
+#define BIT_CW(x) (((x) & BIT_MASK_CW) << BIT_SHIFT_CW)
+#define BITS_CW (BIT_MASK_CW << BIT_SHIFT_CW)
+#define BIT_CLEAR_CW(x) ((x) & (~BITS_CW))
+#define BIT_GET_CW(x) (((x) >> BIT_SHIFT_CW) & BIT_MASK_CW)
+#define BIT_SET_CW(x, v) (BIT_CLEAR_CW(x) | BIT_CW(v))
+
+#define BIT_SHIFT_AIFS 0
+#define BIT_MASK_AIFS 0xff
+#define BIT_AIFS(x) (((x) & BIT_MASK_AIFS) << BIT_SHIFT_AIFS)
+#define BITS_AIFS (BIT_MASK_AIFS << BIT_SHIFT_AIFS)
+#define BIT_CLEAR_AIFS(x) ((x) & (~BITS_AIFS))
+#define BIT_GET_AIFS(x) (((x) >> BIT_SHIFT_AIFS) & BIT_MASK_AIFS)
+#define BIT_SET_AIFS(x, v) (BIT_CLEAR_AIFS(x) | BIT_AIFS(v))
-#endif
+/* 2 REG_BCNTCFG (Offset 0x0510) */
+#define BIT_SHIFT_BCNCW_MAX 12
+#define BIT_MASK_BCNCW_MAX 0xf
+#define BIT_BCNCW_MAX(x) (((x) & BIT_MASK_BCNCW_MAX) << BIT_SHIFT_BCNCW_MAX)
+#define BITS_BCNCW_MAX (BIT_MASK_BCNCW_MAX << BIT_SHIFT_BCNCW_MAX)
+#define BIT_CLEAR_BCNCW_MAX(x) ((x) & (~BITS_BCNCW_MAX))
+#define BIT_GET_BCNCW_MAX(x) (((x) >> BIT_SHIFT_BCNCW_MAX) & BIT_MASK_BCNCW_MAX)
+#define BIT_SET_BCNCW_MAX(x, v) (BIT_CLEAR_BCNCW_MAX(x) | BIT_BCNCW_MAX(v))
+
+#define BIT_SHIFT_BCNCW_MIN 8
+#define BIT_MASK_BCNCW_MIN 0xf
+#define BIT_BCNCW_MIN(x) (((x) & BIT_MASK_BCNCW_MIN) << BIT_SHIFT_BCNCW_MIN)
+#define BITS_BCNCW_MIN (BIT_MASK_BCNCW_MIN << BIT_SHIFT_BCNCW_MIN)
+#define BIT_CLEAR_BCNCW_MIN(x) ((x) & (~BITS_BCNCW_MIN))
+#define BIT_GET_BCNCW_MIN(x) (((x) >> BIT_SHIFT_BCNCW_MIN) & BIT_MASK_BCNCW_MIN)
+#define BIT_SET_BCNCW_MIN(x, v) (BIT_CLEAR_BCNCW_MIN(x) | BIT_BCNCW_MIN(v))
+
+#define BIT_SHIFT_BCNIFS 0
+#define BIT_MASK_BCNIFS 0xff
+#define BIT_BCNIFS(x) (((x) & BIT_MASK_BCNIFS) << BIT_SHIFT_BCNIFS)
+#define BITS_BCNIFS (BIT_MASK_BCNIFS << BIT_SHIFT_BCNIFS)
+#define BIT_CLEAR_BCNIFS(x) ((x) & (~BITS_BCNIFS))
+#define BIT_GET_BCNIFS(x) (((x) >> BIT_SHIFT_BCNIFS) & BIT_MASK_BCNIFS)
+#define BIT_SET_BCNIFS(x, v) (BIT_CLEAR_BCNIFS(x) | BIT_BCNIFS(v))
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_PIFS (Offset 0x0512) */
+#define BIT_SHIFT_PIFS 0
+#define BIT_MASK_PIFS 0xff
+#define BIT_PIFS(x) (((x) & BIT_MASK_PIFS) << BIT_SHIFT_PIFS)
+#define BITS_PIFS (BIT_MASK_PIFS << BIT_SHIFT_PIFS)
+#define BIT_CLEAR_PIFS(x) ((x) & (~BITS_PIFS))
+#define BIT_GET_PIFS(x) (((x) >> BIT_SHIFT_PIFS) & BIT_MASK_PIFS)
+#define BIT_SET_PIFS(x, v) (BIT_CLEAR_PIFS(x) | BIT_PIFS(v))
-/* 2 REG_TBTT_PROHIBIT (Offset 0x0540) */
+/* 2 REG_RDG_PIFS (Offset 0x0513) */
+#define BIT_SHIFT_RDG_PIFS 0
+#define BIT_MASK_RDG_PIFS 0xff
+#define BIT_RDG_PIFS(x) (((x) & BIT_MASK_RDG_PIFS) << BIT_SHIFT_RDG_PIFS)
+#define BITS_RDG_PIFS (BIT_MASK_RDG_PIFS << BIT_SHIFT_RDG_PIFS)
+#define BIT_CLEAR_RDG_PIFS(x) ((x) & (~BITS_RDG_PIFS))
+#define BIT_GET_RDG_PIFS(x) (((x) >> BIT_SHIFT_RDG_PIFS) & BIT_MASK_RDG_PIFS)
+#define BIT_SET_RDG_PIFS(x, v) (BIT_CLEAR_RDG_PIFS(x) | BIT_RDG_PIFS(v))
-#define BIT_SHIFT_TBTT_HOLD_TIME_INFRA 4
-#define BIT_MASK_TBTT_HOLD_TIME_INFRA 0xf
-#define BIT_TBTT_HOLD_TIME_INFRA(x) (((x) & BIT_MASK_TBTT_HOLD_TIME_INFRA) << BIT_SHIFT_TBTT_HOLD_TIME_INFRA)
-#define BIT_GET_TBTT_HOLD_TIME_INFRA(x) (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_INFRA) & BIT_MASK_TBTT_HOLD_TIME_INFRA)
+/* 2 REG_SIFS (Offset 0x0514) */
+
+#define BIT_SHIFT_SIFS_OFDM_TRX 24
+#define BIT_MASK_SIFS_OFDM_TRX 0xff
+#define BIT_SIFS_OFDM_TRX(x) \
+ (((x) & BIT_MASK_SIFS_OFDM_TRX) << BIT_SHIFT_SIFS_OFDM_TRX)
+#define BITS_SIFS_OFDM_TRX (BIT_MASK_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX)
+#define BIT_CLEAR_SIFS_OFDM_TRX(x) ((x) & (~BITS_SIFS_OFDM_TRX))
+#define BIT_GET_SIFS_OFDM_TRX(x) \
+ (((x) >> BIT_SHIFT_SIFS_OFDM_TRX) & BIT_MASK_SIFS_OFDM_TRX)
+#define BIT_SET_SIFS_OFDM_TRX(x, v) \
+ (BIT_CLEAR_SIFS_OFDM_TRX(x) | BIT_SIFS_OFDM_TRX(v))
+
+#define BIT_SHIFT_SIFS_CCK_TRX 16
+#define BIT_MASK_SIFS_CCK_TRX 0xff
+#define BIT_SIFS_CCK_TRX(x) \
+ (((x) & BIT_MASK_SIFS_CCK_TRX) << BIT_SHIFT_SIFS_CCK_TRX)
+#define BITS_SIFS_CCK_TRX (BIT_MASK_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX)
+#define BIT_CLEAR_SIFS_CCK_TRX(x) ((x) & (~BITS_SIFS_CCK_TRX))
+#define BIT_GET_SIFS_CCK_TRX(x) \
+ (((x) >> BIT_SHIFT_SIFS_CCK_TRX) & BIT_MASK_SIFS_CCK_TRX)
+#define BIT_SET_SIFS_CCK_TRX(x, v) \
+ (BIT_CLEAR_SIFS_CCK_TRX(x) | BIT_SIFS_CCK_TRX(v))
+
+#define BIT_SHIFT_SIFS_OFDM_CTX 8
+#define BIT_MASK_SIFS_OFDM_CTX 0xff
+#define BIT_SIFS_OFDM_CTX(x) \
+ (((x) & BIT_MASK_SIFS_OFDM_CTX) << BIT_SHIFT_SIFS_OFDM_CTX)
+#define BITS_SIFS_OFDM_CTX (BIT_MASK_SIFS_OFDM_CTX << BIT_SHIFT_SIFS_OFDM_CTX)
+#define BIT_CLEAR_SIFS_OFDM_CTX(x) ((x) & (~BITS_SIFS_OFDM_CTX))
+#define BIT_GET_SIFS_OFDM_CTX(x) \
+ (((x) >> BIT_SHIFT_SIFS_OFDM_CTX) & BIT_MASK_SIFS_OFDM_CTX)
+#define BIT_SET_SIFS_OFDM_CTX(x, v) \
+ (BIT_CLEAR_SIFS_OFDM_CTX(x) | BIT_SIFS_OFDM_CTX(v))
+
+#define BIT_SHIFT_SIFS_CCK_CTX 0
+#define BIT_MASK_SIFS_CCK_CTX 0xff
+#define BIT_SIFS_CCK_CTX(x) \
+ (((x) & BIT_MASK_SIFS_CCK_CTX) << BIT_SHIFT_SIFS_CCK_CTX)
+#define BITS_SIFS_CCK_CTX (BIT_MASK_SIFS_CCK_CTX << BIT_SHIFT_SIFS_CCK_CTX)
+#define BIT_CLEAR_SIFS_CCK_CTX(x) ((x) & (~BITS_SIFS_CCK_CTX))
+#define BIT_GET_SIFS_CCK_CTX(x) \
+ (((x) >> BIT_SHIFT_SIFS_CCK_CTX) & BIT_MASK_SIFS_CCK_CTX)
+#define BIT_SET_SIFS_CCK_CTX(x, v) \
+ (BIT_CLEAR_SIFS_CCK_CTX(x) | BIT_SIFS_CCK_CTX(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TSFTR_SYN_OFFSET (Offset 0x0518) */
+#define BIT_SHIFT_TSFTR_SNC_OFFSET 0
+#define BIT_MASK_TSFTR_SNC_OFFSET 0xffff
+#define BIT_TSFTR_SNC_OFFSET(x) \
+ (((x) & BIT_MASK_TSFTR_SNC_OFFSET) << BIT_SHIFT_TSFTR_SNC_OFFSET)
+#define BITS_TSFTR_SNC_OFFSET \
+ (BIT_MASK_TSFTR_SNC_OFFSET << BIT_SHIFT_TSFTR_SNC_OFFSET)
+#define BIT_CLEAR_TSFTR_SNC_OFFSET(x) ((x) & (~BITS_TSFTR_SNC_OFFSET))
+#define BIT_GET_TSFTR_SNC_OFFSET(x) \
+ (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET) & BIT_MASK_TSFTR_SNC_OFFSET)
+#define BIT_SET_TSFTR_SNC_OFFSET(x, v) \
+ (BIT_CLEAR_TSFTR_SNC_OFFSET(x) | BIT_TSFTR_SNC_OFFSET(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_AGGR_BREAK_TIME (Offset 0x051A) */
+#define BIT_SHIFT_AGGR_BK_TIME 0
+#define BIT_MASK_AGGR_BK_TIME 0xff
+#define BIT_AGGR_BK_TIME(x) \
+ (((x) & BIT_MASK_AGGR_BK_TIME) << BIT_SHIFT_AGGR_BK_TIME)
+#define BITS_AGGR_BK_TIME (BIT_MASK_AGGR_BK_TIME << BIT_SHIFT_AGGR_BK_TIME)
+#define BIT_CLEAR_AGGR_BK_TIME(x) ((x) & (~BITS_AGGR_BK_TIME))
+#define BIT_GET_AGGR_BK_TIME(x) \
+ (((x) >> BIT_SHIFT_AGGR_BK_TIME) & BIT_MASK_AGGR_BK_TIME)
+#define BIT_SET_AGGR_BK_TIME(x, v) \
+ (BIT_CLEAR_AGGR_BK_TIME(x) | BIT_AGGR_BK_TIME(v))
-/* 2 REG_TBTT_PROHIBIT (Offset 0x0540) */
+/* 2 REG_SLOT (Offset 0x051B) */
+#define BIT_SHIFT_SLOT 0
+#define BIT_MASK_SLOT 0xff
+#define BIT_SLOT(x) (((x) & BIT_MASK_SLOT) << BIT_SHIFT_SLOT)
+#define BITS_SLOT (BIT_MASK_SLOT << BIT_SHIFT_SLOT)
+#define BIT_CLEAR_SLOT(x) ((x) & (~BITS_SLOT))
+#define BIT_GET_SLOT(x) (((x) >> BIT_SHIFT_SLOT) & BIT_MASK_SLOT)
+#define BIT_SET_SLOT(x, v) (BIT_CLEAR_SLOT(x) | BIT_SLOT(v))
-#define BIT_SHIFT_TBTT_PROHIBIT_SETUP 0
-#define BIT_MASK_TBTT_PROHIBIT_SETUP 0xf
-#define BIT_TBTT_PROHIBIT_SETUP(x) (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP) << BIT_SHIFT_TBTT_PROHIBIT_SETUP)
-#define BIT_GET_TBTT_PROHIBIT_SETUP(x) (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP) & BIT_MASK_TBTT_PROHIBIT_SETUP)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_P2PPS_STATE (Offset 0x0543) */
+/* 2 REG_EDCA_CPUMGQ_PARAM (Offset 0x051C) */
-#define BIT_POWER_STATE BIT(7)
-#define BIT_CTWINDOW_ON BIT(6)
-#define BIT_BEACON_AREA_ON BIT(5)
-#define BIT_CTWIN_EARLY_DISTX BIT(4)
-#define BIT_NOA1_OFF_PERIOD BIT(3)
-#define BIT_FORCE_DOZE1 BIT(2)
-#define BIT_NOA0_OFF_PERIOD BIT(1)
-#define BIT_FORCE_DOZE0 BIT(0)
+#define BIT_SHIFT_CW_V1 8
+#define BIT_MASK_CW_V1 0xff
+#define BIT_CW_V1(x) (((x) & BIT_MASK_CW_V1) << BIT_SHIFT_CW_V1)
+#define BITS_CW_V1 (BIT_MASK_CW_V1 << BIT_SHIFT_CW_V1)
+#define BIT_CLEAR_CW_V1(x) ((x) & (~BITS_CW_V1))
+#define BIT_GET_CW_V1(x) (((x) >> BIT_SHIFT_CW_V1) & BIT_MASK_CW_V1)
+#define BIT_SET_CW_V1(x, v) (BIT_CLEAR_CW_V1(x) | BIT_CW_V1(v))
-/* 2 REG_RD_NAV_NXT (Offset 0x0544) */
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_RD_NAV_PROT_NXT 0
-#define BIT_MASK_RD_NAV_PROT_NXT 0xffff
-#define BIT_RD_NAV_PROT_NXT(x) (((x) & BIT_MASK_RD_NAV_PROT_NXT) << BIT_SHIFT_RD_NAV_PROT_NXT)
-#define BIT_GET_RD_NAV_PROT_NXT(x) (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT) & BIT_MASK_RD_NAV_PROT_NXT)
+/* 2 REG_NOA_ON_ERLY_TIME (Offset 0x051C) */
+#define BIT_SHIFT__NOA_ON_ERLY_TIME 0
+#define BIT_MASK__NOA_ON_ERLY_TIME 0xff
+#define BIT__NOA_ON_ERLY_TIME(x) \
+ (((x) & BIT_MASK__NOA_ON_ERLY_TIME) << BIT_SHIFT__NOA_ON_ERLY_TIME)
+#define BITS__NOA_ON_ERLY_TIME \
+ (BIT_MASK__NOA_ON_ERLY_TIME << BIT_SHIFT__NOA_ON_ERLY_TIME)
+#define BIT_CLEAR__NOA_ON_ERLY_TIME(x) ((x) & (~BITS__NOA_ON_ERLY_TIME))
+#define BIT_GET__NOA_ON_ERLY_TIME(x) \
+ (((x) >> BIT_SHIFT__NOA_ON_ERLY_TIME) & BIT_MASK__NOA_ON_ERLY_TIME)
+#define BIT_SET__NOA_ON_ERLY_TIME(x, v) \
+ (BIT_CLEAR__NOA_ON_ERLY_TIME(x) | BIT__NOA_ON_ERLY_TIME(v))
-/* 2 REG_NAV_PROT_LEN (Offset 0x0546) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_NAV_PROT_LEN 0
-#define BIT_MASK_NAV_PROT_LEN 0xffff
-#define BIT_NAV_PROT_LEN(x) (((x) & BIT_MASK_NAV_PROT_LEN) << BIT_SHIFT_NAV_PROT_LEN)
-#define BIT_GET_NAV_PROT_LEN(x) (((x) >> BIT_SHIFT_NAV_PROT_LEN) & BIT_MASK_NAV_PROT_LEN)
+/* 2 REG_EDCA_CPUMGQ_PARAM (Offset 0x051C) */
+#define BIT_SHIFT_AIFS_V1 0
+#define BIT_MASK_AIFS_V1 0xff
+#define BIT_AIFS_V1(x) (((x) & BIT_MASK_AIFS_V1) << BIT_SHIFT_AIFS_V1)
+#define BITS_AIFS_V1 (BIT_MASK_AIFS_V1 << BIT_SHIFT_AIFS_V1)
+#define BIT_CLEAR_AIFS_V1(x) ((x) & (~BITS_AIFS_V1))
+#define BIT_GET_AIFS_V1(x) (((x) >> BIT_SHIFT_AIFS_V1) & BIT_MASK_AIFS_V1)
+#define BIT_SET_AIFS_V1(x, v) (BIT_CLEAR_AIFS_V1(x) | BIT_AIFS_V1(v))
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_NOA_OFF_ERLY_TIME (Offset 0x051D) */
+#define BIT_SHIFT__NOA_OFF_ERLY_TIME 0
+#define BIT_MASK__NOA_OFF_ERLY_TIME 0xff
+#define BIT__NOA_OFF_ERLY_TIME(x) \
+ (((x) & BIT_MASK__NOA_OFF_ERLY_TIME) << BIT_SHIFT__NOA_OFF_ERLY_TIME)
+#define BITS__NOA_OFF_ERLY_TIME \
+ (BIT_MASK__NOA_OFF_ERLY_TIME << BIT_SHIFT__NOA_OFF_ERLY_TIME)
+#define BIT_CLEAR__NOA_OFF_ERLY_TIME(x) ((x) & (~BITS__NOA_OFF_ERLY_TIME))
+#define BIT_GET__NOA_OFF_ERLY_TIME(x) \
+ (((x) >> BIT_SHIFT__NOA_OFF_ERLY_TIME) & BIT_MASK__NOA_OFF_ERLY_TIME)
+#define BIT_SET__NOA_OFF_ERLY_TIME(x, v) \
+ (BIT_CLEAR__NOA_OFF_ERLY_TIME(x) | BIT__NOA_OFF_ERLY_TIME(v))
-/* 2 REG_FTM_CTRL (Offset 0x0548) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_FTM_TSF_R2T_PORT 22
-#define BIT_MASK_FTM_TSF_R2T_PORT 0x7
-#define BIT_FTM_TSF_R2T_PORT(x) (((x) & BIT_MASK_FTM_TSF_R2T_PORT) << BIT_SHIFT_FTM_TSF_R2T_PORT)
-#define BIT_GET_FTM_TSF_R2T_PORT(x) (((x) >> BIT_SHIFT_FTM_TSF_R2T_PORT) & BIT_MASK_FTM_TSF_R2T_PORT)
+/* 2 REG_CPUMGQ_PAUSE (Offset 0x051E) */
+#define BIT_MAC_STOP_CPUMGQ_V1 BIT(0)
-#define BIT_SHIFT_FTM_TSF_T2R_PORT 19
-#define BIT_MASK_FTM_TSF_T2R_PORT 0x7
-#define BIT_FTM_TSF_T2R_PORT(x) (((x) & BIT_MASK_FTM_TSF_T2R_PORT) << BIT_SHIFT_FTM_TSF_T2R_PORT)
-#define BIT_GET_FTM_TSF_T2R_PORT(x) (((x) >> BIT_SHIFT_FTM_TSF_T2R_PORT) & BIT_MASK_FTM_TSF_T2R_PORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_FTM_PTT_PORT 16
-#define BIT_MASK_FTM_PTT_PORT 0x7
-#define BIT_FTM_PTT_PORT(x) (((x) & BIT_MASK_FTM_PTT_PORT) << BIT_SHIFT_FTM_PTT_PORT)
-#define BIT_GET_FTM_PTT_PORT(x) (((x) >> BIT_SHIFT_FTM_PTT_PORT) & BIT_MASK_FTM_PTT_PORT)
+/* 2 REG_TX_PTCL_CTRL (Offset 0x0520) */
+#define BIT_DIS_EDCCA BIT(15)
+#define BIT_DIS_CCA BIT(14)
+#define BIT_LSIG_TXOP_TXCMD_NAV BIT(13)
+#define BIT_SIFS_BK_EN BIT(12)
+
+#define BIT_SHIFT_TXQ_NAV_MSK 8
+#define BIT_MASK_TXQ_NAV_MSK 0xf
+#define BIT_TXQ_NAV_MSK(x) \
+ (((x) & BIT_MASK_TXQ_NAV_MSK) << BIT_SHIFT_TXQ_NAV_MSK)
+#define BITS_TXQ_NAV_MSK (BIT_MASK_TXQ_NAV_MSK << BIT_SHIFT_TXQ_NAV_MSK)
+#define BIT_CLEAR_TXQ_NAV_MSK(x) ((x) & (~BITS_TXQ_NAV_MSK))
+#define BIT_GET_TXQ_NAV_MSK(x) \
+ (((x) >> BIT_SHIFT_TXQ_NAV_MSK) & BIT_MASK_TXQ_NAV_MSK)
+#define BIT_SET_TXQ_NAV_MSK(x, v) \
+ (BIT_CLEAR_TXQ_NAV_MSK(x) | BIT_TXQ_NAV_MSK(v))
+
+#define BIT_DIS_CW BIT(7)
+#define BIT_NAV_END_TXOP BIT(6)
+#define BIT_RDG_END_TXOP BIT(5)
+#define BIT_AC_INBCN_HOLD BIT(4)
+#define BIT_MGTQ_TXOP_EN BIT(3)
+#define BIT_MGTQ_RTSMF_EN BIT(2)
+#define BIT_HIQ_RTSMF_EN BIT(1)
+#define BIT_BCN_RTSMF_EN BIT(0)
-#define BIT_SHIFT_FTM_PTT 0
-#define BIT_MASK_FTM_PTT 0xffff
-#define BIT_FTM_PTT(x) (((x) & BIT_MASK_FTM_PTT) << BIT_SHIFT_FTM_PTT)
-#define BIT_GET_FTM_PTT(x) (((x) >> BIT_SHIFT_FTM_PTT) & BIT_MASK_FTM_PTT)
+/* 2 REG_TXPAUSE (Offset 0x0522) */
+#define BIT_STOP_BCN_HI_MGT BIT(7)
+#define BIT_MAC_STOPBCNQ BIT(6)
+#define BIT_MAC_STOPHIQ BIT(5)
+#define BIT_MAC_STOPMGQ BIT(4)
+#define BIT_MAC_STOPBK BIT(3)
+#define BIT_MAC_STOPBE BIT(2)
+#define BIT_MAC_STOPVI BIT(1)
+#define BIT_MAC_STOPVO BIT(0)
-/* 2 REG_FTM_TSF_CNT (Offset 0x054C) */
+/* 2 REG_DIS_TXREQ_CLR (Offset 0x0523) */
+#define BIT_DIS_BT_CCA BIT(7)
-#define BIT_SHIFT_FTM_TSF_R2T 16
-#define BIT_MASK_FTM_TSF_R2T 0xffff
-#define BIT_FTM_TSF_R2T(x) (((x) & BIT_MASK_FTM_TSF_R2T) << BIT_SHIFT_FTM_TSF_R2T)
-#define BIT_GET_FTM_TSF_R2T(x) (((x) >> BIT_SHIFT_FTM_TSF_R2T) & BIT_MASK_FTM_TSF_R2T)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_FTM_TSF_T2R 0
-#define BIT_MASK_FTM_TSF_T2R 0xffff
-#define BIT_FTM_TSF_T2R(x) (((x) & BIT_MASK_FTM_TSF_T2R) << BIT_SHIFT_FTM_TSF_T2R)
-#define BIT_GET_FTM_TSF_T2R(x) (((x) >> BIT_SHIFT_FTM_TSF_T2R) & BIT_MASK_FTM_TSF_T2R)
+/* 2 REG_DIS_TXREQ_CLR (Offset 0x0523) */
+#define BIT_DIS_TXREQ_CLR_CPUMGQ BIT(6)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_DIS_TXREQ_CLR (Offset 0x0523) */
+#define BIT_DIS_TXREQ_CLR_HI BIT(5)
+#define BIT_DIS_TXREQ_CLR_MGQ BIT(4)
+#define BIT_DIS_TXREQ_CLR_VO BIT(3)
+#define BIT_DIS_TXREQ_CLR_VI BIT(2)
+#define BIT_DIS_TXREQ_CLR_BE BIT(1)
+#define BIT_DIS_TXREQ_CLR_BK BIT(0)
-/* 2 REG_BCN_CTRL (Offset 0x0550) */
+/* 2 REG_RD_CTRL (Offset 0x0524) */
-#define BIT_DIS_RX_BSSID_FIT BIT(6)
+#define BIT_EN_CLR_TXREQ_INCCA BIT(15)
+#define BIT_DIS_TX_OVER_BCNQ BIT(14)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_BCN_CTRL (Offset 0x0550) */
+/* 2 REG_RD_CTRL (Offset 0x0524) */
-#define BIT_P0_EN_TXBCN_RPT BIT(5)
+#define BIT_EN_BCNERR_INCCCA BIT(13)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_RD_CTRL (Offset 0x0524) */
+#define BIT_EN_BCNERR_INCCA BIT(13)
+#define BIT_EN_BCNERR_INEDCCA BIT(12)
-/* 2 REG_BCN_CTRL (Offset 0x0550) */
+#endif
-#define BIT_DIS_TSF_UDT BIT(4)
-#define BIT_EN_BCN_FUNCTION BIT(3)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_RD_CTRL (Offset 0x0524) */
+#define BIT_EDCCA_MSK_CNTDOWN_EN BIT(11)
+#define BIT_DIS_TXOP_CFE BIT(10)
+#define BIT_DIS_LSIG_CFE BIT(9)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_BCN_CTRL (Offset 0x0550) */
+/* 2 REG_RD_CTRL (Offset 0x0524) */
-#define BIT_EN_TXBCN_RPT BIT(2)
+#define BIT_DIS_STBC_CFE BIT(8)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_RD_CTRL (Offset 0x0524) */
+#define BIT_BKQ_RD_INIT_EN BIT(7)
+#define BIT_BEQ_RD_INIT_EN BIT(6)
+#define BIT_VIQ_RD_INIT_EN BIT(5)
+#define BIT_VOQ_RD_INIT_EN BIT(4)
+#define BIT_BKQ_RD_RESP_EN BIT(3)
+#define BIT_BEQ_RD_RESP_EN BIT(2)
+#define BIT_VIQ_RD_RESP_EN BIT(1)
+#define BIT_VOQ_RD_RESP_EN BIT(0)
-/* 2 REG_BCN_CTRL (Offset 0x0550) */
+/* 2 REG_MBSSID_CTRL (Offset 0x0526) */
-#define BIT_P0_EN_RXBCN_RPT BIT(2)
+#define BIT_MBID_BCNQ7_EN BIT(7)
+#define BIT_MBID_BCNQ6_EN BIT(6)
+#define BIT_MBID_BCNQ5_EN BIT(5)
+#define BIT_MBID_BCNQ4_EN BIT(4)
+#define BIT_MBID_BCNQ3_EN BIT(3)
+#define BIT_MBID_BCNQ2_EN BIT(2)
+#define BIT_MBID_BCNQ1_EN BIT(1)
+#define BIT_MBID_BCNQ0_EN BIT(0)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_P2PPS_CTRL (Offset 0x0527) */
+#define BIT_P2P_CTW_ALLSTASLEEP BIT(7)
+#define BIT_P2P_OFF_DISTX_EN BIT(6)
+#define BIT_PWR_MGT_EN BIT(5)
-/* 2 REG_BCN_CTRL (Offset 0x0550) */
+#endif
-#define BIT_DIS_BCNQ_SUB BIT(1)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_P2PPS_CTRL (Offset 0x0527) */
+#define BIT_P2P_BCN_AREA_EN BIT(4)
+#define BIT_P2P_CTWND_EN BIT(3)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_BCN_CTRL (Offset 0x0550) */
+/* 2 REG_P2PPS_CTRL (Offset 0x0527) */
-#define BIT_EN_P2P_CTWINDOW BIT(1)
-#define BIT_EN_P2P_BCNQ_AREA BIT(0)
+#define BIT_P2P_NOA1_EN BIT(2)
+#define BIT_P2P_NOA0_EN BIT(1)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_P2PPS_CTRL (Offset 0x0527) */
-/* 2 REG_BCN_CTRL1 (Offset 0x0551) */
-
-#define BIT_DIS_RX_BSSID_FIT1 BIT(6)
+#define BIT_P2P_BCN_SEL BIT(0)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_PKT_LIFETIME_CTRL (Offset 0x0528) */
+#define BIT_EN_P2P_CTWND1 BIT(23)
-/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */
+#endif
-#define BIT_CLI0_DIS_RX_BSSID_FIT BIT(6)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#endif
+/* 2 REG_PKT_LIFETIME_CTRL (Offset 0x0528) */
+#define BIT_EN_TBTT_AREA_FOR_BB BIT(23)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-/* 2 REG_BCN_CTRL1 (Offset 0x0551) */
+/* 2 REG_PKT_LIFETIME_CTRL (Offset 0x0528) */
-#define BIT_DIS_TSF1_UDT BIT(4)
+#define BIT_EN_BKF_CLR_TXREQ BIT(22)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_PKT_LIFETIME_CTRL (Offset 0x0528) */
+#define BIT_EN_TSFBIT32_RST_P2P BIT(21)
-/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */
+#endif
-#define BIT_CLI0_DIS_TSF_UDT BIT(4)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_PKT_LIFETIME_CTRL (Offset 0x0528) */
+#define BIT_EN_BCN_TX_BTCCA BIT(20)
+#define BIT_DIS_PKT_TX_ATIM BIT(19)
+#define BIT_DIS_BCN_DIS_CTN BIT(18)
+#define BIT_EN_NAVEND_RST_TXOP BIT(17)
+#define BIT_EN_FILTER_CCA BIT(16)
+
+#define BIT_SHIFT_CCA_FILTER_THRS 8
+#define BIT_MASK_CCA_FILTER_THRS 0xff
+#define BIT_CCA_FILTER_THRS(x) \
+ (((x) & BIT_MASK_CCA_FILTER_THRS) << BIT_SHIFT_CCA_FILTER_THRS)
+#define BITS_CCA_FILTER_THRS \
+ (BIT_MASK_CCA_FILTER_THRS << BIT_SHIFT_CCA_FILTER_THRS)
+#define BIT_CLEAR_CCA_FILTER_THRS(x) ((x) & (~BITS_CCA_FILTER_THRS))
+#define BIT_GET_CCA_FILTER_THRS(x) \
+ (((x) >> BIT_SHIFT_CCA_FILTER_THRS) & BIT_MASK_CCA_FILTER_THRS)
+#define BIT_SET_CCA_FILTER_THRS(x, v) \
+ (BIT_CLEAR_CCA_FILTER_THRS(x) | BIT_CCA_FILTER_THRS(v))
+
+#define BIT_SHIFT_EDCCA_THRS 0
+#define BIT_MASK_EDCCA_THRS 0xff
+#define BIT_EDCCA_THRS(x) (((x) & BIT_MASK_EDCCA_THRS) << BIT_SHIFT_EDCCA_THRS)
+#define BITS_EDCCA_THRS (BIT_MASK_EDCCA_THRS << BIT_SHIFT_EDCCA_THRS)
+#define BIT_CLEAR_EDCCA_THRS(x) ((x) & (~BITS_EDCCA_THRS))
+#define BIT_GET_EDCCA_THRS(x) \
+ (((x) >> BIT_SHIFT_EDCCA_THRS) & BIT_MASK_EDCCA_THRS)
+#define BIT_SET_EDCCA_THRS(x, v) (BIT_CLEAR_EDCCA_THRS(x) | BIT_EDCCA_THRS(v))
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_P2PPS_SPEC_STATE (Offset 0x052B) */
+#define BIT_SPEC_POWER_STATE BIT(7)
+#define BIT_SPEC_CTWINDOW_ON BIT(6)
+#define BIT_SPEC_BEACON_AREA_ON BIT(5)
+#define BIT_SPEC_CTWIN_EARLY_DISTX BIT(4)
+#define BIT_SPEC_NOA1_OFF_PERIOD BIT(3)
+#define BIT_SPEC_FORCE_DOZE1 BIT(2)
+#define BIT_SPEC_NOA0_OFF_PERIOD BIT(1)
+#define BIT_SPEC_FORCE_DOZE0 BIT(0)
+
+#define BIT_SHIFT_TBTT_PROHIBIT_SETUP 0
+#define BIT_MASK_TBTT_PROHIBIT_SETUP 0xf
+#define BIT_TBTT_PROHIBIT_SETUP(x) \
+ (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP) << BIT_SHIFT_TBTT_PROHIBIT_SETUP)
+#define BITS_TBTT_PROHIBIT_SETUP \
+ (BIT_MASK_TBTT_PROHIBIT_SETUP << BIT_SHIFT_TBTT_PROHIBIT_SETUP)
+#define BIT_CLEAR_TBTT_PROHIBIT_SETUP(x) ((x) & (~BITS_TBTT_PROHIBIT_SETUP))
+#define BIT_GET_TBTT_PROHIBIT_SETUP(x) \
+ (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP) & BIT_MASK_TBTT_PROHIBIT_SETUP)
+#define BIT_SET_TBTT_PROHIBIT_SETUP(x, v) \
+ (BIT_CLEAR_TBTT_PROHIBIT_SETUP(x) | BIT_TBTT_PROHIBIT_SETUP(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TXOP_LIMIT_CTRL (Offset 0x052C) */
+
+#define BIT_SHIFT_TXOP_TBTT_CNT 24
+#define BIT_MASK_TXOP_TBTT_CNT 0xff
+#define BIT_TXOP_TBTT_CNT(x) \
+ (((x) & BIT_MASK_TXOP_TBTT_CNT) << BIT_SHIFT_TXOP_TBTT_CNT)
+#define BITS_TXOP_TBTT_CNT (BIT_MASK_TXOP_TBTT_CNT << BIT_SHIFT_TXOP_TBTT_CNT)
+#define BIT_CLEAR_TXOP_TBTT_CNT(x) ((x) & (~BITS_TXOP_TBTT_CNT))
+#define BIT_GET_TXOP_TBTT_CNT(x) \
+ (((x) >> BIT_SHIFT_TXOP_TBTT_CNT) & BIT_MASK_TXOP_TBTT_CNT)
+#define BIT_SET_TXOP_TBTT_CNT(x, v) \
+ (BIT_CLEAR_TXOP_TBTT_CNT(x) | BIT_TXOP_TBTT_CNT(v))
+
+#define BIT_SHIFT_TXOP_TBTT_CNT_SEL 20
+#define BIT_MASK_TXOP_TBTT_CNT_SEL 0xf
+#define BIT_TXOP_TBTT_CNT_SEL(x) \
+ (((x) & BIT_MASK_TXOP_TBTT_CNT_SEL) << BIT_SHIFT_TXOP_TBTT_CNT_SEL)
+#define BITS_TXOP_TBTT_CNT_SEL \
+ (BIT_MASK_TXOP_TBTT_CNT_SEL << BIT_SHIFT_TXOP_TBTT_CNT_SEL)
+#define BIT_CLEAR_TXOP_TBTT_CNT_SEL(x) ((x) & (~BITS_TXOP_TBTT_CNT_SEL))
+#define BIT_GET_TXOP_TBTT_CNT_SEL(x) \
+ (((x) >> BIT_SHIFT_TXOP_TBTT_CNT_SEL) & BIT_MASK_TXOP_TBTT_CNT_SEL)
+#define BIT_SET_TXOP_TBTT_CNT_SEL(x, v) \
+ (BIT_CLEAR_TXOP_TBTT_CNT_SEL(x) | BIT_TXOP_TBTT_CNT_SEL(v))
+
+#define BIT_SHIFT_TXOP_LMT_EN 16
+#define BIT_MASK_TXOP_LMT_EN 0xf
+#define BIT_TXOP_LMT_EN(x) \
+ (((x) & BIT_MASK_TXOP_LMT_EN) << BIT_SHIFT_TXOP_LMT_EN)
+#define BITS_TXOP_LMT_EN (BIT_MASK_TXOP_LMT_EN << BIT_SHIFT_TXOP_LMT_EN)
+#define BIT_CLEAR_TXOP_LMT_EN(x) ((x) & (~BITS_TXOP_LMT_EN))
+#define BIT_GET_TXOP_LMT_EN(x) \
+ (((x) >> BIT_SHIFT_TXOP_LMT_EN) & BIT_MASK_TXOP_LMT_EN)
+#define BIT_SET_TXOP_LMT_EN(x, v) \
+ (BIT_CLEAR_TXOP_LMT_EN(x) | BIT_TXOP_LMT_EN(v))
+
+#define BIT_SHIFT_TXOP_LMT_TX_TIME 8
+#define BIT_MASK_TXOP_LMT_TX_TIME 0xff
+#define BIT_TXOP_LMT_TX_TIME(x) \
+ (((x) & BIT_MASK_TXOP_LMT_TX_TIME) << BIT_SHIFT_TXOP_LMT_TX_TIME)
+#define BITS_TXOP_LMT_TX_TIME \
+ (BIT_MASK_TXOP_LMT_TX_TIME << BIT_SHIFT_TXOP_LMT_TX_TIME)
+#define BIT_CLEAR_TXOP_LMT_TX_TIME(x) ((x) & (~BITS_TXOP_LMT_TX_TIME))
+#define BIT_GET_TXOP_LMT_TX_TIME(x) \
+ (((x) >> BIT_SHIFT_TXOP_LMT_TX_TIME) & BIT_MASK_TXOP_LMT_TX_TIME)
+#define BIT_SET_TXOP_LMT_TX_TIME(x, v) \
+ (BIT_CLEAR_TXOP_LMT_TX_TIME(x) | BIT_TXOP_LMT_TX_TIME(v))
+
+#define BIT_TXOP_CNT_TRIGGER_RESET BIT(7)
+
+#define BIT_SHIFT_TXOP_LMT_PKT_NUM 0
+#define BIT_MASK_TXOP_LMT_PKT_NUM 0x3f
+#define BIT_TXOP_LMT_PKT_NUM(x) \
+ (((x) & BIT_MASK_TXOP_LMT_PKT_NUM) << BIT_SHIFT_TXOP_LMT_PKT_NUM)
+#define BITS_TXOP_LMT_PKT_NUM \
+ (BIT_MASK_TXOP_LMT_PKT_NUM << BIT_SHIFT_TXOP_LMT_PKT_NUM)
+#define BIT_CLEAR_TXOP_LMT_PKT_NUM(x) ((x) & (~BITS_TXOP_LMT_PKT_NUM))
+#define BIT_GET_TXOP_LMT_PKT_NUM(x) \
+ (((x) >> BIT_SHIFT_TXOP_LMT_PKT_NUM) & BIT_MASK_TXOP_LMT_PKT_NUM)
+#define BIT_SET_TXOP_LMT_PKT_NUM(x, v) \
+ (BIT_CLEAR_TXOP_LMT_PKT_NUM(x) | BIT_TXOP_LMT_PKT_NUM(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_P2PON_DIS_TXTIME (Offset 0x0531) */
+
+#define BIT_SHIFT_P2PON_DIS_TXTIME 0
+#define BIT_MASK_P2PON_DIS_TXTIME 0xff
+#define BIT_P2PON_DIS_TXTIME(x) \
+ (((x) & BIT_MASK_P2PON_DIS_TXTIME) << BIT_SHIFT_P2PON_DIS_TXTIME)
+#define BITS_P2PON_DIS_TXTIME \
+ (BIT_MASK_P2PON_DIS_TXTIME << BIT_SHIFT_P2PON_DIS_TXTIME)
+#define BIT_CLEAR_P2PON_DIS_TXTIME(x) ((x) & (~BITS_P2PON_DIS_TXTIME))
+#define BIT_GET_P2PON_DIS_TXTIME(x) \
+ (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME) & BIT_MASK_P2PON_DIS_TXTIME)
+#define BIT_SET_P2PON_DIS_TXTIME(x, v) \
+ (BIT_CLEAR_P2PON_DIS_TXTIME(x) | BIT_P2PON_DIS_TXTIME(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CCA_TXEN_CNT (Offset 0x0534) */
+
+#define BIT_CCA_TXEN_CNT_SWITCH BIT(17)
+#define BIT_CCA_TXEN_CNT_EN BIT(16)
+
+#define BIT_SHIFT_CCA_TXEN_BIG_CNT 8
+#define BIT_MASK_CCA_TXEN_BIG_CNT 0xff
+#define BIT_CCA_TXEN_BIG_CNT(x) \
+ (((x) & BIT_MASK_CCA_TXEN_BIG_CNT) << BIT_SHIFT_CCA_TXEN_BIG_CNT)
+#define BITS_CCA_TXEN_BIG_CNT \
+ (BIT_MASK_CCA_TXEN_BIG_CNT << BIT_SHIFT_CCA_TXEN_BIG_CNT)
+#define BIT_CLEAR_CCA_TXEN_BIG_CNT(x) ((x) & (~BITS_CCA_TXEN_BIG_CNT))
+#define BIT_GET_CCA_TXEN_BIG_CNT(x) \
+ (((x) >> BIT_SHIFT_CCA_TXEN_BIG_CNT) & BIT_MASK_CCA_TXEN_BIG_CNT)
+#define BIT_SET_CCA_TXEN_BIG_CNT(x, v) \
+ (BIT_CLEAR_CCA_TXEN_BIG_CNT(x) | BIT_CCA_TXEN_BIG_CNT(v))
+
+#define BIT_SHIFT_CCA_TXEN_SMALL_CNT 0
+#define BIT_MASK_CCA_TXEN_SMALL_CNT 0xff
+#define BIT_CCA_TXEN_SMALL_CNT(x) \
+ (((x) & BIT_MASK_CCA_TXEN_SMALL_CNT) << BIT_SHIFT_CCA_TXEN_SMALL_CNT)
+#define BITS_CCA_TXEN_SMALL_CNT \
+ (BIT_MASK_CCA_TXEN_SMALL_CNT << BIT_SHIFT_CCA_TXEN_SMALL_CNT)
+#define BIT_CLEAR_CCA_TXEN_SMALL_CNT(x) ((x) & (~BITS_CCA_TXEN_SMALL_CNT))
+#define BIT_GET_CCA_TXEN_SMALL_CNT(x) \
+ (((x) >> BIT_SHIFT_CCA_TXEN_SMALL_CNT) & BIT_MASK_CCA_TXEN_SMALL_CNT)
+#define BIT_SET_CCA_TXEN_SMALL_CNT(x, v) \
+ (BIT_CLEAR_CCA_TXEN_SMALL_CNT(x) | BIT_CCA_TXEN_SMALL_CNT(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
-/* 2 REG_BCN_CTRL1 (Offset 0x0551) */
+/* 2 REG_QUEUE_INCOL_THR (Offset 0x0538) */
-#define BIT_EN_BCN1_FUNCTION BIT(3)
+#define BIT_SHIFT_BK_QUEUE_THR 24
+#define BIT_MASK_BK_QUEUE_THR 0xff
+#define BIT_BK_QUEUE_THR(x) \
+ (((x) & BIT_MASK_BK_QUEUE_THR) << BIT_SHIFT_BK_QUEUE_THR)
+#define BITS_BK_QUEUE_THR (BIT_MASK_BK_QUEUE_THR << BIT_SHIFT_BK_QUEUE_THR)
+#define BIT_CLEAR_BK_QUEUE_THR(x) ((x) & (~BITS_BK_QUEUE_THR))
+#define BIT_GET_BK_QUEUE_THR(x) \
+ (((x) >> BIT_SHIFT_BK_QUEUE_THR) & BIT_MASK_BK_QUEUE_THR)
+#define BIT_SET_BK_QUEUE_THR(x, v) \
+ (BIT_CLEAR_BK_QUEUE_THR(x) | BIT_BK_QUEUE_THR(v))
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_MAX_INTER_COLLISION (Offset 0x0538) */
+#define BIT_SHIFT_MAX_INTER_COLLISION_BK 24
+#define BIT_MASK_MAX_INTER_COLLISION_BK 0xff
+#define BIT_MAX_INTER_COLLISION_BK(x) \
+ (((x) & BIT_MASK_MAX_INTER_COLLISION_BK) \
+ << BIT_SHIFT_MAX_INTER_COLLISION_BK)
+#define BITS_MAX_INTER_COLLISION_BK \
+ (BIT_MASK_MAX_INTER_COLLISION_BK << BIT_SHIFT_MAX_INTER_COLLISION_BK)
+#define BIT_CLEAR_MAX_INTER_COLLISION_BK(x) \
+ ((x) & (~BITS_MAX_INTER_COLLISION_BK))
+#define BIT_GET_MAX_INTER_COLLISION_BK(x) \
+ (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_BK) & \
+ BIT_MASK_MAX_INTER_COLLISION_BK)
+#define BIT_SET_MAX_INTER_COLLISION_BK(x, v) \
+ (BIT_CLEAR_MAX_INTER_COLLISION_BK(x) | BIT_MAX_INTER_COLLISION_BK(v))
-/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */
+#endif
-#define BIT_CLI0_EN_BCN_FUNCTION BIT(3)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
-#endif
+/* 2 REG_QUEUE_INCOL_THR (Offset 0x0538) */
+#define BIT_SHIFT_BE_QUEUE_THR 16
+#define BIT_MASK_BE_QUEUE_THR 0xff
+#define BIT_BE_QUEUE_THR(x) \
+ (((x) & BIT_MASK_BE_QUEUE_THR) << BIT_SHIFT_BE_QUEUE_THR)
+#define BITS_BE_QUEUE_THR (BIT_MASK_BE_QUEUE_THR << BIT_SHIFT_BE_QUEUE_THR)
+#define BIT_CLEAR_BE_QUEUE_THR(x) ((x) & (~BITS_BE_QUEUE_THR))
+#define BIT_GET_BE_QUEUE_THR(x) \
+ (((x) >> BIT_SHIFT_BE_QUEUE_THR) & BIT_MASK_BE_QUEUE_THR)
+#define BIT_SET_BE_QUEUE_THR(x, v) \
+ (BIT_CLEAR_BE_QUEUE_THR(x) | BIT_BE_QUEUE_THR(v))
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_BCN_CTRL1 (Offset 0x0551) */
+/* 2 REG_MAX_INTER_COLLISION (Offset 0x0538) */
-#define BIT_EN_TXBCN1_RPT BIT(2)
+#define BIT_SHIFT_MAX_INTER_COLLISION_BE 16
+#define BIT_MASK_MAX_INTER_COLLISION_BE 0xff
+#define BIT_MAX_INTER_COLLISION_BE(x) \
+ (((x) & BIT_MASK_MAX_INTER_COLLISION_BE) \
+ << BIT_SHIFT_MAX_INTER_COLLISION_BE)
+#define BITS_MAX_INTER_COLLISION_BE \
+ (BIT_MASK_MAX_INTER_COLLISION_BE << BIT_SHIFT_MAX_INTER_COLLISION_BE)
+#define BIT_CLEAR_MAX_INTER_COLLISION_BE(x) \
+ ((x) & (~BITS_MAX_INTER_COLLISION_BE))
+#define BIT_GET_MAX_INTER_COLLISION_BE(x) \
+ (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_BE) & \
+ BIT_MASK_MAX_INTER_COLLISION_BE)
+#define BIT_SET_MAX_INTER_COLLISION_BE(x, v) \
+ (BIT_CLEAR_MAX_INTER_COLLISION_BE(x) | BIT_MAX_INTER_COLLISION_BE(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_QUEUE_INCOL_THR (Offset 0x0538) */
+#define BIT_SHIFT_VI_QUEUE_THR 8
+#define BIT_MASK_VI_QUEUE_THR 0xff
+#define BIT_VI_QUEUE_THR(x) \
+ (((x) & BIT_MASK_VI_QUEUE_THR) << BIT_SHIFT_VI_QUEUE_THR)
+#define BITS_VI_QUEUE_THR (BIT_MASK_VI_QUEUE_THR << BIT_SHIFT_VI_QUEUE_THR)
+#define BIT_CLEAR_VI_QUEUE_THR(x) ((x) & (~BITS_VI_QUEUE_THR))
+#define BIT_GET_VI_QUEUE_THR(x) \
+ (((x) >> BIT_SHIFT_VI_QUEUE_THR) & BIT_MASK_VI_QUEUE_THR)
+#define BIT_SET_VI_QUEUE_THR(x, v) \
+ (BIT_CLEAR_VI_QUEUE_THR(x) | BIT_VI_QUEUE_THR(v))
-/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */
+#endif
-#define BIT_CLI0_EN_RXBCN_RPT BIT(2)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_MAX_INTER_COLLISION (Offset 0x0538) */
+#define BIT_SHIFT_MAX_INTER_COLLISION_VI 8
+#define BIT_MASK_MAX_INTER_COLLISION_VI 0xff
+#define BIT_MAX_INTER_COLLISION_VI(x) \
+ (((x) & BIT_MASK_MAX_INTER_COLLISION_VI) \
+ << BIT_SHIFT_MAX_INTER_COLLISION_VI)
+#define BITS_MAX_INTER_COLLISION_VI \
+ (BIT_MASK_MAX_INTER_COLLISION_VI << BIT_SHIFT_MAX_INTER_COLLISION_VI)
+#define BIT_CLEAR_MAX_INTER_COLLISION_VI(x) \
+ ((x) & (~BITS_MAX_INTER_COLLISION_VI))
+#define BIT_GET_MAX_INTER_COLLISION_VI(x) \
+ (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_VI) & \
+ BIT_MASK_MAX_INTER_COLLISION_VI)
+#define BIT_SET_MAX_INTER_COLLISION_VI(x, v) \
+ (BIT_CLEAR_MAX_INTER_COLLISION_VI(x) | BIT_MAX_INTER_COLLISION_VI(v))
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
-/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */
+/* 2 REG_QUEUE_INCOL_THR (Offset 0x0538) */
-#define BIT_CLI0_EN_BCN_RPT BIT(2)
+#define BIT_SHIFT_VO_QUEUE_THR 0
+#define BIT_MASK_VO_QUEUE_THR 0xff
+#define BIT_VO_QUEUE_THR(x) \
+ (((x) & BIT_MASK_VO_QUEUE_THR) << BIT_SHIFT_VO_QUEUE_THR)
+#define BITS_VO_QUEUE_THR (BIT_MASK_VO_QUEUE_THR << BIT_SHIFT_VO_QUEUE_THR)
+#define BIT_CLEAR_VO_QUEUE_THR(x) ((x) & (~BITS_VO_QUEUE_THR))
+#define BIT_GET_VO_QUEUE_THR(x) \
+ (((x) >> BIT_SHIFT_VO_QUEUE_THR) & BIT_MASK_VO_QUEUE_THR)
+#define BIT_SET_VO_QUEUE_THR(x, v) \
+ (BIT_CLEAR_VO_QUEUE_THR(x) | BIT_VO_QUEUE_THR(v))
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_MAX_INTER_COLLISION (Offset 0x0538) */
+#define BIT_SHIFT_MAX_INTER_COLLISION_VO 0
+#define BIT_MASK_MAX_INTER_COLLISION_VO 0xff
+#define BIT_MAX_INTER_COLLISION_VO(x) \
+ (((x) & BIT_MASK_MAX_INTER_COLLISION_VO) \
+ << BIT_SHIFT_MAX_INTER_COLLISION_VO)
+#define BITS_MAX_INTER_COLLISION_VO \
+ (BIT_MASK_MAX_INTER_COLLISION_VO << BIT_SHIFT_MAX_INTER_COLLISION_VO)
+#define BIT_CLEAR_MAX_INTER_COLLISION_VO(x) \
+ ((x) & (~BITS_MAX_INTER_COLLISION_VO))
+#define BIT_GET_MAX_INTER_COLLISION_VO(x) \
+ (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_VO) & \
+ BIT_MASK_MAX_INTER_COLLISION_VO)
+#define BIT_SET_MAX_INTER_COLLISION_VO(x, v) \
+ (BIT_CLEAR_MAX_INTER_COLLISION_VO(x) | BIT_MAX_INTER_COLLISION_VO(v))
-/* 2 REG_BCN_CTRL1 (Offset 0x0551) */
+#endif
-#define BIT_DIS_BCNQ1_SUB BIT(1)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
-#endif
+/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */
+#define BIT_QUEUE_INCOL_EN BIT(16)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */
+/* 2 REG_MAX_INTER_COLLISION_CNT (Offset 0x053C) */
-#define BIT_CLI0_ENP2P_CTWINDOW BIT(1)
-#define BIT_CLI0_ENP2P_BCNQ_AREA BIT(0)
+#define BIT_MAX_INTER_COLLISION_EN BIT(16)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */
+#define BIT_SHIFT_BK_TRIGGER_NUM_V1 12
+#define BIT_MASK_BK_TRIGGER_NUM_V1 0xf
+#define BIT_BK_TRIGGER_NUM_V1(x) \
+ (((x) & BIT_MASK_BK_TRIGGER_NUM_V1) << BIT_SHIFT_BK_TRIGGER_NUM_V1)
+#define BITS_BK_TRIGGER_NUM_V1 \
+ (BIT_MASK_BK_TRIGGER_NUM_V1 << BIT_SHIFT_BK_TRIGGER_NUM_V1)
+#define BIT_CLEAR_BK_TRIGGER_NUM_V1(x) ((x) & (~BITS_BK_TRIGGER_NUM_V1))
+#define BIT_GET_BK_TRIGGER_NUM_V1(x) \
+ (((x) >> BIT_SHIFT_BK_TRIGGER_NUM_V1) & BIT_MASK_BK_TRIGGER_NUM_V1)
+#define BIT_SET_BK_TRIGGER_NUM_V1(x, v) \
+ (BIT_CLEAR_BK_TRIGGER_NUM_V1(x) | BIT_BK_TRIGGER_NUM_V1(v))
-/* 2 REG_MBID_NUM (Offset 0x0552) */
+#endif
-#define BIT_EN_PRE_DL_BEACON BIT(3)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_MBID_BCN_NUM 0
-#define BIT_MASK_MBID_BCN_NUM 0x7
-#define BIT_MBID_BCN_NUM(x) (((x) & BIT_MASK_MBID_BCN_NUM) << BIT_SHIFT_MBID_BCN_NUM)
-#define BIT_GET_MBID_BCN_NUM(x) (((x) >> BIT_SHIFT_MBID_BCN_NUM) & BIT_MASK_MBID_BCN_NUM)
+/* 2 REG_MAX_INTER_COLLISION_CNT (Offset 0x053C) */
+#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK 12
+#define BIT_MASK_MAX_INTER_COLLISION_CNT_BK 0xf
+#define BIT_MAX_INTER_COLLISION_CNT_BK(x) \
+ (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_BK) \
+ << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK)
+#define BITS_MAX_INTER_COLLISION_CNT_BK \
+ (BIT_MASK_MAX_INTER_COLLISION_CNT_BK \
+ << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK)
+#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_BK(x) \
+ ((x) & (~BITS_MAX_INTER_COLLISION_CNT_BK))
+#define BIT_GET_MAX_INTER_COLLISION_CNT_BK(x) \
+ (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK) & \
+ BIT_MASK_MAX_INTER_COLLISION_CNT_BK)
+#define BIT_SET_MAX_INTER_COLLISION_CNT_BK(x, v) \
+ (BIT_CLEAR_MAX_INTER_COLLISION_CNT_BK(x) | \
+ BIT_MAX_INTER_COLLISION_CNT_BK(v))
#endif
+#if (HALMAC_8822B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */
+#define BIT_SHIFT_BE_TRIGGER_NUM 12
+#define BIT_MASK_BE_TRIGGER_NUM 0xf
+#define BIT_BE_TRIGGER_NUM(x) \
+ (((x) & BIT_MASK_BE_TRIGGER_NUM) << BIT_SHIFT_BE_TRIGGER_NUM)
+#define BITS_BE_TRIGGER_NUM \
+ (BIT_MASK_BE_TRIGGER_NUM << BIT_SHIFT_BE_TRIGGER_NUM)
+#define BIT_CLEAR_BE_TRIGGER_NUM(x) ((x) & (~BITS_BE_TRIGGER_NUM))
+#define BIT_GET_BE_TRIGGER_NUM(x) \
+ (((x) >> BIT_SHIFT_BE_TRIGGER_NUM) & BIT_MASK_BE_TRIGGER_NUM)
+#define BIT_SET_BE_TRIGGER_NUM(x, v) \
+ (BIT_CLEAR_BE_TRIGGER_NUM(x) | BIT_BE_TRIGGER_NUM(v))
-/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */
+#endif
-#define BIT_P2P_PWR_RST1 BIT(6)
-#define BIT_SCHEDULER_RST BIT(5)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#endif
+/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */
+#define BIT_SHIFT_BE_TRIGGER_NUM_V1 8
+#define BIT_MASK_BE_TRIGGER_NUM_V1 0xf
+#define BIT_BE_TRIGGER_NUM_V1(x) \
+ (((x) & BIT_MASK_BE_TRIGGER_NUM_V1) << BIT_SHIFT_BE_TRIGGER_NUM_V1)
+#define BITS_BE_TRIGGER_NUM_V1 \
+ (BIT_MASK_BE_TRIGGER_NUM_V1 << BIT_SHIFT_BE_TRIGGER_NUM_V1)
+#define BIT_CLEAR_BE_TRIGGER_NUM_V1(x) ((x) & (~BITS_BE_TRIGGER_NUM_V1))
+#define BIT_GET_BE_TRIGGER_NUM_V1(x) \
+ (((x) >> BIT_SHIFT_BE_TRIGGER_NUM_V1) & BIT_MASK_BE_TRIGGER_NUM_V1)
+#define BIT_SET_BE_TRIGGER_NUM_V1(x, v) \
+ (BIT_CLEAR_BE_TRIGGER_NUM_V1(x) | BIT_BE_TRIGGER_NUM_V1(v))
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */
+/* 2 REG_MAX_INTER_COLLISION_CNT (Offset 0x053C) */
-#define BIT_FREECNT_RST BIT(5)
+#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE 8
+#define BIT_MASK_MAX_INTER_COLLISION_CNT_BE 0xf
+#define BIT_MAX_INTER_COLLISION_CNT_BE(x) \
+ (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_BE) \
+ << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE)
+#define BITS_MAX_INTER_COLLISION_CNT_BE \
+ (BIT_MASK_MAX_INTER_COLLISION_CNT_BE \
+ << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE)
+#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_BE(x) \
+ ((x) & (~BITS_MAX_INTER_COLLISION_CNT_BE))
+#define BIT_GET_MAX_INTER_COLLISION_CNT_BE(x) \
+ (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE) & \
+ BIT_MASK_MAX_INTER_COLLISION_CNT_BE)
+#define BIT_SET_MAX_INTER_COLLISION_CNT_BE(x, v) \
+ (BIT_CLEAR_MAX_INTER_COLLISION_CNT_BE(x) | \
+ BIT_MAX_INTER_COLLISION_CNT_BE(v))
#endif
+#if (HALMAC_8822B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */
+#define BIT_SHIFT_BK_TRIGGER_NUM 8
+#define BIT_MASK_BK_TRIGGER_NUM 0xf
+#define BIT_BK_TRIGGER_NUM(x) \
+ (((x) & BIT_MASK_BK_TRIGGER_NUM) << BIT_SHIFT_BK_TRIGGER_NUM)
+#define BITS_BK_TRIGGER_NUM \
+ (BIT_MASK_BK_TRIGGER_NUM << BIT_SHIFT_BK_TRIGGER_NUM)
+#define BIT_CLEAR_BK_TRIGGER_NUM(x) ((x) & (~BITS_BK_TRIGGER_NUM))
+#define BIT_GET_BK_TRIGGER_NUM(x) \
+ (((x) >> BIT_SHIFT_BK_TRIGGER_NUM) & BIT_MASK_BK_TRIGGER_NUM)
+#define BIT_SET_BK_TRIGGER_NUM(x, v) \
+ (BIT_CLEAR_BK_TRIGGER_NUM(x) | BIT_BK_TRIGGER_NUM(v))
-/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */
+#endif
-#define BIT_P2P_PWR_RST0 BIT(4)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
-#endif
+/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */
+#define BIT_SHIFT_VI_TRIGGER_NUM 4
+#define BIT_MASK_VI_TRIGGER_NUM 0xf
+#define BIT_VI_TRIGGER_NUM(x) \
+ (((x) & BIT_MASK_VI_TRIGGER_NUM) << BIT_SHIFT_VI_TRIGGER_NUM)
+#define BITS_VI_TRIGGER_NUM \
+ (BIT_MASK_VI_TRIGGER_NUM << BIT_SHIFT_VI_TRIGGER_NUM)
+#define BIT_CLEAR_VI_TRIGGER_NUM(x) ((x) & (~BITS_VI_TRIGGER_NUM))
+#define BIT_GET_VI_TRIGGER_NUM(x) \
+ (((x) >> BIT_SHIFT_VI_TRIGGER_NUM) & BIT_MASK_VI_TRIGGER_NUM)
+#define BIT_SET_VI_TRIGGER_NUM(x, v) \
+ (BIT_CLEAR_VI_TRIGGER_NUM(x) | BIT_VI_TRIGGER_NUM(v))
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */
+/* 2 REG_MAX_INTER_COLLISION_CNT (Offset 0x053C) */
-#define BIT_TSFTR_CLI3_RST BIT(4)
+#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI 4
+#define BIT_MASK_MAX_INTER_COLLISION_CNT_VI 0xf
+#define BIT_MAX_INTER_COLLISION_CNT_VI(x) \
+ (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_VI) \
+ << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI)
+#define BITS_MAX_INTER_COLLISION_CNT_VI \
+ (BIT_MASK_MAX_INTER_COLLISION_CNT_VI \
+ << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI)
+#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_VI(x) \
+ ((x) & (~BITS_MAX_INTER_COLLISION_CNT_VI))
+#define BIT_GET_MAX_INTER_COLLISION_CNT_VI(x) \
+ (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI) & \
+ BIT_MASK_MAX_INTER_COLLISION_CNT_VI)
+#define BIT_SET_MAX_INTER_COLLISION_CNT_VI(x, v) \
+ (BIT_CLEAR_MAX_INTER_COLLISION_CNT_VI(x) | \
+ BIT_MAX_INTER_COLLISION_CNT_VI(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */
+#define BIT_SHIFT_VO_TRIGGER_NUM 0
+#define BIT_MASK_VO_TRIGGER_NUM 0xf
+#define BIT_VO_TRIGGER_NUM(x) \
+ (((x) & BIT_MASK_VO_TRIGGER_NUM) << BIT_SHIFT_VO_TRIGGER_NUM)
+#define BITS_VO_TRIGGER_NUM \
+ (BIT_MASK_VO_TRIGGER_NUM << BIT_SHIFT_VO_TRIGGER_NUM)
+#define BIT_CLEAR_VO_TRIGGER_NUM(x) ((x) & (~BITS_VO_TRIGGER_NUM))
+#define BIT_GET_VO_TRIGGER_NUM(x) \
+ (((x) >> BIT_SHIFT_VO_TRIGGER_NUM) & BIT_MASK_VO_TRIGGER_NUM)
+#define BIT_SET_VO_TRIGGER_NUM(x, v) \
+ (BIT_CLEAR_VO_TRIGGER_NUM(x) | BIT_VO_TRIGGER_NUM(v))
-/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */
+#endif
-#define BIT_TSFTR1_SYNC_EN BIT(3)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_MAX_INTER_COLLISION_CNT (Offset 0x053C) */
+#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO 0
+#define BIT_MASK_MAX_INTER_COLLISION_CNT_VO 0xf
+#define BIT_MAX_INTER_COLLISION_CNT_VO(x) \
+ (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_VO) \
+ << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO)
+#define BITS_MAX_INTER_COLLISION_CNT_VO \
+ (BIT_MASK_MAX_INTER_COLLISION_CNT_VO \
+ << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO)
+#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_VO(x) \
+ ((x) & (~BITS_MAX_INTER_COLLISION_CNT_VO))
+#define BIT_GET_MAX_INTER_COLLISION_CNT_VO(x) \
+ (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO) & \
+ BIT_MASK_MAX_INTER_COLLISION_CNT_VO)
+#define BIT_SET_MAX_INTER_COLLISION_CNT_VO(x, v) \
+ (BIT_CLEAR_MAX_INTER_COLLISION_CNT_VO(x) | \
+ BIT_MAX_INTER_COLLISION_CNT_VO(v))
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */
+/* 2 REG_TBTT_PROHIBIT (Offset 0x0540) */
-#define BIT_TSFTR_CLI2_RST BIT(3)
+#define BIT_SHIFT_TBTT_HOLD_TIME_AP 8
+#define BIT_MASK_TBTT_HOLD_TIME_AP 0xfff
+#define BIT_TBTT_HOLD_TIME_AP(x) \
+ (((x) & BIT_MASK_TBTT_HOLD_TIME_AP) << BIT_SHIFT_TBTT_HOLD_TIME_AP)
+#define BITS_TBTT_HOLD_TIME_AP \
+ (BIT_MASK_TBTT_HOLD_TIME_AP << BIT_SHIFT_TBTT_HOLD_TIME_AP)
+#define BIT_CLEAR_TBTT_HOLD_TIME_AP(x) ((x) & (~BITS_TBTT_HOLD_TIME_AP))
+#define BIT_GET_TBTT_HOLD_TIME_AP(x) \
+ (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP) & BIT_MASK_TBTT_HOLD_TIME_AP)
+#define BIT_SET_TBTT_HOLD_TIME_AP(x, v) \
+ (BIT_CLEAR_TBTT_HOLD_TIME_AP(x) | BIT_TBTT_HOLD_TIME_AP(v))
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_TBTT_PROHIBIT (Offset 0x0540) */
-/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */
-
-#define BIT_TSFTR_SYNC_EN BIT(2)
+#define BIT_SHIFT_TBTT_HOLD_TIME_INFRA 4
+#define BIT_MASK_TBTT_HOLD_TIME_INFRA 0xf
+#define BIT_TBTT_HOLD_TIME_INFRA(x) \
+ (((x) & BIT_MASK_TBTT_HOLD_TIME_INFRA) \
+ << BIT_SHIFT_TBTT_HOLD_TIME_INFRA)
+#define BITS_TBTT_HOLD_TIME_INFRA \
+ (BIT_MASK_TBTT_HOLD_TIME_INFRA << BIT_SHIFT_TBTT_HOLD_TIME_INFRA)
+#define BIT_CLEAR_TBTT_HOLD_TIME_INFRA(x) ((x) & (~BITS_TBTT_HOLD_TIME_INFRA))
+#define BIT_GET_TBTT_HOLD_TIME_INFRA(x) \
+ (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_INFRA) & \
+ BIT_MASK_TBTT_HOLD_TIME_INFRA)
+#define BIT_SET_TBTT_HOLD_TIME_INFRA(x, v) \
+ (BIT_CLEAR_TBTT_HOLD_TIME_INFRA(x) | BIT_TBTT_HOLD_TIME_INFRA(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_P2PPS_STATE (Offset 0x0543) */
+#define BIT_POWER_STATE BIT(7)
+#define BIT_CTWINDOW_ON BIT(6)
+#define BIT_BEACON_AREA_ON BIT(5)
+#define BIT_CTWIN_EARLY_DISTX BIT(4)
+#define BIT_NOA1_OFF_PERIOD BIT(3)
+#define BIT_FORCE_DOZE1 BIT(2)
+#define BIT_NOA0_OFF_PERIOD BIT(1)
+#define BIT_FORCE_DOZE0 BIT(0)
-/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */
+/* 2 REG_RD_NAV_NXT (Offset 0x0544) */
-#define BIT_TSFTR_CLI1_RST BIT(2)
+#define BIT_SHIFT_RD_NAV_PROT_NXT 0
+#define BIT_MASK_RD_NAV_PROT_NXT 0xffff
+#define BIT_RD_NAV_PROT_NXT(x) \
+ (((x) & BIT_MASK_RD_NAV_PROT_NXT) << BIT_SHIFT_RD_NAV_PROT_NXT)
+#define BITS_RD_NAV_PROT_NXT \
+ (BIT_MASK_RD_NAV_PROT_NXT << BIT_SHIFT_RD_NAV_PROT_NXT)
+#define BIT_CLEAR_RD_NAV_PROT_NXT(x) ((x) & (~BITS_RD_NAV_PROT_NXT))
+#define BIT_GET_RD_NAV_PROT_NXT(x) \
+ (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT) & BIT_MASK_RD_NAV_PROT_NXT)
+#define BIT_SET_RD_NAV_PROT_NXT(x, v) \
+ (BIT_CLEAR_RD_NAV_PROT_NXT(x) | BIT_RD_NAV_PROT_NXT(v))
-#endif
+/* 2 REG_NAV_PROT_LEN (Offset 0x0546) */
+#define BIT_DIS_RX_BSSID_FIT BIT(6)
+#define BIT_DIS_TSF_UDT BIT(4)
+
+#define BIT_SHIFT_NAV_PROT_LEN 0
+#define BIT_MASK_NAV_PROT_LEN 0xffff
+#define BIT_NAV_PROT_LEN(x) \
+ (((x) & BIT_MASK_NAV_PROT_LEN) << BIT_SHIFT_NAV_PROT_LEN)
+#define BITS_NAV_PROT_LEN (BIT_MASK_NAV_PROT_LEN << BIT_SHIFT_NAV_PROT_LEN)
+#define BIT_CLEAR_NAV_PROT_LEN(x) ((x) & (~BITS_NAV_PROT_LEN))
+#define BIT_GET_NAV_PROT_LEN(x) \
+ (((x) >> BIT_SHIFT_NAV_PROT_LEN) & BIT_MASK_NAV_PROT_LEN)
+#define BIT_SET_NAV_PROT_LEN(x, v) \
+ (BIT_CLEAR_NAV_PROT_LEN(x) | BIT_NAV_PROT_LEN(v))
+
+#define BIT_SHIFT_DRVERLYITV 0
+#define BIT_MASK_DRVERLYITV 0xff
+#define BIT_DRVERLYITV(x) (((x) & BIT_MASK_DRVERLYITV) << BIT_SHIFT_DRVERLYITV)
+#define BITS_DRVERLYITV (BIT_MASK_DRVERLYITV << BIT_SHIFT_DRVERLYITV)
+#define BIT_CLEAR_DRVERLYITV(x) ((x) & (~BITS_DRVERLYITV))
+#define BIT_GET_DRVERLYITV(x) \
+ (((x) >> BIT_SHIFT_DRVERLYITV) & BIT_MASK_DRVERLYITV)
+#define BIT_SET_DRVERLYITV(x, v) (BIT_CLEAR_DRVERLYITV(x) | BIT_DRVERLYITV(v))
+
+#define BIT_SHIFT_BCNDMATIM 0
+#define BIT_MASK_BCNDMATIM 0xff
+#define BIT_BCNDMATIM(x) (((x) & BIT_MASK_BCNDMATIM) << BIT_SHIFT_BCNDMATIM)
+#define BITS_BCNDMATIM (BIT_MASK_BCNDMATIM << BIT_SHIFT_BCNDMATIM)
+#define BIT_CLEAR_BCNDMATIM(x) ((x) & (~BITS_BCNDMATIM))
+#define BIT_GET_BCNDMATIM(x) (((x) >> BIT_SHIFT_BCNDMATIM) & BIT_MASK_BCNDMATIM)
+#define BIT_SET_BCNDMATIM(x, v) (BIT_CLEAR_BCNDMATIM(x) | BIT_BCNDMATIM(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_FTM_CTRL (Offset 0x0548) */
+#define BIT_SHIFT_FTM_TSF_R2T_PORT 22
+#define BIT_MASK_FTM_TSF_R2T_PORT 0x7
+#define BIT_FTM_TSF_R2T_PORT(x) \
+ (((x) & BIT_MASK_FTM_TSF_R2T_PORT) << BIT_SHIFT_FTM_TSF_R2T_PORT)
+#define BITS_FTM_TSF_R2T_PORT \
+ (BIT_MASK_FTM_TSF_R2T_PORT << BIT_SHIFT_FTM_TSF_R2T_PORT)
+#define BIT_CLEAR_FTM_TSF_R2T_PORT(x) ((x) & (~BITS_FTM_TSF_R2T_PORT))
+#define BIT_GET_FTM_TSF_R2T_PORT(x) \
+ (((x) >> BIT_SHIFT_FTM_TSF_R2T_PORT) & BIT_MASK_FTM_TSF_R2T_PORT)
+#define BIT_SET_FTM_TSF_R2T_PORT(x, v) \
+ (BIT_CLEAR_FTM_TSF_R2T_PORT(x) | BIT_FTM_TSF_R2T_PORT(v))
-/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */
+#endif
-#define BIT_TSFTR1_RST BIT(1)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_FTM_PTT (Offset 0x0548) */
+#define BIT_SHIFT_FTM_PTT_TSF_R2T_SEL 22
+#define BIT_MASK_FTM_PTT_TSF_R2T_SEL 0x7
+#define BIT_FTM_PTT_TSF_R2T_SEL(x) \
+ (((x) & BIT_MASK_FTM_PTT_TSF_R2T_SEL) << BIT_SHIFT_FTM_PTT_TSF_R2T_SEL)
+#define BITS_FTM_PTT_TSF_R2T_SEL \
+ (BIT_MASK_FTM_PTT_TSF_R2T_SEL << BIT_SHIFT_FTM_PTT_TSF_R2T_SEL)
+#define BIT_CLEAR_FTM_PTT_TSF_R2T_SEL(x) ((x) & (~BITS_FTM_PTT_TSF_R2T_SEL))
+#define BIT_GET_FTM_PTT_TSF_R2T_SEL(x) \
+ (((x) >> BIT_SHIFT_FTM_PTT_TSF_R2T_SEL) & BIT_MASK_FTM_PTT_TSF_R2T_SEL)
+#define BIT_SET_FTM_PTT_TSF_R2T_SEL(x, v) \
+ (BIT_CLEAR_FTM_PTT_TSF_R2T_SEL(x) | BIT_FTM_PTT_TSF_R2T_SEL(v))
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */
+/* 2 REG_FTM_CTRL (Offset 0x0548) */
-#define BIT_TSFTR_CLI0_RST BIT(1)
+#define BIT_SHIFT_FTM_TSF_T2R_PORT 19
+#define BIT_MASK_FTM_TSF_T2R_PORT 0x7
+#define BIT_FTM_TSF_T2R_PORT(x) \
+ (((x) & BIT_MASK_FTM_TSF_T2R_PORT) << BIT_SHIFT_FTM_TSF_T2R_PORT)
+#define BITS_FTM_TSF_T2R_PORT \
+ (BIT_MASK_FTM_TSF_T2R_PORT << BIT_SHIFT_FTM_TSF_T2R_PORT)
+#define BIT_CLEAR_FTM_TSF_T2R_PORT(x) ((x) & (~BITS_FTM_TSF_T2R_PORT))
+#define BIT_GET_FTM_TSF_T2R_PORT(x) \
+ (((x) >> BIT_SHIFT_FTM_TSF_T2R_PORT) & BIT_MASK_FTM_TSF_T2R_PORT)
+#define BIT_SET_FTM_TSF_T2R_PORT(x, v) \
+ (BIT_CLEAR_FTM_TSF_T2R_PORT(x) | BIT_FTM_TSF_T2R_PORT(v))
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_FTM_PTT (Offset 0x0548) */
+#define BIT_SHIFT_FTM_PTT_TSF_T2R_SEL 19
+#define BIT_MASK_FTM_PTT_TSF_T2R_SEL 0x7
+#define BIT_FTM_PTT_TSF_T2R_SEL(x) \
+ (((x) & BIT_MASK_FTM_PTT_TSF_T2R_SEL) << BIT_SHIFT_FTM_PTT_TSF_T2R_SEL)
+#define BITS_FTM_PTT_TSF_T2R_SEL \
+ (BIT_MASK_FTM_PTT_TSF_T2R_SEL << BIT_SHIFT_FTM_PTT_TSF_T2R_SEL)
+#define BIT_CLEAR_FTM_PTT_TSF_T2R_SEL(x) ((x) & (~BITS_FTM_PTT_TSF_T2R_SEL))
+#define BIT_GET_FTM_PTT_TSF_T2R_SEL(x) \
+ (((x) >> BIT_SHIFT_FTM_PTT_TSF_T2R_SEL) & BIT_MASK_FTM_PTT_TSF_T2R_SEL)
+#define BIT_SET_FTM_PTT_TSF_T2R_SEL(x, v) \
+ (BIT_CLEAR_FTM_PTT_TSF_T2R_SEL(x) | BIT_FTM_PTT_TSF_T2R_SEL(v))
-/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FTM_CTRL (Offset 0x0548) */
-#define BIT_TSFTR_RST BIT(0)
+#define BIT_SHIFT_FTM_PTT_PORT 16
+#define BIT_MASK_FTM_PTT_PORT 0x7
+#define BIT_FTM_PTT_PORT(x) \
+ (((x) & BIT_MASK_FTM_PTT_PORT) << BIT_SHIFT_FTM_PTT_PORT)
+#define BITS_FTM_PTT_PORT (BIT_MASK_FTM_PTT_PORT << BIT_SHIFT_FTM_PTT_PORT)
+#define BIT_CLEAR_FTM_PTT_PORT(x) ((x) & (~BITS_FTM_PTT_PORT))
+#define BIT_GET_FTM_PTT_PORT(x) \
+ (((x) >> BIT_SHIFT_FTM_PTT_PORT) & BIT_MASK_FTM_PTT_PORT)
+#define BIT_SET_FTM_PTT_PORT(x, v) \
+ (BIT_CLEAR_FTM_PTT_PORT(x) | BIT_FTM_PTT_PORT(v))
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FTM_PTT (Offset 0x0548) */
+#define BIT_SHIFT_FTM_PTT_TSF_SEL 16
+#define BIT_MASK_FTM_PTT_TSF_SEL 0x7
+#define BIT_FTM_PTT_TSF_SEL(x) \
+ (((x) & BIT_MASK_FTM_PTT_TSF_SEL) << BIT_SHIFT_FTM_PTT_TSF_SEL)
+#define BITS_FTM_PTT_TSF_SEL \
+ (BIT_MASK_FTM_PTT_TSF_SEL << BIT_SHIFT_FTM_PTT_TSF_SEL)
+#define BIT_CLEAR_FTM_PTT_TSF_SEL(x) ((x) & (~BITS_FTM_PTT_TSF_SEL))
+#define BIT_GET_FTM_PTT_TSF_SEL(x) \
+ (((x) >> BIT_SHIFT_FTM_PTT_TSF_SEL) & BIT_MASK_FTM_PTT_TSF_SEL)
+#define BIT_SET_FTM_PTT_TSF_SEL(x, v) \
+ (BIT_CLEAR_FTM_PTT_TSF_SEL(x) | BIT_FTM_PTT_TSF_SEL(v))
-/* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_BCN_TIMER_SEL_FWRD 28
-#define BIT_MASK_BCN_TIMER_SEL_FWRD 0x7
-#define BIT_BCN_TIMER_SEL_FWRD(x) (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD) << BIT_SHIFT_BCN_TIMER_SEL_FWRD)
-#define BIT_GET_BCN_TIMER_SEL_FWRD(x) (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD) & BIT_MASK_BCN_TIMER_SEL_FWRD)
+/* 2 REG_FTM_CTRL (Offset 0x0548) */
+#define BIT_SHIFT_FTM_PTT 0
+#define BIT_MASK_FTM_PTT 0xffff
+#define BIT_FTM_PTT(x) (((x) & BIT_MASK_FTM_PTT) << BIT_SHIFT_FTM_PTT)
+#define BITS_FTM_PTT (BIT_MASK_FTM_PTT << BIT_SHIFT_FTM_PTT)
+#define BIT_CLEAR_FTM_PTT(x) ((x) & (~BITS_FTM_PTT))
+#define BIT_GET_FTM_PTT(x) (((x) >> BIT_SHIFT_FTM_PTT) & BIT_MASK_FTM_PTT)
+#define BIT_SET_FTM_PTT(x, v) (BIT_CLEAR_FTM_PTT(x) | BIT_FTM_PTT(v))
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_FTM_PTT (Offset 0x0548) */
+#define BIT_SHIFT_FTM_PTT_VALUE 0
+#define BIT_MASK_FTM_PTT_VALUE 0xffff
+#define BIT_FTM_PTT_VALUE(x) \
+ (((x) & BIT_MASK_FTM_PTT_VALUE) << BIT_SHIFT_FTM_PTT_VALUE)
+#define BITS_FTM_PTT_VALUE (BIT_MASK_FTM_PTT_VALUE << BIT_SHIFT_FTM_PTT_VALUE)
+#define BIT_CLEAR_FTM_PTT_VALUE(x) ((x) & (~BITS_FTM_PTT_VALUE))
+#define BIT_GET_FTM_PTT_VALUE(x) \
+ (((x) >> BIT_SHIFT_FTM_PTT_VALUE) & BIT_MASK_FTM_PTT_VALUE)
+#define BIT_SET_FTM_PTT_VALUE(x, v) \
+ (BIT_CLEAR_FTM_PTT_VALUE(x) | BIT_FTM_PTT_VALUE(v))
-/* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_BCN_SPACE1 16
-#define BIT_MASK_BCN_SPACE1 0xffff
-#define BIT_BCN_SPACE1(x) (((x) & BIT_MASK_BCN_SPACE1) << BIT_SHIFT_BCN_SPACE1)
-#define BIT_GET_BCN_SPACE1(x) (((x) >> BIT_SHIFT_BCN_SPACE1) & BIT_MASK_BCN_SPACE1)
+/* 2 REG_FTM_TSF_CNT (Offset 0x054C) */
+#define BIT_SHIFT_FTM_TSF_R2T 16
+#define BIT_MASK_FTM_TSF_R2T 0xffff
+#define BIT_FTM_TSF_R2T(x) \
+ (((x) & BIT_MASK_FTM_TSF_R2T) << BIT_SHIFT_FTM_TSF_R2T)
+#define BITS_FTM_TSF_R2T (BIT_MASK_FTM_TSF_R2T << BIT_SHIFT_FTM_TSF_R2T)
+#define BIT_CLEAR_FTM_TSF_R2T(x) ((x) & (~BITS_FTM_TSF_R2T))
+#define BIT_GET_FTM_TSF_R2T(x) \
+ (((x) >> BIT_SHIFT_FTM_TSF_R2T) & BIT_MASK_FTM_TSF_R2T)
+#define BIT_SET_FTM_TSF_R2T(x, v) \
+ (BIT_CLEAR_FTM_TSF_R2T(x) | BIT_FTM_TSF_R2T(v))
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FTM_TSF (Offset 0x054C) */
+#define BIT_SHIFT_FTM_T2_TSF 16
+#define BIT_MASK_FTM_T2_TSF 0xffff
+#define BIT_FTM_T2_TSF(x) (((x) & BIT_MASK_FTM_T2_TSF) << BIT_SHIFT_FTM_T2_TSF)
+#define BITS_FTM_T2_TSF (BIT_MASK_FTM_T2_TSF << BIT_SHIFT_FTM_T2_TSF)
+#define BIT_CLEAR_FTM_T2_TSF(x) ((x) & (~BITS_FTM_T2_TSF))
+#define BIT_GET_FTM_T2_TSF(x) \
+ (((x) >> BIT_SHIFT_FTM_T2_TSF) & BIT_MASK_FTM_T2_TSF)
+#define BIT_SET_FTM_T2_TSF(x, v) (BIT_CLEAR_FTM_T2_TSF(x) | BIT_FTM_T2_TSF(v))
-/* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_BCN_SPACE_CLINT0 16
-#define BIT_MASK_BCN_SPACE_CLINT0 0xfff
-#define BIT_BCN_SPACE_CLINT0(x) (((x) & BIT_MASK_BCN_SPACE_CLINT0) << BIT_SHIFT_BCN_SPACE_CLINT0)
-#define BIT_GET_BCN_SPACE_CLINT0(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT0) & BIT_MASK_BCN_SPACE_CLINT0)
+/* 2 REG_FTM_TSF_CNT (Offset 0x054C) */
+#define BIT_SHIFT_FTM_TSF_T2R 0
+#define BIT_MASK_FTM_TSF_T2R 0xffff
+#define BIT_FTM_TSF_T2R(x) \
+ (((x) & BIT_MASK_FTM_TSF_T2R) << BIT_SHIFT_FTM_TSF_T2R)
+#define BITS_FTM_TSF_T2R (BIT_MASK_FTM_TSF_T2R << BIT_SHIFT_FTM_TSF_T2R)
+#define BIT_CLEAR_FTM_TSF_T2R(x) ((x) & (~BITS_FTM_TSF_T2R))
+#define BIT_GET_FTM_TSF_T2R(x) \
+ (((x) >> BIT_SHIFT_FTM_TSF_T2R) & BIT_MASK_FTM_TSF_T2R)
+#define BIT_SET_FTM_TSF_T2R(x, v) \
+ (BIT_CLEAR_FTM_TSF_T2R(x) | BIT_FTM_TSF_T2R(v))
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_FTM_TSF (Offset 0x054C) */
+#define BIT_SHIFT_FTM_T1_TSF 0
+#define BIT_MASK_FTM_T1_TSF 0xffff
+#define BIT_FTM_T1_TSF(x) (((x) & BIT_MASK_FTM_T1_TSF) << BIT_SHIFT_FTM_T1_TSF)
+#define BITS_FTM_T1_TSF (BIT_MASK_FTM_T1_TSF << BIT_SHIFT_FTM_T1_TSF)
+#define BIT_CLEAR_FTM_T1_TSF(x) ((x) & (~BITS_FTM_T1_TSF))
+#define BIT_GET_FTM_T1_TSF(x) \
+ (((x) >> BIT_SHIFT_FTM_T1_TSF) & BIT_MASK_FTM_T1_TSF)
+#define BIT_SET_FTM_T1_TSF(x, v) (BIT_CLEAR_FTM_T1_TSF(x) | BIT_FTM_T1_TSF(v))
-/* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_BCN_SPACE0 0
-#define BIT_MASK_BCN_SPACE0 0xffff
-#define BIT_BCN_SPACE0(x) (((x) & BIT_MASK_BCN_SPACE0) << BIT_SHIFT_BCN_SPACE0)
-#define BIT_GET_BCN_SPACE0(x) (((x) >> BIT_SHIFT_BCN_SPACE0) & BIT_MASK_BCN_SPACE0)
+/* 2 REG_BCN_CTRL (Offset 0x0550) */
+#define BIT_P0_EN_TXBCN_RPT BIT(5)
-/* 2 REG_DRVERLYINT (Offset 0x0558) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_DRVERLYITV 0
-#define BIT_MASK_DRVERLYITV 0xff
-#define BIT_DRVERLYITV(x) (((x) & BIT_MASK_DRVERLYITV) << BIT_SHIFT_DRVERLYITV)
-#define BIT_GET_DRVERLYITV(x) (((x) >> BIT_SHIFT_DRVERLYITV) & BIT_MASK_DRVERLYITV)
+/* 2 REG_BCN_CTRL (Offset 0x0550) */
+#define BIT_EN_BCN_FUNCTION BIT(3)
-/* 2 REG_BCNDMATIM (Offset 0x0559) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_BCNDMATIM 0
-#define BIT_MASK_BCNDMATIM 0xff
-#define BIT_BCNDMATIM(x) (((x) & BIT_MASK_BCNDMATIM) << BIT_SHIFT_BCNDMATIM)
-#define BIT_GET_BCNDMATIM(x) (((x) >> BIT_SHIFT_BCNDMATIM) & BIT_MASK_BCNDMATIM)
+/* 2 REG_BCN_CTRL (Offset 0x0550) */
+#define BIT_EN_TXBCN_RPT BIT(2)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-
-/* 2 REG_ATIMWND (Offset 0x055A) */
+/* 2 REG_BCN_CTRL (Offset 0x0550) */
+#define BIT_P0_EN_RXBCN_RPT BIT(2)
-#define BIT_SHIFT_ATIMWND 0
-#define BIT_MASK_ATIMWND 0xffff
-#define BIT_ATIMWND(x) (((x) & BIT_MASK_ATIMWND) << BIT_SHIFT_ATIMWND)
-#define BIT_GET_ATIMWND(x) (((x) >> BIT_SHIFT_ATIMWND) & BIT_MASK_ATIMWND)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_BCN_CTRL (Offset 0x0550) */
+#define BIT_DIS_BCNQ_SUB BIT(1)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_BCN_CTRL1 (Offset 0x0551) */
+#define BIT_DIS_RX_BSSID_FIT1 BIT(6)
-/* 2 REG_ATIMWND (Offset 0x055A) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_ATIMWND0 0
-#define BIT_MASK_ATIMWND0 0xffff
-#define BIT_ATIMWND0(x) (((x) & BIT_MASK_ATIMWND0) << BIT_SHIFT_ATIMWND0)
-#define BIT_GET_ATIMWND0(x) (((x) >> BIT_SHIFT_ATIMWND0) & BIT_MASK_ATIMWND0)
+/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */
+#define BIT_CLI0_DIS_RX_BSSID_FIT BIT(6)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_BCN_CTRL1 (Offset 0x0551) */
+#define BIT_DIS_TSF1_UDT BIT(4)
-/* 2 REG_USTIME_TSF (Offset 0x055C) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_USTIME_TSF_V1 0
-#define BIT_MASK_USTIME_TSF_V1 0xff
-#define BIT_USTIME_TSF_V1(x) (((x) & BIT_MASK_USTIME_TSF_V1) << BIT_SHIFT_USTIME_TSF_V1)
-#define BIT_GET_USTIME_TSF_V1(x) (((x) >> BIT_SHIFT_USTIME_TSF_V1) & BIT_MASK_USTIME_TSF_V1)
+/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */
+#define BIT_CLI0_DIS_TSF_UDT BIT(4)
-/* 2 REG_BCN_MAX_ERR (Offset 0x055D) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_BCN_MAX_ERR 0
-#define BIT_MASK_BCN_MAX_ERR 0xff
-#define BIT_BCN_MAX_ERR(x) (((x) & BIT_MASK_BCN_MAX_ERR) << BIT_SHIFT_BCN_MAX_ERR)
-#define BIT_GET_BCN_MAX_ERR(x) (((x) >> BIT_SHIFT_BCN_MAX_ERR) & BIT_MASK_BCN_MAX_ERR)
+/* 2 REG_BCN_CTRL1 (Offset 0x0551) */
+#define BIT_EN_BCN1_FUNCTION BIT(3)
-/* 2 REG_RXTSF_OFFSET_CCK (Offset 0x055E) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_CCK_RXTSF_OFFSET 0
-#define BIT_MASK_CCK_RXTSF_OFFSET 0xff
-#define BIT_CCK_RXTSF_OFFSET(x) (((x) & BIT_MASK_CCK_RXTSF_OFFSET) << BIT_SHIFT_CCK_RXTSF_OFFSET)
-#define BIT_GET_CCK_RXTSF_OFFSET(x) (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET) & BIT_MASK_CCK_RXTSF_OFFSET)
+/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */
+#define BIT_CLI0_EN_BCN_FUNCTION BIT(3)
-/* 2 REG_RXTSF_OFFSET_OFDM (Offset 0x055F) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_OFDM_RXTSF_OFFSET 0
-#define BIT_MASK_OFDM_RXTSF_OFFSET 0xff
-#define BIT_OFDM_RXTSF_OFFSET(x) (((x) & BIT_MASK_OFDM_RXTSF_OFFSET) << BIT_SHIFT_OFDM_RXTSF_OFFSET)
-#define BIT_GET_OFDM_RXTSF_OFFSET(x) (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET) & BIT_MASK_OFDM_RXTSF_OFFSET)
+/* 2 REG_BCN_CTRL1 (Offset 0x0551) */
+#define BIT_EN_TXBCN1_RPT BIT(2)
-/* 2 REG_TSFTR (Offset 0x0560) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_TSF_TIMER 0
-#define BIT_MASK_TSF_TIMER 0xffffffffffffffffL
-#define BIT_TSF_TIMER(x) (((x) & BIT_MASK_TSF_TIMER) << BIT_SHIFT_TSF_TIMER)
-#define BIT_GET_TSF_TIMER(x) (((x) >> BIT_SHIFT_TSF_TIMER) & BIT_MASK_TSF_TIMER)
+/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */
+#define BIT_CLI0_EN_RXBCN_RPT BIT(2)
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */
+#define BIT_CLI0_EN_BCN_RPT BIT(2)
-/* 2 REG_TSFTR1 (Offset 0x0568) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_TSF_TIMER1 0
-#define BIT_MASK_TSF_TIMER1 0xffffffffffffffffL
-#define BIT_TSF_TIMER1(x) (((x) & BIT_MASK_TSF_TIMER1) << BIT_SHIFT_TSF_TIMER1)
-#define BIT_GET_TSF_TIMER1(x) (((x) >> BIT_SHIFT_TSF_TIMER1) & BIT_MASK_TSF_TIMER1)
+/* 2 REG_BCN_CTRL1 (Offset 0x0551) */
+#define BIT_DIS_BCNQ1_SUB BIT(1)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */
+#define BIT_CLI0_ENP2P_CTWINDOW BIT(1)
+#define BIT_CLI0_ENP2P_BCNQ_AREA BIT(0)
-/* 2 REG_FREERUN_CNT (Offset 0x0568) */
+#endif
+#if (HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_FREERUN_CNT 0
-#define BIT_MASK_FREERUN_CNT 0xffffffffffffffffL
-#define BIT_FREERUN_CNT(x) (((x) & BIT_MASK_FREERUN_CNT) << BIT_SHIFT_FREERUN_CNT)
-#define BIT_GET_FREERUN_CNT(x) (((x) >> BIT_SHIFT_FREERUN_CNT) & BIT_MASK_FREERUN_CNT)
+/* 2 REG_MBID_NUM (Offset 0x0552) */
+#define BIT_SHIFT_MBID_BCN_NUM_V2 4
+#define BIT_MASK_MBID_BCN_NUM_V2 0xf
+#define BIT_MBID_BCN_NUM_V2(x) \
+ (((x) & BIT_MASK_MBID_BCN_NUM_V2) << BIT_SHIFT_MBID_BCN_NUM_V2)
+#define BITS_MBID_BCN_NUM_V2 \
+ (BIT_MASK_MBID_BCN_NUM_V2 << BIT_SHIFT_MBID_BCN_NUM_V2)
+#define BIT_CLEAR_MBID_BCN_NUM_V2(x) ((x) & (~BITS_MBID_BCN_NUM_V2))
+#define BIT_GET_MBID_BCN_NUM_V2(x) \
+ (((x) >> BIT_SHIFT_MBID_BCN_NUM_V2) & BIT_MASK_MBID_BCN_NUM_V2)
+#define BIT_SET_MBID_BCN_NUM_V2(x, v) \
+ (BIT_CLEAR_MBID_BCN_NUM_V2(x) | BIT_MBID_BCN_NUM_V2(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_MBID_NUM (Offset 0x0552) */
+#define BIT_EN_PRE_DL_BEACON BIT(3)
-/* 2 REG_ATIMWND1 (Offset 0x0570) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_ATIMWND1 0
-#define BIT_MASK_ATIMWND1 0xffff
-#define BIT_ATIMWND1(x) (((x) & BIT_MASK_ATIMWND1) << BIT_SHIFT_ATIMWND1)
-#define BIT_GET_ATIMWND1(x) (((x) >> BIT_SHIFT_ATIMWND1) & BIT_MASK_ATIMWND1)
+/* 2 REG_MBID_NUM (Offset 0x0552) */
+#define BIT_SHIFT_MBID_BCN_NUM 0
+#define BIT_MASK_MBID_BCN_NUM 0x7
+#define BIT_MBID_BCN_NUM(x) \
+ (((x) & BIT_MASK_MBID_BCN_NUM) << BIT_SHIFT_MBID_BCN_NUM)
+#define BITS_MBID_BCN_NUM (BIT_MASK_MBID_BCN_NUM << BIT_SHIFT_MBID_BCN_NUM)
+#define BIT_CLEAR_MBID_BCN_NUM(x) ((x) & (~BITS_MBID_BCN_NUM))
+#define BIT_GET_MBID_BCN_NUM(x) \
+ (((x) >> BIT_SHIFT_MBID_BCN_NUM) & BIT_MASK_MBID_BCN_NUM)
+#define BIT_SET_MBID_BCN_NUM(x, v) \
+ (BIT_CLEAR_MBID_BCN_NUM(x) | BIT_MBID_BCN_NUM(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */
+#define BIT_P2P_PWR_RST1 BIT(6)
+#define BIT_SCHEDULER_RST BIT(5)
-/* 2 REG_ATIMWND1_V1 (Offset 0x0570) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_ATIMWND1_V1 0
-#define BIT_MASK_ATIMWND1_V1 0xff
-#define BIT_ATIMWND1_V1(x) (((x) & BIT_MASK_ATIMWND1_V1) << BIT_SHIFT_ATIMWND1_V1)
-#define BIT_GET_ATIMWND1_V1(x) (((x) >> BIT_SHIFT_ATIMWND1_V1) & BIT_MASK_ATIMWND1_V1)
+/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */
+#define BIT_FREECNT_RST BIT(5)
-/* 2 REG_TBTT_PROHIBIT_INFRA (Offset 0x0571) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_TBTT_PROHIBIT_INFRA 0
-#define BIT_MASK_TBTT_PROHIBIT_INFRA 0xff
-#define BIT_TBTT_PROHIBIT_INFRA(x) (((x) & BIT_MASK_TBTT_PROHIBIT_INFRA) << BIT_SHIFT_TBTT_PROHIBIT_INFRA)
-#define BIT_GET_TBTT_PROHIBIT_INFRA(x) (((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA) & BIT_MASK_TBTT_PROHIBIT_INFRA)
+/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */
+#define BIT_P2P_PWR_RST0 BIT(4)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */
+#define BIT_TSFTR_CLI3_RST BIT(4)
-/* 2 REG_CTWND (Offset 0x0572) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_CTWND 0
-#define BIT_MASK_CTWND 0xff
-#define BIT_CTWND(x) (((x) & BIT_MASK_CTWND) << BIT_SHIFT_CTWND)
-#define BIT_GET_CTWND(x) (((x) >> BIT_SHIFT_CTWND) & BIT_MASK_CTWND)
+/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */
+#define BIT_TSFTR1_SYNC_EN BIT(3)
-/* 2 REG_BCNIVLCUNT (Offset 0x0573) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_BCNIVLCUNT 0
-#define BIT_MASK_BCNIVLCUNT 0x7f
-#define BIT_BCNIVLCUNT(x) (((x) & BIT_MASK_BCNIVLCUNT) << BIT_SHIFT_BCNIVLCUNT)
-#define BIT_GET_BCNIVLCUNT(x) (((x) >> BIT_SHIFT_BCNIVLCUNT) & BIT_MASK_BCNIVLCUNT)
+/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */
+#define BIT_TSFTR_CLI2_RST BIT(3)
-/* 2 REG_BCNDROPCTRL (Offset 0x0574) */
+#endif
-#define BIT_BEACON_DROP_EN BIT(7)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_BEACON_DROP_IVL 0
-#define BIT_MASK_BEACON_DROP_IVL 0x7f
-#define BIT_BEACON_DROP_IVL(x) (((x) & BIT_MASK_BEACON_DROP_IVL) << BIT_SHIFT_BEACON_DROP_IVL)
-#define BIT_GET_BEACON_DROP_IVL(x) (((x) >> BIT_SHIFT_BEACON_DROP_IVL) & BIT_MASK_BEACON_DROP_IVL)
+/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */
+#define BIT_TSFTR_SYNC_EN BIT(2)
-/* 2 REG_HGQ_TIMEOUT_PERIOD (Offset 0x0575) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_HGQ_TIMEOUT_PERIOD 0
-#define BIT_MASK_HGQ_TIMEOUT_PERIOD 0xff
-#define BIT_HGQ_TIMEOUT_PERIOD(x) (((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD) << BIT_SHIFT_HGQ_TIMEOUT_PERIOD)
-#define BIT_GET_HGQ_TIMEOUT_PERIOD(x) (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD) & BIT_MASK_HGQ_TIMEOUT_PERIOD)
+/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */
+#define BIT_TSFTR_CLI1_RST BIT(2)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */
+#define BIT_TSFTR1_RST BIT(1)
-/* 2 REG_TXCMD_TIMEOUT_PERIOD (Offset 0x0576) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD 0
-#define BIT_MASK_TXCMD_TIMEOUT_PERIOD 0xff
-#define BIT_TXCMD_TIMEOUT_PERIOD(x) (((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD) << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD)
-#define BIT_GET_TXCMD_TIMEOUT_PERIOD(x) (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD) & BIT_MASK_TXCMD_TIMEOUT_PERIOD)
+/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */
+#define BIT_TSFTR_CLI0_RST BIT(1)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_DUAL_TSF_RST (Offset 0x0553) */
+#define BIT_TSFTR_RST BIT(0)
-/* 2 REG_MISC_CTRL (Offset 0x0577) */
+#endif
-#define BIT_DIS_MARK_TSF_US BIT(7)
-#define BIT_EN_TSFAUTO_SYNC BIT(6)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */
+#define BIT_SHIFT_BCN_TIMER_SEL_FWRD 28
+#define BIT_MASK_BCN_TIMER_SEL_FWRD 0x7
+#define BIT_BCN_TIMER_SEL_FWRD(x) \
+ (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD) << BIT_SHIFT_BCN_TIMER_SEL_FWRD)
+#define BITS_BCN_TIMER_SEL_FWRD \
+ (BIT_MASK_BCN_TIMER_SEL_FWRD << BIT_SHIFT_BCN_TIMER_SEL_FWRD)
+#define BIT_CLEAR_BCN_TIMER_SEL_FWRD(x) ((x) & (~BITS_BCN_TIMER_SEL_FWRD))
+#define BIT_GET_BCN_TIMER_SEL_FWRD(x) \
+ (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD) & BIT_MASK_BCN_TIMER_SEL_FWRD)
+#define BIT_SET_BCN_TIMER_SEL_FWRD(x, v) \
+ (BIT_CLEAR_BCN_TIMER_SEL_FWRD(x) | BIT_BCN_TIMER_SEL_FWRD(v))
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_MISC_CTRL (Offset 0x0577) */
+/* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */
-#define BIT_DIS_TRX_CAL_BCN BIT(5)
-#define BIT_DIS_TX_CAL_TBTT BIT(4)
-#define BIT_EN_FREECNT BIT(3)
-#define BIT_BCN_AGGRESSION BIT(2)
+#define BIT_SHIFT_BCN_SPACE1 16
+#define BIT_MASK_BCN_SPACE1 0xffff
+#define BIT_BCN_SPACE1(x) (((x) & BIT_MASK_BCN_SPACE1) << BIT_SHIFT_BCN_SPACE1)
+#define BITS_BCN_SPACE1 (BIT_MASK_BCN_SPACE1 << BIT_SHIFT_BCN_SPACE1)
+#define BIT_CLEAR_BCN_SPACE1(x) ((x) & (~BITS_BCN_SPACE1))
+#define BIT_GET_BCN_SPACE1(x) \
+ (((x) >> BIT_SHIFT_BCN_SPACE1) & BIT_MASK_BCN_SPACE1)
+#define BIT_SET_BCN_SPACE1(x, v) (BIT_CLEAR_BCN_SPACE1(x) | BIT_BCN_SPACE1(v))
-#define BIT_SHIFT_DIS_SECONDARY_CCA 0
-#define BIT_MASK_DIS_SECONDARY_CCA 0x3
-#define BIT_DIS_SECONDARY_CCA(x) (((x) & BIT_MASK_DIS_SECONDARY_CCA) << BIT_SHIFT_DIS_SECONDARY_CCA)
-#define BIT_GET_DIS_SECONDARY_CCA(x) (((x) >> BIT_SHIFT_DIS_SECONDARY_CCA) & BIT_MASK_DIS_SECONDARY_CCA)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-/* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */
+/* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */
-#define BIT_CLI1_DIS_RX_BSSID_FIT BIT(6)
-#define BIT_CLI1_DIS_TSF_UDT BIT(4)
-#define BIT_CLI1_EN_BCN_FUNCTION BIT(3)
+#define BIT_SHIFT_BCN_SPACE_CLINT0 16
+#define BIT_MASK_BCN_SPACE_CLINT0 0xfff
+#define BIT_BCN_SPACE_CLINT0(x) \
+ (((x) & BIT_MASK_BCN_SPACE_CLINT0) << BIT_SHIFT_BCN_SPACE_CLINT0)
+#define BITS_BCN_SPACE_CLINT0 \
+ (BIT_MASK_BCN_SPACE_CLINT0 << BIT_SHIFT_BCN_SPACE_CLINT0)
+#define BIT_CLEAR_BCN_SPACE_CLINT0(x) ((x) & (~BITS_BCN_SPACE_CLINT0))
+#define BIT_GET_BCN_SPACE_CLINT0(x) \
+ (((x) >> BIT_SHIFT_BCN_SPACE_CLINT0) & BIT_MASK_BCN_SPACE_CLINT0)
+#define BIT_SET_BCN_SPACE_CLINT0(x, v) \
+ (BIT_CLEAR_BCN_SPACE_CLINT0(x) | BIT_BCN_SPACE_CLINT0(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */
+#define BIT_SHIFT_BCN_SPACE0 0
+#define BIT_MASK_BCN_SPACE0 0xffff
+#define BIT_BCN_SPACE0(x) (((x) & BIT_MASK_BCN_SPACE0) << BIT_SHIFT_BCN_SPACE0)
+#define BITS_BCN_SPACE0 (BIT_MASK_BCN_SPACE0 << BIT_SHIFT_BCN_SPACE0)
+#define BIT_CLEAR_BCN_SPACE0(x) ((x) & (~BITS_BCN_SPACE0))
+#define BIT_GET_BCN_SPACE0(x) \
+ (((x) >> BIT_SHIFT_BCN_SPACE0) & BIT_MASK_BCN_SPACE0)
+#define BIT_SET_BCN_SPACE0(x, v) (BIT_CLEAR_BCN_SPACE0(x) | BIT_BCN_SPACE0(v))
-/* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */
+#endif
-#define BIT_CLI1_EN_RXBCN_RPT BIT(2)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_ATIMWND (Offset 0x055A) */
+#define BIT_SHIFT_ATIMWND 0
+#define BIT_MASK_ATIMWND 0xffff
+#define BIT_ATIMWND(x) (((x) & BIT_MASK_ATIMWND) << BIT_SHIFT_ATIMWND)
+#define BITS_ATIMWND (BIT_MASK_ATIMWND << BIT_SHIFT_ATIMWND)
+#define BIT_CLEAR_ATIMWND(x) ((x) & (~BITS_ATIMWND))
+#define BIT_GET_ATIMWND(x) (((x) >> BIT_SHIFT_ATIMWND) & BIT_MASK_ATIMWND)
+#define BIT_SET_ATIMWND(x, v) (BIT_CLEAR_ATIMWND(x) | BIT_ATIMWND(v))
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-/* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */
+/* 2 REG_ATIMWND (Offset 0x055A) */
-#define BIT_CLI1_EN_BCN_RPT BIT(2)
+#define BIT_SHIFT_ATIMWND0 0
+#define BIT_MASK_ATIMWND0 0xffff
+#define BIT_ATIMWND0(x) (((x) & BIT_MASK_ATIMWND0) << BIT_SHIFT_ATIMWND0)
+#define BITS_ATIMWND0 (BIT_MASK_ATIMWND0 << BIT_SHIFT_ATIMWND0)
+#define BIT_CLEAR_ATIMWND0(x) ((x) & (~BITS_ATIMWND0))
+#define BIT_GET_ATIMWND0(x) (((x) >> BIT_SHIFT_ATIMWND0) & BIT_MASK_ATIMWND0)
+#define BIT_SET_ATIMWND0(x, v) (BIT_CLEAR_ATIMWND0(x) | BIT_ATIMWND0(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_USTIME_TSF (Offset 0x055C) */
+#define BIT_SHIFT_USTIME_TSF_V1 0
+#define BIT_MASK_USTIME_TSF_V1 0xff
+#define BIT_USTIME_TSF_V1(x) \
+ (((x) & BIT_MASK_USTIME_TSF_V1) << BIT_SHIFT_USTIME_TSF_V1)
+#define BITS_USTIME_TSF_V1 (BIT_MASK_USTIME_TSF_V1 << BIT_SHIFT_USTIME_TSF_V1)
+#define BIT_CLEAR_USTIME_TSF_V1(x) ((x) & (~BITS_USTIME_TSF_V1))
+#define BIT_GET_USTIME_TSF_V1(x) \
+ (((x) >> BIT_SHIFT_USTIME_TSF_V1) & BIT_MASK_USTIME_TSF_V1)
+#define BIT_SET_USTIME_TSF_V1(x, v) \
+ (BIT_CLEAR_USTIME_TSF_V1(x) | BIT_USTIME_TSF_V1(v))
-/* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */
+/* 2 REG_BCN_MAX_ERR (Offset 0x055D) */
-#define BIT_CLI1_ENP2P_CTWINDOW BIT(1)
-#define BIT_CLI1_ENP2P_BCNQ_AREA BIT(0)
+#define BIT_SHIFT_BCN_MAX_ERR 0
+#define BIT_MASK_BCN_MAX_ERR 0xff
+#define BIT_BCN_MAX_ERR(x) \
+ (((x) & BIT_MASK_BCN_MAX_ERR) << BIT_SHIFT_BCN_MAX_ERR)
+#define BITS_BCN_MAX_ERR (BIT_MASK_BCN_MAX_ERR << BIT_SHIFT_BCN_MAX_ERR)
+#define BIT_CLEAR_BCN_MAX_ERR(x) ((x) & (~BITS_BCN_MAX_ERR))
+#define BIT_GET_BCN_MAX_ERR(x) \
+ (((x) >> BIT_SHIFT_BCN_MAX_ERR) & BIT_MASK_BCN_MAX_ERR)
+#define BIT_SET_BCN_MAX_ERR(x, v) \
+ (BIT_CLEAR_BCN_MAX_ERR(x) | BIT_BCN_MAX_ERR(v))
-/* 2 REG_BCN_CTRL_CLINT2 (Offset 0x0579) */
+/* 2 REG_RXTSF_OFFSET_CCK (Offset 0x055E) */
-#define BIT_CLI2_DIS_RX_BSSID_FIT BIT(6)
-#define BIT_CLI2_DIS_TSF_UDT BIT(4)
-#define BIT_CLI2_EN_BCN_FUNCTION BIT(3)
+#define BIT_SHIFT_CCK_RXTSF_OFFSET 0
+#define BIT_MASK_CCK_RXTSF_OFFSET 0xff
+#define BIT_CCK_RXTSF_OFFSET(x) \
+ (((x) & BIT_MASK_CCK_RXTSF_OFFSET) << BIT_SHIFT_CCK_RXTSF_OFFSET)
+#define BITS_CCK_RXTSF_OFFSET \
+ (BIT_MASK_CCK_RXTSF_OFFSET << BIT_SHIFT_CCK_RXTSF_OFFSET)
+#define BIT_CLEAR_CCK_RXTSF_OFFSET(x) ((x) & (~BITS_CCK_RXTSF_OFFSET))
+#define BIT_GET_CCK_RXTSF_OFFSET(x) \
+ (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET) & BIT_MASK_CCK_RXTSF_OFFSET)
+#define BIT_SET_CCK_RXTSF_OFFSET(x, v) \
+ (BIT_CLEAR_CCK_RXTSF_OFFSET(x) | BIT_CCK_RXTSF_OFFSET(v))
-#endif
+/* 2 REG_RXTSF_OFFSET_OFDM (Offset 0x055F) */
+#define BIT_SHIFT_OFDM_RXTSF_OFFSET 0
+#define BIT_MASK_OFDM_RXTSF_OFFSET 0xff
+#define BIT_OFDM_RXTSF_OFFSET(x) \
+ (((x) & BIT_MASK_OFDM_RXTSF_OFFSET) << BIT_SHIFT_OFDM_RXTSF_OFFSET)
+#define BITS_OFDM_RXTSF_OFFSET \
+ (BIT_MASK_OFDM_RXTSF_OFFSET << BIT_SHIFT_OFDM_RXTSF_OFFSET)
+#define BIT_CLEAR_OFDM_RXTSF_OFFSET(x) ((x) & (~BITS_OFDM_RXTSF_OFFSET))
+#define BIT_GET_OFDM_RXTSF_OFFSET(x) \
+ (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET) & BIT_MASK_OFDM_RXTSF_OFFSET)
+#define BIT_SET_OFDM_RXTSF_OFFSET(x, v) \
+ (BIT_CLEAR_OFDM_RXTSF_OFFSET(x) | BIT_OFDM_RXTSF_OFFSET(v))
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#define BIT_SHIFT_CTWND 0
+#define BIT_MASK_CTWND 0xff
+#define BIT_CTWND(x) (((x) & BIT_MASK_CTWND) << BIT_SHIFT_CTWND)
+#define BITS_CTWND (BIT_MASK_CTWND << BIT_SHIFT_CTWND)
+#define BIT_CLEAR_CTWND(x) ((x) & (~BITS_CTWND))
+#define BIT_GET_CTWND(x) (((x) >> BIT_SHIFT_CTWND) & BIT_MASK_CTWND)
+#define BIT_SET_CTWND(x, v) (BIT_CLEAR_CTWND(x) | BIT_CTWND(v))
+#endif
-/* 2 REG_BCN_CTRL_CLINT2 (Offset 0x0579) */
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_CLI2_EN_RXBCN_RPT BIT(2)
+/* 2 REG_TSFTR (Offset 0x0560) */
+
+#define BIT_SHIFT_TSF_TIMER 0
+#define BIT_MASK_TSF_TIMER 0xffffffffffffffffL
+#define BIT_TSF_TIMER(x) (((x) & BIT_MASK_TSF_TIMER) << BIT_SHIFT_TSF_TIMER)
+#define BITS_TSF_TIMER (BIT_MASK_TSF_TIMER << BIT_SHIFT_TSF_TIMER)
+#define BIT_CLEAR_TSF_TIMER(x) ((x) & (~BITS_TSF_TIMER))
+#define BIT_GET_TSF_TIMER(x) (((x) >> BIT_SHIFT_TSF_TIMER) & BIT_MASK_TSF_TIMER)
+#define BIT_SET_TSF_TIMER(x, v) (BIT_CLEAR_TSF_TIMER(x) | BIT_TSF_TIMER(v))
#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_TSFTR (Offset 0x0560) */
+#define BIT_SHIFT_TSF_TIMER_V1 0
+#define BIT_MASK_TSF_TIMER_V1 0xffffffffL
+#define BIT_TSF_TIMER_V1(x) \
+ (((x) & BIT_MASK_TSF_TIMER_V1) << BIT_SHIFT_TSF_TIMER_V1)
+#define BITS_TSF_TIMER_V1 (BIT_MASK_TSF_TIMER_V1 << BIT_SHIFT_TSF_TIMER_V1)
+#define BIT_CLEAR_TSF_TIMER_V1(x) ((x) & (~BITS_TSF_TIMER_V1))
+#define BIT_GET_TSF_TIMER_V1(x) \
+ (((x) >> BIT_SHIFT_TSF_TIMER_V1) & BIT_MASK_TSF_TIMER_V1)
+#define BIT_SET_TSF_TIMER_V1(x, v) \
+ (BIT_CLEAR_TSF_TIMER_V1(x) | BIT_TSF_TIMER_V1(v))
-/* 2 REG_BCN_CTRL_CLINT2 (Offset 0x0579) */
+/* 2 REG_TSFTR_1 (Offset 0x0564) */
-#define BIT_CLI2_EN_BCN_RPT BIT(2)
+#define BIT_SHIFT_TSF_TIMER_V2 0
+#define BIT_MASK_TSF_TIMER_V2 0xffffffffL
+#define BIT_TSF_TIMER_V2(x) \
+ (((x) & BIT_MASK_TSF_TIMER_V2) << BIT_SHIFT_TSF_TIMER_V2)
+#define BITS_TSF_TIMER_V2 (BIT_MASK_TSF_TIMER_V2 << BIT_SHIFT_TSF_TIMER_V2)
+#define BIT_CLEAR_TSF_TIMER_V2(x) ((x) & (~BITS_TSF_TIMER_V2))
+#define BIT_GET_TSF_TIMER_V2(x) \
+ (((x) >> BIT_SHIFT_TSF_TIMER_V2) & BIT_MASK_TSF_TIMER_V2)
+#define BIT_SET_TSF_TIMER_V2(x, v) \
+ (BIT_CLEAR_TSF_TIMER_V2(x) | BIT_TSF_TIMER_V2(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_TSFTR1 (Offset 0x0568) */
+#define BIT_SHIFT_TSF_TIMER1 0
+#define BIT_MASK_TSF_TIMER1 0xffffffffffffffffL
+#define BIT_TSF_TIMER1(x) (((x) & BIT_MASK_TSF_TIMER1) << BIT_SHIFT_TSF_TIMER1)
+#define BITS_TSF_TIMER1 (BIT_MASK_TSF_TIMER1 << BIT_SHIFT_TSF_TIMER1)
+#define BIT_CLEAR_TSF_TIMER1(x) ((x) & (~BITS_TSF_TIMER1))
+#define BIT_GET_TSF_TIMER1(x) \
+ (((x) >> BIT_SHIFT_TSF_TIMER1) & BIT_MASK_TSF_TIMER1)
+#define BIT_SET_TSF_TIMER1(x, v) (BIT_CLEAR_TSF_TIMER1(x) | BIT_TSF_TIMER1(v))
-/* 2 REG_BCN_CTRL_CLINT2 (Offset 0x0579) */
+#endif
-#define BIT_CLI2_ENP2P_CTWINDOW BIT(1)
-#define BIT_CLI2_ENP2P_BCNQ_AREA BIT(0)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
-/* 2 REG_BCN_CTRL_CLINT3 (Offset 0x057A) */
+/* 2 REG_FREERUN_CNT (Offset 0x0568) */
-#define BIT_CLI3_DIS_RX_BSSID_FIT BIT(6)
-#define BIT_CLI3_DIS_TSF_UDT BIT(4)
-#define BIT_CLI3_EN_BCN_FUNCTION BIT(3)
+#define BIT_SHIFT_FREERUN_CNT 0
+#define BIT_MASK_FREERUN_CNT 0xffffffffffffffffL
+#define BIT_FREERUN_CNT(x) \
+ (((x) & BIT_MASK_FREERUN_CNT) << BIT_SHIFT_FREERUN_CNT)
+#define BITS_FREERUN_CNT (BIT_MASK_FREERUN_CNT << BIT_SHIFT_FREERUN_CNT)
+#define BIT_CLEAR_FREERUN_CNT(x) ((x) & (~BITS_FREERUN_CNT))
+#define BIT_GET_FREERUN_CNT(x) \
+ (((x) >> BIT_SHIFT_FREERUN_CNT) & BIT_MASK_FREERUN_CNT)
+#define BIT_SET_FREERUN_CNT(x, v) \
+ (BIT_CLEAR_FREERUN_CNT(x) | BIT_FREERUN_CNT(v))
#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FREERUN_CNT (Offset 0x0568) */
+#define BIT_SHIFT_FREERUN_CNT_V1 0
+#define BIT_MASK_FREERUN_CNT_V1 0xffffffffL
+#define BIT_FREERUN_CNT_V1(x) \
+ (((x) & BIT_MASK_FREERUN_CNT_V1) << BIT_SHIFT_FREERUN_CNT_V1)
+#define BITS_FREERUN_CNT_V1 \
+ (BIT_MASK_FREERUN_CNT_V1 << BIT_SHIFT_FREERUN_CNT_V1)
+#define BIT_CLEAR_FREERUN_CNT_V1(x) ((x) & (~BITS_FREERUN_CNT_V1))
+#define BIT_GET_FREERUN_CNT_V1(x) \
+ (((x) >> BIT_SHIFT_FREERUN_CNT_V1) & BIT_MASK_FREERUN_CNT_V1)
+#define BIT_SET_FREERUN_CNT_V1(x, v) \
+ (BIT_CLEAR_FREERUN_CNT_V1(x) | BIT_FREERUN_CNT_V1(v))
-/* 2 REG_BCN_CTRL_CLINT3 (Offset 0x057A) */
+/* 2 REG_FREERUN_CNT_1 (Offset 0x056C) */
-#define BIT_CLI3_EN_RXBCN_RPT BIT(2)
+#define BIT_SHIFT_FREERUN_CNT_V2 0
+#define BIT_MASK_FREERUN_CNT_V2 0xffffffffL
+#define BIT_FREERUN_CNT_V2(x) \
+ (((x) & BIT_MASK_FREERUN_CNT_V2) << BIT_SHIFT_FREERUN_CNT_V2)
+#define BITS_FREERUN_CNT_V2 \
+ (BIT_MASK_FREERUN_CNT_V2 << BIT_SHIFT_FREERUN_CNT_V2)
+#define BIT_CLEAR_FREERUN_CNT_V2(x) ((x) & (~BITS_FREERUN_CNT_V2))
+#define BIT_GET_FREERUN_CNT_V2(x) \
+ (((x) >> BIT_SHIFT_FREERUN_CNT_V2) & BIT_MASK_FREERUN_CNT_V2)
+#define BIT_SET_FREERUN_CNT_V2(x, v) \
+ (BIT_CLEAR_FREERUN_CNT_V2(x) | BIT_FREERUN_CNT_V2(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
-
-/* 2 REG_BCN_CTRL_CLINT3 (Offset 0x057A) */
+/* 2 REG_ATIMWND1 (Offset 0x0570) */
-#define BIT_CLI3_EN_BCN_RPT BIT(2)
+#define BIT_SHIFT_ATIMWND1 0
+#define BIT_MASK_ATIMWND1 0xffff
+#define BIT_ATIMWND1(x) (((x) & BIT_MASK_ATIMWND1) << BIT_SHIFT_ATIMWND1)
+#define BITS_ATIMWND1 (BIT_MASK_ATIMWND1 << BIT_SHIFT_ATIMWND1)
+#define BIT_CLEAR_ATIMWND1(x) ((x) & (~BITS_ATIMWND1))
+#define BIT_GET_ATIMWND1(x) (((x) >> BIT_SHIFT_ATIMWND1) & BIT_MASK_ATIMWND1)
+#define BIT_SET_ATIMWND1(x, v) (BIT_CLEAR_ATIMWND1(x) | BIT_ATIMWND1(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ATIMWND1_V1 (Offset 0x0570) */
+#define BIT_SHIFT_ATIMWND1_V1 0
+#define BIT_MASK_ATIMWND1_V1 0xff
+#define BIT_ATIMWND1_V1(x) \
+ (((x) & BIT_MASK_ATIMWND1_V1) << BIT_SHIFT_ATIMWND1_V1)
+#define BITS_ATIMWND1_V1 (BIT_MASK_ATIMWND1_V1 << BIT_SHIFT_ATIMWND1_V1)
+#define BIT_CLEAR_ATIMWND1_V1(x) ((x) & (~BITS_ATIMWND1_V1))
+#define BIT_GET_ATIMWND1_V1(x) \
+ (((x) >> BIT_SHIFT_ATIMWND1_V1) & BIT_MASK_ATIMWND1_V1)
+#define BIT_SET_ATIMWND1_V1(x, v) \
+ (BIT_CLEAR_ATIMWND1_V1(x) | BIT_ATIMWND1_V1(v))
-/* 2 REG_BCN_CTRL_CLINT3 (Offset 0x057A) */
+/* 2 REG_TBTT_PROHIBIT_INFRA (Offset 0x0571) */
-#define BIT_CLI3_ENP2P_CTWINDOW BIT(1)
-#define BIT_CLI3_ENP2P_BCNQ_AREA BIT(0)
+#define BIT_SHIFT_TBTT_PROHIBIT_INFRA 0
+#define BIT_MASK_TBTT_PROHIBIT_INFRA 0xff
+#define BIT_TBTT_PROHIBIT_INFRA(x) \
+ (((x) & BIT_MASK_TBTT_PROHIBIT_INFRA) << BIT_SHIFT_TBTT_PROHIBIT_INFRA)
+#define BITS_TBTT_PROHIBIT_INFRA \
+ (BIT_MASK_TBTT_PROHIBIT_INFRA << BIT_SHIFT_TBTT_PROHIBIT_INFRA)
+#define BIT_CLEAR_TBTT_PROHIBIT_INFRA(x) ((x) & (~BITS_TBTT_PROHIBIT_INFRA))
+#define BIT_GET_TBTT_PROHIBIT_INFRA(x) \
+ (((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA) & BIT_MASK_TBTT_PROHIBIT_INFRA)
+#define BIT_SET_TBTT_PROHIBIT_INFRA(x, v) \
+ (BIT_CLEAR_TBTT_PROHIBIT_INFRA(x) | BIT_TBTT_PROHIBIT_INFRA(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_BCNIVLCUNT (Offset 0x0573) */
+#define BIT_SHIFT_BCNIVLCUNT 0
+#define BIT_MASK_BCNIVLCUNT 0x7f
+#define BIT_BCNIVLCUNT(x) (((x) & BIT_MASK_BCNIVLCUNT) << BIT_SHIFT_BCNIVLCUNT)
+#define BITS_BCNIVLCUNT (BIT_MASK_BCNIVLCUNT << BIT_SHIFT_BCNIVLCUNT)
+#define BIT_CLEAR_BCNIVLCUNT(x) ((x) & (~BITS_BCNIVLCUNT))
+#define BIT_GET_BCNIVLCUNT(x) \
+ (((x) >> BIT_SHIFT_BCNIVLCUNT) & BIT_MASK_BCNIVLCUNT)
+#define BIT_SET_BCNIVLCUNT(x, v) (BIT_CLEAR_BCNIVLCUNT(x) | BIT_BCNIVLCUNT(v))
-/* 2 REG_EXTEND_CTRL (Offset 0x057B) */
+/* 2 REG_BCNDROPCTRL (Offset 0x0574) */
+
+#define BIT_BEACON_DROP_EN BIT(7)
-#define BIT_EN_TSFBIT32_RST_P2P2 BIT(5)
-#define BIT_EN_TSFBIT32_RST_P2P1 BIT(4)
+#define BIT_SHIFT_BEACON_DROP_IVL 0
+#define BIT_MASK_BEACON_DROP_IVL 0x7f
+#define BIT_BEACON_DROP_IVL(x) \
+ (((x) & BIT_MASK_BEACON_DROP_IVL) << BIT_SHIFT_BEACON_DROP_IVL)
+#define BITS_BEACON_DROP_IVL \
+ (BIT_MASK_BEACON_DROP_IVL << BIT_SHIFT_BEACON_DROP_IVL)
+#define BIT_CLEAR_BEACON_DROP_IVL(x) ((x) & (~BITS_BEACON_DROP_IVL))
+#define BIT_GET_BEACON_DROP_IVL(x) \
+ (((x) >> BIT_SHIFT_BEACON_DROP_IVL) & BIT_MASK_BEACON_DROP_IVL)
+#define BIT_SET_BEACON_DROP_IVL(x, v) \
+ (BIT_CLEAR_BEACON_DROP_IVL(x) | BIT_BEACON_DROP_IVL(v))
-#define BIT_SHIFT_PORT_SEL 0
-#define BIT_MASK_PORT_SEL 0x7
-#define BIT_PORT_SEL(x) (((x) & BIT_MASK_PORT_SEL) << BIT_SHIFT_PORT_SEL)
-#define BIT_GET_PORT_SEL(x) (((x) >> BIT_SHIFT_PORT_SEL) & BIT_MASK_PORT_SEL)
+/* 2 REG_HGQ_TIMEOUT_PERIOD (Offset 0x0575) */
+#define BIT_SHIFT_HGQ_TIMEOUT_PERIOD 0
+#define BIT_MASK_HGQ_TIMEOUT_PERIOD 0xff
+#define BIT_HGQ_TIMEOUT_PERIOD(x) \
+ (((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD) << BIT_SHIFT_HGQ_TIMEOUT_PERIOD)
+#define BITS_HGQ_TIMEOUT_PERIOD \
+ (BIT_MASK_HGQ_TIMEOUT_PERIOD << BIT_SHIFT_HGQ_TIMEOUT_PERIOD)
+#define BIT_CLEAR_HGQ_TIMEOUT_PERIOD(x) ((x) & (~BITS_HGQ_TIMEOUT_PERIOD))
+#define BIT_GET_HGQ_TIMEOUT_PERIOD(x) \
+ (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD) & BIT_MASK_HGQ_TIMEOUT_PERIOD)
+#define BIT_SET_HGQ_TIMEOUT_PERIOD(x, v) \
+ (BIT_CLEAR_HGQ_TIMEOUT_PERIOD(x) | BIT_HGQ_TIMEOUT_PERIOD(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_TXCMD_TIMEOUT_PERIOD (Offset 0x0576) */
+#define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD 0
+#define BIT_MASK_TXCMD_TIMEOUT_PERIOD 0xff
+#define BIT_TXCMD_TIMEOUT_PERIOD(x) \
+ (((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD) \
+ << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD)
+#define BITS_TXCMD_TIMEOUT_PERIOD \
+ (BIT_MASK_TXCMD_TIMEOUT_PERIOD << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD)
+#define BIT_CLEAR_TXCMD_TIMEOUT_PERIOD(x) ((x) & (~BITS_TXCMD_TIMEOUT_PERIOD))
+#define BIT_GET_TXCMD_TIMEOUT_PERIOD(x) \
+ (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD) & \
+ BIT_MASK_TXCMD_TIMEOUT_PERIOD)
+#define BIT_SET_TXCMD_TIMEOUT_PERIOD(x, v) \
+ (BIT_CLEAR_TXCMD_TIMEOUT_PERIOD(x) | BIT_TXCMD_TIMEOUT_PERIOD(v))
-/* 2 REG_P2PPS1_SPEC_STATE (Offset 0x057C) */
+#endif
-#define BIT_P2P1_SPEC_POWER_STATE BIT(7)
-#define BIT_P2P1_SPEC_CTWINDOW_ON BIT(6)
-#define BIT_P2P1_SPEC_BCN_AREA_ON BIT(5)
-#define BIT_P2P1_SPEC_CTWIN_EARLY_DISTX BIT(4)
-#define BIT_P2P1_SPEC_NOA1_OFF_PERIOD BIT(3)
-#define BIT_P2P1_SPEC_FORCE_DOZE1 BIT(2)
-#define BIT_P2P1_SPEC_NOA0_OFF_PERIOD BIT(1)
-#define BIT_P2P1_SPEC_FORCE_DOZE0 BIT(0)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-/* 2 REG_P2PPS1_STATE (Offset 0x057D) */
+/* 2 REG_MISC_CTRL (Offset 0x0577) */
-#define BIT_P2P1_POWER_STATE BIT(7)
-#define BIT_P2P1_CTWINDOW_ON BIT(6)
-#define BIT_P2P1_BEACON_AREA_ON BIT(5)
-#define BIT_P2P1_CTWIN_EARLY_DISTX BIT(4)
-#define BIT_P2P1_NOA1_OFF_PERIOD BIT(3)
-#define BIT_P2P1_FORCE_DOZE1 BIT(2)
-#define BIT_P2P1_NOA0_OFF_PERIOD BIT(1)
-#define BIT_P2P1_FORCE_DOZE0 BIT(0)
+#define BIT_DIS_MARK_TSF_US BIT(7)
-/* 2 REG_P2PPS2_SPEC_STATE (Offset 0x057E) */
+#endif
-#define BIT_P2P2_SPEC_POWER_STATE BIT(7)
-#define BIT_P2P2_SPEC_CTWINDOW_ON BIT(6)
-#define BIT_P2P2_SPEC_BCN_AREA_ON BIT(5)
-#define BIT_P2P2_SPEC_CTWIN_EARLY_DISTX BIT(4)
-#define BIT_P2P2_SPEC_NOA1_OFF_PERIOD BIT(3)
-#define BIT_P2P2_SPEC_FORCE_DOZE1 BIT(2)
-#define BIT_P2P2_SPEC_NOA0_OFF_PERIOD BIT(1)
-#define BIT_P2P2_SPEC_FORCE_DOZE0 BIT(0)
+#if (HALMAC_8822C_SUPPORT)
-/* 2 REG_P2PPS2_STATE (Offset 0x057F) */
+/* 2 REG_MISC_CTRL (Offset 0x0577) */
-#define BIT_P2P2_POWER_STATE BIT(7)
-#define BIT_P2P2_CTWINDOW_ON BIT(6)
-#define BIT_P2P2_BEACON_AREA_ON BIT(5)
-#define BIT_P2P2_CTWIN_EARLY_DISTX BIT(4)
-#define BIT_P2P2_NOA1_OFF_PERIOD BIT(3)
-#define BIT_P2P2_FORCE_DOZE1 BIT(2)
-#define BIT_P2P2_NOA0_OFF_PERIOD BIT(1)
-#define BIT_P2P2_FORCE_DOZE0 BIT(0)
+#define BIT_DIS_MARK_TSF_US_V2 BIT(7)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT)
+/* 2 REG_MISC_CTRL (Offset 0x0577) */
+#define BIT_EN_TSFAUTO_SYNC BIT(6)
-/* 2 REG_PS_TIMER (Offset 0x0580) */
+#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_PSTIMER_INT 5
-#define BIT_MASK_PSTIMER_INT 0x7ffffff
-#define BIT_PSTIMER_INT(x) (((x) & BIT_MASK_PSTIMER_INT) << BIT_SHIFT_PSTIMER_INT)
-#define BIT_GET_PSTIMER_INT(x) (((x) >> BIT_SHIFT_PSTIMER_INT) & BIT_MASK_PSTIMER_INT)
+/* 2 REG_MISC_CTRL (Offset 0x0577) */
+#define BIT_AUTO_SYNC_BY_TBTT BIT(6)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_MISC_CTRL (Offset 0x0577) */
+#define BIT_DIS_TRX_CAL_BCN BIT(5)
+#define BIT_DIS_TX_CAL_TBTT BIT(4)
+#define BIT_EN_FREECNT BIT(3)
+#define BIT_BCN_AGGRESSION BIT(2)
-/* 2 REG_PS_TIMER0 (Offset 0x0580) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_PSTIMER0_INT 5
-#define BIT_MASK_PSTIMER0_INT 0x7ffffff
-#define BIT_PSTIMER0_INT(x) (((x) & BIT_MASK_PSTIMER0_INT) << BIT_SHIFT_PSTIMER0_INT)
-#define BIT_GET_PSTIMER0_INT(x) (((x) >> BIT_SHIFT_PSTIMER0_INT) & BIT_MASK_PSTIMER0_INT)
+/* 2 REG_MISC_CTRL (Offset 0x0577) */
+#define BIT_DIS_SECONDARY_CCA_80M BIT(2)
+#define BIT_DIS_SECONDARY_CCA_40M BIT(1)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8881A_SUPPORT)
+/* 2 REG_MISC_CTRL (Offset 0x0577) */
+#define BIT_SHIFT_DIS_SECONDARY_CCA 0
+#define BIT_MASK_DIS_SECONDARY_CCA 0x3
+#define BIT_DIS_SECONDARY_CCA(x) \
+ (((x) & BIT_MASK_DIS_SECONDARY_CCA) << BIT_SHIFT_DIS_SECONDARY_CCA)
+#define BITS_DIS_SECONDARY_CCA \
+ (BIT_MASK_DIS_SECONDARY_CCA << BIT_SHIFT_DIS_SECONDARY_CCA)
+#define BIT_CLEAR_DIS_SECONDARY_CCA(x) ((x) & (~BITS_DIS_SECONDARY_CCA))
+#define BIT_GET_DIS_SECONDARY_CCA(x) \
+ (((x) >> BIT_SHIFT_DIS_SECONDARY_CCA) & BIT_MASK_DIS_SECONDARY_CCA)
+#define BIT_SET_DIS_SECONDARY_CCA(x, v) \
+ (BIT_CLEAR_DIS_SECONDARY_CCA(x) | BIT_DIS_SECONDARY_CCA(v))
-/* 2 REG_PS_TIMER (Offset 0x0580) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_PSTIMER_INT_V1 5
-#define BIT_MASK_PSTIMER_INT_V1 0x7ffffff
-#define BIT_PSTIMER_INT_V1(x) (((x) & BIT_MASK_PSTIMER_INT_V1) << BIT_SHIFT_PSTIMER_INT_V1)
-#define BIT_GET_PSTIMER_INT_V1(x) (((x) >> BIT_SHIFT_PSTIMER_INT_V1) & BIT_MASK_PSTIMER_INT_V1)
+/* 2 REG_MISC_CTRL (Offset 0x0577) */
+#define BIT_DIS_SECONDARY_CCA_20M BIT(0)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */
+#define BIT_CLI1_DIS_RX_BSSID_FIT BIT(6)
+#define BIT_CLI1_DIS_TSF_UDT BIT(4)
+#define BIT_CLI1_EN_BCN_FUNCTION BIT(3)
-/* 2 REG_TIMER0 (Offset 0x0584) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_TIMER0_INT 5
-#define BIT_MASK_TIMER0_INT 0x7ffffff
-#define BIT_TIMER0_INT(x) (((x) & BIT_MASK_TIMER0_INT) << BIT_SHIFT_TIMER0_INT)
-#define BIT_GET_TIMER0_INT(x) (((x) >> BIT_SHIFT_TIMER0_INT) & BIT_MASK_TIMER0_INT)
+/* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */
+#define BIT_CLI1_EN_RXBCN_RPT BIT(2)
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */
+#define BIT_CLI1_EN_BCN_RPT BIT(2)
-/* 2 REG_PS_TIMER1 (Offset 0x0584) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_PSTIMER1_INT 5
-#define BIT_MASK_PSTIMER1_INT 0x7ffffff
-#define BIT_PSTIMER1_INT(x) (((x) & BIT_MASK_PSTIMER1_INT) << BIT_SHIFT_PSTIMER1_INT)
-#define BIT_GET_PSTIMER1_INT(x) (((x) >> BIT_SHIFT_PSTIMER1_INT) & BIT_MASK_PSTIMER1_INT)
+/* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */
+#define BIT_CLI1_ENP2P_CTWINDOW BIT(1)
+#define BIT_CLI1_ENP2P_BCNQ_AREA BIT(0)
-#endif
+/* 2 REG_BCN_CTRL_CLINT2 (Offset 0x0579) */
+#define BIT_CLI2_DIS_RX_BSSID_FIT BIT(6)
+#define BIT_CLI2_DIS_TSF_UDT BIT(4)
+#define BIT_CLI2_EN_BCN_FUNCTION BIT(3)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_TIMER1 (Offset 0x0588) */
+/* 2 REG_BCN_CTRL_CLINT2 (Offset 0x0579) */
+#define BIT_CLI2_EN_RXBCN_RPT BIT(2)
-#define BIT_SHIFT_TIMER1_INT 5
-#define BIT_MASK_TIMER1_INT 0x7ffffff
-#define BIT_TIMER1_INT(x) (((x) & BIT_MASK_TIMER1_INT) << BIT_SHIFT_TIMER1_INT)
-#define BIT_GET_TIMER1_INT(x) (((x) >> BIT_SHIFT_TIMER1_INT) & BIT_MASK_TIMER1_INT)
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#endif
+/* 2 REG_BCN_CTRL_CLINT2 (Offset 0x0579) */
+#define BIT_CLI2_EN_BCN_RPT BIT(2)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-/* 2 REG_PS_TIMER2 (Offset 0x0588) */
+/* 2 REG_BCN_CTRL_CLINT2 (Offset 0x0579) */
+#define BIT_CLI2_ENP2P_CTWINDOW BIT(1)
+#define BIT_CLI2_ENP2P_BCNQ_AREA BIT(0)
-#define BIT_SHIFT_PSTIMER2_INT 5
-#define BIT_MASK_PSTIMER2_INT 0x7ffffff
-#define BIT_PSTIMER2_INT(x) (((x) & BIT_MASK_PSTIMER2_INT) << BIT_SHIFT_PSTIMER2_INT)
-#define BIT_GET_PSTIMER2_INT(x) (((x) >> BIT_SHIFT_PSTIMER2_INT) & BIT_MASK_PSTIMER2_INT)
+/* 2 REG_BCN_CTRL_CLINT3 (Offset 0x057A) */
+#define BIT_CLI3_DIS_RX_BSSID_FIT BIT(6)
+#define BIT_CLI3_DIS_TSF_UDT BIT(4)
+#define BIT_CLI3_EN_BCN_FUNCTION BIT(3)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_BCN_CTRL_CLINT3 (Offset 0x057A) */
+#define BIT_CLI3_EN_RXBCN_RPT BIT(2)
-/* 2 REG_TBTT_CTN_AREA (Offset 0x058C) */
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define BIT_SHIFT_TBTT_CTN_AREA 0
-#define BIT_MASK_TBTT_CTN_AREA 0xff
-#define BIT_TBTT_CTN_AREA(x) (((x) & BIT_MASK_TBTT_CTN_AREA) << BIT_SHIFT_TBTT_CTN_AREA)
-#define BIT_GET_TBTT_CTN_AREA(x) (((x) >> BIT_SHIFT_TBTT_CTN_AREA) & BIT_MASK_TBTT_CTN_AREA)
+/* 2 REG_BCN_CTRL_CLINT3 (Offset 0x057A) */
+#define BIT_CLI3_EN_BCN_RPT BIT(2)
-/* 2 REG_FORCE_BCN_IFS (Offset 0x058E) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_FORCE_BCN_IFS 0
-#define BIT_MASK_FORCE_BCN_IFS 0xff
-#define BIT_FORCE_BCN_IFS(x) (((x) & BIT_MASK_FORCE_BCN_IFS) << BIT_SHIFT_FORCE_BCN_IFS)
-#define BIT_GET_FORCE_BCN_IFS(x) (((x) >> BIT_SHIFT_FORCE_BCN_IFS) & BIT_MASK_FORCE_BCN_IFS)
+/* 2 REG_BCN_CTRL_CLINT3 (Offset 0x057A) */
+#define BIT_CLI3_ENP2P_CTWINDOW BIT(1)
+#define BIT_CLI3_ENP2P_BCNQ_AREA BIT(0)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
+/* 2 REG_EXTEND_CTRL (Offset 0x057B) */
-/* 2 REG_TXOP_MIN (Offset 0x0590) */
+#define BIT_EN_TSFBIT32_RST_P2P2 BIT(5)
+#define BIT_EN_TSFBIT32_RST_P2P1 BIT(4)
-#define BIT_NAV_BLK_HGQ BIT(15)
-#define BIT_NAV_BLK_MGQ BIT(14)
+#define BIT_SHIFT_PORT_SEL 0
+#define BIT_MASK_PORT_SEL 0x7
+#define BIT_PORT_SEL(x) (((x) & BIT_MASK_PORT_SEL) << BIT_SHIFT_PORT_SEL)
+#define BITS_PORT_SEL (BIT_MASK_PORT_SEL << BIT_SHIFT_PORT_SEL)
+#define BIT_CLEAR_PORT_SEL(x) ((x) & (~BITS_PORT_SEL))
+#define BIT_GET_PORT_SEL(x) (((x) >> BIT_SHIFT_PORT_SEL) & BIT_MASK_PORT_SEL)
+#define BIT_SET_PORT_SEL(x, v) (BIT_CLEAR_PORT_SEL(x) | BIT_PORT_SEL(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_P2PPS1_SPEC_STATE (Offset 0x057C) */
+#define BIT_P2P1_SPEC_POWER_STATE BIT(7)
-/* 2 REG_TXOP_MIN (Offset 0x0590) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_TXOP_MIN 0
-#define BIT_MASK_TXOP_MIN 0x3fff
-#define BIT_TXOP_MIN(x) (((x) & BIT_MASK_TXOP_MIN) << BIT_SHIFT_TXOP_MIN)
-#define BIT_GET_TXOP_MIN(x) (((x) >> BIT_SHIFT_TXOP_MIN) & BIT_MASK_TXOP_MIN)
+/* 2 REG_P2PPS1_SPEC_STATE (Offset 0x057C) */
+#define BIT_P2P1_SPEC_CTWINDOW_ON BIT(6)
-/* 2 REG_PRE_BKF_TIME (Offset 0x0592) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_PRE_BKF_TIME 0
-#define BIT_MASK_PRE_BKF_TIME 0xff
-#define BIT_PRE_BKF_TIME(x) (((x) & BIT_MASK_PRE_BKF_TIME) << BIT_SHIFT_PRE_BKF_TIME)
-#define BIT_GET_PRE_BKF_TIME(x) (((x) >> BIT_SHIFT_PRE_BKF_TIME) & BIT_MASK_PRE_BKF_TIME)
+/* 2 REG_P2PPS1_SPEC_STATE (Offset 0x057C) */
+#define BIT_P2P1_SPEC_BCN_AREA_ON BIT(5)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT)
+/* 2 REG_P2PPS1_SPEC_STATE (Offset 0x057C) */
+#define BIT_P2P1_SPEC_CTWIN_EARLY_DISTX BIT(4)
+#define BIT_P2P1_SPEC_NOA1_OFF_PERIOD BIT(3)
+#define BIT_P2P1_SPEC_FORCE_DOZE1 BIT(2)
+#define BIT_P2P1_SPEC_NOA0_OFF_PERIOD BIT(1)
+#define BIT_P2P1_SPEC_FORCE_DOZE0 BIT(0)
-/* 2 REG_CROSS_TXOP_CTRL (Offset 0x0593) */
+/* 2 REG_P2PPS1_STATE (Offset 0x057D) */
-#define BIT_TXFAIL_BREACK_TXOP_EN BIT(3)
+#define BIT_P2P1_POWER_STATE BIT(7)
+#define BIT_P2P1_CTWINDOW_ON BIT(6)
+#define BIT_P2P1_BEACON_AREA_ON BIT(5)
+#define BIT_P2P1_CTWIN_EARLY_DISTX BIT(4)
+#define BIT_P2P1_NOA1_OFF_PERIOD BIT(3)
+#define BIT_P2P1_FORCE_DOZE1 BIT(2)
+#define BIT_P2P1_NOA0_OFF_PERIOD BIT(1)
+#define BIT_P2P1_FORCE_DOZE0 BIT(0)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-
-/* 2 REG_CROSS_TXOP_CTRL (Offset 0x0593) */
+/* 2 REG_P2PPS2_SPEC_STATE (Offset 0x057E) */
-#define BIT_DTIM_BYPASS BIT(2)
-#define BIT_RTS_NAV_TXOP BIT(1)
-#define BIT_NOT_CROSS_TXOP BIT(0)
+#define BIT_P2P2_SPEC_POWER_STATE BIT(7)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_P2PPS2_SPEC_STATE (Offset 0x057E) */
+#define BIT_P2P2_SPEC_CTWINDOW_ON BIT(6)
-/* 2 REG_TBTT_INT_SHIFT_CLI0 (Offset 0x0594) */
+#endif
-#define BIT_TBTT_INT_SHIFT_DIR_CLI0 BIT(7)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_TBTT_INT_SHIFT_CLI0 0
-#define BIT_MASK_TBTT_INT_SHIFT_CLI0 0x7f
-#define BIT_TBTT_INT_SHIFT_CLI0(x) (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI0) << BIT_SHIFT_TBTT_INT_SHIFT_CLI0)
-#define BIT_GET_TBTT_INT_SHIFT_CLI0(x) (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI0) & BIT_MASK_TBTT_INT_SHIFT_CLI0)
+/* 2 REG_P2PPS2_SPEC_STATE (Offset 0x057E) */
+#define BIT_P2P2_SPEC_BCN_AREA_ON BIT(5)
-/* 2 REG_TBTT_INT_SHIFT_CLI1 (Offset 0x0595) */
+#endif
-#define BIT_TBTT_INT_SHIFT_DIR_CLI1 BIT(7)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_TBTT_INT_SHIFT_CLI1 0
-#define BIT_MASK_TBTT_INT_SHIFT_CLI1 0x7f
-#define BIT_TBTT_INT_SHIFT_CLI1(x) (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI1) << BIT_SHIFT_TBTT_INT_SHIFT_CLI1)
-#define BIT_GET_TBTT_INT_SHIFT_CLI1(x) (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI1) & BIT_MASK_TBTT_INT_SHIFT_CLI1)
+/* 2 REG_P2PPS2_SPEC_STATE (Offset 0x057E) */
+#define BIT_P2P2_SPEC_CTWIN_EARLY_DISTX BIT(4)
+#define BIT_P2P2_SPEC_NOA1_OFF_PERIOD BIT(3)
+#define BIT_P2P2_SPEC_FORCE_DOZE1 BIT(2)
+#define BIT_P2P2_SPEC_NOA0_OFF_PERIOD BIT(1)
+#define BIT_P2P2_SPEC_FORCE_DOZE0 BIT(0)
-/* 2 REG_TBTT_INT_SHIFT_CLI2 (Offset 0x0596) */
+/* 2 REG_P2PPS2_STATE (Offset 0x057F) */
-#define BIT_TBTT_INT_SHIFT_DIR_CLI2 BIT(7)
+#define BIT_P2P2_POWER_STATE BIT(7)
+#define BIT_P2P2_CTWINDOW_ON BIT(6)
+#define BIT_P2P2_BEACON_AREA_ON BIT(5)
+#define BIT_P2P2_CTWIN_EARLY_DISTX BIT(4)
+#define BIT_P2P2_NOA1_OFF_PERIOD BIT(3)
+#define BIT_P2P2_FORCE_DOZE1 BIT(2)
+#define BIT_P2P2_NOA0_OFF_PERIOD BIT(1)
+#define BIT_P2P2_FORCE_DOZE0 BIT(0)
-#define BIT_SHIFT_TBTT_INT_SHIFT_CLI2 0
-#define BIT_MASK_TBTT_INT_SHIFT_CLI2 0x7f
-#define BIT_TBTT_INT_SHIFT_CLI2(x) (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI2) << BIT_SHIFT_TBTT_INT_SHIFT_CLI2)
-#define BIT_GET_TBTT_INT_SHIFT_CLI2(x) (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI2) & BIT_MASK_TBTT_INT_SHIFT_CLI2)
+#define BIT_SHIFT_EARLY_128US 0
+#define BIT_MASK_EARLY_128US 0x7
+#define BIT_EARLY_128US(x) \
+ (((x) & BIT_MASK_EARLY_128US) << BIT_SHIFT_EARLY_128US)
+#define BITS_EARLY_128US (BIT_MASK_EARLY_128US << BIT_SHIFT_EARLY_128US)
+#define BIT_CLEAR_EARLY_128US(x) ((x) & (~BITS_EARLY_128US))
+#define BIT_GET_EARLY_128US(x) \
+ (((x) >> BIT_SHIFT_EARLY_128US) & BIT_MASK_EARLY_128US)
+#define BIT_SET_EARLY_128US(x, v) \
+ (BIT_CLEAR_EARLY_128US(x) | BIT_EARLY_128US(v))
+#endif
-/* 2 REG_TBTT_INT_SHIFT_CLI3 (Offset 0x0597) */
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_TBTT_INT_SHIFT_DIR_CLI3 BIT(7)
+/* 2 REG_PS_TIMER (Offset 0x0580) */
+
+#define BIT_SHIFT_PSTIMER 5
+#define BIT_MASK_PSTIMER 0x7ffffff
+#define BIT_PSTIMER(x) (((x) & BIT_MASK_PSTIMER) << BIT_SHIFT_PSTIMER)
+#define BITS_PSTIMER (BIT_MASK_PSTIMER << BIT_SHIFT_PSTIMER)
+#define BIT_CLEAR_PSTIMER(x) ((x) & (~BITS_PSTIMER))
+#define BIT_GET_PSTIMER(x) (((x) >> BIT_SHIFT_PSTIMER) & BIT_MASK_PSTIMER)
+#define BIT_SET_PSTIMER(x, v) (BIT_CLEAR_PSTIMER(x) | BIT_PSTIMER(v))
-#define BIT_SHIFT_TBTT_INT_SHIFT_CLI3 0
-#define BIT_MASK_TBTT_INT_SHIFT_CLI3 0x7f
-#define BIT_TBTT_INT_SHIFT_CLI3(x) (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI3) << BIT_SHIFT_TBTT_INT_SHIFT_CLI3)
-#define BIT_GET_TBTT_INT_SHIFT_CLI3(x) (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI3) & BIT_MASK_TBTT_INT_SHIFT_CLI3)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-/* 2 REG_TBTT_INT_SHIFT_ENABLE (Offset 0x0598) */
+/* 2 REG_PS_TIMER0 (Offset 0x0580) */
-#define BIT_EN_TBTT_RTY BIT(1)
-#define BIT_TBTT_INT_SHIFT_ENABLE BIT(0)
+#define BIT_SHIFT_PSTIMER0_INT 5
+#define BIT_MASK_PSTIMER0_INT 0x7ffffff
+#define BIT_PSTIMER0_INT(x) \
+ (((x) & BIT_MASK_PSTIMER0_INT) << BIT_SHIFT_PSTIMER0_INT)
+#define BITS_PSTIMER0_INT (BIT_MASK_PSTIMER0_INT << BIT_SHIFT_PSTIMER0_INT)
+#define BIT_CLEAR_PSTIMER0_INT(x) ((x) & (~BITS_PSTIMER0_INT))
+#define BIT_GET_PSTIMER0_INT(x) \
+ (((x) >> BIT_SHIFT_PSTIMER0_INT) & BIT_MASK_PSTIMER0_INT)
+#define BIT_SET_PSTIMER0_INT(x, v) \
+ (BIT_CLEAR_PSTIMER0_INT(x) | BIT_PSTIMER0_INT(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_TIMER0 (Offset 0x0584) */
+#define BIT_SHIFT_TIMER0_INT 5
+#define BIT_MASK_TIMER0_INT 0x7ffffff
+#define BIT_TIMER0_INT(x) (((x) & BIT_MASK_TIMER0_INT) << BIT_SHIFT_TIMER0_INT)
+#define BITS_TIMER0_INT (BIT_MASK_TIMER0_INT << BIT_SHIFT_TIMER0_INT)
+#define BIT_CLEAR_TIMER0_INT(x) ((x) & (~BITS_TIMER0_INT))
+#define BIT_GET_TIMER0_INT(x) \
+ (((x) >> BIT_SHIFT_TIMER0_INT) & BIT_MASK_TIMER0_INT)
+#define BIT_SET_TIMER0_INT(x, v) (BIT_CLEAR_TIMER0_INT(x) | BIT_TIMER0_INT(v))
-/* 2 REG_ATIMWND2 (Offset 0x05A0) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_ATIMWND2 0
-#define BIT_MASK_ATIMWND2 0xff
-#define BIT_ATIMWND2(x) (((x) & BIT_MASK_ATIMWND2) << BIT_SHIFT_ATIMWND2)
-#define BIT_GET_ATIMWND2(x) (((x) >> BIT_SHIFT_ATIMWND2) & BIT_MASK_ATIMWND2)
+/* 2 REG_PS_TIMER1 (Offset 0x0584) */
+#define BIT_SHIFT_PSTIMER1_INT 5
+#define BIT_MASK_PSTIMER1_INT 0x7ffffff
+#define BIT_PSTIMER1_INT(x) \
+ (((x) & BIT_MASK_PSTIMER1_INT) << BIT_SHIFT_PSTIMER1_INT)
+#define BITS_PSTIMER1_INT (BIT_MASK_PSTIMER1_INT << BIT_SHIFT_PSTIMER1_INT)
+#define BIT_CLEAR_PSTIMER1_INT(x) ((x) & (~BITS_PSTIMER1_INT))
+#define BIT_GET_PSTIMER1_INT(x) \
+ (((x) >> BIT_SHIFT_PSTIMER1_INT) & BIT_MASK_PSTIMER1_INT)
+#define BIT_SET_PSTIMER1_INT(x, v) \
+ (BIT_CLEAR_PSTIMER1_INT(x) | BIT_PSTIMER1_INT(v))
-/* 2 REG_ATIMWND3 (Offset 0x05A1) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_ATIMWND3 0
-#define BIT_MASK_ATIMWND3 0xff
-#define BIT_ATIMWND3(x) (((x) & BIT_MASK_ATIMWND3) << BIT_SHIFT_ATIMWND3)
-#define BIT_GET_ATIMWND3(x) (((x) >> BIT_SHIFT_ATIMWND3) & BIT_MASK_ATIMWND3)
+/* 2 REG_TIMER1 (Offset 0x0588) */
+#define BIT_SHIFT_TIMER1_INT 5
+#define BIT_MASK_TIMER1_INT 0x7ffffff
+#define BIT_TIMER1_INT(x) (((x) & BIT_MASK_TIMER1_INT) << BIT_SHIFT_TIMER1_INT)
+#define BITS_TIMER1_INT (BIT_MASK_TIMER1_INT << BIT_SHIFT_TIMER1_INT)
+#define BIT_CLEAR_TIMER1_INT(x) ((x) & (~BITS_TIMER1_INT))
+#define BIT_GET_TIMER1_INT(x) \
+ (((x) >> BIT_SHIFT_TIMER1_INT) & BIT_MASK_TIMER1_INT)
+#define BIT_SET_TIMER1_INT(x, v) (BIT_CLEAR_TIMER1_INT(x) | BIT_TIMER1_INT(v))
-/* 2 REG_ATIMWND4 (Offset 0x05A2) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_ATIMWND4 0
-#define BIT_MASK_ATIMWND4 0xff
-#define BIT_ATIMWND4(x) (((x) & BIT_MASK_ATIMWND4) << BIT_SHIFT_ATIMWND4)
-#define BIT_GET_ATIMWND4(x) (((x) >> BIT_SHIFT_ATIMWND4) & BIT_MASK_ATIMWND4)
+/* 2 REG_PS_TIMER2 (Offset 0x0588) */
+#define BIT_SHIFT_PSTIMER2_INT 5
+#define BIT_MASK_PSTIMER2_INT 0x7ffffff
+#define BIT_PSTIMER2_INT(x) \
+ (((x) & BIT_MASK_PSTIMER2_INT) << BIT_SHIFT_PSTIMER2_INT)
+#define BITS_PSTIMER2_INT (BIT_MASK_PSTIMER2_INT << BIT_SHIFT_PSTIMER2_INT)
+#define BIT_CLEAR_PSTIMER2_INT(x) ((x) & (~BITS_PSTIMER2_INT))
+#define BIT_GET_PSTIMER2_INT(x) \
+ (((x) >> BIT_SHIFT_PSTIMER2_INT) & BIT_MASK_PSTIMER2_INT)
+#define BIT_SET_PSTIMER2_INT(x, v) \
+ (BIT_CLEAR_PSTIMER2_INT(x) | BIT_PSTIMER2_INT(v))
-/* 2 REG_ATIMWND5 (Offset 0x05A3) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_ATIMWND5 0
-#define BIT_MASK_ATIMWND5 0xff
-#define BIT_ATIMWND5(x) (((x) & BIT_MASK_ATIMWND5) << BIT_SHIFT_ATIMWND5)
-#define BIT_GET_ATIMWND5(x) (((x) >> BIT_SHIFT_ATIMWND5) & BIT_MASK_ATIMWND5)
+/* 2 REG_TBTT_CTN_AREA (Offset 0x058C) */
+#define BIT_SHIFT_TBTT_CTN_AREA 0
+#define BIT_MASK_TBTT_CTN_AREA 0xff
+#define BIT_TBTT_CTN_AREA(x) \
+ (((x) & BIT_MASK_TBTT_CTN_AREA) << BIT_SHIFT_TBTT_CTN_AREA)
+#define BITS_TBTT_CTN_AREA (BIT_MASK_TBTT_CTN_AREA << BIT_SHIFT_TBTT_CTN_AREA)
+#define BIT_CLEAR_TBTT_CTN_AREA(x) ((x) & (~BITS_TBTT_CTN_AREA))
+#define BIT_GET_TBTT_CTN_AREA(x) \
+ (((x) >> BIT_SHIFT_TBTT_CTN_AREA) & BIT_MASK_TBTT_CTN_AREA)
+#define BIT_SET_TBTT_CTN_AREA(x, v) \
+ (BIT_CLEAR_TBTT_CTN_AREA(x) | BIT_TBTT_CTN_AREA(v))
-/* 2 REG_ATIMWND6 (Offset 0x05A4) */
+/* 2 REG_FORCE_BCN_IFS (Offset 0x058E) */
+#define BIT_SHIFT_FORCE_BCN_IFS 0
+#define BIT_MASK_FORCE_BCN_IFS 0xff
+#define BIT_FORCE_BCN_IFS(x) \
+ (((x) & BIT_MASK_FORCE_BCN_IFS) << BIT_SHIFT_FORCE_BCN_IFS)
+#define BITS_FORCE_BCN_IFS (BIT_MASK_FORCE_BCN_IFS << BIT_SHIFT_FORCE_BCN_IFS)
+#define BIT_CLEAR_FORCE_BCN_IFS(x) ((x) & (~BITS_FORCE_BCN_IFS))
+#define BIT_GET_FORCE_BCN_IFS(x) \
+ (((x) >> BIT_SHIFT_FORCE_BCN_IFS) & BIT_MASK_FORCE_BCN_IFS)
+#define BIT_SET_FORCE_BCN_IFS(x, v) \
+ (BIT_CLEAR_FORCE_BCN_IFS(x) | BIT_FORCE_BCN_IFS(v))
-#define BIT_SHIFT_ATIMWND6 0
-#define BIT_MASK_ATIMWND6 0xff
-#define BIT_ATIMWND6(x) (((x) & BIT_MASK_ATIMWND6) << BIT_SHIFT_ATIMWND6)
-#define BIT_GET_ATIMWND6(x) (((x) >> BIT_SHIFT_ATIMWND6) & BIT_MASK_ATIMWND6)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-/* 2 REG_ATIMWND7 (Offset 0x05A5) */
+/* 2 REG_TXOP_MIN (Offset 0x0590) */
+#define BIT_NAV_BLK_HGQ BIT(15)
-#define BIT_SHIFT_ATIMWND7 0
-#define BIT_MASK_ATIMWND7 0xff
-#define BIT_ATIMWND7(x) (((x) & BIT_MASK_ATIMWND7) << BIT_SHIFT_ATIMWND7)
-#define BIT_GET_ATIMWND7(x) (((x) >> BIT_SHIFT_ATIMWND7) & BIT_MASK_ATIMWND7)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_ATIMUGT (Offset 0x05A6) */
+/* 2 REG_TXOP_MIN (Offset 0x0590) */
+#define BIT_HIQ_NAV_BREAK_EN BIT(15)
-#define BIT_SHIFT_ATIM_URGENT 0
-#define BIT_MASK_ATIM_URGENT 0xff
-#define BIT_ATIM_URGENT(x) (((x) & BIT_MASK_ATIM_URGENT) << BIT_SHIFT_ATIM_URGENT)
-#define BIT_GET_ATIM_URGENT(x) (((x) >> BIT_SHIFT_ATIM_URGENT) & BIT_MASK_ATIM_URGENT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-/* 2 REG_HIQ_NO_LMT_EN (Offset 0x05A7) */
+/* 2 REG_TXOP_MIN (Offset 0x0590) */
-#define BIT_HIQ_NO_LMT_EN_VAP7 BIT(7)
-#define BIT_HIQ_NO_LMT_EN_VAP6 BIT(6)
-#define BIT_HIQ_NO_LMT_EN_VAP5 BIT(5)
-#define BIT_HIQ_NO_LMT_EN_VAP4 BIT(4)
-#define BIT_HIQ_NO_LMT_EN_VAP3 BIT(3)
-#define BIT_HIQ_NO_LMT_EN_VAP2 BIT(2)
-#define BIT_HIQ_NO_LMT_EN_VAP1 BIT(1)
-#define BIT_HIQ_NO_LMT_EN_ROOT BIT(0)
+#define BIT_NAV_BLK_MGQ BIT(14)
-/* 2 REG_DTIM_COUNTER_ROOT (Offset 0x05A8) */
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_DTIM_COUNT_ROOT 0
-#define BIT_MASK_DTIM_COUNT_ROOT 0xff
-#define BIT_DTIM_COUNT_ROOT(x) (((x) & BIT_MASK_DTIM_COUNT_ROOT) << BIT_SHIFT_DTIM_COUNT_ROOT)
-#define BIT_GET_DTIM_COUNT_ROOT(x) (((x) >> BIT_SHIFT_DTIM_COUNT_ROOT) & BIT_MASK_DTIM_COUNT_ROOT)
+/* 2 REG_TXOP_MIN (Offset 0x0590) */
+#define BIT_MGQ_NAV_BREAK_EN BIT(14)
-/* 2 REG_DTIM_COUNTER_VAP1 (Offset 0x05A9) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_DTIM_COUNT_VAP1 0
-#define BIT_MASK_DTIM_COUNT_VAP1 0xff
-#define BIT_DTIM_COUNT_VAP1(x) (((x) & BIT_MASK_DTIM_COUNT_VAP1) << BIT_SHIFT_DTIM_COUNT_VAP1)
-#define BIT_GET_DTIM_COUNT_VAP1(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP1) & BIT_MASK_DTIM_COUNT_VAP1)
+/* 2 REG_TXOP_MIN (Offset 0x0590) */
+#define BIT_SHIFT_TXOP_MIN 0
+#define BIT_MASK_TXOP_MIN 0x3fff
+#define BIT_TXOP_MIN(x) (((x) & BIT_MASK_TXOP_MIN) << BIT_SHIFT_TXOP_MIN)
+#define BITS_TXOP_MIN (BIT_MASK_TXOP_MIN << BIT_SHIFT_TXOP_MIN)
+#define BIT_CLEAR_TXOP_MIN(x) ((x) & (~BITS_TXOP_MIN))
+#define BIT_GET_TXOP_MIN(x) (((x) >> BIT_SHIFT_TXOP_MIN) & BIT_MASK_TXOP_MIN)
+#define BIT_SET_TXOP_MIN(x, v) (BIT_CLEAR_TXOP_MIN(x) | BIT_TXOP_MIN(v))
-/* 2 REG_DTIM_COUNTER_VAP2 (Offset 0x05AA) */
+/* 2 REG_PRE_BKF_TIME (Offset 0x0592) */
+#define BIT_SHIFT_PRE_BKF_TIME 0
+#define BIT_MASK_PRE_BKF_TIME 0xff
+#define BIT_PRE_BKF_TIME(x) \
+ (((x) & BIT_MASK_PRE_BKF_TIME) << BIT_SHIFT_PRE_BKF_TIME)
+#define BITS_PRE_BKF_TIME (BIT_MASK_PRE_BKF_TIME << BIT_SHIFT_PRE_BKF_TIME)
+#define BIT_CLEAR_PRE_BKF_TIME(x) ((x) & (~BITS_PRE_BKF_TIME))
+#define BIT_GET_PRE_BKF_TIME(x) \
+ (((x) >> BIT_SHIFT_PRE_BKF_TIME) & BIT_MASK_PRE_BKF_TIME)
+#define BIT_SET_PRE_BKF_TIME(x, v) \
+ (BIT_CLEAR_PRE_BKF_TIME(x) | BIT_PRE_BKF_TIME(v))
-#define BIT_SHIFT_DTIM_COUNT_VAP2 0
-#define BIT_MASK_DTIM_COUNT_VAP2 0xff
-#define BIT_DTIM_COUNT_VAP2(x) (((x) & BIT_MASK_DTIM_COUNT_VAP2) << BIT_SHIFT_DTIM_COUNT_VAP2)
-#define BIT_GET_DTIM_COUNT_VAP2(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP2) & BIT_MASK_DTIM_COUNT_VAP2)
+#endif
+#if (HALMAC_8198F_SUPPORT)
-/* 2 REG_DTIM_COUNTER_VAP3 (Offset 0x05AB) */
+/* 2 REG_CROSS_TXOP_CTRL (Offset 0x0593) */
+#define BIT_NOPKT_END_RTSMF BIT(7)
-#define BIT_SHIFT_DTIM_COUNT_VAP3 0
-#define BIT_MASK_DTIM_COUNT_VAP3 0xff
-#define BIT_DTIM_COUNT_VAP3(x) (((x) & BIT_MASK_DTIM_COUNT_VAP3) << BIT_SHIFT_DTIM_COUNT_VAP3)
-#define BIT_GET_DTIM_COUNT_VAP3(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP3) & BIT_MASK_DTIM_COUNT_VAP3)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_DTIM_COUNTER_VAP4 (Offset 0x05AC) */
+/* 2 REG_CROSS_TXOP_CTRL (Offset 0x0593) */
+#define BIT_TBTT_RETRY BIT(4)
-#define BIT_SHIFT_DTIM_COUNT_VAP4 0
-#define BIT_MASK_DTIM_COUNT_VAP4 0xff
-#define BIT_DTIM_COUNT_VAP4(x) (((x) & BIT_MASK_DTIM_COUNT_VAP4) << BIT_SHIFT_DTIM_COUNT_VAP4)
-#define BIT_GET_DTIM_COUNT_VAP4(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP4) & BIT_MASK_DTIM_COUNT_VAP4)
+#endif
+#if (HALMAC_8198F_SUPPORT)
-/* 2 REG_DTIM_COUNTER_VAP5 (Offset 0x05AD) */
+/* 2 REG_CROSS_TXOP_CTRL (Offset 0x0593) */
+#define BIT_TXOP_FAIL_BREAK BIT(3)
-#define BIT_SHIFT_DTIM_COUNT_VAP5 0
-#define BIT_MASK_DTIM_COUNT_VAP5 0xff
-#define BIT_DTIM_COUNT_VAP5(x) (((x) & BIT_MASK_DTIM_COUNT_VAP5) << BIT_SHIFT_DTIM_COUNT_VAP5)
-#define BIT_GET_DTIM_COUNT_VAP5(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP5) & BIT_MASK_DTIM_COUNT_VAP5)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_DTIM_COUNTER_VAP6 (Offset 0x05AE) */
+/* 2 REG_CROSS_TXOP_CTRL (Offset 0x0593) */
+#define BIT_TXFAIL_BREACK_TXOP_EN BIT(3)
-#define BIT_SHIFT_DTIM_COUNT_VAP6 0
-#define BIT_MASK_DTIM_COUNT_VAP6 0xff
-#define BIT_DTIM_COUNT_VAP6(x) (((x) & BIT_MASK_DTIM_COUNT_VAP6) << BIT_SHIFT_DTIM_COUNT_VAP6)
-#define BIT_GET_DTIM_COUNT_VAP6(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP6) & BIT_MASK_DTIM_COUNT_VAP6)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_DTIM_COUNTER_VAP7 (Offset 0x05AF) */
+/* 2 REG_CROSS_TXOP_CTRL (Offset 0x0593) */
+#define BIT_DTIM_BYPASS BIT(2)
-#define BIT_SHIFT_DTIM_COUNT_VAP7 0
-#define BIT_MASK_DTIM_COUNT_VAP7 0xff
-#define BIT_DTIM_COUNT_VAP7(x) (((x) & BIT_MASK_DTIM_COUNT_VAP7) << BIT_SHIFT_DTIM_COUNT_VAP7)
-#define BIT_GET_DTIM_COUNT_VAP7(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP7) & BIT_MASK_DTIM_COUNT_VAP7)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-/* 2 REG_DIS_ATIM (Offset 0x05B0) */
+/* 2 REG_CROSS_TXOP_CTRL (Offset 0x0593) */
-#define BIT_DIS_ATIM_VAP7 BIT(7)
-#define BIT_DIS_ATIM_VAP6 BIT(6)
-#define BIT_DIS_ATIM_VAP5 BIT(5)
-#define BIT_DIS_ATIM_VAP4 BIT(4)
-#define BIT_DIS_ATIM_VAP3 BIT(3)
-#define BIT_DIS_ATIM_VAP2 BIT(2)
-#define BIT_DIS_ATIM_VAP1 BIT(1)
-#define BIT_DIS_ATIM_ROOT BIT(0)
+#define BIT_RTS_NAV_TXOP BIT(1)
+#define BIT_NOT_CROSS_TXOP BIT(0)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_TBTT_INT_SHIFT_CLI0 (Offset 0x0594) */
+#define BIT_TBTT_INT_SHIFT_DIR_CLI0 BIT(7)
-/* 2 REG_EARLY_128US (Offset 0x05B1) */
+#define BIT_SHIFT_TBTT_INT_SHIFT_CLI0 0
+#define BIT_MASK_TBTT_INT_SHIFT_CLI0 0x7f
+#define BIT_TBTT_INT_SHIFT_CLI0(x) \
+ (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI0) << BIT_SHIFT_TBTT_INT_SHIFT_CLI0)
+#define BITS_TBTT_INT_SHIFT_CLI0 \
+ (BIT_MASK_TBTT_INT_SHIFT_CLI0 << BIT_SHIFT_TBTT_INT_SHIFT_CLI0)
+#define BIT_CLEAR_TBTT_INT_SHIFT_CLI0(x) ((x) & (~BITS_TBTT_INT_SHIFT_CLI0))
+#define BIT_GET_TBTT_INT_SHIFT_CLI0(x) \
+ (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI0) & BIT_MASK_TBTT_INT_SHIFT_CLI0)
+#define BIT_SET_TBTT_INT_SHIFT_CLI0(x, v) \
+ (BIT_CLEAR_TBTT_INT_SHIFT_CLI0(x) | BIT_TBTT_INT_SHIFT_CLI0(v))
+/* 2 REG_TBTT_INT_SHIFT_CLI1 (Offset 0x0595) */
-#define BIT_SHIFT_TSFT_SEL_TIMER1 3
-#define BIT_MASK_TSFT_SEL_TIMER1 0x7
-#define BIT_TSFT_SEL_TIMER1(x) (((x) & BIT_MASK_TSFT_SEL_TIMER1) << BIT_SHIFT_TSFT_SEL_TIMER1)
-#define BIT_GET_TSFT_SEL_TIMER1(x) (((x) >> BIT_SHIFT_TSFT_SEL_TIMER1) & BIT_MASK_TSFT_SEL_TIMER1)
+#define BIT_TBTT_INT_SHIFT_DIR_CLI1 BIT(7)
+#define BIT_SHIFT_TBTT_INT_SHIFT_CLI1 0
+#define BIT_MASK_TBTT_INT_SHIFT_CLI1 0x7f
+#define BIT_TBTT_INT_SHIFT_CLI1(x) \
+ (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI1) << BIT_SHIFT_TBTT_INT_SHIFT_CLI1)
+#define BITS_TBTT_INT_SHIFT_CLI1 \
+ (BIT_MASK_TBTT_INT_SHIFT_CLI1 << BIT_SHIFT_TBTT_INT_SHIFT_CLI1)
+#define BIT_CLEAR_TBTT_INT_SHIFT_CLI1(x) ((x) & (~BITS_TBTT_INT_SHIFT_CLI1))
+#define BIT_GET_TBTT_INT_SHIFT_CLI1(x) \
+ (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI1) & BIT_MASK_TBTT_INT_SHIFT_CLI1)
+#define BIT_SET_TBTT_INT_SHIFT_CLI1(x, v) \
+ (BIT_CLEAR_TBTT_INT_SHIFT_CLI1(x) | BIT_TBTT_INT_SHIFT_CLI1(v))
-#define BIT_SHIFT_EARLY_128US 0
-#define BIT_MASK_EARLY_128US 0x7
-#define BIT_EARLY_128US(x) (((x) & BIT_MASK_EARLY_128US) << BIT_SHIFT_EARLY_128US)
-#define BIT_GET_EARLY_128US(x) (((x) >> BIT_SHIFT_EARLY_128US) & BIT_MASK_EARLY_128US)
+/* 2 REG_TBTT_INT_SHIFT_CLI2 (Offset 0x0596) */
+#define BIT_TBTT_INT_SHIFT_DIR_CLI2 BIT(7)
-/* 2 REG_P2PPS1_CTRL (Offset 0x05B2) */
+#define BIT_SHIFT_TBTT_INT_SHIFT_CLI2 0
+#define BIT_MASK_TBTT_INT_SHIFT_CLI2 0x7f
+#define BIT_TBTT_INT_SHIFT_CLI2(x) \
+ (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI2) << BIT_SHIFT_TBTT_INT_SHIFT_CLI2)
+#define BITS_TBTT_INT_SHIFT_CLI2 \
+ (BIT_MASK_TBTT_INT_SHIFT_CLI2 << BIT_SHIFT_TBTT_INT_SHIFT_CLI2)
+#define BIT_CLEAR_TBTT_INT_SHIFT_CLI2(x) ((x) & (~BITS_TBTT_INT_SHIFT_CLI2))
+#define BIT_GET_TBTT_INT_SHIFT_CLI2(x) \
+ (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI2) & BIT_MASK_TBTT_INT_SHIFT_CLI2)
+#define BIT_SET_TBTT_INT_SHIFT_CLI2(x, v) \
+ (BIT_CLEAR_TBTT_INT_SHIFT_CLI2(x) | BIT_TBTT_INT_SHIFT_CLI2(v))
-#define BIT_P2P1_CTW_ALLSTASLEEP BIT(7)
-#define BIT_P2P1_OFF_DISTX_EN BIT(6)
-#define BIT_P2P1_PWR_MGT_EN BIT(5)
-#define BIT_P2P1_NOA1_EN BIT(2)
-#define BIT_P2P1_NOA0_EN BIT(1)
+/* 2 REG_TBTT_INT_SHIFT_CLI3 (Offset 0x0597) */
-/* 2 REG_P2PPS2_CTRL (Offset 0x05B3) */
+#define BIT_TBTT_INT_SHIFT_DIR_CLI3 BIT(7)
-#define BIT_P2P2_CTW_ALLSTASLEEP BIT(7)
-#define BIT_P2P2_OFF_DISTX_EN BIT(6)
-#define BIT_P2P2_PWR_MGT_EN BIT(5)
-#define BIT_P2P2_NOA1_EN BIT(2)
-#define BIT_P2P2_NOA0_EN BIT(1)
+#define BIT_SHIFT_TBTT_INT_SHIFT_CLI3 0
+#define BIT_MASK_TBTT_INT_SHIFT_CLI3 0x7f
+#define BIT_TBTT_INT_SHIFT_CLI3(x) \
+ (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI3) << BIT_SHIFT_TBTT_INT_SHIFT_CLI3)
+#define BITS_TBTT_INT_SHIFT_CLI3 \
+ (BIT_MASK_TBTT_INT_SHIFT_CLI3 << BIT_SHIFT_TBTT_INT_SHIFT_CLI3)
+#define BIT_CLEAR_TBTT_INT_SHIFT_CLI3(x) ((x) & (~BITS_TBTT_INT_SHIFT_CLI3))
+#define BIT_GET_TBTT_INT_SHIFT_CLI3(x) \
+ (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI3) & BIT_MASK_TBTT_INT_SHIFT_CLI3)
+#define BIT_SET_TBTT_INT_SHIFT_CLI3(x, v) \
+ (BIT_CLEAR_TBTT_INT_SHIFT_CLI3(x) | BIT_TBTT_INT_SHIFT_CLI3(v))
-/* 2 REG_TIMER0_SRC_SEL (Offset 0x05B4) */
+#endif
+#if (HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_SYNC_CLI_SEL 4
-#define BIT_MASK_SYNC_CLI_SEL 0x7
-#define BIT_SYNC_CLI_SEL(x) (((x) & BIT_MASK_SYNC_CLI_SEL) << BIT_SHIFT_SYNC_CLI_SEL)
-#define BIT_GET_SYNC_CLI_SEL(x) (((x) >> BIT_SHIFT_SYNC_CLI_SEL) & BIT_MASK_SYNC_CLI_SEL)
+/* 2 REG_RX_TBTT_SHIFT_V1 (Offset 0x0598) */
+#define BIT_RX_TBTT_SHIFT_RW_FLAG_V1 BIT(31)
-#define BIT_SHIFT_TSFT_SEL_TIMER0 0
-#define BIT_MASK_TSFT_SEL_TIMER0 0x7
-#define BIT_TSFT_SEL_TIMER0(x) (((x) & BIT_MASK_TSFT_SEL_TIMER0) << BIT_SHIFT_TSFT_SEL_TIMER0)
-#define BIT_GET_TSFT_SEL_TIMER0(x) (((x) >> BIT_SHIFT_TSFT_SEL_TIMER0) & BIT_MASK_TSFT_SEL_TIMER0)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-/* 2 REG_NOA_UNIT_SEL (Offset 0x05B5) */
+/* 2 REG_TBTT_INT_SHIFT_ENABLE (Offset 0x0598) */
+#define BIT_BCNERR_CNT_EN BIT(20)
-#define BIT_SHIFT_NOA_UNIT2_SEL 8
-#define BIT_MASK_NOA_UNIT2_SEL 0x7
-#define BIT_NOA_UNIT2_SEL(x) (((x) & BIT_MASK_NOA_UNIT2_SEL) << BIT_SHIFT_NOA_UNIT2_SEL)
-#define BIT_GET_NOA_UNIT2_SEL(x) (((x) >> BIT_SHIFT_NOA_UNIT2_SEL) & BIT_MASK_NOA_UNIT2_SEL)
+#endif
+#if (HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_NOA_UNIT1_SEL 4
-#define BIT_MASK_NOA_UNIT1_SEL 0x7
-#define BIT_NOA_UNIT1_SEL(x) (((x) & BIT_MASK_NOA_UNIT1_SEL) << BIT_SHIFT_NOA_UNIT1_SEL)
-#define BIT_GET_NOA_UNIT1_SEL(x) (((x) >> BIT_SHIFT_NOA_UNIT1_SEL) & BIT_MASK_NOA_UNIT1_SEL)
+/* 2 REG_RX_TBTT_SHIFT_V1 (Offset 0x0598) */
+#define BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1 16
+#define BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1 0xfff
+#define BIT_RX_TBTT_SHIFT_OFFSET_V1(x) \
+ (((x) & BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1) \
+ << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1)
+#define BITS_RX_TBTT_SHIFT_OFFSET_V1 \
+ (BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1 << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1)
+#define BIT_CLEAR_RX_TBTT_SHIFT_OFFSET_V1(x) \
+ ((x) & (~BITS_RX_TBTT_SHIFT_OFFSET_V1))
+#define BIT_GET_RX_TBTT_SHIFT_OFFSET_V1(x) \
+ (((x) >> BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1) & \
+ BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1)
+#define BIT_SET_RX_TBTT_SHIFT_OFFSET_V1(x, v) \
+ (BIT_CLEAR_RX_TBTT_SHIFT_OFFSET_V1(x) | BIT_RX_TBTT_SHIFT_OFFSET_V1(v))
-#define BIT_SHIFT_NOA_UNIT0_SEL 0
-#define BIT_MASK_NOA_UNIT0_SEL 0x7
-#define BIT_NOA_UNIT0_SEL(x) (((x) & BIT_MASK_NOA_UNIT0_SEL) << BIT_SHIFT_NOA_UNIT0_SEL)
-#define BIT_GET_NOA_UNIT0_SEL(x) (((x) >> BIT_SHIFT_NOA_UNIT0_SEL) & BIT_MASK_NOA_UNIT0_SEL)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-/* 2 REG_P2POFF_DIS_TXTIME (Offset 0x05B7) */
+/* 2 REG_TBTT_INT_SHIFT_ENABLE (Offset 0x0598) */
+
+#define BIT_CHANGE_POW_BCN_AREA BIT(9)
+#define BIT_SHIFT_TXPAUSE1 8
+#define BIT_MASK_TXPAUSE1 0xff
+#define BIT_TXPAUSE1(x) (((x) & BIT_MASK_TXPAUSE1) << BIT_SHIFT_TXPAUSE1)
+#define BITS_TXPAUSE1 (BIT_MASK_TXPAUSE1 << BIT_SHIFT_TXPAUSE1)
+#define BIT_CLEAR_TXPAUSE1(x) ((x) & (~BITS_TXPAUSE1))
+#define BIT_GET_TXPAUSE1(x) (((x) >> BIT_SHIFT_TXPAUSE1) & BIT_MASK_TXPAUSE1)
+#define BIT_SET_TXPAUSE1(x, v) (BIT_CLEAR_TXPAUSE1(x) | BIT_TXPAUSE1(v))
-#define BIT_SHIFT_P2POFF_DIS_TXTIME 0
-#define BIT_MASK_P2POFF_DIS_TXTIME 0xff
-#define BIT_P2POFF_DIS_TXTIME(x) (((x) & BIT_MASK_P2POFF_DIS_TXTIME) << BIT_SHIFT_P2POFF_DIS_TXTIME)
-#define BIT_GET_P2POFF_DIS_TXTIME(x) (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME) & BIT_MASK_P2POFF_DIS_TXTIME)
+#endif
+#if (HALMAC_8822C_SUPPORT)
-/* 2 REG_MBSSID_BCN_SPACE2 (Offset 0x05B8) */
+/* 2 REG_RX_TBTT_SHIFT_V1 (Offset 0x0598) */
+#define BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1 8
+#define BIT_MASK_RX_TBTT_SHIFT_SEL_V1 0x7
+#define BIT_RX_TBTT_SHIFT_SEL_V1(x) \
+ (((x) & BIT_MASK_RX_TBTT_SHIFT_SEL_V1) \
+ << BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1)
+#define BITS_RX_TBTT_SHIFT_SEL_V1 \
+ (BIT_MASK_RX_TBTT_SHIFT_SEL_V1 << BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1)
+#define BIT_CLEAR_RX_TBTT_SHIFT_SEL_V1(x) ((x) & (~BITS_RX_TBTT_SHIFT_SEL_V1))
+#define BIT_GET_RX_TBTT_SHIFT_SEL_V1(x) \
+ (((x) >> BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1) & \
+ BIT_MASK_RX_TBTT_SHIFT_SEL_V1)
+#define BIT_SET_RX_TBTT_SHIFT_SEL_V1(x, v) \
+ (BIT_CLEAR_RX_TBTT_SHIFT_SEL_V1(x) | BIT_RX_TBTT_SHIFT_SEL_V1(v))
-#define BIT_SHIFT_BCN_SPACE_CLINT2 16
-#define BIT_MASK_BCN_SPACE_CLINT2 0xfff
-#define BIT_BCN_SPACE_CLINT2(x) (((x) & BIT_MASK_BCN_SPACE_CLINT2) << BIT_SHIFT_BCN_SPACE_CLINT2)
-#define BIT_GET_BCN_SPACE_CLINT2(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT2) & BIT_MASK_BCN_SPACE_CLINT2)
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+/* 2 REG_TBTT_INT_SHIFT_ENABLE (Offset 0x0598) */
-#define BIT_SHIFT_BCN_SPACE_CLINT1 0
-#define BIT_MASK_BCN_SPACE_CLINT1 0xfff
-#define BIT_BCN_SPACE_CLINT1(x) (((x) & BIT_MASK_BCN_SPACE_CLINT1) << BIT_SHIFT_BCN_SPACE_CLINT1)
-#define BIT_GET_BCN_SPACE_CLINT1(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT1) & BIT_MASK_BCN_SPACE_CLINT1)
+#define BIT_EN_TBTT_RTY BIT(1)
+#define BIT_TBTT_INT_SHIFT_ENABLE BIT(0)
+#define BIT_SHIFT_BCN_ELY_ADJ 0
+#define BIT_MASK_BCN_ELY_ADJ 0xffff
+#define BIT_BCN_ELY_ADJ(x) \
+ (((x) & BIT_MASK_BCN_ELY_ADJ) << BIT_SHIFT_BCN_ELY_ADJ)
+#define BITS_BCN_ELY_ADJ (BIT_MASK_BCN_ELY_ADJ << BIT_SHIFT_BCN_ELY_ADJ)
+#define BIT_CLEAR_BCN_ELY_ADJ(x) ((x) & (~BITS_BCN_ELY_ADJ))
+#define BIT_GET_BCN_ELY_ADJ(x) \
+ (((x) >> BIT_SHIFT_BCN_ELY_ADJ) & BIT_MASK_BCN_ELY_ADJ)
+#define BIT_SET_BCN_ELY_ADJ(x, v) \
+ (BIT_CLEAR_BCN_ELY_ADJ(x) | BIT_BCN_ELY_ADJ(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_ATIMWND2 (Offset 0x05A0) */
+#define BIT_SHIFT_ATIMWND2 0
+#define BIT_MASK_ATIMWND2 0xff
+#define BIT_ATIMWND2(x) (((x) & BIT_MASK_ATIMWND2) << BIT_SHIFT_ATIMWND2)
+#define BITS_ATIMWND2 (BIT_MASK_ATIMWND2 << BIT_SHIFT_ATIMWND2)
+#define BIT_CLEAR_ATIMWND2(x) ((x) & (~BITS_ATIMWND2))
+#define BIT_GET_ATIMWND2(x) (((x) >> BIT_SHIFT_ATIMWND2) & BIT_MASK_ATIMWND2)
+#define BIT_SET_ATIMWND2(x, v) (BIT_CLEAR_ATIMWND2(x) | BIT_ATIMWND2(v))
-/* 2 REG_MBSSID_BCN_SPACE3 (Offset 0x05BC) */
+#endif
+#if (HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_BCNERR_CNT_OTHERS 24
-#define BIT_MASK_BCNERR_CNT_OTHERS 0xff
-#define BIT_BCNERR_CNT_OTHERS(x) (((x) & BIT_MASK_BCNERR_CNT_OTHERS) << BIT_SHIFT_BCNERR_CNT_OTHERS)
-#define BIT_GET_BCNERR_CNT_OTHERS(x) (((x) >> BIT_SHIFT_BCNERR_CNT_OTHERS) & BIT_MASK_BCNERR_CNT_OTHERS)
+/* 2 REG_ATIMWND_GROUP1 (Offset 0x05A0) */
-#define BIT_BCNERR_CNT_EN BIT(20)
+#define BIT_SHIFT_ATIMWND_GROUP1 0
+#define BIT_MASK_ATIMWND_GROUP1 0xff
+#define BIT_ATIMWND_GROUP1(x) \
+ (((x) & BIT_MASK_ATIMWND_GROUP1) << BIT_SHIFT_ATIMWND_GROUP1)
+#define BITS_ATIMWND_GROUP1 \
+ (BIT_MASK_ATIMWND_GROUP1 << BIT_SHIFT_ATIMWND_GROUP1)
+#define BIT_CLEAR_ATIMWND_GROUP1(x) ((x) & (~BITS_ATIMWND_GROUP1))
+#define BIT_GET_ATIMWND_GROUP1(x) \
+ (((x) >> BIT_SHIFT_ATIMWND_GROUP1) & BIT_MASK_ATIMWND_GROUP1)
+#define BIT_SET_ATIMWND_GROUP1(x, v) \
+ (BIT_CLEAR_ATIMWND_GROUP1(x) | BIT_ATIMWND_GROUP1(v))
-#define BIT_SHIFT_SUB_BCN_SPACE_V1 16
-#define BIT_MASK_SUB_BCN_SPACE_V1 0xfff
-#define BIT_SUB_BCN_SPACE_V1(x) (((x) & BIT_MASK_SUB_BCN_SPACE_V1) << BIT_SHIFT_SUB_BCN_SPACE_V1)
-#define BIT_GET_SUB_BCN_SPACE_V1(x) (((x) >> BIT_SHIFT_SUB_BCN_SPACE_V1) & BIT_MASK_SUB_BCN_SPACE_V1)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_BCNERR_PORT_SEL 16
-#define BIT_MASK_BCNERR_PORT_SEL 0x7
-#define BIT_BCNERR_PORT_SEL(x) (((x) & BIT_MASK_BCNERR_PORT_SEL) << BIT_SHIFT_BCNERR_PORT_SEL)
-#define BIT_GET_BCNERR_PORT_SEL(x) (((x) >> BIT_SHIFT_BCNERR_PORT_SEL) & BIT_MASK_BCNERR_PORT_SEL)
+/* 2 REG_ATIMWND3 (Offset 0x05A1) */
+#define BIT_SHIFT_ATIMWND3 0
+#define BIT_MASK_ATIMWND3 0xff
+#define BIT_ATIMWND3(x) (((x) & BIT_MASK_ATIMWND3) << BIT_SHIFT_ATIMWND3)
+#define BITS_ATIMWND3 (BIT_MASK_ATIMWND3 << BIT_SHIFT_ATIMWND3)
+#define BIT_CLEAR_ATIMWND3(x) ((x) & (~BITS_ATIMWND3))
+#define BIT_GET_ATIMWND3(x) (((x) >> BIT_SHIFT_ATIMWND3) & BIT_MASK_ATIMWND3)
+#define BIT_SET_ATIMWND3(x, v) (BIT_CLEAR_ATIMWND3(x) | BIT_ATIMWND3(v))
-#define BIT_SHIFT_RXBCN_TIMER 16
-#define BIT_MASK_RXBCN_TIMER 0xffff
-#define BIT_RXBCN_TIMER(x) (((x) & BIT_MASK_RXBCN_TIMER) << BIT_SHIFT_RXBCN_TIMER)
-#define BIT_GET_RXBCN_TIMER(x) (((x) >> BIT_SHIFT_RXBCN_TIMER) & BIT_MASK_RXBCN_TIMER)
+#endif
+#if (HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_BCNERR_CNT_INVALID 16
-#define BIT_MASK_BCNERR_CNT_INVALID 0xff
-#define BIT_BCNERR_CNT_INVALID(x) (((x) & BIT_MASK_BCNERR_CNT_INVALID) << BIT_SHIFT_BCNERR_CNT_INVALID)
-#define BIT_GET_BCNERR_CNT_INVALID(x) (((x) >> BIT_SHIFT_BCNERR_CNT_INVALID) & BIT_MASK_BCNERR_CNT_INVALID)
+/* 2 REG_ATIMWND_GROUP2 (Offset 0x05A1) */
+#define BIT_SHIFT_ATIMWND_GROUP2 0
+#define BIT_MASK_ATIMWND_GROUP2 0xff
+#define BIT_ATIMWND_GROUP2(x) \
+ (((x) & BIT_MASK_ATIMWND_GROUP2) << BIT_SHIFT_ATIMWND_GROUP2)
+#define BITS_ATIMWND_GROUP2 \
+ (BIT_MASK_ATIMWND_GROUP2 << BIT_SHIFT_ATIMWND_GROUP2)
+#define BIT_CLEAR_ATIMWND_GROUP2(x) ((x) & (~BITS_ATIMWND_GROUP2))
+#define BIT_GET_ATIMWND_GROUP2(x) \
+ (((x) >> BIT_SHIFT_ATIMWND_GROUP2) & BIT_MASK_ATIMWND_GROUP2)
+#define BIT_SET_ATIMWND_GROUP2(x, v) \
+ (BIT_CLEAR_ATIMWND_GROUP2(x) | BIT_ATIMWND_GROUP2(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ATIMWND4 (Offset 0x05A2) */
+#define BIT_SHIFT_ATIMWND4 0
+#define BIT_MASK_ATIMWND4 0xff
+#define BIT_ATIMWND4(x) (((x) & BIT_MASK_ATIMWND4) << BIT_SHIFT_ATIMWND4)
+#define BITS_ATIMWND4 (BIT_MASK_ATIMWND4 << BIT_SHIFT_ATIMWND4)
+#define BIT_CLEAR_ATIMWND4(x) ((x) & (~BITS_ATIMWND4))
+#define BIT_GET_ATIMWND4(x) (((x) >> BIT_SHIFT_ATIMWND4) & BIT_MASK_ATIMWND4)
+#define BIT_SET_ATIMWND4(x, v) (BIT_CLEAR_ATIMWND4(x) | BIT_ATIMWND4(v))
-/* 2 REG_MBSSID_BCN_SPACE3 (Offset 0x05BC) */
+#endif
+#if (HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_SUB_BCN_SPACE 16
-#define BIT_MASK_SUB_BCN_SPACE 0xff
-#define BIT_SUB_BCN_SPACE(x) (((x) & BIT_MASK_SUB_BCN_SPACE) << BIT_SHIFT_SUB_BCN_SPACE)
-#define BIT_GET_SUB_BCN_SPACE(x) (((x) >> BIT_SHIFT_SUB_BCN_SPACE) & BIT_MASK_SUB_BCN_SPACE)
+/* 2 REG_ATIMWND_GROUP3 (Offset 0x05A2) */
+#define BIT_SHIFT_ATIMWND_GROUP3 0
+#define BIT_MASK_ATIMWND_GROUP3 0xff
+#define BIT_ATIMWND_GROUP3(x) \
+ (((x) & BIT_MASK_ATIMWND_GROUP3) << BIT_SHIFT_ATIMWND_GROUP3)
+#define BITS_ATIMWND_GROUP3 \
+ (BIT_MASK_ATIMWND_GROUP3 << BIT_SHIFT_ATIMWND_GROUP3)
+#define BIT_CLEAR_ATIMWND_GROUP3(x) ((x) & (~BITS_ATIMWND_GROUP3))
+#define BIT_GET_ATIMWND_GROUP3(x) \
+ (((x) >> BIT_SHIFT_ATIMWND_GROUP3) & BIT_MASK_ATIMWND_GROUP3)
+#define BIT_SET_ATIMWND_GROUP3(x, v) \
+ (BIT_CLEAR_ATIMWND_GROUP3(x) | BIT_ATIMWND_GROUP3(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
-
-/* 2 REG_MBSSID_BCN_SPACE3 (Offset 0x05BC) */
+/* 2 REG_ATIMWND5 (Offset 0x05A3) */
+#define BIT_SHIFT_ATIMWND5 0
+#define BIT_MASK_ATIMWND5 0xff
+#define BIT_ATIMWND5(x) (((x) & BIT_MASK_ATIMWND5) << BIT_SHIFT_ATIMWND5)
+#define BITS_ATIMWND5 (BIT_MASK_ATIMWND5 << BIT_SHIFT_ATIMWND5)
+#define BIT_CLEAR_ATIMWND5(x) ((x) & (~BITS_ATIMWND5))
+#define BIT_GET_ATIMWND5(x) (((x) >> BIT_SHIFT_ATIMWND5) & BIT_MASK_ATIMWND5)
+#define BIT_SET_ATIMWND5(x, v) (BIT_CLEAR_ATIMWND5(x) | BIT_ATIMWND5(v))
-#define BIT_SHIFT_TXPAUSE1 8
-#define BIT_MASK_TXPAUSE1 0xff
-#define BIT_TXPAUSE1(x) (((x) & BIT_MASK_TXPAUSE1) << BIT_SHIFT_TXPAUSE1)
-#define BIT_GET_TXPAUSE1(x) (((x) >> BIT_SHIFT_TXPAUSE1) & BIT_MASK_TXPAUSE1)
+#endif
+#if (HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_BCNERR_CNT_MAC 8
-#define BIT_MASK_BCNERR_CNT_MAC 0xff
-#define BIT_BCNERR_CNT_MAC(x) (((x) & BIT_MASK_BCNERR_CNT_MAC) << BIT_SHIFT_BCNERR_CNT_MAC)
-#define BIT_GET_BCNERR_CNT_MAC(x) (((x) >> BIT_SHIFT_BCNERR_CNT_MAC) & BIT_MASK_BCNERR_CNT_MAC)
+/* 2 REG_ATIMWND_GROUP4 (Offset 0x05A3) */
-#define BIT_CHANGE_POW_BCN_AREA BIT(1)
+#define BIT_SHIFT_ATIMWND_GROUP4 0
+#define BIT_MASK_ATIMWND_GROUP4 0xff
+#define BIT_ATIMWND_GROUP4(x) \
+ (((x) & BIT_MASK_ATIMWND_GROUP4) << BIT_SHIFT_ATIMWND_GROUP4)
+#define BITS_ATIMWND_GROUP4 \
+ (BIT_MASK_ATIMWND_GROUP4 << BIT_SHIFT_ATIMWND_GROUP4)
+#define BIT_CLEAR_ATIMWND_GROUP4(x) ((x) & (~BITS_ATIMWND_GROUP4))
+#define BIT_GET_ATIMWND_GROUP4(x) \
+ (((x) >> BIT_SHIFT_ATIMWND_GROUP4) & BIT_MASK_ATIMWND_GROUP4)
+#define BIT_SET_ATIMWND_GROUP4(x, v) \
+ (BIT_CLEAR_ATIMWND_GROUP4(x) | BIT_ATIMWND_GROUP4(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ATIMWND6 (Offset 0x05A4) */
+#define BIT_SHIFT_ATIMWND6 0
+#define BIT_MASK_ATIMWND6 0xff
+#define BIT_ATIMWND6(x) (((x) & BIT_MASK_ATIMWND6) << BIT_SHIFT_ATIMWND6)
+#define BITS_ATIMWND6 (BIT_MASK_ATIMWND6 << BIT_SHIFT_ATIMWND6)
+#define BIT_CLEAR_ATIMWND6(x) ((x) & (~BITS_ATIMWND6))
+#define BIT_GET_ATIMWND6(x) (((x) >> BIT_SHIFT_ATIMWND6) & BIT_MASK_ATIMWND6)
+#define BIT_SET_ATIMWND6(x, v) (BIT_CLEAR_ATIMWND6(x) | BIT_ATIMWND6(v))
-/* 2 REG_MBSSID_BCN_SPACE3 (Offset 0x05BC) */
+#endif
+#if (HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_BCN_SPACE_CLINT3 0
-#define BIT_MASK_BCN_SPACE_CLINT3 0xfff
-#define BIT_BCN_SPACE_CLINT3(x) (((x) & BIT_MASK_BCN_SPACE_CLINT3) << BIT_SHIFT_BCN_SPACE_CLINT3)
-#define BIT_GET_BCN_SPACE_CLINT3(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT3) & BIT_MASK_BCN_SPACE_CLINT3)
+/* 2 REG_DTIM_COUNT_GROUP1 (Offset 0x05A4) */
+#define BIT_SHIFT_DTIM_COUNT_GROUP1 0
+#define BIT_MASK_DTIM_COUNT_GROUP1 0xff
+#define BIT_DTIM_COUNT_GROUP1(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_GROUP1) << BIT_SHIFT_DTIM_COUNT_GROUP1)
+#define BITS_DTIM_COUNT_GROUP1 \
+ (BIT_MASK_DTIM_COUNT_GROUP1 << BIT_SHIFT_DTIM_COUNT_GROUP1)
+#define BIT_CLEAR_DTIM_COUNT_GROUP1(x) ((x) & (~BITS_DTIM_COUNT_GROUP1))
+#define BIT_GET_DTIM_COUNT_GROUP1(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_GROUP1) & BIT_MASK_DTIM_COUNT_GROUP1)
+#define BIT_SET_DTIM_COUNT_GROUP1(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_GROUP1(x) | BIT_DTIM_COUNT_GROUP1(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_ATIMWND7 (Offset 0x05A5) */
+#define BIT_SHIFT_ATIMWND7 0
+#define BIT_MASK_ATIMWND7 0xff
+#define BIT_ATIMWND7(x) (((x) & BIT_MASK_ATIMWND7) << BIT_SHIFT_ATIMWND7)
+#define BITS_ATIMWND7 (BIT_MASK_ATIMWND7 << BIT_SHIFT_ATIMWND7)
+#define BIT_CLEAR_ATIMWND7(x) ((x) & (~BITS_ATIMWND7))
+#define BIT_GET_ATIMWND7(x) (((x) >> BIT_SHIFT_ATIMWND7) & BIT_MASK_ATIMWND7)
+#define BIT_SET_ATIMWND7(x, v) (BIT_CLEAR_ATIMWND7(x) | BIT_ATIMWND7(v))
-/* 2 REG_MBSSID_BCN_SPACE3 (Offset 0x05BC) */
+#endif
+#if (HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_BW_CFG 0
-#define BIT_MASK_BW_CFG 0x3
-#define BIT_BW_CFG(x) (((x) & BIT_MASK_BW_CFG) << BIT_SHIFT_BW_CFG)
-#define BIT_GET_BW_CFG(x) (((x) >> BIT_SHIFT_BW_CFG) & BIT_MASK_BW_CFG)
+/* 2 REG_DTIM_COUNT_GROUP2 (Offset 0x05A5) */
+#define BIT_SHIFT_DTIM_COUNT_GROUP2 0
+#define BIT_MASK_DTIM_COUNT_GROUP2 0xff
+#define BIT_DTIM_COUNT_GROUP2(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_GROUP2) << BIT_SHIFT_DTIM_COUNT_GROUP2)
+#define BITS_DTIM_COUNT_GROUP2 \
+ (BIT_MASK_DTIM_COUNT_GROUP2 << BIT_SHIFT_DTIM_COUNT_GROUP2)
+#define BIT_CLEAR_DTIM_COUNT_GROUP2(x) ((x) & (~BITS_DTIM_COUNT_GROUP2))
+#define BIT_GET_DTIM_COUNT_GROUP2(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_GROUP2) & BIT_MASK_DTIM_COUNT_GROUP2)
+#define BIT_SET_DTIM_COUNT_GROUP2(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_GROUP2(x) | BIT_DTIM_COUNT_GROUP2(v))
-#define BIT_SHIFT_BCN_ELY_ADJ 0
-#define BIT_MASK_BCN_ELY_ADJ 0xffff
-#define BIT_BCN_ELY_ADJ(x) (((x) & BIT_MASK_BCN_ELY_ADJ) << BIT_SHIFT_BCN_ELY_ADJ)
-#define BIT_GET_BCN_ELY_ADJ(x) (((x) >> BIT_SHIFT_BCN_ELY_ADJ) & BIT_MASK_BCN_ELY_ADJ)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_BCNERR_CNT_CCA 0
-#define BIT_MASK_BCNERR_CNT_CCA 0xff
-#define BIT_BCNERR_CNT_CCA(x) (((x) & BIT_MASK_BCNERR_CNT_CCA) << BIT_SHIFT_BCNERR_CNT_CCA)
-#define BIT_GET_BCNERR_CNT_CCA(x) (((x) >> BIT_SHIFT_BCNERR_CNT_CCA) & BIT_MASK_BCNERR_CNT_CCA)
+/* 2 REG_ATIMUGT (Offset 0x05A6) */
+#define BIT_SHIFT_ATIM_URGENT 0
+#define BIT_MASK_ATIM_URGENT 0xff
+#define BIT_ATIM_URGENT(x) \
+ (((x) & BIT_MASK_ATIM_URGENT) << BIT_SHIFT_ATIM_URGENT)
+#define BITS_ATIM_URGENT (BIT_MASK_ATIM_URGENT << BIT_SHIFT_ATIM_URGENT)
+#define BIT_CLEAR_ATIM_URGENT(x) ((x) & (~BITS_ATIM_URGENT))
+#define BIT_GET_ATIM_URGENT(x) \
+ (((x) >> BIT_SHIFT_ATIM_URGENT) & BIT_MASK_ATIM_URGENT)
+#define BIT_SET_ATIM_URGENT(x, v) \
+ (BIT_CLEAR_ATIM_URGENT(x) | BIT_ATIM_URGENT(v))
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_DTIM_COUNT_GROUP3 (Offset 0x05A6) */
+#define BIT_SHIFT_DTIM_COUNT_GROUP3 0
+#define BIT_MASK_DTIM_COUNT_GROUP3 0xff
+#define BIT_DTIM_COUNT_GROUP3(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_GROUP3) << BIT_SHIFT_DTIM_COUNT_GROUP3)
+#define BITS_DTIM_COUNT_GROUP3 \
+ (BIT_MASK_DTIM_COUNT_GROUP3 << BIT_SHIFT_DTIM_COUNT_GROUP3)
+#define BIT_CLEAR_DTIM_COUNT_GROUP3(x) ((x) & (~BITS_DTIM_COUNT_GROUP3))
+#define BIT_GET_DTIM_COUNT_GROUP3(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_GROUP3) & BIT_MASK_DTIM_COUNT_GROUP3)
+#define BIT_SET_DTIM_COUNT_GROUP3(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_GROUP3(x) | BIT_DTIM_COUNT_GROUP3(v))
-/* 2 REG_ACMHWCTRL (Offset 0x05C0) */
+#endif
-#define BIT_BEQ_ACM_STATUS BIT(7)
-#define BIT_VIQ_ACM_STATUS BIT(6)
-#define BIT_VOQ_ACM_STATUS BIT(5)
-#define BIT_BEQ_ACM_EN BIT(3)
-#define BIT_VIQ_ACM_EN BIT(2)
-#define BIT_VOQ_ACM_EN BIT(1)
-#define BIT_ACMHWEN BIT(0)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-/* 2 REG_ACMRSTCTRL (Offset 0x05C1) */
+/* 2 REG_HIQ_NO_LMT_EN (Offset 0x05A7) */
-#define BIT_BE_ACM_RESET_USED_TIME BIT(2)
-#define BIT_VI_ACM_RESET_USED_TIME BIT(1)
-#define BIT_VO_ACM_RESET_USED_TIME BIT(0)
+#define BIT_HIQ_NO_LMT_EN_VAP7 BIT(7)
+#define BIT_HIQ_NO_LMT_EN_VAP6 BIT(6)
+#define BIT_HIQ_NO_LMT_EN_VAP5 BIT(5)
+#define BIT_HIQ_NO_LMT_EN_VAP4 BIT(4)
+#define BIT_HIQ_NO_LMT_EN_VAP3 BIT(3)
+#define BIT_HIQ_NO_LMT_EN_VAP2 BIT(2)
+#define BIT_HIQ_NO_LMT_EN_VAP1 BIT(1)
-/* 2 REG_ACMAVG (Offset 0x05C2) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_AVGPERIOD 0
-#define BIT_MASK_AVGPERIOD 0xffff
-#define BIT_AVGPERIOD(x) (((x) & BIT_MASK_AVGPERIOD) << BIT_SHIFT_AVGPERIOD)
-#define BIT_GET_AVGPERIOD(x) (((x) >> BIT_SHIFT_AVGPERIOD) & BIT_MASK_AVGPERIOD)
+/* 2 REG_HIQ_NO_LMT_EN (Offset 0x05A7) */
+#define BIT_HIQ_NO_LMT_EN_ROOT BIT(0)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_DTIM_COUNT_GROUP4 (Offset 0x05A7) */
+
+#define BIT_SHIFT_DTIM_COUNT_GROUP4 0
+#define BIT_MASK_DTIM_COUNT_GROUP4 0xff
+#define BIT_DTIM_COUNT_GROUP4(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_GROUP4) << BIT_SHIFT_DTIM_COUNT_GROUP4)
+#define BITS_DTIM_COUNT_GROUP4 \
+ (BIT_MASK_DTIM_COUNT_GROUP4 << BIT_SHIFT_DTIM_COUNT_GROUP4)
+#define BIT_CLEAR_DTIM_COUNT_GROUP4(x) ((x) & (~BITS_DTIM_COUNT_GROUP4))
+#define BIT_GET_DTIM_COUNT_GROUP4(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_GROUP4) & BIT_MASK_DTIM_COUNT_GROUP4)
+#define BIT_SET_DTIM_COUNT_GROUP4(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_GROUP4(x) | BIT_DTIM_COUNT_GROUP4(v))
+
+/* 2 REG_HIQ_NO_LMT_EN_V2 (Offset 0x05A8) */
+
+#define BIT_SHIFT_ATIM_CFG_SEL 24
+#define BIT_MASK_ATIM_CFG_SEL 0x3
+#define BIT_ATIM_CFG_SEL(x) \
+ (((x) & BIT_MASK_ATIM_CFG_SEL) << BIT_SHIFT_ATIM_CFG_SEL)
+#define BITS_ATIM_CFG_SEL (BIT_MASK_ATIM_CFG_SEL << BIT_SHIFT_ATIM_CFG_SEL)
+#define BIT_CLEAR_ATIM_CFG_SEL(x) ((x) & (~BITS_ATIM_CFG_SEL))
+#define BIT_GET_ATIM_CFG_SEL(x) \
+ (((x) >> BIT_SHIFT_ATIM_CFG_SEL) & BIT_MASK_ATIM_CFG_SEL)
+#define BIT_SET_ATIM_CFG_SEL(x, v) \
+ (BIT_CLEAR_ATIM_CFG_SEL(x) | BIT_ATIM_CFG_SEL(v))
+
+#define BIT_SHIFT_DIS_ATIM 16
+#define BIT_MASK_DIS_ATIM 0xffff
+#define BIT_DIS_ATIM(x) (((x) & BIT_MASK_DIS_ATIM) << BIT_SHIFT_DIS_ATIM)
+#define BITS_DIS_ATIM (BIT_MASK_DIS_ATIM << BIT_SHIFT_DIS_ATIM)
+#define BIT_CLEAR_DIS_ATIM(x) ((x) & (~BITS_DIS_ATIM))
+#define BIT_GET_DIS_ATIM(x) (((x) >> BIT_SHIFT_DIS_ATIM) & BIT_MASK_DIS_ATIM)
+#define BIT_SET_DIS_ATIM(x, v) (BIT_CLEAR_DIS_ATIM(x) | BIT_DIS_ATIM(v))
+
+#define BIT_SHIFT_ATIM_URGENT_V1 16
+#define BIT_MASK_ATIM_URGENT_V1 0xff
+#define BIT_ATIM_URGENT_V1(x) \
+ (((x) & BIT_MASK_ATIM_URGENT_V1) << BIT_SHIFT_ATIM_URGENT_V1)
+#define BITS_ATIM_URGENT_V1 \
+ (BIT_MASK_ATIM_URGENT_V1 << BIT_SHIFT_ATIM_URGENT_V1)
+#define BIT_CLEAR_ATIM_URGENT_V1(x) ((x) & (~BITS_ATIM_URGENT_V1))
+#define BIT_GET_ATIM_URGENT_V1(x) \
+ (((x) >> BIT_SHIFT_ATIM_URGENT_V1) & BIT_MASK_ATIM_URGENT_V1)
+#define BIT_SET_ATIM_URGENT_V1(x, v) \
+ (BIT_CLEAR_ATIM_URGENT_V1(x) | BIT_ATIM_URGENT_V1(v))
+
+#define BIT_SHIFT_BCNERR_PORT_SEL_V1 16
+#define BIT_MASK_BCNERR_PORT_SEL_V1 0xf
+#define BIT_BCNERR_PORT_SEL_V1(x) \
+ (((x) & BIT_MASK_BCNERR_PORT_SEL_V1) << BIT_SHIFT_BCNERR_PORT_SEL_V1)
+#define BITS_BCNERR_PORT_SEL_V1 \
+ (BIT_MASK_BCNERR_PORT_SEL_V1 << BIT_SHIFT_BCNERR_PORT_SEL_V1)
+#define BIT_CLEAR_BCNERR_PORT_SEL_V1(x) ((x) & (~BITS_BCNERR_PORT_SEL_V1))
+#define BIT_GET_BCNERR_PORT_SEL_V1(x) \
+ (((x) >> BIT_SHIFT_BCNERR_PORT_SEL_V1) & BIT_MASK_BCNERR_PORT_SEL_V1)
+#define BIT_SET_BCNERR_PORT_SEL_V1(x, v) \
+ (BIT_CLEAR_BCNERR_PORT_SEL_V1(x) | BIT_BCNERR_PORT_SEL_V1(v))
+
+#define BIT_DIS_NDPA_NAV_CHK BIT(8)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_VO_ADMTIME (Offset 0x05C4) */
+/* 2 REG_DTIM_COUNTER_ROOT (Offset 0x05A8) */
+#define BIT_SHIFT_DTIM_COUNT_ROOT 0
+#define BIT_MASK_DTIM_COUNT_ROOT 0xff
+#define BIT_DTIM_COUNT_ROOT(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_ROOT) << BIT_SHIFT_DTIM_COUNT_ROOT)
+#define BITS_DTIM_COUNT_ROOT \
+ (BIT_MASK_DTIM_COUNT_ROOT << BIT_SHIFT_DTIM_COUNT_ROOT)
+#define BIT_CLEAR_DTIM_COUNT_ROOT(x) ((x) & (~BITS_DTIM_COUNT_ROOT))
+#define BIT_GET_DTIM_COUNT_ROOT(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_ROOT) & BIT_MASK_DTIM_COUNT_ROOT)
+#define BIT_SET_DTIM_COUNT_ROOT(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_ROOT(x) | BIT_DTIM_COUNT_ROOT(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HIQ_NO_LMT_EN_V2 (Offset 0x05A8) */
+
+#define BIT_SHIFT_MBID_BCNQ_EN 0
+#define BIT_MASK_MBID_BCNQ_EN 0xffff
+#define BIT_MBID_BCNQ_EN(x) \
+ (((x) & BIT_MASK_MBID_BCNQ_EN) << BIT_SHIFT_MBID_BCNQ_EN)
+#define BITS_MBID_BCNQ_EN (BIT_MASK_MBID_BCNQ_EN << BIT_SHIFT_MBID_BCNQ_EN)
+#define BIT_CLEAR_MBID_BCNQ_EN(x) ((x) & (~BITS_MBID_BCNQ_EN))
+#define BIT_GET_MBID_BCNQ_EN(x) \
+ (((x) >> BIT_SHIFT_MBID_BCNQ_EN) & BIT_MASK_MBID_BCNQ_EN)
+#define BIT_SET_MBID_BCNQ_EN(x, v) \
+ (BIT_CLEAR_MBID_BCNQ_EN(x) | BIT_MBID_BCNQ_EN(v))
+
+#define BIT_SHIFT_MHDR_NAV_OFFSET 0
+#define BIT_MASK_MHDR_NAV_OFFSET 0xff
+#define BIT_MHDR_NAV_OFFSET(x) \
+ (((x) & BIT_MASK_MHDR_NAV_OFFSET) << BIT_SHIFT_MHDR_NAV_OFFSET)
+#define BITS_MHDR_NAV_OFFSET \
+ (BIT_MASK_MHDR_NAV_OFFSET << BIT_SHIFT_MHDR_NAV_OFFSET)
+#define BIT_CLEAR_MHDR_NAV_OFFSET(x) ((x) & (~BITS_MHDR_NAV_OFFSET))
+#define BIT_GET_MHDR_NAV_OFFSET(x) \
+ (((x) >> BIT_SHIFT_MHDR_NAV_OFFSET) & BIT_MASK_MHDR_NAV_OFFSET)
+#define BIT_SET_MHDR_NAV_OFFSET(x, v) \
+ (BIT_CLEAR_MHDR_NAV_OFFSET(x) | BIT_MHDR_NAV_OFFSET(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_VO_ADMITTED_TIME 0
-#define BIT_MASK_VO_ADMITTED_TIME 0xffff
-#define BIT_VO_ADMITTED_TIME(x) (((x) & BIT_MASK_VO_ADMITTED_TIME) << BIT_SHIFT_VO_ADMITTED_TIME)
-#define BIT_GET_VO_ADMITTED_TIME(x) (((x) >> BIT_SHIFT_VO_ADMITTED_TIME) & BIT_MASK_VO_ADMITTED_TIME)
+/* 2 REG_DTIM_COUNTER_VAP1 (Offset 0x05A9) */
+#define BIT_SHIFT_DTIM_COUNT_VAP1 0
+#define BIT_MASK_DTIM_COUNT_VAP1 0xff
+#define BIT_DTIM_COUNT_VAP1(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_VAP1) << BIT_SHIFT_DTIM_COUNT_VAP1)
+#define BITS_DTIM_COUNT_VAP1 \
+ (BIT_MASK_DTIM_COUNT_VAP1 << BIT_SHIFT_DTIM_COUNT_VAP1)
+#define BIT_CLEAR_DTIM_COUNT_VAP1(x) ((x) & (~BITS_DTIM_COUNT_VAP1))
+#define BIT_GET_DTIM_COUNT_VAP1(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP1) & BIT_MASK_DTIM_COUNT_VAP1)
+#define BIT_SET_DTIM_COUNT_VAP1(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_VAP1(x) | BIT_DTIM_COUNT_VAP1(v))
-/* 2 REG_VI_ADMTIME (Offset 0x05C6) */
+/* 2 REG_DTIM_COUNTER_VAP2 (Offset 0x05AA) */
+#define BIT_SHIFT_DTIM_COUNT_VAP2 0
+#define BIT_MASK_DTIM_COUNT_VAP2 0xff
+#define BIT_DTIM_COUNT_VAP2(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_VAP2) << BIT_SHIFT_DTIM_COUNT_VAP2)
+#define BITS_DTIM_COUNT_VAP2 \
+ (BIT_MASK_DTIM_COUNT_VAP2 << BIT_SHIFT_DTIM_COUNT_VAP2)
+#define BIT_CLEAR_DTIM_COUNT_VAP2(x) ((x) & (~BITS_DTIM_COUNT_VAP2))
+#define BIT_GET_DTIM_COUNT_VAP2(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP2) & BIT_MASK_DTIM_COUNT_VAP2)
+#define BIT_SET_DTIM_COUNT_VAP2(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_VAP2(x) | BIT_DTIM_COUNT_VAP2(v))
-#define BIT_SHIFT_VI_ADMITTED_TIME 0
-#define BIT_MASK_VI_ADMITTED_TIME 0xffff
-#define BIT_VI_ADMITTED_TIME(x) (((x) & BIT_MASK_VI_ADMITTED_TIME) << BIT_SHIFT_VI_ADMITTED_TIME)
-#define BIT_GET_VI_ADMITTED_TIME(x) (((x) >> BIT_SHIFT_VI_ADMITTED_TIME) & BIT_MASK_VI_ADMITTED_TIME)
+/* 2 REG_DTIM_COUNTER_VAP3 (Offset 0x05AB) */
+#define BIT_SHIFT_DTIM_COUNT_VAP3 0
+#define BIT_MASK_DTIM_COUNT_VAP3 0xff
+#define BIT_DTIM_COUNT_VAP3(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_VAP3) << BIT_SHIFT_DTIM_COUNT_VAP3)
+#define BITS_DTIM_COUNT_VAP3 \
+ (BIT_MASK_DTIM_COUNT_VAP3 << BIT_SHIFT_DTIM_COUNT_VAP3)
+#define BIT_CLEAR_DTIM_COUNT_VAP3(x) ((x) & (~BITS_DTIM_COUNT_VAP3))
+#define BIT_GET_DTIM_COUNT_VAP3(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP3) & BIT_MASK_DTIM_COUNT_VAP3)
+#define BIT_SET_DTIM_COUNT_VAP3(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_VAP3(x) | BIT_DTIM_COUNT_VAP3(v))
-/* 2 REG_BE_ADMTIME (Offset 0x05C8) */
+/* 2 REG_DTIM_COUNTER_VAP4 (Offset 0x05AC) */
+#define BIT_SHIFT_DTIM_COUNT_VAP4 0
+#define BIT_MASK_DTIM_COUNT_VAP4 0xff
+#define BIT_DTIM_COUNT_VAP4(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_VAP4) << BIT_SHIFT_DTIM_COUNT_VAP4)
+#define BITS_DTIM_COUNT_VAP4 \
+ (BIT_MASK_DTIM_COUNT_VAP4 << BIT_SHIFT_DTIM_COUNT_VAP4)
+#define BIT_CLEAR_DTIM_COUNT_VAP4(x) ((x) & (~BITS_DTIM_COUNT_VAP4))
+#define BIT_GET_DTIM_COUNT_VAP4(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP4) & BIT_MASK_DTIM_COUNT_VAP4)
+#define BIT_SET_DTIM_COUNT_VAP4(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_VAP4(x) | BIT_DTIM_COUNT_VAP4(v))
-#define BIT_SHIFT_BE_ADMITTED_TIME 0
-#define BIT_MASK_BE_ADMITTED_TIME 0xffff
-#define BIT_BE_ADMITTED_TIME(x) (((x) & BIT_MASK_BE_ADMITTED_TIME) << BIT_SHIFT_BE_ADMITTED_TIME)
-#define BIT_GET_BE_ADMITTED_TIME(x) (((x) >> BIT_SHIFT_BE_ADMITTED_TIME) & BIT_MASK_BE_ADMITTED_TIME)
+/* 2 REG_DTIM_COUNTER_VAP5 (Offset 0x05AD) */
+#define BIT_SHIFT_DTIM_COUNT_VAP5 0
+#define BIT_MASK_DTIM_COUNT_VAP5 0xff
+#define BIT_DTIM_COUNT_VAP5(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_VAP5) << BIT_SHIFT_DTIM_COUNT_VAP5)
+#define BITS_DTIM_COUNT_VAP5 \
+ (BIT_MASK_DTIM_COUNT_VAP5 << BIT_SHIFT_DTIM_COUNT_VAP5)
+#define BIT_CLEAR_DTIM_COUNT_VAP5(x) ((x) & (~BITS_DTIM_COUNT_VAP5))
+#define BIT_GET_DTIM_COUNT_VAP5(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP5) & BIT_MASK_DTIM_COUNT_VAP5)
+#define BIT_SET_DTIM_COUNT_VAP5(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_VAP5(x) | BIT_DTIM_COUNT_VAP5(v))
-/* 2 REG_EDCA_RANDOM_GEN (Offset 0x05CC) */
+/* 2 REG_DTIM_COUNTER_VAP6 (Offset 0x05AE) */
+#define BIT_SHIFT_DTIM_COUNT_VAP6 0
+#define BIT_MASK_DTIM_COUNT_VAP6 0xff
+#define BIT_DTIM_COUNT_VAP6(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_VAP6) << BIT_SHIFT_DTIM_COUNT_VAP6)
+#define BITS_DTIM_COUNT_VAP6 \
+ (BIT_MASK_DTIM_COUNT_VAP6 << BIT_SHIFT_DTIM_COUNT_VAP6)
+#define BIT_CLEAR_DTIM_COUNT_VAP6(x) ((x) & (~BITS_DTIM_COUNT_VAP6))
+#define BIT_GET_DTIM_COUNT_VAP6(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP6) & BIT_MASK_DTIM_COUNT_VAP6)
+#define BIT_SET_DTIM_COUNT_VAP6(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_VAP6(x) | BIT_DTIM_COUNT_VAP6(v))
-#define BIT_SHIFT_RANDOM_GEN 0
-#define BIT_MASK_RANDOM_GEN 0xffffff
-#define BIT_RANDOM_GEN(x) (((x) & BIT_MASK_RANDOM_GEN) << BIT_SHIFT_RANDOM_GEN)
-#define BIT_GET_RANDOM_GEN(x) (((x) >> BIT_SHIFT_RANDOM_GEN) & BIT_MASK_RANDOM_GEN)
+/* 2 REG_DTIM_COUNTER_VAP7 (Offset 0x05AF) */
+#define BIT_SHIFT_DTIM_COUNT_VAP7 0
+#define BIT_MASK_DTIM_COUNT_VAP7 0xff
+#define BIT_DTIM_COUNT_VAP7(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_VAP7) << BIT_SHIFT_DTIM_COUNT_VAP7)
+#define BITS_DTIM_COUNT_VAP7 \
+ (BIT_MASK_DTIM_COUNT_VAP7 << BIT_SHIFT_DTIM_COUNT_VAP7)
+#define BIT_CLEAR_DTIM_COUNT_VAP7(x) ((x) & (~BITS_DTIM_COUNT_VAP7))
+#define BIT_GET_DTIM_COUNT_VAP7(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP7) & BIT_MASK_DTIM_COUNT_VAP7)
+#define BIT_SET_DTIM_COUNT_VAP7(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_VAP7(x) | BIT_DTIM_COUNT_VAP7(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT)
+/* 2 REG_DIS_ATIM (Offset 0x05B0) */
+#define BIT_DIS_ATIM_VAP7 BIT(7)
+#define BIT_DIS_ATIM_VAP6 BIT(6)
+#define BIT_DIS_ATIM_VAP5 BIT(5)
+#define BIT_DIS_ATIM_VAP4 BIT(4)
+#define BIT_DIS_ATIM_VAP3 BIT(3)
+#define BIT_DIS_ATIM_VAP2 BIT(2)
+#define BIT_DIS_ATIM_VAP1 BIT(1)
-/* 2 REG_TXCMD_NOA_SEL (Offset 0x05CF) */
+#endif
-#define BIT_NOA_SEL BIT(4)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_DIS_ATIM (Offset 0x05B0) */
+#define BIT_DIS_ATIM_ROOT BIT(0)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-/* 2 REG_TXCMD_NOA_SEL (Offset 0x05CF) */
+/* 2 REG_EARLY_128US (Offset 0x05B1) */
+#define BIT_SHIFT_TSFT_SEL_TIMER1 3
+#define BIT_MASK_TSFT_SEL_TIMER1 0x7
+#define BIT_TSFT_SEL_TIMER1(x) \
+ (((x) & BIT_MASK_TSFT_SEL_TIMER1) << BIT_SHIFT_TSFT_SEL_TIMER1)
+#define BITS_TSFT_SEL_TIMER1 \
+ (BIT_MASK_TSFT_SEL_TIMER1 << BIT_SHIFT_TSFT_SEL_TIMER1)
+#define BIT_CLEAR_TSFT_SEL_TIMER1(x) ((x) & (~BITS_TSFT_SEL_TIMER1))
+#define BIT_GET_TSFT_SEL_TIMER1(x) \
+ (((x) >> BIT_SHIFT_TSFT_SEL_TIMER1) & BIT_MASK_TSFT_SEL_TIMER1)
+#define BIT_SET_TSFT_SEL_TIMER1(x, v) \
+ (BIT_CLEAR_TSFT_SEL_TIMER1(x) | BIT_TSFT_SEL_TIMER1(v))
-#define BIT_SHIFT_NOA_SEL 4
-#define BIT_MASK_NOA_SEL 0x7
-#define BIT_NOA_SEL(x) (((x) & BIT_MASK_NOA_SEL) << BIT_SHIFT_NOA_SEL)
-#define BIT_GET_NOA_SEL(x) (((x) >> BIT_SHIFT_NOA_SEL) & BIT_MASK_NOA_SEL)
+/* 2 REG_P2PPS1_CTRL (Offset 0x05B2) */
+#define BIT_P2P1_CTW_ALLSTASLEEP BIT(7)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8881A_SUPPORT)
+/* 2 REG_P2PPS1_CTRL (Offset 0x05B2) */
+#define BIT_P2P1_OFF_DISTX_EN BIT(6)
-/* 2 REG_TXCMD_NOA_SEL (Offset 0x05CF) */
+#endif
-#define BIT_NOA_SEL_V1 BIT(4)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_P2PPS1_CTRL (Offset 0x05B2) */
+#define BIT_P2P1_PWR_MGT_EN BIT(5)
+#define BIT_P2P1_NOA1_EN BIT(2)
+#define BIT_P2P1_NOA0_EN BIT(1)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_P2PPS2_CTRL (Offset 0x05B3) */
+#define BIT_P2P2_CTW_ALLSTASLEEP BIT(7)
-/* 2 REG_TXCMD_NOA_SEL (Offset 0x05CF) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_TXCMD_SEG_SEL 0
-#define BIT_MASK_TXCMD_SEG_SEL 0xf
-#define BIT_TXCMD_SEG_SEL(x) (((x) & BIT_MASK_TXCMD_SEG_SEL) << BIT_SHIFT_TXCMD_SEG_SEL)
-#define BIT_GET_TXCMD_SEG_SEL(x) (((x) >> BIT_SHIFT_TXCMD_SEG_SEL) & BIT_MASK_TXCMD_SEG_SEL)
+/* 2 REG_P2PPS2_CTRL (Offset 0x05B3) */
+#define BIT_P2P2_OFF_DISTX_EN BIT(6)
-/* 2 REG_NOA_PARAM (Offset 0x05E0) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_NOA_COUNT (96 & CPU_OPT_WIDTH)
-#define BIT_MASK_NOA_COUNT 0xff
-#define BIT_NOA_COUNT(x) (((x) & BIT_MASK_NOA_COUNT) << BIT_SHIFT_NOA_COUNT)
-#define BIT_GET_NOA_COUNT(x) (((x) >> BIT_SHIFT_NOA_COUNT) & BIT_MASK_NOA_COUNT)
+/* 2 REG_P2PPS2_CTRL (Offset 0x05B3) */
+#define BIT_P2P2_PWR_MGT_EN BIT(5)
+#define BIT_P2P2_NOA1_EN BIT(2)
+#define BIT_P2P2_NOA0_EN BIT(1)
-#define BIT_SHIFT_NOA_START_TIME (64 & CPU_OPT_WIDTH)
-#define BIT_MASK_NOA_START_TIME 0xffffffffL
-#define BIT_NOA_START_TIME(x) (((x) & BIT_MASK_NOA_START_TIME) << BIT_SHIFT_NOA_START_TIME)
-#define BIT_GET_NOA_START_TIME(x) (((x) >> BIT_SHIFT_NOA_START_TIME) & BIT_MASK_NOA_START_TIME)
+/* 2 REG_TIMER0_SRC_SEL (Offset 0x05B4) */
+#define BIT_SHIFT_SYNC_CLI_SEL 4
+#define BIT_MASK_SYNC_CLI_SEL 0x7
+#define BIT_SYNC_CLI_SEL(x) \
+ (((x) & BIT_MASK_SYNC_CLI_SEL) << BIT_SHIFT_SYNC_CLI_SEL)
+#define BITS_SYNC_CLI_SEL (BIT_MASK_SYNC_CLI_SEL << BIT_SHIFT_SYNC_CLI_SEL)
+#define BIT_CLEAR_SYNC_CLI_SEL(x) ((x) & (~BITS_SYNC_CLI_SEL))
+#define BIT_GET_SYNC_CLI_SEL(x) \
+ (((x) >> BIT_SHIFT_SYNC_CLI_SEL) & BIT_MASK_SYNC_CLI_SEL)
+#define BIT_SET_SYNC_CLI_SEL(x, v) \
+ (BIT_CLEAR_SYNC_CLI_SEL(x) | BIT_SYNC_CLI_SEL(v))
+
+#define BIT_SHIFT_TSFT_SEL_TIMER0 0
+#define BIT_MASK_TSFT_SEL_TIMER0 0x7
+#define BIT_TSFT_SEL_TIMER0(x) \
+ (((x) & BIT_MASK_TSFT_SEL_TIMER0) << BIT_SHIFT_TSFT_SEL_TIMER0)
+#define BITS_TSFT_SEL_TIMER0 \
+ (BIT_MASK_TSFT_SEL_TIMER0 << BIT_SHIFT_TSFT_SEL_TIMER0)
+#define BIT_CLEAR_TSFT_SEL_TIMER0(x) ((x) & (~BITS_TSFT_SEL_TIMER0))
+#define BIT_GET_TSFT_SEL_TIMER0(x) \
+ (((x) >> BIT_SHIFT_TSFT_SEL_TIMER0) & BIT_MASK_TSFT_SEL_TIMER0)
+#define BIT_SET_TSFT_SEL_TIMER0(x, v) \
+ (BIT_CLEAR_TSFT_SEL_TIMER0(x) | BIT_TSFT_SEL_TIMER0(v))
-#define BIT_SHIFT_NOA_INTERVAL (32 & CPU_OPT_WIDTH)
-#define BIT_MASK_NOA_INTERVAL 0xffffffffL
-#define BIT_NOA_INTERVAL(x) (((x) & BIT_MASK_NOA_INTERVAL) << BIT_SHIFT_NOA_INTERVAL)
-#define BIT_GET_NOA_INTERVAL(x) (((x) >> BIT_SHIFT_NOA_INTERVAL) & BIT_MASK_NOA_INTERVAL)
+/* 2 REG_NOA_UNIT_SEL (Offset 0x05B5) */
+#define BIT_SHIFT_NOA_UNIT2_SEL 8
+#define BIT_MASK_NOA_UNIT2_SEL 0x7
+#define BIT_NOA_UNIT2_SEL(x) \
+ (((x) & BIT_MASK_NOA_UNIT2_SEL) << BIT_SHIFT_NOA_UNIT2_SEL)
+#define BITS_NOA_UNIT2_SEL (BIT_MASK_NOA_UNIT2_SEL << BIT_SHIFT_NOA_UNIT2_SEL)
+#define BIT_CLEAR_NOA_UNIT2_SEL(x) ((x) & (~BITS_NOA_UNIT2_SEL))
+#define BIT_GET_NOA_UNIT2_SEL(x) \
+ (((x) >> BIT_SHIFT_NOA_UNIT2_SEL) & BIT_MASK_NOA_UNIT2_SEL)
+#define BIT_SET_NOA_UNIT2_SEL(x, v) \
+ (BIT_CLEAR_NOA_UNIT2_SEL(x) | BIT_NOA_UNIT2_SEL(v))
+
+#define BIT_SHIFT_NOA_UNIT1_SEL 4
+#define BIT_MASK_NOA_UNIT1_SEL 0x7
+#define BIT_NOA_UNIT1_SEL(x) \
+ (((x) & BIT_MASK_NOA_UNIT1_SEL) << BIT_SHIFT_NOA_UNIT1_SEL)
+#define BITS_NOA_UNIT1_SEL (BIT_MASK_NOA_UNIT1_SEL << BIT_SHIFT_NOA_UNIT1_SEL)
+#define BIT_CLEAR_NOA_UNIT1_SEL(x) ((x) & (~BITS_NOA_UNIT1_SEL))
+#define BIT_GET_NOA_UNIT1_SEL(x) \
+ (((x) >> BIT_SHIFT_NOA_UNIT1_SEL) & BIT_MASK_NOA_UNIT1_SEL)
+#define BIT_SET_NOA_UNIT1_SEL(x, v) \
+ (BIT_CLEAR_NOA_UNIT1_SEL(x) | BIT_NOA_UNIT1_SEL(v))
+
+#define BIT_SHIFT_NOA_UNIT0_SEL 0
+#define BIT_MASK_NOA_UNIT0_SEL 0x7
+#define BIT_NOA_UNIT0_SEL(x) \
+ (((x) & BIT_MASK_NOA_UNIT0_SEL) << BIT_SHIFT_NOA_UNIT0_SEL)
+#define BITS_NOA_UNIT0_SEL (BIT_MASK_NOA_UNIT0_SEL << BIT_SHIFT_NOA_UNIT0_SEL)
+#define BIT_CLEAR_NOA_UNIT0_SEL(x) ((x) & (~BITS_NOA_UNIT0_SEL))
+#define BIT_GET_NOA_UNIT0_SEL(x) \
+ (((x) >> BIT_SHIFT_NOA_UNIT0_SEL) & BIT_MASK_NOA_UNIT0_SEL)
+#define BIT_SET_NOA_UNIT0_SEL(x, v) \
+ (BIT_CLEAR_NOA_UNIT0_SEL(x) | BIT_NOA_UNIT0_SEL(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_NOA_DURATION 0
-#define BIT_MASK_NOA_DURATION 0xffffffffL
-#define BIT_NOA_DURATION(x) (((x) & BIT_MASK_NOA_DURATION) << BIT_SHIFT_NOA_DURATION)
-#define BIT_GET_NOA_DURATION(x) (((x) >> BIT_SHIFT_NOA_DURATION) & BIT_MASK_NOA_DURATION)
+/* 2 REG_P2POFF_DIS_TXTIME (Offset 0x05B7) */
+#define BIT_SHIFT_P2POFF_DIS_TXTIME 0
+#define BIT_MASK_P2POFF_DIS_TXTIME 0xff
+#define BIT_P2POFF_DIS_TXTIME(x) \
+ (((x) & BIT_MASK_P2POFF_DIS_TXTIME) << BIT_SHIFT_P2POFF_DIS_TXTIME)
+#define BITS_P2POFF_DIS_TXTIME \
+ (BIT_MASK_P2POFF_DIS_TXTIME << BIT_SHIFT_P2POFF_DIS_TXTIME)
+#define BIT_CLEAR_P2POFF_DIS_TXTIME(x) ((x) & (~BITS_P2POFF_DIS_TXTIME))
+#define BIT_GET_P2POFF_DIS_TXTIME(x) \
+ (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME) & BIT_MASK_P2POFF_DIS_TXTIME)
+#define BIT_SET_P2POFF_DIS_TXTIME(x, v) \
+ (BIT_CLEAR_P2POFF_DIS_TXTIME(x) | BIT_P2POFF_DIS_TXTIME(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_MBSSID_BCN_SPACE2 (Offset 0x05B8) */
+#define BIT_SHIFT_BCN_SPACE_CLINT2 16
+#define BIT_MASK_BCN_SPACE_CLINT2 0xfff
+#define BIT_BCN_SPACE_CLINT2(x) \
+ (((x) & BIT_MASK_BCN_SPACE_CLINT2) << BIT_SHIFT_BCN_SPACE_CLINT2)
+#define BITS_BCN_SPACE_CLINT2 \
+ (BIT_MASK_BCN_SPACE_CLINT2 << BIT_SHIFT_BCN_SPACE_CLINT2)
+#define BIT_CLEAR_BCN_SPACE_CLINT2(x) ((x) & (~BITS_BCN_SPACE_CLINT2))
+#define BIT_GET_BCN_SPACE_CLINT2(x) \
+ (((x) >> BIT_SHIFT_BCN_SPACE_CLINT2) & BIT_MASK_BCN_SPACE_CLINT2)
+#define BIT_SET_BCN_SPACE_CLINT2(x, v) \
+ (BIT_CLEAR_BCN_SPACE_CLINT2(x) | BIT_BCN_SPACE_CLINT2(v))
+
+#define BIT_SHIFT_BCN_SPACE_CLINT1 0
+#define BIT_MASK_BCN_SPACE_CLINT1 0xfff
+#define BIT_BCN_SPACE_CLINT1(x) \
+ (((x) & BIT_MASK_BCN_SPACE_CLINT1) << BIT_SHIFT_BCN_SPACE_CLINT1)
+#define BITS_BCN_SPACE_CLINT1 \
+ (BIT_MASK_BCN_SPACE_CLINT1 << BIT_SHIFT_BCN_SPACE_CLINT1)
+#define BIT_CLEAR_BCN_SPACE_CLINT1(x) ((x) & (~BITS_BCN_SPACE_CLINT1))
+#define BIT_GET_BCN_SPACE_CLINT1(x) \
+ (((x) >> BIT_SHIFT_BCN_SPACE_CLINT1) & BIT_MASK_BCN_SPACE_CLINT1)
+#define BIT_SET_BCN_SPACE_CLINT1(x, v) \
+ (BIT_CLEAR_BCN_SPACE_CLINT1(x) | BIT_BCN_SPACE_CLINT1(v))
-/* 2 REG_NOA_SUBIE (Offset 0x05ED) */
+/* 2 REG_MBSSID_BCN_SPACE3 (Offset 0x05BC) */
-#define BIT_MORE_NOA_DESC BIT(19)
-#define BIT_NOA_DESC1_VALID BIT(18)
-#define BIT_NOA_DESC0_VALID BIT(17)
-#define BIT_NOA_HEAD_VALID BIT(16)
-#define BIT_NOA_OPP_PS BIT(15)
+#define BIT_SHIFT_SUB_BCN_SPACE 16
+#define BIT_MASK_SUB_BCN_SPACE 0xff
+#define BIT_SUB_BCN_SPACE(x) \
+ (((x) & BIT_MASK_SUB_BCN_SPACE) << BIT_SHIFT_SUB_BCN_SPACE)
+#define BITS_SUB_BCN_SPACE (BIT_MASK_SUB_BCN_SPACE << BIT_SHIFT_SUB_BCN_SPACE)
+#define BIT_CLEAR_SUB_BCN_SPACE(x) ((x) & (~BITS_SUB_BCN_SPACE))
+#define BIT_GET_SUB_BCN_SPACE(x) \
+ (((x) >> BIT_SHIFT_SUB_BCN_SPACE) & BIT_MASK_SUB_BCN_SPACE)
+#define BIT_SET_SUB_BCN_SPACE(x, v) \
+ (BIT_CLEAR_SUB_BCN_SPACE(x) | BIT_SUB_BCN_SPACE(v))
+
+#define BIT_SHIFT_BCN_SPACE_CLINT3 0
+#define BIT_MASK_BCN_SPACE_CLINT3 0xfff
+#define BIT_BCN_SPACE_CLINT3(x) \
+ (((x) & BIT_MASK_BCN_SPACE_CLINT3) << BIT_SHIFT_BCN_SPACE_CLINT3)
+#define BITS_BCN_SPACE_CLINT3 \
+ (BIT_MASK_BCN_SPACE_CLINT3 << BIT_SHIFT_BCN_SPACE_CLINT3)
+#define BIT_CLEAR_BCN_SPACE_CLINT3(x) ((x) & (~BITS_BCN_SPACE_CLINT3))
+#define BIT_GET_BCN_SPACE_CLINT3(x) \
+ (((x) >> BIT_SHIFT_BCN_SPACE_CLINT3) & BIT_MASK_BCN_SPACE_CLINT3)
+#define BIT_SET_BCN_SPACE_CLINT3(x, v) \
+ (BIT_CLEAR_BCN_SPACE_CLINT3(x) | BIT_BCN_SPACE_CLINT3(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_NOA_CTW 8
-#define BIT_MASK_NOA_CTW 0x7f
-#define BIT_NOA_CTW(x) (((x) & BIT_MASK_NOA_CTW) << BIT_SHIFT_NOA_CTW)
-#define BIT_GET_NOA_CTW(x) (((x) >> BIT_SHIFT_NOA_CTW) & BIT_MASK_NOA_CTW)
+/* 2 REG_ACMHWCTRL (Offset 0x05C0) */
+#define BIT_BEQ_ACM_STATUS BIT(7)
+#define BIT_VIQ_ACM_STATUS BIT(6)
+#define BIT_VOQ_ACM_STATUS BIT(5)
+#define BIT_BEQ_ACM_EN BIT(3)
+#define BIT_VIQ_ACM_EN BIT(2)
+#define BIT_VOQ_ACM_EN BIT(1)
+#define BIT_ACMHWEN BIT(0)
-#define BIT_SHIFT_NOA_INDEX 0
-#define BIT_MASK_NOA_INDEX 0xff
-#define BIT_NOA_INDEX(x) (((x) & BIT_MASK_NOA_INDEX) << BIT_SHIFT_NOA_INDEX)
-#define BIT_GET_NOA_INDEX(x) (((x) >> BIT_SHIFT_NOA_INDEX) & BIT_MASK_NOA_INDEX)
+/* 2 REG_ACMRSTCTRL (Offset 0x05C1) */
+#define BIT_BE_ACM_RESET_USED_TIME BIT(2)
+#define BIT_VI_ACM_RESET_USED_TIME BIT(1)
+#define BIT_VO_ACM_RESET_USED_TIME BIT(0)
-#endif
+/* 2 REG_ACMAVG (Offset 0x05C2) */
+#define BIT_SHIFT_AVGPERIOD 0
+#define BIT_MASK_AVGPERIOD 0xffff
+#define BIT_AVGPERIOD(x) (((x) & BIT_MASK_AVGPERIOD) << BIT_SHIFT_AVGPERIOD)
+#define BITS_AVGPERIOD (BIT_MASK_AVGPERIOD << BIT_SHIFT_AVGPERIOD)
+#define BIT_CLEAR_AVGPERIOD(x) ((x) & (~BITS_AVGPERIOD))
+#define BIT_GET_AVGPERIOD(x) (((x) >> BIT_SHIFT_AVGPERIOD) & BIT_MASK_AVGPERIOD)
+#define BIT_SET_AVGPERIOD(x, v) (BIT_CLEAR_AVGPERIOD(x) | BIT_AVGPERIOD(v))
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_VO_ADMTIME (Offset 0x05C4) */
+#define BIT_SHIFT_VO_ADMITTED_TIME 0
+#define BIT_MASK_VO_ADMITTED_TIME 0xffff
+#define BIT_VO_ADMITTED_TIME(x) \
+ (((x) & BIT_MASK_VO_ADMITTED_TIME) << BIT_SHIFT_VO_ADMITTED_TIME)
+#define BITS_VO_ADMITTED_TIME \
+ (BIT_MASK_VO_ADMITTED_TIME << BIT_SHIFT_VO_ADMITTED_TIME)
+#define BIT_CLEAR_VO_ADMITTED_TIME(x) ((x) & (~BITS_VO_ADMITTED_TIME))
+#define BIT_GET_VO_ADMITTED_TIME(x) \
+ (((x) >> BIT_SHIFT_VO_ADMITTED_TIME) & BIT_MASK_VO_ADMITTED_TIME)
+#define BIT_SET_VO_ADMITTED_TIME(x, v) \
+ (BIT_CLEAR_VO_ADMITTED_TIME(x) | BIT_VO_ADMITTED_TIME(v))
-/* 2 REG_P2P_RST (Offset 0x05F0) */
+/* 2 REG_VI_ADMTIME (Offset 0x05C6) */
-#define BIT_P2P2_PWR_RST1 BIT(5)
-#define BIT_P2P2_PWR_RST0 BIT(4)
-#define BIT_P2P1_PWR_RST1 BIT(3)
-#define BIT_P2P1_PWR_RST0 BIT(2)
-#define BIT_P2P_PWR_RST1_V1 BIT(1)
-#define BIT_P2P_PWR_RST0_V1 BIT(0)
+#define BIT_SHIFT_VI_ADMITTED_TIME 0
+#define BIT_MASK_VI_ADMITTED_TIME 0xffff
+#define BIT_VI_ADMITTED_TIME(x) \
+ (((x) & BIT_MASK_VI_ADMITTED_TIME) << BIT_SHIFT_VI_ADMITTED_TIME)
+#define BITS_VI_ADMITTED_TIME \
+ (BIT_MASK_VI_ADMITTED_TIME << BIT_SHIFT_VI_ADMITTED_TIME)
+#define BIT_CLEAR_VI_ADMITTED_TIME(x) ((x) & (~BITS_VI_ADMITTED_TIME))
+#define BIT_GET_VI_ADMITTED_TIME(x) \
+ (((x) >> BIT_SHIFT_VI_ADMITTED_TIME) & BIT_MASK_VI_ADMITTED_TIME)
+#define BIT_SET_VI_ADMITTED_TIME(x, v) \
+ (BIT_CLEAR_VI_ADMITTED_TIME(x) | BIT_VI_ADMITTED_TIME(v))
-#endif
+/* 2 REG_BE_ADMTIME (Offset 0x05C8) */
+#define BIT_SHIFT_BE_ADMITTED_TIME 0
+#define BIT_MASK_BE_ADMITTED_TIME 0xffff
+#define BIT_BE_ADMITTED_TIME(x) \
+ (((x) & BIT_MASK_BE_ADMITTED_TIME) << BIT_SHIFT_BE_ADMITTED_TIME)
+#define BITS_BE_ADMITTED_TIME \
+ (BIT_MASK_BE_ADMITTED_TIME << BIT_SHIFT_BE_ADMITTED_TIME)
+#define BIT_CLEAR_BE_ADMITTED_TIME(x) ((x) & (~BITS_BE_ADMITTED_TIME))
+#define BIT_GET_BE_ADMITTED_TIME(x) \
+ (((x) >> BIT_SHIFT_BE_ADMITTED_TIME) & BIT_MASK_BE_ADMITTED_TIME)
+#define BIT_SET_BE_ADMITTED_TIME(x, v) \
+ (BIT_CLEAR_BE_ADMITTED_TIME(x) | BIT_BE_ADMITTED_TIME(v))
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_SCHEDULER_RST (Offset 0x05F1) */
+/* 2 REG_MAC_HEADER_NAV_OFFSET (Offset 0x05CA) */
-#define BIT_STOP_CPUMGQ BIT(16)
-#define BIT_SYNC_TSF_NOW BIT(2)
+#define BIT_SHIFT_MAC_HEADER_NAV_OFFSET 0
+#define BIT_MASK_MAC_HEADER_NAV_OFFSET 0xff
+#define BIT_MAC_HEADER_NAV_OFFSET(x) \
+ (((x) & BIT_MASK_MAC_HEADER_NAV_OFFSET) \
+ << BIT_SHIFT_MAC_HEADER_NAV_OFFSET)
+#define BITS_MAC_HEADER_NAV_OFFSET \
+ (BIT_MASK_MAC_HEADER_NAV_OFFSET << BIT_SHIFT_MAC_HEADER_NAV_OFFSET)
+#define BIT_CLEAR_MAC_HEADER_NAV_OFFSET(x) ((x) & (~BITS_MAC_HEADER_NAV_OFFSET))
+#define BIT_GET_MAC_HEADER_NAV_OFFSET(x) \
+ (((x) >> BIT_SHIFT_MAC_HEADER_NAV_OFFSET) & \
+ BIT_MASK_MAC_HEADER_NAV_OFFSET)
+#define BIT_SET_MAC_HEADER_NAV_OFFSET(x, v) \
+ (BIT_CLEAR_MAC_HEADER_NAV_OFFSET(x) | BIT_MAC_HEADER_NAV_OFFSET(v))
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_SCHEDULER_RST (Offset 0x05F1) */
+/* 2 REG_DIS_NDPA_NAV_CHECK (Offset 0x05CB) */
-#define BIT_SYNC_CLI BIT(1)
-#define BIT_SCHEDULER_RST_V1 BIT(0)
+#define BIT_CHG_POWER_BCN_AREA_V1 BIT(1)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_DIS_NDPA_NAV_CHECK (Offset 0x05CB) */
+#define BIT_DIS_NDPA_NAV_CHECK BIT(0)
-/* 2 REG_SCHEDULER_RST (Offset 0x05F1) */
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+/* 2 REG_EDCA_RANDOM_GEN (Offset 0x05CC) */
-#define BIT_SHIFT_CPUMGQ_PARAMETER 0
-#define BIT_MASK_CPUMGQ_PARAMETER 0xffff
-#define BIT_CPUMGQ_PARAMETER(x) (((x) & BIT_MASK_CPUMGQ_PARAMETER) << BIT_SHIFT_CPUMGQ_PARAMETER)
-#define BIT_GET_CPUMGQ_PARAMETER(x) (((x) >> BIT_SHIFT_CPUMGQ_PARAMETER) & BIT_MASK_CPUMGQ_PARAMETER)
+#define BIT_SHIFT_RANDOM_GEN 0
+#define BIT_MASK_RANDOM_GEN 0xffffff
+#define BIT_RANDOM_GEN(x) (((x) & BIT_MASK_RANDOM_GEN) << BIT_SHIFT_RANDOM_GEN)
+#define BITS_RANDOM_GEN (BIT_MASK_RANDOM_GEN << BIT_SHIFT_RANDOM_GEN)
+#define BIT_CLEAR_RANDOM_GEN(x) ((x) & (~BITS_RANDOM_GEN))
+#define BIT_GET_RANDOM_GEN(x) \
+ (((x) >> BIT_SHIFT_RANDOM_GEN) & BIT_MASK_RANDOM_GEN)
+#define BIT_SET_RANDOM_GEN(x, v) (BIT_CLEAR_RANDOM_GEN(x) | BIT_RANDOM_GEN(v))
+#define BIT_SHIFT_TXCMD_SEG_SEL 0
+#define BIT_MASK_TXCMD_SEG_SEL 0xf
+#define BIT_TXCMD_SEG_SEL(x) \
+ (((x) & BIT_MASK_TXCMD_SEG_SEL) << BIT_SHIFT_TXCMD_SEG_SEL)
+#define BITS_TXCMD_SEG_SEL (BIT_MASK_TXCMD_SEG_SEL << BIT_SHIFT_TXCMD_SEG_SEL)
+#define BIT_CLEAR_TXCMD_SEG_SEL(x) ((x) & (~BITS_TXCMD_SEG_SEL))
+#define BIT_GET_TXCMD_SEG_SEL(x) \
+ (((x) >> BIT_SHIFT_TXCMD_SEG_SEL) & BIT_MASK_TXCMD_SEG_SEL)
+#define BIT_SET_TXCMD_SEG_SEL(x, v) \
+ (BIT_CLEAR_TXCMD_SEG_SEL(x) | BIT_TXCMD_SEG_SEL(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_TXCMD_NOA_SEL (Offset 0x05CF) */
+#define BIT_NOA_SEL BIT(4)
-/* 2 REG_SCH_TXCMD (Offset 0x05F8) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_SCH_TXCMD 0
-#define BIT_MASK_SCH_TXCMD 0xffffffffL
-#define BIT_SCH_TXCMD(x) (((x) & BIT_MASK_SCH_TXCMD) << BIT_SHIFT_SCH_TXCMD)
-#define BIT_GET_SCH_TXCMD(x) (((x) >> BIT_SHIFT_SCH_TXCMD) & BIT_MASK_SCH_TXCMD)
+/* 2 REG_TXCMD_NOA_SEL (Offset 0x05CF) */
+#define BIT_SHIFT_NOA_SEL_V2 4
+#define BIT_MASK_NOA_SEL_V2 0x7
+#define BIT_NOA_SEL_V2(x) (((x) & BIT_MASK_NOA_SEL_V2) << BIT_SHIFT_NOA_SEL_V2)
+#define BITS_NOA_SEL_V2 (BIT_MASK_NOA_SEL_V2 << BIT_SHIFT_NOA_SEL_V2)
+#define BIT_CLEAR_NOA_SEL_V2(x) ((x) & (~BITS_NOA_SEL_V2))
+#define BIT_GET_NOA_SEL_V2(x) \
+ (((x) >> BIT_SHIFT_NOA_SEL_V2) & BIT_MASK_NOA_SEL_V2)
+#define BIT_SET_NOA_SEL_V2(x, v) (BIT_CLEAR_NOA_SEL_V2(x) | BIT_NOA_SEL_V2(v))
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+/* 2 REG_32K_CLK_SEL (Offset 0x05D0) */
+
+#define BIT_R_BCNERR_CNT_EN BIT(20)
+
+#define BIT_SHIFT_R_BCNERR_PORT_SEL 16
+#define BIT_MASK_R_BCNERR_PORT_SEL 0x7
+#define BIT_R_BCNERR_PORT_SEL(x) \
+ (((x) & BIT_MASK_R_BCNERR_PORT_SEL) << BIT_SHIFT_R_BCNERR_PORT_SEL)
+#define BITS_R_BCNERR_PORT_SEL \
+ (BIT_MASK_R_BCNERR_PORT_SEL << BIT_SHIFT_R_BCNERR_PORT_SEL)
+#define BIT_CLEAR_R_BCNERR_PORT_SEL(x) ((x) & (~BITS_R_BCNERR_PORT_SEL))
+#define BIT_GET_R_BCNERR_PORT_SEL(x) \
+ (((x) >> BIT_SHIFT_R_BCNERR_PORT_SEL) & BIT_MASK_R_BCNERR_PORT_SEL)
+#define BIT_SET_R_BCNERR_PORT_SEL(x, v) \
+ (BIT_CLEAR_R_BCNERR_PORT_SEL(x) | BIT_R_BCNERR_PORT_SEL(v))
+
+#define BIT_SHIFT_R_TXPAUSE1 8
+#define BIT_MASK_R_TXPAUSE1 0xff
+#define BIT_R_TXPAUSE1(x) (((x) & BIT_MASK_R_TXPAUSE1) << BIT_SHIFT_R_TXPAUSE1)
+#define BITS_R_TXPAUSE1 (BIT_MASK_R_TXPAUSE1 << BIT_SHIFT_R_TXPAUSE1)
+#define BIT_CLEAR_R_TXPAUSE1(x) ((x) & (~BITS_R_TXPAUSE1))
+#define BIT_GET_R_TXPAUSE1(x) \
+ (((x) >> BIT_SHIFT_R_TXPAUSE1) & BIT_MASK_R_TXPAUSE1)
+#define BIT_SET_R_TXPAUSE1(x, v) (BIT_CLEAR_R_TXPAUSE1(x) | BIT_R_TXPAUSE1(v))
+
+#define BIT_SLEEP_32K_EN_V1 BIT(2)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_EARLYINT_ADJUST (Offset 0x05D4) */
+
+#define BIT_SHIFT_RXBCN_TIMER 16
+#define BIT_MASK_RXBCN_TIMER 0xffff
+#define BIT_RXBCN_TIMER(x) \
+ (((x) & BIT_MASK_RXBCN_TIMER) << BIT_SHIFT_RXBCN_TIMER)
+#define BITS_RXBCN_TIMER (BIT_MASK_RXBCN_TIMER << BIT_SHIFT_RXBCN_TIMER)
+#define BIT_CLEAR_RXBCN_TIMER(x) ((x) & (~BITS_RXBCN_TIMER))
+#define BIT_GET_RXBCN_TIMER(x) \
+ (((x) >> BIT_SHIFT_RXBCN_TIMER) & BIT_MASK_RXBCN_TIMER)
+#define BIT_SET_RXBCN_TIMER(x, v) \
+ (BIT_CLEAR_RXBCN_TIMER(x) | BIT_RXBCN_TIMER(v))
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+/* 2 REG_EARLYINT_ADJUST (Offset 0x05D4) */
+
+#define BIT_SHIFT_R_ERLYINTADJ 0
+#define BIT_MASK_R_ERLYINTADJ 0xffff
+#define BIT_R_ERLYINTADJ(x) \
+ (((x) & BIT_MASK_R_ERLYINTADJ) << BIT_SHIFT_R_ERLYINTADJ)
+#define BITS_R_ERLYINTADJ (BIT_MASK_R_ERLYINTADJ << BIT_SHIFT_R_ERLYINTADJ)
+#define BIT_CLEAR_R_ERLYINTADJ(x) ((x) & (~BITS_R_ERLYINTADJ))
+#define BIT_GET_R_ERLYINTADJ(x) \
+ (((x) >> BIT_SHIFT_R_ERLYINTADJ) & BIT_MASK_R_ERLYINTADJ)
+#define BIT_SET_R_ERLYINTADJ(x, v) \
+ (BIT_CLEAR_R_ERLYINTADJ(x) | BIT_R_ERLYINTADJ(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BCNERR_CNT (Offset 0x05D8) */
+
+#define BIT_SHIFT_BCNERR_CNT_OTHERS 24
+#define BIT_MASK_BCNERR_CNT_OTHERS 0xff
+#define BIT_BCNERR_CNT_OTHERS(x) \
+ (((x) & BIT_MASK_BCNERR_CNT_OTHERS) << BIT_SHIFT_BCNERR_CNT_OTHERS)
+#define BITS_BCNERR_CNT_OTHERS \
+ (BIT_MASK_BCNERR_CNT_OTHERS << BIT_SHIFT_BCNERR_CNT_OTHERS)
+#define BIT_CLEAR_BCNERR_CNT_OTHERS(x) ((x) & (~BITS_BCNERR_CNT_OTHERS))
+#define BIT_GET_BCNERR_CNT_OTHERS(x) \
+ (((x) >> BIT_SHIFT_BCNERR_CNT_OTHERS) & BIT_MASK_BCNERR_CNT_OTHERS)
+#define BIT_SET_BCNERR_CNT_OTHERS(x, v) \
+ (BIT_CLEAR_BCNERR_CNT_OTHERS(x) | BIT_BCNERR_CNT_OTHERS(v))
+
+#define BIT_SHIFT_BCNERR_CNT_INVALID 16
+#define BIT_MASK_BCNERR_CNT_INVALID 0xff
+#define BIT_BCNERR_CNT_INVALID(x) \
+ (((x) & BIT_MASK_BCNERR_CNT_INVALID) << BIT_SHIFT_BCNERR_CNT_INVALID)
+#define BITS_BCNERR_CNT_INVALID \
+ (BIT_MASK_BCNERR_CNT_INVALID << BIT_SHIFT_BCNERR_CNT_INVALID)
+#define BIT_CLEAR_BCNERR_CNT_INVALID(x) ((x) & (~BITS_BCNERR_CNT_INVALID))
+#define BIT_GET_BCNERR_CNT_INVALID(x) \
+ (((x) >> BIT_SHIFT_BCNERR_CNT_INVALID) & BIT_MASK_BCNERR_CNT_INVALID)
+#define BIT_SET_BCNERR_CNT_INVALID(x, v) \
+ (BIT_CLEAR_BCNERR_CNT_INVALID(x) | BIT_BCNERR_CNT_INVALID(v))
+
+#define BIT_SHIFT_BCNERR_CNT_MAC 8
+#define BIT_MASK_BCNERR_CNT_MAC 0xff
+#define BIT_BCNERR_CNT_MAC(x) \
+ (((x) & BIT_MASK_BCNERR_CNT_MAC) << BIT_SHIFT_BCNERR_CNT_MAC)
+#define BITS_BCNERR_CNT_MAC \
+ (BIT_MASK_BCNERR_CNT_MAC << BIT_SHIFT_BCNERR_CNT_MAC)
+#define BIT_CLEAR_BCNERR_CNT_MAC(x) ((x) & (~BITS_BCNERR_CNT_MAC))
+#define BIT_GET_BCNERR_CNT_MAC(x) \
+ (((x) >> BIT_SHIFT_BCNERR_CNT_MAC) & BIT_MASK_BCNERR_CNT_MAC)
+#define BIT_SET_BCNERR_CNT_MAC(x, v) \
+ (BIT_CLEAR_BCNERR_CNT_MAC(x) | BIT_BCNERR_CNT_MAC(v))
+
+#define BIT_SHIFT_BCNERR_CNT_CCA 0
+#define BIT_MASK_BCNERR_CNT_CCA 0xff
+#define BIT_BCNERR_CNT_CCA(x) \
+ (((x) & BIT_MASK_BCNERR_CNT_CCA) << BIT_SHIFT_BCNERR_CNT_CCA)
+#define BITS_BCNERR_CNT_CCA \
+ (BIT_MASK_BCNERR_CNT_CCA << BIT_SHIFT_BCNERR_CNT_CCA)
+#define BIT_CLEAR_BCNERR_CNT_CCA(x) ((x) & (~BITS_BCNERR_CNT_CCA))
+#define BIT_GET_BCNERR_CNT_CCA(x) \
+ (((x) >> BIT_SHIFT_BCNERR_CNT_CCA) & BIT_MASK_BCNERR_CNT_CCA)
+#define BIT_SET_BCNERR_CNT_CCA(x, v) \
+ (BIT_CLEAR_BCNERR_CNT_CCA(x) | BIT_BCNERR_CNT_CCA(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_NOA_PARAM (Offset 0x05E0) */
+#define BIT_SHIFT_NOA_COUNT (96 & CPU_OPT_WIDTH)
+#define BIT_MASK_NOA_COUNT 0xff
+#define BIT_NOA_COUNT(x) (((x) & BIT_MASK_NOA_COUNT) << BIT_SHIFT_NOA_COUNT)
+#define BITS_NOA_COUNT (BIT_MASK_NOA_COUNT << BIT_SHIFT_NOA_COUNT)
+#define BIT_CLEAR_NOA_COUNT(x) ((x) & (~BITS_NOA_COUNT))
+#define BIT_GET_NOA_COUNT(x) (((x) >> BIT_SHIFT_NOA_COUNT) & BIT_MASK_NOA_COUNT)
+#define BIT_SET_NOA_COUNT(x, v) (BIT_CLEAR_NOA_COUNT(x) | BIT_NOA_COUNT(v))
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_WMAC_CR (Offset 0x0600) */
+/* 2 REG_NOA_PARAM (Offset 0x05E0) */
-#define BIT_APSDOFF_STATUS BIT(7)
+#define BIT_SHIFT_NOA_DURATION 0
+#define BIT_MASK_NOA_DURATION 0xffffffffL
+#define BIT_NOA_DURATION(x) \
+ (((x) & BIT_MASK_NOA_DURATION) << BIT_SHIFT_NOA_DURATION)
+#define BITS_NOA_DURATION (BIT_MASK_NOA_DURATION << BIT_SHIFT_NOA_DURATION)
+#define BIT_CLEAR_NOA_DURATION(x) ((x) & (~BITS_NOA_DURATION))
+#define BIT_GET_NOA_DURATION(x) \
+ (((x) >> BIT_SHIFT_NOA_DURATION) & BIT_MASK_NOA_DURATION)
+#define BIT_SET_NOA_DURATION(x, v) \
+ (BIT_CLEAR_NOA_DURATION(x) | BIT_NOA_DURATION(v))
#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_NOA_PARAM (Offset 0x05E0) */
+#define BIT_SHIFT_NOA_DURATION_V1 0
+#define BIT_MASK_NOA_DURATION_V1 0xffffffffL
+#define BIT_NOA_DURATION_V1(x) \
+ (((x) & BIT_MASK_NOA_DURATION_V1) << BIT_SHIFT_NOA_DURATION_V1)
+#define BITS_NOA_DURATION_V1 \
+ (BIT_MASK_NOA_DURATION_V1 << BIT_SHIFT_NOA_DURATION_V1)
+#define BIT_CLEAR_NOA_DURATION_V1(x) ((x) & (~BITS_NOA_DURATION_V1))
+#define BIT_GET_NOA_DURATION_V1(x) \
+ (((x) >> BIT_SHIFT_NOA_DURATION_V1) & BIT_MASK_NOA_DURATION_V1)
+#define BIT_SET_NOA_DURATION_V1(x, v) \
+ (BIT_CLEAR_NOA_DURATION_V1(x) | BIT_NOA_DURATION_V1(v))
-/* 2 REG_WMAC_CR (Offset 0x0600) */
+/* 2 REG_NOA_PARAM_1 (Offset 0x05E4) */
-#define BIT_APSDOFF BIT(6)
+#define BIT_SHIFT_NOA_INTERVAL_V1 0
+#define BIT_MASK_NOA_INTERVAL_V1 0xffffffffL
+#define BIT_NOA_INTERVAL_V1(x) \
+ (((x) & BIT_MASK_NOA_INTERVAL_V1) << BIT_SHIFT_NOA_INTERVAL_V1)
+#define BITS_NOA_INTERVAL_V1 \
+ (BIT_MASK_NOA_INTERVAL_V1 << BIT_SHIFT_NOA_INTERVAL_V1)
+#define BIT_CLEAR_NOA_INTERVAL_V1(x) ((x) & (~BITS_NOA_INTERVAL_V1))
+#define BIT_GET_NOA_INTERVAL_V1(x) \
+ (((x) >> BIT_SHIFT_NOA_INTERVAL_V1) & BIT_MASK_NOA_INTERVAL_V1)
+#define BIT_SET_NOA_INTERVAL_V1(x, v) \
+ (BIT_CLEAR_NOA_INTERVAL_V1(x) | BIT_NOA_INTERVAL_V1(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
-
-/* 2 REG_WMAC_CR (Offset 0x0600) */
+/* 2 REG_MU_DBG_INFO (Offset 0x05E8) */
-#define BIT_STANDBY_STATUS BIT(5)
+#define BIT_SHIFT_MU_DBG_INFO 0
+#define BIT_MASK_MU_DBG_INFO 0xffffffffL
+#define BIT_MU_DBG_INFO(x) \
+ (((x) & BIT_MASK_MU_DBG_INFO) << BIT_SHIFT_MU_DBG_INFO)
+#define BITS_MU_DBG_INFO (BIT_MASK_MU_DBG_INFO << BIT_SHIFT_MU_DBG_INFO)
+#define BIT_CLEAR_MU_DBG_INFO(x) ((x) & (~BITS_MU_DBG_INFO))
+#define BIT_GET_MU_DBG_INFO(x) \
+ (((x) >> BIT_SHIFT_MU_DBG_INFO) & BIT_MASK_MU_DBG_INFO)
+#define BIT_SET_MU_DBG_INFO(x, v) \
+ (BIT_CLEAR_MU_DBG_INFO(x) | BIT_MU_DBG_INFO(v))
#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_NOA_PARAM_2 (Offset 0x05E8) */
+#define BIT_SHIFT_NOA_START_TIME_V1 0
+#define BIT_MASK_NOA_START_TIME_V1 0xffffffffL
+#define BIT_NOA_START_TIME_V1(x) \
+ (((x) & BIT_MASK_NOA_START_TIME_V1) << BIT_SHIFT_NOA_START_TIME_V1)
+#define BITS_NOA_START_TIME_V1 \
+ (BIT_MASK_NOA_START_TIME_V1 << BIT_SHIFT_NOA_START_TIME_V1)
+#define BIT_CLEAR_NOA_START_TIME_V1(x) ((x) & (~BITS_NOA_START_TIME_V1))
+#define BIT_GET_NOA_START_TIME_V1(x) \
+ (((x) >> BIT_SHIFT_NOA_START_TIME_V1) & BIT_MASK_NOA_START_TIME_V1)
+#define BIT_SET_NOA_START_TIME_V1(x, v) \
+ (BIT_CLEAR_NOA_START_TIME_V1(x) | BIT_NOA_START_TIME_V1(v))
-/* 2 REG_WMAC_CR (Offset 0x0600) */
+#endif
-#define BIT_IC_MACPHY_M BIT(0)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_MU_DBG_INFO_1 (Offset 0x05EC) */
+#define BIT_SHIFT_MU_DBG_INFO_1 0
+#define BIT_MASK_MU_DBG_INFO_1 0xffffffffL
+#define BIT_MU_DBG_INFO_1(x) \
+ (((x) & BIT_MASK_MU_DBG_INFO_1) << BIT_SHIFT_MU_DBG_INFO_1)
+#define BITS_MU_DBG_INFO_1 (BIT_MASK_MU_DBG_INFO_1 << BIT_SHIFT_MU_DBG_INFO_1)
+#define BIT_CLEAR_MU_DBG_INFO_1(x) ((x) & (~BITS_MU_DBG_INFO_1))
+#define BIT_GET_MU_DBG_INFO_1(x) \
+ (((x) >> BIT_SHIFT_MU_DBG_INFO_1) & BIT_MASK_MU_DBG_INFO_1)
+#define BIT_SET_MU_DBG_INFO_1(x, v) \
+ (BIT_CLEAR_MU_DBG_INFO_1(x) | BIT_MU_DBG_INFO_1(v))
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_WMAC_FWPKT_CR (Offset 0x0601) */
+/* 2 REG_NOA_PARAM_3 (Offset 0x05EC) */
-#define BIT_FWEN BIT(7)
+#define BIT_SHIFT_NOA_COUNT_V1 0
+#define BIT_MASK_NOA_COUNT_V1 0xffffffffL
+#define BIT_NOA_COUNT_V1(x) \
+ (((x) & BIT_MASK_NOA_COUNT_V1) << BIT_SHIFT_NOA_COUNT_V1)
+#define BITS_NOA_COUNT_V1 (BIT_MASK_NOA_COUNT_V1 << BIT_SHIFT_NOA_COUNT_V1)
+#define BIT_CLEAR_NOA_COUNT_V1(x) ((x) & (~BITS_NOA_COUNT_V1))
+#define BIT_GET_NOA_COUNT_V1(x) \
+ (((x) >> BIT_SHIFT_NOA_COUNT_V1) & BIT_MASK_NOA_COUNT_V1)
+#define BIT_SET_NOA_COUNT_V1(x, v) \
+ (BIT_CLEAR_NOA_COUNT_V1(x) | BIT_NOA_COUNT_V1(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_NOA_SUBIE (Offset 0x05ED) */
+#define BIT_MORE_NOA_DESC BIT(19)
+#define BIT_NOA_DESC1_VALID BIT(18)
+#define BIT_NOA_DESC0_VALID BIT(17)
+#define BIT_NOA_HEAD_VALID BIT(16)
+#define BIT_NOA_OPP_PS BIT(15)
-/* 2 REG_WMAC_FWPKT_CR (Offset 0x0601) */
+#define BIT_SHIFT_NOA_CTW 8
+#define BIT_MASK_NOA_CTW 0x7f
+#define BIT_NOA_CTW(x) (((x) & BIT_MASK_NOA_CTW) << BIT_SHIFT_NOA_CTW)
+#define BITS_NOA_CTW (BIT_MASK_NOA_CTW << BIT_SHIFT_NOA_CTW)
+#define BIT_CLEAR_NOA_CTW(x) ((x) & (~BITS_NOA_CTW))
+#define BIT_GET_NOA_CTW(x) (((x) >> BIT_SHIFT_NOA_CTW) & BIT_MASK_NOA_CTW)
+#define BIT_SET_NOA_CTW(x, v) (BIT_CLEAR_NOA_CTW(x) | BIT_NOA_CTW(v))
-#define BIT_PHYSTS_PKT_CTRL BIT(6)
+#define BIT_SHIFT_NOA_INDEX 0
+#define BIT_MASK_NOA_INDEX 0xff
+#define BIT_NOA_INDEX(x) (((x) & BIT_MASK_NOA_INDEX) << BIT_SHIFT_NOA_INDEX)
+#define BITS_NOA_INDEX (BIT_MASK_NOA_INDEX << BIT_SHIFT_NOA_INDEX)
+#define BIT_CLEAR_NOA_INDEX(x) ((x) & (~BITS_NOA_INDEX))
+#define BIT_GET_NOA_INDEX(x) (((x) >> BIT_SHIFT_NOA_INDEX) & BIT_MASK_NOA_INDEX)
+#define BIT_SET_NOA_INDEX(x, v) (BIT_CLEAR_NOA_INDEX(x) | BIT_NOA_INDEX(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_P2P_RST (Offset 0x05F0) */
+#define BIT_P2P2_PWR_RST1 BIT(5)
+#define BIT_P2P2_PWR_RST0 BIT(4)
+#define BIT_P2P1_PWR_RST1 BIT(3)
+#define BIT_P2P1_PWR_RST0 BIT(2)
+#define BIT_P2P_PWR_RST1_V1 BIT(1)
+#define BIT_P2P_PWR_RST0_V1 BIT(0)
-/* 2 REG_WMAC_FWPKT_CR (Offset 0x0601) */
+#endif
-#define BIT_APPHDR_MIDSRCH_FAIL BIT(4)
-#define BIT_FWPARSING_EN BIT(3)
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_APPEND_MHDR_LEN 0
-#define BIT_MASK_APPEND_MHDR_LEN 0x7
-#define BIT_APPEND_MHDR_LEN(x) (((x) & BIT_MASK_APPEND_MHDR_LEN) << BIT_SHIFT_APPEND_MHDR_LEN)
-#define BIT_GET_APPEND_MHDR_LEN(x) (((x) >> BIT_SHIFT_APPEND_MHDR_LEN) & BIT_MASK_APPEND_MHDR_LEN)
+/* 2 REG_SCH_DBG_SEL (Offset 0x05F0) */
+#define BIT_SHIFT_SCH_DBG_SEL 0
+#define BIT_MASK_SCH_DBG_SEL 0xff
+#define BIT_SCH_DBG_SEL(x) \
+ (((x) & BIT_MASK_SCH_DBG_SEL) << BIT_SHIFT_SCH_DBG_SEL)
+#define BITS_SCH_DBG_SEL (BIT_MASK_SCH_DBG_SEL << BIT_SHIFT_SCH_DBG_SEL)
+#define BIT_CLEAR_SCH_DBG_SEL(x) ((x) & (~BITS_SCH_DBG_SEL))
+#define BIT_GET_SCH_DBG_SEL(x) \
+ (((x) >> BIT_SHIFT_SCH_DBG_SEL) & BIT_MASK_SCH_DBG_SEL)
+#define BIT_SET_SCH_DBG_SEL(x, v) \
+ (BIT_CLEAR_SCH_DBG_SEL(x) | BIT_SCH_DBG_SEL(v))
#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT)
+/* 2 REG_SCHEDULER_RST (Offset 0x05F1) */
+#define BIT_MAC_STOP_CPUMGQ BIT(16)
-/* 2 REG_FW_STS_FILTER (Offset 0x0602) */
+#endif
-#define BIT_DATA_FW_STS_FILTER BIT(2)
-#define BIT_CTRL_FW_STS_FILTER BIT(1)
-#define BIT_MGNT_FW_STS_FILTER BIT(0)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#endif
+/* 2 REG_SCHEDULER_RST (Offset 0x05F1) */
+#define BIT_SYNC_TSF_NOW BIT(2)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_TCR (Offset 0x0604) */
+/* 2 REG_SCHEDULER_RST (Offset 0x05F1) */
-#define BIT_WMAC_EN_RTS_ADDR BIT(31)
-#define BIT_WMAC_DISABLE_CCK BIT(30)
-#define BIT_WMAC_RAW_LEN BIT(29)
-#define BIT_WMAC_NOTX_IN_RXNDP BIT(28)
-#define BIT_WMAC_EN_EOF BIT(27)
-#define BIT_WMAC_BF_SEL BIT(26)
-#define BIT_WMAC_ANTMODE_SEL BIT(25)
+#define BIT_SYNC_CLI_ONCE_RIGHT_NOW BIT(2)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_SCHEDULER_RST (Offset 0x05F1) */
+#define BIT_SYNC_CLI BIT(1)
-/* 2 REG_TCR (Offset 0x0604) */
+#endif
-#define BIT_WMAC_TCRPWRMGT_HWCTL BIT(24)
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_SCHEDULER_RST (Offset 0x05F1) */
+#define BIT_SYNC_CLI_ONCE_BY_TBTT BIT(1)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_TCR (Offset 0x0604) */
+/* 2 REG_SCHEDULER_RST (Offset 0x05F1) */
-#define BIT_RXLEN_SEL BIT(24)
+#define BIT_SCHEDULER_RST_V1 BIT(0)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_MU_DBG_ERR_FLAG (Offset 0x05F2) */
+#define BIT_BCN_PORTID_ERR BIT(2)
-/* 2 REG_TCR (Offset 0x0604) */
+#define BIT_SHIFT_MU_DBG_ERR_FLAG 0
+#define BIT_MASK_MU_DBG_ERR_FLAG 0x3
+#define BIT_MU_DBG_ERR_FLAG(x) \
+ (((x) & BIT_MASK_MU_DBG_ERR_FLAG) << BIT_SHIFT_MU_DBG_ERR_FLAG)
+#define BITS_MU_DBG_ERR_FLAG \
+ (BIT_MASK_MU_DBG_ERR_FLAG << BIT_SHIFT_MU_DBG_ERR_FLAG)
+#define BIT_CLEAR_MU_DBG_ERR_FLAG(x) ((x) & (~BITS_MU_DBG_ERR_FLAG))
+#define BIT_GET_MU_DBG_ERR_FLAG(x) \
+ (((x) >> BIT_SHIFT_MU_DBG_ERR_FLAG) & BIT_MASK_MU_DBG_ERR_FLAG)
+#define BIT_SET_MU_DBG_ERR_FLAG(x, v) \
+ (BIT_CLEAR_MU_DBG_ERR_FLAG(x) | BIT_MU_DBG_ERR_FLAG(v))
-#define BIT_WMAC_SMOOTH_VAL BIT(23)
+/* 2 REG_TX_ERR_RECOVERY_RST (Offset 0x05F3) */
-#endif
+#define BIT_SHIFT_ERR_RECOVER_CNT 4
+#define BIT_MASK_ERR_RECOVER_CNT 0xf
+#define BIT_ERR_RECOVER_CNT(x) \
+ (((x) & BIT_MASK_ERR_RECOVER_CNT) << BIT_SHIFT_ERR_RECOVER_CNT)
+#define BITS_ERR_RECOVER_CNT \
+ (BIT_MASK_ERR_RECOVER_CNT << BIT_SHIFT_ERR_RECOVER_CNT)
+#define BIT_CLEAR_ERR_RECOVER_CNT(x) ((x) & (~BITS_ERR_RECOVER_CNT))
+#define BIT_GET_ERR_RECOVER_CNT(x) \
+ (((x) >> BIT_SHIFT_ERR_RECOVER_CNT) & BIT_MASK_ERR_RECOVER_CNT)
+#define BIT_SET_ERR_RECOVER_CNT(x, v) \
+ (BIT_CLEAR_ERR_RECOVER_CNT(x) | BIT_ERR_RECOVER_CNT(v))
+#define BIT_RX_HANG_ERR BIT(2)
+#define BIT_TX_HANG_ERR BIT(1)
+#define BIT_TX_ERR_RECOVERY_RST BIT(0)
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_TCR (Offset 0x0604) */
+/* 2 REG_SCH_DBG_VALUE (Offset 0x05F4) */
-#define BIT_UNDERFLOWEN_CMPLEN_SEL BIT(21)
+#define BIT_SHIFT_SCH_DBG_VALUE 0
+#define BIT_MASK_SCH_DBG_VALUE 0xffffffffL
+#define BIT_SCH_DBG_VALUE(x) \
+ (((x) & BIT_MASK_SCH_DBG_VALUE) << BIT_SHIFT_SCH_DBG_VALUE)
+#define BITS_SCH_DBG_VALUE (BIT_MASK_SCH_DBG_VALUE << BIT_SHIFT_SCH_DBG_VALUE)
+#define BIT_CLEAR_SCH_DBG_VALUE(x) ((x) & (~BITS_SCH_DBG_VALUE))
+#define BIT_GET_SCH_DBG_VALUE(x) \
+ (((x) >> BIT_SHIFT_SCH_DBG_VALUE) & BIT_MASK_SCH_DBG_VALUE)
+#define BIT_SET_SCH_DBG_VALUE(x, v) \
+ (BIT_CLEAR_SCH_DBG_VALUE(x) | BIT_SCH_DBG_VALUE(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_SCH_TXCMD (Offset 0x05F8) */
+#define BIT_SHIFT_SCH_TXCMD 0
+#define BIT_MASK_SCH_TXCMD 0xffffffffL
+#define BIT_SCH_TXCMD(x) (((x) & BIT_MASK_SCH_TXCMD) << BIT_SHIFT_SCH_TXCMD)
+#define BITS_SCH_TXCMD (BIT_MASK_SCH_TXCMD << BIT_SHIFT_SCH_TXCMD)
+#define BIT_CLEAR_SCH_TXCMD(x) ((x) & (~BITS_SCH_TXCMD))
+#define BIT_GET_SCH_TXCMD(x) (((x) >> BIT_SHIFT_SCH_TXCMD) & BIT_MASK_SCH_TXCMD)
+#define BIT_SET_SCH_TXCMD(x, v) (BIT_CLEAR_SCH_TXCMD(x) | BIT_SCH_TXCMD(v))
-/* 2 REG_TCR (Offset 0x0604) */
+#endif
+#if (HALMAC_8821C_SUPPORT)
-#define BIT_SHIFT_TSFT_CMP 20
-#define BIT_MASK_TSFT_CMP 0xf
-#define BIT_TSFT_CMP(x) (((x) & BIT_MASK_TSFT_CMP) << BIT_SHIFT_TSFT_CMP)
-#define BIT_GET_TSFT_CMP(x) (((x) >> BIT_SHIFT_TSFT_CMP) & BIT_MASK_TSFT_CMP)
+/* 2 REG_PAGE5_DUMMY (Offset 0x05FC) */
+#define BIT_ECO_TXOP_BREAK_FORCE_CFEND BIT(0)
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_WMAC_CR (Offset 0x0600) */
+#define BIT_APSDOFF_STATUS BIT(7)
-/* 2 REG_TCR (Offset 0x0604) */
+#endif
-#define BIT_FETCH_MPDU_AFTER_WSEC_RDY BIT(20)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT)
-#endif
+/* 2 REG_WMAC_CR (Offset 0x0600) */
+#define BIT_APSDOFF BIT(6)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-/* 2 REG_TCR (Offset 0x0604) */
+/* 2 REG_WMAC_CR (Offset 0x0600) */
-#define BIT_WMAC_TCR_EN_20MST BIT(19)
-#define BIT_WMAC_DIS_SIGTA BIT(18)
-#define BIT_WMAC_DIS_A2B0 BIT(17)
-#define BIT_WMAC_MSK_SIGBCRC BIT(16)
+#define BIT_STANDBY_STATUS BIT(5)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_WMAC_CR (Offset 0x0600) */
+#define BIT_IC_MACPHY_M BIT(0)
-/* 2 REG_TCR (Offset 0x0604) */
+#endif
-#define BIT_WMAC_TCR_ERRSTEN_3 BIT(15)
-#define BIT_WMAC_TCR_ERRSTEN_2 BIT(14)
-#define BIT_WMAC_TCR_ERRSTEN_1 BIT(13)
-#define BIT_WMAC_TCR_ERRSTEN_0 BIT(12)
-#define BIT_WMAC_TCR_TXSK_PERPKT BIT(11)
-#define BIT_ICV BIT(10)
-#define BIT_CFEND_FORMAT BIT(9)
-#define BIT_CRC BIT(8)
-#define BIT_PWRBIT_OW_EN BIT(7)
-#define BIT_PWR_ST BIT(6)
-#define BIT_WMAC_TCR_UPD_TIMIE BIT(5)
-#define BIT_WMAC_TCR_UPD_HGQMD BIT(4)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_WMAC_FWPKT_CR (Offset 0x0601) */
+#define BIT_FWEN BIT(7)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8198F_SUPPORT)
-/* 2 REG_TCR (Offset 0x0604) */
+/* 2 REG_WMAC_FWPKT_CR (Offset 0x0601) */
-#define BIT_VHTSIGA1_TXPS BIT(3)
+#define BIT_FWRX_EN BIT(7)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_WMAC_FWPKT_CR (Offset 0x0601) */
+#define BIT_PHYSTS_PKT_CTRL BIT(6)
-/* 2 REG_TCR (Offset 0x0604) */
+#endif
-#define BIT_PAD_SEL BIT(2)
-#define BIT_DIS_GCLK BIT(1)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT)
-#endif
+/* 2 REG_WMAC_FWPKT_CR (Offset 0x0601) */
+#define BIT_FWFULL_TO_RXFF_EN BIT(5)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_TCR (Offset 0x0604) */
+/* 2 REG_WMAC_FWPKT_CR (Offset 0x0601) */
+
+#define BIT_APPHDR_MIDSRCH_FAIL BIT(4)
+#define BIT_FWPARSING_EN BIT(3)
-#define BIT_TSFRST BIT(0)
+#define BIT_SHIFT_APPEND_MHDR_LEN 0
+#define BIT_MASK_APPEND_MHDR_LEN 0x7
+#define BIT_APPEND_MHDR_LEN(x) \
+ (((x) & BIT_MASK_APPEND_MHDR_LEN) << BIT_SHIFT_APPEND_MHDR_LEN)
+#define BITS_APPEND_MHDR_LEN \
+ (BIT_MASK_APPEND_MHDR_LEN << BIT_SHIFT_APPEND_MHDR_LEN)
+#define BIT_CLEAR_APPEND_MHDR_LEN(x) ((x) & (~BITS_APPEND_MHDR_LEN))
+#define BIT_GET_APPEND_MHDR_LEN(x) \
+ (((x) >> BIT_SHIFT_APPEND_MHDR_LEN) & BIT_MASK_APPEND_MHDR_LEN)
+#define BIT_SET_APPEND_MHDR_LEN(x, v) \
+ (BIT_CLEAR_APPEND_MHDR_LEN(x) | BIT_APPEND_MHDR_LEN(v))
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_BWOPMODE (Offset 0x0603) */
+
+#define BIT_WMAC_20MHZBW BIT(2)
+#define BIT_WMAC_M11J BIT(0)
+
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_TCR (Offset 0x0604) */
-#define BIT_R_WMAC_TCR_LSIG BIT(0)
+#define BIT_WMAC_EN_RTS_ADDR BIT(31)
+#define BIT_WMAC_DISABLE_CCK BIT(30)
+#define BIT_WMAC_RAW_LEN BIT(29)
+#define BIT_WMAC_NOTX_IN_RXNDP BIT(28)
+#define BIT_WMAC_EN_EOF BIT(27)
+#define BIT_WMAC_BF_SEL BIT(26)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_TCR (Offset 0x0604) */
+#define BIT_WMAC_ANTMODE_SEL BIT(25)
-/* 2 REG_RCR (Offset 0x0608) */
+#endif
-#define BIT_APP_FCS BIT(31)
-#define BIT_APP_MIC BIT(30)
-#define BIT_APP_ICV BIT(29)
-#define BIT_APP_PHYSTS BIT(28)
-#define BIT_APP_BASSN BIT(27)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_TCR (Offset 0x0604) */
+#define BIT_WMAC_TCRPWRMGT_HWCTL BIT(24)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814A_SUPPORT)
-/* 2 REG_RCR (Offset 0x0608) */
+/* 2 REG_TCR (Offset 0x0604) */
-#define BIT_VHT_DACK BIT(26)
+#define BIT_RXLEN_SEL BIT(24)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_TCR (Offset 0x0604) */
+#define BIT_WMAC_TCRPWRMGT_HWCTL_EN BIT(24)
-/* 2 REG_RCR (Offset 0x0608) */
+#endif
-#define BIT_TCPOFLD_EN BIT(25)
-#define BIT_ENMBID BIT(24)
-#define BIT_LSIGEN BIT(23)
-#define BIT_MFBEN BIT(22)
-#define BIT_DISCHKPPDLLEN BIT(21)
-#define BIT_PKTCTL_DLEN BIT(20)
-#define BIT_TIM_PARSER_EN BIT(18)
-#define BIT_BC_MD_EN BIT(17)
-#define BIT_UC_MD_EN BIT(16)
-#define BIT_RXSK_PERPKT BIT(15)
-#define BIT_HTC_LOC_CTRL BIT(14)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_TCR (Offset 0x0604) */
+#define BIT_WMAC_SMOOTH_VAL BIT(23)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_RCR (Offset 0x0608) */
+/* 2 REG_TCR (Offset 0x0604) */
-#define BIT_AMF BIT(13)
-#define BIT_ACF BIT(12)
+#define BIT_WMAC_EN_SCRAM_INC BIT(22)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_RCR (Offset 0x0608) */
+/* 2 REG_TCR (Offset 0x0604) */
-#define BIT_RPFM_CAM_ENABLE BIT(12)
+#define BIT_UNDERFLOWEN_CMPLEN_SEL BIT(21)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_TCR (Offset 0x0604) */
-/* 2 REG_RCR (Offset 0x0608) */
-
-#define BIT_ADF BIT(11)
+#define BIT_SHIFT_TSFT_CMP 20
+#define BIT_MASK_TSFT_CMP 0xf
+#define BIT_TSFT_CMP(x) (((x) & BIT_MASK_TSFT_CMP) << BIT_SHIFT_TSFT_CMP)
+#define BITS_TSFT_CMP (BIT_MASK_TSFT_CMP << BIT_SHIFT_TSFT_CMP)
+#define BIT_CLEAR_TSFT_CMP(x) ((x) & (~BITS_TSFT_CMP))
+#define BIT_GET_TSFT_CMP(x) (((x) >> BIT_SHIFT_TSFT_CMP) & BIT_MASK_TSFT_CMP)
+#define BIT_SET_TSFT_CMP(x, v) (BIT_CLEAR_TSFT_CMP(x) | BIT_TSFT_CMP(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_RCR (Offset 0x0608) */
+/* 2 REG_TCR (Offset 0x0604) */
-#define BIT_TA_BCN BIT(11)
+#define BIT_FETCH_MPDU_AFTER_WSEC_RDY BIT(20)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_TCR (Offset 0x0604) */
+#define BIT_WMAC_TCR_EN_20MST BIT(19)
+#define BIT_WMAC_DIS_SIGTA BIT(18)
+#define BIT_WMAC_DIS_A2B0 BIT(17)
+#define BIT_WMAC_MSK_SIGBCRC BIT(16)
-/* 2 REG_RCR (Offset 0x0608) */
+#endif
-#define BIT_DISDECMYPKT BIT(10)
-#define BIT_AICV BIT(9)
-#define BIT_ACRC32 BIT(8)
-#define BIT_CBSSID_BCN BIT(7)
-#define BIT_CBSSID_DATA BIT(6)
-#define BIT_APWRMGT BIT(5)
-#define BIT_ADD3 BIT(4)
-#define BIT_AB BIT(3)
-#define BIT_AM BIT(2)
-#define BIT_APM BIT(1)
-#define BIT_AAP BIT(0)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-/* 2 REG_RX_PKT_LIMIT (Offset 0x060C) */
+/* 2 REG_TCR (Offset 0x0604) */
+#define BIT_WMAC_TCR_ERRSTEN_3 BIT(15)
+#define BIT_WMAC_TCR_ERRSTEN_2 BIT(14)
+#define BIT_WMAC_TCR_ERRSTEN_1 BIT(13)
+#define BIT_WMAC_TCR_ERRSTEN_0 BIT(12)
+#define BIT_WMAC_TCR_TXSK_PERPKT BIT(11)
+#define BIT_ICV BIT(10)
-#define BIT_SHIFT_RXPKTLMT 0
-#define BIT_MASK_RXPKTLMT 0x3f
-#define BIT_RXPKTLMT(x) (((x) & BIT_MASK_RXPKTLMT) << BIT_SHIFT_RXPKTLMT)
-#define BIT_GET_RXPKTLMT(x) (((x) >> BIT_SHIFT_RXPKTLMT) & BIT_MASK_RXPKTLMT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_RX_DLK_TIME (Offset 0x060D) */
+/* 2 REG_TCR (Offset 0x0604) */
+#define BIT_CFEND_FORMAT BIT(9)
-#define BIT_SHIFT_RX_DLK_TIME 0
-#define BIT_MASK_RX_DLK_TIME 0xff
-#define BIT_RX_DLK_TIME(x) (((x) & BIT_MASK_RX_DLK_TIME) << BIT_SHIFT_RX_DLK_TIME)
-#define BIT_GET_RX_DLK_TIME(x) (((x) >> BIT_SHIFT_RX_DLK_TIME) & BIT_MASK_RX_DLK_TIME)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_TCR (Offset 0x0604) */
+#define BIT_CRC BIT(8)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */
+/* 2 REG_TCR (Offset 0x0604) */
-#define BIT_BITMAP_VO BIT(7)
+#define BIT_PWRBIT_OW_EN BIT(7)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_TCR (Offset 0x0604) */
+#define BIT_WMAC_TCRPWRMGT_HWDATA_EN BIT(7)
-/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */
+#endif
-#define BIT_APP_PHYSTS_PER_SUBMPDU BIT(7)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_TCR (Offset 0x0604) */
+#define BIT_PWR_ST BIT(6)
+#define BIT_WMAC_TCR_UPD_TIMIE BIT(5)
+#define BIT_WMAC_TCR_UPD_HGQMD BIT(4)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */
+/* 2 REG_TCR (Offset 0x0604) */
-#define BIT_PHYSTS_PER_PKT_MODE BIT(7)
+#define BIT_VHTSIGA1_TXPS BIT(3)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_TCR (Offset 0x0604) */
+#define BIT_PAD_SEL BIT(2)
+#define BIT_DIS_GCLK BIT(1)
-/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */
+#endif
-#define BIT_BITMAP_VI BIT(6)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_TCR (Offset 0x0604) */
+#define BIT_TSFRST BIT(0)
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */
+/* 2 REG_TCR (Offset 0x0604) */
-#define BIT_APP_MH_SHIFT_VAL BIT(6)
+#define BIT_R_WMAC_TCR_LSIG BIT(0)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_TCR (Offset 0x0604) */
+#define BIT_WMAC_TCRPWRMGT_HWACT_EN BIT(0)
-/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */
+#endif
-#define BIT_BITMAP_BE BIT(5)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_RCR (Offset 0x0608) */
+#define BIT_APP_FCS BIT(31)
+#define BIT_APP_MIC BIT(30)
+#define BIT_APP_ICV BIT(29)
+#define BIT_APP_PHYSTS BIT(28)
+#define BIT_APP_BASSN BIT(27)
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */
+/* 2 REG_RCR (Offset 0x0608) */
-#define BIT_WMAC_ENSHIFT BIT(5)
+#define BIT_VHT_DACK BIT(26)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_RCR (Offset 0x0608) */
+#define BIT_TCPOFLD_EN BIT(25)
-/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */
+#endif
-#define BIT_BITMAP_BK BIT(4)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_BITMAP_CONDITION 2
-#define BIT_MASK_BITMAP_CONDITION 0x3
-#define BIT_BITMAP_CONDITION(x) (((x) & BIT_MASK_BITMAP_CONDITION) << BIT_SHIFT_BITMAP_CONDITION)
-#define BIT_GET_BITMAP_CONDITION(x) (((x) >> BIT_SHIFT_BITMAP_CONDITION) & BIT_MASK_BITMAP_CONDITION)
+/* 2 REG_RCR (Offset 0x0608) */
-#define BIT_BITMAP_SSNBK_COUNTER_CLR BIT(1)
+#define BIT_ENMBID BIT(24)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_RCR (Offset 0x0608) */
+#define BIT_ENADDRCAM BIT(24)
-/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_DRVINFO_SZ 0
-#define BIT_MASK_DRVINFO_SZ 0xff
-#define BIT_DRVINFO_SZ(x) (((x) & BIT_MASK_DRVINFO_SZ) << BIT_SHIFT_DRVINFO_SZ)
-#define BIT_GET_DRVINFO_SZ(x) (((x) >> BIT_SHIFT_DRVINFO_SZ) & BIT_MASK_DRVINFO_SZ)
+/* 2 REG_RCR (Offset 0x0608) */
+#define BIT_LSIGEN BIT(23)
+#define BIT_MFBEN BIT(22)
+#define BIT_DISCHKPPDLLEN BIT(21)
+#define BIT_PKTCTL_DLEN BIT(20)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_RCR (Offset 0x0608) */
+#define BIT_DISGCLK BIT(19)
-/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_DRVINFO_SZ_V1 0
-#define BIT_MASK_DRVINFO_SZ_V1 0xf
-#define BIT_DRVINFO_SZ_V1(x) (((x) & BIT_MASK_DRVINFO_SZ_V1) << BIT_SHIFT_DRVINFO_SZ_V1)
-#define BIT_GET_DRVINFO_SZ_V1(x) (((x) >> BIT_SHIFT_DRVINFO_SZ_V1) & BIT_MASK_DRVINFO_SZ_V1)
+/* 2 REG_RCR (Offset 0x0608) */
-#define BIT_BITMAP_FORCE BIT(0)
+#define BIT_TIM_PARSER_EN BIT(18)
+#define BIT_BC_MD_EN BIT(17)
+#define BIT_UC_MD_EN BIT(16)
+#define BIT_RXSK_PERPKT BIT(15)
+#define BIT_HTC_LOC_CTRL BIT(14)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_RCR (Offset 0x0608) */
+#define BIT_AMF BIT(13)
-/* 2 REG_MACID (Offset 0x0610) */
+#endif
+#if (HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_MACID 0
-#define BIT_MASK_MACID 0xffffffffffffL
-#define BIT_MACID(x) (((x) & BIT_MASK_MACID) << BIT_SHIFT_MACID)
-#define BIT_GET_MACID(x) (((x) >> BIT_SHIFT_MACID) & BIT_MASK_MACID)
+/* 2 REG_RCR (Offset 0x0608) */
+#define BIT_CHK_PREVTCA2 BIT(13)
-/* 2 REG_BSSID (Offset 0x0618) */
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_BSSID 0
-#define BIT_MASK_BSSID 0xffffffffffffL
-#define BIT_BSSID(x) (((x) & BIT_MASK_BSSID) << BIT_SHIFT_BSSID)
-#define BIT_GET_BSSID(x) (((x) >> BIT_SHIFT_BSSID) & BIT_MASK_BSSID)
+/* 2 REG_RCR (Offset 0x0608) */
+#define BIT_ACK_WITH_CBSSID_DATA_OPTION BIT(13)
-/* 2 REG_MAR (Offset 0x0620) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_MAR 0
-#define BIT_MASK_MAR 0xffffffffffffffffL
-#define BIT_MAR(x) (((x) & BIT_MASK_MAR) << BIT_SHIFT_MAR)
-#define BIT_GET_MAR(x) (((x) >> BIT_SHIFT_MAR) & BIT_MASK_MAR)
+/* 2 REG_RCR (Offset 0x0608) */
+#define BIT_ACF BIT(12)
-/* 2 REG_MBIDCAMCFG_1 (Offset 0x0628) */
+#endif
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_MBIDCAM_RWDATA_L 0
-#define BIT_MASK_MBIDCAM_RWDATA_L 0xffffffffL
-#define BIT_MBIDCAM_RWDATA_L(x) (((x) & BIT_MASK_MBIDCAM_RWDATA_L) << BIT_SHIFT_MBIDCAM_RWDATA_L)
-#define BIT_GET_MBIDCAM_RWDATA_L(x) (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L) & BIT_MASK_MBIDCAM_RWDATA_L)
+/* 2 REG_RCR (Offset 0x0608) */
+#define BIT_RPFM_CAM_ENABLE BIT(12)
-/* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */
+#endif
-#define BIT_MBIDCAM_POLL BIT(31)
-#define BIT_MBIDCAM_WT_EN BIT(30)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_MBIDCAM_ADDR 24
-#define BIT_MASK_MBIDCAM_ADDR 0x1f
-#define BIT_MBIDCAM_ADDR(x) (((x) & BIT_MASK_MBIDCAM_ADDR) << BIT_SHIFT_MBIDCAM_ADDR)
-#define BIT_GET_MBIDCAM_ADDR(x) (((x) >> BIT_SHIFT_MBIDCAM_ADDR) & BIT_MASK_MBIDCAM_ADDR)
+/* 2 REG_RCR (Offset 0x0608) */
-#define BIT_MBIDCAM_VALID BIT(23)
-#define BIT_LSIC_TXOP_EN BIT(17)
+#define BIT_ADF BIT(11)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_RCR (Offset 0x0608) */
+#define BIT_TA_BCN BIT(11)
-/* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */
+#endif
-#define BIT_CTS_EN BIT(16)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_RCR (Offset 0x0608) */
+#define BIT_DISDECMYPKT BIT(10)
+#define BIT_AICV BIT(9)
+#define BIT_ACRC32 BIT(8)
+#define BIT_CBSSID_BCN BIT(7)
+#define BIT_CBSSID_DATA BIT(6)
+#define BIT_APWRMGT BIT(5)
+#define BIT_ADD3 BIT(4)
+#define BIT_AB BIT(3)
+#define BIT_AM BIT(2)
+#define BIT_APM BIT(1)
+#define BIT_AAP BIT(0)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_RX_PKT_LIMIT (Offset 0x060C) */
+#define BIT_SHIFT_RXPKTLMT 0
+#define BIT_MASK_RXPKTLMT 0x3f
+#define BIT_RXPKTLMT(x) (((x) & BIT_MASK_RXPKTLMT) << BIT_SHIFT_RXPKTLMT)
+#define BITS_RXPKTLMT (BIT_MASK_RXPKTLMT << BIT_SHIFT_RXPKTLMT)
+#define BIT_CLEAR_RXPKTLMT(x) ((x) & (~BITS_RXPKTLMT))
+#define BIT_GET_RXPKTLMT(x) (((x) >> BIT_SHIFT_RXPKTLMT) & BIT_MASK_RXPKTLMT)
+#define BIT_SET_RXPKTLMT(x, v) (BIT_CLEAR_RXPKTLMT(x) | BIT_RXPKTLMT(v))
-/* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */
+/* 2 REG_RX_DLK_TIME (Offset 0x060D) */
-#define BIT_REPEAT_MODE_EN BIT(16)
+#define BIT_SHIFT_RX_DLK_TIME 0
+#define BIT_MASK_RX_DLK_TIME 0xff
+#define BIT_RX_DLK_TIME(x) \
+ (((x) & BIT_MASK_RX_DLK_TIME) << BIT_SHIFT_RX_DLK_TIME)
+#define BITS_RX_DLK_TIME (BIT_MASK_RX_DLK_TIME << BIT_SHIFT_RX_DLK_TIME)
+#define BIT_CLEAR_RX_DLK_TIME(x) ((x) & (~BITS_RX_DLK_TIME))
+#define BIT_GET_RX_DLK_TIME(x) \
+ (((x) >> BIT_SHIFT_RX_DLK_TIME) & BIT_MASK_RX_DLK_TIME)
+#define BIT_SET_RX_DLK_TIME(x, v) \
+ (BIT_CLEAR_RX_DLK_TIME(x) | BIT_RX_DLK_TIME(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */
+#define BIT_APP_PHYSTS_PER_SUBMPDU BIT(7)
-/* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_MBIDCAM_RWDATA_H 0
-#define BIT_MASK_MBIDCAM_RWDATA_H 0xffff
-#define BIT_MBIDCAM_RWDATA_H(x) (((x) & BIT_MASK_MBIDCAM_RWDATA_H) << BIT_SHIFT_MBIDCAM_RWDATA_H)
-#define BIT_GET_MBIDCAM_RWDATA_H(x) (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H) & BIT_MASK_MBIDCAM_RWDATA_H)
+/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */
+#define BIT_PHYSTS_PER_PKT_MODE BIT(7)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */
+#define BIT_APP_MH_SHIFT_VAL BIT(6)
+#define BIT_WMAC_ENSHIFT BIT(5)
-/* 2 REG_MCU_TEST_1 (Offset 0x0630) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_MCU_RSVD 0
-#define BIT_MASK_MCU_RSVD 0xffffffffL
-#define BIT_MCU_RSVD(x) (((x) & BIT_MASK_MCU_RSVD) << BIT_SHIFT_MCU_RSVD)
-#define BIT_GET_MCU_RSVD(x) (((x) >> BIT_SHIFT_MCU_RSVD) & BIT_MASK_MCU_RSVD)
+/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */
+#define BIT_SHIFT_DRVINFO_SZ 0
+#define BIT_MASK_DRVINFO_SZ 0xff
+#define BIT_DRVINFO_SZ(x) (((x) & BIT_MASK_DRVINFO_SZ) << BIT_SHIFT_DRVINFO_SZ)
+#define BITS_DRVINFO_SZ (BIT_MASK_DRVINFO_SZ << BIT_SHIFT_DRVINFO_SZ)
+#define BIT_CLEAR_DRVINFO_SZ(x) ((x) & (~BITS_DRVINFO_SZ))
+#define BIT_GET_DRVINFO_SZ(x) \
+ (((x) >> BIT_SHIFT_DRVINFO_SZ) & BIT_MASK_DRVINFO_SZ)
+#define BIT_SET_DRVINFO_SZ(x, v) (BIT_CLEAR_DRVINFO_SZ(x) | BIT_DRVINFO_SZ(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_WMAC_TCR_TSFT_OFS (Offset 0x0630) */
+/* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */
+#define BIT_SHIFT_DRVINFO_SZ_V1 0
+#define BIT_MASK_DRVINFO_SZ_V1 0xf
+#define BIT_DRVINFO_SZ_V1(x) \
+ (((x) & BIT_MASK_DRVINFO_SZ_V1) << BIT_SHIFT_DRVINFO_SZ_V1)
+#define BITS_DRVINFO_SZ_V1 (BIT_MASK_DRVINFO_SZ_V1 << BIT_SHIFT_DRVINFO_SZ_V1)
+#define BIT_CLEAR_DRVINFO_SZ_V1(x) ((x) & (~BITS_DRVINFO_SZ_V1))
+#define BIT_GET_DRVINFO_SZ_V1(x) \
+ (((x) >> BIT_SHIFT_DRVINFO_SZ_V1) & BIT_MASK_DRVINFO_SZ_V1)
+#define BIT_SET_DRVINFO_SZ_V1(x, v) \
+ (BIT_CLEAR_DRVINFO_SZ_V1(x) | BIT_DRVINFO_SZ_V1(v))
-#define BIT_SHIFT_WMAC_TCR_TSFT_OFS 0
-#define BIT_MASK_WMAC_TCR_TSFT_OFS 0xffff
-#define BIT_WMAC_TCR_TSFT_OFS(x) (((x) & BIT_MASK_WMAC_TCR_TSFT_OFS) << BIT_SHIFT_WMAC_TCR_TSFT_OFS)
-#define BIT_GET_WMAC_TCR_TSFT_OFS(x) (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS) & BIT_MASK_WMAC_TCR_TSFT_OFS)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-/* 2 REG_UDF_THSD (Offset 0x0632) */
+/* 2 REG_MACID (Offset 0x0610) */
+#define BIT_SHIFT_MACID 0
+#define BIT_MASK_MACID 0xffffffffffffL
+#define BIT_MACID(x) (((x) & BIT_MASK_MACID) << BIT_SHIFT_MACID)
+#define BITS_MACID (BIT_MASK_MACID << BIT_SHIFT_MACID)
+#define BIT_CLEAR_MACID(x) ((x) & (~BITS_MACID))
+#define BIT_GET_MACID(x) (((x) >> BIT_SHIFT_MACID) & BIT_MASK_MACID)
+#define BIT_SET_MACID(x, v) (BIT_CLEAR_MACID(x) | BIT_MACID(v))
-#define BIT_SHIFT_UDF_THSD 0
-#define BIT_MASK_UDF_THSD 0xff
-#define BIT_UDF_THSD(x) (((x) & BIT_MASK_UDF_THSD) << BIT_SHIFT_UDF_THSD)
-#define BIT_GET_UDF_THSD(x) (((x) >> BIT_SHIFT_UDF_THSD) & BIT_MASK_UDF_THSD)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_ZLD_NUM (Offset 0x0633) */
+/* 2 REG_MACID (Offset 0x0610) */
+#define BIT_SHIFT_MACID_V1 0
+#define BIT_MASK_MACID_V1 0xffffffffL
+#define BIT_MACID_V1(x) (((x) & BIT_MASK_MACID_V1) << BIT_SHIFT_MACID_V1)
+#define BITS_MACID_V1 (BIT_MASK_MACID_V1 << BIT_SHIFT_MACID_V1)
+#define BIT_CLEAR_MACID_V1(x) ((x) & (~BITS_MACID_V1))
+#define BIT_GET_MACID_V1(x) (((x) >> BIT_SHIFT_MACID_V1) & BIT_MASK_MACID_V1)
+#define BIT_SET_MACID_V1(x, v) (BIT_CLEAR_MACID_V1(x) | BIT_MACID_V1(v))
-#define BIT_SHIFT_ZLD_NUM 0
-#define BIT_MASK_ZLD_NUM 0xff
-#define BIT_ZLD_NUM(x) (((x) & BIT_MASK_ZLD_NUM) << BIT_SHIFT_ZLD_NUM)
-#define BIT_GET_ZLD_NUM(x) (((x) >> BIT_SHIFT_ZLD_NUM) & BIT_MASK_ZLD_NUM)
+/* 2 REG_MACID_H (Offset 0x0614) */
+#define BIT_SHIFT_MACID_H_V1 0
+#define BIT_MASK_MACID_H_V1 0xffff
+#define BIT_MACID_H_V1(x) (((x) & BIT_MASK_MACID_H_V1) << BIT_SHIFT_MACID_H_V1)
+#define BITS_MACID_H_V1 (BIT_MASK_MACID_H_V1 << BIT_SHIFT_MACID_H_V1)
+#define BIT_CLEAR_MACID_H_V1(x) ((x) & (~BITS_MACID_H_V1))
+#define BIT_GET_MACID_H_V1(x) \
+ (((x) >> BIT_SHIFT_MACID_H_V1) & BIT_MASK_MACID_H_V1)
+#define BIT_SET_MACID_H_V1(x, v) (BIT_CLEAR_MACID_H_V1(x) | BIT_MACID_H_V1(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_BSSID (Offset 0x0618) */
+#define BIT_SHIFT_BSSID 0
+#define BIT_MASK_BSSID 0xffffffffffffL
+#define BIT_BSSID(x) (((x) & BIT_MASK_BSSID) << BIT_SHIFT_BSSID)
+#define BITS_BSSID (BIT_MASK_BSSID << BIT_SHIFT_BSSID)
+#define BIT_CLEAR_BSSID(x) ((x) & (~BITS_BSSID))
+#define BIT_GET_BSSID(x) (((x) >> BIT_SHIFT_BSSID) & BIT_MASK_BSSID)
+#define BIT_SET_BSSID(x, v) (BIT_CLEAR_BSSID(x) | BIT_BSSID(v))
-/* 2 REG_MCU_TEST_2 (Offset 0x0634) */
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_MCU_RSVD_2 0
-#define BIT_MASK_MCU_RSVD_2 0xffffffffL
-#define BIT_MCU_RSVD_2(x) (((x) & BIT_MASK_MCU_RSVD_2) << BIT_SHIFT_MCU_RSVD_2)
-#define BIT_GET_MCU_RSVD_2(x) (((x) >> BIT_SHIFT_MCU_RSVD_2) & BIT_MASK_MCU_RSVD_2)
+/* 2 REG_BSSID (Offset 0x0618) */
+
+#define BIT_SHIFT_BSSID_V1 0
+#define BIT_MASK_BSSID_V1 0xffffffffL
+#define BIT_BSSID_V1(x) (((x) & BIT_MASK_BSSID_V1) << BIT_SHIFT_BSSID_V1)
+#define BITS_BSSID_V1 (BIT_MASK_BSSID_V1 << BIT_SHIFT_BSSID_V1)
+#define BIT_CLEAR_BSSID_V1(x) ((x) & (~BITS_BSSID_V1))
+#define BIT_GET_BSSID_V1(x) (((x) >> BIT_SHIFT_BSSID_V1) & BIT_MASK_BSSID_V1)
+#define BIT_SET_BSSID_V1(x, v) (BIT_CLEAR_BSSID_V1(x) | BIT_BSSID_V1(v))
+#define BIT_SHIFT_BSSID_H_V1 0
+#define BIT_MASK_BSSID_H_V1 0xffff
+#define BIT_BSSID_H_V1(x) (((x) & BIT_MASK_BSSID_H_V1) << BIT_SHIFT_BSSID_H_V1)
+#define BITS_BSSID_H_V1 (BIT_MASK_BSSID_H_V1 << BIT_SHIFT_BSSID_H_V1)
+#define BIT_CLEAR_BSSID_H_V1(x) ((x) & (~BITS_BSSID_H_V1))
+#define BIT_GET_BSSID_H_V1(x) \
+ (((x) >> BIT_SHIFT_BSSID_H_V1) & BIT_MASK_BSSID_H_V1)
+#define BIT_SET_BSSID_H_V1(x, v) (BIT_CLEAR_BSSID_H_V1(x) | BIT_BSSID_H_V1(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_MAR (Offset 0x0620) */
+#define BIT_SHIFT_MAR 0
+#define BIT_MASK_MAR 0xffffffffffffffffL
+#define BIT_MAR(x) (((x) & BIT_MASK_MAR) << BIT_SHIFT_MAR)
+#define BITS_MAR (BIT_MASK_MAR << BIT_SHIFT_MAR)
+#define BIT_CLEAR_MAR(x) ((x) & (~BITS_MAR))
+#define BIT_GET_MAR(x) (((x) >> BIT_SHIFT_MAR) & BIT_MASK_MAR)
+#define BIT_SET_MAR(x, v) (BIT_CLEAR_MAR(x) | BIT_MAR(v))
-/* 2 REG_STMP_THSD (Offset 0x0634) */
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_STMP_THSD 0
-#define BIT_MASK_STMP_THSD 0xff
-#define BIT_STMP_THSD(x) (((x) & BIT_MASK_STMP_THSD) << BIT_SHIFT_STMP_THSD)
-#define BIT_GET_STMP_THSD(x) (((x) >> BIT_SHIFT_STMP_THSD) & BIT_MASK_STMP_THSD)
+/* 2 REG_MAR (Offset 0x0620) */
+#define BIT_SHIFT_MAR_V1 0
+#define BIT_MASK_MAR_V1 0xffffffffL
+#define BIT_MAR_V1(x) (((x) & BIT_MASK_MAR_V1) << BIT_SHIFT_MAR_V1)
+#define BITS_MAR_V1 (BIT_MASK_MAR_V1 << BIT_SHIFT_MAR_V1)
+#define BIT_CLEAR_MAR_V1(x) ((x) & (~BITS_MAR_V1))
+#define BIT_GET_MAR_V1(x) (((x) >> BIT_SHIFT_MAR_V1) & BIT_MASK_MAR_V1)
+#define BIT_SET_MAR_V1(x, v) (BIT_CLEAR_MAR_V1(x) | BIT_MAR_V1(v))
-/* 2 REG_WMAC_TXTIMEOUT (Offset 0x0635) */
+/* 2 REG_MAR_H (Offset 0x0624) */
+#define BIT_SHIFT_MAR_H_V1 0
+#define BIT_MASK_MAR_H_V1 0xffffffffL
+#define BIT_MAR_H_V1(x) (((x) & BIT_MASK_MAR_H_V1) << BIT_SHIFT_MAR_H_V1)
+#define BITS_MAR_H_V1 (BIT_MASK_MAR_H_V1 << BIT_SHIFT_MAR_H_V1)
+#define BIT_CLEAR_MAR_H_V1(x) ((x) & (~BITS_MAR_H_V1))
+#define BIT_GET_MAR_H_V1(x) (((x) >> BIT_SHIFT_MAR_H_V1) & BIT_MASK_MAR_H_V1)
+#define BIT_SET_MAR_H_V1(x, v) (BIT_CLEAR_MAR_H_V1(x) | BIT_MAR_H_V1(v))
-#define BIT_SHIFT_WMAC_TXTIMEOUT 0
-#define BIT_MASK_WMAC_TXTIMEOUT 0xff
-#define BIT_WMAC_TXTIMEOUT(x) (((x) & BIT_MASK_WMAC_TXTIMEOUT) << BIT_SHIFT_WMAC_TXTIMEOUT)
-#define BIT_GET_WMAC_TXTIMEOUT(x) (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT) & BIT_MASK_WMAC_TXTIMEOUT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_MCU_TEST_2_V1 (Offset 0x0636) */
+/* 2 REG_MBIDCAMCFG_1 (Offset 0x0628) */
+#define BIT_SHIFT_MBIDCAM_RWDATA_L 0
+#define BIT_MASK_MBIDCAM_RWDATA_L 0xffffffffL
+#define BIT_MBIDCAM_RWDATA_L(x) \
+ (((x) & BIT_MASK_MBIDCAM_RWDATA_L) << BIT_SHIFT_MBIDCAM_RWDATA_L)
+#define BITS_MBIDCAM_RWDATA_L \
+ (BIT_MASK_MBIDCAM_RWDATA_L << BIT_SHIFT_MBIDCAM_RWDATA_L)
+#define BIT_CLEAR_MBIDCAM_RWDATA_L(x) ((x) & (~BITS_MBIDCAM_RWDATA_L))
+#define BIT_GET_MBIDCAM_RWDATA_L(x) \
+ (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L) & BIT_MASK_MBIDCAM_RWDATA_L)
+#define BIT_SET_MBIDCAM_RWDATA_L(x, v) \
+ (BIT_CLEAR_MBIDCAM_RWDATA_L(x) | BIT_MBIDCAM_RWDATA_L(v))
-#define BIT_SHIFT_MCU_RSVD_2_V1 0
-#define BIT_MASK_MCU_RSVD_2_V1 0xffff
-#define BIT_MCU_RSVD_2_V1(x) (((x) & BIT_MASK_MCU_RSVD_2_V1) << BIT_SHIFT_MCU_RSVD_2_V1)
-#define BIT_GET_MCU_RSVD_2_V1(x) (((x) >> BIT_SHIFT_MCU_RSVD_2_V1) & BIT_MASK_MCU_RSVD_2_V1)
+/* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */
+#define BIT_MBIDCAM_POLL BIT(31)
+#define BIT_MBIDCAM_WT_EN BIT(30)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */
+#define BIT_SHIFT_MBIDCAM_ADDR 24
+#define BIT_MASK_MBIDCAM_ADDR 0x1f
+#define BIT_MBIDCAM_ADDR(x) \
+ (((x) & BIT_MASK_MBIDCAM_ADDR) << BIT_SHIFT_MBIDCAM_ADDR)
+#define BITS_MBIDCAM_ADDR (BIT_MASK_MBIDCAM_ADDR << BIT_SHIFT_MBIDCAM_ADDR)
+#define BIT_CLEAR_MBIDCAM_ADDR(x) ((x) & (~BITS_MBIDCAM_ADDR))
+#define BIT_GET_MBIDCAM_ADDR(x) \
+ (((x) >> BIT_SHIFT_MBIDCAM_ADDR) & BIT_MASK_MBIDCAM_ADDR)
+#define BIT_SET_MBIDCAM_ADDR(x, v) \
+ (BIT_CLEAR_MBIDCAM_ADDR(x) | BIT_MBIDCAM_ADDR(v))
-/* 2 REG_USTIME_EDCA (Offset 0x0638) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_USTIME_EDCA 0
-#define BIT_MASK_USTIME_EDCA 0xff
-#define BIT_USTIME_EDCA(x) (((x) & BIT_MASK_USTIME_EDCA) << BIT_SHIFT_USTIME_EDCA)
-#define BIT_GET_USTIME_EDCA(x) (((x) >> BIT_SHIFT_USTIME_EDCA) & BIT_MASK_USTIME_EDCA)
+/* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */
+#define BIT_SHIFT_MBIDCAM_ADDR_V1 24
+#define BIT_MASK_MBIDCAM_ADDR_V1 0x3f
+#define BIT_MBIDCAM_ADDR_V1(x) \
+ (((x) & BIT_MASK_MBIDCAM_ADDR_V1) << BIT_SHIFT_MBIDCAM_ADDR_V1)
+#define BITS_MBIDCAM_ADDR_V1 \
+ (BIT_MASK_MBIDCAM_ADDR_V1 << BIT_SHIFT_MBIDCAM_ADDR_V1)
+#define BIT_CLEAR_MBIDCAM_ADDR_V1(x) ((x) & (~BITS_MBIDCAM_ADDR_V1))
+#define BIT_GET_MBIDCAM_ADDR_V1(x) \
+ (((x) >> BIT_SHIFT_MBIDCAM_ADDR_V1) & BIT_MASK_MBIDCAM_ADDR_V1)
+#define BIT_SET_MBIDCAM_ADDR_V1(x, v) \
+ (BIT_CLEAR_MBIDCAM_ADDR_V1(x) | BIT_MBIDCAM_ADDR_V1(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */
-#if (HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#define BIT_MBIDCAM_VALID BIT(23)
+#endif
-/* 2 REG_USTIME_EDCA (Offset 0x0638) */
+#if (HALMAC_8198F_SUPPORT)
+/* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */
-#define BIT_SHIFT_USTIME_EDCA_V1 0
-#define BIT_MASK_USTIME_EDCA_V1 0x1ff
-#define BIT_USTIME_EDCA_V1(x) (((x) & BIT_MASK_USTIME_EDCA_V1) << BIT_SHIFT_USTIME_EDCA_V1)
-#define BIT_GET_USTIME_EDCA_V1(x) (((x) >> BIT_SHIFT_USTIME_EDCA_V1) & BIT_MASK_USTIME_EDCA_V1)
+#define BIT_SHIFT_MBIDCAM_ADDR_V2 23
+#define BIT_MASK_MBIDCAM_ADDR_V2 0x7f
+#define BIT_MBIDCAM_ADDR_V2(x) \
+ (((x) & BIT_MASK_MBIDCAM_ADDR_V2) << BIT_SHIFT_MBIDCAM_ADDR_V2)
+#define BITS_MBIDCAM_ADDR_V2 \
+ (BIT_MASK_MBIDCAM_ADDR_V2 << BIT_SHIFT_MBIDCAM_ADDR_V2)
+#define BIT_CLEAR_MBIDCAM_ADDR_V2(x) ((x) & (~BITS_MBIDCAM_ADDR_V2))
+#define BIT_GET_MBIDCAM_ADDR_V2(x) \
+ (((x) >> BIT_SHIFT_MBIDCAM_ADDR_V2) & BIT_MASK_MBIDCAM_ADDR_V2)
+#define BIT_SET_MBIDCAM_ADDR_V2(x, v) \
+ (BIT_CLEAR_MBIDCAM_ADDR_V2(x) | BIT_MBIDCAM_ADDR_V2(v))
+#define BIT_MBIDCAM_RST BIT(19)
+#define BIT_MBIDCAM_VALID_V1 BIT(18)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8821C_SUPPORT)
+/* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */
+#define BIT_LSIC_TXOP_EN BIT(17)
-/* 2 REG_ACKTO_CCK (Offset 0x0639) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_ACKTO_CCK 0
-#define BIT_MASK_ACKTO_CCK 0xff
-#define BIT_ACKTO_CCK(x) (((x) & BIT_MASK_ACKTO_CCK) << BIT_SHIFT_ACKTO_CCK)
-#define BIT_GET_ACKTO_CCK(x) (((x) >> BIT_SHIFT_ACKTO_CCK) & BIT_MASK_ACKTO_CCK)
+/* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */
+#define BIT_CTS_EN BIT(16)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+/* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */
-/* 2 REG_MAC_SPEC_SIFS (Offset 0x063A) */
+#define BIT_REPEAT_MODE_EN BIT(16)
+#endif
-#define BIT_SHIFT_SPEC_SIFS_OFDM 8
-#define BIT_MASK_SPEC_SIFS_OFDM 0xff
-#define BIT_SPEC_SIFS_OFDM(x) (((x) & BIT_MASK_SPEC_SIFS_OFDM) << BIT_SHIFT_SPEC_SIFS_OFDM)
-#define BIT_GET_SPEC_SIFS_OFDM(x) (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM) & BIT_MASK_SPEC_SIFS_OFDM)
+#if (HALMAC_8814B_SUPPORT)
+/* 2 REG_WMAC_DEBUG_SEL (Offset 0x062C) */
-#define BIT_SHIFT_SPEC_SIFS_CCK 0
-#define BIT_MASK_SPEC_SIFS_CCK 0xff
-#define BIT_SPEC_SIFS_CCK(x) (((x) & BIT_MASK_SPEC_SIFS_CCK) << BIT_SHIFT_SPEC_SIFS_CCK)
-#define BIT_GET_SPEC_SIFS_CCK(x) (((x) >> BIT_SHIFT_SPEC_SIFS_CCK) & BIT_MASK_SPEC_SIFS_CCK)
+#define BIT_SHIFT_WMAC_ARB_DBG_SEL 3
+#define BIT_MASK_WMAC_ARB_DBG_SEL 0x3
+#define BIT_WMAC_ARB_DBG_SEL(x) \
+ (((x) & BIT_MASK_WMAC_ARB_DBG_SEL) << BIT_SHIFT_WMAC_ARB_DBG_SEL)
+#define BITS_WMAC_ARB_DBG_SEL \
+ (BIT_MASK_WMAC_ARB_DBG_SEL << BIT_SHIFT_WMAC_ARB_DBG_SEL)
+#define BIT_CLEAR_WMAC_ARB_DBG_SEL(x) ((x) & (~BITS_WMAC_ARB_DBG_SEL))
+#define BIT_GET_WMAC_ARB_DBG_SEL(x) \
+ (((x) >> BIT_SHIFT_WMAC_ARB_DBG_SEL) & BIT_MASK_WMAC_ARB_DBG_SEL)
+#define BIT_SET_WMAC_ARB_DBG_SEL(x, v) \
+ (BIT_CLEAR_WMAC_ARB_DBG_SEL(x) | BIT_WMAC_ARB_DBG_SEL(v))
+#define BIT_WMAC_EXT_DBG_SEL BIT(2)
-/* 2 REG_RESP_SIFS_CCK (Offset 0x063C) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_SIFS_R2T_CCK 8
-#define BIT_MASK_SIFS_R2T_CCK 0xff
-#define BIT_SIFS_R2T_CCK(x) (((x) & BIT_MASK_SIFS_R2T_CCK) << BIT_SHIFT_SIFS_R2T_CCK)
-#define BIT_GET_SIFS_R2T_CCK(x) (((x) >> BIT_SHIFT_SIFS_R2T_CCK) & BIT_MASK_SIFS_R2T_CCK)
+/* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */
+#define BIT_SHIFT_MBIDCAM_RWDATA_H 0
+#define BIT_MASK_MBIDCAM_RWDATA_H 0xffff
+#define BIT_MBIDCAM_RWDATA_H(x) \
+ (((x) & BIT_MASK_MBIDCAM_RWDATA_H) << BIT_SHIFT_MBIDCAM_RWDATA_H)
+#define BITS_MBIDCAM_RWDATA_H \
+ (BIT_MASK_MBIDCAM_RWDATA_H << BIT_SHIFT_MBIDCAM_RWDATA_H)
+#define BIT_CLEAR_MBIDCAM_RWDATA_H(x) ((x) & (~BITS_MBIDCAM_RWDATA_H))
+#define BIT_GET_MBIDCAM_RWDATA_H(x) \
+ (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H) & BIT_MASK_MBIDCAM_RWDATA_H)
+#define BIT_SET_MBIDCAM_RWDATA_H(x, v) \
+ (BIT_CLEAR_MBIDCAM_RWDATA_H(x) | BIT_MBIDCAM_RWDATA_H(v))
-#define BIT_SHIFT_SIFS_T2T_CCK 0
-#define BIT_MASK_SIFS_T2T_CCK 0xff
-#define BIT_SIFS_T2T_CCK(x) (((x) & BIT_MASK_SIFS_T2T_CCK) << BIT_SHIFT_SIFS_T2T_CCK)
-#define BIT_GET_SIFS_T2T_CCK(x) (((x) >> BIT_SHIFT_SIFS_T2T_CCK) & BIT_MASK_SIFS_T2T_CCK)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_RESP_SIFS_OFDM (Offset 0x063E) */
+/* 2 REG_WMAC_DEBUG_SEL (Offset 0x062C) */
+#define BIT_SHIFT_WMAC_MU_DBGSEL_V1 0
+#define BIT_MASK_WMAC_MU_DBGSEL_V1 0x3
+#define BIT_WMAC_MU_DBGSEL_V1(x) \
+ (((x) & BIT_MASK_WMAC_MU_DBGSEL_V1) << BIT_SHIFT_WMAC_MU_DBGSEL_V1)
+#define BITS_WMAC_MU_DBGSEL_V1 \
+ (BIT_MASK_WMAC_MU_DBGSEL_V1 << BIT_SHIFT_WMAC_MU_DBGSEL_V1)
+#define BIT_CLEAR_WMAC_MU_DBGSEL_V1(x) ((x) & (~BITS_WMAC_MU_DBGSEL_V1))
+#define BIT_GET_WMAC_MU_DBGSEL_V1(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_V1) & BIT_MASK_WMAC_MU_DBGSEL_V1)
+#define BIT_SET_WMAC_MU_DBGSEL_V1(x, v) \
+ (BIT_CLEAR_WMAC_MU_DBGSEL_V1(x) | BIT_WMAC_MU_DBGSEL_V1(v))
-#define BIT_SHIFT_SIFS_R2T_OFDM 8
-#define BIT_MASK_SIFS_R2T_OFDM 0xff
-#define BIT_SIFS_R2T_OFDM(x) (((x) & BIT_MASK_SIFS_R2T_OFDM) << BIT_SHIFT_SIFS_R2T_OFDM)
-#define BIT_GET_SIFS_R2T_OFDM(x) (((x) >> BIT_SHIFT_SIFS_R2T_OFDM) & BIT_MASK_SIFS_R2T_OFDM)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_SIFS_T2T_OFDM 0
-#define BIT_MASK_SIFS_T2T_OFDM 0xff
-#define BIT_SIFS_T2T_OFDM(x) (((x) & BIT_MASK_SIFS_T2T_OFDM) << BIT_SHIFT_SIFS_T2T_OFDM)
-#define BIT_GET_SIFS_T2T_OFDM(x) (((x) >> BIT_SHIFT_SIFS_T2T_OFDM) & BIT_MASK_SIFS_T2T_OFDM)
+/* 2 REG_MCU_TEST_1 (Offset 0x0630) */
+#define BIT_SHIFT_MCU_RSVD 0
+#define BIT_MASK_MCU_RSVD 0xffffffffL
+#define BIT_MCU_RSVD(x) (((x) & BIT_MASK_MCU_RSVD) << BIT_SHIFT_MCU_RSVD)
+#define BITS_MCU_RSVD (BIT_MASK_MCU_RSVD << BIT_SHIFT_MCU_RSVD)
+#define BIT_CLEAR_MCU_RSVD(x) ((x) & (~BITS_MCU_RSVD))
+#define BIT_GET_MCU_RSVD(x) (((x) >> BIT_SHIFT_MCU_RSVD) & BIT_MASK_MCU_RSVD)
+#define BIT_SET_MCU_RSVD(x, v) (BIT_CLEAR_MCU_RSVD(x) | BIT_MCU_RSVD(v))
-/* 2 REG_ACKTO (Offset 0x0640) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_ACKTO 0
-#define BIT_MASK_ACKTO 0xff
-#define BIT_ACKTO(x) (((x) & BIT_MASK_ACKTO) << BIT_SHIFT_ACKTO)
-#define BIT_GET_ACKTO(x) (((x) >> BIT_SHIFT_ACKTO) & BIT_MASK_ACKTO)
+/* 2 REG_WMAC_TCR_TSFT_OFS (Offset 0x0630) */
+#define BIT_SHIFT_WMAC_TCR_TSFT_OFS 0
+#define BIT_MASK_WMAC_TCR_TSFT_OFS 0xffff
+#define BIT_WMAC_TCR_TSFT_OFS(x) \
+ (((x) & BIT_MASK_WMAC_TCR_TSFT_OFS) << BIT_SHIFT_WMAC_TCR_TSFT_OFS)
+#define BITS_WMAC_TCR_TSFT_OFS \
+ (BIT_MASK_WMAC_TCR_TSFT_OFS << BIT_SHIFT_WMAC_TCR_TSFT_OFS)
+#define BIT_CLEAR_WMAC_TCR_TSFT_OFS(x) ((x) & (~BITS_WMAC_TCR_TSFT_OFS))
+#define BIT_GET_WMAC_TCR_TSFT_OFS(x) \
+ (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS) & BIT_MASK_WMAC_TCR_TSFT_OFS)
+#define BIT_SET_WMAC_TCR_TSFT_OFS(x, v) \
+ (BIT_CLEAR_WMAC_TCR_TSFT_OFS(x) | BIT_WMAC_TCR_TSFT_OFS(v))
-/* 2 REG_CTS2TO (Offset 0x0641) */
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_CTS2TO 0
-#define BIT_MASK_CTS2TO 0xff
-#define BIT_CTS2TO(x) (((x) & BIT_MASK_CTS2TO) << BIT_SHIFT_CTS2TO)
-#define BIT_GET_CTS2TO(x) (((x) >> BIT_SHIFT_CTS2TO) & BIT_MASK_CTS2TO)
+/* 2 REG_UDF_THSD (Offset 0x0632) */
+#define BIT_UDF_THSD_V1 BIT(7)
-/* 2 REG_EIFS (Offset 0x0642) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_EIFS 0
-#define BIT_MASK_EIFS 0xffff
-#define BIT_EIFS(x) (((x) & BIT_MASK_EIFS) << BIT_SHIFT_EIFS)
-#define BIT_GET_EIFS(x) (((x) >> BIT_SHIFT_EIFS) & BIT_MASK_EIFS)
+/* 2 REG_UDF_THSD (Offset 0x0632) */
+#define BIT_SHIFT_UDF_THSD 0
+#define BIT_MASK_UDF_THSD 0xff
+#define BIT_UDF_THSD(x) (((x) & BIT_MASK_UDF_THSD) << BIT_SHIFT_UDF_THSD)
+#define BITS_UDF_THSD (BIT_MASK_UDF_THSD << BIT_SHIFT_UDF_THSD)
+#define BIT_CLEAR_UDF_THSD(x) ((x) & (~BITS_UDF_THSD))
+#define BIT_GET_UDF_THSD(x) (((x) >> BIT_SHIFT_UDF_THSD) & BIT_MASK_UDF_THSD)
+#define BIT_SET_UDF_THSD(x, v) (BIT_CLEAR_UDF_THSD(x) | BIT_UDF_THSD(v))
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT)
-
-
-/* 2 REG_RPFM_MAP0 (Offset 0x0644) */
+/* 2 REG_UDF_THSD (Offset 0x0632) */
-#define BIT_MGT_RPFM15EN BIT(15)
-#define BIT_MGT_RPFM14EN BIT(14)
-#define BIT_MGT_RPFM13EN BIT(13)
-#define BIT_MGT_RPFM12EN BIT(12)
-#define BIT_MGT_RPFM11EN BIT(11)
-#define BIT_MGT_RPFM10EN BIT(10)
-#define BIT_MGT_RPFM9EN BIT(9)
-#define BIT_MGT_RPFM8EN BIT(8)
-#define BIT_MGT_RPFM7EN BIT(7)
-#define BIT_MGT_RPFM6EN BIT(6)
-#define BIT_MGT_RPFM5EN BIT(5)
-#define BIT_MGT_RPFM4EN BIT(4)
-#define BIT_MGT_RPFM3EN BIT(3)
-#define BIT_MGT_RPFM2EN BIT(2)
-#define BIT_MGT_RPFM1EN BIT(1)
-#define BIT_MGT_RPFM0EN BIT(0)
+#define BIT_SHIFT_UDF_THSD_VALUE 0
+#define BIT_MASK_UDF_THSD_VALUE 0x7f
+#define BIT_UDF_THSD_VALUE(x) \
+ (((x) & BIT_MASK_UDF_THSD_VALUE) << BIT_SHIFT_UDF_THSD_VALUE)
+#define BITS_UDF_THSD_VALUE \
+ (BIT_MASK_UDF_THSD_VALUE << BIT_SHIFT_UDF_THSD_VALUE)
+#define BIT_CLEAR_UDF_THSD_VALUE(x) ((x) & (~BITS_UDF_THSD_VALUE))
+#define BIT_GET_UDF_THSD_VALUE(x) \
+ (((x) >> BIT_SHIFT_UDF_THSD_VALUE) & BIT_MASK_UDF_THSD_VALUE)
+#define BIT_SET_UDF_THSD_VALUE(x, v) \
+ (BIT_CLEAR_UDF_THSD_VALUE(x) | BIT_UDF_THSD_VALUE(v))
-/* 2 REG_RPFM_CAM_CMD (Offset 0x0648) */
+#endif
-#define BIT_RPFM_CAM_POLLING BIT(31)
-#define BIT_RPFM_CAM_CLR BIT(30)
-#define BIT_RPFM_CAM_WE BIT(16)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_RPFM_CAM_ADDR 0
-#define BIT_MASK_RPFM_CAM_ADDR 0x7f
-#define BIT_RPFM_CAM_ADDR(x) (((x) & BIT_MASK_RPFM_CAM_ADDR) << BIT_SHIFT_RPFM_CAM_ADDR)
-#define BIT_GET_RPFM_CAM_ADDR(x) (((x) >> BIT_SHIFT_RPFM_CAM_ADDR) & BIT_MASK_RPFM_CAM_ADDR)
+/* 2 REG_ZLD_NUM (Offset 0x0633) */
+#define BIT_SHIFT_ZLD_NUM 0
+#define BIT_MASK_ZLD_NUM 0xff
+#define BIT_ZLD_NUM(x) (((x) & BIT_MASK_ZLD_NUM) << BIT_SHIFT_ZLD_NUM)
+#define BITS_ZLD_NUM (BIT_MASK_ZLD_NUM << BIT_SHIFT_ZLD_NUM)
+#define BIT_CLEAR_ZLD_NUM(x) ((x) & (~BITS_ZLD_NUM))
+#define BIT_GET_ZLD_NUM(x) (((x) >> BIT_SHIFT_ZLD_NUM) & BIT_MASK_ZLD_NUM)
+#define BIT_SET_ZLD_NUM(x, v) (BIT_CLEAR_ZLD_NUM(x) | BIT_ZLD_NUM(v))
-/* 2 REG_RPFM_CAM_RWD (Offset 0x064C) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_RPFM_CAM_RWD 0
-#define BIT_MASK_RPFM_CAM_RWD 0xffffffffL
-#define BIT_RPFM_CAM_RWD(x) (((x) & BIT_MASK_RPFM_CAM_RWD) << BIT_SHIFT_RPFM_CAM_RWD)
-#define BIT_GET_RPFM_CAM_RWD(x) (((x) >> BIT_SHIFT_RPFM_CAM_RWD) & BIT_MASK_RPFM_CAM_RWD)
+/* 2 REG_MCU_TEST_2 (Offset 0x0634) */
+#define BIT_SHIFT_MCU_RSVD_2 0
+#define BIT_MASK_MCU_RSVD_2 0xffffffffL
+#define BIT_MCU_RSVD_2(x) (((x) & BIT_MASK_MCU_RSVD_2) << BIT_SHIFT_MCU_RSVD_2)
+#define BITS_MCU_RSVD_2 (BIT_MASK_MCU_RSVD_2 << BIT_SHIFT_MCU_RSVD_2)
+#define BIT_CLEAR_MCU_RSVD_2(x) ((x) & (~BITS_MCU_RSVD_2))
+#define BIT_GET_MCU_RSVD_2(x) \
+ (((x) >> BIT_SHIFT_MCU_RSVD_2) & BIT_MASK_MCU_RSVD_2)
+#define BIT_SET_MCU_RSVD_2(x, v) (BIT_CLEAR_MCU_RSVD_2(x) | BIT_MCU_RSVD_2(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_STMP_THSD (Offset 0x0634) */
+#define BIT_SHIFT_STMP_THSD 0
+#define BIT_MASK_STMP_THSD 0xff
+#define BIT_STMP_THSD(x) (((x) & BIT_MASK_STMP_THSD) << BIT_SHIFT_STMP_THSD)
+#define BITS_STMP_THSD (BIT_MASK_STMP_THSD << BIT_SHIFT_STMP_THSD)
+#define BIT_CLEAR_STMP_THSD(x) ((x) & (~BITS_STMP_THSD))
+#define BIT_GET_STMP_THSD(x) (((x) >> BIT_SHIFT_STMP_THSD) & BIT_MASK_STMP_THSD)
+#define BIT_SET_STMP_THSD(x, v) (BIT_CLEAR_STMP_THSD(x) | BIT_STMP_THSD(v))
-/* 2 REG_NAV_CTRL (Offset 0x0650) */
+/* 2 REG_WMAC_TXTIMEOUT (Offset 0x0635) */
+#define BIT_SHIFT_WMAC_TXTIMEOUT 0
+#define BIT_MASK_WMAC_TXTIMEOUT 0xff
+#define BIT_WMAC_TXTIMEOUT(x) \
+ (((x) & BIT_MASK_WMAC_TXTIMEOUT) << BIT_SHIFT_WMAC_TXTIMEOUT)
+#define BITS_WMAC_TXTIMEOUT \
+ (BIT_MASK_WMAC_TXTIMEOUT << BIT_SHIFT_WMAC_TXTIMEOUT)
+#define BIT_CLEAR_WMAC_TXTIMEOUT(x) ((x) & (~BITS_WMAC_TXTIMEOUT))
+#define BIT_GET_WMAC_TXTIMEOUT(x) \
+ (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT) & BIT_MASK_WMAC_TXTIMEOUT)
+#define BIT_SET_WMAC_TXTIMEOUT(x, v) \
+ (BIT_CLEAR_WMAC_TXTIMEOUT(x) | BIT_WMAC_TXTIMEOUT(v))
-#define BIT_SHIFT_NAV_UPPER 16
-#define BIT_MASK_NAV_UPPER 0xff
-#define BIT_NAV_UPPER(x) (((x) & BIT_MASK_NAV_UPPER) << BIT_SHIFT_NAV_UPPER)
-#define BIT_GET_NAV_UPPER(x) (((x) >> BIT_SHIFT_NAV_UPPER) & BIT_MASK_NAV_UPPER)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_RXMYRTS_NAV 8
-#define BIT_MASK_RXMYRTS_NAV 0xf
-#define BIT_RXMYRTS_NAV(x) (((x) & BIT_MASK_RXMYRTS_NAV) << BIT_SHIFT_RXMYRTS_NAV)
-#define BIT_GET_RXMYRTS_NAV(x) (((x) >> BIT_SHIFT_RXMYRTS_NAV) & BIT_MASK_RXMYRTS_NAV)
+/* 2 REG_MCU_TEST_2_V1 (Offset 0x0636) */
+#define BIT_SHIFT_MCU_RSVD_2_V1 0
+#define BIT_MASK_MCU_RSVD_2_V1 0xffff
+#define BIT_MCU_RSVD_2_V1(x) \
+ (((x) & BIT_MASK_MCU_RSVD_2_V1) << BIT_SHIFT_MCU_RSVD_2_V1)
+#define BITS_MCU_RSVD_2_V1 (BIT_MASK_MCU_RSVD_2_V1 << BIT_SHIFT_MCU_RSVD_2_V1)
+#define BIT_CLEAR_MCU_RSVD_2_V1(x) ((x) & (~BITS_MCU_RSVD_2_V1))
+#define BIT_GET_MCU_RSVD_2_V1(x) \
+ (((x) >> BIT_SHIFT_MCU_RSVD_2_V1) & BIT_MASK_MCU_RSVD_2_V1)
+#define BIT_SET_MCU_RSVD_2_V1(x, v) \
+ (BIT_CLEAR_MCU_RSVD_2_V1(x) | BIT_MCU_RSVD_2_V1(v))
-#define BIT_SHIFT_RTSRST 0
-#define BIT_MASK_RTSRST 0xff
-#define BIT_RTSRST(x) (((x) & BIT_MASK_RTSRST) << BIT_SHIFT_RTSRST)
-#define BIT_GET_RTSRST(x) (((x) >> BIT_SHIFT_RTSRST) & BIT_MASK_RTSRST)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_BACAMCMD (Offset 0x0654) */
+/* 2 REG_USTIME_EDCA (Offset 0x0638) */
-#define BIT_BACAM_POLL BIT(31)
-#define BIT_BACAM_RST BIT(17)
-#define BIT_BACAM_RW BIT(16)
+#define BIT_SHIFT_USTIME_EDCA 0
+#define BIT_MASK_USTIME_EDCA 0xff
+#define BIT_USTIME_EDCA(x) \
+ (((x) & BIT_MASK_USTIME_EDCA) << BIT_SHIFT_USTIME_EDCA)
+#define BITS_USTIME_EDCA (BIT_MASK_USTIME_EDCA << BIT_SHIFT_USTIME_EDCA)
+#define BIT_CLEAR_USTIME_EDCA(x) ((x) & (~BITS_USTIME_EDCA))
+#define BIT_GET_USTIME_EDCA(x) \
+ (((x) >> BIT_SHIFT_USTIME_EDCA) & BIT_MASK_USTIME_EDCA)
+#define BIT_SET_USTIME_EDCA(x, v) \
+ (BIT_CLEAR_USTIME_EDCA(x) | BIT_USTIME_EDCA(v))
-#define BIT_SHIFT_TXSBM 14
-#define BIT_MASK_TXSBM 0x3
-#define BIT_TXSBM(x) (((x) & BIT_MASK_TXSBM) << BIT_SHIFT_TXSBM)
-#define BIT_GET_TXSBM(x) (((x) >> BIT_SHIFT_TXSBM) & BIT_MASK_TXSBM)
+#endif
+#if (HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_BACAM_ADDR 0
-#define BIT_MASK_BACAM_ADDR 0x3f
-#define BIT_BACAM_ADDR(x) (((x) & BIT_MASK_BACAM_ADDR) << BIT_SHIFT_BACAM_ADDR)
-#define BIT_GET_BACAM_ADDR(x) (((x) >> BIT_SHIFT_BACAM_ADDR) & BIT_MASK_BACAM_ADDR)
+/* 2 REG_USTIME_EDCA (Offset 0x0638) */
+#define BIT_SHIFT_USTIME_EDCA_V1 0
+#define BIT_MASK_USTIME_EDCA_V1 0x1ff
+#define BIT_USTIME_EDCA_V1(x) \
+ (((x) & BIT_MASK_USTIME_EDCA_V1) << BIT_SHIFT_USTIME_EDCA_V1)
+#define BITS_USTIME_EDCA_V1 \
+ (BIT_MASK_USTIME_EDCA_V1 << BIT_SHIFT_USTIME_EDCA_V1)
+#define BIT_CLEAR_USTIME_EDCA_V1(x) ((x) & (~BITS_USTIME_EDCA_V1))
+#define BIT_GET_USTIME_EDCA_V1(x) \
+ (((x) >> BIT_SHIFT_USTIME_EDCA_V1) & BIT_MASK_USTIME_EDCA_V1)
+#define BIT_SET_USTIME_EDCA_V1(x, v) \
+ (BIT_CLEAR_USTIME_EDCA_V1(x) | BIT_USTIME_EDCA_V1(v))
-/* 2 REG_BACAMCONTENT (Offset 0x0658) */
+#endif
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_BA_CONTENT_H (32 & CPU_OPT_WIDTH)
-#define BIT_MASK_BA_CONTENT_H 0xffffffffL
-#define BIT_BA_CONTENT_H(x) (((x) & BIT_MASK_BA_CONTENT_H) << BIT_SHIFT_BA_CONTENT_H)
-#define BIT_GET_BA_CONTENT_H(x) (((x) >> BIT_SHIFT_BA_CONTENT_H) & BIT_MASK_BA_CONTENT_H)
+/* 2 REG_ACKTO_CCK (Offset 0x0639) */
+#define BIT_SHIFT_ACKTO_CCK 0
+#define BIT_MASK_ACKTO_CCK 0xff
+#define BIT_ACKTO_CCK(x) (((x) & BIT_MASK_ACKTO_CCK) << BIT_SHIFT_ACKTO_CCK)
+#define BITS_ACKTO_CCK (BIT_MASK_ACKTO_CCK << BIT_SHIFT_ACKTO_CCK)
+#define BIT_CLEAR_ACKTO_CCK(x) ((x) & (~BITS_ACKTO_CCK))
+#define BIT_GET_ACKTO_CCK(x) (((x) >> BIT_SHIFT_ACKTO_CCK) & BIT_MASK_ACKTO_CCK)
+#define BIT_SET_ACKTO_CCK(x, v) (BIT_CLEAR_ACKTO_CCK(x) | BIT_ACKTO_CCK(v))
-#define BIT_SHIFT_BA_CONTENT_L 0
-#define BIT_MASK_BA_CONTENT_L 0xffffffffL
-#define BIT_BA_CONTENT_L(x) (((x) & BIT_MASK_BA_CONTENT_L) << BIT_SHIFT_BA_CONTENT_L)
-#define BIT_GET_BA_CONTENT_L(x) (((x) >> BIT_SHIFT_BA_CONTENT_L) & BIT_MASK_BA_CONTENT_L)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-/* 2 REG_LBDLY (Offset 0x0660) */
+/* 2 REG_MAC_SPEC_SIFS (Offset 0x063A) */
+#define BIT_SHIFT_SPEC_SIFS_OFDM 8
+#define BIT_MASK_SPEC_SIFS_OFDM 0xff
+#define BIT_SPEC_SIFS_OFDM(x) \
+ (((x) & BIT_MASK_SPEC_SIFS_OFDM) << BIT_SHIFT_SPEC_SIFS_OFDM)
+#define BITS_SPEC_SIFS_OFDM \
+ (BIT_MASK_SPEC_SIFS_OFDM << BIT_SHIFT_SPEC_SIFS_OFDM)
+#define BIT_CLEAR_SPEC_SIFS_OFDM(x) ((x) & (~BITS_SPEC_SIFS_OFDM))
+#define BIT_GET_SPEC_SIFS_OFDM(x) \
+ (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM) & BIT_MASK_SPEC_SIFS_OFDM)
+#define BIT_SET_SPEC_SIFS_OFDM(x, v) \
+ (BIT_CLEAR_SPEC_SIFS_OFDM(x) | BIT_SPEC_SIFS_OFDM(v))
+
+#define BIT_SHIFT_SPEC_SIFS_CCK 0
+#define BIT_MASK_SPEC_SIFS_CCK 0xff
+#define BIT_SPEC_SIFS_CCK(x) \
+ (((x) & BIT_MASK_SPEC_SIFS_CCK) << BIT_SHIFT_SPEC_SIFS_CCK)
+#define BITS_SPEC_SIFS_CCK (BIT_MASK_SPEC_SIFS_CCK << BIT_SHIFT_SPEC_SIFS_CCK)
+#define BIT_CLEAR_SPEC_SIFS_CCK(x) ((x) & (~BITS_SPEC_SIFS_CCK))
+#define BIT_GET_SPEC_SIFS_CCK(x) \
+ (((x) >> BIT_SHIFT_SPEC_SIFS_CCK) & BIT_MASK_SPEC_SIFS_CCK)
+#define BIT_SET_SPEC_SIFS_CCK(x, v) \
+ (BIT_CLEAR_SPEC_SIFS_CCK(x) | BIT_SPEC_SIFS_CCK(v))
-#define BIT_SHIFT_LBDLY 0
-#define BIT_MASK_LBDLY 0x1f
-#define BIT_LBDLY(x) (((x) & BIT_MASK_LBDLY) << BIT_SHIFT_LBDLY)
-#define BIT_GET_LBDLY(x) (((x) >> BIT_SHIFT_LBDLY) & BIT_MASK_LBDLY)
+/* 2 REG_RESP_SIFS_CCK (Offset 0x063C) */
+#define BIT_SHIFT_SIFS_R2T_CCK 8
+#define BIT_MASK_SIFS_R2T_CCK 0xff
+#define BIT_SIFS_R2T_CCK(x) \
+ (((x) & BIT_MASK_SIFS_R2T_CCK) << BIT_SHIFT_SIFS_R2T_CCK)
+#define BITS_SIFS_R2T_CCK (BIT_MASK_SIFS_R2T_CCK << BIT_SHIFT_SIFS_R2T_CCK)
+#define BIT_CLEAR_SIFS_R2T_CCK(x) ((x) & (~BITS_SIFS_R2T_CCK))
+#define BIT_GET_SIFS_R2T_CCK(x) \
+ (((x) >> BIT_SHIFT_SIFS_R2T_CCK) & BIT_MASK_SIFS_R2T_CCK)
+#define BIT_SET_SIFS_R2T_CCK(x, v) \
+ (BIT_CLEAR_SIFS_R2T_CCK(x) | BIT_SIFS_R2T_CCK(v))
+
+#define BIT_SHIFT_SIFS_T2T_CCK 0
+#define BIT_MASK_SIFS_T2T_CCK 0xff
+#define BIT_SIFS_T2T_CCK(x) \
+ (((x) & BIT_MASK_SIFS_T2T_CCK) << BIT_SHIFT_SIFS_T2T_CCK)
+#define BITS_SIFS_T2T_CCK (BIT_MASK_SIFS_T2T_CCK << BIT_SHIFT_SIFS_T2T_CCK)
+#define BIT_CLEAR_SIFS_T2T_CCK(x) ((x) & (~BITS_SIFS_T2T_CCK))
+#define BIT_GET_SIFS_T2T_CCK(x) \
+ (((x) >> BIT_SHIFT_SIFS_T2T_CCK) & BIT_MASK_SIFS_T2T_CCK)
+#define BIT_SET_SIFS_T2T_CCK(x, v) \
+ (BIT_CLEAR_SIFS_T2T_CCK(x) | BIT_SIFS_T2T_CCK(v))
-#endif
+/* 2 REG_RESP_SIFS_OFDM (Offset 0x063E) */
+#define BIT_SHIFT_SIFS_R2T_OFDM 8
+#define BIT_MASK_SIFS_R2T_OFDM 0xff
+#define BIT_SIFS_R2T_OFDM(x) \
+ (((x) & BIT_MASK_SIFS_R2T_OFDM) << BIT_SHIFT_SIFS_R2T_OFDM)
+#define BITS_SIFS_R2T_OFDM (BIT_MASK_SIFS_R2T_OFDM << BIT_SHIFT_SIFS_R2T_OFDM)
+#define BIT_CLEAR_SIFS_R2T_OFDM(x) ((x) & (~BITS_SIFS_R2T_OFDM))
+#define BIT_GET_SIFS_R2T_OFDM(x) \
+ (((x) >> BIT_SHIFT_SIFS_R2T_OFDM) & BIT_MASK_SIFS_R2T_OFDM)
+#define BIT_SET_SIFS_R2T_OFDM(x, v) \
+ (BIT_CLEAR_SIFS_R2T_OFDM(x) | BIT_SIFS_R2T_OFDM(v))
+
+#define BIT_SHIFT_SIFS_T2T_OFDM 0
+#define BIT_MASK_SIFS_T2T_OFDM 0xff
+#define BIT_SIFS_T2T_OFDM(x) \
+ (((x) & BIT_MASK_SIFS_T2T_OFDM) << BIT_SHIFT_SIFS_T2T_OFDM)
+#define BITS_SIFS_T2T_OFDM (BIT_MASK_SIFS_T2T_OFDM << BIT_SHIFT_SIFS_T2T_OFDM)
+#define BIT_CLEAR_SIFS_T2T_OFDM(x) ((x) & (~BITS_SIFS_T2T_OFDM))
+#define BIT_GET_SIFS_T2T_OFDM(x) \
+ (((x) >> BIT_SHIFT_SIFS_T2T_OFDM) & BIT_MASK_SIFS_T2T_OFDM)
+#define BIT_SET_SIFS_T2T_OFDM(x, v) \
+ (BIT_CLEAR_SIFS_T2T_OFDM(x) | BIT_SIFS_T2T_OFDM(v))
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ACKTO (Offset 0x0640) */
+#define BIT_SHIFT_ACKTO 0
+#define BIT_MASK_ACKTO 0xff
+#define BIT_ACKTO(x) (((x) & BIT_MASK_ACKTO) << BIT_SHIFT_ACKTO)
+#define BITS_ACKTO (BIT_MASK_ACKTO << BIT_SHIFT_ACKTO)
+#define BIT_CLEAR_ACKTO(x) ((x) & (~BITS_ACKTO))
+#define BIT_GET_ACKTO(x) (((x) >> BIT_SHIFT_ACKTO) & BIT_MASK_ACKTO)
+#define BIT_SET_ACKTO(x, v) (BIT_CLEAR_ACKTO(x) | BIT_ACKTO(v))
-/* 2 REG_WMAC_BACAM_RPMEN (Offset 0x0661) */
+/* 2 REG_CTS2TO (Offset 0x0641) */
+#define BIT_SHIFT_CTS2TO 0
+#define BIT_MASK_CTS2TO 0xff
+#define BIT_CTS2TO(x) (((x) & BIT_MASK_CTS2TO) << BIT_SHIFT_CTS2TO)
+#define BITS_CTS2TO (BIT_MASK_CTS2TO << BIT_SHIFT_CTS2TO)
+#define BIT_CLEAR_CTS2TO(x) ((x) & (~BITS_CTS2TO))
+#define BIT_GET_CTS2TO(x) (((x) >> BIT_SHIFT_CTS2TO) & BIT_MASK_CTS2TO)
+#define BIT_SET_CTS2TO(x, v) (BIT_CLEAR_CTS2TO(x) | BIT_CTS2TO(v))
-#define BIT_SHIFT_BITMAP_SSNBK_COUNTER 2
-#define BIT_MASK_BITMAP_SSNBK_COUNTER 0x3f
-#define BIT_BITMAP_SSNBK_COUNTER(x) (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER) << BIT_SHIFT_BITMAP_SSNBK_COUNTER)
-#define BIT_GET_BITMAP_SSNBK_COUNTER(x) (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER) & BIT_MASK_BITMAP_SSNBK_COUNTER)
+/* 2 REG_EIFS (Offset 0x0642) */
-#define BIT_BITMAP_EN BIT(1)
+#define BIT_SHIFT_EIFS 0
+#define BIT_MASK_EIFS 0xffff
+#define BIT_EIFS(x) (((x) & BIT_MASK_EIFS) << BIT_SHIFT_EIFS)
+#define BITS_EIFS (BIT_MASK_EIFS << BIT_SHIFT_EIFS)
+#define BIT_CLEAR_EIFS(x) ((x) & (~BITS_EIFS))
+#define BIT_GET_EIFS(x) (((x) >> BIT_SHIFT_EIFS) & BIT_MASK_EIFS)
+#define BIT_SET_EIFS(x, v) (BIT_CLEAR_EIFS(x) | BIT_EIFS(v))
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_WMAC_BACAM_RPMEN (Offset 0x0661) */
+/* 2 REG_RPFM_MAP0 (Offset 0x0644) */
-#define BIT_WMAC_BACAM_RPMEN BIT(0)
+#define BIT_MGT_RPFM15EN BIT(15)
+#define BIT_MGT_RPFM14EN BIT(14)
+#define BIT_MGT_RPFM13EN BIT(13)
+#define BIT_MGT_RPFM12EN BIT(12)
+#define BIT_MGT_RPFM11EN BIT(11)
+#define BIT_MGT_RPFM10EN BIT(10)
+#define BIT_MGT_RPFM9EN BIT(9)
+#define BIT_MGT_RPFM8EN BIT(8)
+#define BIT_MGT_RPFM7EN BIT(7)
+#define BIT_MGT_RPFM6EN BIT(6)
+#define BIT_MGT_RPFM5EN BIT(5)
+#define BIT_MGT_RPFM4EN BIT(4)
+#define BIT_MGT_RPFM3EN BIT(3)
+#define BIT_MGT_RPFM2EN BIT(2)
+#define BIT_MGT_RPFM1EN BIT(1)
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_RPFM_MAP0 (Offset 0x0644) */
+#define BIT_SHIFT_RPFM_MAP0 0
+#define BIT_MASK_RPFM_MAP0 0xffff
+#define BIT_RPFM_MAP0(x) (((x) & BIT_MASK_RPFM_MAP0) << BIT_SHIFT_RPFM_MAP0)
+#define BITS_RPFM_MAP0 (BIT_MASK_RPFM_MAP0 << BIT_SHIFT_RPFM_MAP0)
+#define BIT_CLEAR_RPFM_MAP0(x) ((x) & (~BITS_RPFM_MAP0))
+#define BIT_GET_RPFM_MAP0(x) (((x) >> BIT_SHIFT_RPFM_MAP0) & BIT_MASK_RPFM_MAP0)
+#define BIT_SET_RPFM_MAP0(x, v) (BIT_CLEAR_RPFM_MAP0(x) | BIT_RPFM_MAP0(v))
-/* 2 REG_TX_RX (Offset 0x0662) */
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_RXPKT_TYPE 2
-#define BIT_MASK_RXPKT_TYPE 0x3f
-#define BIT_RXPKT_TYPE(x) (((x) & BIT_MASK_RXPKT_TYPE) << BIT_SHIFT_RXPKT_TYPE)
-#define BIT_GET_RXPKT_TYPE(x) (((x) >> BIT_SHIFT_RXPKT_TYPE) & BIT_MASK_RXPKT_TYPE)
+/* 2 REG_RPFM_MAP0 (Offset 0x0644) */
-#define BIT_TXACT_IND BIT(1)
-#define BIT_RXACT_IND BIT(0)
+#define BIT_MGT_RPFM0EN BIT(0)
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_RPFM_MAP1 (Offset 0x0646) */
+#define BIT_SHIFT_RPFM_MAP1 0
+#define BIT_MASK_RPFM_MAP1 0xffff
+#define BIT_RPFM_MAP1(x) (((x) & BIT_MASK_RPFM_MAP1) << BIT_SHIFT_RPFM_MAP1)
+#define BITS_RPFM_MAP1 (BIT_MASK_RPFM_MAP1 << BIT_SHIFT_RPFM_MAP1)
+#define BIT_CLEAR_RPFM_MAP1(x) ((x) & (~BITS_RPFM_MAP1))
+#define BIT_GET_RPFM_MAP1(x) (((x) >> BIT_SHIFT_RPFM_MAP1) & BIT_MASK_RPFM_MAP1)
+#define BIT_SET_RPFM_MAP1(x, v) (BIT_CLEAR_RPFM_MAP1(x) | BIT_RPFM_MAP1(v))
-/* 2 REG_RXERR_RPT (Offset 0x0664) */
+#endif
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0 28
-#define BIT_MASK_RXERR_RPT_SEL_V1_3_0 0xf
-#define BIT_RXERR_RPT_SEL_V1_3_0(x) (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0) << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0)
-#define BIT_GET_RXERR_RPT_SEL_V1_3_0(x) (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0) & BIT_MASK_RXERR_RPT_SEL_V1_3_0)
+/* 2 REG_RPFM_CAM_CMD (Offset 0x0648) */
+#define BIT_RPFM_CAM_POLLING BIT(31)
+#define BIT_RPFM_CAM_CLR BIT(30)
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8881A_SUPPORT)
+/* 2 REG_RPFM_CAM_CMD (Offset 0x0648) */
+#define BIT_RPFM_CAM_WR BIT(16)
-/* 2 REG_RXERR_RPT (Offset 0x0664) */
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_RXERR_RPT_SEL 28
-#define BIT_MASK_RXERR_RPT_SEL 0xf
-#define BIT_RXERR_RPT_SEL(x) (((x) & BIT_MASK_RXERR_RPT_SEL) << BIT_SHIFT_RXERR_RPT_SEL)
-#define BIT_GET_RXERR_RPT_SEL(x) (((x) >> BIT_SHIFT_RXERR_RPT_SEL) & BIT_MASK_RXERR_RPT_SEL)
+/* 2 REG_RPFM_CAM_CMD (Offset 0x0648) */
+#define BIT_RPFM_CAM_WE BIT(16)
#endif
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_RPFM_CAM_CMD (Offset 0x0648) */
+#define BIT_SHIFT_RPFM_CAM_ADDR 0
+#define BIT_MASK_RPFM_CAM_ADDR 0x7f
+#define BIT_RPFM_CAM_ADDR(x) \
+ (((x) & BIT_MASK_RPFM_CAM_ADDR) << BIT_SHIFT_RPFM_CAM_ADDR)
+#define BITS_RPFM_CAM_ADDR (BIT_MASK_RPFM_CAM_ADDR << BIT_SHIFT_RPFM_CAM_ADDR)
+#define BIT_CLEAR_RPFM_CAM_ADDR(x) ((x) & (~BITS_RPFM_CAM_ADDR))
+#define BIT_GET_RPFM_CAM_ADDR(x) \
+ (((x) >> BIT_SHIFT_RPFM_CAM_ADDR) & BIT_MASK_RPFM_CAM_ADDR)
+#define BIT_SET_RPFM_CAM_ADDR(x, v) \
+ (BIT_CLEAR_RPFM_CAM_ADDR(x) | BIT_RPFM_CAM_ADDR(v))
-/* 2 REG_RXERR_RPT (Offset 0x0664) */
+/* 2 REG_RPFM_CAM_RWD (Offset 0x064C) */
-#define BIT_RXERR_RPT_RST BIT(27)
+#define BIT_SHIFT_RPFM_CAM_RWD 0
+#define BIT_MASK_RPFM_CAM_RWD 0xffffffffL
+#define BIT_RPFM_CAM_RWD(x) \
+ (((x) & BIT_MASK_RPFM_CAM_RWD) << BIT_SHIFT_RPFM_CAM_RWD)
+#define BITS_RPFM_CAM_RWD (BIT_MASK_RPFM_CAM_RWD << BIT_SHIFT_RPFM_CAM_RWD)
+#define BIT_CLEAR_RPFM_CAM_RWD(x) ((x) & (~BITS_RPFM_CAM_RWD))
+#define BIT_GET_RPFM_CAM_RWD(x) \
+ (((x) >> BIT_SHIFT_RPFM_CAM_RWD) & BIT_MASK_RPFM_CAM_RWD)
+#define BIT_SET_RPFM_CAM_RWD(x, v) \
+ (BIT_CLEAR_RPFM_CAM_RWD(x) | BIT_RPFM_CAM_RWD(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+/* 2 REG_NAV_CTRL (Offset 0x0650) */
-/* 2 REG_RXERR_RPT (Offset 0x0664) */
+#define BIT_SHIFT_NAV_UPPER 16
+#define BIT_MASK_NAV_UPPER 0xff
+#define BIT_NAV_UPPER(x) (((x) & BIT_MASK_NAV_UPPER) << BIT_SHIFT_NAV_UPPER)
+#define BITS_NAV_UPPER (BIT_MASK_NAV_UPPER << BIT_SHIFT_NAV_UPPER)
+#define BIT_CLEAR_NAV_UPPER(x) ((x) & (~BITS_NAV_UPPER))
+#define BIT_GET_NAV_UPPER(x) (((x) >> BIT_SHIFT_NAV_UPPER) & BIT_MASK_NAV_UPPER)
+#define BIT_SET_NAV_UPPER(x, v) (BIT_CLEAR_NAV_UPPER(x) | BIT_NAV_UPPER(v))
+
+#define BIT_SHIFT_RXMYRTS_NAV 8
+#define BIT_MASK_RXMYRTS_NAV 0xf
+#define BIT_RXMYRTS_NAV(x) \
+ (((x) & BIT_MASK_RXMYRTS_NAV) << BIT_SHIFT_RXMYRTS_NAV)
+#define BITS_RXMYRTS_NAV (BIT_MASK_RXMYRTS_NAV << BIT_SHIFT_RXMYRTS_NAV)
+#define BIT_CLEAR_RXMYRTS_NAV(x) ((x) & (~BITS_RXMYRTS_NAV))
+#define BIT_GET_RXMYRTS_NAV(x) \
+ (((x) >> BIT_SHIFT_RXMYRTS_NAV) & BIT_MASK_RXMYRTS_NAV)
+#define BIT_SET_RXMYRTS_NAV(x, v) \
+ (BIT_CLEAR_RXMYRTS_NAV(x) | BIT_RXMYRTS_NAV(v))
+
+#define BIT_SHIFT_RTSRST 0
+#define BIT_MASK_RTSRST 0xff
+#define BIT_RTSRST(x) (((x) & BIT_MASK_RTSRST) << BIT_SHIFT_RTSRST)
+#define BITS_RTSRST (BIT_MASK_RTSRST << BIT_SHIFT_RTSRST)
+#define BIT_CLEAR_RTSRST(x) ((x) & (~BITS_RTSRST))
+#define BIT_GET_RTSRST(x) (((x) >> BIT_SHIFT_RTSRST) & BIT_MASK_RTSRST)
+#define BIT_SET_RTSRST(x, v) (BIT_CLEAR_RTSRST(x) | BIT_RTSRST(v))
-#define BIT_RXERR_RPT_SEL_V1_4 BIT(26)
+/* 2 REG_BACAMCMD (Offset 0x0654) */
-#endif
+#define BIT_BACAM_POLL BIT(31)
+#define BIT_BACAM_RST BIT(17)
+#define BIT_BACAM_RW BIT(16)
+
+#define BIT_SHIFT_TXSBM 14
+#define BIT_MASK_TXSBM 0x3
+#define BIT_TXSBM(x) (((x) & BIT_MASK_TXSBM) << BIT_SHIFT_TXSBM)
+#define BITS_TXSBM (BIT_MASK_TXSBM << BIT_SHIFT_TXSBM)
+#define BIT_CLEAR_TXSBM(x) ((x) & (~BITS_TXSBM))
+#define BIT_GET_TXSBM(x) (((x) >> BIT_SHIFT_TXSBM) & BIT_MASK_TXSBM)
+#define BIT_SET_TXSBM(x, v) (BIT_CLEAR_TXSBM(x) | BIT_TXSBM(v))
+
+#define BIT_SHIFT_BACAM_ADDR 0
+#define BIT_MASK_BACAM_ADDR 0x3f
+#define BIT_BACAM_ADDR(x) (((x) & BIT_MASK_BACAM_ADDR) << BIT_SHIFT_BACAM_ADDR)
+#define BITS_BACAM_ADDR (BIT_MASK_BACAM_ADDR << BIT_SHIFT_BACAM_ADDR)
+#define BIT_CLEAR_BACAM_ADDR(x) ((x) & (~BITS_BACAM_ADDR))
+#define BIT_GET_BACAM_ADDR(x) \
+ (((x) >> BIT_SHIFT_BACAM_ADDR) & BIT_MASK_BACAM_ADDR)
+#define BIT_SET_BACAM_ADDR(x, v) (BIT_CLEAR_BACAM_ADDR(x) | BIT_BACAM_ADDR(v))
+/* 2 REG_BACAMCONTENT (Offset 0x0658) */
-#if (HALMAC_8197F_SUPPORT)
+#define BIT_SHIFT_BA_CONTENT_L 0
+#define BIT_MASK_BA_CONTENT_L 0xffffffffL
+#define BIT_BA_CONTENT_L(x) \
+ (((x) & BIT_MASK_BA_CONTENT_L) << BIT_SHIFT_BA_CONTENT_L)
+#define BITS_BA_CONTENT_L (BIT_MASK_BA_CONTENT_L << BIT_SHIFT_BA_CONTENT_L)
+#define BIT_CLEAR_BA_CONTENT_L(x) ((x) & (~BITS_BA_CONTENT_L))
+#define BIT_GET_BA_CONTENT_L(x) \
+ (((x) >> BIT_SHIFT_BA_CONTENT_L) & BIT_MASK_BA_CONTENT_L)
+#define BIT_SET_BA_CONTENT_L(x, v) \
+ (BIT_CLEAR_BA_CONTENT_L(x) | BIT_BA_CONTENT_L(v))
+/* 2 REG_LBDLY (Offset 0x0660) */
-/* 2 REG_RXERR_RPT (Offset 0x0664) */
+#define BIT_SHIFT_LBDLY 0
+#define BIT_MASK_LBDLY 0x1f
+#define BIT_LBDLY(x) (((x) & BIT_MASK_LBDLY) << BIT_SHIFT_LBDLY)
+#define BITS_LBDLY (BIT_MASK_LBDLY << BIT_SHIFT_LBDLY)
+#define BIT_CLEAR_LBDLY(x) ((x) & (~BITS_LBDLY))
+#define BIT_GET_LBDLY(x) (((x) >> BIT_SHIFT_LBDLY) & BIT_MASK_LBDLY)
+#define BIT_SET_LBDLY(x, v) (BIT_CLEAR_LBDLY(x) | BIT_LBDLY(v))
+#endif
-#define BIT_SHIFT_UD_SELECT_BSSID_2_1 24
-#define BIT_MASK_UD_SELECT_BSSID_2_1 0x3
-#define BIT_UD_SELECT_BSSID_2_1(x) (((x) & BIT_MASK_UD_SELECT_BSSID_2_1) << BIT_SHIFT_UD_SELECT_BSSID_2_1)
-#define BIT_GET_UD_SELECT_BSSID_2_1(x) (((x) >> BIT_SHIFT_UD_SELECT_BSSID_2_1) & BIT_MASK_UD_SELECT_BSSID_2_1)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+/* 2 REG_WMAC_BACAM_RPMEN (Offset 0x0661) */
-#endif
+#define BIT_SHIFT_BITMAP_SSNBK_COUNTER 2
+#define BIT_MASK_BITMAP_SSNBK_COUNTER 0x3f
+#define BIT_BITMAP_SSNBK_COUNTER(x) \
+ (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER) \
+ << BIT_SHIFT_BITMAP_SSNBK_COUNTER)
+#define BITS_BITMAP_SSNBK_COUNTER \
+ (BIT_MASK_BITMAP_SSNBK_COUNTER << BIT_SHIFT_BITMAP_SSNBK_COUNTER)
+#define BIT_CLEAR_BITMAP_SSNBK_COUNTER(x) ((x) & (~BITS_BITMAP_SSNBK_COUNTER))
+#define BIT_GET_BITMAP_SSNBK_COUNTER(x) \
+ (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER) & \
+ BIT_MASK_BITMAP_SSNBK_COUNTER)
+#define BIT_SET_BITMAP_SSNBK_COUNTER(x, v) \
+ (BIT_CLEAR_BITMAP_SSNBK_COUNTER(x) | BIT_BITMAP_SSNBK_COUNTER(v))
+#define BIT_BITMAP_EN BIT(1)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_RXERR_RPT (Offset 0x0664) */
+/* 2 REG_WMAC_BACAM_RPMEN (Offset 0x0661) */
-#define BIT_W1S BIT(23)
+#define BIT_WMAC_BACAM_RPMEN BIT(0)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_TX_RX (Offset 0x0662) */
+#define BIT_SHIFT_RXPKT_TYPE 2
+#define BIT_MASK_RXPKT_TYPE 0x3f
+#define BIT_RXPKT_TYPE(x) (((x) & BIT_MASK_RXPKT_TYPE) << BIT_SHIFT_RXPKT_TYPE)
+#define BITS_RXPKT_TYPE (BIT_MASK_RXPKT_TYPE << BIT_SHIFT_RXPKT_TYPE)
+#define BIT_CLEAR_RXPKT_TYPE(x) ((x) & (~BITS_RXPKT_TYPE))
+#define BIT_GET_RXPKT_TYPE(x) \
+ (((x) >> BIT_SHIFT_RXPKT_TYPE) & BIT_MASK_RXPKT_TYPE)
+#define BIT_SET_RXPKT_TYPE(x, v) (BIT_CLEAR_RXPKT_TYPE(x) | BIT_RXPKT_TYPE(v))
-/* 2 REG_RXERR_RPT (Offset 0x0664) */
+#define BIT_TXACT_IND BIT(1)
+#define BIT_RXACT_IND BIT(0)
-#define BIT_UD_SELECT_BSSID BIT(22)
+/* 2 REG_WMAC_BITMAP_CTL (Offset 0x0663) */
-#endif
+#define BIT_BITMAP_VO BIT(7)
+#define BIT_BITMAP_VI BIT(6)
+#define BIT_BITMAP_BE BIT(5)
+#define BIT_BITMAP_BK BIT(4)
+#define BIT_SHIFT_BITMAP_CONDITION 2
+#define BIT_MASK_BITMAP_CONDITION 0x3
+#define BIT_BITMAP_CONDITION(x) \
+ (((x) & BIT_MASK_BITMAP_CONDITION) << BIT_SHIFT_BITMAP_CONDITION)
+#define BITS_BITMAP_CONDITION \
+ (BIT_MASK_BITMAP_CONDITION << BIT_SHIFT_BITMAP_CONDITION)
+#define BIT_CLEAR_BITMAP_CONDITION(x) ((x) & (~BITS_BITMAP_CONDITION))
+#define BIT_GET_BITMAP_CONDITION(x) \
+ (((x) >> BIT_SHIFT_BITMAP_CONDITION) & BIT_MASK_BITMAP_CONDITION)
+#define BIT_SET_BITMAP_CONDITION(x, v) \
+ (BIT_CLEAR_BITMAP_CONDITION(x) | BIT_BITMAP_CONDITION(v))
-#if (HALMAC_8197F_SUPPORT)
+#define BIT_BITMAP_SSNBK_COUNTER_CLR BIT(1)
+#define BIT_BITMAP_FORCE BIT(0)
+
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_RXERR_RPT (Offset 0x0664) */
-#define BIT_UD_SELECT_BSSID_0 BIT(22)
+#define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0 28
+#define BIT_MASK_RXERR_RPT_SEL_V1_3_0 0xf
+#define BIT_RXERR_RPT_SEL_V1_3_0(x) \
+ (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0) \
+ << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0)
+#define BITS_RXERR_RPT_SEL_V1_3_0 \
+ (BIT_MASK_RXERR_RPT_SEL_V1_3_0 << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0)
+#define BIT_CLEAR_RXERR_RPT_SEL_V1_3_0(x) ((x) & (~BITS_RXERR_RPT_SEL_V1_3_0))
+#define BIT_GET_RXERR_RPT_SEL_V1_3_0(x) \
+ (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0) & \
+ BIT_MASK_RXERR_RPT_SEL_V1_3_0)
+#define BIT_SET_RXERR_RPT_SEL_V1_3_0(x, v) \
+ (BIT_CLEAR_RXERR_RPT_SEL_V1_3_0(x) | BIT_RXERR_RPT_SEL_V1_3_0(v))
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8881A_SUPPORT)
/* 2 REG_RXERR_RPT (Offset 0x0664) */
+#define BIT_SHIFT_RXERR_RPT_SEL 28
+#define BIT_MASK_RXERR_RPT_SEL 0xf
+#define BIT_RXERR_RPT_SEL(x) \
+ (((x) & BIT_MASK_RXERR_RPT_SEL) << BIT_SHIFT_RXERR_RPT_SEL)
+#define BITS_RXERR_RPT_SEL (BIT_MASK_RXERR_RPT_SEL << BIT_SHIFT_RXERR_RPT_SEL)
+#define BIT_CLEAR_RXERR_RPT_SEL(x) ((x) & (~BITS_RXERR_RPT_SEL))
+#define BIT_GET_RXERR_RPT_SEL(x) \
+ (((x) >> BIT_SHIFT_RXERR_RPT_SEL) & BIT_MASK_RXERR_RPT_SEL)
+#define BIT_SET_RXERR_RPT_SEL(x, v) \
+ (BIT_CLEAR_RXERR_RPT_SEL(x) | BIT_RXERR_RPT_SEL(v))
-#define BIT_SHIFT_UD_SUB_TYPE 18
-#define BIT_MASK_UD_SUB_TYPE 0xf
-#define BIT_UD_SUB_TYPE(x) (((x) & BIT_MASK_UD_SUB_TYPE) << BIT_SHIFT_UD_SUB_TYPE)
-#define BIT_GET_UD_SUB_TYPE(x) (((x) >> BIT_SHIFT_UD_SUB_TYPE) & BIT_MASK_UD_SUB_TYPE)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_UD_TYPE 16
-#define BIT_MASK_UD_TYPE 0x3
-#define BIT_UD_TYPE(x) (((x) & BIT_MASK_UD_TYPE) << BIT_SHIFT_UD_TYPE)
-#define BIT_GET_UD_TYPE(x) (((x) >> BIT_SHIFT_UD_TYPE) & BIT_MASK_UD_TYPE)
+/* 2 REG_RXERR_RPT (Offset 0x0664) */
+#define BIT_RXERR_RPT_RST BIT(27)
-#define BIT_SHIFT_RPT_COUNTER 0
-#define BIT_MASK_RPT_COUNTER 0xffff
-#define BIT_RPT_COUNTER(x) (((x) & BIT_MASK_RPT_COUNTER) << BIT_SHIFT_RPT_COUNTER)
-#define BIT_GET_RPT_COUNTER(x) (((x) >> BIT_SHIFT_RPT_COUNTER) & BIT_MASK_RPT_COUNTER)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */
+/* 2 REG_RXERR_RPT (Offset 0x0664) */
+#define BIT_RXERR_RPT_SEL_V1_4 BIT(26)
-#define BIT_SHIFT_ACKBA_TYPSEL (60 & CPU_OPT_WIDTH)
-#define BIT_MASK_ACKBA_TYPSEL 0xf
-#define BIT_ACKBA_TYPSEL(x) (((x) & BIT_MASK_ACKBA_TYPSEL) << BIT_SHIFT_ACKBA_TYPSEL)
-#define BIT_GET_ACKBA_TYPSEL(x) (((x) >> BIT_SHIFT_ACKBA_TYPSEL) & BIT_MASK_ACKBA_TYPSEL)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_ACKBA_ACKPCHK (56 & CPU_OPT_WIDTH)
-#define BIT_MASK_ACKBA_ACKPCHK 0xf
-#define BIT_ACKBA_ACKPCHK(x) (((x) & BIT_MASK_ACKBA_ACKPCHK) << BIT_SHIFT_ACKBA_ACKPCHK)
-#define BIT_GET_ACKBA_ACKPCHK(x) (((x) >> BIT_SHIFT_ACKBA_ACKPCHK) & BIT_MASK_ACKBA_ACKPCHK)
+/* 2 REG_RXERR_RPT (Offset 0x0664) */
+#define BIT_SHIFT_UD_SELECT_BSSID_2_1 24
+#define BIT_MASK_UD_SELECT_BSSID_2_1 0x3
+#define BIT_UD_SELECT_BSSID_2_1(x) \
+ (((x) & BIT_MASK_UD_SELECT_BSSID_2_1) << BIT_SHIFT_UD_SELECT_BSSID_2_1)
+#define BITS_UD_SELECT_BSSID_2_1 \
+ (BIT_MASK_UD_SELECT_BSSID_2_1 << BIT_SHIFT_UD_SELECT_BSSID_2_1)
+#define BIT_CLEAR_UD_SELECT_BSSID_2_1(x) ((x) & (~BITS_UD_SELECT_BSSID_2_1))
+#define BIT_GET_UD_SELECT_BSSID_2_1(x) \
+ (((x) >> BIT_SHIFT_UD_SELECT_BSSID_2_1) & BIT_MASK_UD_SELECT_BSSID_2_1)
+#define BIT_SET_UD_SELECT_BSSID_2_1(x, v) \
+ (BIT_CLEAR_UD_SELECT_BSSID_2_1(x) | BIT_UD_SELECT_BSSID_2_1(v))
-#define BIT_SHIFT_ACKBAR_TYPESEL (48 & CPU_OPT_WIDTH)
-#define BIT_MASK_ACKBAR_TYPESEL 0xff
-#define BIT_ACKBAR_TYPESEL(x) (((x) & BIT_MASK_ACKBAR_TYPESEL) << BIT_SHIFT_ACKBAR_TYPESEL)
-#define BIT_GET_ACKBAR_TYPESEL(x) (((x) >> BIT_SHIFT_ACKBAR_TYPESEL) & BIT_MASK_ACKBAR_TYPESEL)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_ACKBAR_ACKPCHK (44 & CPU_OPT_WIDTH)
-#define BIT_MASK_ACKBAR_ACKPCHK 0xf
-#define BIT_ACKBAR_ACKPCHK(x) (((x) & BIT_MASK_ACKBAR_ACKPCHK) << BIT_SHIFT_ACKBAR_ACKPCHK)
-#define BIT_GET_ACKBAR_ACKPCHK(x) (((x) >> BIT_SHIFT_ACKBAR_ACKPCHK) & BIT_MASK_ACKBAR_ACKPCHK)
+/* 2 REG_RXERR_RPT (Offset 0x0664) */
+#define BIT_W1S BIT(23)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_RXERR_RPT (Offset 0x0664) */
+#define BIT_UD_SELECT_BSSID BIT(22)
-/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_RXBA_IGNOREA2 BIT(42)
-#define BIT_EN_SAVE_ALL_TXOPADDR BIT(41)
-#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV BIT(40)
+/* 2 REG_RXERR_RPT (Offset 0x0664) */
+
+#define BIT_UD_SELECT_BSSID_0 BIT(22)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_RXERR_RPT (Offset 0x0664) */
+#define BIT_SHIFT_UD_SUB_TYPE 18
+#define BIT_MASK_UD_SUB_TYPE 0xf
+#define BIT_UD_SUB_TYPE(x) \
+ (((x) & BIT_MASK_UD_SUB_TYPE) << BIT_SHIFT_UD_SUB_TYPE)
+#define BITS_UD_SUB_TYPE (BIT_MASK_UD_SUB_TYPE << BIT_SHIFT_UD_SUB_TYPE)
+#define BIT_CLEAR_UD_SUB_TYPE(x) ((x) & (~BITS_UD_SUB_TYPE))
+#define BIT_GET_UD_SUB_TYPE(x) \
+ (((x) >> BIT_SHIFT_UD_SUB_TYPE) & BIT_MASK_UD_SUB_TYPE)
+#define BIT_SET_UD_SUB_TYPE(x, v) \
+ (BIT_CLEAR_UD_SUB_TYPE(x) | BIT_UD_SUB_TYPE(v))
+
+#define BIT_SHIFT_UD_TYPE 16
+#define BIT_MASK_UD_TYPE 0x3
+#define BIT_UD_TYPE(x) (((x) & BIT_MASK_UD_TYPE) << BIT_SHIFT_UD_TYPE)
+#define BITS_UD_TYPE (BIT_MASK_UD_TYPE << BIT_SHIFT_UD_TYPE)
+#define BIT_CLEAR_UD_TYPE(x) ((x) & (~BITS_UD_TYPE))
+#define BIT_GET_UD_TYPE(x) (((x) >> BIT_SHIFT_UD_TYPE) & BIT_MASK_UD_TYPE)
+#define BIT_SET_UD_TYPE(x, v) (BIT_CLEAR_UD_TYPE(x) | BIT_UD_TYPE(v))
+
+#define BIT_SHIFT_RPT_COUNTER 0
+#define BIT_MASK_RPT_COUNTER 0xffff
+#define BIT_RPT_COUNTER(x) \
+ (((x) & BIT_MASK_RPT_COUNTER) << BIT_SHIFT_RPT_COUNTER)
+#define BITS_RPT_COUNTER (BIT_MASK_RPT_COUNTER << BIT_SHIFT_RPT_COUNTER)
+#define BIT_CLEAR_RPT_COUNTER(x) ((x) & (~BITS_RPT_COUNTER))
+#define BIT_GET_RPT_COUNTER(x) \
+ (((x) >> BIT_SHIFT_RPT_COUNTER) & BIT_MASK_RPT_COUNTER)
+#define BIT_SET_RPT_COUNTER(x, v) \
+ (BIT_CLEAR_RPT_COUNTER(x) | BIT_RPT_COUNTER(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */
-#define BIT_DIS_TXBA_AMPDUFCSERR BIT(39)
-#define BIT_DIS_TXBA_RXBARINFULL BIT(38)
-#define BIT_DIS_TXCFE_INFULL BIT(37)
-#define BIT_DIS_TXCTS_INFULL BIT(36)
-#define BIT_EN_TXACKBA_IN_TX_RDG BIT(35)
-#define BIT_EN_TXACKBA_IN_TXOP BIT(34)
-#define BIT_EN_TXCTS_IN_RXNAV BIT(33)
-#define BIT_EN_TXCTS_INTXOP BIT(32)
-#define BIT_BLK_EDCA_BBSLP BIT(31)
-#define BIT_BLK_EDCA_BBSBY BIT(30)
-#define BIT_ACKTO_BLOCK_SCH_EN BIT(27)
-#define BIT_EIFS_BLOCK_SCH_EN BIT(26)
-#define BIT_PLCPCHK_RST_EIFS BIT(25)
-#define BIT_CCA_RST_EIFS BIT(24)
-#define BIT_DIS_UPD_MYRXPKTNAV BIT(23)
-#define BIT_EARLY_TXBA BIT(22)
+#define BIT_RXBA_IGNOREA2 BIT(42)
+#define BIT_EN_SAVE_ALL_TXOPADDR BIT(41)
+#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV BIT(40)
-#define BIT_SHIFT_RESP_CHNBUSY 20
-#define BIT_MASK_RESP_CHNBUSY 0x3
-#define BIT_RESP_CHNBUSY(x) (((x) & BIT_MASK_RESP_CHNBUSY) << BIT_SHIFT_RESP_CHNBUSY)
-#define BIT_GET_RESP_CHNBUSY(x) (((x) >> BIT_SHIFT_RESP_CHNBUSY) & BIT_MASK_RESP_CHNBUSY)
+#endif
-#define BIT_RESP_DCTS_EN BIT(19)
-#define BIT_RESP_DCFE_EN BIT(18)
-#define BIT_RESP_SPLCPEN BIT(17)
-#define BIT_RESP_SGIEN BIT(16)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */
+#define BIT_DIS_TXBA_AMPDUFCSERR BIT(39)
+#define BIT_DIS_TXBA_RXBARINFULL BIT(38)
+#define BIT_DIS_TXCFE_INFULL BIT(37)
+#define BIT_DIS_TXCTS_INFULL BIT(36)
+#define BIT_EN_TXACKBA_IN_TX_RDG BIT(35)
+#define BIT_EN_TXACKBA_IN_TXOP BIT(34)
+#define BIT_EN_TXCTS_IN_RXNAV BIT(33)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */
-#define BIT_RESP_LDPC_EN BIT(15)
-#define BIT_DIS_RESP_ACKINCCA BIT(14)
-#define BIT_DIS_RESP_CTSINCCA BIT(13)
+#define BIT_EN_TXCTS_INTXOP BIT(32)
+#define BIT_BLK_EDCA_BBSLP BIT(31)
+#define BIT_BLK_EDCA_BBSBY BIT(30)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */
+#define BIT_ACKTO_BLOCK_SCH_EN BIT(27)
+#define BIT_EIFS_BLOCK_SCH_EN BIT(26)
+#define BIT_PLCPCHK_RST_EIFS BIT(25)
+#define BIT_CCA_RST_EIFS BIT(24)
+#define BIT_DIS_UPD_MYRXPKTNAV BIT(23)
+#define BIT_EARLY_TXBA BIT(22)
-#define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER 10
-#define BIT_MASK_R_WMAC_SECOND_CCA_TIMER 0x7
-#define BIT_R_WMAC_SECOND_CCA_TIMER(x) (((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER) << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER)
-#define BIT_GET_R_WMAC_SECOND_CCA_TIMER(x) (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER)
+#define BIT_SHIFT_RESP_CHNBUSY 20
+#define BIT_MASK_RESP_CHNBUSY 0x3
+#define BIT_RESP_CHNBUSY(x) \
+ (((x) & BIT_MASK_RESP_CHNBUSY) << BIT_SHIFT_RESP_CHNBUSY)
+#define BITS_RESP_CHNBUSY (BIT_MASK_RESP_CHNBUSY << BIT_SHIFT_RESP_CHNBUSY)
+#define BIT_CLEAR_RESP_CHNBUSY(x) ((x) & (~BITS_RESP_CHNBUSY))
+#define BIT_GET_RESP_CHNBUSY(x) \
+ (((x) >> BIT_SHIFT_RESP_CHNBUSY) & BIT_MASK_RESP_CHNBUSY)
+#define BIT_SET_RESP_CHNBUSY(x, v) \
+ (BIT_CLEAR_RESP_CHNBUSY(x) | BIT_RESP_CHNBUSY(v))
+#define BIT_RESP_DCTS_EN BIT(19)
+#define BIT_RESP_DCFE_EN BIT(18)
+#define BIT_RESP_SPLCPEN BIT(17)
+#define BIT_RESP_SGIEN BIT(16)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8814AMP_SUPPORT)
+/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */
+#define BIT_RESP_LDPC_EN BIT(15)
+#define BIT_DIS_RESP_ACKINCCA BIT(14)
+#define BIT_DIS_RESP_CTSINCCA BIT(13)
-/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_SECOND_CCA_CNT 10
-#define BIT_MASK_SECOND_CCA_CNT 0x7
-#define BIT_SECOND_CCA_CNT(x) (((x) & BIT_MASK_SECOND_CCA_CNT) << BIT_SHIFT_SECOND_CCA_CNT)
-#define BIT_GET_SECOND_CCA_CNT(x) (((x) >> BIT_SHIFT_SECOND_CCA_CNT) & BIT_MASK_SECOND_CCA_CNT)
+/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */
+#define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER 10
+#define BIT_MASK_R_WMAC_SECOND_CCA_TIMER 0x7
+#define BIT_R_WMAC_SECOND_CCA_TIMER(x) \
+ (((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER) \
+ << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER)
+#define BITS_R_WMAC_SECOND_CCA_TIMER \
+ (BIT_MASK_R_WMAC_SECOND_CCA_TIMER << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER)
+#define BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER(x) \
+ ((x) & (~BITS_R_WMAC_SECOND_CCA_TIMER))
+#define BIT_GET_R_WMAC_SECOND_CCA_TIMER(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER) & \
+ BIT_MASK_R_WMAC_SECOND_CCA_TIMER)
+#define BIT_SET_R_WMAC_SECOND_CCA_TIMER(x, v) \
+ (BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER(x) | BIT_R_WMAC_SECOND_CCA_TIMER(v))
#endif
+#if (HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */
+#define BIT_SHIFT_SECOND_CCA_CNT 10
+#define BIT_MASK_SECOND_CCA_CNT 0x7
+#define BIT_SECOND_CCA_CNT(x) \
+ (((x) & BIT_MASK_SECOND_CCA_CNT) << BIT_SHIFT_SECOND_CCA_CNT)
+#define BITS_SECOND_CCA_CNT \
+ (BIT_MASK_SECOND_CCA_CNT << BIT_SHIFT_SECOND_CCA_CNT)
+#define BIT_CLEAR_SECOND_CCA_CNT(x) ((x) & (~BITS_SECOND_CCA_CNT))
+#define BIT_GET_SECOND_CCA_CNT(x) \
+ (((x) >> BIT_SHIFT_SECOND_CCA_CNT) & BIT_MASK_SECOND_CCA_CNT)
+#define BIT_SET_SECOND_CCA_CNT(x, v) \
+ (BIT_CLEAR_SECOND_CCA_CNT(x) | BIT_SECOND_CCA_CNT(v))
-/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_RFMOD 7
-#define BIT_MASK_RFMOD 0x3
-#define BIT_RFMOD(x) (((x) & BIT_MASK_RFMOD) << BIT_SHIFT_RFMOD)
-#define BIT_GET_RFMOD(x) (((x) >> BIT_SHIFT_RFMOD) & BIT_MASK_RFMOD)
+/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */
+#define BIT_SHIFT_RFMOD 7
+#define BIT_MASK_RFMOD 0x3
+#define BIT_RFMOD(x) (((x) & BIT_MASK_RFMOD) << BIT_SHIFT_RFMOD)
+#define BITS_RFMOD (BIT_MASK_RFMOD << BIT_SHIFT_RFMOD)
+#define BIT_CLEAR_RFMOD(x) ((x) & (~BITS_RFMOD))
+#define BIT_GET_RFMOD(x) (((x) >> BIT_SHIFT_RFMOD) & BIT_MASK_RFMOD)
+#define BIT_SET_RFMOD(x, v) (BIT_CLEAR_RFMOD(x) | BIT_RFMOD(v))
#endif
-
#if (HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */
-
-#define BIT_SHIFT_RF_MOD 7
-#define BIT_MASK_RF_MOD 0x3
-#define BIT_RF_MOD(x) (((x) & BIT_MASK_RF_MOD) << BIT_SHIFT_RF_MOD)
-#define BIT_GET_RF_MOD(x) (((x) >> BIT_SHIFT_RF_MOD) & BIT_MASK_RF_MOD)
-
+#define BIT_SHIFT_RF_MOD 7
+#define BIT_MASK_RF_MOD 0x3
+#define BIT_RF_MOD(x) (((x) & BIT_MASK_RF_MOD) << BIT_SHIFT_RF_MOD)
+#define BITS_RF_MOD (BIT_MASK_RF_MOD << BIT_SHIFT_RF_MOD)
+#define BIT_CLEAR_RF_MOD(x) ((x) & (~BITS_RF_MOD))
+#define BIT_GET_RF_MOD(x) (((x) >> BIT_SHIFT_RF_MOD) & BIT_MASK_RF_MOD)
+#define BIT_SET_RF_MOD(x, v) (BIT_CLEAR_RF_MOD(x) | BIT_RF_MOD(v))
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */
-
-#define BIT_SHIFT_RESP_CTS_DYNBW_SEL 5
-#define BIT_MASK_RESP_CTS_DYNBW_SEL 0x3
-#define BIT_RESP_CTS_DYNBW_SEL(x) (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL) << BIT_SHIFT_RESP_CTS_DYNBW_SEL)
-#define BIT_GET_RESP_CTS_DYNBW_SEL(x) (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL) & BIT_MASK_RESP_CTS_DYNBW_SEL)
-
+#define BIT_SHIFT_RESP_CTS_DYNBW_SEL 5
+#define BIT_MASK_RESP_CTS_DYNBW_SEL 0x3
+#define BIT_RESP_CTS_DYNBW_SEL(x) \
+ (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL) << BIT_SHIFT_RESP_CTS_DYNBW_SEL)
+#define BITS_RESP_CTS_DYNBW_SEL \
+ (BIT_MASK_RESP_CTS_DYNBW_SEL << BIT_SHIFT_RESP_CTS_DYNBW_SEL)
+#define BIT_CLEAR_RESP_CTS_DYNBW_SEL(x) ((x) & (~BITS_RESP_CTS_DYNBW_SEL))
+#define BIT_GET_RESP_CTS_DYNBW_SEL(x) \
+ (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL) & BIT_MASK_RESP_CTS_DYNBW_SEL)
+#define BIT_SET_RESP_CTS_DYNBW_SEL(x, v) \
+ (BIT_CLEAR_RESP_CTS_DYNBW_SEL(x) | BIT_RESP_CTS_DYNBW_SEL(v))
#endif
-
#if (HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */
-
-#define BIT_SHIFT_RESP_CTS_BW_DYNBW_SEL 5
-#define BIT_MASK_RESP_CTS_BW_DYNBW_SEL 0x3
-#define BIT_RESP_CTS_BW_DYNBW_SEL(x) (((x) & BIT_MASK_RESP_CTS_BW_DYNBW_SEL) << BIT_SHIFT_RESP_CTS_BW_DYNBW_SEL)
-#define BIT_GET_RESP_CTS_BW_DYNBW_SEL(x) (((x) >> BIT_SHIFT_RESP_CTS_BW_DYNBW_SEL) & BIT_MASK_RESP_CTS_BW_DYNBW_SEL)
-
+#define BIT_SHIFT_RESP_CTS_BW_DYNBW_SEL 5
+#define BIT_MASK_RESP_CTS_BW_DYNBW_SEL 0x3
+#define BIT_RESP_CTS_BW_DYNBW_SEL(x) \
+ (((x) & BIT_MASK_RESP_CTS_BW_DYNBW_SEL) \
+ << BIT_SHIFT_RESP_CTS_BW_DYNBW_SEL)
+#define BITS_RESP_CTS_BW_DYNBW_SEL \
+ (BIT_MASK_RESP_CTS_BW_DYNBW_SEL << BIT_SHIFT_RESP_CTS_BW_DYNBW_SEL)
+#define BIT_CLEAR_RESP_CTS_BW_DYNBW_SEL(x) ((x) & (~BITS_RESP_CTS_BW_DYNBW_SEL))
+#define BIT_GET_RESP_CTS_BW_DYNBW_SEL(x) \
+ (((x) >> BIT_SHIFT_RESP_CTS_BW_DYNBW_SEL) & \
+ BIT_MASK_RESP_CTS_BW_DYNBW_SEL)
+#define BIT_SET_RESP_CTS_BW_DYNBW_SEL(x, v) \
+ (BIT_CLEAR_RESP_CTS_BW_DYNBW_SEL(x) | BIT_RESP_CTS_BW_DYNBW_SEL(v))
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */
-#define BIT_DLY_TX_WAIT_RXANTSEL BIT(4)
+#define BIT_DLY_TX_WAIT_RXANTSEL BIT(4)
#endif
-
#if (HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */
-#define BIT_DELAY_TX_USE_RX_ANTSEL BIT(4)
+#define BIT_DELAY_TX_USE_RX_ANTSEL BIT(4)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */
-#define BIT_TXRESP_BY_RXANTSEL BIT(3)
+#define BIT_TXRESP_BY_RXANTSEL BIT(3)
#endif
-
#if (HALMAC_8814AMP_SUPPORT)
-
/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */
-#define BIT_TX_USE_RX_ANTSEL BIT(3)
+#define BIT_TX_USE_RX_ANTSEL BIT(3)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */
-#define BIT_RESP_EARLY_TXACK_RWEPTKIP BIT(2)
+#define BIT_RESP_EARLY_TXACK_RWEPTKIP BIT(2)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */
+#define BIT_SHIFT_ORIG_DCTS_CHK 0
+#define BIT_MASK_ORIG_DCTS_CHK 0x3
+#define BIT_ORIG_DCTS_CHK(x) \
+ (((x) & BIT_MASK_ORIG_DCTS_CHK) << BIT_SHIFT_ORIG_DCTS_CHK)
+#define BITS_ORIG_DCTS_CHK (BIT_MASK_ORIG_DCTS_CHK << BIT_SHIFT_ORIG_DCTS_CHK)
+#define BIT_CLEAR_ORIG_DCTS_CHK(x) ((x) & (~BITS_ORIG_DCTS_CHK))
+#define BIT_GET_ORIG_DCTS_CHK(x) \
+ (((x) >> BIT_SHIFT_ORIG_DCTS_CHK) & BIT_MASK_ORIG_DCTS_CHK)
+#define BIT_SET_ORIG_DCTS_CHK(x, v) \
+ (BIT_CLEAR_ORIG_DCTS_CHK(x) | BIT_ORIG_DCTS_CHK(v))
-#define BIT_SHIFT_ORIG_DCTS_CHK 0
-#define BIT_MASK_ORIG_DCTS_CHK 0x3
-#define BIT_ORIG_DCTS_CHK(x) (((x) & BIT_MASK_ORIG_DCTS_CHK) << BIT_SHIFT_ORIG_DCTS_CHK)
-#define BIT_GET_ORIG_DCTS_CHK(x) (((x) >> BIT_SHIFT_ORIG_DCTS_CHK) & BIT_MASK_ORIG_DCTS_CHK)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_WMAC_TRXPTCL_CTL_H (Offset 0x066C) */
+#define BIT_RPT_VALID BIT(13)
+#define BIT_RXBA_IGNOREA2_V1 BIT(10)
+#define BIT_EN_SAVE_ALL_TXOPADDR_V1 BIT(9)
+#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV_V1 BIT(8)
+#define BIT_DIS_TXBA_AMPDUFCSERR_V1 BIT(7)
+#define BIT_DIS_TXBA_RXBARINFULL_V1 BIT(6)
+#define BIT_DIS_TXCFE_INFULL_V1 BIT(5)
+#define BIT_DIS_TXCTS_INFULL_V1 BIT(4)
+#define BIT_EN_TXACKBA_IN_TX_RDG_V1 BIT(3)
+#define BIT_EN_TXACKBA_IN_TXOP_V1 BIT(2)
+#define BIT_EN_TXCTS_IN_RXNAV_V1 BIT(1)
+#define BIT_EN_TXCTS_INTXOP_V1 BIT(0)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_CAMCMD (Offset 0x0670) */
-#define BIT_SECCAM_POLLING BIT(31)
-#define BIT_SECCAM_CLR BIT(30)
-#define BIT_MFBCAM_CLR BIT(29)
+#define BIT_SECCAM_POLLING BIT(31)
+#define BIT_SECCAM_CLR BIT(30)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_CAMCMD (Offset 0x0670) */
-#define BIT_SECCAM_WE BIT(16)
+#define BIT_MFBCAM_CLR BIT(29)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_CAMCMD (Offset 0x0670) */
+#define BIT_SECCAM_WE BIT(16)
+
+#endif
-#define BIT_SHIFT_SECCAM_ADDR_V1 0
-#define BIT_MASK_SECCAM_ADDR_V1 0xff
-#define BIT_SECCAM_ADDR_V1(x) (((x) & BIT_MASK_SECCAM_ADDR_V1) << BIT_SHIFT_SECCAM_ADDR_V1)
-#define BIT_GET_SECCAM_ADDR_V1(x) (((x) >> BIT_SHIFT_SECCAM_ADDR_V1) & BIT_MASK_SECCAM_ADDR_V1)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_CAMCMD (Offset 0x0670) */
-#define BIT_SHIFT_WKFCAM_NUM 0
-#define BIT_MASK_WKFCAM_NUM 0x7f
-#define BIT_WKFCAM_NUM(x) (((x) & BIT_MASK_WKFCAM_NUM) << BIT_SHIFT_WKFCAM_NUM)
-#define BIT_GET_WKFCAM_NUM(x) (((x) >> BIT_SHIFT_WKFCAM_NUM) & BIT_MASK_WKFCAM_NUM)
+#define BIT_SHIFT_SECCAM_ADDR_V1 0
+#define BIT_MASK_SECCAM_ADDR_V1 0xff
+#define BIT_SECCAM_ADDR_V1(x) \
+ (((x) & BIT_MASK_SECCAM_ADDR_V1) << BIT_SHIFT_SECCAM_ADDR_V1)
+#define BITS_SECCAM_ADDR_V1 \
+ (BIT_MASK_SECCAM_ADDR_V1 << BIT_SHIFT_SECCAM_ADDR_V1)
+#define BIT_CLEAR_SECCAM_ADDR_V1(x) ((x) & (~BITS_SECCAM_ADDR_V1))
+#define BIT_GET_SECCAM_ADDR_V1(x) \
+ (((x) >> BIT_SHIFT_SECCAM_ADDR_V1) & BIT_MASK_SECCAM_ADDR_V1)
+#define BIT_SET_SECCAM_ADDR_V1(x, v) \
+ (BIT_CLEAR_SECCAM_ADDR_V1(x) | BIT_SECCAM_ADDR_V1(v))
+#define BIT_SHIFT_WKFCAM_NUM 0
+#define BIT_MASK_WKFCAM_NUM 0x7f
+#define BIT_WKFCAM_NUM(x) (((x) & BIT_MASK_WKFCAM_NUM) << BIT_SHIFT_WKFCAM_NUM)
+#define BITS_WKFCAM_NUM (BIT_MASK_WKFCAM_NUM << BIT_SHIFT_WKFCAM_NUM)
+#define BIT_CLEAR_WKFCAM_NUM(x) ((x) & (~BITS_WKFCAM_NUM))
+#define BIT_GET_WKFCAM_NUM(x) \
+ (((x) >> BIT_SHIFT_WKFCAM_NUM) & BIT_MASK_WKFCAM_NUM)
+#define BIT_SET_WKFCAM_NUM(x, v) (BIT_CLEAR_WKFCAM_NUM(x) | BIT_WKFCAM_NUM(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_CAMCMD (Offset 0x0670) */
+#define BIT_SHIFT_SECCAM_ADDR_V2 0
+#define BIT_MASK_SECCAM_ADDR_V2 0x3ff
+#define BIT_SECCAM_ADDR_V2(x) \
+ (((x) & BIT_MASK_SECCAM_ADDR_V2) << BIT_SHIFT_SECCAM_ADDR_V2)
+#define BITS_SECCAM_ADDR_V2 \
+ (BIT_MASK_SECCAM_ADDR_V2 << BIT_SHIFT_SECCAM_ADDR_V2)
+#define BIT_CLEAR_SECCAM_ADDR_V2(x) ((x) & (~BITS_SECCAM_ADDR_V2))
+#define BIT_GET_SECCAM_ADDR_V2(x) \
+ (((x) >> BIT_SHIFT_SECCAM_ADDR_V2) & BIT_MASK_SECCAM_ADDR_V2)
+#define BIT_SET_SECCAM_ADDR_V2(x, v) \
+ (BIT_CLEAR_SECCAM_ADDR_V2(x) | BIT_SECCAM_ADDR_V2(v))
-/* 2 REG_CAMCMD (Offset 0x0670) */
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define BIT_SHIFT_SECCAM_ADDR_V2 0
-#define BIT_MASK_SECCAM_ADDR_V2 0x3ff
-#define BIT_SECCAM_ADDR_V2(x) (((x) & BIT_MASK_SECCAM_ADDR_V2) << BIT_SHIFT_SECCAM_ADDR_V2)
-#define BIT_GET_SECCAM_ADDR_V2(x) (((x) >> BIT_SHIFT_SECCAM_ADDR_V2) & BIT_MASK_SECCAM_ADDR_V2)
+/* 2 REG_CAMCMD (Offset 0x0670) */
+#define BIT_SHIFT_SECCAM_ADDR 0
+#define BIT_MASK_SECCAM_ADDR 0xff
+#define BIT_SECCAM_ADDR(x) \
+ (((x) & BIT_MASK_SECCAM_ADDR) << BIT_SHIFT_SECCAM_ADDR)
+#define BITS_SECCAM_ADDR (BIT_MASK_SECCAM_ADDR << BIT_SHIFT_SECCAM_ADDR)
+#define BIT_CLEAR_SECCAM_ADDR(x) ((x) & (~BITS_SECCAM_ADDR))
+#define BIT_GET_SECCAM_ADDR(x) \
+ (((x) >> BIT_SHIFT_SECCAM_ADDR) & BIT_MASK_SECCAM_ADDR)
+#define BIT_SET_SECCAM_ADDR(x, v) \
+ (BIT_CLEAR_SECCAM_ADDR(x) | BIT_SECCAM_ADDR(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_CAMWRITE (Offset 0x0674) */
+#define BIT_SHIFT_CAMW_DATA 0
+#define BIT_MASK_CAMW_DATA 0xffffffffL
+#define BIT_CAMW_DATA(x) (((x) & BIT_MASK_CAMW_DATA) << BIT_SHIFT_CAMW_DATA)
+#define BITS_CAMW_DATA (BIT_MASK_CAMW_DATA << BIT_SHIFT_CAMW_DATA)
+#define BIT_CLEAR_CAMW_DATA(x) ((x) & (~BITS_CAMW_DATA))
+#define BIT_GET_CAMW_DATA(x) (((x) >> BIT_SHIFT_CAMW_DATA) & BIT_MASK_CAMW_DATA)
+#define BIT_SET_CAMW_DATA(x, v) (BIT_CLEAR_CAMW_DATA(x) | BIT_CAMW_DATA(v))
-/* 2 REG_CAMCMD (Offset 0x0670) */
+/* 2 REG_CAMREAD (Offset 0x0678) */
+#define BIT_SHIFT_CAMR_DATA 0
+#define BIT_MASK_CAMR_DATA 0xffffffffL
+#define BIT_CAMR_DATA(x) (((x) & BIT_MASK_CAMR_DATA) << BIT_SHIFT_CAMR_DATA)
+#define BITS_CAMR_DATA (BIT_MASK_CAMR_DATA << BIT_SHIFT_CAMR_DATA)
+#define BIT_CLEAR_CAMR_DATA(x) ((x) & (~BITS_CAMR_DATA))
+#define BIT_GET_CAMR_DATA(x) (((x) >> BIT_SHIFT_CAMR_DATA) & BIT_MASK_CAMR_DATA)
+#define BIT_SET_CAMR_DATA(x, v) (BIT_CLEAR_CAMR_DATA(x) | BIT_CAMR_DATA(v))
-#define BIT_SHIFT_SECCAM_ADDR 0
-#define BIT_MASK_SECCAM_ADDR 0xff
-#define BIT_SECCAM_ADDR(x) (((x) & BIT_MASK_SECCAM_ADDR) << BIT_SHIFT_SECCAM_ADDR)
-#define BIT_GET_SECCAM_ADDR(x) (((x) >> BIT_SHIFT_SECCAM_ADDR) & BIT_MASK_SECCAM_ADDR)
+/* 2 REG_CAMDBG (Offset 0x067C) */
+#define BIT_SECCAM_INFO BIT(31)
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+/* 2 REG_CAMDBG (Offset 0x067C) */
-/* 2 REG_CAMWRITE (Offset 0x0674) */
+#define BIT_SEC_KEYFOUND_V1 BIT(19)
+#define BIT_SHIFT_CAMDBG_SEC_TYPE_V1 16
+#define BIT_MASK_CAMDBG_SEC_TYPE_V1 0x7
+#define BIT_CAMDBG_SEC_TYPE_V1(x) \
+ (((x) & BIT_MASK_CAMDBG_SEC_TYPE_V1) << BIT_SHIFT_CAMDBG_SEC_TYPE_V1)
+#define BITS_CAMDBG_SEC_TYPE_V1 \
+ (BIT_MASK_CAMDBG_SEC_TYPE_V1 << BIT_SHIFT_CAMDBG_SEC_TYPE_V1)
+#define BIT_CLEAR_CAMDBG_SEC_TYPE_V1(x) ((x) & (~BITS_CAMDBG_SEC_TYPE_V1))
+#define BIT_GET_CAMDBG_SEC_TYPE_V1(x) \
+ (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_V1) & BIT_MASK_CAMDBG_SEC_TYPE_V1)
+#define BIT_SET_CAMDBG_SEC_TYPE_V1(x, v) \
+ (BIT_CLEAR_CAMDBG_SEC_TYPE_V1(x) | BIT_CAMDBG_SEC_TYPE_V1(v))
-#define BIT_SHIFT_CAMW_DATA 0
-#define BIT_MASK_CAMW_DATA 0xffffffffL
-#define BIT_CAMW_DATA(x) (((x) & BIT_MASK_CAMW_DATA) << BIT_SHIFT_CAMW_DATA)
-#define BIT_GET_CAMW_DATA(x) (((x) >> BIT_SHIFT_CAMW_DATA) & BIT_MASK_CAMW_DATA)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-/* 2 REG_CAMREAD (Offset 0x0678) */
+/* 2 REG_CAMDBG (Offset 0x067C) */
+#define BIT_SEC_KEYFOUND BIT(15)
-#define BIT_SHIFT_CAMR_DATA 0
-#define BIT_MASK_CAMR_DATA 0xffffffffL
-#define BIT_CAMR_DATA(x) (((x) & BIT_MASK_CAMR_DATA) << BIT_SHIFT_CAMR_DATA)
-#define BIT_GET_CAMR_DATA(x) (((x) >> BIT_SHIFT_CAMR_DATA) & BIT_MASK_CAMR_DATA)
+#endif
+#if (HALMAC_8198F_SUPPORT)
/* 2 REG_CAMDBG (Offset 0x067C) */
-#define BIT_SECCAM_INFO BIT(31)
-#define BIT_SEC_KEYFOUND BIT(15)
+#define BIT_CAMDBG_EXT_SEC_TYPE_V1 BIT(15)
-#define BIT_SHIFT_CAMDBG_SEC_TYPE 12
-#define BIT_MASK_CAMDBG_SEC_TYPE 0x7
-#define BIT_CAMDBG_SEC_TYPE(x) (((x) & BIT_MASK_CAMDBG_SEC_TYPE) << BIT_SHIFT_CAMDBG_SEC_TYPE)
-#define BIT_GET_CAMDBG_SEC_TYPE(x) (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE) & BIT_MASK_CAMDBG_SEC_TYPE)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#endif
+/* 2 REG_CAMDBG (Offset 0x067C) */
+#define BIT_SHIFT_CAMDBG_SEC_TYPE 12
+#define BIT_MASK_CAMDBG_SEC_TYPE 0x7
+#define BIT_CAMDBG_SEC_TYPE(x) \
+ (((x) & BIT_MASK_CAMDBG_SEC_TYPE) << BIT_SHIFT_CAMDBG_SEC_TYPE)
+#define BITS_CAMDBG_SEC_TYPE \
+ (BIT_MASK_CAMDBG_SEC_TYPE << BIT_SHIFT_CAMDBG_SEC_TYPE)
+#define BIT_CLEAR_CAMDBG_SEC_TYPE(x) ((x) & (~BITS_CAMDBG_SEC_TYPE))
+#define BIT_GET_CAMDBG_SEC_TYPE(x) \
+ (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE) & BIT_MASK_CAMDBG_SEC_TYPE)
+#define BIT_SET_CAMDBG_SEC_TYPE(x, v) \
+ (BIT_CLEAR_CAMDBG_SEC_TYPE(x) | BIT_CAMDBG_SEC_TYPE(v))
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT)
/* 2 REG_CAMDBG (Offset 0x067C) */
-#define BIT_CAMDBG_EXT_SEC_TYPE BIT(11)
+#define BIT_CAMDBG_EXT_SEC_TYPE BIT(11)
#endif
-
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_CAMDBG (Offset 0x067C) */
-#define BIT_CAMDBG_EXT_SECTYPE BIT(11)
+#define BIT_CAMDBG_EXT_SECTYPE BIT(11)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8198F_SUPPORT)
/* 2 REG_CAMDBG (Offset 0x067C) */
+#define BIT_SHIFT_CAMDBG_MIC_KEY_IDX_V1 7
+#define BIT_MASK_CAMDBG_MIC_KEY_IDX_V1 0x7f
+#define BIT_CAMDBG_MIC_KEY_IDX_V1(x) \
+ (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_V1) \
+ << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_V1)
+#define BITS_CAMDBG_MIC_KEY_IDX_V1 \
+ (BIT_MASK_CAMDBG_MIC_KEY_IDX_V1 << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_V1)
+#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX_V1(x) ((x) & (~BITS_CAMDBG_MIC_KEY_IDX_V1))
+#define BIT_GET_CAMDBG_MIC_KEY_IDX_V1(x) \
+ (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_V1) & \
+ BIT_MASK_CAMDBG_MIC_KEY_IDX_V1)
+#define BIT_SET_CAMDBG_MIC_KEY_IDX_V1(x, v) \
+ (BIT_CLEAR_CAMDBG_MIC_KEY_IDX_V1(x) | BIT_CAMDBG_MIC_KEY_IDX_V1(v))
-#define BIT_SHIFT_CAMDBG_MIC_KEY_IDX 5
-#define BIT_MASK_CAMDBG_MIC_KEY_IDX 0x1f
-#define BIT_CAMDBG_MIC_KEY_IDX(x) (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX) << BIT_SHIFT_CAMDBG_MIC_KEY_IDX)
-#define BIT_GET_CAMDBG_MIC_KEY_IDX(x) (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX) & BIT_MASK_CAMDBG_MIC_KEY_IDX)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_CAMDBG_SEC_KEY_IDX 0
-#define BIT_MASK_CAMDBG_SEC_KEY_IDX 0x1f
-#define BIT_CAMDBG_SEC_KEY_IDX(x) (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX) << BIT_SHIFT_CAMDBG_SEC_KEY_IDX)
-#define BIT_GET_CAMDBG_SEC_KEY_IDX(x) (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX) & BIT_MASK_CAMDBG_SEC_KEY_IDX)
+/* 2 REG_CAMDBG (Offset 0x067C) */
+#define BIT_SHIFT_CAMDBG_MIC_KEY_IDX 5
+#define BIT_MASK_CAMDBG_MIC_KEY_IDX 0x1f
+#define BIT_CAMDBG_MIC_KEY_IDX(x) \
+ (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX) << BIT_SHIFT_CAMDBG_MIC_KEY_IDX)
+#define BITS_CAMDBG_MIC_KEY_IDX \
+ (BIT_MASK_CAMDBG_MIC_KEY_IDX << BIT_SHIFT_CAMDBG_MIC_KEY_IDX)
+#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX(x) ((x) & (~BITS_CAMDBG_MIC_KEY_IDX))
+#define BIT_GET_CAMDBG_MIC_KEY_IDX(x) \
+ (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX) & BIT_MASK_CAMDBG_MIC_KEY_IDX)
+#define BIT_SET_CAMDBG_MIC_KEY_IDX(x, v) \
+ (BIT_CLEAR_CAMDBG_MIC_KEY_IDX(x) | BIT_CAMDBG_MIC_KEY_IDX(v))
+
+#define BIT_SHIFT_CAMDBG_SEC_KEY_IDX 0
+#define BIT_MASK_CAMDBG_SEC_KEY_IDX 0x1f
+#define BIT_CAMDBG_SEC_KEY_IDX(x) \
+ (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX) << BIT_SHIFT_CAMDBG_SEC_KEY_IDX)
+#define BITS_CAMDBG_SEC_KEY_IDX \
+ (BIT_MASK_CAMDBG_SEC_KEY_IDX << BIT_SHIFT_CAMDBG_SEC_KEY_IDX)
+#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX(x) ((x) & (~BITS_CAMDBG_SEC_KEY_IDX))
+#define BIT_GET_CAMDBG_SEC_KEY_IDX(x) \
+ (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX) & BIT_MASK_CAMDBG_SEC_KEY_IDX)
+#define BIT_SET_CAMDBG_SEC_KEY_IDX(x, v) \
+ (BIT_CLEAR_CAMDBG_SEC_KEY_IDX(x) | BIT_CAMDBG_SEC_KEY_IDX(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
-/* 2 REG_SECCFG (Offset 0x0680) */
+/* 2 REG_CAMDBG (Offset 0x067C) */
-#define BIT_DIS_GCLK_WAPI BIT(15)
-#define BIT_DIS_GCLK_AES BIT(14)
-#define BIT_DIS_GCLK_TKIP BIT(13)
+#define BIT_SHIFT_CAMDBG_SEC_KEY_IDX_V1 0
+#define BIT_MASK_CAMDBG_SEC_KEY_IDX_V1 0x7f
+#define BIT_CAMDBG_SEC_KEY_IDX_V1(x) \
+ (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_V1) \
+ << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_V1)
+#define BITS_CAMDBG_SEC_KEY_IDX_V1 \
+ (BIT_MASK_CAMDBG_SEC_KEY_IDX_V1 << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_V1)
+#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX_V1(x) ((x) & (~BITS_CAMDBG_SEC_KEY_IDX_V1))
+#define BIT_GET_CAMDBG_SEC_KEY_IDX_V1(x) \
+ (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_V1) & \
+ BIT_MASK_CAMDBG_SEC_KEY_IDX_V1)
+#define BIT_SET_CAMDBG_SEC_KEY_IDX_V1(x, v) \
+ (BIT_CLEAR_CAMDBG_SEC_KEY_IDX_V1(x) | BIT_CAMDBG_SEC_KEY_IDX_V1(v))
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_SECCFG (Offset 0x0680) */
-#define BIT_AES_SEL_QC_1 BIT(12)
-#define BIT_AES_SEL_QC_0 BIT(11)
+#define BIT_DIS_GCLK_WAPI BIT(15)
+#define BIT_DIS_GCLK_AES BIT(14)
+#define BIT_DIS_GCLK_TKIP BIT(13)
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_SECCFG (Offset 0x0680) */
-#define BIT_WMAC_CKECK_BMC BIT(9)
+#define BIT_AES_SEL_QC_1 BIT(12)
+#define BIT_AES_SEL_QC_0 BIT(11)
#endif
-
-#if (HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_SECCFG (Offset 0x0680) */
-#define BIT_CHK_BMC BIT(9)
+#define BIT_WMAC_CKECK_BMC BIT(9)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_SECCFG (Offset 0x0680) */
-#define BIT_CHK_KEYID BIT(8)
-#define BIT_RXBCUSEDK BIT(7)
-#define BIT_TXBCUSEDK BIT(6)
-#define BIT_NOSKMC BIT(5)
-#define BIT_SKBYA2 BIT(4)
-#define BIT_RXDEC BIT(3)
-#define BIT_TXENC BIT(2)
-#define BIT_RXUHUSEDK BIT(1)
-#define BIT_TXUHUSEDK BIT(0)
+#define BIT_CHK_BMC BIT(9)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_SECCFG (Offset 0x0680) */
+#define BIT_CHK_KEYID BIT(8)
+#define BIT_RXBCUSEDK BIT(7)
+#define BIT_TXBCUSEDK BIT(6)
+#define BIT_NOSKMC BIT(5)
+#define BIT_SKBYA2 BIT(4)
+#define BIT_RXDEC BIT(3)
+#define BIT_TXENC BIT(2)
+#define BIT_RXUHUSEDK BIT(1)
+#define BIT_TXUHUSEDK BIT(0)
-/* 2 REG_RXFILTER_CATEGORY_1 (Offset 0x0682) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_RXFILTER_CATEGORY_1 0
-#define BIT_MASK_RXFILTER_CATEGORY_1 0xff
-#define BIT_RXFILTER_CATEGORY_1(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_1) << BIT_SHIFT_RXFILTER_CATEGORY_1)
-#define BIT_GET_RXFILTER_CATEGORY_1(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1) & BIT_MASK_RXFILTER_CATEGORY_1)
+/* 2 REG_RXFILTER_CATEGORY_1 (Offset 0x0682) */
+#define BIT_SHIFT_RXFILTER_CATEGORY_1 0
+#define BIT_MASK_RXFILTER_CATEGORY_1 0xff
+#define BIT_RXFILTER_CATEGORY_1(x) \
+ (((x) & BIT_MASK_RXFILTER_CATEGORY_1) << BIT_SHIFT_RXFILTER_CATEGORY_1)
+#define BITS_RXFILTER_CATEGORY_1 \
+ (BIT_MASK_RXFILTER_CATEGORY_1 << BIT_SHIFT_RXFILTER_CATEGORY_1)
+#define BIT_CLEAR_RXFILTER_CATEGORY_1(x) ((x) & (~BITS_RXFILTER_CATEGORY_1))
+#define BIT_GET_RXFILTER_CATEGORY_1(x) \
+ (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1) & BIT_MASK_RXFILTER_CATEGORY_1)
+#define BIT_SET_RXFILTER_CATEGORY_1(x, v) \
+ (BIT_CLEAR_RXFILTER_CATEGORY_1(x) | BIT_RXFILTER_CATEGORY_1(v))
/* 2 REG_RXFILTER_ACTION_1 (Offset 0x0683) */
-
-#define BIT_SHIFT_RXFILTER_ACTION_1 0
-#define BIT_MASK_RXFILTER_ACTION_1 0xff
-#define BIT_RXFILTER_ACTION_1(x) (((x) & BIT_MASK_RXFILTER_ACTION_1) << BIT_SHIFT_RXFILTER_ACTION_1)
-#define BIT_GET_RXFILTER_ACTION_1(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_1) & BIT_MASK_RXFILTER_ACTION_1)
-
+#define BIT_SHIFT_RXFILTER_ACTION_1 0
+#define BIT_MASK_RXFILTER_ACTION_1 0xff
+#define BIT_RXFILTER_ACTION_1(x) \
+ (((x) & BIT_MASK_RXFILTER_ACTION_1) << BIT_SHIFT_RXFILTER_ACTION_1)
+#define BITS_RXFILTER_ACTION_1 \
+ (BIT_MASK_RXFILTER_ACTION_1 << BIT_SHIFT_RXFILTER_ACTION_1)
+#define BIT_CLEAR_RXFILTER_ACTION_1(x) ((x) & (~BITS_RXFILTER_ACTION_1))
+#define BIT_GET_RXFILTER_ACTION_1(x) \
+ (((x) >> BIT_SHIFT_RXFILTER_ACTION_1) & BIT_MASK_RXFILTER_ACTION_1)
+#define BIT_SET_RXFILTER_ACTION_1(x, v) \
+ (BIT_CLEAR_RXFILTER_ACTION_1(x) | BIT_RXFILTER_ACTION_1(v))
/* 2 REG_RXFILTER_CATEGORY_2 (Offset 0x0684) */
-
-#define BIT_SHIFT_RXFILTER_CATEGORY_2 0
-#define BIT_MASK_RXFILTER_CATEGORY_2 0xff
-#define BIT_RXFILTER_CATEGORY_2(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_2) << BIT_SHIFT_RXFILTER_CATEGORY_2)
-#define BIT_GET_RXFILTER_CATEGORY_2(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2) & BIT_MASK_RXFILTER_CATEGORY_2)
-
+#define BIT_SHIFT_RXFILTER_CATEGORY_2 0
+#define BIT_MASK_RXFILTER_CATEGORY_2 0xff
+#define BIT_RXFILTER_CATEGORY_2(x) \
+ (((x) & BIT_MASK_RXFILTER_CATEGORY_2) << BIT_SHIFT_RXFILTER_CATEGORY_2)
+#define BITS_RXFILTER_CATEGORY_2 \
+ (BIT_MASK_RXFILTER_CATEGORY_2 << BIT_SHIFT_RXFILTER_CATEGORY_2)
+#define BIT_CLEAR_RXFILTER_CATEGORY_2(x) ((x) & (~BITS_RXFILTER_CATEGORY_2))
+#define BIT_GET_RXFILTER_CATEGORY_2(x) \
+ (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2) & BIT_MASK_RXFILTER_CATEGORY_2)
+#define BIT_SET_RXFILTER_CATEGORY_2(x, v) \
+ (BIT_CLEAR_RXFILTER_CATEGORY_2(x) | BIT_RXFILTER_CATEGORY_2(v))
/* 2 REG_RXFILTER_ACTION_2 (Offset 0x0685) */
-
-#define BIT_SHIFT_RXFILTER_ACTION_2 0
-#define BIT_MASK_RXFILTER_ACTION_2 0xff
-#define BIT_RXFILTER_ACTION_2(x) (((x) & BIT_MASK_RXFILTER_ACTION_2) << BIT_SHIFT_RXFILTER_ACTION_2)
-#define BIT_GET_RXFILTER_ACTION_2(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_2) & BIT_MASK_RXFILTER_ACTION_2)
-
+#define BIT_SHIFT_RXFILTER_ACTION_2 0
+#define BIT_MASK_RXFILTER_ACTION_2 0xff
+#define BIT_RXFILTER_ACTION_2(x) \
+ (((x) & BIT_MASK_RXFILTER_ACTION_2) << BIT_SHIFT_RXFILTER_ACTION_2)
+#define BITS_RXFILTER_ACTION_2 \
+ (BIT_MASK_RXFILTER_ACTION_2 << BIT_SHIFT_RXFILTER_ACTION_2)
+#define BIT_CLEAR_RXFILTER_ACTION_2(x) ((x) & (~BITS_RXFILTER_ACTION_2))
+#define BIT_GET_RXFILTER_ACTION_2(x) \
+ (((x) >> BIT_SHIFT_RXFILTER_ACTION_2) & BIT_MASK_RXFILTER_ACTION_2)
+#define BIT_SET_RXFILTER_ACTION_2(x, v) \
+ (BIT_CLEAR_RXFILTER_ACTION_2(x) | BIT_RXFILTER_ACTION_2(v))
/* 2 REG_RXFILTER_CATEGORY_3 (Offset 0x0686) */
-
-#define BIT_SHIFT_RXFILTER_CATEGORY_3 0
-#define BIT_MASK_RXFILTER_CATEGORY_3 0xff
-#define BIT_RXFILTER_CATEGORY_3(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_3) << BIT_SHIFT_RXFILTER_CATEGORY_3)
-#define BIT_GET_RXFILTER_CATEGORY_3(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3) & BIT_MASK_RXFILTER_CATEGORY_3)
-
+#define BIT_SHIFT_RXFILTER_CATEGORY_3 0
+#define BIT_MASK_RXFILTER_CATEGORY_3 0xff
+#define BIT_RXFILTER_CATEGORY_3(x) \
+ (((x) & BIT_MASK_RXFILTER_CATEGORY_3) << BIT_SHIFT_RXFILTER_CATEGORY_3)
+#define BITS_RXFILTER_CATEGORY_3 \
+ (BIT_MASK_RXFILTER_CATEGORY_3 << BIT_SHIFT_RXFILTER_CATEGORY_3)
+#define BIT_CLEAR_RXFILTER_CATEGORY_3(x) ((x) & (~BITS_RXFILTER_CATEGORY_3))
+#define BIT_GET_RXFILTER_CATEGORY_3(x) \
+ (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3) & BIT_MASK_RXFILTER_CATEGORY_3)
+#define BIT_SET_RXFILTER_CATEGORY_3(x, v) \
+ (BIT_CLEAR_RXFILTER_CATEGORY_3(x) | BIT_RXFILTER_CATEGORY_3(v))
/* 2 REG_RXFILTER_ACTION_3 (Offset 0x0687) */
-
-#define BIT_SHIFT_RXFILTER_ACTION_3 0
-#define BIT_MASK_RXFILTER_ACTION_3 0xff
-#define BIT_RXFILTER_ACTION_3(x) (((x) & BIT_MASK_RXFILTER_ACTION_3) << BIT_SHIFT_RXFILTER_ACTION_3)
-#define BIT_GET_RXFILTER_ACTION_3(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_3) & BIT_MASK_RXFILTER_ACTION_3)
-
+#define BIT_SHIFT_RXFILTER_ACTION_3 0
+#define BIT_MASK_RXFILTER_ACTION_3 0xff
+#define BIT_RXFILTER_ACTION_3(x) \
+ (((x) & BIT_MASK_RXFILTER_ACTION_3) << BIT_SHIFT_RXFILTER_ACTION_3)
+#define BITS_RXFILTER_ACTION_3 \
+ (BIT_MASK_RXFILTER_ACTION_3 << BIT_SHIFT_RXFILTER_ACTION_3)
+#define BIT_CLEAR_RXFILTER_ACTION_3(x) ((x) & (~BITS_RXFILTER_ACTION_3))
+#define BIT_GET_RXFILTER_ACTION_3(x) \
+ (((x) >> BIT_SHIFT_RXFILTER_ACTION_3) & BIT_MASK_RXFILTER_ACTION_3)
+#define BIT_SET_RXFILTER_ACTION_3(x, v) \
+ (BIT_CLEAR_RXFILTER_ACTION_3(x) | BIT_RXFILTER_ACTION_3(v))
/* 2 REG_RXFLTMAP3 (Offset 0x0688) */
-#define BIT_MGTFLT15EN_FW BIT(15)
-#define BIT_MGTFLT14EN_FW BIT(14)
-#define BIT_MGTFLT13EN_FW BIT(13)
-#define BIT_MGTFLT12EN_FW BIT(12)
-#define BIT_MGTFLT11EN_FW BIT(11)
-#define BIT_MGTFLT10EN_FW BIT(10)
-#define BIT_MGTFLT9EN_FW BIT(9)
-#define BIT_MGTFLT8EN_FW BIT(8)
-#define BIT_MGTFLT7EN_FW BIT(7)
-#define BIT_MGTFLT6EN_FW BIT(6)
-#define BIT_MGTFLT5EN_FW BIT(5)
-#define BIT_MGTFLT4EN_FW BIT(4)
-#define BIT_MGTFLT3EN_FW BIT(3)
-#define BIT_MGTFLT2EN_FW BIT(2)
-#define BIT_MGTFLT1EN_FW BIT(1)
-#define BIT_MGTFLT0EN_FW BIT(0)
+#define BIT_MGTFLT15EN_FW BIT(15)
+#define BIT_MGTFLT14EN_FW BIT(14)
+#define BIT_MGTFLT13EN_FW BIT(13)
+#define BIT_MGTFLT12EN_FW BIT(12)
+#define BIT_MGTFLT11EN_FW BIT(11)
+#define BIT_MGTFLT10EN_FW BIT(10)
+#define BIT_MGTFLT9EN_FW BIT(9)
+#define BIT_MGTFLT8EN_FW BIT(8)
+#define BIT_MGTFLT7EN_FW BIT(7)
+#define BIT_MGTFLT6EN_FW BIT(6)
+#define BIT_MGTFLT5EN_FW BIT(5)
+#define BIT_MGTFLT4EN_FW BIT(4)
+#define BIT_MGTFLT3EN_FW BIT(3)
+#define BIT_MGTFLT2EN_FW BIT(2)
+#define BIT_MGTFLT1EN_FW BIT(1)
+#define BIT_MGTFLT0EN_FW BIT(0)
/* 2 REG_RXFLTMAP4 (Offset 0x068A) */
-#define BIT_CTRLFLT15EN_FW BIT(15)
-#define BIT_CTRLFLT14EN_FW BIT(14)
-#define BIT_CTRLFLT13EN_FW BIT(13)
-#define BIT_CTRLFLT12EN_FW BIT(12)
-#define BIT_CTRLFLT11EN_FW BIT(11)
-#define BIT_CTRLFLT10EN_FW BIT(10)
-#define BIT_CTRLFLT9EN_FW BIT(9)
-#define BIT_CTRLFLT8EN_FW BIT(8)
-#define BIT_CTRLFLT7EN_FW BIT(7)
-#define BIT_CTRLFLT6EN_FW BIT(6)
-#define BIT_CTRLFLT5EN_FW BIT(5)
-#define BIT_CTRLFLT4EN_FW BIT(4)
-#define BIT_CTRLFLT3EN_FW BIT(3)
-#define BIT_CTRLFLT2EN_FW BIT(2)
-#define BIT_CTRLFLT1EN_FW BIT(1)
-#define BIT_CTRLFLT0EN_FW BIT(0)
+#define BIT_CTRLFLT15EN_FW BIT(15)
+#define BIT_CTRLFLT14EN_FW BIT(14)
+#define BIT_CTRLFLT13EN_FW BIT(13)
+#define BIT_CTRLFLT12EN_FW BIT(12)
+#define BIT_CTRLFLT11EN_FW BIT(11)
+#define BIT_CTRLFLT10EN_FW BIT(10)
+#define BIT_CTRLFLT9EN_FW BIT(9)
+#define BIT_CTRLFLT8EN_FW BIT(8)
+#define BIT_CTRLFLT7EN_FW BIT(7)
+#define BIT_CTRLFLT6EN_FW BIT(6)
+#define BIT_CTRLFLT5EN_FW BIT(5)
+#define BIT_CTRLFLT4EN_FW BIT(4)
+#define BIT_CTRLFLT3EN_FW BIT(3)
+#define BIT_CTRLFLT2EN_FW BIT(2)
+#define BIT_CTRLFLT1EN_FW BIT(1)
+#define BIT_CTRLFLT0EN_FW BIT(0)
/* 2 REG_RXFLTMAP5 (Offset 0x068C) */
-#define BIT_DATAFLT15EN_FW BIT(15)
-#define BIT_DATAFLT14EN_FW BIT(14)
-#define BIT_DATAFLT13EN_FW BIT(13)
-#define BIT_DATAFLT12EN_FW BIT(12)
-#define BIT_DATAFLT11EN_FW BIT(11)
-#define BIT_DATAFLT10EN_FW BIT(10)
-#define BIT_DATAFLT9EN_FW BIT(9)
-#define BIT_DATAFLT8EN_FW BIT(8)
-#define BIT_DATAFLT7EN_FW BIT(7)
-#define BIT_DATAFLT6EN_FW BIT(6)
-#define BIT_DATAFLT5EN_FW BIT(5)
-#define BIT_DATAFLT4EN_FW BIT(4)
-#define BIT_DATAFLT3EN_FW BIT(3)
-#define BIT_DATAFLT2EN_FW BIT(2)
-#define BIT_DATAFLT1EN_FW BIT(1)
-#define BIT_DATAFLT0EN_FW BIT(0)
+#define BIT_DATAFLT15EN_FW BIT(15)
+#define BIT_DATAFLT14EN_FW BIT(14)
+#define BIT_DATAFLT13EN_FW BIT(13)
+#define BIT_DATAFLT12EN_FW BIT(12)
+#define BIT_DATAFLT11EN_FW BIT(11)
+#define BIT_DATAFLT10EN_FW BIT(10)
+#define BIT_DATAFLT9EN_FW BIT(9)
+#define BIT_DATAFLT8EN_FW BIT(8)
+#define BIT_DATAFLT7EN_FW BIT(7)
+#define BIT_DATAFLT6EN_FW BIT(6)
+#define BIT_DATAFLT5EN_FW BIT(5)
+#define BIT_DATAFLT4EN_FW BIT(4)
+#define BIT_DATAFLT3EN_FW BIT(3)
+#define BIT_DATAFLT2EN_FW BIT(2)
+#define BIT_DATAFLT1EN_FW BIT(1)
+#define BIT_DATAFLT0EN_FW BIT(0)
/* 2 REG_RXFLTMAP6 (Offset 0x068E) */
-#define BIT_ACTIONFLT15EN_FW BIT(15)
-#define BIT_ACTIONFLT14EN_FW BIT(14)
-#define BIT_ACTIONFLT13EN_FW BIT(13)
-#define BIT_ACTIONFLT12EN_FW BIT(12)
-#define BIT_ACTIONFLT11EN_FW BIT(11)
-#define BIT_ACTIONFLT10EN_FW BIT(10)
-#define BIT_ACTIONFLT9EN_FW BIT(9)
-#define BIT_ACTIONFLT8EN_FW BIT(8)
-#define BIT_ACTIONFLT7EN_FW BIT(7)
-#define BIT_ACTIONFLT6EN_FW BIT(6)
-#define BIT_ACTIONFLT5EN_FW BIT(5)
-#define BIT_ACTIONFLT4EN_FW BIT(4)
-#define BIT_ACTIONFLT3EN_FW BIT(3)
-#define BIT_ACTIONFLT2EN_FW BIT(2)
-#define BIT_ACTIONFLT1EN_FW BIT(1)
-#define BIT_ACTIONFLT0EN_FW BIT(0)
+#define BIT_ACTIONFLT15EN_FW BIT(15)
+#define BIT_ACTIONFLT14EN_FW BIT(14)
+#define BIT_ACTIONFLT13EN_FW BIT(13)
+#define BIT_ACTIONFLT12EN_FW BIT(12)
+#define BIT_ACTIONFLT11EN_FW BIT(11)
+#define BIT_ACTIONFLT10EN_FW BIT(10)
+#define BIT_ACTIONFLT9EN_FW BIT(9)
+#define BIT_ACTIONFLT8EN_FW BIT(8)
+#define BIT_ACTIONFLT7EN_FW BIT(7)
+#define BIT_ACTIONFLT6EN_FW BIT(6)
+#define BIT_ACTIONFLT5EN_FW BIT(5)
+#define BIT_ACTIONFLT4EN_FW BIT(4)
+#define BIT_ACTIONFLT3EN_FW BIT(3)
+#define BIT_ACTIONFLT2EN_FW BIT(2)
+#define BIT_ACTIONFLT1EN_FW BIT(1)
+#define BIT_ACTIONFLT0EN_FW BIT(0)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_WOW_CTRL (Offset 0x0690) */
-
-#define BIT_SHIFT_PSF_BSSIDSEL_B2B1 6
-#define BIT_MASK_PSF_BSSIDSEL_B2B1 0x3
-#define BIT_PSF_BSSIDSEL_B2B1(x) (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1) << BIT_SHIFT_PSF_BSSIDSEL_B2B1)
-#define BIT_GET_PSF_BSSIDSEL_B2B1(x) (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1) & BIT_MASK_PSF_BSSIDSEL_B2B1)
-
+#define BIT_SHIFT_PSF_BSSIDSEL_B2B1 6
+#define BIT_MASK_PSF_BSSIDSEL_B2B1 0x3
+#define BIT_PSF_BSSIDSEL_B2B1(x) \
+ (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1) << BIT_SHIFT_PSF_BSSIDSEL_B2B1)
+#define BITS_PSF_BSSIDSEL_B2B1 \
+ (BIT_MASK_PSF_BSSIDSEL_B2B1 << BIT_SHIFT_PSF_BSSIDSEL_B2B1)
+#define BIT_CLEAR_PSF_BSSIDSEL_B2B1(x) ((x) & (~BITS_PSF_BSSIDSEL_B2B1))
+#define BIT_GET_PSF_BSSIDSEL_B2B1(x) \
+ (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1) & BIT_MASK_PSF_BSSIDSEL_B2B1)
+#define BIT_SET_PSF_BSSIDSEL_B2B1(x, v) \
+ (BIT_CLEAR_PSF_BSSIDSEL_B2B1(x) | BIT_PSF_BSSIDSEL_B2B1(v))
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_WOW_CTRL (Offset 0x0690) */
-#define BIT_WOWHCI BIT(5)
+#define BIT_WOWHCI BIT(5)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_WOW_CTRL (Offset 0x0690) */
-#define BIT_PSF_BSSIDSEL BIT(4)
+#define BIT_PSF_BSSIDSEL BIT(4)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_WOW_CTRL (Offset 0x0690) */
-#define BIT_PSF_BSSIDSEL_B0 BIT(4)
+#define BIT_PSF_BSSIDSEL_B0 BIT(4)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_WOW_CTRL (Offset 0x0690) */
-#define BIT_UWF BIT(3)
-#define BIT_MAGIC BIT(2)
-#define BIT_WOWEN BIT(1)
-#define BIT_FORCE_WAKEUP BIT(0)
+#define BIT_UWF BIT(3)
+#define BIT_MAGIC BIT(2)
+#define BIT_WOWEN BIT(1)
+#define BIT_FORCE_WAKEUP BIT(0)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_NAN_RX_TSF_FILTER (Offset 0x0691) */
-#define BIT_CHK_TSF_TA BIT(2)
-#define BIT_CHK_TSF_CBSSID BIT(1)
-#define BIT_CHK_TSF_EN BIT(0)
+#define BIT_CHK_TSF_TA BIT(2)
+#define BIT_CHK_TSF_CBSSID BIT(1)
+#define BIT_CHK_TSF_EN BIT(0)
/* 2 REG_PS_RX_INFO (Offset 0x0692) */
-
-#define BIT_SHIFT_PORTSEL__PS_RX_INFO 5
-#define BIT_MASK_PORTSEL__PS_RX_INFO 0x7
-#define BIT_PORTSEL__PS_RX_INFO(x) (((x) & BIT_MASK_PORTSEL__PS_RX_INFO) << BIT_SHIFT_PORTSEL__PS_RX_INFO)
-#define BIT_GET_PORTSEL__PS_RX_INFO(x) (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO) & BIT_MASK_PORTSEL__PS_RX_INFO)
-
+#define BIT_SHIFT_PORTSEL__PS_RX_INFO 5
+#define BIT_MASK_PORTSEL__PS_RX_INFO 0x7
+#define BIT_PORTSEL__PS_RX_INFO(x) \
+ (((x) & BIT_MASK_PORTSEL__PS_RX_INFO) << BIT_SHIFT_PORTSEL__PS_RX_INFO)
+#define BITS_PORTSEL__PS_RX_INFO \
+ (BIT_MASK_PORTSEL__PS_RX_INFO << BIT_SHIFT_PORTSEL__PS_RX_INFO)
+#define BIT_CLEAR_PORTSEL__PS_RX_INFO(x) ((x) & (~BITS_PORTSEL__PS_RX_INFO))
+#define BIT_GET_PORTSEL__PS_RX_INFO(x) \
+ (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO) & BIT_MASK_PORTSEL__PS_RX_INFO)
+#define BIT_SET_PORTSEL__PS_RX_INFO(x, v) \
+ (BIT_CLEAR_PORTSEL__PS_RX_INFO(x) | BIT_PORTSEL__PS_RX_INFO(v))
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_PS_RX_INFO (Offset 0x0692) */
-#define BIT_RXCTRLIN0 BIT(4)
-#define BIT_RXMGTIN0 BIT(3)
-#define BIT_RXDATAIN2 BIT(2)
-#define BIT_RXDATAIN1 BIT(1)
-#define BIT_RXDATAIN0 BIT(0)
+#define BIT_RXCTRLIN0 BIT(4)
+#define BIT_RXMGTIN0 BIT(3)
+#define BIT_RXDATAIN2 BIT(2)
+#define BIT_RXDATAIN1 BIT(1)
+#define BIT_RXDATAIN0 BIT(0)
/* 2 REG_WMMPS_UAPSD_TID (Offset 0x0693) */
-#define BIT_WMMPS_UAPSD_TID7 BIT(7)
-#define BIT_WMMPS_UAPSD_TID6 BIT(6)
-#define BIT_WMMPS_UAPSD_TID5 BIT(5)
-#define BIT_WMMPS_UAPSD_TID4 BIT(4)
-#define BIT_WMMPS_UAPSD_TID3 BIT(3)
-#define BIT_WMMPS_UAPSD_TID2 BIT(2)
-#define BIT_WMMPS_UAPSD_TID1 BIT(1)
-#define BIT_WMMPS_UAPSD_TID0 BIT(0)
+#define BIT_WMMPS_UAPSD_TID7 BIT(7)
+#define BIT_WMMPS_UAPSD_TID6 BIT(6)
+#define BIT_WMMPS_UAPSD_TID5 BIT(5)
+#define BIT_WMMPS_UAPSD_TID4 BIT(4)
+#define BIT_WMMPS_UAPSD_TID3 BIT(3)
+#define BIT_WMMPS_UAPSD_TID2 BIT(2)
+#define BIT_WMMPS_UAPSD_TID1 BIT(1)
+#define BIT_WMMPS_UAPSD_TID0 BIT(0)
-/* 2 REG_LPNAV_CTRL (Offset 0x0694) */
+#endif
-#define BIT_LPNAV_EN BIT(31)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_LPNAV_EARLY 16
-#define BIT_MASK_LPNAV_EARLY 0x7fff
-#define BIT_LPNAV_EARLY(x) (((x) & BIT_MASK_LPNAV_EARLY) << BIT_SHIFT_LPNAV_EARLY)
-#define BIT_GET_LPNAV_EARLY(x) (((x) >> BIT_SHIFT_LPNAV_EARLY) & BIT_MASK_LPNAV_EARLY)
+/* 2 REG_LPNAV_CTRL (Offset 0x0694) */
+#define BIT_LPNAV_EN BIT(31)
-#define BIT_SHIFT_LPNAV_TH 0
-#define BIT_MASK_LPNAV_TH 0xffff
-#define BIT_LPNAV_TH(x) (((x) & BIT_MASK_LPNAV_TH) << BIT_SHIFT_LPNAV_TH)
-#define BIT_GET_LPNAV_TH(x) (((x) >> BIT_SHIFT_LPNAV_TH) & BIT_MASK_LPNAV_TH)
+#define BIT_SHIFT_LPNAV_EARLY 16
+#define BIT_MASK_LPNAV_EARLY 0x7fff
+#define BIT_LPNAV_EARLY(x) \
+ (((x) & BIT_MASK_LPNAV_EARLY) << BIT_SHIFT_LPNAV_EARLY)
+#define BITS_LPNAV_EARLY (BIT_MASK_LPNAV_EARLY << BIT_SHIFT_LPNAV_EARLY)
+#define BIT_CLEAR_LPNAV_EARLY(x) ((x) & (~BITS_LPNAV_EARLY))
+#define BIT_GET_LPNAV_EARLY(x) \
+ (((x) >> BIT_SHIFT_LPNAV_EARLY) & BIT_MASK_LPNAV_EARLY)
+#define BIT_SET_LPNAV_EARLY(x, v) \
+ (BIT_CLEAR_LPNAV_EARLY(x) | BIT_LPNAV_EARLY(v))
+#define BIT_SHIFT_LPNAV_TH 0
+#define BIT_MASK_LPNAV_TH 0xffff
+#define BIT_LPNAV_TH(x) (((x) & BIT_MASK_LPNAV_TH) << BIT_SHIFT_LPNAV_TH)
+#define BITS_LPNAV_TH (BIT_MASK_LPNAV_TH << BIT_SHIFT_LPNAV_TH)
+#define BIT_CLEAR_LPNAV_TH(x) ((x) & (~BITS_LPNAV_TH))
+#define BIT_GET_LPNAV_TH(x) (((x) >> BIT_SHIFT_LPNAV_TH) & BIT_MASK_LPNAV_TH)
+#define BIT_SET_LPNAV_TH(x, v) (BIT_CLEAR_LPNAV_TH(x) | BIT_LPNAV_TH(v))
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_WKFMCAM_CMD (Offset 0x0698) */
-#define BIT_WKFCAM_POLLING_V1 BIT(31)
-#define BIT_WKFCAM_CLR_V1 BIT(30)
+#define BIT_WKFCAM_POLLING_V1 BIT(31)
+#define BIT_WKFCAM_CLR_V1 BIT(30)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_WKFMCAM_CMD (Offset 0x0698) */
-#define BIT_WKFCAM_WE BIT(16)
+#define BIT_WKFCAM_WE BIT(16)
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_WKFMCAM_CMD (Offset 0x0698) */
-
-#define BIT_SHIFT_WKFCAM_ADDR_V2 8
-#define BIT_MASK_WKFCAM_ADDR_V2 0xff
-#define BIT_WKFCAM_ADDR_V2(x) (((x) & BIT_MASK_WKFCAM_ADDR_V2) << BIT_SHIFT_WKFCAM_ADDR_V2)
-#define BIT_GET_WKFCAM_ADDR_V2(x) (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2) & BIT_MASK_WKFCAM_ADDR_V2)
-
+#define BIT_SHIFT_WKFCAM_ADDR_V2 8
+#define BIT_MASK_WKFCAM_ADDR_V2 0xff
+#define BIT_WKFCAM_ADDR_V2(x) \
+ (((x) & BIT_MASK_WKFCAM_ADDR_V2) << BIT_SHIFT_WKFCAM_ADDR_V2)
+#define BITS_WKFCAM_ADDR_V2 \
+ (BIT_MASK_WKFCAM_ADDR_V2 << BIT_SHIFT_WKFCAM_ADDR_V2)
+#define BIT_CLEAR_WKFCAM_ADDR_V2(x) ((x) & (~BITS_WKFCAM_ADDR_V2))
+#define BIT_GET_WKFCAM_ADDR_V2(x) \
+ (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2) & BIT_MASK_WKFCAM_ADDR_V2)
+#define BIT_SET_WKFCAM_ADDR_V2(x, v) \
+ (BIT_CLEAR_WKFCAM_ADDR_V2(x) | BIT_WKFCAM_ADDR_V2(v))
+
+#define BIT_WMAC_RESP_NONSTA1_DIS BIT(7)
+
+#define BIT_SHIFT_WMAC_TXMU_ACKPOLICY 4
+#define BIT_MASK_WMAC_TXMU_ACKPOLICY 0x3
+#define BIT_WMAC_TXMU_ACKPOLICY(x) \
+ (((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY) << BIT_SHIFT_WMAC_TXMU_ACKPOLICY)
+#define BITS_WMAC_TXMU_ACKPOLICY \
+ (BIT_MASK_WMAC_TXMU_ACKPOLICY << BIT_SHIFT_WMAC_TXMU_ACKPOLICY)
+#define BIT_CLEAR_WMAC_TXMU_ACKPOLICY(x) ((x) & (~BITS_WMAC_TXMU_ACKPOLICY))
+#define BIT_GET_WMAC_TXMU_ACKPOLICY(x) \
+ (((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY) & BIT_MASK_WMAC_TXMU_ACKPOLICY)
+#define BIT_SET_WMAC_TXMU_ACKPOLICY(x, v) \
+ (BIT_CLEAR_WMAC_TXMU_ACKPOLICY(x) | BIT_WMAC_TXMU_ACKPOLICY(v))
+
+#define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL 1
+#define BIT_MASK_WMAC_MU_BFEE_PORT_SEL 0x7
+#define BIT_WMAC_MU_BFEE_PORT_SEL(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL) \
+ << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL)
+#define BITS_WMAC_MU_BFEE_PORT_SEL \
+ (BIT_MASK_WMAC_MU_BFEE_PORT_SEL << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL)
+#define BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL(x) ((x) & (~BITS_WMAC_MU_BFEE_PORT_SEL))
+#define BIT_GET_WMAC_MU_BFEE_PORT_SEL(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL) & \
+ BIT_MASK_WMAC_MU_BFEE_PORT_SEL)
+#define BIT_SET_WMAC_MU_BFEE_PORT_SEL(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL(x) | BIT_WMAC_MU_BFEE_PORT_SEL(v))
+
+#define BIT_SHIFT_WKFCAM_CAM_NUM_V1 0
+#define BIT_MASK_WKFCAM_CAM_NUM_V1 0xff
+#define BIT_WKFCAM_CAM_NUM_V1(x) \
+ (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1) << BIT_SHIFT_WKFCAM_CAM_NUM_V1)
+#define BITS_WKFCAM_CAM_NUM_V1 \
+ (BIT_MASK_WKFCAM_CAM_NUM_V1 << BIT_SHIFT_WKFCAM_CAM_NUM_V1)
+#define BIT_CLEAR_WKFCAM_CAM_NUM_V1(x) ((x) & (~BITS_WKFCAM_CAM_NUM_V1))
+#define BIT_GET_WKFCAM_CAM_NUM_V1(x) \
+ (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1) & BIT_MASK_WKFCAM_CAM_NUM_V1)
+#define BIT_SET_WKFCAM_CAM_NUM_V1(x, v) \
+ (BIT_CLEAR_WKFCAM_CAM_NUM_V1(x) | BIT_WKFCAM_CAM_NUM_V1(v))
+
+#define BIT_WMAC_MU_BFEE_DIS BIT(0)
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_WKFMCAM_CMD (Offset 0x0698) */
+#define BIT_SHIFT_WKFCAM_ADDR 0
+#define BIT_MASK_WKFCAM_ADDR 0x7f
+#define BIT_WKFCAM_ADDR(x) \
+ (((x) & BIT_MASK_WKFCAM_ADDR) << BIT_SHIFT_WKFCAM_ADDR)
+#define BITS_WKFCAM_ADDR (BIT_MASK_WKFCAM_ADDR << BIT_SHIFT_WKFCAM_ADDR)
+#define BIT_CLEAR_WKFCAM_ADDR(x) ((x) & (~BITS_WKFCAM_ADDR))
+#define BIT_GET_WKFCAM_ADDR(x) \
+ (((x) >> BIT_SHIFT_WKFCAM_ADDR) & BIT_MASK_WKFCAM_ADDR)
+#define BIT_SET_WKFCAM_ADDR(x, v) \
+ (BIT_CLEAR_WKFCAM_ADDR(x) | BIT_WKFCAM_ADDR(v))
-/* 2 REG_WKFMCAM_CMD (Offset 0x0698) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_WKFCAM_ADDR_V1 7
-#define BIT_MASK_WKFCAM_ADDR_V1 0x1ff
-#define BIT_WKFCAM_ADDR_V1(x) (((x) & BIT_MASK_WKFCAM_ADDR_V1) << BIT_SHIFT_WKFCAM_ADDR_V1)
-#define BIT_GET_WKFCAM_ADDR_V1(x) (((x) >> BIT_SHIFT_WKFCAM_ADDR_V1) & BIT_MASK_WKFCAM_ADDR_V1)
+/* 2 REG_WKFMCAM_RWD (Offset 0x069C) */
+#define BIT_SHIFT_WKFMCAM_RWD 0
+#define BIT_MASK_WKFMCAM_RWD 0xffffffffL
+#define BIT_WKFMCAM_RWD(x) \
+ (((x) & BIT_MASK_WKFMCAM_RWD) << BIT_SHIFT_WKFMCAM_RWD)
+#define BITS_WKFMCAM_RWD (BIT_MASK_WKFMCAM_RWD << BIT_SHIFT_WKFMCAM_RWD)
+#define BIT_CLEAR_WKFMCAM_RWD(x) ((x) & (~BITS_WKFMCAM_RWD))
+#define BIT_GET_WKFMCAM_RWD(x) \
+ (((x) >> BIT_SHIFT_WKFMCAM_RWD) & BIT_MASK_WKFMCAM_RWD)
+#define BIT_SET_WKFMCAM_RWD(x, v) \
+ (BIT_CLEAR_WKFMCAM_RWD(x) | BIT_WKFMCAM_RWD(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_RXFLTMAP0 (Offset 0x06A0) */
+#define BIT_DATAFLT15EN BIT(15)
-/* 2 REG_WKFMCAM_CMD (Offset 0x0698) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_WKFCAM_CAM_NUM_V1 0
-#define BIT_MASK_WKFCAM_CAM_NUM_V1 0xff
-#define BIT_WKFCAM_CAM_NUM_V1(x) (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1) << BIT_SHIFT_WKFCAM_CAM_NUM_V1)
-#define BIT_GET_WKFCAM_CAM_NUM_V1(x) (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1) & BIT_MASK_WKFCAM_CAM_NUM_V1)
+/* 2 REG_RXFLTMAP0 (Offset 0x06A0) */
+#define BIT_MGTFLT15EN BIT(15)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_RXFLTMAP0 (Offset 0x06A0) */
+#define BIT_DATAFLT14EN BIT(14)
-/* 2 REG_WKFMCAM_CMD (Offset 0x0698) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_WKFCAM_ADDR 0
-#define BIT_MASK_WKFCAM_ADDR 0x7f
-#define BIT_WKFCAM_ADDR(x) (((x) & BIT_MASK_WKFCAM_ADDR) << BIT_SHIFT_WKFCAM_ADDR)
-#define BIT_GET_WKFCAM_ADDR(x) (((x) >> BIT_SHIFT_WKFCAM_ADDR) & BIT_MASK_WKFCAM_ADDR)
+/* 2 REG_RXFLTMAP0 (Offset 0x06A0) */
+#define BIT_MGTFLT14EN BIT(14)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_WKFMCAM_RWD (Offset 0x069C) */
+/* 2 REG_RXFLTMAP0 (Offset 0x06A0) */
+#define BIT_MGTFLT13EN BIT(13)
+#define BIT_DATAFLT13EN BIT(13)
+#define BIT_MGTFLT12EN BIT(12)
+#define BIT_DATAFLT12EN BIT(12)
+#define BIT_MGTFLT11EN BIT(11)
+#define BIT_DATAFLT11EN BIT(11)
+#define BIT_MGTFLT10EN BIT(10)
+#define BIT_DATAFLT10EN BIT(10)
+#define BIT_MGTFLT9EN BIT(9)
+#define BIT_DATAFLT9EN BIT(9)
+#define BIT_MGTFLT8EN BIT(8)
+#define BIT_DATAFLT8EN BIT(8)
+#define BIT_DATAFLT7EN BIT(7)
-#define BIT_SHIFT_WKFMCAM_RWD 0
-#define BIT_MASK_WKFMCAM_RWD 0xffffffffL
-#define BIT_WKFMCAM_RWD(x) (((x) & BIT_MASK_WKFMCAM_RWD) << BIT_SHIFT_WKFMCAM_RWD)
-#define BIT_GET_WKFMCAM_RWD(x) (((x) >> BIT_SHIFT_WKFMCAM_RWD) & BIT_MASK_WKFMCAM_RWD)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_RXFLTMAP0 (Offset 0x06A0) */
-#define BIT_MGTFLT15EN BIT(15)
-#define BIT_MGTFLT14EN BIT(14)
+#define BIT_MGTFLT7EN BIT(7)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_RXFLTMAP0 (Offset 0x06A0) */
-#define BIT_MGTFLT13EN BIT(13)
-#define BIT_MGTFLT12EN BIT(12)
-#define BIT_MGTFLT11EN BIT(11)
-#define BIT_MGTFLT10EN BIT(10)
-#define BIT_MGTFLT9EN BIT(9)
-#define BIT_MGTFLT8EN BIT(8)
+#define BIT_DATAFLT6EN BIT(6)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_RXFLTMAP0 (Offset 0x06A0) */
-#define BIT_MGTFLT7EN BIT(7)
-#define BIT_MGTFLT6EN BIT(6)
+#define BIT_MGTFLT6EN BIT(6)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_RXFLTMAP0 (Offset 0x06A0) */
-#define BIT_MGTFLT5EN BIT(5)
-#define BIT_MGTFLT4EN BIT(4)
-#define BIT_MGTFLT3EN BIT(3)
-#define BIT_MGTFLT2EN BIT(2)
-#define BIT_MGTFLT1EN BIT(1)
-#define BIT_MGTFLT0EN BIT(0)
+#define BIT_MGTFLT5EN BIT(5)
+#define BIT_DATAFLT5EN BIT(5)
+#define BIT_MGTFLT4EN BIT(4)
+#define BIT_DATAFLT4EN BIT(4)
+#define BIT_MGTFLT3EN BIT(3)
+#define BIT_DATAFLT3EN BIT(3)
+#define BIT_MGTFLT2EN BIT(2)
+#define BIT_DATAFLT2EN BIT(2)
+#define BIT_MGTFLT1EN BIT(1)
+#define BIT_DATAFLT1EN BIT(1)
+#define BIT_MGTFLT0EN BIT(0)
+#define BIT_DATAFLT0EN BIT(0)
/* 2 REG_RXFLTMAP1 (Offset 0x06A2) */
-#define BIT_CTRLFLT15EN BIT(15)
-#define BIT_CTRLFLT14EN BIT(14)
-#define BIT_CTRLFLT13EN BIT(13)
-#define BIT_CTRLFLT12EN BIT(12)
-#define BIT_CTRLFLT11EN BIT(11)
-#define BIT_CTRLFLT10EN BIT(10)
-#define BIT_CTRLFLT9EN BIT(9)
-#define BIT_CTRLFLT8EN BIT(8)
-#define BIT_CTRLFLT7EN BIT(7)
-#define BIT_CTRLFLT6EN BIT(6)
+#define BIT_CTRLFLT15EN BIT(15)
+#define BIT_CTRLFLT14EN BIT(14)
+#define BIT_CTRLFLT13EN BIT(13)
+#define BIT_CTRLFLT12EN BIT(12)
+#define BIT_CTRLFLT11EN BIT(11)
+#define BIT_CTRLFLT10EN BIT(10)
+#define BIT_CTRLFLT9EN BIT(9)
+#define BIT_CTRLFLT8EN BIT(8)
+#define BIT_CTRLFLT7EN BIT(7)
+#define BIT_CTRLFLT6EN BIT(6)
#endif
-
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_RXFLTMAP1 (Offset 0x06A2) */
-#define BIT_CTRLFLT5EN BIT(5)
-#define BIT_CTRLFLT4EN BIT(4)
-#define BIT_CTRLFLT3EN BIT(3)
-#define BIT_CTRLFLT2EN BIT(2)
-#define BIT_CTRLFLT1EN BIT(1)
-#define BIT_CTRLFLT0EN BIT(0)
+#define BIT_CTRLFLT5EN BIT(5)
+#define BIT_CTRLFLT4EN BIT(4)
+#define BIT_CTRLFLT3EN BIT(3)
+#define BIT_CTRLFLT2EN BIT(2)
+#define BIT_CTRLFLT1EN BIT(1)
+#define BIT_CTRLFLT0EN BIT(0)
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
+/* 2 REG_BCN_PSR_RPT (Offset 0x06A8) */
-/* 2 REG_RXFLTMAP (Offset 0x06A4) */
+#define BIT_SHIFT_DTIM_CNT 24
+#define BIT_MASK_DTIM_CNT 0xff
+#define BIT_DTIM_CNT(x) (((x) & BIT_MASK_DTIM_CNT) << BIT_SHIFT_DTIM_CNT)
+#define BITS_DTIM_CNT (BIT_MASK_DTIM_CNT << BIT_SHIFT_DTIM_CNT)
+#define BIT_CLEAR_DTIM_CNT(x) ((x) & (~BITS_DTIM_CNT))
+#define BIT_GET_DTIM_CNT(x) (((x) >> BIT_SHIFT_DTIM_CNT) & BIT_MASK_DTIM_CNT)
+#define BIT_SET_DTIM_CNT(x, v) (BIT_CLEAR_DTIM_CNT(x) | BIT_DTIM_CNT(v))
+
+#define BIT_SHIFT_DTIM_PERIOD 16
+#define BIT_MASK_DTIM_PERIOD 0xff
+#define BIT_DTIM_PERIOD(x) \
+ (((x) & BIT_MASK_DTIM_PERIOD) << BIT_SHIFT_DTIM_PERIOD)
+#define BITS_DTIM_PERIOD (BIT_MASK_DTIM_PERIOD << BIT_SHIFT_DTIM_PERIOD)
+#define BIT_CLEAR_DTIM_PERIOD(x) ((x) & (~BITS_DTIM_PERIOD))
+#define BIT_GET_DTIM_PERIOD(x) \
+ (((x) >> BIT_SHIFT_DTIM_PERIOD) & BIT_MASK_DTIM_PERIOD)
+#define BIT_SET_DTIM_PERIOD(x, v) \
+ (BIT_CLEAR_DTIM_PERIOD(x) | BIT_DTIM_PERIOD(v))
+
+#define BIT_DTIM BIT(15)
+#define BIT_TIM BIT(14)
+
+#define BIT_SHIFT_PS_AID_0 0
+#define BIT_MASK_PS_AID_0 0x7ff
+#define BIT_PS_AID_0(x) (((x) & BIT_MASK_PS_AID_0) << BIT_SHIFT_PS_AID_0)
+#define BITS_PS_AID_0 (BIT_MASK_PS_AID_0 << BIT_SHIFT_PS_AID_0)
+#define BIT_CLEAR_PS_AID_0(x) ((x) & (~BITS_PS_AID_0))
+#define BIT_GET_PS_AID_0(x) (((x) >> BIT_SHIFT_PS_AID_0) & BIT_MASK_PS_AID_0)
+#define BIT_SET_PS_AID_0(x, v) (BIT_CLEAR_PS_AID_0(x) | BIT_PS_AID_0(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_DATAFLT15EN BIT(15)
-#define BIT_DATAFLT14EN BIT(14)
-#define BIT_DATAFLT13EN BIT(13)
-#define BIT_DATAFLT12EN BIT(12)
-#define BIT_DATAFLT11EN BIT(11)
-#define BIT_DATAFLT10EN BIT(10)
-#define BIT_DATAFLT9EN BIT(9)
-#define BIT_DATAFLT8EN BIT(8)
-#define BIT_DATAFLT7EN BIT(7)
-#define BIT_DATAFLT6EN BIT(6)
-#define BIT_DATAFLT5EN BIT(5)
-#define BIT_DATAFLT4EN BIT(4)
-#define BIT_DATAFLT3EN BIT(3)
-#define BIT_DATAFLT2EN BIT(2)
-#define BIT_DATAFLT1EN BIT(1)
-#define BIT_DATAFLT0EN BIT(0)
+/* 2 REG_FLC_RPC (Offset 0x06AC) */
-/* 2 REG_BCN_PSR_RPT (Offset 0x06A8) */
+#define BIT_SHIFT_FLC_RPC 0
+#define BIT_MASK_FLC_RPC 0xff
+#define BIT_FLC_RPC(x) (((x) & BIT_MASK_FLC_RPC) << BIT_SHIFT_FLC_RPC)
+#define BITS_FLC_RPC (BIT_MASK_FLC_RPC << BIT_SHIFT_FLC_RPC)
+#define BIT_CLEAR_FLC_RPC(x) ((x) & (~BITS_FLC_RPC))
+#define BIT_GET_FLC_RPC(x) (((x) >> BIT_SHIFT_FLC_RPC) & BIT_MASK_FLC_RPC)
+#define BIT_SET_FLC_RPC(x, v) (BIT_CLEAR_FLC_RPC(x) | BIT_FLC_RPC(v))
+/* 2 REG_FLC_RPCT (Offset 0x06AD) */
-#define BIT_SHIFT_DTIM_CNT 24
-#define BIT_MASK_DTIM_CNT 0xff
-#define BIT_DTIM_CNT(x) (((x) & BIT_MASK_DTIM_CNT) << BIT_SHIFT_DTIM_CNT)
-#define BIT_GET_DTIM_CNT(x) (((x) >> BIT_SHIFT_DTIM_CNT) & BIT_MASK_DTIM_CNT)
+#define BIT_SHIFT_FLC_RPCT 0
+#define BIT_MASK_FLC_RPCT 0xff
+#define BIT_FLC_RPCT(x) (((x) & BIT_MASK_FLC_RPCT) << BIT_SHIFT_FLC_RPCT)
+#define BITS_FLC_RPCT (BIT_MASK_FLC_RPCT << BIT_SHIFT_FLC_RPCT)
+#define BIT_CLEAR_FLC_RPCT(x) ((x) & (~BITS_FLC_RPCT))
+#define BIT_GET_FLC_RPCT(x) (((x) >> BIT_SHIFT_FLC_RPCT) & BIT_MASK_FLC_RPCT)
+#define BIT_SET_FLC_RPCT(x, v) (BIT_CLEAR_FLC_RPCT(x) | BIT_FLC_RPCT(v))
+/* 2 REG_FLC_PTS (Offset 0x06AE) */
-#define BIT_SHIFT_DTIM_PERIOD 16
-#define BIT_MASK_DTIM_PERIOD 0xff
-#define BIT_DTIM_PERIOD(x) (((x) & BIT_MASK_DTIM_PERIOD) << BIT_SHIFT_DTIM_PERIOD)
-#define BIT_GET_DTIM_PERIOD(x) (((x) >> BIT_SHIFT_DTIM_PERIOD) & BIT_MASK_DTIM_PERIOD)
+#define BIT_CMF BIT(2)
+#define BIT_CCF BIT(1)
+#define BIT_CDF BIT(0)
-#define BIT_DTIM BIT(15)
-#define BIT_TIM BIT(14)
+/* 2 REG_FLC_TRPC (Offset 0x06AF) */
-#define BIT_SHIFT_PS_AID_0 0
-#define BIT_MASK_PS_AID_0 0x7ff
-#define BIT_PS_AID_0(x) (((x) & BIT_MASK_PS_AID_0) << BIT_SHIFT_PS_AID_0)
-#define BIT_GET_PS_AID_0(x) (((x) >> BIT_SHIFT_PS_AID_0) & BIT_MASK_PS_AID_0)
+#define BIT_FLC_RPCT_V1 BIT(7)
+#define BIT_MODE BIT(6)
+#define BIT_SHIFT_TRPCD 0
+#define BIT_MASK_TRPCD 0x3f
+#define BIT_TRPCD(x) (((x) & BIT_MASK_TRPCD) << BIT_SHIFT_TRPCD)
+#define BITS_TRPCD (BIT_MASK_TRPCD << BIT_SHIFT_TRPCD)
+#define BIT_CLEAR_TRPCD(x) ((x) & (~BITS_TRPCD))
+#define BIT_GET_TRPCD(x) (((x) >> BIT_SHIFT_TRPCD) & BIT_MASK_TRPCD)
+#define BIT_SET_TRPCD(x, v) (BIT_CLEAR_TRPCD(x) | BIT_TRPCD(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_RXPKTMON_CTRL (Offset 0x06B0) */
+#define BIT_SHIFT_RXBKQPKT_SEQ 20
+#define BIT_MASK_RXBKQPKT_SEQ 0xf
+#define BIT_RXBKQPKT_SEQ(x) \
+ (((x) & BIT_MASK_RXBKQPKT_SEQ) << BIT_SHIFT_RXBKQPKT_SEQ)
+#define BITS_RXBKQPKT_SEQ (BIT_MASK_RXBKQPKT_SEQ << BIT_SHIFT_RXBKQPKT_SEQ)
+#define BIT_CLEAR_RXBKQPKT_SEQ(x) ((x) & (~BITS_RXBKQPKT_SEQ))
+#define BIT_GET_RXBKQPKT_SEQ(x) \
+ (((x) >> BIT_SHIFT_RXBKQPKT_SEQ) & BIT_MASK_RXBKQPKT_SEQ)
+#define BIT_SET_RXBKQPKT_SEQ(x, v) \
+ (BIT_CLEAR_RXBKQPKT_SEQ(x) | BIT_RXBKQPKT_SEQ(v))
+
+#define BIT_SHIFT_RXBEQPKT_SEQ 16
+#define BIT_MASK_RXBEQPKT_SEQ 0xf
+#define BIT_RXBEQPKT_SEQ(x) \
+ (((x) & BIT_MASK_RXBEQPKT_SEQ) << BIT_SHIFT_RXBEQPKT_SEQ)
+#define BITS_RXBEQPKT_SEQ (BIT_MASK_RXBEQPKT_SEQ << BIT_SHIFT_RXBEQPKT_SEQ)
+#define BIT_CLEAR_RXBEQPKT_SEQ(x) ((x) & (~BITS_RXBEQPKT_SEQ))
+#define BIT_GET_RXBEQPKT_SEQ(x) \
+ (((x) >> BIT_SHIFT_RXBEQPKT_SEQ) & BIT_MASK_RXBEQPKT_SEQ)
+#define BIT_SET_RXBEQPKT_SEQ(x, v) \
+ (BIT_CLEAR_RXBEQPKT_SEQ(x) | BIT_RXBEQPKT_SEQ(v))
+
+#define BIT_SHIFT_RXVIQPKT_SEQ 12
+#define BIT_MASK_RXVIQPKT_SEQ 0xf
+#define BIT_RXVIQPKT_SEQ(x) \
+ (((x) & BIT_MASK_RXVIQPKT_SEQ) << BIT_SHIFT_RXVIQPKT_SEQ)
+#define BITS_RXVIQPKT_SEQ (BIT_MASK_RXVIQPKT_SEQ << BIT_SHIFT_RXVIQPKT_SEQ)
+#define BIT_CLEAR_RXVIQPKT_SEQ(x) ((x) & (~BITS_RXVIQPKT_SEQ))
+#define BIT_GET_RXVIQPKT_SEQ(x) \
+ (((x) >> BIT_SHIFT_RXVIQPKT_SEQ) & BIT_MASK_RXVIQPKT_SEQ)
+#define BIT_SET_RXVIQPKT_SEQ(x, v) \
+ (BIT_CLEAR_RXVIQPKT_SEQ(x) | BIT_RXVIQPKT_SEQ(v))
+
+#define BIT_SHIFT_RXVOQPKT_SEQ 8
+#define BIT_MASK_RXVOQPKT_SEQ 0xf
+#define BIT_RXVOQPKT_SEQ(x) \
+ (((x) & BIT_MASK_RXVOQPKT_SEQ) << BIT_SHIFT_RXVOQPKT_SEQ)
+#define BITS_RXVOQPKT_SEQ (BIT_MASK_RXVOQPKT_SEQ << BIT_SHIFT_RXVOQPKT_SEQ)
+#define BIT_CLEAR_RXVOQPKT_SEQ(x) ((x) & (~BITS_RXVOQPKT_SEQ))
+#define BIT_GET_RXVOQPKT_SEQ(x) \
+ (((x) >> BIT_SHIFT_RXVOQPKT_SEQ) & BIT_MASK_RXVOQPKT_SEQ)
+#define BIT_SET_RXVOQPKT_SEQ(x, v) \
+ (BIT_CLEAR_RXVOQPKT_SEQ(x) | BIT_RXVOQPKT_SEQ(v))
+
+#define BIT_RXBKQPKT_ERR BIT(7)
+#define BIT_RXBEQPKT_ERR BIT(6)
+#define BIT_RXVIQPKT_ERR BIT(5)
+#define BIT_RXVOQPKT_ERR BIT(4)
+#define BIT_RXDMA_MON_EN BIT(2)
+#define BIT_RXPKT_MON_RST BIT(1)
+#define BIT_RXPKT_MON_EN BIT(0)
-/* 2 REG_FLC_RPC (Offset 0x06AC) */
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_FLC_RPC 0
-#define BIT_MASK_FLC_RPC 0xff
-#define BIT_FLC_RPC(x) (((x) & BIT_MASK_FLC_RPC) << BIT_SHIFT_FLC_RPC)
-#define BIT_GET_FLC_RPC(x) (((x) >> BIT_SHIFT_FLC_RPC) & BIT_MASK_FLC_RPC)
+/* 2 REG_STATE_MON (Offset 0x06B4) */
+#define BIT_SHIFT_DMA_MON_EN 24
+#define BIT_MASK_DMA_MON_EN 0x1f
+#define BIT_DMA_MON_EN(x) (((x) & BIT_MASK_DMA_MON_EN) << BIT_SHIFT_DMA_MON_EN)
+#define BITS_DMA_MON_EN (BIT_MASK_DMA_MON_EN << BIT_SHIFT_DMA_MON_EN)
+#define BIT_CLEAR_DMA_MON_EN(x) ((x) & (~BITS_DMA_MON_EN))
+#define BIT_GET_DMA_MON_EN(x) \
+ (((x) >> BIT_SHIFT_DMA_MON_EN) & BIT_MASK_DMA_MON_EN)
+#define BIT_SET_DMA_MON_EN(x, v) (BIT_CLEAR_DMA_MON_EN(x) | BIT_DMA_MON_EN(v))
-/* 2 REG_FLC_RPCT (Offset 0x06AD) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_FLC_RPCT 0
-#define BIT_MASK_FLC_RPCT 0xff
-#define BIT_FLC_RPCT(x) (((x) & BIT_MASK_FLC_RPCT) << BIT_SHIFT_FLC_RPCT)
-#define BIT_GET_FLC_RPCT(x) (((x) >> BIT_SHIFT_FLC_RPCT) & BIT_MASK_FLC_RPCT)
+/* 2 REG_STATE_MON (Offset 0x06B4) */
+#define BIT_SHIFT_STATE_SEL 24
+#define BIT_MASK_STATE_SEL 0x1f
+#define BIT_STATE_SEL(x) (((x) & BIT_MASK_STATE_SEL) << BIT_SHIFT_STATE_SEL)
+#define BITS_STATE_SEL (BIT_MASK_STATE_SEL << BIT_SHIFT_STATE_SEL)
+#define BIT_CLEAR_STATE_SEL(x) ((x) & (~BITS_STATE_SEL))
+#define BIT_GET_STATE_SEL(x) (((x) >> BIT_SHIFT_STATE_SEL) & BIT_MASK_STATE_SEL)
+#define BIT_SET_STATE_SEL(x, v) (BIT_CLEAR_STATE_SEL(x) | BIT_STATE_SEL(v))
-/* 2 REG_FLC_PTS (Offset 0x06AE) */
+#define BIT_SHIFT_STATE_INFO 8
+#define BIT_MASK_STATE_INFO 0xff
+#define BIT_STATE_INFO(x) (((x) & BIT_MASK_STATE_INFO) << BIT_SHIFT_STATE_INFO)
+#define BITS_STATE_INFO (BIT_MASK_STATE_INFO << BIT_SHIFT_STATE_INFO)
+#define BIT_CLEAR_STATE_INFO(x) ((x) & (~BITS_STATE_INFO))
+#define BIT_GET_STATE_INFO(x) \
+ (((x) >> BIT_SHIFT_STATE_INFO) & BIT_MASK_STATE_INFO)
+#define BIT_SET_STATE_INFO(x, v) (BIT_CLEAR_STATE_INFO(x) | BIT_STATE_INFO(v))
-#define BIT_CMF BIT(2)
-#define BIT_CCF BIT(1)
-#define BIT_CDF BIT(0)
+#define BIT_UPD_NXT_STATE BIT(7)
-/* 2 REG_FLC_TRPC (Offset 0x06AF) */
+#endif
-#define BIT_FLC_RPCT_V1 BIT(7)
-#define BIT_MODE BIT(6)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_TRPCD 0
-#define BIT_MASK_TRPCD 0x3f
-#define BIT_TRPCD(x) (((x) & BIT_MASK_TRPCD) << BIT_SHIFT_TRPCD)
-#define BIT_GET_TRPCD(x) (((x) >> BIT_SHIFT_TRPCD) & BIT_MASK_TRPCD)
+/* 2 REG_STATE_MON (Offset 0x06B4) */
+#define BIT_SHIFT_PKT_MON_EN 0
+#define BIT_MASK_PKT_MON_EN 0x7f
+#define BIT_PKT_MON_EN(x) (((x) & BIT_MASK_PKT_MON_EN) << BIT_SHIFT_PKT_MON_EN)
+#define BITS_PKT_MON_EN (BIT_MASK_PKT_MON_EN << BIT_SHIFT_PKT_MON_EN)
+#define BIT_CLEAR_PKT_MON_EN(x) ((x) & (~BITS_PKT_MON_EN))
+#define BIT_GET_PKT_MON_EN(x) \
+ (((x) >> BIT_SHIFT_PKT_MON_EN) & BIT_MASK_PKT_MON_EN)
+#define BIT_SET_PKT_MON_EN(x, v) (BIT_CLEAR_PKT_MON_EN(x) | BIT_PKT_MON_EN(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_RXPKTMON_CTRL (Offset 0x06B0) */
+/* 2 REG_STATE_MON (Offset 0x06B4) */
+#define BIT_SHIFT_CUR_STATE 0
+#define BIT_MASK_CUR_STATE 0x7f
+#define BIT_CUR_STATE(x) (((x) & BIT_MASK_CUR_STATE) << BIT_SHIFT_CUR_STATE)
+#define BITS_CUR_STATE (BIT_MASK_CUR_STATE << BIT_SHIFT_CUR_STATE)
+#define BIT_CLEAR_CUR_STATE(x) ((x) & (~BITS_CUR_STATE))
+#define BIT_GET_CUR_STATE(x) (((x) >> BIT_SHIFT_CUR_STATE) & BIT_MASK_CUR_STATE)
+#define BIT_SET_CUR_STATE(x, v) (BIT_CLEAR_CUR_STATE(x) | BIT_CUR_STATE(v))
-#define BIT_SHIFT_RXBKQPKT_SEQ 20
-#define BIT_MASK_RXBKQPKT_SEQ 0xf
-#define BIT_RXBKQPKT_SEQ(x) (((x) & BIT_MASK_RXBKQPKT_SEQ) << BIT_SHIFT_RXBKQPKT_SEQ)
-#define BIT_GET_RXBKQPKT_SEQ(x) (((x) >> BIT_SHIFT_RXBKQPKT_SEQ) & BIT_MASK_RXBKQPKT_SEQ)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_RXBEQPKT_SEQ 16
-#define BIT_MASK_RXBEQPKT_SEQ 0xf
-#define BIT_RXBEQPKT_SEQ(x) (((x) & BIT_MASK_RXBEQPKT_SEQ) << BIT_SHIFT_RXBEQPKT_SEQ)
-#define BIT_GET_RXBEQPKT_SEQ(x) (((x) >> BIT_SHIFT_RXBEQPKT_SEQ) & BIT_MASK_RXBEQPKT_SEQ)
+/* 2 REG_ERROR_MON (Offset 0x06B8) */
+#define BIT_CSIRPT_LEN_BB_MORE_THAN_MAC BIT(23)
+#define BIT_CSI_CHKSUM_ERROR BIT(22)
-#define BIT_SHIFT_RXVIQPKT_SEQ 12
-#define BIT_MASK_RXVIQPKT_SEQ 0xf
-#define BIT_RXVIQPKT_SEQ(x) (((x) & BIT_MASK_RXVIQPKT_SEQ) << BIT_SHIFT_RXVIQPKT_SEQ)
-#define BIT_GET_RXVIQPKT_SEQ(x) (((x) >> BIT_SHIFT_RXVIQPKT_SEQ) & BIT_MASK_RXVIQPKT_SEQ)
+#endif
+#if (HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_RXVOQPKT_SEQ 8
-#define BIT_MASK_RXVOQPKT_SEQ 0xf
-#define BIT_RXVOQPKT_SEQ(x) (((x) & BIT_MASK_RXVOQPKT_SEQ) << BIT_SHIFT_RXVOQPKT_SEQ)
-#define BIT_GET_RXVOQPKT_SEQ(x) (((x) >> BIT_SHIFT_RXVOQPKT_SEQ) & BIT_MASK_RXVOQPKT_SEQ)
+/* 2 REG_ERROR_MON (Offset 0x06B8) */
-#define BIT_RXBKQPKT_ERR BIT(7)
-#define BIT_RXBEQPKT_ERR BIT(6)
-#define BIT_RXVIQPKT_ERR BIT(5)
-#define BIT_RXVOQPKT_ERR BIT(4)
-#define BIT_RXDMA_MON_EN BIT(2)
-#define BIT_RXPKT_MON_RST BIT(1)
-#define BIT_RXPKT_MON_EN BIT(0)
+#define BIT_BFM_RPTNUM_ERROR BIT(21)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_ERROR_MON (Offset 0x06B8) */
+#define BIT_MACRX_ERR_5 BIT(21)
-/* 2 REG_STATE_MON (Offset 0x06B4) */
+#endif
+#if (HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_DMA_MON_EN 24
-#define BIT_MASK_DMA_MON_EN 0x1f
-#define BIT_DMA_MON_EN(x) (((x) & BIT_MASK_DMA_MON_EN) << BIT_SHIFT_DMA_MON_EN)
-#define BIT_GET_DMA_MON_EN(x) (((x) >> BIT_SHIFT_DMA_MON_EN) & BIT_MASK_DMA_MON_EN)
+/* 2 REG_ERROR_MON (Offset 0x06B8) */
+#define BIT_BFM_CHECKSUM_ERROR BIT(20)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_STATE_MON (Offset 0x06B4) */
+/* 2 REG_ERROR_MON (Offset 0x06B8) */
+#define BIT_MACRX_ERR_4 BIT(20)
+#define BIT_MACRX_ERR_3 BIT(19)
+#define BIT_MACRX_ERR_2 BIT(18)
-#define BIT_SHIFT_STATE_SEL 24
-#define BIT_MASK_STATE_SEL 0x1f
-#define BIT_STATE_SEL(x) (((x) & BIT_MASK_STATE_SEL) << BIT_SHIFT_STATE_SEL)
-#define BIT_GET_STATE_SEL(x) (((x) >> BIT_SHIFT_STATE_SEL) & BIT_MASK_STATE_SEL)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_STATE_INFO 8
-#define BIT_MASK_STATE_INFO 0xff
-#define BIT_STATE_INFO(x) (((x) & BIT_MASK_STATE_INFO) << BIT_SHIFT_STATE_INFO)
-#define BIT_GET_STATE_INFO(x) (((x) >> BIT_SHIFT_STATE_INFO) & BIT_MASK_STATE_INFO)
+/* 2 REG_ERROR_MON (Offset 0x06B8) */
-#define BIT_UPD_NXT_STATE BIT(7)
+#define BIT_MACRX_ERR_1 BIT(17)
+#define BIT_MACRX_ERR_0 BIT(16)
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_ERROR_MON (Offset 0x06B8) */
+#define BIT_PRETX_ERRHDL_EN BIT(15)
-/* 2 REG_STATE_MON (Offset 0x06B4) */
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_PKT_MON_EN 0
-#define BIT_MASK_PKT_MON_EN 0x7f
-#define BIT_PKT_MON_EN(x) (((x) & BIT_MASK_PKT_MON_EN) << BIT_SHIFT_PKT_MON_EN)
-#define BIT_GET_PKT_MON_EN(x) (((x) >> BIT_SHIFT_PKT_MON_EN) & BIT_MASK_PKT_MON_EN)
+/* 2 REG_ERROR_MON (Offset 0x06B8) */
+#define BIT_WMAC_PRETX_ERRHDL_EN BIT(15)
+#define BIT_MACTX_ERR_5 BIT(5)
#endif
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_STATE_MON (Offset 0x06B4) */
+/* 2 REG_ERROR_MON (Offset 0x06B8) */
+#define BIT_MACTX_ERR_4 BIT(4)
-#define BIT_SHIFT_CUR_STATE 0
-#define BIT_MASK_CUR_STATE 0x7f
-#define BIT_CUR_STATE(x) (((x) & BIT_MASK_CUR_STATE) << BIT_SHIFT_CUR_STATE)
-#define BIT_GET_CUR_STATE(x) (((x) >> BIT_SHIFT_CUR_STATE) & BIT_MASK_CUR_STATE)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_ERROR_MON (Offset 0x06B8) */
-#define BIT_MACRX_ERR_1 BIT(17)
-#define BIT_MACRX_ERR_0 BIT(16)
-#define BIT_MACTX_ERR_3 BIT(3)
-#define BIT_MACTX_ERR_2 BIT(2)
-#define BIT_MACTX_ERR_1 BIT(1)
-#define BIT_MACTX_ERR_0 BIT(0)
+#define BIT_MACTX_ERR_3 BIT(3)
+#define BIT_MACTX_ERR_2 BIT(2)
+#define BIT_MACTX_ERR_1 BIT(1)
+#define BIT_MACTX_ERR_0 BIT(0)
/* 2 REG_SEARCH_MACID (Offset 0x06BC) */
-#define BIT_EN_TXRPTBUF_CLK BIT(31)
+#define BIT_EN_TXRPTBUF_CLK BIT(31)
-#define BIT_SHIFT_INFO_INDEX_OFFSET 16
-#define BIT_MASK_INFO_INDEX_OFFSET 0x1fff
-#define BIT_INFO_INDEX_OFFSET(x) (((x) & BIT_MASK_INFO_INDEX_OFFSET) << BIT_SHIFT_INFO_INDEX_OFFSET)
-#define BIT_GET_INFO_INDEX_OFFSET(x) (((x) >> BIT_SHIFT_INFO_INDEX_OFFSET) & BIT_MASK_INFO_INDEX_OFFSET)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_SEARCH_MACID (Offset 0x06BC) */
+#define BIT_SHIFT_INFO_INDEX_OFFSET 16
+#define BIT_MASK_INFO_INDEX_OFFSET 0x1fff
+#define BIT_INFO_INDEX_OFFSET(x) \
+ (((x) & BIT_MASK_INFO_INDEX_OFFSET) << BIT_SHIFT_INFO_INDEX_OFFSET)
+#define BITS_INFO_INDEX_OFFSET \
+ (BIT_MASK_INFO_INDEX_OFFSET << BIT_SHIFT_INFO_INDEX_OFFSET)
+#define BIT_CLEAR_INFO_INDEX_OFFSET(x) ((x) & (~BITS_INFO_INDEX_OFFSET))
+#define BIT_GET_INFO_INDEX_OFFSET(x) \
+ (((x) >> BIT_SHIFT_INFO_INDEX_OFFSET) & BIT_MASK_INFO_INDEX_OFFSET)
+#define BIT_SET_INFO_INDEX_OFFSET(x, v) \
+ (BIT_CLEAR_INFO_INDEX_OFFSET(x) | BIT_INFO_INDEX_OFFSET(v))
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_SEARCH_MACID (Offset 0x06BC) */
-#define BIT_WMAC_SRCH_FIFOFULL BIT(15)
+#define BIT_WMAC_SRCH_FIFOFULL BIT(15)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_SEARCH_MACID (Offset 0x06BC) */
+#define BIT_DIS_INFOSRCH BIT(14)
-/* 2 REG_SEARCH_MACID (Offset 0x06BC) */
+#endif
-#define BIT_DIS_INFOSRCH BIT(14)
-#define BIT_DISABLE_B0 BIT(13)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_INFO_ADDR_OFFSET 0
-#define BIT_MASK_INFO_ADDR_OFFSET 0x1fff
-#define BIT_INFO_ADDR_OFFSET(x) (((x) & BIT_MASK_INFO_ADDR_OFFSET) << BIT_SHIFT_INFO_ADDR_OFFSET)
-#define BIT_GET_INFO_ADDR_OFFSET(x) (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET) & BIT_MASK_INFO_ADDR_OFFSET)
+/* 2 REG_SEARCH_MACID (Offset 0x06BC) */
+#define BIT_DISABLE_B0 BIT(13)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_SEARCH_MACID (Offset 0x06BC) */
+#define BIT_SHIFT_INFO_ADDR_OFFSET 0
+#define BIT_MASK_INFO_ADDR_OFFSET 0x1fff
+#define BIT_INFO_ADDR_OFFSET(x) \
+ (((x) & BIT_MASK_INFO_ADDR_OFFSET) << BIT_SHIFT_INFO_ADDR_OFFSET)
+#define BITS_INFO_ADDR_OFFSET \
+ (BIT_MASK_INFO_ADDR_OFFSET << BIT_SHIFT_INFO_ADDR_OFFSET)
+#define BIT_CLEAR_INFO_ADDR_OFFSET(x) ((x) & (~BITS_INFO_ADDR_OFFSET))
+#define BIT_GET_INFO_ADDR_OFFSET(x) \
+ (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET) & BIT_MASK_INFO_ADDR_OFFSET)
+#define BIT_SET_INFO_ADDR_OFFSET(x, v) \
+ (BIT_CLEAR_INFO_ADDR_OFFSET(x) | BIT_INFO_ADDR_OFFSET(v))
-/* 2 REG_BT_COEX_TABLE (Offset 0x06C0) */
+#endif
-#define BIT_PRI_MASK_RX_RESP BIT(126)
-#define BIT_PRI_MASK_RXOFDM BIT(125)
-#define BIT_PRI_MASK_RXCCK BIT(124)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_PRI_MASK_TXAC (117 & CPU_OPT_WIDTH)
-#define BIT_MASK_PRI_MASK_TXAC 0x7f
-#define BIT_PRI_MASK_TXAC(x) (((x) & BIT_MASK_PRI_MASK_TXAC) << BIT_SHIFT_PRI_MASK_TXAC)
-#define BIT_GET_PRI_MASK_TXAC(x) (((x) >> BIT_SHIFT_PRI_MASK_TXAC) & BIT_MASK_PRI_MASK_TXAC)
+/* 2 REG_BT_COEX_TABLE (Offset 0x06C0) */
+#define BIT_PRI_MASK_RX_RESP BIT(126)
+#define BIT_PRI_MASK_RXOFDM BIT(125)
+#define BIT_PRI_MASK_RXCCK BIT(124)
+#define BIT_PRI_MASK_CCK BIT(108)
+#define BIT_PRI_MASK_OFDM BIT(107)
+#define BIT_PRI_MASK_RTY BIT(106)
+#define BIT_OOB BIT(97)
+#define BIT_ANT_SEL BIT(96)
-#define BIT_SHIFT_PRI_MASK_NAV (109 & CPU_OPT_WIDTH)
-#define BIT_MASK_PRI_MASK_NAV 0xff
-#define BIT_PRI_MASK_NAV(x) (((x) & BIT_MASK_PRI_MASK_NAV) << BIT_SHIFT_PRI_MASK_NAV)
-#define BIT_GET_PRI_MASK_NAV(x) (((x) >> BIT_SHIFT_PRI_MASK_NAV) & BIT_MASK_PRI_MASK_NAV)
+#endif
-#define BIT_PRI_MASK_CCK BIT(108)
-#define BIT_PRI_MASK_OFDM BIT(107)
-#define BIT_PRI_MASK_RTY BIT(106)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_PRI_MASK_NUM (102 & CPU_OPT_WIDTH)
-#define BIT_MASK_PRI_MASK_NUM 0xf
-#define BIT_PRI_MASK_NUM(x) (((x) & BIT_MASK_PRI_MASK_NUM) << BIT_SHIFT_PRI_MASK_NUM)
-#define BIT_GET_PRI_MASK_NUM(x) (((x) >> BIT_SHIFT_PRI_MASK_NUM) & BIT_MASK_PRI_MASK_NUM)
+/* 2 REG_BT_COEX_TABLE (Offset 0x06C0) */
+#define BIT_SHIFT_COEX_TABLE_1 0
+#define BIT_MASK_COEX_TABLE_1 0xffffffffL
+#define BIT_COEX_TABLE_1(x) \
+ (((x) & BIT_MASK_COEX_TABLE_1) << BIT_SHIFT_COEX_TABLE_1)
+#define BITS_COEX_TABLE_1 (BIT_MASK_COEX_TABLE_1 << BIT_SHIFT_COEX_TABLE_1)
+#define BIT_CLEAR_COEX_TABLE_1(x) ((x) & (~BITS_COEX_TABLE_1))
+#define BIT_GET_COEX_TABLE_1(x) \
+ (((x) >> BIT_SHIFT_COEX_TABLE_1) & BIT_MASK_COEX_TABLE_1)
+#define BIT_SET_COEX_TABLE_1(x, v) \
+ (BIT_CLEAR_COEX_TABLE_1(x) | BIT_COEX_TABLE_1(v))
-#define BIT_SHIFT_PRI_MASK_TYPE (98 & CPU_OPT_WIDTH)
-#define BIT_MASK_PRI_MASK_TYPE 0xf
-#define BIT_PRI_MASK_TYPE(x) (((x) & BIT_MASK_PRI_MASK_TYPE) << BIT_SHIFT_PRI_MASK_TYPE)
-#define BIT_GET_PRI_MASK_TYPE(x) (((x) >> BIT_SHIFT_PRI_MASK_TYPE) & BIT_MASK_PRI_MASK_TYPE)
+#endif
-#define BIT_OOB BIT(97)
-#define BIT_ANT_SEL BIT(96)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_BREAK_TABLE_2 (80 & CPU_OPT_WIDTH)
-#define BIT_MASK_BREAK_TABLE_2 0xffff
-#define BIT_BREAK_TABLE_2(x) (((x) & BIT_MASK_BREAK_TABLE_2) << BIT_SHIFT_BREAK_TABLE_2)
-#define BIT_GET_BREAK_TABLE_2(x) (((x) >> BIT_SHIFT_BREAK_TABLE_2) & BIT_MASK_BREAK_TABLE_2)
+/* 2 REG_BT_COEX_TABLE_H (Offset 0x06CC) */
+#define BIT_PRI_MASK_RX_RESP_V1 BIT(30)
+#define BIT_PRI_MASK_RXOFDM_V1 BIT(29)
+#define BIT_PRI_MASK_RXCCK_V1 BIT(28)
+#define BIT_PRI_MASK_CCK_V1 BIT(12)
+#define BIT_PRI_MASK_OFDM_V1 BIT(11)
+#define BIT_PRI_MASK_RTY_V1 BIT(10)
+#define BIT_OOB_V1 BIT(1)
+#define BIT_ANT_SEL_V1 BIT(0)
-#define BIT_SHIFT_BREAK_TABLE_1 (64 & CPU_OPT_WIDTH)
-#define BIT_MASK_BREAK_TABLE_1 0xffff
-#define BIT_BREAK_TABLE_1(x) (((x) & BIT_MASK_BREAK_TABLE_1) << BIT_SHIFT_BREAK_TABLE_1)
-#define BIT_GET_BREAK_TABLE_1(x) (((x) >> BIT_SHIFT_BREAK_TABLE_1) & BIT_MASK_BREAK_TABLE_1)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_COEX_TABLE_2 (32 & CPU_OPT_WIDTH)
-#define BIT_MASK_COEX_TABLE_2 0xffffffffL
-#define BIT_COEX_TABLE_2(x) (((x) & BIT_MASK_COEX_TABLE_2) << BIT_SHIFT_COEX_TABLE_2)
-#define BIT_GET_COEX_TABLE_2(x) (((x) >> BIT_SHIFT_COEX_TABLE_2) & BIT_MASK_COEX_TABLE_2)
-
+/* 2 REG_RXCMD_0 (Offset 0x06D0) */
-#define BIT_SHIFT_COEX_TABLE_1 0
-#define BIT_MASK_COEX_TABLE_1 0xffffffffL
-#define BIT_COEX_TABLE_1(x) (((x) & BIT_MASK_COEX_TABLE_1) << BIT_SHIFT_COEX_TABLE_1)
-#define BIT_GET_COEX_TABLE_1(x) (((x) >> BIT_SHIFT_COEX_TABLE_1) & BIT_MASK_COEX_TABLE_1)
+#define BIT_RXCMD_EN BIT(31)
+#define BIT_SHIFT_RXCMD_INFO 0
+#define BIT_MASK_RXCMD_INFO 0x7fffffffL
+#define BIT_RXCMD_INFO(x) (((x) & BIT_MASK_RXCMD_INFO) << BIT_SHIFT_RXCMD_INFO)
+#define BITS_RXCMD_INFO (BIT_MASK_RXCMD_INFO << BIT_SHIFT_RXCMD_INFO)
+#define BIT_CLEAR_RXCMD_INFO(x) ((x) & (~BITS_RXCMD_INFO))
+#define BIT_GET_RXCMD_INFO(x) \
+ (((x) >> BIT_SHIFT_RXCMD_INFO) & BIT_MASK_RXCMD_INFO)
+#define BIT_SET_RXCMD_INFO(x, v) (BIT_CLEAR_RXCMD_INFO(x) | BIT_RXCMD_INFO(v))
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_RXCMD_1 (Offset 0x06D4) */
+#define BIT_SHIFT_CSI_RADDR_LATCH_V1 24
+#define BIT_MASK_CSI_RADDR_LATCH_V1 0x3f
+#define BIT_CSI_RADDR_LATCH_V1(x) \
+ (((x) & BIT_MASK_CSI_RADDR_LATCH_V1) << BIT_SHIFT_CSI_RADDR_LATCH_V1)
+#define BITS_CSI_RADDR_LATCH_V1 \
+ (BIT_MASK_CSI_RADDR_LATCH_V1 << BIT_SHIFT_CSI_RADDR_LATCH_V1)
+#define BIT_CLEAR_CSI_RADDR_LATCH_V1(x) ((x) & (~BITS_CSI_RADDR_LATCH_V1))
+#define BIT_GET_CSI_RADDR_LATCH_V1(x) \
+ (((x) >> BIT_SHIFT_CSI_RADDR_LATCH_V1) & BIT_MASK_CSI_RADDR_LATCH_V1)
+#define BIT_SET_CSI_RADDR_LATCH_V1(x, v) \
+ (BIT_CLEAR_CSI_RADDR_LATCH_V1(x) | BIT_CSI_RADDR_LATCH_V1(v))
-/* 2 REG_RXCMD_0 (Offset 0x06D0) */
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT)
+
+/* 2 REG_RXCMD_1 (Offset 0x06D4) */
-#define BIT_RXCMD_EN BIT(31)
+#define BIT_SHIFT_CSI_RADDR_LATCH 24
+#define BIT_MASK_CSI_RADDR_LATCH 0xff
+#define BIT_CSI_RADDR_LATCH(x) \
+ (((x) & BIT_MASK_CSI_RADDR_LATCH) << BIT_SHIFT_CSI_RADDR_LATCH)
+#define BITS_CSI_RADDR_LATCH \
+ (BIT_MASK_CSI_RADDR_LATCH << BIT_SHIFT_CSI_RADDR_LATCH)
+#define BIT_CLEAR_CSI_RADDR_LATCH(x) ((x) & (~BITS_CSI_RADDR_LATCH))
+#define BIT_GET_CSI_RADDR_LATCH(x) \
+ (((x) >> BIT_SHIFT_CSI_RADDR_LATCH) & BIT_MASK_CSI_RADDR_LATCH)
+#define BIT_SET_CSI_RADDR_LATCH(x, v) \
+ (BIT_CLEAR_CSI_RADDR_LATCH(x) | BIT_CSI_RADDR_LATCH(v))
-#define BIT_SHIFT_RXCMD_INFO 0
-#define BIT_MASK_RXCMD_INFO 0x7fffffffL
-#define BIT_RXCMD_INFO(x) (((x) & BIT_MASK_RXCMD_INFO) << BIT_SHIFT_RXCMD_INFO)
-#define BIT_GET_RXCMD_INFO(x) (((x) >> BIT_SHIFT_RXCMD_INFO) & BIT_MASK_RXCMD_INFO)
+#endif
+#if (HALMAC_8198F_SUPPORT)
/* 2 REG_RXCMD_1 (Offset 0x06D4) */
+#define BIT_SHIFT_CSI_WADDR_LATCH_V1 16
+#define BIT_MASK_CSI_WADDR_LATCH_V1 0x3f
+#define BIT_CSI_WADDR_LATCH_V1(x) \
+ (((x) & BIT_MASK_CSI_WADDR_LATCH_V1) << BIT_SHIFT_CSI_WADDR_LATCH_V1)
+#define BITS_CSI_WADDR_LATCH_V1 \
+ (BIT_MASK_CSI_WADDR_LATCH_V1 << BIT_SHIFT_CSI_WADDR_LATCH_V1)
+#define BIT_CLEAR_CSI_WADDR_LATCH_V1(x) ((x) & (~BITS_CSI_WADDR_LATCH_V1))
+#define BIT_GET_CSI_WADDR_LATCH_V1(x) \
+ (((x) >> BIT_SHIFT_CSI_WADDR_LATCH_V1) & BIT_MASK_CSI_WADDR_LATCH_V1)
+#define BIT_SET_CSI_WADDR_LATCH_V1(x, v) \
+ (BIT_CLEAR_CSI_WADDR_LATCH_V1(x) | BIT_CSI_WADDR_LATCH_V1(v))
-#define BIT_SHIFT_RXCMD_PRD 0
-#define BIT_MASK_RXCMD_PRD 0xffff
-#define BIT_RXCMD_PRD(x) (((x) & BIT_MASK_RXCMD_PRD) << BIT_SHIFT_RXCMD_PRD)
-#define BIT_GET_RXCMD_PRD(x) (((x) >> BIT_SHIFT_RXCMD_PRD) & BIT_MASK_RXCMD_PRD)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT)
-/* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */
+/* 2 REG_RXCMD_1 (Offset 0x06D4) */
+#define BIT_SHIFT_CSI_WADDR_LATCH 16
+#define BIT_MASK_CSI_WADDR_LATCH 0xff
+#define BIT_CSI_WADDR_LATCH(x) \
+ (((x) & BIT_MASK_CSI_WADDR_LATCH) << BIT_SHIFT_CSI_WADDR_LATCH)
+#define BITS_CSI_WADDR_LATCH \
+ (BIT_MASK_CSI_WADDR_LATCH << BIT_SHIFT_CSI_WADDR_LATCH)
+#define BIT_CLEAR_CSI_WADDR_LATCH(x) ((x) & (~BITS_CSI_WADDR_LATCH))
+#define BIT_GET_CSI_WADDR_LATCH(x) \
+ (((x) >> BIT_SHIFT_CSI_WADDR_LATCH) & BIT_MASK_CSI_WADDR_LATCH)
+#define BIT_SET_CSI_WADDR_LATCH(x, v) \
+ (BIT_CLEAR_CSI_WADDR_LATCH(x) | BIT_CSI_WADDR_LATCH(v))
-#define BIT_SHIFT_WMAC_RESP_MFB 25
-#define BIT_MASK_WMAC_RESP_MFB 0x7f
-#define BIT_WMAC_RESP_MFB(x) (((x) & BIT_MASK_WMAC_RESP_MFB) << BIT_SHIFT_WMAC_RESP_MFB)
-#define BIT_GET_WMAC_RESP_MFB(x) (((x) >> BIT_SHIFT_WMAC_RESP_MFB) & BIT_MASK_WMAC_RESP_MFB)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_WMAC_ANTINF_SEL 23
-#define BIT_MASK_WMAC_ANTINF_SEL 0x3
-#define BIT_WMAC_ANTINF_SEL(x) (((x) & BIT_MASK_WMAC_ANTINF_SEL) << BIT_SHIFT_WMAC_ANTINF_SEL)
-#define BIT_GET_WMAC_ANTINF_SEL(x) (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL) & BIT_MASK_WMAC_ANTINF_SEL)
+/* 2 REG_RXCMD_1 (Offset 0x06D4) */
+#define BIT_SHIFT_RXCMD_PRD 0
+#define BIT_MASK_RXCMD_PRD 0xffff
+#define BIT_RXCMD_PRD(x) (((x) & BIT_MASK_RXCMD_PRD) << BIT_SHIFT_RXCMD_PRD)
+#define BITS_RXCMD_PRD (BIT_MASK_RXCMD_PRD << BIT_SHIFT_RXCMD_PRD)
+#define BIT_CLEAR_RXCMD_PRD(x) ((x) & (~BITS_RXCMD_PRD))
+#define BIT_GET_RXCMD_PRD(x) (((x) >> BIT_SHIFT_RXCMD_PRD) & BIT_MASK_RXCMD_PRD)
+#define BIT_SET_RXCMD_PRD(x, v) (BIT_CLEAR_RXCMD_PRD(x) | BIT_RXCMD_PRD(v))
-#define BIT_SHIFT_WMAC_ANTSEL_SEL 21
-#define BIT_MASK_WMAC_ANTSEL_SEL 0x3
-#define BIT_WMAC_ANTSEL_SEL(x) (((x) & BIT_MASK_WMAC_ANTSEL_SEL) << BIT_SHIFT_WMAC_ANTSEL_SEL)
-#define BIT_GET_WMAC_ANTSEL_SEL(x) (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL) & BIT_MASK_WMAC_ANTSEL_SEL)
+/* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */
+#define BIT_SHIFT_WMAC_RESP_MFB 25
+#define BIT_MASK_WMAC_RESP_MFB 0x7f
+#define BIT_WMAC_RESP_MFB(x) \
+ (((x) & BIT_MASK_WMAC_RESP_MFB) << BIT_SHIFT_WMAC_RESP_MFB)
+#define BITS_WMAC_RESP_MFB (BIT_MASK_WMAC_RESP_MFB << BIT_SHIFT_WMAC_RESP_MFB)
+#define BIT_CLEAR_WMAC_RESP_MFB(x) ((x) & (~BITS_WMAC_RESP_MFB))
+#define BIT_GET_WMAC_RESP_MFB(x) \
+ (((x) >> BIT_SHIFT_WMAC_RESP_MFB) & BIT_MASK_WMAC_RESP_MFB)
+#define BIT_SET_WMAC_RESP_MFB(x, v) \
+ (BIT_CLEAR_WMAC_RESP_MFB(x) | BIT_WMAC_RESP_MFB(v))
+
+#define BIT_SHIFT_WMAC_ANTINF_SEL 23
+#define BIT_MASK_WMAC_ANTINF_SEL 0x3
+#define BIT_WMAC_ANTINF_SEL(x) \
+ (((x) & BIT_MASK_WMAC_ANTINF_SEL) << BIT_SHIFT_WMAC_ANTINF_SEL)
+#define BITS_WMAC_ANTINF_SEL \
+ (BIT_MASK_WMAC_ANTINF_SEL << BIT_SHIFT_WMAC_ANTINF_SEL)
+#define BIT_CLEAR_WMAC_ANTINF_SEL(x) ((x) & (~BITS_WMAC_ANTINF_SEL))
+#define BIT_GET_WMAC_ANTINF_SEL(x) \
+ (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL) & BIT_MASK_WMAC_ANTINF_SEL)
+#define BIT_SET_WMAC_ANTINF_SEL(x, v) \
+ (BIT_CLEAR_WMAC_ANTINF_SEL(x) | BIT_WMAC_ANTINF_SEL(v))
+
+#define BIT_SHIFT_WMAC_ANTSEL_SEL 21
+#define BIT_MASK_WMAC_ANTSEL_SEL 0x3
+#define BIT_WMAC_ANTSEL_SEL(x) \
+ (((x) & BIT_MASK_WMAC_ANTSEL_SEL) << BIT_SHIFT_WMAC_ANTSEL_SEL)
+#define BITS_WMAC_ANTSEL_SEL \
+ (BIT_MASK_WMAC_ANTSEL_SEL << BIT_SHIFT_WMAC_ANTSEL_SEL)
+#define BIT_CLEAR_WMAC_ANTSEL_SEL(x) ((x) & (~BITS_WMAC_ANTSEL_SEL))
+#define BIT_GET_WMAC_ANTSEL_SEL(x) \
+ (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL) & BIT_MASK_WMAC_ANTSEL_SEL)
+#define BIT_SET_WMAC_ANTSEL_SEL(x, v) \
+ (BIT_CLEAR_WMAC_ANTSEL_SEL(x) | BIT_WMAC_ANTSEL_SEL(v))
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */
+#define BIT_SHIFT_RESP_TXPOWER 18
+#define BIT_MASK_RESP_TXPOWER 0x7
+#define BIT_RESP_TXPOWER(x) \
+ (((x) & BIT_MASK_RESP_TXPOWER) << BIT_SHIFT_RESP_TXPOWER)
+#define BITS_RESP_TXPOWER (BIT_MASK_RESP_TXPOWER << BIT_SHIFT_RESP_TXPOWER)
+#define BIT_CLEAR_RESP_TXPOWER(x) ((x) & (~BITS_RESP_TXPOWER))
+#define BIT_GET_RESP_TXPOWER(x) \
+ (((x) >> BIT_SHIFT_RESP_TXPOWER) & BIT_MASK_RESP_TXPOWER)
+#define BIT_SET_RESP_TXPOWER(x, v) \
+ (BIT_CLEAR_RESP_TXPOWER(x) | BIT_RESP_TXPOWER(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_RESP_TXPOWER 18
-#define BIT_MASK_RESP_TXPOWER 0x7
-#define BIT_RESP_TXPOWER(x) (((x) & BIT_MASK_RESP_TXPOWER) << BIT_SHIFT_RESP_TXPOWER)
-#define BIT_GET_RESP_TXPOWER(x) (((x) >> BIT_SHIFT_RESP_TXPOWER) & BIT_MASK_RESP_TXPOWER)
+/* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */
+#define BIT_SHIFT_R_WMAC_RESP_TXPOWER 18
+#define BIT_MASK_R_WMAC_RESP_TXPOWER 0x7
+#define BIT_R_WMAC_RESP_TXPOWER(x) \
+ (((x) & BIT_MASK_R_WMAC_RESP_TXPOWER) << BIT_SHIFT_R_WMAC_RESP_TXPOWER)
+#define BITS_R_WMAC_RESP_TXPOWER \
+ (BIT_MASK_R_WMAC_RESP_TXPOWER << BIT_SHIFT_R_WMAC_RESP_TXPOWER)
+#define BIT_CLEAR_R_WMAC_RESP_TXPOWER(x) ((x) & (~BITS_R_WMAC_RESP_TXPOWER))
+#define BIT_GET_R_WMAC_RESP_TXPOWER(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER) & BIT_MASK_R_WMAC_RESP_TXPOWER)
+#define BIT_SET_R_WMAC_RESP_TXPOWER(x, v) \
+ (BIT_CLEAR_R_WMAC_RESP_TXPOWER(x) | BIT_R_WMAC_RESP_TXPOWER(v))
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */
+
+#define BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE 18
+#define BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE 0x3
+#define BIT_WMAC_RESP_TXPOWER_OFFSET_TYPE(x) \
+ (((x) & BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE) \
+ << BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE)
+#define BITS_WMAC_RESP_TXPOWER_OFFSET_TYPE \
+ (BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE \
+ << BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE)
+#define BIT_CLEAR_WMAC_RESP_TXPOWER_OFFSET_TYPE(x) \
+ ((x) & (~BITS_WMAC_RESP_TXPOWER_OFFSET_TYPE))
+#define BIT_GET_WMAC_RESP_TXPOWER_OFFSET_TYPE(x) \
+ (((x) >> BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE) & \
+ BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE)
+#define BIT_SET_WMAC_RESP_TXPOWER_OFFSET_TYPE(x, v) \
+ (BIT_CLEAR_WMAC_RESP_TXPOWER_OFFSET_TYPE(x) | \
+ BIT_WMAC_RESP_TXPOWER_OFFSET_TYPE(v))
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */
+#define BIT_SHIFT_RESP_TXAGC_B 13
+#define BIT_MASK_RESP_TXAGC_B 0x1f
+#define BIT_RESP_TXAGC_B(x) \
+ (((x) & BIT_MASK_RESP_TXAGC_B) << BIT_SHIFT_RESP_TXAGC_B)
+#define BITS_RESP_TXAGC_B (BIT_MASK_RESP_TXAGC_B << BIT_SHIFT_RESP_TXAGC_B)
+#define BIT_CLEAR_RESP_TXAGC_B(x) ((x) & (~BITS_RESP_TXAGC_B))
+#define BIT_GET_RESP_TXAGC_B(x) \
+ (((x) >> BIT_SHIFT_RESP_TXAGC_B) & BIT_MASK_RESP_TXAGC_B)
+#define BIT_SET_RESP_TXAGC_B(x, v) \
+ (BIT_CLEAR_RESP_TXAGC_B(x) | BIT_RESP_TXAGC_B(v))
-#define BIT_SHIFT_R_WMAC_RESP_TXPOWER 18
-#define BIT_MASK_R_WMAC_RESP_TXPOWER 0x7
-#define BIT_R_WMAC_RESP_TXPOWER(x) (((x) & BIT_MASK_R_WMAC_RESP_TXPOWER) << BIT_SHIFT_R_WMAC_RESP_TXPOWER)
-#define BIT_GET_R_WMAC_RESP_TXPOWER(x) (((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER) & BIT_MASK_R_WMAC_RESP_TXPOWER)
+#define BIT_SHIFT_RESP_TXAGC_A 8
+#define BIT_MASK_RESP_TXAGC_A 0x1f
+#define BIT_RESP_TXAGC_A(x) \
+ (((x) & BIT_MASK_RESP_TXAGC_A) << BIT_SHIFT_RESP_TXAGC_A)
+#define BITS_RESP_TXAGC_A (BIT_MASK_RESP_TXAGC_A << BIT_SHIFT_RESP_TXAGC_A)
+#define BIT_CLEAR_RESP_TXAGC_A(x) ((x) & (~BITS_RESP_TXAGC_A))
+#define BIT_GET_RESP_TXAGC_A(x) \
+ (((x) >> BIT_SHIFT_RESP_TXAGC_A) & BIT_MASK_RESP_TXAGC_A)
+#define BIT_SET_RESP_TXAGC_A(x, v) \
+ (BIT_CLEAR_RESP_TXAGC_A(x) | BIT_RESP_TXAGC_A(v))
+#define BIT_RESP_ANTSEL_B BIT(7)
+#define BIT_RESP_ANTSEL_A BIT(6)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */
+
+#define BIT_SHIFT_WMAC_RESP_TXANT_V1 6
+#define BIT_MASK_WMAC_RESP_TXANT_V1 0xfff
+#define BIT_WMAC_RESP_TXANT_V1(x) \
+ (((x) & BIT_MASK_WMAC_RESP_TXANT_V1) << BIT_SHIFT_WMAC_RESP_TXANT_V1)
+#define BITS_WMAC_RESP_TXANT_V1 \
+ (BIT_MASK_WMAC_RESP_TXANT_V1 << BIT_SHIFT_WMAC_RESP_TXANT_V1)
+#define BIT_CLEAR_WMAC_RESP_TXANT_V1(x) ((x) & (~BITS_WMAC_RESP_TXANT_V1))
+#define BIT_GET_WMAC_RESP_TXANT_V1(x) \
+ (((x) >> BIT_SHIFT_WMAC_RESP_TXANT_V1) & BIT_MASK_WMAC_RESP_TXANT_V1)
+#define BIT_SET_WMAC_RESP_TXANT_V1(x, v) \
+ (BIT_CLEAR_WMAC_RESP_TXANT_V1(x) | BIT_WMAC_RESP_TXANT_V1(v))
+
+#endif
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */
+
+#define BIT_SHIFT_RESP_TXANT_CCK 4
+#define BIT_MASK_RESP_TXANT_CCK 0x3
+#define BIT_RESP_TXANT_CCK(x) \
+ (((x) & BIT_MASK_RESP_TXANT_CCK) << BIT_SHIFT_RESP_TXANT_CCK)
+#define BITS_RESP_TXANT_CCK \
+ (BIT_MASK_RESP_TXANT_CCK << BIT_SHIFT_RESP_TXANT_CCK)
+#define BIT_CLEAR_RESP_TXANT_CCK(x) ((x) & (~BITS_RESP_TXANT_CCK))
+#define BIT_GET_RESP_TXANT_CCK(x) \
+ (((x) >> BIT_SHIFT_RESP_TXANT_CCK) & BIT_MASK_RESP_TXANT_CCK)
+#define BIT_SET_RESP_TXANT_CCK(x, v) \
+ (BIT_CLEAR_RESP_TXANT_CCK(x) | BIT_RESP_TXANT_CCK(v))
+
+#define BIT_SHIFT_RESP_TXANT_L 2
+#define BIT_MASK_RESP_TXANT_L 0x3
+#define BIT_RESP_TXANT_L(x) \
+ (((x) & BIT_MASK_RESP_TXANT_L) << BIT_SHIFT_RESP_TXANT_L)
+#define BITS_RESP_TXANT_L (BIT_MASK_RESP_TXANT_L << BIT_SHIFT_RESP_TXANT_L)
+#define BIT_CLEAR_RESP_TXANT_L(x) ((x) & (~BITS_RESP_TXANT_L))
+#define BIT_GET_RESP_TXANT_L(x) \
+ (((x) >> BIT_SHIFT_RESP_TXANT_L) & BIT_MASK_RESP_TXANT_L)
+#define BIT_SET_RESP_TXANT_L(x, v) \
+ (BIT_CLEAR_RESP_TXANT_L(x) | BIT_RESP_TXANT_L(v))
+
+#define BIT_SHIFT_RESP_TXANT_HT 0
+#define BIT_MASK_RESP_TXANT_HT 0x3
+#define BIT_RESP_TXANT_HT(x) \
+ (((x) & BIT_MASK_RESP_TXANT_HT) << BIT_SHIFT_RESP_TXANT_HT)
+#define BITS_RESP_TXANT_HT (BIT_MASK_RESP_TXANT_HT << BIT_SHIFT_RESP_TXANT_HT)
+#define BIT_CLEAR_RESP_TXANT_HT(x) ((x) & (~BITS_RESP_TXANT_HT))
+#define BIT_GET_RESP_TXANT_HT(x) \
+ (((x) >> BIT_SHIFT_RESP_TXANT_HT) & BIT_MASK_RESP_TXANT_HT)
+#define BIT_SET_RESP_TXANT_HT(x, v) \
+ (BIT_CLEAR_RESP_TXANT_HT(x) | BIT_RESP_TXANT_HT(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
/* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */
+#define BIT_SHIFT_WMAC_RESP_TXANT 0
+#define BIT_MASK_WMAC_RESP_TXANT 0x3ffff
+#define BIT_WMAC_RESP_TXANT(x) \
+ (((x) & BIT_MASK_WMAC_RESP_TXANT) << BIT_SHIFT_WMAC_RESP_TXANT)
+#define BITS_WMAC_RESP_TXANT \
+ (BIT_MASK_WMAC_RESP_TXANT << BIT_SHIFT_WMAC_RESP_TXANT)
+#define BIT_CLEAR_WMAC_RESP_TXANT(x) ((x) & (~BITS_WMAC_RESP_TXANT))
+#define BIT_GET_WMAC_RESP_TXANT(x) \
+ (((x) >> BIT_SHIFT_WMAC_RESP_TXANT) & BIT_MASK_WMAC_RESP_TXANT)
+#define BIT_SET_WMAC_RESP_TXANT(x, v) \
+ (BIT_CLEAR_WMAC_RESP_TXANT(x) | BIT_WMAC_RESP_TXANT(v))
-#define BIT_SHIFT_RESP_TXAGC_B 13
-#define BIT_MASK_RESP_TXAGC_B 0x1f
-#define BIT_RESP_TXAGC_B(x) (((x) & BIT_MASK_RESP_TXAGC_B) << BIT_SHIFT_RESP_TXAGC_B)
-#define BIT_GET_RESP_TXAGC_B(x) (((x) >> BIT_SHIFT_RESP_TXAGC_B) & BIT_MASK_RESP_TXAGC_B)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_RESP_TXAGC_A 8
-#define BIT_MASK_RESP_TXAGC_A 0x1f
-#define BIT_RESP_TXAGC_A(x) (((x) & BIT_MASK_RESP_TXAGC_A) << BIT_SHIFT_RESP_TXAGC_A)
-#define BIT_GET_RESP_TXAGC_A(x) (((x) >> BIT_SHIFT_RESP_TXAGC_A) & BIT_MASK_RESP_TXAGC_A)
+/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */
-#define BIT_RESP_ANTSEL_B BIT(7)
-#define BIT_RESP_ANTSEL_A BIT(6)
+#define BIT_CTL_IDLE_CLR_CSI_RPT BIT(31)
-#define BIT_SHIFT_RESP_TXANT_CCK 4
-#define BIT_MASK_RESP_TXANT_CCK 0x3
-#define BIT_RESP_TXANT_CCK(x) (((x) & BIT_MASK_RESP_TXANT_CCK) << BIT_SHIFT_RESP_TXANT_CCK)
-#define BIT_GET_RESP_TXANT_CCK(x) (((x) >> BIT_SHIFT_RESP_TXANT_CCK) & BIT_MASK_RESP_TXANT_CCK)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_RESP_TXANT_L 2
-#define BIT_MASK_RESP_TXANT_L 0x3
-#define BIT_RESP_TXANT_L(x) (((x) & BIT_MASK_RESP_TXANT_L) << BIT_SHIFT_RESP_TXANT_L)
-#define BIT_GET_RESP_TXANT_L(x) (((x) >> BIT_SHIFT_RESP_TXANT_L) & BIT_MASK_RESP_TXANT_L)
+/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */
+#define BIT_WMAC_USE_NDPARATE BIT(30)
-#define BIT_SHIFT_RESP_TXANT_HT 0
-#define BIT_MASK_RESP_TXANT_HT 0x3
-#define BIT_RESP_TXANT_HT(x) (((x) & BIT_MASK_RESP_TXANT_HT) << BIT_SHIFT_RESP_TXANT_HT)
-#define BIT_GET_RESP_TXANT_HT(x) (((x) >> BIT_SHIFT_RESP_TXANT_HT) & BIT_MASK_RESP_TXANT_HT)
+#define BIT_SHIFT_WMAC_CSI_RATE 24
+#define BIT_MASK_WMAC_CSI_RATE 0x3f
+#define BIT_WMAC_CSI_RATE(x) \
+ (((x) & BIT_MASK_WMAC_CSI_RATE) << BIT_SHIFT_WMAC_CSI_RATE)
+#define BITS_WMAC_CSI_RATE (BIT_MASK_WMAC_CSI_RATE << BIT_SHIFT_WMAC_CSI_RATE)
+#define BIT_CLEAR_WMAC_CSI_RATE(x) ((x) & (~BITS_WMAC_CSI_RATE))
+#define BIT_GET_WMAC_CSI_RATE(x) \
+ (((x) >> BIT_SHIFT_WMAC_CSI_RATE) & BIT_MASK_WMAC_CSI_RATE)
+#define BIT_SET_WMAC_CSI_RATE(x, v) \
+ (BIT_CLEAR_WMAC_CSI_RATE(x) | BIT_WMAC_CSI_RATE(v))
+#define BIT_SHIFT_WMAC_RESP_TXRATE 16
+#define BIT_MASK_WMAC_RESP_TXRATE 0xff
+#define BIT_WMAC_RESP_TXRATE(x) \
+ (((x) & BIT_MASK_WMAC_RESP_TXRATE) << BIT_SHIFT_WMAC_RESP_TXRATE)
+#define BITS_WMAC_RESP_TXRATE \
+ (BIT_MASK_WMAC_RESP_TXRATE << BIT_SHIFT_WMAC_RESP_TXRATE)
+#define BIT_CLEAR_WMAC_RESP_TXRATE(x) ((x) & (~BITS_WMAC_RESP_TXRATE))
+#define BIT_GET_WMAC_RESP_TXRATE(x) \
+ (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE) & BIT_MASK_WMAC_RESP_TXRATE)
+#define BIT_SET_WMAC_RESP_TXRATE(x, v) \
+ (BIT_CLEAR_WMAC_RESP_TXRATE(x) | BIT_WMAC_RESP_TXRATE(v))
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */
+#define BIT_WMAC_CSI_RATE_FORCE_EN BIT(15)
-/* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT)
-#define BIT_SHIFT_WMAC_RESP_TXANT 0
-#define BIT_MASK_WMAC_RESP_TXANT 0x3ffff
-#define BIT_WMAC_RESP_TXANT(x) (((x) & BIT_MASK_WMAC_RESP_TXANT) << BIT_SHIFT_WMAC_RESP_TXANT)
-#define BIT_GET_WMAC_RESP_TXANT(x) (((x) >> BIT_SHIFT_WMAC_RESP_TXANT) & BIT_MASK_WMAC_RESP_TXANT)
+/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */
+#define BIT_CSI_FORCE_RATE_EN BIT(15)
#endif
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */
+
+#define BIT_SHIFT_WMAC_CSI_RSC_FORCE 13
+#define BIT_MASK_WMAC_CSI_RSC_FORCE 0x3
+#define BIT_WMAC_CSI_RSC_FORCE(x) \
+ (((x) & BIT_MASK_WMAC_CSI_RSC_FORCE) << BIT_SHIFT_WMAC_CSI_RSC_FORCE)
+#define BITS_WMAC_CSI_RSC_FORCE \
+ (BIT_MASK_WMAC_CSI_RSC_FORCE << BIT_SHIFT_WMAC_CSI_RSC_FORCE)
+#define BIT_CLEAR_WMAC_CSI_RSC_FORCE(x) ((x) & (~BITS_WMAC_CSI_RSC_FORCE))
+#define BIT_GET_WMAC_CSI_RSC_FORCE(x) \
+ (((x) >> BIT_SHIFT_WMAC_CSI_RSC_FORCE) & BIT_MASK_WMAC_CSI_RSC_FORCE)
+#define BIT_SET_WMAC_CSI_RSC_FORCE(x, v) \
+ (BIT_CLEAR_WMAC_CSI_RSC_FORCE(x) | BIT_WMAC_CSI_RSC_FORCE(v))
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */
-#define BIT_CTL_IDLE_CLR_CSI_RPT BIT(31)
+#define BIT_SHIFT_CSI_RSC 13
+#define BIT_MASK_CSI_RSC 0x3
+#define BIT_CSI_RSC(x) (((x) & BIT_MASK_CSI_RSC) << BIT_SHIFT_CSI_RSC)
+#define BITS_CSI_RSC (BIT_MASK_CSI_RSC << BIT_SHIFT_CSI_RSC)
+#define BIT_CLEAR_CSI_RSC(x) ((x) & (~BITS_CSI_RSC))
+#define BIT_GET_CSI_RSC(x) (((x) >> BIT_SHIFT_CSI_RSC) & BIT_MASK_CSI_RSC)
+#define BIT_SET_CSI_RSC(x, v) (BIT_CLEAR_CSI_RSC(x) | BIT_CSI_RSC(v))
#endif
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */
+
+#define BIT_WMAC_CSI_GID_SEL BIT(12)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */
-#define BIT_WMAC_USE_NDPARATE BIT(30)
+#define BIT_CSI_GID_SEL BIT(12)
-#define BIT_SHIFT_WMAC_CSI_RATE 24
-#define BIT_MASK_WMAC_CSI_RATE 0x3f
-#define BIT_WMAC_CSI_RATE(x) (((x) & BIT_MASK_WMAC_CSI_RATE) << BIT_SHIFT_WMAC_CSI_RATE)
-#define BIT_GET_WMAC_CSI_RATE(x) (((x) >> BIT_SHIFT_WMAC_CSI_RATE) & BIT_MASK_WMAC_CSI_RATE)
+#endif
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT)
-#define BIT_SHIFT_WMAC_RESP_TXRATE 16
-#define BIT_MASK_WMAC_RESP_TXRATE 0xff
-#define BIT_WMAC_RESP_TXRATE(x) (((x) & BIT_MASK_WMAC_RESP_TXRATE) << BIT_SHIFT_WMAC_RESP_TXRATE)
-#define BIT_GET_WMAC_RESP_TXRATE(x) (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE) & BIT_MASK_WMAC_RESP_TXRATE)
+/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */
+#define BIT_RDCSIMD_FLAG_TRIG_SEL BIT(11)
+#define BIT_NDPVLD_POS_RST_FFPTR_DIS_V1 BIT(10)
#endif
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */
+
+#define BIT_NDPVLD_PROTECT_RDRDY_DIS BIT(9)
+
+#endif
+#if (HALMAC_8198F_SUPPORT)
/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */
-#define BIT_BBPSF_MPDUCHKEN BIT(5)
+#define BIT_CSIRD_EMPTY_APPZERO BIT(8)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */
+#define BIT_RDCSI_EMPTY_APPZERO BIT(8)
-/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */
+#endif
-#define BIT_BBPSF_MHCHKEN BIT(4)
-#define BIT_BBPSF_ERRCHKEN BIT(3)
+#if (HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_BBPSF_ERRTHR 0
-#define BIT_MASK_BBPSF_ERRTHR 0x7
-#define BIT_BBPSF_ERRTHR(x) (((x) & BIT_MASK_BBPSF_ERRTHR) << BIT_SHIFT_BBPSF_ERRTHR)
-#define BIT_GET_BBPSF_ERRTHR(x) (((x) >> BIT_SHIFT_BBPSF_ERRTHR) & BIT_MASK_BBPSF_ERRTHR)
+/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */
+#define BIT_WMC_CSI_RATE_FB_EN BIT(7)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */
+#define BIT_CSI_RATE_FB_EN BIT(7)
-/* 2 REG_P2P_RX_BCN_NOA (Offset 0x06E0) */
+#endif
-#define BIT_NOA_PARSER_EN BIT(15)
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */
+#define BIT_RXFIFO_WRPTR_WO_CHKSUM BIT(6)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
-/* 2 REG_P2P_RX_BCN_NOA (Offset 0x06E0) */
+/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */
-#define BIT_BSSID_SEL BIT(14)
+#define BIT_BBPSF_MPDUCHKEN BIT(5)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_BBPSF_CTRL (Offset 0x06DC) */
+
+#define BIT_BBPSF_MHCHKEN BIT(4)
+#define BIT_BBPSF_ERRCHKEN BIT(3)
+
+#define BIT_SHIFT_BBPSF_ERRTHR 0
+#define BIT_MASK_BBPSF_ERRTHR 0x7
+#define BIT_BBPSF_ERRTHR(x) \
+ (((x) & BIT_MASK_BBPSF_ERRTHR) << BIT_SHIFT_BBPSF_ERRTHR)
+#define BITS_BBPSF_ERRTHR (BIT_MASK_BBPSF_ERRTHR << BIT_SHIFT_BBPSF_ERRTHR)
+#define BIT_CLEAR_BBPSF_ERRTHR(x) ((x) & (~BITS_BBPSF_ERRTHR))
+#define BIT_GET_BBPSF_ERRTHR(x) \
+ (((x) >> BIT_SHIFT_BBPSF_ERRTHR) & BIT_MASK_BBPSF_ERRTHR)
+#define BIT_SET_BBPSF_ERRTHR(x, v) \
+ (BIT_CLEAR_BBPSF_ERRTHR(x) | BIT_BBPSF_ERRTHR(v))
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_P2P_RX_BCN_NOA (Offset 0x06E0) */
+#define BIT_NOA_PARSER_EN BIT(15)
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_BSSID_SEL 12
-#define BIT_MASK_BSSID_SEL 0x7
-#define BIT_BSSID_SEL(x) (((x) & BIT_MASK_BSSID_SEL) << BIT_SHIFT_BSSID_SEL)
-#define BIT_GET_BSSID_SEL(x) (((x) >> BIT_SHIFT_BSSID_SEL) & BIT_MASK_BSSID_SEL)
+/* 2 REG_P2P_RX_BCN_NOA (Offset 0x06E0) */
+#define BIT_BSSID_SEL BIT(14)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_P2P_RX_BCN_NOA (Offset 0x06E0) */
+
+#define BIT_SHIFT_BSSID_SEL_V1 12
+#define BIT_MASK_BSSID_SEL_V1 0x7
+#define BIT_BSSID_SEL_V1(x) \
+ (((x) & BIT_MASK_BSSID_SEL_V1) << BIT_SHIFT_BSSID_SEL_V1)
+#define BITS_BSSID_SEL_V1 (BIT_MASK_BSSID_SEL_V1 << BIT_SHIFT_BSSID_SEL_V1)
+#define BIT_CLEAR_BSSID_SEL_V1(x) ((x) & (~BITS_BSSID_SEL_V1))
+#define BIT_GET_BSSID_SEL_V1(x) \
+ (((x) >> BIT_SHIFT_BSSID_SEL_V1) & BIT_MASK_BSSID_SEL_V1)
+#define BIT_SET_BSSID_SEL_V1(x, v) \
+ (BIT_CLEAR_BSSID_SEL_V1(x) | BIT_BSSID_SEL_V1(v))
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_P2P_RX_BCN_NOA (Offset 0x06E0) */
+#define BIT_SHIFT_P2P_OUI_TYPE 0
+#define BIT_MASK_P2P_OUI_TYPE 0xff
+#define BIT_P2P_OUI_TYPE(x) \
+ (((x) & BIT_MASK_P2P_OUI_TYPE) << BIT_SHIFT_P2P_OUI_TYPE)
+#define BITS_P2P_OUI_TYPE (BIT_MASK_P2P_OUI_TYPE << BIT_SHIFT_P2P_OUI_TYPE)
+#define BIT_CLEAR_P2P_OUI_TYPE(x) ((x) & (~BITS_P2P_OUI_TYPE))
+#define BIT_GET_P2P_OUI_TYPE(x) \
+ (((x) >> BIT_SHIFT_P2P_OUI_TYPE) & BIT_MASK_P2P_OUI_TYPE)
+#define BIT_SET_P2P_OUI_TYPE(x, v) \
+ (BIT_CLEAR_P2P_OUI_TYPE(x) | BIT_P2P_OUI_TYPE(v))
-#define BIT_SHIFT_P2P_OUI_TYPE 0
-#define BIT_MASK_P2P_OUI_TYPE 0xff
-#define BIT_P2P_OUI_TYPE(x) (((x) & BIT_MASK_P2P_OUI_TYPE) << BIT_SHIFT_P2P_OUI_TYPE)
-#define BIT_GET_P2P_OUI_TYPE(x) (((x) >> BIT_SHIFT_P2P_OUI_TYPE) & BIT_MASK_P2P_OUI_TYPE)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_ASSOCIATED_BFMER0_INFO (Offset 0x06E4) */
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0 0xffffffffffffL
+#define BIT_R_WMAC_SOUNDING_RXADD_R0(x) \
+ (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0) \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0)
+#define BITS_R_WMAC_SOUNDING_RXADD_R0 \
+ (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0 \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0(x) \
+ ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0) & \
+ BIT_MASK_R_WMAC_SOUNDING_RXADD_R0)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0(x, v) \
+ (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0(x) | \
+ BIT_R_WMAC_SOUNDING_RXADD_R0(v))
-#define BIT_SHIFT_R_WMAC_TXCSI_AID0 (48 & CPU_OPT_WIDTH)
-#define BIT_MASK_R_WMAC_TXCSI_AID0 0x1ff
-#define BIT_R_WMAC_TXCSI_AID0(x) (((x) & BIT_MASK_R_WMAC_TXCSI_AID0) << BIT_SHIFT_R_WMAC_TXCSI_AID0)
-#define BIT_GET_R_WMAC_TXCSI_AID0(x) (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0) & BIT_MASK_R_WMAC_TXCSI_AID0)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0 0
-#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0 0xffffffffffffL
-#define BIT_R_WMAC_SOUNDING_RXADD_R0(x) (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0)
-#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0(x) (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0)
+/* 2 REG_ASSOCIATED_BFMER0_INFO (Offset 0x06E4) */
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1 0xffffffffL
+#define BIT_R_WMAC_SOUNDING_RXADD_R0_V1(x) \
+ (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1) \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1)
+#define BITS_R_WMAC_SOUNDING_RXADD_R0_V1 \
+ (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1 \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1(x) \
+ ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_V1))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_V1(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1) & \
+ BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_V1(x, v) \
+ (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1(x) | \
+ BIT_R_WMAC_SOUNDING_RXADD_R0_V1(v))
+
+/* 2 REG_ASSOCIATED_BFMER0_INFO_H (Offset 0x06E8) */
+
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1 0xffff
+#define BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1(x) \
+ (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1) \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1)
+#define BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1 \
+ (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1 \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1(x) \
+ ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_H_V1(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1) & \
+ BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_H_V1(x, v) \
+ (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1(x) | \
+ BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_ASSOCIATED_BFMER1_INFO (Offset 0x06EC) */
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1 0xffffffffffffL
+#define BIT_R_WMAC_SOUNDING_RXADD_R1(x) \
+ (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1) \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1)
+#define BITS_R_WMAC_SOUNDING_RXADD_R1 \
+ (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1 \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1(x) \
+ ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1) & \
+ BIT_MASK_R_WMAC_SOUNDING_RXADD_R1)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1(x, v) \
+ (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1(x) | \
+ BIT_R_WMAC_SOUNDING_RXADD_R1(v))
-#define BIT_SHIFT_R_WMAC_TXCSI_AID1 (48 & CPU_OPT_WIDTH)
-#define BIT_MASK_R_WMAC_TXCSI_AID1 0x1ff
-#define BIT_R_WMAC_TXCSI_AID1(x) (((x) & BIT_MASK_R_WMAC_TXCSI_AID1) << BIT_SHIFT_R_WMAC_TXCSI_AID1)
-#define BIT_GET_R_WMAC_TXCSI_AID1(x) (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1) & BIT_MASK_R_WMAC_TXCSI_AID1)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1 0
-#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1 0xffffffffffffL
-#define BIT_R_WMAC_SOUNDING_RXADD_R1(x) (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1)
-#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1(x) (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1)
+/* 2 REG_ASSOCIATED_BFMER1_INFO (Offset 0x06EC) */
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1 0xffffffffL
+#define BIT_R_WMAC_SOUNDING_RXADD_R1_V1(x) \
+ (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1) \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1)
+#define BITS_R_WMAC_SOUNDING_RXADD_R1_V1 \
+ (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1 \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1(x) \
+ ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_V1))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_V1(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1) & \
+ BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_V1(x, v) \
+ (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1(x) | \
+ BIT_R_WMAC_SOUNDING_RXADD_R1_V1(v))
+
+/* 2 REG_ASSOCIATED_BFMER1_INFO_H (Offset 0x06F0) */
+
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1 0xffff
+#define BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1(x) \
+ (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1) \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1)
+#define BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1 \
+ (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1 \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1(x) \
+ ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_H_V1(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1) & \
+ BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_H_V1(x, v) \
+ (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1(x) | \
+ BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
/* 2 REG_TX_CSI_RPT_PARAM_BW20 (Offset 0x06F4) */
+#define BIT_SHIFT_R_WMAC_BFINFO_20M_1 16
+#define BIT_MASK_R_WMAC_BFINFO_20M_1 0xfff
+#define BIT_R_WMAC_BFINFO_20M_1(x) \
+ (((x) & BIT_MASK_R_WMAC_BFINFO_20M_1) << BIT_SHIFT_R_WMAC_BFINFO_20M_1)
+#define BITS_R_WMAC_BFINFO_20M_1 \
+ (BIT_MASK_R_WMAC_BFINFO_20M_1 << BIT_SHIFT_R_WMAC_BFINFO_20M_1)
+#define BIT_CLEAR_R_WMAC_BFINFO_20M_1(x) ((x) & (~BITS_R_WMAC_BFINFO_20M_1))
+#define BIT_GET_R_WMAC_BFINFO_20M_1(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1) & BIT_MASK_R_WMAC_BFINFO_20M_1)
+#define BIT_SET_R_WMAC_BFINFO_20M_1(x, v) \
+ (BIT_CLEAR_R_WMAC_BFINFO_20M_1(x) | BIT_R_WMAC_BFINFO_20M_1(v))
+
+#define BIT_SHIFT_R_WMAC_BFINFO_20M_0 0
+#define BIT_MASK_R_WMAC_BFINFO_20M_0 0xfff
+#define BIT_R_WMAC_BFINFO_20M_0(x) \
+ (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0) << BIT_SHIFT_R_WMAC_BFINFO_20M_0)
+#define BITS_R_WMAC_BFINFO_20M_0 \
+ (BIT_MASK_R_WMAC_BFINFO_20M_0 << BIT_SHIFT_R_WMAC_BFINFO_20M_0)
+#define BIT_CLEAR_R_WMAC_BFINFO_20M_0(x) ((x) & (~BITS_R_WMAC_BFINFO_20M_0))
+#define BIT_GET_R_WMAC_BFINFO_20M_0(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0) & BIT_MASK_R_WMAC_BFINFO_20M_0)
+#define BIT_SET_R_WMAC_BFINFO_20M_0(x, v) \
+ (BIT_CLEAR_R_WMAC_BFINFO_20M_0(x) | BIT_R_WMAC_BFINFO_20M_0(v))
-#define BIT_SHIFT_R_WMAC_BFINFO_20M_1 16
-#define BIT_MASK_R_WMAC_BFINFO_20M_1 0xfff
-#define BIT_R_WMAC_BFINFO_20M_1(x) (((x) & BIT_MASK_R_WMAC_BFINFO_20M_1) << BIT_SHIFT_R_WMAC_BFINFO_20M_1)
-#define BIT_GET_R_WMAC_BFINFO_20M_1(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1) & BIT_MASK_R_WMAC_BFINFO_20M_1)
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_R_WMAC_BFINFO_20M_0 0
-#define BIT_MASK_R_WMAC_BFINFO_20M_0 0xfff
-#define BIT_R_WMAC_BFINFO_20M_0(x) (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0) << BIT_SHIFT_R_WMAC_BFINFO_20M_0)
-#define BIT_GET_R_WMAC_BFINFO_20M_0(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0) & BIT_MASK_R_WMAC_BFINFO_20M_0)
+/* 2 REG_TX_CSI_RPT_PARAM_BW40 (Offset 0x06F8) */
+#define BIT_SHIFT_R_WMAC_BFINFO_40M_1 13
+#define BIT_MASK_R_WMAC_BFINFO_40M_1 0x7fff
+#define BIT_R_WMAC_BFINFO_40M_1(x) \
+ (((x) & BIT_MASK_R_WMAC_BFINFO_40M_1) << BIT_SHIFT_R_WMAC_BFINFO_40M_1)
+#define BITS_R_WMAC_BFINFO_40M_1 \
+ (BIT_MASK_R_WMAC_BFINFO_40M_1 << BIT_SHIFT_R_WMAC_BFINFO_40M_1)
+#define BIT_CLEAR_R_WMAC_BFINFO_40M_1(x) ((x) & (~BITS_R_WMAC_BFINFO_40M_1))
+#define BIT_GET_R_WMAC_BFINFO_40M_1(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_BFINFO_40M_1) & BIT_MASK_R_WMAC_BFINFO_40M_1)
+#define BIT_SET_R_WMAC_BFINFO_40M_1(x, v) \
+ (BIT_CLEAR_R_WMAC_BFINFO_40M_1(x) | BIT_R_WMAC_BFINFO_40M_1(v))
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_TX_CSI_RPT_PARAM_BW40 (Offset 0x06F8) */
+
+#define BIT_SHIFT_WMAC_RESP_ANTD 12
+#define BIT_MASK_WMAC_RESP_ANTD 0xf
+#define BIT_WMAC_RESP_ANTD(x) \
+ (((x) & BIT_MASK_WMAC_RESP_ANTD) << BIT_SHIFT_WMAC_RESP_ANTD)
+#define BITS_WMAC_RESP_ANTD \
+ (BIT_MASK_WMAC_RESP_ANTD << BIT_SHIFT_WMAC_RESP_ANTD)
+#define BIT_CLEAR_WMAC_RESP_ANTD(x) ((x) & (~BITS_WMAC_RESP_ANTD))
+#define BIT_GET_WMAC_RESP_ANTD(x) \
+ (((x) >> BIT_SHIFT_WMAC_RESP_ANTD) & BIT_MASK_WMAC_RESP_ANTD)
+#define BIT_SET_WMAC_RESP_ANTD(x, v) \
+ (BIT_CLEAR_WMAC_RESP_ANTD(x) | BIT_WMAC_RESP_ANTD(v))
+
+#define BIT_SHIFT_WMAC_RESP_ANTC 8
+#define BIT_MASK_WMAC_RESP_ANTC 0xf
+#define BIT_WMAC_RESP_ANTC(x) \
+ (((x) & BIT_MASK_WMAC_RESP_ANTC) << BIT_SHIFT_WMAC_RESP_ANTC)
+#define BITS_WMAC_RESP_ANTC \
+ (BIT_MASK_WMAC_RESP_ANTC << BIT_SHIFT_WMAC_RESP_ANTC)
+#define BIT_CLEAR_WMAC_RESP_ANTC(x) ((x) & (~BITS_WMAC_RESP_ANTC))
+#define BIT_GET_WMAC_RESP_ANTC(x) \
+ (((x) >> BIT_SHIFT_WMAC_RESP_ANTC) & BIT_MASK_WMAC_RESP_ANTC)
+#define BIT_SET_WMAC_RESP_ANTC(x, v) \
+ (BIT_CLEAR_WMAC_RESP_ANTC(x) | BIT_WMAC_RESP_ANTC(v))
+
+#define BIT_SHIFT_WMAC_RESP_ANTB 4
+#define BIT_MASK_WMAC_RESP_ANTB 0xf
+#define BIT_WMAC_RESP_ANTB(x) \
+ (((x) & BIT_MASK_WMAC_RESP_ANTB) << BIT_SHIFT_WMAC_RESP_ANTB)
+#define BITS_WMAC_RESP_ANTB \
+ (BIT_MASK_WMAC_RESP_ANTB << BIT_SHIFT_WMAC_RESP_ANTB)
+#define BIT_CLEAR_WMAC_RESP_ANTB(x) ((x) & (~BITS_WMAC_RESP_ANTB))
+#define BIT_GET_WMAC_RESP_ANTB(x) \
+ (((x) >> BIT_SHIFT_WMAC_RESP_ANTB) & BIT_MASK_WMAC_RESP_ANTB)
+#define BIT_SET_WMAC_RESP_ANTB(x, v) \
+ (BIT_CLEAR_WMAC_RESP_ANTB(x) | BIT_WMAC_RESP_ANTB(v))
+
+#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
/* 2 REG_TX_CSI_RPT_PARAM_BW40 (Offset 0x06F8) */
+#define BIT_SHIFT_R_WMAC_BFINFO_40M_0 0
+#define BIT_MASK_R_WMAC_BFINFO_40M_0 0xfff
+#define BIT_R_WMAC_BFINFO_40M_0(x) \
+ (((x) & BIT_MASK_R_WMAC_BFINFO_40M_0) << BIT_SHIFT_R_WMAC_BFINFO_40M_0)
+#define BITS_R_WMAC_BFINFO_40M_0 \
+ (BIT_MASK_R_WMAC_BFINFO_40M_0 << BIT_SHIFT_R_WMAC_BFINFO_40M_0)
+#define BIT_CLEAR_R_WMAC_BFINFO_40M_0(x) ((x) & (~BITS_R_WMAC_BFINFO_40M_0))
+#define BIT_GET_R_WMAC_BFINFO_40M_0(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_BFINFO_40M_0) & BIT_MASK_R_WMAC_BFINFO_40M_0)
+#define BIT_SET_R_WMAC_BFINFO_40M_0(x, v) \
+ (BIT_CLEAR_R_WMAC_BFINFO_40M_0(x) | BIT_R_WMAC_BFINFO_40M_0(v))
-#define BIT_SHIFT_R_WMAC_BFINFO_40M_1 13
-#define BIT_MASK_R_WMAC_BFINFO_40M_1 0x7fff
-#define BIT_R_WMAC_BFINFO_40M_1(x) (((x) & BIT_MASK_R_WMAC_BFINFO_40M_1) << BIT_SHIFT_R_WMAC_BFINFO_40M_1)
-#define BIT_GET_R_WMAC_BFINFO_40M_1(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_40M_1) & BIT_MASK_R_WMAC_BFINFO_40M_1)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_R_WMAC_BFINFO_40M_0 0
-#define BIT_MASK_R_WMAC_BFINFO_40M_0 0xfff
-#define BIT_R_WMAC_BFINFO_40M_0(x) (((x) & BIT_MASK_R_WMAC_BFINFO_40M_0) << BIT_SHIFT_R_WMAC_BFINFO_40M_0)
-#define BIT_GET_R_WMAC_BFINFO_40M_0(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_40M_0) & BIT_MASK_R_WMAC_BFINFO_40M_0)
+/* 2 REG_TX_CSI_RPT_PARAM_BW40 (Offset 0x06F8) */
+#define BIT_SHIFT_WMAC_RESP_ANTCD 0
+#define BIT_MASK_WMAC_RESP_ANTCD 0xf
+#define BIT_WMAC_RESP_ANTCD(x) \
+ (((x) & BIT_MASK_WMAC_RESP_ANTCD) << BIT_SHIFT_WMAC_RESP_ANTCD)
+#define BITS_WMAC_RESP_ANTCD \
+ (BIT_MASK_WMAC_RESP_ANTCD << BIT_SHIFT_WMAC_RESP_ANTCD)
+#define BIT_CLEAR_WMAC_RESP_ANTCD(x) ((x) & (~BITS_WMAC_RESP_ANTCD))
+#define BIT_GET_WMAC_RESP_ANTCD(x) \
+ (((x) >> BIT_SHIFT_WMAC_RESP_ANTCD) & BIT_MASK_WMAC_RESP_ANTCD)
+#define BIT_SET_WMAC_RESP_ANTCD(x, v) \
+ (BIT_CLEAR_WMAC_RESP_ANTCD(x) | BIT_WMAC_RESP_ANTCD(v))
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_TX_CSI_RPT_PARAM_BW40 (Offset 0x06F8) */
+#define BIT_SHIFT_WMAC_RESP_ANTA 0
+#define BIT_MASK_WMAC_RESP_ANTA 0xf
+#define BIT_WMAC_RESP_ANTA(x) \
+ (((x) & BIT_MASK_WMAC_RESP_ANTA) << BIT_SHIFT_WMAC_RESP_ANTA)
+#define BITS_WMAC_RESP_ANTA \
+ (BIT_MASK_WMAC_RESP_ANTA << BIT_SHIFT_WMAC_RESP_ANTA)
+#define BIT_CLEAR_WMAC_RESP_ANTA(x) ((x) & (~BITS_WMAC_RESP_ANTA))
+#define BIT_GET_WMAC_RESP_ANTA(x) \
+ (((x) >> BIT_SHIFT_WMAC_RESP_ANTA) & BIT_MASK_WMAC_RESP_ANTA)
+#define BIT_SET_WMAC_RESP_ANTA(x, v) \
+ (BIT_CLEAR_WMAC_RESP_ANTA(x) | BIT_WMAC_RESP_ANTA(v))
-/* 2 REG_TX_CSI_RPT_PARAM_BW40 (Offset 0x06F8) */
+#endif
+#if (HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_WMAC_RESP_ANTCD 0
-#define BIT_MASK_WMAC_RESP_ANTCD 0xf
-#define BIT_WMAC_RESP_ANTCD(x) (((x) & BIT_MASK_WMAC_RESP_ANTCD) << BIT_SHIFT_WMAC_RESP_ANTCD)
-#define BIT_GET_WMAC_RESP_ANTCD(x) (((x) >> BIT_SHIFT_WMAC_RESP_ANTCD) & BIT_MASK_WMAC_RESP_ANTCD)
+/* 2 REG_CSI_RRSR_V1 (Offset 0x06FC) */
+#define BIT_WMAC_CSI_LDPC_EN BIT(29)
+#define BIT_WMAC_CSI_STBC_EN BIT(28)
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)
-
/* 2 REG_TX_CSI_RPT_PARAM_BW80 (Offset 0x06FC) */
+#define BIT_SHIFT_R_WMAC_BFINFO_80M_1 16
+#define BIT_MASK_R_WMAC_BFINFO_80M_1 0xfff
+#define BIT_R_WMAC_BFINFO_80M_1(x) \
+ (((x) & BIT_MASK_R_WMAC_BFINFO_80M_1) << BIT_SHIFT_R_WMAC_BFINFO_80M_1)
+#define BITS_R_WMAC_BFINFO_80M_1 \
+ (BIT_MASK_R_WMAC_BFINFO_80M_1 << BIT_SHIFT_R_WMAC_BFINFO_80M_1)
+#define BIT_CLEAR_R_WMAC_BFINFO_80M_1(x) ((x) & (~BITS_R_WMAC_BFINFO_80M_1))
+#define BIT_GET_R_WMAC_BFINFO_80M_1(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_BFINFO_80M_1) & BIT_MASK_R_WMAC_BFINFO_80M_1)
+#define BIT_SET_R_WMAC_BFINFO_80M_1(x, v) \
+ (BIT_CLEAR_R_WMAC_BFINFO_80M_1(x) | BIT_R_WMAC_BFINFO_80M_1(v))
-#define BIT_SHIFT_R_WMAC_BFINFO_80M_1 16
-#define BIT_MASK_R_WMAC_BFINFO_80M_1 0xfff
-#define BIT_R_WMAC_BFINFO_80M_1(x) (((x) & BIT_MASK_R_WMAC_BFINFO_80M_1) << BIT_SHIFT_R_WMAC_BFINFO_80M_1)
-#define BIT_GET_R_WMAC_BFINFO_80M_1(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_80M_1) & BIT_MASK_R_WMAC_BFINFO_80M_1)
+#endif
+#if (HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_R_WMAC_BFINFO_80M_0 0
-#define BIT_MASK_R_WMAC_BFINFO_80M_0 0xfff
-#define BIT_R_WMAC_BFINFO_80M_0(x) (((x) & BIT_MASK_R_WMAC_BFINFO_80M_0) << BIT_SHIFT_R_WMAC_BFINFO_80M_0)
-#define BIT_GET_R_WMAC_BFINFO_80M_0(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_80M_0) & BIT_MASK_R_WMAC_BFINFO_80M_0)
+/* 2 REG_CSI_PTR (Offset 0x06FC) */
+#define BIT_SHIFT_CSI_RADDR_LATCH_V2 16
+#define BIT_MASK_CSI_RADDR_LATCH_V2 0xffff
+#define BIT_CSI_RADDR_LATCH_V2(x) \
+ (((x) & BIT_MASK_CSI_RADDR_LATCH_V2) << BIT_SHIFT_CSI_RADDR_LATCH_V2)
+#define BITS_CSI_RADDR_LATCH_V2 \
+ (BIT_MASK_CSI_RADDR_LATCH_V2 << BIT_SHIFT_CSI_RADDR_LATCH_V2)
+#define BIT_CLEAR_CSI_RADDR_LATCH_V2(x) ((x) & (~BITS_CSI_RADDR_LATCH_V2))
+#define BIT_GET_CSI_RADDR_LATCH_V2(x) \
+ (((x) >> BIT_SHIFT_CSI_RADDR_LATCH_V2) & BIT_MASK_CSI_RADDR_LATCH_V2)
+#define BIT_SET_CSI_RADDR_LATCH_V2(x, v) \
+ (BIT_CLEAR_CSI_RADDR_LATCH_V2(x) | BIT_CSI_RADDR_LATCH_V2(v))
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_CSI_RRSR_V1 (Offset 0x06FC) */
+#define BIT_SHIFT_WMAC_CSI_RRSC_BITMAP 4
+#define BIT_MASK_WMAC_CSI_RRSC_BITMAP 0xffffff
+#define BIT_WMAC_CSI_RRSC_BITMAP(x) \
+ (((x) & BIT_MASK_WMAC_CSI_RRSC_BITMAP) \
+ << BIT_SHIFT_WMAC_CSI_RRSC_BITMAP)
+#define BITS_WMAC_CSI_RRSC_BITMAP \
+ (BIT_MASK_WMAC_CSI_RRSC_BITMAP << BIT_SHIFT_WMAC_CSI_RRSC_BITMAP)
+#define BIT_CLEAR_WMAC_CSI_RRSC_BITMAP(x) ((x) & (~BITS_WMAC_CSI_RRSC_BITMAP))
+#define BIT_GET_WMAC_CSI_RRSC_BITMAP(x) \
+ (((x) >> BIT_SHIFT_WMAC_CSI_RRSC_BITMAP) & \
+ BIT_MASK_WMAC_CSI_RRSC_BITMAP)
+#define BIT_SET_WMAC_CSI_RRSC_BITMAP(x, v) \
+ (BIT_CLEAR_WMAC_CSI_RRSC_BITMAP(x) | BIT_WMAC_CSI_RRSC_BITMAP(v))
-/* 2 REG_MACID1 (Offset 0x0700) */
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)
+
+/* 2 REG_TX_CSI_RPT_PARAM_BW80 (Offset 0x06FC) */
+#define BIT_SHIFT_R_WMAC_BFINFO_80M_0 0
+#define BIT_MASK_R_WMAC_BFINFO_80M_0 0xfff
+#define BIT_R_WMAC_BFINFO_80M_0(x) \
+ (((x) & BIT_MASK_R_WMAC_BFINFO_80M_0) << BIT_SHIFT_R_WMAC_BFINFO_80M_0)
+#define BITS_R_WMAC_BFINFO_80M_0 \
+ (BIT_MASK_R_WMAC_BFINFO_80M_0 << BIT_SHIFT_R_WMAC_BFINFO_80M_0)
+#define BIT_CLEAR_R_WMAC_BFINFO_80M_0(x) ((x) & (~BITS_R_WMAC_BFINFO_80M_0))
+#define BIT_GET_R_WMAC_BFINFO_80M_0(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_BFINFO_80M_0) & BIT_MASK_R_WMAC_BFINFO_80M_0)
+#define BIT_SET_R_WMAC_BFINFO_80M_0(x, v) \
+ (BIT_CLEAR_R_WMAC_BFINFO_80M_0(x) | BIT_R_WMAC_BFINFO_80M_0(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_CSI_RRSR_V1 (Offset 0x06FC) */
+
+#define BIT_SHIFT_WMAC_CSI_OFDM_LEN_TH 0
+#define BIT_MASK_WMAC_CSI_OFDM_LEN_TH 0xf
+#define BIT_WMAC_CSI_OFDM_LEN_TH(x) \
+ (((x) & BIT_MASK_WMAC_CSI_OFDM_LEN_TH) \
+ << BIT_SHIFT_WMAC_CSI_OFDM_LEN_TH)
+#define BITS_WMAC_CSI_OFDM_LEN_TH \
+ (BIT_MASK_WMAC_CSI_OFDM_LEN_TH << BIT_SHIFT_WMAC_CSI_OFDM_LEN_TH)
+#define BIT_CLEAR_WMAC_CSI_OFDM_LEN_TH(x) ((x) & (~BITS_WMAC_CSI_OFDM_LEN_TH))
+#define BIT_GET_WMAC_CSI_OFDM_LEN_TH(x) \
+ (((x) >> BIT_SHIFT_WMAC_CSI_OFDM_LEN_TH) & \
+ BIT_MASK_WMAC_CSI_OFDM_LEN_TH)
+#define BIT_SET_WMAC_CSI_OFDM_LEN_TH(x, v) \
+ (BIT_CLEAR_WMAC_CSI_OFDM_LEN_TH(x) | BIT_WMAC_CSI_OFDM_LEN_TH(v))
+
+#define BIT_SHIFT_CSI_PARA_RDY_DLYCNT 0
+#define BIT_MASK_CSI_PARA_RDY_DLYCNT 0x1f
+#define BIT_CSI_PARA_RDY_DLYCNT(x) \
+ (((x) & BIT_MASK_CSI_PARA_RDY_DLYCNT) << BIT_SHIFT_CSI_PARA_RDY_DLYCNT)
+#define BITS_CSI_PARA_RDY_DLYCNT \
+ (BIT_MASK_CSI_PARA_RDY_DLYCNT << BIT_SHIFT_CSI_PARA_RDY_DLYCNT)
+#define BIT_CLEAR_CSI_PARA_RDY_DLYCNT(x) ((x) & (~BITS_CSI_PARA_RDY_DLYCNT))
+#define BIT_GET_CSI_PARA_RDY_DLYCNT(x) \
+ (((x) >> BIT_SHIFT_CSI_PARA_RDY_DLYCNT) & BIT_MASK_CSI_PARA_RDY_DLYCNT)
+#define BIT_SET_CSI_PARA_RDY_DLYCNT(x, v) \
+ (BIT_CLEAR_CSI_PARA_RDY_DLYCNT(x) | BIT_CSI_PARA_RDY_DLYCNT(v))
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CSI_PTR (Offset 0x06FC) */
+
+#define BIT_SHIFT_CSI_WADDR_LATCH_V2 0
+#define BIT_MASK_CSI_WADDR_LATCH_V2 0xffff
+#define BIT_CSI_WADDR_LATCH_V2(x) \
+ (((x) & BIT_MASK_CSI_WADDR_LATCH_V2) << BIT_SHIFT_CSI_WADDR_LATCH_V2)
+#define BITS_CSI_WADDR_LATCH_V2 \
+ (BIT_MASK_CSI_WADDR_LATCH_V2 << BIT_SHIFT_CSI_WADDR_LATCH_V2)
+#define BIT_CLEAR_CSI_WADDR_LATCH_V2(x) ((x) & (~BITS_CSI_WADDR_LATCH_V2))
+#define BIT_GET_CSI_WADDR_LATCH_V2(x) \
+ (((x) >> BIT_SHIFT_CSI_WADDR_LATCH_V2) & BIT_MASK_CSI_WADDR_LATCH_V2)
+#define BIT_SET_CSI_WADDR_LATCH_V2(x, v) \
+ (BIT_CLEAR_CSI_WADDR_LATCH_V2(x) | BIT_CSI_WADDR_LATCH_V2(v))
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define BIT_SHIFT_MACID1 0
-#define BIT_MASK_MACID1 0xffffffffffffL
-#define BIT_MACID1(x) (((x) & BIT_MASK_MACID1) << BIT_SHIFT_MACID1)
-#define BIT_GET_MACID1(x) (((x) >> BIT_SHIFT_MACID1) & BIT_MASK_MACID1)
+/* 2 REG_MACID1 (Offset 0x0700) */
+#define BIT_SHIFT_MACID1 0
+#define BIT_MASK_MACID1 0xffffffffffffL
+#define BIT_MACID1(x) (((x) & BIT_MASK_MACID1) << BIT_SHIFT_MACID1)
+#define BITS_MACID1 (BIT_MASK_MACID1 << BIT_SHIFT_MACID1)
+#define BIT_CLEAR_MACID1(x) ((x) & (~BITS_MACID1))
+#define BIT_GET_MACID1(x) (((x) >> BIT_SHIFT_MACID1) & BIT_MASK_MACID1)
+#define BIT_SET_MACID1(x, v) (BIT_CLEAR_MACID1(x) | BIT_MACID1(v))
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_MACID1 (Offset 0x0700) */
+#define BIT_SHIFT_MACID1_0 0
+#define BIT_MASK_MACID1_0 0xffffffffL
+#define BIT_MACID1_0(x) (((x) & BIT_MASK_MACID1_0) << BIT_SHIFT_MACID1_0)
+#define BITS_MACID1_0 (BIT_MASK_MACID1_0 << BIT_SHIFT_MACID1_0)
+#define BIT_CLEAR_MACID1_0(x) ((x) & (~BITS_MACID1_0))
+#define BIT_GET_MACID1_0(x) (((x) >> BIT_SHIFT_MACID1_0) & BIT_MASK_MACID1_0)
+#define BIT_SET_MACID1_0(x, v) (BIT_CLEAR_MACID1_0(x) | BIT_MACID1_0(v))
-/* 2 REG_BSSID1 (Offset 0x0708) */
+/* 2 REG_MACID1_1 (Offset 0x0704) */
+#define BIT_SHIFT_MACID1_1 0
+#define BIT_MASK_MACID1_1 0xffff
+#define BIT_MACID1_1(x) (((x) & BIT_MASK_MACID1_1) << BIT_SHIFT_MACID1_1)
+#define BITS_MACID1_1 (BIT_MASK_MACID1_1 << BIT_SHIFT_MACID1_1)
+#define BIT_CLEAR_MACID1_1(x) ((x) & (~BITS_MACID1_1))
+#define BIT_GET_MACID1_1(x) (((x) >> BIT_SHIFT_MACID1_1) & BIT_MASK_MACID1_1)
+#define BIT_SET_MACID1_1(x, v) (BIT_CLEAR_MACID1_1(x) | BIT_MACID1_1(v))
-#define BIT_SHIFT_BSSID1 0
-#define BIT_MASK_BSSID1 0xffffffffffffL
-#define BIT_BSSID1(x) (((x) & BIT_MASK_BSSID1) << BIT_SHIFT_BSSID1)
-#define BIT_GET_BSSID1(x) (((x) >> BIT_SHIFT_BSSID1) & BIT_MASK_BSSID1)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
-/* 2 REG_BCN_PSR_RPT1 (Offset 0x0710) */
+/* 2 REG_BSSID1 (Offset 0x0708) */
+#define BIT_SHIFT_BSSID1 0
+#define BIT_MASK_BSSID1 0xffffffffffffL
+#define BIT_BSSID1(x) (((x) & BIT_MASK_BSSID1) << BIT_SHIFT_BSSID1)
+#define BITS_BSSID1 (BIT_MASK_BSSID1 << BIT_SHIFT_BSSID1)
+#define BIT_CLEAR_BSSID1(x) ((x) & (~BITS_BSSID1))
+#define BIT_GET_BSSID1(x) (((x) >> BIT_SHIFT_BSSID1) & BIT_MASK_BSSID1)
+#define BIT_SET_BSSID1(x, v) (BIT_CLEAR_BSSID1(x) | BIT_BSSID1(v))
-#define BIT_SHIFT_DTIM_CNT1 24
-#define BIT_MASK_DTIM_CNT1 0xff
-#define BIT_DTIM_CNT1(x) (((x) & BIT_MASK_DTIM_CNT1) << BIT_SHIFT_DTIM_CNT1)
-#define BIT_GET_DTIM_CNT1(x) (((x) >> BIT_SHIFT_DTIM_CNT1) & BIT_MASK_DTIM_CNT1)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_DTIM_PERIOD1 16
-#define BIT_MASK_DTIM_PERIOD1 0xff
-#define BIT_DTIM_PERIOD1(x) (((x) & BIT_MASK_DTIM_PERIOD1) << BIT_SHIFT_DTIM_PERIOD1)
-#define BIT_GET_DTIM_PERIOD1(x) (((x) >> BIT_SHIFT_DTIM_PERIOD1) & BIT_MASK_DTIM_PERIOD1)
+/* 2 REG_BSSID1 (Offset 0x0708) */
-#define BIT_DTIM1 BIT(15)
-#define BIT_TIM1 BIT(14)
+#define BIT_SHIFT_BSSID1_0 0
+#define BIT_MASK_BSSID1_0 0xffffffffL
+#define BIT_BSSID1_0(x) (((x) & BIT_MASK_BSSID1_0) << BIT_SHIFT_BSSID1_0)
+#define BITS_BSSID1_0 (BIT_MASK_BSSID1_0 << BIT_SHIFT_BSSID1_0)
+#define BIT_CLEAR_BSSID1_0(x) ((x) & (~BITS_BSSID1_0))
+#define BIT_GET_BSSID1_0(x) (((x) >> BIT_SHIFT_BSSID1_0) & BIT_MASK_BSSID1_0)
+#define BIT_SET_BSSID1_0(x, v) (BIT_CLEAR_BSSID1_0(x) | BIT_BSSID1_0(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_PCIE_CFG_FORCE_LINK_L (Offset 0x0709) */
+
+#define BIT_PCIE_CFG_FORCE_EN BIT(7)
+
+/* 2 REG_PCIE_CFG_FORCE_LINK_H (Offset 0x070A) */
+
+#define BIT_PCIE_CFG_TRXACT_DIS_IDLE_TIMER BIT(6)
+
+#define BIT_SHIFT_PCIE_CFG_LINK_STATE 0
+#define BIT_MASK_PCIE_CFG_LINK_STATE 0x3f
+#define BIT_PCIE_CFG_LINK_STATE(x) \
+ (((x) & BIT_MASK_PCIE_CFG_LINK_STATE) << BIT_SHIFT_PCIE_CFG_LINK_STATE)
+#define BITS_PCIE_CFG_LINK_STATE \
+ (BIT_MASK_PCIE_CFG_LINK_STATE << BIT_SHIFT_PCIE_CFG_LINK_STATE)
+#define BIT_CLEAR_PCIE_CFG_LINK_STATE(x) ((x) & (~BITS_PCIE_CFG_LINK_STATE))
+#define BIT_GET_PCIE_CFG_LINK_STATE(x) \
+ (((x) >> BIT_SHIFT_PCIE_CFG_LINK_STATE) & BIT_MASK_PCIE_CFG_LINK_STATE)
+#define BIT_SET_PCIE_CFG_LINK_STATE(x, v) \
+ (BIT_CLEAR_PCIE_CFG_LINK_STATE(x) | BIT_PCIE_CFG_LINK_STATE(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BSSID1_1 (Offset 0x070C) */
+
+#define BIT_SHIFT_BSSID1_1 0
+#define BIT_MASK_BSSID1_1 0xffff
+#define BIT_BSSID1_1(x) (((x) & BIT_MASK_BSSID1_1) << BIT_SHIFT_BSSID1_1)
+#define BITS_BSSID1_1 (BIT_MASK_BSSID1_1 << BIT_SHIFT_BSSID1_1)
+#define BIT_CLEAR_BSSID1_1(x) ((x) & (~BITS_BSSID1_1))
+#define BIT_GET_BSSID1_1(x) (((x) >> BIT_SHIFT_BSSID1_1) & BIT_MASK_BSSID1_1)
+#define BIT_SET_BSSID1_1(x, v) (BIT_CLEAR_BSSID1_1(x) | BIT_BSSID1_1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_PCIE_CFG_DEFAULT_ACK_FREQUENCY (Offset 0x070C) */
+
+#define BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY 0
+#define BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY 0xff
+#define BIT_PCIE_CFG_DEFAULT_ACK_FREQUENCY(x) \
+ (((x) & BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY) \
+ << BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY)
+#define BITS_PCIE_CFG_DEFAULT_ACK_FREQUENCY \
+ (BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY \
+ << BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY)
+#define BIT_CLEAR_PCIE_CFG_DEFAULT_ACK_FREQUENCY(x) \
+ ((x) & (~BITS_PCIE_CFG_DEFAULT_ACK_FREQUENCY))
+#define BIT_GET_PCIE_CFG_DEFAULT_ACK_FREQUENCY(x) \
+ (((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY) & \
+ BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY)
+#define BIT_SET_PCIE_CFG_DEFAULT_ACK_FREQUENCY(x, v) \
+ (BIT_CLEAR_PCIE_CFG_DEFAULT_ACK_FREQUENCY(x) | \
+ BIT_PCIE_CFG_DEFAULT_ACK_FREQUENCY(v))
+
+/* 2 REG_PCIE_CFG_CX_NFTS (Offset 0x070D) */
+
+#define BIT_SHIFT_PCIE_CFG_CX_NFTS 0
+#define BIT_MASK_PCIE_CFG_CX_NFTS 0xff
+#define BIT_PCIE_CFG_CX_NFTS(x) \
+ (((x) & BIT_MASK_PCIE_CFG_CX_NFTS) << BIT_SHIFT_PCIE_CFG_CX_NFTS)
+#define BITS_PCIE_CFG_CX_NFTS \
+ (BIT_MASK_PCIE_CFG_CX_NFTS << BIT_SHIFT_PCIE_CFG_CX_NFTS)
+#define BIT_CLEAR_PCIE_CFG_CX_NFTS(x) ((x) & (~BITS_PCIE_CFG_CX_NFTS))
+#define BIT_GET_PCIE_CFG_CX_NFTS(x) \
+ (((x) >> BIT_SHIFT_PCIE_CFG_CX_NFTS) & BIT_MASK_PCIE_CFG_CX_NFTS)
+#define BIT_SET_PCIE_CFG_CX_NFTS(x, v) \
+ (BIT_CLEAR_PCIE_CFG_CX_NFTS(x) | BIT_PCIE_CFG_CX_NFTS(v))
+
+/* 2 REG_PCIE_CFG_DEFAULT_ENTR_LATENCY (Offset 0x070F) */
+
+#define BIT_PCIE_CFG_REAL_EN_L0S BIT(7)
+#define BIT_PCIE_CFG_ENTER_ASPM BIT(6)
+
+#define BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY 3
+#define BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY 0x7
+#define BIT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY(x) \
+ (((x) & BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY) \
+ << BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY)
+#define BITS_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY \
+ (BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY \
+ << BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY)
+#define BIT_CLEAR_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY(x) \
+ ((x) & (~BITS_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY))
+#define BIT_GET_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY(x) \
+ (((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY) & \
+ BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY)
+#define BIT_SET_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY(x, v) \
+ (BIT_CLEAR_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY(x) | \
+ BIT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY(v))
+
+#define BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY 0
+#define BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY 0x7
+#define BIT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY(x) \
+ (((x) & BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY) \
+ << BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY)
+#define BITS_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY \
+ (BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY \
+ << BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY)
+#define BIT_CLEAR_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY(x) \
+ ((x) & (~BITS_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY))
+#define BIT_GET_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY(x) \
+ (((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY) & \
+ BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY)
+#define BIT_SET_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY(x, v) \
+ (BIT_CLEAR_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY(x) | \
+ BIT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_PS_AID_1 0
-#define BIT_MASK_PS_AID_1 0x7ff
-#define BIT_PS_AID_1(x) (((x) & BIT_MASK_PS_AID_1) << BIT_SHIFT_PS_AID_1)
-#define BIT_GET_PS_AID_1(x) (((x) >> BIT_SHIFT_PS_AID_1) & BIT_MASK_PS_AID_1)
+/* 2 REG_BCN_PSR_RPT1 (Offset 0x0710) */
+#define BIT_TXUSER_ID1 BIT(25)
-#endif
+#define BIT_SHIFT_DTIM_CNT1 24
+#define BIT_MASK_DTIM_CNT1 0xff
+#define BIT_DTIM_CNT1(x) (((x) & BIT_MASK_DTIM_CNT1) << BIT_SHIFT_DTIM_CNT1)
+#define BITS_DTIM_CNT1 (BIT_MASK_DTIM_CNT1 << BIT_SHIFT_DTIM_CNT1)
+#define BIT_CLEAR_DTIM_CNT1(x) ((x) & (~BITS_DTIM_CNT1))
+#define BIT_GET_DTIM_CNT1(x) (((x) >> BIT_SHIFT_DTIM_CNT1) & BIT_MASK_DTIM_CNT1)
+#define BIT_SET_DTIM_CNT1(x, v) (BIT_CLEAR_DTIM_CNT1(x) | BIT_DTIM_CNT1(v))
+#define BIT_SHIFT_DTIM_PERIOD1 16
+#define BIT_MASK_DTIM_PERIOD1 0xff
+#define BIT_DTIM_PERIOD1(x) \
+ (((x) & BIT_MASK_DTIM_PERIOD1) << BIT_SHIFT_DTIM_PERIOD1)
+#define BITS_DTIM_PERIOD1 (BIT_MASK_DTIM_PERIOD1 << BIT_SHIFT_DTIM_PERIOD1)
+#define BIT_CLEAR_DTIM_PERIOD1(x) ((x) & (~BITS_DTIM_PERIOD1))
+#define BIT_GET_DTIM_PERIOD1(x) \
+ (((x) >> BIT_SHIFT_DTIM_PERIOD1) & BIT_MASK_DTIM_PERIOD1)
+#define BIT_SET_DTIM_PERIOD1(x, v) \
+ (BIT_CLEAR_DTIM_PERIOD1(x) | BIT_DTIM_PERIOD1(v))
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+#define BIT_SHIFT_AID1 16
+#define BIT_MASK_AID1 0x1ff
+#define BIT_AID1(x) (((x) & BIT_MASK_AID1) << BIT_SHIFT_AID1)
+#define BITS_AID1 (BIT_MASK_AID1 << BIT_SHIFT_AID1)
+#define BIT_CLEAR_AID1(x) ((x) & (~BITS_AID1))
+#define BIT_GET_AID1(x) (((x) >> BIT_SHIFT_AID1) & BIT_MASK_AID1)
+#define BIT_SET_AID1(x, v) (BIT_CLEAR_AID1(x) | BIT_AID1(v))
+#define BIT_DTIM1 BIT(15)
+#define BIT_TIM1 BIT(14)
-/* 2 REG_ASSOCIATED_BFMEE_SEL (Offset 0x0714) */
+#endif
+#if (HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_RD_BF_SEL 29
-#define BIT_MASK_RD_BF_SEL 0x7
-#define BIT_RD_BF_SEL(x) (((x) & BIT_MASK_RD_BF_SEL) << BIT_SHIFT_RD_BF_SEL)
-#define BIT_GET_RD_BF_SEL(x) (((x) >> BIT_SHIFT_RD_BF_SEL) & BIT_MASK_RD_BF_SEL)
+/* 2 REG_BCN_PSR_RPT1 (Offset 0x0710) */
+#define BIT_BCN_VALID_V2 BIT(13)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+/* 2 REG_BCN_PSR_RPT1 (Offset 0x0710) */
-/* 2 REG_ASSOCIATED_BFMEE_SEL (Offset 0x0714) */
+#define BIT_TXUSER_ID0 BIT(9)
-#define BIT_TXUSER_ID1 BIT(25)
+#define BIT_SHIFT_PS_AID_1 0
+#define BIT_MASK_PS_AID_1 0x7ff
+#define BIT_PS_AID_1(x) (((x) & BIT_MASK_PS_AID_1) << BIT_SHIFT_PS_AID_1)
+#define BITS_PS_AID_1 (BIT_MASK_PS_AID_1 << BIT_SHIFT_PS_AID_1)
+#define BIT_CLEAR_PS_AID_1(x) ((x) & (~BITS_PS_AID_1))
+#define BIT_GET_PS_AID_1(x) (((x) >> BIT_SHIFT_PS_AID_1) & BIT_MASK_PS_AID_1)
+#define BIT_SET_PS_AID_1(x, v) (BIT_CLEAR_PS_AID_1(x) | BIT_PS_AID_1(v))
-#define BIT_SHIFT_AID1 16
-#define BIT_MASK_AID1 0x1ff
-#define BIT_AID1(x) (((x) & BIT_MASK_AID1) << BIT_SHIFT_AID1)
-#define BIT_GET_AID1(x) (((x) >> BIT_SHIFT_AID1) & BIT_MASK_AID1)
+#define BIT_SHIFT_AID0 0
+#define BIT_MASK_AID0 0x1ff
+#define BIT_AID0(x) (((x) & BIT_MASK_AID0) << BIT_SHIFT_AID0)
+#define BITS_AID0 (BIT_MASK_AID0 << BIT_SHIFT_AID0)
+#define BIT_CLEAR_AID0(x) ((x) & (~BITS_AID0))
+#define BIT_GET_AID0(x) (((x) >> BIT_SHIFT_AID0) & BIT_MASK_AID0)
+#define BIT_SET_AID0(x, v) (BIT_CLEAR_AID0(x) | BIT_AID0(v))
-#define BIT_TXUSER_ID0 BIT(9)
+#endif
-#define BIT_SHIFT_AID0 0
-#define BIT_MASK_AID0 0x1ff
-#define BIT_AID0(x) (((x) & BIT_MASK_AID0) << BIT_SHIFT_AID0)
-#define BIT_GET_AID0(x) (((x) >> BIT_SHIFT_AID0) & BIT_MASK_AID0)
+#if (HALMAC_8814B_SUPPORT)
+/* 2 REG_PCIE_CFG_L1_MISC_SEL (Offset 0x0711) */
-/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */
+#define BIT_PCIE_CFG_L1_RIDLE_SEL BIT(6)
+#define BIT_PCIE_CFG_L1_TIMEOUT_SEL BIT(5)
+#define BIT_PCIE_CFG_L1_EIDLE_SEL BIT(4)
+#define BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE 0
+#define BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE 0xf
+#define BIT_PCIE_CFG_DEFAULT_LINK_RATE(x) \
+ (((x) & BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE) \
+ << BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE)
+#define BITS_PCIE_CFG_DEFAULT_LINK_RATE \
+ (BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE \
+ << BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE)
+#define BIT_CLEAR_PCIE_CFG_DEFAULT_LINK_RATE(x) \
+ ((x) & (~BITS_PCIE_CFG_DEFAULT_LINK_RATE))
+#define BIT_GET_PCIE_CFG_DEFAULT_LINK_RATE(x) \
+ (((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE) & \
+ BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE)
+#define BIT_SET_PCIE_CFG_DEFAULT_LINK_RATE(x, v) \
+ (BIT_CLEAR_PCIE_CFG_DEFAULT_LINK_RATE(x) | \
+ BIT_PCIE_CFG_DEFAULT_LINK_RATE(v))
-#define BIT_SHIFT_NDP_RX_STANDBY_TIMER 24
-#define BIT_MASK_NDP_RX_STANDBY_TIMER 0xff
-#define BIT_NDP_RX_STANDBY_TIMER(x) (((x) & BIT_MASK_NDP_RX_STANDBY_TIMER) << BIT_SHIFT_NDP_RX_STANDBY_TIMER)
-#define BIT_GET_NDP_RX_STANDBY_TIMER(x) (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER) & BIT_MASK_NDP_RX_STANDBY_TIMER)
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define BIT_SHIFT_CSI_RPT_OFFSET_HT 16
-#define BIT_MASK_CSI_RPT_OFFSET_HT 0xff
-#define BIT_CSI_RPT_OFFSET_HT(x) (((x) & BIT_MASK_CSI_RPT_OFFSET_HT) << BIT_SHIFT_CSI_RPT_OFFSET_HT)
-#define BIT_GET_CSI_RPT_OFFSET_HT(x) (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT) & BIT_MASK_CSI_RPT_OFFSET_HT)
+/* 2 REG_ASSOCIATED_BFMEE_SEL (Offset 0x0714) */
+#define BIT_SHIFT_RD_BF_SEL 29
+#define BIT_MASK_RD_BF_SEL 0x7
+#define BIT_RD_BF_SEL(x) (((x) & BIT_MASK_RD_BF_SEL) << BIT_SHIFT_RD_BF_SEL)
+#define BITS_RD_BF_SEL (BIT_MASK_RD_BF_SEL << BIT_SHIFT_RD_BF_SEL)
+#define BIT_CLEAR_RD_BF_SEL(x) ((x) & (~BITS_RD_BF_SEL))
+#define BIT_GET_RD_BF_SEL(x) (((x) >> BIT_SHIFT_RD_BF_SEL) & BIT_MASK_RD_BF_SEL)
+#define BIT_SET_RD_BF_SEL(x, v) (BIT_CLEAR_RD_BF_SEL(x) | BIT_RD_BF_SEL(v))
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */
+#define BIT_SHIFT_NDP_RX_STANDBY_TIMER 24
+#define BIT_MASK_NDP_RX_STANDBY_TIMER 0xff
+#define BIT_NDP_RX_STANDBY_TIMER(x) \
+ (((x) & BIT_MASK_NDP_RX_STANDBY_TIMER) \
+ << BIT_SHIFT_NDP_RX_STANDBY_TIMER)
+#define BITS_NDP_RX_STANDBY_TIMER \
+ (BIT_MASK_NDP_RX_STANDBY_TIMER << BIT_SHIFT_NDP_RX_STANDBY_TIMER)
+#define BIT_CLEAR_NDP_RX_STANDBY_TIMER(x) ((x) & (~BITS_NDP_RX_STANDBY_TIMER))
+#define BIT_GET_NDP_RX_STANDBY_TIMER(x) \
+ (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER) & \
+ BIT_MASK_NDP_RX_STANDBY_TIMER)
+#define BIT_SET_NDP_RX_STANDBY_TIMER(x, v) \
+ (BIT_CLEAR_NDP_RX_STANDBY_TIMER(x) | BIT_NDP_RX_STANDBY_TIMER(v))
-#define BIT_SHIFT_CSI_RPT_OFFSET_VHT 8
-#define BIT_MASK_CSI_RPT_OFFSET_VHT 0xff
-#define BIT_CSI_RPT_OFFSET_VHT(x) (((x) & BIT_MASK_CSI_RPT_OFFSET_VHT) << BIT_SHIFT_CSI_RPT_OFFSET_VHT)
-#define BIT_GET_CSI_RPT_OFFSET_VHT(x) (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_VHT) & BIT_MASK_CSI_RPT_OFFSET_VHT)
+#endif
+#if (HALMAC_8198F_SUPPORT)
-#endif
+/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */
+#define BIT_WMAC_CHK_RPTPOLL_A2_DIS BIT(23)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8822C_SUPPORT)
/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */
+#define BIT_R_WMAC_CHK_RPTPOLL_A2_DIS BIT(23)
-#define BIT_SHIFT_R_WMAC_VHT_CATEGORY 8
-#define BIT_MASK_R_WMAC_VHT_CATEGORY 0xff
-#define BIT_R_WMAC_VHT_CATEGORY(x) (((x) & BIT_MASK_R_WMAC_VHT_CATEGORY) << BIT_SHIFT_R_WMAC_VHT_CATEGORY)
-#define BIT_GET_R_WMAC_VHT_CATEGORY(x) (((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY) & BIT_MASK_R_WMAC_VHT_CATEGORY)
+#endif
+#if (HALMAC_8198F_SUPPORT)
-#endif
+/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */
+#define BIT_WMAC_CHK_UCNDPA_A2_DIS BIT(22)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8822C_SUPPORT)
/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */
-#define BIT_R_WMAC_USE_NSTS BIT(7)
-#define BIT_R_DISABLE_CHECK_VHTSIGB_CRC BIT(6)
-#define BIT_R_DISABLE_CHECK_VHTSIGA_CRC BIT(5)
-#define BIT_R_WMAC_BFPARAM_SEL BIT(4)
-#define BIT_R_WMAC_CSISEQ_SEL BIT(3)
-#define BIT_R_WMAC_CSI_WITHHTC_EN BIT(2)
-#define BIT_R_WMAC_HT_NDPA_EN BIT(1)
-#define BIT_R_WMAC_VHT_NDPA_EN BIT(0)
+#define BIT_R_WMAC_CHK_UCNDPA_A2_DIS BIT(22)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */
+#define BIT_SHIFT_CSI_RPT_OFFSET_HT 16
+#define BIT_MASK_CSI_RPT_OFFSET_HT 0xff
+#define BIT_CSI_RPT_OFFSET_HT(x) \
+ (((x) & BIT_MASK_CSI_RPT_OFFSET_HT) << BIT_SHIFT_CSI_RPT_OFFSET_HT)
+#define BITS_CSI_RPT_OFFSET_HT \
+ (BIT_MASK_CSI_RPT_OFFSET_HT << BIT_SHIFT_CSI_RPT_OFFSET_HT)
+#define BIT_CLEAR_CSI_RPT_OFFSET_HT(x) ((x) & (~BITS_CSI_RPT_OFFSET_HT))
+#define BIT_GET_CSI_RPT_OFFSET_HT(x) \
+ (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT) & BIT_MASK_CSI_RPT_OFFSET_HT)
+#define BIT_SET_CSI_RPT_OFFSET_HT(x, v) \
+ (BIT_CLEAR_CSI_RPT_OFFSET_HT(x) | BIT_CSI_RPT_OFFSET_HT(v))
-/* 2 REG_RX_CSI_RPT_INFO (Offset 0x071C) */
+#endif
-#define BIT_WRITE_ENABLE BIT(31)
-#define BIT_WRITE_USERID BIT(12)
+#if (HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_WRITE_BW 10
-#define BIT_MASK_WRITE_BW 0x3
-#define BIT_WRITE_BW(x) (((x) & BIT_MASK_WRITE_BW) << BIT_SHIFT_WRITE_BW)
-#define BIT_GET_WRITE_BW(x) (((x) >> BIT_SHIFT_WRITE_BW) & BIT_MASK_WRITE_BW)
+/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */
+#define BIT_SHIFT_CSI_RPT_OFFSET_HT_V1 16
+#define BIT_MASK_CSI_RPT_OFFSET_HT_V1 0x3f
+#define BIT_CSI_RPT_OFFSET_HT_V1(x) \
+ (((x) & BIT_MASK_CSI_RPT_OFFSET_HT_V1) \
+ << BIT_SHIFT_CSI_RPT_OFFSET_HT_V1)
+#define BITS_CSI_RPT_OFFSET_HT_V1 \
+ (BIT_MASK_CSI_RPT_OFFSET_HT_V1 << BIT_SHIFT_CSI_RPT_OFFSET_HT_V1)
+#define BIT_CLEAR_CSI_RPT_OFFSET_HT_V1(x) ((x) & (~BITS_CSI_RPT_OFFSET_HT_V1))
+#define BIT_GET_CSI_RPT_OFFSET_HT_V1(x) \
+ (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_V1) & \
+ BIT_MASK_CSI_RPT_OFFSET_HT_V1)
+#define BIT_SET_CSI_RPT_OFFSET_HT_V1(x, v) \
+ (BIT_CLEAR_CSI_RPT_OFFSET_HT_V1(x) | BIT_CSI_RPT_OFFSET_HT_V1(v))
-#define BIT_SHIFT_WRITE_CB 8
-#define BIT_MASK_WRITE_CB 0x3
-#define BIT_WRITE_CB(x) (((x) & BIT_MASK_WRITE_CB) << BIT_SHIFT_WRITE_CB)
-#define BIT_GET_WRITE_CB(x) (((x) >> BIT_SHIFT_WRITE_CB) & BIT_MASK_WRITE_CB)
+#endif
+#if (HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_WRITE_GROUPING 6
-#define BIT_MASK_WRITE_GROUPING 0x3
-#define BIT_WRITE_GROUPING(x) (((x) & BIT_MASK_WRITE_GROUPING) << BIT_SHIFT_WRITE_GROUPING)
-#define BIT_GET_WRITE_GROUPING(x) (((x) >> BIT_SHIFT_WRITE_GROUPING) & BIT_MASK_WRITE_GROUPING)
+/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */
+#define BIT_WMAC_OFFSET_RPTPOLL_EN BIT(15)
-#define BIT_SHIFT_WRITE_NR 3
-#define BIT_MASK_WRITE_NR 0x7
-#define BIT_WRITE_NR(x) (((x) & BIT_MASK_WRITE_NR) << BIT_SHIFT_WRITE_NR)
-#define BIT_GET_WRITE_NR(x) (((x) >> BIT_SHIFT_WRITE_NR) & BIT_MASK_WRITE_NR)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_WRITE_NC 0
-#define BIT_MASK_WRITE_NC 0x7
-#define BIT_WRITE_NC(x) (((x) & BIT_MASK_WRITE_NC) << BIT_SHIFT_WRITE_NC)
-#define BIT_GET_WRITE_NC(x) (((x) >> BIT_SHIFT_WRITE_NC) & BIT_MASK_WRITE_NC)
+/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */
+#define BIT_VHTNDP_RPTPOLL_CSI_STR_OFFSET_SEL BIT(15)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */
+#define BIT_R_WMAC_OFFSET_RPTPOLL_EN BIT(15)
-/* 2 REG_NS_ARP_CTRL (Offset 0x0720) */
+#endif
-#define BIT_R_WMAC_NSARP_RSPEN BIT(15)
-#define BIT_R_WMAC_NSARP_RARP BIT(9)
-#define BIT_R_WMAC_NSARP_RIPV6 BIT(8)
+#if (HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_R_WMAC_NSARP_MODEN 6
-#define BIT_MASK_R_WMAC_NSARP_MODEN 0x3
-#define BIT_R_WMAC_NSARP_MODEN(x) (((x) & BIT_MASK_R_WMAC_NSARP_MODEN) << BIT_SHIFT_R_WMAC_NSARP_MODEN)
-#define BIT_GET_R_WMAC_NSARP_MODEN(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN) & BIT_MASK_R_WMAC_NSARP_MODEN)
+/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */
+#define BIT_WMAC_CSI_CHKSUM_DIS BIT(14)
-#define BIT_SHIFT_R_WMAC_NSARP_RSPFTP 4
-#define BIT_MASK_R_WMAC_NSARP_RSPFTP 0x3
-#define BIT_R_WMAC_NSARP_RSPFTP(x) (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP) << BIT_SHIFT_R_WMAC_NSARP_RSPFTP)
-#define BIT_GET_R_WMAC_NSARP_RSPFTP(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP) & BIT_MASK_R_WMAC_NSARP_RSPFTP)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_R_WMAC_NSARP_RSPSEC 0
-#define BIT_MASK_R_WMAC_NSARP_RSPSEC 0xf
-#define BIT_R_WMAC_NSARP_RSPSEC(x) (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC) << BIT_SHIFT_R_WMAC_NSARP_RSPSEC)
-#define BIT_GET_R_WMAC_NSARP_RSPSEC(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC) & BIT_MASK_R_WMAC_NSARP_RSPSEC)
+/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */
+#define BIT_R_WMAC_CSI_CHKSUM_DIS BIT(14)
#endif
+#if (HALMAC_8822B_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */
+#define BIT_NDPVLD_POS_RST_FFPTR_DIS BIT(14)
-/* 2 REG_NS_ARP_INFO (Offset 0x0724) */
+#endif
-#define BIT_REQ_IS_MCNS BIT(23)
-#define BIT_REQ_IS_UCNS BIT(22)
-#define BIT_REQ_IS_USNS BIT(21)
-#define BIT_REQ_IS_ARP BIT(20)
-#define BIT_EXPRSP_MH_WITHQC BIT(19)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define BIT_SHIFT_EXPRSP_SECTYPE 16
-#define BIT_MASK_EXPRSP_SECTYPE 0x7
-#define BIT_EXPRSP_SECTYPE(x) (((x) & BIT_MASK_EXPRSP_SECTYPE) << BIT_SHIFT_EXPRSP_SECTYPE)
-#define BIT_GET_EXPRSP_SECTYPE(x) (((x) >> BIT_SHIFT_EXPRSP_SECTYPE) & BIT_MASK_EXPRSP_SECTYPE)
+/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */
+#define BIT_SHIFT_CSI_RPT_OFFSET_VHT 8
+#define BIT_MASK_CSI_RPT_OFFSET_VHT 0xff
+#define BIT_CSI_RPT_OFFSET_VHT(x) \
+ (((x) & BIT_MASK_CSI_RPT_OFFSET_VHT) << BIT_SHIFT_CSI_RPT_OFFSET_VHT)
+#define BITS_CSI_RPT_OFFSET_VHT \
+ (BIT_MASK_CSI_RPT_OFFSET_VHT << BIT_SHIFT_CSI_RPT_OFFSET_VHT)
+#define BIT_CLEAR_CSI_RPT_OFFSET_VHT(x) ((x) & (~BITS_CSI_RPT_OFFSET_VHT))
+#define BIT_GET_CSI_RPT_OFFSET_VHT(x) \
+ (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_VHT) & BIT_MASK_CSI_RPT_OFFSET_VHT)
+#define BIT_SET_CSI_RPT_OFFSET_VHT(x, v) \
+ (BIT_CLEAR_CSI_RPT_OFFSET_VHT(x) | BIT_CSI_RPT_OFFSET_VHT(v))
-#define BIT_SHIFT_EXPRSP_CHKSM_7_TO_0 8
-#define BIT_MASK_EXPRSP_CHKSM_7_TO_0 0xff
-#define BIT_EXPRSP_CHKSM_7_TO_0(x) (((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0) << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0)
-#define BIT_GET_EXPRSP_CHKSM_7_TO_0(x) (((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0) & BIT_MASK_EXPRSP_CHKSM_7_TO_0)
+#endif
+#if (HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_EXPRSP_CHKSM_15_TO_8 0
-#define BIT_MASK_EXPRSP_CHKSM_15_TO_8 0xff
-#define BIT_EXPRSP_CHKSM_15_TO_8(x) (((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8) << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8)
-#define BIT_GET_EXPRSP_CHKSM_15_TO_8(x) (((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8) & BIT_MASK_EXPRSP_CHKSM_15_TO_8)
+/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */
+#define BIT_SHIFT_CSI_RPT_OFFSET_VHT_V1 8
+#define BIT_MASK_CSI_RPT_OFFSET_VHT_V1 0x3f
+#define BIT_CSI_RPT_OFFSET_VHT_V1(x) \
+ (((x) & BIT_MASK_CSI_RPT_OFFSET_VHT_V1) \
+ << BIT_SHIFT_CSI_RPT_OFFSET_VHT_V1)
+#define BITS_CSI_RPT_OFFSET_VHT_V1 \
+ (BIT_MASK_CSI_RPT_OFFSET_VHT_V1 << BIT_SHIFT_CSI_RPT_OFFSET_VHT_V1)
+#define BIT_CLEAR_CSI_RPT_OFFSET_VHT_V1(x) ((x) & (~BITS_CSI_RPT_OFFSET_VHT_V1))
+#define BIT_GET_CSI_RPT_OFFSET_VHT_V1(x) \
+ (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_VHT_V1) & \
+ BIT_MASK_CSI_RPT_OFFSET_VHT_V1)
+#define BIT_SET_CSI_RPT_OFFSET_VHT_V1(x, v) \
+ (BIT_CLEAR_CSI_RPT_OFFSET_VHT_V1(x) | BIT_CSI_RPT_OFFSET_VHT_V1(v))
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8821C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */
+#define BIT_SHIFT_R_WMAC_VHT_CATEGORY 8
+#define BIT_MASK_R_WMAC_VHT_CATEGORY 0xff
+#define BIT_R_WMAC_VHT_CATEGORY(x) \
+ (((x) & BIT_MASK_R_WMAC_VHT_CATEGORY) << BIT_SHIFT_R_WMAC_VHT_CATEGORY)
+#define BITS_R_WMAC_VHT_CATEGORY \
+ (BIT_MASK_R_WMAC_VHT_CATEGORY << BIT_SHIFT_R_WMAC_VHT_CATEGORY)
+#define BIT_CLEAR_R_WMAC_VHT_CATEGORY(x) ((x) & (~BITS_R_WMAC_VHT_CATEGORY))
+#define BIT_GET_R_WMAC_VHT_CATEGORY(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY) & BIT_MASK_R_WMAC_VHT_CATEGORY)
+#define BIT_SET_R_WMAC_VHT_CATEGORY(x, v) \
+ (BIT_CLEAR_R_WMAC_VHT_CATEGORY(x) | BIT_R_WMAC_VHT_CATEGORY(v))
-/* 2 REG_BEAMFORMING_INFO_NSARP_V1 (Offset 0x0728) */
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_WMAC_ARPIP 0
-#define BIT_MASK_WMAC_ARPIP 0xffffffffL
-#define BIT_WMAC_ARPIP(x) (((x) & BIT_MASK_WMAC_ARPIP) << BIT_SHIFT_WMAC_ARPIP)
-#define BIT_GET_WMAC_ARPIP(x) (((x) >> BIT_SHIFT_WMAC_ARPIP) & BIT_MASK_WMAC_ARPIP)
+/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */
+#define BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1 8
+#define BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1 0x3f
+#define BIT_R_CSI_RPT_OFFSET_VHT_V1(x) \
+ (((x) & BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1) \
+ << BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1)
+#define BITS_R_CSI_RPT_OFFSET_VHT_V1 \
+ (BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1 << BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1)
+#define BIT_CLEAR_R_CSI_RPT_OFFSET_VHT_V1(x) \
+ ((x) & (~BITS_R_CSI_RPT_OFFSET_VHT_V1))
+#define BIT_GET_R_CSI_RPT_OFFSET_VHT_V1(x) \
+ (((x) >> BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1) & \
+ BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1)
+#define BIT_SET_R_CSI_RPT_OFFSET_VHT_V1(x, v) \
+ (BIT_CLEAR_R_CSI_RPT_OFFSET_VHT_V1(x) | BIT_R_CSI_RPT_OFFSET_VHT_V1(v))
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */
+#define BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1 8
+#define BIT_MASK_R_WMAC_VHT_CATEGORY_V1 0x3f
+#define BIT_R_WMAC_VHT_CATEGORY_V1(x) \
+ (((x) & BIT_MASK_R_WMAC_VHT_CATEGORY_V1) \
+ << BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1)
+#define BITS_R_WMAC_VHT_CATEGORY_V1 \
+ (BIT_MASK_R_WMAC_VHT_CATEGORY_V1 << BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1)
+#define BIT_CLEAR_R_WMAC_VHT_CATEGORY_V1(x) \
+ ((x) & (~BITS_R_WMAC_VHT_CATEGORY_V1))
+#define BIT_GET_R_WMAC_VHT_CATEGORY_V1(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1) & \
+ BIT_MASK_R_WMAC_VHT_CATEGORY_V1)
+#define BIT_SET_R_WMAC_VHT_CATEGORY_V1(x, v) \
+ (BIT_CLEAR_R_WMAC_VHT_CATEGORY_V1(x) | BIT_R_WMAC_VHT_CATEGORY_V1(v))
-/* 2 REG_BEAMFORMING_INFO_NSARP (Offset 0x072C) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_BEAMFORMING_INFO 0
-#define BIT_MASK_BEAMFORMING_INFO 0xffffffffL
-#define BIT_BEAMFORMING_INFO(x) (((x) & BIT_MASK_BEAMFORMING_INFO) << BIT_SHIFT_BEAMFORMING_INFO)
-#define BIT_GET_BEAMFORMING_INFO(x) (((x) >> BIT_SHIFT_BEAMFORMING_INFO) & BIT_MASK_BEAMFORMING_INFO)
+/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */
+#define BIT_R_WMAC_USE_NSTS BIT(7)
+#define BIT_R_DISABLE_CHECK_VHTSIGB_CRC BIT(6)
-#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD 0
-#define BIT_MASK_R_WMAC_IPV6_MYIPAD 0xffffffffffffffffffffffffffffffffL
-#define BIT_R_WMAC_IPV6_MYIPAD(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD)
-#define BIT_GET_R_WMAC_IPV6_MYIPAD(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD) & BIT_MASK_R_WMAC_IPV6_MYIPAD)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_PCIE_CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF (Offset 0x0718) */
+#define BIT_PCIE_CFG_REAL_PTM_ENABLE BIT(6)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_WMAC_RTX_CTX_SUBTYPE_CFG (Offset 0x0750) */
+/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */
+#define BIT_R_DISABLE_CHECK_VHTSIGA_CRC BIT(5)
-#define BIT_SHIFT_R_WMAC_CTX_SUBTYPE 4
-#define BIT_MASK_R_WMAC_CTX_SUBTYPE 0xf
-#define BIT_R_WMAC_CTX_SUBTYPE(x) (((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE) << BIT_SHIFT_R_WMAC_CTX_SUBTYPE)
-#define BIT_GET_R_WMAC_CTX_SUBTYPE(x) (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE) & BIT_MASK_R_WMAC_CTX_SUBTYPE)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_R_WMAC_RTX_SUBTYPE 0
-#define BIT_MASK_R_WMAC_RTX_SUBTYPE 0xf
-#define BIT_R_WMAC_RTX_SUBTYPE(x) (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE) << BIT_SHIFT_R_WMAC_RTX_SUBTYPE)
-#define BIT_GET_R_WMAC_RTX_SUBTYPE(x) (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE) & BIT_MASK_R_WMAC_RTX_SUBTYPE)
+/* 2 REG_PCIE_CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF (Offset 0x0718) */
+#define BIT_PCIE_CFG_REAL_EN_L1SUB BIT(5)
-/* 2 REG_BT_COEX_V2 (Offset 0x0762) */
+#endif
-#define BIT_GNT_BT_POLARITY BIT(12)
-#define BIT_GNT_BT_BYPASS_PRIORITY BIT(8)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_TIMER 0
-#define BIT_MASK_TIMER 0xff
-#define BIT_TIMER(x) (((x) & BIT_MASK_TIMER) << BIT_SHIFT_TIMER)
-#define BIT_GET_TIMER(x) (((x) >> BIT_SHIFT_TIMER) & BIT_MASK_TIMER)
+/* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */
+#define BIT_R_WMAC_BFPARAM_SEL BIT(4)
+#define BIT_R_WMAC_CSISEQ_SEL BIT(3)
+#define BIT_R_WMAC_CSI_WITHHTC_EN BIT(2)
+#define BIT_R_WMAC_HT_NDPA_EN BIT(1)
+#define BIT_R_WMAC_VHT_NDPA_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_PCIE_CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF (Offset 0x0718) */
+
+#define BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM 0
+#define BIT_MASK_PCIE_CFG_MAX_FUNC_NUM 0x7
+#define BIT_PCIE_CFG_MAX_FUNC_NUM(x) \
+ (((x) & BIT_MASK_PCIE_CFG_MAX_FUNC_NUM) \
+ << BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM)
+#define BITS_PCIE_CFG_MAX_FUNC_NUM \
+ (BIT_MASK_PCIE_CFG_MAX_FUNC_NUM << BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM)
+#define BIT_CLEAR_PCIE_CFG_MAX_FUNC_NUM(x) ((x) & (~BITS_PCIE_CFG_MAX_FUNC_NUM))
+#define BIT_GET_PCIE_CFG_MAX_FUNC_NUM(x) \
+ (((x) >> BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM) & \
+ BIT_MASK_PCIE_CFG_MAX_FUNC_NUM)
+#define BIT_SET_PCIE_CFG_MAX_FUNC_NUM(x, v) \
+ (BIT_CLEAR_PCIE_CFG_MAX_FUNC_NUM(x) | BIT_PCIE_CFG_MAX_FUNC_NUM(v))
+
+/* 2 REG_PCIE_CFG_FORCE_CLKREQ_N_PAD (Offset 0x0719) */
+
+#define BIT_PCIE_CFG_REAL_EN_64BITS BIT(5)
+#define BIT_PCIE_CFG_REAL_EN_CLKREQ BIT(4)
+#define BIT_PCIE_CFG_REAL_EN_L1 BIT(3)
+#define BIT_PCIE_CFG_WAKE_N_EN BIT(2)
+#define BIT_PCIE_CFG_BYPASS_LTR_OPTION BIT(1)
+#define BIT_PCIE_CFG_FORCE_CLKREQ_N_PAD BIT(0)
+
+/* 2 REG_PCIE_CFG_TIMER_MODIFIER_FOR_ACK_NAK_LATENCY (Offset 0x071A) */
+
+#define BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK 0
+#define BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK 0xff
+#define BIT_PCIE_CFG_TIMER_MOD_ACK_NAK(x) \
+ (((x) & BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK) \
+ << BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK)
+#define BITS_PCIE_CFG_TIMER_MOD_ACK_NAK \
+ (BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK \
+ << BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK)
+#define BIT_CLEAR_PCIE_CFG_TIMER_MOD_ACK_NAK(x) \
+ ((x) & (~BITS_PCIE_CFG_TIMER_MOD_ACK_NAK))
+#define BIT_GET_PCIE_CFG_TIMER_MOD_ACK_NAK(x) \
+ (((x) >> BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK) & \
+ BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK)
+#define BIT_SET_PCIE_CFG_TIMER_MOD_ACK_NAK(x, v) \
+ (BIT_CLEAR_PCIE_CFG_TIMER_MOD_ACK_NAK(x) | \
+ BIT_PCIE_CFG_TIMER_MOD_ACK_NAK(v))
+
+/* 2 REG_PCIE_CFG_TIMER_MODIFIER_FOR_FLOW_CONTROL_WATCHDOG (Offset 0x071B) */
+
+#define BIT_PCIE_CFG_BYPASS_L1_SUBSTATE_OPTION BIT(7)
+
+#define BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR 5
+#define BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR 0x3
+#define BIT_PCIE_CFG_FAST_LINK_SCALING_FACTOR(x) \
+ (((x) & BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR) \
+ << BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR)
+#define BITS_PCIE_CFG_FAST_LINK_SCALING_FACTOR \
+ (BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR \
+ << BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR)
+#define BIT_CLEAR_PCIE_CFG_FAST_LINK_SCALING_FACTOR(x) \
+ ((x) & (~BITS_PCIE_CFG_FAST_LINK_SCALING_FACTOR))
+#define BIT_GET_PCIE_CFG_FAST_LINK_SCALING_FACTOR(x) \
+ (((x) >> BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR) & \
+ BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR)
+#define BIT_SET_PCIE_CFG_FAST_LINK_SCALING_FACTOR(x, v) \
+ (BIT_CLEAR_PCIE_CFG_FAST_LINK_SCALING_FACTOR(x) | \
+ BIT_PCIE_CFG_FAST_LINK_SCALING_FACTOR(v))
+
+#define BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER 0
+#define BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER 0x1f
+#define BIT_PCIE_CFG_UPDATE_FREQ_TIMER(x) \
+ (((x) & BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER) \
+ << BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER)
+#define BITS_PCIE_CFG_UPDATE_FREQ_TIMER \
+ (BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER \
+ << BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER)
+#define BIT_CLEAR_PCIE_CFG_UPDATE_FREQ_TIMER(x) \
+ ((x) & (~BITS_PCIE_CFG_UPDATE_FREQ_TIMER))
+#define BIT_GET_PCIE_CFG_UPDATE_FREQ_TIMER(x) \
+ (((x) >> BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER) & \
+ BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER)
+#define BIT_SET_PCIE_CFG_UPDATE_FREQ_TIMER(x, v) \
+ (BIT_CLEAR_PCIE_CFG_UPDATE_FREQ_TIMER(x) | \
+ BIT_PCIE_CFG_UPDATE_FREQ_TIMER(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-/* 2 REG_BT_COEX (Offset 0x0764) */
+/* 2 REG_RX_CSI_RPT_INFO (Offset 0x071C) */
-#define BIT_R_GNT_BT_RFC_SW BIT(12)
-#define BIT_R_GNT_BT_RFC_SW_EN BIT(11)
-#define BIT_R_GNT_BT_BB_SW BIT(10)
-#define BIT_R_GNT_BT_BB_SW_EN BIT(9)
-#define BIT_R_BT_CNT_THREN BIT(8)
+#define BIT_WRITE_ENABLE BIT(31)
-#define BIT_SHIFT_R_BT_CNT_THR 0
-#define BIT_MASK_R_BT_CNT_THR 0xff
-#define BIT_R_BT_CNT_THR(x) (((x) & BIT_MASK_R_BT_CNT_THR) << BIT_SHIFT_R_BT_CNT_THR)
-#define BIT_GET_R_BT_CNT_THR(x) (((x) >> BIT_SHIFT_R_BT_CNT_THR) & BIT_MASK_R_BT_CNT_THR)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_WLAN_ACT_MASK_CTRL (Offset 0x0768) */
+/* 2 REG_RX_CSI_RPT_INFO (Offset 0x071C) */
-#define BIT_WLRX_TER_BY_CTL BIT(43)
-#define BIT_WLRX_TER_BY_AD BIT(42)
-#define BIT_ANT_DIVERSITY_SEL BIT(41)
-#define BIT_ANTSEL_FOR_BT_CTRL_EN BIT(40)
-#define BIT_WLACT_LOW_GNTWL_EN BIT(34)
-#define BIT_WLACT_HIGH_GNTBT_EN BIT(33)
+#define BIT_WMAC_CHECK_SOUNDING_SEQ BIT(30)
+#define BIT_ANTTRN_SWITCH BIT(19)
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_RX_CSI_RPT_INFO (Offset 0x071C) */
+#define BIT_WRITE_USERID BIT(12)
+
+#define BIT_SHIFT_WRITE_BW 10
+#define BIT_MASK_WRITE_BW 0x3
+#define BIT_WRITE_BW(x) (((x) & BIT_MASK_WRITE_BW) << BIT_SHIFT_WRITE_BW)
+#define BITS_WRITE_BW (BIT_MASK_WRITE_BW << BIT_SHIFT_WRITE_BW)
+#define BIT_CLEAR_WRITE_BW(x) ((x) & (~BITS_WRITE_BW))
+#define BIT_GET_WRITE_BW(x) (((x) >> BIT_SHIFT_WRITE_BW) & BIT_MASK_WRITE_BW)
+#define BIT_SET_WRITE_BW(x, v) (BIT_CLEAR_WRITE_BW(x) | BIT_WRITE_BW(v))
+
+#define BIT_SHIFT_WRITE_CB 8
+#define BIT_MASK_WRITE_CB 0x3
+#define BIT_WRITE_CB(x) (((x) & BIT_MASK_WRITE_CB) << BIT_SHIFT_WRITE_CB)
+#define BITS_WRITE_CB (BIT_MASK_WRITE_CB << BIT_SHIFT_WRITE_CB)
+#define BIT_CLEAR_WRITE_CB(x) ((x) & (~BITS_WRITE_CB))
+#define BIT_GET_WRITE_CB(x) (((x) >> BIT_SHIFT_WRITE_CB) & BIT_MASK_WRITE_CB)
+#define BIT_SET_WRITE_CB(x, v) (BIT_CLEAR_WRITE_CB(x) | BIT_WRITE_CB(v))
+
+#define BIT_SHIFT_WRITE_GROUPING 6
+#define BIT_MASK_WRITE_GROUPING 0x3
+#define BIT_WRITE_GROUPING(x) \
+ (((x) & BIT_MASK_WRITE_GROUPING) << BIT_SHIFT_WRITE_GROUPING)
+#define BITS_WRITE_GROUPING \
+ (BIT_MASK_WRITE_GROUPING << BIT_SHIFT_WRITE_GROUPING)
+#define BIT_CLEAR_WRITE_GROUPING(x) ((x) & (~BITS_WRITE_GROUPING))
+#define BIT_GET_WRITE_GROUPING(x) \
+ (((x) >> BIT_SHIFT_WRITE_GROUPING) & BIT_MASK_WRITE_GROUPING)
+#define BIT_SET_WRITE_GROUPING(x, v) \
+ (BIT_CLEAR_WRITE_GROUPING(x) | BIT_WRITE_GROUPING(v))
+
+#define BIT_SHIFT_WRITE_NR 3
+#define BIT_MASK_WRITE_NR 0x7
+#define BIT_WRITE_NR(x) (((x) & BIT_MASK_WRITE_NR) << BIT_SHIFT_WRITE_NR)
+#define BITS_WRITE_NR (BIT_MASK_WRITE_NR << BIT_SHIFT_WRITE_NR)
+#define BIT_CLEAR_WRITE_NR(x) ((x) & (~BITS_WRITE_NR))
+#define BIT_GET_WRITE_NR(x) (((x) >> BIT_SHIFT_WRITE_NR) & BIT_MASK_WRITE_NR)
+#define BIT_SET_WRITE_NR(x, v) (BIT_CLEAR_WRITE_NR(x) | BIT_WRITE_NR(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_WLAN_ACT_MASK_CTRL (Offset 0x0768) */
+/* 2 REG_RX_CSI_RPT_INFO (Offset 0x071C) */
-#define BIT_NAV_UPPER_V1 BIT(32)
+#define BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD 1
+#define BIT_MASK_VHTHT_MIMO_CTRL_FIELD 0xffffff
+#define BIT_VHTHT_MIMO_CTRL_FIELD(x) \
+ (((x) & BIT_MASK_VHTHT_MIMO_CTRL_FIELD) \
+ << BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD)
+#define BITS_VHTHT_MIMO_CTRL_FIELD \
+ (BIT_MASK_VHTHT_MIMO_CTRL_FIELD << BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD)
+#define BIT_CLEAR_VHTHT_MIMO_CTRL_FIELD(x) ((x) & (~BITS_VHTHT_MIMO_CTRL_FIELD))
+#define BIT_GET_VHTHT_MIMO_CTRL_FIELD(x) \
+ (((x) >> BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD) & \
+ BIT_MASK_VHTHT_MIMO_CTRL_FIELD)
+#define BIT_SET_VHTHT_MIMO_CTRL_FIELD(x, v) \
+ (BIT_CLEAR_VHTHT_MIMO_CTRL_FIELD(x) | BIT_VHTHT_MIMO_CTRL_FIELD(v))
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_RX_CSI_RPT_INFO (Offset 0x071C) */
+#define BIT_SHIFT_WRITE_NC 0
+#define BIT_MASK_WRITE_NC 0x7
+#define BIT_WRITE_NC(x) (((x) & BIT_MASK_WRITE_NC) << BIT_SHIFT_WRITE_NC)
+#define BITS_WRITE_NC (BIT_MASK_WRITE_NC << BIT_SHIFT_WRITE_NC)
+#define BIT_CLEAR_WRITE_NC(x) ((x) & (~BITS_WRITE_NC))
+#define BIT_GET_WRITE_NC(x) (((x) >> BIT_SHIFT_WRITE_NC) & BIT_MASK_WRITE_NC)
+#define BIT_SET_WRITE_NC(x, v) (BIT_CLEAR_WRITE_NC(x) | BIT_WRITE_NC(v))
-/* 2 REG_WLAN_ACT_MASK_CTRL (Offset 0x0768) */
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_RXMYRTS_NAV_V1 8
-#define BIT_MASK_RXMYRTS_NAV_V1 0xff
-#define BIT_RXMYRTS_NAV_V1(x) (((x) & BIT_MASK_RXMYRTS_NAV_V1) << BIT_SHIFT_RXMYRTS_NAV_V1)
-#define BIT_GET_RXMYRTS_NAV_V1(x) (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1) & BIT_MASK_RXMYRTS_NAV_V1)
+/* 2 REG_RX_CSI_RPT_INFO (Offset 0x071C) */
+#define BIT_CSI_INTERRUPT_STATUS BIT(0)
-#define BIT_SHIFT_RTSRST_V1 0
-#define BIT_MASK_RTSRST_V1 0xff
-#define BIT_RTSRST_V1(x) (((x) & BIT_MASK_RTSRST_V1) << BIT_SHIFT_RTSRST_V1)
-#define BIT_GET_RTSRST_V1(x) (((x) >> BIT_SHIFT_RTSRST_V1) & BIT_MASK_RTSRST_V1)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_BT_COEX_ENHANCED_INTR_CTRL (Offset 0x076E) */
+/* 2 REG_PCIE_CFG_SKP_INTERVAL_VALUE_L (Offset 0x071C) */
+#define BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L 0
+#define BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L 0xff
+#define BIT_PCIE_CFG_SKP_INTERVAL_VALUE_L(x) \
+ (((x) & BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L) \
+ << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L)
+#define BITS_PCIE_CFG_SKP_INTERVAL_VALUE_L \
+ (BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L \
+ << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L)
+#define BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_L(x) \
+ ((x) & (~BITS_PCIE_CFG_SKP_INTERVAL_VALUE_L))
+#define BIT_GET_PCIE_CFG_SKP_INTERVAL_VALUE_L(x) \
+ (((x) >> BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L) & \
+ BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L)
+#define BIT_SET_PCIE_CFG_SKP_INTERVAL_VALUE_L(x, v) \
+ (BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_L(x) | \
+ BIT_PCIE_CFG_SKP_INTERVAL_VALUE_L(v))
-#define BIT_SHIFT_BT_STAT_DELAY 12
-#define BIT_MASK_BT_STAT_DELAY 0xf
-#define BIT_BT_STAT_DELAY(x) (((x) & BIT_MASK_BT_STAT_DELAY) << BIT_SHIFT_BT_STAT_DELAY)
-#define BIT_GET_BT_STAT_DELAY(x) (((x) >> BIT_SHIFT_BT_STAT_DELAY) & BIT_MASK_BT_STAT_DELAY)
+/* 2 REG_PCIE_CFG_SKP_INTERVAL_VALUE_H (Offset 0x071D) */
+#define BIT_PCIE_CFG_DISABLE_FC_WATCHDOG_TIMER BIT(7)
-#define BIT_SHIFT_BT_TRX_INIT_DETECT 8
-#define BIT_MASK_BT_TRX_INIT_DETECT 0xf
-#define BIT_BT_TRX_INIT_DETECT(x) (((x) & BIT_MASK_BT_TRX_INIT_DETECT) << BIT_SHIFT_BT_TRX_INIT_DETECT)
-#define BIT_GET_BT_TRX_INIT_DETECT(x) (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT) & BIT_MASK_BT_TRX_INIT_DETECT)
+#define BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H 0
+#define BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H 0x7
+#define BIT_PCIE_CFG_SKP_INTERVAL_VALUE_H(x) \
+ (((x) & BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H) \
+ << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H)
+#define BITS_PCIE_CFG_SKP_INTERVAL_VALUE_H \
+ (BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H \
+ << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H)
+#define BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_H(x) \
+ ((x) & (~BITS_PCIE_CFG_SKP_INTERVAL_VALUE_H))
+#define BIT_GET_PCIE_CFG_SKP_INTERVAL_VALUE_H(x) \
+ (((x) >> BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H) & \
+ BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H)
+#define BIT_SET_PCIE_CFG_SKP_INTERVAL_VALUE_H(x, v) \
+ (BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_H(x) | \
+ BIT_PCIE_CFG_SKP_INTERVAL_VALUE_H(v))
+#endif
-#define BIT_SHIFT_BT_PRI_DETECT_TO 4
-#define BIT_MASK_BT_PRI_DETECT_TO 0xf
-#define BIT_BT_PRI_DETECT_TO(x) (((x) & BIT_MASK_BT_PRI_DETECT_TO) << BIT_SHIFT_BT_PRI_DETECT_TO)
-#define BIT_GET_BT_PRI_DETECT_TO(x) (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO) & BIT_MASK_BT_PRI_DETECT_TO)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_R_GRANTALL_WLMASK BIT(3)
-#define BIT_STATIS_BT_EN BIT(2)
-#define BIT_WL_ACT_MASK_ENABLE BIT(1)
-#define BIT_ENHANCED_BT BIT(0)
+/* 2 REG_NS_ARP_CTRL (Offset 0x0720) */
-/* 2 REG_BT_ACT_STATISTICS (Offset 0x0770) */
+#define BIT_R_WMAC_NSARP_RSPEN BIT(15)
+#define BIT_R_WMAC_NSARP_RARP BIT(9)
+#define BIT_R_WMAC_NSARP_RIPV6 BIT(8)
+
+#define BIT_SHIFT_R_WMAC_NSARP_MODEN 6
+#define BIT_MASK_R_WMAC_NSARP_MODEN 0x3
+#define BIT_R_WMAC_NSARP_MODEN(x) \
+ (((x) & BIT_MASK_R_WMAC_NSARP_MODEN) << BIT_SHIFT_R_WMAC_NSARP_MODEN)
+#define BITS_R_WMAC_NSARP_MODEN \
+ (BIT_MASK_R_WMAC_NSARP_MODEN << BIT_SHIFT_R_WMAC_NSARP_MODEN)
+#define BIT_CLEAR_R_WMAC_NSARP_MODEN(x) ((x) & (~BITS_R_WMAC_NSARP_MODEN))
+#define BIT_GET_R_WMAC_NSARP_MODEN(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN) & BIT_MASK_R_WMAC_NSARP_MODEN)
+#define BIT_SET_R_WMAC_NSARP_MODEN(x, v) \
+ (BIT_CLEAR_R_WMAC_NSARP_MODEN(x) | BIT_R_WMAC_NSARP_MODEN(v))
+
+#define BIT_SHIFT_R_WMAC_NSARP_RSPFTP 4
+#define BIT_MASK_R_WMAC_NSARP_RSPFTP 0x3
+#define BIT_R_WMAC_NSARP_RSPFTP(x) \
+ (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP) << BIT_SHIFT_R_WMAC_NSARP_RSPFTP)
+#define BITS_R_WMAC_NSARP_RSPFTP \
+ (BIT_MASK_R_WMAC_NSARP_RSPFTP << BIT_SHIFT_R_WMAC_NSARP_RSPFTP)
+#define BIT_CLEAR_R_WMAC_NSARP_RSPFTP(x) ((x) & (~BITS_R_WMAC_NSARP_RSPFTP))
+#define BIT_GET_R_WMAC_NSARP_RSPFTP(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP) & BIT_MASK_R_WMAC_NSARP_RSPFTP)
+#define BIT_SET_R_WMAC_NSARP_RSPFTP(x, v) \
+ (BIT_CLEAR_R_WMAC_NSARP_RSPFTP(x) | BIT_R_WMAC_NSARP_RSPFTP(v))
+
+#define BIT_SHIFT_R_WMAC_NSARP_RSPSEC 0
+#define BIT_MASK_R_WMAC_NSARP_RSPSEC 0xf
+#define BIT_R_WMAC_NSARP_RSPSEC(x) \
+ (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC) << BIT_SHIFT_R_WMAC_NSARP_RSPSEC)
+#define BITS_R_WMAC_NSARP_RSPSEC \
+ (BIT_MASK_R_WMAC_NSARP_RSPSEC << BIT_SHIFT_R_WMAC_NSARP_RSPSEC)
+#define BIT_CLEAR_R_WMAC_NSARP_RSPSEC(x) ((x) & (~BITS_R_WMAC_NSARP_RSPSEC))
+#define BIT_GET_R_WMAC_NSARP_RSPSEC(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC) & BIT_MASK_R_WMAC_NSARP_RSPSEC)
+#define BIT_SET_R_WMAC_NSARP_RSPSEC(x, v) \
+ (BIT_CLEAR_R_WMAC_NSARP_RSPSEC(x) | BIT_R_WMAC_NSARP_RSPSEC(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+/* 2 REG_NS_ARP_INFO (Offset 0x0724) */
-#define BIT_SHIFT_STATIS_BT_LO_RX (48 & CPU_OPT_WIDTH)
-#define BIT_MASK_STATIS_BT_LO_RX 0xffff
-#define BIT_STATIS_BT_LO_RX(x) (((x) & BIT_MASK_STATIS_BT_LO_RX) << BIT_SHIFT_STATIS_BT_LO_RX)
-#define BIT_GET_STATIS_BT_LO_RX(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_RX) & BIT_MASK_STATIS_BT_LO_RX)
+#define BIT_REQ_IS_MCNS BIT(23)
+#define BIT_REQ_IS_UCNS BIT(22)
+#define BIT_REQ_IS_USNS BIT(21)
+#define BIT_REQ_IS_ARP BIT(20)
+#define BIT_EXPRSP_MH_WITHQC BIT(19)
+
+#define BIT_SHIFT_EXPRSP_SECTYPE 16
+#define BIT_MASK_EXPRSP_SECTYPE 0x7
+#define BIT_EXPRSP_SECTYPE(x) \
+ (((x) & BIT_MASK_EXPRSP_SECTYPE) << BIT_SHIFT_EXPRSP_SECTYPE)
+#define BITS_EXPRSP_SECTYPE \
+ (BIT_MASK_EXPRSP_SECTYPE << BIT_SHIFT_EXPRSP_SECTYPE)
+#define BIT_CLEAR_EXPRSP_SECTYPE(x) ((x) & (~BITS_EXPRSP_SECTYPE))
+#define BIT_GET_EXPRSP_SECTYPE(x) \
+ (((x) >> BIT_SHIFT_EXPRSP_SECTYPE) & BIT_MASK_EXPRSP_SECTYPE)
+#define BIT_SET_EXPRSP_SECTYPE(x, v) \
+ (BIT_CLEAR_EXPRSP_SECTYPE(x) | BIT_EXPRSP_SECTYPE(v))
+
+#define BIT_SHIFT_EXPRSP_CHKSM_7_TO_0 8
+#define BIT_MASK_EXPRSP_CHKSM_7_TO_0 0xff
+#define BIT_EXPRSP_CHKSM_7_TO_0(x) \
+ (((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0) << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0)
+#define BITS_EXPRSP_CHKSM_7_TO_0 \
+ (BIT_MASK_EXPRSP_CHKSM_7_TO_0 << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0)
+#define BIT_CLEAR_EXPRSP_CHKSM_7_TO_0(x) ((x) & (~BITS_EXPRSP_CHKSM_7_TO_0))
+#define BIT_GET_EXPRSP_CHKSM_7_TO_0(x) \
+ (((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0) & BIT_MASK_EXPRSP_CHKSM_7_TO_0)
+#define BIT_SET_EXPRSP_CHKSM_7_TO_0(x, v) \
+ (BIT_CLEAR_EXPRSP_CHKSM_7_TO_0(x) | BIT_EXPRSP_CHKSM_7_TO_0(v))
+
+#define BIT_SHIFT_EXPRSP_CHKSM_15_TO_8 0
+#define BIT_MASK_EXPRSP_CHKSM_15_TO_8 0xff
+#define BIT_EXPRSP_CHKSM_15_TO_8(x) \
+ (((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8) \
+ << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8)
+#define BITS_EXPRSP_CHKSM_15_TO_8 \
+ (BIT_MASK_EXPRSP_CHKSM_15_TO_8 << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8)
+#define BIT_CLEAR_EXPRSP_CHKSM_15_TO_8(x) ((x) & (~BITS_EXPRSP_CHKSM_15_TO_8))
+#define BIT_GET_EXPRSP_CHKSM_15_TO_8(x) \
+ (((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8) & \
+ BIT_MASK_EXPRSP_CHKSM_15_TO_8)
+#define BIT_SET_EXPRSP_CHKSM_15_TO_8(x, v) \
+ (BIT_CLEAR_EXPRSP_CHKSM_15_TO_8(x) | BIT_EXPRSP_CHKSM_15_TO_8(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_PCIE_CFG_L1_UNIT_SEL (Offset 0x0724) */
+
+#define BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL 0
+#define BIT_MASK_PCIE_CFG_L1_UNIT_SEL 0xff
+#define BIT_PCIE_CFG_L1_UNIT_SEL(x) \
+ (((x) & BIT_MASK_PCIE_CFG_L1_UNIT_SEL) \
+ << BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL)
+#define BITS_PCIE_CFG_L1_UNIT_SEL \
+ (BIT_MASK_PCIE_CFG_L1_UNIT_SEL << BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL)
+#define BIT_CLEAR_PCIE_CFG_L1_UNIT_SEL(x) ((x) & (~BITS_PCIE_CFG_L1_UNIT_SEL))
+#define BIT_GET_PCIE_CFG_L1_UNIT_SEL(x) \
+ (((x) >> BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL) & \
+ BIT_MASK_PCIE_CFG_L1_UNIT_SEL)
+#define BIT_SET_PCIE_CFG_L1_UNIT_SEL(x, v) \
+ (BIT_CLEAR_PCIE_CFG_L1_UNIT_SEL(x) | BIT_PCIE_CFG_L1_UNIT_SEL(v))
+
+/* 2 REG_PCIE_CFG_MIN_CLKREQ_SEL (Offset 0x0725) */
+
+#define BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL 0
+#define BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL 0xf
+#define BIT_PCIE_CFG_MIN_CLKREQ_SEL(x) \
+ (((x) & BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL) \
+ << BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL)
+#define BITS_PCIE_CFG_MIN_CLKREQ_SEL \
+ (BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL << BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL)
+#define BIT_CLEAR_PCIE_CFG_MIN_CLKREQ_SEL(x) \
+ ((x) & (~BITS_PCIE_CFG_MIN_CLKREQ_SEL))
+#define BIT_GET_PCIE_CFG_MIN_CLKREQ_SEL(x) \
+ (((x) >> BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL) & \
+ BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL)
+#define BIT_SET_PCIE_CFG_MIN_CLKREQ_SEL(x, v) \
+ (BIT_CLEAR_PCIE_CFG_MIN_CLKREQ_SEL(x) | BIT_PCIE_CFG_MIN_CLKREQ_SEL(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+/* 2 REG_BEAMFORMING_INFO_NSARP_V1 (Offset 0x0728) */
-#define BIT_SHIFT_STATIS_BT_LO_TX (32 & CPU_OPT_WIDTH)
-#define BIT_MASK_STATIS_BT_LO_TX 0xffff
-#define BIT_STATIS_BT_LO_TX(x) (((x) & BIT_MASK_STATIS_BT_LO_TX) << BIT_SHIFT_STATIS_BT_LO_TX)
-#define BIT_GET_STATIS_BT_LO_TX(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_TX) & BIT_MASK_STATIS_BT_LO_TX)
+#define BIT_SHIFT_WMAC_ARPIP 0
+#define BIT_MASK_WMAC_ARPIP 0xffffffffL
+#define BIT_WMAC_ARPIP(x) (((x) & BIT_MASK_WMAC_ARPIP) << BIT_SHIFT_WMAC_ARPIP)
+#define BITS_WMAC_ARPIP (BIT_MASK_WMAC_ARPIP << BIT_SHIFT_WMAC_ARPIP)
+#define BIT_CLEAR_WMAC_ARPIP(x) ((x) & (~BITS_WMAC_ARPIP))
+#define BIT_GET_WMAC_ARPIP(x) \
+ (((x) >> BIT_SHIFT_WMAC_ARPIP) & BIT_MASK_WMAC_ARPIP)
+#define BIT_SET_WMAC_ARPIP(x, v) (BIT_CLEAR_WMAC_ARPIP(x) | BIT_WMAC_ARPIP(v))
+#endif
-#define BIT_SHIFT_STATIS_BT_HI_RX 16
-#define BIT_MASK_STATIS_BT_HI_RX 0xffff
-#define BIT_STATIS_BT_HI_RX(x) (((x) & BIT_MASK_STATIS_BT_HI_RX) << BIT_SHIFT_STATIS_BT_HI_RX)
-#define BIT_GET_STATIS_BT_HI_RX(x) (((x) >> BIT_SHIFT_STATIS_BT_HI_RX) & BIT_MASK_STATIS_BT_HI_RX)
+#if (HALMAC_8822C_SUPPORT)
+/* 2 REG_BEAMFORMING_INFO_NSARP (Offset 0x072C) */
-#define BIT_SHIFT_STATIS_BT_HI_TX 0
-#define BIT_MASK_STATIS_BT_HI_TX 0xffff
-#define BIT_STATIS_BT_HI_TX(x) (((x) & BIT_MASK_STATIS_BT_HI_TX) << BIT_SHIFT_STATIS_BT_HI_TX)
-#define BIT_GET_STATIS_BT_HI_TX(x) (((x) >> BIT_SHIFT_STATIS_BT_HI_TX) & BIT_MASK_STATIS_BT_HI_TX)
+#define BIT_SHIFT_UPD_BFMEE_USERID 13
+#define BIT_MASK_UPD_BFMEE_USERID 0x7
+#define BIT_UPD_BFMEE_USERID(x) \
+ (((x) & BIT_MASK_UPD_BFMEE_USERID) << BIT_SHIFT_UPD_BFMEE_USERID)
+#define BITS_UPD_BFMEE_USERID \
+ (BIT_MASK_UPD_BFMEE_USERID << BIT_SHIFT_UPD_BFMEE_USERID)
+#define BIT_CLEAR_UPD_BFMEE_USERID(x) ((x) & (~BITS_UPD_BFMEE_USERID))
+#define BIT_GET_UPD_BFMEE_USERID(x) \
+ (((x) >> BIT_SHIFT_UPD_BFMEE_USERID) & BIT_MASK_UPD_BFMEE_USERID)
+#define BIT_SET_UPD_BFMEE_USERID(x, v) \
+ (BIT_CLEAR_UPD_BFMEE_USERID(x) | BIT_UPD_BFMEE_USERID(v))
+
+#define BIT_UPD_BFMEE_FBTP BIT(12)
+
+#define BIT_SHIFT_UPD_BFMEE_CB 8
+#define BIT_MASK_UPD_BFMEE_CB 0x3
+#define BIT_UPD_BFMEE_CB(x) \
+ (((x) & BIT_MASK_UPD_BFMEE_CB) << BIT_SHIFT_UPD_BFMEE_CB)
+#define BITS_UPD_BFMEE_CB (BIT_MASK_UPD_BFMEE_CB << BIT_SHIFT_UPD_BFMEE_CB)
+#define BIT_CLEAR_UPD_BFMEE_CB(x) ((x) & (~BITS_UPD_BFMEE_CB))
+#define BIT_GET_UPD_BFMEE_CB(x) \
+ (((x) >> BIT_SHIFT_UPD_BFMEE_CB) & BIT_MASK_UPD_BFMEE_CB)
+#define BIT_SET_UPD_BFMEE_CB(x, v) \
+ (BIT_CLEAR_UPD_BFMEE_CB(x) | BIT_UPD_BFMEE_CB(v))
+
+#define BIT_SHIFT_UPD_BFMEE_NG 6
+#define BIT_MASK_UPD_BFMEE_NG 0x3
+#define BIT_UPD_BFMEE_NG(x) \
+ (((x) & BIT_MASK_UPD_BFMEE_NG) << BIT_SHIFT_UPD_BFMEE_NG)
+#define BITS_UPD_BFMEE_NG (BIT_MASK_UPD_BFMEE_NG << BIT_SHIFT_UPD_BFMEE_NG)
+#define BIT_CLEAR_UPD_BFMEE_NG(x) ((x) & (~BITS_UPD_BFMEE_NG))
+#define BIT_GET_UPD_BFMEE_NG(x) \
+ (((x) >> BIT_SHIFT_UPD_BFMEE_NG) & BIT_MASK_UPD_BFMEE_NG)
+#define BIT_SET_UPD_BFMEE_NG(x, v) \
+ (BIT_CLEAR_UPD_BFMEE_NG(x) | BIT_UPD_BFMEE_NG(v))
+
+#define BIT_SHIFT_UPD_BFMEE_NR 3
+#define BIT_MASK_UPD_BFMEE_NR 0x7
+#define BIT_UPD_BFMEE_NR(x) \
+ (((x) & BIT_MASK_UPD_BFMEE_NR) << BIT_SHIFT_UPD_BFMEE_NR)
+#define BITS_UPD_BFMEE_NR (BIT_MASK_UPD_BFMEE_NR << BIT_SHIFT_UPD_BFMEE_NR)
+#define BIT_CLEAR_UPD_BFMEE_NR(x) ((x) & (~BITS_UPD_BFMEE_NR))
+#define BIT_GET_UPD_BFMEE_NR(x) \
+ (((x) >> BIT_SHIFT_UPD_BFMEE_NR) & BIT_MASK_UPD_BFMEE_NR)
+#define BIT_SET_UPD_BFMEE_NR(x, v) \
+ (BIT_CLEAR_UPD_BFMEE_NR(x) | BIT_UPD_BFMEE_NR(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_BEAMFORMING_INFO_NSARP (Offset 0x072C) */
-/* 2 REG_BT_STATISTICS_CONTROL_REGISTER (Offset 0x0778) */
+#define BIT_SHIFT_BEAMFORMING_INFO 0
+#define BIT_MASK_BEAMFORMING_INFO 0xffffffffL
+#define BIT_BEAMFORMING_INFO(x) \
+ (((x) & BIT_MASK_BEAMFORMING_INFO) << BIT_SHIFT_BEAMFORMING_INFO)
+#define BITS_BEAMFORMING_INFO \
+ (BIT_MASK_BEAMFORMING_INFO << BIT_SHIFT_BEAMFORMING_INFO)
+#define BIT_CLEAR_BEAMFORMING_INFO(x) ((x) & (~BITS_BEAMFORMING_INFO))
+#define BIT_GET_BEAMFORMING_INFO(x) \
+ (((x) >> BIT_SHIFT_BEAMFORMING_INFO) & BIT_MASK_BEAMFORMING_INFO)
+#define BIT_SET_BEAMFORMING_INFO(x, v) \
+ (BIT_CLEAR_BEAMFORMING_INFO(x) | BIT_BEAMFORMING_INFO(v))
+#endif
-#define BIT_SHIFT_R_BT_CMD_RPT 16
-#define BIT_MASK_R_BT_CMD_RPT 0xffff
-#define BIT_R_BT_CMD_RPT(x) (((x) & BIT_MASK_R_BT_CMD_RPT) << BIT_SHIFT_R_BT_CMD_RPT)
-#define BIT_GET_R_BT_CMD_RPT(x) (((x) >> BIT_SHIFT_R_BT_CMD_RPT) & BIT_MASK_R_BT_CMD_RPT)
+#if (HALMAC_8822C_SUPPORT)
+/* 2 REG_BEAMFORMING_INFO_NSARP (Offset 0x072C) */
-#define BIT_SHIFT_R_RPT_FROM_BT 8
-#define BIT_MASK_R_RPT_FROM_BT 0xff
-#define BIT_R_RPT_FROM_BT(x) (((x) & BIT_MASK_R_RPT_FROM_BT) << BIT_SHIFT_R_RPT_FROM_BT)
-#define BIT_GET_R_RPT_FROM_BT(x) (((x) >> BIT_SHIFT_R_RPT_FROM_BT) & BIT_MASK_R_RPT_FROM_BT)
+#define BIT_SHIFT_UPD_BFMEE_BW 0
+#define BIT_MASK_UPD_BFMEE_BW 0xfff
+#define BIT_UPD_BFMEE_BW(x) \
+ (((x) & BIT_MASK_UPD_BFMEE_BW) << BIT_SHIFT_UPD_BFMEE_BW)
+#define BITS_UPD_BFMEE_BW (BIT_MASK_UPD_BFMEE_BW << BIT_SHIFT_UPD_BFMEE_BW)
+#define BIT_CLEAR_UPD_BFMEE_BW(x) ((x) & (~BITS_UPD_BFMEE_BW))
+#define BIT_GET_UPD_BFMEE_BW(x) \
+ (((x) >> BIT_SHIFT_UPD_BFMEE_BW) & BIT_MASK_UPD_BFMEE_BW)
+#define BIT_SET_UPD_BFMEE_BW(x, v) \
+ (BIT_CLEAR_UPD_BFMEE_BW(x) | BIT_UPD_BFMEE_BW(v))
+
+#define BIT_SHIFT_UPD_BFMEE_NC 0
+#define BIT_MASK_UPD_BFMEE_NC 0x7
+#define BIT_UPD_BFMEE_NC(x) \
+ (((x) & BIT_MASK_UPD_BFMEE_NC) << BIT_SHIFT_UPD_BFMEE_NC)
+#define BITS_UPD_BFMEE_NC (BIT_MASK_UPD_BFMEE_NC << BIT_SHIFT_UPD_BFMEE_NC)
+#define BIT_CLEAR_UPD_BFMEE_NC(x) ((x) & (~BITS_UPD_BFMEE_NC))
+#define BIT_GET_UPD_BFMEE_NC(x) \
+ (((x) >> BIT_SHIFT_UPD_BFMEE_NC) & BIT_MASK_UPD_BFMEE_NC)
+#define BIT_SET_UPD_BFMEE_NC(x, v) \
+ (BIT_CLEAR_UPD_BFMEE_NC(x) | BIT_UPD_BFMEE_NC(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_IPV6 (Offset 0x0730) */
+
+#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0 0
+#define BIT_MASK_R_WMAC_IPV6_MYIPAD_0 0xffffffffL
+#define BIT_R_WMAC_IPV6_MYIPAD_0(x) \
+ (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0) \
+ << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0)
+#define BITS_R_WMAC_IPV6_MYIPAD_0 \
+ (BIT_MASK_R_WMAC_IPV6_MYIPAD_0 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0)
+#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0(x) ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_0))
+#define BIT_GET_R_WMAC_IPV6_MYIPAD_0(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0) & \
+ BIT_MASK_R_WMAC_IPV6_MYIPAD_0)
+#define BIT_SET_R_WMAC_IPV6_MYIPAD_0(x, v) \
+ (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0(x) | BIT_R_WMAC_IPV6_MYIPAD_0(v))
+
+/* 2 REG_IPV6_1 (Offset 0x0734) */
+
+#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1 0
+#define BIT_MASK_R_WMAC_IPV6_MYIPAD_1 0xffffffffL
+#define BIT_R_WMAC_IPV6_MYIPAD_1(x) \
+ (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1) \
+ << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1)
+#define BITS_R_WMAC_IPV6_MYIPAD_1 \
+ (BIT_MASK_R_WMAC_IPV6_MYIPAD_1 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1)
+#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1(x) ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_1))
+#define BIT_GET_R_WMAC_IPV6_MYIPAD_1(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1) & \
+ BIT_MASK_R_WMAC_IPV6_MYIPAD_1)
+#define BIT_SET_R_WMAC_IPV6_MYIPAD_1(x, v) \
+ (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1(x) | BIT_R_WMAC_IPV6_MYIPAD_1(v))
+
+/* 2 REG_IPV6_2 (Offset 0x0738) */
+
+#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2 0
+#define BIT_MASK_R_WMAC_IPV6_MYIPAD_2 0xffffffffL
+#define BIT_R_WMAC_IPV6_MYIPAD_2(x) \
+ (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2) \
+ << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2)
+#define BITS_R_WMAC_IPV6_MYIPAD_2 \
+ (BIT_MASK_R_WMAC_IPV6_MYIPAD_2 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2)
+#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2(x) ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_2))
+#define BIT_GET_R_WMAC_IPV6_MYIPAD_2(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2) & \
+ BIT_MASK_R_WMAC_IPV6_MYIPAD_2)
+#define BIT_SET_R_WMAC_IPV6_MYIPAD_2(x, v) \
+ (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2(x) | BIT_R_WMAC_IPV6_MYIPAD_2(v))
+
+/* 2 REG_IPV6_3 (Offset 0x073C) */
+
+#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3 0
+#define BIT_MASK_R_WMAC_IPV6_MYIPAD_3 0xffffffffL
+#define BIT_R_WMAC_IPV6_MYIPAD_3(x) \
+ (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3) \
+ << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3)
+#define BITS_R_WMAC_IPV6_MYIPAD_3 \
+ (BIT_MASK_R_WMAC_IPV6_MYIPAD_3 << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3)
+#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3(x) ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_3))
+#define BIT_GET_R_WMAC_IPV6_MYIPAD_3(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3) & \
+ BIT_MASK_R_WMAC_IPV6_MYIPAD_3)
+#define BIT_SET_R_WMAC_IPV6_MYIPAD_3(x, v) \
+ (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3(x) | BIT_R_WMAC_IPV6_MYIPAD_3(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+/* 2 REG_WMAC_RTX_CTX_SUBTYPE_CFG (Offset 0x0750) */
-#define BIT_SHIFT_BT_HID_ISR_SET 6
-#define BIT_MASK_BT_HID_ISR_SET 0x3
-#define BIT_BT_HID_ISR_SET(x) (((x) & BIT_MASK_BT_HID_ISR_SET) << BIT_SHIFT_BT_HID_ISR_SET)
-#define BIT_GET_BT_HID_ISR_SET(x) (((x) >> BIT_SHIFT_BT_HID_ISR_SET) & BIT_MASK_BT_HID_ISR_SET)
+#define BIT_SHIFT_R_WMAC_CTX_SUBTYPE 4
+#define BIT_MASK_R_WMAC_CTX_SUBTYPE 0xf
+#define BIT_R_WMAC_CTX_SUBTYPE(x) \
+ (((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE) << BIT_SHIFT_R_WMAC_CTX_SUBTYPE)
+#define BITS_R_WMAC_CTX_SUBTYPE \
+ (BIT_MASK_R_WMAC_CTX_SUBTYPE << BIT_SHIFT_R_WMAC_CTX_SUBTYPE)
+#define BIT_CLEAR_R_WMAC_CTX_SUBTYPE(x) ((x) & (~BITS_R_WMAC_CTX_SUBTYPE))
+#define BIT_GET_R_WMAC_CTX_SUBTYPE(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE) & BIT_MASK_R_WMAC_CTX_SUBTYPE)
+#define BIT_SET_R_WMAC_CTX_SUBTYPE(x, v) \
+ (BIT_CLEAR_R_WMAC_CTX_SUBTYPE(x) | BIT_R_WMAC_CTX_SUBTYPE(v))
+
+#define BIT_SHIFT_R_WMAC_RTX_SUBTYPE 0
+#define BIT_MASK_R_WMAC_RTX_SUBTYPE 0xf
+#define BIT_R_WMAC_RTX_SUBTYPE(x) \
+ (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE) << BIT_SHIFT_R_WMAC_RTX_SUBTYPE)
+#define BITS_R_WMAC_RTX_SUBTYPE \
+ (BIT_MASK_R_WMAC_RTX_SUBTYPE << BIT_SHIFT_R_WMAC_RTX_SUBTYPE)
+#define BIT_CLEAR_R_WMAC_RTX_SUBTYPE(x) ((x) & (~BITS_R_WMAC_RTX_SUBTYPE))
+#define BIT_GET_R_WMAC_RTX_SUBTYPE(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE) & BIT_MASK_R_WMAC_RTX_SUBTYPE)
+#define BIT_SET_R_WMAC_RTX_SUBTYPE(x, v) \
+ (BIT_CLEAR_R_WMAC_RTX_SUBTYPE(x) | BIT_R_WMAC_RTX_SUBTYPE(v))
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_SWAES_DIO_B63_B32 (Offset 0x0754) */
+
+#define BIT_SHIFT_WMAC_SWAES_DIO_B63_B32 0
+#define BIT_MASK_WMAC_SWAES_DIO_B63_B32 0xffffffffL
+#define BIT_WMAC_SWAES_DIO_B63_B32(x) \
+ (((x) & BIT_MASK_WMAC_SWAES_DIO_B63_B32) \
+ << BIT_SHIFT_WMAC_SWAES_DIO_B63_B32)
+#define BITS_WMAC_SWAES_DIO_B63_B32 \
+ (BIT_MASK_WMAC_SWAES_DIO_B63_B32 << BIT_SHIFT_WMAC_SWAES_DIO_B63_B32)
+#define BIT_CLEAR_WMAC_SWAES_DIO_B63_B32(x) \
+ ((x) & (~BITS_WMAC_SWAES_DIO_B63_B32))
+#define BIT_GET_WMAC_SWAES_DIO_B63_B32(x) \
+ (((x) >> BIT_SHIFT_WMAC_SWAES_DIO_B63_B32) & \
+ BIT_MASK_WMAC_SWAES_DIO_B63_B32)
+#define BIT_SET_WMAC_SWAES_DIO_B63_B32(x, v) \
+ (BIT_CLEAR_WMAC_SWAES_DIO_B63_B32(x) | BIT_WMAC_SWAES_DIO_B63_B32(v))
+
+/* 2 REG_WMAC_SWAES_DIO_B95_B64 (Offset 0x0758) */
+
+#define BIT_SHIFT_WMAC_SWAES_DIO_B95_B64 0
+#define BIT_MASK_WMAC_SWAES_DIO_B95_B64 0xffffffffL
+#define BIT_WMAC_SWAES_DIO_B95_B64(x) \
+ (((x) & BIT_MASK_WMAC_SWAES_DIO_B95_B64) \
+ << BIT_SHIFT_WMAC_SWAES_DIO_B95_B64)
+#define BITS_WMAC_SWAES_DIO_B95_B64 \
+ (BIT_MASK_WMAC_SWAES_DIO_B95_B64 << BIT_SHIFT_WMAC_SWAES_DIO_B95_B64)
+#define BIT_CLEAR_WMAC_SWAES_DIO_B95_B64(x) \
+ ((x) & (~BITS_WMAC_SWAES_DIO_B95_B64))
+#define BIT_GET_WMAC_SWAES_DIO_B95_B64(x) \
+ (((x) >> BIT_SHIFT_WMAC_SWAES_DIO_B95_B64) & \
+ BIT_MASK_WMAC_SWAES_DIO_B95_B64)
+#define BIT_SET_WMAC_SWAES_DIO_B95_B64(x, v) \
+ (BIT_CLEAR_WMAC_SWAES_DIO_B95_B64(x) | BIT_WMAC_SWAES_DIO_B95_B64(v))
+
+/* 2 REG_WMAC_SWAES_DIO_B127_B96 (Offset 0x075C) */
+
+#define BIT_SHIFT_WMAC_SWAES_DIO_B127_B96 0
+#define BIT_MASK_WMAC_SWAES_DIO_B127_B96 0xffffffffL
+#define BIT_WMAC_SWAES_DIO_B127_B96(x) \
+ (((x) & BIT_MASK_WMAC_SWAES_DIO_B127_B96) \
+ << BIT_SHIFT_WMAC_SWAES_DIO_B127_B96)
+#define BITS_WMAC_SWAES_DIO_B127_B96 \
+ (BIT_MASK_WMAC_SWAES_DIO_B127_B96 << BIT_SHIFT_WMAC_SWAES_DIO_B127_B96)
+#define BIT_CLEAR_WMAC_SWAES_DIO_B127_B96(x) \
+ ((x) & (~BITS_WMAC_SWAES_DIO_B127_B96))
+#define BIT_GET_WMAC_SWAES_DIO_B127_B96(x) \
+ (((x) >> BIT_SHIFT_WMAC_SWAES_DIO_B127_B96) & \
+ BIT_MASK_WMAC_SWAES_DIO_B127_B96)
+#define BIT_SET_WMAC_SWAES_DIO_B127_B96(x, v) \
+ (BIT_CLEAR_WMAC_SWAES_DIO_B127_B96(x) | BIT_WMAC_SWAES_DIO_B127_B96(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_TDMA_BT_START_NOTIFY BIT(5)
-#define BIT_ENABLE_TDMA_FW_MODE BIT(4)
-#define BIT_ENABLE_PTA_TDMA_MODE BIT(3)
-#define BIT_ENABLE_COEXIST_TAB_IN_TDMA BIT(2)
-#define BIT_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA BIT(1)
-#define BIT_RTK_BT_ENABLE BIT(0)
+/* 2 REG_BT_COEX_V2 (Offset 0x0762) */
-/* 2 REG_BT_STATUS_REPORT_REGISTER (Offset 0x077C) */
+#define BIT_GNT_BT_POLARITY BIT(12)
+#define BIT_GNT_BT_BYPASS_PRIORITY BIT(8)
+#define BIT_SHIFT_TIMER 0
+#define BIT_MASK_TIMER 0xff
+#define BIT_TIMER(x) (((x) & BIT_MASK_TIMER) << BIT_SHIFT_TIMER)
+#define BITS_TIMER (BIT_MASK_TIMER << BIT_SHIFT_TIMER)
+#define BIT_CLEAR_TIMER(x) ((x) & (~BITS_TIMER))
+#define BIT_GET_TIMER(x) (((x) >> BIT_SHIFT_TIMER) & BIT_MASK_TIMER)
+#define BIT_SET_TIMER(x, v) (BIT_CLEAR_TIMER(x) | BIT_TIMER(v))
-#define BIT_SHIFT_BT_PROFILE 24
-#define BIT_MASK_BT_PROFILE 0xff
-#define BIT_BT_PROFILE(x) (((x) & BIT_MASK_BT_PROFILE) << BIT_SHIFT_BT_PROFILE)
-#define BIT_GET_BT_PROFILE(x) (((x) >> BIT_SHIFT_BT_PROFILE) & BIT_MASK_BT_PROFILE)
+/* 2 REG_BT_COEX (Offset 0x0764) */
+#define BIT_R_GNT_BT_RFC_SW BIT(12)
+#define BIT_R_GNT_BT_RFC_SW_EN BIT(11)
+#define BIT_R_GNT_BT_BB_SW BIT(10)
+#define BIT_R_GNT_BT_BB_SW_EN BIT(9)
+#define BIT_R_BT_CNT_THREN BIT(8)
-#define BIT_SHIFT_BT_POWER 16
-#define BIT_MASK_BT_POWER 0xff
-#define BIT_BT_POWER(x) (((x) & BIT_MASK_BT_POWER) << BIT_SHIFT_BT_POWER)
-#define BIT_GET_BT_POWER(x) (((x) >> BIT_SHIFT_BT_POWER) & BIT_MASK_BT_POWER)
+#define BIT_SHIFT_R_BT_CNT_THR 0
+#define BIT_MASK_R_BT_CNT_THR 0xff
+#define BIT_R_BT_CNT_THR(x) \
+ (((x) & BIT_MASK_R_BT_CNT_THR) << BIT_SHIFT_R_BT_CNT_THR)
+#define BITS_R_BT_CNT_THR (BIT_MASK_R_BT_CNT_THR << BIT_SHIFT_R_BT_CNT_THR)
+#define BIT_CLEAR_R_BT_CNT_THR(x) ((x) & (~BITS_R_BT_CNT_THR))
+#define BIT_GET_R_BT_CNT_THR(x) \
+ (((x) >> BIT_SHIFT_R_BT_CNT_THR) & BIT_MASK_R_BT_CNT_THR)
+#define BIT_SET_R_BT_CNT_THR(x, v) \
+ (BIT_CLEAR_R_BT_CNT_THR(x) | BIT_R_BT_CNT_THR(v))
+#endif
-#define BIT_SHIFT_BT_PREDECT_STATUS 8
-#define BIT_MASK_BT_PREDECT_STATUS 0xff
-#define BIT_BT_PREDECT_STATUS(x) (((x) & BIT_MASK_BT_PREDECT_STATUS) << BIT_SHIFT_BT_PREDECT_STATUS)
-#define BIT_GET_BT_PREDECT_STATUS(x) (((x) >> BIT_SHIFT_BT_PREDECT_STATUS) & BIT_MASK_BT_PREDECT_STATUS)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_WLAN_ACT_MASK_CTRL (Offset 0x0768) */
-#define BIT_SHIFT_BT_CMD_INFO 0
-#define BIT_MASK_BT_CMD_INFO 0xff
-#define BIT_BT_CMD_INFO(x) (((x) & BIT_MASK_BT_CMD_INFO) << BIT_SHIFT_BT_CMD_INFO)
-#define BIT_GET_BT_CMD_INFO(x) (((x) >> BIT_SHIFT_BT_CMD_INFO) & BIT_MASK_BT_CMD_INFO)
+#define BIT_WLRX_TER_BY_CTL BIT(43)
+#define BIT_WLRX_TER_BY_AD BIT(42)
+#define BIT_ANT_DIVERSITY_SEL BIT(41)
+#define BIT_ANTSEL_FOR_BT_CTRL_EN BIT(40)
+#define BIT_WLACT_LOW_GNTWL_EN BIT(34)
+#define BIT_WLACT_HIGH_GNTBT_EN BIT(33)
+#endif
-/* 2 REG_BT_INTERRUPT_CONTROL_REGISTER (Offset 0x0780) */
+#if (HALMAC_8822B_SUPPORT)
-#define BIT_EN_MAC_NULL_PKT_NOTIFY BIT(31)
-#define BIT_EN_WLAN_RPT_AND_BT_QUERY BIT(30)
-#define BIT_EN_BT_STSTUS_RPT BIT(29)
-#define BIT_EN_BT_POWER BIT(28)
-#define BIT_EN_BT_CHANNEL BIT(27)
-#define BIT_EN_BT_SLOT_CHANGE BIT(26)
-#define BIT_EN_BT_PROFILE_OR_HID BIT(25)
-#define BIT_WLAN_RPT_NOTIFY BIT(24)
+/* 2 REG_WLAN_ACT_MASK_CTRL (Offset 0x0768) */
-#define BIT_SHIFT_WLAN_RPT_DATA 16
-#define BIT_MASK_WLAN_RPT_DATA 0xff
-#define BIT_WLAN_RPT_DATA(x) (((x) & BIT_MASK_WLAN_RPT_DATA) << BIT_SHIFT_WLAN_RPT_DATA)
-#define BIT_GET_WLAN_RPT_DATA(x) (((x) >> BIT_SHIFT_WLAN_RPT_DATA) & BIT_MASK_WLAN_RPT_DATA)
+#define BIT_NAV_UPPER_V1 BIT(32)
+#endif
-#define BIT_SHIFT_CMD_ID 8
-#define BIT_MASK_CMD_ID 0xff
-#define BIT_CMD_ID(x) (((x) & BIT_MASK_CMD_ID) << BIT_SHIFT_CMD_ID)
-#define BIT_GET_CMD_ID(x) (((x) >> BIT_SHIFT_CMD_ID) & BIT_MASK_CMD_ID)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+/* 2 REG_WLAN_ACT_MASK_CTRL (Offset 0x0768) */
-#define BIT_SHIFT_BT_DATA 0
-#define BIT_MASK_BT_DATA 0xff
-#define BIT_BT_DATA(x) (((x) & BIT_MASK_BT_DATA) << BIT_SHIFT_BT_DATA)
-#define BIT_GET_BT_DATA(x) (((x) >> BIT_SHIFT_BT_DATA) & BIT_MASK_BT_DATA)
+#define BIT_SHIFT_RXMYRTS_NAV_V1 8
+#define BIT_MASK_RXMYRTS_NAV_V1 0xff
+#define BIT_RXMYRTS_NAV_V1(x) \
+ (((x) & BIT_MASK_RXMYRTS_NAV_V1) << BIT_SHIFT_RXMYRTS_NAV_V1)
+#define BITS_RXMYRTS_NAV_V1 \
+ (BIT_MASK_RXMYRTS_NAV_V1 << BIT_SHIFT_RXMYRTS_NAV_V1)
+#define BIT_CLEAR_RXMYRTS_NAV_V1(x) ((x) & (~BITS_RXMYRTS_NAV_V1))
+#define BIT_GET_RXMYRTS_NAV_V1(x) \
+ (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1) & BIT_MASK_RXMYRTS_NAV_V1)
+#define BIT_SET_RXMYRTS_NAV_V1(x, v) \
+ (BIT_CLEAR_RXMYRTS_NAV_V1(x) | BIT_RXMYRTS_NAV_V1(v))
+#define BIT_SHIFT_RTSRST_V1 0
+#define BIT_MASK_RTSRST_V1 0xff
+#define BIT_RTSRST_V1(x) (((x) & BIT_MASK_RTSRST_V1) << BIT_SHIFT_RTSRST_V1)
+#define BITS_RTSRST_V1 (BIT_MASK_RTSRST_V1 << BIT_SHIFT_RTSRST_V1)
+#define BIT_CLEAR_RTSRST_V1(x) ((x) & (~BITS_RTSRST_V1))
+#define BIT_GET_RTSRST_V1(x) (((x) >> BIT_SHIFT_RTSRST_V1) & BIT_MASK_RTSRST_V1)
+#define BIT_SET_RTSRST_V1(x, v) (BIT_CLEAR_RTSRST_V1(x) | BIT_RTSRST_V1(v))
-/* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER (Offset 0x0784) */
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_WLAN_RPT_TO 0
-#define BIT_MASK_WLAN_RPT_TO 0xff
-#define BIT_WLAN_RPT_TO(x) (((x) & BIT_MASK_WLAN_RPT_TO) << BIT_SHIFT_WLAN_RPT_TO)
-#define BIT_GET_WLAN_RPT_TO(x) (((x) >> BIT_SHIFT_WLAN_RPT_TO) & BIT_MASK_WLAN_RPT_TO)
+/* 2 REG_WLAN_ACT_MASK_CTRL_1 (Offset 0x076C) */
+#define BIT_WLRX_TER_BY_CTL_1 BIT(11)
+#define BIT_WLRX_TER_BY_AD_1 BIT(10)
+#define BIT_ANT_DIVERSITY_SEL_1 BIT(9)
+#define BIT_ANTSEL_FOR_BT_CTRL_EN_1 BIT(8)
+#define BIT_WLACT_LOW_GNTWL_EN_1 BIT(2)
+#define BIT_WLACT_HIGH_GNTBT_EN_1 BIT(1)
+#define BIT_NAV_UPPER_1_V1 BIT(0)
-/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER (Offset 0x0785) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_ISOLATION_CHK 1
-#define BIT_MASK_ISOLATION_CHK 0x7fffffffffffffffffffL
-#define BIT_ISOLATION_CHK(x) (((x) & BIT_MASK_ISOLATION_CHK) << BIT_SHIFT_ISOLATION_CHK)
-#define BIT_GET_ISOLATION_CHK(x) (((x) >> BIT_SHIFT_ISOLATION_CHK) & BIT_MASK_ISOLATION_CHK)
+/* 2 REG_BT_COEX_ENHANCED_INTR_CTRL (Offset 0x076E) */
-#define BIT_ISOLATION_EN BIT(0)
+#define BIT_SHIFT_BT_STAT_DELAY 12
+#define BIT_MASK_BT_STAT_DELAY 0xf
+#define BIT_BT_STAT_DELAY(x) \
+ (((x) & BIT_MASK_BT_STAT_DELAY) << BIT_SHIFT_BT_STAT_DELAY)
+#define BITS_BT_STAT_DELAY (BIT_MASK_BT_STAT_DELAY << BIT_SHIFT_BT_STAT_DELAY)
+#define BIT_CLEAR_BT_STAT_DELAY(x) ((x) & (~BITS_BT_STAT_DELAY))
+#define BIT_GET_BT_STAT_DELAY(x) \
+ (((x) >> BIT_SHIFT_BT_STAT_DELAY) & BIT_MASK_BT_STAT_DELAY)
+#define BIT_SET_BT_STAT_DELAY(x, v) \
+ (BIT_CLEAR_BT_STAT_DELAY(x) | BIT_BT_STAT_DELAY(v))
+
+#define BIT_SHIFT_BT_TRX_INIT_DETECT 8
+#define BIT_MASK_BT_TRX_INIT_DETECT 0xf
+#define BIT_BT_TRX_INIT_DETECT(x) \
+ (((x) & BIT_MASK_BT_TRX_INIT_DETECT) << BIT_SHIFT_BT_TRX_INIT_DETECT)
+#define BITS_BT_TRX_INIT_DETECT \
+ (BIT_MASK_BT_TRX_INIT_DETECT << BIT_SHIFT_BT_TRX_INIT_DETECT)
+#define BIT_CLEAR_BT_TRX_INIT_DETECT(x) ((x) & (~BITS_BT_TRX_INIT_DETECT))
+#define BIT_GET_BT_TRX_INIT_DETECT(x) \
+ (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT) & BIT_MASK_BT_TRX_INIT_DETECT)
+#define BIT_SET_BT_TRX_INIT_DETECT(x, v) \
+ (BIT_CLEAR_BT_TRX_INIT_DETECT(x) | BIT_BT_TRX_INIT_DETECT(v))
+
+#define BIT_SHIFT_BT_PRI_DETECT_TO 4
+#define BIT_MASK_BT_PRI_DETECT_TO 0xf
+#define BIT_BT_PRI_DETECT_TO(x) \
+ (((x) & BIT_MASK_BT_PRI_DETECT_TO) << BIT_SHIFT_BT_PRI_DETECT_TO)
+#define BITS_BT_PRI_DETECT_TO \
+ (BIT_MASK_BT_PRI_DETECT_TO << BIT_SHIFT_BT_PRI_DETECT_TO)
+#define BIT_CLEAR_BT_PRI_DETECT_TO(x) ((x) & (~BITS_BT_PRI_DETECT_TO))
+#define BIT_GET_BT_PRI_DETECT_TO(x) \
+ (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO) & BIT_MASK_BT_PRI_DETECT_TO)
+#define BIT_SET_BT_PRI_DETECT_TO(x, v) \
+ (BIT_CLEAR_BT_PRI_DETECT_TO(x) | BIT_BT_PRI_DETECT_TO(v))
+
+#define BIT_R_GRANTALL_WLMASK BIT(3)
+#define BIT_STATIS_BT_EN BIT(2)
+#define BIT_WL_ACT_MASK_ENABLE BIT(1)
+#define BIT_ENHANCED_BT BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
-/* 2 REG_BT_INTERRUPT_STATUS_REGISTER (Offset 0x078F) */
+/* 2 REG_BT_ACT_STATISTICS (Offset 0x0770) */
-#define BIT_BT_HID_ISR BIT(7)
-#define BIT_BT_QUERY_ISR BIT(6)
-#define BIT_MAC_NULL_PKT_NOTIFY_ISR BIT(5)
-#define BIT_WLAN_RPT_ISR BIT(4)
-#define BIT_BT_POWER_ISR BIT(3)
-#define BIT_BT_CHANNEL_ISR BIT(2)
-#define BIT_BT_SLOT_CHANGE_ISR BIT(1)
-#define BIT_BT_PROFILE_ISR BIT(0)
+#define BIT_SHIFT_STATIS_BT_LO_RX (48 & CPU_OPT_WIDTH)
+#define BIT_MASK_STATIS_BT_LO_RX 0xffff
+#define BIT_STATIS_BT_LO_RX(x) \
+ (((x) & BIT_MASK_STATIS_BT_LO_RX) << BIT_SHIFT_STATIS_BT_LO_RX)
+#define BITS_STATIS_BT_LO_RX \
+ (BIT_MASK_STATIS_BT_LO_RX << BIT_SHIFT_STATIS_BT_LO_RX)
+#define BIT_CLEAR_STATIS_BT_LO_RX(x) ((x) & (~BITS_STATIS_BT_LO_RX))
+#define BIT_GET_STATIS_BT_LO_RX(x) \
+ (((x) >> BIT_SHIFT_STATIS_BT_LO_RX) & BIT_MASK_STATIS_BT_LO_RX)
+#define BIT_SET_STATIS_BT_LO_RX(x, v) \
+ (BIT_CLEAR_STATIS_BT_LO_RX(x) | BIT_STATIS_BT_LO_RX(v))
+
+#define BIT_SHIFT_STATIS_BT_LO_TX (32 & CPU_OPT_WIDTH)
+#define BIT_MASK_STATIS_BT_LO_TX 0xffff
+#define BIT_STATIS_BT_LO_TX(x) \
+ (((x) & BIT_MASK_STATIS_BT_LO_TX) << BIT_SHIFT_STATIS_BT_LO_TX)
+#define BITS_STATIS_BT_LO_TX \
+ (BIT_MASK_STATIS_BT_LO_TX << BIT_SHIFT_STATIS_BT_LO_TX)
+#define BIT_CLEAR_STATIS_BT_LO_TX(x) ((x) & (~BITS_STATIS_BT_LO_TX))
+#define BIT_GET_STATIS_BT_LO_TX(x) \
+ (((x) >> BIT_SHIFT_STATIS_BT_LO_TX) & BIT_MASK_STATIS_BT_LO_TX)
+#define BIT_SET_STATIS_BT_LO_TX(x, v) \
+ (BIT_CLEAR_STATIS_BT_LO_TX(x) | BIT_STATIS_BT_LO_TX(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_BT_TDMA_TIME_REGISTER (Offset 0x0790) */
+/* 2 REG_BT_ACT_STATISTICS (Offset 0x0770) */
+#define BIT_SHIFT_STATIS_BT_HI_RX 16
+#define BIT_MASK_STATIS_BT_HI_RX 0xffff
+#define BIT_STATIS_BT_HI_RX(x) \
+ (((x) & BIT_MASK_STATIS_BT_HI_RX) << BIT_SHIFT_STATIS_BT_HI_RX)
+#define BITS_STATIS_BT_HI_RX \
+ (BIT_MASK_STATIS_BT_HI_RX << BIT_SHIFT_STATIS_BT_HI_RX)
+#define BIT_CLEAR_STATIS_BT_HI_RX(x) ((x) & (~BITS_STATIS_BT_HI_RX))
+#define BIT_GET_STATIS_BT_HI_RX(x) \
+ (((x) >> BIT_SHIFT_STATIS_BT_HI_RX) & BIT_MASK_STATIS_BT_HI_RX)
+#define BIT_SET_STATIS_BT_HI_RX(x, v) \
+ (BIT_CLEAR_STATIS_BT_HI_RX(x) | BIT_STATIS_BT_HI_RX(v))
+
+#define BIT_SHIFT_STATIS_BT_HI_TX 0
+#define BIT_MASK_STATIS_BT_HI_TX 0xffff
+#define BIT_STATIS_BT_HI_TX(x) \
+ (((x) & BIT_MASK_STATIS_BT_HI_TX) << BIT_SHIFT_STATIS_BT_HI_TX)
+#define BITS_STATIS_BT_HI_TX \
+ (BIT_MASK_STATIS_BT_HI_TX << BIT_SHIFT_STATIS_BT_HI_TX)
+#define BIT_CLEAR_STATIS_BT_HI_TX(x) ((x) & (~BITS_STATIS_BT_HI_TX))
+#define BIT_GET_STATIS_BT_HI_TX(x) \
+ (((x) >> BIT_SHIFT_STATIS_BT_HI_TX) & BIT_MASK_STATIS_BT_HI_TX)
+#define BIT_SET_STATIS_BT_HI_TX(x, v) \
+ (BIT_CLEAR_STATIS_BT_HI_TX(x) | BIT_STATIS_BT_HI_TX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_BT_ACT_STATISTICS_1 (Offset 0x0774) */
+
+#define BIT_SHIFT_STATIS_BT_LO_RX_1 16
+#define BIT_MASK_STATIS_BT_LO_RX_1 0xffff
+#define BIT_STATIS_BT_LO_RX_1(x) \
+ (((x) & BIT_MASK_STATIS_BT_LO_RX_1) << BIT_SHIFT_STATIS_BT_LO_RX_1)
+#define BITS_STATIS_BT_LO_RX_1 \
+ (BIT_MASK_STATIS_BT_LO_RX_1 << BIT_SHIFT_STATIS_BT_LO_RX_1)
+#define BIT_CLEAR_STATIS_BT_LO_RX_1(x) ((x) & (~BITS_STATIS_BT_LO_RX_1))
+#define BIT_GET_STATIS_BT_LO_RX_1(x) \
+ (((x) >> BIT_SHIFT_STATIS_BT_LO_RX_1) & BIT_MASK_STATIS_BT_LO_RX_1)
+#define BIT_SET_STATIS_BT_LO_RX_1(x, v) \
+ (BIT_CLEAR_STATIS_BT_LO_RX_1(x) | BIT_STATIS_BT_LO_RX_1(v))
+
+#define BIT_SHIFT_STATIS_BT_LO_TX_1 0
+#define BIT_MASK_STATIS_BT_LO_TX_1 0xffff
+#define BIT_STATIS_BT_LO_TX_1(x) \
+ (((x) & BIT_MASK_STATIS_BT_LO_TX_1) << BIT_SHIFT_STATIS_BT_LO_TX_1)
+#define BITS_STATIS_BT_LO_TX_1 \
+ (BIT_MASK_STATIS_BT_LO_TX_1 << BIT_SHIFT_STATIS_BT_LO_TX_1)
+#define BIT_CLEAR_STATIS_BT_LO_TX_1(x) ((x) & (~BITS_STATIS_BT_LO_TX_1))
+#define BIT_GET_STATIS_BT_LO_TX_1(x) \
+ (((x) >> BIT_SHIFT_STATIS_BT_LO_TX_1) & BIT_MASK_STATIS_BT_LO_TX_1)
+#define BIT_SET_STATIS_BT_LO_TX_1(x, v) \
+ (BIT_CLEAR_STATIS_BT_LO_TX_1(x) | BIT_STATIS_BT_LO_TX_1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_BT_TIME 6
-#define BIT_MASK_BT_TIME 0x3ffffff
-#define BIT_BT_TIME(x) (((x) & BIT_MASK_BT_TIME) << BIT_SHIFT_BT_TIME)
-#define BIT_GET_BT_TIME(x) (((x) >> BIT_SHIFT_BT_TIME) & BIT_MASK_BT_TIME)
+/* 2 REG_BT_STATISTICS_CONTROL_REGISTER (Offset 0x0778) */
+#define BIT_SHIFT_R_BT_CMD_RPT 16
+#define BIT_MASK_R_BT_CMD_RPT 0xffff
+#define BIT_R_BT_CMD_RPT(x) \
+ (((x) & BIT_MASK_R_BT_CMD_RPT) << BIT_SHIFT_R_BT_CMD_RPT)
+#define BITS_R_BT_CMD_RPT (BIT_MASK_R_BT_CMD_RPT << BIT_SHIFT_R_BT_CMD_RPT)
+#define BIT_CLEAR_R_BT_CMD_RPT(x) ((x) & (~BITS_R_BT_CMD_RPT))
+#define BIT_GET_R_BT_CMD_RPT(x) \
+ (((x) >> BIT_SHIFT_R_BT_CMD_RPT) & BIT_MASK_R_BT_CMD_RPT)
+#define BIT_SET_R_BT_CMD_RPT(x, v) \
+ (BIT_CLEAR_R_BT_CMD_RPT(x) | BIT_R_BT_CMD_RPT(v))
+
+#define BIT_SHIFT_R_RPT_FROM_BT 8
+#define BIT_MASK_R_RPT_FROM_BT 0xff
+#define BIT_R_RPT_FROM_BT(x) \
+ (((x) & BIT_MASK_R_RPT_FROM_BT) << BIT_SHIFT_R_RPT_FROM_BT)
+#define BITS_R_RPT_FROM_BT (BIT_MASK_R_RPT_FROM_BT << BIT_SHIFT_R_RPT_FROM_BT)
+#define BIT_CLEAR_R_RPT_FROM_BT(x) ((x) & (~BITS_R_RPT_FROM_BT))
+#define BIT_GET_R_RPT_FROM_BT(x) \
+ (((x) >> BIT_SHIFT_R_RPT_FROM_BT) & BIT_MASK_R_RPT_FROM_BT)
+#define BIT_SET_R_RPT_FROM_BT(x, v) \
+ (BIT_CLEAR_R_RPT_FROM_BT(x) | BIT_R_RPT_FROM_BT(v))
+
+#define BIT_SHIFT_BT_HID_ISR_SET 6
+#define BIT_MASK_BT_HID_ISR_SET 0x3
+#define BIT_BT_HID_ISR_SET(x) \
+ (((x) & BIT_MASK_BT_HID_ISR_SET) << BIT_SHIFT_BT_HID_ISR_SET)
+#define BITS_BT_HID_ISR_SET \
+ (BIT_MASK_BT_HID_ISR_SET << BIT_SHIFT_BT_HID_ISR_SET)
+#define BIT_CLEAR_BT_HID_ISR_SET(x) ((x) & (~BITS_BT_HID_ISR_SET))
+#define BIT_GET_BT_HID_ISR_SET(x) \
+ (((x) >> BIT_SHIFT_BT_HID_ISR_SET) & BIT_MASK_BT_HID_ISR_SET)
+#define BIT_SET_BT_HID_ISR_SET(x, v) \
+ (BIT_CLEAR_BT_HID_ISR_SET(x) | BIT_BT_HID_ISR_SET(v))
+
+#define BIT_TDMA_BT_START_NOTIFY BIT(5)
+#define BIT_ENABLE_TDMA_FW_MODE BIT(4)
+#define BIT_ENABLE_PTA_TDMA_MODE BIT(3)
+#define BIT_ENABLE_COEXIST_TAB_IN_TDMA BIT(2)
+#define BIT_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA BIT(1)
+#define BIT_RTK_BT_ENABLE BIT(0)
-#define BIT_SHIFT_BT_RPT_SAMPLE_RATE 0
-#define BIT_MASK_BT_RPT_SAMPLE_RATE 0x3f
-#define BIT_BT_RPT_SAMPLE_RATE(x) (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE) << BIT_SHIFT_BT_RPT_SAMPLE_RATE)
-#define BIT_GET_BT_RPT_SAMPLE_RATE(x) (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE) & BIT_MASK_BT_RPT_SAMPLE_RATE)
+/* 2 REG_BT_STATUS_REPORT_REGISTER (Offset 0x077C) */
+#define BIT_SHIFT_BT_PROFILE 24
+#define BIT_MASK_BT_PROFILE 0xff
+#define BIT_BT_PROFILE(x) (((x) & BIT_MASK_BT_PROFILE) << BIT_SHIFT_BT_PROFILE)
+#define BITS_BT_PROFILE (BIT_MASK_BT_PROFILE << BIT_SHIFT_BT_PROFILE)
+#define BIT_CLEAR_BT_PROFILE(x) ((x) & (~BITS_BT_PROFILE))
+#define BIT_GET_BT_PROFILE(x) \
+ (((x) >> BIT_SHIFT_BT_PROFILE) & BIT_MASK_BT_PROFILE)
+#define BIT_SET_BT_PROFILE(x, v) (BIT_CLEAR_BT_PROFILE(x) | BIT_BT_PROFILE(v))
+
+#define BIT_SHIFT_BT_POWER 16
+#define BIT_MASK_BT_POWER 0xff
+#define BIT_BT_POWER(x) (((x) & BIT_MASK_BT_POWER) << BIT_SHIFT_BT_POWER)
+#define BITS_BT_POWER (BIT_MASK_BT_POWER << BIT_SHIFT_BT_POWER)
+#define BIT_CLEAR_BT_POWER(x) ((x) & (~BITS_BT_POWER))
+#define BIT_GET_BT_POWER(x) (((x) >> BIT_SHIFT_BT_POWER) & BIT_MASK_BT_POWER)
+#define BIT_SET_BT_POWER(x, v) (BIT_CLEAR_BT_POWER(x) | BIT_BT_POWER(v))
+
+#define BIT_SHIFT_BT_PREDECT_STATUS 8
+#define BIT_MASK_BT_PREDECT_STATUS 0xff
+#define BIT_BT_PREDECT_STATUS(x) \
+ (((x) & BIT_MASK_BT_PREDECT_STATUS) << BIT_SHIFT_BT_PREDECT_STATUS)
+#define BITS_BT_PREDECT_STATUS \
+ (BIT_MASK_BT_PREDECT_STATUS << BIT_SHIFT_BT_PREDECT_STATUS)
+#define BIT_CLEAR_BT_PREDECT_STATUS(x) ((x) & (~BITS_BT_PREDECT_STATUS))
+#define BIT_GET_BT_PREDECT_STATUS(x) \
+ (((x) >> BIT_SHIFT_BT_PREDECT_STATUS) & BIT_MASK_BT_PREDECT_STATUS)
+#define BIT_SET_BT_PREDECT_STATUS(x, v) \
+ (BIT_CLEAR_BT_PREDECT_STATUS(x) | BIT_BT_PREDECT_STATUS(v))
+
+#define BIT_SHIFT_BT_CMD_INFO 0
+#define BIT_MASK_BT_CMD_INFO 0xff
+#define BIT_BT_CMD_INFO(x) \
+ (((x) & BIT_MASK_BT_CMD_INFO) << BIT_SHIFT_BT_CMD_INFO)
+#define BITS_BT_CMD_INFO (BIT_MASK_BT_CMD_INFO << BIT_SHIFT_BT_CMD_INFO)
+#define BIT_CLEAR_BT_CMD_INFO(x) ((x) & (~BITS_BT_CMD_INFO))
+#define BIT_GET_BT_CMD_INFO(x) \
+ (((x) >> BIT_SHIFT_BT_CMD_INFO) & BIT_MASK_BT_CMD_INFO)
+#define BIT_SET_BT_CMD_INFO(x, v) \
+ (BIT_CLEAR_BT_CMD_INFO(x) | BIT_BT_CMD_INFO(v))
-/* 2 REG_BT_ACT_REGISTER (Offset 0x0794) */
+/* 2 REG_BT_INTERRUPT_CONTROL_REGISTER (Offset 0x0780) */
+#define BIT_EN_MAC_NULL_PKT_NOTIFY BIT(31)
+#define BIT_EN_WLAN_RPT_AND_BT_QUERY BIT(30)
+#define BIT_EN_BT_STSTUS_RPT BIT(29)
+#define BIT_EN_BT_POWER BIT(28)
+#define BIT_EN_BT_CHANNEL BIT(27)
+#define BIT_EN_BT_SLOT_CHANGE BIT(26)
+#define BIT_EN_BT_PROFILE_OR_HID BIT(25)
+#define BIT_WLAN_RPT_NOTIFY BIT(24)
+
+#define BIT_SHIFT_WLAN_RPT_DATA 16
+#define BIT_MASK_WLAN_RPT_DATA 0xff
+#define BIT_WLAN_RPT_DATA(x) \
+ (((x) & BIT_MASK_WLAN_RPT_DATA) << BIT_SHIFT_WLAN_RPT_DATA)
+#define BITS_WLAN_RPT_DATA (BIT_MASK_WLAN_RPT_DATA << BIT_SHIFT_WLAN_RPT_DATA)
+#define BIT_CLEAR_WLAN_RPT_DATA(x) ((x) & (~BITS_WLAN_RPT_DATA))
+#define BIT_GET_WLAN_RPT_DATA(x) \
+ (((x) >> BIT_SHIFT_WLAN_RPT_DATA) & BIT_MASK_WLAN_RPT_DATA)
+#define BIT_SET_WLAN_RPT_DATA(x, v) \
+ (BIT_CLEAR_WLAN_RPT_DATA(x) | BIT_WLAN_RPT_DATA(v))
+
+#define BIT_SHIFT_CMD_ID 8
+#define BIT_MASK_CMD_ID 0xff
+#define BIT_CMD_ID(x) (((x) & BIT_MASK_CMD_ID) << BIT_SHIFT_CMD_ID)
+#define BITS_CMD_ID (BIT_MASK_CMD_ID << BIT_SHIFT_CMD_ID)
+#define BIT_CLEAR_CMD_ID(x) ((x) & (~BITS_CMD_ID))
+#define BIT_GET_CMD_ID(x) (((x) >> BIT_SHIFT_CMD_ID) & BIT_MASK_CMD_ID)
+#define BIT_SET_CMD_ID(x, v) (BIT_CLEAR_CMD_ID(x) | BIT_CMD_ID(v))
+
+#define BIT_SHIFT_BT_DATA 0
+#define BIT_MASK_BT_DATA 0xff
+#define BIT_BT_DATA(x) (((x) & BIT_MASK_BT_DATA) << BIT_SHIFT_BT_DATA)
+#define BITS_BT_DATA (BIT_MASK_BT_DATA << BIT_SHIFT_BT_DATA)
+#define BIT_CLEAR_BT_DATA(x) ((x) & (~BITS_BT_DATA))
+#define BIT_GET_BT_DATA(x) (((x) >> BIT_SHIFT_BT_DATA) & BIT_MASK_BT_DATA)
+#define BIT_SET_BT_DATA(x, v) (BIT_CLEAR_BT_DATA(x) | BIT_BT_DATA(v))
-#define BIT_SHIFT_BT_EISR_EN 16
-#define BIT_MASK_BT_EISR_EN 0xff
-#define BIT_BT_EISR_EN(x) (((x) & BIT_MASK_BT_EISR_EN) << BIT_SHIFT_BT_EISR_EN)
-#define BIT_GET_BT_EISR_EN(x) (((x) >> BIT_SHIFT_BT_EISR_EN) & BIT_MASK_BT_EISR_EN)
+/* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER (Offset 0x0784) */
-#define BIT_BT_ACT_FALLING_ISR BIT(10)
-#define BIT_BT_ACT_RISING_ISR BIT(9)
-#define BIT_TDMA_TO_ISR BIT(8)
+#define BIT_SHIFT_WLAN_RPT_TO 0
+#define BIT_MASK_WLAN_RPT_TO 0xff
+#define BIT_WLAN_RPT_TO(x) \
+ (((x) & BIT_MASK_WLAN_RPT_TO) << BIT_SHIFT_WLAN_RPT_TO)
+#define BITS_WLAN_RPT_TO (BIT_MASK_WLAN_RPT_TO << BIT_SHIFT_WLAN_RPT_TO)
+#define BIT_CLEAR_WLAN_RPT_TO(x) ((x) & (~BITS_WLAN_RPT_TO))
+#define BIT_GET_WLAN_RPT_TO(x) \
+ (((x) >> BIT_SHIFT_WLAN_RPT_TO) & BIT_MASK_WLAN_RPT_TO)
+#define BIT_SET_WLAN_RPT_TO(x, v) \
+ (BIT_CLEAR_WLAN_RPT_TO(x) | BIT_WLAN_RPT_TO(v))
-#define BIT_SHIFT_BT_CH 0
-#define BIT_MASK_BT_CH 0xff
-#define BIT_BT_CH(x) (((x) & BIT_MASK_BT_CH) << BIT_SHIFT_BT_CH)
-#define BIT_GET_BT_CH(x) (((x) >> BIT_SHIFT_BT_CH) & BIT_MASK_BT_CH)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
-/* 2 REG_OBFF_CTRL_BASIC (Offset 0x0798) */
+/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER (Offset 0x0785) */
-#define BIT_OBFF_EN_V1 BIT(31)
+#define BIT_SHIFT_ISOLATION_CHK 1
+#define BIT_MASK_ISOLATION_CHK 0x7fffffffffffffffffffL
+#define BIT_ISOLATION_CHK(x) \
+ (((x) & BIT_MASK_ISOLATION_CHK) << BIT_SHIFT_ISOLATION_CHK)
+#define BITS_ISOLATION_CHK (BIT_MASK_ISOLATION_CHK << BIT_SHIFT_ISOLATION_CHK)
+#define BIT_CLEAR_ISOLATION_CHK(x) ((x) & (~BITS_ISOLATION_CHK))
+#define BIT_GET_ISOLATION_CHK(x) \
+ (((x) >> BIT_SHIFT_ISOLATION_CHK) & BIT_MASK_ISOLATION_CHK)
+#define BIT_SET_ISOLATION_CHK(x, v) \
+ (BIT_CLEAR_ISOLATION_CHK(x) | BIT_ISOLATION_CHK(v))
-#define BIT_SHIFT_OBFF_STATE_V1 28
-#define BIT_MASK_OBFF_STATE_V1 0x3
-#define BIT_OBFF_STATE_V1(x) (((x) & BIT_MASK_OBFF_STATE_V1) << BIT_SHIFT_OBFF_STATE_V1)
-#define BIT_GET_OBFF_STATE_V1(x) (((x) >> BIT_SHIFT_OBFF_STATE_V1) & BIT_MASK_OBFF_STATE_V1)
+#endif
-#define BIT_OBFF_ACT_RXDMA_EN BIT(27)
-#define BIT_OBFF_BLOCK_INT_EN BIT(26)
-#define BIT_OBFF_AUTOACT_EN BIT(25)
-#define BIT_OBFF_AUTOIDLE_EN BIT(24)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_WAKE_MAX_PLS 20
-#define BIT_MASK_WAKE_MAX_PLS 0x7
-#define BIT_WAKE_MAX_PLS(x) (((x) & BIT_MASK_WAKE_MAX_PLS) << BIT_SHIFT_WAKE_MAX_PLS)
-#define BIT_GET_WAKE_MAX_PLS(x) (((x) >> BIT_SHIFT_WAKE_MAX_PLS) & BIT_MASK_WAKE_MAX_PLS)
+/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER (Offset 0x0785) */
+#define BIT_SHIFT_ISOLATION_CHK_0 1
+#define BIT_MASK_ISOLATION_CHK_0 0x7fffff
+#define BIT_ISOLATION_CHK_0(x) \
+ (((x) & BIT_MASK_ISOLATION_CHK_0) << BIT_SHIFT_ISOLATION_CHK_0)
+#define BITS_ISOLATION_CHK_0 \
+ (BIT_MASK_ISOLATION_CHK_0 << BIT_SHIFT_ISOLATION_CHK_0)
+#define BIT_CLEAR_ISOLATION_CHK_0(x) ((x) & (~BITS_ISOLATION_CHK_0))
+#define BIT_GET_ISOLATION_CHK_0(x) \
+ (((x) >> BIT_SHIFT_ISOLATION_CHK_0) & BIT_MASK_ISOLATION_CHK_0)
+#define BIT_SET_ISOLATION_CHK_0(x, v) \
+ (BIT_CLEAR_ISOLATION_CHK_0(x) | BIT_ISOLATION_CHK_0(v))
-#define BIT_SHIFT_WAKE_MIN_PLS 16
-#define BIT_MASK_WAKE_MIN_PLS 0x7
-#define BIT_WAKE_MIN_PLS(x) (((x) & BIT_MASK_WAKE_MIN_PLS) << BIT_SHIFT_WAKE_MIN_PLS)
-#define BIT_GET_WAKE_MIN_PLS(x) (((x) >> BIT_SHIFT_WAKE_MIN_PLS) & BIT_MASK_WAKE_MIN_PLS)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_WAKE_MAX_F2F 12
-#define BIT_MASK_WAKE_MAX_F2F 0x7
-#define BIT_WAKE_MAX_F2F(x) (((x) & BIT_MASK_WAKE_MAX_F2F) << BIT_SHIFT_WAKE_MAX_F2F)
-#define BIT_GET_WAKE_MAX_F2F(x) (((x) >> BIT_SHIFT_WAKE_MAX_F2F) & BIT_MASK_WAKE_MAX_F2F)
+/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER (Offset 0x0785) */
+#define BIT_ISOLATION_EN BIT(0)
-#define BIT_SHIFT_WAKE_MIN_F2F 8
-#define BIT_MASK_WAKE_MIN_F2F 0x7
-#define BIT_WAKE_MIN_F2F(x) (((x) & BIT_MASK_WAKE_MIN_F2F) << BIT_SHIFT_WAKE_MIN_F2F)
-#define BIT_GET_WAKE_MIN_F2F(x) (((x) >> BIT_SHIFT_WAKE_MIN_F2F) & BIT_MASK_WAKE_MIN_F2F)
+#endif
-#define BIT_APP_CPU_ACT_V1 BIT(3)
-#define BIT_APP_OBFF_V1 BIT(2)
-#define BIT_APP_IDLE_V1 BIT(1)
-#define BIT_APP_INIT_V1 BIT(0)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_OBFF_CTRL2_TIMER (Offset 0x079C) */
+/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1 (Offset 0x0788) */
+#define BIT_SHIFT_ISOLATION_CHK_1 0
+#define BIT_MASK_ISOLATION_CHK_1 0xffffffffL
+#define BIT_ISOLATION_CHK_1(x) \
+ (((x) & BIT_MASK_ISOLATION_CHK_1) << BIT_SHIFT_ISOLATION_CHK_1)
+#define BITS_ISOLATION_CHK_1 \
+ (BIT_MASK_ISOLATION_CHK_1 << BIT_SHIFT_ISOLATION_CHK_1)
+#define BIT_CLEAR_ISOLATION_CHK_1(x) ((x) & (~BITS_ISOLATION_CHK_1))
+#define BIT_GET_ISOLATION_CHK_1(x) \
+ (((x) >> BIT_SHIFT_ISOLATION_CHK_1) & BIT_MASK_ISOLATION_CHK_1)
+#define BIT_SET_ISOLATION_CHK_1(x, v) \
+ (BIT_CLEAR_ISOLATION_CHK_1(x) | BIT_ISOLATION_CHK_1(v))
-#define BIT_SHIFT_RX_HIGH_TIMER_IDX 24
-#define BIT_MASK_RX_HIGH_TIMER_IDX 0x7
-#define BIT_RX_HIGH_TIMER_IDX(x) (((x) & BIT_MASK_RX_HIGH_TIMER_IDX) << BIT_SHIFT_RX_HIGH_TIMER_IDX)
-#define BIT_GET_RX_HIGH_TIMER_IDX(x) (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX) & BIT_MASK_RX_HIGH_TIMER_IDX)
+/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2 (Offset 0x078C) */
+#define BIT_APPEND_MACID_IN_RESP_EN_1 BIT(18)
+#define BIT_ADDR2_MATCH_EN_1 BIT(17)
+#define BIT_ANTTRN_EN_1 BIT(16)
-#define BIT_SHIFT_RX_MED_TIMER_IDX 16
-#define BIT_MASK_RX_MED_TIMER_IDX 0x7
-#define BIT_RX_MED_TIMER_IDX(x) (((x) & BIT_MASK_RX_MED_TIMER_IDX) << BIT_SHIFT_RX_MED_TIMER_IDX)
-#define BIT_GET_RX_MED_TIMER_IDX(x) (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX) & BIT_MASK_RX_MED_TIMER_IDX)
+#define BIT_SHIFT_ISOLATION_CHK_2 0
+#define BIT_MASK_ISOLATION_CHK_2 0xffffff
+#define BIT_ISOLATION_CHK_2(x) \
+ (((x) & BIT_MASK_ISOLATION_CHK_2) << BIT_SHIFT_ISOLATION_CHK_2)
+#define BITS_ISOLATION_CHK_2 \
+ (BIT_MASK_ISOLATION_CHK_2 << BIT_SHIFT_ISOLATION_CHK_2)
+#define BIT_CLEAR_ISOLATION_CHK_2(x) ((x) & (~BITS_ISOLATION_CHK_2))
+#define BIT_GET_ISOLATION_CHK_2(x) \
+ (((x) >> BIT_SHIFT_ISOLATION_CHK_2) & BIT_MASK_ISOLATION_CHK_2)
+#define BIT_SET_ISOLATION_CHK_2(x, v) \
+ (BIT_CLEAR_ISOLATION_CHK_2(x) | BIT_ISOLATION_CHK_2(v))
+#endif
-#define BIT_SHIFT_RX_LOW_TIMER_IDX 8
-#define BIT_MASK_RX_LOW_TIMER_IDX 0x7
-#define BIT_RX_LOW_TIMER_IDX(x) (((x) & BIT_MASK_RX_LOW_TIMER_IDX) << BIT_SHIFT_RX_LOW_TIMER_IDX)
-#define BIT_GET_RX_LOW_TIMER_IDX(x) (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX) & BIT_MASK_RX_LOW_TIMER_IDX)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+/* 2 REG_BT_INTERRUPT_STATUS_REGISTER (Offset 0x078F) */
-#define BIT_SHIFT_OBFF_INT_TIMER_IDX 0
-#define BIT_MASK_OBFF_INT_TIMER_IDX 0x7
-#define BIT_OBFF_INT_TIMER_IDX(x) (((x) & BIT_MASK_OBFF_INT_TIMER_IDX) << BIT_SHIFT_OBFF_INT_TIMER_IDX)
-#define BIT_GET_OBFF_INT_TIMER_IDX(x) (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX) & BIT_MASK_OBFF_INT_TIMER_IDX)
+#define BIT_BT_HID_ISR BIT(7)
+#define BIT_BT_QUERY_ISR BIT(6)
+#define BIT_MAC_NULL_PKT_NOTIFY_ISR BIT(5)
+#define BIT_WLAN_RPT_ISR BIT(4)
+#define BIT_BT_POWER_ISR BIT(3)
+#define BIT_BT_CHANNEL_ISR BIT(2)
+#define BIT_BT_SLOT_CHANGE_ISR BIT(1)
+#define BIT_BT_PROFILE_ISR BIT(0)
+/* 2 REG_BT_TDMA_TIME_REGISTER (Offset 0x0790) */
-/* 2 REG_LTR_CTRL_BASIC (Offset 0x07A0) */
+#define BIT_SHIFT_BT_TIME 6
+#define BIT_MASK_BT_TIME 0x3ffffff
+#define BIT_BT_TIME(x) (((x) & BIT_MASK_BT_TIME) << BIT_SHIFT_BT_TIME)
+#define BITS_BT_TIME (BIT_MASK_BT_TIME << BIT_SHIFT_BT_TIME)
+#define BIT_CLEAR_BT_TIME(x) ((x) & (~BITS_BT_TIME))
+#define BIT_GET_BT_TIME(x) (((x) >> BIT_SHIFT_BT_TIME) & BIT_MASK_BT_TIME)
+#define BIT_SET_BT_TIME(x, v) (BIT_CLEAR_BT_TIME(x) | BIT_BT_TIME(v))
-#define BIT_LTR_EN_V1 BIT(31)
-#define BIT_LTR_HW_EN_V1 BIT(30)
-#define BIT_LRT_ACT_CTS_EN BIT(29)
-#define BIT_LTR_ACT_RXPKT_EN BIT(28)
-#define BIT_LTR_ACT_RXDMA_EN BIT(27)
-#define BIT_LTR_IDLE_NO_SNOOP BIT(26)
-#define BIT_SPDUP_MGTPKT BIT(25)
-#define BIT_RX_AGG_EN BIT(24)
-#define BIT_APP_LTR_ACT BIT(23)
-#define BIT_APP_LTR_IDLE BIT(22)
+#define BIT_SHIFT_BT_RPT_SAMPLE_RATE 0
+#define BIT_MASK_BT_RPT_SAMPLE_RATE 0x3f
+#define BIT_BT_RPT_SAMPLE_RATE(x) \
+ (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE) << BIT_SHIFT_BT_RPT_SAMPLE_RATE)
+#define BITS_BT_RPT_SAMPLE_RATE \
+ (BIT_MASK_BT_RPT_SAMPLE_RATE << BIT_SHIFT_BT_RPT_SAMPLE_RATE)
+#define BIT_CLEAR_BT_RPT_SAMPLE_RATE(x) ((x) & (~BITS_BT_RPT_SAMPLE_RATE))
+#define BIT_GET_BT_RPT_SAMPLE_RATE(x) \
+ (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE) & BIT_MASK_BT_RPT_SAMPLE_RATE)
+#define BIT_SET_BT_RPT_SAMPLE_RATE(x, v) \
+ (BIT_CLEAR_BT_RPT_SAMPLE_RATE(x) | BIT_BT_RPT_SAMPLE_RATE(v))
-#define BIT_SHIFT_HIGH_RATE_TRIG_SEL 20
-#define BIT_MASK_HIGH_RATE_TRIG_SEL 0x3
-#define BIT_HIGH_RATE_TRIG_SEL(x) (((x) & BIT_MASK_HIGH_RATE_TRIG_SEL) << BIT_SHIFT_HIGH_RATE_TRIG_SEL)
-#define BIT_GET_HIGH_RATE_TRIG_SEL(x) (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL) & BIT_MASK_HIGH_RATE_TRIG_SEL)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_MED_RATE_TRIG_SEL 18
-#define BIT_MASK_MED_RATE_TRIG_SEL 0x3
-#define BIT_MED_RATE_TRIG_SEL(x) (((x) & BIT_MASK_MED_RATE_TRIG_SEL) << BIT_SHIFT_MED_RATE_TRIG_SEL)
-#define BIT_GET_MED_RATE_TRIG_SEL(x) (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL) & BIT_MASK_MED_RATE_TRIG_SEL)
+/* 2 REG_BT_ACT_REGISTER (Offset 0x0794) */
+#define BIT_SHIFT_R_OFDM_LEN 26
+#define BIT_MASK_R_OFDM_LEN 0x3f
+#define BIT_R_OFDM_LEN(x) (((x) & BIT_MASK_R_OFDM_LEN) << BIT_SHIFT_R_OFDM_LEN)
+#define BITS_R_OFDM_LEN (BIT_MASK_R_OFDM_LEN << BIT_SHIFT_R_OFDM_LEN)
+#define BIT_CLEAR_R_OFDM_LEN(x) ((x) & (~BITS_R_OFDM_LEN))
+#define BIT_GET_R_OFDM_LEN(x) \
+ (((x) >> BIT_SHIFT_R_OFDM_LEN) & BIT_MASK_R_OFDM_LEN)
+#define BIT_SET_R_OFDM_LEN(x, v) (BIT_CLEAR_R_OFDM_LEN(x) | BIT_R_OFDM_LEN(v))
-#define BIT_SHIFT_LOW_RATE_TRIG_SEL 16
-#define BIT_MASK_LOW_RATE_TRIG_SEL 0x3
-#define BIT_LOW_RATE_TRIG_SEL(x) (((x) & BIT_MASK_LOW_RATE_TRIG_SEL) << BIT_SHIFT_LOW_RATE_TRIG_SEL)
-#define BIT_GET_LOW_RATE_TRIG_SEL(x) (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL) & BIT_MASK_LOW_RATE_TRIG_SEL)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_HIGH_RATE_BD_IDX 8
-#define BIT_MASK_HIGH_RATE_BD_IDX 0x7f
-#define BIT_HIGH_RATE_BD_IDX(x) (((x) & BIT_MASK_HIGH_RATE_BD_IDX) << BIT_SHIFT_HIGH_RATE_BD_IDX)
-#define BIT_GET_HIGH_RATE_BD_IDX(x) (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX) & BIT_MASK_HIGH_RATE_BD_IDX)
+/* 2 REG_BT_ACT_REGISTER (Offset 0x0794) */
+#define BIT_SHIFT_BT_EISR_EN 16
+#define BIT_MASK_BT_EISR_EN 0xff
+#define BIT_BT_EISR_EN(x) (((x) & BIT_MASK_BT_EISR_EN) << BIT_SHIFT_BT_EISR_EN)
+#define BITS_BT_EISR_EN (BIT_MASK_BT_EISR_EN << BIT_SHIFT_BT_EISR_EN)
+#define BIT_CLEAR_BT_EISR_EN(x) ((x) & (~BITS_BT_EISR_EN))
+#define BIT_GET_BT_EISR_EN(x) \
+ (((x) >> BIT_SHIFT_BT_EISR_EN) & BIT_MASK_BT_EISR_EN)
+#define BIT_SET_BT_EISR_EN(x, v) (BIT_CLEAR_BT_EISR_EN(x) | BIT_BT_EISR_EN(v))
-#define BIT_SHIFT_LOW_RATE_BD_IDX 0
-#define BIT_MASK_LOW_RATE_BD_IDX 0x7f
-#define BIT_LOW_RATE_BD_IDX(x) (((x) & BIT_MASK_LOW_RATE_BD_IDX) << BIT_SHIFT_LOW_RATE_BD_IDX)
-#define BIT_GET_LOW_RATE_BD_IDX(x) (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX) & BIT_MASK_LOW_RATE_BD_IDX)
+#define BIT_BT_ACT_FALLING_ISR BIT(10)
+#define BIT_BT_ACT_RISING_ISR BIT(9)
+#define BIT_TDMA_TO_ISR BIT(8)
+#endif
-/* 2 REG_LTR_CTRL2_TIMER_THRESHOLD (Offset 0x07A4) */
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
+
+/* 2 REG_BT_ACT_REGISTER (Offset 0x0794) */
+#define BIT_SHIFT_BT_CH 0
+#define BIT_MASK_BT_CH 0xff
+#define BIT_BT_CH(x) (((x) & BIT_MASK_BT_CH) << BIT_SHIFT_BT_CH)
+#define BITS_BT_CH (BIT_MASK_BT_CH << BIT_SHIFT_BT_CH)
+#define BIT_CLEAR_BT_CH(x) ((x) & (~BITS_BT_CH))
+#define BIT_GET_BT_CH(x) (((x) >> BIT_SHIFT_BT_CH) & BIT_MASK_BT_CH)
+#define BIT_SET_BT_CH(x, v) (BIT_CLEAR_BT_CH(x) | BIT_BT_CH(v))
-#define BIT_SHIFT_RX_EMPTY_TIMER_IDX 24
-#define BIT_MASK_RX_EMPTY_TIMER_IDX 0x7
-#define BIT_RX_EMPTY_TIMER_IDX(x) (((x) & BIT_MASK_RX_EMPTY_TIMER_IDX) << BIT_SHIFT_RX_EMPTY_TIMER_IDX)
-#define BIT_GET_RX_EMPTY_TIMER_IDX(x) (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX) & BIT_MASK_RX_EMPTY_TIMER_IDX)
+#endif
+#if (HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_RX_AFULL_TH_IDX 20
-#define BIT_MASK_RX_AFULL_TH_IDX 0x7
-#define BIT_RX_AFULL_TH_IDX(x) (((x) & BIT_MASK_RX_AFULL_TH_IDX) << BIT_SHIFT_RX_AFULL_TH_IDX)
-#define BIT_GET_RX_AFULL_TH_IDX(x) (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX) & BIT_MASK_RX_AFULL_TH_IDX)
+/* 2 REG_BT_ACT_REGISTER (Offset 0x0794) */
+#define BIT_SHIFT_BT_CH_V1 0
+#define BIT_MASK_BT_CH_V1 0x7f
+#define BIT_BT_CH_V1(x) (((x) & BIT_MASK_BT_CH_V1) << BIT_SHIFT_BT_CH_V1)
+#define BITS_BT_CH_V1 (BIT_MASK_BT_CH_V1 << BIT_SHIFT_BT_CH_V1)
+#define BIT_CLEAR_BT_CH_V1(x) ((x) & (~BITS_BT_CH_V1))
+#define BIT_GET_BT_CH_V1(x) (((x) >> BIT_SHIFT_BT_CH_V1) & BIT_MASK_BT_CH_V1)
+#define BIT_SET_BT_CH_V1(x, v) (BIT_CLEAR_BT_CH_V1(x) | BIT_BT_CH_V1(v))
-#define BIT_SHIFT_RX_HIGH_TH_IDX 16
-#define BIT_MASK_RX_HIGH_TH_IDX 0x7
-#define BIT_RX_HIGH_TH_IDX(x) (((x) & BIT_MASK_RX_HIGH_TH_IDX) << BIT_SHIFT_RX_HIGH_TH_IDX)
-#define BIT_GET_RX_HIGH_TH_IDX(x) (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX) & BIT_MASK_RX_HIGH_TH_IDX)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_RX_MED_TH_IDX 12
-#define BIT_MASK_RX_MED_TH_IDX 0x7
-#define BIT_RX_MED_TH_IDX(x) (((x) & BIT_MASK_RX_MED_TH_IDX) << BIT_SHIFT_RX_MED_TH_IDX)
-#define BIT_GET_RX_MED_TH_IDX(x) (((x) >> BIT_SHIFT_RX_MED_TH_IDX) & BIT_MASK_RX_MED_TH_IDX)
+/* 2 REG_OBFF_CTRL_BASIC (Offset 0x0798) */
+#define BIT_OBFF_EN_V1 BIT(31)
+
+#define BIT_SHIFT_OBFF_STATE_V1 28
+#define BIT_MASK_OBFF_STATE_V1 0x3
+#define BIT_OBFF_STATE_V1(x) \
+ (((x) & BIT_MASK_OBFF_STATE_V1) << BIT_SHIFT_OBFF_STATE_V1)
+#define BITS_OBFF_STATE_V1 (BIT_MASK_OBFF_STATE_V1 << BIT_SHIFT_OBFF_STATE_V1)
+#define BIT_CLEAR_OBFF_STATE_V1(x) ((x) & (~BITS_OBFF_STATE_V1))
+#define BIT_GET_OBFF_STATE_V1(x) \
+ (((x) >> BIT_SHIFT_OBFF_STATE_V1) & BIT_MASK_OBFF_STATE_V1)
+#define BIT_SET_OBFF_STATE_V1(x, v) \
+ (BIT_CLEAR_OBFF_STATE_V1(x) | BIT_OBFF_STATE_V1(v))
+
+#define BIT_OBFF_ACT_RXDMA_EN BIT(27)
+#define BIT_OBFF_BLOCK_INT_EN BIT(26)
+#define BIT_OBFF_AUTOACT_EN BIT(25)
+#define BIT_OBFF_AUTOIDLE_EN BIT(24)
+
+#define BIT_SHIFT_WAKE_MAX_PLS 20
+#define BIT_MASK_WAKE_MAX_PLS 0x7
+#define BIT_WAKE_MAX_PLS(x) \
+ (((x) & BIT_MASK_WAKE_MAX_PLS) << BIT_SHIFT_WAKE_MAX_PLS)
+#define BITS_WAKE_MAX_PLS (BIT_MASK_WAKE_MAX_PLS << BIT_SHIFT_WAKE_MAX_PLS)
+#define BIT_CLEAR_WAKE_MAX_PLS(x) ((x) & (~BITS_WAKE_MAX_PLS))
+#define BIT_GET_WAKE_MAX_PLS(x) \
+ (((x) >> BIT_SHIFT_WAKE_MAX_PLS) & BIT_MASK_WAKE_MAX_PLS)
+#define BIT_SET_WAKE_MAX_PLS(x, v) \
+ (BIT_CLEAR_WAKE_MAX_PLS(x) | BIT_WAKE_MAX_PLS(v))
+
+#define BIT_SHIFT_WAKE_MIN_PLS 16
+#define BIT_MASK_WAKE_MIN_PLS 0x7
+#define BIT_WAKE_MIN_PLS(x) \
+ (((x) & BIT_MASK_WAKE_MIN_PLS) << BIT_SHIFT_WAKE_MIN_PLS)
+#define BITS_WAKE_MIN_PLS (BIT_MASK_WAKE_MIN_PLS << BIT_SHIFT_WAKE_MIN_PLS)
+#define BIT_CLEAR_WAKE_MIN_PLS(x) ((x) & (~BITS_WAKE_MIN_PLS))
+#define BIT_GET_WAKE_MIN_PLS(x) \
+ (((x) >> BIT_SHIFT_WAKE_MIN_PLS) & BIT_MASK_WAKE_MIN_PLS)
+#define BIT_SET_WAKE_MIN_PLS(x, v) \
+ (BIT_CLEAR_WAKE_MIN_PLS(x) | BIT_WAKE_MIN_PLS(v))
+
+#define BIT_SHIFT_WAKE_MAX_F2F 12
+#define BIT_MASK_WAKE_MAX_F2F 0x7
+#define BIT_WAKE_MAX_F2F(x) \
+ (((x) & BIT_MASK_WAKE_MAX_F2F) << BIT_SHIFT_WAKE_MAX_F2F)
+#define BITS_WAKE_MAX_F2F (BIT_MASK_WAKE_MAX_F2F << BIT_SHIFT_WAKE_MAX_F2F)
+#define BIT_CLEAR_WAKE_MAX_F2F(x) ((x) & (~BITS_WAKE_MAX_F2F))
+#define BIT_GET_WAKE_MAX_F2F(x) \
+ (((x) >> BIT_SHIFT_WAKE_MAX_F2F) & BIT_MASK_WAKE_MAX_F2F)
+#define BIT_SET_WAKE_MAX_F2F(x, v) \
+ (BIT_CLEAR_WAKE_MAX_F2F(x) | BIT_WAKE_MAX_F2F(v))
+
+#define BIT_SHIFT_WAKE_MIN_F2F 8
+#define BIT_MASK_WAKE_MIN_F2F 0x7
+#define BIT_WAKE_MIN_F2F(x) \
+ (((x) & BIT_MASK_WAKE_MIN_F2F) << BIT_SHIFT_WAKE_MIN_F2F)
+#define BITS_WAKE_MIN_F2F (BIT_MASK_WAKE_MIN_F2F << BIT_SHIFT_WAKE_MIN_F2F)
+#define BIT_CLEAR_WAKE_MIN_F2F(x) ((x) & (~BITS_WAKE_MIN_F2F))
+#define BIT_GET_WAKE_MIN_F2F(x) \
+ (((x) >> BIT_SHIFT_WAKE_MIN_F2F) & BIT_MASK_WAKE_MIN_F2F)
+#define BIT_SET_WAKE_MIN_F2F(x, v) \
+ (BIT_CLEAR_WAKE_MIN_F2F(x) | BIT_WAKE_MIN_F2F(v))
+
+#define BIT_APP_CPU_ACT_V1 BIT(3)
+#define BIT_APP_OBFF_V1 BIT(2)
+#define BIT_APP_IDLE_V1 BIT(1)
+#define BIT_APP_INIT_V1 BIT(0)
-#define BIT_SHIFT_RX_LOW_TH_IDX 8
-#define BIT_MASK_RX_LOW_TH_IDX 0x7
-#define BIT_RX_LOW_TH_IDX(x) (((x) & BIT_MASK_RX_LOW_TH_IDX) << BIT_SHIFT_RX_LOW_TH_IDX)
-#define BIT_GET_RX_LOW_TH_IDX(x) (((x) >> BIT_SHIFT_RX_LOW_TH_IDX) & BIT_MASK_RX_LOW_TH_IDX)
+/* 2 REG_OBFF_CTRL2_TIMER (Offset 0x079C) */
+#define BIT_SHIFT_RX_HIGH_TIMER_IDX 24
+#define BIT_MASK_RX_HIGH_TIMER_IDX 0x7
+#define BIT_RX_HIGH_TIMER_IDX(x) \
+ (((x) & BIT_MASK_RX_HIGH_TIMER_IDX) << BIT_SHIFT_RX_HIGH_TIMER_IDX)
+#define BITS_RX_HIGH_TIMER_IDX \
+ (BIT_MASK_RX_HIGH_TIMER_IDX << BIT_SHIFT_RX_HIGH_TIMER_IDX)
+#define BIT_CLEAR_RX_HIGH_TIMER_IDX(x) ((x) & (~BITS_RX_HIGH_TIMER_IDX))
+#define BIT_GET_RX_HIGH_TIMER_IDX(x) \
+ (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX) & BIT_MASK_RX_HIGH_TIMER_IDX)
+#define BIT_SET_RX_HIGH_TIMER_IDX(x, v) \
+ (BIT_CLEAR_RX_HIGH_TIMER_IDX(x) | BIT_RX_HIGH_TIMER_IDX(v))
+
+#define BIT_SHIFT_RX_MED_TIMER_IDX 16
+#define BIT_MASK_RX_MED_TIMER_IDX 0x7
+#define BIT_RX_MED_TIMER_IDX(x) \
+ (((x) & BIT_MASK_RX_MED_TIMER_IDX) << BIT_SHIFT_RX_MED_TIMER_IDX)
+#define BITS_RX_MED_TIMER_IDX \
+ (BIT_MASK_RX_MED_TIMER_IDX << BIT_SHIFT_RX_MED_TIMER_IDX)
+#define BIT_CLEAR_RX_MED_TIMER_IDX(x) ((x) & (~BITS_RX_MED_TIMER_IDX))
+#define BIT_GET_RX_MED_TIMER_IDX(x) \
+ (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX) & BIT_MASK_RX_MED_TIMER_IDX)
+#define BIT_SET_RX_MED_TIMER_IDX(x, v) \
+ (BIT_CLEAR_RX_MED_TIMER_IDX(x) | BIT_RX_MED_TIMER_IDX(v))
+
+#define BIT_SHIFT_RX_LOW_TIMER_IDX 8
+#define BIT_MASK_RX_LOW_TIMER_IDX 0x7
+#define BIT_RX_LOW_TIMER_IDX(x) \
+ (((x) & BIT_MASK_RX_LOW_TIMER_IDX) << BIT_SHIFT_RX_LOW_TIMER_IDX)
+#define BITS_RX_LOW_TIMER_IDX \
+ (BIT_MASK_RX_LOW_TIMER_IDX << BIT_SHIFT_RX_LOW_TIMER_IDX)
+#define BIT_CLEAR_RX_LOW_TIMER_IDX(x) ((x) & (~BITS_RX_LOW_TIMER_IDX))
+#define BIT_GET_RX_LOW_TIMER_IDX(x) \
+ (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX) & BIT_MASK_RX_LOW_TIMER_IDX)
+#define BIT_SET_RX_LOW_TIMER_IDX(x, v) \
+ (BIT_CLEAR_RX_LOW_TIMER_IDX(x) | BIT_RX_LOW_TIMER_IDX(v))
+
+#define BIT_SHIFT_OBFF_INT_TIMER_IDX 0
+#define BIT_MASK_OBFF_INT_TIMER_IDX 0x7
+#define BIT_OBFF_INT_TIMER_IDX(x) \
+ (((x) & BIT_MASK_OBFF_INT_TIMER_IDX) << BIT_SHIFT_OBFF_INT_TIMER_IDX)
+#define BITS_OBFF_INT_TIMER_IDX \
+ (BIT_MASK_OBFF_INT_TIMER_IDX << BIT_SHIFT_OBFF_INT_TIMER_IDX)
+#define BIT_CLEAR_OBFF_INT_TIMER_IDX(x) ((x) & (~BITS_OBFF_INT_TIMER_IDX))
+#define BIT_GET_OBFF_INT_TIMER_IDX(x) \
+ (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX) & BIT_MASK_OBFF_INT_TIMER_IDX)
+#define BIT_SET_OBFF_INT_TIMER_IDX(x, v) \
+ (BIT_CLEAR_OBFF_INT_TIMER_IDX(x) | BIT_OBFF_INT_TIMER_IDX(v))
-#define BIT_SHIFT_LTR_SPACE_IDX 4
-#define BIT_MASK_LTR_SPACE_IDX 0x3
-#define BIT_LTR_SPACE_IDX(x) (((x) & BIT_MASK_LTR_SPACE_IDX) << BIT_SHIFT_LTR_SPACE_IDX)
-#define BIT_GET_LTR_SPACE_IDX(x) (((x) >> BIT_SHIFT_LTR_SPACE_IDX) & BIT_MASK_LTR_SPACE_IDX)
+/* 2 REG_LTR_CTRL_BASIC (Offset 0x07A0) */
+#define BIT_LTR_EN_V1 BIT(31)
+#define BIT_LTR_HW_EN_V1 BIT(30)
+#define BIT_LRT_ACT_CTS_EN BIT(29)
+#define BIT_LTR_ACT_RXPKT_EN BIT(28)
+#define BIT_LTR_ACT_RXDMA_EN BIT(27)
+#define BIT_LTR_IDLE_NO_SNOOP BIT(26)
+#define BIT_SPDUP_MGTPKT BIT(25)
+#define BIT_RX_AGG_EN BIT(24)
+#define BIT_APP_LTR_ACT BIT(23)
+#define BIT_APP_LTR_IDLE BIT(22)
+
+#define BIT_SHIFT_HIGH_RATE_TRIG_SEL 20
+#define BIT_MASK_HIGH_RATE_TRIG_SEL 0x3
+#define BIT_HIGH_RATE_TRIG_SEL(x) \
+ (((x) & BIT_MASK_HIGH_RATE_TRIG_SEL) << BIT_SHIFT_HIGH_RATE_TRIG_SEL)
+#define BITS_HIGH_RATE_TRIG_SEL \
+ (BIT_MASK_HIGH_RATE_TRIG_SEL << BIT_SHIFT_HIGH_RATE_TRIG_SEL)
+#define BIT_CLEAR_HIGH_RATE_TRIG_SEL(x) ((x) & (~BITS_HIGH_RATE_TRIG_SEL))
+#define BIT_GET_HIGH_RATE_TRIG_SEL(x) \
+ (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL) & BIT_MASK_HIGH_RATE_TRIG_SEL)
+#define BIT_SET_HIGH_RATE_TRIG_SEL(x, v) \
+ (BIT_CLEAR_HIGH_RATE_TRIG_SEL(x) | BIT_HIGH_RATE_TRIG_SEL(v))
+
+#define BIT_SHIFT_MED_RATE_TRIG_SEL 18
+#define BIT_MASK_MED_RATE_TRIG_SEL 0x3
+#define BIT_MED_RATE_TRIG_SEL(x) \
+ (((x) & BIT_MASK_MED_RATE_TRIG_SEL) << BIT_SHIFT_MED_RATE_TRIG_SEL)
+#define BITS_MED_RATE_TRIG_SEL \
+ (BIT_MASK_MED_RATE_TRIG_SEL << BIT_SHIFT_MED_RATE_TRIG_SEL)
+#define BIT_CLEAR_MED_RATE_TRIG_SEL(x) ((x) & (~BITS_MED_RATE_TRIG_SEL))
+#define BIT_GET_MED_RATE_TRIG_SEL(x) \
+ (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL) & BIT_MASK_MED_RATE_TRIG_SEL)
+#define BIT_SET_MED_RATE_TRIG_SEL(x, v) \
+ (BIT_CLEAR_MED_RATE_TRIG_SEL(x) | BIT_MED_RATE_TRIG_SEL(v))
+
+#define BIT_SHIFT_LOW_RATE_TRIG_SEL 16
+#define BIT_MASK_LOW_RATE_TRIG_SEL 0x3
+#define BIT_LOW_RATE_TRIG_SEL(x) \
+ (((x) & BIT_MASK_LOW_RATE_TRIG_SEL) << BIT_SHIFT_LOW_RATE_TRIG_SEL)
+#define BITS_LOW_RATE_TRIG_SEL \
+ (BIT_MASK_LOW_RATE_TRIG_SEL << BIT_SHIFT_LOW_RATE_TRIG_SEL)
+#define BIT_CLEAR_LOW_RATE_TRIG_SEL(x) ((x) & (~BITS_LOW_RATE_TRIG_SEL))
+#define BIT_GET_LOW_RATE_TRIG_SEL(x) \
+ (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL) & BIT_MASK_LOW_RATE_TRIG_SEL)
+#define BIT_SET_LOW_RATE_TRIG_SEL(x, v) \
+ (BIT_CLEAR_LOW_RATE_TRIG_SEL(x) | BIT_LOW_RATE_TRIG_SEL(v))
+
+#define BIT_SHIFT_HIGH_RATE_BD_IDX 8
+#define BIT_MASK_HIGH_RATE_BD_IDX 0x7f
+#define BIT_HIGH_RATE_BD_IDX(x) \
+ (((x) & BIT_MASK_HIGH_RATE_BD_IDX) << BIT_SHIFT_HIGH_RATE_BD_IDX)
+#define BITS_HIGH_RATE_BD_IDX \
+ (BIT_MASK_HIGH_RATE_BD_IDX << BIT_SHIFT_HIGH_RATE_BD_IDX)
+#define BIT_CLEAR_HIGH_RATE_BD_IDX(x) ((x) & (~BITS_HIGH_RATE_BD_IDX))
+#define BIT_GET_HIGH_RATE_BD_IDX(x) \
+ (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX) & BIT_MASK_HIGH_RATE_BD_IDX)
+#define BIT_SET_HIGH_RATE_BD_IDX(x, v) \
+ (BIT_CLEAR_HIGH_RATE_BD_IDX(x) | BIT_HIGH_RATE_BD_IDX(v))
+
+#define BIT_SHIFT_LOW_RATE_BD_IDX 0
+#define BIT_MASK_LOW_RATE_BD_IDX 0x7f
+#define BIT_LOW_RATE_BD_IDX(x) \
+ (((x) & BIT_MASK_LOW_RATE_BD_IDX) << BIT_SHIFT_LOW_RATE_BD_IDX)
+#define BITS_LOW_RATE_BD_IDX \
+ (BIT_MASK_LOW_RATE_BD_IDX << BIT_SHIFT_LOW_RATE_BD_IDX)
+#define BIT_CLEAR_LOW_RATE_BD_IDX(x) ((x) & (~BITS_LOW_RATE_BD_IDX))
+#define BIT_GET_LOW_RATE_BD_IDX(x) \
+ (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX) & BIT_MASK_LOW_RATE_BD_IDX)
+#define BIT_SET_LOW_RATE_BD_IDX(x, v) \
+ (BIT_CLEAR_LOW_RATE_BD_IDX(x) | BIT_LOW_RATE_BD_IDX(v))
-#define BIT_SHIFT_LTR_IDLE_TIMER_IDX 0
-#define BIT_MASK_LTR_IDLE_TIMER_IDX 0x7
-#define BIT_LTR_IDLE_TIMER_IDX(x) (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX) << BIT_SHIFT_LTR_IDLE_TIMER_IDX)
-#define BIT_GET_LTR_IDLE_TIMER_IDX(x) (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX) & BIT_MASK_LTR_IDLE_TIMER_IDX)
+/* 2 REG_LTR_CTRL2_TIMER_THRESHOLD (Offset 0x07A4) */
+#define BIT_SHIFT_RX_EMPTY_TIMER_IDX 24
+#define BIT_MASK_RX_EMPTY_TIMER_IDX 0x7
+#define BIT_RX_EMPTY_TIMER_IDX(x) \
+ (((x) & BIT_MASK_RX_EMPTY_TIMER_IDX) << BIT_SHIFT_RX_EMPTY_TIMER_IDX)
+#define BITS_RX_EMPTY_TIMER_IDX \
+ (BIT_MASK_RX_EMPTY_TIMER_IDX << BIT_SHIFT_RX_EMPTY_TIMER_IDX)
+#define BIT_CLEAR_RX_EMPTY_TIMER_IDX(x) ((x) & (~BITS_RX_EMPTY_TIMER_IDX))
+#define BIT_GET_RX_EMPTY_TIMER_IDX(x) \
+ (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX) & BIT_MASK_RX_EMPTY_TIMER_IDX)
+#define BIT_SET_RX_EMPTY_TIMER_IDX(x, v) \
+ (BIT_CLEAR_RX_EMPTY_TIMER_IDX(x) | BIT_RX_EMPTY_TIMER_IDX(v))
+
+#define BIT_SHIFT_RX_AFULL_TH_IDX 20
+#define BIT_MASK_RX_AFULL_TH_IDX 0x7
+#define BIT_RX_AFULL_TH_IDX(x) \
+ (((x) & BIT_MASK_RX_AFULL_TH_IDX) << BIT_SHIFT_RX_AFULL_TH_IDX)
+#define BITS_RX_AFULL_TH_IDX \
+ (BIT_MASK_RX_AFULL_TH_IDX << BIT_SHIFT_RX_AFULL_TH_IDX)
+#define BIT_CLEAR_RX_AFULL_TH_IDX(x) ((x) & (~BITS_RX_AFULL_TH_IDX))
+#define BIT_GET_RX_AFULL_TH_IDX(x) \
+ (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX) & BIT_MASK_RX_AFULL_TH_IDX)
+#define BIT_SET_RX_AFULL_TH_IDX(x, v) \
+ (BIT_CLEAR_RX_AFULL_TH_IDX(x) | BIT_RX_AFULL_TH_IDX(v))
+
+#define BIT_SHIFT_RX_HIGH_TH_IDX 16
+#define BIT_MASK_RX_HIGH_TH_IDX 0x7
+#define BIT_RX_HIGH_TH_IDX(x) \
+ (((x) & BIT_MASK_RX_HIGH_TH_IDX) << BIT_SHIFT_RX_HIGH_TH_IDX)
+#define BITS_RX_HIGH_TH_IDX \
+ (BIT_MASK_RX_HIGH_TH_IDX << BIT_SHIFT_RX_HIGH_TH_IDX)
+#define BIT_CLEAR_RX_HIGH_TH_IDX(x) ((x) & (~BITS_RX_HIGH_TH_IDX))
+#define BIT_GET_RX_HIGH_TH_IDX(x) \
+ (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX) & BIT_MASK_RX_HIGH_TH_IDX)
+#define BIT_SET_RX_HIGH_TH_IDX(x, v) \
+ (BIT_CLEAR_RX_HIGH_TH_IDX(x) | BIT_RX_HIGH_TH_IDX(v))
+
+#define BIT_SHIFT_RX_MED_TH_IDX 12
+#define BIT_MASK_RX_MED_TH_IDX 0x7
+#define BIT_RX_MED_TH_IDX(x) \
+ (((x) & BIT_MASK_RX_MED_TH_IDX) << BIT_SHIFT_RX_MED_TH_IDX)
+#define BITS_RX_MED_TH_IDX (BIT_MASK_RX_MED_TH_IDX << BIT_SHIFT_RX_MED_TH_IDX)
+#define BIT_CLEAR_RX_MED_TH_IDX(x) ((x) & (~BITS_RX_MED_TH_IDX))
+#define BIT_GET_RX_MED_TH_IDX(x) \
+ (((x) >> BIT_SHIFT_RX_MED_TH_IDX) & BIT_MASK_RX_MED_TH_IDX)
+#define BIT_SET_RX_MED_TH_IDX(x, v) \
+ (BIT_CLEAR_RX_MED_TH_IDX(x) | BIT_RX_MED_TH_IDX(v))
+
+#define BIT_SHIFT_RX_LOW_TH_IDX 8
+#define BIT_MASK_RX_LOW_TH_IDX 0x7
+#define BIT_RX_LOW_TH_IDX(x) \
+ (((x) & BIT_MASK_RX_LOW_TH_IDX) << BIT_SHIFT_RX_LOW_TH_IDX)
+#define BITS_RX_LOW_TH_IDX (BIT_MASK_RX_LOW_TH_IDX << BIT_SHIFT_RX_LOW_TH_IDX)
+#define BIT_CLEAR_RX_LOW_TH_IDX(x) ((x) & (~BITS_RX_LOW_TH_IDX))
+#define BIT_GET_RX_LOW_TH_IDX(x) \
+ (((x) >> BIT_SHIFT_RX_LOW_TH_IDX) & BIT_MASK_RX_LOW_TH_IDX)
+#define BIT_SET_RX_LOW_TH_IDX(x, v) \
+ (BIT_CLEAR_RX_LOW_TH_IDX(x) | BIT_RX_LOW_TH_IDX(v))
+
+#define BIT_SHIFT_LTR_SPACE_IDX 4
+#define BIT_MASK_LTR_SPACE_IDX 0x3
+#define BIT_LTR_SPACE_IDX(x) \
+ (((x) & BIT_MASK_LTR_SPACE_IDX) << BIT_SHIFT_LTR_SPACE_IDX)
+#define BITS_LTR_SPACE_IDX (BIT_MASK_LTR_SPACE_IDX << BIT_SHIFT_LTR_SPACE_IDX)
+#define BIT_CLEAR_LTR_SPACE_IDX(x) ((x) & (~BITS_LTR_SPACE_IDX))
+#define BIT_GET_LTR_SPACE_IDX(x) \
+ (((x) >> BIT_SHIFT_LTR_SPACE_IDX) & BIT_MASK_LTR_SPACE_IDX)
+#define BIT_SET_LTR_SPACE_IDX(x, v) \
+ (BIT_CLEAR_LTR_SPACE_IDX(x) | BIT_LTR_SPACE_IDX(v))
+
+#define BIT_SHIFT_LTR_IDLE_TIMER_IDX 0
+#define BIT_MASK_LTR_IDLE_TIMER_IDX 0x7
+#define BIT_LTR_IDLE_TIMER_IDX(x) \
+ (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX) << BIT_SHIFT_LTR_IDLE_TIMER_IDX)
+#define BITS_LTR_IDLE_TIMER_IDX \
+ (BIT_MASK_LTR_IDLE_TIMER_IDX << BIT_SHIFT_LTR_IDLE_TIMER_IDX)
+#define BIT_CLEAR_LTR_IDLE_TIMER_IDX(x) ((x) & (~BITS_LTR_IDLE_TIMER_IDX))
+#define BIT_GET_LTR_IDLE_TIMER_IDX(x) \
+ (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX) & BIT_MASK_LTR_IDLE_TIMER_IDX)
+#define BIT_SET_LTR_IDLE_TIMER_IDX(x, v) \
+ (BIT_CLEAR_LTR_IDLE_TIMER_IDX(x) | BIT_LTR_IDLE_TIMER_IDX(v))
/* 2 REG_LTR_IDLE_LATENCY_V1 (Offset 0x07A8) */
+#define BIT_SHIFT_LTR_IDLE_L 0
+#define BIT_MASK_LTR_IDLE_L 0xffffffffL
+#define BIT_LTR_IDLE_L(x) (((x) & BIT_MASK_LTR_IDLE_L) << BIT_SHIFT_LTR_IDLE_L)
+#define BITS_LTR_IDLE_L (BIT_MASK_LTR_IDLE_L << BIT_SHIFT_LTR_IDLE_L)
+#define BIT_CLEAR_LTR_IDLE_L(x) ((x) & (~BITS_LTR_IDLE_L))
+#define BIT_GET_LTR_IDLE_L(x) \
+ (((x) >> BIT_SHIFT_LTR_IDLE_L) & BIT_MASK_LTR_IDLE_L)
+#define BIT_SET_LTR_IDLE_L(x, v) (BIT_CLEAR_LTR_IDLE_L(x) | BIT_LTR_IDLE_L(v))
+
+/* 2 REG_LTR_ACTIVE_LATENCY_V1 (Offset 0x07AC) */
+
+#define BIT_SHIFT_LTR_ACT_L 0
+#define BIT_MASK_LTR_ACT_L 0xffffffffL
+#define BIT_LTR_ACT_L(x) (((x) & BIT_MASK_LTR_ACT_L) << BIT_SHIFT_LTR_ACT_L)
+#define BITS_LTR_ACT_L (BIT_MASK_LTR_ACT_L << BIT_SHIFT_LTR_ACT_L)
+#define BIT_CLEAR_LTR_ACT_L(x) ((x) & (~BITS_LTR_ACT_L))
+#define BIT_GET_LTR_ACT_L(x) (((x) >> BIT_SHIFT_LTR_ACT_L) & BIT_MASK_LTR_ACT_L)
+#define BIT_SET_LTR_ACT_L(x, v) (BIT_CLEAR_LTR_ACT_L(x) | BIT_LTR_ACT_L(v))
-#define BIT_SHIFT_LTR_IDLE_L 0
-#define BIT_MASK_LTR_IDLE_L 0xffffffffL
-#define BIT_LTR_IDLE_L(x) (((x) & BIT_MASK_LTR_IDLE_L) << BIT_SHIFT_LTR_IDLE_L)
-#define BIT_GET_LTR_IDLE_L(x) (((x) >> BIT_SHIFT_LTR_IDLE_L) & BIT_MASK_LTR_IDLE_L)
+#endif
+#if (HALMAC_8814B_SUPPORT)
/* 2 REG_LTR_ACTIVE_LATENCY_V1 (Offset 0x07AC) */
+#define BIT_SHIFT_ANT_ADDR2_1 0
+#define BIT_MASK_ANT_ADDR2_1 0xffffffffL
+#define BIT_ANT_ADDR2_1(x) \
+ (((x) & BIT_MASK_ANT_ADDR2_1) << BIT_SHIFT_ANT_ADDR2_1)
+#define BITS_ANT_ADDR2_1 (BIT_MASK_ANT_ADDR2_1 << BIT_SHIFT_ANT_ADDR2_1)
+#define BIT_CLEAR_ANT_ADDR2_1(x) ((x) & (~BITS_ANT_ADDR2_1))
+#define BIT_GET_ANT_ADDR2_1(x) \
+ (((x) >> BIT_SHIFT_ANT_ADDR2_1) & BIT_MASK_ANT_ADDR2_1)
+#define BIT_SET_ANT_ADDR2_1(x, v) \
+ (BIT_CLEAR_ANT_ADDR2_1(x) | BIT_ANT_ADDR2_1(v))
-#define BIT_SHIFT_LTR_ACT_L 0
-#define BIT_MASK_LTR_ACT_L 0xffffffffL
-#define BIT_LTR_ACT_L(x) (((x) & BIT_MASK_LTR_ACT_L) << BIT_SHIFT_LTR_ACT_L)
-#define BIT_GET_LTR_ACT_L(x) (((x) >> BIT_SHIFT_LTR_ACT_L) & BIT_MASK_LTR_ACT_L)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER (Offset 0x07B0) */
-#define BIT_APPEND_MACID_IN_RESP_EN BIT(50)
-#define BIT_ADDR2_MATCH_EN BIT(49)
-#define BIT_ANTTRN_EN BIT(48)
-
-#define BIT_SHIFT_TRAIN_STA_ADDR 0
-#define BIT_MASK_TRAIN_STA_ADDR 0xffffffffffffL
-#define BIT_TRAIN_STA_ADDR(x) (((x) & BIT_MASK_TRAIN_STA_ADDR) << BIT_SHIFT_TRAIN_STA_ADDR)
-#define BIT_GET_TRAIN_STA_ADDR(x) (((x) >> BIT_SHIFT_TRAIN_STA_ADDR) & BIT_MASK_TRAIN_STA_ADDR)
+#define BIT_APPEND_MACID_IN_RESP_EN BIT(50)
+#define BIT_ADDR2_MATCH_EN BIT(49)
+#define BIT_ANTTRN_EN BIT(48)
+#define BIT_SHIFT_TRAIN_STA_ADDR 0
+#define BIT_MASK_TRAIN_STA_ADDR 0xffffffffffffL
+#define BIT_TRAIN_STA_ADDR(x) \
+ (((x) & BIT_MASK_TRAIN_STA_ADDR) << BIT_SHIFT_TRAIN_STA_ADDR)
+#define BITS_TRAIN_STA_ADDR \
+ (BIT_MASK_TRAIN_STA_ADDR << BIT_SHIFT_TRAIN_STA_ADDR)
+#define BIT_CLEAR_TRAIN_STA_ADDR(x) ((x) & (~BITS_TRAIN_STA_ADDR))
+#define BIT_GET_TRAIN_STA_ADDR(x) \
+ (((x) >> BIT_SHIFT_TRAIN_STA_ADDR) & BIT_MASK_TRAIN_STA_ADDR)
+#define BIT_SET_TRAIN_STA_ADDR(x, v) \
+ (BIT_CLEAR_TRAIN_STA_ADDR(x) | BIT_TRAIN_STA_ADDR(v))
#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER (Offset 0x07B0) */
+#define BIT_SHIFT_TRAIN_STA_ADDR_0 0
+#define BIT_MASK_TRAIN_STA_ADDR_0 0xffffffffL
+#define BIT_TRAIN_STA_ADDR_0(x) \
+ (((x) & BIT_MASK_TRAIN_STA_ADDR_0) << BIT_SHIFT_TRAIN_STA_ADDR_0)
+#define BITS_TRAIN_STA_ADDR_0 \
+ (BIT_MASK_TRAIN_STA_ADDR_0 << BIT_SHIFT_TRAIN_STA_ADDR_0)
+#define BIT_CLEAR_TRAIN_STA_ADDR_0(x) ((x) & (~BITS_TRAIN_STA_ADDR_0))
+#define BIT_GET_TRAIN_STA_ADDR_0(x) \
+ (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_0) & BIT_MASK_TRAIN_STA_ADDR_0)
+#define BIT_SET_TRAIN_STA_ADDR_0(x, v) \
+ (BIT_CLEAR_TRAIN_STA_ADDR_0(x) | BIT_TRAIN_STA_ADDR_0(v))
-/* 2 REG_WMAC_PKTCNT_RWD (Offset 0x07B8) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_PKTCNT_BSSIDMAP 4
-#define BIT_MASK_PKTCNT_BSSIDMAP 0xf
-#define BIT_PKTCNT_BSSIDMAP(x) (((x) & BIT_MASK_PKTCNT_BSSIDMAP) << BIT_SHIFT_PKTCNT_BSSIDMAP)
-#define BIT_GET_PKTCNT_BSSIDMAP(x) (((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP) & BIT_MASK_PKTCNT_BSSIDMAP)
+/* 2 REG_SMART_ANT_CTRL (Offset 0x07B4) */
-#define BIT_PKTCNT_CNTRST BIT(1)
-#define BIT_PKTCNT_CNTEN BIT(0)
+#define BIT_SHIFT_ANT_ADDR2_2 0
+#define BIT_MASK_ANT_ADDR2_2 0xffff
+#define BIT_ANT_ADDR2_2(x) \
+ (((x) & BIT_MASK_ANT_ADDR2_2) << BIT_SHIFT_ANT_ADDR2_2)
+#define BITS_ANT_ADDR2_2 (BIT_MASK_ANT_ADDR2_2 << BIT_SHIFT_ANT_ADDR2_2)
+#define BIT_CLEAR_ANT_ADDR2_2(x) ((x) & (~BITS_ANT_ADDR2_2))
+#define BIT_GET_ANT_ADDR2_2(x) \
+ (((x) >> BIT_SHIFT_ANT_ADDR2_2) & BIT_MASK_ANT_ADDR2_2)
+#define BIT_SET_ANT_ADDR2_2(x, v) \
+ (BIT_CLEAR_ANT_ADDR2_2(x) | BIT_ANT_ADDR2_2(v))
-/* 2 REG_WMAC_PKTCNT_CTRL (Offset 0x07BC) */
+#endif
-#define BIT_WMAC_PKTCNT_TRST BIT(9)
-#define BIT_WMAC_PKTCNT_FEN BIT(8)
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_WMAC_PKTCNT_CFGAD 0
-#define BIT_MASK_WMAC_PKTCNT_CFGAD 0xff
-#define BIT_WMAC_PKTCNT_CFGAD(x) (((x) & BIT_MASK_WMAC_PKTCNT_CFGAD) << BIT_SHIFT_WMAC_PKTCNT_CFGAD)
-#define BIT_GET_WMAC_PKTCNT_CFGAD(x) (((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD) & BIT_MASK_WMAC_PKTCNT_CFGAD)
+/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_1 (Offset 0x07B4) */
+#define BIT_SHIFT_TRAIN_STA_ADDR_1 0
+#define BIT_MASK_TRAIN_STA_ADDR_1 0xffff
+#define BIT_TRAIN_STA_ADDR_1(x) \
+ (((x) & BIT_MASK_TRAIN_STA_ADDR_1) << BIT_SHIFT_TRAIN_STA_ADDR_1)
+#define BITS_TRAIN_STA_ADDR_1 \
+ (BIT_MASK_TRAIN_STA_ADDR_1 << BIT_SHIFT_TRAIN_STA_ADDR_1)
+#define BIT_CLEAR_TRAIN_STA_ADDR_1(x) ((x) & (~BITS_TRAIN_STA_ADDR_1))
+#define BIT_GET_TRAIN_STA_ADDR_1(x) \
+ (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_1) & BIT_MASK_TRAIN_STA_ADDR_1)
+#define BIT_SET_TRAIN_STA_ADDR_1(x, v) \
+ (BIT_CLEAR_TRAIN_STA_ADDR_1(x) | BIT_TRAIN_STA_ADDR_1(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_WMAC_PKTCNT_RWD (Offset 0x07B8) */
+#define BIT_SHIFT_PKTCNT_BSSIDMAP 4
+#define BIT_MASK_PKTCNT_BSSIDMAP 0xf
+#define BIT_PKTCNT_BSSIDMAP(x) \
+ (((x) & BIT_MASK_PKTCNT_BSSIDMAP) << BIT_SHIFT_PKTCNT_BSSIDMAP)
+#define BITS_PKTCNT_BSSIDMAP \
+ (BIT_MASK_PKTCNT_BSSIDMAP << BIT_SHIFT_PKTCNT_BSSIDMAP)
+#define BIT_CLEAR_PKTCNT_BSSIDMAP(x) ((x) & (~BITS_PKTCNT_BSSIDMAP))
+#define BIT_GET_PKTCNT_BSSIDMAP(x) \
+ (((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP) & BIT_MASK_PKTCNT_BSSIDMAP)
+#define BIT_SET_PKTCNT_BSSIDMAP(x, v) \
+ (BIT_CLEAR_PKTCNT_BSSIDMAP(x) | BIT_PKTCNT_BSSIDMAP(v))
-/* 2 REG_IQ_DUMP (Offset 0x07C0) */
+#define BIT_PKTCNT_CNTRST BIT(1)
+#define BIT_PKTCNT_CNTEN BIT(0)
+#endif
-#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC (64 & CPU_OPT_WIDTH)
-#define BIT_MASK_R_WMAC_MATCH_REF_MAC 0xffffffffL
-#define BIT_R_WMAC_MATCH_REF_MAC(x) (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC) << BIT_SHIFT_R_WMAC_MATCH_REF_MAC)
-#define BIT_GET_R_WMAC_MATCH_REF_MAC(x) (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC) & BIT_MASK_R_WMAC_MATCH_REF_MAC)
+#if (HALMAC_8814B_SUPPORT)
+/* 2 REG_CONTROL_FRAME_REPORT (Offset 0x07B8) */
-#define BIT_SHIFT_R_WMAC_RX_FIL_LEN (64 & CPU_OPT_WIDTH)
-#define BIT_MASK_R_WMAC_RX_FIL_LEN 0xffff
-#define BIT_R_WMAC_RX_FIL_LEN(x) (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN) << BIT_SHIFT_R_WMAC_RX_FIL_LEN)
-#define BIT_GET_R_WMAC_RX_FIL_LEN(x) (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN) & BIT_MASK_R_WMAC_RX_FIL_LEN)
+#define BIT_SHIFT_CONTROL_FRAME_REPORT 0
+#define BIT_MASK_CONTROL_FRAME_REPORT 0xffffffffL
+#define BIT_CONTROL_FRAME_REPORT(x) \
+ (((x) & BIT_MASK_CONTROL_FRAME_REPORT) \
+ << BIT_SHIFT_CONTROL_FRAME_REPORT)
+#define BITS_CONTROL_FRAME_REPORT \
+ (BIT_MASK_CONTROL_FRAME_REPORT << BIT_SHIFT_CONTROL_FRAME_REPORT)
+#define BIT_CLEAR_CONTROL_FRAME_REPORT(x) ((x) & (~BITS_CONTROL_FRAME_REPORT))
+#define BIT_GET_CONTROL_FRAME_REPORT(x) \
+ (((x) >> BIT_SHIFT_CONTROL_FRAME_REPORT) & \
+ BIT_MASK_CONTROL_FRAME_REPORT)
+#define BIT_SET_CONTROL_FRAME_REPORT(x, v) \
+ (BIT_CLEAR_CONTROL_FRAME_REPORT(x) | BIT_CONTROL_FRAME_REPORT(v))
+#endif
-#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH (56 & CPU_OPT_WIDTH)
-#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH 0xff
-#define BIT_R_WMAC_RXFIFO_FULL_TH(x) (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH) << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH)
-#define BIT_GET_R_WMAC_RXFIFO_FULL_TH(x) (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define BIT_R_WMAC_SRCH_TXRPT_TYPE BIT(51)
-#define BIT_R_WMAC_NDP_RST BIT(50)
-#define BIT_R_WMAC_POWINT_EN BIT(49)
-#define BIT_R_WMAC_SRCH_TXRPT_PERPKT BIT(48)
-#define BIT_R_WMAC_SRCH_TXRPT_MID BIT(47)
-#define BIT_R_WMAC_PFIN_TOEN BIT(46)
-#define BIT_R_WMAC_FIL_SECERR BIT(45)
-#define BIT_R_WMAC_FIL_CTLPKTLEN BIT(44)
-#define BIT_R_WMAC_FIL_FCTYPE BIT(43)
-#define BIT_R_WMAC_FIL_FCPROVER BIT(42)
-#define BIT_R_WMAC_PHYSTS_SNIF BIT(41)
-#define BIT_R_WMAC_PHYSTS_PLCP BIT(40)
-#define BIT_R_MAC_TCR_VBONF_RD BIT(39)
-#define BIT_R_WMAC_TCR_MPAR_NDP BIT(38)
-#define BIT_R_WMAC_NDP_FILTER BIT(37)
-#define BIT_R_WMAC_RXLEN_SEL BIT(36)
-#define BIT_R_WMAC_RXLEN_SEL1 BIT(35)
-#define BIT_R_OFDM_FILTER BIT(34)
-#define BIT_R_WMAC_CHK_OFDM_LEN BIT(33)
+/* 2 REG_WMAC_PKTCNT_CTRL (Offset 0x07BC) */
-#define BIT_SHIFT_R_WMAC_MASK_LA_MAC (32 & CPU_OPT_WIDTH)
-#define BIT_MASK_R_WMAC_MASK_LA_MAC 0xffffffffL
-#define BIT_R_WMAC_MASK_LA_MAC(x) (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC) << BIT_SHIFT_R_WMAC_MASK_LA_MAC)
-#define BIT_GET_R_WMAC_MASK_LA_MAC(x) (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC) & BIT_MASK_R_WMAC_MASK_LA_MAC)
+#define BIT_WMAC_PKTCNT_TRST BIT(9)
-#define BIT_R_WMAC_CHK_CCK_LEN BIT(32)
+#endif
-#define BIT_SHIFT_R_OFDM_LEN 26
-#define BIT_MASK_R_OFDM_LEN 0x3f
-#define BIT_R_OFDM_LEN(x) (((x) & BIT_MASK_R_OFDM_LEN) << BIT_SHIFT_R_OFDM_LEN)
-#define BIT_GET_R_OFDM_LEN(x) (((x) >> BIT_SHIFT_R_OFDM_LEN) & BIT_MASK_R_OFDM_LEN)
+#if (HALMAC_8814B_SUPPORT)
+/* 2 REG_CONTROL_FRAME_CNT_CTRL (Offset 0x07BC) */
-#define BIT_SHIFT_DUMP_OK_ADDR 15
-#define BIT_MASK_DUMP_OK_ADDR 0x1ffff
-#define BIT_DUMP_OK_ADDR(x) (((x) & BIT_MASK_DUMP_OK_ADDR) << BIT_SHIFT_DUMP_OK_ADDR)
-#define BIT_GET_DUMP_OK_ADDR(x) (((x) >> BIT_SHIFT_DUMP_OK_ADDR) & BIT_MASK_DUMP_OK_ADDR)
+#define BIT_ALLCNTRST BIT(9)
+#endif
-#define BIT_SHIFT_R_TRIG_TIME_SEL 8
-#define BIT_MASK_R_TRIG_TIME_SEL 0x7f
-#define BIT_R_TRIG_TIME_SEL(x) (((x) & BIT_MASK_R_TRIG_TIME_SEL) << BIT_SHIFT_R_TRIG_TIME_SEL)
-#define BIT_GET_R_TRIG_TIME_SEL(x) (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL) & BIT_MASK_R_TRIG_TIME_SEL)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+/* 2 REG_WMAC_PKTCNT_CTRL (Offset 0x07BC) */
-#define BIT_SHIFT_R_MAC_TRIG_SEL 6
-#define BIT_MASK_R_MAC_TRIG_SEL 0x3
-#define BIT_R_MAC_TRIG_SEL(x) (((x) & BIT_MASK_R_MAC_TRIG_SEL) << BIT_SHIFT_R_MAC_TRIG_SEL)
-#define BIT_GET_R_MAC_TRIG_SEL(x) (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL) & BIT_MASK_R_MAC_TRIG_SEL)
+#define BIT_WMAC_PKTCNT_FEN BIT(8)
-#define BIT_MAC_TRIG_REG BIT(5)
+#endif
-#define BIT_SHIFT_R_LEVEL_PULSE_SEL 3
-#define BIT_MASK_R_LEVEL_PULSE_SEL 0x3
-#define BIT_R_LEVEL_PULSE_SEL(x) (((x) & BIT_MASK_R_LEVEL_PULSE_SEL) << BIT_SHIFT_R_LEVEL_PULSE_SEL)
-#define BIT_GET_R_LEVEL_PULSE_SEL(x) (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL) & BIT_MASK_R_LEVEL_PULSE_SEL)
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_EN_LA_MAC BIT(2)
-#define BIT_R_EN_IQDUMP BIT(1)
-#define BIT_R_IQDATA_DUMP BIT(0)
+/* 2 REG_CONTROL_FRAME_CNT_CTRL (Offset 0x07BC) */
-#define BIT_SHIFT_R_CCK_LEN 0
-#define BIT_MASK_R_CCK_LEN 0xffff
-#define BIT_R_CCK_LEN(x) (((x) & BIT_MASK_R_CCK_LEN) << BIT_SHIFT_R_CCK_LEN)
-#define BIT_GET_R_CCK_LEN(x) (((x) >> BIT_SHIFT_R_CCK_LEN) & BIT_MASK_R_CCK_LEN)
+#define BIT__ALLCNTEN BIT(8)
+#define BIT_SHIFT_ADDR 4
+#define BIT_MASK_ADDR 0xf
+#define BIT_ADDR(x) (((x) & BIT_MASK_ADDR) << BIT_SHIFT_ADDR)
+#define BITS_ADDR (BIT_MASK_ADDR << BIT_SHIFT_ADDR)
+#define BIT_CLEAR_ADDR(x) ((x) & (~BITS_ADDR))
+#define BIT_GET_ADDR(x) (((x) >> BIT_SHIFT_ADDR) & BIT_MASK_ADDR)
+#define BIT_SET_ADDR(x, v) (BIT_CLEAR_ADDR(x) | BIT_ADDR(v))
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_WMAC_FTM_CTL (Offset 0x07CC) */
+/* 2 REG_WMAC_PKTCNT_CTRL (Offset 0x07BC) */
-#define BIT_R_WMAC_RX_SYNCFIFO_SYNC BIT(55)
-#define BIT_R_WMAC_RXRST_DLY BIT(54)
-#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP BIT(53)
-#define BIT_R_WMAC_SRCH_TXRPT_UA1 BIT(52)
-#define BIT_RXFTM_TXACK_SC BIT(6)
-#define BIT_RXFTM_TXACK_BW BIT(5)
-#define BIT_RXFTM_EN BIT(3)
-#define BIT_RXFTMREQ_BYDRV BIT(2)
-#define BIT_RXFTMREQ_EN BIT(1)
-#define BIT_FTM_EN BIT(0)
+#define BIT_SHIFT_WMAC_PKTCNT_CFGAD 0
+#define BIT_MASK_WMAC_PKTCNT_CFGAD 0xff
+#define BIT_WMAC_PKTCNT_CFGAD(x) \
+ (((x) & BIT_MASK_WMAC_PKTCNT_CFGAD) << BIT_SHIFT_WMAC_PKTCNT_CFGAD)
+#define BITS_WMAC_PKTCNT_CFGAD \
+ (BIT_MASK_WMAC_PKTCNT_CFGAD << BIT_SHIFT_WMAC_PKTCNT_CFGAD)
+#define BIT_CLEAR_WMAC_PKTCNT_CFGAD(x) ((x) & (~BITS_WMAC_PKTCNT_CFGAD))
+#define BIT_GET_WMAC_PKTCNT_CFGAD(x) \
+ (((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD) & BIT_MASK_WMAC_PKTCNT_CFGAD)
+#define BIT_SET_WMAC_PKTCNT_CFGAD(x, v) \
+ (BIT_CLEAR_WMAC_PKTCNT_CFGAD(x) | BIT_WMAC_PKTCNT_CFGAD(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_CONTROL_FRAME_CNT_CTRL (Offset 0x07BC) */
+#define BIT_SHIFT_CTRL_SEL 0
+#define BIT_MASK_CTRL_SEL 0xf
+#define BIT_CTRL_SEL(x) (((x) & BIT_MASK_CTRL_SEL) << BIT_SHIFT_CTRL_SEL)
+#define BITS_CTRL_SEL (BIT_MASK_CTRL_SEL << BIT_SHIFT_CTRL_SEL)
+#define BIT_CLEAR_CTRL_SEL(x) ((x) & (~BITS_CTRL_SEL))
+#define BIT_GET_CTRL_SEL(x) (((x) >> BIT_SHIFT_CTRL_SEL) & BIT_MASK_CTRL_SEL)
+#define BIT_SET_CTRL_SEL(x, v) (BIT_CLEAR_CTRL_SEL(x) | BIT_CTRL_SEL(v))
-/* 2 REG_IQ_DUMP_EXT (Offset 0x07CF) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_R_TIME_UNIT_SEL 0
-#define BIT_MASK_R_TIME_UNIT_SEL 0x7
-#define BIT_R_TIME_UNIT_SEL(x) (((x) & BIT_MASK_R_TIME_UNIT_SEL) << BIT_SHIFT_R_TIME_UNIT_SEL)
-#define BIT_GET_R_TIME_UNIT_SEL(x) (((x) >> BIT_SHIFT_R_TIME_UNIT_SEL) & BIT_MASK_R_TIME_UNIT_SEL)
+/* 2 REG_IQ_DUMP (Offset 0x07C0) */
+#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC (64 & CPU_OPT_WIDTH)
+#define BIT_MASK_R_WMAC_MATCH_REF_MAC 0xffffffffL
+#define BIT_R_WMAC_MATCH_REF_MAC(x) \
+ (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC) \
+ << BIT_SHIFT_R_WMAC_MATCH_REF_MAC)
+#define BITS_R_WMAC_MATCH_REF_MAC \
+ (BIT_MASK_R_WMAC_MATCH_REF_MAC << BIT_SHIFT_R_WMAC_MATCH_REF_MAC)
+#define BIT_CLEAR_R_WMAC_MATCH_REF_MAC(x) ((x) & (~BITS_R_WMAC_MATCH_REF_MAC))
+#define BIT_GET_R_WMAC_MATCH_REF_MAC(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC) & \
+ BIT_MASK_R_WMAC_MATCH_REF_MAC)
+#define BIT_SET_R_WMAC_MATCH_REF_MAC(x, v) \
+ (BIT_CLEAR_R_WMAC_MATCH_REF_MAC(x) | BIT_R_WMAC_MATCH_REF_MAC(v))
+
+#define BIT_SHIFT_R_WMAC_RX_FIL_LEN (64 & CPU_OPT_WIDTH)
+#define BIT_MASK_R_WMAC_RX_FIL_LEN 0xffff
+#define BIT_R_WMAC_RX_FIL_LEN(x) \
+ (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN) << BIT_SHIFT_R_WMAC_RX_FIL_LEN)
+#define BITS_R_WMAC_RX_FIL_LEN \
+ (BIT_MASK_R_WMAC_RX_FIL_LEN << BIT_SHIFT_R_WMAC_RX_FIL_LEN)
+#define BIT_CLEAR_R_WMAC_RX_FIL_LEN(x) ((x) & (~BITS_R_WMAC_RX_FIL_LEN))
+#define BIT_GET_R_WMAC_RX_FIL_LEN(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN) & BIT_MASK_R_WMAC_RX_FIL_LEN)
+#define BIT_SET_R_WMAC_RX_FIL_LEN(x, v) \
+ (BIT_CLEAR_R_WMAC_RX_FIL_LEN(x) | BIT_R_WMAC_RX_FIL_LEN(v))
+
+#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH (56 & CPU_OPT_WIDTH)
+#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH 0xff
+#define BIT_R_WMAC_RXFIFO_FULL_TH(x) \
+ (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH) \
+ << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH)
+#define BITS_R_WMAC_RXFIFO_FULL_TH \
+ (BIT_MASK_R_WMAC_RXFIFO_FULL_TH << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH)
+#define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH(x) ((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH))
+#define BIT_GET_R_WMAC_RXFIFO_FULL_TH(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH) & \
+ BIT_MASK_R_WMAC_RXFIFO_FULL_TH)
+#define BIT_SET_R_WMAC_RXFIFO_FULL_TH(x, v) \
+ (BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH(x) | BIT_R_WMAC_RXFIFO_FULL_TH(v))
+
+#define BIT_R_WMAC_SRCH_TXRPT_TYPE BIT(51)
+#define BIT_R_WMAC_NDP_RST BIT(50)
+#define BIT_R_WMAC_POWINT_EN BIT(49)
+#define BIT_R_WMAC_SRCH_TXRPT_PERPKT BIT(48)
+#define BIT_R_WMAC_SRCH_TXRPT_MID BIT(47)
+#define BIT_R_WMAC_PFIN_TOEN BIT(46)
+#define BIT_R_WMAC_FIL_SECERR BIT(45)
+#define BIT_R_WMAC_FIL_CTLPKTLEN BIT(44)
+#define BIT_R_WMAC_FIL_FCTYPE BIT(43)
+#define BIT_R_WMAC_FIL_FCPROVER BIT(42)
+#define BIT_R_WMAC_PHYSTS_SNIF BIT(41)
+#define BIT_R_WMAC_PHYSTS_PLCP BIT(40)
+#define BIT_R_MAC_TCR_VBONF_RD BIT(39)
+#define BIT_R_WMAC_TCR_MPAR_NDP BIT(38)
+#define BIT_R_WMAC_NDP_FILTER BIT(37)
+#define BIT_R_WMAC_RXLEN_SEL BIT(36)
+#define BIT_R_WMAC_RXLEN_SEL1 BIT(35)
+#define BIT_R_OFDM_FILTER BIT(34)
+#define BIT_R_WMAC_CHK_OFDM_LEN BIT(33)
+
+#define BIT_SHIFT_R_WMAC_MASK_LA_MAC (32 & CPU_OPT_WIDTH)
+#define BIT_MASK_R_WMAC_MASK_LA_MAC 0xffffffffL
+#define BIT_R_WMAC_MASK_LA_MAC(x) \
+ (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC) << BIT_SHIFT_R_WMAC_MASK_LA_MAC)
+#define BITS_R_WMAC_MASK_LA_MAC \
+ (BIT_MASK_R_WMAC_MASK_LA_MAC << BIT_SHIFT_R_WMAC_MASK_LA_MAC)
+#define BIT_CLEAR_R_WMAC_MASK_LA_MAC(x) ((x) & (~BITS_R_WMAC_MASK_LA_MAC))
+#define BIT_GET_R_WMAC_MASK_LA_MAC(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC) & BIT_MASK_R_WMAC_MASK_LA_MAC)
+#define BIT_SET_R_WMAC_MASK_LA_MAC(x, v) \
+ (BIT_CLEAR_R_WMAC_MASK_LA_MAC(x) | BIT_R_WMAC_MASK_LA_MAC(v))
+
+#define BIT_R_WMAC_CHK_CCK_LEN BIT(32)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_IQ_DUMP (Offset 0x07C0) */
+#define BIT_SHIFT_DUMP_OK_ADDR 16
+#define BIT_MASK_DUMP_OK_ADDR 0xffff
+#define BIT_DUMP_OK_ADDR(x) \
+ (((x) & BIT_MASK_DUMP_OK_ADDR) << BIT_SHIFT_DUMP_OK_ADDR)
+#define BITS_DUMP_OK_ADDR (BIT_MASK_DUMP_OK_ADDR << BIT_SHIFT_DUMP_OK_ADDR)
+#define BIT_CLEAR_DUMP_OK_ADDR(x) ((x) & (~BITS_DUMP_OK_ADDR))
+#define BIT_GET_DUMP_OK_ADDR(x) \
+ (((x) >> BIT_SHIFT_DUMP_OK_ADDR) & BIT_MASK_DUMP_OK_ADDR)
+#define BIT_SET_DUMP_OK_ADDR(x, v) \
+ (BIT_CLEAR_DUMP_OK_ADDR(x) | BIT_DUMP_OK_ADDR(v))
-#if (HALMAC_8814AMP_SUPPORT)
+#endif
+#if (HALMAC_8822C_SUPPORT)
-/* 2 REG_OFDM_CCK_LEN_MASK (Offset 0x07D0) */
+/* 2 REG_IQ_DUMP (Offset 0x07C0) */
-#define BIT_MICICV_CLR BIT(86)
-#define BIT_MPDU_RDY_SET BIT(85)
-#define BIT_CLR_SEC_TYPE BIT(84)
-#define BIT_NEWPKT_IN BIT(83)
-#define BIT_FCS_END BIT(82)
-#define BIT_DEL_MESH_TYPE BIT(81)
-#define BIT_MASK_MESH_TYPE BIT(80)
+#define BIT_MACDBG_TRIG_IQDUMP BIT(15)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_IQ_DUMP (Offset 0x07C0) */
+#define BIT_SHIFT_R_TRIG_TIME_SEL 8
+#define BIT_MASK_R_TRIG_TIME_SEL 0x7f
+#define BIT_R_TRIG_TIME_SEL(x) \
+ (((x) & BIT_MASK_R_TRIG_TIME_SEL) << BIT_SHIFT_R_TRIG_TIME_SEL)
+#define BITS_R_TRIG_TIME_SEL \
+ (BIT_MASK_R_TRIG_TIME_SEL << BIT_SHIFT_R_TRIG_TIME_SEL)
+#define BIT_CLEAR_R_TRIG_TIME_SEL(x) ((x) & (~BITS_R_TRIG_TIME_SEL))
+#define BIT_GET_R_TRIG_TIME_SEL(x) \
+ (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL) & BIT_MASK_R_TRIG_TIME_SEL)
+#define BIT_SET_R_TRIG_TIME_SEL(x, v) \
+ (BIT_CLEAR_R_TRIG_TIME_SEL(x) | BIT_R_TRIG_TIME_SEL(v))
+
+#define BIT_SHIFT_R_MAC_TRIG_SEL 6
+#define BIT_MASK_R_MAC_TRIG_SEL 0x3
+#define BIT_R_MAC_TRIG_SEL(x) \
+ (((x) & BIT_MASK_R_MAC_TRIG_SEL) << BIT_SHIFT_R_MAC_TRIG_SEL)
+#define BITS_R_MAC_TRIG_SEL \
+ (BIT_MASK_R_MAC_TRIG_SEL << BIT_SHIFT_R_MAC_TRIG_SEL)
+#define BIT_CLEAR_R_MAC_TRIG_SEL(x) ((x) & (~BITS_R_MAC_TRIG_SEL))
+#define BIT_GET_R_MAC_TRIG_SEL(x) \
+ (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL) & BIT_MASK_R_MAC_TRIG_SEL)
+#define BIT_SET_R_MAC_TRIG_SEL(x, v) \
+ (BIT_CLEAR_R_MAC_TRIG_SEL(x) | BIT_R_MAC_TRIG_SEL(v))
+
+#define BIT_MAC_TRIG_REG BIT(5)
+
+#define BIT_SHIFT_R_LEVEL_PULSE_SEL 3
+#define BIT_MASK_R_LEVEL_PULSE_SEL 0x3
+#define BIT_R_LEVEL_PULSE_SEL(x) \
+ (((x) & BIT_MASK_R_LEVEL_PULSE_SEL) << BIT_SHIFT_R_LEVEL_PULSE_SEL)
+#define BITS_R_LEVEL_PULSE_SEL \
+ (BIT_MASK_R_LEVEL_PULSE_SEL << BIT_SHIFT_R_LEVEL_PULSE_SEL)
+#define BIT_CLEAR_R_LEVEL_PULSE_SEL(x) ((x) & (~BITS_R_LEVEL_PULSE_SEL))
+#define BIT_GET_R_LEVEL_PULSE_SEL(x) \
+ (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL) & BIT_MASK_R_LEVEL_PULSE_SEL)
+#define BIT_SET_R_LEVEL_PULSE_SEL(x, v) \
+ (BIT_CLEAR_R_LEVEL_PULSE_SEL(x) | BIT_R_LEVEL_PULSE_SEL(v))
+
+#define BIT_EN_LA_MAC BIT(2)
+#define BIT_R_EN_IQDUMP BIT(1)
+#define BIT_R_IQDATA_DUMP BIT(0)
+
+#define BIT_SHIFT_R_CCK_LEN 0
+#define BIT_MASK_R_CCK_LEN 0xffff
+#define BIT_R_CCK_LEN(x) (((x) & BIT_MASK_R_CCK_LEN) << BIT_SHIFT_R_CCK_LEN)
+#define BITS_R_CCK_LEN (BIT_MASK_R_CCK_LEN << BIT_SHIFT_R_CCK_LEN)
+#define BIT_CLEAR_R_CCK_LEN(x) ((x) & (~BITS_R_CCK_LEN))
+#define BIT_GET_R_CCK_LEN(x) (((x) >> BIT_SHIFT_R_CCK_LEN) & BIT_MASK_R_CCK_LEN)
+#define BIT_SET_R_CCK_LEN(x, v) (BIT_CLEAR_R_CCK_LEN(x) | BIT_R_CCK_LEN(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_IQ_DUMP_1 (Offset 0x07C4) */
+
+#define BIT_SHIFT_R_WMAC_MASK_LA_MAC_1 0
+#define BIT_MASK_R_WMAC_MASK_LA_MAC_1 0xffffffffL
+#define BIT_R_WMAC_MASK_LA_MAC_1(x) \
+ (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_1) \
+ << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1)
+#define BITS_R_WMAC_MASK_LA_MAC_1 \
+ (BIT_MASK_R_WMAC_MASK_LA_MAC_1 << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1)
+#define BIT_CLEAR_R_WMAC_MASK_LA_MAC_1(x) ((x) & (~BITS_R_WMAC_MASK_LA_MAC_1))
+#define BIT_GET_R_WMAC_MASK_LA_MAC_1(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_1) & \
+ BIT_MASK_R_WMAC_MASK_LA_MAC_1)
+#define BIT_SET_R_WMAC_MASK_LA_MAC_1(x, v) \
+ (BIT_CLEAR_R_WMAC_MASK_LA_MAC_1(x) | BIT_R_WMAC_MASK_LA_MAC_1(v))
+
+/* 2 REG_IQ_DUMP_2 (Offset 0x07C8) */
+
+#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2 0
+#define BIT_MASK_R_WMAC_MATCH_REF_MAC_2 0xffffffffL
+#define BIT_R_WMAC_MATCH_REF_MAC_2(x) \
+ (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2) \
+ << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2)
+#define BITS_R_WMAC_MATCH_REF_MAC_2 \
+ (BIT_MASK_R_WMAC_MATCH_REF_MAC_2 << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2)
+#define BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2(x) \
+ ((x) & (~BITS_R_WMAC_MATCH_REF_MAC_2))
+#define BIT_GET_R_WMAC_MATCH_REF_MAC_2(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2) & \
+ BIT_MASK_R_WMAC_MATCH_REF_MAC_2)
+#define BIT_SET_R_WMAC_MATCH_REF_MAC_2(x, v) \
+ (BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2(x) | BIT_R_WMAC_MATCH_REF_MAC_2(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */
+/* 2 REG_WMAC_FTM_CTL (Offset 0x07CC) */
-#define BIT_R_WMAC_RXHANG_EN BIT(15)
+#define BIT_RXFTM_TXACK_SC BIT(6)
+#define BIT_RXFTM_TXACK_BW BIT(5)
+#define BIT_RXFTM_EN BIT(3)
+#define BIT_RXFTMREQ_BYDRV BIT(2)
+#define BIT_RXFTMREQ_EN BIT(1)
+#define BIT_FTM_EN BIT(0)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */
+/* 2 REG_IQ_DUMP_EXT (Offset 0x07CF) */
-#define BIT_DATA_RPFM15EN BIT(15)
+#define BIT_SHIFT_R_TIME_UNIT_SEL 0
+#define BIT_MASK_R_TIME_UNIT_SEL 0x7
+#define BIT_R_TIME_UNIT_SEL(x) \
+ (((x) & BIT_MASK_R_TIME_UNIT_SEL) << BIT_SHIFT_R_TIME_UNIT_SEL)
+#define BITS_R_TIME_UNIT_SEL \
+ (BIT_MASK_R_TIME_UNIT_SEL << BIT_SHIFT_R_TIME_UNIT_SEL)
+#define BIT_CLEAR_R_TIME_UNIT_SEL(x) ((x) & (~BITS_R_TIME_UNIT_SEL))
+#define BIT_GET_R_TIME_UNIT_SEL(x) \
+ (((x) >> BIT_SHIFT_R_TIME_UNIT_SEL) & BIT_MASK_R_TIME_UNIT_SEL)
+#define BIT_SET_R_TIME_UNIT_SEL(x, v) \
+ (BIT_CLEAR_R_TIME_UNIT_SEL(x) | BIT_R_TIME_UNIT_SEL(v))
#endif
+#if (HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_OFDM_CCK_LEN_MASK (Offset 0x07D0) */
+#define BIT_MICICV_CLR BIT(86)
+#define BIT_MPDU_RDY_SET BIT(85)
+#define BIT_CLR_SEC_TYPE BIT(84)
+#define BIT_NEWPKT_IN BIT(83)
+#define BIT_FCS_END BIT(82)
+#define BIT_DEL_MESH_TYPE BIT(81)
+#define BIT_MASK_MESH_TYPE BIT(80)
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_OPTION_FUNCTION (Offset 0x07D0) */
+
+#define BIT_SHIFT_R_OFDM_LEN_V1 16
+#define BIT_MASK_R_OFDM_LEN_V1 0xffff
+#define BIT_R_OFDM_LEN_V1(x) \
+ (((x) & BIT_MASK_R_OFDM_LEN_V1) << BIT_SHIFT_R_OFDM_LEN_V1)
+#define BITS_R_OFDM_LEN_V1 (BIT_MASK_R_OFDM_LEN_V1 << BIT_SHIFT_R_OFDM_LEN_V1)
+#define BIT_CLEAR_R_OFDM_LEN_V1(x) ((x) & (~BITS_R_OFDM_LEN_V1))
+#define BIT_GET_R_OFDM_LEN_V1(x) \
+ (((x) >> BIT_SHIFT_R_OFDM_LEN_V1) & BIT_MASK_R_OFDM_LEN_V1)
+#define BIT_SET_R_OFDM_LEN_V1(x, v) \
+ (BIT_CLEAR_R_OFDM_LEN_V1(x) | BIT_R_OFDM_LEN_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_OPTION_FUNCTION_1 (Offset 0x07D4) */
+
+#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1 24
+#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1 0xff
+#define BIT_R_WMAC_RXFIFO_FULL_TH_1(x) \
+ (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1) \
+ << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1)
+#define BITS_R_WMAC_RXFIFO_FULL_TH_1 \
+ (BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1 << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1)
+#define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1(x) \
+ ((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH_1))
+#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_1(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1) & \
+ BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1)
+#define BIT_SET_R_WMAC_RXFIFO_FULL_TH_1(x, v) \
+ (BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1(x) | BIT_R_WMAC_RXFIFO_FULL_TH_1(v))
+
+#define BIT_R_WMAC_RX_SYNCFIFO_SYNC_1 BIT(23)
+#define BIT_R_WMAC_RXRST_DLY_1 BIT(22)
+#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP_1 BIT(21)
+#define BIT_R_WMAC_SRCH_TXRPT_UA1_1 BIT(20)
+#define BIT_R_WMAC_SRCH_TXRPT_TYPE_1 BIT(19)
+#define BIT_R_WMAC_NDP_RST_1 BIT(18)
+#define BIT_R_WMAC_POWINT_EN_1 BIT(17)
+#define BIT_R_WMAC_SRCH_TXRPT_PERPKT_1 BIT(16)
+#define BIT_R_WMAC_SRCH_TXRPT_MID_1 BIT(15)
+#define BIT_R_WMAC_PFIN_TOEN_1 BIT(14)
+#define BIT_R_WMAC_FIL_SECERR_1 BIT(13)
+#define BIT_R_WMAC_FIL_CTLPKTLEN_1 BIT(12)
+#define BIT_R_WMAC_FIL_FCTYPE_1 BIT(11)
+#define BIT_R_WMAC_FIL_FCPROVER_1 BIT(10)
+#define BIT_R_WMAC_PHYSTS_SNIF_1 BIT(9)
+#define BIT_R_WMAC_PHYSTS_PLCP_1 BIT(8)
+#define BIT_R_MAC_TCR_VBONF_RD_1 BIT(7)
+#define BIT_R_WMAC_TCR_MPAR_NDP_1 BIT(6)
+#define BIT_R_WMAC_NDP_FILTER_1 BIT(5)
+#define BIT_R_WMAC_RXLEN_SEL_1 BIT(4)
+#define BIT_R_WMAC_RXLEN_SEL1_1 BIT(3)
+#define BIT_R_OFDM_FILTER_1 BIT(2)
+#define BIT_R_WMAC_CHK_OFDM_LEN_1 BIT(1)
+#define BIT_R_WMAC_CHK_CCK_LEN_1 BIT(0)
+
+/* 2 REG_WMAC_OPTION_FUNCTION_2 (Offset 0x07D8) */
+
+#define BIT_SHIFT_R_WMAC_RX_FIL_LEN_2 0
+#define BIT_MASK_R_WMAC_RX_FIL_LEN_2 0xffff
+#define BIT_R_WMAC_RX_FIL_LEN_2(x) \
+ (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_2) << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2)
+#define BITS_R_WMAC_RX_FIL_LEN_2 \
+ (BIT_MASK_R_WMAC_RX_FIL_LEN_2 << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2)
+#define BIT_CLEAR_R_WMAC_RX_FIL_LEN_2(x) ((x) & (~BITS_R_WMAC_RX_FIL_LEN_2))
+#define BIT_GET_R_WMAC_RX_FIL_LEN_2(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_2) & BIT_MASK_R_WMAC_RX_FIL_LEN_2)
+#define BIT_SET_R_WMAC_RX_FIL_LEN_2(x, v) \
+ (BIT_CLEAR_R_WMAC_RX_FIL_LEN_2(x) | BIT_R_WMAC_RX_FIL_LEN_2(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */
-#define BIT_R_WMAC_MHRDDY_LATCH BIT(14)
+#define BIT_R_WMAC_RXHANG_EN BIT(15)
#endif
-
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8822C_SUPPORT)
/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */
-#define BIT_DATA_RPFM14EN BIT(14)
+#define BIT_RXHANG_EN BIT(15)
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */
-#define BIT_R_MHRDDY_CLR BIT(13)
+#define BIT_R_WMAC_MHRDDY_LATCH BIT(14)
#endif
-
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */
-#define BIT_R_WMAC_MHRDDY_CLR BIT(13)
-#define BIT_DATA_RPFM13EN BIT(13)
+#define BIT_R_MHRDDY_CLR BIT(13)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */
-#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY1 BIT(12)
+#define BIT_R_WMAC_MHRDDY_CLR BIT(13)
#endif
-
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */
-#define BIT_DATA_RPFM12EN BIT(12)
+#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY1 BIT(12)
#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */
-#define BIT_R_WMAC_DIS_VHT_PLCP_CHK_MU BIT(11)
+#define BIT_R_WMAC_DIS_VHT_PLCP_CHK_MU BIT(11)
#endif
-
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */
-#define BIT_WMAC_DIS_VHT_PLCP_CHK_MU BIT(11)
-#define BIT_DATA_RPFM11EN BIT(11)
+#define BIT_WMAC_DIS_VHT_PLCP_CHK_MU BIT(11)
#endif
-
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */
-#define BIT_R_CHK_DELIMIT_LEN BIT(10)
+#define BIT_R_CHK_DELIMIT_LEN BIT(10)
+#define BIT_R_REAPTER_ADDR_MATCH BIT(9)
+#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY BIT(8)
+#define BIT_R_LATCH_MACHRDY BIT(7)
+#define BIT_R_WMAC_RXFIL_REND BIT(6)
+#define BIT_R_WMAC_MPDURDY_CLR BIT(5)
+#define BIT_R_WMAC_CLRRXSEC BIT(4)
+#define BIT_R_WMAC_RXFIL_RDEL BIT(3)
+#define BIT_R_WMAC_RXFIL_FCSE BIT(2)
+#define BIT_R_WMAC_RXFIL_MESH_DEL BIT(1)
+#define BIT_R_WMAC_RXFIL_MASKM BIT(0)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */
+/* 2 REG_NDP_SIG (Offset 0x07E0) */
-#define BIT_DATA_RPFM10EN BIT(10)
+#define BIT_SHIFT_R_WMAC_TXNDP_SIGB 0
+#define BIT_MASK_R_WMAC_TXNDP_SIGB 0x1fffff
+#define BIT_R_WMAC_TXNDP_SIGB(x) \
+ (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB) << BIT_SHIFT_R_WMAC_TXNDP_SIGB)
+#define BITS_R_WMAC_TXNDP_SIGB \
+ (BIT_MASK_R_WMAC_TXNDP_SIGB << BIT_SHIFT_R_WMAC_TXNDP_SIGB)
+#define BIT_CLEAR_R_WMAC_TXNDP_SIGB(x) ((x) & (~BITS_R_WMAC_TXNDP_SIGB))
+#define BIT_GET_R_WMAC_TXNDP_SIGB(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB) & BIT_MASK_R_WMAC_TXNDP_SIGB)
+#define BIT_SET_R_WMAC_TXNDP_SIGB(x, v) \
+ (BIT_CLEAR_R_WMAC_TXNDP_SIGB(x) | BIT_R_WMAC_TXNDP_SIGB(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_TXCMD_INFO_FOR_RSP_PKT (Offset 0x07E4) */
+#define BIT_SHIFT_R_MAC_DEBUG (32 & CPU_OPT_WIDTH)
+#define BIT_MASK_R_MAC_DEBUG 0xffffffffL
+#define BIT_R_MAC_DEBUG(x) \
+ (((x) & BIT_MASK_R_MAC_DEBUG) << BIT_SHIFT_R_MAC_DEBUG)
+#define BITS_R_MAC_DEBUG (BIT_MASK_R_MAC_DEBUG << BIT_SHIFT_R_MAC_DEBUG)
+#define BIT_CLEAR_R_MAC_DEBUG(x) ((x) & (~BITS_R_MAC_DEBUG))
+#define BIT_GET_R_MAC_DEBUG(x) \
+ (((x) >> BIT_SHIFT_R_MAC_DEBUG) & BIT_MASK_R_MAC_DEBUG)
+#define BIT_SET_R_MAC_DEBUG(x, v) \
+ (BIT_CLEAR_R_MAC_DEBUG(x) | BIT_R_MAC_DEBUG(v))
-/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */
+#endif
-#define BIT_R_REAPTER_ADDR_MATCH BIT(9)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_TXCMD_INFO_FOR_RSP_PKT (Offset 0x07E4) */
+#define BIT_SHIFT_R_MAC_DBG_SHIFT 8
+#define BIT_MASK_R_MAC_DBG_SHIFT 0x7
+#define BIT_R_MAC_DBG_SHIFT(x) \
+ (((x) & BIT_MASK_R_MAC_DBG_SHIFT) << BIT_SHIFT_R_MAC_DBG_SHIFT)
+#define BITS_R_MAC_DBG_SHIFT \
+ (BIT_MASK_R_MAC_DBG_SHIFT << BIT_SHIFT_R_MAC_DBG_SHIFT)
+#define BIT_CLEAR_R_MAC_DBG_SHIFT(x) ((x) & (~BITS_R_MAC_DBG_SHIFT))
+#define BIT_GET_R_MAC_DBG_SHIFT(x) \
+ (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT) & BIT_MASK_R_MAC_DBG_SHIFT)
+#define BIT_SET_R_MAC_DBG_SHIFT(x, v) \
+ (BIT_CLEAR_R_MAC_DBG_SHIFT(x) | BIT_R_MAC_DBG_SHIFT(v))
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#define BIT_SHIFT_R_MAC_DBG_SEL 0
+#define BIT_MASK_R_MAC_DBG_SEL 0x3
+#define BIT_R_MAC_DBG_SEL(x) \
+ (((x) & BIT_MASK_R_MAC_DBG_SEL) << BIT_SHIFT_R_MAC_DBG_SEL)
+#define BITS_R_MAC_DBG_SEL (BIT_MASK_R_MAC_DBG_SEL << BIT_SHIFT_R_MAC_DBG_SEL)
+#define BIT_CLEAR_R_MAC_DBG_SEL(x) ((x) & (~BITS_R_MAC_DBG_SEL))
+#define BIT_GET_R_MAC_DBG_SEL(x) \
+ (((x) >> BIT_SHIFT_R_MAC_DBG_SEL) & BIT_MASK_R_MAC_DBG_SEL)
+#define BIT_SET_R_MAC_DBG_SEL(x, v) \
+ (BIT_CLEAR_R_MAC_DBG_SEL(x) | BIT_R_MAC_DBG_SEL(v))
+#endif
-/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define BIT_DATA_RPFM9EN BIT(9)
+/* 2 REG_SEC_OPT (Offset 0x07E8) */
+
+#define BIT_MASK_IV BIT(18)
+#define BIT_EIVL_ENDIAN BIT(17)
+#define BIT_EIVH_ENDIAN BIT(16)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_SEC_OPT (Offset 0x07E8) */
+#define BIT_SHIFT_BT_TIME_CNT 0
+#define BIT_MASK_BT_TIME_CNT 0xff
+#define BIT_BT_TIME_CNT(x) \
+ (((x) & BIT_MASK_BT_TIME_CNT) << BIT_SHIFT_BT_TIME_CNT)
+#define BITS_BT_TIME_CNT (BIT_MASK_BT_TIME_CNT << BIT_SHIFT_BT_TIME_CNT)
+#define BIT_CLEAR_BT_TIME_CNT(x) ((x) & (~BITS_BT_TIME_CNT))
+#define BIT_GET_BT_TIME_CNT(x) \
+ (((x) >> BIT_SHIFT_BT_TIME_CNT) & BIT_MASK_BT_TIME_CNT)
+#define BIT_SET_BT_TIME_CNT(x, v) \
+ (BIT_CLEAR_BT_TIME_CNT(x) | BIT_BT_TIME_CNT(v))
-/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */
+#endif
-#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY BIT(8)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_1 (Offset 0x07E8) */
+#define BIT_SHIFT_R_MAC_DEBUG_1 0
+#define BIT_MASK_R_MAC_DEBUG_1 0xffffffffL
+#define BIT_R_MAC_DEBUG_1(x) \
+ (((x) & BIT_MASK_R_MAC_DEBUG_1) << BIT_SHIFT_R_MAC_DEBUG_1)
+#define BITS_R_MAC_DEBUG_1 (BIT_MASK_R_MAC_DEBUG_1 << BIT_SHIFT_R_MAC_DEBUG_1)
+#define BIT_CLEAR_R_MAC_DEBUG_1(x) ((x) & (~BITS_R_MAC_DEBUG_1))
+#define BIT_GET_R_MAC_DEBUG_1(x) \
+ (((x) >> BIT_SHIFT_R_MAC_DEBUG_1) & BIT_MASK_R_MAC_DEBUG_1)
+#define BIT_SET_R_MAC_DEBUG_1(x, v) \
+ (BIT_CLEAR_R_MAC_DEBUG_1(x) | BIT_R_MAC_DEBUG_1(v))
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */
+/* 2 REG_WSEC_OPTION (Offset 0x07EC) */
-#define BIT_DATA_RPFM8EN BIT(8)
+#define BIT_RXDEC_BM_MGNT BIT(22)
+#define BIT_TXENC_BM_MGNT BIT(21)
+#define BIT_RXDEC_UNI_MGNT BIT(20)
+#define BIT_TXENC_UNI_MGNT BIT(19)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+/* 2 REG_WSEC_OPTION (Offset 0x07EC) */
-/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */
+#define BIT_WMAC_SEC_MASKIV BIT(18)
-#define BIT_R_LATCH_MACHRDY BIT(7)
+#define BIT_SHIFT_WMAC_SEC_PN_SEL 16
+#define BIT_MASK_WMAC_SEC_PN_SEL 0x3
+#define BIT_WMAC_SEC_PN_SEL(x) \
+ (((x) & BIT_MASK_WMAC_SEC_PN_SEL) << BIT_SHIFT_WMAC_SEC_PN_SEL)
+#define BITS_WMAC_SEC_PN_SEL \
+ (BIT_MASK_WMAC_SEC_PN_SEL << BIT_SHIFT_WMAC_SEC_PN_SEL)
+#define BIT_CLEAR_WMAC_SEC_PN_SEL(x) ((x) & (~BITS_WMAC_SEC_PN_SEL))
+#define BIT_GET_WMAC_SEC_PN_SEL(x) \
+ (((x) >> BIT_SHIFT_WMAC_SEC_PN_SEL) & BIT_MASK_WMAC_SEC_PN_SEL)
+#define BIT_SET_WMAC_SEC_PN_SEL(x, v) \
+ (BIT_CLEAR_WMAC_SEC_PN_SEL(x) | BIT_WMAC_SEC_PN_SEL(v))
#endif
+#if (HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_RTS_ADDR0 (Offset 0x07F0) */
+#define BIT_SHIFT_RTS_ADDR0 0
+#define BIT_MASK_RTS_ADDR0 0xffffffffffffL
+#define BIT_RTS_ADDR0(x) (((x) & BIT_MASK_RTS_ADDR0) << BIT_SHIFT_RTS_ADDR0)
+#define BITS_RTS_ADDR0 (BIT_MASK_RTS_ADDR0 << BIT_SHIFT_RTS_ADDR0)
+#define BIT_CLEAR_RTS_ADDR0(x) ((x) & (~BITS_RTS_ADDR0))
+#define BIT_GET_RTS_ADDR0(x) (((x) >> BIT_SHIFT_RTS_ADDR0) & BIT_MASK_RTS_ADDR0)
+#define BIT_SET_RTS_ADDR0(x, v) (BIT_CLEAR_RTS_ADDR0(x) | BIT_RTS_ADDR0(v))
-/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */
+/* 2 REG_RTS_ADDR1 (Offset 0x07F8) */
-#define BIT_DATA_RPFM7EN BIT(7)
+#define BIT_SHIFT_RTS_ADDR1 0
+#define BIT_MASK_RTS_ADDR1 0xffffffffffffL
+#define BIT_RTS_ADDR1(x) (((x) & BIT_MASK_RTS_ADDR1) << BIT_SHIFT_RTS_ADDR1)
+#define BITS_RTS_ADDR1 (BIT_MASK_RTS_ADDR1 << BIT_SHIFT_RTS_ADDR1)
+#define BIT_CLEAR_RTS_ADDR1(x) ((x) & (~BITS_RTS_ADDR1))
+#define BIT_GET_RTS_ADDR1(x) (((x) >> BIT_SHIFT_RTS_ADDR1) & BIT_MASK_RTS_ADDR1)
+#define BIT_SET_RTS_ADDR1(x, v) (BIT_CLEAR_RTS_ADDR1(x) | BIT_RTS_ADDR1(v))
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG__RPFM_MAP1 (Offset 0x07FE) */
+#define BIT_DATA_RPFM15EN BIT(15)
+#define BIT_DATA_RPFM14EN BIT(14)
+#define BIT_DATA_RPFM13EN BIT(13)
+#define BIT_DATA_RPFM12EN BIT(12)
+#define BIT_DATA_RPFM11EN BIT(11)
+#define BIT_DATA_RPFM10EN BIT(10)
+#define BIT_DATA_RPFM9EN BIT(9)
+#define BIT_DATA_RPFM8EN BIT(8)
+#define BIT_DATA_RPFM7EN BIT(7)
+#define BIT_DATA_RPFM6EN BIT(6)
+#define BIT_DATA_RPFM5EN BIT(5)
+#define BIT_DATA_RPFM4EN BIT(4)
+#define BIT_DATA_RPFM3EN BIT(3)
+#define BIT_DATA_RPFM2EN BIT(2)
+#define BIT_DATA_RPFM1EN BIT(1)
+#define BIT_DATA_RPFM0EN BIT(0)
-/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */
+#endif
-#define BIT_R_WMAC_RXFIL_REND BIT(6)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#endif
+/* 2 REG_SYS_CFG3 (Offset 0x1000) */
+#define BIT_FEN_BB_GLB_RSTN_V1 BIT(17)
+#define BIT_FEN_BBRSTB_V1 BIT(16)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT)
-/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */
+/* 2 REG_SYS_CFG3 (Offset 0x1000) */
-#define BIT_DATA_RPFM6EN BIT(6)
+#define BIT_PWC_MA33V BIT(15)
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_SYS_CFG3 (Offset 0x1000) */
+#define BIT_PWC_EV25V_1 BIT(14)
-/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */
+#endif
-#define BIT_R_WMAC_MPDURDY_CLR BIT(5)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT)
-#endif
+/* 2 REG_SYS_CFG3 (Offset 0x1000) */
+#define BIT_PWC_MA12V BIT(14)
+#define BIT_PWC_MD12V BIT(13)
+#define BIT_PWC_PD12V BIT(12)
+#define BIT_PWC_UD12V BIT(11)
+#define BIT_ISO_MA2MD BIT(1)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */
+/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */
-#define BIT_DATA_RPFM5EN BIT(5)
+#define BIT_OCP_L_0 BIT(31)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */
+#define BIT_OCP_L BIT(31)
-/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */
+#endif
-#define BIT_R_WMAC_CLRRXSEC BIT(4)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */
+#define BIT_POWOCP_L BIT(30)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */
+/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */
-#define BIT_DATA_RPFM4EN BIT(4)
+#define BIT_SHIFT_CF_L_1_0 28
+#define BIT_MASK_CF_L_1_0 0x3
+#define BIT_CF_L_1_0(x) (((x) & BIT_MASK_CF_L_1_0) << BIT_SHIFT_CF_L_1_0)
+#define BITS_CF_L_1_0 (BIT_MASK_CF_L_1_0 << BIT_SHIFT_CF_L_1_0)
+#define BIT_CLEAR_CF_L_1_0(x) ((x) & (~BITS_CF_L_1_0))
+#define BIT_GET_CF_L_1_0(x) (((x) >> BIT_SHIFT_CF_L_1_0) & BIT_MASK_CF_L_1_0)
+#define BIT_SET_CF_L_1_0(x, v) (BIT_CLEAR_CF_L_1_0(x) | BIT_CF_L_1_0(v))
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */
+#define BIT_SHIFT_CF_L_V2 28
+#define BIT_MASK_CF_L_V2 0x3
+#define BIT_CF_L_V2(x) (((x) & BIT_MASK_CF_L_V2) << BIT_SHIFT_CF_L_V2)
+#define BITS_CF_L_V2 (BIT_MASK_CF_L_V2 << BIT_SHIFT_CF_L_V2)
+#define BIT_CLEAR_CF_L_V2(x) ((x) & (~BITS_CF_L_V2))
+#define BIT_GET_CF_L_V2(x) (((x) >> BIT_SHIFT_CF_L_V2) & BIT_MASK_CF_L_V2)
+#define BIT_SET_CF_L_V2(x, v) (BIT_CLEAR_CF_L_V2(x) | BIT_CF_L_V2(v))
-/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */
+#endif
-#define BIT_R_WMAC_RXFIL_RDEL BIT(3)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */
+#define BIT_SHIFT_CFC_L_1_0 26
+#define BIT_MASK_CFC_L_1_0 0x3
+#define BIT_CFC_L_1_0(x) (((x) & BIT_MASK_CFC_L_1_0) << BIT_SHIFT_CFC_L_1_0)
+#define BITS_CFC_L_1_0 (BIT_MASK_CFC_L_1_0 << BIT_SHIFT_CFC_L_1_0)
+#define BIT_CLEAR_CFC_L_1_0(x) ((x) & (~BITS_CFC_L_1_0))
+#define BIT_GET_CFC_L_1_0(x) (((x) >> BIT_SHIFT_CFC_L_1_0) & BIT_MASK_CFC_L_1_0)
+#define BIT_SET_CFC_L_1_0(x, v) (BIT_CLEAR_CFC_L_1_0(x) | BIT_CFC_L_1_0(v))
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8822C_SUPPORT)
-/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */
+/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */
-#define BIT_DATA_RPFM3EN BIT(3)
+#define BIT_SHIFT_CFC_L_V2 26
+#define BIT_MASK_CFC_L_V2 0x3
+#define BIT_CFC_L_V2(x) (((x) & BIT_MASK_CFC_L_V2) << BIT_SHIFT_CFC_L_V2)
+#define BITS_CFC_L_V2 (BIT_MASK_CFC_L_V2 << BIT_SHIFT_CFC_L_V2)
+#define BIT_CLEAR_CFC_L_V2(x) ((x) & (~BITS_CFC_L_V2))
+#define BIT_GET_CFC_L_V2(x) (((x) >> BIT_SHIFT_CFC_L_V2) & BIT_MASK_CFC_L_V2)
+#define BIT_SET_CFC_L_V2(x, v) (BIT_CLEAR_CFC_L_V2(x) | BIT_CFC_L_V2(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */
+#define BIT_SHIFT_R3_L_1_0 24
+#define BIT_MASK_R3_L_1_0 0x3
+#define BIT_R3_L_1_0(x) (((x) & BIT_MASK_R3_L_1_0) << BIT_SHIFT_R3_L_1_0)
+#define BITS_R3_L_1_0 (BIT_MASK_R3_L_1_0 << BIT_SHIFT_R3_L_1_0)
+#define BIT_CLEAR_R3_L_1_0(x) ((x) & (~BITS_R3_L_1_0))
+#define BIT_GET_R3_L_1_0(x) (((x) >> BIT_SHIFT_R3_L_1_0) & BIT_MASK_R3_L_1_0)
+#define BIT_SET_R3_L_1_0(x, v) (BIT_CLEAR_R3_L_1_0(x) | BIT_R3_L_1_0(v))
-/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */
+#endif
-#define BIT_R_WMAC_RXFIL_FCSE BIT(2)
+#if (HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */
+#define BIT_SHIFT_R3_L_V2 24
+#define BIT_MASK_R3_L_V2 0x3
+#define BIT_R3_L_V2(x) (((x) & BIT_MASK_R3_L_V2) << BIT_SHIFT_R3_L_V2)
+#define BITS_R3_L_V2 (BIT_MASK_R3_L_V2 << BIT_SHIFT_R3_L_V2)
+#define BIT_CLEAR_R3_L_V2(x) ((x) & (~BITS_R3_L_V2))
+#define BIT_GET_R3_L_V2(x) (((x) >> BIT_SHIFT_R3_L_V2) & BIT_MASK_R3_L_V2)
+#define BIT_SET_R3_L_V2(x, v) (BIT_CLEAR_R3_L_V2(x) | BIT_R3_L_V2(v))
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */
+/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */
-#define BIT_DATA_RPFM2EN BIT(2)
+#define BIT_SHIFT_R2_L_1_0 22
+#define BIT_MASK_R2_L_1_0 0x3
+#define BIT_R2_L_1_0(x) (((x) & BIT_MASK_R2_L_1_0) << BIT_SHIFT_R2_L_1_0)
+#define BITS_R2_L_1_0 (BIT_MASK_R2_L_1_0 << BIT_SHIFT_R2_L_1_0)
+#define BIT_CLEAR_R2_L_1_0(x) ((x) & (~BITS_R2_L_1_0))
+#define BIT_GET_R2_L_1_0(x) (((x) >> BIT_SHIFT_R2_L_1_0) & BIT_MASK_R2_L_1_0)
+#define BIT_SET_R2_L_1_0(x, v) (BIT_CLEAR_R2_L_1_0(x) | BIT_R2_L_1_0(v))
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */
+#define BIT_SHIFT_R2_L 22
+#define BIT_MASK_R2_L 0x3
+#define BIT_R2_L(x) (((x) & BIT_MASK_R2_L) << BIT_SHIFT_R2_L)
+#define BITS_R2_L (BIT_MASK_R2_L << BIT_SHIFT_R2_L)
+#define BIT_CLEAR_R2_L(x) ((x) & (~BITS_R2_L))
+#define BIT_GET_R2_L(x) (((x) >> BIT_SHIFT_R2_L) & BIT_MASK_R2_L)
+#define BIT_SET_R2_L(x, v) (BIT_CLEAR_R2_L(x) | BIT_R2_L(v))
-/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */
+#endif
-#define BIT_R_WMAC_RXFIL_MESH_DEL BIT(1)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */
+#define BIT_SHIFT_R1_L_1_0 20
+#define BIT_MASK_R1_L_1_0 0x3
+#define BIT_R1_L_1_0(x) (((x) & BIT_MASK_R1_L_1_0) << BIT_SHIFT_R1_L_1_0)
+#define BITS_R1_L_1_0 (BIT_MASK_R1_L_1_0 << BIT_SHIFT_R1_L_1_0)
+#define BIT_CLEAR_R1_L_1_0(x) ((x) & (~BITS_R1_L_1_0))
+#define BIT_GET_R1_L_1_0(x) (((x) >> BIT_SHIFT_R1_L_1_0) & BIT_MASK_R1_L_1_0)
+#define BIT_SET_R1_L_1_0(x, v) (BIT_CLEAR_R1_L_1_0(x) | BIT_R1_L_1_0(v))
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8822C_SUPPORT)
-/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */
+/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */
-#define BIT_DATA_RPFM1EN BIT(1)
+#define BIT_SHIFT_R1_L 20
+#define BIT_MASK_R1_L 0x3
+#define BIT_R1_L(x) (((x) & BIT_MASK_R1_L) << BIT_SHIFT_R1_L)
+#define BITS_R1_L (BIT_MASK_R1_L << BIT_SHIFT_R1_L)
+#define BIT_CLEAR_R1_L(x) ((x) & (~BITS_R1_L))
+#define BIT_GET_R1_L(x) (((x) >> BIT_SHIFT_R1_L) & BIT_MASK_R1_L)
+#define BIT_SET_R1_L(x, v) (BIT_CLEAR_R1_L(x) | BIT_R1_L(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */
+#define BIT_SHIFT_C3_L_1_0 18
+#define BIT_MASK_C3_L_1_0 0x3
+#define BIT_C3_L_1_0(x) (((x) & BIT_MASK_C3_L_1_0) << BIT_SHIFT_C3_L_1_0)
+#define BITS_C3_L_1_0 (BIT_MASK_C3_L_1_0 << BIT_SHIFT_C3_L_1_0)
+#define BIT_CLEAR_C3_L_1_0(x) ((x) & (~BITS_C3_L_1_0))
+#define BIT_GET_C3_L_1_0(x) (((x) >> BIT_SHIFT_C3_L_1_0) & BIT_MASK_C3_L_1_0)
+#define BIT_SET_C3_L_1_0(x, v) (BIT_CLEAR_C3_L_1_0(x) | BIT_C3_L_1_0(v))
-/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */
+#endif
-#define BIT_R_WMAC_RXFIL_MASKM BIT(0)
+#if (HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */
+#define BIT_SHIFT_C3_L 18
+#define BIT_MASK_C3_L 0x3
+#define BIT_C3_L(x) (((x) & BIT_MASK_C3_L) << BIT_SHIFT_C3_L)
+#define BITS_C3_L (BIT_MASK_C3_L << BIT_SHIFT_C3_L)
+#define BIT_CLEAR_C3_L(x) ((x) & (~BITS_C3_L))
+#define BIT_GET_C3_L(x) (((x) >> BIT_SHIFT_C3_L) & BIT_MASK_C3_L)
+#define BIT_SET_C3_L(x, v) (BIT_CLEAR_C3_L(x) | BIT_C3_L(v))
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */
+/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */
-#define BIT_DATA_RPFM0EN BIT(0)
+#define BIT_SHIFT_C2_L_1_0 16
+#define BIT_MASK_C2_L_1_0 0x3
+#define BIT_C2_L_1_0(x) (((x) & BIT_MASK_C2_L_1_0) << BIT_SHIFT_C2_L_1_0)
+#define BITS_C2_L_1_0 (BIT_MASK_C2_L_1_0 << BIT_SHIFT_C2_L_1_0)
+#define BIT_CLEAR_C2_L_1_0(x) ((x) & (~BITS_C2_L_1_0))
+#define BIT_GET_C2_L_1_0(x) (((x) >> BIT_SHIFT_C2_L_1_0) & BIT_MASK_C2_L_1_0)
+#define BIT_SET_C2_L_1_0(x, v) (BIT_CLEAR_C2_L_1_0(x) | BIT_C2_L_1_0(v))
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */
+#define BIT_SHIFT_C2_L 16
+#define BIT_MASK_C2_L 0x3
+#define BIT_C2_L(x) (((x) & BIT_MASK_C2_L) << BIT_SHIFT_C2_L)
+#define BITS_C2_L (BIT_MASK_C2_L << BIT_SHIFT_C2_L)
+#define BIT_CLEAR_C2_L(x) ((x) & (~BITS_C2_L))
+#define BIT_GET_C2_L(x) (((x) >> BIT_SHIFT_C2_L) & BIT_MASK_C2_L)
+#define BIT_SET_C2_L(x, v) (BIT_CLEAR_C2_L(x) | BIT_C2_L(v))
-/* 2 REG_NDP_SIG (Offset 0x07E0) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_R_WMAC_TXNDP_SIGB 0
-#define BIT_MASK_R_WMAC_TXNDP_SIGB 0x1fffff
-#define BIT_R_WMAC_TXNDP_SIGB(x) (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB) << BIT_SHIFT_R_WMAC_TXNDP_SIGB)
-#define BIT_GET_R_WMAC_TXNDP_SIGB(x) (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB) & BIT_MASK_R_WMAC_TXNDP_SIGB)
+/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */
+#define BIT_SHIFT_C1_L_1_0 14
+#define BIT_MASK_C1_L_1_0 0x3
+#define BIT_C1_L_1_0(x) (((x) & BIT_MASK_C1_L_1_0) << BIT_SHIFT_C1_L_1_0)
+#define BITS_C1_L_1_0 (BIT_MASK_C1_L_1_0 << BIT_SHIFT_C1_L_1_0)
+#define BIT_CLEAR_C1_L_1_0(x) ((x) & (~BITS_C1_L_1_0))
+#define BIT_GET_C1_L_1_0(x) (((x) >> BIT_SHIFT_C1_L_1_0) & BIT_MASK_C1_L_1_0)
+#define BIT_SET_C1_L_1_0(x, v) (BIT_CLEAR_C1_L_1_0(x) | BIT_C1_L_1_0(v))
-/* 2 REG_TXCMD_INFO_FOR_RSP_PKT (Offset 0x07E4) */
+#endif
+#if (HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_R_MAC_DEBUG (32 & CPU_OPT_WIDTH)
-#define BIT_MASK_R_MAC_DEBUG 0xffffffffL
-#define BIT_R_MAC_DEBUG(x) (((x) & BIT_MASK_R_MAC_DEBUG) << BIT_SHIFT_R_MAC_DEBUG)
-#define BIT_GET_R_MAC_DEBUG(x) (((x) >> BIT_SHIFT_R_MAC_DEBUG) & BIT_MASK_R_MAC_DEBUG)
+/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */
+#define BIT_SHIFT_C1_L_V2 14
+#define BIT_MASK_C1_L_V2 0x3
+#define BIT_C1_L_V2(x) (((x) & BIT_MASK_C1_L_V2) << BIT_SHIFT_C1_L_V2)
+#define BITS_C1_L_V2 (BIT_MASK_C1_L_V2 << BIT_SHIFT_C1_L_V2)
+#define BIT_CLEAR_C1_L_V2(x) ((x) & (~BITS_C1_L_V2))
+#define BIT_GET_C1_L_V2(x) (((x) >> BIT_SHIFT_C1_L_V2) & BIT_MASK_C1_L_V2)
+#define BIT_SET_C1_L_V2(x, v) (BIT_CLEAR_C1_L_V2(x) | BIT_C1_L_V2(v))
-#define BIT_SHIFT_R_MAC_DBG_SHIFT 8
-#define BIT_MASK_R_MAC_DBG_SHIFT 0x7
-#define BIT_R_MAC_DBG_SHIFT(x) (((x) & BIT_MASK_R_MAC_DBG_SHIFT) << BIT_SHIFT_R_MAC_DBG_SHIFT)
-#define BIT_GET_R_MAC_DBG_SHIFT(x) (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT) & BIT_MASK_R_MAC_DBG_SHIFT)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_R_MAC_DBG_SEL 0
-#define BIT_MASK_R_MAC_DBG_SEL 0x3
-#define BIT_R_MAC_DBG_SEL(x) (((x) & BIT_MASK_R_MAC_DBG_SEL) << BIT_SHIFT_R_MAC_DBG_SEL)
-#define BIT_GET_R_MAC_DBG_SEL(x) (((x) >> BIT_SHIFT_R_MAC_DBG_SEL) & BIT_MASK_R_MAC_DBG_SEL)
+/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */
+#define BIT_REG_TYPE_L_V2 BIT(13)
+#define BIT_REG_PWM_L BIT(12)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8821C_SUPPORT)
-
-
-/* 2 REG_WSEC_OPTION (Offset 0x07EC) */
+/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */
-#define BIT_RXDEC_BM_MGNT BIT(22)
-#define BIT_TXENC_BM_MGNT BIT(21)
-#define BIT_RXDEC_UNI_MGNT BIT(20)
-#define BIT_TXENC_UNI_MGNT BIT(19)
+#define BIT_SHIFT_V15ADJ_L_2_0 9
+#define BIT_MASK_V15ADJ_L_2_0 0x7
+#define BIT_V15ADJ_L_2_0(x) \
+ (((x) & BIT_MASK_V15ADJ_L_2_0) << BIT_SHIFT_V15ADJ_L_2_0)
+#define BITS_V15ADJ_L_2_0 (BIT_MASK_V15ADJ_L_2_0 << BIT_SHIFT_V15ADJ_L_2_0)
+#define BIT_CLEAR_V15ADJ_L_2_0(x) ((x) & (~BITS_V15ADJ_L_2_0))
+#define BIT_GET_V15ADJ_L_2_0(x) \
+ (((x) >> BIT_SHIFT_V15ADJ_L_2_0) & BIT_MASK_V15ADJ_L_2_0)
+#define BIT_SET_V15ADJ_L_2_0(x, v) \
+ (BIT_CLEAR_V15ADJ_L_2_0(x) | BIT_V15ADJ_L_2_0(v))
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */
+#define BIT_SHIFT_V15ADJ_L 9
+#define BIT_MASK_V15ADJ_L 0x7
+#define BIT_V15ADJ_L(x) (((x) & BIT_MASK_V15ADJ_L) << BIT_SHIFT_V15ADJ_L)
+#define BITS_V15ADJ_L (BIT_MASK_V15ADJ_L << BIT_SHIFT_V15ADJ_L)
+#define BIT_CLEAR_V15ADJ_L(x) ((x) & (~BITS_V15ADJ_L))
+#define BIT_GET_V15ADJ_L(x) (((x) >> BIT_SHIFT_V15ADJ_L) & BIT_MASK_V15ADJ_L)
+#define BIT_SET_V15ADJ_L(x, v) (BIT_CLEAR_V15ADJ_L(x) | BIT_V15ADJ_L(v))
-/* 2 REG_SEC_OPT_V2 (Offset 0x07EC) */
+#endif
-#define BIT_MASK_IV BIT(18)
-#define BIT_EIVL_ENDIAN BIT(17)
-#define BIT_EIVH_ENDIAN BIT(16)
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_BT_TIME_CNT 0
-#define BIT_MASK_BT_TIME_CNT 0xff
-#define BIT_BT_TIME_CNT(x) (((x) & BIT_MASK_BT_TIME_CNT) << BIT_SHIFT_BT_TIME_CNT)
-#define BIT_GET_BT_TIME_CNT(x) (((x) >> BIT_SHIFT_BT_TIME_CNT) & BIT_MASK_BT_TIME_CNT)
+/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */
+#define BIT_SHIFT_IN_L_2_0 6
+#define BIT_MASK_IN_L_2_0 0x7
+#define BIT_IN_L_2_0(x) (((x) & BIT_MASK_IN_L_2_0) << BIT_SHIFT_IN_L_2_0)
+#define BITS_IN_L_2_0 (BIT_MASK_IN_L_2_0 << BIT_SHIFT_IN_L_2_0)
+#define BIT_CLEAR_IN_L_2_0(x) ((x) & (~BITS_IN_L_2_0))
+#define BIT_GET_IN_L_2_0(x) (((x) >> BIT_SHIFT_IN_L_2_0) & BIT_MASK_IN_L_2_0)
+#define BIT_SET_IN_L_2_0(x, v) (BIT_CLEAR_IN_L_2_0(x) | BIT_IN_L_2_0(v))
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814AMP_SUPPORT)
+/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */
+#define BIT_SHIFT_IN_L 6
+#define BIT_MASK_IN_L 0x7
+#define BIT_IN_L(x) (((x) & BIT_MASK_IN_L) << BIT_SHIFT_IN_L)
+#define BITS_IN_L (BIT_MASK_IN_L << BIT_SHIFT_IN_L)
+#define BIT_CLEAR_IN_L(x) ((x) & (~BITS_IN_L))
+#define BIT_GET_IN_L(x) (((x) >> BIT_SHIFT_IN_L) & BIT_MASK_IN_L)
+#define BIT_SET_IN_L(x, v) (BIT_CLEAR_IN_L(x) | BIT_IN_L(v))
-/* 2 REG_RTS_ADDR0 (Offset 0x07F0) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_RTS_ADDR0 0
-#define BIT_MASK_RTS_ADDR0 0xffffffffffffL
-#define BIT_RTS_ADDR0(x) (((x) & BIT_MASK_RTS_ADDR0) << BIT_SHIFT_RTS_ADDR0)
-#define BIT_GET_RTS_ADDR0(x) (((x) >> BIT_SHIFT_RTS_ADDR0) & BIT_MASK_RTS_ADDR0)
+/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */
+#define BIT_SHIFT_STD_L_1_0 4
+#define BIT_MASK_STD_L_1_0 0x3
+#define BIT_STD_L_1_0(x) (((x) & BIT_MASK_STD_L_1_0) << BIT_SHIFT_STD_L_1_0)
+#define BITS_STD_L_1_0 (BIT_MASK_STD_L_1_0 << BIT_SHIFT_STD_L_1_0)
+#define BIT_CLEAR_STD_L_1_0(x) ((x) & (~BITS_STD_L_1_0))
+#define BIT_GET_STD_L_1_0(x) (((x) >> BIT_SHIFT_STD_L_1_0) & BIT_MASK_STD_L_1_0)
+#define BIT_SET_STD_L_1_0(x, v) (BIT_CLEAR_STD_L_1_0(x) | BIT_STD_L_1_0(v))
-/* 2 REG_RTS_ADDR1 (Offset 0x07F8) */
+#endif
+#if (HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_RTS_ADDR1 0
-#define BIT_MASK_RTS_ADDR1 0xffffffffffffL
-#define BIT_RTS_ADDR1(x) (((x) & BIT_MASK_RTS_ADDR1) << BIT_SHIFT_RTS_ADDR1)
-#define BIT_GET_RTS_ADDR1(x) (((x) >> BIT_SHIFT_RTS_ADDR1) & BIT_MASK_RTS_ADDR1)
+/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */
+#define BIT_SHIFT_STD_L 4
+#define BIT_MASK_STD_L 0x3
+#define BIT_STD_L(x) (((x) & BIT_MASK_STD_L) << BIT_SHIFT_STD_L)
+#define BITS_STD_L (BIT_MASK_STD_L << BIT_SHIFT_STD_L)
+#define BIT_CLEAR_STD_L(x) ((x) & (~BITS_STD_L))
+#define BIT_GET_STD_L(x) (((x) >> BIT_SHIFT_STD_L) & BIT_MASK_STD_L)
+#define BIT_SET_STD_L(x, v) (BIT_CLEAR_STD_L(x) | BIT_STD_L(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
-
-/* 2 REG_SYS_CFG3 (Offset 0x1000) */
+/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */
-#define BIT_FEN_BB_GLB_RSTN_V1 BIT(17)
-#define BIT_FEN_BBRSTB_V1 BIT(16)
+#define BIT_SHIFT_VOL_L_3_0 0
+#define BIT_MASK_VOL_L_3_0 0xf
+#define BIT_VOL_L_3_0(x) (((x) & BIT_MASK_VOL_L_3_0) << BIT_SHIFT_VOL_L_3_0)
+#define BITS_VOL_L_3_0 (BIT_MASK_VOL_L_3_0 << BIT_SHIFT_VOL_L_3_0)
+#define BIT_CLEAR_VOL_L_3_0(x) ((x) & (~BITS_VOL_L_3_0))
+#define BIT_GET_VOL_L_3_0(x) (((x) >> BIT_SHIFT_VOL_L_3_0) & BIT_MASK_VOL_L_3_0)
+#define BIT_SET_VOL_L_3_0(x, v) (BIT_CLEAR_VOL_L_3_0(x) | BIT_VOL_L_3_0(v))
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ANAPARSW_MAC_0 (Offset 0x1010) */
+#define BIT_SHIFT_VOL_L 0
+#define BIT_MASK_VOL_L 0xf
+#define BIT_VOL_L(x) (((x) & BIT_MASK_VOL_L) << BIT_SHIFT_VOL_L)
+#define BITS_VOL_L (BIT_MASK_VOL_L << BIT_SHIFT_VOL_L)
+#define BIT_CLEAR_VOL_L(x) ((x) & (~BITS_VOL_L))
+#define BIT_GET_VOL_L(x) (((x) >> BIT_SHIFT_VOL_L) & BIT_MASK_VOL_L)
+#define BIT_SET_VOL_L(x, v) (BIT_CLEAR_VOL_L(x) | BIT_VOL_L(v))
-/* 2 REG_SYS_CFG3 (Offset 0x1000) */
+/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */
-#define BIT_PWC_MA33V BIT(15)
+#define BIT_SHIFT_OCP_L_PFM 29
+#define BIT_MASK_OCP_L_PFM 0x7
+#define BIT_OCP_L_PFM(x) (((x) & BIT_MASK_OCP_L_PFM) << BIT_SHIFT_OCP_L_PFM)
+#define BITS_OCP_L_PFM (BIT_MASK_OCP_L_PFM << BIT_SHIFT_OCP_L_PFM)
+#define BIT_CLEAR_OCP_L_PFM(x) ((x) & (~BITS_OCP_L_PFM))
+#define BIT_GET_OCP_L_PFM(x) (((x) >> BIT_SHIFT_OCP_L_PFM) & BIT_MASK_OCP_L_PFM)
+#define BIT_SET_OCP_L_PFM(x, v) (BIT_CLEAR_OCP_L_PFM(x) | BIT_OCP_L_PFM(v))
-#endif
+#define BIT_SHIFT_CFC_L_PFM 27
+#define BIT_MASK_CFC_L_PFM 0x3
+#define BIT_CFC_L_PFM(x) (((x) & BIT_MASK_CFC_L_PFM) << BIT_SHIFT_CFC_L_PFM)
+#define BITS_CFC_L_PFM (BIT_MASK_CFC_L_PFM << BIT_SHIFT_CFC_L_PFM)
+#define BIT_CLEAR_CFC_L_PFM(x) ((x) & (~BITS_CFC_L_PFM))
+#define BIT_GET_CFC_L_PFM(x) (((x) >> BIT_SHIFT_CFC_L_PFM) & BIT_MASK_CFC_L_PFM)
+#define BIT_SET_CFC_L_PFM(x, v) (BIT_CLEAR_CFC_L_PFM(x) | BIT_CFC_L_PFM(v))
+#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */
-/* 2 REG_SYS_CFG3 (Offset 0x1000) */
+#define BIT_SHIFT_REG_FREQ_L_V1 20
+#define BIT_MASK_REG_FREQ_L_V1 0x7
+#define BIT_REG_FREQ_L_V1(x) \
+ (((x) & BIT_MASK_REG_FREQ_L_V1) << BIT_SHIFT_REG_FREQ_L_V1)
+#define BITS_REG_FREQ_L_V1 (BIT_MASK_REG_FREQ_L_V1 << BIT_SHIFT_REG_FREQ_L_V1)
+#define BIT_CLEAR_REG_FREQ_L_V1(x) ((x) & (~BITS_REG_FREQ_L_V1))
+#define BIT_GET_REG_FREQ_L_V1(x) \
+ (((x) >> BIT_SHIFT_REG_FREQ_L_V1) & BIT_MASK_REG_FREQ_L_V1)
+#define BIT_SET_REG_FREQ_L_V1(x, v) \
+ (BIT_CLEAR_REG_FREQ_L_V1(x) | BIT_REG_FREQ_L_V1(v))
-#define BIT_PWC_EV25V_1 BIT(14)
+#define BIT_EN_DUTY BIT(19)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */
+#define BIT_SHIFT_REG_MOS_HALF 17
+#define BIT_MASK_REG_MOS_HALF 0x3
+#define BIT_REG_MOS_HALF(x) \
+ (((x) & BIT_MASK_REG_MOS_HALF) << BIT_SHIFT_REG_MOS_HALF)
+#define BITS_REG_MOS_HALF (BIT_MASK_REG_MOS_HALF << BIT_SHIFT_REG_MOS_HALF)
+#define BIT_CLEAR_REG_MOS_HALF(x) ((x) & (~BITS_REG_MOS_HALF))
+#define BIT_GET_REG_MOS_HALF(x) \
+ (((x) >> BIT_SHIFT_REG_MOS_HALF) & BIT_MASK_REG_MOS_HALF)
+#define BIT_SET_REG_MOS_HALF(x, v) \
+ (BIT_CLEAR_REG_MOS_HALF(x) | BIT_REG_MOS_HALF(v))
-/* 2 REG_SYS_CFG3 (Offset 0x1000) */
+#endif
-#define BIT_PWC_MA12V BIT(14)
-#define BIT_PWC_MD12V BIT(13)
-#define BIT_PWC_PD12V BIT(12)
-#define BIT_PWC_UD12V BIT(11)
-#define BIT_ISO_MA2MD BIT(1)
+#if (HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */
+#define BIT_SHIFT_REG_MODE_V2 17
+#define BIT_MASK_REG_MODE_V2 0x3
+#define BIT_REG_MODE_V2(x) \
+ (((x) & BIT_MASK_REG_MODE_V2) << BIT_SHIFT_REG_MODE_V2)
+#define BITS_REG_MODE_V2 (BIT_MASK_REG_MODE_V2 << BIT_SHIFT_REG_MODE_V2)
+#define BIT_CLEAR_REG_MODE_V2(x) ((x) & (~BITS_REG_MODE_V2))
+#define BIT_GET_REG_MODE_V2(x) \
+ (((x) >> BIT_SHIFT_REG_MODE_V2) & BIT_MASK_REG_MODE_V2)
+#define BIT_SET_REG_MODE_V2(x, v) \
+ (BIT_CLEAR_REG_MODE_V2(x) | BIT_REG_MODE_V2(v))
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_SYS_CFG4 (Offset 0x1034) */
+/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */
-#define BIT_EF_CSER_1 BIT(26)
-#define BIT_SW_PG_EN_1 BIT(10)
+#define BIT_EN_SP BIT(16)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */
+#define BIT_REG_AUTO_L_V1 BIT(15)
-/* 2 REG_SYS_CFG5 (Offset 0x1070) */
+#endif
-#define BIT_LPS_STATUS BIT(3)
-#define BIT_HCI_TXDMA_BUSY BIT(2)
-#define BIT_HCI_TXDMA_ALLOW BIT(1)
-#define BIT_FW_CTRL_HCI_TXDMA_EN BIT(0)
+#if (HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */
+#define BIT_REG_AUTO_L_V2 BIT(15)
-#if (HALMAC_8821C_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */
+/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */
-#define BIT_WDT_AUTO_MODE BIT(22)
-#define BIT_WDT_PLATFORM_EN BIT(21)
-#define BIT_WDT_CPU_EN BIT(20)
+#define BIT_REG_LDOF_L_V2 BIT(14)
+#define BIT_REG_OCPS_L_V2 BIT(13)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */
+#define BIT_VO15_V1P05_H BIT(12)
-/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */
+#endif
-#define BIT_WDT_OPT_IOWRAPPER BIT(19)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */
+#define BIT_ARENB_L_V1 BIT(11)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8822C_SUPPORT)
-/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */
+/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */
-#define BIT_ANA_PORT_IDLE BIT(18)
-#define BIT_MAC_PORT_IDLE BIT(17)
-#define BIT_WL_PLATFORM_RST BIT(16)
-#define BIT_WL_SECURITY_CLK BIT(15)
+#define BIT_ARENB_L_V2 BIT(11)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */
+#define BIT_SHIFT_TBOX_L1_1_0 9
+#define BIT_MASK_TBOX_L1_1_0 0x3
+#define BIT_TBOX_L1_1_0(x) \
+ (((x) & BIT_MASK_TBOX_L1_1_0) << BIT_SHIFT_TBOX_L1_1_0)
+#define BITS_TBOX_L1_1_0 (BIT_MASK_TBOX_L1_1_0 << BIT_SHIFT_TBOX_L1_1_0)
+#define BIT_CLEAR_TBOX_L1_1_0(x) ((x) & (~BITS_TBOX_L1_1_0))
+#define BIT_GET_TBOX_L1_1_0(x) \
+ (((x) >> BIT_SHIFT_TBOX_L1_1_0) & BIT_MASK_TBOX_L1_1_0)
+#define BIT_SET_TBOX_L1_1_0(x, v) \
+ (BIT_CLEAR_TBOX_L1_1_0(x) | BIT_TBOX_L1_1_0(v))
-/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */
+#endif
+#if (HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_CPU_DMEM_CON 0
-#define BIT_MASK_CPU_DMEM_CON 0xff
-#define BIT_CPU_DMEM_CON(x) (((x) & BIT_MASK_CPU_DMEM_CON) << BIT_SHIFT_CPU_DMEM_CON)
-#define BIT_GET_CPU_DMEM_CON(x) (((x) >> BIT_SHIFT_CPU_DMEM_CON) & BIT_MASK_CPU_DMEM_CON)
+/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */
+#define BIT_SHIFT_TBOX_L1_V2 9
+#define BIT_MASK_TBOX_L1_V2 0x3
+#define BIT_TBOX_L1_V2(x) (((x) & BIT_MASK_TBOX_L1_V2) << BIT_SHIFT_TBOX_L1_V2)
+#define BITS_TBOX_L1_V2 (BIT_MASK_TBOX_L1_V2 << BIT_SHIFT_TBOX_L1_V2)
+#define BIT_CLEAR_TBOX_L1_V2(x) ((x) & (~BITS_TBOX_L1_V2))
+#define BIT_GET_TBOX_L1_V2(x) \
+ (((x) >> BIT_SHIFT_TBOX_L1_V2) & BIT_MASK_TBOX_L1_V2)
+#define BIT_SET_TBOX_L1_V2(x, v) (BIT_CLEAR_TBOX_L1_V2(x) | BIT_TBOX_L1_V2(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */
+#define BIT_SHIFT_REG_DELAY_L_1_0 7
+#define BIT_MASK_REG_DELAY_L_1_0 0x3
+#define BIT_REG_DELAY_L_1_0(x) \
+ (((x) & BIT_MASK_REG_DELAY_L_1_0) << BIT_SHIFT_REG_DELAY_L_1_0)
+#define BITS_REG_DELAY_L_1_0 \
+ (BIT_MASK_REG_DELAY_L_1_0 << BIT_SHIFT_REG_DELAY_L_1_0)
+#define BIT_CLEAR_REG_DELAY_L_1_0(x) ((x) & (~BITS_REG_DELAY_L_1_0))
+#define BIT_GET_REG_DELAY_L_1_0(x) \
+ (((x) >> BIT_SHIFT_REG_DELAY_L_1_0) & BIT_MASK_REG_DELAY_L_1_0)
+#define BIT_SET_REG_DELAY_L_1_0(x, v) \
+ (BIT_CLEAR_REG_DELAY_L_1_0(x) | BIT_REG_DELAY_L_1_0(v))
-/* 2 REG_BOOT_REASON (Offset 0x1088) */
+#endif
+#if (HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_BOOT_REASON 0
-#define BIT_MASK_BOOT_REASON 0x7
-#define BIT_BOOT_REASON(x) (((x) & BIT_MASK_BOOT_REASON) << BIT_SHIFT_BOOT_REASON)
-#define BIT_GET_BOOT_REASON(x) (((x) >> BIT_SHIFT_BOOT_REASON) & BIT_MASK_BOOT_REASON)
+/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */
+#define BIT_SHIFT_REG_DELAY_L 7
+#define BIT_MASK_REG_DELAY_L 0x3
+#define BIT_REG_DELAY_L(x) \
+ (((x) & BIT_MASK_REG_DELAY_L) << BIT_SHIFT_REG_DELAY_L)
+#define BITS_REG_DELAY_L (BIT_MASK_REG_DELAY_L << BIT_SHIFT_REG_DELAY_L)
+#define BIT_CLEAR_REG_DELAY_L(x) ((x) & (~BITS_REG_DELAY_L))
+#define BIT_GET_REG_DELAY_L(x) \
+ (((x) >> BIT_SHIFT_REG_DELAY_L) & BIT_MASK_REG_DELAY_L)
+#define BIT_SET_REG_DELAY_L(x, v) \
+ (BIT_CLEAR_REG_DELAY_L(x) | BIT_REG_DELAY_L(v))
-/* 2 REG_NFCPAD_CTRL (Offset 0x10A8) */
+#endif
-#define BIT_PAD_SHUTDW BIT(18)
-#define BIT_SYSON_NFC_PAD BIT(17)
-#define BIT_NFC_INT_PAD_CTRL BIT(16)
-#define BIT_NFC_RFDIS_PAD_CTRL BIT(15)
-#define BIT_NFC_CLK_PAD_CTRL BIT(14)
-#define BIT_NFC_DATA_PAD_CTRL BIT(13)
-#define BIT_NFC_PAD_PULL_CTRL BIT(12)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_NFCPAD_IO_SEL 8
-#define BIT_MASK_NFCPAD_IO_SEL 0xf
-#define BIT_NFCPAD_IO_SEL(x) (((x) & BIT_MASK_NFCPAD_IO_SEL) << BIT_SHIFT_NFCPAD_IO_SEL)
-#define BIT_GET_NFCPAD_IO_SEL(x) (((x) >> BIT_SHIFT_NFCPAD_IO_SEL) & BIT_MASK_NFCPAD_IO_SEL)
+/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */
+#define BIT_REG_CLAMP_D_L BIT(6)
-#define BIT_SHIFT_NFCPAD_OUT 4
-#define BIT_MASK_NFCPAD_OUT 0xf
-#define BIT_NFCPAD_OUT(x) (((x) & BIT_MASK_NFCPAD_OUT) << BIT_SHIFT_NFCPAD_OUT)
-#define BIT_GET_NFCPAD_OUT(x) (((x) >> BIT_SHIFT_NFCPAD_OUT) & BIT_MASK_NFCPAD_OUT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_NFCPAD_IN 0
-#define BIT_MASK_NFCPAD_IN 0xf
-#define BIT_NFCPAD_IN(x) (((x) & BIT_MASK_NFCPAD_IN) << BIT_SHIFT_NFCPAD_IN)
-#define BIT_GET_NFCPAD_IN(x) (((x) >> BIT_SHIFT_NFCPAD_IN) & BIT_MASK_NFCPAD_IN)
+/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */
+#define BIT_REG_BYPASS_L_V1 BIT(5)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */
+#define BIT_REG_BYPASS_L_V2 BIT(5)
-/* 2 REG_HIMR2 (Offset 0x10B0) */
+#endif
-#define BIT_BCNDMAINT_P4_MSK BIT(31)
-#define BIT_BCNDMAINT_P3_MSK BIT(30)
-#define BIT_BCNDMAINT_P2_MSK BIT(29)
-#define BIT_BCNDMAINT_P1_MSK BIT(28)
-#define BIT_ATIMEND7_MSK BIT(22)
-#define BIT_ATIMEND6_MSK BIT(21)
-#define BIT_ATIMEND5_MSK BIT(20)
-#define BIT_ATIMEND4_MSK BIT(19)
-#define BIT_ATIMEND3_MSK BIT(18)
-#define BIT_ATIMEND2_MSK BIT(17)
-#define BIT_ATIMEND1_MSK BIT(16)
-#define BIT_TXBCN7OK_MSK BIT(14)
-#define BIT_TXBCN6OK_MSK BIT(13)
-#define BIT_TXBCN5OK_MSK BIT(12)
-#define BIT_TXBCN4OK_MSK BIT(11)
-#define BIT_TXBCN3OK_MSK BIT(10)
-#define BIT_TXBCN2OK_MSK BIT(9)
-#define BIT_TXBCN1OK_MSK_V1 BIT(8)
-#define BIT_TXBCN7ERR_MSK BIT(6)
-#define BIT_TXBCN6ERR_MSK BIT(5)
-#define BIT_TXBCN5ERR_MSK BIT(4)
-#define BIT_TXBCN4ERR_MSK BIT(3)
-#define BIT_TXBCN3ERR_MSK BIT(2)
-#define BIT_TXBCN2ERR_MSK BIT(1)
-#define BIT_TXBCN1ERR_MSK_V1 BIT(0)
-
-/* 2 REG_HISR2 (Offset 0x10B4) */
-
-#define BIT_BCNDMAINT_P4 BIT(31)
-#define BIT_BCNDMAINT_P3 BIT(30)
-#define BIT_BCNDMAINT_P2 BIT(29)
-#define BIT_BCNDMAINT_P1 BIT(28)
-#define BIT_ATIMEND7 BIT(22)
-#define BIT_ATIMEND6 BIT(21)
-#define BIT_ATIMEND5 BIT(20)
-#define BIT_ATIMEND4 BIT(19)
-#define BIT_ATIMEND3 BIT(18)
-#define BIT_ATIMEND2 BIT(17)
-#define BIT_ATIMEND1 BIT(16)
-#define BIT_TXBCN7OK BIT(14)
-#define BIT_TXBCN6OK BIT(13)
-#define BIT_TXBCN5OK BIT(12)
-#define BIT_TXBCN4OK BIT(11)
-#define BIT_TXBCN3OK BIT(10)
-#define BIT_TXBCN2OK BIT(9)
-#define BIT_TXBCN1OK BIT(8)
-#define BIT_TXBCN7ERR BIT(6)
-#define BIT_TXBCN6ERR BIT(5)
-#define BIT_TXBCN5ERR BIT(4)
-#define BIT_TXBCN4ERR BIT(3)
-#define BIT_TXBCN3ERR BIT(2)
-#define BIT_TXBCN2ERR BIT(1)
-#define BIT_TXBCN1ERR BIT(0)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */
+#define BIT_REG_AUTOZCD_L BIT(4)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_HIMR3 (Offset 0x10B8) */
+/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */
-#define BIT_WDT_PLATFORM_INT_MSK BIT(18)
-#define BIT_WDT_CPU_INT_MSK BIT(17)
+#define BIT_POW_ZCD_L_V1 BIT(3)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */
+#define BIT_POW_ZCD_L_V2 BIT(3)
+#define BIT_REG_HALF_L BIT(2)
-/* 2 REG_HIMR3 (Offset 0x10B8) */
+#endif
-#define BIT_SETH2CDOK_MASK BIT(16)
-#define BIT_H2C_CMD_FULL_MASK BIT(15)
-#define BIT_PWR_INT_127_MASK BIT(14)
-#define BIT_TXSHORTCUT_TXDESUPDATEOK_MASK BIT(13)
-#define BIT_TXSHORTCUT_BKUPDATEOK_MASK BIT(12)
-#define BIT_TXSHORTCUT_BEUPDATEOK_MASK BIT(11)
-#define BIT_TXSHORTCUT_VIUPDATEOK_MAS BIT(10)
-#define BIT_TXSHORTCUT_VOUPDATEOK_MASK BIT(9)
-#define BIT_PWR_INT_127_MASK_V1 BIT(8)
-#define BIT_PWR_INT_126TO96_MASK BIT(7)
-#define BIT_PWR_INT_95TO64_MASK BIT(6)
-#define BIT_PWR_INT_63TO32_MASK BIT(5)
-#define BIT_PWR_INT_31TO0_MASK BIT(4)
-#define BIT_DDMA0_LP_INT_MSK BIT(1)
-#define BIT_DDMA0_HP_INT_MSK BIT(0)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */
+#define BIT_SHIFT_OCP_L_2_1 0
+#define BIT_MASK_OCP_L_2_1 0x3
+#define BIT_OCP_L_2_1(x) (((x) & BIT_MASK_OCP_L_2_1) << BIT_SHIFT_OCP_L_2_1)
+#define BITS_OCP_L_2_1 (BIT_MASK_OCP_L_2_1 << BIT_SHIFT_OCP_L_2_1)
+#define BIT_CLEAR_OCP_L_2_1(x) ((x) & (~BITS_OCP_L_2_1))
+#define BIT_GET_OCP_L_2_1(x) (((x) >> BIT_SHIFT_OCP_L_2_1) & BIT_MASK_OCP_L_2_1)
+#define BIT_SET_OCP_L_2_1(x, v) (BIT_CLEAR_OCP_L_2_1(x) | BIT_OCP_L_2_1(v))
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8822C_SUPPORT)
-/* 2 REG_HISR3 (Offset 0x10BC) */
+/* 2 REG_ANAPARSW_MAC_1 (Offset 0x1014) */
-#define BIT_WDT_PLATFORM_INT BIT(18)
-#define BIT_WDT_CPU_INT BIT(17)
+#define BIT_SHIFT_OCP_L_V2 0
+#define BIT_MASK_OCP_L_V2 0x3
+#define BIT_OCP_L_V2(x) (((x) & BIT_MASK_OCP_L_V2) << BIT_SHIFT_OCP_L_V2)
+#define BITS_OCP_L_V2 (BIT_MASK_OCP_L_V2 << BIT_SHIFT_OCP_L_V2)
+#define BIT_CLEAR_OCP_L_V2(x) ((x) & (~BITS_OCP_L_V2))
+#define BIT_GET_OCP_L_V2(x) (((x) >> BIT_SHIFT_OCP_L_V2) & BIT_MASK_OCP_L_V2)
+#define BIT_SET_OCP_L_V2(x, v) (BIT_CLEAR_OCP_L_V2(x) | BIT_OCP_L_V2(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */
+#define BIT_SHIFT_LPF_C2_1_0 30
+#define BIT_MASK_LPF_C2_1_0 0x3
+#define BIT_LPF_C2_1_0(x) (((x) & BIT_MASK_LPF_C2_1_0) << BIT_SHIFT_LPF_C2_1_0)
+#define BITS_LPF_C2_1_0 (BIT_MASK_LPF_C2_1_0 << BIT_SHIFT_LPF_C2_1_0)
+#define BIT_CLEAR_LPF_C2_1_0(x) ((x) & (~BITS_LPF_C2_1_0))
+#define BIT_GET_LPF_C2_1_0(x) \
+ (((x) >> BIT_SHIFT_LPF_C2_1_0) & BIT_MASK_LPF_C2_1_0)
+#define BIT_SET_LPF_C2_1_0(x, v) (BIT_CLEAR_LPF_C2_1_0(x) | BIT_LPF_C2_1_0(v))
-/* 2 REG_HISR3 (Offset 0x10BC) */
+#endif
-#define BIT_SETH2CDOK BIT(16)
-#define BIT_H2C_CMD_FULL BIT(15)
-#define BIT_PWR_INT_127 BIT(14)
-#define BIT_TXSHORTCUT_TXDESUPDATEOK BIT(13)
-#define BIT_TXSHORTCUT_BKUPDATEOK BIT(12)
-#define BIT_TXSHORTCUT_BEUPDATEOK BIT(11)
-#define BIT_TXSHORTCUT_VIUPDATEOK BIT(10)
-#define BIT_TXSHORTCUT_VOUPDATEOK BIT(9)
-#define BIT_PWR_INT_127_V1 BIT(8)
-#define BIT_PWR_INT_126TO96 BIT(7)
-#define BIT_PWR_INT_95TO64 BIT(6)
-#define BIT_PWR_INT_63TO32 BIT(5)
-#define BIT_PWR_INT_31TO0 BIT(4)
-#define BIT_DDMA0_LP_INT BIT(1)
-#define BIT_DDMA0_HP_INT BIT(0)
+#if (HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */
+#define BIT_SHIFT_REG_LPF_R3 29
+#define BIT_MASK_REG_LPF_R3 0x7
+#define BIT_REG_LPF_R3(x) (((x) & BIT_MASK_REG_LPF_R3) << BIT_SHIFT_REG_LPF_R3)
+#define BITS_REG_LPF_R3 (BIT_MASK_REG_LPF_R3 << BIT_SHIFT_REG_LPF_R3)
+#define BIT_CLEAR_REG_LPF_R3(x) ((x) & (~BITS_REG_LPF_R3))
+#define BIT_GET_REG_LPF_R3(x) \
+ (((x) >> BIT_SHIFT_REG_LPF_R3) & BIT_MASK_REG_LPF_R3)
+#define BIT_SET_REG_LPF_R3(x, v) (BIT_CLEAR_REG_LPF_R3(x) | BIT_REG_LPF_R3(v))
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_SW_MDIO (Offset 0x10C0) */
+/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */
-#define BIT_DIS_TIMEOUT_IO BIT(24)
+#define BIT_EN_XTAL_AAC_TRIG BIT(28)
+#define BIT_EN_XTAL_AAC BIT(27)
+#define BIT_EN_XTAL_AAC_DIGI BIT(26)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */
+#define BIT_SHIFT_LPF_C1_5_0 24
+#define BIT_MASK_LPF_C1_5_0 0x3f
+#define BIT_LPF_C1_5_0(x) (((x) & BIT_MASK_LPF_C1_5_0) << BIT_SHIFT_LPF_C1_5_0)
+#define BITS_LPF_C1_5_0 (BIT_MASK_LPF_C1_5_0 << BIT_SHIFT_LPF_C1_5_0)
+#define BIT_CLEAR_LPF_C1_5_0(x) ((x) & (~BITS_LPF_C1_5_0))
+#define BIT_GET_LPF_C1_5_0(x) \
+ (((x) >> BIT_SHIFT_LPF_C1_5_0) & BIT_MASK_LPF_C1_5_0)
+#define BIT_SET_LPF_C1_5_0(x, v) (BIT_CLEAR_LPF_C1_5_0(x) | BIT_LPF_C1_5_0(v))
-/* 2 REG_SW_MDIO (Offset 0x10C0) */
+#endif
-#define BIT_SUS_PL BIT(18)
-#define BIT_SOP_ESUS BIT(17)
-#define BIT_SOP_DLDO BIT(16)
-#define BIT_R_OCP_ST_CLR BIT(8)
-#define BIT_SW_USB3_MD_SEL BIT(5)
-#define BIT_SW_PCIE_MD_SEL BIT(4)
-#define BIT_SW_MDCK BIT(2)
-#define BIT_SW_MDI BIT(1)
-#define BIT_MDO BIT(0)
+#if (HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */
+#define BIT_SHIFT_REG_LPF_R2 24
+#define BIT_MASK_REG_LPF_R2 0x1f
+#define BIT_REG_LPF_R2(x) (((x) & BIT_MASK_REG_LPF_R2) << BIT_SHIFT_REG_LPF_R2)
+#define BITS_REG_LPF_R2 (BIT_MASK_REG_LPF_R2 << BIT_SHIFT_REG_LPF_R2)
+#define BIT_CLEAR_REG_LPF_R2(x) ((x) & (~BITS_REG_LPF_R2))
+#define BIT_GET_REG_LPF_R2(x) \
+ (((x) >> BIT_SHIFT_REG_LPF_R2) & BIT_MASK_REG_LPF_R2)
+#define BIT_SET_REG_LPF_R2(x, v) (BIT_CLEAR_REG_LPF_R2(x) | BIT_REG_LPF_R2(v))
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_SW_FLUSH (Offset 0x10C4) */
+/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */
-#define BIT_FLUSH_HOLDN_EN BIT(25)
-#define BIT_FLUSH_WR_EN BIT(24)
-#define BIT_SW_FLASH_CONTROL BIT(23)
-#define BIT_SW_FLASH_WEN_E BIT(19)
-#define BIT_SW_FLASH_HOLDN_E BIT(18)
-#define BIT_SW_FLASH_SO_E BIT(17)
-#define BIT_SW_FLASH_SI_E BIT(16)
-#define BIT_SW_FLASH_SK_O BIT(13)
-#define BIT_SW_FLASH_CEN_O BIT(12)
-#define BIT_SW_FLASH_WEN_O BIT(11)
-#define BIT_SW_FLASH_HOLDN_O BIT(10)
-#define BIT_SW_FLASH_SO_O BIT(9)
-#define BIT_SW_FLASH_SI_O BIT(8)
-#define BIT_SW_FLASH_WEN_I BIT(3)
-#define BIT_SW_FLASH_HOLDN_I BIT(2)
-#define BIT_SW_FLASH_SO_I BIT(1)
-#define BIT_SW_FLASH_SI_I BIT(0)
+#define BIT_LPF_TIEL BIT(23)
+#define BIT_LPF_TIEH BIT(22)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */
+#define BIT_SHIFT_REG_LPF_C3 21
+#define BIT_MASK_REG_LPF_C3 0x7
+#define BIT_REG_LPF_C3(x) (((x) & BIT_MASK_REG_LPF_C3) << BIT_SHIFT_REG_LPF_C3)
+#define BITS_REG_LPF_C3 (BIT_MASK_REG_LPF_C3 << BIT_SHIFT_REG_LPF_C3)
+#define BIT_CLEAR_REG_LPF_C3(x) ((x) & (~BITS_REG_LPF_C3))
+#define BIT_GET_REG_LPF_C3(x) \
+ (((x) >> BIT_SHIFT_REG_LPF_C3) & BIT_MASK_REG_LPF_C3)
+#define BIT_SET_REG_LPF_C3(x, v) (BIT_CLEAR_REG_LPF_C3(x) | BIT_REG_LPF_C3(v))
-/* 2 REG_DBG_GPIO_BMUX (Offset 0x10C8) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_DBG_GPIO_BMUX_7 21
-#define BIT_MASK_DBG_GPIO_BMUX_7 0x7
-#define BIT_DBG_GPIO_BMUX_7(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_7) << BIT_SHIFT_DBG_GPIO_BMUX_7)
-#define BIT_GET_DBG_GPIO_BMUX_7(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_7) & BIT_MASK_DBG_GPIO_BMUX_7)
+/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */
+#define BIT_SHIFT_LOCKDET_VREF_L_1_0 20
+#define BIT_MASK_LOCKDET_VREF_L_1_0 0x3
+#define BIT_LOCKDET_VREF_L_1_0(x) \
+ (((x) & BIT_MASK_LOCKDET_VREF_L_1_0) << BIT_SHIFT_LOCKDET_VREF_L_1_0)
+#define BITS_LOCKDET_VREF_L_1_0 \
+ (BIT_MASK_LOCKDET_VREF_L_1_0 << BIT_SHIFT_LOCKDET_VREF_L_1_0)
+#define BIT_CLEAR_LOCKDET_VREF_L_1_0(x) ((x) & (~BITS_LOCKDET_VREF_L_1_0))
+#define BIT_GET_LOCKDET_VREF_L_1_0(x) \
+ (((x) >> BIT_SHIFT_LOCKDET_VREF_L_1_0) & BIT_MASK_LOCKDET_VREF_L_1_0)
+#define BIT_SET_LOCKDET_VREF_L_1_0(x, v) \
+ (BIT_CLEAR_LOCKDET_VREF_L_1_0(x) | BIT_LOCKDET_VREF_L_1_0(v))
-#define BIT_SHIFT_DBG_GPIO_BMUX_6 18
-#define BIT_MASK_DBG_GPIO_BMUX_6 0x7
-#define BIT_DBG_GPIO_BMUX_6(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_6) << BIT_SHIFT_DBG_GPIO_BMUX_6)
-#define BIT_GET_DBG_GPIO_BMUX_6(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_6) & BIT_MASK_DBG_GPIO_BMUX_6)
+#define BIT_SHIFT_LOCKDET_VREF_H_1_0 18
+#define BIT_MASK_LOCKDET_VREF_H_1_0 0x3
+#define BIT_LOCKDET_VREF_H_1_0(x) \
+ (((x) & BIT_MASK_LOCKDET_VREF_H_1_0) << BIT_SHIFT_LOCKDET_VREF_H_1_0)
+#define BITS_LOCKDET_VREF_H_1_0 \
+ (BIT_MASK_LOCKDET_VREF_H_1_0 << BIT_SHIFT_LOCKDET_VREF_H_1_0)
+#define BIT_CLEAR_LOCKDET_VREF_H_1_0(x) ((x) & (~BITS_LOCKDET_VREF_H_1_0))
+#define BIT_GET_LOCKDET_VREF_H_1_0(x) \
+ (((x) >> BIT_SHIFT_LOCKDET_VREF_H_1_0) & BIT_MASK_LOCKDET_VREF_H_1_0)
+#define BIT_SET_LOCKDET_VREF_H_1_0(x, v) \
+ (BIT_CLEAR_LOCKDET_VREF_H_1_0(x) | BIT_LOCKDET_VREF_H_1_0(v))
+#endif
-#define BIT_SHIFT_DBG_GPIO_BMUX_5 15
-#define BIT_MASK_DBG_GPIO_BMUX_5 0x7
-#define BIT_DBG_GPIO_BMUX_5(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_5) << BIT_SHIFT_DBG_GPIO_BMUX_5)
-#define BIT_GET_DBG_GPIO_BMUX_5(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_5) & BIT_MASK_DBG_GPIO_BMUX_5)
+#if (HALMAC_8822C_SUPPORT)
+/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */
-#define BIT_SHIFT_DBG_GPIO_BMUX_4 12
-#define BIT_MASK_DBG_GPIO_BMUX_4 0x7
-#define BIT_DBG_GPIO_BMUX_4(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_4) << BIT_SHIFT_DBG_GPIO_BMUX_4)
-#define BIT_GET_DBG_GPIO_BMUX_4(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_4) & BIT_MASK_DBG_GPIO_BMUX_4)
+#define BIT_SHIFT_REG_LPF_C2 18
+#define BIT_MASK_REG_LPF_C2 0x7
+#define BIT_REG_LPF_C2(x) (((x) & BIT_MASK_REG_LPF_C2) << BIT_SHIFT_REG_LPF_C2)
+#define BITS_REG_LPF_C2 (BIT_MASK_REG_LPF_C2 << BIT_SHIFT_REG_LPF_C2)
+#define BIT_CLEAR_REG_LPF_C2(x) ((x) & (~BITS_REG_LPF_C2))
+#define BIT_GET_REG_LPF_C2(x) \
+ (((x) >> BIT_SHIFT_REG_LPF_C2) & BIT_MASK_REG_LPF_C2)
+#define BIT_SET_REG_LPF_C2(x, v) (BIT_CLEAR_REG_LPF_C2(x) | BIT_REG_LPF_C2(v))
+#endif
-#define BIT_SHIFT_DBG_GPIO_BMUX_3 9
-#define BIT_MASK_DBG_GPIO_BMUX_3 0x7
-#define BIT_DBG_GPIO_BMUX_3(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_3) << BIT_SHIFT_DBG_GPIO_BMUX_3)
-#define BIT_GET_DBG_GPIO_BMUX_3(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_3) & BIT_MASK_DBG_GPIO_BMUX_3)
+#if (HALMAC_8814B_SUPPORT)
+/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */
-#define BIT_SHIFT_DBG_GPIO_BMUX_2 6
-#define BIT_MASK_DBG_GPIO_BMUX_2 0x7
-#define BIT_DBG_GPIO_BMUX_2(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_2) << BIT_SHIFT_DBG_GPIO_BMUX_2)
-#define BIT_GET_DBG_GPIO_BMUX_2(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_2) & BIT_MASK_DBG_GPIO_BMUX_2)
+#define BIT_SHIFT_LDO_SEL_1_0 16
+#define BIT_MASK_LDO_SEL_1_0 0x3
+#define BIT_LDO_SEL_1_0(x) \
+ (((x) & BIT_MASK_LDO_SEL_1_0) << BIT_SHIFT_LDO_SEL_1_0)
+#define BITS_LDO_SEL_1_0 (BIT_MASK_LDO_SEL_1_0 << BIT_SHIFT_LDO_SEL_1_0)
+#define BIT_CLEAR_LDO_SEL_1_0(x) ((x) & (~BITS_LDO_SEL_1_0))
+#define BIT_GET_LDO_SEL_1_0(x) \
+ (((x) >> BIT_SHIFT_LDO_SEL_1_0) & BIT_MASK_LDO_SEL_1_0)
+#define BIT_SET_LDO_SEL_1_0(x, v) \
+ (BIT_CLEAR_LDO_SEL_1_0(x) | BIT_LDO_SEL_1_0(v))
+#endif
-#define BIT_SHIFT_DBG_GPIO_BMUX_1 3
-#define BIT_MASK_DBG_GPIO_BMUX_1 0x7
-#define BIT_DBG_GPIO_BMUX_1(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_1) << BIT_SHIFT_DBG_GPIO_BMUX_1)
-#define BIT_GET_DBG_GPIO_BMUX_1(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_1) & BIT_MASK_DBG_GPIO_BMUX_1)
+#if (HALMAC_8822C_SUPPORT)
+/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */
-#define BIT_SHIFT_DBG_GPIO_BMUX_0 0
-#define BIT_MASK_DBG_GPIO_BMUX_0 0x7
-#define BIT_DBG_GPIO_BMUX_0(x) (((x) & BIT_MASK_DBG_GPIO_BMUX_0) << BIT_SHIFT_DBG_GPIO_BMUX_0)
-#define BIT_GET_DBG_GPIO_BMUX_0(x) (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_0) & BIT_MASK_DBG_GPIO_BMUX_0)
+#define BIT_SHIFT_REG_LPF_C1 15
+#define BIT_MASK_REG_LPF_C1 0x7
+#define BIT_REG_LPF_C1(x) (((x) & BIT_MASK_REG_LPF_C1) << BIT_SHIFT_REG_LPF_C1)
+#define BITS_REG_LPF_C1 (BIT_MASK_REG_LPF_C1 << BIT_SHIFT_REG_LPF_C1)
+#define BIT_CLEAR_REG_LPF_C1(x) ((x) & (~BITS_REG_LPF_C1))
+#define BIT_GET_REG_LPF_C1(x) \
+ (((x) >> BIT_SHIFT_REG_LPF_C1) & BIT_MASK_REG_LPF_C1)
+#define BIT_SET_REG_LPF_C1(x, v) (BIT_CLEAR_REG_LPF_C1(x) | BIT_REG_LPF_C1(v))
+#define BIT_SHIFT_REG_LDO_SEL_V1 13
+#define BIT_MASK_REG_LDO_SEL_V1 0x3
+#define BIT_REG_LDO_SEL_V1(x) \
+ (((x) & BIT_MASK_REG_LDO_SEL_V1) << BIT_SHIFT_REG_LDO_SEL_V1)
+#define BITS_REG_LDO_SEL_V1 \
+ (BIT_MASK_REG_LDO_SEL_V1 << BIT_SHIFT_REG_LDO_SEL_V1)
+#define BIT_CLEAR_REG_LDO_SEL_V1(x) ((x) & (~BITS_REG_LDO_SEL_V1))
+#define BIT_GET_REG_LDO_SEL_V1(x) \
+ (((x) >> BIT_SHIFT_REG_LDO_SEL_V1) & BIT_MASK_REG_LDO_SEL_V1)
+#define BIT_SET_REG_LDO_SEL_V1(x, v) \
+ (BIT_CLEAR_REG_LDO_SEL_V1(x) | BIT_REG_LDO_SEL_V1(v))
-/* 2 REG_FPGA_TAG (Offset 0x10CC) */
+#define BIT_REG_CP_ICPX2 BIT(12)
-#define BIT_WL_DSS_RSTN BIT(27)
-#define BIT_WL_DSS_EN_CLK BIT(26)
-#define BIT_WL_DSS_SPEED_EN BIT(25)
+#endif
-#define BIT_SHIFT_FPGA_TAG 0
-#define BIT_MASK_FPGA_TAG 0xffffffffL
-#define BIT_FPGA_TAG(x) (((x) & BIT_MASK_FPGA_TAG) << BIT_SHIFT_FPGA_TAG)
-#define BIT_GET_FPGA_TAG(x) (((x) >> BIT_SHIFT_FPGA_TAG) & BIT_MASK_FPGA_TAG)
+#if (HALMAC_8814B_SUPPORT)
+/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */
-#define BIT_SHIFT_WL_DSS_COUNT_OUT 0
-#define BIT_MASK_WL_DSS_COUNT_OUT 0xfffff
-#define BIT_WL_DSS_COUNT_OUT(x) (((x) & BIT_MASK_WL_DSS_COUNT_OUT) << BIT_SHIFT_WL_DSS_COUNT_OUT)
-#define BIT_GET_WL_DSS_COUNT_OUT(x) (((x) >> BIT_SHIFT_WL_DSS_COUNT_OUT) & BIT_MASK_WL_DSS_COUNT_OUT)
+#define BIT_SHIFT_IOFFSET_5_0 10
+#define BIT_MASK_IOFFSET_5_0 0x3f
+#define BIT_IOFFSET_5_0(x) \
+ (((x) & BIT_MASK_IOFFSET_5_0) << BIT_SHIFT_IOFFSET_5_0)
+#define BITS_IOFFSET_5_0 (BIT_MASK_IOFFSET_5_0 << BIT_SHIFT_IOFFSET_5_0)
+#define BIT_CLEAR_IOFFSET_5_0(x) ((x) & (~BITS_IOFFSET_5_0))
+#define BIT_GET_IOFFSET_5_0(x) \
+ (((x) >> BIT_SHIFT_IOFFSET_5_0) & BIT_MASK_IOFFSET_5_0)
+#define BIT_SET_IOFFSET_5_0(x, v) \
+ (BIT_CLEAR_IOFFSET_5_0(x) | BIT_IOFFSET_5_0(v))
+#define BIT_CP_ICPX2 BIT(9)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */
+#define BIT_SHIFT_REG_CP_ICP_SEL_FAST 9
+#define BIT_MASK_REG_CP_ICP_SEL_FAST 0x7
+#define BIT_REG_CP_ICP_SEL_FAST(x) \
+ (((x) & BIT_MASK_REG_CP_ICP_SEL_FAST) << BIT_SHIFT_REG_CP_ICP_SEL_FAST)
+#define BITS_REG_CP_ICP_SEL_FAST \
+ (BIT_MASK_REG_CP_ICP_SEL_FAST << BIT_SHIFT_REG_CP_ICP_SEL_FAST)
+#define BIT_CLEAR_REG_CP_ICP_SEL_FAST(x) ((x) & (~BITS_REG_CP_ICP_SEL_FAST))
+#define BIT_GET_REG_CP_ICP_SEL_FAST(x) \
+ (((x) >> BIT_SHIFT_REG_CP_ICP_SEL_FAST) & BIT_MASK_REG_CP_ICP_SEL_FAST)
+#define BIT_SET_REG_CP_ICP_SEL_FAST(x, v) \
+ (BIT_CLEAR_REG_CP_ICP_SEL_FAST(x) | BIT_REG_CP_ICP_SEL_FAST(v))
-/* 2 REG_H2C_PKT_READADDR (Offset 0x10D0) */
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_H2C_PKT_READADDR 0
-#define BIT_MASK_H2C_PKT_READADDR 0x3ffff
-#define BIT_H2C_PKT_READADDR(x) (((x) & BIT_MASK_H2C_PKT_READADDR) << BIT_SHIFT_H2C_PKT_READADDR)
-#define BIT_GET_H2C_PKT_READADDR(x) (((x) >> BIT_SHIFT_H2C_PKT_READADDR) & BIT_MASK_H2C_PKT_READADDR)
+/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */
+#define BIT_GM_STEP BIT(7)
-/* 2 REG_H2C_PKT_WRITEADDR (Offset 0x10D4) */
+#endif
+#if (HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_H2C_PKT_WRITEADDR 0
-#define BIT_MASK_H2C_PKT_WRITEADDR 0x3ffff
-#define BIT_H2C_PKT_WRITEADDR(x) (((x) & BIT_MASK_H2C_PKT_WRITEADDR) << BIT_SHIFT_H2C_PKT_WRITEADDR)
-#define BIT_GET_H2C_PKT_WRITEADDR(x) (((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR) & BIT_MASK_H2C_PKT_WRITEADDR)
+/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */
+#define BIT_SHIFT_REG_CP_ICP_SEL 6
+#define BIT_MASK_REG_CP_ICP_SEL 0x7
+#define BIT_REG_CP_ICP_SEL(x) \
+ (((x) & BIT_MASK_REG_CP_ICP_SEL) << BIT_SHIFT_REG_CP_ICP_SEL)
+#define BITS_REG_CP_ICP_SEL \
+ (BIT_MASK_REG_CP_ICP_SEL << BIT_SHIFT_REG_CP_ICP_SEL)
+#define BIT_CLEAR_REG_CP_ICP_SEL(x) ((x) & (~BITS_REG_CP_ICP_SEL))
+#define BIT_GET_REG_CP_ICP_SEL(x) \
+ (((x) >> BIT_SHIFT_REG_CP_ICP_SEL) & BIT_MASK_REG_CP_ICP_SEL)
+#define BIT_SET_REG_CP_ICP_SEL(x, v) \
+ (BIT_CLEAR_REG_CP_ICP_SEL(x) | BIT_REG_CP_ICP_SEL(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
+/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */
-/* 2 REG_WL_DSS_CTRL1 (Offset 0x10D8) */
+#define BIT_SHIFT_CP_ICP_SEL_4_0 4
+#define BIT_MASK_CP_ICP_SEL_4_0 0x1f
+#define BIT_CP_ICP_SEL_4_0(x) \
+ (((x) & BIT_MASK_CP_ICP_SEL_4_0) << BIT_SHIFT_CP_ICP_SEL_4_0)
+#define BITS_CP_ICP_SEL_4_0 \
+ (BIT_MASK_CP_ICP_SEL_4_0 << BIT_SHIFT_CP_ICP_SEL_4_0)
+#define BIT_CLEAR_CP_ICP_SEL_4_0(x) ((x) & (~BITS_CP_ICP_SEL_4_0))
+#define BIT_GET_CP_ICP_SEL_4_0(x) \
+ (((x) >> BIT_SHIFT_CP_ICP_SEL_4_0) & BIT_MASK_CP_ICP_SEL_4_0)
+#define BIT_SET_CP_ICP_SEL_4_0(x, v) \
+ (BIT_CLEAR_CP_ICP_SEL_4_0(x) | BIT_CP_ICP_SEL_4_0(v))
-#define BIT_WL_DSS_WIRE_SEL BIT(24)
+#endif
-#define BIT_SHIFT_WL_DSS_RO_SEL 20
-#define BIT_MASK_WL_DSS_RO_SEL 0x7
-#define BIT_WL_DSS_RO_SEL(x) (((x) & BIT_MASK_WL_DSS_RO_SEL) << BIT_SHIFT_WL_DSS_RO_SEL)
-#define BIT_GET_WL_DSS_RO_SEL(x) (((x) >> BIT_SHIFT_WL_DSS_RO_SEL) & BIT_MASK_WL_DSS_RO_SEL)
+#if (HALMAC_8822C_SUPPORT)
+/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */
-#endif
+#define BIT_SHIFT_REG_IB_PI 4
+#define BIT_MASK_REG_IB_PI 0x3
+#define BIT_REG_IB_PI(x) (((x) & BIT_MASK_REG_IB_PI) << BIT_SHIFT_REG_IB_PI)
+#define BITS_REG_IB_PI (BIT_MASK_REG_IB_PI << BIT_SHIFT_REG_IB_PI)
+#define BIT_CLEAR_REG_IB_PI(x) ((x) & (~BITS_REG_IB_PI))
+#define BIT_GET_REG_IB_PI(x) (((x) >> BIT_SHIFT_REG_IB_PI) & BIT_MASK_REG_IB_PI)
+#define BIT_SET_REG_IB_PI(x, v) (BIT_CLEAR_REG_IB_PI(x) | BIT_REG_IB_PI(v))
+#define BIT_LDO2PWRCUT BIT(3)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_MEM_PWR_CRTL (Offset 0x10D8) */
+/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */
-#define BIT_MEM_BB_SD BIT(17)
-#define BIT_MEM_BB_DS BIT(16)
-#define BIT_MEM_BT_DS BIT(10)
-#define BIT_MEM_SDIO_LS BIT(9)
-#define BIT_MEM_SDIO_DS BIT(8)
-#define BIT_MEM_USB_LS BIT(7)
-#define BIT_MEM_USB_DS BIT(6)
-#define BIT_MEM_PCI_LS BIT(5)
-#define BIT_MEM_PCI_DS BIT(4)
-#define BIT_MEM_WLMAC_LS BIT(3)
-#define BIT_MEM_WLMAC_DS BIT(2)
-#define BIT_MEM_WLMCU_LS BIT(1)
+#define BIT_SHIFT_IB_PI_1_0 2
+#define BIT_MASK_IB_PI_1_0 0x3
+#define BIT_IB_PI_1_0(x) (((x) & BIT_MASK_IB_PI_1_0) << BIT_SHIFT_IB_PI_1_0)
+#define BITS_IB_PI_1_0 (BIT_MASK_IB_PI_1_0 << BIT_SHIFT_IB_PI_1_0)
+#define BIT_CLEAR_IB_PI_1_0(x) ((x) & (~BITS_IB_PI_1_0))
+#define BIT_GET_IB_PI_1_0(x) (((x) >> BIT_SHIFT_IB_PI_1_0) & BIT_MASK_IB_PI_1_0)
+#define BIT_SET_IB_PI_1_0(x, v) (BIT_CLEAR_IB_PI_1_0(x) | BIT_IB_PI_1_0(v))
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */
+#define BIT_VPULSE_LDO BIT(2)
-/* 2 REG_WL_DSS_CTRL1 (Offset 0x10D8) */
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_WL_DSS_DATA_IN 0
-#define BIT_MASK_WL_DSS_DATA_IN 0xfffff
-#define BIT_WL_DSS_DATA_IN(x) (((x) & BIT_MASK_WL_DSS_DATA_IN) << BIT_SHIFT_WL_DSS_DATA_IN)
-#define BIT_GET_WL_DSS_DATA_IN(x) (((x) >> BIT_SHIFT_WL_DSS_DATA_IN) & BIT_MASK_WL_DSS_DATA_IN)
+/* 2 REG_ANAPAR_MAC_0 (Offset 0x1018) */
+#define BIT_OFFSET_PLUS BIT(1)
-#endif
+#define BIT_SHIFT_LDO_VSEL 0
+#define BIT_MASK_LDO_VSEL 0x3
+#define BIT_LDO_VSEL(x) (((x) & BIT_MASK_LDO_VSEL) << BIT_SHIFT_LDO_VSEL)
+#define BITS_LDO_VSEL (BIT_MASK_LDO_VSEL << BIT_SHIFT_LDO_VSEL)
+#define BIT_CLEAR_LDO_VSEL(x) ((x) & (~BITS_LDO_VSEL))
+#define BIT_GET_LDO_VSEL(x) (((x) >> BIT_SHIFT_LDO_VSEL) & BIT_MASK_LDO_VSEL)
+#define BIT_SET_LDO_VSEL(x, v) (BIT_CLEAR_LDO_VSEL(x) | BIT_LDO_VSEL(v))
+#define BIT_RESET_N BIT(0)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_MEM_PWR_CRTL (Offset 0x10D8) */
+/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */
-#define BIT_MEM_WLMCU_DS BIT(0)
+#define BIT_SHIFT_CKX_USB_IB_SEL 29
+#define BIT_MASK_CKX_USB_IB_SEL 0x7
+#define BIT_CKX_USB_IB_SEL(x) \
+ (((x) & BIT_MASK_CKX_USB_IB_SEL) << BIT_SHIFT_CKX_USB_IB_SEL)
+#define BITS_CKX_USB_IB_SEL \
+ (BIT_MASK_CKX_USB_IB_SEL << BIT_SHIFT_CKX_USB_IB_SEL)
+#define BIT_CLEAR_CKX_USB_IB_SEL(x) ((x) & (~BITS_CKX_USB_IB_SEL))
+#define BIT_GET_CKX_USB_IB_SEL(x) \
+ (((x) >> BIT_SHIFT_CKX_USB_IB_SEL) & BIT_MASK_CKX_USB_IB_SEL)
+#define BIT_SET_CKX_USB_IB_SEL(x, v) \
+ (BIT_CLEAR_CKX_USB_IB_SEL(x) | BIT_CKX_USB_IB_SEL(v))
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */
+#define BIT_SHIFT_REG_CK_MON_SEL 29
+#define BIT_MASK_REG_CK_MON_SEL 0x7
+#define BIT_REG_CK_MON_SEL(x) \
+ (((x) & BIT_MASK_REG_CK_MON_SEL) << BIT_SHIFT_REG_CK_MON_SEL)
+#define BITS_REG_CK_MON_SEL \
+ (BIT_MASK_REG_CK_MON_SEL << BIT_SHIFT_REG_CK_MON_SEL)
+#define BIT_CLEAR_REG_CK_MON_SEL(x) ((x) & (~BITS_REG_CK_MON_SEL))
+#define BIT_GET_REG_CK_MON_SEL(x) \
+ (((x) >> BIT_SHIFT_REG_CK_MON_SEL) & BIT_MASK_REG_CK_MON_SEL)
+#define BIT_SET_REG_CK_MON_SEL(x, v) \
+ (BIT_CLEAR_REG_CK_MON_SEL(x) | BIT_REG_CK_MON_SEL(v))
-/* 2 REG_WL_DSS_STATUS1 (Offset 0x10DC) */
+#endif
-#define BIT_WL_DSS_READY BIT(21)
-#define BIT_WL_DSS_WSORT_GO BIT(20)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */
+#define BIT_PFD_DN_GATED BIT(28)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8822C_SUPPORT)
-/* 2 REG_FW_DBG0 (Offset 0x10E0) */
+/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */
+#define BIT_REG_CK_MON_EN BIT(28)
-#define BIT_SHIFT_FW_DBG0 0
-#define BIT_MASK_FW_DBG0 0xffffffffL
-#define BIT_FW_DBG0(x) (((x) & BIT_MASK_FW_DBG0) << BIT_SHIFT_FW_DBG0)
-#define BIT_GET_FW_DBG0(x) (((x) >> BIT_SHIFT_FW_DBG0) & BIT_MASK_FW_DBG0)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_FW_DBG1 (Offset 0x10E4) */
+/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */
+#define BIT_PFD_UP_GATED BIT(27)
-#define BIT_SHIFT_FW_DBG1 0
-#define BIT_MASK_FW_DBG1 0xffffffffL
-#define BIT_FW_DBG1(x) (((x) & BIT_MASK_FW_DBG1) << BIT_SHIFT_FW_DBG1)
-#define BIT_GET_FW_DBG1(x) (((x) >> BIT_SHIFT_FW_DBG1) & BIT_MASK_FW_DBG1)
+#endif
+#if (HALMAC_8822C_SUPPORT)
-/* 2 REG_FW_DBG2 (Offset 0x10E8) */
+/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */
+#define BIT_REG_XTAL_FREQ_SEL BIT(27)
-#define BIT_SHIFT_FW_DBG2 0
-#define BIT_MASK_FW_DBG2 0xffffffffL
-#define BIT_FW_DBG2(x) (((x) & BIT_MASK_FW_DBG2) << BIT_SHIFT_FW_DBG2)
-#define BIT_GET_FW_DBG2(x) (((x) >> BIT_SHIFT_FW_DBG2) & BIT_MASK_FW_DBG2)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_FW_DBG3 (Offset 0x10EC) */
+/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */
+#define BIT_PFD_RESET_GATED BIT(26)
-#define BIT_SHIFT_FW_DBG3 0
-#define BIT_MASK_FW_DBG3 0xffffffffL
-#define BIT_FW_DBG3(x) (((x) & BIT_MASK_FW_DBG3) << BIT_SHIFT_FW_DBG3)
-#define BIT_GET_FW_DBG3(x) (((x) >> BIT_SHIFT_FW_DBG3) & BIT_MASK_FW_DBG3)
+#endif
+#if (HALMAC_8822C_SUPPORT)
-/* 2 REG_FW_DBG4 (Offset 0x10F0) */
+/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */
+#define BIT_REG_XTAL_EDGE_SEL BIT(26)
+#define BIT_REG_VCO_KVCO BIT(25)
-#define BIT_SHIFT_FW_DBG4 0
-#define BIT_MASK_FW_DBG4 0xffffffffL
-#define BIT_FW_DBG4(x) (((x) & BIT_MASK_FW_DBG4) << BIT_SHIFT_FW_DBG4)
-#define BIT_GET_FW_DBG4(x) (((x) >> BIT_SHIFT_FW_DBG4) & BIT_MASK_FW_DBG4)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_FW_DBG5 (Offset 0x10F4) */
+/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */
+#define BIT_SHIFT_PFD_OUT_DRV_1_0 24
+#define BIT_MASK_PFD_OUT_DRV_1_0 0x3
+#define BIT_PFD_OUT_DRV_1_0(x) \
+ (((x) & BIT_MASK_PFD_OUT_DRV_1_0) << BIT_SHIFT_PFD_OUT_DRV_1_0)
+#define BITS_PFD_OUT_DRV_1_0 \
+ (BIT_MASK_PFD_OUT_DRV_1_0 << BIT_SHIFT_PFD_OUT_DRV_1_0)
+#define BIT_CLEAR_PFD_OUT_DRV_1_0(x) ((x) & (~BITS_PFD_OUT_DRV_1_0))
+#define BIT_GET_PFD_OUT_DRV_1_0(x) \
+ (((x) >> BIT_SHIFT_PFD_OUT_DRV_1_0) & BIT_MASK_PFD_OUT_DRV_1_0)
+#define BIT_SET_PFD_OUT_DRV_1_0(x, v) \
+ (BIT_CLEAR_PFD_OUT_DRV_1_0(x) | BIT_PFD_OUT_DRV_1_0(v))
-#define BIT_SHIFT_FW_DBG5 0
-#define BIT_MASK_FW_DBG5 0xffffffffL
-#define BIT_FW_DBG5(x) (((x) & BIT_MASK_FW_DBG5) << BIT_SHIFT_FW_DBG5)
-#define BIT_GET_FW_DBG5(x) (((x) >> BIT_SHIFT_FW_DBG5) & BIT_MASK_FW_DBG5)
+#endif
+#if (HALMAC_8822C_SUPPORT)
-/* 2 REG_FW_DBG6 (Offset 0x10F8) */
+/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */
+#define BIT_REG_SDM_EDGE_SEL BIT(24)
+#define BIT_REG_SDM_CK_SEL BIT(23)
+#define BIT_REG_SDM_CK_GATED BIT(22)
+#define BIT_REG_PFD_RESET_GATED BIT(21)
-#define BIT_SHIFT_FW_DBG6 0
-#define BIT_MASK_FW_DBG6 0xffffffffL
-#define BIT_FW_DBG6(x) (((x) & BIT_MASK_FW_DBG6) << BIT_SHIFT_FW_DBG6)
-#define BIT_GET_FW_DBG6(x) (((x) >> BIT_SHIFT_FW_DBG6) & BIT_MASK_FW_DBG6)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_FW_DBG7 (Offset 0x10FC) */
+/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */
+#define BIT_SHIFT_LPF_TIEMID_2_0 20
+#define BIT_MASK_LPF_TIEMID_2_0 0x7
+#define BIT_LPF_TIEMID_2_0(x) \
+ (((x) & BIT_MASK_LPF_TIEMID_2_0) << BIT_SHIFT_LPF_TIEMID_2_0)
+#define BITS_LPF_TIEMID_2_0 \
+ (BIT_MASK_LPF_TIEMID_2_0 << BIT_SHIFT_LPF_TIEMID_2_0)
+#define BIT_CLEAR_LPF_TIEMID_2_0(x) ((x) & (~BITS_LPF_TIEMID_2_0))
+#define BIT_GET_LPF_TIEMID_2_0(x) \
+ (((x) >> BIT_SHIFT_LPF_TIEMID_2_0) & BIT_MASK_LPF_TIEMID_2_0)
+#define BIT_SET_LPF_TIEMID_2_0(x, v) \
+ (BIT_CLEAR_LPF_TIEMID_2_0(x) | BIT_LPF_TIEMID_2_0(v))
-#define BIT_SHIFT_FW_DBG7 0
-#define BIT_MASK_FW_DBG7 0xffffffffL
-#define BIT_FW_DBG7(x) (((x) & BIT_MASK_FW_DBG7) << BIT_SHIFT_FW_DBG7)
-#define BIT_GET_FW_DBG7(x) (((x) >> BIT_SHIFT_FW_DBG7) & BIT_MASK_FW_DBG7)
+#endif
+#if (HALMAC_8822C_SUPPORT)
-/* 2 REG_CR_EXT (Offset 0x1100) */
+/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */
+#define BIT_SHIFT_REG_LPF_R3_FAST 16
+#define BIT_MASK_REG_LPF_R3_FAST 0x1f
+#define BIT_REG_LPF_R3_FAST(x) \
+ (((x) & BIT_MASK_REG_LPF_R3_FAST) << BIT_SHIFT_REG_LPF_R3_FAST)
+#define BITS_REG_LPF_R3_FAST \
+ (BIT_MASK_REG_LPF_R3_FAST << BIT_SHIFT_REG_LPF_R3_FAST)
+#define BIT_CLEAR_REG_LPF_R3_FAST(x) ((x) & (~BITS_REG_LPF_R3_FAST))
+#define BIT_GET_REG_LPF_R3_FAST(x) \
+ (((x) >> BIT_SHIFT_REG_LPF_R3_FAST) & BIT_MASK_REG_LPF_R3_FAST)
+#define BIT_SET_REG_LPF_R3_FAST(x, v) \
+ (BIT_CLEAR_REG_LPF_R3_FAST(x) | BIT_REG_LPF_R3_FAST(v))
-#define BIT_SHIFT_PHY_REQ_DELAY 24
-#define BIT_MASK_PHY_REQ_DELAY 0xf
-#define BIT_PHY_REQ_DELAY(x) (((x) & BIT_MASK_PHY_REQ_DELAY) << BIT_SHIFT_PHY_REQ_DELAY)
-#define BIT_GET_PHY_REQ_DELAY(x) (((x) >> BIT_SHIFT_PHY_REQ_DELAY) & BIT_MASK_PHY_REQ_DELAY)
+#endif
-#define BIT_SPD_DOWN BIT(16)
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_NETYPE4 4
-#define BIT_MASK_NETYPE4 0x3
-#define BIT_NETYPE4(x) (((x) & BIT_MASK_NETYPE4) << BIT_SHIFT_NETYPE4)
-#define BIT_GET_NETYPE4(x) (((x) >> BIT_SHIFT_NETYPE4) & BIT_MASK_NETYPE4)
+/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */
+#define BIT_SHIFT_LPF_R3_4_0 15
+#define BIT_MASK_LPF_R3_4_0 0x1f
+#define BIT_LPF_R3_4_0(x) (((x) & BIT_MASK_LPF_R3_4_0) << BIT_SHIFT_LPF_R3_4_0)
+#define BITS_LPF_R3_4_0 (BIT_MASK_LPF_R3_4_0 << BIT_SHIFT_LPF_R3_4_0)
+#define BIT_CLEAR_LPF_R3_4_0(x) ((x) & (~BITS_LPF_R3_4_0))
+#define BIT_GET_LPF_R3_4_0(x) \
+ (((x) >> BIT_SHIFT_LPF_R3_4_0) & BIT_MASK_LPF_R3_4_0)
+#define BIT_SET_LPF_R3_4_0(x, v) (BIT_CLEAR_LPF_R3_4_0(x) | BIT_LPF_R3_4_0(v))
-#define BIT_SHIFT_NETYPE3 2
-#define BIT_MASK_NETYPE3 0x3
-#define BIT_NETYPE3(x) (((x) & BIT_MASK_NETYPE3) << BIT_SHIFT_NETYPE3)
-#define BIT_GET_NETYPE3(x) (((x) >> BIT_SHIFT_NETYPE3) & BIT_MASK_NETYPE3)
+#endif
+#if (HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_NETYPE2 0
-#define BIT_MASK_NETYPE2 0x3
-#define BIT_NETYPE2(x) (((x) & BIT_MASK_NETYPE2) << BIT_SHIFT_NETYPE2)
-#define BIT_GET_NETYPE2(x) (((x) >> BIT_SHIFT_NETYPE2) & BIT_MASK_NETYPE2)
+/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */
+#define BIT_SHIFT_REG_LPF_R2_FAST 11
+#define BIT_MASK_REG_LPF_R2_FAST 0x1f
+#define BIT_REG_LPF_R2_FAST(x) \
+ (((x) & BIT_MASK_REG_LPF_R2_FAST) << BIT_SHIFT_REG_LPF_R2_FAST)
+#define BITS_REG_LPF_R2_FAST \
+ (BIT_MASK_REG_LPF_R2_FAST << BIT_SHIFT_REG_LPF_R2_FAST)
+#define BIT_CLEAR_REG_LPF_R2_FAST(x) ((x) & (~BITS_REG_LPF_R2_FAST))
+#define BIT_GET_REG_LPF_R2_FAST(x) \
+ (((x) >> BIT_SHIFT_REG_LPF_R2_FAST) & BIT_MASK_REG_LPF_R2_FAST)
+#define BIT_SET_REG_LPF_R2_FAST(x, v) \
+ (BIT_CLEAR_REG_LPF_R2_FAST(x) | BIT_REG_LPF_R2_FAST(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */
+#define BIT_SHIFT_LPF_R2_4_0 10
+#define BIT_MASK_LPF_R2_4_0 0x1f
+#define BIT_LPF_R2_4_0(x) (((x) & BIT_MASK_LPF_R2_4_0) << BIT_SHIFT_LPF_R2_4_0)
+#define BITS_LPF_R2_4_0 (BIT_MASK_LPF_R2_4_0 << BIT_SHIFT_LPF_R2_4_0)
+#define BIT_CLEAR_LPF_R2_4_0(x) ((x) & (~BITS_LPF_R2_4_0))
+#define BIT_GET_LPF_R2_4_0(x) \
+ (((x) >> BIT_SHIFT_LPF_R2_4_0) & BIT_MASK_LPF_R2_4_0)
+#define BIT_SET_LPF_R2_4_0(x, v) (BIT_CLEAR_LPF_R2_4_0(x) | BIT_LPF_R2_4_0(v))
-/* 2 REG_FWFF (Offset 0x1114) */
+#endif
+#if (HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_PKTNUM_TH 24
-#define BIT_MASK_PKTNUM_TH 0xff
-#define BIT_PKTNUM_TH(x) (((x) & BIT_MASK_PKTNUM_TH) << BIT_SHIFT_PKTNUM_TH)
-#define BIT_GET_PKTNUM_TH(x) (((x) >> BIT_SHIFT_PKTNUM_TH) & BIT_MASK_PKTNUM_TH)
+/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */
+#define BIT_SHIFT_REG_LPF_C3_FAST 8
+#define BIT_MASK_REG_LPF_C3_FAST 0x7
+#define BIT_REG_LPF_C3_FAST(x) \
+ (((x) & BIT_MASK_REG_LPF_C3_FAST) << BIT_SHIFT_REG_LPF_C3_FAST)
+#define BITS_REG_LPF_C3_FAST \
+ (BIT_MASK_REG_LPF_C3_FAST << BIT_SHIFT_REG_LPF_C3_FAST)
+#define BIT_CLEAR_REG_LPF_C3_FAST(x) ((x) & (~BITS_REG_LPF_C3_FAST))
+#define BIT_GET_REG_LPF_C3_FAST(x) \
+ (((x) >> BIT_SHIFT_REG_LPF_C3_FAST) & BIT_MASK_REG_LPF_C3_FAST)
+#define BIT_SET_REG_LPF_C3_FAST(x, v) \
+ (BIT_CLEAR_REG_LPF_C3_FAST(x) | BIT_REG_LPF_C3_FAST(v))
+
+#define BIT_SHIFT_REG_LPF_C2_FAST 5
+#define BIT_MASK_REG_LPF_C2_FAST 0x7
+#define BIT_REG_LPF_C2_FAST(x) \
+ (((x) & BIT_MASK_REG_LPF_C2_FAST) << BIT_SHIFT_REG_LPF_C2_FAST)
+#define BITS_REG_LPF_C2_FAST \
+ (BIT_MASK_REG_LPF_C2_FAST << BIT_SHIFT_REG_LPF_C2_FAST)
+#define BIT_CLEAR_REG_LPF_C2_FAST(x) ((x) & (~BITS_REG_LPF_C2_FAST))
+#define BIT_GET_REG_LPF_C2_FAST(x) \
+ (((x) >> BIT_SHIFT_REG_LPF_C2_FAST) & BIT_MASK_REG_LPF_C2_FAST)
+#define BIT_SET_REG_LPF_C2_FAST(x, v) \
+ (BIT_CLEAR_REG_LPF_C2_FAST(x) | BIT_REG_LPF_C2_FAST(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */
+#define BIT_SHIFT_LPF_C3_5_0 4
+#define BIT_MASK_LPF_C3_5_0 0x3f
+#define BIT_LPF_C3_5_0(x) (((x) & BIT_MASK_LPF_C3_5_0) << BIT_SHIFT_LPF_C3_5_0)
+#define BITS_LPF_C3_5_0 (BIT_MASK_LPF_C3_5_0 << BIT_SHIFT_LPF_C3_5_0)
+#define BIT_CLEAR_LPF_C3_5_0(x) ((x) & (~BITS_LPF_C3_5_0))
+#define BIT_GET_LPF_C3_5_0(x) \
+ (((x) >> BIT_SHIFT_LPF_C3_5_0) & BIT_MASK_LPF_C3_5_0)
+#define BIT_SET_LPF_C3_5_0(x, v) (BIT_CLEAR_LPF_C3_5_0(x) | BIT_LPF_C3_5_0(v))
-/* 2 REG_FWFF (Offset 0x1114) */
+#endif
+#if (HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_PKTNUM_TH_V1 24
-#define BIT_MASK_PKTNUM_TH_V1 0xff
-#define BIT_PKTNUM_TH_V1(x) (((x) & BIT_MASK_PKTNUM_TH_V1) << BIT_SHIFT_PKTNUM_TH_V1)
-#define BIT_GET_PKTNUM_TH_V1(x) (((x) >> BIT_SHIFT_PKTNUM_TH_V1) & BIT_MASK_PKTNUM_TH_V1)
+/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */
+#define BIT_SHIFT_REG_LPF_C1_FAST 2
+#define BIT_MASK_REG_LPF_C1_FAST 0x7
+#define BIT_REG_LPF_C1_FAST(x) \
+ (((x) & BIT_MASK_REG_LPF_C1_FAST) << BIT_SHIFT_REG_LPF_C1_FAST)
+#define BITS_REG_LPF_C1_FAST \
+ (BIT_MASK_REG_LPF_C1_FAST << BIT_SHIFT_REG_LPF_C1_FAST)
+#define BIT_CLEAR_REG_LPF_C1_FAST(x) ((x) & (~BITS_REG_LPF_C1_FAST))
+#define BIT_GET_REG_LPF_C1_FAST(x) \
+ (((x) >> BIT_SHIFT_REG_LPF_C1_FAST) & BIT_MASK_REG_LPF_C1_FAST)
+#define BIT_SET_REG_LPF_C1_FAST(x, v) \
+ (BIT_CLEAR_REG_LPF_C1_FAST(x) | BIT_REG_LPF_C1_FAST(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */
+#define BIT_SHIFT_LPF_C2_5_2 0
+#define BIT_MASK_LPF_C2_5_2 0xf
+#define BIT_LPF_C2_5_2(x) (((x) & BIT_MASK_LPF_C2_5_2) << BIT_SHIFT_LPF_C2_5_2)
+#define BITS_LPF_C2_5_2 (BIT_MASK_LPF_C2_5_2 << BIT_SHIFT_LPF_C2_5_2)
+#define BIT_CLEAR_LPF_C2_5_2(x) ((x) & (~BITS_LPF_C2_5_2))
+#define BIT_GET_LPF_C2_5_2(x) \
+ (((x) >> BIT_SHIFT_LPF_C2_5_2) & BIT_MASK_LPF_C2_5_2)
+#define BIT_SET_LPF_C2_5_2(x, v) (BIT_CLEAR_LPF_C2_5_2(x) | BIT_LPF_C2_5_2(v))
-/* 2 REG_FWFF (Offset 0x1114) */
+#endif
+#if (HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_TIMER_TH 16
-#define BIT_MASK_TIMER_TH 0xff
-#define BIT_TIMER_TH(x) (((x) & BIT_MASK_TIMER_TH) << BIT_SHIFT_TIMER_TH)
-#define BIT_GET_TIMER_TH(x) (((x) >> BIT_SHIFT_TIMER_TH) & BIT_MASK_TIMER_TH)
+/* 2 REG_ANAPAR_MAC_1 (Offset 0x101C) */
+#define BIT_SHIFT_REG_LPF_R3_V1 0
+#define BIT_MASK_REG_LPF_R3_V1 0x3
+#define BIT_REG_LPF_R3_V1(x) \
+ (((x) & BIT_MASK_REG_LPF_R3_V1) << BIT_SHIFT_REG_LPF_R3_V1)
+#define BITS_REG_LPF_R3_V1 (BIT_MASK_REG_LPF_R3_V1 << BIT_SHIFT_REG_LPF_R3_V1)
+#define BIT_CLEAR_REG_LPF_R3_V1(x) ((x) & (~BITS_REG_LPF_R3_V1))
+#define BIT_GET_REG_LPF_R3_V1(x) \
+ (((x) >> BIT_SHIFT_REG_LPF_R3_V1) & BIT_MASK_REG_LPF_R3_V1)
+#define BIT_SET_REG_LPF_R3_V1(x, v) \
+ (BIT_CLEAR_REG_LPF_R3_V1(x) | BIT_REG_LPF_R3_V1(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */
+#define BIT_CK_PHASE_SEL BIT(31)
+#define BIT_CK960M_EN BIT(30)
-/* 2 REG_FWFF (Offset 0x1114) */
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */
-#define BIT_EN_SPD BIT(6)
-#define BIT_EN_RXDMA_ALIGN_V1 BIT(1)
+#define BIT_SHIFT_AGPIO_DRV_V1 30
+#define BIT_MASK_AGPIO_DRV_V1 0x3
+#define BIT_AGPIO_DRV_V1(x) \
+ (((x) & BIT_MASK_AGPIO_DRV_V1) << BIT_SHIFT_AGPIO_DRV_V1)
+#define BITS_AGPIO_DRV_V1 (BIT_MASK_AGPIO_DRV_V1 << BIT_SHIFT_AGPIO_DRV_V1)
+#define BIT_CLEAR_AGPIO_DRV_V1(x) ((x) & (~BITS_AGPIO_DRV_V1))
+#define BIT_GET_AGPIO_DRV_V1(x) \
+ (((x) >> BIT_SHIFT_AGPIO_DRV_V1) & BIT_MASK_AGPIO_DRV_V1)
+#define BIT_SET_AGPIO_DRV_V1(x, v) \
+ (BIT_CLEAR_AGPIO_DRV_V1(x) | BIT_AGPIO_DRV_V1(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */
+#define BIT_CK640M_EN BIT(29)
-/* 2 REG_FWFF (Offset 0x1114) */
+#endif
+#if (HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_RXPKT1ENADDR 0
-#define BIT_MASK_RXPKT1ENADDR 0xffff
-#define BIT_RXPKT1ENADDR(x) (((x) & BIT_MASK_RXPKT1ENADDR) << BIT_SHIFT_RXPKT1ENADDR)
-#define BIT_GET_RXPKT1ENADDR(x) (((x) >> BIT_SHIFT_RXPKT1ENADDR) & BIT_MASK_RXPKT1ENADDR)
+/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */
+#define BIT_AGPIO_GPO_V1 BIT(29)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */
+#define BIT_CK240M_EN BIT(28)
-/* 2 REG_FWFF (Offset 0x1114) */
+#endif
-#define BIT_EN_TXDMA_ALIGN_V1 BIT(0)
+#if (HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_MDIO_REG_ADDR 0
-#define BIT_MASK_MDIO_REG_ADDR 0x1f
-#define BIT_MDIO_REG_ADDR(x) (((x) & BIT_MASK_MDIO_REG_ADDR) << BIT_SHIFT_MDIO_REG_ADDR)
-#define BIT_GET_MDIO_REG_ADDR(x) (((x) >> BIT_SHIFT_MDIO_REG_ADDR) & BIT_MASK_MDIO_REG_ADDR)
+/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */
+#define BIT_AGPIO_GPE_V1 BIT(28)
+#define BIT_SEL_CLK BIT(27)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */
-/* 2 REG_FE2IMR (Offset 0x1120) */
+#define BIT_SHIFT_CK_MON_SEL_2_0 25
+#define BIT_MASK_CK_MON_SEL_2_0 0x7
+#define BIT_CK_MON_SEL_2_0(x) \
+ (((x) & BIT_MASK_CK_MON_SEL_2_0) << BIT_SHIFT_CK_MON_SEL_2_0)
+#define BITS_CK_MON_SEL_2_0 \
+ (BIT_MASK_CK_MON_SEL_2_0 << BIT_SHIFT_CK_MON_SEL_2_0)
+#define BIT_CLEAR_CK_MON_SEL_2_0(x) ((x) & (~BITS_CK_MON_SEL_2_0))
+#define BIT_GET_CK_MON_SEL_2_0(x) \
+ (((x) >> BIT_SHIFT_CK_MON_SEL_2_0) & BIT_MASK_CK_MON_SEL_2_0)
+#define BIT_SET_CK_MON_SEL_2_0(x, v) \
+ (BIT_CLEAR_CK_MON_SEL_2_0(x) | BIT_CK_MON_SEL_2_0(v))
-#define BIT__FE4ISR__IND_MSK BIT(29)
+#define BIT_CK_MON_EN_V1 BIT(24)
+#define BIT_XTAL_SOURCE_SEL BIT(23)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */
+#define BIT_SHIFT_LS_XTAL_SEL 23
+#define BIT_MASK_LS_XTAL_SEL 0xf
+#define BIT_LS_XTAL_SEL(x) \
+ (((x) & BIT_MASK_LS_XTAL_SEL) << BIT_SHIFT_LS_XTAL_SEL)
+#define BITS_LS_XTAL_SEL (BIT_MASK_LS_XTAL_SEL << BIT_SHIFT_LS_XTAL_SEL)
+#define BIT_CLEAR_LS_XTAL_SEL(x) ((x) & (~BITS_LS_XTAL_SEL))
+#define BIT_GET_LS_XTAL_SEL(x) \
+ (((x) >> BIT_SHIFT_LS_XTAL_SEL) & BIT_MASK_LS_XTAL_SEL)
+#define BIT_SET_LS_XTAL_SEL(x, v) \
+ (BIT_CLEAR_LS_XTAL_SEL(x) | BIT_LS_XTAL_SEL(v))
-/* 2 REG_FE2IMR (Offset 0x1120) */
+#endif
-#define BIT_FS_TXSC_DESC_DONE_INT_EN BIT(28)
-#define BIT_FS_TXSC_BKDONE_INT_EN BIT(27)
-#define BIT_FS_TXSC_BEDONE_INT_EN BIT(26)
-#define BIT_FS_TXSC_VIDONE_INT_EN BIT(25)
-#define BIT_FS_TXSC_VODONE_INT_EN BIT(24)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */
+#define BIT_XTAL_FREQ_SEL BIT(22)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8822C_SUPPORT)
-/* 2 REG_FE2IMR (Offset 0x1120) */
+/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */
-#define BIT_FS_ATIM_MB7_INT_EN BIT(23)
-#define BIT_FS_ATIM_MB6_INT_EN BIT(22)
-#define BIT_FS_ATIM_MB5_INT_EN BIT(21)
-#define BIT_FS_ATIM_MB4_INT_EN BIT(20)
-#define BIT_FS_ATIM_MB3_INT_EN BIT(19)
-#define BIT_FS_ATIM_MB2_INT_EN BIT(18)
-#define BIT_FS_ATIM_MB1_INT_EN BIT(17)
-#define BIT_FS_ATIM_MB0_INT_EN BIT(16)
-#define BIT_FS_TBTT4INT_EN BIT(11)
-#define BIT_FS_TBTT3INT_EN BIT(10)
-#define BIT_FS_TBTT2INT_EN BIT(9)
-#define BIT_FS_TBTT1INT_EN BIT(8)
-#define BIT_FS_TBTT0_MB7INT_EN BIT(7)
-#define BIT_FS_TBTT0_MB6INT_EN BIT(6)
-#define BIT_FS_TBTT0_MB5INT_EN BIT(5)
-#define BIT_FS_TBTT0_MB4INT_EN BIT(4)
-#define BIT_FS_TBTT0_MB3INT_EN BIT(3)
-#define BIT_FS_TBTT0_MB2INT_EN BIT(2)
-#define BIT_FS_TBTT0_MB1INT_EN BIT(1)
-#define BIT_FS_TBTT0_INT_EN BIT(0)
+#define BIT_LS_SDM_ORDER_V1 BIT(22)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */
+#define BIT_XTAL_EDGE_SEL BIT(21)
-/* 2 REG_FE2ISR (Offset 0x1124) */
+#endif
-#define BIT__FE4ISR__IND_INT BIT(29)
+#if (HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */
+#define BIT_LS_DELAY_PH BIT(21)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_FE2ISR (Offset 0x1124) */
+/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */
-#define BIT_FS_TXSC_DESC_DONE_INT BIT(28)
-#define BIT_FS_TXSC_BKDONE_INT BIT(27)
-#define BIT_FS_TXSC_BEDONE_INT BIT(26)
-#define BIT_FS_TXSC_VIDONE_INT BIT(25)
-#define BIT_FS_TXSC_VODONE_INT BIT(24)
+#define BIT_XTAL_BUF_SEL BIT(20)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */
+#define BIT_DIVIDER_SEL BIT(20)
-/* 2 REG_FE2ISR (Offset 0x1124) */
+#define BIT_SHIFT_PCODE 15
+#define BIT_MASK_PCODE 0x1f
+#define BIT_PCODE(x) (((x) & BIT_MASK_PCODE) << BIT_SHIFT_PCODE)
+#define BITS_PCODE (BIT_MASK_PCODE << BIT_SHIFT_PCODE)
+#define BIT_CLEAR_PCODE(x) ((x) & (~BITS_PCODE))
+#define BIT_GET_PCODE(x) (((x) >> BIT_SHIFT_PCODE) & BIT_MASK_PCODE)
+#define BIT_SET_PCODE(x, v) (BIT_CLEAR_PCODE(x) | BIT_PCODE(v))
-#define BIT_FS_ATIM_MB7_INT BIT(23)
-#define BIT_FS_ATIM_MB6_INT BIT(22)
-#define BIT_FS_ATIM_MB5_INT BIT(21)
-#define BIT_FS_ATIM_MB4_INT BIT(20)
-#define BIT_FS_ATIM_MB3_INT BIT(19)
-#define BIT_FS_ATIM_MB2_INT BIT(18)
-#define BIT_FS_ATIM_MB1_INT BIT(17)
-#define BIT_FS_ATIM_MB0_INT BIT(16)
-#define BIT_FS_TBTT4INT BIT(11)
-#define BIT_FS_TBTT3INT BIT(10)
-#define BIT_FS_TBTT2INT BIT(9)
-#define BIT_FS_TBTT1INT BIT(8)
-#define BIT_FS_TBTT0_MB7INT BIT(7)
-#define BIT_FS_TBTT0_MB6INT BIT(6)
-#define BIT_FS_TBTT0_MB5INT BIT(5)
-#define BIT_FS_TBTT0_MB4INT BIT(4)
-#define BIT_FS_TBTT0_MB3INT BIT(3)
-#define BIT_FS_TBTT0_MB2INT BIT(2)
-#define BIT_FS_TBTT0_MB1INT BIT(1)
-#define BIT_FS_TBTT0_INT BIT(0)
+#define BIT_SHIFT_NCODE 7
+#define BIT_MASK_NCODE 0xff
+#define BIT_NCODE(x) (((x) & BIT_MASK_NCODE) << BIT_SHIFT_NCODE)
+#define BITS_NCODE (BIT_MASK_NCODE << BIT_SHIFT_NCODE)
+#define BIT_CLEAR_NCODE(x) ((x) & (~BITS_NCODE))
+#define BIT_GET_NCODE(x) (((x) >> BIT_SHIFT_NCODE) & BIT_MASK_NCODE)
+#define BIT_SET_NCODE(x, v) (BIT_CLEAR_NCODE(x) | BIT_NCODE(v))
-#endif
+#define BIT_REG_BEACON BIT(6)
+#define BIT_REG_MBIASE BIT(5)
+#endif
-#if (HALMAC_8197F_SUPPORT)
+#if (HALMAC_8814B_SUPPORT)
+/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */
-/* 2 REG_FE3IMR (Offset 0x1128) */
+#define BIT_SHIFT_VCO_CV_7_0 4
+#define BIT_MASK_VCO_CV_7_0 0xff
+#define BIT_VCO_CV_7_0(x) (((x) & BIT_MASK_VCO_CV_7_0) << BIT_SHIFT_VCO_CV_7_0)
+#define BITS_VCO_CV_7_0 (BIT_MASK_VCO_CV_7_0 << BIT_SHIFT_VCO_CV_7_0)
+#define BIT_CLEAR_VCO_CV_7_0(x) ((x) & (~BITS_VCO_CV_7_0))
+#define BIT_GET_VCO_CV_7_0(x) \
+ (((x) >> BIT_SHIFT_VCO_CV_7_0) & BIT_MASK_VCO_CV_7_0)
+#define BIT_SET_VCO_CV_7_0(x, v) (BIT_CLEAR_VCO_CV_7_0(x) | BIT_VCO_CV_7_0(v))
-#define BIT_FS_BCNELY4_AGGR_INT_EN BIT(31)
+#define BIT_VCO_KVCO BIT(3)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_FE3IMR (Offset 0x1128) */
+/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */
-#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT__EN BIT(31)
+#define BIT_SHIFT_REG_FAST_SEL 3
+#define BIT_MASK_REG_FAST_SEL 0x3
+#define BIT_REG_FAST_SEL(x) \
+ (((x) & BIT_MASK_REG_FAST_SEL) << BIT_SHIFT_REG_FAST_SEL)
+#define BITS_REG_FAST_SEL (BIT_MASK_REG_FAST_SEL << BIT_SHIFT_REG_FAST_SEL)
+#define BIT_CLEAR_REG_FAST_SEL(x) ((x) & (~BITS_REG_FAST_SEL))
+#define BIT_GET_REG_FAST_SEL(x) \
+ (((x) >> BIT_SHIFT_REG_FAST_SEL) & BIT_MASK_REG_FAST_SEL)
+#define BIT_SET_REG_FAST_SEL(x, v) \
+ (BIT_CLEAR_REG_FAST_SEL(x) | BIT_REG_FAST_SEL(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */
+#define BIT_SDM_EDGE_SEL BIT(2)
-/* 2 REG_FE3IMR (Offset 0x1128) */
+#endif
-#define BIT_FS_BCNELY3_AGGR_INT_EN BIT(30)
+#if (HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */
+#define BIT_REG_CK960M_EN BIT(2)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_FE3IMR (Offset 0x1128) */
+/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */
-#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT__EN BIT(30)
+#define BIT_SDM_CK_SEL BIT(1)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */
+#define BIT_REG_CK320M_EN BIT(1)
-/* 2 REG_FE3IMR (Offset 0x1128) */
+#endif
-#define BIT_FS_BCNELY2_AGGR_INT_EN BIT(29)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */
+#define BIT_SDM_CK_GATED BIT(0)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8822C_SUPPORT)
-/* 2 REG_FE3IMR (Offset 0x1128) */
+/* 2 REG_ANAPAR_MAC_2 (Offset 0x1020) */
-#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT__EN BIT(29)
+#define BIT_REG_CK_5M_EN BIT(0)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_ANAPAR_MAC_3 (Offset 0x1024) */
+#define BIT_SHIFT_LCK_WAIT_CYCLE_2_0 28
+#define BIT_MASK_LCK_WAIT_CYCLE_2_0 0x7
+#define BIT_LCK_WAIT_CYCLE_2_0(x) \
+ (((x) & BIT_MASK_LCK_WAIT_CYCLE_2_0) << BIT_SHIFT_LCK_WAIT_CYCLE_2_0)
+#define BITS_LCK_WAIT_CYCLE_2_0 \
+ (BIT_MASK_LCK_WAIT_CYCLE_2_0 << BIT_SHIFT_LCK_WAIT_CYCLE_2_0)
+#define BIT_CLEAR_LCK_WAIT_CYCLE_2_0(x) ((x) & (~BITS_LCK_WAIT_CYCLE_2_0))
+#define BIT_GET_LCK_WAIT_CYCLE_2_0(x) \
+ (((x) >> BIT_SHIFT_LCK_WAIT_CYCLE_2_0) & BIT_MASK_LCK_WAIT_CYCLE_2_0)
+#define BIT_SET_LCK_WAIT_CYCLE_2_0(x, v) \
+ (BIT_CLEAR_LCK_WAIT_CYCLE_2_0(x) | BIT_LCK_WAIT_CYCLE_2_0(v))
-/* 2 REG_FE3IMR (Offset 0x1128) */
+#define BIT_SHIFT_LCK_VCO_DIVISOR_1_0 26
+#define BIT_MASK_LCK_VCO_DIVISOR_1_0 0x3
+#define BIT_LCK_VCO_DIVISOR_1_0(x) \
+ (((x) & BIT_MASK_LCK_VCO_DIVISOR_1_0) << BIT_SHIFT_LCK_VCO_DIVISOR_1_0)
+#define BITS_LCK_VCO_DIVISOR_1_0 \
+ (BIT_MASK_LCK_VCO_DIVISOR_1_0 << BIT_SHIFT_LCK_VCO_DIVISOR_1_0)
+#define BIT_CLEAR_LCK_VCO_DIVISOR_1_0(x) ((x) & (~BITS_LCK_VCO_DIVISOR_1_0))
+#define BIT_GET_LCK_VCO_DIVISOR_1_0(x) \
+ (((x) >> BIT_SHIFT_LCK_VCO_DIVISOR_1_0) & BIT_MASK_LCK_VCO_DIVISOR_1_0)
+#define BIT_SET_LCK_VCO_DIVISOR_1_0(x, v) \
+ (BIT_CLEAR_LCK_VCO_DIVISOR_1_0(x) | BIT_LCK_VCO_DIVISOR_1_0(v))
-#define BIT_FS_BCNELY1_AGGR_INT_EN BIT(28)
+#define BIT_SHIFT_LCK_SEARCH_MODE_1_0 24
+#define BIT_MASK_LCK_SEARCH_MODE_1_0 0x3
+#define BIT_LCK_SEARCH_MODE_1_0(x) \
+ (((x) & BIT_MASK_LCK_SEARCH_MODE_1_0) << BIT_SHIFT_LCK_SEARCH_MODE_1_0)
+#define BITS_LCK_SEARCH_MODE_1_0 \
+ (BIT_MASK_LCK_SEARCH_MODE_1_0 << BIT_SHIFT_LCK_SEARCH_MODE_1_0)
+#define BIT_CLEAR_LCK_SEARCH_MODE_1_0(x) ((x) & (~BITS_LCK_SEARCH_MODE_1_0))
+#define BIT_GET_LCK_SEARCH_MODE_1_0(x) \
+ (((x) >> BIT_SHIFT_LCK_SEARCH_MODE_1_0) & BIT_MASK_LCK_SEARCH_MODE_1_0)
+#define BIT_SET_LCK_SEARCH_MODE_1_0(x, v) \
+ (BIT_CLEAR_LCK_SEARCH_MODE_1_0(x) | BIT_LCK_SEARCH_MODE_1_0(v))
-#endif
+#define BIT_SHIFT_LS_CV_OFFSET_3_0 12
+#define BIT_MASK_LS_CV_OFFSET_3_0 0xf
+#define BIT_LS_CV_OFFSET_3_0(x) \
+ (((x) & BIT_MASK_LS_CV_OFFSET_3_0) << BIT_SHIFT_LS_CV_OFFSET_3_0)
+#define BITS_LS_CV_OFFSET_3_0 \
+ (BIT_MASK_LS_CV_OFFSET_3_0 << BIT_SHIFT_LS_CV_OFFSET_3_0)
+#define BIT_CLEAR_LS_CV_OFFSET_3_0(x) ((x) & (~BITS_LS_CV_OFFSET_3_0))
+#define BIT_GET_LS_CV_OFFSET_3_0(x) \
+ (((x) >> BIT_SHIFT_LS_CV_OFFSET_3_0) & BIT_MASK_LS_CV_OFFSET_3_0)
+#define BIT_SET_LS_CV_OFFSET_3_0(x, v) \
+ (BIT_CLEAR_LS_CV_OFFSET_3_0(x) | BIT_LS_CV_OFFSET_3_0(v))
+#define BIT_LS_EN_LC_CK40M BIT(11)
+#define BIT_LS__CV_MANUAL BIT(10)
+#define BIT_LS_PYPASS_PI BIT(9)
+#define BIT_MBIASE BIT(4)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ANAPAR_MAC_4 (Offset 0x1028) */
+#define BIT_LS_TIE_MID_MODE BIT(28)
-/* 2 REG_FE3IMR (Offset 0x1128) */
+#define BIT_SHIFT_LS_SYNC_CYCLE_1_0 26
+#define BIT_MASK_LS_SYNC_CYCLE_1_0 0x3
+#define BIT_LS_SYNC_CYCLE_1_0(x) \
+ (((x) & BIT_MASK_LS_SYNC_CYCLE_1_0) << BIT_SHIFT_LS_SYNC_CYCLE_1_0)
+#define BITS_LS_SYNC_CYCLE_1_0 \
+ (BIT_MASK_LS_SYNC_CYCLE_1_0 << BIT_SHIFT_LS_SYNC_CYCLE_1_0)
+#define BIT_CLEAR_LS_SYNC_CYCLE_1_0(x) ((x) & (~BITS_LS_SYNC_CYCLE_1_0))
+#define BIT_GET_LS_SYNC_CYCLE_1_0(x) \
+ (((x) >> BIT_SHIFT_LS_SYNC_CYCLE_1_0) & BIT_MASK_LS_SYNC_CYCLE_1_0)
+#define BIT_SET_LS_SYNC_CYCLE_1_0(x, v) \
+ (BIT_CLEAR_LS_SYNC_CYCLE_1_0(x) | BIT_LS_SYNC_CYCLE_1_0(v))
-#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT__EN BIT(28)
+#define BIT_LS_SDM_ORDER BIT(25)
+#define BIT_LS_RST_LC_CAL BIT(14)
+#define BIT_LS_RSTB BIT(13)
+#define BIT_LS_POW_LC_CAL_PREP BIT(11)
+
+#define BIT_SHIFT_LCK_XTAL_DIVISOR_1_0 0
+#define BIT_MASK_LCK_XTAL_DIVISOR_1_0 0x3
+#define BIT_LCK_XTAL_DIVISOR_1_0(x) \
+ (((x) & BIT_MASK_LCK_XTAL_DIVISOR_1_0) \
+ << BIT_SHIFT_LCK_XTAL_DIVISOR_1_0)
+#define BITS_LCK_XTAL_DIVISOR_1_0 \
+ (BIT_MASK_LCK_XTAL_DIVISOR_1_0 << BIT_SHIFT_LCK_XTAL_DIVISOR_1_0)
+#define BIT_CLEAR_LCK_XTAL_DIVISOR_1_0(x) ((x) & (~BITS_LCK_XTAL_DIVISOR_1_0))
+#define BIT_GET_LCK_XTAL_DIVISOR_1_0(x) \
+ (((x) >> BIT_SHIFT_LCK_XTAL_DIVISOR_1_0) & \
+ BIT_MASK_LCK_XTAL_DIVISOR_1_0)
+#define BIT_SET_LCK_XTAL_DIVISOR_1_0(x, v) \
+ (BIT_CLEAR_LCK_XTAL_DIVISOR_1_0(x) | BIT_LCK_XTAL_DIVISOR_1_0(v))
+
+/* 2 REG_ANAPAR_MAC_5 (Offset 0x102C) */
+
+#define BIT_SHIFT_LS_XTAL_SEL_3_0 0
+#define BIT_MASK_LS_XTAL_SEL_3_0 0xf
+#define BIT_LS_XTAL_SEL_3_0(x) \
+ (((x) & BIT_MASK_LS_XTAL_SEL_3_0) << BIT_SHIFT_LS_XTAL_SEL_3_0)
+#define BITS_LS_XTAL_SEL_3_0 \
+ (BIT_MASK_LS_XTAL_SEL_3_0 << BIT_SHIFT_LS_XTAL_SEL_3_0)
+#define BIT_CLEAR_LS_XTAL_SEL_3_0(x) ((x) & (~BITS_LS_XTAL_SEL_3_0))
+#define BIT_GET_LS_XTAL_SEL_3_0(x) \
+ (((x) >> BIT_SHIFT_LS_XTAL_SEL_3_0) & BIT_MASK_LS_XTAL_SEL_3_0)
+#define BIT_SET_LS_XTAL_SEL_3_0(x, v) \
+ (BIT_CLEAR_LS_XTAL_SEL_3_0(x) | BIT_LS_XTAL_SEL_3_0(v))
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_SYS_CFG4 (Offset 0x1034) */
+#define BIT_EF_CSER_1 BIT(26)
+#define BIT_SW_PG_EN_1 BIT(10)
-/* 2 REG_FE3IMR (Offset 0x1128) */
+#endif
-#define BIT_FS_BCNDMA4_INT_EN BIT(27)
-#define BIT_FS_BCNDMA3_INT_EN BIT(26)
-#define BIT_FS_BCNDMA2_INT_EN BIT(25)
-#define BIT_FS_BCNDMA1_INT_EN BIT(24)
-#define BIT_FS_BCNDMA0_MB7_INT_EN BIT(23)
-#define BIT_FS_BCNDMA0_MB6_INT_EN BIT(22)
-#define BIT_FS_BCNDMA0_MB5_INT_EN BIT(21)
-#define BIT_FS_BCNDMA0_MB4_INT_EN BIT(20)
-#define BIT_FS_BCNDMA0_MB3_INT_EN BIT(19)
-#define BIT_FS_BCNDMA0_MB2_INT_EN BIT(18)
-#define BIT_FS_BCNDMA0_MB1_INT_EN BIT(17)
-#define BIT_FS_BCNDMA0_INT_EN BIT(16)
-#define BIT_FS_MTI_BCNIVLEAR_INT__EN BIT(15)
-#define BIT_FS_BCNERLY4_INT_EN BIT(11)
-#define BIT_FS_BCNERLY3_INT_EN BIT(10)
-#define BIT_FS_BCNERLY2_INT_EN BIT(9)
-#define BIT_FS_BCNERLY1_INT_EN BIT(8)
-#define BIT_FS_BCNERLY0_MB7INT_EN BIT(7)
-#define BIT_FS_BCNERLY0_MB6INT_EN BIT(6)
-#define BIT_FS_BCNERLY0_MB5INT_EN BIT(5)
-#define BIT_FS_BCNERLY0_MB4INT_EN BIT(4)
-#define BIT_FS_BCNERLY0_MB3INT_EN BIT(3)
-#define BIT_FS_BCNERLY0_MB2INT_EN BIT(2)
-#define BIT_FS_BCNERLY0_MB1INT_EN BIT(1)
-#define BIT_FS_BCNERLY0_INT_EN BIT(0)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */
+#define BIT_XTAL_DRV_RF1_0 BIT(31)
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8822C_SUPPORT)
-/* 2 REG_FE3ISR (Offset 0x112C) */
+/* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */
-#define BIT_FS_BCNELY4_AGGR_INT BIT(31)
+#define BIT_XTAL_SC_LPS BIT(31)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */
+#define BIT_XTAL_GATED_RF1N BIT(30)
+#define BIT_XTAL_GATED_RF1P BIT(29)
+#define BIT_XTAL_GM_SEP_V2 BIT(28)
-/* 2 REG_FE3ISR (Offset 0x112C) */
+#define BIT_SHIFT_XTAL_LDO_1_0 26
+#define BIT_MASK_XTAL_LDO_1_0 0x3
+#define BIT_XTAL_LDO_1_0(x) \
+ (((x) & BIT_MASK_XTAL_LDO_1_0) << BIT_SHIFT_XTAL_LDO_1_0)
+#define BITS_XTAL_LDO_1_0 (BIT_MASK_XTAL_LDO_1_0 << BIT_SHIFT_XTAL_LDO_1_0)
+#define BIT_CLEAR_XTAL_LDO_1_0(x) ((x) & (~BITS_XTAL_LDO_1_0))
+#define BIT_GET_XTAL_LDO_1_0(x) \
+ (((x) >> BIT_SHIFT_XTAL_LDO_1_0) & BIT_MASK_XTAL_LDO_1_0)
+#define BIT_SET_XTAL_LDO_1_0(x, v) \
+ (BIT_CLEAR_XTAL_LDO_1_0(x) | BIT_XTAL_LDO_1_0(v))
-#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT BIT(31)
+#define BIT_XQSEL_V1 BIT(25)
+#define BIT_GATED_XTAL_OK0 BIT(24)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */
+#define BIT_SHIFT_XTAL_SC_INIT 24
+#define BIT_MASK_XTAL_SC_INIT 0x7f
+#define BIT_XTAL_SC_INIT(x) \
+ (((x) & BIT_MASK_XTAL_SC_INIT) << BIT_SHIFT_XTAL_SC_INIT)
+#define BITS_XTAL_SC_INIT (BIT_MASK_XTAL_SC_INIT << BIT_SHIFT_XTAL_SC_INIT)
+#define BIT_CLEAR_XTAL_SC_INIT(x) ((x) & (~BITS_XTAL_SC_INIT))
+#define BIT_GET_XTAL_SC_INIT(x) \
+ (((x) >> BIT_SHIFT_XTAL_SC_INIT) & BIT_MASK_XTAL_SC_INIT)
+#define BIT_SET_XTAL_SC_INIT(x, v) \
+ (BIT_CLEAR_XTAL_SC_INIT(x) | BIT_XTAL_SC_INIT(v))
-/* 2 REG_FE3ISR (Offset 0x112C) */
+#endif
-#define BIT_FS_BCNELY3_AGGR_INT BIT(30)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */
+#define BIT_SHIFT_XTAL_SC_XO_6_0 17
+#define BIT_MASK_XTAL_SC_XO_6_0 0x7f
+#define BIT_XTAL_SC_XO_6_0(x) \
+ (((x) & BIT_MASK_XTAL_SC_XO_6_0) << BIT_SHIFT_XTAL_SC_XO_6_0)
+#define BITS_XTAL_SC_XO_6_0 \
+ (BIT_MASK_XTAL_SC_XO_6_0 << BIT_SHIFT_XTAL_SC_XO_6_0)
+#define BIT_CLEAR_XTAL_SC_XO_6_0(x) ((x) & (~BITS_XTAL_SC_XO_6_0))
+#define BIT_GET_XTAL_SC_XO_6_0(x) \
+ (((x) >> BIT_SHIFT_XTAL_SC_XO_6_0) & BIT_MASK_XTAL_SC_XO_6_0)
+#define BIT_SET_XTAL_SC_XO_6_0(x, v) \
+ (BIT_CLEAR_XTAL_SC_XO_6_0(x) | BIT_XTAL_SC_XO_6_0(v))
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8822C_SUPPORT)
-/* 2 REG_FE3ISR (Offset 0x112C) */
+/* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */
-#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT BIT(30)
+#define BIT_SHIFT_XTAL_SC_XO 17
+#define BIT_MASK_XTAL_SC_XO 0x7f
+#define BIT_XTAL_SC_XO(x) (((x) & BIT_MASK_XTAL_SC_XO) << BIT_SHIFT_XTAL_SC_XO)
+#define BITS_XTAL_SC_XO (BIT_MASK_XTAL_SC_XO << BIT_SHIFT_XTAL_SC_XO)
+#define BIT_CLEAR_XTAL_SC_XO(x) ((x) & (~BITS_XTAL_SC_XO))
+#define BIT_GET_XTAL_SC_XO(x) \
+ (((x) >> BIT_SHIFT_XTAL_SC_XO) & BIT_MASK_XTAL_SC_XO)
+#define BIT_SET_XTAL_SC_XO(x, v) (BIT_CLEAR_XTAL_SC_XO(x) | BIT_XTAL_SC_XO(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */
+#define BIT_SHIFT_XTAL_SC_XI_6_0 10
+#define BIT_MASK_XTAL_SC_XI_6_0 0x7f
+#define BIT_XTAL_SC_XI_6_0(x) \
+ (((x) & BIT_MASK_XTAL_SC_XI_6_0) << BIT_SHIFT_XTAL_SC_XI_6_0)
+#define BITS_XTAL_SC_XI_6_0 \
+ (BIT_MASK_XTAL_SC_XI_6_0 << BIT_SHIFT_XTAL_SC_XI_6_0)
+#define BIT_CLEAR_XTAL_SC_XI_6_0(x) ((x) & (~BITS_XTAL_SC_XI_6_0))
+#define BIT_GET_XTAL_SC_XI_6_0(x) \
+ (((x) >> BIT_SHIFT_XTAL_SC_XI_6_0) & BIT_MASK_XTAL_SC_XI_6_0)
+#define BIT_SET_XTAL_SC_XI_6_0(x, v) \
+ (BIT_CLEAR_XTAL_SC_XI_6_0(x) | BIT_XTAL_SC_XI_6_0(v))
-/* 2 REG_FE3ISR (Offset 0x112C) */
+#endif
-#define BIT_FS_BCNELY2_AGGR_INT BIT(29)
+#if (HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */
+#define BIT_SHIFT_XTAL_SC_XI 10
+#define BIT_MASK_XTAL_SC_XI 0x7f
+#define BIT_XTAL_SC_XI(x) (((x) & BIT_MASK_XTAL_SC_XI) << BIT_SHIFT_XTAL_SC_XI)
+#define BITS_XTAL_SC_XI (BIT_MASK_XTAL_SC_XI << BIT_SHIFT_XTAL_SC_XI)
+#define BIT_CLEAR_XTAL_SC_XI(x) ((x) & (~BITS_XTAL_SC_XI))
+#define BIT_GET_XTAL_SC_XI(x) \
+ (((x) >> BIT_SHIFT_XTAL_SC_XI) & BIT_MASK_XTAL_SC_XI)
+#define BIT_SET_XTAL_SC_XI(x, v) (BIT_CLEAR_XTAL_SC_XI(x) | BIT_XTAL_SC_XI(v))
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_FE3ISR (Offset 0x112C) */
+/* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */
-#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT BIT(29)
+#define BIT_SHIFT_XTAL_GMN_4_0 5
+#define BIT_MASK_XTAL_GMN_4_0 0x1f
+#define BIT_XTAL_GMN_4_0(x) \
+ (((x) & BIT_MASK_XTAL_GMN_4_0) << BIT_SHIFT_XTAL_GMN_4_0)
+#define BITS_XTAL_GMN_4_0 (BIT_MASK_XTAL_GMN_4_0 << BIT_SHIFT_XTAL_GMN_4_0)
+#define BIT_CLEAR_XTAL_GMN_4_0(x) ((x) & (~BITS_XTAL_GMN_4_0))
+#define BIT_GET_XTAL_GMN_4_0(x) \
+ (((x) >> BIT_SHIFT_XTAL_GMN_4_0) & BIT_MASK_XTAL_GMN_4_0)
+#define BIT_SET_XTAL_GMN_4_0(x, v) \
+ (BIT_CLEAR_XTAL_GMN_4_0(x) | BIT_XTAL_GMN_4_0(v))
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */
+#define BIT_SHIFT_XTAL_GMN_V3 5
+#define BIT_MASK_XTAL_GMN_V3 0x1f
+#define BIT_XTAL_GMN_V3(x) \
+ (((x) & BIT_MASK_XTAL_GMN_V3) << BIT_SHIFT_XTAL_GMN_V3)
+#define BITS_XTAL_GMN_V3 (BIT_MASK_XTAL_GMN_V3 << BIT_SHIFT_XTAL_GMN_V3)
+#define BIT_CLEAR_XTAL_GMN_V3(x) ((x) & (~BITS_XTAL_GMN_V3))
+#define BIT_GET_XTAL_GMN_V3(x) \
+ (((x) >> BIT_SHIFT_XTAL_GMN_V3) & BIT_MASK_XTAL_GMN_V3)
+#define BIT_SET_XTAL_GMN_V3(x, v) \
+ (BIT_CLEAR_XTAL_GMN_V3(x) | BIT_XTAL_GMN_V3(v))
-/* 2 REG_FE3ISR (Offset 0x112C) */
+#endif
-#define BIT_FS_BCNELY1_AGGR_INT BIT(28)
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */
+
+#define BIT_SHIFT_XTAL_GMP_4_0 0
+#define BIT_MASK_XTAL_GMP_4_0 0x1f
+#define BIT_XTAL_GMP_4_0(x) \
+ (((x) & BIT_MASK_XTAL_GMP_4_0) << BIT_SHIFT_XTAL_GMP_4_0)
+#define BITS_XTAL_GMP_4_0 (BIT_MASK_XTAL_GMP_4_0 << BIT_SHIFT_XTAL_GMP_4_0)
+#define BIT_CLEAR_XTAL_GMP_4_0(x) ((x) & (~BITS_XTAL_GMP_4_0))
+#define BIT_GET_XTAL_GMP_4_0(x) \
+ (((x) >> BIT_SHIFT_XTAL_GMP_4_0) & BIT_MASK_XTAL_GMP_4_0)
+#define BIT_SET_XTAL_GMP_4_0(x, v) \
+ (BIT_CLEAR_XTAL_GMP_4_0(x) | BIT_XTAL_GMP_4_0(v))
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ANAPAR_XTAL_0 (Offset 0x1040) */
+#define BIT_SHIFT_XTAL_GMP_V3 0
+#define BIT_MASK_XTAL_GMP_V3 0x1f
+#define BIT_XTAL_GMP_V3(x) \
+ (((x) & BIT_MASK_XTAL_GMP_V3) << BIT_SHIFT_XTAL_GMP_V3)
+#define BITS_XTAL_GMP_V3 (BIT_MASK_XTAL_GMP_V3 << BIT_SHIFT_XTAL_GMP_V3)
+#define BIT_CLEAR_XTAL_GMP_V3(x) ((x) & (~BITS_XTAL_GMP_V3))
+#define BIT_GET_XTAL_GMP_V3(x) \
+ (((x) >> BIT_SHIFT_XTAL_GMP_V3) & BIT_MASK_XTAL_GMP_V3)
+#define BIT_SET_XTAL_GMP_V3(x, v) \
+ (BIT_CLEAR_XTAL_GMP_V3(x) | BIT_XTAL_GMP_V3(v))
-/* 2 REG_FE3ISR (Offset 0x112C) */
+/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */
-#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT BIT(28)
+#define BIT_XTAL_SEL_TOK_V1 BIT(31)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */
+#define BIT_SHIFT_XTAL_LDO_OK_1_0 30
+#define BIT_MASK_XTAL_LDO_OK_1_0 0x3
+#define BIT_XTAL_LDO_OK_1_0(x) \
+ (((x) & BIT_MASK_XTAL_LDO_OK_1_0) << BIT_SHIFT_XTAL_LDO_OK_1_0)
+#define BITS_XTAL_LDO_OK_1_0 \
+ (BIT_MASK_XTAL_LDO_OK_1_0 << BIT_SHIFT_XTAL_LDO_OK_1_0)
+#define BIT_CLEAR_XTAL_LDO_OK_1_0(x) ((x) & (~BITS_XTAL_LDO_OK_1_0))
+#define BIT_GET_XTAL_LDO_OK_1_0(x) \
+ (((x) >> BIT_SHIFT_XTAL_LDO_OK_1_0) & BIT_MASK_XTAL_LDO_OK_1_0)
+#define BIT_SET_XTAL_LDO_OK_1_0(x, v) \
+ (BIT_CLEAR_XTAL_LDO_OK_1_0(x) | BIT_XTAL_LDO_OK_1_0(v))
-/* 2 REG_FE3ISR (Offset 0x112C) */
+#endif
-#define BIT_FS_BCNDMA4_INT BIT(27)
-#define BIT_FS_BCNDMA3_INT BIT(26)
-#define BIT_FS_BCNDMA2_INT BIT(25)
-#define BIT_FS_BCNDMA1_INT BIT(24)
-#define BIT_FS_BCNDMA0_MB7_INT BIT(23)
-#define BIT_FS_BCNDMA0_MB6_INT BIT(22)
-#define BIT_FS_BCNDMA0_MB5_INT BIT(21)
-#define BIT_FS_BCNDMA0_MB4_INT BIT(20)
-#define BIT_FS_BCNDMA0_MB3_INT BIT(19)
-#define BIT_FS_BCNDMA0_MB2_INT BIT(18)
-#define BIT_FS_BCNDMA0_MB1_INT BIT(17)
-#define BIT_FS_BCNDMA0_INT BIT(16)
-#define BIT_FS_MTI_BCNIVLEAR_INT BIT(15)
-#define BIT_FS_BCNERLY4_INT BIT(11)
-#define BIT_FS_BCNERLY3_INT BIT(10)
-#define BIT_FS_BCNERLY2_INT BIT(9)
-#define BIT_FS_BCNERLY1_INT BIT(8)
-#define BIT_FS_BCNERLY0_MB7INT BIT(7)
-#define BIT_FS_BCNERLY0_MB6INT BIT(6)
-#define BIT_FS_BCNERLY0_MB5INT BIT(5)
-#define BIT_FS_BCNERLY0_MB4INT BIT(4)
-#define BIT_FS_BCNERLY0_MB3INT BIT(3)
-#define BIT_FS_BCNERLY0_MB2INT BIT(2)
-#define BIT_FS_BCNERLY0_MB1INT BIT(1)
-#define BIT_FS_BCNERLY0_INT BIT(0)
+#if (HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */
+#define BIT_XTAL_DELAY_DIGI_V2 BIT(30)
+#define BIT_XTAL_DELAY_USB_V2 BIT(29)
+#define BIT_XTAL_DELAY_AFE_V2 BIT(28)
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_FE4IMR (Offset 0x1130) */
+/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */
-#define BIT_PORT4_PKTIN_INT_EN BIT(19)
+#define BIT_SHIFT_XTAL_XORES_SEL_2_0 27
+#define BIT_MASK_XTAL_XORES_SEL_2_0 0x7
+#define BIT_XTAL_XORES_SEL_2_0(x) \
+ (((x) & BIT_MASK_XTAL_XORES_SEL_2_0) << BIT_SHIFT_XTAL_XORES_SEL_2_0)
+#define BITS_XTAL_XORES_SEL_2_0 \
+ (BIT_MASK_XTAL_XORES_SEL_2_0 << BIT_SHIFT_XTAL_XORES_SEL_2_0)
+#define BIT_CLEAR_XTAL_XORES_SEL_2_0(x) ((x) & (~BITS_XTAL_XORES_SEL_2_0))
+#define BIT_GET_XTAL_XORES_SEL_2_0(x) \
+ (((x) >> BIT_SHIFT_XTAL_XORES_SEL_2_0) & BIT_MASK_XTAL_XORES_SEL_2_0)
+#define BIT_SET_XTAL_XORES_SEL_2_0(x, v) \
+ (BIT_CLEAR_XTAL_XORES_SEL_2_0(x) | BIT_XTAL_XORES_SEL_2_0(v))
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */
+#define BIT_SHIFT_XTAL_DRV_DIGI_V2 26
+#define BIT_MASK_XTAL_DRV_DIGI_V2 0x3
+#define BIT_XTAL_DRV_DIGI_V2(x) \
+ (((x) & BIT_MASK_XTAL_DRV_DIGI_V2) << BIT_SHIFT_XTAL_DRV_DIGI_V2)
+#define BITS_XTAL_DRV_DIGI_V2 \
+ (BIT_MASK_XTAL_DRV_DIGI_V2 << BIT_SHIFT_XTAL_DRV_DIGI_V2)
+#define BIT_CLEAR_XTAL_DRV_DIGI_V2(x) ((x) & (~BITS_XTAL_DRV_DIGI_V2))
+#define BIT_GET_XTAL_DRV_DIGI_V2(x) \
+ (((x) >> BIT_SHIFT_XTAL_DRV_DIGI_V2) & BIT_MASK_XTAL_DRV_DIGI_V2)
+#define BIT_SET_XTAL_DRV_DIGI_V2(x, v) \
+ (BIT_CLEAR_XTAL_DRV_DIGI_V2(x) | BIT_XTAL_DRV_DIGI_V2(v))
-/* 2 REG_FE4IMR (Offset 0x1130) */
+#endif
-#define BIT_FS_CLI3_TXPKTIN_INT_EN BIT(19)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */
+#define BIT_SHIFT_XTAL_AAC_PK_SEL_1_0 25
+#define BIT_MASK_XTAL_AAC_PK_SEL_1_0 0x3
+#define BIT_XTAL_AAC_PK_SEL_1_0(x) \
+ (((x) & BIT_MASK_XTAL_AAC_PK_SEL_1_0) << BIT_SHIFT_XTAL_AAC_PK_SEL_1_0)
+#define BITS_XTAL_AAC_PK_SEL_1_0 \
+ (BIT_MASK_XTAL_AAC_PK_SEL_1_0 << BIT_SHIFT_XTAL_AAC_PK_SEL_1_0)
+#define BIT_CLEAR_XTAL_AAC_PK_SEL_1_0(x) ((x) & (~BITS_XTAL_AAC_PK_SEL_1_0))
+#define BIT_GET_XTAL_AAC_PK_SEL_1_0(x) \
+ (((x) >> BIT_SHIFT_XTAL_AAC_PK_SEL_1_0) & BIT_MASK_XTAL_AAC_PK_SEL_1_0)
+#define BIT_SET_XTAL_AAC_PK_SEL_1_0(x, v) \
+ (BIT_CLEAR_XTAL_AAC_PK_SEL_1_0(x) | BIT_XTAL_AAC_PK_SEL_1_0(v))
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8822C_SUPPORT)
-/* 2 REG_FE4IMR (Offset 0x1130) */
+/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */
-#define BIT_PORT3_PKTIN_INT_EN BIT(18)
+#define BIT_EN_XTAL_DRV_LPS BIT(25)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */
+#define BIT_EN_XTAL_AAC_PKDET BIT(24)
-/* 2 REG_FE4IMR (Offset 0x1130) */
+#endif
-#define BIT_FS_CLI2_TXPKTIN_INT_EN BIT(18)
+#if (HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */
+#define BIT_EN_XTAL_DRV_DIGI_V2 BIT(24)
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_FE4IMR (Offset 0x1130) */
+/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */
-#define BIT_PORT2_PKTIN_INT_EN BIT(17)
+#define BIT_EN_XTAL_AAC_GM BIT(23)
+#define BIT_XTAL_LPMODE BIT(22)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */
-/* 2 REG_FE4IMR (Offset 0x1130) */
+#define BIT_SHIFT_XTAL_DRV_USB 22
+#define BIT_MASK_XTAL_DRV_USB 0x3
+#define BIT_XTAL_DRV_USB(x) \
+ (((x) & BIT_MASK_XTAL_DRV_USB) << BIT_SHIFT_XTAL_DRV_USB)
+#define BITS_XTAL_DRV_USB (BIT_MASK_XTAL_DRV_USB << BIT_SHIFT_XTAL_DRV_USB)
+#define BIT_CLEAR_XTAL_DRV_USB(x) ((x) & (~BITS_XTAL_DRV_USB))
+#define BIT_GET_XTAL_DRV_USB(x) \
+ (((x) >> BIT_SHIFT_XTAL_DRV_USB) & BIT_MASK_XTAL_DRV_USB)
+#define BIT_SET_XTAL_DRV_USB(x, v) \
+ (BIT_CLEAR_XTAL_DRV_USB(x) | BIT_XTAL_DRV_USB(v))
-#define BIT_FS_CLI1_TXPKTIN_INT_EN BIT(17)
+#define BIT_EN_XTAL_DRV_USB BIT(21)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */
+#define BIT_SHIFT_XTAL_SEL_TOK_2_0 19
+#define BIT_MASK_XTAL_SEL_TOK_2_0 0x7
+#define BIT_XTAL_SEL_TOK_2_0(x) \
+ (((x) & BIT_MASK_XTAL_SEL_TOK_2_0) << BIT_SHIFT_XTAL_SEL_TOK_2_0)
+#define BITS_XTAL_SEL_TOK_2_0 \
+ (BIT_MASK_XTAL_SEL_TOK_2_0 << BIT_SHIFT_XTAL_SEL_TOK_2_0)
+#define BIT_CLEAR_XTAL_SEL_TOK_2_0(x) ((x) & (~BITS_XTAL_SEL_TOK_2_0))
+#define BIT_GET_XTAL_SEL_TOK_2_0(x) \
+ (((x) >> BIT_SHIFT_XTAL_SEL_TOK_2_0) & BIT_MASK_XTAL_SEL_TOK_2_0)
+#define BIT_SET_XTAL_SEL_TOK_2_0(x, v) \
+ (BIT_CLEAR_XTAL_SEL_TOK_2_0(x) | BIT_XTAL_SEL_TOK_2_0(v))
-/* 2 REG_FE4IMR (Offset 0x1130) */
+#endif
-#define BIT_PORT1_PKTIN_INT_EN BIT(16)
+#if (HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */
+#define BIT_SHIFT_XTAL_DRV_AFE_V2 19
+#define BIT_MASK_XTAL_DRV_AFE_V2 0x3
+#define BIT_XTAL_DRV_AFE_V2(x) \
+ (((x) & BIT_MASK_XTAL_DRV_AFE_V2) << BIT_SHIFT_XTAL_DRV_AFE_V2)
+#define BITS_XTAL_DRV_AFE_V2 \
+ (BIT_MASK_XTAL_DRV_AFE_V2 << BIT_SHIFT_XTAL_DRV_AFE_V2)
+#define BIT_CLEAR_XTAL_DRV_AFE_V2(x) ((x) & (~BITS_XTAL_DRV_AFE_V2))
+#define BIT_GET_XTAL_DRV_AFE_V2(x) \
+ (((x) >> BIT_SHIFT_XTAL_DRV_AFE_V2) & BIT_MASK_XTAL_DRV_AFE_V2)
+#define BIT_SET_XTAL_DRV_AFE_V2(x, v) \
+ (BIT_CLEAR_XTAL_DRV_AFE_V2(x) | BIT_XTAL_DRV_AFE_V2(v))
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_FE4IMR (Offset 0x1130) */
+/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */
-#define BIT_FS_CLI0_TXPKTIN_INT_EN BIT(16)
+#define BIT_XQSEL_RF_AWAKE_V2 BIT(18)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */
+#define BIT_EN_XTAL_DRV_AFE BIT(18)
-/* 2 REG_FE4IMR (Offset 0x1130) */
+#endif
-#define BIT_PORT4_RXUCMD0_OK_INT_EN BIT(15)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */
+#define BIT_XQSEL_RF_INITIAL_V2 BIT(17)
+#define BIT_XTAL_DELAY_USB_V1 BIT(16)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8822C_SUPPORT)
-/* 2 REG_FE4IMR (Offset 0x1130) */
+/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */
-#define BIT_FS_CLI3_RX_UMD0_INT_EN BIT(15)
+#define BIT_SHIFT_XTAL_DRV_RF2_V2 16
+#define BIT_MASK_XTAL_DRV_RF2_V2 0x3
+#define BIT_XTAL_DRV_RF2_V2(x) \
+ (((x) & BIT_MASK_XTAL_DRV_RF2_V2) << BIT_SHIFT_XTAL_DRV_RF2_V2)
+#define BITS_XTAL_DRV_RF2_V2 \
+ (BIT_MASK_XTAL_DRV_RF2_V2 << BIT_SHIFT_XTAL_DRV_RF2_V2)
+#define BIT_CLEAR_XTAL_DRV_RF2_V2(x) ((x) & (~BITS_XTAL_DRV_RF2_V2))
+#define BIT_GET_XTAL_DRV_RF2_V2(x) \
+ (((x) >> BIT_SHIFT_XTAL_DRV_RF2_V2) & BIT_MASK_XTAL_DRV_RF2_V2)
+#define BIT_SET_XTAL_DRV_RF2_V2(x, v) \
+ (BIT_CLEAR_XTAL_DRV_RF2_V2(x) | BIT_XTAL_DRV_RF2_V2(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */
+#define BIT_XTAL_DELAY_DIGI_V1 BIT(15)
-/* 2 REG_FE4IMR (Offset 0x1130) */
+#endif
-#define BIT_PORT4_RXUCMD1_OK_INT_EN BIT(14)
+#if (HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */
+#define BIT_EN_XTAL_DRV_RF2 BIT(15)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_FE4IMR (Offset 0x1130) */
+/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */
-#define BIT_FS_CLI3_RX_UMD1_INT_EN BIT(14)
+#define BIT_XTAL_DELAY_AFE_V1 BIT(14)
+#define BIT_XTAL_DRV_RF_LATCH_V3 BIT(13)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */
+#define BIT_EN_XTAL_DRV_RF1 BIT(12)
-/* 2 REG_FE4IMR (Offset 0x1130) */
+#endif
-#define BIT_PORT4_RXBCMD0_OK_INT_EN BIT(13)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */
+#define BIT_SHIFT_XTAL_DRV_DIGI_1_0 11
+#define BIT_MASK_XTAL_DRV_DIGI_1_0 0x3
+#define BIT_XTAL_DRV_DIGI_1_0(x) \
+ (((x) & BIT_MASK_XTAL_DRV_DIGI_1_0) << BIT_SHIFT_XTAL_DRV_DIGI_1_0)
+#define BITS_XTAL_DRV_DIGI_1_0 \
+ (BIT_MASK_XTAL_DRV_DIGI_1_0 << BIT_SHIFT_XTAL_DRV_DIGI_1_0)
+#define BIT_CLEAR_XTAL_DRV_DIGI_1_0(x) ((x) & (~BITS_XTAL_DRV_DIGI_1_0))
+#define BIT_GET_XTAL_DRV_DIGI_1_0(x) \
+ (((x) >> BIT_SHIFT_XTAL_DRV_DIGI_1_0) & BIT_MASK_XTAL_DRV_DIGI_1_0)
+#define BIT_SET_XTAL_DRV_DIGI_1_0(x, v) \
+ (BIT_CLEAR_XTAL_DRV_DIGI_1_0(x) | BIT_XTAL_DRV_DIGI_1_0(v))
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8822C_SUPPORT)
-/* 2 REG_FE4IMR (Offset 0x1130) */
+/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */
-#define BIT_FS_CLI3_RX_BMD0_INT_EN BIT(13)
+#define BIT_XTAL_DRV_RF_LATCH_V4 BIT(11)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */
+#define BIT_XTAL_GATED_DIGIN BIT(10)
-/* 2 REG_FE4IMR (Offset 0x1130) */
+#endif
-#define BIT_PORT4_RXBCMD1_OK_INT_EN BIT(12)
+#if (HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */
+#define BIT_XTAL_GM_SEP_V3 BIT(10)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_FE4IMR (Offset 0x1130) */
+/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */
-#define BIT_FS_CLI3_RX_BMD1_INT_EN BIT(12)
+#define BIT_XTAL_GATED_DIGIP BIT(9)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */
+#define BIT_XQSEL_RF_AWAKE_V3 BIT(9)
+#define BIT_XQSEL_RF_INITIAL_V3 BIT(8)
-/* 2 REG_FE4IMR (Offset 0x1130) */
+#endif
-#define BIT_PORT3_RXUCMD0_OK_INT_EN BIT(11)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */
+#define BIT_SHIFT_XTAL_DRV_USB_1_0 7
+#define BIT_MASK_XTAL_DRV_USB_1_0 0x3
+#define BIT_XTAL_DRV_USB_1_0(x) \
+ (((x) & BIT_MASK_XTAL_DRV_USB_1_0) << BIT_SHIFT_XTAL_DRV_USB_1_0)
+#define BITS_XTAL_DRV_USB_1_0 \
+ (BIT_MASK_XTAL_DRV_USB_1_0 << BIT_SHIFT_XTAL_DRV_USB_1_0)
+#define BIT_CLEAR_XTAL_DRV_USB_1_0(x) ((x) & (~BITS_XTAL_DRV_USB_1_0))
+#define BIT_GET_XTAL_DRV_USB_1_0(x) \
+ (((x) >> BIT_SHIFT_XTAL_DRV_USB_1_0) & BIT_MASK_XTAL_DRV_USB_1_0)
+#define BIT_SET_XTAL_DRV_USB_1_0(x, v) \
+ (BIT_CLEAR_XTAL_DRV_USB_1_0(x) | BIT_XTAL_DRV_USB_1_0(v))
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8822C_SUPPORT)
-/* 2 REG_FE4IMR (Offset 0x1130) */
+/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */
-#define BIT_FS_CLI2_RX_UMD0_INT_EN BIT(11)
+#define BIT_XQSEL_V2 BIT(7)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */
+#define BIT_XTAL_GATED_USBN BIT(6)
-/* 2 REG_FE4IMR (Offset 0x1130) */
+#endif
-#define BIT_PORT3_RXUCMD1_OK_INT_EN BIT(10)
+#if (HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */
+
+#define BIT_GATED_XTAL_OK0_V2 BIT(6)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */
+#define BIT_XTAL_GATED_USBP BIT(5)
-/* 2 REG_FE4IMR (Offset 0x1130) */
+#define BIT_SHIFT_XTAL_DRV_AFE_1_0 3
+#define BIT_MASK_XTAL_DRV_AFE_1_0 0x3
+#define BIT_XTAL_DRV_AFE_1_0(x) \
+ (((x) & BIT_MASK_XTAL_DRV_AFE_1_0) << BIT_SHIFT_XTAL_DRV_AFE_1_0)
+#define BITS_XTAL_DRV_AFE_1_0 \
+ (BIT_MASK_XTAL_DRV_AFE_1_0 << BIT_SHIFT_XTAL_DRV_AFE_1_0)
+#define BIT_CLEAR_XTAL_DRV_AFE_1_0(x) ((x) & (~BITS_XTAL_DRV_AFE_1_0))
+#define BIT_GET_XTAL_DRV_AFE_1_0(x) \
+ (((x) >> BIT_SHIFT_XTAL_DRV_AFE_1_0) & BIT_MASK_XTAL_DRV_AFE_1_0)
+#define BIT_SET_XTAL_DRV_AFE_1_0(x, v) \
+ (BIT_CLEAR_XTAL_DRV_AFE_1_0(x) | BIT_XTAL_DRV_AFE_1_0(v))
-#define BIT_FS_CLI2_RX_UMD1_INT_EN BIT(10)
+#define BIT_XTAL_GATED_AFEN BIT(2)
+#define BIT_XTAL_GATED_AFEP BIT(1)
+#define BIT_XTAL_DRV_RF1_1 BIT(0)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_ANAPAR_XTAL_1 (Offset 0x1044) */
+#define BIT_SHIFT_XTAL_SC_LPS_V2 0
+#define BIT_MASK_XTAL_SC_LPS_V2 0x3f
+#define BIT_XTAL_SC_LPS_V2(x) \
+ (((x) & BIT_MASK_XTAL_SC_LPS_V2) << BIT_SHIFT_XTAL_SC_LPS_V2)
+#define BITS_XTAL_SC_LPS_V2 \
+ (BIT_MASK_XTAL_SC_LPS_V2 << BIT_SHIFT_XTAL_SC_LPS_V2)
+#define BIT_CLEAR_XTAL_SC_LPS_V2(x) ((x) & (~BITS_XTAL_SC_LPS_V2))
+#define BIT_GET_XTAL_SC_LPS_V2(x) \
+ (((x) >> BIT_SHIFT_XTAL_SC_LPS_V2) & BIT_MASK_XTAL_SC_LPS_V2)
+#define BIT_SET_XTAL_SC_LPS_V2(x, v) \
+ (BIT_CLEAR_XTAL_SC_LPS_V2(x) | BIT_XTAL_SC_LPS_V2(v))
-/* 2 REG_FE4IMR (Offset 0x1130) */
+/* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */
-#define BIT_PORT3_RXBCMD0_OK_INT_EN BIT(9)
+#define BIT_XTAL_AAC_CAP BIT(31)
-#endif
+#define BIT_SHIFT_XTAL_PDSW 29
+#define BIT_MASK_XTAL_PDSW 0x3
+#define BIT_XTAL_PDSW(x) (((x) & BIT_MASK_XTAL_PDSW) << BIT_SHIFT_XTAL_PDSW)
+#define BITS_XTAL_PDSW (BIT_MASK_XTAL_PDSW << BIT_SHIFT_XTAL_PDSW)
+#define BIT_CLEAR_XTAL_PDSW(x) ((x) & (~BITS_XTAL_PDSW))
+#define BIT_GET_XTAL_PDSW(x) (((x) >> BIT_SHIFT_XTAL_PDSW) & BIT_MASK_XTAL_PDSW)
+#define BIT_SET_XTAL_PDSW(x, v) (BIT_CLEAR_XTAL_PDSW(x) | BIT_XTAL_PDSW(v))
+#define BIT_SHIFT_XTAL_LPS_BUF_VB 27
+#define BIT_MASK_XTAL_LPS_BUF_VB 0x3
+#define BIT_XTAL_LPS_BUF_VB(x) \
+ (((x) & BIT_MASK_XTAL_LPS_BUF_VB) << BIT_SHIFT_XTAL_LPS_BUF_VB)
+#define BITS_XTAL_LPS_BUF_VB \
+ (BIT_MASK_XTAL_LPS_BUF_VB << BIT_SHIFT_XTAL_LPS_BUF_VB)
+#define BIT_CLEAR_XTAL_LPS_BUF_VB(x) ((x) & (~BITS_XTAL_LPS_BUF_VB))
+#define BIT_GET_XTAL_LPS_BUF_VB(x) \
+ (((x) >> BIT_SHIFT_XTAL_LPS_BUF_VB) & BIT_MASK_XTAL_LPS_BUF_VB)
+#define BIT_SET_XTAL_LPS_BUF_VB(x, v) \
+ (BIT_CLEAR_XTAL_LPS_BUF_VB(x) | BIT_XTAL_LPS_BUF_VB(v))
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#define BIT_XTAL_PDCK_MANU BIT(26)
+#define BIT_XTAL_PDCK_OK_MANU BIT(25)
+#define BIT_SHIFT_XTAL_VREF_SEL 20
+#define BIT_MASK_XTAL_VREF_SEL 0x1f
+#define BIT_XTAL_VREF_SEL(x) \
+ (((x) & BIT_MASK_XTAL_VREF_SEL) << BIT_SHIFT_XTAL_VREF_SEL)
+#define BITS_XTAL_VREF_SEL (BIT_MASK_XTAL_VREF_SEL << BIT_SHIFT_XTAL_VREF_SEL)
+#define BIT_CLEAR_XTAL_VREF_SEL(x) ((x) & (~BITS_XTAL_VREF_SEL))
+#define BIT_GET_XTAL_VREF_SEL(x) \
+ (((x) >> BIT_SHIFT_XTAL_VREF_SEL) & BIT_MASK_XTAL_VREF_SEL)
+#define BIT_SET_XTAL_VREF_SEL(x, v) \
+ (BIT_CLEAR_XTAL_VREF_SEL(x) | BIT_XTAL_VREF_SEL(v))
-/* 2 REG_FE4IMR (Offset 0x1130) */
+#define BIT_EN_XTAL_PDCK_VREF BIT(19)
+#define BIT_XTAL_SEL_PWR_V1 BIT(18)
+#define BIT_XTAL_LPS_DIVISOR BIT(17)
+#define BIT_XTAL_CKDIGI_SEL BIT(16)
+#define BIT_EN_XTAL_LPS_CLK BIT(15)
+#define BIT_EN_XTAL_SCHMITT BIT(14)
+#define BIT_XTAL_PK_SEL_OFFSET BIT(13)
-#define BIT_FS_CLI2_RX_BMD0_INT_EN BIT(9)
+#define BIT_SHIFT_XTAL_MANU_PK_SEL 11
+#define BIT_MASK_XTAL_MANU_PK_SEL 0x3
+#define BIT_XTAL_MANU_PK_SEL(x) \
+ (((x) & BIT_MASK_XTAL_MANU_PK_SEL) << BIT_SHIFT_XTAL_MANU_PK_SEL)
+#define BITS_XTAL_MANU_PK_SEL \
+ (BIT_MASK_XTAL_MANU_PK_SEL << BIT_SHIFT_XTAL_MANU_PK_SEL)
+#define BIT_CLEAR_XTAL_MANU_PK_SEL(x) ((x) & (~BITS_XTAL_MANU_PK_SEL))
+#define BIT_GET_XTAL_MANU_PK_SEL(x) \
+ (((x) >> BIT_SHIFT_XTAL_MANU_PK_SEL) & BIT_MASK_XTAL_MANU_PK_SEL)
+#define BIT_SET_XTAL_MANU_PK_SEL(x, v) \
+ (BIT_CLEAR_XTAL_MANU_PK_SEL(x) | BIT_XTAL_MANU_PK_SEL(v))
-#endif
+#define BIT_XTAL_AACK_PK_MANU BIT(10)
+#define BIT_EN_XTAL_AAC_PKDET_V1 BIT(9)
+#define BIT_EN_XTAL_AAC_GM_V1 BIT(8)
+#define BIT_XTAL_LDO_OPVB_SEL BIT(7)
+#define BIT_SHIFT_XTAL_DUMMY_V1 7
+#define BIT_MASK_XTAL_DUMMY_V1 0x3f
+#define BIT_XTAL_DUMMY_V1(x) \
+ (((x) & BIT_MASK_XTAL_DUMMY_V1) << BIT_SHIFT_XTAL_DUMMY_V1)
+#define BITS_XTAL_DUMMY_V1 (BIT_MASK_XTAL_DUMMY_V1 << BIT_SHIFT_XTAL_DUMMY_V1)
+#define BIT_CLEAR_XTAL_DUMMY_V1(x) ((x) & (~BITS_XTAL_DUMMY_V1))
+#define BIT_GET_XTAL_DUMMY_V1(x) \
+ (((x) >> BIT_SHIFT_XTAL_DUMMY_V1) & BIT_MASK_XTAL_DUMMY_V1)
+#define BIT_SET_XTAL_DUMMY_V1(x, v) \
+ (BIT_CLEAR_XTAL_DUMMY_V1(x) | BIT_XTAL_DUMMY_V1(v))
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_FE4IMR (Offset 0x1130) */
+/* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */
-#define BIT_PORT3_RXBCMD1_OK_INT_EN BIT(8)
+#define BIT_XTAL_DRV_RF2_LATCH BIT(6)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */
+#define BIT_XTAL_LDO_NC BIT(6)
+#define BIT_XTAL_EN_LNBUF BIT(6)
+#define BIT_XTAL__AAC_TIE_MID BIT(5)
-/* 2 REG_FE4IMR (Offset 0x1130) */
+#endif
-#define BIT_FS_CLI2_RX_BMD1_INT_EN BIT(8)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */
+#define BIT_SHIFT_XTAL_DRV_RF2_1_0 4
+#define BIT_MASK_XTAL_DRV_RF2_1_0 0x3
+#define BIT_XTAL_DRV_RF2_1_0(x) \
+ (((x) & BIT_MASK_XTAL_DRV_RF2_1_0) << BIT_SHIFT_XTAL_DRV_RF2_1_0)
+#define BITS_XTAL_DRV_RF2_1_0 \
+ (BIT_MASK_XTAL_DRV_RF2_1_0 << BIT_SHIFT_XTAL_DRV_RF2_1_0)
+#define BIT_CLEAR_XTAL_DRV_RF2_1_0(x) ((x) & (~BITS_XTAL_DRV_RF2_1_0))
+#define BIT_GET_XTAL_DRV_RF2_1_0(x) \
+ (((x) >> BIT_SHIFT_XTAL_DRV_RF2_1_0) & BIT_MASK_XTAL_DRV_RF2_1_0)
+#define BIT_SET_XTAL_DRV_RF2_1_0(x, v) \
+ (BIT_CLEAR_XTAL_DRV_RF2_1_0(x) | BIT_XTAL_DRV_RF2_1_0(v))
-#if (HALMAC_8197F_SUPPORT)
+#define BIT_XTAL_GATED_RF2N BIT(3)
+#endif
-/* 2 REG_FE4IMR (Offset 0x1130) */
+#if (HALMAC_8822C_SUPPORT)
-#define BIT_PORT2_RXUCMD0_OK_INT_EN BIT(7)
+/* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */
-#endif
+#define BIT_SHIFT_XTAL_LDO_VREF_V2 3
+#define BIT_MASK_XTAL_LDO_VREF_V2 0x7
+#define BIT_XTAL_LDO_VREF_V2(x) \
+ (((x) & BIT_MASK_XTAL_LDO_VREF_V2) << BIT_SHIFT_XTAL_LDO_VREF_V2)
+#define BITS_XTAL_LDO_VREF_V2 \
+ (BIT_MASK_XTAL_LDO_VREF_V2 << BIT_SHIFT_XTAL_LDO_VREF_V2)
+#define BIT_CLEAR_XTAL_LDO_VREF_V2(x) ((x) & (~BITS_XTAL_LDO_VREF_V2))
+#define BIT_GET_XTAL_LDO_VREF_V2(x) \
+ (((x) >> BIT_SHIFT_XTAL_LDO_VREF_V2) & BIT_MASK_XTAL_LDO_VREF_V2)
+#define BIT_SET_XTAL_LDO_VREF_V2(x, v) \
+ (BIT_CLEAR_XTAL_LDO_VREF_V2(x) | BIT_XTAL_LDO_VREF_V2(v))
+#define BIT_SHIFT_XTAL_AAC_OPCUR 3
+#define BIT_MASK_XTAL_AAC_OPCUR 0x3
+#define BIT_XTAL_AAC_OPCUR(x) \
+ (((x) & BIT_MASK_XTAL_AAC_OPCUR) << BIT_SHIFT_XTAL_AAC_OPCUR)
+#define BITS_XTAL_AAC_OPCUR \
+ (BIT_MASK_XTAL_AAC_OPCUR << BIT_SHIFT_XTAL_AAC_OPCUR)
+#define BIT_CLEAR_XTAL_AAC_OPCUR(x) ((x) & (~BITS_XTAL_AAC_OPCUR))
+#define BIT_GET_XTAL_AAC_OPCUR(x) \
+ (((x) >> BIT_SHIFT_XTAL_AAC_OPCUR) & BIT_MASK_XTAL_AAC_OPCUR)
+#define BIT_SET_XTAL_AAC_OPCUR(x, v) \
+ (BIT_CLEAR_XTAL_AAC_OPCUR(x) | BIT_XTAL_AAC_OPCUR(v))
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_FE4IMR (Offset 0x1130) */
+/* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */
-#define BIT_FS_CLI1_RX_UMD0_INT_EN BIT(7)
+#define BIT_XTAL_GATED_RF2P BIT(2)
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */
+#define BIT_XTAL_LPMODE_V1 BIT(2)
-/* 2 REG_FE4IMR (Offset 0x1130) */
+#endif
-#define BIT_PORT2_RXUCMD1_OK_INT_EN BIT(6)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */
+#define BIT_XTAL_LDO_DI BIT(1)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8822C_SUPPORT)
-/* 2 REG_FE4IMR (Offset 0x1130) */
+/* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */
-#define BIT_FS_CLI1_RX_UMD1_INT_EN BIT(6)
+#define BIT_SHIFT_XTAL_AAC_IOFFSET 1
+#define BIT_MASK_XTAL_AAC_IOFFSET 0x3
+#define BIT_XTAL_AAC_IOFFSET(x) \
+ (((x) & BIT_MASK_XTAL_AAC_IOFFSET) << BIT_SHIFT_XTAL_AAC_IOFFSET)
+#define BITS_XTAL_AAC_IOFFSET \
+ (BIT_MASK_XTAL_AAC_IOFFSET << BIT_SHIFT_XTAL_AAC_IOFFSET)
+#define BIT_CLEAR_XTAL_AAC_IOFFSET(x) ((x) & (~BITS_XTAL_AAC_IOFFSET))
+#define BIT_GET_XTAL_AAC_IOFFSET(x) \
+ (((x) >> BIT_SHIFT_XTAL_AAC_IOFFSET) & BIT_MASK_XTAL_AAC_IOFFSET)
+#define BIT_SET_XTAL_AAC_IOFFSET(x, v) \
+ (BIT_CLEAR_XTAL_AAC_IOFFSET(x) | BIT_XTAL_AAC_IOFFSET(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */
+#define BIT_XTAL_SEL_PWR BIT(0)
-/* 2 REG_FE4IMR (Offset 0x1130) */
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_2 (Offset 0x1048) */
-#define BIT_PORT2_RXBCMD0_OK_INT_EN BIT(5)
+#define BIT_SHIFT_XTAL_SEL_TOK_V3 0
+#define BIT_MASK_XTAL_SEL_TOK_V3 0x3
+#define BIT_XTAL_SEL_TOK_V3(x) \
+ (((x) & BIT_MASK_XTAL_SEL_TOK_V3) << BIT_SHIFT_XTAL_SEL_TOK_V3)
+#define BITS_XTAL_SEL_TOK_V3 \
+ (BIT_MASK_XTAL_SEL_TOK_V3 << BIT_SHIFT_XTAL_SEL_TOK_V3)
+#define BIT_CLEAR_XTAL_SEL_TOK_V3(x) ((x) & (~BITS_XTAL_SEL_TOK_V3))
+#define BIT_GET_XTAL_SEL_TOK_V3(x) \
+ (((x) >> BIT_SHIFT_XTAL_SEL_TOK_V3) & BIT_MASK_XTAL_SEL_TOK_V3)
+#define BIT_SET_XTAL_SEL_TOK_V3(x, v) \
+ (BIT_CLEAR_XTAL_SEL_TOK_V3(x) | BIT_XTAL_SEL_TOK_V3(v))
+
+#define BIT_XTAL_AAC_CAP_V1 BIT(0)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ANAPAR_XTAL_AAC (Offset 0x104C) */
+#define BIT_SHIFT_GM_MANUAL_4_0 21
+#define BIT_MASK_GM_MANUAL_4_0 0x1f
+#define BIT_GM_MANUAL_4_0(x) \
+ (((x) & BIT_MASK_GM_MANUAL_4_0) << BIT_SHIFT_GM_MANUAL_4_0)
+#define BITS_GM_MANUAL_4_0 (BIT_MASK_GM_MANUAL_4_0 << BIT_SHIFT_GM_MANUAL_4_0)
+#define BIT_CLEAR_GM_MANUAL_4_0(x) ((x) & (~BITS_GM_MANUAL_4_0))
+#define BIT_GET_GM_MANUAL_4_0(x) \
+ (((x) >> BIT_SHIFT_GM_MANUAL_4_0) & BIT_MASK_GM_MANUAL_4_0)
+#define BIT_SET_GM_MANUAL_4_0(x, v) \
+ (BIT_CLEAR_GM_MANUAL_4_0(x) | BIT_GM_MANUAL_4_0(v))
-/* 2 REG_FE4IMR (Offset 0x1130) */
+#define BIT_SHIFT_GM_STUP_4_0 16
+#define BIT_MASK_GM_STUP_4_0 0x1f
+#define BIT_GM_STUP_4_0(x) \
+ (((x) & BIT_MASK_GM_STUP_4_0) << BIT_SHIFT_GM_STUP_4_0)
+#define BITS_GM_STUP_4_0 (BIT_MASK_GM_STUP_4_0 << BIT_SHIFT_GM_STUP_4_0)
+#define BIT_CLEAR_GM_STUP_4_0(x) ((x) & (~BITS_GM_STUP_4_0))
+#define BIT_GET_GM_STUP_4_0(x) \
+ (((x) >> BIT_SHIFT_GM_STUP_4_0) & BIT_MASK_GM_STUP_4_0)
+#define BIT_SET_GM_STUP_4_0(x, v) \
+ (BIT_CLEAR_GM_STUP_4_0(x) | BIT_GM_STUP_4_0(v))
-#define BIT_FS_CLI1_RX_BMD0_INT_EN BIT(5)
+#define BIT_SHIFT_XTAL_CK_SET_2_0 13
+#define BIT_MASK_XTAL_CK_SET_2_0 0x7
+#define BIT_XTAL_CK_SET_2_0(x) \
+ (((x) & BIT_MASK_XTAL_CK_SET_2_0) << BIT_SHIFT_XTAL_CK_SET_2_0)
+#define BITS_XTAL_CK_SET_2_0 \
+ (BIT_MASK_XTAL_CK_SET_2_0 << BIT_SHIFT_XTAL_CK_SET_2_0)
+#define BIT_CLEAR_XTAL_CK_SET_2_0(x) ((x) & (~BITS_XTAL_CK_SET_2_0))
+#define BIT_GET_XTAL_CK_SET_2_0(x) \
+ (((x) >> BIT_SHIFT_XTAL_CK_SET_2_0) & BIT_MASK_XTAL_CK_SET_2_0)
+#define BIT_SET_XTAL_CK_SET_2_0(x, v) \
+ (BIT_CLEAR_XTAL_CK_SET_2_0(x) | BIT_XTAL_CK_SET_2_0(v))
+
+#define BIT_SHIFT_GM_INIT_4_0 8
+#define BIT_MASK_GM_INIT_4_0 0x1f
+#define BIT_GM_INIT_4_0(x) \
+ (((x) & BIT_MASK_GM_INIT_4_0) << BIT_SHIFT_GM_INIT_4_0)
+#define BITS_GM_INIT_4_0 (BIT_MASK_GM_INIT_4_0 << BIT_SHIFT_GM_INIT_4_0)
+#define BIT_CLEAR_GM_INIT_4_0(x) ((x) & (~BITS_GM_INIT_4_0))
+#define BIT_GET_GM_INIT_4_0(x) \
+ (((x) >> BIT_SHIFT_GM_INIT_4_0) & BIT_MASK_GM_INIT_4_0)
+#define BIT_SET_GM_INIT_4_0(x, v) \
+ (BIT_CLEAR_GM_INIT_4_0(x) | BIT_GM_INIT_4_0(v))
+
+#define BIT_SHIFT_XAAC_GM_OFFSET_4_0 2
+#define BIT_MASK_XAAC_GM_OFFSET_4_0 0x1f
+#define BIT_XAAC_GM_OFFSET_4_0(x) \
+ (((x) & BIT_MASK_XAAC_GM_OFFSET_4_0) << BIT_SHIFT_XAAC_GM_OFFSET_4_0)
+#define BITS_XAAC_GM_OFFSET_4_0 \
+ (BIT_MASK_XAAC_GM_OFFSET_4_0 << BIT_SHIFT_XAAC_GM_OFFSET_4_0)
+#define BIT_CLEAR_XAAC_GM_OFFSET_4_0(x) ((x) & (~BITS_XAAC_GM_OFFSET_4_0))
+#define BIT_GET_XAAC_GM_OFFSET_4_0(x) \
+ (((x) >> BIT_SHIFT_XAAC_GM_OFFSET_4_0) & BIT_MASK_XAAC_GM_OFFSET_4_0)
+#define BIT_SET_XAAC_GM_OFFSET_4_0(x, v) \
+ (BIT_CLEAR_XAAC_GM_OFFSET_4_0(x) | BIT_XAAC_GM_OFFSET_4_0(v))
+
+/* 2 REG_ANAPAR_XTAL_R_ONLY (Offset 0x1050) */
+
+#define BIT_XTAL_PKDET_OUT BIT(6)
+
+#define BIT_SHIFT_XTAL_GM_AAC_4_0 1
+#define BIT_MASK_XTAL_GM_AAC_4_0 0x1f
+#define BIT_XTAL_GM_AAC_4_0(x) \
+ (((x) & BIT_MASK_XTAL_GM_AAC_4_0) << BIT_SHIFT_XTAL_GM_AAC_4_0)
+#define BITS_XTAL_GM_AAC_4_0 \
+ (BIT_MASK_XTAL_GM_AAC_4_0 << BIT_SHIFT_XTAL_GM_AAC_4_0)
+#define BIT_CLEAR_XTAL_GM_AAC_4_0(x) ((x) & (~BITS_XTAL_GM_AAC_4_0))
+#define BIT_GET_XTAL_GM_AAC_4_0(x) \
+ (((x) >> BIT_SHIFT_XTAL_GM_AAC_4_0) & BIT_MASK_XTAL_GM_AAC_4_0)
+#define BIT_SET_XTAL_GM_AAC_4_0(x, v) \
+ (BIT_CLEAR_XTAL_GM_AAC_4_0(x) | BIT_XTAL_GM_AAC_4_0(v))
+
+#define BIT_XAAC_READY BIT(0)
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_AACK_0 (Offset 0x1054) */
+
+#define BIT_XAAC_LPOW BIT(31)
+
+#define BIT_SHIFT_AAC_MODE 29
+#define BIT_MASK_AAC_MODE 0x3
+#define BIT_AAC_MODE(x) (((x) & BIT_MASK_AAC_MODE) << BIT_SHIFT_AAC_MODE)
+#define BITS_AAC_MODE (BIT_MASK_AAC_MODE << BIT_SHIFT_AAC_MODE)
+#define BIT_CLEAR_AAC_MODE(x) ((x) & (~BITS_AAC_MODE))
+#define BIT_GET_AAC_MODE(x) (((x) >> BIT_SHIFT_AAC_MODE) & BIT_MASK_AAC_MODE)
+#define BIT_SET_AAC_MODE(x, v) (BIT_CLEAR_AAC_MODE(x) | BIT_AAC_MODE(v))
+
+#define BIT_SHIFT_GM_MANUAL 21
+#define BIT_MASK_GM_MANUAL 0x1f
+#define BIT_GM_MANUAL(x) (((x) & BIT_MASK_GM_MANUAL) << BIT_SHIFT_GM_MANUAL)
+#define BITS_GM_MANUAL (BIT_MASK_GM_MANUAL << BIT_SHIFT_GM_MANUAL)
+#define BIT_CLEAR_GM_MANUAL(x) ((x) & (~BITS_GM_MANUAL))
+#define BIT_GET_GM_MANUAL(x) (((x) >> BIT_SHIFT_GM_MANUAL) & BIT_MASK_GM_MANUAL)
+#define BIT_SET_GM_MANUAL(x, v) (BIT_CLEAR_GM_MANUAL(x) | BIT_GM_MANUAL(v))
+
+#define BIT_SHIFT_XTAL_LDO_LPS 21
+#define BIT_MASK_XTAL_LDO_LPS 0x7
+#define BIT_XTAL_LDO_LPS(x) \
+ (((x) & BIT_MASK_XTAL_LDO_LPS) << BIT_SHIFT_XTAL_LDO_LPS)
+#define BITS_XTAL_LDO_LPS (BIT_MASK_XTAL_LDO_LPS << BIT_SHIFT_XTAL_LDO_LPS)
+#define BIT_CLEAR_XTAL_LDO_LPS(x) ((x) & (~BITS_XTAL_LDO_LPS))
+#define BIT_GET_XTAL_LDO_LPS(x) \
+ (((x) >> BIT_SHIFT_XTAL_LDO_LPS) & BIT_MASK_XTAL_LDO_LPS)
+#define BIT_SET_XTAL_LDO_LPS(x, v) \
+ (BIT_CLEAR_XTAL_LDO_LPS(x) | BIT_XTAL_LDO_LPS(v))
+
+#define BIT_SHIFT_GM_STUP 16
+#define BIT_MASK_GM_STUP 0x1f
+#define BIT_GM_STUP(x) (((x) & BIT_MASK_GM_STUP) << BIT_SHIFT_GM_STUP)
+#define BITS_GM_STUP (BIT_MASK_GM_STUP << BIT_SHIFT_GM_STUP)
+#define BIT_CLEAR_GM_STUP(x) ((x) & (~BITS_GM_STUP))
+#define BIT_GET_GM_STUP(x) (((x) >> BIT_SHIFT_GM_STUP) & BIT_MASK_GM_STUP)
+#define BIT_SET_GM_STUP(x, v) (BIT_CLEAR_GM_STUP(x) | BIT_GM_STUP(v))
+
+#define BIT_SHIFT_XTAL_WAIT_CYC 15
+#define BIT_MASK_XTAL_WAIT_CYC 0x3f
+#define BIT_XTAL_WAIT_CYC(x) \
+ (((x) & BIT_MASK_XTAL_WAIT_CYC) << BIT_SHIFT_XTAL_WAIT_CYC)
+#define BITS_XTAL_WAIT_CYC (BIT_MASK_XTAL_WAIT_CYC << BIT_SHIFT_XTAL_WAIT_CYC)
+#define BIT_CLEAR_XTAL_WAIT_CYC(x) ((x) & (~BITS_XTAL_WAIT_CYC))
+#define BIT_GET_XTAL_WAIT_CYC(x) \
+ (((x) >> BIT_SHIFT_XTAL_WAIT_CYC) & BIT_MASK_XTAL_WAIT_CYC)
+#define BIT_SET_XTAL_WAIT_CYC(x, v) \
+ (BIT_CLEAR_XTAL_WAIT_CYC(x) | BIT_XTAL_WAIT_CYC(v))
+
+#define BIT_SHIFT_XTAL_CK_SET 13
+#define BIT_MASK_XTAL_CK_SET 0x7
+#define BIT_XTAL_CK_SET(x) \
+ (((x) & BIT_MASK_XTAL_CK_SET) << BIT_SHIFT_XTAL_CK_SET)
+#define BITS_XTAL_CK_SET (BIT_MASK_XTAL_CK_SET << BIT_SHIFT_XTAL_CK_SET)
+#define BIT_CLEAR_XTAL_CK_SET(x) ((x) & (~BITS_XTAL_CK_SET))
+#define BIT_GET_XTAL_CK_SET(x) \
+ (((x) >> BIT_SHIFT_XTAL_CK_SET) & BIT_MASK_XTAL_CK_SET)
+#define BIT_SET_XTAL_CK_SET(x, v) \
+ (BIT_CLEAR_XTAL_CK_SET(x) | BIT_XTAL_CK_SET(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_CPHY_LDO (Offset 0x1054) */
+
+#define BIT_SHIFT_CPHY_LDO_PD 12
+#define BIT_MASK_CPHY_LDO_PD 0x3
+#define BIT_CPHY_LDO_PD(x) \
+ (((x) & BIT_MASK_CPHY_LDO_PD) << BIT_SHIFT_CPHY_LDO_PD)
+#define BITS_CPHY_LDO_PD (BIT_MASK_CPHY_LDO_PD << BIT_SHIFT_CPHY_LDO_PD)
+#define BIT_CLEAR_CPHY_LDO_PD(x) ((x) & (~BITS_CPHY_LDO_PD))
+#define BIT_GET_CPHY_LDO_PD(x) \
+ (((x) >> BIT_SHIFT_CPHY_LDO_PD) & BIT_MASK_CPHY_LDO_PD)
+#define BIT_SET_CPHY_LDO_PD(x, v) \
+ (BIT_CLEAR_CPHY_LDO_PD(x) | BIT_CPHY_LDO_PD(v))
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_ANAPAR_XTAL_AACK_0 (Offset 0x1054) */
+
+#define BIT_SHIFT_XTAL_LDO_OK 12
+#define BIT_MASK_XTAL_LDO_OK 0x7
+#define BIT_XTAL_LDO_OK(x) \
+ (((x) & BIT_MASK_XTAL_LDO_OK) << BIT_SHIFT_XTAL_LDO_OK)
+#define BITS_XTAL_LDO_OK (BIT_MASK_XTAL_LDO_OK << BIT_SHIFT_XTAL_LDO_OK)
+#define BIT_CLEAR_XTAL_LDO_OK(x) ((x) & (~BITS_XTAL_LDO_OK))
+#define BIT_GET_XTAL_LDO_OK(x) \
+ (((x) >> BIT_SHIFT_XTAL_LDO_OK) & BIT_MASK_XTAL_LDO_OK)
+#define BIT_SET_XTAL_LDO_OK(x, v) \
+ (BIT_CLEAR_XTAL_LDO_OK(x) | BIT_XTAL_LDO_OK(v))
+#define BIT_XTAL_MD_LPOW BIT(11)
-/* 2 REG_FE4IMR (Offset 0x1130) */
+#endif
-#define BIT_PORT2_RXBCMD1_OK_INT_EN BIT(4)
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_CPHY_LDO (Offset 0x1054) */
+
+#define BIT_SHIFT_CPHY_LDO_SR 10
+#define BIT_MASK_CPHY_LDO_SR 0x3
+#define BIT_CPHY_LDO_SR(x) \
+ (((x) & BIT_MASK_CPHY_LDO_SR) << BIT_SHIFT_CPHY_LDO_SR)
+#define BITS_CPHY_LDO_SR (BIT_MASK_CPHY_LDO_SR << BIT_SHIFT_CPHY_LDO_SR)
+#define BIT_CLEAR_CPHY_LDO_SR(x) ((x) & (~BITS_CPHY_LDO_SR))
+#define BIT_GET_CPHY_LDO_SR(x) \
+ (((x) >> BIT_SHIFT_CPHY_LDO_SR) & BIT_MASK_CPHY_LDO_SR)
+#define BIT_SET_CPHY_LDO_SR(x, v) \
+ (BIT_CLEAR_CPHY_LDO_SR(x) | BIT_CPHY_LDO_SR(v))
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_AACK_0 (Offset 0x1054) */
+
+#define BIT_SHIFT_XTAL_OV_RATIO 9
+#define BIT_MASK_XTAL_OV_RATIO 0x3
+#define BIT_XTAL_OV_RATIO(x) \
+ (((x) & BIT_MASK_XTAL_OV_RATIO) << BIT_SHIFT_XTAL_OV_RATIO)
+#define BITS_XTAL_OV_RATIO (BIT_MASK_XTAL_OV_RATIO << BIT_SHIFT_XTAL_OV_RATIO)
+#define BIT_CLEAR_XTAL_OV_RATIO(x) ((x) & (~BITS_XTAL_OV_RATIO))
+#define BIT_GET_XTAL_OV_RATIO(x) \
+ (((x) >> BIT_SHIFT_XTAL_OV_RATIO) & BIT_MASK_XTAL_OV_RATIO)
+#define BIT_SET_XTAL_OV_RATIO(x, v) \
+ (BIT_CLEAR_XTAL_OV_RATIO(x) | BIT_XTAL_OV_RATIO(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_CPHY_LDO (Offset 0x1054) */
+#define BIT_SHIFT_CPHY_LDO_TUNEREF 8
+#define BIT_MASK_CPHY_LDO_TUNEREF 0x3
+#define BIT_CPHY_LDO_TUNEREF(x) \
+ (((x) & BIT_MASK_CPHY_LDO_TUNEREF) << BIT_SHIFT_CPHY_LDO_TUNEREF)
+#define BITS_CPHY_LDO_TUNEREF \
+ (BIT_MASK_CPHY_LDO_TUNEREF << BIT_SHIFT_CPHY_LDO_TUNEREF)
+#define BIT_CLEAR_CPHY_LDO_TUNEREF(x) ((x) & (~BITS_CPHY_LDO_TUNEREF))
+#define BIT_GET_CPHY_LDO_TUNEREF(x) \
+ (((x) >> BIT_SHIFT_CPHY_LDO_TUNEREF) & BIT_MASK_CPHY_LDO_TUNEREF)
+#define BIT_SET_CPHY_LDO_TUNEREF(x, v) \
+ (BIT_CLEAR_CPHY_LDO_TUNEREF(x) | BIT_CPHY_LDO_TUNEREF(v))
-/* 2 REG_FE4IMR (Offset 0x1130) */
+#endif
-#define BIT_FS_CLI1_RX_BMD1_INT_EN BIT(4)
+#if (HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_ANAPAR_XTAL_AACK_0 (Offset 0x1054) */
+#define BIT_SHIFT_GM_INIT 8
+#define BIT_MASK_GM_INIT 0x1f
+#define BIT_GM_INIT(x) (((x) & BIT_MASK_GM_INIT) << BIT_SHIFT_GM_INIT)
+#define BITS_GM_INIT (BIT_MASK_GM_INIT << BIT_SHIFT_GM_INIT)
+#define BIT_CLEAR_GM_INIT(x) ((x) & (~BITS_GM_INIT))
+#define BIT_GET_GM_INIT(x) (((x) >> BIT_SHIFT_GM_INIT) & BIT_MASK_GM_INIT)
+#define BIT_SET_GM_INIT(x, v) (BIT_CLEAR_GM_INIT(x) | BIT_GM_INIT(v))
-#if (HALMAC_8197F_SUPPORT)
+#define BIT_SHIFT_XTAL_OV_UNIT 6
+#define BIT_MASK_XTAL_OV_UNIT 0x7
+#define BIT_XTAL_OV_UNIT(x) \
+ (((x) & BIT_MASK_XTAL_OV_UNIT) << BIT_SHIFT_XTAL_OV_UNIT)
+#define BITS_XTAL_OV_UNIT (BIT_MASK_XTAL_OV_UNIT << BIT_SHIFT_XTAL_OV_UNIT)
+#define BIT_CLEAR_XTAL_OV_UNIT(x) ((x) & (~BITS_XTAL_OV_UNIT))
+#define BIT_GET_XTAL_OV_UNIT(x) \
+ (((x) >> BIT_SHIFT_XTAL_OV_UNIT) & BIT_MASK_XTAL_OV_UNIT)
+#define BIT_SET_XTAL_OV_UNIT(x, v) \
+ (BIT_CLEAR_XTAL_OV_UNIT(x) | BIT_XTAL_OV_UNIT(v))
+
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_FE4IMR (Offset 0x1130) */
+/* 2 REG_CPHY_LDO (Offset 0x1054) */
-#define BIT_PORT1_RXUCMD0_OK_INT_EN BIT(3)
+#define BIT_SHIFT_CPHY_LDO_TUNE_VO 5
+#define BIT_MASK_CPHY_LDO_TUNE_VO 0x7
+#define BIT_CPHY_LDO_TUNE_VO(x) \
+ (((x) & BIT_MASK_CPHY_LDO_TUNE_VO) << BIT_SHIFT_CPHY_LDO_TUNE_VO)
+#define BITS_CPHY_LDO_TUNE_VO \
+ (BIT_MASK_CPHY_LDO_TUNE_VO << BIT_SHIFT_CPHY_LDO_TUNE_VO)
+#define BIT_CLEAR_CPHY_LDO_TUNE_VO(x) ((x) & (~BITS_CPHY_LDO_TUNE_VO))
+#define BIT_GET_CPHY_LDO_TUNE_VO(x) \
+ (((x) >> BIT_SHIFT_CPHY_LDO_TUNE_VO) & BIT_MASK_CPHY_LDO_TUNE_VO)
+#define BIT_SET_CPHY_LDO_TUNE_VO(x, v) \
+ (BIT_CLEAR_CPHY_LDO_TUNE_VO(x) | BIT_CPHY_LDO_TUNE_VO(v))
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ANAPAR_XTAL_AACK_0 (Offset 0x1054) */
+#define BIT_SHIFT_XTAL_MODE_MANUAL 4
+#define BIT_MASK_XTAL_MODE_MANUAL 0x3
+#define BIT_XTAL_MODE_MANUAL(x) \
+ (((x) & BIT_MASK_XTAL_MODE_MANUAL) << BIT_SHIFT_XTAL_MODE_MANUAL)
+#define BITS_XTAL_MODE_MANUAL \
+ (BIT_MASK_XTAL_MODE_MANUAL << BIT_SHIFT_XTAL_MODE_MANUAL)
+#define BIT_CLEAR_XTAL_MODE_MANUAL(x) ((x) & (~BITS_XTAL_MODE_MANUAL))
+#define BIT_GET_XTAL_MODE_MANUAL(x) \
+ (((x) >> BIT_SHIFT_XTAL_MODE_MANUAL) & BIT_MASK_XTAL_MODE_MANUAL)
+#define BIT_SET_XTAL_MODE_MANUAL(x, v) \
+ (BIT_CLEAR_XTAL_MODE_MANUAL(x) | BIT_XTAL_MODE_MANUAL(v))
-/* 2 REG_FE4IMR (Offset 0x1130) */
+#define BIT_SHIFT_PK_END_AR 3
+#define BIT_MASK_PK_END_AR 0x3
+#define BIT_PK_END_AR(x) (((x) & BIT_MASK_PK_END_AR) << BIT_SHIFT_PK_END_AR)
+#define BITS_PK_END_AR (BIT_MASK_PK_END_AR << BIT_SHIFT_PK_END_AR)
+#define BIT_CLEAR_PK_END_AR(x) ((x) & (~BITS_PK_END_AR))
+#define BIT_GET_PK_END_AR(x) (((x) >> BIT_SHIFT_PK_END_AR) & BIT_MASK_PK_END_AR)
+#define BIT_SET_PK_END_AR(x, v) (BIT_CLEAR_PK_END_AR(x) | BIT_PK_END_AR(v))
-#define BIT_FS_CLI0_RX_UMD0_INT_EN BIT(3)
+#define BIT_XTAL_MANU_SEL BIT(3)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_CPHY_LDO (Offset 0x1054) */
+#define BIT_SHIFT_CPHY_LDO_OCP_VTH 2
+#define BIT_MASK_CPHY_LDO_OCP_VTH 0x7
+#define BIT_CPHY_LDO_OCP_VTH(x) \
+ (((x) & BIT_MASK_CPHY_LDO_OCP_VTH) << BIT_SHIFT_CPHY_LDO_OCP_VTH)
+#define BITS_CPHY_LDO_OCP_VTH \
+ (BIT_MASK_CPHY_LDO_OCP_VTH << BIT_SHIFT_CPHY_LDO_OCP_VTH)
+#define BIT_CLEAR_CPHY_LDO_OCP_VTH(x) ((x) & (~BITS_CPHY_LDO_OCP_VTH))
+#define BIT_GET_CPHY_LDO_OCP_VTH(x) \
+ (((x) >> BIT_SHIFT_CPHY_LDO_OCP_VTH) & BIT_MASK_CPHY_LDO_OCP_VTH)
+#define BIT_SET_CPHY_LDO_OCP_VTH(x, v) \
+ (BIT_CLEAR_CPHY_LDO_OCP_VTH(x) | BIT_CPHY_LDO_OCP_VTH(v))
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_AACK_0 (Offset 0x1054) */
+
+#define BIT_SHIFT_XAAC_GM_OFFSET 2
+#define BIT_MASK_XAAC_GM_OFFSET 0x1f
+#define BIT_XAAC_GM_OFFSET(x) \
+ (((x) & BIT_MASK_XAAC_GM_OFFSET) << BIT_SHIFT_XAAC_GM_OFFSET)
+#define BITS_XAAC_GM_OFFSET \
+ (BIT_MASK_XAAC_GM_OFFSET << BIT_SHIFT_XAAC_GM_OFFSET)
+#define BIT_CLEAR_XAAC_GM_OFFSET(x) ((x) & (~BITS_XAAC_GM_OFFSET))
+#define BIT_GET_XAAC_GM_OFFSET(x) \
+ (((x) >> BIT_SHIFT_XAAC_GM_OFFSET) & BIT_MASK_XAAC_GM_OFFSET)
+#define BIT_SET_XAAC_GM_OFFSET(x, v) \
+ (BIT_CLEAR_XAAC_GM_OFFSET(x) | BIT_XAAC_GM_OFFSET(v))
+
+#define BIT_SHIFT_PK_START_AR 1
+#define BIT_MASK_PK_START_AR 0x3
+#define BIT_PK_START_AR(x) \
+ (((x) & BIT_MASK_PK_START_AR) << BIT_SHIFT_PK_START_AR)
+#define BITS_PK_START_AR (BIT_MASK_PK_START_AR << BIT_SHIFT_PK_START_AR)
+#define BIT_CLEAR_PK_START_AR(x) ((x) & (~BITS_PK_START_AR))
+#define BIT_GET_PK_START_AR(x) \
+ (((x) >> BIT_SHIFT_PK_START_AR) & BIT_MASK_PK_START_AR)
+#define BIT_SET_PK_START_AR(x, v) \
+ (BIT_CLEAR_PK_START_AR(x) | BIT_PK_START_AR(v))
+
+#define BIT_XTAL_MODE BIT(1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_CPHY_LDO (Offset 0x1054) */
+
+#define BIT_SHIFT_VREF_LDO_OK 0
+#define BIT_MASK_VREF_LDO_OK 0x3
+#define BIT_VREF_LDO_OK(x) \
+ (((x) & BIT_MASK_VREF_LDO_OK) << BIT_SHIFT_VREF_LDO_OK)
+#define BITS_VREF_LDO_OK (BIT_MASK_VREF_LDO_OK << BIT_SHIFT_VREF_LDO_OK)
+#define BIT_CLEAR_VREF_LDO_OK(x) ((x) & (~BITS_VREF_LDO_OK))
+#define BIT_GET_VREF_LDO_OK(x) \
+ (((x) >> BIT_SHIFT_VREF_LDO_OK) & BIT_MASK_VREF_LDO_OK)
+#define BIT_SET_VREF_LDO_OK(x, v) \
+ (BIT_CLEAR_VREF_LDO_OK(x) | BIT_VREF_LDO_OK(v))
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+/* 2 REG_ANAPAR_XTAL_AACK_0 (Offset 0x1054) */
+
+#define BIT_XAAC_LUT_MANUAL_EN BIT(0)
+#define BIT_RESET_N_DECODER BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_CPHY_BG (Offset 0x1058) */
+
+#define BIT_TXBCN_OK_PORT4 BIT(31)
+#define BIT_ATIMEND_PORT4 BIT(31)
+#define BIT_TXBCN_OK_PORT3 BIT(30)
+#define BIT_ATIMEND_PORT3 BIT(30)
+#define BIT_TXBCN_OK_PORT2 BIT(29)
+#define BIT_ATIMEND_PORT2 BIT(29)
+#define BIT_TXBCN_OK_PORT1 BIT(28)
+#define BIT_ATIMEND_PORT1 BIT(28)
+#define BIT_TXBCN15OK BIT(23)
+#define BIT_BCNDMAINT15 BIT(23)
+#define BIT_ATIMEND15 BIT(23)
+#define BIT_TXBCN14OK BIT(22)
+#define BIT_BCNDMAINT14 BIT(22)
+#define BIT_ATIMEND14 BIT(22)
+#define BIT_TXBCN13OK BIT(21)
+#define BIT_BCNDMAINT13 BIT(21)
+#define BIT_ATIMEND13 BIT(21)
+#define BIT_TXBCN12OK BIT(20)
+#define BIT_BCNDMAINT12 BIT(20)
+#define BIT_ATIMEND12 BIT(20)
+#define BIT_TXBCN11OK BIT(19)
+#define BIT_BCNDMAINT11 BIT(19)
+#define BIT_ATIMEND11 BIT(19)
+#define BIT_TXBCN10OK BIT(18)
+#define BIT_BCNDMAINT10 BIT(18)
+#define BIT_ATIMEND10 BIT(18)
+#define BIT_TXBCN9OK BIT(17)
+#define BIT_BCNDMAINT9 BIT(17)
+#define BIT_ATIMEND9 BIT(17)
+#define BIT_TXBCN8OK BIT(16)
+#define BIT_BCNDMAINT8 BIT(16)
+#define BIT_ATIMEND8 BIT(16)
+#define BIT_BCNDERR_PORT4 BIT(15)
+#define BIT_BCNDERR_PORT3 BIT(14)
+#define BIT_BCNDERR_PORT2 BIT(13)
+#define BIT_BCNDERR_PORT1 BIT(12)
+#define BIT_TXBCN15ERR BIT(7)
+#define BIT_BCNDERR15 BIT(7)
+#define BIT_TXBCN14ERR BIT(6)
+#define BIT_BCNDERR14 BIT(6)
+#define BIT_TXBCN13ERR BIT(5)
+#define BIT_BCNDERR13 BIT(5)
+#define BIT_PS_TIMER_EARLY_INT_5 BIT(5)
+#define BIT_TXBCN12ERR BIT(4)
+#define BIT_BCNDERR12 BIT(4)
+#define BIT_PS_TIMER_EARLY_INT_4 BIT(4)
+#define BIT_TXBCN11ERR BIT(3)
+#define BIT_BCNDERR11 BIT(3)
+#define BIT_PS_TIMER_EARLY_INT_3 BIT(3)
+#define BIT_TXBCN10ERR BIT(2)
+#define BIT_BCNDERR10 BIT(2)
+#define BIT_PS_TIMER_EARLY_INT_2 BIT(2)
+#define BIT_TXBCN9ERR BIT(1)
+#define BIT_BCNDERR9 BIT(1)
+#define BIT_PS_TIMER_EARLY_INT_1 BIT(1)
+
+#define BIT_SHIFT_BG 0
+#define BIT_MASK_BG 0x7
+#define BIT_BG(x) (((x) & BIT_MASK_BG) << BIT_SHIFT_BG)
+#define BITS_BG (BIT_MASK_BG << BIT_SHIFT_BG)
+#define BIT_CLEAR_BG(x) ((x) & (~BITS_BG))
+#define BIT_GET_BG(x) (((x) >> BIT_SHIFT_BG) & BIT_MASK_BG)
+#define BIT_SET_BG(x, v) (BIT_CLEAR_BG(x) | BIT_BG(v))
+
+#define BIT_TXBCN8ERR BIT(0)
+#define BIT_BCNDERR8 BIT(0)
+#define BIT_PS_TIMER_EARLY_INT_0 BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-/* 2 REG_FE4IMR (Offset 0x1130) */
+/* 2 REG_SYS_CFG5 (Offset 0x1070) */
-#define BIT_PORT1_RXUCMD1_OK_INT_EN BIT(2)
+#define BIT_LPS_STATUS BIT(3)
+#define BIT_HCI_TXDMA_BUSY BIT(2)
+#define BIT_HCI_TXDMA_ALLOW BIT(1)
+#define BIT_FW_CTRL_HCI_TXDMA_EN BIT(0)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */
+#define BIT_SCH_PHY_TXOP_SIFS_INT BIT(23)
-/* 2 REG_FE4IMR (Offset 0x1130) */
+#endif
-#define BIT_FS_DMEM1_WPTR_UPDATE_INT_EN BIT(2)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */
+#define BIT_WDT_AUTO_MODE BIT(22)
+#define BIT_WDT_PLATFORM_EN BIT(21)
+#define BIT_WDT_CPU_EN BIT(20)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-/* 2 REG_FE4IMR (Offset 0x1130) */
+/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */
-#define BIT_FS_CLI0_RX_UMD1_INT_EN BIT(2)
+#define BIT_WDT_OPT_IOWRAPPER BIT(19)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */
+#define BIT_ANA_PORT_IDLE BIT(18)
+#define BIT_MAC_PORT_IDLE BIT(17)
+#define BIT_WL_PLATFORM_RST BIT(16)
+#define BIT_WL_SECURITY_CLK BIT(15)
-/* 2 REG_FE4IMR (Offset 0x1130) */
+#endif
-#define BIT_PORT1_RXBCMD0_OK_INT_EN BIT(1)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */
+#define BIT_DDMA_EN BIT(8)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_FE4IMR (Offset 0x1130) */
+/* 2 REG_CPU_DMEM_CON (Offset 0x1080) */
-#define BIT_FS_CLI0_RX_BMD0_INT_EN BIT(1)
+#define BIT_SHIFT_CPU_DMEM_CON 0
+#define BIT_MASK_CPU_DMEM_CON 0xff
+#define BIT_CPU_DMEM_CON(x) \
+ (((x) & BIT_MASK_CPU_DMEM_CON) << BIT_SHIFT_CPU_DMEM_CON)
+#define BITS_CPU_DMEM_CON (BIT_MASK_CPU_DMEM_CON << BIT_SHIFT_CPU_DMEM_CON)
+#define BIT_CLEAR_CPU_DMEM_CON(x) ((x) & (~BITS_CPU_DMEM_CON))
+#define BIT_GET_CPU_DMEM_CON(x) \
+ (((x) >> BIT_SHIFT_CPU_DMEM_CON) & BIT_MASK_CPU_DMEM_CON)
+#define BIT_SET_CPU_DMEM_CON(x, v) \
+ (BIT_CLEAR_CPU_DMEM_CON(x) | BIT_CPU_DMEM_CON(v))
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_BOOT_REASON (Offset 0x1088) */
+#define BIT_SHIFT_BOOT_REASON_V1 0
+#define BIT_MASK_BOOT_REASON_V1 0x7
+#define BIT_BOOT_REASON_V1(x) \
+ (((x) & BIT_MASK_BOOT_REASON_V1) << BIT_SHIFT_BOOT_REASON_V1)
+#define BITS_BOOT_REASON_V1 \
+ (BIT_MASK_BOOT_REASON_V1 << BIT_SHIFT_BOOT_REASON_V1)
+#define BIT_CLEAR_BOOT_REASON_V1(x) ((x) & (~BITS_BOOT_REASON_V1))
+#define BIT_GET_BOOT_REASON_V1(x) \
+ (((x) >> BIT_SHIFT_BOOT_REASON_V1) & BIT_MASK_BOOT_REASON_V1)
+#define BIT_SET_BOOT_REASON_V1(x, v) \
+ (BIT_CLEAR_BOOT_REASON_V1(x) | BIT_BOOT_REASON_V1(v))
-/* 2 REG_FE4IMR (Offset 0x1130) */
+#endif
-#define BIT_PORT1_RXBCMD1_OK_INT_EN BIT(0)
+#if (HALMAC_8198F_SUPPORT)
-#endif
+/* 2 REG_HIMR4 (Offset 0x1090) */
+#define BIT_ATIM_END_INT16_MSK BIT(32)
+#define BIT_ATIM_END_INT15_MSK BIT(31)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_FE4IMR (Offset 0x1130) */
+/* 2 REG_DATA_CPU_CTL0 (Offset 0x1090) */
-#define BIT_FS_CLI0_RX_BMD1_INT_EN BIT(0)
+#define BIT_DATA_FW_READY BIT(31)
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_HIMR4 (Offset 0x1090) */
+#define BIT_ATIM_END_INT14_MSK BIT(30)
+#define BIT_ATIM_END_INT13_MSK BIT(29)
+#define BIT_ATIM_END_INT12_MSK BIT(28)
+#define BIT_ATIM_END_INT11_MSK BIT(27)
+#define BIT_ATIM_END_INT10_MSK BIT(26)
+#define BIT_ATIM_END_INT9_MSK BIT(25)
+#define BIT_ATIM_END_INT8_MSK BIT(24)
+#define BIT_TX_BCN_ERR_INT15_MSK BIT(23)
+#define BIT_TX_BCN_ERR_INT14_MSK BIT(22)
+#define BIT_TX_BCN_ERR_INT13_MSK BIT(21)
+#define BIT_TX_BCN_ERR_INT12_MSK BIT(20)
+#define BIT_TX_BCN_ERR_INT11_MSK BIT(19)
+#define BIT_TX_BCN_ERR_INT10_MSK BIT(18)
+#define BIT_TX_BCN_ERR_INT9_MSK BIT(17)
+#define BIT_TX_BCN_ERR_INT8_MSK BIT(16)
+#define BIT_TX_BCN_OK_INT15_MSK BIT(15)
+#define BIT_TX_BCN_OK_INT14_MSK BIT(14)
+#define BIT_TX_BCN_OK_INT13_MSK BIT(13)
-/* 2 REG_FE4ISR (Offset 0x1134) */
+#endif
-#define BIT_PORT4_PKTIN_INT BIT(19)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_DATA_CPU_CTL0 (Offset 0x1090) */
+#define BIT_WDT_SYS_RST BIT(13)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8198F_SUPPORT)
-/* 2 REG_FE4ISR (Offset 0x1134) */
+/* 2 REG_HIMR4 (Offset 0x1090) */
-#define BIT_FS_CLI3_TXPKTIN_INT BIT(19)
+#define BIT_TX_BCN_OK_INT12_MSK BIT(12)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_DATA_CPU_CTL0 (Offset 0x1090) */
+#define BIT_WDT_ENABLE BIT(12)
-/* 2 REG_FE4ISR (Offset 0x1134) */
+#endif
-#define BIT_PORT3_PKTIN_INT BIT(18)
+#if (HALMAC_8198F_SUPPORT)
-#endif
+/* 2 REG_HIMR4 (Offset 0x1090) */
+#define BIT_TX_BCN_OK_INT11_MSK BIT(11)
+#define BIT_TX_BCN_OK_INT10_MSK BIT(10)
+#define BIT_TX_BCN_OK_INT9_MSK BIT(9)
+#define BIT_TX_BCN_OK_INT8_MSK BIT(8)
+#define BIT_BCN_DMA_INT15_MSK BIT(7)
+#define BIT_BCN_DMA_INT14_MSK BIT(6)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_FE4ISR (Offset 0x1134) */
+/* 2 REG_DATA_CPU_CTL0 (Offset 0x1090) */
-#define BIT_FS_CLI2_TXPKTIN_INT BIT(18)
+#define BIT_SHIFT_BOOT_SEL 6
+#define BIT_MASK_BOOT_SEL 0x3
+#define BIT_BOOT_SEL(x) (((x) & BIT_MASK_BOOT_SEL) << BIT_SHIFT_BOOT_SEL)
+#define BITS_BOOT_SEL (BIT_MASK_BOOT_SEL << BIT_SHIFT_BOOT_SEL)
+#define BIT_CLEAR_BOOT_SEL(x) ((x) & (~BITS_BOOT_SEL))
+#define BIT_GET_BOOT_SEL(x) (((x) >> BIT_SHIFT_BOOT_SEL) & BIT_MASK_BOOT_SEL)
+#define BIT_SET_BOOT_SEL(x, v) (BIT_CLEAR_BOOT_SEL(x) | BIT_BOOT_SEL(v))
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_HIMR4 (Offset 0x1090) */
+#define BIT_BCN_DMA_INT13_MSK BIT(5)
+#define BIT_BCN_DMA_INT12_MSK BIT(4)
-/* 2 REG_FE4ISR (Offset 0x1134) */
+#endif
-#define BIT_PORT2_PKTIN_INT BIT(17)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_DATA_CPU_CTL0 (Offset 0x1090) */
+#define BIT_CLK_SEL BIT(4)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8198F_SUPPORT)
-/* 2 REG_FE4ISR (Offset 0x1134) */
+/* 2 REG_HIMR4 (Offset 0x1090) */
-#define BIT_FS_CLI1_TXPKTIN_INT BIT(17)
+#define BIT_BCN_DMA_INT11_MSK BIT(3)
+#define BIT_BCN_DMA_INT10_MSK BIT(2)
+#define BIT_BCN_DMA_INT9_MSK BIT(1)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_DATA_CPU_CTL0 (Offset 0x1090) */
+#define BIT_DATA_PLATFORM_RST BIT(1)
-/* 2 REG_FE4ISR (Offset 0x1134) */
+#endif
-#define BIT_PORT1_PKTIN_INT BIT(16)
+#if (HALMAC_8198F_SUPPORT)
-#endif
+/* 2 REG_HIMR4 (Offset 0x1090) */
+#define BIT_BCN_DMA_INT8_MSK BIT(0)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_FE4ISR (Offset 0x1134) */
+/* 2 REG_DATA_CPU_CTL0 (Offset 0x1090) */
-#define BIT_FS_CLI0_TXPKTIN_INT BIT(16)
+#define BIT_DATA_CPU_RST BIT(0)
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_HISR4 (Offset 0x1094) */
+#define BIT_TX_BCN_ERR_INT15 BIT(23)
+#define BIT_TX_BCN_ERR_INT14 BIT(22)
+#define BIT_TX_BCN_ERR_INT13 BIT(21)
+#define BIT_TX_BCN_ERR_INT12 BIT(20)
+#define BIT_TX_BCN_ERR_INT11 BIT(19)
+#define BIT_TX_BCN_ERR_INT10 BIT(18)
+#define BIT_TX_BCN_ERR_INT9 BIT(17)
+#define BIT_TX_BCN_ERR_INT8 BIT(16)
+#define BIT_TX_BCN_OK_INT15 BIT(15)
+#define BIT_TX_BCN_OK_INT14 BIT(14)
+#define BIT_TX_BCN_OK_INT13 BIT(13)
+#define BIT_TX_BCN_OK_INT12 BIT(12)
+#define BIT_TX_BCN_OK_INT11 BIT(11)
+#define BIT_TX_BCN_OK_INT10 BIT(10)
+#define BIT_TX_BCN_OK_INT9 BIT(9)
+#define BIT_TX_BCN_OK_INT8 BIT(8)
+#define BIT_BCN_DMA_INT15 BIT(7)
-/* 2 REG_FE4ISR (Offset 0x1134) */
+#endif
-#define BIT_PORT4_RXUCMD0_OK_INT BIT(15)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_DATA_CPU_CTL1 (Offset 0x1094) */
+#define BIT_HOST_INTERFACE_IO_PATH BIT(7)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8198F_SUPPORT)
-/* 2 REG_FE4ISR (Offset 0x1134) */
+/* 2 REG_HISR4 (Offset 0x1094) */
-#define BIT_FS_CLI3_RX_UMD0_INT BIT(15)
+#define BIT_BCN_DMA_INT14 BIT(6)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_DATA_CPU_CTL1 (Offset 0x1094) */
+#define BIT_EN_TXDMA_OFLD BIT(6)
-/* 2 REG_FE4ISR (Offset 0x1134) */
+#endif
-#define BIT_PORT4_RXUCMD1_OK_INT BIT(14)
+#if (HALMAC_8198F_SUPPORT)
-#endif
+/* 2 REG_HISR4 (Offset 0x1094) */
+#define BIT_BCN_DMA_INT13 BIT(5)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_FE4ISR (Offset 0x1134) */
+/* 2 REG_DATA_CPU_CTL1 (Offset 0x1094) */
-#define BIT_FS_CLI3_RX_UMD1_INT BIT(14)
+#define BIT_EN_RXDMA_OFLD BIT(5)
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_HISR4 (Offset 0x1094) */
+#define BIT_BCN_DMA_INT12 BIT(4)
-/* 2 REG_FE4ISR (Offset 0x1134) */
+#endif
-#define BIT_PORT4_RXBCMD0_OK_INT BIT(13)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_DATA_CPU_CTL1 (Offset 0x1094) */
+#define BIT_EN_HCI_DMA_TX BIT(4)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8198F_SUPPORT)
-/* 2 REG_FE4ISR (Offset 0x1134) */
+/* 2 REG_HISR4 (Offset 0x1094) */
-#define BIT_FS_CLI3_RX_BMD0_INT BIT(13)
+#define BIT_BCN_DMA_INT11 BIT(3)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_DATA_CPU_CTL1 (Offset 0x1094) */
+#define BIT_EN_HCI_DMA_RX BIT(3)
-/* 2 REG_FE4ISR (Offset 0x1134) */
+#endif
-#define BIT_PORT4_RXBCMD1_OK_INT BIT(12)
+#if (HALMAC_8198F_SUPPORT)
-#endif
+/* 2 REG_HISR4 (Offset 0x1094) */
+#define BIT_BCN_DMA_INT10 BIT(2)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_FE4ISR (Offset 0x1134) */
+/* 2 REG_DATA_CPU_CTL1 (Offset 0x1094) */
-#define BIT_FS_CLI3_RX_BMD1_INT BIT(12)
+#define BIT_EN_AXI_DMA_TX BIT(2)
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_HISR4 (Offset 0x1094) */
+#define BIT_BCN_DMA_INT9 BIT(1)
-/* 2 REG_FE4ISR (Offset 0x1134) */
+#endif
-#define BIT_PORT3_RXUCMD0_OK_INT BIT(11)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_DATA_CPU_CTL1 (Offset 0x1094) */
+#define BIT_EN_AXI_DMA_RX BIT(1)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8198F_SUPPORT)
-/* 2 REG_FE4ISR (Offset 0x1134) */
+/* 2 REG_HISR4 (Offset 0x1094) */
-#define BIT_FS_CLI2_RX_UMD0_INT BIT(11)
+#define BIT_BCN_DMA_INT8 BIT(0)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_DATA_CPU_CTL1 (Offset 0x1094) */
+#define BIT_EN_PKT_ENG BIT(0)
-/* 2 REG_FE4ISR (Offset 0x1134) */
+#endif
-#define BIT_PORT3_RXUCMD1_OK_INT BIT(10)
+#if (HALMAC_8198F_SUPPORT)
-#endif
+/* 2 REG_HIMR5 (Offset 0x1098) */
+#define BIT_BCN_QDMA_ERR_INT15_MSK BIT(7)
+#define BIT_BCN_QDMA_ERR_INT14_MSK BIT(6)
+#define BIT_BCN_QDMA_ERR_INT13_MSK BIT(5)
+#define BIT_BCN_QDMA_ERR_INT12_MSK BIT(4)
+#define BIT_BCN_QDMA_ERR_INT11_MSK BIT(3)
+#define BIT_BCN_QDMA_ERR_INT10_MSK BIT(2)
+#define BIT_BCN_QDMA_ERR_INT9_MSK BIT(1)
+#define BIT_BCN_QDMA_ERR_INT8_MSK BIT(0)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_FE4ISR (Offset 0x1134) */
+/* 2 REG_TXDMA_STOP_HIMR (Offset 0x1098) */
-#define BIT_FS_CLI2_RX_UMD1_INT BIT(10)
+#define BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK 0
+#define BIT_MASK_NTH_TXDMA_STOP_INT_MSK 0x1ffff
+#define BIT_NTH_TXDMA_STOP_INT_MSK(x) \
+ (((x) & BIT_MASK_NTH_TXDMA_STOP_INT_MSK) \
+ << BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK)
+#define BITS_NTH_TXDMA_STOP_INT_MSK \
+ (BIT_MASK_NTH_TXDMA_STOP_INT_MSK << BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK)
+#define BIT_CLEAR_NTH_TXDMA_STOP_INT_MSK(x) \
+ ((x) & (~BITS_NTH_TXDMA_STOP_INT_MSK))
+#define BIT_GET_NTH_TXDMA_STOP_INT_MSK(x) \
+ (((x) >> BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK) & \
+ BIT_MASK_NTH_TXDMA_STOP_INT_MSK)
+#define BIT_SET_NTH_TXDMA_STOP_INT_MSK(x, v) \
+ (BIT_CLEAR_NTH_TXDMA_STOP_INT_MSK(x) | BIT_NTH_TXDMA_STOP_INT_MSK(v))
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_HISR5 (Offset 0x109C) */
+#define BIT_BCN_QDMA_ERR_INT15 BIT(7)
+#define BIT_BCN_QDMA_ERR_INT14 BIT(6)
+#define BIT_BCN_QDMA_ERR_INT13 BIT(5)
+#define BIT_BCN_QDMA_ERR_INT12 BIT(4)
+#define BIT_BCN_QDMA_ERR_INT11 BIT(3)
+#define BIT_BCN_QDMA_ERR_INT10 BIT(2)
+#define BIT_BCN_QDMA_ERR_INT9 BIT(1)
+#define BIT_BCN_QDMA_ERR_INT8 BIT(0)
-/* 2 REG_FE4ISR (Offset 0x1134) */
+#endif
-#define BIT_PORT3_RXBCMD0_OK_INT BIT(9)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_TXDMA_STOP_HISR (Offset 0x109C) */
+#define BIT_SHIFT_NTH_TXDMA_STOP_INT 0
+#define BIT_MASK_NTH_TXDMA_STOP_INT 0x1ffff
+#define BIT_NTH_TXDMA_STOP_INT(x) \
+ (((x) & BIT_MASK_NTH_TXDMA_STOP_INT) << BIT_SHIFT_NTH_TXDMA_STOP_INT)
+#define BITS_NTH_TXDMA_STOP_INT \
+ (BIT_MASK_NTH_TXDMA_STOP_INT << BIT_SHIFT_NTH_TXDMA_STOP_INT)
+#define BIT_CLEAR_NTH_TXDMA_STOP_INT(x) ((x) & (~BITS_NTH_TXDMA_STOP_INT))
+#define BIT_GET_NTH_TXDMA_STOP_INT(x) \
+ (((x) >> BIT_SHIFT_NTH_TXDMA_STOP_INT) & BIT_MASK_NTH_TXDMA_STOP_INT)
+#define BIT_SET_NTH_TXDMA_STOP_INT(x, v) \
+ (BIT_CLEAR_NTH_TXDMA_STOP_INT(x) | BIT_NTH_TXDMA_STOP_INT(v))
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_TXDMA_START_HIMR (Offset 0x10A0) */
+#define BIT_SHIFT_NTH_TXDMA_START_INT_MSK 0
+#define BIT_MASK_NTH_TXDMA_START_INT_MSK 0x1ffff
+#define BIT_NTH_TXDMA_START_INT_MSK(x) \
+ (((x) & BIT_MASK_NTH_TXDMA_START_INT_MSK) \
+ << BIT_SHIFT_NTH_TXDMA_START_INT_MSK)
+#define BITS_NTH_TXDMA_START_INT_MSK \
+ (BIT_MASK_NTH_TXDMA_START_INT_MSK << BIT_SHIFT_NTH_TXDMA_START_INT_MSK)
+#define BIT_CLEAR_NTH_TXDMA_START_INT_MSK(x) \
+ ((x) & (~BITS_NTH_TXDMA_START_INT_MSK))
+#define BIT_GET_NTH_TXDMA_START_INT_MSK(x) \
+ (((x) >> BIT_SHIFT_NTH_TXDMA_START_INT_MSK) & \
+ BIT_MASK_NTH_TXDMA_START_INT_MSK)
+#define BIT_SET_NTH_TXDMA_START_INT_MSK(x, v) \
+ (BIT_CLEAR_NTH_TXDMA_START_INT_MSK(x) | BIT_NTH_TXDMA_START_INT_MSK(v))
-/* 2 REG_FE4ISR (Offset 0x1134) */
+/* 2 REG_TXDMA_START_HISR (Offset 0x10A4) */
-#define BIT_FS_CLI2_RX_BMD0_INT BIT(9)
+#define BIT_SHIFT_NTH_TXDMA_START_INT 0
+#define BIT_MASK_NTH_TXDMA_START_INT 0x1ffff
+#define BIT_NTH_TXDMA_START_INT(x) \
+ (((x) & BIT_MASK_NTH_TXDMA_START_INT) << BIT_SHIFT_NTH_TXDMA_START_INT)
+#define BITS_NTH_TXDMA_START_INT \
+ (BIT_MASK_NTH_TXDMA_START_INT << BIT_SHIFT_NTH_TXDMA_START_INT)
+#define BIT_CLEAR_NTH_TXDMA_START_INT(x) ((x) & (~BITS_NTH_TXDMA_START_INT))
+#define BIT_GET_NTH_TXDMA_START_INT(x) \
+ (((x) >> BIT_SHIFT_NTH_TXDMA_START_INT) & BIT_MASK_NTH_TXDMA_START_INT)
+#define BIT_SET_NTH_TXDMA_START_INT(x, v) \
+ (BIT_CLEAR_NTH_TXDMA_START_INT(x) | BIT_NTH_TXDMA_START_INT(v))
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_NFCPAD_CTRL (Offset 0x10A8) */
+#define BIT_PAD_SHUTDW BIT(18)
+#define BIT_SYSON_NFC_PAD BIT(17)
+#define BIT_NFC_INT_PAD_CTRL BIT(16)
+#define BIT_NFC_RFDIS_PAD_CTRL BIT(15)
+#define BIT_NFC_CLK_PAD_CTRL BIT(14)
+#define BIT_NFC_DATA_PAD_CTRL BIT(13)
+#define BIT_NFC_PAD_PULL_CTRL BIT(12)
+
+#define BIT_SHIFT_NFCPAD_IO_SEL 8
+#define BIT_MASK_NFCPAD_IO_SEL 0xf
+#define BIT_NFCPAD_IO_SEL(x) \
+ (((x) & BIT_MASK_NFCPAD_IO_SEL) << BIT_SHIFT_NFCPAD_IO_SEL)
+#define BITS_NFCPAD_IO_SEL (BIT_MASK_NFCPAD_IO_SEL << BIT_SHIFT_NFCPAD_IO_SEL)
+#define BIT_CLEAR_NFCPAD_IO_SEL(x) ((x) & (~BITS_NFCPAD_IO_SEL))
+#define BIT_GET_NFCPAD_IO_SEL(x) \
+ (((x) >> BIT_SHIFT_NFCPAD_IO_SEL) & BIT_MASK_NFCPAD_IO_SEL)
+#define BIT_SET_NFCPAD_IO_SEL(x, v) \
+ (BIT_CLEAR_NFCPAD_IO_SEL(x) | BIT_NFCPAD_IO_SEL(v))
+
+#define BIT_SHIFT_NFCPAD_OUT 4
+#define BIT_MASK_NFCPAD_OUT 0xf
+#define BIT_NFCPAD_OUT(x) (((x) & BIT_MASK_NFCPAD_OUT) << BIT_SHIFT_NFCPAD_OUT)
+#define BITS_NFCPAD_OUT (BIT_MASK_NFCPAD_OUT << BIT_SHIFT_NFCPAD_OUT)
+#define BIT_CLEAR_NFCPAD_OUT(x) ((x) & (~BITS_NFCPAD_OUT))
+#define BIT_GET_NFCPAD_OUT(x) \
+ (((x) >> BIT_SHIFT_NFCPAD_OUT) & BIT_MASK_NFCPAD_OUT)
+#define BIT_SET_NFCPAD_OUT(x, v) (BIT_CLEAR_NFCPAD_OUT(x) | BIT_NFCPAD_OUT(v))
+
+#define BIT_SHIFT_NFCPAD_IN 0
+#define BIT_MASK_NFCPAD_IN 0xf
+#define BIT_NFCPAD_IN(x) (((x) & BIT_MASK_NFCPAD_IN) << BIT_SHIFT_NFCPAD_IN)
+#define BITS_NFCPAD_IN (BIT_MASK_NFCPAD_IN << BIT_SHIFT_NFCPAD_IN)
+#define BIT_CLEAR_NFCPAD_IN(x) ((x) & (~BITS_NFCPAD_IN))
+#define BIT_GET_NFCPAD_IN(x) (((x) >> BIT_SHIFT_NFCPAD_IN) & BIT_MASK_NFCPAD_IN)
+#define BIT_SET_NFCPAD_IN(x, v) (BIT_CLEAR_NFCPAD_IN(x) | BIT_NFCPAD_IN(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_FE4ISR (Offset 0x1134) */
+/* 2 REG_HIMR2 (Offset 0x10B0) */
-#define BIT_PORT3_RXBCMD1_OK_INT BIT(8)
+#define BIT_BCNDMAINT_P4_MSK BIT(31)
+#define BIT_BCNDMAINT_P4 BIT(31)
+#define BIT_BCNDMAINT_P3_MSK BIT(30)
+#define BIT_BCNDMAINT_P3 BIT(30)
+#define BIT_BCNDMAINT_P2_MSK BIT(29)
+#define BIT_BCNDMAINT_P2 BIT(29)
+#define BIT_BCNDMAINT_P1_MSK BIT(28)
+#define BIT_BCNDMAINT_P1 BIT(28)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_FE4ISR (Offset 0x1134) */
+/* 2 REG_HIMR2 (Offset 0x10B0) */
-#define BIT_FS_CLI2_RX_BMD1_INT BIT(8)
+#define BIT_SCH_PHY_TXOP_SIFS_INT_MSK BIT(23)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_HIMR2 (Offset 0x10B0) */
+#define BIT_ATIMEND7_MSK BIT(22)
+#define BIT_ATIMEND7 BIT(22)
+#define BIT_ATIMEND6_MSK BIT(21)
+#define BIT_ATIMEND6 BIT(21)
+#define BIT_ATIMEND5_MSK BIT(20)
+#define BIT_ATIMEND5 BIT(20)
+#define BIT_ATIMEND4_MSK BIT(19)
+#define BIT_ATIMEND4 BIT(19)
+#define BIT_ATIMEND3_MSK BIT(18)
+#define BIT_ATIMEND3 BIT(18)
+#define BIT_ATIMEND2_MSK BIT(17)
+#define BIT_ATIMEND2 BIT(17)
+#define BIT_ATIMEND1_MSK BIT(16)
+#define BIT_ATIMEND1 BIT(16)
+#define BIT_TXBCN7OK_MSK BIT(14)
+#define BIT_TXBCN7OK BIT(14)
+#define BIT_TXBCN6OK_MSK BIT(13)
+#define BIT_TXBCN6OK BIT(13)
+#define BIT_TXBCN5OK_MSK BIT(12)
+#define BIT_TXBCN5OK BIT(12)
+#define BIT_TXBCN4OK_MSK BIT(11)
+#define BIT_TXBCN4OK BIT(11)
+#define BIT_TXBCN3OK_MSK BIT(10)
+#define BIT_TXBCN3OK BIT(10)
+#define BIT_TXBCN2OK_MSK BIT(9)
+#define BIT_TXBCN2OK BIT(9)
+#define BIT_TXBCN1OK_MSK_V1 BIT(8)
+#define BIT_TXBCN1OK BIT(8)
+#define BIT_TXBCN7ERR_MSK BIT(6)
+#define BIT_TXBCN7ERR BIT(6)
+#define BIT_TXBCN6ERR_MSK BIT(5)
+#define BIT_TXBCN6ERR BIT(5)
+#define BIT_TXBCN5ERR_MSK BIT(4)
+#define BIT_TXBCN5ERR BIT(4)
+#define BIT_TXBCN4ERR_MSK BIT(3)
+#define BIT_TXBCN4ERR BIT(3)
+#define BIT_TXBCN3ERR_MSK BIT(2)
+#define BIT_TXBCN3ERR BIT(2)
+#define BIT_TXBCN2ERR_MSK BIT(1)
+#define BIT_TXBCN2ERR BIT(1)
+#define BIT_TXBCN1ERR_MSK_V1 BIT(0)
+#define BIT_TXBCN1ERR BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_FE4ISR (Offset 0x1134) */
+/* 2 REG_HIMR3 (Offset 0x10B8) */
-#define BIT_PORT2_RXUCMD0_OK_INT BIT(7)
+#define BIT_GTINT12 BIT(24)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_HIMR3 (Offset 0x10B8) */
+#define BIT_GTINT12_MSK BIT(24)
-/* 2 REG_FE4ISR (Offset 0x1134) */
+#endif
-#define BIT_FS_CLI1_RX_UMD0_INT BIT(7)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_HIMR3 (Offset 0x10B8) */
+#define BIT_GTINT11 BIT(23)
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_FE4ISR (Offset 0x1134) */
+/* 2 REG_HIMR3 (Offset 0x10B8) */
-#define BIT_PORT2_RXUCMD1_OK_INT BIT(6)
+#define BIT_GTINT11_MSK BIT(23)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_HIMR3 (Offset 0x10B8) */
+#define BIT_GTINT10 BIT(22)
-/* 2 REG_FE4ISR (Offset 0x1134) */
+#endif
-#define BIT_FS_CLI1_RX_UMD1_INT BIT(6)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_HIMR3 (Offset 0x10B8) */
+#define BIT_GTINT10_MSK BIT(22)
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_FE4ISR (Offset 0x1134) */
+/* 2 REG_HIMR3 (Offset 0x10B8) */
-#define BIT_PORT2_RXBCMD0_OK_INT BIT(5)
+#define BIT_GTINT9 BIT(21)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_HIMR3 (Offset 0x10B8) */
+#define BIT_GTINT9_MSK BIT(21)
-/* 2 REG_FE4ISR (Offset 0x1134) */
+#endif
-#define BIT_FS_CLI1_RX_BMD0_INT BIT(5)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_HIMR3 (Offset 0x10B8) */
+#define BIT_RX_DESC_BUF_FULL BIT(20)
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_FE4ISR (Offset 0x1134) */
+/* 2 REG_HIMR3 (Offset 0x10B8) */
-#define BIT_PORT2_RXBCMD1_OK_INT BIT(4)
+#define BIT_RX_DESC_BUF_FULL_MSK BIT(20)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_HIMR3 (Offset 0x10B8) */
+#define BIT_CPHY_LDO_OCP_DET_INT BIT(19)
-/* 2 REG_FE4ISR (Offset 0x1134) */
+#endif
-#define BIT_FS_CLI1_RX_BMD1_INT BIT(4)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_HIMR3 (Offset 0x10B8) */
+#define BIT_CPHY_LDO_OCP_DET_INT_MSK BIT(19)
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-/* 2 REG_FE4ISR (Offset 0x1134) */
+/* 2 REG_HIMR3 (Offset 0x10B8) */
-#define BIT_PORT1_RXUCMD0_OK_INT BIT(3)
+#define BIT_WDT_PLATFORM_INT_MSK BIT(18)
+#define BIT_WDT_PLATFORM_INT BIT(18)
+#define BIT_WDT_CPU_INT_MSK BIT(17)
+#define BIT_WDT_CPU_INT BIT(17)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_HIMR3 (Offset 0x10B8) */
+#define BIT_SETH2CDOK_MASK BIT(16)
+#define BIT_SETH2CDOK BIT(16)
+#define BIT_H2C_CMD_FULL_MASK BIT(15)
+#define BIT_H2C_CMD_FULL BIT(15)
-/* 2 REG_FE4ISR (Offset 0x1134) */
+#endif
-#define BIT_FS_CLI0_RX_UMD0_INT BIT(3)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_HIMR3 (Offset 0x10B8) */
+#define BIT_PWR_INT_127_MASK BIT(14)
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_FE4ISR (Offset 0x1134) */
+/* 2 REG_HIMR3 (Offset 0x10B8) */
-#define BIT_PORT1_RXUCMD1_OK_INT BIT(2)
+#define BIT_PKT_TRANS_ERR BIT(14)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_HIMR3 (Offset 0x10B8) */
+#define BIT_PKT_TRANS_ERR_MASK BIT(14)
-/* 2 REG_FE4ISR (Offset 0x1134) */
+#endif
-#define BIT_FS_DMEM1_WPTR_UPDATE_INT BIT(2)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_HIMR3 (Offset 0x10B8) */
+#define BIT_TXSHORTCUT_TXDESUPDATEOK_MASK BIT(13)
+#define BIT_TXSHORTCUT_TXDESUPDATEOK BIT(13)
+#define BIT_TXSHORTCUT_BKUPDATEOK_MASK BIT(12)
+#define BIT_TXSHORTCUT_BKUPDATEOK BIT(12)
+#define BIT_TXSHORTCUT_BEUPDATEOK_MASK BIT(11)
+#define BIT_TXSHORTCUT_BEUPDATEOK BIT(11)
+#define BIT_TXSHORTCUT_VIUPDATEOK_MAS BIT(10)
+#define BIT_TXSHORTCUT_VIUPDATEOK BIT(10)
+#define BIT_TXSHORTCUT_VOUPDATEOK_MASK BIT(9)
+#define BIT_TXSHORTCUT_VOUPDATEOK BIT(9)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-/* 2 REG_FE4ISR (Offset 0x1134) */
+/* 2 REG_HIMR3 (Offset 0x10B8) */
-#define BIT_FS_CLI0_RX_UMD1_INT BIT(2)
+#define BIT_PWR_INT_127_MASK_V1 BIT(8)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_HIMR3 (Offset 0x10B8) */
+#define BIT_SEARCH_FAIL BIT(8)
-/* 2 REG_FE4ISR (Offset 0x1134) */
+#endif
-#define BIT_PORT1_RXBCMD0_OK_INT BIT(1)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_HIMR3 (Offset 0x10B8) */
+#define BIT_SEARCH_FAIL_MSK BIT(8)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-/* 2 REG_FE4ISR (Offset 0x1134) */
+/* 2 REG_HIMR3 (Offset 0x10B8) */
-#define BIT_FS_CLI0_RX_BMD0_INT BIT(1)
+#define BIT_PWR_INT_126TO96_MASK BIT(7)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_HIMR3 (Offset 0x10B8) */
+#define BIT_PWR_INT_127TO96 BIT(7)
-/* 2 REG_FE4ISR (Offset 0x1134) */
+#endif
-#define BIT_PORT1_RXBCMD1_OK_INT BIT(0)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_HIMR3 (Offset 0x10B8) */
+#define BIT_PWR_INT_127TO96_MASK BIT(7)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_FE4ISR (Offset 0x1134) */
+/* 2 REG_HIMR3 (Offset 0x10B8) */
-#define BIT_FS_CLI0_RX_BMD1_INT BIT(0)
+#define BIT_PWR_INT_95TO64_MASK BIT(6)
+#define BIT_PWR_INT_95TO64 BIT(6)
+#define BIT_PWR_INT_63TO32_MASK BIT(5)
+#define BIT_PWR_INT_63TO32 BIT(5)
+#define BIT_PWR_INT_31TO0_MASK BIT(4)
+#define BIT_PWR_INT_31TO0 BIT(4)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_HIMR3 (Offset 0x10B8) */
+#define BIT_RX_DMA_STUCK_MSK BIT(3)
+#define BIT_RX_DMA_STUCK BIT(3)
+#define BIT_TX_DMA_STUCK_MSK BIT(2)
+#define BIT_TX_DMA_STUCK BIT(2)
-/* 2 REG_FT1IMR (Offset 0x1138) */
+#endif
-#define BIT__FT2ISR__IND_MSK BIT(30)
-#define BIT_FTM_PTT_INT_EN BIT(29)
-#define BIT_RXFTMREQ_INT_EN BIT(28)
-#define BIT_RXFTM_INT_EN BIT(27)
-#define BIT_TXFTM_INT_EN BIT(26)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_HIMR3 (Offset 0x10B8) */
+#define BIT_DDMA0_LP_INT_MSK BIT(1)
+#define BIT_DDMA0_LP_INT BIT(1)
+#define BIT_DDMA0_HP_INT_MSK BIT(0)
+#define BIT_DDMA0_HP_INT BIT(0)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-/* 2 REG_FT1IMR (Offset 0x1138) */
+/* 2 REG_HISR3 (Offset 0x10BC) */
-#define BIT_FS_H2C_CMD_OK_INT_EN BIT(25)
-#define BIT_FS_H2C_CMD_FULL_INT_EN BIT(24)
+#define BIT_PWR_INT_127 BIT(14)
+#define BIT_PWR_INT_127_V1 BIT(8)
+#define BIT_PWR_INT_126TO96 BIT(7)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_SW_MDIO (Offset 0x10C0) */
+#define BIT_DIS_TIMEOUT_IO BIT(24)
-/* 2 REG_FT1IMR (Offset 0x1138) */
+#endif
-#define BIT_FS_MACID_PWRCHANGE5_INT_EN BIT(23)
-#define BIT_FS_MACID_PWRCHANGE4_INT_EN BIT(22)
-#define BIT_FS_MACID_PWRCHANGE3_INT_EN BIT(21)
-#define BIT_FS_MACID_PWRCHANGE2_INT_EN BIT(20)
-#define BIT_FS_MACID_PWRCHANGE1_INT_EN BIT(19)
-#define BIT_FS_MACID_PWRCHANGE0_INT_EN BIT(18)
-#define BIT_FS_CTWEND2_INT_EN BIT(17)
-#define BIT_FS_CTWEND1_INT_EN BIT(16)
-#define BIT_FS_CTWEND0_INT_EN BIT(15)
-#define BIT_FS_TX_NULL1_INT_EN BIT(14)
-#define BIT_FS_TX_NULL0_INT_EN BIT(13)
-#define BIT_FS_TSF_BIT32_TOGGLE_EN BIT(12)
-#define BIT_FS_P2P_RFON2_INT_EN BIT(11)
-#define BIT_FS_P2P_RFOFF2_INT_EN BIT(10)
-#define BIT_FS_P2P_RFON1_INT_EN BIT(9)
-#define BIT_FS_P2P_RFOFF1_INT_EN BIT(8)
-#define BIT_FS_P2P_RFON0_INT_EN BIT(7)
-#define BIT_FS_P2P_RFOFF0_INT_EN BIT(6)
-#define BIT_FS_RX_UAPSDMD1_EN BIT(5)
-#define BIT_FS_RX_UAPSDMD0_EN BIT(4)
-#define BIT_FS_TRIGGER_PKT_EN BIT(3)
-#define BIT_FS_EOSP_INT_EN BIT(2)
-#define BIT_FS_RPWM2_INT_EN BIT(1)
-#define BIT_FS_RPWM_INT_EN BIT(0)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#endif
+/* 2 REG_SW_MDIO (Offset 0x10C0) */
+#define BIT_SUS_PL BIT(18)
+#define BIT_SOP_ESUS BIT(17)
+#define BIT_SOP_DLDO BIT(16)
+#define BIT_R_OCP_ST_CLR BIT(8)
+#define BIT_SW_USB3_MD_SEL BIT(5)
+#define BIT_SW_PCIE_MD_SEL BIT(4)
+#define BIT_SW_MDCK BIT(2)
+#define BIT_SW_MDI BIT(1)
+#define BIT_MDO BIT(0)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
-/* 2 REG_FT1ISR (Offset 0x113C) */
+/* 2 REG_SW_FLUSH (Offset 0x10C4) */
-#define BIT__FT2ISR__IND_INT BIT(30)
-#define BIT_FTM_PTT_INT BIT(29)
-#define BIT_RXFTMREQ_INT BIT(28)
-#define BIT_RXFTM_INT BIT(27)
-#define BIT_TXFTM_INT BIT(26)
+#define BIT_FLUSH_HOLDN_EN BIT(25)
+#define BIT_FLUSH_WR_EN BIT(24)
+#define BIT_SW_FLASH_CONTROL BIT(23)
+#define BIT_SW_FLASH_WEN_E BIT(19)
+#define BIT_SW_FLASH_HOLDN_E BIT(18)
+#define BIT_SW_FLASH_SO_E BIT(17)
+#define BIT_SW_FLASH_SI_E BIT(16)
+#define BIT_SW_FLASH_SK_O BIT(13)
+#define BIT_SW_FLASH_CEN_O BIT(12)
+#define BIT_SW_FLASH_WEN_O BIT(11)
+#define BIT_SW_FLASH_HOLDN_O BIT(10)
+#define BIT_SW_FLASH_SO_O BIT(9)
+#define BIT_SW_FLASH_SI_O BIT(8)
+#define BIT_SW_FLASH_WEN_I BIT(3)
+#define BIT_SW_FLASH_HOLDN_I BIT(2)
+#define BIT_SW_FLASH_SO_I BIT(1)
+#define BIT_SW_FLASH_SI_I BIT(0)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_HIMR_7 (Offset 0x10C8) */
+#define BIT_DATA_CPU_WDT_INT_MSK BIT(31)
+#define BIT_OFLD_TXDMA_ERR_MSK BIT(30)
+#define BIT_OFLD_TXDMA_FULL_MSK BIT(29)
+#define BIT_OFLD_RXDMA_OVR_MSK BIT(28)
+#define BIT_OFLD_RXDMA_ERR_MSK BIT(27)
+#define BIT_OFLD_RXDMA_DES_UA_MSK BIT(26)
-/* 2 REG_FT1ISR (Offset 0x113C) */
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_DBG_GPIO_BMUX (Offset 0x10C8) */
-#define BIT_FS_H2C_CMD_OK_INT BIT(25)
-#define BIT_FS_H2C_CMD_FULL_INT BIT(24)
+#define BIT_SHIFT_DBG_GPIO_BMUX_7 21
+#define BIT_MASK_DBG_GPIO_BMUX_7 0x7
+#define BIT_DBG_GPIO_BMUX_7(x) \
+ (((x) & BIT_MASK_DBG_GPIO_BMUX_7) << BIT_SHIFT_DBG_GPIO_BMUX_7)
+#define BITS_DBG_GPIO_BMUX_7 \
+ (BIT_MASK_DBG_GPIO_BMUX_7 << BIT_SHIFT_DBG_GPIO_BMUX_7)
+#define BIT_CLEAR_DBG_GPIO_BMUX_7(x) ((x) & (~BITS_DBG_GPIO_BMUX_7))
+#define BIT_GET_DBG_GPIO_BMUX_7(x) \
+ (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_7) & BIT_MASK_DBG_GPIO_BMUX_7)
+#define BIT_SET_DBG_GPIO_BMUX_7(x, v) \
+ (BIT_CLEAR_DBG_GPIO_BMUX_7(x) | BIT_DBG_GPIO_BMUX_7(v))
+
+#define BIT_SHIFT_DBG_GPIO_BMUX_6 18
+#define BIT_MASK_DBG_GPIO_BMUX_6 0x7
+#define BIT_DBG_GPIO_BMUX_6(x) \
+ (((x) & BIT_MASK_DBG_GPIO_BMUX_6) << BIT_SHIFT_DBG_GPIO_BMUX_6)
+#define BITS_DBG_GPIO_BMUX_6 \
+ (BIT_MASK_DBG_GPIO_BMUX_6 << BIT_SHIFT_DBG_GPIO_BMUX_6)
+#define BIT_CLEAR_DBG_GPIO_BMUX_6(x) ((x) & (~BITS_DBG_GPIO_BMUX_6))
+#define BIT_GET_DBG_GPIO_BMUX_6(x) \
+ (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_6) & BIT_MASK_DBG_GPIO_BMUX_6)
+#define BIT_SET_DBG_GPIO_BMUX_6(x, v) \
+ (BIT_CLEAR_DBG_GPIO_BMUX_6(x) | BIT_DBG_GPIO_BMUX_6(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_HIMR_7 (Offset 0x10C8) */
+#define BIT_TXDMAOK_CHANNEL_16_MSK BIT(16)
-/* 2 REG_FT1ISR (Offset 0x113C) */
+#endif
-#define BIT_FS_MACID_PWRCHANGE5_INT BIT(23)
-#define BIT_FS_MACID_PWRCHANGE4_INT BIT(22)
-#define BIT_FS_MACID_PWRCHANGE3_INT BIT(21)
-#define BIT_FS_MACID_PWRCHANGE2_INT BIT(20)
-#define BIT_FS_MACID_PWRCHANGE1_INT BIT(19)
-#define BIT_FS_MACID_PWRCHANGE0_INT BIT(18)
-#define BIT_FS_CTWEND2_INT BIT(17)
-#define BIT_FS_CTWEND1_INT BIT(16)
-#define BIT_FS_CTWEND0_INT BIT(15)
-#define BIT_FS_TX_NULL1_INT BIT(14)
-#define BIT_FS_TX_NULL0_INT BIT(13)
-#define BIT_FS_TSF_BIT32_TOGGLE_INT BIT(12)
-#define BIT_FS_P2P_RFON2_INT BIT(11)
-#define BIT_FS_P2P_RFOFF2_INT BIT(10)
-#define BIT_FS_P2P_RFON1_INT BIT(9)
-#define BIT_FS_P2P_RFOFF1_INT BIT(8)
-#define BIT_FS_P2P_RFON0_INT BIT(7)
-#define BIT_FS_P2P_RFOFF0_INT BIT(6)
-#define BIT_FS_RX_UAPSDMD1_INT BIT(5)
-#define BIT_FS_RX_UAPSDMD0_INT BIT(4)
-#define BIT_FS_TRIGGER_PKT_INT BIT(3)
-#define BIT_FS_EOSP_INT BIT(2)
-#define BIT_FS_RPWM2_INT BIT(1)
-#define BIT_FS_RPWM_INT BIT(0)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-/* 2 REG_SPWR0 (Offset 0x1140) */
+/* 2 REG_DBG_GPIO_BMUX (Offset 0x10C8) */
+#define BIT_SHIFT_DBG_GPIO_BMUX_5 15
+#define BIT_MASK_DBG_GPIO_BMUX_5 0x7
+#define BIT_DBG_GPIO_BMUX_5(x) \
+ (((x) & BIT_MASK_DBG_GPIO_BMUX_5) << BIT_SHIFT_DBG_GPIO_BMUX_5)
+#define BITS_DBG_GPIO_BMUX_5 \
+ (BIT_MASK_DBG_GPIO_BMUX_5 << BIT_SHIFT_DBG_GPIO_BMUX_5)
+#define BIT_CLEAR_DBG_GPIO_BMUX_5(x) ((x) & (~BITS_DBG_GPIO_BMUX_5))
+#define BIT_GET_DBG_GPIO_BMUX_5(x) \
+ (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_5) & BIT_MASK_DBG_GPIO_BMUX_5)
+#define BIT_SET_DBG_GPIO_BMUX_5(x, v) \
+ (BIT_CLEAR_DBG_GPIO_BMUX_5(x) | BIT_DBG_GPIO_BMUX_5(v))
-#define BIT_SHIFT_MID_31TO0 0
-#define BIT_MASK_MID_31TO0 0xffffffffL
-#define BIT_MID_31TO0(x) (((x) & BIT_MASK_MID_31TO0) << BIT_SHIFT_MID_31TO0)
-#define BIT_GET_MID_31TO0(x) (((x) >> BIT_SHIFT_MID_31TO0) & BIT_MASK_MID_31TO0)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_SPWR1 (Offset 0x1144) */
+/* 2 REG_HIMR_7 (Offset 0x10C8) */
+#define BIT_TXDMAOK_CHANNEL_13_MSK BIT(13)
-#define BIT_SHIFT_MID_63TO32 0
-#define BIT_MASK_MID_63TO32 0xffffffffL
-#define BIT_MID_63TO32(x) (((x) & BIT_MASK_MID_63TO32) << BIT_SHIFT_MID_63TO32)
-#define BIT_GET_MID_63TO32(x) (((x) >> BIT_SHIFT_MID_63TO32) & BIT_MASK_MID_63TO32)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-/* 2 REG_SPWR2 (Offset 0x1148) */
+/* 2 REG_DBG_GPIO_BMUX (Offset 0x10C8) */
+#define BIT_SHIFT_DBG_GPIO_BMUX_4 12
+#define BIT_MASK_DBG_GPIO_BMUX_4 0x7
+#define BIT_DBG_GPIO_BMUX_4(x) \
+ (((x) & BIT_MASK_DBG_GPIO_BMUX_4) << BIT_SHIFT_DBG_GPIO_BMUX_4)
+#define BITS_DBG_GPIO_BMUX_4 \
+ (BIT_MASK_DBG_GPIO_BMUX_4 << BIT_SHIFT_DBG_GPIO_BMUX_4)
+#define BIT_CLEAR_DBG_GPIO_BMUX_4(x) ((x) & (~BITS_DBG_GPIO_BMUX_4))
+#define BIT_GET_DBG_GPIO_BMUX_4(x) \
+ (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_4) & BIT_MASK_DBG_GPIO_BMUX_4)
+#define BIT_SET_DBG_GPIO_BMUX_4(x, v) \
+ (BIT_CLEAR_DBG_GPIO_BMUX_4(x) | BIT_DBG_GPIO_BMUX_4(v))
-#define BIT_SHIFT_MID_95O64 0
-#define BIT_MASK_MID_95O64 0xffffffffL
-#define BIT_MID_95O64(x) (((x) & BIT_MASK_MID_95O64) << BIT_SHIFT_MID_95O64)
-#define BIT_GET_MID_95O64(x) (((x) >> BIT_SHIFT_MID_95O64) & BIT_MASK_MID_95O64)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_SPWR3 (Offset 0x114C) */
+/* 2 REG_HIMR_7 (Offset 0x10C8) */
+#define BIT_TXDMAOK_CHANNEL_12_MSK BIT(12)
+#define BIT_TXDMAOK_CHANNEL_11_MSK BIT(11)
+#define BIT_TXDMAOK_CHANNEL_10_MSK BIT(10)
-#define BIT_SHIFT_MID_127TO96 0
-#define BIT_MASK_MID_127TO96 0xffffffffL
-#define BIT_MID_127TO96(x) (((x) & BIT_MASK_MID_127TO96) << BIT_SHIFT_MID_127TO96)
-#define BIT_GET_MID_127TO96(x) (((x) >> BIT_SHIFT_MID_127TO96) & BIT_MASK_MID_127TO96)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-/* 2 REG_POWSEQ (Offset 0x1150) */
+/* 2 REG_DBG_GPIO_BMUX (Offset 0x10C8) */
+#define BIT_SHIFT_DBG_GPIO_BMUX_3 9
+#define BIT_MASK_DBG_GPIO_BMUX_3 0x7
+#define BIT_DBG_GPIO_BMUX_3(x) \
+ (((x) & BIT_MASK_DBG_GPIO_BMUX_3) << BIT_SHIFT_DBG_GPIO_BMUX_3)
+#define BITS_DBG_GPIO_BMUX_3 \
+ (BIT_MASK_DBG_GPIO_BMUX_3 << BIT_SHIFT_DBG_GPIO_BMUX_3)
+#define BIT_CLEAR_DBG_GPIO_BMUX_3(x) ((x) & (~BITS_DBG_GPIO_BMUX_3))
+#define BIT_GET_DBG_GPIO_BMUX_3(x) \
+ (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_3) & BIT_MASK_DBG_GPIO_BMUX_3)
+#define BIT_SET_DBG_GPIO_BMUX_3(x, v) \
+ (BIT_CLEAR_DBG_GPIO_BMUX_3(x) | BIT_DBG_GPIO_BMUX_3(v))
-#define BIT_SHIFT_SEQNUM_MID 16
-#define BIT_MASK_SEQNUM_MID 0xffff
-#define BIT_SEQNUM_MID(x) (((x) & BIT_MASK_SEQNUM_MID) << BIT_SHIFT_SEQNUM_MID)
-#define BIT_GET_SEQNUM_MID(x) (((x) >> BIT_SHIFT_SEQNUM_MID) & BIT_MASK_SEQNUM_MID)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_REF_MID 0
-#define BIT_MASK_REF_MID 0x7f
-#define BIT_REF_MID(x) (((x) & BIT_MASK_REF_MID) << BIT_SHIFT_REF_MID)
-#define BIT_GET_REF_MID(x) (((x) >> BIT_SHIFT_REF_MID) & BIT_MASK_REF_MID)
+/* 2 REG_HIMR_7 (Offset 0x10C8) */
+#define BIT_TXDMAOK_CHANNEL_9_MSK BIT(9)
+#define BIT_TXDMAOK_CHANNEL_8_MSK BIT(8)
+#define BIT_TXDMAOK_CHANNEL_7_MSK BIT(7)
-/* 2 REG_TC7_CTRL_V1 (Offset 0x1158) */
+#endif
-#define BIT_TC7INT_EN BIT(26)
-#define BIT_TC7MODE BIT(25)
-#define BIT_TC7EN BIT(24)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_TC7DATA 0
-#define BIT_MASK_TC7DATA 0xffffff
-#define BIT_TC7DATA(x) (((x) & BIT_MASK_TC7DATA) << BIT_SHIFT_TC7DATA)
-#define BIT_GET_TC7DATA(x) (((x) >> BIT_SHIFT_TC7DATA) & BIT_MASK_TC7DATA)
+/* 2 REG_DBG_GPIO_BMUX (Offset 0x10C8) */
+#define BIT_SHIFT_DBG_GPIO_BMUX_2 6
+#define BIT_MASK_DBG_GPIO_BMUX_2 0x7
+#define BIT_DBG_GPIO_BMUX_2(x) \
+ (((x) & BIT_MASK_DBG_GPIO_BMUX_2) << BIT_SHIFT_DBG_GPIO_BMUX_2)
+#define BITS_DBG_GPIO_BMUX_2 \
+ (BIT_MASK_DBG_GPIO_BMUX_2 << BIT_SHIFT_DBG_GPIO_BMUX_2)
+#define BIT_CLEAR_DBG_GPIO_BMUX_2(x) ((x) & (~BITS_DBG_GPIO_BMUX_2))
+#define BIT_GET_DBG_GPIO_BMUX_2(x) \
+ (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_2) & BIT_MASK_DBG_GPIO_BMUX_2)
+#define BIT_SET_DBG_GPIO_BMUX_2(x, v) \
+ (BIT_CLEAR_DBG_GPIO_BMUX_2(x) | BIT_DBG_GPIO_BMUX_2(v))
-/* 2 REG_TC8_CTRL_V1 (Offset 0x115C) */
+#endif
-#define BIT_TC8INT_EN BIT(26)
-#define BIT_TC8MODE BIT(25)
-#define BIT_TC8EN BIT(24)
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_TC8DATA 0
-#define BIT_MASK_TC8DATA 0xffffff
-#define BIT_TC8DATA(x) (((x) & BIT_MASK_TC8DATA) << BIT_SHIFT_TC8DATA)
-#define BIT_GET_TC8DATA(x) (((x) >> BIT_SHIFT_TC8DATA) & BIT_MASK_TC8DATA)
+/* 2 REG_HIMR_7 (Offset 0x10C8) */
+#define BIT_TXDMAOK_CHANNEL_6_MSK BIT(6)
+#define BIT_TXDMAOK_CHANNEL_5_MSK BIT(5)
+#define BIT_TXDMAOK_CHANNEL_4_MSK BIT(4)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_DBG_GPIO_BMUX (Offset 0x10C8) */
+#define BIT_SHIFT_DBG_GPIO_BMUX_1 3
+#define BIT_MASK_DBG_GPIO_BMUX_1 0x7
+#define BIT_DBG_GPIO_BMUX_1(x) \
+ (((x) & BIT_MASK_DBG_GPIO_BMUX_1) << BIT_SHIFT_DBG_GPIO_BMUX_1)
+#define BITS_DBG_GPIO_BMUX_1 \
+ (BIT_MASK_DBG_GPIO_BMUX_1 << BIT_SHIFT_DBG_GPIO_BMUX_1)
+#define BIT_CLEAR_DBG_GPIO_BMUX_1(x) ((x) & (~BITS_DBG_GPIO_BMUX_1))
+#define BIT_GET_DBG_GPIO_BMUX_1(x) \
+ (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_1) & BIT_MASK_DBG_GPIO_BMUX_1)
+#define BIT_SET_DBG_GPIO_BMUX_1(x, v) \
+ (BIT_CLEAR_DBG_GPIO_BMUX_1(x) | BIT_DBG_GPIO_BMUX_1(v))
-/* 2 REG_EXT_QUEUE_REG (Offset 0x11C0) */
+#define BIT_SHIFT_DBG_GPIO_BMUX_0 0
+#define BIT_MASK_DBG_GPIO_BMUX_0 0x7
+#define BIT_DBG_GPIO_BMUX_0(x) \
+ (((x) & BIT_MASK_DBG_GPIO_BMUX_0) << BIT_SHIFT_DBG_GPIO_BMUX_0)
+#define BITS_DBG_GPIO_BMUX_0 \
+ (BIT_MASK_DBG_GPIO_BMUX_0 << BIT_SHIFT_DBG_GPIO_BMUX_0)
+#define BIT_CLEAR_DBG_GPIO_BMUX_0(x) ((x) & (~BITS_DBG_GPIO_BMUX_0))
+#define BIT_GET_DBG_GPIO_BMUX_0(x) \
+ (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_0) & BIT_MASK_DBG_GPIO_BMUX_0)
+#define BIT_SET_DBG_GPIO_BMUX_0(x, v) \
+ (BIT_CLEAR_DBG_GPIO_BMUX_0(x) | BIT_DBG_GPIO_BMUX_0(v))
+#endif
-#define BIT_SHIFT_PCIE_PRIORITY_SEL 0
-#define BIT_MASK_PCIE_PRIORITY_SEL 0x3
-#define BIT_PCIE_PRIORITY_SEL(x) (((x) & BIT_MASK_PCIE_PRIORITY_SEL) << BIT_SHIFT_PCIE_PRIORITY_SEL)
-#define BIT_GET_PCIE_PRIORITY_SEL(x) (((x) >> BIT_SHIFT_PCIE_PRIORITY_SEL) & BIT_MASK_PCIE_PRIORITY_SEL)
+#if (HALMAC_8814B_SUPPORT)
+/* 2 REG_HISR_7 (Offset 0x10CC) */
-/* 2 REG_COUNTER_CONTROL (Offset 0x11C4) */
+#define BIT_DATA_CPU_WDT_INT BIT(31)
+#define BIT_OFLD_TXDMA_ERR BIT(30)
+#define BIT_OFLD_TXDMA_FULL BIT(29)
+#define BIT_OFLD_RXDMA_OVR BIT(28)
+#endif
-#define BIT_SHIFT_COUNTER_BASE 16
-#define BIT_MASK_COUNTER_BASE 0x1fff
-#define BIT_COUNTER_BASE(x) (((x) & BIT_MASK_COUNTER_BASE) << BIT_SHIFT_COUNTER_BASE)
-#define BIT_GET_COUNTER_BASE(x) (((x) >> BIT_SHIFT_COUNTER_BASE) & BIT_MASK_COUNTER_BASE)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#define BIT_EN_RTS_REQ BIT(9)
-#define BIT_EN_EDCA_REQ BIT(8)
-#define BIT_EN_PTCL_REQ BIT(7)
-#define BIT_EN_SCH_REQ BIT(6)
-#define BIT_EN_USB_CNT BIT(5)
-#define BIT_EN_PCIE_CNT BIT(4)
-#define BIT_RQPN_CNT BIT(3)
-#define BIT_RDE_CNT BIT(2)
-#define BIT_TDE_CNT BIT(1)
-#define BIT_DIS_CNT BIT(0)
+/* 2 REG_FPGA_TAG (Offset 0x10CC) */
-/* 2 REG_COUNTER_TH (Offset 0x11C8) */
+#define BIT_WL_DSS_RSTN BIT(27)
-#define BIT_CNT_ALL_MACID BIT(31)
+#endif
-#define BIT_SHIFT_CNT_MACID 24
-#define BIT_MASK_CNT_MACID 0x7f
-#define BIT_CNT_MACID(x) (((x) & BIT_MASK_CNT_MACID) << BIT_SHIFT_CNT_MACID)
-#define BIT_GET_CNT_MACID(x) (((x) >> BIT_SHIFT_CNT_MACID) & BIT_MASK_CNT_MACID)
+#if (HALMAC_8814B_SUPPORT)
+/* 2 REG_HISR_7 (Offset 0x10CC) */
-#define BIT_SHIFT_AGG_VALUE2 16
-#define BIT_MASK_AGG_VALUE2 0x7f
-#define BIT_AGG_VALUE2(x) (((x) & BIT_MASK_AGG_VALUE2) << BIT_SHIFT_AGG_VALUE2)
-#define BIT_GET_AGG_VALUE2(x) (((x) >> BIT_SHIFT_AGG_VALUE2) & BIT_MASK_AGG_VALUE2)
+#define BIT_OFLD_RXDMA_ERR BIT(27)
+#endif
-#define BIT_SHIFT_AGG_VALUE1 8
-#define BIT_MASK_AGG_VALUE1 0x7f
-#define BIT_AGG_VALUE1(x) (((x) & BIT_MASK_AGG_VALUE1) << BIT_SHIFT_AGG_VALUE1)
-#define BIT_GET_AGG_VALUE1(x) (((x) >> BIT_SHIFT_AGG_VALUE1) & BIT_MASK_AGG_VALUE1)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+/* 2 REG_FPGA_TAG (Offset 0x10CC) */
-#define BIT_SHIFT_AGG_VALUE0 0
-#define BIT_MASK_AGG_VALUE0 0x7f
-#define BIT_AGG_VALUE0(x) (((x) & BIT_MASK_AGG_VALUE0) << BIT_SHIFT_AGG_VALUE0)
-#define BIT_GET_AGG_VALUE0(x) (((x) >> BIT_SHIFT_AGG_VALUE0) & BIT_MASK_AGG_VALUE0)
+#define BIT_WL_DSS_EN_CLK BIT(26)
+#endif
-/* 2 REG_COUNTER_SET (Offset 0x11CC) */
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_RTS_RST BIT(24)
-#define BIT_PTCL_RST BIT(23)
-#define BIT_SCH_RST BIT(22)
-#define BIT_EDCA_RST BIT(21)
-#define BIT_RQPN_RST BIT(20)
-#define BIT_USB_RST BIT(19)
-#define BIT_PCIE_RST BIT(18)
-#define BIT_RXDMA_RST BIT(17)
-#define BIT_TXDMA_RST BIT(16)
-#define BIT_EN_RTS_START BIT(8)
-#define BIT_EN_PTCL_START BIT(7)
-#define BIT_EN_SCH_START BIT(6)
-#define BIT_EN_EDCA_START BIT(5)
-#define BIT_EN_RQPN_START BIT(4)
-#define BIT_EN_USB_START BIT(3)
-#define BIT_EN_PCIE_START BIT(2)
-#define BIT_EN_RXDMA_START BIT(1)
-#define BIT_EN_TXDMA_START BIT(0)
+/* 2 REG_HISR_7 (Offset 0x10CC) */
-/* 2 REG_COUNTER_OVERFLOW (Offset 0x11D0) */
-
-#define BIT_RTS_OVF BIT(8)
-#define BIT_PTCL_OVF BIT(7)
-#define BIT_SCH_OVF BIT(6)
-#define BIT_EDCA_OVF BIT(5)
-#define BIT_RQPN_OVF BIT(4)
-#define BIT_USB_OVF BIT(3)
-#define BIT_PCIE_OVF BIT(2)
-#define BIT_RXDMA_OVF BIT(1)
-#define BIT_TXDMA_OVF BIT(0)
-
-/* 2 REG_TDE_LEN_TH (Offset 0x11D4) */
+#define BIT_OFLD_RXDMA_DES_UA BIT(26)
+#endif
-#define BIT_SHIFT_TXDMA_LEN_TH0 16
-#define BIT_MASK_TXDMA_LEN_TH0 0xffff
-#define BIT_TXDMA_LEN_TH0(x) (((x) & BIT_MASK_TXDMA_LEN_TH0) << BIT_SHIFT_TXDMA_LEN_TH0)
-#define BIT_GET_TXDMA_LEN_TH0(x) (((x) >> BIT_SHIFT_TXDMA_LEN_TH0) & BIT_MASK_TXDMA_LEN_TH0)
-
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_TXDMA_LEN_TH1 0
-#define BIT_MASK_TXDMA_LEN_TH1 0xffff
-#define BIT_TXDMA_LEN_TH1(x) (((x) & BIT_MASK_TXDMA_LEN_TH1) << BIT_SHIFT_TXDMA_LEN_TH1)
-#define BIT_GET_TXDMA_LEN_TH1(x) (((x) >> BIT_SHIFT_TXDMA_LEN_TH1) & BIT_MASK_TXDMA_LEN_TH1)
+/* 2 REG_FPGA_TAG (Offset 0x10CC) */
+#define BIT_WL_DSS_SPEED_EN BIT(25)
+#define BIT_WL_DSS_WIRE_SEL BIT(24)
-/* 2 REG_RDE_LEN_TH (Offset 0x11D8) */
+#define BIT_SHIFT_WL_DSS_RO_SEL 20
+#define BIT_MASK_WL_DSS_RO_SEL 0x7
+#define BIT_WL_DSS_RO_SEL(x) \
+ (((x) & BIT_MASK_WL_DSS_RO_SEL) << BIT_SHIFT_WL_DSS_RO_SEL)
+#define BITS_WL_DSS_RO_SEL (BIT_MASK_WL_DSS_RO_SEL << BIT_SHIFT_WL_DSS_RO_SEL)
+#define BIT_CLEAR_WL_DSS_RO_SEL(x) ((x) & (~BITS_WL_DSS_RO_SEL))
+#define BIT_GET_WL_DSS_RO_SEL(x) \
+ (((x) >> BIT_SHIFT_WL_DSS_RO_SEL) & BIT_MASK_WL_DSS_RO_SEL)
+#define BIT_SET_WL_DSS_RO_SEL(x, v) \
+ (BIT_CLEAR_WL_DSS_RO_SEL(x) | BIT_WL_DSS_RO_SEL(v))
+#endif
-#define BIT_SHIFT_RXDMA_LEN_TH0 16
-#define BIT_MASK_RXDMA_LEN_TH0 0xffff
-#define BIT_RXDMA_LEN_TH0(x) (((x) & BIT_MASK_RXDMA_LEN_TH0) << BIT_SHIFT_RXDMA_LEN_TH0)
-#define BIT_GET_RXDMA_LEN_TH0(x) (((x) >> BIT_SHIFT_RXDMA_LEN_TH0) & BIT_MASK_RXDMA_LEN_TH0)
+#if (HALMAC_8814B_SUPPORT)
+/* 2 REG_HISR_7 (Offset 0x10CC) */
-#define BIT_SHIFT_RXDMA_LEN_TH1 0
-#define BIT_MASK_RXDMA_LEN_TH1 0xffff
-#define BIT_RXDMA_LEN_TH1(x) (((x) & BIT_MASK_RXDMA_LEN_TH1) << BIT_SHIFT_RXDMA_LEN_TH1)
-#define BIT_GET_RXDMA_LEN_TH1(x) (((x) >> BIT_SHIFT_RXDMA_LEN_TH1) & BIT_MASK_RXDMA_LEN_TH1)
+#define BIT_TXDMAOK_CHANNEL_16 BIT(16)
+#define BIT_TXDMAOK_CHANNEL_13 BIT(13)
+#define BIT_TXDMAOK_CHANNEL_12 BIT(12)
+#define BIT_TXDMAOK_CHANNEL_11 BIT(11)
+#define BIT_TXDMAOK_CHANNEL_10 BIT(10)
+#define BIT_TXDMAOK_CHANNEL_9 BIT(9)
+#define BIT_TXDMAOK_CHANNEL_8 BIT(8)
+#define BIT_TXDMAOK_CHANNEL_7 BIT(7)
+#define BIT_TXDMAOK_CHANNEL_6 BIT(6)
+#define BIT_TXDMAOK_CHANNEL_5 BIT(5)
+#define BIT_TXDMAOK_CHANNEL_4 BIT(4)
+#endif
-/* 2 REG_PCIE_EXEC_TIME (Offset 0x11DC) */
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+/* 2 REG_FPGA_TAG (Offset 0x10CC) */
-#define BIT_SHIFT_COUNTER_INTERVAL_SEL 16
-#define BIT_MASK_COUNTER_INTERVAL_SEL 0x3
-#define BIT_COUNTER_INTERVAL_SEL(x) (((x) & BIT_MASK_COUNTER_INTERVAL_SEL) << BIT_SHIFT_COUNTER_INTERVAL_SEL)
-#define BIT_GET_COUNTER_INTERVAL_SEL(x) (((x) >> BIT_SHIFT_COUNTER_INTERVAL_SEL) & BIT_MASK_COUNTER_INTERVAL_SEL)
+#define BIT_SHIFT_FPGA_TAG 0
+#define BIT_MASK_FPGA_TAG 0xffffffffL
+#define BIT_FPGA_TAG(x) (((x) & BIT_MASK_FPGA_TAG) << BIT_SHIFT_FPGA_TAG)
+#define BITS_FPGA_TAG (BIT_MASK_FPGA_TAG << BIT_SHIFT_FPGA_TAG)
+#define BIT_CLEAR_FPGA_TAG(x) ((x) & (~BITS_FPGA_TAG))
+#define BIT_GET_FPGA_TAG(x) (((x) >> BIT_SHIFT_FPGA_TAG) & BIT_MASK_FPGA_TAG)
+#define BIT_SET_FPGA_TAG(x, v) (BIT_CLEAR_FPGA_TAG(x) | BIT_FPGA_TAG(v))
+#define BIT_SHIFT_WL_DSS_COUNT_OUT 0
+#define BIT_MASK_WL_DSS_COUNT_OUT 0xfffff
+#define BIT_WL_DSS_COUNT_OUT(x) \
+ (((x) & BIT_MASK_WL_DSS_COUNT_OUT) << BIT_SHIFT_WL_DSS_COUNT_OUT)
+#define BITS_WL_DSS_COUNT_OUT \
+ (BIT_MASK_WL_DSS_COUNT_OUT << BIT_SHIFT_WL_DSS_COUNT_OUT)
+#define BIT_CLEAR_WL_DSS_COUNT_OUT(x) ((x) & (~BITS_WL_DSS_COUNT_OUT))
+#define BIT_GET_WL_DSS_COUNT_OUT(x) \
+ (((x) >> BIT_SHIFT_WL_DSS_COUNT_OUT) & BIT_MASK_WL_DSS_COUNT_OUT)
+#define BIT_SET_WL_DSS_COUNT_OUT(x, v) \
+ (BIT_CLEAR_WL_DSS_COUNT_OUT(x) | BIT_WL_DSS_COUNT_OUT(v))
-#define BIT_SHIFT_PCIE_TRANS_DATA_TH1 0
-#define BIT_MASK_PCIE_TRANS_DATA_TH1 0xffff
-#define BIT_PCIE_TRANS_DATA_TH1(x) (((x) & BIT_MASK_PCIE_TRANS_DATA_TH1) << BIT_SHIFT_PCIE_TRANS_DATA_TH1)
-#define BIT_GET_PCIE_TRANS_DATA_TH1(x) (((x) >> BIT_SHIFT_PCIE_TRANS_DATA_TH1) & BIT_MASK_PCIE_TRANS_DATA_TH1)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_H2C_PKT_READADDR (Offset 0x10D0) */
+#define BIT_SHIFT_H2C_PKT_READADDR 0
+#define BIT_MASK_H2C_PKT_READADDR 0x3ffff
+#define BIT_H2C_PKT_READADDR(x) \
+ (((x) & BIT_MASK_H2C_PKT_READADDR) << BIT_SHIFT_H2C_PKT_READADDR)
+#define BITS_H2C_PKT_READADDR \
+ (BIT_MASK_H2C_PKT_READADDR << BIT_SHIFT_H2C_PKT_READADDR)
+#define BIT_CLEAR_H2C_PKT_READADDR(x) ((x) & (~BITS_H2C_PKT_READADDR))
+#define BIT_GET_H2C_PKT_READADDR(x) \
+ (((x) >> BIT_SHIFT_H2C_PKT_READADDR) & BIT_MASK_H2C_PKT_READADDR)
+#define BIT_SET_H2C_PKT_READADDR(x, v) \
+ (BIT_CLEAR_H2C_PKT_READADDR(x) | BIT_H2C_PKT_READADDR(v))
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_H2C_PKT_WRITEADDR (Offset 0x10D4) */
+#define BIT_SHIFT_H2C_PKT_WRITEADDR 0
+#define BIT_MASK_H2C_PKT_WRITEADDR 0x3ffff
+#define BIT_H2C_PKT_WRITEADDR(x) \
+ (((x) & BIT_MASK_H2C_PKT_WRITEADDR) << BIT_SHIFT_H2C_PKT_WRITEADDR)
+#define BITS_H2C_PKT_WRITEADDR \
+ (BIT_MASK_H2C_PKT_WRITEADDR << BIT_SHIFT_H2C_PKT_WRITEADDR)
+#define BIT_CLEAR_H2C_PKT_WRITEADDR(x) ((x) & (~BITS_H2C_PKT_WRITEADDR))
+#define BIT_GET_H2C_PKT_WRITEADDR(x) \
+ (((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR) & BIT_MASK_H2C_PKT_WRITEADDR)
+#define BIT_SET_H2C_PKT_WRITEADDR(x, v) \
+ (BIT_CLEAR_H2C_PKT_WRITEADDR(x) | BIT_H2C_PKT_WRITEADDR(v))
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+/* 2 REG_MEM_PWR_CRTL (Offset 0x10D8) */
-#define BIT_PORT4_RX_UCMD1_UAPSD0_OK_INT_EN BIT(31)
+#define BIT_MEM_BB_SD BIT(17)
+#define BIT_MEM_BB_DS BIT(16)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_MEM_PWR_CRTL (Offset 0x10D8) */
+#define BIT_MEM_DENG_LS BIT(13)
+#define BIT_MEM_DENG_DS BIT(12)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+#endif
-#define BIT_FS_CLI3_RX_UAPSDMD1_EN BIT(31)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_MEM_PWR_CRTL (Offset 0x10D8) */
+#define BIT_MEM_BT_DS BIT(10)
+#define BIT_MEM_SDIO_LS BIT(9)
+#define BIT_MEM_SDIO_DS BIT(8)
+#define BIT_MEM_USB_LS BIT(7)
+#define BIT_MEM_USB_DS BIT(6)
+#define BIT_MEM_PCI_LS BIT(5)
+#define BIT_MEM_PCI_DS BIT(4)
+#define BIT_MEM_WLMAC_LS BIT(3)
+#define BIT_MEM_WLMAC_DS BIT(2)
+#define BIT_MEM_WLMCU_LS BIT(1)
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+/* 2 REG_WL_DSS_CTRL1 (Offset 0x10D8) */
-#define BIT_PORT4_RX_UCMD0_UAPSD0_OK_INT_EN BIT(30)
+#define BIT_SHIFT_WL_DSS_DATA_IN 0
+#define BIT_MASK_WL_DSS_DATA_IN 0xfffff
+#define BIT_WL_DSS_DATA_IN(x) \
+ (((x) & BIT_MASK_WL_DSS_DATA_IN) << BIT_SHIFT_WL_DSS_DATA_IN)
+#define BITS_WL_DSS_DATA_IN \
+ (BIT_MASK_WL_DSS_DATA_IN << BIT_SHIFT_WL_DSS_DATA_IN)
+#define BIT_CLEAR_WL_DSS_DATA_IN(x) ((x) & (~BITS_WL_DSS_DATA_IN))
+#define BIT_GET_WL_DSS_DATA_IN(x) \
+ (((x) >> BIT_SHIFT_WL_DSS_DATA_IN) & BIT_MASK_WL_DSS_DATA_IN)
+#define BIT_SET_WL_DSS_DATA_IN(x, v) \
+ (BIT_CLEAR_WL_DSS_DATA_IN(x) | BIT_WL_DSS_DATA_IN(v))
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_MEM_PWR_CRTL (Offset 0x10D8) */
+#define BIT_MEM_WLMCU_DS BIT(0)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+#endif
-#define BIT_FS_CLI3_RX_UAPSDMD0_EN BIT(30)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#endif
+/* 2 REG_WL_DSS_STATUS1 (Offset 0x10DC) */
+#define BIT_WL_DSS_READY BIT(21)
+#define BIT_WL_DSS_WSORT_GO BIT(20)
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+/* 2 REG_FW_DRV_HANDSHAKE (Offset 0x10DC) */
-#define BIT_PORT4_TRIPKT_OK_INT_EN BIT(29)
+#define BIT_SHIFT_FW_DRV_HANDSHAKE 0
+#define BIT_MASK_FW_DRV_HANDSHAKE 0xffffffffL
+#define BIT_FW_DRV_HANDSHAKE(x) \
+ (((x) & BIT_MASK_FW_DRV_HANDSHAKE) << BIT_SHIFT_FW_DRV_HANDSHAKE)
+#define BITS_FW_DRV_HANDSHAKE \
+ (BIT_MASK_FW_DRV_HANDSHAKE << BIT_SHIFT_FW_DRV_HANDSHAKE)
+#define BIT_CLEAR_FW_DRV_HANDSHAKE(x) ((x) & (~BITS_FW_DRV_HANDSHAKE))
+#define BIT_GET_FW_DRV_HANDSHAKE(x) \
+ (((x) >> BIT_SHIFT_FW_DRV_HANDSHAKE) & BIT_MASK_FW_DRV_HANDSHAKE)
+#define BIT_SET_FW_DRV_HANDSHAKE(x, v) \
+ (BIT_CLEAR_FW_DRV_HANDSHAKE(x) | BIT_FW_DRV_HANDSHAKE(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FW_DBG0 (Offset 0x10E0) */
+#define BIT_SHIFT_FW_DBG0 0
+#define BIT_MASK_FW_DBG0 0xffffffffL
+#define BIT_FW_DBG0(x) (((x) & BIT_MASK_FW_DBG0) << BIT_SHIFT_FW_DBG0)
+#define BITS_FW_DBG0 (BIT_MASK_FW_DBG0 << BIT_SHIFT_FW_DBG0)
+#define BIT_CLEAR_FW_DBG0(x) ((x) & (~BITS_FW_DBG0))
+#define BIT_GET_FW_DBG0(x) (((x) >> BIT_SHIFT_FW_DBG0) & BIT_MASK_FW_DBG0)
+#define BIT_SET_FW_DBG0(x, v) (BIT_CLEAR_FW_DBG0(x) | BIT_FW_DBG0(v))
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+/* 2 REG_FW_DBG1 (Offset 0x10E4) */
-#define BIT_FS_CLI3_TRIGGER_PKT_EN BIT(29)
+#define BIT_SHIFT_FW_DBG1 0
+#define BIT_MASK_FW_DBG1 0xffffffffL
+#define BIT_FW_DBG1(x) (((x) & BIT_MASK_FW_DBG1) << BIT_SHIFT_FW_DBG1)
+#define BITS_FW_DBG1 (BIT_MASK_FW_DBG1 << BIT_SHIFT_FW_DBG1)
+#define BIT_CLEAR_FW_DBG1(x) ((x) & (~BITS_FW_DBG1))
+#define BIT_GET_FW_DBG1(x) (((x) >> BIT_SHIFT_FW_DBG1) & BIT_MASK_FW_DBG1)
+#define BIT_SET_FW_DBG1(x, v) (BIT_CLEAR_FW_DBG1(x) | BIT_FW_DBG1(v))
-#endif
+/* 2 REG_FW_DBG2 (Offset 0x10E8) */
+#define BIT_SHIFT_FW_DBG2 0
+#define BIT_MASK_FW_DBG2 0xffffffffL
+#define BIT_FW_DBG2(x) (((x) & BIT_MASK_FW_DBG2) << BIT_SHIFT_FW_DBG2)
+#define BITS_FW_DBG2 (BIT_MASK_FW_DBG2 << BIT_SHIFT_FW_DBG2)
+#define BIT_CLEAR_FW_DBG2(x) ((x) & (~BITS_FW_DBG2))
+#define BIT_GET_FW_DBG2(x) (((x) >> BIT_SHIFT_FW_DBG2) & BIT_MASK_FW_DBG2)
+#define BIT_SET_FW_DBG2(x, v) (BIT_CLEAR_FW_DBG2(x) | BIT_FW_DBG2(v))
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_FW_DBG3 (Offset 0x10EC) */
+#define BIT_SHIFT_FW_DBG3 0
+#define BIT_MASK_FW_DBG3 0xffffffffL
+#define BIT_FW_DBG3(x) (((x) & BIT_MASK_FW_DBG3) << BIT_SHIFT_FW_DBG3)
+#define BITS_FW_DBG3 (BIT_MASK_FW_DBG3 << BIT_SHIFT_FW_DBG3)
+#define BIT_CLEAR_FW_DBG3(x) ((x) & (~BITS_FW_DBG3))
+#define BIT_GET_FW_DBG3(x) (((x) >> BIT_SHIFT_FW_DBG3) & BIT_MASK_FW_DBG3)
+#define BIT_SET_FW_DBG3(x, v) (BIT_CLEAR_FW_DBG3(x) | BIT_FW_DBG3(v))
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+/* 2 REG_FW_DBG4 (Offset 0x10F0) */
-#define BIT_PORT4_RX_EOSP_OK_INT_EN BIT(28)
+#define BIT_SHIFT_FW_DBG4 0
+#define BIT_MASK_FW_DBG4 0xffffffffL
+#define BIT_FW_DBG4(x) (((x) & BIT_MASK_FW_DBG4) << BIT_SHIFT_FW_DBG4)
+#define BITS_FW_DBG4 (BIT_MASK_FW_DBG4 << BIT_SHIFT_FW_DBG4)
+#define BIT_CLEAR_FW_DBG4(x) ((x) & (~BITS_FW_DBG4))
+#define BIT_GET_FW_DBG4(x) (((x) >> BIT_SHIFT_FW_DBG4) & BIT_MASK_FW_DBG4)
+#define BIT_SET_FW_DBG4(x, v) (BIT_CLEAR_FW_DBG4(x) | BIT_FW_DBG4(v))
-#endif
+/* 2 REG_FW_DBG5 (Offset 0x10F4) */
+#define BIT_SHIFT_FW_DBG5 0
+#define BIT_MASK_FW_DBG5 0xffffffffL
+#define BIT_FW_DBG5(x) (((x) & BIT_MASK_FW_DBG5) << BIT_SHIFT_FW_DBG5)
+#define BITS_FW_DBG5 (BIT_MASK_FW_DBG5 << BIT_SHIFT_FW_DBG5)
+#define BIT_CLEAR_FW_DBG5(x) ((x) & (~BITS_FW_DBG5))
+#define BIT_GET_FW_DBG5(x) (((x) >> BIT_SHIFT_FW_DBG5) & BIT_MASK_FW_DBG5)
+#define BIT_SET_FW_DBG5(x, v) (BIT_CLEAR_FW_DBG5(x) | BIT_FW_DBG5(v))
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+/* 2 REG_FW_DBG6 (Offset 0x10F8) */
-#define BIT_FS_CLI3_EOSP_INT_EN BIT(28)
+#define BIT_SHIFT_FW_DBG6 0
+#define BIT_MASK_FW_DBG6 0xffffffffL
+#define BIT_FW_DBG6(x) (((x) & BIT_MASK_FW_DBG6) << BIT_SHIFT_FW_DBG6)
+#define BITS_FW_DBG6 (BIT_MASK_FW_DBG6 << BIT_SHIFT_FW_DBG6)
+#define BIT_CLEAR_FW_DBG6(x) ((x) & (~BITS_FW_DBG6))
+#define BIT_GET_FW_DBG6(x) (((x) >> BIT_SHIFT_FW_DBG6) & BIT_MASK_FW_DBG6)
+#define BIT_SET_FW_DBG6(x, v) (BIT_CLEAR_FW_DBG6(x) | BIT_FW_DBG6(v))
-#endif
+/* 2 REG_FW_DBG7 (Offset 0x10FC) */
+#define BIT_SHIFT_FW_DBG7 0
+#define BIT_MASK_FW_DBG7 0xffffffffL
+#define BIT_FW_DBG7(x) (((x) & BIT_MASK_FW_DBG7) << BIT_SHIFT_FW_DBG7)
+#define BITS_FW_DBG7 (BIT_MASK_FW_DBG7 << BIT_SHIFT_FW_DBG7)
+#define BIT_CLEAR_FW_DBG7(x) ((x) & (~BITS_FW_DBG7))
+#define BIT_GET_FW_DBG7(x) (((x) >> BIT_SHIFT_FW_DBG7) & BIT_MASK_FW_DBG7)
+#define BIT_SET_FW_DBG7(x, v) (BIT_CLEAR_FW_DBG7(x) | BIT_FW_DBG7(v))
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_CR_EXT (Offset 0x1100) */
+#define BIT_SHIFT_PHY_REQ_DELAY 24
+#define BIT_MASK_PHY_REQ_DELAY 0xf
+#define BIT_PHY_REQ_DELAY(x) \
+ (((x) & BIT_MASK_PHY_REQ_DELAY) << BIT_SHIFT_PHY_REQ_DELAY)
+#define BITS_PHY_REQ_DELAY (BIT_MASK_PHY_REQ_DELAY << BIT_SHIFT_PHY_REQ_DELAY)
+#define BIT_CLEAR_PHY_REQ_DELAY(x) ((x) & (~BITS_PHY_REQ_DELAY))
+#define BIT_GET_PHY_REQ_DELAY(x) \
+ (((x) >> BIT_SHIFT_PHY_REQ_DELAY) & BIT_MASK_PHY_REQ_DELAY)
+#define BIT_SET_PHY_REQ_DELAY(x, v) \
+ (BIT_CLEAR_PHY_REQ_DELAY(x) | BIT_PHY_REQ_DELAY(v))
+
+#define BIT_SPD_DOWN BIT(16)
+
+#define BIT_SHIFT_NETYPE4 4
+#define BIT_MASK_NETYPE4 0x3
+#define BIT_NETYPE4(x) (((x) & BIT_MASK_NETYPE4) << BIT_SHIFT_NETYPE4)
+#define BITS_NETYPE4 (BIT_MASK_NETYPE4 << BIT_SHIFT_NETYPE4)
+#define BIT_CLEAR_NETYPE4(x) ((x) & (~BITS_NETYPE4))
+#define BIT_GET_NETYPE4(x) (((x) >> BIT_SHIFT_NETYPE4) & BIT_MASK_NETYPE4)
+#define BIT_SET_NETYPE4(x, v) (BIT_CLEAR_NETYPE4(x) | BIT_NETYPE4(v))
+
+#define BIT_SHIFT_NETYPE3 2
+#define BIT_MASK_NETYPE3 0x3
+#define BIT_NETYPE3(x) (((x) & BIT_MASK_NETYPE3) << BIT_SHIFT_NETYPE3)
+#define BITS_NETYPE3 (BIT_MASK_NETYPE3 << BIT_SHIFT_NETYPE3)
+#define BIT_CLEAR_NETYPE3(x) ((x) & (~BITS_NETYPE3))
+#define BIT_GET_NETYPE3(x) (((x) >> BIT_SHIFT_NETYPE3) & BIT_MASK_NETYPE3)
+#define BIT_SET_NETYPE3(x, v) (BIT_CLEAR_NETYPE3(x) | BIT_NETYPE3(v))
+
+#define BIT_SHIFT_NETYPE2 0
+#define BIT_MASK_NETYPE2 0x3
+#define BIT_NETYPE2(x) (((x) & BIT_MASK_NETYPE2) << BIT_SHIFT_NETYPE2)
+#define BITS_NETYPE2 (BIT_MASK_NETYPE2 << BIT_SHIFT_NETYPE2)
+#define BIT_CLEAR_NETYPE2(x) ((x) & (~BITS_NETYPE2))
+#define BIT_GET_NETYPE2(x) (((x) >> BIT_SHIFT_NETYPE2) & BIT_MASK_NETYPE2)
+#define BIT_SET_NETYPE2(x, v) (BIT_CLEAR_NETYPE2(x) | BIT_NETYPE2(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_TC9_CTRL (Offset 0x1104) */
+
+#define BIT_TC9INT_EN BIT(26)
+#define BIT_TC9MODE BIT(25)
+#define BIT_TC9EN BIT(24)
+
+#define BIT_SHIFT_TC9DATA 0
+#define BIT_MASK_TC9DATA 0xffffff
+#define BIT_TC9DATA(x) (((x) & BIT_MASK_TC9DATA) << BIT_SHIFT_TC9DATA)
+#define BITS_TC9DATA (BIT_MASK_TC9DATA << BIT_SHIFT_TC9DATA)
+#define BIT_CLEAR_TC9DATA(x) ((x) & (~BITS_TC9DATA))
+#define BIT_GET_TC9DATA(x) (((x) >> BIT_SHIFT_TC9DATA) & BIT_MASK_TC9DATA)
+#define BIT_SET_TC9DATA(x, v) (BIT_CLEAR_TC9DATA(x) | BIT_TC9DATA(v))
+
+/* 2 REG_TC10_CTRL (Offset 0x1108) */
+
+#define BIT_TC10INT_EN BIT(26)
+#define BIT_TC10MODE BIT(25)
+#define BIT_TC10EN BIT(24)
+
+#define BIT_SHIFT_TC10DATA 0
+#define BIT_MASK_TC10DATA 0xffffff
+#define BIT_TC10DATA(x) (((x) & BIT_MASK_TC10DATA) << BIT_SHIFT_TC10DATA)
+#define BITS_TC10DATA (BIT_MASK_TC10DATA << BIT_SHIFT_TC10DATA)
+#define BIT_CLEAR_TC10DATA(x) ((x) & (~BITS_TC10DATA))
+#define BIT_GET_TC10DATA(x) (((x) >> BIT_SHIFT_TC10DATA) & BIT_MASK_TC10DATA)
+#define BIT_SET_TC10DATA(x, v) (BIT_CLEAR_TC10DATA(x) | BIT_TC10DATA(v))
+
+/* 2 REG_TC11_CTRL (Offset 0x110C) */
+
+#define BIT_TC11INT_EN BIT(26)
+#define BIT_TC11MODE BIT(25)
+#define BIT_TC11EN BIT(24)
+
+#define BIT_SHIFT_TC11DATA 0
+#define BIT_MASK_TC11DATA 0xffffff
+#define BIT_TC11DATA(x) (((x) & BIT_MASK_TC11DATA) << BIT_SHIFT_TC11DATA)
+#define BITS_TC11DATA (BIT_MASK_TC11DATA << BIT_SHIFT_TC11DATA)
+#define BIT_CLEAR_TC11DATA(x) ((x) & (~BITS_TC11DATA))
+#define BIT_GET_TC11DATA(x) (((x) >> BIT_SHIFT_TC11DATA) & BIT_MASK_TC11DATA)
+#define BIT_SET_TC11DATA(x, v) (BIT_CLEAR_TC11DATA(x) | BIT_TC11DATA(v))
+
+/* 2 REG_TC12_CTRL (Offset 0x1110) */
+
+#define BIT_TC12INT_EN BIT(26)
+#define BIT_TC12MODE BIT(25)
+#define BIT_TC12EN BIT(24)
+#define BIT_P2P_PWROFF_NOA2_ERLY_INT BIT(22)
+#define BIT_P2P_PWROFF_NOA1_ERLY_INT BIT(21)
+#define BIT_P2P_PWROFF_NOA0_ERLY_INT BIT(20)
+
+#define BIT_SHIFT_TC12DATA 0
+#define BIT_MASK_TC12DATA 0xffffff
+#define BIT_TC12DATA(x) (((x) & BIT_MASK_TC12DATA) << BIT_SHIFT_TC12DATA)
+#define BITS_TC12DATA (BIT_MASK_TC12DATA << BIT_SHIFT_TC12DATA)
+#define BIT_CLEAR_TC12DATA(x) ((x) & (~BITS_TC12DATA))
+#define BIT_GET_TC12DATA(x) (((x) >> BIT_SHIFT_TC12DATA) & BIT_MASK_TC12DATA)
+#define BIT_SET_TC12DATA(x, v) (BIT_CLEAR_TC12DATA(x) | BIT_TC12DATA(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+/* 2 REG_FWFF (Offset 0x1114) */
-#define BIT_PORT3_RX_UCMD1_UAPSD0_OK_INT_EN BIT(27)
+#define BIT_SHIFT_PKTNUM_TH 24
+#define BIT_MASK_PKTNUM_TH 0xff
+#define BIT_PKTNUM_TH(x) (((x) & BIT_MASK_PKTNUM_TH) << BIT_SHIFT_PKTNUM_TH)
+#define BITS_PKTNUM_TH (BIT_MASK_PKTNUM_TH << BIT_SHIFT_PKTNUM_TH)
+#define BIT_CLEAR_PKTNUM_TH(x) ((x) & (~BITS_PKTNUM_TH))
+#define BIT_GET_PKTNUM_TH(x) (((x) >> BIT_SHIFT_PKTNUM_TH) & BIT_MASK_PKTNUM_TH)
+#define BIT_SET_PKTNUM_TH(x, v) (BIT_CLEAR_PKTNUM_TH(x) | BIT_PKTNUM_TH(v))
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+/* 2 REG_FWFF (Offset 0x1114) */
-#define BIT_FS_CLI2_RX_UAPSDMD1_EN BIT(27)
+#define BIT_SHIFT_PKTNUM_TH_V1 24
+#define BIT_MASK_PKTNUM_TH_V1 0xff
+#define BIT_PKTNUM_TH_V1(x) \
+ (((x) & BIT_MASK_PKTNUM_TH_V1) << BIT_SHIFT_PKTNUM_TH_V1)
+#define BITS_PKTNUM_TH_V1 (BIT_MASK_PKTNUM_TH_V1 << BIT_SHIFT_PKTNUM_TH_V1)
+#define BIT_CLEAR_PKTNUM_TH_V1(x) ((x) & (~BITS_PKTNUM_TH_V1))
+#define BIT_GET_PKTNUM_TH_V1(x) \
+ (((x) >> BIT_SHIFT_PKTNUM_TH_V1) & BIT_MASK_PKTNUM_TH_V1)
+#define BIT_SET_PKTNUM_TH_V1(x, v) \
+ (BIT_CLEAR_PKTNUM_TH_V1(x) | BIT_PKTNUM_TH_V1(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_FWFF (Offset 0x1114) */
+#define BIT_SHIFT_TIMER_TH 16
+#define BIT_MASK_TIMER_TH 0xff
+#define BIT_TIMER_TH(x) (((x) & BIT_MASK_TIMER_TH) << BIT_SHIFT_TIMER_TH)
+#define BITS_TIMER_TH (BIT_MASK_TIMER_TH << BIT_SHIFT_TIMER_TH)
+#define BIT_CLEAR_TIMER_TH(x) ((x) & (~BITS_TIMER_TH))
+#define BIT_GET_TIMER_TH(x) (((x) >> BIT_SHIFT_TIMER_TH) & BIT_MASK_TIMER_TH)
+#define BIT_SET_TIMER_TH(x, v) (BIT_CLEAR_TIMER_TH(x) | BIT_TIMER_TH(v))
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+#endif
-#define BIT_PORT3_RX_UCMD0_UAPSD0_OK_INT_EN BIT(26)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT)
-#endif
+/* 2 REG_FWFF (Offset 0x1114) */
+#define BIT_EN_RXDMA_ALIGN_V1 BIT(1)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+/* 2 REG_FWFF (Offset 0x1114) */
-#define BIT_FS_CLI2_RX_UAPSDMD0_EN BIT(26)
+#define BIT_SHIFT_RXPKT1ENADDR 0
+#define BIT_MASK_RXPKT1ENADDR 0xffff
+#define BIT_RXPKT1ENADDR(x) \
+ (((x) & BIT_MASK_RXPKT1ENADDR) << BIT_SHIFT_RXPKT1ENADDR)
+#define BITS_RXPKT1ENADDR (BIT_MASK_RXPKT1ENADDR << BIT_SHIFT_RXPKT1ENADDR)
+#define BIT_CLEAR_RXPKT1ENADDR(x) ((x) & (~BITS_RXPKT1ENADDR))
+#define BIT_GET_RXPKT1ENADDR(x) \
+ (((x) >> BIT_SHIFT_RXPKT1ENADDR) & BIT_MASK_RXPKT1ENADDR)
+#define BIT_SET_RXPKT1ENADDR(x, v) \
+ (BIT_CLEAR_RXPKT1ENADDR(x) | BIT_RXPKT1ENADDR(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_FWFF (Offset 0x1114) */
+#define BIT_EN_TXDMA_ALIGN_V1 BIT(0)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+#endif
-#define BIT_PORT3_TRIPKT_OK_INT_EN BIT(25)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_FE2IMR (Offset 0x1120) */
+#define BIT__FE4ISR__IND_MSK BIT(29)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+/* 2 REG_FE2IMR (Offset 0x1120) */
-#define BIT_FS_CLI2_TRIGGER_PKT_EN BIT(25)
+#define BIT_FS_TXSC_DESC_DONE_INT_EN BIT(28)
+#define BIT_FS_TXSC_BKDONE_INT_EN BIT(27)
+#define BIT_FS_TXSC_BEDONE_INT_EN BIT(26)
+#define BIT_FS_TXSC_VIDONE_INT_EN BIT(25)
+#define BIT_FS_TXSC_VODONE_INT_EN BIT(24)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_FE2IMR (Offset 0x1120) */
+#define BIT_FS_ATIM_MB7_INT_EN BIT(23)
+#define BIT_FS_ATIM_MB6_INT_EN BIT(22)
+#define BIT_FS_ATIM_MB5_INT_EN BIT(21)
+#define BIT_FS_ATIM_MB4_INT_EN BIT(20)
+#define BIT_FS_ATIM_MB3_INT_EN BIT(19)
+#define BIT_FS_ATIM_MB2_INT_EN BIT(18)
+#define BIT_FS_ATIM_MB1_INT_EN BIT(17)
+#define BIT_FS_ATIM_MB0_INT_EN BIT(16)
+#define BIT_FS_TBTT4INT_EN BIT(11)
+#define BIT_FS_TBTT3INT_EN BIT(10)
+#define BIT_FS_TBTT2INT_EN BIT(9)
+#define BIT_FS_TBTT1INT_EN BIT(8)
+#define BIT_FS_TBTT0_MB7INT_EN BIT(7)
+#define BIT_FS_TBTT0_MB6INT_EN BIT(6)
+#define BIT_FS_TBTT0_MB5INT_EN BIT(5)
+#define BIT_FS_TBTT0_MB4INT_EN BIT(4)
+#define BIT_FS_TBTT0_MB3INT_EN BIT(3)
+#define BIT_FS_TBTT0_MB2INT_EN BIT(2)
+#define BIT_FS_TBTT0_MB1INT_EN BIT(1)
+#define BIT_FS_TBTT0_INT_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+/* 2 REG_FE2ISR (Offset 0x1124) */
-#define BIT_PORT3_RX_EOSP_OK_INT_EN BIT(24)
+#define BIT__FE4ISR__IND_INT BIT(29)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+/* 2 REG_FE2ISR (Offset 0x1124) */
-#define BIT_FS_CLI2_EOSP_INT_EN BIT(24)
+#define BIT_FS_TXSC_DESC_DONE_INT BIT(28)
+#define BIT_FS_TXSC_BKDONE_INT BIT(27)
+#define BIT_FS_TXSC_BEDONE_INT BIT(26)
+#define BIT_FS_TXSC_VIDONE_INT BIT(25)
+#define BIT_FS_TXSC_VODONE_INT BIT(24)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_FE2ISR (Offset 0x1124) */
+#define BIT_FS_ATIM_MB7_INT BIT(23)
+#define BIT_FS_ATIM_MB6_INT BIT(22)
+#define BIT_FS_ATIM_MB5_INT BIT(21)
+#define BIT_FS_ATIM_MB4_INT BIT(20)
+#define BIT_FS_ATIM_MB3_INT BIT(19)
+#define BIT_FS_ATIM_MB2_INT BIT(18)
+#define BIT_FS_ATIM_MB1_INT BIT(17)
+#define BIT_FS_ATIM_MB0_INT BIT(16)
+#define BIT_FS_TBTT4INT BIT(11)
+#define BIT_FS_TBTT3INT BIT(10)
+#define BIT_FS_TBTT2INT BIT(9)
+#define BIT_FS_TBTT1INT BIT(8)
+#define BIT_FS_TBTT0_MB7INT BIT(7)
+#define BIT_FS_TBTT0_MB6INT BIT(6)
+#define BIT_FS_TBTT0_MB5INT BIT(5)
+#define BIT_FS_TBTT0_MB4INT BIT(4)
+#define BIT_FS_TBTT0_MB3INT BIT(3)
+#define BIT_FS_TBTT0_MB2INT BIT(2)
+#define BIT_FS_TBTT0_MB1INT BIT(1)
+#define BIT_FS_TBTT0_INT BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+/* 2 REG_FE3IMR (Offset 0x1128) */
-#define BIT_PORT2_RX_UCMD1_UAPSD0_OK_INT_EN BIT(23)
+#define BIT_FS_BCNELY4_AGGR_INT_EN BIT(31)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+/* 2 REG_FE3IMR (Offset 0x1128) */
-#define BIT_FS_CLI1_RX_UAPSDMD1_EN BIT(23)
+#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT__EN BIT(31)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_FE3IMR (Offset 0x1128) */
+#define BIT_FS_BCNELY3_AGGR_INT_EN BIT(30)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+#endif
-#define BIT_PORT2_RX_UCMD0_UAPSD0_OK_INT_EN BIT(22)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_FE3IMR (Offset 0x1128) */
+#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT__EN BIT(30)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+/* 2 REG_FE3IMR (Offset 0x1128) */
-#define BIT_FS_CLI1_RX_UAPSDMD0_EN BIT(22)
+#define BIT_FS_BCNELY2_AGGR_INT_EN BIT(29)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_FE3IMR (Offset 0x1128) */
+#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT__EN BIT(29)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+#endif
-#define BIT_PORT2_TRIPKT_OK_INT_EN BIT(21)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#endif
+/* 2 REG_FE3IMR (Offset 0x1128) */
+#define BIT_FS_BCNELY1_AGGR_INT_EN BIT(28)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+/* 2 REG_FE3IMR (Offset 0x1128) */
-#define BIT_FS_CLI1_TRIGGER_PKT_EN BIT(21)
+#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT__EN BIT(28)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_FE3IMR (Offset 0x1128) */
+#define BIT_FS_BCNDMA4_INT_EN BIT(27)
+#define BIT_FS_BCNDMA3_INT_EN BIT(26)
+#define BIT_FS_BCNDMA2_INT_EN BIT(25)
+#define BIT_FS_BCNDMA1_INT_EN BIT(24)
+#define BIT_FS_BCNDMA0_MB7_INT_EN BIT(23)
+#define BIT_FS_BCNDMA0_MB6_INT_EN BIT(22)
+#define BIT_FS_BCNDMA0_MB5_INT_EN BIT(21)
+#define BIT_FS_BCNDMA0_MB4_INT_EN BIT(20)
+#define BIT_FS_BCNDMA0_MB3_INT_EN BIT(19)
+#define BIT_FS_BCNDMA0_MB2_INT_EN BIT(18)
+#define BIT_FS_BCNDMA0_MB1_INT_EN BIT(17)
+#define BIT_FS_BCNDMA0_INT_EN BIT(16)
+#define BIT_FS_MTI_BCNIVLEAR_INT__EN BIT(15)
+#define BIT_FS_BCNERLY4_INT_EN BIT(11)
+#define BIT_FS_BCNERLY3_INT_EN BIT(10)
+#define BIT_FS_BCNERLY2_INT_EN BIT(9)
+#define BIT_FS_BCNERLY1_INT_EN BIT(8)
+#define BIT_FS_BCNERLY0_MB7INT_EN BIT(7)
+#define BIT_FS_BCNERLY0_MB6INT_EN BIT(6)
+#define BIT_FS_BCNERLY0_MB5INT_EN BIT(5)
+#define BIT_FS_BCNERLY0_MB4INT_EN BIT(4)
+#define BIT_FS_BCNERLY0_MB3INT_EN BIT(3)
+#define BIT_FS_BCNERLY0_MB2INT_EN BIT(2)
+#define BIT_FS_BCNERLY0_MB1INT_EN BIT(1)
+#define BIT_FS_BCNERLY0_INT_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+/* 2 REG_FE3ISR (Offset 0x112C) */
-#define BIT_PORT2_RX_EOSP_OK_INT_EN BIT(20)
+#define BIT_FS_BCNELY4_AGGR_INT BIT(31)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+/* 2 REG_FE3ISR (Offset 0x112C) */
-#define BIT_FS_CLI1_EOSP_INT_EN BIT(20)
+#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT BIT(31)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_FE3ISR (Offset 0x112C) */
+#define BIT_FS_BCNELY3_AGGR_INT BIT(30)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+#endif
-#define BIT_PORT1_RX_UCMD1_UAPSD0_OK_INT_EN BIT(19)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_FE3ISR (Offset 0x112C) */
+#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT BIT(30)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+/* 2 REG_FE3ISR (Offset 0x112C) */
-#define BIT_FS_CLI0_RX_UAPSDMD1_EN BIT(19)
+#define BIT_FS_BCNELY2_AGGR_INT BIT(29)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_FE3ISR (Offset 0x112C) */
+#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT BIT(29)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+#endif
-#define BIT_PORT1_RX_UCMD0_UAPSD0_OK_INT_EN BIT(18)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#endif
+/* 2 REG_FE3ISR (Offset 0x112C) */
+#define BIT_FS_BCNELY1_AGGR_INT BIT(28)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+/* 2 REG_FE3ISR (Offset 0x112C) */
-#define BIT_FS_CLI0_RX_UAPSDMD0_EN BIT(18)
+#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT BIT(28)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_FE3ISR (Offset 0x112C) */
+#define BIT_FS_BCNDMA4_INT BIT(27)
+#define BIT_FS_BCNDMA3_INT BIT(26)
+#define BIT_FS_BCNDMA2_INT BIT(25)
+#define BIT_FS_BCNDMA1_INT BIT(24)
+#define BIT_FS_BCNDMA0_MB7_INT BIT(23)
+#define BIT_FS_BCNDMA0_MB6_INT BIT(22)
+#define BIT_FS_BCNDMA0_MB5_INT BIT(21)
+#define BIT_FS_BCNDMA0_MB4_INT BIT(20)
+#define BIT_FS_BCNDMA0_MB3_INT BIT(19)
+#define BIT_FS_BCNDMA0_MB2_INT BIT(18)
+#define BIT_FS_BCNDMA0_MB1_INT BIT(17)
+#define BIT_FS_BCNDMA0_INT BIT(16)
+#define BIT_FS_MTI_BCNIVLEAR_INT BIT(15)
+#define BIT_FS_BCNERLY4_INT BIT(11)
+#define BIT_FS_BCNERLY3_INT BIT(10)
+#define BIT_FS_BCNERLY2_INT BIT(9)
+#define BIT_FS_BCNERLY1_INT BIT(8)
+#define BIT_FS_BCNERLY0_MB7INT BIT(7)
+#define BIT_FS_BCNERLY0_MB6INT BIT(6)
+#define BIT_FS_BCNERLY0_MB5INT BIT(5)
+#define BIT_FS_BCNERLY0_MB4INT BIT(4)
+#define BIT_FS_BCNERLY0_MB3INT BIT(3)
+#define BIT_FS_BCNERLY0_MB2INT BIT(2)
+#define BIT_FS_BCNERLY0_MB1INT BIT(1)
+#define BIT_FS_BCNERLY0_INT BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+/* 2 REG_FE4IMR (Offset 0x1130) */
-#define BIT_PORT1_TRIPKT_OK_INT_EN BIT(17)
+#define BIT_PORT4_PKTIN_INT_EN BIT(19)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FE4IMR (Offset 0x1130) */
+#define BIT_FS_CLI3_TXPKTIN_INT_EN BIT(19)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+#endif
-#define BIT_FS_CLI0_TRIGGER_PKT_EN BIT(17)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#endif
+/* 2 REG_FE4IMR (Offset 0x1130) */
+#define BIT_PORT3_PKTIN_INT_EN BIT(18)
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+/* 2 REG_FE4IMR (Offset 0x1130) */
-#define BIT_PORT1_RX_EOSP_OK_INT_EN BIT(16)
+#define BIT_FS_CLI2_TXPKTIN_INT_EN BIT(18)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FE4IMR (Offset 0x1130) */
+#define BIT_PORT2_PKTIN_INT_EN BIT(17)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+#endif
-#define BIT_FS_CLI0_EOSP_INT_EN BIT(16)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_FE4IMR (Offset 0x1130) */
+#define BIT_FS_CLI1_TXPKTIN_INT_EN BIT(17)
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+/* 2 REG_FE4IMR (Offset 0x1130) */
-#define BIT_NOA2_TSFT_BIT32_TOGGLE_INT_EN BIT(9)
+#define BIT_PORT1_PKTIN_INT_EN BIT(16)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FE4IMR (Offset 0x1130) */
+#define BIT_FS_CLI0_TXPKTIN_INT_EN BIT(16)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+#endif
-#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_EN BIT(9)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#endif
+/* 2 REG_FE4IMR (Offset 0x1130) */
+#define BIT_PORT4_RXUCMD0_OK_INT_EN BIT(15)
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+/* 2 REG_FE4IMR (Offset 0x1130) */
-#define BIT_NOA1_TSFT_BIT32_TOGGLE_INT_EN BIT(8)
+#define BIT_FS_CLI3_RX_UMD0_INT_EN BIT(15)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FE4IMR (Offset 0x1130) */
+#define BIT_PORT4_RXUCMD1_OK_INT_EN BIT(14)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+#endif
-#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_EN BIT(8)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_FE4IMR (Offset 0x1130) */
+#define BIT_FS_CLI3_RX_UMD1_INT_EN BIT(14)
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+/* 2 REG_FE4IMR (Offset 0x1130) */
-#define BIT_PORT4_TX_NULL1_DONE_INT_EN BIT(7)
+#define BIT_PORT4_RXBCMD0_OK_INT_EN BIT(13)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FE4IMR (Offset 0x1130) */
+#define BIT_FS_CLI3_RX_BMD0_INT_EN BIT(13)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+#endif
-#define BIT_FS_CLI3_TX_NULL1_INT_EN BIT(7)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#endif
+/* 2 REG_FE4IMR (Offset 0x1130) */
+#define BIT_PORT4_RXBCMD1_OK_INT_EN BIT(12)
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+/* 2 REG_FE4IMR (Offset 0x1130) */
-#define BIT_PORT4_TX_NULL0_DONE_INT_EN BIT(6)
+#define BIT_FS_CLI3_RX_BMD1_INT_EN BIT(12)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FE4IMR (Offset 0x1130) */
+#define BIT_PORT3_RXUCMD0_OK_INT_EN BIT(11)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+#endif
-#define BIT_FS_CLI3_TX_NULL0_INT_EN BIT(6)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_FE4IMR (Offset 0x1130) */
+#define BIT_FS_CLI2_RX_UMD0_INT_EN BIT(11)
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+/* 2 REG_FE4IMR (Offset 0x1130) */
-#define BIT_PORT3_TX_NULL1_DONE_INT_EN BIT(5)
+#define BIT_PORT3_RXUCMD1_OK_INT_EN BIT(10)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FE4IMR (Offset 0x1130) */
+#define BIT_FS_CLI2_RX_UMD1_INT_EN BIT(10)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+#endif
-#define BIT_FS_CLI2_TX_NULL1_INT_EN BIT(5)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#endif
+/* 2 REG_FE4IMR (Offset 0x1130) */
+#define BIT_PORT3_RXBCMD0_OK_INT_EN BIT(9)
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+/* 2 REG_FE4IMR (Offset 0x1130) */
-#define BIT_PORT3_TX_NULL0_DONE_INT_EN BIT(4)
+#define BIT_FS_CLI2_RX_BMD0_INT_EN BIT(9)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FE4IMR (Offset 0x1130) */
+#define BIT_PORT3_RXBCMD1_OK_INT_EN BIT(8)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+#endif
-#define BIT_FS_CLI2_TX_NULL0_INT_EN BIT(4)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_FE4IMR (Offset 0x1130) */
+#define BIT_FS_CLI2_RX_BMD1_INT_EN BIT(8)
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+/* 2 REG_FE4IMR (Offset 0x1130) */
-#define BIT_PORT2_TX_NULL1_DONE_INT_EN BIT(3)
+#define BIT_PORT2_RXUCMD0_OK_INT_EN BIT(7)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FE4IMR (Offset 0x1130) */
+#define BIT_FS_CLI1_RX_UMD0_INT_EN BIT(7)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+#endif
-#define BIT_FS_CLI1_TX_NULL1_INT_EN BIT(3)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#endif
+/* 2 REG_FE4IMR (Offset 0x1130) */
+#define BIT_PORT2_RXUCMD1_OK_INT_EN BIT(6)
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+/* 2 REG_FE4IMR (Offset 0x1130) */
-#define BIT_PORT2_TX_NULL0_DONE_INT_EN BIT(2)
+#define BIT_FS_CLI1_RX_UMD1_INT_EN BIT(6)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FE4IMR (Offset 0x1130) */
+#define BIT_PORT2_RXBCMD0_OK_INT_EN BIT(5)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+#endif
-#define BIT_FS_CLI1_TX_NULL0_INT_EN BIT(2)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_FE4IMR (Offset 0x1130) */
+#define BIT_FS_CLI1_RX_BMD0_INT_EN BIT(5)
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+/* 2 REG_FE4IMR (Offset 0x1130) */
-#define BIT_PORT1_TX_NULL1_DONE_INT_EN BIT(1)
+#define BIT_PORT2_RXBCMD1_OK_INT_EN BIT(4)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FE4IMR (Offset 0x1130) */
+
+#define BIT_FS_CLI1_RX_BMD1_INT_EN BIT(4)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4IMR (Offset 0x1130) */
+
+#define BIT_PORT1_RXUCMD0_OK_INT_EN BIT(3)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4IMR (Offset 0x1130) */
+
+#define BIT_FS_CLI0_RX_UMD0_INT_EN BIT(3)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4IMR (Offset 0x1130) */
+
+#define BIT_PORT1_RXUCMD1_OK_INT_EN BIT(2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FE4IMR (Offset 0x1130) */
+
+#define BIT_FS_DMEM1_WPTR_UPDATE_INT_EN BIT(2)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4IMR (Offset 0x1130) */
+
+#define BIT_FS_CLI0_RX_UMD1_INT_EN BIT(2)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4IMR (Offset 0x1130) */
+
+#define BIT_PORT1_RXBCMD0_OK_INT_EN BIT(1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4IMR (Offset 0x1130) */
+
+#define BIT_FS_CLI0_RX_BMD0_INT_EN BIT(1)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4IMR (Offset 0x1130) */
+
+#define BIT_PORT1_RXBCMD1_OK_INT_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4IMR (Offset 0x1130) */
+
+#define BIT_FS_CLI0_RX_BMD1_INT_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_PORT4_PKTIN_INT BIT(19)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_FS_CLI3_TXPKTIN_INT BIT(19)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_PORT3_PKTIN_INT BIT(18)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_FS_CLI2_TXPKTIN_INT BIT(18)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_PORT2_PKTIN_INT BIT(17)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_FS_CLI1_TXPKTIN_INT BIT(17)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_PORT1_PKTIN_INT BIT(16)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_FS_CLI0_TXPKTIN_INT BIT(16)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_PORT4_RXUCMD0_OK_INT BIT(15)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_FS_CLI3_RX_UMD0_INT BIT(15)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_PORT4_RXUCMD1_OK_INT BIT(14)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_FS_CLI3_RX_UMD1_INT BIT(14)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_PORT4_RXBCMD0_OK_INT BIT(13)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_FS_CLI3_RX_BMD0_INT BIT(13)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_PORT4_RXBCMD1_OK_INT BIT(12)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_FS_CLI3_RX_BMD1_INT BIT(12)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_PORT3_RXUCMD0_OK_INT BIT(11)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_FS_CLI2_RX_UMD0_INT BIT(11)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_PORT3_RXUCMD1_OK_INT BIT(10)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_FS_CLI2_RX_UMD1_INT BIT(10)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_PORT3_RXBCMD0_OK_INT BIT(9)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_FS_CLI2_RX_BMD0_INT BIT(9)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_PORT3_RXBCMD1_OK_INT BIT(8)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_FS_CLI2_RX_BMD1_INT BIT(8)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_PORT2_RXUCMD0_OK_INT BIT(7)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_FS_CLI1_RX_UMD0_INT BIT(7)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_PORT2_RXUCMD1_OK_INT BIT(6)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_FS_CLI1_RX_UMD1_INT BIT(6)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_PORT2_RXBCMD0_OK_INT BIT(5)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_FS_CLI1_RX_BMD0_INT BIT(5)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_PORT2_RXBCMD1_OK_INT BIT(4)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_FS_CLI1_RX_BMD1_INT BIT(4)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_PORT1_RXUCMD0_OK_INT BIT(3)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_FS_CLI0_RX_UMD0_INT BIT(3)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_PORT1_RXUCMD1_OK_INT BIT(2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_FS_DMEM1_WPTR_UPDATE_INT BIT(2)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_FS_CLI0_RX_UMD1_INT BIT(2)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_PORT1_RXBCMD0_OK_INT BIT(1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_FS_CLI0_RX_BMD0_INT BIT(1)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_PORT1_RXBCMD1_OK_INT BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FE4ISR (Offset 0x1134) */
+
+#define BIT_FS_CLI0_RX_BMD1_INT BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT1IMR (Offset 0x1138) */
+
+#define BIT__FT2ISR__IND_MSK BIT(30)
+#define BIT_FTM_PTT_INT_EN BIT(29)
+#define BIT_RXFTMREQ_INT_EN BIT(28)
+#define BIT_RXFTM_INT_EN BIT(27)
+#define BIT_TXFTM_INT_EN BIT(26)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT1IMR (Offset 0x1138) */
+
+#define BIT_FS_H2C_CMD_OK_INT_EN BIT(25)
+#define BIT_FS_H2C_CMD_FULL_INT_EN BIT(24)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT1IMR (Offset 0x1138) */
+
+#define BIT_FS_MACID_PWRCHANGE5_INT_EN BIT(23)
+#define BIT_FS_MACID_PWRCHANGE4_INT_EN BIT(22)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FT1IMR (Offset 0x1138) */
+
+#define BIT_FS_MACID_SEARCH_FAIL_INT_EN BIT(22)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT1IMR (Offset 0x1138) */
+
+#define BIT_FS_MACID_PWRCHANGE3_INT_EN BIT(21)
+#define BIT_FS_MACID_PWRCHANGE2_INT_EN BIT(20)
+#define BIT_FS_MACID_PWRCHANGE1_INT_EN BIT(19)
+#define BIT_FS_MACID_PWRCHANGE0_INT_EN BIT(18)
+#define BIT_FS_CTWEND2_INT_EN BIT(17)
+#define BIT_FS_CTWEND1_INT_EN BIT(16)
+#define BIT_FS_CTWEND0_INT_EN BIT(15)
+#define BIT_FS_TX_NULL1_INT_EN BIT(14)
+#define BIT_FS_TX_NULL0_INT_EN BIT(13)
+#define BIT_FS_TSF_BIT32_TOGGLE_EN BIT(12)
+#define BIT_FS_P2P_RFON2_INT_EN BIT(11)
+#define BIT_FS_P2P_RFOFF2_INT_EN BIT(10)
+#define BIT_FS_P2P_RFON1_INT_EN BIT(9)
+#define BIT_FS_P2P_RFOFF1_INT_EN BIT(8)
+#define BIT_FS_P2P_RFON0_INT_EN BIT(7)
+#define BIT_FS_P2P_RFOFF0_INT_EN BIT(6)
+#define BIT_FS_RX_UAPSDMD1_EN BIT(5)
+#define BIT_FS_RX_UAPSDMD0_EN BIT(4)
+#define BIT_FS_TRIGGER_PKT_EN BIT(3)
+#define BIT_FS_EOSP_INT_EN BIT(2)
+#define BIT_FS_RPWM2_INT_EN BIT(1)
+#define BIT_FS_RPWM_INT_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT1ISR (Offset 0x113C) */
+
+#define BIT__FT2ISR__IND_INT BIT(30)
+#define BIT_FTM_PTT_INT BIT(29)
+#define BIT_RXFTMREQ_INT BIT(28)
+#define BIT_RXFTM_INT BIT(27)
+#define BIT_TXFTM_INT BIT(26)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT1ISR (Offset 0x113C) */
+
+#define BIT_FS_H2C_CMD_OK_INT BIT(25)
+#define BIT_FS_H2C_CMD_FULL_INT BIT(24)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT1ISR (Offset 0x113C) */
+
+#define BIT_FS_MACID_PWRCHANGE5_INT BIT(23)
+#define BIT_FS_MACID_PWRCHANGE4_INT BIT(22)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FT1ISR (Offset 0x113C) */
+
+#define BIT_FS_MACID_SEARCH_FAIL_INT BIT(22)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT1ISR (Offset 0x113C) */
+
+#define BIT_FS_MACID_PWRCHANGE3_INT BIT(21)
+#define BIT_FS_MACID_PWRCHANGE2_INT BIT(20)
+#define BIT_FS_MACID_PWRCHANGE1_INT BIT(19)
+#define BIT_FS_MACID_PWRCHANGE0_INT BIT(18)
+#define BIT_FS_CTWEND2_INT BIT(17)
+#define BIT_FS_CTWEND1_INT BIT(16)
+#define BIT_FS_CTWEND0_INT BIT(15)
+#define BIT_FS_TX_NULL1_INT BIT(14)
+#define BIT_FS_TX_NULL0_INT BIT(13)
+#define BIT_FS_TSF_BIT32_TOGGLE_INT BIT(12)
+#define BIT_FS_P2P_RFON2_INT BIT(11)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FT1ISR (Offset 0x113C) */
+
+#define BIT_FS_TXBCNOK_PORT4_INT_EN BIT(11)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT1ISR (Offset 0x113C) */
+
+#define BIT_FS_P2P_RFOFF2_INT BIT(10)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FT1ISR (Offset 0x113C) */
+
+#define BIT_FS_TXBCNOK_PORT3_INT_EN BIT(10)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT1ISR (Offset 0x113C) */
+
+#define BIT_FS_P2P_RFON1_INT BIT(9)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FT1ISR (Offset 0x113C) */
+
+#define BIT_FS_TXBCNOK_PORT2_INT_EN BIT(9)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT1ISR (Offset 0x113C) */
+
+#define BIT_FS_P2P_RFOFF1_INT BIT(8)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FT1ISR (Offset 0x113C) */
+
+#define BIT_FS_TXBCNOK_PORT1_INT_EN BIT(8)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT1ISR (Offset 0x113C) */
+
+#define BIT_FS_P2P_RFON0_INT BIT(7)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FT1ISR (Offset 0x113C) */
+
+#define BIT_FS_TXBCNERR_PORT4_INT_EN BIT(7)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT1ISR (Offset 0x113C) */
+
+#define BIT_FS_P2P_RFOFF0_INT BIT(6)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FT1ISR (Offset 0x113C) */
+
+#define BIT_FS_TXBCNERR_PORT3_INT_EN BIT(6)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT1ISR (Offset 0x113C) */
+
+#define BIT_FS_RX_UAPSDMD1_INT BIT(5)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FT1ISR (Offset 0x113C) */
+
+#define BIT_FS_TXBCNERR_PORT2_INT_EN BIT(5)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT1ISR (Offset 0x113C) */
+
+#define BIT_FS_RX_UAPSDMD0_INT BIT(4)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FT1ISR (Offset 0x113C) */
+
+#define BIT_FS_TXBCNERR_PORT1_INT_EN BIT(4)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT1ISR (Offset 0x113C) */
+
+#define BIT_FS_TRIGGER_PKT_INT BIT(3)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FT1ISR (Offset 0x113C) */
+
+#define BIT_FS_ATIM_PORT4_INT_EN BIT(3)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT1ISR (Offset 0x113C) */
+
+#define BIT_FS_EOSP_INT BIT(2)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FT1ISR (Offset 0x113C) */
+
+#define BIT_FS_ATIM_PORT3_INT_EN BIT(2)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT1ISR (Offset 0x113C) */
+
+#define BIT_FS_RPWM2_INT BIT(1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FT1ISR (Offset 0x113C) */
+
+#define BIT_FS_ATIM_PORT2_INT_EN BIT(1)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT1ISR (Offset 0x113C) */
+
+#define BIT_FS_RPWM_INT BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FT1ISR (Offset 0x113C) */
+
+#define BIT_FS_ATIM_PORT1_INT_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SPWR0 (Offset 0x1140) */
+
+#define BIT_SHIFT_MID_31TO0 0
+#define BIT_MASK_MID_31TO0 0xffffffffL
+#define BIT_MID_31TO0(x) (((x) & BIT_MASK_MID_31TO0) << BIT_SHIFT_MID_31TO0)
+#define BITS_MID_31TO0 (BIT_MASK_MID_31TO0 << BIT_SHIFT_MID_31TO0)
+#define BIT_CLEAR_MID_31TO0(x) ((x) & (~BITS_MID_31TO0))
+#define BIT_GET_MID_31TO0(x) (((x) >> BIT_SHIFT_MID_31TO0) & BIT_MASK_MID_31TO0)
+#define BIT_SET_MID_31TO0(x, v) (BIT_CLEAR_MID_31TO0(x) | BIT_MID_31TO0(v))
+
+/* 2 REG_SPWR1 (Offset 0x1144) */
+
+#define BIT_SHIFT_MID_63TO32 0
+#define BIT_MASK_MID_63TO32 0xffffffffL
+#define BIT_MID_63TO32(x) (((x) & BIT_MASK_MID_63TO32) << BIT_SHIFT_MID_63TO32)
+#define BITS_MID_63TO32 (BIT_MASK_MID_63TO32 << BIT_SHIFT_MID_63TO32)
+#define BIT_CLEAR_MID_63TO32(x) ((x) & (~BITS_MID_63TO32))
+#define BIT_GET_MID_63TO32(x) \
+ (((x) >> BIT_SHIFT_MID_63TO32) & BIT_MASK_MID_63TO32)
+#define BIT_SET_MID_63TO32(x, v) (BIT_CLEAR_MID_63TO32(x) | BIT_MID_63TO32(v))
+
+/* 2 REG_SPWR2 (Offset 0x1148) */
+
+#define BIT_SHIFT_MID_95O64 0
+#define BIT_MASK_MID_95O64 0xffffffffL
+#define BIT_MID_95O64(x) (((x) & BIT_MASK_MID_95O64) << BIT_SHIFT_MID_95O64)
+#define BITS_MID_95O64 (BIT_MASK_MID_95O64 << BIT_SHIFT_MID_95O64)
+#define BIT_CLEAR_MID_95O64(x) ((x) & (~BITS_MID_95O64))
+#define BIT_GET_MID_95O64(x) (((x) >> BIT_SHIFT_MID_95O64) & BIT_MASK_MID_95O64)
+#define BIT_SET_MID_95O64(x, v) (BIT_CLEAR_MID_95O64(x) | BIT_MID_95O64(v))
+
+/* 2 REG_SPWR3 (Offset 0x114C) */
+
+#define BIT_SHIFT_MID_127TO96 0
+#define BIT_MASK_MID_127TO96 0xffffffffL
+#define BIT_MID_127TO96(x) \
+ (((x) & BIT_MASK_MID_127TO96) << BIT_SHIFT_MID_127TO96)
+#define BITS_MID_127TO96 (BIT_MASK_MID_127TO96 << BIT_SHIFT_MID_127TO96)
+#define BIT_CLEAR_MID_127TO96(x) ((x) & (~BITS_MID_127TO96))
+#define BIT_GET_MID_127TO96(x) \
+ (((x) >> BIT_SHIFT_MID_127TO96) & BIT_MASK_MID_127TO96)
+#define BIT_SET_MID_127TO96(x, v) \
+ (BIT_CLEAR_MID_127TO96(x) | BIT_MID_127TO96(v))
+
+/* 2 REG_POWSEQ (Offset 0x1150) */
+
+#define BIT_SHIFT_SEQNUM_MID 16
+#define BIT_MASK_SEQNUM_MID 0xffff
+#define BIT_SEQNUM_MID(x) (((x) & BIT_MASK_SEQNUM_MID) << BIT_SHIFT_SEQNUM_MID)
+#define BITS_SEQNUM_MID (BIT_MASK_SEQNUM_MID << BIT_SHIFT_SEQNUM_MID)
+#define BIT_CLEAR_SEQNUM_MID(x) ((x) & (~BITS_SEQNUM_MID))
+#define BIT_GET_SEQNUM_MID(x) \
+ (((x) >> BIT_SHIFT_SEQNUM_MID) & BIT_MASK_SEQNUM_MID)
+#define BIT_SET_SEQNUM_MID(x, v) (BIT_CLEAR_SEQNUM_MID(x) | BIT_SEQNUM_MID(v))
+
+#define BIT_SHIFT_REF_MID 0
+#define BIT_MASK_REF_MID 0x7f
+#define BIT_REF_MID(x) (((x) & BIT_MASK_REF_MID) << BIT_SHIFT_REF_MID)
+#define BITS_REF_MID (BIT_MASK_REF_MID << BIT_SHIFT_REF_MID)
+#define BIT_CLEAR_REF_MID(x) ((x) & (~BITS_REF_MID))
+#define BIT_GET_REF_MID(x) (((x) >> BIT_SHIFT_REF_MID) & BIT_MASK_REF_MID)
+#define BIT_SET_REF_MID(x, v) (BIT_CLEAR_REF_MID(x) | BIT_REF_MID(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RX_BCN_TBTT_ITVL0 (Offset 0x1160) */
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2 24
+#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2 0xff
+#define BIT_RX_BCN_TBTT_ITVL_CLIENT2(x) \
+ (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2) \
+ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2)
+#define BITS_RX_BCN_TBTT_ITVL_CLIENT2 \
+ (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2 \
+ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2(x) \
+ ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT2))
+#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT2(x) \
+ (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2) & \
+ BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2)
+#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT2(x, v) \
+ (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2(x) | \
+ BIT_RX_BCN_TBTT_ITVL_CLIENT2(v))
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1 16
+#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1 0xff
+#define BIT_RX_BCN_TBTT_ITVL_CLIENT1(x) \
+ (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1) \
+ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1)
+#define BITS_RX_BCN_TBTT_ITVL_CLIENT1 \
+ (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1 \
+ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1(x) \
+ ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT1))
+#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT1(x) \
+ (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1) & \
+ BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1)
+#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT1(x, v) \
+ (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1(x) | \
+ BIT_RX_BCN_TBTT_ITVL_CLIENT1(v))
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0 8
+#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0 0xff
+#define BIT_RX_BCN_TBTT_ITVL_CLIENT0(x) \
+ (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0) \
+ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0)
+#define BITS_RX_BCN_TBTT_ITVL_CLIENT0 \
+ (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0 \
+ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0(x) \
+ ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT0))
+#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT0(x) \
+ (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0) & \
+ BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0)
+#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT0(x, v) \
+ (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0(x) | \
+ BIT_RX_BCN_TBTT_ITVL_CLIENT0(v))
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0 0
+#define BIT_MASK_RX_BCN_TBTT_ITVL_PORT0 0xff
+#define BIT_RX_BCN_TBTT_ITVL_PORT0(x) \
+ (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_PORT0) \
+ << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0)
+#define BITS_RX_BCN_TBTT_ITVL_PORT0 \
+ (BIT_MASK_RX_BCN_TBTT_ITVL_PORT0 << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0(x) \
+ ((x) & (~BITS_RX_BCN_TBTT_ITVL_PORT0))
+#define BIT_GET_RX_BCN_TBTT_ITVL_PORT0(x) \
+ (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0) & \
+ BIT_MASK_RX_BCN_TBTT_ITVL_PORT0)
+#define BIT_SET_RX_BCN_TBTT_ITVL_PORT0(x, v) \
+ (BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0(x) | BIT_RX_BCN_TBTT_ITVL_PORT0(v))
+
+/* 2 REG_RX_BCN_TBTT_ITVL1 (Offset 0x1164) */
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3 0
+#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3 0xff
+#define BIT_RX_BCN_TBTT_ITVL_CLIENT3(x) \
+ (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3) \
+ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3)
+#define BITS_RX_BCN_TBTT_ITVL_CLIENT3 \
+ (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3 \
+ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3(x) \
+ ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT3))
+#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT3(x) \
+ (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3) & \
+ BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3)
+#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT3(x, v) \
+ (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3(x) | \
+ BIT_RX_BCN_TBTT_ITVL_CLIENT3(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FWIMR1 (Offset 0x1168) */
+
+#define BIT_FS_ATIM_MB15_INT_EN BIT(31)
+#define BIT_FS_ATIM_MB14_INT_EN BIT(30)
+#define BIT_FS_ATIM_MB13_INT_EN BIT(29)
+#define BIT_FS_ATIM_MB12_INT_EN BIT(28)
+#define BIT_FS_ATIM_MB11_INT_EN BIT(27)
+#define BIT_FS_ATIM_MB10_INT_EN BIT(26)
+#define BIT_FS_ATIM_MB9_INT_EN BIT(25)
+#define BIT_FS_ATIM_MB8_INT_EN BIT(24)
+#define BIT_FS_TXBCNERR_MB15_INT_EN BIT(23)
+#define BIT_FS_TXBCNERR_MB14_INT_EN BIT(22)
+#define BIT_FS_TXBCNERR_MB13_INT_EN BIT(21)
+#define BIT_FS_TXBCNERR_MB12_INT_EN BIT(20)
+#define BIT_FS_TXBCNERR_MB11_INT_EN BIT(19)
+#define BIT_FS_TXBCNERR_MB10_INT_EN BIT(18)
+#define BIT_FS_TXBCNERR_MB9_INT_EN BIT(17)
+#define BIT_FS_TXBCNERR_MB8_INT_EN BIT(16)
+#define BIT_FS_TXBCNOK_MB15_INT_EN BIT(15)
+#define BIT_FS_TXBCNOK_MB14_INT_EN BIT(14)
+#define BIT_FS_TXBCNOK_MB13_INT_EN BIT(13)
+#define BIT_FS_TXBCNOK_MB12_INT_EN BIT(12)
+#define BIT_FS_TXBCNOK_MB11_INT_EN BIT(11)
+#define BIT_FS_TXBCNOK_MB10_INT_EN BIT(10)
+#define BIT_FS_TXBCNOK_MB9_INT_EN BIT(9)
+#define BIT_FS_TXBCNOK_MB8_INT_EN BIT(8)
+#define BIT_FS_BCNERLY0_MB15INT_EN BIT(7)
+#define BIT_FS_BCNERLY0_MB14INT_EN BIT(6)
+#define BIT_FS_BCNERLY0_MB13INT_EN BIT(5)
+#define BIT_FS_BCNERLY0_MB12INT_EN BIT(4)
+#define BIT_FS_BCNERLY0_MB11INT_EN BIT(3)
+#define BIT_FS_BCNERLY0_MB10INT_EN BIT(2)
+#define BIT_FS_BCNERLY0_MB9INT_EN BIT(1)
+#define BIT_FS_BCNERLY0_MB8INT_EN BIT(0)
+
+/* 2 REG_FWISR1 (Offset 0x116C) */
+
+#define BIT_FS_ATIM_MB15_INT BIT(31)
+#define BIT_FS_ATIM_MB14_INT BIT(30)
+#define BIT_FS_ATIM_MB13_INT BIT(29)
+#define BIT_FS_ATIM_MB12_INT BIT(28)
+#define BIT_FS_ATIM_MB11_INT BIT(27)
+#define BIT_FS_ATIM_MB10_INT BIT(26)
+#define BIT_FS_ATIM_MB9_INT BIT(25)
+#define BIT_FS_ATIM_MB8_INT BIT(24)
+#define BIT_FS_TXBCNERR_MB15_INT BIT(23)
+#define BIT_FS_TXBCNERR_MB14_INT BIT(22)
+#define BIT_FS_TXBCNERR_MB13_INT BIT(21)
+#define BIT_FS_TXBCNERR_MB12_INT BIT(20)
+#define BIT_FS_TXBCNERR_MB11_INT BIT(19)
+#define BIT_FS_TXBCNERR_MB10_INT BIT(18)
+#define BIT_FS_TXBCNERR_MB9_INT BIT(17)
+#define BIT_FS_TXBCNERR_MB8_INT BIT(16)
+#define BIT_FS_TXBCNOK_MB15_INT BIT(15)
+#define BIT_FS_TXBCNOK_MB14_INT BIT(14)
+#define BIT_FS_TXBCNOK_MB13_INT BIT(13)
+#define BIT_FS_TXBCNOK_MB12_INT BIT(12)
+#define BIT_FS_TXBCNOK_MB11_INT BIT(11)
+#define BIT_FS_TXBCNOK_MB10_INT BIT(10)
+#define BIT_FS_TXBCNOK_MB9_INT BIT(9)
+#define BIT_FS_TXBCNOK_MB8_INT BIT(8)
+#define BIT_FS_BCNERLY0_MB15INT BIT(7)
+#define BIT_FS_BCNERLY0_MB14INT BIT(6)
+#define BIT_FS_BCNERLY0_MB13INT BIT(5)
+#define BIT_FS_BCNERLY0_MB12INT BIT(4)
+#define BIT_FS_BCNERLY0_MB11INT BIT(3)
+#define BIT_FS_BCNERLY0_MB10INT BIT(2)
+#define BIT_FS_BCNERLY0_MB9INT BIT(1)
+#define BIT_FS_BCNERLY0_MB8INT BIT(0)
+
+/* 2 REG_FWIMR2 (Offset 0x1170) */
+
+#define BIT_FS_BCNDMA0_MB15_INT_EN BIT(15)
+#define BIT_FS_BCNDMA0_MB14_INT_EN BIT(14)
+#define BIT_FS_BCNDMA0_MB13_INT_EN BIT(13)
+#define BIT_FS_BCNDMA0_MB12_INT_EN BIT(12)
+#define BIT_FS_BCNDMA0_MB11_INT_EN BIT(11)
+#define BIT_FS_BCNDMA0_MB10_INT_EN BIT(10)
+#define BIT_FS_BCNDMA0_MB9_INT_EN BIT(9)
+#define BIT_FS_BCNDMA0_MB8_INT_EN BIT(8)
+#define BIT_FS_TBTT0_MB15INT_EN BIT(7)
+#define BIT_FS_TBTT0_MB14INT_EN BIT(6)
+#define BIT_FS_TBTT0_MB13INT_EN BIT(5)
+#define BIT_FS_TBTT0_MB12INT_EN BIT(4)
+#define BIT_FS_TBTT0_MB11INT_EN BIT(3)
+#define BIT_FS_TBTT0_MB10INT_EN BIT(2)
+#define BIT_FS_TBTT0_MB9INT_EN BIT(1)
+#define BIT_FS_TBTT0_MB8INT_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_IO_WRAP_ERR_FLAG (Offset 0x1170) */
+
+#define BIT_IO_WRAP_ERR BIT(0)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FWISR2 (Offset 0x1174) */
+
+#define BIT_FS_BCNDMA0_MB15_INT BIT(15)
+#define BIT_FS_BCNDMA0_MB14_INT BIT(14)
+#define BIT_FS_BCNDMA0_MB13_INT BIT(13)
+#define BIT_FS_BCNDMA0_MB12_INT BIT(12)
+#define BIT_FS_BCNDMA0_MB11_INT BIT(11)
+#define BIT_FS_BCNDMA0_MB10_INT BIT(10)
+#define BIT_FS_BCNDMA0_MB9_INT BIT(9)
+#define BIT_FS_BCNDMA0_MB8_INT BIT(8)
+#define BIT_FS_TBTT0_MB15INT BIT(7)
+#define BIT_FS_TBTT0_MB14INT BIT(6)
+#define BIT_FS_TBTT0_MB13INT BIT(5)
+#define BIT_FS_TBTT0_MB12INT BIT(4)
+#define BIT_FS_TBTT0_MB11INT BIT(3)
+#define BIT_FS_TBTT0_MB10INT BIT(2)
+#define BIT_FS_TBTT0_MB9INT BIT(1)
+#define BIT_FS_TBTT0_MB8INT BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FWISR3 (Offset 0x117C) */
+
+#define BIT_FS_TXBCNOK_PORT4_INT BIT(11)
+#define BIT_FS_TXBCNOK_PORT3_INT BIT(10)
+#define BIT_FS_TXBCNOK_PORT2_INT BIT(9)
+#define BIT_FS_TXBCNOK_PORT1_INT BIT(8)
+#define BIT_FS_TXBCNERR_PORT4_INT BIT(7)
+#define BIT_FS_TXBCNERR_PORT3_INT BIT(6)
+#define BIT_FS_TXBCNERR_PORT2_INT BIT(5)
+#define BIT_FS_TXBCNERR_PORT1_INT BIT(4)
+#define BIT_FS_ATIM_PORT4_INT BIT(3)
+#define BIT_FS_ATIM_PORT3_INT BIT(2)
+#define BIT_FS_ATIM_PORT2_INT BIT(1)
+#define BIT_FS_ATIM_PORT1_INT BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_SPEED_SENSOR (Offset 0x1180) */
+
+#define BIT_DSS_1_RST_N BIT(31)
+#define BIT_DSS_1_SPEED_EN BIT(30)
+#define BIT_DSS_1_WIRE_SEL BIT(29)
+#define BIT_DSS_ENCLK BIT(28)
+
+#define BIT_SHIFT_DSS_1_RO_SEL 24
+#define BIT_MASK_DSS_1_RO_SEL 0x7
+#define BIT_DSS_1_RO_SEL(x) \
+ (((x) & BIT_MASK_DSS_1_RO_SEL) << BIT_SHIFT_DSS_1_RO_SEL)
+#define BITS_DSS_1_RO_SEL (BIT_MASK_DSS_1_RO_SEL << BIT_SHIFT_DSS_1_RO_SEL)
+#define BIT_CLEAR_DSS_1_RO_SEL(x) ((x) & (~BITS_DSS_1_RO_SEL))
+#define BIT_GET_DSS_1_RO_SEL(x) \
+ (((x) >> BIT_SHIFT_DSS_1_RO_SEL) & BIT_MASK_DSS_1_RO_SEL)
+#define BIT_SET_DSS_1_RO_SEL(x, v) \
+ (BIT_CLEAR_DSS_1_RO_SEL(x) | BIT_DSS_1_RO_SEL(v))
+
+#define BIT_SHIFT_DSS_1_DATA_IN 0
+#define BIT_MASK_DSS_1_DATA_IN 0xfffff
+#define BIT_DSS_1_DATA_IN(x) \
+ (((x) & BIT_MASK_DSS_1_DATA_IN) << BIT_SHIFT_DSS_1_DATA_IN)
+#define BITS_DSS_1_DATA_IN (BIT_MASK_DSS_1_DATA_IN << BIT_SHIFT_DSS_1_DATA_IN)
+#define BIT_CLEAR_DSS_1_DATA_IN(x) ((x) & (~BITS_DSS_1_DATA_IN))
+#define BIT_GET_DSS_1_DATA_IN(x) \
+ (((x) >> BIT_SHIFT_DSS_1_DATA_IN) & BIT_MASK_DSS_1_DATA_IN)
+#define BIT_SET_DSS_1_DATA_IN(x, v) \
+ (BIT_CLEAR_DSS_1_DATA_IN(x) | BIT_DSS_1_DATA_IN(v))
+
+/* 2 REG_SPEED_SENSOR1 (Offset 0x1184) */
+
+#define BIT_DSS_1_READY BIT(31)
+#define BIT_DSS_1_WSORT_GO BIT(30)
+
+#define BIT_SHIFT_DSS_1_COUNT_OUT 0
+#define BIT_MASK_DSS_1_COUNT_OUT 0xfffff
+#define BIT_DSS_1_COUNT_OUT(x) \
+ (((x) & BIT_MASK_DSS_1_COUNT_OUT) << BIT_SHIFT_DSS_1_COUNT_OUT)
+#define BITS_DSS_1_COUNT_OUT \
+ (BIT_MASK_DSS_1_COUNT_OUT << BIT_SHIFT_DSS_1_COUNT_OUT)
+#define BIT_CLEAR_DSS_1_COUNT_OUT(x) ((x) & (~BITS_DSS_1_COUNT_OUT))
+#define BIT_GET_DSS_1_COUNT_OUT(x) \
+ (((x) >> BIT_SHIFT_DSS_1_COUNT_OUT) & BIT_MASK_DSS_1_COUNT_OUT)
+#define BIT_SET_DSS_1_COUNT_OUT(x, v) \
+ (BIT_CLEAR_DSS_1_COUNT_OUT(x) | BIT_DSS_1_COUNT_OUT(v))
+
+/* 2 REG_SPEED_SENSOR2 (Offset 0x1188) */
+
+#define BIT_DSS_2_RST_N BIT(31)
+#define BIT_DSS_2_SPEED_EN BIT(30)
+#define BIT_DSS_2_WIRE_SEL BIT(29)
+
+#define BIT_SHIFT_DSS_2_RO_SEL 24
+#define BIT_MASK_DSS_2_RO_SEL 0x7
+#define BIT_DSS_2_RO_SEL(x) \
+ (((x) & BIT_MASK_DSS_2_RO_SEL) << BIT_SHIFT_DSS_2_RO_SEL)
+#define BITS_DSS_2_RO_SEL (BIT_MASK_DSS_2_RO_SEL << BIT_SHIFT_DSS_2_RO_SEL)
+#define BIT_CLEAR_DSS_2_RO_SEL(x) ((x) & (~BITS_DSS_2_RO_SEL))
+#define BIT_GET_DSS_2_RO_SEL(x) \
+ (((x) >> BIT_SHIFT_DSS_2_RO_SEL) & BIT_MASK_DSS_2_RO_SEL)
+#define BIT_SET_DSS_2_RO_SEL(x, v) \
+ (BIT_CLEAR_DSS_2_RO_SEL(x) | BIT_DSS_2_RO_SEL(v))
+
+#define BIT_SHIFT_DSS_2_DATA_IN 0
+#define BIT_MASK_DSS_2_DATA_IN 0xfffff
+#define BIT_DSS_2_DATA_IN(x) \
+ (((x) & BIT_MASK_DSS_2_DATA_IN) << BIT_SHIFT_DSS_2_DATA_IN)
+#define BITS_DSS_2_DATA_IN (BIT_MASK_DSS_2_DATA_IN << BIT_SHIFT_DSS_2_DATA_IN)
+#define BIT_CLEAR_DSS_2_DATA_IN(x) ((x) & (~BITS_DSS_2_DATA_IN))
+#define BIT_GET_DSS_2_DATA_IN(x) \
+ (((x) >> BIT_SHIFT_DSS_2_DATA_IN) & BIT_MASK_DSS_2_DATA_IN)
+#define BIT_SET_DSS_2_DATA_IN(x, v) \
+ (BIT_CLEAR_DSS_2_DATA_IN(x) | BIT_DSS_2_DATA_IN(v))
+
+/* 2 REG_SPEED_SENSOR3 (Offset 0x118C) */
+
+#define BIT_DSS_2_READY BIT(31)
+#define BIT_DSS_2_WSORT_GO BIT(30)
+
+#define BIT_SHIFT_DSS_2_COUNT_OUT 0
+#define BIT_MASK_DSS_2_COUNT_OUT 0xfffff
+#define BIT_DSS_2_COUNT_OUT(x) \
+ (((x) & BIT_MASK_DSS_2_COUNT_OUT) << BIT_SHIFT_DSS_2_COUNT_OUT)
+#define BITS_DSS_2_COUNT_OUT \
+ (BIT_MASK_DSS_2_COUNT_OUT << BIT_SHIFT_DSS_2_COUNT_OUT)
+#define BIT_CLEAR_DSS_2_COUNT_OUT(x) ((x) & (~BITS_DSS_2_COUNT_OUT))
+#define BIT_GET_DSS_2_COUNT_OUT(x) \
+ (((x) >> BIT_SHIFT_DSS_2_COUNT_OUT) & BIT_MASK_DSS_2_COUNT_OUT)
+#define BIT_SET_DSS_2_COUNT_OUT(x, v) \
+ (BIT_CLEAR_DSS_2_COUNT_OUT(x) | BIT_DSS_2_COUNT_OUT(v))
+
+/* 2 REG_SPEED_SENSOR4 (Offset 0x1190) */
+
+#define BIT_DSS_3_RST_N BIT(31)
+#define BIT_DSS_3_SPEED_EN BIT(30)
+#define BIT_DSS_3_WIRE_SEL BIT(29)
+
+#define BIT_SHIFT_DSS_3_RO_SEL 24
+#define BIT_MASK_DSS_3_RO_SEL 0x7
+#define BIT_DSS_3_RO_SEL(x) \
+ (((x) & BIT_MASK_DSS_3_RO_SEL) << BIT_SHIFT_DSS_3_RO_SEL)
+#define BITS_DSS_3_RO_SEL (BIT_MASK_DSS_3_RO_SEL << BIT_SHIFT_DSS_3_RO_SEL)
+#define BIT_CLEAR_DSS_3_RO_SEL(x) ((x) & (~BITS_DSS_3_RO_SEL))
+#define BIT_GET_DSS_3_RO_SEL(x) \
+ (((x) >> BIT_SHIFT_DSS_3_RO_SEL) & BIT_MASK_DSS_3_RO_SEL)
+#define BIT_SET_DSS_3_RO_SEL(x, v) \
+ (BIT_CLEAR_DSS_3_RO_SEL(x) | BIT_DSS_3_RO_SEL(v))
+
+#define BIT_SHIFT_DSS_3_DATA_IN 0
+#define BIT_MASK_DSS_3_DATA_IN 0xfffff
+#define BIT_DSS_3_DATA_IN(x) \
+ (((x) & BIT_MASK_DSS_3_DATA_IN) << BIT_SHIFT_DSS_3_DATA_IN)
+#define BITS_DSS_3_DATA_IN (BIT_MASK_DSS_3_DATA_IN << BIT_SHIFT_DSS_3_DATA_IN)
+#define BIT_CLEAR_DSS_3_DATA_IN(x) ((x) & (~BITS_DSS_3_DATA_IN))
+#define BIT_GET_DSS_3_DATA_IN(x) \
+ (((x) >> BIT_SHIFT_DSS_3_DATA_IN) & BIT_MASK_DSS_3_DATA_IN)
+#define BIT_SET_DSS_3_DATA_IN(x, v) \
+ (BIT_CLEAR_DSS_3_DATA_IN(x) | BIT_DSS_3_DATA_IN(v))
+
+/* 2 REG_SPEED_SENSOR5 (Offset 0x1194) */
+
+#define BIT_DSS_3_READY BIT(31)
+#define BIT_DSS_3_WSORT_GO BIT(30)
+
+#define BIT_SHIFT_DSS_3_COUNT_OUT 0
+#define BIT_MASK_DSS_3_COUNT_OUT 0xfffff
+#define BIT_DSS_3_COUNT_OUT(x) \
+ (((x) & BIT_MASK_DSS_3_COUNT_OUT) << BIT_SHIFT_DSS_3_COUNT_OUT)
+#define BITS_DSS_3_COUNT_OUT \
+ (BIT_MASK_DSS_3_COUNT_OUT << BIT_SHIFT_DSS_3_COUNT_OUT)
+#define BIT_CLEAR_DSS_3_COUNT_OUT(x) ((x) & (~BITS_DSS_3_COUNT_OUT))
+#define BIT_GET_DSS_3_COUNT_OUT(x) \
+ (((x) >> BIT_SHIFT_DSS_3_COUNT_OUT) & BIT_MASK_DSS_3_COUNT_OUT)
+#define BIT_SET_DSS_3_COUNT_OUT(x, v) \
+ (BIT_CLEAR_DSS_3_COUNT_OUT(x) | BIT_DSS_3_COUNT_OUT(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_RXPKTBUF_1_MAX_ADDR (Offset 0x1198) */
+
+#define BIT_SHIFT_RXPKTBUF_SIZE 30
+#define BIT_MASK_RXPKTBUF_SIZE 0x3
+#define BIT_RXPKTBUF_SIZE(x) \
+ (((x) & BIT_MASK_RXPKTBUF_SIZE) << BIT_SHIFT_RXPKTBUF_SIZE)
+#define BITS_RXPKTBUF_SIZE (BIT_MASK_RXPKTBUF_SIZE << BIT_SHIFT_RXPKTBUF_SIZE)
+#define BIT_CLEAR_RXPKTBUF_SIZE(x) ((x) & (~BITS_RXPKTBUF_SIZE))
+#define BIT_GET_RXPKTBUF_SIZE(x) \
+ (((x) >> BIT_SHIFT_RXPKTBUF_SIZE) & BIT_MASK_RXPKTBUF_SIZE)
+#define BIT_SET_RXPKTBUF_SIZE(x, v) \
+ (BIT_CLEAR_RXPKTBUF_SIZE(x) | BIT_RXPKTBUF_SIZE(v))
+
+#define BIT_RXPKTBUF_DBG_SEL BIT(29)
+
+#define BIT_SHIFT_RXPKTBUF_1_MAX_ADDR 0
+#define BIT_MASK_RXPKTBUF_1_MAX_ADDR 0x3ffff
+#define BIT_RXPKTBUF_1_MAX_ADDR(x) \
+ (((x) & BIT_MASK_RXPKTBUF_1_MAX_ADDR) << BIT_SHIFT_RXPKTBUF_1_MAX_ADDR)
+#define BITS_RXPKTBUF_1_MAX_ADDR \
+ (BIT_MASK_RXPKTBUF_1_MAX_ADDR << BIT_SHIFT_RXPKTBUF_1_MAX_ADDR)
+#define BIT_CLEAR_RXPKTBUF_1_MAX_ADDR(x) ((x) & (~BITS_RXPKTBUF_1_MAX_ADDR))
+#define BIT_GET_RXPKTBUF_1_MAX_ADDR(x) \
+ (((x) >> BIT_SHIFT_RXPKTBUF_1_MAX_ADDR) & BIT_MASK_RXPKTBUF_1_MAX_ADDR)
+#define BIT_SET_RXPKTBUF_1_MAX_ADDR(x, v) \
+ (BIT_CLEAR_RXPKTBUF_1_MAX_ADDR(x) | BIT_RXPKTBUF_1_MAX_ADDR(v))
+
+/* 2 REG_RXFWBUF_1_MAX_ADDR (Offset 0x119C) */
+
+#define BIT_SHIFT_RXFWBUF_1_MAX_ADDR 0
+#define BIT_MASK_RXFWBUF_1_MAX_ADDR 0xffff
+#define BIT_RXFWBUF_1_MAX_ADDR(x) \
+ (((x) & BIT_MASK_RXFWBUF_1_MAX_ADDR) << BIT_SHIFT_RXFWBUF_1_MAX_ADDR)
+#define BITS_RXFWBUF_1_MAX_ADDR \
+ (BIT_MASK_RXFWBUF_1_MAX_ADDR << BIT_SHIFT_RXFWBUF_1_MAX_ADDR)
+#define BIT_CLEAR_RXFWBUF_1_MAX_ADDR(x) ((x) & (~BITS_RXFWBUF_1_MAX_ADDR))
+#define BIT_GET_RXFWBUF_1_MAX_ADDR(x) \
+ (((x) >> BIT_SHIFT_RXFWBUF_1_MAX_ADDR) & BIT_MASK_RXFWBUF_1_MAX_ADDR)
+#define BIT_SET_RXFWBUF_1_MAX_ADDR(x, v) \
+ (BIT_CLEAR_RXFWBUF_1_MAX_ADDR(x) | BIT_RXFWBUF_1_MAX_ADDR(v))
+
+/* 2 REG_RXPKTBUF_1_READ (Offset 0x11A4) */
+
+#define BIT_SHIFT_RXPKTBUF_1_READ 0
+#define BIT_MASK_RXPKTBUF_1_READ 0x3ffff
+#define BIT_RXPKTBUF_1_READ(x) \
+ (((x) & BIT_MASK_RXPKTBUF_1_READ) << BIT_SHIFT_RXPKTBUF_1_READ)
+#define BITS_RXPKTBUF_1_READ \
+ (BIT_MASK_RXPKTBUF_1_READ << BIT_SHIFT_RXPKTBUF_1_READ)
+#define BIT_CLEAR_RXPKTBUF_1_READ(x) ((x) & (~BITS_RXPKTBUF_1_READ))
+#define BIT_GET_RXPKTBUF_1_READ(x) \
+ (((x) >> BIT_SHIFT_RXPKTBUF_1_READ) & BIT_MASK_RXPKTBUF_1_READ)
+#define BIT_SET_RXPKTBUF_1_READ(x, v) \
+ (BIT_CLEAR_RXPKTBUF_1_READ(x) | BIT_RXPKTBUF_1_READ(v))
+
+/* 2 REG_RXPKTBUF_1_WRITE (Offset 0x11A8) */
+
+#define BIT_SHIFT_R_OQT_DBG_SEL 16
+#define BIT_MASK_R_OQT_DBG_SEL 0xff
+#define BIT_R_OQT_DBG_SEL(x) \
+ (((x) & BIT_MASK_R_OQT_DBG_SEL) << BIT_SHIFT_R_OQT_DBG_SEL)
+#define BITS_R_OQT_DBG_SEL (BIT_MASK_R_OQT_DBG_SEL << BIT_SHIFT_R_OQT_DBG_SEL)
+#define BIT_CLEAR_R_OQT_DBG_SEL(x) ((x) & (~BITS_R_OQT_DBG_SEL))
+#define BIT_GET_R_OQT_DBG_SEL(x) \
+ (((x) >> BIT_SHIFT_R_OQT_DBG_SEL) & BIT_MASK_R_OQT_DBG_SEL)
+#define BIT_SET_R_OQT_DBG_SEL(x, v) \
+ (BIT_CLEAR_R_OQT_DBG_SEL(x) | BIT_R_OQT_DBG_SEL(v))
+
+#define BIT_SHIFT_R_TXPKTBF_DBG_SEL 8
+#define BIT_MASK_R_TXPKTBF_DBG_SEL 0x7
+#define BIT_R_TXPKTBF_DBG_SEL(x) \
+ (((x) & BIT_MASK_R_TXPKTBF_DBG_SEL) << BIT_SHIFT_R_TXPKTBF_DBG_SEL)
+#define BITS_R_TXPKTBF_DBG_SEL \
+ (BIT_MASK_R_TXPKTBF_DBG_SEL << BIT_SHIFT_R_TXPKTBF_DBG_SEL)
+#define BIT_CLEAR_R_TXPKTBF_DBG_SEL(x) ((x) & (~BITS_R_TXPKTBF_DBG_SEL))
+#define BIT_GET_R_TXPKTBF_DBG_SEL(x) \
+ (((x) >> BIT_SHIFT_R_TXPKTBF_DBG_SEL) & BIT_MASK_R_TXPKTBF_DBG_SEL)
+#define BIT_SET_R_TXPKTBF_DBG_SEL(x, v) \
+ (BIT_CLEAR_R_TXPKTBF_DBG_SEL(x) | BIT_R_TXPKTBF_DBG_SEL(v))
+
+#define BIT_SHIFT_R_RXPKT_DBG_SEL 6
+#define BIT_MASK_R_RXPKT_DBG_SEL 0x3
+#define BIT_R_RXPKT_DBG_SEL(x) \
+ (((x) & BIT_MASK_R_RXPKT_DBG_SEL) << BIT_SHIFT_R_RXPKT_DBG_SEL)
+#define BITS_R_RXPKT_DBG_SEL \
+ (BIT_MASK_R_RXPKT_DBG_SEL << BIT_SHIFT_R_RXPKT_DBG_SEL)
+#define BIT_CLEAR_R_RXPKT_DBG_SEL(x) ((x) & (~BITS_R_RXPKT_DBG_SEL))
+#define BIT_GET_R_RXPKT_DBG_SEL(x) \
+ (((x) >> BIT_SHIFT_R_RXPKT_DBG_SEL) & BIT_MASK_R_RXPKT_DBG_SEL)
+#define BIT_SET_R_RXPKT_DBG_SEL(x, v) \
+ (BIT_CLEAR_R_RXPKT_DBG_SEL(x) | BIT_R_RXPKT_DBG_SEL(v))
+
+#define BIT_SHIFT_RXPKTBUF_1_WRITE 0
+#define BIT_MASK_RXPKTBUF_1_WRITE 0x3ffff
+#define BIT_RXPKTBUF_1_WRITE(x) \
+ (((x) & BIT_MASK_RXPKTBUF_1_WRITE) << BIT_SHIFT_RXPKTBUF_1_WRITE)
+#define BITS_RXPKTBUF_1_WRITE \
+ (BIT_MASK_RXPKTBUF_1_WRITE << BIT_SHIFT_RXPKTBUF_1_WRITE)
+#define BIT_CLEAR_RXPKTBUF_1_WRITE(x) ((x) & (~BITS_RXPKTBUF_1_WRITE))
+#define BIT_GET_RXPKTBUF_1_WRITE(x) \
+ (((x) >> BIT_SHIFT_RXPKTBUF_1_WRITE) & BIT_MASK_RXPKTBUF_1_WRITE)
+#define BIT_SET_RXPKTBUF_1_WRITE(x, v) \
+ (BIT_CLEAR_RXPKTBUF_1_WRITE(x) | BIT_RXPKTBUF_1_WRITE(v))
+
+#define BIT_SHIFT_R_RXPKTBF_DBG_SEL 0
+#define BIT_MASK_R_RXPKTBF_DBG_SEL 0x3
+#define BIT_R_RXPKTBF_DBG_SEL(x) \
+ (((x) & BIT_MASK_R_RXPKTBF_DBG_SEL) << BIT_SHIFT_R_RXPKTBF_DBG_SEL)
+#define BITS_R_RXPKTBF_DBG_SEL \
+ (BIT_MASK_R_RXPKTBF_DBG_SEL << BIT_SHIFT_R_RXPKTBF_DBG_SEL)
+#define BIT_CLEAR_R_RXPKTBF_DBG_SEL(x) ((x) & (~BITS_R_RXPKTBF_DBG_SEL))
+#define BIT_GET_R_RXPKTBF_DBG_SEL(x) \
+ (((x) >> BIT_SHIFT_R_RXPKTBF_DBG_SEL) & BIT_MASK_R_RXPKTBF_DBG_SEL)
+#define BIT_SET_R_RXPKTBF_DBG_SEL(x, v) \
+ (BIT_CLEAR_R_RXPKTBF_DBG_SEL(x) | BIT_R_RXPKTBF_DBG_SEL(v))
+
+/* 2 REG_RFE_CTRL_PAD_E2 (Offset 0x11B0) */
+
+#define BIT_RFE_CTRL_ANTSW_E2 BIT(16)
+#define BIT_RFE_CTRL_PIN15_E2 BIT(15)
+#define BIT_RFE_CTRL_PIN14_E2 BIT(14)
+#define BIT_RFE_CTRL_PIN13_E2 BIT(13)
+#define BIT_RFE_CTRL_PIN12_E2 BIT(12)
+#define BIT_RFE_CTRL_PIN11_E2 BIT(11)
+#define BIT_RFE_CTRL_PIN10_E2 BIT(10)
+#define BIT_RFE_CTRL_PIN9_E2 BIT(9)
+#define BIT_RFE_CTRL_PIN8_E2 BIT(8)
+#define BIT_RFE_CTRL_PIN7_E2 BIT(7)
+#define BIT_RFE_CTRL_PIN6_E2 BIT(6)
+#define BIT_RFE_CTRL_PIN5_E2 BIT(5)
+#define BIT_RFE_CTRL_PIN4_E2 BIT(4)
+#define BIT_RFE_CTRL_PIN3_E2 BIT(3)
+#define BIT_RFE_CTRL_PIN2_E2 BIT(2)
+#define BIT_RFE_CTRL_PIN1_E2 BIT(1)
+#define BIT_RFE_CTRL_PIN0_E2 BIT(0)
+
+/* 2 REG_RFE_CTRL_PAD_SR (Offset 0x11B4) */
+
+#define BIT_RFE_CTRL_ANTSW_SR BIT(16)
+#define BIT_RFE_CTRL_PIN15_SR BIT(15)
+#define BIT_RFE_CTRL_PIN14_SR BIT(14)
+#define BIT_RFE_CTRL_PIN13_SR BIT(13)
+#define BIT_RFE_CTRL_PIN12_SR BIT(12)
+#define BIT_RFE_CTRL_PIN11_SR BIT(11)
+#define BIT_RFE_CTRL_PIN10_SR BIT(10)
+#define BIT_RFE_CTRL_PIN9_SR BIT(9)
+#define BIT_RFE_CTRL_PIN8_SR BIT(8)
+#define BIT_RFE_CTRL_PIN7_SR BIT(7)
+#define BIT_RFE_CTRL_PIN6_SR BIT(6)
+#define BIT_RFE_CTRL_PIN5_SR BIT(5)
+#define BIT_RFE_CTRL_PIN4_SR BIT(4)
+#define BIT_RFE_CTRL_PIN3_SR BIT(3)
+#define BIT_RFE_CTRL_PIN2_SR BIT(2)
+#define BIT_RFE_CTRL_PIN1_SR BIT(1)
+#define BIT_RFE_CTRL_PIN0_SR BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_EXT_QUEUE_REG (Offset 0x11C0) */
+
+#define BIT_SHIFT_PCIE_PRIORITY_SEL 0
+#define BIT_MASK_PCIE_PRIORITY_SEL 0x3
+#define BIT_PCIE_PRIORITY_SEL(x) \
+ (((x) & BIT_MASK_PCIE_PRIORITY_SEL) << BIT_SHIFT_PCIE_PRIORITY_SEL)
+#define BITS_PCIE_PRIORITY_SEL \
+ (BIT_MASK_PCIE_PRIORITY_SEL << BIT_SHIFT_PCIE_PRIORITY_SEL)
+#define BIT_CLEAR_PCIE_PRIORITY_SEL(x) ((x) & (~BITS_PCIE_PRIORITY_SEL))
+#define BIT_GET_PCIE_PRIORITY_SEL(x) \
+ (((x) >> BIT_SHIFT_PCIE_PRIORITY_SEL) & BIT_MASK_PCIE_PRIORITY_SEL)
+#define BIT_SET_PCIE_PRIORITY_SEL(x, v) \
+ (BIT_CLEAR_PCIE_PRIORITY_SEL(x) | BIT_PCIE_PRIORITY_SEL(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_H2C_PRIORITY_SEL (Offset 0x11C0) */
+
+#define BIT_SHIFT_H2C_PRIORITY_SEL 0
+#define BIT_MASK_H2C_PRIORITY_SEL 0x3
+#define BIT_H2C_PRIORITY_SEL(x) \
+ (((x) & BIT_MASK_H2C_PRIORITY_SEL) << BIT_SHIFT_H2C_PRIORITY_SEL)
+#define BITS_H2C_PRIORITY_SEL \
+ (BIT_MASK_H2C_PRIORITY_SEL << BIT_SHIFT_H2C_PRIORITY_SEL)
+#define BIT_CLEAR_H2C_PRIORITY_SEL(x) ((x) & (~BITS_H2C_PRIORITY_SEL))
+#define BIT_GET_H2C_PRIORITY_SEL(x) \
+ (((x) >> BIT_SHIFT_H2C_PRIORITY_SEL) & BIT_MASK_H2C_PRIORITY_SEL)
+#define BIT_SET_H2C_PRIORITY_SEL(x, v) \
+ (BIT_CLEAR_H2C_PRIORITY_SEL(x) | BIT_H2C_PRIORITY_SEL(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_COUNTER_CONTROL (Offset 0x11C4) */
+
+#define BIT_EN_USB_CNT BIT(5)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_COUNTER_CTRL (Offset 0x11C4) */
+
+#define BIT_USB_COUNT_EN BIT(5)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_COUNTER_CONTROL (Offset 0x11C4) */
+
+#define BIT_EN_PCIE_CNT BIT(4)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_COUNTER_CTRL (Offset 0x11C4) */
+
+#define BIT_PCIE_COUNT_EN BIT(4)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_COUNTER_CONTROL (Offset 0x11C4) */
+
+#define BIT_RQPN_CNT BIT(3)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_COUNTER_CTRL (Offset 0x11C4) */
+
+#define BIT_RQPN_COUNT_EN BIT(3)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_COUNTER_CONTROL (Offset 0x11C4) */
+
+#define BIT_RDE_CNT BIT(2)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_COUNTER_CTRL (Offset 0x11C4) */
+
+#define BIT_RDE_COUNT_EN BIT(2)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_COUNTER_CONTROL (Offset 0x11C4) */
+
+#define BIT_TDE_CNT BIT(1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_COUNTER_CTRL (Offset 0x11C4) */
+
+#define BIT_TDE_COUNT_EN BIT(1)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_COUNTER_CONTROL (Offset 0x11C4) */
+
+#define BIT_DIS_CNT BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_COUNTER_CTRL (Offset 0x11C4) */
+
+#define BIT_DISABLE_COUNTER BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_COUNTER_TH (Offset 0x11C8) */
+
+#define BIT_CNT_ALL_MACID BIT(31)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_COUNTER_THRESHOLD (Offset 0x11C8) */
+
+#define BIT_SEL_ALL_MACID BIT(31)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_COUNTER_TH (Offset 0x11C8) */
+
+#define BIT_SHIFT_CNT_MACID 24
+#define BIT_MASK_CNT_MACID 0x7f
+#define BIT_CNT_MACID(x) (((x) & BIT_MASK_CNT_MACID) << BIT_SHIFT_CNT_MACID)
+#define BITS_CNT_MACID (BIT_MASK_CNT_MACID << BIT_SHIFT_CNT_MACID)
+#define BIT_CLEAR_CNT_MACID(x) ((x) & (~BITS_CNT_MACID))
+#define BIT_GET_CNT_MACID(x) (((x) >> BIT_SHIFT_CNT_MACID) & BIT_MASK_CNT_MACID)
+#define BIT_SET_CNT_MACID(x, v) (BIT_CLEAR_CNT_MACID(x) | BIT_CNT_MACID(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_COUNTER_THRESHOLD (Offset 0x11C8) */
+
+#define BIT_SHIFT_COUNTER_MACID 24
+#define BIT_MASK_COUNTER_MACID 0x7f
+#define BIT_COUNTER_MACID(x) \
+ (((x) & BIT_MASK_COUNTER_MACID) << BIT_SHIFT_COUNTER_MACID)
+#define BITS_COUNTER_MACID (BIT_MASK_COUNTER_MACID << BIT_SHIFT_COUNTER_MACID)
+#define BIT_CLEAR_COUNTER_MACID(x) ((x) & (~BITS_COUNTER_MACID))
+#define BIT_GET_COUNTER_MACID(x) \
+ (((x) >> BIT_SHIFT_COUNTER_MACID) & BIT_MASK_COUNTER_MACID)
+#define BIT_SET_COUNTER_MACID(x, v) \
+ (BIT_CLEAR_COUNTER_MACID(x) | BIT_COUNTER_MACID(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_COUNTER_SET (Offset 0x11CC) */
+
+#define BIT_RTS_RST BIT(24)
+#define BIT_PTCL_RST BIT(23)
+#define BIT_SCH_RST BIT(22)
+#define BIT_EDCA_RST BIT(21)
+#define BIT_RQPN_RST BIT(20)
+#define BIT_USB_RST BIT(19)
+#define BIT_PCIE_RST BIT(18)
+#define BIT_RXDMA_RST BIT(17)
+#define BIT_TXDMA_RST BIT(16)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_COUNTER_SET (Offset 0x11CC) */
+
+#define BIT_SHIFT_REQUEST_RESET 16
+#define BIT_MASK_REQUEST_RESET 0xffff
+#define BIT_REQUEST_RESET(x) \
+ (((x) & BIT_MASK_REQUEST_RESET) << BIT_SHIFT_REQUEST_RESET)
+#define BITS_REQUEST_RESET (BIT_MASK_REQUEST_RESET << BIT_SHIFT_REQUEST_RESET)
+#define BIT_CLEAR_REQUEST_RESET(x) ((x) & (~BITS_REQUEST_RESET))
+#define BIT_GET_REQUEST_RESET(x) \
+ (((x) >> BIT_SHIFT_REQUEST_RESET) & BIT_MASK_REQUEST_RESET)
+#define BIT_SET_REQUEST_RESET(x, v) \
+ (BIT_CLEAR_REQUEST_RESET(x) | BIT_REQUEST_RESET(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_COUNTER_SET (Offset 0x11CC) */
+
+#define BIT_EN_RTS_START BIT(8)
+#define BIT_EN_PTCL_START BIT(7)
+#define BIT_EN_SCH_START BIT(6)
+#define BIT_EN_EDCA_START BIT(5)
+#define BIT_EN_RQPN_START BIT(4)
+#define BIT_EN_USB_START BIT(3)
+#define BIT_EN_PCIE_START BIT(2)
+#define BIT_EN_RXDMA_START BIT(1)
+#define BIT_EN_TXDMA_START BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_COUNTER_SET (Offset 0x11CC) */
+
+#define BIT_SHIFT_REQUEST_START 0
+#define BIT_MASK_REQUEST_START 0xffff
+#define BIT_REQUEST_START(x) \
+ (((x) & BIT_MASK_REQUEST_START) << BIT_SHIFT_REQUEST_START)
+#define BITS_REQUEST_START (BIT_MASK_REQUEST_START << BIT_SHIFT_REQUEST_START)
+#define BIT_CLEAR_REQUEST_START(x) ((x) & (~BITS_REQUEST_START))
+#define BIT_GET_REQUEST_START(x) \
+ (((x) >> BIT_SHIFT_REQUEST_START) & BIT_MASK_REQUEST_START)
+#define BIT_SET_REQUEST_START(x, v) \
+ (BIT_CLEAR_REQUEST_START(x) | BIT_REQUEST_START(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_COUNTER_OVERFLOW (Offset 0x11D0) */
+
+#define BIT_RTS_OVF BIT(8)
+#define BIT_PTCL_OVF BIT(7)
+#define BIT_SCH_OVF BIT(6)
+#define BIT_EDCA_OVF BIT(5)
+#define BIT_RQPN_OVF BIT(4)
+#define BIT_USB_OVF BIT(3)
+#define BIT_PCIE_OVF BIT(2)
+#define BIT_RXDMA_OVF BIT(1)
+#define BIT_TXDMA_OVF BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_COUNTER_OVERFLOW (Offset 0x11D0) */
+
+#define BIT_SHIFT_CNT_OVF_REG 0
+#define BIT_MASK_CNT_OVF_REG 0xffff
+#define BIT_CNT_OVF_REG(x) \
+ (((x) & BIT_MASK_CNT_OVF_REG) << BIT_SHIFT_CNT_OVF_REG)
+#define BITS_CNT_OVF_REG (BIT_MASK_CNT_OVF_REG << BIT_SHIFT_CNT_OVF_REG)
+#define BIT_CLEAR_CNT_OVF_REG(x) ((x) & (~BITS_CNT_OVF_REG))
+#define BIT_GET_CNT_OVF_REG(x) \
+ (((x) >> BIT_SHIFT_CNT_OVF_REG) & BIT_MASK_CNT_OVF_REG)
+#define BIT_SET_CNT_OVF_REG(x, v) \
+ (BIT_CLEAR_CNT_OVF_REG(x) | BIT_CNT_OVF_REG(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_TDE_LEN_TH (Offset 0x11D4) */
+
+#define BIT_SHIFT_TXDMA_LEN_TH0 16
+#define BIT_MASK_TXDMA_LEN_TH0 0xffff
+#define BIT_TXDMA_LEN_TH0(x) \
+ (((x) & BIT_MASK_TXDMA_LEN_TH0) << BIT_SHIFT_TXDMA_LEN_TH0)
+#define BITS_TXDMA_LEN_TH0 (BIT_MASK_TXDMA_LEN_TH0 << BIT_SHIFT_TXDMA_LEN_TH0)
+#define BIT_CLEAR_TXDMA_LEN_TH0(x) ((x) & (~BITS_TXDMA_LEN_TH0))
+#define BIT_GET_TXDMA_LEN_TH0(x) \
+ (((x) >> BIT_SHIFT_TXDMA_LEN_TH0) & BIT_MASK_TXDMA_LEN_TH0)
+#define BIT_SET_TXDMA_LEN_TH0(x, v) \
+ (BIT_CLEAR_TXDMA_LEN_TH0(x) | BIT_TXDMA_LEN_TH0(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TXDMA_LEN_THRESHOLD (Offset 0x11D4) */
+
+#define BIT_SHIFT_TDE_LEN_TH1 16
+#define BIT_MASK_TDE_LEN_TH1 0xffff
+#define BIT_TDE_LEN_TH1(x) \
+ (((x) & BIT_MASK_TDE_LEN_TH1) << BIT_SHIFT_TDE_LEN_TH1)
+#define BITS_TDE_LEN_TH1 (BIT_MASK_TDE_LEN_TH1 << BIT_SHIFT_TDE_LEN_TH1)
+#define BIT_CLEAR_TDE_LEN_TH1(x) ((x) & (~BITS_TDE_LEN_TH1))
+#define BIT_GET_TDE_LEN_TH1(x) \
+ (((x) >> BIT_SHIFT_TDE_LEN_TH1) & BIT_MASK_TDE_LEN_TH1)
+#define BIT_SET_TDE_LEN_TH1(x, v) \
+ (BIT_CLEAR_TDE_LEN_TH1(x) | BIT_TDE_LEN_TH1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_TDE_LEN_TH (Offset 0x11D4) */
+
+#define BIT_SHIFT_TXDMA_LEN_TH1 0
+#define BIT_MASK_TXDMA_LEN_TH1 0xffff
+#define BIT_TXDMA_LEN_TH1(x) \
+ (((x) & BIT_MASK_TXDMA_LEN_TH1) << BIT_SHIFT_TXDMA_LEN_TH1)
+#define BITS_TXDMA_LEN_TH1 (BIT_MASK_TXDMA_LEN_TH1 << BIT_SHIFT_TXDMA_LEN_TH1)
+#define BIT_CLEAR_TXDMA_LEN_TH1(x) ((x) & (~BITS_TXDMA_LEN_TH1))
+#define BIT_GET_TXDMA_LEN_TH1(x) \
+ (((x) >> BIT_SHIFT_TXDMA_LEN_TH1) & BIT_MASK_TXDMA_LEN_TH1)
+#define BIT_SET_TXDMA_LEN_TH1(x, v) \
+ (BIT_CLEAR_TXDMA_LEN_TH1(x) | BIT_TXDMA_LEN_TH1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TXDMA_LEN_THRESHOLD (Offset 0x11D4) */
+
+#define BIT_SHIFT_TDE_LEN_TH0 0
+#define BIT_MASK_TDE_LEN_TH0 0xffff
+#define BIT_TDE_LEN_TH0(x) \
+ (((x) & BIT_MASK_TDE_LEN_TH0) << BIT_SHIFT_TDE_LEN_TH0)
+#define BITS_TDE_LEN_TH0 (BIT_MASK_TDE_LEN_TH0 << BIT_SHIFT_TDE_LEN_TH0)
+#define BIT_CLEAR_TDE_LEN_TH0(x) ((x) & (~BITS_TDE_LEN_TH0))
+#define BIT_GET_TDE_LEN_TH0(x) \
+ (((x) >> BIT_SHIFT_TDE_LEN_TH0) & BIT_MASK_TDE_LEN_TH0)
+#define BIT_SET_TDE_LEN_TH0(x, v) \
+ (BIT_CLEAR_TDE_LEN_TH0(x) | BIT_TDE_LEN_TH0(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_RDE_LEN_TH (Offset 0x11D8) */
+
+#define BIT_SHIFT_RXDMA_LEN_TH0 16
+#define BIT_MASK_RXDMA_LEN_TH0 0xffff
+#define BIT_RXDMA_LEN_TH0(x) \
+ (((x) & BIT_MASK_RXDMA_LEN_TH0) << BIT_SHIFT_RXDMA_LEN_TH0)
+#define BITS_RXDMA_LEN_TH0 (BIT_MASK_RXDMA_LEN_TH0 << BIT_SHIFT_RXDMA_LEN_TH0)
+#define BIT_CLEAR_RXDMA_LEN_TH0(x) ((x) & (~BITS_RXDMA_LEN_TH0))
+#define BIT_GET_RXDMA_LEN_TH0(x) \
+ (((x) >> BIT_SHIFT_RXDMA_LEN_TH0) & BIT_MASK_RXDMA_LEN_TH0)
+#define BIT_SET_RXDMA_LEN_TH0(x, v) \
+ (BIT_CLEAR_RXDMA_LEN_TH0(x) | BIT_RXDMA_LEN_TH0(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RXDMA_LEN_THRESHOLD (Offset 0x11D8) */
+
+#define BIT_SHIFT_RDE_LEN_TH1 16
+#define BIT_MASK_RDE_LEN_TH1 0xffff
+#define BIT_RDE_LEN_TH1(x) \
+ (((x) & BIT_MASK_RDE_LEN_TH1) << BIT_SHIFT_RDE_LEN_TH1)
+#define BITS_RDE_LEN_TH1 (BIT_MASK_RDE_LEN_TH1 << BIT_SHIFT_RDE_LEN_TH1)
+#define BIT_CLEAR_RDE_LEN_TH1(x) ((x) & (~BITS_RDE_LEN_TH1))
+#define BIT_GET_RDE_LEN_TH1(x) \
+ (((x) >> BIT_SHIFT_RDE_LEN_TH1) & BIT_MASK_RDE_LEN_TH1)
+#define BIT_SET_RDE_LEN_TH1(x, v) \
+ (BIT_CLEAR_RDE_LEN_TH1(x) | BIT_RDE_LEN_TH1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_RDE_LEN_TH (Offset 0x11D8) */
+
+#define BIT_SHIFT_RXDMA_LEN_TH1 0
+#define BIT_MASK_RXDMA_LEN_TH1 0xffff
+#define BIT_RXDMA_LEN_TH1(x) \
+ (((x) & BIT_MASK_RXDMA_LEN_TH1) << BIT_SHIFT_RXDMA_LEN_TH1)
+#define BITS_RXDMA_LEN_TH1 (BIT_MASK_RXDMA_LEN_TH1 << BIT_SHIFT_RXDMA_LEN_TH1)
+#define BIT_CLEAR_RXDMA_LEN_TH1(x) ((x) & (~BITS_RXDMA_LEN_TH1))
+#define BIT_GET_RXDMA_LEN_TH1(x) \
+ (((x) >> BIT_SHIFT_RXDMA_LEN_TH1) & BIT_MASK_RXDMA_LEN_TH1)
+#define BIT_SET_RXDMA_LEN_TH1(x, v) \
+ (BIT_CLEAR_RXDMA_LEN_TH1(x) | BIT_RXDMA_LEN_TH1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RXDMA_LEN_THRESHOLD (Offset 0x11D8) */
+
+#define BIT_SHIFT_RDE_LEN_TH0 0
+#define BIT_MASK_RDE_LEN_TH0 0xffff
+#define BIT_RDE_LEN_TH0(x) \
+ (((x) & BIT_MASK_RDE_LEN_TH0) << BIT_SHIFT_RDE_LEN_TH0)
+#define BITS_RDE_LEN_TH0 (BIT_MASK_RDE_LEN_TH0 << BIT_SHIFT_RDE_LEN_TH0)
+#define BIT_CLEAR_RDE_LEN_TH0(x) ((x) & (~BITS_RDE_LEN_TH0))
+#define BIT_GET_RDE_LEN_TH0(x) \
+ (((x) >> BIT_SHIFT_RDE_LEN_TH0) & BIT_MASK_RDE_LEN_TH0)
+#define BIT_SET_RDE_LEN_TH0(x, v) \
+ (BIT_CLEAR_RDE_LEN_TH0(x) | BIT_RDE_LEN_TH0(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PCIE_EXEC_TIME (Offset 0x11DC) */
+
+#define BIT_SHIFT_COUNTER_INTERVAL_SEL 16
+#define BIT_MASK_COUNTER_INTERVAL_SEL 0x3
+#define BIT_COUNTER_INTERVAL_SEL(x) \
+ (((x) & BIT_MASK_COUNTER_INTERVAL_SEL) \
+ << BIT_SHIFT_COUNTER_INTERVAL_SEL)
+#define BITS_COUNTER_INTERVAL_SEL \
+ (BIT_MASK_COUNTER_INTERVAL_SEL << BIT_SHIFT_COUNTER_INTERVAL_SEL)
+#define BIT_CLEAR_COUNTER_INTERVAL_SEL(x) ((x) & (~BITS_COUNTER_INTERVAL_SEL))
+#define BIT_GET_COUNTER_INTERVAL_SEL(x) \
+ (((x) >> BIT_SHIFT_COUNTER_INTERVAL_SEL) & \
+ BIT_MASK_COUNTER_INTERVAL_SEL)
+#define BIT_SET_COUNTER_INTERVAL_SEL(x, v) \
+ (BIT_CLEAR_COUNTER_INTERVAL_SEL(x) | BIT_COUNTER_INTERVAL_SEL(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PCIE_EXEC_TIME_THRESHOLD (Offset 0x11DC) */
+
+#define BIT_SHIFT_COUNT_INT_SEL 16
+#define BIT_MASK_COUNT_INT_SEL 0x3
+#define BIT_COUNT_INT_SEL(x) \
+ (((x) & BIT_MASK_COUNT_INT_SEL) << BIT_SHIFT_COUNT_INT_SEL)
+#define BITS_COUNT_INT_SEL (BIT_MASK_COUNT_INT_SEL << BIT_SHIFT_COUNT_INT_SEL)
+#define BIT_CLEAR_COUNT_INT_SEL(x) ((x) & (~BITS_COUNT_INT_SEL))
+#define BIT_GET_COUNT_INT_SEL(x) \
+ (((x) >> BIT_SHIFT_COUNT_INT_SEL) & BIT_MASK_COUNT_INT_SEL)
+#define BIT_SET_COUNT_INT_SEL(x, v) \
+ (BIT_CLEAR_COUNT_INT_SEL(x) | BIT_COUNT_INT_SEL(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+/* 2 REG_PCIE_EXEC_TIME (Offset 0x11DC) */
+
+#define BIT_SHIFT_PCIE_TRANS_DATA_TH1 0
+#define BIT_MASK_PCIE_TRANS_DATA_TH1 0xffff
+#define BIT_PCIE_TRANS_DATA_TH1(x) \
+ (((x) & BIT_MASK_PCIE_TRANS_DATA_TH1) << BIT_SHIFT_PCIE_TRANS_DATA_TH1)
+#define BITS_PCIE_TRANS_DATA_TH1 \
+ (BIT_MASK_PCIE_TRANS_DATA_TH1 << BIT_SHIFT_PCIE_TRANS_DATA_TH1)
+#define BIT_CLEAR_PCIE_TRANS_DATA_TH1(x) ((x) & (~BITS_PCIE_TRANS_DATA_TH1))
+#define BIT_GET_PCIE_TRANS_DATA_TH1(x) \
+ (((x) >> BIT_SHIFT_PCIE_TRANS_DATA_TH1) & BIT_MASK_PCIE_TRANS_DATA_TH1)
+#define BIT_SET_PCIE_TRANS_DATA_TH1(x, v) \
+ (BIT_CLEAR_PCIE_TRANS_DATA_TH1(x) | BIT_PCIE_TRANS_DATA_TH1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PCIE_EXEC_TIME_THRESHOLD (Offset 0x11DC) */
+
+#define BIT_SHIFT_EXEC_TIME_TH 0
+#define BIT_MASK_EXEC_TIME_TH 0xffff
+#define BIT_EXEC_TIME_TH(x) \
+ (((x) & BIT_MASK_EXEC_TIME_TH) << BIT_SHIFT_EXEC_TIME_TH)
+#define BITS_EXEC_TIME_TH (BIT_MASK_EXEC_TIME_TH << BIT_SHIFT_EXEC_TIME_TH)
+#define BIT_CLEAR_EXEC_TIME_TH(x) ((x) & (~BITS_EXEC_TIME_TH))
+#define BIT_GET_EXEC_TIME_TH(x) \
+ (((x) >> BIT_SHIFT_EXEC_TIME_TH) & BIT_MASK_EXEC_TIME_TH)
+#define BIT_SET_EXEC_TIME_TH(x, v) \
+ (BIT_CLEAR_EXEC_TIME_TH(x) | BIT_EXEC_TIME_TH(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_PORT4_RX_UCMD1_UAPSD0_OK_INT_EN BIT(31)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_FS_CLI3_RX_UAPSDMD1_EN BIT(31)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_PORT4_RX_UCMD0_UAPSD0_OK_INT_EN BIT(30)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_FS_CLI3_RX_UAPSDMD0_EN BIT(30)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_PORT4_TRIPKT_OK_INT_EN BIT(29)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_FS_CLI3_TRIGGER_PKT_EN BIT(29)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_PORT4_RX_EOSP_OK_INT_EN BIT(28)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_FS_CLI3_EOSP_INT_EN BIT(28)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_PORT3_RX_UCMD1_UAPSD0_OK_INT_EN BIT(27)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_FS_CLI2_RX_UAPSDMD1_EN BIT(27)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_PORT3_RX_UCMD0_UAPSD0_OK_INT_EN BIT(26)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_FS_CLI2_RX_UAPSDMD0_EN BIT(26)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_PORT3_TRIPKT_OK_INT_EN BIT(25)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_FS_CLI2_TRIGGER_PKT_EN BIT(25)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_PORT3_RX_EOSP_OK_INT_EN BIT(24)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_FS_CLI2_EOSP_INT_EN BIT(24)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_PORT2_RX_UCMD1_UAPSD0_OK_INT_EN BIT(23)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_FS_CLI1_RX_UAPSDMD1_EN BIT(23)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_PORT2_RX_UCMD0_UAPSD0_OK_INT_EN BIT(22)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_FS_CLI1_RX_UAPSDMD0_EN BIT(22)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_PORT2_TRIPKT_OK_INT_EN BIT(21)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_FS_CLI1_TRIGGER_PKT_EN BIT(21)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_PORT2_RX_EOSP_OK_INT_EN BIT(20)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_FS_CLI1_EOSP_INT_EN BIT(20)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_PORT1_RX_UCMD1_UAPSD0_OK_INT_EN BIT(19)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_FS_CLI0_RX_UAPSDMD1_EN BIT(19)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_PORT1_RX_UCMD0_UAPSD0_OK_INT_EN BIT(18)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_FS_CLI0_RX_UAPSDMD0_EN BIT(18)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_PORT1_TRIPKT_OK_INT_EN BIT(17)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_FS_CLI0_TRIGGER_PKT_EN BIT(17)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_PORT1_RX_EOSP_OK_INT_EN BIT(16)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_FS_CLI0_EOSP_INT_EN BIT(16)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_NOA2_TSFT_BIT32_TOGGLE_INT_EN BIT(9)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_EN BIT(9)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_NOA1_TSFT_BIT32_TOGGLE_INT_EN BIT(8)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_EN BIT(8)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_PORT4_TX_NULL1_DONE_INT_EN BIT(7)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_FS_CLI3_TX_NULL1_INT_EN BIT(7)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_PORT4_TX_NULL0_DONE_INT_EN BIT(6)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_FS_CLI3_TX_NULL0_INT_EN BIT(6)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_PORT3_TX_NULL1_DONE_INT_EN BIT(5)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_FS_CLI2_TX_NULL1_INT_EN BIT(5)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_PORT3_TX_NULL0_DONE_INT_EN BIT(4)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_FS_CLI2_TX_NULL0_INT_EN BIT(4)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_PORT2_TX_NULL1_DONE_INT_EN BIT(3)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_FS_CLI1_TX_NULL1_INT_EN BIT(3)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_PORT2_TX_NULL0_DONE_INT_EN BIT(2)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_FS_CLI1_TX_NULL0_INT_EN BIT(2)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_PORT1_TX_NULL1_DONE_INT_EN BIT(1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_FS_CLI0_TX_NULL1_INT_EN BIT(1)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_PORT1_TX_NULL0_DONE_INT_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2IMR (Offset 0x11E0) */
+
+#define BIT_FS_CLI0_TX_NULL0_INT_EN BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_PORT4_RX_UCMD1_UAPSD0_OK_INT BIT(31)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_FS_CLI3_RX_UAPSDMD1_INT BIT(31)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_PORT4_RX_UCMD0_UAPSD0_OK_INT BIT(30)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_FS_CLI3_RX_UAPSDMD0_INT BIT(30)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_PORT4_TRIPKT_OK_INT BIT(29)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_FS_CLI3_TRIGGER_PKT_INT BIT(29)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_PORT4_RX_EOSP_OK_INT BIT(28)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_FS_CLI3_EOSP_INT BIT(28)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_PORT3_RX_UCMD1_UAPSD0_OK_INT BIT(27)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_FS_CLI2_RX_UAPSDMD1_INT BIT(27)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_PORT3_RX_UCMD0_UAPSD0_OK_INT BIT(26)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_FS_CLI2_RX_UAPSDMD0_INT BIT(26)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_PORT3_TRIPKT_OK_INT BIT(25)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_FS_CLI2_TRIGGER_PKT_INT BIT(25)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_PORT3_RX_EOSP_OK_INT BIT(24)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_FS_CLI2_EOSP_INT BIT(24)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_PORT2_RX_UCMD1_UAPSD0_OK_INT BIT(23)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_FS_CLI1_RX_UAPSDMD1_INT BIT(23)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_PORT2_RX_UCMD0_UAPSD0_OK_INT BIT(22)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_FS_CLI1_RX_UAPSDMD0_INT BIT(22)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_PORT2_TRIPKT_OK_INT BIT(21)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_FS_CLI1_TRIGGER_PKT_INT BIT(21)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_PORT2_RX_EOSP_OK_INT BIT(20)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_FS_CLI1_EOSP_INT BIT(20)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_PORT1_RX_UCMD1_UAPSD0_OK_INT BIT(19)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_FS_CLI0_RX_UAPSDMD1_INT BIT(19)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_PORT1_RX_UCMD0_UAPSD0_OK_INT BIT(18)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_FS_CLI0_RX_UAPSDMD0_INT BIT(18)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_PORT1_TRIPKT_OK_INT BIT(17)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_FS_CLI0_TRIGGER_PKT_INT BIT(17)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_PORT1_RX_EOSP_OK_INT BIT(16)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_FS_CLI0_EOSP_INT BIT(16)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_NOA2_TSFT_BIT32_TOGGLE_INT BIT(9)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_INT BIT(9)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_NOA1_TSFT_BIT32_TOGGLE_INT BIT(8)
+
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+/* 2 REG_FT2ISR (Offset 0x11E4) */
-#define BIT_FS_CLI0_TX_NULL1_INT_EN BIT(1)
+#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_INT BIT(8)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+#define BIT_PORT4_TX_NULL1_DONE_INT BIT(7)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR (Offset 0x11E4) */
-#define BIT_PORT1_TX_NULL0_DONE_INT_EN BIT(0)
+#define BIT_FS_CLI3_TX_NULL1_INT BIT(7)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+#define BIT_PORT4_TX_NULL0_DONE_INT BIT(6)
-/* 2 REG_FT2IMR (Offset 0x11E0) */
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_FT2ISR (Offset 0x11E4) */
-#define BIT_FS_CLI0_TX_NULL0_INT_EN BIT(0)
+#define BIT_FS_CLI3_TX_NULL0_INT BIT(6)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_PORT3_TX_NULL1_DONE_INT BIT(5)
+
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_FT2ISR (Offset 0x11E4) */
-#define BIT_PORT4_RX_UCMD1_UAPSD0_OK_INT BIT(31)
+#define BIT_FS_CLI2_TX_NULL1_INT BIT(5)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_PORT3_TX_NULL0_DONE_INT BIT(4)
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_FT2ISR (Offset 0x11E4) */
-#define BIT_FS_CLI3_RX_UAPSDMD1_INT BIT(31)
+#define BIT_FS_CLI2_TX_NULL0_INT BIT(4)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+#define BIT_PORT2_TX_NULL1_DONE_INT BIT(3)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_FT2ISR (Offset 0x11E4) */
-#define BIT_PORT4_RX_UCMD0_UAPSD0_OK_INT BIT(30)
+#define BIT_FS_CLI1_TX_NULL1_INT BIT(3)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_PORT2_TX_NULL0_DONE_INT BIT(2)
+
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_FT2ISR (Offset 0x11E4) */
-#define BIT_FS_CLI3_RX_UAPSDMD0_INT BIT(30)
+#define BIT_FS_CLI1_TX_NULL0_INT BIT(2)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_PORT1_TX_NULL1_DONE_INT BIT(1)
+
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_FT2ISR (Offset 0x11E4) */
-#define BIT_PORT4_TRIPKT_OK_INT BIT(29)
+#define BIT_FS_CLI0_TX_NULL1_INT BIT(1)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FT2ISR (Offset 0x11E4) */
+
+#define BIT_PORT1_TX_NULL0_DONE_INT BIT(0)
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
/* 2 REG_FT2ISR (Offset 0x11E4) */
-#define BIT_FS_CLI3_TRIGGER_PKT_INT BIT(29)
+#define BIT_FS_CLI0_TX_NULL0_INT BIT(0)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_MSG2 (Offset 0x11F0) */
+#define BIT_SHIFT_FW_MSG2 0
+#define BIT_MASK_FW_MSG2 0xffffffffL
+#define BIT_FW_MSG2(x) (((x) & BIT_MASK_FW_MSG2) << BIT_SHIFT_FW_MSG2)
+#define BITS_FW_MSG2 (BIT_MASK_FW_MSG2 << BIT_SHIFT_FW_MSG2)
+#define BIT_CLEAR_FW_MSG2(x) ((x) & (~BITS_FW_MSG2))
+#define BIT_GET_FW_MSG2(x) (((x) >> BIT_SHIFT_FW_MSG2) & BIT_MASK_FW_MSG2)
+#define BIT_SET_FW_MSG2(x, v) (BIT_CLEAR_FW_MSG2(x) | BIT_FW_MSG2(v))
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+/* 2 REG_MSG3 (Offset 0x11F4) */
+
+#define BIT_SHIFT_FW_MSG3 0
+#define BIT_MASK_FW_MSG3 0xffffffffL
+#define BIT_FW_MSG3(x) (((x) & BIT_MASK_FW_MSG3) << BIT_SHIFT_FW_MSG3)
+#define BITS_FW_MSG3 (BIT_MASK_FW_MSG3 << BIT_SHIFT_FW_MSG3)
+#define BIT_CLEAR_FW_MSG3(x) ((x) & (~BITS_FW_MSG3))
+#define BIT_GET_FW_MSG3(x) (((x) >> BIT_SHIFT_FW_MSG3) & BIT_MASK_FW_MSG3)
+#define BIT_SET_FW_MSG3(x, v) (BIT_CLEAR_FW_MSG3(x) | BIT_FW_MSG3(v))
+
+/* 2 REG_MSG4 (Offset 0x11F8) */
+
+#define BIT_SHIFT_FW_MSG4 0
+#define BIT_MASK_FW_MSG4 0xffffffffL
+#define BIT_FW_MSG4(x) (((x) & BIT_MASK_FW_MSG4) << BIT_SHIFT_FW_MSG4)
+#define BITS_FW_MSG4 (BIT_MASK_FW_MSG4 << BIT_SHIFT_FW_MSG4)
+#define BIT_CLEAR_FW_MSG4(x) ((x) & (~BITS_FW_MSG4))
+#define BIT_GET_FW_MSG4(x) (((x) >> BIT_SHIFT_FW_MSG4) & BIT_MASK_FW_MSG4)
+#define BIT_SET_FW_MSG4(x, v) (BIT_CLEAR_FW_MSG4(x) | BIT_FW_MSG4(v))
+
+/* 2 REG_MSG5 (Offset 0x11FC) */
+
+#define BIT_SHIFT_FW_MSG5 0
+#define BIT_MASK_FW_MSG5 0xffffffffL
+#define BIT_FW_MSG5(x) (((x) & BIT_MASK_FW_MSG5) << BIT_SHIFT_FW_MSG5)
+#define BITS_FW_MSG5 (BIT_MASK_FW_MSG5 << BIT_SHIFT_FW_MSG5)
+#define BIT_CLEAR_FW_MSG5(x) ((x) & (~BITS_FW_MSG5))
+#define BIT_GET_FW_MSG5(x) (((x) >> BIT_SHIFT_FW_MSG5) & BIT_MASK_FW_MSG5)
+#define BIT_SET_FW_MSG5(x, v) (BIT_CLEAR_FW_MSG5(x) | BIT_FW_MSG5(v))
+
+/* 2 REG_DDMA_CH0SA (Offset 0x1200) */
+
+#define BIT_SHIFT_DDMACH0_SA 0
+#define BIT_MASK_DDMACH0_SA 0xffffffffL
+#define BIT_DDMACH0_SA(x) (((x) & BIT_MASK_DDMACH0_SA) << BIT_SHIFT_DDMACH0_SA)
+#define BITS_DDMACH0_SA (BIT_MASK_DDMACH0_SA << BIT_SHIFT_DDMACH0_SA)
+#define BIT_CLEAR_DDMACH0_SA(x) ((x) & (~BITS_DDMACH0_SA))
+#define BIT_GET_DDMACH0_SA(x) \
+ (((x) >> BIT_SHIFT_DDMACH0_SA) & BIT_MASK_DDMACH0_SA)
+#define BIT_SET_DDMACH0_SA(x, v) (BIT_CLEAR_DDMACH0_SA(x) | BIT_DDMACH0_SA(v))
+
+/* 2 REG_DDMA_CH0DA (Offset 0x1204) */
+
+#define BIT_SHIFT_DDMACH0_DA 0
+#define BIT_MASK_DDMACH0_DA 0xffffffffL
+#define BIT_DDMACH0_DA(x) (((x) & BIT_MASK_DDMACH0_DA) << BIT_SHIFT_DDMACH0_DA)
+#define BITS_DDMACH0_DA (BIT_MASK_DDMACH0_DA << BIT_SHIFT_DDMACH0_DA)
+#define BIT_CLEAR_DDMACH0_DA(x) ((x) & (~BITS_DDMACH0_DA))
+#define BIT_GET_DDMACH0_DA(x) \
+ (((x) >> BIT_SHIFT_DDMACH0_DA) & BIT_MASK_DDMACH0_DA)
+#define BIT_SET_DDMACH0_DA(x, v) (BIT_CLEAR_DDMACH0_DA(x) | BIT_DDMACH0_DA(v))
+
+/* 2 REG_DDMA_CH0CTRL (Offset 0x1208) */
+
+#define BIT_DDMACH0_OWN BIT(31)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_DDMA_CH0CTRL (Offset 0x1208) */
+
+#define BIT_DDMACH0_ERR_MON BIT(30)
+
+#endif
+
+#if (HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DDMA_CH0CTRL (Offset 0x1208) */
+
+#define BIT_DDMACH0_IDMEM_ERR BIT(30)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DDMA_CH0CTRL (Offset 0x1208) */
+
+#define BIT_DDMACH0_CHKSUM_EN BIT(29)
+#define BIT_DDMACH0_DA_W_DISABLE BIT(28)
+#define BIT_DDMACH0_CHKSUM_STS BIT(27)
+#define BIT_DDMACH0_DDMA_MODE BIT(26)
+#define BIT_DDMACH0_RESET_CHKSUM_STS BIT(25)
+#define BIT_DDMACH0_CHKSUM_CONT BIT(24)
+
+#define BIT_SHIFT_DDMACH0_DLEN 0
+#define BIT_MASK_DDMACH0_DLEN 0x3ffff
+#define BIT_DDMACH0_DLEN(x) \
+ (((x) & BIT_MASK_DDMACH0_DLEN) << BIT_SHIFT_DDMACH0_DLEN)
+#define BITS_DDMACH0_DLEN (BIT_MASK_DDMACH0_DLEN << BIT_SHIFT_DDMACH0_DLEN)
+#define BIT_CLEAR_DDMACH0_DLEN(x) ((x) & (~BITS_DDMACH0_DLEN))
+#define BIT_GET_DDMACH0_DLEN(x) \
+ (((x) >> BIT_SHIFT_DDMACH0_DLEN) & BIT_MASK_DDMACH0_DLEN)
+#define BIT_SET_DDMACH0_DLEN(x, v) \
+ (BIT_CLEAR_DDMACH0_DLEN(x) | BIT_DDMACH0_DLEN(v))
+
+/* 2 REG_DDMA_CH1SA (Offset 0x1210) */
+
+#define BIT_SHIFT_DDMACH1_SA 0
+#define BIT_MASK_DDMACH1_SA 0xffffffffL
+#define BIT_DDMACH1_SA(x) (((x) & BIT_MASK_DDMACH1_SA) << BIT_SHIFT_DDMACH1_SA)
+#define BITS_DDMACH1_SA (BIT_MASK_DDMACH1_SA << BIT_SHIFT_DDMACH1_SA)
+#define BIT_CLEAR_DDMACH1_SA(x) ((x) & (~BITS_DDMACH1_SA))
+#define BIT_GET_DDMACH1_SA(x) \
+ (((x) >> BIT_SHIFT_DDMACH1_SA) & BIT_MASK_DDMACH1_SA)
+#define BIT_SET_DDMACH1_SA(x, v) (BIT_CLEAR_DDMACH1_SA(x) | BIT_DDMACH1_SA(v))
+
+/* 2 REG_DDMA_CH1DA (Offset 0x1214) */
+
+#define BIT_SHIFT_DDMACH1_DA 0
+#define BIT_MASK_DDMACH1_DA 0xffffffffL
+#define BIT_DDMACH1_DA(x) (((x) & BIT_MASK_DDMACH1_DA) << BIT_SHIFT_DDMACH1_DA)
+#define BITS_DDMACH1_DA (BIT_MASK_DDMACH1_DA << BIT_SHIFT_DDMACH1_DA)
+#define BIT_CLEAR_DDMACH1_DA(x) ((x) & (~BITS_DDMACH1_DA))
+#define BIT_GET_DDMACH1_DA(x) \
+ (((x) >> BIT_SHIFT_DDMACH1_DA) & BIT_MASK_DDMACH1_DA)
+#define BIT_SET_DDMACH1_DA(x, v) (BIT_CLEAR_DDMACH1_DA(x) | BIT_DDMACH1_DA(v))
+
+/* 2 REG_DDMA_CH1CTRL (Offset 0x1218) */
+
+#define BIT_DDMACH1_OWN BIT(31)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_DDMA_CH1CTRL (Offset 0x1218) */
+
+#define BIT_DDMACH1_ERR_MON BIT(30)
+
+#endif
+
+#if (HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DDMA_CH1CTRL (Offset 0x1218) */
+
+#define BIT_DDMACH1_IDMEM_ERR BIT(30)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DDMA_CH1CTRL (Offset 0x1218) */
+
+#define BIT_DDMACH1_CHKSUM_EN BIT(29)
+#define BIT_DDMACH1_DA_W_DISABLE BIT(28)
+#define BIT_DDMACH1_CHKSUM_STS BIT(27)
+#define BIT_DDMACH1_DDMA_MODE BIT(26)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
+
+/* 2 REG_DDMA_CH1CTRL (Offset 0x1218) */
+
+#define BIT_DDMACH1_RESET_CHKSUM_STS BIT(25)
+#define BIT_DDMACH1_CHKSUM_CONT BIT(24)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DDMA_CH1CTRL (Offset 0x1218) */
+
+#define BIT_SHIFT_DDMACH1_DLEN 0
+#define BIT_MASK_DDMACH1_DLEN 0x3ffff
+#define BIT_DDMACH1_DLEN(x) \
+ (((x) & BIT_MASK_DDMACH1_DLEN) << BIT_SHIFT_DDMACH1_DLEN)
+#define BITS_DDMACH1_DLEN (BIT_MASK_DDMACH1_DLEN << BIT_SHIFT_DDMACH1_DLEN)
+#define BIT_CLEAR_DDMACH1_DLEN(x) ((x) & (~BITS_DDMACH1_DLEN))
+#define BIT_GET_DDMACH1_DLEN(x) \
+ (((x) >> BIT_SHIFT_DDMACH1_DLEN) & BIT_MASK_DDMACH1_DLEN)
+#define BIT_SET_DDMACH1_DLEN(x, v) \
+ (BIT_CLEAR_DDMACH1_DLEN(x) | BIT_DDMACH1_DLEN(v))
+
+/* 2 REG_DDMA_CH2SA (Offset 0x1220) */
+
+#define BIT_SHIFT_DDMACH2_SA 0
+#define BIT_MASK_DDMACH2_SA 0xffffffffL
+#define BIT_DDMACH2_SA(x) (((x) & BIT_MASK_DDMACH2_SA) << BIT_SHIFT_DDMACH2_SA)
+#define BITS_DDMACH2_SA (BIT_MASK_DDMACH2_SA << BIT_SHIFT_DDMACH2_SA)
+#define BIT_CLEAR_DDMACH2_SA(x) ((x) & (~BITS_DDMACH2_SA))
+#define BIT_GET_DDMACH2_SA(x) \
+ (((x) >> BIT_SHIFT_DDMACH2_SA) & BIT_MASK_DDMACH2_SA)
+#define BIT_SET_DDMACH2_SA(x, v) (BIT_CLEAR_DDMACH2_SA(x) | BIT_DDMACH2_SA(v))
+
+/* 2 REG_DDMA_CH2DA (Offset 0x1224) */
-#define BIT_PORT4_RX_EOSP_OK_INT BIT(28)
+#define BIT_SHIFT_DDMACH2_DA 0
+#define BIT_MASK_DDMACH2_DA 0xffffffffL
+#define BIT_DDMACH2_DA(x) (((x) & BIT_MASK_DDMACH2_DA) << BIT_SHIFT_DDMACH2_DA)
+#define BITS_DDMACH2_DA (BIT_MASK_DDMACH2_DA << BIT_SHIFT_DDMACH2_DA)
+#define BIT_CLEAR_DDMACH2_DA(x) ((x) & (~BITS_DDMACH2_DA))
+#define BIT_GET_DDMACH2_DA(x) \
+ (((x) >> BIT_SHIFT_DDMACH2_DA) & BIT_MASK_DDMACH2_DA)
+#define BIT_SET_DDMACH2_DA(x, v) (BIT_CLEAR_DDMACH2_DA(x) | BIT_DDMACH2_DA(v))
+
+/* 2 REG_DDMA_CH2CTRL (Offset 0x1228) */
+
+#define BIT_DDMACH2_OWN BIT(31)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_DDMA_CH2CTRL (Offset 0x1228) */
+
+#define BIT_DDMACH2_ERR_MON BIT(30)
+
+#endif
+
+#if (HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DDMA_CH2CTRL (Offset 0x1228) */
+
+#define BIT_DDMACH2_IDMEM_ERR BIT(30)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DDMA_CH2CTRL (Offset 0x1228) */
+
+#define BIT_DDMACH2_CHKSUM_EN BIT(29)
+#define BIT_DDMACH2_DA_W_DISABLE BIT(28)
+#define BIT_DDMACH2_CHKSUM_STS BIT(27)
+#define BIT_DDMACH2_DDMA_MODE BIT(26)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
+
+/* 2 REG_DDMA_CH2CTRL (Offset 0x1228) */
+
+#define BIT_DDMACH2_RESET_CHKSUM_STS BIT(25)
+#define BIT_DDMACH2_CHKSUM_CONT BIT(24)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DDMA_CH2CTRL (Offset 0x1228) */
+
+#define BIT_SHIFT_DDMACH2_DLEN 0
+#define BIT_MASK_DDMACH2_DLEN 0x3ffff
+#define BIT_DDMACH2_DLEN(x) \
+ (((x) & BIT_MASK_DDMACH2_DLEN) << BIT_SHIFT_DDMACH2_DLEN)
+#define BITS_DDMACH2_DLEN (BIT_MASK_DDMACH2_DLEN << BIT_SHIFT_DDMACH2_DLEN)
+#define BIT_CLEAR_DDMACH2_DLEN(x) ((x) & (~BITS_DDMACH2_DLEN))
+#define BIT_GET_DDMACH2_DLEN(x) \
+ (((x) >> BIT_SHIFT_DDMACH2_DLEN) & BIT_MASK_DDMACH2_DLEN)
+#define BIT_SET_DDMACH2_DLEN(x, v) \
+ (BIT_CLEAR_DDMACH2_DLEN(x) | BIT_DDMACH2_DLEN(v))
+
+/* 2 REG_DDMA_CH3SA (Offset 0x1230) */
+
+#define BIT_SHIFT_DDMACH3_SA 0
+#define BIT_MASK_DDMACH3_SA 0xffffffffL
+#define BIT_DDMACH3_SA(x) (((x) & BIT_MASK_DDMACH3_SA) << BIT_SHIFT_DDMACH3_SA)
+#define BITS_DDMACH3_SA (BIT_MASK_DDMACH3_SA << BIT_SHIFT_DDMACH3_SA)
+#define BIT_CLEAR_DDMACH3_SA(x) ((x) & (~BITS_DDMACH3_SA))
+#define BIT_GET_DDMACH3_SA(x) \
+ (((x) >> BIT_SHIFT_DDMACH3_SA) & BIT_MASK_DDMACH3_SA)
+#define BIT_SET_DDMACH3_SA(x, v) (BIT_CLEAR_DDMACH3_SA(x) | BIT_DDMACH3_SA(v))
+
+/* 2 REG_DDMA_CH3DA (Offset 0x1234) */
+
+#define BIT_SHIFT_DDMACH3_DA 0
+#define BIT_MASK_DDMACH3_DA 0xffffffffL
+#define BIT_DDMACH3_DA(x) (((x) & BIT_MASK_DDMACH3_DA) << BIT_SHIFT_DDMACH3_DA)
+#define BITS_DDMACH3_DA (BIT_MASK_DDMACH3_DA << BIT_SHIFT_DDMACH3_DA)
+#define BIT_CLEAR_DDMACH3_DA(x) ((x) & (~BITS_DDMACH3_DA))
+#define BIT_GET_DDMACH3_DA(x) \
+ (((x) >> BIT_SHIFT_DDMACH3_DA) & BIT_MASK_DDMACH3_DA)
+#define BIT_SET_DDMACH3_DA(x, v) (BIT_CLEAR_DDMACH3_DA(x) | BIT_DDMACH3_DA(v))
+
+/* 2 REG_DDMA_CH3CTRL (Offset 0x1238) */
+
+#define BIT_DDMACH3_OWN BIT(31)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_DDMA_CH3CTRL (Offset 0x1238) */
+
+#define BIT_DDMACH3_ERR_MON BIT(30)
+
+#endif
+
+#if (HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DDMA_CH3CTRL (Offset 0x1238) */
+
+#define BIT_DDMACH3_IDMEM_ERR BIT(30)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DDMA_CH3CTRL (Offset 0x1238) */
+
+#define BIT_DDMACH3_CHKSUM_EN BIT(29)
+#define BIT_DDMACH3_DA_W_DISABLE BIT(28)
+#define BIT_DDMACH3_CHKSUM_STS BIT(27)
+#define BIT_DDMACH3_DDMA_MODE BIT(26)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
+
+/* 2 REG_DDMA_CH3CTRL (Offset 0x1238) */
+
+#define BIT_DDMACH3_RESET_CHKSUM_STS BIT(25)
+#define BIT_DDMACH3_CHKSUM_CONT BIT(24)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DDMA_CH3CTRL (Offset 0x1238) */
+
+#define BIT_SHIFT_DDMACH3_DLEN 0
+#define BIT_MASK_DDMACH3_DLEN 0x3ffff
+#define BIT_DDMACH3_DLEN(x) \
+ (((x) & BIT_MASK_DDMACH3_DLEN) << BIT_SHIFT_DDMACH3_DLEN)
+#define BITS_DDMACH3_DLEN (BIT_MASK_DDMACH3_DLEN << BIT_SHIFT_DDMACH3_DLEN)
+#define BIT_CLEAR_DDMACH3_DLEN(x) ((x) & (~BITS_DDMACH3_DLEN))
+#define BIT_GET_DDMACH3_DLEN(x) \
+ (((x) >> BIT_SHIFT_DDMACH3_DLEN) & BIT_MASK_DDMACH3_DLEN)
+#define BIT_SET_DDMACH3_DLEN(x, v) \
+ (BIT_CLEAR_DDMACH3_DLEN(x) | BIT_DDMACH3_DLEN(v))
+
+/* 2 REG_DDMA_CH4SA (Offset 0x1240) */
+
+#define BIT_SHIFT_DDMACH4_SA 0
+#define BIT_MASK_DDMACH4_SA 0xffffffffL
+#define BIT_DDMACH4_SA(x) (((x) & BIT_MASK_DDMACH4_SA) << BIT_SHIFT_DDMACH4_SA)
+#define BITS_DDMACH4_SA (BIT_MASK_DDMACH4_SA << BIT_SHIFT_DDMACH4_SA)
+#define BIT_CLEAR_DDMACH4_SA(x) ((x) & (~BITS_DDMACH4_SA))
+#define BIT_GET_DDMACH4_SA(x) \
+ (((x) >> BIT_SHIFT_DDMACH4_SA) & BIT_MASK_DDMACH4_SA)
+#define BIT_SET_DDMACH4_SA(x, v) (BIT_CLEAR_DDMACH4_SA(x) | BIT_DDMACH4_SA(v))
+
+/* 2 REG_DDMA_CH4DA (Offset 0x1244) */
+
+#define BIT_SHIFT_DDMACH4_DA 0
+#define BIT_MASK_DDMACH4_DA 0xffffffffL
+#define BIT_DDMACH4_DA(x) (((x) & BIT_MASK_DDMACH4_DA) << BIT_SHIFT_DDMACH4_DA)
+#define BITS_DDMACH4_DA (BIT_MASK_DDMACH4_DA << BIT_SHIFT_DDMACH4_DA)
+#define BIT_CLEAR_DDMACH4_DA(x) ((x) & (~BITS_DDMACH4_DA))
+#define BIT_GET_DDMACH4_DA(x) \
+ (((x) >> BIT_SHIFT_DDMACH4_DA) & BIT_MASK_DDMACH4_DA)
+#define BIT_SET_DDMACH4_DA(x, v) (BIT_CLEAR_DDMACH4_DA(x) | BIT_DDMACH4_DA(v))
+
+/* 2 REG_DDMA_CH4CTRL (Offset 0x1248) */
+
+#define BIT_DDMACH4_OWN BIT(31)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_DDMA_CH4CTRL (Offset 0x1248) */
+
+#define BIT_DDMACH4_ERR_MON BIT(30)
+
+#endif
+
+#if (HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DDMA_CH4CTRL (Offset 0x1248) */
+
+#define BIT_DDMACH4_IDMEM_ERR BIT(30)
+#define BIT_DDMACH5_IDMEM_ERR BIT(30)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DDMA_CH4CTRL (Offset 0x1248) */
+
+#define BIT_DDMACH4_CHKSUM_EN BIT(29)
+#define BIT_DDMACH4_DA_W_DISABLE BIT(28)
+#define BIT_DDMACH4_CHKSUM_STS BIT(27)
+#define BIT_DDMACH4_DDMA_MODE BIT(26)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
+
+/* 2 REG_DDMA_CH4CTRL (Offset 0x1248) */
+
+#define BIT_DDMACH4_RESET_CHKSUM_STS BIT(25)
+#define BIT_DDMACH5_RESET_CHKSUM_STS BIT(25)
+#define BIT_DDMACH4_CHKSUM_CONT BIT(24)
+#define BIT_DDMACH5_CHKSUM_CONT BIT(24)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DDMA_CH4CTRL (Offset 0x1248) */
+
+#define BIT_SHIFT_DDMACH4_DLEN 0
+#define BIT_MASK_DDMACH4_DLEN 0x3ffff
+#define BIT_DDMACH4_DLEN(x) \
+ (((x) & BIT_MASK_DDMACH4_DLEN) << BIT_SHIFT_DDMACH4_DLEN)
+#define BITS_DDMACH4_DLEN (BIT_MASK_DDMACH4_DLEN << BIT_SHIFT_DDMACH4_DLEN)
+#define BIT_CLEAR_DDMACH4_DLEN(x) ((x) & (~BITS_DDMACH4_DLEN))
+#define BIT_GET_DDMACH4_DLEN(x) \
+ (((x) >> BIT_SHIFT_DDMACH4_DLEN) & BIT_MASK_DDMACH4_DLEN)
+#define BIT_SET_DDMACH4_DLEN(x, v) \
+ (BIT_CLEAR_DDMACH4_DLEN(x) | BIT_DDMACH4_DLEN(v))
+
+/* 2 REG_DDMA_CH5SA (Offset 0x1250) */
+
+#define BIT_SHIFT_DDMACH5_SA 0
+#define BIT_MASK_DDMACH5_SA 0xffffffffL
+#define BIT_DDMACH5_SA(x) (((x) & BIT_MASK_DDMACH5_SA) << BIT_SHIFT_DDMACH5_SA)
+#define BITS_DDMACH5_SA (BIT_MASK_DDMACH5_SA << BIT_SHIFT_DDMACH5_SA)
+#define BIT_CLEAR_DDMACH5_SA(x) ((x) & (~BITS_DDMACH5_SA))
+#define BIT_GET_DDMACH5_SA(x) \
+ (((x) >> BIT_SHIFT_DDMACH5_SA) & BIT_MASK_DDMACH5_SA)
+#define BIT_SET_DDMACH5_SA(x, v) (BIT_CLEAR_DDMACH5_SA(x) | BIT_DDMACH5_SA(v))
+
+/* 2 REG_DDMA_CH5DA (Offset 0x1254) */
+
+#define BIT_DDMACH5_OWN BIT(31)
+#define BIT_DDMACH5_CHKSUM_EN BIT(29)
+#define BIT_DDMACH5_DA_W_DISABLE BIT(28)
+#define BIT_DDMACH5_CHKSUM_STS BIT(27)
+#define BIT_DDMACH5_DDMA_MODE BIT(26)
+
+#define BIT_SHIFT_DDMACH5_DA 0
+#define BIT_MASK_DDMACH5_DA 0xffffffffL
+#define BIT_DDMACH5_DA(x) (((x) & BIT_MASK_DDMACH5_DA) << BIT_SHIFT_DDMACH5_DA)
+#define BITS_DDMACH5_DA (BIT_MASK_DDMACH5_DA << BIT_SHIFT_DDMACH5_DA)
+#define BIT_CLEAR_DDMACH5_DA(x) ((x) & (~BITS_DDMACH5_DA))
+#define BIT_GET_DDMACH5_DA(x) \
+ (((x) >> BIT_SHIFT_DDMACH5_DA) & BIT_MASK_DDMACH5_DA)
+#define BIT_SET_DDMACH5_DA(x, v) (BIT_CLEAR_DDMACH5_DA(x) | BIT_DDMACH5_DA(v))
+
+#define BIT_SHIFT_DDMACH5_DLEN 0
+#define BIT_MASK_DDMACH5_DLEN 0x3ffff
+#define BIT_DDMACH5_DLEN(x) \
+ (((x) & BIT_MASK_DDMACH5_DLEN) << BIT_SHIFT_DDMACH5_DLEN)
+#define BITS_DDMACH5_DLEN (BIT_MASK_DDMACH5_DLEN << BIT_SHIFT_DDMACH5_DLEN)
+#define BIT_CLEAR_DDMACH5_DLEN(x) ((x) & (~BITS_DDMACH5_DLEN))
+#define BIT_GET_DDMACH5_DLEN(x) \
+ (((x) >> BIT_SHIFT_DDMACH5_DLEN) & BIT_MASK_DDMACH5_DLEN)
+#define BIT_SET_DDMACH5_DLEN(x, v) \
+ (BIT_CLEAR_DDMACH5_DLEN(x) | BIT_DDMACH5_DLEN(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_REG_DDMA_CH5CTRL (Offset 0x1258) */
+
+#define BIT_DDMACH5_ERR_MON BIT(30)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DDMA_INT_MSK (Offset 0x12E0) */
+
+#define BIT_DDMACH5_MSK BIT(5)
+#define BIT_DDMACH4_MSK BIT(4)
+#define BIT_DDMACH3_MSK BIT(3)
+#define BIT_DDMACH2_MSK BIT(2)
+#define BIT_DDMACH1_MSK BIT(1)
+#define BIT_DDMACH0_MSK BIT(0)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_DDMA_CHSTATUS (Offset 0x12E8) */
+#define BIT_DDMACH5_BUSY BIT(5)
+#define BIT_DDMACH4_BUSY BIT(4)
+#define BIT_DDMACH3_BUSY BIT(3)
+#define BIT_DDMACH2_BUSY BIT(2)
+#define BIT_DDMACH1_BUSY BIT(1)
+#define BIT_DDMACH0_BUSY BIT(0)
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+/* 2 REG_DDMA_CHKSUM (Offset 0x12F0) */
-#define BIT_FS_CLI3_EOSP_INT BIT(28)
+#define BIT_SHIFT_IDDMA0_CHKSUM 0
+#define BIT_MASK_IDDMA0_CHKSUM 0xffff
+#define BIT_IDDMA0_CHKSUM(x) \
+ (((x) & BIT_MASK_IDDMA0_CHKSUM) << BIT_SHIFT_IDDMA0_CHKSUM)
+#define BITS_IDDMA0_CHKSUM (BIT_MASK_IDDMA0_CHKSUM << BIT_SHIFT_IDDMA0_CHKSUM)
+#define BIT_CLEAR_IDDMA0_CHKSUM(x) ((x) & (~BITS_IDDMA0_CHKSUM))
+#define BIT_GET_IDDMA0_CHKSUM(x) \
+ (((x) >> BIT_SHIFT_IDDMA0_CHKSUM) & BIT_MASK_IDDMA0_CHKSUM)
+#define BIT_SET_IDDMA0_CHKSUM(x, v) \
+ (BIT_CLEAR_IDDMA0_CHKSUM(x) | BIT_IDDMA0_CHKSUM(v))
-#endif
+/* 2 REG_DDMA_MONITOR (Offset 0x12FC) */
+#define BIT_IDDMA0_PERMU_UNDERFLOW BIT(14)
+#define BIT_IDDMA0_FIFO_UNDERFLOW BIT(13)
+#define BIT_IDDMA0_FIFO_OVERFLOW BIT(12)
+#define BIT_CH5_ERR BIT(5)
+#define BIT_CH4_ERR BIT(4)
+#define BIT_CH3_ERR BIT(3)
+#define BIT_CH2_ERR BIT(2)
+#define BIT_CH1_ERR BIT(1)
+#define BIT_CH0_ERR BIT(0)
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+/* 2 REG_STC_INT_CS (Offset 0x1300) */
-#define BIT_PORT3_RX_UCMD1_UAPSD0_OK_INT BIT(27)
+#define BIT_STC_INT_EN BIT(31)
+#define BIT_STC_INT_GRP_EN BIT(31)
+
+#define BIT_SHIFT_STC_INT_FLAG 16
+#define BIT_MASK_STC_INT_FLAG 0xff
+#define BIT_STC_INT_FLAG(x) \
+ (((x) & BIT_MASK_STC_INT_FLAG) << BIT_SHIFT_STC_INT_FLAG)
+#define BITS_STC_INT_FLAG (BIT_MASK_STC_INT_FLAG << BIT_SHIFT_STC_INT_FLAG)
+#define BIT_CLEAR_STC_INT_FLAG(x) ((x) & (~BITS_STC_INT_FLAG))
+#define BIT_GET_STC_INT_FLAG(x) \
+ (((x) >> BIT_SHIFT_STC_INT_FLAG) & BIT_MASK_STC_INT_FLAG)
+#define BIT_SET_STC_INT_FLAG(x, v) \
+ (BIT_CLEAR_STC_INT_FLAG(x) | BIT_STC_INT_FLAG(v))
+
+#define BIT_SHIFT_STC_INT_IDX 8
+#define BIT_MASK_STC_INT_IDX 0x7
+#define BIT_STC_INT_IDX(x) \
+ (((x) & BIT_MASK_STC_INT_IDX) << BIT_SHIFT_STC_INT_IDX)
+#define BITS_STC_INT_IDX (BIT_MASK_STC_INT_IDX << BIT_SHIFT_STC_INT_IDX)
+#define BIT_CLEAR_STC_INT_IDX(x) ((x) & (~BITS_STC_INT_IDX))
+#define BIT_GET_STC_INT_IDX(x) \
+ (((x) >> BIT_SHIFT_STC_INT_IDX) & BIT_MASK_STC_INT_IDX)
+#define BIT_SET_STC_INT_IDX(x, v) \
+ (BIT_CLEAR_STC_INT_IDX(x) | BIT_STC_INT_IDX(v))
+
+#define BIT_SHIFT_STC_INT_EXPECT_LS 8
+#define BIT_MASK_STC_INT_EXPECT_LS 0x3f
+#define BIT_STC_INT_EXPECT_LS(x) \
+ (((x) & BIT_MASK_STC_INT_EXPECT_LS) << BIT_SHIFT_STC_INT_EXPECT_LS)
+#define BITS_STC_INT_EXPECT_LS \
+ (BIT_MASK_STC_INT_EXPECT_LS << BIT_SHIFT_STC_INT_EXPECT_LS)
+#define BIT_CLEAR_STC_INT_EXPECT_LS(x) ((x) & (~BITS_STC_INT_EXPECT_LS))
+#define BIT_GET_STC_INT_EXPECT_LS(x) \
+ (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS) & BIT_MASK_STC_INT_EXPECT_LS)
+#define BIT_SET_STC_INT_EXPECT_LS(x, v) \
+ (BIT_CLEAR_STC_INT_EXPECT_LS(x) | BIT_STC_INT_EXPECT_LS(v))
+
+#define BIT_SHIFT_STC_INT_REALTIME_CS 0
+#define BIT_MASK_STC_INT_REALTIME_CS 0x3f
+#define BIT_STC_INT_REALTIME_CS(x) \
+ (((x) & BIT_MASK_STC_INT_REALTIME_CS) << BIT_SHIFT_STC_INT_REALTIME_CS)
+#define BITS_STC_INT_REALTIME_CS \
+ (BIT_MASK_STC_INT_REALTIME_CS << BIT_SHIFT_STC_INT_REALTIME_CS)
+#define BIT_CLEAR_STC_INT_REALTIME_CS(x) ((x) & (~BITS_STC_INT_REALTIME_CS))
+#define BIT_GET_STC_INT_REALTIME_CS(x) \
+ (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS) & BIT_MASK_STC_INT_REALTIME_CS)
+#define BIT_SET_STC_INT_REALTIME_CS(x, v) \
+ (BIT_CLEAR_STC_INT_REALTIME_CS(x) | BIT_STC_INT_REALTIME_CS(v))
+
+#define BIT_SHIFT_STC_INT_EXPECT_CS 0
+#define BIT_MASK_STC_INT_EXPECT_CS 0x3f
+#define BIT_STC_INT_EXPECT_CS(x) \
+ (((x) & BIT_MASK_STC_INT_EXPECT_CS) << BIT_SHIFT_STC_INT_EXPECT_CS)
+#define BITS_STC_INT_EXPECT_CS \
+ (BIT_MASK_STC_INT_EXPECT_CS << BIT_SHIFT_STC_INT_EXPECT_CS)
+#define BIT_CLEAR_STC_INT_EXPECT_CS(x) ((x) & (~BITS_STC_INT_EXPECT_CS))
+#define BIT_GET_STC_INT_EXPECT_CS(x) \
+ (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS) & BIT_MASK_STC_INT_EXPECT_CS)
+#define BIT_SET_STC_INT_EXPECT_CS(x, v) \
+ (BIT_CLEAR_STC_INT_EXPECT_CS(x) | BIT_STC_INT_EXPECT_CS(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH4_ACH5_TXBD_NUM (Offset 0x130C) */
+
+#define BIT_PCIE_ACH5_FLAG BIT(30)
+
+#define BIT_SHIFT_ACH5_DESC_MODE 28
+#define BIT_MASK_ACH5_DESC_MODE 0x3
+#define BIT_ACH5_DESC_MODE(x) \
+ (((x) & BIT_MASK_ACH5_DESC_MODE) << BIT_SHIFT_ACH5_DESC_MODE)
+#define BITS_ACH5_DESC_MODE \
+ (BIT_MASK_ACH5_DESC_MODE << BIT_SHIFT_ACH5_DESC_MODE)
+#define BIT_CLEAR_ACH5_DESC_MODE(x) ((x) & (~BITS_ACH5_DESC_MODE))
+#define BIT_GET_ACH5_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_ACH5_DESC_MODE) & BIT_MASK_ACH5_DESC_MODE)
+#define BIT_SET_ACH5_DESC_MODE(x, v) \
+ (BIT_CLEAR_ACH5_DESC_MODE(x) | BIT_ACH5_DESC_MODE(v))
+
+#define BIT_SHIFT_ACH5_DESC_NUM 16
+#define BIT_MASK_ACH5_DESC_NUM 0xfff
+#define BIT_ACH5_DESC_NUM(x) \
+ (((x) & BIT_MASK_ACH5_DESC_NUM) << BIT_SHIFT_ACH5_DESC_NUM)
+#define BITS_ACH5_DESC_NUM (BIT_MASK_ACH5_DESC_NUM << BIT_SHIFT_ACH5_DESC_NUM)
+#define BIT_CLEAR_ACH5_DESC_NUM(x) ((x) & (~BITS_ACH5_DESC_NUM))
+#define BIT_GET_ACH5_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_ACH5_DESC_NUM) & BIT_MASK_ACH5_DESC_NUM)
+#define BIT_SET_ACH5_DESC_NUM(x, v) \
+ (BIT_CLEAR_ACH5_DESC_NUM(x) | BIT_ACH5_DESC_NUM(v))
+
+#define BIT_PCIE_ACH4_FLAG BIT(14)
+
+#define BIT_SHIFT_ACH4_DESC_MODE 12
+#define BIT_MASK_ACH4_DESC_MODE 0x3
+#define BIT_ACH4_DESC_MODE(x) \
+ (((x) & BIT_MASK_ACH4_DESC_MODE) << BIT_SHIFT_ACH4_DESC_MODE)
+#define BITS_ACH4_DESC_MODE \
+ (BIT_MASK_ACH4_DESC_MODE << BIT_SHIFT_ACH4_DESC_MODE)
+#define BIT_CLEAR_ACH4_DESC_MODE(x) ((x) & (~BITS_ACH4_DESC_MODE))
+#define BIT_GET_ACH4_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_ACH4_DESC_MODE) & BIT_MASK_ACH4_DESC_MODE)
+#define BIT_SET_ACH4_DESC_MODE(x, v) \
+ (BIT_CLEAR_ACH4_DESC_MODE(x) | BIT_ACH4_DESC_MODE(v))
+
+#define BIT_SHIFT_ACH4_DESC_NUM 0
+#define BIT_MASK_ACH4_DESC_NUM 0xfff
+#define BIT_ACH4_DESC_NUM(x) \
+ (((x) & BIT_MASK_ACH4_DESC_NUM) << BIT_SHIFT_ACH4_DESC_NUM)
+#define BITS_ACH4_DESC_NUM (BIT_MASK_ACH4_DESC_NUM << BIT_SHIFT_ACH4_DESC_NUM)
+#define BIT_CLEAR_ACH4_DESC_NUM(x) ((x) & (~BITS_ACH4_DESC_NUM))
+#define BIT_GET_ACH4_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_ACH4_DESC_NUM) & BIT_MASK_ACH4_DESC_NUM)
+#define BIT_SET_ACH4_DESC_NUM(x, v) \
+ (BIT_CLEAR_ACH4_DESC_NUM(x) | BIT_ACH4_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-#endif
+/* 2 REG_CMU_DLY_CTRL (Offset 0x1310) */
+#define BIT_CMU_DLY_EN BIT(31)
+#define BIT_CMU_DLY_MODE BIT(30)
+
+#define BIT_SHIFT_CMU_DLY_PRE_DIV 0
+#define BIT_MASK_CMU_DLY_PRE_DIV 0xff
+#define BIT_CMU_DLY_PRE_DIV(x) \
+ (((x) & BIT_MASK_CMU_DLY_PRE_DIV) << BIT_SHIFT_CMU_DLY_PRE_DIV)
+#define BITS_CMU_DLY_PRE_DIV \
+ (BIT_MASK_CMU_DLY_PRE_DIV << BIT_SHIFT_CMU_DLY_PRE_DIV)
+#define BIT_CLEAR_CMU_DLY_PRE_DIV(x) ((x) & (~BITS_CMU_DLY_PRE_DIV))
+#define BIT_GET_CMU_DLY_PRE_DIV(x) \
+ (((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV) & BIT_MASK_CMU_DLY_PRE_DIV)
+#define BIT_SET_CMU_DLY_PRE_DIV(x, v) \
+ (BIT_CLEAR_CMU_DLY_PRE_DIV(x) | BIT_CMU_DLY_PRE_DIV(v))
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_CMU_DLY_CFG (Offset 0x1314) */
+#define BIT_SHIFT_CMU_DLY_LTR_A2I 24
+#define BIT_MASK_CMU_DLY_LTR_A2I 0xff
+#define BIT_CMU_DLY_LTR_A2I(x) \
+ (((x) & BIT_MASK_CMU_DLY_LTR_A2I) << BIT_SHIFT_CMU_DLY_LTR_A2I)
+#define BITS_CMU_DLY_LTR_A2I \
+ (BIT_MASK_CMU_DLY_LTR_A2I << BIT_SHIFT_CMU_DLY_LTR_A2I)
+#define BIT_CLEAR_CMU_DLY_LTR_A2I(x) ((x) & (~BITS_CMU_DLY_LTR_A2I))
+#define BIT_GET_CMU_DLY_LTR_A2I(x) \
+ (((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I) & BIT_MASK_CMU_DLY_LTR_A2I)
+#define BIT_SET_CMU_DLY_LTR_A2I(x, v) \
+ (BIT_CLEAR_CMU_DLY_LTR_A2I(x) | BIT_CMU_DLY_LTR_A2I(v))
+
+#define BIT_SHIFT_CMU_DLY_LTR_I2A 16
+#define BIT_MASK_CMU_DLY_LTR_I2A 0xff
+#define BIT_CMU_DLY_LTR_I2A(x) \
+ (((x) & BIT_MASK_CMU_DLY_LTR_I2A) << BIT_SHIFT_CMU_DLY_LTR_I2A)
+#define BITS_CMU_DLY_LTR_I2A \
+ (BIT_MASK_CMU_DLY_LTR_I2A << BIT_SHIFT_CMU_DLY_LTR_I2A)
+#define BIT_CLEAR_CMU_DLY_LTR_I2A(x) ((x) & (~BITS_CMU_DLY_LTR_I2A))
+#define BIT_GET_CMU_DLY_LTR_I2A(x) \
+ (((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A) & BIT_MASK_CMU_DLY_LTR_I2A)
+#define BIT_SET_CMU_DLY_LTR_I2A(x, v) \
+ (BIT_CLEAR_CMU_DLY_LTR_I2A(x) | BIT_CMU_DLY_LTR_I2A(v))
+
+#define BIT_SHIFT_CMU_DLY_LTR_IDLE 8
+#define BIT_MASK_CMU_DLY_LTR_IDLE 0xff
+#define BIT_CMU_DLY_LTR_IDLE(x) \
+ (((x) & BIT_MASK_CMU_DLY_LTR_IDLE) << BIT_SHIFT_CMU_DLY_LTR_IDLE)
+#define BITS_CMU_DLY_LTR_IDLE \
+ (BIT_MASK_CMU_DLY_LTR_IDLE << BIT_SHIFT_CMU_DLY_LTR_IDLE)
+#define BIT_CLEAR_CMU_DLY_LTR_IDLE(x) ((x) & (~BITS_CMU_DLY_LTR_IDLE))
+#define BIT_GET_CMU_DLY_LTR_IDLE(x) \
+ (((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE) & BIT_MASK_CMU_DLY_LTR_IDLE)
+#define BIT_SET_CMU_DLY_LTR_IDLE(x, v) \
+ (BIT_CLEAR_CMU_DLY_LTR_IDLE(x) | BIT_CMU_DLY_LTR_IDLE(v))
+
+#define BIT_SHIFT_CMU_DLY_LTR_ACT 0
+#define BIT_MASK_CMU_DLY_LTR_ACT 0xff
+#define BIT_CMU_DLY_LTR_ACT(x) \
+ (((x) & BIT_MASK_CMU_DLY_LTR_ACT) << BIT_SHIFT_CMU_DLY_LTR_ACT)
+#define BITS_CMU_DLY_LTR_ACT \
+ (BIT_MASK_CMU_DLY_LTR_ACT << BIT_SHIFT_CMU_DLY_LTR_ACT)
+#define BIT_CLEAR_CMU_DLY_LTR_ACT(x) ((x) & (~BITS_CMU_DLY_LTR_ACT))
+#define BIT_GET_CMU_DLY_LTR_ACT(x) \
+ (((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT) & BIT_MASK_CMU_DLY_LTR_ACT)
+#define BIT_SET_CMU_DLY_LTR_ACT(x, v) \
+ (BIT_CLEAR_CMU_DLY_LTR_ACT(x) | BIT_CMU_DLY_LTR_ACT(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_FWCMDQ_TXBD_IDX (Offset 0x1318) */
+
+#define BIT_SHIFT_FWCMDQ_HW_IDX 16
+#define BIT_MASK_FWCMDQ_HW_IDX 0xfff
+#define BIT_FWCMDQ_HW_IDX(x) \
+ (((x) & BIT_MASK_FWCMDQ_HW_IDX) << BIT_SHIFT_FWCMDQ_HW_IDX)
+#define BITS_FWCMDQ_HW_IDX (BIT_MASK_FWCMDQ_HW_IDX << BIT_SHIFT_FWCMDQ_HW_IDX)
+#define BIT_CLEAR_FWCMDQ_HW_IDX(x) ((x) & (~BITS_FWCMDQ_HW_IDX))
+#define BIT_GET_FWCMDQ_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_FWCMDQ_HW_IDX) & BIT_MASK_FWCMDQ_HW_IDX)
+#define BIT_SET_FWCMDQ_HW_IDX(x, v) \
+ (BIT_CLEAR_FWCMDQ_HW_IDX(x) | BIT_FWCMDQ_HW_IDX(v))
+
+#define BIT_SHIFT_FWCMDQ_HOST_IDX 0
+#define BIT_MASK_FWCMDQ_HOST_IDX 0xfff
+#define BIT_FWCMDQ_HOST_IDX(x) \
+ (((x) & BIT_MASK_FWCMDQ_HOST_IDX) << BIT_SHIFT_FWCMDQ_HOST_IDX)
+#define BITS_FWCMDQ_HOST_IDX \
+ (BIT_MASK_FWCMDQ_HOST_IDX << BIT_SHIFT_FWCMDQ_HOST_IDX)
+#define BIT_CLEAR_FWCMDQ_HOST_IDX(x) ((x) & (~BITS_FWCMDQ_HOST_IDX))
+#define BIT_GET_FWCMDQ_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_FWCMDQ_HOST_IDX) & BIT_MASK_FWCMDQ_HOST_IDX)
+#define BIT_SET_FWCMDQ_HOST_IDX(x, v) \
+ (BIT_CLEAR_FWCMDQ_HOST_IDX(x) | BIT_FWCMDQ_HOST_IDX(v))
+
+/* 2 REG_P0HI8Q_TXBD_IDX (Offset 0x131C) */
+
+#define BIT_SHIFT_P0HI8Q_HW_IDX 16
+#define BIT_MASK_P0HI8Q_HW_IDX 0xfff
+#define BIT_P0HI8Q_HW_IDX(x) \
+ (((x) & BIT_MASK_P0HI8Q_HW_IDX) << BIT_SHIFT_P0HI8Q_HW_IDX)
+#define BITS_P0HI8Q_HW_IDX (BIT_MASK_P0HI8Q_HW_IDX << BIT_SHIFT_P0HI8Q_HW_IDX)
+#define BIT_CLEAR_P0HI8Q_HW_IDX(x) ((x) & (~BITS_P0HI8Q_HW_IDX))
+#define BIT_GET_P0HI8Q_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI8Q_HW_IDX) & BIT_MASK_P0HI8Q_HW_IDX)
+#define BIT_SET_P0HI8Q_HW_IDX(x, v) \
+ (BIT_CLEAR_P0HI8Q_HW_IDX(x) | BIT_P0HI8Q_HW_IDX(v))
+
+#define BIT_SHIFT_P0HI8Q_HOST_IDX 0
+#define BIT_MASK_P0HI8Q_HOST_IDX 0xfff
+#define BIT_P0HI8Q_HOST_IDX(x) \
+ (((x) & BIT_MASK_P0HI8Q_HOST_IDX) << BIT_SHIFT_P0HI8Q_HOST_IDX)
+#define BITS_P0HI8Q_HOST_IDX \
+ (BIT_MASK_P0HI8Q_HOST_IDX << BIT_SHIFT_P0HI8Q_HOST_IDX)
+#define BIT_CLEAR_P0HI8Q_HOST_IDX(x) ((x) & (~BITS_P0HI8Q_HOST_IDX))
+#define BIT_GET_P0HI8Q_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI8Q_HOST_IDX) & BIT_MASK_P0HI8Q_HOST_IDX)
+#define BIT_SET_P0HI8Q_HOST_IDX(x, v) \
+ (BIT_CLEAR_P0HI8Q_HOST_IDX(x) | BIT_P0HI8Q_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+/* 2 REG_H2CQ_TXBD_DESA (Offset 0x1320) */
-#define BIT_FS_CLI2_RX_UAPSDMD1_INT BIT(27)
+#define BIT_SHIFT_H2CQ_TXBD_DESA 0
+#define BIT_MASK_H2CQ_TXBD_DESA 0xffffffffffffffffL
+#define BIT_H2CQ_TXBD_DESA(x) \
+ (((x) & BIT_MASK_H2CQ_TXBD_DESA) << BIT_SHIFT_H2CQ_TXBD_DESA)
+#define BITS_H2CQ_TXBD_DESA \
+ (BIT_MASK_H2CQ_TXBD_DESA << BIT_SHIFT_H2CQ_TXBD_DESA)
+#define BIT_CLEAR_H2CQ_TXBD_DESA(x) ((x) & (~BITS_H2CQ_TXBD_DESA))
+#define BIT_GET_H2CQ_TXBD_DESA(x) \
+ (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA) & BIT_MASK_H2CQ_TXBD_DESA)
+#define BIT_SET_H2CQ_TXBD_DESA(x, v) \
+ (BIT_CLEAR_H2CQ_TXBD_DESA(x) | BIT_H2CQ_TXBD_DESA(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_H2CQ_TXBD_DESA_L (Offset 0x1320) */
+#define BIT_SHIFT_H2CQ_TXBD_DESA_L 0
+#define BIT_MASK_H2CQ_TXBD_DESA_L 0xffffffffL
+#define BIT_H2CQ_TXBD_DESA_L(x) \
+ (((x) & BIT_MASK_H2CQ_TXBD_DESA_L) << BIT_SHIFT_H2CQ_TXBD_DESA_L)
+#define BITS_H2CQ_TXBD_DESA_L \
+ (BIT_MASK_H2CQ_TXBD_DESA_L << BIT_SHIFT_H2CQ_TXBD_DESA_L)
+#define BIT_CLEAR_H2CQ_TXBD_DESA_L(x) ((x) & (~BITS_H2CQ_TXBD_DESA_L))
+#define BIT_GET_H2CQ_TXBD_DESA_L(x) \
+ (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_L) & BIT_MASK_H2CQ_TXBD_DESA_L)
+#define BIT_SET_H2CQ_TXBD_DESA_L(x, v) \
+ (BIT_CLEAR_H2CQ_TXBD_DESA_L(x) | BIT_H2CQ_TXBD_DESA_L(v))
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+/* 2 REG_H2CQ_TXBD_DESA_H (Offset 0x1324) */
-#define BIT_PORT3_RX_UCMD0_UAPSD0_OK_INT BIT(26)
+#define BIT_SHIFT_H2CQ_TXBD_DESA_H 0
+#define BIT_MASK_H2CQ_TXBD_DESA_H 0xffffffffL
+#define BIT_H2CQ_TXBD_DESA_H(x) \
+ (((x) & BIT_MASK_H2CQ_TXBD_DESA_H) << BIT_SHIFT_H2CQ_TXBD_DESA_H)
+#define BITS_H2CQ_TXBD_DESA_H \
+ (BIT_MASK_H2CQ_TXBD_DESA_H << BIT_SHIFT_H2CQ_TXBD_DESA_H)
+#define BIT_CLEAR_H2CQ_TXBD_DESA_H(x) ((x) & (~BITS_H2CQ_TXBD_DESA_H))
+#define BIT_GET_H2CQ_TXBD_DESA_H(x) \
+ (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_H) & BIT_MASK_H2CQ_TXBD_DESA_H)
+#define BIT_SET_H2CQ_TXBD_DESA_H(x, v) \
+ (BIT_CLEAR_H2CQ_TXBD_DESA_H(x) | BIT_H2CQ_TXBD_DESA_H(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+/* 2 REG_H2CQ_TXBD_NUM (Offset 0x1328) */
-#define BIT_FS_CLI2_RX_UAPSDMD0_INT BIT(26)
+#define BIT_HCI_H2CQ_FLAG BIT(14)
#endif
+#if (HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_H2CQ_TXBD_NUM (Offset 0x1328) */
+#define BIT_PCIE_H2CQ_FLAG BIT(14)
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+#endif
-#define BIT_PORT3_TRIPKT_OK_INT BIT(25)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_H2CQ_TXBD_NUM (Offset 0x1328) */
+#define BIT_SHIFT_H2CQ_DESC_MODE 12
+#define BIT_MASK_H2CQ_DESC_MODE 0x3
+#define BIT_H2CQ_DESC_MODE(x) \
+ (((x) & BIT_MASK_H2CQ_DESC_MODE) << BIT_SHIFT_H2CQ_DESC_MODE)
+#define BITS_H2CQ_DESC_MODE \
+ (BIT_MASK_H2CQ_DESC_MODE << BIT_SHIFT_H2CQ_DESC_MODE)
+#define BIT_CLEAR_H2CQ_DESC_MODE(x) ((x) & (~BITS_H2CQ_DESC_MODE))
+#define BIT_GET_H2CQ_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_H2CQ_DESC_MODE) & BIT_MASK_H2CQ_DESC_MODE)
+#define BIT_SET_H2CQ_DESC_MODE(x, v) \
+ (BIT_CLEAR_H2CQ_DESC_MODE(x) | BIT_H2CQ_DESC_MODE(v))
+
+#define BIT_SHIFT_H2CQ_DESC_NUM 0
+#define BIT_MASK_H2CQ_DESC_NUM 0xfff
+#define BIT_H2CQ_DESC_NUM(x) \
+ (((x) & BIT_MASK_H2CQ_DESC_NUM) << BIT_SHIFT_H2CQ_DESC_NUM)
+#define BITS_H2CQ_DESC_NUM (BIT_MASK_H2CQ_DESC_NUM << BIT_SHIFT_H2CQ_DESC_NUM)
+#define BIT_CLEAR_H2CQ_DESC_NUM(x) ((x) & (~BITS_H2CQ_DESC_NUM))
+#define BIT_GET_H2CQ_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_H2CQ_DESC_NUM) & BIT_MASK_H2CQ_DESC_NUM)
+#define BIT_SET_H2CQ_DESC_NUM(x, v) \
+ (BIT_CLEAR_H2CQ_DESC_NUM(x) | BIT_H2CQ_DESC_NUM(v))
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_H2CQ_TXBD_IDX (Offset 0x132C) */
+#define BIT_SHIFT_H2CQ_HW_IDX 16
+#define BIT_MASK_H2CQ_HW_IDX 0xfff
+#define BIT_H2CQ_HW_IDX(x) \
+ (((x) & BIT_MASK_H2CQ_HW_IDX) << BIT_SHIFT_H2CQ_HW_IDX)
+#define BITS_H2CQ_HW_IDX (BIT_MASK_H2CQ_HW_IDX << BIT_SHIFT_H2CQ_HW_IDX)
+#define BIT_CLEAR_H2CQ_HW_IDX(x) ((x) & (~BITS_H2CQ_HW_IDX))
+#define BIT_GET_H2CQ_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_H2CQ_HW_IDX) & BIT_MASK_H2CQ_HW_IDX)
+#define BIT_SET_H2CQ_HW_IDX(x, v) \
+ (BIT_CLEAR_H2CQ_HW_IDX(x) | BIT_H2CQ_HW_IDX(v))
+
+#define BIT_SHIFT_H2CQ_HOST_IDX 0
+#define BIT_MASK_H2CQ_HOST_IDX 0xfff
+#define BIT_H2CQ_HOST_IDX(x) \
+ (((x) & BIT_MASK_H2CQ_HOST_IDX) << BIT_SHIFT_H2CQ_HOST_IDX)
+#define BITS_H2CQ_HOST_IDX (BIT_MASK_H2CQ_HOST_IDX << BIT_SHIFT_H2CQ_HOST_IDX)
+#define BIT_CLEAR_H2CQ_HOST_IDX(x) ((x) & (~BITS_H2CQ_HOST_IDX))
+#define BIT_GET_H2CQ_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_H2CQ_HOST_IDX) & BIT_MASK_H2CQ_HOST_IDX)
+#define BIT_SET_H2CQ_HOST_IDX(x, v) \
+ (BIT_CLEAR_H2CQ_HOST_IDX(x) | BIT_H2CQ_HOST_IDX(v))
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+/* 2 REG_H2CQ_CSR (Offset 0x1330) */
-#define BIT_FS_CLI2_TRIGGER_PKT_INT BIT(25)
+#define BIT_H2CQ_FULL BIT(31)
+#define BIT_CLR_H2CQ_HOST_IDX BIT(16)
+#define BIT_CLR_H2CQ_HW_IDX BIT(8)
+#define BIT_STOP_H2CQ BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI9Q_TXBD_IDX (Offset 0x1334) */
+
+#define BIT_SHIFT_P0HI9Q_HW_IDX 16
+#define BIT_MASK_P0HI9Q_HW_IDX 0xfff
+#define BIT_P0HI9Q_HW_IDX(x) \
+ (((x) & BIT_MASK_P0HI9Q_HW_IDX) << BIT_SHIFT_P0HI9Q_HW_IDX)
+#define BITS_P0HI9Q_HW_IDX (BIT_MASK_P0HI9Q_HW_IDX << BIT_SHIFT_P0HI9Q_HW_IDX)
+#define BIT_CLEAR_P0HI9Q_HW_IDX(x) ((x) & (~BITS_P0HI9Q_HW_IDX))
+#define BIT_GET_P0HI9Q_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI9Q_HW_IDX) & BIT_MASK_P0HI9Q_HW_IDX)
+#define BIT_SET_P0HI9Q_HW_IDX(x, v) \
+ (BIT_CLEAR_P0HI9Q_HW_IDX(x) | BIT_P0HI9Q_HW_IDX(v))
+
+#define BIT_SHIFT_P0HI9Q_HOST_IDX 0
+#define BIT_MASK_P0HI9Q_HOST_IDX 0xfff
+#define BIT_P0HI9Q_HOST_IDX(x) \
+ (((x) & BIT_MASK_P0HI9Q_HOST_IDX) << BIT_SHIFT_P0HI9Q_HOST_IDX)
+#define BITS_P0HI9Q_HOST_IDX \
+ (BIT_MASK_P0HI9Q_HOST_IDX << BIT_SHIFT_P0HI9Q_HOST_IDX)
+#define BIT_CLEAR_P0HI9Q_HOST_IDX(x) ((x) & (~BITS_P0HI9Q_HOST_IDX))
+#define BIT_GET_P0HI9Q_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI9Q_HOST_IDX) & BIT_MASK_P0HI9Q_HOST_IDX)
+#define BIT_SET_P0HI9Q_HOST_IDX(x, v) \
+ (BIT_CLEAR_P0HI9Q_HOST_IDX(x) | BIT_P0HI9Q_HOST_IDX(v))
+
+/* 2 REG_P0HI10Q_TXBD_IDX (Offset 0x1338) */
+
+#define BIT_SHIFT_P0HI10Q_HW_IDX 16
+#define BIT_MASK_P0HI10Q_HW_IDX 0xfff
+#define BIT_P0HI10Q_HW_IDX(x) \
+ (((x) & BIT_MASK_P0HI10Q_HW_IDX) << BIT_SHIFT_P0HI10Q_HW_IDX)
+#define BITS_P0HI10Q_HW_IDX \
+ (BIT_MASK_P0HI10Q_HW_IDX << BIT_SHIFT_P0HI10Q_HW_IDX)
+#define BIT_CLEAR_P0HI10Q_HW_IDX(x) ((x) & (~BITS_P0HI10Q_HW_IDX))
+#define BIT_GET_P0HI10Q_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI10Q_HW_IDX) & BIT_MASK_P0HI10Q_HW_IDX)
+#define BIT_SET_P0HI10Q_HW_IDX(x, v) \
+ (BIT_CLEAR_P0HI10Q_HW_IDX(x) | BIT_P0HI10Q_HW_IDX(v))
+
+#define BIT_SHIFT_P0HI10Q_HOST_IDX 0
+#define BIT_MASK_P0HI10Q_HOST_IDX 0xfff
+#define BIT_P0HI10Q_HOST_IDX(x) \
+ (((x) & BIT_MASK_P0HI10Q_HOST_IDX) << BIT_SHIFT_P0HI10Q_HOST_IDX)
+#define BITS_P0HI10Q_HOST_IDX \
+ (BIT_MASK_P0HI10Q_HOST_IDX << BIT_SHIFT_P0HI10Q_HOST_IDX)
+#define BIT_CLEAR_P0HI10Q_HOST_IDX(x) ((x) & (~BITS_P0HI10Q_HOST_IDX))
+#define BIT_GET_P0HI10Q_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI10Q_HOST_IDX) & BIT_MASK_P0HI10Q_HOST_IDX)
+#define BIT_SET_P0HI10Q_HOST_IDX(x, v) \
+ (BIT_CLEAR_P0HI10Q_HOST_IDX(x) | BIT_P0HI10Q_HOST_IDX(v))
+
+/* 2 REG_P0HI11Q_TXBD_IDX (Offset 0x133C) */
+
+#define BIT_SHIFT_P0HI11Q_HW_IDX 16
+#define BIT_MASK_P0HI11Q_HW_IDX 0xfff
+#define BIT_P0HI11Q_HW_IDX(x) \
+ (((x) & BIT_MASK_P0HI11Q_HW_IDX) << BIT_SHIFT_P0HI11Q_HW_IDX)
+#define BITS_P0HI11Q_HW_IDX \
+ (BIT_MASK_P0HI11Q_HW_IDX << BIT_SHIFT_P0HI11Q_HW_IDX)
+#define BIT_CLEAR_P0HI11Q_HW_IDX(x) ((x) & (~BITS_P0HI11Q_HW_IDX))
+#define BIT_GET_P0HI11Q_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI11Q_HW_IDX) & BIT_MASK_P0HI11Q_HW_IDX)
+#define BIT_SET_P0HI11Q_HW_IDX(x, v) \
+ (BIT_CLEAR_P0HI11Q_HW_IDX(x) | BIT_P0HI11Q_HW_IDX(v))
+
+#define BIT_SHIFT_P0HI11Q_HOST_IDX 0
+#define BIT_MASK_P0HI11Q_HOST_IDX 0xfff
+#define BIT_P0HI11Q_HOST_IDX(x) \
+ (((x) & BIT_MASK_P0HI11Q_HOST_IDX) << BIT_SHIFT_P0HI11Q_HOST_IDX)
+#define BITS_P0HI11Q_HOST_IDX \
+ (BIT_MASK_P0HI11Q_HOST_IDX << BIT_SHIFT_P0HI11Q_HOST_IDX)
+#define BIT_CLEAR_P0HI11Q_HOST_IDX(x) ((x) & (~BITS_P0HI11Q_HOST_IDX))
+#define BIT_GET_P0HI11Q_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI11Q_HOST_IDX) & BIT_MASK_P0HI11Q_HOST_IDX)
+#define BIT_SET_P0HI11Q_HOST_IDX(x, v) \
+ (BIT_CLEAR_P0HI11Q_HOST_IDX(x) | BIT_P0HI11Q_HOST_IDX(v))
+
+/* 2 REG_P0HI12Q_TXBD_IDX (Offset 0x1340) */
+
+#define BIT_SHIFT_P0HI12Q_HW_IDX 16
+#define BIT_MASK_P0HI12Q_HW_IDX 0xfff
+#define BIT_P0HI12Q_HW_IDX(x) \
+ (((x) & BIT_MASK_P0HI12Q_HW_IDX) << BIT_SHIFT_P0HI12Q_HW_IDX)
+#define BITS_P0HI12Q_HW_IDX \
+ (BIT_MASK_P0HI12Q_HW_IDX << BIT_SHIFT_P0HI12Q_HW_IDX)
+#define BIT_CLEAR_P0HI12Q_HW_IDX(x) ((x) & (~BITS_P0HI12Q_HW_IDX))
+#define BIT_GET_P0HI12Q_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI12Q_HW_IDX) & BIT_MASK_P0HI12Q_HW_IDX)
+#define BIT_SET_P0HI12Q_HW_IDX(x, v) \
+ (BIT_CLEAR_P0HI12Q_HW_IDX(x) | BIT_P0HI12Q_HW_IDX(v))
+
+#define BIT_SHIFT_P0HI12Q_HOST_IDX 0
+#define BIT_MASK_P0HI12Q_HOST_IDX 0xfff
+#define BIT_P0HI12Q_HOST_IDX(x) \
+ (((x) & BIT_MASK_P0HI12Q_HOST_IDX) << BIT_SHIFT_P0HI12Q_HOST_IDX)
+#define BITS_P0HI12Q_HOST_IDX \
+ (BIT_MASK_P0HI12Q_HOST_IDX << BIT_SHIFT_P0HI12Q_HOST_IDX)
+#define BIT_CLEAR_P0HI12Q_HOST_IDX(x) ((x) & (~BITS_P0HI12Q_HOST_IDX))
+#define BIT_GET_P0HI12Q_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI12Q_HOST_IDX) & BIT_MASK_P0HI12Q_HOST_IDX)
+#define BIT_SET_P0HI12Q_HOST_IDX(x, v) \
+ (BIT_CLEAR_P0HI12Q_HOST_IDX(x) | BIT_P0HI12Q_HOST_IDX(v))
+
+/* 2 REG_P0HI13Q_TXBD_IDX (Offset 0x1344) */
+
+#define BIT_SHIFT_P0HI13Q_HW_IDX 16
+#define BIT_MASK_P0HI13Q_HW_IDX 0xfff
+#define BIT_P0HI13Q_HW_IDX(x) \
+ (((x) & BIT_MASK_P0HI13Q_HW_IDX) << BIT_SHIFT_P0HI13Q_HW_IDX)
+#define BITS_P0HI13Q_HW_IDX \
+ (BIT_MASK_P0HI13Q_HW_IDX << BIT_SHIFT_P0HI13Q_HW_IDX)
+#define BIT_CLEAR_P0HI13Q_HW_IDX(x) ((x) & (~BITS_P0HI13Q_HW_IDX))
+#define BIT_GET_P0HI13Q_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI13Q_HW_IDX) & BIT_MASK_P0HI13Q_HW_IDX)
+#define BIT_SET_P0HI13Q_HW_IDX(x, v) \
+ (BIT_CLEAR_P0HI13Q_HW_IDX(x) | BIT_P0HI13Q_HW_IDX(v))
+
+#define BIT_SHIFT_P0HI13Q_HOST_IDX 0
+#define BIT_MASK_P0HI13Q_HOST_IDX 0xfff
+#define BIT_P0HI13Q_HOST_IDX(x) \
+ (((x) & BIT_MASK_P0HI13Q_HOST_IDX) << BIT_SHIFT_P0HI13Q_HOST_IDX)
+#define BITS_P0HI13Q_HOST_IDX \
+ (BIT_MASK_P0HI13Q_HOST_IDX << BIT_SHIFT_P0HI13Q_HOST_IDX)
+#define BIT_CLEAR_P0HI13Q_HOST_IDX(x) ((x) & (~BITS_P0HI13Q_HOST_IDX))
+#define BIT_GET_P0HI13Q_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI13Q_HOST_IDX) & BIT_MASK_P0HI13Q_HOST_IDX)
+#define BIT_SET_P0HI13Q_HOST_IDX(x, v) \
+ (BIT_CLEAR_P0HI13Q_HOST_IDX(x) | BIT_P0HI13Q_HOST_IDX(v))
+
+/* 2 REG_P0HI14Q_TXBD_IDX (Offset 0x1348) */
+
+#define BIT_SHIFT_P0HI14Q_HW_IDX 16
+#define BIT_MASK_P0HI14Q_HW_IDX 0xfff
+#define BIT_P0HI14Q_HW_IDX(x) \
+ (((x) & BIT_MASK_P0HI14Q_HW_IDX) << BIT_SHIFT_P0HI14Q_HW_IDX)
+#define BITS_P0HI14Q_HW_IDX \
+ (BIT_MASK_P0HI14Q_HW_IDX << BIT_SHIFT_P0HI14Q_HW_IDX)
+#define BIT_CLEAR_P0HI14Q_HW_IDX(x) ((x) & (~BITS_P0HI14Q_HW_IDX))
+#define BIT_GET_P0HI14Q_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI14Q_HW_IDX) & BIT_MASK_P0HI14Q_HW_IDX)
+#define BIT_SET_P0HI14Q_HW_IDX(x, v) \
+ (BIT_CLEAR_P0HI14Q_HW_IDX(x) | BIT_P0HI14Q_HW_IDX(v))
+
+#define BIT_SHIFT_P0HI14Q_HOST_IDX 0
+#define BIT_MASK_P0HI14Q_HOST_IDX 0xfff
+#define BIT_P0HI14Q_HOST_IDX(x) \
+ (((x) & BIT_MASK_P0HI14Q_HOST_IDX) << BIT_SHIFT_P0HI14Q_HOST_IDX)
+#define BITS_P0HI14Q_HOST_IDX \
+ (BIT_MASK_P0HI14Q_HOST_IDX << BIT_SHIFT_P0HI14Q_HOST_IDX)
+#define BIT_CLEAR_P0HI14Q_HOST_IDX(x) ((x) & (~BITS_P0HI14Q_HOST_IDX))
+#define BIT_GET_P0HI14Q_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI14Q_HOST_IDX) & BIT_MASK_P0HI14Q_HOST_IDX)
+#define BIT_SET_P0HI14Q_HOST_IDX(x, v) \
+ (BIT_CLEAR_P0HI14Q_HOST_IDX(x) | BIT_P0HI14Q_HOST_IDX(v))
+
+/* 2 REG_P0HI15Q_TXBD_IDX (Offset 0x134C) */
+
+#define BIT_SHIFT_P0HI15Q_HW_IDX 16
+#define BIT_MASK_P0HI15Q_HW_IDX 0xfff
+#define BIT_P0HI15Q_HW_IDX(x) \
+ (((x) & BIT_MASK_P0HI15Q_HW_IDX) << BIT_SHIFT_P0HI15Q_HW_IDX)
+#define BITS_P0HI15Q_HW_IDX \
+ (BIT_MASK_P0HI15Q_HW_IDX << BIT_SHIFT_P0HI15Q_HW_IDX)
+#define BIT_CLEAR_P0HI15Q_HW_IDX(x) ((x) & (~BITS_P0HI15Q_HW_IDX))
+#define BIT_GET_P0HI15Q_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI15Q_HW_IDX) & BIT_MASK_P0HI15Q_HW_IDX)
+#define BIT_SET_P0HI15Q_HW_IDX(x, v) \
+ (BIT_CLEAR_P0HI15Q_HW_IDX(x) | BIT_P0HI15Q_HW_IDX(v))
+
+#define BIT_SHIFT_P0HI15Q_HOST_IDX 0
+#define BIT_MASK_P0HI15Q_HOST_IDX 0xfff
+#define BIT_P0HI15Q_HOST_IDX(x) \
+ (((x) & BIT_MASK_P0HI15Q_HOST_IDX) << BIT_SHIFT_P0HI15Q_HOST_IDX)
+#define BITS_P0HI15Q_HOST_IDX \
+ (BIT_MASK_P0HI15Q_HOST_IDX << BIT_SHIFT_P0HI15Q_HOST_IDX)
+#define BIT_CLEAR_P0HI15Q_HOST_IDX(x) ((x) & (~BITS_P0HI15Q_HOST_IDX))
+#define BIT_GET_P0HI15Q_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI15Q_HOST_IDX) & BIT_MASK_P0HI15Q_HOST_IDX)
+#define BIT_SET_P0HI15Q_HOST_IDX(x, v) \
+ (BIT_CLEAR_P0HI15Q_HOST_IDX(x) | BIT_P0HI15Q_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#endif
+/* 2 REG_AXI_EXCEPT_CS (Offset 0x1350) */
+#define BIT_AXI_RXDMA_TIMEOUT_RE BIT(21)
+#define BIT_AXI_TXDMA_TIMEOUT_RE BIT(20)
+#define BIT_AXI_DECERR_W_RE BIT(19)
+#define BIT_AXI_DECERR_R_RE BIT(18)
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8822B_SUPPORT)
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+/* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */
-#define BIT_PORT3_RX_EOSP_OK_INT BIT(24)
+#define BIT_CHANGE_PCIE_SPEED BIT(18)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_AXI_EXCEPT_CS (Offset 0x1350) */
+#define BIT_AXI_SLVERR_W_RE BIT(17)
+#define BIT_AXI_SLVERR_R_RE BIT(16)
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+#endif
-#define BIT_FS_CLI2_EOSP_INT BIT(24)
+#if (HALMAC_8822B_SUPPORT)
-#endif
+/* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */
+#define BIT_SHIFT_GEN1_GEN2 16
+#define BIT_MASK_GEN1_GEN2 0x3
+#define BIT_GEN1_GEN2(x) (((x) & BIT_MASK_GEN1_GEN2) << BIT_SHIFT_GEN1_GEN2)
+#define BITS_GEN1_GEN2 (BIT_MASK_GEN1_GEN2 << BIT_SHIFT_GEN1_GEN2)
+#define BIT_CLEAR_GEN1_GEN2(x) ((x) & (~BITS_GEN1_GEN2))
+#define BIT_GET_GEN1_GEN2(x) (((x) >> BIT_SHIFT_GEN1_GEN2) & BIT_MASK_GEN1_GEN2)
+#define BIT_SET_GEN1_GEN2(x, v) (BIT_CLEAR_GEN1_GEN2(x) | BIT_GEN1_GEN2(v))
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+/* 2 REG_AXI_EXCEPT_CS (Offset 0x1350) */
-#define BIT_PORT2_RX_UCMD1_UAPSD0_OK_INT BIT(23)
+#define BIT_AXI_RXDMA_TIMEOUT_IE BIT(13)
+#define BIT_AXI_TXDMA_TIMEOUT_IE BIT(12)
+#define BIT_AXI_DECERR_W_IE BIT(11)
+#define BIT_AXI_DECERR_R_IE BIT(10)
+#define BIT_AXI_SLVERR_W_IE BIT(9)
+#define BIT_AXI_SLVERR_R_IE BIT(8)
#endif
+#if (HALMAC_8822B_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+/* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+#define BIT_SHIFT_RXDMA_ERROR_COUNTER 8
+#define BIT_MASK_RXDMA_ERROR_COUNTER 0xff
+#define BIT_RXDMA_ERROR_COUNTER(x) \
+ (((x) & BIT_MASK_RXDMA_ERROR_COUNTER) << BIT_SHIFT_RXDMA_ERROR_COUNTER)
+#define BITS_RXDMA_ERROR_COUNTER \
+ (BIT_MASK_RXDMA_ERROR_COUNTER << BIT_SHIFT_RXDMA_ERROR_COUNTER)
+#define BIT_CLEAR_RXDMA_ERROR_COUNTER(x) ((x) & (~BITS_RXDMA_ERROR_COUNTER))
+#define BIT_GET_RXDMA_ERROR_COUNTER(x) \
+ (((x) >> BIT_SHIFT_RXDMA_ERROR_COUNTER) & BIT_MASK_RXDMA_ERROR_COUNTER)
+#define BIT_SET_RXDMA_ERROR_COUNTER(x, v) \
+ (BIT_CLEAR_RXDMA_ERROR_COUNTER(x) | BIT_RXDMA_ERROR_COUNTER(v))
-#define BIT_FS_CLI1_RX_UAPSDMD1_INT BIT(23)
+#define BIT_TXDMA_ERROR_HANDLE_STATUS BIT(7)
+#define BIT_TXDMA_ERROR_PULSE BIT(6)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_AXI_EXCEPT_CS (Offset 0x1350) */
+#define BIT_AXI_RXDMA_TIMEOUT_FLAG BIT(5)
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+#endif
-#define BIT_PORT2_RX_UCMD0_UAPSD0_OK_INT BIT(22)
+#if (HALMAC_8822B_SUPPORT)
-#endif
+/* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */
+#define BIT_TXDMA_STUCK_ERROR_HANDLE_ENABLE BIT(5)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+/* 2 REG_AXI_EXCEPT_CS (Offset 0x1350) */
-#define BIT_FS_CLI1_RX_UAPSDMD0_INT BIT(22)
+#define BIT_AXI_TXDMA_TIMEOUT_FLAG BIT(4)
#endif
+#if (HALMAC_8822B_SUPPORT)
+
+/* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */
-#if (HALMAC_8197F_SUPPORT)
+#define BIT_TXDMA_RETURN_ERROR_ENABLE BIT(4)
+#endif
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#define BIT_PORT2_TRIPKT_OK_INT BIT(21)
+/* 2 REG_AXI_EXCEPT_CS (Offset 0x1350) */
+
+#define BIT_AXI_DECERR_W_FLAG BIT(3)
#endif
+#if (HALMAC_8822B_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */
+#define BIT_RXDMA_ERROR_HANDLE_STATUS BIT(3)
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+#endif
-#define BIT_FS_CLI1_TRIGGER_PKT_INT BIT(21)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#endif
+/* 2 REG_AXI_EXCEPT_CS (Offset 0x1350) */
+#define BIT_AXI_DECERR_R_FLAG BIT(2)
+#define BIT_AXI_SLVERR_W_FLAG BIT(1)
+#define BIT_AXI_SLVERR_R_FLAG BIT(0)
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8822B_SUPPORT)
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+/* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */
-#define BIT_PORT2_RX_EOSP_OK_INT BIT(20)
+#define BIT_SHIFT_AUTO_HANG_RELEASE 0
+#define BIT_MASK_AUTO_HANG_RELEASE 0x7
+#define BIT_AUTO_HANG_RELEASE(x) \
+ (((x) & BIT_MASK_AUTO_HANG_RELEASE) << BIT_SHIFT_AUTO_HANG_RELEASE)
+#define BITS_AUTO_HANG_RELEASE \
+ (BIT_MASK_AUTO_HANG_RELEASE << BIT_SHIFT_AUTO_HANG_RELEASE)
+#define BIT_CLEAR_AUTO_HANG_RELEASE(x) ((x) & (~BITS_AUTO_HANG_RELEASE))
+#define BIT_GET_AUTO_HANG_RELEASE(x) \
+ (((x) >> BIT_SHIFT_AUTO_HANG_RELEASE) & BIT_MASK_AUTO_HANG_RELEASE)
+#define BIT_SET_AUTO_HANG_RELEASE(x, v) \
+ (BIT_CLEAR_AUTO_HANG_RELEASE(x) | BIT_AUTO_HANG_RELEASE(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_AXI_EXCEPT_TIME (Offset 0x1354) */
+#define BIT_SHIFT_AXI_RECOVERY_TIME 24
+#define BIT_MASK_AXI_RECOVERY_TIME 0xff
+#define BIT_AXI_RECOVERY_TIME(x) \
+ (((x) & BIT_MASK_AXI_RECOVERY_TIME) << BIT_SHIFT_AXI_RECOVERY_TIME)
+#define BITS_AXI_RECOVERY_TIME \
+ (BIT_MASK_AXI_RECOVERY_TIME << BIT_SHIFT_AXI_RECOVERY_TIME)
+#define BIT_CLEAR_AXI_RECOVERY_TIME(x) ((x) & (~BITS_AXI_RECOVERY_TIME))
+#define BIT_GET_AXI_RECOVERY_TIME(x) \
+ (((x) >> BIT_SHIFT_AXI_RECOVERY_TIME) & BIT_MASK_AXI_RECOVERY_TIME)
+#define BIT_SET_AXI_RECOVERY_TIME(x, v) \
+ (BIT_CLEAR_AXI_RECOVERY_TIME(x) | BIT_AXI_RECOVERY_TIME(v))
+
+#define BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL 12
+#define BIT_MASK_AXI_RXDMA_TIMEOUT_VAL 0xfff
+#define BIT_AXI_RXDMA_TIMEOUT_VAL(x) \
+ (((x) & BIT_MASK_AXI_RXDMA_TIMEOUT_VAL) \
+ << BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL)
+#define BITS_AXI_RXDMA_TIMEOUT_VAL \
+ (BIT_MASK_AXI_RXDMA_TIMEOUT_VAL << BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL)
+#define BIT_CLEAR_AXI_RXDMA_TIMEOUT_VAL(x) ((x) & (~BITS_AXI_RXDMA_TIMEOUT_VAL))
+#define BIT_GET_AXI_RXDMA_TIMEOUT_VAL(x) \
+ (((x) >> BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL) & \
+ BIT_MASK_AXI_RXDMA_TIMEOUT_VAL)
+#define BIT_SET_AXI_RXDMA_TIMEOUT_VAL(x, v) \
+ (BIT_CLEAR_AXI_RXDMA_TIMEOUT_VAL(x) | BIT_AXI_RXDMA_TIMEOUT_VAL(v))
+
+#define BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL 0
+#define BIT_MASK_AXI_TXDMA_TIMEOUT_VAL 0xfff
+#define BIT_AXI_TXDMA_TIMEOUT_VAL(x) \
+ (((x) & BIT_MASK_AXI_TXDMA_TIMEOUT_VAL) \
+ << BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL)
+#define BITS_AXI_TXDMA_TIMEOUT_VAL \
+ (BIT_MASK_AXI_TXDMA_TIMEOUT_VAL << BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL)
+#define BIT_CLEAR_AXI_TXDMA_TIMEOUT_VAL(x) ((x) & (~BITS_AXI_TXDMA_TIMEOUT_VAL))
+#define BIT_GET_AXI_TXDMA_TIMEOUT_VAL(x) \
+ (((x) >> BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL) & \
+ BIT_MASK_AXI_TXDMA_TIMEOUT_VAL)
+#define BIT_SET_AXI_TXDMA_TIMEOUT_VAL(x, v) \
+ (BIT_CLEAR_AXI_TXDMA_TIMEOUT_VAL(x) | BIT_AXI_TXDMA_TIMEOUT_VAL(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DEBUG_STATE1 (Offset 0x1354) */
+
+#define BIT_SHIFT_DEBUG_STATE1 0
+#define BIT_MASK_DEBUG_STATE1 0xffffffffL
+#define BIT_DEBUG_STATE1(x) \
+ (((x) & BIT_MASK_DEBUG_STATE1) << BIT_SHIFT_DEBUG_STATE1)
+#define BITS_DEBUG_STATE1 (BIT_MASK_DEBUG_STATE1 << BIT_SHIFT_DEBUG_STATE1)
+#define BIT_CLEAR_DEBUG_STATE1(x) ((x) & (~BITS_DEBUG_STATE1))
+#define BIT_GET_DEBUG_STATE1(x) \
+ (((x) >> BIT_SHIFT_DEBUG_STATE1) & BIT_MASK_DEBUG_STATE1)
+#define BIT_SET_DEBUG_STATE1(x, v) \
+ (BIT_CLEAR_DEBUG_STATE1(x) | BIT_DEBUG_STATE1(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HI8Q_TXBD_IDX (Offset 0x1358) */
+
+#define BIT_SHIFT_HI8Q_HW_IDX 16
+#define BIT_MASK_HI8Q_HW_IDX 0xfff
+#define BIT_HI8Q_HW_IDX(x) \
+ (((x) & BIT_MASK_HI8Q_HW_IDX) << BIT_SHIFT_HI8Q_HW_IDX)
+#define BITS_HI8Q_HW_IDX (BIT_MASK_HI8Q_HW_IDX << BIT_SHIFT_HI8Q_HW_IDX)
+#define BIT_CLEAR_HI8Q_HW_IDX(x) ((x) & (~BITS_HI8Q_HW_IDX))
+#define BIT_GET_HI8Q_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_HI8Q_HW_IDX) & BIT_MASK_HI8Q_HW_IDX)
+#define BIT_SET_HI8Q_HW_IDX(x, v) \
+ (BIT_CLEAR_HI8Q_HW_IDX(x) | BIT_HI8Q_HW_IDX(v))
+
+#define BIT_SHIFT_HI8Q_HOST_IDX 0
+#define BIT_MASK_HI8Q_HOST_IDX 0xfff
+#define BIT_HI8Q_HOST_IDX(x) \
+ (((x) & BIT_MASK_HI8Q_HOST_IDX) << BIT_SHIFT_HI8Q_HOST_IDX)
+#define BITS_HI8Q_HOST_IDX (BIT_MASK_HI8Q_HOST_IDX << BIT_SHIFT_HI8Q_HOST_IDX)
+#define BIT_CLEAR_HI8Q_HOST_IDX(x) ((x) & (~BITS_HI8Q_HOST_IDX))
+#define BIT_GET_HI8Q_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_HI8Q_HOST_IDX) & BIT_MASK_HI8Q_HOST_IDX)
+#define BIT_SET_HI8Q_HOST_IDX(x, v) \
+ (BIT_CLEAR_HI8Q_HOST_IDX(x) | BIT_HI8Q_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DEBUG_STATE2 (Offset 0x1358) */
+
+#define BIT_SHIFT_DEBUG_STATE2 0
+#define BIT_MASK_DEBUG_STATE2 0xffffffffL
+#define BIT_DEBUG_STATE2(x) \
+ (((x) & BIT_MASK_DEBUG_STATE2) << BIT_SHIFT_DEBUG_STATE2)
+#define BITS_DEBUG_STATE2 (BIT_MASK_DEBUG_STATE2 << BIT_SHIFT_DEBUG_STATE2)
+#define BIT_CLEAR_DEBUG_STATE2(x) ((x) & (~BITS_DEBUG_STATE2))
+#define BIT_GET_DEBUG_STATE2(x) \
+ (((x) >> BIT_SHIFT_DEBUG_STATE2) & BIT_MASK_DEBUG_STATE2)
+#define BIT_SET_DEBUG_STATE2(x, v) \
+ (BIT_CLEAR_DEBUG_STATE2(x) | BIT_DEBUG_STATE2(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HI9Q_TXBD_IDX (Offset 0x135C) */
+
+#define BIT_SHIFT_HI9Q_HW_IDX 16
+#define BIT_MASK_HI9Q_HW_IDX 0xfff
+#define BIT_HI9Q_HW_IDX(x) \
+ (((x) & BIT_MASK_HI9Q_HW_IDX) << BIT_SHIFT_HI9Q_HW_IDX)
+#define BITS_HI9Q_HW_IDX (BIT_MASK_HI9Q_HW_IDX << BIT_SHIFT_HI9Q_HW_IDX)
+#define BIT_CLEAR_HI9Q_HW_IDX(x) ((x) & (~BITS_HI9Q_HW_IDX))
+#define BIT_GET_HI9Q_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_HI9Q_HW_IDX) & BIT_MASK_HI9Q_HW_IDX)
+#define BIT_SET_HI9Q_HW_IDX(x, v) \
+ (BIT_CLEAR_HI9Q_HW_IDX(x) | BIT_HI9Q_HW_IDX(v))
+
+#define BIT_SHIFT_HI9Q_HOST_IDX 0
+#define BIT_MASK_HI9Q_HOST_IDX 0xfff
+#define BIT_HI9Q_HOST_IDX(x) \
+ (((x) & BIT_MASK_HI9Q_HOST_IDX) << BIT_SHIFT_HI9Q_HOST_IDX)
+#define BITS_HI9Q_HOST_IDX (BIT_MASK_HI9Q_HOST_IDX << BIT_SHIFT_HI9Q_HOST_IDX)
+#define BIT_CLEAR_HI9Q_HOST_IDX(x) ((x) & (~BITS_HI9Q_HOST_IDX))
+#define BIT_GET_HI9Q_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_HI9Q_HOST_IDX) & BIT_MASK_HI9Q_HOST_IDX)
+#define BIT_SET_HI9Q_HOST_IDX(x, v) \
+ (BIT_CLEAR_HI9Q_HOST_IDX(x) | BIT_HI9Q_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_DEBUG_STATE3 (Offset 0x135C) */
+
+#define BIT_SHIFT_DEBUG_STATE3 0
+#define BIT_MASK_DEBUG_STATE3 0xffffffffL
+#define BIT_DEBUG_STATE3(x) \
+ (((x) & BIT_MASK_DEBUG_STATE3) << BIT_SHIFT_DEBUG_STATE3)
+#define BITS_DEBUG_STATE3 (BIT_MASK_DEBUG_STATE3 << BIT_SHIFT_DEBUG_STATE3)
+#define BIT_CLEAR_DEBUG_STATE3(x) ((x) & (~BITS_DEBUG_STATE3))
+#define BIT_GET_DEBUG_STATE3(x) \
+ (((x) >> BIT_SHIFT_DEBUG_STATE3) & BIT_MASK_DEBUG_STATE3)
+#define BIT_SET_DEBUG_STATE3(x, v) \
+ (BIT_CLEAR_DEBUG_STATE3(x) | BIT_DEBUG_STATE3(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HI10Q_TXBD_IDX (Offset 0x1360) */
+
+#define BIT_SHIFT_HI10Q_HW_IDX 16
+#define BIT_MASK_HI10Q_HW_IDX 0xfff
+#define BIT_HI10Q_HW_IDX(x) \
+ (((x) & BIT_MASK_HI10Q_HW_IDX) << BIT_SHIFT_HI10Q_HW_IDX)
+#define BITS_HI10Q_HW_IDX (BIT_MASK_HI10Q_HW_IDX << BIT_SHIFT_HI10Q_HW_IDX)
+#define BIT_CLEAR_HI10Q_HW_IDX(x) ((x) & (~BITS_HI10Q_HW_IDX))
+#define BIT_GET_HI10Q_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_HI10Q_HW_IDX) & BIT_MASK_HI10Q_HW_IDX)
+#define BIT_SET_HI10Q_HW_IDX(x, v) \
+ (BIT_CLEAR_HI10Q_HW_IDX(x) | BIT_HI10Q_HW_IDX(v))
+
+#define BIT_SHIFT_HI10Q_HOST_IDX 0
+#define BIT_MASK_HI10Q_HOST_IDX 0xfff
+#define BIT_HI10Q_HOST_IDX(x) \
+ (((x) & BIT_MASK_HI10Q_HOST_IDX) << BIT_SHIFT_HI10Q_HOST_IDX)
+#define BITS_HI10Q_HOST_IDX \
+ (BIT_MASK_HI10Q_HOST_IDX << BIT_SHIFT_HI10Q_HOST_IDX)
+#define BIT_CLEAR_HI10Q_HOST_IDX(x) ((x) & (~BITS_HI10Q_HOST_IDX))
+#define BIT_GET_HI10Q_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_HI10Q_HOST_IDX) & BIT_MASK_HI10Q_HOST_IDX)
+#define BIT_SET_HI10Q_HOST_IDX(x, v) \
+ (BIT_CLEAR_HI10Q_HOST_IDX(x) | BIT_HI10Q_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH5_TXBD_DESA_L (Offset 0x1360) */
+
+#define BIT_SHIFT_ACH5_TXBD_DESA_L 0
+#define BIT_MASK_ACH5_TXBD_DESA_L 0xffffffffL
+#define BIT_ACH5_TXBD_DESA_L(x) \
+ (((x) & BIT_MASK_ACH5_TXBD_DESA_L) << BIT_SHIFT_ACH5_TXBD_DESA_L)
+#define BITS_ACH5_TXBD_DESA_L \
+ (BIT_MASK_ACH5_TXBD_DESA_L << BIT_SHIFT_ACH5_TXBD_DESA_L)
+#define BIT_CLEAR_ACH5_TXBD_DESA_L(x) ((x) & (~BITS_ACH5_TXBD_DESA_L))
+#define BIT_GET_ACH5_TXBD_DESA_L(x) \
+ (((x) >> BIT_SHIFT_ACH5_TXBD_DESA_L) & BIT_MASK_ACH5_TXBD_DESA_L)
+#define BIT_SET_ACH5_TXBD_DESA_L(x, v) \
+ (BIT_CLEAR_ACH5_TXBD_DESA_L(x) | BIT_ACH5_TXBD_DESA_L(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HI11Q_TXBD_IDX (Offset 0x1364) */
+
+#define BIT_SHIFT_HI11Q_HW_IDX 16
+#define BIT_MASK_HI11Q_HW_IDX 0xfff
+#define BIT_HI11Q_HW_IDX(x) \
+ (((x) & BIT_MASK_HI11Q_HW_IDX) << BIT_SHIFT_HI11Q_HW_IDX)
+#define BITS_HI11Q_HW_IDX (BIT_MASK_HI11Q_HW_IDX << BIT_SHIFT_HI11Q_HW_IDX)
+#define BIT_CLEAR_HI11Q_HW_IDX(x) ((x) & (~BITS_HI11Q_HW_IDX))
+#define BIT_GET_HI11Q_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_HI11Q_HW_IDX) & BIT_MASK_HI11Q_HW_IDX)
+#define BIT_SET_HI11Q_HW_IDX(x, v) \
+ (BIT_CLEAR_HI11Q_HW_IDX(x) | BIT_HI11Q_HW_IDX(v))
+
+#define BIT_SHIFT_HI11Q_HOST_IDX 0
+#define BIT_MASK_HI11Q_HOST_IDX 0xfff
+#define BIT_HI11Q_HOST_IDX(x) \
+ (((x) & BIT_MASK_HI11Q_HOST_IDX) << BIT_SHIFT_HI11Q_HOST_IDX)
+#define BITS_HI11Q_HOST_IDX \
+ (BIT_MASK_HI11Q_HOST_IDX << BIT_SHIFT_HI11Q_HOST_IDX)
+#define BIT_CLEAR_HI11Q_HOST_IDX(x) ((x) & (~BITS_HI11Q_HOST_IDX))
+#define BIT_GET_HI11Q_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_HI11Q_HOST_IDX) & BIT_MASK_HI11Q_HOST_IDX)
+#define BIT_SET_HI11Q_HOST_IDX(x, v) \
+ (BIT_CLEAR_HI11Q_HOST_IDX(x) | BIT_HI11Q_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH5_TXBD_DESA_H (Offset 0x1364) */
+
+#define BIT_SHIFT_ACH5_TXBD_DESA_H 0
+#define BIT_MASK_ACH5_TXBD_DESA_H 0xffffffffL
+#define BIT_ACH5_TXBD_DESA_H(x) \
+ (((x) & BIT_MASK_ACH5_TXBD_DESA_H) << BIT_SHIFT_ACH5_TXBD_DESA_H)
+#define BITS_ACH5_TXBD_DESA_H \
+ (BIT_MASK_ACH5_TXBD_DESA_H << BIT_SHIFT_ACH5_TXBD_DESA_H)
+#define BIT_CLEAR_ACH5_TXBD_DESA_H(x) ((x) & (~BITS_ACH5_TXBD_DESA_H))
+#define BIT_GET_ACH5_TXBD_DESA_H(x) \
+ (((x) >> BIT_SHIFT_ACH5_TXBD_DESA_H) & BIT_MASK_ACH5_TXBD_DESA_H)
+#define BIT_SET_ACH5_TXBD_DESA_H(x, v) \
+ (BIT_CLEAR_ACH5_TXBD_DESA_H(x) | BIT_ACH5_TXBD_DESA_H(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HI12Q_TXBD_IDX (Offset 0x1368) */
+
+#define BIT_SHIFT_HI12Q_HW_IDX 16
+#define BIT_MASK_HI12Q_HW_IDX 0xfff
+#define BIT_HI12Q_HW_IDX(x) \
+ (((x) & BIT_MASK_HI12Q_HW_IDX) << BIT_SHIFT_HI12Q_HW_IDX)
+#define BITS_HI12Q_HW_IDX (BIT_MASK_HI12Q_HW_IDX << BIT_SHIFT_HI12Q_HW_IDX)
+#define BIT_CLEAR_HI12Q_HW_IDX(x) ((x) & (~BITS_HI12Q_HW_IDX))
+#define BIT_GET_HI12Q_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_HI12Q_HW_IDX) & BIT_MASK_HI12Q_HW_IDX)
+#define BIT_SET_HI12Q_HW_IDX(x, v) \
+ (BIT_CLEAR_HI12Q_HW_IDX(x) | BIT_HI12Q_HW_IDX(v))
+
+#define BIT_SHIFT_HI12Q_HOST_IDX 0
+#define BIT_MASK_HI12Q_HOST_IDX 0xfff
+#define BIT_HI12Q_HOST_IDX(x) \
+ (((x) & BIT_MASK_HI12Q_HOST_IDX) << BIT_SHIFT_HI12Q_HOST_IDX)
+#define BITS_HI12Q_HOST_IDX \
+ (BIT_MASK_HI12Q_HOST_IDX << BIT_SHIFT_HI12Q_HOST_IDX)
+#define BIT_CLEAR_HI12Q_HOST_IDX(x) ((x) & (~BITS_HI12Q_HOST_IDX))
+#define BIT_GET_HI12Q_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_HI12Q_HOST_IDX) & BIT_MASK_HI12Q_HOST_IDX)
+#define BIT_SET_HI12Q_HOST_IDX(x, v) \
+ (BIT_CLEAR_HI12Q_HOST_IDX(x) | BIT_HI12Q_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH6_TXBD_DESA_L (Offset 0x1368) */
+
+#define BIT_SHIFT_ACH6_TXBD_DESA_L 0
+#define BIT_MASK_ACH6_TXBD_DESA_L 0xffffffffL
+#define BIT_ACH6_TXBD_DESA_L(x) \
+ (((x) & BIT_MASK_ACH6_TXBD_DESA_L) << BIT_SHIFT_ACH6_TXBD_DESA_L)
+#define BITS_ACH6_TXBD_DESA_L \
+ (BIT_MASK_ACH6_TXBD_DESA_L << BIT_SHIFT_ACH6_TXBD_DESA_L)
+#define BIT_CLEAR_ACH6_TXBD_DESA_L(x) ((x) & (~BITS_ACH6_TXBD_DESA_L))
+#define BIT_GET_ACH6_TXBD_DESA_L(x) \
+ (((x) >> BIT_SHIFT_ACH6_TXBD_DESA_L) & BIT_MASK_ACH6_TXBD_DESA_L)
+#define BIT_SET_ACH6_TXBD_DESA_L(x, v) \
+ (BIT_CLEAR_ACH6_TXBD_DESA_L(x) | BIT_ACH6_TXBD_DESA_L(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HI13Q_TXBD_IDX (Offset 0x136C) */
+
+#define BIT_SHIFT_HI13Q_HW_IDX 16
+#define BIT_MASK_HI13Q_HW_IDX 0xfff
+#define BIT_HI13Q_HW_IDX(x) \
+ (((x) & BIT_MASK_HI13Q_HW_IDX) << BIT_SHIFT_HI13Q_HW_IDX)
+#define BITS_HI13Q_HW_IDX (BIT_MASK_HI13Q_HW_IDX << BIT_SHIFT_HI13Q_HW_IDX)
+#define BIT_CLEAR_HI13Q_HW_IDX(x) ((x) & (~BITS_HI13Q_HW_IDX))
+#define BIT_GET_HI13Q_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_HI13Q_HW_IDX) & BIT_MASK_HI13Q_HW_IDX)
+#define BIT_SET_HI13Q_HW_IDX(x, v) \
+ (BIT_CLEAR_HI13Q_HW_IDX(x) | BIT_HI13Q_HW_IDX(v))
+
+#define BIT_SHIFT_HI13Q_HOST_IDX 0
+#define BIT_MASK_HI13Q_HOST_IDX 0xfff
+#define BIT_HI13Q_HOST_IDX(x) \
+ (((x) & BIT_MASK_HI13Q_HOST_IDX) << BIT_SHIFT_HI13Q_HOST_IDX)
+#define BITS_HI13Q_HOST_IDX \
+ (BIT_MASK_HI13Q_HOST_IDX << BIT_SHIFT_HI13Q_HOST_IDX)
+#define BIT_CLEAR_HI13Q_HOST_IDX(x) ((x) & (~BITS_HI13Q_HOST_IDX))
+#define BIT_GET_HI13Q_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_HI13Q_HOST_IDX) & BIT_MASK_HI13Q_HOST_IDX)
+#define BIT_SET_HI13Q_HOST_IDX(x, v) \
+ (BIT_CLEAR_HI13Q_HOST_IDX(x) | BIT_HI13Q_HOST_IDX(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH6_TXBD_DESA_H (Offset 0x136C) */
+
+#define BIT_SHIFT_ACH6_TXBD_DESA_H 0
+#define BIT_MASK_ACH6_TXBD_DESA_H 0xffffffffL
+#define BIT_ACH6_TXBD_DESA_H(x) \
+ (((x) & BIT_MASK_ACH6_TXBD_DESA_H) << BIT_SHIFT_ACH6_TXBD_DESA_H)
+#define BITS_ACH6_TXBD_DESA_H \
+ (BIT_MASK_ACH6_TXBD_DESA_H << BIT_SHIFT_ACH6_TXBD_DESA_H)
+#define BIT_CLEAR_ACH6_TXBD_DESA_H(x) ((x) & (~BITS_ACH6_TXBD_DESA_H))
+#define BIT_GET_ACH6_TXBD_DESA_H(x) \
+ (((x) >> BIT_SHIFT_ACH6_TXBD_DESA_H) & BIT_MASK_ACH6_TXBD_DESA_H)
+#define BIT_SET_ACH6_TXBD_DESA_H(x, v) \
+ (BIT_CLEAR_ACH6_TXBD_DESA_H(x) | BIT_ACH6_TXBD_DESA_H(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HI14Q_TXBD_IDX (Offset 0x1370) */
+
+#define BIT_SHIFT_HI14Q_HW_IDX 16
+#define BIT_MASK_HI14Q_HW_IDX 0xfff
+#define BIT_HI14Q_HW_IDX(x) \
+ (((x) & BIT_MASK_HI14Q_HW_IDX) << BIT_SHIFT_HI14Q_HW_IDX)
+#define BITS_HI14Q_HW_IDX (BIT_MASK_HI14Q_HW_IDX << BIT_SHIFT_HI14Q_HW_IDX)
+#define BIT_CLEAR_HI14Q_HW_IDX(x) ((x) & (~BITS_HI14Q_HW_IDX))
+#define BIT_GET_HI14Q_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_HI14Q_HW_IDX) & BIT_MASK_HI14Q_HW_IDX)
+#define BIT_SET_HI14Q_HW_IDX(x, v) \
+ (BIT_CLEAR_HI14Q_HW_IDX(x) | BIT_HI14Q_HW_IDX(v))
+
+#define BIT_SHIFT_HI14Q_HOST_IDX 0
+#define BIT_MASK_HI14Q_HOST_IDX 0xfff
+#define BIT_HI14Q_HOST_IDX(x) \
+ (((x) & BIT_MASK_HI14Q_HOST_IDX) << BIT_SHIFT_HI14Q_HOST_IDX)
+#define BITS_HI14Q_HOST_IDX \
+ (BIT_MASK_HI14Q_HOST_IDX << BIT_SHIFT_HI14Q_HOST_IDX)
+#define BIT_CLEAR_HI14Q_HOST_IDX(x) ((x) & (~BITS_HI14Q_HOST_IDX))
+#define BIT_GET_HI14Q_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_HI14Q_HOST_IDX) & BIT_MASK_HI14Q_HOST_IDX)
+#define BIT_SET_HI14Q_HOST_IDX(x, v) \
+ (BIT_CLEAR_HI14Q_HOST_IDX(x) | BIT_HI14Q_HOST_IDX(v))
+
+#endif
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_FS_CLI1_EOSP_INT BIT(20)
+/* 2 REG_ACH7_TXBD_DESA_L (Offset 0x1370) */
-#endif
+#define BIT_SHIFT_ACH7_TXBD_DESA_L 0
+#define BIT_MASK_ACH7_TXBD_DESA_L 0xffffffffL
+#define BIT_ACH7_TXBD_DESA_L(x) \
+ (((x) & BIT_MASK_ACH7_TXBD_DESA_L) << BIT_SHIFT_ACH7_TXBD_DESA_L)
+#define BITS_ACH7_TXBD_DESA_L \
+ (BIT_MASK_ACH7_TXBD_DESA_L << BIT_SHIFT_ACH7_TXBD_DESA_L)
+#define BIT_CLEAR_ACH7_TXBD_DESA_L(x) ((x) & (~BITS_ACH7_TXBD_DESA_L))
+#define BIT_GET_ACH7_TXBD_DESA_L(x) \
+ (((x) >> BIT_SHIFT_ACH7_TXBD_DESA_L) & BIT_MASK_ACH7_TXBD_DESA_L)
+#define BIT_SET_ACH7_TXBD_DESA_L(x, v) \
+ (BIT_CLEAR_ACH7_TXBD_DESA_L(x) | BIT_ACH7_TXBD_DESA_L(v))
+#endif
-#if (HALMAC_8197F_SUPPORT)
+#if (HALMAC_8198F_SUPPORT)
+/* 2 REG_HI15Q_TXBD_IDX (Offset 0x1374) */
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+#define BIT_SHIFT_HI15Q_HW_IDX 16
+#define BIT_MASK_HI15Q_HW_IDX 0xfff
+#define BIT_HI15Q_HW_IDX(x) \
+ (((x) & BIT_MASK_HI15Q_HW_IDX) << BIT_SHIFT_HI15Q_HW_IDX)
+#define BITS_HI15Q_HW_IDX (BIT_MASK_HI15Q_HW_IDX << BIT_SHIFT_HI15Q_HW_IDX)
+#define BIT_CLEAR_HI15Q_HW_IDX(x) ((x) & (~BITS_HI15Q_HW_IDX))
+#define BIT_GET_HI15Q_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_HI15Q_HW_IDX) & BIT_MASK_HI15Q_HW_IDX)
+#define BIT_SET_HI15Q_HW_IDX(x, v) \
+ (BIT_CLEAR_HI15Q_HW_IDX(x) | BIT_HI15Q_HW_IDX(v))
-#define BIT_PORT1_RX_UCMD1_UAPSD0_OK_INT BIT(19)
+#define BIT_SHIFT_HI15Q_HOST_IDX 0
+#define BIT_MASK_HI15Q_HOST_IDX 0xfff
+#define BIT_HI15Q_HOST_IDX(x) \
+ (((x) & BIT_MASK_HI15Q_HOST_IDX) << BIT_SHIFT_HI15Q_HOST_IDX)
+#define BITS_HI15Q_HOST_IDX \
+ (BIT_MASK_HI15Q_HOST_IDX << BIT_SHIFT_HI15Q_HOST_IDX)
+#define BIT_CLEAR_HI15Q_HOST_IDX(x) ((x) & (~BITS_HI15Q_HOST_IDX))
+#define BIT_GET_HI15Q_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_HI15Q_HOST_IDX) & BIT_MASK_HI15Q_HOST_IDX)
+#define BIT_SET_HI15Q_HOST_IDX(x, v) \
+ (BIT_CLEAR_HI15Q_HOST_IDX(x) | BIT_HI15Q_HOST_IDX(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ACH7_TXBD_DESA_H (Offset 0x1374) */
+#define BIT_SHIFT_ACH7_TXBD_DESA_H 0
+#define BIT_MASK_ACH7_TXBD_DESA_H 0xffffffffL
+#define BIT_ACH7_TXBD_DESA_H(x) \
+ (((x) & BIT_MASK_ACH7_TXBD_DESA_H) << BIT_SHIFT_ACH7_TXBD_DESA_H)
+#define BITS_ACH7_TXBD_DESA_H \
+ (BIT_MASK_ACH7_TXBD_DESA_H << BIT_SHIFT_ACH7_TXBD_DESA_H)
+#define BIT_CLEAR_ACH7_TXBD_DESA_H(x) ((x) & (~BITS_ACH7_TXBD_DESA_H))
+#define BIT_GET_ACH7_TXBD_DESA_H(x) \
+ (((x) >> BIT_SHIFT_ACH7_TXBD_DESA_H) & BIT_MASK_ACH7_TXBD_DESA_H)
+#define BIT_SET_ACH7_TXBD_DESA_H(x, v) \
+ (BIT_CLEAR_ACH7_TXBD_DESA_H(x) | BIT_ACH7_TXBD_DESA_H(v))
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+#endif
-#define BIT_FS_CLI0_RX_UAPSDMD1_INT BIT(19)
+#if (HALMAC_8198F_SUPPORT)
-#endif
+/* 2 REG_HI8Q_TXBD_DESA (Offset 0x1378) */
+#define BIT_SHIFT_HI8Q_TXBD_DESA 0
+#define BIT_MASK_HI8Q_TXBD_DESA 0xffffffffffffffffL
+#define BIT_HI8Q_TXBD_DESA(x) \
+ (((x) & BIT_MASK_HI8Q_TXBD_DESA) << BIT_SHIFT_HI8Q_TXBD_DESA)
+#define BITS_HI8Q_TXBD_DESA \
+ (BIT_MASK_HI8Q_TXBD_DESA << BIT_SHIFT_HI8Q_TXBD_DESA)
+#define BIT_CLEAR_HI8Q_TXBD_DESA(x) ((x) & (~BITS_HI8Q_TXBD_DESA))
+#define BIT_GET_HI8Q_TXBD_DESA(x) \
+ (((x) >> BIT_SHIFT_HI8Q_TXBD_DESA) & BIT_MASK_HI8Q_TXBD_DESA)
+#define BIT_SET_HI8Q_TXBD_DESA(x, v) \
+ (BIT_CLEAR_HI8Q_TXBD_DESA(x) | BIT_HI8Q_TXBD_DESA(v))
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+/* 2 REG_ACH8_TXBD_DESA_L (Offset 0x1378) */
-#define BIT_PORT1_RX_UCMD0_UAPSD0_OK_INT BIT(18)
+#define BIT_SHIFT_ACH8_TXBD_DESA_L 0
+#define BIT_MASK_ACH8_TXBD_DESA_L 0xffffffffL
+#define BIT_ACH8_TXBD_DESA_L(x) \
+ (((x) & BIT_MASK_ACH8_TXBD_DESA_L) << BIT_SHIFT_ACH8_TXBD_DESA_L)
+#define BITS_ACH8_TXBD_DESA_L \
+ (BIT_MASK_ACH8_TXBD_DESA_L << BIT_SHIFT_ACH8_TXBD_DESA_L)
+#define BIT_CLEAR_ACH8_TXBD_DESA_L(x) ((x) & (~BITS_ACH8_TXBD_DESA_L))
+#define BIT_GET_ACH8_TXBD_DESA_L(x) \
+ (((x) >> BIT_SHIFT_ACH8_TXBD_DESA_L) & BIT_MASK_ACH8_TXBD_DESA_L)
+#define BIT_SET_ACH8_TXBD_DESA_L(x, v) \
+ (BIT_CLEAR_ACH8_TXBD_DESA_L(x) | BIT_ACH8_TXBD_DESA_L(v))
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_CHNL_DMA_CFG_V1 (Offset 0x137C) */
+#define BIT_TXHCI_EN_V1 BIT(26)
+#define BIT_TXHCI_IDLE_V1 BIT(25)
+#define BIT_DMA_PRI_EN_V1 BIT(24)
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+#endif
-#define BIT_FS_CLI0_RX_UAPSDMD0_INT BIT(18)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_ACH8_TXBD_DESA_H (Offset 0x137C) */
+#define BIT_SHIFT_ACH8_TXBD_DESA_H 0
+#define BIT_MASK_ACH8_TXBD_DESA_H 0xffffffffL
+#define BIT_ACH8_TXBD_DESA_H(x) \
+ (((x) & BIT_MASK_ACH8_TXBD_DESA_H) << BIT_SHIFT_ACH8_TXBD_DESA_H)
+#define BITS_ACH8_TXBD_DESA_H \
+ (BIT_MASK_ACH8_TXBD_DESA_H << BIT_SHIFT_ACH8_TXBD_DESA_H)
+#define BIT_CLEAR_ACH8_TXBD_DESA_H(x) ((x) & (~BITS_ACH8_TXBD_DESA_H))
+#define BIT_GET_ACH8_TXBD_DESA_H(x) \
+ (((x) >> BIT_SHIFT_ACH8_TXBD_DESA_H) & BIT_MASK_ACH8_TXBD_DESA_H)
+#define BIT_SET_ACH8_TXBD_DESA_H(x, v) \
+ (BIT_CLEAR_ACH8_TXBD_DESA_H(x) | BIT_ACH8_TXBD_DESA_H(v))
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8198F_SUPPORT)
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+/* 2 REG_HI9Q_TXBD_DESA (Offset 0x1380) */
-#define BIT_PORT1_TRIPKT_OK_INT BIT(17)
+#define BIT_SHIFT_HI9Q_TXBD_DESA 0
+#define BIT_MASK_HI9Q_TXBD_DESA 0xffffffffffffffffL
+#define BIT_HI9Q_TXBD_DESA(x) \
+ (((x) & BIT_MASK_HI9Q_TXBD_DESA) << BIT_SHIFT_HI9Q_TXBD_DESA)
+#define BITS_HI9Q_TXBD_DESA \
+ (BIT_MASK_HI9Q_TXBD_DESA << BIT_SHIFT_HI9Q_TXBD_DESA)
+#define BIT_CLEAR_HI9Q_TXBD_DESA(x) ((x) & (~BITS_HI9Q_TXBD_DESA))
+#define BIT_GET_HI9Q_TXBD_DESA(x) \
+ (((x) >> BIT_SHIFT_HI9Q_TXBD_DESA) & BIT_MASK_HI9Q_TXBD_DESA)
+#define BIT_SET_HI9Q_TXBD_DESA(x, v) \
+ (BIT_CLEAR_HI9Q_TXBD_DESA(x) | BIT_HI9Q_TXBD_DESA(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_ACH9_TXBD_DESA_L (Offset 0x1380) */
+#define BIT_SHIFT_ACH9_TXBD_DESA_L 0
+#define BIT_MASK_ACH9_TXBD_DESA_L 0xffffffffL
+#define BIT_ACH9_TXBD_DESA_L(x) \
+ (((x) & BIT_MASK_ACH9_TXBD_DESA_L) << BIT_SHIFT_ACH9_TXBD_DESA_L)
+#define BITS_ACH9_TXBD_DESA_L \
+ (BIT_MASK_ACH9_TXBD_DESA_L << BIT_SHIFT_ACH9_TXBD_DESA_L)
+#define BIT_CLEAR_ACH9_TXBD_DESA_L(x) ((x) & (~BITS_ACH9_TXBD_DESA_L))
+#define BIT_GET_ACH9_TXBD_DESA_L(x) \
+ (((x) >> BIT_SHIFT_ACH9_TXBD_DESA_L) & BIT_MASK_ACH9_TXBD_DESA_L)
+#define BIT_SET_ACH9_TXBD_DESA_L(x, v) \
+ (BIT_CLEAR_ACH9_TXBD_DESA_L(x) | BIT_ACH9_TXBD_DESA_L(v))
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+/* 2 REG_ACH9_TXBD_DESA_H (Offset 0x1384) */
-#define BIT_FS_CLI0_TRIGGER_PKT_INT BIT(17)
+#define BIT_SHIFT_ACH9_TXBD_DESA_H 0
+#define BIT_MASK_ACH9_TXBD_DESA_H 0xffffffffL
+#define BIT_ACH9_TXBD_DESA_H(x) \
+ (((x) & BIT_MASK_ACH9_TXBD_DESA_H) << BIT_SHIFT_ACH9_TXBD_DESA_H)
+#define BITS_ACH9_TXBD_DESA_H \
+ (BIT_MASK_ACH9_TXBD_DESA_H << BIT_SHIFT_ACH9_TXBD_DESA_H)
+#define BIT_CLEAR_ACH9_TXBD_DESA_H(x) ((x) & (~BITS_ACH9_TXBD_DESA_H))
+#define BIT_GET_ACH9_TXBD_DESA_H(x) \
+ (((x) >> BIT_SHIFT_ACH9_TXBD_DESA_H) & BIT_MASK_ACH9_TXBD_DESA_H)
+#define BIT_SET_ACH9_TXBD_DESA_H(x, v) \
+ (BIT_CLEAR_ACH9_TXBD_DESA_H(x) | BIT_ACH9_TXBD_DESA_H(v))
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_HI10Q_TXBD_DESA (Offset 0x1388) */
+#define BIT_SHIFT_HI10Q_TXBD_DESA 0
+#define BIT_MASK_HI10Q_TXBD_DESA 0xffffffffffffffffL
+#define BIT_HI10Q_TXBD_DESA(x) \
+ (((x) & BIT_MASK_HI10Q_TXBD_DESA) << BIT_SHIFT_HI10Q_TXBD_DESA)
+#define BITS_HI10Q_TXBD_DESA \
+ (BIT_MASK_HI10Q_TXBD_DESA << BIT_SHIFT_HI10Q_TXBD_DESA)
+#define BIT_CLEAR_HI10Q_TXBD_DESA(x) ((x) & (~BITS_HI10Q_TXBD_DESA))
+#define BIT_GET_HI10Q_TXBD_DESA(x) \
+ (((x) >> BIT_SHIFT_HI10Q_TXBD_DESA) & BIT_MASK_HI10Q_TXBD_DESA)
+#define BIT_SET_HI10Q_TXBD_DESA(x, v) \
+ (BIT_CLEAR_HI10Q_TXBD_DESA(x) | BIT_HI10Q_TXBD_DESA(v))
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH10_TXBD_DESA_L (Offset 0x1388) */
-#define BIT_PORT1_RX_EOSP_OK_INT BIT(16)
+#define BIT_SHIFT_ACH10_TXBD_DESA_L 0
+#define BIT_MASK_ACH10_TXBD_DESA_L 0xffffffffL
+#define BIT_ACH10_TXBD_DESA_L(x) \
+ (((x) & BIT_MASK_ACH10_TXBD_DESA_L) << BIT_SHIFT_ACH10_TXBD_DESA_L)
+#define BITS_ACH10_TXBD_DESA_L \
+ (BIT_MASK_ACH10_TXBD_DESA_L << BIT_SHIFT_ACH10_TXBD_DESA_L)
+#define BIT_CLEAR_ACH10_TXBD_DESA_L(x) ((x) & (~BITS_ACH10_TXBD_DESA_L))
+#define BIT_GET_ACH10_TXBD_DESA_L(x) \
+ (((x) >> BIT_SHIFT_ACH10_TXBD_DESA_L) & BIT_MASK_ACH10_TXBD_DESA_L)
+#define BIT_SET_ACH10_TXBD_DESA_L(x, v) \
+ (BIT_CLEAR_ACH10_TXBD_DESA_L(x) | BIT_ACH10_TXBD_DESA_L(v))
+
+/* 2 REG_ACH10_TXBD_DESA_H (Offset 0x138C) */
+
+#define BIT_SHIFT_ACH10_TXBD_DESA_H 0
+#define BIT_MASK_ACH10_TXBD_DESA_H 0xffffffffL
+#define BIT_ACH10_TXBD_DESA_H(x) \
+ (((x) & BIT_MASK_ACH10_TXBD_DESA_H) << BIT_SHIFT_ACH10_TXBD_DESA_H)
+#define BITS_ACH10_TXBD_DESA_H \
+ (BIT_MASK_ACH10_TXBD_DESA_H << BIT_SHIFT_ACH10_TXBD_DESA_H)
+#define BIT_CLEAR_ACH10_TXBD_DESA_H(x) ((x) & (~BITS_ACH10_TXBD_DESA_H))
+#define BIT_GET_ACH10_TXBD_DESA_H(x) \
+ (((x) >> BIT_SHIFT_ACH10_TXBD_DESA_H) & BIT_MASK_ACH10_TXBD_DESA_H)
+#define BIT_SET_ACH10_TXBD_DESA_H(x, v) \
+ (BIT_CLEAR_ACH10_TXBD_DESA_H(x) | BIT_ACH10_TXBD_DESA_H(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HI11Q_TXBD_DESA (Offset 0x1390) */
+
+#define BIT_SHIFT_HI11Q_TXBD_DESA 0
+#define BIT_MASK_HI11Q_TXBD_DESA 0xffffffffffffffffL
+#define BIT_HI11Q_TXBD_DESA(x) \
+ (((x) & BIT_MASK_HI11Q_TXBD_DESA) << BIT_SHIFT_HI11Q_TXBD_DESA)
+#define BITS_HI11Q_TXBD_DESA \
+ (BIT_MASK_HI11Q_TXBD_DESA << BIT_SHIFT_HI11Q_TXBD_DESA)
+#define BIT_CLEAR_HI11Q_TXBD_DESA(x) ((x) & (~BITS_HI11Q_TXBD_DESA))
+#define BIT_GET_HI11Q_TXBD_DESA(x) \
+ (((x) >> BIT_SHIFT_HI11Q_TXBD_DESA) & BIT_MASK_HI11Q_TXBD_DESA)
+#define BIT_SET_HI11Q_TXBD_DESA(x, v) \
+ (BIT_CLEAR_HI11Q_TXBD_DESA(x) | BIT_HI11Q_TXBD_DESA(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH11_TXBD_DESA_L (Offset 0x1390) */
+
+#define BIT_SHIFT_ACH11_TXBD_DESA_L 0
+#define BIT_MASK_ACH11_TXBD_DESA_L 0xffffffffL
+#define BIT_ACH11_TXBD_DESA_L(x) \
+ (((x) & BIT_MASK_ACH11_TXBD_DESA_L) << BIT_SHIFT_ACH11_TXBD_DESA_L)
+#define BITS_ACH11_TXBD_DESA_L \
+ (BIT_MASK_ACH11_TXBD_DESA_L << BIT_SHIFT_ACH11_TXBD_DESA_L)
+#define BIT_CLEAR_ACH11_TXBD_DESA_L(x) ((x) & (~BITS_ACH11_TXBD_DESA_L))
+#define BIT_GET_ACH11_TXBD_DESA_L(x) \
+ (((x) >> BIT_SHIFT_ACH11_TXBD_DESA_L) & BIT_MASK_ACH11_TXBD_DESA_L)
+#define BIT_SET_ACH11_TXBD_DESA_L(x, v) \
+ (BIT_CLEAR_ACH11_TXBD_DESA_L(x) | BIT_ACH11_TXBD_DESA_L(v))
+
+/* 2 REG_ACH11_TXBD_DESA_H (Offset 0x1394) */
+
+#define BIT_SHIFT_ACH11_TXBD_DESA_H 0
+#define BIT_MASK_ACH11_TXBD_DESA_H 0xffffffffL
+#define BIT_ACH11_TXBD_DESA_H(x) \
+ (((x) & BIT_MASK_ACH11_TXBD_DESA_H) << BIT_SHIFT_ACH11_TXBD_DESA_H)
+#define BITS_ACH11_TXBD_DESA_H \
+ (BIT_MASK_ACH11_TXBD_DESA_H << BIT_SHIFT_ACH11_TXBD_DESA_H)
+#define BIT_CLEAR_ACH11_TXBD_DESA_H(x) ((x) & (~BITS_ACH11_TXBD_DESA_H))
+#define BIT_GET_ACH11_TXBD_DESA_H(x) \
+ (((x) >> BIT_SHIFT_ACH11_TXBD_DESA_H) & BIT_MASK_ACH11_TXBD_DESA_H)
+#define BIT_SET_ACH11_TXBD_DESA_H(x, v) \
+ (BIT_CLEAR_ACH11_TXBD_DESA_H(x) | BIT_ACH11_TXBD_DESA_H(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HI12Q_TXBD_DESA (Offset 0x1398) */
+
+#define BIT_SHIFT_HI12Q_TXBD_DESA 0
+#define BIT_MASK_HI12Q_TXBD_DESA 0xffffffffffffffffL
+#define BIT_HI12Q_TXBD_DESA(x) \
+ (((x) & BIT_MASK_HI12Q_TXBD_DESA) << BIT_SHIFT_HI12Q_TXBD_DESA)
+#define BITS_HI12Q_TXBD_DESA \
+ (BIT_MASK_HI12Q_TXBD_DESA << BIT_SHIFT_HI12Q_TXBD_DESA)
+#define BIT_CLEAR_HI12Q_TXBD_DESA(x) ((x) & (~BITS_HI12Q_TXBD_DESA))
+#define BIT_GET_HI12Q_TXBD_DESA(x) \
+ (((x) >> BIT_SHIFT_HI12Q_TXBD_DESA) & BIT_MASK_HI12Q_TXBD_DESA)
+#define BIT_SET_HI12Q_TXBD_DESA(x, v) \
+ (BIT_CLEAR_HI12Q_TXBD_DESA(x) | BIT_HI12Q_TXBD_DESA(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH12_TXBD_DESA_L (Offset 0x1398) */
+
+#define BIT_SHIFT_ACH12_TXBD_DESA_L 0
+#define BIT_MASK_ACH12_TXBD_DESA_L 0xffffffffL
+#define BIT_ACH12_TXBD_DESA_L(x) \
+ (((x) & BIT_MASK_ACH12_TXBD_DESA_L) << BIT_SHIFT_ACH12_TXBD_DESA_L)
+#define BITS_ACH12_TXBD_DESA_L \
+ (BIT_MASK_ACH12_TXBD_DESA_L << BIT_SHIFT_ACH12_TXBD_DESA_L)
+#define BIT_CLEAR_ACH12_TXBD_DESA_L(x) ((x) & (~BITS_ACH12_TXBD_DESA_L))
+#define BIT_GET_ACH12_TXBD_DESA_L(x) \
+ (((x) >> BIT_SHIFT_ACH12_TXBD_DESA_L) & BIT_MASK_ACH12_TXBD_DESA_L)
+#define BIT_SET_ACH12_TXBD_DESA_L(x, v) \
+ (BIT_CLEAR_ACH12_TXBD_DESA_L(x) | BIT_ACH12_TXBD_DESA_L(v))
+
+/* 2 REG_ACH12_TXBD_DESA_H (Offset 0x139C) */
+
+#define BIT_SHIFT_ACH12_TXBD_DESA_H 0
+#define BIT_MASK_ACH12_TXBD_DESA_H 0xffffffffL
+#define BIT_ACH12_TXBD_DESA_H(x) \
+ (((x) & BIT_MASK_ACH12_TXBD_DESA_H) << BIT_SHIFT_ACH12_TXBD_DESA_H)
+#define BITS_ACH12_TXBD_DESA_H \
+ (BIT_MASK_ACH12_TXBD_DESA_H << BIT_SHIFT_ACH12_TXBD_DESA_H)
+#define BIT_CLEAR_ACH12_TXBD_DESA_H(x) ((x) & (~BITS_ACH12_TXBD_DESA_H))
+#define BIT_GET_ACH12_TXBD_DESA_H(x) \
+ (((x) >> BIT_SHIFT_ACH12_TXBD_DESA_H) & BIT_MASK_ACH12_TXBD_DESA_H)
+#define BIT_SET_ACH12_TXBD_DESA_H(x, v) \
+ (BIT_CLEAR_ACH12_TXBD_DESA_H(x) | BIT_ACH12_TXBD_DESA_H(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HI13Q_TXBD_DESA (Offset 0x13A0) */
+
+#define BIT_SHIFT_HI13Q_TXBD_DESA 0
+#define BIT_MASK_HI13Q_TXBD_DESA 0xffffffffffffffffL
+#define BIT_HI13Q_TXBD_DESA(x) \
+ (((x) & BIT_MASK_HI13Q_TXBD_DESA) << BIT_SHIFT_HI13Q_TXBD_DESA)
+#define BITS_HI13Q_TXBD_DESA \
+ (BIT_MASK_HI13Q_TXBD_DESA << BIT_SHIFT_HI13Q_TXBD_DESA)
+#define BIT_CLEAR_HI13Q_TXBD_DESA(x) ((x) & (~BITS_HI13Q_TXBD_DESA))
+#define BIT_GET_HI13Q_TXBD_DESA(x) \
+ (((x) >> BIT_SHIFT_HI13Q_TXBD_DESA) & BIT_MASK_HI13Q_TXBD_DESA)
+#define BIT_SET_HI13Q_TXBD_DESA(x, v) \
+ (BIT_CLEAR_HI13Q_TXBD_DESA(x) | BIT_HI13Q_TXBD_DESA(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH13_TXBD_DESA_L (Offset 0x13A0) */
+
+#define BIT_SHIFT_ACH13_TXBD_DESA_L 0
+#define BIT_MASK_ACH13_TXBD_DESA_L 0xffffffffL
+#define BIT_ACH13_TXBD_DESA_L(x) \
+ (((x) & BIT_MASK_ACH13_TXBD_DESA_L) << BIT_SHIFT_ACH13_TXBD_DESA_L)
+#define BITS_ACH13_TXBD_DESA_L \
+ (BIT_MASK_ACH13_TXBD_DESA_L << BIT_SHIFT_ACH13_TXBD_DESA_L)
+#define BIT_CLEAR_ACH13_TXBD_DESA_L(x) ((x) & (~BITS_ACH13_TXBD_DESA_L))
+#define BIT_GET_ACH13_TXBD_DESA_L(x) \
+ (((x) >> BIT_SHIFT_ACH13_TXBD_DESA_L) & BIT_MASK_ACH13_TXBD_DESA_L)
+#define BIT_SET_ACH13_TXBD_DESA_L(x, v) \
+ (BIT_CLEAR_ACH13_TXBD_DESA_L(x) | BIT_ACH13_TXBD_DESA_L(v))
+
+/* 2 REG_ACH13_TXBD_DESA_H (Offset 0x13A4) */
+
+#define BIT_SHIFT_ACH13_TXBD_DESA_H 0
+#define BIT_MASK_ACH13_TXBD_DESA_H 0xffffffffL
+#define BIT_ACH13_TXBD_DESA_H(x) \
+ (((x) & BIT_MASK_ACH13_TXBD_DESA_H) << BIT_SHIFT_ACH13_TXBD_DESA_H)
+#define BITS_ACH13_TXBD_DESA_H \
+ (BIT_MASK_ACH13_TXBD_DESA_H << BIT_SHIFT_ACH13_TXBD_DESA_H)
+#define BIT_CLEAR_ACH13_TXBD_DESA_H(x) ((x) & (~BITS_ACH13_TXBD_DESA_H))
+#define BIT_GET_ACH13_TXBD_DESA_H(x) \
+ (((x) >> BIT_SHIFT_ACH13_TXBD_DESA_H) & BIT_MASK_ACH13_TXBD_DESA_H)
+#define BIT_SET_ACH13_TXBD_DESA_H(x, v) \
+ (BIT_CLEAR_ACH13_TXBD_DESA_H(x) | BIT_ACH13_TXBD_DESA_H(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HI14Q_TXBD_DESA (Offset 0x13A8) */
+
+#define BIT_SHIFT_HI14Q_TXBD_DESA 0
+#define BIT_MASK_HI14Q_TXBD_DESA 0xffffffffffffffffL
+#define BIT_HI14Q_TXBD_DESA(x) \
+ (((x) & BIT_MASK_HI14Q_TXBD_DESA) << BIT_SHIFT_HI14Q_TXBD_DESA)
+#define BITS_HI14Q_TXBD_DESA \
+ (BIT_MASK_HI14Q_TXBD_DESA << BIT_SHIFT_HI14Q_TXBD_DESA)
+#define BIT_CLEAR_HI14Q_TXBD_DESA(x) ((x) & (~BITS_HI14Q_TXBD_DESA))
+#define BIT_GET_HI14Q_TXBD_DESA(x) \
+ (((x) >> BIT_SHIFT_HI14Q_TXBD_DESA) & BIT_MASK_HI14Q_TXBD_DESA)
+#define BIT_SET_HI14Q_TXBD_DESA(x, v) \
+ (BIT_CLEAR_HI14Q_TXBD_DESA(x) | BIT_HI14Q_TXBD_DESA(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HI0Q_TXBD_DESA_L (Offset 0x13A8) */
+
+#define BIT_SHIFT_HI0Q_TXBD_DESA_L 0
+#define BIT_MASK_HI0Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI0Q_TXBD_DESA_L(x) \
+ (((x) & BIT_MASK_HI0Q_TXBD_DESA_L) << BIT_SHIFT_HI0Q_TXBD_DESA_L)
+#define BITS_HI0Q_TXBD_DESA_L \
+ (BIT_MASK_HI0Q_TXBD_DESA_L << BIT_SHIFT_HI0Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI0Q_TXBD_DESA_L(x) ((x) & (~BITS_HI0Q_TXBD_DESA_L))
+#define BIT_GET_HI0Q_TXBD_DESA_L(x) \
+ (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_L) & BIT_MASK_HI0Q_TXBD_DESA_L)
+#define BIT_SET_HI0Q_TXBD_DESA_L(x, v) \
+ (BIT_CLEAR_HI0Q_TXBD_DESA_L(x) | BIT_HI0Q_TXBD_DESA_L(v))
+
+/* 2 REG_HI0Q_TXBD_DESA_H (Offset 0x13AC) */
+
+#define BIT_SHIFT_HI0Q_TXBD_DESA_H 0
+#define BIT_MASK_HI0Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI0Q_TXBD_DESA_H(x) \
+ (((x) & BIT_MASK_HI0Q_TXBD_DESA_H) << BIT_SHIFT_HI0Q_TXBD_DESA_H)
+#define BITS_HI0Q_TXBD_DESA_H \
+ (BIT_MASK_HI0Q_TXBD_DESA_H << BIT_SHIFT_HI0Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI0Q_TXBD_DESA_H(x) ((x) & (~BITS_HI0Q_TXBD_DESA_H))
+#define BIT_GET_HI0Q_TXBD_DESA_H(x) \
+ (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_H) & BIT_MASK_HI0Q_TXBD_DESA_H)
+#define BIT_SET_HI0Q_TXBD_DESA_H(x, v) \
+ (BIT_CLEAR_HI0Q_TXBD_DESA_H(x) | BIT_HI0Q_TXBD_DESA_H(v))
#endif
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HI15Q_TXBD_DESA (Offset 0x13B0) */
+
+#define BIT_SHIFT_HI15Q_TXBD_DESA 0
+#define BIT_MASK_HI15Q_TXBD_DESA 0xffffffffffffffffL
+#define BIT_HI15Q_TXBD_DESA(x) \
+ (((x) & BIT_MASK_HI15Q_TXBD_DESA) << BIT_SHIFT_HI15Q_TXBD_DESA)
+#define BITS_HI15Q_TXBD_DESA \
+ (BIT_MASK_HI15Q_TXBD_DESA << BIT_SHIFT_HI15Q_TXBD_DESA)
+#define BIT_CLEAR_HI15Q_TXBD_DESA(x) ((x) & (~BITS_HI15Q_TXBD_DESA))
+#define BIT_GET_HI15Q_TXBD_DESA(x) \
+ (((x) >> BIT_SHIFT_HI15Q_TXBD_DESA) & BIT_MASK_HI15Q_TXBD_DESA)
+#define BIT_SET_HI15Q_TXBD_DESA(x, v) \
+ (BIT_CLEAR_HI15Q_TXBD_DESA(x) | BIT_HI15Q_TXBD_DESA(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HI1Q_TXBD_DESA_L (Offset 0x13B0) */
+
+#define BIT_SHIFT_HI1Q_TXBD_DESA_L 0
+#define BIT_MASK_HI1Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI1Q_TXBD_DESA_L(x) \
+ (((x) & BIT_MASK_HI1Q_TXBD_DESA_L) << BIT_SHIFT_HI1Q_TXBD_DESA_L)
+#define BITS_HI1Q_TXBD_DESA_L \
+ (BIT_MASK_HI1Q_TXBD_DESA_L << BIT_SHIFT_HI1Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI1Q_TXBD_DESA_L(x) ((x) & (~BITS_HI1Q_TXBD_DESA_L))
+#define BIT_GET_HI1Q_TXBD_DESA_L(x) \
+ (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_L) & BIT_MASK_HI1Q_TXBD_DESA_L)
+#define BIT_SET_HI1Q_TXBD_DESA_L(x, v) \
+ (BIT_CLEAR_HI1Q_TXBD_DESA_L(x) | BIT_HI1Q_TXBD_DESA_L(v))
+
+/* 2 REG_HI1Q_TXBD_DESA_H (Offset 0x13B4) */
+
+#define BIT_SHIFT_HI1Q_TXBD_DESA_H 0
+#define BIT_MASK_HI1Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI1Q_TXBD_DESA_H(x) \
+ (((x) & BIT_MASK_HI1Q_TXBD_DESA_H) << BIT_SHIFT_HI1Q_TXBD_DESA_H)
+#define BITS_HI1Q_TXBD_DESA_H \
+ (BIT_MASK_HI1Q_TXBD_DESA_H << BIT_SHIFT_HI1Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI1Q_TXBD_DESA_H(x) ((x) & (~BITS_HI1Q_TXBD_DESA_H))
+#define BIT_GET_HI1Q_TXBD_DESA_H(x) \
+ (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_H) & BIT_MASK_HI1Q_TXBD_DESA_H)
+#define BIT_SET_HI1Q_TXBD_DESA_H(x, v) \
+ (BIT_CLEAR_HI1Q_TXBD_DESA_H(x) | BIT_HI1Q_TXBD_DESA_H(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HI8Q_TXBD_NUM (Offset 0x13B8) */
+
+#define BIT_HI8Q_FLAG BIT(14)
+
+#define BIT_SHIFT_HI8Q_DESC_MODE 12
+#define BIT_MASK_HI8Q_DESC_MODE 0x3
+#define BIT_HI8Q_DESC_MODE(x) \
+ (((x) & BIT_MASK_HI8Q_DESC_MODE) << BIT_SHIFT_HI8Q_DESC_MODE)
+#define BITS_HI8Q_DESC_MODE \
+ (BIT_MASK_HI8Q_DESC_MODE << BIT_SHIFT_HI8Q_DESC_MODE)
+#define BIT_CLEAR_HI8Q_DESC_MODE(x) ((x) & (~BITS_HI8Q_DESC_MODE))
+#define BIT_GET_HI8Q_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_HI8Q_DESC_MODE) & BIT_MASK_HI8Q_DESC_MODE)
+#define BIT_SET_HI8Q_DESC_MODE(x, v) \
+ (BIT_CLEAR_HI8Q_DESC_MODE(x) | BIT_HI8Q_DESC_MODE(v))
+
+#define BIT_SHIFT_HI8Q_DESC_NUM 0
+#define BIT_MASK_HI8Q_DESC_NUM 0xfff
+#define BIT_HI8Q_DESC_NUM(x) \
+ (((x) & BIT_MASK_HI8Q_DESC_NUM) << BIT_SHIFT_HI8Q_DESC_NUM)
+#define BITS_HI8Q_DESC_NUM (BIT_MASK_HI8Q_DESC_NUM << BIT_SHIFT_HI8Q_DESC_NUM)
+#define BIT_CLEAR_HI8Q_DESC_NUM(x) ((x) & (~BITS_HI8Q_DESC_NUM))
+#define BIT_GET_HI8Q_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_HI8Q_DESC_NUM) & BIT_MASK_HI8Q_DESC_NUM)
+#define BIT_SET_HI8Q_DESC_NUM(x, v) \
+ (BIT_CLEAR_HI8Q_DESC_NUM(x) | BIT_HI8Q_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HI2Q_TXBD_DESA_L (Offset 0x13B8) */
+
+#define BIT_SHIFT_HI2Q_TXBD_DESA_L 0
+#define BIT_MASK_HI2Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI2Q_TXBD_DESA_L(x) \
+ (((x) & BIT_MASK_HI2Q_TXBD_DESA_L) << BIT_SHIFT_HI2Q_TXBD_DESA_L)
+#define BITS_HI2Q_TXBD_DESA_L \
+ (BIT_MASK_HI2Q_TXBD_DESA_L << BIT_SHIFT_HI2Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI2Q_TXBD_DESA_L(x) ((x) & (~BITS_HI2Q_TXBD_DESA_L))
+#define BIT_GET_HI2Q_TXBD_DESA_L(x) \
+ (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_L) & BIT_MASK_HI2Q_TXBD_DESA_L)
+#define BIT_SET_HI2Q_TXBD_DESA_L(x, v) \
+ (BIT_CLEAR_HI2Q_TXBD_DESA_L(x) | BIT_HI2Q_TXBD_DESA_L(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HI9Q_TXBD_NUM (Offset 0x13BA) */
+
+#define BIT_HI9Q_FLAG BIT(14)
+
+#define BIT_SHIFT_HI9Q_DESC_MODE 12
+#define BIT_MASK_HI9Q_DESC_MODE 0x3
+#define BIT_HI9Q_DESC_MODE(x) \
+ (((x) & BIT_MASK_HI9Q_DESC_MODE) << BIT_SHIFT_HI9Q_DESC_MODE)
+#define BITS_HI9Q_DESC_MODE \
+ (BIT_MASK_HI9Q_DESC_MODE << BIT_SHIFT_HI9Q_DESC_MODE)
+#define BIT_CLEAR_HI9Q_DESC_MODE(x) ((x) & (~BITS_HI9Q_DESC_MODE))
+#define BIT_GET_HI9Q_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_HI9Q_DESC_MODE) & BIT_MASK_HI9Q_DESC_MODE)
+#define BIT_SET_HI9Q_DESC_MODE(x, v) \
+ (BIT_CLEAR_HI9Q_DESC_MODE(x) | BIT_HI9Q_DESC_MODE(v))
+
+#define BIT_SHIFT_HI9Q_DESC_NUM 0
+#define BIT_MASK_HI9Q_DESC_NUM 0xfff
+#define BIT_HI9Q_DESC_NUM(x) \
+ (((x) & BIT_MASK_HI9Q_DESC_NUM) << BIT_SHIFT_HI9Q_DESC_NUM)
+#define BITS_HI9Q_DESC_NUM (BIT_MASK_HI9Q_DESC_NUM << BIT_SHIFT_HI9Q_DESC_NUM)
+#define BIT_CLEAR_HI9Q_DESC_NUM(x) ((x) & (~BITS_HI9Q_DESC_NUM))
+#define BIT_GET_HI9Q_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_HI9Q_DESC_NUM) & BIT_MASK_HI9Q_DESC_NUM)
+#define BIT_SET_HI9Q_DESC_NUM(x, v) \
+ (BIT_CLEAR_HI9Q_DESC_NUM(x) | BIT_HI9Q_DESC_NUM(v))
+
+/* 2 REG_HI10Q_TXBD_NUM (Offset 0x13BC) */
+
+#define BIT_HI10Q_FLAG BIT(14)
+
+#define BIT_SHIFT_HI10Q_DESC_MODE 12
+#define BIT_MASK_HI10Q_DESC_MODE 0x3
+#define BIT_HI10Q_DESC_MODE(x) \
+ (((x) & BIT_MASK_HI10Q_DESC_MODE) << BIT_SHIFT_HI10Q_DESC_MODE)
+#define BITS_HI10Q_DESC_MODE \
+ (BIT_MASK_HI10Q_DESC_MODE << BIT_SHIFT_HI10Q_DESC_MODE)
+#define BIT_CLEAR_HI10Q_DESC_MODE(x) ((x) & (~BITS_HI10Q_DESC_MODE))
+#define BIT_GET_HI10Q_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_HI10Q_DESC_MODE) & BIT_MASK_HI10Q_DESC_MODE)
+#define BIT_SET_HI10Q_DESC_MODE(x, v) \
+ (BIT_CLEAR_HI10Q_DESC_MODE(x) | BIT_HI10Q_DESC_MODE(v))
+
+#define BIT_SHIFT_HI10Q_DESC_NUM 0
+#define BIT_MASK_HI10Q_DESC_NUM 0xfff
+#define BIT_HI10Q_DESC_NUM(x) \
+ (((x) & BIT_MASK_HI10Q_DESC_NUM) << BIT_SHIFT_HI10Q_DESC_NUM)
+#define BITS_HI10Q_DESC_NUM \
+ (BIT_MASK_HI10Q_DESC_NUM << BIT_SHIFT_HI10Q_DESC_NUM)
+#define BIT_CLEAR_HI10Q_DESC_NUM(x) ((x) & (~BITS_HI10Q_DESC_NUM))
+#define BIT_GET_HI10Q_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_HI10Q_DESC_NUM) & BIT_MASK_HI10Q_DESC_NUM)
+#define BIT_SET_HI10Q_DESC_NUM(x, v) \
+ (BIT_CLEAR_HI10Q_DESC_NUM(x) | BIT_HI10Q_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HI2Q_TXBD_DESA_H (Offset 0x13BC) */
+
+#define BIT_SHIFT_HI2Q_TXBD_DESA_H 0
+#define BIT_MASK_HI2Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI2Q_TXBD_DESA_H(x) \
+ (((x) & BIT_MASK_HI2Q_TXBD_DESA_H) << BIT_SHIFT_HI2Q_TXBD_DESA_H)
+#define BITS_HI2Q_TXBD_DESA_H \
+ (BIT_MASK_HI2Q_TXBD_DESA_H << BIT_SHIFT_HI2Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI2Q_TXBD_DESA_H(x) ((x) & (~BITS_HI2Q_TXBD_DESA_H))
+#define BIT_GET_HI2Q_TXBD_DESA_H(x) \
+ (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_H) & BIT_MASK_HI2Q_TXBD_DESA_H)
+#define BIT_SET_HI2Q_TXBD_DESA_H(x, v) \
+ (BIT_CLEAR_HI2Q_TXBD_DESA_H(x) | BIT_HI2Q_TXBD_DESA_H(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HI11Q_TXBD_NUM (Offset 0x13BE) */
+
+#define BIT_HI11Q_FLAG BIT(14)
+
+#define BIT_SHIFT_HI11Q_DESC_MODE 12
+#define BIT_MASK_HI11Q_DESC_MODE 0x3
+#define BIT_HI11Q_DESC_MODE(x) \
+ (((x) & BIT_MASK_HI11Q_DESC_MODE) << BIT_SHIFT_HI11Q_DESC_MODE)
+#define BITS_HI11Q_DESC_MODE \
+ (BIT_MASK_HI11Q_DESC_MODE << BIT_SHIFT_HI11Q_DESC_MODE)
+#define BIT_CLEAR_HI11Q_DESC_MODE(x) ((x) & (~BITS_HI11Q_DESC_MODE))
+#define BIT_GET_HI11Q_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_HI11Q_DESC_MODE) & BIT_MASK_HI11Q_DESC_MODE)
+#define BIT_SET_HI11Q_DESC_MODE(x, v) \
+ (BIT_CLEAR_HI11Q_DESC_MODE(x) | BIT_HI11Q_DESC_MODE(v))
+
+#define BIT_SHIFT_HI11Q_DESC_NUM 0
+#define BIT_MASK_HI11Q_DESC_NUM 0xfff
+#define BIT_HI11Q_DESC_NUM(x) \
+ (((x) & BIT_MASK_HI11Q_DESC_NUM) << BIT_SHIFT_HI11Q_DESC_NUM)
+#define BITS_HI11Q_DESC_NUM \
+ (BIT_MASK_HI11Q_DESC_NUM << BIT_SHIFT_HI11Q_DESC_NUM)
+#define BIT_CLEAR_HI11Q_DESC_NUM(x) ((x) & (~BITS_HI11Q_DESC_NUM))
+#define BIT_GET_HI11Q_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_HI11Q_DESC_NUM) & BIT_MASK_HI11Q_DESC_NUM)
+#define BIT_SET_HI11Q_DESC_NUM(x, v) \
+ (BIT_CLEAR_HI11Q_DESC_NUM(x) | BIT_HI11Q_DESC_NUM(v))
+
+/* 2 REG_HI12Q_TXBD_NUM (Offset 0x13C0) */
+
+#define BIT_HI12Q_FLAG BIT(14)
+
+#define BIT_SHIFT_HI12Q_DESC_MODE 12
+#define BIT_MASK_HI12Q_DESC_MODE 0x3
+#define BIT_HI12Q_DESC_MODE(x) \
+ (((x) & BIT_MASK_HI12Q_DESC_MODE) << BIT_SHIFT_HI12Q_DESC_MODE)
+#define BITS_HI12Q_DESC_MODE \
+ (BIT_MASK_HI12Q_DESC_MODE << BIT_SHIFT_HI12Q_DESC_MODE)
+#define BIT_CLEAR_HI12Q_DESC_MODE(x) ((x) & (~BITS_HI12Q_DESC_MODE))
+#define BIT_GET_HI12Q_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_HI12Q_DESC_MODE) & BIT_MASK_HI12Q_DESC_MODE)
+#define BIT_SET_HI12Q_DESC_MODE(x, v) \
+ (BIT_CLEAR_HI12Q_DESC_MODE(x) | BIT_HI12Q_DESC_MODE(v))
+
+#define BIT_SHIFT_HI12Q_DESC_NUM 0
+#define BIT_MASK_HI12Q_DESC_NUM 0xfff
+#define BIT_HI12Q_DESC_NUM(x) \
+ (((x) & BIT_MASK_HI12Q_DESC_NUM) << BIT_SHIFT_HI12Q_DESC_NUM)
+#define BITS_HI12Q_DESC_NUM \
+ (BIT_MASK_HI12Q_DESC_NUM << BIT_SHIFT_HI12Q_DESC_NUM)
+#define BIT_CLEAR_HI12Q_DESC_NUM(x) ((x) & (~BITS_HI12Q_DESC_NUM))
+#define BIT_GET_HI12Q_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_HI12Q_DESC_NUM) & BIT_MASK_HI12Q_DESC_NUM)
+#define BIT_SET_HI12Q_DESC_NUM(x, v) \
+ (BIT_CLEAR_HI12Q_DESC_NUM(x) | BIT_HI12Q_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HI3Q_TXBD_DESA_L (Offset 0x13C0) */
+
+#define BIT_SHIFT_HI3Q_TXBD_DESA_L 0
+#define BIT_MASK_HI3Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI3Q_TXBD_DESA_L(x) \
+ (((x) & BIT_MASK_HI3Q_TXBD_DESA_L) << BIT_SHIFT_HI3Q_TXBD_DESA_L)
+#define BITS_HI3Q_TXBD_DESA_L \
+ (BIT_MASK_HI3Q_TXBD_DESA_L << BIT_SHIFT_HI3Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI3Q_TXBD_DESA_L(x) ((x) & (~BITS_HI3Q_TXBD_DESA_L))
+#define BIT_GET_HI3Q_TXBD_DESA_L(x) \
+ (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_L) & BIT_MASK_HI3Q_TXBD_DESA_L)
+#define BIT_SET_HI3Q_TXBD_DESA_L(x, v) \
+ (BIT_CLEAR_HI3Q_TXBD_DESA_L(x) | BIT_HI3Q_TXBD_DESA_L(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HI13Q_TXBD_NUM (Offset 0x13C2) */
+
+#define BIT_HI13Q_FLAG BIT(14)
+
+#define BIT_SHIFT_HI13Q_DESC_MODE 12
+#define BIT_MASK_HI13Q_DESC_MODE 0x3
+#define BIT_HI13Q_DESC_MODE(x) \
+ (((x) & BIT_MASK_HI13Q_DESC_MODE) << BIT_SHIFT_HI13Q_DESC_MODE)
+#define BITS_HI13Q_DESC_MODE \
+ (BIT_MASK_HI13Q_DESC_MODE << BIT_SHIFT_HI13Q_DESC_MODE)
+#define BIT_CLEAR_HI13Q_DESC_MODE(x) ((x) & (~BITS_HI13Q_DESC_MODE))
+#define BIT_GET_HI13Q_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_HI13Q_DESC_MODE) & BIT_MASK_HI13Q_DESC_MODE)
+#define BIT_SET_HI13Q_DESC_MODE(x, v) \
+ (BIT_CLEAR_HI13Q_DESC_MODE(x) | BIT_HI13Q_DESC_MODE(v))
+
+#define BIT_SHIFT_HI13Q_DESC_NUM 0
+#define BIT_MASK_HI13Q_DESC_NUM 0xfff
+#define BIT_HI13Q_DESC_NUM(x) \
+ (((x) & BIT_MASK_HI13Q_DESC_NUM) << BIT_SHIFT_HI13Q_DESC_NUM)
+#define BITS_HI13Q_DESC_NUM \
+ (BIT_MASK_HI13Q_DESC_NUM << BIT_SHIFT_HI13Q_DESC_NUM)
+#define BIT_CLEAR_HI13Q_DESC_NUM(x) ((x) & (~BITS_HI13Q_DESC_NUM))
+#define BIT_GET_HI13Q_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_HI13Q_DESC_NUM) & BIT_MASK_HI13Q_DESC_NUM)
+#define BIT_SET_HI13Q_DESC_NUM(x, v) \
+ (BIT_CLEAR_HI13Q_DESC_NUM(x) | BIT_HI13Q_DESC_NUM(v))
+
+/* 2 REG_HI14Q_TXBD_NUM (Offset 0x13C4) */
+
+#define BIT_HI14Q_FLAG BIT(14)
+
+#define BIT_SHIFT_HI14Q_DESC_MODE 12
+#define BIT_MASK_HI14Q_DESC_MODE 0x3
+#define BIT_HI14Q_DESC_MODE(x) \
+ (((x) & BIT_MASK_HI14Q_DESC_MODE) << BIT_SHIFT_HI14Q_DESC_MODE)
+#define BITS_HI14Q_DESC_MODE \
+ (BIT_MASK_HI14Q_DESC_MODE << BIT_SHIFT_HI14Q_DESC_MODE)
+#define BIT_CLEAR_HI14Q_DESC_MODE(x) ((x) & (~BITS_HI14Q_DESC_MODE))
+#define BIT_GET_HI14Q_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_HI14Q_DESC_MODE) & BIT_MASK_HI14Q_DESC_MODE)
+#define BIT_SET_HI14Q_DESC_MODE(x, v) \
+ (BIT_CLEAR_HI14Q_DESC_MODE(x) | BIT_HI14Q_DESC_MODE(v))
+
+#define BIT_SHIFT_HI14Q_DESC_NUM 0
+#define BIT_MASK_HI14Q_DESC_NUM 0xfff
+#define BIT_HI14Q_DESC_NUM(x) \
+ (((x) & BIT_MASK_HI14Q_DESC_NUM) << BIT_SHIFT_HI14Q_DESC_NUM)
+#define BITS_HI14Q_DESC_NUM \
+ (BIT_MASK_HI14Q_DESC_NUM << BIT_SHIFT_HI14Q_DESC_NUM)
+#define BIT_CLEAR_HI14Q_DESC_NUM(x) ((x) & (~BITS_HI14Q_DESC_NUM))
+#define BIT_GET_HI14Q_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_HI14Q_DESC_NUM) & BIT_MASK_HI14Q_DESC_NUM)
+#define BIT_SET_HI14Q_DESC_NUM(x, v) \
+ (BIT_CLEAR_HI14Q_DESC_NUM(x) | BIT_HI14Q_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HI3Q_TXBD_DESA_H (Offset 0x13C4) */
+
+#define BIT_SHIFT_HI3Q_TXBD_DESA_H 0
+#define BIT_MASK_HI3Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI3Q_TXBD_DESA_H(x) \
+ (((x) & BIT_MASK_HI3Q_TXBD_DESA_H) << BIT_SHIFT_HI3Q_TXBD_DESA_H)
+#define BITS_HI3Q_TXBD_DESA_H \
+ (BIT_MASK_HI3Q_TXBD_DESA_H << BIT_SHIFT_HI3Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI3Q_TXBD_DESA_H(x) ((x) & (~BITS_HI3Q_TXBD_DESA_H))
+#define BIT_GET_HI3Q_TXBD_DESA_H(x) \
+ (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_H) & BIT_MASK_HI3Q_TXBD_DESA_H)
+#define BIT_SET_HI3Q_TXBD_DESA_H(x, v) \
+ (BIT_CLEAR_HI3Q_TXBD_DESA_H(x) | BIT_HI3Q_TXBD_DESA_H(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_HI15Q_TXBD_NUM (Offset 0x13C6) */
+
+#define BIT_HI15Q_FLAG BIT(14)
+
+#define BIT_SHIFT_HI15Q_DESC_MODE 12
+#define BIT_MASK_HI15Q_DESC_MODE 0x3
+#define BIT_HI15Q_DESC_MODE(x) \
+ (((x) & BIT_MASK_HI15Q_DESC_MODE) << BIT_SHIFT_HI15Q_DESC_MODE)
+#define BITS_HI15Q_DESC_MODE \
+ (BIT_MASK_HI15Q_DESC_MODE << BIT_SHIFT_HI15Q_DESC_MODE)
+#define BIT_CLEAR_HI15Q_DESC_MODE(x) ((x) & (~BITS_HI15Q_DESC_MODE))
+#define BIT_GET_HI15Q_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_HI15Q_DESC_MODE) & BIT_MASK_HI15Q_DESC_MODE)
+#define BIT_SET_HI15Q_DESC_MODE(x, v) \
+ (BIT_CLEAR_HI15Q_DESC_MODE(x) | BIT_HI15Q_DESC_MODE(v))
+
+#define BIT_SHIFT_HI15Q_DESC_NUM 0
+#define BIT_MASK_HI15Q_DESC_NUM 0xfff
+#define BIT_HI15Q_DESC_NUM(x) \
+ (((x) & BIT_MASK_HI15Q_DESC_NUM) << BIT_SHIFT_HI15Q_DESC_NUM)
+#define BITS_HI15Q_DESC_NUM \
+ (BIT_MASK_HI15Q_DESC_NUM << BIT_SHIFT_HI15Q_DESC_NUM)
+#define BIT_CLEAR_HI15Q_DESC_NUM(x) ((x) & (~BITS_HI15Q_DESC_NUM))
+#define BIT_GET_HI15Q_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_HI15Q_DESC_NUM) & BIT_MASK_HI15Q_DESC_NUM)
+#define BIT_SET_HI15Q_DESC_NUM(x, v) \
+ (BIT_CLEAR_HI15Q_DESC_NUM(x) | BIT_HI15Q_DESC_NUM(v))
+
+/* 2 REG_HIQ_DMA_STOP (Offset 0x13C8) */
+
+#define BIT_STOP_HI15Q BIT(7)
+#define BIT_STOP_HI14Q BIT(6)
+#define BIT_STOP_HI13Q BIT(5)
+#define BIT_STOP_HI12Q BIT(4)
+#define BIT_STOP_HI11Q BIT(3)
+#define BIT_STOP_HI10Q BIT(2)
+#define BIT_STOP_HI9Q BIT(1)
+#define BIT_STOP_HI8Q BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HI4Q_TXBD_DESA_L (Offset 0x13C8) */
+
+#define BIT_SHIFT_HI4Q_TXBD_DESA_L 0
+#define BIT_MASK_HI4Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI4Q_TXBD_DESA_L(x) \
+ (((x) & BIT_MASK_HI4Q_TXBD_DESA_L) << BIT_SHIFT_HI4Q_TXBD_DESA_L)
+#define BITS_HI4Q_TXBD_DESA_L \
+ (BIT_MASK_HI4Q_TXBD_DESA_L << BIT_SHIFT_HI4Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI4Q_TXBD_DESA_L(x) ((x) & (~BITS_HI4Q_TXBD_DESA_L))
+#define BIT_GET_HI4Q_TXBD_DESA_L(x) \
+ (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_L) & BIT_MASK_HI4Q_TXBD_DESA_L)
+#define BIT_SET_HI4Q_TXBD_DESA_L(x, v) \
+ (BIT_CLEAR_HI4Q_TXBD_DESA_L(x) | BIT_HI4Q_TXBD_DESA_L(v))
+
+/* 2 REG_HI4Q_TXBD_DESA_H (Offset 0x13CC) */
+
+#define BIT_SHIFT_HI4Q_TXBD_DESA_H 0
+#define BIT_MASK_HI4Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI4Q_TXBD_DESA_H(x) \
+ (((x) & BIT_MASK_HI4Q_TXBD_DESA_H) << BIT_SHIFT_HI4Q_TXBD_DESA_H)
+#define BITS_HI4Q_TXBD_DESA_H \
+ (BIT_MASK_HI4Q_TXBD_DESA_H << BIT_SHIFT_HI4Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI4Q_TXBD_DESA_H(x) ((x) & (~BITS_HI4Q_TXBD_DESA_H))
+#define BIT_GET_HI4Q_TXBD_DESA_H(x) \
+ (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_H) & BIT_MASK_HI4Q_TXBD_DESA_H)
+#define BIT_SET_HI4Q_TXBD_DESA_H(x, v) \
+ (BIT_CLEAR_HI4Q_TXBD_DESA_H(x) | BIT_HI4Q_TXBD_DESA_H(v))
+
+/* 2 REG_HI5Q_TXBD_DESA_L (Offset 0x13D0) */
+
+#define BIT_SHIFT_HI5Q_TXBD_DESA_L 0
+#define BIT_MASK_HI5Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI5Q_TXBD_DESA_L(x) \
+ (((x) & BIT_MASK_HI5Q_TXBD_DESA_L) << BIT_SHIFT_HI5Q_TXBD_DESA_L)
+#define BITS_HI5Q_TXBD_DESA_L \
+ (BIT_MASK_HI5Q_TXBD_DESA_L << BIT_SHIFT_HI5Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI5Q_TXBD_DESA_L(x) ((x) & (~BITS_HI5Q_TXBD_DESA_L))
+#define BIT_GET_HI5Q_TXBD_DESA_L(x) \
+ (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_L) & BIT_MASK_HI5Q_TXBD_DESA_L)
+#define BIT_SET_HI5Q_TXBD_DESA_L(x, v) \
+ (BIT_CLEAR_HI5Q_TXBD_DESA_L(x) | BIT_HI5Q_TXBD_DESA_L(v))
+
+/* 2 REG_HI5Q_TXBD_DESA_H (Offset 0x13D4) */
+
+#define BIT_SHIFT_HI5Q_TXBD_DESA_H 0
+#define BIT_MASK_HI5Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI5Q_TXBD_DESA_H(x) \
+ (((x) & BIT_MASK_HI5Q_TXBD_DESA_H) << BIT_SHIFT_HI5Q_TXBD_DESA_H)
+#define BITS_HI5Q_TXBD_DESA_H \
+ (BIT_MASK_HI5Q_TXBD_DESA_H << BIT_SHIFT_HI5Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI5Q_TXBD_DESA_H(x) ((x) & (~BITS_HI5Q_TXBD_DESA_H))
+#define BIT_GET_HI5Q_TXBD_DESA_H(x) \
+ (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_H) & BIT_MASK_HI5Q_TXBD_DESA_H)
+#define BIT_SET_HI5Q_TXBD_DESA_H(x, v) \
+ (BIT_CLEAR_HI5Q_TXBD_DESA_H(x) | BIT_HI5Q_TXBD_DESA_H(v))
+
+/* 2 REG_HI6Q_TXBD_DESA_L (Offset 0x13D8) */
+
+#define BIT_SHIFT_HI6Q_TXBD_DESA_L 0
+#define BIT_MASK_HI6Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI6Q_TXBD_DESA_L(x) \
+ (((x) & BIT_MASK_HI6Q_TXBD_DESA_L) << BIT_SHIFT_HI6Q_TXBD_DESA_L)
+#define BITS_HI6Q_TXBD_DESA_L \
+ (BIT_MASK_HI6Q_TXBD_DESA_L << BIT_SHIFT_HI6Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI6Q_TXBD_DESA_L(x) ((x) & (~BITS_HI6Q_TXBD_DESA_L))
+#define BIT_GET_HI6Q_TXBD_DESA_L(x) \
+ (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_L) & BIT_MASK_HI6Q_TXBD_DESA_L)
+#define BIT_SET_HI6Q_TXBD_DESA_L(x, v) \
+ (BIT_CLEAR_HI6Q_TXBD_DESA_L(x) | BIT_HI6Q_TXBD_DESA_L(v))
+
+/* 2 REG_HI6Q_TXBD_DESA_H (Offset 0x13DC) */
+
+#define BIT_SHIFT_HI6Q_TXBD_DESA_H 0
+#define BIT_MASK_HI6Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI6Q_TXBD_DESA_H(x) \
+ (((x) & BIT_MASK_HI6Q_TXBD_DESA_H) << BIT_SHIFT_HI6Q_TXBD_DESA_H)
+#define BITS_HI6Q_TXBD_DESA_H \
+ (BIT_MASK_HI6Q_TXBD_DESA_H << BIT_SHIFT_HI6Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI6Q_TXBD_DESA_H(x) ((x) & (~BITS_HI6Q_TXBD_DESA_H))
+#define BIT_GET_HI6Q_TXBD_DESA_H(x) \
+ (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_H) & BIT_MASK_HI6Q_TXBD_DESA_H)
+#define BIT_SET_HI6Q_TXBD_DESA_H(x, v) \
+ (BIT_CLEAR_HI6Q_TXBD_DESA_H(x) | BIT_HI6Q_TXBD_DESA_H(v))
+
+/* 2 REG_HI7Q_TXBD_DESA_L (Offset 0x13E0) */
+
+#define BIT_SHIFT_HI7Q_TXBD_DESA_L 0
+#define BIT_MASK_HI7Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI7Q_TXBD_DESA_L(x) \
+ (((x) & BIT_MASK_HI7Q_TXBD_DESA_L) << BIT_SHIFT_HI7Q_TXBD_DESA_L)
+#define BITS_HI7Q_TXBD_DESA_L \
+ (BIT_MASK_HI7Q_TXBD_DESA_L << BIT_SHIFT_HI7Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI7Q_TXBD_DESA_L(x) ((x) & (~BITS_HI7Q_TXBD_DESA_L))
+#define BIT_GET_HI7Q_TXBD_DESA_L(x) \
+ (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_L) & BIT_MASK_HI7Q_TXBD_DESA_L)
+#define BIT_SET_HI7Q_TXBD_DESA_L(x, v) \
+ (BIT_CLEAR_HI7Q_TXBD_DESA_L(x) | BIT_HI7Q_TXBD_DESA_L(v))
+
+/* 2 REG_HI7Q_TXBD_DESA_H (Offset 0x13E4) */
+
+#define BIT_SHIFT_HI7Q_TXBD_DESA_H 0
+#define BIT_MASK_HI7Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI7Q_TXBD_DESA_H(x) \
+ (((x) & BIT_MASK_HI7Q_TXBD_DESA_H) << BIT_SHIFT_HI7Q_TXBD_DESA_H)
+#define BITS_HI7Q_TXBD_DESA_H \
+ (BIT_MASK_HI7Q_TXBD_DESA_H << BIT_SHIFT_HI7Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI7Q_TXBD_DESA_H(x) ((x) & (~BITS_HI7Q_TXBD_DESA_H))
+#define BIT_GET_HI7Q_TXBD_DESA_H(x) \
+ (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_H) & BIT_MASK_HI7Q_TXBD_DESA_H)
+#define BIT_SET_HI7Q_TXBD_DESA_H(x, v) \
+ (BIT_CLEAR_HI7Q_TXBD_DESA_H(x) | BIT_HI7Q_TXBD_DESA_H(v))
+
+/* 2 REG_ACH8_ACH9_TXBD_NUM (Offset 0x13E8) */
+
+#define BIT_PCIE_ACH9_FLAG BIT(30)
+
+#define BIT_SHIFT_ACH9_DESC_MODE 28
+#define BIT_MASK_ACH9_DESC_MODE 0x3
+#define BIT_ACH9_DESC_MODE(x) \
+ (((x) & BIT_MASK_ACH9_DESC_MODE) << BIT_SHIFT_ACH9_DESC_MODE)
+#define BITS_ACH9_DESC_MODE \
+ (BIT_MASK_ACH9_DESC_MODE << BIT_SHIFT_ACH9_DESC_MODE)
+#define BIT_CLEAR_ACH9_DESC_MODE(x) ((x) & (~BITS_ACH9_DESC_MODE))
+#define BIT_GET_ACH9_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_ACH9_DESC_MODE) & BIT_MASK_ACH9_DESC_MODE)
+#define BIT_SET_ACH9_DESC_MODE(x, v) \
+ (BIT_CLEAR_ACH9_DESC_MODE(x) | BIT_ACH9_DESC_MODE(v))
+
+#define BIT_SHIFT_ACH9_DESC_NUM 16
+#define BIT_MASK_ACH9_DESC_NUM 0xfff
+#define BIT_ACH9_DESC_NUM(x) \
+ (((x) & BIT_MASK_ACH9_DESC_NUM) << BIT_SHIFT_ACH9_DESC_NUM)
+#define BITS_ACH9_DESC_NUM (BIT_MASK_ACH9_DESC_NUM << BIT_SHIFT_ACH9_DESC_NUM)
+#define BIT_CLEAR_ACH9_DESC_NUM(x) ((x) & (~BITS_ACH9_DESC_NUM))
+#define BIT_GET_ACH9_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_ACH9_DESC_NUM) & BIT_MASK_ACH9_DESC_NUM)
+#define BIT_SET_ACH9_DESC_NUM(x, v) \
+ (BIT_CLEAR_ACH9_DESC_NUM(x) | BIT_ACH9_DESC_NUM(v))
+
+#define BIT_PCIE_ACH8_FLAG BIT(14)
+
+#define BIT_SHIFT_ACH8_DESC_MODE 12
+#define BIT_MASK_ACH8_DESC_MODE 0x3
+#define BIT_ACH8_DESC_MODE(x) \
+ (((x) & BIT_MASK_ACH8_DESC_MODE) << BIT_SHIFT_ACH8_DESC_MODE)
+#define BITS_ACH8_DESC_MODE \
+ (BIT_MASK_ACH8_DESC_MODE << BIT_SHIFT_ACH8_DESC_MODE)
+#define BIT_CLEAR_ACH8_DESC_MODE(x) ((x) & (~BITS_ACH8_DESC_MODE))
+#define BIT_GET_ACH8_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_ACH8_DESC_MODE) & BIT_MASK_ACH8_DESC_MODE)
+#define BIT_SET_ACH8_DESC_MODE(x, v) \
+ (BIT_CLEAR_ACH8_DESC_MODE(x) | BIT_ACH8_DESC_MODE(v))
+
+#define BIT_SHIFT_ACH8_DESC_NUM 0
+#define BIT_MASK_ACH8_DESC_NUM 0xfff
+#define BIT_ACH8_DESC_NUM(x) \
+ (((x) & BIT_MASK_ACH8_DESC_NUM) << BIT_SHIFT_ACH8_DESC_NUM)
+#define BITS_ACH8_DESC_NUM (BIT_MASK_ACH8_DESC_NUM << BIT_SHIFT_ACH8_DESC_NUM)
+#define BIT_CLEAR_ACH8_DESC_NUM(x) ((x) & (~BITS_ACH8_DESC_NUM))
+#define BIT_GET_ACH8_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_ACH8_DESC_NUM) & BIT_MASK_ACH8_DESC_NUM)
+#define BIT_SET_ACH8_DESC_NUM(x, v) \
+ (BIT_CLEAR_ACH8_DESC_NUM(x) | BIT_ACH8_DESC_NUM(v))
+
+/* 2 REG_ACH10_ACH11_TXBD_NUM (Offset 0x13EC) */
+
+#define BIT_PCIE_ACH11_FLAG BIT(30)
+
+#define BIT_SHIFT_ACH11_DESC_MODE 28
+#define BIT_MASK_ACH11_DESC_MODE 0x3
+#define BIT_ACH11_DESC_MODE(x) \
+ (((x) & BIT_MASK_ACH11_DESC_MODE) << BIT_SHIFT_ACH11_DESC_MODE)
+#define BITS_ACH11_DESC_MODE \
+ (BIT_MASK_ACH11_DESC_MODE << BIT_SHIFT_ACH11_DESC_MODE)
+#define BIT_CLEAR_ACH11_DESC_MODE(x) ((x) & (~BITS_ACH11_DESC_MODE))
+#define BIT_GET_ACH11_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_ACH11_DESC_MODE) & BIT_MASK_ACH11_DESC_MODE)
+#define BIT_SET_ACH11_DESC_MODE(x, v) \
+ (BIT_CLEAR_ACH11_DESC_MODE(x) | BIT_ACH11_DESC_MODE(v))
+
+#define BIT_SHIFT_ACH11_DESC_NUM 16
+#define BIT_MASK_ACH11_DESC_NUM 0xfff
+#define BIT_ACH11_DESC_NUM(x) \
+ (((x) & BIT_MASK_ACH11_DESC_NUM) << BIT_SHIFT_ACH11_DESC_NUM)
+#define BITS_ACH11_DESC_NUM \
+ (BIT_MASK_ACH11_DESC_NUM << BIT_SHIFT_ACH11_DESC_NUM)
+#define BIT_CLEAR_ACH11_DESC_NUM(x) ((x) & (~BITS_ACH11_DESC_NUM))
+#define BIT_GET_ACH11_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_ACH11_DESC_NUM) & BIT_MASK_ACH11_DESC_NUM)
+#define BIT_SET_ACH11_DESC_NUM(x, v) \
+ (BIT_CLEAR_ACH11_DESC_NUM(x) | BIT_ACH11_DESC_NUM(v))
+
+#define BIT_PCIE_ACH10_FLAG BIT(14)
+
+#define BIT_SHIFT_ACH10_DESC_MODE 12
+#define BIT_MASK_ACH10_DESC_MODE 0x3
+#define BIT_ACH10_DESC_MODE(x) \
+ (((x) & BIT_MASK_ACH10_DESC_MODE) << BIT_SHIFT_ACH10_DESC_MODE)
+#define BITS_ACH10_DESC_MODE \
+ (BIT_MASK_ACH10_DESC_MODE << BIT_SHIFT_ACH10_DESC_MODE)
+#define BIT_CLEAR_ACH10_DESC_MODE(x) ((x) & (~BITS_ACH10_DESC_MODE))
+#define BIT_GET_ACH10_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_ACH10_DESC_MODE) & BIT_MASK_ACH10_DESC_MODE)
+#define BIT_SET_ACH10_DESC_MODE(x, v) \
+ (BIT_CLEAR_ACH10_DESC_MODE(x) | BIT_ACH10_DESC_MODE(v))
+
+#define BIT_SHIFT_ACH10_DESC_NUM 0
+#define BIT_MASK_ACH10_DESC_NUM 0xfff
+#define BIT_ACH10_DESC_NUM(x) \
+ (((x) & BIT_MASK_ACH10_DESC_NUM) << BIT_SHIFT_ACH10_DESC_NUM)
+#define BITS_ACH10_DESC_NUM \
+ (BIT_MASK_ACH10_DESC_NUM << BIT_SHIFT_ACH10_DESC_NUM)
+#define BIT_CLEAR_ACH10_DESC_NUM(x) ((x) & (~BITS_ACH10_DESC_NUM))
+#define BIT_GET_ACH10_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_ACH10_DESC_NUM) & BIT_MASK_ACH10_DESC_NUM)
+#define BIT_SET_ACH10_DESC_NUM(x, v) \
+ (BIT_CLEAR_ACH10_DESC_NUM(x) | BIT_ACH10_DESC_NUM(v))
+
+/* 2 REG_ACH12_ACH13_TXBD_NUM (Offset 0x13F0) */
+
+#define BIT_PCIE_ACH13_FLAG BIT(30)
+
+#define BIT_SHIFT_ACH13_DESC_MODE 28
+#define BIT_MASK_ACH13_DESC_MODE 0x3
+#define BIT_ACH13_DESC_MODE(x) \
+ (((x) & BIT_MASK_ACH13_DESC_MODE) << BIT_SHIFT_ACH13_DESC_MODE)
+#define BITS_ACH13_DESC_MODE \
+ (BIT_MASK_ACH13_DESC_MODE << BIT_SHIFT_ACH13_DESC_MODE)
+#define BIT_CLEAR_ACH13_DESC_MODE(x) ((x) & (~BITS_ACH13_DESC_MODE))
+#define BIT_GET_ACH13_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_ACH13_DESC_MODE) & BIT_MASK_ACH13_DESC_MODE)
+#define BIT_SET_ACH13_DESC_MODE(x, v) \
+ (BIT_CLEAR_ACH13_DESC_MODE(x) | BIT_ACH13_DESC_MODE(v))
+
+#define BIT_SHIFT_ACH13_DESC_NUM 16
+#define BIT_MASK_ACH13_DESC_NUM 0xfff
+#define BIT_ACH13_DESC_NUM(x) \
+ (((x) & BIT_MASK_ACH13_DESC_NUM) << BIT_SHIFT_ACH13_DESC_NUM)
+#define BITS_ACH13_DESC_NUM \
+ (BIT_MASK_ACH13_DESC_NUM << BIT_SHIFT_ACH13_DESC_NUM)
+#define BIT_CLEAR_ACH13_DESC_NUM(x) ((x) & (~BITS_ACH13_DESC_NUM))
+#define BIT_GET_ACH13_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_ACH13_DESC_NUM) & BIT_MASK_ACH13_DESC_NUM)
+#define BIT_SET_ACH13_DESC_NUM(x, v) \
+ (BIT_CLEAR_ACH13_DESC_NUM(x) | BIT_ACH13_DESC_NUM(v))
+
+#define BIT_PCIE_ACH12_FLAG BIT(14)
+
+#define BIT_SHIFT_ACH12_DESC_MODE 12
+#define BIT_MASK_ACH12_DESC_MODE 0x3
+#define BIT_ACH12_DESC_MODE(x) \
+ (((x) & BIT_MASK_ACH12_DESC_MODE) << BIT_SHIFT_ACH12_DESC_MODE)
+#define BITS_ACH12_DESC_MODE \
+ (BIT_MASK_ACH12_DESC_MODE << BIT_SHIFT_ACH12_DESC_MODE)
+#define BIT_CLEAR_ACH12_DESC_MODE(x) ((x) & (~BITS_ACH12_DESC_MODE))
+#define BIT_GET_ACH12_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_ACH12_DESC_MODE) & BIT_MASK_ACH12_DESC_MODE)
+#define BIT_SET_ACH12_DESC_MODE(x, v) \
+ (BIT_CLEAR_ACH12_DESC_MODE(x) | BIT_ACH12_DESC_MODE(v))
+
+#define BIT_SHIFT_ACH12_DESC_NUM 0
+#define BIT_MASK_ACH12_DESC_NUM 0xfff
+#define BIT_ACH12_DESC_NUM(x) \
+ (((x) & BIT_MASK_ACH12_DESC_NUM) << BIT_SHIFT_ACH12_DESC_NUM)
+#define BITS_ACH12_DESC_NUM \
+ (BIT_MASK_ACH12_DESC_NUM << BIT_SHIFT_ACH12_DESC_NUM)
+#define BIT_CLEAR_ACH12_DESC_NUM(x) ((x) & (~BITS_ACH12_DESC_NUM))
+#define BIT_GET_ACH12_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_ACH12_DESC_NUM) & BIT_MASK_ACH12_DESC_NUM)
+#define BIT_SET_ACH12_DESC_NUM(x, v) \
+ (BIT_CLEAR_ACH12_DESC_NUM(x) | BIT_ACH12_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_OLD_DEHANG (Offset 0x13F4) */
+
+#define BIT_OLD_DEHANG BIT(1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_ACH4_TXBD_DESA_L (Offset 0x13F8) */
+
+#define BIT_SHIFT_ACH4_TXBD_DESA_L 0
+#define BIT_MASK_ACH4_TXBD_DESA_L 0xffffffffL
+#define BIT_ACH4_TXBD_DESA_L(x) \
+ (((x) & BIT_MASK_ACH4_TXBD_DESA_L) << BIT_SHIFT_ACH4_TXBD_DESA_L)
+#define BITS_ACH4_TXBD_DESA_L \
+ (BIT_MASK_ACH4_TXBD_DESA_L << BIT_SHIFT_ACH4_TXBD_DESA_L)
+#define BIT_CLEAR_ACH4_TXBD_DESA_L(x) ((x) & (~BITS_ACH4_TXBD_DESA_L))
+#define BIT_GET_ACH4_TXBD_DESA_L(x) \
+ (((x) >> BIT_SHIFT_ACH4_TXBD_DESA_L) & BIT_MASK_ACH4_TXBD_DESA_L)
+#define BIT_SET_ACH4_TXBD_DESA_L(x, v) \
+ (BIT_CLEAR_ACH4_TXBD_DESA_L(x) | BIT_ACH4_TXBD_DESA_L(v))
+
+/* 2 REG_ACH4_TXBD_DESA_H (Offset 0x13FC) */
+
+#define BIT_SHIFT_ACH4_TXBD_DESA_H 0
+#define BIT_MASK_ACH4_TXBD_DESA_H 0xffffffffL
+#define BIT_ACH4_TXBD_DESA_H(x) \
+ (((x) & BIT_MASK_ACH4_TXBD_DESA_H) << BIT_SHIFT_ACH4_TXBD_DESA_H)
+#define BITS_ACH4_TXBD_DESA_H \
+ (BIT_MASK_ACH4_TXBD_DESA_H << BIT_SHIFT_ACH4_TXBD_DESA_H)
+#define BIT_CLEAR_ACH4_TXBD_DESA_H(x) ((x) & (~BITS_ACH4_TXBD_DESA_H))
+#define BIT_GET_ACH4_TXBD_DESA_H(x) \
+ (((x) >> BIT_SHIFT_ACH4_TXBD_DESA_H) & BIT_MASK_ACH4_TXBD_DESA_H)
+#define BIT_SET_ACH4_TXBD_DESA_H(x, v) \
+ (BIT_CLEAR_ACH4_TXBD_DESA_H(x) | BIT_ACH4_TXBD_DESA_H(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_Q0_Q1_INFO (Offset 0x1400) */
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#define BIT_SHIFT_AC1_PKT_INFO 16
+#define BIT_MASK_AC1_PKT_INFO 0xfff
+#define BIT_AC1_PKT_INFO(x) \
+ (((x) & BIT_MASK_AC1_PKT_INFO) << BIT_SHIFT_AC1_PKT_INFO)
+#define BITS_AC1_PKT_INFO (BIT_MASK_AC1_PKT_INFO << BIT_SHIFT_AC1_PKT_INFO)
+#define BIT_CLEAR_AC1_PKT_INFO(x) ((x) & (~BITS_AC1_PKT_INFO))
+#define BIT_GET_AC1_PKT_INFO(x) \
+ (((x) >> BIT_SHIFT_AC1_PKT_INFO) & BIT_MASK_AC1_PKT_INFO)
+#define BIT_SET_AC1_PKT_INFO(x, v) \
+ (BIT_CLEAR_AC1_PKT_INFO(x) | BIT_AC1_PKT_INFO(v))
+#endif
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_FS_CLI0_EOSP_INT BIT(16)
+/* 2 REG_MU_OFFSET (Offset 0x1400) */
+
+#define BIT_SHIFT_MU_RATETABLE_OFFSET 16
+#define BIT_MASK_MU_RATETABLE_OFFSET 0x1ff
+#define BIT_MU_RATETABLE_OFFSET(x) \
+ (((x) & BIT_MASK_MU_RATETABLE_OFFSET) << BIT_SHIFT_MU_RATETABLE_OFFSET)
+#define BITS_MU_RATETABLE_OFFSET \
+ (BIT_MASK_MU_RATETABLE_OFFSET << BIT_SHIFT_MU_RATETABLE_OFFSET)
+#define BIT_CLEAR_MU_RATETABLE_OFFSET(x) ((x) & (~BITS_MU_RATETABLE_OFFSET))
+#define BIT_GET_MU_RATETABLE_OFFSET(x) \
+ (((x) >> BIT_SHIFT_MU_RATETABLE_OFFSET) & BIT_MASK_MU_RATETABLE_OFFSET)
+#define BIT_SET_MU_RATETABLE_OFFSET(x, v) \
+ (BIT_CLEAR_MU_RATETABLE_OFFSET(x) | BIT_MU_RATETABLE_OFFSET(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_Q0_Q1_INFO (Offset 0x1400) */
+#define BIT_SHIFT_AC0_PKT_INFO 0
+#define BIT_MASK_AC0_PKT_INFO 0xfff
+#define BIT_AC0_PKT_INFO(x) \
+ (((x) & BIT_MASK_AC0_PKT_INFO) << BIT_SHIFT_AC0_PKT_INFO)
+#define BITS_AC0_PKT_INFO (BIT_MASK_AC0_PKT_INFO << BIT_SHIFT_AC0_PKT_INFO)
+#define BIT_CLEAR_AC0_PKT_INFO(x) ((x) & (~BITS_AC0_PKT_INFO))
+#define BIT_GET_AC0_PKT_INFO(x) \
+ (((x) >> BIT_SHIFT_AC0_PKT_INFO) & BIT_MASK_AC0_PKT_INFO)
+#define BIT_SET_AC0_PKT_INFO(x, v) \
+ (BIT_CLEAR_AC0_PKT_INFO(x) | BIT_AC0_PKT_INFO(v))
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+#endif
-#define BIT_NOA2_TSFT_BIT32_TOGGLE_INT BIT(9)
+#if (HALMAC_8198F_SUPPORT)
-#endif
+/* 2 REG_ARFR6 (Offset 0x1400) */
+#define BIT_SHIFT_ARFR6_V1 0
+#define BIT_MASK_ARFR6_V1 0xffffffffffffffffL
+#define BIT_ARFR6_V1(x) (((x) & BIT_MASK_ARFR6_V1) << BIT_SHIFT_ARFR6_V1)
+#define BITS_ARFR6_V1 (BIT_MASK_ARFR6_V1 << BIT_SHIFT_ARFR6_V1)
+#define BIT_CLEAR_ARFR6_V1(x) ((x) & (~BITS_ARFR6_V1))
+#define BIT_GET_ARFR6_V1(x) (((x) >> BIT_SHIFT_ARFR6_V1) & BIT_MASK_ARFR6_V1)
+#define BIT_SET_ARFR6_V1(x, v) (BIT_CLEAR_ARFR6_V1(x) | BIT_ARFR6_V1(v))
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+/* 2 REG_MU_OFFSET (Offset 0x1400) */
-#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_INT BIT(9)
+#define BIT_SHIFT_MU_SCORETABLE_OFFSET 0
+#define BIT_MASK_MU_SCORETABLE_OFFSET 0x1ff
+#define BIT_MU_SCORETABLE_OFFSET(x) \
+ (((x) & BIT_MASK_MU_SCORETABLE_OFFSET) \
+ << BIT_SHIFT_MU_SCORETABLE_OFFSET)
+#define BITS_MU_SCORETABLE_OFFSET \
+ (BIT_MASK_MU_SCORETABLE_OFFSET << BIT_SHIFT_MU_SCORETABLE_OFFSET)
+#define BIT_CLEAR_MU_SCORETABLE_OFFSET(x) ((x) & (~BITS_MU_SCORETABLE_OFFSET))
+#define BIT_GET_MU_SCORETABLE_OFFSET(x) \
+ (((x) >> BIT_SHIFT_MU_SCORETABLE_OFFSET) & \
+ BIT_MASK_MU_SCORETABLE_OFFSET)
+#define BIT_SET_MU_SCORETABLE_OFFSET(x, v) \
+ (BIT_CLEAR_MU_SCORETABLE_OFFSET(x) | BIT_MU_SCORETABLE_OFFSET(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
+/* 2 REG_Q2_Q3_INFO (Offset 0x1404) */
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+#define BIT_SHIFT_AC3_PKT_INFO 16
+#define BIT_MASK_AC3_PKT_INFO 0xfff
+#define BIT_AC3_PKT_INFO(x) \
+ (((x) & BIT_MASK_AC3_PKT_INFO) << BIT_SHIFT_AC3_PKT_INFO)
+#define BITS_AC3_PKT_INFO (BIT_MASK_AC3_PKT_INFO << BIT_SHIFT_AC3_PKT_INFO)
+#define BIT_CLEAR_AC3_PKT_INFO(x) ((x) & (~BITS_AC3_PKT_INFO))
+#define BIT_GET_AC3_PKT_INFO(x) \
+ (((x) >> BIT_SHIFT_AC3_PKT_INFO) & BIT_MASK_AC3_PKT_INFO)
+#define BIT_SET_AC3_PKT_INFO(x, v) \
+ (BIT_CLEAR_AC3_PKT_INFO(x) | BIT_AC3_PKT_INFO(v))
+
+#define BIT_SHIFT_AC2_PKT_INFO 0
+#define BIT_MASK_AC2_PKT_INFO 0xfff
+#define BIT_AC2_PKT_INFO(x) \
+ (((x) & BIT_MASK_AC2_PKT_INFO) << BIT_SHIFT_AC2_PKT_INFO)
+#define BITS_AC2_PKT_INFO (BIT_MASK_AC2_PKT_INFO << BIT_SHIFT_AC2_PKT_INFO)
+#define BIT_CLEAR_AC2_PKT_INFO(x) ((x) & (~BITS_AC2_PKT_INFO))
+#define BIT_GET_AC2_PKT_INFO(x) \
+ (((x) >> BIT_SHIFT_AC2_PKT_INFO) & BIT_MASK_AC2_PKT_INFO)
+#define BIT_SET_AC2_PKT_INFO(x, v) \
+ (BIT_CLEAR_AC2_PKT_INFO(x) | BIT_AC2_PKT_INFO(v))
-#define BIT_NOA1_TSFT_BIT32_TOGGLE_INT BIT(8)
+/* 2 REG_Q4_Q5_INFO (Offset 0x1408) */
-#endif
+#define BIT_SHIFT_AC5_PKT_INFO 16
+#define BIT_MASK_AC5_PKT_INFO 0xfff
+#define BIT_AC5_PKT_INFO(x) \
+ (((x) & BIT_MASK_AC5_PKT_INFO) << BIT_SHIFT_AC5_PKT_INFO)
+#define BITS_AC5_PKT_INFO (BIT_MASK_AC5_PKT_INFO << BIT_SHIFT_AC5_PKT_INFO)
+#define BIT_CLEAR_AC5_PKT_INFO(x) ((x) & (~BITS_AC5_PKT_INFO))
+#define BIT_GET_AC5_PKT_INFO(x) \
+ (((x) >> BIT_SHIFT_AC5_PKT_INFO) & BIT_MASK_AC5_PKT_INFO)
+#define BIT_SET_AC5_PKT_INFO(x, v) \
+ (BIT_CLEAR_AC5_PKT_INFO(x) | BIT_AC5_PKT_INFO(v))
+#define BIT_SHIFT_AC4_PKT_INFO 0
+#define BIT_MASK_AC4_PKT_INFO 0xfff
+#define BIT_AC4_PKT_INFO(x) \
+ (((x) & BIT_MASK_AC4_PKT_INFO) << BIT_SHIFT_AC4_PKT_INFO)
+#define BITS_AC4_PKT_INFO (BIT_MASK_AC4_PKT_INFO << BIT_SHIFT_AC4_PKT_INFO)
+#define BIT_CLEAR_AC4_PKT_INFO(x) ((x) & (~BITS_AC4_PKT_INFO))
+#define BIT_GET_AC4_PKT_INFO(x) \
+ (((x) >> BIT_SHIFT_AC4_PKT_INFO) & BIT_MASK_AC4_PKT_INFO)
+#define BIT_SET_AC4_PKT_INFO(x, v) \
+ (BIT_CLEAR_AC4_PKT_INFO(x) | BIT_AC4_PKT_INFO(v))
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8198F_SUPPORT)
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+/* 2 REG_ARFR7 (Offset 0x1408) */
-#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_INT BIT(8)
+#define BIT_SHIFT_ARFR7_V1 0
+#define BIT_MASK_ARFR7_V1 0xffffffffffffffffL
+#define BIT_ARFR7_V1(x) (((x) & BIT_MASK_ARFR7_V1) << BIT_SHIFT_ARFR7_V1)
+#define BITS_ARFR7_V1 (BIT_MASK_ARFR7_V1 << BIT_SHIFT_ARFR7_V1)
+#define BIT_CLEAR_ARFR7_V1(x) ((x) & (~BITS_ARFR7_V1))
+#define BIT_GET_ARFR7_V1(x) (((x) >> BIT_SHIFT_ARFR7_V1) & BIT_MASK_ARFR7_V1)
+#define BIT_SET_ARFR7_V1(x, v) (BIT_CLEAR_ARFR7_V1(x) | BIT_ARFR7_V1(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_Q6_Q7_INFO (Offset 0x140C) */
+#define BIT_SHIFT_AC7_PKT_INFO 16
+#define BIT_MASK_AC7_PKT_INFO 0xfff
+#define BIT_AC7_PKT_INFO(x) \
+ (((x) & BIT_MASK_AC7_PKT_INFO) << BIT_SHIFT_AC7_PKT_INFO)
+#define BITS_AC7_PKT_INFO (BIT_MASK_AC7_PKT_INFO << BIT_SHIFT_AC7_PKT_INFO)
+#define BIT_CLEAR_AC7_PKT_INFO(x) ((x) & (~BITS_AC7_PKT_INFO))
+#define BIT_GET_AC7_PKT_INFO(x) \
+ (((x) >> BIT_SHIFT_AC7_PKT_INFO) & BIT_MASK_AC7_PKT_INFO)
+#define BIT_SET_AC7_PKT_INFO(x, v) \
+ (BIT_CLEAR_AC7_PKT_INFO(x) | BIT_AC7_PKT_INFO(v))
+
+#define BIT_SHIFT_AC6_PKT_INFO 0
+#define BIT_MASK_AC6_PKT_INFO 0xfff
+#define BIT_AC6_PKT_INFO(x) \
+ (((x) & BIT_MASK_AC6_PKT_INFO) << BIT_SHIFT_AC6_PKT_INFO)
+#define BITS_AC6_PKT_INFO (BIT_MASK_AC6_PKT_INFO << BIT_SHIFT_AC6_PKT_INFO)
+#define BIT_CLEAR_AC6_PKT_INFO(x) ((x) & (~BITS_AC6_PKT_INFO))
+#define BIT_GET_AC6_PKT_INFO(x) \
+ (((x) >> BIT_SHIFT_AC6_PKT_INFO) & BIT_MASK_AC6_PKT_INFO)
+#define BIT_SET_AC6_PKT_INFO(x, v) \
+ (BIT_CLEAR_AC6_PKT_INFO(x) | BIT_AC6_PKT_INFO(v))
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+/* 2 REG_MGQ_HIQ_INFO (Offset 0x1410) */
-#define BIT_PORT4_TX_NULL1_DONE_INT BIT(7)
+#define BIT_SHIFT_HIQ_PKT_INFO 16
+#define BIT_MASK_HIQ_PKT_INFO 0xfff
+#define BIT_HIQ_PKT_INFO(x) \
+ (((x) & BIT_MASK_HIQ_PKT_INFO) << BIT_SHIFT_HIQ_PKT_INFO)
+#define BITS_HIQ_PKT_INFO (BIT_MASK_HIQ_PKT_INFO << BIT_SHIFT_HIQ_PKT_INFO)
+#define BIT_CLEAR_HIQ_PKT_INFO(x) ((x) & (~BITS_HIQ_PKT_INFO))
+#define BIT_GET_HIQ_PKT_INFO(x) \
+ (((x) >> BIT_SHIFT_HIQ_PKT_INFO) & BIT_MASK_HIQ_PKT_INFO)
+#define BIT_SET_HIQ_PKT_INFO(x, v) \
+ (BIT_CLEAR_HIQ_PKT_INFO(x) | BIT_HIQ_PKT_INFO(v))
+
+#define BIT_SHIFT_MGQ_PKT_INFO 0
+#define BIT_MASK_MGQ_PKT_INFO 0xfff
+#define BIT_MGQ_PKT_INFO(x) \
+ (((x) & BIT_MASK_MGQ_PKT_INFO) << BIT_SHIFT_MGQ_PKT_INFO)
+#define BITS_MGQ_PKT_INFO (BIT_MASK_MGQ_PKT_INFO << BIT_SHIFT_MGQ_PKT_INFO)
+#define BIT_CLEAR_MGQ_PKT_INFO(x) ((x) & (~BITS_MGQ_PKT_INFO))
+#define BIT_GET_MGQ_PKT_INFO(x) \
+ (((x) >> BIT_SHIFT_MGQ_PKT_INFO) & BIT_MASK_MGQ_PKT_INFO)
+#define BIT_SET_MGQ_PKT_INFO(x, v) \
+ (BIT_CLEAR_MGQ_PKT_INFO(x) | BIT_MGQ_PKT_INFO(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/* 2 REG_ARFR8 (Offset 0x1410) */
+
+#define BIT_SHIFT_ARFR8_V1 0
+#define BIT_MASK_ARFR8_V1 0xffffffffffffffffL
+#define BIT_ARFR8_V1(x) (((x) & BIT_MASK_ARFR8_V1) << BIT_SHIFT_ARFR8_V1)
+#define BITS_ARFR8_V1 (BIT_MASK_ARFR8_V1 << BIT_SHIFT_ARFR8_V1)
+#define BIT_CLEAR_ARFR8_V1(x) ((x) & (~BITS_ARFR8_V1))
+#define BIT_GET_ARFR8_V1(x) (((x) >> BIT_SHIFT_ARFR8_V1) & BIT_MASK_ARFR8_V1)
+#define BIT_SET_ARFR8_V1(x, v) (BIT_CLEAR_ARFR8_V1(x) | BIT_ARFR8_V1(v))
+
+#define BIT_SHIFT_MEDIUM_HAS_IDLE_TRIGGER 0
+#define BIT_MASK_MEDIUM_HAS_IDLE_TRIGGER 0xff
+#define BIT_MEDIUM_HAS_IDLE_TRIGGER(x) \
+ (((x) & BIT_MASK_MEDIUM_HAS_IDLE_TRIGGER) \
+ << BIT_SHIFT_MEDIUM_HAS_IDLE_TRIGGER)
+#define BITS_MEDIUM_HAS_IDLE_TRIGGER \
+ (BIT_MASK_MEDIUM_HAS_IDLE_TRIGGER << BIT_SHIFT_MEDIUM_HAS_IDLE_TRIGGER)
+#define BIT_CLEAR_MEDIUM_HAS_IDLE_TRIGGER(x) \
+ ((x) & (~BITS_MEDIUM_HAS_IDLE_TRIGGER))
+#define BIT_GET_MEDIUM_HAS_IDLE_TRIGGER(x) \
+ (((x) >> BIT_SHIFT_MEDIUM_HAS_IDLE_TRIGGER) & \
+ BIT_MASK_MEDIUM_HAS_IDLE_TRIGGER)
+#define BIT_SET_MEDIUM_HAS_IDLE_TRIGGER(x, v) \
+ (BIT_CLEAR_MEDIUM_HAS_IDLE_TRIGGER(x) | BIT_MEDIUM_HAS_IDLE_TRIGGER(v))
#endif
+#if (HALMAC_8197F_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_CMDQ_BCNQ_INFO (Offset 0x1414) */
+#define BIT_SHIFT_BCNQ_PKT_INFO_V1 16
+#define BIT_MASK_BCNQ_PKT_INFO_V1 0xfff
+#define BIT_BCNQ_PKT_INFO_V1(x) \
+ (((x) & BIT_MASK_BCNQ_PKT_INFO_V1) << BIT_SHIFT_BCNQ_PKT_INFO_V1)
+#define BITS_BCNQ_PKT_INFO_V1 \
+ (BIT_MASK_BCNQ_PKT_INFO_V1 << BIT_SHIFT_BCNQ_PKT_INFO_V1)
+#define BIT_CLEAR_BCNQ_PKT_INFO_V1(x) ((x) & (~BITS_BCNQ_PKT_INFO_V1))
+#define BIT_GET_BCNQ_PKT_INFO_V1(x) \
+ (((x) >> BIT_SHIFT_BCNQ_PKT_INFO_V1) & BIT_MASK_BCNQ_PKT_INFO_V1)
+#define BIT_SET_BCNQ_PKT_INFO_V1(x, v) \
+ (BIT_CLEAR_BCNQ_PKT_INFO_V1(x) | BIT_BCNQ_PKT_INFO_V1(v))
+
+#define BIT_SHIFT_BCNERR_PORT_SEL 16
+#define BIT_MASK_BCNERR_PORT_SEL 0x7
+#define BIT_BCNERR_PORT_SEL(x) \
+ (((x) & BIT_MASK_BCNERR_PORT_SEL) << BIT_SHIFT_BCNERR_PORT_SEL)
+#define BITS_BCNERR_PORT_SEL \
+ (BIT_MASK_BCNERR_PORT_SEL << BIT_SHIFT_BCNERR_PORT_SEL)
+#define BIT_CLEAR_BCNERR_PORT_SEL(x) ((x) & (~BITS_BCNERR_PORT_SEL))
+#define BIT_GET_BCNERR_PORT_SEL(x) \
+ (((x) >> BIT_SHIFT_BCNERR_PORT_SEL) & BIT_MASK_BCNERR_PORT_SEL)
+#define BIT_SET_BCNERR_PORT_SEL(x, v) \
+ (BIT_CLEAR_BCNERR_PORT_SEL(x) | BIT_BCNERR_PORT_SEL(v))
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+/* 2 REG_CMDQ_BCNQ_INFO (Offset 0x1414) */
-#define BIT_FS_CLI3_TX_NULL1_INT BIT(7)
+#define BIT_SHIFT_CMDQ_PKT_INFO 16
+#define BIT_MASK_CMDQ_PKT_INFO 0xfff
+#define BIT_CMDQ_PKT_INFO(x) \
+ (((x) & BIT_MASK_CMDQ_PKT_INFO) << BIT_SHIFT_CMDQ_PKT_INFO)
+#define BITS_CMDQ_PKT_INFO (BIT_MASK_CMDQ_PKT_INFO << BIT_SHIFT_CMDQ_PKT_INFO)
+#define BIT_CLEAR_CMDQ_PKT_INFO(x) ((x) & (~BITS_CMDQ_PKT_INFO))
+#define BIT_GET_CMDQ_PKT_INFO(x) \
+ (((x) >> BIT_SHIFT_CMDQ_PKT_INFO) & BIT_MASK_CMDQ_PKT_INFO)
+#define BIT_SET_CMDQ_PKT_INFO(x, v) \
+ (BIT_CLEAR_CMDQ_PKT_INFO(x) | BIT_CMDQ_PKT_INFO(v))
#endif
-
#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_CMDQ_BCNQ_INFO (Offset 0x1414) */
-/* 2 REG_FT2ISR (Offset 0x11E4) */
-
-#define BIT_PORT4_TX_NULL0_DONE_INT BIT(6)
+#define BIT_SHIFT_CMDQ_PKT_INFO_V1 0
+#define BIT_MASK_CMDQ_PKT_INFO_V1 0xfff
+#define BIT_CMDQ_PKT_INFO_V1(x) \
+ (((x) & BIT_MASK_CMDQ_PKT_INFO_V1) << BIT_SHIFT_CMDQ_PKT_INFO_V1)
+#define BITS_CMDQ_PKT_INFO_V1 \
+ (BIT_MASK_CMDQ_PKT_INFO_V1 << BIT_SHIFT_CMDQ_PKT_INFO_V1)
+#define BIT_CLEAR_CMDQ_PKT_INFO_V1(x) ((x) & (~BITS_CMDQ_PKT_INFO_V1))
+#define BIT_GET_CMDQ_PKT_INFO_V1(x) \
+ (((x) >> BIT_SHIFT_CMDQ_PKT_INFO_V1) & BIT_MASK_CMDQ_PKT_INFO_V1)
+#define BIT_SET_CMDQ_PKT_INFO_V1(x, v) \
+ (BIT_CLEAR_CMDQ_PKT_INFO_V1(x) | BIT_CMDQ_PKT_INFO_V1(v))
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+/* 2 REG_CMDQ_BCNQ_INFO (Offset 0x1414) */
-#define BIT_FS_CLI3_TX_NULL0_INT BIT(6)
+#define BIT_SHIFT_BCNQ_PKT_INFO 0
+#define BIT_MASK_BCNQ_PKT_INFO 0xfff
+#define BIT_BCNQ_PKT_INFO(x) \
+ (((x) & BIT_MASK_BCNQ_PKT_INFO) << BIT_SHIFT_BCNQ_PKT_INFO)
+#define BITS_BCNQ_PKT_INFO (BIT_MASK_BCNQ_PKT_INFO << BIT_SHIFT_BCNQ_PKT_INFO)
+#define BIT_CLEAR_BCNQ_PKT_INFO(x) ((x) & (~BITS_BCNQ_PKT_INFO))
+#define BIT_GET_BCNQ_PKT_INFO(x) \
+ (((x) >> BIT_SHIFT_BCNQ_PKT_INFO) & BIT_MASK_BCNQ_PKT_INFO)
+#define BIT_SET_BCNQ_PKT_INFO(x, v) \
+ (BIT_CLEAR_BCNQ_PKT_INFO(x) | BIT_BCNQ_PKT_INFO(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_USEREG_SETTING (Offset 0x1420) */
+#define BIT_NDPA_USEREG BIT(21)
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+#define BIT_SHIFT_RETRY_USEREG 19
+#define BIT_MASK_RETRY_USEREG 0x3
+#define BIT_RETRY_USEREG(x) \
+ (((x) & BIT_MASK_RETRY_USEREG) << BIT_SHIFT_RETRY_USEREG)
+#define BITS_RETRY_USEREG (BIT_MASK_RETRY_USEREG << BIT_SHIFT_RETRY_USEREG)
+#define BIT_CLEAR_RETRY_USEREG(x) ((x) & (~BITS_RETRY_USEREG))
+#define BIT_GET_RETRY_USEREG(x) \
+ (((x) >> BIT_SHIFT_RETRY_USEREG) & BIT_MASK_RETRY_USEREG)
+#define BIT_SET_RETRY_USEREG(x, v) \
+ (BIT_CLEAR_RETRY_USEREG(x) | BIT_RETRY_USEREG(v))
+
+#define BIT_SHIFT_TRYPKT_USEREG 17
+#define BIT_MASK_TRYPKT_USEREG 0x3
+#define BIT_TRYPKT_USEREG(x) \
+ (((x) & BIT_MASK_TRYPKT_USEREG) << BIT_SHIFT_TRYPKT_USEREG)
+#define BITS_TRYPKT_USEREG (BIT_MASK_TRYPKT_USEREG << BIT_SHIFT_TRYPKT_USEREG)
+#define BIT_CLEAR_TRYPKT_USEREG(x) ((x) & (~BITS_TRYPKT_USEREG))
+#define BIT_GET_TRYPKT_USEREG(x) \
+ (((x) >> BIT_SHIFT_TRYPKT_USEREG) & BIT_MASK_TRYPKT_USEREG)
+#define BIT_SET_TRYPKT_USEREG(x, v) \
+ (BIT_CLEAR_TRYPKT_USEREG(x) | BIT_TRYPKT_USEREG(v))
-#define BIT_PORT3_TX_NULL1_DONE_INT BIT(5)
+#define BIT_CTLPKT_USEREG BIT(16)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_AESIV_SETTING (Offset 0x1424) */
+#define BIT_SHIFT_AESIV_OFFSET 0
+#define BIT_MASK_AESIV_OFFSET 0xfff
+#define BIT_AESIV_OFFSET(x) \
+ (((x) & BIT_MASK_AESIV_OFFSET) << BIT_SHIFT_AESIV_OFFSET)
+#define BITS_AESIV_OFFSET (BIT_MASK_AESIV_OFFSET << BIT_SHIFT_AESIV_OFFSET)
+#define BIT_CLEAR_AESIV_OFFSET(x) ((x) & (~BITS_AESIV_OFFSET))
+#define BIT_GET_AESIV_OFFSET(x) \
+ (((x) >> BIT_SHIFT_AESIV_OFFSET) & BIT_MASK_AESIV_OFFSET)
+#define BIT_SET_AESIV_OFFSET(x, v) \
+ (BIT_CLEAR_AESIV_OFFSET(x) | BIT_AESIV_OFFSET(v))
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+#endif
-#define BIT_FS_CLI2_TX_NULL1_INT BIT(5)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_BF0_TIME_SETTING (Offset 0x1428) */
+#define BIT_BF0_TIMER_SET BIT(31)
+#define BIT_BF0_TIMER_CLR BIT(30)
+#define BIT_BF0_UPDATE_EN BIT(29)
+#define BIT_BF0_TIMER_EN BIT(28)
+
+#define BIT_SHIFT_BF0_PRETIME_OVER 16
+#define BIT_MASK_BF0_PRETIME_OVER 0xfff
+#define BIT_BF0_PRETIME_OVER(x) \
+ (((x) & BIT_MASK_BF0_PRETIME_OVER) << BIT_SHIFT_BF0_PRETIME_OVER)
+#define BITS_BF0_PRETIME_OVER \
+ (BIT_MASK_BF0_PRETIME_OVER << BIT_SHIFT_BF0_PRETIME_OVER)
+#define BIT_CLEAR_BF0_PRETIME_OVER(x) ((x) & (~BITS_BF0_PRETIME_OVER))
+#define BIT_GET_BF0_PRETIME_OVER(x) \
+ (((x) >> BIT_SHIFT_BF0_PRETIME_OVER) & BIT_MASK_BF0_PRETIME_OVER)
+#define BIT_SET_BF0_PRETIME_OVER(x, v) \
+ (BIT_CLEAR_BF0_PRETIME_OVER(x) | BIT_BF0_PRETIME_OVER(v))
+
+#define BIT_SHIFT_BF0_LIFETIME 0
+#define BIT_MASK_BF0_LIFETIME 0xffff
+#define BIT_BF0_LIFETIME(x) \
+ (((x) & BIT_MASK_BF0_LIFETIME) << BIT_SHIFT_BF0_LIFETIME)
+#define BITS_BF0_LIFETIME (BIT_MASK_BF0_LIFETIME << BIT_SHIFT_BF0_LIFETIME)
+#define BIT_CLEAR_BF0_LIFETIME(x) ((x) & (~BITS_BF0_LIFETIME))
+#define BIT_GET_BF0_LIFETIME(x) \
+ (((x) >> BIT_SHIFT_BF0_LIFETIME) & BIT_MASK_BF0_LIFETIME)
+#define BIT_SET_BF0_LIFETIME(x, v) \
+ (BIT_CLEAR_BF0_LIFETIME(x) | BIT_BF0_LIFETIME(v))
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_BF1_TIME_SETTING (Offset 0x142C) */
+#define BIT_BF1_TIMER_SET BIT(31)
+#define BIT_BF1_TIMER_CLR BIT(30)
+#define BIT_BF1_UPDATE_EN BIT(29)
+#define BIT_BF1_TIMER_EN BIT(28)
+
+#define BIT_SHIFT_BF1_PRETIME_OVER 16
+#define BIT_MASK_BF1_PRETIME_OVER 0xfff
+#define BIT_BF1_PRETIME_OVER(x) \
+ (((x) & BIT_MASK_BF1_PRETIME_OVER) << BIT_SHIFT_BF1_PRETIME_OVER)
+#define BITS_BF1_PRETIME_OVER \
+ (BIT_MASK_BF1_PRETIME_OVER << BIT_SHIFT_BF1_PRETIME_OVER)
+#define BIT_CLEAR_BF1_PRETIME_OVER(x) ((x) & (~BITS_BF1_PRETIME_OVER))
+#define BIT_GET_BF1_PRETIME_OVER(x) \
+ (((x) >> BIT_SHIFT_BF1_PRETIME_OVER) & BIT_MASK_BF1_PRETIME_OVER)
+#define BIT_SET_BF1_PRETIME_OVER(x, v) \
+ (BIT_CLEAR_BF1_PRETIME_OVER(x) | BIT_BF1_PRETIME_OVER(v))
+
+#define BIT_SHIFT_BF1_LIFETIME 0
+#define BIT_MASK_BF1_LIFETIME 0xffff
+#define BIT_BF1_LIFETIME(x) \
+ (((x) & BIT_MASK_BF1_LIFETIME) << BIT_SHIFT_BF1_LIFETIME)
+#define BITS_BF1_LIFETIME (BIT_MASK_BF1_LIFETIME << BIT_SHIFT_BF1_LIFETIME)
+#define BIT_CLEAR_BF1_LIFETIME(x) ((x) & (~BITS_BF1_LIFETIME))
+#define BIT_GET_BF1_LIFETIME(x) \
+ (((x) >> BIT_SHIFT_BF1_LIFETIME) & BIT_MASK_BF1_LIFETIME)
+#define BIT_SET_BF1_LIFETIME(x, v) \
+ (BIT_CLEAR_BF1_LIFETIME(x) | BIT_BF1_LIFETIME(v))
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+/* 2 REG_BF_TIMEOUT_EN (Offset 0x1430) */
-#define BIT_PORT3_TX_NULL0_DONE_INT BIT(4)
+#define BIT_EN_VHT_LDPC BIT(9)
+#define BIT_EN_HT_LDPC BIT(8)
+#define BIT_BF1_TIMEOUT_EN BIT(1)
+#define BIT_BF0_TIMEOUT_EN BIT(0)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_MACID_RELEASE0 (Offset 0x1434) */
+#define BIT_SHIFT_MACID31_0_RELEASE 0
+#define BIT_MASK_MACID31_0_RELEASE 0xffffffffL
+#define BIT_MACID31_0_RELEASE(x) \
+ (((x) & BIT_MASK_MACID31_0_RELEASE) << BIT_SHIFT_MACID31_0_RELEASE)
+#define BITS_MACID31_0_RELEASE \
+ (BIT_MASK_MACID31_0_RELEASE << BIT_SHIFT_MACID31_0_RELEASE)
+#define BIT_CLEAR_MACID31_0_RELEASE(x) ((x) & (~BITS_MACID31_0_RELEASE))
+#define BIT_GET_MACID31_0_RELEASE(x) \
+ (((x) >> BIT_SHIFT_MACID31_0_RELEASE) & BIT_MASK_MACID31_0_RELEASE)
+#define BIT_SET_MACID31_0_RELEASE(x, v) \
+ (BIT_CLEAR_MACID31_0_RELEASE(x) | BIT_MACID31_0_RELEASE(v))
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+#endif
-#define BIT_FS_CLI2_TX_NULL0_INT BIT(4)
+#if (HALMAC_8814B_SUPPORT)
-#endif
+/* 2 REG_MACID_RELEASE_INFO (Offset 0x1434) */
+#define BIT_SHIFT_MACID_RELEASE_INFO 0
+#define BIT_MASK_MACID_RELEASE_INFO 0xffffffffL
+#define BIT_MACID_RELEASE_INFO(x) \
+ (((x) & BIT_MASK_MACID_RELEASE_INFO) << BIT_SHIFT_MACID_RELEASE_INFO)
+#define BITS_MACID_RELEASE_INFO \
+ (BIT_MASK_MACID_RELEASE_INFO << BIT_SHIFT_MACID_RELEASE_INFO)
+#define BIT_CLEAR_MACID_RELEASE_INFO(x) ((x) & (~BITS_MACID_RELEASE_INFO))
+#define BIT_GET_MACID_RELEASE_INFO(x) \
+ (((x) >> BIT_SHIFT_MACID_RELEASE_INFO) & BIT_MASK_MACID_RELEASE_INFO)
+#define BIT_SET_MACID_RELEASE_INFO(x, v) \
+ (BIT_CLEAR_MACID_RELEASE_INFO(x) | BIT_MACID_RELEASE_INFO(v))
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+/* 2 REG_MACID_RELEASE1 (Offset 0x1438) */
-#define BIT_PORT2_TX_NULL1_DONE_INT BIT(3)
+#define BIT_SHIFT_MACID63_32_RELEASE 0
+#define BIT_MASK_MACID63_32_RELEASE 0xffffffffL
+#define BIT_MACID63_32_RELEASE(x) \
+ (((x) & BIT_MASK_MACID63_32_RELEASE) << BIT_SHIFT_MACID63_32_RELEASE)
+#define BITS_MACID63_32_RELEASE \
+ (BIT_MASK_MACID63_32_RELEASE << BIT_SHIFT_MACID63_32_RELEASE)
+#define BIT_CLEAR_MACID63_32_RELEASE(x) ((x) & (~BITS_MACID63_32_RELEASE))
+#define BIT_GET_MACID63_32_RELEASE(x) \
+ (((x) >> BIT_SHIFT_MACID63_32_RELEASE) & BIT_MASK_MACID63_32_RELEASE)
+#define BIT_SET_MACID63_32_RELEASE(x, v) \
+ (BIT_CLEAR_MACID63_32_RELEASE(x) | BIT_MACID63_32_RELEASE(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_MACID_RELEASE_SUCCESS_INFO (Offset 0x1438) */
+
+#define BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO 0
+#define BIT_MASK_MACID_RELEASE_SUCCESS_INFO 0xffffffffL
+#define BIT_MACID_RELEASE_SUCCESS_INFO(x) \
+ (((x) & BIT_MASK_MACID_RELEASE_SUCCESS_INFO) \
+ << BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO)
+#define BITS_MACID_RELEASE_SUCCESS_INFO \
+ (BIT_MASK_MACID_RELEASE_SUCCESS_INFO \
+ << BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO)
+#define BIT_CLEAR_MACID_RELEASE_SUCCESS_INFO(x) \
+ ((x) & (~BITS_MACID_RELEASE_SUCCESS_INFO))
+#define BIT_GET_MACID_RELEASE_SUCCESS_INFO(x) \
+ (((x) >> BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO) & \
+ BIT_MASK_MACID_RELEASE_SUCCESS_INFO)
+#define BIT_SET_MACID_RELEASE_SUCCESS_INFO(x, v) \
+ (BIT_CLEAR_MACID_RELEASE_SUCCESS_INFO(x) | \
+ BIT_MACID_RELEASE_SUCCESS_INFO(v))
+
+/* 2 REG_MACID_RELEASE_CTRL (Offset 0x143C) */
+
+#define BIT_SHIFT_MACID_RELEASE_SEL 24
+#define BIT_MASK_MACID_RELEASE_SEL 0x7
+#define BIT_MACID_RELEASE_SEL(x) \
+ (((x) & BIT_MASK_MACID_RELEASE_SEL) << BIT_SHIFT_MACID_RELEASE_SEL)
+#define BITS_MACID_RELEASE_SEL \
+ (BIT_MASK_MACID_RELEASE_SEL << BIT_SHIFT_MACID_RELEASE_SEL)
+#define BIT_CLEAR_MACID_RELEASE_SEL(x) ((x) & (~BITS_MACID_RELEASE_SEL))
+#define BIT_GET_MACID_RELEASE_SEL(x) \
+ (((x) >> BIT_SHIFT_MACID_RELEASE_SEL) & BIT_MASK_MACID_RELEASE_SEL)
+#define BIT_SET_MACID_RELEASE_SEL(x, v) \
+ (BIT_CLEAR_MACID_RELEASE_SEL(x) | BIT_MACID_RELEASE_SEL(v))
+
+#define BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET 16
+#define BIT_MASK_MACID_RELEASE_CLEAR_OFFSET 0xff
+#define BIT_MACID_RELEASE_CLEAR_OFFSET(x) \
+ (((x) & BIT_MASK_MACID_RELEASE_CLEAR_OFFSET) \
+ << BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET)
+#define BITS_MACID_RELEASE_CLEAR_OFFSET \
+ (BIT_MASK_MACID_RELEASE_CLEAR_OFFSET \
+ << BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET)
+#define BIT_CLEAR_MACID_RELEASE_CLEAR_OFFSET(x) \
+ ((x) & (~BITS_MACID_RELEASE_CLEAR_OFFSET))
+#define BIT_GET_MACID_RELEASE_CLEAR_OFFSET(x) \
+ (((x) >> BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET) & \
+ BIT_MASK_MACID_RELEASE_CLEAR_OFFSET)
+#define BIT_SET_MACID_RELEASE_CLEAR_OFFSET(x, v) \
+ (BIT_CLEAR_MACID_RELEASE_CLEAR_OFFSET(x) | \
+ BIT_MACID_RELEASE_CLEAR_OFFSET(v))
+
+#define BIT_MACID_RELEASE_VALUE BIT(8)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_MACID_RELEASE2 (Offset 0x143C) */
+#define BIT_SHIFT_MACID95_64_RELEASE 0
+#define BIT_MASK_MACID95_64_RELEASE 0xffffffffL
+#define BIT_MACID95_64_RELEASE(x) \
+ (((x) & BIT_MASK_MACID95_64_RELEASE) << BIT_SHIFT_MACID95_64_RELEASE)
+#define BITS_MACID95_64_RELEASE \
+ (BIT_MASK_MACID95_64_RELEASE << BIT_SHIFT_MACID95_64_RELEASE)
+#define BIT_CLEAR_MACID95_64_RELEASE(x) ((x) & (~BITS_MACID95_64_RELEASE))
+#define BIT_GET_MACID95_64_RELEASE(x) \
+ (((x) >> BIT_SHIFT_MACID95_64_RELEASE) & BIT_MASK_MACID95_64_RELEASE)
+#define BIT_SET_MACID95_64_RELEASE(x, v) \
+ (BIT_CLEAR_MACID95_64_RELEASE(x) | BIT_MACID95_64_RELEASE(v))
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+/* 2 REG_MACID_RELEASE_CTRL (Offset 0x143C) */
-#define BIT_FS_CLI1_TX_NULL1_INT BIT(3)
+#define BIT_SHIFT_MACID_RELEASE_OFFSET 0
+#define BIT_MASK_MACID_RELEASE_OFFSET 0xff
+#define BIT_MACID_RELEASE_OFFSET(x) \
+ (((x) & BIT_MASK_MACID_RELEASE_OFFSET) \
+ << BIT_SHIFT_MACID_RELEASE_OFFSET)
+#define BITS_MACID_RELEASE_OFFSET \
+ (BIT_MASK_MACID_RELEASE_OFFSET << BIT_SHIFT_MACID_RELEASE_OFFSET)
+#define BIT_CLEAR_MACID_RELEASE_OFFSET(x) ((x) & (~BITS_MACID_RELEASE_OFFSET))
+#define BIT_GET_MACID_RELEASE_OFFSET(x) \
+ (((x) >> BIT_SHIFT_MACID_RELEASE_OFFSET) & \
+ BIT_MASK_MACID_RELEASE_OFFSET)
+#define BIT_SET_MACID_RELEASE_OFFSET(x, v) \
+ (BIT_CLEAR_MACID_RELEASE_OFFSET(x) | BIT_MACID_RELEASE_OFFSET(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_MACID_RELEASE3 (Offset 0x1440) */
+#define BIT_SHIFT_MACID127_96_RELEASE 0
+#define BIT_MASK_MACID127_96_RELEASE 0xffffffffL
+#define BIT_MACID127_96_RELEASE(x) \
+ (((x) & BIT_MASK_MACID127_96_RELEASE) << BIT_SHIFT_MACID127_96_RELEASE)
+#define BITS_MACID127_96_RELEASE \
+ (BIT_MASK_MACID127_96_RELEASE << BIT_SHIFT_MACID127_96_RELEASE)
+#define BIT_CLEAR_MACID127_96_RELEASE(x) ((x) & (~BITS_MACID127_96_RELEASE))
+#define BIT_GET_MACID127_96_RELEASE(x) \
+ (((x) >> BIT_SHIFT_MACID127_96_RELEASE) & BIT_MASK_MACID127_96_RELEASE)
+#define BIT_SET_MACID127_96_RELEASE(x, v) \
+ (BIT_CLEAR_MACID127_96_RELEASE(x) | BIT_MACID127_96_RELEASE(v))
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+/* 2 REG_MACID_RELEASE_SETTING (Offset 0x1444) */
-#define BIT_PORT2_TX_NULL0_DONE_INT BIT(2)
+#define BIT_MACID_VALUE BIT(7)
+
+#define BIT_SHIFT_MACID_OFFSET 0
+#define BIT_MASK_MACID_OFFSET 0x7f
+#define BIT_MACID_OFFSET(x) \
+ (((x) & BIT_MASK_MACID_OFFSET) << BIT_SHIFT_MACID_OFFSET)
+#define BITS_MACID_OFFSET (BIT_MASK_MACID_OFFSET << BIT_SHIFT_MACID_OFFSET)
+#define BIT_CLEAR_MACID_OFFSET(x) ((x) & (~BITS_MACID_OFFSET))
+#define BIT_GET_MACID_OFFSET(x) \
+ (((x) >> BIT_SHIFT_MACID_OFFSET) & BIT_MASK_MACID_OFFSET)
+#define BIT_SET_MACID_OFFSET(x, v) \
+ (BIT_CLEAR_MACID_OFFSET(x) | BIT_MACID_OFFSET(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_FAST_EDCA_VOVI_SETTING (Offset 0x1448) */
+#define BIT_SHIFT_VI_FAST_EDCA_TO 24
+#define BIT_MASK_VI_FAST_EDCA_TO 0xff
+#define BIT_VI_FAST_EDCA_TO(x) \
+ (((x) & BIT_MASK_VI_FAST_EDCA_TO) << BIT_SHIFT_VI_FAST_EDCA_TO)
+#define BITS_VI_FAST_EDCA_TO \
+ (BIT_MASK_VI_FAST_EDCA_TO << BIT_SHIFT_VI_FAST_EDCA_TO)
+#define BIT_CLEAR_VI_FAST_EDCA_TO(x) ((x) & (~BITS_VI_FAST_EDCA_TO))
+#define BIT_GET_VI_FAST_EDCA_TO(x) \
+ (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO) & BIT_MASK_VI_FAST_EDCA_TO)
+#define BIT_SET_VI_FAST_EDCA_TO(x, v) \
+ (BIT_CLEAR_VI_FAST_EDCA_TO(x) | BIT_VI_FAST_EDCA_TO(v))
+
+#define BIT_VI_THRESHOLD_SEL BIT(23)
+
+#define BIT_SHIFT_VI_FAST_EDCA_PKT_TH 16
+#define BIT_MASK_VI_FAST_EDCA_PKT_TH 0x7f
+#define BIT_VI_FAST_EDCA_PKT_TH(x) \
+ (((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH) << BIT_SHIFT_VI_FAST_EDCA_PKT_TH)
+#define BITS_VI_FAST_EDCA_PKT_TH \
+ (BIT_MASK_VI_FAST_EDCA_PKT_TH << BIT_SHIFT_VI_FAST_EDCA_PKT_TH)
+#define BIT_CLEAR_VI_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_VI_FAST_EDCA_PKT_TH))
+#define BIT_GET_VI_FAST_EDCA_PKT_TH(x) \
+ (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH) & BIT_MASK_VI_FAST_EDCA_PKT_TH)
+#define BIT_SET_VI_FAST_EDCA_PKT_TH(x, v) \
+ (BIT_CLEAR_VI_FAST_EDCA_PKT_TH(x) | BIT_VI_FAST_EDCA_PKT_TH(v))
+
+#define BIT_SHIFT_VO_FAST_EDCA_TO 8
+#define BIT_MASK_VO_FAST_EDCA_TO 0xff
+#define BIT_VO_FAST_EDCA_TO(x) \
+ (((x) & BIT_MASK_VO_FAST_EDCA_TO) << BIT_SHIFT_VO_FAST_EDCA_TO)
+#define BITS_VO_FAST_EDCA_TO \
+ (BIT_MASK_VO_FAST_EDCA_TO << BIT_SHIFT_VO_FAST_EDCA_TO)
+#define BIT_CLEAR_VO_FAST_EDCA_TO(x) ((x) & (~BITS_VO_FAST_EDCA_TO))
+#define BIT_GET_VO_FAST_EDCA_TO(x) \
+ (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO) & BIT_MASK_VO_FAST_EDCA_TO)
+#define BIT_SET_VO_FAST_EDCA_TO(x, v) \
+ (BIT_CLEAR_VO_FAST_EDCA_TO(x) | BIT_VO_FAST_EDCA_TO(v))
+
+#define BIT_VO_THRESHOLD_SEL BIT(7)
+
+#define BIT_SHIFT_VO_FAST_EDCA_PKT_TH 0
+#define BIT_MASK_VO_FAST_EDCA_PKT_TH 0x7f
+#define BIT_VO_FAST_EDCA_PKT_TH(x) \
+ (((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH) << BIT_SHIFT_VO_FAST_EDCA_PKT_TH)
+#define BITS_VO_FAST_EDCA_PKT_TH \
+ (BIT_MASK_VO_FAST_EDCA_PKT_TH << BIT_SHIFT_VO_FAST_EDCA_PKT_TH)
+#define BIT_CLEAR_VO_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_VO_FAST_EDCA_PKT_TH))
+#define BIT_GET_VO_FAST_EDCA_PKT_TH(x) \
+ (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH) & BIT_MASK_VO_FAST_EDCA_PKT_TH)
+#define BIT_SET_VO_FAST_EDCA_PKT_TH(x, v) \
+ (BIT_CLEAR_VO_FAST_EDCA_PKT_TH(x) | BIT_VO_FAST_EDCA_PKT_TH(v))
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+/* 2 REG_FAST_EDCA_BEBK_SETTING (Offset 0x144C) */
-#define BIT_FS_CLI1_TX_NULL0_INT BIT(2)
+#define BIT_SHIFT_BK_FAST_EDCA_TO 24
+#define BIT_MASK_BK_FAST_EDCA_TO 0xff
+#define BIT_BK_FAST_EDCA_TO(x) \
+ (((x) & BIT_MASK_BK_FAST_EDCA_TO) << BIT_SHIFT_BK_FAST_EDCA_TO)
+#define BITS_BK_FAST_EDCA_TO \
+ (BIT_MASK_BK_FAST_EDCA_TO << BIT_SHIFT_BK_FAST_EDCA_TO)
+#define BIT_CLEAR_BK_FAST_EDCA_TO(x) ((x) & (~BITS_BK_FAST_EDCA_TO))
+#define BIT_GET_BK_FAST_EDCA_TO(x) \
+ (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO) & BIT_MASK_BK_FAST_EDCA_TO)
+#define BIT_SET_BK_FAST_EDCA_TO(x, v) \
+ (BIT_CLEAR_BK_FAST_EDCA_TO(x) | BIT_BK_FAST_EDCA_TO(v))
+
+#define BIT_BK_THRESHOLD_SEL BIT(23)
+
+#define BIT_SHIFT_BK_FAST_EDCA_PKT_TH 16
+#define BIT_MASK_BK_FAST_EDCA_PKT_TH 0x7f
+#define BIT_BK_FAST_EDCA_PKT_TH(x) \
+ (((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH) << BIT_SHIFT_BK_FAST_EDCA_PKT_TH)
+#define BITS_BK_FAST_EDCA_PKT_TH \
+ (BIT_MASK_BK_FAST_EDCA_PKT_TH << BIT_SHIFT_BK_FAST_EDCA_PKT_TH)
+#define BIT_CLEAR_BK_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_BK_FAST_EDCA_PKT_TH))
+#define BIT_GET_BK_FAST_EDCA_PKT_TH(x) \
+ (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH) & BIT_MASK_BK_FAST_EDCA_PKT_TH)
+#define BIT_SET_BK_FAST_EDCA_PKT_TH(x, v) \
+ (BIT_CLEAR_BK_FAST_EDCA_PKT_TH(x) | BIT_BK_FAST_EDCA_PKT_TH(v))
+
+#define BIT_SHIFT_BE_FAST_EDCA_TO 8
+#define BIT_MASK_BE_FAST_EDCA_TO 0xff
+#define BIT_BE_FAST_EDCA_TO(x) \
+ (((x) & BIT_MASK_BE_FAST_EDCA_TO) << BIT_SHIFT_BE_FAST_EDCA_TO)
+#define BITS_BE_FAST_EDCA_TO \
+ (BIT_MASK_BE_FAST_EDCA_TO << BIT_SHIFT_BE_FAST_EDCA_TO)
+#define BIT_CLEAR_BE_FAST_EDCA_TO(x) ((x) & (~BITS_BE_FAST_EDCA_TO))
+#define BIT_GET_BE_FAST_EDCA_TO(x) \
+ (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO) & BIT_MASK_BE_FAST_EDCA_TO)
+#define BIT_SET_BE_FAST_EDCA_TO(x, v) \
+ (BIT_CLEAR_BE_FAST_EDCA_TO(x) | BIT_BE_FAST_EDCA_TO(v))
+
+#define BIT_BE_THRESHOLD_SEL BIT(7)
+#define BIT_EN_P2P_CTWINDOW BIT(1)
+
+#define BIT_SHIFT_BE_FAST_EDCA_PKT_TH 0
+#define BIT_MASK_BE_FAST_EDCA_PKT_TH 0x7f
+#define BIT_BE_FAST_EDCA_PKT_TH(x) \
+ (((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH) << BIT_SHIFT_BE_FAST_EDCA_PKT_TH)
+#define BITS_BE_FAST_EDCA_PKT_TH \
+ (BIT_MASK_BE_FAST_EDCA_PKT_TH << BIT_SHIFT_BE_FAST_EDCA_PKT_TH)
+#define BIT_CLEAR_BE_FAST_EDCA_PKT_TH(x) ((x) & (~BITS_BE_FAST_EDCA_PKT_TH))
+#define BIT_GET_BE_FAST_EDCA_PKT_TH(x) \
+ (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH) & BIT_MASK_BE_FAST_EDCA_PKT_TH)
+#define BIT_SET_BE_FAST_EDCA_PKT_TH(x, v) \
+ (BIT_CLEAR_BE_FAST_EDCA_PKT_TH(x) | BIT_BE_FAST_EDCA_PKT_TH(v))
+
+#define BIT_EN_P2P_BCNQ_AREA BIT(0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_MACID_DROP0 (Offset 0x1450) */
+#define BIT_SHIFT_MACID31_0_DROP 0
+#define BIT_MASK_MACID31_0_DROP 0xffffffffL
+#define BIT_MACID31_0_DROP(x) \
+ (((x) & BIT_MASK_MACID31_0_DROP) << BIT_SHIFT_MACID31_0_DROP)
+#define BITS_MACID31_0_DROP \
+ (BIT_MASK_MACID31_0_DROP << BIT_SHIFT_MACID31_0_DROP)
+#define BIT_CLEAR_MACID31_0_DROP(x) ((x) & (~BITS_MACID31_0_DROP))
+#define BIT_GET_MACID31_0_DROP(x) \
+ (((x) >> BIT_SHIFT_MACID31_0_DROP) & BIT_MASK_MACID31_0_DROP)
+#define BIT_SET_MACID31_0_DROP(x, v) \
+ (BIT_CLEAR_MACID31_0_DROP(x) | BIT_MACID31_0_DROP(v))
-#if (HALMAC_8197F_SUPPORT)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+/* 2 REG_MACID_DROP_INFO (Offset 0x1450) */
-#define BIT_PORT1_TX_NULL1_DONE_INT BIT(1)
+#define BIT_SHIFT_MACID_DROP_INFO 0
+#define BIT_MASK_MACID_DROP_INFO 0xffffffffL
+#define BIT_MACID_DROP_INFO(x) \
+ (((x) & BIT_MASK_MACID_DROP_INFO) << BIT_SHIFT_MACID_DROP_INFO)
+#define BITS_MACID_DROP_INFO \
+ (BIT_MASK_MACID_DROP_INFO << BIT_SHIFT_MACID_DROP_INFO)
+#define BIT_CLEAR_MACID_DROP_INFO(x) ((x) & (~BITS_MACID_DROP_INFO))
+#define BIT_GET_MACID_DROP_INFO(x) \
+ (((x) >> BIT_SHIFT_MACID_DROP_INFO) & BIT_MASK_MACID_DROP_INFO)
+#define BIT_SET_MACID_DROP_INFO(x, v) \
+ (BIT_CLEAR_MACID_DROP_INFO(x) | BIT_MACID_DROP_INFO(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_MACID_DROP1 (Offset 0x1454) */
+#define BIT_SHIFT_MACID63_32_DROP 0
+#define BIT_MASK_MACID63_32_DROP 0xffffffffL
+#define BIT_MACID63_32_DROP(x) \
+ (((x) & BIT_MASK_MACID63_32_DROP) << BIT_SHIFT_MACID63_32_DROP)
+#define BITS_MACID63_32_DROP \
+ (BIT_MASK_MACID63_32_DROP << BIT_SHIFT_MACID63_32_DROP)
+#define BIT_CLEAR_MACID63_32_DROP(x) ((x) & (~BITS_MACID63_32_DROP))
+#define BIT_GET_MACID63_32_DROP(x) \
+ (((x) >> BIT_SHIFT_MACID63_32_DROP) & BIT_MASK_MACID63_32_DROP)
+#define BIT_SET_MACID63_32_DROP(x, v) \
+ (BIT_CLEAR_MACID63_32_DROP(x) | BIT_MACID63_32_DROP(v))
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_MACID_DROP_CTRL (Offset 0x1454) */
-#define BIT_FS_CLI0_TX_NULL1_INT BIT(1)
+#define BIT_SHIFT_MACID_DROP_SEL 0
+#define BIT_MASK_MACID_DROP_SEL 0x7
+#define BIT_MACID_DROP_SEL(x) \
+ (((x) & BIT_MASK_MACID_DROP_SEL) << BIT_SHIFT_MACID_DROP_SEL)
+#define BITS_MACID_DROP_SEL \
+ (BIT_MASK_MACID_DROP_SEL << BIT_SHIFT_MACID_DROP_SEL)
+#define BIT_CLEAR_MACID_DROP_SEL(x) ((x) & (~BITS_MACID_DROP_SEL))
+#define BIT_GET_MACID_DROP_SEL(x) \
+ (((x) >> BIT_SHIFT_MACID_DROP_SEL) & BIT_MASK_MACID_DROP_SEL)
+#define BIT_SET_MACID_DROP_SEL(x, v) \
+ (BIT_CLEAR_MACID_DROP_SEL(x) | BIT_MACID_DROP_SEL(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_MACID_DROP2 (Offset 0x1458) */
+#define BIT_SHIFT_MACID95_64_DROP 0
+#define BIT_MASK_MACID95_64_DROP 0xffffffffL
+#define BIT_MACID95_64_DROP(x) \
+ (((x) & BIT_MASK_MACID95_64_DROP) << BIT_SHIFT_MACID95_64_DROP)
+#define BITS_MACID95_64_DROP \
+ (BIT_MASK_MACID95_64_DROP << BIT_SHIFT_MACID95_64_DROP)
+#define BIT_CLEAR_MACID95_64_DROP(x) ((x) & (~BITS_MACID95_64_DROP))
+#define BIT_GET_MACID95_64_DROP(x) \
+ (((x) >> BIT_SHIFT_MACID95_64_DROP) & BIT_MASK_MACID95_64_DROP)
+#define BIT_SET_MACID95_64_DROP(x, v) \
+ (BIT_CLEAR_MACID95_64_DROP(x) | BIT_MACID95_64_DROP(v))
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+/* 2 REG_MACID_DROP3 (Offset 0x145C) */
-#define BIT_PORT1_TX_NULL0_DONE_INT BIT(0)
+#define BIT_SHIFT_MACID127_96_DROP 0
+#define BIT_MASK_MACID127_96_DROP 0xffffffffL
+#define BIT_MACID127_96_DROP(x) \
+ (((x) & BIT_MASK_MACID127_96_DROP) << BIT_SHIFT_MACID127_96_DROP)
+#define BITS_MACID127_96_DROP \
+ (BIT_MASK_MACID127_96_DROP << BIT_SHIFT_MACID127_96_DROP)
+#define BIT_CLEAR_MACID127_96_DROP(x) ((x) & (~BITS_MACID127_96_DROP))
+#define BIT_GET_MACID127_96_DROP(x) \
+ (((x) >> BIT_SHIFT_MACID127_96_DROP) & BIT_MASK_MACID127_96_DROP)
+#define BIT_SET_MACID127_96_DROP(x, v) \
+ (BIT_CLEAR_MACID127_96_DROP(x) | BIT_MACID127_96_DROP(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+/* 2 REG_R_MACID_RELEASE_SUCCESS_0 (Offset 0x1460) */
-/* 2 REG_FT2ISR (Offset 0x11E4) */
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_0 0xffffffffL
+#define BIT_R_MACID_RELEASE_SUCCESS_0(x) \
+ (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0) \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0)
+#define BITS_R_MACID_RELEASE_SUCCESS_0 \
+ (BIT_MASK_R_MACID_RELEASE_SUCCESS_0 \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0(x) \
+ ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_0))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_0(x) \
+ (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0) & \
+ BIT_MASK_R_MACID_RELEASE_SUCCESS_0)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_0(x, v) \
+ (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0(x) | \
+ BIT_R_MACID_RELEASE_SUCCESS_0(v))
-#define BIT_FS_CLI0_TX_NULL0_INT BIT(0)
+/* 2 REG_R_MACID_RELEASE_SUCCESS_1 (Offset 0x1464) */
-#endif
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_1 0xffffffffL
+#define BIT_R_MACID_RELEASE_SUCCESS_1(x) \
+ (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1) \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1)
+#define BITS_R_MACID_RELEASE_SUCCESS_1 \
+ (BIT_MASK_R_MACID_RELEASE_SUCCESS_1 \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1(x) \
+ ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_1))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_1(x) \
+ (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1) & \
+ BIT_MASK_R_MACID_RELEASE_SUCCESS_1)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_1(x, v) \
+ (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1(x) | \
+ BIT_R_MACID_RELEASE_SUCCESS_1(v))
+/* 2 REG_R_MACID_RELEASE_SUCCESS_2 (Offset 0x1468) */
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_2 0xffffffffL
+#define BIT_R_MACID_RELEASE_SUCCESS_2(x) \
+ (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2) \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2)
+#define BITS_R_MACID_RELEASE_SUCCESS_2 \
+ (BIT_MASK_R_MACID_RELEASE_SUCCESS_2 \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2(x) \
+ ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_2))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_2(x) \
+ (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2) & \
+ BIT_MASK_R_MACID_RELEASE_SUCCESS_2)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_2(x, v) \
+ (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2(x) | \
+ BIT_R_MACID_RELEASE_SUCCESS_2(v))
+/* 2 REG_R_MACID_RELEASE_SUCCESS_3 (Offset 0x146C) */
-/* 2 REG_MSG2 (Offset 0x11F0) */
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_3 0xffffffffL
+#define BIT_R_MACID_RELEASE_SUCCESS_3(x) \
+ (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3) \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3)
+#define BITS_R_MACID_RELEASE_SUCCESS_3 \
+ (BIT_MASK_R_MACID_RELEASE_SUCCESS_3 \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3(x) \
+ ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_3))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_3(x) \
+ (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3) & \
+ BIT_MASK_R_MACID_RELEASE_SUCCESS_3)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_3(x, v) \
+ (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3(x) | \
+ BIT_R_MACID_RELEASE_SUCCESS_3(v))
+#endif
-#define BIT_SHIFT_FW_MSG2 0
-#define BIT_MASK_FW_MSG2 0xffffffffL
-#define BIT_FW_MSG2(x) (((x) & BIT_MASK_FW_MSG2) << BIT_SHIFT_FW_MSG2)
-#define BIT_GET_FW_MSG2(x) (((x) >> BIT_SHIFT_FW_MSG2) & BIT_MASK_FW_MSG2)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_MGG_FIFO_CRTL (Offset 0x1470) */
-/* 2 REG_MSG3 (Offset 0x11F4) */
+#define BIT_R_MGG_FIFO_EN BIT(31)
+#define BIT_SHIFT_R_MGG_FIFO_PG_SIZE 28
+#define BIT_MASK_R_MGG_FIFO_PG_SIZE 0x7
+#define BIT_R_MGG_FIFO_PG_SIZE(x) \
+ (((x) & BIT_MASK_R_MGG_FIFO_PG_SIZE) << BIT_SHIFT_R_MGG_FIFO_PG_SIZE)
+#define BITS_R_MGG_FIFO_PG_SIZE \
+ (BIT_MASK_R_MGG_FIFO_PG_SIZE << BIT_SHIFT_R_MGG_FIFO_PG_SIZE)
+#define BIT_CLEAR_R_MGG_FIFO_PG_SIZE(x) ((x) & (~BITS_R_MGG_FIFO_PG_SIZE))
+#define BIT_GET_R_MGG_FIFO_PG_SIZE(x) \
+ (((x) >> BIT_SHIFT_R_MGG_FIFO_PG_SIZE) & BIT_MASK_R_MGG_FIFO_PG_SIZE)
+#define BIT_SET_R_MGG_FIFO_PG_SIZE(x, v) \
+ (BIT_CLEAR_R_MGG_FIFO_PG_SIZE(x) | BIT_R_MGG_FIFO_PG_SIZE(v))
-#define BIT_SHIFT_FW_MSG3 0
-#define BIT_MASK_FW_MSG3 0xffffffffL
-#define BIT_FW_MSG3(x) (((x) & BIT_MASK_FW_MSG3) << BIT_SHIFT_FW_MSG3)
-#define BIT_GET_FW_MSG3(x) (((x) >> BIT_SHIFT_FW_MSG3) & BIT_MASK_FW_MSG3)
+#define BIT_SHIFT_R_MGG_FIFO_START_PG 16
+#define BIT_MASK_R_MGG_FIFO_START_PG 0xfff
+#define BIT_R_MGG_FIFO_START_PG(x) \
+ (((x) & BIT_MASK_R_MGG_FIFO_START_PG) << BIT_SHIFT_R_MGG_FIFO_START_PG)
+#define BITS_R_MGG_FIFO_START_PG \
+ (BIT_MASK_R_MGG_FIFO_START_PG << BIT_SHIFT_R_MGG_FIFO_START_PG)
+#define BIT_CLEAR_R_MGG_FIFO_START_PG(x) ((x) & (~BITS_R_MGG_FIFO_START_PG))
+#define BIT_GET_R_MGG_FIFO_START_PG(x) \
+ (((x) >> BIT_SHIFT_R_MGG_FIFO_START_PG) & BIT_MASK_R_MGG_FIFO_START_PG)
+#define BIT_SET_R_MGG_FIFO_START_PG(x, v) \
+ (BIT_CLEAR_R_MGG_FIFO_START_PG(x) | BIT_R_MGG_FIFO_START_PG(v))
+#define BIT_SHIFT_R_MGG_FIFO_SIZE 14
+#define BIT_MASK_R_MGG_FIFO_SIZE 0x3
+#define BIT_R_MGG_FIFO_SIZE(x) \
+ (((x) & BIT_MASK_R_MGG_FIFO_SIZE) << BIT_SHIFT_R_MGG_FIFO_SIZE)
+#define BITS_R_MGG_FIFO_SIZE \
+ (BIT_MASK_R_MGG_FIFO_SIZE << BIT_SHIFT_R_MGG_FIFO_SIZE)
+#define BIT_CLEAR_R_MGG_FIFO_SIZE(x) ((x) & (~BITS_R_MGG_FIFO_SIZE))
+#define BIT_GET_R_MGG_FIFO_SIZE(x) \
+ (((x) >> BIT_SHIFT_R_MGG_FIFO_SIZE) & BIT_MASK_R_MGG_FIFO_SIZE)
+#define BIT_SET_R_MGG_FIFO_SIZE(x, v) \
+ (BIT_CLEAR_R_MGG_FIFO_SIZE(x) | BIT_R_MGG_FIFO_SIZE(v))
-/* 2 REG_MSG4 (Offset 0x11F8) */
+#define BIT_R_MGG_FIFO_PAUSE BIT(13)
+#define BIT_SHIFT_R_MGG_FIFO_RPTR 8
+#define BIT_MASK_R_MGG_FIFO_RPTR 0x1f
+#define BIT_R_MGG_FIFO_RPTR(x) \
+ (((x) & BIT_MASK_R_MGG_FIFO_RPTR) << BIT_SHIFT_R_MGG_FIFO_RPTR)
+#define BITS_R_MGG_FIFO_RPTR \
+ (BIT_MASK_R_MGG_FIFO_RPTR << BIT_SHIFT_R_MGG_FIFO_RPTR)
+#define BIT_CLEAR_R_MGG_FIFO_RPTR(x) ((x) & (~BITS_R_MGG_FIFO_RPTR))
+#define BIT_GET_R_MGG_FIFO_RPTR(x) \
+ (((x) >> BIT_SHIFT_R_MGG_FIFO_RPTR) & BIT_MASK_R_MGG_FIFO_RPTR)
+#define BIT_SET_R_MGG_FIFO_RPTR(x, v) \
+ (BIT_CLEAR_R_MGG_FIFO_RPTR(x) | BIT_R_MGG_FIFO_RPTR(v))
-#define BIT_SHIFT_FW_MSG4 0
-#define BIT_MASK_FW_MSG4 0xffffffffL
-#define BIT_FW_MSG4(x) (((x) & BIT_MASK_FW_MSG4) << BIT_SHIFT_FW_MSG4)
-#define BIT_GET_FW_MSG4(x) (((x) >> BIT_SHIFT_FW_MSG4) & BIT_MASK_FW_MSG4)
+#define BIT_R_MGG_FIFO_OV BIT(7)
+#endif
-/* 2 REG_MSG5 (Offset 0x11FC) */
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+/* 2 REG_MGQ_FIFO_WRITE_POINTER (Offset 0x1470) */
-#define BIT_SHIFT_FW_MSG5 0
-#define BIT_MASK_FW_MSG5 0xffffffffL
-#define BIT_FW_MSG5(x) (((x) & BIT_MASK_FW_MSG5) << BIT_SHIFT_FW_MSG5)
-#define BIT_GET_FW_MSG5(x) (((x) >> BIT_SHIFT_FW_MSG5) & BIT_MASK_FW_MSG5)
+#define BIT_MGQ_FIFO_OV BIT(7)
+#endif
-/* 2 REG_DDMA_CH0SA (Offset 0x1200) */
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_MGG_FIFO_CRTL (Offset 0x1470) */
-#define BIT_SHIFT_DDMACH0_SA 0
-#define BIT_MASK_DDMACH0_SA 0xffffffffL
-#define BIT_DDMACH0_SA(x) (((x) & BIT_MASK_DDMACH0_SA) << BIT_SHIFT_DDMACH0_SA)
-#define BIT_GET_DDMACH0_SA(x) (((x) >> BIT_SHIFT_DDMACH0_SA) & BIT_MASK_DDMACH0_SA)
+#define BIT_R_MGG_FIFO_WPTR_ERROR BIT(6)
+#endif
-/* 2 REG_DDMA_CH0DA (Offset 0x1204) */
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+/* 2 REG_MGQ_FIFO_WRITE_POINTER (Offset 0x1470) */
-#define BIT_SHIFT_DDMACH0_DA 0
-#define BIT_MASK_DDMACH0_DA 0xffffffffL
-#define BIT_DDMACH0_DA(x) (((x) & BIT_MASK_DDMACH0_DA) << BIT_SHIFT_DDMACH0_DA)
-#define BIT_GET_DDMACH0_DA(x) (((x) >> BIT_SHIFT_DDMACH0_DA) & BIT_MASK_DDMACH0_DA)
+#define BIT_MGQ_FIFO_WPTR_ERROR BIT(6)
+#endif
-/* 2 REG_DDMA_CH0CTRL (Offset 0x1208) */
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
-#define BIT_DDMACH0_OWN BIT(31)
-#define BIT_DDMACH0_CHKSUM_EN BIT(29)
-#define BIT_DDMACH0_DA_W_DISABLE BIT(28)
-#define BIT_DDMACH0_CHKSUM_STS BIT(27)
-#define BIT_DDMACH0_DDMA_MODE BIT(26)
-#define BIT_DDMACH0_RESET_CHKSUM_STS BIT(25)
-#define BIT_DDMACH0_CHKSUM_CONT BIT(24)
+/* 2 REG_MGG_FIFO_CRTL (Offset 0x1470) */
-#define BIT_SHIFT_DDMACH0_DLEN 0
-#define BIT_MASK_DDMACH0_DLEN 0x3ffff
-#define BIT_DDMACH0_DLEN(x) (((x) & BIT_MASK_DDMACH0_DLEN) << BIT_SHIFT_DDMACH0_DLEN)
-#define BIT_GET_DDMACH0_DLEN(x) (((x) >> BIT_SHIFT_DDMACH0_DLEN) & BIT_MASK_DDMACH0_DLEN)
+#define BIT_R_EN_CPU_LIFETIME BIT(5)
+#endif
-/* 2 REG_DDMA_CH1SA (Offset 0x1210) */
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+/* 2 REG_MGQ_FIFO_WRITE_POINTER (Offset 0x1470) */
-#define BIT_SHIFT_DDMACH1_SA 0
-#define BIT_MASK_DDMACH1_SA 0xffffffffL
-#define BIT_DDMACH1_SA(x) (((x) & BIT_MASK_DDMACH1_SA) << BIT_SHIFT_DDMACH1_SA)
-#define BIT_GET_DDMACH1_SA(x) (((x) >> BIT_SHIFT_DDMACH1_SA) & BIT_MASK_DDMACH1_SA)
+#define BIT_EN_MGQ_FIFO_LIFETIME BIT(5)
+#endif
-/* 2 REG_DDMA_CH1DA (Offset 0x1214) */
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_MGG_FIFO_CRTL (Offset 0x1470) */
-#define BIT_SHIFT_DDMACH1_DA 0
-#define BIT_MASK_DDMACH1_DA 0xffffffffL
-#define BIT_DDMACH1_DA(x) (((x) & BIT_MASK_DDMACH1_DA) << BIT_SHIFT_DDMACH1_DA)
-#define BIT_GET_DDMACH1_DA(x) (((x) >> BIT_SHIFT_DDMACH1_DA) & BIT_MASK_DDMACH1_DA)
+#define BIT_SHIFT_R_MGG_FIFO_WPTR 0
+#define BIT_MASK_R_MGG_FIFO_WPTR 0x1f
+#define BIT_R_MGG_FIFO_WPTR(x) \
+ (((x) & BIT_MASK_R_MGG_FIFO_WPTR) << BIT_SHIFT_R_MGG_FIFO_WPTR)
+#define BITS_R_MGG_FIFO_WPTR \
+ (BIT_MASK_R_MGG_FIFO_WPTR << BIT_SHIFT_R_MGG_FIFO_WPTR)
+#define BIT_CLEAR_R_MGG_FIFO_WPTR(x) ((x) & (~BITS_R_MGG_FIFO_WPTR))
+#define BIT_GET_R_MGG_FIFO_WPTR(x) \
+ (((x) >> BIT_SHIFT_R_MGG_FIFO_WPTR) & BIT_MASK_R_MGG_FIFO_WPTR)
+#define BIT_SET_R_MGG_FIFO_WPTR(x, v) \
+ (BIT_CLEAR_R_MGG_FIFO_WPTR(x) | BIT_R_MGG_FIFO_WPTR(v))
+#endif
-/* 2 REG_DDMA_CH1CTRL (Offset 0x1218) */
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_DDMACH1_OWN BIT(31)
-#define BIT_DDMACH1_CHKSUM_EN BIT(29)
-#define BIT_DDMACH1_DA_W_DISABLE BIT(28)
-#define BIT_DDMACH1_CHKSUM_STS BIT(27)
-#define BIT_DDMACH1_DDMA_MODE BIT(26)
-#define BIT_DDMACH1_RESET_CHKSUM_STS BIT(25)
-#define BIT_DDMACH1_CHKSUM_CONT BIT(24)
+/* 2 REG_MGQ_FIFO_WRITE_POINTER (Offset 0x1470) */
-#define BIT_SHIFT_DDMACH1_DLEN 0
-#define BIT_MASK_DDMACH1_DLEN 0x3ffff
-#define BIT_DDMACH1_DLEN(x) (((x) & BIT_MASK_DDMACH1_DLEN) << BIT_SHIFT_DDMACH1_DLEN)
-#define BIT_GET_DDMACH1_DLEN(x) (((x) >> BIT_SHIFT_DDMACH1_DLEN) & BIT_MASK_DDMACH1_DLEN)
+#define BIT_SHIFT_MGQ_FIFO_WPTR 0
+#define BIT_MASK_MGQ_FIFO_WPTR 0x1f
+#define BIT_MGQ_FIFO_WPTR(x) \
+ (((x) & BIT_MASK_MGQ_FIFO_WPTR) << BIT_SHIFT_MGQ_FIFO_WPTR)
+#define BITS_MGQ_FIFO_WPTR (BIT_MASK_MGQ_FIFO_WPTR << BIT_SHIFT_MGQ_FIFO_WPTR)
+#define BIT_CLEAR_MGQ_FIFO_WPTR(x) ((x) & (~BITS_MGQ_FIFO_WPTR))
+#define BIT_GET_MGQ_FIFO_WPTR(x) \
+ (((x) >> BIT_SHIFT_MGQ_FIFO_WPTR) & BIT_MASK_MGQ_FIFO_WPTR)
+#define BIT_SET_MGQ_FIFO_WPTR(x, v) \
+ (BIT_CLEAR_MGQ_FIFO_WPTR(x) | BIT_MGQ_FIFO_WPTR(v))
+#endif
-/* 2 REG_DDMA_CH2SA (Offset 0x1220) */
+#if (HALMAC_8814B_SUPPORT)
+/* 2 REG_MGQ_FIFO_ENABLE (Offset 0x1472) */
-#define BIT_SHIFT_DDMACH2_SA 0
-#define BIT_MASK_DDMACH2_SA 0xffffffffL
-#define BIT_DDMACH2_SA(x) (((x) & BIT_MASK_DDMACH2_SA) << BIT_SHIFT_DDMACH2_SA)
-#define BIT_GET_DDMACH2_SA(x) (((x) >> BIT_SHIFT_DDMACH2_SA) & BIT_MASK_DDMACH2_SA)
+#define BIT_MGQ_FIFO_EN_V1 BIT(15)
+#endif
-/* 2 REG_DDMA_CH2DA (Offset 0x1224) */
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+/* 2 REG_MGQ_FIFO_ENABLE (Offset 0x1472) */
-#define BIT_SHIFT_DDMACH2_DA 0
-#define BIT_MASK_DDMACH2_DA 0xffffffffL
-#define BIT_DDMACH2_DA(x) (((x) & BIT_MASK_DDMACH2_DA) << BIT_SHIFT_DDMACH2_DA)
-#define BIT_GET_DDMACH2_DA(x) (((x) >> BIT_SHIFT_DDMACH2_DA) & BIT_MASK_DDMACH2_DA)
+#define BIT_MGQ_FIFO_EN BIT(15)
+#endif
-/* 2 REG_DDMA_CH2CTRL (Offset 0x1228) */
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_DDMACH2_OWN BIT(31)
-#define BIT_DDMACH2_CHKSUM_EN BIT(29)
-#define BIT_DDMACH2_DA_W_DISABLE BIT(28)
-#define BIT_DDMACH2_CHKSUM_STS BIT(27)
-#define BIT_DDMACH2_DDMA_MODE BIT(26)
-#define BIT_DDMACH2_RESET_CHKSUM_STS BIT(25)
-#define BIT_DDMACH2_CHKSUM_CONT BIT(24)
+/* 2 REG_MGQ_FIFO_READ_POINTER (Offset 0x1472) */
-#define BIT_SHIFT_DDMACH2_DLEN 0
-#define BIT_MASK_DDMACH2_DLEN 0x3ffff
-#define BIT_DDMACH2_DLEN(x) (((x) & BIT_MASK_DDMACH2_DLEN) << BIT_SHIFT_DDMACH2_DLEN)
-#define BIT_GET_DDMACH2_DLEN(x) (((x) >> BIT_SHIFT_DDMACH2_DLEN) & BIT_MASK_DDMACH2_DLEN)
+#define BIT_SHIFT_MGQ_FIFO_SIZE 14
+#define BIT_MASK_MGQ_FIFO_SIZE 0x3
+#define BIT_MGQ_FIFO_SIZE(x) \
+ (((x) & BIT_MASK_MGQ_FIFO_SIZE) << BIT_SHIFT_MGQ_FIFO_SIZE)
+#define BITS_MGQ_FIFO_SIZE (BIT_MASK_MGQ_FIFO_SIZE << BIT_SHIFT_MGQ_FIFO_SIZE)
+#define BIT_CLEAR_MGQ_FIFO_SIZE(x) ((x) & (~BITS_MGQ_FIFO_SIZE))
+#define BIT_GET_MGQ_FIFO_SIZE(x) \
+ (((x) >> BIT_SHIFT_MGQ_FIFO_SIZE) & BIT_MASK_MGQ_FIFO_SIZE)
+#define BIT_SET_MGQ_FIFO_SIZE(x, v) \
+ (BIT_CLEAR_MGQ_FIFO_SIZE(x) | BIT_MGQ_FIFO_SIZE(v))
+#define BIT_MGQ_FIFO_PAUSE BIT(13)
-/* 2 REG_DDMA_CH3SA (Offset 0x1230) */
+#define BIT_SHIFT_MGQ_FIFO_PG_SIZE 12
+#define BIT_MASK_MGQ_FIFO_PG_SIZE 0x7
+#define BIT_MGQ_FIFO_PG_SIZE(x) \
+ (((x) & BIT_MASK_MGQ_FIFO_PG_SIZE) << BIT_SHIFT_MGQ_FIFO_PG_SIZE)
+#define BITS_MGQ_FIFO_PG_SIZE \
+ (BIT_MASK_MGQ_FIFO_PG_SIZE << BIT_SHIFT_MGQ_FIFO_PG_SIZE)
+#define BIT_CLEAR_MGQ_FIFO_PG_SIZE(x) ((x) & (~BITS_MGQ_FIFO_PG_SIZE))
+#define BIT_GET_MGQ_FIFO_PG_SIZE(x) \
+ (((x) >> BIT_SHIFT_MGQ_FIFO_PG_SIZE) & BIT_MASK_MGQ_FIFO_PG_SIZE)
+#define BIT_SET_MGQ_FIFO_PG_SIZE(x, v) \
+ (BIT_CLEAR_MGQ_FIFO_PG_SIZE(x) | BIT_MGQ_FIFO_PG_SIZE(v))
+#define BIT_SHIFT_MGQ_FIFO_RPTR 8
+#define BIT_MASK_MGQ_FIFO_RPTR 0x1f
+#define BIT_MGQ_FIFO_RPTR(x) \
+ (((x) & BIT_MASK_MGQ_FIFO_RPTR) << BIT_SHIFT_MGQ_FIFO_RPTR)
+#define BITS_MGQ_FIFO_RPTR (BIT_MASK_MGQ_FIFO_RPTR << BIT_SHIFT_MGQ_FIFO_RPTR)
+#define BIT_CLEAR_MGQ_FIFO_RPTR(x) ((x) & (~BITS_MGQ_FIFO_RPTR))
+#define BIT_GET_MGQ_FIFO_RPTR(x) \
+ (((x) >> BIT_SHIFT_MGQ_FIFO_RPTR) & BIT_MASK_MGQ_FIFO_RPTR)
+#define BIT_SET_MGQ_FIFO_RPTR(x, v) \
+ (BIT_CLEAR_MGQ_FIFO_RPTR(x) | BIT_MGQ_FIFO_RPTR(v))
-#define BIT_SHIFT_DDMACH3_SA 0
-#define BIT_MASK_DDMACH3_SA 0xffffffffL
-#define BIT_DDMACH3_SA(x) (((x) & BIT_MASK_DDMACH3_SA) << BIT_SHIFT_DDMACH3_SA)
-#define BIT_GET_DDMACH3_SA(x) (((x) >> BIT_SHIFT_DDMACH3_SA) & BIT_MASK_DDMACH3_SA)
+#define BIT_SHIFT_MGQ_FIFO_START_PG 0
+#define BIT_MASK_MGQ_FIFO_START_PG 0xfff
+#define BIT_MGQ_FIFO_START_PG(x) \
+ (((x) & BIT_MASK_MGQ_FIFO_START_PG) << BIT_SHIFT_MGQ_FIFO_START_PG)
+#define BITS_MGQ_FIFO_START_PG \
+ (BIT_MASK_MGQ_FIFO_START_PG << BIT_SHIFT_MGQ_FIFO_START_PG)
+#define BIT_CLEAR_MGQ_FIFO_START_PG(x) ((x) & (~BITS_MGQ_FIFO_START_PG))
+#define BIT_GET_MGQ_FIFO_START_PG(x) \
+ (((x) >> BIT_SHIFT_MGQ_FIFO_START_PG) & BIT_MASK_MGQ_FIFO_START_PG)
+#define BIT_SET_MGQ_FIFO_START_PG(x, v) \
+ (BIT_CLEAR_MGQ_FIFO_START_PG(x) | BIT_MGQ_FIFO_START_PG(v))
+#endif
-/* 2 REG_DDMA_CH3DA (Offset 0x1234) */
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_MGG_FIFO_INT (Offset 0x1474) */
-#define BIT_SHIFT_DDMACH3_DA 0
-#define BIT_MASK_DDMACH3_DA 0xffffffffL
-#define BIT_DDMACH3_DA(x) (((x) & BIT_MASK_DDMACH3_DA) << BIT_SHIFT_DDMACH3_DA)
-#define BIT_GET_DDMACH3_DA(x) (((x) >> BIT_SHIFT_DDMACH3_DA) & BIT_MASK_DDMACH3_DA)
+#define BIT_SHIFT_R_MGG_FIFO_INT_FLAG 16
+#define BIT_MASK_R_MGG_FIFO_INT_FLAG 0xffff
+#define BIT_R_MGG_FIFO_INT_FLAG(x) \
+ (((x) & BIT_MASK_R_MGG_FIFO_INT_FLAG) << BIT_SHIFT_R_MGG_FIFO_INT_FLAG)
+#define BITS_R_MGG_FIFO_INT_FLAG \
+ (BIT_MASK_R_MGG_FIFO_INT_FLAG << BIT_SHIFT_R_MGG_FIFO_INT_FLAG)
+#define BIT_CLEAR_R_MGG_FIFO_INT_FLAG(x) ((x) & (~BITS_R_MGG_FIFO_INT_FLAG))
+#define BIT_GET_R_MGG_FIFO_INT_FLAG(x) \
+ (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_FLAG) & BIT_MASK_R_MGG_FIFO_INT_FLAG)
+#define BIT_SET_R_MGG_FIFO_INT_FLAG(x, v) \
+ (BIT_CLEAR_R_MGG_FIFO_INT_FLAG(x) | BIT_R_MGG_FIFO_INT_FLAG(v))
+
+#define BIT_SHIFT_R_MGG_FIFO_INT_MASK 0
+#define BIT_MASK_R_MGG_FIFO_INT_MASK 0xffff
+#define BIT_R_MGG_FIFO_INT_MASK(x) \
+ (((x) & BIT_MASK_R_MGG_FIFO_INT_MASK) << BIT_SHIFT_R_MGG_FIFO_INT_MASK)
+#define BITS_R_MGG_FIFO_INT_MASK \
+ (BIT_MASK_R_MGG_FIFO_INT_MASK << BIT_SHIFT_R_MGG_FIFO_INT_MASK)
+#define BIT_CLEAR_R_MGG_FIFO_INT_MASK(x) ((x) & (~BITS_R_MGG_FIFO_INT_MASK))
+#define BIT_GET_R_MGG_FIFO_INT_MASK(x) \
+ (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_MASK) & BIT_MASK_R_MGG_FIFO_INT_MASK)
+#define BIT_SET_R_MGG_FIFO_INT_MASK(x, v) \
+ (BIT_CLEAR_R_MGG_FIFO_INT_MASK(x) | BIT_R_MGG_FIFO_INT_MASK(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MGQ_FIFO_RELEASE_INT_MASK (Offset 0x1474) */
+
+#define BIT_SHIFT_MGQ_FIFO_REL_INT_MASK 0
+#define BIT_MASK_MGQ_FIFO_REL_INT_MASK 0xffff
+#define BIT_MGQ_FIFO_REL_INT_MASK(x) \
+ (((x) & BIT_MASK_MGQ_FIFO_REL_INT_MASK) \
+ << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK)
+#define BITS_MGQ_FIFO_REL_INT_MASK \
+ (BIT_MASK_MGQ_FIFO_REL_INT_MASK << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK)
+#define BIT_CLEAR_MGQ_FIFO_REL_INT_MASK(x) ((x) & (~BITS_MGQ_FIFO_REL_INT_MASK))
+#define BIT_GET_MGQ_FIFO_REL_INT_MASK(x) \
+ (((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_MASK) & \
+ BIT_MASK_MGQ_FIFO_REL_INT_MASK)
+#define BIT_SET_MGQ_FIFO_REL_INT_MASK(x, v) \
+ (BIT_CLEAR_MGQ_FIFO_REL_INT_MASK(x) | BIT_MGQ_FIFO_REL_INT_MASK(v))
+
+/* 2 REG_MGQ_FIFO_RELEASE_INT_FLAG (Offset 0x1476) */
+
+#define BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG 0
+#define BIT_MASK_MGQ_FIFO_REL_INT_FLAG 0xffff
+#define BIT_MGQ_FIFO_REL_INT_FLAG(x) \
+ (((x) & BIT_MASK_MGQ_FIFO_REL_INT_FLAG) \
+ << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG)
+#define BITS_MGQ_FIFO_REL_INT_FLAG \
+ (BIT_MASK_MGQ_FIFO_REL_INT_FLAG << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG)
+#define BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG(x) ((x) & (~BITS_MGQ_FIFO_REL_INT_FLAG))
+#define BIT_GET_MGQ_FIFO_REL_INT_FLAG(x) \
+ (((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG) & \
+ BIT_MASK_MGQ_FIFO_REL_INT_FLAG)
+#define BIT_SET_MGQ_FIFO_REL_INT_FLAG(x, v) \
+ (BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG(x) | BIT_MGQ_FIFO_REL_INT_FLAG(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_MGG_FIFO_LIFETIME (Offset 0x1478) */
-/* 2 REG_DDMA_CH3CTRL (Offset 0x1238) */
+#define BIT_SHIFT_R_MGG_FIFO_LIFETIME 16
+#define BIT_MASK_R_MGG_FIFO_LIFETIME 0xffff
+#define BIT_R_MGG_FIFO_LIFETIME(x) \
+ (((x) & BIT_MASK_R_MGG_FIFO_LIFETIME) << BIT_SHIFT_R_MGG_FIFO_LIFETIME)
+#define BITS_R_MGG_FIFO_LIFETIME \
+ (BIT_MASK_R_MGG_FIFO_LIFETIME << BIT_SHIFT_R_MGG_FIFO_LIFETIME)
+#define BIT_CLEAR_R_MGG_FIFO_LIFETIME(x) ((x) & (~BITS_R_MGG_FIFO_LIFETIME))
+#define BIT_GET_R_MGG_FIFO_LIFETIME(x) \
+ (((x) >> BIT_SHIFT_R_MGG_FIFO_LIFETIME) & BIT_MASK_R_MGG_FIFO_LIFETIME)
+#define BIT_SET_R_MGG_FIFO_LIFETIME(x, v) \
+ (BIT_CLEAR_R_MGG_FIFO_LIFETIME(x) | BIT_R_MGG_FIFO_LIFETIME(v))
+
+#define BIT_SHIFT_R_MGG_FIFO_VALID_MAP 0
+#define BIT_MASK_R_MGG_FIFO_VALID_MAP 0xffff
+#define BIT_R_MGG_FIFO_VALID_MAP(x) \
+ (((x) & BIT_MASK_R_MGG_FIFO_VALID_MAP) \
+ << BIT_SHIFT_R_MGG_FIFO_VALID_MAP)
+#define BITS_R_MGG_FIFO_VALID_MAP \
+ (BIT_MASK_R_MGG_FIFO_VALID_MAP << BIT_SHIFT_R_MGG_FIFO_VALID_MAP)
+#define BIT_CLEAR_R_MGG_FIFO_VALID_MAP(x) ((x) & (~BITS_R_MGG_FIFO_VALID_MAP))
+#define BIT_GET_R_MGG_FIFO_VALID_MAP(x) \
+ (((x) >> BIT_SHIFT_R_MGG_FIFO_VALID_MAP) & \
+ BIT_MASK_R_MGG_FIFO_VALID_MAP)
+#define BIT_SET_R_MGG_FIFO_VALID_MAP(x, v) \
+ (BIT_CLEAR_R_MGG_FIFO_VALID_MAP(x) | BIT_R_MGG_FIFO_VALID_MAP(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MGQ_FIFO_VALID_MAP (Offset 0x1478) */
+
+#define BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP 0
+#define BIT_MASK_MGQ_FIFO_PKT_VALID_MAP 0xffff
+#define BIT_MGQ_FIFO_PKT_VALID_MAP(x) \
+ (((x) & BIT_MASK_MGQ_FIFO_PKT_VALID_MAP) \
+ << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP)
+#define BITS_MGQ_FIFO_PKT_VALID_MAP \
+ (BIT_MASK_MGQ_FIFO_PKT_VALID_MAP << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP)
+#define BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP(x) \
+ ((x) & (~BITS_MGQ_FIFO_PKT_VALID_MAP))
+#define BIT_GET_MGQ_FIFO_PKT_VALID_MAP(x) \
+ (((x) >> BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP) & \
+ BIT_MASK_MGQ_FIFO_PKT_VALID_MAP)
+#define BIT_SET_MGQ_FIFO_PKT_VALID_MAP(x, v) \
+ (BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP(x) | BIT_MGQ_FIFO_PKT_VALID_MAP(v))
+
+/* 2 REG_MGQ_FIFO_LIFETIME (Offset 0x147A) */
+
+#define BIT_SHIFT_MGQ_FIFO_LIFETIME 0
+#define BIT_MASK_MGQ_FIFO_LIFETIME 0xffff
+#define BIT_MGQ_FIFO_LIFETIME(x) \
+ (((x) & BIT_MASK_MGQ_FIFO_LIFETIME) << BIT_SHIFT_MGQ_FIFO_LIFETIME)
+#define BITS_MGQ_FIFO_LIFETIME \
+ (BIT_MASK_MGQ_FIFO_LIFETIME << BIT_SHIFT_MGQ_FIFO_LIFETIME)
+#define BIT_CLEAR_MGQ_FIFO_LIFETIME(x) ((x) & (~BITS_MGQ_FIFO_LIFETIME))
+#define BIT_GET_MGQ_FIFO_LIFETIME(x) \
+ (((x) >> BIT_SHIFT_MGQ_FIFO_LIFETIME) & BIT_MASK_MGQ_FIFO_LIFETIME)
+#define BIT_SET_MGQ_FIFO_LIFETIME(x, v) \
+ (BIT_CLEAR_MGQ_FIFO_LIFETIME(x) | BIT_MGQ_FIFO_LIFETIME(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_DDMACH3_OWN BIT(31)
-#define BIT_DDMACH3_CHKSUM_EN BIT(29)
-#define BIT_DDMACH3_DA_W_DISABLE BIT(28)
-#define BIT_DDMACH3_CHKSUM_STS BIT(27)
-#define BIT_DDMACH3_DDMA_MODE BIT(26)
-#define BIT_DDMACH3_RESET_CHKSUM_STS BIT(25)
-#define BIT_DDMACH3_CHKSUM_CONT BIT(24)
+/* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET (Offset 0x147C) */
-#define BIT_SHIFT_DDMACH3_DLEN 0
-#define BIT_MASK_DDMACH3_DLEN 0x3ffff
-#define BIT_DDMACH3_DLEN(x) (((x) & BIT_MASK_DDMACH3_DLEN) << BIT_SHIFT_DDMACH3_DLEN)
-#define BIT_GET_DDMACH3_DLEN(x) (((x) >> BIT_SHIFT_DDMACH3_DLEN) & BIT_MASK_DDMACH3_DLEN)
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET 0x7f
+#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x) \
+ (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET)
+#define BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET \
+ (BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x) \
+ ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x) \
+ (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) & \
+ BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x, v) \
+ (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x) | \
+ BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_PKT_TRANS (Offset 0x1480) */
+
+#define BIT_SHIFT_IE_DESC_OFFSET 16
+#define BIT_MASK_IE_DESC_OFFSET 0x1ff
+#define BIT_IE_DESC_OFFSET(x) \
+ (((x) & BIT_MASK_IE_DESC_OFFSET) << BIT_SHIFT_IE_DESC_OFFSET)
+#define BITS_IE_DESC_OFFSET \
+ (BIT_MASK_IE_DESC_OFFSET << BIT_SHIFT_IE_DESC_OFFSET)
+#define BIT_CLEAR_IE_DESC_OFFSET(x) ((x) & (~BITS_IE_DESC_OFFSET))
+#define BIT_GET_IE_DESC_OFFSET(x) \
+ (((x) >> BIT_SHIFT_IE_DESC_OFFSET) & BIT_MASK_IE_DESC_OFFSET)
+#define BIT_SET_IE_DESC_OFFSET(x, v) \
+ (BIT_CLEAR_IE_DESC_OFFSET(x) | BIT_IE_DESC_OFFSET(v))
+
+#define BIT_DIS_FWCMD_PATH_ERRCHK BIT(13)
+#define BIT_MAC_HDR_CONVERT_EN BIT(12)
+#define BIT_TXDESC_TRANS_EN BIT(8)
+#define BIT_PKT_TRANS_ERRINT_EN BIT(7)
+
+#define BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL 4
+#define BIT_MASK_PKT_TRANS_ERR_MACID_SEL 0x3
+#define BIT_PKT_TRANS_ERR_MACID_SEL(x) \
+ (((x) & BIT_MASK_PKT_TRANS_ERR_MACID_SEL) \
+ << BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL)
+#define BITS_PKT_TRANS_ERR_MACID_SEL \
+ (BIT_MASK_PKT_TRANS_ERR_MACID_SEL << BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL)
+#define BIT_CLEAR_PKT_TRANS_ERR_MACID_SEL(x) \
+ ((x) & (~BITS_PKT_TRANS_ERR_MACID_SEL))
+#define BIT_GET_PKT_TRANS_ERR_MACID_SEL(x) \
+ (((x) >> BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL) & \
+ BIT_MASK_PKT_TRANS_ERR_MACID_SEL)
+#define BIT_SET_PKT_TRANS_ERR_MACID_SEL(x, v) \
+ (BIT_CLEAR_PKT_TRANS_ERR_MACID_SEL(x) | BIT_PKT_TRANS_ERR_MACID_SEL(v))
+
+#define BIT_PKT_TRANS_IEINIT_ERR BIT(3)
+#define BIT_PKT_TRANS_IENUM_ERR BIT(2)
+#define BIT_PKT_TRANS_IECNT_ERR1 BIT(1)
+#define BIT_PKT_TRANS_IECNT_ERR0 BIT(0)
+
+/* 2 REG_SHCUT_LLC_ETH_TYPE1 (Offset 0x1488) */
+
+#define BIT_SHIFT_SHCUT_MHDR_OFFSET 16
+#define BIT_MASK_SHCUT_MHDR_OFFSET 0x1ff
+#define BIT_SHCUT_MHDR_OFFSET(x) \
+ (((x) & BIT_MASK_SHCUT_MHDR_OFFSET) << BIT_SHIFT_SHCUT_MHDR_OFFSET)
+#define BITS_SHCUT_MHDR_OFFSET \
+ (BIT_MASK_SHCUT_MHDR_OFFSET << BIT_SHIFT_SHCUT_MHDR_OFFSET)
+#define BIT_CLEAR_SHCUT_MHDR_OFFSET(x) ((x) & (~BITS_SHCUT_MHDR_OFFSET))
+#define BIT_GET_SHCUT_MHDR_OFFSET(x) \
+ (((x) >> BIT_SHIFT_SHCUT_MHDR_OFFSET) & BIT_MASK_SHCUT_MHDR_OFFSET)
+#define BIT_SET_SHCUT_MHDR_OFFSET(x, v) \
+ (BIT_CLEAR_SHCUT_MHDR_OFFSET(x) | BIT_SHCUT_MHDR_OFFSET(v))
+
+#define BIT_SHIFT_PKT_TRANS_ERR_MACID 0
+#define BIT_MASK_PKT_TRANS_ERR_MACID 0xffffffffL
+#define BIT_PKT_TRANS_ERR_MACID(x) \
+ (((x) & BIT_MASK_PKT_TRANS_ERR_MACID) << BIT_SHIFT_PKT_TRANS_ERR_MACID)
+#define BITS_PKT_TRANS_ERR_MACID \
+ (BIT_MASK_PKT_TRANS_ERR_MACID << BIT_SHIFT_PKT_TRANS_ERR_MACID)
+#define BIT_CLEAR_PKT_TRANS_ERR_MACID(x) ((x) & (~BITS_PKT_TRANS_ERR_MACID))
+#define BIT_GET_PKT_TRANS_ERR_MACID(x) \
+ (((x) >> BIT_SHIFT_PKT_TRANS_ERR_MACID) & BIT_MASK_PKT_TRANS_ERR_MACID)
+#define BIT_SET_PKT_TRANS_ERR_MACID(x, v) \
+ (BIT_CLEAR_PKT_TRANS_ERR_MACID(x) | BIT_PKT_TRANS_ERR_MACID(v))
+
+/* 2 REG_FWCMDQ_CTRL (Offset 0x14A0) */
+
+#define BIT_FW_RELEASEPKT_POLLING BIT(31)
+
+#define BIT_SHIFT_FWCMDQ_RELEASE_HEAD 16
+#define BIT_MASK_FWCMDQ_RELEASE_HEAD 0xfff
+#define BIT_FWCMDQ_RELEASE_HEAD(x) \
+ (((x) & BIT_MASK_FWCMDQ_RELEASE_HEAD) << BIT_SHIFT_FWCMDQ_RELEASE_HEAD)
+#define BITS_FWCMDQ_RELEASE_HEAD \
+ (BIT_MASK_FWCMDQ_RELEASE_HEAD << BIT_SHIFT_FWCMDQ_RELEASE_HEAD)
+#define BIT_CLEAR_FWCMDQ_RELEASE_HEAD(x) ((x) & (~BITS_FWCMDQ_RELEASE_HEAD))
+#define BIT_GET_FWCMDQ_RELEASE_HEAD(x) \
+ (((x) >> BIT_SHIFT_FWCMDQ_RELEASE_HEAD) & BIT_MASK_FWCMDQ_RELEASE_HEAD)
+#define BIT_SET_FWCMDQ_RELEASE_HEAD(x, v) \
+ (BIT_CLEAR_FWCMDQ_RELEASE_HEAD(x) | BIT_FWCMDQ_RELEASE_HEAD(v))
+
+#define BIT_FW_GETPKTT_POLLING BIT(15)
+
+#define BIT_SHIFT_FWCMDQ_H 0
+#define BIT_MASK_FWCMDQ_H 0xfff
+#define BIT_FWCMDQ_H(x) (((x) & BIT_MASK_FWCMDQ_H) << BIT_SHIFT_FWCMDQ_H)
+#define BITS_FWCMDQ_H (BIT_MASK_FWCMDQ_H << BIT_SHIFT_FWCMDQ_H)
+#define BIT_CLEAR_FWCMDQ_H(x) ((x) & (~BITS_FWCMDQ_H))
+#define BIT_GET_FWCMDQ_H(x) (((x) >> BIT_SHIFT_FWCMDQ_H) & BIT_MASK_FWCMDQ_H)
+#define BIT_SET_FWCMDQ_H(x, v) (BIT_CLEAR_FWCMDQ_H(x) | BIT_FWCMDQ_H(v))
+
+/* 2 REG_FWCMDQ_PAGE (Offset 0x14A4) */
+
+#define BIT_SHIFT_FWCMDQ_TOTAL_PAGE 16
+#define BIT_MASK_FWCMDQ_TOTAL_PAGE 0xfff
+#define BIT_FWCMDQ_TOTAL_PAGE(x) \
+ (((x) & BIT_MASK_FWCMDQ_TOTAL_PAGE) << BIT_SHIFT_FWCMDQ_TOTAL_PAGE)
+#define BITS_FWCMDQ_TOTAL_PAGE \
+ (BIT_MASK_FWCMDQ_TOTAL_PAGE << BIT_SHIFT_FWCMDQ_TOTAL_PAGE)
+#define BIT_CLEAR_FWCMDQ_TOTAL_PAGE(x) ((x) & (~BITS_FWCMDQ_TOTAL_PAGE))
+#define BIT_GET_FWCMDQ_TOTAL_PAGE(x) \
+ (((x) >> BIT_SHIFT_FWCMDQ_TOTAL_PAGE) & BIT_MASK_FWCMDQ_TOTAL_PAGE)
+#define BIT_SET_FWCMDQ_TOTAL_PAGE(x, v) \
+ (BIT_CLEAR_FWCMDQ_TOTAL_PAGE(x) | BIT_FWCMDQ_TOTAL_PAGE(v))
+
+#define BIT_SHIFT_FWCMDQ_QUEUE_PAGE 0
+#define BIT_MASK_FWCMDQ_QUEUE_PAGE 0xfff
+#define BIT_FWCMDQ_QUEUE_PAGE(x) \
+ (((x) & BIT_MASK_FWCMDQ_QUEUE_PAGE) << BIT_SHIFT_FWCMDQ_QUEUE_PAGE)
+#define BITS_FWCMDQ_QUEUE_PAGE \
+ (BIT_MASK_FWCMDQ_QUEUE_PAGE << BIT_SHIFT_FWCMDQ_QUEUE_PAGE)
+#define BIT_CLEAR_FWCMDQ_QUEUE_PAGE(x) ((x) & (~BITS_FWCMDQ_QUEUE_PAGE))
+#define BIT_GET_FWCMDQ_QUEUE_PAGE(x) \
+ (((x) >> BIT_SHIFT_FWCMDQ_QUEUE_PAGE) & BIT_MASK_FWCMDQ_QUEUE_PAGE)
+#define BIT_SET_FWCMDQ_QUEUE_PAGE(x, v) \
+ (BIT_CLEAR_FWCMDQ_QUEUE_PAGE(x) | BIT_FWCMDQ_QUEUE_PAGE(v))
+
+/* 2 REG_FWCMDQ_INFO (Offset 0x14A8) */
+
+#define BIT_FWCMD_READY BIT(31)
+#define BIT_FWCMDQ_OVERFLOW BIT(30)
+#define BIT_FWCMDQ_UNDERFLOW BIT(29)
+#define BIT_FWCMDQ_RELEASE_MISS BIT(28)
+
+#define BIT_SHIFT_FWCMDQ_TOTAL_PKT 16
+#define BIT_MASK_FWCMDQ_TOTAL_PKT 0xfff
+#define BIT_FWCMDQ_TOTAL_PKT(x) \
+ (((x) & BIT_MASK_FWCMDQ_TOTAL_PKT) << BIT_SHIFT_FWCMDQ_TOTAL_PKT)
+#define BITS_FWCMDQ_TOTAL_PKT \
+ (BIT_MASK_FWCMDQ_TOTAL_PKT << BIT_SHIFT_FWCMDQ_TOTAL_PKT)
+#define BIT_CLEAR_FWCMDQ_TOTAL_PKT(x) ((x) & (~BITS_FWCMDQ_TOTAL_PKT))
+#define BIT_GET_FWCMDQ_TOTAL_PKT(x) \
+ (((x) >> BIT_SHIFT_FWCMDQ_TOTAL_PKT) & BIT_MASK_FWCMDQ_TOTAL_PKT)
+#define BIT_SET_FWCMDQ_TOTAL_PKT(x, v) \
+ (BIT_CLEAR_FWCMDQ_TOTAL_PKT(x) | BIT_FWCMDQ_TOTAL_PKT(v))
+
+#define BIT_SHIFT_FWCMDQ_QUEUE_PKT 0
+#define BIT_MASK_FWCMDQ_QUEUE_PKT 0xfff
+#define BIT_FWCMDQ_QUEUE_PKT(x) \
+ (((x) & BIT_MASK_FWCMDQ_QUEUE_PKT) << BIT_SHIFT_FWCMDQ_QUEUE_PKT)
+#define BITS_FWCMDQ_QUEUE_PKT \
+ (BIT_MASK_FWCMDQ_QUEUE_PKT << BIT_SHIFT_FWCMDQ_QUEUE_PKT)
+#define BIT_CLEAR_FWCMDQ_QUEUE_PKT(x) ((x) & (~BITS_FWCMDQ_QUEUE_PKT))
+#define BIT_GET_FWCMDQ_QUEUE_PKT(x) \
+ (((x) >> BIT_SHIFT_FWCMDQ_QUEUE_PKT) & BIT_MASK_FWCMDQ_QUEUE_PKT)
+#define BIT_SET_FWCMDQ_QUEUE_PKT(x, v) \
+ (BIT_CLEAR_FWCMDQ_QUEUE_PKT(x) | BIT_FWCMDQ_QUEUE_PKT(v))
+
+/* 2 REG_FWCMDQ_HOLD_PKTNUM (Offset 0x14AC) */
+
+#define BIT_SHIFT_FWCMDQ_HOLD__PKTNUM 0
+#define BIT_MASK_FWCMDQ_HOLD__PKTNUM 0xfff
+#define BIT_FWCMDQ_HOLD__PKTNUM(x) \
+ (((x) & BIT_MASK_FWCMDQ_HOLD__PKTNUM) << BIT_SHIFT_FWCMDQ_HOLD__PKTNUM)
+#define BITS_FWCMDQ_HOLD__PKTNUM \
+ (BIT_MASK_FWCMDQ_HOLD__PKTNUM << BIT_SHIFT_FWCMDQ_HOLD__PKTNUM)
+#define BIT_CLEAR_FWCMDQ_HOLD__PKTNUM(x) ((x) & (~BITS_FWCMDQ_HOLD__PKTNUM))
+#define BIT_GET_FWCMDQ_HOLD__PKTNUM(x) \
+ (((x) >> BIT_SHIFT_FWCMDQ_HOLD__PKTNUM) & BIT_MASK_FWCMDQ_HOLD__PKTNUM)
+#define BIT_SET_FWCMDQ_HOLD__PKTNUM(x, v) \
+ (BIT_CLEAR_FWCMDQ_HOLD__PKTNUM(x) | BIT_FWCMDQ_HOLD__PKTNUM(v))
+
+/* 2 REG_MU_TX_CTRL (Offset 0x14C0) */
+
+#define BIT_SEARCH_DONE_RDY BIT(31)
+#define BIT_MU_EN BIT(30)
+#define BIT_MU_SECONDARY_WAITMODE_EN BIT(29)
+#define BIT_MU_BB_SCORE_EN BIT(28)
+#define BIT_MU_SECONDARY_ANT_COUNT_EN BIT(27)
+#define BIT_MUARB_SEARCH_ERR_EN BIT(26)
+
+#define BIT_SHIFT_DIS_SU_TXBF 16
+#define BIT_MASK_DIS_SU_TXBF 0x3f
+#define BIT_DIS_SU_TXBF(x) \
+ (((x) & BIT_MASK_DIS_SU_TXBF) << BIT_SHIFT_DIS_SU_TXBF)
+#define BITS_DIS_SU_TXBF (BIT_MASK_DIS_SU_TXBF << BIT_SHIFT_DIS_SU_TXBF)
+#define BIT_CLEAR_DIS_SU_TXBF(x) ((x) & (~BITS_DIS_SU_TXBF))
+#define BIT_GET_DIS_SU_TXBF(x) \
+ (((x) >> BIT_SHIFT_DIS_SU_TXBF) & BIT_MASK_DIS_SU_TXBF)
+#define BIT_SET_DIS_SU_TXBF(x, v) \
+ (BIT_CLEAR_DIS_SU_TXBF(x) | BIT_DIS_SU_TXBF(v))
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+/* 2 REG_MU_TX_CTL (Offset 0x14C0) */
-/* 2 REG_DDMA_CH4SA (Offset 0x1240) */
+#define BIT_R_MU_P1_WAIT_STATE_EN BIT(16)
+#endif
-#define BIT_SHIFT_DDMACH4_SA 0
-#define BIT_MASK_DDMACH4_SA 0xffffffffL
-#define BIT_DDMACH4_SA(x) (((x) & BIT_MASK_DDMACH4_SA) << BIT_SHIFT_DDMACH4_SA)
-#define BIT_GET_DDMACH4_SA(x) (((x) >> BIT_SHIFT_DDMACH4_SA) & BIT_MASK_DDMACH4_SA)
+#if (HALMAC_8814B_SUPPORT)
+/* 2 REG_MU_TX_CTRL (Offset 0x14C0) */
-/* 2 REG_DDMA_CH4DA (Offset 0x1244) */
+#define BIT_SHIFT_MU_RL 12
+#define BIT_MASK_MU_RL 0xf
+#define BIT_MU_RL(x) (((x) & BIT_MASK_MU_RL) << BIT_SHIFT_MU_RL)
+#define BITS_MU_RL (BIT_MASK_MU_RL << BIT_SHIFT_MU_RL)
+#define BIT_CLEAR_MU_RL(x) ((x) & (~BITS_MU_RL))
+#define BIT_GET_MU_RL(x) (((x) >> BIT_SHIFT_MU_RL) & BIT_MASK_MU_RL)
+#define BIT_SET_MU_RL(x, v) (BIT_CLEAR_MU_RL(x) | BIT_MU_RL(v))
+#endif
-#define BIT_SHIFT_DDMACH4_DA 0
-#define BIT_MASK_DDMACH4_DA 0xffffffffL
-#define BIT_DDMACH4_DA(x) (((x) & BIT_MASK_DDMACH4_DA) << BIT_SHIFT_DDMACH4_DA)
-#define BIT_GET_DDMACH4_DA(x) (((x) >> BIT_SHIFT_DDMACH4_DA) & BIT_MASK_DDMACH4_DA)
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+/* 2 REG_MU_TX_CTL (Offset 0x14C0) */
-/* 2 REG_DDMA_CH4CTRL (Offset 0x1248) */
+#define BIT_SHIFT_R_MU_RL 12
+#define BIT_MASK_R_MU_RL 0xf
+#define BIT_R_MU_RL(x) (((x) & BIT_MASK_R_MU_RL) << BIT_SHIFT_R_MU_RL)
+#define BITS_R_MU_RL (BIT_MASK_R_MU_RL << BIT_SHIFT_R_MU_RL)
+#define BIT_CLEAR_R_MU_RL(x) ((x) & (~BITS_R_MU_RL))
+#define BIT_GET_R_MU_RL(x) (((x) >> BIT_SHIFT_R_MU_RL) & BIT_MASK_R_MU_RL)
+#define BIT_SET_R_MU_RL(x, v) (BIT_CLEAR_R_MU_RL(x) | BIT_R_MU_RL(v))
-#define BIT_DDMACH4_OWN BIT(31)
-#define BIT_DDMACH4_CHKSUM_EN BIT(29)
-#define BIT_DDMACH4_DA_W_DISABLE BIT(28)
-#define BIT_DDMACH4_CHKSUM_STS BIT(27)
-#define BIT_DDMACH4_DDMA_MODE BIT(26)
-#define BIT_DDMACH4_RESET_CHKSUM_STS BIT(25)
-#define BIT_DDMACH4_CHKSUM_CONT BIT(24)
+#define BIT_R_FORCE_P1_RATEDOWN BIT(11)
-#define BIT_SHIFT_DDMACH4_DLEN 0
-#define BIT_MASK_DDMACH4_DLEN 0x3ffff
-#define BIT_DDMACH4_DLEN(x) (((x) & BIT_MASK_DDMACH4_DLEN) << BIT_SHIFT_DDMACH4_DLEN)
-#define BIT_GET_DDMACH4_DLEN(x) (((x) >> BIT_SHIFT_DDMACH4_DLEN) & BIT_MASK_DDMACH4_DLEN)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_DDMA_CH5SA (Offset 0x1250) */
+/* 2 REG_MU_TX_CTRL (Offset 0x14C0) */
+#define BIT_SHIFT_MU_TAB_SEL 8
+#define BIT_MASK_MU_TAB_SEL 0xf
+#define BIT_MU_TAB_SEL(x) (((x) & BIT_MASK_MU_TAB_SEL) << BIT_SHIFT_MU_TAB_SEL)
+#define BITS_MU_TAB_SEL (BIT_MASK_MU_TAB_SEL << BIT_SHIFT_MU_TAB_SEL)
+#define BIT_CLEAR_MU_TAB_SEL(x) ((x) & (~BITS_MU_TAB_SEL))
+#define BIT_GET_MU_TAB_SEL(x) \
+ (((x) >> BIT_SHIFT_MU_TAB_SEL) & BIT_MASK_MU_TAB_SEL)
+#define BIT_SET_MU_TAB_SEL(x, v) (BIT_CLEAR_MU_TAB_SEL(x) | BIT_MU_TAB_SEL(v))
-#define BIT_SHIFT_DDMACH5_SA 0
-#define BIT_MASK_DDMACH5_SA 0xffffffffL
-#define BIT_DDMACH5_SA(x) (((x) & BIT_MASK_DDMACH5_SA) << BIT_SHIFT_DDMACH5_SA)
-#define BIT_GET_DDMACH5_SA(x) (((x) >> BIT_SHIFT_DDMACH5_SA) & BIT_MASK_DDMACH5_SA)
+#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_DDMA_CH5DA (Offset 0x1254) */
+/* 2 REG_MU_TX_CTL (Offset 0x14C0) */
+#define BIT_SHIFT_R_MU_TAB_SEL 8
+#define BIT_MASK_R_MU_TAB_SEL 0x7
+#define BIT_R_MU_TAB_SEL(x) \
+ (((x) & BIT_MASK_R_MU_TAB_SEL) << BIT_SHIFT_R_MU_TAB_SEL)
+#define BITS_R_MU_TAB_SEL (BIT_MASK_R_MU_TAB_SEL << BIT_SHIFT_R_MU_TAB_SEL)
+#define BIT_CLEAR_R_MU_TAB_SEL(x) ((x) & (~BITS_R_MU_TAB_SEL))
+#define BIT_GET_R_MU_TAB_SEL(x) \
+ (((x) >> BIT_SHIFT_R_MU_TAB_SEL) & BIT_MASK_R_MU_TAB_SEL)
+#define BIT_SET_R_MU_TAB_SEL(x, v) \
+ (BIT_CLEAR_R_MU_TAB_SEL(x) | BIT_R_MU_TAB_SEL(v))
-#define BIT_SHIFT_DDMACH5_DA 0
-#define BIT_MASK_DDMACH5_DA 0xffffffffL
-#define BIT_DDMACH5_DA(x) (((x) & BIT_MASK_DDMACH5_DA) << BIT_SHIFT_DDMACH5_DA)
-#define BIT_GET_DDMACH5_DA(x) (((x) >> BIT_SHIFT_DDMACH5_DA) & BIT_MASK_DDMACH5_DA)
+#define BIT_R_EN_MU_MIMO BIT(7)
+#endif
-/* 2 REG_REG_DDMA_CH5CTRL (Offset 0x1258) */
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_DDMACH5_OWN BIT(31)
-#define BIT_DDMACH5_CHKSUM_EN BIT(29)
-#define BIT_DDMACH5_DA_W_DISABLE BIT(28)
-#define BIT_DDMACH5_CHKSUM_STS BIT(27)
-#define BIT_DDMACH5_DDMA_MODE BIT(26)
-#define BIT_DDMACH5_RESET_CHKSUM_STS BIT(25)
-#define BIT_DDMACH5_CHKSUM_CONT BIT(24)
+/* 2 REG_MU_TX_CTL (Offset 0x14C0) */
-#define BIT_SHIFT_DDMACH5_DLEN 0
-#define BIT_MASK_DDMACH5_DLEN 0x3ffff
-#define BIT_DDMACH5_DLEN(x) (((x) & BIT_MASK_DDMACH5_DLEN) << BIT_SHIFT_DDMACH5_DLEN)
-#define BIT_GET_DDMACH5_DLEN(x) (((x) >> BIT_SHIFT_DDMACH5_DLEN) & BIT_MASK_DDMACH5_DLEN)
+#define BIT_R_EN_REVERS_GTAB BIT(6)
+#endif
-/* 2 REG_DDMA_INT_MSK (Offset 0x12E0) */
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_DDMACH5_MSK BIT(5)
-#define BIT_DDMACH4_MSK BIT(4)
-#define BIT_DDMACH3_MSK BIT(3)
-#define BIT_DDMACH2_MSK BIT(2)
-#define BIT_DDMACH1_MSK BIT(1)
-#define BIT_DDMACH0_MSK BIT(0)
+/* 2 REG_MU_TX_CTRL (Offset 0x14C0) */
-/* 2 REG_DDMA_CHSTATUS (Offset 0x12E8) */
+#define BIT_SHIFT_MU_TAB_VALID 0
+#define BIT_MASK_MU_TAB_VALID 0x3f
+#define BIT_MU_TAB_VALID(x) \
+ (((x) & BIT_MASK_MU_TAB_VALID) << BIT_SHIFT_MU_TAB_VALID)
+#define BITS_MU_TAB_VALID (BIT_MASK_MU_TAB_VALID << BIT_SHIFT_MU_TAB_VALID)
+#define BIT_CLEAR_MU_TAB_VALID(x) ((x) & (~BITS_MU_TAB_VALID))
+#define BIT_GET_MU_TAB_VALID(x) \
+ (((x) >> BIT_SHIFT_MU_TAB_VALID) & BIT_MASK_MU_TAB_VALID)
+#define BIT_SET_MU_TAB_VALID(x, v) \
+ (BIT_CLEAR_MU_TAB_VALID(x) | BIT_MU_TAB_VALID(v))
-#define BIT_DDMACH5_BUSY BIT(5)
-#define BIT_DDMACH4_BUSY BIT(4)
-#define BIT_DDMACH3_BUSY BIT(3)
-#define BIT_DDMACH2_BUSY BIT(2)
-#define BIT_DDMACH1_BUSY BIT(1)
-#define BIT_DDMACH0_BUSY BIT(0)
+#endif
-/* 2 REG_DDMA_CHKSUM (Offset 0x12F0) */
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+/* 2 REG_MU_TX_CTL (Offset 0x14C0) */
-#define BIT_SHIFT_IDDMA0_CHKSUM 0
-#define BIT_MASK_IDDMA0_CHKSUM 0xffff
-#define BIT_IDDMA0_CHKSUM(x) (((x) & BIT_MASK_IDDMA0_CHKSUM) << BIT_SHIFT_IDDMA0_CHKSUM)
-#define BIT_GET_IDDMA0_CHKSUM(x) (((x) >> BIT_SHIFT_IDDMA0_CHKSUM) & BIT_MASK_IDDMA0_CHKSUM)
+#define BIT_SHIFT_R_MU_TABLE_VALID 0
+#define BIT_MASK_R_MU_TABLE_VALID 0x3f
+#define BIT_R_MU_TABLE_VALID(x) \
+ (((x) & BIT_MASK_R_MU_TABLE_VALID) << BIT_SHIFT_R_MU_TABLE_VALID)
+#define BITS_R_MU_TABLE_VALID \
+ (BIT_MASK_R_MU_TABLE_VALID << BIT_SHIFT_R_MU_TABLE_VALID)
+#define BIT_CLEAR_R_MU_TABLE_VALID(x) ((x) & (~BITS_R_MU_TABLE_VALID))
+#define BIT_GET_R_MU_TABLE_VALID(x) \
+ (((x) >> BIT_SHIFT_R_MU_TABLE_VALID) & BIT_MASK_R_MU_TABLE_VALID)
+#define BIT_SET_R_MU_TABLE_VALID(x, v) \
+ (BIT_CLEAR_R_MU_TABLE_VALID(x) | BIT_R_MU_TABLE_VALID(v))
+
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_DDMA_MONITOR (Offset 0x12FC) */
+/* 2 REG_MU_STA_GID_VLD (Offset 0x14C4) */
-#define BIT_IDDMA0_PERMU_UNDERFLOW BIT(14)
-#define BIT_IDDMA0_FIFO_UNDERFLOW BIT(13)
-#define BIT_IDDMA0_FIFO_OVERFLOW BIT(12)
-#define BIT_ECRC_EN_V1 BIT(7)
-#define BIT_MDIO_RFLAG_V1 BIT(6)
-#define BIT_CH5_ERR BIT(5)
-#define BIT_MDIO_WFLAG_V1 BIT(5)
-#define BIT_CH4_ERR BIT(4)
-#define BIT_CH3_ERR BIT(3)
-#define BIT_CH2_ERR BIT(2)
-#define BIT_CH1_ERR BIT(1)
-#define BIT_CH0_ERR BIT(0)
+#define BIT_SHIFT_MU_STA_GTAB_VALID 0
+#define BIT_MASK_MU_STA_GTAB_VALID 0xffffffffL
+#define BIT_MU_STA_GTAB_VALID(x) \
+ (((x) & BIT_MASK_MU_STA_GTAB_VALID) << BIT_SHIFT_MU_STA_GTAB_VALID)
+#define BITS_MU_STA_GTAB_VALID \
+ (BIT_MASK_MU_STA_GTAB_VALID << BIT_SHIFT_MU_STA_GTAB_VALID)
+#define BIT_CLEAR_MU_STA_GTAB_VALID(x) ((x) & (~BITS_MU_STA_GTAB_VALID))
+#define BIT_GET_MU_STA_GTAB_VALID(x) \
+ (((x) >> BIT_SHIFT_MU_STA_GTAB_VALID) & BIT_MASK_MU_STA_GTAB_VALID)
+#define BIT_SET_MU_STA_GTAB_VALID(x, v) \
+ (BIT_CLEAR_MU_STA_GTAB_VALID(x) | BIT_MU_STA_GTAB_VALID(v))
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MU_STA_GID_VLD (Offset 0x14C4) */
+
+#define BIT_SHIFT_R_MU_STA_GTAB_VALID 0
+#define BIT_MASK_R_MU_STA_GTAB_VALID 0xffffffffL
+#define BIT_R_MU_STA_GTAB_VALID(x) \
+ (((x) & BIT_MASK_R_MU_STA_GTAB_VALID) << BIT_SHIFT_R_MU_STA_GTAB_VALID)
+#define BITS_R_MU_STA_GTAB_VALID \
+ (BIT_MASK_R_MU_STA_GTAB_VALID << BIT_SHIFT_R_MU_STA_GTAB_VALID)
+#define BIT_CLEAR_R_MU_STA_GTAB_VALID(x) ((x) & (~BITS_R_MU_STA_GTAB_VALID))
+#define BIT_GET_R_MU_STA_GTAB_VALID(x) \
+ (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID) & BIT_MASK_R_MU_STA_GTAB_VALID)
+#define BIT_SET_R_MU_STA_GTAB_VALID(x, v) \
+ (BIT_CLEAR_R_MU_STA_GTAB_VALID(x) | BIT_R_MU_STA_GTAB_VALID(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_MU_STA_USER_POS_INFO (Offset 0x14C8) */
+#define BIT_SHIFT_MU_STA_GTAB_POSITION_L 0
+#define BIT_MASK_MU_STA_GTAB_POSITION_L 0xffffffffL
+#define BIT_MU_STA_GTAB_POSITION_L(x) \
+ (((x) & BIT_MASK_MU_STA_GTAB_POSITION_L) \
+ << BIT_SHIFT_MU_STA_GTAB_POSITION_L)
+#define BITS_MU_STA_GTAB_POSITION_L \
+ (BIT_MASK_MU_STA_GTAB_POSITION_L << BIT_SHIFT_MU_STA_GTAB_POSITION_L)
+#define BIT_CLEAR_MU_STA_GTAB_POSITION_L(x) \
+ ((x) & (~BITS_MU_STA_GTAB_POSITION_L))
+#define BIT_GET_MU_STA_GTAB_POSITION_L(x) \
+ (((x) >> BIT_SHIFT_MU_STA_GTAB_POSITION_L) & \
+ BIT_MASK_MU_STA_GTAB_POSITION_L)
+#define BIT_SET_MU_STA_GTAB_POSITION_L(x, v) \
+ (BIT_CLEAR_MU_STA_GTAB_POSITION_L(x) | BIT_MU_STA_GTAB_POSITION_L(v))
-/* 2 REG_STC_INT_CS (Offset 0x1300) */
+#endif
-#define BIT_STC_INT_EN BIT(31)
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_STC_INT_FLAG 16
-#define BIT_MASK_STC_INT_FLAG 0xff
-#define BIT_STC_INT_FLAG(x) (((x) & BIT_MASK_STC_INT_FLAG) << BIT_SHIFT_STC_INT_FLAG)
-#define BIT_GET_STC_INT_FLAG(x) (((x) >> BIT_SHIFT_STC_INT_FLAG) & BIT_MASK_STC_INT_FLAG)
+/* 2 REG_MU_STA_USER_POS_INFO (Offset 0x14C8) */
+#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_L 0
+#define BIT_MASK_R_MU_STA_GTAB_POSITION_L 0xffffffffL
+#define BIT_R_MU_STA_GTAB_POSITION_L(x) \
+ (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_L) \
+ << BIT_SHIFT_R_MU_STA_GTAB_POSITION_L)
+#define BITS_R_MU_STA_GTAB_POSITION_L \
+ (BIT_MASK_R_MU_STA_GTAB_POSITION_L \
+ << BIT_SHIFT_R_MU_STA_GTAB_POSITION_L)
+#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_L(x) \
+ ((x) & (~BITS_R_MU_STA_GTAB_POSITION_L))
+#define BIT_GET_R_MU_STA_GTAB_POSITION_L(x) \
+ (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_L) & \
+ BIT_MASK_R_MU_STA_GTAB_POSITION_L)
+#define BIT_SET_R_MU_STA_GTAB_POSITION_L(x, v) \
+ (BIT_CLEAR_R_MU_STA_GTAB_POSITION_L(x) | \
+ BIT_R_MU_STA_GTAB_POSITION_L(v))
-#define BIT_SHIFT_STC_INT_IDX 8
-#define BIT_MASK_STC_INT_IDX 0x7
-#define BIT_STC_INT_IDX(x) (((x) & BIT_MASK_STC_INT_IDX) << BIT_SHIFT_STC_INT_IDX)
-#define BIT_GET_STC_INT_IDX(x) (((x) >> BIT_SHIFT_STC_INT_IDX) & BIT_MASK_STC_INT_IDX)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_STC_INT_REALTIME_CS 0
-#define BIT_MASK_STC_INT_REALTIME_CS 0x3f
-#define BIT_STC_INT_REALTIME_CS(x) (((x) & BIT_MASK_STC_INT_REALTIME_CS) << BIT_SHIFT_STC_INT_REALTIME_CS)
-#define BIT_GET_STC_INT_REALTIME_CS(x) (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS) & BIT_MASK_STC_INT_REALTIME_CS)
+/* 2 REG_MU_STA_USER_POS_INFO_H (Offset 0x14CC) */
+#define BIT_SHIFT_MU_STA_GTAB_POSITION_H 0
+#define BIT_MASK_MU_STA_GTAB_POSITION_H 0xffffffffL
+#define BIT_MU_STA_GTAB_POSITION_H(x) \
+ (((x) & BIT_MASK_MU_STA_GTAB_POSITION_H) \
+ << BIT_SHIFT_MU_STA_GTAB_POSITION_H)
+#define BITS_MU_STA_GTAB_POSITION_H \
+ (BIT_MASK_MU_STA_GTAB_POSITION_H << BIT_SHIFT_MU_STA_GTAB_POSITION_H)
+#define BIT_CLEAR_MU_STA_GTAB_POSITION_H(x) \
+ ((x) & (~BITS_MU_STA_GTAB_POSITION_H))
+#define BIT_GET_MU_STA_GTAB_POSITION_H(x) \
+ (((x) >> BIT_SHIFT_MU_STA_GTAB_POSITION_H) & \
+ BIT_MASK_MU_STA_GTAB_POSITION_H)
+#define BIT_SET_MU_STA_GTAB_POSITION_H(x, v) \
+ (BIT_CLEAR_MU_STA_GTAB_POSITION_H(x) | BIT_MU_STA_GTAB_POSITION_H(v))
-/* 2 REG_ST_INT_CFG (Offset 0x1304) */
+#endif
-#define BIT_STC_INT_GRP_EN BIT(31)
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MU_STA_USER_POS_INFO_H (Offset 0x14CC) */
+
+#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_H 0
+#define BIT_MASK_R_MU_STA_GTAB_POSITION_H 0xffffffffL
+#define BIT_R_MU_STA_GTAB_POSITION_H(x) \
+ (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_H) \
+ << BIT_SHIFT_R_MU_STA_GTAB_POSITION_H)
+#define BITS_R_MU_STA_GTAB_POSITION_H \
+ (BIT_MASK_R_MU_STA_GTAB_POSITION_H \
+ << BIT_SHIFT_R_MU_STA_GTAB_POSITION_H)
+#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_H(x) \
+ ((x) & (~BITS_R_MU_STA_GTAB_POSITION_H))
+#define BIT_GET_R_MU_STA_GTAB_POSITION_H(x) \
+ (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_H) & \
+ BIT_MASK_R_MU_STA_GTAB_POSITION_H)
+#define BIT_SET_R_MU_STA_GTAB_POSITION_H(x, v) \
+ (BIT_CLEAR_R_MU_STA_GTAB_POSITION_H(x) | \
+ BIT_R_MU_STA_GTAB_POSITION_H(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_STC_INT_EXPECT_LS 8
-#define BIT_MASK_STC_INT_EXPECT_LS 0x3f
-#define BIT_STC_INT_EXPECT_LS(x) (((x) & BIT_MASK_STC_INT_EXPECT_LS) << BIT_SHIFT_STC_INT_EXPECT_LS)
-#define BIT_GET_STC_INT_EXPECT_LS(x) (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS) & BIT_MASK_STC_INT_EXPECT_LS)
+/* 2 REG_MU_TRX_DBG_CNT (Offset 0x14D0) */
+#define BIT_MU_DNGCNT_RST BIT(20)
-#define BIT_SHIFT_STC_INT_EXPECT_CS 0
-#define BIT_MASK_STC_INT_EXPECT_CS 0x3f
-#define BIT_STC_INT_EXPECT_CS(x) (((x) & BIT_MASK_STC_INT_EXPECT_CS) << BIT_SHIFT_STC_INT_EXPECT_CS)
-#define BIT_GET_STC_INT_EXPECT_CS(x) (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS) & BIT_MASK_STC_INT_EXPECT_CS)
+#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-/* 2 REG_CMU_DLY_CTRL (Offset 0x1310) */
+/* 2 REG_MU_TRX_DBG_CNT (Offset 0x14D0) */
-#define BIT_CMU_DLY_EN BIT(31)
-#define BIT_CMU_DLY_MODE BIT(30)
+#define BIT_SHIFT_MU_DBGCNT_SEL 16
+#define BIT_MASK_MU_DBGCNT_SEL 0xf
+#define BIT_MU_DBGCNT_SEL(x) \
+ (((x) & BIT_MASK_MU_DBGCNT_SEL) << BIT_SHIFT_MU_DBGCNT_SEL)
+#define BITS_MU_DBGCNT_SEL (BIT_MASK_MU_DBGCNT_SEL << BIT_SHIFT_MU_DBGCNT_SEL)
+#define BIT_CLEAR_MU_DBGCNT_SEL(x) ((x) & (~BITS_MU_DBGCNT_SEL))
+#define BIT_GET_MU_DBGCNT_SEL(x) \
+ (((x) >> BIT_SHIFT_MU_DBGCNT_SEL) & BIT_MASK_MU_DBGCNT_SEL)
+#define BIT_SET_MU_DBGCNT_SEL(x, v) \
+ (BIT_CLEAR_MU_DBGCNT_SEL(x) | BIT_MU_DBGCNT_SEL(v))
-#define BIT_SHIFT_CMU_DLY_PRE_DIV 0
-#define BIT_MASK_CMU_DLY_PRE_DIV 0xff
-#define BIT_CMU_DLY_PRE_DIV(x) (((x) & BIT_MASK_CMU_DLY_PRE_DIV) << BIT_SHIFT_CMU_DLY_PRE_DIV)
-#define BIT_GET_CMU_DLY_PRE_DIV(x) (((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV) & BIT_MASK_CMU_DLY_PRE_DIV)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-/* 2 REG_CMU_DLY_CFG (Offset 0x1314) */
+/* 2 REG_CHNL_INFO_CTRL (Offset 0x14D0) */
+#define BIT_CHNL_REF_RXNAV BIT(7)
+#define BIT_CHNL_REF_VBON BIT(6)
-#define BIT_SHIFT_CMU_DLY_LTR_A2I 24
-#define BIT_MASK_CMU_DLY_LTR_A2I 0xff
-#define BIT_CMU_DLY_LTR_A2I(x) (((x) & BIT_MASK_CMU_DLY_LTR_A2I) << BIT_SHIFT_CMU_DLY_LTR_A2I)
-#define BIT_GET_CMU_DLY_LTR_A2I(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I) & BIT_MASK_CMU_DLY_LTR_A2I)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_CMU_DLY_LTR_I2A 16
-#define BIT_MASK_CMU_DLY_LTR_I2A 0xff
-#define BIT_CMU_DLY_LTR_I2A(x) (((x) & BIT_MASK_CMU_DLY_LTR_I2A) << BIT_SHIFT_CMU_DLY_LTR_I2A)
-#define BIT_GET_CMU_DLY_LTR_I2A(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A) & BIT_MASK_CMU_DLY_LTR_I2A)
+/* 2 REG_CHNL_INFO_CTRL (Offset 0x14D0) */
+#define BIT_CHNL_REF_EDCCA BIT(5)
-#define BIT_SHIFT_CMU_DLY_LTR_IDLE 8
-#define BIT_MASK_CMU_DLY_LTR_IDLE 0xff
-#define BIT_CMU_DLY_LTR_IDLE(x) (((x) & BIT_MASK_CMU_DLY_LTR_IDLE) << BIT_SHIFT_CMU_DLY_LTR_IDLE)
-#define BIT_GET_CMU_DLY_LTR_IDLE(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE) & BIT_MASK_CMU_DLY_LTR_IDLE)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_CMU_DLY_LTR_ACT 0
-#define BIT_MASK_CMU_DLY_LTR_ACT 0xff
-#define BIT_CMU_DLY_LTR_ACT(x) (((x) & BIT_MASK_CMU_DLY_LTR_ACT) << BIT_SHIFT_CMU_DLY_LTR_ACT)
-#define BIT_GET_CMU_DLY_LTR_ACT(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT) & BIT_MASK_CMU_DLY_LTR_ACT)
+/* 2 REG_CHNL_INFO_CTRL (Offset 0x14D0) */
+#define BIT_CHNL_REF_EDCA BIT(5)
+#define BIT_CHNL_REF_CCA BIT(4)
-/* 2 REG_H2CQ_TXBD_DESA (Offset 0x1320) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_H2CQ_TXBD_DESA 0
-#define BIT_MASK_H2CQ_TXBD_DESA 0xffffffffffffffffL
-#define BIT_H2CQ_TXBD_DESA(x) (((x) & BIT_MASK_H2CQ_TXBD_DESA) << BIT_SHIFT_H2CQ_TXBD_DESA)
-#define BIT_GET_H2CQ_TXBD_DESA(x) (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA) & BIT_MASK_H2CQ_TXBD_DESA)
+/* 2 REG_CHNL_INFO_CTRL (Offset 0x14D0) */
+#define BIT_RST_CHNL_BUSY BIT(3)
+#define BIT_RST_CHNL_IDLE BIT(2)
+#define BIT_CHNL_INFO_RST BIT(1)
+#define BIT_ATM_AIRTIME_EN BIT(0)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_MU_TRX_DBG_CNT (Offset 0x14D0) */
+#define BIT_SHIFT_MU_DNGCNT 0
+#define BIT_MASK_MU_DNGCNT 0xffff
+#define BIT_MU_DNGCNT(x) (((x) & BIT_MASK_MU_DNGCNT) << BIT_SHIFT_MU_DNGCNT)
+#define BITS_MU_DNGCNT (BIT_MASK_MU_DNGCNT << BIT_SHIFT_MU_DNGCNT)
+#define BIT_CLEAR_MU_DNGCNT(x) ((x) & (~BITS_MU_DNGCNT))
+#define BIT_GET_MU_DNGCNT(x) (((x) >> BIT_SHIFT_MU_DNGCNT) & BIT_MASK_MU_DNGCNT)
+#define BIT_SET_MU_DNGCNT(x, v) (BIT_CLEAR_MU_DNGCNT(x) | BIT_MU_DNGCNT(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CHNL_IDLE_TIME (Offset 0x14D4) */
+
+#define BIT_SHIFT_CHNL_IDLE_TIME 0
+#define BIT_MASK_CHNL_IDLE_TIME 0xffffffffL
+#define BIT_CHNL_IDLE_TIME(x) \
+ (((x) & BIT_MASK_CHNL_IDLE_TIME) << BIT_SHIFT_CHNL_IDLE_TIME)
+#define BITS_CHNL_IDLE_TIME \
+ (BIT_MASK_CHNL_IDLE_TIME << BIT_SHIFT_CHNL_IDLE_TIME)
+#define BIT_CLEAR_CHNL_IDLE_TIME(x) ((x) & (~BITS_CHNL_IDLE_TIME))
+#define BIT_GET_CHNL_IDLE_TIME(x) \
+ (((x) >> BIT_SHIFT_CHNL_IDLE_TIME) & BIT_MASK_CHNL_IDLE_TIME)
+#define BIT_SET_CHNL_IDLE_TIME(x, v) \
+ (BIT_CLEAR_CHNL_IDLE_TIME(x) | BIT_CHNL_IDLE_TIME(v))
+
+/* 2 REG_CHNL_BUSY_TIME (Offset 0x14D8) */
+
+#define BIT_SHIFT_CHNL_BUSY_TIME 0
+#define BIT_MASK_CHNL_BUSY_TIME 0xffffffffL
+#define BIT_CHNL_BUSY_TIME(x) \
+ (((x) & BIT_MASK_CHNL_BUSY_TIME) << BIT_SHIFT_CHNL_BUSY_TIME)
+#define BITS_CHNL_BUSY_TIME \
+ (BIT_MASK_CHNL_BUSY_TIME << BIT_SHIFT_CHNL_BUSY_TIME)
+#define BIT_CLEAR_CHNL_BUSY_TIME(x) ((x) & (~BITS_CHNL_BUSY_TIME))
+#define BIT_GET_CHNL_BUSY_TIME(x) \
+ (((x) >> BIT_SHIFT_CHNL_BUSY_TIME) & BIT_MASK_CHNL_BUSY_TIME)
+#define BIT_SET_CHNL_BUSY_TIME(x, v) \
+ (BIT_CLEAR_CHNL_BUSY_TIME(x) | BIT_CHNL_BUSY_TIME(v))
+
+#define BIT_SHIFT_BW_CFG 0
+#define BIT_MASK_BW_CFG 0x3
+#define BIT_BW_CFG(x) (((x) & BIT_MASK_BW_CFG) << BIT_SHIFT_BW_CFG)
+#define BITS_BW_CFG (BIT_MASK_BW_CFG << BIT_SHIFT_BW_CFG)
+#define BIT_CLEAR_BW_CFG(x) ((x) & (~BITS_BW_CFG))
+#define BIT_GET_BW_CFG(x) (((x) >> BIT_SHIFT_BW_CFG) & BIT_MASK_BW_CFG)
+#define BIT_SET_BW_CFG(x, v) (BIT_CLEAR_BW_CFG(x) | BIT_BW_CFG(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_MU_TRX_DBG_CNT_V1 (Offset 0x14DC) */
+
+#define BIT_FORCE_SND_STS_EN BIT(31)
+
+#define BIT_SHIFT_SND_STS_VALUE 24
+#define BIT_MASK_SND_STS_VALUE 0x3f
+#define BIT_SND_STS_VALUE(x) \
+ (((x) & BIT_MASK_SND_STS_VALUE) << BIT_SHIFT_SND_STS_VALUE)
+#define BITS_SND_STS_VALUE (BIT_MASK_SND_STS_VALUE << BIT_SHIFT_SND_STS_VALUE)
+#define BIT_CLEAR_SND_STS_VALUE(x) ((x) & (~BITS_SND_STS_VALUE))
+#define BIT_GET_SND_STS_VALUE(x) \
+ (((x) >> BIT_SHIFT_SND_STS_VALUE) & BIT_MASK_SND_STS_VALUE)
+#define BIT_SET_SND_STS_VALUE(x, v) \
+ (BIT_CLEAR_SND_STS_VALUE(x) | BIT_SND_STS_VALUE(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_MU_TRX_DBG_CNT_V1 (Offset 0x14DC) */
+
+#define BIT_SHIFT_MU_DNGCNT_SEL 16
+#define BIT_MASK_MU_DNGCNT_SEL 0xf
+#define BIT_MU_DNGCNT_SEL(x) \
+ (((x) & BIT_MASK_MU_DNGCNT_SEL) << BIT_SHIFT_MU_DNGCNT_SEL)
+#define BITS_MU_DNGCNT_SEL (BIT_MASK_MU_DNGCNT_SEL << BIT_SHIFT_MU_DNGCNT_SEL)
+#define BIT_CLEAR_MU_DNGCNT_SEL(x) ((x) & (~BITS_MU_DNGCNT_SEL))
+#define BIT_GET_MU_DNGCNT_SEL(x) \
+ (((x) >> BIT_SHIFT_MU_DNGCNT_SEL) & BIT_MASK_MU_DNGCNT_SEL)
+#define BIT_SET_MU_DNGCNT_SEL(x, v) \
+ (BIT_CLEAR_MU_DNGCNT_SEL(x) | BIT_MU_DNGCNT_SEL(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_SWPS_CTRL (Offset 0x14F4) */
+
+#define BIT_SHIFT_SWPS_RPT_LENGTH 8
+#define BIT_MASK_SWPS_RPT_LENGTH 0x7f
+#define BIT_SWPS_RPT_LENGTH(x) \
+ (((x) & BIT_MASK_SWPS_RPT_LENGTH) << BIT_SHIFT_SWPS_RPT_LENGTH)
+#define BITS_SWPS_RPT_LENGTH \
+ (BIT_MASK_SWPS_RPT_LENGTH << BIT_SHIFT_SWPS_RPT_LENGTH)
+#define BIT_CLEAR_SWPS_RPT_LENGTH(x) ((x) & (~BITS_SWPS_RPT_LENGTH))
+#define BIT_GET_SWPS_RPT_LENGTH(x) \
+ (((x) >> BIT_SHIFT_SWPS_RPT_LENGTH) & BIT_MASK_SWPS_RPT_LENGTH)
+#define BIT_SET_SWPS_RPT_LENGTH(x, v) \
+ (BIT_CLEAR_SWPS_RPT_LENGTH(x) | BIT_SWPS_RPT_LENGTH(v))
+
+#define BIT_SHIFT_MACID_SWPS_EN_SEL 2
+#define BIT_MASK_MACID_SWPS_EN_SEL 0x3
+#define BIT_MACID_SWPS_EN_SEL(x) \
+ (((x) & BIT_MASK_MACID_SWPS_EN_SEL) << BIT_SHIFT_MACID_SWPS_EN_SEL)
+#define BITS_MACID_SWPS_EN_SEL \
+ (BIT_MASK_MACID_SWPS_EN_SEL << BIT_SHIFT_MACID_SWPS_EN_SEL)
+#define BIT_CLEAR_MACID_SWPS_EN_SEL(x) ((x) & (~BITS_MACID_SWPS_EN_SEL))
+#define BIT_GET_MACID_SWPS_EN_SEL(x) \
+ (((x) >> BIT_SHIFT_MACID_SWPS_EN_SEL) & BIT_MASK_MACID_SWPS_EN_SEL)
+#define BIT_SET_MACID_SWPS_EN_SEL(x, v) \
+ (BIT_CLEAR_MACID_SWPS_EN_SEL(x) | BIT_MACID_SWPS_EN_SEL(v))
+
+#define BIT_SWPS_MANUALL_POLLING BIT(1)
+#define BIT_SWPS_EN BIT(0)
+
+/* 2 REG_SWPS_PKT_TH (Offset 0x14F6) */
+
+#define BIT_SHIFT_SWPS_PKT_TH 0
+#define BIT_MASK_SWPS_PKT_TH 0xffff
+#define BIT_SWPS_PKT_TH(x) \
+ (((x) & BIT_MASK_SWPS_PKT_TH) << BIT_SHIFT_SWPS_PKT_TH)
+#define BITS_SWPS_PKT_TH (BIT_MASK_SWPS_PKT_TH << BIT_SHIFT_SWPS_PKT_TH)
+#define BIT_CLEAR_SWPS_PKT_TH(x) ((x) & (~BITS_SWPS_PKT_TH))
+#define BIT_GET_SWPS_PKT_TH(x) \
+ (((x) >> BIT_SHIFT_SWPS_PKT_TH) & BIT_MASK_SWPS_PKT_TH)
+#define BIT_SET_SWPS_PKT_TH(x, v) \
+ (BIT_CLEAR_SWPS_PKT_TH(x) | BIT_SWPS_PKT_TH(v))
+
+/* 2 REG_SWPS_TIME_TH (Offset 0x14F8) */
+
+#define BIT_SHIFT_SWPS_PSTIME_TH 16
+#define BIT_MASK_SWPS_PSTIME_TH 0xffff
+#define BIT_SWPS_PSTIME_TH(x) \
+ (((x) & BIT_MASK_SWPS_PSTIME_TH) << BIT_SHIFT_SWPS_PSTIME_TH)
+#define BITS_SWPS_PSTIME_TH \
+ (BIT_MASK_SWPS_PSTIME_TH << BIT_SHIFT_SWPS_PSTIME_TH)
+#define BIT_CLEAR_SWPS_PSTIME_TH(x) ((x) & (~BITS_SWPS_PSTIME_TH))
+#define BIT_GET_SWPS_PSTIME_TH(x) \
+ (((x) >> BIT_SHIFT_SWPS_PSTIME_TH) & BIT_MASK_SWPS_PSTIME_TH)
+#define BIT_SET_SWPS_PSTIME_TH(x, v) \
+ (BIT_CLEAR_SWPS_PSTIME_TH(x) | BIT_SWPS_PSTIME_TH(v))
+
+#define BIT_SHIFT_SWPS_TIME_TH 0
+#define BIT_MASK_SWPS_TIME_TH 0xffff
+#define BIT_SWPS_TIME_TH(x) \
+ (((x) & BIT_MASK_SWPS_TIME_TH) << BIT_SHIFT_SWPS_TIME_TH)
+#define BITS_SWPS_TIME_TH (BIT_MASK_SWPS_TIME_TH << BIT_SHIFT_SWPS_TIME_TH)
+#define BIT_CLEAR_SWPS_TIME_TH(x) ((x) & (~BITS_SWPS_TIME_TH))
+#define BIT_GET_SWPS_TIME_TH(x) \
+ (((x) >> BIT_SHIFT_SWPS_TIME_TH) & BIT_MASK_SWPS_TIME_TH)
+#define BIT_SET_SWPS_TIME_TH(x, v) \
+ (BIT_CLEAR_SWPS_TIME_TH(x) | BIT_SWPS_TIME_TH(v))
+
+/* 2 REG_MACID_SWPS_EN (Offset 0x14FC) */
+
+#define BIT_SHIFT_MACID_SWPS_EN 0
+#define BIT_MASK_MACID_SWPS_EN 0xffffffffL
+#define BIT_MACID_SWPS_EN(x) \
+ (((x) & BIT_MASK_MACID_SWPS_EN) << BIT_SHIFT_MACID_SWPS_EN)
+#define BITS_MACID_SWPS_EN (BIT_MASK_MACID_SWPS_EN << BIT_SHIFT_MACID_SWPS_EN)
+#define BIT_CLEAR_MACID_SWPS_EN(x) ((x) & (~BITS_MACID_SWPS_EN))
+#define BIT_GET_MACID_SWPS_EN(x) \
+ (((x) >> BIT_SHIFT_MACID_SWPS_EN) & BIT_MASK_MACID_SWPS_EN)
+#define BIT_SET_MACID_SWPS_EN(x, v) \
+ (BIT_CLEAR_MACID_SWPS_EN(x) | BIT_MACID_SWPS_EN(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_PORT_CTRL_SEL (Offset 0x1500) */
+
+#define BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1 4
+#define BIT_MASK_BCN_TIMER_SEL_FWRD_V1 0x7
+#define BIT_BCN_TIMER_SEL_FWRD_V1(x) \
+ (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_V1) \
+ << BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1)
+#define BITS_BCN_TIMER_SEL_FWRD_V1 \
+ (BIT_MASK_BCN_TIMER_SEL_FWRD_V1 << BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1)
+#define BIT_CLEAR_BCN_TIMER_SEL_FWRD_V1(x) ((x) & (~BITS_BCN_TIMER_SEL_FWRD_V1))
+#define BIT_GET_BCN_TIMER_SEL_FWRD_V1(x) \
+ (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1) & \
+ BIT_MASK_BCN_TIMER_SEL_FWRD_V1)
+#define BIT_SET_BCN_TIMER_SEL_FWRD_V1(x, v) \
+ (BIT_CLEAR_BCN_TIMER_SEL_FWRD_V1(x) | BIT_BCN_TIMER_SEL_FWRD_V1(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_H2CQ_TXBD_NUM (Offset 0x1328) */
+/* 2 REG_CPUMGQ_TX_TIMER (Offset 0x1500) */
-#define BIT_HCI_H2CQ_FLAG BIT(14)
+#define BIT_SHIFT_CPUMGQ_TX_TIMER_V1 0
+#define BIT_MASK_CPUMGQ_TX_TIMER_V1 0xffffffffL
+#define BIT_CPUMGQ_TX_TIMER_V1(x) \
+ (((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1) << BIT_SHIFT_CPUMGQ_TX_TIMER_V1)
+#define BITS_CPUMGQ_TX_TIMER_V1 \
+ (BIT_MASK_CPUMGQ_TX_TIMER_V1 << BIT_SHIFT_CPUMGQ_TX_TIMER_V1)
+#define BIT_CLEAR_CPUMGQ_TX_TIMER_V1(x) ((x) & (~BITS_CPUMGQ_TX_TIMER_V1))
+#define BIT_GET_CPUMGQ_TX_TIMER_V1(x) \
+ (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1) & BIT_MASK_CPUMGQ_TX_TIMER_V1)
+#define BIT_SET_CPUMGQ_TX_TIMER_V1(x, v) \
+ (BIT_CLEAR_CPUMGQ_TX_TIMER_V1(x) | BIT_CPUMGQ_TX_TIMER_V1(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_PORT_CTRL_SEL (Offset 0x1500) */
+#define BIT_SHIFT_PORT_CTRL_SEL 0
+#define BIT_MASK_PORT_CTRL_SEL 0x7
+#define BIT_PORT_CTRL_SEL(x) \
+ (((x) & BIT_MASK_PORT_CTRL_SEL) << BIT_SHIFT_PORT_CTRL_SEL)
+#define BITS_PORT_CTRL_SEL (BIT_MASK_PORT_CTRL_SEL << BIT_SHIFT_PORT_CTRL_SEL)
+#define BIT_CLEAR_PORT_CTRL_SEL(x) ((x) & (~BITS_PORT_CTRL_SEL))
+#define BIT_GET_PORT_CTRL_SEL(x) \
+ (((x) >> BIT_SHIFT_PORT_CTRL_SEL) & BIT_MASK_PORT_CTRL_SEL)
+#define BIT_SET_PORT_CTRL_SEL(x, v) \
+ (BIT_CLEAR_PORT_CTRL_SEL(x) | BIT_PORT_CTRL_SEL(v))
-/* 2 REG_H2CQ_TXBD_NUM (Offset 0x1328) */
+/* 2 REG_PORT_CTRL_CFG (Offset 0x1501) */
-#define BIT_PCIE_H2CQ_FLAG BIT(14)
+#define BIT_BCNERR_CNT_EN_V1 BIT(11)
+#define BIT_DIS_TRX_CAL_BCN_V1 BIT(10)
+#define BIT_DIS_TX_CAL_TBTT_V1 BIT(9)
+#define BIT_BCN_AGGRESSION_V1 BIT(8)
+#define BIT_TSFTR_RST_V1 BIT(7)
+#define BIT_EN_TXBCN_RPT_V1 BIT(5)
+#define BIT_EN_PORT_FUNCTION BIT(3)
+#define BIT_EN_RXBCN_RPT BIT(2)
-#endif
+/* 2 REG_TBTT_PROHIBIT_CFG (Offset 0x1504) */
+#define BIT_MASK_PROHIBIT BIT(23)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#define BIT_SHIFT_TBTT_HOLD_TIME 8
+#define BIT_MASK_TBTT_HOLD_TIME 0xfff
+#define BIT_TBTT_HOLD_TIME(x) \
+ (((x) & BIT_MASK_TBTT_HOLD_TIME) << BIT_SHIFT_TBTT_HOLD_TIME)
+#define BITS_TBTT_HOLD_TIME \
+ (BIT_MASK_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME)
+#define BIT_CLEAR_TBTT_HOLD_TIME(x) ((x) & (~BITS_TBTT_HOLD_TIME))
+#define BIT_GET_TBTT_HOLD_TIME(x) \
+ (((x) >> BIT_SHIFT_TBTT_HOLD_TIME) & BIT_MASK_TBTT_HOLD_TIME)
+#define BIT_SET_TBTT_HOLD_TIME(x, v) \
+ (BIT_CLEAR_TBTT_HOLD_TIME(x) | BIT_TBTT_HOLD_TIME(v))
+#endif
-/* 2 REG_H2CQ_TXBD_NUM (Offset 0x1328) */
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+/* 2 REG_PS_TIMER_A (Offset 0x1504) */
-#define BIT_SHIFT_H2CQ_DESC_MODE 12
-#define BIT_MASK_H2CQ_DESC_MODE 0x3
-#define BIT_H2CQ_DESC_MODE(x) (((x) & BIT_MASK_H2CQ_DESC_MODE) << BIT_SHIFT_H2CQ_DESC_MODE)
-#define BIT_GET_H2CQ_DESC_MODE(x) (((x) >> BIT_SHIFT_H2CQ_DESC_MODE) & BIT_MASK_H2CQ_DESC_MODE)
+#define BIT_SHIFT_PS_TIMER_A_V1 0
+#define BIT_MASK_PS_TIMER_A_V1 0xffffffffL
+#define BIT_PS_TIMER_A_V1(x) \
+ (((x) & BIT_MASK_PS_TIMER_A_V1) << BIT_SHIFT_PS_TIMER_A_V1)
+#define BITS_PS_TIMER_A_V1 (BIT_MASK_PS_TIMER_A_V1 << BIT_SHIFT_PS_TIMER_A_V1)
+#define BIT_CLEAR_PS_TIMER_A_V1(x) ((x) & (~BITS_PS_TIMER_A_V1))
+#define BIT_GET_PS_TIMER_A_V1(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_A_V1) & BIT_MASK_PS_TIMER_A_V1)
+#define BIT_SET_PS_TIMER_A_V1(x, v) \
+ (BIT_CLEAR_PS_TIMER_A_V1(x) | BIT_PS_TIMER_A_V1(v))
+/* 2 REG_PS_TIMER_B (Offset 0x1508) */
-#define BIT_SHIFT_H2CQ_DESC_NUM 0
-#define BIT_MASK_H2CQ_DESC_NUM 0xfff
-#define BIT_H2CQ_DESC_NUM(x) (((x) & BIT_MASK_H2CQ_DESC_NUM) << BIT_SHIFT_H2CQ_DESC_NUM)
-#define BIT_GET_H2CQ_DESC_NUM(x) (((x) >> BIT_SHIFT_H2CQ_DESC_NUM) & BIT_MASK_H2CQ_DESC_NUM)
+#define BIT_SHIFT_PS_TIMER_B_V1 0
+#define BIT_MASK_PS_TIMER_B_V1 0xffffffffL
+#define BIT_PS_TIMER_B_V1(x) \
+ (((x) & BIT_MASK_PS_TIMER_B_V1) << BIT_SHIFT_PS_TIMER_B_V1)
+#define BITS_PS_TIMER_B_V1 (BIT_MASK_PS_TIMER_B_V1 << BIT_SHIFT_PS_TIMER_B_V1)
+#define BIT_CLEAR_PS_TIMER_B_V1(x) ((x) & (~BITS_PS_TIMER_B_V1))
+#define BIT_GET_PS_TIMER_B_V1(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_B_V1) & BIT_MASK_PS_TIMER_B_V1)
+#define BIT_SET_PS_TIMER_B_V1(x, v) \
+ (BIT_CLEAR_PS_TIMER_B_V1(x) | BIT_PS_TIMER_B_V1(v))
+/* 2 REG_PS_TIMER_C (Offset 0x150C) */
-/* 2 REG_H2CQ_TXBD_IDX (Offset 0x132C) */
+#define BIT_SHIFT_PS_TIMER_C_V1 0
+#define BIT_MASK_PS_TIMER_C_V1 0xffffffffL
+#define BIT_PS_TIMER_C_V1(x) \
+ (((x) & BIT_MASK_PS_TIMER_C_V1) << BIT_SHIFT_PS_TIMER_C_V1)
+#define BITS_PS_TIMER_C_V1 (BIT_MASK_PS_TIMER_C_V1 << BIT_SHIFT_PS_TIMER_C_V1)
+#define BIT_CLEAR_PS_TIMER_C_V1(x) ((x) & (~BITS_PS_TIMER_C_V1))
+#define BIT_GET_PS_TIMER_C_V1(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_C_V1) & BIT_MASK_PS_TIMER_C_V1)
+#define BIT_SET_PS_TIMER_C_V1(x, v) \
+ (BIT_CLEAR_PS_TIMER_C_V1(x) | BIT_PS_TIMER_C_V1(v))
+#endif
-#define BIT_SHIFT_H2CQ_HW_IDX 16
-#define BIT_MASK_H2CQ_HW_IDX 0xfff
-#define BIT_H2CQ_HW_IDX(x) (((x) & BIT_MASK_H2CQ_HW_IDX) << BIT_SHIFT_H2CQ_HW_IDX)
-#define BIT_GET_H2CQ_HW_IDX(x) (((x) >> BIT_SHIFT_H2CQ_HW_IDX) & BIT_MASK_H2CQ_HW_IDX)
+#if (HALMAC_8814B_SUPPORT)
+/* 2 REG_TSFTR_SYNC_OFFSET_CFG (Offset 0x150C) */
-#define BIT_SHIFT_H2CQ_HOST_IDX 0
-#define BIT_MASK_H2CQ_HOST_IDX 0xfff
-#define BIT_H2CQ_HOST_IDX(x) (((x) & BIT_MASK_H2CQ_HOST_IDX) << BIT_SHIFT_H2CQ_HOST_IDX)
-#define BIT_GET_H2CQ_HOST_IDX(x) (((x) >> BIT_SHIFT_H2CQ_HOST_IDX) & BIT_MASK_H2CQ_HOST_IDX)
+#define BIT_SHIFT_TSFTR_SNC_OFFSET_V1 0
+#define BIT_MASK_TSFTR_SNC_OFFSET_V1 0xffffff
+#define BIT_TSFTR_SNC_OFFSET_V1(x) \
+ (((x) & BIT_MASK_TSFTR_SNC_OFFSET_V1) << BIT_SHIFT_TSFTR_SNC_OFFSET_V1)
+#define BITS_TSFTR_SNC_OFFSET_V1 \
+ (BIT_MASK_TSFTR_SNC_OFFSET_V1 << BIT_SHIFT_TSFTR_SNC_OFFSET_V1)
+#define BIT_CLEAR_TSFTR_SNC_OFFSET_V1(x) ((x) & (~BITS_TSFTR_SNC_OFFSET_V1))
+#define BIT_GET_TSFTR_SNC_OFFSET_V1(x) \
+ (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_V1) & BIT_MASK_TSFTR_SNC_OFFSET_V1)
+#define BIT_SET_TSFTR_SNC_OFFSET_V1(x, v) \
+ (BIT_CLEAR_TSFTR_SNC_OFFSET_V1(x) | BIT_TSFTR_SNC_OFFSET_V1(v))
+/* 2 REG_TSFTR_SYNC_CTRL_CFG (Offset 0x150F) */
-/* 2 REG_H2CQ_CSR (Offset 0x1330) */
+#define BIT_SYNC_TSF_NOW_V1 BIT(5)
+#define BIT_SYNC_TSF_ONCE BIT(4)
+#define BIT_SYNC_TSF_AUTO BIT(3)
-#define BIT_H2CQ_FULL BIT(31)
-#define BIT_CLR_H2CQ_HOST_IDX BIT(16)
-#define BIT_CLR_H2CQ_HW_IDX BIT(8)
+#define BIT_SHIFT_SYNC_PORT_SEL 0
+#define BIT_MASK_SYNC_PORT_SEL 0x7
+#define BIT_SYNC_PORT_SEL(x) \
+ (((x) & BIT_MASK_SYNC_PORT_SEL) << BIT_SHIFT_SYNC_PORT_SEL)
+#define BITS_SYNC_PORT_SEL (BIT_MASK_SYNC_PORT_SEL << BIT_SHIFT_SYNC_PORT_SEL)
+#define BIT_CLEAR_SYNC_PORT_SEL(x) ((x) & (~BITS_SYNC_PORT_SEL))
+#define BIT_GET_SYNC_PORT_SEL(x) \
+ (((x) >> BIT_SHIFT_SYNC_PORT_SEL) & BIT_MASK_SYNC_PORT_SEL)
+#define BIT_SET_SYNC_PORT_SEL(x, v) \
+ (BIT_CLEAR_SYNC_PORT_SEL(x) | BIT_SYNC_PORT_SEL(v))
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+/* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL (Offset 0x1510) */
+#define BIT_CPUMGQ_TIMER_EN BIT(31)
+#define BIT_CPUMGQ_TX_EN BIT(28)
+
+#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL 24
+#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL 0x7
+#define BIT_CPUMGQ_TIMER_TSF_SEL(x) \
+ (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL) \
+ << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL)
+#define BITS_CPUMGQ_TIMER_TSF_SEL \
+ (BIT_MASK_CPUMGQ_TIMER_TSF_SEL << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL)
+#define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL(x) ((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL))
+#define BIT_GET_CPUMGQ_TIMER_TSF_SEL(x) \
+ (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL) & \
+ BIT_MASK_CPUMGQ_TIMER_TSF_SEL)
+#define BIT_SET_CPUMGQ_TIMER_TSF_SEL(x, v) \
+ (BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL(x) | BIT_CPUMGQ_TIMER_TSF_SEL(v))
+
+#define BIT_PS_TIMER_C_EN BIT(23)
+
+#define BIT_SHIFT_PS_TIMER_C_TSF_SEL 16
+#define BIT_MASK_PS_TIMER_C_TSF_SEL 0x7
+#define BIT_PS_TIMER_C_TSF_SEL(x) \
+ (((x) & BIT_MASK_PS_TIMER_C_TSF_SEL) << BIT_SHIFT_PS_TIMER_C_TSF_SEL)
+#define BITS_PS_TIMER_C_TSF_SEL \
+ (BIT_MASK_PS_TIMER_C_TSF_SEL << BIT_SHIFT_PS_TIMER_C_TSF_SEL)
+#define BIT_CLEAR_PS_TIMER_C_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_C_TSF_SEL))
+#define BIT_GET_PS_TIMER_C_TSF_SEL(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL) & BIT_MASK_PS_TIMER_C_TSF_SEL)
+#define BIT_SET_PS_TIMER_C_TSF_SEL(x, v) \
+ (BIT_CLEAR_PS_TIMER_C_TSF_SEL(x) | BIT_PS_TIMER_C_TSF_SEL(v))
+
+#define BIT_PS_TIMER_B_EN BIT(15)
+
+#define BIT_SHIFT_PS_TIMER_B_TSF_SEL 8
+#define BIT_MASK_PS_TIMER_B_TSF_SEL 0x7
+#define BIT_PS_TIMER_B_TSF_SEL(x) \
+ (((x) & BIT_MASK_PS_TIMER_B_TSF_SEL) << BIT_SHIFT_PS_TIMER_B_TSF_SEL)
+#define BITS_PS_TIMER_B_TSF_SEL \
+ (BIT_MASK_PS_TIMER_B_TSF_SEL << BIT_SHIFT_PS_TIMER_B_TSF_SEL)
+#define BIT_CLEAR_PS_TIMER_B_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_B_TSF_SEL))
+#define BIT_GET_PS_TIMER_B_TSF_SEL(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL) & BIT_MASK_PS_TIMER_B_TSF_SEL)
+#define BIT_SET_PS_TIMER_B_TSF_SEL(x, v) \
+ (BIT_CLEAR_PS_TIMER_B_TSF_SEL(x) | BIT_PS_TIMER_B_TSF_SEL(v))
+
+#define BIT_PS_TIMER_A_EN BIT(7)
+
+#define BIT_SHIFT_PS_TIMER_A_TSF_SEL 0
+#define BIT_MASK_PS_TIMER_A_TSF_SEL 0x7
+#define BIT_PS_TIMER_A_TSF_SEL(x) \
+ (((x) & BIT_MASK_PS_TIMER_A_TSF_SEL) << BIT_SHIFT_PS_TIMER_A_TSF_SEL)
+#define BITS_PS_TIMER_A_TSF_SEL \
+ (BIT_MASK_PS_TIMER_A_TSF_SEL << BIT_SHIFT_PS_TIMER_A_TSF_SEL)
+#define BIT_CLEAR_PS_TIMER_A_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_A_TSF_SEL))
+#define BIT_GET_PS_TIMER_A_TSF_SEL(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL) & BIT_MASK_PS_TIMER_A_TSF_SEL)
+#define BIT_SET_PS_TIMER_A_TSF_SEL(x, v) \
+ (BIT_CLEAR_PS_TIMER_A_TSF_SEL(x) | BIT_PS_TIMER_A_TSF_SEL(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_BCN_SPACE_CFG (Offset 0x1510) */
+
+#define BIT_SHIFT_BCN_SPACE 0
+#define BIT_MASK_BCN_SPACE 0xffff
+#define BIT_BCN_SPACE(x) (((x) & BIT_MASK_BCN_SPACE) << BIT_SHIFT_BCN_SPACE)
+#define BITS_BCN_SPACE (BIT_MASK_BCN_SPACE << BIT_SHIFT_BCN_SPACE)
+#define BIT_CLEAR_BCN_SPACE(x) ((x) & (~BITS_BCN_SPACE))
+#define BIT_GET_BCN_SPACE(x) (((x) >> BIT_SHIFT_BCN_SPACE) & BIT_MASK_BCN_SPACE)
+#define BIT_SET_BCN_SPACE(x, v) (BIT_CLEAR_BCN_SPACE(x) | BIT_BCN_SPACE(v))
+
+/* 2 REG_EARLY_INT_ADJUST_CFG (Offset 0x1512) */
+
+#define BIT_SHIFT_EARLY_INT_ADJUST 0
+#define BIT_MASK_EARLY_INT_ADJUST 0xffff
+#define BIT_EARLY_INT_ADJUST(x) \
+ (((x) & BIT_MASK_EARLY_INT_ADJUST) << BIT_SHIFT_EARLY_INT_ADJUST)
+#define BITS_EARLY_INT_ADJUST \
+ (BIT_MASK_EARLY_INT_ADJUST << BIT_SHIFT_EARLY_INT_ADJUST)
+#define BIT_CLEAR_EARLY_INT_ADJUST(x) ((x) & (~BITS_EARLY_INT_ADJUST))
+#define BIT_GET_EARLY_INT_ADJUST(x) \
+ (((x) >> BIT_SHIFT_EARLY_INT_ADJUST) & BIT_MASK_EARLY_INT_ADJUST)
+#define BIT_SET_EARLY_INT_ADJUST(x, v) \
+ (BIT_CLEAR_EARLY_INT_ADJUST(x) | BIT_EARLY_INT_ADJUST(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_H2CQ_CSR (Offset 0x1330) */
+/* 2 REG_CPUMGQ_TX_TIMER_EARLY (Offset 0x1514) */
-#define BIT_STOP_H2CQ BIT(0)
+#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY 0
+#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY 0xff
+#define BIT_CPUMGQ_TX_TIMER_EARLY(x) \
+ (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY) \
+ << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY)
+#define BITS_CPUMGQ_TX_TIMER_EARLY \
+ (BIT_MASK_CPUMGQ_TX_TIMER_EARLY << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY)
+#define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY(x) ((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY))
+#define BIT_GET_CPUMGQ_TX_TIMER_EARLY(x) \
+ (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY) & \
+ BIT_MASK_CPUMGQ_TX_TIMER_EARLY)
+#define BIT_SET_CPUMGQ_TX_TIMER_EARLY(x, v) \
+ (BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY(x) | BIT_CPUMGQ_TX_TIMER_EARLY(v))
-#endif
+/* 2 REG_PS_TIMER_A_EARLY (Offset 0x1515) */
+#define BIT_SHIFT_PS_TIMER_A_EARLY 0
+#define BIT_MASK_PS_TIMER_A_EARLY 0xff
+#define BIT_PS_TIMER_A_EARLY(x) \
+ (((x) & BIT_MASK_PS_TIMER_A_EARLY) << BIT_SHIFT_PS_TIMER_A_EARLY)
+#define BITS_PS_TIMER_A_EARLY \
+ (BIT_MASK_PS_TIMER_A_EARLY << BIT_SHIFT_PS_TIMER_A_EARLY)
+#define BIT_CLEAR_PS_TIMER_A_EARLY(x) ((x) & (~BITS_PS_TIMER_A_EARLY))
+#define BIT_GET_PS_TIMER_A_EARLY(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_A_EARLY) & BIT_MASK_PS_TIMER_A_EARLY)
+#define BIT_SET_PS_TIMER_A_EARLY(x, v) \
+ (BIT_CLEAR_PS_TIMER_A_EARLY(x) | BIT_PS_TIMER_A_EARLY(v))
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_PS_TIMER_B_EARLY (Offset 0x1516) */
+#define BIT_SHIFT_PS_TIMER_B_EARLY 0
+#define BIT_MASK_PS_TIMER_B_EARLY 0xff
+#define BIT_PS_TIMER_B_EARLY(x) \
+ (((x) & BIT_MASK_PS_TIMER_B_EARLY) << BIT_SHIFT_PS_TIMER_B_EARLY)
+#define BITS_PS_TIMER_B_EARLY \
+ (BIT_MASK_PS_TIMER_B_EARLY << BIT_SHIFT_PS_TIMER_B_EARLY)
+#define BIT_CLEAR_PS_TIMER_B_EARLY(x) ((x) & (~BITS_PS_TIMER_B_EARLY))
+#define BIT_GET_PS_TIMER_B_EARLY(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_B_EARLY) & BIT_MASK_PS_TIMER_B_EARLY)
+#define BIT_SET_PS_TIMER_B_EARLY(x, v) \
+ (BIT_CLEAR_PS_TIMER_B_EARLY(x) | BIT_PS_TIMER_B_EARLY(v))
-/* 2 REG_AXI_EXCEPT_CS (Offset 0x1350) */
+/* 2 REG_PS_TIMER_C_EARLY (Offset 0x1517) */
-#define BIT_AXI_RXDMA_TIMEOUT_RE BIT(21)
-#define BIT_AXI_TXDMA_TIMEOUT_RE BIT(20)
-#define BIT_AXI_DECERR_W_RE BIT(19)
-#define BIT_AXI_DECERR_R_RE BIT(18)
-#define BIT_AXI_SLVERR_W_RE BIT(17)
-#define BIT_AXI_SLVERR_R_RE BIT(16)
-#define BIT_AXI_RXDMA_TIMEOUT_IE BIT(13)
-#define BIT_AXI_TXDMA_TIMEOUT_IE BIT(12)
-#define BIT_AXI_DECERR_W_IE BIT(11)
-#define BIT_AXI_DECERR_R_IE BIT(10)
-#define BIT_AXI_SLVERR_W_IE BIT(9)
-#define BIT_AXI_SLVERR_R_IE BIT(8)
-#define BIT_AXI_RXDMA_TIMEOUT_FLAG BIT(5)
-#define BIT_AXI_TXDMA_TIMEOUT_FLAG BIT(4)
-#define BIT_AXI_DECERR_W_FLAG BIT(3)
-#define BIT_AXI_DECERR_R_FLAG BIT(2)
-#define BIT_AXI_SLVERR_W_FLAG BIT(1)
-#define BIT_AXI_SLVERR_R_FLAG BIT(0)
+#define BIT_SHIFT_PS_TIMER_C_EARLY 0
+#define BIT_MASK_PS_TIMER_C_EARLY 0xff
+#define BIT_PS_TIMER_C_EARLY(x) \
+ (((x) & BIT_MASK_PS_TIMER_C_EARLY) << BIT_SHIFT_PS_TIMER_C_EARLY)
+#define BITS_PS_TIMER_C_EARLY \
+ (BIT_MASK_PS_TIMER_C_EARLY << BIT_SHIFT_PS_TIMER_C_EARLY)
+#define BIT_CLEAR_PS_TIMER_C_EARLY(x) ((x) & (~BITS_PS_TIMER_C_EARLY))
+#define BIT_GET_PS_TIMER_C_EARLY(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_C_EARLY) & BIT_MASK_PS_TIMER_C_EARLY)
+#define BIT_SET_PS_TIMER_C_EARLY(x, v) \
+ (BIT_CLEAR_PS_TIMER_C_EARLY(x) | BIT_PS_TIMER_C_EARLY(v))
-/* 2 REG_AXI_EXCEPT_TIME (Offset 0x1354) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_AXI_RECOVERY_TIME 24
-#define BIT_MASK_AXI_RECOVERY_TIME 0xff
-#define BIT_AXI_RECOVERY_TIME(x) (((x) & BIT_MASK_AXI_RECOVERY_TIME) << BIT_SHIFT_AXI_RECOVERY_TIME)
-#define BIT_GET_AXI_RECOVERY_TIME(x) (((x) >> BIT_SHIFT_AXI_RECOVERY_TIME) & BIT_MASK_AXI_RECOVERY_TIME)
+/* 2 REG_CPUMGQ_PARAMETER (Offset 0x1518) */
+#define BIT_STOP_CPUMGQ BIT(16)
-#define BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL 12
-#define BIT_MASK_AXI_RXDMA_TIMEOUT_VAL 0xfff
-#define BIT_AXI_RXDMA_TIMEOUT_VAL(x) (((x) & BIT_MASK_AXI_RXDMA_TIMEOUT_VAL) << BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL)
-#define BIT_GET_AXI_RXDMA_TIMEOUT_VAL(x) (((x) >> BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL) & BIT_MASK_AXI_RXDMA_TIMEOUT_VAL)
+#define BIT_SHIFT_CPUMGQ_PARAMETER 0
+#define BIT_MASK_CPUMGQ_PARAMETER 0xffff
+#define BIT_CPUMGQ_PARAMETER(x) \
+ (((x) & BIT_MASK_CPUMGQ_PARAMETER) << BIT_SHIFT_CPUMGQ_PARAMETER)
+#define BITS_CPUMGQ_PARAMETER \
+ (BIT_MASK_CPUMGQ_PARAMETER << BIT_SHIFT_CPUMGQ_PARAMETER)
+#define BIT_CLEAR_CPUMGQ_PARAMETER(x) ((x) & (~BITS_CPUMGQ_PARAMETER))
+#define BIT_GET_CPUMGQ_PARAMETER(x) \
+ (((x) >> BIT_SHIFT_CPUMGQ_PARAMETER) & BIT_MASK_CPUMGQ_PARAMETER)
+#define BIT_SET_CPUMGQ_PARAMETER(x, v) \
+ (BIT_CLEAR_CPUMGQ_PARAMETER(x) | BIT_CPUMGQ_PARAMETER(v))
+#endif
-#define BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL 0
-#define BIT_MASK_AXI_TXDMA_TIMEOUT_VAL 0xfff
-#define BIT_AXI_TXDMA_TIMEOUT_VAL(x) (((x) & BIT_MASK_AXI_TXDMA_TIMEOUT_VAL) << BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL)
-#define BIT_GET_AXI_TXDMA_TIMEOUT_VAL(x) (((x) >> BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL) & BIT_MASK_AXI_TXDMA_TIMEOUT_VAL)
+#if (HALMAC_8814B_SUPPORT)
+/* 2 REG_SW_TBTT_TSF_INFO (Offset 0x151C) */
-#endif
+#define BIT_SHIFT_SW_TBTT_TSF_INFO 0
+#define BIT_MASK_SW_TBTT_TSF_INFO 0xffffffffL
+#define BIT_SW_TBTT_TSF_INFO(x) \
+ (((x) & BIT_MASK_SW_TBTT_TSF_INFO) << BIT_SHIFT_SW_TBTT_TSF_INFO)
+#define BITS_SW_TBTT_TSF_INFO \
+ (BIT_MASK_SW_TBTT_TSF_INFO << BIT_SHIFT_SW_TBTT_TSF_INFO)
+#define BIT_CLEAR_SW_TBTT_TSF_INFO(x) ((x) & (~BITS_SW_TBTT_TSF_INFO))
+#define BIT_GET_SW_TBTT_TSF_INFO(x) \
+ (((x) >> BIT_SHIFT_SW_TBTT_TSF_INFO) & BIT_MASK_SW_TBTT_TSF_INFO)
+#define BIT_SET_SW_TBTT_TSF_INFO(x, v) \
+ (BIT_CLEAR_SW_TBTT_TSF_INFO(x) | BIT_SW_TBTT_TSF_INFO(v))
+#endif
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#if (HALMAC_8822C_SUPPORT)
+/* 2 REG_TSF_SYNC_ADJ (Offset 0x1520) */
-/* 2 REG_Q0_Q1_INFO (Offset 0x1400) */
+#define BIT_SHIFT_R_P0_TSFT_ADJ_VAL 16
+#define BIT_MASK_R_P0_TSFT_ADJ_VAL 0xffff
+#define BIT_R_P0_TSFT_ADJ_VAL(x) \
+ (((x) & BIT_MASK_R_P0_TSFT_ADJ_VAL) << BIT_SHIFT_R_P0_TSFT_ADJ_VAL)
+#define BITS_R_P0_TSFT_ADJ_VAL \
+ (BIT_MASK_R_P0_TSFT_ADJ_VAL << BIT_SHIFT_R_P0_TSFT_ADJ_VAL)
+#define BIT_CLEAR_R_P0_TSFT_ADJ_VAL(x) ((x) & (~BITS_R_P0_TSFT_ADJ_VAL))
+#define BIT_GET_R_P0_TSFT_ADJ_VAL(x) \
+ (((x) >> BIT_SHIFT_R_P0_TSFT_ADJ_VAL) & BIT_MASK_R_P0_TSFT_ADJ_VAL)
+#define BIT_SET_R_P0_TSFT_ADJ_VAL(x, v) \
+ (BIT_CLEAR_R_P0_TSFT_ADJ_VAL(x) | BIT_R_P0_TSFT_ADJ_VAL(v))
+#define BIT_R_X_COMP_Y_OVER BIT(8)
-#define BIT_SHIFT_AC1_PKT_INFO 16
-#define BIT_MASK_AC1_PKT_INFO 0xfff
-#define BIT_AC1_PKT_INFO(x) (((x) & BIT_MASK_AC1_PKT_INFO) << BIT_SHIFT_AC1_PKT_INFO)
-#define BIT_GET_AC1_PKT_INFO(x) (((x) >> BIT_SHIFT_AC1_PKT_INFO) & BIT_MASK_AC1_PKT_INFO)
+#endif
+#if (HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_AC0_PKT_INFO 0
-#define BIT_MASK_AC0_PKT_INFO 0xfff
-#define BIT_AC0_PKT_INFO(x) (((x) & BIT_MASK_AC0_PKT_INFO) << BIT_SHIFT_AC0_PKT_INFO)
-#define BIT_GET_AC0_PKT_INFO(x) (((x) >> BIT_SHIFT_AC0_PKT_INFO) & BIT_MASK_AC0_PKT_INFO)
+/* 2 REG_TSF_SYN_CTRL0 (Offset 0x1520) */
+#define BIT_TSF_SYNC_COMPARE_POLLING BIT(7)
+#define BIT_TSF_SYNC_POLLING BIT(6)
-/* 2 REG_Q2_Q3_INFO (Offset 0x1404) */
+#define BIT_SHIFT_TSF_SYNC_DUT 3
+#define BIT_MASK_TSF_SYNC_DUT 0x7
+#define BIT_TSF_SYNC_DUT(x) \
+ (((x) & BIT_MASK_TSF_SYNC_DUT) << BIT_SHIFT_TSF_SYNC_DUT)
+#define BITS_TSF_SYNC_DUT (BIT_MASK_TSF_SYNC_DUT << BIT_SHIFT_TSF_SYNC_DUT)
+#define BIT_CLEAR_TSF_SYNC_DUT(x) ((x) & (~BITS_TSF_SYNC_DUT))
+#define BIT_GET_TSF_SYNC_DUT(x) \
+ (((x) >> BIT_SHIFT_TSF_SYNC_DUT) & BIT_MASK_TSF_SYNC_DUT)
+#define BIT_SET_TSF_SYNC_DUT(x, v) \
+ (BIT_CLEAR_TSF_SYNC_DUT(x) | BIT_TSF_SYNC_DUT(v))
+#endif
-#define BIT_SHIFT_AC3_PKT_INFO 16
-#define BIT_MASK_AC3_PKT_INFO 0xfff
-#define BIT_AC3_PKT_INFO(x) (((x) & BIT_MASK_AC3_PKT_INFO) << BIT_SHIFT_AC3_PKT_INFO)
-#define BIT_GET_AC3_PKT_INFO(x) (((x) >> BIT_SHIFT_AC3_PKT_INFO) & BIT_MASK_AC3_PKT_INFO)
+#if (HALMAC_8822C_SUPPORT)
+/* 2 REG_TSF_SYNC_ADJ (Offset 0x1520) */
-#define BIT_SHIFT_AC2_PKT_INFO 0
-#define BIT_MASK_AC2_PKT_INFO 0xfff
-#define BIT_AC2_PKT_INFO(x) (((x) & BIT_MASK_AC2_PKT_INFO) << BIT_SHIFT_AC2_PKT_INFO)
-#define BIT_GET_AC2_PKT_INFO(x) (((x) >> BIT_SHIFT_AC2_PKT_INFO) & BIT_MASK_AC2_PKT_INFO)
+#define BIT_SHIFT_R_X_SYNC_SEL 3
+#define BIT_MASK_R_X_SYNC_SEL 0x7
+#define BIT_R_X_SYNC_SEL(x) \
+ (((x) & BIT_MASK_R_X_SYNC_SEL) << BIT_SHIFT_R_X_SYNC_SEL)
+#define BITS_R_X_SYNC_SEL (BIT_MASK_R_X_SYNC_SEL << BIT_SHIFT_R_X_SYNC_SEL)
+#define BIT_CLEAR_R_X_SYNC_SEL(x) ((x) & (~BITS_R_X_SYNC_SEL))
+#define BIT_GET_R_X_SYNC_SEL(x) \
+ (((x) >> BIT_SHIFT_R_X_SYNC_SEL) & BIT_MASK_R_X_SYNC_SEL)
+#define BIT_SET_R_X_SYNC_SEL(x, v) \
+ (BIT_CLEAR_R_X_SYNC_SEL(x) | BIT_R_X_SYNC_SEL(v))
+#endif
-/* 2 REG_Q4_Q5_INFO (Offset 0x1408) */
+#if (HALMAC_8198F_SUPPORT)
+/* 2 REG_TSF_SYN_CTRL0 (Offset 0x1520) */
-#define BIT_SHIFT_AC5_PKT_INFO 16
-#define BIT_MASK_AC5_PKT_INFO 0xfff
-#define BIT_AC5_PKT_INFO(x) (((x) & BIT_MASK_AC5_PKT_INFO) << BIT_SHIFT_AC5_PKT_INFO)
-#define BIT_GET_AC5_PKT_INFO(x) (((x) >> BIT_SHIFT_AC5_PKT_INFO) & BIT_MASK_AC5_PKT_INFO)
+#define BIT_SHIFT_TSF_SYNC_SOURCE 0
+#define BIT_MASK_TSF_SYNC_SOURCE 0x7
+#define BIT_TSF_SYNC_SOURCE(x) \
+ (((x) & BIT_MASK_TSF_SYNC_SOURCE) << BIT_SHIFT_TSF_SYNC_SOURCE)
+#define BITS_TSF_SYNC_SOURCE \
+ (BIT_MASK_TSF_SYNC_SOURCE << BIT_SHIFT_TSF_SYNC_SOURCE)
+#define BIT_CLEAR_TSF_SYNC_SOURCE(x) ((x) & (~BITS_TSF_SYNC_SOURCE))
+#define BIT_GET_TSF_SYNC_SOURCE(x) \
+ (((x) >> BIT_SHIFT_TSF_SYNC_SOURCE) & BIT_MASK_TSF_SYNC_SOURCE)
+#define BIT_SET_TSF_SYNC_SOURCE(x, v) \
+ (BIT_CLEAR_TSF_SYNC_SOURCE(x) | BIT_TSF_SYNC_SOURCE(v))
+#define BIT_TSF_SYNC_SIGNAL BIT(0)
-#define BIT_SHIFT_AC4_PKT_INFO 0
-#define BIT_MASK_AC4_PKT_INFO 0xfff
-#define BIT_AC4_PKT_INFO(x) (((x) & BIT_MASK_AC4_PKT_INFO) << BIT_SHIFT_AC4_PKT_INFO)
-#define BIT_GET_AC4_PKT_INFO(x) (((x) >> BIT_SHIFT_AC4_PKT_INFO) & BIT_MASK_AC4_PKT_INFO)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-/* 2 REG_Q6_Q7_INFO (Offset 0x140C) */
+/* 2 REG_TSFTR_LOW (Offset 0x1520) */
+#define BIT_SHIFT_TSF_TIMER_LOW 0
+#define BIT_MASK_TSF_TIMER_LOW 0xffffffffL
+#define BIT_TSF_TIMER_LOW(x) \
+ (((x) & BIT_MASK_TSF_TIMER_LOW) << BIT_SHIFT_TSF_TIMER_LOW)
+#define BITS_TSF_TIMER_LOW (BIT_MASK_TSF_TIMER_LOW << BIT_SHIFT_TSF_TIMER_LOW)
+#define BIT_CLEAR_TSF_TIMER_LOW(x) ((x) & (~BITS_TSF_TIMER_LOW))
+#define BIT_GET_TSF_TIMER_LOW(x) \
+ (((x) >> BIT_SHIFT_TSF_TIMER_LOW) & BIT_MASK_TSF_TIMER_LOW)
+#define BIT_SET_TSF_TIMER_LOW(x, v) \
+ (BIT_CLEAR_TSF_TIMER_LOW(x) | BIT_TSF_TIMER_LOW(v))
-#define BIT_SHIFT_AC7_PKT_INFO 16
-#define BIT_MASK_AC7_PKT_INFO 0xfff
-#define BIT_AC7_PKT_INFO(x) (((x) & BIT_MASK_AC7_PKT_INFO) << BIT_SHIFT_AC7_PKT_INFO)
-#define BIT_GET_AC7_PKT_INFO(x) (((x) >> BIT_SHIFT_AC7_PKT_INFO) & BIT_MASK_AC7_PKT_INFO)
+#endif
+#if (HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_AC6_PKT_INFO 0
-#define BIT_MASK_AC6_PKT_INFO 0xfff
-#define BIT_AC6_PKT_INFO(x) (((x) & BIT_MASK_AC6_PKT_INFO) << BIT_SHIFT_AC6_PKT_INFO)
-#define BIT_GET_AC6_PKT_INFO(x) (((x) >> BIT_SHIFT_AC6_PKT_INFO) & BIT_MASK_AC6_PKT_INFO)
+/* 2 REG_TSF_SYNC_ADJ (Offset 0x1520) */
+#define BIT_SHIFT_R_SYNC_Y_SEL 0
+#define BIT_MASK_R_SYNC_Y_SEL 0x7
+#define BIT_R_SYNC_Y_SEL(x) \
+ (((x) & BIT_MASK_R_SYNC_Y_SEL) << BIT_SHIFT_R_SYNC_Y_SEL)
+#define BITS_R_SYNC_Y_SEL (BIT_MASK_R_SYNC_Y_SEL << BIT_SHIFT_R_SYNC_Y_SEL)
+#define BIT_CLEAR_R_SYNC_Y_SEL(x) ((x) & (~BITS_R_SYNC_Y_SEL))
+#define BIT_GET_R_SYNC_Y_SEL(x) \
+ (((x) >> BIT_SHIFT_R_SYNC_Y_SEL) & BIT_MASK_R_SYNC_Y_SEL)
+#define BIT_SET_R_SYNC_Y_SEL(x, v) \
+ (BIT_CLEAR_R_SYNC_Y_SEL(x) | BIT_R_SYNC_Y_SEL(v))
-/* 2 REG_MGQ_HIQ_INFO (Offset 0x1410) */
+#endif
+#if (HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_HIQ_PKT_INFO 16
-#define BIT_MASK_HIQ_PKT_INFO 0xfff
-#define BIT_HIQ_PKT_INFO(x) (((x) & BIT_MASK_HIQ_PKT_INFO) << BIT_SHIFT_HIQ_PKT_INFO)
-#define BIT_GET_HIQ_PKT_INFO(x) (((x) >> BIT_SHIFT_HIQ_PKT_INFO) & BIT_MASK_HIQ_PKT_INFO)
+/* 2 REG_TSF_SYN_OFFSET0 (Offset 0x1522) */
+#define BIT_SHIFT_TSF_SYNC_INTERVAL_PORT0 0
+#define BIT_MASK_TSF_SYNC_INTERVAL_PORT0 0xffff
+#define BIT_TSF_SYNC_INTERVAL_PORT0(x) \
+ (((x) & BIT_MASK_TSF_SYNC_INTERVAL_PORT0) \
+ << BIT_SHIFT_TSF_SYNC_INTERVAL_PORT0)
+#define BITS_TSF_SYNC_INTERVAL_PORT0 \
+ (BIT_MASK_TSF_SYNC_INTERVAL_PORT0 << BIT_SHIFT_TSF_SYNC_INTERVAL_PORT0)
+#define BIT_CLEAR_TSF_SYNC_INTERVAL_PORT0(x) \
+ ((x) & (~BITS_TSF_SYNC_INTERVAL_PORT0))
+#define BIT_GET_TSF_SYNC_INTERVAL_PORT0(x) \
+ (((x) >> BIT_SHIFT_TSF_SYNC_INTERVAL_PORT0) & \
+ BIT_MASK_TSF_SYNC_INTERVAL_PORT0)
+#define BIT_SET_TSF_SYNC_INTERVAL_PORT0(x, v) \
+ (BIT_CLEAR_TSF_SYNC_INTERVAL_PORT0(x) | BIT_TSF_SYNC_INTERVAL_PORT0(v))
-#define BIT_SHIFT_MGQ_PKT_INFO 0
-#define BIT_MASK_MGQ_PKT_INFO 0xfff
-#define BIT_MGQ_PKT_INFO(x) (((x) & BIT_MASK_MGQ_PKT_INFO) << BIT_SHIFT_MGQ_PKT_INFO)
-#define BIT_GET_MGQ_PKT_INFO(x) (((x) >> BIT_SHIFT_MGQ_PKT_INFO) & BIT_MASK_MGQ_PKT_INFO)
+/* 2 REG_TSF_SYN_OFFSET1 (Offset 0x1524) */
+#define BIT_SHIFT_TSF_SYNC_INTERVAL_CLI1 16
+#define BIT_MASK_TSF_SYNC_INTERVAL_CLI1 0xffff
+#define BIT_TSF_SYNC_INTERVAL_CLI1(x) \
+ (((x) & BIT_MASK_TSF_SYNC_INTERVAL_CLI1) \
+ << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI1)
+#define BITS_TSF_SYNC_INTERVAL_CLI1 \
+ (BIT_MASK_TSF_SYNC_INTERVAL_CLI1 << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI1)
+#define BIT_CLEAR_TSF_SYNC_INTERVAL_CLI1(x) \
+ ((x) & (~BITS_TSF_SYNC_INTERVAL_CLI1))
+#define BIT_GET_TSF_SYNC_INTERVAL_CLI1(x) \
+ (((x) >> BIT_SHIFT_TSF_SYNC_INTERVAL_CLI1) & \
+ BIT_MASK_TSF_SYNC_INTERVAL_CLI1)
+#define BIT_SET_TSF_SYNC_INTERVAL_CLI1(x, v) \
+ (BIT_CLEAR_TSF_SYNC_INTERVAL_CLI1(x) | BIT_TSF_SYNC_INTERVAL_CLI1(v))
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_TSF_ADJ_VLAUE (Offset 0x1524) */
+#define BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL 16
+#define BIT_MASK_R_CLI1_TSFT_ADJ_VAL 0xffff
+#define BIT_R_CLI1_TSFT_ADJ_VAL(x) \
+ (((x) & BIT_MASK_R_CLI1_TSFT_ADJ_VAL) << BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL)
+#define BITS_R_CLI1_TSFT_ADJ_VAL \
+ (BIT_MASK_R_CLI1_TSFT_ADJ_VAL << BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL)
+#define BIT_CLEAR_R_CLI1_TSFT_ADJ_VAL(x) ((x) & (~BITS_R_CLI1_TSFT_ADJ_VAL))
+#define BIT_GET_R_CLI1_TSFT_ADJ_VAL(x) \
+ (((x) >> BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL) & BIT_MASK_R_CLI1_TSFT_ADJ_VAL)
+#define BIT_SET_R_CLI1_TSFT_ADJ_VAL(x, v) \
+ (BIT_CLEAR_R_CLI1_TSFT_ADJ_VAL(x) | BIT_R_CLI1_TSFT_ADJ_VAL(v))
-/* 2 REG_CMDQ_BCNQ_INFO (Offset 0x1414) */
+#endif
+#if (HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_BCNQ_PKT_INFO_V1 16
-#define BIT_MASK_BCNQ_PKT_INFO_V1 0xfff
-#define BIT_BCNQ_PKT_INFO_V1(x) (((x) & BIT_MASK_BCNQ_PKT_INFO_V1) << BIT_SHIFT_BCNQ_PKT_INFO_V1)
-#define BIT_GET_BCNQ_PKT_INFO_V1(x) (((x) >> BIT_SHIFT_BCNQ_PKT_INFO_V1) & BIT_MASK_BCNQ_PKT_INFO_V1)
+/* 2 REG_TSF_SYN_OFFSET1 (Offset 0x1524) */
+#define BIT_SHIFT_TSF_SYNC_INTERVAL_CLI0 0
+#define BIT_MASK_TSF_SYNC_INTERVAL_CLI0 0xffff
+#define BIT_TSF_SYNC_INTERVAL_CLI0(x) \
+ (((x) & BIT_MASK_TSF_SYNC_INTERVAL_CLI0) \
+ << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI0)
+#define BITS_TSF_SYNC_INTERVAL_CLI0 \
+ (BIT_MASK_TSF_SYNC_INTERVAL_CLI0 << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI0)
+#define BIT_CLEAR_TSF_SYNC_INTERVAL_CLI0(x) \
+ ((x) & (~BITS_TSF_SYNC_INTERVAL_CLI0))
+#define BIT_GET_TSF_SYNC_INTERVAL_CLI0(x) \
+ (((x) >> BIT_SHIFT_TSF_SYNC_INTERVAL_CLI0) & \
+ BIT_MASK_TSF_SYNC_INTERVAL_CLI0)
+#define BIT_SET_TSF_SYNC_INTERVAL_CLI0(x, v) \
+ (BIT_CLEAR_TSF_SYNC_INTERVAL_CLI0(x) | BIT_TSF_SYNC_INTERVAL_CLI0(v))
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_TSFTR_HIGH (Offset 0x1524) */
+#define BIT_SHIFT_TSF_TIMER_HIGH 0
+#define BIT_MASK_TSF_TIMER_HIGH 0xffffffffL
+#define BIT_TSF_TIMER_HIGH(x) \
+ (((x) & BIT_MASK_TSF_TIMER_HIGH) << BIT_SHIFT_TSF_TIMER_HIGH)
+#define BITS_TSF_TIMER_HIGH \
+ (BIT_MASK_TSF_TIMER_HIGH << BIT_SHIFT_TSF_TIMER_HIGH)
+#define BIT_CLEAR_TSF_TIMER_HIGH(x) ((x) & (~BITS_TSF_TIMER_HIGH))
+#define BIT_GET_TSF_TIMER_HIGH(x) \
+ (((x) >> BIT_SHIFT_TSF_TIMER_HIGH) & BIT_MASK_TSF_TIMER_HIGH)
+#define BIT_SET_TSF_TIMER_HIGH(x, v) \
+ (BIT_CLEAR_TSF_TIMER_HIGH(x) | BIT_TSF_TIMER_HIGH(v))
-/* 2 REG_CMDQ_BCNQ_INFO (Offset 0x1414) */
+#endif
+#if (HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_CMDQ_PKT_INFO 16
-#define BIT_MASK_CMDQ_PKT_INFO 0xfff
-#define BIT_CMDQ_PKT_INFO(x) (((x) & BIT_MASK_CMDQ_PKT_INFO) << BIT_SHIFT_CMDQ_PKT_INFO)
-#define BIT_GET_CMDQ_PKT_INFO(x) (((x) >> BIT_SHIFT_CMDQ_PKT_INFO) & BIT_MASK_CMDQ_PKT_INFO)
+/* 2 REG_TSF_ADJ_VLAUE (Offset 0x1524) */
+#define BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL 0
+#define BIT_MASK_R_CLI0_TSFT_ADJ_VAL 0xffff
+#define BIT_R_CLI0_TSFT_ADJ_VAL(x) \
+ (((x) & BIT_MASK_R_CLI0_TSFT_ADJ_VAL) << BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL)
+#define BITS_R_CLI0_TSFT_ADJ_VAL \
+ (BIT_MASK_R_CLI0_TSFT_ADJ_VAL << BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL)
+#define BIT_CLEAR_R_CLI0_TSFT_ADJ_VAL(x) ((x) & (~BITS_R_CLI0_TSFT_ADJ_VAL))
+#define BIT_GET_R_CLI0_TSFT_ADJ_VAL(x) \
+ (((x) >> BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL) & BIT_MASK_R_CLI0_TSFT_ADJ_VAL)
+#define BIT_SET_R_CLI0_TSFT_ADJ_VAL(x, v) \
+ (BIT_CLEAR_R_CLI0_TSFT_ADJ_VAL(x) | BIT_R_CLI0_TSFT_ADJ_VAL(v))
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+/* 2 REG_TSF_SYN_OFFSET2 (Offset 0x1528) */
+#define BIT_SHIFT_TSF_SYNC_INTERVAL_CLI3 16
+#define BIT_MASK_TSF_SYNC_INTERVAL_CLI3 0xffff
+#define BIT_TSF_SYNC_INTERVAL_CLI3(x) \
+ (((x) & BIT_MASK_TSF_SYNC_INTERVAL_CLI3) \
+ << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI3)
+#define BITS_TSF_SYNC_INTERVAL_CLI3 \
+ (BIT_MASK_TSF_SYNC_INTERVAL_CLI3 << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI3)
+#define BIT_CLEAR_TSF_SYNC_INTERVAL_CLI3(x) \
+ ((x) & (~BITS_TSF_SYNC_INTERVAL_CLI3))
+#define BIT_GET_TSF_SYNC_INTERVAL_CLI3(x) \
+ (((x) >> BIT_SHIFT_TSF_SYNC_INTERVAL_CLI3) & \
+ BIT_MASK_TSF_SYNC_INTERVAL_CLI3)
+#define BIT_SET_TSF_SYNC_INTERVAL_CLI3(x, v) \
+ (BIT_CLEAR_TSF_SYNC_INTERVAL_CLI3(x) | BIT_TSF_SYNC_INTERVAL_CLI3(v))
-/* 2 REG_CMDQ_BCNQ_INFO (Offset 0x1414) */
+#endif
-#define BIT_CHNL_REF_RXNAV BIT(7)
-#define BIT_CHNL_REF_VBON BIT(6)
-#define BIT_CHNL_REF_EDCCA BIT(5)
-#define BIT_RST_CHNL_BUSY BIT(3)
-#define BIT_RST_CHNL_IDLE BIT(2)
-#define BIT_CHNL_INFO_RST BIT(1)
+#if (HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_CMDQ_PKT_INFO_V1 0
-#define BIT_MASK_CMDQ_PKT_INFO_V1 0xfff
-#define BIT_CMDQ_PKT_INFO_V1(x) (((x) & BIT_MASK_CMDQ_PKT_INFO_V1) << BIT_SHIFT_CMDQ_PKT_INFO_V1)
-#define BIT_GET_CMDQ_PKT_INFO_V1(x) (((x) >> BIT_SHIFT_CMDQ_PKT_INFO_V1) & BIT_MASK_CMDQ_PKT_INFO_V1)
+/* 2 REG_TSF_ADJ_VLAUE_2 (Offset 0x1528) */
-#define BIT_ATM_AIRTIME_EN BIT(0)
+#define BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL 16
+#define BIT_MASK_R_CLI3_TSFT_ADJ_VAL 0xffff
+#define BIT_R_CLI3_TSFT_ADJ_VAL(x) \
+ (((x) & BIT_MASK_R_CLI3_TSFT_ADJ_VAL) << BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL)
+#define BITS_R_CLI3_TSFT_ADJ_VAL \
+ (BIT_MASK_R_CLI3_TSFT_ADJ_VAL << BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL)
+#define BIT_CLEAR_R_CLI3_TSFT_ADJ_VAL(x) ((x) & (~BITS_R_CLI3_TSFT_ADJ_VAL))
+#define BIT_GET_R_CLI3_TSFT_ADJ_VAL(x) \
+ (((x) >> BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL) & BIT_MASK_R_CLI3_TSFT_ADJ_VAL)
+#define BIT_SET_R_CLI3_TSFT_ADJ_VAL(x, v) \
+ (BIT_CLEAR_R_CLI3_TSFT_ADJ_VAL(x) | BIT_R_CLI3_TSFT_ADJ_VAL(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
-#define BIT_SHIFT_CHNL_IDLE_TIME 0
-#define BIT_MASK_CHNL_IDLE_TIME 0xffffffffL
-#define BIT_CHNL_IDLE_TIME(x) (((x) & BIT_MASK_CHNL_IDLE_TIME) << BIT_SHIFT_CHNL_IDLE_TIME)
-#define BIT_GET_CHNL_IDLE_TIME(x) (((x) >> BIT_SHIFT_CHNL_IDLE_TIME) & BIT_MASK_CHNL_IDLE_TIME)
+/* 2 REG_TSF_SYN_OFFSET2 (Offset 0x1528) */
+
+#define BIT_SHIFT_TSF_SYNC_INTERVAL_CLI2 0
+#define BIT_MASK_TSF_SYNC_INTERVAL_CLI2 0xffff
+#define BIT_TSF_SYNC_INTERVAL_CLI2(x) \
+ (((x) & BIT_MASK_TSF_SYNC_INTERVAL_CLI2) \
+ << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI2)
+#define BITS_TSF_SYNC_INTERVAL_CLI2 \
+ (BIT_MASK_TSF_SYNC_INTERVAL_CLI2 << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI2)
+#define BIT_CLEAR_TSF_SYNC_INTERVAL_CLI2(x) \
+ ((x) & (~BITS_TSF_SYNC_INTERVAL_CLI2))
+#define BIT_GET_TSF_SYNC_INTERVAL_CLI2(x) \
+ (((x) >> BIT_SHIFT_TSF_SYNC_INTERVAL_CLI2) & \
+ BIT_MASK_TSF_SYNC_INTERVAL_CLI2)
+#define BIT_SET_TSF_SYNC_INTERVAL_CLI2(x, v) \
+ (BIT_CLEAR_TSF_SYNC_INTERVAL_CLI2(x) | BIT_TSF_SYNC_INTERVAL_CLI2(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_BCN_ERR_CNT_MAC (Offset 0x1528) */
+
+#define BIT_SHIFT_BCN_ERR_CNT_MAC 0
+#define BIT_MASK_BCN_ERR_CNT_MAC 0xff
+#define BIT_BCN_ERR_CNT_MAC(x) \
+ (((x) & BIT_MASK_BCN_ERR_CNT_MAC) << BIT_SHIFT_BCN_ERR_CNT_MAC)
+#define BITS_BCN_ERR_CNT_MAC \
+ (BIT_MASK_BCN_ERR_CNT_MAC << BIT_SHIFT_BCN_ERR_CNT_MAC)
+#define BIT_CLEAR_BCN_ERR_CNT_MAC(x) ((x) & (~BITS_BCN_ERR_CNT_MAC))
+#define BIT_GET_BCN_ERR_CNT_MAC(x) \
+ (((x) >> BIT_SHIFT_BCN_ERR_CNT_MAC) & BIT_MASK_BCN_ERR_CNT_MAC)
+#define BIT_SET_BCN_ERR_CNT_MAC(x, v) \
+ (BIT_CLEAR_BCN_ERR_CNT_MAC(x) | BIT_BCN_ERR_CNT_MAC(v))
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+/* 2 REG_TSF_ADJ_VLAUE_2 (Offset 0x1528) */
+
+#define BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL 0
+#define BIT_MASK_R_CLI2_TSFT_ADJ_VAL 0xffff
+#define BIT_R_CLI2_TSFT_ADJ_VAL(x) \
+ (((x) & BIT_MASK_R_CLI2_TSFT_ADJ_VAL) << BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL)
+#define BITS_R_CLI2_TSFT_ADJ_VAL \
+ (BIT_MASK_R_CLI2_TSFT_ADJ_VAL << BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL)
+#define BIT_CLEAR_R_CLI2_TSFT_ADJ_VAL(x) ((x) & (~BITS_R_CLI2_TSFT_ADJ_VAL))
+#define BIT_GET_R_CLI2_TSFT_ADJ_VAL(x) \
+ (((x) >> BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL) & BIT_MASK_R_CLI2_TSFT_ADJ_VAL)
+#define BIT_SET_R_CLI2_TSFT_ADJ_VAL(x, v) \
+ (BIT_CLEAR_R_CLI2_TSFT_ADJ_VAL(x) | BIT_R_CLI2_TSFT_ADJ_VAL(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_BCN_ERR_CNT_EDCCA (Offset 0x1529) */
+
+#define BIT_SHIFT_BCN_ERR_CNT_EDCCA 0
+#define BIT_MASK_BCN_ERR_CNT_EDCCA 0xff
+#define BIT_BCN_ERR_CNT_EDCCA(x) \
+ (((x) & BIT_MASK_BCN_ERR_CNT_EDCCA) << BIT_SHIFT_BCN_ERR_CNT_EDCCA)
+#define BITS_BCN_ERR_CNT_EDCCA \
+ (BIT_MASK_BCN_ERR_CNT_EDCCA << BIT_SHIFT_BCN_ERR_CNT_EDCCA)
+#define BIT_CLEAR_BCN_ERR_CNT_EDCCA(x) ((x) & (~BITS_BCN_ERR_CNT_EDCCA))
+#define BIT_GET_BCN_ERR_CNT_EDCCA(x) \
+ (((x) >> BIT_SHIFT_BCN_ERR_CNT_EDCCA) & BIT_MASK_BCN_ERR_CNT_EDCCA)
+#define BIT_SET_BCN_ERR_CNT_EDCCA(x, v) \
+ (BIT_CLEAR_BCN_ERR_CNT_EDCCA(x) | BIT_BCN_ERR_CNT_EDCCA(v))
+
+/* 2 REG_BCN_ERR_CNT_CCA (Offset 0x152A) */
+
+#define BIT_SHIFT_BCN_ERR_CNT_CCA 0
+#define BIT_MASK_BCN_ERR_CNT_CCA 0xff
+#define BIT_BCN_ERR_CNT_CCA(x) \
+ (((x) & BIT_MASK_BCN_ERR_CNT_CCA) << BIT_SHIFT_BCN_ERR_CNT_CCA)
+#define BITS_BCN_ERR_CNT_CCA \
+ (BIT_MASK_BCN_ERR_CNT_CCA << BIT_SHIFT_BCN_ERR_CNT_CCA)
+#define BIT_CLEAR_BCN_ERR_CNT_CCA(x) ((x) & (~BITS_BCN_ERR_CNT_CCA))
+#define BIT_GET_BCN_ERR_CNT_CCA(x) \
+ (((x) >> BIT_SHIFT_BCN_ERR_CNT_CCA) & BIT_MASK_BCN_ERR_CNT_CCA)
+#define BIT_SET_BCN_ERR_CNT_CCA(x, v) \
+ (BIT_CLEAR_BCN_ERR_CNT_CCA(x) | BIT_BCN_ERR_CNT_CCA(v))
+
+/* 2 REG_BCN_ERR_CNT_INVALID (Offset 0x152B) */
+
+#define BIT_SHIFT_BCN_ERR_CNT_INVALID 0
+#define BIT_MASK_BCN_ERR_CNT_INVALID 0xff
+#define BIT_BCN_ERR_CNT_INVALID(x) \
+ (((x) & BIT_MASK_BCN_ERR_CNT_INVALID) << BIT_SHIFT_BCN_ERR_CNT_INVALID)
+#define BITS_BCN_ERR_CNT_INVALID \
+ (BIT_MASK_BCN_ERR_CNT_INVALID << BIT_SHIFT_BCN_ERR_CNT_INVALID)
+#define BIT_CLEAR_BCN_ERR_CNT_INVALID(x) ((x) & (~BITS_BCN_ERR_CNT_INVALID))
+#define BIT_GET_BCN_ERR_CNT_INVALID(x) \
+ (((x) >> BIT_SHIFT_BCN_ERR_CNT_INVALID) & BIT_MASK_BCN_ERR_CNT_INVALID)
+#define BIT_SET_BCN_ERR_CNT_INVALID(x, v) \
+ (BIT_CLEAR_BCN_ERR_CNT_INVALID(x) | BIT_BCN_ERR_CNT_INVALID(v))
+
+/* 2 REG_BCN_ERR_CNT_OTHERS (Offset 0x152C) */
+
+#define BIT_SHIFT_BCN_ERR_CNT_OTHERS 0
+#define BIT_MASK_BCN_ERR_CNT_OTHERS 0xff
+#define BIT_BCN_ERR_CNT_OTHERS(x) \
+ (((x) & BIT_MASK_BCN_ERR_CNT_OTHERS) << BIT_SHIFT_BCN_ERR_CNT_OTHERS)
+#define BITS_BCN_ERR_CNT_OTHERS \
+ (BIT_MASK_BCN_ERR_CNT_OTHERS << BIT_SHIFT_BCN_ERR_CNT_OTHERS)
+#define BIT_CLEAR_BCN_ERR_CNT_OTHERS(x) ((x) & (~BITS_BCN_ERR_CNT_OTHERS))
+#define BIT_GET_BCN_ERR_CNT_OTHERS(x) \
+ (((x) >> BIT_SHIFT_BCN_ERR_CNT_OTHERS) & BIT_MASK_BCN_ERR_CNT_OTHERS)
+#define BIT_SET_BCN_ERR_CNT_OTHERS(x, v) \
+ (BIT_CLEAR_BCN_ERR_CNT_OTHERS(x) | BIT_BCN_ERR_CNT_OTHERS(v))
+
+/* 2 REG_RX_BCN_TIMER (Offset 0x152D) */
+
+#define BIT_SHIFT_RX_BCN_TIMER 0
+#define BIT_MASK_RX_BCN_TIMER 0xffff
+#define BIT_RX_BCN_TIMER(x) \
+ (((x) & BIT_MASK_RX_BCN_TIMER) << BIT_SHIFT_RX_BCN_TIMER)
+#define BITS_RX_BCN_TIMER (BIT_MASK_RX_BCN_TIMER << BIT_SHIFT_RX_BCN_TIMER)
+#define BIT_CLEAR_RX_BCN_TIMER(x) ((x) & (~BITS_RX_BCN_TIMER))
+#define BIT_GET_RX_BCN_TIMER(x) \
+ (((x) >> BIT_SHIFT_RX_BCN_TIMER) & BIT_MASK_RX_BCN_TIMER)
+#define BIT_SET_RX_BCN_TIMER(x, v) \
+ (BIT_CLEAR_RX_BCN_TIMER(x) | BIT_RX_BCN_TIMER(v))
+
+/* 2 REG_SUB_BCN_SPACE (Offset 0x1534) */
+
+#define BIT_SHIFT_SUB_BCN_SPACE_V2 0
+#define BIT_MASK_SUB_BCN_SPACE_V2 0xff
+#define BIT_SUB_BCN_SPACE_V2(x) \
+ (((x) & BIT_MASK_SUB_BCN_SPACE_V2) << BIT_SHIFT_SUB_BCN_SPACE_V2)
+#define BITS_SUB_BCN_SPACE_V2 \
+ (BIT_MASK_SUB_BCN_SPACE_V2 << BIT_SHIFT_SUB_BCN_SPACE_V2)
+#define BIT_CLEAR_SUB_BCN_SPACE_V2(x) ((x) & (~BITS_SUB_BCN_SPACE_V2))
+#define BIT_GET_SUB_BCN_SPACE_V2(x) \
+ (((x) >> BIT_SHIFT_SUB_BCN_SPACE_V2) & BIT_MASK_SUB_BCN_SPACE_V2)
+#define BIT_SET_SUB_BCN_SPACE_V2(x, v) \
+ (BIT_CLEAR_SUB_BCN_SPACE_V2(x) | BIT_SUB_BCN_SPACE_V2(v))
+
+/* 2 REG_MBID_NUM_V1 (Offset 0x1535) */
+
+#define BIT_SHIFT_BCN_ERR_PORT_SEL 4
+#define BIT_MASK_BCN_ERR_PORT_SEL 0xf
+#define BIT_BCN_ERR_PORT_SEL(x) \
+ (((x) & BIT_MASK_BCN_ERR_PORT_SEL) << BIT_SHIFT_BCN_ERR_PORT_SEL)
+#define BITS_BCN_ERR_PORT_SEL \
+ (BIT_MASK_BCN_ERR_PORT_SEL << BIT_SHIFT_BCN_ERR_PORT_SEL)
+#define BIT_CLEAR_BCN_ERR_PORT_SEL(x) ((x) & (~BITS_BCN_ERR_PORT_SEL))
+#define BIT_GET_BCN_ERR_PORT_SEL(x) \
+ (((x) >> BIT_SHIFT_BCN_ERR_PORT_SEL) & BIT_MASK_BCN_ERR_PORT_SEL)
+#define BIT_SET_BCN_ERR_PORT_SEL(x, v) \
+ (BIT_CLEAR_BCN_ERR_PORT_SEL(x) | BIT_BCN_ERR_PORT_SEL(v))
+
+#define BIT_SHIFT_MBID_BCN_NUM_V1 0
+#define BIT_MASK_MBID_BCN_NUM_V1 0xf
+#define BIT_MBID_BCN_NUM_V1(x) \
+ (((x) & BIT_MASK_MBID_BCN_NUM_V1) << BIT_SHIFT_MBID_BCN_NUM_V1)
+#define BITS_MBID_BCN_NUM_V1 \
+ (BIT_MASK_MBID_BCN_NUM_V1 << BIT_SHIFT_MBID_BCN_NUM_V1)
+#define BIT_CLEAR_MBID_BCN_NUM_V1(x) ((x) & (~BITS_MBID_BCN_NUM_V1))
+#define BIT_GET_MBID_BCN_NUM_V1(x) \
+ (((x) >> BIT_SHIFT_MBID_BCN_NUM_V1) & BIT_MASK_MBID_BCN_NUM_V1)
+#define BIT_SET_MBID_BCN_NUM_V1(x, v) \
+ (BIT_CLEAR_MBID_BCN_NUM_V1(x) | BIT_MBID_BCN_NUM_V1(v))
+
+/* 2 REG_MBSSID_CTRL_V1 (Offset 0x1536) */
+
+#define BIT_MBID_BCNQ15_EN BIT(15)
+#define BIT_MBID_BCNQ14_EN BIT(14)
+#define BIT_MBID_BCNQ13_EN BIT(13)
+#define BIT_MBID_BCNQ12_EN BIT(12)
+#define BIT_MBID_BCNQ11_EN BIT(11)
+#define BIT_MBID_BCNQ10_EN BIT(10)
+#define BIT_MBID_BCNQ9_EN BIT(9)
+#define BIT_MBID_BCNQ8_EN BIT(8)
+
+/* 2 REG_BW_CFG (Offset 0x1539) */
+
+#define BIT_SLEEP_32K_EN BIT(3)
+#define BIT_DIS_MARK_TSF_US_V1 BIT(2)
+
+/* 2 REG_ATIMWND_CFG (Offset 0x153A) */
+
+#define BIT_SHIFT_ATIMWND_V1 0
+#define BIT_MASK_ATIMWND_V1 0xff
+#define BIT_ATIMWND_V1(x) (((x) & BIT_MASK_ATIMWND_V1) << BIT_SHIFT_ATIMWND_V1)
+#define BITS_ATIMWND_V1 (BIT_MASK_ATIMWND_V1 << BIT_SHIFT_ATIMWND_V1)
+#define BIT_CLEAR_ATIMWND_V1(x) ((x) & (~BITS_ATIMWND_V1))
+#define BIT_GET_ATIMWND_V1(x) \
+ (((x) >> BIT_SHIFT_ATIMWND_V1) & BIT_MASK_ATIMWND_V1)
+#define BIT_SET_ATIMWND_V1(x, v) (BIT_CLEAR_ATIMWND_V1(x) | BIT_ATIMWND_V1(v))
+
+/* 2 REG_DTIM_COUNTER_CFG (Offset 0x153B) */
+
+#define BIT_SHIFT_DTIM_COUNT 0
+#define BIT_MASK_DTIM_COUNT 0xff
+#define BIT_DTIM_COUNT(x) (((x) & BIT_MASK_DTIM_COUNT) << BIT_SHIFT_DTIM_COUNT)
+#define BITS_DTIM_COUNT (BIT_MASK_DTIM_COUNT << BIT_SHIFT_DTIM_COUNT)
+#define BIT_CLEAR_DTIM_COUNT(x) ((x) & (~BITS_DTIM_COUNT))
+#define BIT_GET_DTIM_COUNT(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT) & BIT_MASK_DTIM_COUNT)
+#define BIT_SET_DTIM_COUNT(x, v) (BIT_CLEAR_DTIM_COUNT(x) | BIT_DTIM_COUNT(v))
+
+/* 2 REG_ATIM_DTIM_CTRL_SEL (Offset 0x153C) */
+
+#define BIT_DTIM_BYPASS_V1 BIT(7)
+
+#define BIT_SHIFT_ATIM_DTIM_SEL 0
+#define BIT_MASK_ATIM_DTIM_SEL 0x1f
+#define BIT_ATIM_DTIM_SEL(x) \
+ (((x) & BIT_MASK_ATIM_DTIM_SEL) << BIT_SHIFT_ATIM_DTIM_SEL)
+#define BITS_ATIM_DTIM_SEL (BIT_MASK_ATIM_DTIM_SEL << BIT_SHIFT_ATIM_DTIM_SEL)
+#define BIT_CLEAR_ATIM_DTIM_SEL(x) ((x) & (~BITS_ATIM_DTIM_SEL))
+#define BIT_GET_ATIM_DTIM_SEL(x) \
+ (((x) >> BIT_SHIFT_ATIM_DTIM_SEL) & BIT_MASK_ATIM_DTIM_SEL)
+#define BIT_SET_ATIM_DTIM_SEL(x, v) \
+ (BIT_CLEAR_ATIM_DTIM_SEL(x) | BIT_ATIM_DTIM_SEL(v))
+
+/* 2 REG_DIS_ATIM_V1 (Offset 0x1540) */
+
+#define BIT_DIS_ATIM_P4 BIT(19)
+#define BIT_DIS_ATIM_P3 BIT(18)
+#define BIT_DIS_ATIM_P2 BIT(17)
+#define BIT_DIS_ATIM_P1 BIT(16)
+#define BIT_DIS_ATIM_VAP15 BIT(15)
+#define BIT_DIS_ATIM_VAP14 BIT(14)
+#define BIT_DIS_ATIM_VAP13 BIT(13)
+#define BIT_DIS_ATIM_VAP12 BIT(12)
+#define BIT_DIS_ATIM_VAP11 BIT(11)
+#define BIT_DIS_ATIM_VAP10 BIT(10)
+#define BIT_DIS_ATIM_VAP9 BIT(9)
+#define BIT_DIS_ATIM_VAP8 BIT(8)
+#define BIT_DIS_ATIM_ROOT_P0 BIT(0)
+
+/* 2 REG_HIQ_NO_LMT_EN_V1 (Offset 0x1544) */
+
+#define BIT_HIQ_NO_LMT_EN_P4 BIT(19)
+#define BIT_HIQ_NO_LMT_EN_P3 BIT(18)
+#define BIT_HIQ_NO_LMT_EN_P2 BIT(17)
+#define BIT_HIQ_NO_LMT_EN_P1 BIT(16)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIQ_NO_LMT_EN_V1 (Offset 0x1544) */
+
+#define BIT_HIQ_NO_LMT_EN_VAP15 BIT(15)
+#define BIT_HIQ_NO_LMT_EN_VAP14 BIT(14)
+#define BIT_HIQ_NO_LMT_EN_VAP13 BIT(13)
+#define BIT_HIQ_NO_LMT_EN_VAP12 BIT(12)
+#define BIT_HIQ_NO_LMT_EN_VAP11 BIT(11)
+#define BIT_HIQ_NO_LMT_EN_VAP10 BIT(10)
+#define BIT_HIQ_NO_LMT_EN_VAP9 BIT(9)
+#define BIT_HIQ_NO_LMT_EN_VAP8 BIT(8)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_HIQ_NO_LMT_EN_V1 (Offset 0x1544) */
+
+#define BIT_HIQ_NO_LMT_EN_ROOT_P0 BIT(0)
+
+/* 2 REG_P2PPS_CTRL_V1 (Offset 0x1548) */
+
+#define BIT_P2P_PWR_RST1_V2 BIT(15)
+#define BIT_P2P_PWR_RST0_V2 BIT(14)
+#define BIT_EN_TSFBIT32_RST_P2P_V1 BIT(13)
+
+#define BIT_SHIFT_NOA_UNIT0_SEL_V1 8
+#define BIT_MASK_NOA_UNIT0_SEL_V1 0x7
+#define BIT_NOA_UNIT0_SEL_V1(x) \
+ (((x) & BIT_MASK_NOA_UNIT0_SEL_V1) << BIT_SHIFT_NOA_UNIT0_SEL_V1)
+#define BITS_NOA_UNIT0_SEL_V1 \
+ (BIT_MASK_NOA_UNIT0_SEL_V1 << BIT_SHIFT_NOA_UNIT0_SEL_V1)
+#define BIT_CLEAR_NOA_UNIT0_SEL_V1(x) ((x) & (~BITS_NOA_UNIT0_SEL_V1))
+#define BIT_GET_NOA_UNIT0_SEL_V1(x) \
+ (((x) >> BIT_SHIFT_NOA_UNIT0_SEL_V1) & BIT_MASK_NOA_UNIT0_SEL_V1)
+#define BIT_SET_NOA_UNIT0_SEL_V1(x, v) \
+ (BIT_CLEAR_NOA_UNIT0_SEL_V1(x) | BIT_NOA_UNIT0_SEL_V1(v))
+
+#define BIT_P2P_CTW_ALLSTASLEEP_V1 BIT(7)
+#define BIT_P2P_OFF_DISTX_EN_V1 BIT(6)
+#define BIT_PWR_MGT_EN_V1 BIT(5)
+#define BIT_P2P_NOA1_EN_V1 BIT(2)
+#define BIT_P2P_NOA0_EN_V1 BIT(1)
+
+/* 2 REG_P2PPS1_CTRL_V1 (Offset 0x154C) */
+
+#define BIT_P2P1_PWR_RST1_V2 BIT(15)
+#define BIT_P2P1_PWR_RST0_V2 BIT(14)
+#define BIT_EN_TSFBIT32_RST_P2P1_V1 BIT(13)
+
+#define BIT_SHIFT_NOA_UNIT1_SEL_V1 8
+#define BIT_MASK_NOA_UNIT1_SEL_V1 0x7
+#define BIT_NOA_UNIT1_SEL_V1(x) \
+ (((x) & BIT_MASK_NOA_UNIT1_SEL_V1) << BIT_SHIFT_NOA_UNIT1_SEL_V1)
+#define BITS_NOA_UNIT1_SEL_V1 \
+ (BIT_MASK_NOA_UNIT1_SEL_V1 << BIT_SHIFT_NOA_UNIT1_SEL_V1)
+#define BIT_CLEAR_NOA_UNIT1_SEL_V1(x) ((x) & (~BITS_NOA_UNIT1_SEL_V1))
+#define BIT_GET_NOA_UNIT1_SEL_V1(x) \
+ (((x) >> BIT_SHIFT_NOA_UNIT1_SEL_V1) & BIT_MASK_NOA_UNIT1_SEL_V1)
+#define BIT_SET_NOA_UNIT1_SEL_V1(x, v) \
+ (BIT_CLEAR_NOA_UNIT1_SEL_V1(x) | BIT_NOA_UNIT1_SEL_V1(v))
+
+#define BIT_P2P1_CTW_ALLSTASLEEP_V1 BIT(7)
+#define BIT_P2P1_PWR_MGT_EN_V1 BIT(5)
+#define BIT_P2P1_NOA1_EN_V1 BIT(2)
+#define BIT_P2P1_NOA0_EN_V1 BIT(1)
+
+/* 2 REG_P2PPS1_SPEC_STATE_V1 (Offset 0x154E) */
+
+#define BIT_P2P1_SPEC_POWER_STATEP BIT(7)
+#define BIT_P2P1_SPEC_BEACON_AREA_ON BIT(5)
+
+/* 2 REG_P2PPS2_CTRL_V1 (Offset 0x1550) */
+
+#define BIT_P2P2_PWR_RST1_V2 BIT(15)
+#define BIT_P2P2_PWR_RST0_V2 BIT(14)
+#define BIT_EN_TSFBIT32_RST_P2P2_V1 BIT(13)
+
+#define BIT_SHIFT_NOA_UNIT2_SEL_V1 8
+#define BIT_MASK_NOA_UNIT2_SEL_V1 0x7
+#define BIT_NOA_UNIT2_SEL_V1(x) \
+ (((x) & BIT_MASK_NOA_UNIT2_SEL_V1) << BIT_SHIFT_NOA_UNIT2_SEL_V1)
+#define BITS_NOA_UNIT2_SEL_V1 \
+ (BIT_MASK_NOA_UNIT2_SEL_V1 << BIT_SHIFT_NOA_UNIT2_SEL_V1)
+#define BIT_CLEAR_NOA_UNIT2_SEL_V1(x) ((x) & (~BITS_NOA_UNIT2_SEL_V1))
+#define BIT_GET_NOA_UNIT2_SEL_V1(x) \
+ (((x) >> BIT_SHIFT_NOA_UNIT2_SEL_V1) & BIT_MASK_NOA_UNIT2_SEL_V1)
+#define BIT_SET_NOA_UNIT2_SEL_V1(x, v) \
+ (BIT_CLEAR_NOA_UNIT2_SEL_V1(x) | BIT_NOA_UNIT2_SEL_V1(v))
+
+#define BIT_P2P2_CTW_ALLSTASLEEP_V1 BIT(7)
+#define BIT_P2P2_OFF_DISTX_EN_V1 BIT(6)
+#define BIT_P2P2_PWR_MGT_EN_V1 BIT(5)
+#define BIT_P2P2_NOA1_EN_V1 BIT(2)
+#define BIT_P2P2_NOA0_EN_V1 BIT(1)
+
+/* 2 REG_P2PPS2_SPEC_STATE_V1 (Offset 0x1552) */
+
+#define BIT_P2P2_SPEC_POWER_STATEP BIT(7)
+#define BIT_P2P2_SPEC_BEACON_AREA_ON BIT(5)
+
+/* 2 REG_CHG_POWER_BCN_AREA (Offset 0x1556) */
+
+#define BIT_CHG_POWER_BCN_AREA BIT(0)
+
+/* 2 REG_NOA_SEL (Offset 0x1557) */
+
+#define BIT_SHIFT_NOA_SEL_V1 0
+#define BIT_MASK_NOA_SEL_V1 0x7
+#define BIT_NOA_SEL_V1(x) (((x) & BIT_MASK_NOA_SEL_V1) << BIT_SHIFT_NOA_SEL_V1)
+#define BITS_NOA_SEL_V1 (BIT_MASK_NOA_SEL_V1 << BIT_SHIFT_NOA_SEL_V1)
+#define BIT_CLEAR_NOA_SEL_V1(x) ((x) & (~BITS_NOA_SEL_V1))
+#define BIT_GET_NOA_SEL_V1(x) \
+ (((x) >> BIT_SHIFT_NOA_SEL_V1) & BIT_MASK_NOA_SEL_V1)
+#define BIT_SET_NOA_SEL_V1(x, v) (BIT_CLEAR_NOA_SEL_V1(x) | BIT_NOA_SEL_V1(v))
+
+/* 2 REG_NOA_PARAM_3_V1 (Offset 0x1564) */
+
+#define BIT_SHIFT_NOA_COUNT_V2 0
+#define BIT_MASK_NOA_COUNT_V2 0xffffffffL
+#define BIT_NOA_COUNT_V2(x) \
+ (((x) & BIT_MASK_NOA_COUNT_V2) << BIT_SHIFT_NOA_COUNT_V2)
+#define BITS_NOA_COUNT_V2 (BIT_MASK_NOA_COUNT_V2 << BIT_SHIFT_NOA_COUNT_V2)
+#define BIT_CLEAR_NOA_COUNT_V2(x) ((x) & (~BITS_NOA_COUNT_V2))
+#define BIT_GET_NOA_COUNT_V2(x) \
+ (((x) >> BIT_SHIFT_NOA_COUNT_V2) & BIT_MASK_NOA_COUNT_V2)
+#define BIT_SET_NOA_COUNT_V2(x, v) \
+ (BIT_CLEAR_NOA_COUNT_V2(x) | BIT_NOA_COUNT_V2(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_P2PPS_HW_AUTO_PAUSE_CTRL (Offset 0x156C) */
+
+#define BIT_P2PPS_NOA_STOP_TX_HANG BIT(31)
+#define BIT_P2PPS_MACID_PAUSE_EN BIT(11)
+#define BIT_P2PPS__MGQ_PAUSE BIT(10)
+#define BIT_P2PPS__HIQ_PAUSE BIT(9)
+#define BIT_P2PPS__BCNQ_PAUSE BIT(8)
+
+#define BIT_SHIFT_P2PPS_MACID_PAUSE 0
+#define BIT_MASK_P2PPS_MACID_PAUSE 0xff
+#define BIT_P2PPS_MACID_PAUSE(x) \
+ (((x) & BIT_MASK_P2PPS_MACID_PAUSE) << BIT_SHIFT_P2PPS_MACID_PAUSE)
+#define BITS_P2PPS_MACID_PAUSE \
+ (BIT_MASK_P2PPS_MACID_PAUSE << BIT_SHIFT_P2PPS_MACID_PAUSE)
+#define BIT_CLEAR_P2PPS_MACID_PAUSE(x) ((x) & (~BITS_P2PPS_MACID_PAUSE))
+#define BIT_GET_P2PPS_MACID_PAUSE(x) \
+ (((x) >> BIT_SHIFT_P2PPS_MACID_PAUSE) & BIT_MASK_P2PPS_MACID_PAUSE)
+#define BIT_SET_P2PPS_MACID_PAUSE(x, v) \
+ (BIT_CLEAR_P2PPS_MACID_PAUSE(x) | BIT_P2PPS_MACID_PAUSE(v))
+
+/* 2 REG_P2PPS1_HW_AUTO_PAUSE_CTRL (Offset 0x1570) */
+
+#define BIT_P2PPS1_NOA_STOP_TX_HANG BIT(31)
+#define BIT_P2PPS1_MACID_PAUSE_EN BIT(11)
+#define BIT_P2PPS1__MGQ_PAUSE BIT(10)
+#define BIT_P2PPS1__HIQ_PAUSE BIT(9)
+#define BIT_P2PPS1__BCNQ_PAUSE BIT(8)
+
+#define BIT_SHIFT_P2PPS1_MACID_PAUSE 0
+#define BIT_MASK_P2PPS1_MACID_PAUSE 0xff
+#define BIT_P2PPS1_MACID_PAUSE(x) \
+ (((x) & BIT_MASK_P2PPS1_MACID_PAUSE) << BIT_SHIFT_P2PPS1_MACID_PAUSE)
+#define BITS_P2PPS1_MACID_PAUSE \
+ (BIT_MASK_P2PPS1_MACID_PAUSE << BIT_SHIFT_P2PPS1_MACID_PAUSE)
+#define BIT_CLEAR_P2PPS1_MACID_PAUSE(x) ((x) & (~BITS_P2PPS1_MACID_PAUSE))
+#define BIT_GET_P2PPS1_MACID_PAUSE(x) \
+ (((x) >> BIT_SHIFT_P2PPS1_MACID_PAUSE) & BIT_MASK_P2PPS1_MACID_PAUSE)
+#define BIT_SET_P2PPS1_MACID_PAUSE(x, v) \
+ (BIT_CLEAR_P2PPS1_MACID_PAUSE(x) | BIT_P2PPS1_MACID_PAUSE(v))
+
+/* 2 REG_P2PPS2_HW_AUTO_PAUSE_CTRL (Offset 0x1574) */
+
+#define BIT_P2PPS2_NOA_STOP_TX_HANG BIT(31)
+#define BIT_P2PPS2_MACID_PAUSE_EN BIT(11)
+#define BIT_P2PPS2__MGQ_PAUSE BIT(10)
+#define BIT_P2PPS2__HIQ_PAUSE BIT(9)
+#define BIT_P2PPS2__BCNQ_PAUSE BIT(8)
+
+#define BIT_SHIFT_P2PPS2_MACID_PAUSE 0
+#define BIT_MASK_P2PPS2_MACID_PAUSE 0xff
+#define BIT_P2PPS2_MACID_PAUSE(x) \
+ (((x) & BIT_MASK_P2PPS2_MACID_PAUSE) << BIT_SHIFT_P2PPS2_MACID_PAUSE)
+#define BITS_P2PPS2_MACID_PAUSE \
+ (BIT_MASK_P2PPS2_MACID_PAUSE << BIT_SHIFT_P2PPS2_MACID_PAUSE)
+#define BIT_CLEAR_P2PPS2_MACID_PAUSE(x) ((x) & (~BITS_P2PPS2_MACID_PAUSE))
+#define BIT_GET_P2PPS2_MACID_PAUSE(x) \
+ (((x) >> BIT_SHIFT_P2PPS2_MACID_PAUSE) & BIT_MASK_P2PPS2_MACID_PAUSE)
+#define BIT_SET_P2PPS2_MACID_PAUSE(x, v) \
+ (BIT_CLEAR_P2PPS2_MACID_PAUSE(x) | BIT_P2PPS2_MACID_PAUSE(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_RX_TBTT_SHIFT (Offset 0x1578) */
+
+#define BIT_SHIFT_RX_TBTT_SHIFT_SEL 24
+#define BIT_MASK_RX_TBTT_SHIFT_SEL 0x7
+#define BIT_RX_TBTT_SHIFT_SEL(x) \
+ (((x) & BIT_MASK_RX_TBTT_SHIFT_SEL) << BIT_SHIFT_RX_TBTT_SHIFT_SEL)
+#define BITS_RX_TBTT_SHIFT_SEL \
+ (BIT_MASK_RX_TBTT_SHIFT_SEL << BIT_SHIFT_RX_TBTT_SHIFT_SEL)
+#define BIT_CLEAR_RX_TBTT_SHIFT_SEL(x) ((x) & (~BITS_RX_TBTT_SHIFT_SEL))
+#define BIT_GET_RX_TBTT_SHIFT_SEL(x) \
+ (((x) >> BIT_SHIFT_RX_TBTT_SHIFT_SEL) & BIT_MASK_RX_TBTT_SHIFT_SEL)
+#define BIT_SET_RX_TBTT_SHIFT_SEL(x, v) \
+ (BIT_CLEAR_RX_TBTT_SHIFT_SEL(x) | BIT_RX_TBTT_SHIFT_SEL(v))
+
+#define BIT_RX_TBTT_SHIFT_RW_FLAG BIT(15)
+
+#define BIT_SHIFT_RX_TBTT_SHIFT_OFFSET 0
+#define BIT_MASK_RX_TBTT_SHIFT_OFFSET 0xfff
+#define BIT_RX_TBTT_SHIFT_OFFSET(x) \
+ (((x) & BIT_MASK_RX_TBTT_SHIFT_OFFSET) \
+ << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET)
+#define BITS_RX_TBTT_SHIFT_OFFSET \
+ (BIT_MASK_RX_TBTT_SHIFT_OFFSET << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET)
+#define BIT_CLEAR_RX_TBTT_SHIFT_OFFSET(x) ((x) & (~BITS_RX_TBTT_SHIFT_OFFSET))
+#define BIT_GET_RX_TBTT_SHIFT_OFFSET(x) \
+ (((x) >> BIT_SHIFT_RX_TBTT_SHIFT_OFFSET) & \
+ BIT_MASK_RX_TBTT_SHIFT_OFFSET)
+#define BIT_SET_RX_TBTT_SHIFT_OFFSET(x, v) \
+ (BIT_CLEAR_RX_TBTT_SHIFT_OFFSET(x) | BIT_RX_TBTT_SHIFT_OFFSET(v))
+
+/* 2 REG_FREERUN_CNT_LOW (Offset 0x1580) */
+
+#define BIT_SHIFT_FREERUN_CNT_LOW 0
+#define BIT_MASK_FREERUN_CNT_LOW 0xffffffffL
+#define BIT_FREERUN_CNT_LOW(x) \
+ (((x) & BIT_MASK_FREERUN_CNT_LOW) << BIT_SHIFT_FREERUN_CNT_LOW)
+#define BITS_FREERUN_CNT_LOW \
+ (BIT_MASK_FREERUN_CNT_LOW << BIT_SHIFT_FREERUN_CNT_LOW)
+#define BIT_CLEAR_FREERUN_CNT_LOW(x) ((x) & (~BITS_FREERUN_CNT_LOW))
+#define BIT_GET_FREERUN_CNT_LOW(x) \
+ (((x) >> BIT_SHIFT_FREERUN_CNT_LOW) & BIT_MASK_FREERUN_CNT_LOW)
+#define BIT_SET_FREERUN_CNT_LOW(x, v) \
+ (BIT_CLEAR_FREERUN_CNT_LOW(x) | BIT_FREERUN_CNT_LOW(v))
+
+/* 2 REG_FREERUN_CNT_HIGH (Offset 0x1584) */
+
+#define BIT_SHIFT_FREERUN_CNT_HIGH 0
+#define BIT_MASK_FREERUN_CNT_HIGH 0xffffffffL
+#define BIT_FREERUN_CNT_HIGH(x) \
+ (((x) & BIT_MASK_FREERUN_CNT_HIGH) << BIT_SHIFT_FREERUN_CNT_HIGH)
+#define BITS_FREERUN_CNT_HIGH \
+ (BIT_MASK_FREERUN_CNT_HIGH << BIT_SHIFT_FREERUN_CNT_HIGH)
+#define BIT_CLEAR_FREERUN_CNT_HIGH(x) ((x) & (~BITS_FREERUN_CNT_HIGH))
+#define BIT_GET_FREERUN_CNT_HIGH(x) \
+ (((x) >> BIT_SHIFT_FREERUN_CNT_HIGH) & BIT_MASK_FREERUN_CNT_HIGH)
+#define BIT_SET_FREERUN_CNT_HIGH(x, v) \
+ (BIT_CLEAR_FREERUN_CNT_HIGH(x) | BIT_FREERUN_CNT_HIGH(v))
+
+/* 2 REG_PS_TIMER_0 (Offset 0x158C) */
+
+#define BIT_SHIFT_PS_TIMER_0 0
+#define BIT_MASK_PS_TIMER_0 0xffffffffL
+#define BIT_PS_TIMER_0(x) (((x) & BIT_MASK_PS_TIMER_0) << BIT_SHIFT_PS_TIMER_0)
+#define BITS_PS_TIMER_0 (BIT_MASK_PS_TIMER_0 << BIT_SHIFT_PS_TIMER_0)
+#define BIT_CLEAR_PS_TIMER_0(x) ((x) & (~BITS_PS_TIMER_0))
+#define BIT_GET_PS_TIMER_0(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_0) & BIT_MASK_PS_TIMER_0)
+#define BIT_SET_PS_TIMER_0(x, v) (BIT_CLEAR_PS_TIMER_0(x) | BIT_PS_TIMER_0(v))
+
+/* 2 REG_PS_TIMER_1 (Offset 0x1590) */
+
+#define BIT_SHIFT_PS_TIMER_1 0
+#define BIT_MASK_PS_TIMER_1 0xffffffffL
+#define BIT_PS_TIMER_1(x) (((x) & BIT_MASK_PS_TIMER_1) << BIT_SHIFT_PS_TIMER_1)
+#define BITS_PS_TIMER_1 (BIT_MASK_PS_TIMER_1 << BIT_SHIFT_PS_TIMER_1)
+#define BIT_CLEAR_PS_TIMER_1(x) ((x) & (~BITS_PS_TIMER_1))
+#define BIT_GET_PS_TIMER_1(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_1) & BIT_MASK_PS_TIMER_1)
+#define BIT_SET_PS_TIMER_1(x, v) (BIT_CLEAR_PS_TIMER_1(x) | BIT_PS_TIMER_1(v))
+
+/* 2 REG_PS_TIMER_2 (Offset 0x1594) */
+
+#define BIT_SHIFT_PS_TIMER_2 0
+#define BIT_MASK_PS_TIMER_2 0xffffffffL
+#define BIT_PS_TIMER_2(x) (((x) & BIT_MASK_PS_TIMER_2) << BIT_SHIFT_PS_TIMER_2)
+#define BITS_PS_TIMER_2 (BIT_MASK_PS_TIMER_2 << BIT_SHIFT_PS_TIMER_2)
+#define BIT_CLEAR_PS_TIMER_2(x) ((x) & (~BITS_PS_TIMER_2))
+#define BIT_GET_PS_TIMER_2(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_2) & BIT_MASK_PS_TIMER_2)
+#define BIT_SET_PS_TIMER_2(x, v) (BIT_CLEAR_PS_TIMER_2(x) | BIT_PS_TIMER_2(v))
+
+/* 2 REG_PS_TIMER_3 (Offset 0x1598) */
+
+#define BIT_SHIFT_PS_TIMER_3 0
+#define BIT_MASK_PS_TIMER_3 0xffffffffL
+#define BIT_PS_TIMER_3(x) (((x) & BIT_MASK_PS_TIMER_3) << BIT_SHIFT_PS_TIMER_3)
+#define BITS_PS_TIMER_3 (BIT_MASK_PS_TIMER_3 << BIT_SHIFT_PS_TIMER_3)
+#define BIT_CLEAR_PS_TIMER_3(x) ((x) & (~BITS_PS_TIMER_3))
+#define BIT_GET_PS_TIMER_3(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_3) & BIT_MASK_PS_TIMER_3)
+#define BIT_SET_PS_TIMER_3(x, v) (BIT_CLEAR_PS_TIMER_3(x) | BIT_PS_TIMER_3(v))
+
+/* 2 REG_PS_TIMER_4 (Offset 0x159C) */
+
+#define BIT_SHIFT_PS_TIMER_4 0
+#define BIT_MASK_PS_TIMER_4 0xffffffffL
+#define BIT_PS_TIMER_4(x) (((x) & BIT_MASK_PS_TIMER_4) << BIT_SHIFT_PS_TIMER_4)
+#define BITS_PS_TIMER_4 (BIT_MASK_PS_TIMER_4 << BIT_SHIFT_PS_TIMER_4)
+#define BIT_CLEAR_PS_TIMER_4(x) ((x) & (~BITS_PS_TIMER_4))
+#define BIT_GET_PS_TIMER_4(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_4) & BIT_MASK_PS_TIMER_4)
+#define BIT_SET_PS_TIMER_4(x, v) (BIT_CLEAR_PS_TIMER_4(x) | BIT_PS_TIMER_4(v))
+
+/* 2 REG_PS_TIMER_5 (Offset 0x15A0) */
+
+#define BIT_SHIFT_PS_TIMER_5 0
+#define BIT_MASK_PS_TIMER_5 0xffffffffL
+#define BIT_PS_TIMER_5(x) (((x) & BIT_MASK_PS_TIMER_5) << BIT_SHIFT_PS_TIMER_5)
+#define BITS_PS_TIMER_5 (BIT_MASK_PS_TIMER_5 << BIT_SHIFT_PS_TIMER_5)
+#define BIT_CLEAR_PS_TIMER_5(x) ((x) & (~BITS_PS_TIMER_5))
+#define BIT_GET_PS_TIMER_5(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_5) & BIT_MASK_PS_TIMER_5)
+#define BIT_SET_PS_TIMER_5(x, v) (BIT_CLEAR_PS_TIMER_5(x) | BIT_PS_TIMER_5(v))
+
+/* 2 REG_PS_TIMER_01_CTRL (Offset 0x15A4) */
+
+#define BIT_SHIFT_PS_TIMER_1_EARLY_TIME 24
+#define BIT_MASK_PS_TIMER_1_EARLY_TIME 0xff
+#define BIT_PS_TIMER_1_EARLY_TIME(x) \
+ (((x) & BIT_MASK_PS_TIMER_1_EARLY_TIME) \
+ << BIT_SHIFT_PS_TIMER_1_EARLY_TIME)
+#define BITS_PS_TIMER_1_EARLY_TIME \
+ (BIT_MASK_PS_TIMER_1_EARLY_TIME << BIT_SHIFT_PS_TIMER_1_EARLY_TIME)
+#define BIT_CLEAR_PS_TIMER_1_EARLY_TIME(x) ((x) & (~BITS_PS_TIMER_1_EARLY_TIME))
+#define BIT_GET_PS_TIMER_1_EARLY_TIME(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_1_EARLY_TIME) & \
+ BIT_MASK_PS_TIMER_1_EARLY_TIME)
+#define BIT_SET_PS_TIMER_1_EARLY_TIME(x, v) \
+ (BIT_CLEAR_PS_TIMER_1_EARLY_TIME(x) | BIT_PS_TIMER_1_EARLY_TIME(v))
+
+#define BIT_PS_TIMER_1_EN BIT(23)
+
+#define BIT_SHIFT_PS_TIMER_1_TSF_SEL 16
+#define BIT_MASK_PS_TIMER_1_TSF_SEL 0x7
+#define BIT_PS_TIMER_1_TSF_SEL(x) \
+ (((x) & BIT_MASK_PS_TIMER_1_TSF_SEL) << BIT_SHIFT_PS_TIMER_1_TSF_SEL)
+#define BITS_PS_TIMER_1_TSF_SEL \
+ (BIT_MASK_PS_TIMER_1_TSF_SEL << BIT_SHIFT_PS_TIMER_1_TSF_SEL)
+#define BIT_CLEAR_PS_TIMER_1_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_1_TSF_SEL))
+#define BIT_GET_PS_TIMER_1_TSF_SEL(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_1_TSF_SEL) & BIT_MASK_PS_TIMER_1_TSF_SEL)
+#define BIT_SET_PS_TIMER_1_TSF_SEL(x, v) \
+ (BIT_CLEAR_PS_TIMER_1_TSF_SEL(x) | BIT_PS_TIMER_1_TSF_SEL(v))
+
+#define BIT_SHIFT_PS_TIMER_0_EARLY_TIME 8
+#define BIT_MASK_PS_TIMER_0_EARLY_TIME 0xff
+#define BIT_PS_TIMER_0_EARLY_TIME(x) \
+ (((x) & BIT_MASK_PS_TIMER_0_EARLY_TIME) \
+ << BIT_SHIFT_PS_TIMER_0_EARLY_TIME)
+#define BITS_PS_TIMER_0_EARLY_TIME \
+ (BIT_MASK_PS_TIMER_0_EARLY_TIME << BIT_SHIFT_PS_TIMER_0_EARLY_TIME)
+#define BIT_CLEAR_PS_TIMER_0_EARLY_TIME(x) ((x) & (~BITS_PS_TIMER_0_EARLY_TIME))
+#define BIT_GET_PS_TIMER_0_EARLY_TIME(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_0_EARLY_TIME) & \
+ BIT_MASK_PS_TIMER_0_EARLY_TIME)
+#define BIT_SET_PS_TIMER_0_EARLY_TIME(x, v) \
+ (BIT_CLEAR_PS_TIMER_0_EARLY_TIME(x) | BIT_PS_TIMER_0_EARLY_TIME(v))
+
+#define BIT_PS_TIMER_0_EN BIT(7)
+
+#define BIT_SHIFT_PS_TIMER_0_TSF_SEL 0
+#define BIT_MASK_PS_TIMER_0_TSF_SEL 0x7
+#define BIT_PS_TIMER_0_TSF_SEL(x) \
+ (((x) & BIT_MASK_PS_TIMER_0_TSF_SEL) << BIT_SHIFT_PS_TIMER_0_TSF_SEL)
+#define BITS_PS_TIMER_0_TSF_SEL \
+ (BIT_MASK_PS_TIMER_0_TSF_SEL << BIT_SHIFT_PS_TIMER_0_TSF_SEL)
+#define BIT_CLEAR_PS_TIMER_0_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_0_TSF_SEL))
+#define BIT_GET_PS_TIMER_0_TSF_SEL(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_0_TSF_SEL) & BIT_MASK_PS_TIMER_0_TSF_SEL)
+#define BIT_SET_PS_TIMER_0_TSF_SEL(x, v) \
+ (BIT_CLEAR_PS_TIMER_0_TSF_SEL(x) | BIT_PS_TIMER_0_TSF_SEL(v))
+
+/* 2 REG_PS_TIMER_23_CTRL (Offset 0x15A8) */
+
+#define BIT_SHIFT_PS_TIMER_3_EARLY_TIME 24
+#define BIT_MASK_PS_TIMER_3_EARLY_TIME 0xff
+#define BIT_PS_TIMER_3_EARLY_TIME(x) \
+ (((x) & BIT_MASK_PS_TIMER_3_EARLY_TIME) \
+ << BIT_SHIFT_PS_TIMER_3_EARLY_TIME)
+#define BITS_PS_TIMER_3_EARLY_TIME \
+ (BIT_MASK_PS_TIMER_3_EARLY_TIME << BIT_SHIFT_PS_TIMER_3_EARLY_TIME)
+#define BIT_CLEAR_PS_TIMER_3_EARLY_TIME(x) ((x) & (~BITS_PS_TIMER_3_EARLY_TIME))
+#define BIT_GET_PS_TIMER_3_EARLY_TIME(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_3_EARLY_TIME) & \
+ BIT_MASK_PS_TIMER_3_EARLY_TIME)
+#define BIT_SET_PS_TIMER_3_EARLY_TIME(x, v) \
+ (BIT_CLEAR_PS_TIMER_3_EARLY_TIME(x) | BIT_PS_TIMER_3_EARLY_TIME(v))
+
+#define BIT_PS_TIMER_3_EN BIT(23)
+
+#define BIT_SHIFT_PS_TIMER_3_TSF_SEL 16
+#define BIT_MASK_PS_TIMER_3_TSF_SEL 0x7
+#define BIT_PS_TIMER_3_TSF_SEL(x) \
+ (((x) & BIT_MASK_PS_TIMER_3_TSF_SEL) << BIT_SHIFT_PS_TIMER_3_TSF_SEL)
+#define BITS_PS_TIMER_3_TSF_SEL \
+ (BIT_MASK_PS_TIMER_3_TSF_SEL << BIT_SHIFT_PS_TIMER_3_TSF_SEL)
+#define BIT_CLEAR_PS_TIMER_3_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_3_TSF_SEL))
+#define BIT_GET_PS_TIMER_3_TSF_SEL(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_3_TSF_SEL) & BIT_MASK_PS_TIMER_3_TSF_SEL)
+#define BIT_SET_PS_TIMER_3_TSF_SEL(x, v) \
+ (BIT_CLEAR_PS_TIMER_3_TSF_SEL(x) | BIT_PS_TIMER_3_TSF_SEL(v))
+
+#define BIT_SHIFT_PS_TIMER_2_EARLY_TIME 8
+#define BIT_MASK_PS_TIMER_2_EARLY_TIME 0xff
+#define BIT_PS_TIMER_2_EARLY_TIME(x) \
+ (((x) & BIT_MASK_PS_TIMER_2_EARLY_TIME) \
+ << BIT_SHIFT_PS_TIMER_2_EARLY_TIME)
+#define BITS_PS_TIMER_2_EARLY_TIME \
+ (BIT_MASK_PS_TIMER_2_EARLY_TIME << BIT_SHIFT_PS_TIMER_2_EARLY_TIME)
+#define BIT_CLEAR_PS_TIMER_2_EARLY_TIME(x) ((x) & (~BITS_PS_TIMER_2_EARLY_TIME))
+#define BIT_GET_PS_TIMER_2_EARLY_TIME(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_2_EARLY_TIME) & \
+ BIT_MASK_PS_TIMER_2_EARLY_TIME)
+#define BIT_SET_PS_TIMER_2_EARLY_TIME(x, v) \
+ (BIT_CLEAR_PS_TIMER_2_EARLY_TIME(x) | BIT_PS_TIMER_2_EARLY_TIME(v))
+
+#define BIT_PS_TIMER_2_EN BIT(7)
+
+#define BIT_SHIFT_PS_TIMER_2_TSF_SEL 0
+#define BIT_MASK_PS_TIMER_2_TSF_SEL 0x7
+#define BIT_PS_TIMER_2_TSF_SEL(x) \
+ (((x) & BIT_MASK_PS_TIMER_2_TSF_SEL) << BIT_SHIFT_PS_TIMER_2_TSF_SEL)
+#define BITS_PS_TIMER_2_TSF_SEL \
+ (BIT_MASK_PS_TIMER_2_TSF_SEL << BIT_SHIFT_PS_TIMER_2_TSF_SEL)
+#define BIT_CLEAR_PS_TIMER_2_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_2_TSF_SEL))
+#define BIT_GET_PS_TIMER_2_TSF_SEL(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_2_TSF_SEL) & BIT_MASK_PS_TIMER_2_TSF_SEL)
+#define BIT_SET_PS_TIMER_2_TSF_SEL(x, v) \
+ (BIT_CLEAR_PS_TIMER_2_TSF_SEL(x) | BIT_PS_TIMER_2_TSF_SEL(v))
+
+/* 2 REG_PS_TIMER_45_CTRL (Offset 0x15AC) */
+
+#define BIT_SHIFT_PS_TIMER_5_EARLY_TIME 24
+#define BIT_MASK_PS_TIMER_5_EARLY_TIME 0xff
+#define BIT_PS_TIMER_5_EARLY_TIME(x) \
+ (((x) & BIT_MASK_PS_TIMER_5_EARLY_TIME) \
+ << BIT_SHIFT_PS_TIMER_5_EARLY_TIME)
+#define BITS_PS_TIMER_5_EARLY_TIME \
+ (BIT_MASK_PS_TIMER_5_EARLY_TIME << BIT_SHIFT_PS_TIMER_5_EARLY_TIME)
+#define BIT_CLEAR_PS_TIMER_5_EARLY_TIME(x) ((x) & (~BITS_PS_TIMER_5_EARLY_TIME))
+#define BIT_GET_PS_TIMER_5_EARLY_TIME(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_5_EARLY_TIME) & \
+ BIT_MASK_PS_TIMER_5_EARLY_TIME)
+#define BIT_SET_PS_TIMER_5_EARLY_TIME(x, v) \
+ (BIT_CLEAR_PS_TIMER_5_EARLY_TIME(x) | BIT_PS_TIMER_5_EARLY_TIME(v))
+
+#define BIT_PS_TIMER_5_EN BIT(23)
+
+#define BIT_SHIFT_PS_TIMER_5_TSF_SEL 16
+#define BIT_MASK_PS_TIMER_5_TSF_SEL 0x7
+#define BIT_PS_TIMER_5_TSF_SEL(x) \
+ (((x) & BIT_MASK_PS_TIMER_5_TSF_SEL) << BIT_SHIFT_PS_TIMER_5_TSF_SEL)
+#define BITS_PS_TIMER_5_TSF_SEL \
+ (BIT_MASK_PS_TIMER_5_TSF_SEL << BIT_SHIFT_PS_TIMER_5_TSF_SEL)
+#define BIT_CLEAR_PS_TIMER_5_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_5_TSF_SEL))
+#define BIT_GET_PS_TIMER_5_TSF_SEL(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_5_TSF_SEL) & BIT_MASK_PS_TIMER_5_TSF_SEL)
+#define BIT_SET_PS_TIMER_5_TSF_SEL(x, v) \
+ (BIT_CLEAR_PS_TIMER_5_TSF_SEL(x) | BIT_PS_TIMER_5_TSF_SEL(v))
+
+#define BIT_SHIFT_PS_TIMER_4_EARLY_TIME 8
+#define BIT_MASK_PS_TIMER_4_EARLY_TIME 0xff
+#define BIT_PS_TIMER_4_EARLY_TIME(x) \
+ (((x) & BIT_MASK_PS_TIMER_4_EARLY_TIME) \
+ << BIT_SHIFT_PS_TIMER_4_EARLY_TIME)
+#define BITS_PS_TIMER_4_EARLY_TIME \
+ (BIT_MASK_PS_TIMER_4_EARLY_TIME << BIT_SHIFT_PS_TIMER_4_EARLY_TIME)
+#define BIT_CLEAR_PS_TIMER_4_EARLY_TIME(x) ((x) & (~BITS_PS_TIMER_4_EARLY_TIME))
+#define BIT_GET_PS_TIMER_4_EARLY_TIME(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_4_EARLY_TIME) & \
+ BIT_MASK_PS_TIMER_4_EARLY_TIME)
+#define BIT_SET_PS_TIMER_4_EARLY_TIME(x, v) \
+ (BIT_CLEAR_PS_TIMER_4_EARLY_TIME(x) | BIT_PS_TIMER_4_EARLY_TIME(v))
+
+#define BIT_PS_TIMER_4_EN BIT(7)
+
+#define BIT_SHIFT_PS_TIMER_4_TSF_SEL 0
+#define BIT_MASK_PS_TIMER_4_TSF_SEL 0x7
+#define BIT_PS_TIMER_4_TSF_SEL(x) \
+ (((x) & BIT_MASK_PS_TIMER_4_TSF_SEL) << BIT_SHIFT_PS_TIMER_4_TSF_SEL)
+#define BITS_PS_TIMER_4_TSF_SEL \
+ (BIT_MASK_PS_TIMER_4_TSF_SEL << BIT_SHIFT_PS_TIMER_4_TSF_SEL)
+#define BIT_CLEAR_PS_TIMER_4_TSF_SEL(x) ((x) & (~BITS_PS_TIMER_4_TSF_SEL))
+#define BIT_GET_PS_TIMER_4_TSF_SEL(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_4_TSF_SEL) & BIT_MASK_PS_TIMER_4_TSF_SEL)
+#define BIT_SET_PS_TIMER_4_TSF_SEL(x, v) \
+ (BIT_CLEAR_PS_TIMER_4_TSF_SEL(x) | BIT_PS_TIMER_4_TSF_SEL(v))
+
+/* 2 REG_CPUMGQ_FREERUN_TIMER_CTRL (Offset 0x15B0) */
+
+#define BIT_FREECNT_RST_V1 BIT(23)
+#define BIT_EN_FREECNT_V1 BIT(16)
+
+#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1 8
+#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1 0xff
+#define BIT_CPUMGQ_TX_TIMER_EARLY_V1(x) \
+ (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1) \
+ << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1)
+#define BITS_CPUMGQ_TX_TIMER_EARLY_V1 \
+ (BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1 \
+ << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1)
+#define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_V1(x) \
+ ((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY_V1))
+#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_V1(x) \
+ (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1) & \
+ BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1)
+#define BIT_SET_CPUMGQ_TX_TIMER_EARLY_V1(x, v) \
+ (BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_V1(x) | \
+ BIT_CPUMGQ_TX_TIMER_EARLY_V1(v))
+
+#define BIT_CPUMGQ_TIMER_EN_V1 BIT(7)
+#define BIT_CPUMGQ_DROP_BY_HOLDTIME BIT(5)
+#define BIT_CPUMGQ_TX_EN_V1 BIT(4)
+
+#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1 0
+#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1 0x7
+#define BIT_CPUMGQ_TIMER_TSF_SEL_V1(x) \
+ (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1) \
+ << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1)
+#define BITS_CPUMGQ_TIMER_TSF_SEL_V1 \
+ (BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1 << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1)
+#define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_V1(x) \
+ ((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL_V1))
+#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_V1(x) \
+ (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1) & \
+ BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1)
+#define BIT_SET_CPUMGQ_TIMER_TSF_SEL_V1(x, v) \
+ (BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_V1(x) | BIT_CPUMGQ_TIMER_TSF_SEL_V1(v))
+
+/* 2 REG_CPUMGQ_PROHIBIT (Offset 0x15B4) */
+
+#define BIT_SHIFT_CPUMGQ_HOLD_TIME 8
+#define BIT_MASK_CPUMGQ_HOLD_TIME 0xfff
+#define BIT_CPUMGQ_HOLD_TIME(x) \
+ (((x) & BIT_MASK_CPUMGQ_HOLD_TIME) << BIT_SHIFT_CPUMGQ_HOLD_TIME)
+#define BITS_CPUMGQ_HOLD_TIME \
+ (BIT_MASK_CPUMGQ_HOLD_TIME << BIT_SHIFT_CPUMGQ_HOLD_TIME)
+#define BIT_CLEAR_CPUMGQ_HOLD_TIME(x) ((x) & (~BITS_CPUMGQ_HOLD_TIME))
+#define BIT_GET_CPUMGQ_HOLD_TIME(x) \
+ (((x) >> BIT_SHIFT_CPUMGQ_HOLD_TIME) & BIT_MASK_CPUMGQ_HOLD_TIME)
+#define BIT_SET_CPUMGQ_HOLD_TIME(x, v) \
+ (BIT_CLEAR_CPUMGQ_HOLD_TIME(x) | BIT_CPUMGQ_HOLD_TIME(v))
+
+#define BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP 0
+#define BIT_MASK_CPUMGQ_PROHIBIT_SETUP 0xf
+#define BIT_CPUMGQ_PROHIBIT_SETUP(x) \
+ (((x) & BIT_MASK_CPUMGQ_PROHIBIT_SETUP) \
+ << BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP)
+#define BITS_CPUMGQ_PROHIBIT_SETUP \
+ (BIT_MASK_CPUMGQ_PROHIBIT_SETUP << BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP)
+#define BIT_CLEAR_CPUMGQ_PROHIBIT_SETUP(x) ((x) & (~BITS_CPUMGQ_PROHIBIT_SETUP))
+#define BIT_GET_CPUMGQ_PROHIBIT_SETUP(x) \
+ (((x) >> BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP) & \
+ BIT_MASK_CPUMGQ_PROHIBIT_SETUP)
+#define BIT_SET_CPUMGQ_PROHIBIT_SETUP(x, v) \
+ (BIT_CLEAR_CPUMGQ_PROHIBIT_SETUP(x) | BIT_CPUMGQ_PROHIBIT_SETUP(v))
+
+/* 2 REG_TIMER_COMPARE (Offset 0x15C0) */
+
+#define BIT_COMP_TRIGGER BIT(7)
+
+#define BIT_SHIFT_Y_COMP 4
+#define BIT_MASK_Y_COMP 0x7
+#define BIT_Y_COMP(x) (((x) & BIT_MASK_Y_COMP) << BIT_SHIFT_Y_COMP)
+#define BITS_Y_COMP (BIT_MASK_Y_COMP << BIT_SHIFT_Y_COMP)
+#define BIT_CLEAR_Y_COMP(x) ((x) & (~BITS_Y_COMP))
+#define BIT_GET_Y_COMP(x) (((x) >> BIT_SHIFT_Y_COMP) & BIT_MASK_Y_COMP)
+#define BIT_SET_Y_COMP(x, v) (BIT_CLEAR_Y_COMP(x) | BIT_Y_COMP(v))
+
+#define BIT_X_COMP_Y_OVERFLOW BIT(3)
+
+#define BIT_SHIFT_X_COMP 0
+#define BIT_MASK_X_COMP 0x7
+#define BIT_X_COMP(x) (((x) & BIT_MASK_X_COMP) << BIT_SHIFT_X_COMP)
+#define BITS_X_COMP (BIT_MASK_X_COMP << BIT_SHIFT_X_COMP)
+#define BIT_CLEAR_X_COMP(x) ((x) & (~BITS_X_COMP))
+#define BIT_GET_X_COMP(x) (((x) >> BIT_SHIFT_X_COMP) & BIT_MASK_X_COMP)
+#define BIT_SET_X_COMP(x, v) (BIT_CLEAR_X_COMP(x) | BIT_X_COMP(v))
+
+/* 2 REG_TIMER_COMPARE_VALUE_LOW (Offset 0x15C4) */
+
+#define BIT_SHIFT_COMP_VALUE_LOW 0
+#define BIT_MASK_COMP_VALUE_LOW 0xffffffffL
+#define BIT_COMP_VALUE_LOW(x) \
+ (((x) & BIT_MASK_COMP_VALUE_LOW) << BIT_SHIFT_COMP_VALUE_LOW)
+#define BITS_COMP_VALUE_LOW \
+ (BIT_MASK_COMP_VALUE_LOW << BIT_SHIFT_COMP_VALUE_LOW)
+#define BIT_CLEAR_COMP_VALUE_LOW(x) ((x) & (~BITS_COMP_VALUE_LOW))
+#define BIT_GET_COMP_VALUE_LOW(x) \
+ (((x) >> BIT_SHIFT_COMP_VALUE_LOW) & BIT_MASK_COMP_VALUE_LOW)
+#define BIT_SET_COMP_VALUE_LOW(x, v) \
+ (BIT_CLEAR_COMP_VALUE_LOW(x) | BIT_COMP_VALUE_LOW(v))
+
+/* 2 REG_TIMER_COMPARE_VALUE_HIGH (Offset 0x15C8) */
+
+#define BIT_SHIFT_COMP_VALUE_HIGH 0
+#define BIT_MASK_COMP_VALUE_HIGH 0xffffffffL
+#define BIT_COMP_VALUE_HIGH(x) \
+ (((x) & BIT_MASK_COMP_VALUE_HIGH) << BIT_SHIFT_COMP_VALUE_HIGH)
+#define BITS_COMP_VALUE_HIGH \
+ (BIT_MASK_COMP_VALUE_HIGH << BIT_SHIFT_COMP_VALUE_HIGH)
+#define BIT_CLEAR_COMP_VALUE_HIGH(x) ((x) & (~BITS_COMP_VALUE_HIGH))
+#define BIT_GET_COMP_VALUE_HIGH(x) \
+ (((x) >> BIT_SHIFT_COMP_VALUE_HIGH) & BIT_MASK_COMP_VALUE_HIGH)
+#define BIT_SET_COMP_VALUE_HIGH(x, v) \
+ (BIT_CLEAR_COMP_VALUE_HIGH(x) | BIT_COMP_VALUE_HIGH(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+/* 2 REG_BCN_PSR_RPT2 (Offset 0x1600) */
-#define BIT_SHIFT_CHNL_BUSY_TIME 0
-#define BIT_MASK_CHNL_BUSY_TIME 0xffffffffL
-#define BIT_CHNL_BUSY_TIME(x) (((x) & BIT_MASK_CHNL_BUSY_TIME) << BIT_SHIFT_CHNL_BUSY_TIME)
-#define BIT_GET_CHNL_BUSY_TIME(x) (((x) >> BIT_SHIFT_CHNL_BUSY_TIME) & BIT_MASK_CHNL_BUSY_TIME)
+#define BIT_SHIFT_DTIM_CNT2 24
+#define BIT_MASK_DTIM_CNT2 0xff
+#define BIT_DTIM_CNT2(x) (((x) & BIT_MASK_DTIM_CNT2) << BIT_SHIFT_DTIM_CNT2)
+#define BITS_DTIM_CNT2 (BIT_MASK_DTIM_CNT2 << BIT_SHIFT_DTIM_CNT2)
+#define BIT_CLEAR_DTIM_CNT2(x) ((x) & (~BITS_DTIM_CNT2))
+#define BIT_GET_DTIM_CNT2(x) (((x) >> BIT_SHIFT_DTIM_CNT2) & BIT_MASK_DTIM_CNT2)
+#define BIT_SET_DTIM_CNT2(x, v) (BIT_CLEAR_DTIM_CNT2(x) | BIT_DTIM_CNT2(v))
+
+#define BIT_SHIFT_DTIM_PERIOD2 16
+#define BIT_MASK_DTIM_PERIOD2 0xff
+#define BIT_DTIM_PERIOD2(x) \
+ (((x) & BIT_MASK_DTIM_PERIOD2) << BIT_SHIFT_DTIM_PERIOD2)
+#define BITS_DTIM_PERIOD2 (BIT_MASK_DTIM_PERIOD2 << BIT_SHIFT_DTIM_PERIOD2)
+#define BIT_CLEAR_DTIM_PERIOD2(x) ((x) & (~BITS_DTIM_PERIOD2))
+#define BIT_GET_DTIM_PERIOD2(x) \
+ (((x) >> BIT_SHIFT_DTIM_PERIOD2) & BIT_MASK_DTIM_PERIOD2)
+#define BIT_SET_DTIM_PERIOD2(x, v) \
+ (BIT_CLEAR_DTIM_PERIOD2(x) | BIT_DTIM_PERIOD2(v))
+
+#define BIT_DTIM2 BIT(15)
+#define BIT_TIM2 BIT(14)
+
+#define BIT_SHIFT_PS_AID_2 0
+#define BIT_MASK_PS_AID_2 0x7ff
+#define BIT_PS_AID_2(x) (((x) & BIT_MASK_PS_AID_2) << BIT_SHIFT_PS_AID_2)
+#define BITS_PS_AID_2 (BIT_MASK_PS_AID_2 << BIT_SHIFT_PS_AID_2)
+#define BIT_CLEAR_PS_AID_2(x) ((x) & (~BITS_PS_AID_2))
+#define BIT_GET_PS_AID_2(x) (((x) >> BIT_SHIFT_PS_AID_2) & BIT_MASK_PS_AID_2)
+#define BIT_SET_PS_AID_2(x, v) (BIT_CLEAR_PS_AID_2(x) | BIT_PS_AID_2(v))
+/* 2 REG_BCN_PSR_RPT3 (Offset 0x1604) */
-#endif
+#define BIT_SHIFT_DTIM_CNT3 24
+#define BIT_MASK_DTIM_CNT3 0xff
+#define BIT_DTIM_CNT3(x) (((x) & BIT_MASK_DTIM_CNT3) << BIT_SHIFT_DTIM_CNT3)
+#define BITS_DTIM_CNT3 (BIT_MASK_DTIM_CNT3 << BIT_SHIFT_DTIM_CNT3)
+#define BIT_CLEAR_DTIM_CNT3(x) ((x) & (~BITS_DTIM_CNT3))
+#define BIT_GET_DTIM_CNT3(x) (((x) >> BIT_SHIFT_DTIM_CNT3) & BIT_MASK_DTIM_CNT3)
+#define BIT_SET_DTIM_CNT3(x, v) (BIT_CLEAR_DTIM_CNT3(x) | BIT_DTIM_CNT3(v))
+
+#define BIT_SHIFT_DTIM_PERIOD3 16
+#define BIT_MASK_DTIM_PERIOD3 0xff
+#define BIT_DTIM_PERIOD3(x) \
+ (((x) & BIT_MASK_DTIM_PERIOD3) << BIT_SHIFT_DTIM_PERIOD3)
+#define BITS_DTIM_PERIOD3 (BIT_MASK_DTIM_PERIOD3 << BIT_SHIFT_DTIM_PERIOD3)
+#define BIT_CLEAR_DTIM_PERIOD3(x) ((x) & (~BITS_DTIM_PERIOD3))
+#define BIT_GET_DTIM_PERIOD3(x) \
+ (((x) >> BIT_SHIFT_DTIM_PERIOD3) & BIT_MASK_DTIM_PERIOD3)
+#define BIT_SET_DTIM_PERIOD3(x, v) \
+ (BIT_CLEAR_DTIM_PERIOD3(x) | BIT_DTIM_PERIOD3(v))
+
+#define BIT_DTIM3 BIT(15)
+#define BIT_TIM3 BIT(14)
+
+#define BIT_SHIFT_PS_AID_3 0
+#define BIT_MASK_PS_AID_3 0x7ff
+#define BIT_PS_AID_3(x) (((x) & BIT_MASK_PS_AID_3) << BIT_SHIFT_PS_AID_3)
+#define BITS_PS_AID_3 (BIT_MASK_PS_AID_3 << BIT_SHIFT_PS_AID_3)
+#define BIT_CLEAR_PS_AID_3(x) ((x) & (~BITS_PS_AID_3))
+#define BIT_GET_PS_AID_3(x) (((x) >> BIT_SHIFT_PS_AID_3) & BIT_MASK_PS_AID_3)
+#define BIT_SET_PS_AID_3(x, v) (BIT_CLEAR_PS_AID_3(x) | BIT_PS_AID_3(v))
+/* 2 REG_BCN_PSR_RPT4 (Offset 0x1608) */
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#define BIT_SHIFT_DTIM_CNT4 24
+#define BIT_MASK_DTIM_CNT4 0xff
+#define BIT_DTIM_CNT4(x) (((x) & BIT_MASK_DTIM_CNT4) << BIT_SHIFT_DTIM_CNT4)
+#define BITS_DTIM_CNT4 (BIT_MASK_DTIM_CNT4 << BIT_SHIFT_DTIM_CNT4)
+#define BIT_CLEAR_DTIM_CNT4(x) ((x) & (~BITS_DTIM_CNT4))
+#define BIT_GET_DTIM_CNT4(x) (((x) >> BIT_SHIFT_DTIM_CNT4) & BIT_MASK_DTIM_CNT4)
+#define BIT_SET_DTIM_CNT4(x, v) (BIT_CLEAR_DTIM_CNT4(x) | BIT_DTIM_CNT4(v))
+
+#define BIT_SHIFT_DTIM_PERIOD4 16
+#define BIT_MASK_DTIM_PERIOD4 0xff
+#define BIT_DTIM_PERIOD4(x) \
+ (((x) & BIT_MASK_DTIM_PERIOD4) << BIT_SHIFT_DTIM_PERIOD4)
+#define BITS_DTIM_PERIOD4 (BIT_MASK_DTIM_PERIOD4 << BIT_SHIFT_DTIM_PERIOD4)
+#define BIT_CLEAR_DTIM_PERIOD4(x) ((x) & (~BITS_DTIM_PERIOD4))
+#define BIT_GET_DTIM_PERIOD4(x) \
+ (((x) >> BIT_SHIFT_DTIM_PERIOD4) & BIT_MASK_DTIM_PERIOD4)
+#define BIT_SET_DTIM_PERIOD4(x, v) \
+ (BIT_CLEAR_DTIM_PERIOD4(x) | BIT_DTIM_PERIOD4(v))
+
+#define BIT_DTIM4 BIT(15)
+#define BIT_TIM4 BIT(14)
+
+#define BIT_SHIFT_PS_AID_4 0
+#define BIT_MASK_PS_AID_4 0x7ff
+#define BIT_PS_AID_4(x) (((x) & BIT_MASK_PS_AID_4) << BIT_SHIFT_PS_AID_4)
+#define BITS_PS_AID_4 (BIT_MASK_PS_AID_4 << BIT_SHIFT_PS_AID_4)
+#define BIT_CLEAR_PS_AID_4(x) ((x) & (~BITS_PS_AID_4))
+#define BIT_GET_PS_AID_4(x) (((x) >> BIT_SHIFT_PS_AID_4) & BIT_MASK_PS_AID_4)
+#define BIT_SET_PS_AID_4(x, v) (BIT_CLEAR_PS_AID_4(x) | BIT_PS_AID_4(v))
+/* 2 REG_A1_ADDR_MASK (Offset 0x160C) */
-/* 2 REG_CMDQ_BCNQ_INFO (Offset 0x1414) */
+#define BIT_SHIFT_A1_ADDR_MASK 0
+#define BIT_MASK_A1_ADDR_MASK 0xffffffffL
+#define BIT_A1_ADDR_MASK(x) \
+ (((x) & BIT_MASK_A1_ADDR_MASK) << BIT_SHIFT_A1_ADDR_MASK)
+#define BITS_A1_ADDR_MASK (BIT_MASK_A1_ADDR_MASK << BIT_SHIFT_A1_ADDR_MASK)
+#define BIT_CLEAR_A1_ADDR_MASK(x) ((x) & (~BITS_A1_ADDR_MASK))
+#define BIT_GET_A1_ADDR_MASK(x) \
+ (((x) >> BIT_SHIFT_A1_ADDR_MASK) & BIT_MASK_A1_ADDR_MASK)
+#define BIT_SET_A1_ADDR_MASK(x, v) \
+ (BIT_CLEAR_A1_ADDR_MASK(x) | BIT_A1_ADDR_MASK(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_RXPSF_CTRL (Offset 0x1610) */
+
+#define BIT_RXGCK_FIFOTHR_EN BIT(28)
+
+#define BIT_SHIFT_RXGCK_VHT_FIFOTHR 26
+#define BIT_MASK_RXGCK_VHT_FIFOTHR 0x3
+#define BIT_RXGCK_VHT_FIFOTHR(x) \
+ (((x) & BIT_MASK_RXGCK_VHT_FIFOTHR) << BIT_SHIFT_RXGCK_VHT_FIFOTHR)
+#define BITS_RXGCK_VHT_FIFOTHR \
+ (BIT_MASK_RXGCK_VHT_FIFOTHR << BIT_SHIFT_RXGCK_VHT_FIFOTHR)
+#define BIT_CLEAR_RXGCK_VHT_FIFOTHR(x) ((x) & (~BITS_RXGCK_VHT_FIFOTHR))
+#define BIT_GET_RXGCK_VHT_FIFOTHR(x) \
+ (((x) >> BIT_SHIFT_RXGCK_VHT_FIFOTHR) & BIT_MASK_RXGCK_VHT_FIFOTHR)
+#define BIT_SET_RXGCK_VHT_FIFOTHR(x, v) \
+ (BIT_CLEAR_RXGCK_VHT_FIFOTHR(x) | BIT_RXGCK_VHT_FIFOTHR(v))
+
+#define BIT_SHIFT_RXGCK_HT_FIFOTHR 24
+#define BIT_MASK_RXGCK_HT_FIFOTHR 0x3
+#define BIT_RXGCK_HT_FIFOTHR(x) \
+ (((x) & BIT_MASK_RXGCK_HT_FIFOTHR) << BIT_SHIFT_RXGCK_HT_FIFOTHR)
+#define BITS_RXGCK_HT_FIFOTHR \
+ (BIT_MASK_RXGCK_HT_FIFOTHR << BIT_SHIFT_RXGCK_HT_FIFOTHR)
+#define BIT_CLEAR_RXGCK_HT_FIFOTHR(x) ((x) & (~BITS_RXGCK_HT_FIFOTHR))
+#define BIT_GET_RXGCK_HT_FIFOTHR(x) \
+ (((x) >> BIT_SHIFT_RXGCK_HT_FIFOTHR) & BIT_MASK_RXGCK_HT_FIFOTHR)
+#define BIT_SET_RXGCK_HT_FIFOTHR(x, v) \
+ (BIT_CLEAR_RXGCK_HT_FIFOTHR(x) | BIT_RXGCK_HT_FIFOTHR(v))
+
+#define BIT_SHIFT_RXGCK_OFDM_FIFOTHR 22
+#define BIT_MASK_RXGCK_OFDM_FIFOTHR 0x3
+#define BIT_RXGCK_OFDM_FIFOTHR(x) \
+ (((x) & BIT_MASK_RXGCK_OFDM_FIFOTHR) << BIT_SHIFT_RXGCK_OFDM_FIFOTHR)
+#define BITS_RXGCK_OFDM_FIFOTHR \
+ (BIT_MASK_RXGCK_OFDM_FIFOTHR << BIT_SHIFT_RXGCK_OFDM_FIFOTHR)
+#define BIT_CLEAR_RXGCK_OFDM_FIFOTHR(x) ((x) & (~BITS_RXGCK_OFDM_FIFOTHR))
+#define BIT_GET_RXGCK_OFDM_FIFOTHR(x) \
+ (((x) >> BIT_SHIFT_RXGCK_OFDM_FIFOTHR) & BIT_MASK_RXGCK_OFDM_FIFOTHR)
+#define BIT_SET_RXGCK_OFDM_FIFOTHR(x, v) \
+ (BIT_CLEAR_RXGCK_OFDM_FIFOTHR(x) | BIT_RXGCK_OFDM_FIFOTHR(v))
+
+#define BIT_SHIFT_RXGCK_CCK_FIFOTHR 20
+#define BIT_MASK_RXGCK_CCK_FIFOTHR 0x3
+#define BIT_RXGCK_CCK_FIFOTHR(x) \
+ (((x) & BIT_MASK_RXGCK_CCK_FIFOTHR) << BIT_SHIFT_RXGCK_CCK_FIFOTHR)
+#define BITS_RXGCK_CCK_FIFOTHR \
+ (BIT_MASK_RXGCK_CCK_FIFOTHR << BIT_SHIFT_RXGCK_CCK_FIFOTHR)
+#define BIT_CLEAR_RXGCK_CCK_FIFOTHR(x) ((x) & (~BITS_RXGCK_CCK_FIFOTHR))
+#define BIT_GET_RXGCK_CCK_FIFOTHR(x) \
+ (((x) >> BIT_SHIFT_RXGCK_CCK_FIFOTHR) & BIT_MASK_RXGCK_CCK_FIFOTHR)
+#define BIT_SET_RXGCK_CCK_FIFOTHR(x, v) \
+ (BIT_CLEAR_RXGCK_CCK_FIFOTHR(x) | BIT_RXGCK_CCK_FIFOTHR(v))
+
+#define BIT_SHIFT_RXGCK_ENTRY_DELAY 17
+#define BIT_MASK_RXGCK_ENTRY_DELAY 0x7
+#define BIT_RXGCK_ENTRY_DELAY(x) \
+ (((x) & BIT_MASK_RXGCK_ENTRY_DELAY) << BIT_SHIFT_RXGCK_ENTRY_DELAY)
+#define BITS_RXGCK_ENTRY_DELAY \
+ (BIT_MASK_RXGCK_ENTRY_DELAY << BIT_SHIFT_RXGCK_ENTRY_DELAY)
+#define BIT_CLEAR_RXGCK_ENTRY_DELAY(x) ((x) & (~BITS_RXGCK_ENTRY_DELAY))
+#define BIT_GET_RXGCK_ENTRY_DELAY(x) \
+ (((x) >> BIT_SHIFT_RXGCK_ENTRY_DELAY) & BIT_MASK_RXGCK_ENTRY_DELAY)
+#define BIT_SET_RXGCK_ENTRY_DELAY(x, v) \
+ (BIT_CLEAR_RXGCK_ENTRY_DELAY(x) | BIT_RXGCK_ENTRY_DELAY(v))
+
+#define BIT_RXGCK_OFDMCCA_EN BIT(16)
+
+#define BIT_SHIFT_RXPSF_PKTLENTHR 13
+#define BIT_MASK_RXPSF_PKTLENTHR 0x7
+#define BIT_RXPSF_PKTLENTHR(x) \
+ (((x) & BIT_MASK_RXPSF_PKTLENTHR) << BIT_SHIFT_RXPSF_PKTLENTHR)
+#define BITS_RXPSF_PKTLENTHR \
+ (BIT_MASK_RXPSF_PKTLENTHR << BIT_SHIFT_RXPSF_PKTLENTHR)
+#define BIT_CLEAR_RXPSF_PKTLENTHR(x) ((x) & (~BITS_RXPSF_PKTLENTHR))
+#define BIT_GET_RXPSF_PKTLENTHR(x) \
+ (((x) >> BIT_SHIFT_RXPSF_PKTLENTHR) & BIT_MASK_RXPSF_PKTLENTHR)
+#define BIT_SET_RXPSF_PKTLENTHR(x, v) \
+ (BIT_CLEAR_RXPSF_PKTLENTHR(x) | BIT_RXPSF_PKTLENTHR(v))
+
+#define BIT_RXPSF_CTRLEN BIT(12)
+#define BIT_RXPSF_VHTCHKEN BIT(11)
+#define BIT_RXPSF_HTCHKEN BIT(10)
+#define BIT_RXPSF_OFDMCHKEN BIT(9)
+#define BIT_RXPSF_CCKCHKEN BIT(8)
+#define BIT_RXPSF_OFDMRST BIT(7)
+#define BIT_RXPSF_CCKRST BIT(6)
+#define BIT_RXPSF_MHCHKEN BIT(5)
+#define BIT_RXPSF_CONT_ERRCHKEN BIT(4)
+#define BIT_RXPSF_ALL_ERRCHKEN BIT(3)
+
+#define BIT_SHIFT_RXPSF_ERRTHR 0
+#define BIT_MASK_RXPSF_ERRTHR 0x7
+#define BIT_RXPSF_ERRTHR(x) \
+ (((x) & BIT_MASK_RXPSF_ERRTHR) << BIT_SHIFT_RXPSF_ERRTHR)
+#define BITS_RXPSF_ERRTHR (BIT_MASK_RXPSF_ERRTHR << BIT_SHIFT_RXPSF_ERRTHR)
+#define BIT_CLEAR_RXPSF_ERRTHR(x) ((x) & (~BITS_RXPSF_ERRTHR))
+#define BIT_GET_RXPSF_ERRTHR(x) \
+ (((x) >> BIT_SHIFT_RXPSF_ERRTHR) & BIT_MASK_RXPSF_ERRTHR)
+#define BIT_SET_RXPSF_ERRTHR(x, v) \
+ (BIT_CLEAR_RXPSF_ERRTHR(x) | BIT_RXPSF_ERRTHR(v))
+
+/* 2 REG_RXPSF_TYPE_CTRL (Offset 0x1614) */
+
+#define BIT_RXPSF_DATA15EN BIT(31)
+#define BIT_RXPSF_DATA14EN BIT(30)
+#define BIT_RXPSF_DATA13EN BIT(29)
+#define BIT_RXPSF_DATA12EN BIT(28)
+#define BIT_RXPSF_DATA11EN BIT(27)
+#define BIT_RXPSF_DATA10EN BIT(26)
+#define BIT_RXPSF_DATA9EN BIT(25)
+#define BIT_RXPSF_DATA8EN BIT(24)
+#define BIT_RXPSF_DATA7EN BIT(23)
+#define BIT_RXPSF_DATA6EN BIT(22)
+#define BIT_RXPSF_DATA5EN BIT(21)
+#define BIT_RXPSF_DATA4EN BIT(20)
+#define BIT_RXPSF_DATA3EN BIT(19)
+#define BIT_RXPSF_DATA2EN BIT(18)
+#define BIT_RXPSF_DATA1EN BIT(17)
+#define BIT_RXPSF_DATA0EN BIT(16)
+#define BIT_RXPSF_MGT15EN BIT(15)
+#define BIT_RXPSF_MGT14EN BIT(14)
+#define BIT_RXPSF_MGT13EN BIT(13)
+#define BIT_RXPSF_MGT12EN BIT(12)
+#define BIT_RXPSF_MGT11EN BIT(11)
+#define BIT_RXPSF_MGT10EN BIT(10)
+#define BIT_RXPSF_MGT9EN BIT(9)
+#define BIT_RXPSF_MGT8EN BIT(8)
+#define BIT_RXPSF_MGT7EN BIT(7)
+#define BIT_RXPSF_MGT6EN BIT(6)
+#define BIT_RXPSF_MGT5EN BIT(5)
+#define BIT_RXPSF_MGT4EN BIT(4)
+#define BIT_RXPSF_MGT3EN BIT(3)
+#define BIT_RXPSF_MGT2EN BIT(2)
+#define BIT_RXPSF_MGT1EN BIT(1)
+#define BIT_RXPSF_MGT0EN BIT(0)
+
+/* 2 REG_CAM_ACCESS_CTRL (Offset 0x1618) */
+
+#define BIT_INDIRECT_ERR BIT(6)
+#define BIT_DIRECT_ERR BIT(5)
+#define BIT_DIR_ACCESS_EN_RX_BA BIT(4)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_CAM_ACCESS_CTRL (Offset 0x1618) */
+
+#define BIT_DIR_ACCESS_EN_ADDRCAM BIT(3)
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CAM_ACCESS_CTRL (Offset 0x1618) */
+
+#define BIT_DIR_ACCESS_EN_MBSSIDCAM BIT(3)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_CAM_ACCESS_CTRL (Offset 0x1618) */
+
+#define BIT_DIR_ACCESS_EN_KEY BIT(2)
+#define BIT_DIR_ACCESS_EN_WOWLAN BIT(1)
+#define BIT_DIR_ACCESS_EN_FW_FILTER BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_CUT_AMSDU_CTRL (Offset 0x161C) */
+
+#define BIT__CUT_AMSDU_CHKLEN_EN BIT(31)
+#define BIT_EN_CUT_AMSDU BIT(30)
+
+#define BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH 16
+#define BIT_MASK_CUT_AMSDU_CHKLEN_L_TH 0xff
+#define BIT_CUT_AMSDU_CHKLEN_L_TH(x) \
+ (((x) & BIT_MASK_CUT_AMSDU_CHKLEN_L_TH) \
+ << BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH)
+#define BITS_CUT_AMSDU_CHKLEN_L_TH \
+ (BIT_MASK_CUT_AMSDU_CHKLEN_L_TH << BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH)
+#define BIT_CLEAR_CUT_AMSDU_CHKLEN_L_TH(x) ((x) & (~BITS_CUT_AMSDU_CHKLEN_L_TH))
+#define BIT_GET_CUT_AMSDU_CHKLEN_L_TH(x) \
+ (((x) >> BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH) & \
+ BIT_MASK_CUT_AMSDU_CHKLEN_L_TH)
+#define BIT_SET_CUT_AMSDU_CHKLEN_L_TH(x, v) \
+ (BIT_CLEAR_CUT_AMSDU_CHKLEN_L_TH(x) | BIT_CUT_AMSDU_CHKLEN_L_TH(v))
+#define BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH 0
+#define BIT_MASK_CUT_AMSDU_CHKLEN_H_TH 0xffff
+#define BIT_CUT_AMSDU_CHKLEN_H_TH(x) \
+ (((x) & BIT_MASK_CUT_AMSDU_CHKLEN_H_TH) \
+ << BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH)
+#define BITS_CUT_AMSDU_CHKLEN_H_TH \
+ (BIT_MASK_CUT_AMSDU_CHKLEN_H_TH << BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH)
+#define BIT_CLEAR_CUT_AMSDU_CHKLEN_H_TH(x) ((x) & (~BITS_CUT_AMSDU_CHKLEN_H_TH))
+#define BIT_GET_CUT_AMSDU_CHKLEN_H_TH(x) \
+ (((x) >> BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH) & \
+ BIT_MASK_CUT_AMSDU_CHKLEN_H_TH)
+#define BIT_SET_CUT_AMSDU_CHKLEN_H_TH(x, v) \
+ (BIT_CLEAR_CUT_AMSDU_CHKLEN_H_TH(x) | BIT_CUT_AMSDU_CHKLEN_H_TH(v))
-#define BIT_SHIFT_BCNQ_PKT_INFO 0
-#define BIT_MASK_BCNQ_PKT_INFO 0xfff
-#define BIT_BCNQ_PKT_INFO(x) (((x) & BIT_MASK_BCNQ_PKT_INFO) << BIT_SHIFT_BCNQ_PKT_INFO)
-#define BIT_GET_BCNQ_PKT_INFO(x) (((x) >> BIT_SHIFT_BCNQ_PKT_INFO) & BIT_MASK_BCNQ_PKT_INFO)
+#endif
+#if (HALMAC_8822C_SUPPORT)
-#endif
+/* 2 REG_HT_SND_REF_RATE (Offset 0x161C) */
+#define BIT_SHIFT_WMAC_HT_CSI_RATE 0
+#define BIT_MASK_WMAC_HT_CSI_RATE 0x3f
+#define BIT_WMAC_HT_CSI_RATE(x) \
+ (((x) & BIT_MASK_WMAC_HT_CSI_RATE) << BIT_SHIFT_WMAC_HT_CSI_RATE)
+#define BITS_WMAC_HT_CSI_RATE \
+ (BIT_MASK_WMAC_HT_CSI_RATE << BIT_SHIFT_WMAC_HT_CSI_RATE)
+#define BIT_CLEAR_WMAC_HT_CSI_RATE(x) ((x) & (~BITS_WMAC_HT_CSI_RATE))
+#define BIT_GET_WMAC_HT_CSI_RATE(x) \
+ (((x) >> BIT_SHIFT_WMAC_HT_CSI_RATE) & BIT_MASK_WMAC_HT_CSI_RATE)
+#define BIT_SET_WMAC_HT_CSI_RATE(x, v) \
+ (BIT_CLEAR_WMAC_HT_CSI_RATE(x) | BIT_WMAC_HT_CSI_RATE(v))
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
-/* 2 REG_USEREG_SETTING (Offset 0x1420) */
+/* 2 REG_MACID2 (Offset 0x1620) */
-#define BIT_NDPA_USEREG BIT(21)
+#define BIT_SHIFT_MACID2 0
+#define BIT_MASK_MACID2 0xffffffffffffL
+#define BIT_MACID2(x) (((x) & BIT_MASK_MACID2) << BIT_SHIFT_MACID2)
+#define BITS_MACID2 (BIT_MASK_MACID2 << BIT_SHIFT_MACID2)
+#define BIT_CLEAR_MACID2(x) ((x) & (~BITS_MACID2))
+#define BIT_GET_MACID2(x) (((x) >> BIT_SHIFT_MACID2) & BIT_MASK_MACID2)
+#define BIT_SET_MACID2(x, v) (BIT_CLEAR_MACID2(x) | BIT_MACID2(v))
-#define BIT_SHIFT_RETRY_USEREG 19
-#define BIT_MASK_RETRY_USEREG 0x3
-#define BIT_RETRY_USEREG(x) (((x) & BIT_MASK_RETRY_USEREG) << BIT_SHIFT_RETRY_USEREG)
-#define BIT_GET_RETRY_USEREG(x) (((x) >> BIT_SHIFT_RETRY_USEREG) & BIT_MASK_RETRY_USEREG)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_TRYPKT_USEREG 17
-#define BIT_MASK_TRYPKT_USEREG 0x3
-#define BIT_TRYPKT_USEREG(x) (((x) & BIT_MASK_TRYPKT_USEREG) << BIT_SHIFT_TRYPKT_USEREG)
-#define BIT_GET_TRYPKT_USEREG(x) (((x) >> BIT_SHIFT_TRYPKT_USEREG) & BIT_MASK_TRYPKT_USEREG)
+/* 2 REG_MACID2 (Offset 0x1620) */
-#define BIT_CTLPKT_USEREG BIT(16)
+#define BIT_SHIFT_MACID2_V1 0
+#define BIT_MASK_MACID2_V1 0xffffffffL
+#define BIT_MACID2_V1(x) (((x) & BIT_MASK_MACID2_V1) << BIT_SHIFT_MACID2_V1)
+#define BITS_MACID2_V1 (BIT_MASK_MACID2_V1 << BIT_SHIFT_MACID2_V1)
+#define BIT_CLEAR_MACID2_V1(x) ((x) & (~BITS_MACID2_V1))
+#define BIT_GET_MACID2_V1(x) (((x) >> BIT_SHIFT_MACID2_V1) & BIT_MASK_MACID2_V1)
+#define BIT_SET_MACID2_V1(x, v) (BIT_CLEAR_MACID2_V1(x) | BIT_MACID2_V1(v))
-/* 2 REG_AESIV_SETTING (Offset 0x1424) */
+/* 2 REG_MACID2_H (Offset 0x1624) */
+#define BIT_SHIFT_MACID2_H_V1 0
+#define BIT_MASK_MACID2_H_V1 0xffff
+#define BIT_MACID2_H_V1(x) \
+ (((x) & BIT_MASK_MACID2_H_V1) << BIT_SHIFT_MACID2_H_V1)
+#define BITS_MACID2_H_V1 (BIT_MASK_MACID2_H_V1 << BIT_SHIFT_MACID2_H_V1)
+#define BIT_CLEAR_MACID2_H_V1(x) ((x) & (~BITS_MACID2_H_V1))
+#define BIT_GET_MACID2_H_V1(x) \
+ (((x) >> BIT_SHIFT_MACID2_H_V1) & BIT_MASK_MACID2_H_V1)
+#define BIT_SET_MACID2_H_V1(x, v) \
+ (BIT_CLEAR_MACID2_H_V1(x) | BIT_MACID2_H_V1(v))
-#define BIT_SHIFT_AESIV_OFFSET 0
-#define BIT_MASK_AESIV_OFFSET 0xfff
-#define BIT_AESIV_OFFSET(x) (((x) & BIT_MASK_AESIV_OFFSET) << BIT_SHIFT_AESIV_OFFSET)
-#define BIT_GET_AESIV_OFFSET(x) (((x) >> BIT_SHIFT_AESIV_OFFSET) & BIT_MASK_AESIV_OFFSET)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
-/* 2 REG_BF0_TIME_SETTING (Offset 0x1428) */
+/* 2 REG_BSSID2 (Offset 0x1628) */
-#define BIT_BF0_TIMER_SET BIT(31)
-#define BIT_BF0_TIMER_CLR BIT(30)
-#define BIT_BF0_UPDATE_EN BIT(29)
-#define BIT_BF0_TIMER_EN BIT(28)
+#define BIT_SHIFT_BSSID2 0
+#define BIT_MASK_BSSID2 0xffffffffffffL
+#define BIT_BSSID2(x) (((x) & BIT_MASK_BSSID2) << BIT_SHIFT_BSSID2)
+#define BITS_BSSID2 (BIT_MASK_BSSID2 << BIT_SHIFT_BSSID2)
+#define BIT_CLEAR_BSSID2(x) ((x) & (~BITS_BSSID2))
+#define BIT_GET_BSSID2(x) (((x) >> BIT_SHIFT_BSSID2) & BIT_MASK_BSSID2)
+#define BIT_SET_BSSID2(x, v) (BIT_CLEAR_BSSID2(x) | BIT_BSSID2(v))
-#define BIT_SHIFT_BF0_PRETIME_OVER 16
-#define BIT_MASK_BF0_PRETIME_OVER 0xfff
-#define BIT_BF0_PRETIME_OVER(x) (((x) & BIT_MASK_BF0_PRETIME_OVER) << BIT_SHIFT_BF0_PRETIME_OVER)
-#define BIT_GET_BF0_PRETIME_OVER(x) (((x) >> BIT_SHIFT_BF0_PRETIME_OVER) & BIT_MASK_BF0_PRETIME_OVER)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_BF0_LIFETIME 0
-#define BIT_MASK_BF0_LIFETIME 0xffff
-#define BIT_BF0_LIFETIME(x) (((x) & BIT_MASK_BF0_LIFETIME) << BIT_SHIFT_BF0_LIFETIME)
-#define BIT_GET_BF0_LIFETIME(x) (((x) >> BIT_SHIFT_BF0_LIFETIME) & BIT_MASK_BF0_LIFETIME)
+/* 2 REG_BSSID2 (Offset 0x1628) */
+#define BIT_SHIFT_BSSID2_V1 0
+#define BIT_MASK_BSSID2_V1 0xffffffffL
+#define BIT_BSSID2_V1(x) (((x) & BIT_MASK_BSSID2_V1) << BIT_SHIFT_BSSID2_V1)
+#define BITS_BSSID2_V1 (BIT_MASK_BSSID2_V1 << BIT_SHIFT_BSSID2_V1)
+#define BIT_CLEAR_BSSID2_V1(x) ((x) & (~BITS_BSSID2_V1))
+#define BIT_GET_BSSID2_V1(x) (((x) >> BIT_SHIFT_BSSID2_V1) & BIT_MASK_BSSID2_V1)
+#define BIT_SET_BSSID2_V1(x, v) (BIT_CLEAR_BSSID2_V1(x) | BIT_BSSID2_V1(v))
-/* 2 REG_BF1_TIME_SETTING (Offset 0x142C) */
+/* 2 REG_BSSID2_H (Offset 0x162C) */
-#define BIT_BF1_TIMER_SET BIT(31)
-#define BIT_BF1_TIMER_CLR BIT(30)
-#define BIT_BF1_UPDATE_EN BIT(29)
-#define BIT_BF1_TIMER_EN BIT(28)
+#define BIT_SHIFT_BSSID2_H_V1 0
+#define BIT_MASK_BSSID2_H_V1 0xffff
+#define BIT_BSSID2_H_V1(x) \
+ (((x) & BIT_MASK_BSSID2_H_V1) << BIT_SHIFT_BSSID2_H_V1)
+#define BITS_BSSID2_H_V1 (BIT_MASK_BSSID2_H_V1 << BIT_SHIFT_BSSID2_H_V1)
+#define BIT_CLEAR_BSSID2_H_V1(x) ((x) & (~BITS_BSSID2_H_V1))
+#define BIT_GET_BSSID2_H_V1(x) \
+ (((x) >> BIT_SHIFT_BSSID2_H_V1) & BIT_MASK_BSSID2_H_V1)
+#define BIT_SET_BSSID2_H_V1(x, v) \
+ (BIT_CLEAR_BSSID2_H_V1(x) | BIT_BSSID2_H_V1(v))
-#define BIT_SHIFT_BF1_PRETIME_OVER 16
-#define BIT_MASK_BF1_PRETIME_OVER 0xfff
-#define BIT_BF1_PRETIME_OVER(x) (((x) & BIT_MASK_BF1_PRETIME_OVER) << BIT_SHIFT_BF1_PRETIME_OVER)
-#define BIT_GET_BF1_PRETIME_OVER(x) (((x) >> BIT_SHIFT_BF1_PRETIME_OVER) & BIT_MASK_BF1_PRETIME_OVER)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_BF1_LIFETIME 0
-#define BIT_MASK_BF1_LIFETIME 0xffff
-#define BIT_BF1_LIFETIME(x) (((x) & BIT_MASK_BF1_LIFETIME) << BIT_SHIFT_BF1_LIFETIME)
-#define BIT_GET_BF1_LIFETIME(x) (((x) >> BIT_SHIFT_BF1_LIFETIME) & BIT_MASK_BF1_LIFETIME)
+/* 2 REG_MACID3 (Offset 0x1630) */
+#define BIT_SHIFT_MACID3 0
+#define BIT_MASK_MACID3 0xffffffffffffL
+#define BIT_MACID3(x) (((x) & BIT_MASK_MACID3) << BIT_SHIFT_MACID3)
+#define BITS_MACID3 (BIT_MASK_MACID3 << BIT_SHIFT_MACID3)
+#define BIT_CLEAR_MACID3(x) ((x) & (~BITS_MACID3))
+#define BIT_GET_MACID3(x) (((x) >> BIT_SHIFT_MACID3) & BIT_MASK_MACID3)
+#define BIT_SET_MACID3(x, v) (BIT_CLEAR_MACID3(x) | BIT_MACID3(v))
-/* 2 REG_BF_TIMEOUT_EN (Offset 0x1430) */
+#endif
-#define BIT_EN_VHT_LDPC BIT(9)
-#define BIT_EN_HT_LDPC BIT(8)
-#define BIT_BF1_TIMEOUT_EN BIT(1)
-#define BIT_BF0_TIMEOUT_EN BIT(0)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_MACID_RELEASE0 (Offset 0x1434) */
+/* 2 REG_MACID3 (Offset 0x1630) */
+#define BIT_SHIFT_MACID3_V1 0
+#define BIT_MASK_MACID3_V1 0xffffffffL
+#define BIT_MACID3_V1(x) (((x) & BIT_MASK_MACID3_V1) << BIT_SHIFT_MACID3_V1)
+#define BITS_MACID3_V1 (BIT_MASK_MACID3_V1 << BIT_SHIFT_MACID3_V1)
+#define BIT_CLEAR_MACID3_V1(x) ((x) & (~BITS_MACID3_V1))
+#define BIT_GET_MACID3_V1(x) (((x) >> BIT_SHIFT_MACID3_V1) & BIT_MASK_MACID3_V1)
+#define BIT_SET_MACID3_V1(x, v) (BIT_CLEAR_MACID3_V1(x) | BIT_MACID3_V1(v))
-#define BIT_SHIFT_MACID31_0_RELEASE 0
-#define BIT_MASK_MACID31_0_RELEASE 0xffffffffL
-#define BIT_MACID31_0_RELEASE(x) (((x) & BIT_MASK_MACID31_0_RELEASE) << BIT_SHIFT_MACID31_0_RELEASE)
-#define BIT_GET_MACID31_0_RELEASE(x) (((x) >> BIT_SHIFT_MACID31_0_RELEASE) & BIT_MASK_MACID31_0_RELEASE)
+/* 2 REG_MACID3_H (Offset 0x1634) */
+#define BIT_SHIFT_MACID3_H_V1 0
+#define BIT_MASK_MACID3_H_V1 0xffff
+#define BIT_MACID3_H_V1(x) \
+ (((x) & BIT_MASK_MACID3_H_V1) << BIT_SHIFT_MACID3_H_V1)
+#define BITS_MACID3_H_V1 (BIT_MASK_MACID3_H_V1 << BIT_SHIFT_MACID3_H_V1)
+#define BIT_CLEAR_MACID3_H_V1(x) ((x) & (~BITS_MACID3_H_V1))
+#define BIT_GET_MACID3_H_V1(x) \
+ (((x) >> BIT_SHIFT_MACID3_H_V1) & BIT_MASK_MACID3_H_V1)
+#define BIT_SET_MACID3_H_V1(x, v) \
+ (BIT_CLEAR_MACID3_H_V1(x) | BIT_MACID3_H_V1(v))
-/* 2 REG_MACID_RELEASE1 (Offset 0x1438) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_MACID63_32_RELEASE 0
-#define BIT_MASK_MACID63_32_RELEASE 0xffffffffL
-#define BIT_MACID63_32_RELEASE(x) (((x) & BIT_MASK_MACID63_32_RELEASE) << BIT_SHIFT_MACID63_32_RELEASE)
-#define BIT_GET_MACID63_32_RELEASE(x) (((x) >> BIT_SHIFT_MACID63_32_RELEASE) & BIT_MASK_MACID63_32_RELEASE)
+/* 2 REG_BSSID3 (Offset 0x1638) */
+#define BIT_SHIFT_BSSID3 0
+#define BIT_MASK_BSSID3 0xffffffffffffL
+#define BIT_BSSID3(x) (((x) & BIT_MASK_BSSID3) << BIT_SHIFT_BSSID3)
+#define BITS_BSSID3 (BIT_MASK_BSSID3 << BIT_SHIFT_BSSID3)
+#define BIT_CLEAR_BSSID3(x) ((x) & (~BITS_BSSID3))
+#define BIT_GET_BSSID3(x) (((x) >> BIT_SHIFT_BSSID3) & BIT_MASK_BSSID3)
+#define BIT_SET_BSSID3(x, v) (BIT_CLEAR_BSSID3(x) | BIT_BSSID3(v))
-/* 2 REG_MACID_RELEASE2 (Offset 0x143C) */
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_MACID95_64_RELEASE 0
-#define BIT_MASK_MACID95_64_RELEASE 0xffffffffL
-#define BIT_MACID95_64_RELEASE(x) (((x) & BIT_MASK_MACID95_64_RELEASE) << BIT_SHIFT_MACID95_64_RELEASE)
-#define BIT_GET_MACID95_64_RELEASE(x) (((x) >> BIT_SHIFT_MACID95_64_RELEASE) & BIT_MASK_MACID95_64_RELEASE)
+/* 2 REG_BSSID3 (Offset 0x1638) */
+#define BIT_SHIFT_BSSID3_V1 0
+#define BIT_MASK_BSSID3_V1 0xffffffffL
+#define BIT_BSSID3_V1(x) (((x) & BIT_MASK_BSSID3_V1) << BIT_SHIFT_BSSID3_V1)
+#define BITS_BSSID3_V1 (BIT_MASK_BSSID3_V1 << BIT_SHIFT_BSSID3_V1)
+#define BIT_CLEAR_BSSID3_V1(x) ((x) & (~BITS_BSSID3_V1))
+#define BIT_GET_BSSID3_V1(x) (((x) >> BIT_SHIFT_BSSID3_V1) & BIT_MASK_BSSID3_V1)
+#define BIT_SET_BSSID3_V1(x, v) (BIT_CLEAR_BSSID3_V1(x) | BIT_BSSID3_V1(v))
-/* 2 REG_MACID_RELEASE3 (Offset 0x1440) */
+/* 2 REG_BSSID3_H (Offset 0x163C) */
+#define BIT_SHIFT_BSSID3_H_V1 0
+#define BIT_MASK_BSSID3_H_V1 0xffff
+#define BIT_BSSID3_H_V1(x) \
+ (((x) & BIT_MASK_BSSID3_H_V1) << BIT_SHIFT_BSSID3_H_V1)
+#define BITS_BSSID3_H_V1 (BIT_MASK_BSSID3_H_V1 << BIT_SHIFT_BSSID3_H_V1)
+#define BIT_CLEAR_BSSID3_H_V1(x) ((x) & (~BITS_BSSID3_H_V1))
+#define BIT_GET_BSSID3_H_V1(x) \
+ (((x) >> BIT_SHIFT_BSSID3_H_V1) & BIT_MASK_BSSID3_H_V1)
+#define BIT_SET_BSSID3_H_V1(x, v) \
+ (BIT_CLEAR_BSSID3_H_V1(x) | BIT_BSSID3_H_V1(v))
-#define BIT_SHIFT_MACID127_96_RELEASE 0
-#define BIT_MASK_MACID127_96_RELEASE 0xffffffffL
-#define BIT_MACID127_96_RELEASE(x) (((x) & BIT_MASK_MACID127_96_RELEASE) << BIT_SHIFT_MACID127_96_RELEASE)
-#define BIT_GET_MACID127_96_RELEASE(x) (((x) >> BIT_SHIFT_MACID127_96_RELEASE) & BIT_MASK_MACID127_96_RELEASE)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
-/* 2 REG_MACID_RELEASE_SETTING (Offset 0x1444) */
+/* 2 REG_MACID4 (Offset 0x1640) */
-#define BIT_MACID_VALUE BIT(7)
+#define BIT_SHIFT_MACID4 0
+#define BIT_MASK_MACID4 0xffffffffffffL
+#define BIT_MACID4(x) (((x) & BIT_MASK_MACID4) << BIT_SHIFT_MACID4)
+#define BITS_MACID4 (BIT_MASK_MACID4 << BIT_SHIFT_MACID4)
+#define BIT_CLEAR_MACID4(x) ((x) & (~BITS_MACID4))
+#define BIT_GET_MACID4(x) (((x) >> BIT_SHIFT_MACID4) & BIT_MASK_MACID4)
+#define BIT_SET_MACID4(x, v) (BIT_CLEAR_MACID4(x) | BIT_MACID4(v))
-#define BIT_SHIFT_MACID_OFFSET 0
-#define BIT_MASK_MACID_OFFSET 0x7f
-#define BIT_MACID_OFFSET(x) (((x) & BIT_MASK_MACID_OFFSET) << BIT_SHIFT_MACID_OFFSET)
-#define BIT_GET_MACID_OFFSET(x) (((x) >> BIT_SHIFT_MACID_OFFSET) & BIT_MASK_MACID_OFFSET)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_FAST_EDCA_VOVI_SETTING (Offset 0x1448) */
+/* 2 REG_MACID4 (Offset 0x1640) */
+#define BIT_SHIFT_MACID4_V1 0
+#define BIT_MASK_MACID4_V1 0xffffffffL
+#define BIT_MACID4_V1(x) (((x) & BIT_MASK_MACID4_V1) << BIT_SHIFT_MACID4_V1)
+#define BITS_MACID4_V1 (BIT_MASK_MACID4_V1 << BIT_SHIFT_MACID4_V1)
+#define BIT_CLEAR_MACID4_V1(x) ((x) & (~BITS_MACID4_V1))
+#define BIT_GET_MACID4_V1(x) (((x) >> BIT_SHIFT_MACID4_V1) & BIT_MASK_MACID4_V1)
+#define BIT_SET_MACID4_V1(x, v) (BIT_CLEAR_MACID4_V1(x) | BIT_MACID4_V1(v))
-#define BIT_SHIFT_VI_FAST_EDCA_TO 24
-#define BIT_MASK_VI_FAST_EDCA_TO 0xff
-#define BIT_VI_FAST_EDCA_TO(x) (((x) & BIT_MASK_VI_FAST_EDCA_TO) << BIT_SHIFT_VI_FAST_EDCA_TO)
-#define BIT_GET_VI_FAST_EDCA_TO(x) (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO) & BIT_MASK_VI_FAST_EDCA_TO)
+/* 2 REG_MACID4_H (Offset 0x1644) */
-#define BIT_VI_THRESHOLD_SEL BIT(23)
+#define BIT_SHIFT_MACID4_H_V1 0
+#define BIT_MASK_MACID4_H_V1 0xffff
+#define BIT_MACID4_H_V1(x) \
+ (((x) & BIT_MASK_MACID4_H_V1) << BIT_SHIFT_MACID4_H_V1)
+#define BITS_MACID4_H_V1 (BIT_MASK_MACID4_H_V1 << BIT_SHIFT_MACID4_H_V1)
+#define BIT_CLEAR_MACID4_H_V1(x) ((x) & (~BITS_MACID4_H_V1))
+#define BIT_GET_MACID4_H_V1(x) \
+ (((x) >> BIT_SHIFT_MACID4_H_V1) & BIT_MASK_MACID4_H_V1)
+#define BIT_SET_MACID4_H_V1(x, v) \
+ (BIT_CLEAR_MACID4_H_V1(x) | BIT_MACID4_H_V1(v))
-#define BIT_SHIFT_VI_FAST_EDCA_PKT_TH 16
-#define BIT_MASK_VI_FAST_EDCA_PKT_TH 0x7f
-#define BIT_VI_FAST_EDCA_PKT_TH(x) (((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH) << BIT_SHIFT_VI_FAST_EDCA_PKT_TH)
-#define BIT_GET_VI_FAST_EDCA_PKT_TH(x) (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH) & BIT_MASK_VI_FAST_EDCA_PKT_TH)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_VO_FAST_EDCA_TO 8
-#define BIT_MASK_VO_FAST_EDCA_TO 0xff
-#define BIT_VO_FAST_EDCA_TO(x) (((x) & BIT_MASK_VO_FAST_EDCA_TO) << BIT_SHIFT_VO_FAST_EDCA_TO)
-#define BIT_GET_VO_FAST_EDCA_TO(x) (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO) & BIT_MASK_VO_FAST_EDCA_TO)
+/* 2 REG_BSSID4 (Offset 0x1648) */
-#define BIT_VO_THRESHOLD_SEL BIT(7)
+#define BIT_SHIFT_BSSID4 0
+#define BIT_MASK_BSSID4 0xffffffffffffL
+#define BIT_BSSID4(x) (((x) & BIT_MASK_BSSID4) << BIT_SHIFT_BSSID4)
+#define BITS_BSSID4 (BIT_MASK_BSSID4 << BIT_SHIFT_BSSID4)
+#define BIT_CLEAR_BSSID4(x) ((x) & (~BITS_BSSID4))
+#define BIT_GET_BSSID4(x) (((x) >> BIT_SHIFT_BSSID4) & BIT_MASK_BSSID4)
+#define BIT_SET_BSSID4(x, v) (BIT_CLEAR_BSSID4(x) | BIT_BSSID4(v))
-#define BIT_SHIFT_VO_FAST_EDCA_PKT_TH 0
-#define BIT_MASK_VO_FAST_EDCA_PKT_TH 0x7f
-#define BIT_VO_FAST_EDCA_PKT_TH(x) (((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH) << BIT_SHIFT_VO_FAST_EDCA_PKT_TH)
-#define BIT_GET_VO_FAST_EDCA_PKT_TH(x) (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH) & BIT_MASK_VO_FAST_EDCA_PKT_TH)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_FAST_EDCA_BEBK_SETTING (Offset 0x144C) */
+/* 2 REG_BSSID4 (Offset 0x1648) */
+#define BIT_SHIFT_BSSID4_V1 0
+#define BIT_MASK_BSSID4_V1 0xffffffffL
+#define BIT_BSSID4_V1(x) (((x) & BIT_MASK_BSSID4_V1) << BIT_SHIFT_BSSID4_V1)
+#define BITS_BSSID4_V1 (BIT_MASK_BSSID4_V1 << BIT_SHIFT_BSSID4_V1)
+#define BIT_CLEAR_BSSID4_V1(x) ((x) & (~BITS_BSSID4_V1))
+#define BIT_GET_BSSID4_V1(x) (((x) >> BIT_SHIFT_BSSID4_V1) & BIT_MASK_BSSID4_V1)
+#define BIT_SET_BSSID4_V1(x, v) (BIT_CLEAR_BSSID4_V1(x) | BIT_BSSID4_V1(v))
-#define BIT_SHIFT_BK_FAST_EDCA_TO 24
-#define BIT_MASK_BK_FAST_EDCA_TO 0xff
-#define BIT_BK_FAST_EDCA_TO(x) (((x) & BIT_MASK_BK_FAST_EDCA_TO) << BIT_SHIFT_BK_FAST_EDCA_TO)
-#define BIT_GET_BK_FAST_EDCA_TO(x) (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO) & BIT_MASK_BK_FAST_EDCA_TO)
+/* 2 REG_BSSID4_H (Offset 0x164C) */
-#define BIT_BK_THRESHOLD_SEL BIT(23)
+#define BIT_SHIFT_BSSID4_H_V1 0
+#define BIT_MASK_BSSID4_H_V1 0xffff
+#define BIT_BSSID4_H_V1(x) \
+ (((x) & BIT_MASK_BSSID4_H_V1) << BIT_SHIFT_BSSID4_H_V1)
+#define BITS_BSSID4_H_V1 (BIT_MASK_BSSID4_H_V1 << BIT_SHIFT_BSSID4_H_V1)
+#define BIT_CLEAR_BSSID4_H_V1(x) ((x) & (~BITS_BSSID4_H_V1))
+#define BIT_GET_BSSID4_H_V1(x) \
+ (((x) >> BIT_SHIFT_BSSID4_H_V1) & BIT_MASK_BSSID4_H_V1)
+#define BIT_SET_BSSID4_H_V1(x, v) \
+ (BIT_CLEAR_BSSID4_H_V1(x) | BIT_BSSID4_H_V1(v))
-#define BIT_SHIFT_BK_FAST_EDCA_PKT_TH 16
-#define BIT_MASK_BK_FAST_EDCA_PKT_TH 0x7f
-#define BIT_BK_FAST_EDCA_PKT_TH(x) (((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH) << BIT_SHIFT_BK_FAST_EDCA_PKT_TH)
-#define BIT_GET_BK_FAST_EDCA_PKT_TH(x) (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH) & BIT_MASK_BK_FAST_EDCA_PKT_TH)
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_BE_FAST_EDCA_TO 8
-#define BIT_MASK_BE_FAST_EDCA_TO 0xff
-#define BIT_BE_FAST_EDCA_TO(x) (((x) & BIT_MASK_BE_FAST_EDCA_TO) << BIT_SHIFT_BE_FAST_EDCA_TO)
-#define BIT_GET_BE_FAST_EDCA_TO(x) (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO) & BIT_MASK_BE_FAST_EDCA_TO)
+/* 2 REG_NOA_REPORT (Offset 0x1650) */
-#define BIT_BE_THRESHOLD_SEL BIT(7)
+#define BIT_SHIFT_NOA_RPT 0
+#define BIT_MASK_NOA_RPT 0xffffffffL
+#define BIT_NOA_RPT(x) (((x) & BIT_MASK_NOA_RPT) << BIT_SHIFT_NOA_RPT)
+#define BITS_NOA_RPT (BIT_MASK_NOA_RPT << BIT_SHIFT_NOA_RPT)
+#define BIT_CLEAR_NOA_RPT(x) ((x) & (~BITS_NOA_RPT))
+#define BIT_GET_NOA_RPT(x) (((x) >> BIT_SHIFT_NOA_RPT) & BIT_MASK_NOA_RPT)
+#define BIT_SET_NOA_RPT(x, v) (BIT_CLEAR_NOA_RPT(x) | BIT_NOA_RPT(v))
-#define BIT_SHIFT_BE_FAST_EDCA_PKT_TH 0
-#define BIT_MASK_BE_FAST_EDCA_PKT_TH 0x7f
-#define BIT_BE_FAST_EDCA_PKT_TH(x) (((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH) << BIT_SHIFT_BE_FAST_EDCA_PKT_TH)
-#define BIT_GET_BE_FAST_EDCA_PKT_TH(x) (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH) & BIT_MASK_BE_FAST_EDCA_PKT_TH)
+/* 2 REG_NOA_REPORT_1 (Offset 0x1654) */
+#define BIT_SHIFT_NOA_RPT_1 0
+#define BIT_MASK_NOA_RPT_1 0xffffffffL
+#define BIT_NOA_RPT_1(x) (((x) & BIT_MASK_NOA_RPT_1) << BIT_SHIFT_NOA_RPT_1)
+#define BITS_NOA_RPT_1 (BIT_MASK_NOA_RPT_1 << BIT_SHIFT_NOA_RPT_1)
+#define BIT_CLEAR_NOA_RPT_1(x) ((x) & (~BITS_NOA_RPT_1))
+#define BIT_GET_NOA_RPT_1(x) (((x) >> BIT_SHIFT_NOA_RPT_1) & BIT_MASK_NOA_RPT_1)
+#define BIT_SET_NOA_RPT_1(x, v) (BIT_CLEAR_NOA_RPT_1(x) | BIT_NOA_RPT_1(v))
-/* 2 REG_MACID_DROP0 (Offset 0x1450) */
+/* 2 REG_NOA_REPORT_2 (Offset 0x1658) */
+#define BIT_SHIFT_NOA_RPT_2 0
+#define BIT_MASK_NOA_RPT_2 0xffffffffL
+#define BIT_NOA_RPT_2(x) (((x) & BIT_MASK_NOA_RPT_2) << BIT_SHIFT_NOA_RPT_2)
+#define BITS_NOA_RPT_2 (BIT_MASK_NOA_RPT_2 << BIT_SHIFT_NOA_RPT_2)
+#define BIT_CLEAR_NOA_RPT_2(x) ((x) & (~BITS_NOA_RPT_2))
+#define BIT_GET_NOA_RPT_2(x) (((x) >> BIT_SHIFT_NOA_RPT_2) & BIT_MASK_NOA_RPT_2)
+#define BIT_SET_NOA_RPT_2(x, v) (BIT_CLEAR_NOA_RPT_2(x) | BIT_NOA_RPT_2(v))
-#define BIT_SHIFT_MACID31_0_DROP 0
-#define BIT_MASK_MACID31_0_DROP 0xffffffffL
-#define BIT_MACID31_0_DROP(x) (((x) & BIT_MASK_MACID31_0_DROP) << BIT_SHIFT_MACID31_0_DROP)
-#define BIT_GET_MACID31_0_DROP(x) (((x) >> BIT_SHIFT_MACID31_0_DROP) & BIT_MASK_MACID31_0_DROP)
+/* 2 REG_NOA_REPORT_3 (Offset 0x165C) */
+#define BIT_SHIFT_NOA_RPT_3 0
+#define BIT_MASK_NOA_RPT_3 0xff
+#define BIT_NOA_RPT_3(x) (((x) & BIT_MASK_NOA_RPT_3) << BIT_SHIFT_NOA_RPT_3)
+#define BITS_NOA_RPT_3 (BIT_MASK_NOA_RPT_3 << BIT_SHIFT_NOA_RPT_3)
+#define BIT_CLEAR_NOA_RPT_3(x) ((x) & (~BITS_NOA_RPT_3))
+#define BIT_GET_NOA_RPT_3(x) (((x) >> BIT_SHIFT_NOA_RPT_3) & BIT_MASK_NOA_RPT_3)
+#define BIT_SET_NOA_RPT_3(x, v) (BIT_CLEAR_NOA_RPT_3(x) | BIT_NOA_RPT_3(v))
-/* 2 REG_MACID_DROP1 (Offset 0x1454) */
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_MACID63_32_DROP 0
-#define BIT_MASK_MACID63_32_DROP 0xffffffffL
-#define BIT_MACID63_32_DROP(x) (((x) & BIT_MASK_MACID63_32_DROP) << BIT_SHIFT_MACID63_32_DROP)
-#define BIT_GET_MACID63_32_DROP(x) (((x) >> BIT_SHIFT_MACID63_32_DROP) & BIT_MASK_MACID63_32_DROP)
+/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */
+#define BIT_CLI3_WMAC_TCRPWRMGT_HWCTL_EN BIT(15)
+#define BIT_CLI3_WMAC_TCRPWRMGT_HWDATA_EN BIT(14)
+#define BIT_CLI3_WMAC_TCRPWRMGT_HWACT_EN BIT(13)
+#define BIT_CLI3_PWR_ST_V1 BIT(12)
+#define BIT_CLI2_WMAC_TCRPWRMGT_HWCTL_EN BIT(11)
+#define BIT_CLI2_WMAC_TCRPWRMGT_HWDATA_EN BIT(10)
+#define BIT_CLI2_WMAC_TCRPWRMGT_HWACT_EN BIT(9)
+#define BIT_CLI2_PWR_ST_V1 BIT(8)
-/* 2 REG_MACID_DROP2 (Offset 0x1458) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_MACID95_64_DROP 0
-#define BIT_MASK_MACID95_64_DROP 0xffffffffL
-#define BIT_MACID95_64_DROP(x) (((x) & BIT_MASK_MACID95_64_DROP) << BIT_SHIFT_MACID95_64_DROP)
-#define BIT_GET_MACID95_64_DROP(x) (((x) >> BIT_SHIFT_MACID95_64_DROP) & BIT_MASK_MACID95_64_DROP)
+/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */
+#define BIT_CLI3_PWRBIT_OW_EN BIT(7)
-/* 2 REG_MACID_DROP3 (Offset 0x145C) */
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_MACID127_96_DROP 0
-#define BIT_MASK_MACID127_96_DROP 0xffffffffL
-#define BIT_MACID127_96_DROP(x) (((x) & BIT_MASK_MACID127_96_DROP) << BIT_SHIFT_MACID127_96_DROP)
-#define BIT_GET_MACID127_96_DROP(x) (((x) >> BIT_SHIFT_MACID127_96_DROP) & BIT_MASK_MACID127_96_DROP)
+/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */
+#define BIT_CLI1_WMAC_TCRPWRMGT_HWCTL_EN BIT(7)
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */
+#define BIT_CLI3_PWR_ST BIT(6)
-/* 2 REG_R_MACID_RELEASE_SUCCESS_0 (Offset 0x1460) */
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0 0
-#define BIT_MASK_R_MACID_RELEASE_SUCCESS_0 0xffffffffL
-#define BIT_R_MACID_RELEASE_SUCCESS_0(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0)
-#define BIT_GET_R_MACID_RELEASE_SUCCESS_0(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0)
+/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */
+#define BIT_CLI1_WMAC_TCRPWRMGT_HWDATA_EN BIT(6)
-/* 2 REG_R_MACID_RELEASE_SUCCESS_1 (Offset 0x1464) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1 0
-#define BIT_MASK_R_MACID_RELEASE_SUCCESS_1 0xffffffffL
-#define BIT_R_MACID_RELEASE_SUCCESS_1(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1)
-#define BIT_GET_R_MACID_RELEASE_SUCCESS_1(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1)
+/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */
+#define BIT_CLI2_PWRBIT_OW_EN BIT(5)
-/* 2 REG_R_MACID_RELEASE_SUCCESS_2 (Offset 0x1468) */
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2 0
-#define BIT_MASK_R_MACID_RELEASE_SUCCESS_2 0xffffffffL
-#define BIT_R_MACID_RELEASE_SUCCESS_2(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2)
-#define BIT_GET_R_MACID_RELEASE_SUCCESS_2(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2)
+/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */
+#define BIT_CLI1_WMAC_TCRPWRMGT_HWACT_EN BIT(5)
-/* 2 REG_R_MACID_RELEASE_SUCCESS_3 (Offset 0x146C) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3 0
-#define BIT_MASK_R_MACID_RELEASE_SUCCESS_3 0xffffffffL
-#define BIT_R_MACID_RELEASE_SUCCESS_3(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3)
-#define BIT_GET_R_MACID_RELEASE_SUCCESS_3(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3)
+/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */
+#define BIT_CLI2_PWR_ST BIT(4)
-/* 2 REG_MGG_FIFO_CRTL (Offset 0x1470) */
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_R_MGG_FIFO_EN BIT(31)
+/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */
+
+#define BIT_CLI1_PWR_ST_V1 BIT(4)
-#define BIT_SHIFT_R_MGG_FIFO_PG_SIZE 28
-#define BIT_MASK_R_MGG_FIFO_PG_SIZE 0x7
-#define BIT_R_MGG_FIFO_PG_SIZE(x) (((x) & BIT_MASK_R_MGG_FIFO_PG_SIZE) << BIT_SHIFT_R_MGG_FIFO_PG_SIZE)
-#define BIT_GET_R_MGG_FIFO_PG_SIZE(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_PG_SIZE) & BIT_MASK_R_MGG_FIFO_PG_SIZE)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_R_MGG_FIFO_START_PG 16
-#define BIT_MASK_R_MGG_FIFO_START_PG 0xfff
-#define BIT_R_MGG_FIFO_START_PG(x) (((x) & BIT_MASK_R_MGG_FIFO_START_PG) << BIT_SHIFT_R_MGG_FIFO_START_PG)
-#define BIT_GET_R_MGG_FIFO_START_PG(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_START_PG) & BIT_MASK_R_MGG_FIFO_START_PG)
+/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */
+#define BIT_CLI1_PWRBIT_OW_EN BIT(3)
-#define BIT_SHIFT_R_MGG_FIFO_SIZE 14
-#define BIT_MASK_R_MGG_FIFO_SIZE 0x3
-#define BIT_R_MGG_FIFO_SIZE(x) (((x) & BIT_MASK_R_MGG_FIFO_SIZE) << BIT_SHIFT_R_MGG_FIFO_SIZE)
-#define BIT_GET_R_MGG_FIFO_SIZE(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_SIZE) & BIT_MASK_R_MGG_FIFO_SIZE)
+#endif
-#define BIT_R_MGG_FIFO_PAUSE BIT(13)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_R_MGG_FIFO_RPTR 8
-#define BIT_MASK_R_MGG_FIFO_RPTR 0x1f
-#define BIT_R_MGG_FIFO_RPTR(x) (((x) & BIT_MASK_R_MGG_FIFO_RPTR) << BIT_SHIFT_R_MGG_FIFO_RPTR)
-#define BIT_GET_R_MGG_FIFO_RPTR(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_RPTR) & BIT_MASK_R_MGG_FIFO_RPTR)
+/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */
-#define BIT_R_MGG_FIFO_OV BIT(7)
-#define BIT_R_MGG_FIFO_WPTR_ERROR BIT(6)
-#define BIT_R_EN_CPU_LIFETIME BIT(5)
+#define BIT_CLI0_WMAC_TCRPWRMGT_HWCTL_EN BIT(3)
-#define BIT_SHIFT_R_MGG_FIFO_WPTR 0
-#define BIT_MASK_R_MGG_FIFO_WPTR 0x1f
-#define BIT_R_MGG_FIFO_WPTR(x) (((x) & BIT_MASK_R_MGG_FIFO_WPTR) << BIT_SHIFT_R_MGG_FIFO_WPTR)
-#define BIT_GET_R_MGG_FIFO_WPTR(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_WPTR) & BIT_MASK_R_MGG_FIFO_WPTR)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
-/* 2 REG_MGG_FIFO_INT (Offset 0x1474) */
+/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */
+#define BIT_CLI1_PWR_ST BIT(2)
-#define BIT_SHIFT_R_MGG_FIFO_INT_FLAG 16
-#define BIT_MASK_R_MGG_FIFO_INT_FLAG 0xffff
-#define BIT_R_MGG_FIFO_INT_FLAG(x) (((x) & BIT_MASK_R_MGG_FIFO_INT_FLAG) << BIT_SHIFT_R_MGG_FIFO_INT_FLAG)
-#define BIT_GET_R_MGG_FIFO_INT_FLAG(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_FLAG) & BIT_MASK_R_MGG_FIFO_INT_FLAG)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_R_MGG_FIFO_INT_MASK 0
-#define BIT_MASK_R_MGG_FIFO_INT_MASK 0xffff
-#define BIT_R_MGG_FIFO_INT_MASK(x) (((x) & BIT_MASK_R_MGG_FIFO_INT_MASK) << BIT_SHIFT_R_MGG_FIFO_INT_MASK)
-#define BIT_GET_R_MGG_FIFO_INT_MASK(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_MASK) & BIT_MASK_R_MGG_FIFO_INT_MASK)
+/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */
+#define BIT_CLI0_WMAC_TCRPWRMGT_HWDATA_EN BIT(2)
-/* 2 REG_MGG_FIFO_LIFETIME (Offset 0x1478) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_R_MGG_FIFO_LIFETIME 16
-#define BIT_MASK_R_MGG_FIFO_LIFETIME 0xffff
-#define BIT_R_MGG_FIFO_LIFETIME(x) (((x) & BIT_MASK_R_MGG_FIFO_LIFETIME) << BIT_SHIFT_R_MGG_FIFO_LIFETIME)
-#define BIT_GET_R_MGG_FIFO_LIFETIME(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_LIFETIME) & BIT_MASK_R_MGG_FIFO_LIFETIME)
+/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */
+#define BIT_CLI0_PWRBIT_OW_EN BIT(1)
-#define BIT_SHIFT_R_MGG_FIFO_VALID_MAP 0
-#define BIT_MASK_R_MGG_FIFO_VALID_MAP 0xffff
-#define BIT_R_MGG_FIFO_VALID_MAP(x) (((x) & BIT_MASK_R_MGG_FIFO_VALID_MAP) << BIT_SHIFT_R_MGG_FIFO_VALID_MAP)
-#define BIT_GET_R_MGG_FIFO_VALID_MAP(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_VALID_MAP) & BIT_MASK_R_MGG_FIFO_VALID_MAP)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET (Offset 0x147C) */
+/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */
+#define BIT_CLI0_WMAC_TCRPWRMGT_HWACT_EN BIT(1)
-#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET 0
-#define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET 0x7f
-#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET)
-#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_P2PON_DIS_TXTIME 0
-#define BIT_MASK_P2PON_DIS_TXTIME 0xff
-#define BIT_P2PON_DIS_TXTIME(x) (((x) & BIT_MASK_P2PON_DIS_TXTIME) << BIT_SHIFT_P2PON_DIS_TXTIME)
-#define BIT_GET_P2PON_DIS_TXTIME(x) (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME) & BIT_MASK_P2PON_DIS_TXTIME)
+/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */
+#define BIT_CLI0_PWR_ST BIT(0)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8822B_SUPPORT)
+/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */
+#define BIT_CLI0_PWR_ST_V1 BIT(0)
-/* 2 REG_MACID_SHCUT_OFFSET (Offset 0x1480) */
+#endif
+#if (HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_MACID_SHCUT_OFFSET_V1 0
-#define BIT_MASK_MACID_SHCUT_OFFSET_V1 0xff
-#define BIT_MACID_SHCUT_OFFSET_V1(x) (((x) & BIT_MASK_MACID_SHCUT_OFFSET_V1) << BIT_SHIFT_MACID_SHCUT_OFFSET_V1)
-#define BIT_GET_MACID_SHCUT_OFFSET_V1(x) (((x) >> BIT_SHIFT_MACID_SHCUT_OFFSET_V1) & BIT_MASK_MACID_SHCUT_OFFSET_V1)
+/* 2 REG_GENERAL_OPTION (Offset 0x1664) */
+#define BIT_WMAC_EXT_DBG_SEL_V1 BIT(6)
+#define BIT_RX_DMA_BYPASS_CHECK_DATABYPASS_CHECK_DATA BIT(4)
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8821C_SUPPORT)
+/* 2 REG_GENERAL_OPTION (Offset 0x1664) */
+#define BIT_PATTERN_MATCH_FIX_EN BIT(3)
-/* 2 REG_MU_TX_CTL (Offset 0x14C0) */
+#endif
-#define BIT_R_FORCE_P1_RATEDOWN BIT(11)
+#if (HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_R_MU_TAB_SEL 8
-#define BIT_MASK_R_MU_TAB_SEL 0x7
-#define BIT_R_MU_TAB_SEL(x) (((x) & BIT_MASK_R_MU_TAB_SEL) << BIT_SHIFT_R_MU_TAB_SEL)
-#define BIT_GET_R_MU_TAB_SEL(x) (((x) >> BIT_SHIFT_R_MU_TAB_SEL) & BIT_MASK_R_MU_TAB_SEL)
+/* 2 REG_GENERAL_OPTION (Offset 0x1664) */
-#define BIT_R_EN_MU_MIMO BIT(7)
+#define BIT_RX_DMA_BYPASS_CHECK_MGTBIT_RX_DMA_BYPASS_CHECK_MGT BIT(3)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_GENERAL_OPTION (Offset 0x1664) */
+#define BIT_TXSERV_FIELD_SEL BIT(2)
+#define BIT_RXVHT_LEN_SEL BIT(1)
+#define BIT_RXMIC_PROTECT_EN BIT(0)
-/* 2 REG_MU_TX_CTL (Offset 0x14C0) */
+#endif
-#define BIT_R_EN_REVERS_GTAB BIT(6)
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_R_MU_TABLE_VALID 0
-#define BIT_MASK_R_MU_TABLE_VALID 0x3f
-#define BIT_R_MU_TABLE_VALID(x) (((x) & BIT_MASK_R_MU_TABLE_VALID) << BIT_SHIFT_R_MU_TABLE_VALID)
-#define BIT_GET_R_MU_TABLE_VALID(x) (((x) >> BIT_SHIFT_R_MU_TABLE_VALID) & BIT_MASK_R_MU_TABLE_VALID)
+/* 2 REG_FWPHYFF_RCR (Offset 0x1668) */
+#define BIT_RCR2_AAMSDU BIT(25)
+#define BIT_RCR2_CBSSID_BCN BIT(24)
+#define BIT_RCR2_ACRC32 BIT(23)
+#define BIT_RCR2_TA_BCN BIT(22)
+#define BIT_RCR2_CBSSID_DATA BIT(21)
+#define BIT_RCR2_ADD3 BIT(20)
+#define BIT_RCR2_AB BIT(19)
+#define BIT_RCR2_AM BIT(18)
+#define BIT_RCR2_APM BIT(17)
+#define BIT_RCR2_AAP BIT(16)
+#define BIT_RCR1_AAMSDU BIT(9)
+#define BIT_RCR1_CBSSID_BCN BIT(8)
+#define BIT_RCR1_ACRC32 BIT(7)
+#define BIT_RCR1_TA_BCN BIT(6)
+#define BIT_RCR1_CBSSID_DATA BIT(5)
+#define BIT_RCR1_ADD3 BIT(4)
+#define BIT_RCR1_AB BIT(3)
+#define BIT_RCR1_AM BIT(2)
+#define BIT_RCR1_APM BIT(1)
+#define BIT_RCR1_AAP BIT(0)
-#define BIT_SHIFT_R_MU_STA_GTAB_VALID 0
-#define BIT_MASK_R_MU_STA_GTAB_VALID 0xffffffffL
-#define BIT_R_MU_STA_GTAB_VALID(x) (((x) & BIT_MASK_R_MU_STA_GTAB_VALID) << BIT_SHIFT_R_MU_STA_GTAB_VALID)
-#define BIT_GET_R_MU_STA_GTAB_VALID(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID) & BIT_MASK_R_MU_STA_GTAB_VALID)
+/* 2 REG_ADDRCAM_WRITE_CONTENT (Offset 0x166C) */
+#define BIT_SHIFT_ADDRCAM_WDATA 0
+#define BIT_MASK_ADDRCAM_WDATA 0xffffffffL
+#define BIT_ADDRCAM_WDATA(x) \
+ (((x) & BIT_MASK_ADDRCAM_WDATA) << BIT_SHIFT_ADDRCAM_WDATA)
+#define BITS_ADDRCAM_WDATA (BIT_MASK_ADDRCAM_WDATA << BIT_SHIFT_ADDRCAM_WDATA)
+#define BIT_CLEAR_ADDRCAM_WDATA(x) ((x) & (~BITS_ADDRCAM_WDATA))
+#define BIT_GET_ADDRCAM_WDATA(x) \
+ (((x) >> BIT_SHIFT_ADDRCAM_WDATA) & BIT_MASK_ADDRCAM_WDATA)
+#define BIT_SET_ADDRCAM_WDATA(x, v) \
+ (BIT_CLEAR_ADDRCAM_WDATA(x) | BIT_ADDRCAM_WDATA(v))
-#define BIT_SHIFT_R_MU_STA_GTAB_POSITION 0
-#define BIT_MASK_R_MU_STA_GTAB_POSITION 0xffffffffffffffffL
-#define BIT_R_MU_STA_GTAB_POSITION(x) (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION) << BIT_SHIFT_R_MU_STA_GTAB_POSITION)
-#define BIT_GET_R_MU_STA_GTAB_POSITION(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION) & BIT_MASK_R_MU_STA_GTAB_POSITION)
+/* 2 REG_ADDRCAM_READ_CONTENT (Offset 0x1670) */
+#define BIT_SHIFT_ADDRCAM_RDATA 0
+#define BIT_MASK_ADDRCAM_RDATA 0xffffffffL
+#define BIT_ADDRCAM_RDATA(x) \
+ (((x) & BIT_MASK_ADDRCAM_RDATA) << BIT_SHIFT_ADDRCAM_RDATA)
+#define BITS_ADDRCAM_RDATA (BIT_MASK_ADDRCAM_RDATA << BIT_SHIFT_ADDRCAM_RDATA)
+#define BIT_CLEAR_ADDRCAM_RDATA(x) ((x) & (~BITS_ADDRCAM_RDATA))
+#define BIT_GET_ADDRCAM_RDATA(x) \
+ (((x) >> BIT_SHIFT_ADDRCAM_RDATA) & BIT_MASK_ADDRCAM_RDATA)
+#define BIT_SET_ADDRCAM_RDATA(x, v) \
+ (BIT_CLEAR_ADDRCAM_RDATA(x) | BIT_ADDRCAM_RDATA(v))
-/* 2 REG_MU_TRX_DBG_CNT (Offset 0x14D0) */
+/* 2 REG_ADDRCAM_CFG (Offset 0x1674) */
+
+#define BIT_ADDRCAM_POLL BIT(31)
+#define BIT__ADDRCAM_WT_EN BIT(30)
+#define BIT_CLRADDRCAM BIT(29)
-#define BIT_MU_DNGCNT_RST BIT(20)
+#define BIT_SHIFT__ADDRCAM_ADDR 8
+#define BIT_MASK__ADDRCAM_ADDR 0x3ff
+#define BIT__ADDRCAM_ADDR(x) \
+ (((x) & BIT_MASK__ADDRCAM_ADDR) << BIT_SHIFT__ADDRCAM_ADDR)
+#define BITS__ADDRCAM_ADDR (BIT_MASK__ADDRCAM_ADDR << BIT_SHIFT__ADDRCAM_ADDR)
+#define BIT_CLEAR__ADDRCAM_ADDR(x) ((x) & (~BITS__ADDRCAM_ADDR))
+#define BIT_GET__ADDRCAM_ADDR(x) \
+ (((x) >> BIT_SHIFT__ADDRCAM_ADDR) & BIT_MASK__ADDRCAM_ADDR)
+#define BIT_SET__ADDRCAM_ADDR(x, v) \
+ (BIT_CLEAR__ADDRCAM_ADDR(x) | BIT__ADDRCAM_ADDR(v))
-#define BIT_SHIFT_MU_DBGCNT_SEL 16
-#define BIT_MASK_MU_DBGCNT_SEL 0xf
-#define BIT_MU_DBGCNT_SEL(x) (((x) & BIT_MASK_MU_DBGCNT_SEL) << BIT_SHIFT_MU_DBGCNT_SEL)
-#define BIT_GET_MU_DBGCNT_SEL(x) (((x) >> BIT_SHIFT_MU_DBGCNT_SEL) & BIT_MASK_MU_DBGCNT_SEL)
+#define BIT_SHIFT_ADDRCAM_RANGE 0
+#define BIT_MASK_ADDRCAM_RANGE 0x7f
+#define BIT_ADDRCAM_RANGE(x) \
+ (((x) & BIT_MASK_ADDRCAM_RANGE) << BIT_SHIFT_ADDRCAM_RANGE)
+#define BITS_ADDRCAM_RANGE (BIT_MASK_ADDRCAM_RANGE << BIT_SHIFT_ADDRCAM_RANGE)
+#define BIT_CLEAR_ADDRCAM_RANGE(x) ((x) & (~BITS_ADDRCAM_RANGE))
+#define BIT_GET_ADDRCAM_RANGE(x) \
+ (((x) >> BIT_SHIFT_ADDRCAM_RANGE) & BIT_MASK_ADDRCAM_RANGE)
+#define BIT_SET_ADDRCAM_RANGE(x, v) \
+ (BIT_CLEAR_ADDRCAM_RANGE(x) | BIT_ADDRCAM_RANGE(v))
+
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_MU_DNGCNT 0
-#define BIT_MASK_MU_DNGCNT 0xffff
-#define BIT_MU_DNGCNT(x) (((x) & BIT_MASK_MU_DNGCNT) << BIT_SHIFT_MU_DNGCNT)
-#define BIT_GET_MU_DNGCNT(x) (((x) >> BIT_SHIFT_MU_DNGCNT) & BIT_MASK_MU_DNGCNT)
+/* 2 REG_CSI_RRSR (Offset 0x1678) */
+#define BIT_CSI_LDPC_EN BIT(29)
+#define BIT_CSI_STBC_EN BIT(28)
+
+#define BIT_SHIFT_CSI_RRSC_BITMAP 4
+#define BIT_MASK_CSI_RRSC_BITMAP 0xffffff
+#define BIT_CSI_RRSC_BITMAP(x) \
+ (((x) & BIT_MASK_CSI_RRSC_BITMAP) << BIT_SHIFT_CSI_RRSC_BITMAP)
+#define BITS_CSI_RRSC_BITMAP \
+ (BIT_MASK_CSI_RRSC_BITMAP << BIT_SHIFT_CSI_RRSC_BITMAP)
+#define BIT_CLEAR_CSI_RRSC_BITMAP(x) ((x) & (~BITS_CSI_RRSC_BITMAP))
+#define BIT_GET_CSI_RRSC_BITMAP(x) \
+ (((x) >> BIT_SHIFT_CSI_RRSC_BITMAP) & BIT_MASK_CSI_RRSC_BITMAP)
+#define BIT_SET_CSI_RRSC_BITMAP(x, v) \
+ (BIT_CLEAR_CSI_RRSC_BITMAP(x) | BIT_CSI_RRSC_BITMAP(v))
+
+#define BIT_SHIFT_OFDM_LEN_TH 0
+#define BIT_MASK_OFDM_LEN_TH 0xf
+#define BIT_OFDM_LEN_TH(x) \
+ (((x) & BIT_MASK_OFDM_LEN_TH) << BIT_SHIFT_OFDM_LEN_TH)
+#define BITS_OFDM_LEN_TH (BIT_MASK_OFDM_LEN_TH << BIT_SHIFT_OFDM_LEN_TH)
+#define BIT_CLEAR_OFDM_LEN_TH(x) ((x) & (~BITS_OFDM_LEN_TH))
+#define BIT_GET_OFDM_LEN_TH(x) \
+ (((x) >> BIT_SHIFT_OFDM_LEN_TH) & BIT_MASK_OFDM_LEN_TH)
+#define BIT_SET_OFDM_LEN_TH(x, v) \
+ (BIT_CLEAR_OFDM_LEN_TH(x) | BIT_OFDM_LEN_TH(v))
+
+#define BIT_SHIFT_WMAC_MULBK_PAGE_SIZE 0
+#define BIT_MASK_WMAC_MULBK_PAGE_SIZE 0xff
+#define BIT_WMAC_MULBK_PAGE_SIZE(x) \
+ (((x) & BIT_MASK_WMAC_MULBK_PAGE_SIZE) \
+ << BIT_SHIFT_WMAC_MULBK_PAGE_SIZE)
+#define BITS_WMAC_MULBK_PAGE_SIZE \
+ (BIT_MASK_WMAC_MULBK_PAGE_SIZE << BIT_SHIFT_WMAC_MULBK_PAGE_SIZE)
+#define BIT_CLEAR_WMAC_MULBK_PAGE_SIZE(x) ((x) & (~BITS_WMAC_MULBK_PAGE_SIZE))
+#define BIT_GET_WMAC_MULBK_PAGE_SIZE(x) \
+ (((x) >> BIT_SHIFT_WMAC_MULBK_PAGE_SIZE) & \
+ BIT_MASK_WMAC_MULBK_PAGE_SIZE)
+#define BIT_SET_WMAC_MULBK_PAGE_SIZE(x, v) \
+ (BIT_CLEAR_WMAC_MULBK_PAGE_SIZE(x) | BIT_WMAC_MULBK_PAGE_SIZE(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_WMAC_MU_BF_OPTION (Offset 0x167C) */
+
+#define BIT_BIT_WMAC_TXMU_ACKPOLICY_EN BIT(6)
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_MU_BF_OPTION (Offset 0x167C) */
+#define BIT_WMAC_TXMU_ACKPOLICY_EN BIT(6)
+
+#endif
-/* 2 REG_CPUMGQ_TX_TIMER (Offset 0x1500) */
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+/* 2 REG_WMAC_PAUSE_BB_CLR_TH (Offset 0x167D) */
-#define BIT_SHIFT_CPUMGQ_TX_TIMER_V1 0
-#define BIT_MASK_CPUMGQ_TX_TIMER_V1 0xffffffffL
-#define BIT_CPUMGQ_TX_TIMER_V1(x) (((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1) << BIT_SHIFT_CPUMGQ_TX_TIMER_V1)
-#define BIT_GET_CPUMGQ_TX_TIMER_V1(x) (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1) & BIT_MASK_CPUMGQ_TX_TIMER_V1)
+#define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH 0
+#define BIT_MASK_WMAC_PAUSE_BB_CLR_TH 0xff
+#define BIT_WMAC_PAUSE_BB_CLR_TH(x) \
+ (((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH) \
+ << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH)
+#define BITS_WMAC_PAUSE_BB_CLR_TH \
+ (BIT_MASK_WMAC_PAUSE_BB_CLR_TH << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH)
+#define BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH(x) ((x) & (~BITS_WMAC_PAUSE_BB_CLR_TH))
+#define BIT_GET_WMAC_PAUSE_BB_CLR_TH(x) \
+ (((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH) & \
+ BIT_MASK_WMAC_PAUSE_BB_CLR_TH)
+#define BIT_SET_WMAC_PAUSE_BB_CLR_TH(x, v) \
+ (BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH(x) | BIT_WMAC_PAUSE_BB_CLR_TH(v))
+#endif
-/* 2 REG_PS_TIMER_A (Offset 0x1504) */
+#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_WMAC_MU_ARB (Offset 0x167E) */
-#define BIT_SHIFT_PS_TIMER_A_V1 0
-#define BIT_MASK_PS_TIMER_A_V1 0xffffffffL
-#define BIT_PS_TIMER_A_V1(x) (((x) & BIT_MASK_PS_TIMER_A_V1) << BIT_SHIFT_PS_TIMER_A_V1)
-#define BIT_GET_PS_TIMER_A_V1(x) (((x) >> BIT_SHIFT_PS_TIMER_A_V1) & BIT_MASK_PS_TIMER_A_V1)
+#define BIT_WMAC_ARB_HW_ADAPT_EN BIT(7)
+#define BIT_WMAC_ARB_SW_EN BIT(6)
+#define BIT_SHIFT_WMAC_ARB_SW_STATE 0
+#define BIT_MASK_WMAC_ARB_SW_STATE 0x3f
+#define BIT_WMAC_ARB_SW_STATE(x) \
+ (((x) & BIT_MASK_WMAC_ARB_SW_STATE) << BIT_SHIFT_WMAC_ARB_SW_STATE)
+#define BITS_WMAC_ARB_SW_STATE \
+ (BIT_MASK_WMAC_ARB_SW_STATE << BIT_SHIFT_WMAC_ARB_SW_STATE)
+#define BIT_CLEAR_WMAC_ARB_SW_STATE(x) ((x) & (~BITS_WMAC_ARB_SW_STATE))
+#define BIT_GET_WMAC_ARB_SW_STATE(x) \
+ (((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE) & BIT_MASK_WMAC_ARB_SW_STATE)
+#define BIT_SET_WMAC_ARB_SW_STATE(x, v) \
+ (BIT_CLEAR_WMAC_ARB_SW_STATE(x) | BIT_WMAC_ARB_SW_STATE(v))
-/* 2 REG_PS_TIMER_B (Offset 0x1508) */
+#endif
+#if (HALMAC_8814B_SUPPORT)
-#define BIT_SHIFT_PS_TIMER_B_V1 0
-#define BIT_MASK_PS_TIMER_B_V1 0xffffffffL
-#define BIT_PS_TIMER_B_V1(x) (((x) & BIT_MASK_PS_TIMER_B_V1) << BIT_SHIFT_PS_TIMER_B_V1)
-#define BIT_GET_PS_TIMER_B_V1(x) (((x) >> BIT_SHIFT_PS_TIMER_B_V1) & BIT_MASK_PS_TIMER_B_V1)
+/* 2 REG_WMAC_MU_OPTION (Offset 0x167F) */
+#define BIT_NOCHK_BFPOLL_BMP BIT(7)
-/* 2 REG_PS_TIMER_C (Offset 0x150C) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_PS_TIMER_C_V1 0
-#define BIT_MASK_PS_TIMER_C_V1 0xffffffffL
-#define BIT_PS_TIMER_C_V1(x) (((x) & BIT_MASK_PS_TIMER_C_V1) << BIT_SHIFT_PS_TIMER_C_V1)
-#define BIT_GET_PS_TIMER_C_V1(x) (((x) >> BIT_SHIFT_PS_TIMER_C_V1) & BIT_MASK_PS_TIMER_C_V1)
+/* 2 REG_WMAC_MU_OPTION (Offset 0x167F) */
+#define BIT_SHIFT_WMAC_MU_DBGSEL 5
+#define BIT_MASK_WMAC_MU_DBGSEL 0x3
+#define BIT_WMAC_MU_DBGSEL(x) \
+ (((x) & BIT_MASK_WMAC_MU_DBGSEL) << BIT_SHIFT_WMAC_MU_DBGSEL)
+#define BITS_WMAC_MU_DBGSEL \
+ (BIT_MASK_WMAC_MU_DBGSEL << BIT_SHIFT_WMAC_MU_DBGSEL)
+#define BIT_CLEAR_WMAC_MU_DBGSEL(x) ((x) & (~BITS_WMAC_MU_DBGSEL))
+#define BIT_GET_WMAC_MU_DBGSEL(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL) & BIT_MASK_WMAC_MU_DBGSEL)
+#define BIT_SET_WMAC_MU_DBGSEL(x, v) \
+ (BIT_CLEAR_WMAC_MU_DBGSEL(x) | BIT_WMAC_MU_DBGSEL(v))
-/* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL (Offset 0x1510) */
+#endif
-#define BIT_CPUMGQ_TIMER_EN BIT(31)
-#define BIT_CPUMGQ_TX_EN BIT(28)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_WMAC_MU_OPTION (Offset 0x167F) */
+
+#define BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT 0
+#define BIT_MASK_WMAC_MU_CPRD_TIMEOUT 0x1f
+#define BIT_WMAC_MU_CPRD_TIMEOUT(x) \
+ (((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT) \
+ << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT)
+#define BITS_WMAC_MU_CPRD_TIMEOUT \
+ (BIT_MASK_WMAC_MU_CPRD_TIMEOUT << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT)
+#define BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT(x) ((x) & (~BITS_WMAC_MU_CPRD_TIMEOUT))
+#define BIT_GET_WMAC_MU_CPRD_TIMEOUT(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT) & \
+ BIT_MASK_WMAC_MU_CPRD_TIMEOUT)
+#define BIT_SET_WMAC_MU_CPRD_TIMEOUT(x, v) \
+ (BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT(x) | BIT_WMAC_MU_CPRD_TIMEOUT(v))
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_MU_BF_CTL (Offset 0x1680) */
+
+#define BIT_WMAC_INVLD_BFPRT_CHK BIT(15)
+#define BIT_WMAC_RETXBFRPTSEQ_UPD BIT(14)
+
+#define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL 12
+#define BIT_MASK_WMAC_MU_BFRPTSEG_SEL 0x3
+#define BIT_WMAC_MU_BFRPTSEG_SEL(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL) \
+ << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL)
+#define BITS_WMAC_MU_BFRPTSEG_SEL \
+ (BIT_MASK_WMAC_MU_BFRPTSEG_SEL << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL)
+#define BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL(x) ((x) & (~BITS_WMAC_MU_BFRPTSEG_SEL))
+#define BIT_GET_WMAC_MU_BFRPTSEG_SEL(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL) & \
+ BIT_MASK_WMAC_MU_BFRPTSEG_SEL)
+#define BIT_SET_WMAC_MU_BFRPTSEG_SEL(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL(x) | BIT_WMAC_MU_BFRPTSEG_SEL(v))
+
+#define BIT_SHIFT_WMAC_MU_BF_MYAID 0
+#define BIT_MASK_WMAC_MU_BF_MYAID 0xfff
+#define BIT_WMAC_MU_BF_MYAID(x) \
+ (((x) & BIT_MASK_WMAC_MU_BF_MYAID) << BIT_SHIFT_WMAC_MU_BF_MYAID)
+#define BITS_WMAC_MU_BF_MYAID \
+ (BIT_MASK_WMAC_MU_BF_MYAID << BIT_SHIFT_WMAC_MU_BF_MYAID)
+#define BIT_CLEAR_WMAC_MU_BF_MYAID(x) ((x) & (~BITS_WMAC_MU_BF_MYAID))
+#define BIT_GET_WMAC_MU_BF_MYAID(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID) & BIT_MASK_WMAC_MU_BF_MYAID)
+#define BIT_SET_WMAC_MU_BF_MYAID(x, v) \
+ (BIT_CLEAR_WMAC_MU_BF_MYAID(x) | BIT_WMAC_MU_BF_MYAID(v))
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_MU_BFRPT_PARA (Offset 0x1682) */
+
+#define BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1 13
+#define BIT_MASK_BFRPT_PARA_USERID_SEL_V1 0x7
+#define BIT_BFRPT_PARA_USERID_SEL_V1(x) \
+ (((x) & BIT_MASK_BFRPT_PARA_USERID_SEL_V1) \
+ << BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1)
+#define BITS_BFRPT_PARA_USERID_SEL_V1 \
+ (BIT_MASK_BFRPT_PARA_USERID_SEL_V1 \
+ << BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1)
+#define BIT_CLEAR_BFRPT_PARA_USERID_SEL_V1(x) \
+ ((x) & (~BITS_BFRPT_PARA_USERID_SEL_V1))
+#define BIT_GET_BFRPT_PARA_USERID_SEL_V1(x) \
+ (((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1) & \
+ BIT_MASK_BFRPT_PARA_USERID_SEL_V1)
+#define BIT_SET_BFRPT_PARA_USERID_SEL_V1(x, v) \
+ (BIT_CLEAR_BFRPT_PARA_USERID_SEL_V1(x) | \
+ BIT_BFRPT_PARA_USERID_SEL_V1(v))
-#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL 24
-#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL 0x7
-#define BIT_CPUMGQ_TIMER_TSF_SEL(x) (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL) << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL)
-#define BIT_GET_CPUMGQ_TIMER_TSF_SEL(x) (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL)
+#endif
-#define BIT_PS_TIMER_C_EN BIT(23)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
-#define BIT_SHIFT_PS_TIMER_C_TSF_SEL 16
-#define BIT_MASK_PS_TIMER_C_TSF_SEL 0x7
-#define BIT_PS_TIMER_C_TSF_SEL(x) (((x) & BIT_MASK_PS_TIMER_C_TSF_SEL) << BIT_SHIFT_PS_TIMER_C_TSF_SEL)
-#define BIT_GET_PS_TIMER_C_TSF_SEL(x) (((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL) & BIT_MASK_PS_TIMER_C_TSF_SEL)
+/* 2 REG_WMAC_MU_BFRPT_PARA (Offset 0x1682) */
-#define BIT_PS_TIMER_B_EN BIT(15)
+#define BIT_SHIFT_BFRPT_PARA_USERID_SEL 12
+#define BIT_MASK_BFRPT_PARA_USERID_SEL 0x7
+#define BIT_BFRPT_PARA_USERID_SEL(x) \
+ (((x) & BIT_MASK_BFRPT_PARA_USERID_SEL) \
+ << BIT_SHIFT_BFRPT_PARA_USERID_SEL)
+#define BITS_BFRPT_PARA_USERID_SEL \
+ (BIT_MASK_BFRPT_PARA_USERID_SEL << BIT_SHIFT_BFRPT_PARA_USERID_SEL)
+#define BIT_CLEAR_BFRPT_PARA_USERID_SEL(x) ((x) & (~BITS_BFRPT_PARA_USERID_SEL))
+#define BIT_GET_BFRPT_PARA_USERID_SEL(x) \
+ (((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL) & \
+ BIT_MASK_BFRPT_PARA_USERID_SEL)
+#define BIT_SET_BFRPT_PARA_USERID_SEL(x, v) \
+ (BIT_CLEAR_BFRPT_PARA_USERID_SEL(x) | BIT_BFRPT_PARA_USERID_SEL(v))
-#define BIT_SHIFT_PS_TIMER_B_TSF_SEL 8
-#define BIT_MASK_PS_TIMER_B_TSF_SEL 0x7
-#define BIT_PS_TIMER_B_TSF_SEL(x) (((x) & BIT_MASK_PS_TIMER_B_TSF_SEL) << BIT_SHIFT_PS_TIMER_B_TSF_SEL)
-#define BIT_GET_PS_TIMER_B_TSF_SEL(x) (((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL) & BIT_MASK_PS_TIMER_B_TSF_SEL)
+#endif
-#define BIT_PS_TIMER_A_EN BIT(7)
+#if (HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_PS_TIMER_A_TSF_SEL 0
-#define BIT_MASK_PS_TIMER_A_TSF_SEL 0x7
-#define BIT_PS_TIMER_A_TSF_SEL(x) (((x) & BIT_MASK_PS_TIMER_A_TSF_SEL) << BIT_SHIFT_PS_TIMER_A_TSF_SEL)
-#define BIT_GET_PS_TIMER_A_TSF_SEL(x) (((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL) & BIT_MASK_PS_TIMER_A_TSF_SEL)
+/* 2 REG_WMAC_MU_BFRPT_PARA (Offset 0x1682) */
+#define BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL 12
+#define BIT_MASK_BIT_BFRPT_PARA_USERID_SEL 0x7
+#define BIT_BIT_BFRPT_PARA_USERID_SEL(x) \
+ (((x) & BIT_MASK_BIT_BFRPT_PARA_USERID_SEL) \
+ << BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL)
+#define BITS_BIT_BFRPT_PARA_USERID_SEL \
+ (BIT_MASK_BIT_BFRPT_PARA_USERID_SEL \
+ << BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL)
+#define BIT_CLEAR_BIT_BFRPT_PARA_USERID_SEL(x) \
+ ((x) & (~BITS_BIT_BFRPT_PARA_USERID_SEL))
+#define BIT_GET_BIT_BFRPT_PARA_USERID_SEL(x) \
+ (((x) >> BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL) & \
+ BIT_MASK_BIT_BFRPT_PARA_USERID_SEL)
+#define BIT_SET_BIT_BFRPT_PARA_USERID_SEL(x, v) \
+ (BIT_CLEAR_BIT_BFRPT_PARA_USERID_SEL(x) | \
+ BIT_BIT_BFRPT_PARA_USERID_SEL(v))
-/* 2 REG_CPUMGQ_TX_TIMER_EARLY (Offset 0x1514) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY 0
-#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY 0xff
-#define BIT_CPUMGQ_TX_TIMER_EARLY(x) (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY) << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY)
-#define BIT_GET_CPUMGQ_TX_TIMER_EARLY(x) (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY)
+/* 2 REG_WMAC_MU_BFRPT_PARA (Offset 0x1682) */
+#define BIT_SHIFT_BFRPT_PARA 0
+#define BIT_MASK_BFRPT_PARA 0xfff
+#define BIT_BFRPT_PARA(x) (((x) & BIT_MASK_BFRPT_PARA) << BIT_SHIFT_BFRPT_PARA)
+#define BITS_BFRPT_PARA (BIT_MASK_BFRPT_PARA << BIT_SHIFT_BFRPT_PARA)
+#define BIT_CLEAR_BFRPT_PARA(x) ((x) & (~BITS_BFRPT_PARA))
+#define BIT_GET_BFRPT_PARA(x) \
+ (((x) >> BIT_SHIFT_BFRPT_PARA) & BIT_MASK_BFRPT_PARA)
+#define BIT_SET_BFRPT_PARA(x, v) (BIT_CLEAR_BFRPT_PARA(x) | BIT_BFRPT_PARA(v))
-/* 2 REG_PS_TIMER_A_EARLY (Offset 0x1515) */
+#endif
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_PS_TIMER_A_EARLY 0
-#define BIT_MASK_PS_TIMER_A_EARLY 0xff
-#define BIT_PS_TIMER_A_EARLY(x) (((x) & BIT_MASK_PS_TIMER_A_EARLY) << BIT_SHIFT_PS_TIMER_A_EARLY)
-#define BIT_GET_PS_TIMER_A_EARLY(x) (((x) >> BIT_SHIFT_PS_TIMER_A_EARLY) & BIT_MASK_PS_TIMER_A_EARLY)
+/* 2 REG_WMAC_MU_BFRPT_PARA (Offset 0x1682) */
+#define BIT_SHIFT_BFRPT_PARA_V1 0
+#define BIT_MASK_BFRPT_PARA_V1 0x1fff
+#define BIT_BFRPT_PARA_V1(x) \
+ (((x) & BIT_MASK_BFRPT_PARA_V1) << BIT_SHIFT_BFRPT_PARA_V1)
+#define BITS_BFRPT_PARA_V1 (BIT_MASK_BFRPT_PARA_V1 << BIT_SHIFT_BFRPT_PARA_V1)
+#define BIT_CLEAR_BFRPT_PARA_V1(x) ((x) & (~BITS_BFRPT_PARA_V1))
+#define BIT_GET_BFRPT_PARA_V1(x) \
+ (((x) >> BIT_SHIFT_BFRPT_PARA_V1) & BIT_MASK_BFRPT_PARA_V1)
+#define BIT_SET_BFRPT_PARA_V1(x, v) \
+ (BIT_CLEAR_BFRPT_PARA_V1(x) | BIT_BFRPT_PARA_V1(v))
-/* 2 REG_PS_TIMER_B_EARLY (Offset 0x1516) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_PS_TIMER_B_EARLY 0
-#define BIT_MASK_PS_TIMER_B_EARLY 0xff
-#define BIT_PS_TIMER_B_EARLY(x) (((x) & BIT_MASK_PS_TIMER_B_EARLY) << BIT_SHIFT_PS_TIMER_B_EARLY)
-#define BIT_GET_PS_TIMER_B_EARLY(x) (((x) >> BIT_SHIFT_PS_TIMER_B_EARLY) & BIT_MASK_PS_TIMER_B_EARLY)
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2 (Offset 0x1684) */
+#define BIT_STATUS_BFEE2 BIT(10)
-/* 2 REG_PS_TIMER_C_EARLY (Offset 0x1517) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_PS_TIMER_C_EARLY 0
-#define BIT_MASK_PS_TIMER_C_EARLY 0xff
-#define BIT_PS_TIMER_C_EARLY(x) (((x) & BIT_MASK_PS_TIMER_C_EARLY) << BIT_SHIFT_PS_TIMER_C_EARLY)
-#define BIT_GET_PS_TIMER_C_EARLY(x) (((x) >> BIT_SHIFT_PS_TIMER_C_EARLY) & BIT_MASK_PS_TIMER_C_EARLY)
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2 (Offset 0x1684) */
+#define BIT_WMAC_MU_BFEE2_EN BIT(9)
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2 (Offset 0x1684) */
-/* 2 REG_BCN_PSR_RPT2 (Offset 0x1600) */
+#define BIT_WMAC_MU_BFEE2_USER_EN BIT(9)
+#endif
-#define BIT_SHIFT_DTIM_CNT2 24
-#define BIT_MASK_DTIM_CNT2 0xff
-#define BIT_DTIM_CNT2(x) (((x) & BIT_MASK_DTIM_CNT2) << BIT_SHIFT_DTIM_CNT2)
-#define BIT_GET_DTIM_CNT2(x) (((x) >> BIT_SHIFT_DTIM_CNT2) & BIT_MASK_DTIM_CNT2)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2 (Offset 0x1684) */
-#define BIT_SHIFT_DTIM_PERIOD2 16
-#define BIT_MASK_DTIM_PERIOD2 0xff
-#define BIT_DTIM_PERIOD2(x) (((x) & BIT_MASK_DTIM_PERIOD2) << BIT_SHIFT_DTIM_PERIOD2)
-#define BIT_GET_DTIM_PERIOD2(x) (((x) >> BIT_SHIFT_DTIM_PERIOD2) & BIT_MASK_DTIM_PERIOD2)
+#define BIT_SHIFT_WMAC_MU_BFEE2_AID 0
+#define BIT_MASK_WMAC_MU_BFEE2_AID 0x1ff
+#define BIT_WMAC_MU_BFEE2_AID(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE2_AID) << BIT_SHIFT_WMAC_MU_BFEE2_AID)
+#define BITS_WMAC_MU_BFEE2_AID \
+ (BIT_MASK_WMAC_MU_BFEE2_AID << BIT_SHIFT_WMAC_MU_BFEE2_AID)
+#define BIT_CLEAR_WMAC_MU_BFEE2_AID(x) ((x) & (~BITS_WMAC_MU_BFEE2_AID))
+#define BIT_GET_WMAC_MU_BFEE2_AID(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID) & BIT_MASK_WMAC_MU_BFEE2_AID)
+#define BIT_SET_WMAC_MU_BFEE2_AID(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE2_AID(x) | BIT_WMAC_MU_BFEE2_AID(v))
-#define BIT_DTIM2 BIT(15)
-#define BIT_TIM2 BIT(14)
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3 (Offset 0x1686) */
-#define BIT_SHIFT_PS_AID_2 0
-#define BIT_MASK_PS_AID_2 0x7ff
-#define BIT_PS_AID_2(x) (((x) & BIT_MASK_PS_AID_2) << BIT_SHIFT_PS_AID_2)
-#define BIT_GET_PS_AID_2(x) (((x) >> BIT_SHIFT_PS_AID_2) & BIT_MASK_PS_AID_2)
+#define BIT_STATUS_BFEE3 BIT(10)
+#endif
-/* 2 REG_BCN_PSR_RPT3 (Offset 0x1604) */
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3 (Offset 0x1686) */
-#define BIT_SHIFT_DTIM_CNT3 24
-#define BIT_MASK_DTIM_CNT3 0xff
-#define BIT_DTIM_CNT3(x) (((x) & BIT_MASK_DTIM_CNT3) << BIT_SHIFT_DTIM_CNT3)
-#define BIT_GET_DTIM_CNT3(x) (((x) >> BIT_SHIFT_DTIM_CNT3) & BIT_MASK_DTIM_CNT3)
+#define BIT_WMAC_MU_BFEE3_EN BIT(9)
+#endif
-#define BIT_SHIFT_DTIM_PERIOD3 16
-#define BIT_MASK_DTIM_PERIOD3 0xff
-#define BIT_DTIM_PERIOD3(x) (((x) & BIT_MASK_DTIM_PERIOD3) << BIT_SHIFT_DTIM_PERIOD3)
-#define BIT_GET_DTIM_PERIOD3(x) (((x) >> BIT_SHIFT_DTIM_PERIOD3) & BIT_MASK_DTIM_PERIOD3)
+#if (HALMAC_8198F_SUPPORT)
-#define BIT_DTIM3 BIT(15)
-#define BIT_TIM3 BIT(14)
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3 (Offset 0x1686) */
-#define BIT_SHIFT_PS_AID_3 0
-#define BIT_MASK_PS_AID_3 0x7ff
-#define BIT_PS_AID_3(x) (((x) & BIT_MASK_PS_AID_3) << BIT_SHIFT_PS_AID_3)
-#define BIT_GET_PS_AID_3(x) (((x) >> BIT_SHIFT_PS_AID_3) & BIT_MASK_PS_AID_3)
+#define BIT_WMAC_MU_BFEE3_USER_EN BIT(9)
+#endif
-/* 2 REG_BCN_PSR_RPT4 (Offset 0x1608) */
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3 (Offset 0x1686) */
-#define BIT_SHIFT_DTIM_CNT4 24
-#define BIT_MASK_DTIM_CNT4 0xff
-#define BIT_DTIM_CNT4(x) (((x) & BIT_MASK_DTIM_CNT4) << BIT_SHIFT_DTIM_CNT4)
-#define BIT_GET_DTIM_CNT4(x) (((x) >> BIT_SHIFT_DTIM_CNT4) & BIT_MASK_DTIM_CNT4)
+#define BIT_SHIFT_WMAC_MU_BFEE3_AID 0
+#define BIT_MASK_WMAC_MU_BFEE3_AID 0x1ff
+#define BIT_WMAC_MU_BFEE3_AID(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE3_AID) << BIT_SHIFT_WMAC_MU_BFEE3_AID)
+#define BITS_WMAC_MU_BFEE3_AID \
+ (BIT_MASK_WMAC_MU_BFEE3_AID << BIT_SHIFT_WMAC_MU_BFEE3_AID)
+#define BIT_CLEAR_WMAC_MU_BFEE3_AID(x) ((x) & (~BITS_WMAC_MU_BFEE3_AID))
+#define BIT_GET_WMAC_MU_BFEE3_AID(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID) & BIT_MASK_WMAC_MU_BFEE3_AID)
+#define BIT_SET_WMAC_MU_BFEE3_AID(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE3_AID(x) | BIT_WMAC_MU_BFEE3_AID(v))
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4 (Offset 0x1688) */
-#define BIT_SHIFT_DTIM_PERIOD4 16
-#define BIT_MASK_DTIM_PERIOD4 0xff
-#define BIT_DTIM_PERIOD4(x) (((x) & BIT_MASK_DTIM_PERIOD4) << BIT_SHIFT_DTIM_PERIOD4)
-#define BIT_GET_DTIM_PERIOD4(x) (((x) >> BIT_SHIFT_DTIM_PERIOD4) & BIT_MASK_DTIM_PERIOD4)
+#define BIT_STATUS_BFEE4 BIT(10)
+#define BIT_WMAC_MU_BFEE4_EN BIT(9)
-#define BIT_DTIM4 BIT(15)
-#define BIT_TIM4 BIT(14)
+#define BIT_SHIFT_WMAC_MU_BFEE4_AID 0
+#define BIT_MASK_WMAC_MU_BFEE4_AID 0x1ff
+#define BIT_WMAC_MU_BFEE4_AID(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE4_AID) << BIT_SHIFT_WMAC_MU_BFEE4_AID)
+#define BITS_WMAC_MU_BFEE4_AID \
+ (BIT_MASK_WMAC_MU_BFEE4_AID << BIT_SHIFT_WMAC_MU_BFEE4_AID)
+#define BIT_CLEAR_WMAC_MU_BFEE4_AID(x) ((x) & (~BITS_WMAC_MU_BFEE4_AID))
+#define BIT_GET_WMAC_MU_BFEE4_AID(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID) & BIT_MASK_WMAC_MU_BFEE4_AID)
+#define BIT_SET_WMAC_MU_BFEE4_AID(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE4_AID(x) | BIT_WMAC_MU_BFEE4_AID(v))
-#define BIT_SHIFT_PS_AID_4 0
-#define BIT_MASK_PS_AID_4 0x7ff
-#define BIT_PS_AID_4(x) (((x) & BIT_MASK_PS_AID_4) << BIT_SHIFT_PS_AID_4)
-#define BIT_GET_PS_AID_4(x) (((x) >> BIT_SHIFT_PS_AID_4) & BIT_MASK_PS_AID_4)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
-/* 2 REG_A1_ADDR_MASK (Offset 0x160C) */
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5 (Offset 0x168A) */
+#define BIT_STATUS_BFEE5 BIT(10)
-#define BIT_SHIFT_A1_ADDR_MASK 0
-#define BIT_MASK_A1_ADDR_MASK 0xffffffffL
-#define BIT_A1_ADDR_MASK(x) (((x) & BIT_MASK_A1_ADDR_MASK) << BIT_SHIFT_A1_ADDR_MASK)
-#define BIT_GET_A1_ADDR_MASK(x) (((x) >> BIT_SHIFT_A1_ADDR_MASK) & BIT_MASK_A1_ADDR_MASK)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_MACID2 (Offset 0x1620) */
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5 (Offset 0x168A) */
+#define BIT_BIT_STATUS_BFEE5 BIT(10)
-#define BIT_SHIFT_MACID2 0
-#define BIT_MASK_MACID2 0xffffffffffffL
-#define BIT_MACID2(x) (((x) & BIT_MASK_MACID2) << BIT_SHIFT_MACID2)
-#define BIT_GET_MACID2(x) (((x) >> BIT_SHIFT_MACID2) & BIT_MASK_MACID2)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-/* 2 REG_BSSID2 (Offset 0x1628) */
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5 (Offset 0x168A) */
+#define BIT_WMAC_MU_BFEE5_EN BIT(9)
-#define BIT_SHIFT_BSSID2 0
-#define BIT_MASK_BSSID2 0xffffffffffffL
-#define BIT_BSSID2(x) (((x) & BIT_MASK_BSSID2) << BIT_SHIFT_BSSID2)
-#define BIT_GET_BSSID2(x) (((x) >> BIT_SHIFT_BSSID2) & BIT_MASK_BSSID2)
+#define BIT_SHIFT_WMAC_MU_BFEE5_AID 0
+#define BIT_MASK_WMAC_MU_BFEE5_AID 0x1ff
+#define BIT_WMAC_MU_BFEE5_AID(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE5_AID) << BIT_SHIFT_WMAC_MU_BFEE5_AID)
+#define BITS_WMAC_MU_BFEE5_AID \
+ (BIT_MASK_WMAC_MU_BFEE5_AID << BIT_SHIFT_WMAC_MU_BFEE5_AID)
+#define BIT_CLEAR_WMAC_MU_BFEE5_AID(x) ((x) & (~BITS_WMAC_MU_BFEE5_AID))
+#define BIT_GET_WMAC_MU_BFEE5_AID(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID) & BIT_MASK_WMAC_MU_BFEE5_AID)
+#define BIT_SET_WMAC_MU_BFEE5_AID(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE5_AID(x) | BIT_WMAC_MU_BFEE5_AID(v))
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6 (Offset 0x168C) */
-/* 2 REG_MACID3 (Offset 0x1630) */
+#define BIT_STATUS_BFEE6 BIT(10)
+#define BIT_WMAC_MU_BFEE6_EN BIT(9)
+#define BIT_SHIFT_WMAC_MU_BFEE6_AID 0
+#define BIT_MASK_WMAC_MU_BFEE6_AID 0x1ff
+#define BIT_WMAC_MU_BFEE6_AID(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE6_AID) << BIT_SHIFT_WMAC_MU_BFEE6_AID)
+#define BITS_WMAC_MU_BFEE6_AID \
+ (BIT_MASK_WMAC_MU_BFEE6_AID << BIT_SHIFT_WMAC_MU_BFEE6_AID)
+#define BIT_CLEAR_WMAC_MU_BFEE6_AID(x) ((x) & (~BITS_WMAC_MU_BFEE6_AID))
+#define BIT_GET_WMAC_MU_BFEE6_AID(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID) & BIT_MASK_WMAC_MU_BFEE6_AID)
+#define BIT_SET_WMAC_MU_BFEE6_AID(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE6_AID(x) | BIT_WMAC_MU_BFEE6_AID(v))
-#define BIT_SHIFT_MACID3 0
-#define BIT_MASK_MACID3 0xffffffffffffL
-#define BIT_MACID3(x) (((x) & BIT_MASK_MACID3) << BIT_SHIFT_MACID3)
-#define BIT_GET_MACID3(x) (((x) >> BIT_SHIFT_MACID3) & BIT_MASK_MACID3)
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-/* 2 REG_BSSID3 (Offset 0x1638) */
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7 (Offset 0x168E) */
+#define BIT_BIT_STATUS_BFEE4 BIT(10)
-#define BIT_SHIFT_BSSID3 0
-#define BIT_MASK_BSSID3 0xffffffffffffL
-#define BIT_BSSID3(x) (((x) & BIT_MASK_BSSID3) << BIT_SHIFT_BSSID3)
-#define BIT_GET_BSSID3(x) (((x) >> BIT_SHIFT_BSSID3) & BIT_MASK_BSSID3)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7 (Offset 0x168E) */
-/* 2 REG_MACID4 (Offset 0x1640) */
+#define BIT_STATUS_BFEE7 BIT(10)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7 (Offset 0x168E) */
+
+#define BIT_WMAC_MU_BFEE7_EN BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE7_AID 0
+#define BIT_MASK_WMAC_MU_BFEE7_AID 0x1ff
+#define BIT_WMAC_MU_BFEE7_AID(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE7_AID) << BIT_SHIFT_WMAC_MU_BFEE7_AID)
+#define BITS_WMAC_MU_BFEE7_AID \
+ (BIT_MASK_WMAC_MU_BFEE7_AID << BIT_SHIFT_WMAC_MU_BFEE7_AID)
+#define BIT_CLEAR_WMAC_MU_BFEE7_AID(x) ((x) & (~BITS_WMAC_MU_BFEE7_AID))
+#define BIT_GET_WMAC_MU_BFEE7_AID(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID) & BIT_MASK_WMAC_MU_BFEE7_AID)
+#define BIT_SET_WMAC_MU_BFEE7_AID(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE7_AID(x) | BIT_WMAC_MU_BFEE7_AID(v))
+/* 2 REG_WMAC_BB_STOP_RX_COUNTER (Offset 0x1690) */
-#define BIT_SHIFT_MACID4 0
-#define BIT_MASK_MACID4 0xffffffffffffL
-#define BIT_MACID4(x) (((x) & BIT_MASK_MACID4) << BIT_SHIFT_MACID4)
-#define BIT_GET_MACID4(x) (((x) >> BIT_SHIFT_MACID4) & BIT_MASK_MACID4)
+#define BIT_RST_ALL_COUNTER BIT(31)
+#define BIT_SHIFT_ABORT_RX_VBON_COUNTER 16
+#define BIT_MASK_ABORT_RX_VBON_COUNTER 0xff
+#define BIT_ABORT_RX_VBON_COUNTER(x) \
+ (((x) & BIT_MASK_ABORT_RX_VBON_COUNTER) \
+ << BIT_SHIFT_ABORT_RX_VBON_COUNTER)
+#define BITS_ABORT_RX_VBON_COUNTER \
+ (BIT_MASK_ABORT_RX_VBON_COUNTER << BIT_SHIFT_ABORT_RX_VBON_COUNTER)
+#define BIT_CLEAR_ABORT_RX_VBON_COUNTER(x) ((x) & (~BITS_ABORT_RX_VBON_COUNTER))
+#define BIT_GET_ABORT_RX_VBON_COUNTER(x) \
+ (((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER) & \
+ BIT_MASK_ABORT_RX_VBON_COUNTER)
+#define BIT_SET_ABORT_RX_VBON_COUNTER(x, v) \
+ (BIT_CLEAR_ABORT_RX_VBON_COUNTER(x) | BIT_ABORT_RX_VBON_COUNTER(v))
-/* 2 REG_BSSID4 (Offset 0x1648) */
+#define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER 8
+#define BIT_MASK_ABORT_RX_RDRDY_COUNTER 0xff
+#define BIT_ABORT_RX_RDRDY_COUNTER(x) \
+ (((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER) \
+ << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER)
+#define BITS_ABORT_RX_RDRDY_COUNTER \
+ (BIT_MASK_ABORT_RX_RDRDY_COUNTER << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER)
+#define BIT_CLEAR_ABORT_RX_RDRDY_COUNTER(x) \
+ ((x) & (~BITS_ABORT_RX_RDRDY_COUNTER))
+#define BIT_GET_ABORT_RX_RDRDY_COUNTER(x) \
+ (((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER) & \
+ BIT_MASK_ABORT_RX_RDRDY_COUNTER)
+#define BIT_SET_ABORT_RX_RDRDY_COUNTER(x, v) \
+ (BIT_CLEAR_ABORT_RX_RDRDY_COUNTER(x) | BIT_ABORT_RX_RDRDY_COUNTER(v))
+
+#define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER 0
+#define BIT_MASK_VBON_EARLY_FALLING_COUNTER 0xff
+#define BIT_VBON_EARLY_FALLING_COUNTER(x) \
+ (((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER) \
+ << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER)
+#define BITS_VBON_EARLY_FALLING_COUNTER \
+ (BIT_MASK_VBON_EARLY_FALLING_COUNTER \
+ << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER)
+#define BIT_CLEAR_VBON_EARLY_FALLING_COUNTER(x) \
+ ((x) & (~BITS_VBON_EARLY_FALLING_COUNTER))
+#define BIT_GET_VBON_EARLY_FALLING_COUNTER(x) \
+ (((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER) & \
+ BIT_MASK_VBON_EARLY_FALLING_COUNTER)
+#define BIT_SET_VBON_EARLY_FALLING_COUNTER(x, v) \
+ (BIT_CLEAR_VBON_EARLY_FALLING_COUNTER(x) | \
+ BIT_VBON_EARLY_FALLING_COUNTER(v))
+
+/* 2 REG_WMAC_PLCP_MONITOR (Offset 0x1694) */
+
+#define BIT_WMAC_PLCP_TRX_SEL BIT(31)
+
+#define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL 28
+#define BIT_MASK_WMAC_PLCP_RDSIG_SEL 0x7
+#define BIT_WMAC_PLCP_RDSIG_SEL(x) \
+ (((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL) << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL)
+#define BITS_WMAC_PLCP_RDSIG_SEL \
+ (BIT_MASK_WMAC_PLCP_RDSIG_SEL << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL)
+#define BIT_CLEAR_WMAC_PLCP_RDSIG_SEL(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_SEL))
+#define BIT_GET_WMAC_PLCP_RDSIG_SEL(x) \
+ (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL) & BIT_MASK_WMAC_PLCP_RDSIG_SEL)
+#define BIT_SET_WMAC_PLCP_RDSIG_SEL(x, v) \
+ (BIT_CLEAR_WMAC_PLCP_RDSIG_SEL(x) | BIT_WMAC_PLCP_RDSIG_SEL(v))
+
+#define BIT_SHIFT_WMAC_RATE_IDX 24
+#define BIT_MASK_WMAC_RATE_IDX 0xf
+#define BIT_WMAC_RATE_IDX(x) \
+ (((x) & BIT_MASK_WMAC_RATE_IDX) << BIT_SHIFT_WMAC_RATE_IDX)
+#define BITS_WMAC_RATE_IDX (BIT_MASK_WMAC_RATE_IDX << BIT_SHIFT_WMAC_RATE_IDX)
+#define BIT_CLEAR_WMAC_RATE_IDX(x) ((x) & (~BITS_WMAC_RATE_IDX))
+#define BIT_GET_WMAC_RATE_IDX(x) \
+ (((x) >> BIT_SHIFT_WMAC_RATE_IDX) & BIT_MASK_WMAC_RATE_IDX)
+#define BIT_SET_WMAC_RATE_IDX(x, v) \
+ (BIT_CLEAR_WMAC_RATE_IDX(x) | BIT_WMAC_RATE_IDX(v))
+
+#define BIT_SHIFT_WMAC_PLCP_RDSIG 0
+#define BIT_MASK_WMAC_PLCP_RDSIG 0xffffff
+#define BIT_WMAC_PLCP_RDSIG(x) \
+ (((x) & BIT_MASK_WMAC_PLCP_RDSIG) << BIT_SHIFT_WMAC_PLCP_RDSIG)
+#define BITS_WMAC_PLCP_RDSIG \
+ (BIT_MASK_WMAC_PLCP_RDSIG << BIT_SHIFT_WMAC_PLCP_RDSIG)
+#define BIT_CLEAR_WMAC_PLCP_RDSIG(x) ((x) & (~BITS_WMAC_PLCP_RDSIG))
+#define BIT_GET_WMAC_PLCP_RDSIG(x) \
+ (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG) & BIT_MASK_WMAC_PLCP_RDSIG)
+#define BIT_SET_WMAC_PLCP_RDSIG(x, v) \
+ (BIT_CLEAR_WMAC_PLCP_RDSIG(x) | BIT_WMAC_PLCP_RDSIG(v))
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_PLCP_MONITOR_MUTX (Offset 0x1698) */
+
+#define BIT_WMAC_MUTX_IDX BIT(24)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_WMAC_DEBUG_PORT (Offset 0x1698) */
+
+#define BIT_SHIFT_WMAC_DEBUG_PORT 0
+#define BIT_MASK_WMAC_DEBUG_PORT 0xffffffffL
+#define BIT_WMAC_DEBUG_PORT(x) \
+ (((x) & BIT_MASK_WMAC_DEBUG_PORT) << BIT_SHIFT_WMAC_DEBUG_PORT)
+#define BITS_WMAC_DEBUG_PORT \
+ (BIT_MASK_WMAC_DEBUG_PORT << BIT_SHIFT_WMAC_DEBUG_PORT)
+#define BIT_CLEAR_WMAC_DEBUG_PORT(x) ((x) & (~BITS_WMAC_DEBUG_PORT))
+#define BIT_GET_WMAC_DEBUG_PORT(x) \
+ (((x) >> BIT_SHIFT_WMAC_DEBUG_PORT) & BIT_MASK_WMAC_DEBUG_PORT)
+#define BIT_SET_WMAC_DEBUG_PORT(x, v) \
+ (BIT_CLEAR_WMAC_DEBUG_PORT(x) | BIT_WMAC_DEBUG_PORT(v))
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+/* 2 REG_WMAC_CSIDMA_CFG (Offset 0x169C) */
+
+#define BIT_SHIFT_CSI_SEG_SIZE 16
+#define BIT_MASK_CSI_SEG_SIZE 0xfff
+#define BIT_CSI_SEG_SIZE(x) \
+ (((x) & BIT_MASK_CSI_SEG_SIZE) << BIT_SHIFT_CSI_SEG_SIZE)
+#define BITS_CSI_SEG_SIZE (BIT_MASK_CSI_SEG_SIZE << BIT_SHIFT_CSI_SEG_SIZE)
+#define BIT_CLEAR_CSI_SEG_SIZE(x) ((x) & (~BITS_CSI_SEG_SIZE))
+#define BIT_GET_CSI_SEG_SIZE(x) \
+ (((x) >> BIT_SHIFT_CSI_SEG_SIZE) & BIT_MASK_CSI_SEG_SIZE)
+#define BIT_SET_CSI_SEG_SIZE(x, v) \
+ (BIT_CLEAR_CSI_SEG_SIZE(x) | BIT_CSI_SEG_SIZE(v))
+
+#define BIT_SHIFT_CSI_START_PAGE 0
+#define BIT_MASK_CSI_START_PAGE 0xfff
+#define BIT_CSI_START_PAGE(x) \
+ (((x) & BIT_MASK_CSI_START_PAGE) << BIT_SHIFT_CSI_START_PAGE)
+#define BITS_CSI_START_PAGE \
+ (BIT_MASK_CSI_START_PAGE << BIT_SHIFT_CSI_START_PAGE)
+#define BIT_CLEAR_CSI_START_PAGE(x) ((x) & (~BITS_CSI_START_PAGE))
+#define BIT_GET_CSI_START_PAGE(x) \
+ (((x) >> BIT_SHIFT_CSI_START_PAGE) & BIT_MASK_CSI_START_PAGE)
+#define BIT_SET_CSI_START_PAGE(x, v) \
+ (BIT_CLEAR_CSI_START_PAGE(x) | BIT_CSI_START_PAGE(v))
+
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_BSSID4 0
-#define BIT_MASK_BSSID4 0xffffffffffffL
-#define BIT_BSSID4(x) (((x) & BIT_MASK_BSSID4) << BIT_SHIFT_BSSID4)
-#define BIT_GET_BSSID4(x) (((x) >> BIT_SHIFT_BSSID4) & BIT_MASK_BSSID4)
+/* 2 REG_TRANSMIT_ADDRSS_0 (Offset 0x16A0) */
+#define BIT_SHIFT_TA0 0
+#define BIT_MASK_TA0 0xffffffffffffL
+#define BIT_TA0(x) (((x) & BIT_MASK_TA0) << BIT_SHIFT_TA0)
+#define BITS_TA0 (BIT_MASK_TA0 << BIT_SHIFT_TA0)
+#define BIT_CLEAR_TA0(x) ((x) & (~BITS_TA0))
+#define BIT_GET_TA0(x) (((x) >> BIT_SHIFT_TA0) & BIT_MASK_TA0)
+#define BIT_SET_TA0(x, v) (BIT_CLEAR_TA0(x) | BIT_TA0(v))
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_TRANSMIT_ADDRSS_0 (Offset 0x16A0) */
+#define BIT_SHIFT_TA0_V1 0
+#define BIT_MASK_TA0_V1 0xffffffffL
+#define BIT_TA0_V1(x) (((x) & BIT_MASK_TA0_V1) << BIT_SHIFT_TA0_V1)
+#define BITS_TA0_V1 (BIT_MASK_TA0_V1 << BIT_SHIFT_TA0_V1)
+#define BIT_CLEAR_TA0_V1(x) ((x) & (~BITS_TA0_V1))
+#define BIT_GET_TA0_V1(x) (((x) >> BIT_SHIFT_TA0_V1) & BIT_MASK_TA0_V1)
+#define BIT_SET_TA0_V1(x, v) (BIT_CLEAR_TA0_V1(x) | BIT_TA0_V1(v))
-/* 2 REG_PWRBIT_SETTING (Offset 0x1660) */
+/* 2 REG_TRANSMIT_ADDRSS_0_H (Offset 0x16A4) */
-#define BIT_CLI3_PWRBIT_OW_EN BIT(7)
-#define BIT_CLI3_PWR_ST BIT(6)
-#define BIT_CLI2_PWRBIT_OW_EN BIT(5)
-#define BIT_CLI2_PWR_ST BIT(4)
-#define BIT_CLI1_PWRBIT_OW_EN BIT(3)
-#define BIT_CLI1_PWR_ST BIT(2)
-#define BIT_CLI0_PWRBIT_OW_EN BIT(1)
-#define BIT_CLI0_PWR_ST BIT(0)
+#define BIT_SHIFT_TA0_H_V1 0
+#define BIT_MASK_TA0_H_V1 0xffff
+#define BIT_TA0_H_V1(x) (((x) & BIT_MASK_TA0_H_V1) << BIT_SHIFT_TA0_H_V1)
+#define BITS_TA0_H_V1 (BIT_MASK_TA0_H_V1 << BIT_SHIFT_TA0_H_V1)
+#define BIT_CLEAR_TA0_H_V1(x) ((x) & (~BITS_TA0_H_V1))
+#define BIT_GET_TA0_H_V1(x) (((x) >> BIT_SHIFT_TA0_H_V1) & BIT_MASK_TA0_H_V1)
+#define BIT_SET_TA0_H_V1(x, v) (BIT_CLEAR_TA0_H_V1(x) | BIT_TA0_H_V1(v))
-/* 2 REG_TRANSMIT_ADDRSS_0 (Offset 0x16A0) */
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
+
+/* 2 REG_TRANSMIT_ADDRSS_1 (Offset 0x16A8) */
+#define BIT_SHIFT_TA1 0
+#define BIT_MASK_TA1 0xffffffffffffL
+#define BIT_TA1(x) (((x) & BIT_MASK_TA1) << BIT_SHIFT_TA1)
+#define BITS_TA1 (BIT_MASK_TA1 << BIT_SHIFT_TA1)
+#define BIT_CLEAR_TA1(x) ((x) & (~BITS_TA1))
+#define BIT_GET_TA1(x) (((x) >> BIT_SHIFT_TA1) & BIT_MASK_TA1)
+#define BIT_SET_TA1(x, v) (BIT_CLEAR_TA1(x) | BIT_TA1(v))
-#define BIT_SHIFT_TA0 0
-#define BIT_MASK_TA0 0xffffffffffffL
-#define BIT_TA0(x) (((x) & BIT_MASK_TA0) << BIT_SHIFT_TA0)
-#define BIT_GET_TA0(x) (((x) >> BIT_SHIFT_TA0) & BIT_MASK_TA0)
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
/* 2 REG_TRANSMIT_ADDRSS_1 (Offset 0x16A8) */
+#define BIT_SHIFT_TA1_V1 0
+#define BIT_MASK_TA1_V1 0xffffffffL
+#define BIT_TA1_V1(x) (((x) & BIT_MASK_TA1_V1) << BIT_SHIFT_TA1_V1)
+#define BITS_TA1_V1 (BIT_MASK_TA1_V1 << BIT_SHIFT_TA1_V1)
+#define BIT_CLEAR_TA1_V1(x) ((x) & (~BITS_TA1_V1))
+#define BIT_GET_TA1_V1(x) (((x) >> BIT_SHIFT_TA1_V1) & BIT_MASK_TA1_V1)
+#define BIT_SET_TA1_V1(x, v) (BIT_CLEAR_TA1_V1(x) | BIT_TA1_V1(v))
-#define BIT_SHIFT_TA1 0
-#define BIT_MASK_TA1 0xffffffffffffL
-#define BIT_TA1(x) (((x) & BIT_MASK_TA1) << BIT_SHIFT_TA1)
-#define BIT_GET_TA1(x) (((x) >> BIT_SHIFT_TA1) & BIT_MASK_TA1)
+/* 2 REG_TRANSMIT_ADDRSS_1_H (Offset 0x16AC) */
+#define BIT_SHIFT_TA1_H_V1 0
+#define BIT_MASK_TA1_H_V1 0xffff
+#define BIT_TA1_H_V1(x) (((x) & BIT_MASK_TA1_H_V1) << BIT_SHIFT_TA1_H_V1)
+#define BITS_TA1_H_V1 (BIT_MASK_TA1_H_V1 << BIT_SHIFT_TA1_H_V1)
+#define BIT_CLEAR_TA1_H_V1(x) ((x) & (~BITS_TA1_H_V1))
+#define BIT_GET_TA1_H_V1(x) (((x) >> BIT_SHIFT_TA1_H_V1) & BIT_MASK_TA1_H_V1)
+#define BIT_SET_TA1_H_V1(x, v) (BIT_CLEAR_TA1_H_V1(x) | BIT_TA1_H_V1(v))
-/* 2 REG_TRANSMIT_ADDRSS_2 (Offset 0x16B0) */
+#define BIT_SHIFT_TA2_V1 0
+#define BIT_MASK_TA2_V1 0xffffffffL
+#define BIT_TA2_V1(x) (((x) & BIT_MASK_TA2_V1) << BIT_SHIFT_TA2_V1)
+#define BITS_TA2_V1 (BIT_MASK_TA2_V1 << BIT_SHIFT_TA2_V1)
+#define BIT_CLEAR_TA2_V1(x) ((x) & (~BITS_TA2_V1))
+#define BIT_GET_TA2_V1(x) (((x) >> BIT_SHIFT_TA2_V1) & BIT_MASK_TA2_V1)
+#define BIT_SET_TA2_V1(x, v) (BIT_CLEAR_TA2_V1(x) | BIT_TA2_V1(v))
+
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_TA2 0
-#define BIT_MASK_TA2 0xffffffffffffL
-#define BIT_TA2(x) (((x) & BIT_MASK_TA2) << BIT_SHIFT_TA2)
-#define BIT_GET_TA2(x) (((x) >> BIT_SHIFT_TA2) & BIT_MASK_TA2)
+/* 2 REG_TRANSMIT_ADDRSS_2 (Offset 0x16B0) */
+#define BIT_SHIFT_TA2 0
+#define BIT_MASK_TA2 0xffffffffffffL
+#define BIT_TA2(x) (((x) & BIT_MASK_TA2) << BIT_SHIFT_TA2)
+#define BITS_TA2 (BIT_MASK_TA2 << BIT_SHIFT_TA2)
+#define BIT_CLEAR_TA2(x) ((x) & (~BITS_TA2))
+#define BIT_GET_TA2(x) (((x) >> BIT_SHIFT_TA2) & BIT_MASK_TA2)
+#define BIT_SET_TA2(x, v) (BIT_CLEAR_TA2(x) | BIT_TA2(v))
-/* 2 REG_TRANSMIT_ADDRSS_3 (Offset 0x16B8) */
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_TA3 0
-#define BIT_MASK_TA3 0xffffffffffffL
-#define BIT_TA3(x) (((x) & BIT_MASK_TA3) << BIT_SHIFT_TA3)
-#define BIT_GET_TA3(x) (((x) >> BIT_SHIFT_TA3) & BIT_MASK_TA3)
+/* 2 REG_TRANSMIT_ADDRSS_2_H (Offset 0x16B4) */
+#define BIT_SHIFT_TA2_H_V1 0
+#define BIT_MASK_TA2_H_V1 0xffff
+#define BIT_TA2_H_V1(x) (((x) & BIT_MASK_TA2_H_V1) << BIT_SHIFT_TA2_H_V1)
+#define BITS_TA2_H_V1 (BIT_MASK_TA2_H_V1 << BIT_SHIFT_TA2_H_V1)
+#define BIT_CLEAR_TA2_H_V1(x) ((x) & (~BITS_TA2_H_V1))
+#define BIT_GET_TA2_H_V1(x) (((x) >> BIT_SHIFT_TA2_H_V1) & BIT_MASK_TA2_H_V1)
+#define BIT_SET_TA2_H_V1(x, v) (BIT_CLEAR_TA2_H_V1(x) | BIT_TA2_H_V1(v))
-/* 2 REG_TRANSMIT_ADDRSS_4 (Offset 0x16C0) */
+#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_TA4 0
-#define BIT_MASK_TA4 0xffffffffffffL
-#define BIT_TA4(x) (((x) & BIT_MASK_TA4) << BIT_SHIFT_TA4)
-#define BIT_GET_TA4(x) (((x) >> BIT_SHIFT_TA4) & BIT_MASK_TA4)
+/* 2 REG_TRANSMIT_ADDRSS_3 (Offset 0x16B8) */
+#define BIT_SHIFT_TA3 0
+#define BIT_MASK_TA3 0xffffffffffffL
+#define BIT_TA3(x) (((x) & BIT_MASK_TA3) << BIT_SHIFT_TA3)
+#define BITS_TA3 (BIT_MASK_TA3 << BIT_SHIFT_TA3)
+#define BIT_CLEAR_TA3(x) ((x) & (~BITS_TA3))
+#define BIT_GET_TA3(x) (((x) >> BIT_SHIFT_TA3) & BIT_MASK_TA3)
+#define BIT_SET_TA3(x, v) (BIT_CLEAR_TA3(x) | BIT_TA3(v))
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+/* 2 REG_TRANSMIT_ADDRSS_3_H (Offset 0x16BC) */
+#define BIT_SHIFT_TA3_H_V1 0
+#define BIT_MASK_TA3_H_V1 0xffff
+#define BIT_TA3_H_V1(x) (((x) & BIT_MASK_TA3_H_V1) << BIT_SHIFT_TA3_H_V1)
+#define BITS_TA3_H_V1 (BIT_MASK_TA3_H_V1 << BIT_SHIFT_TA3_H_V1)
+#define BIT_CLEAR_TA3_H_V1(x) ((x) & (~BITS_TA3_H_V1))
+#define BIT_GET_TA3_H_V1(x) (((x) >> BIT_SHIFT_TA3_H_V1) & BIT_MASK_TA3_H_V1)
+#define BIT_SET_TA3_H_V1(x, v) (BIT_CLEAR_TA3_H_V1(x) | BIT_TA3_H_V1(v))
-/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 (Offset 0x1700) */
+#endif
-#define BIT_LTECOEX_ACCESS_START_V1 BIT(31)
-#define BIT_LTECOEX_WRITE_MODE_V1 BIT(30)
-#define BIT_LTECOEX_READY_BIT_V1 BIT(29)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
-#define BIT_SHIFT_WRITE_BYTE_EN_V1 16
-#define BIT_MASK_WRITE_BYTE_EN_V1 0xf
-#define BIT_WRITE_BYTE_EN_V1(x) (((x) & BIT_MASK_WRITE_BYTE_EN_V1) << BIT_SHIFT_WRITE_BYTE_EN_V1)
-#define BIT_GET_WRITE_BYTE_EN_V1(x) (((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1) & BIT_MASK_WRITE_BYTE_EN_V1)
+/* 2 REG_TRANSMIT_ADDRSS_4 (Offset 0x16C0) */
+#define BIT_R_WMAC_RX_SYNCFIFO_SYNC BIT(55)
+#define BIT_R_WMAC_RXRST_DLY BIT(54)
+#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP BIT(53)
+#define BIT_R_WMAC_SRCH_TXRPT_UA1 BIT(52)
-#define BIT_SHIFT_LTECOEX_REG_ADDR_V1 0
-#define BIT_MASK_LTECOEX_REG_ADDR_V1 0xffff
-#define BIT_LTECOEX_REG_ADDR_V1(x) (((x) & BIT_MASK_LTECOEX_REG_ADDR_V1) << BIT_SHIFT_LTECOEX_REG_ADDR_V1)
-#define BIT_GET_LTECOEX_REG_ADDR_V1(x) (((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1) & BIT_MASK_LTECOEX_REG_ADDR_V1)
+#define BIT_SHIFT_TA4 0
+#define BIT_MASK_TA4 0xffffffffffffL
+#define BIT_TA4(x) (((x) & BIT_MASK_TA4) << BIT_SHIFT_TA4)
+#define BITS_TA4 (BIT_MASK_TA4 << BIT_SHIFT_TA4)
+#define BIT_CLEAR_TA4(x) ((x) & (~BITS_TA4))
+#define BIT_GET_TA4(x) (((x) >> BIT_SHIFT_TA4) & BIT_MASK_TA4)
+#define BIT_SET_TA4(x, v) (BIT_CLEAR_TA4(x) | BIT_TA4(v))
+#endif
-/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 (Offset 0x1704) */
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+/* 2 REG_TRANSMIT_ADDRSS_4 (Offset 0x16C0) */
-#define BIT_SHIFT_LTECOEX_W_DATA_V1 0
-#define BIT_MASK_LTECOEX_W_DATA_V1 0xffffffffL
-#define BIT_LTECOEX_W_DATA_V1(x) (((x) & BIT_MASK_LTECOEX_W_DATA_V1) << BIT_SHIFT_LTECOEX_W_DATA_V1)
-#define BIT_GET_LTECOEX_W_DATA_V1(x) (((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1) & BIT_MASK_LTECOEX_W_DATA_V1)
+#define BIT_SHIFT_TA4_V1 0
+#define BIT_MASK_TA4_V1 0xffffffffL
+#define BIT_TA4_V1(x) (((x) & BIT_MASK_TA4_V1) << BIT_SHIFT_TA4_V1)
+#define BITS_TA4_V1 (BIT_MASK_TA4_V1 << BIT_SHIFT_TA4_V1)
+#define BIT_CLEAR_TA4_V1(x) ((x) & (~BITS_TA4_V1))
+#define BIT_GET_TA4_V1(x) (((x) >> BIT_SHIFT_TA4_V1) & BIT_MASK_TA4_V1)
+#define BIT_SET_TA4_V1(x, v) (BIT_CLEAR_TA4_V1(x) | BIT_TA4_V1(v))
+/* 2 REG_TRANSMIT_ADDRSS_4_H (Offset 0x16C4) */
-/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 (Offset 0x1708) */
+#define BIT_SHIFT_TA4_H_V1 0
+#define BIT_MASK_TA4_H_V1 0xffff
+#define BIT_TA4_H_V1(x) (((x) & BIT_MASK_TA4_H_V1) << BIT_SHIFT_TA4_H_V1)
+#define BITS_TA4_H_V1 (BIT_MASK_TA4_H_V1 << BIT_SHIFT_TA4_H_V1)
+#define BIT_CLEAR_TA4_H_V1(x) ((x) & (~BITS_TA4_H_V1))
+#define BIT_GET_TA4_H_V1(x) (((x) >> BIT_SHIFT_TA4_H_V1) & BIT_MASK_TA4_H_V1)
+#define BIT_SET_TA4_H_V1(x, v) (BIT_CLEAR_TA4_H_V1(x) | BIT_TA4_H_V1(v))
+
+#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define BIT_SHIFT_LTECOEX_R_DATA_V1 0
-#define BIT_MASK_LTECOEX_R_DATA_V1 0xffffffffL
-#define BIT_LTECOEX_R_DATA_V1(x) (((x) & BIT_MASK_LTECOEX_R_DATA_V1) << BIT_SHIFT_LTECOEX_R_DATA_V1)
-#define BIT_GET_LTECOEX_R_DATA_V1(x) (((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1) & BIT_MASK_LTECOEX_R_DATA_V1)
+/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 (Offset 0x1700) */
+#define BIT_LTECOEX_ACCESS_START_V1 BIT(31)
+#define BIT_LTECOEX_WRITE_MODE_V1 BIT(30)
+#define BIT_LTECOEX_READY_BIT_V1 BIT(29)
+
+#define BIT_SHIFT_WRITE_BYTE_EN_V1 16
+#define BIT_MASK_WRITE_BYTE_EN_V1 0xf
+#define BIT_WRITE_BYTE_EN_V1(x) \
+ (((x) & BIT_MASK_WRITE_BYTE_EN_V1) << BIT_SHIFT_WRITE_BYTE_EN_V1)
+#define BITS_WRITE_BYTE_EN_V1 \
+ (BIT_MASK_WRITE_BYTE_EN_V1 << BIT_SHIFT_WRITE_BYTE_EN_V1)
+#define BIT_CLEAR_WRITE_BYTE_EN_V1(x) ((x) & (~BITS_WRITE_BYTE_EN_V1))
+#define BIT_GET_WRITE_BYTE_EN_V1(x) \
+ (((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1) & BIT_MASK_WRITE_BYTE_EN_V1)
+#define BIT_SET_WRITE_BYTE_EN_V1(x, v) \
+ (BIT_CLEAR_WRITE_BYTE_EN_V1(x) | BIT_WRITE_BYTE_EN_V1(v))
+
+#define BIT_SHIFT_LTECOEX_REG_ADDR_V1 0
+#define BIT_MASK_LTECOEX_REG_ADDR_V1 0xffff
+#define BIT_LTECOEX_REG_ADDR_V1(x) \
+ (((x) & BIT_MASK_LTECOEX_REG_ADDR_V1) << BIT_SHIFT_LTECOEX_REG_ADDR_V1)
+#define BITS_LTECOEX_REG_ADDR_V1 \
+ (BIT_MASK_LTECOEX_REG_ADDR_V1 << BIT_SHIFT_LTECOEX_REG_ADDR_V1)
+#define BIT_CLEAR_LTECOEX_REG_ADDR_V1(x) ((x) & (~BITS_LTECOEX_REG_ADDR_V1))
+#define BIT_GET_LTECOEX_REG_ADDR_V1(x) \
+ (((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1) & BIT_MASK_LTECOEX_REG_ADDR_V1)
+#define BIT_SET_LTECOEX_REG_ADDR_V1(x, v) \
+ (BIT_CLEAR_LTECOEX_REG_ADDR_V1(x) | BIT_LTECOEX_REG_ADDR_V1(v))
-#endif
+/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 (Offset 0x1704) */
+#define BIT_SHIFT_LTECOEX_W_DATA_V1 0
+#define BIT_MASK_LTECOEX_W_DATA_V1 0xffffffffL
+#define BIT_LTECOEX_W_DATA_V1(x) \
+ (((x) & BIT_MASK_LTECOEX_W_DATA_V1) << BIT_SHIFT_LTECOEX_W_DATA_V1)
+#define BITS_LTECOEX_W_DATA_V1 \
+ (BIT_MASK_LTECOEX_W_DATA_V1 << BIT_SHIFT_LTECOEX_W_DATA_V1)
+#define BIT_CLEAR_LTECOEX_W_DATA_V1(x) ((x) & (~BITS_LTECOEX_W_DATA_V1))
+#define BIT_GET_LTECOEX_W_DATA_V1(x) \
+ (((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1) & BIT_MASK_LTECOEX_W_DATA_V1)
+#define BIT_SET_LTECOEX_W_DATA_V1(x, v) \
+ (BIT_CLEAR_LTECOEX_W_DATA_V1(x) | BIT_LTECOEX_W_DATA_V1(v))
+/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 (Offset 0x1708) */
-#endif/* __RTL_WLAN_BITDEF_H__ */
+#define BIT_SHIFT_LTECOEX_R_DATA_V1 0
+#define BIT_MASK_LTECOEX_R_DATA_V1 0xffffffffL
+#define BIT_LTECOEX_R_DATA_V1(x) \
+ (((x) & BIT_MASK_LTECOEX_R_DATA_V1) << BIT_SHIFT_LTECOEX_R_DATA_V1)
+#define BITS_LTECOEX_R_DATA_V1 \
+ (BIT_MASK_LTECOEX_R_DATA_V1 << BIT_SHIFT_LTECOEX_R_DATA_V1)
+#define BIT_CLEAR_LTECOEX_R_DATA_V1(x) ((x) & (~BITS_LTECOEX_R_DATA_V1))
+#define BIT_GET_LTECOEX_R_DATA_V1(x) \
+ (((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1) & BIT_MASK_LTECOEX_R_DATA_V1)
+#define BIT_SET_LTECOEX_R_DATA_V1(x, v) \
+ (BIT_CLEAR_LTECOEX_R_DATA_V1(x) | BIT_LTECOEX_R_DATA_V1(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_DMA_RQPN_INFO_0 (Offset 0x2200) */
+
+#define BIT_SHIFT_CH0_AVAL_PG 16
+#define BIT_MASK_CH0_AVAL_PG 0xfff
+#define BIT_CH0_AVAL_PG(x) \
+ (((x) & BIT_MASK_CH0_AVAL_PG) << BIT_SHIFT_CH0_AVAL_PG)
+#define BITS_CH0_AVAL_PG (BIT_MASK_CH0_AVAL_PG << BIT_SHIFT_CH0_AVAL_PG)
+#define BIT_CLEAR_CH0_AVAL_PG(x) ((x) & (~BITS_CH0_AVAL_PG))
+#define BIT_GET_CH0_AVAL_PG(x) \
+ (((x) >> BIT_SHIFT_CH0_AVAL_PG) & BIT_MASK_CH0_AVAL_PG)
+#define BIT_SET_CH0_AVAL_PG(x, v) \
+ (BIT_CLEAR_CH0_AVAL_PG(x) | BIT_CH0_AVAL_PG(v))
+
+#define BIT_SHIFT_CH0_RSVD_PG 0
+#define BIT_MASK_CH0_RSVD_PG 0xfff
+#define BIT_CH0_RSVD_PG(x) \
+ (((x) & BIT_MASK_CH0_RSVD_PG) << BIT_SHIFT_CH0_RSVD_PG)
+#define BITS_CH0_RSVD_PG (BIT_MASK_CH0_RSVD_PG << BIT_SHIFT_CH0_RSVD_PG)
+#define BIT_CLEAR_CH0_RSVD_PG(x) ((x) & (~BITS_CH0_RSVD_PG))
+#define BIT_GET_CH0_RSVD_PG(x) \
+ (((x) >> BIT_SHIFT_CH0_RSVD_PG) & BIT_MASK_CH0_RSVD_PG)
+#define BIT_SET_CH0_RSVD_PG(x, v) \
+ (BIT_CLEAR_CH0_RSVD_PG(x) | BIT_CH0_RSVD_PG(v))
+
+/* 2 REG_DMA_RQPN_INFO_1 (Offset 0x2204) */
+
+#define BIT_SHIFT_CH1_AVAL_PG 16
+#define BIT_MASK_CH1_AVAL_PG 0xfff
+#define BIT_CH1_AVAL_PG(x) \
+ (((x) & BIT_MASK_CH1_AVAL_PG) << BIT_SHIFT_CH1_AVAL_PG)
+#define BITS_CH1_AVAL_PG (BIT_MASK_CH1_AVAL_PG << BIT_SHIFT_CH1_AVAL_PG)
+#define BIT_CLEAR_CH1_AVAL_PG(x) ((x) & (~BITS_CH1_AVAL_PG))
+#define BIT_GET_CH1_AVAL_PG(x) \
+ (((x) >> BIT_SHIFT_CH1_AVAL_PG) & BIT_MASK_CH1_AVAL_PG)
+#define BIT_SET_CH1_AVAL_PG(x, v) \
+ (BIT_CLEAR_CH1_AVAL_PG(x) | BIT_CH1_AVAL_PG(v))
+
+#define BIT_SHIFT_CH1_RSVD_PG 0
+#define BIT_MASK_CH1_RSVD_PG 0xfff
+#define BIT_CH1_RSVD_PG(x) \
+ (((x) & BIT_MASK_CH1_RSVD_PG) << BIT_SHIFT_CH1_RSVD_PG)
+#define BITS_CH1_RSVD_PG (BIT_MASK_CH1_RSVD_PG << BIT_SHIFT_CH1_RSVD_PG)
+#define BIT_CLEAR_CH1_RSVD_PG(x) ((x) & (~BITS_CH1_RSVD_PG))
+#define BIT_GET_CH1_RSVD_PG(x) \
+ (((x) >> BIT_SHIFT_CH1_RSVD_PG) & BIT_MASK_CH1_RSVD_PG)
+#define BIT_SET_CH1_RSVD_PG(x, v) \
+ (BIT_CLEAR_CH1_RSVD_PG(x) | BIT_CH1_RSVD_PG(v))
+
+/* 2 REG_DMA_RQPN_INFO_2 (Offset 0x2208) */
+
+#define BIT_SHIFT_CH2_AVAL_PG 16
+#define BIT_MASK_CH2_AVAL_PG 0xfff
+#define BIT_CH2_AVAL_PG(x) \
+ (((x) & BIT_MASK_CH2_AVAL_PG) << BIT_SHIFT_CH2_AVAL_PG)
+#define BITS_CH2_AVAL_PG (BIT_MASK_CH2_AVAL_PG << BIT_SHIFT_CH2_AVAL_PG)
+#define BIT_CLEAR_CH2_AVAL_PG(x) ((x) & (~BITS_CH2_AVAL_PG))
+#define BIT_GET_CH2_AVAL_PG(x) \
+ (((x) >> BIT_SHIFT_CH2_AVAL_PG) & BIT_MASK_CH2_AVAL_PG)
+#define BIT_SET_CH2_AVAL_PG(x, v) \
+ (BIT_CLEAR_CH2_AVAL_PG(x) | BIT_CH2_AVAL_PG(v))
+
+#define BIT_SHIFT_CH2_RSVD_PG 0
+#define BIT_MASK_CH2_RSVD_PG 0xfff
+#define BIT_CH2_RSVD_PG(x) \
+ (((x) & BIT_MASK_CH2_RSVD_PG) << BIT_SHIFT_CH2_RSVD_PG)
+#define BITS_CH2_RSVD_PG (BIT_MASK_CH2_RSVD_PG << BIT_SHIFT_CH2_RSVD_PG)
+#define BIT_CLEAR_CH2_RSVD_PG(x) ((x) & (~BITS_CH2_RSVD_PG))
+#define BIT_GET_CH2_RSVD_PG(x) \
+ (((x) >> BIT_SHIFT_CH2_RSVD_PG) & BIT_MASK_CH2_RSVD_PG)
+#define BIT_SET_CH2_RSVD_PG(x, v) \
+ (BIT_CLEAR_CH2_RSVD_PG(x) | BIT_CH2_RSVD_PG(v))
+
+/* 2 REG_DMA_RQPN_INFO_3 (Offset 0x220C) */
+
+#define BIT_SHIFT_CH3_AVAL_PG 16
+#define BIT_MASK_CH3_AVAL_PG 0xfff
+#define BIT_CH3_AVAL_PG(x) \
+ (((x) & BIT_MASK_CH3_AVAL_PG) << BIT_SHIFT_CH3_AVAL_PG)
+#define BITS_CH3_AVAL_PG (BIT_MASK_CH3_AVAL_PG << BIT_SHIFT_CH3_AVAL_PG)
+#define BIT_CLEAR_CH3_AVAL_PG(x) ((x) & (~BITS_CH3_AVAL_PG))
+#define BIT_GET_CH3_AVAL_PG(x) \
+ (((x) >> BIT_SHIFT_CH3_AVAL_PG) & BIT_MASK_CH3_AVAL_PG)
+#define BIT_SET_CH3_AVAL_PG(x, v) \
+ (BIT_CLEAR_CH3_AVAL_PG(x) | BIT_CH3_AVAL_PG(v))
+
+#define BIT_SHIFT_CH3_RSVD_PG 0
+#define BIT_MASK_CH3_RSVD_PG 0xfff
+#define BIT_CH3_RSVD_PG(x) \
+ (((x) & BIT_MASK_CH3_RSVD_PG) << BIT_SHIFT_CH3_RSVD_PG)
+#define BITS_CH3_RSVD_PG (BIT_MASK_CH3_RSVD_PG << BIT_SHIFT_CH3_RSVD_PG)
+#define BIT_CLEAR_CH3_RSVD_PG(x) ((x) & (~BITS_CH3_RSVD_PG))
+#define BIT_GET_CH3_RSVD_PG(x) \
+ (((x) >> BIT_SHIFT_CH3_RSVD_PG) & BIT_MASK_CH3_RSVD_PG)
+#define BIT_SET_CH3_RSVD_PG(x, v) \
+ (BIT_CLEAR_CH3_RSVD_PG(x) | BIT_CH3_RSVD_PG(v))
+
+/* 2 REG_DMA_RQPN_INFO_4 (Offset 0x2210) */
+
+#define BIT_SHIFT_CH4_AVAL_PG 16
+#define BIT_MASK_CH4_AVAL_PG 0xfff
+#define BIT_CH4_AVAL_PG(x) \
+ (((x) & BIT_MASK_CH4_AVAL_PG) << BIT_SHIFT_CH4_AVAL_PG)
+#define BITS_CH4_AVAL_PG (BIT_MASK_CH4_AVAL_PG << BIT_SHIFT_CH4_AVAL_PG)
+#define BIT_CLEAR_CH4_AVAL_PG(x) ((x) & (~BITS_CH4_AVAL_PG))
+#define BIT_GET_CH4_AVAL_PG(x) \
+ (((x) >> BIT_SHIFT_CH4_AVAL_PG) & BIT_MASK_CH4_AVAL_PG)
+#define BIT_SET_CH4_AVAL_PG(x, v) \
+ (BIT_CLEAR_CH4_AVAL_PG(x) | BIT_CH4_AVAL_PG(v))
+
+#define BIT_SHIFT_CH4_RSVD_PG 0
+#define BIT_MASK_CH4_RSVD_PG 0xfff
+#define BIT_CH4_RSVD_PG(x) \
+ (((x) & BIT_MASK_CH4_RSVD_PG) << BIT_SHIFT_CH4_RSVD_PG)
+#define BITS_CH4_RSVD_PG (BIT_MASK_CH4_RSVD_PG << BIT_SHIFT_CH4_RSVD_PG)
+#define BIT_CLEAR_CH4_RSVD_PG(x) ((x) & (~BITS_CH4_RSVD_PG))
+#define BIT_GET_CH4_RSVD_PG(x) \
+ (((x) >> BIT_SHIFT_CH4_RSVD_PG) & BIT_MASK_CH4_RSVD_PG)
+#define BIT_SET_CH4_RSVD_PG(x, v) \
+ (BIT_CLEAR_CH4_RSVD_PG(x) | BIT_CH4_RSVD_PG(v))
+
+/* 2 REG_DMA_RQPN_INFO_5 (Offset 0x2214) */
+
+#define BIT_SHIFT_CH5_AVAL_PG 16
+#define BIT_MASK_CH5_AVAL_PG 0xfff
+#define BIT_CH5_AVAL_PG(x) \
+ (((x) & BIT_MASK_CH5_AVAL_PG) << BIT_SHIFT_CH5_AVAL_PG)
+#define BITS_CH5_AVAL_PG (BIT_MASK_CH5_AVAL_PG << BIT_SHIFT_CH5_AVAL_PG)
+#define BIT_CLEAR_CH5_AVAL_PG(x) ((x) & (~BITS_CH5_AVAL_PG))
+#define BIT_GET_CH5_AVAL_PG(x) \
+ (((x) >> BIT_SHIFT_CH5_AVAL_PG) & BIT_MASK_CH5_AVAL_PG)
+#define BIT_SET_CH5_AVAL_PG(x, v) \
+ (BIT_CLEAR_CH5_AVAL_PG(x) | BIT_CH5_AVAL_PG(v))
+
+#define BIT_SHIFT_CH5_RSVD_PG 0
+#define BIT_MASK_CH5_RSVD_PG 0xfff
+#define BIT_CH5_RSVD_PG(x) \
+ (((x) & BIT_MASK_CH5_RSVD_PG) << BIT_SHIFT_CH5_RSVD_PG)
+#define BITS_CH5_RSVD_PG (BIT_MASK_CH5_RSVD_PG << BIT_SHIFT_CH5_RSVD_PG)
+#define BIT_CLEAR_CH5_RSVD_PG(x) ((x) & (~BITS_CH5_RSVD_PG))
+#define BIT_GET_CH5_RSVD_PG(x) \
+ (((x) >> BIT_SHIFT_CH5_RSVD_PG) & BIT_MASK_CH5_RSVD_PG)
+#define BIT_SET_CH5_RSVD_PG(x, v) \
+ (BIT_CLEAR_CH5_RSVD_PG(x) | BIT_CH5_RSVD_PG(v))
+
+/* 2 REG_DMA_RQPN_INFO_6 (Offset 0x2218) */
+
+#define BIT_SHIFT_CH6_AVAL_PG 16
+#define BIT_MASK_CH6_AVAL_PG 0xfff
+#define BIT_CH6_AVAL_PG(x) \
+ (((x) & BIT_MASK_CH6_AVAL_PG) << BIT_SHIFT_CH6_AVAL_PG)
+#define BITS_CH6_AVAL_PG (BIT_MASK_CH6_AVAL_PG << BIT_SHIFT_CH6_AVAL_PG)
+#define BIT_CLEAR_CH6_AVAL_PG(x) ((x) & (~BITS_CH6_AVAL_PG))
+#define BIT_GET_CH6_AVAL_PG(x) \
+ (((x) >> BIT_SHIFT_CH6_AVAL_PG) & BIT_MASK_CH6_AVAL_PG)
+#define BIT_SET_CH6_AVAL_PG(x, v) \
+ (BIT_CLEAR_CH6_AVAL_PG(x) | BIT_CH6_AVAL_PG(v))
+
+#define BIT_SHIFT_CH6_RSVD_PG 0
+#define BIT_MASK_CH6_RSVD_PG 0xfff
+#define BIT_CH6_RSVD_PG(x) \
+ (((x) & BIT_MASK_CH6_RSVD_PG) << BIT_SHIFT_CH6_RSVD_PG)
+#define BITS_CH6_RSVD_PG (BIT_MASK_CH6_RSVD_PG << BIT_SHIFT_CH6_RSVD_PG)
+#define BIT_CLEAR_CH6_RSVD_PG(x) ((x) & (~BITS_CH6_RSVD_PG))
+#define BIT_GET_CH6_RSVD_PG(x) \
+ (((x) >> BIT_SHIFT_CH6_RSVD_PG) & BIT_MASK_CH6_RSVD_PG)
+#define BIT_SET_CH6_RSVD_PG(x, v) \
+ (BIT_CLEAR_CH6_RSVD_PG(x) | BIT_CH6_RSVD_PG(v))
+
+/* 2 REG_DMA_RQPN_INFO_7 (Offset 0x221C) */
+
+#define BIT_SHIFT_CH7_AVAL_PG 16
+#define BIT_MASK_CH7_AVAL_PG 0xfff
+#define BIT_CH7_AVAL_PG(x) \
+ (((x) & BIT_MASK_CH7_AVAL_PG) << BIT_SHIFT_CH7_AVAL_PG)
+#define BITS_CH7_AVAL_PG (BIT_MASK_CH7_AVAL_PG << BIT_SHIFT_CH7_AVAL_PG)
+#define BIT_CLEAR_CH7_AVAL_PG(x) ((x) & (~BITS_CH7_AVAL_PG))
+#define BIT_GET_CH7_AVAL_PG(x) \
+ (((x) >> BIT_SHIFT_CH7_AVAL_PG) & BIT_MASK_CH7_AVAL_PG)
+#define BIT_SET_CH7_AVAL_PG(x, v) \
+ (BIT_CLEAR_CH7_AVAL_PG(x) | BIT_CH7_AVAL_PG(v))
+
+#define BIT_SHIFT_CH7_RSVD_PG 0
+#define BIT_MASK_CH7_RSVD_PG 0xfff
+#define BIT_CH7_RSVD_PG(x) \
+ (((x) & BIT_MASK_CH7_RSVD_PG) << BIT_SHIFT_CH7_RSVD_PG)
+#define BITS_CH7_RSVD_PG (BIT_MASK_CH7_RSVD_PG << BIT_SHIFT_CH7_RSVD_PG)
+#define BIT_CLEAR_CH7_RSVD_PG(x) ((x) & (~BITS_CH7_RSVD_PG))
+#define BIT_GET_CH7_RSVD_PG(x) \
+ (((x) >> BIT_SHIFT_CH7_RSVD_PG) & BIT_MASK_CH7_RSVD_PG)
+#define BIT_SET_CH7_RSVD_PG(x, v) \
+ (BIT_CLEAR_CH7_RSVD_PG(x) | BIT_CH7_RSVD_PG(v))
+
+/* 2 REG_DMA_RQPN_INFO_8 (Offset 0x2220) */
+
+#define BIT_SHIFT_CH8_AVAL_PG 16
+#define BIT_MASK_CH8_AVAL_PG 0xfff
+#define BIT_CH8_AVAL_PG(x) \
+ (((x) & BIT_MASK_CH8_AVAL_PG) << BIT_SHIFT_CH8_AVAL_PG)
+#define BITS_CH8_AVAL_PG (BIT_MASK_CH8_AVAL_PG << BIT_SHIFT_CH8_AVAL_PG)
+#define BIT_CLEAR_CH8_AVAL_PG(x) ((x) & (~BITS_CH8_AVAL_PG))
+#define BIT_GET_CH8_AVAL_PG(x) \
+ (((x) >> BIT_SHIFT_CH8_AVAL_PG) & BIT_MASK_CH8_AVAL_PG)
+#define BIT_SET_CH8_AVAL_PG(x, v) \
+ (BIT_CLEAR_CH8_AVAL_PG(x) | BIT_CH8_AVAL_PG(v))
+
+#define BIT_SHIFT_CH8_RSVD_PG 0
+#define BIT_MASK_CH8_RSVD_PG 0xfff
+#define BIT_CH8_RSVD_PG(x) \
+ (((x) & BIT_MASK_CH8_RSVD_PG) << BIT_SHIFT_CH8_RSVD_PG)
+#define BITS_CH8_RSVD_PG (BIT_MASK_CH8_RSVD_PG << BIT_SHIFT_CH8_RSVD_PG)
+#define BIT_CLEAR_CH8_RSVD_PG(x) ((x) & (~BITS_CH8_RSVD_PG))
+#define BIT_GET_CH8_RSVD_PG(x) \
+ (((x) >> BIT_SHIFT_CH8_RSVD_PG) & BIT_MASK_CH8_RSVD_PG)
+#define BIT_SET_CH8_RSVD_PG(x, v) \
+ (BIT_CLEAR_CH8_RSVD_PG(x) | BIT_CH8_RSVD_PG(v))
+
+/* 2 REG_DMA_RQPN_INFO_9 (Offset 0x2224) */
+
+#define BIT_SHIFT_CH9_AVAL_PG 16
+#define BIT_MASK_CH9_AVAL_PG 0xfff
+#define BIT_CH9_AVAL_PG(x) \
+ (((x) & BIT_MASK_CH9_AVAL_PG) << BIT_SHIFT_CH9_AVAL_PG)
+#define BITS_CH9_AVAL_PG (BIT_MASK_CH9_AVAL_PG << BIT_SHIFT_CH9_AVAL_PG)
+#define BIT_CLEAR_CH9_AVAL_PG(x) ((x) & (~BITS_CH9_AVAL_PG))
+#define BIT_GET_CH9_AVAL_PG(x) \
+ (((x) >> BIT_SHIFT_CH9_AVAL_PG) & BIT_MASK_CH9_AVAL_PG)
+#define BIT_SET_CH9_AVAL_PG(x, v) \
+ (BIT_CLEAR_CH9_AVAL_PG(x) | BIT_CH9_AVAL_PG(v))
+
+#define BIT_SHIFT_CH9_RSVD_PG 0
+#define BIT_MASK_CH9_RSVD_PG 0xfff
+#define BIT_CH9_RSVD_PG(x) \
+ (((x) & BIT_MASK_CH9_RSVD_PG) << BIT_SHIFT_CH9_RSVD_PG)
+#define BITS_CH9_RSVD_PG (BIT_MASK_CH9_RSVD_PG << BIT_SHIFT_CH9_RSVD_PG)
+#define BIT_CLEAR_CH9_RSVD_PG(x) ((x) & (~BITS_CH9_RSVD_PG))
+#define BIT_GET_CH9_RSVD_PG(x) \
+ (((x) >> BIT_SHIFT_CH9_RSVD_PG) & BIT_MASK_CH9_RSVD_PG)
+#define BIT_SET_CH9_RSVD_PG(x, v) \
+ (BIT_CLEAR_CH9_RSVD_PG(x) | BIT_CH9_RSVD_PG(v))
+
+/* 2 REG_DMA_RQPN_INFO_10 (Offset 0x2228) */
+
+#define BIT_SHIFT_CH10_AVAL_PG 16
+#define BIT_MASK_CH10_AVAL_PG 0xfff
+#define BIT_CH10_AVAL_PG(x) \
+ (((x) & BIT_MASK_CH10_AVAL_PG) << BIT_SHIFT_CH10_AVAL_PG)
+#define BITS_CH10_AVAL_PG (BIT_MASK_CH10_AVAL_PG << BIT_SHIFT_CH10_AVAL_PG)
+#define BIT_CLEAR_CH10_AVAL_PG(x) ((x) & (~BITS_CH10_AVAL_PG))
+#define BIT_GET_CH10_AVAL_PG(x) \
+ (((x) >> BIT_SHIFT_CH10_AVAL_PG) & BIT_MASK_CH10_AVAL_PG)
+#define BIT_SET_CH10_AVAL_PG(x, v) \
+ (BIT_CLEAR_CH10_AVAL_PG(x) | BIT_CH10_AVAL_PG(v))
+
+#define BIT_SHIFT_CH10_RSVD_PG 0
+#define BIT_MASK_CH10_RSVD_PG 0xfff
+#define BIT_CH10_RSVD_PG(x) \
+ (((x) & BIT_MASK_CH10_RSVD_PG) << BIT_SHIFT_CH10_RSVD_PG)
+#define BITS_CH10_RSVD_PG (BIT_MASK_CH10_RSVD_PG << BIT_SHIFT_CH10_RSVD_PG)
+#define BIT_CLEAR_CH10_RSVD_PG(x) ((x) & (~BITS_CH10_RSVD_PG))
+#define BIT_GET_CH10_RSVD_PG(x) \
+ (((x) >> BIT_SHIFT_CH10_RSVD_PG) & BIT_MASK_CH10_RSVD_PG)
+#define BIT_SET_CH10_RSVD_PG(x, v) \
+ (BIT_CLEAR_CH10_RSVD_PG(x) | BIT_CH10_RSVD_PG(v))
+
+/* 2 REG_DMA_RQPN_INFO_11 (Offset 0x222C) */
+
+#define BIT_SHIFT_CH11_AVAL_PG 16
+#define BIT_MASK_CH11_AVAL_PG 0xfff
+#define BIT_CH11_AVAL_PG(x) \
+ (((x) & BIT_MASK_CH11_AVAL_PG) << BIT_SHIFT_CH11_AVAL_PG)
+#define BITS_CH11_AVAL_PG (BIT_MASK_CH11_AVAL_PG << BIT_SHIFT_CH11_AVAL_PG)
+#define BIT_CLEAR_CH11_AVAL_PG(x) ((x) & (~BITS_CH11_AVAL_PG))
+#define BIT_GET_CH11_AVAL_PG(x) \
+ (((x) >> BIT_SHIFT_CH11_AVAL_PG) & BIT_MASK_CH11_AVAL_PG)
+#define BIT_SET_CH11_AVAL_PG(x, v) \
+ (BIT_CLEAR_CH11_AVAL_PG(x) | BIT_CH11_AVAL_PG(v))
+
+#define BIT_SHIFT_CH11_RSVD_PG 0
+#define BIT_MASK_CH11_RSVD_PG 0xfff
+#define BIT_CH11_RSVD_PG(x) \
+ (((x) & BIT_MASK_CH11_RSVD_PG) << BIT_SHIFT_CH11_RSVD_PG)
+#define BITS_CH11_RSVD_PG (BIT_MASK_CH11_RSVD_PG << BIT_SHIFT_CH11_RSVD_PG)
+#define BIT_CLEAR_CH11_RSVD_PG(x) ((x) & (~BITS_CH11_RSVD_PG))
+#define BIT_GET_CH11_RSVD_PG(x) \
+ (((x) >> BIT_SHIFT_CH11_RSVD_PG) & BIT_MASK_CH11_RSVD_PG)
+#define BIT_SET_CH11_RSVD_PG(x, v) \
+ (BIT_CLEAR_CH11_RSVD_PG(x) | BIT_CH11_RSVD_PG(v))
+
+/* 2 REG_DMA_RQPN_INFO_12 (Offset 0x2230) */
+
+#define BIT_SHIFT_CH12_AVAL_PG 16
+#define BIT_MASK_CH12_AVAL_PG 0xfff
+#define BIT_CH12_AVAL_PG(x) \
+ (((x) & BIT_MASK_CH12_AVAL_PG) << BIT_SHIFT_CH12_AVAL_PG)
+#define BITS_CH12_AVAL_PG (BIT_MASK_CH12_AVAL_PG << BIT_SHIFT_CH12_AVAL_PG)
+#define BIT_CLEAR_CH12_AVAL_PG(x) ((x) & (~BITS_CH12_AVAL_PG))
+#define BIT_GET_CH12_AVAL_PG(x) \
+ (((x) >> BIT_SHIFT_CH12_AVAL_PG) & BIT_MASK_CH12_AVAL_PG)
+#define BIT_SET_CH12_AVAL_PG(x, v) \
+ (BIT_CLEAR_CH12_AVAL_PG(x) | BIT_CH12_AVAL_PG(v))
+
+#define BIT_SHIFT_CH12_RSVD_PG 0
+#define BIT_MASK_CH12_RSVD_PG 0xfff
+#define BIT_CH12_RSVD_PG(x) \
+ (((x) & BIT_MASK_CH12_RSVD_PG) << BIT_SHIFT_CH12_RSVD_PG)
+#define BITS_CH12_RSVD_PG (BIT_MASK_CH12_RSVD_PG << BIT_SHIFT_CH12_RSVD_PG)
+#define BIT_CLEAR_CH12_RSVD_PG(x) ((x) & (~BITS_CH12_RSVD_PG))
+#define BIT_GET_CH12_RSVD_PG(x) \
+ (((x) >> BIT_SHIFT_CH12_RSVD_PG) & BIT_MASK_CH12_RSVD_PG)
+#define BIT_SET_CH12_RSVD_PG(x, v) \
+ (BIT_CLEAR_CH12_RSVD_PG(x) | BIT_CH12_RSVD_PG(v))
+
+/* 2 REG_DMA_RQPN_INFO_13 (Offset 0x2234) */
+
+#define BIT_SHIFT_CH13_AVAL_PG 16
+#define BIT_MASK_CH13_AVAL_PG 0xfff
+#define BIT_CH13_AVAL_PG(x) \
+ (((x) & BIT_MASK_CH13_AVAL_PG) << BIT_SHIFT_CH13_AVAL_PG)
+#define BITS_CH13_AVAL_PG (BIT_MASK_CH13_AVAL_PG << BIT_SHIFT_CH13_AVAL_PG)
+#define BIT_CLEAR_CH13_AVAL_PG(x) ((x) & (~BITS_CH13_AVAL_PG))
+#define BIT_GET_CH13_AVAL_PG(x) \
+ (((x) >> BIT_SHIFT_CH13_AVAL_PG) & BIT_MASK_CH13_AVAL_PG)
+#define BIT_SET_CH13_AVAL_PG(x, v) \
+ (BIT_CLEAR_CH13_AVAL_PG(x) | BIT_CH13_AVAL_PG(v))
+
+#define BIT_SHIFT_CH13_RSVD_PG 0
+#define BIT_MASK_CH13_RSVD_PG 0xfff
+#define BIT_CH13_RSVD_PG(x) \
+ (((x) & BIT_MASK_CH13_RSVD_PG) << BIT_SHIFT_CH13_RSVD_PG)
+#define BITS_CH13_RSVD_PG (BIT_MASK_CH13_RSVD_PG << BIT_SHIFT_CH13_RSVD_PG)
+#define BIT_CLEAR_CH13_RSVD_PG(x) ((x) & (~BITS_CH13_RSVD_PG))
+#define BIT_GET_CH13_RSVD_PG(x) \
+ (((x) >> BIT_SHIFT_CH13_RSVD_PG) & BIT_MASK_CH13_RSVD_PG)
+#define BIT_SET_CH13_RSVD_PG(x, v) \
+ (BIT_CLEAR_CH13_RSVD_PG(x) | BIT_CH13_RSVD_PG(v))
+
+/* 2 REG_DMA_RQPN_INFO_14 (Offset 0x2238) */
+
+#define BIT_SHIFT_CH14_AVAL_PG 16
+#define BIT_MASK_CH14_AVAL_PG 0xfff
+#define BIT_CH14_AVAL_PG(x) \
+ (((x) & BIT_MASK_CH14_AVAL_PG) << BIT_SHIFT_CH14_AVAL_PG)
+#define BITS_CH14_AVAL_PG (BIT_MASK_CH14_AVAL_PG << BIT_SHIFT_CH14_AVAL_PG)
+#define BIT_CLEAR_CH14_AVAL_PG(x) ((x) & (~BITS_CH14_AVAL_PG))
+#define BIT_GET_CH14_AVAL_PG(x) \
+ (((x) >> BIT_SHIFT_CH14_AVAL_PG) & BIT_MASK_CH14_AVAL_PG)
+#define BIT_SET_CH14_AVAL_PG(x, v) \
+ (BIT_CLEAR_CH14_AVAL_PG(x) | BIT_CH14_AVAL_PG(v))
+
+#define BIT_SHIFT_CH14_RSVD_PG 0
+#define BIT_MASK_CH14_RSVD_PG 0xfff
+#define BIT_CH14_RSVD_PG(x) \
+ (((x) & BIT_MASK_CH14_RSVD_PG) << BIT_SHIFT_CH14_RSVD_PG)
+#define BITS_CH14_RSVD_PG (BIT_MASK_CH14_RSVD_PG << BIT_SHIFT_CH14_RSVD_PG)
+#define BIT_CLEAR_CH14_RSVD_PG(x) ((x) & (~BITS_CH14_RSVD_PG))
+#define BIT_GET_CH14_RSVD_PG(x) \
+ (((x) >> BIT_SHIFT_CH14_RSVD_PG) & BIT_MASK_CH14_RSVD_PG)
+#define BIT_SET_CH14_RSVD_PG(x, v) \
+ (BIT_CLEAR_CH14_RSVD_PG(x) | BIT_CH14_RSVD_PG(v))
+
+/* 2 REG_DMA_RQPN_INFO_15 (Offset 0x223C) */
+
+#define BIT_SHIFT_CH15_AVAL_PG 16
+#define BIT_MASK_CH15_AVAL_PG 0xfff
+#define BIT_CH15_AVAL_PG(x) \
+ (((x) & BIT_MASK_CH15_AVAL_PG) << BIT_SHIFT_CH15_AVAL_PG)
+#define BITS_CH15_AVAL_PG (BIT_MASK_CH15_AVAL_PG << BIT_SHIFT_CH15_AVAL_PG)
+#define BIT_CLEAR_CH15_AVAL_PG(x) ((x) & (~BITS_CH15_AVAL_PG))
+#define BIT_GET_CH15_AVAL_PG(x) \
+ (((x) >> BIT_SHIFT_CH15_AVAL_PG) & BIT_MASK_CH15_AVAL_PG)
+#define BIT_SET_CH15_AVAL_PG(x, v) \
+ (BIT_CLEAR_CH15_AVAL_PG(x) | BIT_CH15_AVAL_PG(v))
+
+#define BIT_SHIFT_CH15_RSVD_PG 0
+#define BIT_MASK_CH15_RSVD_PG 0xfff
+#define BIT_CH15_RSVD_PG(x) \
+ (((x) & BIT_MASK_CH15_RSVD_PG) << BIT_SHIFT_CH15_RSVD_PG)
+#define BITS_CH15_RSVD_PG (BIT_MASK_CH15_RSVD_PG << BIT_SHIFT_CH15_RSVD_PG)
+#define BIT_CLEAR_CH15_RSVD_PG(x) ((x) & (~BITS_CH15_RSVD_PG))
+#define BIT_GET_CH15_RSVD_PG(x) \
+ (((x) >> BIT_SHIFT_CH15_RSVD_PG) & BIT_MASK_CH15_RSVD_PG)
+#define BIT_SET_CH15_RSVD_PG(x, v) \
+ (BIT_CLEAR_CH15_RSVD_PG(x) | BIT_CH15_RSVD_PG(v))
+
+/* 2 REG_DMA_RQPN_INFO_16 (Offset 0x2240) */
+
+#define BIT_SHIFT_CH16_AVAL_PG 16
+#define BIT_MASK_CH16_AVAL_PG 0xfff
+#define BIT_CH16_AVAL_PG(x) \
+ (((x) & BIT_MASK_CH16_AVAL_PG) << BIT_SHIFT_CH16_AVAL_PG)
+#define BITS_CH16_AVAL_PG (BIT_MASK_CH16_AVAL_PG << BIT_SHIFT_CH16_AVAL_PG)
+#define BIT_CLEAR_CH16_AVAL_PG(x) ((x) & (~BITS_CH16_AVAL_PG))
+#define BIT_GET_CH16_AVAL_PG(x) \
+ (((x) >> BIT_SHIFT_CH16_AVAL_PG) & BIT_MASK_CH16_AVAL_PG)
+#define BIT_SET_CH16_AVAL_PG(x, v) \
+ (BIT_CLEAR_CH16_AVAL_PG(x) | BIT_CH16_AVAL_PG(v))
+
+#define BIT_SHIFT_CH16_RSVD_PG 0
+#define BIT_MASK_CH16_RSVD_PG 0xfff
+#define BIT_CH16_RSVD_PG(x) \
+ (((x) & BIT_MASK_CH16_RSVD_PG) << BIT_SHIFT_CH16_RSVD_PG)
+#define BITS_CH16_RSVD_PG (BIT_MASK_CH16_RSVD_PG << BIT_SHIFT_CH16_RSVD_PG)
+#define BIT_CLEAR_CH16_RSVD_PG(x) ((x) & (~BITS_CH16_RSVD_PG))
+#define BIT_GET_CH16_RSVD_PG(x) \
+ (((x) >> BIT_SHIFT_CH16_RSVD_PG) & BIT_MASK_CH16_RSVD_PG)
+#define BIT_SET_CH16_RSVD_PG(x, v) \
+ (BIT_CLEAR_CH16_RSVD_PG(x) | BIT_CH16_RSVD_PG(v))
+
+/* 2 REG_HWAMSDU_CTL1 (Offset 0x2250) */
+
+#define BIT_SHIFT_HWAMSDU_PKTNUM 8
+#define BIT_MASK_HWAMSDU_PKTNUM 0x3f
+#define BIT_HWAMSDU_PKTNUM(x) \
+ (((x) & BIT_MASK_HWAMSDU_PKTNUM) << BIT_SHIFT_HWAMSDU_PKTNUM)
+#define BITS_HWAMSDU_PKTNUM \
+ (BIT_MASK_HWAMSDU_PKTNUM << BIT_SHIFT_HWAMSDU_PKTNUM)
+#define BIT_CLEAR_HWAMSDU_PKTNUM(x) ((x) & (~BITS_HWAMSDU_PKTNUM))
+#define BIT_GET_HWAMSDU_PKTNUM(x) \
+ (((x) >> BIT_SHIFT_HWAMSDU_PKTNUM) & BIT_MASK_HWAMSDU_PKTNUM)
+#define BIT_SET_HWAMSDU_PKTNUM(x, v) \
+ (BIT_CLEAR_HWAMSDU_PKTNUM(x) | BIT_HWAMSDU_PKTNUM(v))
+
+#define BIT_HWAMSDU_BUSY BIT(7)
+#define BIT_SINGLE_AMSDU BIT(2)
+#define BIT_HWAMSDU_PADDING_MODE BIT(1)
+#define BIT_HWAMSDU_EN BIT(0)
+
+/* 2 REG_HWAMSDU_CTL2 (Offset 0x2254) */
+
+#define BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT 16
+#define BIT_MASK_HWAMSDU_AMSDU_TIMEOUT 0xffff
+#define BIT_HWAMSDU_AMSDU_TIMEOUT(x) \
+ (((x) & BIT_MASK_HWAMSDU_AMSDU_TIMEOUT) \
+ << BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT)
+#define BITS_HWAMSDU_AMSDU_TIMEOUT \
+ (BIT_MASK_HWAMSDU_AMSDU_TIMEOUT << BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT)
+#define BIT_CLEAR_HWAMSDU_AMSDU_TIMEOUT(x) ((x) & (~BITS_HWAMSDU_AMSDU_TIMEOUT))
+#define BIT_GET_HWAMSDU_AMSDU_TIMEOUT(x) \
+ (((x) >> BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT) & \
+ BIT_MASK_HWAMSDU_AMSDU_TIMEOUT)
+#define BIT_SET_HWAMSDU_AMSDU_TIMEOUT(x, v) \
+ (BIT_CLEAR_HWAMSDU_AMSDU_TIMEOUT(x) | BIT_HWAMSDU_AMSDU_TIMEOUT(v))
+
+#define BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT 0
+#define BIT_MASK_HWAMSDU_MSDU_TIMEOUT 0xffff
+#define BIT_HWAMSDU_MSDU_TIMEOUT(x) \
+ (((x) & BIT_MASK_HWAMSDU_MSDU_TIMEOUT) \
+ << BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT)
+#define BITS_HWAMSDU_MSDU_TIMEOUT \
+ (BIT_MASK_HWAMSDU_MSDU_TIMEOUT << BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT)
+#define BIT_CLEAR_HWAMSDU_MSDU_TIMEOUT(x) ((x) & (~BITS_HWAMSDU_MSDU_TIMEOUT))
+#define BIT_GET_HWAMSDU_MSDU_TIMEOUT(x) \
+ (((x) >> BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT) & \
+ BIT_MASK_HWAMSDU_MSDU_TIMEOUT)
+#define BIT_SET_HWAMSDU_MSDU_TIMEOUT(x, v) \
+ (BIT_CLEAR_HWAMSDU_MSDU_TIMEOUT(x) | BIT_HWAMSDU_MSDU_TIMEOUT(v))
+
+/* 2 REG_HI8Q_TXBD_DESA_L (Offset 0x2300) */
+
+#define BIT_SHIFT_HI8Q_TXBD_DESA_L 0
+#define BIT_MASK_HI8Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI8Q_TXBD_DESA_L(x) \
+ (((x) & BIT_MASK_HI8Q_TXBD_DESA_L) << BIT_SHIFT_HI8Q_TXBD_DESA_L)
+#define BITS_HI8Q_TXBD_DESA_L \
+ (BIT_MASK_HI8Q_TXBD_DESA_L << BIT_SHIFT_HI8Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI8Q_TXBD_DESA_L(x) ((x) & (~BITS_HI8Q_TXBD_DESA_L))
+#define BIT_GET_HI8Q_TXBD_DESA_L(x) \
+ (((x) >> BIT_SHIFT_HI8Q_TXBD_DESA_L) & BIT_MASK_HI8Q_TXBD_DESA_L)
+#define BIT_SET_HI8Q_TXBD_DESA_L(x, v) \
+ (BIT_CLEAR_HI8Q_TXBD_DESA_L(x) | BIT_HI8Q_TXBD_DESA_L(v))
+
+/* 2 REG_HI8Q_TXBD_DESA_H (Offset 0x2304) */
+
+#define BIT_SHIFT_HI8Q_TXBD_DESA_H 0
+#define BIT_MASK_HI8Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI8Q_TXBD_DESA_H(x) \
+ (((x) & BIT_MASK_HI8Q_TXBD_DESA_H) << BIT_SHIFT_HI8Q_TXBD_DESA_H)
+#define BITS_HI8Q_TXBD_DESA_H \
+ (BIT_MASK_HI8Q_TXBD_DESA_H << BIT_SHIFT_HI8Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI8Q_TXBD_DESA_H(x) ((x) & (~BITS_HI8Q_TXBD_DESA_H))
+#define BIT_GET_HI8Q_TXBD_DESA_H(x) \
+ (((x) >> BIT_SHIFT_HI8Q_TXBD_DESA_H) & BIT_MASK_HI8Q_TXBD_DESA_H)
+#define BIT_SET_HI8Q_TXBD_DESA_H(x, v) \
+ (BIT_CLEAR_HI8Q_TXBD_DESA_H(x) | BIT_HI8Q_TXBD_DESA_H(v))
+
+/* 2 REG_HI9Q_TXBD_DESA_L (Offset 0x2308) */
+
+#define BIT_SHIFT_HI9Q_TXBD_DESA_L 0
+#define BIT_MASK_HI9Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI9Q_TXBD_DESA_L(x) \
+ (((x) & BIT_MASK_HI9Q_TXBD_DESA_L) << BIT_SHIFT_HI9Q_TXBD_DESA_L)
+#define BITS_HI9Q_TXBD_DESA_L \
+ (BIT_MASK_HI9Q_TXBD_DESA_L << BIT_SHIFT_HI9Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI9Q_TXBD_DESA_L(x) ((x) & (~BITS_HI9Q_TXBD_DESA_L))
+#define BIT_GET_HI9Q_TXBD_DESA_L(x) \
+ (((x) >> BIT_SHIFT_HI9Q_TXBD_DESA_L) & BIT_MASK_HI9Q_TXBD_DESA_L)
+#define BIT_SET_HI9Q_TXBD_DESA_L(x, v) \
+ (BIT_CLEAR_HI9Q_TXBD_DESA_L(x) | BIT_HI9Q_TXBD_DESA_L(v))
+
+/* 2 REG_HI9Q_TXBD_DESA_H (Offset 0x230C) */
+
+#define BIT_SHIFT_HI9Q_TXBD_DESA_H 0
+#define BIT_MASK_HI9Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI9Q_TXBD_DESA_H(x) \
+ (((x) & BIT_MASK_HI9Q_TXBD_DESA_H) << BIT_SHIFT_HI9Q_TXBD_DESA_H)
+#define BITS_HI9Q_TXBD_DESA_H \
+ (BIT_MASK_HI9Q_TXBD_DESA_H << BIT_SHIFT_HI9Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI9Q_TXBD_DESA_H(x) ((x) & (~BITS_HI9Q_TXBD_DESA_H))
+#define BIT_GET_HI9Q_TXBD_DESA_H(x) \
+ (((x) >> BIT_SHIFT_HI9Q_TXBD_DESA_H) & BIT_MASK_HI9Q_TXBD_DESA_H)
+#define BIT_SET_HI9Q_TXBD_DESA_H(x, v) \
+ (BIT_CLEAR_HI9Q_TXBD_DESA_H(x) | BIT_HI9Q_TXBD_DESA_H(v))
+
+/* 2 REG_HI10Q_TXBD_DESA_L (Offset 0x2310) */
+
+#define BIT_SHIFT_HI10Q_TXBD_DESA_L 0
+#define BIT_MASK_HI10Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI10Q_TXBD_DESA_L(x) \
+ (((x) & BIT_MASK_HI10Q_TXBD_DESA_L) << BIT_SHIFT_HI10Q_TXBD_DESA_L)
+#define BITS_HI10Q_TXBD_DESA_L \
+ (BIT_MASK_HI10Q_TXBD_DESA_L << BIT_SHIFT_HI10Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI10Q_TXBD_DESA_L(x) ((x) & (~BITS_HI10Q_TXBD_DESA_L))
+#define BIT_GET_HI10Q_TXBD_DESA_L(x) \
+ (((x) >> BIT_SHIFT_HI10Q_TXBD_DESA_L) & BIT_MASK_HI10Q_TXBD_DESA_L)
+#define BIT_SET_HI10Q_TXBD_DESA_L(x, v) \
+ (BIT_CLEAR_HI10Q_TXBD_DESA_L(x) | BIT_HI10Q_TXBD_DESA_L(v))
+
+/* 2 REG_HI10Q_TXBD_DESA_H (Offset 0x2314) */
+
+#define BIT_SHIFT_HI10Q_TXBD_DESA_H 0
+#define BIT_MASK_HI10Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI10Q_TXBD_DESA_H(x) \
+ (((x) & BIT_MASK_HI10Q_TXBD_DESA_H) << BIT_SHIFT_HI10Q_TXBD_DESA_H)
+#define BITS_HI10Q_TXBD_DESA_H \
+ (BIT_MASK_HI10Q_TXBD_DESA_H << BIT_SHIFT_HI10Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI10Q_TXBD_DESA_H(x) ((x) & (~BITS_HI10Q_TXBD_DESA_H))
+#define BIT_GET_HI10Q_TXBD_DESA_H(x) \
+ (((x) >> BIT_SHIFT_HI10Q_TXBD_DESA_H) & BIT_MASK_HI10Q_TXBD_DESA_H)
+#define BIT_SET_HI10Q_TXBD_DESA_H(x, v) \
+ (BIT_CLEAR_HI10Q_TXBD_DESA_H(x) | BIT_HI10Q_TXBD_DESA_H(v))
+
+/* 2 REG_HI11Q_TXBD_DESA_L (Offset 0x2318) */
+
+#define BIT_SHIFT_HI11Q_TXBD_DESA_L 0
+#define BIT_MASK_HI11Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI11Q_TXBD_DESA_L(x) \
+ (((x) & BIT_MASK_HI11Q_TXBD_DESA_L) << BIT_SHIFT_HI11Q_TXBD_DESA_L)
+#define BITS_HI11Q_TXBD_DESA_L \
+ (BIT_MASK_HI11Q_TXBD_DESA_L << BIT_SHIFT_HI11Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI11Q_TXBD_DESA_L(x) ((x) & (~BITS_HI11Q_TXBD_DESA_L))
+#define BIT_GET_HI11Q_TXBD_DESA_L(x) \
+ (((x) >> BIT_SHIFT_HI11Q_TXBD_DESA_L) & BIT_MASK_HI11Q_TXBD_DESA_L)
+#define BIT_SET_HI11Q_TXBD_DESA_L(x, v) \
+ (BIT_CLEAR_HI11Q_TXBD_DESA_L(x) | BIT_HI11Q_TXBD_DESA_L(v))
+
+/* 2 REG_HI11Q_TXBD_DESA_H (Offset 0x231C) */
+
+#define BIT_SHIFT_HI11Q_TXBD_DESA_H 0
+#define BIT_MASK_HI11Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI11Q_TXBD_DESA_H(x) \
+ (((x) & BIT_MASK_HI11Q_TXBD_DESA_H) << BIT_SHIFT_HI11Q_TXBD_DESA_H)
+#define BITS_HI11Q_TXBD_DESA_H \
+ (BIT_MASK_HI11Q_TXBD_DESA_H << BIT_SHIFT_HI11Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI11Q_TXBD_DESA_H(x) ((x) & (~BITS_HI11Q_TXBD_DESA_H))
+#define BIT_GET_HI11Q_TXBD_DESA_H(x) \
+ (((x) >> BIT_SHIFT_HI11Q_TXBD_DESA_H) & BIT_MASK_HI11Q_TXBD_DESA_H)
+#define BIT_SET_HI11Q_TXBD_DESA_H(x, v) \
+ (BIT_CLEAR_HI11Q_TXBD_DESA_H(x) | BIT_HI11Q_TXBD_DESA_H(v))
+
+/* 2 REG_HI12Q_TXBD_DESA_L (Offset 0x2320) */
+
+#define BIT_SHIFT_HI12Q_TXBD_DESA_L 0
+#define BIT_MASK_HI12Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI12Q_TXBD_DESA_L(x) \
+ (((x) & BIT_MASK_HI12Q_TXBD_DESA_L) << BIT_SHIFT_HI12Q_TXBD_DESA_L)
+#define BITS_HI12Q_TXBD_DESA_L \
+ (BIT_MASK_HI12Q_TXBD_DESA_L << BIT_SHIFT_HI12Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI12Q_TXBD_DESA_L(x) ((x) & (~BITS_HI12Q_TXBD_DESA_L))
+#define BIT_GET_HI12Q_TXBD_DESA_L(x) \
+ (((x) >> BIT_SHIFT_HI12Q_TXBD_DESA_L) & BIT_MASK_HI12Q_TXBD_DESA_L)
+#define BIT_SET_HI12Q_TXBD_DESA_L(x, v) \
+ (BIT_CLEAR_HI12Q_TXBD_DESA_L(x) | BIT_HI12Q_TXBD_DESA_L(v))
+
+/* 2 REG_HI12Q_TXBD_DESA_H (Offset 0x2324) */
+
+#define BIT_SHIFT_HI12Q_TXBD_DESA_H 0
+#define BIT_MASK_HI12Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI12Q_TXBD_DESA_H(x) \
+ (((x) & BIT_MASK_HI12Q_TXBD_DESA_H) << BIT_SHIFT_HI12Q_TXBD_DESA_H)
+#define BITS_HI12Q_TXBD_DESA_H \
+ (BIT_MASK_HI12Q_TXBD_DESA_H << BIT_SHIFT_HI12Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI12Q_TXBD_DESA_H(x) ((x) & (~BITS_HI12Q_TXBD_DESA_H))
+#define BIT_GET_HI12Q_TXBD_DESA_H(x) \
+ (((x) >> BIT_SHIFT_HI12Q_TXBD_DESA_H) & BIT_MASK_HI12Q_TXBD_DESA_H)
+#define BIT_SET_HI12Q_TXBD_DESA_H(x, v) \
+ (BIT_CLEAR_HI12Q_TXBD_DESA_H(x) | BIT_HI12Q_TXBD_DESA_H(v))
+
+/* 2 REG_HI13Q_TXBD_DESA_L (Offset 0x2328) */
+
+#define BIT_SHIFT_HI13Q_TXBD_DESA_L 0
+#define BIT_MASK_HI13Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI13Q_TXBD_DESA_L(x) \
+ (((x) & BIT_MASK_HI13Q_TXBD_DESA_L) << BIT_SHIFT_HI13Q_TXBD_DESA_L)
+#define BITS_HI13Q_TXBD_DESA_L \
+ (BIT_MASK_HI13Q_TXBD_DESA_L << BIT_SHIFT_HI13Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI13Q_TXBD_DESA_L(x) ((x) & (~BITS_HI13Q_TXBD_DESA_L))
+#define BIT_GET_HI13Q_TXBD_DESA_L(x) \
+ (((x) >> BIT_SHIFT_HI13Q_TXBD_DESA_L) & BIT_MASK_HI13Q_TXBD_DESA_L)
+#define BIT_SET_HI13Q_TXBD_DESA_L(x, v) \
+ (BIT_CLEAR_HI13Q_TXBD_DESA_L(x) | BIT_HI13Q_TXBD_DESA_L(v))
+
+/* 2 REG_HI13Q_TXBD_DESA_H (Offset 0x232C) */
+
+#define BIT_SHIFT_HI13Q_TXBD_DESA_H 0
+#define BIT_MASK_HI13Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI13Q_TXBD_DESA_H(x) \
+ (((x) & BIT_MASK_HI13Q_TXBD_DESA_H) << BIT_SHIFT_HI13Q_TXBD_DESA_H)
+#define BITS_HI13Q_TXBD_DESA_H \
+ (BIT_MASK_HI13Q_TXBD_DESA_H << BIT_SHIFT_HI13Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI13Q_TXBD_DESA_H(x) ((x) & (~BITS_HI13Q_TXBD_DESA_H))
+#define BIT_GET_HI13Q_TXBD_DESA_H(x) \
+ (((x) >> BIT_SHIFT_HI13Q_TXBD_DESA_H) & BIT_MASK_HI13Q_TXBD_DESA_H)
+#define BIT_SET_HI13Q_TXBD_DESA_H(x, v) \
+ (BIT_CLEAR_HI13Q_TXBD_DESA_H(x) | BIT_HI13Q_TXBD_DESA_H(v))
+
+/* 2 REG_HI14Q_TXBD_DESA_L (Offset 0x2330) */
+
+#define BIT_SHIFT_HI14Q_TXBD_DESA_L 0
+#define BIT_MASK_HI14Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI14Q_TXBD_DESA_L(x) \
+ (((x) & BIT_MASK_HI14Q_TXBD_DESA_L) << BIT_SHIFT_HI14Q_TXBD_DESA_L)
+#define BITS_HI14Q_TXBD_DESA_L \
+ (BIT_MASK_HI14Q_TXBD_DESA_L << BIT_SHIFT_HI14Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI14Q_TXBD_DESA_L(x) ((x) & (~BITS_HI14Q_TXBD_DESA_L))
+#define BIT_GET_HI14Q_TXBD_DESA_L(x) \
+ (((x) >> BIT_SHIFT_HI14Q_TXBD_DESA_L) & BIT_MASK_HI14Q_TXBD_DESA_L)
+#define BIT_SET_HI14Q_TXBD_DESA_L(x, v) \
+ (BIT_CLEAR_HI14Q_TXBD_DESA_L(x) | BIT_HI14Q_TXBD_DESA_L(v))
+
+/* 2 REG_HI14Q_TXBD_DESA_H (Offset 0x2334) */
+
+#define BIT_SHIFT_HI14Q_TXBD_DESA_H 0
+#define BIT_MASK_HI14Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI14Q_TXBD_DESA_H(x) \
+ (((x) & BIT_MASK_HI14Q_TXBD_DESA_H) << BIT_SHIFT_HI14Q_TXBD_DESA_H)
+#define BITS_HI14Q_TXBD_DESA_H \
+ (BIT_MASK_HI14Q_TXBD_DESA_H << BIT_SHIFT_HI14Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI14Q_TXBD_DESA_H(x) ((x) & (~BITS_HI14Q_TXBD_DESA_H))
+#define BIT_GET_HI14Q_TXBD_DESA_H(x) \
+ (((x) >> BIT_SHIFT_HI14Q_TXBD_DESA_H) & BIT_MASK_HI14Q_TXBD_DESA_H)
+#define BIT_SET_HI14Q_TXBD_DESA_H(x, v) \
+ (BIT_CLEAR_HI14Q_TXBD_DESA_H(x) | BIT_HI14Q_TXBD_DESA_H(v))
+
+/* 2 REG_HI15Q_TXBD_DESA_L (Offset 0x2338) */
+
+#define BIT_SHIFT_HI15Q_TXBD_DESA_L 0
+#define BIT_MASK_HI15Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI15Q_TXBD_DESA_L(x) \
+ (((x) & BIT_MASK_HI15Q_TXBD_DESA_L) << BIT_SHIFT_HI15Q_TXBD_DESA_L)
+#define BITS_HI15Q_TXBD_DESA_L \
+ (BIT_MASK_HI15Q_TXBD_DESA_L << BIT_SHIFT_HI15Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI15Q_TXBD_DESA_L(x) ((x) & (~BITS_HI15Q_TXBD_DESA_L))
+#define BIT_GET_HI15Q_TXBD_DESA_L(x) \
+ (((x) >> BIT_SHIFT_HI15Q_TXBD_DESA_L) & BIT_MASK_HI15Q_TXBD_DESA_L)
+#define BIT_SET_HI15Q_TXBD_DESA_L(x, v) \
+ (BIT_CLEAR_HI15Q_TXBD_DESA_L(x) | BIT_HI15Q_TXBD_DESA_L(v))
+
+/* 2 REG_HI15Q_TXBD_DESA_H (Offset 0x233C) */
+
+#define BIT_SHIFT_HI15Q_TXBD_DESA_H 0
+#define BIT_MASK_HI15Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI15Q_TXBD_DESA_H(x) \
+ (((x) & BIT_MASK_HI15Q_TXBD_DESA_H) << BIT_SHIFT_HI15Q_TXBD_DESA_H)
+#define BITS_HI15Q_TXBD_DESA_H \
+ (BIT_MASK_HI15Q_TXBD_DESA_H << BIT_SHIFT_HI15Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI15Q_TXBD_DESA_H(x) ((x) & (~BITS_HI15Q_TXBD_DESA_H))
+#define BIT_GET_HI15Q_TXBD_DESA_H(x) \
+ (((x) >> BIT_SHIFT_HI15Q_TXBD_DESA_H) & BIT_MASK_HI15Q_TXBD_DESA_H)
+#define BIT_SET_HI15Q_TXBD_DESA_H(x, v) \
+ (BIT_CLEAR_HI15Q_TXBD_DESA_H(x) | BIT_HI15Q_TXBD_DESA_H(v))
+
+/* 2 REG_HI16Q_TXBD_DESA_L (Offset 0x2340) */
+
+#define BIT_SHIFT_HI16Q_TXBD_DESA_L 0
+#define BIT_MASK_HI16Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI16Q_TXBD_DESA_L(x) \
+ (((x) & BIT_MASK_HI16Q_TXBD_DESA_L) << BIT_SHIFT_HI16Q_TXBD_DESA_L)
+#define BITS_HI16Q_TXBD_DESA_L \
+ (BIT_MASK_HI16Q_TXBD_DESA_L << BIT_SHIFT_HI16Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI16Q_TXBD_DESA_L(x) ((x) & (~BITS_HI16Q_TXBD_DESA_L))
+#define BIT_GET_HI16Q_TXBD_DESA_L(x) \
+ (((x) >> BIT_SHIFT_HI16Q_TXBD_DESA_L) & BIT_MASK_HI16Q_TXBD_DESA_L)
+#define BIT_SET_HI16Q_TXBD_DESA_L(x, v) \
+ (BIT_CLEAR_HI16Q_TXBD_DESA_L(x) | BIT_HI16Q_TXBD_DESA_L(v))
+
+/* 2 REG_HI16Q_TXBD_DESA_H (Offset 0x2344) */
+
+#define BIT_SHIFT_HI16Q_TXBD_DESA_H 0
+#define BIT_MASK_HI16Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI16Q_TXBD_DESA_H(x) \
+ (((x) & BIT_MASK_HI16Q_TXBD_DESA_H) << BIT_SHIFT_HI16Q_TXBD_DESA_H)
+#define BITS_HI16Q_TXBD_DESA_H \
+ (BIT_MASK_HI16Q_TXBD_DESA_H << BIT_SHIFT_HI16Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI16Q_TXBD_DESA_H(x) ((x) & (~BITS_HI16Q_TXBD_DESA_H))
+#define BIT_GET_HI16Q_TXBD_DESA_H(x) \
+ (((x) >> BIT_SHIFT_HI16Q_TXBD_DESA_H) & BIT_MASK_HI16Q_TXBD_DESA_H)
+#define BIT_SET_HI16Q_TXBD_DESA_H(x, v) \
+ (BIT_CLEAR_HI16Q_TXBD_DESA_H(x) | BIT_HI16Q_TXBD_DESA_H(v))
+
+/* 2 REG_HI17Q_TXBD_DESA_L (Offset 0x2348) */
+
+#define BIT_SHIFT_HI17Q_TXBD_DESA_L 0
+#define BIT_MASK_HI17Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI17Q_TXBD_DESA_L(x) \
+ (((x) & BIT_MASK_HI17Q_TXBD_DESA_L) << BIT_SHIFT_HI17Q_TXBD_DESA_L)
+#define BITS_HI17Q_TXBD_DESA_L \
+ (BIT_MASK_HI17Q_TXBD_DESA_L << BIT_SHIFT_HI17Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI17Q_TXBD_DESA_L(x) ((x) & (~BITS_HI17Q_TXBD_DESA_L))
+#define BIT_GET_HI17Q_TXBD_DESA_L(x) \
+ (((x) >> BIT_SHIFT_HI17Q_TXBD_DESA_L) & BIT_MASK_HI17Q_TXBD_DESA_L)
+#define BIT_SET_HI17Q_TXBD_DESA_L(x, v) \
+ (BIT_CLEAR_HI17Q_TXBD_DESA_L(x) | BIT_HI17Q_TXBD_DESA_L(v))
+
+/* 2 REG_HI17Q_TXBD_DESA_H (Offset 0x234C) */
+
+#define BIT_SHIFT_HI17Q_TXBD_DESA_H 0
+#define BIT_MASK_HI17Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI17Q_TXBD_DESA_H(x) \
+ (((x) & BIT_MASK_HI17Q_TXBD_DESA_H) << BIT_SHIFT_HI17Q_TXBD_DESA_H)
+#define BITS_HI17Q_TXBD_DESA_H \
+ (BIT_MASK_HI17Q_TXBD_DESA_H << BIT_SHIFT_HI17Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI17Q_TXBD_DESA_H(x) ((x) & (~BITS_HI17Q_TXBD_DESA_H))
+#define BIT_GET_HI17Q_TXBD_DESA_H(x) \
+ (((x) >> BIT_SHIFT_HI17Q_TXBD_DESA_H) & BIT_MASK_HI17Q_TXBD_DESA_H)
+#define BIT_SET_HI17Q_TXBD_DESA_H(x, v) \
+ (BIT_CLEAR_HI17Q_TXBD_DESA_H(x) | BIT_HI17Q_TXBD_DESA_H(v))
+
+/* 2 REG_HI18Q_TXBD_DESA_L (Offset 0x2350) */
+
+#define BIT_SHIFT_HI18Q_TXBD_DESA_L 0
+#define BIT_MASK_HI18Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI18Q_TXBD_DESA_L(x) \
+ (((x) & BIT_MASK_HI18Q_TXBD_DESA_L) << BIT_SHIFT_HI18Q_TXBD_DESA_L)
+#define BITS_HI18Q_TXBD_DESA_L \
+ (BIT_MASK_HI18Q_TXBD_DESA_L << BIT_SHIFT_HI18Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI18Q_TXBD_DESA_L(x) ((x) & (~BITS_HI18Q_TXBD_DESA_L))
+#define BIT_GET_HI18Q_TXBD_DESA_L(x) \
+ (((x) >> BIT_SHIFT_HI18Q_TXBD_DESA_L) & BIT_MASK_HI18Q_TXBD_DESA_L)
+#define BIT_SET_HI18Q_TXBD_DESA_L(x, v) \
+ (BIT_CLEAR_HI18Q_TXBD_DESA_L(x) | BIT_HI18Q_TXBD_DESA_L(v))
+
+/* 2 REG_HI18Q_TXBD_DESA_H (Offset 0x2354) */
+
+#define BIT_SHIFT_HI18Q_TXBD_DESA_H 0
+#define BIT_MASK_HI18Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI18Q_TXBD_DESA_H(x) \
+ (((x) & BIT_MASK_HI18Q_TXBD_DESA_H) << BIT_SHIFT_HI18Q_TXBD_DESA_H)
+#define BITS_HI18Q_TXBD_DESA_H \
+ (BIT_MASK_HI18Q_TXBD_DESA_H << BIT_SHIFT_HI18Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI18Q_TXBD_DESA_H(x) ((x) & (~BITS_HI18Q_TXBD_DESA_H))
+#define BIT_GET_HI18Q_TXBD_DESA_H(x) \
+ (((x) >> BIT_SHIFT_HI18Q_TXBD_DESA_H) & BIT_MASK_HI18Q_TXBD_DESA_H)
+#define BIT_SET_HI18Q_TXBD_DESA_H(x, v) \
+ (BIT_CLEAR_HI18Q_TXBD_DESA_H(x) | BIT_HI18Q_TXBD_DESA_H(v))
+
+/* 2 REG_HI19Q_TXBD_DESA_L (Offset 0x2358) */
+
+#define BIT_SHIFT_HI19Q_TXBD_DESA_L 0
+#define BIT_MASK_HI19Q_TXBD_DESA_L 0xffffffffL
+#define BIT_HI19Q_TXBD_DESA_L(x) \
+ (((x) & BIT_MASK_HI19Q_TXBD_DESA_L) << BIT_SHIFT_HI19Q_TXBD_DESA_L)
+#define BITS_HI19Q_TXBD_DESA_L \
+ (BIT_MASK_HI19Q_TXBD_DESA_L << BIT_SHIFT_HI19Q_TXBD_DESA_L)
+#define BIT_CLEAR_HI19Q_TXBD_DESA_L(x) ((x) & (~BITS_HI19Q_TXBD_DESA_L))
+#define BIT_GET_HI19Q_TXBD_DESA_L(x) \
+ (((x) >> BIT_SHIFT_HI19Q_TXBD_DESA_L) & BIT_MASK_HI19Q_TXBD_DESA_L)
+#define BIT_SET_HI19Q_TXBD_DESA_L(x, v) \
+ (BIT_CLEAR_HI19Q_TXBD_DESA_L(x) | BIT_HI19Q_TXBD_DESA_L(v))
+
+/* 2 REG_HI19Q_TXBD_DESA_H (Offset 0x235C) */
+
+#define BIT_CLR_P0HI19Q_HW_IDX BIT(25)
+#define BIT_CLR_P0HI18Q_HW_IDX BIT(24)
+#define BIT_CLR_P0HI17Q_HW_IDX BIT(23)
+#define BIT_CLR_P0HI16Q_HW_IDX BIT(22)
+#define BIT_CLR_P0HI19Q_HOST_IDX BIT(9)
+#define BIT_CLR_P0HI18Q_HOST_IDX BIT(8)
+#define BIT_CLR_P0HI17Q_HOST_IDX BIT(7)
+#define BIT_CLR_P0HI16Q_HOST_IDX BIT(6)
+
+#define BIT_SHIFT_HI19Q_TXBD_DESA_H 0
+#define BIT_MASK_HI19Q_TXBD_DESA_H 0xffffffffL
+#define BIT_HI19Q_TXBD_DESA_H(x) \
+ (((x) & BIT_MASK_HI19Q_TXBD_DESA_H) << BIT_SHIFT_HI19Q_TXBD_DESA_H)
+#define BITS_HI19Q_TXBD_DESA_H \
+ (BIT_MASK_HI19Q_TXBD_DESA_H << BIT_SHIFT_HI19Q_TXBD_DESA_H)
+#define BIT_CLEAR_HI19Q_TXBD_DESA_H(x) ((x) & (~BITS_HI19Q_TXBD_DESA_H))
+#define BIT_GET_HI19Q_TXBD_DESA_H(x) \
+ (((x) >> BIT_SHIFT_HI19Q_TXBD_DESA_H) & BIT_MASK_HI19Q_TXBD_DESA_H)
+#define BIT_SET_HI19Q_TXBD_DESA_H(x, v) \
+ (BIT_CLEAR_HI19Q_TXBD_DESA_H(x) | BIT_HI19Q_TXBD_DESA_H(v))
+
+/* 2 REG_P0HI16Q_TXBD_IDX (Offset 0x2370) */
+
+#define BIT_SHIFT_P0HI16Q_HW_IDX 16
+#define BIT_MASK_P0HI16Q_HW_IDX 0xfff
+#define BIT_P0HI16Q_HW_IDX(x) \
+ (((x) & BIT_MASK_P0HI16Q_HW_IDX) << BIT_SHIFT_P0HI16Q_HW_IDX)
+#define BITS_P0HI16Q_HW_IDX \
+ (BIT_MASK_P0HI16Q_HW_IDX << BIT_SHIFT_P0HI16Q_HW_IDX)
+#define BIT_CLEAR_P0HI16Q_HW_IDX(x) ((x) & (~BITS_P0HI16Q_HW_IDX))
+#define BIT_GET_P0HI16Q_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI16Q_HW_IDX) & BIT_MASK_P0HI16Q_HW_IDX)
+#define BIT_SET_P0HI16Q_HW_IDX(x, v) \
+ (BIT_CLEAR_P0HI16Q_HW_IDX(x) | BIT_P0HI16Q_HW_IDX(v))
+
+#define BIT_SHIFT_P0HI16Q_HOST_IDX 0
+#define BIT_MASK_P0HI16Q_HOST_IDX 0xfff
+#define BIT_P0HI16Q_HOST_IDX(x) \
+ (((x) & BIT_MASK_P0HI16Q_HOST_IDX) << BIT_SHIFT_P0HI16Q_HOST_IDX)
+#define BITS_P0HI16Q_HOST_IDX \
+ (BIT_MASK_P0HI16Q_HOST_IDX << BIT_SHIFT_P0HI16Q_HOST_IDX)
+#define BIT_CLEAR_P0HI16Q_HOST_IDX(x) ((x) & (~BITS_P0HI16Q_HOST_IDX))
+#define BIT_GET_P0HI16Q_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI16Q_HOST_IDX) & BIT_MASK_P0HI16Q_HOST_IDX)
+#define BIT_SET_P0HI16Q_HOST_IDX(x, v) \
+ (BIT_CLEAR_P0HI16Q_HOST_IDX(x) | BIT_P0HI16Q_HOST_IDX(v))
+
+/* 2 REG_P0HI17Q_TXBD_IDX (Offset 0x2374) */
+
+#define BIT_SHIFT_P0HI17Q_HW_IDX 16
+#define BIT_MASK_P0HI17Q_HW_IDX 0xfff
+#define BIT_P0HI17Q_HW_IDX(x) \
+ (((x) & BIT_MASK_P0HI17Q_HW_IDX) << BIT_SHIFT_P0HI17Q_HW_IDX)
+#define BITS_P0HI17Q_HW_IDX \
+ (BIT_MASK_P0HI17Q_HW_IDX << BIT_SHIFT_P0HI17Q_HW_IDX)
+#define BIT_CLEAR_P0HI17Q_HW_IDX(x) ((x) & (~BITS_P0HI17Q_HW_IDX))
+#define BIT_GET_P0HI17Q_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI17Q_HW_IDX) & BIT_MASK_P0HI17Q_HW_IDX)
+#define BIT_SET_P0HI17Q_HW_IDX(x, v) \
+ (BIT_CLEAR_P0HI17Q_HW_IDX(x) | BIT_P0HI17Q_HW_IDX(v))
+
+#define BIT_SHIFT_P0HI17Q_HOST_IDX 0
+#define BIT_MASK_P0HI17Q_HOST_IDX 0xfff
+#define BIT_P0HI17Q_HOST_IDX(x) \
+ (((x) & BIT_MASK_P0HI17Q_HOST_IDX) << BIT_SHIFT_P0HI17Q_HOST_IDX)
+#define BITS_P0HI17Q_HOST_IDX \
+ (BIT_MASK_P0HI17Q_HOST_IDX << BIT_SHIFT_P0HI17Q_HOST_IDX)
+#define BIT_CLEAR_P0HI17Q_HOST_IDX(x) ((x) & (~BITS_P0HI17Q_HOST_IDX))
+#define BIT_GET_P0HI17Q_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI17Q_HOST_IDX) & BIT_MASK_P0HI17Q_HOST_IDX)
+#define BIT_SET_P0HI17Q_HOST_IDX(x, v) \
+ (BIT_CLEAR_P0HI17Q_HOST_IDX(x) | BIT_P0HI17Q_HOST_IDX(v))
+
+/* 2 REG_P0HI18Q_TXBD_IDX (Offset 0x2378) */
+
+#define BIT_SHIFT_P0HI18Q_HW_IDX 16
+#define BIT_MASK_P0HI18Q_HW_IDX 0xfff
+#define BIT_P0HI18Q_HW_IDX(x) \
+ (((x) & BIT_MASK_P0HI18Q_HW_IDX) << BIT_SHIFT_P0HI18Q_HW_IDX)
+#define BITS_P0HI18Q_HW_IDX \
+ (BIT_MASK_P0HI18Q_HW_IDX << BIT_SHIFT_P0HI18Q_HW_IDX)
+#define BIT_CLEAR_P0HI18Q_HW_IDX(x) ((x) & (~BITS_P0HI18Q_HW_IDX))
+#define BIT_GET_P0HI18Q_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI18Q_HW_IDX) & BIT_MASK_P0HI18Q_HW_IDX)
+#define BIT_SET_P0HI18Q_HW_IDX(x, v) \
+ (BIT_CLEAR_P0HI18Q_HW_IDX(x) | BIT_P0HI18Q_HW_IDX(v))
+
+#define BIT_SHIFT_P0HI18Q_HOST_IDX 0
+#define BIT_MASK_P0HI18Q_HOST_IDX 0xfff
+#define BIT_P0HI18Q_HOST_IDX(x) \
+ (((x) & BIT_MASK_P0HI18Q_HOST_IDX) << BIT_SHIFT_P0HI18Q_HOST_IDX)
+#define BITS_P0HI18Q_HOST_IDX \
+ (BIT_MASK_P0HI18Q_HOST_IDX << BIT_SHIFT_P0HI18Q_HOST_IDX)
+#define BIT_CLEAR_P0HI18Q_HOST_IDX(x) ((x) & (~BITS_P0HI18Q_HOST_IDX))
+#define BIT_GET_P0HI18Q_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI18Q_HOST_IDX) & BIT_MASK_P0HI18Q_HOST_IDX)
+#define BIT_SET_P0HI18Q_HOST_IDX(x, v) \
+ (BIT_CLEAR_P0HI18Q_HOST_IDX(x) | BIT_P0HI18Q_HOST_IDX(v))
+
+/* 2 REG_P0HI19Q_TXBD_IDX (Offset 0x237C) */
+
+#define BIT_SHIFT_P0HI19Q_HW_IDX 16
+#define BIT_MASK_P0HI19Q_HW_IDX 0xfff
+#define BIT_P0HI19Q_HW_IDX(x) \
+ (((x) & BIT_MASK_P0HI19Q_HW_IDX) << BIT_SHIFT_P0HI19Q_HW_IDX)
+#define BITS_P0HI19Q_HW_IDX \
+ (BIT_MASK_P0HI19Q_HW_IDX << BIT_SHIFT_P0HI19Q_HW_IDX)
+#define BIT_CLEAR_P0HI19Q_HW_IDX(x) ((x) & (~BITS_P0HI19Q_HW_IDX))
+#define BIT_GET_P0HI19Q_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI19Q_HW_IDX) & BIT_MASK_P0HI19Q_HW_IDX)
+#define BIT_SET_P0HI19Q_HW_IDX(x, v) \
+ (BIT_CLEAR_P0HI19Q_HW_IDX(x) | BIT_P0HI19Q_HW_IDX(v))
+
+#define BIT_SHIFT_P0HI19Q_HOST_IDX 0
+#define BIT_MASK_P0HI19Q_HOST_IDX 0xfff
+#define BIT_P0HI19Q_HOST_IDX(x) \
+ (((x) & BIT_MASK_P0HI19Q_HOST_IDX) << BIT_SHIFT_P0HI19Q_HOST_IDX)
+#define BITS_P0HI19Q_HOST_IDX \
+ (BIT_MASK_P0HI19Q_HOST_IDX << BIT_SHIFT_P0HI19Q_HOST_IDX)
+#define BIT_CLEAR_P0HI19Q_HOST_IDX(x) ((x) & (~BITS_P0HI19Q_HOST_IDX))
+#define BIT_GET_P0HI19Q_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_P0HI19Q_HOST_IDX) & BIT_MASK_P0HI19Q_HOST_IDX)
+#define BIT_SET_P0HI19Q_HOST_IDX(x, v) \
+ (BIT_CLEAR_P0HI19Q_HOST_IDX(x) | BIT_P0HI19Q_HOST_IDX(v))
+
+/* 2 REG_P0HI16Q_HI17Q_TXBD_NUM (Offset 0x2380) */
+
+#define BIT_P0HI17Q_FLAG BIT(30)
+
+#define BIT_SHIFT_P0HI17Q_DESC_MODE 28
+#define BIT_MASK_P0HI17Q_DESC_MODE 0x3
+#define BIT_P0HI17Q_DESC_MODE(x) \
+ (((x) & BIT_MASK_P0HI17Q_DESC_MODE) << BIT_SHIFT_P0HI17Q_DESC_MODE)
+#define BITS_P0HI17Q_DESC_MODE \
+ (BIT_MASK_P0HI17Q_DESC_MODE << BIT_SHIFT_P0HI17Q_DESC_MODE)
+#define BIT_CLEAR_P0HI17Q_DESC_MODE(x) ((x) & (~BITS_P0HI17Q_DESC_MODE))
+#define BIT_GET_P0HI17Q_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_P0HI17Q_DESC_MODE) & BIT_MASK_P0HI17Q_DESC_MODE)
+#define BIT_SET_P0HI17Q_DESC_MODE(x, v) \
+ (BIT_CLEAR_P0HI17Q_DESC_MODE(x) | BIT_P0HI17Q_DESC_MODE(v))
+
+#define BIT_SHIFT_P0HI17Q_DESC_NUM 16
+#define BIT_MASK_P0HI17Q_DESC_NUM 0xfff
+#define BIT_P0HI17Q_DESC_NUM(x) \
+ (((x) & BIT_MASK_P0HI17Q_DESC_NUM) << BIT_SHIFT_P0HI17Q_DESC_NUM)
+#define BITS_P0HI17Q_DESC_NUM \
+ (BIT_MASK_P0HI17Q_DESC_NUM << BIT_SHIFT_P0HI17Q_DESC_NUM)
+#define BIT_CLEAR_P0HI17Q_DESC_NUM(x) ((x) & (~BITS_P0HI17Q_DESC_NUM))
+#define BIT_GET_P0HI17Q_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_P0HI17Q_DESC_NUM) & BIT_MASK_P0HI17Q_DESC_NUM)
+#define BIT_SET_P0HI17Q_DESC_NUM(x, v) \
+ (BIT_CLEAR_P0HI17Q_DESC_NUM(x) | BIT_P0HI17Q_DESC_NUM(v))
+
+#define BIT_P0HI16Q_FLAG BIT(14)
+
+#define BIT_SHIFT_P0HI16Q_DESC_MODE 12
+#define BIT_MASK_P0HI16Q_DESC_MODE 0x3
+#define BIT_P0HI16Q_DESC_MODE(x) \
+ (((x) & BIT_MASK_P0HI16Q_DESC_MODE) << BIT_SHIFT_P0HI16Q_DESC_MODE)
+#define BITS_P0HI16Q_DESC_MODE \
+ (BIT_MASK_P0HI16Q_DESC_MODE << BIT_SHIFT_P0HI16Q_DESC_MODE)
+#define BIT_CLEAR_P0HI16Q_DESC_MODE(x) ((x) & (~BITS_P0HI16Q_DESC_MODE))
+#define BIT_GET_P0HI16Q_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_P0HI16Q_DESC_MODE) & BIT_MASK_P0HI16Q_DESC_MODE)
+#define BIT_SET_P0HI16Q_DESC_MODE(x, v) \
+ (BIT_CLEAR_P0HI16Q_DESC_MODE(x) | BIT_P0HI16Q_DESC_MODE(v))
+
+#define BIT_SHIFT_P0HI16Q_DESC_NUM 0
+#define BIT_MASK_P0HI16Q_DESC_NUM 0xfff
+#define BIT_P0HI16Q_DESC_NUM(x) \
+ (((x) & BIT_MASK_P0HI16Q_DESC_NUM) << BIT_SHIFT_P0HI16Q_DESC_NUM)
+#define BITS_P0HI16Q_DESC_NUM \
+ (BIT_MASK_P0HI16Q_DESC_NUM << BIT_SHIFT_P0HI16Q_DESC_NUM)
+#define BIT_CLEAR_P0HI16Q_DESC_NUM(x) ((x) & (~BITS_P0HI16Q_DESC_NUM))
+#define BIT_GET_P0HI16Q_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_P0HI16Q_DESC_NUM) & BIT_MASK_P0HI16Q_DESC_NUM)
+#define BIT_SET_P0HI16Q_DESC_NUM(x, v) \
+ (BIT_CLEAR_P0HI16Q_DESC_NUM(x) | BIT_P0HI16Q_DESC_NUM(v))
+
+/* 2 REG_P0HI18Q_HI19Q_TXBD_NUM (Offset 0x2384) */
+
+#define BIT_P0HI19Q_FLAG BIT(30)
+
+#define BIT_SHIFT_P0HI19Q_DESC_MODE 28
+#define BIT_MASK_P0HI19Q_DESC_MODE 0x3
+#define BIT_P0HI19Q_DESC_MODE(x) \
+ (((x) & BIT_MASK_P0HI19Q_DESC_MODE) << BIT_SHIFT_P0HI19Q_DESC_MODE)
+#define BITS_P0HI19Q_DESC_MODE \
+ (BIT_MASK_P0HI19Q_DESC_MODE << BIT_SHIFT_P0HI19Q_DESC_MODE)
+#define BIT_CLEAR_P0HI19Q_DESC_MODE(x) ((x) & (~BITS_P0HI19Q_DESC_MODE))
+#define BIT_GET_P0HI19Q_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_P0HI19Q_DESC_MODE) & BIT_MASK_P0HI19Q_DESC_MODE)
+#define BIT_SET_P0HI19Q_DESC_MODE(x, v) \
+ (BIT_CLEAR_P0HI19Q_DESC_MODE(x) | BIT_P0HI19Q_DESC_MODE(v))
+
+#define BIT_SHIFT_P0HI19Q_DESC_NUM 16
+#define BIT_MASK_P0HI19Q_DESC_NUM 0xfff
+#define BIT_P0HI19Q_DESC_NUM(x) \
+ (((x) & BIT_MASK_P0HI19Q_DESC_NUM) << BIT_SHIFT_P0HI19Q_DESC_NUM)
+#define BITS_P0HI19Q_DESC_NUM \
+ (BIT_MASK_P0HI19Q_DESC_NUM << BIT_SHIFT_P0HI19Q_DESC_NUM)
+#define BIT_CLEAR_P0HI19Q_DESC_NUM(x) ((x) & (~BITS_P0HI19Q_DESC_NUM))
+#define BIT_GET_P0HI19Q_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_P0HI19Q_DESC_NUM) & BIT_MASK_P0HI19Q_DESC_NUM)
+#define BIT_SET_P0HI19Q_DESC_NUM(x, v) \
+ (BIT_CLEAR_P0HI19Q_DESC_NUM(x) | BIT_P0HI19Q_DESC_NUM(v))
+
+#define BIT_P0HI18Q_FLAG BIT(14)
+
+#define BIT_SHIFT_P0HI18Q_DESC_MODE 12
+#define BIT_MASK_P0HI18Q_DESC_MODE 0x3
+#define BIT_P0HI18Q_DESC_MODE(x) \
+ (((x) & BIT_MASK_P0HI18Q_DESC_MODE) << BIT_SHIFT_P0HI18Q_DESC_MODE)
+#define BITS_P0HI18Q_DESC_MODE \
+ (BIT_MASK_P0HI18Q_DESC_MODE << BIT_SHIFT_P0HI18Q_DESC_MODE)
+#define BIT_CLEAR_P0HI18Q_DESC_MODE(x) ((x) & (~BITS_P0HI18Q_DESC_MODE))
+#define BIT_GET_P0HI18Q_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_P0HI18Q_DESC_MODE) & BIT_MASK_P0HI18Q_DESC_MODE)
+#define BIT_SET_P0HI18Q_DESC_MODE(x, v) \
+ (BIT_CLEAR_P0HI18Q_DESC_MODE(x) | BIT_P0HI18Q_DESC_MODE(v))
+
+#define BIT_SHIFT_P0HI18Q_DESC_NUM 0
+#define BIT_MASK_P0HI18Q_DESC_NUM 0xfff
+#define BIT_P0HI18Q_DESC_NUM(x) \
+ (((x) & BIT_MASK_P0HI18Q_DESC_NUM) << BIT_SHIFT_P0HI18Q_DESC_NUM)
+#define BITS_P0HI18Q_DESC_NUM \
+ (BIT_MASK_P0HI18Q_DESC_NUM << BIT_SHIFT_P0HI18Q_DESC_NUM)
+#define BIT_CLEAR_P0HI18Q_DESC_NUM(x) ((x) & (~BITS_P0HI18Q_DESC_NUM))
+#define BIT_GET_P0HI18Q_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_P0HI18Q_DESC_NUM) & BIT_MASK_P0HI18Q_DESC_NUM)
+#define BIT_SET_P0HI18Q_DESC_NUM(x, v) \
+ (BIT_CLEAR_P0HI18Q_DESC_NUM(x) | BIT_P0HI18Q_DESC_NUM(v))
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/* 2 REG_PCIE_HISR0 (Offset 0x23B4) */
+
+#define BIT_PRE_TX_ERR_INT BIT(31)
+#define BIT_HISR1_IND BIT(11)
+#define BIT_TXDMAOK_CHANNEL15 BIT(7)
+#define BIT_TXDMAOK_CHANNEL14 BIT(6)
+#define BIT_TXDMAOK_CHANNEL3 BIT(5)
+#define BIT_TXDMAOK_CHANNEL2 BIT(4)
+#define BIT_TXDMAOK_CHANNEL1 BIT(3)
+#define BIT_TXDMAOK_CHANNEL0 BIT(2)
+
+/* 2 REG_PCIE_HISR1 (Offset 0x23BC) */
+
+#define BIT_CPU_MGQ_EARLY_INT BIT(6)
+#define BIT_PSTIMER_5 BIT(4)
+#define BIT_PSTIMER_4 BIT(3)
+#define BIT_PSTIMER_3 BIT(2)
+#define BIT_BB_STOPRX_INT BIT(0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/* 2 REG_P0HI8Q_HI9Q_TXBD_NUM (Offset 0x23C0) */
+
+#define BIT_P0HI9Q_FLAG BIT(30)
+
+#define BIT_SHIFT_P0HI9Q_DESC_MODE 28
+#define BIT_MASK_P0HI9Q_DESC_MODE 0x3
+#define BIT_P0HI9Q_DESC_MODE(x) \
+ (((x) & BIT_MASK_P0HI9Q_DESC_MODE) << BIT_SHIFT_P0HI9Q_DESC_MODE)
+#define BITS_P0HI9Q_DESC_MODE \
+ (BIT_MASK_P0HI9Q_DESC_MODE << BIT_SHIFT_P0HI9Q_DESC_MODE)
+#define BIT_CLEAR_P0HI9Q_DESC_MODE(x) ((x) & (~BITS_P0HI9Q_DESC_MODE))
+#define BIT_GET_P0HI9Q_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_P0HI9Q_DESC_MODE) & BIT_MASK_P0HI9Q_DESC_MODE)
+#define BIT_SET_P0HI9Q_DESC_MODE(x, v) \
+ (BIT_CLEAR_P0HI9Q_DESC_MODE(x) | BIT_P0HI9Q_DESC_MODE(v))
+
+#define BIT_SHIFT_P0HI9Q_DESC_NUM 16
+#define BIT_MASK_P0HI9Q_DESC_NUM 0xfff
+#define BIT_P0HI9Q_DESC_NUM(x) \
+ (((x) & BIT_MASK_P0HI9Q_DESC_NUM) << BIT_SHIFT_P0HI9Q_DESC_NUM)
+#define BITS_P0HI9Q_DESC_NUM \
+ (BIT_MASK_P0HI9Q_DESC_NUM << BIT_SHIFT_P0HI9Q_DESC_NUM)
+#define BIT_CLEAR_P0HI9Q_DESC_NUM(x) ((x) & (~BITS_P0HI9Q_DESC_NUM))
+#define BIT_GET_P0HI9Q_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_P0HI9Q_DESC_NUM) & BIT_MASK_P0HI9Q_DESC_NUM)
+#define BIT_SET_P0HI9Q_DESC_NUM(x, v) \
+ (BIT_CLEAR_P0HI9Q_DESC_NUM(x) | BIT_P0HI9Q_DESC_NUM(v))
+
+#define BIT_P0HI8Q_FLAG BIT(14)
+
+#define BIT_SHIFT_P0HI8Q_DESC_MODE 12
+#define BIT_MASK_P0HI8Q_DESC_MODE 0x3
+#define BIT_P0HI8Q_DESC_MODE(x) \
+ (((x) & BIT_MASK_P0HI8Q_DESC_MODE) << BIT_SHIFT_P0HI8Q_DESC_MODE)
+#define BITS_P0HI8Q_DESC_MODE \
+ (BIT_MASK_P0HI8Q_DESC_MODE << BIT_SHIFT_P0HI8Q_DESC_MODE)
+#define BIT_CLEAR_P0HI8Q_DESC_MODE(x) ((x) & (~BITS_P0HI8Q_DESC_MODE))
+#define BIT_GET_P0HI8Q_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_P0HI8Q_DESC_MODE) & BIT_MASK_P0HI8Q_DESC_MODE)
+#define BIT_SET_P0HI8Q_DESC_MODE(x, v) \
+ (BIT_CLEAR_P0HI8Q_DESC_MODE(x) | BIT_P0HI8Q_DESC_MODE(v))
+
+#define BIT_SHIFT_P0HI8Q_DESC_NUM 0
+#define BIT_MASK_P0HI8Q_DESC_NUM 0xfff
+#define BIT_P0HI8Q_DESC_NUM(x) \
+ (((x) & BIT_MASK_P0HI8Q_DESC_NUM) << BIT_SHIFT_P0HI8Q_DESC_NUM)
+#define BITS_P0HI8Q_DESC_NUM \
+ (BIT_MASK_P0HI8Q_DESC_NUM << BIT_SHIFT_P0HI8Q_DESC_NUM)
+#define BIT_CLEAR_P0HI8Q_DESC_NUM(x) ((x) & (~BITS_P0HI8Q_DESC_NUM))
+#define BIT_GET_P0HI8Q_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_P0HI8Q_DESC_NUM) & BIT_MASK_P0HI8Q_DESC_NUM)
+#define BIT_SET_P0HI8Q_DESC_NUM(x, v) \
+ (BIT_CLEAR_P0HI8Q_DESC_NUM(x) | BIT_P0HI8Q_DESC_NUM(v))
+
+/* 2 REG_P0HI10Q_HI11Q_TXBD_NUM (Offset 0x23C4) */
+
+#define BIT_P0HI11Q_FLAG BIT(30)
+
+#define BIT_SHIFT_P0HI11Q_DESC_MODE 28
+#define BIT_MASK_P0HI11Q_DESC_MODE 0x3
+#define BIT_P0HI11Q_DESC_MODE(x) \
+ (((x) & BIT_MASK_P0HI11Q_DESC_MODE) << BIT_SHIFT_P0HI11Q_DESC_MODE)
+#define BITS_P0HI11Q_DESC_MODE \
+ (BIT_MASK_P0HI11Q_DESC_MODE << BIT_SHIFT_P0HI11Q_DESC_MODE)
+#define BIT_CLEAR_P0HI11Q_DESC_MODE(x) ((x) & (~BITS_P0HI11Q_DESC_MODE))
+#define BIT_GET_P0HI11Q_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_P0HI11Q_DESC_MODE) & BIT_MASK_P0HI11Q_DESC_MODE)
+#define BIT_SET_P0HI11Q_DESC_MODE(x, v) \
+ (BIT_CLEAR_P0HI11Q_DESC_MODE(x) | BIT_P0HI11Q_DESC_MODE(v))
+
+#define BIT_SHIFT_P0HI11Q_DESC_NUM 16
+#define BIT_MASK_P0HI11Q_DESC_NUM 0xfff
+#define BIT_P0HI11Q_DESC_NUM(x) \
+ (((x) & BIT_MASK_P0HI11Q_DESC_NUM) << BIT_SHIFT_P0HI11Q_DESC_NUM)
+#define BITS_P0HI11Q_DESC_NUM \
+ (BIT_MASK_P0HI11Q_DESC_NUM << BIT_SHIFT_P0HI11Q_DESC_NUM)
+#define BIT_CLEAR_P0HI11Q_DESC_NUM(x) ((x) & (~BITS_P0HI11Q_DESC_NUM))
+#define BIT_GET_P0HI11Q_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_P0HI11Q_DESC_NUM) & BIT_MASK_P0HI11Q_DESC_NUM)
+#define BIT_SET_P0HI11Q_DESC_NUM(x, v) \
+ (BIT_CLEAR_P0HI11Q_DESC_NUM(x) | BIT_P0HI11Q_DESC_NUM(v))
+
+#define BIT_P0HI10Q_FLAG BIT(14)
+
+#define BIT_SHIFT_P0HI10Q_DESC_MODE 12
+#define BIT_MASK_P0HI10Q_DESC_MODE 0x3
+#define BIT_P0HI10Q_DESC_MODE(x) \
+ (((x) & BIT_MASK_P0HI10Q_DESC_MODE) << BIT_SHIFT_P0HI10Q_DESC_MODE)
+#define BITS_P0HI10Q_DESC_MODE \
+ (BIT_MASK_P0HI10Q_DESC_MODE << BIT_SHIFT_P0HI10Q_DESC_MODE)
+#define BIT_CLEAR_P0HI10Q_DESC_MODE(x) ((x) & (~BITS_P0HI10Q_DESC_MODE))
+#define BIT_GET_P0HI10Q_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_P0HI10Q_DESC_MODE) & BIT_MASK_P0HI10Q_DESC_MODE)
+#define BIT_SET_P0HI10Q_DESC_MODE(x, v) \
+ (BIT_CLEAR_P0HI10Q_DESC_MODE(x) | BIT_P0HI10Q_DESC_MODE(v))
+
+#define BIT_SHIFT_P0HI10Q_DESC_NUM 0
+#define BIT_MASK_P0HI10Q_DESC_NUM 0xfff
+#define BIT_P0HI10Q_DESC_NUM(x) \
+ (((x) & BIT_MASK_P0HI10Q_DESC_NUM) << BIT_SHIFT_P0HI10Q_DESC_NUM)
+#define BITS_P0HI10Q_DESC_NUM \
+ (BIT_MASK_P0HI10Q_DESC_NUM << BIT_SHIFT_P0HI10Q_DESC_NUM)
+#define BIT_CLEAR_P0HI10Q_DESC_NUM(x) ((x) & (~BITS_P0HI10Q_DESC_NUM))
+#define BIT_GET_P0HI10Q_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_P0HI10Q_DESC_NUM) & BIT_MASK_P0HI10Q_DESC_NUM)
+#define BIT_SET_P0HI10Q_DESC_NUM(x, v) \
+ (BIT_CLEAR_P0HI10Q_DESC_NUM(x) | BIT_P0HI10Q_DESC_NUM(v))
+
+/* 2 REG_P0HI12Q_HI13Q_TXBD_NUM (Offset 0x23C8) */
+
+#define BIT_P0HI13Q_FLAG BIT(30)
+
+#define BIT_SHIFT_P0HI13Q_DESC_MODE 28
+#define BIT_MASK_P0HI13Q_DESC_MODE 0x3
+#define BIT_P0HI13Q_DESC_MODE(x) \
+ (((x) & BIT_MASK_P0HI13Q_DESC_MODE) << BIT_SHIFT_P0HI13Q_DESC_MODE)
+#define BITS_P0HI13Q_DESC_MODE \
+ (BIT_MASK_P0HI13Q_DESC_MODE << BIT_SHIFT_P0HI13Q_DESC_MODE)
+#define BIT_CLEAR_P0HI13Q_DESC_MODE(x) ((x) & (~BITS_P0HI13Q_DESC_MODE))
+#define BIT_GET_P0HI13Q_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_P0HI13Q_DESC_MODE) & BIT_MASK_P0HI13Q_DESC_MODE)
+#define BIT_SET_P0HI13Q_DESC_MODE(x, v) \
+ (BIT_CLEAR_P0HI13Q_DESC_MODE(x) | BIT_P0HI13Q_DESC_MODE(v))
+
+#define BIT_SHIFT_P0HI13Q_DESC_NUM 16
+#define BIT_MASK_P0HI13Q_DESC_NUM 0xfff
+#define BIT_P0HI13Q_DESC_NUM(x) \
+ (((x) & BIT_MASK_P0HI13Q_DESC_NUM) << BIT_SHIFT_P0HI13Q_DESC_NUM)
+#define BITS_P0HI13Q_DESC_NUM \
+ (BIT_MASK_P0HI13Q_DESC_NUM << BIT_SHIFT_P0HI13Q_DESC_NUM)
+#define BIT_CLEAR_P0HI13Q_DESC_NUM(x) ((x) & (~BITS_P0HI13Q_DESC_NUM))
+#define BIT_GET_P0HI13Q_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_P0HI13Q_DESC_NUM) & BIT_MASK_P0HI13Q_DESC_NUM)
+#define BIT_SET_P0HI13Q_DESC_NUM(x, v) \
+ (BIT_CLEAR_P0HI13Q_DESC_NUM(x) | BIT_P0HI13Q_DESC_NUM(v))
+
+#define BIT_P0HI12Q_FLAG BIT(14)
+
+#define BIT_SHIFT_P0HI12Q_DESC_MODE 12
+#define BIT_MASK_P0HI12Q_DESC_MODE 0x3
+#define BIT_P0HI12Q_DESC_MODE(x) \
+ (((x) & BIT_MASK_P0HI12Q_DESC_MODE) << BIT_SHIFT_P0HI12Q_DESC_MODE)
+#define BITS_P0HI12Q_DESC_MODE \
+ (BIT_MASK_P0HI12Q_DESC_MODE << BIT_SHIFT_P0HI12Q_DESC_MODE)
+#define BIT_CLEAR_P0HI12Q_DESC_MODE(x) ((x) & (~BITS_P0HI12Q_DESC_MODE))
+#define BIT_GET_P0HI12Q_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_P0HI12Q_DESC_MODE) & BIT_MASK_P0HI12Q_DESC_MODE)
+#define BIT_SET_P0HI12Q_DESC_MODE(x, v) \
+ (BIT_CLEAR_P0HI12Q_DESC_MODE(x) | BIT_P0HI12Q_DESC_MODE(v))
+
+#define BIT_SHIFT_P0HI12Q_DESC_NUM 0
+#define BIT_MASK_P0HI12Q_DESC_NUM 0xfff
+#define BIT_P0HI12Q_DESC_NUM(x) \
+ (((x) & BIT_MASK_P0HI12Q_DESC_NUM) << BIT_SHIFT_P0HI12Q_DESC_NUM)
+#define BITS_P0HI12Q_DESC_NUM \
+ (BIT_MASK_P0HI12Q_DESC_NUM << BIT_SHIFT_P0HI12Q_DESC_NUM)
+#define BIT_CLEAR_P0HI12Q_DESC_NUM(x) ((x) & (~BITS_P0HI12Q_DESC_NUM))
+#define BIT_GET_P0HI12Q_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_P0HI12Q_DESC_NUM) & BIT_MASK_P0HI12Q_DESC_NUM)
+#define BIT_SET_P0HI12Q_DESC_NUM(x, v) \
+ (BIT_CLEAR_P0HI12Q_DESC_NUM(x) | BIT_P0HI12Q_DESC_NUM(v))
+
+/* 2 REG_P0HI14Q_HI15Q_TXBD_NUM (Offset 0x23CC) */
+
+#define BIT_P0HI15Q_FLAG BIT(30)
+
+#define BIT_SHIFT_P0HI15Q_DESC_MODE 28
+#define BIT_MASK_P0HI15Q_DESC_MODE 0x3
+#define BIT_P0HI15Q_DESC_MODE(x) \
+ (((x) & BIT_MASK_P0HI15Q_DESC_MODE) << BIT_SHIFT_P0HI15Q_DESC_MODE)
+#define BITS_P0HI15Q_DESC_MODE \
+ (BIT_MASK_P0HI15Q_DESC_MODE << BIT_SHIFT_P0HI15Q_DESC_MODE)
+#define BIT_CLEAR_P0HI15Q_DESC_MODE(x) ((x) & (~BITS_P0HI15Q_DESC_MODE))
+#define BIT_GET_P0HI15Q_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_P0HI15Q_DESC_MODE) & BIT_MASK_P0HI15Q_DESC_MODE)
+#define BIT_SET_P0HI15Q_DESC_MODE(x, v) \
+ (BIT_CLEAR_P0HI15Q_DESC_MODE(x) | BIT_P0HI15Q_DESC_MODE(v))
+
+#define BIT_SHIFT_P0HI15Q_DESC_NUM 16
+#define BIT_MASK_P0HI15Q_DESC_NUM 0xfff
+#define BIT_P0HI15Q_DESC_NUM(x) \
+ (((x) & BIT_MASK_P0HI15Q_DESC_NUM) << BIT_SHIFT_P0HI15Q_DESC_NUM)
+#define BITS_P0HI15Q_DESC_NUM \
+ (BIT_MASK_P0HI15Q_DESC_NUM << BIT_SHIFT_P0HI15Q_DESC_NUM)
+#define BIT_CLEAR_P0HI15Q_DESC_NUM(x) ((x) & (~BITS_P0HI15Q_DESC_NUM))
+#define BIT_GET_P0HI15Q_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_P0HI15Q_DESC_NUM) & BIT_MASK_P0HI15Q_DESC_NUM)
+#define BIT_SET_P0HI15Q_DESC_NUM(x, v) \
+ (BIT_CLEAR_P0HI15Q_DESC_NUM(x) | BIT_P0HI15Q_DESC_NUM(v))
+
+#define BIT_P0HI14Q_FLAG BIT(14)
+
+#define BIT_SHIFT_P0HI14Q_DESC_MODE 12
+#define BIT_MASK_P0HI14Q_DESC_MODE 0x3
+#define BIT_P0HI14Q_DESC_MODE(x) \
+ (((x) & BIT_MASK_P0HI14Q_DESC_MODE) << BIT_SHIFT_P0HI14Q_DESC_MODE)
+#define BITS_P0HI14Q_DESC_MODE \
+ (BIT_MASK_P0HI14Q_DESC_MODE << BIT_SHIFT_P0HI14Q_DESC_MODE)
+#define BIT_CLEAR_P0HI14Q_DESC_MODE(x) ((x) & (~BITS_P0HI14Q_DESC_MODE))
+#define BIT_GET_P0HI14Q_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_P0HI14Q_DESC_MODE) & BIT_MASK_P0HI14Q_DESC_MODE)
+#define BIT_SET_P0HI14Q_DESC_MODE(x, v) \
+ (BIT_CLEAR_P0HI14Q_DESC_MODE(x) | BIT_P0HI14Q_DESC_MODE(v))
+
+#define BIT_SHIFT_P0HI14Q_DESC_NUM 0
+#define BIT_MASK_P0HI14Q_DESC_NUM 0xfff
+#define BIT_P0HI14Q_DESC_NUM(x) \
+ (((x) & BIT_MASK_P0HI14Q_DESC_NUM) << BIT_SHIFT_P0HI14Q_DESC_NUM)
+#define BITS_P0HI14Q_DESC_NUM \
+ (BIT_MASK_P0HI14Q_DESC_NUM << BIT_SHIFT_P0HI14Q_DESC_NUM)
+#define BIT_CLEAR_P0HI14Q_DESC_NUM(x) ((x) & (~BITS_P0HI14Q_DESC_NUM))
+#define BIT_GET_P0HI14Q_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_P0HI14Q_DESC_NUM) & BIT_MASK_P0HI14Q_DESC_NUM)
+#define BIT_SET_P0HI14Q_DESC_NUM(x, v) \
+ (BIT_CLEAR_P0HI14Q_DESC_NUM(x) | BIT_P0HI14Q_DESC_NUM(v))
+
+/* 2 REG_ACH6_ACH7_TXBD_NUM (Offset 0x23F0) */
+
+#define BIT_PCIE_ACH7_FLAG BIT(30)
+
+#define BIT_SHIFT_ACH7_DESC_MODE 28
+#define BIT_MASK_ACH7_DESC_MODE 0x3
+#define BIT_ACH7_DESC_MODE(x) \
+ (((x) & BIT_MASK_ACH7_DESC_MODE) << BIT_SHIFT_ACH7_DESC_MODE)
+#define BITS_ACH7_DESC_MODE \
+ (BIT_MASK_ACH7_DESC_MODE << BIT_SHIFT_ACH7_DESC_MODE)
+#define BIT_CLEAR_ACH7_DESC_MODE(x) ((x) & (~BITS_ACH7_DESC_MODE))
+#define BIT_GET_ACH7_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_ACH7_DESC_MODE) & BIT_MASK_ACH7_DESC_MODE)
+#define BIT_SET_ACH7_DESC_MODE(x, v) \
+ (BIT_CLEAR_ACH7_DESC_MODE(x) | BIT_ACH7_DESC_MODE(v))
+
+#define BIT_SHIFT_ACH7_DESC_NUM 16
+#define BIT_MASK_ACH7_DESC_NUM 0xfff
+#define BIT_ACH7_DESC_NUM(x) \
+ (((x) & BIT_MASK_ACH7_DESC_NUM) << BIT_SHIFT_ACH7_DESC_NUM)
+#define BITS_ACH7_DESC_NUM (BIT_MASK_ACH7_DESC_NUM << BIT_SHIFT_ACH7_DESC_NUM)
+#define BIT_CLEAR_ACH7_DESC_NUM(x) ((x) & (~BITS_ACH7_DESC_NUM))
+#define BIT_GET_ACH7_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_ACH7_DESC_NUM) & BIT_MASK_ACH7_DESC_NUM)
+#define BIT_SET_ACH7_DESC_NUM(x, v) \
+ (BIT_CLEAR_ACH7_DESC_NUM(x) | BIT_ACH7_DESC_NUM(v))
+
+#define BIT_PCIE_ACH6_FLAG BIT(14)
+
+#define BIT_SHIFT_ACH6_DESC_MODE 12
+#define BIT_MASK_ACH6_DESC_MODE 0x3
+#define BIT_ACH6_DESC_MODE(x) \
+ (((x) & BIT_MASK_ACH6_DESC_MODE) << BIT_SHIFT_ACH6_DESC_MODE)
+#define BITS_ACH6_DESC_MODE \
+ (BIT_MASK_ACH6_DESC_MODE << BIT_SHIFT_ACH6_DESC_MODE)
+#define BIT_CLEAR_ACH6_DESC_MODE(x) ((x) & (~BITS_ACH6_DESC_MODE))
+#define BIT_GET_ACH6_DESC_MODE(x) \
+ (((x) >> BIT_SHIFT_ACH6_DESC_MODE) & BIT_MASK_ACH6_DESC_MODE)
+#define BIT_SET_ACH6_DESC_MODE(x, v) \
+ (BIT_CLEAR_ACH6_DESC_MODE(x) | BIT_ACH6_DESC_MODE(v))
+
+#define BIT_SHIFT_ACH6_DESC_NUM 0
+#define BIT_MASK_ACH6_DESC_NUM 0xfff
+#define BIT_ACH6_DESC_NUM(x) \
+ (((x) & BIT_MASK_ACH6_DESC_NUM) << BIT_SHIFT_ACH6_DESC_NUM)
+#define BITS_ACH6_DESC_NUM (BIT_MASK_ACH6_DESC_NUM << BIT_SHIFT_ACH6_DESC_NUM)
+#define BIT_CLEAR_ACH6_DESC_NUM(x) ((x) & (~BITS_ACH6_DESC_NUM))
+#define BIT_GET_ACH6_DESC_NUM(x) \
+ (((x) >> BIT_SHIFT_ACH6_DESC_NUM) & BIT_MASK_ACH6_DESC_NUM)
+#define BIT_SET_ACH6_DESC_NUM(x, v) \
+ (BIT_CLEAR_ACH6_DESC_NUM(x) | BIT_ACH6_DESC_NUM(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_0 (Offset 0x3200) */
+
+#define BIT_CH0_INT_EN BIT(31)
+
+#define BIT_SHIFT_CH0_HIGH_TH 16
+#define BIT_MASK_CH0_HIGH_TH 0xfff
+#define BIT_CH0_HIGH_TH(x) \
+ (((x) & BIT_MASK_CH0_HIGH_TH) << BIT_SHIFT_CH0_HIGH_TH)
+#define BITS_CH0_HIGH_TH (BIT_MASK_CH0_HIGH_TH << BIT_SHIFT_CH0_HIGH_TH)
+#define BIT_CLEAR_CH0_HIGH_TH(x) ((x) & (~BITS_CH0_HIGH_TH))
+#define BIT_GET_CH0_HIGH_TH(x) \
+ (((x) >> BIT_SHIFT_CH0_HIGH_TH) & BIT_MASK_CH0_HIGH_TH)
+#define BIT_SET_CH0_HIGH_TH(x, v) \
+ (BIT_CLEAR_CH0_HIGH_TH(x) | BIT_CH0_HIGH_TH(v))
+
+#define BIT_SHIFT_CH0_LOW_TH 0
+#define BIT_MASK_CH0_LOW_TH 0xfff
+#define BIT_CH0_LOW_TH(x) (((x) & BIT_MASK_CH0_LOW_TH) << BIT_SHIFT_CH0_LOW_TH)
+#define BITS_CH0_LOW_TH (BIT_MASK_CH0_LOW_TH << BIT_SHIFT_CH0_LOW_TH)
+#define BIT_CLEAR_CH0_LOW_TH(x) ((x) & (~BITS_CH0_LOW_TH))
+#define BIT_GET_CH0_LOW_TH(x) \
+ (((x) >> BIT_SHIFT_CH0_LOW_TH) & BIT_MASK_CH0_LOW_TH)
+#define BIT_SET_CH0_LOW_TH(x, v) (BIT_CLEAR_CH0_LOW_TH(x) | BIT_CH0_LOW_TH(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_1 (Offset 0x3204) */
+
+#define BIT_CH1_INT_EN BIT(31)
+
+#define BIT_SHIFT_CH1_HIGH_TH 16
+#define BIT_MASK_CH1_HIGH_TH 0xfff
+#define BIT_CH1_HIGH_TH(x) \
+ (((x) & BIT_MASK_CH1_HIGH_TH) << BIT_SHIFT_CH1_HIGH_TH)
+#define BITS_CH1_HIGH_TH (BIT_MASK_CH1_HIGH_TH << BIT_SHIFT_CH1_HIGH_TH)
+#define BIT_CLEAR_CH1_HIGH_TH(x) ((x) & (~BITS_CH1_HIGH_TH))
+#define BIT_GET_CH1_HIGH_TH(x) \
+ (((x) >> BIT_SHIFT_CH1_HIGH_TH) & BIT_MASK_CH1_HIGH_TH)
+#define BIT_SET_CH1_HIGH_TH(x, v) \
+ (BIT_CLEAR_CH1_HIGH_TH(x) | BIT_CH1_HIGH_TH(v))
+
+#define BIT_SHIFT_CH1_LOW_TH 0
+#define BIT_MASK_CH1_LOW_TH 0xfff
+#define BIT_CH1_LOW_TH(x) (((x) & BIT_MASK_CH1_LOW_TH) << BIT_SHIFT_CH1_LOW_TH)
+#define BITS_CH1_LOW_TH (BIT_MASK_CH1_LOW_TH << BIT_SHIFT_CH1_LOW_TH)
+#define BIT_CLEAR_CH1_LOW_TH(x) ((x) & (~BITS_CH1_LOW_TH))
+#define BIT_GET_CH1_LOW_TH(x) \
+ (((x) >> BIT_SHIFT_CH1_LOW_TH) & BIT_MASK_CH1_LOW_TH)
+#define BIT_SET_CH1_LOW_TH(x, v) (BIT_CLEAR_CH1_LOW_TH(x) | BIT_CH1_LOW_TH(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_2 (Offset 0x3208) */
+
+#define BIT_CH2_INT_EN BIT(31)
+
+#define BIT_SHIFT_CH2_HIGH_TH 16
+#define BIT_MASK_CH2_HIGH_TH 0xfff
+#define BIT_CH2_HIGH_TH(x) \
+ (((x) & BIT_MASK_CH2_HIGH_TH) << BIT_SHIFT_CH2_HIGH_TH)
+#define BITS_CH2_HIGH_TH (BIT_MASK_CH2_HIGH_TH << BIT_SHIFT_CH2_HIGH_TH)
+#define BIT_CLEAR_CH2_HIGH_TH(x) ((x) & (~BITS_CH2_HIGH_TH))
+#define BIT_GET_CH2_HIGH_TH(x) \
+ (((x) >> BIT_SHIFT_CH2_HIGH_TH) & BIT_MASK_CH2_HIGH_TH)
+#define BIT_SET_CH2_HIGH_TH(x, v) \
+ (BIT_CLEAR_CH2_HIGH_TH(x) | BIT_CH2_HIGH_TH(v))
+
+#define BIT_SHIFT_CH2_LOW_TH 0
+#define BIT_MASK_CH2_LOW_TH 0xfff
+#define BIT_CH2_LOW_TH(x) (((x) & BIT_MASK_CH2_LOW_TH) << BIT_SHIFT_CH2_LOW_TH)
+#define BITS_CH2_LOW_TH (BIT_MASK_CH2_LOW_TH << BIT_SHIFT_CH2_LOW_TH)
+#define BIT_CLEAR_CH2_LOW_TH(x) ((x) & (~BITS_CH2_LOW_TH))
+#define BIT_GET_CH2_LOW_TH(x) \
+ (((x) >> BIT_SHIFT_CH2_LOW_TH) & BIT_MASK_CH2_LOW_TH)
+#define BIT_SET_CH2_LOW_TH(x, v) (BIT_CLEAR_CH2_LOW_TH(x) | BIT_CH2_LOW_TH(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_3 (Offset 0x320C) */
+
+#define BIT_CH3_INT_EN BIT(31)
+
+#define BIT_SHIFT_CH3_HIGH_TH 16
+#define BIT_MASK_CH3_HIGH_TH 0xfff
+#define BIT_CH3_HIGH_TH(x) \
+ (((x) & BIT_MASK_CH3_HIGH_TH) << BIT_SHIFT_CH3_HIGH_TH)
+#define BITS_CH3_HIGH_TH (BIT_MASK_CH3_HIGH_TH << BIT_SHIFT_CH3_HIGH_TH)
+#define BIT_CLEAR_CH3_HIGH_TH(x) ((x) & (~BITS_CH3_HIGH_TH))
+#define BIT_GET_CH3_HIGH_TH(x) \
+ (((x) >> BIT_SHIFT_CH3_HIGH_TH) & BIT_MASK_CH3_HIGH_TH)
+#define BIT_SET_CH3_HIGH_TH(x, v) \
+ (BIT_CLEAR_CH3_HIGH_TH(x) | BIT_CH3_HIGH_TH(v))
+
+#define BIT_SHIFT_CH3_LOW_TH 0
+#define BIT_MASK_CH3_LOW_TH 0xfff
+#define BIT_CH3_LOW_TH(x) (((x) & BIT_MASK_CH3_LOW_TH) << BIT_SHIFT_CH3_LOW_TH)
+#define BITS_CH3_LOW_TH (BIT_MASK_CH3_LOW_TH << BIT_SHIFT_CH3_LOW_TH)
+#define BIT_CLEAR_CH3_LOW_TH(x) ((x) & (~BITS_CH3_LOW_TH))
+#define BIT_GET_CH3_LOW_TH(x) \
+ (((x) >> BIT_SHIFT_CH3_LOW_TH) & BIT_MASK_CH3_LOW_TH)
+#define BIT_SET_CH3_LOW_TH(x, v) (BIT_CLEAR_CH3_LOW_TH(x) | BIT_CH3_LOW_TH(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_4 (Offset 0x3210) */
+
+#define BIT_CH4_INT_EN BIT(31)
+
+#define BIT_SHIFT_CH4_HIGH_TH 16
+#define BIT_MASK_CH4_HIGH_TH 0xfff
+#define BIT_CH4_HIGH_TH(x) \
+ (((x) & BIT_MASK_CH4_HIGH_TH) << BIT_SHIFT_CH4_HIGH_TH)
+#define BITS_CH4_HIGH_TH (BIT_MASK_CH4_HIGH_TH << BIT_SHIFT_CH4_HIGH_TH)
+#define BIT_CLEAR_CH4_HIGH_TH(x) ((x) & (~BITS_CH4_HIGH_TH))
+#define BIT_GET_CH4_HIGH_TH(x) \
+ (((x) >> BIT_SHIFT_CH4_HIGH_TH) & BIT_MASK_CH4_HIGH_TH)
+#define BIT_SET_CH4_HIGH_TH(x, v) \
+ (BIT_CLEAR_CH4_HIGH_TH(x) | BIT_CH4_HIGH_TH(v))
+
+#define BIT_SHIFT_CH4_LOW_TH 0
+#define BIT_MASK_CH4_LOW_TH 0xfff
+#define BIT_CH4_LOW_TH(x) (((x) & BIT_MASK_CH4_LOW_TH) << BIT_SHIFT_CH4_LOW_TH)
+#define BITS_CH4_LOW_TH (BIT_MASK_CH4_LOW_TH << BIT_SHIFT_CH4_LOW_TH)
+#define BIT_CLEAR_CH4_LOW_TH(x) ((x) & (~BITS_CH4_LOW_TH))
+#define BIT_GET_CH4_LOW_TH(x) \
+ (((x) >> BIT_SHIFT_CH4_LOW_TH) & BIT_MASK_CH4_LOW_TH)
+#define BIT_SET_CH4_LOW_TH(x, v) (BIT_CLEAR_CH4_LOW_TH(x) | BIT_CH4_LOW_TH(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_5 (Offset 0x3214) */
+
+#define BIT_CH5_INT_EN BIT(31)
+
+#define BIT_SHIFT_CH5_HIGH_TH 16
+#define BIT_MASK_CH5_HIGH_TH 0xfff
+#define BIT_CH5_HIGH_TH(x) \
+ (((x) & BIT_MASK_CH5_HIGH_TH) << BIT_SHIFT_CH5_HIGH_TH)
+#define BITS_CH5_HIGH_TH (BIT_MASK_CH5_HIGH_TH << BIT_SHIFT_CH5_HIGH_TH)
+#define BIT_CLEAR_CH5_HIGH_TH(x) ((x) & (~BITS_CH5_HIGH_TH))
+#define BIT_GET_CH5_HIGH_TH(x) \
+ (((x) >> BIT_SHIFT_CH5_HIGH_TH) & BIT_MASK_CH5_HIGH_TH)
+#define BIT_SET_CH5_HIGH_TH(x, v) \
+ (BIT_CLEAR_CH5_HIGH_TH(x) | BIT_CH5_HIGH_TH(v))
+
+#define BIT_SHIFT_CH5_LOW_TH 0
+#define BIT_MASK_CH5_LOW_TH 0xfff
+#define BIT_CH5_LOW_TH(x) (((x) & BIT_MASK_CH5_LOW_TH) << BIT_SHIFT_CH5_LOW_TH)
+#define BITS_CH5_LOW_TH (BIT_MASK_CH5_LOW_TH << BIT_SHIFT_CH5_LOW_TH)
+#define BIT_CLEAR_CH5_LOW_TH(x) ((x) & (~BITS_CH5_LOW_TH))
+#define BIT_GET_CH5_LOW_TH(x) \
+ (((x) >> BIT_SHIFT_CH5_LOW_TH) & BIT_MASK_CH5_LOW_TH)
+#define BIT_SET_CH5_LOW_TH(x, v) (BIT_CLEAR_CH5_LOW_TH(x) | BIT_CH5_LOW_TH(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_6 (Offset 0x3218) */
+
+#define BIT_CH6_INT_EN BIT(31)
+
+#define BIT_SHIFT_CH6_HIGH_TH 16
+#define BIT_MASK_CH6_HIGH_TH 0xfff
+#define BIT_CH6_HIGH_TH(x) \
+ (((x) & BIT_MASK_CH6_HIGH_TH) << BIT_SHIFT_CH6_HIGH_TH)
+#define BITS_CH6_HIGH_TH (BIT_MASK_CH6_HIGH_TH << BIT_SHIFT_CH6_HIGH_TH)
+#define BIT_CLEAR_CH6_HIGH_TH(x) ((x) & (~BITS_CH6_HIGH_TH))
+#define BIT_GET_CH6_HIGH_TH(x) \
+ (((x) >> BIT_SHIFT_CH6_HIGH_TH) & BIT_MASK_CH6_HIGH_TH)
+#define BIT_SET_CH6_HIGH_TH(x, v) \
+ (BIT_CLEAR_CH6_HIGH_TH(x) | BIT_CH6_HIGH_TH(v))
+
+#define BIT_SHIFT_CH6_LOW_TH 0
+#define BIT_MASK_CH6_LOW_TH 0xfff
+#define BIT_CH6_LOW_TH(x) (((x) & BIT_MASK_CH6_LOW_TH) << BIT_SHIFT_CH6_LOW_TH)
+#define BITS_CH6_LOW_TH (BIT_MASK_CH6_LOW_TH << BIT_SHIFT_CH6_LOW_TH)
+#define BIT_CLEAR_CH6_LOW_TH(x) ((x) & (~BITS_CH6_LOW_TH))
+#define BIT_GET_CH6_LOW_TH(x) \
+ (((x) >> BIT_SHIFT_CH6_LOW_TH) & BIT_MASK_CH6_LOW_TH)
+#define BIT_SET_CH6_LOW_TH(x, v) (BIT_CLEAR_CH6_LOW_TH(x) | BIT_CH6_LOW_TH(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_7 (Offset 0x321C) */
+
+#define BIT_CH7_INT_EN BIT(31)
+
+#define BIT_SHIFT_CH7_HIGH_TH 16
+#define BIT_MASK_CH7_HIGH_TH 0xfff
+#define BIT_CH7_HIGH_TH(x) \
+ (((x) & BIT_MASK_CH7_HIGH_TH) << BIT_SHIFT_CH7_HIGH_TH)
+#define BITS_CH7_HIGH_TH (BIT_MASK_CH7_HIGH_TH << BIT_SHIFT_CH7_HIGH_TH)
+#define BIT_CLEAR_CH7_HIGH_TH(x) ((x) & (~BITS_CH7_HIGH_TH))
+#define BIT_GET_CH7_HIGH_TH(x) \
+ (((x) >> BIT_SHIFT_CH7_HIGH_TH) & BIT_MASK_CH7_HIGH_TH)
+#define BIT_SET_CH7_HIGH_TH(x, v) \
+ (BIT_CLEAR_CH7_HIGH_TH(x) | BIT_CH7_HIGH_TH(v))
+
+#define BIT_SHIFT_CH7_LOW_TH 0
+#define BIT_MASK_CH7_LOW_TH 0xfff
+#define BIT_CH7_LOW_TH(x) (((x) & BIT_MASK_CH7_LOW_TH) << BIT_SHIFT_CH7_LOW_TH)
+#define BITS_CH7_LOW_TH (BIT_MASK_CH7_LOW_TH << BIT_SHIFT_CH7_LOW_TH)
+#define BIT_CLEAR_CH7_LOW_TH(x) ((x) & (~BITS_CH7_LOW_TH))
+#define BIT_GET_CH7_LOW_TH(x) \
+ (((x) >> BIT_SHIFT_CH7_LOW_TH) & BIT_MASK_CH7_LOW_TH)
+#define BIT_SET_CH7_LOW_TH(x, v) (BIT_CLEAR_CH7_LOW_TH(x) | BIT_CH7_LOW_TH(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_8 (Offset 0x3220) */
+
+#define BIT_CH8_INT_EN BIT(31)
+
+#define BIT_SHIFT_CH8_HIGH_TH 16
+#define BIT_MASK_CH8_HIGH_TH 0xfff
+#define BIT_CH8_HIGH_TH(x) \
+ (((x) & BIT_MASK_CH8_HIGH_TH) << BIT_SHIFT_CH8_HIGH_TH)
+#define BITS_CH8_HIGH_TH (BIT_MASK_CH8_HIGH_TH << BIT_SHIFT_CH8_HIGH_TH)
+#define BIT_CLEAR_CH8_HIGH_TH(x) ((x) & (~BITS_CH8_HIGH_TH))
+#define BIT_GET_CH8_HIGH_TH(x) \
+ (((x) >> BIT_SHIFT_CH8_HIGH_TH) & BIT_MASK_CH8_HIGH_TH)
+#define BIT_SET_CH8_HIGH_TH(x, v) \
+ (BIT_CLEAR_CH8_HIGH_TH(x) | BIT_CH8_HIGH_TH(v))
+
+#define BIT_SHIFT_CH8_LOW_TH 0
+#define BIT_MASK_CH8_LOW_TH 0xfff
+#define BIT_CH8_LOW_TH(x) (((x) & BIT_MASK_CH8_LOW_TH) << BIT_SHIFT_CH8_LOW_TH)
+#define BITS_CH8_LOW_TH (BIT_MASK_CH8_LOW_TH << BIT_SHIFT_CH8_LOW_TH)
+#define BIT_CLEAR_CH8_LOW_TH(x) ((x) & (~BITS_CH8_LOW_TH))
+#define BIT_GET_CH8_LOW_TH(x) \
+ (((x) >> BIT_SHIFT_CH8_LOW_TH) & BIT_MASK_CH8_LOW_TH)
+#define BIT_SET_CH8_LOW_TH(x, v) (BIT_CLEAR_CH8_LOW_TH(x) | BIT_CH8_LOW_TH(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_9 (Offset 0x3224) */
+
+#define BIT_CH9_INT_EN BIT(31)
+
+#define BIT_SHIFT_CH9_HIGH_TH 16
+#define BIT_MASK_CH9_HIGH_TH 0xfff
+#define BIT_CH9_HIGH_TH(x) \
+ (((x) & BIT_MASK_CH9_HIGH_TH) << BIT_SHIFT_CH9_HIGH_TH)
+#define BITS_CH9_HIGH_TH (BIT_MASK_CH9_HIGH_TH << BIT_SHIFT_CH9_HIGH_TH)
+#define BIT_CLEAR_CH9_HIGH_TH(x) ((x) & (~BITS_CH9_HIGH_TH))
+#define BIT_GET_CH9_HIGH_TH(x) \
+ (((x) >> BIT_SHIFT_CH9_HIGH_TH) & BIT_MASK_CH9_HIGH_TH)
+#define BIT_SET_CH9_HIGH_TH(x, v) \
+ (BIT_CLEAR_CH9_HIGH_TH(x) | BIT_CH9_HIGH_TH(v))
+
+#define BIT_SHIFT_CH9_LOW_TH 0
+#define BIT_MASK_CH9_LOW_TH 0xfff
+#define BIT_CH9_LOW_TH(x) (((x) & BIT_MASK_CH9_LOW_TH) << BIT_SHIFT_CH9_LOW_TH)
+#define BITS_CH9_LOW_TH (BIT_MASK_CH9_LOW_TH << BIT_SHIFT_CH9_LOW_TH)
+#define BIT_CLEAR_CH9_LOW_TH(x) ((x) & (~BITS_CH9_LOW_TH))
+#define BIT_GET_CH9_LOW_TH(x) \
+ (((x) >> BIT_SHIFT_CH9_LOW_TH) & BIT_MASK_CH9_LOW_TH)
+#define BIT_SET_CH9_LOW_TH(x, v) (BIT_CLEAR_CH9_LOW_TH(x) | BIT_CH9_LOW_TH(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_10 (Offset 0x3228) */
+
+#define BIT_CH10_INT_EN BIT(31)
+
+#define BIT_SHIFT_CH10_HIGH_TH 16
+#define BIT_MASK_CH10_HIGH_TH 0xfff
+#define BIT_CH10_HIGH_TH(x) \
+ (((x) & BIT_MASK_CH10_HIGH_TH) << BIT_SHIFT_CH10_HIGH_TH)
+#define BITS_CH10_HIGH_TH (BIT_MASK_CH10_HIGH_TH << BIT_SHIFT_CH10_HIGH_TH)
+#define BIT_CLEAR_CH10_HIGH_TH(x) ((x) & (~BITS_CH10_HIGH_TH))
+#define BIT_GET_CH10_HIGH_TH(x) \
+ (((x) >> BIT_SHIFT_CH10_HIGH_TH) & BIT_MASK_CH10_HIGH_TH)
+#define BIT_SET_CH10_HIGH_TH(x, v) \
+ (BIT_CLEAR_CH10_HIGH_TH(x) | BIT_CH10_HIGH_TH(v))
+
+#define BIT_SHIFT_CH10_LOW_TH 0
+#define BIT_MASK_CH10_LOW_TH 0xfff
+#define BIT_CH10_LOW_TH(x) \
+ (((x) & BIT_MASK_CH10_LOW_TH) << BIT_SHIFT_CH10_LOW_TH)
+#define BITS_CH10_LOW_TH (BIT_MASK_CH10_LOW_TH << BIT_SHIFT_CH10_LOW_TH)
+#define BIT_CLEAR_CH10_LOW_TH(x) ((x) & (~BITS_CH10_LOW_TH))
+#define BIT_GET_CH10_LOW_TH(x) \
+ (((x) >> BIT_SHIFT_CH10_LOW_TH) & BIT_MASK_CH10_LOW_TH)
+#define BIT_SET_CH10_LOW_TH(x, v) \
+ (BIT_CLEAR_CH10_LOW_TH(x) | BIT_CH10_LOW_TH(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_11 (Offset 0x322C) */
+
+#define BIT_CH11_INT_EN BIT(31)
+
+#define BIT_SHIFT_CH11_HIGH_TH 16
+#define BIT_MASK_CH11_HIGH_TH 0xfff
+#define BIT_CH11_HIGH_TH(x) \
+ (((x) & BIT_MASK_CH11_HIGH_TH) << BIT_SHIFT_CH11_HIGH_TH)
+#define BITS_CH11_HIGH_TH (BIT_MASK_CH11_HIGH_TH << BIT_SHIFT_CH11_HIGH_TH)
+#define BIT_CLEAR_CH11_HIGH_TH(x) ((x) & (~BITS_CH11_HIGH_TH))
+#define BIT_GET_CH11_HIGH_TH(x) \
+ (((x) >> BIT_SHIFT_CH11_HIGH_TH) & BIT_MASK_CH11_HIGH_TH)
+#define BIT_SET_CH11_HIGH_TH(x, v) \
+ (BIT_CLEAR_CH11_HIGH_TH(x) | BIT_CH11_HIGH_TH(v))
+
+#define BIT_SHIFT_CH11_LOW_TH 0
+#define BIT_MASK_CH11_LOW_TH 0xfff
+#define BIT_CH11_LOW_TH(x) \
+ (((x) & BIT_MASK_CH11_LOW_TH) << BIT_SHIFT_CH11_LOW_TH)
+#define BITS_CH11_LOW_TH (BIT_MASK_CH11_LOW_TH << BIT_SHIFT_CH11_LOW_TH)
+#define BIT_CLEAR_CH11_LOW_TH(x) ((x) & (~BITS_CH11_LOW_TH))
+#define BIT_GET_CH11_LOW_TH(x) \
+ (((x) >> BIT_SHIFT_CH11_LOW_TH) & BIT_MASK_CH11_LOW_TH)
+#define BIT_SET_CH11_LOW_TH(x, v) \
+ (BIT_CLEAR_CH11_LOW_TH(x) | BIT_CH11_LOW_TH(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_12 (Offset 0x3230) */
+
+#define BIT_CH12_INT_EN BIT(31)
+
+#define BIT_SHIFT_CH12_HIGH_TH 16
+#define BIT_MASK_CH12_HIGH_TH 0xfff
+#define BIT_CH12_HIGH_TH(x) \
+ (((x) & BIT_MASK_CH12_HIGH_TH) << BIT_SHIFT_CH12_HIGH_TH)
+#define BITS_CH12_HIGH_TH (BIT_MASK_CH12_HIGH_TH << BIT_SHIFT_CH12_HIGH_TH)
+#define BIT_CLEAR_CH12_HIGH_TH(x) ((x) & (~BITS_CH12_HIGH_TH))
+#define BIT_GET_CH12_HIGH_TH(x) \
+ (((x) >> BIT_SHIFT_CH12_HIGH_TH) & BIT_MASK_CH12_HIGH_TH)
+#define BIT_SET_CH12_HIGH_TH(x, v) \
+ (BIT_CLEAR_CH12_HIGH_TH(x) | BIT_CH12_HIGH_TH(v))
+
+#define BIT_SHIFT_CH12_LOW_TH 0
+#define BIT_MASK_CH12_LOW_TH 0xfff
+#define BIT_CH12_LOW_TH(x) \
+ (((x) & BIT_MASK_CH12_LOW_TH) << BIT_SHIFT_CH12_LOW_TH)
+#define BITS_CH12_LOW_TH (BIT_MASK_CH12_LOW_TH << BIT_SHIFT_CH12_LOW_TH)
+#define BIT_CLEAR_CH12_LOW_TH(x) ((x) & (~BITS_CH12_LOW_TH))
+#define BIT_GET_CH12_LOW_TH(x) \
+ (((x) >> BIT_SHIFT_CH12_LOW_TH) & BIT_MASK_CH12_LOW_TH)
+#define BIT_SET_CH12_LOW_TH(x, v) \
+ (BIT_CLEAR_CH12_LOW_TH(x) | BIT_CH12_LOW_TH(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_13 (Offset 0x3234) */
+
+#define BIT_CH13_INT_EN BIT(31)
+
+#define BIT_SHIFT_CH13_HIGH_TH 16
+#define BIT_MASK_CH13_HIGH_TH 0xfff
+#define BIT_CH13_HIGH_TH(x) \
+ (((x) & BIT_MASK_CH13_HIGH_TH) << BIT_SHIFT_CH13_HIGH_TH)
+#define BITS_CH13_HIGH_TH (BIT_MASK_CH13_HIGH_TH << BIT_SHIFT_CH13_HIGH_TH)
+#define BIT_CLEAR_CH13_HIGH_TH(x) ((x) & (~BITS_CH13_HIGH_TH))
+#define BIT_GET_CH13_HIGH_TH(x) \
+ (((x) >> BIT_SHIFT_CH13_HIGH_TH) & BIT_MASK_CH13_HIGH_TH)
+#define BIT_SET_CH13_HIGH_TH(x, v) \
+ (BIT_CLEAR_CH13_HIGH_TH(x) | BIT_CH13_HIGH_TH(v))
+
+#define BIT_SHIFT_CH13_LOW_TH 0
+#define BIT_MASK_CH13_LOW_TH 0xfff
+#define BIT_CH13_LOW_TH(x) \
+ (((x) & BIT_MASK_CH13_LOW_TH) << BIT_SHIFT_CH13_LOW_TH)
+#define BITS_CH13_LOW_TH (BIT_MASK_CH13_LOW_TH << BIT_SHIFT_CH13_LOW_TH)
+#define BIT_CLEAR_CH13_LOW_TH(x) ((x) & (~BITS_CH13_LOW_TH))
+#define BIT_GET_CH13_LOW_TH(x) \
+ (((x) >> BIT_SHIFT_CH13_LOW_TH) & BIT_MASK_CH13_LOW_TH)
+#define BIT_SET_CH13_LOW_TH(x, v) \
+ (BIT_CLEAR_CH13_LOW_TH(x) | BIT_CH13_LOW_TH(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_14 (Offset 0x3238) */
+
+#define BIT_CH14_INT_EN BIT(31)
+
+#define BIT_SHIFT_CH14_HIGH_TH 16
+#define BIT_MASK_CH14_HIGH_TH 0xfff
+#define BIT_CH14_HIGH_TH(x) \
+ (((x) & BIT_MASK_CH14_HIGH_TH) << BIT_SHIFT_CH14_HIGH_TH)
+#define BITS_CH14_HIGH_TH (BIT_MASK_CH14_HIGH_TH << BIT_SHIFT_CH14_HIGH_TH)
+#define BIT_CLEAR_CH14_HIGH_TH(x) ((x) & (~BITS_CH14_HIGH_TH))
+#define BIT_GET_CH14_HIGH_TH(x) \
+ (((x) >> BIT_SHIFT_CH14_HIGH_TH) & BIT_MASK_CH14_HIGH_TH)
+#define BIT_SET_CH14_HIGH_TH(x, v) \
+ (BIT_CLEAR_CH14_HIGH_TH(x) | BIT_CH14_HIGH_TH(v))
+
+#define BIT_SHIFT_CH14_LOW_TH 0
+#define BIT_MASK_CH14_LOW_TH 0xfff
+#define BIT_CH14_LOW_TH(x) \
+ (((x) & BIT_MASK_CH14_LOW_TH) << BIT_SHIFT_CH14_LOW_TH)
+#define BITS_CH14_LOW_TH (BIT_MASK_CH14_LOW_TH << BIT_SHIFT_CH14_LOW_TH)
+#define BIT_CLEAR_CH14_LOW_TH(x) ((x) & (~BITS_CH14_LOW_TH))
+#define BIT_GET_CH14_LOW_TH(x) \
+ (((x) >> BIT_SHIFT_CH14_LOW_TH) & BIT_MASK_CH14_LOW_TH)
+#define BIT_SET_CH14_LOW_TH(x, v) \
+ (BIT_CLEAR_CH14_LOW_TH(x) | BIT_CH14_LOW_TH(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_15 (Offset 0x323C) */
+
+#define BIT_CH15_INT_EN BIT(31)
+
+#define BIT_SHIFT_CH15_HIGH_TH 16
+#define BIT_MASK_CH15_HIGH_TH 0xfff
+#define BIT_CH15_HIGH_TH(x) \
+ (((x) & BIT_MASK_CH15_HIGH_TH) << BIT_SHIFT_CH15_HIGH_TH)
+#define BITS_CH15_HIGH_TH (BIT_MASK_CH15_HIGH_TH << BIT_SHIFT_CH15_HIGH_TH)
+#define BIT_CLEAR_CH15_HIGH_TH(x) ((x) & (~BITS_CH15_HIGH_TH))
+#define BIT_GET_CH15_HIGH_TH(x) \
+ (((x) >> BIT_SHIFT_CH15_HIGH_TH) & BIT_MASK_CH15_HIGH_TH)
+#define BIT_SET_CH15_HIGH_TH(x, v) \
+ (BIT_CLEAR_CH15_HIGH_TH(x) | BIT_CH15_HIGH_TH(v))
+
+#define BIT_SHIFT_CH15_LOW_TH 0
+#define BIT_MASK_CH15_LOW_TH 0xfff
+#define BIT_CH15_LOW_TH(x) \
+ (((x) & BIT_MASK_CH15_LOW_TH) << BIT_SHIFT_CH15_LOW_TH)
+#define BITS_CH15_LOW_TH (BIT_MASK_CH15_LOW_TH << BIT_SHIFT_CH15_LOW_TH)
+#define BIT_CLEAR_CH15_LOW_TH(x) ((x) & (~BITS_CH15_LOW_TH))
+#define BIT_GET_CH15_LOW_TH(x) \
+ (((x) >> BIT_SHIFT_CH15_LOW_TH) & BIT_MASK_CH15_LOW_TH)
+#define BIT_SET_CH15_LOW_TH(x, v) \
+ (BIT_CLEAR_CH15_LOW_TH(x) | BIT_CH15_LOW_TH(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_16 (Offset 0x3240) */
+
+#define BIT_CH16_INT_EN BIT(31)
+
+#define BIT_SHIFT_CH16_HIGH_TH 16
+#define BIT_MASK_CH16_HIGH_TH 0xfff
+#define BIT_CH16_HIGH_TH(x) \
+ (((x) & BIT_MASK_CH16_HIGH_TH) << BIT_SHIFT_CH16_HIGH_TH)
+#define BITS_CH16_HIGH_TH (BIT_MASK_CH16_HIGH_TH << BIT_SHIFT_CH16_HIGH_TH)
+#define BIT_CLEAR_CH16_HIGH_TH(x) ((x) & (~BITS_CH16_HIGH_TH))
+#define BIT_GET_CH16_HIGH_TH(x) \
+ (((x) >> BIT_SHIFT_CH16_HIGH_TH) & BIT_MASK_CH16_HIGH_TH)
+#define BIT_SET_CH16_HIGH_TH(x, v) \
+ (BIT_CLEAR_CH16_HIGH_TH(x) | BIT_CH16_HIGH_TH(v))
+
+#define BIT_SHIFT_CH16_LOW_TH 0
+#define BIT_MASK_CH16_LOW_TH 0xfff
+#define BIT_CH16_LOW_TH(x) \
+ (((x) & BIT_MASK_CH16_LOW_TH) << BIT_SHIFT_CH16_LOW_TH)
+#define BITS_CH16_LOW_TH (BIT_MASK_CH16_LOW_TH << BIT_SHIFT_CH16_LOW_TH)
+#define BIT_CLEAR_CH16_LOW_TH(x) ((x) & (~BITS_CH16_LOW_TH))
+#define BIT_GET_CH16_LOW_TH(x) \
+ (((x) >> BIT_SHIFT_CH16_LOW_TH) & BIT_MASK_CH16_LOW_TH)
+#define BIT_SET_CH16_LOW_TH(x, v) \
+ (BIT_CLEAR_CH16_LOW_TH(x) | BIT_CH16_LOW_TH(v))
+
+/* 2 REG_ACH4_TXBD_IDX (Offset 0x3340) */
+
+#define BIT_SHIFT_ACH4_HW_IDX 16
+#define BIT_MASK_ACH4_HW_IDX 0xfff
+#define BIT_ACH4_HW_IDX(x) \
+ (((x) & BIT_MASK_ACH4_HW_IDX) << BIT_SHIFT_ACH4_HW_IDX)
+#define BITS_ACH4_HW_IDX (BIT_MASK_ACH4_HW_IDX << BIT_SHIFT_ACH4_HW_IDX)
+#define BIT_CLEAR_ACH4_HW_IDX(x) ((x) & (~BITS_ACH4_HW_IDX))
+#define BIT_GET_ACH4_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_ACH4_HW_IDX) & BIT_MASK_ACH4_HW_IDX)
+#define BIT_SET_ACH4_HW_IDX(x, v) \
+ (BIT_CLEAR_ACH4_HW_IDX(x) | BIT_ACH4_HW_IDX(v))
+
+#define BIT_SHIFT_ACH4_HOST_IDX 0
+#define BIT_MASK_ACH4_HOST_IDX 0xfff
+#define BIT_ACH4_HOST_IDX(x) \
+ (((x) & BIT_MASK_ACH4_HOST_IDX) << BIT_SHIFT_ACH4_HOST_IDX)
+#define BITS_ACH4_HOST_IDX (BIT_MASK_ACH4_HOST_IDX << BIT_SHIFT_ACH4_HOST_IDX)
+#define BIT_CLEAR_ACH4_HOST_IDX(x) ((x) & (~BITS_ACH4_HOST_IDX))
+#define BIT_GET_ACH4_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_ACH4_HOST_IDX) & BIT_MASK_ACH4_HOST_IDX)
+#define BIT_SET_ACH4_HOST_IDX(x, v) \
+ (BIT_CLEAR_ACH4_HOST_IDX(x) | BIT_ACH4_HOST_IDX(v))
+
+/* 2 REG_ACH5_TXBD_IDX (Offset 0x3344) */
+
+#define BIT_SHIFT_ACH5_HW_IDX 16
+#define BIT_MASK_ACH5_HW_IDX 0xfff
+#define BIT_ACH5_HW_IDX(x) \
+ (((x) & BIT_MASK_ACH5_HW_IDX) << BIT_SHIFT_ACH5_HW_IDX)
+#define BITS_ACH5_HW_IDX (BIT_MASK_ACH5_HW_IDX << BIT_SHIFT_ACH5_HW_IDX)
+#define BIT_CLEAR_ACH5_HW_IDX(x) ((x) & (~BITS_ACH5_HW_IDX))
+#define BIT_GET_ACH5_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_ACH5_HW_IDX) & BIT_MASK_ACH5_HW_IDX)
+#define BIT_SET_ACH5_HW_IDX(x, v) \
+ (BIT_CLEAR_ACH5_HW_IDX(x) | BIT_ACH5_HW_IDX(v))
+
+#define BIT_SHIFT_ACH5_HOST_IDX 0
+#define BIT_MASK_ACH5_HOST_IDX 0xfff
+#define BIT_ACH5_HOST_IDX(x) \
+ (((x) & BIT_MASK_ACH5_HOST_IDX) << BIT_SHIFT_ACH5_HOST_IDX)
+#define BITS_ACH5_HOST_IDX (BIT_MASK_ACH5_HOST_IDX << BIT_SHIFT_ACH5_HOST_IDX)
+#define BIT_CLEAR_ACH5_HOST_IDX(x) ((x) & (~BITS_ACH5_HOST_IDX))
+#define BIT_GET_ACH5_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_ACH5_HOST_IDX) & BIT_MASK_ACH5_HOST_IDX)
+#define BIT_SET_ACH5_HOST_IDX(x, v) \
+ (BIT_CLEAR_ACH5_HOST_IDX(x) | BIT_ACH5_HOST_IDX(v))
+
+/* 2 REG_ACH6_TXBD_IDX (Offset 0x3348) */
+
+#define BIT_SHIFT_ACH6_HW_IDX 16
+#define BIT_MASK_ACH6_HW_IDX 0xfff
+#define BIT_ACH6_HW_IDX(x) \
+ (((x) & BIT_MASK_ACH6_HW_IDX) << BIT_SHIFT_ACH6_HW_IDX)
+#define BITS_ACH6_HW_IDX (BIT_MASK_ACH6_HW_IDX << BIT_SHIFT_ACH6_HW_IDX)
+#define BIT_CLEAR_ACH6_HW_IDX(x) ((x) & (~BITS_ACH6_HW_IDX))
+#define BIT_GET_ACH6_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_ACH6_HW_IDX) & BIT_MASK_ACH6_HW_IDX)
+#define BIT_SET_ACH6_HW_IDX(x, v) \
+ (BIT_CLEAR_ACH6_HW_IDX(x) | BIT_ACH6_HW_IDX(v))
+
+#define BIT_SHIFT_ACH6_HOST_IDX 0
+#define BIT_MASK_ACH6_HOST_IDX 0xfff
+#define BIT_ACH6_HOST_IDX(x) \
+ (((x) & BIT_MASK_ACH6_HOST_IDX) << BIT_SHIFT_ACH6_HOST_IDX)
+#define BITS_ACH6_HOST_IDX (BIT_MASK_ACH6_HOST_IDX << BIT_SHIFT_ACH6_HOST_IDX)
+#define BIT_CLEAR_ACH6_HOST_IDX(x) ((x) & (~BITS_ACH6_HOST_IDX))
+#define BIT_GET_ACH6_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_ACH6_HOST_IDX) & BIT_MASK_ACH6_HOST_IDX)
+#define BIT_SET_ACH6_HOST_IDX(x, v) \
+ (BIT_CLEAR_ACH6_HOST_IDX(x) | BIT_ACH6_HOST_IDX(v))
+
+/* 2 REG_ACH7_TXBD_IDX (Offset 0x334C) */
+
+#define BIT_SHIFT_ACH7_HW_IDX 16
+#define BIT_MASK_ACH7_HW_IDX 0xfff
+#define BIT_ACH7_HW_IDX(x) \
+ (((x) & BIT_MASK_ACH7_HW_IDX) << BIT_SHIFT_ACH7_HW_IDX)
+#define BITS_ACH7_HW_IDX (BIT_MASK_ACH7_HW_IDX << BIT_SHIFT_ACH7_HW_IDX)
+#define BIT_CLEAR_ACH7_HW_IDX(x) ((x) & (~BITS_ACH7_HW_IDX))
+#define BIT_GET_ACH7_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_ACH7_HW_IDX) & BIT_MASK_ACH7_HW_IDX)
+#define BIT_SET_ACH7_HW_IDX(x, v) \
+ (BIT_CLEAR_ACH7_HW_IDX(x) | BIT_ACH7_HW_IDX(v))
+
+#define BIT_SHIFT_ACH7_HOST_IDX 0
+#define BIT_MASK_ACH7_HOST_IDX 0xfff
+#define BIT_ACH7_HOST_IDX(x) \
+ (((x) & BIT_MASK_ACH7_HOST_IDX) << BIT_SHIFT_ACH7_HOST_IDX)
+#define BITS_ACH7_HOST_IDX (BIT_MASK_ACH7_HOST_IDX << BIT_SHIFT_ACH7_HOST_IDX)
+#define BIT_CLEAR_ACH7_HOST_IDX(x) ((x) & (~BITS_ACH7_HOST_IDX))
+#define BIT_GET_ACH7_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_ACH7_HOST_IDX) & BIT_MASK_ACH7_HOST_IDX)
+#define BIT_SET_ACH7_HOST_IDX(x, v) \
+ (BIT_CLEAR_ACH7_HOST_IDX(x) | BIT_ACH7_HOST_IDX(v))
+
+/* 2 REG_ACH8_TXBD_IDX (Offset 0x3350) */
+
+#define BIT_SHIFT_ACH8_HW_IDX 16
+#define BIT_MASK_ACH8_HW_IDX 0xfff
+#define BIT_ACH8_HW_IDX(x) \
+ (((x) & BIT_MASK_ACH8_HW_IDX) << BIT_SHIFT_ACH8_HW_IDX)
+#define BITS_ACH8_HW_IDX (BIT_MASK_ACH8_HW_IDX << BIT_SHIFT_ACH8_HW_IDX)
+#define BIT_CLEAR_ACH8_HW_IDX(x) ((x) & (~BITS_ACH8_HW_IDX))
+#define BIT_GET_ACH8_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_ACH8_HW_IDX) & BIT_MASK_ACH8_HW_IDX)
+#define BIT_SET_ACH8_HW_IDX(x, v) \
+ (BIT_CLEAR_ACH8_HW_IDX(x) | BIT_ACH8_HW_IDX(v))
+
+#define BIT_SHIFT_ACH8_HOST_IDX 0
+#define BIT_MASK_ACH8_HOST_IDX 0xfff
+#define BIT_ACH8_HOST_IDX(x) \
+ (((x) & BIT_MASK_ACH8_HOST_IDX) << BIT_SHIFT_ACH8_HOST_IDX)
+#define BITS_ACH8_HOST_IDX (BIT_MASK_ACH8_HOST_IDX << BIT_SHIFT_ACH8_HOST_IDX)
+#define BIT_CLEAR_ACH8_HOST_IDX(x) ((x) & (~BITS_ACH8_HOST_IDX))
+#define BIT_GET_ACH8_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_ACH8_HOST_IDX) & BIT_MASK_ACH8_HOST_IDX)
+#define BIT_SET_ACH8_HOST_IDX(x, v) \
+ (BIT_CLEAR_ACH8_HOST_IDX(x) | BIT_ACH8_HOST_IDX(v))
+
+/* 2 REG_ACH9_TXBD_IDX (Offset 0x3354) */
+
+#define BIT_SHIFT_ACH9_HW_IDX 16
+#define BIT_MASK_ACH9_HW_IDX 0xfff
+#define BIT_ACH9_HW_IDX(x) \
+ (((x) & BIT_MASK_ACH9_HW_IDX) << BIT_SHIFT_ACH9_HW_IDX)
+#define BITS_ACH9_HW_IDX (BIT_MASK_ACH9_HW_IDX << BIT_SHIFT_ACH9_HW_IDX)
+#define BIT_CLEAR_ACH9_HW_IDX(x) ((x) & (~BITS_ACH9_HW_IDX))
+#define BIT_GET_ACH9_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_ACH9_HW_IDX) & BIT_MASK_ACH9_HW_IDX)
+#define BIT_SET_ACH9_HW_IDX(x, v) \
+ (BIT_CLEAR_ACH9_HW_IDX(x) | BIT_ACH9_HW_IDX(v))
+
+#define BIT_SHIFT_ACH9_HOST_IDX 0
+#define BIT_MASK_ACH9_HOST_IDX 0xfff
+#define BIT_ACH9_HOST_IDX(x) \
+ (((x) & BIT_MASK_ACH9_HOST_IDX) << BIT_SHIFT_ACH9_HOST_IDX)
+#define BITS_ACH9_HOST_IDX (BIT_MASK_ACH9_HOST_IDX << BIT_SHIFT_ACH9_HOST_IDX)
+#define BIT_CLEAR_ACH9_HOST_IDX(x) ((x) & (~BITS_ACH9_HOST_IDX))
+#define BIT_GET_ACH9_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_ACH9_HOST_IDX) & BIT_MASK_ACH9_HOST_IDX)
+#define BIT_SET_ACH9_HOST_IDX(x, v) \
+ (BIT_CLEAR_ACH9_HOST_IDX(x) | BIT_ACH9_HOST_IDX(v))
+
+/* 2 REG_ACH10_TXBD_IDX (Offset 0x3358) */
+
+#define BIT_SHIFT_ACH10_HW_IDX 16
+#define BIT_MASK_ACH10_HW_IDX 0xfff
+#define BIT_ACH10_HW_IDX(x) \
+ (((x) & BIT_MASK_ACH10_HW_IDX) << BIT_SHIFT_ACH10_HW_IDX)
+#define BITS_ACH10_HW_IDX (BIT_MASK_ACH10_HW_IDX << BIT_SHIFT_ACH10_HW_IDX)
+#define BIT_CLEAR_ACH10_HW_IDX(x) ((x) & (~BITS_ACH10_HW_IDX))
+#define BIT_GET_ACH10_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_ACH10_HW_IDX) & BIT_MASK_ACH10_HW_IDX)
+#define BIT_SET_ACH10_HW_IDX(x, v) \
+ (BIT_CLEAR_ACH10_HW_IDX(x) | BIT_ACH10_HW_IDX(v))
+
+#define BIT_SHIFT_ACH10_HOST_IDX 0
+#define BIT_MASK_ACH10_HOST_IDX 0xfff
+#define BIT_ACH10_HOST_IDX(x) \
+ (((x) & BIT_MASK_ACH10_HOST_IDX) << BIT_SHIFT_ACH10_HOST_IDX)
+#define BITS_ACH10_HOST_IDX \
+ (BIT_MASK_ACH10_HOST_IDX << BIT_SHIFT_ACH10_HOST_IDX)
+#define BIT_CLEAR_ACH10_HOST_IDX(x) ((x) & (~BITS_ACH10_HOST_IDX))
+#define BIT_GET_ACH10_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_ACH10_HOST_IDX) & BIT_MASK_ACH10_HOST_IDX)
+#define BIT_SET_ACH10_HOST_IDX(x, v) \
+ (BIT_CLEAR_ACH10_HOST_IDX(x) | BIT_ACH10_HOST_IDX(v))
+
+/* 2 REG_ACH11_TXBD_IDX (Offset 0x335C) */
+
+#define BIT_SHIFT_ACH11_HW_IDX 16
+#define BIT_MASK_ACH11_HW_IDX 0xfff
+#define BIT_ACH11_HW_IDX(x) \
+ (((x) & BIT_MASK_ACH11_HW_IDX) << BIT_SHIFT_ACH11_HW_IDX)
+#define BITS_ACH11_HW_IDX (BIT_MASK_ACH11_HW_IDX << BIT_SHIFT_ACH11_HW_IDX)
+#define BIT_CLEAR_ACH11_HW_IDX(x) ((x) & (~BITS_ACH11_HW_IDX))
+#define BIT_GET_ACH11_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_ACH11_HW_IDX) & BIT_MASK_ACH11_HW_IDX)
+#define BIT_SET_ACH11_HW_IDX(x, v) \
+ (BIT_CLEAR_ACH11_HW_IDX(x) | BIT_ACH11_HW_IDX(v))
+
+#define BIT_SHIFT_ACH11_HOST_IDX 0
+#define BIT_MASK_ACH11_HOST_IDX 0xfff
+#define BIT_ACH11_HOST_IDX(x) \
+ (((x) & BIT_MASK_ACH11_HOST_IDX) << BIT_SHIFT_ACH11_HOST_IDX)
+#define BITS_ACH11_HOST_IDX \
+ (BIT_MASK_ACH11_HOST_IDX << BIT_SHIFT_ACH11_HOST_IDX)
+#define BIT_CLEAR_ACH11_HOST_IDX(x) ((x) & (~BITS_ACH11_HOST_IDX))
+#define BIT_GET_ACH11_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_ACH11_HOST_IDX) & BIT_MASK_ACH11_HOST_IDX)
+#define BIT_SET_ACH11_HOST_IDX(x, v) \
+ (BIT_CLEAR_ACH11_HOST_IDX(x) | BIT_ACH11_HOST_IDX(v))
+
+/* 2 REG_ACH12_TXBD_IDX (Offset 0x3360) */
+
+#define BIT_SHIFT_ACH12_HW_IDX 16
+#define BIT_MASK_ACH12_HW_IDX 0xfff
+#define BIT_ACH12_HW_IDX(x) \
+ (((x) & BIT_MASK_ACH12_HW_IDX) << BIT_SHIFT_ACH12_HW_IDX)
+#define BITS_ACH12_HW_IDX (BIT_MASK_ACH12_HW_IDX << BIT_SHIFT_ACH12_HW_IDX)
+#define BIT_CLEAR_ACH12_HW_IDX(x) ((x) & (~BITS_ACH12_HW_IDX))
+#define BIT_GET_ACH12_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_ACH12_HW_IDX) & BIT_MASK_ACH12_HW_IDX)
+#define BIT_SET_ACH12_HW_IDX(x, v) \
+ (BIT_CLEAR_ACH12_HW_IDX(x) | BIT_ACH12_HW_IDX(v))
+
+#define BIT_SHIFT_ACH12_HOST_IDX 0
+#define BIT_MASK_ACH12_HOST_IDX 0xfff
+#define BIT_ACH12_HOST_IDX(x) \
+ (((x) & BIT_MASK_ACH12_HOST_IDX) << BIT_SHIFT_ACH12_HOST_IDX)
+#define BITS_ACH12_HOST_IDX \
+ (BIT_MASK_ACH12_HOST_IDX << BIT_SHIFT_ACH12_HOST_IDX)
+#define BIT_CLEAR_ACH12_HOST_IDX(x) ((x) & (~BITS_ACH12_HOST_IDX))
+#define BIT_GET_ACH12_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_ACH12_HOST_IDX) & BIT_MASK_ACH12_HOST_IDX)
+#define BIT_SET_ACH12_HOST_IDX(x, v) \
+ (BIT_CLEAR_ACH12_HOST_IDX(x) | BIT_ACH12_HOST_IDX(v))
+
+/* 2 REG_ACH13_TXBD_IDX (Offset 0x3364) */
+
+#define BIT_SHIFT_ACH13_HW_IDX 16
+#define BIT_MASK_ACH13_HW_IDX 0xfff
+#define BIT_ACH13_HW_IDX(x) \
+ (((x) & BIT_MASK_ACH13_HW_IDX) << BIT_SHIFT_ACH13_HW_IDX)
+#define BITS_ACH13_HW_IDX (BIT_MASK_ACH13_HW_IDX << BIT_SHIFT_ACH13_HW_IDX)
+#define BIT_CLEAR_ACH13_HW_IDX(x) ((x) & (~BITS_ACH13_HW_IDX))
+#define BIT_GET_ACH13_HW_IDX(x) \
+ (((x) >> BIT_SHIFT_ACH13_HW_IDX) & BIT_MASK_ACH13_HW_IDX)
+#define BIT_SET_ACH13_HW_IDX(x, v) \
+ (BIT_CLEAR_ACH13_HW_IDX(x) | BIT_ACH13_HW_IDX(v))
+
+#define BIT_SHIFT_ACH13_HOST_IDX 0
+#define BIT_MASK_ACH13_HOST_IDX 0xfff
+#define BIT_ACH13_HOST_IDX(x) \
+ (((x) & BIT_MASK_ACH13_HOST_IDX) << BIT_SHIFT_ACH13_HOST_IDX)
+#define BITS_ACH13_HOST_IDX \
+ (BIT_MASK_ACH13_HOST_IDX << BIT_SHIFT_ACH13_HOST_IDX)
+#define BIT_CLEAR_ACH13_HOST_IDX(x) ((x) & (~BITS_ACH13_HOST_IDX))
+#define BIT_GET_ACH13_HOST_IDX(x) \
+ (((x) >> BIT_SHIFT_ACH13_HOST_IDX) & BIT_MASK_ACH13_HOST_IDX)
+#define BIT_SET_ACH13_HOST_IDX(x, v) \
+ (BIT_CLEAR_ACH13_HOST_IDX(x) | BIT_ACH13_HOST_IDX(v))
+
+/* 2 REG_AC_CHANNEL0_WEIGHT (Offset 0x3368) */
+
+#define BIT_SHIFT_AC_CHANNEL0_WEIGHT 0
+#define BIT_MASK_AC_CHANNEL0_WEIGHT 0xff
+#define BIT_AC_CHANNEL0_WEIGHT(x) \
+ (((x) & BIT_MASK_AC_CHANNEL0_WEIGHT) << BIT_SHIFT_AC_CHANNEL0_WEIGHT)
+#define BITS_AC_CHANNEL0_WEIGHT \
+ (BIT_MASK_AC_CHANNEL0_WEIGHT << BIT_SHIFT_AC_CHANNEL0_WEIGHT)
+#define BIT_CLEAR_AC_CHANNEL0_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL0_WEIGHT))
+#define BIT_GET_AC_CHANNEL0_WEIGHT(x) \
+ (((x) >> BIT_SHIFT_AC_CHANNEL0_WEIGHT) & BIT_MASK_AC_CHANNEL0_WEIGHT)
+#define BIT_SET_AC_CHANNEL0_WEIGHT(x, v) \
+ (BIT_CLEAR_AC_CHANNEL0_WEIGHT(x) | BIT_AC_CHANNEL0_WEIGHT(v))
+
+/* 2 REG_AC_CHANNEL1_WEIGHT (Offset 0x3369) */
+
+#define BIT_SHIFT_AC_CHANNEL1_WEIGHT 0
+#define BIT_MASK_AC_CHANNEL1_WEIGHT 0xff
+#define BIT_AC_CHANNEL1_WEIGHT(x) \
+ (((x) & BIT_MASK_AC_CHANNEL1_WEIGHT) << BIT_SHIFT_AC_CHANNEL1_WEIGHT)
+#define BITS_AC_CHANNEL1_WEIGHT \
+ (BIT_MASK_AC_CHANNEL1_WEIGHT << BIT_SHIFT_AC_CHANNEL1_WEIGHT)
+#define BIT_CLEAR_AC_CHANNEL1_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL1_WEIGHT))
+#define BIT_GET_AC_CHANNEL1_WEIGHT(x) \
+ (((x) >> BIT_SHIFT_AC_CHANNEL1_WEIGHT) & BIT_MASK_AC_CHANNEL1_WEIGHT)
+#define BIT_SET_AC_CHANNEL1_WEIGHT(x, v) \
+ (BIT_CLEAR_AC_CHANNEL1_WEIGHT(x) | BIT_AC_CHANNEL1_WEIGHT(v))
+
+/* 2 REG_AC_CHANNEL2_WEIGHT (Offset 0x336A) */
+
+#define BIT_SHIFT_AC_CHANNEL2_WEIGHT 0
+#define BIT_MASK_AC_CHANNEL2_WEIGHT 0xff
+#define BIT_AC_CHANNEL2_WEIGHT(x) \
+ (((x) & BIT_MASK_AC_CHANNEL2_WEIGHT) << BIT_SHIFT_AC_CHANNEL2_WEIGHT)
+#define BITS_AC_CHANNEL2_WEIGHT \
+ (BIT_MASK_AC_CHANNEL2_WEIGHT << BIT_SHIFT_AC_CHANNEL2_WEIGHT)
+#define BIT_CLEAR_AC_CHANNEL2_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL2_WEIGHT))
+#define BIT_GET_AC_CHANNEL2_WEIGHT(x) \
+ (((x) >> BIT_SHIFT_AC_CHANNEL2_WEIGHT) & BIT_MASK_AC_CHANNEL2_WEIGHT)
+#define BIT_SET_AC_CHANNEL2_WEIGHT(x, v) \
+ (BIT_CLEAR_AC_CHANNEL2_WEIGHT(x) | BIT_AC_CHANNEL2_WEIGHT(v))
+
+/* 2 REG_AC_CHANNEL3_WEIGHT (Offset 0x336B) */
+
+#define BIT_SHIFT_AC_CHANNEL3_WEIGHT 0
+#define BIT_MASK_AC_CHANNEL3_WEIGHT 0xff
+#define BIT_AC_CHANNEL3_WEIGHT(x) \
+ (((x) & BIT_MASK_AC_CHANNEL3_WEIGHT) << BIT_SHIFT_AC_CHANNEL3_WEIGHT)
+#define BITS_AC_CHANNEL3_WEIGHT \
+ (BIT_MASK_AC_CHANNEL3_WEIGHT << BIT_SHIFT_AC_CHANNEL3_WEIGHT)
+#define BIT_CLEAR_AC_CHANNEL3_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL3_WEIGHT))
+#define BIT_GET_AC_CHANNEL3_WEIGHT(x) \
+ (((x) >> BIT_SHIFT_AC_CHANNEL3_WEIGHT) & BIT_MASK_AC_CHANNEL3_WEIGHT)
+#define BIT_SET_AC_CHANNEL3_WEIGHT(x, v) \
+ (BIT_CLEAR_AC_CHANNEL3_WEIGHT(x) | BIT_AC_CHANNEL3_WEIGHT(v))
+
+/* 2 REG_AC_CHANNEL4_WEIGHT (Offset 0x336C) */
+
+#define BIT_SHIFT_AC_CHANNEL4_WEIGHT 0
+#define BIT_MASK_AC_CHANNEL4_WEIGHT 0xff
+#define BIT_AC_CHANNEL4_WEIGHT(x) \
+ (((x) & BIT_MASK_AC_CHANNEL4_WEIGHT) << BIT_SHIFT_AC_CHANNEL4_WEIGHT)
+#define BITS_AC_CHANNEL4_WEIGHT \
+ (BIT_MASK_AC_CHANNEL4_WEIGHT << BIT_SHIFT_AC_CHANNEL4_WEIGHT)
+#define BIT_CLEAR_AC_CHANNEL4_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL4_WEIGHT))
+#define BIT_GET_AC_CHANNEL4_WEIGHT(x) \
+ (((x) >> BIT_SHIFT_AC_CHANNEL4_WEIGHT) & BIT_MASK_AC_CHANNEL4_WEIGHT)
+#define BIT_SET_AC_CHANNEL4_WEIGHT(x, v) \
+ (BIT_CLEAR_AC_CHANNEL4_WEIGHT(x) | BIT_AC_CHANNEL4_WEIGHT(v))
+
+/* 2 REG_AC_CHANNEL5_WEIGHT (Offset 0x336D) */
+
+#define BIT_SHIFT_AC_CHANNEL5_WEIGHT 0
+#define BIT_MASK_AC_CHANNEL5_WEIGHT 0xff
+#define BIT_AC_CHANNEL5_WEIGHT(x) \
+ (((x) & BIT_MASK_AC_CHANNEL5_WEIGHT) << BIT_SHIFT_AC_CHANNEL5_WEIGHT)
+#define BITS_AC_CHANNEL5_WEIGHT \
+ (BIT_MASK_AC_CHANNEL5_WEIGHT << BIT_SHIFT_AC_CHANNEL5_WEIGHT)
+#define BIT_CLEAR_AC_CHANNEL5_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL5_WEIGHT))
+#define BIT_GET_AC_CHANNEL5_WEIGHT(x) \
+ (((x) >> BIT_SHIFT_AC_CHANNEL5_WEIGHT) & BIT_MASK_AC_CHANNEL5_WEIGHT)
+#define BIT_SET_AC_CHANNEL5_WEIGHT(x, v) \
+ (BIT_CLEAR_AC_CHANNEL5_WEIGHT(x) | BIT_AC_CHANNEL5_WEIGHT(v))
+
+/* 2 REG_AC_CHANNEL6_WEIGHT (Offset 0x336E) */
+
+#define BIT_SHIFT_AC_CHANNEL6_WEIGHT 0
+#define BIT_MASK_AC_CHANNEL6_WEIGHT 0xff
+#define BIT_AC_CHANNEL6_WEIGHT(x) \
+ (((x) & BIT_MASK_AC_CHANNEL6_WEIGHT) << BIT_SHIFT_AC_CHANNEL6_WEIGHT)
+#define BITS_AC_CHANNEL6_WEIGHT \
+ (BIT_MASK_AC_CHANNEL6_WEIGHT << BIT_SHIFT_AC_CHANNEL6_WEIGHT)
+#define BIT_CLEAR_AC_CHANNEL6_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL6_WEIGHT))
+#define BIT_GET_AC_CHANNEL6_WEIGHT(x) \
+ (((x) >> BIT_SHIFT_AC_CHANNEL6_WEIGHT) & BIT_MASK_AC_CHANNEL6_WEIGHT)
+#define BIT_SET_AC_CHANNEL6_WEIGHT(x, v) \
+ (BIT_CLEAR_AC_CHANNEL6_WEIGHT(x) | BIT_AC_CHANNEL6_WEIGHT(v))
+
+/* 2 REG_AC_CHANNEL7_WEIGHT (Offset 0x336F) */
+
+#define BIT_SHIFT_AC_CHANNEL7_WEIGHT 0
+#define BIT_MASK_AC_CHANNEL7_WEIGHT 0xff
+#define BIT_AC_CHANNEL7_WEIGHT(x) \
+ (((x) & BIT_MASK_AC_CHANNEL7_WEIGHT) << BIT_SHIFT_AC_CHANNEL7_WEIGHT)
+#define BITS_AC_CHANNEL7_WEIGHT \
+ (BIT_MASK_AC_CHANNEL7_WEIGHT << BIT_SHIFT_AC_CHANNEL7_WEIGHT)
+#define BIT_CLEAR_AC_CHANNEL7_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL7_WEIGHT))
+#define BIT_GET_AC_CHANNEL7_WEIGHT(x) \
+ (((x) >> BIT_SHIFT_AC_CHANNEL7_WEIGHT) & BIT_MASK_AC_CHANNEL7_WEIGHT)
+#define BIT_SET_AC_CHANNEL7_WEIGHT(x, v) \
+ (BIT_CLEAR_AC_CHANNEL7_WEIGHT(x) | BIT_AC_CHANNEL7_WEIGHT(v))
+
+/* 2 REG_AC_CHANNEL8_WEIGHT (Offset 0x3370) */
+
+#define BIT_SHIFT_AC_CHANNEL8_WEIGHT 0
+#define BIT_MASK_AC_CHANNEL8_WEIGHT 0xff
+#define BIT_AC_CHANNEL8_WEIGHT(x) \
+ (((x) & BIT_MASK_AC_CHANNEL8_WEIGHT) << BIT_SHIFT_AC_CHANNEL8_WEIGHT)
+#define BITS_AC_CHANNEL8_WEIGHT \
+ (BIT_MASK_AC_CHANNEL8_WEIGHT << BIT_SHIFT_AC_CHANNEL8_WEIGHT)
+#define BIT_CLEAR_AC_CHANNEL8_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL8_WEIGHT))
+#define BIT_GET_AC_CHANNEL8_WEIGHT(x) \
+ (((x) >> BIT_SHIFT_AC_CHANNEL8_WEIGHT) & BIT_MASK_AC_CHANNEL8_WEIGHT)
+#define BIT_SET_AC_CHANNEL8_WEIGHT(x, v) \
+ (BIT_CLEAR_AC_CHANNEL8_WEIGHT(x) | BIT_AC_CHANNEL8_WEIGHT(v))
+
+/* 2 REG_AC_CHANNEL9_WEIGHT (Offset 0x3371) */
+
+#define BIT_SHIFT_AC_CHANNEL9_WEIGHT 0
+#define BIT_MASK_AC_CHANNEL9_WEIGHT 0xff
+#define BIT_AC_CHANNEL9_WEIGHT(x) \
+ (((x) & BIT_MASK_AC_CHANNEL9_WEIGHT) << BIT_SHIFT_AC_CHANNEL9_WEIGHT)
+#define BITS_AC_CHANNEL9_WEIGHT \
+ (BIT_MASK_AC_CHANNEL9_WEIGHT << BIT_SHIFT_AC_CHANNEL9_WEIGHT)
+#define BIT_CLEAR_AC_CHANNEL9_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL9_WEIGHT))
+#define BIT_GET_AC_CHANNEL9_WEIGHT(x) \
+ (((x) >> BIT_SHIFT_AC_CHANNEL9_WEIGHT) & BIT_MASK_AC_CHANNEL9_WEIGHT)
+#define BIT_SET_AC_CHANNEL9_WEIGHT(x, v) \
+ (BIT_CLEAR_AC_CHANNEL9_WEIGHT(x) | BIT_AC_CHANNEL9_WEIGHT(v))
+
+/* 2 REG_AC_CHANNEL10_WEIGHT (Offset 0x3372) */
+
+#define BIT_SHIFT_AC_CHANNEL10_WEIGHT 0
+#define BIT_MASK_AC_CHANNEL10_WEIGHT 0xff
+#define BIT_AC_CHANNEL10_WEIGHT(x) \
+ (((x) & BIT_MASK_AC_CHANNEL10_WEIGHT) << BIT_SHIFT_AC_CHANNEL10_WEIGHT)
+#define BITS_AC_CHANNEL10_WEIGHT \
+ (BIT_MASK_AC_CHANNEL10_WEIGHT << BIT_SHIFT_AC_CHANNEL10_WEIGHT)
+#define BIT_CLEAR_AC_CHANNEL10_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL10_WEIGHT))
+#define BIT_GET_AC_CHANNEL10_WEIGHT(x) \
+ (((x) >> BIT_SHIFT_AC_CHANNEL10_WEIGHT) & BIT_MASK_AC_CHANNEL10_WEIGHT)
+#define BIT_SET_AC_CHANNEL10_WEIGHT(x, v) \
+ (BIT_CLEAR_AC_CHANNEL10_WEIGHT(x) | BIT_AC_CHANNEL10_WEIGHT(v))
+
+/* 2 REG_AC_CHANNEL11_WEIGHT (Offset 0x3373) */
+
+#define BIT_SHIFT_AC_CHANNEL11_WEIGHT 0
+#define BIT_MASK_AC_CHANNEL11_WEIGHT 0xff
+#define BIT_AC_CHANNEL11_WEIGHT(x) \
+ (((x) & BIT_MASK_AC_CHANNEL11_WEIGHT) << BIT_SHIFT_AC_CHANNEL11_WEIGHT)
+#define BITS_AC_CHANNEL11_WEIGHT \
+ (BIT_MASK_AC_CHANNEL11_WEIGHT << BIT_SHIFT_AC_CHANNEL11_WEIGHT)
+#define BIT_CLEAR_AC_CHANNEL11_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL11_WEIGHT))
+#define BIT_GET_AC_CHANNEL11_WEIGHT(x) \
+ (((x) >> BIT_SHIFT_AC_CHANNEL11_WEIGHT) & BIT_MASK_AC_CHANNEL11_WEIGHT)
+#define BIT_SET_AC_CHANNEL11_WEIGHT(x, v) \
+ (BIT_CLEAR_AC_CHANNEL11_WEIGHT(x) | BIT_AC_CHANNEL11_WEIGHT(v))
+
+/* 2 REG_AC_CHANNEL12_WEIGHT (Offset 0x3374) */
+
+#define BIT_SHIFT_AC_CHANNEL12_WEIGHT 0
+#define BIT_MASK_AC_CHANNEL12_WEIGHT 0xff
+#define BIT_AC_CHANNEL12_WEIGHT(x) \
+ (((x) & BIT_MASK_AC_CHANNEL12_WEIGHT) << BIT_SHIFT_AC_CHANNEL12_WEIGHT)
+#define BITS_AC_CHANNEL12_WEIGHT \
+ (BIT_MASK_AC_CHANNEL12_WEIGHT << BIT_SHIFT_AC_CHANNEL12_WEIGHT)
+#define BIT_CLEAR_AC_CHANNEL12_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL12_WEIGHT))
+#define BIT_GET_AC_CHANNEL12_WEIGHT(x) \
+ (((x) >> BIT_SHIFT_AC_CHANNEL12_WEIGHT) & BIT_MASK_AC_CHANNEL12_WEIGHT)
+#define BIT_SET_AC_CHANNEL12_WEIGHT(x, v) \
+ (BIT_CLEAR_AC_CHANNEL12_WEIGHT(x) | BIT_AC_CHANNEL12_WEIGHT(v))
+
+/* 2 REG_AC_CHANNEL13_WEIGHT (Offset 0x3375) */
+
+#define BIT_SHIFT_AC_CHANNEL13_WEIGHT 0
+#define BIT_MASK_AC_CHANNEL13_WEIGHT 0xff
+#define BIT_AC_CHANNEL13_WEIGHT(x) \
+ (((x) & BIT_MASK_AC_CHANNEL13_WEIGHT) << BIT_SHIFT_AC_CHANNEL13_WEIGHT)
+#define BITS_AC_CHANNEL13_WEIGHT \
+ (BIT_MASK_AC_CHANNEL13_WEIGHT << BIT_SHIFT_AC_CHANNEL13_WEIGHT)
+#define BIT_CLEAR_AC_CHANNEL13_WEIGHT(x) ((x) & (~BITS_AC_CHANNEL13_WEIGHT))
+#define BIT_GET_AC_CHANNEL13_WEIGHT(x) \
+ (((x) >> BIT_SHIFT_AC_CHANNEL13_WEIGHT) & BIT_MASK_AC_CHANNEL13_WEIGHT)
+#define BIT_SET_AC_CHANNEL13_WEIGHT(x, v) \
+ (BIT_CLEAR_AC_CHANNEL13_WEIGHT(x) | BIT_AC_CHANNEL13_WEIGHT(v))
+
+#endif
+
+#endif /* __RTL_WLAN_BITDEF_H__ */
diff --git a/hal/halmac/halmac_bit_8197f.h b/hal/halmac/halmac_bit_8197f.h
new file mode 100644
index 0000000..a8cf8eb
--- /dev/null
+++ b/hal/halmac/halmac_bit_8197f.h
@@ -0,0 +1,17293 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef __INC_HALMAC_BIT_8197F_H
+#define __INC_HALMAC_BIT_8197F_H
+
+#define CPU_OPT_WIDTH 0x1F
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_SYS_ISO_CTRL_8197F */
+#define BIT_PWC_EV12V_8197F BIT(15)
+#define BIT_PWC_EV25V_8197F BIT(14)
+#define BIT_PA33V_EN_8197F BIT(13)
+#define BIT_PA12V_EN_8197F BIT(12)
+#define BIT_UA33V_EN_8197F BIT(11)
+#define BIT_UA12V_EN_8197F BIT(10)
+#define BIT_ISO_RFDIO_8197F BIT(9)
+#define BIT_ISO_EB2CORE_8197F BIT(8)
+#define BIT_ISO_DIOE_8197F BIT(7)
+#define BIT_ISO_WLPON2PP_8197F BIT(6)
+#define BIT_ISO_IP2MAC_WA2PP_8197F BIT(5)
+#define BIT_ISO_PD2CORE_8197F BIT(4)
+#define BIT_ISO_PA2PCIE_8197F BIT(3)
+#define BIT_ISO_UD2CORE_8197F BIT(2)
+#define BIT_ISO_UA2USB_8197F BIT(1)
+#define BIT_ISO_WD2PP_8197F BIT(0)
+
+/* 2 REG_SYS_FUNC_EN_8197F */
+#define BIT_FEN_MREGEN_8197F BIT(15)
+#define BIT_FEN_HWPDN_8197F BIT(14)
+#define BIT_EN_25_1_8197F BIT(13)
+#define BIT_FEN_ELDR_8197F BIT(12)
+#define BIT_FEN_DCORE_8197F BIT(11)
+#define BIT_FEN_CPUEN_8197F BIT(10)
+#define BIT_FEN_DIOE_8197F BIT(9)
+#define BIT_FEN_PCIED_8197F BIT(8)
+#define BIT_FEN_PPLL_8197F BIT(7)
+#define BIT_FEN_PCIEA_8197F BIT(6)
+#define BIT_FEN_DIO_PCIE_8197F BIT(5)
+#define BIT_FEN_USBD_8197F BIT(4)
+#define BIT_FEN_UPLL_8197F BIT(3)
+#define BIT_FEN_USBA_8197F BIT(2)
+#define BIT_FEN_BB_GLB_RSTN_8197F BIT(1)
+#define BIT_FEN_BBRSTB_8197F BIT(0)
+
+/* 2 REG_SYS_PW_CTRL_8197F */
+#define BIT_SOP_EABM_8197F BIT(31)
+#define BIT_SOP_ACKF_8197F BIT(30)
+#define BIT_SOP_ERCK_8197F BIT(29)
+#define BIT_SOP_ESWR_8197F BIT(28)
+#define BIT_SOP_PWMM_8197F BIT(27)
+#define BIT_SOP_EECK_8197F BIT(26)
+#define BIT_SOP_EXTL_8197F BIT(24)
+#define BIT_SYM_OP_RING_12M_8197F BIT(22)
+#define BIT_ROP_SWPR_8197F BIT(21)
+#define BIT_DIS_HW_LPLDM_8197F BIT(20)
+#define BIT_OPT_SWRST_WLMCU_8197F BIT(19)
+#define BIT_RDY_SYSPWR_8197F BIT(17)
+#define BIT_EN_WLON_8197F BIT(16)
+#define BIT_APDM_HPDN_8197F BIT(15)
+#define BIT_AFSM_PCIE_SUS_EN_8197F BIT(12)
+#define BIT_AFSM_WLSUS_EN_8197F BIT(11)
+#define BIT_APFM_SWLPS_8197F BIT(10)
+#define BIT_APFM_OFFMAC_8197F BIT(9)
+#define BIT_APFN_ONMAC_8197F BIT(8)
+#define BIT_CHIP_PDN_EN_8197F BIT(7)
+#define BIT_RDY_MACDIS_8197F BIT(6)
+#define BIT_RING_CLK_12M_EN_8197F BIT(4)
+#define BIT_PFM_WOWL_8197F BIT(3)
+#define BIT_PFM_LDKP_8197F BIT(2)
+#define BIT_WL_HCI_ALD_8197F BIT(1)
+#define BIT_PFM_LDALL_8197F BIT(0)
+
+/* 2 REG_SYS_CLK_CTRL_8197F */
+#define BIT_LDO_DUMMY_8197F BIT(15)
+#define BIT_CPU_CLK_EN_8197F BIT(14)
+#define BIT_SYMREG_CLK_EN_8197F BIT(13)
+#define BIT_HCI_CLK_EN_8197F BIT(12)
+#define BIT_MAC_CLK_EN_8197F BIT(11)
+#define BIT_SEC_CLK_EN_8197F BIT(10)
+#define BIT_PHY_SSC_RSTB_8197F BIT(9)
+#define BIT_EXT_32K_EN_8197F BIT(8)
+#define BIT_WL_CLK_TEST_8197F BIT(7)
+#define BIT_OP_SPS_PWM_EN_8197F BIT(6)
+#define BIT_LOADER_CLK_EN_8197F BIT(5)
+#define BIT_MACSLP_8197F BIT(4)
+#define BIT_WAKEPAD_EN_8197F BIT(3)
+#define BIT_ROMD16V_EN_8197F BIT(2)
+#define BIT_CKANA12M_EN_8197F BIT(1)
+#define BIT_CNTD16V_EN_8197F BIT(0)
+
+/* 2 REG_SYS_EEPROM_CTRL_8197F */
+
+#define BIT_SHIFT_VPDIDX_8197F 8
+#define BIT_MASK_VPDIDX_8197F 0xff
+#define BIT_VPDIDX_8197F(x) \
+ (((x) & BIT_MASK_VPDIDX_8197F) << BIT_SHIFT_VPDIDX_8197F)
+#define BITS_VPDIDX_8197F (BIT_MASK_VPDIDX_8197F << BIT_SHIFT_VPDIDX_8197F)
+#define BIT_CLEAR_VPDIDX_8197F(x) ((x) & (~BITS_VPDIDX_8197F))
+#define BIT_GET_VPDIDX_8197F(x) \
+ (((x) >> BIT_SHIFT_VPDIDX_8197F) & BIT_MASK_VPDIDX_8197F)
+#define BIT_SET_VPDIDX_8197F(x, v) \
+ (BIT_CLEAR_VPDIDX_8197F(x) | BIT_VPDIDX_8197F(v))
+
+#define BIT_SHIFT_EEM1_0_8197F 6
+#define BIT_MASK_EEM1_0_8197F 0x3
+#define BIT_EEM1_0_8197F(x) \
+ (((x) & BIT_MASK_EEM1_0_8197F) << BIT_SHIFT_EEM1_0_8197F)
+#define BITS_EEM1_0_8197F (BIT_MASK_EEM1_0_8197F << BIT_SHIFT_EEM1_0_8197F)
+#define BIT_CLEAR_EEM1_0_8197F(x) ((x) & (~BITS_EEM1_0_8197F))
+#define BIT_GET_EEM1_0_8197F(x) \
+ (((x) >> BIT_SHIFT_EEM1_0_8197F) & BIT_MASK_EEM1_0_8197F)
+#define BIT_SET_EEM1_0_8197F(x, v) \
+ (BIT_CLEAR_EEM1_0_8197F(x) | BIT_EEM1_0_8197F(v))
+
+#define BIT_AUTOLOAD_SUS_8197F BIT(5)
+#define BIT_EERPOMSEL_8197F BIT(4)
+#define BIT_EECS_V1_8197F BIT(3)
+#define BIT_EESK_V1_8197F BIT(2)
+#define BIT_EEDI_V1_8197F BIT(1)
+#define BIT_EEDO_V1_8197F BIT(0)
+
+/* 2 REG_EE_VPD_8197F */
+
+#define BIT_SHIFT_VPD_DATA_8197F 0
+#define BIT_MASK_VPD_DATA_8197F 0xffffffffL
+#define BIT_VPD_DATA_8197F(x) \
+ (((x) & BIT_MASK_VPD_DATA_8197F) << BIT_SHIFT_VPD_DATA_8197F)
+#define BITS_VPD_DATA_8197F \
+ (BIT_MASK_VPD_DATA_8197F << BIT_SHIFT_VPD_DATA_8197F)
+#define BIT_CLEAR_VPD_DATA_8197F(x) ((x) & (~BITS_VPD_DATA_8197F))
+#define BIT_GET_VPD_DATA_8197F(x) \
+ (((x) >> BIT_SHIFT_VPD_DATA_8197F) & BIT_MASK_VPD_DATA_8197F)
+#define BIT_SET_VPD_DATA_8197F(x, v) \
+ (BIT_CLEAR_VPD_DATA_8197F(x) | BIT_VPD_DATA_8197F(v))
+
+/* 2 REG_SYS_SWR_CTRL1_8197F */
+#define BIT_SW18_C2_BIT0_8197F BIT(31)
+
+#define BIT_SHIFT_SW18_C1_8197F 29
+#define BIT_MASK_SW18_C1_8197F 0x3
+#define BIT_SW18_C1_8197F(x) \
+ (((x) & BIT_MASK_SW18_C1_8197F) << BIT_SHIFT_SW18_C1_8197F)
+#define BITS_SW18_C1_8197F (BIT_MASK_SW18_C1_8197F << BIT_SHIFT_SW18_C1_8197F)
+#define BIT_CLEAR_SW18_C1_8197F(x) ((x) & (~BITS_SW18_C1_8197F))
+#define BIT_GET_SW18_C1_8197F(x) \
+ (((x) >> BIT_SHIFT_SW18_C1_8197F) & BIT_MASK_SW18_C1_8197F)
+#define BIT_SET_SW18_C1_8197F(x, v) \
+ (BIT_CLEAR_SW18_C1_8197F(x) | BIT_SW18_C1_8197F(v))
+
+#define BIT_SHIFT_REG_FREQ_L_8197F 25
+#define BIT_MASK_REG_FREQ_L_8197F 0x7
+#define BIT_REG_FREQ_L_8197F(x) \
+ (((x) & BIT_MASK_REG_FREQ_L_8197F) << BIT_SHIFT_REG_FREQ_L_8197F)
+#define BITS_REG_FREQ_L_8197F \
+ (BIT_MASK_REG_FREQ_L_8197F << BIT_SHIFT_REG_FREQ_L_8197F)
+#define BIT_CLEAR_REG_FREQ_L_8197F(x) ((x) & (~BITS_REG_FREQ_L_8197F))
+#define BIT_GET_REG_FREQ_L_8197F(x) \
+ (((x) >> BIT_SHIFT_REG_FREQ_L_8197F) & BIT_MASK_REG_FREQ_L_8197F)
+#define BIT_SET_REG_FREQ_L_8197F(x, v) \
+ (BIT_CLEAR_REG_FREQ_L_8197F(x) | BIT_REG_FREQ_L_8197F(v))
+
+#define BIT_REG_EN_DUTY_8197F BIT(24)
+
+#define BIT_SHIFT_REG_MODE_8197F 22
+#define BIT_MASK_REG_MODE_8197F 0x3
+#define BIT_REG_MODE_8197F(x) \
+ (((x) & BIT_MASK_REG_MODE_8197F) << BIT_SHIFT_REG_MODE_8197F)
+#define BITS_REG_MODE_8197F \
+ (BIT_MASK_REG_MODE_8197F << BIT_SHIFT_REG_MODE_8197F)
+#define BIT_CLEAR_REG_MODE_8197F(x) ((x) & (~BITS_REG_MODE_8197F))
+#define BIT_GET_REG_MODE_8197F(x) \
+ (((x) >> BIT_SHIFT_REG_MODE_8197F) & BIT_MASK_REG_MODE_8197F)
+#define BIT_SET_REG_MODE_8197F(x, v) \
+ (BIT_CLEAR_REG_MODE_8197F(x) | BIT_REG_MODE_8197F(v))
+
+#define BIT_REG_EN_SP_8197F BIT(21)
+#define BIT_REG_AUTO_L_8197F BIT(20)
+#define BIT_SW18_SELD_BIT0_8197F BIT(19)
+#define BIT_SW18_POWOCP_8197F BIT(18)
+
+#define BIT_SHIFT_SW18_OCP_8197F 15
+#define BIT_MASK_SW18_OCP_8197F 0x7
+#define BIT_SW18_OCP_8197F(x) \
+ (((x) & BIT_MASK_SW18_OCP_8197F) << BIT_SHIFT_SW18_OCP_8197F)
+#define BITS_SW18_OCP_8197F \
+ (BIT_MASK_SW18_OCP_8197F << BIT_SHIFT_SW18_OCP_8197F)
+#define BIT_CLEAR_SW18_OCP_8197F(x) ((x) & (~BITS_SW18_OCP_8197F))
+#define BIT_GET_SW18_OCP_8197F(x) \
+ (((x) >> BIT_SHIFT_SW18_OCP_8197F) & BIT_MASK_SW18_OCP_8197F)
+#define BIT_SET_SW18_OCP_8197F(x, v) \
+ (BIT_CLEAR_SW18_OCP_8197F(x) | BIT_SW18_OCP_8197F(v))
+
+#define BIT_SHIFT_CF_L_BIT0_TO_1_8197F 13
+#define BIT_MASK_CF_L_BIT0_TO_1_8197F 0x3
+#define BIT_CF_L_BIT0_TO_1_8197F(x) \
+ (((x) & BIT_MASK_CF_L_BIT0_TO_1_8197F) \
+ << BIT_SHIFT_CF_L_BIT0_TO_1_8197F)
+#define BITS_CF_L_BIT0_TO_1_8197F \
+ (BIT_MASK_CF_L_BIT0_TO_1_8197F << BIT_SHIFT_CF_L_BIT0_TO_1_8197F)
+#define BIT_CLEAR_CF_L_BIT0_TO_1_8197F(x) ((x) & (~BITS_CF_L_BIT0_TO_1_8197F))
+#define BIT_GET_CF_L_BIT0_TO_1_8197F(x) \
+ (((x) >> BIT_SHIFT_CF_L_BIT0_TO_1_8197F) & \
+ BIT_MASK_CF_L_BIT0_TO_1_8197F)
+#define BIT_SET_CF_L_BIT0_TO_1_8197F(x, v) \
+ (BIT_CLEAR_CF_L_BIT0_TO_1_8197F(x) | BIT_CF_L_BIT0_TO_1_8197F(v))
+
+#define BIT_SW18_FPWM_8197F BIT(11)
+#define BIT_SW18_SWEN_8197F BIT(9)
+#define BIT_SW18_LDEN_8197F BIT(8)
+#define BIT_MAC_ID_EN_8197F BIT(7)
+#define BIT_WL_CTRL_XTAL_CADJ_8197F BIT(6)
+#define BIT_AFE_BGEN_8197F BIT(0)
+
+/* 2 REG_SYS_SWR_CTRL2_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_SYS_SWR_CTRL3_8197F */
+#define BIT_SPS18_OCP_DIS_8197F BIT(31)
+
+#define BIT_SHIFT_SPS18_OCP_TH_8197F 16
+#define BIT_MASK_SPS18_OCP_TH_8197F 0x7fff
+#define BIT_SPS18_OCP_TH_8197F(x) \
+ (((x) & BIT_MASK_SPS18_OCP_TH_8197F) << BIT_SHIFT_SPS18_OCP_TH_8197F)
+#define BITS_SPS18_OCP_TH_8197F \
+ (BIT_MASK_SPS18_OCP_TH_8197F << BIT_SHIFT_SPS18_OCP_TH_8197F)
+#define BIT_CLEAR_SPS18_OCP_TH_8197F(x) ((x) & (~BITS_SPS18_OCP_TH_8197F))
+#define BIT_GET_SPS18_OCP_TH_8197F(x) \
+ (((x) >> BIT_SHIFT_SPS18_OCP_TH_8197F) & BIT_MASK_SPS18_OCP_TH_8197F)
+#define BIT_SET_SPS18_OCP_TH_8197F(x, v) \
+ (BIT_CLEAR_SPS18_OCP_TH_8197F(x) | BIT_SPS18_OCP_TH_8197F(v))
+
+#define BIT_SHIFT_OCP_WINDOW_8197F 0
+#define BIT_MASK_OCP_WINDOW_8197F 0xffff
+#define BIT_OCP_WINDOW_8197F(x) \
+ (((x) & BIT_MASK_OCP_WINDOW_8197F) << BIT_SHIFT_OCP_WINDOW_8197F)
+#define BITS_OCP_WINDOW_8197F \
+ (BIT_MASK_OCP_WINDOW_8197F << BIT_SHIFT_OCP_WINDOW_8197F)
+#define BIT_CLEAR_OCP_WINDOW_8197F(x) ((x) & (~BITS_OCP_WINDOW_8197F))
+#define BIT_GET_OCP_WINDOW_8197F(x) \
+ (((x) >> BIT_SHIFT_OCP_WINDOW_8197F) & BIT_MASK_OCP_WINDOW_8197F)
+#define BIT_SET_OCP_WINDOW_8197F(x, v) \
+ (BIT_CLEAR_OCP_WINDOW_8197F(x) | BIT_OCP_WINDOW_8197F(v))
+
+/* 2 REG_RSV_CTRL_8197F */
+#define BIT_HREG_DBG_8197F BIT(23)
+#define BIT_WLMCUIOIF_8197F BIT(8)
+#define BIT_LOCK_ALL_EN_8197F BIT(7)
+#define BIT_R_DIS_PRST_8197F BIT(6)
+#define BIT_WLOCK_1C_B6_8197F BIT(5)
+#define BIT_WLOCK_40_8197F BIT(4)
+#define BIT_WLOCK_08_8197F BIT(3)
+#define BIT_WLOCK_04_8197F BIT(2)
+#define BIT_WLOCK_00_8197F BIT(1)
+#define BIT_WLOCK_ALL_8197F BIT(0)
+
+/* 2 REG_RF0_CTRL_8197F */
+#define BIT_RF0_SDMRSTB_8197F BIT(2)
+#define BIT_RF0_RSTB_8197F BIT(1)
+#define BIT_RF0_EN_8197F BIT(0)
+
+/* 2 REG_AFE_LDO_CTRL_8197F */
+
+#define BIT_SHIFT_LPLDH12_RSV_8197F 29
+#define BIT_MASK_LPLDH12_RSV_8197F 0x7
+#define BIT_LPLDH12_RSV_8197F(x) \
+ (((x) & BIT_MASK_LPLDH12_RSV_8197F) << BIT_SHIFT_LPLDH12_RSV_8197F)
+#define BITS_LPLDH12_RSV_8197F \
+ (BIT_MASK_LPLDH12_RSV_8197F << BIT_SHIFT_LPLDH12_RSV_8197F)
+#define BIT_CLEAR_LPLDH12_RSV_8197F(x) ((x) & (~BITS_LPLDH12_RSV_8197F))
+#define BIT_GET_LPLDH12_RSV_8197F(x) \
+ (((x) >> BIT_SHIFT_LPLDH12_RSV_8197F) & BIT_MASK_LPLDH12_RSV_8197F)
+#define BIT_SET_LPLDH12_RSV_8197F(x, v) \
+ (BIT_CLEAR_LPLDH12_RSV_8197F(x) | BIT_LPLDH12_RSV_8197F(v))
+
+#define BIT_LPLDH12_SLP_8197F BIT(28)
+
+#define BIT_SHIFT_LPLDH12_VADJ_8197F 24
+#define BIT_MASK_LPLDH12_VADJ_8197F 0xf
+#define BIT_LPLDH12_VADJ_8197F(x) \
+ (((x) & BIT_MASK_LPLDH12_VADJ_8197F) << BIT_SHIFT_LPLDH12_VADJ_8197F)
+#define BITS_LPLDH12_VADJ_8197F \
+ (BIT_MASK_LPLDH12_VADJ_8197F << BIT_SHIFT_LPLDH12_VADJ_8197F)
+#define BIT_CLEAR_LPLDH12_VADJ_8197F(x) ((x) & (~BITS_LPLDH12_VADJ_8197F))
+#define BIT_GET_LPLDH12_VADJ_8197F(x) \
+ (((x) >> BIT_SHIFT_LPLDH12_VADJ_8197F) & BIT_MASK_LPLDH12_VADJ_8197F)
+#define BIT_SET_LPLDH12_VADJ_8197F(x, v) \
+ (BIT_CLEAR_LPLDH12_VADJ_8197F(x) | BIT_LPLDH12_VADJ_8197F(v))
+
+#define BIT_LDH12_EN_8197F BIT(16)
+#define BIT_POW_REGU_P1_8197F BIT(10)
+#define BIT_LDOV12W_EN_8197F BIT(8)
+#define BIT_EX_XTAL_DRV_DIGI_8197F BIT(7)
+#define BIT_EX_XTAL_DRV_USB_8197F BIT(6)
+#define BIT_EX_XTAL_DRV_AFE_8197F BIT(5)
+#define BIT_EX_XTAL_DRV_RF2_8197F BIT(4)
+#define BIT_EX_XTAL_DRV_RF1_8197F BIT(3)
+#define BIT_POW_REGU_P0_8197F BIT(2)
+
+/* 2 REG_NOT_VALID_8197F */
+#define BIT_POW_PLL_LDO_8197F BIT(0)
+
+/* 2 REG_AFE_CTRL1_8197F */
+#define BIT_AGPIO_GPE_8197F BIT(31)
+
+#define BIT_SHIFT_XTAL_CAP_XI_8197F 25
+#define BIT_MASK_XTAL_CAP_XI_8197F 0x3f
+#define BIT_XTAL_CAP_XI_8197F(x) \
+ (((x) & BIT_MASK_XTAL_CAP_XI_8197F) << BIT_SHIFT_XTAL_CAP_XI_8197F)
+#define BITS_XTAL_CAP_XI_8197F \
+ (BIT_MASK_XTAL_CAP_XI_8197F << BIT_SHIFT_XTAL_CAP_XI_8197F)
+#define BIT_CLEAR_XTAL_CAP_XI_8197F(x) ((x) & (~BITS_XTAL_CAP_XI_8197F))
+#define BIT_GET_XTAL_CAP_XI_8197F(x) \
+ (((x) >> BIT_SHIFT_XTAL_CAP_XI_8197F) & BIT_MASK_XTAL_CAP_XI_8197F)
+#define BIT_SET_XTAL_CAP_XI_8197F(x, v) \
+ (BIT_CLEAR_XTAL_CAP_XI_8197F(x) | BIT_XTAL_CAP_XI_8197F(v))
+
+#define BIT_SHIFT_XTAL_DRV_DIGI_8197F 23
+#define BIT_MASK_XTAL_DRV_DIGI_8197F 0x3
+#define BIT_XTAL_DRV_DIGI_8197F(x) \
+ (((x) & BIT_MASK_XTAL_DRV_DIGI_8197F) << BIT_SHIFT_XTAL_DRV_DIGI_8197F)
+#define BITS_XTAL_DRV_DIGI_8197F \
+ (BIT_MASK_XTAL_DRV_DIGI_8197F << BIT_SHIFT_XTAL_DRV_DIGI_8197F)
+#define BIT_CLEAR_XTAL_DRV_DIGI_8197F(x) ((x) & (~BITS_XTAL_DRV_DIGI_8197F))
+#define BIT_GET_XTAL_DRV_DIGI_8197F(x) \
+ (((x) >> BIT_SHIFT_XTAL_DRV_DIGI_8197F) & BIT_MASK_XTAL_DRV_DIGI_8197F)
+#define BIT_SET_XTAL_DRV_DIGI_8197F(x, v) \
+ (BIT_CLEAR_XTAL_DRV_DIGI_8197F(x) | BIT_XTAL_DRV_DIGI_8197F(v))
+
+#define BIT_XTAL_DRV_USB_BIT1_8197F BIT(22)
+
+#define BIT_SHIFT_MAC_CLK_SEL_8197F 20
+#define BIT_MASK_MAC_CLK_SEL_8197F 0x3
+#define BIT_MAC_CLK_SEL_8197F(x) \
+ (((x) & BIT_MASK_MAC_CLK_SEL_8197F) << BIT_SHIFT_MAC_CLK_SEL_8197F)
+#define BITS_MAC_CLK_SEL_8197F \
+ (BIT_MASK_MAC_CLK_SEL_8197F << BIT_SHIFT_MAC_CLK_SEL_8197F)
+#define BIT_CLEAR_MAC_CLK_SEL_8197F(x) ((x) & (~BITS_MAC_CLK_SEL_8197F))
+#define BIT_GET_MAC_CLK_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_MAC_CLK_SEL_8197F) & BIT_MASK_MAC_CLK_SEL_8197F)
+#define BIT_SET_MAC_CLK_SEL_8197F(x, v) \
+ (BIT_CLEAR_MAC_CLK_SEL_8197F(x) | BIT_MAC_CLK_SEL_8197F(v))
+
+#define BIT_XTAL_DRV_USB_BIT0_8197F BIT(19)
+
+#define BIT_SHIFT_XTAL_DRV_AFE_8197F 17
+#define BIT_MASK_XTAL_DRV_AFE_8197F 0x3
+#define BIT_XTAL_DRV_AFE_8197F(x) \
+ (((x) & BIT_MASK_XTAL_DRV_AFE_8197F) << BIT_SHIFT_XTAL_DRV_AFE_8197F)
+#define BITS_XTAL_DRV_AFE_8197F \
+ (BIT_MASK_XTAL_DRV_AFE_8197F << BIT_SHIFT_XTAL_DRV_AFE_8197F)
+#define BIT_CLEAR_XTAL_DRV_AFE_8197F(x) ((x) & (~BITS_XTAL_DRV_AFE_8197F))
+#define BIT_GET_XTAL_DRV_AFE_8197F(x) \
+ (((x) >> BIT_SHIFT_XTAL_DRV_AFE_8197F) & BIT_MASK_XTAL_DRV_AFE_8197F)
+#define BIT_SET_XTAL_DRV_AFE_8197F(x, v) \
+ (BIT_CLEAR_XTAL_DRV_AFE_8197F(x) | BIT_XTAL_DRV_AFE_8197F(v))
+
+#define BIT_SHIFT_XTAL_DRV_RF2_8197F 15
+#define BIT_MASK_XTAL_DRV_RF2_8197F 0x3
+#define BIT_XTAL_DRV_RF2_8197F(x) \
+ (((x) & BIT_MASK_XTAL_DRV_RF2_8197F) << BIT_SHIFT_XTAL_DRV_RF2_8197F)
+#define BITS_XTAL_DRV_RF2_8197F \
+ (BIT_MASK_XTAL_DRV_RF2_8197F << BIT_SHIFT_XTAL_DRV_RF2_8197F)
+#define BIT_CLEAR_XTAL_DRV_RF2_8197F(x) ((x) & (~BITS_XTAL_DRV_RF2_8197F))
+#define BIT_GET_XTAL_DRV_RF2_8197F(x) \
+ (((x) >> BIT_SHIFT_XTAL_DRV_RF2_8197F) & BIT_MASK_XTAL_DRV_RF2_8197F)
+#define BIT_SET_XTAL_DRV_RF2_8197F(x, v) \
+ (BIT_CLEAR_XTAL_DRV_RF2_8197F(x) | BIT_XTAL_DRV_RF2_8197F(v))
+
+#define BIT_SHIFT_XTAL_DRV_RF1_8197F 13
+#define BIT_MASK_XTAL_DRV_RF1_8197F 0x3
+#define BIT_XTAL_DRV_RF1_8197F(x) \
+ (((x) & BIT_MASK_XTAL_DRV_RF1_8197F) << BIT_SHIFT_XTAL_DRV_RF1_8197F)
+#define BITS_XTAL_DRV_RF1_8197F \
+ (BIT_MASK_XTAL_DRV_RF1_8197F << BIT_SHIFT_XTAL_DRV_RF1_8197F)
+#define BIT_CLEAR_XTAL_DRV_RF1_8197F(x) ((x) & (~BITS_XTAL_DRV_RF1_8197F))
+#define BIT_GET_XTAL_DRV_RF1_8197F(x) \
+ (((x) >> BIT_SHIFT_XTAL_DRV_RF1_8197F) & BIT_MASK_XTAL_DRV_RF1_8197F)
+#define BIT_SET_XTAL_DRV_RF1_8197F(x, v) \
+ (BIT_CLEAR_XTAL_DRV_RF1_8197F(x) | BIT_XTAL_DRV_RF1_8197F(v))
+
+#define BIT_XTAL_DELAY_DIGI_8197F BIT(12)
+#define BIT_XTAL_DELAY_USB_8197F BIT(11)
+#define BIT_XTAL_DELAY_AFE_8197F BIT(10)
+#define BIT_XTAL_LP_V1_8197F BIT(9)
+#define BIT_XTAL_GM_SEP_V1_8197F BIT(8)
+#define BIT_XTAL_LDO_VREF_V1_8197F BIT(7)
+#define BIT_XTAL_XQSEL_RF_8197F BIT(6)
+#define BIT_XTAL_XQSEL_8197F BIT(5)
+
+#define BIT_SHIFT_XTAL_GMN_V1_8197F 3
+#define BIT_MASK_XTAL_GMN_V1_8197F 0x3
+#define BIT_XTAL_GMN_V1_8197F(x) \
+ (((x) & BIT_MASK_XTAL_GMN_V1_8197F) << BIT_SHIFT_XTAL_GMN_V1_8197F)
+#define BITS_XTAL_GMN_V1_8197F \
+ (BIT_MASK_XTAL_GMN_V1_8197F << BIT_SHIFT_XTAL_GMN_V1_8197F)
+#define BIT_CLEAR_XTAL_GMN_V1_8197F(x) ((x) & (~BITS_XTAL_GMN_V1_8197F))
+#define BIT_GET_XTAL_GMN_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_XTAL_GMN_V1_8197F) & BIT_MASK_XTAL_GMN_V1_8197F)
+#define BIT_SET_XTAL_GMN_V1_8197F(x, v) \
+ (BIT_CLEAR_XTAL_GMN_V1_8197F(x) | BIT_XTAL_GMN_V1_8197F(v))
+
+#define BIT_SHIFT_XTAL_GMP_V1_8197F 1
+#define BIT_MASK_XTAL_GMP_V1_8197F 0x3
+#define BIT_XTAL_GMP_V1_8197F(x) \
+ (((x) & BIT_MASK_XTAL_GMP_V1_8197F) << BIT_SHIFT_XTAL_GMP_V1_8197F)
+#define BITS_XTAL_GMP_V1_8197F \
+ (BIT_MASK_XTAL_GMP_V1_8197F << BIT_SHIFT_XTAL_GMP_V1_8197F)
+#define BIT_CLEAR_XTAL_GMP_V1_8197F(x) ((x) & (~BITS_XTAL_GMP_V1_8197F))
+#define BIT_GET_XTAL_GMP_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_XTAL_GMP_V1_8197F) & BIT_MASK_XTAL_GMP_V1_8197F)
+#define BIT_SET_XTAL_GMP_V1_8197F(x, v) \
+ (BIT_CLEAR_XTAL_GMP_V1_8197F(x) | BIT_XTAL_GMP_V1_8197F(v))
+
+#define BIT_XTAL_EN_8197F BIT(0)
+
+/* 2 REG_AFE_CTRL2_8197F */
+
+#define BIT_SHIFT_RS_SET_V2_8197F 26
+#define BIT_MASK_RS_SET_V2_8197F 0x7
+#define BIT_RS_SET_V2_8197F(x) \
+ (((x) & BIT_MASK_RS_SET_V2_8197F) << BIT_SHIFT_RS_SET_V2_8197F)
+#define BITS_RS_SET_V2_8197F \
+ (BIT_MASK_RS_SET_V2_8197F << BIT_SHIFT_RS_SET_V2_8197F)
+#define BIT_CLEAR_RS_SET_V2_8197F(x) ((x) & (~BITS_RS_SET_V2_8197F))
+#define BIT_GET_RS_SET_V2_8197F(x) \
+ (((x) >> BIT_SHIFT_RS_SET_V2_8197F) & BIT_MASK_RS_SET_V2_8197F)
+#define BIT_SET_RS_SET_V2_8197F(x, v) \
+ (BIT_CLEAR_RS_SET_V2_8197F(x) | BIT_RS_SET_V2_8197F(v))
+
+#define BIT_SHIFT_CP_BIAS_V2_8197F 18
+#define BIT_MASK_CP_BIAS_V2_8197F 0x7
+#define BIT_CP_BIAS_V2_8197F(x) \
+ (((x) & BIT_MASK_CP_BIAS_V2_8197F) << BIT_SHIFT_CP_BIAS_V2_8197F)
+#define BITS_CP_BIAS_V2_8197F \
+ (BIT_MASK_CP_BIAS_V2_8197F << BIT_SHIFT_CP_BIAS_V2_8197F)
+#define BIT_CLEAR_CP_BIAS_V2_8197F(x) ((x) & (~BITS_CP_BIAS_V2_8197F))
+#define BIT_GET_CP_BIAS_V2_8197F(x) \
+ (((x) >> BIT_SHIFT_CP_BIAS_V2_8197F) & BIT_MASK_CP_BIAS_V2_8197F)
+#define BIT_SET_CP_BIAS_V2_8197F(x, v) \
+ (BIT_CLEAR_CP_BIAS_V2_8197F(x) | BIT_CP_BIAS_V2_8197F(v))
+
+#define BIT_FREF_SEL_8197F BIT(16)
+
+#define BIT_SHIFT_MCCO_V2_8197F 14
+#define BIT_MASK_MCCO_V2_8197F 0x3
+#define BIT_MCCO_V2_8197F(x) \
+ (((x) & BIT_MASK_MCCO_V2_8197F) << BIT_SHIFT_MCCO_V2_8197F)
+#define BITS_MCCO_V2_8197F (BIT_MASK_MCCO_V2_8197F << BIT_SHIFT_MCCO_V2_8197F)
+#define BIT_CLEAR_MCCO_V2_8197F(x) ((x) & (~BITS_MCCO_V2_8197F))
+#define BIT_GET_MCCO_V2_8197F(x) \
+ (((x) >> BIT_SHIFT_MCCO_V2_8197F) & BIT_MASK_MCCO_V2_8197F)
+#define BIT_SET_MCCO_V2_8197F(x, v) \
+ (BIT_CLEAR_MCCO_V2_8197F(x) | BIT_MCCO_V2_8197F(v))
+
+#define BIT_SHIFT_CK320_EN_8197F 12
+#define BIT_MASK_CK320_EN_8197F 0x3
+#define BIT_CK320_EN_8197F(x) \
+ (((x) & BIT_MASK_CK320_EN_8197F) << BIT_SHIFT_CK320_EN_8197F)
+#define BITS_CK320_EN_8197F \
+ (BIT_MASK_CK320_EN_8197F << BIT_SHIFT_CK320_EN_8197F)
+#define BIT_CLEAR_CK320_EN_8197F(x) ((x) & (~BITS_CK320_EN_8197F))
+#define BIT_GET_CK320_EN_8197F(x) \
+ (((x) >> BIT_SHIFT_CK320_EN_8197F) & BIT_MASK_CK320_EN_8197F)
+#define BIT_SET_CK320_EN_8197F(x, v) \
+ (BIT_CLEAR_CK320_EN_8197F(x) | BIT_CK320_EN_8197F(v))
+
+#define BIT_AGPIO_GPO_8197F BIT(9)
+
+#define BIT_SHIFT_AGPIO_DRV_8197F 7
+#define BIT_MASK_AGPIO_DRV_8197F 0x3
+#define BIT_AGPIO_DRV_8197F(x) \
+ (((x) & BIT_MASK_AGPIO_DRV_8197F) << BIT_SHIFT_AGPIO_DRV_8197F)
+#define BITS_AGPIO_DRV_8197F \
+ (BIT_MASK_AGPIO_DRV_8197F << BIT_SHIFT_AGPIO_DRV_8197F)
+#define BIT_CLEAR_AGPIO_DRV_8197F(x) ((x) & (~BITS_AGPIO_DRV_8197F))
+#define BIT_GET_AGPIO_DRV_8197F(x) \
+ (((x) >> BIT_SHIFT_AGPIO_DRV_8197F) & BIT_MASK_AGPIO_DRV_8197F)
+#define BIT_SET_AGPIO_DRV_8197F(x, v) \
+ (BIT_CLEAR_AGPIO_DRV_8197F(x) | BIT_AGPIO_DRV_8197F(v))
+
+#define BIT_SHIFT_XTAL_CAP_XO_8197F 1
+#define BIT_MASK_XTAL_CAP_XO_8197F 0x3f
+#define BIT_XTAL_CAP_XO_8197F(x) \
+ (((x) & BIT_MASK_XTAL_CAP_XO_8197F) << BIT_SHIFT_XTAL_CAP_XO_8197F)
+#define BITS_XTAL_CAP_XO_8197F \
+ (BIT_MASK_XTAL_CAP_XO_8197F << BIT_SHIFT_XTAL_CAP_XO_8197F)
+#define BIT_CLEAR_XTAL_CAP_XO_8197F(x) ((x) & (~BITS_XTAL_CAP_XO_8197F))
+#define BIT_GET_XTAL_CAP_XO_8197F(x) \
+ (((x) >> BIT_SHIFT_XTAL_CAP_XO_8197F) & BIT_MASK_XTAL_CAP_XO_8197F)
+#define BIT_SET_XTAL_CAP_XO_8197F(x, v) \
+ (BIT_CLEAR_XTAL_CAP_XO_8197F(x) | BIT_XTAL_CAP_XO_8197F(v))
+
+#define BIT_POW_PLL_8197F BIT(0)
+
+/* 2 REG_AFE_CTRL3_8197F */
+
+#define BIT_SHIFT_PS_V2_8197F 7
+#define BIT_MASK_PS_V2_8197F 0x7
+#define BIT_PS_V2_8197F(x) \
+ (((x) & BIT_MASK_PS_V2_8197F) << BIT_SHIFT_PS_V2_8197F)
+#define BITS_PS_V2_8197F (BIT_MASK_PS_V2_8197F << BIT_SHIFT_PS_V2_8197F)
+#define BIT_CLEAR_PS_V2_8197F(x) ((x) & (~BITS_PS_V2_8197F))
+#define BIT_GET_PS_V2_8197F(x) \
+ (((x) >> BIT_SHIFT_PS_V2_8197F) & BIT_MASK_PS_V2_8197F)
+#define BIT_SET_PS_V2_8197F(x, v) \
+ (BIT_CLEAR_PS_V2_8197F(x) | BIT_PS_V2_8197F(v))
+
+#define BIT_PSEN_8197F BIT(6)
+#define BIT_DOGENB_8197F BIT(5)
+
+/* 2 REG_EFUSE_CTRL_8197F */
+#define BIT_EF_FLAG_8197F BIT(31)
+
+#define BIT_SHIFT_EF_PGPD_8197F 28
+#define BIT_MASK_EF_PGPD_8197F 0x7
+#define BIT_EF_PGPD_8197F(x) \
+ (((x) & BIT_MASK_EF_PGPD_8197F) << BIT_SHIFT_EF_PGPD_8197F)
+#define BITS_EF_PGPD_8197F (BIT_MASK_EF_PGPD_8197F << BIT_SHIFT_EF_PGPD_8197F)
+#define BIT_CLEAR_EF_PGPD_8197F(x) ((x) & (~BITS_EF_PGPD_8197F))
+#define BIT_GET_EF_PGPD_8197F(x) \
+ (((x) >> BIT_SHIFT_EF_PGPD_8197F) & BIT_MASK_EF_PGPD_8197F)
+#define BIT_SET_EF_PGPD_8197F(x, v) \
+ (BIT_CLEAR_EF_PGPD_8197F(x) | BIT_EF_PGPD_8197F(v))
+
+#define BIT_SHIFT_EF_RDT_8197F 24
+#define BIT_MASK_EF_RDT_8197F 0xf
+#define BIT_EF_RDT_8197F(x) \
+ (((x) & BIT_MASK_EF_RDT_8197F) << BIT_SHIFT_EF_RDT_8197F)
+#define BITS_EF_RDT_8197F (BIT_MASK_EF_RDT_8197F << BIT_SHIFT_EF_RDT_8197F)
+#define BIT_CLEAR_EF_RDT_8197F(x) ((x) & (~BITS_EF_RDT_8197F))
+#define BIT_GET_EF_RDT_8197F(x) \
+ (((x) >> BIT_SHIFT_EF_RDT_8197F) & BIT_MASK_EF_RDT_8197F)
+#define BIT_SET_EF_RDT_8197F(x, v) \
+ (BIT_CLEAR_EF_RDT_8197F(x) | BIT_EF_RDT_8197F(v))
+
+#define BIT_SHIFT_EF_PGTS_8197F 20
+#define BIT_MASK_EF_PGTS_8197F 0xf
+#define BIT_EF_PGTS_8197F(x) \
+ (((x) & BIT_MASK_EF_PGTS_8197F) << BIT_SHIFT_EF_PGTS_8197F)
+#define BITS_EF_PGTS_8197F (BIT_MASK_EF_PGTS_8197F << BIT_SHIFT_EF_PGTS_8197F)
+#define BIT_CLEAR_EF_PGTS_8197F(x) ((x) & (~BITS_EF_PGTS_8197F))
+#define BIT_GET_EF_PGTS_8197F(x) \
+ (((x) >> BIT_SHIFT_EF_PGTS_8197F) & BIT_MASK_EF_PGTS_8197F)
+#define BIT_SET_EF_PGTS_8197F(x, v) \
+ (BIT_CLEAR_EF_PGTS_8197F(x) | BIT_EF_PGTS_8197F(v))
+
+#define BIT_EF_PDWN_8197F BIT(19)
+#define BIT_EF_ALDEN_8197F BIT(18)
+
+#define BIT_SHIFT_EF_ADDR_8197F 8
+#define BIT_MASK_EF_ADDR_8197F 0x3ff
+#define BIT_EF_ADDR_8197F(x) \
+ (((x) & BIT_MASK_EF_ADDR_8197F) << BIT_SHIFT_EF_ADDR_8197F)
+#define BITS_EF_ADDR_8197F (BIT_MASK_EF_ADDR_8197F << BIT_SHIFT_EF_ADDR_8197F)
+#define BIT_CLEAR_EF_ADDR_8197F(x) ((x) & (~BITS_EF_ADDR_8197F))
+#define BIT_GET_EF_ADDR_8197F(x) \
+ (((x) >> BIT_SHIFT_EF_ADDR_8197F) & BIT_MASK_EF_ADDR_8197F)
+#define BIT_SET_EF_ADDR_8197F(x, v) \
+ (BIT_CLEAR_EF_ADDR_8197F(x) | BIT_EF_ADDR_8197F(v))
+
+#define BIT_SHIFT_EF_DATA_8197F 0
+#define BIT_MASK_EF_DATA_8197F 0xff
+#define BIT_EF_DATA_8197F(x) \
+ (((x) & BIT_MASK_EF_DATA_8197F) << BIT_SHIFT_EF_DATA_8197F)
+#define BITS_EF_DATA_8197F (BIT_MASK_EF_DATA_8197F << BIT_SHIFT_EF_DATA_8197F)
+#define BIT_CLEAR_EF_DATA_8197F(x) ((x) & (~BITS_EF_DATA_8197F))
+#define BIT_GET_EF_DATA_8197F(x) \
+ (((x) >> BIT_SHIFT_EF_DATA_8197F) & BIT_MASK_EF_DATA_8197F)
+#define BIT_SET_EF_DATA_8197F(x, v) \
+ (BIT_CLEAR_EF_DATA_8197F(x) | BIT_EF_DATA_8197F(v))
+
+/* 2 REG_LDO_EFUSE_CTRL_8197F */
+#define BIT_LDOE25_EN_8197F BIT(31)
+
+#define BIT_SHIFT_LDOE25_V12ADJ_L_8197F 27
+#define BIT_MASK_LDOE25_V12ADJ_L_8197F 0xf
+#define BIT_LDOE25_V12ADJ_L_8197F(x) \
+ (((x) & BIT_MASK_LDOE25_V12ADJ_L_8197F) \
+ << BIT_SHIFT_LDOE25_V12ADJ_L_8197F)
+#define BITS_LDOE25_V12ADJ_L_8197F \
+ (BIT_MASK_LDOE25_V12ADJ_L_8197F << BIT_SHIFT_LDOE25_V12ADJ_L_8197F)
+#define BIT_CLEAR_LDOE25_V12ADJ_L_8197F(x) ((x) & (~BITS_LDOE25_V12ADJ_L_8197F))
+#define BIT_GET_LDOE25_V12ADJ_L_8197F(x) \
+ (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_8197F) & \
+ BIT_MASK_LDOE25_V12ADJ_L_8197F)
+#define BIT_SET_LDOE25_V12ADJ_L_8197F(x, v) \
+ (BIT_CLEAR_LDOE25_V12ADJ_L_8197F(x) | BIT_LDOE25_V12ADJ_L_8197F(v))
+
+#define BIT_SHIFT_EF_SCAN_START_V1_8197F 16
+#define BIT_MASK_EF_SCAN_START_V1_8197F 0x3ff
+#define BIT_EF_SCAN_START_V1_8197F(x) \
+ (((x) & BIT_MASK_EF_SCAN_START_V1_8197F) \
+ << BIT_SHIFT_EF_SCAN_START_V1_8197F)
+#define BITS_EF_SCAN_START_V1_8197F \
+ (BIT_MASK_EF_SCAN_START_V1_8197F << BIT_SHIFT_EF_SCAN_START_V1_8197F)
+#define BIT_CLEAR_EF_SCAN_START_V1_8197F(x) \
+ ((x) & (~BITS_EF_SCAN_START_V1_8197F))
+#define BIT_GET_EF_SCAN_START_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_EF_SCAN_START_V1_8197F) & \
+ BIT_MASK_EF_SCAN_START_V1_8197F)
+#define BIT_SET_EF_SCAN_START_V1_8197F(x, v) \
+ (BIT_CLEAR_EF_SCAN_START_V1_8197F(x) | BIT_EF_SCAN_START_V1_8197F(v))
+
+#define BIT_SHIFT_EF_SCAN_END_8197F 12
+#define BIT_MASK_EF_SCAN_END_8197F 0xf
+#define BIT_EF_SCAN_END_8197F(x) \
+ (((x) & BIT_MASK_EF_SCAN_END_8197F) << BIT_SHIFT_EF_SCAN_END_8197F)
+#define BITS_EF_SCAN_END_8197F \
+ (BIT_MASK_EF_SCAN_END_8197F << BIT_SHIFT_EF_SCAN_END_8197F)
+#define BIT_CLEAR_EF_SCAN_END_8197F(x) ((x) & (~BITS_EF_SCAN_END_8197F))
+#define BIT_GET_EF_SCAN_END_8197F(x) \
+ (((x) >> BIT_SHIFT_EF_SCAN_END_8197F) & BIT_MASK_EF_SCAN_END_8197F)
+#define BIT_SET_EF_SCAN_END_8197F(x, v) \
+ (BIT_CLEAR_EF_SCAN_END_8197F(x) | BIT_EF_SCAN_END_8197F(v))
+
+#define BIT_SHIFT_EF_CELL_SEL_8197F 8
+#define BIT_MASK_EF_CELL_SEL_8197F 0x3
+#define BIT_EF_CELL_SEL_8197F(x) \
+ (((x) & BIT_MASK_EF_CELL_SEL_8197F) << BIT_SHIFT_EF_CELL_SEL_8197F)
+#define BITS_EF_CELL_SEL_8197F \
+ (BIT_MASK_EF_CELL_SEL_8197F << BIT_SHIFT_EF_CELL_SEL_8197F)
+#define BIT_CLEAR_EF_CELL_SEL_8197F(x) ((x) & (~BITS_EF_CELL_SEL_8197F))
+#define BIT_GET_EF_CELL_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_EF_CELL_SEL_8197F) & BIT_MASK_EF_CELL_SEL_8197F)
+#define BIT_SET_EF_CELL_SEL_8197F(x, v) \
+ (BIT_CLEAR_EF_CELL_SEL_8197F(x) | BIT_EF_CELL_SEL_8197F(v))
+
+#define BIT_EF_TRPT_8197F BIT(7)
+
+#define BIT_SHIFT_EF_TTHD_8197F 0
+#define BIT_MASK_EF_TTHD_8197F 0x7f
+#define BIT_EF_TTHD_8197F(x) \
+ (((x) & BIT_MASK_EF_TTHD_8197F) << BIT_SHIFT_EF_TTHD_8197F)
+#define BITS_EF_TTHD_8197F (BIT_MASK_EF_TTHD_8197F << BIT_SHIFT_EF_TTHD_8197F)
+#define BIT_CLEAR_EF_TTHD_8197F(x) ((x) & (~BITS_EF_TTHD_8197F))
+#define BIT_GET_EF_TTHD_8197F(x) \
+ (((x) >> BIT_SHIFT_EF_TTHD_8197F) & BIT_MASK_EF_TTHD_8197F)
+#define BIT_SET_EF_TTHD_8197F(x, v) \
+ (BIT_CLEAR_EF_TTHD_8197F(x) | BIT_EF_TTHD_8197F(v))
+
+/* 2 REG_PWR_OPTION_CTRL_8197F */
+
+#define BIT_SHIFT_DBG_SEL_V1_8197F 16
+#define BIT_MASK_DBG_SEL_V1_8197F 0xff
+#define BIT_DBG_SEL_V1_8197F(x) \
+ (((x) & BIT_MASK_DBG_SEL_V1_8197F) << BIT_SHIFT_DBG_SEL_V1_8197F)
+#define BITS_DBG_SEL_V1_8197F \
+ (BIT_MASK_DBG_SEL_V1_8197F << BIT_SHIFT_DBG_SEL_V1_8197F)
+#define BIT_CLEAR_DBG_SEL_V1_8197F(x) ((x) & (~BITS_DBG_SEL_V1_8197F))
+#define BIT_GET_DBG_SEL_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_DBG_SEL_V1_8197F) & BIT_MASK_DBG_SEL_V1_8197F)
+#define BIT_SET_DBG_SEL_V1_8197F(x, v) \
+ (BIT_CLEAR_DBG_SEL_V1_8197F(x) | BIT_DBG_SEL_V1_8197F(v))
+
+#define BIT_SHIFT_DBG_SEL_BYTE_8197F 14
+#define BIT_MASK_DBG_SEL_BYTE_8197F 0x3
+#define BIT_DBG_SEL_BYTE_8197F(x) \
+ (((x) & BIT_MASK_DBG_SEL_BYTE_8197F) << BIT_SHIFT_DBG_SEL_BYTE_8197F)
+#define BITS_DBG_SEL_BYTE_8197F \
+ (BIT_MASK_DBG_SEL_BYTE_8197F << BIT_SHIFT_DBG_SEL_BYTE_8197F)
+#define BIT_CLEAR_DBG_SEL_BYTE_8197F(x) ((x) & (~BITS_DBG_SEL_BYTE_8197F))
+#define BIT_GET_DBG_SEL_BYTE_8197F(x) \
+ (((x) >> BIT_SHIFT_DBG_SEL_BYTE_8197F) & BIT_MASK_DBG_SEL_BYTE_8197F)
+#define BIT_SET_DBG_SEL_BYTE_8197F(x, v) \
+ (BIT_CLEAR_DBG_SEL_BYTE_8197F(x) | BIT_DBG_SEL_BYTE_8197F(v))
+
+#define BIT_SHIFT_STD_L1_V1_8197F 12
+#define BIT_MASK_STD_L1_V1_8197F 0x3
+#define BIT_STD_L1_V1_8197F(x) \
+ (((x) & BIT_MASK_STD_L1_V1_8197F) << BIT_SHIFT_STD_L1_V1_8197F)
+#define BITS_STD_L1_V1_8197F \
+ (BIT_MASK_STD_L1_V1_8197F << BIT_SHIFT_STD_L1_V1_8197F)
+#define BIT_CLEAR_STD_L1_V1_8197F(x) ((x) & (~BITS_STD_L1_V1_8197F))
+#define BIT_GET_STD_L1_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_STD_L1_V1_8197F) & BIT_MASK_STD_L1_V1_8197F)
+#define BIT_SET_STD_L1_V1_8197F(x, v) \
+ (BIT_CLEAR_STD_L1_V1_8197F(x) | BIT_STD_L1_V1_8197F(v))
+
+#define BIT_SYSON_DBG_PAD_E2_8197F BIT(11)
+#define BIT_SYSON_LED_PAD_E2_8197F BIT(10)
+#define BIT_SYSON_GPEE_PAD_E2_8197F BIT(9)
+#define BIT_SYSON_PCI_PAD_E2_8197F BIT(8)
+#define BIT_AUTO_SW_LDO_VOL_EN_8197F BIT(7)
+
+#define BIT_SHIFT_SYSON_SPS0WWV_WT_8197F 4
+#define BIT_MASK_SYSON_SPS0WWV_WT_8197F 0x3
+#define BIT_SYSON_SPS0WWV_WT_8197F(x) \
+ (((x) & BIT_MASK_SYSON_SPS0WWV_WT_8197F) \
+ << BIT_SHIFT_SYSON_SPS0WWV_WT_8197F)
+#define BITS_SYSON_SPS0WWV_WT_8197F \
+ (BIT_MASK_SYSON_SPS0WWV_WT_8197F << BIT_SHIFT_SYSON_SPS0WWV_WT_8197F)
+#define BIT_CLEAR_SYSON_SPS0WWV_WT_8197F(x) \
+ ((x) & (~BITS_SYSON_SPS0WWV_WT_8197F))
+#define BIT_GET_SYSON_SPS0WWV_WT_8197F(x) \
+ (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8197F) & \
+ BIT_MASK_SYSON_SPS0WWV_WT_8197F)
+#define BIT_SET_SYSON_SPS0WWV_WT_8197F(x, v) \
+ (BIT_CLEAR_SYSON_SPS0WWV_WT_8197F(x) | BIT_SYSON_SPS0WWV_WT_8197F(v))
+
+#define BIT_SHIFT_SYSON_SPS0LDO_WT_8197F 2
+#define BIT_MASK_SYSON_SPS0LDO_WT_8197F 0x3
+#define BIT_SYSON_SPS0LDO_WT_8197F(x) \
+ (((x) & BIT_MASK_SYSON_SPS0LDO_WT_8197F) \
+ << BIT_SHIFT_SYSON_SPS0LDO_WT_8197F)
+#define BITS_SYSON_SPS0LDO_WT_8197F \
+ (BIT_MASK_SYSON_SPS0LDO_WT_8197F << BIT_SHIFT_SYSON_SPS0LDO_WT_8197F)
+#define BIT_CLEAR_SYSON_SPS0LDO_WT_8197F(x) \
+ ((x) & (~BITS_SYSON_SPS0LDO_WT_8197F))
+#define BIT_GET_SYSON_SPS0LDO_WT_8197F(x) \
+ (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8197F) & \
+ BIT_MASK_SYSON_SPS0LDO_WT_8197F)
+#define BIT_SET_SYSON_SPS0LDO_WT_8197F(x, v) \
+ (BIT_CLEAR_SYSON_SPS0LDO_WT_8197F(x) | BIT_SYSON_SPS0LDO_WT_8197F(v))
+
+#define BIT_SHIFT_SYSON_RCLK_SCALE_8197F 0
+#define BIT_MASK_SYSON_RCLK_SCALE_8197F 0x3
+#define BIT_SYSON_RCLK_SCALE_8197F(x) \
+ (((x) & BIT_MASK_SYSON_RCLK_SCALE_8197F) \
+ << BIT_SHIFT_SYSON_RCLK_SCALE_8197F)
+#define BITS_SYSON_RCLK_SCALE_8197F \
+ (BIT_MASK_SYSON_RCLK_SCALE_8197F << BIT_SHIFT_SYSON_RCLK_SCALE_8197F)
+#define BIT_CLEAR_SYSON_RCLK_SCALE_8197F(x) \
+ ((x) & (~BITS_SYSON_RCLK_SCALE_8197F))
+#define BIT_GET_SYSON_RCLK_SCALE_8197F(x) \
+ (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8197F) & \
+ BIT_MASK_SYSON_RCLK_SCALE_8197F)
+#define BIT_SET_SYSON_RCLK_SCALE_8197F(x, v) \
+ (BIT_CLEAR_SYSON_RCLK_SCALE_8197F(x) | BIT_SYSON_RCLK_SCALE_8197F(v))
+
+/* 2 REG_CAL_TIMER_8197F */
+
+#define BIT_SHIFT_MATCH_CNT_8197F 8
+#define BIT_MASK_MATCH_CNT_8197F 0xff
+#define BIT_MATCH_CNT_8197F(x) \
+ (((x) & BIT_MASK_MATCH_CNT_8197F) << BIT_SHIFT_MATCH_CNT_8197F)
+#define BITS_MATCH_CNT_8197F \
+ (BIT_MASK_MATCH_CNT_8197F << BIT_SHIFT_MATCH_CNT_8197F)
+#define BIT_CLEAR_MATCH_CNT_8197F(x) ((x) & (~BITS_MATCH_CNT_8197F))
+#define BIT_GET_MATCH_CNT_8197F(x) \
+ (((x) >> BIT_SHIFT_MATCH_CNT_8197F) & BIT_MASK_MATCH_CNT_8197F)
+#define BIT_SET_MATCH_CNT_8197F(x, v) \
+ (BIT_CLEAR_MATCH_CNT_8197F(x) | BIT_MATCH_CNT_8197F(v))
+
+#define BIT_SHIFT_CAL_SCAL_8197F 0
+#define BIT_MASK_CAL_SCAL_8197F 0xff
+#define BIT_CAL_SCAL_8197F(x) \
+ (((x) & BIT_MASK_CAL_SCAL_8197F) << BIT_SHIFT_CAL_SCAL_8197F)
+#define BITS_CAL_SCAL_8197F \
+ (BIT_MASK_CAL_SCAL_8197F << BIT_SHIFT_CAL_SCAL_8197F)
+#define BIT_CLEAR_CAL_SCAL_8197F(x) ((x) & (~BITS_CAL_SCAL_8197F))
+#define BIT_GET_CAL_SCAL_8197F(x) \
+ (((x) >> BIT_SHIFT_CAL_SCAL_8197F) & BIT_MASK_CAL_SCAL_8197F)
+#define BIT_SET_CAL_SCAL_8197F(x, v) \
+ (BIT_CLEAR_CAL_SCAL_8197F(x) | BIT_CAL_SCAL_8197F(v))
+
+/* 2 REG_ACLK_MON_8197F */
+
+#define BIT_SHIFT_RCLK_MON_8197F 5
+#define BIT_MASK_RCLK_MON_8197F 0x7ff
+#define BIT_RCLK_MON_8197F(x) \
+ (((x) & BIT_MASK_RCLK_MON_8197F) << BIT_SHIFT_RCLK_MON_8197F)
+#define BITS_RCLK_MON_8197F \
+ (BIT_MASK_RCLK_MON_8197F << BIT_SHIFT_RCLK_MON_8197F)
+#define BIT_CLEAR_RCLK_MON_8197F(x) ((x) & (~BITS_RCLK_MON_8197F))
+#define BIT_GET_RCLK_MON_8197F(x) \
+ (((x) >> BIT_SHIFT_RCLK_MON_8197F) & BIT_MASK_RCLK_MON_8197F)
+#define BIT_SET_RCLK_MON_8197F(x, v) \
+ (BIT_CLEAR_RCLK_MON_8197F(x) | BIT_RCLK_MON_8197F(v))
+
+#define BIT_CAL_EN_8197F BIT(4)
+
+#define BIT_SHIFT_DPSTU_8197F 2
+#define BIT_MASK_DPSTU_8197F 0x3
+#define BIT_DPSTU_8197F(x) \
+ (((x) & BIT_MASK_DPSTU_8197F) << BIT_SHIFT_DPSTU_8197F)
+#define BITS_DPSTU_8197F (BIT_MASK_DPSTU_8197F << BIT_SHIFT_DPSTU_8197F)
+#define BIT_CLEAR_DPSTU_8197F(x) ((x) & (~BITS_DPSTU_8197F))
+#define BIT_GET_DPSTU_8197F(x) \
+ (((x) >> BIT_SHIFT_DPSTU_8197F) & BIT_MASK_DPSTU_8197F)
+#define BIT_SET_DPSTU_8197F(x, v) \
+ (BIT_CLEAR_DPSTU_8197F(x) | BIT_DPSTU_8197F(v))
+
+#define BIT_SUS_16X_8197F BIT(1)
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_GPIO_MUXCFG_8197F */
+#define BIT_SIC_LOWEST_PRIORITY_8197F BIT(28)
+
+#define BIT_SHIFT_PIN_USECASE_8197F 24
+#define BIT_MASK_PIN_USECASE_8197F 0xf
+#define BIT_PIN_USECASE_8197F(x) \
+ (((x) & BIT_MASK_PIN_USECASE_8197F) << BIT_SHIFT_PIN_USECASE_8197F)
+#define BITS_PIN_USECASE_8197F \
+ (BIT_MASK_PIN_USECASE_8197F << BIT_SHIFT_PIN_USECASE_8197F)
+#define BIT_CLEAR_PIN_USECASE_8197F(x) ((x) & (~BITS_PIN_USECASE_8197F))
+#define BIT_GET_PIN_USECASE_8197F(x) \
+ (((x) >> BIT_SHIFT_PIN_USECASE_8197F) & BIT_MASK_PIN_USECASE_8197F)
+#define BIT_SET_PIN_USECASE_8197F(x, v) \
+ (BIT_CLEAR_PIN_USECASE_8197F(x) | BIT_PIN_USECASE_8197F(v))
+
+#define BIT_FSPI_EN_8197F BIT(19)
+#define BIT_WL_RTS_EXT_32K_SEL_8197F BIT(18)
+#define BIT_WLGP_SPI_EN_8197F BIT(16)
+#define BIT_SIC_LBK_8197F BIT(15)
+#define BIT_ENHTP_8197F BIT(14)
+#define BIT_WLPHY_DBG_EN_8197F BIT(13)
+#define BIT_ENSIC_8197F BIT(12)
+#define BIT_SIC_SWRST_8197F BIT(11)
+#define BIT_PO_WIFI_PTA_PINS_8197F BIT(10)
+#define BIT_BTCOEX_MBOX_EN_8197F BIT(9)
+#define BIT_ENUART_8197F BIT(8)
+
+#define BIT_SHIFT_BTMODE_8197F 6
+#define BIT_MASK_BTMODE_8197F 0x3
+#define BIT_BTMODE_8197F(x) \
+ (((x) & BIT_MASK_BTMODE_8197F) << BIT_SHIFT_BTMODE_8197F)
+#define BITS_BTMODE_8197F (BIT_MASK_BTMODE_8197F << BIT_SHIFT_BTMODE_8197F)
+#define BIT_CLEAR_BTMODE_8197F(x) ((x) & (~BITS_BTMODE_8197F))
+#define BIT_GET_BTMODE_8197F(x) \
+ (((x) >> BIT_SHIFT_BTMODE_8197F) & BIT_MASK_BTMODE_8197F)
+#define BIT_SET_BTMODE_8197F(x, v) \
+ (BIT_CLEAR_BTMODE_8197F(x) | BIT_BTMODE_8197F(v))
+
+#define BIT_ENBT_8197F BIT(5)
+#define BIT_EROM_EN_8197F BIT(4)
+#define BIT_WLRFE_6_7_EN_8197F BIT(3)
+#define BIT_WLRFE_4_5_EN_8197F BIT(2)
+
+#define BIT_SHIFT_GPIOSEL_8197F 0
+#define BIT_MASK_GPIOSEL_8197F 0x3
+#define BIT_GPIOSEL_8197F(x) \
+ (((x) & BIT_MASK_GPIOSEL_8197F) << BIT_SHIFT_GPIOSEL_8197F)
+#define BITS_GPIOSEL_8197F (BIT_MASK_GPIOSEL_8197F << BIT_SHIFT_GPIOSEL_8197F)
+#define BIT_CLEAR_GPIOSEL_8197F(x) ((x) & (~BITS_GPIOSEL_8197F))
+#define BIT_GET_GPIOSEL_8197F(x) \
+ (((x) >> BIT_SHIFT_GPIOSEL_8197F) & BIT_MASK_GPIOSEL_8197F)
+#define BIT_SET_GPIOSEL_8197F(x, v) \
+ (BIT_CLEAR_GPIOSEL_8197F(x) | BIT_GPIOSEL_8197F(v))
+
+/* 2 REG_GPIO_PIN_CTRL_8197F */
+
+#define BIT_SHIFT_GPIO_MOD_7_TO_0_8197F 24
+#define BIT_MASK_GPIO_MOD_7_TO_0_8197F 0xff
+#define BIT_GPIO_MOD_7_TO_0_8197F(x) \
+ (((x) & BIT_MASK_GPIO_MOD_7_TO_0_8197F) \
+ << BIT_SHIFT_GPIO_MOD_7_TO_0_8197F)
+#define BITS_GPIO_MOD_7_TO_0_8197F \
+ (BIT_MASK_GPIO_MOD_7_TO_0_8197F << BIT_SHIFT_GPIO_MOD_7_TO_0_8197F)
+#define BIT_CLEAR_GPIO_MOD_7_TO_0_8197F(x) ((x) & (~BITS_GPIO_MOD_7_TO_0_8197F))
+#define BIT_GET_GPIO_MOD_7_TO_0_8197F(x) \
+ (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8197F) & \
+ BIT_MASK_GPIO_MOD_7_TO_0_8197F)
+#define BIT_SET_GPIO_MOD_7_TO_0_8197F(x, v) \
+ (BIT_CLEAR_GPIO_MOD_7_TO_0_8197F(x) | BIT_GPIO_MOD_7_TO_0_8197F(v))
+
+#define BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8197F 16
+#define BIT_MASK_GPIO_IO_SEL_7_TO_0_8197F 0xff
+#define BIT_GPIO_IO_SEL_7_TO_0_8197F(x) \
+ (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8197F) \
+ << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8197F)
+#define BITS_GPIO_IO_SEL_7_TO_0_8197F \
+ (BIT_MASK_GPIO_IO_SEL_7_TO_0_8197F \
+ << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8197F)
+#define BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8197F(x) \
+ ((x) & (~BITS_GPIO_IO_SEL_7_TO_0_8197F))
+#define BIT_GET_GPIO_IO_SEL_7_TO_0_8197F(x) \
+ (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8197F) & \
+ BIT_MASK_GPIO_IO_SEL_7_TO_0_8197F)
+#define BIT_SET_GPIO_IO_SEL_7_TO_0_8197F(x, v) \
+ (BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8197F(x) | \
+ BIT_GPIO_IO_SEL_7_TO_0_8197F(v))
+
+#define BIT_SHIFT_GPIO_OUT_7_TO_0_8197F 8
+#define BIT_MASK_GPIO_OUT_7_TO_0_8197F 0xff
+#define BIT_GPIO_OUT_7_TO_0_8197F(x) \
+ (((x) & BIT_MASK_GPIO_OUT_7_TO_0_8197F) \
+ << BIT_SHIFT_GPIO_OUT_7_TO_0_8197F)
+#define BITS_GPIO_OUT_7_TO_0_8197F \
+ (BIT_MASK_GPIO_OUT_7_TO_0_8197F << BIT_SHIFT_GPIO_OUT_7_TO_0_8197F)
+#define BIT_CLEAR_GPIO_OUT_7_TO_0_8197F(x) ((x) & (~BITS_GPIO_OUT_7_TO_0_8197F))
+#define BIT_GET_GPIO_OUT_7_TO_0_8197F(x) \
+ (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8197F) & \
+ BIT_MASK_GPIO_OUT_7_TO_0_8197F)
+#define BIT_SET_GPIO_OUT_7_TO_0_8197F(x, v) \
+ (BIT_CLEAR_GPIO_OUT_7_TO_0_8197F(x) | BIT_GPIO_OUT_7_TO_0_8197F(v))
+
+#define BIT_SHIFT_GPIO_IN_7_TO_0_8197F 0
+#define BIT_MASK_GPIO_IN_7_TO_0_8197F 0xff
+#define BIT_GPIO_IN_7_TO_0_8197F(x) \
+ (((x) & BIT_MASK_GPIO_IN_7_TO_0_8197F) \
+ << BIT_SHIFT_GPIO_IN_7_TO_0_8197F)
+#define BITS_GPIO_IN_7_TO_0_8197F \
+ (BIT_MASK_GPIO_IN_7_TO_0_8197F << BIT_SHIFT_GPIO_IN_7_TO_0_8197F)
+#define BIT_CLEAR_GPIO_IN_7_TO_0_8197F(x) ((x) & (~BITS_GPIO_IN_7_TO_0_8197F))
+#define BIT_GET_GPIO_IN_7_TO_0_8197F(x) \
+ (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8197F) & \
+ BIT_MASK_GPIO_IN_7_TO_0_8197F)
+#define BIT_SET_GPIO_IN_7_TO_0_8197F(x, v) \
+ (BIT_CLEAR_GPIO_IN_7_TO_0_8197F(x) | BIT_GPIO_IN_7_TO_0_8197F(v))
+
+/* 2 REG_GPIO_INTM_8197F */
+
+#define BIT_SHIFT_MUXDBG_SEL_8197F 30
+#define BIT_MASK_MUXDBG_SEL_8197F 0x3
+#define BIT_MUXDBG_SEL_8197F(x) \
+ (((x) & BIT_MASK_MUXDBG_SEL_8197F) << BIT_SHIFT_MUXDBG_SEL_8197F)
+#define BITS_MUXDBG_SEL_8197F \
+ (BIT_MASK_MUXDBG_SEL_8197F << BIT_SHIFT_MUXDBG_SEL_8197F)
+#define BIT_CLEAR_MUXDBG_SEL_8197F(x) ((x) & (~BITS_MUXDBG_SEL_8197F))
+#define BIT_GET_MUXDBG_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_MUXDBG_SEL_8197F) & BIT_MASK_MUXDBG_SEL_8197F)
+#define BIT_SET_MUXDBG_SEL_8197F(x, v) \
+ (BIT_CLEAR_MUXDBG_SEL_8197F(x) | BIT_MUXDBG_SEL_8197F(v))
+
+#define BIT_EXTWOL_SEL_8197F BIT(17)
+#define BIT_EXTWOL_EN_8197F BIT(16)
+#define BIT_GPIOF_INT_MD_8197F BIT(15)
+#define BIT_GPIOE_INT_MD_8197F BIT(14)
+#define BIT_GPIOD_INT_MD_8197F BIT(13)
+#define BIT_GPIOC_INT_MD_8197F BIT(12)
+#define BIT_GPIOB_INT_MD_8197F BIT(11)
+#define BIT_GPIOA_INT_MD_8197F BIT(10)
+#define BIT_GPIO9_INT_MD_8197F BIT(9)
+#define BIT_GPIO8_INT_MD_8197F BIT(8)
+#define BIT_GPIO7_INT_MD_8197F BIT(7)
+#define BIT_GPIO6_INT_MD_8197F BIT(6)
+#define BIT_GPIO5_INT_MD_8197F BIT(5)
+#define BIT_GPIO4_INT_MD_8197F BIT(4)
+#define BIT_GPIO3_INT_MD_8197F BIT(3)
+#define BIT_GPIO2_INT_MD_8197F BIT(2)
+#define BIT_GPIO1_INT_MD_8197F BIT(1)
+#define BIT_GPIO0_INT_MD_8197F BIT(0)
+
+/* 2 REG_LED_CFG_8197F */
+#define BIT_LNAON_SEL_EN_8197F BIT(26)
+#define BIT_PAPE_SEL_EN_8197F BIT(25)
+#define BIT_DPDT_WLBT_SEL_8197F BIT(24)
+#define BIT_DPDT_SEL_EN_8197F BIT(23)
+#define BIT_LED2DIS_V1_8197F BIT(22)
+#define BIT_LED2EN_8197F BIT(21)
+#define BIT_LED2PL_8197F BIT(20)
+#define BIT_LED2SV_8197F BIT(19)
+
+#define BIT_SHIFT_LED2CM_8197F 16
+#define BIT_MASK_LED2CM_8197F 0x7
+#define BIT_LED2CM_8197F(x) \
+ (((x) & BIT_MASK_LED2CM_8197F) << BIT_SHIFT_LED2CM_8197F)
+#define BITS_LED2CM_8197F (BIT_MASK_LED2CM_8197F << BIT_SHIFT_LED2CM_8197F)
+#define BIT_CLEAR_LED2CM_8197F(x) ((x) & (~BITS_LED2CM_8197F))
+#define BIT_GET_LED2CM_8197F(x) \
+ (((x) >> BIT_SHIFT_LED2CM_8197F) & BIT_MASK_LED2CM_8197F)
+#define BIT_SET_LED2CM_8197F(x, v) \
+ (BIT_CLEAR_LED2CM_8197F(x) | BIT_LED2CM_8197F(v))
+
+#define BIT_LED1DIS_8197F BIT(15)
+#define BIT_LED1PL_8197F BIT(12)
+#define BIT_LED1SV_8197F BIT(11)
+
+#define BIT_SHIFT_LED1CM_8197F 8
+#define BIT_MASK_LED1CM_8197F 0x7
+#define BIT_LED1CM_8197F(x) \
+ (((x) & BIT_MASK_LED1CM_8197F) << BIT_SHIFT_LED1CM_8197F)
+#define BITS_LED1CM_8197F (BIT_MASK_LED1CM_8197F << BIT_SHIFT_LED1CM_8197F)
+#define BIT_CLEAR_LED1CM_8197F(x) ((x) & (~BITS_LED1CM_8197F))
+#define BIT_GET_LED1CM_8197F(x) \
+ (((x) >> BIT_SHIFT_LED1CM_8197F) & BIT_MASK_LED1CM_8197F)
+#define BIT_SET_LED1CM_8197F(x, v) \
+ (BIT_CLEAR_LED1CM_8197F(x) | BIT_LED1CM_8197F(v))
+
+#define BIT_LED0DIS_8197F BIT(7)
+
+#define BIT_SHIFT_AFE_LDO_SWR_CHECK_8197F 5
+#define BIT_MASK_AFE_LDO_SWR_CHECK_8197F 0x3
+#define BIT_AFE_LDO_SWR_CHECK_8197F(x) \
+ (((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8197F) \
+ << BIT_SHIFT_AFE_LDO_SWR_CHECK_8197F)
+#define BITS_AFE_LDO_SWR_CHECK_8197F \
+ (BIT_MASK_AFE_LDO_SWR_CHECK_8197F << BIT_SHIFT_AFE_LDO_SWR_CHECK_8197F)
+#define BIT_CLEAR_AFE_LDO_SWR_CHECK_8197F(x) \
+ ((x) & (~BITS_AFE_LDO_SWR_CHECK_8197F))
+#define BIT_GET_AFE_LDO_SWR_CHECK_8197F(x) \
+ (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8197F) & \
+ BIT_MASK_AFE_LDO_SWR_CHECK_8197F)
+#define BIT_SET_AFE_LDO_SWR_CHECK_8197F(x, v) \
+ (BIT_CLEAR_AFE_LDO_SWR_CHECK_8197F(x) | BIT_AFE_LDO_SWR_CHECK_8197F(v))
+
+#define BIT_LED0PL_8197F BIT(4)
+#define BIT_LED0SV_8197F BIT(3)
+
+#define BIT_SHIFT_LED0CM_8197F 0
+#define BIT_MASK_LED0CM_8197F 0x7
+#define BIT_LED0CM_8197F(x) \
+ (((x) & BIT_MASK_LED0CM_8197F) << BIT_SHIFT_LED0CM_8197F)
+#define BITS_LED0CM_8197F (BIT_MASK_LED0CM_8197F << BIT_SHIFT_LED0CM_8197F)
+#define BIT_CLEAR_LED0CM_8197F(x) ((x) & (~BITS_LED0CM_8197F))
+#define BIT_GET_LED0CM_8197F(x) \
+ (((x) >> BIT_SHIFT_LED0CM_8197F) & BIT_MASK_LED0CM_8197F)
+#define BIT_SET_LED0CM_8197F(x, v) \
+ (BIT_CLEAR_LED0CM_8197F(x) | BIT_LED0CM_8197F(v))
+
+/* 2 REG_FSIMR_8197F */
+#define BIT_FS_PDNINT_EN_8197F BIT(31)
+#define BIT_FS_SPS_OCP_INT_EN_8197F BIT(29)
+#define BIT_FS_PWMERR_INT_EN_8197F BIT(28)
+#define BIT_FS_GPIOF_INT_EN_8197F BIT(27)
+#define BIT_FS_GPIOE_INT_EN_8197F BIT(26)
+#define BIT_FS_GPIOD_INT_EN_8197F BIT(25)
+#define BIT_FS_GPIOC_INT_EN_8197F BIT(24)
+#define BIT_FS_GPIOB_INT_EN_8197F BIT(23)
+#define BIT_FS_GPIOA_INT_EN_8197F BIT(22)
+#define BIT_FS_GPIO9_INT_EN_8197F BIT(21)
+#define BIT_FS_GPIO8_INT_EN_8197F BIT(20)
+#define BIT_FS_GPIO7_INT_EN_8197F BIT(19)
+#define BIT_FS_GPIO6_INT_EN_8197F BIT(18)
+#define BIT_FS_GPIO5_INT_EN_8197F BIT(17)
+#define BIT_FS_GPIO4_INT_EN_8197F BIT(16)
+#define BIT_FS_GPIO3_INT_EN_8197F BIT(15)
+#define BIT_FS_GPIO2_INT_EN_8197F BIT(14)
+#define BIT_FS_GPIO1_INT_EN_8197F BIT(13)
+#define BIT_FS_GPIO0_INT_EN_8197F BIT(12)
+#define BIT_FS_HCI_SUS_EN_8197F BIT(11)
+#define BIT_FS_HCI_RES_EN_8197F BIT(10)
+#define BIT_FS_HCI_RESET_EN_8197F BIT(9)
+#define BIT_AXI_EXCEPT_FINT_EN_8197F BIT(8)
+#define BIT_FS_BTON_STS_UPDATE_MSK_EN_8197F BIT(7)
+#define BIT_ACT2RECOVERY_INT_EN_V1_8197F BIT(6)
+#define BIT_FS_TRPC_TO_INT_EN_8197F BIT(5)
+#define BIT_FS_RPC_O_T_INT_EN_8197F BIT(4)
+#define BIT_FS_32K_LEAVE_SETTING_MAK_8197F BIT(3)
+#define BIT_FS_32K_ENTER_SETTING_MAK_8197F BIT(2)
+#define BIT_FS_USB_LPMRSM_MSK_8197F BIT(1)
+#define BIT_FS_USB_LPMINT_MSK_8197F BIT(0)
+
+/* 2 REG_FSISR_8197F */
+#define BIT_FS_PDNINT_8197F BIT(31)
+#define BIT_FS_SPS_OCP_INT_8197F BIT(29)
+#define BIT_FS_PWMERR_INT_8197F BIT(28)
+#define BIT_FS_GPIOF_INT_8197F BIT(27)
+#define BIT_FS_GPIOE_INT_8197F BIT(26)
+#define BIT_FS_GPIOD_INT_8197F BIT(25)
+#define BIT_FS_GPIOC_INT_8197F BIT(24)
+#define BIT_FS_GPIOB_INT_8197F BIT(23)
+#define BIT_FS_GPIOA_INT_8197F BIT(22)
+#define BIT_FS_GPIO9_INT_8197F BIT(21)
+#define BIT_FS_GPIO8_INT_8197F BIT(20)
+#define BIT_FS_GPIO7_INT_8197F BIT(19)
+#define BIT_FS_GPIO6_INT_8197F BIT(18)
+#define BIT_FS_GPIO5_INT_8197F BIT(17)
+#define BIT_FS_GPIO4_INT_8197F BIT(16)
+#define BIT_FS_GPIO3_INT_8197F BIT(15)
+#define BIT_FS_GPIO2_INT_8197F BIT(14)
+#define BIT_FS_GPIO1_INT_8197F BIT(13)
+#define BIT_FS_GPIO0_INT_8197F BIT(12)
+#define BIT_FS_HCI_SUS_INT_8197F BIT(11)
+#define BIT_FS_HCI_RES_INT_8197F BIT(10)
+#define BIT_FS_HCI_RESET_INT_8197F BIT(9)
+#define BIT_AXI_EXCEPT_FINT_8197F BIT(8)
+#define BIT_FS_BTON_STS_UPDATE_INT_8197F BIT(7)
+#define BIT_ACT2RECOVERY_INT_V1_8197F BIT(6)
+#define BIT_FS_TRPC_TO_INT_INT_8197F BIT(5)
+#define BIT_FS_RPC_O_T_INT_INT_8197F BIT(4)
+#define BIT_FS_32K_LEAVE_SETTING_INT_8197F BIT(3)
+#define BIT_FS_32K_ENTER_SETTING_INT_8197F BIT(2)
+#define BIT_FS_USB_LPMRSM_INT_8197F BIT(1)
+#define BIT_FS_USB_LPMINT_INT_8197F BIT(0)
+
+/* 2 REG_HSIMR_8197F */
+#define BIT_GPIOF_INT_EN_8197F BIT(31)
+#define BIT_GPIOE_INT_EN_8197F BIT(30)
+#define BIT_GPIOD_INT_EN_8197F BIT(29)
+#define BIT_GPIOC_INT_EN_8197F BIT(28)
+#define BIT_GPIOB_INT_EN_8197F BIT(27)
+#define BIT_GPIOA_INT_EN_8197F BIT(26)
+#define BIT_GPIO9_INT_EN_8197F BIT(25)
+#define BIT_GPIO8_INT_EN_8197F BIT(24)
+#define BIT_GPIO7_INT_EN_8197F BIT(23)
+#define BIT_GPIO6_INT_EN_8197F BIT(22)
+#define BIT_GPIO5_INT_EN_8197F BIT(21)
+#define BIT_GPIO4_INT_EN_8197F BIT(20)
+#define BIT_GPIO3_INT_EN_8197F BIT(19)
+#define BIT_GPIO2_INT_EN_8197F BIT(18)
+#define BIT_GPIO1_INT_EN_8197F BIT(17)
+#define BIT_GPIO0_INT_EN_8197F BIT(16)
+#define BIT_AXI_EXCEPT_HINT_EN_8197F BIT(9)
+#define BIT_PDNINT_EN_V2_8197F BIT(8)
+#define BIT_PDNINT_EN_V1_8197F BIT(7)
+#define BIT_RON_INT_EN_V1_8197F BIT(6)
+#define BIT_SPS_OCP_INT_EN_V1_8197F BIT(5)
+#define BIT_GPIO15_0_INT_EN_V1_8197F BIT(0)
+
+/* 2 REG_HSISR_8197F */
+#define BIT_GPIOF_INT_8197F BIT(31)
+#define BIT_GPIOE_INT_8197F BIT(30)
+#define BIT_GPIOD_INT_8197F BIT(29)
+#define BIT_GPIOC_INT_8197F BIT(28)
+#define BIT_GPIOB_INT_8197F BIT(27)
+#define BIT_GPIOA_INT_8197F BIT(26)
+#define BIT_GPIO9_INT_8197F BIT(25)
+#define BIT_GPIO8_INT_8197F BIT(24)
+#define BIT_GPIO7_INT_8197F BIT(23)
+#define BIT_GPIO6_INT_8197F BIT(22)
+#define BIT_GPIO5_INT_8197F BIT(21)
+#define BIT_GPIO4_INT_8197F BIT(20)
+#define BIT_GPIO3_INT_8197F BIT(19)
+#define BIT_GPIO2_INT_8197F BIT(18)
+#define BIT_GPIO1_INT_8197F BIT(17)
+#define BIT_GPIO0_INT_8197F BIT(16)
+#define BIT_AXI_EXCEPT_HINT_8197F BIT(8)
+#define BIT_PDNINT_V1_8197F BIT(7)
+#define BIT_RON_INT_V1_8197F BIT(6)
+#define BIT_SPS_OCP_INT_V1_8197F BIT(5)
+#define BIT_GPIO15_0_INT_V1_8197F BIT(0)
+
+/* 2 REG_GPIO_EXT_CTRL_8197F */
+
+#define BIT_SHIFT_GPIO_MOD_15_TO_8_8197F 24
+#define BIT_MASK_GPIO_MOD_15_TO_8_8197F 0xff
+#define BIT_GPIO_MOD_15_TO_8_8197F(x) \
+ (((x) & BIT_MASK_GPIO_MOD_15_TO_8_8197F) \
+ << BIT_SHIFT_GPIO_MOD_15_TO_8_8197F)
+#define BITS_GPIO_MOD_15_TO_8_8197F \
+ (BIT_MASK_GPIO_MOD_15_TO_8_8197F << BIT_SHIFT_GPIO_MOD_15_TO_8_8197F)
+#define BIT_CLEAR_GPIO_MOD_15_TO_8_8197F(x) \
+ ((x) & (~BITS_GPIO_MOD_15_TO_8_8197F))
+#define BIT_GET_GPIO_MOD_15_TO_8_8197F(x) \
+ (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8197F) & \
+ BIT_MASK_GPIO_MOD_15_TO_8_8197F)
+#define BIT_SET_GPIO_MOD_15_TO_8_8197F(x, v) \
+ (BIT_CLEAR_GPIO_MOD_15_TO_8_8197F(x) | BIT_GPIO_MOD_15_TO_8_8197F(v))
+
+#define BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8197F 16
+#define BIT_MASK_GPIO_IO_SEL_15_TO_8_8197F 0xff
+#define BIT_GPIO_IO_SEL_15_TO_8_8197F(x) \
+ (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8197F) \
+ << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8197F)
+#define BITS_GPIO_IO_SEL_15_TO_8_8197F \
+ (BIT_MASK_GPIO_IO_SEL_15_TO_8_8197F \
+ << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8197F)
+#define BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8197F(x) \
+ ((x) & (~BITS_GPIO_IO_SEL_15_TO_8_8197F))
+#define BIT_GET_GPIO_IO_SEL_15_TO_8_8197F(x) \
+ (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8197F) & \
+ BIT_MASK_GPIO_IO_SEL_15_TO_8_8197F)
+#define BIT_SET_GPIO_IO_SEL_15_TO_8_8197F(x, v) \
+ (BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8197F(x) | \
+ BIT_GPIO_IO_SEL_15_TO_8_8197F(v))
+
+#define BIT_SHIFT_GPIO_OUT_15_TO_8_8197F 8
+#define BIT_MASK_GPIO_OUT_15_TO_8_8197F 0xff
+#define BIT_GPIO_OUT_15_TO_8_8197F(x) \
+ (((x) & BIT_MASK_GPIO_OUT_15_TO_8_8197F) \
+ << BIT_SHIFT_GPIO_OUT_15_TO_8_8197F)
+#define BITS_GPIO_OUT_15_TO_8_8197F \
+ (BIT_MASK_GPIO_OUT_15_TO_8_8197F << BIT_SHIFT_GPIO_OUT_15_TO_8_8197F)
+#define BIT_CLEAR_GPIO_OUT_15_TO_8_8197F(x) \
+ ((x) & (~BITS_GPIO_OUT_15_TO_8_8197F))
+#define BIT_GET_GPIO_OUT_15_TO_8_8197F(x) \
+ (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8197F) & \
+ BIT_MASK_GPIO_OUT_15_TO_8_8197F)
+#define BIT_SET_GPIO_OUT_15_TO_8_8197F(x, v) \
+ (BIT_CLEAR_GPIO_OUT_15_TO_8_8197F(x) | BIT_GPIO_OUT_15_TO_8_8197F(v))
+
+#define BIT_SHIFT_GPIO_IN_15_TO_8_8197F 0
+#define BIT_MASK_GPIO_IN_15_TO_8_8197F 0xff
+#define BIT_GPIO_IN_15_TO_8_8197F(x) \
+ (((x) & BIT_MASK_GPIO_IN_15_TO_8_8197F) \
+ << BIT_SHIFT_GPIO_IN_15_TO_8_8197F)
+#define BITS_GPIO_IN_15_TO_8_8197F \
+ (BIT_MASK_GPIO_IN_15_TO_8_8197F << BIT_SHIFT_GPIO_IN_15_TO_8_8197F)
+#define BIT_CLEAR_GPIO_IN_15_TO_8_8197F(x) ((x) & (~BITS_GPIO_IN_15_TO_8_8197F))
+#define BIT_GET_GPIO_IN_15_TO_8_8197F(x) \
+ (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8197F) & \
+ BIT_MASK_GPIO_IN_15_TO_8_8197F)
+#define BIT_SET_GPIO_IN_15_TO_8_8197F(x, v) \
+ (BIT_CLEAR_GPIO_IN_15_TO_8_8197F(x) | BIT_GPIO_IN_15_TO_8_8197F(v))
+
+/* 2 REG_PAD_CTRL1_8197F */
+#define BIT_PAPE_WLBT_SEL_8197F BIT(29)
+#define BIT_LNAON_WLBT_SEL_8197F BIT(28)
+#define BIT_BTGP_GPG3_FEN_8197F BIT(26)
+#define BIT_BTGP_GPG2_FEN_8197F BIT(25)
+#define BIT_BTGP_JTAG_EN_8197F BIT(24)
+#define BIT_XTAL_CLK_EXTARNAL_EN_8197F BIT(23)
+#define BIT_BTGP_UART0_EN_8197F BIT(22)
+#define BIT_BTGP_UART1_EN_8197F BIT(21)
+#define BIT_BTGP_SPI_EN_8197F BIT(20)
+#define BIT_BTGP_GPIO_E2_8197F BIT(19)
+#define BIT_BTGP_GPIO_EN_8197F BIT(18)
+
+#define BIT_SHIFT_BTGP_GPIO_SL_8197F 16
+#define BIT_MASK_BTGP_GPIO_SL_8197F 0x3
+#define BIT_BTGP_GPIO_SL_8197F(x) \
+ (((x) & BIT_MASK_BTGP_GPIO_SL_8197F) << BIT_SHIFT_BTGP_GPIO_SL_8197F)
+#define BITS_BTGP_GPIO_SL_8197F \
+ (BIT_MASK_BTGP_GPIO_SL_8197F << BIT_SHIFT_BTGP_GPIO_SL_8197F)
+#define BIT_CLEAR_BTGP_GPIO_SL_8197F(x) ((x) & (~BITS_BTGP_GPIO_SL_8197F))
+#define BIT_GET_BTGP_GPIO_SL_8197F(x) \
+ (((x) >> BIT_SHIFT_BTGP_GPIO_SL_8197F) & BIT_MASK_BTGP_GPIO_SL_8197F)
+#define BIT_SET_BTGP_GPIO_SL_8197F(x, v) \
+ (BIT_CLEAR_BTGP_GPIO_SL_8197F(x) | BIT_BTGP_GPIO_SL_8197F(v))
+
+#define BIT_PAD_SDIO_SR_8197F BIT(14)
+#define BIT_GPIO14_OUTPUT_PL_8197F BIT(13)
+#define BIT_HOST_WAKE_PAD_PULL_EN_8197F BIT(12)
+#define BIT_HOST_WAKE_PAD_SL_8197F BIT(11)
+#define BIT_PAD_LNAON_SR_8197F BIT(10)
+#define BIT_PAD_LNAON_E2_8197F BIT(9)
+#define BIT_SW_LNAON_G_SEL_DATA_8197F BIT(8)
+#define BIT_SW_LNAON_A_SEL_DATA_8197F BIT(7)
+#define BIT_PAD_PAPE_SR_8197F BIT(6)
+#define BIT_PAD_PAPE_E2_8197F BIT(5)
+#define BIT_SW_PAPE_G_SEL_DATA_8197F BIT(4)
+#define BIT_SW_PAPE_A_SEL_DATA_8197F BIT(3)
+#define BIT_PAD_DPDT_SR_8197F BIT(2)
+#define BIT_PAD_DPDT_PAD_E2_8197F BIT(1)
+#define BIT_SW_DPDT_SEL_DATA_8197F BIT(0)
+
+/* 2 REG_WL_BT_PWR_CTRL_8197F */
+#define BIT_ISO_BD2PP_8197F BIT(31)
+#define BIT_LDOV12B_EN_8197F BIT(30)
+#define BIT_CKEN_BTGPS_8197F BIT(29)
+#define BIT_FEN_BTGPS_8197F BIT(28)
+#define BIT_BTCPU_BOOTSEL_8197F BIT(27)
+#define BIT_SPI_SPEEDUP_8197F BIT(26)
+#define BIT_DEVWAKE_PAD_TYPE_SEL_8197F BIT(24)
+#define BIT_CLKREQ_PAD_TYPE_SEL_8197F BIT(23)
+#define BIT_ISO_BTPON2PP_8197F BIT(22)
+#define BIT_BT_HWROF_EN_8197F BIT(19)
+#define BIT_BT_FUNC_EN_8197F BIT(18)
+#define BIT_BT_HWPDN_SL_8197F BIT(17)
+#define BIT_BT_DISN_EN_8197F BIT(16)
+#define BIT_BT_PDN_PULL_EN_8197F BIT(15)
+#define BIT_WL_PDN_PULL_EN_8197F BIT(14)
+#define BIT_EXTERNAL_REQUEST_PL_8197F BIT(13)
+#define BIT_GPIO0_2_3_PULL_LOW_EN_8197F BIT(12)
+#define BIT_ISO_BA2PP_8197F BIT(11)
+#define BIT_BT_AFE_LDO_EN_8197F BIT(10)
+#define BIT_BT_AFE_PLL_EN_8197F BIT(9)
+#define BIT_BT_DIG_CLK_EN_8197F BIT(8)
+#define BIT_WL_DRV_EXIST_IDX_8197F BIT(5)
+#define BIT_DOP_EHPAD_8197F BIT(4)
+#define BIT_WL_HWROF_EN_8197F BIT(3)
+#define BIT_WL_FUNC_EN_8197F BIT(2)
+#define BIT_WL_HWPDN_SL_8197F BIT(1)
+#define BIT_WL_HWPDN_EN_8197F BIT(0)
+
+/* 2 REG_SDM_DEBUG_8197F */
+
+#define BIT_SHIFT_WLCLK_PHASE_8197F 0
+#define BIT_MASK_WLCLK_PHASE_8197F 0x1f
+#define BIT_WLCLK_PHASE_8197F(x) \
+ (((x) & BIT_MASK_WLCLK_PHASE_8197F) << BIT_SHIFT_WLCLK_PHASE_8197F)
+#define BITS_WLCLK_PHASE_8197F \
+ (BIT_MASK_WLCLK_PHASE_8197F << BIT_SHIFT_WLCLK_PHASE_8197F)
+#define BIT_CLEAR_WLCLK_PHASE_8197F(x) ((x) & (~BITS_WLCLK_PHASE_8197F))
+#define BIT_GET_WLCLK_PHASE_8197F(x) \
+ (((x) >> BIT_SHIFT_WLCLK_PHASE_8197F) & BIT_MASK_WLCLK_PHASE_8197F)
+#define BIT_SET_WLCLK_PHASE_8197F(x, v) \
+ (BIT_CLEAR_WLCLK_PHASE_8197F(x) | BIT_WLCLK_PHASE_8197F(v))
+
+/* 2 REG_SYS_SDIO_CTRL_8197F */
+#define BIT_DBG_GNT_WL_BT_8197F BIT(27)
+#define BIT_LTE_MUX_CTRL_PATH_8197F BIT(26)
+#define BIT_SDIO_INT_POLARITY_8197F BIT(19)
+#define BIT_SDIO_INT_8197F BIT(18)
+#define BIT_SDIO_OFF_EN_8197F BIT(17)
+#define BIT_SDIO_ON_EN_8197F BIT(16)
+
+/* 2 REG_HCI_OPT_CTRL_8197F */
+#define BIT_USB_HOST_PWR_OFF_EN_8197F BIT(12)
+#define BIT_SYM_LPS_BLOCK_EN_8197F BIT(11)
+#define BIT_USB_LPM_ACT_EN_8197F BIT(10)
+#define BIT_USB_LPM_NY_8197F BIT(9)
+#define BIT_USB_SUS_DIS_8197F BIT(8)
+
+#define BIT_SHIFT_SDIO_PAD_E_8197F 5
+#define BIT_MASK_SDIO_PAD_E_8197F 0x7
+#define BIT_SDIO_PAD_E_8197F(x) \
+ (((x) & BIT_MASK_SDIO_PAD_E_8197F) << BIT_SHIFT_SDIO_PAD_E_8197F)
+#define BITS_SDIO_PAD_E_8197F \
+ (BIT_MASK_SDIO_PAD_E_8197F << BIT_SHIFT_SDIO_PAD_E_8197F)
+#define BIT_CLEAR_SDIO_PAD_E_8197F(x) ((x) & (~BITS_SDIO_PAD_E_8197F))
+#define BIT_GET_SDIO_PAD_E_8197F(x) \
+ (((x) >> BIT_SHIFT_SDIO_PAD_E_8197F) & BIT_MASK_SDIO_PAD_E_8197F)
+#define BIT_SET_SDIO_PAD_E_8197F(x, v) \
+ (BIT_CLEAR_SDIO_PAD_E_8197F(x) | BIT_SDIO_PAD_E_8197F(v))
+
+#define BIT_USB_LPPLL_EN_8197F BIT(4)
+#define BIT_ROP_SW15_8197F BIT(2)
+#define BIT_PCI_CKRDY_OPT_8197F BIT(1)
+#define BIT_PCI_VAUX_EN_8197F BIT(0)
+
+/* 2 REG_AFE_CTRL4_8197F */
+#define BIT_RF1_SDMRSTB_8197F BIT(26)
+#define BIT_RF1_RSTB_8197F BIT(25)
+#define BIT_RF1_EN_8197F BIT(24)
+
+#define BIT_SHIFT_XTAL_LDO_8197F 20
+#define BIT_MASK_XTAL_LDO_8197F 0x7
+#define BIT_XTAL_LDO_8197F(x) \
+ (((x) & BIT_MASK_XTAL_LDO_8197F) << BIT_SHIFT_XTAL_LDO_8197F)
+#define BITS_XTAL_LDO_8197F \
+ (BIT_MASK_XTAL_LDO_8197F << BIT_SHIFT_XTAL_LDO_8197F)
+#define BIT_CLEAR_XTAL_LDO_8197F(x) ((x) & (~BITS_XTAL_LDO_8197F))
+#define BIT_GET_XTAL_LDO_8197F(x) \
+ (((x) >> BIT_SHIFT_XTAL_LDO_8197F) & BIT_MASK_XTAL_LDO_8197F)
+#define BIT_SET_XTAL_LDO_8197F(x, v) \
+ (BIT_CLEAR_XTAL_LDO_8197F(x) | BIT_XTAL_LDO_8197F(v))
+
+#define BIT_ADC_CK_SYNC_EN_8197F BIT(16)
+
+/* 2 REG_LDO_SWR_CTRL_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_MCUFW_CTRL_8197F */
+
+#define BIT_SHIFT_RPWM_8197F 24
+#define BIT_MASK_RPWM_8197F 0xff
+#define BIT_RPWM_8197F(x) (((x) & BIT_MASK_RPWM_8197F) << BIT_SHIFT_RPWM_8197F)
+#define BITS_RPWM_8197F (BIT_MASK_RPWM_8197F << BIT_SHIFT_RPWM_8197F)
+#define BIT_CLEAR_RPWM_8197F(x) ((x) & (~BITS_RPWM_8197F))
+#define BIT_GET_RPWM_8197F(x) \
+ (((x) >> BIT_SHIFT_RPWM_8197F) & BIT_MASK_RPWM_8197F)
+#define BIT_SET_RPWM_8197F(x, v) (BIT_CLEAR_RPWM_8197F(x) | BIT_RPWM_8197F(v))
+
+#define BIT_CPRST_8197F BIT(23)
+#define BIT_ANA_PORT_EN_8197F BIT(22)
+#define BIT_MAC_PORT_EN_8197F BIT(21)
+#define BIT_BOOT_FSPI_EN_8197F BIT(20)
+#define BIT_ROM_DLEN_8197F BIT(19)
+
+#define BIT_SHIFT_ROM_PGE_8197F 16
+#define BIT_MASK_ROM_PGE_8197F 0x7
+#define BIT_ROM_PGE_8197F(x) \
+ (((x) & BIT_MASK_ROM_PGE_8197F) << BIT_SHIFT_ROM_PGE_8197F)
+#define BITS_ROM_PGE_8197F (BIT_MASK_ROM_PGE_8197F << BIT_SHIFT_ROM_PGE_8197F)
+#define BIT_CLEAR_ROM_PGE_8197F(x) ((x) & (~BITS_ROM_PGE_8197F))
+#define BIT_GET_ROM_PGE_8197F(x) \
+ (((x) >> BIT_SHIFT_ROM_PGE_8197F) & BIT_MASK_ROM_PGE_8197F)
+#define BIT_SET_ROM_PGE_8197F(x, v) \
+ (BIT_CLEAR_ROM_PGE_8197F(x) | BIT_ROM_PGE_8197F(v))
+
+#define BIT_FW_INIT_RDY_8197F BIT(15)
+#define BIT_FW_DW_RDY_8197F BIT(14)
+
+#define BIT_SHIFT_CPU_CLK_SEL_8197F 12
+#define BIT_MASK_CPU_CLK_SEL_8197F 0x3
+#define BIT_CPU_CLK_SEL_8197F(x) \
+ (((x) & BIT_MASK_CPU_CLK_SEL_8197F) << BIT_SHIFT_CPU_CLK_SEL_8197F)
+#define BITS_CPU_CLK_SEL_8197F \
+ (BIT_MASK_CPU_CLK_SEL_8197F << BIT_SHIFT_CPU_CLK_SEL_8197F)
+#define BIT_CLEAR_CPU_CLK_SEL_8197F(x) ((x) & (~BITS_CPU_CLK_SEL_8197F))
+#define BIT_GET_CPU_CLK_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_CPU_CLK_SEL_8197F) & BIT_MASK_CPU_CLK_SEL_8197F)
+#define BIT_SET_CPU_CLK_SEL_8197F(x, v) \
+ (BIT_CLEAR_CPU_CLK_SEL_8197F(x) | BIT_CPU_CLK_SEL_8197F(v))
+
+#define BIT_CCLK_CHG_MASK_8197F BIT(11)
+#define BIT_FW_INIT_RDY_V1_8197F BIT(10)
+#define BIT_R_8051_SPD_8197F BIT(9)
+#define BIT_MCU_CLK_EN_8197F BIT(8)
+#define BIT_RAM_DL_SEL_8197F BIT(7)
+#define BIT_WINTINI_RDY_8197F BIT(6)
+#define BIT_RF_INIT_RDY_8197F BIT(5)
+#define BIT_BB_INIT_RDY_8197F BIT(4)
+#define BIT_MAC_INIT_RDY_8197F BIT(3)
+#define BIT_MCU_FWDL_RDY_8197F BIT(1)
+#define BIT_MCU_FWDL_EN_8197F BIT(0)
+
+/* 2 REG_MCU_TST_CFG_8197F */
+
+#define BIT_SHIFT_LBKTST_8197F 0
+#define BIT_MASK_LBKTST_8197F 0xffff
+#define BIT_LBKTST_8197F(x) \
+ (((x) & BIT_MASK_LBKTST_8197F) << BIT_SHIFT_LBKTST_8197F)
+#define BITS_LBKTST_8197F (BIT_MASK_LBKTST_8197F << BIT_SHIFT_LBKTST_8197F)
+#define BIT_CLEAR_LBKTST_8197F(x) ((x) & (~BITS_LBKTST_8197F))
+#define BIT_GET_LBKTST_8197F(x) \
+ (((x) >> BIT_SHIFT_LBKTST_8197F) & BIT_MASK_LBKTST_8197F)
+#define BIT_SET_LBKTST_8197F(x, v) \
+ (BIT_CLEAR_LBKTST_8197F(x) | BIT_LBKTST_8197F(v))
+
+/* 2 REG_HMEBOX_E0_E1_8197F */
+
+#define BIT_SHIFT_HOST_MSG_E1_8197F 16
+#define BIT_MASK_HOST_MSG_E1_8197F 0xffff
+#define BIT_HOST_MSG_E1_8197F(x) \
+ (((x) & BIT_MASK_HOST_MSG_E1_8197F) << BIT_SHIFT_HOST_MSG_E1_8197F)
+#define BITS_HOST_MSG_E1_8197F \
+ (BIT_MASK_HOST_MSG_E1_8197F << BIT_SHIFT_HOST_MSG_E1_8197F)
+#define BIT_CLEAR_HOST_MSG_E1_8197F(x) ((x) & (~BITS_HOST_MSG_E1_8197F))
+#define BIT_GET_HOST_MSG_E1_8197F(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_E1_8197F) & BIT_MASK_HOST_MSG_E1_8197F)
+#define BIT_SET_HOST_MSG_E1_8197F(x, v) \
+ (BIT_CLEAR_HOST_MSG_E1_8197F(x) | BIT_HOST_MSG_E1_8197F(v))
+
+#define BIT_SHIFT_HOST_MSG_E0_8197F 0
+#define BIT_MASK_HOST_MSG_E0_8197F 0xffff
+#define BIT_HOST_MSG_E0_8197F(x) \
+ (((x) & BIT_MASK_HOST_MSG_E0_8197F) << BIT_SHIFT_HOST_MSG_E0_8197F)
+#define BITS_HOST_MSG_E0_8197F \
+ (BIT_MASK_HOST_MSG_E0_8197F << BIT_SHIFT_HOST_MSG_E0_8197F)
+#define BIT_CLEAR_HOST_MSG_E0_8197F(x) ((x) & (~BITS_HOST_MSG_E0_8197F))
+#define BIT_GET_HOST_MSG_E0_8197F(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_E0_8197F) & BIT_MASK_HOST_MSG_E0_8197F)
+#define BIT_SET_HOST_MSG_E0_8197F(x, v) \
+ (BIT_CLEAR_HOST_MSG_E0_8197F(x) | BIT_HOST_MSG_E0_8197F(v))
+
+/* 2 REG_HMEBOX_E2_E3_8197F */
+
+#define BIT_SHIFT_HOST_MSG_E3_8197F 16
+#define BIT_MASK_HOST_MSG_E3_8197F 0xffff
+#define BIT_HOST_MSG_E3_8197F(x) \
+ (((x) & BIT_MASK_HOST_MSG_E3_8197F) << BIT_SHIFT_HOST_MSG_E3_8197F)
+#define BITS_HOST_MSG_E3_8197F \
+ (BIT_MASK_HOST_MSG_E3_8197F << BIT_SHIFT_HOST_MSG_E3_8197F)
+#define BIT_CLEAR_HOST_MSG_E3_8197F(x) ((x) & (~BITS_HOST_MSG_E3_8197F))
+#define BIT_GET_HOST_MSG_E3_8197F(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_E3_8197F) & BIT_MASK_HOST_MSG_E3_8197F)
+#define BIT_SET_HOST_MSG_E3_8197F(x, v) \
+ (BIT_CLEAR_HOST_MSG_E3_8197F(x) | BIT_HOST_MSG_E3_8197F(v))
+
+#define BIT_SHIFT_HOST_MSG_E2_8197F 0
+#define BIT_MASK_HOST_MSG_E2_8197F 0xffff
+#define BIT_HOST_MSG_E2_8197F(x) \
+ (((x) & BIT_MASK_HOST_MSG_E2_8197F) << BIT_SHIFT_HOST_MSG_E2_8197F)
+#define BITS_HOST_MSG_E2_8197F \
+ (BIT_MASK_HOST_MSG_E2_8197F << BIT_SHIFT_HOST_MSG_E2_8197F)
+#define BIT_CLEAR_HOST_MSG_E2_8197F(x) ((x) & (~BITS_HOST_MSG_E2_8197F))
+#define BIT_GET_HOST_MSG_E2_8197F(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_E2_8197F) & BIT_MASK_HOST_MSG_E2_8197F)
+#define BIT_SET_HOST_MSG_E2_8197F(x, v) \
+ (BIT_CLEAR_HOST_MSG_E2_8197F(x) | BIT_HOST_MSG_E2_8197F(v))
+
+/* 2 REG_WLLPS_CTRL_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_AFE_CTRL5_8197F */
+#define BIT_BB_DBG_SEL_AFE_SDM_V3_8197F BIT(31)
+#define BIT_ORDER_SDM_8197F BIT(30)
+#define BIT_RFE_SEL_SDM_8197F BIT(29)
+
+#define BIT_SHIFT_REF_SEL_8197F 25
+#define BIT_MASK_REF_SEL_8197F 0xf
+#define BIT_REF_SEL_8197F(x) \
+ (((x) & BIT_MASK_REF_SEL_8197F) << BIT_SHIFT_REF_SEL_8197F)
+#define BITS_REF_SEL_8197F (BIT_MASK_REF_SEL_8197F << BIT_SHIFT_REF_SEL_8197F)
+#define BIT_CLEAR_REF_SEL_8197F(x) ((x) & (~BITS_REF_SEL_8197F))
+#define BIT_GET_REF_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_REF_SEL_8197F) & BIT_MASK_REF_SEL_8197F)
+#define BIT_SET_REF_SEL_8197F(x, v) \
+ (BIT_CLEAR_REF_SEL_8197F(x) | BIT_REF_SEL_8197F(v))
+
+#define BIT_SHIFT_F0F_SDM_V2_8197F 12
+#define BIT_MASK_F0F_SDM_V2_8197F 0x1fff
+#define BIT_F0F_SDM_V2_8197F(x) \
+ (((x) & BIT_MASK_F0F_SDM_V2_8197F) << BIT_SHIFT_F0F_SDM_V2_8197F)
+#define BITS_F0F_SDM_V2_8197F \
+ (BIT_MASK_F0F_SDM_V2_8197F << BIT_SHIFT_F0F_SDM_V2_8197F)
+#define BIT_CLEAR_F0F_SDM_V2_8197F(x) ((x) & (~BITS_F0F_SDM_V2_8197F))
+#define BIT_GET_F0F_SDM_V2_8197F(x) \
+ (((x) >> BIT_SHIFT_F0F_SDM_V2_8197F) & BIT_MASK_F0F_SDM_V2_8197F)
+#define BIT_SET_F0F_SDM_V2_8197F(x, v) \
+ (BIT_CLEAR_F0F_SDM_V2_8197F(x) | BIT_F0F_SDM_V2_8197F(v))
+
+#define BIT_SHIFT_F0N_SDM_V2_8197F 9
+#define BIT_MASK_F0N_SDM_V2_8197F 0x7
+#define BIT_F0N_SDM_V2_8197F(x) \
+ (((x) & BIT_MASK_F0N_SDM_V2_8197F) << BIT_SHIFT_F0N_SDM_V2_8197F)
+#define BITS_F0N_SDM_V2_8197F \
+ (BIT_MASK_F0N_SDM_V2_8197F << BIT_SHIFT_F0N_SDM_V2_8197F)
+#define BIT_CLEAR_F0N_SDM_V2_8197F(x) ((x) & (~BITS_F0N_SDM_V2_8197F))
+#define BIT_GET_F0N_SDM_V2_8197F(x) \
+ (((x) >> BIT_SHIFT_F0N_SDM_V2_8197F) & BIT_MASK_F0N_SDM_V2_8197F)
+#define BIT_SET_F0N_SDM_V2_8197F(x, v) \
+ (BIT_CLEAR_F0N_SDM_V2_8197F(x) | BIT_F0N_SDM_V2_8197F(v))
+
+#define BIT_SHIFT_DIVN_SDM_V2_8197F 3
+#define BIT_MASK_DIVN_SDM_V2_8197F 0x3f
+#define BIT_DIVN_SDM_V2_8197F(x) \
+ (((x) & BIT_MASK_DIVN_SDM_V2_8197F) << BIT_SHIFT_DIVN_SDM_V2_8197F)
+#define BITS_DIVN_SDM_V2_8197F \
+ (BIT_MASK_DIVN_SDM_V2_8197F << BIT_SHIFT_DIVN_SDM_V2_8197F)
+#define BIT_CLEAR_DIVN_SDM_V2_8197F(x) ((x) & (~BITS_DIVN_SDM_V2_8197F))
+#define BIT_GET_DIVN_SDM_V2_8197F(x) \
+ (((x) >> BIT_SHIFT_DIVN_SDM_V2_8197F) & BIT_MASK_DIVN_SDM_V2_8197F)
+#define BIT_SET_DIVN_SDM_V2_8197F(x, v) \
+ (BIT_CLEAR_DIVN_SDM_V2_8197F(x) | BIT_DIVN_SDM_V2_8197F(v))
+
+#define BIT_SHIFT_DITHER_SDM_V2_8197F 0
+#define BIT_MASK_DITHER_SDM_V2_8197F 0x7
+#define BIT_DITHER_SDM_V2_8197F(x) \
+ (((x) & BIT_MASK_DITHER_SDM_V2_8197F) << BIT_SHIFT_DITHER_SDM_V2_8197F)
+#define BITS_DITHER_SDM_V2_8197F \
+ (BIT_MASK_DITHER_SDM_V2_8197F << BIT_SHIFT_DITHER_SDM_V2_8197F)
+#define BIT_CLEAR_DITHER_SDM_V2_8197F(x) ((x) & (~BITS_DITHER_SDM_V2_8197F))
+#define BIT_GET_DITHER_SDM_V2_8197F(x) \
+ (((x) >> BIT_SHIFT_DITHER_SDM_V2_8197F) & BIT_MASK_DITHER_SDM_V2_8197F)
+#define BIT_SET_DITHER_SDM_V2_8197F(x, v) \
+ (BIT_CLEAR_DITHER_SDM_V2_8197F(x) | BIT_DITHER_SDM_V2_8197F(v))
+
+/* 2 REG_GPIO_DEBOUNCE_CTRL_8197F */
+#define BIT_WLGP_DBC1EN_8197F BIT(15)
+
+#define BIT_SHIFT_WLGP_DBC1_8197F 8
+#define BIT_MASK_WLGP_DBC1_8197F 0xf
+#define BIT_WLGP_DBC1_8197F(x) \
+ (((x) & BIT_MASK_WLGP_DBC1_8197F) << BIT_SHIFT_WLGP_DBC1_8197F)
+#define BITS_WLGP_DBC1_8197F \
+ (BIT_MASK_WLGP_DBC1_8197F << BIT_SHIFT_WLGP_DBC1_8197F)
+#define BIT_CLEAR_WLGP_DBC1_8197F(x) ((x) & (~BITS_WLGP_DBC1_8197F))
+#define BIT_GET_WLGP_DBC1_8197F(x) \
+ (((x) >> BIT_SHIFT_WLGP_DBC1_8197F) & BIT_MASK_WLGP_DBC1_8197F)
+#define BIT_SET_WLGP_DBC1_8197F(x, v) \
+ (BIT_CLEAR_WLGP_DBC1_8197F(x) | BIT_WLGP_DBC1_8197F(v))
+
+#define BIT_WLGP_DBC0EN_8197F BIT(7)
+
+#define BIT_SHIFT_WLGP_DBC0_8197F 0
+#define BIT_MASK_WLGP_DBC0_8197F 0xf
+#define BIT_WLGP_DBC0_8197F(x) \
+ (((x) & BIT_MASK_WLGP_DBC0_8197F) << BIT_SHIFT_WLGP_DBC0_8197F)
+#define BITS_WLGP_DBC0_8197F \
+ (BIT_MASK_WLGP_DBC0_8197F << BIT_SHIFT_WLGP_DBC0_8197F)
+#define BIT_CLEAR_WLGP_DBC0_8197F(x) ((x) & (~BITS_WLGP_DBC0_8197F))
+#define BIT_GET_WLGP_DBC0_8197F(x) \
+ (((x) >> BIT_SHIFT_WLGP_DBC0_8197F) & BIT_MASK_WLGP_DBC0_8197F)
+#define BIT_SET_WLGP_DBC0_8197F(x, v) \
+ (BIT_CLEAR_WLGP_DBC0_8197F(x) | BIT_WLGP_DBC0_8197F(v))
+
+/* 2 REG_RPWM2_8197F */
+
+#define BIT_SHIFT_RPWM2_8197F 16
+#define BIT_MASK_RPWM2_8197F 0xffff
+#define BIT_RPWM2_8197F(x) \
+ (((x) & BIT_MASK_RPWM2_8197F) << BIT_SHIFT_RPWM2_8197F)
+#define BITS_RPWM2_8197F (BIT_MASK_RPWM2_8197F << BIT_SHIFT_RPWM2_8197F)
+#define BIT_CLEAR_RPWM2_8197F(x) ((x) & (~BITS_RPWM2_8197F))
+#define BIT_GET_RPWM2_8197F(x) \
+ (((x) >> BIT_SHIFT_RPWM2_8197F) & BIT_MASK_RPWM2_8197F)
+#define BIT_SET_RPWM2_8197F(x, v) \
+ (BIT_CLEAR_RPWM2_8197F(x) | BIT_RPWM2_8197F(v))
+
+/* 2 REG_SYSON_FSM_MON_8197F */
+
+#define BIT_SHIFT_FSM_MON_SEL_8197F 24
+#define BIT_MASK_FSM_MON_SEL_8197F 0x7
+#define BIT_FSM_MON_SEL_8197F(x) \
+ (((x) & BIT_MASK_FSM_MON_SEL_8197F) << BIT_SHIFT_FSM_MON_SEL_8197F)
+#define BITS_FSM_MON_SEL_8197F \
+ (BIT_MASK_FSM_MON_SEL_8197F << BIT_SHIFT_FSM_MON_SEL_8197F)
+#define BIT_CLEAR_FSM_MON_SEL_8197F(x) ((x) & (~BITS_FSM_MON_SEL_8197F))
+#define BIT_GET_FSM_MON_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_FSM_MON_SEL_8197F) & BIT_MASK_FSM_MON_SEL_8197F)
+#define BIT_SET_FSM_MON_SEL_8197F(x, v) \
+ (BIT_CLEAR_FSM_MON_SEL_8197F(x) | BIT_FSM_MON_SEL_8197F(v))
+
+#define BIT_DOP_ELDO_8197F BIT(23)
+#define BIT_FSM_MON_UPD_8197F BIT(15)
+
+#define BIT_SHIFT_FSM_PAR_8197F 0
+#define BIT_MASK_FSM_PAR_8197F 0x7fff
+#define BIT_FSM_PAR_8197F(x) \
+ (((x) & BIT_MASK_FSM_PAR_8197F) << BIT_SHIFT_FSM_PAR_8197F)
+#define BITS_FSM_PAR_8197F (BIT_MASK_FSM_PAR_8197F << BIT_SHIFT_FSM_PAR_8197F)
+#define BIT_CLEAR_FSM_PAR_8197F(x) ((x) & (~BITS_FSM_PAR_8197F))
+#define BIT_GET_FSM_PAR_8197F(x) \
+ (((x) >> BIT_SHIFT_FSM_PAR_8197F) & BIT_MASK_FSM_PAR_8197F)
+#define BIT_SET_FSM_PAR_8197F(x, v) \
+ (BIT_CLEAR_FSM_PAR_8197F(x) | BIT_FSM_PAR_8197F(v))
+
+/* 2 REG_AFE_CTRL6_8197F */
+
+#define BIT_SHIFT_TSFT_SEL_V1_8197F 0
+#define BIT_MASK_TSFT_SEL_V1_8197F 0x7
+#define BIT_TSFT_SEL_V1_8197F(x) \
+ (((x) & BIT_MASK_TSFT_SEL_V1_8197F) << BIT_SHIFT_TSFT_SEL_V1_8197F)
+#define BITS_TSFT_SEL_V1_8197F \
+ (BIT_MASK_TSFT_SEL_V1_8197F << BIT_SHIFT_TSFT_SEL_V1_8197F)
+#define BIT_CLEAR_TSFT_SEL_V1_8197F(x) ((x) & (~BITS_TSFT_SEL_V1_8197F))
+#define BIT_GET_TSFT_SEL_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_TSFT_SEL_V1_8197F) & BIT_MASK_TSFT_SEL_V1_8197F)
+#define BIT_SET_TSFT_SEL_V1_8197F(x, v) \
+ (BIT_CLEAR_TSFT_SEL_V1_8197F(x) | BIT_TSFT_SEL_V1_8197F(v))
+
+/* 2 REG_PMC_DBG_CTRL1_8197F */
+#define BIT_BT_INT_EN_8197F BIT(31)
+
+#define BIT_SHIFT_RD_WR_WIFI_BT_INFO_8197F 16
+#define BIT_MASK_RD_WR_WIFI_BT_INFO_8197F 0x7fff
+#define BIT_RD_WR_WIFI_BT_INFO_8197F(x) \
+ (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8197F) \
+ << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8197F)
+#define BITS_RD_WR_WIFI_BT_INFO_8197F \
+ (BIT_MASK_RD_WR_WIFI_BT_INFO_8197F \
+ << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8197F)
+#define BIT_CLEAR_RD_WR_WIFI_BT_INFO_8197F(x) \
+ ((x) & (~BITS_RD_WR_WIFI_BT_INFO_8197F))
+#define BIT_GET_RD_WR_WIFI_BT_INFO_8197F(x) \
+ (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8197F) & \
+ BIT_MASK_RD_WR_WIFI_BT_INFO_8197F)
+#define BIT_SET_RD_WR_WIFI_BT_INFO_8197F(x, v) \
+ (BIT_CLEAR_RD_WR_WIFI_BT_INFO_8197F(x) | \
+ BIT_RD_WR_WIFI_BT_INFO_8197F(v))
+
+#define BIT_PMC_WR_OVF_8197F BIT(8)
+
+#define BIT_SHIFT_WLPMC_ERRINT_8197F 0
+#define BIT_MASK_WLPMC_ERRINT_8197F 0xff
+#define BIT_WLPMC_ERRINT_8197F(x) \
+ (((x) & BIT_MASK_WLPMC_ERRINT_8197F) << BIT_SHIFT_WLPMC_ERRINT_8197F)
+#define BITS_WLPMC_ERRINT_8197F \
+ (BIT_MASK_WLPMC_ERRINT_8197F << BIT_SHIFT_WLPMC_ERRINT_8197F)
+#define BIT_CLEAR_WLPMC_ERRINT_8197F(x) ((x) & (~BITS_WLPMC_ERRINT_8197F))
+#define BIT_GET_WLPMC_ERRINT_8197F(x) \
+ (((x) >> BIT_SHIFT_WLPMC_ERRINT_8197F) & BIT_MASK_WLPMC_ERRINT_8197F)
+#define BIT_SET_WLPMC_ERRINT_8197F(x, v) \
+ (BIT_CLEAR_WLPMC_ERRINT_8197F(x) | BIT_WLPMC_ERRINT_8197F(v))
+
+/* 2 REG_AFE_CTRL7_8197F */
+
+#define BIT_SHIFT_SEL_V_8197F 30
+#define BIT_MASK_SEL_V_8197F 0x3
+#define BIT_SEL_V_8197F(x) \
+ (((x) & BIT_MASK_SEL_V_8197F) << BIT_SHIFT_SEL_V_8197F)
+#define BITS_SEL_V_8197F (BIT_MASK_SEL_V_8197F << BIT_SHIFT_SEL_V_8197F)
+#define BIT_CLEAR_SEL_V_8197F(x) ((x) & (~BITS_SEL_V_8197F))
+#define BIT_GET_SEL_V_8197F(x) \
+ (((x) >> BIT_SHIFT_SEL_V_8197F) & BIT_MASK_SEL_V_8197F)
+#define BIT_SET_SEL_V_8197F(x, v) \
+ (BIT_CLEAR_SEL_V_8197F(x) | BIT_SEL_V_8197F(v))
+
+#define BIT_SEL_LDO_PC_8197F BIT(29)
+
+#define BIT_SHIFT_CK_MON_SEL_V2_8197F 26
+#define BIT_MASK_CK_MON_SEL_V2_8197F 0x7
+#define BIT_CK_MON_SEL_V2_8197F(x) \
+ (((x) & BIT_MASK_CK_MON_SEL_V2_8197F) << BIT_SHIFT_CK_MON_SEL_V2_8197F)
+#define BITS_CK_MON_SEL_V2_8197F \
+ (BIT_MASK_CK_MON_SEL_V2_8197F << BIT_SHIFT_CK_MON_SEL_V2_8197F)
+#define BIT_CLEAR_CK_MON_SEL_V2_8197F(x) ((x) & (~BITS_CK_MON_SEL_V2_8197F))
+#define BIT_GET_CK_MON_SEL_V2_8197F(x) \
+ (((x) >> BIT_SHIFT_CK_MON_SEL_V2_8197F) & BIT_MASK_CK_MON_SEL_V2_8197F)
+#define BIT_SET_CK_MON_SEL_V2_8197F(x, v) \
+ (BIT_CLEAR_CK_MON_SEL_V2_8197F(x) | BIT_CK_MON_SEL_V2_8197F(v))
+
+#define BIT_CK_MON_EN_8197F BIT(25)
+#define BIT_FREF_EDGE_8197F BIT(24)
+#define BIT_CK320M_EN_8197F BIT(23)
+#define BIT_CK_5M_EN_8197F BIT(22)
+#define BIT_TESTEN_8197F BIT(21)
+
+/* 2 REG_HIMR0_8197F */
+#define BIT_TIMEOUT_INTERRUPT2_MASK_8197F BIT(31)
+#define BIT_TIMEOUT_INTERRUTP1_MASK_8197F BIT(30)
+#define BIT_PSTIMEOUT_MSK_8197F BIT(29)
+#define BIT_GTINT4_MSK_8197F BIT(28)
+#define BIT_GTINT3_MSK_8197F BIT(27)
+#define BIT_TXBCN0ERR_MSK_8197F BIT(26)
+#define BIT_TXBCN0OK_MSK_8197F BIT(25)
+#define BIT_TSF_BIT32_TOGGLE_MSK_8197F BIT(24)
+#define BIT_BCNDMAINT0_MSK_8197F BIT(20)
+#define BIT_BCNDERR0_MSK_8197F BIT(16)
+#define BIT_HSISR_IND_ON_INT_MSK_8197F BIT(15)
+#define BIT_HISR3_IND_INT_MSK_8197F BIT(14)
+#define BIT_HISR2_IND_INT_MSK_8197F BIT(13)
+#define BIT_CTWEND_MSK_8197F BIT(12)
+#define BIT_HISR1_IND_MSK_8197F BIT(11)
+#define BIT_C2HCMD_MSK_8197F BIT(10)
+#define BIT_CPWM2_MSK_8197F BIT(9)
+#define BIT_CPWM_MSK_8197F BIT(8)
+#define BIT_HIGHDOK_MSK_8197F BIT(7)
+#define BIT_MGTDOK_MSK_8197F BIT(6)
+#define BIT_BKDOK_MSK_8197F BIT(5)
+#define BIT_BEDOK_MSK_8197F BIT(4)
+#define BIT_VIDOK_MSK_8197F BIT(3)
+#define BIT_VODOK_MSK_8197F BIT(2)
+#define BIT_RDU_MSK_8197F BIT(1)
+#define BIT_RXOK_MSK_8197F BIT(0)
+
+/* 2 REG_HISR0_8197F */
+#define BIT_PSTIMEOUT2_8197F BIT(31)
+#define BIT_PSTIMEOUT1_8197F BIT(30)
+#define BIT_PSTIMEOUT_8197F BIT(29)
+#define BIT_GTINT4_8197F BIT(28)
+#define BIT_GTINT3_8197F BIT(27)
+#define BIT_TXBCN0ERR_8197F BIT(26)
+#define BIT_TXBCN0OK_8197F BIT(25)
+#define BIT_TSF_BIT32_TOGGLE_8197F BIT(24)
+#define BIT_BCNDMAINT0_8197F BIT(20)
+#define BIT_BCNDERR0_8197F BIT(16)
+#define BIT_HSISR_IND_ON_INT_8197F BIT(15)
+#define BIT_HISR3_IND_INT_8197F BIT(14)
+#define BIT_HISR2_IND_INT_8197F BIT(13)
+#define BIT_CTWEND_8197F BIT(12)
+#define BIT_HISR1_IND_INT_8197F BIT(11)
+#define BIT_C2HCMD_8197F BIT(10)
+#define BIT_CPWM2_8197F BIT(9)
+#define BIT_CPWM_8197F BIT(8)
+#define BIT_HIGHDOK_8197F BIT(7)
+#define BIT_MGTDOK_8197F BIT(6)
+#define BIT_BKDOK_8197F BIT(5)
+#define BIT_BEDOK_8197F BIT(4)
+#define BIT_VIDOK_8197F BIT(3)
+#define BIT_VODOK_8197F BIT(2)
+#define BIT_RDU_8197F BIT(1)
+#define BIT_RXOK_8197F BIT(0)
+
+/* 2 REG_HIMR1_8197F */
+#define BIT_BTON_STS_UPDATE_MSK_8197F BIT(29)
+#define BIT_MCU_ERR_MASK_8197F BIT(28)
+#define BIT_BCNDMAINT7__MSK_8197F BIT(27)
+#define BIT_BCNDMAINT6__MSK_8197F BIT(26)
+#define BIT_BCNDMAINT5__MSK_8197F BIT(25)
+#define BIT_BCNDMAINT4__MSK_8197F BIT(24)
+#define BIT_BCNDMAINT3_MSK_8197F BIT(23)
+#define BIT_BCNDMAINT2_MSK_8197F BIT(22)
+#define BIT_BCNDMAINT1_MSK_8197F BIT(21)
+#define BIT_BCNDERR7_MSK_8197F BIT(20)
+#define BIT_BCNDERR6_MSK_8197F BIT(19)
+#define BIT_BCNDERR5_MSK_8197F BIT(18)
+#define BIT_BCNDERR4_MSK_8197F BIT(17)
+#define BIT_BCNDERR3_MSK_8197F BIT(16)
+#define BIT_BCNDERR2_MSK_8197F BIT(15)
+#define BIT_BCNDERR1_MSK_8197F BIT(14)
+#define BIT_ATIMEND_E_MSK_8197F BIT(13)
+#define BIT_ATIMEND__MSK_8197F BIT(12)
+#define BIT_TXERR_MSK_8197F BIT(11)
+#define BIT_RXERR_MSK_8197F BIT(10)
+#define BIT_TXFOVW_MSK_8197F BIT(9)
+#define BIT_FOVW_MSK_8197F BIT(8)
+
+/* 2 REG_HISR1_8197F */
+#define BIT_BTON_STS_UPDATE_INT_8197F BIT(29)
+#define BIT_MCU_ERR_8197F BIT(28)
+#define BIT_BCNDMAINT7_8197F BIT(27)
+#define BIT_BCNDMAINT6_8197F BIT(26)
+#define BIT_BCNDMAINT5_8197F BIT(25)
+#define BIT_BCNDMAINT4_8197F BIT(24)
+#define BIT_BCNDMAINT3_8197F BIT(23)
+#define BIT_BCNDMAINT2_8197F BIT(22)
+#define BIT_BCNDMAINT1_8197F BIT(21)
+#define BIT_BCNDERR7_8197F BIT(20)
+#define BIT_BCNDERR6_8197F BIT(19)
+#define BIT_BCNDERR5_8197F BIT(18)
+#define BIT_BCNDERR4_8197F BIT(17)
+#define BIT_BCNDERR3_8197F BIT(16)
+#define BIT_BCNDERR2_8197F BIT(15)
+#define BIT_BCNDERR1_8197F BIT(14)
+#define BIT_ATIMEND_E_8197F BIT(13)
+#define BIT_ATIMEND_8197F BIT(12)
+#define BIT_TXERR_INT_8197F BIT(11)
+#define BIT_RXERR_INT_8197F BIT(10)
+#define BIT_TXFOVW_8197F BIT(9)
+#define BIT_FOVW_8197F BIT(8)
+
+/* 2 REG_DBG_PORT_SEL_8197F */
+
+#define BIT_SHIFT_DEBUG_ST_8197F 0
+#define BIT_MASK_DEBUG_ST_8197F 0xffffffffL
+#define BIT_DEBUG_ST_8197F(x) \
+ (((x) & BIT_MASK_DEBUG_ST_8197F) << BIT_SHIFT_DEBUG_ST_8197F)
+#define BITS_DEBUG_ST_8197F \
+ (BIT_MASK_DEBUG_ST_8197F << BIT_SHIFT_DEBUG_ST_8197F)
+#define BIT_CLEAR_DEBUG_ST_8197F(x) ((x) & (~BITS_DEBUG_ST_8197F))
+#define BIT_GET_DEBUG_ST_8197F(x) \
+ (((x) >> BIT_SHIFT_DEBUG_ST_8197F) & BIT_MASK_DEBUG_ST_8197F)
+#define BIT_SET_DEBUG_ST_8197F(x, v) \
+ (BIT_CLEAR_DEBUG_ST_8197F(x) | BIT_DEBUG_ST_8197F(v))
+
+/* 2 REG_PAD_CTRL2_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+#define BIT_LD_B12V_EN_V1_8197F BIT(7)
+#define BIT_EECS_IOSEL_V1_8197F BIT(6)
+#define BIT_EECS_DATA_O_V1_8197F BIT(5)
+#define BIT_EECS_DATA_I_V1_8197F BIT(4)
+#define BIT_EESK_IOSEL_V1_8197F BIT(2)
+#define BIT_EESK_DATA_O_V1_8197F BIT(1)
+#define BIT_EESK_DATA_I_V1_8197F BIT(0)
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_PMC_DBG_CTRL2_8197F */
+
+#define BIT_SHIFT_EFUSE_BURN_GNT_8197F 24
+#define BIT_MASK_EFUSE_BURN_GNT_8197F 0xff
+#define BIT_EFUSE_BURN_GNT_8197F(x) \
+ (((x) & BIT_MASK_EFUSE_BURN_GNT_8197F) \
+ << BIT_SHIFT_EFUSE_BURN_GNT_8197F)
+#define BITS_EFUSE_BURN_GNT_8197F \
+ (BIT_MASK_EFUSE_BURN_GNT_8197F << BIT_SHIFT_EFUSE_BURN_GNT_8197F)
+#define BIT_CLEAR_EFUSE_BURN_GNT_8197F(x) ((x) & (~BITS_EFUSE_BURN_GNT_8197F))
+#define BIT_GET_EFUSE_BURN_GNT_8197F(x) \
+ (((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8197F) & \
+ BIT_MASK_EFUSE_BURN_GNT_8197F)
+#define BIT_SET_EFUSE_BURN_GNT_8197F(x, v) \
+ (BIT_CLEAR_EFUSE_BURN_GNT_8197F(x) | BIT_EFUSE_BURN_GNT_8197F(v))
+
+#define BIT_STOP_WL_PMC_8197F BIT(9)
+#define BIT_STOP_SYM_PMC_8197F BIT(8)
+#define BIT_REG_RST_WLPMC_8197F BIT(5)
+#define BIT_REG_RST_PD12N_8197F BIT(4)
+#define BIT_SYSON_DIS_WLREG_WRMSK_8197F BIT(3)
+#define BIT_SYSON_DIS_PMCREG_WRMSK_8197F BIT(2)
+
+#define BIT_SHIFT_SYSON_REG_ARB_8197F 0
+#define BIT_MASK_SYSON_REG_ARB_8197F 0x3
+#define BIT_SYSON_REG_ARB_8197F(x) \
+ (((x) & BIT_MASK_SYSON_REG_ARB_8197F) << BIT_SHIFT_SYSON_REG_ARB_8197F)
+#define BITS_SYSON_REG_ARB_8197F \
+ (BIT_MASK_SYSON_REG_ARB_8197F << BIT_SHIFT_SYSON_REG_ARB_8197F)
+#define BIT_CLEAR_SYSON_REG_ARB_8197F(x) ((x) & (~BITS_SYSON_REG_ARB_8197F))
+#define BIT_GET_SYSON_REG_ARB_8197F(x) \
+ (((x) >> BIT_SHIFT_SYSON_REG_ARB_8197F) & BIT_MASK_SYSON_REG_ARB_8197F)
+#define BIT_SET_SYSON_REG_ARB_8197F(x, v) \
+ (BIT_CLEAR_SYSON_REG_ARB_8197F(x) | BIT_SYSON_REG_ARB_8197F(v))
+
+/* 2 REG_BIST_CTRL_8197F */
+#define BIT_BIST_USB_DIS_8197F BIT(27)
+#define BIT_BIST_PCI_DIS_8197F BIT(26)
+#define BIT_BIST_BT_DIS_8197F BIT(25)
+#define BIT_BIST_WL_DIS_8197F BIT(24)
+
+#define BIT_SHIFT_BIST_RPT_SEL_8197F 16
+#define BIT_MASK_BIST_RPT_SEL_8197F 0xf
+#define BIT_BIST_RPT_SEL_8197F(x) \
+ (((x) & BIT_MASK_BIST_RPT_SEL_8197F) << BIT_SHIFT_BIST_RPT_SEL_8197F)
+#define BITS_BIST_RPT_SEL_8197F \
+ (BIT_MASK_BIST_RPT_SEL_8197F << BIT_SHIFT_BIST_RPT_SEL_8197F)
+#define BIT_CLEAR_BIST_RPT_SEL_8197F(x) ((x) & (~BITS_BIST_RPT_SEL_8197F))
+#define BIT_GET_BIST_RPT_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_BIST_RPT_SEL_8197F) & BIT_MASK_BIST_RPT_SEL_8197F)
+#define BIT_SET_BIST_RPT_SEL_8197F(x, v) \
+ (BIT_CLEAR_BIST_RPT_SEL_8197F(x) | BIT_BIST_RPT_SEL_8197F(v))
+
+#define BIT_BIST_RESUME_PS_8197F BIT(4)
+#define BIT_BIST_RESUME_8197F BIT(3)
+#define BIT_BIST_NORMAL_8197F BIT(2)
+#define BIT_BIST_RSTN_8197F BIT(1)
+#define BIT_BIST_CLK_EN_8197F BIT(0)
+
+/* 2 REG_BIST_RPT_8197F */
+
+#define BIT_SHIFT_MBIST_REPORT_8197F 0
+#define BIT_MASK_MBIST_REPORT_8197F 0xffffffffL
+#define BIT_MBIST_REPORT_8197F(x) \
+ (((x) & BIT_MASK_MBIST_REPORT_8197F) << BIT_SHIFT_MBIST_REPORT_8197F)
+#define BITS_MBIST_REPORT_8197F \
+ (BIT_MASK_MBIST_REPORT_8197F << BIT_SHIFT_MBIST_REPORT_8197F)
+#define BIT_CLEAR_MBIST_REPORT_8197F(x) ((x) & (~BITS_MBIST_REPORT_8197F))
+#define BIT_GET_MBIST_REPORT_8197F(x) \
+ (((x) >> BIT_SHIFT_MBIST_REPORT_8197F) & BIT_MASK_MBIST_REPORT_8197F)
+#define BIT_SET_MBIST_REPORT_8197F(x, v) \
+ (BIT_CLEAR_MBIST_REPORT_8197F(x) | BIT_MBIST_REPORT_8197F(v))
+
+/* 2 REG_MEM_CTRL_8197F */
+#define BIT_UMEM_RME_8197F BIT(31)
+
+#define BIT_SHIFT_BT_SPRAM_8197F 28
+#define BIT_MASK_BT_SPRAM_8197F 0x3
+#define BIT_BT_SPRAM_8197F(x) \
+ (((x) & BIT_MASK_BT_SPRAM_8197F) << BIT_SHIFT_BT_SPRAM_8197F)
+#define BITS_BT_SPRAM_8197F \
+ (BIT_MASK_BT_SPRAM_8197F << BIT_SHIFT_BT_SPRAM_8197F)
+#define BIT_CLEAR_BT_SPRAM_8197F(x) ((x) & (~BITS_BT_SPRAM_8197F))
+#define BIT_GET_BT_SPRAM_8197F(x) \
+ (((x) >> BIT_SHIFT_BT_SPRAM_8197F) & BIT_MASK_BT_SPRAM_8197F)
+#define BIT_SET_BT_SPRAM_8197F(x, v) \
+ (BIT_CLEAR_BT_SPRAM_8197F(x) | BIT_BT_SPRAM_8197F(v))
+
+#define BIT_SHIFT_BT_ROM_8197F 24
+#define BIT_MASK_BT_ROM_8197F 0xf
+#define BIT_BT_ROM_8197F(x) \
+ (((x) & BIT_MASK_BT_ROM_8197F) << BIT_SHIFT_BT_ROM_8197F)
+#define BITS_BT_ROM_8197F (BIT_MASK_BT_ROM_8197F << BIT_SHIFT_BT_ROM_8197F)
+#define BIT_CLEAR_BT_ROM_8197F(x) ((x) & (~BITS_BT_ROM_8197F))
+#define BIT_GET_BT_ROM_8197F(x) \
+ (((x) >> BIT_SHIFT_BT_ROM_8197F) & BIT_MASK_BT_ROM_8197F)
+#define BIT_SET_BT_ROM_8197F(x, v) \
+ (BIT_CLEAR_BT_ROM_8197F(x) | BIT_BT_ROM_8197F(v))
+
+#define BIT_SHIFT_PCI_DPRAM_8197F 10
+#define BIT_MASK_PCI_DPRAM_8197F 0x3
+#define BIT_PCI_DPRAM_8197F(x) \
+ (((x) & BIT_MASK_PCI_DPRAM_8197F) << BIT_SHIFT_PCI_DPRAM_8197F)
+#define BITS_PCI_DPRAM_8197F \
+ (BIT_MASK_PCI_DPRAM_8197F << BIT_SHIFT_PCI_DPRAM_8197F)
+#define BIT_CLEAR_PCI_DPRAM_8197F(x) ((x) & (~BITS_PCI_DPRAM_8197F))
+#define BIT_GET_PCI_DPRAM_8197F(x) \
+ (((x) >> BIT_SHIFT_PCI_DPRAM_8197F) & BIT_MASK_PCI_DPRAM_8197F)
+#define BIT_SET_PCI_DPRAM_8197F(x, v) \
+ (BIT_CLEAR_PCI_DPRAM_8197F(x) | BIT_PCI_DPRAM_8197F(v))
+
+#define BIT_SHIFT_PCI_SPRAM_8197F 8
+#define BIT_MASK_PCI_SPRAM_8197F 0x3
+#define BIT_PCI_SPRAM_8197F(x) \
+ (((x) & BIT_MASK_PCI_SPRAM_8197F) << BIT_SHIFT_PCI_SPRAM_8197F)
+#define BITS_PCI_SPRAM_8197F \
+ (BIT_MASK_PCI_SPRAM_8197F << BIT_SHIFT_PCI_SPRAM_8197F)
+#define BIT_CLEAR_PCI_SPRAM_8197F(x) ((x) & (~BITS_PCI_SPRAM_8197F))
+#define BIT_GET_PCI_SPRAM_8197F(x) \
+ (((x) >> BIT_SHIFT_PCI_SPRAM_8197F) & BIT_MASK_PCI_SPRAM_8197F)
+#define BIT_SET_PCI_SPRAM_8197F(x, v) \
+ (BIT_CLEAR_PCI_SPRAM_8197F(x) | BIT_PCI_SPRAM_8197F(v))
+
+#define BIT_SHIFT_USB_SPRAM_8197F 6
+#define BIT_MASK_USB_SPRAM_8197F 0x3
+#define BIT_USB_SPRAM_8197F(x) \
+ (((x) & BIT_MASK_USB_SPRAM_8197F) << BIT_SHIFT_USB_SPRAM_8197F)
+#define BITS_USB_SPRAM_8197F \
+ (BIT_MASK_USB_SPRAM_8197F << BIT_SHIFT_USB_SPRAM_8197F)
+#define BIT_CLEAR_USB_SPRAM_8197F(x) ((x) & (~BITS_USB_SPRAM_8197F))
+#define BIT_GET_USB_SPRAM_8197F(x) \
+ (((x) >> BIT_SHIFT_USB_SPRAM_8197F) & BIT_MASK_USB_SPRAM_8197F)
+#define BIT_SET_USB_SPRAM_8197F(x, v) \
+ (BIT_CLEAR_USB_SPRAM_8197F(x) | BIT_USB_SPRAM_8197F(v))
+
+#define BIT_SHIFT_USB_SPRF_8197F 4
+#define BIT_MASK_USB_SPRF_8197F 0x3
+#define BIT_USB_SPRF_8197F(x) \
+ (((x) & BIT_MASK_USB_SPRF_8197F) << BIT_SHIFT_USB_SPRF_8197F)
+#define BITS_USB_SPRF_8197F \
+ (BIT_MASK_USB_SPRF_8197F << BIT_SHIFT_USB_SPRF_8197F)
+#define BIT_CLEAR_USB_SPRF_8197F(x) ((x) & (~BITS_USB_SPRF_8197F))
+#define BIT_GET_USB_SPRF_8197F(x) \
+ (((x) >> BIT_SHIFT_USB_SPRF_8197F) & BIT_MASK_USB_SPRF_8197F)
+#define BIT_SET_USB_SPRF_8197F(x, v) \
+ (BIT_CLEAR_USB_SPRF_8197F(x) | BIT_USB_SPRF_8197F(v))
+
+#define BIT_SHIFT_MCU_ROM_8197F 0
+#define BIT_MASK_MCU_ROM_8197F 0xf
+#define BIT_MCU_ROM_8197F(x) \
+ (((x) & BIT_MASK_MCU_ROM_8197F) << BIT_SHIFT_MCU_ROM_8197F)
+#define BITS_MCU_ROM_8197F (BIT_MASK_MCU_ROM_8197F << BIT_SHIFT_MCU_ROM_8197F)
+#define BIT_CLEAR_MCU_ROM_8197F(x) ((x) & (~BITS_MCU_ROM_8197F))
+#define BIT_GET_MCU_ROM_8197F(x) \
+ (((x) >> BIT_SHIFT_MCU_ROM_8197F) & BIT_MASK_MCU_ROM_8197F)
+#define BIT_SET_MCU_ROM_8197F(x, v) \
+ (BIT_CLEAR_MCU_ROM_8197F(x) | BIT_MCU_ROM_8197F(v))
+
+/* 2 REG_AFE_CTRL8_8197F */
+
+#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4_8197F 26
+#define BIT_MASK_BB_DBG_SEL_AFE_SDM_V4_8197F 0x7
+#define BIT_BB_DBG_SEL_AFE_SDM_V4_8197F(x) \
+ (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_V4_8197F) \
+ << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4_8197F)
+#define BITS_BB_DBG_SEL_AFE_SDM_V4_8197F \
+ (BIT_MASK_BB_DBG_SEL_AFE_SDM_V4_8197F \
+ << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4_8197F)
+#define BIT_CLEAR_BB_DBG_SEL_AFE_SDM_V4_8197F(x) \
+ ((x) & (~BITS_BB_DBG_SEL_AFE_SDM_V4_8197F))
+#define BIT_GET_BB_DBG_SEL_AFE_SDM_V4_8197F(x) \
+ (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_V4_8197F) & \
+ BIT_MASK_BB_DBG_SEL_AFE_SDM_V4_8197F)
+#define BIT_SET_BB_DBG_SEL_AFE_SDM_V4_8197F(x, v) \
+ (BIT_CLEAR_BB_DBG_SEL_AFE_SDM_V4_8197F(x) | \
+ BIT_BB_DBG_SEL_AFE_SDM_V4_8197F(v))
+
+#define BIT_SYN_AGPIO_8197F BIT(20)
+
+#define BIT_SHIFT_XTAL_SEL_TOK_V2_8197F 0
+#define BIT_MASK_XTAL_SEL_TOK_V2_8197F 0x7
+#define BIT_XTAL_SEL_TOK_V2_8197F(x) \
+ (((x) & BIT_MASK_XTAL_SEL_TOK_V2_8197F) \
+ << BIT_SHIFT_XTAL_SEL_TOK_V2_8197F)
+#define BITS_XTAL_SEL_TOK_V2_8197F \
+ (BIT_MASK_XTAL_SEL_TOK_V2_8197F << BIT_SHIFT_XTAL_SEL_TOK_V2_8197F)
+#define BIT_CLEAR_XTAL_SEL_TOK_V2_8197F(x) ((x) & (~BITS_XTAL_SEL_TOK_V2_8197F))
+#define BIT_GET_XTAL_SEL_TOK_V2_8197F(x) \
+ (((x) >> BIT_SHIFT_XTAL_SEL_TOK_V2_8197F) & \
+ BIT_MASK_XTAL_SEL_TOK_V2_8197F)
+#define BIT_SET_XTAL_SEL_TOK_V2_8197F(x, v) \
+ (BIT_CLEAR_XTAL_SEL_TOK_V2_8197F(x) | BIT_XTAL_SEL_TOK_V2_8197F(v))
+
+/* 2 REG_USB_SIE_INTF_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_PCIE_MIO_INTF_8197F */
+#define BIT_PCIE_MIO_BYIOREG_8197F BIT(13)
+#define BIT_PCIE_MIO_RE_8197F BIT(12)
+
+#define BIT_SHIFT_PCIE_MIO_WE_8197F 8
+#define BIT_MASK_PCIE_MIO_WE_8197F 0xf
+#define BIT_PCIE_MIO_WE_8197F(x) \
+ (((x) & BIT_MASK_PCIE_MIO_WE_8197F) << BIT_SHIFT_PCIE_MIO_WE_8197F)
+#define BITS_PCIE_MIO_WE_8197F \
+ (BIT_MASK_PCIE_MIO_WE_8197F << BIT_SHIFT_PCIE_MIO_WE_8197F)
+#define BIT_CLEAR_PCIE_MIO_WE_8197F(x) ((x) & (~BITS_PCIE_MIO_WE_8197F))
+#define BIT_GET_PCIE_MIO_WE_8197F(x) \
+ (((x) >> BIT_SHIFT_PCIE_MIO_WE_8197F) & BIT_MASK_PCIE_MIO_WE_8197F)
+#define BIT_SET_PCIE_MIO_WE_8197F(x, v) \
+ (BIT_CLEAR_PCIE_MIO_WE_8197F(x) | BIT_PCIE_MIO_WE_8197F(v))
+
+#define BIT_SHIFT_PCIE_MIO_ADDR_8197F 0
+#define BIT_MASK_PCIE_MIO_ADDR_8197F 0xff
+#define BIT_PCIE_MIO_ADDR_8197F(x) \
+ (((x) & BIT_MASK_PCIE_MIO_ADDR_8197F) << BIT_SHIFT_PCIE_MIO_ADDR_8197F)
+#define BITS_PCIE_MIO_ADDR_8197F \
+ (BIT_MASK_PCIE_MIO_ADDR_8197F << BIT_SHIFT_PCIE_MIO_ADDR_8197F)
+#define BIT_CLEAR_PCIE_MIO_ADDR_8197F(x) ((x) & (~BITS_PCIE_MIO_ADDR_8197F))
+#define BIT_GET_PCIE_MIO_ADDR_8197F(x) \
+ (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8197F) & BIT_MASK_PCIE_MIO_ADDR_8197F)
+#define BIT_SET_PCIE_MIO_ADDR_8197F(x, v) \
+ (BIT_CLEAR_PCIE_MIO_ADDR_8197F(x) | BIT_PCIE_MIO_ADDR_8197F(v))
+
+/* 2 REG_PCIE_MIO_INTD_8197F */
+
+#define BIT_SHIFT_PCIE_MIO_DATA_8197F 0
+#define BIT_MASK_PCIE_MIO_DATA_8197F 0xffffffffL
+#define BIT_PCIE_MIO_DATA_8197F(x) \
+ (((x) & BIT_MASK_PCIE_MIO_DATA_8197F) << BIT_SHIFT_PCIE_MIO_DATA_8197F)
+#define BITS_PCIE_MIO_DATA_8197F \
+ (BIT_MASK_PCIE_MIO_DATA_8197F << BIT_SHIFT_PCIE_MIO_DATA_8197F)
+#define BIT_CLEAR_PCIE_MIO_DATA_8197F(x) ((x) & (~BITS_PCIE_MIO_DATA_8197F))
+#define BIT_GET_PCIE_MIO_DATA_8197F(x) \
+ (((x) >> BIT_SHIFT_PCIE_MIO_DATA_8197F) & BIT_MASK_PCIE_MIO_DATA_8197F)
+#define BIT_SET_PCIE_MIO_DATA_8197F(x, v) \
+ (BIT_CLEAR_PCIE_MIO_DATA_8197F(x) | BIT_PCIE_MIO_DATA_8197F(v))
+
+/* 2 REG_WLRF1_8197F */
+
+/* 2 REG_SYS_CFG1_8197F */
+
+#define BIT_SHIFT_TRP_ICFG_8197F 28
+#define BIT_MASK_TRP_ICFG_8197F 0xf
+#define BIT_TRP_ICFG_8197F(x) \
+ (((x) & BIT_MASK_TRP_ICFG_8197F) << BIT_SHIFT_TRP_ICFG_8197F)
+#define BITS_TRP_ICFG_8197F \
+ (BIT_MASK_TRP_ICFG_8197F << BIT_SHIFT_TRP_ICFG_8197F)
+#define BIT_CLEAR_TRP_ICFG_8197F(x) ((x) & (~BITS_TRP_ICFG_8197F))
+#define BIT_GET_TRP_ICFG_8197F(x) \
+ (((x) >> BIT_SHIFT_TRP_ICFG_8197F) & BIT_MASK_TRP_ICFG_8197F)
+#define BIT_SET_TRP_ICFG_8197F(x, v) \
+ (BIT_CLEAR_TRP_ICFG_8197F(x) | BIT_TRP_ICFG_8197F(v))
+
+#define BIT_RF_TYPE_ID_8197F BIT(27)
+#define BIT_BD_HCI_SEL_8197F BIT(26)
+#define BIT_BD_PKG_SEL_8197F BIT(25)
+#define BIT_SPSLDO_SEL_8197F BIT(24)
+#define BIT_RTL_ID_8197F BIT(23)
+#define BIT_PAD_HWPD_IDN_8197F BIT(22)
+#define BIT_TESTMODE_8197F BIT(20)
+
+#define BIT_SHIFT_VENDOR_ID_8197F 16
+#define BIT_MASK_VENDOR_ID_8197F 0xf
+#define BIT_VENDOR_ID_8197F(x) \
+ (((x) & BIT_MASK_VENDOR_ID_8197F) << BIT_SHIFT_VENDOR_ID_8197F)
+#define BITS_VENDOR_ID_8197F \
+ (BIT_MASK_VENDOR_ID_8197F << BIT_SHIFT_VENDOR_ID_8197F)
+#define BIT_CLEAR_VENDOR_ID_8197F(x) ((x) & (~BITS_VENDOR_ID_8197F))
+#define BIT_GET_VENDOR_ID_8197F(x) \
+ (((x) >> BIT_SHIFT_VENDOR_ID_8197F) & BIT_MASK_VENDOR_ID_8197F)
+#define BIT_SET_VENDOR_ID_8197F(x, v) \
+ (BIT_CLEAR_VENDOR_ID_8197F(x) | BIT_VENDOR_ID_8197F(v))
+
+#define BIT_SHIFT_CHIP_VER_8197F 12
+#define BIT_MASK_CHIP_VER_8197F 0xf
+#define BIT_CHIP_VER_8197F(x) \
+ (((x) & BIT_MASK_CHIP_VER_8197F) << BIT_SHIFT_CHIP_VER_8197F)
+#define BITS_CHIP_VER_8197F \
+ (BIT_MASK_CHIP_VER_8197F << BIT_SHIFT_CHIP_VER_8197F)
+#define BIT_CLEAR_CHIP_VER_8197F(x) ((x) & (~BITS_CHIP_VER_8197F))
+#define BIT_GET_CHIP_VER_8197F(x) \
+ (((x) >> BIT_SHIFT_CHIP_VER_8197F) & BIT_MASK_CHIP_VER_8197F)
+#define BIT_SET_CHIP_VER_8197F(x, v) \
+ (BIT_CLEAR_CHIP_VER_8197F(x) | BIT_CHIP_VER_8197F(v))
+
+#define BIT_BD_MAC1_8197F BIT(10)
+#define BIT_BD_MAC2_8197F BIT(9)
+#define BIT_SIC_IDLE_8197F BIT(8)
+#define BIT_SW_OFFLOAD_EN_8197F BIT(7)
+#define BIT_OCP_SHUTDN_8197F BIT(6)
+#define BIT_V15_VLD_8197F BIT(5)
+#define BIT_PCIRSTB_8197F BIT(4)
+#define BIT_PCLK_VLD_8197F BIT(3)
+#define BIT_UCLK_VLD_8197F BIT(2)
+#define BIT_ACLK_VLD_8197F BIT(1)
+#define BIT_XCLK_VLD_8197F BIT(0)
+
+/* 2 REG_SYS_STATUS1_8197F */
+
+#define BIT_SHIFT_RF_RL_ID_8197F 28
+#define BIT_MASK_RF_RL_ID_8197F 0xf
+#define BIT_RF_RL_ID_8197F(x) \
+ (((x) & BIT_MASK_RF_RL_ID_8197F) << BIT_SHIFT_RF_RL_ID_8197F)
+#define BITS_RF_RL_ID_8197F \
+ (BIT_MASK_RF_RL_ID_8197F << BIT_SHIFT_RF_RL_ID_8197F)
+#define BIT_CLEAR_RF_RL_ID_8197F(x) ((x) & (~BITS_RF_RL_ID_8197F))
+#define BIT_GET_RF_RL_ID_8197F(x) \
+ (((x) >> BIT_SHIFT_RF_RL_ID_8197F) & BIT_MASK_RF_RL_ID_8197F)
+#define BIT_SET_RF_RL_ID_8197F(x, v) \
+ (BIT_CLEAR_RF_RL_ID_8197F(x) | BIT_RF_RL_ID_8197F(v))
+
+#define BIT_HPHY_ICFG_8197F BIT(19)
+
+#define BIT_SHIFT_SEL_0XC0_8197F 16
+#define BIT_MASK_SEL_0XC0_8197F 0x3
+#define BIT_SEL_0XC0_8197F(x) \
+ (((x) & BIT_MASK_SEL_0XC0_8197F) << BIT_SHIFT_SEL_0XC0_8197F)
+#define BITS_SEL_0XC0_8197F \
+ (BIT_MASK_SEL_0XC0_8197F << BIT_SHIFT_SEL_0XC0_8197F)
+#define BIT_CLEAR_SEL_0XC0_8197F(x) ((x) & (~BITS_SEL_0XC0_8197F))
+#define BIT_GET_SEL_0XC0_8197F(x) \
+ (((x) >> BIT_SHIFT_SEL_0XC0_8197F) & BIT_MASK_SEL_0XC0_8197F)
+#define BIT_SET_SEL_0XC0_8197F(x, v) \
+ (BIT_CLEAR_SEL_0XC0_8197F(x) | BIT_SEL_0XC0_8197F(v))
+
+#define BIT_USB_OPERATION_MODE_8197F BIT(10)
+#define BIT_BT_PDN_8197F BIT(9)
+#define BIT_AUTO_WLPON_8197F BIT(8)
+#define BIT_WL_MODE_8197F BIT(7)
+#define BIT_PKG_SEL_HCI_8197F BIT(6)
+
+#define BIT_SHIFT_HCI_SEL_8197F 4
+#define BIT_MASK_HCI_SEL_8197F 0x3
+#define BIT_HCI_SEL_8197F(x) \
+ (((x) & BIT_MASK_HCI_SEL_8197F) << BIT_SHIFT_HCI_SEL_8197F)
+#define BITS_HCI_SEL_8197F (BIT_MASK_HCI_SEL_8197F << BIT_SHIFT_HCI_SEL_8197F)
+#define BIT_CLEAR_HCI_SEL_8197F(x) ((x) & (~BITS_HCI_SEL_8197F))
+#define BIT_GET_HCI_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_HCI_SEL_8197F) & BIT_MASK_HCI_SEL_8197F)
+#define BIT_SET_HCI_SEL_8197F(x, v) \
+ (BIT_CLEAR_HCI_SEL_8197F(x) | BIT_HCI_SEL_8197F(v))
+
+#define BIT_SHIFT_PAD_HCI_SEL_8197F 2
+#define BIT_MASK_PAD_HCI_SEL_8197F 0x3
+#define BIT_PAD_HCI_SEL_8197F(x) \
+ (((x) & BIT_MASK_PAD_HCI_SEL_8197F) << BIT_SHIFT_PAD_HCI_SEL_8197F)
+#define BITS_PAD_HCI_SEL_8197F \
+ (BIT_MASK_PAD_HCI_SEL_8197F << BIT_SHIFT_PAD_HCI_SEL_8197F)
+#define BIT_CLEAR_PAD_HCI_SEL_8197F(x) ((x) & (~BITS_PAD_HCI_SEL_8197F))
+#define BIT_GET_PAD_HCI_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_PAD_HCI_SEL_8197F) & BIT_MASK_PAD_HCI_SEL_8197F)
+#define BIT_SET_PAD_HCI_SEL_8197F(x, v) \
+ (BIT_CLEAR_PAD_HCI_SEL_8197F(x) | BIT_PAD_HCI_SEL_8197F(v))
+
+#define BIT_SHIFT_EFS_HCI_SEL_8197F 0
+#define BIT_MASK_EFS_HCI_SEL_8197F 0x3
+#define BIT_EFS_HCI_SEL_8197F(x) \
+ (((x) & BIT_MASK_EFS_HCI_SEL_8197F) << BIT_SHIFT_EFS_HCI_SEL_8197F)
+#define BITS_EFS_HCI_SEL_8197F \
+ (BIT_MASK_EFS_HCI_SEL_8197F << BIT_SHIFT_EFS_HCI_SEL_8197F)
+#define BIT_CLEAR_EFS_HCI_SEL_8197F(x) ((x) & (~BITS_EFS_HCI_SEL_8197F))
+#define BIT_GET_EFS_HCI_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_EFS_HCI_SEL_8197F) & BIT_MASK_EFS_HCI_SEL_8197F)
+#define BIT_SET_EFS_HCI_SEL_8197F(x, v) \
+ (BIT_CLEAR_EFS_HCI_SEL_8197F(x) | BIT_EFS_HCI_SEL_8197F(v))
+
+/* 2 REG_SYS_STATUS2_8197F */
+#define BIT_SIO_ALDN_8197F BIT(19)
+#define BIT_USB_ALDN_8197F BIT(18)
+#define BIT_PCI_ALDN_8197F BIT(17)
+#define BIT_SYS_ALDN_8197F BIT(16)
+
+#define BIT_SHIFT_EPVID1_8197F 8
+#define BIT_MASK_EPVID1_8197F 0xff
+#define BIT_EPVID1_8197F(x) \
+ (((x) & BIT_MASK_EPVID1_8197F) << BIT_SHIFT_EPVID1_8197F)
+#define BITS_EPVID1_8197F (BIT_MASK_EPVID1_8197F << BIT_SHIFT_EPVID1_8197F)
+#define BIT_CLEAR_EPVID1_8197F(x) ((x) & (~BITS_EPVID1_8197F))
+#define BIT_GET_EPVID1_8197F(x) \
+ (((x) >> BIT_SHIFT_EPVID1_8197F) & BIT_MASK_EPVID1_8197F)
+#define BIT_SET_EPVID1_8197F(x, v) \
+ (BIT_CLEAR_EPVID1_8197F(x) | BIT_EPVID1_8197F(v))
+
+#define BIT_SHIFT_EPVID0_8197F 0
+#define BIT_MASK_EPVID0_8197F 0xff
+#define BIT_EPVID0_8197F(x) \
+ (((x) & BIT_MASK_EPVID0_8197F) << BIT_SHIFT_EPVID0_8197F)
+#define BITS_EPVID0_8197F (BIT_MASK_EPVID0_8197F << BIT_SHIFT_EPVID0_8197F)
+#define BIT_CLEAR_EPVID0_8197F(x) ((x) & (~BITS_EPVID0_8197F))
+#define BIT_GET_EPVID0_8197F(x) \
+ (((x) >> BIT_SHIFT_EPVID0_8197F) & BIT_MASK_EPVID0_8197F)
+#define BIT_SET_EPVID0_8197F(x, v) \
+ (BIT_CLEAR_EPVID0_8197F(x) | BIT_EPVID0_8197F(v))
+
+/* 2 REG_SYS_CFG2_8197F */
+
+#define BIT_SHIFT_HW_ID_8197F 0
+#define BIT_MASK_HW_ID_8197F 0xff
+#define BIT_HW_ID_8197F(x) \
+ (((x) & BIT_MASK_HW_ID_8197F) << BIT_SHIFT_HW_ID_8197F)
+#define BITS_HW_ID_8197F (BIT_MASK_HW_ID_8197F << BIT_SHIFT_HW_ID_8197F)
+#define BIT_CLEAR_HW_ID_8197F(x) ((x) & (~BITS_HW_ID_8197F))
+#define BIT_GET_HW_ID_8197F(x) \
+ (((x) >> BIT_SHIFT_HW_ID_8197F) & BIT_MASK_HW_ID_8197F)
+#define BIT_SET_HW_ID_8197F(x, v) \
+ (BIT_CLEAR_HW_ID_8197F(x) | BIT_HW_ID_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_SYS_CFG3_8197F */
+
+/* 2 REG_SYS_CFG4_8197F */
+
+/* 2 REG_CPU_DMEM_CON_8197F */
+#define BIT_ANA_PORT_IDLE_8197F BIT(18)
+#define BIT_MAC_PORT_IDLE_8197F BIT(17)
+#define BIT_WL_PLATFORM_RST_8197F BIT(16)
+#define BIT_WL_SECURITY_CLK_8197F BIT(15)
+
+#define BIT_SHIFT_CPU_DMEM_CON_8197F 0
+#define BIT_MASK_CPU_DMEM_CON_8197F 0xff
+#define BIT_CPU_DMEM_CON_8197F(x) \
+ (((x) & BIT_MASK_CPU_DMEM_CON_8197F) << BIT_SHIFT_CPU_DMEM_CON_8197F)
+#define BITS_CPU_DMEM_CON_8197F \
+ (BIT_MASK_CPU_DMEM_CON_8197F << BIT_SHIFT_CPU_DMEM_CON_8197F)
+#define BIT_CLEAR_CPU_DMEM_CON_8197F(x) ((x) & (~BITS_CPU_DMEM_CON_8197F))
+#define BIT_GET_CPU_DMEM_CON_8197F(x) \
+ (((x) >> BIT_SHIFT_CPU_DMEM_CON_8197F) & BIT_MASK_CPU_DMEM_CON_8197F)
+#define BIT_SET_CPU_DMEM_CON_8197F(x, v) \
+ (BIT_CLEAR_CPU_DMEM_CON_8197F(x) | BIT_CPU_DMEM_CON_8197F(v))
+
+/* 2 REG_HIMR2_8197F */
+#define BIT_BCNDMAINT_P4_MSK_8197F BIT(31)
+#define BIT_BCNDMAINT_P3_MSK_8197F BIT(30)
+#define BIT_BCNDMAINT_P2_MSK_8197F BIT(29)
+#define BIT_BCNDMAINT_P1_MSK_8197F BIT(28)
+#define BIT_ATIMEND7_MSK_8197F BIT(22)
+#define BIT_ATIMEND6_MSK_8197F BIT(21)
+#define BIT_ATIMEND5_MSK_8197F BIT(20)
+#define BIT_ATIMEND4_MSK_8197F BIT(19)
+#define BIT_ATIMEND3_MSK_8197F BIT(18)
+#define BIT_ATIMEND2_MSK_8197F BIT(17)
+#define BIT_ATIMEND1_MSK_8197F BIT(16)
+#define BIT_TXBCN7OK_MSK_8197F BIT(14)
+#define BIT_TXBCN6OK_MSK_8197F BIT(13)
+#define BIT_TXBCN5OK_MSK_8197F BIT(12)
+#define BIT_TXBCN4OK_MSK_8197F BIT(11)
+#define BIT_TXBCN3OK_MSK_8197F BIT(10)
+#define BIT_TXBCN2OK_MSK_8197F BIT(9)
+#define BIT_TXBCN1OK_MSK_V1_8197F BIT(8)
+#define BIT_TXBCN7ERR_MSK_8197F BIT(6)
+#define BIT_TXBCN6ERR_MSK_8197F BIT(5)
+#define BIT_TXBCN5ERR_MSK_8197F BIT(4)
+#define BIT_TXBCN4ERR_MSK_8197F BIT(3)
+#define BIT_TXBCN3ERR_MSK_8197F BIT(2)
+#define BIT_TXBCN2ERR_MSK_8197F BIT(1)
+#define BIT_TXBCN1ERR_MSK_V1_8197F BIT(0)
+
+/* 2 REG_HISR2_8197F */
+#define BIT_BCNDMAINT_P4_8197F BIT(31)
+#define BIT_BCNDMAINT_P3_8197F BIT(30)
+#define BIT_BCNDMAINT_P2_8197F BIT(29)
+#define BIT_BCNDMAINT_P1_8197F BIT(28)
+#define BIT_ATIMEND7_8197F BIT(22)
+#define BIT_ATIMEND6_8197F BIT(21)
+#define BIT_ATIMEND5_8197F BIT(20)
+#define BIT_ATIMEND4_8197F BIT(19)
+#define BIT_ATIMEND3_8197F BIT(18)
+#define BIT_ATIMEND2_8197F BIT(17)
+#define BIT_ATIMEND1_8197F BIT(16)
+#define BIT_TXBCN7OK_8197F BIT(14)
+#define BIT_TXBCN6OK_8197F BIT(13)
+#define BIT_TXBCN5OK_8197F BIT(12)
+#define BIT_TXBCN4OK_8197F BIT(11)
+#define BIT_TXBCN3OK_8197F BIT(10)
+#define BIT_TXBCN2OK_8197F BIT(9)
+#define BIT_TXBCN1OK_8197F BIT(8)
+#define BIT_TXBCN7ERR_8197F BIT(6)
+#define BIT_TXBCN6ERR_8197F BIT(5)
+#define BIT_TXBCN5ERR_8197F BIT(4)
+#define BIT_TXBCN4ERR_8197F BIT(3)
+#define BIT_TXBCN3ERR_8197F BIT(2)
+#define BIT_TXBCN2ERR_8197F BIT(1)
+#define BIT_TXBCN1ERR_8197F BIT(0)
+
+/* 2 REG_HIMR3_8197F */
+#define BIT_SETH2CDOK_MASK_8197F BIT(16)
+#define BIT_H2C_CMD_FULL_MASK_8197F BIT(15)
+#define BIT_PWR_INT_127_MASK_8197F BIT(14)
+#define BIT_TXSHORTCUT_TXDESUPDATEOK_MASK_8197F BIT(13)
+#define BIT_TXSHORTCUT_BKUPDATEOK_MASK_8197F BIT(12)
+#define BIT_TXSHORTCUT_BEUPDATEOK_MASK_8197F BIT(11)
+#define BIT_TXSHORTCUT_VIUPDATEOK_MAS_8197F BIT(10)
+#define BIT_TXSHORTCUT_VOUPDATEOK_MASK_8197F BIT(9)
+#define BIT_PWR_INT_127_MASK_V1_8197F BIT(8)
+#define BIT_PWR_INT_126TO96_MASK_8197F BIT(7)
+#define BIT_PWR_INT_95TO64_MASK_8197F BIT(6)
+#define BIT_PWR_INT_63TO32_MASK_8197F BIT(5)
+#define BIT_PWR_INT_31TO0_MASK_8197F BIT(4)
+#define BIT_DDMA0_LP_INT_MSK_8197F BIT(1)
+#define BIT_DDMA0_HP_INT_MSK_8197F BIT(0)
+
+/* 2 REG_HISR3_8197F */
+#define BIT_SETH2CDOK_8197F BIT(16)
+#define BIT_H2C_CMD_FULL_8197F BIT(15)
+#define BIT_PWR_INT_127_8197F BIT(14)
+#define BIT_TXSHORTCUT_TXDESUPDATEOK_8197F BIT(13)
+#define BIT_TXSHORTCUT_BKUPDATEOK_8197F BIT(12)
+#define BIT_TXSHORTCUT_BEUPDATEOK_8197F BIT(11)
+#define BIT_TXSHORTCUT_VIUPDATEOK_8197F BIT(10)
+#define BIT_TXSHORTCUT_VOUPDATEOK_8197F BIT(9)
+#define BIT_PWR_INT_127_V1_8197F BIT(8)
+#define BIT_PWR_INT_126TO96_8197F BIT(7)
+#define BIT_PWR_INT_95TO64_8197F BIT(6)
+#define BIT_PWR_INT_63TO32_8197F BIT(5)
+#define BIT_PWR_INT_31TO0_8197F BIT(4)
+#define BIT_DDMA0_LP_INT_8197F BIT(1)
+#define BIT_DDMA0_HP_INT_8197F BIT(0)
+
+/* 2 REG_SW_MDIO_8197F */
+
+/* 2 REG_SW_FLUSH_8197F */
+#define BIT_FLUSH_HOLDN_EN_8197F BIT(25)
+#define BIT_FLUSH_WR_EN_8197F BIT(24)
+#define BIT_SW_FLASH_CONTROL_8197F BIT(23)
+#define BIT_SW_FLASH_WEN_E_8197F BIT(19)
+#define BIT_SW_FLASH_HOLDN_E_8197F BIT(18)
+#define BIT_SW_FLASH_SO_E_8197F BIT(17)
+#define BIT_SW_FLASH_SI_E_8197F BIT(16)
+#define BIT_SW_FLASH_SK_O_8197F BIT(13)
+#define BIT_SW_FLASH_CEN_O_8197F BIT(12)
+#define BIT_SW_FLASH_WEN_O_8197F BIT(11)
+#define BIT_SW_FLASH_HOLDN_O_8197F BIT(10)
+#define BIT_SW_FLASH_SO_O_8197F BIT(9)
+#define BIT_SW_FLASH_SI_O_8197F BIT(8)
+#define BIT_SW_FLASH_WEN_I_8197F BIT(3)
+#define BIT_SW_FLASH_HOLDN_I_8197F BIT(2)
+#define BIT_SW_FLASH_SO_I_8197F BIT(1)
+#define BIT_SW_FLASH_SI_I_8197F BIT(0)
+
+/* 2 REG_DBG_GPIO_BMUX_8197F */
+
+#define BIT_SHIFT_DBG_GPIO_BMUX_7_8197F 21
+#define BIT_MASK_DBG_GPIO_BMUX_7_8197F 0x7
+#define BIT_DBG_GPIO_BMUX_7_8197F(x) \
+ (((x) & BIT_MASK_DBG_GPIO_BMUX_7_8197F) \
+ << BIT_SHIFT_DBG_GPIO_BMUX_7_8197F)
+#define BITS_DBG_GPIO_BMUX_7_8197F \
+ (BIT_MASK_DBG_GPIO_BMUX_7_8197F << BIT_SHIFT_DBG_GPIO_BMUX_7_8197F)
+#define BIT_CLEAR_DBG_GPIO_BMUX_7_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_7_8197F))
+#define BIT_GET_DBG_GPIO_BMUX_7_8197F(x) \
+ (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_7_8197F) & \
+ BIT_MASK_DBG_GPIO_BMUX_7_8197F)
+#define BIT_SET_DBG_GPIO_BMUX_7_8197F(x, v) \
+ (BIT_CLEAR_DBG_GPIO_BMUX_7_8197F(x) | BIT_DBG_GPIO_BMUX_7_8197F(v))
+
+#define BIT_SHIFT_DBG_GPIO_BMUX_6_8197F 18
+#define BIT_MASK_DBG_GPIO_BMUX_6_8197F 0x7
+#define BIT_DBG_GPIO_BMUX_6_8197F(x) \
+ (((x) & BIT_MASK_DBG_GPIO_BMUX_6_8197F) \
+ << BIT_SHIFT_DBG_GPIO_BMUX_6_8197F)
+#define BITS_DBG_GPIO_BMUX_6_8197F \
+ (BIT_MASK_DBG_GPIO_BMUX_6_8197F << BIT_SHIFT_DBG_GPIO_BMUX_6_8197F)
+#define BIT_CLEAR_DBG_GPIO_BMUX_6_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_6_8197F))
+#define BIT_GET_DBG_GPIO_BMUX_6_8197F(x) \
+ (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_6_8197F) & \
+ BIT_MASK_DBG_GPIO_BMUX_6_8197F)
+#define BIT_SET_DBG_GPIO_BMUX_6_8197F(x, v) \
+ (BIT_CLEAR_DBG_GPIO_BMUX_6_8197F(x) | BIT_DBG_GPIO_BMUX_6_8197F(v))
+
+#define BIT_SHIFT_DBG_GPIO_BMUX_5_8197F 15
+#define BIT_MASK_DBG_GPIO_BMUX_5_8197F 0x7
+#define BIT_DBG_GPIO_BMUX_5_8197F(x) \
+ (((x) & BIT_MASK_DBG_GPIO_BMUX_5_8197F) \
+ << BIT_SHIFT_DBG_GPIO_BMUX_5_8197F)
+#define BITS_DBG_GPIO_BMUX_5_8197F \
+ (BIT_MASK_DBG_GPIO_BMUX_5_8197F << BIT_SHIFT_DBG_GPIO_BMUX_5_8197F)
+#define BIT_CLEAR_DBG_GPIO_BMUX_5_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_5_8197F))
+#define BIT_GET_DBG_GPIO_BMUX_5_8197F(x) \
+ (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_5_8197F) & \
+ BIT_MASK_DBG_GPIO_BMUX_5_8197F)
+#define BIT_SET_DBG_GPIO_BMUX_5_8197F(x, v) \
+ (BIT_CLEAR_DBG_GPIO_BMUX_5_8197F(x) | BIT_DBG_GPIO_BMUX_5_8197F(v))
+
+#define BIT_SHIFT_DBG_GPIO_BMUX_4_8197F 12
+#define BIT_MASK_DBG_GPIO_BMUX_4_8197F 0x7
+#define BIT_DBG_GPIO_BMUX_4_8197F(x) \
+ (((x) & BIT_MASK_DBG_GPIO_BMUX_4_8197F) \
+ << BIT_SHIFT_DBG_GPIO_BMUX_4_8197F)
+#define BITS_DBG_GPIO_BMUX_4_8197F \
+ (BIT_MASK_DBG_GPIO_BMUX_4_8197F << BIT_SHIFT_DBG_GPIO_BMUX_4_8197F)
+#define BIT_CLEAR_DBG_GPIO_BMUX_4_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_4_8197F))
+#define BIT_GET_DBG_GPIO_BMUX_4_8197F(x) \
+ (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_4_8197F) & \
+ BIT_MASK_DBG_GPIO_BMUX_4_8197F)
+#define BIT_SET_DBG_GPIO_BMUX_4_8197F(x, v) \
+ (BIT_CLEAR_DBG_GPIO_BMUX_4_8197F(x) | BIT_DBG_GPIO_BMUX_4_8197F(v))
+
+#define BIT_SHIFT_DBG_GPIO_BMUX_3_8197F 9
+#define BIT_MASK_DBG_GPIO_BMUX_3_8197F 0x7
+#define BIT_DBG_GPIO_BMUX_3_8197F(x) \
+ (((x) & BIT_MASK_DBG_GPIO_BMUX_3_8197F) \
+ << BIT_SHIFT_DBG_GPIO_BMUX_3_8197F)
+#define BITS_DBG_GPIO_BMUX_3_8197F \
+ (BIT_MASK_DBG_GPIO_BMUX_3_8197F << BIT_SHIFT_DBG_GPIO_BMUX_3_8197F)
+#define BIT_CLEAR_DBG_GPIO_BMUX_3_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_3_8197F))
+#define BIT_GET_DBG_GPIO_BMUX_3_8197F(x) \
+ (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_3_8197F) & \
+ BIT_MASK_DBG_GPIO_BMUX_3_8197F)
+#define BIT_SET_DBG_GPIO_BMUX_3_8197F(x, v) \
+ (BIT_CLEAR_DBG_GPIO_BMUX_3_8197F(x) | BIT_DBG_GPIO_BMUX_3_8197F(v))
+
+#define BIT_SHIFT_DBG_GPIO_BMUX_2_8197F 6
+#define BIT_MASK_DBG_GPIO_BMUX_2_8197F 0x7
+#define BIT_DBG_GPIO_BMUX_2_8197F(x) \
+ (((x) & BIT_MASK_DBG_GPIO_BMUX_2_8197F) \
+ << BIT_SHIFT_DBG_GPIO_BMUX_2_8197F)
+#define BITS_DBG_GPIO_BMUX_2_8197F \
+ (BIT_MASK_DBG_GPIO_BMUX_2_8197F << BIT_SHIFT_DBG_GPIO_BMUX_2_8197F)
+#define BIT_CLEAR_DBG_GPIO_BMUX_2_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_2_8197F))
+#define BIT_GET_DBG_GPIO_BMUX_2_8197F(x) \
+ (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_2_8197F) & \
+ BIT_MASK_DBG_GPIO_BMUX_2_8197F)
+#define BIT_SET_DBG_GPIO_BMUX_2_8197F(x, v) \
+ (BIT_CLEAR_DBG_GPIO_BMUX_2_8197F(x) | BIT_DBG_GPIO_BMUX_2_8197F(v))
+
+#define BIT_SHIFT_DBG_GPIO_BMUX_1_8197F 3
+#define BIT_MASK_DBG_GPIO_BMUX_1_8197F 0x7
+#define BIT_DBG_GPIO_BMUX_1_8197F(x) \
+ (((x) & BIT_MASK_DBG_GPIO_BMUX_1_8197F) \
+ << BIT_SHIFT_DBG_GPIO_BMUX_1_8197F)
+#define BITS_DBG_GPIO_BMUX_1_8197F \
+ (BIT_MASK_DBG_GPIO_BMUX_1_8197F << BIT_SHIFT_DBG_GPIO_BMUX_1_8197F)
+#define BIT_CLEAR_DBG_GPIO_BMUX_1_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_1_8197F))
+#define BIT_GET_DBG_GPIO_BMUX_1_8197F(x) \
+ (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_1_8197F) & \
+ BIT_MASK_DBG_GPIO_BMUX_1_8197F)
+#define BIT_SET_DBG_GPIO_BMUX_1_8197F(x, v) \
+ (BIT_CLEAR_DBG_GPIO_BMUX_1_8197F(x) | BIT_DBG_GPIO_BMUX_1_8197F(v))
+
+#define BIT_SHIFT_DBG_GPIO_BMUX_0_8197F 0
+#define BIT_MASK_DBG_GPIO_BMUX_0_8197F 0x7
+#define BIT_DBG_GPIO_BMUX_0_8197F(x) \
+ (((x) & BIT_MASK_DBG_GPIO_BMUX_0_8197F) \
+ << BIT_SHIFT_DBG_GPIO_BMUX_0_8197F)
+#define BITS_DBG_GPIO_BMUX_0_8197F \
+ (BIT_MASK_DBG_GPIO_BMUX_0_8197F << BIT_SHIFT_DBG_GPIO_BMUX_0_8197F)
+#define BIT_CLEAR_DBG_GPIO_BMUX_0_8197F(x) ((x) & (~BITS_DBG_GPIO_BMUX_0_8197F))
+#define BIT_GET_DBG_GPIO_BMUX_0_8197F(x) \
+ (((x) >> BIT_SHIFT_DBG_GPIO_BMUX_0_8197F) & \
+ BIT_MASK_DBG_GPIO_BMUX_0_8197F)
+#define BIT_SET_DBG_GPIO_BMUX_0_8197F(x, v) \
+ (BIT_CLEAR_DBG_GPIO_BMUX_0_8197F(x) | BIT_DBG_GPIO_BMUX_0_8197F(v))
+
+/* 2 REG_FPGA_TAG_8197F (NO USE IN ASIC) */
+
+#define BIT_SHIFT_FPGA_TAG_8197F 0
+#define BIT_MASK_FPGA_TAG_8197F 0xffffffffL
+#define BIT_FPGA_TAG_8197F(x) \
+ (((x) & BIT_MASK_FPGA_TAG_8197F) << BIT_SHIFT_FPGA_TAG_8197F)
+#define BITS_FPGA_TAG_8197F \
+ (BIT_MASK_FPGA_TAG_8197F << BIT_SHIFT_FPGA_TAG_8197F)
+#define BIT_CLEAR_FPGA_TAG_8197F(x) ((x) & (~BITS_FPGA_TAG_8197F))
+#define BIT_GET_FPGA_TAG_8197F(x) \
+ (((x) >> BIT_SHIFT_FPGA_TAG_8197F) & BIT_MASK_FPGA_TAG_8197F)
+#define BIT_SET_FPGA_TAG_8197F(x, v) \
+ (BIT_CLEAR_FPGA_TAG_8197F(x) | BIT_FPGA_TAG_8197F(v))
+
+/* 2 REG_WL_DSS_CTRL0_8197F */
+#define BIT_WL_DSS_RSTN_8197F BIT(27)
+#define BIT_WL_DSS_EN_CLK_8197F BIT(26)
+#define BIT_WL_DSS_SPEED_EN_8197F BIT(25)
+
+#define BIT_SHIFT_WL_DSS_COUNT_OUT_8197F 0
+#define BIT_MASK_WL_DSS_COUNT_OUT_8197F 0xfffff
+#define BIT_WL_DSS_COUNT_OUT_8197F(x) \
+ (((x) & BIT_MASK_WL_DSS_COUNT_OUT_8197F) \
+ << BIT_SHIFT_WL_DSS_COUNT_OUT_8197F)
+#define BITS_WL_DSS_COUNT_OUT_8197F \
+ (BIT_MASK_WL_DSS_COUNT_OUT_8197F << BIT_SHIFT_WL_DSS_COUNT_OUT_8197F)
+#define BIT_CLEAR_WL_DSS_COUNT_OUT_8197F(x) \
+ ((x) & (~BITS_WL_DSS_COUNT_OUT_8197F))
+#define BIT_GET_WL_DSS_COUNT_OUT_8197F(x) \
+ (((x) >> BIT_SHIFT_WL_DSS_COUNT_OUT_8197F) & \
+ BIT_MASK_WL_DSS_COUNT_OUT_8197F)
+#define BIT_SET_WL_DSS_COUNT_OUT_8197F(x, v) \
+ (BIT_CLEAR_WL_DSS_COUNT_OUT_8197F(x) | BIT_WL_DSS_COUNT_OUT_8197F(v))
+
+/* 2 REG_WL_DSS_CTRL1_8197F */
+#define BIT_WL_DSS_RSTN_8197F BIT(27)
+#define BIT_WL_DSS_EN_CLK_8197F BIT(26)
+#define BIT_WL_DSS_SPEED_EN_8197F BIT(25)
+#define BIT_WL_DSS_WIRE_SEL_8197F BIT(24)
+
+#define BIT_SHIFT_WL_DSS_RO_SEL_8197F 20
+#define BIT_MASK_WL_DSS_RO_SEL_8197F 0x7
+#define BIT_WL_DSS_RO_SEL_8197F(x) \
+ (((x) & BIT_MASK_WL_DSS_RO_SEL_8197F) << BIT_SHIFT_WL_DSS_RO_SEL_8197F)
+#define BITS_WL_DSS_RO_SEL_8197F \
+ (BIT_MASK_WL_DSS_RO_SEL_8197F << BIT_SHIFT_WL_DSS_RO_SEL_8197F)
+#define BIT_CLEAR_WL_DSS_RO_SEL_8197F(x) ((x) & (~BITS_WL_DSS_RO_SEL_8197F))
+#define BIT_GET_WL_DSS_RO_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_WL_DSS_RO_SEL_8197F) & BIT_MASK_WL_DSS_RO_SEL_8197F)
+#define BIT_SET_WL_DSS_RO_SEL_8197F(x, v) \
+ (BIT_CLEAR_WL_DSS_RO_SEL_8197F(x) | BIT_WL_DSS_RO_SEL_8197F(v))
+
+#define BIT_SHIFT_WL_DSS_DATA_IN_8197F 0
+#define BIT_MASK_WL_DSS_DATA_IN_8197F 0xfffff
+#define BIT_WL_DSS_DATA_IN_8197F(x) \
+ (((x) & BIT_MASK_WL_DSS_DATA_IN_8197F) \
+ << BIT_SHIFT_WL_DSS_DATA_IN_8197F)
+#define BITS_WL_DSS_DATA_IN_8197F \
+ (BIT_MASK_WL_DSS_DATA_IN_8197F << BIT_SHIFT_WL_DSS_DATA_IN_8197F)
+#define BIT_CLEAR_WL_DSS_DATA_IN_8197F(x) ((x) & (~BITS_WL_DSS_DATA_IN_8197F))
+#define BIT_GET_WL_DSS_DATA_IN_8197F(x) \
+ (((x) >> BIT_SHIFT_WL_DSS_DATA_IN_8197F) & \
+ BIT_MASK_WL_DSS_DATA_IN_8197F)
+#define BIT_SET_WL_DSS_DATA_IN_8197F(x, v) \
+ (BIT_CLEAR_WL_DSS_DATA_IN_8197F(x) | BIT_WL_DSS_DATA_IN_8197F(v))
+
+/* 2 REG_WL_DSS_STATUS1_8197F */
+#define BIT_WL_DSS_READY_8197F BIT(21)
+#define BIT_WL_DSS_WSORT_GO_8197F BIT(20)
+
+#define BIT_SHIFT_WL_DSS_COUNT_OUT_8197F 0
+#define BIT_MASK_WL_DSS_COUNT_OUT_8197F 0xfffff
+#define BIT_WL_DSS_COUNT_OUT_8197F(x) \
+ (((x) & BIT_MASK_WL_DSS_COUNT_OUT_8197F) \
+ << BIT_SHIFT_WL_DSS_COUNT_OUT_8197F)
+#define BITS_WL_DSS_COUNT_OUT_8197F \
+ (BIT_MASK_WL_DSS_COUNT_OUT_8197F << BIT_SHIFT_WL_DSS_COUNT_OUT_8197F)
+#define BIT_CLEAR_WL_DSS_COUNT_OUT_8197F(x) \
+ ((x) & (~BITS_WL_DSS_COUNT_OUT_8197F))
+#define BIT_GET_WL_DSS_COUNT_OUT_8197F(x) \
+ (((x) >> BIT_SHIFT_WL_DSS_COUNT_OUT_8197F) & \
+ BIT_MASK_WL_DSS_COUNT_OUT_8197F)
+#define BIT_SET_WL_DSS_COUNT_OUT_8197F(x, v) \
+ (BIT_CLEAR_WL_DSS_COUNT_OUT_8197F(x) | BIT_WL_DSS_COUNT_OUT_8197F(v))
+
+/* 2 REG_FW_DBG0_8197F */
+
+#define BIT_SHIFT_FW_DBG0_8197F 0
+#define BIT_MASK_FW_DBG0_8197F 0xffffffffL
+#define BIT_FW_DBG0_8197F(x) \
+ (((x) & BIT_MASK_FW_DBG0_8197F) << BIT_SHIFT_FW_DBG0_8197F)
+#define BITS_FW_DBG0_8197F (BIT_MASK_FW_DBG0_8197F << BIT_SHIFT_FW_DBG0_8197F)
+#define BIT_CLEAR_FW_DBG0_8197F(x) ((x) & (~BITS_FW_DBG0_8197F))
+#define BIT_GET_FW_DBG0_8197F(x) \
+ (((x) >> BIT_SHIFT_FW_DBG0_8197F) & BIT_MASK_FW_DBG0_8197F)
+#define BIT_SET_FW_DBG0_8197F(x, v) \
+ (BIT_CLEAR_FW_DBG0_8197F(x) | BIT_FW_DBG0_8197F(v))
+
+/* 2 REG_FW_DBG1_8197F */
+
+#define BIT_SHIFT_FW_DBG1_8197F 0
+#define BIT_MASK_FW_DBG1_8197F 0xffffffffL
+#define BIT_FW_DBG1_8197F(x) \
+ (((x) & BIT_MASK_FW_DBG1_8197F) << BIT_SHIFT_FW_DBG1_8197F)
+#define BITS_FW_DBG1_8197F (BIT_MASK_FW_DBG1_8197F << BIT_SHIFT_FW_DBG1_8197F)
+#define BIT_CLEAR_FW_DBG1_8197F(x) ((x) & (~BITS_FW_DBG1_8197F))
+#define BIT_GET_FW_DBG1_8197F(x) \
+ (((x) >> BIT_SHIFT_FW_DBG1_8197F) & BIT_MASK_FW_DBG1_8197F)
+#define BIT_SET_FW_DBG1_8197F(x, v) \
+ (BIT_CLEAR_FW_DBG1_8197F(x) | BIT_FW_DBG1_8197F(v))
+
+/* 2 REG_FW_DBG2_8197F */
+
+#define BIT_SHIFT_FW_DBG2_8197F 0
+#define BIT_MASK_FW_DBG2_8197F 0xffffffffL
+#define BIT_FW_DBG2_8197F(x) \
+ (((x) & BIT_MASK_FW_DBG2_8197F) << BIT_SHIFT_FW_DBG2_8197F)
+#define BITS_FW_DBG2_8197F (BIT_MASK_FW_DBG2_8197F << BIT_SHIFT_FW_DBG2_8197F)
+#define BIT_CLEAR_FW_DBG2_8197F(x) ((x) & (~BITS_FW_DBG2_8197F))
+#define BIT_GET_FW_DBG2_8197F(x) \
+ (((x) >> BIT_SHIFT_FW_DBG2_8197F) & BIT_MASK_FW_DBG2_8197F)
+#define BIT_SET_FW_DBG2_8197F(x, v) \
+ (BIT_CLEAR_FW_DBG2_8197F(x) | BIT_FW_DBG2_8197F(v))
+
+/* 2 REG_FW_DBG3_8197F */
+
+#define BIT_SHIFT_FW_DBG3_8197F 0
+#define BIT_MASK_FW_DBG3_8197F 0xffffffffL
+#define BIT_FW_DBG3_8197F(x) \
+ (((x) & BIT_MASK_FW_DBG3_8197F) << BIT_SHIFT_FW_DBG3_8197F)
+#define BITS_FW_DBG3_8197F (BIT_MASK_FW_DBG3_8197F << BIT_SHIFT_FW_DBG3_8197F)
+#define BIT_CLEAR_FW_DBG3_8197F(x) ((x) & (~BITS_FW_DBG3_8197F))
+#define BIT_GET_FW_DBG3_8197F(x) \
+ (((x) >> BIT_SHIFT_FW_DBG3_8197F) & BIT_MASK_FW_DBG3_8197F)
+#define BIT_SET_FW_DBG3_8197F(x, v) \
+ (BIT_CLEAR_FW_DBG3_8197F(x) | BIT_FW_DBG3_8197F(v))
+
+/* 2 REG_FW_DBG4_8197F */
+
+#define BIT_SHIFT_FW_DBG4_8197F 0
+#define BIT_MASK_FW_DBG4_8197F 0xffffffffL
+#define BIT_FW_DBG4_8197F(x) \
+ (((x) & BIT_MASK_FW_DBG4_8197F) << BIT_SHIFT_FW_DBG4_8197F)
+#define BITS_FW_DBG4_8197F (BIT_MASK_FW_DBG4_8197F << BIT_SHIFT_FW_DBG4_8197F)
+#define BIT_CLEAR_FW_DBG4_8197F(x) ((x) & (~BITS_FW_DBG4_8197F))
+#define BIT_GET_FW_DBG4_8197F(x) \
+ (((x) >> BIT_SHIFT_FW_DBG4_8197F) & BIT_MASK_FW_DBG4_8197F)
+#define BIT_SET_FW_DBG4_8197F(x, v) \
+ (BIT_CLEAR_FW_DBG4_8197F(x) | BIT_FW_DBG4_8197F(v))
+
+/* 2 REG_FW_DBG5_8197F */
+
+#define BIT_SHIFT_FW_DBG5_8197F 0
+#define BIT_MASK_FW_DBG5_8197F 0xffffffffL
+#define BIT_FW_DBG5_8197F(x) \
+ (((x) & BIT_MASK_FW_DBG5_8197F) << BIT_SHIFT_FW_DBG5_8197F)
+#define BITS_FW_DBG5_8197F (BIT_MASK_FW_DBG5_8197F << BIT_SHIFT_FW_DBG5_8197F)
+#define BIT_CLEAR_FW_DBG5_8197F(x) ((x) & (~BITS_FW_DBG5_8197F))
+#define BIT_GET_FW_DBG5_8197F(x) \
+ (((x) >> BIT_SHIFT_FW_DBG5_8197F) & BIT_MASK_FW_DBG5_8197F)
+#define BIT_SET_FW_DBG5_8197F(x, v) \
+ (BIT_CLEAR_FW_DBG5_8197F(x) | BIT_FW_DBG5_8197F(v))
+
+/* 2 REG_FW_DBG6_8197F */
+
+#define BIT_SHIFT_FW_DBG6_8197F 0
+#define BIT_MASK_FW_DBG6_8197F 0xffffffffL
+#define BIT_FW_DBG6_8197F(x) \
+ (((x) & BIT_MASK_FW_DBG6_8197F) << BIT_SHIFT_FW_DBG6_8197F)
+#define BITS_FW_DBG6_8197F (BIT_MASK_FW_DBG6_8197F << BIT_SHIFT_FW_DBG6_8197F)
+#define BIT_CLEAR_FW_DBG6_8197F(x) ((x) & (~BITS_FW_DBG6_8197F))
+#define BIT_GET_FW_DBG6_8197F(x) \
+ (((x) >> BIT_SHIFT_FW_DBG6_8197F) & BIT_MASK_FW_DBG6_8197F)
+#define BIT_SET_FW_DBG6_8197F(x, v) \
+ (BIT_CLEAR_FW_DBG6_8197F(x) | BIT_FW_DBG6_8197F(v))
+
+/* 2 REG_FW_DBG7_8197F */
+
+#define BIT_SHIFT_FW_DBG7_8197F 0
+#define BIT_MASK_FW_DBG7_8197F 0xffffffffL
+#define BIT_FW_DBG7_8197F(x) \
+ (((x) & BIT_MASK_FW_DBG7_8197F) << BIT_SHIFT_FW_DBG7_8197F)
+#define BITS_FW_DBG7_8197F (BIT_MASK_FW_DBG7_8197F << BIT_SHIFT_FW_DBG7_8197F)
+#define BIT_CLEAR_FW_DBG7_8197F(x) ((x) & (~BITS_FW_DBG7_8197F))
+#define BIT_GET_FW_DBG7_8197F(x) \
+ (((x) >> BIT_SHIFT_FW_DBG7_8197F) & BIT_MASK_FW_DBG7_8197F)
+#define BIT_SET_FW_DBG7_8197F(x, v) \
+ (BIT_CLEAR_FW_DBG7_8197F(x) | BIT_FW_DBG7_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_CR_8197F (ENABLE FUNCTION REGISTER) */
+#define BIT_MACIO_TIMEOUT_EN_8197F BIT(29)
+
+#define BIT_SHIFT_LBMODE_8197F 24
+#define BIT_MASK_LBMODE_8197F 0x1f
+#define BIT_LBMODE_8197F(x) \
+ (((x) & BIT_MASK_LBMODE_8197F) << BIT_SHIFT_LBMODE_8197F)
+#define BITS_LBMODE_8197F (BIT_MASK_LBMODE_8197F << BIT_SHIFT_LBMODE_8197F)
+#define BIT_CLEAR_LBMODE_8197F(x) ((x) & (~BITS_LBMODE_8197F))
+#define BIT_GET_LBMODE_8197F(x) \
+ (((x) >> BIT_SHIFT_LBMODE_8197F) & BIT_MASK_LBMODE_8197F)
+#define BIT_SET_LBMODE_8197F(x, v) \
+ (BIT_CLEAR_LBMODE_8197F(x) | BIT_LBMODE_8197F(v))
+
+#define BIT_SHIFT_NETYPE1_8197F 18
+#define BIT_MASK_NETYPE1_8197F 0x3
+#define BIT_NETYPE1_8197F(x) \
+ (((x) & BIT_MASK_NETYPE1_8197F) << BIT_SHIFT_NETYPE1_8197F)
+#define BITS_NETYPE1_8197F (BIT_MASK_NETYPE1_8197F << BIT_SHIFT_NETYPE1_8197F)
+#define BIT_CLEAR_NETYPE1_8197F(x) ((x) & (~BITS_NETYPE1_8197F))
+#define BIT_GET_NETYPE1_8197F(x) \
+ (((x) >> BIT_SHIFT_NETYPE1_8197F) & BIT_MASK_NETYPE1_8197F)
+#define BIT_SET_NETYPE1_8197F(x, v) \
+ (BIT_CLEAR_NETYPE1_8197F(x) | BIT_NETYPE1_8197F(v))
+
+#define BIT_SHIFT_NETYPE0_8197F 16
+#define BIT_MASK_NETYPE0_8197F 0x3
+#define BIT_NETYPE0_8197F(x) \
+ (((x) & BIT_MASK_NETYPE0_8197F) << BIT_SHIFT_NETYPE0_8197F)
+#define BITS_NETYPE0_8197F (BIT_MASK_NETYPE0_8197F << BIT_SHIFT_NETYPE0_8197F)
+#define BIT_CLEAR_NETYPE0_8197F(x) ((x) & (~BITS_NETYPE0_8197F))
+#define BIT_GET_NETYPE0_8197F(x) \
+ (((x) >> BIT_SHIFT_NETYPE0_8197F) & BIT_MASK_NETYPE0_8197F)
+#define BIT_SET_NETYPE0_8197F(x, v) \
+ (BIT_CLEAR_NETYPE0_8197F(x) | BIT_NETYPE0_8197F(v))
+
+#define BIT_STAT_FUNC_RST_8197F BIT(13)
+#define BIT_I2C_MAILBOX_EN_8197F BIT(12)
+#define BIT_SHCUT_EN_8197F BIT(11)
+#define BIT_32K_CAL_TMR_EN_8197F BIT(10)
+#define BIT_MAC_SEC_EN_8197F BIT(9)
+#define BIT_ENSWBCN_8197F BIT(8)
+#define BIT_MACRXEN_8197F BIT(7)
+#define BIT_MACTXEN_8197F BIT(6)
+#define BIT_SCHEDULE_EN_8197F BIT(5)
+#define BIT_PROTOCOL_EN_8197F BIT(4)
+#define BIT_RXDMA_EN_8197F BIT(3)
+#define BIT_TXDMA_EN_8197F BIT(2)
+#define BIT_HCI_RXDMA_EN_8197F BIT(1)
+#define BIT_HCI_TXDMA_EN_8197F BIT(0)
+
+/* 2 REG_TSF_CLK_STATE_8197F */
+#define BIT_TSF_CLK_STABLE_8197F BIT(15)
+
+/* 2 REG_TXDMA_PQ_MAP_8197F */
+
+#define BIT_SHIFT_TXDMA_HIQ_MAP_8197F 14
+#define BIT_MASK_TXDMA_HIQ_MAP_8197F 0x3
+#define BIT_TXDMA_HIQ_MAP_8197F(x) \
+ (((x) & BIT_MASK_TXDMA_HIQ_MAP_8197F) << BIT_SHIFT_TXDMA_HIQ_MAP_8197F)
+#define BITS_TXDMA_HIQ_MAP_8197F \
+ (BIT_MASK_TXDMA_HIQ_MAP_8197F << BIT_SHIFT_TXDMA_HIQ_MAP_8197F)
+#define BIT_CLEAR_TXDMA_HIQ_MAP_8197F(x) ((x) & (~BITS_TXDMA_HIQ_MAP_8197F))
+#define BIT_GET_TXDMA_HIQ_MAP_8197F(x) \
+ (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8197F) & BIT_MASK_TXDMA_HIQ_MAP_8197F)
+#define BIT_SET_TXDMA_HIQ_MAP_8197F(x, v) \
+ (BIT_CLEAR_TXDMA_HIQ_MAP_8197F(x) | BIT_TXDMA_HIQ_MAP_8197F(v))
+
+#define BIT_SHIFT_TXDMA_MGQ_MAP_8197F 12
+#define BIT_MASK_TXDMA_MGQ_MAP_8197F 0x3
+#define BIT_TXDMA_MGQ_MAP_8197F(x) \
+ (((x) & BIT_MASK_TXDMA_MGQ_MAP_8197F) << BIT_SHIFT_TXDMA_MGQ_MAP_8197F)
+#define BITS_TXDMA_MGQ_MAP_8197F \
+ (BIT_MASK_TXDMA_MGQ_MAP_8197F << BIT_SHIFT_TXDMA_MGQ_MAP_8197F)
+#define BIT_CLEAR_TXDMA_MGQ_MAP_8197F(x) ((x) & (~BITS_TXDMA_MGQ_MAP_8197F))
+#define BIT_GET_TXDMA_MGQ_MAP_8197F(x) \
+ (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8197F) & BIT_MASK_TXDMA_MGQ_MAP_8197F)
+#define BIT_SET_TXDMA_MGQ_MAP_8197F(x, v) \
+ (BIT_CLEAR_TXDMA_MGQ_MAP_8197F(x) | BIT_TXDMA_MGQ_MAP_8197F(v))
+
+#define BIT_SHIFT_TXDMA_BKQ_MAP_8197F 10
+#define BIT_MASK_TXDMA_BKQ_MAP_8197F 0x3
+#define BIT_TXDMA_BKQ_MAP_8197F(x) \
+ (((x) & BIT_MASK_TXDMA_BKQ_MAP_8197F) << BIT_SHIFT_TXDMA_BKQ_MAP_8197F)
+#define BITS_TXDMA_BKQ_MAP_8197F \
+ (BIT_MASK_TXDMA_BKQ_MAP_8197F << BIT_SHIFT_TXDMA_BKQ_MAP_8197F)
+#define BIT_CLEAR_TXDMA_BKQ_MAP_8197F(x) ((x) & (~BITS_TXDMA_BKQ_MAP_8197F))
+#define BIT_GET_TXDMA_BKQ_MAP_8197F(x) \
+ (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8197F) & BIT_MASK_TXDMA_BKQ_MAP_8197F)
+#define BIT_SET_TXDMA_BKQ_MAP_8197F(x, v) \
+ (BIT_CLEAR_TXDMA_BKQ_MAP_8197F(x) | BIT_TXDMA_BKQ_MAP_8197F(v))
+
+#define BIT_SHIFT_TXDMA_BEQ_MAP_8197F 8
+#define BIT_MASK_TXDMA_BEQ_MAP_8197F 0x3
+#define BIT_TXDMA_BEQ_MAP_8197F(x) \
+ (((x) & BIT_MASK_TXDMA_BEQ_MAP_8197F) << BIT_SHIFT_TXDMA_BEQ_MAP_8197F)
+#define BITS_TXDMA_BEQ_MAP_8197F \
+ (BIT_MASK_TXDMA_BEQ_MAP_8197F << BIT_SHIFT_TXDMA_BEQ_MAP_8197F)
+#define BIT_CLEAR_TXDMA_BEQ_MAP_8197F(x) ((x) & (~BITS_TXDMA_BEQ_MAP_8197F))
+#define BIT_GET_TXDMA_BEQ_MAP_8197F(x) \
+ (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8197F) & BIT_MASK_TXDMA_BEQ_MAP_8197F)
+#define BIT_SET_TXDMA_BEQ_MAP_8197F(x, v) \
+ (BIT_CLEAR_TXDMA_BEQ_MAP_8197F(x) | BIT_TXDMA_BEQ_MAP_8197F(v))
+
+#define BIT_SHIFT_TXDMA_VIQ_MAP_8197F 6
+#define BIT_MASK_TXDMA_VIQ_MAP_8197F 0x3
+#define BIT_TXDMA_VIQ_MAP_8197F(x) \
+ (((x) & BIT_MASK_TXDMA_VIQ_MAP_8197F) << BIT_SHIFT_TXDMA_VIQ_MAP_8197F)
+#define BITS_TXDMA_VIQ_MAP_8197F \
+ (BIT_MASK_TXDMA_VIQ_MAP_8197F << BIT_SHIFT_TXDMA_VIQ_MAP_8197F)
+#define BIT_CLEAR_TXDMA_VIQ_MAP_8197F(x) ((x) & (~BITS_TXDMA_VIQ_MAP_8197F))
+#define BIT_GET_TXDMA_VIQ_MAP_8197F(x) \
+ (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8197F) & BIT_MASK_TXDMA_VIQ_MAP_8197F)
+#define BIT_SET_TXDMA_VIQ_MAP_8197F(x, v) \
+ (BIT_CLEAR_TXDMA_VIQ_MAP_8197F(x) | BIT_TXDMA_VIQ_MAP_8197F(v))
+
+#define BIT_SHIFT_TXDMA_VOQ_MAP_8197F 4
+#define BIT_MASK_TXDMA_VOQ_MAP_8197F 0x3
+#define BIT_TXDMA_VOQ_MAP_8197F(x) \
+ (((x) & BIT_MASK_TXDMA_VOQ_MAP_8197F) << BIT_SHIFT_TXDMA_VOQ_MAP_8197F)
+#define BITS_TXDMA_VOQ_MAP_8197F \
+ (BIT_MASK_TXDMA_VOQ_MAP_8197F << BIT_SHIFT_TXDMA_VOQ_MAP_8197F)
+#define BIT_CLEAR_TXDMA_VOQ_MAP_8197F(x) ((x) & (~BITS_TXDMA_VOQ_MAP_8197F))
+#define BIT_GET_TXDMA_VOQ_MAP_8197F(x) \
+ (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8197F) & BIT_MASK_TXDMA_VOQ_MAP_8197F)
+#define BIT_SET_TXDMA_VOQ_MAP_8197F(x, v) \
+ (BIT_CLEAR_TXDMA_VOQ_MAP_8197F(x) | BIT_TXDMA_VOQ_MAP_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+#define BIT_RXDMA_AGG_EN_8197F BIT(2)
+#define BIT_RXSHFT_EN_8197F BIT(1)
+#define BIT_RXDMA_ARBBW_EN_8197F BIT(0)
+
+/* 2 REG_TRXFF_BNDY_8197F */
+
+#define BIT_SHIFT_RXFFOVFL_RSV_V2_8197F 8
+#define BIT_MASK_RXFFOVFL_RSV_V2_8197F 0xf
+#define BIT_RXFFOVFL_RSV_V2_8197F(x) \
+ (((x) & BIT_MASK_RXFFOVFL_RSV_V2_8197F) \
+ << BIT_SHIFT_RXFFOVFL_RSV_V2_8197F)
+#define BITS_RXFFOVFL_RSV_V2_8197F \
+ (BIT_MASK_RXFFOVFL_RSV_V2_8197F << BIT_SHIFT_RXFFOVFL_RSV_V2_8197F)
+#define BIT_CLEAR_RXFFOVFL_RSV_V2_8197F(x) ((x) & (~BITS_RXFFOVFL_RSV_V2_8197F))
+#define BIT_GET_RXFFOVFL_RSV_V2_8197F(x) \
+ (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8197F) & \
+ BIT_MASK_RXFFOVFL_RSV_V2_8197F)
+#define BIT_SET_RXFFOVFL_RSV_V2_8197F(x, v) \
+ (BIT_CLEAR_RXFFOVFL_RSV_V2_8197F(x) | BIT_RXFFOVFL_RSV_V2_8197F(v))
+
+#define BIT_SHIFT_TXPKTBUF_PGBNDY_8197F 0
+#define BIT_MASK_TXPKTBUF_PGBNDY_8197F 0xff
+#define BIT_TXPKTBUF_PGBNDY_8197F(x) \
+ (((x) & BIT_MASK_TXPKTBUF_PGBNDY_8197F) \
+ << BIT_SHIFT_TXPKTBUF_PGBNDY_8197F)
+#define BITS_TXPKTBUF_PGBNDY_8197F \
+ (BIT_MASK_TXPKTBUF_PGBNDY_8197F << BIT_SHIFT_TXPKTBUF_PGBNDY_8197F)
+#define BIT_CLEAR_TXPKTBUF_PGBNDY_8197F(x) ((x) & (~BITS_TXPKTBUF_PGBNDY_8197F))
+#define BIT_GET_TXPKTBUF_PGBNDY_8197F(x) \
+ (((x) >> BIT_SHIFT_TXPKTBUF_PGBNDY_8197F) & \
+ BIT_MASK_TXPKTBUF_PGBNDY_8197F)
+#define BIT_SET_TXPKTBUF_PGBNDY_8197F(x, v) \
+ (BIT_CLEAR_TXPKTBUF_PGBNDY_8197F(x) | BIT_TXPKTBUF_PGBNDY_8197F(v))
+
+/* 2 REG_PTA_I2C_MBOX_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+#define BIT_SHIFT_I2C_M_STATUS_8197F 8
+#define BIT_MASK_I2C_M_STATUS_8197F 0xf
+#define BIT_I2C_M_STATUS_8197F(x) \
+ (((x) & BIT_MASK_I2C_M_STATUS_8197F) << BIT_SHIFT_I2C_M_STATUS_8197F)
+#define BITS_I2C_M_STATUS_8197F \
+ (BIT_MASK_I2C_M_STATUS_8197F << BIT_SHIFT_I2C_M_STATUS_8197F)
+#define BIT_CLEAR_I2C_M_STATUS_8197F(x) ((x) & (~BITS_I2C_M_STATUS_8197F))
+#define BIT_GET_I2C_M_STATUS_8197F(x) \
+ (((x) >> BIT_SHIFT_I2C_M_STATUS_8197F) & BIT_MASK_I2C_M_STATUS_8197F)
+#define BIT_SET_I2C_M_STATUS_8197F(x, v) \
+ (BIT_CLEAR_I2C_M_STATUS_8197F(x) | BIT_I2C_M_STATUS_8197F(v))
+
+#define BIT_SHIFT_I2C_M_BUS_GNT_FW_8197F 4
+#define BIT_MASK_I2C_M_BUS_GNT_FW_8197F 0x7
+#define BIT_I2C_M_BUS_GNT_FW_8197F(x) \
+ (((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8197F) \
+ << BIT_SHIFT_I2C_M_BUS_GNT_FW_8197F)
+#define BITS_I2C_M_BUS_GNT_FW_8197F \
+ (BIT_MASK_I2C_M_BUS_GNT_FW_8197F << BIT_SHIFT_I2C_M_BUS_GNT_FW_8197F)
+#define BIT_CLEAR_I2C_M_BUS_GNT_FW_8197F(x) \
+ ((x) & (~BITS_I2C_M_BUS_GNT_FW_8197F))
+#define BIT_GET_I2C_M_BUS_GNT_FW_8197F(x) \
+ (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8197F) & \
+ BIT_MASK_I2C_M_BUS_GNT_FW_8197F)
+#define BIT_SET_I2C_M_BUS_GNT_FW_8197F(x, v) \
+ (BIT_CLEAR_I2C_M_BUS_GNT_FW_8197F(x) | BIT_I2C_M_BUS_GNT_FW_8197F(v))
+
+#define BIT_I2C_M_GNT_FW_8197F BIT(3)
+
+#define BIT_SHIFT_I2C_M_SPEED_8197F 1
+#define BIT_MASK_I2C_M_SPEED_8197F 0x3
+#define BIT_I2C_M_SPEED_8197F(x) \
+ (((x) & BIT_MASK_I2C_M_SPEED_8197F) << BIT_SHIFT_I2C_M_SPEED_8197F)
+#define BITS_I2C_M_SPEED_8197F \
+ (BIT_MASK_I2C_M_SPEED_8197F << BIT_SHIFT_I2C_M_SPEED_8197F)
+#define BIT_CLEAR_I2C_M_SPEED_8197F(x) ((x) & (~BITS_I2C_M_SPEED_8197F))
+#define BIT_GET_I2C_M_SPEED_8197F(x) \
+ (((x) >> BIT_SHIFT_I2C_M_SPEED_8197F) & BIT_MASK_I2C_M_SPEED_8197F)
+#define BIT_SET_I2C_M_SPEED_8197F(x, v) \
+ (BIT_CLEAR_I2C_M_SPEED_8197F(x) | BIT_I2C_M_SPEED_8197F(v))
+
+#define BIT_I2C_M_UNLOCK_8197F BIT(0)
+
+/* 2 REG_RXFF_BNDY_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+#define BIT_SHIFT_RXFF0_BNDY_V2_8197F 0
+#define BIT_MASK_RXFF0_BNDY_V2_8197F 0x3ffff
+#define BIT_RXFF0_BNDY_V2_8197F(x) \
+ (((x) & BIT_MASK_RXFF0_BNDY_V2_8197F) << BIT_SHIFT_RXFF0_BNDY_V2_8197F)
+#define BITS_RXFF0_BNDY_V2_8197F \
+ (BIT_MASK_RXFF0_BNDY_V2_8197F << BIT_SHIFT_RXFF0_BNDY_V2_8197F)
+#define BIT_CLEAR_RXFF0_BNDY_V2_8197F(x) ((x) & (~BITS_RXFF0_BNDY_V2_8197F))
+#define BIT_GET_RXFF0_BNDY_V2_8197F(x) \
+ (((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8197F) & BIT_MASK_RXFF0_BNDY_V2_8197F)
+#define BIT_SET_RXFF0_BNDY_V2_8197F(x, v) \
+ (BIT_CLEAR_RXFF0_BNDY_V2_8197F(x) | BIT_RXFF0_BNDY_V2_8197F(v))
+
+/* 2 REG_FE1IMR_8197F */
+#define BIT_BB_STOP_RX_INT_EN_8197F BIT(29)
+#define BIT_FS_RXDMA2_DONE_INT_EN_8197F BIT(28)
+#define BIT_FS_RXDONE3_INT_EN_8197F BIT(27)
+#define BIT_FS_RXDONE2_INT_EN_8197F BIT(26)
+#define BIT_FS_RX_BCN_P4_INT_EN_8197F BIT(25)
+#define BIT_FS_RX_BCN_P3_INT_EN_8197F BIT(24)
+#define BIT_FS_RX_BCN_P2_INT_EN_8197F BIT(23)
+#define BIT_FS_RX_BCN_P1_INT_EN_8197F BIT(22)
+#define BIT_FS_RX_BCN_P0_INT_EN_8197F BIT(21)
+#define BIT_FS_RX_UMD0_INT_EN_8197F BIT(20)
+#define BIT_FS_RX_UMD1_INT_EN_8197F BIT(19)
+#define BIT_FS_RX_BMD0_INT_EN_8197F BIT(18)
+#define BIT_FS_RX_BMD1_INT_EN_8197F BIT(17)
+#define BIT_FS_RXDONE_INT_EN_8197F BIT(16)
+#define BIT_FS_WWLAN_INT_EN_8197F BIT(15)
+#define BIT_FS_SOUND_DONE_INT_EN_8197F BIT(14)
+#define BIT_FS_LP_STBY_INT_EN_8197F BIT(13)
+#define BIT_FS_TRL_MTR_INT_EN_8197F BIT(12)
+#define BIT_FS_BF1_PRETO_INT_EN_8197F BIT(11)
+#define BIT_FS_BF0_PRETO_INT_EN_8197F BIT(10)
+#define BIT_FS_PTCL_RELEASE_MACID_INT_EN_8197F BIT(9)
+#define BIT_FS_LTE_COEX_EN_8197F BIT(6)
+#define BIT_FS_WLACTOFF_INT_EN_8197F BIT(5)
+#define BIT_FS_WLACTON_INT_EN_8197F BIT(4)
+#define BIT_FS_BTCMD_INT_EN_8197F BIT(3)
+#define BIT_FS_REG_MAILBOX_TO_I2C_INT_EN_8197F BIT(2)
+#define BIT_FS_TRPC_TO_INT_EN_V1_8197F BIT(1)
+#define BIT_FS_RPC_O_T_INT_EN_V1_8197F BIT(0)
+
+/* 2 REG_FE1ISR_8197F */
+#define BIT_BB_STOP_RX_INT_8197F BIT(29)
+#define BIT_FS_RXDMA2_DONE_INT_8197F BIT(28)
+#define BIT_FS_RXDONE3_INT_8197F BIT(27)
+#define BIT_FS_RXDONE2_INT_8197F BIT(26)
+#define BIT_FS_RX_BCN_P4_INT_8197F BIT(25)
+#define BIT_FS_RX_BCN_P3_INT_8197F BIT(24)
+#define BIT_FS_RX_BCN_P2_INT_8197F BIT(23)
+#define BIT_FS_RX_BCN_P1_INT_8197F BIT(22)
+#define BIT_FS_RX_BCN_P0_INT_8197F BIT(21)
+#define BIT_FS_RX_UMD0_INT_8197F BIT(20)
+#define BIT_FS_RX_UMD1_INT_8197F BIT(19)
+#define BIT_FS_RX_BMD0_INT_8197F BIT(18)
+#define BIT_FS_RX_BMD1_INT_8197F BIT(17)
+#define BIT_FS_RXDONE_INT_8197F BIT(16)
+#define BIT_FS_WWLAN_INT_8197F BIT(15)
+#define BIT_FS_SOUND_DONE_INT_8197F BIT(14)
+#define BIT_FS_LP_STBY_INT_8197F BIT(13)
+#define BIT_FS_TRL_MTR_INT_8197F BIT(12)
+#define BIT_FS_BF1_PRETO_INT_8197F BIT(11)
+#define BIT_FS_BF0_PRETO_INT_8197F BIT(10)
+#define BIT_FS_PTCL_RELEASE_MACID_INT_8197F BIT(9)
+#define BIT_FS_LTE_COEX_INT_8197F BIT(6)
+#define BIT_FS_WLACTOFF_INT_8197F BIT(5)
+#define BIT_FS_WLACTON_INT_8197F BIT(4)
+#define BIT_FS_BCN_RX_INT_INT_8197F BIT(3)
+#define BIT_FS_MAILBOX_TO_I2C_INT_8197F BIT(2)
+#define BIT_FS_TRPC_TO_INT_8197F BIT(1)
+#define BIT_FS_RPC_O_T_INT_8197F BIT(0)
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_CPWM_8197F */
+#define BIT_CPWM_TOGGLING_8197F BIT(31)
+
+#define BIT_SHIFT_CPWM_MOD_8197F 24
+#define BIT_MASK_CPWM_MOD_8197F 0x7f
+#define BIT_CPWM_MOD_8197F(x) \
+ (((x) & BIT_MASK_CPWM_MOD_8197F) << BIT_SHIFT_CPWM_MOD_8197F)
+#define BITS_CPWM_MOD_8197F \
+ (BIT_MASK_CPWM_MOD_8197F << BIT_SHIFT_CPWM_MOD_8197F)
+#define BIT_CLEAR_CPWM_MOD_8197F(x) ((x) & (~BITS_CPWM_MOD_8197F))
+#define BIT_GET_CPWM_MOD_8197F(x) \
+ (((x) >> BIT_SHIFT_CPWM_MOD_8197F) & BIT_MASK_CPWM_MOD_8197F)
+#define BIT_SET_CPWM_MOD_8197F(x, v) \
+ (BIT_CLEAR_CPWM_MOD_8197F(x) | BIT_CPWM_MOD_8197F(v))
+
+/* 2 REG_FWIMR_8197F */
+#define BIT_FS_TXBCNOK_MB7_INT_EN_8197F BIT(31)
+#define BIT_FS_TXBCNOK_MB6_INT_EN_8197F BIT(30)
+#define BIT_FS_TXBCNOK_MB5_INT_EN_8197F BIT(29)
+#define BIT_FS_TXBCNOK_MB4_INT_EN_8197F BIT(28)
+#define BIT_FS_TXBCNOK_MB3_INT_EN_8197F BIT(27)
+#define BIT_FS_TXBCNOK_MB2_INT_EN_8197F BIT(26)
+#define BIT_FS_TXBCNOK_MB1_INT_EN_8197F BIT(25)
+#define BIT_FS_TXBCNOK_MB0_INT_EN_8197F BIT(24)
+#define BIT_FS_TXBCNERR_MB7_INT_EN_8197F BIT(23)
+#define BIT_FS_TXBCNERR_MB6_INT_EN_8197F BIT(22)
+#define BIT_FS_TXBCNERR_MB5_INT_EN_8197F BIT(21)
+#define BIT_FS_TXBCNERR_MB4_INT_EN_8197F BIT(20)
+#define BIT_FS_TXBCNERR_MB3_INT_EN_8197F BIT(19)
+#define BIT_FS_TXBCNERR_MB2_INT_EN_8197F BIT(18)
+#define BIT_FS_TXBCNERR_MB1_INT_EN_8197F BIT(17)
+#define BIT_FS_TXBCNERR_MB0_INT_EN_8197F BIT(16)
+#define BIT_CPUMGN_POLLED_PKT_DONE_INT_EN_8197F BIT(15)
+#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_EN_8197F BIT(13)
+#define BIT_FS_MGNTQFF_TO_INT_EN_8197F BIT(12)
+#define BIT_FS_DDMA1_LP_INT_ENBIT_CPUMGN_POLLED_PKT_BUSY_ERR_INT_EN_8197F \
+ BIT(11)
+#define BIT_FS_DDMA1_HP_INT_EN_8197F BIT(10)
+#define BIT_FS_DDMA0_LP_INT_EN_8197F BIT(9)
+#define BIT_FS_DDMA0_HP_INT_EN_8197F BIT(8)
+#define BIT_FS_TRXRPT_INT_EN_8197F BIT(7)
+#define BIT_FS_C2H_W_READY_INT_EN_8197F BIT(6)
+#define BIT_FS_HRCV_INT_EN_8197F BIT(5)
+#define BIT_FS_H2CCMD_INT_EN_8197F BIT(4)
+#define BIT_FS_TXPKTIN_INT_EN_8197F BIT(3)
+#define BIT_FS_ERRORHDL_INT_EN_8197F BIT(2)
+#define BIT_FS_TXCCX_INT_EN_8197F BIT(1)
+#define BIT_FS_TXCLOSE_INT_EN_8197F BIT(0)
+
+/* 2 REG_FWISR_8197F */
+#define BIT_FS_TXBCNOK_MB7_INT_8197F BIT(31)
+#define BIT_FS_TXBCNOK_MB6_INT_8197F BIT(30)
+#define BIT_FS_TXBCNOK_MB5_INT_8197F BIT(29)
+#define BIT_FS_TXBCNOK_MB4_INT_8197F BIT(28)
+#define BIT_FS_TXBCNOK_MB3_INT_8197F BIT(27)
+#define BIT_FS_TXBCNOK_MB2_INT_8197F BIT(26)
+#define BIT_FS_TXBCNOK_MB1_INT_8197F BIT(25)
+#define BIT_FS_TXBCNOK_MB0_INT_8197F BIT(24)
+#define BIT_FS_TXBCNERR_MB7_INT_8197F BIT(23)
+#define BIT_FS_TXBCNERR_MB6_INT_8197F BIT(22)
+#define BIT_FS_TXBCNERR_MB5_INT_8197F BIT(21)
+#define BIT_FS_TXBCNERR_MB4_INT_8197F BIT(20)
+#define BIT_FS_TXBCNERR_MB3_INT_8197F BIT(19)
+#define BIT_FS_TXBCNERR_MB2_INT_8197F BIT(18)
+#define BIT_FS_TXBCNERR_MB1_INT_8197F BIT(17)
+#define BIT_FS_TXBCNERR_MB0_INT_8197F BIT(16)
+#define BIT_CPUMGN_POLLED_PKT_DONE_INT_8197F BIT(15)
+#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_8197F BIT(13)
+#define BIT_FS_MGNTQFF_TO_INT_8197F BIT(12)
+#define BIT_FS_DDMA1_LP_INTBIT_CPUMGN_POLLED_PKT_BUSY_ERR_INT_8197F BIT(11)
+#define BIT_FS_DDMA1_HP_INT_8197F BIT(10)
+#define BIT_FS_DDMA0_LP_INT_8197F BIT(9)
+#define BIT_FS_DDMA0_HP_INT_8197F BIT(8)
+#define BIT_FS_TRXRPT_INT_8197F BIT(7)
+#define BIT_FS_C2H_W_READY_INT_8197F BIT(6)
+#define BIT_FS_HRCV_INT_8197F BIT(5)
+#define BIT_FS_H2CCMD_INT_8197F BIT(4)
+#define BIT_FS_TXPKTIN_INT_8197F BIT(3)
+#define BIT_FS_ERRORHDL_INT_8197F BIT(2)
+#define BIT_FS_TXCCX_INT_8197F BIT(1)
+#define BIT_FS_TXCLOSE_INT_8197F BIT(0)
+
+/* 2 REG_FTIMR_8197F */
+#define BIT_PS_TIMER_C_EARLY_INT_EN_8197F BIT(23)
+#define BIT_PS_TIMER_B_EARLY_INT_EN_8197F BIT(22)
+#define BIT_PS_TIMER_A_EARLY_INT_EN_8197F BIT(21)
+#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_EN_8197F BIT(20)
+#define BIT_PS_TIMER_C_INT_EN_8197F BIT(19)
+#define BIT_PS_TIMER_B_INT_EN_8197F BIT(18)
+#define BIT_PS_TIMER_A_INT_EN_8197F BIT(17)
+#define BIT_CPUMGQ_TX_TIMER_INT_EN_8197F BIT(16)
+#define BIT_FS_PS_TIMEOUT2_EN_8197F BIT(15)
+#define BIT_FS_PS_TIMEOUT1_EN_8197F BIT(14)
+#define BIT_FS_PS_TIMEOUT0_EN_8197F BIT(13)
+#define BIT_FS_GTINT8_EN_8197F BIT(8)
+#define BIT_FS_GTINT7_EN_8197F BIT(7)
+#define BIT_FS_GTINT6_EN_8197F BIT(6)
+#define BIT_FS_GTINT5_EN_8197F BIT(5)
+#define BIT_FS_GTINT4_EN_8197F BIT(4)
+#define BIT_FS_GTINT3_EN_8197F BIT(3)
+#define BIT_FS_GTINT2_EN_8197F BIT(2)
+#define BIT_FS_GTINT1_EN_8197F BIT(1)
+#define BIT_FS_GTINT0_EN_8197F BIT(0)
+
+/* 2 REG_FTISR_8197F */
+#define BIT_PS_TIMER_C_EARLY__INT_8197F BIT(23)
+#define BIT_PS_TIMER_B_EARLY__INT_8197F BIT(22)
+#define BIT_PS_TIMER_A_EARLY__INT_8197F BIT(21)
+#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_8197F BIT(20)
+#define BIT_PS_TIMER_C_INT_8197F BIT(19)
+#define BIT_PS_TIMER_B_INT_8197F BIT(18)
+#define BIT_PS_TIMER_A_INT_8197F BIT(17)
+#define BIT_CPUMGQ_TX_TIMER_INT_8197F BIT(16)
+#define BIT_FS_PS_TIMEOUT2_INT_8197F BIT(15)
+#define BIT_FS_PS_TIMEOUT1_INT_8197F BIT(14)
+#define BIT_FS_PS_TIMEOUT0_INT_8197F BIT(13)
+#define BIT_FS_GTINT8_INT_8197F BIT(8)
+#define BIT_FS_GTINT7_INT_8197F BIT(7)
+#define BIT_FS_GTINT6_INT_8197F BIT(6)
+#define BIT_FS_GTINT5_INT_8197F BIT(5)
+#define BIT_FS_GTINT4_INT_8197F BIT(4)
+#define BIT_FS_GTINT3_INT_8197F BIT(3)
+#define BIT_FS_GTINT2_INT_8197F BIT(2)
+#define BIT_FS_GTINT1_INT_8197F BIT(1)
+#define BIT_FS_GTINT0_INT_8197F BIT(0)
+
+/* 2 REG_PKTBUF_DBG_CTRL_8197F */
+
+#define BIT_SHIFT_PKTBUF_WRITE_EN_8197F 24
+#define BIT_MASK_PKTBUF_WRITE_EN_8197F 0xff
+#define BIT_PKTBUF_WRITE_EN_8197F(x) \
+ (((x) & BIT_MASK_PKTBUF_WRITE_EN_8197F) \
+ << BIT_SHIFT_PKTBUF_WRITE_EN_8197F)
+#define BITS_PKTBUF_WRITE_EN_8197F \
+ (BIT_MASK_PKTBUF_WRITE_EN_8197F << BIT_SHIFT_PKTBUF_WRITE_EN_8197F)
+#define BIT_CLEAR_PKTBUF_WRITE_EN_8197F(x) ((x) & (~BITS_PKTBUF_WRITE_EN_8197F))
+#define BIT_GET_PKTBUF_WRITE_EN_8197F(x) \
+ (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8197F) & \
+ BIT_MASK_PKTBUF_WRITE_EN_8197F)
+#define BIT_SET_PKTBUF_WRITE_EN_8197F(x, v) \
+ (BIT_CLEAR_PKTBUF_WRITE_EN_8197F(x) | BIT_PKTBUF_WRITE_EN_8197F(v))
+
+#define BIT_TXRPTBUF_DBG_8197F BIT(23)
+
+/* 2 REG_NOT_VALID_8197F */
+#define BIT_TXPKTBUF_DBG_V2_8197F BIT(20)
+#define BIT_RXPKTBUF_DBG_8197F BIT(16)
+
+#define BIT_SHIFT_PKTBUF_DBG_ADDR_8197F 0
+#define BIT_MASK_PKTBUF_DBG_ADDR_8197F 0x1fff
+#define BIT_PKTBUF_DBG_ADDR_8197F(x) \
+ (((x) & BIT_MASK_PKTBUF_DBG_ADDR_8197F) \
+ << BIT_SHIFT_PKTBUF_DBG_ADDR_8197F)
+#define BITS_PKTBUF_DBG_ADDR_8197F \
+ (BIT_MASK_PKTBUF_DBG_ADDR_8197F << BIT_SHIFT_PKTBUF_DBG_ADDR_8197F)
+#define BIT_CLEAR_PKTBUF_DBG_ADDR_8197F(x) ((x) & (~BITS_PKTBUF_DBG_ADDR_8197F))
+#define BIT_GET_PKTBUF_DBG_ADDR_8197F(x) \
+ (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8197F) & \
+ BIT_MASK_PKTBUF_DBG_ADDR_8197F)
+#define BIT_SET_PKTBUF_DBG_ADDR_8197F(x, v) \
+ (BIT_CLEAR_PKTBUF_DBG_ADDR_8197F(x) | BIT_PKTBUF_DBG_ADDR_8197F(v))
+
+/* 2 REG_PKTBUF_DBG_DATA_L_8197F */
+
+#define BIT_SHIFT_PKTBUF_DBG_DATA_L_8197F 0
+#define BIT_MASK_PKTBUF_DBG_DATA_L_8197F 0xffffffffL
+#define BIT_PKTBUF_DBG_DATA_L_8197F(x) \
+ (((x) & BIT_MASK_PKTBUF_DBG_DATA_L_8197F) \
+ << BIT_SHIFT_PKTBUF_DBG_DATA_L_8197F)
+#define BITS_PKTBUF_DBG_DATA_L_8197F \
+ (BIT_MASK_PKTBUF_DBG_DATA_L_8197F << BIT_SHIFT_PKTBUF_DBG_DATA_L_8197F)
+#define BIT_CLEAR_PKTBUF_DBG_DATA_L_8197F(x) \
+ ((x) & (~BITS_PKTBUF_DBG_DATA_L_8197F))
+#define BIT_GET_PKTBUF_DBG_DATA_L_8197F(x) \
+ (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8197F) & \
+ BIT_MASK_PKTBUF_DBG_DATA_L_8197F)
+#define BIT_SET_PKTBUF_DBG_DATA_L_8197F(x, v) \
+ (BIT_CLEAR_PKTBUF_DBG_DATA_L_8197F(x) | BIT_PKTBUF_DBG_DATA_L_8197F(v))
+
+/* 2 REG_PKTBUF_DBG_DATA_H_8197F */
+
+#define BIT_SHIFT_PKTBUF_DBG_DATA_H_8197F 0
+#define BIT_MASK_PKTBUF_DBG_DATA_H_8197F 0xffffffffL
+#define BIT_PKTBUF_DBG_DATA_H_8197F(x) \
+ (((x) & BIT_MASK_PKTBUF_DBG_DATA_H_8197F) \
+ << BIT_SHIFT_PKTBUF_DBG_DATA_H_8197F)
+#define BITS_PKTBUF_DBG_DATA_H_8197F \
+ (BIT_MASK_PKTBUF_DBG_DATA_H_8197F << BIT_SHIFT_PKTBUF_DBG_DATA_H_8197F)
+#define BIT_CLEAR_PKTBUF_DBG_DATA_H_8197F(x) \
+ ((x) & (~BITS_PKTBUF_DBG_DATA_H_8197F))
+#define BIT_GET_PKTBUF_DBG_DATA_H_8197F(x) \
+ (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8197F) & \
+ BIT_MASK_PKTBUF_DBG_DATA_H_8197F)
+#define BIT_SET_PKTBUF_DBG_DATA_H_8197F(x, v) \
+ (BIT_CLEAR_PKTBUF_DBG_DATA_H_8197F(x) | BIT_PKTBUF_DBG_DATA_H_8197F(v))
+
+/* 2 REG_CPWM2_8197F */
+
+#define BIT_SHIFT_L0S_TO_RCVY_NUM_8197F 16
+#define BIT_MASK_L0S_TO_RCVY_NUM_8197F 0xff
+#define BIT_L0S_TO_RCVY_NUM_8197F(x) \
+ (((x) & BIT_MASK_L0S_TO_RCVY_NUM_8197F) \
+ << BIT_SHIFT_L0S_TO_RCVY_NUM_8197F)
+#define BITS_L0S_TO_RCVY_NUM_8197F \
+ (BIT_MASK_L0S_TO_RCVY_NUM_8197F << BIT_SHIFT_L0S_TO_RCVY_NUM_8197F)
+#define BIT_CLEAR_L0S_TO_RCVY_NUM_8197F(x) ((x) & (~BITS_L0S_TO_RCVY_NUM_8197F))
+#define BIT_GET_L0S_TO_RCVY_NUM_8197F(x) \
+ (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8197F) & \
+ BIT_MASK_L0S_TO_RCVY_NUM_8197F)
+#define BIT_SET_L0S_TO_RCVY_NUM_8197F(x, v) \
+ (BIT_CLEAR_L0S_TO_RCVY_NUM_8197F(x) | BIT_L0S_TO_RCVY_NUM_8197F(v))
+
+#define BIT_CPWM2_TOGGLING_8197F BIT(15)
+
+#define BIT_SHIFT_CPWM2_MOD_8197F 0
+#define BIT_MASK_CPWM2_MOD_8197F 0x7fff
+#define BIT_CPWM2_MOD_8197F(x) \
+ (((x) & BIT_MASK_CPWM2_MOD_8197F) << BIT_SHIFT_CPWM2_MOD_8197F)
+#define BITS_CPWM2_MOD_8197F \
+ (BIT_MASK_CPWM2_MOD_8197F << BIT_SHIFT_CPWM2_MOD_8197F)
+#define BIT_CLEAR_CPWM2_MOD_8197F(x) ((x) & (~BITS_CPWM2_MOD_8197F))
+#define BIT_GET_CPWM2_MOD_8197F(x) \
+ (((x) >> BIT_SHIFT_CPWM2_MOD_8197F) & BIT_MASK_CPWM2_MOD_8197F)
+#define BIT_SET_CPWM2_MOD_8197F(x, v) \
+ (BIT_CLEAR_CPWM2_MOD_8197F(x) | BIT_CPWM2_MOD_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_TC0_CTRL_8197F */
+#define BIT_TC0INT_EN_8197F BIT(26)
+#define BIT_TC0MODE_8197F BIT(25)
+#define BIT_TC0EN_8197F BIT(24)
+
+#define BIT_SHIFT_TC0DATA_8197F 0
+#define BIT_MASK_TC0DATA_8197F 0xffffff
+#define BIT_TC0DATA_8197F(x) \
+ (((x) & BIT_MASK_TC0DATA_8197F) << BIT_SHIFT_TC0DATA_8197F)
+#define BITS_TC0DATA_8197F (BIT_MASK_TC0DATA_8197F << BIT_SHIFT_TC0DATA_8197F)
+#define BIT_CLEAR_TC0DATA_8197F(x) ((x) & (~BITS_TC0DATA_8197F))
+#define BIT_GET_TC0DATA_8197F(x) \
+ (((x) >> BIT_SHIFT_TC0DATA_8197F) & BIT_MASK_TC0DATA_8197F)
+#define BIT_SET_TC0DATA_8197F(x, v) \
+ (BIT_CLEAR_TC0DATA_8197F(x) | BIT_TC0DATA_8197F(v))
+
+/* 2 REG_TC1_CTRL_8197F */
+#define BIT_TC1INT_EN_8197F BIT(26)
+#define BIT_TC1MODE_8197F BIT(25)
+#define BIT_TC1EN_8197F BIT(24)
+
+#define BIT_SHIFT_TC1DATA_8197F 0
+#define BIT_MASK_TC1DATA_8197F 0xffffff
+#define BIT_TC1DATA_8197F(x) \
+ (((x) & BIT_MASK_TC1DATA_8197F) << BIT_SHIFT_TC1DATA_8197F)
+#define BITS_TC1DATA_8197F (BIT_MASK_TC1DATA_8197F << BIT_SHIFT_TC1DATA_8197F)
+#define BIT_CLEAR_TC1DATA_8197F(x) ((x) & (~BITS_TC1DATA_8197F))
+#define BIT_GET_TC1DATA_8197F(x) \
+ (((x) >> BIT_SHIFT_TC1DATA_8197F) & BIT_MASK_TC1DATA_8197F)
+#define BIT_SET_TC1DATA_8197F(x, v) \
+ (BIT_CLEAR_TC1DATA_8197F(x) | BIT_TC1DATA_8197F(v))
+
+/* 2 REG_TC2_CTRL_8197F */
+#define BIT_TC2INT_EN_8197F BIT(26)
+#define BIT_TC2MODE_8197F BIT(25)
+#define BIT_TC2EN_8197F BIT(24)
+
+#define BIT_SHIFT_TC2DATA_8197F 0
+#define BIT_MASK_TC2DATA_8197F 0xffffff
+#define BIT_TC2DATA_8197F(x) \
+ (((x) & BIT_MASK_TC2DATA_8197F) << BIT_SHIFT_TC2DATA_8197F)
+#define BITS_TC2DATA_8197F (BIT_MASK_TC2DATA_8197F << BIT_SHIFT_TC2DATA_8197F)
+#define BIT_CLEAR_TC2DATA_8197F(x) ((x) & (~BITS_TC2DATA_8197F))
+#define BIT_GET_TC2DATA_8197F(x) \
+ (((x) >> BIT_SHIFT_TC2DATA_8197F) & BIT_MASK_TC2DATA_8197F)
+#define BIT_SET_TC2DATA_8197F(x, v) \
+ (BIT_CLEAR_TC2DATA_8197F(x) | BIT_TC2DATA_8197F(v))
+
+/* 2 REG_TC3_CTRL_8197F */
+#define BIT_TC3INT_EN_8197F BIT(26)
+#define BIT_TC3MODE_8197F BIT(25)
+#define BIT_TC3EN_8197F BIT(24)
+
+#define BIT_SHIFT_TC3DATA_8197F 0
+#define BIT_MASK_TC3DATA_8197F 0xffffff
+#define BIT_TC3DATA_8197F(x) \
+ (((x) & BIT_MASK_TC3DATA_8197F) << BIT_SHIFT_TC3DATA_8197F)
+#define BITS_TC3DATA_8197F (BIT_MASK_TC3DATA_8197F << BIT_SHIFT_TC3DATA_8197F)
+#define BIT_CLEAR_TC3DATA_8197F(x) ((x) & (~BITS_TC3DATA_8197F))
+#define BIT_GET_TC3DATA_8197F(x) \
+ (((x) >> BIT_SHIFT_TC3DATA_8197F) & BIT_MASK_TC3DATA_8197F)
+#define BIT_SET_TC3DATA_8197F(x, v) \
+ (BIT_CLEAR_TC3DATA_8197F(x) | BIT_TC3DATA_8197F(v))
+
+/* 2 REG_TC4_CTRL_8197F */
+#define BIT_TC4INT_EN_8197F BIT(26)
+#define BIT_TC4MODE_8197F BIT(25)
+#define BIT_TC4EN_8197F BIT(24)
+
+#define BIT_SHIFT_TC4DATA_8197F 0
+#define BIT_MASK_TC4DATA_8197F 0xffffff
+#define BIT_TC4DATA_8197F(x) \
+ (((x) & BIT_MASK_TC4DATA_8197F) << BIT_SHIFT_TC4DATA_8197F)
+#define BITS_TC4DATA_8197F (BIT_MASK_TC4DATA_8197F << BIT_SHIFT_TC4DATA_8197F)
+#define BIT_CLEAR_TC4DATA_8197F(x) ((x) & (~BITS_TC4DATA_8197F))
+#define BIT_GET_TC4DATA_8197F(x) \
+ (((x) >> BIT_SHIFT_TC4DATA_8197F) & BIT_MASK_TC4DATA_8197F)
+#define BIT_SET_TC4DATA_8197F(x, v) \
+ (BIT_CLEAR_TC4DATA_8197F(x) | BIT_TC4DATA_8197F(v))
+
+/* 2 REG_TCUNIT_BASE_8197F */
+
+#define BIT_SHIFT_TCUNIT_BASE_8197F 0
+#define BIT_MASK_TCUNIT_BASE_8197F 0x3fff
+#define BIT_TCUNIT_BASE_8197F(x) \
+ (((x) & BIT_MASK_TCUNIT_BASE_8197F) << BIT_SHIFT_TCUNIT_BASE_8197F)
+#define BITS_TCUNIT_BASE_8197F \
+ (BIT_MASK_TCUNIT_BASE_8197F << BIT_SHIFT_TCUNIT_BASE_8197F)
+#define BIT_CLEAR_TCUNIT_BASE_8197F(x) ((x) & (~BITS_TCUNIT_BASE_8197F))
+#define BIT_GET_TCUNIT_BASE_8197F(x) \
+ (((x) >> BIT_SHIFT_TCUNIT_BASE_8197F) & BIT_MASK_TCUNIT_BASE_8197F)
+#define BIT_SET_TCUNIT_BASE_8197F(x, v) \
+ (BIT_CLEAR_TCUNIT_BASE_8197F(x) | BIT_TCUNIT_BASE_8197F(v))
+
+/* 2 REG_TC5_CTRL_8197F */
+#define BIT_TC5INT_EN_8197F BIT(26)
+#define BIT_TC5MODE_8197F BIT(25)
+#define BIT_TC5EN_8197F BIT(24)
+
+#define BIT_SHIFT_TC5DATA_8197F 0
+#define BIT_MASK_TC5DATA_8197F 0xffffff
+#define BIT_TC5DATA_8197F(x) \
+ (((x) & BIT_MASK_TC5DATA_8197F) << BIT_SHIFT_TC5DATA_8197F)
+#define BITS_TC5DATA_8197F (BIT_MASK_TC5DATA_8197F << BIT_SHIFT_TC5DATA_8197F)
+#define BIT_CLEAR_TC5DATA_8197F(x) ((x) & (~BITS_TC5DATA_8197F))
+#define BIT_GET_TC5DATA_8197F(x) \
+ (((x) >> BIT_SHIFT_TC5DATA_8197F) & BIT_MASK_TC5DATA_8197F)
+#define BIT_SET_TC5DATA_8197F(x, v) \
+ (BIT_CLEAR_TC5DATA_8197F(x) | BIT_TC5DATA_8197F(v))
+
+/* 2 REG_TC6_CTRL_8197F */
+#define BIT_TC6INT_EN_8197F BIT(26)
+#define BIT_TC6MODE_8197F BIT(25)
+#define BIT_TC6EN_8197F BIT(24)
+
+#define BIT_SHIFT_TC6DATA_8197F 0
+#define BIT_MASK_TC6DATA_8197F 0xffffff
+#define BIT_TC6DATA_8197F(x) \
+ (((x) & BIT_MASK_TC6DATA_8197F) << BIT_SHIFT_TC6DATA_8197F)
+#define BITS_TC6DATA_8197F (BIT_MASK_TC6DATA_8197F << BIT_SHIFT_TC6DATA_8197F)
+#define BIT_CLEAR_TC6DATA_8197F(x) ((x) & (~BITS_TC6DATA_8197F))
+#define BIT_GET_TC6DATA_8197F(x) \
+ (((x) >> BIT_SHIFT_TC6DATA_8197F) & BIT_MASK_TC6DATA_8197F)
+#define BIT_SET_TC6DATA_8197F(x, v) \
+ (BIT_CLEAR_TC6DATA_8197F(x) | BIT_TC6DATA_8197F(v))
+
+/* 2 REG_MBIST_FAIL_8197F */
+
+#define BIT_SHIFT_8051_MBIST_FAIL_8197F 26
+#define BIT_MASK_8051_MBIST_FAIL_8197F 0x7
+#define BIT_8051_MBIST_FAIL_8197F(x) \
+ (((x) & BIT_MASK_8051_MBIST_FAIL_8197F) \
+ << BIT_SHIFT_8051_MBIST_FAIL_8197F)
+#define BITS_8051_MBIST_FAIL_8197F \
+ (BIT_MASK_8051_MBIST_FAIL_8197F << BIT_SHIFT_8051_MBIST_FAIL_8197F)
+#define BIT_CLEAR_8051_MBIST_FAIL_8197F(x) ((x) & (~BITS_8051_MBIST_FAIL_8197F))
+#define BIT_GET_8051_MBIST_FAIL_8197F(x) \
+ (((x) >> BIT_SHIFT_8051_MBIST_FAIL_8197F) & \
+ BIT_MASK_8051_MBIST_FAIL_8197F)
+#define BIT_SET_8051_MBIST_FAIL_8197F(x, v) \
+ (BIT_CLEAR_8051_MBIST_FAIL_8197F(x) | BIT_8051_MBIST_FAIL_8197F(v))
+
+#define BIT_SHIFT_USB_MBIST_FAIL_8197F 24
+#define BIT_MASK_USB_MBIST_FAIL_8197F 0x3
+#define BIT_USB_MBIST_FAIL_8197F(x) \
+ (((x) & BIT_MASK_USB_MBIST_FAIL_8197F) \
+ << BIT_SHIFT_USB_MBIST_FAIL_8197F)
+#define BITS_USB_MBIST_FAIL_8197F \
+ (BIT_MASK_USB_MBIST_FAIL_8197F << BIT_SHIFT_USB_MBIST_FAIL_8197F)
+#define BIT_CLEAR_USB_MBIST_FAIL_8197F(x) ((x) & (~BITS_USB_MBIST_FAIL_8197F))
+#define BIT_GET_USB_MBIST_FAIL_8197F(x) \
+ (((x) >> BIT_SHIFT_USB_MBIST_FAIL_8197F) & \
+ BIT_MASK_USB_MBIST_FAIL_8197F)
+#define BIT_SET_USB_MBIST_FAIL_8197F(x, v) \
+ (BIT_CLEAR_USB_MBIST_FAIL_8197F(x) | BIT_USB_MBIST_FAIL_8197F(v))
+
+#define BIT_SHIFT_PCIE_MBIST_FAIL_8197F 16
+#define BIT_MASK_PCIE_MBIST_FAIL_8197F 0x3f
+#define BIT_PCIE_MBIST_FAIL_8197F(x) \
+ (((x) & BIT_MASK_PCIE_MBIST_FAIL_8197F) \
+ << BIT_SHIFT_PCIE_MBIST_FAIL_8197F)
+#define BITS_PCIE_MBIST_FAIL_8197F \
+ (BIT_MASK_PCIE_MBIST_FAIL_8197F << BIT_SHIFT_PCIE_MBIST_FAIL_8197F)
+#define BIT_CLEAR_PCIE_MBIST_FAIL_8197F(x) ((x) & (~BITS_PCIE_MBIST_FAIL_8197F))
+#define BIT_GET_PCIE_MBIST_FAIL_8197F(x) \
+ (((x) >> BIT_SHIFT_PCIE_MBIST_FAIL_8197F) & \
+ BIT_MASK_PCIE_MBIST_FAIL_8197F)
+#define BIT_SET_PCIE_MBIST_FAIL_8197F(x, v) \
+ (BIT_CLEAR_PCIE_MBIST_FAIL_8197F(x) | BIT_PCIE_MBIST_FAIL_8197F(v))
+
+#define BIT_SHIFT_MAC_MBIST_FAIL_DRF_8197F 0
+#define BIT_MASK_MAC_MBIST_FAIL_DRF_8197F 0x3ffff
+#define BIT_MAC_MBIST_FAIL_DRF_8197F(x) \
+ (((x) & BIT_MASK_MAC_MBIST_FAIL_DRF_8197F) \
+ << BIT_SHIFT_MAC_MBIST_FAIL_DRF_8197F)
+#define BITS_MAC_MBIST_FAIL_DRF_8197F \
+ (BIT_MASK_MAC_MBIST_FAIL_DRF_8197F \
+ << BIT_SHIFT_MAC_MBIST_FAIL_DRF_8197F)
+#define BIT_CLEAR_MAC_MBIST_FAIL_DRF_8197F(x) \
+ ((x) & (~BITS_MAC_MBIST_FAIL_DRF_8197F))
+#define BIT_GET_MAC_MBIST_FAIL_DRF_8197F(x) \
+ (((x) >> BIT_SHIFT_MAC_MBIST_FAIL_DRF_8197F) & \
+ BIT_MASK_MAC_MBIST_FAIL_DRF_8197F)
+#define BIT_SET_MAC_MBIST_FAIL_DRF_8197F(x, v) \
+ (BIT_CLEAR_MAC_MBIST_FAIL_DRF_8197F(x) | \
+ BIT_MAC_MBIST_FAIL_DRF_8197F(v))
+
+/* 2 REG_MBIST_START_PAUSE_8197F */
+
+#define BIT_SHIFT_8051_MBIST_START_PAUSE_8197F 26
+#define BIT_MASK_8051_MBIST_START_PAUSE_8197F 0x7
+#define BIT_8051_MBIST_START_PAUSE_8197F(x) \
+ (((x) & BIT_MASK_8051_MBIST_START_PAUSE_8197F) \
+ << BIT_SHIFT_8051_MBIST_START_PAUSE_8197F)
+#define BITS_8051_MBIST_START_PAUSE_8197F \
+ (BIT_MASK_8051_MBIST_START_PAUSE_8197F \
+ << BIT_SHIFT_8051_MBIST_START_PAUSE_8197F)
+#define BIT_CLEAR_8051_MBIST_START_PAUSE_8197F(x) \
+ ((x) & (~BITS_8051_MBIST_START_PAUSE_8197F))
+#define BIT_GET_8051_MBIST_START_PAUSE_8197F(x) \
+ (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_8197F) & \
+ BIT_MASK_8051_MBIST_START_PAUSE_8197F)
+#define BIT_SET_8051_MBIST_START_PAUSE_8197F(x, v) \
+ (BIT_CLEAR_8051_MBIST_START_PAUSE_8197F(x) | \
+ BIT_8051_MBIST_START_PAUSE_8197F(v))
+
+#define BIT_SHIFT_USB_MBIST_START_PAUSE_8197F 24
+#define BIT_MASK_USB_MBIST_START_PAUSE_8197F 0x3
+#define BIT_USB_MBIST_START_PAUSE_8197F(x) \
+ (((x) & BIT_MASK_USB_MBIST_START_PAUSE_8197F) \
+ << BIT_SHIFT_USB_MBIST_START_PAUSE_8197F)
+#define BITS_USB_MBIST_START_PAUSE_8197F \
+ (BIT_MASK_USB_MBIST_START_PAUSE_8197F \
+ << BIT_SHIFT_USB_MBIST_START_PAUSE_8197F)
+#define BIT_CLEAR_USB_MBIST_START_PAUSE_8197F(x) \
+ ((x) & (~BITS_USB_MBIST_START_PAUSE_8197F))
+#define BIT_GET_USB_MBIST_START_PAUSE_8197F(x) \
+ (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_8197F) & \
+ BIT_MASK_USB_MBIST_START_PAUSE_8197F)
+#define BIT_SET_USB_MBIST_START_PAUSE_8197F(x, v) \
+ (BIT_CLEAR_USB_MBIST_START_PAUSE_8197F(x) | \
+ BIT_USB_MBIST_START_PAUSE_8197F(v))
+
+#define BIT_SHIFT_PCIE_MBIST_START_PAUSE_8197F 16
+#define BIT_MASK_PCIE_MBIST_START_PAUSE_8197F 0x3f
+#define BIT_PCIE_MBIST_START_PAUSE_8197F(x) \
+ (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_8197F) \
+ << BIT_SHIFT_PCIE_MBIST_START_PAUSE_8197F)
+#define BITS_PCIE_MBIST_START_PAUSE_8197F \
+ (BIT_MASK_PCIE_MBIST_START_PAUSE_8197F \
+ << BIT_SHIFT_PCIE_MBIST_START_PAUSE_8197F)
+#define BIT_CLEAR_PCIE_MBIST_START_PAUSE_8197F(x) \
+ ((x) & (~BITS_PCIE_MBIST_START_PAUSE_8197F))
+#define BIT_GET_PCIE_MBIST_START_PAUSE_8197F(x) \
+ (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_8197F) & \
+ BIT_MASK_PCIE_MBIST_START_PAUSE_8197F)
+#define BIT_SET_PCIE_MBIST_START_PAUSE_8197F(x, v) \
+ (BIT_CLEAR_PCIE_MBIST_START_PAUSE_8197F(x) | \
+ BIT_PCIE_MBIST_START_PAUSE_8197F(v))
+
+#define BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8197F 0
+#define BIT_MASK_MAC_MBIST_START_PAUSE_V1_8197F 0x3ffff
+#define BIT_MAC_MBIST_START_PAUSE_V1_8197F(x) \
+ (((x) & BIT_MASK_MAC_MBIST_START_PAUSE_V1_8197F) \
+ << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8197F)
+#define BITS_MAC_MBIST_START_PAUSE_V1_8197F \
+ (BIT_MASK_MAC_MBIST_START_PAUSE_V1_8197F \
+ << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8197F)
+#define BIT_CLEAR_MAC_MBIST_START_PAUSE_V1_8197F(x) \
+ ((x) & (~BITS_MAC_MBIST_START_PAUSE_V1_8197F))
+#define BIT_GET_MAC_MBIST_START_PAUSE_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8197F) & \
+ BIT_MASK_MAC_MBIST_START_PAUSE_V1_8197F)
+#define BIT_SET_MAC_MBIST_START_PAUSE_V1_8197F(x, v) \
+ (BIT_CLEAR_MAC_MBIST_START_PAUSE_V1_8197F(x) | \
+ BIT_MAC_MBIST_START_PAUSE_V1_8197F(v))
+
+/* 2 REG_MBIST_DONE_8197F */
+
+#define BIT_SHIFT_8051_MBIST_DONE_8197F 26
+#define BIT_MASK_8051_MBIST_DONE_8197F 0x7
+#define BIT_8051_MBIST_DONE_8197F(x) \
+ (((x) & BIT_MASK_8051_MBIST_DONE_8197F) \
+ << BIT_SHIFT_8051_MBIST_DONE_8197F)
+#define BITS_8051_MBIST_DONE_8197F \
+ (BIT_MASK_8051_MBIST_DONE_8197F << BIT_SHIFT_8051_MBIST_DONE_8197F)
+#define BIT_CLEAR_8051_MBIST_DONE_8197F(x) ((x) & (~BITS_8051_MBIST_DONE_8197F))
+#define BIT_GET_8051_MBIST_DONE_8197F(x) \
+ (((x) >> BIT_SHIFT_8051_MBIST_DONE_8197F) & \
+ BIT_MASK_8051_MBIST_DONE_8197F)
+#define BIT_SET_8051_MBIST_DONE_8197F(x, v) \
+ (BIT_CLEAR_8051_MBIST_DONE_8197F(x) | BIT_8051_MBIST_DONE_8197F(v))
+
+#define BIT_SHIFT_USB_MBIST_DONE_8197F 24
+#define BIT_MASK_USB_MBIST_DONE_8197F 0x3
+#define BIT_USB_MBIST_DONE_8197F(x) \
+ (((x) & BIT_MASK_USB_MBIST_DONE_8197F) \
+ << BIT_SHIFT_USB_MBIST_DONE_8197F)
+#define BITS_USB_MBIST_DONE_8197F \
+ (BIT_MASK_USB_MBIST_DONE_8197F << BIT_SHIFT_USB_MBIST_DONE_8197F)
+#define BIT_CLEAR_USB_MBIST_DONE_8197F(x) ((x) & (~BITS_USB_MBIST_DONE_8197F))
+#define BIT_GET_USB_MBIST_DONE_8197F(x) \
+ (((x) >> BIT_SHIFT_USB_MBIST_DONE_8197F) & \
+ BIT_MASK_USB_MBIST_DONE_8197F)
+#define BIT_SET_USB_MBIST_DONE_8197F(x, v) \
+ (BIT_CLEAR_USB_MBIST_DONE_8197F(x) | BIT_USB_MBIST_DONE_8197F(v))
+
+#define BIT_SHIFT_PCIE_MBIST_DONE_8197F 16
+#define BIT_MASK_PCIE_MBIST_DONE_8197F 0x3f
+#define BIT_PCIE_MBIST_DONE_8197F(x) \
+ (((x) & BIT_MASK_PCIE_MBIST_DONE_8197F) \
+ << BIT_SHIFT_PCIE_MBIST_DONE_8197F)
+#define BITS_PCIE_MBIST_DONE_8197F \
+ (BIT_MASK_PCIE_MBIST_DONE_8197F << BIT_SHIFT_PCIE_MBIST_DONE_8197F)
+#define BIT_CLEAR_PCIE_MBIST_DONE_8197F(x) ((x) & (~BITS_PCIE_MBIST_DONE_8197F))
+#define BIT_GET_PCIE_MBIST_DONE_8197F(x) \
+ (((x) >> BIT_SHIFT_PCIE_MBIST_DONE_8197F) & \
+ BIT_MASK_PCIE_MBIST_DONE_8197F)
+#define BIT_SET_PCIE_MBIST_DONE_8197F(x, v) \
+ (BIT_CLEAR_PCIE_MBIST_DONE_8197F(x) | BIT_PCIE_MBIST_DONE_8197F(v))
+
+#define BIT_SHIFT_MAC_MBIST_DONE_V1_8197F 0
+#define BIT_MASK_MAC_MBIST_DONE_V1_8197F 0x3ffff
+#define BIT_MAC_MBIST_DONE_V1_8197F(x) \
+ (((x) & BIT_MASK_MAC_MBIST_DONE_V1_8197F) \
+ << BIT_SHIFT_MAC_MBIST_DONE_V1_8197F)
+#define BITS_MAC_MBIST_DONE_V1_8197F \
+ (BIT_MASK_MAC_MBIST_DONE_V1_8197F << BIT_SHIFT_MAC_MBIST_DONE_V1_8197F)
+#define BIT_CLEAR_MAC_MBIST_DONE_V1_8197F(x) \
+ ((x) & (~BITS_MAC_MBIST_DONE_V1_8197F))
+#define BIT_GET_MAC_MBIST_DONE_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_MAC_MBIST_DONE_V1_8197F) & \
+ BIT_MASK_MAC_MBIST_DONE_V1_8197F)
+#define BIT_SET_MAC_MBIST_DONE_V1_8197F(x, v) \
+ (BIT_CLEAR_MAC_MBIST_DONE_V1_8197F(x) | BIT_MAC_MBIST_DONE_V1_8197F(v))
+
+/* 2 REG_MBIST_FAIL_NRML_8197F */
+
+#define BIT_SHIFT_MBIST_FAIL_NRML_V1_8197F 0
+#define BIT_MASK_MBIST_FAIL_NRML_V1_8197F 0x3ffff
+#define BIT_MBIST_FAIL_NRML_V1_8197F(x) \
+ (((x) & BIT_MASK_MBIST_FAIL_NRML_V1_8197F) \
+ << BIT_SHIFT_MBIST_FAIL_NRML_V1_8197F)
+#define BITS_MBIST_FAIL_NRML_V1_8197F \
+ (BIT_MASK_MBIST_FAIL_NRML_V1_8197F \
+ << BIT_SHIFT_MBIST_FAIL_NRML_V1_8197F)
+#define BIT_CLEAR_MBIST_FAIL_NRML_V1_8197F(x) \
+ ((x) & (~BITS_MBIST_FAIL_NRML_V1_8197F))
+#define BIT_GET_MBIST_FAIL_NRML_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_MBIST_FAIL_NRML_V1_8197F) & \
+ BIT_MASK_MBIST_FAIL_NRML_V1_8197F)
+#define BIT_SET_MBIST_FAIL_NRML_V1_8197F(x, v) \
+ (BIT_CLEAR_MBIST_FAIL_NRML_V1_8197F(x) | \
+ BIT_MBIST_FAIL_NRML_V1_8197F(v))
+
+/* 2 REG_AES_DECRPT_DATA_8197F */
+
+#define BIT_SHIFT_IPS_CFG_ADDR_8197F 0
+#define BIT_MASK_IPS_CFG_ADDR_8197F 0xff
+#define BIT_IPS_CFG_ADDR_8197F(x) \
+ (((x) & BIT_MASK_IPS_CFG_ADDR_8197F) << BIT_SHIFT_IPS_CFG_ADDR_8197F)
+#define BITS_IPS_CFG_ADDR_8197F \
+ (BIT_MASK_IPS_CFG_ADDR_8197F << BIT_SHIFT_IPS_CFG_ADDR_8197F)
+#define BIT_CLEAR_IPS_CFG_ADDR_8197F(x) ((x) & (~BITS_IPS_CFG_ADDR_8197F))
+#define BIT_GET_IPS_CFG_ADDR_8197F(x) \
+ (((x) >> BIT_SHIFT_IPS_CFG_ADDR_8197F) & BIT_MASK_IPS_CFG_ADDR_8197F)
+#define BIT_SET_IPS_CFG_ADDR_8197F(x, v) \
+ (BIT_CLEAR_IPS_CFG_ADDR_8197F(x) | BIT_IPS_CFG_ADDR_8197F(v))
+
+/* 2 REG_AES_DECRPT_CFG_8197F */
+
+#define BIT_SHIFT_IPS_CFG_DATA_8197F 0
+#define BIT_MASK_IPS_CFG_DATA_8197F 0xffffffffL
+#define BIT_IPS_CFG_DATA_8197F(x) \
+ (((x) & BIT_MASK_IPS_CFG_DATA_8197F) << BIT_SHIFT_IPS_CFG_DATA_8197F)
+#define BITS_IPS_CFG_DATA_8197F \
+ (BIT_MASK_IPS_CFG_DATA_8197F << BIT_SHIFT_IPS_CFG_DATA_8197F)
+#define BIT_CLEAR_IPS_CFG_DATA_8197F(x) ((x) & (~BITS_IPS_CFG_DATA_8197F))
+#define BIT_GET_IPS_CFG_DATA_8197F(x) \
+ (((x) >> BIT_SHIFT_IPS_CFG_DATA_8197F) & BIT_MASK_IPS_CFG_DATA_8197F)
+#define BIT_SET_IPS_CFG_DATA_8197F(x, v) \
+ (BIT_CLEAR_IPS_CFG_DATA_8197F(x) | BIT_IPS_CFG_DATA_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_MACCLKFRQ_8197F */
+
+#define BIT_SHIFT_MACCLK_FREQ_LOW32_8197F 0
+#define BIT_MASK_MACCLK_FREQ_LOW32_8197F 0xffffffffL
+#define BIT_MACCLK_FREQ_LOW32_8197F(x) \
+ (((x) & BIT_MASK_MACCLK_FREQ_LOW32_8197F) \
+ << BIT_SHIFT_MACCLK_FREQ_LOW32_8197F)
+#define BITS_MACCLK_FREQ_LOW32_8197F \
+ (BIT_MASK_MACCLK_FREQ_LOW32_8197F << BIT_SHIFT_MACCLK_FREQ_LOW32_8197F)
+#define BIT_CLEAR_MACCLK_FREQ_LOW32_8197F(x) \
+ ((x) & (~BITS_MACCLK_FREQ_LOW32_8197F))
+#define BIT_GET_MACCLK_FREQ_LOW32_8197F(x) \
+ (((x) >> BIT_SHIFT_MACCLK_FREQ_LOW32_8197F) & \
+ BIT_MASK_MACCLK_FREQ_LOW32_8197F)
+#define BIT_SET_MACCLK_FREQ_LOW32_8197F(x, v) \
+ (BIT_CLEAR_MACCLK_FREQ_LOW32_8197F(x) | BIT_MACCLK_FREQ_LOW32_8197F(v))
+
+/* 2 REG_TMETER_8197F */
+
+#define BIT_SHIFT_MACCLK_FREQ_HIGH10_8197F 0
+#define BIT_MASK_MACCLK_FREQ_HIGH10_8197F 0x3ff
+#define BIT_MACCLK_FREQ_HIGH10_8197F(x) \
+ (((x) & BIT_MASK_MACCLK_FREQ_HIGH10_8197F) \
+ << BIT_SHIFT_MACCLK_FREQ_HIGH10_8197F)
+#define BITS_MACCLK_FREQ_HIGH10_8197F \
+ (BIT_MASK_MACCLK_FREQ_HIGH10_8197F \
+ << BIT_SHIFT_MACCLK_FREQ_HIGH10_8197F)
+#define BIT_CLEAR_MACCLK_FREQ_HIGH10_8197F(x) \
+ ((x) & (~BITS_MACCLK_FREQ_HIGH10_8197F))
+#define BIT_GET_MACCLK_FREQ_HIGH10_8197F(x) \
+ (((x) >> BIT_SHIFT_MACCLK_FREQ_HIGH10_8197F) & \
+ BIT_MASK_MACCLK_FREQ_HIGH10_8197F)
+#define BIT_SET_MACCLK_FREQ_HIGH10_8197F(x, v) \
+ (BIT_CLEAR_MACCLK_FREQ_HIGH10_8197F(x) | \
+ BIT_MACCLK_FREQ_HIGH10_8197F(v))
+
+/* 2 REG_OSC_32K_CTRL_8197F */
+#define BIT_32K_CLK_OUT_RDY_8197F BIT(12)
+
+#define BIT_SHIFT_MONITOR_CYCLE_LOG2_8197F 8
+#define BIT_MASK_MONITOR_CYCLE_LOG2_8197F 0xf
+#define BIT_MONITOR_CYCLE_LOG2_8197F(x) \
+ (((x) & BIT_MASK_MONITOR_CYCLE_LOG2_8197F) \
+ << BIT_SHIFT_MONITOR_CYCLE_LOG2_8197F)
+#define BITS_MONITOR_CYCLE_LOG2_8197F \
+ (BIT_MASK_MONITOR_CYCLE_LOG2_8197F \
+ << BIT_SHIFT_MONITOR_CYCLE_LOG2_8197F)
+#define BIT_CLEAR_MONITOR_CYCLE_LOG2_8197F(x) \
+ ((x) & (~BITS_MONITOR_CYCLE_LOG2_8197F))
+#define BIT_GET_MONITOR_CYCLE_LOG2_8197F(x) \
+ (((x) >> BIT_SHIFT_MONITOR_CYCLE_LOG2_8197F) & \
+ BIT_MASK_MONITOR_CYCLE_LOG2_8197F)
+#define BIT_SET_MONITOR_CYCLE_LOG2_8197F(x, v) \
+ (BIT_CLEAR_MONITOR_CYCLE_LOG2_8197F(x) | \
+ BIT_MONITOR_CYCLE_LOG2_8197F(v))
+
+/* 2 REG_32K_CAL_REG1_8197F */
+
+#define BIT_SHIFT_FREQVALUE_UNREGCLK_8197F 8
+#define BIT_MASK_FREQVALUE_UNREGCLK_8197F 0xffffff
+#define BIT_FREQVALUE_UNREGCLK_8197F(x) \
+ (((x) & BIT_MASK_FREQVALUE_UNREGCLK_8197F) \
+ << BIT_SHIFT_FREQVALUE_UNREGCLK_8197F)
+#define BITS_FREQVALUE_UNREGCLK_8197F \
+ (BIT_MASK_FREQVALUE_UNREGCLK_8197F \
+ << BIT_SHIFT_FREQVALUE_UNREGCLK_8197F)
+#define BIT_CLEAR_FREQVALUE_UNREGCLK_8197F(x) \
+ ((x) & (~BITS_FREQVALUE_UNREGCLK_8197F))
+#define BIT_GET_FREQVALUE_UNREGCLK_8197F(x) \
+ (((x) >> BIT_SHIFT_FREQVALUE_UNREGCLK_8197F) & \
+ BIT_MASK_FREQVALUE_UNREGCLK_8197F)
+#define BIT_SET_FREQVALUE_UNREGCLK_8197F(x, v) \
+ (BIT_CLEAR_FREQVALUE_UNREGCLK_8197F(x) | \
+ BIT_FREQVALUE_UNREGCLK_8197F(v))
+
+#define BIT_CAL32K_DBGMOD_8197F BIT(7)
+
+#define BIT_SHIFT_NCO_THRS_8197F 0
+#define BIT_MASK_NCO_THRS_8197F 0x7f
+#define BIT_NCO_THRS_8197F(x) \
+ (((x) & BIT_MASK_NCO_THRS_8197F) << BIT_SHIFT_NCO_THRS_8197F)
+#define BITS_NCO_THRS_8197F \
+ (BIT_MASK_NCO_THRS_8197F << BIT_SHIFT_NCO_THRS_8197F)
+#define BIT_CLEAR_NCO_THRS_8197F(x) ((x) & (~BITS_NCO_THRS_8197F))
+#define BIT_GET_NCO_THRS_8197F(x) \
+ (((x) >> BIT_SHIFT_NCO_THRS_8197F) & BIT_MASK_NCO_THRS_8197F)
+#define BIT_SET_NCO_THRS_8197F(x, v) \
+ (BIT_CLEAR_NCO_THRS_8197F(x) | BIT_NCO_THRS_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_C2HEVT_8197F */
+
+#define BIT_SHIFT_C2HEVT_MSG_8197F 0
+#define BIT_MASK_C2HEVT_MSG_8197F 0xffffffffffffffffffffffffffffffffL
+#define BIT_C2HEVT_MSG_8197F(x) \
+ (((x) & BIT_MASK_C2HEVT_MSG_8197F) << BIT_SHIFT_C2HEVT_MSG_8197F)
+#define BITS_C2HEVT_MSG_8197F \
+ (BIT_MASK_C2HEVT_MSG_8197F << BIT_SHIFT_C2HEVT_MSG_8197F)
+#define BIT_CLEAR_C2HEVT_MSG_8197F(x) ((x) & (~BITS_C2HEVT_MSG_8197F))
+#define BIT_GET_C2HEVT_MSG_8197F(x) \
+ (((x) >> BIT_SHIFT_C2HEVT_MSG_8197F) & BIT_MASK_C2HEVT_MSG_8197F)
+#define BIT_SET_C2HEVT_MSG_8197F(x, v) \
+ (BIT_CLEAR_C2HEVT_MSG_8197F(x) | BIT_C2HEVT_MSG_8197F(v))
+
+/* 2 REG_SW_DEFINED_PAGE1_8197F */
+
+#define BIT_SHIFT_SW_DEFINED_PAGE1_8197F 0
+#define BIT_MASK_SW_DEFINED_PAGE1_8197F 0xffffffffffffffffL
+#define BIT_SW_DEFINED_PAGE1_8197F(x) \
+ (((x) & BIT_MASK_SW_DEFINED_PAGE1_8197F) \
+ << BIT_SHIFT_SW_DEFINED_PAGE1_8197F)
+#define BITS_SW_DEFINED_PAGE1_8197F \
+ (BIT_MASK_SW_DEFINED_PAGE1_8197F << BIT_SHIFT_SW_DEFINED_PAGE1_8197F)
+#define BIT_CLEAR_SW_DEFINED_PAGE1_8197F(x) \
+ ((x) & (~BITS_SW_DEFINED_PAGE1_8197F))
+#define BIT_GET_SW_DEFINED_PAGE1_8197F(x) \
+ (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_8197F) & \
+ BIT_MASK_SW_DEFINED_PAGE1_8197F)
+#define BIT_SET_SW_DEFINED_PAGE1_8197F(x, v) \
+ (BIT_CLEAR_SW_DEFINED_PAGE1_8197F(x) | BIT_SW_DEFINED_PAGE1_8197F(v))
+
+/* 2 REG_MCUTST_I_8197F */
+
+#define BIT_SHIFT_MCUDMSG_I_8197F 0
+#define BIT_MASK_MCUDMSG_I_8197F 0xffffffffL
+#define BIT_MCUDMSG_I_8197F(x) \
+ (((x) & BIT_MASK_MCUDMSG_I_8197F) << BIT_SHIFT_MCUDMSG_I_8197F)
+#define BITS_MCUDMSG_I_8197F \
+ (BIT_MASK_MCUDMSG_I_8197F << BIT_SHIFT_MCUDMSG_I_8197F)
+#define BIT_CLEAR_MCUDMSG_I_8197F(x) ((x) & (~BITS_MCUDMSG_I_8197F))
+#define BIT_GET_MCUDMSG_I_8197F(x) \
+ (((x) >> BIT_SHIFT_MCUDMSG_I_8197F) & BIT_MASK_MCUDMSG_I_8197F)
+#define BIT_SET_MCUDMSG_I_8197F(x, v) \
+ (BIT_CLEAR_MCUDMSG_I_8197F(x) | BIT_MCUDMSG_I_8197F(v))
+
+/* 2 REG_MCUTST_II_8197F */
+
+#define BIT_SHIFT_MCUDMSG_II_8197F 0
+#define BIT_MASK_MCUDMSG_II_8197F 0xffffffffL
+#define BIT_MCUDMSG_II_8197F(x) \
+ (((x) & BIT_MASK_MCUDMSG_II_8197F) << BIT_SHIFT_MCUDMSG_II_8197F)
+#define BITS_MCUDMSG_II_8197F \
+ (BIT_MASK_MCUDMSG_II_8197F << BIT_SHIFT_MCUDMSG_II_8197F)
+#define BIT_CLEAR_MCUDMSG_II_8197F(x) ((x) & (~BITS_MCUDMSG_II_8197F))
+#define BIT_GET_MCUDMSG_II_8197F(x) \
+ (((x) >> BIT_SHIFT_MCUDMSG_II_8197F) & BIT_MASK_MCUDMSG_II_8197F)
+#define BIT_SET_MCUDMSG_II_8197F(x, v) \
+ (BIT_CLEAR_MCUDMSG_II_8197F(x) | BIT_MCUDMSG_II_8197F(v))
+
+/* 2 REG_FMETHR_8197F */
+#define BIT_FMSG_INT_8197F BIT(31)
+
+#define BIT_SHIFT_FW_MSG_8197F 0
+#define BIT_MASK_FW_MSG_8197F 0xffffffffL
+#define BIT_FW_MSG_8197F(x) \
+ (((x) & BIT_MASK_FW_MSG_8197F) << BIT_SHIFT_FW_MSG_8197F)
+#define BITS_FW_MSG_8197F (BIT_MASK_FW_MSG_8197F << BIT_SHIFT_FW_MSG_8197F)
+#define BIT_CLEAR_FW_MSG_8197F(x) ((x) & (~BITS_FW_MSG_8197F))
+#define BIT_GET_FW_MSG_8197F(x) \
+ (((x) >> BIT_SHIFT_FW_MSG_8197F) & BIT_MASK_FW_MSG_8197F)
+#define BIT_SET_FW_MSG_8197F(x, v) \
+ (BIT_CLEAR_FW_MSG_8197F(x) | BIT_FW_MSG_8197F(v))
+
+/* 2 REG_HMETFR_8197F */
+
+#define BIT_SHIFT_HRCV_MSG_8197F 24
+#define BIT_MASK_HRCV_MSG_8197F 0xff
+#define BIT_HRCV_MSG_8197F(x) \
+ (((x) & BIT_MASK_HRCV_MSG_8197F) << BIT_SHIFT_HRCV_MSG_8197F)
+#define BITS_HRCV_MSG_8197F \
+ (BIT_MASK_HRCV_MSG_8197F << BIT_SHIFT_HRCV_MSG_8197F)
+#define BIT_CLEAR_HRCV_MSG_8197F(x) ((x) & (~BITS_HRCV_MSG_8197F))
+#define BIT_GET_HRCV_MSG_8197F(x) \
+ (((x) >> BIT_SHIFT_HRCV_MSG_8197F) & BIT_MASK_HRCV_MSG_8197F)
+#define BIT_SET_HRCV_MSG_8197F(x, v) \
+ (BIT_CLEAR_HRCV_MSG_8197F(x) | BIT_HRCV_MSG_8197F(v))
+
+#define BIT_INT_BOX3_8197F BIT(3)
+#define BIT_INT_BOX2_8197F BIT(2)
+#define BIT_INT_BOX1_8197F BIT(1)
+#define BIT_INT_BOX0_8197F BIT(0)
+
+/* 2 REG_HMEBOX0_8197F */
+
+#define BIT_SHIFT_HOST_MSG_0_8197F 0
+#define BIT_MASK_HOST_MSG_0_8197F 0xffffffffL
+#define BIT_HOST_MSG_0_8197F(x) \
+ (((x) & BIT_MASK_HOST_MSG_0_8197F) << BIT_SHIFT_HOST_MSG_0_8197F)
+#define BITS_HOST_MSG_0_8197F \
+ (BIT_MASK_HOST_MSG_0_8197F << BIT_SHIFT_HOST_MSG_0_8197F)
+#define BIT_CLEAR_HOST_MSG_0_8197F(x) ((x) & (~BITS_HOST_MSG_0_8197F))
+#define BIT_GET_HOST_MSG_0_8197F(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_0_8197F) & BIT_MASK_HOST_MSG_0_8197F)
+#define BIT_SET_HOST_MSG_0_8197F(x, v) \
+ (BIT_CLEAR_HOST_MSG_0_8197F(x) | BIT_HOST_MSG_0_8197F(v))
+
+/* 2 REG_HMEBOX1_8197F */
+
+#define BIT_SHIFT_HOST_MSG_1_8197F 0
+#define BIT_MASK_HOST_MSG_1_8197F 0xffffffffL
+#define BIT_HOST_MSG_1_8197F(x) \
+ (((x) & BIT_MASK_HOST_MSG_1_8197F) << BIT_SHIFT_HOST_MSG_1_8197F)
+#define BITS_HOST_MSG_1_8197F \
+ (BIT_MASK_HOST_MSG_1_8197F << BIT_SHIFT_HOST_MSG_1_8197F)
+#define BIT_CLEAR_HOST_MSG_1_8197F(x) ((x) & (~BITS_HOST_MSG_1_8197F))
+#define BIT_GET_HOST_MSG_1_8197F(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_1_8197F) & BIT_MASK_HOST_MSG_1_8197F)
+#define BIT_SET_HOST_MSG_1_8197F(x, v) \
+ (BIT_CLEAR_HOST_MSG_1_8197F(x) | BIT_HOST_MSG_1_8197F(v))
+
+/* 2 REG_HMEBOX2_8197F */
+
+#define BIT_SHIFT_HOST_MSG_2_8197F 0
+#define BIT_MASK_HOST_MSG_2_8197F 0xffffffffL
+#define BIT_HOST_MSG_2_8197F(x) \
+ (((x) & BIT_MASK_HOST_MSG_2_8197F) << BIT_SHIFT_HOST_MSG_2_8197F)
+#define BITS_HOST_MSG_2_8197F \
+ (BIT_MASK_HOST_MSG_2_8197F << BIT_SHIFT_HOST_MSG_2_8197F)
+#define BIT_CLEAR_HOST_MSG_2_8197F(x) ((x) & (~BITS_HOST_MSG_2_8197F))
+#define BIT_GET_HOST_MSG_2_8197F(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_2_8197F) & BIT_MASK_HOST_MSG_2_8197F)
+#define BIT_SET_HOST_MSG_2_8197F(x, v) \
+ (BIT_CLEAR_HOST_MSG_2_8197F(x) | BIT_HOST_MSG_2_8197F(v))
+
+/* 2 REG_HMEBOX3_8197F */
+
+#define BIT_SHIFT_HOST_MSG_3_8197F 0
+#define BIT_MASK_HOST_MSG_3_8197F 0xffffffffL
+#define BIT_HOST_MSG_3_8197F(x) \
+ (((x) & BIT_MASK_HOST_MSG_3_8197F) << BIT_SHIFT_HOST_MSG_3_8197F)
+#define BITS_HOST_MSG_3_8197F \
+ (BIT_MASK_HOST_MSG_3_8197F << BIT_SHIFT_HOST_MSG_3_8197F)
+#define BIT_CLEAR_HOST_MSG_3_8197F(x) ((x) & (~BITS_HOST_MSG_3_8197F))
+#define BIT_GET_HOST_MSG_3_8197F(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_3_8197F) & BIT_MASK_HOST_MSG_3_8197F)
+#define BIT_SET_HOST_MSG_3_8197F(x, v) \
+ (BIT_CLEAR_HOST_MSG_3_8197F(x) | BIT_HOST_MSG_3_8197F(v))
+
+/* 2 REG_LLT_INIT_8197F */
+
+#define BIT_SHIFT_LLTE_RWM_8197F 30
+#define BIT_MASK_LLTE_RWM_8197F 0x3
+#define BIT_LLTE_RWM_8197F(x) \
+ (((x) & BIT_MASK_LLTE_RWM_8197F) << BIT_SHIFT_LLTE_RWM_8197F)
+#define BITS_LLTE_RWM_8197F \
+ (BIT_MASK_LLTE_RWM_8197F << BIT_SHIFT_LLTE_RWM_8197F)
+#define BIT_CLEAR_LLTE_RWM_8197F(x) ((x) & (~BITS_LLTE_RWM_8197F))
+#define BIT_GET_LLTE_RWM_8197F(x) \
+ (((x) >> BIT_SHIFT_LLTE_RWM_8197F) & BIT_MASK_LLTE_RWM_8197F)
+#define BIT_SET_LLTE_RWM_8197F(x, v) \
+ (BIT_CLEAR_LLTE_RWM_8197F(x) | BIT_LLTE_RWM_8197F(v))
+
+#define BIT_SHIFT_LLTINI_PDATA_V1_8197F 16
+#define BIT_MASK_LLTINI_PDATA_V1_8197F 0xfff
+#define BIT_LLTINI_PDATA_V1_8197F(x) \
+ (((x) & BIT_MASK_LLTINI_PDATA_V1_8197F) \
+ << BIT_SHIFT_LLTINI_PDATA_V1_8197F)
+#define BITS_LLTINI_PDATA_V1_8197F \
+ (BIT_MASK_LLTINI_PDATA_V1_8197F << BIT_SHIFT_LLTINI_PDATA_V1_8197F)
+#define BIT_CLEAR_LLTINI_PDATA_V1_8197F(x) ((x) & (~BITS_LLTINI_PDATA_V1_8197F))
+#define BIT_GET_LLTINI_PDATA_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_LLTINI_PDATA_V1_8197F) & \
+ BIT_MASK_LLTINI_PDATA_V1_8197F)
+#define BIT_SET_LLTINI_PDATA_V1_8197F(x, v) \
+ (BIT_CLEAR_LLTINI_PDATA_V1_8197F(x) | BIT_LLTINI_PDATA_V1_8197F(v))
+
+#define BIT_SHIFT_LLTINI_HDATA_V1_8197F 0
+#define BIT_MASK_LLTINI_HDATA_V1_8197F 0xfff
+#define BIT_LLTINI_HDATA_V1_8197F(x) \
+ (((x) & BIT_MASK_LLTINI_HDATA_V1_8197F) \
+ << BIT_SHIFT_LLTINI_HDATA_V1_8197F)
+#define BITS_LLTINI_HDATA_V1_8197F \
+ (BIT_MASK_LLTINI_HDATA_V1_8197F << BIT_SHIFT_LLTINI_HDATA_V1_8197F)
+#define BIT_CLEAR_LLTINI_HDATA_V1_8197F(x) ((x) & (~BITS_LLTINI_HDATA_V1_8197F))
+#define BIT_GET_LLTINI_HDATA_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_LLTINI_HDATA_V1_8197F) & \
+ BIT_MASK_LLTINI_HDATA_V1_8197F)
+#define BIT_SET_LLTINI_HDATA_V1_8197F(x, v) \
+ (BIT_CLEAR_LLTINI_HDATA_V1_8197F(x) | BIT_LLTINI_HDATA_V1_8197F(v))
+
+/* 2 REG_LLT_INIT_ADDR_8197F */
+
+#define BIT_SHIFT_LLTINI_ADDR_V1_8197F 0
+#define BIT_MASK_LLTINI_ADDR_V1_8197F 0xfff
+#define BIT_LLTINI_ADDR_V1_8197F(x) \
+ (((x) & BIT_MASK_LLTINI_ADDR_V1_8197F) \
+ << BIT_SHIFT_LLTINI_ADDR_V1_8197F)
+#define BITS_LLTINI_ADDR_V1_8197F \
+ (BIT_MASK_LLTINI_ADDR_V1_8197F << BIT_SHIFT_LLTINI_ADDR_V1_8197F)
+#define BIT_CLEAR_LLTINI_ADDR_V1_8197F(x) ((x) & (~BITS_LLTINI_ADDR_V1_8197F))
+#define BIT_GET_LLTINI_ADDR_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_LLTINI_ADDR_V1_8197F) & \
+ BIT_MASK_LLTINI_ADDR_V1_8197F)
+#define BIT_SET_LLTINI_ADDR_V1_8197F(x, v) \
+ (BIT_CLEAR_LLTINI_ADDR_V1_8197F(x) | BIT_LLTINI_ADDR_V1_8197F(v))
+
+/* 2 REG_BB_ACCESS_CTRL_8197F */
+
+#define BIT_SHIFT_BB_WRITE_READ_8197F 30
+#define BIT_MASK_BB_WRITE_READ_8197F 0x3
+#define BIT_BB_WRITE_READ_8197F(x) \
+ (((x) & BIT_MASK_BB_WRITE_READ_8197F) << BIT_SHIFT_BB_WRITE_READ_8197F)
+#define BITS_BB_WRITE_READ_8197F \
+ (BIT_MASK_BB_WRITE_READ_8197F << BIT_SHIFT_BB_WRITE_READ_8197F)
+#define BIT_CLEAR_BB_WRITE_READ_8197F(x) ((x) & (~BITS_BB_WRITE_READ_8197F))
+#define BIT_GET_BB_WRITE_READ_8197F(x) \
+ (((x) >> BIT_SHIFT_BB_WRITE_READ_8197F) & BIT_MASK_BB_WRITE_READ_8197F)
+#define BIT_SET_BB_WRITE_READ_8197F(x, v) \
+ (BIT_CLEAR_BB_WRITE_READ_8197F(x) | BIT_BB_WRITE_READ_8197F(v))
+
+#define BIT_SHIFT_BB_WRITE_EN_V1_8197F 16
+#define BIT_MASK_BB_WRITE_EN_V1_8197F 0xf
+#define BIT_BB_WRITE_EN_V1_8197F(x) \
+ (((x) & BIT_MASK_BB_WRITE_EN_V1_8197F) \
+ << BIT_SHIFT_BB_WRITE_EN_V1_8197F)
+#define BITS_BB_WRITE_EN_V1_8197F \
+ (BIT_MASK_BB_WRITE_EN_V1_8197F << BIT_SHIFT_BB_WRITE_EN_V1_8197F)
+#define BIT_CLEAR_BB_WRITE_EN_V1_8197F(x) ((x) & (~BITS_BB_WRITE_EN_V1_8197F))
+#define BIT_GET_BB_WRITE_EN_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_BB_WRITE_EN_V1_8197F) & \
+ BIT_MASK_BB_WRITE_EN_V1_8197F)
+#define BIT_SET_BB_WRITE_EN_V1_8197F(x, v) \
+ (BIT_CLEAR_BB_WRITE_EN_V1_8197F(x) | BIT_BB_WRITE_EN_V1_8197F(v))
+
+#define BIT_SHIFT_BB_ADDR_V1_8197F 2
+#define BIT_MASK_BB_ADDR_V1_8197F 0xfff
+#define BIT_BB_ADDR_V1_8197F(x) \
+ (((x) & BIT_MASK_BB_ADDR_V1_8197F) << BIT_SHIFT_BB_ADDR_V1_8197F)
+#define BITS_BB_ADDR_V1_8197F \
+ (BIT_MASK_BB_ADDR_V1_8197F << BIT_SHIFT_BB_ADDR_V1_8197F)
+#define BIT_CLEAR_BB_ADDR_V1_8197F(x) ((x) & (~BITS_BB_ADDR_V1_8197F))
+#define BIT_GET_BB_ADDR_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_BB_ADDR_V1_8197F) & BIT_MASK_BB_ADDR_V1_8197F)
+#define BIT_SET_BB_ADDR_V1_8197F(x, v) \
+ (BIT_CLEAR_BB_ADDR_V1_8197F(x) | BIT_BB_ADDR_V1_8197F(v))
+
+#define BIT_BB_ERRACC_8197F BIT(0)
+
+/* 2 REG_BB_ACCESS_DATA_8197F */
+
+#define BIT_SHIFT_BB_DATA_8197F 0
+#define BIT_MASK_BB_DATA_8197F 0xffffffffL
+#define BIT_BB_DATA_8197F(x) \
+ (((x) & BIT_MASK_BB_DATA_8197F) << BIT_SHIFT_BB_DATA_8197F)
+#define BITS_BB_DATA_8197F (BIT_MASK_BB_DATA_8197F << BIT_SHIFT_BB_DATA_8197F)
+#define BIT_CLEAR_BB_DATA_8197F(x) ((x) & (~BITS_BB_DATA_8197F))
+#define BIT_GET_BB_DATA_8197F(x) \
+ (((x) >> BIT_SHIFT_BB_DATA_8197F) & BIT_MASK_BB_DATA_8197F)
+#define BIT_SET_BB_DATA_8197F(x, v) \
+ (BIT_CLEAR_BB_DATA_8197F(x) | BIT_BB_DATA_8197F(v))
+
+/* 2 REG_HMEBOX_E0_8197F */
+
+#define BIT_SHIFT_HMEBOX_E0_8197F 0
+#define BIT_MASK_HMEBOX_E0_8197F 0xffffffffL
+#define BIT_HMEBOX_E0_8197F(x) \
+ (((x) & BIT_MASK_HMEBOX_E0_8197F) << BIT_SHIFT_HMEBOX_E0_8197F)
+#define BITS_HMEBOX_E0_8197F \
+ (BIT_MASK_HMEBOX_E0_8197F << BIT_SHIFT_HMEBOX_E0_8197F)
+#define BIT_CLEAR_HMEBOX_E0_8197F(x) ((x) & (~BITS_HMEBOX_E0_8197F))
+#define BIT_GET_HMEBOX_E0_8197F(x) \
+ (((x) >> BIT_SHIFT_HMEBOX_E0_8197F) & BIT_MASK_HMEBOX_E0_8197F)
+#define BIT_SET_HMEBOX_E0_8197F(x, v) \
+ (BIT_CLEAR_HMEBOX_E0_8197F(x) | BIT_HMEBOX_E0_8197F(v))
+
+/* 2 REG_HMEBOX_E1_8197F */
+
+#define BIT_SHIFT_HMEBOX_E1_8197F 0
+#define BIT_MASK_HMEBOX_E1_8197F 0xffffffffL
+#define BIT_HMEBOX_E1_8197F(x) \
+ (((x) & BIT_MASK_HMEBOX_E1_8197F) << BIT_SHIFT_HMEBOX_E1_8197F)
+#define BITS_HMEBOX_E1_8197F \
+ (BIT_MASK_HMEBOX_E1_8197F << BIT_SHIFT_HMEBOX_E1_8197F)
+#define BIT_CLEAR_HMEBOX_E1_8197F(x) ((x) & (~BITS_HMEBOX_E1_8197F))
+#define BIT_GET_HMEBOX_E1_8197F(x) \
+ (((x) >> BIT_SHIFT_HMEBOX_E1_8197F) & BIT_MASK_HMEBOX_E1_8197F)
+#define BIT_SET_HMEBOX_E1_8197F(x, v) \
+ (BIT_CLEAR_HMEBOX_E1_8197F(x) | BIT_HMEBOX_E1_8197F(v))
+
+/* 2 REG_HMEBOX_E2_8197F */
+
+#define BIT_SHIFT_HMEBOX_E2_8197F 0
+#define BIT_MASK_HMEBOX_E2_8197F 0xffffffffL
+#define BIT_HMEBOX_E2_8197F(x) \
+ (((x) & BIT_MASK_HMEBOX_E2_8197F) << BIT_SHIFT_HMEBOX_E2_8197F)
+#define BITS_HMEBOX_E2_8197F \
+ (BIT_MASK_HMEBOX_E2_8197F << BIT_SHIFT_HMEBOX_E2_8197F)
+#define BIT_CLEAR_HMEBOX_E2_8197F(x) ((x) & (~BITS_HMEBOX_E2_8197F))
+#define BIT_GET_HMEBOX_E2_8197F(x) \
+ (((x) >> BIT_SHIFT_HMEBOX_E2_8197F) & BIT_MASK_HMEBOX_E2_8197F)
+#define BIT_SET_HMEBOX_E2_8197F(x, v) \
+ (BIT_CLEAR_HMEBOX_E2_8197F(x) | BIT_HMEBOX_E2_8197F(v))
+
+/* 2 REG_HMEBOX_E3_8197F */
+
+#define BIT_SHIFT_HMEBOX_E3_8197F 0
+#define BIT_MASK_HMEBOX_E3_8197F 0xffffffffL
+#define BIT_HMEBOX_E3_8197F(x) \
+ (((x) & BIT_MASK_HMEBOX_E3_8197F) << BIT_SHIFT_HMEBOX_E3_8197F)
+#define BITS_HMEBOX_E3_8197F \
+ (BIT_MASK_HMEBOX_E3_8197F << BIT_SHIFT_HMEBOX_E3_8197F)
+#define BIT_CLEAR_HMEBOX_E3_8197F(x) ((x) & (~BITS_HMEBOX_E3_8197F))
+#define BIT_GET_HMEBOX_E3_8197F(x) \
+ (((x) >> BIT_SHIFT_HMEBOX_E3_8197F) & BIT_MASK_HMEBOX_E3_8197F)
+#define BIT_SET_HMEBOX_E3_8197F(x, v) \
+ (BIT_CLEAR_HMEBOX_E3_8197F(x) | BIT_HMEBOX_E3_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_CR_EXT_8197F */
+
+#define BIT_SHIFT_PHY_REQ_DELAY_8197F 24
+#define BIT_MASK_PHY_REQ_DELAY_8197F 0xf
+#define BIT_PHY_REQ_DELAY_8197F(x) \
+ (((x) & BIT_MASK_PHY_REQ_DELAY_8197F) << BIT_SHIFT_PHY_REQ_DELAY_8197F)
+#define BITS_PHY_REQ_DELAY_8197F \
+ (BIT_MASK_PHY_REQ_DELAY_8197F << BIT_SHIFT_PHY_REQ_DELAY_8197F)
+#define BIT_CLEAR_PHY_REQ_DELAY_8197F(x) ((x) & (~BITS_PHY_REQ_DELAY_8197F))
+#define BIT_GET_PHY_REQ_DELAY_8197F(x) \
+ (((x) >> BIT_SHIFT_PHY_REQ_DELAY_8197F) & BIT_MASK_PHY_REQ_DELAY_8197F)
+#define BIT_SET_PHY_REQ_DELAY_8197F(x, v) \
+ (BIT_CLEAR_PHY_REQ_DELAY_8197F(x) | BIT_PHY_REQ_DELAY_8197F(v))
+
+#define BIT_SPD_DOWN_8197F BIT(16)
+
+#define BIT_SHIFT_NETYPE4_8197F 4
+#define BIT_MASK_NETYPE4_8197F 0x3
+#define BIT_NETYPE4_8197F(x) \
+ (((x) & BIT_MASK_NETYPE4_8197F) << BIT_SHIFT_NETYPE4_8197F)
+#define BITS_NETYPE4_8197F (BIT_MASK_NETYPE4_8197F << BIT_SHIFT_NETYPE4_8197F)
+#define BIT_CLEAR_NETYPE4_8197F(x) ((x) & (~BITS_NETYPE4_8197F))
+#define BIT_GET_NETYPE4_8197F(x) \
+ (((x) >> BIT_SHIFT_NETYPE4_8197F) & BIT_MASK_NETYPE4_8197F)
+#define BIT_SET_NETYPE4_8197F(x, v) \
+ (BIT_CLEAR_NETYPE4_8197F(x) | BIT_NETYPE4_8197F(v))
+
+#define BIT_SHIFT_NETYPE3_8197F 2
+#define BIT_MASK_NETYPE3_8197F 0x3
+#define BIT_NETYPE3_8197F(x) \
+ (((x) & BIT_MASK_NETYPE3_8197F) << BIT_SHIFT_NETYPE3_8197F)
+#define BITS_NETYPE3_8197F (BIT_MASK_NETYPE3_8197F << BIT_SHIFT_NETYPE3_8197F)
+#define BIT_CLEAR_NETYPE3_8197F(x) ((x) & (~BITS_NETYPE3_8197F))
+#define BIT_GET_NETYPE3_8197F(x) \
+ (((x) >> BIT_SHIFT_NETYPE3_8197F) & BIT_MASK_NETYPE3_8197F)
+#define BIT_SET_NETYPE3_8197F(x, v) \
+ (BIT_CLEAR_NETYPE3_8197F(x) | BIT_NETYPE3_8197F(v))
+
+#define BIT_SHIFT_NETYPE2_8197F 0
+#define BIT_MASK_NETYPE2_8197F 0x3
+#define BIT_NETYPE2_8197F(x) \
+ (((x) & BIT_MASK_NETYPE2_8197F) << BIT_SHIFT_NETYPE2_8197F)
+#define BITS_NETYPE2_8197F (BIT_MASK_NETYPE2_8197F << BIT_SHIFT_NETYPE2_8197F)
+#define BIT_CLEAR_NETYPE2_8197F(x) ((x) & (~BITS_NETYPE2_8197F))
+#define BIT_GET_NETYPE2_8197F(x) \
+ (((x) >> BIT_SHIFT_NETYPE2_8197F) & BIT_MASK_NETYPE2_8197F)
+#define BIT_SET_NETYPE2_8197F(x, v) \
+ (BIT_CLEAR_NETYPE2_8197F(x) | BIT_NETYPE2_8197F(v))
+
+/* 2 REG_FWFF_8197F */
+
+#define BIT_SHIFT_PKTNUM_TH_8197F 24
+#define BIT_MASK_PKTNUM_TH_8197F 0xff
+#define BIT_PKTNUM_TH_8197F(x) \
+ (((x) & BIT_MASK_PKTNUM_TH_8197F) << BIT_SHIFT_PKTNUM_TH_8197F)
+#define BITS_PKTNUM_TH_8197F \
+ (BIT_MASK_PKTNUM_TH_8197F << BIT_SHIFT_PKTNUM_TH_8197F)
+#define BIT_CLEAR_PKTNUM_TH_8197F(x) ((x) & (~BITS_PKTNUM_TH_8197F))
+#define BIT_GET_PKTNUM_TH_8197F(x) \
+ (((x) >> BIT_SHIFT_PKTNUM_TH_8197F) & BIT_MASK_PKTNUM_TH_8197F)
+#define BIT_SET_PKTNUM_TH_8197F(x, v) \
+ (BIT_CLEAR_PKTNUM_TH_8197F(x) | BIT_PKTNUM_TH_8197F(v))
+
+#define BIT_SHIFT_TIMER_TH_8197F 16
+#define BIT_MASK_TIMER_TH_8197F 0xff
+#define BIT_TIMER_TH_8197F(x) \
+ (((x) & BIT_MASK_TIMER_TH_8197F) << BIT_SHIFT_TIMER_TH_8197F)
+#define BITS_TIMER_TH_8197F \
+ (BIT_MASK_TIMER_TH_8197F << BIT_SHIFT_TIMER_TH_8197F)
+#define BIT_CLEAR_TIMER_TH_8197F(x) ((x) & (~BITS_TIMER_TH_8197F))
+#define BIT_GET_TIMER_TH_8197F(x) \
+ (((x) >> BIT_SHIFT_TIMER_TH_8197F) & BIT_MASK_TIMER_TH_8197F)
+#define BIT_SET_TIMER_TH_8197F(x, v) \
+ (BIT_CLEAR_TIMER_TH_8197F(x) | BIT_TIMER_TH_8197F(v))
+
+#define BIT_SHIFT_RXPKT1ENADDR_8197F 0
+#define BIT_MASK_RXPKT1ENADDR_8197F 0xffff
+#define BIT_RXPKT1ENADDR_8197F(x) \
+ (((x) & BIT_MASK_RXPKT1ENADDR_8197F) << BIT_SHIFT_RXPKT1ENADDR_8197F)
+#define BITS_RXPKT1ENADDR_8197F \
+ (BIT_MASK_RXPKT1ENADDR_8197F << BIT_SHIFT_RXPKT1ENADDR_8197F)
+#define BIT_CLEAR_RXPKT1ENADDR_8197F(x) ((x) & (~BITS_RXPKT1ENADDR_8197F))
+#define BIT_GET_RXPKT1ENADDR_8197F(x) \
+ (((x) >> BIT_SHIFT_RXPKT1ENADDR_8197F) & BIT_MASK_RXPKT1ENADDR_8197F)
+#define BIT_SET_RXPKT1ENADDR_8197F(x, v) \
+ (BIT_CLEAR_RXPKT1ENADDR_8197F(x) | BIT_RXPKT1ENADDR_8197F(v))
+
+/* 2 REG_RXFF_PTR_V1_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+#define BIT_SHIFT_RXFF0_RDPTR_V2_8197F 0
+#define BIT_MASK_RXFF0_RDPTR_V2_8197F 0x3ffff
+#define BIT_RXFF0_RDPTR_V2_8197F(x) \
+ (((x) & BIT_MASK_RXFF0_RDPTR_V2_8197F) \
+ << BIT_SHIFT_RXFF0_RDPTR_V2_8197F)
+#define BITS_RXFF0_RDPTR_V2_8197F \
+ (BIT_MASK_RXFF0_RDPTR_V2_8197F << BIT_SHIFT_RXFF0_RDPTR_V2_8197F)
+#define BIT_CLEAR_RXFF0_RDPTR_V2_8197F(x) ((x) & (~BITS_RXFF0_RDPTR_V2_8197F))
+#define BIT_GET_RXFF0_RDPTR_V2_8197F(x) \
+ (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8197F) & \
+ BIT_MASK_RXFF0_RDPTR_V2_8197F)
+#define BIT_SET_RXFF0_RDPTR_V2_8197F(x, v) \
+ (BIT_CLEAR_RXFF0_RDPTR_V2_8197F(x) | BIT_RXFF0_RDPTR_V2_8197F(v))
+
+/* 2 REG_RXFF_WTR_V1_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+#define BIT_SHIFT_RXFF0_WTPTR_V2_8197F 0
+#define BIT_MASK_RXFF0_WTPTR_V2_8197F 0x3ffff
+#define BIT_RXFF0_WTPTR_V2_8197F(x) \
+ (((x) & BIT_MASK_RXFF0_WTPTR_V2_8197F) \
+ << BIT_SHIFT_RXFF0_WTPTR_V2_8197F)
+#define BITS_RXFF0_WTPTR_V2_8197F \
+ (BIT_MASK_RXFF0_WTPTR_V2_8197F << BIT_SHIFT_RXFF0_WTPTR_V2_8197F)
+#define BIT_CLEAR_RXFF0_WTPTR_V2_8197F(x) ((x) & (~BITS_RXFF0_WTPTR_V2_8197F))
+#define BIT_GET_RXFF0_WTPTR_V2_8197F(x) \
+ (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8197F) & \
+ BIT_MASK_RXFF0_WTPTR_V2_8197F)
+#define BIT_SET_RXFF0_WTPTR_V2_8197F(x, v) \
+ (BIT_CLEAR_RXFF0_WTPTR_V2_8197F(x) | BIT_RXFF0_WTPTR_V2_8197F(v))
+
+/* 2 REG_FE2IMR_8197F */
+#define BIT_FS_TXSC_DESC_DONE_INT_EN_8197F BIT(28)
+#define BIT_FS_TXSC_BKDONE_INT_EN_8197F BIT(27)
+#define BIT_FS_TXSC_BEDONE_INT_EN_8197F BIT(26)
+#define BIT_FS_TXSC_VIDONE_INT_EN_8197F BIT(25)
+#define BIT_FS_TXSC_VODONE_INT_EN_8197F BIT(24)
+#define BIT_FS_ATIM_MB7_INT_EN_8197F BIT(23)
+#define BIT_FS_ATIM_MB6_INT_EN_8197F BIT(22)
+#define BIT_FS_ATIM_MB5_INT_EN_8197F BIT(21)
+#define BIT_FS_ATIM_MB4_INT_EN_8197F BIT(20)
+#define BIT_FS_ATIM_MB3_INT_EN_8197F BIT(19)
+#define BIT_FS_ATIM_MB2_INT_EN_8197F BIT(18)
+#define BIT_FS_ATIM_MB1_INT_EN_8197F BIT(17)
+#define BIT_FS_ATIM_MB0_INT_EN_8197F BIT(16)
+#define BIT_FS_TBTT4INT_EN_8197F BIT(11)
+#define BIT_FS_TBTT3INT_EN_8197F BIT(10)
+#define BIT_FS_TBTT2INT_EN_8197F BIT(9)
+#define BIT_FS_TBTT1INT_EN_8197F BIT(8)
+#define BIT_FS_TBTT0_MB7INT_EN_8197F BIT(7)
+#define BIT_FS_TBTT0_MB6INT_EN_8197F BIT(6)
+#define BIT_FS_TBTT0_MB5INT_EN_8197F BIT(5)
+#define BIT_FS_TBTT0_MB4INT_EN_8197F BIT(4)
+#define BIT_FS_TBTT0_MB3INT_EN_8197F BIT(3)
+#define BIT_FS_TBTT0_MB2INT_EN_8197F BIT(2)
+#define BIT_FS_TBTT0_MB1INT_EN_8197F BIT(1)
+#define BIT_FS_TBTT0_INT_EN_8197F BIT(0)
+
+/* 2 REG_FE2ISR_8197F */
+#define BIT_FS_TXSC_DESC_DONE_INT_8197F BIT(28)
+#define BIT_FS_TXSC_BKDONE_INT_8197F BIT(27)
+#define BIT_FS_TXSC_BEDONE_INT_8197F BIT(26)
+#define BIT_FS_TXSC_VIDONE_INT_8197F BIT(25)
+#define BIT_FS_TXSC_VODONE_INT_8197F BIT(24)
+#define BIT_FS_ATIM_MB7_INT_8197F BIT(23)
+#define BIT_FS_ATIM_MB6_INT_8197F BIT(22)
+#define BIT_FS_ATIM_MB5_INT_8197F BIT(21)
+#define BIT_FS_ATIM_MB4_INT_8197F BIT(20)
+#define BIT_FS_ATIM_MB3_INT_8197F BIT(19)
+#define BIT_FS_ATIM_MB2_INT_8197F BIT(18)
+#define BIT_FS_ATIM_MB1_INT_8197F BIT(17)
+#define BIT_FS_ATIM_MB0_INT_8197F BIT(16)
+#define BIT_FS_TBTT4INT_8197F BIT(11)
+#define BIT_FS_TBTT3INT_8197F BIT(10)
+#define BIT_FS_TBTT2INT_8197F BIT(9)
+#define BIT_FS_TBTT1INT_8197F BIT(8)
+#define BIT_FS_TBTT0_MB7INT_8197F BIT(7)
+#define BIT_FS_TBTT0_MB6INT_8197F BIT(6)
+#define BIT_FS_TBTT0_MB5INT_8197F BIT(5)
+#define BIT_FS_TBTT0_MB4INT_8197F BIT(4)
+#define BIT_FS_TBTT0_MB3INT_8197F BIT(3)
+#define BIT_FS_TBTT0_MB2INT_8197F BIT(2)
+#define BIT_FS_TBTT0_MB1INT_8197F BIT(1)
+#define BIT_FS_TBTT0_INT_8197F BIT(0)
+
+/* 2 REG_FE3IMR_8197F */
+#define BIT_FS_BCNELY4_AGGR_INT_EN_8197F BIT(31)
+#define BIT_FS_BCNELY3_AGGR_INT_EN_8197F BIT(30)
+#define BIT_FS_BCNELY2_AGGR_INT_EN_8197F BIT(29)
+#define BIT_FS_BCNELY1_AGGR_INT_EN_8197F BIT(28)
+#define BIT_FS_BCNDMA4_INT_EN_8197F BIT(27)
+#define BIT_FS_BCNDMA3_INT_EN_8197F BIT(26)
+#define BIT_FS_BCNDMA2_INT_EN_8197F BIT(25)
+#define BIT_FS_BCNDMA1_INT_EN_8197F BIT(24)
+#define BIT_FS_BCNDMA0_MB7_INT_EN_8197F BIT(23)
+#define BIT_FS_BCNDMA0_MB6_INT_EN_8197F BIT(22)
+#define BIT_FS_BCNDMA0_MB5_INT_EN_8197F BIT(21)
+#define BIT_FS_BCNDMA0_MB4_INT_EN_8197F BIT(20)
+#define BIT_FS_BCNDMA0_MB3_INT_EN_8197F BIT(19)
+#define BIT_FS_BCNDMA0_MB2_INT_EN_8197F BIT(18)
+#define BIT_FS_BCNDMA0_MB1_INT_EN_8197F BIT(17)
+#define BIT_FS_BCNDMA0_INT_EN_8197F BIT(16)
+#define BIT_FS_MTI_BCNIVLEAR_INT__EN_8197F BIT(15)
+#define BIT_FS_BCNERLY4_INT_EN_8197F BIT(11)
+#define BIT_FS_BCNERLY3_INT_EN_8197F BIT(10)
+#define BIT_FS_BCNERLY2_INT_EN_8197F BIT(9)
+#define BIT_FS_BCNERLY1_INT_EN_8197F BIT(8)
+#define BIT_FS_BCNERLY0_MB7INT_EN_8197F BIT(7)
+#define BIT_FS_BCNERLY0_MB6INT_EN_8197F BIT(6)
+#define BIT_FS_BCNERLY0_MB5INT_EN_8197F BIT(5)
+#define BIT_FS_BCNERLY0_MB4INT_EN_8197F BIT(4)
+#define BIT_FS_BCNERLY0_MB3INT_EN_8197F BIT(3)
+#define BIT_FS_BCNERLY0_MB2INT_EN_8197F BIT(2)
+#define BIT_FS_BCNERLY0_MB1INT_EN_8197F BIT(1)
+#define BIT_FS_BCNERLY0_INT_EN_8197F BIT(0)
+
+/* 2 REG_FE3ISR_8197F */
+#define BIT_FS_BCNELY4_AGGR_INT_8197F BIT(31)
+#define BIT_FS_BCNELY3_AGGR_INT_8197F BIT(30)
+#define BIT_FS_BCNELY2_AGGR_INT_8197F BIT(29)
+#define BIT_FS_BCNELY1_AGGR_INT_8197F BIT(28)
+#define BIT_FS_BCNDMA4_INT_8197F BIT(27)
+#define BIT_FS_BCNDMA3_INT_8197F BIT(26)
+#define BIT_FS_BCNDMA2_INT_8197F BIT(25)
+#define BIT_FS_BCNDMA1_INT_8197F BIT(24)
+#define BIT_FS_BCNDMA0_MB7_INT_8197F BIT(23)
+#define BIT_FS_BCNDMA0_MB6_INT_8197F BIT(22)
+#define BIT_FS_BCNDMA0_MB5_INT_8197F BIT(21)
+#define BIT_FS_BCNDMA0_MB4_INT_8197F BIT(20)
+#define BIT_FS_BCNDMA0_MB3_INT_8197F BIT(19)
+#define BIT_FS_BCNDMA0_MB2_INT_8197F BIT(18)
+#define BIT_FS_BCNDMA0_MB1_INT_8197F BIT(17)
+#define BIT_FS_BCNDMA0_INT_8197F BIT(16)
+#define BIT_FS_MTI_BCNIVLEAR_INT_8197F BIT(15)
+#define BIT_FS_BCNERLY4_INT_8197F BIT(11)
+#define BIT_FS_BCNERLY3_INT_8197F BIT(10)
+#define BIT_FS_BCNERLY2_INT_8197F BIT(9)
+#define BIT_FS_BCNERLY1_INT_8197F BIT(8)
+#define BIT_FS_BCNERLY0_MB7INT_8197F BIT(7)
+#define BIT_FS_BCNERLY0_MB6INT_8197F BIT(6)
+#define BIT_FS_BCNERLY0_MB5INT_8197F BIT(5)
+#define BIT_FS_BCNERLY0_MB4INT_8197F BIT(4)
+#define BIT_FS_BCNERLY0_MB3INT_8197F BIT(3)
+#define BIT_FS_BCNERLY0_MB2INT_8197F BIT(2)
+#define BIT_FS_BCNERLY0_MB1INT_8197F BIT(1)
+#define BIT_FS_BCNERLY0_INT_8197F BIT(0)
+
+/* 2 REG_FE4IMR_8197F */
+#define BIT_PORT4_PKTIN_INT_EN_8197F BIT(19)
+#define BIT_PORT3_PKTIN_INT_EN_8197F BIT(18)
+#define BIT_PORT2_PKTIN_INT_EN_8197F BIT(17)
+#define BIT_PORT1_PKTIN_INT_EN_8197F BIT(16)
+#define BIT_PORT4_RXUCMD0_OK_INT_EN_8197F BIT(15)
+#define BIT_PORT4_RXUCMD1_OK_INT_EN_8197F BIT(14)
+#define BIT_PORT4_RXBCMD0_OK_INT_EN_8197F BIT(13)
+#define BIT_PORT4_RXBCMD1_OK_INT_EN_8197F BIT(12)
+#define BIT_PORT3_RXUCMD0_OK_INT_EN_8197F BIT(11)
+#define BIT_PORT3_RXUCMD1_OK_INT_EN_8197F BIT(10)
+#define BIT_PORT3_RXBCMD0_OK_INT_EN_8197F BIT(9)
+#define BIT_PORT3_RXBCMD1_OK_INT_EN_8197F BIT(8)
+#define BIT_PORT2_RXUCMD0_OK_INT_EN_8197F BIT(7)
+#define BIT_PORT2_RXUCMD1_OK_INT_EN_8197F BIT(6)
+#define BIT_PORT2_RXBCMD0_OK_INT_EN_8197F BIT(5)
+#define BIT_PORT2_RXBCMD1_OK_INT_EN_8197F BIT(4)
+#define BIT_PORT1_RXUCMD0_OK_INT_EN_8197F BIT(3)
+#define BIT_PORT1_RXUCMD1_OK_INT_EN_8197F BIT(2)
+#define BIT_PORT1_RXBCMD0_OK_INT_EN_8197F BIT(1)
+#define BIT_PORT1_RXBCMD1_OK_INT_EN_8197F BIT(0)
+
+/* 2 REG_FE4ISR_8197F */
+#define BIT_PORT4_PKTIN_INT_8197F BIT(19)
+#define BIT_PORT3_PKTIN_INT_8197F BIT(18)
+#define BIT_PORT2_PKTIN_INT_8197F BIT(17)
+#define BIT_PORT1_PKTIN_INT_8197F BIT(16)
+#define BIT_PORT4_RXUCMD0_OK_INT_8197F BIT(15)
+#define BIT_PORT4_RXUCMD1_OK_INT_8197F BIT(14)
+#define BIT_PORT4_RXBCMD0_OK_INT_8197F BIT(13)
+#define BIT_PORT4_RXBCMD1_OK_INT_8197F BIT(12)
+#define BIT_PORT3_RXUCMD0_OK_INT_8197F BIT(11)
+#define BIT_PORT3_RXUCMD1_OK_INT_8197F BIT(10)
+#define BIT_PORT3_RXBCMD0_OK_INT_8197F BIT(9)
+#define BIT_PORT3_RXBCMD1_OK_INT_8197F BIT(8)
+#define BIT_PORT2_RXUCMD0_OK_INT_8197F BIT(7)
+#define BIT_PORT2_RXUCMD1_OK_INT_8197F BIT(6)
+#define BIT_PORT2_RXBCMD0_OK_INT_8197F BIT(5)
+#define BIT_PORT2_RXBCMD1_OK_INT_8197F BIT(4)
+#define BIT_PORT1_RXUCMD0_OK_INT_8197F BIT(3)
+#define BIT_PORT1_RXUCMD1_OK_INT_8197F BIT(2)
+#define BIT_PORT1_RXBCMD0_OK_INT_8197F BIT(1)
+#define BIT_PORT1_RXBCMD1_OK_INT_8197F BIT(0)
+
+/* 2 REG_FT1IMR_8197F */
+#define BIT__FT2ISR__IND_MSK_8197F BIT(30)
+#define BIT_FTM_PTT_INT_EN_8197F BIT(29)
+#define BIT_RXFTMREQ_INT_EN_8197F BIT(28)
+#define BIT_RXFTM_INT_EN_8197F BIT(27)
+#define BIT_TXFTM_INT_EN_8197F BIT(26)
+#define BIT_FS_H2C_CMD_OK_INT_EN_8197F BIT(25)
+#define BIT_FS_H2C_CMD_FULL_INT_EN_8197F BIT(24)
+#define BIT_FS_MACID_PWRCHANGE5_INT_EN_8197F BIT(23)
+#define BIT_FS_MACID_PWRCHANGE4_INT_EN_8197F BIT(22)
+#define BIT_FS_MACID_PWRCHANGE3_INT_EN_8197F BIT(21)
+#define BIT_FS_MACID_PWRCHANGE2_INT_EN_8197F BIT(20)
+#define BIT_FS_MACID_PWRCHANGE1_INT_EN_8197F BIT(19)
+#define BIT_FS_MACID_PWRCHANGE0_INT_EN_8197F BIT(18)
+#define BIT_FS_CTWEND2_INT_EN_8197F BIT(17)
+#define BIT_FS_CTWEND1_INT_EN_8197F BIT(16)
+#define BIT_FS_CTWEND0_INT_EN_8197F BIT(15)
+#define BIT_FS_TX_NULL1_INT_EN_8197F BIT(14)
+#define BIT_FS_TX_NULL0_INT_EN_8197F BIT(13)
+#define BIT_FS_TSF_BIT32_TOGGLE_EN_8197F BIT(12)
+#define BIT_FS_P2P_RFON2_INT_EN_8197F BIT(11)
+#define BIT_FS_P2P_RFOFF2_INT_EN_8197F BIT(10)
+#define BIT_FS_P2P_RFON1_INT_EN_8197F BIT(9)
+#define BIT_FS_P2P_RFOFF1_INT_EN_8197F BIT(8)
+#define BIT_FS_P2P_RFON0_INT_EN_8197F BIT(7)
+#define BIT_FS_P2P_RFOFF0_INT_EN_8197F BIT(6)
+#define BIT_FS_RX_UAPSDMD1_EN_8197F BIT(5)
+#define BIT_FS_RX_UAPSDMD0_EN_8197F BIT(4)
+#define BIT_FS_TRIGGER_PKT_EN_8197F BIT(3)
+#define BIT_FS_EOSP_INT_EN_8197F BIT(2)
+#define BIT_FS_RPWM2_INT_EN_8197F BIT(1)
+#define BIT_FS_RPWM_INT_EN_8197F BIT(0)
+
+/* 2 REG_FT1ISR_8197F */
+#define BIT__FT2ISR__IND_INT_8197F BIT(30)
+#define BIT_FTM_PTT_INT_8197F BIT(29)
+#define BIT_RXFTMREQ_INT_8197F BIT(28)
+#define BIT_RXFTM_INT_8197F BIT(27)
+#define BIT_TXFTM_INT_8197F BIT(26)
+#define BIT_FS_H2C_CMD_OK_INT_8197F BIT(25)
+#define BIT_FS_H2C_CMD_FULL_INT_8197F BIT(24)
+#define BIT_FS_MACID_PWRCHANGE5_INT_8197F BIT(23)
+#define BIT_FS_MACID_PWRCHANGE4_INT_8197F BIT(22)
+#define BIT_FS_MACID_PWRCHANGE3_INT_8197F BIT(21)
+#define BIT_FS_MACID_PWRCHANGE2_INT_8197F BIT(20)
+#define BIT_FS_MACID_PWRCHANGE1_INT_8197F BIT(19)
+#define BIT_FS_MACID_PWRCHANGE0_INT_8197F BIT(18)
+#define BIT_FS_CTWEND2_INT_8197F BIT(17)
+#define BIT_FS_CTWEND1_INT_8197F BIT(16)
+#define BIT_FS_CTWEND0_INT_8197F BIT(15)
+#define BIT_FS_TX_NULL1_INT_8197F BIT(14)
+#define BIT_FS_TX_NULL0_INT_8197F BIT(13)
+#define BIT_FS_TSF_BIT32_TOGGLE_INT_8197F BIT(12)
+#define BIT_FS_P2P_RFON2_INT_8197F BIT(11)
+#define BIT_FS_P2P_RFOFF2_INT_8197F BIT(10)
+#define BIT_FS_P2P_RFON1_INT_8197F BIT(9)
+#define BIT_FS_P2P_RFOFF1_INT_8197F BIT(8)
+#define BIT_FS_P2P_RFON0_INT_8197F BIT(7)
+#define BIT_FS_P2P_RFOFF0_INT_8197F BIT(6)
+#define BIT_FS_RX_UAPSDMD1_INT_8197F BIT(5)
+#define BIT_FS_RX_UAPSDMD0_INT_8197F BIT(4)
+#define BIT_FS_TRIGGER_PKT_INT_8197F BIT(3)
+#define BIT_FS_EOSP_INT_8197F BIT(2)
+#define BIT_FS_RPWM2_INT_8197F BIT(1)
+#define BIT_FS_RPWM_INT_8197F BIT(0)
+
+/* 2 REG_SPWR0_8197F */
+
+#define BIT_SHIFT_MID_31TO0_8197F 0
+#define BIT_MASK_MID_31TO0_8197F 0xffffffffL
+#define BIT_MID_31TO0_8197F(x) \
+ (((x) & BIT_MASK_MID_31TO0_8197F) << BIT_SHIFT_MID_31TO0_8197F)
+#define BITS_MID_31TO0_8197F \
+ (BIT_MASK_MID_31TO0_8197F << BIT_SHIFT_MID_31TO0_8197F)
+#define BIT_CLEAR_MID_31TO0_8197F(x) ((x) & (~BITS_MID_31TO0_8197F))
+#define BIT_GET_MID_31TO0_8197F(x) \
+ (((x) >> BIT_SHIFT_MID_31TO0_8197F) & BIT_MASK_MID_31TO0_8197F)
+#define BIT_SET_MID_31TO0_8197F(x, v) \
+ (BIT_CLEAR_MID_31TO0_8197F(x) | BIT_MID_31TO0_8197F(v))
+
+/* 2 REG_SPWR1_8197F */
+
+#define BIT_SHIFT_MID_63TO32_8197F 0
+#define BIT_MASK_MID_63TO32_8197F 0xffffffffL
+#define BIT_MID_63TO32_8197F(x) \
+ (((x) & BIT_MASK_MID_63TO32_8197F) << BIT_SHIFT_MID_63TO32_8197F)
+#define BITS_MID_63TO32_8197F \
+ (BIT_MASK_MID_63TO32_8197F << BIT_SHIFT_MID_63TO32_8197F)
+#define BIT_CLEAR_MID_63TO32_8197F(x) ((x) & (~BITS_MID_63TO32_8197F))
+#define BIT_GET_MID_63TO32_8197F(x) \
+ (((x) >> BIT_SHIFT_MID_63TO32_8197F) & BIT_MASK_MID_63TO32_8197F)
+#define BIT_SET_MID_63TO32_8197F(x, v) \
+ (BIT_CLEAR_MID_63TO32_8197F(x) | BIT_MID_63TO32_8197F(v))
+
+/* 2 REG_SPWR2_8197F */
+
+#define BIT_SHIFT_MID_95O64_8197F 0
+#define BIT_MASK_MID_95O64_8197F 0xffffffffL
+#define BIT_MID_95O64_8197F(x) \
+ (((x) & BIT_MASK_MID_95O64_8197F) << BIT_SHIFT_MID_95O64_8197F)
+#define BITS_MID_95O64_8197F \
+ (BIT_MASK_MID_95O64_8197F << BIT_SHIFT_MID_95O64_8197F)
+#define BIT_CLEAR_MID_95O64_8197F(x) ((x) & (~BITS_MID_95O64_8197F))
+#define BIT_GET_MID_95O64_8197F(x) \
+ (((x) >> BIT_SHIFT_MID_95O64_8197F) & BIT_MASK_MID_95O64_8197F)
+#define BIT_SET_MID_95O64_8197F(x, v) \
+ (BIT_CLEAR_MID_95O64_8197F(x) | BIT_MID_95O64_8197F(v))
+
+/* 2 REG_SPWR3_8197F */
+
+#define BIT_SHIFT_MID_127TO96_8197F 0
+#define BIT_MASK_MID_127TO96_8197F 0xffffffffL
+#define BIT_MID_127TO96_8197F(x) \
+ (((x) & BIT_MASK_MID_127TO96_8197F) << BIT_SHIFT_MID_127TO96_8197F)
+#define BITS_MID_127TO96_8197F \
+ (BIT_MASK_MID_127TO96_8197F << BIT_SHIFT_MID_127TO96_8197F)
+#define BIT_CLEAR_MID_127TO96_8197F(x) ((x) & (~BITS_MID_127TO96_8197F))
+#define BIT_GET_MID_127TO96_8197F(x) \
+ (((x) >> BIT_SHIFT_MID_127TO96_8197F) & BIT_MASK_MID_127TO96_8197F)
+#define BIT_SET_MID_127TO96_8197F(x, v) \
+ (BIT_CLEAR_MID_127TO96_8197F(x) | BIT_MID_127TO96_8197F(v))
+
+/* 2 REG_POWSEQ_8197F */
+
+#define BIT_SHIFT_SEQNUM_MID_8197F 16
+#define BIT_MASK_SEQNUM_MID_8197F 0xffff
+#define BIT_SEQNUM_MID_8197F(x) \
+ (((x) & BIT_MASK_SEQNUM_MID_8197F) << BIT_SHIFT_SEQNUM_MID_8197F)
+#define BITS_SEQNUM_MID_8197F \
+ (BIT_MASK_SEQNUM_MID_8197F << BIT_SHIFT_SEQNUM_MID_8197F)
+#define BIT_CLEAR_SEQNUM_MID_8197F(x) ((x) & (~BITS_SEQNUM_MID_8197F))
+#define BIT_GET_SEQNUM_MID_8197F(x) \
+ (((x) >> BIT_SHIFT_SEQNUM_MID_8197F) & BIT_MASK_SEQNUM_MID_8197F)
+#define BIT_SET_SEQNUM_MID_8197F(x, v) \
+ (BIT_CLEAR_SEQNUM_MID_8197F(x) | BIT_SEQNUM_MID_8197F(v))
+
+#define BIT_SHIFT_REF_MID_8197F 0
+#define BIT_MASK_REF_MID_8197F 0x7f
+#define BIT_REF_MID_8197F(x) \
+ (((x) & BIT_MASK_REF_MID_8197F) << BIT_SHIFT_REF_MID_8197F)
+#define BITS_REF_MID_8197F (BIT_MASK_REF_MID_8197F << BIT_SHIFT_REF_MID_8197F)
+#define BIT_CLEAR_REF_MID_8197F(x) ((x) & (~BITS_REF_MID_8197F))
+#define BIT_GET_REF_MID_8197F(x) \
+ (((x) >> BIT_SHIFT_REF_MID_8197F) & BIT_MASK_REF_MID_8197F)
+#define BIT_SET_REF_MID_8197F(x, v) \
+ (BIT_CLEAR_REF_MID_8197F(x) | BIT_REF_MID_8197F(v))
+
+/* 2 REG_TC7_CTRL_V1_8197F */
+#define BIT_TC7INT_EN_8197F BIT(26)
+#define BIT_TC7MODE_8197F BIT(25)
+#define BIT_TC7EN_8197F BIT(24)
+
+#define BIT_SHIFT_TC7DATA_8197F 0
+#define BIT_MASK_TC7DATA_8197F 0xffffff
+#define BIT_TC7DATA_8197F(x) \
+ (((x) & BIT_MASK_TC7DATA_8197F) << BIT_SHIFT_TC7DATA_8197F)
+#define BITS_TC7DATA_8197F (BIT_MASK_TC7DATA_8197F << BIT_SHIFT_TC7DATA_8197F)
+#define BIT_CLEAR_TC7DATA_8197F(x) ((x) & (~BITS_TC7DATA_8197F))
+#define BIT_GET_TC7DATA_8197F(x) \
+ (((x) >> BIT_SHIFT_TC7DATA_8197F) & BIT_MASK_TC7DATA_8197F)
+#define BIT_SET_TC7DATA_8197F(x, v) \
+ (BIT_CLEAR_TC7DATA_8197F(x) | BIT_TC7DATA_8197F(v))
+
+/* 2 REG_TC8_CTRL_V1_8197F */
+#define BIT_TC8INT_EN_8197F BIT(26)
+#define BIT_TC8MODE_8197F BIT(25)
+#define BIT_TC8EN_8197F BIT(24)
+
+#define BIT_SHIFT_TC8DATA_8197F 0
+#define BIT_MASK_TC8DATA_8197F 0xffffff
+#define BIT_TC8DATA_8197F(x) \
+ (((x) & BIT_MASK_TC8DATA_8197F) << BIT_SHIFT_TC8DATA_8197F)
+#define BITS_TC8DATA_8197F (BIT_MASK_TC8DATA_8197F << BIT_SHIFT_TC8DATA_8197F)
+#define BIT_CLEAR_TC8DATA_8197F(x) ((x) & (~BITS_TC8DATA_8197F))
+#define BIT_GET_TC8DATA_8197F(x) \
+ (((x) >> BIT_SHIFT_TC8DATA_8197F) & BIT_MASK_TC8DATA_8197F)
+#define BIT_SET_TC8DATA_8197F(x, v) \
+ (BIT_CLEAR_TC8DATA_8197F(x) | BIT_TC8DATA_8197F(v))
+
+/* 2 REG_RXBCN_TBTT_INTERVAL_PORT0TO3_8197F */
+
+/* 2 REG_RXBCN_TBTT_INTERVAL_PORT4_8197F */
+
+/* 2 REG_EXT_QUEUE_REG_8197F */
+
+#define BIT_SHIFT_PCIE_PRIORITY_SEL_8197F 0
+#define BIT_MASK_PCIE_PRIORITY_SEL_8197F 0x3
+#define BIT_PCIE_PRIORITY_SEL_8197F(x) \
+ (((x) & BIT_MASK_PCIE_PRIORITY_SEL_8197F) \
+ << BIT_SHIFT_PCIE_PRIORITY_SEL_8197F)
+#define BITS_PCIE_PRIORITY_SEL_8197F \
+ (BIT_MASK_PCIE_PRIORITY_SEL_8197F << BIT_SHIFT_PCIE_PRIORITY_SEL_8197F)
+#define BIT_CLEAR_PCIE_PRIORITY_SEL_8197F(x) \
+ ((x) & (~BITS_PCIE_PRIORITY_SEL_8197F))
+#define BIT_GET_PCIE_PRIORITY_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_PCIE_PRIORITY_SEL_8197F) & \
+ BIT_MASK_PCIE_PRIORITY_SEL_8197F)
+#define BIT_SET_PCIE_PRIORITY_SEL_8197F(x, v) \
+ (BIT_CLEAR_PCIE_PRIORITY_SEL_8197F(x) | BIT_PCIE_PRIORITY_SEL_8197F(v))
+
+/* 2 REG_COUNTER_CONTROL_8197F */
+
+#define BIT_SHIFT_COUNTER_BASE_8197F 16
+#define BIT_MASK_COUNTER_BASE_8197F 0x1fff
+#define BIT_COUNTER_BASE_8197F(x) \
+ (((x) & BIT_MASK_COUNTER_BASE_8197F) << BIT_SHIFT_COUNTER_BASE_8197F)
+#define BITS_COUNTER_BASE_8197F \
+ (BIT_MASK_COUNTER_BASE_8197F << BIT_SHIFT_COUNTER_BASE_8197F)
+#define BIT_CLEAR_COUNTER_BASE_8197F(x) ((x) & (~BITS_COUNTER_BASE_8197F))
+#define BIT_GET_COUNTER_BASE_8197F(x) \
+ (((x) >> BIT_SHIFT_COUNTER_BASE_8197F) & BIT_MASK_COUNTER_BASE_8197F)
+#define BIT_SET_COUNTER_BASE_8197F(x, v) \
+ (BIT_CLEAR_COUNTER_BASE_8197F(x) | BIT_COUNTER_BASE_8197F(v))
+
+#define BIT_EN_RTS_REQ_8197F BIT(9)
+#define BIT_EN_EDCA_REQ_8197F BIT(8)
+#define BIT_EN_PTCL_REQ_8197F BIT(7)
+#define BIT_EN_SCH_REQ_8197F BIT(6)
+#define BIT_EN_USB_CNT_8197F BIT(5)
+#define BIT_EN_PCIE_CNT_8197F BIT(4)
+#define BIT_RQPN_CNT_8197F BIT(3)
+#define BIT_RDE_CNT_8197F BIT(2)
+#define BIT_TDE_CNT_8197F BIT(1)
+#define BIT_DIS_CNT_8197F BIT(0)
+
+/* 2 REG_COUNTER_TH_8197F */
+#define BIT_CNT_ALL_MACID_8197F BIT(31)
+
+#define BIT_SHIFT_CNT_MACID_8197F 24
+#define BIT_MASK_CNT_MACID_8197F 0x7f
+#define BIT_CNT_MACID_8197F(x) \
+ (((x) & BIT_MASK_CNT_MACID_8197F) << BIT_SHIFT_CNT_MACID_8197F)
+#define BITS_CNT_MACID_8197F \
+ (BIT_MASK_CNT_MACID_8197F << BIT_SHIFT_CNT_MACID_8197F)
+#define BIT_CLEAR_CNT_MACID_8197F(x) ((x) & (~BITS_CNT_MACID_8197F))
+#define BIT_GET_CNT_MACID_8197F(x) \
+ (((x) >> BIT_SHIFT_CNT_MACID_8197F) & BIT_MASK_CNT_MACID_8197F)
+#define BIT_SET_CNT_MACID_8197F(x, v) \
+ (BIT_CLEAR_CNT_MACID_8197F(x) | BIT_CNT_MACID_8197F(v))
+
+#define BIT_SHIFT_AGG_VALUE2_8197F 16
+#define BIT_MASK_AGG_VALUE2_8197F 0x7f
+#define BIT_AGG_VALUE2_8197F(x) \
+ (((x) & BIT_MASK_AGG_VALUE2_8197F) << BIT_SHIFT_AGG_VALUE2_8197F)
+#define BITS_AGG_VALUE2_8197F \
+ (BIT_MASK_AGG_VALUE2_8197F << BIT_SHIFT_AGG_VALUE2_8197F)
+#define BIT_CLEAR_AGG_VALUE2_8197F(x) ((x) & (~BITS_AGG_VALUE2_8197F))
+#define BIT_GET_AGG_VALUE2_8197F(x) \
+ (((x) >> BIT_SHIFT_AGG_VALUE2_8197F) & BIT_MASK_AGG_VALUE2_8197F)
+#define BIT_SET_AGG_VALUE2_8197F(x, v) \
+ (BIT_CLEAR_AGG_VALUE2_8197F(x) | BIT_AGG_VALUE2_8197F(v))
+
+#define BIT_SHIFT_AGG_VALUE1_8197F 8
+#define BIT_MASK_AGG_VALUE1_8197F 0x7f
+#define BIT_AGG_VALUE1_8197F(x) \
+ (((x) & BIT_MASK_AGG_VALUE1_8197F) << BIT_SHIFT_AGG_VALUE1_8197F)
+#define BITS_AGG_VALUE1_8197F \
+ (BIT_MASK_AGG_VALUE1_8197F << BIT_SHIFT_AGG_VALUE1_8197F)
+#define BIT_CLEAR_AGG_VALUE1_8197F(x) ((x) & (~BITS_AGG_VALUE1_8197F))
+#define BIT_GET_AGG_VALUE1_8197F(x) \
+ (((x) >> BIT_SHIFT_AGG_VALUE1_8197F) & BIT_MASK_AGG_VALUE1_8197F)
+#define BIT_SET_AGG_VALUE1_8197F(x, v) \
+ (BIT_CLEAR_AGG_VALUE1_8197F(x) | BIT_AGG_VALUE1_8197F(v))
+
+#define BIT_SHIFT_AGG_VALUE0_8197F 0
+#define BIT_MASK_AGG_VALUE0_8197F 0x7f
+#define BIT_AGG_VALUE0_8197F(x) \
+ (((x) & BIT_MASK_AGG_VALUE0_8197F) << BIT_SHIFT_AGG_VALUE0_8197F)
+#define BITS_AGG_VALUE0_8197F \
+ (BIT_MASK_AGG_VALUE0_8197F << BIT_SHIFT_AGG_VALUE0_8197F)
+#define BIT_CLEAR_AGG_VALUE0_8197F(x) ((x) & (~BITS_AGG_VALUE0_8197F))
+#define BIT_GET_AGG_VALUE0_8197F(x) \
+ (((x) >> BIT_SHIFT_AGG_VALUE0_8197F) & BIT_MASK_AGG_VALUE0_8197F)
+#define BIT_SET_AGG_VALUE0_8197F(x, v) \
+ (BIT_CLEAR_AGG_VALUE0_8197F(x) | BIT_AGG_VALUE0_8197F(v))
+
+/* 2 REG_COUNTER_SET_8197F */
+#define BIT_RTS_RST_8197F BIT(24)
+#define BIT_PTCL_RST_8197F BIT(23)
+#define BIT_SCH_RST_8197F BIT(22)
+#define BIT_EDCA_RST_8197F BIT(21)
+#define BIT_RQPN_RST_8197F BIT(20)
+#define BIT_USB_RST_8197F BIT(19)
+#define BIT_PCIE_RST_8197F BIT(18)
+#define BIT_RXDMA_RST_8197F BIT(17)
+#define BIT_TXDMA_RST_8197F BIT(16)
+#define BIT_EN_RTS_START_8197F BIT(8)
+#define BIT_EN_PTCL_START_8197F BIT(7)
+#define BIT_EN_SCH_START_8197F BIT(6)
+#define BIT_EN_EDCA_START_8197F BIT(5)
+#define BIT_EN_RQPN_START_8197F BIT(4)
+#define BIT_EN_USB_START_8197F BIT(3)
+#define BIT_EN_PCIE_START_8197F BIT(2)
+#define BIT_EN_RXDMA_START_8197F BIT(1)
+#define BIT_EN_TXDMA_START_8197F BIT(0)
+
+/* 2 REG_COUNTER_OVERFLOW_8197F */
+#define BIT_RTS_OVF_8197F BIT(8)
+#define BIT_PTCL_OVF_8197F BIT(7)
+#define BIT_SCH_OVF_8197F BIT(6)
+#define BIT_EDCA_OVF_8197F BIT(5)
+#define BIT_RQPN_OVF_8197F BIT(4)
+#define BIT_USB_OVF_8197F BIT(3)
+#define BIT_PCIE_OVF_8197F BIT(2)
+#define BIT_RXDMA_OVF_8197F BIT(1)
+#define BIT_TXDMA_OVF_8197F BIT(0)
+
+/* 2 REG_TDE_LEN_TH_8197F */
+
+#define BIT_SHIFT_TXDMA_LEN_TH0_8197F 16
+#define BIT_MASK_TXDMA_LEN_TH0_8197F 0xffff
+#define BIT_TXDMA_LEN_TH0_8197F(x) \
+ (((x) & BIT_MASK_TXDMA_LEN_TH0_8197F) << BIT_SHIFT_TXDMA_LEN_TH0_8197F)
+#define BITS_TXDMA_LEN_TH0_8197F \
+ (BIT_MASK_TXDMA_LEN_TH0_8197F << BIT_SHIFT_TXDMA_LEN_TH0_8197F)
+#define BIT_CLEAR_TXDMA_LEN_TH0_8197F(x) ((x) & (~BITS_TXDMA_LEN_TH0_8197F))
+#define BIT_GET_TXDMA_LEN_TH0_8197F(x) \
+ (((x) >> BIT_SHIFT_TXDMA_LEN_TH0_8197F) & BIT_MASK_TXDMA_LEN_TH0_8197F)
+#define BIT_SET_TXDMA_LEN_TH0_8197F(x, v) \
+ (BIT_CLEAR_TXDMA_LEN_TH0_8197F(x) | BIT_TXDMA_LEN_TH0_8197F(v))
+
+#define BIT_SHIFT_TXDMA_LEN_TH1_8197F 0
+#define BIT_MASK_TXDMA_LEN_TH1_8197F 0xffff
+#define BIT_TXDMA_LEN_TH1_8197F(x) \
+ (((x) & BIT_MASK_TXDMA_LEN_TH1_8197F) << BIT_SHIFT_TXDMA_LEN_TH1_8197F)
+#define BITS_TXDMA_LEN_TH1_8197F \
+ (BIT_MASK_TXDMA_LEN_TH1_8197F << BIT_SHIFT_TXDMA_LEN_TH1_8197F)
+#define BIT_CLEAR_TXDMA_LEN_TH1_8197F(x) ((x) & (~BITS_TXDMA_LEN_TH1_8197F))
+#define BIT_GET_TXDMA_LEN_TH1_8197F(x) \
+ (((x) >> BIT_SHIFT_TXDMA_LEN_TH1_8197F) & BIT_MASK_TXDMA_LEN_TH1_8197F)
+#define BIT_SET_TXDMA_LEN_TH1_8197F(x, v) \
+ (BIT_CLEAR_TXDMA_LEN_TH1_8197F(x) | BIT_TXDMA_LEN_TH1_8197F(v))
+
+/* 2 REG_RDE_LEN_TH_8197F */
+
+#define BIT_SHIFT_RXDMA_LEN_TH0_8197F 16
+#define BIT_MASK_RXDMA_LEN_TH0_8197F 0xffff
+#define BIT_RXDMA_LEN_TH0_8197F(x) \
+ (((x) & BIT_MASK_RXDMA_LEN_TH0_8197F) << BIT_SHIFT_RXDMA_LEN_TH0_8197F)
+#define BITS_RXDMA_LEN_TH0_8197F \
+ (BIT_MASK_RXDMA_LEN_TH0_8197F << BIT_SHIFT_RXDMA_LEN_TH0_8197F)
+#define BIT_CLEAR_RXDMA_LEN_TH0_8197F(x) ((x) & (~BITS_RXDMA_LEN_TH0_8197F))
+#define BIT_GET_RXDMA_LEN_TH0_8197F(x) \
+ (((x) >> BIT_SHIFT_RXDMA_LEN_TH0_8197F) & BIT_MASK_RXDMA_LEN_TH0_8197F)
+#define BIT_SET_RXDMA_LEN_TH0_8197F(x, v) \
+ (BIT_CLEAR_RXDMA_LEN_TH0_8197F(x) | BIT_RXDMA_LEN_TH0_8197F(v))
+
+#define BIT_SHIFT_RXDMA_LEN_TH1_8197F 0
+#define BIT_MASK_RXDMA_LEN_TH1_8197F 0xffff
+#define BIT_RXDMA_LEN_TH1_8197F(x) \
+ (((x) & BIT_MASK_RXDMA_LEN_TH1_8197F) << BIT_SHIFT_RXDMA_LEN_TH1_8197F)
+#define BITS_RXDMA_LEN_TH1_8197F \
+ (BIT_MASK_RXDMA_LEN_TH1_8197F << BIT_SHIFT_RXDMA_LEN_TH1_8197F)
+#define BIT_CLEAR_RXDMA_LEN_TH1_8197F(x) ((x) & (~BITS_RXDMA_LEN_TH1_8197F))
+#define BIT_GET_RXDMA_LEN_TH1_8197F(x) \
+ (((x) >> BIT_SHIFT_RXDMA_LEN_TH1_8197F) & BIT_MASK_RXDMA_LEN_TH1_8197F)
+#define BIT_SET_RXDMA_LEN_TH1_8197F(x, v) \
+ (BIT_CLEAR_RXDMA_LEN_TH1_8197F(x) | BIT_RXDMA_LEN_TH1_8197F(v))
+
+/* 2 REG_PCIE_EXEC_TIME_8197F */
+
+#define BIT_SHIFT_COUNTER_INTERVAL_SEL_8197F 16
+#define BIT_MASK_COUNTER_INTERVAL_SEL_8197F 0x3
+#define BIT_COUNTER_INTERVAL_SEL_8197F(x) \
+ (((x) & BIT_MASK_COUNTER_INTERVAL_SEL_8197F) \
+ << BIT_SHIFT_COUNTER_INTERVAL_SEL_8197F)
+#define BITS_COUNTER_INTERVAL_SEL_8197F \
+ (BIT_MASK_COUNTER_INTERVAL_SEL_8197F \
+ << BIT_SHIFT_COUNTER_INTERVAL_SEL_8197F)
+#define BIT_CLEAR_COUNTER_INTERVAL_SEL_8197F(x) \
+ ((x) & (~BITS_COUNTER_INTERVAL_SEL_8197F))
+#define BIT_GET_COUNTER_INTERVAL_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_COUNTER_INTERVAL_SEL_8197F) & \
+ BIT_MASK_COUNTER_INTERVAL_SEL_8197F)
+#define BIT_SET_COUNTER_INTERVAL_SEL_8197F(x, v) \
+ (BIT_CLEAR_COUNTER_INTERVAL_SEL_8197F(x) | \
+ BIT_COUNTER_INTERVAL_SEL_8197F(v))
+
+#define BIT_SHIFT_PCIE_TRANS_DATA_TH1_8197F 0
+#define BIT_MASK_PCIE_TRANS_DATA_TH1_8197F 0xffff
+#define BIT_PCIE_TRANS_DATA_TH1_8197F(x) \
+ (((x) & BIT_MASK_PCIE_TRANS_DATA_TH1_8197F) \
+ << BIT_SHIFT_PCIE_TRANS_DATA_TH1_8197F)
+#define BITS_PCIE_TRANS_DATA_TH1_8197F \
+ (BIT_MASK_PCIE_TRANS_DATA_TH1_8197F \
+ << BIT_SHIFT_PCIE_TRANS_DATA_TH1_8197F)
+#define BIT_CLEAR_PCIE_TRANS_DATA_TH1_8197F(x) \
+ ((x) & (~BITS_PCIE_TRANS_DATA_TH1_8197F))
+#define BIT_GET_PCIE_TRANS_DATA_TH1_8197F(x) \
+ (((x) >> BIT_SHIFT_PCIE_TRANS_DATA_TH1_8197F) & \
+ BIT_MASK_PCIE_TRANS_DATA_TH1_8197F)
+#define BIT_SET_PCIE_TRANS_DATA_TH1_8197F(x, v) \
+ (BIT_CLEAR_PCIE_TRANS_DATA_TH1_8197F(x) | \
+ BIT_PCIE_TRANS_DATA_TH1_8197F(v))
+
+/* 2 REG_FT2IMR_8197F */
+#define BIT_PORT4_RX_UCMD1_UAPSD0_OK_INT_EN_8197F BIT(31)
+#define BIT_PORT4_RX_UCMD0_UAPSD0_OK_INT_EN_8197F BIT(30)
+#define BIT_PORT4_TRIPKT_OK_INT_EN_8197F BIT(29)
+#define BIT_PORT4_RX_EOSP_OK_INT_EN_8197F BIT(28)
+#define BIT_PORT3_RX_UCMD1_UAPSD0_OK_INT_EN_8197F BIT(27)
+#define BIT_PORT3_RX_UCMD0_UAPSD0_OK_INT_EN_8197F BIT(26)
+#define BIT_PORT3_TRIPKT_OK_INT_EN_8197F BIT(25)
+#define BIT_PORT3_RX_EOSP_OK_INT_EN_8197F BIT(24)
+#define BIT_PORT2_RX_UCMD1_UAPSD0_OK_INT_EN_8197F BIT(23)
+#define BIT_PORT2_RX_UCMD0_UAPSD0_OK_INT_EN_8197F BIT(22)
+#define BIT_PORT2_TRIPKT_OK_INT_EN_8197F BIT(21)
+#define BIT_PORT2_RX_EOSP_OK_INT_EN_8197F BIT(20)
+#define BIT_PORT1_RX_UCMD1_UAPSD0_OK_INT_EN_8197F BIT(19)
+#define BIT_PORT1_RX_UCMD0_UAPSD0_OK_INT_EN_8197F BIT(18)
+#define BIT_PORT1_TRIPKT_OK_INT_EN_8197F BIT(17)
+#define BIT_PORT1_RX_EOSP_OK_INT_EN_8197F BIT(16)
+#define BIT_NOA2_TSFT_BIT32_TOGGLE_INT_EN_8197F BIT(9)
+#define BIT_NOA1_TSFT_BIT32_TOGGLE_INT_EN_8197F BIT(8)
+#define BIT_PORT4_TX_NULL1_DONE_INT_EN_8197F BIT(7)
+#define BIT_PORT4_TX_NULL0_DONE_INT_EN_8197F BIT(6)
+#define BIT_PORT3_TX_NULL1_DONE_INT_EN_8197F BIT(5)
+#define BIT_PORT3_TX_NULL0_DONE_INT_EN_8197F BIT(4)
+#define BIT_PORT2_TX_NULL1_DONE_INT_EN_8197F BIT(3)
+#define BIT_PORT2_TX_NULL0_DONE_INT_EN_8197F BIT(2)
+#define BIT_PORT1_TX_NULL1_DONE_INT_EN_8197F BIT(1)
+#define BIT_PORT1_TX_NULL0_DONE_INT_EN_8197F BIT(0)
+
+/* 2 REG_FT2ISR_8197F */
+#define BIT_PORT4_RX_UCMD1_UAPSD0_OK_INT_8197F BIT(31)
+#define BIT_PORT4_RX_UCMD0_UAPSD0_OK_INT_8197F BIT(30)
+#define BIT_PORT4_TRIPKT_OK_INT_8197F BIT(29)
+#define BIT_PORT4_RX_EOSP_OK_INT_8197F BIT(28)
+#define BIT_PORT3_RX_UCMD1_UAPSD0_OK_INT_8197F BIT(27)
+#define BIT_PORT3_RX_UCMD0_UAPSD0_OK_INT_8197F BIT(26)
+#define BIT_PORT3_TRIPKT_OK_INT_8197F BIT(25)
+#define BIT_PORT3_RX_EOSP_OK_INT_8197F BIT(24)
+#define BIT_PORT2_RX_UCMD1_UAPSD0_OK_INT_8197F BIT(23)
+#define BIT_PORT2_RX_UCMD0_UAPSD0_OK_INT_8197F BIT(22)
+#define BIT_PORT2_TRIPKT_OK_INT_8197F BIT(21)
+#define BIT_PORT2_RX_EOSP_OK_INT_8197F BIT(20)
+#define BIT_PORT1_RX_UCMD1_UAPSD0_OK_INT_8197F BIT(19)
+#define BIT_PORT1_RX_UCMD0_UAPSD0_OK_INT_8197F BIT(18)
+#define BIT_PORT1_TRIPKT_OK_INT_8197F BIT(17)
+#define BIT_PORT1_RX_EOSP_OK_INT_8197F BIT(16)
+#define BIT_NOA2_TSFT_BIT32_TOGGLE_INT_8197F BIT(9)
+#define BIT_NOA1_TSFT_BIT32_TOGGLE_INT_8197F BIT(8)
+#define BIT_PORT4_TX_NULL1_DONE_INT_8197F BIT(7)
+#define BIT_PORT4_TX_NULL0_DONE_INT_8197F BIT(6)
+#define BIT_PORT3_TX_NULL1_DONE_INT_8197F BIT(5)
+#define BIT_PORT3_TX_NULL0_DONE_INT_8197F BIT(4)
+#define BIT_PORT2_TX_NULL1_DONE_INT_8197F BIT(3)
+#define BIT_PORT2_TX_NULL0_DONE_INT_8197F BIT(2)
+#define BIT_PORT1_TX_NULL1_DONE_INT_8197F BIT(1)
+#define BIT_PORT1_TX_NULL0_DONE_INT_8197F BIT(0)
+
+/* 2 REG_MSG2_8197F */
+
+#define BIT_SHIFT_FW_MSG2_8197F 0
+#define BIT_MASK_FW_MSG2_8197F 0xffffffffL
+#define BIT_FW_MSG2_8197F(x) \
+ (((x) & BIT_MASK_FW_MSG2_8197F) << BIT_SHIFT_FW_MSG2_8197F)
+#define BITS_FW_MSG2_8197F (BIT_MASK_FW_MSG2_8197F << BIT_SHIFT_FW_MSG2_8197F)
+#define BIT_CLEAR_FW_MSG2_8197F(x) ((x) & (~BITS_FW_MSG2_8197F))
+#define BIT_GET_FW_MSG2_8197F(x) \
+ (((x) >> BIT_SHIFT_FW_MSG2_8197F) & BIT_MASK_FW_MSG2_8197F)
+#define BIT_SET_FW_MSG2_8197F(x, v) \
+ (BIT_CLEAR_FW_MSG2_8197F(x) | BIT_FW_MSG2_8197F(v))
+
+/* 2 REG_MSG3_8197F */
+
+#define BIT_SHIFT_FW_MSG3_8197F 0
+#define BIT_MASK_FW_MSG3_8197F 0xffffffffL
+#define BIT_FW_MSG3_8197F(x) \
+ (((x) & BIT_MASK_FW_MSG3_8197F) << BIT_SHIFT_FW_MSG3_8197F)
+#define BITS_FW_MSG3_8197F (BIT_MASK_FW_MSG3_8197F << BIT_SHIFT_FW_MSG3_8197F)
+#define BIT_CLEAR_FW_MSG3_8197F(x) ((x) & (~BITS_FW_MSG3_8197F))
+#define BIT_GET_FW_MSG3_8197F(x) \
+ (((x) >> BIT_SHIFT_FW_MSG3_8197F) & BIT_MASK_FW_MSG3_8197F)
+#define BIT_SET_FW_MSG3_8197F(x, v) \
+ (BIT_CLEAR_FW_MSG3_8197F(x) | BIT_FW_MSG3_8197F(v))
+
+/* 2 REG_MSG4_8197F */
+
+#define BIT_SHIFT_FW_MSG4_8197F 0
+#define BIT_MASK_FW_MSG4_8197F 0xffffffffL
+#define BIT_FW_MSG4_8197F(x) \
+ (((x) & BIT_MASK_FW_MSG4_8197F) << BIT_SHIFT_FW_MSG4_8197F)
+#define BITS_FW_MSG4_8197F (BIT_MASK_FW_MSG4_8197F << BIT_SHIFT_FW_MSG4_8197F)
+#define BIT_CLEAR_FW_MSG4_8197F(x) ((x) & (~BITS_FW_MSG4_8197F))
+#define BIT_GET_FW_MSG4_8197F(x) \
+ (((x) >> BIT_SHIFT_FW_MSG4_8197F) & BIT_MASK_FW_MSG4_8197F)
+#define BIT_SET_FW_MSG4_8197F(x, v) \
+ (BIT_CLEAR_FW_MSG4_8197F(x) | BIT_FW_MSG4_8197F(v))
+
+/* 2 REG_MSG5_8197F */
+
+#define BIT_SHIFT_FW_MSG5_8197F 0
+#define BIT_MASK_FW_MSG5_8197F 0xffffffffL
+#define BIT_FW_MSG5_8197F(x) \
+ (((x) & BIT_MASK_FW_MSG5_8197F) << BIT_SHIFT_FW_MSG5_8197F)
+#define BITS_FW_MSG5_8197F (BIT_MASK_FW_MSG5_8197F << BIT_SHIFT_FW_MSG5_8197F)
+#define BIT_CLEAR_FW_MSG5_8197F(x) ((x) & (~BITS_FW_MSG5_8197F))
+#define BIT_GET_FW_MSG5_8197F(x) \
+ (((x) >> BIT_SHIFT_FW_MSG5_8197F) & BIT_MASK_FW_MSG5_8197F)
+#define BIT_SET_FW_MSG5_8197F(x, v) \
+ (BIT_CLEAR_FW_MSG5_8197F(x) | BIT_FW_MSG5_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_FIFOPAGE_CTRL_1_8197F */
+
+#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8197F 16
+#define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8197F 0xff
+#define BIT_TX_OQT_HE_FREE_SPACE_V1_8197F(x) \
+ (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8197F) \
+ << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8197F)
+#define BITS_TX_OQT_HE_FREE_SPACE_V1_8197F \
+ (BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8197F \
+ << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8197F)
+#define BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8197F(x) \
+ ((x) & (~BITS_TX_OQT_HE_FREE_SPACE_V1_8197F))
+#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8197F) & \
+ BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8197F)
+#define BIT_SET_TX_OQT_HE_FREE_SPACE_V1_8197F(x, v) \
+ (BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8197F(x) | \
+ BIT_TX_OQT_HE_FREE_SPACE_V1_8197F(v))
+
+#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8197F 0
+#define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8197F 0xff
+#define BIT_TX_OQT_NL_FREE_SPACE_V1_8197F(x) \
+ (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8197F) \
+ << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8197F)
+#define BITS_TX_OQT_NL_FREE_SPACE_V1_8197F \
+ (BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8197F \
+ << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8197F)
+#define BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8197F(x) \
+ ((x) & (~BITS_TX_OQT_NL_FREE_SPACE_V1_8197F))
+#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8197F) & \
+ BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8197F)
+#define BIT_SET_TX_OQT_NL_FREE_SPACE_V1_8197F(x, v) \
+ (BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8197F(x) | \
+ BIT_TX_OQT_NL_FREE_SPACE_V1_8197F(v))
+
+/* 2 REG_FIFOPAGE_CTRL_2_8197F */
+#define BIT_BCN_VALID_1_V1_8197F BIT(31)
+
+#define BIT_SHIFT_BCN_HEAD_1_V1_8197F 16
+#define BIT_MASK_BCN_HEAD_1_V1_8197F 0xfff
+#define BIT_BCN_HEAD_1_V1_8197F(x) \
+ (((x) & BIT_MASK_BCN_HEAD_1_V1_8197F) << BIT_SHIFT_BCN_HEAD_1_V1_8197F)
+#define BITS_BCN_HEAD_1_V1_8197F \
+ (BIT_MASK_BCN_HEAD_1_V1_8197F << BIT_SHIFT_BCN_HEAD_1_V1_8197F)
+#define BIT_CLEAR_BCN_HEAD_1_V1_8197F(x) ((x) & (~BITS_BCN_HEAD_1_V1_8197F))
+#define BIT_GET_BCN_HEAD_1_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_BCN_HEAD_1_V1_8197F) & BIT_MASK_BCN_HEAD_1_V1_8197F)
+#define BIT_SET_BCN_HEAD_1_V1_8197F(x, v) \
+ (BIT_CLEAR_BCN_HEAD_1_V1_8197F(x) | BIT_BCN_HEAD_1_V1_8197F(v))
+
+#define BIT_BCN_VALID_V1_8197F BIT(15)
+
+#define BIT_SHIFT_BCN_HEAD_V1_8197F 0
+#define BIT_MASK_BCN_HEAD_V1_8197F 0xfff
+#define BIT_BCN_HEAD_V1_8197F(x) \
+ (((x) & BIT_MASK_BCN_HEAD_V1_8197F) << BIT_SHIFT_BCN_HEAD_V1_8197F)
+#define BITS_BCN_HEAD_V1_8197F \
+ (BIT_MASK_BCN_HEAD_V1_8197F << BIT_SHIFT_BCN_HEAD_V1_8197F)
+#define BIT_CLEAR_BCN_HEAD_V1_8197F(x) ((x) & (~BITS_BCN_HEAD_V1_8197F))
+#define BIT_GET_BCN_HEAD_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_BCN_HEAD_V1_8197F) & BIT_MASK_BCN_HEAD_V1_8197F)
+#define BIT_SET_BCN_HEAD_V1_8197F(x, v) \
+ (BIT_CLEAR_BCN_HEAD_V1_8197F(x) | BIT_BCN_HEAD_V1_8197F(v))
+
+/* 2 REG_AUTO_LLT_V1_8197F */
+
+#define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F 24
+#define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F 0xff
+#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x) \
+ (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F) \
+ << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F)
+#define BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F \
+ (BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F \
+ << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F)
+#define BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x) \
+ ((x) & (~BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F))
+#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F) & \
+ BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F)
+#define BIT_SET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x, v) \
+ (BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(x) | \
+ BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8197F(v))
+
+#define BIT_SHIFT_LLT_FREE_PAGE_V1_8197F 8
+#define BIT_MASK_LLT_FREE_PAGE_V1_8197F 0xffff
+#define BIT_LLT_FREE_PAGE_V1_8197F(x) \
+ (((x) & BIT_MASK_LLT_FREE_PAGE_V1_8197F) \
+ << BIT_SHIFT_LLT_FREE_PAGE_V1_8197F)
+#define BITS_LLT_FREE_PAGE_V1_8197F \
+ (BIT_MASK_LLT_FREE_PAGE_V1_8197F << BIT_SHIFT_LLT_FREE_PAGE_V1_8197F)
+#define BIT_CLEAR_LLT_FREE_PAGE_V1_8197F(x) \
+ ((x) & (~BITS_LLT_FREE_PAGE_V1_8197F))
+#define BIT_GET_LLT_FREE_PAGE_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1_8197F) & \
+ BIT_MASK_LLT_FREE_PAGE_V1_8197F)
+#define BIT_SET_LLT_FREE_PAGE_V1_8197F(x, v) \
+ (BIT_CLEAR_LLT_FREE_PAGE_V1_8197F(x) | BIT_LLT_FREE_PAGE_V1_8197F(v))
+
+#define BIT_SHIFT_BLK_DESC_NUM_8197F 4
+#define BIT_MASK_BLK_DESC_NUM_8197F 0xf
+#define BIT_BLK_DESC_NUM_8197F(x) \
+ (((x) & BIT_MASK_BLK_DESC_NUM_8197F) << BIT_SHIFT_BLK_DESC_NUM_8197F)
+#define BITS_BLK_DESC_NUM_8197F \
+ (BIT_MASK_BLK_DESC_NUM_8197F << BIT_SHIFT_BLK_DESC_NUM_8197F)
+#define BIT_CLEAR_BLK_DESC_NUM_8197F(x) ((x) & (~BITS_BLK_DESC_NUM_8197F))
+#define BIT_GET_BLK_DESC_NUM_8197F(x) \
+ (((x) >> BIT_SHIFT_BLK_DESC_NUM_8197F) & BIT_MASK_BLK_DESC_NUM_8197F)
+#define BIT_SET_BLK_DESC_NUM_8197F(x, v) \
+ (BIT_CLEAR_BLK_DESC_NUM_8197F(x) | BIT_BLK_DESC_NUM_8197F(v))
+
+#define BIT_R_BCN_HEAD_SEL_8197F BIT(3)
+#define BIT_R_EN_BCN_SW_HEAD_SEL_8197F BIT(2)
+#define BIT_LLT_DBG_SEL_8197F BIT(1)
+#define BIT_AUTO_INIT_LLT_V1_8197F BIT(0)
+
+/* 2 REG_TXDMA_OFFSET_CHK_8197F */
+#define BIT_EM_CHKSUM_FIN_8197F BIT(31)
+#define BIT_EMN_PCIE_DMA_MOD_8197F BIT(30)
+#define BIT_EN_TXQUE_CLR_8197F BIT(29)
+#define BIT_EN_PCIE_FIFO_MODE_8197F BIT(28)
+
+#define BIT_SHIFT_PG_UNDER_TH_V1_8197F 16
+#define BIT_MASK_PG_UNDER_TH_V1_8197F 0xfff
+#define BIT_PG_UNDER_TH_V1_8197F(x) \
+ (((x) & BIT_MASK_PG_UNDER_TH_V1_8197F) \
+ << BIT_SHIFT_PG_UNDER_TH_V1_8197F)
+#define BITS_PG_UNDER_TH_V1_8197F \
+ (BIT_MASK_PG_UNDER_TH_V1_8197F << BIT_SHIFT_PG_UNDER_TH_V1_8197F)
+#define BIT_CLEAR_PG_UNDER_TH_V1_8197F(x) ((x) & (~BITS_PG_UNDER_TH_V1_8197F))
+#define BIT_GET_PG_UNDER_TH_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8197F) & \
+ BIT_MASK_PG_UNDER_TH_V1_8197F)
+#define BIT_SET_PG_UNDER_TH_V1_8197F(x, v) \
+ (BIT_CLEAR_PG_UNDER_TH_V1_8197F(x) | BIT_PG_UNDER_TH_V1_8197F(v))
+
+#define BIT_EN_RESET_RESTORE_H2C_8197F BIT(15)
+#define BIT_SDIO_TDE_FINISH_8197F BIT(14)
+#define BIT_SDIO_TXDESC_CHKSUM_EN_8197F BIT(13)
+#define BIT_RST_RDPTR_8197F BIT(12)
+#define BIT_RST_WRPTR_8197F BIT(11)
+#define BIT_CHK_PG_TH_EN_8197F BIT(10)
+#define BIT_DROP_DATA_EN_8197F BIT(9)
+#define BIT_CHECK_OFFSET_EN_8197F BIT(8)
+
+#define BIT_SHIFT_CHECK_OFFSET_8197F 0
+#define BIT_MASK_CHECK_OFFSET_8197F 0xff
+#define BIT_CHECK_OFFSET_8197F(x) \
+ (((x) & BIT_MASK_CHECK_OFFSET_8197F) << BIT_SHIFT_CHECK_OFFSET_8197F)
+#define BITS_CHECK_OFFSET_8197F \
+ (BIT_MASK_CHECK_OFFSET_8197F << BIT_SHIFT_CHECK_OFFSET_8197F)
+#define BIT_CLEAR_CHECK_OFFSET_8197F(x) ((x) & (~BITS_CHECK_OFFSET_8197F))
+#define BIT_GET_CHECK_OFFSET_8197F(x) \
+ (((x) >> BIT_SHIFT_CHECK_OFFSET_8197F) & BIT_MASK_CHECK_OFFSET_8197F)
+#define BIT_SET_CHECK_OFFSET_8197F(x, v) \
+ (BIT_CLEAR_CHECK_OFFSET_8197F(x) | BIT_CHECK_OFFSET_8197F(v))
+
+/* 2 REG_TXDMA_STATUS_8197F */
+#define BIT_HI_OQT_UDN_8197F BIT(17)
+#define BIT_HI_OQT_OVF_8197F BIT(16)
+#define BIT_PAYLOAD_CHKSUM_ERR_8197F BIT(15)
+#define BIT_PAYLOAD_UDN_8197F BIT(14)
+#define BIT_PAYLOAD_OVF_8197F BIT(13)
+#define BIT_DSC_CHKSUM_FAIL_8197F BIT(12)
+#define BIT_UNKNOWN_QSEL_8197F BIT(11)
+#define BIT_EP_QSEL_DIFF_8197F BIT(10)
+#define BIT_TX_OFFS_UNMATCH_8197F BIT(9)
+#define BIT_TXOQT_UDN_8197F BIT(8)
+#define BIT_TXOQT_OVF_8197F BIT(7)
+#define BIT_TXDMA_SFF_UDN_8197F BIT(6)
+#define BIT_TXDMA_SFF_OVF_8197F BIT(5)
+#define BIT_LLT_NULL_PG_8197F BIT(4)
+#define BIT_PAGE_UDN_8197F BIT(3)
+#define BIT_PAGE_OVF_8197F BIT(2)
+#define BIT_TXFF_PG_UDN_8197F BIT(1)
+#define BIT_TXFF_PG_OVF_8197F BIT(0)
+
+/* 2 REG_TX_DMA_DBG_8197F */
+
+/* 2 REG_TQPNT1_8197F */
+
+#define BIT_SHIFT_HPQ_HIGH_TH_V1_8197F 16
+#define BIT_MASK_HPQ_HIGH_TH_V1_8197F 0xfff
+#define BIT_HPQ_HIGH_TH_V1_8197F(x) \
+ (((x) & BIT_MASK_HPQ_HIGH_TH_V1_8197F) \
+ << BIT_SHIFT_HPQ_HIGH_TH_V1_8197F)
+#define BITS_HPQ_HIGH_TH_V1_8197F \
+ (BIT_MASK_HPQ_HIGH_TH_V1_8197F << BIT_SHIFT_HPQ_HIGH_TH_V1_8197F)
+#define BIT_CLEAR_HPQ_HIGH_TH_V1_8197F(x) ((x) & (~BITS_HPQ_HIGH_TH_V1_8197F))
+#define BIT_GET_HPQ_HIGH_TH_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1_8197F) & \
+ BIT_MASK_HPQ_HIGH_TH_V1_8197F)
+#define BIT_SET_HPQ_HIGH_TH_V1_8197F(x, v) \
+ (BIT_CLEAR_HPQ_HIGH_TH_V1_8197F(x) | BIT_HPQ_HIGH_TH_V1_8197F(v))
+
+#define BIT_SHIFT_HPQ_LOW_TH_V1_8197F 0
+#define BIT_MASK_HPQ_LOW_TH_V1_8197F 0xfff
+#define BIT_HPQ_LOW_TH_V1_8197F(x) \
+ (((x) & BIT_MASK_HPQ_LOW_TH_V1_8197F) << BIT_SHIFT_HPQ_LOW_TH_V1_8197F)
+#define BITS_HPQ_LOW_TH_V1_8197F \
+ (BIT_MASK_HPQ_LOW_TH_V1_8197F << BIT_SHIFT_HPQ_LOW_TH_V1_8197F)
+#define BIT_CLEAR_HPQ_LOW_TH_V1_8197F(x) ((x) & (~BITS_HPQ_LOW_TH_V1_8197F))
+#define BIT_GET_HPQ_LOW_TH_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_HPQ_LOW_TH_V1_8197F) & BIT_MASK_HPQ_LOW_TH_V1_8197F)
+#define BIT_SET_HPQ_LOW_TH_V1_8197F(x, v) \
+ (BIT_CLEAR_HPQ_LOW_TH_V1_8197F(x) | BIT_HPQ_LOW_TH_V1_8197F(v))
+
+/* 2 REG_TQPNT2_8197F */
+
+#define BIT_SHIFT_NPQ_HIGH_TH_V1_8197F 16
+#define BIT_MASK_NPQ_HIGH_TH_V1_8197F 0xfff
+#define BIT_NPQ_HIGH_TH_V1_8197F(x) \
+ (((x) & BIT_MASK_NPQ_HIGH_TH_V1_8197F) \
+ << BIT_SHIFT_NPQ_HIGH_TH_V1_8197F)
+#define BITS_NPQ_HIGH_TH_V1_8197F \
+ (BIT_MASK_NPQ_HIGH_TH_V1_8197F << BIT_SHIFT_NPQ_HIGH_TH_V1_8197F)
+#define BIT_CLEAR_NPQ_HIGH_TH_V1_8197F(x) ((x) & (~BITS_NPQ_HIGH_TH_V1_8197F))
+#define BIT_GET_NPQ_HIGH_TH_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1_8197F) & \
+ BIT_MASK_NPQ_HIGH_TH_V1_8197F)
+#define BIT_SET_NPQ_HIGH_TH_V1_8197F(x, v) \
+ (BIT_CLEAR_NPQ_HIGH_TH_V1_8197F(x) | BIT_NPQ_HIGH_TH_V1_8197F(v))
+
+#define BIT_SHIFT_NPQ_LOW_TH_V1_8197F 0
+#define BIT_MASK_NPQ_LOW_TH_V1_8197F 0xfff
+#define BIT_NPQ_LOW_TH_V1_8197F(x) \
+ (((x) & BIT_MASK_NPQ_LOW_TH_V1_8197F) << BIT_SHIFT_NPQ_LOW_TH_V1_8197F)
+#define BITS_NPQ_LOW_TH_V1_8197F \
+ (BIT_MASK_NPQ_LOW_TH_V1_8197F << BIT_SHIFT_NPQ_LOW_TH_V1_8197F)
+#define BIT_CLEAR_NPQ_LOW_TH_V1_8197F(x) ((x) & (~BITS_NPQ_LOW_TH_V1_8197F))
+#define BIT_GET_NPQ_LOW_TH_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_NPQ_LOW_TH_V1_8197F) & BIT_MASK_NPQ_LOW_TH_V1_8197F)
+#define BIT_SET_NPQ_LOW_TH_V1_8197F(x, v) \
+ (BIT_CLEAR_NPQ_LOW_TH_V1_8197F(x) | BIT_NPQ_LOW_TH_V1_8197F(v))
+
+/* 2 REG_TQPNT3_8197F */
+
+#define BIT_SHIFT_LPQ_HIGH_TH_V1_8197F 16
+#define BIT_MASK_LPQ_HIGH_TH_V1_8197F 0xfff
+#define BIT_LPQ_HIGH_TH_V1_8197F(x) \
+ (((x) & BIT_MASK_LPQ_HIGH_TH_V1_8197F) \
+ << BIT_SHIFT_LPQ_HIGH_TH_V1_8197F)
+#define BITS_LPQ_HIGH_TH_V1_8197F \
+ (BIT_MASK_LPQ_HIGH_TH_V1_8197F << BIT_SHIFT_LPQ_HIGH_TH_V1_8197F)
+#define BIT_CLEAR_LPQ_HIGH_TH_V1_8197F(x) ((x) & (~BITS_LPQ_HIGH_TH_V1_8197F))
+#define BIT_GET_LPQ_HIGH_TH_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1_8197F) & \
+ BIT_MASK_LPQ_HIGH_TH_V1_8197F)
+#define BIT_SET_LPQ_HIGH_TH_V1_8197F(x, v) \
+ (BIT_CLEAR_LPQ_HIGH_TH_V1_8197F(x) | BIT_LPQ_HIGH_TH_V1_8197F(v))
+
+#define BIT_SHIFT_LPQ_LOW_TH_V1_8197F 0
+#define BIT_MASK_LPQ_LOW_TH_V1_8197F 0xfff
+#define BIT_LPQ_LOW_TH_V1_8197F(x) \
+ (((x) & BIT_MASK_LPQ_LOW_TH_V1_8197F) << BIT_SHIFT_LPQ_LOW_TH_V1_8197F)
+#define BITS_LPQ_LOW_TH_V1_8197F \
+ (BIT_MASK_LPQ_LOW_TH_V1_8197F << BIT_SHIFT_LPQ_LOW_TH_V1_8197F)
+#define BIT_CLEAR_LPQ_LOW_TH_V1_8197F(x) ((x) & (~BITS_LPQ_LOW_TH_V1_8197F))
+#define BIT_GET_LPQ_LOW_TH_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_LPQ_LOW_TH_V1_8197F) & BIT_MASK_LPQ_LOW_TH_V1_8197F)
+#define BIT_SET_LPQ_LOW_TH_V1_8197F(x, v) \
+ (BIT_CLEAR_LPQ_LOW_TH_V1_8197F(x) | BIT_LPQ_LOW_TH_V1_8197F(v))
+
+/* 2 REG_TQPNT4_8197F */
+
+#define BIT_SHIFT_EXQ_HIGH_TH_V1_8197F 16
+#define BIT_MASK_EXQ_HIGH_TH_V1_8197F 0xfff
+#define BIT_EXQ_HIGH_TH_V1_8197F(x) \
+ (((x) & BIT_MASK_EXQ_HIGH_TH_V1_8197F) \
+ << BIT_SHIFT_EXQ_HIGH_TH_V1_8197F)
+#define BITS_EXQ_HIGH_TH_V1_8197F \
+ (BIT_MASK_EXQ_HIGH_TH_V1_8197F << BIT_SHIFT_EXQ_HIGH_TH_V1_8197F)
+#define BIT_CLEAR_EXQ_HIGH_TH_V1_8197F(x) ((x) & (~BITS_EXQ_HIGH_TH_V1_8197F))
+#define BIT_GET_EXQ_HIGH_TH_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1_8197F) & \
+ BIT_MASK_EXQ_HIGH_TH_V1_8197F)
+#define BIT_SET_EXQ_HIGH_TH_V1_8197F(x, v) \
+ (BIT_CLEAR_EXQ_HIGH_TH_V1_8197F(x) | BIT_EXQ_HIGH_TH_V1_8197F(v))
+
+#define BIT_SHIFT_EXQ_LOW_TH_V1_8197F 0
+#define BIT_MASK_EXQ_LOW_TH_V1_8197F 0xfff
+#define BIT_EXQ_LOW_TH_V1_8197F(x) \
+ (((x) & BIT_MASK_EXQ_LOW_TH_V1_8197F) << BIT_SHIFT_EXQ_LOW_TH_V1_8197F)
+#define BITS_EXQ_LOW_TH_V1_8197F \
+ (BIT_MASK_EXQ_LOW_TH_V1_8197F << BIT_SHIFT_EXQ_LOW_TH_V1_8197F)
+#define BIT_CLEAR_EXQ_LOW_TH_V1_8197F(x) ((x) & (~BITS_EXQ_LOW_TH_V1_8197F))
+#define BIT_GET_EXQ_LOW_TH_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_EXQ_LOW_TH_V1_8197F) & BIT_MASK_EXQ_LOW_TH_V1_8197F)
+#define BIT_SET_EXQ_LOW_TH_V1_8197F(x, v) \
+ (BIT_CLEAR_EXQ_LOW_TH_V1_8197F(x) | BIT_EXQ_LOW_TH_V1_8197F(v))
+
+/* 2 REG_RQPN_CTRL_1_8197F */
+
+#define BIT_SHIFT_TXPKTNUM_H_8197F 16
+#define BIT_MASK_TXPKTNUM_H_8197F 0xffff
+#define BIT_TXPKTNUM_H_8197F(x) \
+ (((x) & BIT_MASK_TXPKTNUM_H_8197F) << BIT_SHIFT_TXPKTNUM_H_8197F)
+#define BITS_TXPKTNUM_H_8197F \
+ (BIT_MASK_TXPKTNUM_H_8197F << BIT_SHIFT_TXPKTNUM_H_8197F)
+#define BIT_CLEAR_TXPKTNUM_H_8197F(x) ((x) & (~BITS_TXPKTNUM_H_8197F))
+#define BIT_GET_TXPKTNUM_H_8197F(x) \
+ (((x) >> BIT_SHIFT_TXPKTNUM_H_8197F) & BIT_MASK_TXPKTNUM_H_8197F)
+#define BIT_SET_TXPKTNUM_H_8197F(x, v) \
+ (BIT_CLEAR_TXPKTNUM_H_8197F(x) | BIT_TXPKTNUM_H_8197F(v))
+
+#define BIT_SHIFT_TXPKTNUM_H_V1_8197F 0
+#define BIT_MASK_TXPKTNUM_H_V1_8197F 0xffff
+#define BIT_TXPKTNUM_H_V1_8197F(x) \
+ (((x) & BIT_MASK_TXPKTNUM_H_V1_8197F) << BIT_SHIFT_TXPKTNUM_H_V1_8197F)
+#define BITS_TXPKTNUM_H_V1_8197F \
+ (BIT_MASK_TXPKTNUM_H_V1_8197F << BIT_SHIFT_TXPKTNUM_H_V1_8197F)
+#define BIT_CLEAR_TXPKTNUM_H_V1_8197F(x) ((x) & (~BITS_TXPKTNUM_H_V1_8197F))
+#define BIT_GET_TXPKTNUM_H_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_TXPKTNUM_H_V1_8197F) & BIT_MASK_TXPKTNUM_H_V1_8197F)
+#define BIT_SET_TXPKTNUM_H_V1_8197F(x, v) \
+ (BIT_CLEAR_TXPKTNUM_H_V1_8197F(x) | BIT_TXPKTNUM_H_V1_8197F(v))
+
+/* 2 REG_RQPN_CTRL_2_8197F */
+#define BIT_LD_RQPN_8197F BIT(31)
+#define BIT_EXQ_PUBLIC_DIS_V1_8197F BIT(19)
+#define BIT_NPQ_PUBLIC_DIS_V1_8197F BIT(18)
+#define BIT_LPQ_PUBLIC_DIS_V1_8197F BIT(17)
+#define BIT_HPQ_PUBLIC_DIS_V1_8197F BIT(16)
+
+/* 2 REG_FIFOPAGE_INFO_1_8197F */
+
+#define BIT_SHIFT_HPQ_AVAL_PG_V1_8197F 16
+#define BIT_MASK_HPQ_AVAL_PG_V1_8197F 0xfff
+#define BIT_HPQ_AVAL_PG_V1_8197F(x) \
+ (((x) & BIT_MASK_HPQ_AVAL_PG_V1_8197F) \
+ << BIT_SHIFT_HPQ_AVAL_PG_V1_8197F)
+#define BITS_HPQ_AVAL_PG_V1_8197F \
+ (BIT_MASK_HPQ_AVAL_PG_V1_8197F << BIT_SHIFT_HPQ_AVAL_PG_V1_8197F)
+#define BIT_CLEAR_HPQ_AVAL_PG_V1_8197F(x) ((x) & (~BITS_HPQ_AVAL_PG_V1_8197F))
+#define BIT_GET_HPQ_AVAL_PG_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1_8197F) & \
+ BIT_MASK_HPQ_AVAL_PG_V1_8197F)
+#define BIT_SET_HPQ_AVAL_PG_V1_8197F(x, v) \
+ (BIT_CLEAR_HPQ_AVAL_PG_V1_8197F(x) | BIT_HPQ_AVAL_PG_V1_8197F(v))
+
+#define BIT_SHIFT_HPQ_V1_8197F 0
+#define BIT_MASK_HPQ_V1_8197F 0xfff
+#define BIT_HPQ_V1_8197F(x) \
+ (((x) & BIT_MASK_HPQ_V1_8197F) << BIT_SHIFT_HPQ_V1_8197F)
+#define BITS_HPQ_V1_8197F (BIT_MASK_HPQ_V1_8197F << BIT_SHIFT_HPQ_V1_8197F)
+#define BIT_CLEAR_HPQ_V1_8197F(x) ((x) & (~BITS_HPQ_V1_8197F))
+#define BIT_GET_HPQ_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_HPQ_V1_8197F) & BIT_MASK_HPQ_V1_8197F)
+#define BIT_SET_HPQ_V1_8197F(x, v) \
+ (BIT_CLEAR_HPQ_V1_8197F(x) | BIT_HPQ_V1_8197F(v))
+
+/* 2 REG_FIFOPAGE_INFO_2_8197F */
+
+#define BIT_SHIFT_LPQ_AVAL_PG_V1_8197F 16
+#define BIT_MASK_LPQ_AVAL_PG_V1_8197F 0xfff
+#define BIT_LPQ_AVAL_PG_V1_8197F(x) \
+ (((x) & BIT_MASK_LPQ_AVAL_PG_V1_8197F) \
+ << BIT_SHIFT_LPQ_AVAL_PG_V1_8197F)
+#define BITS_LPQ_AVAL_PG_V1_8197F \
+ (BIT_MASK_LPQ_AVAL_PG_V1_8197F << BIT_SHIFT_LPQ_AVAL_PG_V1_8197F)
+#define BIT_CLEAR_LPQ_AVAL_PG_V1_8197F(x) ((x) & (~BITS_LPQ_AVAL_PG_V1_8197F))
+#define BIT_GET_LPQ_AVAL_PG_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1_8197F) & \
+ BIT_MASK_LPQ_AVAL_PG_V1_8197F)
+#define BIT_SET_LPQ_AVAL_PG_V1_8197F(x, v) \
+ (BIT_CLEAR_LPQ_AVAL_PG_V1_8197F(x) | BIT_LPQ_AVAL_PG_V1_8197F(v))
+
+#define BIT_SHIFT_LPQ_V1_8197F 0
+#define BIT_MASK_LPQ_V1_8197F 0xfff
+#define BIT_LPQ_V1_8197F(x) \
+ (((x) & BIT_MASK_LPQ_V1_8197F) << BIT_SHIFT_LPQ_V1_8197F)
+#define BITS_LPQ_V1_8197F (BIT_MASK_LPQ_V1_8197F << BIT_SHIFT_LPQ_V1_8197F)
+#define BIT_CLEAR_LPQ_V1_8197F(x) ((x) & (~BITS_LPQ_V1_8197F))
+#define BIT_GET_LPQ_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_LPQ_V1_8197F) & BIT_MASK_LPQ_V1_8197F)
+#define BIT_SET_LPQ_V1_8197F(x, v) \
+ (BIT_CLEAR_LPQ_V1_8197F(x) | BIT_LPQ_V1_8197F(v))
+
+/* 2 REG_FIFOPAGE_INFO_3_8197F */
+
+#define BIT_SHIFT_NPQ_AVAL_PG_V1_8197F 16
+#define BIT_MASK_NPQ_AVAL_PG_V1_8197F 0xfff
+#define BIT_NPQ_AVAL_PG_V1_8197F(x) \
+ (((x) & BIT_MASK_NPQ_AVAL_PG_V1_8197F) \
+ << BIT_SHIFT_NPQ_AVAL_PG_V1_8197F)
+#define BITS_NPQ_AVAL_PG_V1_8197F \
+ (BIT_MASK_NPQ_AVAL_PG_V1_8197F << BIT_SHIFT_NPQ_AVAL_PG_V1_8197F)
+#define BIT_CLEAR_NPQ_AVAL_PG_V1_8197F(x) ((x) & (~BITS_NPQ_AVAL_PG_V1_8197F))
+#define BIT_GET_NPQ_AVAL_PG_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1_8197F) & \
+ BIT_MASK_NPQ_AVAL_PG_V1_8197F)
+#define BIT_SET_NPQ_AVAL_PG_V1_8197F(x, v) \
+ (BIT_CLEAR_NPQ_AVAL_PG_V1_8197F(x) | BIT_NPQ_AVAL_PG_V1_8197F(v))
+
+#define BIT_SHIFT_NPQ_V1_8197F 0
+#define BIT_MASK_NPQ_V1_8197F 0xfff
+#define BIT_NPQ_V1_8197F(x) \
+ (((x) & BIT_MASK_NPQ_V1_8197F) << BIT_SHIFT_NPQ_V1_8197F)
+#define BITS_NPQ_V1_8197F (BIT_MASK_NPQ_V1_8197F << BIT_SHIFT_NPQ_V1_8197F)
+#define BIT_CLEAR_NPQ_V1_8197F(x) ((x) & (~BITS_NPQ_V1_8197F))
+#define BIT_GET_NPQ_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_NPQ_V1_8197F) & BIT_MASK_NPQ_V1_8197F)
+#define BIT_SET_NPQ_V1_8197F(x, v) \
+ (BIT_CLEAR_NPQ_V1_8197F(x) | BIT_NPQ_V1_8197F(v))
+
+/* 2 REG_FIFOPAGE_INFO_4_8197F */
+
+#define BIT_SHIFT_EXQ_AVAL_PG_V1_8197F 16
+#define BIT_MASK_EXQ_AVAL_PG_V1_8197F 0xfff
+#define BIT_EXQ_AVAL_PG_V1_8197F(x) \
+ (((x) & BIT_MASK_EXQ_AVAL_PG_V1_8197F) \
+ << BIT_SHIFT_EXQ_AVAL_PG_V1_8197F)
+#define BITS_EXQ_AVAL_PG_V1_8197F \
+ (BIT_MASK_EXQ_AVAL_PG_V1_8197F << BIT_SHIFT_EXQ_AVAL_PG_V1_8197F)
+#define BIT_CLEAR_EXQ_AVAL_PG_V1_8197F(x) ((x) & (~BITS_EXQ_AVAL_PG_V1_8197F))
+#define BIT_GET_EXQ_AVAL_PG_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1_8197F) & \
+ BIT_MASK_EXQ_AVAL_PG_V1_8197F)
+#define BIT_SET_EXQ_AVAL_PG_V1_8197F(x, v) \
+ (BIT_CLEAR_EXQ_AVAL_PG_V1_8197F(x) | BIT_EXQ_AVAL_PG_V1_8197F(v))
+
+#define BIT_SHIFT_EXQ_V1_8197F 0
+#define BIT_MASK_EXQ_V1_8197F 0xfff
+#define BIT_EXQ_V1_8197F(x) \
+ (((x) & BIT_MASK_EXQ_V1_8197F) << BIT_SHIFT_EXQ_V1_8197F)
+#define BITS_EXQ_V1_8197F (BIT_MASK_EXQ_V1_8197F << BIT_SHIFT_EXQ_V1_8197F)
+#define BIT_CLEAR_EXQ_V1_8197F(x) ((x) & (~BITS_EXQ_V1_8197F))
+#define BIT_GET_EXQ_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_EXQ_V1_8197F) & BIT_MASK_EXQ_V1_8197F)
+#define BIT_SET_EXQ_V1_8197F(x, v) \
+ (BIT_CLEAR_EXQ_V1_8197F(x) | BIT_EXQ_V1_8197F(v))
+
+/* 2 REG_FIFOPAGE_INFO_5_8197F */
+
+#define BIT_SHIFT_PUBQ_AVAL_PG_V1_8197F 16
+#define BIT_MASK_PUBQ_AVAL_PG_V1_8197F 0xfff
+#define BIT_PUBQ_AVAL_PG_V1_8197F(x) \
+ (((x) & BIT_MASK_PUBQ_AVAL_PG_V1_8197F) \
+ << BIT_SHIFT_PUBQ_AVAL_PG_V1_8197F)
+#define BITS_PUBQ_AVAL_PG_V1_8197F \
+ (BIT_MASK_PUBQ_AVAL_PG_V1_8197F << BIT_SHIFT_PUBQ_AVAL_PG_V1_8197F)
+#define BIT_CLEAR_PUBQ_AVAL_PG_V1_8197F(x) ((x) & (~BITS_PUBQ_AVAL_PG_V1_8197F))
+#define BIT_GET_PUBQ_AVAL_PG_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1_8197F) & \
+ BIT_MASK_PUBQ_AVAL_PG_V1_8197F)
+#define BIT_SET_PUBQ_AVAL_PG_V1_8197F(x, v) \
+ (BIT_CLEAR_PUBQ_AVAL_PG_V1_8197F(x) | BIT_PUBQ_AVAL_PG_V1_8197F(v))
+
+#define BIT_SHIFT_PUBQ_V1_8197F 0
+#define BIT_MASK_PUBQ_V1_8197F 0xfff
+#define BIT_PUBQ_V1_8197F(x) \
+ (((x) & BIT_MASK_PUBQ_V1_8197F) << BIT_SHIFT_PUBQ_V1_8197F)
+#define BITS_PUBQ_V1_8197F (BIT_MASK_PUBQ_V1_8197F << BIT_SHIFT_PUBQ_V1_8197F)
+#define BIT_CLEAR_PUBQ_V1_8197F(x) ((x) & (~BITS_PUBQ_V1_8197F))
+#define BIT_GET_PUBQ_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_PUBQ_V1_8197F) & BIT_MASK_PUBQ_V1_8197F)
+#define BIT_SET_PUBQ_V1_8197F(x, v) \
+ (BIT_CLEAR_PUBQ_V1_8197F(x) | BIT_PUBQ_V1_8197F(v))
+
+/* 2 REG_H2C_HEAD_8197F */
+
+#define BIT_SHIFT_H2C_HEAD_8197F 0
+#define BIT_MASK_H2C_HEAD_8197F 0x3ffff
+#define BIT_H2C_HEAD_8197F(x) \
+ (((x) & BIT_MASK_H2C_HEAD_8197F) << BIT_SHIFT_H2C_HEAD_8197F)
+#define BITS_H2C_HEAD_8197F \
+ (BIT_MASK_H2C_HEAD_8197F << BIT_SHIFT_H2C_HEAD_8197F)
+#define BIT_CLEAR_H2C_HEAD_8197F(x) ((x) & (~BITS_H2C_HEAD_8197F))
+#define BIT_GET_H2C_HEAD_8197F(x) \
+ (((x) >> BIT_SHIFT_H2C_HEAD_8197F) & BIT_MASK_H2C_HEAD_8197F)
+#define BIT_SET_H2C_HEAD_8197F(x, v) \
+ (BIT_CLEAR_H2C_HEAD_8197F(x) | BIT_H2C_HEAD_8197F(v))
+
+/* 2 REG_H2C_TAIL_8197F */
+
+#define BIT_SHIFT_H2C_TAIL_8197F 0
+#define BIT_MASK_H2C_TAIL_8197F 0x3ffff
+#define BIT_H2C_TAIL_8197F(x) \
+ (((x) & BIT_MASK_H2C_TAIL_8197F) << BIT_SHIFT_H2C_TAIL_8197F)
+#define BITS_H2C_TAIL_8197F \
+ (BIT_MASK_H2C_TAIL_8197F << BIT_SHIFT_H2C_TAIL_8197F)
+#define BIT_CLEAR_H2C_TAIL_8197F(x) ((x) & (~BITS_H2C_TAIL_8197F))
+#define BIT_GET_H2C_TAIL_8197F(x) \
+ (((x) >> BIT_SHIFT_H2C_TAIL_8197F) & BIT_MASK_H2C_TAIL_8197F)
+#define BIT_SET_H2C_TAIL_8197F(x, v) \
+ (BIT_CLEAR_H2C_TAIL_8197F(x) | BIT_H2C_TAIL_8197F(v))
+
+/* 2 REG_H2C_READ_ADDR_8197F */
+
+#define BIT_SHIFT_H2C_READ_ADDR_8197F 0
+#define BIT_MASK_H2C_READ_ADDR_8197F 0x3ffff
+#define BIT_H2C_READ_ADDR_8197F(x) \
+ (((x) & BIT_MASK_H2C_READ_ADDR_8197F) << BIT_SHIFT_H2C_READ_ADDR_8197F)
+#define BITS_H2C_READ_ADDR_8197F \
+ (BIT_MASK_H2C_READ_ADDR_8197F << BIT_SHIFT_H2C_READ_ADDR_8197F)
+#define BIT_CLEAR_H2C_READ_ADDR_8197F(x) ((x) & (~BITS_H2C_READ_ADDR_8197F))
+#define BIT_GET_H2C_READ_ADDR_8197F(x) \
+ (((x) >> BIT_SHIFT_H2C_READ_ADDR_8197F) & BIT_MASK_H2C_READ_ADDR_8197F)
+#define BIT_SET_H2C_READ_ADDR_8197F(x, v) \
+ (BIT_CLEAR_H2C_READ_ADDR_8197F(x) | BIT_H2C_READ_ADDR_8197F(v))
+
+/* 2 REG_H2C_WR_ADDR_8197F */
+
+#define BIT_SHIFT_H2C_WR_ADDR_8197F 0
+#define BIT_MASK_H2C_WR_ADDR_8197F 0x3ffff
+#define BIT_H2C_WR_ADDR_8197F(x) \
+ (((x) & BIT_MASK_H2C_WR_ADDR_8197F) << BIT_SHIFT_H2C_WR_ADDR_8197F)
+#define BITS_H2C_WR_ADDR_8197F \
+ (BIT_MASK_H2C_WR_ADDR_8197F << BIT_SHIFT_H2C_WR_ADDR_8197F)
+#define BIT_CLEAR_H2C_WR_ADDR_8197F(x) ((x) & (~BITS_H2C_WR_ADDR_8197F))
+#define BIT_GET_H2C_WR_ADDR_8197F(x) \
+ (((x) >> BIT_SHIFT_H2C_WR_ADDR_8197F) & BIT_MASK_H2C_WR_ADDR_8197F)
+#define BIT_SET_H2C_WR_ADDR_8197F(x, v) \
+ (BIT_CLEAR_H2C_WR_ADDR_8197F(x) | BIT_H2C_WR_ADDR_8197F(v))
+
+/* 2 REG_H2C_INFO_8197F */
+#define BIT_EXQ_EN_PUBLIC_LIMIT_8197F BIT(11)
+#define BIT_NPQ_EN_PUBLIC_LIMIT_8197F BIT(10)
+#define BIT_LPQ_EN_PUBLIC_LIMIT_8197F BIT(9)
+#define BIT_HPQ_EN_PUBLIC_LIMIT_8197F BIT(8)
+#define BIT_H2C_SPACE_VLD_8197F BIT(3)
+#define BIT_H2C_WR_ADDR_RST_8197F BIT(2)
+
+#define BIT_SHIFT_H2C_LEN_SEL_8197F 0
+#define BIT_MASK_H2C_LEN_SEL_8197F 0x3
+#define BIT_H2C_LEN_SEL_8197F(x) \
+ (((x) & BIT_MASK_H2C_LEN_SEL_8197F) << BIT_SHIFT_H2C_LEN_SEL_8197F)
+#define BITS_H2C_LEN_SEL_8197F \
+ (BIT_MASK_H2C_LEN_SEL_8197F << BIT_SHIFT_H2C_LEN_SEL_8197F)
+#define BIT_CLEAR_H2C_LEN_SEL_8197F(x) ((x) & (~BITS_H2C_LEN_SEL_8197F))
+#define BIT_GET_H2C_LEN_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_H2C_LEN_SEL_8197F) & BIT_MASK_H2C_LEN_SEL_8197F)
+#define BIT_SET_H2C_LEN_SEL_8197F(x, v) \
+ (BIT_CLEAR_H2C_LEN_SEL_8197F(x) | BIT_H2C_LEN_SEL_8197F(v))
+
+#define BIT_SHIFT_VI_PUB_LIMIT_8197F 16
+#define BIT_MASK_VI_PUB_LIMIT_8197F 0xfff
+#define BIT_VI_PUB_LIMIT_8197F(x) \
+ (((x) & BIT_MASK_VI_PUB_LIMIT_8197F) << BIT_SHIFT_VI_PUB_LIMIT_8197F)
+#define BITS_VI_PUB_LIMIT_8197F \
+ (BIT_MASK_VI_PUB_LIMIT_8197F << BIT_SHIFT_VI_PUB_LIMIT_8197F)
+#define BIT_CLEAR_VI_PUB_LIMIT_8197F(x) ((x) & (~BITS_VI_PUB_LIMIT_8197F))
+#define BIT_GET_VI_PUB_LIMIT_8197F(x) \
+ (((x) >> BIT_SHIFT_VI_PUB_LIMIT_8197F) & BIT_MASK_VI_PUB_LIMIT_8197F)
+#define BIT_SET_VI_PUB_LIMIT_8197F(x, v) \
+ (BIT_CLEAR_VI_PUB_LIMIT_8197F(x) | BIT_VI_PUB_LIMIT_8197F(v))
+
+#define BIT_SHIFT_VO_PUB_LIMIT_8197F 0
+#define BIT_MASK_VO_PUB_LIMIT_8197F 0xfff
+#define BIT_VO_PUB_LIMIT_8197F(x) \
+ (((x) & BIT_MASK_VO_PUB_LIMIT_8197F) << BIT_SHIFT_VO_PUB_LIMIT_8197F)
+#define BITS_VO_PUB_LIMIT_8197F \
+ (BIT_MASK_VO_PUB_LIMIT_8197F << BIT_SHIFT_VO_PUB_LIMIT_8197F)
+#define BIT_CLEAR_VO_PUB_LIMIT_8197F(x) ((x) & (~BITS_VO_PUB_LIMIT_8197F))
+#define BIT_GET_VO_PUB_LIMIT_8197F(x) \
+ (((x) >> BIT_SHIFT_VO_PUB_LIMIT_8197F) & BIT_MASK_VO_PUB_LIMIT_8197F)
+#define BIT_SET_VO_PUB_LIMIT_8197F(x, v) \
+ (BIT_CLEAR_VO_PUB_LIMIT_8197F(x) | BIT_VO_PUB_LIMIT_8197F(v))
+
+#define BIT_SHIFT_BK_PUB_LIMIT_8197F 16
+#define BIT_MASK_BK_PUB_LIMIT_8197F 0xfff
+#define BIT_BK_PUB_LIMIT_8197F(x) \
+ (((x) & BIT_MASK_BK_PUB_LIMIT_8197F) << BIT_SHIFT_BK_PUB_LIMIT_8197F)
+#define BITS_BK_PUB_LIMIT_8197F \
+ (BIT_MASK_BK_PUB_LIMIT_8197F << BIT_SHIFT_BK_PUB_LIMIT_8197F)
+#define BIT_CLEAR_BK_PUB_LIMIT_8197F(x) ((x) & (~BITS_BK_PUB_LIMIT_8197F))
+#define BIT_GET_BK_PUB_LIMIT_8197F(x) \
+ (((x) >> BIT_SHIFT_BK_PUB_LIMIT_8197F) & BIT_MASK_BK_PUB_LIMIT_8197F)
+#define BIT_SET_BK_PUB_LIMIT_8197F(x, v) \
+ (BIT_CLEAR_BK_PUB_LIMIT_8197F(x) | BIT_BK_PUB_LIMIT_8197F(v))
+
+#define BIT_SHIFT_BE_PUB_LIMIT_8197F 0
+#define BIT_MASK_BE_PUB_LIMIT_8197F 0xfff
+#define BIT_BE_PUB_LIMIT_8197F(x) \
+ (((x) & BIT_MASK_BE_PUB_LIMIT_8197F) << BIT_SHIFT_BE_PUB_LIMIT_8197F)
+#define BITS_BE_PUB_LIMIT_8197F \
+ (BIT_MASK_BE_PUB_LIMIT_8197F << BIT_SHIFT_BE_PUB_LIMIT_8197F)
+#define BIT_CLEAR_BE_PUB_LIMIT_8197F(x) ((x) & (~BITS_BE_PUB_LIMIT_8197F))
+#define BIT_GET_BE_PUB_LIMIT_8197F(x) \
+ (((x) >> BIT_SHIFT_BE_PUB_LIMIT_8197F) & BIT_MASK_BE_PUB_LIMIT_8197F)
+#define BIT_SET_BE_PUB_LIMIT_8197F(x, v) \
+ (BIT_CLEAR_BE_PUB_LIMIT_8197F(x) | BIT_BE_PUB_LIMIT_8197F(v))
+
+/* 2 REG_RXDMA_AGG_PG_TH_8197F */
+#define BIT_DMA_STORE_MODE_8197F BIT(31)
+#define BIT_EN_FW_ADD_8197F BIT(30)
+#define BIT_EN_PRE_CALC_8197F BIT(29)
+#define BIT_RXAGG_SW_EN_8197F BIT(28)
+
+#define BIT_SHIFT_PKT_NUM_WOL_8197F 16
+#define BIT_MASK_PKT_NUM_WOL_8197F 0xff
+#define BIT_PKT_NUM_WOL_8197F(x) \
+ (((x) & BIT_MASK_PKT_NUM_WOL_8197F) << BIT_SHIFT_PKT_NUM_WOL_8197F)
+#define BITS_PKT_NUM_WOL_8197F \
+ (BIT_MASK_PKT_NUM_WOL_8197F << BIT_SHIFT_PKT_NUM_WOL_8197F)
+#define BIT_CLEAR_PKT_NUM_WOL_8197F(x) ((x) & (~BITS_PKT_NUM_WOL_8197F))
+#define BIT_GET_PKT_NUM_WOL_8197F(x) \
+ (((x) >> BIT_SHIFT_PKT_NUM_WOL_8197F) & BIT_MASK_PKT_NUM_WOL_8197F)
+#define BIT_SET_PKT_NUM_WOL_8197F(x, v) \
+ (BIT_CLEAR_PKT_NUM_WOL_8197F(x) | BIT_PKT_NUM_WOL_8197F(v))
+
+#define BIT_SHIFT_DMA_AGG_TO_V1_8197F 8
+#define BIT_MASK_DMA_AGG_TO_V1_8197F 0xff
+#define BIT_DMA_AGG_TO_V1_8197F(x) \
+ (((x) & BIT_MASK_DMA_AGG_TO_V1_8197F) << BIT_SHIFT_DMA_AGG_TO_V1_8197F)
+#define BITS_DMA_AGG_TO_V1_8197F \
+ (BIT_MASK_DMA_AGG_TO_V1_8197F << BIT_SHIFT_DMA_AGG_TO_V1_8197F)
+#define BIT_CLEAR_DMA_AGG_TO_V1_8197F(x) ((x) & (~BITS_DMA_AGG_TO_V1_8197F))
+#define BIT_GET_DMA_AGG_TO_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_DMA_AGG_TO_V1_8197F) & BIT_MASK_DMA_AGG_TO_V1_8197F)
+#define BIT_SET_DMA_AGG_TO_V1_8197F(x, v) \
+ (BIT_CLEAR_DMA_AGG_TO_V1_8197F(x) | BIT_DMA_AGG_TO_V1_8197F(v))
+
+#define BIT_SHIFT_RXDMA_AGG_PG_TH_8197F 0
+#define BIT_MASK_RXDMA_AGG_PG_TH_8197F 0xff
+#define BIT_RXDMA_AGG_PG_TH_8197F(x) \
+ (((x) & BIT_MASK_RXDMA_AGG_PG_TH_8197F) \
+ << BIT_SHIFT_RXDMA_AGG_PG_TH_8197F)
+#define BITS_RXDMA_AGG_PG_TH_8197F \
+ (BIT_MASK_RXDMA_AGG_PG_TH_8197F << BIT_SHIFT_RXDMA_AGG_PG_TH_8197F)
+#define BIT_CLEAR_RXDMA_AGG_PG_TH_8197F(x) ((x) & (~BITS_RXDMA_AGG_PG_TH_8197F))
+#define BIT_GET_RXDMA_AGG_PG_TH_8197F(x) \
+ (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_8197F) & \
+ BIT_MASK_RXDMA_AGG_PG_TH_8197F)
+#define BIT_SET_RXDMA_AGG_PG_TH_8197F(x, v) \
+ (BIT_CLEAR_RXDMA_AGG_PG_TH_8197F(x) | BIT_RXDMA_AGG_PG_TH_8197F(v))
+
+/* 2 REG_RXPKT_NUM_8197F */
+
+#define BIT_SHIFT_RXPKT_NUM_8197F 24
+#define BIT_MASK_RXPKT_NUM_8197F 0xff
+#define BIT_RXPKT_NUM_8197F(x) \
+ (((x) & BIT_MASK_RXPKT_NUM_8197F) << BIT_SHIFT_RXPKT_NUM_8197F)
+#define BITS_RXPKT_NUM_8197F \
+ (BIT_MASK_RXPKT_NUM_8197F << BIT_SHIFT_RXPKT_NUM_8197F)
+#define BIT_CLEAR_RXPKT_NUM_8197F(x) ((x) & (~BITS_RXPKT_NUM_8197F))
+#define BIT_GET_RXPKT_NUM_8197F(x) \
+ (((x) >> BIT_SHIFT_RXPKT_NUM_8197F) & BIT_MASK_RXPKT_NUM_8197F)
+#define BIT_SET_RXPKT_NUM_8197F(x, v) \
+ (BIT_CLEAR_RXPKT_NUM_8197F(x) | BIT_RXPKT_NUM_8197F(v))
+
+#define BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8197F 20
+#define BIT_MASK_FW_UPD_RDPTR19_TO_16_8197F 0xf
+#define BIT_FW_UPD_RDPTR19_TO_16_8197F(x) \
+ (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8197F) \
+ << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8197F)
+#define BITS_FW_UPD_RDPTR19_TO_16_8197F \
+ (BIT_MASK_FW_UPD_RDPTR19_TO_16_8197F \
+ << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8197F)
+#define BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8197F(x) \
+ ((x) & (~BITS_FW_UPD_RDPTR19_TO_16_8197F))
+#define BIT_GET_FW_UPD_RDPTR19_TO_16_8197F(x) \
+ (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8197F) & \
+ BIT_MASK_FW_UPD_RDPTR19_TO_16_8197F)
+#define BIT_SET_FW_UPD_RDPTR19_TO_16_8197F(x, v) \
+ (BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8197F(x) | \
+ BIT_FW_UPD_RDPTR19_TO_16_8197F(v))
+
+#define BIT_RXDMA_REQ_8197F BIT(19)
+#define BIT_RW_RELEASE_EN_8197F BIT(18)
+#define BIT_RXDMA_IDLE_8197F BIT(17)
+#define BIT_RXPKT_RELEASE_POLL_8197F BIT(16)
+
+#define BIT_SHIFT_FW_UPD_RDPTR_8197F 0
+#define BIT_MASK_FW_UPD_RDPTR_8197F 0xffff
+#define BIT_FW_UPD_RDPTR_8197F(x) \
+ (((x) & BIT_MASK_FW_UPD_RDPTR_8197F) << BIT_SHIFT_FW_UPD_RDPTR_8197F)
+#define BITS_FW_UPD_RDPTR_8197F \
+ (BIT_MASK_FW_UPD_RDPTR_8197F << BIT_SHIFT_FW_UPD_RDPTR_8197F)
+#define BIT_CLEAR_FW_UPD_RDPTR_8197F(x) ((x) & (~BITS_FW_UPD_RDPTR_8197F))
+#define BIT_GET_FW_UPD_RDPTR_8197F(x) \
+ (((x) >> BIT_SHIFT_FW_UPD_RDPTR_8197F) & BIT_MASK_FW_UPD_RDPTR_8197F)
+#define BIT_SET_FW_UPD_RDPTR_8197F(x, v) \
+ (BIT_CLEAR_FW_UPD_RDPTR_8197F(x) | BIT_FW_UPD_RDPTR_8197F(v))
+
+/* 2 REG_RXDMA_STATUS_8197F */
+#define BIT_FC2H_PKT_OVERFLOW_8197F BIT(8)
+#define BIT_C2H_PKT_OVF_8197F BIT(7)
+#define BIT_AGG_CONFGI_ISSUE_8197F BIT(6)
+#define BIT_FW_POLL_ISSUE_8197F BIT(5)
+#define BIT_RX_DATA_UDN_8197F BIT(4)
+#define BIT_RX_SFF_UDN_8197F BIT(3)
+#define BIT_RX_SFF_OVF_8197F BIT(2)
+#define BIT_RXPKT_OVF_8197F BIT(0)
+
+/* 2 REG_RXDMA_DPR_8197F */
+
+#define BIT_SHIFT_RDE_DEBUG_8197F 0
+#define BIT_MASK_RDE_DEBUG_8197F 0xffffffffL
+#define BIT_RDE_DEBUG_8197F(x) \
+ (((x) & BIT_MASK_RDE_DEBUG_8197F) << BIT_SHIFT_RDE_DEBUG_8197F)
+#define BITS_RDE_DEBUG_8197F \
+ (BIT_MASK_RDE_DEBUG_8197F << BIT_SHIFT_RDE_DEBUG_8197F)
+#define BIT_CLEAR_RDE_DEBUG_8197F(x) ((x) & (~BITS_RDE_DEBUG_8197F))
+#define BIT_GET_RDE_DEBUG_8197F(x) \
+ (((x) >> BIT_SHIFT_RDE_DEBUG_8197F) & BIT_MASK_RDE_DEBUG_8197F)
+#define BIT_SET_RDE_DEBUG_8197F(x, v) \
+ (BIT_CLEAR_RDE_DEBUG_8197F(x) | BIT_RDE_DEBUG_8197F(v))
+
+/* 2 REG_RXDMA_MODE_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+#define BIT_EN_SPD_8197F BIT(6)
+
+#define BIT_SHIFT_BURST_SIZE_8197F 4
+#define BIT_MASK_BURST_SIZE_8197F 0x3
+#define BIT_BURST_SIZE_8197F(x) \
+ (((x) & BIT_MASK_BURST_SIZE_8197F) << BIT_SHIFT_BURST_SIZE_8197F)
+#define BITS_BURST_SIZE_8197F \
+ (BIT_MASK_BURST_SIZE_8197F << BIT_SHIFT_BURST_SIZE_8197F)
+#define BIT_CLEAR_BURST_SIZE_8197F(x) ((x) & (~BITS_BURST_SIZE_8197F))
+#define BIT_GET_BURST_SIZE_8197F(x) \
+ (((x) >> BIT_SHIFT_BURST_SIZE_8197F) & BIT_MASK_BURST_SIZE_8197F)
+#define BIT_SET_BURST_SIZE_8197F(x, v) \
+ (BIT_CLEAR_BURST_SIZE_8197F(x) | BIT_BURST_SIZE_8197F(v))
+
+#define BIT_SHIFT_BURST_CNT_8197F 2
+#define BIT_MASK_BURST_CNT_8197F 0x3
+#define BIT_BURST_CNT_8197F(x) \
+ (((x) & BIT_MASK_BURST_CNT_8197F) << BIT_SHIFT_BURST_CNT_8197F)
+#define BITS_BURST_CNT_8197F \
+ (BIT_MASK_BURST_CNT_8197F << BIT_SHIFT_BURST_CNT_8197F)
+#define BIT_CLEAR_BURST_CNT_8197F(x) ((x) & (~BITS_BURST_CNT_8197F))
+#define BIT_GET_BURST_CNT_8197F(x) \
+ (((x) >> BIT_SHIFT_BURST_CNT_8197F) & BIT_MASK_BURST_CNT_8197F)
+#define BIT_SET_BURST_CNT_8197F(x, v) \
+ (BIT_CLEAR_BURST_CNT_8197F(x) | BIT_BURST_CNT_8197F(v))
+
+#define BIT_DMA_MODE_8197F BIT(1)
+
+/* 2 REG_C2H_PKT_8197F */
+
+#define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8197F 24
+#define BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8197F 0xf
+#define BIT_R_C2H_STR_ADDR_16_TO_19_8197F(x) \
+ (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8197F) \
+ << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8197F)
+#define BITS_R_C2H_STR_ADDR_16_TO_19_8197F \
+ (BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8197F \
+ << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8197F)
+#define BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8197F(x) \
+ ((x) & (~BITS_R_C2H_STR_ADDR_16_TO_19_8197F))
+#define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8197F(x) \
+ (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8197F) & \
+ BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8197F)
+#define BIT_SET_R_C2H_STR_ADDR_16_TO_19_8197F(x, v) \
+ (BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8197F(x) | \
+ BIT_R_C2H_STR_ADDR_16_TO_19_8197F(v))
+
+#define BIT_R_C2H_PKT_REQ_8197F BIT(16)
+
+#define BIT_SHIFT_R_C2H_STR_ADDR_8197F 0
+#define BIT_MASK_R_C2H_STR_ADDR_8197F 0xffff
+#define BIT_R_C2H_STR_ADDR_8197F(x) \
+ (((x) & BIT_MASK_R_C2H_STR_ADDR_8197F) \
+ << BIT_SHIFT_R_C2H_STR_ADDR_8197F)
+#define BITS_R_C2H_STR_ADDR_8197F \
+ (BIT_MASK_R_C2H_STR_ADDR_8197F << BIT_SHIFT_R_C2H_STR_ADDR_8197F)
+#define BIT_CLEAR_R_C2H_STR_ADDR_8197F(x) ((x) & (~BITS_R_C2H_STR_ADDR_8197F))
+#define BIT_GET_R_C2H_STR_ADDR_8197F(x) \
+ (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8197F) & \
+ BIT_MASK_R_C2H_STR_ADDR_8197F)
+#define BIT_SET_R_C2H_STR_ADDR_8197F(x, v) \
+ (BIT_CLEAR_R_C2H_STR_ADDR_8197F(x) | BIT_R_C2H_STR_ADDR_8197F(v))
+
+/* 2 REG_FWFF_C2H_8197F */
+
+#define BIT_SHIFT_C2H_DMA_ADDR_8197F 0
+#define BIT_MASK_C2H_DMA_ADDR_8197F 0x3ffff
+#define BIT_C2H_DMA_ADDR_8197F(x) \
+ (((x) & BIT_MASK_C2H_DMA_ADDR_8197F) << BIT_SHIFT_C2H_DMA_ADDR_8197F)
+#define BITS_C2H_DMA_ADDR_8197F \
+ (BIT_MASK_C2H_DMA_ADDR_8197F << BIT_SHIFT_C2H_DMA_ADDR_8197F)
+#define BIT_CLEAR_C2H_DMA_ADDR_8197F(x) ((x) & (~BITS_C2H_DMA_ADDR_8197F))
+#define BIT_GET_C2H_DMA_ADDR_8197F(x) \
+ (((x) >> BIT_SHIFT_C2H_DMA_ADDR_8197F) & BIT_MASK_C2H_DMA_ADDR_8197F)
+#define BIT_SET_C2H_DMA_ADDR_8197F(x, v) \
+ (BIT_CLEAR_C2H_DMA_ADDR_8197F(x) | BIT_C2H_DMA_ADDR_8197F(v))
+
+/* 2 REG_FWFF_CTRL_8197F */
+#define BIT_FWFF_DMAPKT_REQ_8197F BIT(31)
+
+#define BIT_SHIFT_FWFF_DMA_PKT_NUM_8197F 16
+#define BIT_MASK_FWFF_DMA_PKT_NUM_8197F 0xff
+#define BIT_FWFF_DMA_PKT_NUM_8197F(x) \
+ (((x) & BIT_MASK_FWFF_DMA_PKT_NUM_8197F) \
+ << BIT_SHIFT_FWFF_DMA_PKT_NUM_8197F)
+#define BITS_FWFF_DMA_PKT_NUM_8197F \
+ (BIT_MASK_FWFF_DMA_PKT_NUM_8197F << BIT_SHIFT_FWFF_DMA_PKT_NUM_8197F)
+#define BIT_CLEAR_FWFF_DMA_PKT_NUM_8197F(x) \
+ ((x) & (~BITS_FWFF_DMA_PKT_NUM_8197F))
+#define BIT_GET_FWFF_DMA_PKT_NUM_8197F(x) \
+ (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_8197F) & \
+ BIT_MASK_FWFF_DMA_PKT_NUM_8197F)
+#define BIT_SET_FWFF_DMA_PKT_NUM_8197F(x, v) \
+ (BIT_CLEAR_FWFF_DMA_PKT_NUM_8197F(x) | BIT_FWFF_DMA_PKT_NUM_8197F(v))
+
+#define BIT_SHIFT_FWFF_STR_ADDR_8197F 0
+#define BIT_MASK_FWFF_STR_ADDR_8197F 0xffff
+#define BIT_FWFF_STR_ADDR_8197F(x) \
+ (((x) & BIT_MASK_FWFF_STR_ADDR_8197F) << BIT_SHIFT_FWFF_STR_ADDR_8197F)
+#define BITS_FWFF_STR_ADDR_8197F \
+ (BIT_MASK_FWFF_STR_ADDR_8197F << BIT_SHIFT_FWFF_STR_ADDR_8197F)
+#define BIT_CLEAR_FWFF_STR_ADDR_8197F(x) ((x) & (~BITS_FWFF_STR_ADDR_8197F))
+#define BIT_GET_FWFF_STR_ADDR_8197F(x) \
+ (((x) >> BIT_SHIFT_FWFF_STR_ADDR_8197F) & BIT_MASK_FWFF_STR_ADDR_8197F)
+#define BIT_SET_FWFF_STR_ADDR_8197F(x, v) \
+ (BIT_CLEAR_FWFF_STR_ADDR_8197F(x) | BIT_FWFF_STR_ADDR_8197F(v))
+
+/* 2 REG_FWFF_PKT_INFO_8197F */
+
+#define BIT_SHIFT_FWFF_PKT_QUEUED_8197F 16
+#define BIT_MASK_FWFF_PKT_QUEUED_8197F 0xff
+#define BIT_FWFF_PKT_QUEUED_8197F(x) \
+ (((x) & BIT_MASK_FWFF_PKT_QUEUED_8197F) \
+ << BIT_SHIFT_FWFF_PKT_QUEUED_8197F)
+#define BITS_FWFF_PKT_QUEUED_8197F \
+ (BIT_MASK_FWFF_PKT_QUEUED_8197F << BIT_SHIFT_FWFF_PKT_QUEUED_8197F)
+#define BIT_CLEAR_FWFF_PKT_QUEUED_8197F(x) ((x) & (~BITS_FWFF_PKT_QUEUED_8197F))
+#define BIT_GET_FWFF_PKT_QUEUED_8197F(x) \
+ (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_8197F) & \
+ BIT_MASK_FWFF_PKT_QUEUED_8197F)
+#define BIT_SET_FWFF_PKT_QUEUED_8197F(x, v) \
+ (BIT_CLEAR_FWFF_PKT_QUEUED_8197F(x) | BIT_FWFF_PKT_QUEUED_8197F(v))
+
+#define BIT_SHIFT_FWFF_PKT_STR_ADDR_8197F 0
+#define BIT_MASK_FWFF_PKT_STR_ADDR_8197F 0xffff
+#define BIT_FWFF_PKT_STR_ADDR_8197F(x) \
+ (((x) & BIT_MASK_FWFF_PKT_STR_ADDR_8197F) \
+ << BIT_SHIFT_FWFF_PKT_STR_ADDR_8197F)
+#define BITS_FWFF_PKT_STR_ADDR_8197F \
+ (BIT_MASK_FWFF_PKT_STR_ADDR_8197F << BIT_SHIFT_FWFF_PKT_STR_ADDR_8197F)
+#define BIT_CLEAR_FWFF_PKT_STR_ADDR_8197F(x) \
+ ((x) & (~BITS_FWFF_PKT_STR_ADDR_8197F))
+#define BIT_GET_FWFF_PKT_STR_ADDR_8197F(x) \
+ (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_8197F) & \
+ BIT_MASK_FWFF_PKT_STR_ADDR_8197F)
+#define BIT_SET_FWFF_PKT_STR_ADDR_8197F(x, v) \
+ (BIT_CLEAR_FWFF_PKT_STR_ADDR_8197F(x) | BIT_FWFF_PKT_STR_ADDR_8197F(v))
+
+/* 2 REG_FC2H_INFO_8197F */
+#define BIT_FC2H_PKT_REQ_8197F BIT(16)
+
+#define BIT_SHIFT_FC2H_STR_ADDR_8197F 0
+#define BIT_MASK_FC2H_STR_ADDR_8197F 0xffff
+#define BIT_FC2H_STR_ADDR_8197F(x) \
+ (((x) & BIT_MASK_FC2H_STR_ADDR_8197F) << BIT_SHIFT_FC2H_STR_ADDR_8197F)
+#define BITS_FC2H_STR_ADDR_8197F \
+ (BIT_MASK_FC2H_STR_ADDR_8197F << BIT_SHIFT_FC2H_STR_ADDR_8197F)
+#define BIT_CLEAR_FC2H_STR_ADDR_8197F(x) ((x) & (~BITS_FC2H_STR_ADDR_8197F))
+#define BIT_GET_FC2H_STR_ADDR_8197F(x) \
+ (((x) >> BIT_SHIFT_FC2H_STR_ADDR_8197F) & BIT_MASK_FC2H_STR_ADDR_8197F)
+#define BIT_SET_FC2H_STR_ADDR_8197F(x, v) \
+ (BIT_CLEAR_FC2H_STR_ADDR_8197F(x) | BIT_FC2H_STR_ADDR_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_DDMA_CH0SA_8197F */
+
+#define BIT_SHIFT_DDMACH0_SA_8197F 0
+#define BIT_MASK_DDMACH0_SA_8197F 0xffffffffL
+#define BIT_DDMACH0_SA_8197F(x) \
+ (((x) & BIT_MASK_DDMACH0_SA_8197F) << BIT_SHIFT_DDMACH0_SA_8197F)
+#define BITS_DDMACH0_SA_8197F \
+ (BIT_MASK_DDMACH0_SA_8197F << BIT_SHIFT_DDMACH0_SA_8197F)
+#define BIT_CLEAR_DDMACH0_SA_8197F(x) ((x) & (~BITS_DDMACH0_SA_8197F))
+#define BIT_GET_DDMACH0_SA_8197F(x) \
+ (((x) >> BIT_SHIFT_DDMACH0_SA_8197F) & BIT_MASK_DDMACH0_SA_8197F)
+#define BIT_SET_DDMACH0_SA_8197F(x, v) \
+ (BIT_CLEAR_DDMACH0_SA_8197F(x) | BIT_DDMACH0_SA_8197F(v))
+
+/* 2 REG_DDMA_CH0DA_8197F */
+
+#define BIT_SHIFT_DDMACH0_DA_8197F 0
+#define BIT_MASK_DDMACH0_DA_8197F 0xffffffffL
+#define BIT_DDMACH0_DA_8197F(x) \
+ (((x) & BIT_MASK_DDMACH0_DA_8197F) << BIT_SHIFT_DDMACH0_DA_8197F)
+#define BITS_DDMACH0_DA_8197F \
+ (BIT_MASK_DDMACH0_DA_8197F << BIT_SHIFT_DDMACH0_DA_8197F)
+#define BIT_CLEAR_DDMACH0_DA_8197F(x) ((x) & (~BITS_DDMACH0_DA_8197F))
+#define BIT_GET_DDMACH0_DA_8197F(x) \
+ (((x) >> BIT_SHIFT_DDMACH0_DA_8197F) & BIT_MASK_DDMACH0_DA_8197F)
+#define BIT_SET_DDMACH0_DA_8197F(x, v) \
+ (BIT_CLEAR_DDMACH0_DA_8197F(x) | BIT_DDMACH0_DA_8197F(v))
+
+/* 2 REG_DDMA_CH0CTRL_8197F */
+#define BIT_DDMACH0_OWN_8197F BIT(31)
+#define BIT_DDMACH0_CHKSUM_EN_8197F BIT(29)
+#define BIT_DDMACH0_DA_W_DISABLE_8197F BIT(28)
+#define BIT_DDMACH0_CHKSUM_STS_8197F BIT(27)
+#define BIT_DDMACH0_DDMA_MODE_8197F BIT(26)
+#define BIT_DDMACH0_RESET_CHKSUM_STS_8197F BIT(25)
+#define BIT_DDMACH0_CHKSUM_CONT_8197F BIT(24)
+
+#define BIT_SHIFT_DDMACH0_DLEN_8197F 0
+#define BIT_MASK_DDMACH0_DLEN_8197F 0x3ffff
+#define BIT_DDMACH0_DLEN_8197F(x) \
+ (((x) & BIT_MASK_DDMACH0_DLEN_8197F) << BIT_SHIFT_DDMACH0_DLEN_8197F)
+#define BITS_DDMACH0_DLEN_8197F \
+ (BIT_MASK_DDMACH0_DLEN_8197F << BIT_SHIFT_DDMACH0_DLEN_8197F)
+#define BIT_CLEAR_DDMACH0_DLEN_8197F(x) ((x) & (~BITS_DDMACH0_DLEN_8197F))
+#define BIT_GET_DDMACH0_DLEN_8197F(x) \
+ (((x) >> BIT_SHIFT_DDMACH0_DLEN_8197F) & BIT_MASK_DDMACH0_DLEN_8197F)
+#define BIT_SET_DDMACH0_DLEN_8197F(x, v) \
+ (BIT_CLEAR_DDMACH0_DLEN_8197F(x) | BIT_DDMACH0_DLEN_8197F(v))
+
+/* 2 REG_DDMA_CH1SA_8197F */
+
+#define BIT_SHIFT_DDMACH1_SA_8197F 0
+#define BIT_MASK_DDMACH1_SA_8197F 0xffffffffL
+#define BIT_DDMACH1_SA_8197F(x) \
+ (((x) & BIT_MASK_DDMACH1_SA_8197F) << BIT_SHIFT_DDMACH1_SA_8197F)
+#define BITS_DDMACH1_SA_8197F \
+ (BIT_MASK_DDMACH1_SA_8197F << BIT_SHIFT_DDMACH1_SA_8197F)
+#define BIT_CLEAR_DDMACH1_SA_8197F(x) ((x) & (~BITS_DDMACH1_SA_8197F))
+#define BIT_GET_DDMACH1_SA_8197F(x) \
+ (((x) >> BIT_SHIFT_DDMACH1_SA_8197F) & BIT_MASK_DDMACH1_SA_8197F)
+#define BIT_SET_DDMACH1_SA_8197F(x, v) \
+ (BIT_CLEAR_DDMACH1_SA_8197F(x) | BIT_DDMACH1_SA_8197F(v))
+
+/* 2 REG_DDMA_CH1DA_8197F */
+
+#define BIT_SHIFT_DDMACH1_DA_8197F 0
+#define BIT_MASK_DDMACH1_DA_8197F 0xffffffffL
+#define BIT_DDMACH1_DA_8197F(x) \
+ (((x) & BIT_MASK_DDMACH1_DA_8197F) << BIT_SHIFT_DDMACH1_DA_8197F)
+#define BITS_DDMACH1_DA_8197F \
+ (BIT_MASK_DDMACH1_DA_8197F << BIT_SHIFT_DDMACH1_DA_8197F)
+#define BIT_CLEAR_DDMACH1_DA_8197F(x) ((x) & (~BITS_DDMACH1_DA_8197F))
+#define BIT_GET_DDMACH1_DA_8197F(x) \
+ (((x) >> BIT_SHIFT_DDMACH1_DA_8197F) & BIT_MASK_DDMACH1_DA_8197F)
+#define BIT_SET_DDMACH1_DA_8197F(x, v) \
+ (BIT_CLEAR_DDMACH1_DA_8197F(x) | BIT_DDMACH1_DA_8197F(v))
+
+/* 2 REG_DDMA_CH1CTRL_8197F */
+#define BIT_DDMACH1_OWN_8197F BIT(31)
+#define BIT_DDMACH1_CHKSUM_EN_8197F BIT(29)
+#define BIT_DDMACH1_DA_W_DISABLE_8197F BIT(28)
+#define BIT_DDMACH1_CHKSUM_STS_8197F BIT(27)
+#define BIT_DDMACH1_DDMA_MODE_8197F BIT(26)
+#define BIT_DDMACH1_RESET_CHKSUM_STS_8197F BIT(25)
+#define BIT_DDMACH1_CHKSUM_CONT_8197F BIT(24)
+
+#define BIT_SHIFT_DDMACH1_DLEN_8197F 0
+#define BIT_MASK_DDMACH1_DLEN_8197F 0x3ffff
+#define BIT_DDMACH1_DLEN_8197F(x) \
+ (((x) & BIT_MASK_DDMACH1_DLEN_8197F) << BIT_SHIFT_DDMACH1_DLEN_8197F)
+#define BITS_DDMACH1_DLEN_8197F \
+ (BIT_MASK_DDMACH1_DLEN_8197F << BIT_SHIFT_DDMACH1_DLEN_8197F)
+#define BIT_CLEAR_DDMACH1_DLEN_8197F(x) ((x) & (~BITS_DDMACH1_DLEN_8197F))
+#define BIT_GET_DDMACH1_DLEN_8197F(x) \
+ (((x) >> BIT_SHIFT_DDMACH1_DLEN_8197F) & BIT_MASK_DDMACH1_DLEN_8197F)
+#define BIT_SET_DDMACH1_DLEN_8197F(x, v) \
+ (BIT_CLEAR_DDMACH1_DLEN_8197F(x) | BIT_DDMACH1_DLEN_8197F(v))
+
+/* 2 REG_DDMA_CH2SA_8197F */
+
+#define BIT_SHIFT_DDMACH2_SA_8197F 0
+#define BIT_MASK_DDMACH2_SA_8197F 0xffffffffL
+#define BIT_DDMACH2_SA_8197F(x) \
+ (((x) & BIT_MASK_DDMACH2_SA_8197F) << BIT_SHIFT_DDMACH2_SA_8197F)
+#define BITS_DDMACH2_SA_8197F \
+ (BIT_MASK_DDMACH2_SA_8197F << BIT_SHIFT_DDMACH2_SA_8197F)
+#define BIT_CLEAR_DDMACH2_SA_8197F(x) ((x) & (~BITS_DDMACH2_SA_8197F))
+#define BIT_GET_DDMACH2_SA_8197F(x) \
+ (((x) >> BIT_SHIFT_DDMACH2_SA_8197F) & BIT_MASK_DDMACH2_SA_8197F)
+#define BIT_SET_DDMACH2_SA_8197F(x, v) \
+ (BIT_CLEAR_DDMACH2_SA_8197F(x) | BIT_DDMACH2_SA_8197F(v))
+
+/* 2 REG_DDMA_CH2DA_8197F */
+
+#define BIT_SHIFT_DDMACH2_DA_8197F 0
+#define BIT_MASK_DDMACH2_DA_8197F 0xffffffffL
+#define BIT_DDMACH2_DA_8197F(x) \
+ (((x) & BIT_MASK_DDMACH2_DA_8197F) << BIT_SHIFT_DDMACH2_DA_8197F)
+#define BITS_DDMACH2_DA_8197F \
+ (BIT_MASK_DDMACH2_DA_8197F << BIT_SHIFT_DDMACH2_DA_8197F)
+#define BIT_CLEAR_DDMACH2_DA_8197F(x) ((x) & (~BITS_DDMACH2_DA_8197F))
+#define BIT_GET_DDMACH2_DA_8197F(x) \
+ (((x) >> BIT_SHIFT_DDMACH2_DA_8197F) & BIT_MASK_DDMACH2_DA_8197F)
+#define BIT_SET_DDMACH2_DA_8197F(x, v) \
+ (BIT_CLEAR_DDMACH2_DA_8197F(x) | BIT_DDMACH2_DA_8197F(v))
+
+/* 2 REG_DDMA_CH2CTRL_8197F */
+#define BIT_DDMACH2_OWN_8197F BIT(31)
+#define BIT_DDMACH2_CHKSUM_EN_8197F BIT(29)
+#define BIT_DDMACH2_DA_W_DISABLE_8197F BIT(28)
+#define BIT_DDMACH2_CHKSUM_STS_8197F BIT(27)
+#define BIT_DDMACH2_DDMA_MODE_8197F BIT(26)
+#define BIT_DDMACH2_RESET_CHKSUM_STS_8197F BIT(25)
+#define BIT_DDMACH2_CHKSUM_CONT_8197F BIT(24)
+
+#define BIT_SHIFT_DDMACH2_DLEN_8197F 0
+#define BIT_MASK_DDMACH2_DLEN_8197F 0x3ffff
+#define BIT_DDMACH2_DLEN_8197F(x) \
+ (((x) & BIT_MASK_DDMACH2_DLEN_8197F) << BIT_SHIFT_DDMACH2_DLEN_8197F)
+#define BITS_DDMACH2_DLEN_8197F \
+ (BIT_MASK_DDMACH2_DLEN_8197F << BIT_SHIFT_DDMACH2_DLEN_8197F)
+#define BIT_CLEAR_DDMACH2_DLEN_8197F(x) ((x) & (~BITS_DDMACH2_DLEN_8197F))
+#define BIT_GET_DDMACH2_DLEN_8197F(x) \
+ (((x) >> BIT_SHIFT_DDMACH2_DLEN_8197F) & BIT_MASK_DDMACH2_DLEN_8197F)
+#define BIT_SET_DDMACH2_DLEN_8197F(x, v) \
+ (BIT_CLEAR_DDMACH2_DLEN_8197F(x) | BIT_DDMACH2_DLEN_8197F(v))
+
+/* 2 REG_DDMA_CH3SA_8197F */
+
+#define BIT_SHIFT_DDMACH3_SA_8197F 0
+#define BIT_MASK_DDMACH3_SA_8197F 0xffffffffL
+#define BIT_DDMACH3_SA_8197F(x) \
+ (((x) & BIT_MASK_DDMACH3_SA_8197F) << BIT_SHIFT_DDMACH3_SA_8197F)
+#define BITS_DDMACH3_SA_8197F \
+ (BIT_MASK_DDMACH3_SA_8197F << BIT_SHIFT_DDMACH3_SA_8197F)
+#define BIT_CLEAR_DDMACH3_SA_8197F(x) ((x) & (~BITS_DDMACH3_SA_8197F))
+#define BIT_GET_DDMACH3_SA_8197F(x) \
+ (((x) >> BIT_SHIFT_DDMACH3_SA_8197F) & BIT_MASK_DDMACH3_SA_8197F)
+#define BIT_SET_DDMACH3_SA_8197F(x, v) \
+ (BIT_CLEAR_DDMACH3_SA_8197F(x) | BIT_DDMACH3_SA_8197F(v))
+
+/* 2 REG_DDMA_CH3DA_8197F */
+
+#define BIT_SHIFT_DDMACH3_DA_8197F 0
+#define BIT_MASK_DDMACH3_DA_8197F 0xffffffffL
+#define BIT_DDMACH3_DA_8197F(x) \
+ (((x) & BIT_MASK_DDMACH3_DA_8197F) << BIT_SHIFT_DDMACH3_DA_8197F)
+#define BITS_DDMACH3_DA_8197F \
+ (BIT_MASK_DDMACH3_DA_8197F << BIT_SHIFT_DDMACH3_DA_8197F)
+#define BIT_CLEAR_DDMACH3_DA_8197F(x) ((x) & (~BITS_DDMACH3_DA_8197F))
+#define BIT_GET_DDMACH3_DA_8197F(x) \
+ (((x) >> BIT_SHIFT_DDMACH3_DA_8197F) & BIT_MASK_DDMACH3_DA_8197F)
+#define BIT_SET_DDMACH3_DA_8197F(x, v) \
+ (BIT_CLEAR_DDMACH3_DA_8197F(x) | BIT_DDMACH3_DA_8197F(v))
+
+/* 2 REG_DDMA_CH3CTRL_8197F */
+#define BIT_DDMACH3_OWN_8197F BIT(31)
+#define BIT_DDMACH3_CHKSUM_EN_8197F BIT(29)
+#define BIT_DDMACH3_DA_W_DISABLE_8197F BIT(28)
+#define BIT_DDMACH3_CHKSUM_STS_8197F BIT(27)
+#define BIT_DDMACH3_DDMA_MODE_8197F BIT(26)
+#define BIT_DDMACH3_RESET_CHKSUM_STS_8197F BIT(25)
+#define BIT_DDMACH3_CHKSUM_CONT_8197F BIT(24)
+
+#define BIT_SHIFT_DDMACH3_DLEN_8197F 0
+#define BIT_MASK_DDMACH3_DLEN_8197F 0x3ffff
+#define BIT_DDMACH3_DLEN_8197F(x) \
+ (((x) & BIT_MASK_DDMACH3_DLEN_8197F) << BIT_SHIFT_DDMACH3_DLEN_8197F)
+#define BITS_DDMACH3_DLEN_8197F \
+ (BIT_MASK_DDMACH3_DLEN_8197F << BIT_SHIFT_DDMACH3_DLEN_8197F)
+#define BIT_CLEAR_DDMACH3_DLEN_8197F(x) ((x) & (~BITS_DDMACH3_DLEN_8197F))
+#define BIT_GET_DDMACH3_DLEN_8197F(x) \
+ (((x) >> BIT_SHIFT_DDMACH3_DLEN_8197F) & BIT_MASK_DDMACH3_DLEN_8197F)
+#define BIT_SET_DDMACH3_DLEN_8197F(x, v) \
+ (BIT_CLEAR_DDMACH3_DLEN_8197F(x) | BIT_DDMACH3_DLEN_8197F(v))
+
+/* 2 REG_DDMA_CH4SA_8197F */
+
+#define BIT_SHIFT_DDMACH4_SA_8197F 0
+#define BIT_MASK_DDMACH4_SA_8197F 0xffffffffL
+#define BIT_DDMACH4_SA_8197F(x) \
+ (((x) & BIT_MASK_DDMACH4_SA_8197F) << BIT_SHIFT_DDMACH4_SA_8197F)
+#define BITS_DDMACH4_SA_8197F \
+ (BIT_MASK_DDMACH4_SA_8197F << BIT_SHIFT_DDMACH4_SA_8197F)
+#define BIT_CLEAR_DDMACH4_SA_8197F(x) ((x) & (~BITS_DDMACH4_SA_8197F))
+#define BIT_GET_DDMACH4_SA_8197F(x) \
+ (((x) >> BIT_SHIFT_DDMACH4_SA_8197F) & BIT_MASK_DDMACH4_SA_8197F)
+#define BIT_SET_DDMACH4_SA_8197F(x, v) \
+ (BIT_CLEAR_DDMACH4_SA_8197F(x) | BIT_DDMACH4_SA_8197F(v))
+
+/* 2 REG_DDMA_CH4DA_8197F */
+
+#define BIT_SHIFT_DDMACH4_DA_8197F 0
+#define BIT_MASK_DDMACH4_DA_8197F 0xffffffffL
+#define BIT_DDMACH4_DA_8197F(x) \
+ (((x) & BIT_MASK_DDMACH4_DA_8197F) << BIT_SHIFT_DDMACH4_DA_8197F)
+#define BITS_DDMACH4_DA_8197F \
+ (BIT_MASK_DDMACH4_DA_8197F << BIT_SHIFT_DDMACH4_DA_8197F)
+#define BIT_CLEAR_DDMACH4_DA_8197F(x) ((x) & (~BITS_DDMACH4_DA_8197F))
+#define BIT_GET_DDMACH4_DA_8197F(x) \
+ (((x) >> BIT_SHIFT_DDMACH4_DA_8197F) & BIT_MASK_DDMACH4_DA_8197F)
+#define BIT_SET_DDMACH4_DA_8197F(x, v) \
+ (BIT_CLEAR_DDMACH4_DA_8197F(x) | BIT_DDMACH4_DA_8197F(v))
+
+/* 2 REG_DDMA_CH4CTRL_8197F */
+#define BIT_DDMACH4_OWN_8197F BIT(31)
+#define BIT_DDMACH4_CHKSUM_EN_8197F BIT(29)
+#define BIT_DDMACH4_DA_W_DISABLE_8197F BIT(28)
+#define BIT_DDMACH4_CHKSUM_STS_8197F BIT(27)
+#define BIT_DDMACH4_DDMA_MODE_8197F BIT(26)
+#define BIT_DDMACH4_RESET_CHKSUM_STS_8197F BIT(25)
+#define BIT_DDMACH4_CHKSUM_CONT_8197F BIT(24)
+
+#define BIT_SHIFT_DDMACH4_DLEN_8197F 0
+#define BIT_MASK_DDMACH4_DLEN_8197F 0x3ffff
+#define BIT_DDMACH4_DLEN_8197F(x) \
+ (((x) & BIT_MASK_DDMACH4_DLEN_8197F) << BIT_SHIFT_DDMACH4_DLEN_8197F)
+#define BITS_DDMACH4_DLEN_8197F \
+ (BIT_MASK_DDMACH4_DLEN_8197F << BIT_SHIFT_DDMACH4_DLEN_8197F)
+#define BIT_CLEAR_DDMACH4_DLEN_8197F(x) ((x) & (~BITS_DDMACH4_DLEN_8197F))
+#define BIT_GET_DDMACH4_DLEN_8197F(x) \
+ (((x) >> BIT_SHIFT_DDMACH4_DLEN_8197F) & BIT_MASK_DDMACH4_DLEN_8197F)
+#define BIT_SET_DDMACH4_DLEN_8197F(x, v) \
+ (BIT_CLEAR_DDMACH4_DLEN_8197F(x) | BIT_DDMACH4_DLEN_8197F(v))
+
+/* 2 REG_DDMA_CH5SA_8197F */
+
+#define BIT_SHIFT_DDMACH5_SA_8197F 0
+#define BIT_MASK_DDMACH5_SA_8197F 0xffffffffL
+#define BIT_DDMACH5_SA_8197F(x) \
+ (((x) & BIT_MASK_DDMACH5_SA_8197F) << BIT_SHIFT_DDMACH5_SA_8197F)
+#define BITS_DDMACH5_SA_8197F \
+ (BIT_MASK_DDMACH5_SA_8197F << BIT_SHIFT_DDMACH5_SA_8197F)
+#define BIT_CLEAR_DDMACH5_SA_8197F(x) ((x) & (~BITS_DDMACH5_SA_8197F))
+#define BIT_GET_DDMACH5_SA_8197F(x) \
+ (((x) >> BIT_SHIFT_DDMACH5_SA_8197F) & BIT_MASK_DDMACH5_SA_8197F)
+#define BIT_SET_DDMACH5_SA_8197F(x, v) \
+ (BIT_CLEAR_DDMACH5_SA_8197F(x) | BIT_DDMACH5_SA_8197F(v))
+
+/* 2 REG_DDMA_CH5DA_8197F */
+
+#define BIT_SHIFT_DDMACH5_DA_8197F 0
+#define BIT_MASK_DDMACH5_DA_8197F 0xffffffffL
+#define BIT_DDMACH5_DA_8197F(x) \
+ (((x) & BIT_MASK_DDMACH5_DA_8197F) << BIT_SHIFT_DDMACH5_DA_8197F)
+#define BITS_DDMACH5_DA_8197F \
+ (BIT_MASK_DDMACH5_DA_8197F << BIT_SHIFT_DDMACH5_DA_8197F)
+#define BIT_CLEAR_DDMACH5_DA_8197F(x) ((x) & (~BITS_DDMACH5_DA_8197F))
+#define BIT_GET_DDMACH5_DA_8197F(x) \
+ (((x) >> BIT_SHIFT_DDMACH5_DA_8197F) & BIT_MASK_DDMACH5_DA_8197F)
+#define BIT_SET_DDMACH5_DA_8197F(x, v) \
+ (BIT_CLEAR_DDMACH5_DA_8197F(x) | BIT_DDMACH5_DA_8197F(v))
+
+/* 2 REG_REG_DDMA_CH5CTRL_8197F */
+#define BIT_DDMACH5_OWN_8197F BIT(31)
+#define BIT_DDMACH5_CHKSUM_EN_8197F BIT(29)
+#define BIT_DDMACH5_DA_W_DISABLE_8197F BIT(28)
+#define BIT_DDMACH5_CHKSUM_STS_8197F BIT(27)
+#define BIT_DDMACH5_DDMA_MODE_8197F BIT(26)
+#define BIT_DDMACH5_RESET_CHKSUM_STS_8197F BIT(25)
+#define BIT_DDMACH5_CHKSUM_CONT_8197F BIT(24)
+
+#define BIT_SHIFT_DDMACH5_DLEN_8197F 0
+#define BIT_MASK_DDMACH5_DLEN_8197F 0x3ffff
+#define BIT_DDMACH5_DLEN_8197F(x) \
+ (((x) & BIT_MASK_DDMACH5_DLEN_8197F) << BIT_SHIFT_DDMACH5_DLEN_8197F)
+#define BITS_DDMACH5_DLEN_8197F \
+ (BIT_MASK_DDMACH5_DLEN_8197F << BIT_SHIFT_DDMACH5_DLEN_8197F)
+#define BIT_CLEAR_DDMACH5_DLEN_8197F(x) ((x) & (~BITS_DDMACH5_DLEN_8197F))
+#define BIT_GET_DDMACH5_DLEN_8197F(x) \
+ (((x) >> BIT_SHIFT_DDMACH5_DLEN_8197F) & BIT_MASK_DDMACH5_DLEN_8197F)
+#define BIT_SET_DDMACH5_DLEN_8197F(x, v) \
+ (BIT_CLEAR_DDMACH5_DLEN_8197F(x) | BIT_DDMACH5_DLEN_8197F(v))
+
+/* 2 REG_DDMA_INT_MSK_8197F */
+#define BIT_DDMACH5_MSK_8197F BIT(5)
+#define BIT_DDMACH4_MSK_8197F BIT(4)
+#define BIT_DDMACH3_MSK_8197F BIT(3)
+#define BIT_DDMACH2_MSK_8197F BIT(2)
+#define BIT_DDMACH1_MSK_8197F BIT(1)
+#define BIT_DDMACH0_MSK_8197F BIT(0)
+
+/* 2 REG_DDMA_CHSTATUS_8197F */
+#define BIT_DDMACH5_BUSY_8197F BIT(5)
+#define BIT_DDMACH4_BUSY_8197F BIT(4)
+#define BIT_DDMACH3_BUSY_8197F BIT(3)
+#define BIT_DDMACH2_BUSY_8197F BIT(2)
+#define BIT_DDMACH1_BUSY_8197F BIT(1)
+#define BIT_DDMACH0_BUSY_8197F BIT(0)
+
+/* 2 REG_DDMA_CHKSUM_8197F */
+
+#define BIT_SHIFT_IDDMA0_CHKSUM_8197F 0
+#define BIT_MASK_IDDMA0_CHKSUM_8197F 0xffff
+#define BIT_IDDMA0_CHKSUM_8197F(x) \
+ (((x) & BIT_MASK_IDDMA0_CHKSUM_8197F) << BIT_SHIFT_IDDMA0_CHKSUM_8197F)
+#define BITS_IDDMA0_CHKSUM_8197F \
+ (BIT_MASK_IDDMA0_CHKSUM_8197F << BIT_SHIFT_IDDMA0_CHKSUM_8197F)
+#define BIT_CLEAR_IDDMA0_CHKSUM_8197F(x) ((x) & (~BITS_IDDMA0_CHKSUM_8197F))
+#define BIT_GET_IDDMA0_CHKSUM_8197F(x) \
+ (((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8197F) & BIT_MASK_IDDMA0_CHKSUM_8197F)
+#define BIT_SET_IDDMA0_CHKSUM_8197F(x, v) \
+ (BIT_CLEAR_IDDMA0_CHKSUM_8197F(x) | BIT_IDDMA0_CHKSUM_8197F(v))
+
+/* 2 REG_DDMA_MONITOR_8197F */
+#define BIT_IDDMA0_PERMU_UNDERFLOW_8197F BIT(14)
+#define BIT_IDDMA0_FIFO_UNDERFLOW_8197F BIT(13)
+#define BIT_IDDMA0_FIFO_OVERFLOW_8197F BIT(12)
+#define BIT_CH5_ERR_8197F BIT(5)
+#define BIT_CH4_ERR_8197F BIT(4)
+#define BIT_CH3_ERR_8197F BIT(3)
+#define BIT_CH2_ERR_8197F BIT(2)
+#define BIT_CH1_ERR_8197F BIT(1)
+#define BIT_CH0_ERR_8197F BIT(0)
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_HCI_CTRL_8197F */
+#define BIT_HCIIO_PERSTB_SEL_8197F BIT(31)
+
+#define BIT_SHIFT_HCI_MAX_RXDMA_8197F 28
+#define BIT_MASK_HCI_MAX_RXDMA_8197F 0x7
+#define BIT_HCI_MAX_RXDMA_8197F(x) \
+ (((x) & BIT_MASK_HCI_MAX_RXDMA_8197F) << BIT_SHIFT_HCI_MAX_RXDMA_8197F)
+#define BITS_HCI_MAX_RXDMA_8197F \
+ (BIT_MASK_HCI_MAX_RXDMA_8197F << BIT_SHIFT_HCI_MAX_RXDMA_8197F)
+#define BIT_CLEAR_HCI_MAX_RXDMA_8197F(x) ((x) & (~BITS_HCI_MAX_RXDMA_8197F))
+#define BIT_GET_HCI_MAX_RXDMA_8197F(x) \
+ (((x) >> BIT_SHIFT_HCI_MAX_RXDMA_8197F) & BIT_MASK_HCI_MAX_RXDMA_8197F)
+#define BIT_SET_HCI_MAX_RXDMA_8197F(x, v) \
+ (BIT_CLEAR_HCI_MAX_RXDMA_8197F(x) | BIT_HCI_MAX_RXDMA_8197F(v))
+
+#define BIT_MULRW_8197F BIT(27)
+
+#define BIT_SHIFT_HCI_MAX_TXDMA_8197F 24
+#define BIT_MASK_HCI_MAX_TXDMA_8197F 0x7
+#define BIT_HCI_MAX_TXDMA_8197F(x) \
+ (((x) & BIT_MASK_HCI_MAX_TXDMA_8197F) << BIT_SHIFT_HCI_MAX_TXDMA_8197F)
+#define BITS_HCI_MAX_TXDMA_8197F \
+ (BIT_MASK_HCI_MAX_TXDMA_8197F << BIT_SHIFT_HCI_MAX_TXDMA_8197F)
+#define BIT_CLEAR_HCI_MAX_TXDMA_8197F(x) ((x) & (~BITS_HCI_MAX_TXDMA_8197F))
+#define BIT_GET_HCI_MAX_TXDMA_8197F(x) \
+ (((x) >> BIT_SHIFT_HCI_MAX_TXDMA_8197F) & BIT_MASK_HCI_MAX_TXDMA_8197F)
+#define BIT_SET_HCI_MAX_TXDMA_8197F(x, v) \
+ (BIT_CLEAR_HCI_MAX_TXDMA_8197F(x) | BIT_HCI_MAX_TXDMA_8197F(v))
+
+#define BIT_EN_CPL_TIMEOUT_PS_8197F BIT(22)
+#define BIT_REG_TXDMA_FAIL_PS_8197F BIT(21)
+#define BIT_HCI_RST_TRXDMA_INTF_8197F BIT(20)
+#define BIT_EN_HWENTR_L1_8197F BIT(19)
+#define BIT_EN_ADV_CLKGATE_8197F BIT(18)
+#define BIT_HCI_EN_SWENT_L23_8197F BIT(17)
+#define BIT_HCI_EN_HWEXT_L1_8197F BIT(16)
+#define BIT_RX_CLOSE_EN_8197F BIT(15)
+#define BIT_STOP_BCNQ_8197F BIT(14)
+#define BIT_STOP_MGQ_8197F BIT(13)
+#define BIT_STOP_VOQ_8197F BIT(12)
+#define BIT_STOP_VIQ_8197F BIT(11)
+#define BIT_STOP_BEQ_8197F BIT(10)
+#define BIT_STOP_BKQ_8197F BIT(9)
+#define BIT_STOP_RXQ_8197F BIT(8)
+#define BIT_STOP_HI7Q_8197F BIT(7)
+#define BIT_STOP_HI6Q_8197F BIT(6)
+#define BIT_STOP_HI5Q_8197F BIT(5)
+#define BIT_STOP_HI4Q_8197F BIT(4)
+#define BIT_STOP_HI3Q_8197F BIT(3)
+#define BIT_STOP_HI2Q_8197F BIT(2)
+#define BIT_STOP_HI1Q_8197F BIT(1)
+#define BIT_STOP_HI0Q_8197F BIT(0)
+
+/* 2 REG_INT_MIG_8197F */
+
+#define BIT_SHIFT_TXTTIMER_MATCH_NUM_8197F 28
+#define BIT_MASK_TXTTIMER_MATCH_NUM_8197F 0xf
+#define BIT_TXTTIMER_MATCH_NUM_8197F(x) \
+ (((x) & BIT_MASK_TXTTIMER_MATCH_NUM_8197F) \
+ << BIT_SHIFT_TXTTIMER_MATCH_NUM_8197F)
+#define BITS_TXTTIMER_MATCH_NUM_8197F \
+ (BIT_MASK_TXTTIMER_MATCH_NUM_8197F \
+ << BIT_SHIFT_TXTTIMER_MATCH_NUM_8197F)
+#define BIT_CLEAR_TXTTIMER_MATCH_NUM_8197F(x) \
+ ((x) & (~BITS_TXTTIMER_MATCH_NUM_8197F))
+#define BIT_GET_TXTTIMER_MATCH_NUM_8197F(x) \
+ (((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM_8197F) & \
+ BIT_MASK_TXTTIMER_MATCH_NUM_8197F)
+#define BIT_SET_TXTTIMER_MATCH_NUM_8197F(x, v) \
+ (BIT_CLEAR_TXTTIMER_MATCH_NUM_8197F(x) | \
+ BIT_TXTTIMER_MATCH_NUM_8197F(v))
+
+#define BIT_SHIFT_TXPKT_NUM_MATCH_8197F 24
+#define BIT_MASK_TXPKT_NUM_MATCH_8197F 0xf
+#define BIT_TXPKT_NUM_MATCH_8197F(x) \
+ (((x) & BIT_MASK_TXPKT_NUM_MATCH_8197F) \
+ << BIT_SHIFT_TXPKT_NUM_MATCH_8197F)
+#define BITS_TXPKT_NUM_MATCH_8197F \
+ (BIT_MASK_TXPKT_NUM_MATCH_8197F << BIT_SHIFT_TXPKT_NUM_MATCH_8197F)
+#define BIT_CLEAR_TXPKT_NUM_MATCH_8197F(x) ((x) & (~BITS_TXPKT_NUM_MATCH_8197F))
+#define BIT_GET_TXPKT_NUM_MATCH_8197F(x) \
+ (((x) >> BIT_SHIFT_TXPKT_NUM_MATCH_8197F) & \
+ BIT_MASK_TXPKT_NUM_MATCH_8197F)
+#define BIT_SET_TXPKT_NUM_MATCH_8197F(x, v) \
+ (BIT_CLEAR_TXPKT_NUM_MATCH_8197F(x) | BIT_TXPKT_NUM_MATCH_8197F(v))
+
+#define BIT_SHIFT_RXTTIMER_MATCH_NUM_8197F 20
+#define BIT_MASK_RXTTIMER_MATCH_NUM_8197F 0xf
+#define BIT_RXTTIMER_MATCH_NUM_8197F(x) \
+ (((x) & BIT_MASK_RXTTIMER_MATCH_NUM_8197F) \
+ << BIT_SHIFT_RXTTIMER_MATCH_NUM_8197F)
+#define BITS_RXTTIMER_MATCH_NUM_8197F \
+ (BIT_MASK_RXTTIMER_MATCH_NUM_8197F \
+ << BIT_SHIFT_RXTTIMER_MATCH_NUM_8197F)
+#define BIT_CLEAR_RXTTIMER_MATCH_NUM_8197F(x) \
+ ((x) & (~BITS_RXTTIMER_MATCH_NUM_8197F))
+#define BIT_GET_RXTTIMER_MATCH_NUM_8197F(x) \
+ (((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM_8197F) & \
+ BIT_MASK_RXTTIMER_MATCH_NUM_8197F)
+#define BIT_SET_RXTTIMER_MATCH_NUM_8197F(x, v) \
+ (BIT_CLEAR_RXTTIMER_MATCH_NUM_8197F(x) | \
+ BIT_RXTTIMER_MATCH_NUM_8197F(v))
+
+#define BIT_SHIFT_RXPKT_NUM_MATCH_8197F 16
+#define BIT_MASK_RXPKT_NUM_MATCH_8197F 0xf
+#define BIT_RXPKT_NUM_MATCH_8197F(x) \
+ (((x) & BIT_MASK_RXPKT_NUM_MATCH_8197F) \
+ << BIT_SHIFT_RXPKT_NUM_MATCH_8197F)
+#define BITS_RXPKT_NUM_MATCH_8197F \
+ (BIT_MASK_RXPKT_NUM_MATCH_8197F << BIT_SHIFT_RXPKT_NUM_MATCH_8197F)
+#define BIT_CLEAR_RXPKT_NUM_MATCH_8197F(x) ((x) & (~BITS_RXPKT_NUM_MATCH_8197F))
+#define BIT_GET_RXPKT_NUM_MATCH_8197F(x) \
+ (((x) >> BIT_SHIFT_RXPKT_NUM_MATCH_8197F) & \
+ BIT_MASK_RXPKT_NUM_MATCH_8197F)
+#define BIT_SET_RXPKT_NUM_MATCH_8197F(x, v) \
+ (BIT_CLEAR_RXPKT_NUM_MATCH_8197F(x) | BIT_RXPKT_NUM_MATCH_8197F(v))
+
+#define BIT_SHIFT_MIGRATE_TIMER_8197F 0
+#define BIT_MASK_MIGRATE_TIMER_8197F 0xffff
+#define BIT_MIGRATE_TIMER_8197F(x) \
+ (((x) & BIT_MASK_MIGRATE_TIMER_8197F) << BIT_SHIFT_MIGRATE_TIMER_8197F)
+#define BITS_MIGRATE_TIMER_8197F \
+ (BIT_MASK_MIGRATE_TIMER_8197F << BIT_SHIFT_MIGRATE_TIMER_8197F)
+#define BIT_CLEAR_MIGRATE_TIMER_8197F(x) ((x) & (~BITS_MIGRATE_TIMER_8197F))
+#define BIT_GET_MIGRATE_TIMER_8197F(x) \
+ (((x) >> BIT_SHIFT_MIGRATE_TIMER_8197F) & BIT_MASK_MIGRATE_TIMER_8197F)
+#define BIT_SET_MIGRATE_TIMER_8197F(x, v) \
+ (BIT_CLEAR_MIGRATE_TIMER_8197F(x) | BIT_MIGRATE_TIMER_8197F(v))
+
+/* 2 REG_BCNQ_TXBD_DESA_8197F */
+
+#define BIT_SHIFT_BCNQ_TXBD_DESA_8197F 0
+#define BIT_MASK_BCNQ_TXBD_DESA_8197F 0xffffffffffffffffL
+#define BIT_BCNQ_TXBD_DESA_8197F(x) \
+ (((x) & BIT_MASK_BCNQ_TXBD_DESA_8197F) \
+ << BIT_SHIFT_BCNQ_TXBD_DESA_8197F)
+#define BITS_BCNQ_TXBD_DESA_8197F \
+ (BIT_MASK_BCNQ_TXBD_DESA_8197F << BIT_SHIFT_BCNQ_TXBD_DESA_8197F)
+#define BIT_CLEAR_BCNQ_TXBD_DESA_8197F(x) ((x) & (~BITS_BCNQ_TXBD_DESA_8197F))
+#define BIT_GET_BCNQ_TXBD_DESA_8197F(x) \
+ (((x) >> BIT_SHIFT_BCNQ_TXBD_DESA_8197F) & \
+ BIT_MASK_BCNQ_TXBD_DESA_8197F)
+#define BIT_SET_BCNQ_TXBD_DESA_8197F(x, v) \
+ (BIT_CLEAR_BCNQ_TXBD_DESA_8197F(x) | BIT_BCNQ_TXBD_DESA_8197F(v))
+
+/* 2 REG_MGQ_TXBD_DESA_8197F */
+
+#define BIT_SHIFT_MGQ_TXBD_DESA_8197F 0
+#define BIT_MASK_MGQ_TXBD_DESA_8197F 0xffffffffffffffffL
+#define BIT_MGQ_TXBD_DESA_8197F(x) \
+ (((x) & BIT_MASK_MGQ_TXBD_DESA_8197F) << BIT_SHIFT_MGQ_TXBD_DESA_8197F)
+#define BITS_MGQ_TXBD_DESA_8197F \
+ (BIT_MASK_MGQ_TXBD_DESA_8197F << BIT_SHIFT_MGQ_TXBD_DESA_8197F)
+#define BIT_CLEAR_MGQ_TXBD_DESA_8197F(x) ((x) & (~BITS_MGQ_TXBD_DESA_8197F))
+#define BIT_GET_MGQ_TXBD_DESA_8197F(x) \
+ (((x) >> BIT_SHIFT_MGQ_TXBD_DESA_8197F) & BIT_MASK_MGQ_TXBD_DESA_8197F)
+#define BIT_SET_MGQ_TXBD_DESA_8197F(x, v) \
+ (BIT_CLEAR_MGQ_TXBD_DESA_8197F(x) | BIT_MGQ_TXBD_DESA_8197F(v))
+
+/* 2 REG_VOQ_TXBD_DESA_8197F */
+
+#define BIT_SHIFT_VOQ_TXBD_DESA_8197F 0
+#define BIT_MASK_VOQ_TXBD_DESA_8197F 0xffffffffffffffffL
+#define BIT_VOQ_TXBD_DESA_8197F(x) \
+ (((x) & BIT_MASK_VOQ_TXBD_DESA_8197F) << BIT_SHIFT_VOQ_TXBD_DESA_8197F)
+#define BITS_VOQ_TXBD_DESA_8197F \
+ (BIT_MASK_VOQ_TXBD_DESA_8197F << BIT_SHIFT_VOQ_TXBD_DESA_8197F)
+#define BIT_CLEAR_VOQ_TXBD_DESA_8197F(x) ((x) & (~BITS_VOQ_TXBD_DESA_8197F))
+#define BIT_GET_VOQ_TXBD_DESA_8197F(x) \
+ (((x) >> BIT_SHIFT_VOQ_TXBD_DESA_8197F) & BIT_MASK_VOQ_TXBD_DESA_8197F)
+#define BIT_SET_VOQ_TXBD_DESA_8197F(x, v) \
+ (BIT_CLEAR_VOQ_TXBD_DESA_8197F(x) | BIT_VOQ_TXBD_DESA_8197F(v))
+
+/* 2 REG_VIQ_TXBD_DESA_8197F */
+
+#define BIT_SHIFT_VIQ_TXBD_DESA_8197F 0
+#define BIT_MASK_VIQ_TXBD_DESA_8197F 0xffffffffffffffffL
+#define BIT_VIQ_TXBD_DESA_8197F(x) \
+ (((x) & BIT_MASK_VIQ_TXBD_DESA_8197F) << BIT_SHIFT_VIQ_TXBD_DESA_8197F)
+#define BITS_VIQ_TXBD_DESA_8197F \
+ (BIT_MASK_VIQ_TXBD_DESA_8197F << BIT_SHIFT_VIQ_TXBD_DESA_8197F)
+#define BIT_CLEAR_VIQ_TXBD_DESA_8197F(x) ((x) & (~BITS_VIQ_TXBD_DESA_8197F))
+#define BIT_GET_VIQ_TXBD_DESA_8197F(x) \
+ (((x) >> BIT_SHIFT_VIQ_TXBD_DESA_8197F) & BIT_MASK_VIQ_TXBD_DESA_8197F)
+#define BIT_SET_VIQ_TXBD_DESA_8197F(x, v) \
+ (BIT_CLEAR_VIQ_TXBD_DESA_8197F(x) | BIT_VIQ_TXBD_DESA_8197F(v))
+
+/* 2 REG_BEQ_TXBD_DESA_8197F */
+
+#define BIT_SHIFT_BEQ_TXBD_DESA_8197F 0
+#define BIT_MASK_BEQ_TXBD_DESA_8197F 0xffffffffffffffffL
+#define BIT_BEQ_TXBD_DESA_8197F(x) \
+ (((x) & BIT_MASK_BEQ_TXBD_DESA_8197F) << BIT_SHIFT_BEQ_TXBD_DESA_8197F)
+#define BITS_BEQ_TXBD_DESA_8197F \
+ (BIT_MASK_BEQ_TXBD_DESA_8197F << BIT_SHIFT_BEQ_TXBD_DESA_8197F)
+#define BIT_CLEAR_BEQ_TXBD_DESA_8197F(x) ((x) & (~BITS_BEQ_TXBD_DESA_8197F))
+#define BIT_GET_BEQ_TXBD_DESA_8197F(x) \
+ (((x) >> BIT_SHIFT_BEQ_TXBD_DESA_8197F) & BIT_MASK_BEQ_TXBD_DESA_8197F)
+#define BIT_SET_BEQ_TXBD_DESA_8197F(x, v) \
+ (BIT_CLEAR_BEQ_TXBD_DESA_8197F(x) | BIT_BEQ_TXBD_DESA_8197F(v))
+
+/* 2 REG_BKQ_TXBD_DESA_8197F */
+
+#define BIT_SHIFT_BKQ_TXBD_DESA_8197F 0
+#define BIT_MASK_BKQ_TXBD_DESA_8197F 0xffffffffffffffffL
+#define BIT_BKQ_TXBD_DESA_8197F(x) \
+ (((x) & BIT_MASK_BKQ_TXBD_DESA_8197F) << BIT_SHIFT_BKQ_TXBD_DESA_8197F)
+#define BITS_BKQ_TXBD_DESA_8197F \
+ (BIT_MASK_BKQ_TXBD_DESA_8197F << BIT_SHIFT_BKQ_TXBD_DESA_8197F)
+#define BIT_CLEAR_BKQ_TXBD_DESA_8197F(x) ((x) & (~BITS_BKQ_TXBD_DESA_8197F))
+#define BIT_GET_BKQ_TXBD_DESA_8197F(x) \
+ (((x) >> BIT_SHIFT_BKQ_TXBD_DESA_8197F) & BIT_MASK_BKQ_TXBD_DESA_8197F)
+#define BIT_SET_BKQ_TXBD_DESA_8197F(x, v) \
+ (BIT_CLEAR_BKQ_TXBD_DESA_8197F(x) | BIT_BKQ_TXBD_DESA_8197F(v))
+
+/* 2 REG_RXQ_RXBD_DESA_8197F */
+
+#define BIT_SHIFT_RXQ_RXBD_DESA_8197F 0
+#define BIT_MASK_RXQ_RXBD_DESA_8197F 0xffffffffffffffffL
+#define BIT_RXQ_RXBD_DESA_8197F(x) \
+ (((x) & BIT_MASK_RXQ_RXBD_DESA_8197F) << BIT_SHIFT_RXQ_RXBD_DESA_8197F)
+#define BITS_RXQ_RXBD_DESA_8197F \
+ (BIT_MASK_RXQ_RXBD_DESA_8197F << BIT_SHIFT_RXQ_RXBD_DESA_8197F)
+#define BIT_CLEAR_RXQ_RXBD_DESA_8197F(x) ((x) & (~BITS_RXQ_RXBD_DESA_8197F))
+#define BIT_GET_RXQ_RXBD_DESA_8197F(x) \
+ (((x) >> BIT_SHIFT_RXQ_RXBD_DESA_8197F) & BIT_MASK_RXQ_RXBD_DESA_8197F)
+#define BIT_SET_RXQ_RXBD_DESA_8197F(x, v) \
+ (BIT_CLEAR_RXQ_RXBD_DESA_8197F(x) | BIT_RXQ_RXBD_DESA_8197F(v))
+
+/* 2 REG_HI0Q_TXBD_DESA_8197F */
+
+#define BIT_SHIFT_HI0Q_TXBD_DESA_8197F 0
+#define BIT_MASK_HI0Q_TXBD_DESA_8197F 0xffffffffffffffffL
+#define BIT_HI0Q_TXBD_DESA_8197F(x) \
+ (((x) & BIT_MASK_HI0Q_TXBD_DESA_8197F) \
+ << BIT_SHIFT_HI0Q_TXBD_DESA_8197F)
+#define BITS_HI0Q_TXBD_DESA_8197F \
+ (BIT_MASK_HI0Q_TXBD_DESA_8197F << BIT_SHIFT_HI0Q_TXBD_DESA_8197F)
+#define BIT_CLEAR_HI0Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI0Q_TXBD_DESA_8197F))
+#define BIT_GET_HI0Q_TXBD_DESA_8197F(x) \
+ (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_8197F) & \
+ BIT_MASK_HI0Q_TXBD_DESA_8197F)
+#define BIT_SET_HI0Q_TXBD_DESA_8197F(x, v) \
+ (BIT_CLEAR_HI0Q_TXBD_DESA_8197F(x) | BIT_HI0Q_TXBD_DESA_8197F(v))
+
+/* 2 REG_HI1Q_TXBD_DESA_8197F */
+
+#define BIT_SHIFT_HI1Q_TXBD_DESA_8197F 0
+#define BIT_MASK_HI1Q_TXBD_DESA_8197F 0xffffffffffffffffL
+#define BIT_HI1Q_TXBD_DESA_8197F(x) \
+ (((x) & BIT_MASK_HI1Q_TXBD_DESA_8197F) \
+ << BIT_SHIFT_HI1Q_TXBD_DESA_8197F)
+#define BITS_HI1Q_TXBD_DESA_8197F \
+ (BIT_MASK_HI1Q_TXBD_DESA_8197F << BIT_SHIFT_HI1Q_TXBD_DESA_8197F)
+#define BIT_CLEAR_HI1Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI1Q_TXBD_DESA_8197F))
+#define BIT_GET_HI1Q_TXBD_DESA_8197F(x) \
+ (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_8197F) & \
+ BIT_MASK_HI1Q_TXBD_DESA_8197F)
+#define BIT_SET_HI1Q_TXBD_DESA_8197F(x, v) \
+ (BIT_CLEAR_HI1Q_TXBD_DESA_8197F(x) | BIT_HI1Q_TXBD_DESA_8197F(v))
+
+/* 2 REG_HI2Q_TXBD_DESA_8197F */
+
+#define BIT_SHIFT_HI2Q_TXBD_DESA_8197F 0
+#define BIT_MASK_HI2Q_TXBD_DESA_8197F 0xffffffffffffffffL
+#define BIT_HI2Q_TXBD_DESA_8197F(x) \
+ (((x) & BIT_MASK_HI2Q_TXBD_DESA_8197F) \
+ << BIT_SHIFT_HI2Q_TXBD_DESA_8197F)
+#define BITS_HI2Q_TXBD_DESA_8197F \
+ (BIT_MASK_HI2Q_TXBD_DESA_8197F << BIT_SHIFT_HI2Q_TXBD_DESA_8197F)
+#define BIT_CLEAR_HI2Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI2Q_TXBD_DESA_8197F))
+#define BIT_GET_HI2Q_TXBD_DESA_8197F(x) \
+ (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_8197F) & \
+ BIT_MASK_HI2Q_TXBD_DESA_8197F)
+#define BIT_SET_HI2Q_TXBD_DESA_8197F(x, v) \
+ (BIT_CLEAR_HI2Q_TXBD_DESA_8197F(x) | BIT_HI2Q_TXBD_DESA_8197F(v))
+
+/* 2 REG_HI3Q_TXBD_DESA_8197F */
+
+#define BIT_SHIFT_HI3Q_TXBD_DESA_8197F 0
+#define BIT_MASK_HI3Q_TXBD_DESA_8197F 0xffffffffffffffffL
+#define BIT_HI3Q_TXBD_DESA_8197F(x) \
+ (((x) & BIT_MASK_HI3Q_TXBD_DESA_8197F) \
+ << BIT_SHIFT_HI3Q_TXBD_DESA_8197F)
+#define BITS_HI3Q_TXBD_DESA_8197F \
+ (BIT_MASK_HI3Q_TXBD_DESA_8197F << BIT_SHIFT_HI3Q_TXBD_DESA_8197F)
+#define BIT_CLEAR_HI3Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI3Q_TXBD_DESA_8197F))
+#define BIT_GET_HI3Q_TXBD_DESA_8197F(x) \
+ (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_8197F) & \
+ BIT_MASK_HI3Q_TXBD_DESA_8197F)
+#define BIT_SET_HI3Q_TXBD_DESA_8197F(x, v) \
+ (BIT_CLEAR_HI3Q_TXBD_DESA_8197F(x) | BIT_HI3Q_TXBD_DESA_8197F(v))
+
+/* 2 REG_HI4Q_TXBD_DESA_8197F */
+
+#define BIT_SHIFT_HI4Q_TXBD_DESA_8197F 0
+#define BIT_MASK_HI4Q_TXBD_DESA_8197F 0xffffffffffffffffL
+#define BIT_HI4Q_TXBD_DESA_8197F(x) \
+ (((x) & BIT_MASK_HI4Q_TXBD_DESA_8197F) \
+ << BIT_SHIFT_HI4Q_TXBD_DESA_8197F)
+#define BITS_HI4Q_TXBD_DESA_8197F \
+ (BIT_MASK_HI4Q_TXBD_DESA_8197F << BIT_SHIFT_HI4Q_TXBD_DESA_8197F)
+#define BIT_CLEAR_HI4Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI4Q_TXBD_DESA_8197F))
+#define BIT_GET_HI4Q_TXBD_DESA_8197F(x) \
+ (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_8197F) & \
+ BIT_MASK_HI4Q_TXBD_DESA_8197F)
+#define BIT_SET_HI4Q_TXBD_DESA_8197F(x, v) \
+ (BIT_CLEAR_HI4Q_TXBD_DESA_8197F(x) | BIT_HI4Q_TXBD_DESA_8197F(v))
+
+/* 2 REG_HI5Q_TXBD_DESA_8197F */
+
+#define BIT_SHIFT_HI5Q_TXBD_DESA_8197F 0
+#define BIT_MASK_HI5Q_TXBD_DESA_8197F 0xffffffffffffffffL
+#define BIT_HI5Q_TXBD_DESA_8197F(x) \
+ (((x) & BIT_MASK_HI5Q_TXBD_DESA_8197F) \
+ << BIT_SHIFT_HI5Q_TXBD_DESA_8197F)
+#define BITS_HI5Q_TXBD_DESA_8197F \
+ (BIT_MASK_HI5Q_TXBD_DESA_8197F << BIT_SHIFT_HI5Q_TXBD_DESA_8197F)
+#define BIT_CLEAR_HI5Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI5Q_TXBD_DESA_8197F))
+#define BIT_GET_HI5Q_TXBD_DESA_8197F(x) \
+ (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_8197F) & \
+ BIT_MASK_HI5Q_TXBD_DESA_8197F)
+#define BIT_SET_HI5Q_TXBD_DESA_8197F(x, v) \
+ (BIT_CLEAR_HI5Q_TXBD_DESA_8197F(x) | BIT_HI5Q_TXBD_DESA_8197F(v))
+
+/* 2 REG_HI6Q_TXBD_DESA_8197F */
+
+#define BIT_SHIFT_HI6Q_TXBD_DESA_8197F 0
+#define BIT_MASK_HI6Q_TXBD_DESA_8197F 0xffffffffffffffffL
+#define BIT_HI6Q_TXBD_DESA_8197F(x) \
+ (((x) & BIT_MASK_HI6Q_TXBD_DESA_8197F) \
+ << BIT_SHIFT_HI6Q_TXBD_DESA_8197F)
+#define BITS_HI6Q_TXBD_DESA_8197F \
+ (BIT_MASK_HI6Q_TXBD_DESA_8197F << BIT_SHIFT_HI6Q_TXBD_DESA_8197F)
+#define BIT_CLEAR_HI6Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI6Q_TXBD_DESA_8197F))
+#define BIT_GET_HI6Q_TXBD_DESA_8197F(x) \
+ (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_8197F) & \
+ BIT_MASK_HI6Q_TXBD_DESA_8197F)
+#define BIT_SET_HI6Q_TXBD_DESA_8197F(x, v) \
+ (BIT_CLEAR_HI6Q_TXBD_DESA_8197F(x) | BIT_HI6Q_TXBD_DESA_8197F(v))
+
+/* 2 REG_HI7Q_TXBD_DESA_8197F */
+
+#define BIT_SHIFT_HI7Q_TXBD_DESA_8197F 0
+#define BIT_MASK_HI7Q_TXBD_DESA_8197F 0xffffffffffffffffL
+#define BIT_HI7Q_TXBD_DESA_8197F(x) \
+ (((x) & BIT_MASK_HI7Q_TXBD_DESA_8197F) \
+ << BIT_SHIFT_HI7Q_TXBD_DESA_8197F)
+#define BITS_HI7Q_TXBD_DESA_8197F \
+ (BIT_MASK_HI7Q_TXBD_DESA_8197F << BIT_SHIFT_HI7Q_TXBD_DESA_8197F)
+#define BIT_CLEAR_HI7Q_TXBD_DESA_8197F(x) ((x) & (~BITS_HI7Q_TXBD_DESA_8197F))
+#define BIT_GET_HI7Q_TXBD_DESA_8197F(x) \
+ (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_8197F) & \
+ BIT_MASK_HI7Q_TXBD_DESA_8197F)
+#define BIT_SET_HI7Q_TXBD_DESA_8197F(x, v) \
+ (BIT_CLEAR_HI7Q_TXBD_DESA_8197F(x) | BIT_HI7Q_TXBD_DESA_8197F(v))
+
+/* 2 REG_MGQ_TXBD_NUM_8197F */
+#define BIT_HCI_MGQ_FLAG_8197F BIT(14)
+
+#define BIT_SHIFT_MGQ_DESC_MODE_8197F 12
+#define BIT_MASK_MGQ_DESC_MODE_8197F 0x3
+#define BIT_MGQ_DESC_MODE_8197F(x) \
+ (((x) & BIT_MASK_MGQ_DESC_MODE_8197F) << BIT_SHIFT_MGQ_DESC_MODE_8197F)
+#define BITS_MGQ_DESC_MODE_8197F \
+ (BIT_MASK_MGQ_DESC_MODE_8197F << BIT_SHIFT_MGQ_DESC_MODE_8197F)
+#define BIT_CLEAR_MGQ_DESC_MODE_8197F(x) ((x) & (~BITS_MGQ_DESC_MODE_8197F))
+#define BIT_GET_MGQ_DESC_MODE_8197F(x) \
+ (((x) >> BIT_SHIFT_MGQ_DESC_MODE_8197F) & BIT_MASK_MGQ_DESC_MODE_8197F)
+#define BIT_SET_MGQ_DESC_MODE_8197F(x, v) \
+ (BIT_CLEAR_MGQ_DESC_MODE_8197F(x) | BIT_MGQ_DESC_MODE_8197F(v))
+
+#define BIT_SHIFT_MGQ_DESC_NUM_8197F 0
+#define BIT_MASK_MGQ_DESC_NUM_8197F 0xfff
+#define BIT_MGQ_DESC_NUM_8197F(x) \
+ (((x) & BIT_MASK_MGQ_DESC_NUM_8197F) << BIT_SHIFT_MGQ_DESC_NUM_8197F)
+#define BITS_MGQ_DESC_NUM_8197F \
+ (BIT_MASK_MGQ_DESC_NUM_8197F << BIT_SHIFT_MGQ_DESC_NUM_8197F)
+#define BIT_CLEAR_MGQ_DESC_NUM_8197F(x) ((x) & (~BITS_MGQ_DESC_NUM_8197F))
+#define BIT_GET_MGQ_DESC_NUM_8197F(x) \
+ (((x) >> BIT_SHIFT_MGQ_DESC_NUM_8197F) & BIT_MASK_MGQ_DESC_NUM_8197F)
+#define BIT_SET_MGQ_DESC_NUM_8197F(x, v) \
+ (BIT_CLEAR_MGQ_DESC_NUM_8197F(x) | BIT_MGQ_DESC_NUM_8197F(v))
+
+/* 2 REG_RX_RXBD_NUM_8197F */
+#define BIT_SYS_32_64_8197F BIT(15)
+
+#define BIT_SHIFT_BCNQ_DESC_MODE_8197F 13
+#define BIT_MASK_BCNQ_DESC_MODE_8197F 0x3
+#define BIT_BCNQ_DESC_MODE_8197F(x) \
+ (((x) & BIT_MASK_BCNQ_DESC_MODE_8197F) \
+ << BIT_SHIFT_BCNQ_DESC_MODE_8197F)
+#define BITS_BCNQ_DESC_MODE_8197F \
+ (BIT_MASK_BCNQ_DESC_MODE_8197F << BIT_SHIFT_BCNQ_DESC_MODE_8197F)
+#define BIT_CLEAR_BCNQ_DESC_MODE_8197F(x) ((x) & (~BITS_BCNQ_DESC_MODE_8197F))
+#define BIT_GET_BCNQ_DESC_MODE_8197F(x) \
+ (((x) >> BIT_SHIFT_BCNQ_DESC_MODE_8197F) & \
+ BIT_MASK_BCNQ_DESC_MODE_8197F)
+#define BIT_SET_BCNQ_DESC_MODE_8197F(x, v) \
+ (BIT_CLEAR_BCNQ_DESC_MODE_8197F(x) | BIT_BCNQ_DESC_MODE_8197F(v))
+
+#define BIT_HCI_BCNQ_FLAG_8197F BIT(12)
+
+#define BIT_SHIFT_RXQ_DESC_NUM_8197F 0
+#define BIT_MASK_RXQ_DESC_NUM_8197F 0xfff
+#define BIT_RXQ_DESC_NUM_8197F(x) \
+ (((x) & BIT_MASK_RXQ_DESC_NUM_8197F) << BIT_SHIFT_RXQ_DESC_NUM_8197F)
+#define BITS_RXQ_DESC_NUM_8197F \
+ (BIT_MASK_RXQ_DESC_NUM_8197F << BIT_SHIFT_RXQ_DESC_NUM_8197F)
+#define BIT_CLEAR_RXQ_DESC_NUM_8197F(x) ((x) & (~BITS_RXQ_DESC_NUM_8197F))
+#define BIT_GET_RXQ_DESC_NUM_8197F(x) \
+ (((x) >> BIT_SHIFT_RXQ_DESC_NUM_8197F) & BIT_MASK_RXQ_DESC_NUM_8197F)
+#define BIT_SET_RXQ_DESC_NUM_8197F(x, v) \
+ (BIT_CLEAR_RXQ_DESC_NUM_8197F(x) | BIT_RXQ_DESC_NUM_8197F(v))
+
+/* 2 REG_VOQ_TXBD_NUM_8197F */
+#define BIT_HCI_VOQ_FLAG_8197F BIT(14)
+
+#define BIT_SHIFT_VOQ_DESC_MODE_8197F 12
+#define BIT_MASK_VOQ_DESC_MODE_8197F 0x3
+#define BIT_VOQ_DESC_MODE_8197F(x) \
+ (((x) & BIT_MASK_VOQ_DESC_MODE_8197F) << BIT_SHIFT_VOQ_DESC_MODE_8197F)
+#define BITS_VOQ_DESC_MODE_8197F \
+ (BIT_MASK_VOQ_DESC_MODE_8197F << BIT_SHIFT_VOQ_DESC_MODE_8197F)
+#define BIT_CLEAR_VOQ_DESC_MODE_8197F(x) ((x) & (~BITS_VOQ_DESC_MODE_8197F))
+#define BIT_GET_VOQ_DESC_MODE_8197F(x) \
+ (((x) >> BIT_SHIFT_VOQ_DESC_MODE_8197F) & BIT_MASK_VOQ_DESC_MODE_8197F)
+#define BIT_SET_VOQ_DESC_MODE_8197F(x, v) \
+ (BIT_CLEAR_VOQ_DESC_MODE_8197F(x) | BIT_VOQ_DESC_MODE_8197F(v))
+
+#define BIT_SHIFT_VOQ_DESC_NUM_8197F 0
+#define BIT_MASK_VOQ_DESC_NUM_8197F 0xfff
+#define BIT_VOQ_DESC_NUM_8197F(x) \
+ (((x) & BIT_MASK_VOQ_DESC_NUM_8197F) << BIT_SHIFT_VOQ_DESC_NUM_8197F)
+#define BITS_VOQ_DESC_NUM_8197F \
+ (BIT_MASK_VOQ_DESC_NUM_8197F << BIT_SHIFT_VOQ_DESC_NUM_8197F)
+#define BIT_CLEAR_VOQ_DESC_NUM_8197F(x) ((x) & (~BITS_VOQ_DESC_NUM_8197F))
+#define BIT_GET_VOQ_DESC_NUM_8197F(x) \
+ (((x) >> BIT_SHIFT_VOQ_DESC_NUM_8197F) & BIT_MASK_VOQ_DESC_NUM_8197F)
+#define BIT_SET_VOQ_DESC_NUM_8197F(x, v) \
+ (BIT_CLEAR_VOQ_DESC_NUM_8197F(x) | BIT_VOQ_DESC_NUM_8197F(v))
+
+/* 2 REG_VIQ_TXBD_NUM_8197F */
+#define BIT_HCI_VIQ_FLAG_8197F BIT(14)
+
+#define BIT_SHIFT_VIQ_DESC_MODE_8197F 12
+#define BIT_MASK_VIQ_DESC_MODE_8197F 0x3
+#define BIT_VIQ_DESC_MODE_8197F(x) \
+ (((x) & BIT_MASK_VIQ_DESC_MODE_8197F) << BIT_SHIFT_VIQ_DESC_MODE_8197F)
+#define BITS_VIQ_DESC_MODE_8197F \
+ (BIT_MASK_VIQ_DESC_MODE_8197F << BIT_SHIFT_VIQ_DESC_MODE_8197F)
+#define BIT_CLEAR_VIQ_DESC_MODE_8197F(x) ((x) & (~BITS_VIQ_DESC_MODE_8197F))
+#define BIT_GET_VIQ_DESC_MODE_8197F(x) \
+ (((x) >> BIT_SHIFT_VIQ_DESC_MODE_8197F) & BIT_MASK_VIQ_DESC_MODE_8197F)
+#define BIT_SET_VIQ_DESC_MODE_8197F(x, v) \
+ (BIT_CLEAR_VIQ_DESC_MODE_8197F(x) | BIT_VIQ_DESC_MODE_8197F(v))
+
+#define BIT_SHIFT_VIQ_DESC_NUM_8197F 0
+#define BIT_MASK_VIQ_DESC_NUM_8197F 0xfff
+#define BIT_VIQ_DESC_NUM_8197F(x) \
+ (((x) & BIT_MASK_VIQ_DESC_NUM_8197F) << BIT_SHIFT_VIQ_DESC_NUM_8197F)
+#define BITS_VIQ_DESC_NUM_8197F \
+ (BIT_MASK_VIQ_DESC_NUM_8197F << BIT_SHIFT_VIQ_DESC_NUM_8197F)
+#define BIT_CLEAR_VIQ_DESC_NUM_8197F(x) ((x) & (~BITS_VIQ_DESC_NUM_8197F))
+#define BIT_GET_VIQ_DESC_NUM_8197F(x) \
+ (((x) >> BIT_SHIFT_VIQ_DESC_NUM_8197F) & BIT_MASK_VIQ_DESC_NUM_8197F)
+#define BIT_SET_VIQ_DESC_NUM_8197F(x, v) \
+ (BIT_CLEAR_VIQ_DESC_NUM_8197F(x) | BIT_VIQ_DESC_NUM_8197F(v))
+
+/* 2 REG_BEQ_TXBD_NUM_8197F */
+#define BIT_HCI_BEQ_FLAG_8197F BIT(14)
+
+#define BIT_SHIFT_BEQ_DESC_MODE_8197F 12
+#define BIT_MASK_BEQ_DESC_MODE_8197F 0x3
+#define BIT_BEQ_DESC_MODE_8197F(x) \
+ (((x) & BIT_MASK_BEQ_DESC_MODE_8197F) << BIT_SHIFT_BEQ_DESC_MODE_8197F)
+#define BITS_BEQ_DESC_MODE_8197F \
+ (BIT_MASK_BEQ_DESC_MODE_8197F << BIT_SHIFT_BEQ_DESC_MODE_8197F)
+#define BIT_CLEAR_BEQ_DESC_MODE_8197F(x) ((x) & (~BITS_BEQ_DESC_MODE_8197F))
+#define BIT_GET_BEQ_DESC_MODE_8197F(x) \
+ (((x) >> BIT_SHIFT_BEQ_DESC_MODE_8197F) & BIT_MASK_BEQ_DESC_MODE_8197F)
+#define BIT_SET_BEQ_DESC_MODE_8197F(x, v) \
+ (BIT_CLEAR_BEQ_DESC_MODE_8197F(x) | BIT_BEQ_DESC_MODE_8197F(v))
+
+#define BIT_SHIFT_BEQ_DESC_NUM_8197F 0
+#define BIT_MASK_BEQ_DESC_NUM_8197F 0xfff
+#define BIT_BEQ_DESC_NUM_8197F(x) \
+ (((x) & BIT_MASK_BEQ_DESC_NUM_8197F) << BIT_SHIFT_BEQ_DESC_NUM_8197F)
+#define BITS_BEQ_DESC_NUM_8197F \
+ (BIT_MASK_BEQ_DESC_NUM_8197F << BIT_SHIFT_BEQ_DESC_NUM_8197F)
+#define BIT_CLEAR_BEQ_DESC_NUM_8197F(x) ((x) & (~BITS_BEQ_DESC_NUM_8197F))
+#define BIT_GET_BEQ_DESC_NUM_8197F(x) \
+ (((x) >> BIT_SHIFT_BEQ_DESC_NUM_8197F) & BIT_MASK_BEQ_DESC_NUM_8197F)
+#define BIT_SET_BEQ_DESC_NUM_8197F(x, v) \
+ (BIT_CLEAR_BEQ_DESC_NUM_8197F(x) | BIT_BEQ_DESC_NUM_8197F(v))
+
+/* 2 REG_BKQ_TXBD_NUM_8197F */
+#define BIT_HCI_BKQ_FLAG_8197F BIT(14)
+
+#define BIT_SHIFT_BKQ_DESC_MODE_8197F 12
+#define BIT_MASK_BKQ_DESC_MODE_8197F 0x3
+#define BIT_BKQ_DESC_MODE_8197F(x) \
+ (((x) & BIT_MASK_BKQ_DESC_MODE_8197F) << BIT_SHIFT_BKQ_DESC_MODE_8197F)
+#define BITS_BKQ_DESC_MODE_8197F \
+ (BIT_MASK_BKQ_DESC_MODE_8197F << BIT_SHIFT_BKQ_DESC_MODE_8197F)
+#define BIT_CLEAR_BKQ_DESC_MODE_8197F(x) ((x) & (~BITS_BKQ_DESC_MODE_8197F))
+#define BIT_GET_BKQ_DESC_MODE_8197F(x) \
+ (((x) >> BIT_SHIFT_BKQ_DESC_MODE_8197F) & BIT_MASK_BKQ_DESC_MODE_8197F)
+#define BIT_SET_BKQ_DESC_MODE_8197F(x, v) \
+ (BIT_CLEAR_BKQ_DESC_MODE_8197F(x) | BIT_BKQ_DESC_MODE_8197F(v))
+
+#define BIT_SHIFT_BKQ_DESC_NUM_8197F 0
+#define BIT_MASK_BKQ_DESC_NUM_8197F 0xfff
+#define BIT_BKQ_DESC_NUM_8197F(x) \
+ (((x) & BIT_MASK_BKQ_DESC_NUM_8197F) << BIT_SHIFT_BKQ_DESC_NUM_8197F)
+#define BITS_BKQ_DESC_NUM_8197F \
+ (BIT_MASK_BKQ_DESC_NUM_8197F << BIT_SHIFT_BKQ_DESC_NUM_8197F)
+#define BIT_CLEAR_BKQ_DESC_NUM_8197F(x) ((x) & (~BITS_BKQ_DESC_NUM_8197F))
+#define BIT_GET_BKQ_DESC_NUM_8197F(x) \
+ (((x) >> BIT_SHIFT_BKQ_DESC_NUM_8197F) & BIT_MASK_BKQ_DESC_NUM_8197F)
+#define BIT_SET_BKQ_DESC_NUM_8197F(x, v) \
+ (BIT_CLEAR_BKQ_DESC_NUM_8197F(x) | BIT_BKQ_DESC_NUM_8197F(v))
+
+/* 2 REG_HI0Q_TXBD_NUM_8197F */
+#define BIT_HI0Q_FLAG_8197F BIT(14)
+
+#define BIT_SHIFT_HI0Q_DESC_MODE_8197F 12
+#define BIT_MASK_HI0Q_DESC_MODE_8197F 0x3
+#define BIT_HI0Q_DESC_MODE_8197F(x) \
+ (((x) & BIT_MASK_HI0Q_DESC_MODE_8197F) \
+ << BIT_SHIFT_HI0Q_DESC_MODE_8197F)
+#define BITS_HI0Q_DESC_MODE_8197F \
+ (BIT_MASK_HI0Q_DESC_MODE_8197F << BIT_SHIFT_HI0Q_DESC_MODE_8197F)
+#define BIT_CLEAR_HI0Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI0Q_DESC_MODE_8197F))
+#define BIT_GET_HI0Q_DESC_MODE_8197F(x) \
+ (((x) >> BIT_SHIFT_HI0Q_DESC_MODE_8197F) & \
+ BIT_MASK_HI0Q_DESC_MODE_8197F)
+#define BIT_SET_HI0Q_DESC_MODE_8197F(x, v) \
+ (BIT_CLEAR_HI0Q_DESC_MODE_8197F(x) | BIT_HI0Q_DESC_MODE_8197F(v))
+
+#define BIT_SHIFT_HI0Q_DESC_NUM_8197F 0
+#define BIT_MASK_HI0Q_DESC_NUM_8197F 0xfff
+#define BIT_HI0Q_DESC_NUM_8197F(x) \
+ (((x) & BIT_MASK_HI0Q_DESC_NUM_8197F) << BIT_SHIFT_HI0Q_DESC_NUM_8197F)
+#define BITS_HI0Q_DESC_NUM_8197F \
+ (BIT_MASK_HI0Q_DESC_NUM_8197F << BIT_SHIFT_HI0Q_DESC_NUM_8197F)
+#define BIT_CLEAR_HI0Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI0Q_DESC_NUM_8197F))
+#define BIT_GET_HI0Q_DESC_NUM_8197F(x) \
+ (((x) >> BIT_SHIFT_HI0Q_DESC_NUM_8197F) & BIT_MASK_HI0Q_DESC_NUM_8197F)
+#define BIT_SET_HI0Q_DESC_NUM_8197F(x, v) \
+ (BIT_CLEAR_HI0Q_DESC_NUM_8197F(x) | BIT_HI0Q_DESC_NUM_8197F(v))
+
+/* 2 REG_HI1Q_TXBD_NUM_8197F */
+#define BIT_HI1Q_FLAG_8197F BIT(14)
+
+#define BIT_SHIFT_HI1Q_DESC_MODE_8197F 12
+#define BIT_MASK_HI1Q_DESC_MODE_8197F 0x3
+#define BIT_HI1Q_DESC_MODE_8197F(x) \
+ (((x) & BIT_MASK_HI1Q_DESC_MODE_8197F) \
+ << BIT_SHIFT_HI1Q_DESC_MODE_8197F)
+#define BITS_HI1Q_DESC_MODE_8197F \
+ (BIT_MASK_HI1Q_DESC_MODE_8197F << BIT_SHIFT_HI1Q_DESC_MODE_8197F)
+#define BIT_CLEAR_HI1Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI1Q_DESC_MODE_8197F))
+#define BIT_GET_HI1Q_DESC_MODE_8197F(x) \
+ (((x) >> BIT_SHIFT_HI1Q_DESC_MODE_8197F) & \
+ BIT_MASK_HI1Q_DESC_MODE_8197F)
+#define BIT_SET_HI1Q_DESC_MODE_8197F(x, v) \
+ (BIT_CLEAR_HI1Q_DESC_MODE_8197F(x) | BIT_HI1Q_DESC_MODE_8197F(v))
+
+#define BIT_SHIFT_HI1Q_DESC_NUM_8197F 0
+#define BIT_MASK_HI1Q_DESC_NUM_8197F 0xfff
+#define BIT_HI1Q_DESC_NUM_8197F(x) \
+ (((x) & BIT_MASK_HI1Q_DESC_NUM_8197F) << BIT_SHIFT_HI1Q_DESC_NUM_8197F)
+#define BITS_HI1Q_DESC_NUM_8197F \
+ (BIT_MASK_HI1Q_DESC_NUM_8197F << BIT_SHIFT_HI1Q_DESC_NUM_8197F)
+#define BIT_CLEAR_HI1Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI1Q_DESC_NUM_8197F))
+#define BIT_GET_HI1Q_DESC_NUM_8197F(x) \
+ (((x) >> BIT_SHIFT_HI1Q_DESC_NUM_8197F) & BIT_MASK_HI1Q_DESC_NUM_8197F)
+#define BIT_SET_HI1Q_DESC_NUM_8197F(x, v) \
+ (BIT_CLEAR_HI1Q_DESC_NUM_8197F(x) | BIT_HI1Q_DESC_NUM_8197F(v))
+
+/* 2 REG_HI2Q_TXBD_NUM_8197F */
+#define BIT_HI2Q_FLAG_8197F BIT(14)
+
+#define BIT_SHIFT_HI2Q_DESC_MODE_8197F 12
+#define BIT_MASK_HI2Q_DESC_MODE_8197F 0x3
+#define BIT_HI2Q_DESC_MODE_8197F(x) \
+ (((x) & BIT_MASK_HI2Q_DESC_MODE_8197F) \
+ << BIT_SHIFT_HI2Q_DESC_MODE_8197F)
+#define BITS_HI2Q_DESC_MODE_8197F \
+ (BIT_MASK_HI2Q_DESC_MODE_8197F << BIT_SHIFT_HI2Q_DESC_MODE_8197F)
+#define BIT_CLEAR_HI2Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI2Q_DESC_MODE_8197F))
+#define BIT_GET_HI2Q_DESC_MODE_8197F(x) \
+ (((x) >> BIT_SHIFT_HI2Q_DESC_MODE_8197F) & \
+ BIT_MASK_HI2Q_DESC_MODE_8197F)
+#define BIT_SET_HI2Q_DESC_MODE_8197F(x, v) \
+ (BIT_CLEAR_HI2Q_DESC_MODE_8197F(x) | BIT_HI2Q_DESC_MODE_8197F(v))
+
+#define BIT_SHIFT_HI2Q_DESC_NUM_8197F 0
+#define BIT_MASK_HI2Q_DESC_NUM_8197F 0xfff
+#define BIT_HI2Q_DESC_NUM_8197F(x) \
+ (((x) & BIT_MASK_HI2Q_DESC_NUM_8197F) << BIT_SHIFT_HI2Q_DESC_NUM_8197F)
+#define BITS_HI2Q_DESC_NUM_8197F \
+ (BIT_MASK_HI2Q_DESC_NUM_8197F << BIT_SHIFT_HI2Q_DESC_NUM_8197F)
+#define BIT_CLEAR_HI2Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI2Q_DESC_NUM_8197F))
+#define BIT_GET_HI2Q_DESC_NUM_8197F(x) \
+ (((x) >> BIT_SHIFT_HI2Q_DESC_NUM_8197F) & BIT_MASK_HI2Q_DESC_NUM_8197F)
+#define BIT_SET_HI2Q_DESC_NUM_8197F(x, v) \
+ (BIT_CLEAR_HI2Q_DESC_NUM_8197F(x) | BIT_HI2Q_DESC_NUM_8197F(v))
+
+/* 2 REG_HI3Q_TXBD_NUM_8197F */
+#define BIT_HI3Q_FLAG_8197F BIT(14)
+
+#define BIT_SHIFT_HI3Q_DESC_MODE_8197F 12
+#define BIT_MASK_HI3Q_DESC_MODE_8197F 0x3
+#define BIT_HI3Q_DESC_MODE_8197F(x) \
+ (((x) & BIT_MASK_HI3Q_DESC_MODE_8197F) \
+ << BIT_SHIFT_HI3Q_DESC_MODE_8197F)
+#define BITS_HI3Q_DESC_MODE_8197F \
+ (BIT_MASK_HI3Q_DESC_MODE_8197F << BIT_SHIFT_HI3Q_DESC_MODE_8197F)
+#define BIT_CLEAR_HI3Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI3Q_DESC_MODE_8197F))
+#define BIT_GET_HI3Q_DESC_MODE_8197F(x) \
+ (((x) >> BIT_SHIFT_HI3Q_DESC_MODE_8197F) & \
+ BIT_MASK_HI3Q_DESC_MODE_8197F)
+#define BIT_SET_HI3Q_DESC_MODE_8197F(x, v) \
+ (BIT_CLEAR_HI3Q_DESC_MODE_8197F(x) | BIT_HI3Q_DESC_MODE_8197F(v))
+
+#define BIT_SHIFT_HI3Q_DESC_NUM_8197F 0
+#define BIT_MASK_HI3Q_DESC_NUM_8197F 0xfff
+#define BIT_HI3Q_DESC_NUM_8197F(x) \
+ (((x) & BIT_MASK_HI3Q_DESC_NUM_8197F) << BIT_SHIFT_HI3Q_DESC_NUM_8197F)
+#define BITS_HI3Q_DESC_NUM_8197F \
+ (BIT_MASK_HI3Q_DESC_NUM_8197F << BIT_SHIFT_HI3Q_DESC_NUM_8197F)
+#define BIT_CLEAR_HI3Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI3Q_DESC_NUM_8197F))
+#define BIT_GET_HI3Q_DESC_NUM_8197F(x) \
+ (((x) >> BIT_SHIFT_HI3Q_DESC_NUM_8197F) & BIT_MASK_HI3Q_DESC_NUM_8197F)
+#define BIT_SET_HI3Q_DESC_NUM_8197F(x, v) \
+ (BIT_CLEAR_HI3Q_DESC_NUM_8197F(x) | BIT_HI3Q_DESC_NUM_8197F(v))
+
+/* 2 REG_HI4Q_TXBD_NUM_8197F */
+#define BIT_HI4Q_FLAG_8197F BIT(14)
+
+#define BIT_SHIFT_HI4Q_DESC_MODE_8197F 12
+#define BIT_MASK_HI4Q_DESC_MODE_8197F 0x3
+#define BIT_HI4Q_DESC_MODE_8197F(x) \
+ (((x) & BIT_MASK_HI4Q_DESC_MODE_8197F) \
+ << BIT_SHIFT_HI4Q_DESC_MODE_8197F)
+#define BITS_HI4Q_DESC_MODE_8197F \
+ (BIT_MASK_HI4Q_DESC_MODE_8197F << BIT_SHIFT_HI4Q_DESC_MODE_8197F)
+#define BIT_CLEAR_HI4Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI4Q_DESC_MODE_8197F))
+#define BIT_GET_HI4Q_DESC_MODE_8197F(x) \
+ (((x) >> BIT_SHIFT_HI4Q_DESC_MODE_8197F) & \
+ BIT_MASK_HI4Q_DESC_MODE_8197F)
+#define BIT_SET_HI4Q_DESC_MODE_8197F(x, v) \
+ (BIT_CLEAR_HI4Q_DESC_MODE_8197F(x) | BIT_HI4Q_DESC_MODE_8197F(v))
+
+#define BIT_SHIFT_HI4Q_DESC_NUM_8197F 0
+#define BIT_MASK_HI4Q_DESC_NUM_8197F 0xfff
+#define BIT_HI4Q_DESC_NUM_8197F(x) \
+ (((x) & BIT_MASK_HI4Q_DESC_NUM_8197F) << BIT_SHIFT_HI4Q_DESC_NUM_8197F)
+#define BITS_HI4Q_DESC_NUM_8197F \
+ (BIT_MASK_HI4Q_DESC_NUM_8197F << BIT_SHIFT_HI4Q_DESC_NUM_8197F)
+#define BIT_CLEAR_HI4Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI4Q_DESC_NUM_8197F))
+#define BIT_GET_HI4Q_DESC_NUM_8197F(x) \
+ (((x) >> BIT_SHIFT_HI4Q_DESC_NUM_8197F) & BIT_MASK_HI4Q_DESC_NUM_8197F)
+#define BIT_SET_HI4Q_DESC_NUM_8197F(x, v) \
+ (BIT_CLEAR_HI4Q_DESC_NUM_8197F(x) | BIT_HI4Q_DESC_NUM_8197F(v))
+
+/* 2 REG_HI5Q_TXBD_NUM_8197F */
+#define BIT_HI5Q_FLAG_8197F BIT(14)
+
+#define BIT_SHIFT_HI5Q_DESC_MODE_8197F 12
+#define BIT_MASK_HI5Q_DESC_MODE_8197F 0x3
+#define BIT_HI5Q_DESC_MODE_8197F(x) \
+ (((x) & BIT_MASK_HI5Q_DESC_MODE_8197F) \
+ << BIT_SHIFT_HI5Q_DESC_MODE_8197F)
+#define BITS_HI5Q_DESC_MODE_8197F \
+ (BIT_MASK_HI5Q_DESC_MODE_8197F << BIT_SHIFT_HI5Q_DESC_MODE_8197F)
+#define BIT_CLEAR_HI5Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI5Q_DESC_MODE_8197F))
+#define BIT_GET_HI5Q_DESC_MODE_8197F(x) \
+ (((x) >> BIT_SHIFT_HI5Q_DESC_MODE_8197F) & \
+ BIT_MASK_HI5Q_DESC_MODE_8197F)
+#define BIT_SET_HI5Q_DESC_MODE_8197F(x, v) \
+ (BIT_CLEAR_HI5Q_DESC_MODE_8197F(x) | BIT_HI5Q_DESC_MODE_8197F(v))
+
+#define BIT_SHIFT_HI5Q_DESC_NUM_8197F 0
+#define BIT_MASK_HI5Q_DESC_NUM_8197F 0xfff
+#define BIT_HI5Q_DESC_NUM_8197F(x) \
+ (((x) & BIT_MASK_HI5Q_DESC_NUM_8197F) << BIT_SHIFT_HI5Q_DESC_NUM_8197F)
+#define BITS_HI5Q_DESC_NUM_8197F \
+ (BIT_MASK_HI5Q_DESC_NUM_8197F << BIT_SHIFT_HI5Q_DESC_NUM_8197F)
+#define BIT_CLEAR_HI5Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI5Q_DESC_NUM_8197F))
+#define BIT_GET_HI5Q_DESC_NUM_8197F(x) \
+ (((x) >> BIT_SHIFT_HI5Q_DESC_NUM_8197F) & BIT_MASK_HI5Q_DESC_NUM_8197F)
+#define BIT_SET_HI5Q_DESC_NUM_8197F(x, v) \
+ (BIT_CLEAR_HI5Q_DESC_NUM_8197F(x) | BIT_HI5Q_DESC_NUM_8197F(v))
+
+/* 2 REG_HI6Q_TXBD_NUM_8197F */
+#define BIT_HI6Q_FLAG_8197F BIT(14)
+
+#define BIT_SHIFT_HI6Q_DESC_MODE_8197F 12
+#define BIT_MASK_HI6Q_DESC_MODE_8197F 0x3
+#define BIT_HI6Q_DESC_MODE_8197F(x) \
+ (((x) & BIT_MASK_HI6Q_DESC_MODE_8197F) \
+ << BIT_SHIFT_HI6Q_DESC_MODE_8197F)
+#define BITS_HI6Q_DESC_MODE_8197F \
+ (BIT_MASK_HI6Q_DESC_MODE_8197F << BIT_SHIFT_HI6Q_DESC_MODE_8197F)
+#define BIT_CLEAR_HI6Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI6Q_DESC_MODE_8197F))
+#define BIT_GET_HI6Q_DESC_MODE_8197F(x) \
+ (((x) >> BIT_SHIFT_HI6Q_DESC_MODE_8197F) & \
+ BIT_MASK_HI6Q_DESC_MODE_8197F)
+#define BIT_SET_HI6Q_DESC_MODE_8197F(x, v) \
+ (BIT_CLEAR_HI6Q_DESC_MODE_8197F(x) | BIT_HI6Q_DESC_MODE_8197F(v))
+
+#define BIT_SHIFT_HI6Q_DESC_NUM_8197F 0
+#define BIT_MASK_HI6Q_DESC_NUM_8197F 0xfff
+#define BIT_HI6Q_DESC_NUM_8197F(x) \
+ (((x) & BIT_MASK_HI6Q_DESC_NUM_8197F) << BIT_SHIFT_HI6Q_DESC_NUM_8197F)
+#define BITS_HI6Q_DESC_NUM_8197F \
+ (BIT_MASK_HI6Q_DESC_NUM_8197F << BIT_SHIFT_HI6Q_DESC_NUM_8197F)
+#define BIT_CLEAR_HI6Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI6Q_DESC_NUM_8197F))
+#define BIT_GET_HI6Q_DESC_NUM_8197F(x) \
+ (((x) >> BIT_SHIFT_HI6Q_DESC_NUM_8197F) & BIT_MASK_HI6Q_DESC_NUM_8197F)
+#define BIT_SET_HI6Q_DESC_NUM_8197F(x, v) \
+ (BIT_CLEAR_HI6Q_DESC_NUM_8197F(x) | BIT_HI6Q_DESC_NUM_8197F(v))
+
+/* 2 REG_HI7Q_TXBD_NUM_8197F */
+#define BIT_HI7Q_FLAG_8197F BIT(14)
+
+#define BIT_SHIFT_HI7Q_DESC_MODE_8197F 12
+#define BIT_MASK_HI7Q_DESC_MODE_8197F 0x3
+#define BIT_HI7Q_DESC_MODE_8197F(x) \
+ (((x) & BIT_MASK_HI7Q_DESC_MODE_8197F) \
+ << BIT_SHIFT_HI7Q_DESC_MODE_8197F)
+#define BITS_HI7Q_DESC_MODE_8197F \
+ (BIT_MASK_HI7Q_DESC_MODE_8197F << BIT_SHIFT_HI7Q_DESC_MODE_8197F)
+#define BIT_CLEAR_HI7Q_DESC_MODE_8197F(x) ((x) & (~BITS_HI7Q_DESC_MODE_8197F))
+#define BIT_GET_HI7Q_DESC_MODE_8197F(x) \
+ (((x) >> BIT_SHIFT_HI7Q_DESC_MODE_8197F) & \
+ BIT_MASK_HI7Q_DESC_MODE_8197F)
+#define BIT_SET_HI7Q_DESC_MODE_8197F(x, v) \
+ (BIT_CLEAR_HI7Q_DESC_MODE_8197F(x) | BIT_HI7Q_DESC_MODE_8197F(v))
+
+#define BIT_SHIFT_HI7Q_DESC_NUM_8197F 0
+#define BIT_MASK_HI7Q_DESC_NUM_8197F 0xfff
+#define BIT_HI7Q_DESC_NUM_8197F(x) \
+ (((x) & BIT_MASK_HI7Q_DESC_NUM_8197F) << BIT_SHIFT_HI7Q_DESC_NUM_8197F)
+#define BITS_HI7Q_DESC_NUM_8197F \
+ (BIT_MASK_HI7Q_DESC_NUM_8197F << BIT_SHIFT_HI7Q_DESC_NUM_8197F)
+#define BIT_CLEAR_HI7Q_DESC_NUM_8197F(x) ((x) & (~BITS_HI7Q_DESC_NUM_8197F))
+#define BIT_GET_HI7Q_DESC_NUM_8197F(x) \
+ (((x) >> BIT_SHIFT_HI7Q_DESC_NUM_8197F) & BIT_MASK_HI7Q_DESC_NUM_8197F)
+#define BIT_SET_HI7Q_DESC_NUM_8197F(x, v) \
+ (BIT_CLEAR_HI7Q_DESC_NUM_8197F(x) | BIT_HI7Q_DESC_NUM_8197F(v))
+
+/* 2 REG_TSFTIMER_HCI_8197F */
+
+#define BIT_SHIFT_TSFT2_HCI_8197F 16
+#define BIT_MASK_TSFT2_HCI_8197F 0xffff
+#define BIT_TSFT2_HCI_8197F(x) \
+ (((x) & BIT_MASK_TSFT2_HCI_8197F) << BIT_SHIFT_TSFT2_HCI_8197F)
+#define BITS_TSFT2_HCI_8197F \
+ (BIT_MASK_TSFT2_HCI_8197F << BIT_SHIFT_TSFT2_HCI_8197F)
+#define BIT_CLEAR_TSFT2_HCI_8197F(x) ((x) & (~BITS_TSFT2_HCI_8197F))
+#define BIT_GET_TSFT2_HCI_8197F(x) \
+ (((x) >> BIT_SHIFT_TSFT2_HCI_8197F) & BIT_MASK_TSFT2_HCI_8197F)
+#define BIT_SET_TSFT2_HCI_8197F(x, v) \
+ (BIT_CLEAR_TSFT2_HCI_8197F(x) | BIT_TSFT2_HCI_8197F(v))
+
+#define BIT_SHIFT_TSFT1_HCI_8197F 0
+#define BIT_MASK_TSFT1_HCI_8197F 0xffff
+#define BIT_TSFT1_HCI_8197F(x) \
+ (((x) & BIT_MASK_TSFT1_HCI_8197F) << BIT_SHIFT_TSFT1_HCI_8197F)
+#define BITS_TSFT1_HCI_8197F \
+ (BIT_MASK_TSFT1_HCI_8197F << BIT_SHIFT_TSFT1_HCI_8197F)
+#define BIT_CLEAR_TSFT1_HCI_8197F(x) ((x) & (~BITS_TSFT1_HCI_8197F))
+#define BIT_GET_TSFT1_HCI_8197F(x) \
+ (((x) >> BIT_SHIFT_TSFT1_HCI_8197F) & BIT_MASK_TSFT1_HCI_8197F)
+#define BIT_SET_TSFT1_HCI_8197F(x, v) \
+ (BIT_CLEAR_TSFT1_HCI_8197F(x) | BIT_TSFT1_HCI_8197F(v))
+
+/* 2 REG_BD_RWPTR_CLR_8197F */
+#define BIT_CLR_HI7Q_HW_IDX_8197F BIT(29)
+#define BIT_CLR_HI6Q_HW_IDX_8197F BIT(28)
+#define BIT_CLR_HI5Q_HW_IDX_8197F BIT(27)
+#define BIT_CLR_HI4Q_HW_IDX_8197F BIT(26)
+#define BIT_CLR_HI3Q_HW_IDX_8197F BIT(25)
+#define BIT_CLR_HI2Q_HW_IDX_8197F BIT(24)
+#define BIT_CLR_HI1Q_HW_IDX_8197F BIT(23)
+#define BIT_CLR_HI0Q_HW_IDX_8197F BIT(22)
+#define BIT_CLR_BKQ_HW_IDX_8197F BIT(21)
+#define BIT_CLR_BEQ_HW_IDX_8197F BIT(20)
+#define BIT_CLR_VIQ_HW_IDX_8197F BIT(19)
+#define BIT_CLR_VOQ_HW_IDX_8197F BIT(18)
+#define BIT_CLR_MGQ_HW_IDX_8197F BIT(17)
+#define BIT_CLR_RXQ_HW_IDX_8197F BIT(16)
+#define BIT_CLR_HI7Q_HOST_IDX_8197F BIT(13)
+#define BIT_CLR_HI6Q_HOST_IDX_8197F BIT(12)
+#define BIT_CLR_HI5Q_HOST_IDX_8197F BIT(11)
+#define BIT_CLR_HI4Q_HOST_IDX_8197F BIT(10)
+#define BIT_CLR_HI3Q_HOST_IDX_8197F BIT(9)
+#define BIT_CLR_HI2Q_HOST_IDX_8197F BIT(8)
+#define BIT_CLR_HI1Q_HOST_IDX_8197F BIT(7)
+#define BIT_CLR_HI0Q_HOST_IDX_8197F BIT(6)
+#define BIT_CLR_BKQ_HOST_IDX_8197F BIT(5)
+#define BIT_CLR_BEQ_HOST_IDX_8197F BIT(4)
+#define BIT_CLR_VIQ_HOST_IDX_8197F BIT(3)
+#define BIT_CLR_VOQ_HOST_IDX_8197F BIT(2)
+#define BIT_CLR_MGQ_HOST_IDX_8197F BIT(1)
+#define BIT_CLR_RXQ_HOST_IDX_8197F BIT(0)
+
+/* 2 REG_VOQ_TXBD_IDX_8197F */
+
+#define BIT_SHIFT_VOQ_HW_IDX_8197F 16
+#define BIT_MASK_VOQ_HW_IDX_8197F 0xfff
+#define BIT_VOQ_HW_IDX_8197F(x) \
+ (((x) & BIT_MASK_VOQ_HW_IDX_8197F) << BIT_SHIFT_VOQ_HW_IDX_8197F)
+#define BITS_VOQ_HW_IDX_8197F \
+ (BIT_MASK_VOQ_HW_IDX_8197F << BIT_SHIFT_VOQ_HW_IDX_8197F)
+#define BIT_CLEAR_VOQ_HW_IDX_8197F(x) ((x) & (~BITS_VOQ_HW_IDX_8197F))
+#define BIT_GET_VOQ_HW_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_VOQ_HW_IDX_8197F) & BIT_MASK_VOQ_HW_IDX_8197F)
+#define BIT_SET_VOQ_HW_IDX_8197F(x, v) \
+ (BIT_CLEAR_VOQ_HW_IDX_8197F(x) | BIT_VOQ_HW_IDX_8197F(v))
+
+#define BIT_SHIFT_VOQ_HOST_IDX_8197F 0
+#define BIT_MASK_VOQ_HOST_IDX_8197F 0xfff
+#define BIT_VOQ_HOST_IDX_8197F(x) \
+ (((x) & BIT_MASK_VOQ_HOST_IDX_8197F) << BIT_SHIFT_VOQ_HOST_IDX_8197F)
+#define BITS_VOQ_HOST_IDX_8197F \
+ (BIT_MASK_VOQ_HOST_IDX_8197F << BIT_SHIFT_VOQ_HOST_IDX_8197F)
+#define BIT_CLEAR_VOQ_HOST_IDX_8197F(x) ((x) & (~BITS_VOQ_HOST_IDX_8197F))
+#define BIT_GET_VOQ_HOST_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_VOQ_HOST_IDX_8197F) & BIT_MASK_VOQ_HOST_IDX_8197F)
+#define BIT_SET_VOQ_HOST_IDX_8197F(x, v) \
+ (BIT_CLEAR_VOQ_HOST_IDX_8197F(x) | BIT_VOQ_HOST_IDX_8197F(v))
+
+/* 2 REG_VIQ_TXBD_IDX_8197F */
+
+#define BIT_SHIFT_VIQ_HW_IDX_8197F 16
+#define BIT_MASK_VIQ_HW_IDX_8197F 0xfff
+#define BIT_VIQ_HW_IDX_8197F(x) \
+ (((x) & BIT_MASK_VIQ_HW_IDX_8197F) << BIT_SHIFT_VIQ_HW_IDX_8197F)
+#define BITS_VIQ_HW_IDX_8197F \
+ (BIT_MASK_VIQ_HW_IDX_8197F << BIT_SHIFT_VIQ_HW_IDX_8197F)
+#define BIT_CLEAR_VIQ_HW_IDX_8197F(x) ((x) & (~BITS_VIQ_HW_IDX_8197F))
+#define BIT_GET_VIQ_HW_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_VIQ_HW_IDX_8197F) & BIT_MASK_VIQ_HW_IDX_8197F)
+#define BIT_SET_VIQ_HW_IDX_8197F(x, v) \
+ (BIT_CLEAR_VIQ_HW_IDX_8197F(x) | BIT_VIQ_HW_IDX_8197F(v))
+
+#define BIT_SHIFT_VIQ_HOST_IDX_8197F 0
+#define BIT_MASK_VIQ_HOST_IDX_8197F 0xfff
+#define BIT_VIQ_HOST_IDX_8197F(x) \
+ (((x) & BIT_MASK_VIQ_HOST_IDX_8197F) << BIT_SHIFT_VIQ_HOST_IDX_8197F)
+#define BITS_VIQ_HOST_IDX_8197F \
+ (BIT_MASK_VIQ_HOST_IDX_8197F << BIT_SHIFT_VIQ_HOST_IDX_8197F)
+#define BIT_CLEAR_VIQ_HOST_IDX_8197F(x) ((x) & (~BITS_VIQ_HOST_IDX_8197F))
+#define BIT_GET_VIQ_HOST_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_VIQ_HOST_IDX_8197F) & BIT_MASK_VIQ_HOST_IDX_8197F)
+#define BIT_SET_VIQ_HOST_IDX_8197F(x, v) \
+ (BIT_CLEAR_VIQ_HOST_IDX_8197F(x) | BIT_VIQ_HOST_IDX_8197F(v))
+
+/* 2 REG_BEQ_TXBD_IDX_8197F */
+
+#define BIT_SHIFT_BEQ_HW_IDX_8197F 16
+#define BIT_MASK_BEQ_HW_IDX_8197F 0xfff
+#define BIT_BEQ_HW_IDX_8197F(x) \
+ (((x) & BIT_MASK_BEQ_HW_IDX_8197F) << BIT_SHIFT_BEQ_HW_IDX_8197F)
+#define BITS_BEQ_HW_IDX_8197F \
+ (BIT_MASK_BEQ_HW_IDX_8197F << BIT_SHIFT_BEQ_HW_IDX_8197F)
+#define BIT_CLEAR_BEQ_HW_IDX_8197F(x) ((x) & (~BITS_BEQ_HW_IDX_8197F))
+#define BIT_GET_BEQ_HW_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_BEQ_HW_IDX_8197F) & BIT_MASK_BEQ_HW_IDX_8197F)
+#define BIT_SET_BEQ_HW_IDX_8197F(x, v) \
+ (BIT_CLEAR_BEQ_HW_IDX_8197F(x) | BIT_BEQ_HW_IDX_8197F(v))
+
+#define BIT_SHIFT_BEQ_HOST_IDX_8197F 0
+#define BIT_MASK_BEQ_HOST_IDX_8197F 0xfff
+#define BIT_BEQ_HOST_IDX_8197F(x) \
+ (((x) & BIT_MASK_BEQ_HOST_IDX_8197F) << BIT_SHIFT_BEQ_HOST_IDX_8197F)
+#define BITS_BEQ_HOST_IDX_8197F \
+ (BIT_MASK_BEQ_HOST_IDX_8197F << BIT_SHIFT_BEQ_HOST_IDX_8197F)
+#define BIT_CLEAR_BEQ_HOST_IDX_8197F(x) ((x) & (~BITS_BEQ_HOST_IDX_8197F))
+#define BIT_GET_BEQ_HOST_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_BEQ_HOST_IDX_8197F) & BIT_MASK_BEQ_HOST_IDX_8197F)
+#define BIT_SET_BEQ_HOST_IDX_8197F(x, v) \
+ (BIT_CLEAR_BEQ_HOST_IDX_8197F(x) | BIT_BEQ_HOST_IDX_8197F(v))
+
+/* 2 REG_BKQ_TXBD_IDX_8197F */
+
+#define BIT_SHIFT_BKQ_HW_IDX_8197F 16
+#define BIT_MASK_BKQ_HW_IDX_8197F 0xfff
+#define BIT_BKQ_HW_IDX_8197F(x) \
+ (((x) & BIT_MASK_BKQ_HW_IDX_8197F) << BIT_SHIFT_BKQ_HW_IDX_8197F)
+#define BITS_BKQ_HW_IDX_8197F \
+ (BIT_MASK_BKQ_HW_IDX_8197F << BIT_SHIFT_BKQ_HW_IDX_8197F)
+#define BIT_CLEAR_BKQ_HW_IDX_8197F(x) ((x) & (~BITS_BKQ_HW_IDX_8197F))
+#define BIT_GET_BKQ_HW_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_BKQ_HW_IDX_8197F) & BIT_MASK_BKQ_HW_IDX_8197F)
+#define BIT_SET_BKQ_HW_IDX_8197F(x, v) \
+ (BIT_CLEAR_BKQ_HW_IDX_8197F(x) | BIT_BKQ_HW_IDX_8197F(v))
+
+#define BIT_SHIFT_BKQ_HOST_IDX_8197F 0
+#define BIT_MASK_BKQ_HOST_IDX_8197F 0xfff
+#define BIT_BKQ_HOST_IDX_8197F(x) \
+ (((x) & BIT_MASK_BKQ_HOST_IDX_8197F) << BIT_SHIFT_BKQ_HOST_IDX_8197F)
+#define BITS_BKQ_HOST_IDX_8197F \
+ (BIT_MASK_BKQ_HOST_IDX_8197F << BIT_SHIFT_BKQ_HOST_IDX_8197F)
+#define BIT_CLEAR_BKQ_HOST_IDX_8197F(x) ((x) & (~BITS_BKQ_HOST_IDX_8197F))
+#define BIT_GET_BKQ_HOST_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_BKQ_HOST_IDX_8197F) & BIT_MASK_BKQ_HOST_IDX_8197F)
+#define BIT_SET_BKQ_HOST_IDX_8197F(x, v) \
+ (BIT_CLEAR_BKQ_HOST_IDX_8197F(x) | BIT_BKQ_HOST_IDX_8197F(v))
+
+/* 2 REG_MGQ_TXBD_IDX_8197F */
+
+#define BIT_SHIFT_MGQ_HW_IDX_8197F 16
+#define BIT_MASK_MGQ_HW_IDX_8197F 0xfff
+#define BIT_MGQ_HW_IDX_8197F(x) \
+ (((x) & BIT_MASK_MGQ_HW_IDX_8197F) << BIT_SHIFT_MGQ_HW_IDX_8197F)
+#define BITS_MGQ_HW_IDX_8197F \
+ (BIT_MASK_MGQ_HW_IDX_8197F << BIT_SHIFT_MGQ_HW_IDX_8197F)
+#define BIT_CLEAR_MGQ_HW_IDX_8197F(x) ((x) & (~BITS_MGQ_HW_IDX_8197F))
+#define BIT_GET_MGQ_HW_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_MGQ_HW_IDX_8197F) & BIT_MASK_MGQ_HW_IDX_8197F)
+#define BIT_SET_MGQ_HW_IDX_8197F(x, v) \
+ (BIT_CLEAR_MGQ_HW_IDX_8197F(x) | BIT_MGQ_HW_IDX_8197F(v))
+
+#define BIT_SHIFT_MGQ_HOST_IDX_8197F 0
+#define BIT_MASK_MGQ_HOST_IDX_8197F 0xfff
+#define BIT_MGQ_HOST_IDX_8197F(x) \
+ (((x) & BIT_MASK_MGQ_HOST_IDX_8197F) << BIT_SHIFT_MGQ_HOST_IDX_8197F)
+#define BITS_MGQ_HOST_IDX_8197F \
+ (BIT_MASK_MGQ_HOST_IDX_8197F << BIT_SHIFT_MGQ_HOST_IDX_8197F)
+#define BIT_CLEAR_MGQ_HOST_IDX_8197F(x) ((x) & (~BITS_MGQ_HOST_IDX_8197F))
+#define BIT_GET_MGQ_HOST_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_MGQ_HOST_IDX_8197F) & BIT_MASK_MGQ_HOST_IDX_8197F)
+#define BIT_SET_MGQ_HOST_IDX_8197F(x, v) \
+ (BIT_CLEAR_MGQ_HOST_IDX_8197F(x) | BIT_MGQ_HOST_IDX_8197F(v))
+
+/* 2 REG_RXQ_RXBD_IDX_8197F */
+
+#define BIT_SHIFT_RXQ_HW_IDX_8197F 16
+#define BIT_MASK_RXQ_HW_IDX_8197F 0xfff
+#define BIT_RXQ_HW_IDX_8197F(x) \
+ (((x) & BIT_MASK_RXQ_HW_IDX_8197F) << BIT_SHIFT_RXQ_HW_IDX_8197F)
+#define BITS_RXQ_HW_IDX_8197F \
+ (BIT_MASK_RXQ_HW_IDX_8197F << BIT_SHIFT_RXQ_HW_IDX_8197F)
+#define BIT_CLEAR_RXQ_HW_IDX_8197F(x) ((x) & (~BITS_RXQ_HW_IDX_8197F))
+#define BIT_GET_RXQ_HW_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_RXQ_HW_IDX_8197F) & BIT_MASK_RXQ_HW_IDX_8197F)
+#define BIT_SET_RXQ_HW_IDX_8197F(x, v) \
+ (BIT_CLEAR_RXQ_HW_IDX_8197F(x) | BIT_RXQ_HW_IDX_8197F(v))
+
+#define BIT_SHIFT_RXQ_HOST_IDX_8197F 0
+#define BIT_MASK_RXQ_HOST_IDX_8197F 0xfff
+#define BIT_RXQ_HOST_IDX_8197F(x) \
+ (((x) & BIT_MASK_RXQ_HOST_IDX_8197F) << BIT_SHIFT_RXQ_HOST_IDX_8197F)
+#define BITS_RXQ_HOST_IDX_8197F \
+ (BIT_MASK_RXQ_HOST_IDX_8197F << BIT_SHIFT_RXQ_HOST_IDX_8197F)
+#define BIT_CLEAR_RXQ_HOST_IDX_8197F(x) ((x) & (~BITS_RXQ_HOST_IDX_8197F))
+#define BIT_GET_RXQ_HOST_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_RXQ_HOST_IDX_8197F) & BIT_MASK_RXQ_HOST_IDX_8197F)
+#define BIT_SET_RXQ_HOST_IDX_8197F(x, v) \
+ (BIT_CLEAR_RXQ_HOST_IDX_8197F(x) | BIT_RXQ_HOST_IDX_8197F(v))
+
+/* 2 REG_HI0Q_TXBD_IDX_8197F */
+
+#define BIT_SHIFT_HI0Q_HW_IDX_8197F 16
+#define BIT_MASK_HI0Q_HW_IDX_8197F 0xfff
+#define BIT_HI0Q_HW_IDX_8197F(x) \
+ (((x) & BIT_MASK_HI0Q_HW_IDX_8197F) << BIT_SHIFT_HI0Q_HW_IDX_8197F)
+#define BITS_HI0Q_HW_IDX_8197F \
+ (BIT_MASK_HI0Q_HW_IDX_8197F << BIT_SHIFT_HI0Q_HW_IDX_8197F)
+#define BIT_CLEAR_HI0Q_HW_IDX_8197F(x) ((x) & (~BITS_HI0Q_HW_IDX_8197F))
+#define BIT_GET_HI0Q_HW_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_HI0Q_HW_IDX_8197F) & BIT_MASK_HI0Q_HW_IDX_8197F)
+#define BIT_SET_HI0Q_HW_IDX_8197F(x, v) \
+ (BIT_CLEAR_HI0Q_HW_IDX_8197F(x) | BIT_HI0Q_HW_IDX_8197F(v))
+
+#define BIT_SHIFT_HI0Q_HOST_IDX_8197F 0
+#define BIT_MASK_HI0Q_HOST_IDX_8197F 0xfff
+#define BIT_HI0Q_HOST_IDX_8197F(x) \
+ (((x) & BIT_MASK_HI0Q_HOST_IDX_8197F) << BIT_SHIFT_HI0Q_HOST_IDX_8197F)
+#define BITS_HI0Q_HOST_IDX_8197F \
+ (BIT_MASK_HI0Q_HOST_IDX_8197F << BIT_SHIFT_HI0Q_HOST_IDX_8197F)
+#define BIT_CLEAR_HI0Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI0Q_HOST_IDX_8197F))
+#define BIT_GET_HI0Q_HOST_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_HI0Q_HOST_IDX_8197F) & BIT_MASK_HI0Q_HOST_IDX_8197F)
+#define BIT_SET_HI0Q_HOST_IDX_8197F(x, v) \
+ (BIT_CLEAR_HI0Q_HOST_IDX_8197F(x) | BIT_HI0Q_HOST_IDX_8197F(v))
+
+/* 2 REG_HI1Q_TXBD_IDX_8197F */
+
+#define BIT_SHIFT_HI1Q_HW_IDX_8197F 16
+#define BIT_MASK_HI1Q_HW_IDX_8197F 0xfff
+#define BIT_HI1Q_HW_IDX_8197F(x) \
+ (((x) & BIT_MASK_HI1Q_HW_IDX_8197F) << BIT_SHIFT_HI1Q_HW_IDX_8197F)
+#define BITS_HI1Q_HW_IDX_8197F \
+ (BIT_MASK_HI1Q_HW_IDX_8197F << BIT_SHIFT_HI1Q_HW_IDX_8197F)
+#define BIT_CLEAR_HI1Q_HW_IDX_8197F(x) ((x) & (~BITS_HI1Q_HW_IDX_8197F))
+#define BIT_GET_HI1Q_HW_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_HI1Q_HW_IDX_8197F) & BIT_MASK_HI1Q_HW_IDX_8197F)
+#define BIT_SET_HI1Q_HW_IDX_8197F(x, v) \
+ (BIT_CLEAR_HI1Q_HW_IDX_8197F(x) | BIT_HI1Q_HW_IDX_8197F(v))
+
+#define BIT_SHIFT_HI1Q_HOST_IDX_8197F 0
+#define BIT_MASK_HI1Q_HOST_IDX_8197F 0xfff
+#define BIT_HI1Q_HOST_IDX_8197F(x) \
+ (((x) & BIT_MASK_HI1Q_HOST_IDX_8197F) << BIT_SHIFT_HI1Q_HOST_IDX_8197F)
+#define BITS_HI1Q_HOST_IDX_8197F \
+ (BIT_MASK_HI1Q_HOST_IDX_8197F << BIT_SHIFT_HI1Q_HOST_IDX_8197F)
+#define BIT_CLEAR_HI1Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI1Q_HOST_IDX_8197F))
+#define BIT_GET_HI1Q_HOST_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_HI1Q_HOST_IDX_8197F) & BIT_MASK_HI1Q_HOST_IDX_8197F)
+#define BIT_SET_HI1Q_HOST_IDX_8197F(x, v) \
+ (BIT_CLEAR_HI1Q_HOST_IDX_8197F(x) | BIT_HI1Q_HOST_IDX_8197F(v))
+
+/* 2 REG_HI2Q_TXBD_IDX_8197F */
+
+#define BIT_SHIFT_HI2Q_HW_IDX_8197F 16
+#define BIT_MASK_HI2Q_HW_IDX_8197F 0xfff
+#define BIT_HI2Q_HW_IDX_8197F(x) \
+ (((x) & BIT_MASK_HI2Q_HW_IDX_8197F) << BIT_SHIFT_HI2Q_HW_IDX_8197F)
+#define BITS_HI2Q_HW_IDX_8197F \
+ (BIT_MASK_HI2Q_HW_IDX_8197F << BIT_SHIFT_HI2Q_HW_IDX_8197F)
+#define BIT_CLEAR_HI2Q_HW_IDX_8197F(x) ((x) & (~BITS_HI2Q_HW_IDX_8197F))
+#define BIT_GET_HI2Q_HW_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_HI2Q_HW_IDX_8197F) & BIT_MASK_HI2Q_HW_IDX_8197F)
+#define BIT_SET_HI2Q_HW_IDX_8197F(x, v) \
+ (BIT_CLEAR_HI2Q_HW_IDX_8197F(x) | BIT_HI2Q_HW_IDX_8197F(v))
+
+#define BIT_SHIFT_HI2Q_HOST_IDX_8197F 0
+#define BIT_MASK_HI2Q_HOST_IDX_8197F 0xfff
+#define BIT_HI2Q_HOST_IDX_8197F(x) \
+ (((x) & BIT_MASK_HI2Q_HOST_IDX_8197F) << BIT_SHIFT_HI2Q_HOST_IDX_8197F)
+#define BITS_HI2Q_HOST_IDX_8197F \
+ (BIT_MASK_HI2Q_HOST_IDX_8197F << BIT_SHIFT_HI2Q_HOST_IDX_8197F)
+#define BIT_CLEAR_HI2Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI2Q_HOST_IDX_8197F))
+#define BIT_GET_HI2Q_HOST_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_HI2Q_HOST_IDX_8197F) & BIT_MASK_HI2Q_HOST_IDX_8197F)
+#define BIT_SET_HI2Q_HOST_IDX_8197F(x, v) \
+ (BIT_CLEAR_HI2Q_HOST_IDX_8197F(x) | BIT_HI2Q_HOST_IDX_8197F(v))
+
+/* 2 REG_HI3Q_TXBD_IDX_8197F */
+
+#define BIT_SHIFT_HI3Q_HW_IDX_8197F 16
+#define BIT_MASK_HI3Q_HW_IDX_8197F 0xfff
+#define BIT_HI3Q_HW_IDX_8197F(x) \
+ (((x) & BIT_MASK_HI3Q_HW_IDX_8197F) << BIT_SHIFT_HI3Q_HW_IDX_8197F)
+#define BITS_HI3Q_HW_IDX_8197F \
+ (BIT_MASK_HI3Q_HW_IDX_8197F << BIT_SHIFT_HI3Q_HW_IDX_8197F)
+#define BIT_CLEAR_HI3Q_HW_IDX_8197F(x) ((x) & (~BITS_HI3Q_HW_IDX_8197F))
+#define BIT_GET_HI3Q_HW_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_HI3Q_HW_IDX_8197F) & BIT_MASK_HI3Q_HW_IDX_8197F)
+#define BIT_SET_HI3Q_HW_IDX_8197F(x, v) \
+ (BIT_CLEAR_HI3Q_HW_IDX_8197F(x) | BIT_HI3Q_HW_IDX_8197F(v))
+
+#define BIT_SHIFT_HI3Q_HOST_IDX_8197F 0
+#define BIT_MASK_HI3Q_HOST_IDX_8197F 0xfff
+#define BIT_HI3Q_HOST_IDX_8197F(x) \
+ (((x) & BIT_MASK_HI3Q_HOST_IDX_8197F) << BIT_SHIFT_HI3Q_HOST_IDX_8197F)
+#define BITS_HI3Q_HOST_IDX_8197F \
+ (BIT_MASK_HI3Q_HOST_IDX_8197F << BIT_SHIFT_HI3Q_HOST_IDX_8197F)
+#define BIT_CLEAR_HI3Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI3Q_HOST_IDX_8197F))
+#define BIT_GET_HI3Q_HOST_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_HI3Q_HOST_IDX_8197F) & BIT_MASK_HI3Q_HOST_IDX_8197F)
+#define BIT_SET_HI3Q_HOST_IDX_8197F(x, v) \
+ (BIT_CLEAR_HI3Q_HOST_IDX_8197F(x) | BIT_HI3Q_HOST_IDX_8197F(v))
+
+/* 2 REG_HI4Q_TXBD_IDX_8197F */
+
+#define BIT_SHIFT_HI4Q_HW_IDX_8197F 16
+#define BIT_MASK_HI4Q_HW_IDX_8197F 0xfff
+#define BIT_HI4Q_HW_IDX_8197F(x) \
+ (((x) & BIT_MASK_HI4Q_HW_IDX_8197F) << BIT_SHIFT_HI4Q_HW_IDX_8197F)
+#define BITS_HI4Q_HW_IDX_8197F \
+ (BIT_MASK_HI4Q_HW_IDX_8197F << BIT_SHIFT_HI4Q_HW_IDX_8197F)
+#define BIT_CLEAR_HI4Q_HW_IDX_8197F(x) ((x) & (~BITS_HI4Q_HW_IDX_8197F))
+#define BIT_GET_HI4Q_HW_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_HI4Q_HW_IDX_8197F) & BIT_MASK_HI4Q_HW_IDX_8197F)
+#define BIT_SET_HI4Q_HW_IDX_8197F(x, v) \
+ (BIT_CLEAR_HI4Q_HW_IDX_8197F(x) | BIT_HI4Q_HW_IDX_8197F(v))
+
+#define BIT_SHIFT_HI4Q_HOST_IDX_8197F 0
+#define BIT_MASK_HI4Q_HOST_IDX_8197F 0xfff
+#define BIT_HI4Q_HOST_IDX_8197F(x) \
+ (((x) & BIT_MASK_HI4Q_HOST_IDX_8197F) << BIT_SHIFT_HI4Q_HOST_IDX_8197F)
+#define BITS_HI4Q_HOST_IDX_8197F \
+ (BIT_MASK_HI4Q_HOST_IDX_8197F << BIT_SHIFT_HI4Q_HOST_IDX_8197F)
+#define BIT_CLEAR_HI4Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI4Q_HOST_IDX_8197F))
+#define BIT_GET_HI4Q_HOST_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_HI4Q_HOST_IDX_8197F) & BIT_MASK_HI4Q_HOST_IDX_8197F)
+#define BIT_SET_HI4Q_HOST_IDX_8197F(x, v) \
+ (BIT_CLEAR_HI4Q_HOST_IDX_8197F(x) | BIT_HI4Q_HOST_IDX_8197F(v))
+
+/* 2 REG_HI5Q_TXBD_IDX_8197F */
+
+#define BIT_SHIFT_HI5Q_HW_IDX_8197F 16
+#define BIT_MASK_HI5Q_HW_IDX_8197F 0xfff
+#define BIT_HI5Q_HW_IDX_8197F(x) \
+ (((x) & BIT_MASK_HI5Q_HW_IDX_8197F) << BIT_SHIFT_HI5Q_HW_IDX_8197F)
+#define BITS_HI5Q_HW_IDX_8197F \
+ (BIT_MASK_HI5Q_HW_IDX_8197F << BIT_SHIFT_HI5Q_HW_IDX_8197F)
+#define BIT_CLEAR_HI5Q_HW_IDX_8197F(x) ((x) & (~BITS_HI5Q_HW_IDX_8197F))
+#define BIT_GET_HI5Q_HW_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_HI5Q_HW_IDX_8197F) & BIT_MASK_HI5Q_HW_IDX_8197F)
+#define BIT_SET_HI5Q_HW_IDX_8197F(x, v) \
+ (BIT_CLEAR_HI5Q_HW_IDX_8197F(x) | BIT_HI5Q_HW_IDX_8197F(v))
+
+#define BIT_SHIFT_HI5Q_HOST_IDX_8197F 0
+#define BIT_MASK_HI5Q_HOST_IDX_8197F 0xfff
+#define BIT_HI5Q_HOST_IDX_8197F(x) \
+ (((x) & BIT_MASK_HI5Q_HOST_IDX_8197F) << BIT_SHIFT_HI5Q_HOST_IDX_8197F)
+#define BITS_HI5Q_HOST_IDX_8197F \
+ (BIT_MASK_HI5Q_HOST_IDX_8197F << BIT_SHIFT_HI5Q_HOST_IDX_8197F)
+#define BIT_CLEAR_HI5Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI5Q_HOST_IDX_8197F))
+#define BIT_GET_HI5Q_HOST_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_HI5Q_HOST_IDX_8197F) & BIT_MASK_HI5Q_HOST_IDX_8197F)
+#define BIT_SET_HI5Q_HOST_IDX_8197F(x, v) \
+ (BIT_CLEAR_HI5Q_HOST_IDX_8197F(x) | BIT_HI5Q_HOST_IDX_8197F(v))
+
+/* 2 REG_HI6Q_TXBD_IDX_8197F */
+
+#define BIT_SHIFT_HI6Q_HW_IDX_8197F 16
+#define BIT_MASK_HI6Q_HW_IDX_8197F 0xfff
+#define BIT_HI6Q_HW_IDX_8197F(x) \
+ (((x) & BIT_MASK_HI6Q_HW_IDX_8197F) << BIT_SHIFT_HI6Q_HW_IDX_8197F)
+#define BITS_HI6Q_HW_IDX_8197F \
+ (BIT_MASK_HI6Q_HW_IDX_8197F << BIT_SHIFT_HI6Q_HW_IDX_8197F)
+#define BIT_CLEAR_HI6Q_HW_IDX_8197F(x) ((x) & (~BITS_HI6Q_HW_IDX_8197F))
+#define BIT_GET_HI6Q_HW_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_HI6Q_HW_IDX_8197F) & BIT_MASK_HI6Q_HW_IDX_8197F)
+#define BIT_SET_HI6Q_HW_IDX_8197F(x, v) \
+ (BIT_CLEAR_HI6Q_HW_IDX_8197F(x) | BIT_HI6Q_HW_IDX_8197F(v))
+
+#define BIT_SHIFT_HI6Q_HOST_IDX_8197F 0
+#define BIT_MASK_HI6Q_HOST_IDX_8197F 0xfff
+#define BIT_HI6Q_HOST_IDX_8197F(x) \
+ (((x) & BIT_MASK_HI6Q_HOST_IDX_8197F) << BIT_SHIFT_HI6Q_HOST_IDX_8197F)
+#define BITS_HI6Q_HOST_IDX_8197F \
+ (BIT_MASK_HI6Q_HOST_IDX_8197F << BIT_SHIFT_HI6Q_HOST_IDX_8197F)
+#define BIT_CLEAR_HI6Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI6Q_HOST_IDX_8197F))
+#define BIT_GET_HI6Q_HOST_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_HI6Q_HOST_IDX_8197F) & BIT_MASK_HI6Q_HOST_IDX_8197F)
+#define BIT_SET_HI6Q_HOST_IDX_8197F(x, v) \
+ (BIT_CLEAR_HI6Q_HOST_IDX_8197F(x) | BIT_HI6Q_HOST_IDX_8197F(v))
+
+/* 2 REG_HI7Q_TXBD_IDX_8197F */
+
+#define BIT_SHIFT_HI7Q_HW_IDX_8197F 16
+#define BIT_MASK_HI7Q_HW_IDX_8197F 0xfff
+#define BIT_HI7Q_HW_IDX_8197F(x) \
+ (((x) & BIT_MASK_HI7Q_HW_IDX_8197F) << BIT_SHIFT_HI7Q_HW_IDX_8197F)
+#define BITS_HI7Q_HW_IDX_8197F \
+ (BIT_MASK_HI7Q_HW_IDX_8197F << BIT_SHIFT_HI7Q_HW_IDX_8197F)
+#define BIT_CLEAR_HI7Q_HW_IDX_8197F(x) ((x) & (~BITS_HI7Q_HW_IDX_8197F))
+#define BIT_GET_HI7Q_HW_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_HI7Q_HW_IDX_8197F) & BIT_MASK_HI7Q_HW_IDX_8197F)
+#define BIT_SET_HI7Q_HW_IDX_8197F(x, v) \
+ (BIT_CLEAR_HI7Q_HW_IDX_8197F(x) | BIT_HI7Q_HW_IDX_8197F(v))
+
+#define BIT_SHIFT_HI7Q_HOST_IDX_8197F 0
+#define BIT_MASK_HI7Q_HOST_IDX_8197F 0xfff
+#define BIT_HI7Q_HOST_IDX_8197F(x) \
+ (((x) & BIT_MASK_HI7Q_HOST_IDX_8197F) << BIT_SHIFT_HI7Q_HOST_IDX_8197F)
+#define BITS_HI7Q_HOST_IDX_8197F \
+ (BIT_MASK_HI7Q_HOST_IDX_8197F << BIT_SHIFT_HI7Q_HOST_IDX_8197F)
+#define BIT_CLEAR_HI7Q_HOST_IDX_8197F(x) ((x) & (~BITS_HI7Q_HOST_IDX_8197F))
+#define BIT_GET_HI7Q_HOST_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_HI7Q_HOST_IDX_8197F) & BIT_MASK_HI7Q_HOST_IDX_8197F)
+#define BIT_SET_HI7Q_HOST_IDX_8197F(x, v) \
+ (BIT_CLEAR_HI7Q_HOST_IDX_8197F(x) | BIT_HI7Q_HOST_IDX_8197F(v))
+
+/* 2 REG_DBG_SEL_V1_8197F */
+
+#define BIT_SHIFT_DBG_SEL_8197F 0
+#define BIT_MASK_DBG_SEL_8197F 0xff
+#define BIT_DBG_SEL_8197F(x) \
+ (((x) & BIT_MASK_DBG_SEL_8197F) << BIT_SHIFT_DBG_SEL_8197F)
+#define BITS_DBG_SEL_8197F (BIT_MASK_DBG_SEL_8197F << BIT_SHIFT_DBG_SEL_8197F)
+#define BIT_CLEAR_DBG_SEL_8197F(x) ((x) & (~BITS_DBG_SEL_8197F))
+#define BIT_GET_DBG_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_DBG_SEL_8197F) & BIT_MASK_DBG_SEL_8197F)
+#define BIT_SET_DBG_SEL_8197F(x, v) \
+ (BIT_CLEAR_DBG_SEL_8197F(x) | BIT_DBG_SEL_8197F(v))
+
+/* 2 REG_HCI_HRPWM1_V1_8197F */
+
+#define BIT_SHIFT_HCI_HRPWM_8197F 0
+#define BIT_MASK_HCI_HRPWM_8197F 0xff
+#define BIT_HCI_HRPWM_8197F(x) \
+ (((x) & BIT_MASK_HCI_HRPWM_8197F) << BIT_SHIFT_HCI_HRPWM_8197F)
+#define BITS_HCI_HRPWM_8197F \
+ (BIT_MASK_HCI_HRPWM_8197F << BIT_SHIFT_HCI_HRPWM_8197F)
+#define BIT_CLEAR_HCI_HRPWM_8197F(x) ((x) & (~BITS_HCI_HRPWM_8197F))
+#define BIT_GET_HCI_HRPWM_8197F(x) \
+ (((x) >> BIT_SHIFT_HCI_HRPWM_8197F) & BIT_MASK_HCI_HRPWM_8197F)
+#define BIT_SET_HCI_HRPWM_8197F(x, v) \
+ (BIT_CLEAR_HCI_HRPWM_8197F(x) | BIT_HCI_HRPWM_8197F(v))
+
+/* 2 REG_HCI_HCPWM1_V1_8197F */
+
+#define BIT_SHIFT_HCI_HCPWM_8197F 0
+#define BIT_MASK_HCI_HCPWM_8197F 0xff
+#define BIT_HCI_HCPWM_8197F(x) \
+ (((x) & BIT_MASK_HCI_HCPWM_8197F) << BIT_SHIFT_HCI_HCPWM_8197F)
+#define BITS_HCI_HCPWM_8197F \
+ (BIT_MASK_HCI_HCPWM_8197F << BIT_SHIFT_HCI_HCPWM_8197F)
+#define BIT_CLEAR_HCI_HCPWM_8197F(x) ((x) & (~BITS_HCI_HCPWM_8197F))
+#define BIT_GET_HCI_HCPWM_8197F(x) \
+ (((x) >> BIT_SHIFT_HCI_HCPWM_8197F) & BIT_MASK_HCI_HCPWM_8197F)
+#define BIT_SET_HCI_HCPWM_8197F(x, v) \
+ (BIT_CLEAR_HCI_HCPWM_8197F(x) | BIT_HCI_HCPWM_8197F(v))
+
+/* 2 REG_HCI_CTRL2_8197F */
+#define BIT_DIS_TXDMA_PRE_8197F BIT(7)
+#define BIT_DIS_RXDMA_PRE_8197F BIT(6)
+
+#define BIT_SHIFT_HPS_CLKR_HCI_8197F 4
+#define BIT_MASK_HPS_CLKR_HCI_8197F 0x3
+#define BIT_HPS_CLKR_HCI_8197F(x) \
+ (((x) & BIT_MASK_HPS_CLKR_HCI_8197F) << BIT_SHIFT_HPS_CLKR_HCI_8197F)
+#define BITS_HPS_CLKR_HCI_8197F \
+ (BIT_MASK_HPS_CLKR_HCI_8197F << BIT_SHIFT_HPS_CLKR_HCI_8197F)
+#define BIT_CLEAR_HPS_CLKR_HCI_8197F(x) ((x) & (~BITS_HPS_CLKR_HCI_8197F))
+#define BIT_GET_HPS_CLKR_HCI_8197F(x) \
+ (((x) >> BIT_SHIFT_HPS_CLKR_HCI_8197F) & BIT_MASK_HPS_CLKR_HCI_8197F)
+#define BIT_SET_HPS_CLKR_HCI_8197F(x, v) \
+ (BIT_CLEAR_HPS_CLKR_HCI_8197F(x) | BIT_HPS_CLKR_HCI_8197F(v))
+
+#define BIT_HCI_INT_8197F BIT(3)
+#define BIT_TXFLAG_EXIT_L1_EN_8197F BIT(2)
+#define BIT_EN_RXDMA_ALIGN_V1_8197F BIT(1)
+#define BIT_EN_TXDMA_ALIGN_V1_8197F BIT(0)
+
+/* 2 REG_HCI_HRPWM2_V1_8197F */
+
+#define BIT_SHIFT_HCI_HRPWM2_8197F 0
+#define BIT_MASK_HCI_HRPWM2_8197F 0xffff
+#define BIT_HCI_HRPWM2_8197F(x) \
+ (((x) & BIT_MASK_HCI_HRPWM2_8197F) << BIT_SHIFT_HCI_HRPWM2_8197F)
+#define BITS_HCI_HRPWM2_8197F \
+ (BIT_MASK_HCI_HRPWM2_8197F << BIT_SHIFT_HCI_HRPWM2_8197F)
+#define BIT_CLEAR_HCI_HRPWM2_8197F(x) ((x) & (~BITS_HCI_HRPWM2_8197F))
+#define BIT_GET_HCI_HRPWM2_8197F(x) \
+ (((x) >> BIT_SHIFT_HCI_HRPWM2_8197F) & BIT_MASK_HCI_HRPWM2_8197F)
+#define BIT_SET_HCI_HRPWM2_8197F(x, v) \
+ (BIT_CLEAR_HCI_HRPWM2_8197F(x) | BIT_HCI_HRPWM2_8197F(v))
+
+/* 2 REG_HCI_HCPWM2_V1_8197F */
+
+#define BIT_SHIFT_HCI_HCPWM2_8197F 0
+#define BIT_MASK_HCI_HCPWM2_8197F 0xffff
+#define BIT_HCI_HCPWM2_8197F(x) \
+ (((x) & BIT_MASK_HCI_HCPWM2_8197F) << BIT_SHIFT_HCI_HCPWM2_8197F)
+#define BITS_HCI_HCPWM2_8197F \
+ (BIT_MASK_HCI_HCPWM2_8197F << BIT_SHIFT_HCI_HCPWM2_8197F)
+#define BIT_CLEAR_HCI_HCPWM2_8197F(x) ((x) & (~BITS_HCI_HCPWM2_8197F))
+#define BIT_GET_HCI_HCPWM2_8197F(x) \
+ (((x) >> BIT_SHIFT_HCI_HCPWM2_8197F) & BIT_MASK_HCI_HCPWM2_8197F)
+#define BIT_SET_HCI_HCPWM2_8197F(x, v) \
+ (BIT_CLEAR_HCI_HCPWM2_8197F(x) | BIT_HCI_HCPWM2_8197F(v))
+
+/* 2 REG_HCI_H2C_MSG_V1_8197F */
+
+#define BIT_SHIFT_DRV2FW_INFO_8197F 0
+#define BIT_MASK_DRV2FW_INFO_8197F 0xffffffffL
+#define BIT_DRV2FW_INFO_8197F(x) \
+ (((x) & BIT_MASK_DRV2FW_INFO_8197F) << BIT_SHIFT_DRV2FW_INFO_8197F)
+#define BITS_DRV2FW_INFO_8197F \
+ (BIT_MASK_DRV2FW_INFO_8197F << BIT_SHIFT_DRV2FW_INFO_8197F)
+#define BIT_CLEAR_DRV2FW_INFO_8197F(x) ((x) & (~BITS_DRV2FW_INFO_8197F))
+#define BIT_GET_DRV2FW_INFO_8197F(x) \
+ (((x) >> BIT_SHIFT_DRV2FW_INFO_8197F) & BIT_MASK_DRV2FW_INFO_8197F)
+#define BIT_SET_DRV2FW_INFO_8197F(x, v) \
+ (BIT_CLEAR_DRV2FW_INFO_8197F(x) | BIT_DRV2FW_INFO_8197F(v))
+
+/* 2 REG_HCI_C2H_MSG_V1_8197F */
+
+#define BIT_SHIFT_HCI_C2H_MSG_8197F 0
+#define BIT_MASK_HCI_C2H_MSG_8197F 0xffffffffL
+#define BIT_HCI_C2H_MSG_8197F(x) \
+ (((x) & BIT_MASK_HCI_C2H_MSG_8197F) << BIT_SHIFT_HCI_C2H_MSG_8197F)
+#define BITS_HCI_C2H_MSG_8197F \
+ (BIT_MASK_HCI_C2H_MSG_8197F << BIT_SHIFT_HCI_C2H_MSG_8197F)
+#define BIT_CLEAR_HCI_C2H_MSG_8197F(x) ((x) & (~BITS_HCI_C2H_MSG_8197F))
+#define BIT_GET_HCI_C2H_MSG_8197F(x) \
+ (((x) >> BIT_SHIFT_HCI_C2H_MSG_8197F) & BIT_MASK_HCI_C2H_MSG_8197F)
+#define BIT_SET_HCI_C2H_MSG_8197F(x, v) \
+ (BIT_CLEAR_HCI_C2H_MSG_8197F(x) | BIT_HCI_C2H_MSG_8197F(v))
+
+/* 2 REG_DBI_WDATA_V1_8197F */
+
+#define BIT_SHIFT_DBI_WDATA_8197F 0
+#define BIT_MASK_DBI_WDATA_8197F 0xffffffffL
+#define BIT_DBI_WDATA_8197F(x) \
+ (((x) & BIT_MASK_DBI_WDATA_8197F) << BIT_SHIFT_DBI_WDATA_8197F)
+#define BITS_DBI_WDATA_8197F \
+ (BIT_MASK_DBI_WDATA_8197F << BIT_SHIFT_DBI_WDATA_8197F)
+#define BIT_CLEAR_DBI_WDATA_8197F(x) ((x) & (~BITS_DBI_WDATA_8197F))
+#define BIT_GET_DBI_WDATA_8197F(x) \
+ (((x) >> BIT_SHIFT_DBI_WDATA_8197F) & BIT_MASK_DBI_WDATA_8197F)
+#define BIT_SET_DBI_WDATA_8197F(x, v) \
+ (BIT_CLEAR_DBI_WDATA_8197F(x) | BIT_DBI_WDATA_8197F(v))
+
+/* 2 REG_DBI_RDATA_V1_8197F */
+
+#define BIT_SHIFT_DBI_RDATA_8197F 0
+#define BIT_MASK_DBI_RDATA_8197F 0xffffffffL
+#define BIT_DBI_RDATA_8197F(x) \
+ (((x) & BIT_MASK_DBI_RDATA_8197F) << BIT_SHIFT_DBI_RDATA_8197F)
+#define BITS_DBI_RDATA_8197F \
+ (BIT_MASK_DBI_RDATA_8197F << BIT_SHIFT_DBI_RDATA_8197F)
+#define BIT_CLEAR_DBI_RDATA_8197F(x) ((x) & (~BITS_DBI_RDATA_8197F))
+#define BIT_GET_DBI_RDATA_8197F(x) \
+ (((x) >> BIT_SHIFT_DBI_RDATA_8197F) & BIT_MASK_DBI_RDATA_8197F)
+#define BIT_SET_DBI_RDATA_8197F(x, v) \
+ (BIT_CLEAR_DBI_RDATA_8197F(x) | BIT_DBI_RDATA_8197F(v))
+
+/* 2 REG_STUCK_FLAG_V1_8197F */
+#define BIT_EN_STUCK_DBG_8197F BIT(26)
+#define BIT_RX_STUCK_8197F BIT(25)
+#define BIT_TX_STUCK_8197F BIT(24)
+#define BIT_DBI_RFLAG_8197F BIT(17)
+#define BIT_DBI_WFLAG_8197F BIT(16)
+
+#define BIT_SHIFT_DBI_WREN_8197F 12
+#define BIT_MASK_DBI_WREN_8197F 0xf
+#define BIT_DBI_WREN_8197F(x) \
+ (((x) & BIT_MASK_DBI_WREN_8197F) << BIT_SHIFT_DBI_WREN_8197F)
+#define BITS_DBI_WREN_8197F \
+ (BIT_MASK_DBI_WREN_8197F << BIT_SHIFT_DBI_WREN_8197F)
+#define BIT_CLEAR_DBI_WREN_8197F(x) ((x) & (~BITS_DBI_WREN_8197F))
+#define BIT_GET_DBI_WREN_8197F(x) \
+ (((x) >> BIT_SHIFT_DBI_WREN_8197F) & BIT_MASK_DBI_WREN_8197F)
+#define BIT_SET_DBI_WREN_8197F(x, v) \
+ (BIT_CLEAR_DBI_WREN_8197F(x) | BIT_DBI_WREN_8197F(v))
+
+#define BIT_SHIFT_DBI_ADDR_8197F 0
+#define BIT_MASK_DBI_ADDR_8197F 0xfff
+#define BIT_DBI_ADDR_8197F(x) \
+ (((x) & BIT_MASK_DBI_ADDR_8197F) << BIT_SHIFT_DBI_ADDR_8197F)
+#define BITS_DBI_ADDR_8197F \
+ (BIT_MASK_DBI_ADDR_8197F << BIT_SHIFT_DBI_ADDR_8197F)
+#define BIT_CLEAR_DBI_ADDR_8197F(x) ((x) & (~BITS_DBI_ADDR_8197F))
+#define BIT_GET_DBI_ADDR_8197F(x) \
+ (((x) >> BIT_SHIFT_DBI_ADDR_8197F) & BIT_MASK_DBI_ADDR_8197F)
+#define BIT_SET_DBI_ADDR_8197F(x, v) \
+ (BIT_CLEAR_DBI_ADDR_8197F(x) | BIT_DBI_ADDR_8197F(v))
+
+/* 2 REG_MDIO_V1_8197F */
+
+#define BIT_SHIFT_MDIO_RDATA_8197F 16
+#define BIT_MASK_MDIO_RDATA_8197F 0xffff
+#define BIT_MDIO_RDATA_8197F(x) \
+ (((x) & BIT_MASK_MDIO_RDATA_8197F) << BIT_SHIFT_MDIO_RDATA_8197F)
+#define BITS_MDIO_RDATA_8197F \
+ (BIT_MASK_MDIO_RDATA_8197F << BIT_SHIFT_MDIO_RDATA_8197F)
+#define BIT_CLEAR_MDIO_RDATA_8197F(x) ((x) & (~BITS_MDIO_RDATA_8197F))
+#define BIT_GET_MDIO_RDATA_8197F(x) \
+ (((x) >> BIT_SHIFT_MDIO_RDATA_8197F) & BIT_MASK_MDIO_RDATA_8197F)
+#define BIT_SET_MDIO_RDATA_8197F(x, v) \
+ (BIT_CLEAR_MDIO_RDATA_8197F(x) | BIT_MDIO_RDATA_8197F(v))
+
+#define BIT_SHIFT_MDIO_WDATA_8197F 0
+#define BIT_MASK_MDIO_WDATA_8197F 0xffff
+#define BIT_MDIO_WDATA_8197F(x) \
+ (((x) & BIT_MASK_MDIO_WDATA_8197F) << BIT_SHIFT_MDIO_WDATA_8197F)
+#define BITS_MDIO_WDATA_8197F \
+ (BIT_MASK_MDIO_WDATA_8197F << BIT_SHIFT_MDIO_WDATA_8197F)
+#define BIT_CLEAR_MDIO_WDATA_8197F(x) ((x) & (~BITS_MDIO_WDATA_8197F))
+#define BIT_GET_MDIO_WDATA_8197F(x) \
+ (((x) >> BIT_SHIFT_MDIO_WDATA_8197F) & BIT_MASK_MDIO_WDATA_8197F)
+#define BIT_SET_MDIO_WDATA_8197F(x, v) \
+ (BIT_CLEAR_MDIO_WDATA_8197F(x) | BIT_MDIO_WDATA_8197F(v))
+
+/* 2 REG_WDT_CFG_8197F */
+
+#define BIT_SHIFT_MDIO_PHY_ADDR_8197F 24
+#define BIT_MASK_MDIO_PHY_ADDR_8197F 0x1f
+#define BIT_MDIO_PHY_ADDR_8197F(x) \
+ (((x) & BIT_MASK_MDIO_PHY_ADDR_8197F) << BIT_SHIFT_MDIO_PHY_ADDR_8197F)
+#define BITS_MDIO_PHY_ADDR_8197F \
+ (BIT_MASK_MDIO_PHY_ADDR_8197F << BIT_SHIFT_MDIO_PHY_ADDR_8197F)
+#define BIT_CLEAR_MDIO_PHY_ADDR_8197F(x) ((x) & (~BITS_MDIO_PHY_ADDR_8197F))
+#define BIT_GET_MDIO_PHY_ADDR_8197F(x) \
+ (((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8197F) & BIT_MASK_MDIO_PHY_ADDR_8197F)
+#define BIT_SET_MDIO_PHY_ADDR_8197F(x, v) \
+ (BIT_CLEAR_MDIO_PHY_ADDR_8197F(x) | BIT_MDIO_PHY_ADDR_8197F(v))
+
+#define BIT_SHIFT_WATCH_DOG_RECORD_V1_8197F 10
+#define BIT_MASK_WATCH_DOG_RECORD_V1_8197F 0x3fff
+#define BIT_WATCH_DOG_RECORD_V1_8197F(x) \
+ (((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8197F) \
+ << BIT_SHIFT_WATCH_DOG_RECORD_V1_8197F)
+#define BITS_WATCH_DOG_RECORD_V1_8197F \
+ (BIT_MASK_WATCH_DOG_RECORD_V1_8197F \
+ << BIT_SHIFT_WATCH_DOG_RECORD_V1_8197F)
+#define BIT_CLEAR_WATCH_DOG_RECORD_V1_8197F(x) \
+ ((x) & (~BITS_WATCH_DOG_RECORD_V1_8197F))
+#define BIT_GET_WATCH_DOG_RECORD_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8197F) & \
+ BIT_MASK_WATCH_DOG_RECORD_V1_8197F)
+#define BIT_SET_WATCH_DOG_RECORD_V1_8197F(x, v) \
+ (BIT_CLEAR_WATCH_DOG_RECORD_V1_8197F(x) | \
+ BIT_WATCH_DOG_RECORD_V1_8197F(v))
+
+#define BIT_R_IO_TIMEOUT_FLAG_V1_8197F BIT(9)
+#define BIT_EN_WATCH_DOG_V1_8197F BIT(8)
+#define BIT_ECRC_EN_V1_8197F BIT(7)
+#define BIT_MDIO_RFLAG_V1_8197F BIT(6)
+#define BIT_MDIO_WFLAG_V1_8197F BIT(5)
+
+#define BIT_SHIFT_MDIO_REG_ADDR_8197F 0
+#define BIT_MASK_MDIO_REG_ADDR_8197F 0x1f
+#define BIT_MDIO_REG_ADDR_8197F(x) \
+ (((x) & BIT_MASK_MDIO_REG_ADDR_8197F) << BIT_SHIFT_MDIO_REG_ADDR_8197F)
+#define BITS_MDIO_REG_ADDR_8197F \
+ (BIT_MASK_MDIO_REG_ADDR_8197F << BIT_SHIFT_MDIO_REG_ADDR_8197F)
+#define BIT_CLEAR_MDIO_REG_ADDR_8197F(x) ((x) & (~BITS_MDIO_REG_ADDR_8197F))
+#define BIT_GET_MDIO_REG_ADDR_8197F(x) \
+ (((x) >> BIT_SHIFT_MDIO_REG_ADDR_8197F) & BIT_MASK_MDIO_REG_ADDR_8197F)
+#define BIT_SET_MDIO_REG_ADDR_8197F(x, v) \
+ (BIT_CLEAR_MDIO_REG_ADDR_8197F(x) | BIT_MDIO_REG_ADDR_8197F(v))
+
+/* 2 REG_HCI_MIX_CFG_8197F */
+#define BIT_RXRST_BACKDOOR_8197F BIT(31)
+#define BIT_TXRST_BACKDOOR_8197F BIT(30)
+#define BIT_RXIDX_RSTB_8197F BIT(29)
+#define BIT_TXIDX_RSTB_8197F BIT(28)
+#define BIT_DROP_NEXT_RXPKT_8197F BIT(27)
+#define BIT_SHORT_CORE_RST_SEL_8197F BIT(26)
+#define BIT_EXCEPT_RESUME_EN_8197F BIT(25)
+#define BIT_EXCEPT_RESUME_FLAG_8197F BIT(24)
+#define BIT_ALIGN_MTU_8197F BIT(23)
+#define BIT_HOST_GEN2_SUPPORT_8197F BIT(20)
+
+#define BIT_SHIFT_TXDMA_ERR_FLAG_8197F 16
+#define BIT_MASK_TXDMA_ERR_FLAG_8197F 0xf
+#define BIT_TXDMA_ERR_FLAG_8197F(x) \
+ (((x) & BIT_MASK_TXDMA_ERR_FLAG_8197F) \
+ << BIT_SHIFT_TXDMA_ERR_FLAG_8197F)
+#define BITS_TXDMA_ERR_FLAG_8197F \
+ (BIT_MASK_TXDMA_ERR_FLAG_8197F << BIT_SHIFT_TXDMA_ERR_FLAG_8197F)
+#define BIT_CLEAR_TXDMA_ERR_FLAG_8197F(x) ((x) & (~BITS_TXDMA_ERR_FLAG_8197F))
+#define BIT_GET_TXDMA_ERR_FLAG_8197F(x) \
+ (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_8197F) & \
+ BIT_MASK_TXDMA_ERR_FLAG_8197F)
+#define BIT_SET_TXDMA_ERR_FLAG_8197F(x, v) \
+ (BIT_CLEAR_TXDMA_ERR_FLAG_8197F(x) | BIT_TXDMA_ERR_FLAG_8197F(v))
+
+#define BIT_SHIFT_EARLY_MODE_SEL_8197F 12
+#define BIT_MASK_EARLY_MODE_SEL_8197F 0xf
+#define BIT_EARLY_MODE_SEL_8197F(x) \
+ (((x) & BIT_MASK_EARLY_MODE_SEL_8197F) \
+ << BIT_SHIFT_EARLY_MODE_SEL_8197F)
+#define BITS_EARLY_MODE_SEL_8197F \
+ (BIT_MASK_EARLY_MODE_SEL_8197F << BIT_SHIFT_EARLY_MODE_SEL_8197F)
+#define BIT_CLEAR_EARLY_MODE_SEL_8197F(x) ((x) & (~BITS_EARLY_MODE_SEL_8197F))
+#define BIT_GET_EARLY_MODE_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_EARLY_MODE_SEL_8197F) & \
+ BIT_MASK_EARLY_MODE_SEL_8197F)
+#define BIT_SET_EARLY_MODE_SEL_8197F(x, v) \
+ (BIT_CLEAR_EARLY_MODE_SEL_8197F(x) | BIT_EARLY_MODE_SEL_8197F(v))
+
+#define BIT_EPHY_RX50_EN_8197F BIT(11)
+
+#define BIT_SHIFT_MSI_TIMEOUT_ID_V1_8197F 8
+#define BIT_MASK_MSI_TIMEOUT_ID_V1_8197F 0x7
+#define BIT_MSI_TIMEOUT_ID_V1_8197F(x) \
+ (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8197F) \
+ << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8197F)
+#define BITS_MSI_TIMEOUT_ID_V1_8197F \
+ (BIT_MASK_MSI_TIMEOUT_ID_V1_8197F << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8197F)
+#define BIT_CLEAR_MSI_TIMEOUT_ID_V1_8197F(x) \
+ ((x) & (~BITS_MSI_TIMEOUT_ID_V1_8197F))
+#define BIT_GET_MSI_TIMEOUT_ID_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8197F) & \
+ BIT_MASK_MSI_TIMEOUT_ID_V1_8197F)
+#define BIT_SET_MSI_TIMEOUT_ID_V1_8197F(x, v) \
+ (BIT_CLEAR_MSI_TIMEOUT_ID_V1_8197F(x) | BIT_MSI_TIMEOUT_ID_V1_8197F(v))
+
+#define BIT_RADDR_RD_8197F BIT(7)
+#define BIT_EN_MUL_TAG_8197F BIT(6)
+#define BIT_EN_EARLY_MODE_8197F BIT(5)
+#define BIT_L0S_LINK_OFF_8197F BIT(4)
+#define BIT_ACT_LINK_OFF_8197F BIT(3)
+
+/* 2 REG_STC_INT_CS_8197F(HCI STATE CHANGE INTERRUPT CONTROL AND STATUS) */
+#define BIT_STC_INT_EN_8197F BIT(31)
+
+#define BIT_SHIFT_STC_INT_FLAG_8197F 16
+#define BIT_MASK_STC_INT_FLAG_8197F 0xff
+#define BIT_STC_INT_FLAG_8197F(x) \
+ (((x) & BIT_MASK_STC_INT_FLAG_8197F) << BIT_SHIFT_STC_INT_FLAG_8197F)
+#define BITS_STC_INT_FLAG_8197F \
+ (BIT_MASK_STC_INT_FLAG_8197F << BIT_SHIFT_STC_INT_FLAG_8197F)
+#define BIT_CLEAR_STC_INT_FLAG_8197F(x) ((x) & (~BITS_STC_INT_FLAG_8197F))
+#define BIT_GET_STC_INT_FLAG_8197F(x) \
+ (((x) >> BIT_SHIFT_STC_INT_FLAG_8197F) & BIT_MASK_STC_INT_FLAG_8197F)
+#define BIT_SET_STC_INT_FLAG_8197F(x, v) \
+ (BIT_CLEAR_STC_INT_FLAG_8197F(x) | BIT_STC_INT_FLAG_8197F(v))
+
+#define BIT_SHIFT_STC_INT_IDX_8197F 8
+#define BIT_MASK_STC_INT_IDX_8197F 0x7
+#define BIT_STC_INT_IDX_8197F(x) \
+ (((x) & BIT_MASK_STC_INT_IDX_8197F) << BIT_SHIFT_STC_INT_IDX_8197F)
+#define BITS_STC_INT_IDX_8197F \
+ (BIT_MASK_STC_INT_IDX_8197F << BIT_SHIFT_STC_INT_IDX_8197F)
+#define BIT_CLEAR_STC_INT_IDX_8197F(x) ((x) & (~BITS_STC_INT_IDX_8197F))
+#define BIT_GET_STC_INT_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_STC_INT_IDX_8197F) & BIT_MASK_STC_INT_IDX_8197F)
+#define BIT_SET_STC_INT_IDX_8197F(x, v) \
+ (BIT_CLEAR_STC_INT_IDX_8197F(x) | BIT_STC_INT_IDX_8197F(v))
+
+#define BIT_SHIFT_STC_INT_REALTIME_CS_8197F 0
+#define BIT_MASK_STC_INT_REALTIME_CS_8197F 0x3f
+#define BIT_STC_INT_REALTIME_CS_8197F(x) \
+ (((x) & BIT_MASK_STC_INT_REALTIME_CS_8197F) \
+ << BIT_SHIFT_STC_INT_REALTIME_CS_8197F)
+#define BITS_STC_INT_REALTIME_CS_8197F \
+ (BIT_MASK_STC_INT_REALTIME_CS_8197F \
+ << BIT_SHIFT_STC_INT_REALTIME_CS_8197F)
+#define BIT_CLEAR_STC_INT_REALTIME_CS_8197F(x) \
+ ((x) & (~BITS_STC_INT_REALTIME_CS_8197F))
+#define BIT_GET_STC_INT_REALTIME_CS_8197F(x) \
+ (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8197F) & \
+ BIT_MASK_STC_INT_REALTIME_CS_8197F)
+#define BIT_SET_STC_INT_REALTIME_CS_8197F(x, v) \
+ (BIT_CLEAR_STC_INT_REALTIME_CS_8197F(x) | \
+ BIT_STC_INT_REALTIME_CS_8197F(v))
+
+/* 2 REG_ST_INT_CFG_8197F(HCI STATE CHANGE INTERRUPT CONFIGURATION) */
+#define BIT_STC_INT_GRP_EN_8197F BIT(31)
+
+#define BIT_SHIFT_STC_INT_EXPECT_LS_8197F 8
+#define BIT_MASK_STC_INT_EXPECT_LS_8197F 0x3f
+#define BIT_STC_INT_EXPECT_LS_8197F(x) \
+ (((x) & BIT_MASK_STC_INT_EXPECT_LS_8197F) \
+ << BIT_SHIFT_STC_INT_EXPECT_LS_8197F)
+#define BITS_STC_INT_EXPECT_LS_8197F \
+ (BIT_MASK_STC_INT_EXPECT_LS_8197F << BIT_SHIFT_STC_INT_EXPECT_LS_8197F)
+#define BIT_CLEAR_STC_INT_EXPECT_LS_8197F(x) \
+ ((x) & (~BITS_STC_INT_EXPECT_LS_8197F))
+#define BIT_GET_STC_INT_EXPECT_LS_8197F(x) \
+ (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8197F) & \
+ BIT_MASK_STC_INT_EXPECT_LS_8197F)
+#define BIT_SET_STC_INT_EXPECT_LS_8197F(x, v) \
+ (BIT_CLEAR_STC_INT_EXPECT_LS_8197F(x) | BIT_STC_INT_EXPECT_LS_8197F(v))
+
+#define BIT_SHIFT_STC_INT_EXPECT_CS_8197F 0
+#define BIT_MASK_STC_INT_EXPECT_CS_8197F 0x3f
+#define BIT_STC_INT_EXPECT_CS_8197F(x) \
+ (((x) & BIT_MASK_STC_INT_EXPECT_CS_8197F) \
+ << BIT_SHIFT_STC_INT_EXPECT_CS_8197F)
+#define BITS_STC_INT_EXPECT_CS_8197F \
+ (BIT_MASK_STC_INT_EXPECT_CS_8197F << BIT_SHIFT_STC_INT_EXPECT_CS_8197F)
+#define BIT_CLEAR_STC_INT_EXPECT_CS_8197F(x) \
+ ((x) & (~BITS_STC_INT_EXPECT_CS_8197F))
+#define BIT_GET_STC_INT_EXPECT_CS_8197F(x) \
+ (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8197F) & \
+ BIT_MASK_STC_INT_EXPECT_CS_8197F)
+#define BIT_SET_STC_INT_EXPECT_CS_8197F(x, v) \
+ (BIT_CLEAR_STC_INT_EXPECT_CS_8197F(x) | BIT_STC_INT_EXPECT_CS_8197F(v))
+
+/* 2 REG_CMU_DLY_CTRL_8197F(HCI PHY CLOCK MGT UNIT DELAY CONTROL ) */
+#define BIT_CMU_DLY_EN_8197F BIT(31)
+#define BIT_CMU_DLY_MODE_8197F BIT(30)
+
+#define BIT_SHIFT_CMU_DLY_PRE_DIV_8197F 0
+#define BIT_MASK_CMU_DLY_PRE_DIV_8197F 0xff
+#define BIT_CMU_DLY_PRE_DIV_8197F(x) \
+ (((x) & BIT_MASK_CMU_DLY_PRE_DIV_8197F) \
+ << BIT_SHIFT_CMU_DLY_PRE_DIV_8197F)
+#define BITS_CMU_DLY_PRE_DIV_8197F \
+ (BIT_MASK_CMU_DLY_PRE_DIV_8197F << BIT_SHIFT_CMU_DLY_PRE_DIV_8197F)
+#define BIT_CLEAR_CMU_DLY_PRE_DIV_8197F(x) ((x) & (~BITS_CMU_DLY_PRE_DIV_8197F))
+#define BIT_GET_CMU_DLY_PRE_DIV_8197F(x) \
+ (((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV_8197F) & \
+ BIT_MASK_CMU_DLY_PRE_DIV_8197F)
+#define BIT_SET_CMU_DLY_PRE_DIV_8197F(x, v) \
+ (BIT_CLEAR_CMU_DLY_PRE_DIV_8197F(x) | BIT_CMU_DLY_PRE_DIV_8197F(v))
+
+/* 2 REG_CMU_DLY_CFG_8197F(HCI PHY CLOCK MGT UNIT DELAY CONFIGURATION ) */
+
+#define BIT_SHIFT_CMU_DLY_LTR_A2I_8197F 24
+#define BIT_MASK_CMU_DLY_LTR_A2I_8197F 0xff
+#define BIT_CMU_DLY_LTR_A2I_8197F(x) \
+ (((x) & BIT_MASK_CMU_DLY_LTR_A2I_8197F) \
+ << BIT_SHIFT_CMU_DLY_LTR_A2I_8197F)
+#define BITS_CMU_DLY_LTR_A2I_8197F \
+ (BIT_MASK_CMU_DLY_LTR_A2I_8197F << BIT_SHIFT_CMU_DLY_LTR_A2I_8197F)
+#define BIT_CLEAR_CMU_DLY_LTR_A2I_8197F(x) ((x) & (~BITS_CMU_DLY_LTR_A2I_8197F))
+#define BIT_GET_CMU_DLY_LTR_A2I_8197F(x) \
+ (((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I_8197F) & \
+ BIT_MASK_CMU_DLY_LTR_A2I_8197F)
+#define BIT_SET_CMU_DLY_LTR_A2I_8197F(x, v) \
+ (BIT_CLEAR_CMU_DLY_LTR_A2I_8197F(x) | BIT_CMU_DLY_LTR_A2I_8197F(v))
+
+#define BIT_SHIFT_CMU_DLY_LTR_I2A_8197F 16
+#define BIT_MASK_CMU_DLY_LTR_I2A_8197F 0xff
+#define BIT_CMU_DLY_LTR_I2A_8197F(x) \
+ (((x) & BIT_MASK_CMU_DLY_LTR_I2A_8197F) \
+ << BIT_SHIFT_CMU_DLY_LTR_I2A_8197F)
+#define BITS_CMU_DLY_LTR_I2A_8197F \
+ (BIT_MASK_CMU_DLY_LTR_I2A_8197F << BIT_SHIFT_CMU_DLY_LTR_I2A_8197F)
+#define BIT_CLEAR_CMU_DLY_LTR_I2A_8197F(x) ((x) & (~BITS_CMU_DLY_LTR_I2A_8197F))
+#define BIT_GET_CMU_DLY_LTR_I2A_8197F(x) \
+ (((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A_8197F) & \
+ BIT_MASK_CMU_DLY_LTR_I2A_8197F)
+#define BIT_SET_CMU_DLY_LTR_I2A_8197F(x, v) \
+ (BIT_CLEAR_CMU_DLY_LTR_I2A_8197F(x) | BIT_CMU_DLY_LTR_I2A_8197F(v))
+
+#define BIT_SHIFT_CMU_DLY_LTR_IDLE_8197F 8
+#define BIT_MASK_CMU_DLY_LTR_IDLE_8197F 0xff
+#define BIT_CMU_DLY_LTR_IDLE_8197F(x) \
+ (((x) & BIT_MASK_CMU_DLY_LTR_IDLE_8197F) \
+ << BIT_SHIFT_CMU_DLY_LTR_IDLE_8197F)
+#define BITS_CMU_DLY_LTR_IDLE_8197F \
+ (BIT_MASK_CMU_DLY_LTR_IDLE_8197F << BIT_SHIFT_CMU_DLY_LTR_IDLE_8197F)
+#define BIT_CLEAR_CMU_DLY_LTR_IDLE_8197F(x) \
+ ((x) & (~BITS_CMU_DLY_LTR_IDLE_8197F))
+#define BIT_GET_CMU_DLY_LTR_IDLE_8197F(x) \
+ (((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE_8197F) & \
+ BIT_MASK_CMU_DLY_LTR_IDLE_8197F)
+#define BIT_SET_CMU_DLY_LTR_IDLE_8197F(x, v) \
+ (BIT_CLEAR_CMU_DLY_LTR_IDLE_8197F(x) | BIT_CMU_DLY_LTR_IDLE_8197F(v))
+
+#define BIT_SHIFT_CMU_DLY_LTR_ACT_8197F 0
+#define BIT_MASK_CMU_DLY_LTR_ACT_8197F 0xff
+#define BIT_CMU_DLY_LTR_ACT_8197F(x) \
+ (((x) & BIT_MASK_CMU_DLY_LTR_ACT_8197F) \
+ << BIT_SHIFT_CMU_DLY_LTR_ACT_8197F)
+#define BITS_CMU_DLY_LTR_ACT_8197F \
+ (BIT_MASK_CMU_DLY_LTR_ACT_8197F << BIT_SHIFT_CMU_DLY_LTR_ACT_8197F)
+#define BIT_CLEAR_CMU_DLY_LTR_ACT_8197F(x) ((x) & (~BITS_CMU_DLY_LTR_ACT_8197F))
+#define BIT_GET_CMU_DLY_LTR_ACT_8197F(x) \
+ (((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT_8197F) & \
+ BIT_MASK_CMU_DLY_LTR_ACT_8197F)
+#define BIT_SET_CMU_DLY_LTR_ACT_8197F(x, v) \
+ (BIT_CLEAR_CMU_DLY_LTR_ACT_8197F(x) | BIT_CMU_DLY_LTR_ACT_8197F(v))
+
+/* 2 REG_H2CQ_TXBD_DESA_8197F */
+
+#define BIT_SHIFT_H2CQ_TXBD_DESA_8197F 0
+#define BIT_MASK_H2CQ_TXBD_DESA_8197F 0xffffffffffffffffL
+#define BIT_H2CQ_TXBD_DESA_8197F(x) \
+ (((x) & BIT_MASK_H2CQ_TXBD_DESA_8197F) \
+ << BIT_SHIFT_H2CQ_TXBD_DESA_8197F)
+#define BITS_H2CQ_TXBD_DESA_8197F \
+ (BIT_MASK_H2CQ_TXBD_DESA_8197F << BIT_SHIFT_H2CQ_TXBD_DESA_8197F)
+#define BIT_CLEAR_H2CQ_TXBD_DESA_8197F(x) ((x) & (~BITS_H2CQ_TXBD_DESA_8197F))
+#define BIT_GET_H2CQ_TXBD_DESA_8197F(x) \
+ (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_8197F) & \
+ BIT_MASK_H2CQ_TXBD_DESA_8197F)
+#define BIT_SET_H2CQ_TXBD_DESA_8197F(x, v) \
+ (BIT_CLEAR_H2CQ_TXBD_DESA_8197F(x) | BIT_H2CQ_TXBD_DESA_8197F(v))
+
+/* 2 REG_H2CQ_TXBD_NUM_8197F */
+#define BIT_HCI_H2CQ_FLAG_8197F BIT(14)
+
+#define BIT_SHIFT_H2CQ_DESC_MODE_8197F 12
+#define BIT_MASK_H2CQ_DESC_MODE_8197F 0x3
+#define BIT_H2CQ_DESC_MODE_8197F(x) \
+ (((x) & BIT_MASK_H2CQ_DESC_MODE_8197F) \
+ << BIT_SHIFT_H2CQ_DESC_MODE_8197F)
+#define BITS_H2CQ_DESC_MODE_8197F \
+ (BIT_MASK_H2CQ_DESC_MODE_8197F << BIT_SHIFT_H2CQ_DESC_MODE_8197F)
+#define BIT_CLEAR_H2CQ_DESC_MODE_8197F(x) ((x) & (~BITS_H2CQ_DESC_MODE_8197F))
+#define BIT_GET_H2CQ_DESC_MODE_8197F(x) \
+ (((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8197F) & \
+ BIT_MASK_H2CQ_DESC_MODE_8197F)
+#define BIT_SET_H2CQ_DESC_MODE_8197F(x, v) \
+ (BIT_CLEAR_H2CQ_DESC_MODE_8197F(x) | BIT_H2CQ_DESC_MODE_8197F(v))
+
+#define BIT_SHIFT_H2CQ_DESC_NUM_8197F 0
+#define BIT_MASK_H2CQ_DESC_NUM_8197F 0xfff
+#define BIT_H2CQ_DESC_NUM_8197F(x) \
+ (((x) & BIT_MASK_H2CQ_DESC_NUM_8197F) << BIT_SHIFT_H2CQ_DESC_NUM_8197F)
+#define BITS_H2CQ_DESC_NUM_8197F \
+ (BIT_MASK_H2CQ_DESC_NUM_8197F << BIT_SHIFT_H2CQ_DESC_NUM_8197F)
+#define BIT_CLEAR_H2CQ_DESC_NUM_8197F(x) ((x) & (~BITS_H2CQ_DESC_NUM_8197F))
+#define BIT_GET_H2CQ_DESC_NUM_8197F(x) \
+ (((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8197F) & BIT_MASK_H2CQ_DESC_NUM_8197F)
+#define BIT_SET_H2CQ_DESC_NUM_8197F(x, v) \
+ (BIT_CLEAR_H2CQ_DESC_NUM_8197F(x) | BIT_H2CQ_DESC_NUM_8197F(v))
+
+/* 2 REG_H2CQ_TXBD_IDX_8197F */
+
+#define BIT_SHIFT_H2CQ_HW_IDX_8197F 16
+#define BIT_MASK_H2CQ_HW_IDX_8197F 0xfff
+#define BIT_H2CQ_HW_IDX_8197F(x) \
+ (((x) & BIT_MASK_H2CQ_HW_IDX_8197F) << BIT_SHIFT_H2CQ_HW_IDX_8197F)
+#define BITS_H2CQ_HW_IDX_8197F \
+ (BIT_MASK_H2CQ_HW_IDX_8197F << BIT_SHIFT_H2CQ_HW_IDX_8197F)
+#define BIT_CLEAR_H2CQ_HW_IDX_8197F(x) ((x) & (~BITS_H2CQ_HW_IDX_8197F))
+#define BIT_GET_H2CQ_HW_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_H2CQ_HW_IDX_8197F) & BIT_MASK_H2CQ_HW_IDX_8197F)
+#define BIT_SET_H2CQ_HW_IDX_8197F(x, v) \
+ (BIT_CLEAR_H2CQ_HW_IDX_8197F(x) | BIT_H2CQ_HW_IDX_8197F(v))
+
+#define BIT_SHIFT_H2CQ_HOST_IDX_8197F 0
+#define BIT_MASK_H2CQ_HOST_IDX_8197F 0xfff
+#define BIT_H2CQ_HOST_IDX_8197F(x) \
+ (((x) & BIT_MASK_H2CQ_HOST_IDX_8197F) << BIT_SHIFT_H2CQ_HOST_IDX_8197F)
+#define BITS_H2CQ_HOST_IDX_8197F \
+ (BIT_MASK_H2CQ_HOST_IDX_8197F << BIT_SHIFT_H2CQ_HOST_IDX_8197F)
+#define BIT_CLEAR_H2CQ_HOST_IDX_8197F(x) ((x) & (~BITS_H2CQ_HOST_IDX_8197F))
+#define BIT_GET_H2CQ_HOST_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8197F) & BIT_MASK_H2CQ_HOST_IDX_8197F)
+#define BIT_SET_H2CQ_HOST_IDX_8197F(x, v) \
+ (BIT_CLEAR_H2CQ_HOST_IDX_8197F(x) | BIT_H2CQ_HOST_IDX_8197F(v))
+
+/* 2 REG_H2CQ_CSR_8197F[31:0] (H2CQ CONTROL AND STATUS) */
+#define BIT_H2CQ_FULL_8197F BIT(31)
+#define BIT_CLR_H2CQ_HOST_IDX_8197F BIT(16)
+#define BIT_CLR_H2CQ_HW_IDX_8197F BIT(8)
+#define BIT_STOP_H2CQ_8197F BIT(0)
+
+/* 2 REG_AXI_EXCEPT_CS_8197F[31:0] (AXI EXCEPTION CONTROL AND STATUS) */
+#define BIT_AXI_RXDMA_TIMEOUT_RE_8197F BIT(21)
+#define BIT_AXI_TXDMA_TIMEOUT_RE_8197F BIT(20)
+#define BIT_AXI_DECERR_W_RE_8197F BIT(19)
+#define BIT_AXI_DECERR_R_RE_8197F BIT(18)
+#define BIT_AXI_SLVERR_W_RE_8197F BIT(17)
+#define BIT_AXI_SLVERR_R_RE_8197F BIT(16)
+#define BIT_AXI_RXDMA_TIMEOUT_IE_8197F BIT(13)
+#define BIT_AXI_TXDMA_TIMEOUT_IE_8197F BIT(12)
+#define BIT_AXI_DECERR_W_IE_8197F BIT(11)
+#define BIT_AXI_DECERR_R_IE_8197F BIT(10)
+#define BIT_AXI_SLVERR_W_IE_8197F BIT(9)
+#define BIT_AXI_SLVERR_R_IE_8197F BIT(8)
+#define BIT_AXI_RXDMA_TIMEOUT_FLAG_8197F BIT(5)
+#define BIT_AXI_TXDMA_TIMEOUT_FLAG_8197F BIT(4)
+#define BIT_AXI_DECERR_W_FLAG_8197F BIT(3)
+#define BIT_AXI_DECERR_R_FLAG_8197F BIT(2)
+#define BIT_AXI_SLVERR_W_FLAG_8197F BIT(1)
+#define BIT_AXI_SLVERR_R_FLAG_8197F BIT(0)
+
+/* 2 REG_AXI_EXCEPT_TIME_8197F[31:0] (AXI EXCEPTION TIME CONTROL) */
+
+#define BIT_SHIFT_AXI_RECOVERY_TIME_8197F 24
+#define BIT_MASK_AXI_RECOVERY_TIME_8197F 0xff
+#define BIT_AXI_RECOVERY_TIME_8197F(x) \
+ (((x) & BIT_MASK_AXI_RECOVERY_TIME_8197F) \
+ << BIT_SHIFT_AXI_RECOVERY_TIME_8197F)
+#define BITS_AXI_RECOVERY_TIME_8197F \
+ (BIT_MASK_AXI_RECOVERY_TIME_8197F << BIT_SHIFT_AXI_RECOVERY_TIME_8197F)
+#define BIT_CLEAR_AXI_RECOVERY_TIME_8197F(x) \
+ ((x) & (~BITS_AXI_RECOVERY_TIME_8197F))
+#define BIT_GET_AXI_RECOVERY_TIME_8197F(x) \
+ (((x) >> BIT_SHIFT_AXI_RECOVERY_TIME_8197F) & \
+ BIT_MASK_AXI_RECOVERY_TIME_8197F)
+#define BIT_SET_AXI_RECOVERY_TIME_8197F(x, v) \
+ (BIT_CLEAR_AXI_RECOVERY_TIME_8197F(x) | BIT_AXI_RECOVERY_TIME_8197F(v))
+
+#define BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL_8197F 12
+#define BIT_MASK_AXI_RXDMA_TIMEOUT_VAL_8197F 0xfff
+#define BIT_AXI_RXDMA_TIMEOUT_VAL_8197F(x) \
+ (((x) & BIT_MASK_AXI_RXDMA_TIMEOUT_VAL_8197F) \
+ << BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL_8197F)
+#define BITS_AXI_RXDMA_TIMEOUT_VAL_8197F \
+ (BIT_MASK_AXI_RXDMA_TIMEOUT_VAL_8197F \
+ << BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL_8197F)
+#define BIT_CLEAR_AXI_RXDMA_TIMEOUT_VAL_8197F(x) \
+ ((x) & (~BITS_AXI_RXDMA_TIMEOUT_VAL_8197F))
+#define BIT_GET_AXI_RXDMA_TIMEOUT_VAL_8197F(x) \
+ (((x) >> BIT_SHIFT_AXI_RXDMA_TIMEOUT_VAL_8197F) & \
+ BIT_MASK_AXI_RXDMA_TIMEOUT_VAL_8197F)
+#define BIT_SET_AXI_RXDMA_TIMEOUT_VAL_8197F(x, v) \
+ (BIT_CLEAR_AXI_RXDMA_TIMEOUT_VAL_8197F(x) | \
+ BIT_AXI_RXDMA_TIMEOUT_VAL_8197F(v))
+
+#define BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL_8197F 0
+#define BIT_MASK_AXI_TXDMA_TIMEOUT_VAL_8197F 0xfff
+#define BIT_AXI_TXDMA_TIMEOUT_VAL_8197F(x) \
+ (((x) & BIT_MASK_AXI_TXDMA_TIMEOUT_VAL_8197F) \
+ << BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL_8197F)
+#define BITS_AXI_TXDMA_TIMEOUT_VAL_8197F \
+ (BIT_MASK_AXI_TXDMA_TIMEOUT_VAL_8197F \
+ << BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL_8197F)
+#define BIT_CLEAR_AXI_TXDMA_TIMEOUT_VAL_8197F(x) \
+ ((x) & (~BITS_AXI_TXDMA_TIMEOUT_VAL_8197F))
+#define BIT_GET_AXI_TXDMA_TIMEOUT_VAL_8197F(x) \
+ (((x) >> BIT_SHIFT_AXI_TXDMA_TIMEOUT_VAL_8197F) & \
+ BIT_MASK_AXI_TXDMA_TIMEOUT_VAL_8197F)
+#define BIT_SET_AXI_TXDMA_TIMEOUT_VAL_8197F(x, v) \
+ (BIT_CLEAR_AXI_TXDMA_TIMEOUT_VAL_8197F(x) | \
+ BIT_AXI_TXDMA_TIMEOUT_VAL_8197F(v))
+
+/* 2 REG_Q0_INFO_8197F */
+
+#define BIT_SHIFT_QUEUEMACID_Q0_V1_8197F 25
+#define BIT_MASK_QUEUEMACID_Q0_V1_8197F 0x7f
+#define BIT_QUEUEMACID_Q0_V1_8197F(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q0_V1_8197F) \
+ << BIT_SHIFT_QUEUEMACID_Q0_V1_8197F)
+#define BITS_QUEUEMACID_Q0_V1_8197F \
+ (BIT_MASK_QUEUEMACID_Q0_V1_8197F << BIT_SHIFT_QUEUEMACID_Q0_V1_8197F)
+#define BIT_CLEAR_QUEUEMACID_Q0_V1_8197F(x) \
+ ((x) & (~BITS_QUEUEMACID_Q0_V1_8197F))
+#define BIT_GET_QUEUEMACID_Q0_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1_8197F) & \
+ BIT_MASK_QUEUEMACID_Q0_V1_8197F)
+#define BIT_SET_QUEUEMACID_Q0_V1_8197F(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q0_V1_8197F(x) | BIT_QUEUEMACID_Q0_V1_8197F(v))
+
+#define BIT_SHIFT_QUEUEAC_Q0_V1_8197F 23
+#define BIT_MASK_QUEUEAC_Q0_V1_8197F 0x3
+#define BIT_QUEUEAC_Q0_V1_8197F(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q0_V1_8197F) << BIT_SHIFT_QUEUEAC_Q0_V1_8197F)
+#define BITS_QUEUEAC_Q0_V1_8197F \
+ (BIT_MASK_QUEUEAC_Q0_V1_8197F << BIT_SHIFT_QUEUEAC_Q0_V1_8197F)
+#define BIT_CLEAR_QUEUEAC_Q0_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q0_V1_8197F))
+#define BIT_GET_QUEUEAC_Q0_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q0_V1_8197F) & BIT_MASK_QUEUEAC_Q0_V1_8197F)
+#define BIT_SET_QUEUEAC_Q0_V1_8197F(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q0_V1_8197F(x) | BIT_QUEUEAC_Q0_V1_8197F(v))
+
+#define BIT_TIDEMPTY_Q0_V1_8197F BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q0_V2_8197F 11
+#define BIT_MASK_TAIL_PKT_Q0_V2_8197F 0x7ff
+#define BIT_TAIL_PKT_Q0_V2_8197F(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q0_V2_8197F) \
+ << BIT_SHIFT_TAIL_PKT_Q0_V2_8197F)
+#define BITS_TAIL_PKT_Q0_V2_8197F \
+ (BIT_MASK_TAIL_PKT_Q0_V2_8197F << BIT_SHIFT_TAIL_PKT_Q0_V2_8197F)
+#define BIT_CLEAR_TAIL_PKT_Q0_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q0_V2_8197F))
+#define BIT_GET_TAIL_PKT_Q0_V2_8197F(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2_8197F) & \
+ BIT_MASK_TAIL_PKT_Q0_V2_8197F)
+#define BIT_SET_TAIL_PKT_Q0_V2_8197F(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q0_V2_8197F(x) | BIT_TAIL_PKT_Q0_V2_8197F(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q0_V1_8197F 0
+#define BIT_MASK_HEAD_PKT_Q0_V1_8197F 0x7ff
+#define BIT_HEAD_PKT_Q0_V1_8197F(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q0_V1_8197F) \
+ << BIT_SHIFT_HEAD_PKT_Q0_V1_8197F)
+#define BITS_HEAD_PKT_Q0_V1_8197F \
+ (BIT_MASK_HEAD_PKT_Q0_V1_8197F << BIT_SHIFT_HEAD_PKT_Q0_V1_8197F)
+#define BIT_CLEAR_HEAD_PKT_Q0_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q0_V1_8197F))
+#define BIT_GET_HEAD_PKT_Q0_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1_8197F) & \
+ BIT_MASK_HEAD_PKT_Q0_V1_8197F)
+#define BIT_SET_HEAD_PKT_Q0_V1_8197F(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q0_V1_8197F(x) | BIT_HEAD_PKT_Q0_V1_8197F(v))
+
+/* 2 REG_Q1_INFO_8197F */
+
+#define BIT_SHIFT_QUEUEMACID_Q1_V1_8197F 25
+#define BIT_MASK_QUEUEMACID_Q1_V1_8197F 0x7f
+#define BIT_QUEUEMACID_Q1_V1_8197F(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q1_V1_8197F) \
+ << BIT_SHIFT_QUEUEMACID_Q1_V1_8197F)
+#define BITS_QUEUEMACID_Q1_V1_8197F \
+ (BIT_MASK_QUEUEMACID_Q1_V1_8197F << BIT_SHIFT_QUEUEMACID_Q1_V1_8197F)
+#define BIT_CLEAR_QUEUEMACID_Q1_V1_8197F(x) \
+ ((x) & (~BITS_QUEUEMACID_Q1_V1_8197F))
+#define BIT_GET_QUEUEMACID_Q1_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1_8197F) & \
+ BIT_MASK_QUEUEMACID_Q1_V1_8197F)
+#define BIT_SET_QUEUEMACID_Q1_V1_8197F(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q1_V1_8197F(x) | BIT_QUEUEMACID_Q1_V1_8197F(v))
+
+#define BIT_SHIFT_QUEUEAC_Q1_V1_8197F 23
+#define BIT_MASK_QUEUEAC_Q1_V1_8197F 0x3
+#define BIT_QUEUEAC_Q1_V1_8197F(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q1_V1_8197F) << BIT_SHIFT_QUEUEAC_Q1_V1_8197F)
+#define BITS_QUEUEAC_Q1_V1_8197F \
+ (BIT_MASK_QUEUEAC_Q1_V1_8197F << BIT_SHIFT_QUEUEAC_Q1_V1_8197F)
+#define BIT_CLEAR_QUEUEAC_Q1_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q1_V1_8197F))
+#define BIT_GET_QUEUEAC_Q1_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q1_V1_8197F) & BIT_MASK_QUEUEAC_Q1_V1_8197F)
+#define BIT_SET_QUEUEAC_Q1_V1_8197F(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q1_V1_8197F(x) | BIT_QUEUEAC_Q1_V1_8197F(v))
+
+#define BIT_TIDEMPTY_Q1_V1_8197F BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q1_V2_8197F 11
+#define BIT_MASK_TAIL_PKT_Q1_V2_8197F 0x7ff
+#define BIT_TAIL_PKT_Q1_V2_8197F(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q1_V2_8197F) \
+ << BIT_SHIFT_TAIL_PKT_Q1_V2_8197F)
+#define BITS_TAIL_PKT_Q1_V2_8197F \
+ (BIT_MASK_TAIL_PKT_Q1_V2_8197F << BIT_SHIFT_TAIL_PKT_Q1_V2_8197F)
+#define BIT_CLEAR_TAIL_PKT_Q1_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q1_V2_8197F))
+#define BIT_GET_TAIL_PKT_Q1_V2_8197F(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2_8197F) & \
+ BIT_MASK_TAIL_PKT_Q1_V2_8197F)
+#define BIT_SET_TAIL_PKT_Q1_V2_8197F(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q1_V2_8197F(x) | BIT_TAIL_PKT_Q1_V2_8197F(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q1_V1_8197F 0
+#define BIT_MASK_HEAD_PKT_Q1_V1_8197F 0x7ff
+#define BIT_HEAD_PKT_Q1_V1_8197F(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q1_V1_8197F) \
+ << BIT_SHIFT_HEAD_PKT_Q1_V1_8197F)
+#define BITS_HEAD_PKT_Q1_V1_8197F \
+ (BIT_MASK_HEAD_PKT_Q1_V1_8197F << BIT_SHIFT_HEAD_PKT_Q1_V1_8197F)
+#define BIT_CLEAR_HEAD_PKT_Q1_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q1_V1_8197F))
+#define BIT_GET_HEAD_PKT_Q1_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1_8197F) & \
+ BIT_MASK_HEAD_PKT_Q1_V1_8197F)
+#define BIT_SET_HEAD_PKT_Q1_V1_8197F(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q1_V1_8197F(x) | BIT_HEAD_PKT_Q1_V1_8197F(v))
+
+/* 2 REG_Q2_INFO_8197F */
+
+#define BIT_SHIFT_QUEUEMACID_Q2_V1_8197F 25
+#define BIT_MASK_QUEUEMACID_Q2_V1_8197F 0x7f
+#define BIT_QUEUEMACID_Q2_V1_8197F(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q2_V1_8197F) \
+ << BIT_SHIFT_QUEUEMACID_Q2_V1_8197F)
+#define BITS_QUEUEMACID_Q2_V1_8197F \
+ (BIT_MASK_QUEUEMACID_Q2_V1_8197F << BIT_SHIFT_QUEUEMACID_Q2_V1_8197F)
+#define BIT_CLEAR_QUEUEMACID_Q2_V1_8197F(x) \
+ ((x) & (~BITS_QUEUEMACID_Q2_V1_8197F))
+#define BIT_GET_QUEUEMACID_Q2_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1_8197F) & \
+ BIT_MASK_QUEUEMACID_Q2_V1_8197F)
+#define BIT_SET_QUEUEMACID_Q2_V1_8197F(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q2_V1_8197F(x) | BIT_QUEUEMACID_Q2_V1_8197F(v))
+
+#define BIT_SHIFT_QUEUEAC_Q2_V1_8197F 23
+#define BIT_MASK_QUEUEAC_Q2_V1_8197F 0x3
+#define BIT_QUEUEAC_Q2_V1_8197F(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q2_V1_8197F) << BIT_SHIFT_QUEUEAC_Q2_V1_8197F)
+#define BITS_QUEUEAC_Q2_V1_8197F \
+ (BIT_MASK_QUEUEAC_Q2_V1_8197F << BIT_SHIFT_QUEUEAC_Q2_V1_8197F)
+#define BIT_CLEAR_QUEUEAC_Q2_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q2_V1_8197F))
+#define BIT_GET_QUEUEAC_Q2_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q2_V1_8197F) & BIT_MASK_QUEUEAC_Q2_V1_8197F)
+#define BIT_SET_QUEUEAC_Q2_V1_8197F(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q2_V1_8197F(x) | BIT_QUEUEAC_Q2_V1_8197F(v))
+
+#define BIT_TIDEMPTY_Q2_V1_8197F BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q2_V2_8197F 11
+#define BIT_MASK_TAIL_PKT_Q2_V2_8197F 0x7ff
+#define BIT_TAIL_PKT_Q2_V2_8197F(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q2_V2_8197F) \
+ << BIT_SHIFT_TAIL_PKT_Q2_V2_8197F)
+#define BITS_TAIL_PKT_Q2_V2_8197F \
+ (BIT_MASK_TAIL_PKT_Q2_V2_8197F << BIT_SHIFT_TAIL_PKT_Q2_V2_8197F)
+#define BIT_CLEAR_TAIL_PKT_Q2_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q2_V2_8197F))
+#define BIT_GET_TAIL_PKT_Q2_V2_8197F(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2_8197F) & \
+ BIT_MASK_TAIL_PKT_Q2_V2_8197F)
+#define BIT_SET_TAIL_PKT_Q2_V2_8197F(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q2_V2_8197F(x) | BIT_TAIL_PKT_Q2_V2_8197F(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q2_V1_8197F 0
+#define BIT_MASK_HEAD_PKT_Q2_V1_8197F 0x7ff
+#define BIT_HEAD_PKT_Q2_V1_8197F(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q2_V1_8197F) \
+ << BIT_SHIFT_HEAD_PKT_Q2_V1_8197F)
+#define BITS_HEAD_PKT_Q2_V1_8197F \
+ (BIT_MASK_HEAD_PKT_Q2_V1_8197F << BIT_SHIFT_HEAD_PKT_Q2_V1_8197F)
+#define BIT_CLEAR_HEAD_PKT_Q2_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q2_V1_8197F))
+#define BIT_GET_HEAD_PKT_Q2_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1_8197F) & \
+ BIT_MASK_HEAD_PKT_Q2_V1_8197F)
+#define BIT_SET_HEAD_PKT_Q2_V1_8197F(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q2_V1_8197F(x) | BIT_HEAD_PKT_Q2_V1_8197F(v))
+
+/* 2 REG_Q3_INFO_8197F */
+
+#define BIT_SHIFT_QUEUEMACID_Q3_V1_8197F 25
+#define BIT_MASK_QUEUEMACID_Q3_V1_8197F 0x7f
+#define BIT_QUEUEMACID_Q3_V1_8197F(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q3_V1_8197F) \
+ << BIT_SHIFT_QUEUEMACID_Q3_V1_8197F)
+#define BITS_QUEUEMACID_Q3_V1_8197F \
+ (BIT_MASK_QUEUEMACID_Q3_V1_8197F << BIT_SHIFT_QUEUEMACID_Q3_V1_8197F)
+#define BIT_CLEAR_QUEUEMACID_Q3_V1_8197F(x) \
+ ((x) & (~BITS_QUEUEMACID_Q3_V1_8197F))
+#define BIT_GET_QUEUEMACID_Q3_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1_8197F) & \
+ BIT_MASK_QUEUEMACID_Q3_V1_8197F)
+#define BIT_SET_QUEUEMACID_Q3_V1_8197F(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q3_V1_8197F(x) | BIT_QUEUEMACID_Q3_V1_8197F(v))
+
+#define BIT_SHIFT_QUEUEAC_Q3_V1_8197F 23
+#define BIT_MASK_QUEUEAC_Q3_V1_8197F 0x3
+#define BIT_QUEUEAC_Q3_V1_8197F(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q3_V1_8197F) << BIT_SHIFT_QUEUEAC_Q3_V1_8197F)
+#define BITS_QUEUEAC_Q3_V1_8197F \
+ (BIT_MASK_QUEUEAC_Q3_V1_8197F << BIT_SHIFT_QUEUEAC_Q3_V1_8197F)
+#define BIT_CLEAR_QUEUEAC_Q3_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q3_V1_8197F))
+#define BIT_GET_QUEUEAC_Q3_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q3_V1_8197F) & BIT_MASK_QUEUEAC_Q3_V1_8197F)
+#define BIT_SET_QUEUEAC_Q3_V1_8197F(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q3_V1_8197F(x) | BIT_QUEUEAC_Q3_V1_8197F(v))
+
+#define BIT_TIDEMPTY_Q3_V1_8197F BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q3_V2_8197F 11
+#define BIT_MASK_TAIL_PKT_Q3_V2_8197F 0x7ff
+#define BIT_TAIL_PKT_Q3_V2_8197F(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q3_V2_8197F) \
+ << BIT_SHIFT_TAIL_PKT_Q3_V2_8197F)
+#define BITS_TAIL_PKT_Q3_V2_8197F \
+ (BIT_MASK_TAIL_PKT_Q3_V2_8197F << BIT_SHIFT_TAIL_PKT_Q3_V2_8197F)
+#define BIT_CLEAR_TAIL_PKT_Q3_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q3_V2_8197F))
+#define BIT_GET_TAIL_PKT_Q3_V2_8197F(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2_8197F) & \
+ BIT_MASK_TAIL_PKT_Q3_V2_8197F)
+#define BIT_SET_TAIL_PKT_Q3_V2_8197F(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q3_V2_8197F(x) | BIT_TAIL_PKT_Q3_V2_8197F(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q3_V1_8197F 0
+#define BIT_MASK_HEAD_PKT_Q3_V1_8197F 0x7ff
+#define BIT_HEAD_PKT_Q3_V1_8197F(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q3_V1_8197F) \
+ << BIT_SHIFT_HEAD_PKT_Q3_V1_8197F)
+#define BITS_HEAD_PKT_Q3_V1_8197F \
+ (BIT_MASK_HEAD_PKT_Q3_V1_8197F << BIT_SHIFT_HEAD_PKT_Q3_V1_8197F)
+#define BIT_CLEAR_HEAD_PKT_Q3_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q3_V1_8197F))
+#define BIT_GET_HEAD_PKT_Q3_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1_8197F) & \
+ BIT_MASK_HEAD_PKT_Q3_V1_8197F)
+#define BIT_SET_HEAD_PKT_Q3_V1_8197F(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q3_V1_8197F(x) | BIT_HEAD_PKT_Q3_V1_8197F(v))
+
+/* 2 REG_MGQ_INFO_8197F */
+
+#define BIT_SHIFT_QUEUEMACID_MGQ_V1_8197F 25
+#define BIT_MASK_QUEUEMACID_MGQ_V1_8197F 0x7f
+#define BIT_QUEUEMACID_MGQ_V1_8197F(x) \
+ (((x) & BIT_MASK_QUEUEMACID_MGQ_V1_8197F) \
+ << BIT_SHIFT_QUEUEMACID_MGQ_V1_8197F)
+#define BITS_QUEUEMACID_MGQ_V1_8197F \
+ (BIT_MASK_QUEUEMACID_MGQ_V1_8197F << BIT_SHIFT_QUEUEMACID_MGQ_V1_8197F)
+#define BIT_CLEAR_QUEUEMACID_MGQ_V1_8197F(x) \
+ ((x) & (~BITS_QUEUEMACID_MGQ_V1_8197F))
+#define BIT_GET_QUEUEMACID_MGQ_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1_8197F) & \
+ BIT_MASK_QUEUEMACID_MGQ_V1_8197F)
+#define BIT_SET_QUEUEMACID_MGQ_V1_8197F(x, v) \
+ (BIT_CLEAR_QUEUEMACID_MGQ_V1_8197F(x) | BIT_QUEUEMACID_MGQ_V1_8197F(v))
+
+#define BIT_SHIFT_QUEUEAC_MGQ_V1_8197F 23
+#define BIT_MASK_QUEUEAC_MGQ_V1_8197F 0x3
+#define BIT_QUEUEAC_MGQ_V1_8197F(x) \
+ (((x) & BIT_MASK_QUEUEAC_MGQ_V1_8197F) \
+ << BIT_SHIFT_QUEUEAC_MGQ_V1_8197F)
+#define BITS_QUEUEAC_MGQ_V1_8197F \
+ (BIT_MASK_QUEUEAC_MGQ_V1_8197F << BIT_SHIFT_QUEUEAC_MGQ_V1_8197F)
+#define BIT_CLEAR_QUEUEAC_MGQ_V1_8197F(x) ((x) & (~BITS_QUEUEAC_MGQ_V1_8197F))
+#define BIT_GET_QUEUEAC_MGQ_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1_8197F) & \
+ BIT_MASK_QUEUEAC_MGQ_V1_8197F)
+#define BIT_SET_QUEUEAC_MGQ_V1_8197F(x, v) \
+ (BIT_CLEAR_QUEUEAC_MGQ_V1_8197F(x) | BIT_QUEUEAC_MGQ_V1_8197F(v))
+
+#define BIT_TIDEMPTY_MGQ_V1_8197F BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_MGQ_V2_8197F 11
+#define BIT_MASK_TAIL_PKT_MGQ_V2_8197F 0x7ff
+#define BIT_TAIL_PKT_MGQ_V2_8197F(x) \
+ (((x) & BIT_MASK_TAIL_PKT_MGQ_V2_8197F) \
+ << BIT_SHIFT_TAIL_PKT_MGQ_V2_8197F)
+#define BITS_TAIL_PKT_MGQ_V2_8197F \
+ (BIT_MASK_TAIL_PKT_MGQ_V2_8197F << BIT_SHIFT_TAIL_PKT_MGQ_V2_8197F)
+#define BIT_CLEAR_TAIL_PKT_MGQ_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_MGQ_V2_8197F))
+#define BIT_GET_TAIL_PKT_MGQ_V2_8197F(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2_8197F) & \
+ BIT_MASK_TAIL_PKT_MGQ_V2_8197F)
+#define BIT_SET_TAIL_PKT_MGQ_V2_8197F(x, v) \
+ (BIT_CLEAR_TAIL_PKT_MGQ_V2_8197F(x) | BIT_TAIL_PKT_MGQ_V2_8197F(v))
+
+#define BIT_SHIFT_HEAD_PKT_MGQ_V1_8197F 0
+#define BIT_MASK_HEAD_PKT_MGQ_V1_8197F 0x7ff
+#define BIT_HEAD_PKT_MGQ_V1_8197F(x) \
+ (((x) & BIT_MASK_HEAD_PKT_MGQ_V1_8197F) \
+ << BIT_SHIFT_HEAD_PKT_MGQ_V1_8197F)
+#define BITS_HEAD_PKT_MGQ_V1_8197F \
+ (BIT_MASK_HEAD_PKT_MGQ_V1_8197F << BIT_SHIFT_HEAD_PKT_MGQ_V1_8197F)
+#define BIT_CLEAR_HEAD_PKT_MGQ_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_MGQ_V1_8197F))
+#define BIT_GET_HEAD_PKT_MGQ_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1_8197F) & \
+ BIT_MASK_HEAD_PKT_MGQ_V1_8197F)
+#define BIT_SET_HEAD_PKT_MGQ_V1_8197F(x, v) \
+ (BIT_CLEAR_HEAD_PKT_MGQ_V1_8197F(x) | BIT_HEAD_PKT_MGQ_V1_8197F(v))
+
+/* 2 REG_HIQ_INFO_8197F */
+
+#define BIT_SHIFT_QUEUEMACID_HIQ_V1_8197F 25
+#define BIT_MASK_QUEUEMACID_HIQ_V1_8197F 0x7f
+#define BIT_QUEUEMACID_HIQ_V1_8197F(x) \
+ (((x) & BIT_MASK_QUEUEMACID_HIQ_V1_8197F) \
+ << BIT_SHIFT_QUEUEMACID_HIQ_V1_8197F)
+#define BITS_QUEUEMACID_HIQ_V1_8197F \
+ (BIT_MASK_QUEUEMACID_HIQ_V1_8197F << BIT_SHIFT_QUEUEMACID_HIQ_V1_8197F)
+#define BIT_CLEAR_QUEUEMACID_HIQ_V1_8197F(x) \
+ ((x) & (~BITS_QUEUEMACID_HIQ_V1_8197F))
+#define BIT_GET_QUEUEMACID_HIQ_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1_8197F) & \
+ BIT_MASK_QUEUEMACID_HIQ_V1_8197F)
+#define BIT_SET_QUEUEMACID_HIQ_V1_8197F(x, v) \
+ (BIT_CLEAR_QUEUEMACID_HIQ_V1_8197F(x) | BIT_QUEUEMACID_HIQ_V1_8197F(v))
+
+#define BIT_SHIFT_QUEUEAC_HIQ_V1_8197F 23
+#define BIT_MASK_QUEUEAC_HIQ_V1_8197F 0x3
+#define BIT_QUEUEAC_HIQ_V1_8197F(x) \
+ (((x) & BIT_MASK_QUEUEAC_HIQ_V1_8197F) \
+ << BIT_SHIFT_QUEUEAC_HIQ_V1_8197F)
+#define BITS_QUEUEAC_HIQ_V1_8197F \
+ (BIT_MASK_QUEUEAC_HIQ_V1_8197F << BIT_SHIFT_QUEUEAC_HIQ_V1_8197F)
+#define BIT_CLEAR_QUEUEAC_HIQ_V1_8197F(x) ((x) & (~BITS_QUEUEAC_HIQ_V1_8197F))
+#define BIT_GET_QUEUEAC_HIQ_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1_8197F) & \
+ BIT_MASK_QUEUEAC_HIQ_V1_8197F)
+#define BIT_SET_QUEUEAC_HIQ_V1_8197F(x, v) \
+ (BIT_CLEAR_QUEUEAC_HIQ_V1_8197F(x) | BIT_QUEUEAC_HIQ_V1_8197F(v))
+
+#define BIT_TIDEMPTY_HIQ_V1_8197F BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_HIQ_V2_8197F 11
+#define BIT_MASK_TAIL_PKT_HIQ_V2_8197F 0x7ff
+#define BIT_TAIL_PKT_HIQ_V2_8197F(x) \
+ (((x) & BIT_MASK_TAIL_PKT_HIQ_V2_8197F) \
+ << BIT_SHIFT_TAIL_PKT_HIQ_V2_8197F)
+#define BITS_TAIL_PKT_HIQ_V2_8197F \
+ (BIT_MASK_TAIL_PKT_HIQ_V2_8197F << BIT_SHIFT_TAIL_PKT_HIQ_V2_8197F)
+#define BIT_CLEAR_TAIL_PKT_HIQ_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_HIQ_V2_8197F))
+#define BIT_GET_TAIL_PKT_HIQ_V2_8197F(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2_8197F) & \
+ BIT_MASK_TAIL_PKT_HIQ_V2_8197F)
+#define BIT_SET_TAIL_PKT_HIQ_V2_8197F(x, v) \
+ (BIT_CLEAR_TAIL_PKT_HIQ_V2_8197F(x) | BIT_TAIL_PKT_HIQ_V2_8197F(v))
+
+#define BIT_SHIFT_HEAD_PKT_HIQ_V1_8197F 0
+#define BIT_MASK_HEAD_PKT_HIQ_V1_8197F 0x7ff
+#define BIT_HEAD_PKT_HIQ_V1_8197F(x) \
+ (((x) & BIT_MASK_HEAD_PKT_HIQ_V1_8197F) \
+ << BIT_SHIFT_HEAD_PKT_HIQ_V1_8197F)
+#define BITS_HEAD_PKT_HIQ_V1_8197F \
+ (BIT_MASK_HEAD_PKT_HIQ_V1_8197F << BIT_SHIFT_HEAD_PKT_HIQ_V1_8197F)
+#define BIT_CLEAR_HEAD_PKT_HIQ_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_HIQ_V1_8197F))
+#define BIT_GET_HEAD_PKT_HIQ_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1_8197F) & \
+ BIT_MASK_HEAD_PKT_HIQ_V1_8197F)
+#define BIT_SET_HEAD_PKT_HIQ_V1_8197F(x, v) \
+ (BIT_CLEAR_HEAD_PKT_HIQ_V1_8197F(x) | BIT_HEAD_PKT_HIQ_V1_8197F(v))
+
+/* 2 REG_BCNQ_INFO_8197F */
+
+#define BIT_SHIFT_BCNQ_HEAD_PG_V1_8197F 0
+#define BIT_MASK_BCNQ_HEAD_PG_V1_8197F 0xfff
+#define BIT_BCNQ_HEAD_PG_V1_8197F(x) \
+ (((x) & BIT_MASK_BCNQ_HEAD_PG_V1_8197F) \
+ << BIT_SHIFT_BCNQ_HEAD_PG_V1_8197F)
+#define BITS_BCNQ_HEAD_PG_V1_8197F \
+ (BIT_MASK_BCNQ_HEAD_PG_V1_8197F << BIT_SHIFT_BCNQ_HEAD_PG_V1_8197F)
+#define BIT_CLEAR_BCNQ_HEAD_PG_V1_8197F(x) ((x) & (~BITS_BCNQ_HEAD_PG_V1_8197F))
+#define BIT_GET_BCNQ_HEAD_PG_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1_8197F) & \
+ BIT_MASK_BCNQ_HEAD_PG_V1_8197F)
+#define BIT_SET_BCNQ_HEAD_PG_V1_8197F(x, v) \
+ (BIT_CLEAR_BCNQ_HEAD_PG_V1_8197F(x) | BIT_BCNQ_HEAD_PG_V1_8197F(v))
+
+/* 2 REG_TXPKT_EMPTY_8197F */
+#define BIT_BCNQ_EMPTY_8197F BIT(11)
+#define BIT_HQQ_EMPTY_8197F BIT(10)
+#define BIT_MQQ_EMPTY_8197F BIT(9)
+#define BIT_MGQ_CPU_EMPTY_8197F BIT(8)
+#define BIT_AC7Q_EMPTY_8197F BIT(7)
+#define BIT_AC6Q_EMPTY_8197F BIT(6)
+#define BIT_AC5Q_EMPTY_8197F BIT(5)
+#define BIT_AC4Q_EMPTY_8197F BIT(4)
+#define BIT_AC3Q_EMPTY_8197F BIT(3)
+#define BIT_AC2Q_EMPTY_8197F BIT(2)
+#define BIT_AC1Q_EMPTY_8197F BIT(1)
+#define BIT_AC0Q_EMPTY_8197F BIT(0)
+
+/* 2 REG_CPU_MGQ_INFO_8197F */
+#define BIT_BCN1_POLL_8197F BIT(30)
+#define BIT_CPUMGT_POLL_8197F BIT(29)
+#define BIT_BCN_POLL_8197F BIT(28)
+#define BIT_CPUMGQ_FW_NUM_V1_8197F BIT(12)
+
+#define BIT_SHIFT_FW_FREE_TAIL_V1_8197F 0
+#define BIT_MASK_FW_FREE_TAIL_V1_8197F 0xfff
+#define BIT_FW_FREE_TAIL_V1_8197F(x) \
+ (((x) & BIT_MASK_FW_FREE_TAIL_V1_8197F) \
+ << BIT_SHIFT_FW_FREE_TAIL_V1_8197F)
+#define BITS_FW_FREE_TAIL_V1_8197F \
+ (BIT_MASK_FW_FREE_TAIL_V1_8197F << BIT_SHIFT_FW_FREE_TAIL_V1_8197F)
+#define BIT_CLEAR_FW_FREE_TAIL_V1_8197F(x) ((x) & (~BITS_FW_FREE_TAIL_V1_8197F))
+#define BIT_GET_FW_FREE_TAIL_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_FW_FREE_TAIL_V1_8197F) & \
+ BIT_MASK_FW_FREE_TAIL_V1_8197F)
+#define BIT_SET_FW_FREE_TAIL_V1_8197F(x, v) \
+ (BIT_CLEAR_FW_FREE_TAIL_V1_8197F(x) | BIT_FW_FREE_TAIL_V1_8197F(v))
+
+/* 2 REG_FWHW_TXQ_CTRL_8197F */
+#define BIT_RTS_LIMIT_IN_OFDM_8197F BIT(23)
+#define BIT_EN_BCNQ_DL_8197F BIT(22)
+#define BIT_EN_RD_RESP_NAV_BK_8197F BIT(21)
+#define BIT_EN_WR_FREE_TAIL_8197F BIT(20)
+
+#define BIT_SHIFT_EN_QUEUE_RPT_8197F 8
+#define BIT_MASK_EN_QUEUE_RPT_8197F 0xff
+#define BIT_EN_QUEUE_RPT_8197F(x) \
+ (((x) & BIT_MASK_EN_QUEUE_RPT_8197F) << BIT_SHIFT_EN_QUEUE_RPT_8197F)
+#define BITS_EN_QUEUE_RPT_8197F \
+ (BIT_MASK_EN_QUEUE_RPT_8197F << BIT_SHIFT_EN_QUEUE_RPT_8197F)
+#define BIT_CLEAR_EN_QUEUE_RPT_8197F(x) ((x) & (~BITS_EN_QUEUE_RPT_8197F))
+#define BIT_GET_EN_QUEUE_RPT_8197F(x) \
+ (((x) >> BIT_SHIFT_EN_QUEUE_RPT_8197F) & BIT_MASK_EN_QUEUE_RPT_8197F)
+#define BIT_SET_EN_QUEUE_RPT_8197F(x, v) \
+ (BIT_CLEAR_EN_QUEUE_RPT_8197F(x) | BIT_EN_QUEUE_RPT_8197F(v))
+
+#define BIT_EN_RTY_BK_8197F BIT(7)
+#define BIT_EN_USE_INI_RAT_8197F BIT(6)
+#define BIT_EN_RTS_NAV_BK_8197F BIT(5)
+#define BIT_DIS_SSN_CHECK_8197F BIT(4)
+#define BIT_MACID_MATCH_RTS_8197F BIT(3)
+#define BIT_EN_BCN_TRXRPT_V1_8197F BIT(2)
+#define BIT_R_EN_FTMRPT_8197F BIT(1)
+#define BIT_R_BMC_NAV_PROTECT_8197F BIT(0)
+
+/* 2 REG_NOT_VALID_8197F */
+#define BIT__R_EN_RTY_BK_COD_8197F BIT(2)
+
+#define BIT_SHIFT__R_DATA_FALLBACK_SEL_8197F 0
+#define BIT_MASK__R_DATA_FALLBACK_SEL_8197F 0x3
+#define BIT__R_DATA_FALLBACK_SEL_8197F(x) \
+ (((x) & BIT_MASK__R_DATA_FALLBACK_SEL_8197F) \
+ << BIT_SHIFT__R_DATA_FALLBACK_SEL_8197F)
+#define BITS__R_DATA_FALLBACK_SEL_8197F \
+ (BIT_MASK__R_DATA_FALLBACK_SEL_8197F \
+ << BIT_SHIFT__R_DATA_FALLBACK_SEL_8197F)
+#define BIT_CLEAR__R_DATA_FALLBACK_SEL_8197F(x) \
+ ((x) & (~BITS__R_DATA_FALLBACK_SEL_8197F))
+#define BIT_GET__R_DATA_FALLBACK_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL_8197F) & \
+ BIT_MASK__R_DATA_FALLBACK_SEL_8197F)
+#define BIT_SET__R_DATA_FALLBACK_SEL_8197F(x, v) \
+ (BIT_CLEAR__R_DATA_FALLBACK_SEL_8197F(x) | \
+ BIT__R_DATA_FALLBACK_SEL_8197F(v))
+
+/* 2 REG_BCNQ_BDNY_V1_8197F */
+
+#define BIT_SHIFT_BCNQ_PGBNDY_V1_8197F 0
+#define BIT_MASK_BCNQ_PGBNDY_V1_8197F 0xfff
+#define BIT_BCNQ_PGBNDY_V1_8197F(x) \
+ (((x) & BIT_MASK_BCNQ_PGBNDY_V1_8197F) \
+ << BIT_SHIFT_BCNQ_PGBNDY_V1_8197F)
+#define BITS_BCNQ_PGBNDY_V1_8197F \
+ (BIT_MASK_BCNQ_PGBNDY_V1_8197F << BIT_SHIFT_BCNQ_PGBNDY_V1_8197F)
+#define BIT_CLEAR_BCNQ_PGBNDY_V1_8197F(x) ((x) & (~BITS_BCNQ_PGBNDY_V1_8197F))
+#define BIT_GET_BCNQ_PGBNDY_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1_8197F) & \
+ BIT_MASK_BCNQ_PGBNDY_V1_8197F)
+#define BIT_SET_BCNQ_PGBNDY_V1_8197F(x, v) \
+ (BIT_CLEAR_BCNQ_PGBNDY_V1_8197F(x) | BIT_BCNQ_PGBNDY_V1_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_LIFETIME_EN_8197F */
+#define BIT_BT_INT_CPU_8197F BIT(7)
+#define BIT_BT_INT_PTA_8197F BIT(6)
+#define BIT_EN_CTRL_RTYBIT_8197F BIT(4)
+#define BIT_LIFETIME_BK_EN_8197F BIT(3)
+#define BIT_LIFETIME_BE_EN_8197F BIT(2)
+#define BIT_LIFETIME_VI_EN_8197F BIT(1)
+#define BIT_LIFETIME_VO_EN_8197F BIT(0)
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_SPEC_SIFS_8197F */
+
+#define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8197F 8
+#define BIT_MASK_SPEC_SIFS_OFDM_PTCL_8197F 0xff
+#define BIT_SPEC_SIFS_OFDM_PTCL_8197F(x) \
+ (((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8197F) \
+ << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8197F)
+#define BITS_SPEC_SIFS_OFDM_PTCL_8197F \
+ (BIT_MASK_SPEC_SIFS_OFDM_PTCL_8197F \
+ << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8197F)
+#define BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8197F(x) \
+ ((x) & (~BITS_SPEC_SIFS_OFDM_PTCL_8197F))
+#define BIT_GET_SPEC_SIFS_OFDM_PTCL_8197F(x) \
+ (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8197F) & \
+ BIT_MASK_SPEC_SIFS_OFDM_PTCL_8197F)
+#define BIT_SET_SPEC_SIFS_OFDM_PTCL_8197F(x, v) \
+ (BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8197F(x) | \
+ BIT_SPEC_SIFS_OFDM_PTCL_8197F(v))
+
+#define BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8197F 0
+#define BIT_MASK_SPEC_SIFS_CCK_PTCL_8197F 0xff
+#define BIT_SPEC_SIFS_CCK_PTCL_8197F(x) \
+ (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8197F) \
+ << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8197F)
+#define BITS_SPEC_SIFS_CCK_PTCL_8197F \
+ (BIT_MASK_SPEC_SIFS_CCK_PTCL_8197F \
+ << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8197F)
+#define BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8197F(x) \
+ ((x) & (~BITS_SPEC_SIFS_CCK_PTCL_8197F))
+#define BIT_GET_SPEC_SIFS_CCK_PTCL_8197F(x) \
+ (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8197F) & \
+ BIT_MASK_SPEC_SIFS_CCK_PTCL_8197F)
+#define BIT_SET_SPEC_SIFS_CCK_PTCL_8197F(x, v) \
+ (BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8197F(x) | \
+ BIT_SPEC_SIFS_CCK_PTCL_8197F(v))
+
+/* 2 REG_RETRY_LIMIT_8197F */
+
+#define BIT_SHIFT_SRL_8197F 8
+#define BIT_MASK_SRL_8197F 0x3f
+#define BIT_SRL_8197F(x) (((x) & BIT_MASK_SRL_8197F) << BIT_SHIFT_SRL_8197F)
+#define BITS_SRL_8197F (BIT_MASK_SRL_8197F << BIT_SHIFT_SRL_8197F)
+#define BIT_CLEAR_SRL_8197F(x) ((x) & (~BITS_SRL_8197F))
+#define BIT_GET_SRL_8197F(x) (((x) >> BIT_SHIFT_SRL_8197F) & BIT_MASK_SRL_8197F)
+#define BIT_SET_SRL_8197F(x, v) (BIT_CLEAR_SRL_8197F(x) | BIT_SRL_8197F(v))
+
+#define BIT_SHIFT_LRL_8197F 0
+#define BIT_MASK_LRL_8197F 0x3f
+#define BIT_LRL_8197F(x) (((x) & BIT_MASK_LRL_8197F) << BIT_SHIFT_LRL_8197F)
+#define BITS_LRL_8197F (BIT_MASK_LRL_8197F << BIT_SHIFT_LRL_8197F)
+#define BIT_CLEAR_LRL_8197F(x) ((x) & (~BITS_LRL_8197F))
+#define BIT_GET_LRL_8197F(x) (((x) >> BIT_SHIFT_LRL_8197F) & BIT_MASK_LRL_8197F)
+#define BIT_SET_LRL_8197F(x, v) (BIT_CLEAR_LRL_8197F(x) | BIT_LRL_8197F(v))
+
+/* 2 REG_TXBF_CTRL_8197F */
+#define BIT_R_ENABLE_NDPA_8197F BIT(31)
+#define BIT_USE_NDPA_PARAMETER_8197F BIT(30)
+#define BIT_R_PROP_TXBF_8197F BIT(29)
+#define BIT_R_EN_NDPA_INT_8197F BIT(28)
+#define BIT_R_TXBF1_80M_8197F BIT(27)
+#define BIT_R_TXBF1_40M_8197F BIT(26)
+#define BIT_R_TXBF1_20M_8197F BIT(25)
+
+#define BIT_SHIFT_R_TXBF1_AID_8197F 16
+#define BIT_MASK_R_TXBF1_AID_8197F 0x1ff
+#define BIT_R_TXBF1_AID_8197F(x) \
+ (((x) & BIT_MASK_R_TXBF1_AID_8197F) << BIT_SHIFT_R_TXBF1_AID_8197F)
+#define BITS_R_TXBF1_AID_8197F \
+ (BIT_MASK_R_TXBF1_AID_8197F << BIT_SHIFT_R_TXBF1_AID_8197F)
+#define BIT_CLEAR_R_TXBF1_AID_8197F(x) ((x) & (~BITS_R_TXBF1_AID_8197F))
+#define BIT_GET_R_TXBF1_AID_8197F(x) \
+ (((x) >> BIT_SHIFT_R_TXBF1_AID_8197F) & BIT_MASK_R_TXBF1_AID_8197F)
+#define BIT_SET_R_TXBF1_AID_8197F(x, v) \
+ (BIT_CLEAR_R_TXBF1_AID_8197F(x) | BIT_R_TXBF1_AID_8197F(v))
+
+#define BIT_DIS_NDP_BFEN_8197F BIT(15)
+#define BIT_R_TXBCN_NOBLOCK_NDP_8197F BIT(14)
+#define BIT_R_TXBF0_80M_8197F BIT(11)
+#define BIT_R_TXBF0_40M_8197F BIT(10)
+#define BIT_R_TXBF0_20M_8197F BIT(9)
+
+#define BIT_SHIFT_R_TXBF0_AID_8197F 0
+#define BIT_MASK_R_TXBF0_AID_8197F 0x1ff
+#define BIT_R_TXBF0_AID_8197F(x) \
+ (((x) & BIT_MASK_R_TXBF0_AID_8197F) << BIT_SHIFT_R_TXBF0_AID_8197F)
+#define BITS_R_TXBF0_AID_8197F \
+ (BIT_MASK_R_TXBF0_AID_8197F << BIT_SHIFT_R_TXBF0_AID_8197F)
+#define BIT_CLEAR_R_TXBF0_AID_8197F(x) ((x) & (~BITS_R_TXBF0_AID_8197F))
+#define BIT_GET_R_TXBF0_AID_8197F(x) \
+ (((x) >> BIT_SHIFT_R_TXBF0_AID_8197F) & BIT_MASK_R_TXBF0_AID_8197F)
+#define BIT_SET_R_TXBF0_AID_8197F(x, v) \
+ (BIT_CLEAR_R_TXBF0_AID_8197F(x) | BIT_R_TXBF0_AID_8197F(v))
+
+/* 2 REG_DARFRC_8197F */
+
+#define BIT_SHIFT_DARF_RC8_V2_8197F (56 & CPU_OPT_WIDTH)
+#define BIT_MASK_DARF_RC8_V2_8197F 0x3f
+#define BIT_DARF_RC8_V2_8197F(x) \
+ (((x) & BIT_MASK_DARF_RC8_V2_8197F) << BIT_SHIFT_DARF_RC8_V2_8197F)
+#define BITS_DARF_RC8_V2_8197F \
+ (BIT_MASK_DARF_RC8_V2_8197F << BIT_SHIFT_DARF_RC8_V2_8197F)
+#define BIT_CLEAR_DARF_RC8_V2_8197F(x) ((x) & (~BITS_DARF_RC8_V2_8197F))
+#define BIT_GET_DARF_RC8_V2_8197F(x) \
+ (((x) >> BIT_SHIFT_DARF_RC8_V2_8197F) & BIT_MASK_DARF_RC8_V2_8197F)
+#define BIT_SET_DARF_RC8_V2_8197F(x, v) \
+ (BIT_CLEAR_DARF_RC8_V2_8197F(x) | BIT_DARF_RC8_V2_8197F(v))
+
+#define BIT_SHIFT_DARF_RC7_V2_8197F (48 & CPU_OPT_WIDTH)
+#define BIT_MASK_DARF_RC7_V2_8197F 0x3f
+#define BIT_DARF_RC7_V2_8197F(x) \
+ (((x) & BIT_MASK_DARF_RC7_V2_8197F) << BIT_SHIFT_DARF_RC7_V2_8197F)
+#define BITS_DARF_RC7_V2_8197F \
+ (BIT_MASK_DARF_RC7_V2_8197F << BIT_SHIFT_DARF_RC7_V2_8197F)
+#define BIT_CLEAR_DARF_RC7_V2_8197F(x) ((x) & (~BITS_DARF_RC7_V2_8197F))
+#define BIT_GET_DARF_RC7_V2_8197F(x) \
+ (((x) >> BIT_SHIFT_DARF_RC7_V2_8197F) & BIT_MASK_DARF_RC7_V2_8197F)
+#define BIT_SET_DARF_RC7_V2_8197F(x, v) \
+ (BIT_CLEAR_DARF_RC7_V2_8197F(x) | BIT_DARF_RC7_V2_8197F(v))
+
+#define BIT_SHIFT_DARF_RC6_V2_8197F (40 & CPU_OPT_WIDTH)
+#define BIT_MASK_DARF_RC6_V2_8197F 0x3f
+#define BIT_DARF_RC6_V2_8197F(x) \
+ (((x) & BIT_MASK_DARF_RC6_V2_8197F) << BIT_SHIFT_DARF_RC6_V2_8197F)
+#define BITS_DARF_RC6_V2_8197F \
+ (BIT_MASK_DARF_RC6_V2_8197F << BIT_SHIFT_DARF_RC6_V2_8197F)
+#define BIT_CLEAR_DARF_RC6_V2_8197F(x) ((x) & (~BITS_DARF_RC6_V2_8197F))
+#define BIT_GET_DARF_RC6_V2_8197F(x) \
+ (((x) >> BIT_SHIFT_DARF_RC6_V2_8197F) & BIT_MASK_DARF_RC6_V2_8197F)
+#define BIT_SET_DARF_RC6_V2_8197F(x, v) \
+ (BIT_CLEAR_DARF_RC6_V2_8197F(x) | BIT_DARF_RC6_V2_8197F(v))
+
+#define BIT_SHIFT_DARF_RC5_V2_8197F (32 & CPU_OPT_WIDTH)
+#define BIT_MASK_DARF_RC5_V2_8197F 0x3f
+#define BIT_DARF_RC5_V2_8197F(x) \
+ (((x) & BIT_MASK_DARF_RC5_V2_8197F) << BIT_SHIFT_DARF_RC5_V2_8197F)
+#define BITS_DARF_RC5_V2_8197F \
+ (BIT_MASK_DARF_RC5_V2_8197F << BIT_SHIFT_DARF_RC5_V2_8197F)
+#define BIT_CLEAR_DARF_RC5_V2_8197F(x) ((x) & (~BITS_DARF_RC5_V2_8197F))
+#define BIT_GET_DARF_RC5_V2_8197F(x) \
+ (((x) >> BIT_SHIFT_DARF_RC5_V2_8197F) & BIT_MASK_DARF_RC5_V2_8197F)
+#define BIT_SET_DARF_RC5_V2_8197F(x, v) \
+ (BIT_CLEAR_DARF_RC5_V2_8197F(x) | BIT_DARF_RC5_V2_8197F(v))
+
+#define BIT_SHIFT_DARF_RC4_V1_8197F 24
+#define BIT_MASK_DARF_RC4_V1_8197F 0x3f
+#define BIT_DARF_RC4_V1_8197F(x) \
+ (((x) & BIT_MASK_DARF_RC4_V1_8197F) << BIT_SHIFT_DARF_RC4_V1_8197F)
+#define BITS_DARF_RC4_V1_8197F \
+ (BIT_MASK_DARF_RC4_V1_8197F << BIT_SHIFT_DARF_RC4_V1_8197F)
+#define BIT_CLEAR_DARF_RC4_V1_8197F(x) ((x) & (~BITS_DARF_RC4_V1_8197F))
+#define BIT_GET_DARF_RC4_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_DARF_RC4_V1_8197F) & BIT_MASK_DARF_RC4_V1_8197F)
+#define BIT_SET_DARF_RC4_V1_8197F(x, v) \
+ (BIT_CLEAR_DARF_RC4_V1_8197F(x) | BIT_DARF_RC4_V1_8197F(v))
+
+#define BIT_SHIFT_DARF_RC3_V1_8197F 16
+#define BIT_MASK_DARF_RC3_V1_8197F 0x3f
+#define BIT_DARF_RC3_V1_8197F(x) \
+ (((x) & BIT_MASK_DARF_RC3_V1_8197F) << BIT_SHIFT_DARF_RC3_V1_8197F)
+#define BITS_DARF_RC3_V1_8197F \
+ (BIT_MASK_DARF_RC3_V1_8197F << BIT_SHIFT_DARF_RC3_V1_8197F)
+#define BIT_CLEAR_DARF_RC3_V1_8197F(x) ((x) & (~BITS_DARF_RC3_V1_8197F))
+#define BIT_GET_DARF_RC3_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_DARF_RC3_V1_8197F) & BIT_MASK_DARF_RC3_V1_8197F)
+#define BIT_SET_DARF_RC3_V1_8197F(x, v) \
+ (BIT_CLEAR_DARF_RC3_V1_8197F(x) | BIT_DARF_RC3_V1_8197F(v))
+
+#define BIT_SHIFT_DARF_RC2_V1_8197F 8
+#define BIT_MASK_DARF_RC2_V1_8197F 0x3f
+#define BIT_DARF_RC2_V1_8197F(x) \
+ (((x) & BIT_MASK_DARF_RC2_V1_8197F) << BIT_SHIFT_DARF_RC2_V1_8197F)
+#define BITS_DARF_RC2_V1_8197F \
+ (BIT_MASK_DARF_RC2_V1_8197F << BIT_SHIFT_DARF_RC2_V1_8197F)
+#define BIT_CLEAR_DARF_RC2_V1_8197F(x) ((x) & (~BITS_DARF_RC2_V1_8197F))
+#define BIT_GET_DARF_RC2_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_DARF_RC2_V1_8197F) & BIT_MASK_DARF_RC2_V1_8197F)
+#define BIT_SET_DARF_RC2_V1_8197F(x, v) \
+ (BIT_CLEAR_DARF_RC2_V1_8197F(x) | BIT_DARF_RC2_V1_8197F(v))
+
+#define BIT_SHIFT_DARF_RC1_V1_8197F 0
+#define BIT_MASK_DARF_RC1_V1_8197F 0x3f
+#define BIT_DARF_RC1_V1_8197F(x) \
+ (((x) & BIT_MASK_DARF_RC1_V1_8197F) << BIT_SHIFT_DARF_RC1_V1_8197F)
+#define BITS_DARF_RC1_V1_8197F \
+ (BIT_MASK_DARF_RC1_V1_8197F << BIT_SHIFT_DARF_RC1_V1_8197F)
+#define BIT_CLEAR_DARF_RC1_V1_8197F(x) ((x) & (~BITS_DARF_RC1_V1_8197F))
+#define BIT_GET_DARF_RC1_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_DARF_RC1_V1_8197F) & BIT_MASK_DARF_RC1_V1_8197F)
+#define BIT_SET_DARF_RC1_V1_8197F(x, v) \
+ (BIT_CLEAR_DARF_RC1_V1_8197F(x) | BIT_DARF_RC1_V1_8197F(v))
+
+/* 2 REG_RARFRC_8197F */
+
+#define BIT_SHIFT_RARF_RC8_8197F (56 & CPU_OPT_WIDTH)
+#define BIT_MASK_RARF_RC8_8197F 0x1f
+#define BIT_RARF_RC8_8197F(x) \
+ (((x) & BIT_MASK_RARF_RC8_8197F) << BIT_SHIFT_RARF_RC8_8197F)
+#define BITS_RARF_RC8_8197F \
+ (BIT_MASK_RARF_RC8_8197F << BIT_SHIFT_RARF_RC8_8197F)
+#define BIT_CLEAR_RARF_RC8_8197F(x) ((x) & (~BITS_RARF_RC8_8197F))
+#define BIT_GET_RARF_RC8_8197F(x) \
+ (((x) >> BIT_SHIFT_RARF_RC8_8197F) & BIT_MASK_RARF_RC8_8197F)
+#define BIT_SET_RARF_RC8_8197F(x, v) \
+ (BIT_CLEAR_RARF_RC8_8197F(x) | BIT_RARF_RC8_8197F(v))
+
+#define BIT_SHIFT_RARF_RC7_8197F (48 & CPU_OPT_WIDTH)
+#define BIT_MASK_RARF_RC7_8197F 0x1f
+#define BIT_RARF_RC7_8197F(x) \
+ (((x) & BIT_MASK_RARF_RC7_8197F) << BIT_SHIFT_RARF_RC7_8197F)
+#define BITS_RARF_RC7_8197F \
+ (BIT_MASK_RARF_RC7_8197F << BIT_SHIFT_RARF_RC7_8197F)
+#define BIT_CLEAR_RARF_RC7_8197F(x) ((x) & (~BITS_RARF_RC7_8197F))
+#define BIT_GET_RARF_RC7_8197F(x) \
+ (((x) >> BIT_SHIFT_RARF_RC7_8197F) & BIT_MASK_RARF_RC7_8197F)
+#define BIT_SET_RARF_RC7_8197F(x, v) \
+ (BIT_CLEAR_RARF_RC7_8197F(x) | BIT_RARF_RC7_8197F(v))
+
+#define BIT_SHIFT_RARF_RC6_8197F (40 & CPU_OPT_WIDTH)
+#define BIT_MASK_RARF_RC6_8197F 0x1f
+#define BIT_RARF_RC6_8197F(x) \
+ (((x) & BIT_MASK_RARF_RC6_8197F) << BIT_SHIFT_RARF_RC6_8197F)
+#define BITS_RARF_RC6_8197F \
+ (BIT_MASK_RARF_RC6_8197F << BIT_SHIFT_RARF_RC6_8197F)
+#define BIT_CLEAR_RARF_RC6_8197F(x) ((x) & (~BITS_RARF_RC6_8197F))
+#define BIT_GET_RARF_RC6_8197F(x) \
+ (((x) >> BIT_SHIFT_RARF_RC6_8197F) & BIT_MASK_RARF_RC6_8197F)
+#define BIT_SET_RARF_RC6_8197F(x, v) \
+ (BIT_CLEAR_RARF_RC6_8197F(x) | BIT_RARF_RC6_8197F(v))
+
+#define BIT_SHIFT_RARF_RC5_8197F (32 & CPU_OPT_WIDTH)
+#define BIT_MASK_RARF_RC5_8197F 0x1f
+#define BIT_RARF_RC5_8197F(x) \
+ (((x) & BIT_MASK_RARF_RC5_8197F) << BIT_SHIFT_RARF_RC5_8197F)
+#define BITS_RARF_RC5_8197F \
+ (BIT_MASK_RARF_RC5_8197F << BIT_SHIFT_RARF_RC5_8197F)
+#define BIT_CLEAR_RARF_RC5_8197F(x) ((x) & (~BITS_RARF_RC5_8197F))
+#define BIT_GET_RARF_RC5_8197F(x) \
+ (((x) >> BIT_SHIFT_RARF_RC5_8197F) & BIT_MASK_RARF_RC5_8197F)
+#define BIT_SET_RARF_RC5_8197F(x, v) \
+ (BIT_CLEAR_RARF_RC5_8197F(x) | BIT_RARF_RC5_8197F(v))
+
+#define BIT_SHIFT_RARF_RC4_8197F 24
+#define BIT_MASK_RARF_RC4_8197F 0x1f
+#define BIT_RARF_RC4_8197F(x) \
+ (((x) & BIT_MASK_RARF_RC4_8197F) << BIT_SHIFT_RARF_RC4_8197F)
+#define BITS_RARF_RC4_8197F \
+ (BIT_MASK_RARF_RC4_8197F << BIT_SHIFT_RARF_RC4_8197F)
+#define BIT_CLEAR_RARF_RC4_8197F(x) ((x) & (~BITS_RARF_RC4_8197F))
+#define BIT_GET_RARF_RC4_8197F(x) \
+ (((x) >> BIT_SHIFT_RARF_RC4_8197F) & BIT_MASK_RARF_RC4_8197F)
+#define BIT_SET_RARF_RC4_8197F(x, v) \
+ (BIT_CLEAR_RARF_RC4_8197F(x) | BIT_RARF_RC4_8197F(v))
+
+#define BIT_SHIFT_RARF_RC3_8197F 16
+#define BIT_MASK_RARF_RC3_8197F 0x1f
+#define BIT_RARF_RC3_8197F(x) \
+ (((x) & BIT_MASK_RARF_RC3_8197F) << BIT_SHIFT_RARF_RC3_8197F)
+#define BITS_RARF_RC3_8197F \
+ (BIT_MASK_RARF_RC3_8197F << BIT_SHIFT_RARF_RC3_8197F)
+#define BIT_CLEAR_RARF_RC3_8197F(x) ((x) & (~BITS_RARF_RC3_8197F))
+#define BIT_GET_RARF_RC3_8197F(x) \
+ (((x) >> BIT_SHIFT_RARF_RC3_8197F) & BIT_MASK_RARF_RC3_8197F)
+#define BIT_SET_RARF_RC3_8197F(x, v) \
+ (BIT_CLEAR_RARF_RC3_8197F(x) | BIT_RARF_RC3_8197F(v))
+
+#define BIT_SHIFT_RARF_RC2_8197F 8
+#define BIT_MASK_RARF_RC2_8197F 0x1f
+#define BIT_RARF_RC2_8197F(x) \
+ (((x) & BIT_MASK_RARF_RC2_8197F) << BIT_SHIFT_RARF_RC2_8197F)
+#define BITS_RARF_RC2_8197F \
+ (BIT_MASK_RARF_RC2_8197F << BIT_SHIFT_RARF_RC2_8197F)
+#define BIT_CLEAR_RARF_RC2_8197F(x) ((x) & (~BITS_RARF_RC2_8197F))
+#define BIT_GET_RARF_RC2_8197F(x) \
+ (((x) >> BIT_SHIFT_RARF_RC2_8197F) & BIT_MASK_RARF_RC2_8197F)
+#define BIT_SET_RARF_RC2_8197F(x, v) \
+ (BIT_CLEAR_RARF_RC2_8197F(x) | BIT_RARF_RC2_8197F(v))
+
+#define BIT_SHIFT_RARF_RC1_8197F 0
+#define BIT_MASK_RARF_RC1_8197F 0x1f
+#define BIT_RARF_RC1_8197F(x) \
+ (((x) & BIT_MASK_RARF_RC1_8197F) << BIT_SHIFT_RARF_RC1_8197F)
+#define BITS_RARF_RC1_8197F \
+ (BIT_MASK_RARF_RC1_8197F << BIT_SHIFT_RARF_RC1_8197F)
+#define BIT_CLEAR_RARF_RC1_8197F(x) ((x) & (~BITS_RARF_RC1_8197F))
+#define BIT_GET_RARF_RC1_8197F(x) \
+ (((x) >> BIT_SHIFT_RARF_RC1_8197F) & BIT_MASK_RARF_RC1_8197F)
+#define BIT_SET_RARF_RC1_8197F(x, v) \
+ (BIT_CLEAR_RARF_RC1_8197F(x) | BIT_RARF_RC1_8197F(v))
+
+/* 2 REG_RRSR_8197F */
+#define BIT_EN_VHTBW_FALL_8197F BIT(31)
+#define BIT_EN_HTBW_FALL_8197F BIT(30)
+
+#define BIT_SHIFT_RRSR_RSC_8197F 21
+#define BIT_MASK_RRSR_RSC_8197F 0x3
+#define BIT_RRSR_RSC_8197F(x) \
+ (((x) & BIT_MASK_RRSR_RSC_8197F) << BIT_SHIFT_RRSR_RSC_8197F)
+#define BITS_RRSR_RSC_8197F \
+ (BIT_MASK_RRSR_RSC_8197F << BIT_SHIFT_RRSR_RSC_8197F)
+#define BIT_CLEAR_RRSR_RSC_8197F(x) ((x) & (~BITS_RRSR_RSC_8197F))
+#define BIT_GET_RRSR_RSC_8197F(x) \
+ (((x) >> BIT_SHIFT_RRSR_RSC_8197F) & BIT_MASK_RRSR_RSC_8197F)
+#define BIT_SET_RRSR_RSC_8197F(x, v) \
+ (BIT_CLEAR_RRSR_RSC_8197F(x) | BIT_RRSR_RSC_8197F(v))
+
+#define BIT_RRSR_BW_8197F BIT(20)
+
+#define BIT_SHIFT_RRSC_BITMAP_8197F 0
+#define BIT_MASK_RRSC_BITMAP_8197F 0xfffff
+#define BIT_RRSC_BITMAP_8197F(x) \
+ (((x) & BIT_MASK_RRSC_BITMAP_8197F) << BIT_SHIFT_RRSC_BITMAP_8197F)
+#define BITS_RRSC_BITMAP_8197F \
+ (BIT_MASK_RRSC_BITMAP_8197F << BIT_SHIFT_RRSC_BITMAP_8197F)
+#define BIT_CLEAR_RRSC_BITMAP_8197F(x) ((x) & (~BITS_RRSC_BITMAP_8197F))
+#define BIT_GET_RRSC_BITMAP_8197F(x) \
+ (((x) >> BIT_SHIFT_RRSC_BITMAP_8197F) & BIT_MASK_RRSC_BITMAP_8197F)
+#define BIT_SET_RRSC_BITMAP_8197F(x, v) \
+ (BIT_CLEAR_RRSC_BITMAP_8197F(x) | BIT_RRSC_BITMAP_8197F(v))
+
+/* 2 REG_ARFR0_8197F */
+
+#define BIT_SHIFT_ARFR0_V1_8197F 0
+#define BIT_MASK_ARFR0_V1_8197F 0xffffffffffffffffL
+#define BIT_ARFR0_V1_8197F(x) \
+ (((x) & BIT_MASK_ARFR0_V1_8197F) << BIT_SHIFT_ARFR0_V1_8197F)
+#define BITS_ARFR0_V1_8197F \
+ (BIT_MASK_ARFR0_V1_8197F << BIT_SHIFT_ARFR0_V1_8197F)
+#define BIT_CLEAR_ARFR0_V1_8197F(x) ((x) & (~BITS_ARFR0_V1_8197F))
+#define BIT_GET_ARFR0_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_ARFR0_V1_8197F) & BIT_MASK_ARFR0_V1_8197F)
+#define BIT_SET_ARFR0_V1_8197F(x, v) \
+ (BIT_CLEAR_ARFR0_V1_8197F(x) | BIT_ARFR0_V1_8197F(v))
+
+/* 2 REG_ARFR1_V1_8197F */
+
+#define BIT_SHIFT_ARFR1_V1_8197F 0
+#define BIT_MASK_ARFR1_V1_8197F 0xffffffffffffffffL
+#define BIT_ARFR1_V1_8197F(x) \
+ (((x) & BIT_MASK_ARFR1_V1_8197F) << BIT_SHIFT_ARFR1_V1_8197F)
+#define BITS_ARFR1_V1_8197F \
+ (BIT_MASK_ARFR1_V1_8197F << BIT_SHIFT_ARFR1_V1_8197F)
+#define BIT_CLEAR_ARFR1_V1_8197F(x) ((x) & (~BITS_ARFR1_V1_8197F))
+#define BIT_GET_ARFR1_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_ARFR1_V1_8197F) & BIT_MASK_ARFR1_V1_8197F)
+#define BIT_SET_ARFR1_V1_8197F(x, v) \
+ (BIT_CLEAR_ARFR1_V1_8197F(x) | BIT_ARFR1_V1_8197F(v))
+
+/* 2 REG_CCK_CHECK_8197F */
+#define BIT_CHECK_CCK_EN_8197F BIT(7)
+#define BIT_EN_BCN_PKT_REL_8197F BIT(6)
+#define BIT_BCN_PORT_SEL_8197F BIT(5)
+#define BIT_MOREDATA_BYPASS_8197F BIT(4)
+#define BIT_EN_CLR_CMD_REL_BCN_PKT_8197F BIT(3)
+#define BIT_R_EN_SET_MOREDATA_8197F BIT(2)
+#define BIT__R_DIS_CLEAR_MACID_RELEASE_8197F BIT(1)
+#define BIT__R_MACID_RELEASE_EN_8197F BIT(0)
+
+/* 2 REG_AMPDU_MAX_TIME_V1_8197F */
+
+#define BIT_SHIFT_AMPDU_MAX_TIME_8197F 0
+#define BIT_MASK_AMPDU_MAX_TIME_8197F 0xff
+#define BIT_AMPDU_MAX_TIME_8197F(x) \
+ (((x) & BIT_MASK_AMPDU_MAX_TIME_8197F) \
+ << BIT_SHIFT_AMPDU_MAX_TIME_8197F)
+#define BITS_AMPDU_MAX_TIME_8197F \
+ (BIT_MASK_AMPDU_MAX_TIME_8197F << BIT_SHIFT_AMPDU_MAX_TIME_8197F)
+#define BIT_CLEAR_AMPDU_MAX_TIME_8197F(x) ((x) & (~BITS_AMPDU_MAX_TIME_8197F))
+#define BIT_GET_AMPDU_MAX_TIME_8197F(x) \
+ (((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8197F) & \
+ BIT_MASK_AMPDU_MAX_TIME_8197F)
+#define BIT_SET_AMPDU_MAX_TIME_8197F(x, v) \
+ (BIT_CLEAR_AMPDU_MAX_TIME_8197F(x) | BIT_AMPDU_MAX_TIME_8197F(v))
+
+/* 2 REG_BCNQ1_BDNY_V1_8197F */
+
+#define BIT_SHIFT_BCNQ1_PGBNDY_V1_8197F 0
+#define BIT_MASK_BCNQ1_PGBNDY_V1_8197F 0xfff
+#define BIT_BCNQ1_PGBNDY_V1_8197F(x) \
+ (((x) & BIT_MASK_BCNQ1_PGBNDY_V1_8197F) \
+ << BIT_SHIFT_BCNQ1_PGBNDY_V1_8197F)
+#define BITS_BCNQ1_PGBNDY_V1_8197F \
+ (BIT_MASK_BCNQ1_PGBNDY_V1_8197F << BIT_SHIFT_BCNQ1_PGBNDY_V1_8197F)
+#define BIT_CLEAR_BCNQ1_PGBNDY_V1_8197F(x) ((x) & (~BITS_BCNQ1_PGBNDY_V1_8197F))
+#define BIT_GET_BCNQ1_PGBNDY_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1_8197F) & \
+ BIT_MASK_BCNQ1_PGBNDY_V1_8197F)
+#define BIT_SET_BCNQ1_PGBNDY_V1_8197F(x, v) \
+ (BIT_CLEAR_BCNQ1_PGBNDY_V1_8197F(x) | BIT_BCNQ1_PGBNDY_V1_8197F(v))
+
+/* 2 REG_AMPDU_MAX_LENGTH_8197F */
+
+#define BIT_SHIFT_AMPDU_MAX_LENGTH_8197F 0
+#define BIT_MASK_AMPDU_MAX_LENGTH_8197F 0xffffffffL
+#define BIT_AMPDU_MAX_LENGTH_8197F(x) \
+ (((x) & BIT_MASK_AMPDU_MAX_LENGTH_8197F) \
+ << BIT_SHIFT_AMPDU_MAX_LENGTH_8197F)
+#define BITS_AMPDU_MAX_LENGTH_8197F \
+ (BIT_MASK_AMPDU_MAX_LENGTH_8197F << BIT_SHIFT_AMPDU_MAX_LENGTH_8197F)
+#define BIT_CLEAR_AMPDU_MAX_LENGTH_8197F(x) \
+ ((x) & (~BITS_AMPDU_MAX_LENGTH_8197F))
+#define BIT_GET_AMPDU_MAX_LENGTH_8197F(x) \
+ (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_8197F) & \
+ BIT_MASK_AMPDU_MAX_LENGTH_8197F)
+#define BIT_SET_AMPDU_MAX_LENGTH_8197F(x, v) \
+ (BIT_CLEAR_AMPDU_MAX_LENGTH_8197F(x) | BIT_AMPDU_MAX_LENGTH_8197F(v))
+
+/* 2 REG_ACQ_STOP_8197F */
+#define BIT_AC7Q_STOP_8197F BIT(7)
+#define BIT_AC6Q_STOP_8197F BIT(6)
+#define BIT_AC5Q_STOP_8197F BIT(5)
+#define BIT_AC4Q_STOP_8197F BIT(4)
+#define BIT_AC3Q_STOP_8197F BIT(3)
+#define BIT_AC2Q_STOP_8197F BIT(2)
+#define BIT_AC1Q_STOP_8197F BIT(1)
+#define BIT_AC0Q_STOP_8197F BIT(0)
+
+/* 2 REG_NDPA_RATE_8197F */
+
+#define BIT_SHIFT_R_NDPA_RATE_V1_8197F 0
+#define BIT_MASK_R_NDPA_RATE_V1_8197F 0xff
+#define BIT_R_NDPA_RATE_V1_8197F(x) \
+ (((x) & BIT_MASK_R_NDPA_RATE_V1_8197F) \
+ << BIT_SHIFT_R_NDPA_RATE_V1_8197F)
+#define BITS_R_NDPA_RATE_V1_8197F \
+ (BIT_MASK_R_NDPA_RATE_V1_8197F << BIT_SHIFT_R_NDPA_RATE_V1_8197F)
+#define BIT_CLEAR_R_NDPA_RATE_V1_8197F(x) ((x) & (~BITS_R_NDPA_RATE_V1_8197F))
+#define BIT_GET_R_NDPA_RATE_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8197F) & \
+ BIT_MASK_R_NDPA_RATE_V1_8197F)
+#define BIT_SET_R_NDPA_RATE_V1_8197F(x, v) \
+ (BIT_CLEAR_R_NDPA_RATE_V1_8197F(x) | BIT_R_NDPA_RATE_V1_8197F(v))
+
+/* 2 REG_TX_HANG_CTRL_8197F */
+#define BIT_R_EN_GNT_BT_AWAKE_8197F BIT(3)
+#define BIT_EN_EOF_V1_8197F BIT(2)
+#define BIT_DIS_OQT_BLOCK_8197F BIT(1)
+#define BIT_SEARCH_QUEUE_EN_8197F BIT(0)
+
+/* 2 REG_NDPA_OPT_CTRL_8197F */
+#define BIT_R_DIS_MACID_RELEASE_RTY_8197F BIT(5)
+
+#define BIT_SHIFT_BW_SIGTA_8197F 3
+#define BIT_MASK_BW_SIGTA_8197F 0x3
+#define BIT_BW_SIGTA_8197F(x) \
+ (((x) & BIT_MASK_BW_SIGTA_8197F) << BIT_SHIFT_BW_SIGTA_8197F)
+#define BITS_BW_SIGTA_8197F \
+ (BIT_MASK_BW_SIGTA_8197F << BIT_SHIFT_BW_SIGTA_8197F)
+#define BIT_CLEAR_BW_SIGTA_8197F(x) ((x) & (~BITS_BW_SIGTA_8197F))
+#define BIT_GET_BW_SIGTA_8197F(x) \
+ (((x) >> BIT_SHIFT_BW_SIGTA_8197F) & BIT_MASK_BW_SIGTA_8197F)
+#define BIT_SET_BW_SIGTA_8197F(x, v) \
+ (BIT_CLEAR_BW_SIGTA_8197F(x) | BIT_BW_SIGTA_8197F(v))
+
+#define BIT_EN_BAR_SIGTA_8197F BIT(2)
+
+#define BIT_SHIFT_R_NDPA_BW_8197F 0
+#define BIT_MASK_R_NDPA_BW_8197F 0x3
+#define BIT_R_NDPA_BW_8197F(x) \
+ (((x) & BIT_MASK_R_NDPA_BW_8197F) << BIT_SHIFT_R_NDPA_BW_8197F)
+#define BITS_R_NDPA_BW_8197F \
+ (BIT_MASK_R_NDPA_BW_8197F << BIT_SHIFT_R_NDPA_BW_8197F)
+#define BIT_CLEAR_R_NDPA_BW_8197F(x) ((x) & (~BITS_R_NDPA_BW_8197F))
+#define BIT_GET_R_NDPA_BW_8197F(x) \
+ (((x) >> BIT_SHIFT_R_NDPA_BW_8197F) & BIT_MASK_R_NDPA_BW_8197F)
+#define BIT_SET_R_NDPA_BW_8197F(x, v) \
+ (BIT_CLEAR_R_NDPA_BW_8197F(x) | BIT_R_NDPA_BW_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_RD_RESP_PKT_TH_8197F */
+
+#define BIT_SHIFT_RD_RESP_PKT_TH_V1_8197F 0
+#define BIT_MASK_RD_RESP_PKT_TH_V1_8197F 0x3f
+#define BIT_RD_RESP_PKT_TH_V1_8197F(x) \
+ (((x) & BIT_MASK_RD_RESP_PKT_TH_V1_8197F) \
+ << BIT_SHIFT_RD_RESP_PKT_TH_V1_8197F)
+#define BITS_RD_RESP_PKT_TH_V1_8197F \
+ (BIT_MASK_RD_RESP_PKT_TH_V1_8197F << BIT_SHIFT_RD_RESP_PKT_TH_V1_8197F)
+#define BIT_CLEAR_RD_RESP_PKT_TH_V1_8197F(x) \
+ ((x) & (~BITS_RD_RESP_PKT_TH_V1_8197F))
+#define BIT_GET_RD_RESP_PKT_TH_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8197F) & \
+ BIT_MASK_RD_RESP_PKT_TH_V1_8197F)
+#define BIT_SET_RD_RESP_PKT_TH_V1_8197F(x, v) \
+ (BIT_CLEAR_RD_RESP_PKT_TH_V1_8197F(x) | BIT_RD_RESP_PKT_TH_V1_8197F(v))
+
+/* 2 REG_CMDQ_INFO_8197F */
+
+#define BIT_SHIFT_PKT_NUM_8197F 23
+#define BIT_MASK_PKT_NUM_8197F 0x1ff
+#define BIT_PKT_NUM_8197F(x) \
+ (((x) & BIT_MASK_PKT_NUM_8197F) << BIT_SHIFT_PKT_NUM_8197F)
+#define BITS_PKT_NUM_8197F (BIT_MASK_PKT_NUM_8197F << BIT_SHIFT_PKT_NUM_8197F)
+#define BIT_CLEAR_PKT_NUM_8197F(x) ((x) & (~BITS_PKT_NUM_8197F))
+#define BIT_GET_PKT_NUM_8197F(x) \
+ (((x) >> BIT_SHIFT_PKT_NUM_8197F) & BIT_MASK_PKT_NUM_8197F)
+#define BIT_SET_PKT_NUM_8197F(x, v) \
+ (BIT_CLEAR_PKT_NUM_8197F(x) | BIT_PKT_NUM_8197F(v))
+
+#define BIT_TIDEMPTY_CMDQ_V1_8197F BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_CMDQ_V2_8197F 11
+#define BIT_MASK_TAIL_PKT_CMDQ_V2_8197F 0x7ff
+#define BIT_TAIL_PKT_CMDQ_V2_8197F(x) \
+ (((x) & BIT_MASK_TAIL_PKT_CMDQ_V2_8197F) \
+ << BIT_SHIFT_TAIL_PKT_CMDQ_V2_8197F)
+#define BITS_TAIL_PKT_CMDQ_V2_8197F \
+ (BIT_MASK_TAIL_PKT_CMDQ_V2_8197F << BIT_SHIFT_TAIL_PKT_CMDQ_V2_8197F)
+#define BIT_CLEAR_TAIL_PKT_CMDQ_V2_8197F(x) \
+ ((x) & (~BITS_TAIL_PKT_CMDQ_V2_8197F))
+#define BIT_GET_TAIL_PKT_CMDQ_V2_8197F(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_CMDQ_V2_8197F) & \
+ BIT_MASK_TAIL_PKT_CMDQ_V2_8197F)
+#define BIT_SET_TAIL_PKT_CMDQ_V2_8197F(x, v) \
+ (BIT_CLEAR_TAIL_PKT_CMDQ_V2_8197F(x) | BIT_TAIL_PKT_CMDQ_V2_8197F(v))
+
+#define BIT_SHIFT_HEAD_PKT_CMDQ_V1_8197F 0
+#define BIT_MASK_HEAD_PKT_CMDQ_V1_8197F 0x7ff
+#define BIT_HEAD_PKT_CMDQ_V1_8197F(x) \
+ (((x) & BIT_MASK_HEAD_PKT_CMDQ_V1_8197F) \
+ << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8197F)
+#define BITS_HEAD_PKT_CMDQ_V1_8197F \
+ (BIT_MASK_HEAD_PKT_CMDQ_V1_8197F << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8197F)
+#define BIT_CLEAR_HEAD_PKT_CMDQ_V1_8197F(x) \
+ ((x) & (~BITS_HEAD_PKT_CMDQ_V1_8197F))
+#define BIT_GET_HEAD_PKT_CMDQ_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1_8197F) & \
+ BIT_MASK_HEAD_PKT_CMDQ_V1_8197F)
+#define BIT_SET_HEAD_PKT_CMDQ_V1_8197F(x, v) \
+ (BIT_CLEAR_HEAD_PKT_CMDQ_V1_8197F(x) | BIT_HEAD_PKT_CMDQ_V1_8197F(v))
+
+/* 2 REG_Q4_INFO_8197F */
+
+#define BIT_SHIFT_QUEUEMACID_Q4_V1_8197F 25
+#define BIT_MASK_QUEUEMACID_Q4_V1_8197F 0x7f
+#define BIT_QUEUEMACID_Q4_V1_8197F(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q4_V1_8197F) \
+ << BIT_SHIFT_QUEUEMACID_Q4_V1_8197F)
+#define BITS_QUEUEMACID_Q4_V1_8197F \
+ (BIT_MASK_QUEUEMACID_Q4_V1_8197F << BIT_SHIFT_QUEUEMACID_Q4_V1_8197F)
+#define BIT_CLEAR_QUEUEMACID_Q4_V1_8197F(x) \
+ ((x) & (~BITS_QUEUEMACID_Q4_V1_8197F))
+#define BIT_GET_QUEUEMACID_Q4_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1_8197F) & \
+ BIT_MASK_QUEUEMACID_Q4_V1_8197F)
+#define BIT_SET_QUEUEMACID_Q4_V1_8197F(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q4_V1_8197F(x) | BIT_QUEUEMACID_Q4_V1_8197F(v))
+
+#define BIT_SHIFT_QUEUEAC_Q4_V1_8197F 23
+#define BIT_MASK_QUEUEAC_Q4_V1_8197F 0x3
+#define BIT_QUEUEAC_Q4_V1_8197F(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q4_V1_8197F) << BIT_SHIFT_QUEUEAC_Q4_V1_8197F)
+#define BITS_QUEUEAC_Q4_V1_8197F \
+ (BIT_MASK_QUEUEAC_Q4_V1_8197F << BIT_SHIFT_QUEUEAC_Q4_V1_8197F)
+#define BIT_CLEAR_QUEUEAC_Q4_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q4_V1_8197F))
+#define BIT_GET_QUEUEAC_Q4_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q4_V1_8197F) & BIT_MASK_QUEUEAC_Q4_V1_8197F)
+#define BIT_SET_QUEUEAC_Q4_V1_8197F(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q4_V1_8197F(x) | BIT_QUEUEAC_Q4_V1_8197F(v))
+
+#define BIT_TIDEMPTY_Q4_V1_8197F BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q4_V2_8197F 11
+#define BIT_MASK_TAIL_PKT_Q4_V2_8197F 0x7ff
+#define BIT_TAIL_PKT_Q4_V2_8197F(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q4_V2_8197F) \
+ << BIT_SHIFT_TAIL_PKT_Q4_V2_8197F)
+#define BITS_TAIL_PKT_Q4_V2_8197F \
+ (BIT_MASK_TAIL_PKT_Q4_V2_8197F << BIT_SHIFT_TAIL_PKT_Q4_V2_8197F)
+#define BIT_CLEAR_TAIL_PKT_Q4_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q4_V2_8197F))
+#define BIT_GET_TAIL_PKT_Q4_V2_8197F(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8197F) & \
+ BIT_MASK_TAIL_PKT_Q4_V2_8197F)
+#define BIT_SET_TAIL_PKT_Q4_V2_8197F(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q4_V2_8197F(x) | BIT_TAIL_PKT_Q4_V2_8197F(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q4_V1_8197F 0
+#define BIT_MASK_HEAD_PKT_Q4_V1_8197F 0x7ff
+#define BIT_HEAD_PKT_Q4_V1_8197F(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q4_V1_8197F) \
+ << BIT_SHIFT_HEAD_PKT_Q4_V1_8197F)
+#define BITS_HEAD_PKT_Q4_V1_8197F \
+ (BIT_MASK_HEAD_PKT_Q4_V1_8197F << BIT_SHIFT_HEAD_PKT_Q4_V1_8197F)
+#define BIT_CLEAR_HEAD_PKT_Q4_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q4_V1_8197F))
+#define BIT_GET_HEAD_PKT_Q4_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1_8197F) & \
+ BIT_MASK_HEAD_PKT_Q4_V1_8197F)
+#define BIT_SET_HEAD_PKT_Q4_V1_8197F(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q4_V1_8197F(x) | BIT_HEAD_PKT_Q4_V1_8197F(v))
+
+/* 2 REG_Q5_INFO_8197F */
+
+#define BIT_SHIFT_QUEUEMACID_Q5_V1_8197F 25
+#define BIT_MASK_QUEUEMACID_Q5_V1_8197F 0x7f
+#define BIT_QUEUEMACID_Q5_V1_8197F(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q5_V1_8197F) \
+ << BIT_SHIFT_QUEUEMACID_Q5_V1_8197F)
+#define BITS_QUEUEMACID_Q5_V1_8197F \
+ (BIT_MASK_QUEUEMACID_Q5_V1_8197F << BIT_SHIFT_QUEUEMACID_Q5_V1_8197F)
+#define BIT_CLEAR_QUEUEMACID_Q5_V1_8197F(x) \
+ ((x) & (~BITS_QUEUEMACID_Q5_V1_8197F))
+#define BIT_GET_QUEUEMACID_Q5_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1_8197F) & \
+ BIT_MASK_QUEUEMACID_Q5_V1_8197F)
+#define BIT_SET_QUEUEMACID_Q5_V1_8197F(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q5_V1_8197F(x) | BIT_QUEUEMACID_Q5_V1_8197F(v))
+
+#define BIT_SHIFT_QUEUEAC_Q5_V1_8197F 23
+#define BIT_MASK_QUEUEAC_Q5_V1_8197F 0x3
+#define BIT_QUEUEAC_Q5_V1_8197F(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q5_V1_8197F) << BIT_SHIFT_QUEUEAC_Q5_V1_8197F)
+#define BITS_QUEUEAC_Q5_V1_8197F \
+ (BIT_MASK_QUEUEAC_Q5_V1_8197F << BIT_SHIFT_QUEUEAC_Q5_V1_8197F)
+#define BIT_CLEAR_QUEUEAC_Q5_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q5_V1_8197F))
+#define BIT_GET_QUEUEAC_Q5_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q5_V1_8197F) & BIT_MASK_QUEUEAC_Q5_V1_8197F)
+#define BIT_SET_QUEUEAC_Q5_V1_8197F(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q5_V1_8197F(x) | BIT_QUEUEAC_Q5_V1_8197F(v))
+
+#define BIT_TIDEMPTY_Q5_V1_8197F BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q5_V2_8197F 11
+#define BIT_MASK_TAIL_PKT_Q5_V2_8197F 0x7ff
+#define BIT_TAIL_PKT_Q5_V2_8197F(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q5_V2_8197F) \
+ << BIT_SHIFT_TAIL_PKT_Q5_V2_8197F)
+#define BITS_TAIL_PKT_Q5_V2_8197F \
+ (BIT_MASK_TAIL_PKT_Q5_V2_8197F << BIT_SHIFT_TAIL_PKT_Q5_V2_8197F)
+#define BIT_CLEAR_TAIL_PKT_Q5_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q5_V2_8197F))
+#define BIT_GET_TAIL_PKT_Q5_V2_8197F(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2_8197F) & \
+ BIT_MASK_TAIL_PKT_Q5_V2_8197F)
+#define BIT_SET_TAIL_PKT_Q5_V2_8197F(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q5_V2_8197F(x) | BIT_TAIL_PKT_Q5_V2_8197F(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q5_V1_8197F 0
+#define BIT_MASK_HEAD_PKT_Q5_V1_8197F 0x7ff
+#define BIT_HEAD_PKT_Q5_V1_8197F(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q5_V1_8197F) \
+ << BIT_SHIFT_HEAD_PKT_Q5_V1_8197F)
+#define BITS_HEAD_PKT_Q5_V1_8197F \
+ (BIT_MASK_HEAD_PKT_Q5_V1_8197F << BIT_SHIFT_HEAD_PKT_Q5_V1_8197F)
+#define BIT_CLEAR_HEAD_PKT_Q5_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q5_V1_8197F))
+#define BIT_GET_HEAD_PKT_Q5_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1_8197F) & \
+ BIT_MASK_HEAD_PKT_Q5_V1_8197F)
+#define BIT_SET_HEAD_PKT_Q5_V1_8197F(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q5_V1_8197F(x) | BIT_HEAD_PKT_Q5_V1_8197F(v))
+
+/* 2 REG_Q6_INFO_8197F */
+
+#define BIT_SHIFT_QUEUEMACID_Q6_V1_8197F 25
+#define BIT_MASK_QUEUEMACID_Q6_V1_8197F 0x7f
+#define BIT_QUEUEMACID_Q6_V1_8197F(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q6_V1_8197F) \
+ << BIT_SHIFT_QUEUEMACID_Q6_V1_8197F)
+#define BITS_QUEUEMACID_Q6_V1_8197F \
+ (BIT_MASK_QUEUEMACID_Q6_V1_8197F << BIT_SHIFT_QUEUEMACID_Q6_V1_8197F)
+#define BIT_CLEAR_QUEUEMACID_Q6_V1_8197F(x) \
+ ((x) & (~BITS_QUEUEMACID_Q6_V1_8197F))
+#define BIT_GET_QUEUEMACID_Q6_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1_8197F) & \
+ BIT_MASK_QUEUEMACID_Q6_V1_8197F)
+#define BIT_SET_QUEUEMACID_Q6_V1_8197F(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q6_V1_8197F(x) | BIT_QUEUEMACID_Q6_V1_8197F(v))
+
+#define BIT_SHIFT_QUEUEAC_Q6_V1_8197F 23
+#define BIT_MASK_QUEUEAC_Q6_V1_8197F 0x3
+#define BIT_QUEUEAC_Q6_V1_8197F(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q6_V1_8197F) << BIT_SHIFT_QUEUEAC_Q6_V1_8197F)
+#define BITS_QUEUEAC_Q6_V1_8197F \
+ (BIT_MASK_QUEUEAC_Q6_V1_8197F << BIT_SHIFT_QUEUEAC_Q6_V1_8197F)
+#define BIT_CLEAR_QUEUEAC_Q6_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q6_V1_8197F))
+#define BIT_GET_QUEUEAC_Q6_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q6_V1_8197F) & BIT_MASK_QUEUEAC_Q6_V1_8197F)
+#define BIT_SET_QUEUEAC_Q6_V1_8197F(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q6_V1_8197F(x) | BIT_QUEUEAC_Q6_V1_8197F(v))
+
+#define BIT_TIDEMPTY_Q6_V1_8197F BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q6_V2_8197F 11
+#define BIT_MASK_TAIL_PKT_Q6_V2_8197F 0x7ff
+#define BIT_TAIL_PKT_Q6_V2_8197F(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q6_V2_8197F) \
+ << BIT_SHIFT_TAIL_PKT_Q6_V2_8197F)
+#define BITS_TAIL_PKT_Q6_V2_8197F \
+ (BIT_MASK_TAIL_PKT_Q6_V2_8197F << BIT_SHIFT_TAIL_PKT_Q6_V2_8197F)
+#define BIT_CLEAR_TAIL_PKT_Q6_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q6_V2_8197F))
+#define BIT_GET_TAIL_PKT_Q6_V2_8197F(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2_8197F) & \
+ BIT_MASK_TAIL_PKT_Q6_V2_8197F)
+#define BIT_SET_TAIL_PKT_Q6_V2_8197F(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q6_V2_8197F(x) | BIT_TAIL_PKT_Q6_V2_8197F(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q6_V1_8197F 0
+#define BIT_MASK_HEAD_PKT_Q6_V1_8197F 0x7ff
+#define BIT_HEAD_PKT_Q6_V1_8197F(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q6_V1_8197F) \
+ << BIT_SHIFT_HEAD_PKT_Q6_V1_8197F)
+#define BITS_HEAD_PKT_Q6_V1_8197F \
+ (BIT_MASK_HEAD_PKT_Q6_V1_8197F << BIT_SHIFT_HEAD_PKT_Q6_V1_8197F)
+#define BIT_CLEAR_HEAD_PKT_Q6_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q6_V1_8197F))
+#define BIT_GET_HEAD_PKT_Q6_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1_8197F) & \
+ BIT_MASK_HEAD_PKT_Q6_V1_8197F)
+#define BIT_SET_HEAD_PKT_Q6_V1_8197F(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q6_V1_8197F(x) | BIT_HEAD_PKT_Q6_V1_8197F(v))
+
+/* 2 REG_Q7_INFO_8197F */
+
+#define BIT_SHIFT_QUEUEMACID_Q7_V1_8197F 25
+#define BIT_MASK_QUEUEMACID_Q7_V1_8197F 0x7f
+#define BIT_QUEUEMACID_Q7_V1_8197F(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q7_V1_8197F) \
+ << BIT_SHIFT_QUEUEMACID_Q7_V1_8197F)
+#define BITS_QUEUEMACID_Q7_V1_8197F \
+ (BIT_MASK_QUEUEMACID_Q7_V1_8197F << BIT_SHIFT_QUEUEMACID_Q7_V1_8197F)
+#define BIT_CLEAR_QUEUEMACID_Q7_V1_8197F(x) \
+ ((x) & (~BITS_QUEUEMACID_Q7_V1_8197F))
+#define BIT_GET_QUEUEMACID_Q7_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1_8197F) & \
+ BIT_MASK_QUEUEMACID_Q7_V1_8197F)
+#define BIT_SET_QUEUEMACID_Q7_V1_8197F(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q7_V1_8197F(x) | BIT_QUEUEMACID_Q7_V1_8197F(v))
+
+#define BIT_SHIFT_QUEUEAC_Q7_V1_8197F 23
+#define BIT_MASK_QUEUEAC_Q7_V1_8197F 0x3
+#define BIT_QUEUEAC_Q7_V1_8197F(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q7_V1_8197F) << BIT_SHIFT_QUEUEAC_Q7_V1_8197F)
+#define BITS_QUEUEAC_Q7_V1_8197F \
+ (BIT_MASK_QUEUEAC_Q7_V1_8197F << BIT_SHIFT_QUEUEAC_Q7_V1_8197F)
+#define BIT_CLEAR_QUEUEAC_Q7_V1_8197F(x) ((x) & (~BITS_QUEUEAC_Q7_V1_8197F))
+#define BIT_GET_QUEUEAC_Q7_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q7_V1_8197F) & BIT_MASK_QUEUEAC_Q7_V1_8197F)
+#define BIT_SET_QUEUEAC_Q7_V1_8197F(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q7_V1_8197F(x) | BIT_QUEUEAC_Q7_V1_8197F(v))
+
+#define BIT_TIDEMPTY_Q7_V1_8197F BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q7_V2_8197F 11
+#define BIT_MASK_TAIL_PKT_Q7_V2_8197F 0x7ff
+#define BIT_TAIL_PKT_Q7_V2_8197F(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q7_V2_8197F) \
+ << BIT_SHIFT_TAIL_PKT_Q7_V2_8197F)
+#define BITS_TAIL_PKT_Q7_V2_8197F \
+ (BIT_MASK_TAIL_PKT_Q7_V2_8197F << BIT_SHIFT_TAIL_PKT_Q7_V2_8197F)
+#define BIT_CLEAR_TAIL_PKT_Q7_V2_8197F(x) ((x) & (~BITS_TAIL_PKT_Q7_V2_8197F))
+#define BIT_GET_TAIL_PKT_Q7_V2_8197F(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2_8197F) & \
+ BIT_MASK_TAIL_PKT_Q7_V2_8197F)
+#define BIT_SET_TAIL_PKT_Q7_V2_8197F(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q7_V2_8197F(x) | BIT_TAIL_PKT_Q7_V2_8197F(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q7_V1_8197F 0
+#define BIT_MASK_HEAD_PKT_Q7_V1_8197F 0x7ff
+#define BIT_HEAD_PKT_Q7_V1_8197F(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q7_V1_8197F) \
+ << BIT_SHIFT_HEAD_PKT_Q7_V1_8197F)
+#define BITS_HEAD_PKT_Q7_V1_8197F \
+ (BIT_MASK_HEAD_PKT_Q7_V1_8197F << BIT_SHIFT_HEAD_PKT_Q7_V1_8197F)
+#define BIT_CLEAR_HEAD_PKT_Q7_V1_8197F(x) ((x) & (~BITS_HEAD_PKT_Q7_V1_8197F))
+#define BIT_GET_HEAD_PKT_Q7_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1_8197F) & \
+ BIT_MASK_HEAD_PKT_Q7_V1_8197F)
+#define BIT_SET_HEAD_PKT_Q7_V1_8197F(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q7_V1_8197F(x) | BIT_HEAD_PKT_Q7_V1_8197F(v))
+
+/* 2 REG_WMAC_LBK_BUF_HD_V1_8197F */
+
+#define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8197F 0
+#define BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8197F 0xfff
+#define BIT_WMAC_LBK_BUF_HEAD_V1_8197F(x) \
+ (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8197F) \
+ << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8197F)
+#define BITS_WMAC_LBK_BUF_HEAD_V1_8197F \
+ (BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8197F \
+ << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8197F)
+#define BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8197F(x) \
+ ((x) & (~BITS_WMAC_LBK_BUF_HEAD_V1_8197F))
+#define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8197F) & \
+ BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8197F)
+#define BIT_SET_WMAC_LBK_BUF_HEAD_V1_8197F(x, v) \
+ (BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8197F(x) | \
+ BIT_WMAC_LBK_BUF_HEAD_V1_8197F(v))
+
+/* 2 REG_MGQ_BDNY_V1_8197F */
+
+#define BIT_SHIFT_MGQ_PGBNDY_V1_8197F 0
+#define BIT_MASK_MGQ_PGBNDY_V1_8197F 0xfff
+#define BIT_MGQ_PGBNDY_V1_8197F(x) \
+ (((x) & BIT_MASK_MGQ_PGBNDY_V1_8197F) << BIT_SHIFT_MGQ_PGBNDY_V1_8197F)
+#define BITS_MGQ_PGBNDY_V1_8197F \
+ (BIT_MASK_MGQ_PGBNDY_V1_8197F << BIT_SHIFT_MGQ_PGBNDY_V1_8197F)
+#define BIT_CLEAR_MGQ_PGBNDY_V1_8197F(x) ((x) & (~BITS_MGQ_PGBNDY_V1_8197F))
+#define BIT_GET_MGQ_PGBNDY_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8197F) & BIT_MASK_MGQ_PGBNDY_V1_8197F)
+#define BIT_SET_MGQ_PGBNDY_V1_8197F(x, v) \
+ (BIT_CLEAR_MGQ_PGBNDY_V1_8197F(x) | BIT_MGQ_PGBNDY_V1_8197F(v))
+
+/* 2 REG_TXRPT_CTRL_8197F */
+
+#define BIT_SHIFT_TRXRPT_TIMER_TH_8197F 24
+#define BIT_MASK_TRXRPT_TIMER_TH_8197F 0xff
+#define BIT_TRXRPT_TIMER_TH_8197F(x) \
+ (((x) & BIT_MASK_TRXRPT_TIMER_TH_8197F) \
+ << BIT_SHIFT_TRXRPT_TIMER_TH_8197F)
+#define BITS_TRXRPT_TIMER_TH_8197F \
+ (BIT_MASK_TRXRPT_TIMER_TH_8197F << BIT_SHIFT_TRXRPT_TIMER_TH_8197F)
+#define BIT_CLEAR_TRXRPT_TIMER_TH_8197F(x) ((x) & (~BITS_TRXRPT_TIMER_TH_8197F))
+#define BIT_GET_TRXRPT_TIMER_TH_8197F(x) \
+ (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8197F) & \
+ BIT_MASK_TRXRPT_TIMER_TH_8197F)
+#define BIT_SET_TRXRPT_TIMER_TH_8197F(x, v) \
+ (BIT_CLEAR_TRXRPT_TIMER_TH_8197F(x) | BIT_TRXRPT_TIMER_TH_8197F(v))
+
+#define BIT_SHIFT_TRXRPT_LEN_TH_8197F 16
+#define BIT_MASK_TRXRPT_LEN_TH_8197F 0xff
+#define BIT_TRXRPT_LEN_TH_8197F(x) \
+ (((x) & BIT_MASK_TRXRPT_LEN_TH_8197F) << BIT_SHIFT_TRXRPT_LEN_TH_8197F)
+#define BITS_TRXRPT_LEN_TH_8197F \
+ (BIT_MASK_TRXRPT_LEN_TH_8197F << BIT_SHIFT_TRXRPT_LEN_TH_8197F)
+#define BIT_CLEAR_TRXRPT_LEN_TH_8197F(x) ((x) & (~BITS_TRXRPT_LEN_TH_8197F))
+#define BIT_GET_TRXRPT_LEN_TH_8197F(x) \
+ (((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8197F) & BIT_MASK_TRXRPT_LEN_TH_8197F)
+#define BIT_SET_TRXRPT_LEN_TH_8197F(x, v) \
+ (BIT_CLEAR_TRXRPT_LEN_TH_8197F(x) | BIT_TRXRPT_LEN_TH_8197F(v))
+
+#define BIT_SHIFT_TRXRPT_READ_PTR_8197F 8
+#define BIT_MASK_TRXRPT_READ_PTR_8197F 0xff
+#define BIT_TRXRPT_READ_PTR_8197F(x) \
+ (((x) & BIT_MASK_TRXRPT_READ_PTR_8197F) \
+ << BIT_SHIFT_TRXRPT_READ_PTR_8197F)
+#define BITS_TRXRPT_READ_PTR_8197F \
+ (BIT_MASK_TRXRPT_READ_PTR_8197F << BIT_SHIFT_TRXRPT_READ_PTR_8197F)
+#define BIT_CLEAR_TRXRPT_READ_PTR_8197F(x) ((x) & (~BITS_TRXRPT_READ_PTR_8197F))
+#define BIT_GET_TRXRPT_READ_PTR_8197F(x) \
+ (((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8197F) & \
+ BIT_MASK_TRXRPT_READ_PTR_8197F)
+#define BIT_SET_TRXRPT_READ_PTR_8197F(x, v) \
+ (BIT_CLEAR_TRXRPT_READ_PTR_8197F(x) | BIT_TRXRPT_READ_PTR_8197F(v))
+
+#define BIT_SHIFT_TRXRPT_WRITE_PTR_8197F 0
+#define BIT_MASK_TRXRPT_WRITE_PTR_8197F 0xff
+#define BIT_TRXRPT_WRITE_PTR_8197F(x) \
+ (((x) & BIT_MASK_TRXRPT_WRITE_PTR_8197F) \
+ << BIT_SHIFT_TRXRPT_WRITE_PTR_8197F)
+#define BITS_TRXRPT_WRITE_PTR_8197F \
+ (BIT_MASK_TRXRPT_WRITE_PTR_8197F << BIT_SHIFT_TRXRPT_WRITE_PTR_8197F)
+#define BIT_CLEAR_TRXRPT_WRITE_PTR_8197F(x) \
+ ((x) & (~BITS_TRXRPT_WRITE_PTR_8197F))
+#define BIT_GET_TRXRPT_WRITE_PTR_8197F(x) \
+ (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8197F) & \
+ BIT_MASK_TRXRPT_WRITE_PTR_8197F)
+#define BIT_SET_TRXRPT_WRITE_PTR_8197F(x, v) \
+ (BIT_CLEAR_TRXRPT_WRITE_PTR_8197F(x) | BIT_TRXRPT_WRITE_PTR_8197F(v))
+
+/* 2 REG_INIRTS_RATE_SEL_8197F */
+#define BIT_LEAG_RTS_BW_DUP_8197F BIT(5)
+
+/* 2 REG_BASIC_CFEND_RATE_8197F */
+
+#define BIT_SHIFT_BASIC_CFEND_RATE_8197F 0
+#define BIT_MASK_BASIC_CFEND_RATE_8197F 0x1f
+#define BIT_BASIC_CFEND_RATE_8197F(x) \
+ (((x) & BIT_MASK_BASIC_CFEND_RATE_8197F) \
+ << BIT_SHIFT_BASIC_CFEND_RATE_8197F)
+#define BITS_BASIC_CFEND_RATE_8197F \
+ (BIT_MASK_BASIC_CFEND_RATE_8197F << BIT_SHIFT_BASIC_CFEND_RATE_8197F)
+#define BIT_CLEAR_BASIC_CFEND_RATE_8197F(x) \
+ ((x) & (~BITS_BASIC_CFEND_RATE_8197F))
+#define BIT_GET_BASIC_CFEND_RATE_8197F(x) \
+ (((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8197F) & \
+ BIT_MASK_BASIC_CFEND_RATE_8197F)
+#define BIT_SET_BASIC_CFEND_RATE_8197F(x, v) \
+ (BIT_CLEAR_BASIC_CFEND_RATE_8197F(x) | BIT_BASIC_CFEND_RATE_8197F(v))
+
+/* 2 REG_STBC_CFEND_RATE_8197F */
+
+#define BIT_SHIFT_STBC_CFEND_RATE_8197F 0
+#define BIT_MASK_STBC_CFEND_RATE_8197F 0x1f
+#define BIT_STBC_CFEND_RATE_8197F(x) \
+ (((x) & BIT_MASK_STBC_CFEND_RATE_8197F) \
+ << BIT_SHIFT_STBC_CFEND_RATE_8197F)
+#define BITS_STBC_CFEND_RATE_8197F \
+ (BIT_MASK_STBC_CFEND_RATE_8197F << BIT_SHIFT_STBC_CFEND_RATE_8197F)
+#define BIT_CLEAR_STBC_CFEND_RATE_8197F(x) ((x) & (~BITS_STBC_CFEND_RATE_8197F))
+#define BIT_GET_STBC_CFEND_RATE_8197F(x) \
+ (((x) >> BIT_SHIFT_STBC_CFEND_RATE_8197F) & \
+ BIT_MASK_STBC_CFEND_RATE_8197F)
+#define BIT_SET_STBC_CFEND_RATE_8197F(x, v) \
+ (BIT_CLEAR_STBC_CFEND_RATE_8197F(x) | BIT_STBC_CFEND_RATE_8197F(v))
+
+/* 2 REG_DATA_SC_8197F */
+
+#define BIT_SHIFT_TXSC_40M_8197F 4
+#define BIT_MASK_TXSC_40M_8197F 0xf
+#define BIT_TXSC_40M_8197F(x) \
+ (((x) & BIT_MASK_TXSC_40M_8197F) << BIT_SHIFT_TXSC_40M_8197F)
+#define BITS_TXSC_40M_8197F \
+ (BIT_MASK_TXSC_40M_8197F << BIT_SHIFT_TXSC_40M_8197F)
+#define BIT_CLEAR_TXSC_40M_8197F(x) ((x) & (~BITS_TXSC_40M_8197F))
+#define BIT_GET_TXSC_40M_8197F(x) \
+ (((x) >> BIT_SHIFT_TXSC_40M_8197F) & BIT_MASK_TXSC_40M_8197F)
+#define BIT_SET_TXSC_40M_8197F(x, v) \
+ (BIT_CLEAR_TXSC_40M_8197F(x) | BIT_TXSC_40M_8197F(v))
+
+#define BIT_SHIFT_TXSC_20M_8197F 0
+#define BIT_MASK_TXSC_20M_8197F 0xf
+#define BIT_TXSC_20M_8197F(x) \
+ (((x) & BIT_MASK_TXSC_20M_8197F) << BIT_SHIFT_TXSC_20M_8197F)
+#define BITS_TXSC_20M_8197F \
+ (BIT_MASK_TXSC_20M_8197F << BIT_SHIFT_TXSC_20M_8197F)
+#define BIT_CLEAR_TXSC_20M_8197F(x) ((x) & (~BITS_TXSC_20M_8197F))
+#define BIT_GET_TXSC_20M_8197F(x) \
+ (((x) >> BIT_SHIFT_TXSC_20M_8197F) & BIT_MASK_TXSC_20M_8197F)
+#define BIT_SET_TXSC_20M_8197F(x, v) \
+ (BIT_CLEAR_TXSC_20M_8197F(x) | BIT_TXSC_20M_8197F(v))
+
+/* 2 REG_MACID_SLEEP3_8197F */
+
+#define BIT_SHIFT_MACID127_96_PKTSLEEP_8197F 0
+#define BIT_MASK_MACID127_96_PKTSLEEP_8197F 0xffffffffL
+#define BIT_MACID127_96_PKTSLEEP_8197F(x) \
+ (((x) & BIT_MASK_MACID127_96_PKTSLEEP_8197F) \
+ << BIT_SHIFT_MACID127_96_PKTSLEEP_8197F)
+#define BITS_MACID127_96_PKTSLEEP_8197F \
+ (BIT_MASK_MACID127_96_PKTSLEEP_8197F \
+ << BIT_SHIFT_MACID127_96_PKTSLEEP_8197F)
+#define BIT_CLEAR_MACID127_96_PKTSLEEP_8197F(x) \
+ ((x) & (~BITS_MACID127_96_PKTSLEEP_8197F))
+#define BIT_GET_MACID127_96_PKTSLEEP_8197F(x) \
+ (((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP_8197F) & \
+ BIT_MASK_MACID127_96_PKTSLEEP_8197F)
+#define BIT_SET_MACID127_96_PKTSLEEP_8197F(x, v) \
+ (BIT_CLEAR_MACID127_96_PKTSLEEP_8197F(x) | \
+ BIT_MACID127_96_PKTSLEEP_8197F(v))
+
+/* 2 REG_MACID_SLEEP1_8197F */
+
+#define BIT_SHIFT_MACID63_32_PKTSLEEP_8197F 0
+#define BIT_MASK_MACID63_32_PKTSLEEP_8197F 0xffffffffL
+#define BIT_MACID63_32_PKTSLEEP_8197F(x) \
+ (((x) & BIT_MASK_MACID63_32_PKTSLEEP_8197F) \
+ << BIT_SHIFT_MACID63_32_PKTSLEEP_8197F)
+#define BITS_MACID63_32_PKTSLEEP_8197F \
+ (BIT_MASK_MACID63_32_PKTSLEEP_8197F \
+ << BIT_SHIFT_MACID63_32_PKTSLEEP_8197F)
+#define BIT_CLEAR_MACID63_32_PKTSLEEP_8197F(x) \
+ ((x) & (~BITS_MACID63_32_PKTSLEEP_8197F))
+#define BIT_GET_MACID63_32_PKTSLEEP_8197F(x) \
+ (((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP_8197F) & \
+ BIT_MASK_MACID63_32_PKTSLEEP_8197F)
+#define BIT_SET_MACID63_32_PKTSLEEP_8197F(x, v) \
+ (BIT_CLEAR_MACID63_32_PKTSLEEP_8197F(x) | \
+ BIT_MACID63_32_PKTSLEEP_8197F(v))
+
+/* 2 REG_ARFR2_V1_8197F */
+
+#define BIT_SHIFT_ARFR2_V1_8197F 0
+#define BIT_MASK_ARFR2_V1_8197F 0xffffffffffffffffL
+#define BIT_ARFR2_V1_8197F(x) \
+ (((x) & BIT_MASK_ARFR2_V1_8197F) << BIT_SHIFT_ARFR2_V1_8197F)
+#define BITS_ARFR2_V1_8197F \
+ (BIT_MASK_ARFR2_V1_8197F << BIT_SHIFT_ARFR2_V1_8197F)
+#define BIT_CLEAR_ARFR2_V1_8197F(x) ((x) & (~BITS_ARFR2_V1_8197F))
+#define BIT_GET_ARFR2_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_ARFR2_V1_8197F) & BIT_MASK_ARFR2_V1_8197F)
+#define BIT_SET_ARFR2_V1_8197F(x, v) \
+ (BIT_CLEAR_ARFR2_V1_8197F(x) | BIT_ARFR2_V1_8197F(v))
+
+/* 2 REG_ARFR3_V1_8197F */
+
+#define BIT_SHIFT_ARFR3_V1_8197F 0
+#define BIT_MASK_ARFR3_V1_8197F 0xffffffffffffffffL
+#define BIT_ARFR3_V1_8197F(x) \
+ (((x) & BIT_MASK_ARFR3_V1_8197F) << BIT_SHIFT_ARFR3_V1_8197F)
+#define BITS_ARFR3_V1_8197F \
+ (BIT_MASK_ARFR3_V1_8197F << BIT_SHIFT_ARFR3_V1_8197F)
+#define BIT_CLEAR_ARFR3_V1_8197F(x) ((x) & (~BITS_ARFR3_V1_8197F))
+#define BIT_GET_ARFR3_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_ARFR3_V1_8197F) & BIT_MASK_ARFR3_V1_8197F)
+#define BIT_SET_ARFR3_V1_8197F(x, v) \
+ (BIT_CLEAR_ARFR3_V1_8197F(x) | BIT_ARFR3_V1_8197F(v))
+
+/* 2 REG_ARFR4_8197F */
+
+#define BIT_SHIFT_ARFR4_8197F 0
+#define BIT_MASK_ARFR4_8197F 0xffffffffffffffffL
+#define BIT_ARFR4_8197F(x) \
+ (((x) & BIT_MASK_ARFR4_8197F) << BIT_SHIFT_ARFR4_8197F)
+#define BITS_ARFR4_8197F (BIT_MASK_ARFR4_8197F << BIT_SHIFT_ARFR4_8197F)
+#define BIT_CLEAR_ARFR4_8197F(x) ((x) & (~BITS_ARFR4_8197F))
+#define BIT_GET_ARFR4_8197F(x) \
+ (((x) >> BIT_SHIFT_ARFR4_8197F) & BIT_MASK_ARFR4_8197F)
+#define BIT_SET_ARFR4_8197F(x, v) \
+ (BIT_CLEAR_ARFR4_8197F(x) | BIT_ARFR4_8197F(v))
+
+/* 2 REG_ARFR5_8197F */
+
+#define BIT_SHIFT_ARFR5_8197F 0
+#define BIT_MASK_ARFR5_8197F 0xffffffffffffffffL
+#define BIT_ARFR5_8197F(x) \
+ (((x) & BIT_MASK_ARFR5_8197F) << BIT_SHIFT_ARFR5_8197F)
+#define BITS_ARFR5_8197F (BIT_MASK_ARFR5_8197F << BIT_SHIFT_ARFR5_8197F)
+#define BIT_CLEAR_ARFR5_8197F(x) ((x) & (~BITS_ARFR5_8197F))
+#define BIT_GET_ARFR5_8197F(x) \
+ (((x) >> BIT_SHIFT_ARFR5_8197F) & BIT_MASK_ARFR5_8197F)
+#define BIT_SET_ARFR5_8197F(x, v) \
+ (BIT_CLEAR_ARFR5_8197F(x) | BIT_ARFR5_8197F(v))
+
+/* 2 REG_TXRPT_START_OFFSET_8197F */
+#define BIT_SHCUT_PARSE_DASA_8197F BIT(25)
+#define BIT_SHCUT_BYPASS_8197F BIT(24)
+#define BIT__R_RPTFIFO_1K_8197F BIT(16)
+
+#define BIT_SHIFT_MACID_CTRL_OFFSET_8197F 8
+#define BIT_MASK_MACID_CTRL_OFFSET_8197F 0xff
+#define BIT_MACID_CTRL_OFFSET_8197F(x) \
+ (((x) & BIT_MASK_MACID_CTRL_OFFSET_8197F) \
+ << BIT_SHIFT_MACID_CTRL_OFFSET_8197F)
+#define BITS_MACID_CTRL_OFFSET_8197F \
+ (BIT_MASK_MACID_CTRL_OFFSET_8197F << BIT_SHIFT_MACID_CTRL_OFFSET_8197F)
+#define BIT_CLEAR_MACID_CTRL_OFFSET_8197F(x) \
+ ((x) & (~BITS_MACID_CTRL_OFFSET_8197F))
+#define BIT_GET_MACID_CTRL_OFFSET_8197F(x) \
+ (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_8197F) & \
+ BIT_MASK_MACID_CTRL_OFFSET_8197F)
+#define BIT_SET_MACID_CTRL_OFFSET_8197F(x, v) \
+ (BIT_CLEAR_MACID_CTRL_OFFSET_8197F(x) | BIT_MACID_CTRL_OFFSET_8197F(v))
+
+#define BIT_SHIFT_AMPDU_TXRPT_OFFSET_8197F 0
+#define BIT_MASK_AMPDU_TXRPT_OFFSET_8197F 0xff
+#define BIT_AMPDU_TXRPT_OFFSET_8197F(x) \
+ (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_8197F) \
+ << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8197F)
+#define BITS_AMPDU_TXRPT_OFFSET_8197F \
+ (BIT_MASK_AMPDU_TXRPT_OFFSET_8197F \
+ << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8197F)
+#define BIT_CLEAR_AMPDU_TXRPT_OFFSET_8197F(x) \
+ ((x) & (~BITS_AMPDU_TXRPT_OFFSET_8197F))
+#define BIT_GET_AMPDU_TXRPT_OFFSET_8197F(x) \
+ (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_8197F) & \
+ BIT_MASK_AMPDU_TXRPT_OFFSET_8197F)
+#define BIT_SET_AMPDU_TXRPT_OFFSET_8197F(x, v) \
+ (BIT_CLEAR_AMPDU_TXRPT_OFFSET_8197F(x) | \
+ BIT_AMPDU_TXRPT_OFFSET_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_POWER_STAGE1_8197F */
+#define BIT_PTA_WL_PRI_MASK_CPU_MGQ_8197F BIT(31)
+#define BIT_PTA_WL_PRI_MASK_BCNQ_8197F BIT(30)
+#define BIT_PTA_WL_PRI_MASK_HIQ_8197F BIT(29)
+#define BIT_PTA_WL_PRI_MASK_MGQ_8197F BIT(28)
+#define BIT_PTA_WL_PRI_MASK_BK_8197F BIT(27)
+#define BIT_PTA_WL_PRI_MASK_BE_8197F BIT(26)
+#define BIT_PTA_WL_PRI_MASK_VI_8197F BIT(25)
+#define BIT_PTA_WL_PRI_MASK_VO_8197F BIT(24)
+
+#define BIT_SHIFT_POWER_STAGE1_8197F 0
+#define BIT_MASK_POWER_STAGE1_8197F 0xffffff
+#define BIT_POWER_STAGE1_8197F(x) \
+ (((x) & BIT_MASK_POWER_STAGE1_8197F) << BIT_SHIFT_POWER_STAGE1_8197F)
+#define BITS_POWER_STAGE1_8197F \
+ (BIT_MASK_POWER_STAGE1_8197F << BIT_SHIFT_POWER_STAGE1_8197F)
+#define BIT_CLEAR_POWER_STAGE1_8197F(x) ((x) & (~BITS_POWER_STAGE1_8197F))
+#define BIT_GET_POWER_STAGE1_8197F(x) \
+ (((x) >> BIT_SHIFT_POWER_STAGE1_8197F) & BIT_MASK_POWER_STAGE1_8197F)
+#define BIT_SET_POWER_STAGE1_8197F(x, v) \
+ (BIT_CLEAR_POWER_STAGE1_8197F(x) | BIT_POWER_STAGE1_8197F(v))
+
+/* 2 REG_POWER_STAGE2_8197F */
+#define BIT__R_CTRL_PKT_POW_ADJ_8197F BIT(24)
+
+#define BIT_SHIFT_POWER_STAGE2_8197F 0
+#define BIT_MASK_POWER_STAGE2_8197F 0xffffff
+#define BIT_POWER_STAGE2_8197F(x) \
+ (((x) & BIT_MASK_POWER_STAGE2_8197F) << BIT_SHIFT_POWER_STAGE2_8197F)
+#define BITS_POWER_STAGE2_8197F \
+ (BIT_MASK_POWER_STAGE2_8197F << BIT_SHIFT_POWER_STAGE2_8197F)
+#define BIT_CLEAR_POWER_STAGE2_8197F(x) ((x) & (~BITS_POWER_STAGE2_8197F))
+#define BIT_GET_POWER_STAGE2_8197F(x) \
+ (((x) >> BIT_SHIFT_POWER_STAGE2_8197F) & BIT_MASK_POWER_STAGE2_8197F)
+#define BIT_SET_POWER_STAGE2_8197F(x, v) \
+ (BIT_CLEAR_POWER_STAGE2_8197F(x) | BIT_POWER_STAGE2_8197F(v))
+
+/* 2 REG_SW_AMPDU_BURST_MODE_CTRL_8197F */
+
+#define BIT_SHIFT_PAD_NUM_THRES_8197F 24
+#define BIT_MASK_PAD_NUM_THRES_8197F 0x3f
+#define BIT_PAD_NUM_THRES_8197F(x) \
+ (((x) & BIT_MASK_PAD_NUM_THRES_8197F) << BIT_SHIFT_PAD_NUM_THRES_8197F)
+#define BITS_PAD_NUM_THRES_8197F \
+ (BIT_MASK_PAD_NUM_THRES_8197F << BIT_SHIFT_PAD_NUM_THRES_8197F)
+#define BIT_CLEAR_PAD_NUM_THRES_8197F(x) ((x) & (~BITS_PAD_NUM_THRES_8197F))
+#define BIT_GET_PAD_NUM_THRES_8197F(x) \
+ (((x) >> BIT_SHIFT_PAD_NUM_THRES_8197F) & BIT_MASK_PAD_NUM_THRES_8197F)
+#define BIT_SET_PAD_NUM_THRES_8197F(x, v) \
+ (BIT_CLEAR_PAD_NUM_THRES_8197F(x) | BIT_PAD_NUM_THRES_8197F(v))
+
+#define BIT_R_DMA_THIS_QUEUE_BK_8197F BIT(23)
+#define BIT_R_DMA_THIS_QUEUE_BE_8197F BIT(22)
+#define BIT_R_DMA_THIS_QUEUE_VI_8197F BIT(21)
+#define BIT_R_DMA_THIS_QUEUE_VO_8197F BIT(20)
+
+#define BIT_SHIFT_R_TOTAL_LEN_TH_8197F 8
+#define BIT_MASK_R_TOTAL_LEN_TH_8197F 0xfff
+#define BIT_R_TOTAL_LEN_TH_8197F(x) \
+ (((x) & BIT_MASK_R_TOTAL_LEN_TH_8197F) \
+ << BIT_SHIFT_R_TOTAL_LEN_TH_8197F)
+#define BITS_R_TOTAL_LEN_TH_8197F \
+ (BIT_MASK_R_TOTAL_LEN_TH_8197F << BIT_SHIFT_R_TOTAL_LEN_TH_8197F)
+#define BIT_CLEAR_R_TOTAL_LEN_TH_8197F(x) ((x) & (~BITS_R_TOTAL_LEN_TH_8197F))
+#define BIT_GET_R_TOTAL_LEN_TH_8197F(x) \
+ (((x) >> BIT_SHIFT_R_TOTAL_LEN_TH_8197F) & \
+ BIT_MASK_R_TOTAL_LEN_TH_8197F)
+#define BIT_SET_R_TOTAL_LEN_TH_8197F(x, v) \
+ (BIT_CLEAR_R_TOTAL_LEN_TH_8197F(x) | BIT_R_TOTAL_LEN_TH_8197F(v))
+
+#define BIT_EN_NEW_EARLY_8197F BIT(7)
+#define BIT_PRE_TX_CMD_8197F BIT(6)
+
+#define BIT_SHIFT_NUM_SCL_EN_8197F 4
+#define BIT_MASK_NUM_SCL_EN_8197F 0x3
+#define BIT_NUM_SCL_EN_8197F(x) \
+ (((x) & BIT_MASK_NUM_SCL_EN_8197F) << BIT_SHIFT_NUM_SCL_EN_8197F)
+#define BITS_NUM_SCL_EN_8197F \
+ (BIT_MASK_NUM_SCL_EN_8197F << BIT_SHIFT_NUM_SCL_EN_8197F)
+#define BIT_CLEAR_NUM_SCL_EN_8197F(x) ((x) & (~BITS_NUM_SCL_EN_8197F))
+#define BIT_GET_NUM_SCL_EN_8197F(x) \
+ (((x) >> BIT_SHIFT_NUM_SCL_EN_8197F) & BIT_MASK_NUM_SCL_EN_8197F)
+#define BIT_SET_NUM_SCL_EN_8197F(x, v) \
+ (BIT_CLEAR_NUM_SCL_EN_8197F(x) | BIT_NUM_SCL_EN_8197F(v))
+
+#define BIT_BK_EN_8197F BIT(3)
+#define BIT_BE_EN_8197F BIT(2)
+#define BIT_VI_EN_8197F BIT(1)
+#define BIT_VO_EN_8197F BIT(0)
+
+/* 2 REG_PKT_LIFE_TIME_8197F */
+
+#define BIT_SHIFT_PKT_LIFTIME_BEBK_8197F 16
+#define BIT_MASK_PKT_LIFTIME_BEBK_8197F 0xffff
+#define BIT_PKT_LIFTIME_BEBK_8197F(x) \
+ (((x) & BIT_MASK_PKT_LIFTIME_BEBK_8197F) \
+ << BIT_SHIFT_PKT_LIFTIME_BEBK_8197F)
+#define BITS_PKT_LIFTIME_BEBK_8197F \
+ (BIT_MASK_PKT_LIFTIME_BEBK_8197F << BIT_SHIFT_PKT_LIFTIME_BEBK_8197F)
+#define BIT_CLEAR_PKT_LIFTIME_BEBK_8197F(x) \
+ ((x) & (~BITS_PKT_LIFTIME_BEBK_8197F))
+#define BIT_GET_PKT_LIFTIME_BEBK_8197F(x) \
+ (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8197F) & \
+ BIT_MASK_PKT_LIFTIME_BEBK_8197F)
+#define BIT_SET_PKT_LIFTIME_BEBK_8197F(x, v) \
+ (BIT_CLEAR_PKT_LIFTIME_BEBK_8197F(x) | BIT_PKT_LIFTIME_BEBK_8197F(v))
+
+#define BIT_SHIFT_PKT_LIFTIME_VOVI_8197F 0
+#define BIT_MASK_PKT_LIFTIME_VOVI_8197F 0xffff
+#define BIT_PKT_LIFTIME_VOVI_8197F(x) \
+ (((x) & BIT_MASK_PKT_LIFTIME_VOVI_8197F) \
+ << BIT_SHIFT_PKT_LIFTIME_VOVI_8197F)
+#define BITS_PKT_LIFTIME_VOVI_8197F \
+ (BIT_MASK_PKT_LIFTIME_VOVI_8197F << BIT_SHIFT_PKT_LIFTIME_VOVI_8197F)
+#define BIT_CLEAR_PKT_LIFTIME_VOVI_8197F(x) \
+ ((x) & (~BITS_PKT_LIFTIME_VOVI_8197F))
+#define BIT_GET_PKT_LIFTIME_VOVI_8197F(x) \
+ (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8197F) & \
+ BIT_MASK_PKT_LIFTIME_VOVI_8197F)
+#define BIT_SET_PKT_LIFTIME_VOVI_8197F(x, v) \
+ (BIT_CLEAR_PKT_LIFTIME_VOVI_8197F(x) | BIT_PKT_LIFTIME_VOVI_8197F(v))
+
+/* 2 REG_STBC_SETTING_8197F */
+
+#define BIT_SHIFT_CDEND_TXTIME_L_8197F 4
+#define BIT_MASK_CDEND_TXTIME_L_8197F 0xf
+#define BIT_CDEND_TXTIME_L_8197F(x) \
+ (((x) & BIT_MASK_CDEND_TXTIME_L_8197F) \
+ << BIT_SHIFT_CDEND_TXTIME_L_8197F)
+#define BITS_CDEND_TXTIME_L_8197F \
+ (BIT_MASK_CDEND_TXTIME_L_8197F << BIT_SHIFT_CDEND_TXTIME_L_8197F)
+#define BIT_CLEAR_CDEND_TXTIME_L_8197F(x) ((x) & (~BITS_CDEND_TXTIME_L_8197F))
+#define BIT_GET_CDEND_TXTIME_L_8197F(x) \
+ (((x) >> BIT_SHIFT_CDEND_TXTIME_L_8197F) & \
+ BIT_MASK_CDEND_TXTIME_L_8197F)
+#define BIT_SET_CDEND_TXTIME_L_8197F(x, v) \
+ (BIT_CLEAR_CDEND_TXTIME_L_8197F(x) | BIT_CDEND_TXTIME_L_8197F(v))
+
+#define BIT_SHIFT_NESS_8197F 2
+#define BIT_MASK_NESS_8197F 0x3
+#define BIT_NESS_8197F(x) (((x) & BIT_MASK_NESS_8197F) << BIT_SHIFT_NESS_8197F)
+#define BITS_NESS_8197F (BIT_MASK_NESS_8197F << BIT_SHIFT_NESS_8197F)
+#define BIT_CLEAR_NESS_8197F(x) ((x) & (~BITS_NESS_8197F))
+#define BIT_GET_NESS_8197F(x) \
+ (((x) >> BIT_SHIFT_NESS_8197F) & BIT_MASK_NESS_8197F)
+#define BIT_SET_NESS_8197F(x, v) (BIT_CLEAR_NESS_8197F(x) | BIT_NESS_8197F(v))
+
+#define BIT_SHIFT_STBC_CFEND_8197F 0
+#define BIT_MASK_STBC_CFEND_8197F 0x3
+#define BIT_STBC_CFEND_8197F(x) \
+ (((x) & BIT_MASK_STBC_CFEND_8197F) << BIT_SHIFT_STBC_CFEND_8197F)
+#define BITS_STBC_CFEND_8197F \
+ (BIT_MASK_STBC_CFEND_8197F << BIT_SHIFT_STBC_CFEND_8197F)
+#define BIT_CLEAR_STBC_CFEND_8197F(x) ((x) & (~BITS_STBC_CFEND_8197F))
+#define BIT_GET_STBC_CFEND_8197F(x) \
+ (((x) >> BIT_SHIFT_STBC_CFEND_8197F) & BIT_MASK_STBC_CFEND_8197F)
+#define BIT_SET_STBC_CFEND_8197F(x, v) \
+ (BIT_CLEAR_STBC_CFEND_8197F(x) | BIT_STBC_CFEND_8197F(v))
+
+/* 2 REG_STBC_SETTING2_8197F */
+
+#define BIT_SHIFT_CDEND_TXTIME_H_8197F 0
+#define BIT_MASK_CDEND_TXTIME_H_8197F 0x1f
+#define BIT_CDEND_TXTIME_H_8197F(x) \
+ (((x) & BIT_MASK_CDEND_TXTIME_H_8197F) \
+ << BIT_SHIFT_CDEND_TXTIME_H_8197F)
+#define BITS_CDEND_TXTIME_H_8197F \
+ (BIT_MASK_CDEND_TXTIME_H_8197F << BIT_SHIFT_CDEND_TXTIME_H_8197F)
+#define BIT_CLEAR_CDEND_TXTIME_H_8197F(x) ((x) & (~BITS_CDEND_TXTIME_H_8197F))
+#define BIT_GET_CDEND_TXTIME_H_8197F(x) \
+ (((x) >> BIT_SHIFT_CDEND_TXTIME_H_8197F) & \
+ BIT_MASK_CDEND_TXTIME_H_8197F)
+#define BIT_SET_CDEND_TXTIME_H_8197F(x, v) \
+ (BIT_CLEAR_CDEND_TXTIME_H_8197F(x) | BIT_CDEND_TXTIME_H_8197F(v))
+
+/* 2 REG_QUEUE_CTRL_8197F */
+#define BIT_PTA_EDCCA_EN_8197F BIT(5)
+#define BIT_PTA_WL_TX_EN_8197F BIT(4)
+#define BIT_R_USE_DATA_BW_8197F BIT(3)
+#define BIT_TRI_PKT_INT_MODE1_8197F BIT(2)
+#define BIT_TRI_PKT_INT_MODE0_8197F BIT(1)
+#define BIT_ACQ_MODE_SEL_8197F BIT(0)
+
+/* 2 REG_SINGLE_AMPDU_CTRL_8197F */
+#define BIT_EN_SINGLE_APMDU_8197F BIT(7)
+
+/* 2 REG_PROT_MODE_CTRL_8197F */
+
+#define BIT_SHIFT_RTS_MAX_AGG_NUM_8197F 24
+#define BIT_MASK_RTS_MAX_AGG_NUM_8197F 0x3f
+#define BIT_RTS_MAX_AGG_NUM_8197F(x) \
+ (((x) & BIT_MASK_RTS_MAX_AGG_NUM_8197F) \
+ << BIT_SHIFT_RTS_MAX_AGG_NUM_8197F)
+#define BITS_RTS_MAX_AGG_NUM_8197F \
+ (BIT_MASK_RTS_MAX_AGG_NUM_8197F << BIT_SHIFT_RTS_MAX_AGG_NUM_8197F)
+#define BIT_CLEAR_RTS_MAX_AGG_NUM_8197F(x) ((x) & (~BITS_RTS_MAX_AGG_NUM_8197F))
+#define BIT_GET_RTS_MAX_AGG_NUM_8197F(x) \
+ (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8197F) & \
+ BIT_MASK_RTS_MAX_AGG_NUM_8197F)
+#define BIT_SET_RTS_MAX_AGG_NUM_8197F(x, v) \
+ (BIT_CLEAR_RTS_MAX_AGG_NUM_8197F(x) | BIT_RTS_MAX_AGG_NUM_8197F(v))
+
+#define BIT_SHIFT_MAX_AGG_NUM_8197F 16
+#define BIT_MASK_MAX_AGG_NUM_8197F 0x3f
+#define BIT_MAX_AGG_NUM_8197F(x) \
+ (((x) & BIT_MASK_MAX_AGG_NUM_8197F) << BIT_SHIFT_MAX_AGG_NUM_8197F)
+#define BITS_MAX_AGG_NUM_8197F \
+ (BIT_MASK_MAX_AGG_NUM_8197F << BIT_SHIFT_MAX_AGG_NUM_8197F)
+#define BIT_CLEAR_MAX_AGG_NUM_8197F(x) ((x) & (~BITS_MAX_AGG_NUM_8197F))
+#define BIT_GET_MAX_AGG_NUM_8197F(x) \
+ (((x) >> BIT_SHIFT_MAX_AGG_NUM_8197F) & BIT_MASK_MAX_AGG_NUM_8197F)
+#define BIT_SET_MAX_AGG_NUM_8197F(x, v) \
+ (BIT_CLEAR_MAX_AGG_NUM_8197F(x) | BIT_MAX_AGG_NUM_8197F(v))
+
+#define BIT_SHIFT_RTS_TXTIME_TH_8197F 8
+#define BIT_MASK_RTS_TXTIME_TH_8197F 0xff
+#define BIT_RTS_TXTIME_TH_8197F(x) \
+ (((x) & BIT_MASK_RTS_TXTIME_TH_8197F) << BIT_SHIFT_RTS_TXTIME_TH_8197F)
+#define BITS_RTS_TXTIME_TH_8197F \
+ (BIT_MASK_RTS_TXTIME_TH_8197F << BIT_SHIFT_RTS_TXTIME_TH_8197F)
+#define BIT_CLEAR_RTS_TXTIME_TH_8197F(x) ((x) & (~BITS_RTS_TXTIME_TH_8197F))
+#define BIT_GET_RTS_TXTIME_TH_8197F(x) \
+ (((x) >> BIT_SHIFT_RTS_TXTIME_TH_8197F) & BIT_MASK_RTS_TXTIME_TH_8197F)
+#define BIT_SET_RTS_TXTIME_TH_8197F(x, v) \
+ (BIT_CLEAR_RTS_TXTIME_TH_8197F(x) | BIT_RTS_TXTIME_TH_8197F(v))
+
+#define BIT_SHIFT_RTS_LEN_TH_8197F 0
+#define BIT_MASK_RTS_LEN_TH_8197F 0xff
+#define BIT_RTS_LEN_TH_8197F(x) \
+ (((x) & BIT_MASK_RTS_LEN_TH_8197F) << BIT_SHIFT_RTS_LEN_TH_8197F)
+#define BITS_RTS_LEN_TH_8197F \
+ (BIT_MASK_RTS_LEN_TH_8197F << BIT_SHIFT_RTS_LEN_TH_8197F)
+#define BIT_CLEAR_RTS_LEN_TH_8197F(x) ((x) & (~BITS_RTS_LEN_TH_8197F))
+#define BIT_GET_RTS_LEN_TH_8197F(x) \
+ (((x) >> BIT_SHIFT_RTS_LEN_TH_8197F) & BIT_MASK_RTS_LEN_TH_8197F)
+#define BIT_SET_RTS_LEN_TH_8197F(x, v) \
+ (BIT_CLEAR_RTS_LEN_TH_8197F(x) | BIT_RTS_LEN_TH_8197F(v))
+
+/* 2 REG_BAR_MODE_CTRL_8197F */
+
+#define BIT_SHIFT_BAR_RTY_LMT_8197F 16
+#define BIT_MASK_BAR_RTY_LMT_8197F 0x3
+#define BIT_BAR_RTY_LMT_8197F(x) \
+ (((x) & BIT_MASK_BAR_RTY_LMT_8197F) << BIT_SHIFT_BAR_RTY_LMT_8197F)
+#define BITS_BAR_RTY_LMT_8197F \
+ (BIT_MASK_BAR_RTY_LMT_8197F << BIT_SHIFT_BAR_RTY_LMT_8197F)
+#define BIT_CLEAR_BAR_RTY_LMT_8197F(x) ((x) & (~BITS_BAR_RTY_LMT_8197F))
+#define BIT_GET_BAR_RTY_LMT_8197F(x) \
+ (((x) >> BIT_SHIFT_BAR_RTY_LMT_8197F) & BIT_MASK_BAR_RTY_LMT_8197F)
+#define BIT_SET_BAR_RTY_LMT_8197F(x, v) \
+ (BIT_CLEAR_BAR_RTY_LMT_8197F(x) | BIT_BAR_RTY_LMT_8197F(v))
+
+#define BIT_SHIFT_BAR_PKT_TXTIME_TH_8197F 8
+#define BIT_MASK_BAR_PKT_TXTIME_TH_8197F 0xff
+#define BIT_BAR_PKT_TXTIME_TH_8197F(x) \
+ (((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8197F) \
+ << BIT_SHIFT_BAR_PKT_TXTIME_TH_8197F)
+#define BITS_BAR_PKT_TXTIME_TH_8197F \
+ (BIT_MASK_BAR_PKT_TXTIME_TH_8197F << BIT_SHIFT_BAR_PKT_TXTIME_TH_8197F)
+#define BIT_CLEAR_BAR_PKT_TXTIME_TH_8197F(x) \
+ ((x) & (~BITS_BAR_PKT_TXTIME_TH_8197F))
+#define BIT_GET_BAR_PKT_TXTIME_TH_8197F(x) \
+ (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8197F) & \
+ BIT_MASK_BAR_PKT_TXTIME_TH_8197F)
+#define BIT_SET_BAR_PKT_TXTIME_TH_8197F(x, v) \
+ (BIT_CLEAR_BAR_PKT_TXTIME_TH_8197F(x) | BIT_BAR_PKT_TXTIME_TH_8197F(v))
+
+#define BIT_BAR_EN_V1_8197F BIT(6)
+
+#define BIT_SHIFT_BAR_PKTNUM_TH_V1_8197F 0
+#define BIT_MASK_BAR_PKTNUM_TH_V1_8197F 0x3f
+#define BIT_BAR_PKTNUM_TH_V1_8197F(x) \
+ (((x) & BIT_MASK_BAR_PKTNUM_TH_V1_8197F) \
+ << BIT_SHIFT_BAR_PKTNUM_TH_V1_8197F)
+#define BITS_BAR_PKTNUM_TH_V1_8197F \
+ (BIT_MASK_BAR_PKTNUM_TH_V1_8197F << BIT_SHIFT_BAR_PKTNUM_TH_V1_8197F)
+#define BIT_CLEAR_BAR_PKTNUM_TH_V1_8197F(x) \
+ ((x) & (~BITS_BAR_PKTNUM_TH_V1_8197F))
+#define BIT_GET_BAR_PKTNUM_TH_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8197F) & \
+ BIT_MASK_BAR_PKTNUM_TH_V1_8197F)
+#define BIT_SET_BAR_PKTNUM_TH_V1_8197F(x, v) \
+ (BIT_CLEAR_BAR_PKTNUM_TH_V1_8197F(x) | BIT_BAR_PKTNUM_TH_V1_8197F(v))
+
+/* 2 REG_RA_TRY_RATE_AGG_LMT_8197F */
+
+#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8197F 0
+#define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8197F 0x3f
+#define BIT_RA_TRY_RATE_AGG_LMT_V1_8197F(x) \
+ (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8197F) \
+ << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8197F)
+#define BITS_RA_TRY_RATE_AGG_LMT_V1_8197F \
+ (BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8197F \
+ << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8197F)
+#define BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8197F(x) \
+ ((x) & (~BITS_RA_TRY_RATE_AGG_LMT_V1_8197F))
+#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8197F) & \
+ BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8197F)
+#define BIT_SET_RA_TRY_RATE_AGG_LMT_V1_8197F(x, v) \
+ (BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8197F(x) | \
+ BIT_RA_TRY_RATE_AGG_LMT_V1_8197F(v))
+
+/* 2 REG_MACID_SLEEP2_8197F */
+
+#define BIT_SHIFT_MACID95_64PKTSLEEP_8197F 0
+#define BIT_MASK_MACID95_64PKTSLEEP_8197F 0xffffffffL
+#define BIT_MACID95_64PKTSLEEP_8197F(x) \
+ (((x) & BIT_MASK_MACID95_64PKTSLEEP_8197F) \
+ << BIT_SHIFT_MACID95_64PKTSLEEP_8197F)
+#define BITS_MACID95_64PKTSLEEP_8197F \
+ (BIT_MASK_MACID95_64PKTSLEEP_8197F \
+ << BIT_SHIFT_MACID95_64PKTSLEEP_8197F)
+#define BIT_CLEAR_MACID95_64PKTSLEEP_8197F(x) \
+ ((x) & (~BITS_MACID95_64PKTSLEEP_8197F))
+#define BIT_GET_MACID95_64PKTSLEEP_8197F(x) \
+ (((x) >> BIT_SHIFT_MACID95_64PKTSLEEP_8197F) & \
+ BIT_MASK_MACID95_64PKTSLEEP_8197F)
+#define BIT_SET_MACID95_64PKTSLEEP_8197F(x, v) \
+ (BIT_CLEAR_MACID95_64PKTSLEEP_8197F(x) | \
+ BIT_MACID95_64PKTSLEEP_8197F(v))
+
+/* 2 REG_MACID_SLEEP_8197F */
+
+#define BIT_SHIFT_MACID31_0_PKTSLEEP_8197F 0
+#define BIT_MASK_MACID31_0_PKTSLEEP_8197F 0xffffffffL
+#define BIT_MACID31_0_PKTSLEEP_8197F(x) \
+ (((x) & BIT_MASK_MACID31_0_PKTSLEEP_8197F) \
+ << BIT_SHIFT_MACID31_0_PKTSLEEP_8197F)
+#define BITS_MACID31_0_PKTSLEEP_8197F \
+ (BIT_MASK_MACID31_0_PKTSLEEP_8197F \
+ << BIT_SHIFT_MACID31_0_PKTSLEEP_8197F)
+#define BIT_CLEAR_MACID31_0_PKTSLEEP_8197F(x) \
+ ((x) & (~BITS_MACID31_0_PKTSLEEP_8197F))
+#define BIT_GET_MACID31_0_PKTSLEEP_8197F(x) \
+ (((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP_8197F) & \
+ BIT_MASK_MACID31_0_PKTSLEEP_8197F)
+#define BIT_SET_MACID31_0_PKTSLEEP_8197F(x, v) \
+ (BIT_CLEAR_MACID31_0_PKTSLEEP_8197F(x) | \
+ BIT_MACID31_0_PKTSLEEP_8197F(v))
+
+/* 2 REG_HW_SEQ0_8197F */
+
+#define BIT_SHIFT_HW_SSN_SEQ0_8197F 0
+#define BIT_MASK_HW_SSN_SEQ0_8197F 0xfff
+#define BIT_HW_SSN_SEQ0_8197F(x) \
+ (((x) & BIT_MASK_HW_SSN_SEQ0_8197F) << BIT_SHIFT_HW_SSN_SEQ0_8197F)
+#define BITS_HW_SSN_SEQ0_8197F \
+ (BIT_MASK_HW_SSN_SEQ0_8197F << BIT_SHIFT_HW_SSN_SEQ0_8197F)
+#define BIT_CLEAR_HW_SSN_SEQ0_8197F(x) ((x) & (~BITS_HW_SSN_SEQ0_8197F))
+#define BIT_GET_HW_SSN_SEQ0_8197F(x) \
+ (((x) >> BIT_SHIFT_HW_SSN_SEQ0_8197F) & BIT_MASK_HW_SSN_SEQ0_8197F)
+#define BIT_SET_HW_SSN_SEQ0_8197F(x, v) \
+ (BIT_CLEAR_HW_SSN_SEQ0_8197F(x) | BIT_HW_SSN_SEQ0_8197F(v))
+
+/* 2 REG_HW_SEQ1_8197F */
+
+#define BIT_SHIFT_HW_SSN_SEQ1_8197F 0
+#define BIT_MASK_HW_SSN_SEQ1_8197F 0xfff
+#define BIT_HW_SSN_SEQ1_8197F(x) \
+ (((x) & BIT_MASK_HW_SSN_SEQ1_8197F) << BIT_SHIFT_HW_SSN_SEQ1_8197F)
+#define BITS_HW_SSN_SEQ1_8197F \
+ (BIT_MASK_HW_SSN_SEQ1_8197F << BIT_SHIFT_HW_SSN_SEQ1_8197F)
+#define BIT_CLEAR_HW_SSN_SEQ1_8197F(x) ((x) & (~BITS_HW_SSN_SEQ1_8197F))
+#define BIT_GET_HW_SSN_SEQ1_8197F(x) \
+ (((x) >> BIT_SHIFT_HW_SSN_SEQ1_8197F) & BIT_MASK_HW_SSN_SEQ1_8197F)
+#define BIT_SET_HW_SSN_SEQ1_8197F(x, v) \
+ (BIT_CLEAR_HW_SSN_SEQ1_8197F(x) | BIT_HW_SSN_SEQ1_8197F(v))
+
+/* 2 REG_HW_SEQ2_8197F */
+
+#define BIT_SHIFT_HW_SSN_SEQ2_8197F 0
+#define BIT_MASK_HW_SSN_SEQ2_8197F 0xfff
+#define BIT_HW_SSN_SEQ2_8197F(x) \
+ (((x) & BIT_MASK_HW_SSN_SEQ2_8197F) << BIT_SHIFT_HW_SSN_SEQ2_8197F)
+#define BITS_HW_SSN_SEQ2_8197F \
+ (BIT_MASK_HW_SSN_SEQ2_8197F << BIT_SHIFT_HW_SSN_SEQ2_8197F)
+#define BIT_CLEAR_HW_SSN_SEQ2_8197F(x) ((x) & (~BITS_HW_SSN_SEQ2_8197F))
+#define BIT_GET_HW_SSN_SEQ2_8197F(x) \
+ (((x) >> BIT_SHIFT_HW_SSN_SEQ2_8197F) & BIT_MASK_HW_SSN_SEQ2_8197F)
+#define BIT_SET_HW_SSN_SEQ2_8197F(x, v) \
+ (BIT_CLEAR_HW_SSN_SEQ2_8197F(x) | BIT_HW_SSN_SEQ2_8197F(v))
+
+/* 2 REG_HW_SEQ3_8197F */
+
+#define BIT_SHIFT_CSI_HWSSN_SEL_8197F 12
+#define BIT_MASK_CSI_HWSSN_SEL_8197F 0x3
+#define BIT_CSI_HWSSN_SEL_8197F(x) \
+ (((x) & BIT_MASK_CSI_HWSSN_SEL_8197F) << BIT_SHIFT_CSI_HWSSN_SEL_8197F)
+#define BITS_CSI_HWSSN_SEL_8197F \
+ (BIT_MASK_CSI_HWSSN_SEL_8197F << BIT_SHIFT_CSI_HWSSN_SEL_8197F)
+#define BIT_CLEAR_CSI_HWSSN_SEL_8197F(x) ((x) & (~BITS_CSI_HWSSN_SEL_8197F))
+#define BIT_GET_CSI_HWSSN_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_CSI_HWSSN_SEL_8197F) & BIT_MASK_CSI_HWSSN_SEL_8197F)
+#define BIT_SET_CSI_HWSSN_SEL_8197F(x, v) \
+ (BIT_CLEAR_CSI_HWSSN_SEL_8197F(x) | BIT_CSI_HWSSN_SEL_8197F(v))
+
+#define BIT_SHIFT_HW_SSN_SEQ3_8197F 0
+#define BIT_MASK_HW_SSN_SEQ3_8197F 0xfff
+#define BIT_HW_SSN_SEQ3_8197F(x) \
+ (((x) & BIT_MASK_HW_SSN_SEQ3_8197F) << BIT_SHIFT_HW_SSN_SEQ3_8197F)
+#define BITS_HW_SSN_SEQ3_8197F \
+ (BIT_MASK_HW_SSN_SEQ3_8197F << BIT_SHIFT_HW_SSN_SEQ3_8197F)
+#define BIT_CLEAR_HW_SSN_SEQ3_8197F(x) ((x) & (~BITS_HW_SSN_SEQ3_8197F))
+#define BIT_GET_HW_SSN_SEQ3_8197F(x) \
+ (((x) >> BIT_SHIFT_HW_SSN_SEQ3_8197F) & BIT_MASK_HW_SSN_SEQ3_8197F)
+#define BIT_SET_HW_SSN_SEQ3_8197F(x, v) \
+ (BIT_CLEAR_HW_SSN_SEQ3_8197F(x) | BIT_HW_SSN_SEQ3_8197F(v))
+
+/* 2 REG_NULL_PKT_STATUS_V1_8197F */
+
+#define BIT_SHIFT_PTCL_TOTAL_PG_V1_8197F 2
+#define BIT_MASK_PTCL_TOTAL_PG_V1_8197F 0x1fff
+#define BIT_PTCL_TOTAL_PG_V1_8197F(x) \
+ (((x) & BIT_MASK_PTCL_TOTAL_PG_V1_8197F) \
+ << BIT_SHIFT_PTCL_TOTAL_PG_V1_8197F)
+#define BITS_PTCL_TOTAL_PG_V1_8197F \
+ (BIT_MASK_PTCL_TOTAL_PG_V1_8197F << BIT_SHIFT_PTCL_TOTAL_PG_V1_8197F)
+#define BIT_CLEAR_PTCL_TOTAL_PG_V1_8197F(x) \
+ ((x) & (~BITS_PTCL_TOTAL_PG_V1_8197F))
+#define BIT_GET_PTCL_TOTAL_PG_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V1_8197F) & \
+ BIT_MASK_PTCL_TOTAL_PG_V1_8197F)
+#define BIT_SET_PTCL_TOTAL_PG_V1_8197F(x, v) \
+ (BIT_CLEAR_PTCL_TOTAL_PG_V1_8197F(x) | BIT_PTCL_TOTAL_PG_V1_8197F(v))
+
+#define BIT_TX_NULL_1_8197F BIT(1)
+#define BIT_TX_NULL_0_8197F BIT(0)
+
+/* 2 REG_PTCL_ERR_STATUS_8197F */
+#define BIT_PTCL_RATE_TABLE_INVALID_8197F BIT(7)
+#define BIT_FTM_T2R_ERROR_8197F BIT(6)
+#define BIT_PTCL_ERR0_8197F BIT(5)
+#define BIT_PTCL_ERR1_8197F BIT(4)
+#define BIT_PTCL_ERR2_8197F BIT(3)
+#define BIT_PTCL_ERR3_8197F BIT(2)
+#define BIT_PTCL_ERR4_8197F BIT(1)
+#define BIT_PTCL_ERR5_8197F BIT(0)
+
+/* 2 REG_NULL_PKT_STATUS_EXTEND_8197F */
+#define BIT_CLI3_TX_NULL_1_8197F BIT(7)
+#define BIT_CLI3_TX_NULL_0_8197F BIT(6)
+#define BIT_CLI2_TX_NULL_1_8197F BIT(5)
+#define BIT_CLI2_TX_NULL_0_8197F BIT(4)
+#define BIT_CLI1_TX_NULL_1_8197F BIT(3)
+#define BIT_CLI1_TX_NULL_0_8197F BIT(2)
+#define BIT_CLI0_TX_NULL_1_8197F BIT(1)
+#define BIT_CLI0_TX_NULL_0_8197F BIT(0)
+
+/* 2 REG_VIDEO_ENHANCEMENT_FUN_8197F */
+#define BIT_VIDEO_JUST_DROP_8197F BIT(1)
+#define BIT_VIDEO_ENHANCEMENT_FUN_EN_8197F BIT(0)
+
+/* 2 REG_BT_POLLUTE_PKT_CNT_8197F */
+
+#define BIT_SHIFT_BT_POLLUTE_PKT_CNT_8197F 0
+#define BIT_MASK_BT_POLLUTE_PKT_CNT_8197F 0xffff
+#define BIT_BT_POLLUTE_PKT_CNT_8197F(x) \
+ (((x) & BIT_MASK_BT_POLLUTE_PKT_CNT_8197F) \
+ << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8197F)
+#define BITS_BT_POLLUTE_PKT_CNT_8197F \
+ (BIT_MASK_BT_POLLUTE_PKT_CNT_8197F \
+ << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8197F)
+#define BIT_CLEAR_BT_POLLUTE_PKT_CNT_8197F(x) \
+ ((x) & (~BITS_BT_POLLUTE_PKT_CNT_8197F))
+#define BIT_GET_BT_POLLUTE_PKT_CNT_8197F(x) \
+ (((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT_8197F) & \
+ BIT_MASK_BT_POLLUTE_PKT_CNT_8197F)
+#define BIT_SET_BT_POLLUTE_PKT_CNT_8197F(x, v) \
+ (BIT_CLEAR_BT_POLLUTE_PKT_CNT_8197F(x) | \
+ BIT_BT_POLLUTE_PKT_CNT_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_PTCL_DBG_8197F */
+
+#define BIT_SHIFT_PTCL_DBG_8197F 0
+#define BIT_MASK_PTCL_DBG_8197F 0xffffffffL
+#define BIT_PTCL_DBG_8197F(x) \
+ (((x) & BIT_MASK_PTCL_DBG_8197F) << BIT_SHIFT_PTCL_DBG_8197F)
+#define BITS_PTCL_DBG_8197F \
+ (BIT_MASK_PTCL_DBG_8197F << BIT_SHIFT_PTCL_DBG_8197F)
+#define BIT_CLEAR_PTCL_DBG_8197F(x) ((x) & (~BITS_PTCL_DBG_8197F))
+#define BIT_GET_PTCL_DBG_8197F(x) \
+ (((x) >> BIT_SHIFT_PTCL_DBG_8197F) & BIT_MASK_PTCL_DBG_8197F)
+#define BIT_SET_PTCL_DBG_8197F(x, v) \
+ (BIT_CLEAR_PTCL_DBG_8197F(x) | BIT_PTCL_DBG_8197F(v))
+
+/* 2 REG_TXOP_EXTRA_CTRL_8197F */
+#define BIT_TXOP_EFFICIENCY_EN_8197F BIT(0)
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_CPUMGQ_TIMER_CTRL2_8197F */
+
+#define BIT_SHIFT_TRI_HEAD_ADDR_8197F 16
+#define BIT_MASK_TRI_HEAD_ADDR_8197F 0xfff
+#define BIT_TRI_HEAD_ADDR_8197F(x) \
+ (((x) & BIT_MASK_TRI_HEAD_ADDR_8197F) << BIT_SHIFT_TRI_HEAD_ADDR_8197F)
+#define BITS_TRI_HEAD_ADDR_8197F \
+ (BIT_MASK_TRI_HEAD_ADDR_8197F << BIT_SHIFT_TRI_HEAD_ADDR_8197F)
+#define BIT_CLEAR_TRI_HEAD_ADDR_8197F(x) ((x) & (~BITS_TRI_HEAD_ADDR_8197F))
+#define BIT_GET_TRI_HEAD_ADDR_8197F(x) \
+ (((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8197F) & BIT_MASK_TRI_HEAD_ADDR_8197F)
+#define BIT_SET_TRI_HEAD_ADDR_8197F(x, v) \
+ (BIT_CLEAR_TRI_HEAD_ADDR_8197F(x) | BIT_TRI_HEAD_ADDR_8197F(v))
+
+#define BIT_DROP_TH_EN_8197F BIT(8)
+
+#define BIT_SHIFT_DROP_TH_8197F 0
+#define BIT_MASK_DROP_TH_8197F 0xff
+#define BIT_DROP_TH_8197F(x) \
+ (((x) & BIT_MASK_DROP_TH_8197F) << BIT_SHIFT_DROP_TH_8197F)
+#define BITS_DROP_TH_8197F (BIT_MASK_DROP_TH_8197F << BIT_SHIFT_DROP_TH_8197F)
+#define BIT_CLEAR_DROP_TH_8197F(x) ((x) & (~BITS_DROP_TH_8197F))
+#define BIT_GET_DROP_TH_8197F(x) \
+ (((x) >> BIT_SHIFT_DROP_TH_8197F) & BIT_MASK_DROP_TH_8197F)
+#define BIT_SET_DROP_TH_8197F(x, v) \
+ (BIT_CLEAR_DROP_TH_8197F(x) | BIT_DROP_TH_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_DUMMY_PAGE4_8197F */
+#define BIT_MOREDATA_CTRL2_EN_V2_8197F BIT(19)
+#define BIT_MOREDATA_CTRL1_EN_V2_8197F BIT(18)
+#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE_8197F BIT(16)
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_Q0_Q1_INFO_8197F */
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8197F BIT(31)
+
+#define BIT_SHIFT_GTAB_ID_8197F 28
+#define BIT_MASK_GTAB_ID_8197F 0x7
+#define BIT_GTAB_ID_8197F(x) \
+ (((x) & BIT_MASK_GTAB_ID_8197F) << BIT_SHIFT_GTAB_ID_8197F)
+#define BITS_GTAB_ID_8197F (BIT_MASK_GTAB_ID_8197F << BIT_SHIFT_GTAB_ID_8197F)
+#define BIT_CLEAR_GTAB_ID_8197F(x) ((x) & (~BITS_GTAB_ID_8197F))
+#define BIT_GET_GTAB_ID_8197F(x) \
+ (((x) >> BIT_SHIFT_GTAB_ID_8197F) & BIT_MASK_GTAB_ID_8197F)
+#define BIT_SET_GTAB_ID_8197F(x, v) \
+ (BIT_CLEAR_GTAB_ID_8197F(x) | BIT_GTAB_ID_8197F(v))
+
+#define BIT_SHIFT_AC1_PKT_INFO_8197F 16
+#define BIT_MASK_AC1_PKT_INFO_8197F 0xfff
+#define BIT_AC1_PKT_INFO_8197F(x) \
+ (((x) & BIT_MASK_AC1_PKT_INFO_8197F) << BIT_SHIFT_AC1_PKT_INFO_8197F)
+#define BITS_AC1_PKT_INFO_8197F \
+ (BIT_MASK_AC1_PKT_INFO_8197F << BIT_SHIFT_AC1_PKT_INFO_8197F)
+#define BIT_CLEAR_AC1_PKT_INFO_8197F(x) ((x) & (~BITS_AC1_PKT_INFO_8197F))
+#define BIT_GET_AC1_PKT_INFO_8197F(x) \
+ (((x) >> BIT_SHIFT_AC1_PKT_INFO_8197F) & BIT_MASK_AC1_PKT_INFO_8197F)
+#define BIT_SET_AC1_PKT_INFO_8197F(x, v) \
+ (BIT_CLEAR_AC1_PKT_INFO_8197F(x) | BIT_AC1_PKT_INFO_8197F(v))
+
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8197F BIT(15)
+
+#define BIT_SHIFT_GTAB_ID_V1_8197F 12
+#define BIT_MASK_GTAB_ID_V1_8197F 0x7
+#define BIT_GTAB_ID_V1_8197F(x) \
+ (((x) & BIT_MASK_GTAB_ID_V1_8197F) << BIT_SHIFT_GTAB_ID_V1_8197F)
+#define BITS_GTAB_ID_V1_8197F \
+ (BIT_MASK_GTAB_ID_V1_8197F << BIT_SHIFT_GTAB_ID_V1_8197F)
+#define BIT_CLEAR_GTAB_ID_V1_8197F(x) ((x) & (~BITS_GTAB_ID_V1_8197F))
+#define BIT_GET_GTAB_ID_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_GTAB_ID_V1_8197F) & BIT_MASK_GTAB_ID_V1_8197F)
+#define BIT_SET_GTAB_ID_V1_8197F(x, v) \
+ (BIT_CLEAR_GTAB_ID_V1_8197F(x) | BIT_GTAB_ID_V1_8197F(v))
+
+#define BIT_SHIFT_AC0_PKT_INFO_8197F 0
+#define BIT_MASK_AC0_PKT_INFO_8197F 0xfff
+#define BIT_AC0_PKT_INFO_8197F(x) \
+ (((x) & BIT_MASK_AC0_PKT_INFO_8197F) << BIT_SHIFT_AC0_PKT_INFO_8197F)
+#define BITS_AC0_PKT_INFO_8197F \
+ (BIT_MASK_AC0_PKT_INFO_8197F << BIT_SHIFT_AC0_PKT_INFO_8197F)
+#define BIT_CLEAR_AC0_PKT_INFO_8197F(x) ((x) & (~BITS_AC0_PKT_INFO_8197F))
+#define BIT_GET_AC0_PKT_INFO_8197F(x) \
+ (((x) >> BIT_SHIFT_AC0_PKT_INFO_8197F) & BIT_MASK_AC0_PKT_INFO_8197F)
+#define BIT_SET_AC0_PKT_INFO_8197F(x, v) \
+ (BIT_CLEAR_AC0_PKT_INFO_8197F(x) | BIT_AC0_PKT_INFO_8197F(v))
+
+/* 2 REG_Q2_Q3_INFO_8197F */
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8197F BIT(31)
+
+#define BIT_SHIFT_GTAB_ID_8197F 28
+#define BIT_MASK_GTAB_ID_8197F 0x7
+#define BIT_GTAB_ID_8197F(x) \
+ (((x) & BIT_MASK_GTAB_ID_8197F) << BIT_SHIFT_GTAB_ID_8197F)
+#define BITS_GTAB_ID_8197F (BIT_MASK_GTAB_ID_8197F << BIT_SHIFT_GTAB_ID_8197F)
+#define BIT_CLEAR_GTAB_ID_8197F(x) ((x) & (~BITS_GTAB_ID_8197F))
+#define BIT_GET_GTAB_ID_8197F(x) \
+ (((x) >> BIT_SHIFT_GTAB_ID_8197F) & BIT_MASK_GTAB_ID_8197F)
+#define BIT_SET_GTAB_ID_8197F(x, v) \
+ (BIT_CLEAR_GTAB_ID_8197F(x) | BIT_GTAB_ID_8197F(v))
+
+#define BIT_SHIFT_AC3_PKT_INFO_8197F 16
+#define BIT_MASK_AC3_PKT_INFO_8197F 0xfff
+#define BIT_AC3_PKT_INFO_8197F(x) \
+ (((x) & BIT_MASK_AC3_PKT_INFO_8197F) << BIT_SHIFT_AC3_PKT_INFO_8197F)
+#define BITS_AC3_PKT_INFO_8197F \
+ (BIT_MASK_AC3_PKT_INFO_8197F << BIT_SHIFT_AC3_PKT_INFO_8197F)
+#define BIT_CLEAR_AC3_PKT_INFO_8197F(x) ((x) & (~BITS_AC3_PKT_INFO_8197F))
+#define BIT_GET_AC3_PKT_INFO_8197F(x) \
+ (((x) >> BIT_SHIFT_AC3_PKT_INFO_8197F) & BIT_MASK_AC3_PKT_INFO_8197F)
+#define BIT_SET_AC3_PKT_INFO_8197F(x, v) \
+ (BIT_CLEAR_AC3_PKT_INFO_8197F(x) | BIT_AC3_PKT_INFO_8197F(v))
+
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8197F BIT(15)
+
+#define BIT_SHIFT_GTAB_ID_V1_8197F 12
+#define BIT_MASK_GTAB_ID_V1_8197F 0x7
+#define BIT_GTAB_ID_V1_8197F(x) \
+ (((x) & BIT_MASK_GTAB_ID_V1_8197F) << BIT_SHIFT_GTAB_ID_V1_8197F)
+#define BITS_GTAB_ID_V1_8197F \
+ (BIT_MASK_GTAB_ID_V1_8197F << BIT_SHIFT_GTAB_ID_V1_8197F)
+#define BIT_CLEAR_GTAB_ID_V1_8197F(x) ((x) & (~BITS_GTAB_ID_V1_8197F))
+#define BIT_GET_GTAB_ID_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_GTAB_ID_V1_8197F) & BIT_MASK_GTAB_ID_V1_8197F)
+#define BIT_SET_GTAB_ID_V1_8197F(x, v) \
+ (BIT_CLEAR_GTAB_ID_V1_8197F(x) | BIT_GTAB_ID_V1_8197F(v))
+
+#define BIT_SHIFT_AC2_PKT_INFO_8197F 0
+#define BIT_MASK_AC2_PKT_INFO_8197F 0xfff
+#define BIT_AC2_PKT_INFO_8197F(x) \
+ (((x) & BIT_MASK_AC2_PKT_INFO_8197F) << BIT_SHIFT_AC2_PKT_INFO_8197F)
+#define BITS_AC2_PKT_INFO_8197F \
+ (BIT_MASK_AC2_PKT_INFO_8197F << BIT_SHIFT_AC2_PKT_INFO_8197F)
+#define BIT_CLEAR_AC2_PKT_INFO_8197F(x) ((x) & (~BITS_AC2_PKT_INFO_8197F))
+#define BIT_GET_AC2_PKT_INFO_8197F(x) \
+ (((x) >> BIT_SHIFT_AC2_PKT_INFO_8197F) & BIT_MASK_AC2_PKT_INFO_8197F)
+#define BIT_SET_AC2_PKT_INFO_8197F(x, v) \
+ (BIT_CLEAR_AC2_PKT_INFO_8197F(x) | BIT_AC2_PKT_INFO_8197F(v))
+
+/* 2 REG_Q4_Q5_INFO_8197F */
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8197F BIT(31)
+
+#define BIT_SHIFT_GTAB_ID_8197F 28
+#define BIT_MASK_GTAB_ID_8197F 0x7
+#define BIT_GTAB_ID_8197F(x) \
+ (((x) & BIT_MASK_GTAB_ID_8197F) << BIT_SHIFT_GTAB_ID_8197F)
+#define BITS_GTAB_ID_8197F (BIT_MASK_GTAB_ID_8197F << BIT_SHIFT_GTAB_ID_8197F)
+#define BIT_CLEAR_GTAB_ID_8197F(x) ((x) & (~BITS_GTAB_ID_8197F))
+#define BIT_GET_GTAB_ID_8197F(x) \
+ (((x) >> BIT_SHIFT_GTAB_ID_8197F) & BIT_MASK_GTAB_ID_8197F)
+#define BIT_SET_GTAB_ID_8197F(x, v) \
+ (BIT_CLEAR_GTAB_ID_8197F(x) | BIT_GTAB_ID_8197F(v))
+
+#define BIT_SHIFT_AC5_PKT_INFO_8197F 16
+#define BIT_MASK_AC5_PKT_INFO_8197F 0xfff
+#define BIT_AC5_PKT_INFO_8197F(x) \
+ (((x) & BIT_MASK_AC5_PKT_INFO_8197F) << BIT_SHIFT_AC5_PKT_INFO_8197F)
+#define BITS_AC5_PKT_INFO_8197F \
+ (BIT_MASK_AC5_PKT_INFO_8197F << BIT_SHIFT_AC5_PKT_INFO_8197F)
+#define BIT_CLEAR_AC5_PKT_INFO_8197F(x) ((x) & (~BITS_AC5_PKT_INFO_8197F))
+#define BIT_GET_AC5_PKT_INFO_8197F(x) \
+ (((x) >> BIT_SHIFT_AC5_PKT_INFO_8197F) & BIT_MASK_AC5_PKT_INFO_8197F)
+#define BIT_SET_AC5_PKT_INFO_8197F(x, v) \
+ (BIT_CLEAR_AC5_PKT_INFO_8197F(x) | BIT_AC5_PKT_INFO_8197F(v))
+
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8197F BIT(15)
+
+#define BIT_SHIFT_GTAB_ID_V1_8197F 12
+#define BIT_MASK_GTAB_ID_V1_8197F 0x7
+#define BIT_GTAB_ID_V1_8197F(x) \
+ (((x) & BIT_MASK_GTAB_ID_V1_8197F) << BIT_SHIFT_GTAB_ID_V1_8197F)
+#define BITS_GTAB_ID_V1_8197F \
+ (BIT_MASK_GTAB_ID_V1_8197F << BIT_SHIFT_GTAB_ID_V1_8197F)
+#define BIT_CLEAR_GTAB_ID_V1_8197F(x) ((x) & (~BITS_GTAB_ID_V1_8197F))
+#define BIT_GET_GTAB_ID_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_GTAB_ID_V1_8197F) & BIT_MASK_GTAB_ID_V1_8197F)
+#define BIT_SET_GTAB_ID_V1_8197F(x, v) \
+ (BIT_CLEAR_GTAB_ID_V1_8197F(x) | BIT_GTAB_ID_V1_8197F(v))
+
+#define BIT_SHIFT_AC4_PKT_INFO_8197F 0
+#define BIT_MASK_AC4_PKT_INFO_8197F 0xfff
+#define BIT_AC4_PKT_INFO_8197F(x) \
+ (((x) & BIT_MASK_AC4_PKT_INFO_8197F) << BIT_SHIFT_AC4_PKT_INFO_8197F)
+#define BITS_AC4_PKT_INFO_8197F \
+ (BIT_MASK_AC4_PKT_INFO_8197F << BIT_SHIFT_AC4_PKT_INFO_8197F)
+#define BIT_CLEAR_AC4_PKT_INFO_8197F(x) ((x) & (~BITS_AC4_PKT_INFO_8197F))
+#define BIT_GET_AC4_PKT_INFO_8197F(x) \
+ (((x) >> BIT_SHIFT_AC4_PKT_INFO_8197F) & BIT_MASK_AC4_PKT_INFO_8197F)
+#define BIT_SET_AC4_PKT_INFO_8197F(x, v) \
+ (BIT_CLEAR_AC4_PKT_INFO_8197F(x) | BIT_AC4_PKT_INFO_8197F(v))
+
+/* 2 REG_Q6_Q7_INFO_8197F */
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8197F BIT(31)
+
+#define BIT_SHIFT_GTAB_ID_8197F 28
+#define BIT_MASK_GTAB_ID_8197F 0x7
+#define BIT_GTAB_ID_8197F(x) \
+ (((x) & BIT_MASK_GTAB_ID_8197F) << BIT_SHIFT_GTAB_ID_8197F)
+#define BITS_GTAB_ID_8197F (BIT_MASK_GTAB_ID_8197F << BIT_SHIFT_GTAB_ID_8197F)
+#define BIT_CLEAR_GTAB_ID_8197F(x) ((x) & (~BITS_GTAB_ID_8197F))
+#define BIT_GET_GTAB_ID_8197F(x) \
+ (((x) >> BIT_SHIFT_GTAB_ID_8197F) & BIT_MASK_GTAB_ID_8197F)
+#define BIT_SET_GTAB_ID_8197F(x, v) \
+ (BIT_CLEAR_GTAB_ID_8197F(x) | BIT_GTAB_ID_8197F(v))
+
+#define BIT_SHIFT_AC7_PKT_INFO_8197F 16
+#define BIT_MASK_AC7_PKT_INFO_8197F 0xfff
+#define BIT_AC7_PKT_INFO_8197F(x) \
+ (((x) & BIT_MASK_AC7_PKT_INFO_8197F) << BIT_SHIFT_AC7_PKT_INFO_8197F)
+#define BITS_AC7_PKT_INFO_8197F \
+ (BIT_MASK_AC7_PKT_INFO_8197F << BIT_SHIFT_AC7_PKT_INFO_8197F)
+#define BIT_CLEAR_AC7_PKT_INFO_8197F(x) ((x) & (~BITS_AC7_PKT_INFO_8197F))
+#define BIT_GET_AC7_PKT_INFO_8197F(x) \
+ (((x) >> BIT_SHIFT_AC7_PKT_INFO_8197F) & BIT_MASK_AC7_PKT_INFO_8197F)
+#define BIT_SET_AC7_PKT_INFO_8197F(x, v) \
+ (BIT_CLEAR_AC7_PKT_INFO_8197F(x) | BIT_AC7_PKT_INFO_8197F(v))
+
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8197F BIT(15)
+
+#define BIT_SHIFT_GTAB_ID_V1_8197F 12
+#define BIT_MASK_GTAB_ID_V1_8197F 0x7
+#define BIT_GTAB_ID_V1_8197F(x) \
+ (((x) & BIT_MASK_GTAB_ID_V1_8197F) << BIT_SHIFT_GTAB_ID_V1_8197F)
+#define BITS_GTAB_ID_V1_8197F \
+ (BIT_MASK_GTAB_ID_V1_8197F << BIT_SHIFT_GTAB_ID_V1_8197F)
+#define BIT_CLEAR_GTAB_ID_V1_8197F(x) ((x) & (~BITS_GTAB_ID_V1_8197F))
+#define BIT_GET_GTAB_ID_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_GTAB_ID_V1_8197F) & BIT_MASK_GTAB_ID_V1_8197F)
+#define BIT_SET_GTAB_ID_V1_8197F(x, v) \
+ (BIT_CLEAR_GTAB_ID_V1_8197F(x) | BIT_GTAB_ID_V1_8197F(v))
+
+#define BIT_SHIFT_AC6_PKT_INFO_8197F 0
+#define BIT_MASK_AC6_PKT_INFO_8197F 0xfff
+#define BIT_AC6_PKT_INFO_8197F(x) \
+ (((x) & BIT_MASK_AC6_PKT_INFO_8197F) << BIT_SHIFT_AC6_PKT_INFO_8197F)
+#define BITS_AC6_PKT_INFO_8197F \
+ (BIT_MASK_AC6_PKT_INFO_8197F << BIT_SHIFT_AC6_PKT_INFO_8197F)
+#define BIT_CLEAR_AC6_PKT_INFO_8197F(x) ((x) & (~BITS_AC6_PKT_INFO_8197F))
+#define BIT_GET_AC6_PKT_INFO_8197F(x) \
+ (((x) >> BIT_SHIFT_AC6_PKT_INFO_8197F) & BIT_MASK_AC6_PKT_INFO_8197F)
+#define BIT_SET_AC6_PKT_INFO_8197F(x, v) \
+ (BIT_CLEAR_AC6_PKT_INFO_8197F(x) | BIT_AC6_PKT_INFO_8197F(v))
+
+/* 2 REG_MGQ_HIQ_INFO_8197F */
+
+#define BIT_SHIFT_HIQ_PKT_INFO_8197F 16
+#define BIT_MASK_HIQ_PKT_INFO_8197F 0xfff
+#define BIT_HIQ_PKT_INFO_8197F(x) \
+ (((x) & BIT_MASK_HIQ_PKT_INFO_8197F) << BIT_SHIFT_HIQ_PKT_INFO_8197F)
+#define BITS_HIQ_PKT_INFO_8197F \
+ (BIT_MASK_HIQ_PKT_INFO_8197F << BIT_SHIFT_HIQ_PKT_INFO_8197F)
+#define BIT_CLEAR_HIQ_PKT_INFO_8197F(x) ((x) & (~BITS_HIQ_PKT_INFO_8197F))
+#define BIT_GET_HIQ_PKT_INFO_8197F(x) \
+ (((x) >> BIT_SHIFT_HIQ_PKT_INFO_8197F) & BIT_MASK_HIQ_PKT_INFO_8197F)
+#define BIT_SET_HIQ_PKT_INFO_8197F(x, v) \
+ (BIT_CLEAR_HIQ_PKT_INFO_8197F(x) | BIT_HIQ_PKT_INFO_8197F(v))
+
+#define BIT_SHIFT_MGQ_PKT_INFO_8197F 0
+#define BIT_MASK_MGQ_PKT_INFO_8197F 0xfff
+#define BIT_MGQ_PKT_INFO_8197F(x) \
+ (((x) & BIT_MASK_MGQ_PKT_INFO_8197F) << BIT_SHIFT_MGQ_PKT_INFO_8197F)
+#define BITS_MGQ_PKT_INFO_8197F \
+ (BIT_MASK_MGQ_PKT_INFO_8197F << BIT_SHIFT_MGQ_PKT_INFO_8197F)
+#define BIT_CLEAR_MGQ_PKT_INFO_8197F(x) ((x) & (~BITS_MGQ_PKT_INFO_8197F))
+#define BIT_GET_MGQ_PKT_INFO_8197F(x) \
+ (((x) >> BIT_SHIFT_MGQ_PKT_INFO_8197F) & BIT_MASK_MGQ_PKT_INFO_8197F)
+#define BIT_SET_MGQ_PKT_INFO_8197F(x, v) \
+ (BIT_CLEAR_MGQ_PKT_INFO_8197F(x) | BIT_MGQ_PKT_INFO_8197F(v))
+
+/* 2 REG_CMDQ_BCNQ_INFO_8197F */
+
+#define BIT_SHIFT_BCNQ_PKT_INFO_V1_8197F 16
+#define BIT_MASK_BCNQ_PKT_INFO_V1_8197F 0xfff
+#define BIT_BCNQ_PKT_INFO_V1_8197F(x) \
+ (((x) & BIT_MASK_BCNQ_PKT_INFO_V1_8197F) \
+ << BIT_SHIFT_BCNQ_PKT_INFO_V1_8197F)
+#define BITS_BCNQ_PKT_INFO_V1_8197F \
+ (BIT_MASK_BCNQ_PKT_INFO_V1_8197F << BIT_SHIFT_BCNQ_PKT_INFO_V1_8197F)
+#define BIT_CLEAR_BCNQ_PKT_INFO_V1_8197F(x) \
+ ((x) & (~BITS_BCNQ_PKT_INFO_V1_8197F))
+#define BIT_GET_BCNQ_PKT_INFO_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_BCNQ_PKT_INFO_V1_8197F) & \
+ BIT_MASK_BCNQ_PKT_INFO_V1_8197F)
+#define BIT_SET_BCNQ_PKT_INFO_V1_8197F(x, v) \
+ (BIT_CLEAR_BCNQ_PKT_INFO_V1_8197F(x) | BIT_BCNQ_PKT_INFO_V1_8197F(v))
+
+#define BIT_SHIFT_CMDQ_PKT_INFO_V1_8197F 0
+#define BIT_MASK_CMDQ_PKT_INFO_V1_8197F 0xfff
+#define BIT_CMDQ_PKT_INFO_V1_8197F(x) \
+ (((x) & BIT_MASK_CMDQ_PKT_INFO_V1_8197F) \
+ << BIT_SHIFT_CMDQ_PKT_INFO_V1_8197F)
+#define BITS_CMDQ_PKT_INFO_V1_8197F \
+ (BIT_MASK_CMDQ_PKT_INFO_V1_8197F << BIT_SHIFT_CMDQ_PKT_INFO_V1_8197F)
+#define BIT_CLEAR_CMDQ_PKT_INFO_V1_8197F(x) \
+ ((x) & (~BITS_CMDQ_PKT_INFO_V1_8197F))
+#define BIT_GET_CMDQ_PKT_INFO_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_CMDQ_PKT_INFO_V1_8197F) & \
+ BIT_MASK_CMDQ_PKT_INFO_V1_8197F)
+#define BIT_SET_CMDQ_PKT_INFO_V1_8197F(x, v) \
+ (BIT_CLEAR_CMDQ_PKT_INFO_V1_8197F(x) | BIT_CMDQ_PKT_INFO_V1_8197F(v))
+
+/* 2 REG_USEREG_SETTING_8197F */
+#define BIT_NDPA_USEREG_8197F BIT(21)
+
+#define BIT_SHIFT_RETRY_USEREG_8197F 19
+#define BIT_MASK_RETRY_USEREG_8197F 0x3
+#define BIT_RETRY_USEREG_8197F(x) \
+ (((x) & BIT_MASK_RETRY_USEREG_8197F) << BIT_SHIFT_RETRY_USEREG_8197F)
+#define BITS_RETRY_USEREG_8197F \
+ (BIT_MASK_RETRY_USEREG_8197F << BIT_SHIFT_RETRY_USEREG_8197F)
+#define BIT_CLEAR_RETRY_USEREG_8197F(x) ((x) & (~BITS_RETRY_USEREG_8197F))
+#define BIT_GET_RETRY_USEREG_8197F(x) \
+ (((x) >> BIT_SHIFT_RETRY_USEREG_8197F) & BIT_MASK_RETRY_USEREG_8197F)
+#define BIT_SET_RETRY_USEREG_8197F(x, v) \
+ (BIT_CLEAR_RETRY_USEREG_8197F(x) | BIT_RETRY_USEREG_8197F(v))
+
+#define BIT_SHIFT_TRYPKT_USEREG_8197F 17
+#define BIT_MASK_TRYPKT_USEREG_8197F 0x3
+#define BIT_TRYPKT_USEREG_8197F(x) \
+ (((x) & BIT_MASK_TRYPKT_USEREG_8197F) << BIT_SHIFT_TRYPKT_USEREG_8197F)
+#define BITS_TRYPKT_USEREG_8197F \
+ (BIT_MASK_TRYPKT_USEREG_8197F << BIT_SHIFT_TRYPKT_USEREG_8197F)
+#define BIT_CLEAR_TRYPKT_USEREG_8197F(x) ((x) & (~BITS_TRYPKT_USEREG_8197F))
+#define BIT_GET_TRYPKT_USEREG_8197F(x) \
+ (((x) >> BIT_SHIFT_TRYPKT_USEREG_8197F) & BIT_MASK_TRYPKT_USEREG_8197F)
+#define BIT_SET_TRYPKT_USEREG_8197F(x, v) \
+ (BIT_CLEAR_TRYPKT_USEREG_8197F(x) | BIT_TRYPKT_USEREG_8197F(v))
+
+#define BIT_CTLPKT_USEREG_8197F BIT(16)
+
+/* 2 REG_AESIV_SETTING_8197F */
+
+#define BIT_SHIFT_AESIV_OFFSET_8197F 0
+#define BIT_MASK_AESIV_OFFSET_8197F 0xfff
+#define BIT_AESIV_OFFSET_8197F(x) \
+ (((x) & BIT_MASK_AESIV_OFFSET_8197F) << BIT_SHIFT_AESIV_OFFSET_8197F)
+#define BITS_AESIV_OFFSET_8197F \
+ (BIT_MASK_AESIV_OFFSET_8197F << BIT_SHIFT_AESIV_OFFSET_8197F)
+#define BIT_CLEAR_AESIV_OFFSET_8197F(x) ((x) & (~BITS_AESIV_OFFSET_8197F))
+#define BIT_GET_AESIV_OFFSET_8197F(x) \
+ (((x) >> BIT_SHIFT_AESIV_OFFSET_8197F) & BIT_MASK_AESIV_OFFSET_8197F)
+#define BIT_SET_AESIV_OFFSET_8197F(x, v) \
+ (BIT_CLEAR_AESIV_OFFSET_8197F(x) | BIT_AESIV_OFFSET_8197F(v))
+
+/* 2 REG_BF0_TIME_SETTING_8197F */
+#define BIT_BF0_TIMER_SET_8197F BIT(31)
+#define BIT_BF0_TIMER_CLR_8197F BIT(30)
+#define BIT_BF0_UPDATE_EN_8197F BIT(29)
+#define BIT_BF0_TIMER_EN_8197F BIT(28)
+
+#define BIT_SHIFT_BF0_PRETIME_OVER_8197F 16
+#define BIT_MASK_BF0_PRETIME_OVER_8197F 0xfff
+#define BIT_BF0_PRETIME_OVER_8197F(x) \
+ (((x) & BIT_MASK_BF0_PRETIME_OVER_8197F) \
+ << BIT_SHIFT_BF0_PRETIME_OVER_8197F)
+#define BITS_BF0_PRETIME_OVER_8197F \
+ (BIT_MASK_BF0_PRETIME_OVER_8197F << BIT_SHIFT_BF0_PRETIME_OVER_8197F)
+#define BIT_CLEAR_BF0_PRETIME_OVER_8197F(x) \
+ ((x) & (~BITS_BF0_PRETIME_OVER_8197F))
+#define BIT_GET_BF0_PRETIME_OVER_8197F(x) \
+ (((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8197F) & \
+ BIT_MASK_BF0_PRETIME_OVER_8197F)
+#define BIT_SET_BF0_PRETIME_OVER_8197F(x, v) \
+ (BIT_CLEAR_BF0_PRETIME_OVER_8197F(x) | BIT_BF0_PRETIME_OVER_8197F(v))
+
+#define BIT_SHIFT_BF0_LIFETIME_8197F 0
+#define BIT_MASK_BF0_LIFETIME_8197F 0xffff
+#define BIT_BF0_LIFETIME_8197F(x) \
+ (((x) & BIT_MASK_BF0_LIFETIME_8197F) << BIT_SHIFT_BF0_LIFETIME_8197F)
+#define BITS_BF0_LIFETIME_8197F \
+ (BIT_MASK_BF0_LIFETIME_8197F << BIT_SHIFT_BF0_LIFETIME_8197F)
+#define BIT_CLEAR_BF0_LIFETIME_8197F(x) ((x) & (~BITS_BF0_LIFETIME_8197F))
+#define BIT_GET_BF0_LIFETIME_8197F(x) \
+ (((x) >> BIT_SHIFT_BF0_LIFETIME_8197F) & BIT_MASK_BF0_LIFETIME_8197F)
+#define BIT_SET_BF0_LIFETIME_8197F(x, v) \
+ (BIT_CLEAR_BF0_LIFETIME_8197F(x) | BIT_BF0_LIFETIME_8197F(v))
+
+/* 2 REG_BF1_TIME_SETTING_8197F */
+#define BIT_BF1_TIMER_SET_8197F BIT(31)
+#define BIT_BF1_TIMER_CLR_8197F BIT(30)
+#define BIT_BF1_UPDATE_EN_8197F BIT(29)
+#define BIT_BF1_TIMER_EN_8197F BIT(28)
+
+#define BIT_SHIFT_BF1_PRETIME_OVER_8197F 16
+#define BIT_MASK_BF1_PRETIME_OVER_8197F 0xfff
+#define BIT_BF1_PRETIME_OVER_8197F(x) \
+ (((x) & BIT_MASK_BF1_PRETIME_OVER_8197F) \
+ << BIT_SHIFT_BF1_PRETIME_OVER_8197F)
+#define BITS_BF1_PRETIME_OVER_8197F \
+ (BIT_MASK_BF1_PRETIME_OVER_8197F << BIT_SHIFT_BF1_PRETIME_OVER_8197F)
+#define BIT_CLEAR_BF1_PRETIME_OVER_8197F(x) \
+ ((x) & (~BITS_BF1_PRETIME_OVER_8197F))
+#define BIT_GET_BF1_PRETIME_OVER_8197F(x) \
+ (((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8197F) & \
+ BIT_MASK_BF1_PRETIME_OVER_8197F)
+#define BIT_SET_BF1_PRETIME_OVER_8197F(x, v) \
+ (BIT_CLEAR_BF1_PRETIME_OVER_8197F(x) | BIT_BF1_PRETIME_OVER_8197F(v))
+
+#define BIT_SHIFT_BF1_LIFETIME_8197F 0
+#define BIT_MASK_BF1_LIFETIME_8197F 0xffff
+#define BIT_BF1_LIFETIME_8197F(x) \
+ (((x) & BIT_MASK_BF1_LIFETIME_8197F) << BIT_SHIFT_BF1_LIFETIME_8197F)
+#define BITS_BF1_LIFETIME_8197F \
+ (BIT_MASK_BF1_LIFETIME_8197F << BIT_SHIFT_BF1_LIFETIME_8197F)
+#define BIT_CLEAR_BF1_LIFETIME_8197F(x) ((x) & (~BITS_BF1_LIFETIME_8197F))
+#define BIT_GET_BF1_LIFETIME_8197F(x) \
+ (((x) >> BIT_SHIFT_BF1_LIFETIME_8197F) & BIT_MASK_BF1_LIFETIME_8197F)
+#define BIT_SET_BF1_LIFETIME_8197F(x, v) \
+ (BIT_CLEAR_BF1_LIFETIME_8197F(x) | BIT_BF1_LIFETIME_8197F(v))
+
+/* 2 REG_BF_TIMEOUT_EN_8197F */
+#define BIT_EN_VHT_LDPC_8197F BIT(9)
+#define BIT_EN_HT_LDPC_8197F BIT(8)
+#define BIT_BF1_TIMEOUT_EN_8197F BIT(1)
+#define BIT_BF0_TIMEOUT_EN_8197F BIT(0)
+
+/* 2 REG_MACID_RELEASE0_8197F */
+
+#define BIT_SHIFT_MACID31_0_RELEASE_8197F 0
+#define BIT_MASK_MACID31_0_RELEASE_8197F 0xffffffffL
+#define BIT_MACID31_0_RELEASE_8197F(x) \
+ (((x) & BIT_MASK_MACID31_0_RELEASE_8197F) \
+ << BIT_SHIFT_MACID31_0_RELEASE_8197F)
+#define BITS_MACID31_0_RELEASE_8197F \
+ (BIT_MASK_MACID31_0_RELEASE_8197F << BIT_SHIFT_MACID31_0_RELEASE_8197F)
+#define BIT_CLEAR_MACID31_0_RELEASE_8197F(x) \
+ ((x) & (~BITS_MACID31_0_RELEASE_8197F))
+#define BIT_GET_MACID31_0_RELEASE_8197F(x) \
+ (((x) >> BIT_SHIFT_MACID31_0_RELEASE_8197F) & \
+ BIT_MASK_MACID31_0_RELEASE_8197F)
+#define BIT_SET_MACID31_0_RELEASE_8197F(x, v) \
+ (BIT_CLEAR_MACID31_0_RELEASE_8197F(x) | BIT_MACID31_0_RELEASE_8197F(v))
+
+/* 2 REG_MACID_RELEASE1_8197F */
+
+#define BIT_SHIFT_MACID63_32_RELEASE_8197F 0
+#define BIT_MASK_MACID63_32_RELEASE_8197F 0xffffffffL
+#define BIT_MACID63_32_RELEASE_8197F(x) \
+ (((x) & BIT_MASK_MACID63_32_RELEASE_8197F) \
+ << BIT_SHIFT_MACID63_32_RELEASE_8197F)
+#define BITS_MACID63_32_RELEASE_8197F \
+ (BIT_MASK_MACID63_32_RELEASE_8197F \
+ << BIT_SHIFT_MACID63_32_RELEASE_8197F)
+#define BIT_CLEAR_MACID63_32_RELEASE_8197F(x) \
+ ((x) & (~BITS_MACID63_32_RELEASE_8197F))
+#define BIT_GET_MACID63_32_RELEASE_8197F(x) \
+ (((x) >> BIT_SHIFT_MACID63_32_RELEASE_8197F) & \
+ BIT_MASK_MACID63_32_RELEASE_8197F)
+#define BIT_SET_MACID63_32_RELEASE_8197F(x, v) \
+ (BIT_CLEAR_MACID63_32_RELEASE_8197F(x) | \
+ BIT_MACID63_32_RELEASE_8197F(v))
+
+/* 2 REG_MACID_RELEASE2_8197F */
+
+#define BIT_SHIFT_MACID95_64_RELEASE_8197F 0
+#define BIT_MASK_MACID95_64_RELEASE_8197F 0xffffffffL
+#define BIT_MACID95_64_RELEASE_8197F(x) \
+ (((x) & BIT_MASK_MACID95_64_RELEASE_8197F) \
+ << BIT_SHIFT_MACID95_64_RELEASE_8197F)
+#define BITS_MACID95_64_RELEASE_8197F \
+ (BIT_MASK_MACID95_64_RELEASE_8197F \
+ << BIT_SHIFT_MACID95_64_RELEASE_8197F)
+#define BIT_CLEAR_MACID95_64_RELEASE_8197F(x) \
+ ((x) & (~BITS_MACID95_64_RELEASE_8197F))
+#define BIT_GET_MACID95_64_RELEASE_8197F(x) \
+ (((x) >> BIT_SHIFT_MACID95_64_RELEASE_8197F) & \
+ BIT_MASK_MACID95_64_RELEASE_8197F)
+#define BIT_SET_MACID95_64_RELEASE_8197F(x, v) \
+ (BIT_CLEAR_MACID95_64_RELEASE_8197F(x) | \
+ BIT_MACID95_64_RELEASE_8197F(v))
+
+/* 2 REG_MACID_RELEASE3_8197F */
+
+#define BIT_SHIFT_MACID127_96_RELEASE_8197F 0
+#define BIT_MASK_MACID127_96_RELEASE_8197F 0xffffffffL
+#define BIT_MACID127_96_RELEASE_8197F(x) \
+ (((x) & BIT_MASK_MACID127_96_RELEASE_8197F) \
+ << BIT_SHIFT_MACID127_96_RELEASE_8197F)
+#define BITS_MACID127_96_RELEASE_8197F \
+ (BIT_MASK_MACID127_96_RELEASE_8197F \
+ << BIT_SHIFT_MACID127_96_RELEASE_8197F)
+#define BIT_CLEAR_MACID127_96_RELEASE_8197F(x) \
+ ((x) & (~BITS_MACID127_96_RELEASE_8197F))
+#define BIT_GET_MACID127_96_RELEASE_8197F(x) \
+ (((x) >> BIT_SHIFT_MACID127_96_RELEASE_8197F) & \
+ BIT_MASK_MACID127_96_RELEASE_8197F)
+#define BIT_SET_MACID127_96_RELEASE_8197F(x, v) \
+ (BIT_CLEAR_MACID127_96_RELEASE_8197F(x) | \
+ BIT_MACID127_96_RELEASE_8197F(v))
+
+/* 2 REG_MACID_RELEASE_SETTING_8197F */
+#define BIT_MACID_VALUE_8197F BIT(7)
+
+#define BIT_SHIFT_MACID_OFFSET_8197F 0
+#define BIT_MASK_MACID_OFFSET_8197F 0x7f
+#define BIT_MACID_OFFSET_8197F(x) \
+ (((x) & BIT_MASK_MACID_OFFSET_8197F) << BIT_SHIFT_MACID_OFFSET_8197F)
+#define BITS_MACID_OFFSET_8197F \
+ (BIT_MASK_MACID_OFFSET_8197F << BIT_SHIFT_MACID_OFFSET_8197F)
+#define BIT_CLEAR_MACID_OFFSET_8197F(x) ((x) & (~BITS_MACID_OFFSET_8197F))
+#define BIT_GET_MACID_OFFSET_8197F(x) \
+ (((x) >> BIT_SHIFT_MACID_OFFSET_8197F) & BIT_MASK_MACID_OFFSET_8197F)
+#define BIT_SET_MACID_OFFSET_8197F(x, v) \
+ (BIT_CLEAR_MACID_OFFSET_8197F(x) | BIT_MACID_OFFSET_8197F(v))
+
+/* 2 REG_FAST_EDCA_VOVI_SETTING_8197F */
+
+#define BIT_SHIFT_VI_FAST_EDCA_TO_8197F 24
+#define BIT_MASK_VI_FAST_EDCA_TO_8197F 0xff
+#define BIT_VI_FAST_EDCA_TO_8197F(x) \
+ (((x) & BIT_MASK_VI_FAST_EDCA_TO_8197F) \
+ << BIT_SHIFT_VI_FAST_EDCA_TO_8197F)
+#define BITS_VI_FAST_EDCA_TO_8197F \
+ (BIT_MASK_VI_FAST_EDCA_TO_8197F << BIT_SHIFT_VI_FAST_EDCA_TO_8197F)
+#define BIT_CLEAR_VI_FAST_EDCA_TO_8197F(x) ((x) & (~BITS_VI_FAST_EDCA_TO_8197F))
+#define BIT_GET_VI_FAST_EDCA_TO_8197F(x) \
+ (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8197F) & \
+ BIT_MASK_VI_FAST_EDCA_TO_8197F)
+#define BIT_SET_VI_FAST_EDCA_TO_8197F(x, v) \
+ (BIT_CLEAR_VI_FAST_EDCA_TO_8197F(x) | BIT_VI_FAST_EDCA_TO_8197F(v))
+
+#define BIT_VI_THRESHOLD_SEL_8197F BIT(23)
+
+#define BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8197F 16
+#define BIT_MASK_VI_FAST_EDCA_PKT_TH_8197F 0x7f
+#define BIT_VI_FAST_EDCA_PKT_TH_8197F(x) \
+ (((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8197F) \
+ << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8197F)
+#define BITS_VI_FAST_EDCA_PKT_TH_8197F \
+ (BIT_MASK_VI_FAST_EDCA_PKT_TH_8197F \
+ << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8197F)
+#define BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8197F(x) \
+ ((x) & (~BITS_VI_FAST_EDCA_PKT_TH_8197F))
+#define BIT_GET_VI_FAST_EDCA_PKT_TH_8197F(x) \
+ (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8197F) & \
+ BIT_MASK_VI_FAST_EDCA_PKT_TH_8197F)
+#define BIT_SET_VI_FAST_EDCA_PKT_TH_8197F(x, v) \
+ (BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8197F(x) | \
+ BIT_VI_FAST_EDCA_PKT_TH_8197F(v))
+
+#define BIT_SHIFT_VO_FAST_EDCA_TO_8197F 8
+#define BIT_MASK_VO_FAST_EDCA_TO_8197F 0xff
+#define BIT_VO_FAST_EDCA_TO_8197F(x) \
+ (((x) & BIT_MASK_VO_FAST_EDCA_TO_8197F) \
+ << BIT_SHIFT_VO_FAST_EDCA_TO_8197F)
+#define BITS_VO_FAST_EDCA_TO_8197F \
+ (BIT_MASK_VO_FAST_EDCA_TO_8197F << BIT_SHIFT_VO_FAST_EDCA_TO_8197F)
+#define BIT_CLEAR_VO_FAST_EDCA_TO_8197F(x) ((x) & (~BITS_VO_FAST_EDCA_TO_8197F))
+#define BIT_GET_VO_FAST_EDCA_TO_8197F(x) \
+ (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8197F) & \
+ BIT_MASK_VO_FAST_EDCA_TO_8197F)
+#define BIT_SET_VO_FAST_EDCA_TO_8197F(x, v) \
+ (BIT_CLEAR_VO_FAST_EDCA_TO_8197F(x) | BIT_VO_FAST_EDCA_TO_8197F(v))
+
+#define BIT_VO_THRESHOLD_SEL_8197F BIT(7)
+
+#define BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8197F 0
+#define BIT_MASK_VO_FAST_EDCA_PKT_TH_8197F 0x7f
+#define BIT_VO_FAST_EDCA_PKT_TH_8197F(x) \
+ (((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8197F) \
+ << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8197F)
+#define BITS_VO_FAST_EDCA_PKT_TH_8197F \
+ (BIT_MASK_VO_FAST_EDCA_PKT_TH_8197F \
+ << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8197F)
+#define BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8197F(x) \
+ ((x) & (~BITS_VO_FAST_EDCA_PKT_TH_8197F))
+#define BIT_GET_VO_FAST_EDCA_PKT_TH_8197F(x) \
+ (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8197F) & \
+ BIT_MASK_VO_FAST_EDCA_PKT_TH_8197F)
+#define BIT_SET_VO_FAST_EDCA_PKT_TH_8197F(x, v) \
+ (BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8197F(x) | \
+ BIT_VO_FAST_EDCA_PKT_TH_8197F(v))
+
+/* 2 REG_FAST_EDCA_BEBK_SETTING_8197F */
+
+#define BIT_SHIFT_BK_FAST_EDCA_TO_8197F 24
+#define BIT_MASK_BK_FAST_EDCA_TO_8197F 0xff
+#define BIT_BK_FAST_EDCA_TO_8197F(x) \
+ (((x) & BIT_MASK_BK_FAST_EDCA_TO_8197F) \
+ << BIT_SHIFT_BK_FAST_EDCA_TO_8197F)
+#define BITS_BK_FAST_EDCA_TO_8197F \
+ (BIT_MASK_BK_FAST_EDCA_TO_8197F << BIT_SHIFT_BK_FAST_EDCA_TO_8197F)
+#define BIT_CLEAR_BK_FAST_EDCA_TO_8197F(x) ((x) & (~BITS_BK_FAST_EDCA_TO_8197F))
+#define BIT_GET_BK_FAST_EDCA_TO_8197F(x) \
+ (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8197F) & \
+ BIT_MASK_BK_FAST_EDCA_TO_8197F)
+#define BIT_SET_BK_FAST_EDCA_TO_8197F(x, v) \
+ (BIT_CLEAR_BK_FAST_EDCA_TO_8197F(x) | BIT_BK_FAST_EDCA_TO_8197F(v))
+
+#define BIT_BK_THRESHOLD_SEL_8197F BIT(23)
+
+#define BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8197F 16
+#define BIT_MASK_BK_FAST_EDCA_PKT_TH_8197F 0x7f
+#define BIT_BK_FAST_EDCA_PKT_TH_8197F(x) \
+ (((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8197F) \
+ << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8197F)
+#define BITS_BK_FAST_EDCA_PKT_TH_8197F \
+ (BIT_MASK_BK_FAST_EDCA_PKT_TH_8197F \
+ << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8197F)
+#define BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8197F(x) \
+ ((x) & (~BITS_BK_FAST_EDCA_PKT_TH_8197F))
+#define BIT_GET_BK_FAST_EDCA_PKT_TH_8197F(x) \
+ (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8197F) & \
+ BIT_MASK_BK_FAST_EDCA_PKT_TH_8197F)
+#define BIT_SET_BK_FAST_EDCA_PKT_TH_8197F(x, v) \
+ (BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8197F(x) | \
+ BIT_BK_FAST_EDCA_PKT_TH_8197F(v))
+
+#define BIT_SHIFT_BE_FAST_EDCA_TO_8197F 8
+#define BIT_MASK_BE_FAST_EDCA_TO_8197F 0xff
+#define BIT_BE_FAST_EDCA_TO_8197F(x) \
+ (((x) & BIT_MASK_BE_FAST_EDCA_TO_8197F) \
+ << BIT_SHIFT_BE_FAST_EDCA_TO_8197F)
+#define BITS_BE_FAST_EDCA_TO_8197F \
+ (BIT_MASK_BE_FAST_EDCA_TO_8197F << BIT_SHIFT_BE_FAST_EDCA_TO_8197F)
+#define BIT_CLEAR_BE_FAST_EDCA_TO_8197F(x) ((x) & (~BITS_BE_FAST_EDCA_TO_8197F))
+#define BIT_GET_BE_FAST_EDCA_TO_8197F(x) \
+ (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8197F) & \
+ BIT_MASK_BE_FAST_EDCA_TO_8197F)
+#define BIT_SET_BE_FAST_EDCA_TO_8197F(x, v) \
+ (BIT_CLEAR_BE_FAST_EDCA_TO_8197F(x) | BIT_BE_FAST_EDCA_TO_8197F(v))
+
+#define BIT_BE_THRESHOLD_SEL_8197F BIT(7)
+
+#define BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8197F 0
+#define BIT_MASK_BE_FAST_EDCA_PKT_TH_8197F 0x7f
+#define BIT_BE_FAST_EDCA_PKT_TH_8197F(x) \
+ (((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8197F) \
+ << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8197F)
+#define BITS_BE_FAST_EDCA_PKT_TH_8197F \
+ (BIT_MASK_BE_FAST_EDCA_PKT_TH_8197F \
+ << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8197F)
+#define BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8197F(x) \
+ ((x) & (~BITS_BE_FAST_EDCA_PKT_TH_8197F))
+#define BIT_GET_BE_FAST_EDCA_PKT_TH_8197F(x) \
+ (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8197F) & \
+ BIT_MASK_BE_FAST_EDCA_PKT_TH_8197F)
+#define BIT_SET_BE_FAST_EDCA_PKT_TH_8197F(x, v) \
+ (BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8197F(x) | \
+ BIT_BE_FAST_EDCA_PKT_TH_8197F(v))
+
+/* 2 REG_MACID_DROP0_8197F */
+
+#define BIT_SHIFT_MACID31_0_DROP_8197F 0
+#define BIT_MASK_MACID31_0_DROP_8197F 0xffffffffL
+#define BIT_MACID31_0_DROP_8197F(x) \
+ (((x) & BIT_MASK_MACID31_0_DROP_8197F) \
+ << BIT_SHIFT_MACID31_0_DROP_8197F)
+#define BITS_MACID31_0_DROP_8197F \
+ (BIT_MASK_MACID31_0_DROP_8197F << BIT_SHIFT_MACID31_0_DROP_8197F)
+#define BIT_CLEAR_MACID31_0_DROP_8197F(x) ((x) & (~BITS_MACID31_0_DROP_8197F))
+#define BIT_GET_MACID31_0_DROP_8197F(x) \
+ (((x) >> BIT_SHIFT_MACID31_0_DROP_8197F) & \
+ BIT_MASK_MACID31_0_DROP_8197F)
+#define BIT_SET_MACID31_0_DROP_8197F(x, v) \
+ (BIT_CLEAR_MACID31_0_DROP_8197F(x) | BIT_MACID31_0_DROP_8197F(v))
+
+/* 2 REG_MACID_DROP1_8197F */
+
+#define BIT_SHIFT_MACID63_32_DROP_8197F 0
+#define BIT_MASK_MACID63_32_DROP_8197F 0xffffffffL
+#define BIT_MACID63_32_DROP_8197F(x) \
+ (((x) & BIT_MASK_MACID63_32_DROP_8197F) \
+ << BIT_SHIFT_MACID63_32_DROP_8197F)
+#define BITS_MACID63_32_DROP_8197F \
+ (BIT_MASK_MACID63_32_DROP_8197F << BIT_SHIFT_MACID63_32_DROP_8197F)
+#define BIT_CLEAR_MACID63_32_DROP_8197F(x) ((x) & (~BITS_MACID63_32_DROP_8197F))
+#define BIT_GET_MACID63_32_DROP_8197F(x) \
+ (((x) >> BIT_SHIFT_MACID63_32_DROP_8197F) & \
+ BIT_MASK_MACID63_32_DROP_8197F)
+#define BIT_SET_MACID63_32_DROP_8197F(x, v) \
+ (BIT_CLEAR_MACID63_32_DROP_8197F(x) | BIT_MACID63_32_DROP_8197F(v))
+
+/* 2 REG_MACID_DROP2_8197F */
+
+#define BIT_SHIFT_MACID95_64_DROP_8197F 0
+#define BIT_MASK_MACID95_64_DROP_8197F 0xffffffffL
+#define BIT_MACID95_64_DROP_8197F(x) \
+ (((x) & BIT_MASK_MACID95_64_DROP_8197F) \
+ << BIT_SHIFT_MACID95_64_DROP_8197F)
+#define BITS_MACID95_64_DROP_8197F \
+ (BIT_MASK_MACID95_64_DROP_8197F << BIT_SHIFT_MACID95_64_DROP_8197F)
+#define BIT_CLEAR_MACID95_64_DROP_8197F(x) ((x) & (~BITS_MACID95_64_DROP_8197F))
+#define BIT_GET_MACID95_64_DROP_8197F(x) \
+ (((x) >> BIT_SHIFT_MACID95_64_DROP_8197F) & \
+ BIT_MASK_MACID95_64_DROP_8197F)
+#define BIT_SET_MACID95_64_DROP_8197F(x, v) \
+ (BIT_CLEAR_MACID95_64_DROP_8197F(x) | BIT_MACID95_64_DROP_8197F(v))
+
+/* 2 REG_MACID_DROP3_8197F */
+
+#define BIT_SHIFT_MACID127_96_DROP_8197F 0
+#define BIT_MASK_MACID127_96_DROP_8197F 0xffffffffL
+#define BIT_MACID127_96_DROP_8197F(x) \
+ (((x) & BIT_MASK_MACID127_96_DROP_8197F) \
+ << BIT_SHIFT_MACID127_96_DROP_8197F)
+#define BITS_MACID127_96_DROP_8197F \
+ (BIT_MASK_MACID127_96_DROP_8197F << BIT_SHIFT_MACID127_96_DROP_8197F)
+#define BIT_CLEAR_MACID127_96_DROP_8197F(x) \
+ ((x) & (~BITS_MACID127_96_DROP_8197F))
+#define BIT_GET_MACID127_96_DROP_8197F(x) \
+ (((x) >> BIT_SHIFT_MACID127_96_DROP_8197F) & \
+ BIT_MASK_MACID127_96_DROP_8197F)
+#define BIT_SET_MACID127_96_DROP_8197F(x, v) \
+ (BIT_CLEAR_MACID127_96_DROP_8197F(x) | BIT_MACID127_96_DROP_8197F(v))
+
+/* 2 REG_R_MACID_RELEASE_SUCCESS_0_8197F */
+
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8197F 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8197F 0xffffffffL
+#define BIT_R_MACID_RELEASE_SUCCESS_0_8197F(x) \
+ (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8197F) \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8197F)
+#define BITS_R_MACID_RELEASE_SUCCESS_0_8197F \
+ (BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8197F \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8197F)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8197F(x) \
+ ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_0_8197F))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_0_8197F(x) \
+ (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8197F) & \
+ BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8197F)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_0_8197F(x, v) \
+ (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8197F(x) | \
+ BIT_R_MACID_RELEASE_SUCCESS_0_8197F(v))
+
+/* 2 REG_R_MACID_RELEASE_SUCCESS_1_8197F */
+
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8197F 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8197F 0xffffffffL
+#define BIT_R_MACID_RELEASE_SUCCESS_1_8197F(x) \
+ (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8197F) \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8197F)
+#define BITS_R_MACID_RELEASE_SUCCESS_1_8197F \
+ (BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8197F \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8197F)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8197F(x) \
+ ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_1_8197F))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_1_8197F(x) \
+ (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8197F) & \
+ BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8197F)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_1_8197F(x, v) \
+ (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8197F(x) | \
+ BIT_R_MACID_RELEASE_SUCCESS_1_8197F(v))
+
+/* 2 REG_R_MACID_RELEASE_SUCCESS_2_8197F */
+
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8197F 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8197F 0xffffffffL
+#define BIT_R_MACID_RELEASE_SUCCESS_2_8197F(x) \
+ (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8197F) \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8197F)
+#define BITS_R_MACID_RELEASE_SUCCESS_2_8197F \
+ (BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8197F \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8197F)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8197F(x) \
+ ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_2_8197F))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_2_8197F(x) \
+ (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8197F) & \
+ BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8197F)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_2_8197F(x, v) \
+ (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8197F(x) | \
+ BIT_R_MACID_RELEASE_SUCCESS_2_8197F(v))
+
+/* 2 REG_R_MACID_RELEASE_SUCCESS_3_8197F */
+
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8197F 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8197F 0xffffffffL
+#define BIT_R_MACID_RELEASE_SUCCESS_3_8197F(x) \
+ (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8197F) \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8197F)
+#define BITS_R_MACID_RELEASE_SUCCESS_3_8197F \
+ (BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8197F \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8197F)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8197F(x) \
+ ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_3_8197F))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_3_8197F(x) \
+ (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8197F) & \
+ BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8197F)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_3_8197F(x, v) \
+ (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8197F(x) | \
+ BIT_R_MACID_RELEASE_SUCCESS_3_8197F(v))
+
+/* 2 REG_MGG_FIFO_CRTL_8197F */
+#define BIT_R_MGG_FIFO_EN_8197F BIT(31)
+
+#define BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8197F 28
+#define BIT_MASK_R_MGG_FIFO_PG_SIZE_8197F 0x7
+#define BIT_R_MGG_FIFO_PG_SIZE_8197F(x) \
+ (((x) & BIT_MASK_R_MGG_FIFO_PG_SIZE_8197F) \
+ << BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8197F)
+#define BITS_R_MGG_FIFO_PG_SIZE_8197F \
+ (BIT_MASK_R_MGG_FIFO_PG_SIZE_8197F \
+ << BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8197F)
+#define BIT_CLEAR_R_MGG_FIFO_PG_SIZE_8197F(x) \
+ ((x) & (~BITS_R_MGG_FIFO_PG_SIZE_8197F))
+#define BIT_GET_R_MGG_FIFO_PG_SIZE_8197F(x) \
+ (((x) >> BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8197F) & \
+ BIT_MASK_R_MGG_FIFO_PG_SIZE_8197F)
+#define BIT_SET_R_MGG_FIFO_PG_SIZE_8197F(x, v) \
+ (BIT_CLEAR_R_MGG_FIFO_PG_SIZE_8197F(x) | \
+ BIT_R_MGG_FIFO_PG_SIZE_8197F(v))
+
+#define BIT_SHIFT_R_MGG_FIFO_START_PG_8197F 16
+#define BIT_MASK_R_MGG_FIFO_START_PG_8197F 0xfff
+#define BIT_R_MGG_FIFO_START_PG_8197F(x) \
+ (((x) & BIT_MASK_R_MGG_FIFO_START_PG_8197F) \
+ << BIT_SHIFT_R_MGG_FIFO_START_PG_8197F)
+#define BITS_R_MGG_FIFO_START_PG_8197F \
+ (BIT_MASK_R_MGG_FIFO_START_PG_8197F \
+ << BIT_SHIFT_R_MGG_FIFO_START_PG_8197F)
+#define BIT_CLEAR_R_MGG_FIFO_START_PG_8197F(x) \
+ ((x) & (~BITS_R_MGG_FIFO_START_PG_8197F))
+#define BIT_GET_R_MGG_FIFO_START_PG_8197F(x) \
+ (((x) >> BIT_SHIFT_R_MGG_FIFO_START_PG_8197F) & \
+ BIT_MASK_R_MGG_FIFO_START_PG_8197F)
+#define BIT_SET_R_MGG_FIFO_START_PG_8197F(x, v) \
+ (BIT_CLEAR_R_MGG_FIFO_START_PG_8197F(x) | \
+ BIT_R_MGG_FIFO_START_PG_8197F(v))
+
+#define BIT_SHIFT_R_MGG_FIFO_SIZE_8197F 14
+#define BIT_MASK_R_MGG_FIFO_SIZE_8197F 0x3
+#define BIT_R_MGG_FIFO_SIZE_8197F(x) \
+ (((x) & BIT_MASK_R_MGG_FIFO_SIZE_8197F) \
+ << BIT_SHIFT_R_MGG_FIFO_SIZE_8197F)
+#define BITS_R_MGG_FIFO_SIZE_8197F \
+ (BIT_MASK_R_MGG_FIFO_SIZE_8197F << BIT_SHIFT_R_MGG_FIFO_SIZE_8197F)
+#define BIT_CLEAR_R_MGG_FIFO_SIZE_8197F(x) ((x) & (~BITS_R_MGG_FIFO_SIZE_8197F))
+#define BIT_GET_R_MGG_FIFO_SIZE_8197F(x) \
+ (((x) >> BIT_SHIFT_R_MGG_FIFO_SIZE_8197F) & \
+ BIT_MASK_R_MGG_FIFO_SIZE_8197F)
+#define BIT_SET_R_MGG_FIFO_SIZE_8197F(x, v) \
+ (BIT_CLEAR_R_MGG_FIFO_SIZE_8197F(x) | BIT_R_MGG_FIFO_SIZE_8197F(v))
+
+#define BIT_R_MGG_FIFO_PAUSE_8197F BIT(13)
+
+#define BIT_SHIFT_R_MGG_FIFO_RPTR_8197F 8
+#define BIT_MASK_R_MGG_FIFO_RPTR_8197F 0x1f
+#define BIT_R_MGG_FIFO_RPTR_8197F(x) \
+ (((x) & BIT_MASK_R_MGG_FIFO_RPTR_8197F) \
+ << BIT_SHIFT_R_MGG_FIFO_RPTR_8197F)
+#define BITS_R_MGG_FIFO_RPTR_8197F \
+ (BIT_MASK_R_MGG_FIFO_RPTR_8197F << BIT_SHIFT_R_MGG_FIFO_RPTR_8197F)
+#define BIT_CLEAR_R_MGG_FIFO_RPTR_8197F(x) ((x) & (~BITS_R_MGG_FIFO_RPTR_8197F))
+#define BIT_GET_R_MGG_FIFO_RPTR_8197F(x) \
+ (((x) >> BIT_SHIFT_R_MGG_FIFO_RPTR_8197F) & \
+ BIT_MASK_R_MGG_FIFO_RPTR_8197F)
+#define BIT_SET_R_MGG_FIFO_RPTR_8197F(x, v) \
+ (BIT_CLEAR_R_MGG_FIFO_RPTR_8197F(x) | BIT_R_MGG_FIFO_RPTR_8197F(v))
+
+#define BIT_R_MGG_FIFO_OV_8197F BIT(7)
+#define BIT_R_MGG_FIFO_WPTR_ERROR_8197F BIT(6)
+#define BIT_R_EN_CPU_LIFETIME_8197F BIT(5)
+
+#define BIT_SHIFT_R_MGG_FIFO_WPTR_8197F 0
+#define BIT_MASK_R_MGG_FIFO_WPTR_8197F 0x1f
+#define BIT_R_MGG_FIFO_WPTR_8197F(x) \
+ (((x) & BIT_MASK_R_MGG_FIFO_WPTR_8197F) \
+ << BIT_SHIFT_R_MGG_FIFO_WPTR_8197F)
+#define BITS_R_MGG_FIFO_WPTR_8197F \
+ (BIT_MASK_R_MGG_FIFO_WPTR_8197F << BIT_SHIFT_R_MGG_FIFO_WPTR_8197F)
+#define BIT_CLEAR_R_MGG_FIFO_WPTR_8197F(x) ((x) & (~BITS_R_MGG_FIFO_WPTR_8197F))
+#define BIT_GET_R_MGG_FIFO_WPTR_8197F(x) \
+ (((x) >> BIT_SHIFT_R_MGG_FIFO_WPTR_8197F) & \
+ BIT_MASK_R_MGG_FIFO_WPTR_8197F)
+#define BIT_SET_R_MGG_FIFO_WPTR_8197F(x, v) \
+ (BIT_CLEAR_R_MGG_FIFO_WPTR_8197F(x) | BIT_R_MGG_FIFO_WPTR_8197F(v))
+
+/* 2 REG_MGG_FIFO_INT_8197F */
+
+#define BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8197F 16
+#define BIT_MASK_R_MGG_FIFO_INT_FLAG_8197F 0xffff
+#define BIT_R_MGG_FIFO_INT_FLAG_8197F(x) \
+ (((x) & BIT_MASK_R_MGG_FIFO_INT_FLAG_8197F) \
+ << BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8197F)
+#define BITS_R_MGG_FIFO_INT_FLAG_8197F \
+ (BIT_MASK_R_MGG_FIFO_INT_FLAG_8197F \
+ << BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8197F)
+#define BIT_CLEAR_R_MGG_FIFO_INT_FLAG_8197F(x) \
+ ((x) & (~BITS_R_MGG_FIFO_INT_FLAG_8197F))
+#define BIT_GET_R_MGG_FIFO_INT_FLAG_8197F(x) \
+ (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8197F) & \
+ BIT_MASK_R_MGG_FIFO_INT_FLAG_8197F)
+#define BIT_SET_R_MGG_FIFO_INT_FLAG_8197F(x, v) \
+ (BIT_CLEAR_R_MGG_FIFO_INT_FLAG_8197F(x) | \
+ BIT_R_MGG_FIFO_INT_FLAG_8197F(v))
+
+#define BIT_SHIFT_R_MGG_FIFO_INT_MASK_8197F 0
+#define BIT_MASK_R_MGG_FIFO_INT_MASK_8197F 0xffff
+#define BIT_R_MGG_FIFO_INT_MASK_8197F(x) \
+ (((x) & BIT_MASK_R_MGG_FIFO_INT_MASK_8197F) \
+ << BIT_SHIFT_R_MGG_FIFO_INT_MASK_8197F)
+#define BITS_R_MGG_FIFO_INT_MASK_8197F \
+ (BIT_MASK_R_MGG_FIFO_INT_MASK_8197F \
+ << BIT_SHIFT_R_MGG_FIFO_INT_MASK_8197F)
+#define BIT_CLEAR_R_MGG_FIFO_INT_MASK_8197F(x) \
+ ((x) & (~BITS_R_MGG_FIFO_INT_MASK_8197F))
+#define BIT_GET_R_MGG_FIFO_INT_MASK_8197F(x) \
+ (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_MASK_8197F) & \
+ BIT_MASK_R_MGG_FIFO_INT_MASK_8197F)
+#define BIT_SET_R_MGG_FIFO_INT_MASK_8197F(x, v) \
+ (BIT_CLEAR_R_MGG_FIFO_INT_MASK_8197F(x) | \
+ BIT_R_MGG_FIFO_INT_MASK_8197F(v))
+
+/* 2 REG_MGG_FIFO_LIFETIME_8197F */
+
+#define BIT_SHIFT_R_MGG_FIFO_LIFETIME_8197F 16
+#define BIT_MASK_R_MGG_FIFO_LIFETIME_8197F 0xffff
+#define BIT_R_MGG_FIFO_LIFETIME_8197F(x) \
+ (((x) & BIT_MASK_R_MGG_FIFO_LIFETIME_8197F) \
+ << BIT_SHIFT_R_MGG_FIFO_LIFETIME_8197F)
+#define BITS_R_MGG_FIFO_LIFETIME_8197F \
+ (BIT_MASK_R_MGG_FIFO_LIFETIME_8197F \
+ << BIT_SHIFT_R_MGG_FIFO_LIFETIME_8197F)
+#define BIT_CLEAR_R_MGG_FIFO_LIFETIME_8197F(x) \
+ ((x) & (~BITS_R_MGG_FIFO_LIFETIME_8197F))
+#define BIT_GET_R_MGG_FIFO_LIFETIME_8197F(x) \
+ (((x) >> BIT_SHIFT_R_MGG_FIFO_LIFETIME_8197F) & \
+ BIT_MASK_R_MGG_FIFO_LIFETIME_8197F)
+#define BIT_SET_R_MGG_FIFO_LIFETIME_8197F(x, v) \
+ (BIT_CLEAR_R_MGG_FIFO_LIFETIME_8197F(x) | \
+ BIT_R_MGG_FIFO_LIFETIME_8197F(v))
+
+#define BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8197F 0
+#define BIT_MASK_R_MGG_FIFO_VALID_MAP_8197F 0xffff
+#define BIT_R_MGG_FIFO_VALID_MAP_8197F(x) \
+ (((x) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8197F) \
+ << BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8197F)
+#define BITS_R_MGG_FIFO_VALID_MAP_8197F \
+ (BIT_MASK_R_MGG_FIFO_VALID_MAP_8197F \
+ << BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8197F)
+#define BIT_CLEAR_R_MGG_FIFO_VALID_MAP_8197F(x) \
+ ((x) & (~BITS_R_MGG_FIFO_VALID_MAP_8197F))
+#define BIT_GET_R_MGG_FIFO_VALID_MAP_8197F(x) \
+ (((x) >> BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8197F) & \
+ BIT_MASK_R_MGG_FIFO_VALID_MAP_8197F)
+#define BIT_SET_R_MGG_FIFO_VALID_MAP_8197F(x, v) \
+ (BIT_CLEAR_R_MGG_FIFO_VALID_MAP_8197F(x) | \
+ BIT_R_MGG_FIFO_VALID_MAP_8197F(v))
+
+/* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F */
+
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F 0x7f
+#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x) \
+ (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F) \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F)
+#define BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F \
+ (BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x) \
+ ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x) \
+ (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F) & \
+ BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x, v) \
+ (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(x) | \
+ BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F(v))
+
+/* 2 REG_SHCUT_SETTING_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_SHCUT_LLC_ETH_TYPE0_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_SHCUT_LLC_ETH_TYPE1_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_SHCUT_LLC_OUI0_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_SHCUT_LLC_OUI1_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_SHCUT_LLC_OUI2_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_SHCUT_LLC_OUI3_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_CHNL_INFO_CTRL_8197F */
+#define BIT_CHNL_REF_RXNAV_8197F BIT(7)
+#define BIT_CHNL_REF_VBON_8197F BIT(6)
+#define BIT_CHNL_REF_EDCCA_8197F BIT(5)
+#define BIT_RST_CHNL_BUSY_8197F BIT(3)
+#define BIT_RST_CHNL_IDLE_8197F BIT(2)
+#define BIT_CHNL_INFO_RST_8197F BIT(1)
+#define BIT_ATM_AIRTIME_EN_8197F BIT(0)
+
+/* 2 REG_CHNL_IDLE_TIME_8197F */
+
+#define BIT_SHIFT_CHNL_IDLE_TIME_8197F 0
+#define BIT_MASK_CHNL_IDLE_TIME_8197F 0xffffffffL
+#define BIT_CHNL_IDLE_TIME_8197F(x) \
+ (((x) & BIT_MASK_CHNL_IDLE_TIME_8197F) \
+ << BIT_SHIFT_CHNL_IDLE_TIME_8197F)
+#define BITS_CHNL_IDLE_TIME_8197F \
+ (BIT_MASK_CHNL_IDLE_TIME_8197F << BIT_SHIFT_CHNL_IDLE_TIME_8197F)
+#define BIT_CLEAR_CHNL_IDLE_TIME_8197F(x) ((x) & (~BITS_CHNL_IDLE_TIME_8197F))
+#define BIT_GET_CHNL_IDLE_TIME_8197F(x) \
+ (((x) >> BIT_SHIFT_CHNL_IDLE_TIME_8197F) & \
+ BIT_MASK_CHNL_IDLE_TIME_8197F)
+#define BIT_SET_CHNL_IDLE_TIME_8197F(x, v) \
+ (BIT_CLEAR_CHNL_IDLE_TIME_8197F(x) | BIT_CHNL_IDLE_TIME_8197F(v))
+
+/* 2 REG_CHNL_BUSY_TIME_8197F */
+
+#define BIT_SHIFT_CHNL_BUSY_TIME_8197F 0
+#define BIT_MASK_CHNL_BUSY_TIME_8197F 0xffffffffL
+#define BIT_CHNL_BUSY_TIME_8197F(x) \
+ (((x) & BIT_MASK_CHNL_BUSY_TIME_8197F) \
+ << BIT_SHIFT_CHNL_BUSY_TIME_8197F)
+#define BITS_CHNL_BUSY_TIME_8197F \
+ (BIT_MASK_CHNL_BUSY_TIME_8197F << BIT_SHIFT_CHNL_BUSY_TIME_8197F)
+#define BIT_CLEAR_CHNL_BUSY_TIME_8197F(x) ((x) & (~BITS_CHNL_BUSY_TIME_8197F))
+#define BIT_GET_CHNL_BUSY_TIME_8197F(x) \
+ (((x) >> BIT_SHIFT_CHNL_BUSY_TIME_8197F) & \
+ BIT_MASK_CHNL_BUSY_TIME_8197F)
+#define BIT_SET_CHNL_BUSY_TIME_8197F(x, v) \
+ (BIT_CLEAR_CHNL_BUSY_TIME_8197F(x) | BIT_CHNL_BUSY_TIME_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_EDCA_VO_PARAM_8197F */
+
+#define BIT_SHIFT_TXOPLIMIT_8197F 16
+#define BIT_MASK_TXOPLIMIT_8197F 0x7ff
+#define BIT_TXOPLIMIT_8197F(x) \
+ (((x) & BIT_MASK_TXOPLIMIT_8197F) << BIT_SHIFT_TXOPLIMIT_8197F)
+#define BITS_TXOPLIMIT_8197F \
+ (BIT_MASK_TXOPLIMIT_8197F << BIT_SHIFT_TXOPLIMIT_8197F)
+#define BIT_CLEAR_TXOPLIMIT_8197F(x) ((x) & (~BITS_TXOPLIMIT_8197F))
+#define BIT_GET_TXOPLIMIT_8197F(x) \
+ (((x) >> BIT_SHIFT_TXOPLIMIT_8197F) & BIT_MASK_TXOPLIMIT_8197F)
+#define BIT_SET_TXOPLIMIT_8197F(x, v) \
+ (BIT_CLEAR_TXOPLIMIT_8197F(x) | BIT_TXOPLIMIT_8197F(v))
+
+#define BIT_SHIFT_CW_8197F 8
+#define BIT_MASK_CW_8197F 0xff
+#define BIT_CW_8197F(x) (((x) & BIT_MASK_CW_8197F) << BIT_SHIFT_CW_8197F)
+#define BITS_CW_8197F (BIT_MASK_CW_8197F << BIT_SHIFT_CW_8197F)
+#define BIT_CLEAR_CW_8197F(x) ((x) & (~BITS_CW_8197F))
+#define BIT_GET_CW_8197F(x) (((x) >> BIT_SHIFT_CW_8197F) & BIT_MASK_CW_8197F)
+#define BIT_SET_CW_8197F(x, v) (BIT_CLEAR_CW_8197F(x) | BIT_CW_8197F(v))
+
+#define BIT_SHIFT_AIFS_8197F 0
+#define BIT_MASK_AIFS_8197F 0xff
+#define BIT_AIFS_8197F(x) (((x) & BIT_MASK_AIFS_8197F) << BIT_SHIFT_AIFS_8197F)
+#define BITS_AIFS_8197F (BIT_MASK_AIFS_8197F << BIT_SHIFT_AIFS_8197F)
+#define BIT_CLEAR_AIFS_8197F(x) ((x) & (~BITS_AIFS_8197F))
+#define BIT_GET_AIFS_8197F(x) \
+ (((x) >> BIT_SHIFT_AIFS_8197F) & BIT_MASK_AIFS_8197F)
+#define BIT_SET_AIFS_8197F(x, v) (BIT_CLEAR_AIFS_8197F(x) | BIT_AIFS_8197F(v))
+
+/* 2 REG_EDCA_VI_PARAM_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+#define BIT_SHIFT_TXOPLIMIT_8197F 16
+#define BIT_MASK_TXOPLIMIT_8197F 0x7ff
+#define BIT_TXOPLIMIT_8197F(x) \
+ (((x) & BIT_MASK_TXOPLIMIT_8197F) << BIT_SHIFT_TXOPLIMIT_8197F)
+#define BITS_TXOPLIMIT_8197F \
+ (BIT_MASK_TXOPLIMIT_8197F << BIT_SHIFT_TXOPLIMIT_8197F)
+#define BIT_CLEAR_TXOPLIMIT_8197F(x) ((x) & (~BITS_TXOPLIMIT_8197F))
+#define BIT_GET_TXOPLIMIT_8197F(x) \
+ (((x) >> BIT_SHIFT_TXOPLIMIT_8197F) & BIT_MASK_TXOPLIMIT_8197F)
+#define BIT_SET_TXOPLIMIT_8197F(x, v) \
+ (BIT_CLEAR_TXOPLIMIT_8197F(x) | BIT_TXOPLIMIT_8197F(v))
+
+#define BIT_SHIFT_CW_8197F 8
+#define BIT_MASK_CW_8197F 0xff
+#define BIT_CW_8197F(x) (((x) & BIT_MASK_CW_8197F) << BIT_SHIFT_CW_8197F)
+#define BITS_CW_8197F (BIT_MASK_CW_8197F << BIT_SHIFT_CW_8197F)
+#define BIT_CLEAR_CW_8197F(x) ((x) & (~BITS_CW_8197F))
+#define BIT_GET_CW_8197F(x) (((x) >> BIT_SHIFT_CW_8197F) & BIT_MASK_CW_8197F)
+#define BIT_SET_CW_8197F(x, v) (BIT_CLEAR_CW_8197F(x) | BIT_CW_8197F(v))
+
+#define BIT_SHIFT_AIFS_8197F 0
+#define BIT_MASK_AIFS_8197F 0xff
+#define BIT_AIFS_8197F(x) (((x) & BIT_MASK_AIFS_8197F) << BIT_SHIFT_AIFS_8197F)
+#define BITS_AIFS_8197F (BIT_MASK_AIFS_8197F << BIT_SHIFT_AIFS_8197F)
+#define BIT_CLEAR_AIFS_8197F(x) ((x) & (~BITS_AIFS_8197F))
+#define BIT_GET_AIFS_8197F(x) \
+ (((x) >> BIT_SHIFT_AIFS_8197F) & BIT_MASK_AIFS_8197F)
+#define BIT_SET_AIFS_8197F(x, v) (BIT_CLEAR_AIFS_8197F(x) | BIT_AIFS_8197F(v))
+
+/* 2 REG_EDCA_BE_PARAM_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+#define BIT_SHIFT_TXOPLIMIT_8197F 16
+#define BIT_MASK_TXOPLIMIT_8197F 0x7ff
+#define BIT_TXOPLIMIT_8197F(x) \
+ (((x) & BIT_MASK_TXOPLIMIT_8197F) << BIT_SHIFT_TXOPLIMIT_8197F)
+#define BITS_TXOPLIMIT_8197F \
+ (BIT_MASK_TXOPLIMIT_8197F << BIT_SHIFT_TXOPLIMIT_8197F)
+#define BIT_CLEAR_TXOPLIMIT_8197F(x) ((x) & (~BITS_TXOPLIMIT_8197F))
+#define BIT_GET_TXOPLIMIT_8197F(x) \
+ (((x) >> BIT_SHIFT_TXOPLIMIT_8197F) & BIT_MASK_TXOPLIMIT_8197F)
+#define BIT_SET_TXOPLIMIT_8197F(x, v) \
+ (BIT_CLEAR_TXOPLIMIT_8197F(x) | BIT_TXOPLIMIT_8197F(v))
+
+#define BIT_SHIFT_CW_8197F 8
+#define BIT_MASK_CW_8197F 0xff
+#define BIT_CW_8197F(x) (((x) & BIT_MASK_CW_8197F) << BIT_SHIFT_CW_8197F)
+#define BITS_CW_8197F (BIT_MASK_CW_8197F << BIT_SHIFT_CW_8197F)
+#define BIT_CLEAR_CW_8197F(x) ((x) & (~BITS_CW_8197F))
+#define BIT_GET_CW_8197F(x) (((x) >> BIT_SHIFT_CW_8197F) & BIT_MASK_CW_8197F)
+#define BIT_SET_CW_8197F(x, v) (BIT_CLEAR_CW_8197F(x) | BIT_CW_8197F(v))
+
+#define BIT_SHIFT_AIFS_8197F 0
+#define BIT_MASK_AIFS_8197F 0xff
+#define BIT_AIFS_8197F(x) (((x) & BIT_MASK_AIFS_8197F) << BIT_SHIFT_AIFS_8197F)
+#define BITS_AIFS_8197F (BIT_MASK_AIFS_8197F << BIT_SHIFT_AIFS_8197F)
+#define BIT_CLEAR_AIFS_8197F(x) ((x) & (~BITS_AIFS_8197F))
+#define BIT_GET_AIFS_8197F(x) \
+ (((x) >> BIT_SHIFT_AIFS_8197F) & BIT_MASK_AIFS_8197F)
+#define BIT_SET_AIFS_8197F(x, v) (BIT_CLEAR_AIFS_8197F(x) | BIT_AIFS_8197F(v))
+
+/* 2 REG_EDCA_BK_PARAM_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+#define BIT_SHIFT_TXOPLIMIT_8197F 16
+#define BIT_MASK_TXOPLIMIT_8197F 0x7ff
+#define BIT_TXOPLIMIT_8197F(x) \
+ (((x) & BIT_MASK_TXOPLIMIT_8197F) << BIT_SHIFT_TXOPLIMIT_8197F)
+#define BITS_TXOPLIMIT_8197F \
+ (BIT_MASK_TXOPLIMIT_8197F << BIT_SHIFT_TXOPLIMIT_8197F)
+#define BIT_CLEAR_TXOPLIMIT_8197F(x) ((x) & (~BITS_TXOPLIMIT_8197F))
+#define BIT_GET_TXOPLIMIT_8197F(x) \
+ (((x) >> BIT_SHIFT_TXOPLIMIT_8197F) & BIT_MASK_TXOPLIMIT_8197F)
+#define BIT_SET_TXOPLIMIT_8197F(x, v) \
+ (BIT_CLEAR_TXOPLIMIT_8197F(x) | BIT_TXOPLIMIT_8197F(v))
+
+#define BIT_SHIFT_CW_8197F 8
+#define BIT_MASK_CW_8197F 0xff
+#define BIT_CW_8197F(x) (((x) & BIT_MASK_CW_8197F) << BIT_SHIFT_CW_8197F)
+#define BITS_CW_8197F (BIT_MASK_CW_8197F << BIT_SHIFT_CW_8197F)
+#define BIT_CLEAR_CW_8197F(x) ((x) & (~BITS_CW_8197F))
+#define BIT_GET_CW_8197F(x) (((x) >> BIT_SHIFT_CW_8197F) & BIT_MASK_CW_8197F)
+#define BIT_SET_CW_8197F(x, v) (BIT_CLEAR_CW_8197F(x) | BIT_CW_8197F(v))
+
+#define BIT_SHIFT_AIFS_8197F 0
+#define BIT_MASK_AIFS_8197F 0xff
+#define BIT_AIFS_8197F(x) (((x) & BIT_MASK_AIFS_8197F) << BIT_SHIFT_AIFS_8197F)
+#define BITS_AIFS_8197F (BIT_MASK_AIFS_8197F << BIT_SHIFT_AIFS_8197F)
+#define BIT_CLEAR_AIFS_8197F(x) ((x) & (~BITS_AIFS_8197F))
+#define BIT_GET_AIFS_8197F(x) \
+ (((x) >> BIT_SHIFT_AIFS_8197F) & BIT_MASK_AIFS_8197F)
+#define BIT_SET_AIFS_8197F(x, v) (BIT_CLEAR_AIFS_8197F(x) | BIT_AIFS_8197F(v))
+
+/* 2 REG_BCNTCFG_8197F */
+
+#define BIT_SHIFT_BCNCW_MAX_8197F 12
+#define BIT_MASK_BCNCW_MAX_8197F 0xf
+#define BIT_BCNCW_MAX_8197F(x) \
+ (((x) & BIT_MASK_BCNCW_MAX_8197F) << BIT_SHIFT_BCNCW_MAX_8197F)
+#define BITS_BCNCW_MAX_8197F \
+ (BIT_MASK_BCNCW_MAX_8197F << BIT_SHIFT_BCNCW_MAX_8197F)
+#define BIT_CLEAR_BCNCW_MAX_8197F(x) ((x) & (~BITS_BCNCW_MAX_8197F))
+#define BIT_GET_BCNCW_MAX_8197F(x) \
+ (((x) >> BIT_SHIFT_BCNCW_MAX_8197F) & BIT_MASK_BCNCW_MAX_8197F)
+#define BIT_SET_BCNCW_MAX_8197F(x, v) \
+ (BIT_CLEAR_BCNCW_MAX_8197F(x) | BIT_BCNCW_MAX_8197F(v))
+
+#define BIT_SHIFT_BCNCW_MIN_8197F 8
+#define BIT_MASK_BCNCW_MIN_8197F 0xf
+#define BIT_BCNCW_MIN_8197F(x) \
+ (((x) & BIT_MASK_BCNCW_MIN_8197F) << BIT_SHIFT_BCNCW_MIN_8197F)
+#define BITS_BCNCW_MIN_8197F \
+ (BIT_MASK_BCNCW_MIN_8197F << BIT_SHIFT_BCNCW_MIN_8197F)
+#define BIT_CLEAR_BCNCW_MIN_8197F(x) ((x) & (~BITS_BCNCW_MIN_8197F))
+#define BIT_GET_BCNCW_MIN_8197F(x) \
+ (((x) >> BIT_SHIFT_BCNCW_MIN_8197F) & BIT_MASK_BCNCW_MIN_8197F)
+#define BIT_SET_BCNCW_MIN_8197F(x, v) \
+ (BIT_CLEAR_BCNCW_MIN_8197F(x) | BIT_BCNCW_MIN_8197F(v))
+
+#define BIT_SHIFT_BCNIFS_8197F 0
+#define BIT_MASK_BCNIFS_8197F 0xff
+#define BIT_BCNIFS_8197F(x) \
+ (((x) & BIT_MASK_BCNIFS_8197F) << BIT_SHIFT_BCNIFS_8197F)
+#define BITS_BCNIFS_8197F (BIT_MASK_BCNIFS_8197F << BIT_SHIFT_BCNIFS_8197F)
+#define BIT_CLEAR_BCNIFS_8197F(x) ((x) & (~BITS_BCNIFS_8197F))
+#define BIT_GET_BCNIFS_8197F(x) \
+ (((x) >> BIT_SHIFT_BCNIFS_8197F) & BIT_MASK_BCNIFS_8197F)
+#define BIT_SET_BCNIFS_8197F(x, v) \
+ (BIT_CLEAR_BCNIFS_8197F(x) | BIT_BCNIFS_8197F(v))
+
+/* 2 REG_PIFS_8197F */
+
+#define BIT_SHIFT_PIFS_8197F 0
+#define BIT_MASK_PIFS_8197F 0xff
+#define BIT_PIFS_8197F(x) (((x) & BIT_MASK_PIFS_8197F) << BIT_SHIFT_PIFS_8197F)
+#define BITS_PIFS_8197F (BIT_MASK_PIFS_8197F << BIT_SHIFT_PIFS_8197F)
+#define BIT_CLEAR_PIFS_8197F(x) ((x) & (~BITS_PIFS_8197F))
+#define BIT_GET_PIFS_8197F(x) \
+ (((x) >> BIT_SHIFT_PIFS_8197F) & BIT_MASK_PIFS_8197F)
+#define BIT_SET_PIFS_8197F(x, v) (BIT_CLEAR_PIFS_8197F(x) | BIT_PIFS_8197F(v))
+
+/* 2 REG_RDG_PIFS_8197F */
+
+#define BIT_SHIFT_RDG_PIFS_8197F 0
+#define BIT_MASK_RDG_PIFS_8197F 0xff
+#define BIT_RDG_PIFS_8197F(x) \
+ (((x) & BIT_MASK_RDG_PIFS_8197F) << BIT_SHIFT_RDG_PIFS_8197F)
+#define BITS_RDG_PIFS_8197F \
+ (BIT_MASK_RDG_PIFS_8197F << BIT_SHIFT_RDG_PIFS_8197F)
+#define BIT_CLEAR_RDG_PIFS_8197F(x) ((x) & (~BITS_RDG_PIFS_8197F))
+#define BIT_GET_RDG_PIFS_8197F(x) \
+ (((x) >> BIT_SHIFT_RDG_PIFS_8197F) & BIT_MASK_RDG_PIFS_8197F)
+#define BIT_SET_RDG_PIFS_8197F(x, v) \
+ (BIT_CLEAR_RDG_PIFS_8197F(x) | BIT_RDG_PIFS_8197F(v))
+
+/* 2 REG_SIFS_8197F */
+
+#define BIT_SHIFT_SIFS_OFDM_TRX_8197F 24
+#define BIT_MASK_SIFS_OFDM_TRX_8197F 0xff
+#define BIT_SIFS_OFDM_TRX_8197F(x) \
+ (((x) & BIT_MASK_SIFS_OFDM_TRX_8197F) << BIT_SHIFT_SIFS_OFDM_TRX_8197F)
+#define BITS_SIFS_OFDM_TRX_8197F \
+ (BIT_MASK_SIFS_OFDM_TRX_8197F << BIT_SHIFT_SIFS_OFDM_TRX_8197F)
+#define BIT_CLEAR_SIFS_OFDM_TRX_8197F(x) ((x) & (~BITS_SIFS_OFDM_TRX_8197F))
+#define BIT_GET_SIFS_OFDM_TRX_8197F(x) \
+ (((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8197F) & BIT_MASK_SIFS_OFDM_TRX_8197F)
+#define BIT_SET_SIFS_OFDM_TRX_8197F(x, v) \
+ (BIT_CLEAR_SIFS_OFDM_TRX_8197F(x) | BIT_SIFS_OFDM_TRX_8197F(v))
+
+#define BIT_SHIFT_SIFS_CCK_TRX_8197F 16
+#define BIT_MASK_SIFS_CCK_TRX_8197F 0xff
+#define BIT_SIFS_CCK_TRX_8197F(x) \
+ (((x) & BIT_MASK_SIFS_CCK_TRX_8197F) << BIT_SHIFT_SIFS_CCK_TRX_8197F)
+#define BITS_SIFS_CCK_TRX_8197F \
+ (BIT_MASK_SIFS_CCK_TRX_8197F << BIT_SHIFT_SIFS_CCK_TRX_8197F)
+#define BIT_CLEAR_SIFS_CCK_TRX_8197F(x) ((x) & (~BITS_SIFS_CCK_TRX_8197F))
+#define BIT_GET_SIFS_CCK_TRX_8197F(x) \
+ (((x) >> BIT_SHIFT_SIFS_CCK_TRX_8197F) & BIT_MASK_SIFS_CCK_TRX_8197F)
+#define BIT_SET_SIFS_CCK_TRX_8197F(x, v) \
+ (BIT_CLEAR_SIFS_CCK_TRX_8197F(x) | BIT_SIFS_CCK_TRX_8197F(v))
+
+#define BIT_SHIFT_SIFS_OFDM_CTX_8197F 8
+#define BIT_MASK_SIFS_OFDM_CTX_8197F 0xff
+#define BIT_SIFS_OFDM_CTX_8197F(x) \
+ (((x) & BIT_MASK_SIFS_OFDM_CTX_8197F) << BIT_SHIFT_SIFS_OFDM_CTX_8197F)
+#define BITS_SIFS_OFDM_CTX_8197F \
+ (BIT_MASK_SIFS_OFDM_CTX_8197F << BIT_SHIFT_SIFS_OFDM_CTX_8197F)
+#define BIT_CLEAR_SIFS_OFDM_CTX_8197F(x) ((x) & (~BITS_SIFS_OFDM_CTX_8197F))
+#define BIT_GET_SIFS_OFDM_CTX_8197F(x) \
+ (((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8197F) & BIT_MASK_SIFS_OFDM_CTX_8197F)
+#define BIT_SET_SIFS_OFDM_CTX_8197F(x, v) \
+ (BIT_CLEAR_SIFS_OFDM_CTX_8197F(x) | BIT_SIFS_OFDM_CTX_8197F(v))
+
+#define BIT_SHIFT_SIFS_CCK_CTX_8197F 0
+#define BIT_MASK_SIFS_CCK_CTX_8197F 0xff
+#define BIT_SIFS_CCK_CTX_8197F(x) \
+ (((x) & BIT_MASK_SIFS_CCK_CTX_8197F) << BIT_SHIFT_SIFS_CCK_CTX_8197F)
+#define BITS_SIFS_CCK_CTX_8197F \
+ (BIT_MASK_SIFS_CCK_CTX_8197F << BIT_SHIFT_SIFS_CCK_CTX_8197F)
+#define BIT_CLEAR_SIFS_CCK_CTX_8197F(x) ((x) & (~BITS_SIFS_CCK_CTX_8197F))
+#define BIT_GET_SIFS_CCK_CTX_8197F(x) \
+ (((x) >> BIT_SHIFT_SIFS_CCK_CTX_8197F) & BIT_MASK_SIFS_CCK_CTX_8197F)
+#define BIT_SET_SIFS_CCK_CTX_8197F(x, v) \
+ (BIT_CLEAR_SIFS_CCK_CTX_8197F(x) | BIT_SIFS_CCK_CTX_8197F(v))
+
+/* 2 REG_TSFTR_SYN_OFFSET_8197F */
+
+#define BIT_SHIFT_TSFTR_SNC_OFFSET_8197F 0
+#define BIT_MASK_TSFTR_SNC_OFFSET_8197F 0xffff
+#define BIT_TSFTR_SNC_OFFSET_8197F(x) \
+ (((x) & BIT_MASK_TSFTR_SNC_OFFSET_8197F) \
+ << BIT_SHIFT_TSFTR_SNC_OFFSET_8197F)
+#define BITS_TSFTR_SNC_OFFSET_8197F \
+ (BIT_MASK_TSFTR_SNC_OFFSET_8197F << BIT_SHIFT_TSFTR_SNC_OFFSET_8197F)
+#define BIT_CLEAR_TSFTR_SNC_OFFSET_8197F(x) \
+ ((x) & (~BITS_TSFTR_SNC_OFFSET_8197F))
+#define BIT_GET_TSFTR_SNC_OFFSET_8197F(x) \
+ (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_8197F) & \
+ BIT_MASK_TSFTR_SNC_OFFSET_8197F)
+#define BIT_SET_TSFTR_SNC_OFFSET_8197F(x, v) \
+ (BIT_CLEAR_TSFTR_SNC_OFFSET_8197F(x) | BIT_TSFTR_SNC_OFFSET_8197F(v))
+
+/* 2 REG_AGGR_BREAK_TIME_8197F */
+
+#define BIT_SHIFT_AGGR_BK_TIME_8197F 0
+#define BIT_MASK_AGGR_BK_TIME_8197F 0xff
+#define BIT_AGGR_BK_TIME_8197F(x) \
+ (((x) & BIT_MASK_AGGR_BK_TIME_8197F) << BIT_SHIFT_AGGR_BK_TIME_8197F)
+#define BITS_AGGR_BK_TIME_8197F \
+ (BIT_MASK_AGGR_BK_TIME_8197F << BIT_SHIFT_AGGR_BK_TIME_8197F)
+#define BIT_CLEAR_AGGR_BK_TIME_8197F(x) ((x) & (~BITS_AGGR_BK_TIME_8197F))
+#define BIT_GET_AGGR_BK_TIME_8197F(x) \
+ (((x) >> BIT_SHIFT_AGGR_BK_TIME_8197F) & BIT_MASK_AGGR_BK_TIME_8197F)
+#define BIT_SET_AGGR_BK_TIME_8197F(x, v) \
+ (BIT_CLEAR_AGGR_BK_TIME_8197F(x) | BIT_AGGR_BK_TIME_8197F(v))
+
+/* 2 REG_SLOT_8197F */
+
+#define BIT_SHIFT_SLOT_8197F 0
+#define BIT_MASK_SLOT_8197F 0xff
+#define BIT_SLOT_8197F(x) (((x) & BIT_MASK_SLOT_8197F) << BIT_SHIFT_SLOT_8197F)
+#define BITS_SLOT_8197F (BIT_MASK_SLOT_8197F << BIT_SHIFT_SLOT_8197F)
+#define BIT_CLEAR_SLOT_8197F(x) ((x) & (~BITS_SLOT_8197F))
+#define BIT_GET_SLOT_8197F(x) \
+ (((x) >> BIT_SHIFT_SLOT_8197F) & BIT_MASK_SLOT_8197F)
+#define BIT_SET_SLOT_8197F(x, v) (BIT_CLEAR_SLOT_8197F(x) | BIT_SLOT_8197F(v))
+
+/* 2 REG_TX_PTCL_CTRL_8197F */
+#define BIT_DIS_EDCCA_8197F BIT(15)
+#define BIT_DIS_CCA_8197F BIT(14)
+#define BIT_LSIG_TXOP_TXCMD_NAV_8197F BIT(13)
+#define BIT_SIFS_BK_EN_8197F BIT(12)
+
+#define BIT_SHIFT_TXQ_NAV_MSK_8197F 8
+#define BIT_MASK_TXQ_NAV_MSK_8197F 0xf
+#define BIT_TXQ_NAV_MSK_8197F(x) \
+ (((x) & BIT_MASK_TXQ_NAV_MSK_8197F) << BIT_SHIFT_TXQ_NAV_MSK_8197F)
+#define BITS_TXQ_NAV_MSK_8197F \
+ (BIT_MASK_TXQ_NAV_MSK_8197F << BIT_SHIFT_TXQ_NAV_MSK_8197F)
+#define BIT_CLEAR_TXQ_NAV_MSK_8197F(x) ((x) & (~BITS_TXQ_NAV_MSK_8197F))
+#define BIT_GET_TXQ_NAV_MSK_8197F(x) \
+ (((x) >> BIT_SHIFT_TXQ_NAV_MSK_8197F) & BIT_MASK_TXQ_NAV_MSK_8197F)
+#define BIT_SET_TXQ_NAV_MSK_8197F(x, v) \
+ (BIT_CLEAR_TXQ_NAV_MSK_8197F(x) | BIT_TXQ_NAV_MSK_8197F(v))
+
+#define BIT_DIS_CW_8197F BIT(7)
+#define BIT_NAV_END_TXOP_8197F BIT(6)
+#define BIT_RDG_END_TXOP_8197F BIT(5)
+#define BIT_AC_INBCN_HOLD_8197F BIT(4)
+#define BIT_MGTQ_TXOP_EN_8197F BIT(3)
+#define BIT_MGTQ_RTSMF_EN_8197F BIT(2)
+#define BIT_HIQ_RTSMF_EN_8197F BIT(1)
+#define BIT_BCN_RTSMF_EN_8197F BIT(0)
+
+/* 2 REG_TXPAUSE_8197F */
+#define BIT_STOP_BCN_HI_MGT_8197F BIT(7)
+#define BIT_MAC_STOPBCNQ_8197F BIT(6)
+#define BIT_MAC_STOPHIQ_8197F BIT(5)
+#define BIT_MAC_STOPMGQ_8197F BIT(4)
+#define BIT_MAC_STOPBK_8197F BIT(3)
+#define BIT_MAC_STOPBE_8197F BIT(2)
+#define BIT_MAC_STOPVI_8197F BIT(1)
+#define BIT_MAC_STOPVO_8197F BIT(0)
+
+/* 2 REG_DIS_TXREQ_CLR_8197F */
+#define BIT_DIS_BT_CCA_8197F BIT(7)
+#define BIT_DIS_TXREQ_CLR_CPUMGQ_8197F BIT(6)
+#define BIT_DIS_TXREQ_CLR_HI_8197F BIT(5)
+#define BIT_DIS_TXREQ_CLR_MGQ_8197F BIT(4)
+#define BIT_DIS_TXREQ_CLR_VO_8197F BIT(3)
+#define BIT_DIS_TXREQ_CLR_VI_8197F BIT(2)
+#define BIT_DIS_TXREQ_CLR_BE_8197F BIT(1)
+#define BIT_DIS_TXREQ_CLR_BK_8197F BIT(0)
+
+/* 2 REG_RD_CTRL_8197F */
+#define BIT_EN_CLR_TXREQ_INCCA_8197F BIT(15)
+#define BIT_DIS_TX_OVER_BCNQ_8197F BIT(14)
+#define BIT_EN_BCNERR_INCCA_8197F BIT(13)
+#define BIT_EN_BCNERR_INEDCCA_8197F BIT(12)
+#define BIT_EDCCA_MSK_CNTDOWN_EN_8197F BIT(11)
+#define BIT_DIS_TXOP_CFE_8197F BIT(10)
+#define BIT_DIS_LSIG_CFE_8197F BIT(9)
+#define BIT_DIS_STBC_CFE_8197F BIT(8)
+#define BIT_BKQ_RD_INIT_EN_8197F BIT(7)
+#define BIT_BEQ_RD_INIT_EN_8197F BIT(6)
+#define BIT_VIQ_RD_INIT_EN_8197F BIT(5)
+#define BIT_VOQ_RD_INIT_EN_8197F BIT(4)
+#define BIT_BKQ_RD_RESP_EN_8197F BIT(3)
+#define BIT_BEQ_RD_RESP_EN_8197F BIT(2)
+#define BIT_VIQ_RD_RESP_EN_8197F BIT(1)
+#define BIT_VOQ_RD_RESP_EN_8197F BIT(0)
+
+/* 2 REG_MBSSID_CTRL_8197F */
+#define BIT_MBID_BCNQ7_EN_8197F BIT(7)
+#define BIT_MBID_BCNQ6_EN_8197F BIT(6)
+#define BIT_MBID_BCNQ5_EN_8197F BIT(5)
+#define BIT_MBID_BCNQ4_EN_8197F BIT(4)
+#define BIT_MBID_BCNQ3_EN_8197F BIT(3)
+#define BIT_MBID_BCNQ2_EN_8197F BIT(2)
+#define BIT_MBID_BCNQ1_EN_8197F BIT(1)
+#define BIT_MBID_BCNQ0_EN_8197F BIT(0)
+
+/* 2 REG_P2PPS_CTRL_8197F */
+#define BIT_P2P_CTW_ALLSTASLEEP_8197F BIT(7)
+#define BIT_P2P_OFF_DISTX_EN_8197F BIT(6)
+#define BIT_PWR_MGT_EN_8197F BIT(5)
+#define BIT_P2P_NOA1_EN_8197F BIT(2)
+#define BIT_P2P_NOA0_EN_8197F BIT(1)
+
+/* 2 REG_PKT_LIFETIME_CTRL_8197F */
+#define BIT_EN_TBTT_AREA_FOR_BB_8197F BIT(23)
+#define BIT_EN_BKF_CLR_TXREQ_8197F BIT(22)
+#define BIT_EN_TSFBIT32_RST_P2P_8197F BIT(21)
+#define BIT_EN_BCN_TX_BTCCA_8197F BIT(20)
+#define BIT_DIS_PKT_TX_ATIM_8197F BIT(19)
+#define BIT_DIS_BCN_DIS_CTN_8197F BIT(18)
+#define BIT_EN_NAVEND_RST_TXOP_8197F BIT(17)
+#define BIT_EN_FILTER_CCA_8197F BIT(16)
+
+#define BIT_SHIFT_CCA_FILTER_THRS_8197F 8
+#define BIT_MASK_CCA_FILTER_THRS_8197F 0xff
+#define BIT_CCA_FILTER_THRS_8197F(x) \
+ (((x) & BIT_MASK_CCA_FILTER_THRS_8197F) \
+ << BIT_SHIFT_CCA_FILTER_THRS_8197F)
+#define BITS_CCA_FILTER_THRS_8197F \
+ (BIT_MASK_CCA_FILTER_THRS_8197F << BIT_SHIFT_CCA_FILTER_THRS_8197F)
+#define BIT_CLEAR_CCA_FILTER_THRS_8197F(x) ((x) & (~BITS_CCA_FILTER_THRS_8197F))
+#define BIT_GET_CCA_FILTER_THRS_8197F(x) \
+ (((x) >> BIT_SHIFT_CCA_FILTER_THRS_8197F) & \
+ BIT_MASK_CCA_FILTER_THRS_8197F)
+#define BIT_SET_CCA_FILTER_THRS_8197F(x, v) \
+ (BIT_CLEAR_CCA_FILTER_THRS_8197F(x) | BIT_CCA_FILTER_THRS_8197F(v))
+
+#define BIT_SHIFT_EDCCA_THRS_8197F 0
+#define BIT_MASK_EDCCA_THRS_8197F 0xff
+#define BIT_EDCCA_THRS_8197F(x) \
+ (((x) & BIT_MASK_EDCCA_THRS_8197F) << BIT_SHIFT_EDCCA_THRS_8197F)
+#define BITS_EDCCA_THRS_8197F \
+ (BIT_MASK_EDCCA_THRS_8197F << BIT_SHIFT_EDCCA_THRS_8197F)
+#define BIT_CLEAR_EDCCA_THRS_8197F(x) ((x) & (~BITS_EDCCA_THRS_8197F))
+#define BIT_GET_EDCCA_THRS_8197F(x) \
+ (((x) >> BIT_SHIFT_EDCCA_THRS_8197F) & BIT_MASK_EDCCA_THRS_8197F)
+#define BIT_SET_EDCCA_THRS_8197F(x, v) \
+ (BIT_CLEAR_EDCCA_THRS_8197F(x) | BIT_EDCCA_THRS_8197F(v))
+
+/* 2 REG_P2PPS_SPEC_STATE_8197F */
+#define BIT_SPEC_POWER_STATE_8197F BIT(7)
+#define BIT_SPEC_CTWINDOW_ON_8197F BIT(6)
+#define BIT_SPEC_BEACON_AREA_ON_8197F BIT(5)
+#define BIT_SPEC_CTWIN_EARLY_DISTX_8197F BIT(4)
+#define BIT_SPEC_NOA1_OFF_PERIOD_8197F BIT(3)
+#define BIT_SPEC_FORCE_DOZE1_8197F BIT(2)
+#define BIT_SPEC_NOA0_OFF_PERIOD_8197F BIT(1)
+#define BIT_SPEC_FORCE_DOZE0_8197F BIT(0)
+
+/* 2 REG_NOT_VALID_8197F */
+
+#define BIT_SHIFT_P2PON_DIS_TXTIME_8197F 0
+#define BIT_MASK_P2PON_DIS_TXTIME_8197F 0xff
+#define BIT_P2PON_DIS_TXTIME_8197F(x) \
+ (((x) & BIT_MASK_P2PON_DIS_TXTIME_8197F) \
+ << BIT_SHIFT_P2PON_DIS_TXTIME_8197F)
+#define BITS_P2PON_DIS_TXTIME_8197F \
+ (BIT_MASK_P2PON_DIS_TXTIME_8197F << BIT_SHIFT_P2PON_DIS_TXTIME_8197F)
+#define BIT_CLEAR_P2PON_DIS_TXTIME_8197F(x) \
+ ((x) & (~BITS_P2PON_DIS_TXTIME_8197F))
+#define BIT_GET_P2PON_DIS_TXTIME_8197F(x) \
+ (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8197F) & \
+ BIT_MASK_P2PON_DIS_TXTIME_8197F)
+#define BIT_SET_P2PON_DIS_TXTIME_8197F(x, v) \
+ (BIT_CLEAR_P2PON_DIS_TXTIME_8197F(x) | BIT_P2PON_DIS_TXTIME_8197F(v))
+
+/* 2 REG_QUEUE_INCOL_THR_8197F */
+
+#define BIT_SHIFT_BK_QUEUE_THR_8197F 24
+#define BIT_MASK_BK_QUEUE_THR_8197F 0xff
+#define BIT_BK_QUEUE_THR_8197F(x) \
+ (((x) & BIT_MASK_BK_QUEUE_THR_8197F) << BIT_SHIFT_BK_QUEUE_THR_8197F)
+#define BITS_BK_QUEUE_THR_8197F \
+ (BIT_MASK_BK_QUEUE_THR_8197F << BIT_SHIFT_BK_QUEUE_THR_8197F)
+#define BIT_CLEAR_BK_QUEUE_THR_8197F(x) ((x) & (~BITS_BK_QUEUE_THR_8197F))
+#define BIT_GET_BK_QUEUE_THR_8197F(x) \
+ (((x) >> BIT_SHIFT_BK_QUEUE_THR_8197F) & BIT_MASK_BK_QUEUE_THR_8197F)
+#define BIT_SET_BK_QUEUE_THR_8197F(x, v) \
+ (BIT_CLEAR_BK_QUEUE_THR_8197F(x) | BIT_BK_QUEUE_THR_8197F(v))
+
+#define BIT_SHIFT_BE_QUEUE_THR_8197F 16
+#define BIT_MASK_BE_QUEUE_THR_8197F 0xff
+#define BIT_BE_QUEUE_THR_8197F(x) \
+ (((x) & BIT_MASK_BE_QUEUE_THR_8197F) << BIT_SHIFT_BE_QUEUE_THR_8197F)
+#define BITS_BE_QUEUE_THR_8197F \
+ (BIT_MASK_BE_QUEUE_THR_8197F << BIT_SHIFT_BE_QUEUE_THR_8197F)
+#define BIT_CLEAR_BE_QUEUE_THR_8197F(x) ((x) & (~BITS_BE_QUEUE_THR_8197F))
+#define BIT_GET_BE_QUEUE_THR_8197F(x) \
+ (((x) >> BIT_SHIFT_BE_QUEUE_THR_8197F) & BIT_MASK_BE_QUEUE_THR_8197F)
+#define BIT_SET_BE_QUEUE_THR_8197F(x, v) \
+ (BIT_CLEAR_BE_QUEUE_THR_8197F(x) | BIT_BE_QUEUE_THR_8197F(v))
+
+#define BIT_SHIFT_VI_QUEUE_THR_8197F 8
+#define BIT_MASK_VI_QUEUE_THR_8197F 0xff
+#define BIT_VI_QUEUE_THR_8197F(x) \
+ (((x) & BIT_MASK_VI_QUEUE_THR_8197F) << BIT_SHIFT_VI_QUEUE_THR_8197F)
+#define BITS_VI_QUEUE_THR_8197F \
+ (BIT_MASK_VI_QUEUE_THR_8197F << BIT_SHIFT_VI_QUEUE_THR_8197F)
+#define BIT_CLEAR_VI_QUEUE_THR_8197F(x) ((x) & (~BITS_VI_QUEUE_THR_8197F))
+#define BIT_GET_VI_QUEUE_THR_8197F(x) \
+ (((x) >> BIT_SHIFT_VI_QUEUE_THR_8197F) & BIT_MASK_VI_QUEUE_THR_8197F)
+#define BIT_SET_VI_QUEUE_THR_8197F(x, v) \
+ (BIT_CLEAR_VI_QUEUE_THR_8197F(x) | BIT_VI_QUEUE_THR_8197F(v))
+
+#define BIT_SHIFT_VO_QUEUE_THR_8197F 0
+#define BIT_MASK_VO_QUEUE_THR_8197F 0xff
+#define BIT_VO_QUEUE_THR_8197F(x) \
+ (((x) & BIT_MASK_VO_QUEUE_THR_8197F) << BIT_SHIFT_VO_QUEUE_THR_8197F)
+#define BITS_VO_QUEUE_THR_8197F \
+ (BIT_MASK_VO_QUEUE_THR_8197F << BIT_SHIFT_VO_QUEUE_THR_8197F)
+#define BIT_CLEAR_VO_QUEUE_THR_8197F(x) ((x) & (~BITS_VO_QUEUE_THR_8197F))
+#define BIT_GET_VO_QUEUE_THR_8197F(x) \
+ (((x) >> BIT_SHIFT_VO_QUEUE_THR_8197F) & BIT_MASK_VO_QUEUE_THR_8197F)
+#define BIT_SET_VO_QUEUE_THR_8197F(x, v) \
+ (BIT_CLEAR_VO_QUEUE_THR_8197F(x) | BIT_VO_QUEUE_THR_8197F(v))
+
+/* 2 REG_QUEUE_INCOL_EN_8197F */
+#define BIT_QUEUE_INCOL_EN_8197F BIT(16)
+
+#define BIT_SHIFT_BK_TRIGGER_NUM_V1_8197F 12
+#define BIT_MASK_BK_TRIGGER_NUM_V1_8197F 0xf
+#define BIT_BK_TRIGGER_NUM_V1_8197F(x) \
+ (((x) & BIT_MASK_BK_TRIGGER_NUM_V1_8197F) \
+ << BIT_SHIFT_BK_TRIGGER_NUM_V1_8197F)
+#define BITS_BK_TRIGGER_NUM_V1_8197F \
+ (BIT_MASK_BK_TRIGGER_NUM_V1_8197F << BIT_SHIFT_BK_TRIGGER_NUM_V1_8197F)
+#define BIT_CLEAR_BK_TRIGGER_NUM_V1_8197F(x) \
+ ((x) & (~BITS_BK_TRIGGER_NUM_V1_8197F))
+#define BIT_GET_BK_TRIGGER_NUM_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_BK_TRIGGER_NUM_V1_8197F) & \
+ BIT_MASK_BK_TRIGGER_NUM_V1_8197F)
+#define BIT_SET_BK_TRIGGER_NUM_V1_8197F(x, v) \
+ (BIT_CLEAR_BK_TRIGGER_NUM_V1_8197F(x) | BIT_BK_TRIGGER_NUM_V1_8197F(v))
+
+#define BIT_SHIFT_BE_TRIGGER_NUM_V1_8197F 8
+#define BIT_MASK_BE_TRIGGER_NUM_V1_8197F 0xf
+#define BIT_BE_TRIGGER_NUM_V1_8197F(x) \
+ (((x) & BIT_MASK_BE_TRIGGER_NUM_V1_8197F) \
+ << BIT_SHIFT_BE_TRIGGER_NUM_V1_8197F)
+#define BITS_BE_TRIGGER_NUM_V1_8197F \
+ (BIT_MASK_BE_TRIGGER_NUM_V1_8197F << BIT_SHIFT_BE_TRIGGER_NUM_V1_8197F)
+#define BIT_CLEAR_BE_TRIGGER_NUM_V1_8197F(x) \
+ ((x) & (~BITS_BE_TRIGGER_NUM_V1_8197F))
+#define BIT_GET_BE_TRIGGER_NUM_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_BE_TRIGGER_NUM_V1_8197F) & \
+ BIT_MASK_BE_TRIGGER_NUM_V1_8197F)
+#define BIT_SET_BE_TRIGGER_NUM_V1_8197F(x, v) \
+ (BIT_CLEAR_BE_TRIGGER_NUM_V1_8197F(x) | BIT_BE_TRIGGER_NUM_V1_8197F(v))
+
+#define BIT_SHIFT_VI_TRIGGER_NUM_8197F 4
+#define BIT_MASK_VI_TRIGGER_NUM_8197F 0xf
+#define BIT_VI_TRIGGER_NUM_8197F(x) \
+ (((x) & BIT_MASK_VI_TRIGGER_NUM_8197F) \
+ << BIT_SHIFT_VI_TRIGGER_NUM_8197F)
+#define BITS_VI_TRIGGER_NUM_8197F \
+ (BIT_MASK_VI_TRIGGER_NUM_8197F << BIT_SHIFT_VI_TRIGGER_NUM_8197F)
+#define BIT_CLEAR_VI_TRIGGER_NUM_8197F(x) ((x) & (~BITS_VI_TRIGGER_NUM_8197F))
+#define BIT_GET_VI_TRIGGER_NUM_8197F(x) \
+ (((x) >> BIT_SHIFT_VI_TRIGGER_NUM_8197F) & \
+ BIT_MASK_VI_TRIGGER_NUM_8197F)
+#define BIT_SET_VI_TRIGGER_NUM_8197F(x, v) \
+ (BIT_CLEAR_VI_TRIGGER_NUM_8197F(x) | BIT_VI_TRIGGER_NUM_8197F(v))
+
+#define BIT_SHIFT_VO_TRIGGER_NUM_8197F 0
+#define BIT_MASK_VO_TRIGGER_NUM_8197F 0xf
+#define BIT_VO_TRIGGER_NUM_8197F(x) \
+ (((x) & BIT_MASK_VO_TRIGGER_NUM_8197F) \
+ << BIT_SHIFT_VO_TRIGGER_NUM_8197F)
+#define BITS_VO_TRIGGER_NUM_8197F \
+ (BIT_MASK_VO_TRIGGER_NUM_8197F << BIT_SHIFT_VO_TRIGGER_NUM_8197F)
+#define BIT_CLEAR_VO_TRIGGER_NUM_8197F(x) ((x) & (~BITS_VO_TRIGGER_NUM_8197F))
+#define BIT_GET_VO_TRIGGER_NUM_8197F(x) \
+ (((x) >> BIT_SHIFT_VO_TRIGGER_NUM_8197F) & \
+ BIT_MASK_VO_TRIGGER_NUM_8197F)
+#define BIT_SET_VO_TRIGGER_NUM_8197F(x, v) \
+ (BIT_CLEAR_VO_TRIGGER_NUM_8197F(x) | BIT_VO_TRIGGER_NUM_8197F(v))
+
+/* 2 REG_TBTT_PROHIBIT_8197F */
+
+#define BIT_SHIFT_TBTT_HOLD_TIME_AP_8197F 8
+#define BIT_MASK_TBTT_HOLD_TIME_AP_8197F 0xfff
+#define BIT_TBTT_HOLD_TIME_AP_8197F(x) \
+ (((x) & BIT_MASK_TBTT_HOLD_TIME_AP_8197F) \
+ << BIT_SHIFT_TBTT_HOLD_TIME_AP_8197F)
+#define BITS_TBTT_HOLD_TIME_AP_8197F \
+ (BIT_MASK_TBTT_HOLD_TIME_AP_8197F << BIT_SHIFT_TBTT_HOLD_TIME_AP_8197F)
+#define BIT_CLEAR_TBTT_HOLD_TIME_AP_8197F(x) \
+ ((x) & (~BITS_TBTT_HOLD_TIME_AP_8197F))
+#define BIT_GET_TBTT_HOLD_TIME_AP_8197F(x) \
+ (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP_8197F) & \
+ BIT_MASK_TBTT_HOLD_TIME_AP_8197F)
+#define BIT_SET_TBTT_HOLD_TIME_AP_8197F(x, v) \
+ (BIT_CLEAR_TBTT_HOLD_TIME_AP_8197F(x) | BIT_TBTT_HOLD_TIME_AP_8197F(v))
+
+#define BIT_SHIFT_TBTT_PROHIBIT_SETUP_8197F 0
+#define BIT_MASK_TBTT_PROHIBIT_SETUP_8197F 0xf
+#define BIT_TBTT_PROHIBIT_SETUP_8197F(x) \
+ (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8197F) \
+ << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8197F)
+#define BITS_TBTT_PROHIBIT_SETUP_8197F \
+ (BIT_MASK_TBTT_PROHIBIT_SETUP_8197F \
+ << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8197F)
+#define BIT_CLEAR_TBTT_PROHIBIT_SETUP_8197F(x) \
+ ((x) & (~BITS_TBTT_PROHIBIT_SETUP_8197F))
+#define BIT_GET_TBTT_PROHIBIT_SETUP_8197F(x) \
+ (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8197F) & \
+ BIT_MASK_TBTT_PROHIBIT_SETUP_8197F)
+#define BIT_SET_TBTT_PROHIBIT_SETUP_8197F(x, v) \
+ (BIT_CLEAR_TBTT_PROHIBIT_SETUP_8197F(x) | \
+ BIT_TBTT_PROHIBIT_SETUP_8197F(v))
+
+/* 2 REG_P2PPS_STATE_8197F */
+#define BIT_POWER_STATE_8197F BIT(7)
+#define BIT_CTWINDOW_ON_8197F BIT(6)
+#define BIT_BEACON_AREA_ON_8197F BIT(5)
+#define BIT_CTWIN_EARLY_DISTX_8197F BIT(4)
+#define BIT_NOA1_OFF_PERIOD_8197F BIT(3)
+#define BIT_FORCE_DOZE1_8197F BIT(2)
+#define BIT_NOA0_OFF_PERIOD_8197F BIT(1)
+#define BIT_FORCE_DOZE0_8197F BIT(0)
+
+/* 2 REG_RD_NAV_NXT_8197F */
+
+#define BIT_SHIFT_RD_NAV_PROT_NXT_8197F 0
+#define BIT_MASK_RD_NAV_PROT_NXT_8197F 0xffff
+#define BIT_RD_NAV_PROT_NXT_8197F(x) \
+ (((x) & BIT_MASK_RD_NAV_PROT_NXT_8197F) \
+ << BIT_SHIFT_RD_NAV_PROT_NXT_8197F)
+#define BITS_RD_NAV_PROT_NXT_8197F \
+ (BIT_MASK_RD_NAV_PROT_NXT_8197F << BIT_SHIFT_RD_NAV_PROT_NXT_8197F)
+#define BIT_CLEAR_RD_NAV_PROT_NXT_8197F(x) ((x) & (~BITS_RD_NAV_PROT_NXT_8197F))
+#define BIT_GET_RD_NAV_PROT_NXT_8197F(x) \
+ (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8197F) & \
+ BIT_MASK_RD_NAV_PROT_NXT_8197F)
+#define BIT_SET_RD_NAV_PROT_NXT_8197F(x, v) \
+ (BIT_CLEAR_RD_NAV_PROT_NXT_8197F(x) | BIT_RD_NAV_PROT_NXT_8197F(v))
+
+/* 2 REG_NAV_PROT_LEN_8197F */
+
+#define BIT_SHIFT_NAV_PROT_LEN_8197F 0
+#define BIT_MASK_NAV_PROT_LEN_8197F 0xffff
+#define BIT_NAV_PROT_LEN_8197F(x) \
+ (((x) & BIT_MASK_NAV_PROT_LEN_8197F) << BIT_SHIFT_NAV_PROT_LEN_8197F)
+#define BITS_NAV_PROT_LEN_8197F \
+ (BIT_MASK_NAV_PROT_LEN_8197F << BIT_SHIFT_NAV_PROT_LEN_8197F)
+#define BIT_CLEAR_NAV_PROT_LEN_8197F(x) ((x) & (~BITS_NAV_PROT_LEN_8197F))
+#define BIT_GET_NAV_PROT_LEN_8197F(x) \
+ (((x) >> BIT_SHIFT_NAV_PROT_LEN_8197F) & BIT_MASK_NAV_PROT_LEN_8197F)
+#define BIT_SET_NAV_PROT_LEN_8197F(x, v) \
+ (BIT_CLEAR_NAV_PROT_LEN_8197F(x) | BIT_NAV_PROT_LEN_8197F(v))
+
+/* 2 REG_FTM_CTRL_8197F */
+
+#define BIT_SHIFT_FTM_TSF_R2T_PORT_8197F 22
+#define BIT_MASK_FTM_TSF_R2T_PORT_8197F 0x7
+#define BIT_FTM_TSF_R2T_PORT_8197F(x) \
+ (((x) & BIT_MASK_FTM_TSF_R2T_PORT_8197F) \
+ << BIT_SHIFT_FTM_TSF_R2T_PORT_8197F)
+#define BITS_FTM_TSF_R2T_PORT_8197F \
+ (BIT_MASK_FTM_TSF_R2T_PORT_8197F << BIT_SHIFT_FTM_TSF_R2T_PORT_8197F)
+#define BIT_CLEAR_FTM_TSF_R2T_PORT_8197F(x) \
+ ((x) & (~BITS_FTM_TSF_R2T_PORT_8197F))
+#define BIT_GET_FTM_TSF_R2T_PORT_8197F(x) \
+ (((x) >> BIT_SHIFT_FTM_TSF_R2T_PORT_8197F) & \
+ BIT_MASK_FTM_TSF_R2T_PORT_8197F)
+#define BIT_SET_FTM_TSF_R2T_PORT_8197F(x, v) \
+ (BIT_CLEAR_FTM_TSF_R2T_PORT_8197F(x) | BIT_FTM_TSF_R2T_PORT_8197F(v))
+
+#define BIT_SHIFT_FTM_TSF_T2R_PORT_8197F 19
+#define BIT_MASK_FTM_TSF_T2R_PORT_8197F 0x7
+#define BIT_FTM_TSF_T2R_PORT_8197F(x) \
+ (((x) & BIT_MASK_FTM_TSF_T2R_PORT_8197F) \
+ << BIT_SHIFT_FTM_TSF_T2R_PORT_8197F)
+#define BITS_FTM_TSF_T2R_PORT_8197F \
+ (BIT_MASK_FTM_TSF_T2R_PORT_8197F << BIT_SHIFT_FTM_TSF_T2R_PORT_8197F)
+#define BIT_CLEAR_FTM_TSF_T2R_PORT_8197F(x) \
+ ((x) & (~BITS_FTM_TSF_T2R_PORT_8197F))
+#define BIT_GET_FTM_TSF_T2R_PORT_8197F(x) \
+ (((x) >> BIT_SHIFT_FTM_TSF_T2R_PORT_8197F) & \
+ BIT_MASK_FTM_TSF_T2R_PORT_8197F)
+#define BIT_SET_FTM_TSF_T2R_PORT_8197F(x, v) \
+ (BIT_CLEAR_FTM_TSF_T2R_PORT_8197F(x) | BIT_FTM_TSF_T2R_PORT_8197F(v))
+
+#define BIT_SHIFT_FTM_PTT_PORT_8197F 16
+#define BIT_MASK_FTM_PTT_PORT_8197F 0x7
+#define BIT_FTM_PTT_PORT_8197F(x) \
+ (((x) & BIT_MASK_FTM_PTT_PORT_8197F) << BIT_SHIFT_FTM_PTT_PORT_8197F)
+#define BITS_FTM_PTT_PORT_8197F \
+ (BIT_MASK_FTM_PTT_PORT_8197F << BIT_SHIFT_FTM_PTT_PORT_8197F)
+#define BIT_CLEAR_FTM_PTT_PORT_8197F(x) ((x) & (~BITS_FTM_PTT_PORT_8197F))
+#define BIT_GET_FTM_PTT_PORT_8197F(x) \
+ (((x) >> BIT_SHIFT_FTM_PTT_PORT_8197F) & BIT_MASK_FTM_PTT_PORT_8197F)
+#define BIT_SET_FTM_PTT_PORT_8197F(x, v) \
+ (BIT_CLEAR_FTM_PTT_PORT_8197F(x) | BIT_FTM_PTT_PORT_8197F(v))
+
+#define BIT_SHIFT_FTM_PTT_8197F 0
+#define BIT_MASK_FTM_PTT_8197F 0xffff
+#define BIT_FTM_PTT_8197F(x) \
+ (((x) & BIT_MASK_FTM_PTT_8197F) << BIT_SHIFT_FTM_PTT_8197F)
+#define BITS_FTM_PTT_8197F (BIT_MASK_FTM_PTT_8197F << BIT_SHIFT_FTM_PTT_8197F)
+#define BIT_CLEAR_FTM_PTT_8197F(x) ((x) & (~BITS_FTM_PTT_8197F))
+#define BIT_GET_FTM_PTT_8197F(x) \
+ (((x) >> BIT_SHIFT_FTM_PTT_8197F) & BIT_MASK_FTM_PTT_8197F)
+#define BIT_SET_FTM_PTT_8197F(x, v) \
+ (BIT_CLEAR_FTM_PTT_8197F(x) | BIT_FTM_PTT_8197F(v))
+
+/* 2 REG_FTM_TSF_CNT_8197F */
+
+#define BIT_SHIFT_FTM_TSF_R2T_8197F 16
+#define BIT_MASK_FTM_TSF_R2T_8197F 0xffff
+#define BIT_FTM_TSF_R2T_8197F(x) \
+ (((x) & BIT_MASK_FTM_TSF_R2T_8197F) << BIT_SHIFT_FTM_TSF_R2T_8197F)
+#define BITS_FTM_TSF_R2T_8197F \
+ (BIT_MASK_FTM_TSF_R2T_8197F << BIT_SHIFT_FTM_TSF_R2T_8197F)
+#define BIT_CLEAR_FTM_TSF_R2T_8197F(x) ((x) & (~BITS_FTM_TSF_R2T_8197F))
+#define BIT_GET_FTM_TSF_R2T_8197F(x) \
+ (((x) >> BIT_SHIFT_FTM_TSF_R2T_8197F) & BIT_MASK_FTM_TSF_R2T_8197F)
+#define BIT_SET_FTM_TSF_R2T_8197F(x, v) \
+ (BIT_CLEAR_FTM_TSF_R2T_8197F(x) | BIT_FTM_TSF_R2T_8197F(v))
+
+#define BIT_SHIFT_FTM_TSF_T2R_8197F 0
+#define BIT_MASK_FTM_TSF_T2R_8197F 0xffff
+#define BIT_FTM_TSF_T2R_8197F(x) \
+ (((x) & BIT_MASK_FTM_TSF_T2R_8197F) << BIT_SHIFT_FTM_TSF_T2R_8197F)
+#define BITS_FTM_TSF_T2R_8197F \
+ (BIT_MASK_FTM_TSF_T2R_8197F << BIT_SHIFT_FTM_TSF_T2R_8197F)
+#define BIT_CLEAR_FTM_TSF_T2R_8197F(x) ((x) & (~BITS_FTM_TSF_T2R_8197F))
+#define BIT_GET_FTM_TSF_T2R_8197F(x) \
+ (((x) >> BIT_SHIFT_FTM_TSF_T2R_8197F) & BIT_MASK_FTM_TSF_T2R_8197F)
+#define BIT_SET_FTM_TSF_T2R_8197F(x, v) \
+ (BIT_CLEAR_FTM_TSF_T2R_8197F(x) | BIT_FTM_TSF_T2R_8197F(v))
+
+/* 2 REG_BCN_CTRL_8197F */
+#define BIT_DIS_RX_BSSID_FIT_8197F BIT(6)
+#define BIT_P0_EN_TXBCN_RPT_8197F BIT(5)
+#define BIT_DIS_TSF_UDT_8197F BIT(4)
+#define BIT_EN_BCN_FUNCTION_8197F BIT(3)
+#define BIT_P0_EN_RXBCN_RPT_8197F BIT(2)
+#define BIT_EN_P2P_CTWINDOW_8197F BIT(1)
+#define BIT_EN_P2P_BCNQ_AREA_8197F BIT(0)
+
+/* 2 REG_BCN_CTRL_CLINT0_8197F */
+#define BIT_CLI0_DIS_RX_BSSID_FIT_8197F BIT(6)
+#define BIT_CLI0_DIS_TSF_UDT_8197F BIT(4)
+#define BIT_CLI0_EN_BCN_FUNCTION_8197F BIT(3)
+#define BIT_CLI0_EN_RXBCN_RPT_8197F BIT(2)
+#define BIT_CLI0_ENP2P_CTWINDOW_8197F BIT(1)
+#define BIT_CLI0_ENP2P_BCNQ_AREA_8197F BIT(0)
+
+/* 2 REG_MBID_NUM_8197F */
+#define BIT_EN_PRE_DL_BEACON_8197F BIT(3)
+
+#define BIT_SHIFT_MBID_BCN_NUM_8197F 0
+#define BIT_MASK_MBID_BCN_NUM_8197F 0x7
+#define BIT_MBID_BCN_NUM_8197F(x) \
+ (((x) & BIT_MASK_MBID_BCN_NUM_8197F) << BIT_SHIFT_MBID_BCN_NUM_8197F)
+#define BITS_MBID_BCN_NUM_8197F \
+ (BIT_MASK_MBID_BCN_NUM_8197F << BIT_SHIFT_MBID_BCN_NUM_8197F)
+#define BIT_CLEAR_MBID_BCN_NUM_8197F(x) ((x) & (~BITS_MBID_BCN_NUM_8197F))
+#define BIT_GET_MBID_BCN_NUM_8197F(x) \
+ (((x) >> BIT_SHIFT_MBID_BCN_NUM_8197F) & BIT_MASK_MBID_BCN_NUM_8197F)
+#define BIT_SET_MBID_BCN_NUM_8197F(x, v) \
+ (BIT_CLEAR_MBID_BCN_NUM_8197F(x) | BIT_MBID_BCN_NUM_8197F(v))
+
+/* 2 REG_DUAL_TSF_RST_8197F */
+#define BIT_FREECNT_RST_8197F BIT(5)
+#define BIT_TSFTR_CLI3_RST_8197F BIT(4)
+#define BIT_TSFTR_CLI2_RST_8197F BIT(3)
+#define BIT_TSFTR_CLI1_RST_8197F BIT(2)
+#define BIT_TSFTR_CLI0_RST_8197F BIT(1)
+#define BIT_TSFTR_RST_8197F BIT(0)
+
+/* 2 REG_MBSSID_BCN_SPACE_8197F */
+
+#define BIT_SHIFT_BCN_TIMER_SEL_FWRD_8197F 28
+#define BIT_MASK_BCN_TIMER_SEL_FWRD_8197F 0x7
+#define BIT_BCN_TIMER_SEL_FWRD_8197F(x) \
+ (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_8197F) \
+ << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8197F)
+#define BITS_BCN_TIMER_SEL_FWRD_8197F \
+ (BIT_MASK_BCN_TIMER_SEL_FWRD_8197F \
+ << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8197F)
+#define BIT_CLEAR_BCN_TIMER_SEL_FWRD_8197F(x) \
+ ((x) & (~BITS_BCN_TIMER_SEL_FWRD_8197F))
+#define BIT_GET_BCN_TIMER_SEL_FWRD_8197F(x) \
+ (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_8197F) & \
+ BIT_MASK_BCN_TIMER_SEL_FWRD_8197F)
+#define BIT_SET_BCN_TIMER_SEL_FWRD_8197F(x, v) \
+ (BIT_CLEAR_BCN_TIMER_SEL_FWRD_8197F(x) | \
+ BIT_BCN_TIMER_SEL_FWRD_8197F(v))
+
+#define BIT_SHIFT_BCN_SPACE_CLINT0_8197F 16
+#define BIT_MASK_BCN_SPACE_CLINT0_8197F 0xfff
+#define BIT_BCN_SPACE_CLINT0_8197F(x) \
+ (((x) & BIT_MASK_BCN_SPACE_CLINT0_8197F) \
+ << BIT_SHIFT_BCN_SPACE_CLINT0_8197F)
+#define BITS_BCN_SPACE_CLINT0_8197F \
+ (BIT_MASK_BCN_SPACE_CLINT0_8197F << BIT_SHIFT_BCN_SPACE_CLINT0_8197F)
+#define BIT_CLEAR_BCN_SPACE_CLINT0_8197F(x) \
+ ((x) & (~BITS_BCN_SPACE_CLINT0_8197F))
+#define BIT_GET_BCN_SPACE_CLINT0_8197F(x) \
+ (((x) >> BIT_SHIFT_BCN_SPACE_CLINT0_8197F) & \
+ BIT_MASK_BCN_SPACE_CLINT0_8197F)
+#define BIT_SET_BCN_SPACE_CLINT0_8197F(x, v) \
+ (BIT_CLEAR_BCN_SPACE_CLINT0_8197F(x) | BIT_BCN_SPACE_CLINT0_8197F(v))
+
+#define BIT_SHIFT_BCN_SPACE0_8197F 0
+#define BIT_MASK_BCN_SPACE0_8197F 0xffff
+#define BIT_BCN_SPACE0_8197F(x) \
+ (((x) & BIT_MASK_BCN_SPACE0_8197F) << BIT_SHIFT_BCN_SPACE0_8197F)
+#define BITS_BCN_SPACE0_8197F \
+ (BIT_MASK_BCN_SPACE0_8197F << BIT_SHIFT_BCN_SPACE0_8197F)
+#define BIT_CLEAR_BCN_SPACE0_8197F(x) ((x) & (~BITS_BCN_SPACE0_8197F))
+#define BIT_GET_BCN_SPACE0_8197F(x) \
+ (((x) >> BIT_SHIFT_BCN_SPACE0_8197F) & BIT_MASK_BCN_SPACE0_8197F)
+#define BIT_SET_BCN_SPACE0_8197F(x, v) \
+ (BIT_CLEAR_BCN_SPACE0_8197F(x) | BIT_BCN_SPACE0_8197F(v))
+
+/* 2 REG_DRVERLYINT_8197F */
+
+#define BIT_SHIFT_DRVERLYITV_8197F 0
+#define BIT_MASK_DRVERLYITV_8197F 0xff
+#define BIT_DRVERLYITV_8197F(x) \
+ (((x) & BIT_MASK_DRVERLYITV_8197F) << BIT_SHIFT_DRVERLYITV_8197F)
+#define BITS_DRVERLYITV_8197F \
+ (BIT_MASK_DRVERLYITV_8197F << BIT_SHIFT_DRVERLYITV_8197F)
+#define BIT_CLEAR_DRVERLYITV_8197F(x) ((x) & (~BITS_DRVERLYITV_8197F))
+#define BIT_GET_DRVERLYITV_8197F(x) \
+ (((x) >> BIT_SHIFT_DRVERLYITV_8197F) & BIT_MASK_DRVERLYITV_8197F)
+#define BIT_SET_DRVERLYITV_8197F(x, v) \
+ (BIT_CLEAR_DRVERLYITV_8197F(x) | BIT_DRVERLYITV_8197F(v))
+
+/* 2 REG_BCNDMATIM_8197F */
+
+#define BIT_SHIFT_BCNDMATIM_8197F 0
+#define BIT_MASK_BCNDMATIM_8197F 0xff
+#define BIT_BCNDMATIM_8197F(x) \
+ (((x) & BIT_MASK_BCNDMATIM_8197F) << BIT_SHIFT_BCNDMATIM_8197F)
+#define BITS_BCNDMATIM_8197F \
+ (BIT_MASK_BCNDMATIM_8197F << BIT_SHIFT_BCNDMATIM_8197F)
+#define BIT_CLEAR_BCNDMATIM_8197F(x) ((x) & (~BITS_BCNDMATIM_8197F))
+#define BIT_GET_BCNDMATIM_8197F(x) \
+ (((x) >> BIT_SHIFT_BCNDMATIM_8197F) & BIT_MASK_BCNDMATIM_8197F)
+#define BIT_SET_BCNDMATIM_8197F(x, v) \
+ (BIT_CLEAR_BCNDMATIM_8197F(x) | BIT_BCNDMATIM_8197F(v))
+
+/* 2 REG_ATIMWND_8197F */
+
+#define BIT_SHIFT_ATIMWND0_8197F 0
+#define BIT_MASK_ATIMWND0_8197F 0xffff
+#define BIT_ATIMWND0_8197F(x) \
+ (((x) & BIT_MASK_ATIMWND0_8197F) << BIT_SHIFT_ATIMWND0_8197F)
+#define BITS_ATIMWND0_8197F \
+ (BIT_MASK_ATIMWND0_8197F << BIT_SHIFT_ATIMWND0_8197F)
+#define BIT_CLEAR_ATIMWND0_8197F(x) ((x) & (~BITS_ATIMWND0_8197F))
+#define BIT_GET_ATIMWND0_8197F(x) \
+ (((x) >> BIT_SHIFT_ATIMWND0_8197F) & BIT_MASK_ATIMWND0_8197F)
+#define BIT_SET_ATIMWND0_8197F(x, v) \
+ (BIT_CLEAR_ATIMWND0_8197F(x) | BIT_ATIMWND0_8197F(v))
+
+/* 2 REG_USTIME_TSF_8197F */
+
+#define BIT_SHIFT_USTIME_TSF_V1_8197F 0
+#define BIT_MASK_USTIME_TSF_V1_8197F 0xff
+#define BIT_USTIME_TSF_V1_8197F(x) \
+ (((x) & BIT_MASK_USTIME_TSF_V1_8197F) << BIT_SHIFT_USTIME_TSF_V1_8197F)
+#define BITS_USTIME_TSF_V1_8197F \
+ (BIT_MASK_USTIME_TSF_V1_8197F << BIT_SHIFT_USTIME_TSF_V1_8197F)
+#define BIT_CLEAR_USTIME_TSF_V1_8197F(x) ((x) & (~BITS_USTIME_TSF_V1_8197F))
+#define BIT_GET_USTIME_TSF_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_USTIME_TSF_V1_8197F) & BIT_MASK_USTIME_TSF_V1_8197F)
+#define BIT_SET_USTIME_TSF_V1_8197F(x, v) \
+ (BIT_CLEAR_USTIME_TSF_V1_8197F(x) | BIT_USTIME_TSF_V1_8197F(v))
+
+/* 2 REG_BCN_MAX_ERR_8197F */
+
+#define BIT_SHIFT_BCN_MAX_ERR_8197F 0
+#define BIT_MASK_BCN_MAX_ERR_8197F 0xff
+#define BIT_BCN_MAX_ERR_8197F(x) \
+ (((x) & BIT_MASK_BCN_MAX_ERR_8197F) << BIT_SHIFT_BCN_MAX_ERR_8197F)
+#define BITS_BCN_MAX_ERR_8197F \
+ (BIT_MASK_BCN_MAX_ERR_8197F << BIT_SHIFT_BCN_MAX_ERR_8197F)
+#define BIT_CLEAR_BCN_MAX_ERR_8197F(x) ((x) & (~BITS_BCN_MAX_ERR_8197F))
+#define BIT_GET_BCN_MAX_ERR_8197F(x) \
+ (((x) >> BIT_SHIFT_BCN_MAX_ERR_8197F) & BIT_MASK_BCN_MAX_ERR_8197F)
+#define BIT_SET_BCN_MAX_ERR_8197F(x, v) \
+ (BIT_CLEAR_BCN_MAX_ERR_8197F(x) | BIT_BCN_MAX_ERR_8197F(v))
+
+/* 2 REG_RXTSF_OFFSET_CCK_8197F */
+
+#define BIT_SHIFT_CCK_RXTSF_OFFSET_8197F 0
+#define BIT_MASK_CCK_RXTSF_OFFSET_8197F 0xff
+#define BIT_CCK_RXTSF_OFFSET_8197F(x) \
+ (((x) & BIT_MASK_CCK_RXTSF_OFFSET_8197F) \
+ << BIT_SHIFT_CCK_RXTSF_OFFSET_8197F)
+#define BITS_CCK_RXTSF_OFFSET_8197F \
+ (BIT_MASK_CCK_RXTSF_OFFSET_8197F << BIT_SHIFT_CCK_RXTSF_OFFSET_8197F)
+#define BIT_CLEAR_CCK_RXTSF_OFFSET_8197F(x) \
+ ((x) & (~BITS_CCK_RXTSF_OFFSET_8197F))
+#define BIT_GET_CCK_RXTSF_OFFSET_8197F(x) \
+ (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8197F) & \
+ BIT_MASK_CCK_RXTSF_OFFSET_8197F)
+#define BIT_SET_CCK_RXTSF_OFFSET_8197F(x, v) \
+ (BIT_CLEAR_CCK_RXTSF_OFFSET_8197F(x) | BIT_CCK_RXTSF_OFFSET_8197F(v))
+
+/* 2 REG_RXTSF_OFFSET_OFDM_8197F */
+
+#define BIT_SHIFT_OFDM_RXTSF_OFFSET_8197F 0
+#define BIT_MASK_OFDM_RXTSF_OFFSET_8197F 0xff
+#define BIT_OFDM_RXTSF_OFFSET_8197F(x) \
+ (((x) & BIT_MASK_OFDM_RXTSF_OFFSET_8197F) \
+ << BIT_SHIFT_OFDM_RXTSF_OFFSET_8197F)
+#define BITS_OFDM_RXTSF_OFFSET_8197F \
+ (BIT_MASK_OFDM_RXTSF_OFFSET_8197F << BIT_SHIFT_OFDM_RXTSF_OFFSET_8197F)
+#define BIT_CLEAR_OFDM_RXTSF_OFFSET_8197F(x) \
+ ((x) & (~BITS_OFDM_RXTSF_OFFSET_8197F))
+#define BIT_GET_OFDM_RXTSF_OFFSET_8197F(x) \
+ (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8197F) & \
+ BIT_MASK_OFDM_RXTSF_OFFSET_8197F)
+#define BIT_SET_OFDM_RXTSF_OFFSET_8197F(x, v) \
+ (BIT_CLEAR_OFDM_RXTSF_OFFSET_8197F(x) | BIT_OFDM_RXTSF_OFFSET_8197F(v))
+
+/* 2 REG_TSFTR_8197F */
+
+#define BIT_SHIFT_TSF_TIMER_8197F 0
+#define BIT_MASK_TSF_TIMER_8197F 0xffffffffffffffffL
+#define BIT_TSF_TIMER_8197F(x) \
+ (((x) & BIT_MASK_TSF_TIMER_8197F) << BIT_SHIFT_TSF_TIMER_8197F)
+#define BITS_TSF_TIMER_8197F \
+ (BIT_MASK_TSF_TIMER_8197F << BIT_SHIFT_TSF_TIMER_8197F)
+#define BIT_CLEAR_TSF_TIMER_8197F(x) ((x) & (~BITS_TSF_TIMER_8197F))
+#define BIT_GET_TSF_TIMER_8197F(x) \
+ (((x) >> BIT_SHIFT_TSF_TIMER_8197F) & BIT_MASK_TSF_TIMER_8197F)
+#define BIT_SET_TSF_TIMER_8197F(x, v) \
+ (BIT_CLEAR_TSF_TIMER_8197F(x) | BIT_TSF_TIMER_8197F(v))
+
+/* 2 REG_FREERUN_CNT_8197F */
+
+#define BIT_SHIFT_FREERUN_CNT_8197F 0
+#define BIT_MASK_FREERUN_CNT_8197F 0xffffffffffffffffL
+#define BIT_FREERUN_CNT_8197F(x) \
+ (((x) & BIT_MASK_FREERUN_CNT_8197F) << BIT_SHIFT_FREERUN_CNT_8197F)
+#define BITS_FREERUN_CNT_8197F \
+ (BIT_MASK_FREERUN_CNT_8197F << BIT_SHIFT_FREERUN_CNT_8197F)
+#define BIT_CLEAR_FREERUN_CNT_8197F(x) ((x) & (~BITS_FREERUN_CNT_8197F))
+#define BIT_GET_FREERUN_CNT_8197F(x) \
+ (((x) >> BIT_SHIFT_FREERUN_CNT_8197F) & BIT_MASK_FREERUN_CNT_8197F)
+#define BIT_SET_FREERUN_CNT_8197F(x, v) \
+ (BIT_CLEAR_FREERUN_CNT_8197F(x) | BIT_FREERUN_CNT_8197F(v))
+
+/* 2 REG_ATIMWND1_8197F */
+
+#define BIT_SHIFT_ATIMWND1_V1_8197F 0
+#define BIT_MASK_ATIMWND1_V1_8197F 0xff
+#define BIT_ATIMWND1_V1_8197F(x) \
+ (((x) & BIT_MASK_ATIMWND1_V1_8197F) << BIT_SHIFT_ATIMWND1_V1_8197F)
+#define BITS_ATIMWND1_V1_8197F \
+ (BIT_MASK_ATIMWND1_V1_8197F << BIT_SHIFT_ATIMWND1_V1_8197F)
+#define BIT_CLEAR_ATIMWND1_V1_8197F(x) ((x) & (~BITS_ATIMWND1_V1_8197F))
+#define BIT_GET_ATIMWND1_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_ATIMWND1_V1_8197F) & BIT_MASK_ATIMWND1_V1_8197F)
+#define BIT_SET_ATIMWND1_V1_8197F(x, v) \
+ (BIT_CLEAR_ATIMWND1_V1_8197F(x) | BIT_ATIMWND1_V1_8197F(v))
+
+/* 2 REG_TBTT_PROHIBIT_INFRA_8197F */
+
+#define BIT_SHIFT_TBTT_PROHIBIT_INFRA_8197F 0
+#define BIT_MASK_TBTT_PROHIBIT_INFRA_8197F 0xff
+#define BIT_TBTT_PROHIBIT_INFRA_8197F(x) \
+ (((x) & BIT_MASK_TBTT_PROHIBIT_INFRA_8197F) \
+ << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8197F)
+#define BITS_TBTT_PROHIBIT_INFRA_8197F \
+ (BIT_MASK_TBTT_PROHIBIT_INFRA_8197F \
+ << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8197F)
+#define BIT_CLEAR_TBTT_PROHIBIT_INFRA_8197F(x) \
+ ((x) & (~BITS_TBTT_PROHIBIT_INFRA_8197F))
+#define BIT_GET_TBTT_PROHIBIT_INFRA_8197F(x) \
+ (((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA_8197F) & \
+ BIT_MASK_TBTT_PROHIBIT_INFRA_8197F)
+#define BIT_SET_TBTT_PROHIBIT_INFRA_8197F(x, v) \
+ (BIT_CLEAR_TBTT_PROHIBIT_INFRA_8197F(x) | \
+ BIT_TBTT_PROHIBIT_INFRA_8197F(v))
+
+/* 2 REG_CTWND_8197F */
+
+#define BIT_SHIFT_CTWND_8197F 0
+#define BIT_MASK_CTWND_8197F 0xff
+#define BIT_CTWND_8197F(x) \
+ (((x) & BIT_MASK_CTWND_8197F) << BIT_SHIFT_CTWND_8197F)
+#define BITS_CTWND_8197F (BIT_MASK_CTWND_8197F << BIT_SHIFT_CTWND_8197F)
+#define BIT_CLEAR_CTWND_8197F(x) ((x) & (~BITS_CTWND_8197F))
+#define BIT_GET_CTWND_8197F(x) \
+ (((x) >> BIT_SHIFT_CTWND_8197F) & BIT_MASK_CTWND_8197F)
+#define BIT_SET_CTWND_8197F(x, v) \
+ (BIT_CLEAR_CTWND_8197F(x) | BIT_CTWND_8197F(v))
+
+/* 2 REG_BCNIVLCUNT_8197F */
+
+#define BIT_SHIFT_BCNIVLCUNT_8197F 0
+#define BIT_MASK_BCNIVLCUNT_8197F 0x7f
+#define BIT_BCNIVLCUNT_8197F(x) \
+ (((x) & BIT_MASK_BCNIVLCUNT_8197F) << BIT_SHIFT_BCNIVLCUNT_8197F)
+#define BITS_BCNIVLCUNT_8197F \
+ (BIT_MASK_BCNIVLCUNT_8197F << BIT_SHIFT_BCNIVLCUNT_8197F)
+#define BIT_CLEAR_BCNIVLCUNT_8197F(x) ((x) & (~BITS_BCNIVLCUNT_8197F))
+#define BIT_GET_BCNIVLCUNT_8197F(x) \
+ (((x) >> BIT_SHIFT_BCNIVLCUNT_8197F) & BIT_MASK_BCNIVLCUNT_8197F)
+#define BIT_SET_BCNIVLCUNT_8197F(x, v) \
+ (BIT_CLEAR_BCNIVLCUNT_8197F(x) | BIT_BCNIVLCUNT_8197F(v))
+
+/* 2 REG_BCNDROPCTRL_8197F */
+#define BIT_BEACON_DROP_EN_8197F BIT(7)
+
+#define BIT_SHIFT_BEACON_DROP_IVL_8197F 0
+#define BIT_MASK_BEACON_DROP_IVL_8197F 0x7f
+#define BIT_BEACON_DROP_IVL_8197F(x) \
+ (((x) & BIT_MASK_BEACON_DROP_IVL_8197F) \
+ << BIT_SHIFT_BEACON_DROP_IVL_8197F)
+#define BITS_BEACON_DROP_IVL_8197F \
+ (BIT_MASK_BEACON_DROP_IVL_8197F << BIT_SHIFT_BEACON_DROP_IVL_8197F)
+#define BIT_CLEAR_BEACON_DROP_IVL_8197F(x) ((x) & (~BITS_BEACON_DROP_IVL_8197F))
+#define BIT_GET_BEACON_DROP_IVL_8197F(x) \
+ (((x) >> BIT_SHIFT_BEACON_DROP_IVL_8197F) & \
+ BIT_MASK_BEACON_DROP_IVL_8197F)
+#define BIT_SET_BEACON_DROP_IVL_8197F(x, v) \
+ (BIT_CLEAR_BEACON_DROP_IVL_8197F(x) | BIT_BEACON_DROP_IVL_8197F(v))
+
+/* 2 REG_HGQ_TIMEOUT_PERIOD_8197F */
+
+#define BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8197F 0
+#define BIT_MASK_HGQ_TIMEOUT_PERIOD_8197F 0xff
+#define BIT_HGQ_TIMEOUT_PERIOD_8197F(x) \
+ (((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8197F) \
+ << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8197F)
+#define BITS_HGQ_TIMEOUT_PERIOD_8197F \
+ (BIT_MASK_HGQ_TIMEOUT_PERIOD_8197F \
+ << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8197F)
+#define BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8197F(x) \
+ ((x) & (~BITS_HGQ_TIMEOUT_PERIOD_8197F))
+#define BIT_GET_HGQ_TIMEOUT_PERIOD_8197F(x) \
+ (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8197F) & \
+ BIT_MASK_HGQ_TIMEOUT_PERIOD_8197F)
+#define BIT_SET_HGQ_TIMEOUT_PERIOD_8197F(x, v) \
+ (BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8197F(x) | \
+ BIT_HGQ_TIMEOUT_PERIOD_8197F(v))
+
+/* 2 REG_TXCMD_TIMEOUT_PERIOD_8197F */
+
+#define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8197F 0
+#define BIT_MASK_TXCMD_TIMEOUT_PERIOD_8197F 0xff
+#define BIT_TXCMD_TIMEOUT_PERIOD_8197F(x) \
+ (((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8197F) \
+ << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8197F)
+#define BITS_TXCMD_TIMEOUT_PERIOD_8197F \
+ (BIT_MASK_TXCMD_TIMEOUT_PERIOD_8197F \
+ << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8197F)
+#define BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8197F(x) \
+ ((x) & (~BITS_TXCMD_TIMEOUT_PERIOD_8197F))
+#define BIT_GET_TXCMD_TIMEOUT_PERIOD_8197F(x) \
+ (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8197F) & \
+ BIT_MASK_TXCMD_TIMEOUT_PERIOD_8197F)
+#define BIT_SET_TXCMD_TIMEOUT_PERIOD_8197F(x, v) \
+ (BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8197F(x) | \
+ BIT_TXCMD_TIMEOUT_PERIOD_8197F(v))
+
+/* 2 REG_MISC_CTRL_8197F */
+#define BIT_DIS_MARK_TSF_US_8197F BIT(7)
+#define BIT_EN_TSFAUTO_SYNC_8197F BIT(6)
+#define BIT_DIS_TRX_CAL_BCN_8197F BIT(5)
+#define BIT_DIS_TX_CAL_TBTT_8197F BIT(4)
+#define BIT_EN_FREECNT_8197F BIT(3)
+#define BIT_BCN_AGGRESSION_8197F BIT(2)
+
+#define BIT_SHIFT_DIS_SECONDARY_CCA_8197F 0
+#define BIT_MASK_DIS_SECONDARY_CCA_8197F 0x3
+#define BIT_DIS_SECONDARY_CCA_8197F(x) \
+ (((x) & BIT_MASK_DIS_SECONDARY_CCA_8197F) \
+ << BIT_SHIFT_DIS_SECONDARY_CCA_8197F)
+#define BITS_DIS_SECONDARY_CCA_8197F \
+ (BIT_MASK_DIS_SECONDARY_CCA_8197F << BIT_SHIFT_DIS_SECONDARY_CCA_8197F)
+#define BIT_CLEAR_DIS_SECONDARY_CCA_8197F(x) \
+ ((x) & (~BITS_DIS_SECONDARY_CCA_8197F))
+#define BIT_GET_DIS_SECONDARY_CCA_8197F(x) \
+ (((x) >> BIT_SHIFT_DIS_SECONDARY_CCA_8197F) & \
+ BIT_MASK_DIS_SECONDARY_CCA_8197F)
+#define BIT_SET_DIS_SECONDARY_CCA_8197F(x, v) \
+ (BIT_CLEAR_DIS_SECONDARY_CCA_8197F(x) | BIT_DIS_SECONDARY_CCA_8197F(v))
+
+/* 2 REG_BCN_CTRL_CLINT1_8197F */
+#define BIT_CLI1_DIS_RX_BSSID_FIT_8197F BIT(6)
+#define BIT_CLI1_DIS_TSF_UDT_8197F BIT(4)
+#define BIT_CLI1_EN_BCN_FUNCTION_8197F BIT(3)
+#define BIT_CLI1_EN_RXBCN_RPT_8197F BIT(2)
+#define BIT_CLI1_ENP2P_CTWINDOW_8197F BIT(1)
+#define BIT_CLI1_ENP2P_BCNQ_AREA_8197F BIT(0)
+
+/* 2 REG_BCN_CTRL_CLINT2_8197F */
+#define BIT_CLI2_DIS_RX_BSSID_FIT_8197F BIT(6)
+#define BIT_CLI2_DIS_TSF_UDT_8197F BIT(4)
+#define BIT_CLI2_EN_BCN_FUNCTION_8197F BIT(3)
+#define BIT_CLI2_EN_RXBCN_RPT_8197F BIT(2)
+#define BIT_CLI2_ENP2P_CTWINDOW_8197F BIT(1)
+#define BIT_CLI2_ENP2P_BCNQ_AREA_8197F BIT(0)
+
+/* 2 REG_BCN_CTRL_CLINT3_8197F */
+#define BIT_CLI3_DIS_RX_BSSID_FIT_8197F BIT(6)
+#define BIT_CLI3_DIS_TSF_UDT_8197F BIT(4)
+#define BIT_CLI3_EN_BCN_FUNCTION_8197F BIT(3)
+#define BIT_CLI3_EN_RXBCN_RPT_8197F BIT(2)
+#define BIT_CLI3_ENP2P_CTWINDOW_8197F BIT(1)
+#define BIT_CLI3_ENP2P_BCNQ_AREA_8197F BIT(0)
+
+/* 2 REG_EXTEND_CTRL_8197F */
+#define BIT_EN_TSFBIT32_RST_P2P2_8197F BIT(5)
+#define BIT_EN_TSFBIT32_RST_P2P1_8197F BIT(4)
+
+#define BIT_SHIFT_PORT_SEL_8197F 0
+#define BIT_MASK_PORT_SEL_8197F 0x7
+#define BIT_PORT_SEL_8197F(x) \
+ (((x) & BIT_MASK_PORT_SEL_8197F) << BIT_SHIFT_PORT_SEL_8197F)
+#define BITS_PORT_SEL_8197F \
+ (BIT_MASK_PORT_SEL_8197F << BIT_SHIFT_PORT_SEL_8197F)
+#define BIT_CLEAR_PORT_SEL_8197F(x) ((x) & (~BITS_PORT_SEL_8197F))
+#define BIT_GET_PORT_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_PORT_SEL_8197F) & BIT_MASK_PORT_SEL_8197F)
+#define BIT_SET_PORT_SEL_8197F(x, v) \
+ (BIT_CLEAR_PORT_SEL_8197F(x) | BIT_PORT_SEL_8197F(v))
+
+/* 2 REG_P2PPS1_SPEC_STATE_8197F */
+#define BIT_P2P1_SPEC_POWER_STATE_8197F BIT(7)
+#define BIT_P2P1_SPEC_CTWINDOW_ON_8197F BIT(6)
+#define BIT_P2P1_SPEC_BCN_AREA_ON_8197F BIT(5)
+#define BIT_P2P1_SPEC_CTWIN_EARLY_DISTX_8197F BIT(4)
+#define BIT_P2P1_SPEC_NOA1_OFF_PERIOD_8197F BIT(3)
+#define BIT_P2P1_SPEC_FORCE_DOZE1_8197F BIT(2)
+#define BIT_P2P1_SPEC_NOA0_OFF_PERIOD_8197F BIT(1)
+#define BIT_P2P1_SPEC_FORCE_DOZE0_8197F BIT(0)
+
+/* 2 REG_P2PPS1_STATE_8197F */
+#define BIT_P2P1_POWER_STATE_8197F BIT(7)
+#define BIT_P2P1_CTWINDOW_ON_8197F BIT(6)
+#define BIT_P2P1_BEACON_AREA_ON_8197F BIT(5)
+#define BIT_P2P1_CTWIN_EARLY_DISTX_8197F BIT(4)
+#define BIT_P2P1_NOA1_OFF_PERIOD_8197F BIT(3)
+#define BIT_P2P1_FORCE_DOZE1_8197F BIT(2)
+#define BIT_P2P1_NOA0_OFF_PERIOD_8197F BIT(1)
+#define BIT_P2P1_FORCE_DOZE0_8197F BIT(0)
+
+/* 2 REG_P2PPS2_SPEC_STATE_8197F */
+#define BIT_P2P2_SPEC_POWER_STATE_8197F BIT(7)
+#define BIT_P2P2_SPEC_CTWINDOW_ON_8197F BIT(6)
+#define BIT_P2P2_SPEC_BCN_AREA_ON_8197F BIT(5)
+#define BIT_P2P2_SPEC_CTWIN_EARLY_DISTX_8197F BIT(4)
+#define BIT_P2P2_SPEC_NOA1_OFF_PERIOD_8197F BIT(3)
+#define BIT_P2P2_SPEC_FORCE_DOZE1_8197F BIT(2)
+#define BIT_P2P2_SPEC_NOA0_OFF_PERIOD_8197F BIT(1)
+#define BIT_P2P2_SPEC_FORCE_DOZE0_8197F BIT(0)
+
+/* 2 REG_P2PPS2_STATE_8197F */
+#define BIT_P2P2_POWER_STATE_8197F BIT(7)
+#define BIT_P2P2_CTWINDOW_ON_8197F BIT(6)
+#define BIT_P2P2_BEACON_AREA_ON_8197F BIT(5)
+#define BIT_P2P2_CTWIN_EARLY_DISTX_8197F BIT(4)
+#define BIT_P2P2_NOA1_OFF_PERIOD_8197F BIT(3)
+#define BIT_P2P2_FORCE_DOZE1_8197F BIT(2)
+#define BIT_P2P2_NOA0_OFF_PERIOD_8197F BIT(1)
+#define BIT_P2P2_FORCE_DOZE0_8197F BIT(0)
+
+/* 2 REG_PS_TIMER0_8197F */
+
+#define BIT_SHIFT_PSTIMER0_INT_8197F 5
+#define BIT_MASK_PSTIMER0_INT_8197F 0x7ffffff
+#define BIT_PSTIMER0_INT_8197F(x) \
+ (((x) & BIT_MASK_PSTIMER0_INT_8197F) << BIT_SHIFT_PSTIMER0_INT_8197F)
+#define BITS_PSTIMER0_INT_8197F \
+ (BIT_MASK_PSTIMER0_INT_8197F << BIT_SHIFT_PSTIMER0_INT_8197F)
+#define BIT_CLEAR_PSTIMER0_INT_8197F(x) ((x) & (~BITS_PSTIMER0_INT_8197F))
+#define BIT_GET_PSTIMER0_INT_8197F(x) \
+ (((x) >> BIT_SHIFT_PSTIMER0_INT_8197F) & BIT_MASK_PSTIMER0_INT_8197F)
+#define BIT_SET_PSTIMER0_INT_8197F(x, v) \
+ (BIT_CLEAR_PSTIMER0_INT_8197F(x) | BIT_PSTIMER0_INT_8197F(v))
+
+/* 2 REG_PS_TIMER1_8197F */
+
+#define BIT_SHIFT_PSTIMER1_INT_8197F 5
+#define BIT_MASK_PSTIMER1_INT_8197F 0x7ffffff
+#define BIT_PSTIMER1_INT_8197F(x) \
+ (((x) & BIT_MASK_PSTIMER1_INT_8197F) << BIT_SHIFT_PSTIMER1_INT_8197F)
+#define BITS_PSTIMER1_INT_8197F \
+ (BIT_MASK_PSTIMER1_INT_8197F << BIT_SHIFT_PSTIMER1_INT_8197F)
+#define BIT_CLEAR_PSTIMER1_INT_8197F(x) ((x) & (~BITS_PSTIMER1_INT_8197F))
+#define BIT_GET_PSTIMER1_INT_8197F(x) \
+ (((x) >> BIT_SHIFT_PSTIMER1_INT_8197F) & BIT_MASK_PSTIMER1_INT_8197F)
+#define BIT_SET_PSTIMER1_INT_8197F(x, v) \
+ (BIT_CLEAR_PSTIMER1_INT_8197F(x) | BIT_PSTIMER1_INT_8197F(v))
+
+/* 2 REG_PS_TIMER2_8197F */
+
+#define BIT_SHIFT_PSTIMER2_INT_8197F 5
+#define BIT_MASK_PSTIMER2_INT_8197F 0x7ffffff
+#define BIT_PSTIMER2_INT_8197F(x) \
+ (((x) & BIT_MASK_PSTIMER2_INT_8197F) << BIT_SHIFT_PSTIMER2_INT_8197F)
+#define BITS_PSTIMER2_INT_8197F \
+ (BIT_MASK_PSTIMER2_INT_8197F << BIT_SHIFT_PSTIMER2_INT_8197F)
+#define BIT_CLEAR_PSTIMER2_INT_8197F(x) ((x) & (~BITS_PSTIMER2_INT_8197F))
+#define BIT_GET_PSTIMER2_INT_8197F(x) \
+ (((x) >> BIT_SHIFT_PSTIMER2_INT_8197F) & BIT_MASK_PSTIMER2_INT_8197F)
+#define BIT_SET_PSTIMER2_INT_8197F(x, v) \
+ (BIT_CLEAR_PSTIMER2_INT_8197F(x) | BIT_PSTIMER2_INT_8197F(v))
+
+/* 2 REG_TBTT_CTN_AREA_8197F */
+
+#define BIT_SHIFT_TBTT_CTN_AREA_8197F 0
+#define BIT_MASK_TBTT_CTN_AREA_8197F 0xff
+#define BIT_TBTT_CTN_AREA_8197F(x) \
+ (((x) & BIT_MASK_TBTT_CTN_AREA_8197F) << BIT_SHIFT_TBTT_CTN_AREA_8197F)
+#define BITS_TBTT_CTN_AREA_8197F \
+ (BIT_MASK_TBTT_CTN_AREA_8197F << BIT_SHIFT_TBTT_CTN_AREA_8197F)
+#define BIT_CLEAR_TBTT_CTN_AREA_8197F(x) ((x) & (~BITS_TBTT_CTN_AREA_8197F))
+#define BIT_GET_TBTT_CTN_AREA_8197F(x) \
+ (((x) >> BIT_SHIFT_TBTT_CTN_AREA_8197F) & BIT_MASK_TBTT_CTN_AREA_8197F)
+#define BIT_SET_TBTT_CTN_AREA_8197F(x, v) \
+ (BIT_CLEAR_TBTT_CTN_AREA_8197F(x) | BIT_TBTT_CTN_AREA_8197F(v))
+
+/* 2 REG_FORCE_BCN_IFS_8197F */
+
+#define BIT_SHIFT_FORCE_BCN_IFS_8197F 0
+#define BIT_MASK_FORCE_BCN_IFS_8197F 0xff
+#define BIT_FORCE_BCN_IFS_8197F(x) \
+ (((x) & BIT_MASK_FORCE_BCN_IFS_8197F) << BIT_SHIFT_FORCE_BCN_IFS_8197F)
+#define BITS_FORCE_BCN_IFS_8197F \
+ (BIT_MASK_FORCE_BCN_IFS_8197F << BIT_SHIFT_FORCE_BCN_IFS_8197F)
+#define BIT_CLEAR_FORCE_BCN_IFS_8197F(x) ((x) & (~BITS_FORCE_BCN_IFS_8197F))
+#define BIT_GET_FORCE_BCN_IFS_8197F(x) \
+ (((x) >> BIT_SHIFT_FORCE_BCN_IFS_8197F) & BIT_MASK_FORCE_BCN_IFS_8197F)
+#define BIT_SET_FORCE_BCN_IFS_8197F(x, v) \
+ (BIT_CLEAR_FORCE_BCN_IFS_8197F(x) | BIT_FORCE_BCN_IFS_8197F(v))
+
+/* 2 REG_TXOP_MIN_8197F */
+#define BIT_NAV_BLK_HGQ_8197F BIT(15)
+#define BIT_NAV_BLK_MGQ_8197F BIT(14)
+
+#define BIT_SHIFT_TXOP_MIN_8197F 0
+#define BIT_MASK_TXOP_MIN_8197F 0x3fff
+#define BIT_TXOP_MIN_8197F(x) \
+ (((x) & BIT_MASK_TXOP_MIN_8197F) << BIT_SHIFT_TXOP_MIN_8197F)
+#define BITS_TXOP_MIN_8197F \
+ (BIT_MASK_TXOP_MIN_8197F << BIT_SHIFT_TXOP_MIN_8197F)
+#define BIT_CLEAR_TXOP_MIN_8197F(x) ((x) & (~BITS_TXOP_MIN_8197F))
+#define BIT_GET_TXOP_MIN_8197F(x) \
+ (((x) >> BIT_SHIFT_TXOP_MIN_8197F) & BIT_MASK_TXOP_MIN_8197F)
+#define BIT_SET_TXOP_MIN_8197F(x, v) \
+ (BIT_CLEAR_TXOP_MIN_8197F(x) | BIT_TXOP_MIN_8197F(v))
+
+/* 2 REG_PRE_BKF_TIME_8197F */
+
+#define BIT_SHIFT_PRE_BKF_TIME_8197F 0
+#define BIT_MASK_PRE_BKF_TIME_8197F 0xff
+#define BIT_PRE_BKF_TIME_8197F(x) \
+ (((x) & BIT_MASK_PRE_BKF_TIME_8197F) << BIT_SHIFT_PRE_BKF_TIME_8197F)
+#define BITS_PRE_BKF_TIME_8197F \
+ (BIT_MASK_PRE_BKF_TIME_8197F << BIT_SHIFT_PRE_BKF_TIME_8197F)
+#define BIT_CLEAR_PRE_BKF_TIME_8197F(x) ((x) & (~BITS_PRE_BKF_TIME_8197F))
+#define BIT_GET_PRE_BKF_TIME_8197F(x) \
+ (((x) >> BIT_SHIFT_PRE_BKF_TIME_8197F) & BIT_MASK_PRE_BKF_TIME_8197F)
+#define BIT_SET_PRE_BKF_TIME_8197F(x, v) \
+ (BIT_CLEAR_PRE_BKF_TIME_8197F(x) | BIT_PRE_BKF_TIME_8197F(v))
+
+/* 2 REG_CROSS_TXOP_CTRL_8197F */
+#define BIT_DTIM_BYPASS_8197F BIT(2)
+#define BIT_RTS_NAV_TXOP_8197F BIT(1)
+#define BIT_NOT_CROSS_TXOP_8197F BIT(0)
+
+/* 2 REG_TBTT_INT_SHIFT_CLI0_8197F */
+#define BIT_TBTT_INT_SHIFT_DIR_CLI0_8197F BIT(7)
+
+#define BIT_SHIFT_TBTT_INT_SHIFT_CLI0_8197F 0
+#define BIT_MASK_TBTT_INT_SHIFT_CLI0_8197F 0x7f
+#define BIT_TBTT_INT_SHIFT_CLI0_8197F(x) \
+ (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI0_8197F) \
+ << BIT_SHIFT_TBTT_INT_SHIFT_CLI0_8197F)
+#define BITS_TBTT_INT_SHIFT_CLI0_8197F \
+ (BIT_MASK_TBTT_INT_SHIFT_CLI0_8197F \
+ << BIT_SHIFT_TBTT_INT_SHIFT_CLI0_8197F)
+#define BIT_CLEAR_TBTT_INT_SHIFT_CLI0_8197F(x) \
+ ((x) & (~BITS_TBTT_INT_SHIFT_CLI0_8197F))
+#define BIT_GET_TBTT_INT_SHIFT_CLI0_8197F(x) \
+ (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI0_8197F) & \
+ BIT_MASK_TBTT_INT_SHIFT_CLI0_8197F)
+#define BIT_SET_TBTT_INT_SHIFT_CLI0_8197F(x, v) \
+ (BIT_CLEAR_TBTT_INT_SHIFT_CLI0_8197F(x) | \
+ BIT_TBTT_INT_SHIFT_CLI0_8197F(v))
+
+/* 2 REG_TBTT_INT_SHIFT_CLI1_8197F */
+#define BIT_TBTT_INT_SHIFT_DIR_CLI1_8197F BIT(7)
+
+#define BIT_SHIFT_TBTT_INT_SHIFT_CLI1_8197F 0
+#define BIT_MASK_TBTT_INT_SHIFT_CLI1_8197F 0x7f
+#define BIT_TBTT_INT_SHIFT_CLI1_8197F(x) \
+ (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI1_8197F) \
+ << BIT_SHIFT_TBTT_INT_SHIFT_CLI1_8197F)
+#define BITS_TBTT_INT_SHIFT_CLI1_8197F \
+ (BIT_MASK_TBTT_INT_SHIFT_CLI1_8197F \
+ << BIT_SHIFT_TBTT_INT_SHIFT_CLI1_8197F)
+#define BIT_CLEAR_TBTT_INT_SHIFT_CLI1_8197F(x) \
+ ((x) & (~BITS_TBTT_INT_SHIFT_CLI1_8197F))
+#define BIT_GET_TBTT_INT_SHIFT_CLI1_8197F(x) \
+ (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI1_8197F) & \
+ BIT_MASK_TBTT_INT_SHIFT_CLI1_8197F)
+#define BIT_SET_TBTT_INT_SHIFT_CLI1_8197F(x, v) \
+ (BIT_CLEAR_TBTT_INT_SHIFT_CLI1_8197F(x) | \
+ BIT_TBTT_INT_SHIFT_CLI1_8197F(v))
+
+/* 2 REG_TBTT_INT_SHIFT_CLI2_8197F */
+#define BIT_TBTT_INT_SHIFT_DIR_CLI2_8197F BIT(7)
+
+#define BIT_SHIFT_TBTT_INT_SHIFT_CLI2_8197F 0
+#define BIT_MASK_TBTT_INT_SHIFT_CLI2_8197F 0x7f
+#define BIT_TBTT_INT_SHIFT_CLI2_8197F(x) \
+ (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI2_8197F) \
+ << BIT_SHIFT_TBTT_INT_SHIFT_CLI2_8197F)
+#define BITS_TBTT_INT_SHIFT_CLI2_8197F \
+ (BIT_MASK_TBTT_INT_SHIFT_CLI2_8197F \
+ << BIT_SHIFT_TBTT_INT_SHIFT_CLI2_8197F)
+#define BIT_CLEAR_TBTT_INT_SHIFT_CLI2_8197F(x) \
+ ((x) & (~BITS_TBTT_INT_SHIFT_CLI2_8197F))
+#define BIT_GET_TBTT_INT_SHIFT_CLI2_8197F(x) \
+ (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI2_8197F) & \
+ BIT_MASK_TBTT_INT_SHIFT_CLI2_8197F)
+#define BIT_SET_TBTT_INT_SHIFT_CLI2_8197F(x, v) \
+ (BIT_CLEAR_TBTT_INT_SHIFT_CLI2_8197F(x) | \
+ BIT_TBTT_INT_SHIFT_CLI2_8197F(v))
+
+/* 2 REG_TBTT_INT_SHIFT_CLI3_8197F */
+#define BIT_TBTT_INT_SHIFT_DIR_CLI3_8197F BIT(7)
+
+#define BIT_SHIFT_TBTT_INT_SHIFT_CLI3_8197F 0
+#define BIT_MASK_TBTT_INT_SHIFT_CLI3_8197F 0x7f
+#define BIT_TBTT_INT_SHIFT_CLI3_8197F(x) \
+ (((x) & BIT_MASK_TBTT_INT_SHIFT_CLI3_8197F) \
+ << BIT_SHIFT_TBTT_INT_SHIFT_CLI3_8197F)
+#define BITS_TBTT_INT_SHIFT_CLI3_8197F \
+ (BIT_MASK_TBTT_INT_SHIFT_CLI3_8197F \
+ << BIT_SHIFT_TBTT_INT_SHIFT_CLI3_8197F)
+#define BIT_CLEAR_TBTT_INT_SHIFT_CLI3_8197F(x) \
+ ((x) & (~BITS_TBTT_INT_SHIFT_CLI3_8197F))
+#define BIT_GET_TBTT_INT_SHIFT_CLI3_8197F(x) \
+ (((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI3_8197F) & \
+ BIT_MASK_TBTT_INT_SHIFT_CLI3_8197F)
+#define BIT_SET_TBTT_INT_SHIFT_CLI3_8197F(x, v) \
+ (BIT_CLEAR_TBTT_INT_SHIFT_CLI3_8197F(x) | \
+ BIT_TBTT_INT_SHIFT_CLI3_8197F(v))
+
+/* 2 REG_TBTT_INT_SHIFT_ENABLE_8197F */
+#define BIT_EN_TBTT_RTY_8197F BIT(1)
+#define BIT_TBTT_INT_SHIFT_ENABLE_8197F BIT(0)
+
+/* 2 REG_ATIMWND2_8197F */
+
+#define BIT_SHIFT_ATIMWND2_8197F 0
+#define BIT_MASK_ATIMWND2_8197F 0xff
+#define BIT_ATIMWND2_8197F(x) \
+ (((x) & BIT_MASK_ATIMWND2_8197F) << BIT_SHIFT_ATIMWND2_8197F)
+#define BITS_ATIMWND2_8197F \
+ (BIT_MASK_ATIMWND2_8197F << BIT_SHIFT_ATIMWND2_8197F)
+#define BIT_CLEAR_ATIMWND2_8197F(x) ((x) & (~BITS_ATIMWND2_8197F))
+#define BIT_GET_ATIMWND2_8197F(x) \
+ (((x) >> BIT_SHIFT_ATIMWND2_8197F) & BIT_MASK_ATIMWND2_8197F)
+#define BIT_SET_ATIMWND2_8197F(x, v) \
+ (BIT_CLEAR_ATIMWND2_8197F(x) | BIT_ATIMWND2_8197F(v))
+
+/* 2 REG_ATIMWND3_8197F */
+
+#define BIT_SHIFT_ATIMWND3_8197F 0
+#define BIT_MASK_ATIMWND3_8197F 0xff
+#define BIT_ATIMWND3_8197F(x) \
+ (((x) & BIT_MASK_ATIMWND3_8197F) << BIT_SHIFT_ATIMWND3_8197F)
+#define BITS_ATIMWND3_8197F \
+ (BIT_MASK_ATIMWND3_8197F << BIT_SHIFT_ATIMWND3_8197F)
+#define BIT_CLEAR_ATIMWND3_8197F(x) ((x) & (~BITS_ATIMWND3_8197F))
+#define BIT_GET_ATIMWND3_8197F(x) \
+ (((x) >> BIT_SHIFT_ATIMWND3_8197F) & BIT_MASK_ATIMWND3_8197F)
+#define BIT_SET_ATIMWND3_8197F(x, v) \
+ (BIT_CLEAR_ATIMWND3_8197F(x) | BIT_ATIMWND3_8197F(v))
+
+/* 2 REG_ATIMWND4_8197F */
+
+#define BIT_SHIFT_ATIMWND4_8197F 0
+#define BIT_MASK_ATIMWND4_8197F 0xff
+#define BIT_ATIMWND4_8197F(x) \
+ (((x) & BIT_MASK_ATIMWND4_8197F) << BIT_SHIFT_ATIMWND4_8197F)
+#define BITS_ATIMWND4_8197F \
+ (BIT_MASK_ATIMWND4_8197F << BIT_SHIFT_ATIMWND4_8197F)
+#define BIT_CLEAR_ATIMWND4_8197F(x) ((x) & (~BITS_ATIMWND4_8197F))
+#define BIT_GET_ATIMWND4_8197F(x) \
+ (((x) >> BIT_SHIFT_ATIMWND4_8197F) & BIT_MASK_ATIMWND4_8197F)
+#define BIT_SET_ATIMWND4_8197F(x, v) \
+ (BIT_CLEAR_ATIMWND4_8197F(x) | BIT_ATIMWND4_8197F(v))
+
+/* 2 REG_ATIMWND5_8197F */
+
+#define BIT_SHIFT_ATIMWND5_8197F 0
+#define BIT_MASK_ATIMWND5_8197F 0xff
+#define BIT_ATIMWND5_8197F(x) \
+ (((x) & BIT_MASK_ATIMWND5_8197F) << BIT_SHIFT_ATIMWND5_8197F)
+#define BITS_ATIMWND5_8197F \
+ (BIT_MASK_ATIMWND5_8197F << BIT_SHIFT_ATIMWND5_8197F)
+#define BIT_CLEAR_ATIMWND5_8197F(x) ((x) & (~BITS_ATIMWND5_8197F))
+#define BIT_GET_ATIMWND5_8197F(x) \
+ (((x) >> BIT_SHIFT_ATIMWND5_8197F) & BIT_MASK_ATIMWND5_8197F)
+#define BIT_SET_ATIMWND5_8197F(x, v) \
+ (BIT_CLEAR_ATIMWND5_8197F(x) | BIT_ATIMWND5_8197F(v))
+
+/* 2 REG_ATIMWND6_8197F */
+
+#define BIT_SHIFT_ATIMWND6_8197F 0
+#define BIT_MASK_ATIMWND6_8197F 0xff
+#define BIT_ATIMWND6_8197F(x) \
+ (((x) & BIT_MASK_ATIMWND6_8197F) << BIT_SHIFT_ATIMWND6_8197F)
+#define BITS_ATIMWND6_8197F \
+ (BIT_MASK_ATIMWND6_8197F << BIT_SHIFT_ATIMWND6_8197F)
+#define BIT_CLEAR_ATIMWND6_8197F(x) ((x) & (~BITS_ATIMWND6_8197F))
+#define BIT_GET_ATIMWND6_8197F(x) \
+ (((x) >> BIT_SHIFT_ATIMWND6_8197F) & BIT_MASK_ATIMWND6_8197F)
+#define BIT_SET_ATIMWND6_8197F(x, v) \
+ (BIT_CLEAR_ATIMWND6_8197F(x) | BIT_ATIMWND6_8197F(v))
+
+/* 2 REG_ATIMWND7_8197F */
+
+#define BIT_SHIFT_ATIMWND7_8197F 0
+#define BIT_MASK_ATIMWND7_8197F 0xff
+#define BIT_ATIMWND7_8197F(x) \
+ (((x) & BIT_MASK_ATIMWND7_8197F) << BIT_SHIFT_ATIMWND7_8197F)
+#define BITS_ATIMWND7_8197F \
+ (BIT_MASK_ATIMWND7_8197F << BIT_SHIFT_ATIMWND7_8197F)
+#define BIT_CLEAR_ATIMWND7_8197F(x) ((x) & (~BITS_ATIMWND7_8197F))
+#define BIT_GET_ATIMWND7_8197F(x) \
+ (((x) >> BIT_SHIFT_ATIMWND7_8197F) & BIT_MASK_ATIMWND7_8197F)
+#define BIT_SET_ATIMWND7_8197F(x, v) \
+ (BIT_CLEAR_ATIMWND7_8197F(x) | BIT_ATIMWND7_8197F(v))
+
+/* 2 REG_ATIMUGT_8197F */
+
+#define BIT_SHIFT_ATIM_URGENT_8197F 0
+#define BIT_MASK_ATIM_URGENT_8197F 0xff
+#define BIT_ATIM_URGENT_8197F(x) \
+ (((x) & BIT_MASK_ATIM_URGENT_8197F) << BIT_SHIFT_ATIM_URGENT_8197F)
+#define BITS_ATIM_URGENT_8197F \
+ (BIT_MASK_ATIM_URGENT_8197F << BIT_SHIFT_ATIM_URGENT_8197F)
+#define BIT_CLEAR_ATIM_URGENT_8197F(x) ((x) & (~BITS_ATIM_URGENT_8197F))
+#define BIT_GET_ATIM_URGENT_8197F(x) \
+ (((x) >> BIT_SHIFT_ATIM_URGENT_8197F) & BIT_MASK_ATIM_URGENT_8197F)
+#define BIT_SET_ATIM_URGENT_8197F(x, v) \
+ (BIT_CLEAR_ATIM_URGENT_8197F(x) | BIT_ATIM_URGENT_8197F(v))
+
+/* 2 REG_HIQ_NO_LMT_EN_8197F */
+#define BIT_HIQ_NO_LMT_EN_VAP7_8197F BIT(7)
+#define BIT_HIQ_NO_LMT_EN_VAP6_8197F BIT(6)
+#define BIT_HIQ_NO_LMT_EN_VAP5_8197F BIT(5)
+#define BIT_HIQ_NO_LMT_EN_VAP4_8197F BIT(4)
+#define BIT_HIQ_NO_LMT_EN_VAP3_8197F BIT(3)
+#define BIT_HIQ_NO_LMT_EN_VAP2_8197F BIT(2)
+#define BIT_HIQ_NO_LMT_EN_VAP1_8197F BIT(1)
+#define BIT_HIQ_NO_LMT_EN_ROOT_8197F BIT(0)
+
+/* 2 REG_DTIM_COUNTER_ROOT_8197F */
+
+#define BIT_SHIFT_DTIM_COUNT_ROOT_8197F 0
+#define BIT_MASK_DTIM_COUNT_ROOT_8197F 0xff
+#define BIT_DTIM_COUNT_ROOT_8197F(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_ROOT_8197F) \
+ << BIT_SHIFT_DTIM_COUNT_ROOT_8197F)
+#define BITS_DTIM_COUNT_ROOT_8197F \
+ (BIT_MASK_DTIM_COUNT_ROOT_8197F << BIT_SHIFT_DTIM_COUNT_ROOT_8197F)
+#define BIT_CLEAR_DTIM_COUNT_ROOT_8197F(x) ((x) & (~BITS_DTIM_COUNT_ROOT_8197F))
+#define BIT_GET_DTIM_COUNT_ROOT_8197F(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_ROOT_8197F) & \
+ BIT_MASK_DTIM_COUNT_ROOT_8197F)
+#define BIT_SET_DTIM_COUNT_ROOT_8197F(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_ROOT_8197F(x) | BIT_DTIM_COUNT_ROOT_8197F(v))
+
+/* 2 REG_DTIM_COUNTER_VAP1_8197F */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP1_8197F 0
+#define BIT_MASK_DTIM_COUNT_VAP1_8197F 0xff
+#define BIT_DTIM_COUNT_VAP1_8197F(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_VAP1_8197F) \
+ << BIT_SHIFT_DTIM_COUNT_VAP1_8197F)
+#define BITS_DTIM_COUNT_VAP1_8197F \
+ (BIT_MASK_DTIM_COUNT_VAP1_8197F << BIT_SHIFT_DTIM_COUNT_VAP1_8197F)
+#define BIT_CLEAR_DTIM_COUNT_VAP1_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP1_8197F))
+#define BIT_GET_DTIM_COUNT_VAP1_8197F(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP1_8197F) & \
+ BIT_MASK_DTIM_COUNT_VAP1_8197F)
+#define BIT_SET_DTIM_COUNT_VAP1_8197F(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_VAP1_8197F(x) | BIT_DTIM_COUNT_VAP1_8197F(v))
+
+/* 2 REG_DTIM_COUNTER_VAP2_8197F */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP2_8197F 0
+#define BIT_MASK_DTIM_COUNT_VAP2_8197F 0xff
+#define BIT_DTIM_COUNT_VAP2_8197F(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_VAP2_8197F) \
+ << BIT_SHIFT_DTIM_COUNT_VAP2_8197F)
+#define BITS_DTIM_COUNT_VAP2_8197F \
+ (BIT_MASK_DTIM_COUNT_VAP2_8197F << BIT_SHIFT_DTIM_COUNT_VAP2_8197F)
+#define BIT_CLEAR_DTIM_COUNT_VAP2_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP2_8197F))
+#define BIT_GET_DTIM_COUNT_VAP2_8197F(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP2_8197F) & \
+ BIT_MASK_DTIM_COUNT_VAP2_8197F)
+#define BIT_SET_DTIM_COUNT_VAP2_8197F(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_VAP2_8197F(x) | BIT_DTIM_COUNT_VAP2_8197F(v))
+
+/* 2 REG_DTIM_COUNTER_VAP3_8197F */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP3_8197F 0
+#define BIT_MASK_DTIM_COUNT_VAP3_8197F 0xff
+#define BIT_DTIM_COUNT_VAP3_8197F(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_VAP3_8197F) \
+ << BIT_SHIFT_DTIM_COUNT_VAP3_8197F)
+#define BITS_DTIM_COUNT_VAP3_8197F \
+ (BIT_MASK_DTIM_COUNT_VAP3_8197F << BIT_SHIFT_DTIM_COUNT_VAP3_8197F)
+#define BIT_CLEAR_DTIM_COUNT_VAP3_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP3_8197F))
+#define BIT_GET_DTIM_COUNT_VAP3_8197F(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP3_8197F) & \
+ BIT_MASK_DTIM_COUNT_VAP3_8197F)
+#define BIT_SET_DTIM_COUNT_VAP3_8197F(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_VAP3_8197F(x) | BIT_DTIM_COUNT_VAP3_8197F(v))
+
+/* 2 REG_DTIM_COUNTER_VAP4_8197F */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP4_8197F 0
+#define BIT_MASK_DTIM_COUNT_VAP4_8197F 0xff
+#define BIT_DTIM_COUNT_VAP4_8197F(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_VAP4_8197F) \
+ << BIT_SHIFT_DTIM_COUNT_VAP4_8197F)
+#define BITS_DTIM_COUNT_VAP4_8197F \
+ (BIT_MASK_DTIM_COUNT_VAP4_8197F << BIT_SHIFT_DTIM_COUNT_VAP4_8197F)
+#define BIT_CLEAR_DTIM_COUNT_VAP4_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP4_8197F))
+#define BIT_GET_DTIM_COUNT_VAP4_8197F(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP4_8197F) & \
+ BIT_MASK_DTIM_COUNT_VAP4_8197F)
+#define BIT_SET_DTIM_COUNT_VAP4_8197F(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_VAP4_8197F(x) | BIT_DTIM_COUNT_VAP4_8197F(v))
+
+/* 2 REG_DTIM_COUNTER_VAP5_8197F */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP5_8197F 0
+#define BIT_MASK_DTIM_COUNT_VAP5_8197F 0xff
+#define BIT_DTIM_COUNT_VAP5_8197F(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_VAP5_8197F) \
+ << BIT_SHIFT_DTIM_COUNT_VAP5_8197F)
+#define BITS_DTIM_COUNT_VAP5_8197F \
+ (BIT_MASK_DTIM_COUNT_VAP5_8197F << BIT_SHIFT_DTIM_COUNT_VAP5_8197F)
+#define BIT_CLEAR_DTIM_COUNT_VAP5_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP5_8197F))
+#define BIT_GET_DTIM_COUNT_VAP5_8197F(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP5_8197F) & \
+ BIT_MASK_DTIM_COUNT_VAP5_8197F)
+#define BIT_SET_DTIM_COUNT_VAP5_8197F(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_VAP5_8197F(x) | BIT_DTIM_COUNT_VAP5_8197F(v))
+
+/* 2 REG_DTIM_COUNTER_VAP6_8197F */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP6_8197F 0
+#define BIT_MASK_DTIM_COUNT_VAP6_8197F 0xff
+#define BIT_DTIM_COUNT_VAP6_8197F(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_VAP6_8197F) \
+ << BIT_SHIFT_DTIM_COUNT_VAP6_8197F)
+#define BITS_DTIM_COUNT_VAP6_8197F \
+ (BIT_MASK_DTIM_COUNT_VAP6_8197F << BIT_SHIFT_DTIM_COUNT_VAP6_8197F)
+#define BIT_CLEAR_DTIM_COUNT_VAP6_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP6_8197F))
+#define BIT_GET_DTIM_COUNT_VAP6_8197F(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP6_8197F) & \
+ BIT_MASK_DTIM_COUNT_VAP6_8197F)
+#define BIT_SET_DTIM_COUNT_VAP6_8197F(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_VAP6_8197F(x) | BIT_DTIM_COUNT_VAP6_8197F(v))
+
+/* 2 REG_DTIM_COUNTER_VAP7_8197F */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP7_8197F 0
+#define BIT_MASK_DTIM_COUNT_VAP7_8197F 0xff
+#define BIT_DTIM_COUNT_VAP7_8197F(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_VAP7_8197F) \
+ << BIT_SHIFT_DTIM_COUNT_VAP7_8197F)
+#define BITS_DTIM_COUNT_VAP7_8197F \
+ (BIT_MASK_DTIM_COUNT_VAP7_8197F << BIT_SHIFT_DTIM_COUNT_VAP7_8197F)
+#define BIT_CLEAR_DTIM_COUNT_VAP7_8197F(x) ((x) & (~BITS_DTIM_COUNT_VAP7_8197F))
+#define BIT_GET_DTIM_COUNT_VAP7_8197F(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP7_8197F) & \
+ BIT_MASK_DTIM_COUNT_VAP7_8197F)
+#define BIT_SET_DTIM_COUNT_VAP7_8197F(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_VAP7_8197F(x) | BIT_DTIM_COUNT_VAP7_8197F(v))
+
+/* 2 REG_DIS_ATIM_8197F */
+#define BIT_DIS_ATIM_VAP7_8197F BIT(7)
+#define BIT_DIS_ATIM_VAP6_8197F BIT(6)
+#define BIT_DIS_ATIM_VAP5_8197F BIT(5)
+#define BIT_DIS_ATIM_VAP4_8197F BIT(4)
+#define BIT_DIS_ATIM_VAP3_8197F BIT(3)
+#define BIT_DIS_ATIM_VAP2_8197F BIT(2)
+#define BIT_DIS_ATIM_VAP1_8197F BIT(1)
+#define BIT_DIS_ATIM_ROOT_8197F BIT(0)
+
+/* 2 REG_EARLY_128US_8197F */
+
+#define BIT_SHIFT_TSFT_SEL_TIMER1_8197F 3
+#define BIT_MASK_TSFT_SEL_TIMER1_8197F 0x7
+#define BIT_TSFT_SEL_TIMER1_8197F(x) \
+ (((x) & BIT_MASK_TSFT_SEL_TIMER1_8197F) \
+ << BIT_SHIFT_TSFT_SEL_TIMER1_8197F)
+#define BITS_TSFT_SEL_TIMER1_8197F \
+ (BIT_MASK_TSFT_SEL_TIMER1_8197F << BIT_SHIFT_TSFT_SEL_TIMER1_8197F)
+#define BIT_CLEAR_TSFT_SEL_TIMER1_8197F(x) ((x) & (~BITS_TSFT_SEL_TIMER1_8197F))
+#define BIT_GET_TSFT_SEL_TIMER1_8197F(x) \
+ (((x) >> BIT_SHIFT_TSFT_SEL_TIMER1_8197F) & \
+ BIT_MASK_TSFT_SEL_TIMER1_8197F)
+#define BIT_SET_TSFT_SEL_TIMER1_8197F(x, v) \
+ (BIT_CLEAR_TSFT_SEL_TIMER1_8197F(x) | BIT_TSFT_SEL_TIMER1_8197F(v))
+
+#define BIT_SHIFT_EARLY_128US_8197F 0
+#define BIT_MASK_EARLY_128US_8197F 0x7
+#define BIT_EARLY_128US_8197F(x) \
+ (((x) & BIT_MASK_EARLY_128US_8197F) << BIT_SHIFT_EARLY_128US_8197F)
+#define BITS_EARLY_128US_8197F \
+ (BIT_MASK_EARLY_128US_8197F << BIT_SHIFT_EARLY_128US_8197F)
+#define BIT_CLEAR_EARLY_128US_8197F(x) ((x) & (~BITS_EARLY_128US_8197F))
+#define BIT_GET_EARLY_128US_8197F(x) \
+ (((x) >> BIT_SHIFT_EARLY_128US_8197F) & BIT_MASK_EARLY_128US_8197F)
+#define BIT_SET_EARLY_128US_8197F(x, v) \
+ (BIT_CLEAR_EARLY_128US_8197F(x) | BIT_EARLY_128US_8197F(v))
+
+/* 2 REG_P2PPS1_CTRL_8197F */
+#define BIT_P2P1_CTW_ALLSTASLEEP_8197F BIT(7)
+#define BIT_P2P1_OFF_DISTX_EN_8197F BIT(6)
+#define BIT_P2P1_PWR_MGT_EN_8197F BIT(5)
+#define BIT_P2P1_NOA1_EN_8197F BIT(2)
+#define BIT_P2P1_NOA0_EN_8197F BIT(1)
+
+/* 2 REG_P2PPS2_CTRL_8197F */
+#define BIT_P2P2_CTW_ALLSTASLEEP_8197F BIT(7)
+#define BIT_P2P2_OFF_DISTX_EN_8197F BIT(6)
+#define BIT_P2P2_PWR_MGT_EN_8197F BIT(5)
+#define BIT_P2P2_NOA1_EN_8197F BIT(2)
+#define BIT_P2P2_NOA0_EN_8197F BIT(1)
+
+/* 2 REG_TIMER0_SRC_SEL_8197F */
+
+#define BIT_SHIFT_SYNC_CLI_SEL_8197F 4
+#define BIT_MASK_SYNC_CLI_SEL_8197F 0x7
+#define BIT_SYNC_CLI_SEL_8197F(x) \
+ (((x) & BIT_MASK_SYNC_CLI_SEL_8197F) << BIT_SHIFT_SYNC_CLI_SEL_8197F)
+#define BITS_SYNC_CLI_SEL_8197F \
+ (BIT_MASK_SYNC_CLI_SEL_8197F << BIT_SHIFT_SYNC_CLI_SEL_8197F)
+#define BIT_CLEAR_SYNC_CLI_SEL_8197F(x) ((x) & (~BITS_SYNC_CLI_SEL_8197F))
+#define BIT_GET_SYNC_CLI_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_SYNC_CLI_SEL_8197F) & BIT_MASK_SYNC_CLI_SEL_8197F)
+#define BIT_SET_SYNC_CLI_SEL_8197F(x, v) \
+ (BIT_CLEAR_SYNC_CLI_SEL_8197F(x) | BIT_SYNC_CLI_SEL_8197F(v))
+
+#define BIT_SHIFT_TSFT_SEL_TIMER0_8197F 0
+#define BIT_MASK_TSFT_SEL_TIMER0_8197F 0x7
+#define BIT_TSFT_SEL_TIMER0_8197F(x) \
+ (((x) & BIT_MASK_TSFT_SEL_TIMER0_8197F) \
+ << BIT_SHIFT_TSFT_SEL_TIMER0_8197F)
+#define BITS_TSFT_SEL_TIMER0_8197F \
+ (BIT_MASK_TSFT_SEL_TIMER0_8197F << BIT_SHIFT_TSFT_SEL_TIMER0_8197F)
+#define BIT_CLEAR_TSFT_SEL_TIMER0_8197F(x) ((x) & (~BITS_TSFT_SEL_TIMER0_8197F))
+#define BIT_GET_TSFT_SEL_TIMER0_8197F(x) \
+ (((x) >> BIT_SHIFT_TSFT_SEL_TIMER0_8197F) & \
+ BIT_MASK_TSFT_SEL_TIMER0_8197F)
+#define BIT_SET_TSFT_SEL_TIMER0_8197F(x, v) \
+ (BIT_CLEAR_TSFT_SEL_TIMER0_8197F(x) | BIT_TSFT_SEL_TIMER0_8197F(v))
+
+/* 2 REG_NOA_UNIT_SEL_8197F */
+
+#define BIT_SHIFT_NOA_UNIT2_SEL_8197F 8
+#define BIT_MASK_NOA_UNIT2_SEL_8197F 0x7
+#define BIT_NOA_UNIT2_SEL_8197F(x) \
+ (((x) & BIT_MASK_NOA_UNIT2_SEL_8197F) << BIT_SHIFT_NOA_UNIT2_SEL_8197F)
+#define BITS_NOA_UNIT2_SEL_8197F \
+ (BIT_MASK_NOA_UNIT2_SEL_8197F << BIT_SHIFT_NOA_UNIT2_SEL_8197F)
+#define BIT_CLEAR_NOA_UNIT2_SEL_8197F(x) ((x) & (~BITS_NOA_UNIT2_SEL_8197F))
+#define BIT_GET_NOA_UNIT2_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_NOA_UNIT2_SEL_8197F) & BIT_MASK_NOA_UNIT2_SEL_8197F)
+#define BIT_SET_NOA_UNIT2_SEL_8197F(x, v) \
+ (BIT_CLEAR_NOA_UNIT2_SEL_8197F(x) | BIT_NOA_UNIT2_SEL_8197F(v))
+
+#define BIT_SHIFT_NOA_UNIT1_SEL_8197F 4
+#define BIT_MASK_NOA_UNIT1_SEL_8197F 0x7
+#define BIT_NOA_UNIT1_SEL_8197F(x) \
+ (((x) & BIT_MASK_NOA_UNIT1_SEL_8197F) << BIT_SHIFT_NOA_UNIT1_SEL_8197F)
+#define BITS_NOA_UNIT1_SEL_8197F \
+ (BIT_MASK_NOA_UNIT1_SEL_8197F << BIT_SHIFT_NOA_UNIT1_SEL_8197F)
+#define BIT_CLEAR_NOA_UNIT1_SEL_8197F(x) ((x) & (~BITS_NOA_UNIT1_SEL_8197F))
+#define BIT_GET_NOA_UNIT1_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_NOA_UNIT1_SEL_8197F) & BIT_MASK_NOA_UNIT1_SEL_8197F)
+#define BIT_SET_NOA_UNIT1_SEL_8197F(x, v) \
+ (BIT_CLEAR_NOA_UNIT1_SEL_8197F(x) | BIT_NOA_UNIT1_SEL_8197F(v))
+
+#define BIT_SHIFT_NOA_UNIT0_SEL_8197F 0
+#define BIT_MASK_NOA_UNIT0_SEL_8197F 0x7
+#define BIT_NOA_UNIT0_SEL_8197F(x) \
+ (((x) & BIT_MASK_NOA_UNIT0_SEL_8197F) << BIT_SHIFT_NOA_UNIT0_SEL_8197F)
+#define BITS_NOA_UNIT0_SEL_8197F \
+ (BIT_MASK_NOA_UNIT0_SEL_8197F << BIT_SHIFT_NOA_UNIT0_SEL_8197F)
+#define BIT_CLEAR_NOA_UNIT0_SEL_8197F(x) ((x) & (~BITS_NOA_UNIT0_SEL_8197F))
+#define BIT_GET_NOA_UNIT0_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_NOA_UNIT0_SEL_8197F) & BIT_MASK_NOA_UNIT0_SEL_8197F)
+#define BIT_SET_NOA_UNIT0_SEL_8197F(x, v) \
+ (BIT_CLEAR_NOA_UNIT0_SEL_8197F(x) | BIT_NOA_UNIT0_SEL_8197F(v))
+
+/* 2 REG_P2POFF_DIS_TXTIME_8197F */
+
+#define BIT_SHIFT_P2POFF_DIS_TXTIME_8197F 0
+#define BIT_MASK_P2POFF_DIS_TXTIME_8197F 0xff
+#define BIT_P2POFF_DIS_TXTIME_8197F(x) \
+ (((x) & BIT_MASK_P2POFF_DIS_TXTIME_8197F) \
+ << BIT_SHIFT_P2POFF_DIS_TXTIME_8197F)
+#define BITS_P2POFF_DIS_TXTIME_8197F \
+ (BIT_MASK_P2POFF_DIS_TXTIME_8197F << BIT_SHIFT_P2POFF_DIS_TXTIME_8197F)
+#define BIT_CLEAR_P2POFF_DIS_TXTIME_8197F(x) \
+ ((x) & (~BITS_P2POFF_DIS_TXTIME_8197F))
+#define BIT_GET_P2POFF_DIS_TXTIME_8197F(x) \
+ (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8197F) & \
+ BIT_MASK_P2POFF_DIS_TXTIME_8197F)
+#define BIT_SET_P2POFF_DIS_TXTIME_8197F(x, v) \
+ (BIT_CLEAR_P2POFF_DIS_TXTIME_8197F(x) | BIT_P2POFF_DIS_TXTIME_8197F(v))
+
+/* 2 REG_MBSSID_BCN_SPACE2_8197F */
+
+#define BIT_SHIFT_BCN_SPACE_CLINT2_8197F 16
+#define BIT_MASK_BCN_SPACE_CLINT2_8197F 0xfff
+#define BIT_BCN_SPACE_CLINT2_8197F(x) \
+ (((x) & BIT_MASK_BCN_SPACE_CLINT2_8197F) \
+ << BIT_SHIFT_BCN_SPACE_CLINT2_8197F)
+#define BITS_BCN_SPACE_CLINT2_8197F \
+ (BIT_MASK_BCN_SPACE_CLINT2_8197F << BIT_SHIFT_BCN_SPACE_CLINT2_8197F)
+#define BIT_CLEAR_BCN_SPACE_CLINT2_8197F(x) \
+ ((x) & (~BITS_BCN_SPACE_CLINT2_8197F))
+#define BIT_GET_BCN_SPACE_CLINT2_8197F(x) \
+ (((x) >> BIT_SHIFT_BCN_SPACE_CLINT2_8197F) & \
+ BIT_MASK_BCN_SPACE_CLINT2_8197F)
+#define BIT_SET_BCN_SPACE_CLINT2_8197F(x, v) \
+ (BIT_CLEAR_BCN_SPACE_CLINT2_8197F(x) | BIT_BCN_SPACE_CLINT2_8197F(v))
+
+#define BIT_SHIFT_BCN_SPACE_CLINT1_8197F 0
+#define BIT_MASK_BCN_SPACE_CLINT1_8197F 0xfff
+#define BIT_BCN_SPACE_CLINT1_8197F(x) \
+ (((x) & BIT_MASK_BCN_SPACE_CLINT1_8197F) \
+ << BIT_SHIFT_BCN_SPACE_CLINT1_8197F)
+#define BITS_BCN_SPACE_CLINT1_8197F \
+ (BIT_MASK_BCN_SPACE_CLINT1_8197F << BIT_SHIFT_BCN_SPACE_CLINT1_8197F)
+#define BIT_CLEAR_BCN_SPACE_CLINT1_8197F(x) \
+ ((x) & (~BITS_BCN_SPACE_CLINT1_8197F))
+#define BIT_GET_BCN_SPACE_CLINT1_8197F(x) \
+ (((x) >> BIT_SHIFT_BCN_SPACE_CLINT1_8197F) & \
+ BIT_MASK_BCN_SPACE_CLINT1_8197F)
+#define BIT_SET_BCN_SPACE_CLINT1_8197F(x, v) \
+ (BIT_CLEAR_BCN_SPACE_CLINT1_8197F(x) | BIT_BCN_SPACE_CLINT1_8197F(v))
+
+/* 2 REG_MBSSID_BCN_SPACE3_8197F */
+
+#define BIT_SHIFT_SUB_BCN_SPACE_8197F 16
+#define BIT_MASK_SUB_BCN_SPACE_8197F 0xff
+#define BIT_SUB_BCN_SPACE_8197F(x) \
+ (((x) & BIT_MASK_SUB_BCN_SPACE_8197F) << BIT_SHIFT_SUB_BCN_SPACE_8197F)
+#define BITS_SUB_BCN_SPACE_8197F \
+ (BIT_MASK_SUB_BCN_SPACE_8197F << BIT_SHIFT_SUB_BCN_SPACE_8197F)
+#define BIT_CLEAR_SUB_BCN_SPACE_8197F(x) ((x) & (~BITS_SUB_BCN_SPACE_8197F))
+#define BIT_GET_SUB_BCN_SPACE_8197F(x) \
+ (((x) >> BIT_SHIFT_SUB_BCN_SPACE_8197F) & BIT_MASK_SUB_BCN_SPACE_8197F)
+#define BIT_SET_SUB_BCN_SPACE_8197F(x, v) \
+ (BIT_CLEAR_SUB_BCN_SPACE_8197F(x) | BIT_SUB_BCN_SPACE_8197F(v))
+
+#define BIT_SHIFT_BCN_SPACE_CLINT3_8197F 0
+#define BIT_MASK_BCN_SPACE_CLINT3_8197F 0xfff
+#define BIT_BCN_SPACE_CLINT3_8197F(x) \
+ (((x) & BIT_MASK_BCN_SPACE_CLINT3_8197F) \
+ << BIT_SHIFT_BCN_SPACE_CLINT3_8197F)
+#define BITS_BCN_SPACE_CLINT3_8197F \
+ (BIT_MASK_BCN_SPACE_CLINT3_8197F << BIT_SHIFT_BCN_SPACE_CLINT3_8197F)
+#define BIT_CLEAR_BCN_SPACE_CLINT3_8197F(x) \
+ ((x) & (~BITS_BCN_SPACE_CLINT3_8197F))
+#define BIT_GET_BCN_SPACE_CLINT3_8197F(x) \
+ (((x) >> BIT_SHIFT_BCN_SPACE_CLINT3_8197F) & \
+ BIT_MASK_BCN_SPACE_CLINT3_8197F)
+#define BIT_SET_BCN_SPACE_CLINT3_8197F(x, v) \
+ (BIT_CLEAR_BCN_SPACE_CLINT3_8197F(x) | BIT_BCN_SPACE_CLINT3_8197F(v))
+
+/* 2 REG_ACMHWCTRL_8197F */
+#define BIT_BEQ_ACM_STATUS_8197F BIT(7)
+#define BIT_VIQ_ACM_STATUS_8197F BIT(6)
+#define BIT_VOQ_ACM_STATUS_8197F BIT(5)
+#define BIT_BEQ_ACM_EN_8197F BIT(3)
+#define BIT_VIQ_ACM_EN_8197F BIT(2)
+#define BIT_VOQ_ACM_EN_8197F BIT(1)
+#define BIT_ACMHWEN_8197F BIT(0)
+
+/* 2 REG_ACMRSTCTRL_8197F */
+#define BIT_BE_ACM_RESET_USED_TIME_8197F BIT(2)
+#define BIT_VI_ACM_RESET_USED_TIME_8197F BIT(1)
+#define BIT_VO_ACM_RESET_USED_TIME_8197F BIT(0)
+
+/* 2 REG_ACMAVG_8197F */
+
+#define BIT_SHIFT_AVGPERIOD_8197F 0
+#define BIT_MASK_AVGPERIOD_8197F 0xffff
+#define BIT_AVGPERIOD_8197F(x) \
+ (((x) & BIT_MASK_AVGPERIOD_8197F) << BIT_SHIFT_AVGPERIOD_8197F)
+#define BITS_AVGPERIOD_8197F \
+ (BIT_MASK_AVGPERIOD_8197F << BIT_SHIFT_AVGPERIOD_8197F)
+#define BIT_CLEAR_AVGPERIOD_8197F(x) ((x) & (~BITS_AVGPERIOD_8197F))
+#define BIT_GET_AVGPERIOD_8197F(x) \
+ (((x) >> BIT_SHIFT_AVGPERIOD_8197F) & BIT_MASK_AVGPERIOD_8197F)
+#define BIT_SET_AVGPERIOD_8197F(x, v) \
+ (BIT_CLEAR_AVGPERIOD_8197F(x) | BIT_AVGPERIOD_8197F(v))
+
+/* 2 REG_VO_ADMTIME_8197F */
+
+#define BIT_SHIFT_VO_ADMITTED_TIME_8197F 0
+#define BIT_MASK_VO_ADMITTED_TIME_8197F 0xffff
+#define BIT_VO_ADMITTED_TIME_8197F(x) \
+ (((x) & BIT_MASK_VO_ADMITTED_TIME_8197F) \
+ << BIT_SHIFT_VO_ADMITTED_TIME_8197F)
+#define BITS_VO_ADMITTED_TIME_8197F \
+ (BIT_MASK_VO_ADMITTED_TIME_8197F << BIT_SHIFT_VO_ADMITTED_TIME_8197F)
+#define BIT_CLEAR_VO_ADMITTED_TIME_8197F(x) \
+ ((x) & (~BITS_VO_ADMITTED_TIME_8197F))
+#define BIT_GET_VO_ADMITTED_TIME_8197F(x) \
+ (((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8197F) & \
+ BIT_MASK_VO_ADMITTED_TIME_8197F)
+#define BIT_SET_VO_ADMITTED_TIME_8197F(x, v) \
+ (BIT_CLEAR_VO_ADMITTED_TIME_8197F(x) | BIT_VO_ADMITTED_TIME_8197F(v))
+
+/* 2 REG_VI_ADMTIME_8197F */
+
+#define BIT_SHIFT_VI_ADMITTED_TIME_8197F 0
+#define BIT_MASK_VI_ADMITTED_TIME_8197F 0xffff
+#define BIT_VI_ADMITTED_TIME_8197F(x) \
+ (((x) & BIT_MASK_VI_ADMITTED_TIME_8197F) \
+ << BIT_SHIFT_VI_ADMITTED_TIME_8197F)
+#define BITS_VI_ADMITTED_TIME_8197F \
+ (BIT_MASK_VI_ADMITTED_TIME_8197F << BIT_SHIFT_VI_ADMITTED_TIME_8197F)
+#define BIT_CLEAR_VI_ADMITTED_TIME_8197F(x) \
+ ((x) & (~BITS_VI_ADMITTED_TIME_8197F))
+#define BIT_GET_VI_ADMITTED_TIME_8197F(x) \
+ (((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8197F) & \
+ BIT_MASK_VI_ADMITTED_TIME_8197F)
+#define BIT_SET_VI_ADMITTED_TIME_8197F(x, v) \
+ (BIT_CLEAR_VI_ADMITTED_TIME_8197F(x) | BIT_VI_ADMITTED_TIME_8197F(v))
+
+/* 2 REG_BE_ADMTIME_8197F */
+
+#define BIT_SHIFT_BE_ADMITTED_TIME_8197F 0
+#define BIT_MASK_BE_ADMITTED_TIME_8197F 0xffff
+#define BIT_BE_ADMITTED_TIME_8197F(x) \
+ (((x) & BIT_MASK_BE_ADMITTED_TIME_8197F) \
+ << BIT_SHIFT_BE_ADMITTED_TIME_8197F)
+#define BITS_BE_ADMITTED_TIME_8197F \
+ (BIT_MASK_BE_ADMITTED_TIME_8197F << BIT_SHIFT_BE_ADMITTED_TIME_8197F)
+#define BIT_CLEAR_BE_ADMITTED_TIME_8197F(x) \
+ ((x) & (~BITS_BE_ADMITTED_TIME_8197F))
+#define BIT_GET_BE_ADMITTED_TIME_8197F(x) \
+ (((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8197F) & \
+ BIT_MASK_BE_ADMITTED_TIME_8197F)
+#define BIT_SET_BE_ADMITTED_TIME_8197F(x, v) \
+ (BIT_CLEAR_BE_ADMITTED_TIME_8197F(x) | BIT_BE_ADMITTED_TIME_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+#define BIT_CHANGE_POW_BCN_AREA_8197F BIT(9)
+
+/* 2 REG_EDCA_RANDOM_GEN_8197F */
+
+#define BIT_SHIFT_RANDOM_GEN_8197F 0
+#define BIT_MASK_RANDOM_GEN_8197F 0xffffff
+#define BIT_RANDOM_GEN_8197F(x) \
+ (((x) & BIT_MASK_RANDOM_GEN_8197F) << BIT_SHIFT_RANDOM_GEN_8197F)
+#define BITS_RANDOM_GEN_8197F \
+ (BIT_MASK_RANDOM_GEN_8197F << BIT_SHIFT_RANDOM_GEN_8197F)
+#define BIT_CLEAR_RANDOM_GEN_8197F(x) ((x) & (~BITS_RANDOM_GEN_8197F))
+#define BIT_GET_RANDOM_GEN_8197F(x) \
+ (((x) >> BIT_SHIFT_RANDOM_GEN_8197F) & BIT_MASK_RANDOM_GEN_8197F)
+#define BIT_SET_RANDOM_GEN_8197F(x, v) \
+ (BIT_CLEAR_RANDOM_GEN_8197F(x) | BIT_RANDOM_GEN_8197F(v))
+
+/* 2 REG_TXCMD_NOA_SEL_8197F */
+
+#define BIT_SHIFT_NOA_SEL_V2_8197F 4
+#define BIT_MASK_NOA_SEL_V2_8197F 0x7
+#define BIT_NOA_SEL_V2_8197F(x) \
+ (((x) & BIT_MASK_NOA_SEL_V2_8197F) << BIT_SHIFT_NOA_SEL_V2_8197F)
+#define BITS_NOA_SEL_V2_8197F \
+ (BIT_MASK_NOA_SEL_V2_8197F << BIT_SHIFT_NOA_SEL_V2_8197F)
+#define BIT_CLEAR_NOA_SEL_V2_8197F(x) ((x) & (~BITS_NOA_SEL_V2_8197F))
+#define BIT_GET_NOA_SEL_V2_8197F(x) \
+ (((x) >> BIT_SHIFT_NOA_SEL_V2_8197F) & BIT_MASK_NOA_SEL_V2_8197F)
+#define BIT_SET_NOA_SEL_V2_8197F(x, v) \
+ (BIT_CLEAR_NOA_SEL_V2_8197F(x) | BIT_NOA_SEL_V2_8197F(v))
+
+#define BIT_SHIFT_TXCMD_SEG_SEL_8197F 0
+#define BIT_MASK_TXCMD_SEG_SEL_8197F 0xf
+#define BIT_TXCMD_SEG_SEL_8197F(x) \
+ (((x) & BIT_MASK_TXCMD_SEG_SEL_8197F) << BIT_SHIFT_TXCMD_SEG_SEL_8197F)
+#define BITS_TXCMD_SEG_SEL_8197F \
+ (BIT_MASK_TXCMD_SEG_SEL_8197F << BIT_SHIFT_TXCMD_SEG_SEL_8197F)
+#define BIT_CLEAR_TXCMD_SEG_SEL_8197F(x) ((x) & (~BITS_TXCMD_SEG_SEL_8197F))
+#define BIT_GET_TXCMD_SEG_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8197F) & BIT_MASK_TXCMD_SEG_SEL_8197F)
+#define BIT_SET_TXCMD_SEG_SEL_8197F(x, v) \
+ (BIT_CLEAR_TXCMD_SEG_SEL_8197F(x) | BIT_TXCMD_SEG_SEL_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+#define BIT_BCNERR_CNT_EN_8197F BIT(20)
+
+#define BIT_SHIFT_BCNERR_PORT_SEL_8197F 16
+#define BIT_MASK_BCNERR_PORT_SEL_8197F 0x7
+#define BIT_BCNERR_PORT_SEL_8197F(x) \
+ (((x) & BIT_MASK_BCNERR_PORT_SEL_8197F) \
+ << BIT_SHIFT_BCNERR_PORT_SEL_8197F)
+#define BITS_BCNERR_PORT_SEL_8197F \
+ (BIT_MASK_BCNERR_PORT_SEL_8197F << BIT_SHIFT_BCNERR_PORT_SEL_8197F)
+#define BIT_CLEAR_BCNERR_PORT_SEL_8197F(x) ((x) & (~BITS_BCNERR_PORT_SEL_8197F))
+#define BIT_GET_BCNERR_PORT_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_BCNERR_PORT_SEL_8197F) & \
+ BIT_MASK_BCNERR_PORT_SEL_8197F)
+#define BIT_SET_BCNERR_PORT_SEL_8197F(x, v) \
+ (BIT_CLEAR_BCNERR_PORT_SEL_8197F(x) | BIT_BCNERR_PORT_SEL_8197F(v))
+
+#define BIT_SHIFT_TXPAUSE1_8197F 8
+#define BIT_MASK_TXPAUSE1_8197F 0xff
+#define BIT_TXPAUSE1_8197F(x) \
+ (((x) & BIT_MASK_TXPAUSE1_8197F) << BIT_SHIFT_TXPAUSE1_8197F)
+#define BITS_TXPAUSE1_8197F \
+ (BIT_MASK_TXPAUSE1_8197F << BIT_SHIFT_TXPAUSE1_8197F)
+#define BIT_CLEAR_TXPAUSE1_8197F(x) ((x) & (~BITS_TXPAUSE1_8197F))
+#define BIT_GET_TXPAUSE1_8197F(x) \
+ (((x) >> BIT_SHIFT_TXPAUSE1_8197F) & BIT_MASK_TXPAUSE1_8197F)
+#define BIT_SET_TXPAUSE1_8197F(x, v) \
+ (BIT_CLEAR_TXPAUSE1_8197F(x) | BIT_TXPAUSE1_8197F(v))
+
+#define BIT_SHIFT_BW_CFG_8197F 0
+#define BIT_MASK_BW_CFG_8197F 0x3
+#define BIT_BW_CFG_8197F(x) \
+ (((x) & BIT_MASK_BW_CFG_8197F) << BIT_SHIFT_BW_CFG_8197F)
+#define BITS_BW_CFG_8197F (BIT_MASK_BW_CFG_8197F << BIT_SHIFT_BW_CFG_8197F)
+#define BIT_CLEAR_BW_CFG_8197F(x) ((x) & (~BITS_BW_CFG_8197F))
+#define BIT_GET_BW_CFG_8197F(x) \
+ (((x) >> BIT_SHIFT_BW_CFG_8197F) & BIT_MASK_BW_CFG_8197F)
+#define BIT_SET_BW_CFG_8197F(x, v) \
+ (BIT_CLEAR_BW_CFG_8197F(x) | BIT_BW_CFG_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+#define BIT_SHIFT_RXBCN_TIMER_8197F 16
+#define BIT_MASK_RXBCN_TIMER_8197F 0xffff
+#define BIT_RXBCN_TIMER_8197F(x) \
+ (((x) & BIT_MASK_RXBCN_TIMER_8197F) << BIT_SHIFT_RXBCN_TIMER_8197F)
+#define BITS_RXBCN_TIMER_8197F \
+ (BIT_MASK_RXBCN_TIMER_8197F << BIT_SHIFT_RXBCN_TIMER_8197F)
+#define BIT_CLEAR_RXBCN_TIMER_8197F(x) ((x) & (~BITS_RXBCN_TIMER_8197F))
+#define BIT_GET_RXBCN_TIMER_8197F(x) \
+ (((x) >> BIT_SHIFT_RXBCN_TIMER_8197F) & BIT_MASK_RXBCN_TIMER_8197F)
+#define BIT_SET_RXBCN_TIMER_8197F(x, v) \
+ (BIT_CLEAR_RXBCN_TIMER_8197F(x) | BIT_RXBCN_TIMER_8197F(v))
+
+#define BIT_SHIFT_BCN_ELY_ADJ_8197F 0
+#define BIT_MASK_BCN_ELY_ADJ_8197F 0xffff
+#define BIT_BCN_ELY_ADJ_8197F(x) \
+ (((x) & BIT_MASK_BCN_ELY_ADJ_8197F) << BIT_SHIFT_BCN_ELY_ADJ_8197F)
+#define BITS_BCN_ELY_ADJ_8197F \
+ (BIT_MASK_BCN_ELY_ADJ_8197F << BIT_SHIFT_BCN_ELY_ADJ_8197F)
+#define BIT_CLEAR_BCN_ELY_ADJ_8197F(x) ((x) & (~BITS_BCN_ELY_ADJ_8197F))
+#define BIT_GET_BCN_ELY_ADJ_8197F(x) \
+ (((x) >> BIT_SHIFT_BCN_ELY_ADJ_8197F) & BIT_MASK_BCN_ELY_ADJ_8197F)
+#define BIT_SET_BCN_ELY_ADJ_8197F(x, v) \
+ (BIT_CLEAR_BCN_ELY_ADJ_8197F(x) | BIT_BCN_ELY_ADJ_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+#define BIT_SHIFT_BCNERR_CNT_OTHERS_8197F 24
+#define BIT_MASK_BCNERR_CNT_OTHERS_8197F 0xff
+#define BIT_BCNERR_CNT_OTHERS_8197F(x) \
+ (((x) & BIT_MASK_BCNERR_CNT_OTHERS_8197F) \
+ << BIT_SHIFT_BCNERR_CNT_OTHERS_8197F)
+#define BITS_BCNERR_CNT_OTHERS_8197F \
+ (BIT_MASK_BCNERR_CNT_OTHERS_8197F << BIT_SHIFT_BCNERR_CNT_OTHERS_8197F)
+#define BIT_CLEAR_BCNERR_CNT_OTHERS_8197F(x) \
+ ((x) & (~BITS_BCNERR_CNT_OTHERS_8197F))
+#define BIT_GET_BCNERR_CNT_OTHERS_8197F(x) \
+ (((x) >> BIT_SHIFT_BCNERR_CNT_OTHERS_8197F) & \
+ BIT_MASK_BCNERR_CNT_OTHERS_8197F)
+#define BIT_SET_BCNERR_CNT_OTHERS_8197F(x, v) \
+ (BIT_CLEAR_BCNERR_CNT_OTHERS_8197F(x) | BIT_BCNERR_CNT_OTHERS_8197F(v))
+
+#define BIT_SHIFT_BCNERR_CNT_INVALID_8197F 16
+#define BIT_MASK_BCNERR_CNT_INVALID_8197F 0xff
+#define BIT_BCNERR_CNT_INVALID_8197F(x) \
+ (((x) & BIT_MASK_BCNERR_CNT_INVALID_8197F) \
+ << BIT_SHIFT_BCNERR_CNT_INVALID_8197F)
+#define BITS_BCNERR_CNT_INVALID_8197F \
+ (BIT_MASK_BCNERR_CNT_INVALID_8197F \
+ << BIT_SHIFT_BCNERR_CNT_INVALID_8197F)
+#define BIT_CLEAR_BCNERR_CNT_INVALID_8197F(x) \
+ ((x) & (~BITS_BCNERR_CNT_INVALID_8197F))
+#define BIT_GET_BCNERR_CNT_INVALID_8197F(x) \
+ (((x) >> BIT_SHIFT_BCNERR_CNT_INVALID_8197F) & \
+ BIT_MASK_BCNERR_CNT_INVALID_8197F)
+#define BIT_SET_BCNERR_CNT_INVALID_8197F(x, v) \
+ (BIT_CLEAR_BCNERR_CNT_INVALID_8197F(x) | \
+ BIT_BCNERR_CNT_INVALID_8197F(v))
+
+#define BIT_SHIFT_BCNERR_CNT_MAC_8197F 8
+#define BIT_MASK_BCNERR_CNT_MAC_8197F 0xff
+#define BIT_BCNERR_CNT_MAC_8197F(x) \
+ (((x) & BIT_MASK_BCNERR_CNT_MAC_8197F) \
+ << BIT_SHIFT_BCNERR_CNT_MAC_8197F)
+#define BITS_BCNERR_CNT_MAC_8197F \
+ (BIT_MASK_BCNERR_CNT_MAC_8197F << BIT_SHIFT_BCNERR_CNT_MAC_8197F)
+#define BIT_CLEAR_BCNERR_CNT_MAC_8197F(x) ((x) & (~BITS_BCNERR_CNT_MAC_8197F))
+#define BIT_GET_BCNERR_CNT_MAC_8197F(x) \
+ (((x) >> BIT_SHIFT_BCNERR_CNT_MAC_8197F) & \
+ BIT_MASK_BCNERR_CNT_MAC_8197F)
+#define BIT_SET_BCNERR_CNT_MAC_8197F(x, v) \
+ (BIT_CLEAR_BCNERR_CNT_MAC_8197F(x) | BIT_BCNERR_CNT_MAC_8197F(v))
+
+#define BIT_SHIFT_BCNERR_CNT_CCA_8197F 0
+#define BIT_MASK_BCNERR_CNT_CCA_8197F 0xff
+#define BIT_BCNERR_CNT_CCA_8197F(x) \
+ (((x) & BIT_MASK_BCNERR_CNT_CCA_8197F) \
+ << BIT_SHIFT_BCNERR_CNT_CCA_8197F)
+#define BITS_BCNERR_CNT_CCA_8197F \
+ (BIT_MASK_BCNERR_CNT_CCA_8197F << BIT_SHIFT_BCNERR_CNT_CCA_8197F)
+#define BIT_CLEAR_BCNERR_CNT_CCA_8197F(x) ((x) & (~BITS_BCNERR_CNT_CCA_8197F))
+#define BIT_GET_BCNERR_CNT_CCA_8197F(x) \
+ (((x) >> BIT_SHIFT_BCNERR_CNT_CCA_8197F) & \
+ BIT_MASK_BCNERR_CNT_CCA_8197F)
+#define BIT_SET_BCNERR_CNT_CCA_8197F(x, v) \
+ (BIT_CLEAR_BCNERR_CNT_CCA_8197F(x) | BIT_BCNERR_CNT_CCA_8197F(v))
+
+/* 2 REG_NOA_PARAM_8197F */
+
+#define BIT_SHIFT_NOA_COUNT_8197F (96 & CPU_OPT_WIDTH)
+#define BIT_MASK_NOA_COUNT_8197F 0xff
+#define BIT_NOA_COUNT_8197F(x) \
+ (((x) & BIT_MASK_NOA_COUNT_8197F) << BIT_SHIFT_NOA_COUNT_8197F)
+#define BITS_NOA_COUNT_8197F \
+ (BIT_MASK_NOA_COUNT_8197F << BIT_SHIFT_NOA_COUNT_8197F)
+#define BIT_CLEAR_NOA_COUNT_8197F(x) ((x) & (~BITS_NOA_COUNT_8197F))
+#define BIT_GET_NOA_COUNT_8197F(x) \
+ (((x) >> BIT_SHIFT_NOA_COUNT_8197F) & BIT_MASK_NOA_COUNT_8197F)
+#define BIT_SET_NOA_COUNT_8197F(x, v) \
+ (BIT_CLEAR_NOA_COUNT_8197F(x) | BIT_NOA_COUNT_8197F(v))
+
+#define BIT_SHIFT_NOA_START_TIME_8197F (64 & CPU_OPT_WIDTH)
+#define BIT_MASK_NOA_START_TIME_8197F 0xffffffffL
+#define BIT_NOA_START_TIME_8197F(x) \
+ (((x) & BIT_MASK_NOA_START_TIME_8197F) \
+ << BIT_SHIFT_NOA_START_TIME_8197F)
+#define BITS_NOA_START_TIME_8197F \
+ (BIT_MASK_NOA_START_TIME_8197F << BIT_SHIFT_NOA_START_TIME_8197F)
+#define BIT_CLEAR_NOA_START_TIME_8197F(x) ((x) & (~BITS_NOA_START_TIME_8197F))
+#define BIT_GET_NOA_START_TIME_8197F(x) \
+ (((x) >> BIT_SHIFT_NOA_START_TIME_8197F) & \
+ BIT_MASK_NOA_START_TIME_8197F)
+#define BIT_SET_NOA_START_TIME_8197F(x, v) \
+ (BIT_CLEAR_NOA_START_TIME_8197F(x) | BIT_NOA_START_TIME_8197F(v))
+
+#define BIT_SHIFT_NOA_INTERVAL_8197F (32 & CPU_OPT_WIDTH)
+#define BIT_MASK_NOA_INTERVAL_8197F 0xffffffffL
+#define BIT_NOA_INTERVAL_8197F(x) \
+ (((x) & BIT_MASK_NOA_INTERVAL_8197F) << BIT_SHIFT_NOA_INTERVAL_8197F)
+#define BITS_NOA_INTERVAL_8197F \
+ (BIT_MASK_NOA_INTERVAL_8197F << BIT_SHIFT_NOA_INTERVAL_8197F)
+#define BIT_CLEAR_NOA_INTERVAL_8197F(x) ((x) & (~BITS_NOA_INTERVAL_8197F))
+#define BIT_GET_NOA_INTERVAL_8197F(x) \
+ (((x) >> BIT_SHIFT_NOA_INTERVAL_8197F) & BIT_MASK_NOA_INTERVAL_8197F)
+#define BIT_SET_NOA_INTERVAL_8197F(x, v) \
+ (BIT_CLEAR_NOA_INTERVAL_8197F(x) | BIT_NOA_INTERVAL_8197F(v))
+
+#define BIT_SHIFT_NOA_DURATION_8197F 0
+#define BIT_MASK_NOA_DURATION_8197F 0xffffffffL
+#define BIT_NOA_DURATION_8197F(x) \
+ (((x) & BIT_MASK_NOA_DURATION_8197F) << BIT_SHIFT_NOA_DURATION_8197F)
+#define BITS_NOA_DURATION_8197F \
+ (BIT_MASK_NOA_DURATION_8197F << BIT_SHIFT_NOA_DURATION_8197F)
+#define BIT_CLEAR_NOA_DURATION_8197F(x) ((x) & (~BITS_NOA_DURATION_8197F))
+#define BIT_GET_NOA_DURATION_8197F(x) \
+ (((x) >> BIT_SHIFT_NOA_DURATION_8197F) & BIT_MASK_NOA_DURATION_8197F)
+#define BIT_SET_NOA_DURATION_8197F(x, v) \
+ (BIT_CLEAR_NOA_DURATION_8197F(x) | BIT_NOA_DURATION_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_P2P_RST_8197F */
+#define BIT_P2P2_PWR_RST1_8197F BIT(5)
+#define BIT_P2P2_PWR_RST0_8197F BIT(4)
+#define BIT_P2P1_PWR_RST1_8197F BIT(3)
+#define BIT_P2P1_PWR_RST0_8197F BIT(2)
+#define BIT_P2P_PWR_RST1_V1_8197F BIT(1)
+#define BIT_P2P_PWR_RST0_V1_8197F BIT(0)
+
+/* 2 REG_SCHEDULER_RST_8197F */
+#define BIT_SYNC_TSF_NOW_8197F BIT(2)
+#define BIT_SYNC_CLI_8197F BIT(1)
+#define BIT_SCHEDULER_RST_V1_8197F BIT(0)
+
+/* 2 REG_SCH_TXCMD_8197F */
+
+#define BIT_SHIFT_SCH_TXCMD_8197F 0
+#define BIT_MASK_SCH_TXCMD_8197F 0xffffffffL
+#define BIT_SCH_TXCMD_8197F(x) \
+ (((x) & BIT_MASK_SCH_TXCMD_8197F) << BIT_SHIFT_SCH_TXCMD_8197F)
+#define BITS_SCH_TXCMD_8197F \
+ (BIT_MASK_SCH_TXCMD_8197F << BIT_SHIFT_SCH_TXCMD_8197F)
+#define BIT_CLEAR_SCH_TXCMD_8197F(x) ((x) & (~BITS_SCH_TXCMD_8197F))
+#define BIT_GET_SCH_TXCMD_8197F(x) \
+ (((x) >> BIT_SHIFT_SCH_TXCMD_8197F) & BIT_MASK_SCH_TXCMD_8197F)
+#define BIT_SET_SCH_TXCMD_8197F(x, v) \
+ (BIT_CLEAR_SCH_TXCMD_8197F(x) | BIT_SCH_TXCMD_8197F(v))
+
+/* 2 REG_PAGE5_DUMMY_8197F */
+
+/* 2 REG_CPUMGQ_TX_TIMER_8197F */
+
+#define BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8197F 0
+#define BIT_MASK_CPUMGQ_TX_TIMER_V1_8197F 0xffffffffL
+#define BIT_CPUMGQ_TX_TIMER_V1_8197F(x) \
+ (((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8197F) \
+ << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8197F)
+#define BITS_CPUMGQ_TX_TIMER_V1_8197F \
+ (BIT_MASK_CPUMGQ_TX_TIMER_V1_8197F \
+ << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8197F)
+#define BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8197F(x) \
+ ((x) & (~BITS_CPUMGQ_TX_TIMER_V1_8197F))
+#define BIT_GET_CPUMGQ_TX_TIMER_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8197F) & \
+ BIT_MASK_CPUMGQ_TX_TIMER_V1_8197F)
+#define BIT_SET_CPUMGQ_TX_TIMER_V1_8197F(x, v) \
+ (BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8197F(x) | \
+ BIT_CPUMGQ_TX_TIMER_V1_8197F(v))
+
+/* 2 REG_PS_TIMER_A_8197F */
+
+#define BIT_SHIFT_PS_TIMER_A_V1_8197F 0
+#define BIT_MASK_PS_TIMER_A_V1_8197F 0xffffffffL
+#define BIT_PS_TIMER_A_V1_8197F(x) \
+ (((x) & BIT_MASK_PS_TIMER_A_V1_8197F) << BIT_SHIFT_PS_TIMER_A_V1_8197F)
+#define BITS_PS_TIMER_A_V1_8197F \
+ (BIT_MASK_PS_TIMER_A_V1_8197F << BIT_SHIFT_PS_TIMER_A_V1_8197F)
+#define BIT_CLEAR_PS_TIMER_A_V1_8197F(x) ((x) & (~BITS_PS_TIMER_A_V1_8197F))
+#define BIT_GET_PS_TIMER_A_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_A_V1_8197F) & BIT_MASK_PS_TIMER_A_V1_8197F)
+#define BIT_SET_PS_TIMER_A_V1_8197F(x, v) \
+ (BIT_CLEAR_PS_TIMER_A_V1_8197F(x) | BIT_PS_TIMER_A_V1_8197F(v))
+
+/* 2 REG_PS_TIMER_B_8197F */
+
+#define BIT_SHIFT_PS_TIMER_B_V1_8197F 0
+#define BIT_MASK_PS_TIMER_B_V1_8197F 0xffffffffL
+#define BIT_PS_TIMER_B_V1_8197F(x) \
+ (((x) & BIT_MASK_PS_TIMER_B_V1_8197F) << BIT_SHIFT_PS_TIMER_B_V1_8197F)
+#define BITS_PS_TIMER_B_V1_8197F \
+ (BIT_MASK_PS_TIMER_B_V1_8197F << BIT_SHIFT_PS_TIMER_B_V1_8197F)
+#define BIT_CLEAR_PS_TIMER_B_V1_8197F(x) ((x) & (~BITS_PS_TIMER_B_V1_8197F))
+#define BIT_GET_PS_TIMER_B_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_B_V1_8197F) & BIT_MASK_PS_TIMER_B_V1_8197F)
+#define BIT_SET_PS_TIMER_B_V1_8197F(x, v) \
+ (BIT_CLEAR_PS_TIMER_B_V1_8197F(x) | BIT_PS_TIMER_B_V1_8197F(v))
+
+/* 2 REG_PS_TIMER_C_8197F */
+
+#define BIT_SHIFT_PS_TIMER_C_V1_8197F 0
+#define BIT_MASK_PS_TIMER_C_V1_8197F 0xffffffffL
+#define BIT_PS_TIMER_C_V1_8197F(x) \
+ (((x) & BIT_MASK_PS_TIMER_C_V1_8197F) << BIT_SHIFT_PS_TIMER_C_V1_8197F)
+#define BITS_PS_TIMER_C_V1_8197F \
+ (BIT_MASK_PS_TIMER_C_V1_8197F << BIT_SHIFT_PS_TIMER_C_V1_8197F)
+#define BIT_CLEAR_PS_TIMER_C_V1_8197F(x) ((x) & (~BITS_PS_TIMER_C_V1_8197F))
+#define BIT_GET_PS_TIMER_C_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_C_V1_8197F) & BIT_MASK_PS_TIMER_C_V1_8197F)
+#define BIT_SET_PS_TIMER_C_V1_8197F(x, v) \
+ (BIT_CLEAR_PS_TIMER_C_V1_8197F(x) | BIT_PS_TIMER_C_V1_8197F(v))
+
+/* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8197F */
+#define BIT_CPUMGQ_TIMER_EN_8197F BIT(31)
+#define BIT_CPUMGQ_TX_EN_8197F BIT(28)
+
+#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8197F 24
+#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8197F 0x7
+#define BIT_CPUMGQ_TIMER_TSF_SEL_8197F(x) \
+ (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8197F) \
+ << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8197F)
+#define BITS_CPUMGQ_TIMER_TSF_SEL_8197F \
+ (BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8197F \
+ << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8197F)
+#define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8197F(x) \
+ ((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL_8197F))
+#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8197F) & \
+ BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8197F)
+#define BIT_SET_CPUMGQ_TIMER_TSF_SEL_8197F(x, v) \
+ (BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8197F(x) | \
+ BIT_CPUMGQ_TIMER_TSF_SEL_8197F(v))
+
+#define BIT_PS_TIMER_C_EN_8197F BIT(23)
+
+#define BIT_SHIFT_PS_TIMER_C_TSF_SEL_8197F 16
+#define BIT_MASK_PS_TIMER_C_TSF_SEL_8197F 0x7
+#define BIT_PS_TIMER_C_TSF_SEL_8197F(x) \
+ (((x) & BIT_MASK_PS_TIMER_C_TSF_SEL_8197F) \
+ << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8197F)
+#define BITS_PS_TIMER_C_TSF_SEL_8197F \
+ (BIT_MASK_PS_TIMER_C_TSF_SEL_8197F \
+ << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8197F)
+#define BIT_CLEAR_PS_TIMER_C_TSF_SEL_8197F(x) \
+ ((x) & (~BITS_PS_TIMER_C_TSF_SEL_8197F))
+#define BIT_GET_PS_TIMER_C_TSF_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL_8197F) & \
+ BIT_MASK_PS_TIMER_C_TSF_SEL_8197F)
+#define BIT_SET_PS_TIMER_C_TSF_SEL_8197F(x, v) \
+ (BIT_CLEAR_PS_TIMER_C_TSF_SEL_8197F(x) | \
+ BIT_PS_TIMER_C_TSF_SEL_8197F(v))
+
+#define BIT_PS_TIMER_B_EN_8197F BIT(15)
+
+#define BIT_SHIFT_PS_TIMER_B_TSF_SEL_8197F 8
+#define BIT_MASK_PS_TIMER_B_TSF_SEL_8197F 0x7
+#define BIT_PS_TIMER_B_TSF_SEL_8197F(x) \
+ (((x) & BIT_MASK_PS_TIMER_B_TSF_SEL_8197F) \
+ << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8197F)
+#define BITS_PS_TIMER_B_TSF_SEL_8197F \
+ (BIT_MASK_PS_TIMER_B_TSF_SEL_8197F \
+ << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8197F)
+#define BIT_CLEAR_PS_TIMER_B_TSF_SEL_8197F(x) \
+ ((x) & (~BITS_PS_TIMER_B_TSF_SEL_8197F))
+#define BIT_GET_PS_TIMER_B_TSF_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL_8197F) & \
+ BIT_MASK_PS_TIMER_B_TSF_SEL_8197F)
+#define BIT_SET_PS_TIMER_B_TSF_SEL_8197F(x, v) \
+ (BIT_CLEAR_PS_TIMER_B_TSF_SEL_8197F(x) | \
+ BIT_PS_TIMER_B_TSF_SEL_8197F(v))
+
+#define BIT_PS_TIMER_A_EN_8197F BIT(7)
+
+#define BIT_SHIFT_PS_TIMER_A_TSF_SEL_8197F 0
+#define BIT_MASK_PS_TIMER_A_TSF_SEL_8197F 0x7
+#define BIT_PS_TIMER_A_TSF_SEL_8197F(x) \
+ (((x) & BIT_MASK_PS_TIMER_A_TSF_SEL_8197F) \
+ << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8197F)
+#define BITS_PS_TIMER_A_TSF_SEL_8197F \
+ (BIT_MASK_PS_TIMER_A_TSF_SEL_8197F \
+ << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8197F)
+#define BIT_CLEAR_PS_TIMER_A_TSF_SEL_8197F(x) \
+ ((x) & (~BITS_PS_TIMER_A_TSF_SEL_8197F))
+#define BIT_GET_PS_TIMER_A_TSF_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL_8197F) & \
+ BIT_MASK_PS_TIMER_A_TSF_SEL_8197F)
+#define BIT_SET_PS_TIMER_A_TSF_SEL_8197F(x, v) \
+ (BIT_CLEAR_PS_TIMER_A_TSF_SEL_8197F(x) | \
+ BIT_PS_TIMER_A_TSF_SEL_8197F(v))
+
+/* 2 REG_CPUMGQ_TX_TIMER_EARLY_8197F */
+
+#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8197F 0
+#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8197F 0xff
+#define BIT_CPUMGQ_TX_TIMER_EARLY_8197F(x) \
+ (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8197F) \
+ << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8197F)
+#define BITS_CPUMGQ_TX_TIMER_EARLY_8197F \
+ (BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8197F \
+ << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8197F)
+#define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8197F(x) \
+ ((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY_8197F))
+#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_8197F(x) \
+ (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8197F) & \
+ BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8197F)
+#define BIT_SET_CPUMGQ_TX_TIMER_EARLY_8197F(x, v) \
+ (BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8197F(x) | \
+ BIT_CPUMGQ_TX_TIMER_EARLY_8197F(v))
+
+/* 2 REG_PS_TIMER_A_EARLY_8197F */
+
+#define BIT_SHIFT_PS_TIMER_A_EARLY_8197F 0
+#define BIT_MASK_PS_TIMER_A_EARLY_8197F 0xff
+#define BIT_PS_TIMER_A_EARLY_8197F(x) \
+ (((x) & BIT_MASK_PS_TIMER_A_EARLY_8197F) \
+ << BIT_SHIFT_PS_TIMER_A_EARLY_8197F)
+#define BITS_PS_TIMER_A_EARLY_8197F \
+ (BIT_MASK_PS_TIMER_A_EARLY_8197F << BIT_SHIFT_PS_TIMER_A_EARLY_8197F)
+#define BIT_CLEAR_PS_TIMER_A_EARLY_8197F(x) \
+ ((x) & (~BITS_PS_TIMER_A_EARLY_8197F))
+#define BIT_GET_PS_TIMER_A_EARLY_8197F(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_A_EARLY_8197F) & \
+ BIT_MASK_PS_TIMER_A_EARLY_8197F)
+#define BIT_SET_PS_TIMER_A_EARLY_8197F(x, v) \
+ (BIT_CLEAR_PS_TIMER_A_EARLY_8197F(x) | BIT_PS_TIMER_A_EARLY_8197F(v))
+
+/* 2 REG_PS_TIMER_B_EARLY_8197F */
+
+#define BIT_SHIFT_PS_TIMER_B_EARLY_8197F 0
+#define BIT_MASK_PS_TIMER_B_EARLY_8197F 0xff
+#define BIT_PS_TIMER_B_EARLY_8197F(x) \
+ (((x) & BIT_MASK_PS_TIMER_B_EARLY_8197F) \
+ << BIT_SHIFT_PS_TIMER_B_EARLY_8197F)
+#define BITS_PS_TIMER_B_EARLY_8197F \
+ (BIT_MASK_PS_TIMER_B_EARLY_8197F << BIT_SHIFT_PS_TIMER_B_EARLY_8197F)
+#define BIT_CLEAR_PS_TIMER_B_EARLY_8197F(x) \
+ ((x) & (~BITS_PS_TIMER_B_EARLY_8197F))
+#define BIT_GET_PS_TIMER_B_EARLY_8197F(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_B_EARLY_8197F) & \
+ BIT_MASK_PS_TIMER_B_EARLY_8197F)
+#define BIT_SET_PS_TIMER_B_EARLY_8197F(x, v) \
+ (BIT_CLEAR_PS_TIMER_B_EARLY_8197F(x) | BIT_PS_TIMER_B_EARLY_8197F(v))
+
+/* 2 REG_PS_TIMER_C_EARLY_8197F */
+
+#define BIT_SHIFT_PS_TIMER_C_EARLY_8197F 0
+#define BIT_MASK_PS_TIMER_C_EARLY_8197F 0xff
+#define BIT_PS_TIMER_C_EARLY_8197F(x) \
+ (((x) & BIT_MASK_PS_TIMER_C_EARLY_8197F) \
+ << BIT_SHIFT_PS_TIMER_C_EARLY_8197F)
+#define BITS_PS_TIMER_C_EARLY_8197F \
+ (BIT_MASK_PS_TIMER_C_EARLY_8197F << BIT_SHIFT_PS_TIMER_C_EARLY_8197F)
+#define BIT_CLEAR_PS_TIMER_C_EARLY_8197F(x) \
+ ((x) & (~BITS_PS_TIMER_C_EARLY_8197F))
+#define BIT_GET_PS_TIMER_C_EARLY_8197F(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_C_EARLY_8197F) & \
+ BIT_MASK_PS_TIMER_C_EARLY_8197F)
+#define BIT_SET_PS_TIMER_C_EARLY_8197F(x, v) \
+ (BIT_CLEAR_PS_TIMER_C_EARLY_8197F(x) | BIT_PS_TIMER_C_EARLY_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+#define BIT_STOP_CPUMGQ_8197F BIT(16)
+
+#define BIT_SHIFT_CPUMGQ_PARAMETER_8197F 0
+#define BIT_MASK_CPUMGQ_PARAMETER_8197F 0xffff
+#define BIT_CPUMGQ_PARAMETER_8197F(x) \
+ (((x) & BIT_MASK_CPUMGQ_PARAMETER_8197F) \
+ << BIT_SHIFT_CPUMGQ_PARAMETER_8197F)
+#define BITS_CPUMGQ_PARAMETER_8197F \
+ (BIT_MASK_CPUMGQ_PARAMETER_8197F << BIT_SHIFT_CPUMGQ_PARAMETER_8197F)
+#define BIT_CLEAR_CPUMGQ_PARAMETER_8197F(x) \
+ ((x) & (~BITS_CPUMGQ_PARAMETER_8197F))
+#define BIT_GET_CPUMGQ_PARAMETER_8197F(x) \
+ (((x) >> BIT_SHIFT_CPUMGQ_PARAMETER_8197F) & \
+ BIT_MASK_CPUMGQ_PARAMETER_8197F)
+#define BIT_SET_CPUMGQ_PARAMETER_8197F(x, v) \
+ (BIT_CLEAR_CPUMGQ_PARAMETER_8197F(x) | BIT_CPUMGQ_PARAMETER_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_BWOPMODE_8197F (BW OPERATION MODE REGISTER) */
+
+/* 2 REG_WMAC_FWPKT_CR_8197F */
+#define BIT_FWEN_8197F BIT(7)
+#define BIT_PHYSTS_PKT_CTRL_8197F BIT(6)
+#define BIT_APPHDR_MIDSRCH_FAIL_8197F BIT(4)
+#define BIT_FWPARSING_EN_8197F BIT(3)
+
+#define BIT_SHIFT_APPEND_MHDR_LEN_8197F 0
+#define BIT_MASK_APPEND_MHDR_LEN_8197F 0x7
+#define BIT_APPEND_MHDR_LEN_8197F(x) \
+ (((x) & BIT_MASK_APPEND_MHDR_LEN_8197F) \
+ << BIT_SHIFT_APPEND_MHDR_LEN_8197F)
+#define BITS_APPEND_MHDR_LEN_8197F \
+ (BIT_MASK_APPEND_MHDR_LEN_8197F << BIT_SHIFT_APPEND_MHDR_LEN_8197F)
+#define BIT_CLEAR_APPEND_MHDR_LEN_8197F(x) ((x) & (~BITS_APPEND_MHDR_LEN_8197F))
+#define BIT_GET_APPEND_MHDR_LEN_8197F(x) \
+ (((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8197F) & \
+ BIT_MASK_APPEND_MHDR_LEN_8197F)
+#define BIT_SET_APPEND_MHDR_LEN_8197F(x, v) \
+ (BIT_CLEAR_APPEND_MHDR_LEN_8197F(x) | BIT_APPEND_MHDR_LEN_8197F(v))
+
+/* 2 REG_WMAC_CR_8197F (WMAC CR AND APSD CONTROL REGISTER) */
+#define BIT_APSDOFF_8197F BIT(6)
+#define BIT_IC_MACPHY_M_8197F BIT(0)
+
+/* 2 REG_TCR_8197F (TRANSMISSION CONFIGURATION REGISTER) */
+#define BIT_WMAC_EN_RTS_ADDR_8197F BIT(31)
+#define BIT_WMAC_DISABLE_CCK_8197F BIT(30)
+#define BIT_WMAC_RAW_LEN_8197F BIT(29)
+#define BIT_WMAC_NOTX_IN_RXNDP_8197F BIT(28)
+#define BIT_WMAC_EN_EOF_8197F BIT(27)
+#define BIT_WMAC_BF_SEL_8197F BIT(26)
+#define BIT_WMAC_ANTMODE_SEL_8197F BIT(25)
+#define BIT_WMAC_TCRPWRMGT_HWCTL_8197F BIT(24)
+#define BIT_WMAC_SMOOTH_VAL_8197F BIT(23)
+#define BIT_UNDERFLOWEN_CMPLEN_SEL_8197F BIT(21)
+#define BIT_FETCH_MPDU_AFTER_WSEC_RDY_8197F BIT(20)
+#define BIT_WMAC_TCR_EN_20MST_8197F BIT(19)
+#define BIT_WMAC_DIS_SIGTA_8197F BIT(18)
+#define BIT_WMAC_DIS_A2B0_8197F BIT(17)
+#define BIT_WMAC_MSK_SIGBCRC_8197F BIT(16)
+#define BIT_WMAC_TCR_ERRSTEN_3_8197F BIT(15)
+#define BIT_WMAC_TCR_ERRSTEN_2_8197F BIT(14)
+#define BIT_WMAC_TCR_ERRSTEN_1_8197F BIT(13)
+#define BIT_WMAC_TCR_ERRSTEN_0_8197F BIT(12)
+#define BIT_WMAC_TCR_TXSK_PERPKT_8197F BIT(11)
+#define BIT_ICV_8197F BIT(10)
+#define BIT_CFEND_FORMAT_8197F BIT(9)
+#define BIT_CRC_8197F BIT(8)
+#define BIT_PWRBIT_OW_EN_8197F BIT(7)
+#define BIT_PWR_ST_8197F BIT(6)
+#define BIT_WMAC_TCR_UPD_TIMIE_8197F BIT(5)
+#define BIT_WMAC_TCR_UPD_HGQMD_8197F BIT(4)
+#define BIT_VHTSIGA1_TXPS_8197F BIT(3)
+#define BIT_PAD_SEL_8197F BIT(2)
+#define BIT_DIS_GCLK_8197F BIT(1)
+
+/* 2 REG_RCR_8197F (RECEIVE CONFIGURATION REGISTER) */
+#define BIT_APP_FCS_8197F BIT(31)
+#define BIT_APP_MIC_8197F BIT(30)
+#define BIT_APP_ICV_8197F BIT(29)
+#define BIT_APP_PHYSTS_8197F BIT(28)
+#define BIT_APP_BASSN_8197F BIT(27)
+#define BIT_VHT_DACK_8197F BIT(26)
+#define BIT_TCPOFLD_EN_8197F BIT(25)
+#define BIT_ENMBID_8197F BIT(24)
+#define BIT_LSIGEN_8197F BIT(23)
+#define BIT_MFBEN_8197F BIT(22)
+#define BIT_DISCHKPPDLLEN_8197F BIT(21)
+#define BIT_PKTCTL_DLEN_8197F BIT(20)
+#define BIT_TIM_PARSER_EN_8197F BIT(18)
+#define BIT_BC_MD_EN_8197F BIT(17)
+#define BIT_UC_MD_EN_8197F BIT(16)
+#define BIT_RXSK_PERPKT_8197F BIT(15)
+#define BIT_HTC_LOC_CTRL_8197F BIT(14)
+#define BIT_TA_BCN_8197F BIT(11)
+#define BIT_DISDECMYPKT_8197F BIT(10)
+#define BIT_AICV_8197F BIT(9)
+#define BIT_ACRC32_8197F BIT(8)
+#define BIT_CBSSID_BCN_8197F BIT(7)
+#define BIT_CBSSID_DATA_8197F BIT(6)
+#define BIT_APWRMGT_8197F BIT(5)
+#define BIT_ADD3_8197F BIT(4)
+#define BIT_AB_8197F BIT(3)
+#define BIT_AM_8197F BIT(2)
+#define BIT_APM_8197F BIT(1)
+#define BIT_AAP_8197F BIT(0)
+
+/* 2 REG_RX_DRVINFO_SZ_8197F (RX DRIVER INFO SIZE REGISTER) */
+#define BIT_APP_PHYSTS_PER_SUBMPDU_8197F BIT(7)
+#define BIT_APP_MH_SHIFT_VAL_8197F BIT(6)
+#define BIT_WMAC_ENSHIFT_8197F BIT(5)
+
+#define BIT_SHIFT_DRVINFO_SZ_V1_8197F 0
+#define BIT_MASK_DRVINFO_SZ_V1_8197F 0xf
+#define BIT_DRVINFO_SZ_V1_8197F(x) \
+ (((x) & BIT_MASK_DRVINFO_SZ_V1_8197F) << BIT_SHIFT_DRVINFO_SZ_V1_8197F)
+#define BITS_DRVINFO_SZ_V1_8197F \
+ (BIT_MASK_DRVINFO_SZ_V1_8197F << BIT_SHIFT_DRVINFO_SZ_V1_8197F)
+#define BIT_CLEAR_DRVINFO_SZ_V1_8197F(x) ((x) & (~BITS_DRVINFO_SZ_V1_8197F))
+#define BIT_GET_DRVINFO_SZ_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8197F) & BIT_MASK_DRVINFO_SZ_V1_8197F)
+#define BIT_SET_DRVINFO_SZ_V1_8197F(x, v) \
+ (BIT_CLEAR_DRVINFO_SZ_V1_8197F(x) | BIT_DRVINFO_SZ_V1_8197F(v))
+
+/* 2 REG_RX_DLK_TIME_8197F (RX DEADLOCK TIME REGISTER) */
+
+#define BIT_SHIFT_RX_DLK_TIME_8197F 0
+#define BIT_MASK_RX_DLK_TIME_8197F 0xff
+#define BIT_RX_DLK_TIME_8197F(x) \
+ (((x) & BIT_MASK_RX_DLK_TIME_8197F) << BIT_SHIFT_RX_DLK_TIME_8197F)
+#define BITS_RX_DLK_TIME_8197F \
+ (BIT_MASK_RX_DLK_TIME_8197F << BIT_SHIFT_RX_DLK_TIME_8197F)
+#define BIT_CLEAR_RX_DLK_TIME_8197F(x) ((x) & (~BITS_RX_DLK_TIME_8197F))
+#define BIT_GET_RX_DLK_TIME_8197F(x) \
+ (((x) >> BIT_SHIFT_RX_DLK_TIME_8197F) & BIT_MASK_RX_DLK_TIME_8197F)
+#define BIT_SET_RX_DLK_TIME_8197F(x, v) \
+ (BIT_CLEAR_RX_DLK_TIME_8197F(x) | BIT_RX_DLK_TIME_8197F(v))
+
+/* 2 REG_RX_PKT_LIMIT_8197F (RX PACKET LENGTH LIMIT REGISTER) */
+
+#define BIT_SHIFT_RXPKTLMT_8197F 0
+#define BIT_MASK_RXPKTLMT_8197F 0x3f
+#define BIT_RXPKTLMT_8197F(x) \
+ (((x) & BIT_MASK_RXPKTLMT_8197F) << BIT_SHIFT_RXPKTLMT_8197F)
+#define BITS_RXPKTLMT_8197F \
+ (BIT_MASK_RXPKTLMT_8197F << BIT_SHIFT_RXPKTLMT_8197F)
+#define BIT_CLEAR_RXPKTLMT_8197F(x) ((x) & (~BITS_RXPKTLMT_8197F))
+#define BIT_GET_RXPKTLMT_8197F(x) \
+ (((x) >> BIT_SHIFT_RXPKTLMT_8197F) & BIT_MASK_RXPKTLMT_8197F)
+#define BIT_SET_RXPKTLMT_8197F(x, v) \
+ (BIT_CLEAR_RXPKTLMT_8197F(x) | BIT_RXPKTLMT_8197F(v))
+
+/* 2 REG_MACID_8197F (MAC ID REGISTER) */
+
+#define BIT_SHIFT_MACID_8197F 0
+#define BIT_MASK_MACID_8197F 0xffffffffffffL
+#define BIT_MACID_8197F(x) \
+ (((x) & BIT_MASK_MACID_8197F) << BIT_SHIFT_MACID_8197F)
+#define BITS_MACID_8197F (BIT_MASK_MACID_8197F << BIT_SHIFT_MACID_8197F)
+#define BIT_CLEAR_MACID_8197F(x) ((x) & (~BITS_MACID_8197F))
+#define BIT_GET_MACID_8197F(x) \
+ (((x) >> BIT_SHIFT_MACID_8197F) & BIT_MASK_MACID_8197F)
+#define BIT_SET_MACID_8197F(x, v) \
+ (BIT_CLEAR_MACID_8197F(x) | BIT_MACID_8197F(v))
+
+/* 2 REG_BSSID_8197F (BSSID REGISTER) */
+
+#define BIT_SHIFT_BSSID_8197F 0
+#define BIT_MASK_BSSID_8197F 0xffffffffffffL
+#define BIT_BSSID_8197F(x) \
+ (((x) & BIT_MASK_BSSID_8197F) << BIT_SHIFT_BSSID_8197F)
+#define BITS_BSSID_8197F (BIT_MASK_BSSID_8197F << BIT_SHIFT_BSSID_8197F)
+#define BIT_CLEAR_BSSID_8197F(x) ((x) & (~BITS_BSSID_8197F))
+#define BIT_GET_BSSID_8197F(x) \
+ (((x) >> BIT_SHIFT_BSSID_8197F) & BIT_MASK_BSSID_8197F)
+#define BIT_SET_BSSID_8197F(x, v) \
+ (BIT_CLEAR_BSSID_8197F(x) | BIT_BSSID_8197F(v))
+
+/* 2 REG_MAR_8197F (MULTICAST ADDRESS REGISTER) */
+
+#define BIT_SHIFT_MAR_8197F 0
+#define BIT_MASK_MAR_8197F 0xffffffffffffffffL
+#define BIT_MAR_8197F(x) (((x) & BIT_MASK_MAR_8197F) << BIT_SHIFT_MAR_8197F)
+#define BITS_MAR_8197F (BIT_MASK_MAR_8197F << BIT_SHIFT_MAR_8197F)
+#define BIT_CLEAR_MAR_8197F(x) ((x) & (~BITS_MAR_8197F))
+#define BIT_GET_MAR_8197F(x) (((x) >> BIT_SHIFT_MAR_8197F) & BIT_MASK_MAR_8197F)
+#define BIT_SET_MAR_8197F(x, v) (BIT_CLEAR_MAR_8197F(x) | BIT_MAR_8197F(v))
+
+/* 2 REG_MBIDCAMCFG_1_8197F (MBSSID CAM CONFIGURATION REGISTER) */
+
+#define BIT_SHIFT_MBIDCAM_RWDATA_L_8197F 0
+#define BIT_MASK_MBIDCAM_RWDATA_L_8197F 0xffffffffL
+#define BIT_MBIDCAM_RWDATA_L_8197F(x) \
+ (((x) & BIT_MASK_MBIDCAM_RWDATA_L_8197F) \
+ << BIT_SHIFT_MBIDCAM_RWDATA_L_8197F)
+#define BITS_MBIDCAM_RWDATA_L_8197F \
+ (BIT_MASK_MBIDCAM_RWDATA_L_8197F << BIT_SHIFT_MBIDCAM_RWDATA_L_8197F)
+#define BIT_CLEAR_MBIDCAM_RWDATA_L_8197F(x) \
+ ((x) & (~BITS_MBIDCAM_RWDATA_L_8197F))
+#define BIT_GET_MBIDCAM_RWDATA_L_8197F(x) \
+ (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L_8197F) & \
+ BIT_MASK_MBIDCAM_RWDATA_L_8197F)
+#define BIT_SET_MBIDCAM_RWDATA_L_8197F(x, v) \
+ (BIT_CLEAR_MBIDCAM_RWDATA_L_8197F(x) | BIT_MBIDCAM_RWDATA_L_8197F(v))
+
+/* 2 REG_MBIDCAMCFG_2_8197F (MBSSID CAM CONFIGURATION REGISTER) */
+#define BIT_MBIDCAM_POLL_8197F BIT(31)
+#define BIT_MBIDCAM_WT_EN_8197F BIT(30)
+
+#define BIT_SHIFT_MBIDCAM_ADDR_V1_8197F 24
+#define BIT_MASK_MBIDCAM_ADDR_V1_8197F 0x3f
+#define BIT_MBIDCAM_ADDR_V1_8197F(x) \
+ (((x) & BIT_MASK_MBIDCAM_ADDR_V1_8197F) \
+ << BIT_SHIFT_MBIDCAM_ADDR_V1_8197F)
+#define BITS_MBIDCAM_ADDR_V1_8197F \
+ (BIT_MASK_MBIDCAM_ADDR_V1_8197F << BIT_SHIFT_MBIDCAM_ADDR_V1_8197F)
+#define BIT_CLEAR_MBIDCAM_ADDR_V1_8197F(x) ((x) & (~BITS_MBIDCAM_ADDR_V1_8197F))
+#define BIT_GET_MBIDCAM_ADDR_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_MBIDCAM_ADDR_V1_8197F) & \
+ BIT_MASK_MBIDCAM_ADDR_V1_8197F)
+#define BIT_SET_MBIDCAM_ADDR_V1_8197F(x, v) \
+ (BIT_CLEAR_MBIDCAM_ADDR_V1_8197F(x) | BIT_MBIDCAM_ADDR_V1_8197F(v))
+
+#define BIT_MBIDCAM_VALID_8197F BIT(23)
+#define BIT_LSIC_TXOP_EN_8197F BIT(17)
+#define BIT_REPEAT_MODE_EN_8197F BIT(16)
+
+#define BIT_SHIFT_MBIDCAM_RWDATA_H_8197F 0
+#define BIT_MASK_MBIDCAM_RWDATA_H_8197F 0xffff
+#define BIT_MBIDCAM_RWDATA_H_8197F(x) \
+ (((x) & BIT_MASK_MBIDCAM_RWDATA_H_8197F) \
+ << BIT_SHIFT_MBIDCAM_RWDATA_H_8197F)
+#define BITS_MBIDCAM_RWDATA_H_8197F \
+ (BIT_MASK_MBIDCAM_RWDATA_H_8197F << BIT_SHIFT_MBIDCAM_RWDATA_H_8197F)
+#define BIT_CLEAR_MBIDCAM_RWDATA_H_8197F(x) \
+ ((x) & (~BITS_MBIDCAM_RWDATA_H_8197F))
+#define BIT_GET_MBIDCAM_RWDATA_H_8197F(x) \
+ (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H_8197F) & \
+ BIT_MASK_MBIDCAM_RWDATA_H_8197F)
+#define BIT_SET_MBIDCAM_RWDATA_H_8197F(x, v) \
+ (BIT_CLEAR_MBIDCAM_RWDATA_H_8197F(x) | BIT_MBIDCAM_RWDATA_H_8197F(v))
+
+/* 2 REG_ZLD_NUM_8197F */
+
+#define BIT_SHIFT_ZLD_NUM_8197F 0
+#define BIT_MASK_ZLD_NUM_8197F 0xff
+#define BIT_ZLD_NUM_8197F(x) \
+ (((x) & BIT_MASK_ZLD_NUM_8197F) << BIT_SHIFT_ZLD_NUM_8197F)
+#define BITS_ZLD_NUM_8197F (BIT_MASK_ZLD_NUM_8197F << BIT_SHIFT_ZLD_NUM_8197F)
+#define BIT_CLEAR_ZLD_NUM_8197F(x) ((x) & (~BITS_ZLD_NUM_8197F))
+#define BIT_GET_ZLD_NUM_8197F(x) \
+ (((x) >> BIT_SHIFT_ZLD_NUM_8197F) & BIT_MASK_ZLD_NUM_8197F)
+#define BIT_SET_ZLD_NUM_8197F(x, v) \
+ (BIT_CLEAR_ZLD_NUM_8197F(x) | BIT_ZLD_NUM_8197F(v))
+
+/* 2 REG_UDF_THSD_8197F */
+
+#define BIT_SHIFT_UDF_THSD_8197F 0
+#define BIT_MASK_UDF_THSD_8197F 0xff
+#define BIT_UDF_THSD_8197F(x) \
+ (((x) & BIT_MASK_UDF_THSD_8197F) << BIT_SHIFT_UDF_THSD_8197F)
+#define BITS_UDF_THSD_8197F \
+ (BIT_MASK_UDF_THSD_8197F << BIT_SHIFT_UDF_THSD_8197F)
+#define BIT_CLEAR_UDF_THSD_8197F(x) ((x) & (~BITS_UDF_THSD_8197F))
+#define BIT_GET_UDF_THSD_8197F(x) \
+ (((x) >> BIT_SHIFT_UDF_THSD_8197F) & BIT_MASK_UDF_THSD_8197F)
+#define BIT_SET_UDF_THSD_8197F(x, v) \
+ (BIT_CLEAR_UDF_THSD_8197F(x) | BIT_UDF_THSD_8197F(v))
+
+/* 2 REG_WMAC_TCR_TSFT_OFS_8197F */
+
+#define BIT_SHIFT_WMAC_TCR_TSFT_OFS_8197F 0
+#define BIT_MASK_WMAC_TCR_TSFT_OFS_8197F 0xffff
+#define BIT_WMAC_TCR_TSFT_OFS_8197F(x) \
+ (((x) & BIT_MASK_WMAC_TCR_TSFT_OFS_8197F) \
+ << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8197F)
+#define BITS_WMAC_TCR_TSFT_OFS_8197F \
+ (BIT_MASK_WMAC_TCR_TSFT_OFS_8197F << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8197F)
+#define BIT_CLEAR_WMAC_TCR_TSFT_OFS_8197F(x) \
+ ((x) & (~BITS_WMAC_TCR_TSFT_OFS_8197F))
+#define BIT_GET_WMAC_TCR_TSFT_OFS_8197F(x) \
+ (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8197F) & \
+ BIT_MASK_WMAC_TCR_TSFT_OFS_8197F)
+#define BIT_SET_WMAC_TCR_TSFT_OFS_8197F(x, v) \
+ (BIT_CLEAR_WMAC_TCR_TSFT_OFS_8197F(x) | BIT_WMAC_TCR_TSFT_OFS_8197F(v))
+
+/* 2 REG_MCU_TEST_2_V1_8197F */
+
+#define BIT_SHIFT_MCU_RSVD_2_V1_8197F 0
+#define BIT_MASK_MCU_RSVD_2_V1_8197F 0xffff
+#define BIT_MCU_RSVD_2_V1_8197F(x) \
+ (((x) & BIT_MASK_MCU_RSVD_2_V1_8197F) << BIT_SHIFT_MCU_RSVD_2_V1_8197F)
+#define BITS_MCU_RSVD_2_V1_8197F \
+ (BIT_MASK_MCU_RSVD_2_V1_8197F << BIT_SHIFT_MCU_RSVD_2_V1_8197F)
+#define BIT_CLEAR_MCU_RSVD_2_V1_8197F(x) ((x) & (~BITS_MCU_RSVD_2_V1_8197F))
+#define BIT_GET_MCU_RSVD_2_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_MCU_RSVD_2_V1_8197F) & BIT_MASK_MCU_RSVD_2_V1_8197F)
+#define BIT_SET_MCU_RSVD_2_V1_8197F(x, v) \
+ (BIT_CLEAR_MCU_RSVD_2_V1_8197F(x) | BIT_MCU_RSVD_2_V1_8197F(v))
+
+/* 2 REG_WMAC_TXTIMEOUT_8197F */
+
+#define BIT_SHIFT_WMAC_TXTIMEOUT_8197F 0
+#define BIT_MASK_WMAC_TXTIMEOUT_8197F 0xff
+#define BIT_WMAC_TXTIMEOUT_8197F(x) \
+ (((x) & BIT_MASK_WMAC_TXTIMEOUT_8197F) \
+ << BIT_SHIFT_WMAC_TXTIMEOUT_8197F)
+#define BITS_WMAC_TXTIMEOUT_8197F \
+ (BIT_MASK_WMAC_TXTIMEOUT_8197F << BIT_SHIFT_WMAC_TXTIMEOUT_8197F)
+#define BIT_CLEAR_WMAC_TXTIMEOUT_8197F(x) ((x) & (~BITS_WMAC_TXTIMEOUT_8197F))
+#define BIT_GET_WMAC_TXTIMEOUT_8197F(x) \
+ (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8197F) & \
+ BIT_MASK_WMAC_TXTIMEOUT_8197F)
+#define BIT_SET_WMAC_TXTIMEOUT_8197F(x, v) \
+ (BIT_CLEAR_WMAC_TXTIMEOUT_8197F(x) | BIT_WMAC_TXTIMEOUT_8197F(v))
+
+/* 2 REG_STMP_THSD_8197F */
+
+#define BIT_SHIFT_STMP_THSD_8197F 0
+#define BIT_MASK_STMP_THSD_8197F 0xff
+#define BIT_STMP_THSD_8197F(x) \
+ (((x) & BIT_MASK_STMP_THSD_8197F) << BIT_SHIFT_STMP_THSD_8197F)
+#define BITS_STMP_THSD_8197F \
+ (BIT_MASK_STMP_THSD_8197F << BIT_SHIFT_STMP_THSD_8197F)
+#define BIT_CLEAR_STMP_THSD_8197F(x) ((x) & (~BITS_STMP_THSD_8197F))
+#define BIT_GET_STMP_THSD_8197F(x) \
+ (((x) >> BIT_SHIFT_STMP_THSD_8197F) & BIT_MASK_STMP_THSD_8197F)
+#define BIT_SET_STMP_THSD_8197F(x, v) \
+ (BIT_CLEAR_STMP_THSD_8197F(x) | BIT_STMP_THSD_8197F(v))
+
+/* 2 REG_MAC_SPEC_SIFS_8197F (SPECIFICATION SIFS REGISTER) */
+
+#define BIT_SHIFT_SPEC_SIFS_OFDM_8197F 8
+#define BIT_MASK_SPEC_SIFS_OFDM_8197F 0xff
+#define BIT_SPEC_SIFS_OFDM_8197F(x) \
+ (((x) & BIT_MASK_SPEC_SIFS_OFDM_8197F) \
+ << BIT_SHIFT_SPEC_SIFS_OFDM_8197F)
+#define BITS_SPEC_SIFS_OFDM_8197F \
+ (BIT_MASK_SPEC_SIFS_OFDM_8197F << BIT_SHIFT_SPEC_SIFS_OFDM_8197F)
+#define BIT_CLEAR_SPEC_SIFS_OFDM_8197F(x) ((x) & (~BITS_SPEC_SIFS_OFDM_8197F))
+#define BIT_GET_SPEC_SIFS_OFDM_8197F(x) \
+ (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8197F) & \
+ BIT_MASK_SPEC_SIFS_OFDM_8197F)
+#define BIT_SET_SPEC_SIFS_OFDM_8197F(x, v) \
+ (BIT_CLEAR_SPEC_SIFS_OFDM_8197F(x) | BIT_SPEC_SIFS_OFDM_8197F(v))
+
+#define BIT_SHIFT_SPEC_SIFS_CCK_8197F 0
+#define BIT_MASK_SPEC_SIFS_CCK_8197F 0xff
+#define BIT_SPEC_SIFS_CCK_8197F(x) \
+ (((x) & BIT_MASK_SPEC_SIFS_CCK_8197F) << BIT_SHIFT_SPEC_SIFS_CCK_8197F)
+#define BITS_SPEC_SIFS_CCK_8197F \
+ (BIT_MASK_SPEC_SIFS_CCK_8197F << BIT_SHIFT_SPEC_SIFS_CCK_8197F)
+#define BIT_CLEAR_SPEC_SIFS_CCK_8197F(x) ((x) & (~BITS_SPEC_SIFS_CCK_8197F))
+#define BIT_GET_SPEC_SIFS_CCK_8197F(x) \
+ (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8197F) & BIT_MASK_SPEC_SIFS_CCK_8197F)
+#define BIT_SET_SPEC_SIFS_CCK_8197F(x, v) \
+ (BIT_CLEAR_SPEC_SIFS_CCK_8197F(x) | BIT_SPEC_SIFS_CCK_8197F(v))
+
+/* 2 REG_USTIME_EDCA_8197F (US TIME TUNING FOR EDCA REGISTER) */
+
+#define BIT_SHIFT_USTIME_EDCA_8197F 0
+#define BIT_MASK_USTIME_EDCA_8197F 0xff
+#define BIT_USTIME_EDCA_8197F(x) \
+ (((x) & BIT_MASK_USTIME_EDCA_8197F) << BIT_SHIFT_USTIME_EDCA_8197F)
+#define BITS_USTIME_EDCA_8197F \
+ (BIT_MASK_USTIME_EDCA_8197F << BIT_SHIFT_USTIME_EDCA_8197F)
+#define BIT_CLEAR_USTIME_EDCA_8197F(x) ((x) & (~BITS_USTIME_EDCA_8197F))
+#define BIT_GET_USTIME_EDCA_8197F(x) \
+ (((x) >> BIT_SHIFT_USTIME_EDCA_8197F) & BIT_MASK_USTIME_EDCA_8197F)
+#define BIT_SET_USTIME_EDCA_8197F(x, v) \
+ (BIT_CLEAR_USTIME_EDCA_8197F(x) | BIT_USTIME_EDCA_8197F(v))
+
+/* 2 REG_RESP_SIFS_OFDM_8197F (RESPONSE SIFS FOR OFDM REGISTER) */
+
+#define BIT_SHIFT_SIFS_R2T_OFDM_8197F 8
+#define BIT_MASK_SIFS_R2T_OFDM_8197F 0xff
+#define BIT_SIFS_R2T_OFDM_8197F(x) \
+ (((x) & BIT_MASK_SIFS_R2T_OFDM_8197F) << BIT_SHIFT_SIFS_R2T_OFDM_8197F)
+#define BITS_SIFS_R2T_OFDM_8197F \
+ (BIT_MASK_SIFS_R2T_OFDM_8197F << BIT_SHIFT_SIFS_R2T_OFDM_8197F)
+#define BIT_CLEAR_SIFS_R2T_OFDM_8197F(x) ((x) & (~BITS_SIFS_R2T_OFDM_8197F))
+#define BIT_GET_SIFS_R2T_OFDM_8197F(x) \
+ (((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8197F) & BIT_MASK_SIFS_R2T_OFDM_8197F)
+#define BIT_SET_SIFS_R2T_OFDM_8197F(x, v) \
+ (BIT_CLEAR_SIFS_R2T_OFDM_8197F(x) | BIT_SIFS_R2T_OFDM_8197F(v))
+
+#define BIT_SHIFT_SIFS_T2T_OFDM_8197F 0
+#define BIT_MASK_SIFS_T2T_OFDM_8197F 0xff
+#define BIT_SIFS_T2T_OFDM_8197F(x) \
+ (((x) & BIT_MASK_SIFS_T2T_OFDM_8197F) << BIT_SHIFT_SIFS_T2T_OFDM_8197F)
+#define BITS_SIFS_T2T_OFDM_8197F \
+ (BIT_MASK_SIFS_T2T_OFDM_8197F << BIT_SHIFT_SIFS_T2T_OFDM_8197F)
+#define BIT_CLEAR_SIFS_T2T_OFDM_8197F(x) ((x) & (~BITS_SIFS_T2T_OFDM_8197F))
+#define BIT_GET_SIFS_T2T_OFDM_8197F(x) \
+ (((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8197F) & BIT_MASK_SIFS_T2T_OFDM_8197F)
+#define BIT_SET_SIFS_T2T_OFDM_8197F(x, v) \
+ (BIT_CLEAR_SIFS_T2T_OFDM_8197F(x) | BIT_SIFS_T2T_OFDM_8197F(v))
+
+/* 2 REG_RESP_SIFS_CCK_8197F (RESPONSE SIFS FOR CCK REGISTER) */
+
+#define BIT_SHIFT_SIFS_R2T_CCK_8197F 8
+#define BIT_MASK_SIFS_R2T_CCK_8197F 0xff
+#define BIT_SIFS_R2T_CCK_8197F(x) \
+ (((x) & BIT_MASK_SIFS_R2T_CCK_8197F) << BIT_SHIFT_SIFS_R2T_CCK_8197F)
+#define BITS_SIFS_R2T_CCK_8197F \
+ (BIT_MASK_SIFS_R2T_CCK_8197F << BIT_SHIFT_SIFS_R2T_CCK_8197F)
+#define BIT_CLEAR_SIFS_R2T_CCK_8197F(x) ((x) & (~BITS_SIFS_R2T_CCK_8197F))
+#define BIT_GET_SIFS_R2T_CCK_8197F(x) \
+ (((x) >> BIT_SHIFT_SIFS_R2T_CCK_8197F) & BIT_MASK_SIFS_R2T_CCK_8197F)
+#define BIT_SET_SIFS_R2T_CCK_8197F(x, v) \
+ (BIT_CLEAR_SIFS_R2T_CCK_8197F(x) | BIT_SIFS_R2T_CCK_8197F(v))
+
+#define BIT_SHIFT_SIFS_T2T_CCK_8197F 0
+#define BIT_MASK_SIFS_T2T_CCK_8197F 0xff
+#define BIT_SIFS_T2T_CCK_8197F(x) \
+ (((x) & BIT_MASK_SIFS_T2T_CCK_8197F) << BIT_SHIFT_SIFS_T2T_CCK_8197F)
+#define BITS_SIFS_T2T_CCK_8197F \
+ (BIT_MASK_SIFS_T2T_CCK_8197F << BIT_SHIFT_SIFS_T2T_CCK_8197F)
+#define BIT_CLEAR_SIFS_T2T_CCK_8197F(x) ((x) & (~BITS_SIFS_T2T_CCK_8197F))
+#define BIT_GET_SIFS_T2T_CCK_8197F(x) \
+ (((x) >> BIT_SHIFT_SIFS_T2T_CCK_8197F) & BIT_MASK_SIFS_T2T_CCK_8197F)
+#define BIT_SET_SIFS_T2T_CCK_8197F(x, v) \
+ (BIT_CLEAR_SIFS_T2T_CCK_8197F(x) | BIT_SIFS_T2T_CCK_8197F(v))
+
+/* 2 REG_EIFS_8197F (EIFS REGISTER) */
+
+#define BIT_SHIFT_EIFS_8197F 0
+#define BIT_MASK_EIFS_8197F 0xffff
+#define BIT_EIFS_8197F(x) (((x) & BIT_MASK_EIFS_8197F) << BIT_SHIFT_EIFS_8197F)
+#define BITS_EIFS_8197F (BIT_MASK_EIFS_8197F << BIT_SHIFT_EIFS_8197F)
+#define BIT_CLEAR_EIFS_8197F(x) ((x) & (~BITS_EIFS_8197F))
+#define BIT_GET_EIFS_8197F(x) \
+ (((x) >> BIT_SHIFT_EIFS_8197F) & BIT_MASK_EIFS_8197F)
+#define BIT_SET_EIFS_8197F(x, v) (BIT_CLEAR_EIFS_8197F(x) | BIT_EIFS_8197F(v))
+
+/* 2 REG_CTS2TO_8197F (CTS2 TIMEOUT REGISTER) */
+
+#define BIT_SHIFT_CTS2TO_8197F 0
+#define BIT_MASK_CTS2TO_8197F 0xff
+#define BIT_CTS2TO_8197F(x) \
+ (((x) & BIT_MASK_CTS2TO_8197F) << BIT_SHIFT_CTS2TO_8197F)
+#define BITS_CTS2TO_8197F (BIT_MASK_CTS2TO_8197F << BIT_SHIFT_CTS2TO_8197F)
+#define BIT_CLEAR_CTS2TO_8197F(x) ((x) & (~BITS_CTS2TO_8197F))
+#define BIT_GET_CTS2TO_8197F(x) \
+ (((x) >> BIT_SHIFT_CTS2TO_8197F) & BIT_MASK_CTS2TO_8197F)
+#define BIT_SET_CTS2TO_8197F(x, v) \
+ (BIT_CLEAR_CTS2TO_8197F(x) | BIT_CTS2TO_8197F(v))
+
+/* 2 REG_ACKTO_8197F (ACK TIMEOUT REGISTER) */
+
+#define BIT_SHIFT_ACKTO_8197F 0
+#define BIT_MASK_ACKTO_8197F 0xff
+#define BIT_ACKTO_8197F(x) \
+ (((x) & BIT_MASK_ACKTO_8197F) << BIT_SHIFT_ACKTO_8197F)
+#define BITS_ACKTO_8197F (BIT_MASK_ACKTO_8197F << BIT_SHIFT_ACKTO_8197F)
+#define BIT_CLEAR_ACKTO_8197F(x) ((x) & (~BITS_ACKTO_8197F))
+#define BIT_GET_ACKTO_8197F(x) \
+ (((x) >> BIT_SHIFT_ACKTO_8197F) & BIT_MASK_ACKTO_8197F)
+#define BIT_SET_ACKTO_8197F(x, v) \
+ (BIT_CLEAR_ACKTO_8197F(x) | BIT_ACKTO_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NAV_CTRL_8197F (NAV CONTROL REGISTER) */
+
+#define BIT_SHIFT_NAV_UPPER_8197F 16
+#define BIT_MASK_NAV_UPPER_8197F 0xff
+#define BIT_NAV_UPPER_8197F(x) \
+ (((x) & BIT_MASK_NAV_UPPER_8197F) << BIT_SHIFT_NAV_UPPER_8197F)
+#define BITS_NAV_UPPER_8197F \
+ (BIT_MASK_NAV_UPPER_8197F << BIT_SHIFT_NAV_UPPER_8197F)
+#define BIT_CLEAR_NAV_UPPER_8197F(x) ((x) & (~BITS_NAV_UPPER_8197F))
+#define BIT_GET_NAV_UPPER_8197F(x) \
+ (((x) >> BIT_SHIFT_NAV_UPPER_8197F) & BIT_MASK_NAV_UPPER_8197F)
+#define BIT_SET_NAV_UPPER_8197F(x, v) \
+ (BIT_CLEAR_NAV_UPPER_8197F(x) | BIT_NAV_UPPER_8197F(v))
+
+#define BIT_SHIFT_RXMYRTS_NAV_8197F 8
+#define BIT_MASK_RXMYRTS_NAV_8197F 0xf
+#define BIT_RXMYRTS_NAV_8197F(x) \
+ (((x) & BIT_MASK_RXMYRTS_NAV_8197F) << BIT_SHIFT_RXMYRTS_NAV_8197F)
+#define BITS_RXMYRTS_NAV_8197F \
+ (BIT_MASK_RXMYRTS_NAV_8197F << BIT_SHIFT_RXMYRTS_NAV_8197F)
+#define BIT_CLEAR_RXMYRTS_NAV_8197F(x) ((x) & (~BITS_RXMYRTS_NAV_8197F))
+#define BIT_GET_RXMYRTS_NAV_8197F(x) \
+ (((x) >> BIT_SHIFT_RXMYRTS_NAV_8197F) & BIT_MASK_RXMYRTS_NAV_8197F)
+#define BIT_SET_RXMYRTS_NAV_8197F(x, v) \
+ (BIT_CLEAR_RXMYRTS_NAV_8197F(x) | BIT_RXMYRTS_NAV_8197F(v))
+
+#define BIT_SHIFT_RTSRST_8197F 0
+#define BIT_MASK_RTSRST_8197F 0xff
+#define BIT_RTSRST_8197F(x) \
+ (((x) & BIT_MASK_RTSRST_8197F) << BIT_SHIFT_RTSRST_8197F)
+#define BITS_RTSRST_8197F (BIT_MASK_RTSRST_8197F << BIT_SHIFT_RTSRST_8197F)
+#define BIT_CLEAR_RTSRST_8197F(x) ((x) & (~BITS_RTSRST_8197F))
+#define BIT_GET_RTSRST_8197F(x) \
+ (((x) >> BIT_SHIFT_RTSRST_8197F) & BIT_MASK_RTSRST_8197F)
+#define BIT_SET_RTSRST_8197F(x, v) \
+ (BIT_CLEAR_RTSRST_8197F(x) | BIT_RTSRST_8197F(v))
+
+/* 2 REG_BACAMCMD_8197F (BLOCK ACK CAM COMMAND REGISTER) */
+#define BIT_BACAM_POLL_8197F BIT(31)
+#define BIT_BACAM_RST_8197F BIT(17)
+#define BIT_BACAM_RW_8197F BIT(16)
+
+#define BIT_SHIFT_TXSBM_8197F 14
+#define BIT_MASK_TXSBM_8197F 0x3
+#define BIT_TXSBM_8197F(x) \
+ (((x) & BIT_MASK_TXSBM_8197F) << BIT_SHIFT_TXSBM_8197F)
+#define BITS_TXSBM_8197F (BIT_MASK_TXSBM_8197F << BIT_SHIFT_TXSBM_8197F)
+#define BIT_CLEAR_TXSBM_8197F(x) ((x) & (~BITS_TXSBM_8197F))
+#define BIT_GET_TXSBM_8197F(x) \
+ (((x) >> BIT_SHIFT_TXSBM_8197F) & BIT_MASK_TXSBM_8197F)
+#define BIT_SET_TXSBM_8197F(x, v) \
+ (BIT_CLEAR_TXSBM_8197F(x) | BIT_TXSBM_8197F(v))
+
+#define BIT_SHIFT_BACAM_ADDR_8197F 0
+#define BIT_MASK_BACAM_ADDR_8197F 0x3f
+#define BIT_BACAM_ADDR_8197F(x) \
+ (((x) & BIT_MASK_BACAM_ADDR_8197F) << BIT_SHIFT_BACAM_ADDR_8197F)
+#define BITS_BACAM_ADDR_8197F \
+ (BIT_MASK_BACAM_ADDR_8197F << BIT_SHIFT_BACAM_ADDR_8197F)
+#define BIT_CLEAR_BACAM_ADDR_8197F(x) ((x) & (~BITS_BACAM_ADDR_8197F))
+#define BIT_GET_BACAM_ADDR_8197F(x) \
+ (((x) >> BIT_SHIFT_BACAM_ADDR_8197F) & BIT_MASK_BACAM_ADDR_8197F)
+#define BIT_SET_BACAM_ADDR_8197F(x, v) \
+ (BIT_CLEAR_BACAM_ADDR_8197F(x) | BIT_BACAM_ADDR_8197F(v))
+
+/* 2 REG_BACAMCONTENT_8197F (BLOCK ACK CAM CONTENT REGISTER) */
+
+#define BIT_SHIFT_BA_CONTENT_H_8197F (32 & CPU_OPT_WIDTH)
+#define BIT_MASK_BA_CONTENT_H_8197F 0xffffffffL
+#define BIT_BA_CONTENT_H_8197F(x) \
+ (((x) & BIT_MASK_BA_CONTENT_H_8197F) << BIT_SHIFT_BA_CONTENT_H_8197F)
+#define BITS_BA_CONTENT_H_8197F \
+ (BIT_MASK_BA_CONTENT_H_8197F << BIT_SHIFT_BA_CONTENT_H_8197F)
+#define BIT_CLEAR_BA_CONTENT_H_8197F(x) ((x) & (~BITS_BA_CONTENT_H_8197F))
+#define BIT_GET_BA_CONTENT_H_8197F(x) \
+ (((x) >> BIT_SHIFT_BA_CONTENT_H_8197F) & BIT_MASK_BA_CONTENT_H_8197F)
+#define BIT_SET_BA_CONTENT_H_8197F(x, v) \
+ (BIT_CLEAR_BA_CONTENT_H_8197F(x) | BIT_BA_CONTENT_H_8197F(v))
+
+#define BIT_SHIFT_BA_CONTENT_L_8197F 0
+#define BIT_MASK_BA_CONTENT_L_8197F 0xffffffffL
+#define BIT_BA_CONTENT_L_8197F(x) \
+ (((x) & BIT_MASK_BA_CONTENT_L_8197F) << BIT_SHIFT_BA_CONTENT_L_8197F)
+#define BITS_BA_CONTENT_L_8197F \
+ (BIT_MASK_BA_CONTENT_L_8197F << BIT_SHIFT_BA_CONTENT_L_8197F)
+#define BIT_CLEAR_BA_CONTENT_L_8197F(x) ((x) & (~BITS_BA_CONTENT_L_8197F))
+#define BIT_GET_BA_CONTENT_L_8197F(x) \
+ (((x) >> BIT_SHIFT_BA_CONTENT_L_8197F) & BIT_MASK_BA_CONTENT_L_8197F)
+#define BIT_SET_BA_CONTENT_L_8197F(x, v) \
+ (BIT_CLEAR_BA_CONTENT_L_8197F(x) | BIT_BA_CONTENT_L_8197F(v))
+
+/* 2 REG_WMAC_BITMAP_CTL_8197F */
+#define BIT_BITMAP_VO_8197F BIT(7)
+#define BIT_BITMAP_VI_8197F BIT(6)
+#define BIT_BITMAP_BE_8197F BIT(5)
+#define BIT_BITMAP_BK_8197F BIT(4)
+
+#define BIT_SHIFT_BITMAP_CONDITION_8197F 2
+#define BIT_MASK_BITMAP_CONDITION_8197F 0x3
+#define BIT_BITMAP_CONDITION_8197F(x) \
+ (((x) & BIT_MASK_BITMAP_CONDITION_8197F) \
+ << BIT_SHIFT_BITMAP_CONDITION_8197F)
+#define BITS_BITMAP_CONDITION_8197F \
+ (BIT_MASK_BITMAP_CONDITION_8197F << BIT_SHIFT_BITMAP_CONDITION_8197F)
+#define BIT_CLEAR_BITMAP_CONDITION_8197F(x) \
+ ((x) & (~BITS_BITMAP_CONDITION_8197F))
+#define BIT_GET_BITMAP_CONDITION_8197F(x) \
+ (((x) >> BIT_SHIFT_BITMAP_CONDITION_8197F) & \
+ BIT_MASK_BITMAP_CONDITION_8197F)
+#define BIT_SET_BITMAP_CONDITION_8197F(x, v) \
+ (BIT_CLEAR_BITMAP_CONDITION_8197F(x) | BIT_BITMAP_CONDITION_8197F(v))
+
+#define BIT_BITMAP_SSNBK_COUNTER_CLR_8197F BIT(1)
+#define BIT_BITMAP_FORCE_8197F BIT(0)
+
+/* 2 REG_NOT_VALID_8197F */
+
+#define BIT_SHIFT_RXPKT_TYPE_8197F 2
+#define BIT_MASK_RXPKT_TYPE_8197F 0x3f
+#define BIT_RXPKT_TYPE_8197F(x) \
+ (((x) & BIT_MASK_RXPKT_TYPE_8197F) << BIT_SHIFT_RXPKT_TYPE_8197F)
+#define BITS_RXPKT_TYPE_8197F \
+ (BIT_MASK_RXPKT_TYPE_8197F << BIT_SHIFT_RXPKT_TYPE_8197F)
+#define BIT_CLEAR_RXPKT_TYPE_8197F(x) ((x) & (~BITS_RXPKT_TYPE_8197F))
+#define BIT_GET_RXPKT_TYPE_8197F(x) \
+ (((x) >> BIT_SHIFT_RXPKT_TYPE_8197F) & BIT_MASK_RXPKT_TYPE_8197F)
+#define BIT_SET_RXPKT_TYPE_8197F(x, v) \
+ (BIT_CLEAR_RXPKT_TYPE_8197F(x) | BIT_RXPKT_TYPE_8197F(v))
+
+#define BIT_TXACT_IND_8197F BIT(1)
+#define BIT_RXACT_IND_8197F BIT(0)
+
+/* 2 REG_WMAC_BACAM_RPMEN_8197F */
+
+#define BIT_SHIFT_BITMAP_SSNBK_COUNTER_8197F 2
+#define BIT_MASK_BITMAP_SSNBK_COUNTER_8197F 0x3f
+#define BIT_BITMAP_SSNBK_COUNTER_8197F(x) \
+ (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8197F) \
+ << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8197F)
+#define BITS_BITMAP_SSNBK_COUNTER_8197F \
+ (BIT_MASK_BITMAP_SSNBK_COUNTER_8197F \
+ << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8197F)
+#define BIT_CLEAR_BITMAP_SSNBK_COUNTER_8197F(x) \
+ ((x) & (~BITS_BITMAP_SSNBK_COUNTER_8197F))
+#define BIT_GET_BITMAP_SSNBK_COUNTER_8197F(x) \
+ (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8197F) & \
+ BIT_MASK_BITMAP_SSNBK_COUNTER_8197F)
+#define BIT_SET_BITMAP_SSNBK_COUNTER_8197F(x, v) \
+ (BIT_CLEAR_BITMAP_SSNBK_COUNTER_8197F(x) | \
+ BIT_BITMAP_SSNBK_COUNTER_8197F(v))
+
+#define BIT_BITMAP_EN_8197F BIT(1)
+#define BIT_WMAC_BACAM_RPMEN_8197F BIT(0)
+
+/* 2 REG_LBDLY_8197F (LOOPBACK DELAY REGISTER) */
+
+#define BIT_SHIFT_LBDLY_8197F 0
+#define BIT_MASK_LBDLY_8197F 0x1f
+#define BIT_LBDLY_8197F(x) \
+ (((x) & BIT_MASK_LBDLY_8197F) << BIT_SHIFT_LBDLY_8197F)
+#define BITS_LBDLY_8197F (BIT_MASK_LBDLY_8197F << BIT_SHIFT_LBDLY_8197F)
+#define BIT_CLEAR_LBDLY_8197F(x) ((x) & (~BITS_LBDLY_8197F))
+#define BIT_GET_LBDLY_8197F(x) \
+ (((x) >> BIT_SHIFT_LBDLY_8197F) & BIT_MASK_LBDLY_8197F)
+#define BIT_SET_LBDLY_8197F(x, v) \
+ (BIT_CLEAR_LBDLY_8197F(x) | BIT_LBDLY_8197F(v))
+
+/* 2 REG_RXERR_RPT_8197F (RX ERROR REPORT REGISTER) */
+
+#define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8197F 28
+#define BIT_MASK_RXERR_RPT_SEL_V1_3_0_8197F 0xf
+#define BIT_RXERR_RPT_SEL_V1_3_0_8197F(x) \
+ (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8197F) \
+ << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8197F)
+#define BITS_RXERR_RPT_SEL_V1_3_0_8197F \
+ (BIT_MASK_RXERR_RPT_SEL_V1_3_0_8197F \
+ << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8197F)
+#define BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8197F(x) \
+ ((x) & (~BITS_RXERR_RPT_SEL_V1_3_0_8197F))
+#define BIT_GET_RXERR_RPT_SEL_V1_3_0_8197F(x) \
+ (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8197F) & \
+ BIT_MASK_RXERR_RPT_SEL_V1_3_0_8197F)
+#define BIT_SET_RXERR_RPT_SEL_V1_3_0_8197F(x, v) \
+ (BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8197F(x) | \
+ BIT_RXERR_RPT_SEL_V1_3_0_8197F(v))
+
+#define BIT_RXERR_RPT_RST_8197F BIT(27)
+#define BIT_RXERR_RPT_SEL_V1_4_8197F BIT(26)
+
+#define BIT_SHIFT_UD_SELECT_BSSID_2_1_8197F 24
+#define BIT_MASK_UD_SELECT_BSSID_2_1_8197F 0x3
+#define BIT_UD_SELECT_BSSID_2_1_8197F(x) \
+ (((x) & BIT_MASK_UD_SELECT_BSSID_2_1_8197F) \
+ << BIT_SHIFT_UD_SELECT_BSSID_2_1_8197F)
+#define BITS_UD_SELECT_BSSID_2_1_8197F \
+ (BIT_MASK_UD_SELECT_BSSID_2_1_8197F \
+ << BIT_SHIFT_UD_SELECT_BSSID_2_1_8197F)
+#define BIT_CLEAR_UD_SELECT_BSSID_2_1_8197F(x) \
+ ((x) & (~BITS_UD_SELECT_BSSID_2_1_8197F))
+#define BIT_GET_UD_SELECT_BSSID_2_1_8197F(x) \
+ (((x) >> BIT_SHIFT_UD_SELECT_BSSID_2_1_8197F) & \
+ BIT_MASK_UD_SELECT_BSSID_2_1_8197F)
+#define BIT_SET_UD_SELECT_BSSID_2_1_8197F(x, v) \
+ (BIT_CLEAR_UD_SELECT_BSSID_2_1_8197F(x) | \
+ BIT_UD_SELECT_BSSID_2_1_8197F(v))
+
+#define BIT_W1S_8197F BIT(23)
+#define BIT_UD_SELECT_BSSID_0_8197F BIT(22)
+
+#define BIT_SHIFT_UD_SUB_TYPE_8197F 18
+#define BIT_MASK_UD_SUB_TYPE_8197F 0xf
+#define BIT_UD_SUB_TYPE_8197F(x) \
+ (((x) & BIT_MASK_UD_SUB_TYPE_8197F) << BIT_SHIFT_UD_SUB_TYPE_8197F)
+#define BITS_UD_SUB_TYPE_8197F \
+ (BIT_MASK_UD_SUB_TYPE_8197F << BIT_SHIFT_UD_SUB_TYPE_8197F)
+#define BIT_CLEAR_UD_SUB_TYPE_8197F(x) ((x) & (~BITS_UD_SUB_TYPE_8197F))
+#define BIT_GET_UD_SUB_TYPE_8197F(x) \
+ (((x) >> BIT_SHIFT_UD_SUB_TYPE_8197F) & BIT_MASK_UD_SUB_TYPE_8197F)
+#define BIT_SET_UD_SUB_TYPE_8197F(x, v) \
+ (BIT_CLEAR_UD_SUB_TYPE_8197F(x) | BIT_UD_SUB_TYPE_8197F(v))
+
+#define BIT_SHIFT_UD_TYPE_8197F 16
+#define BIT_MASK_UD_TYPE_8197F 0x3
+#define BIT_UD_TYPE_8197F(x) \
+ (((x) & BIT_MASK_UD_TYPE_8197F) << BIT_SHIFT_UD_TYPE_8197F)
+#define BITS_UD_TYPE_8197F (BIT_MASK_UD_TYPE_8197F << BIT_SHIFT_UD_TYPE_8197F)
+#define BIT_CLEAR_UD_TYPE_8197F(x) ((x) & (~BITS_UD_TYPE_8197F))
+#define BIT_GET_UD_TYPE_8197F(x) \
+ (((x) >> BIT_SHIFT_UD_TYPE_8197F) & BIT_MASK_UD_TYPE_8197F)
+#define BIT_SET_UD_TYPE_8197F(x, v) \
+ (BIT_CLEAR_UD_TYPE_8197F(x) | BIT_UD_TYPE_8197F(v))
+
+#define BIT_SHIFT_RPT_COUNTER_8197F 0
+#define BIT_MASK_RPT_COUNTER_8197F 0xffff
+#define BIT_RPT_COUNTER_8197F(x) \
+ (((x) & BIT_MASK_RPT_COUNTER_8197F) << BIT_SHIFT_RPT_COUNTER_8197F)
+#define BITS_RPT_COUNTER_8197F \
+ (BIT_MASK_RPT_COUNTER_8197F << BIT_SHIFT_RPT_COUNTER_8197F)
+#define BIT_CLEAR_RPT_COUNTER_8197F(x) ((x) & (~BITS_RPT_COUNTER_8197F))
+#define BIT_GET_RPT_COUNTER_8197F(x) \
+ (((x) >> BIT_SHIFT_RPT_COUNTER_8197F) & BIT_MASK_RPT_COUNTER_8197F)
+#define BIT_SET_RPT_COUNTER_8197F(x, v) \
+ (BIT_CLEAR_RPT_COUNTER_8197F(x) | BIT_RPT_COUNTER_8197F(v))
+
+/* 2 REG_WMAC_TRXPTCL_CTL_8197F (WMAC TX/RX PROTOCOL CONTROL REGISTER) */
+
+#define BIT_SHIFT_ACKBA_TYPSEL_8197F (60 & CPU_OPT_WIDTH)
+#define BIT_MASK_ACKBA_TYPSEL_8197F 0xf
+#define BIT_ACKBA_TYPSEL_8197F(x) \
+ (((x) & BIT_MASK_ACKBA_TYPSEL_8197F) << BIT_SHIFT_ACKBA_TYPSEL_8197F)
+#define BITS_ACKBA_TYPSEL_8197F \
+ (BIT_MASK_ACKBA_TYPSEL_8197F << BIT_SHIFT_ACKBA_TYPSEL_8197F)
+#define BIT_CLEAR_ACKBA_TYPSEL_8197F(x) ((x) & (~BITS_ACKBA_TYPSEL_8197F))
+#define BIT_GET_ACKBA_TYPSEL_8197F(x) \
+ (((x) >> BIT_SHIFT_ACKBA_TYPSEL_8197F) & BIT_MASK_ACKBA_TYPSEL_8197F)
+#define BIT_SET_ACKBA_TYPSEL_8197F(x, v) \
+ (BIT_CLEAR_ACKBA_TYPSEL_8197F(x) | BIT_ACKBA_TYPSEL_8197F(v))
+
+#define BIT_SHIFT_ACKBA_ACKPCHK_8197F (56 & CPU_OPT_WIDTH)
+#define BIT_MASK_ACKBA_ACKPCHK_8197F 0xf
+#define BIT_ACKBA_ACKPCHK_8197F(x) \
+ (((x) & BIT_MASK_ACKBA_ACKPCHK_8197F) << BIT_SHIFT_ACKBA_ACKPCHK_8197F)
+#define BITS_ACKBA_ACKPCHK_8197F \
+ (BIT_MASK_ACKBA_ACKPCHK_8197F << BIT_SHIFT_ACKBA_ACKPCHK_8197F)
+#define BIT_CLEAR_ACKBA_ACKPCHK_8197F(x) ((x) & (~BITS_ACKBA_ACKPCHK_8197F))
+#define BIT_GET_ACKBA_ACKPCHK_8197F(x) \
+ (((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8197F) & BIT_MASK_ACKBA_ACKPCHK_8197F)
+#define BIT_SET_ACKBA_ACKPCHK_8197F(x, v) \
+ (BIT_CLEAR_ACKBA_ACKPCHK_8197F(x) | BIT_ACKBA_ACKPCHK_8197F(v))
+
+#define BIT_SHIFT_ACKBAR_TYPESEL_8197F (48 & CPU_OPT_WIDTH)
+#define BIT_MASK_ACKBAR_TYPESEL_8197F 0xff
+#define BIT_ACKBAR_TYPESEL_8197F(x) \
+ (((x) & BIT_MASK_ACKBAR_TYPESEL_8197F) \
+ << BIT_SHIFT_ACKBAR_TYPESEL_8197F)
+#define BITS_ACKBAR_TYPESEL_8197F \
+ (BIT_MASK_ACKBAR_TYPESEL_8197F << BIT_SHIFT_ACKBAR_TYPESEL_8197F)
+#define BIT_CLEAR_ACKBAR_TYPESEL_8197F(x) ((x) & (~BITS_ACKBAR_TYPESEL_8197F))
+#define BIT_GET_ACKBAR_TYPESEL_8197F(x) \
+ (((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8197F) & \
+ BIT_MASK_ACKBAR_TYPESEL_8197F)
+#define BIT_SET_ACKBAR_TYPESEL_8197F(x, v) \
+ (BIT_CLEAR_ACKBAR_TYPESEL_8197F(x) | BIT_ACKBAR_TYPESEL_8197F(v))
+
+#define BIT_SHIFT_ACKBAR_ACKPCHK_8197F (44 & CPU_OPT_WIDTH)
+#define BIT_MASK_ACKBAR_ACKPCHK_8197F 0xf
+#define BIT_ACKBAR_ACKPCHK_8197F(x) \
+ (((x) & BIT_MASK_ACKBAR_ACKPCHK_8197F) \
+ << BIT_SHIFT_ACKBAR_ACKPCHK_8197F)
+#define BITS_ACKBAR_ACKPCHK_8197F \
+ (BIT_MASK_ACKBAR_ACKPCHK_8197F << BIT_SHIFT_ACKBAR_ACKPCHK_8197F)
+#define BIT_CLEAR_ACKBAR_ACKPCHK_8197F(x) ((x) & (~BITS_ACKBAR_ACKPCHK_8197F))
+#define BIT_GET_ACKBAR_ACKPCHK_8197F(x) \
+ (((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8197F) & \
+ BIT_MASK_ACKBAR_ACKPCHK_8197F)
+#define BIT_SET_ACKBAR_ACKPCHK_8197F(x, v) \
+ (BIT_CLEAR_ACKBAR_ACKPCHK_8197F(x) | BIT_ACKBAR_ACKPCHK_8197F(v))
+
+#define BIT_RXBA_IGNOREA2_8197F BIT(42)
+#define BIT_EN_SAVE_ALL_TXOPADDR_8197F BIT(41)
+#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV_8197F BIT(40)
+#define BIT_DIS_TXBA_AMPDUFCSERR_8197F BIT(39)
+#define BIT_DIS_TXBA_RXBARINFULL_8197F BIT(38)
+#define BIT_DIS_TXCFE_INFULL_8197F BIT(37)
+#define BIT_DIS_TXCTS_INFULL_8197F BIT(36)
+#define BIT_EN_TXACKBA_IN_TX_RDG_8197F BIT(35)
+#define BIT_EN_TXACKBA_IN_TXOP_8197F BIT(34)
+#define BIT_EN_TXCTS_IN_RXNAV_8197F BIT(33)
+#define BIT_EN_TXCTS_INTXOP_8197F BIT(32)
+#define BIT_BLK_EDCA_BBSLP_8197F BIT(31)
+#define BIT_BLK_EDCA_BBSBY_8197F BIT(30)
+#define BIT_ACKTO_BLOCK_SCH_EN_8197F BIT(27)
+#define BIT_EIFS_BLOCK_SCH_EN_8197F BIT(26)
+#define BIT_PLCPCHK_RST_EIFS_8197F BIT(25)
+#define BIT_CCA_RST_EIFS_8197F BIT(24)
+#define BIT_DIS_UPD_MYRXPKTNAV_8197F BIT(23)
+#define BIT_EARLY_TXBA_8197F BIT(22)
+
+#define BIT_SHIFT_RESP_CHNBUSY_8197F 20
+#define BIT_MASK_RESP_CHNBUSY_8197F 0x3
+#define BIT_RESP_CHNBUSY_8197F(x) \
+ (((x) & BIT_MASK_RESP_CHNBUSY_8197F) << BIT_SHIFT_RESP_CHNBUSY_8197F)
+#define BITS_RESP_CHNBUSY_8197F \
+ (BIT_MASK_RESP_CHNBUSY_8197F << BIT_SHIFT_RESP_CHNBUSY_8197F)
+#define BIT_CLEAR_RESP_CHNBUSY_8197F(x) ((x) & (~BITS_RESP_CHNBUSY_8197F))
+#define BIT_GET_RESP_CHNBUSY_8197F(x) \
+ (((x) >> BIT_SHIFT_RESP_CHNBUSY_8197F) & BIT_MASK_RESP_CHNBUSY_8197F)
+#define BIT_SET_RESP_CHNBUSY_8197F(x, v) \
+ (BIT_CLEAR_RESP_CHNBUSY_8197F(x) | BIT_RESP_CHNBUSY_8197F(v))
+
+#define BIT_RESP_DCTS_EN_8197F BIT(19)
+#define BIT_RESP_DCFE_EN_8197F BIT(18)
+#define BIT_RESP_SPLCPEN_8197F BIT(17)
+#define BIT_RESP_SGIEN_8197F BIT(16)
+#define BIT_RESP_LDPC_EN_8197F BIT(15)
+#define BIT_DIS_RESP_ACKINCCA_8197F BIT(14)
+#define BIT_DIS_RESP_CTSINCCA_8197F BIT(13)
+
+#define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8197F 10
+#define BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8197F 0x7
+#define BIT_R_WMAC_SECOND_CCA_TIMER_8197F(x) \
+ (((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8197F) \
+ << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8197F)
+#define BITS_R_WMAC_SECOND_CCA_TIMER_8197F \
+ (BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8197F \
+ << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8197F)
+#define BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8197F(x) \
+ ((x) & (~BITS_R_WMAC_SECOND_CCA_TIMER_8197F))
+#define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8197F(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8197F) & \
+ BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8197F)
+#define BIT_SET_R_WMAC_SECOND_CCA_TIMER_8197F(x, v) \
+ (BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8197F(x) | \
+ BIT_R_WMAC_SECOND_CCA_TIMER_8197F(v))
+
+#define BIT_SHIFT_RFMOD_8197F 7
+#define BIT_MASK_RFMOD_8197F 0x3
+#define BIT_RFMOD_8197F(x) \
+ (((x) & BIT_MASK_RFMOD_8197F) << BIT_SHIFT_RFMOD_8197F)
+#define BITS_RFMOD_8197F (BIT_MASK_RFMOD_8197F << BIT_SHIFT_RFMOD_8197F)
+#define BIT_CLEAR_RFMOD_8197F(x) ((x) & (~BITS_RFMOD_8197F))
+#define BIT_GET_RFMOD_8197F(x) \
+ (((x) >> BIT_SHIFT_RFMOD_8197F) & BIT_MASK_RFMOD_8197F)
+#define BIT_SET_RFMOD_8197F(x, v) \
+ (BIT_CLEAR_RFMOD_8197F(x) | BIT_RFMOD_8197F(v))
+
+#define BIT_SHIFT_RESP_CTS_DYNBW_SEL_8197F 5
+#define BIT_MASK_RESP_CTS_DYNBW_SEL_8197F 0x3
+#define BIT_RESP_CTS_DYNBW_SEL_8197F(x) \
+ (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8197F) \
+ << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8197F)
+#define BITS_RESP_CTS_DYNBW_SEL_8197F \
+ (BIT_MASK_RESP_CTS_DYNBW_SEL_8197F \
+ << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8197F)
+#define BIT_CLEAR_RESP_CTS_DYNBW_SEL_8197F(x) \
+ ((x) & (~BITS_RESP_CTS_DYNBW_SEL_8197F))
+#define BIT_GET_RESP_CTS_DYNBW_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8197F) & \
+ BIT_MASK_RESP_CTS_DYNBW_SEL_8197F)
+#define BIT_SET_RESP_CTS_DYNBW_SEL_8197F(x, v) \
+ (BIT_CLEAR_RESP_CTS_DYNBW_SEL_8197F(x) | \
+ BIT_RESP_CTS_DYNBW_SEL_8197F(v))
+
+#define BIT_DLY_TX_WAIT_RXANTSEL_8197F BIT(4)
+#define BIT_TXRESP_BY_RXANTSEL_8197F BIT(3)
+
+#define BIT_SHIFT_ORIG_DCTS_CHK_8197F 0
+#define BIT_MASK_ORIG_DCTS_CHK_8197F 0x3
+#define BIT_ORIG_DCTS_CHK_8197F(x) \
+ (((x) & BIT_MASK_ORIG_DCTS_CHK_8197F) << BIT_SHIFT_ORIG_DCTS_CHK_8197F)
+#define BITS_ORIG_DCTS_CHK_8197F \
+ (BIT_MASK_ORIG_DCTS_CHK_8197F << BIT_SHIFT_ORIG_DCTS_CHK_8197F)
+#define BIT_CLEAR_ORIG_DCTS_CHK_8197F(x) ((x) & (~BITS_ORIG_DCTS_CHK_8197F))
+#define BIT_GET_ORIG_DCTS_CHK_8197F(x) \
+ (((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8197F) & BIT_MASK_ORIG_DCTS_CHK_8197F)
+#define BIT_SET_ORIG_DCTS_CHK_8197F(x, v) \
+ (BIT_CLEAR_ORIG_DCTS_CHK_8197F(x) | BIT_ORIG_DCTS_CHK_8197F(v))
+
+/* 2 REG_CAMCMD_8197F (CAM COMMAND REGISTER) */
+#define BIT_SECCAM_POLLING_8197F BIT(31)
+#define BIT_SECCAM_CLR_8197F BIT(30)
+#define BIT_MFBCAM_CLR_8197F BIT(29)
+#define BIT_SECCAM_WE_8197F BIT(16)
+
+#define BIT_SHIFT_SECCAM_ADDR_V2_8197F 0
+#define BIT_MASK_SECCAM_ADDR_V2_8197F 0x3ff
+#define BIT_SECCAM_ADDR_V2_8197F(x) \
+ (((x) & BIT_MASK_SECCAM_ADDR_V2_8197F) \
+ << BIT_SHIFT_SECCAM_ADDR_V2_8197F)
+#define BITS_SECCAM_ADDR_V2_8197F \
+ (BIT_MASK_SECCAM_ADDR_V2_8197F << BIT_SHIFT_SECCAM_ADDR_V2_8197F)
+#define BIT_CLEAR_SECCAM_ADDR_V2_8197F(x) ((x) & (~BITS_SECCAM_ADDR_V2_8197F))
+#define BIT_GET_SECCAM_ADDR_V2_8197F(x) \
+ (((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8197F) & \
+ BIT_MASK_SECCAM_ADDR_V2_8197F)
+#define BIT_SET_SECCAM_ADDR_V2_8197F(x, v) \
+ (BIT_CLEAR_SECCAM_ADDR_V2_8197F(x) | BIT_SECCAM_ADDR_V2_8197F(v))
+
+/* 2 REG_CAMWRITE_8197F (CAM WRITE REGISTER) */
+
+#define BIT_SHIFT_CAMW_DATA_8197F 0
+#define BIT_MASK_CAMW_DATA_8197F 0xffffffffL
+#define BIT_CAMW_DATA_8197F(x) \
+ (((x) & BIT_MASK_CAMW_DATA_8197F) << BIT_SHIFT_CAMW_DATA_8197F)
+#define BITS_CAMW_DATA_8197F \
+ (BIT_MASK_CAMW_DATA_8197F << BIT_SHIFT_CAMW_DATA_8197F)
+#define BIT_CLEAR_CAMW_DATA_8197F(x) ((x) & (~BITS_CAMW_DATA_8197F))
+#define BIT_GET_CAMW_DATA_8197F(x) \
+ (((x) >> BIT_SHIFT_CAMW_DATA_8197F) & BIT_MASK_CAMW_DATA_8197F)
+#define BIT_SET_CAMW_DATA_8197F(x, v) \
+ (BIT_CLEAR_CAMW_DATA_8197F(x) | BIT_CAMW_DATA_8197F(v))
+
+/* 2 REG_CAMREAD_8197F (CAM READ REGISTER) */
+
+#define BIT_SHIFT_CAMR_DATA_8197F 0
+#define BIT_MASK_CAMR_DATA_8197F 0xffffffffL
+#define BIT_CAMR_DATA_8197F(x) \
+ (((x) & BIT_MASK_CAMR_DATA_8197F) << BIT_SHIFT_CAMR_DATA_8197F)
+#define BITS_CAMR_DATA_8197F \
+ (BIT_MASK_CAMR_DATA_8197F << BIT_SHIFT_CAMR_DATA_8197F)
+#define BIT_CLEAR_CAMR_DATA_8197F(x) ((x) & (~BITS_CAMR_DATA_8197F))
+#define BIT_GET_CAMR_DATA_8197F(x) \
+ (((x) >> BIT_SHIFT_CAMR_DATA_8197F) & BIT_MASK_CAMR_DATA_8197F)
+#define BIT_SET_CAMR_DATA_8197F(x, v) \
+ (BIT_CLEAR_CAMR_DATA_8197F(x) | BIT_CAMR_DATA_8197F(v))
+
+/* 2 REG_CAMDBG_8197F (CAM DEBUG REGISTER) */
+#define BIT_SECCAM_INFO_8197F BIT(31)
+#define BIT_SEC_KEYFOUND_8197F BIT(15)
+
+#define BIT_SHIFT_CAMDBG_SEC_TYPE_8197F 12
+#define BIT_MASK_CAMDBG_SEC_TYPE_8197F 0x7
+#define BIT_CAMDBG_SEC_TYPE_8197F(x) \
+ (((x) & BIT_MASK_CAMDBG_SEC_TYPE_8197F) \
+ << BIT_SHIFT_CAMDBG_SEC_TYPE_8197F)
+#define BITS_CAMDBG_SEC_TYPE_8197F \
+ (BIT_MASK_CAMDBG_SEC_TYPE_8197F << BIT_SHIFT_CAMDBG_SEC_TYPE_8197F)
+#define BIT_CLEAR_CAMDBG_SEC_TYPE_8197F(x) ((x) & (~BITS_CAMDBG_SEC_TYPE_8197F))
+#define BIT_GET_CAMDBG_SEC_TYPE_8197F(x) \
+ (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8197F) & \
+ BIT_MASK_CAMDBG_SEC_TYPE_8197F)
+#define BIT_SET_CAMDBG_SEC_TYPE_8197F(x, v) \
+ (BIT_CLEAR_CAMDBG_SEC_TYPE_8197F(x) | BIT_CAMDBG_SEC_TYPE_8197F(v))
+
+#define BIT_CAMDBG_EXT_SEC_TYPE_8197F BIT(11)
+
+#define BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8197F 5
+#define BIT_MASK_CAMDBG_MIC_KEY_IDX_8197F 0x1f
+#define BIT_CAMDBG_MIC_KEY_IDX_8197F(x) \
+ (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8197F) \
+ << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8197F)
+#define BITS_CAMDBG_MIC_KEY_IDX_8197F \
+ (BIT_MASK_CAMDBG_MIC_KEY_IDX_8197F \
+ << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8197F)
+#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8197F(x) \
+ ((x) & (~BITS_CAMDBG_MIC_KEY_IDX_8197F))
+#define BIT_GET_CAMDBG_MIC_KEY_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8197F) & \
+ BIT_MASK_CAMDBG_MIC_KEY_IDX_8197F)
+#define BIT_SET_CAMDBG_MIC_KEY_IDX_8197F(x, v) \
+ (BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8197F(x) | \
+ BIT_CAMDBG_MIC_KEY_IDX_8197F(v))
+
+#define BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8197F 0
+#define BIT_MASK_CAMDBG_SEC_KEY_IDX_8197F 0x1f
+#define BIT_CAMDBG_SEC_KEY_IDX_8197F(x) \
+ (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8197F) \
+ << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8197F)
+#define BITS_CAMDBG_SEC_KEY_IDX_8197F \
+ (BIT_MASK_CAMDBG_SEC_KEY_IDX_8197F \
+ << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8197F)
+#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8197F(x) \
+ ((x) & (~BITS_CAMDBG_SEC_KEY_IDX_8197F))
+#define BIT_GET_CAMDBG_SEC_KEY_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8197F) & \
+ BIT_MASK_CAMDBG_SEC_KEY_IDX_8197F)
+#define BIT_SET_CAMDBG_SEC_KEY_IDX_8197F(x, v) \
+ (BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8197F(x) | \
+ BIT_CAMDBG_SEC_KEY_IDX_8197F(v))
+
+/* 2 REG_RXFILTER_ACTION_1_8197F */
+
+#define BIT_SHIFT_RXFILTER_ACTION_1_8197F 0
+#define BIT_MASK_RXFILTER_ACTION_1_8197F 0xff
+#define BIT_RXFILTER_ACTION_1_8197F(x) \
+ (((x) & BIT_MASK_RXFILTER_ACTION_1_8197F) \
+ << BIT_SHIFT_RXFILTER_ACTION_1_8197F)
+#define BITS_RXFILTER_ACTION_1_8197F \
+ (BIT_MASK_RXFILTER_ACTION_1_8197F << BIT_SHIFT_RXFILTER_ACTION_1_8197F)
+#define BIT_CLEAR_RXFILTER_ACTION_1_8197F(x) \
+ ((x) & (~BITS_RXFILTER_ACTION_1_8197F))
+#define BIT_GET_RXFILTER_ACTION_1_8197F(x) \
+ (((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8197F) & \
+ BIT_MASK_RXFILTER_ACTION_1_8197F)
+#define BIT_SET_RXFILTER_ACTION_1_8197F(x, v) \
+ (BIT_CLEAR_RXFILTER_ACTION_1_8197F(x) | BIT_RXFILTER_ACTION_1_8197F(v))
+
+/* 2 REG_RXFILTER_CATEGORY_1_8197F */
+
+#define BIT_SHIFT_RXFILTER_CATEGORY_1_8197F 0
+#define BIT_MASK_RXFILTER_CATEGORY_1_8197F 0xff
+#define BIT_RXFILTER_CATEGORY_1_8197F(x) \
+ (((x) & BIT_MASK_RXFILTER_CATEGORY_1_8197F) \
+ << BIT_SHIFT_RXFILTER_CATEGORY_1_8197F)
+#define BITS_RXFILTER_CATEGORY_1_8197F \
+ (BIT_MASK_RXFILTER_CATEGORY_1_8197F \
+ << BIT_SHIFT_RXFILTER_CATEGORY_1_8197F)
+#define BIT_CLEAR_RXFILTER_CATEGORY_1_8197F(x) \
+ ((x) & (~BITS_RXFILTER_CATEGORY_1_8197F))
+#define BIT_GET_RXFILTER_CATEGORY_1_8197F(x) \
+ (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8197F) & \
+ BIT_MASK_RXFILTER_CATEGORY_1_8197F)
+#define BIT_SET_RXFILTER_CATEGORY_1_8197F(x, v) \
+ (BIT_CLEAR_RXFILTER_CATEGORY_1_8197F(x) | \
+ BIT_RXFILTER_CATEGORY_1_8197F(v))
+
+/* 2 REG_SECCFG_8197F (SECURITY CONFIGURATION REGISTER) */
+#define BIT_DIS_GCLK_WAPI_8197F BIT(15)
+#define BIT_DIS_GCLK_AES_8197F BIT(14)
+#define BIT_DIS_GCLK_TKIP_8197F BIT(13)
+#define BIT_AES_SEL_QC_1_8197F BIT(12)
+#define BIT_AES_SEL_QC_0_8197F BIT(11)
+#define BIT_WMAC_CKECK_BMC_8197F BIT(9)
+#define BIT_CHK_KEYID_8197F BIT(8)
+#define BIT_RXBCUSEDK_8197F BIT(7)
+#define BIT_TXBCUSEDK_8197F BIT(6)
+#define BIT_NOSKMC_8197F BIT(5)
+#define BIT_SKBYA2_8197F BIT(4)
+#define BIT_RXDEC_8197F BIT(3)
+#define BIT_TXENC_8197F BIT(2)
+#define BIT_RXUHUSEDK_8197F BIT(1)
+#define BIT_TXUHUSEDK_8197F BIT(0)
+
+/* 2 REG_RXFILTER_ACTION_3_8197F */
+
+#define BIT_SHIFT_RXFILTER_ACTION_3_8197F 0
+#define BIT_MASK_RXFILTER_ACTION_3_8197F 0xff
+#define BIT_RXFILTER_ACTION_3_8197F(x) \
+ (((x) & BIT_MASK_RXFILTER_ACTION_3_8197F) \
+ << BIT_SHIFT_RXFILTER_ACTION_3_8197F)
+#define BITS_RXFILTER_ACTION_3_8197F \
+ (BIT_MASK_RXFILTER_ACTION_3_8197F << BIT_SHIFT_RXFILTER_ACTION_3_8197F)
+#define BIT_CLEAR_RXFILTER_ACTION_3_8197F(x) \
+ ((x) & (~BITS_RXFILTER_ACTION_3_8197F))
+#define BIT_GET_RXFILTER_ACTION_3_8197F(x) \
+ (((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8197F) & \
+ BIT_MASK_RXFILTER_ACTION_3_8197F)
+#define BIT_SET_RXFILTER_ACTION_3_8197F(x, v) \
+ (BIT_CLEAR_RXFILTER_ACTION_3_8197F(x) | BIT_RXFILTER_ACTION_3_8197F(v))
+
+/* 2 REG_RXFILTER_CATEGORY_3_8197F */
+
+#define BIT_SHIFT_RXFILTER_CATEGORY_3_8197F 0
+#define BIT_MASK_RXFILTER_CATEGORY_3_8197F 0xff
+#define BIT_RXFILTER_CATEGORY_3_8197F(x) \
+ (((x) & BIT_MASK_RXFILTER_CATEGORY_3_8197F) \
+ << BIT_SHIFT_RXFILTER_CATEGORY_3_8197F)
+#define BITS_RXFILTER_CATEGORY_3_8197F \
+ (BIT_MASK_RXFILTER_CATEGORY_3_8197F \
+ << BIT_SHIFT_RXFILTER_CATEGORY_3_8197F)
+#define BIT_CLEAR_RXFILTER_CATEGORY_3_8197F(x) \
+ ((x) & (~BITS_RXFILTER_CATEGORY_3_8197F))
+#define BIT_GET_RXFILTER_CATEGORY_3_8197F(x) \
+ (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8197F) & \
+ BIT_MASK_RXFILTER_CATEGORY_3_8197F)
+#define BIT_SET_RXFILTER_CATEGORY_3_8197F(x, v) \
+ (BIT_CLEAR_RXFILTER_CATEGORY_3_8197F(x) | \
+ BIT_RXFILTER_CATEGORY_3_8197F(v))
+
+/* 2 REG_RXFILTER_ACTION_2_8197F */
+
+#define BIT_SHIFT_RXFILTER_ACTION_2_8197F 0
+#define BIT_MASK_RXFILTER_ACTION_2_8197F 0xff
+#define BIT_RXFILTER_ACTION_2_8197F(x) \
+ (((x) & BIT_MASK_RXFILTER_ACTION_2_8197F) \
+ << BIT_SHIFT_RXFILTER_ACTION_2_8197F)
+#define BITS_RXFILTER_ACTION_2_8197F \
+ (BIT_MASK_RXFILTER_ACTION_2_8197F << BIT_SHIFT_RXFILTER_ACTION_2_8197F)
+#define BIT_CLEAR_RXFILTER_ACTION_2_8197F(x) \
+ ((x) & (~BITS_RXFILTER_ACTION_2_8197F))
+#define BIT_GET_RXFILTER_ACTION_2_8197F(x) \
+ (((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8197F) & \
+ BIT_MASK_RXFILTER_ACTION_2_8197F)
+#define BIT_SET_RXFILTER_ACTION_2_8197F(x, v) \
+ (BIT_CLEAR_RXFILTER_ACTION_2_8197F(x) | BIT_RXFILTER_ACTION_2_8197F(v))
+
+/* 2 REG_RXFILTER_CATEGORY_2_8197F */
+
+#define BIT_SHIFT_RXFILTER_CATEGORY_2_8197F 0
+#define BIT_MASK_RXFILTER_CATEGORY_2_8197F 0xff
+#define BIT_RXFILTER_CATEGORY_2_8197F(x) \
+ (((x) & BIT_MASK_RXFILTER_CATEGORY_2_8197F) \
+ << BIT_SHIFT_RXFILTER_CATEGORY_2_8197F)
+#define BITS_RXFILTER_CATEGORY_2_8197F \
+ (BIT_MASK_RXFILTER_CATEGORY_2_8197F \
+ << BIT_SHIFT_RXFILTER_CATEGORY_2_8197F)
+#define BIT_CLEAR_RXFILTER_CATEGORY_2_8197F(x) \
+ ((x) & (~BITS_RXFILTER_CATEGORY_2_8197F))
+#define BIT_GET_RXFILTER_CATEGORY_2_8197F(x) \
+ (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8197F) & \
+ BIT_MASK_RXFILTER_CATEGORY_2_8197F)
+#define BIT_SET_RXFILTER_CATEGORY_2_8197F(x, v) \
+ (BIT_CLEAR_RXFILTER_CATEGORY_2_8197F(x) | \
+ BIT_RXFILTER_CATEGORY_2_8197F(v))
+
+/* 2 REG_RXFLTMAP4_8197F (RX FILTER MAP GROUP 4) */
+#define BIT_CTRLFLT15EN_FW_8197F BIT(15)
+#define BIT_CTRLFLT14EN_FW_8197F BIT(14)
+#define BIT_CTRLFLT13EN_FW_8197F BIT(13)
+#define BIT_CTRLFLT12EN_FW_8197F BIT(12)
+#define BIT_CTRLFLT11EN_FW_8197F BIT(11)
+#define BIT_CTRLFLT10EN_FW_8197F BIT(10)
+#define BIT_CTRLFLT9EN_FW_8197F BIT(9)
+#define BIT_CTRLFLT8EN_FW_8197F BIT(8)
+#define BIT_CTRLFLT7EN_FW_8197F BIT(7)
+#define BIT_CTRLFLT6EN_FW_8197F BIT(6)
+#define BIT_CTRLFLT5EN_FW_8197F BIT(5)
+#define BIT_CTRLFLT4EN_FW_8197F BIT(4)
+#define BIT_CTRLFLT3EN_FW_8197F BIT(3)
+#define BIT_CTRLFLT2EN_FW_8197F BIT(2)
+#define BIT_CTRLFLT1EN_FW_8197F BIT(1)
+#define BIT_CTRLFLT0EN_FW_8197F BIT(0)
+
+/* 2 REG_RXFLTMAP3_8197F (RX FILTER MAP GROUP 3) */
+#define BIT_MGTFLT15EN_FW_8197F BIT(15)
+#define BIT_MGTFLT14EN_FW_8197F BIT(14)
+#define BIT_MGTFLT13EN_FW_8197F BIT(13)
+#define BIT_MGTFLT12EN_FW_8197F BIT(12)
+#define BIT_MGTFLT11EN_FW_8197F BIT(11)
+#define BIT_MGTFLT10EN_FW_8197F BIT(10)
+#define BIT_MGTFLT9EN_FW_8197F BIT(9)
+#define BIT_MGTFLT8EN_FW_8197F BIT(8)
+#define BIT_MGTFLT7EN_FW_8197F BIT(7)
+#define BIT_MGTFLT6EN_FW_8197F BIT(6)
+#define BIT_MGTFLT5EN_FW_8197F BIT(5)
+#define BIT_MGTFLT4EN_FW_8197F BIT(4)
+#define BIT_MGTFLT3EN_FW_8197F BIT(3)
+#define BIT_MGTFLT2EN_FW_8197F BIT(2)
+#define BIT_MGTFLT1EN_FW_8197F BIT(1)
+#define BIT_MGTFLT0EN_FW_8197F BIT(0)
+
+/* 2 REG_RXFLTMAP6_8197F (RX FILTER MAP GROUP 3) */
+#define BIT_ACTIONFLT15EN_FW_8197F BIT(15)
+#define BIT_ACTIONFLT14EN_FW_8197F BIT(14)
+#define BIT_ACTIONFLT13EN_FW_8197F BIT(13)
+#define BIT_ACTIONFLT12EN_FW_8197F BIT(12)
+#define BIT_ACTIONFLT11EN_FW_8197F BIT(11)
+#define BIT_ACTIONFLT10EN_FW_8197F BIT(10)
+#define BIT_ACTIONFLT9EN_FW_8197F BIT(9)
+#define BIT_ACTIONFLT8EN_FW_8197F BIT(8)
+#define BIT_ACTIONFLT7EN_FW_8197F BIT(7)
+#define BIT_ACTIONFLT6EN_FW_8197F BIT(6)
+#define BIT_ACTIONFLT5EN_FW_8197F BIT(5)
+#define BIT_ACTIONFLT4EN_FW_8197F BIT(4)
+#define BIT_ACTIONFLT3EN_FW_8197F BIT(3)
+#define BIT_ACTIONFLT2EN_FW_8197F BIT(2)
+#define BIT_ACTIONFLT1EN_FW_8197F BIT(1)
+#define BIT_ACTIONFLT0EN_FW_8197F BIT(0)
+
+/* 2 REG_RXFLTMAP5_8197F (RX FILTER MAP GROUP 3) */
+#define BIT_DATAFLT15EN_FW_8197F BIT(15)
+#define BIT_DATAFLT14EN_FW_8197F BIT(14)
+#define BIT_DATAFLT13EN_FW_8197F BIT(13)
+#define BIT_DATAFLT12EN_FW_8197F BIT(12)
+#define BIT_DATAFLT11EN_FW_8197F BIT(11)
+#define BIT_DATAFLT10EN_FW_8197F BIT(10)
+#define BIT_DATAFLT9EN_FW_8197F BIT(9)
+#define BIT_DATAFLT8EN_FW_8197F BIT(8)
+#define BIT_DATAFLT7EN_FW_8197F BIT(7)
+#define BIT_DATAFLT6EN_FW_8197F BIT(6)
+#define BIT_DATAFLT5EN_FW_8197F BIT(5)
+#define BIT_DATAFLT4EN_FW_8197F BIT(4)
+#define BIT_DATAFLT3EN_FW_8197F BIT(3)
+#define BIT_DATAFLT2EN_FW_8197F BIT(2)
+#define BIT_DATAFLT1EN_FW_8197F BIT(1)
+#define BIT_DATAFLT0EN_FW_8197F BIT(0)
+
+/* 2 REG_WMMPS_UAPSD_TID_8197F (WMM POWER SAVE UAPSD TID REGISTER) */
+#define BIT_WMMPS_UAPSD_TID7_8197F BIT(7)
+#define BIT_WMMPS_UAPSD_TID6_8197F BIT(6)
+#define BIT_WMMPS_UAPSD_TID5_8197F BIT(5)
+#define BIT_WMMPS_UAPSD_TID4_8197F BIT(4)
+#define BIT_WMMPS_UAPSD_TID3_8197F BIT(3)
+#define BIT_WMMPS_UAPSD_TID2_8197F BIT(2)
+#define BIT_WMMPS_UAPSD_TID1_8197F BIT(1)
+#define BIT_WMMPS_UAPSD_TID0_8197F BIT(0)
+
+/* 2 REG_PS_RX_INFO_8197F (POWER SAVE RX INFORMATION REGISTER) */
+
+#define BIT_SHIFT_PORTSEL__PS_RX_INFO_8197F 5
+#define BIT_MASK_PORTSEL__PS_RX_INFO_8197F 0x7
+#define BIT_PORTSEL__PS_RX_INFO_8197F(x) \
+ (((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8197F) \
+ << BIT_SHIFT_PORTSEL__PS_RX_INFO_8197F)
+#define BITS_PORTSEL__PS_RX_INFO_8197F \
+ (BIT_MASK_PORTSEL__PS_RX_INFO_8197F \
+ << BIT_SHIFT_PORTSEL__PS_RX_INFO_8197F)
+#define BIT_CLEAR_PORTSEL__PS_RX_INFO_8197F(x) \
+ ((x) & (~BITS_PORTSEL__PS_RX_INFO_8197F))
+#define BIT_GET_PORTSEL__PS_RX_INFO_8197F(x) \
+ (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8197F) & \
+ BIT_MASK_PORTSEL__PS_RX_INFO_8197F)
+#define BIT_SET_PORTSEL__PS_RX_INFO_8197F(x, v) \
+ (BIT_CLEAR_PORTSEL__PS_RX_INFO_8197F(x) | \
+ BIT_PORTSEL__PS_RX_INFO_8197F(v))
+
+#define BIT_RXCTRLIN0_8197F BIT(4)
+#define BIT_RXMGTIN0_8197F BIT(3)
+#define BIT_RXDATAIN2_8197F BIT(2)
+#define BIT_RXDATAIN1_8197F BIT(1)
+#define BIT_RXDATAIN0_8197F BIT(0)
+
+/* 2 REG_NOT_VALID_8197F */
+#define BIT_CHK_TSF_TA_8197F BIT(2)
+#define BIT_CHK_TSF_CBSSID_8197F BIT(1)
+#define BIT_CHK_TSF_EN_8197F BIT(0)
+
+/* 2 REG_WOW_CTRL_8197F (WAKE ON WLAN CONTROL REGISTER) */
+
+#define BIT_SHIFT_PSF_BSSIDSEL_B2B1_8197F 6
+#define BIT_MASK_PSF_BSSIDSEL_B2B1_8197F 0x3
+#define BIT_PSF_BSSIDSEL_B2B1_8197F(x) \
+ (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8197F) \
+ << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8197F)
+#define BITS_PSF_BSSIDSEL_B2B1_8197F \
+ (BIT_MASK_PSF_BSSIDSEL_B2B1_8197F << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8197F)
+#define BIT_CLEAR_PSF_BSSIDSEL_B2B1_8197F(x) \
+ ((x) & (~BITS_PSF_BSSIDSEL_B2B1_8197F))
+#define BIT_GET_PSF_BSSIDSEL_B2B1_8197F(x) \
+ (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8197F) & \
+ BIT_MASK_PSF_BSSIDSEL_B2B1_8197F)
+#define BIT_SET_PSF_BSSIDSEL_B2B1_8197F(x, v) \
+ (BIT_CLEAR_PSF_BSSIDSEL_B2B1_8197F(x) | BIT_PSF_BSSIDSEL_B2B1_8197F(v))
+
+#define BIT_WOWHCI_8197F BIT(5)
+#define BIT_PSF_BSSIDSEL_B0_8197F BIT(4)
+#define BIT_UWF_8197F BIT(3)
+#define BIT_MAGIC_8197F BIT(2)
+#define BIT_WOWEN_8197F BIT(1)
+#define BIT_FORCE_WAKEUP_8197F BIT(0)
+
+/* 2 REG_LPNAV_CTRL_8197F (LOW POWER NAV CONTROL REGISTER) */
+#define BIT_LPNAV_EN_8197F BIT(31)
+
+#define BIT_SHIFT_LPNAV_EARLY_8197F 16
+#define BIT_MASK_LPNAV_EARLY_8197F 0x7fff
+#define BIT_LPNAV_EARLY_8197F(x) \
+ (((x) & BIT_MASK_LPNAV_EARLY_8197F) << BIT_SHIFT_LPNAV_EARLY_8197F)
+#define BITS_LPNAV_EARLY_8197F \
+ (BIT_MASK_LPNAV_EARLY_8197F << BIT_SHIFT_LPNAV_EARLY_8197F)
+#define BIT_CLEAR_LPNAV_EARLY_8197F(x) ((x) & (~BITS_LPNAV_EARLY_8197F))
+#define BIT_GET_LPNAV_EARLY_8197F(x) \
+ (((x) >> BIT_SHIFT_LPNAV_EARLY_8197F) & BIT_MASK_LPNAV_EARLY_8197F)
+#define BIT_SET_LPNAV_EARLY_8197F(x, v) \
+ (BIT_CLEAR_LPNAV_EARLY_8197F(x) | BIT_LPNAV_EARLY_8197F(v))
+
+#define BIT_SHIFT_LPNAV_TH_8197F 0
+#define BIT_MASK_LPNAV_TH_8197F 0xffff
+#define BIT_LPNAV_TH_8197F(x) \
+ (((x) & BIT_MASK_LPNAV_TH_8197F) << BIT_SHIFT_LPNAV_TH_8197F)
+#define BITS_LPNAV_TH_8197F \
+ (BIT_MASK_LPNAV_TH_8197F << BIT_SHIFT_LPNAV_TH_8197F)
+#define BIT_CLEAR_LPNAV_TH_8197F(x) ((x) & (~BITS_LPNAV_TH_8197F))
+#define BIT_GET_LPNAV_TH_8197F(x) \
+ (((x) >> BIT_SHIFT_LPNAV_TH_8197F) & BIT_MASK_LPNAV_TH_8197F)
+#define BIT_SET_LPNAV_TH_8197F(x, v) \
+ (BIT_CLEAR_LPNAV_TH_8197F(x) | BIT_LPNAV_TH_8197F(v))
+
+/* 2 REG_WKFMCAM_CMD_8197F (WAKEUP FRAME CAM COMMAND REGISTER) */
+#define BIT_WKFCAM_POLLING_V1_8197F BIT(31)
+#define BIT_WKFCAM_CLR_V1_8197F BIT(30)
+#define BIT_WKFCAM_WE_8197F BIT(16)
+
+#define BIT_SHIFT_WKFCAM_ADDR_V2_8197F 8
+#define BIT_MASK_WKFCAM_ADDR_V2_8197F 0xff
+#define BIT_WKFCAM_ADDR_V2_8197F(x) \
+ (((x) & BIT_MASK_WKFCAM_ADDR_V2_8197F) \
+ << BIT_SHIFT_WKFCAM_ADDR_V2_8197F)
+#define BITS_WKFCAM_ADDR_V2_8197F \
+ (BIT_MASK_WKFCAM_ADDR_V2_8197F << BIT_SHIFT_WKFCAM_ADDR_V2_8197F)
+#define BIT_CLEAR_WKFCAM_ADDR_V2_8197F(x) ((x) & (~BITS_WKFCAM_ADDR_V2_8197F))
+#define BIT_GET_WKFCAM_ADDR_V2_8197F(x) \
+ (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2_8197F) & \
+ BIT_MASK_WKFCAM_ADDR_V2_8197F)
+#define BIT_SET_WKFCAM_ADDR_V2_8197F(x, v) \
+ (BIT_CLEAR_WKFCAM_ADDR_V2_8197F(x) | BIT_WKFCAM_ADDR_V2_8197F(v))
+
+#define BIT_SHIFT_WKFCAM_CAM_NUM_V1_8197F 0
+#define BIT_MASK_WKFCAM_CAM_NUM_V1_8197F 0xff
+#define BIT_WKFCAM_CAM_NUM_V1_8197F(x) \
+ (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1_8197F) \
+ << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8197F)
+#define BITS_WKFCAM_CAM_NUM_V1_8197F \
+ (BIT_MASK_WKFCAM_CAM_NUM_V1_8197F << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8197F)
+#define BIT_CLEAR_WKFCAM_CAM_NUM_V1_8197F(x) \
+ ((x) & (~BITS_WKFCAM_CAM_NUM_V1_8197F))
+#define BIT_GET_WKFCAM_CAM_NUM_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8197F) & \
+ BIT_MASK_WKFCAM_CAM_NUM_V1_8197F)
+#define BIT_SET_WKFCAM_CAM_NUM_V1_8197F(x, v) \
+ (BIT_CLEAR_WKFCAM_CAM_NUM_V1_8197F(x) | BIT_WKFCAM_CAM_NUM_V1_8197F(v))
+
+/* 2 REG_WKFMCAM_RWD_8197F (WAKEUP FRAME READ/WRITE DATA) */
+
+#define BIT_SHIFT_WKFMCAM_RWD_8197F 0
+#define BIT_MASK_WKFMCAM_RWD_8197F 0xffffffffL
+#define BIT_WKFMCAM_RWD_8197F(x) \
+ (((x) & BIT_MASK_WKFMCAM_RWD_8197F) << BIT_SHIFT_WKFMCAM_RWD_8197F)
+#define BITS_WKFMCAM_RWD_8197F \
+ (BIT_MASK_WKFMCAM_RWD_8197F << BIT_SHIFT_WKFMCAM_RWD_8197F)
+#define BIT_CLEAR_WKFMCAM_RWD_8197F(x) ((x) & (~BITS_WKFMCAM_RWD_8197F))
+#define BIT_GET_WKFMCAM_RWD_8197F(x) \
+ (((x) >> BIT_SHIFT_WKFMCAM_RWD_8197F) & BIT_MASK_WKFMCAM_RWD_8197F)
+#define BIT_SET_WKFMCAM_RWD_8197F(x, v) \
+ (BIT_CLEAR_WKFMCAM_RWD_8197F(x) | BIT_WKFMCAM_RWD_8197F(v))
+
+/* 2 REG_RXFLTMAP1_8197F (RX FILTER MAP GROUP 1) */
+#define BIT_CTRLFLT15EN_8197F BIT(15)
+#define BIT_CTRLFLT14EN_8197F BIT(14)
+#define BIT_CTRLFLT13EN_8197F BIT(13)
+#define BIT_CTRLFLT12EN_8197F BIT(12)
+#define BIT_CTRLFLT11EN_8197F BIT(11)
+#define BIT_CTRLFLT10EN_8197F BIT(10)
+#define BIT_CTRLFLT9EN_8197F BIT(9)
+#define BIT_CTRLFLT8EN_8197F BIT(8)
+#define BIT_CTRLFLT7EN_8197F BIT(7)
+#define BIT_CTRLFLT6EN_8197F BIT(6)
+#define BIT_CTRLFLT5EN_8197F BIT(5)
+#define BIT_CTRLFLT4EN_8197F BIT(4)
+#define BIT_CTRLFLT3EN_8197F BIT(3)
+#define BIT_CTRLFLT2EN_8197F BIT(2)
+#define BIT_CTRLFLT1EN_8197F BIT(1)
+#define BIT_CTRLFLT0EN_8197F BIT(0)
+
+/* 2 REG_RXFLTMAP0_8197F (RX FILTER MAP GROUP 0) */
+#define BIT_MGTFLT15EN_8197F BIT(15)
+#define BIT_MGTFLT14EN_8197F BIT(14)
+#define BIT_MGTFLT13EN_8197F BIT(13)
+#define BIT_MGTFLT12EN_8197F BIT(12)
+#define BIT_MGTFLT11EN_8197F BIT(11)
+#define BIT_MGTFLT10EN_8197F BIT(10)
+#define BIT_MGTFLT9EN_8197F BIT(9)
+#define BIT_MGTFLT8EN_8197F BIT(8)
+#define BIT_MGTFLT7EN_8197F BIT(7)
+#define BIT_MGTFLT6EN_8197F BIT(6)
+#define BIT_MGTFLT5EN_8197F BIT(5)
+#define BIT_MGTFLT4EN_8197F BIT(4)
+#define BIT_MGTFLT3EN_8197F BIT(3)
+#define BIT_MGTFLT2EN_8197F BIT(2)
+#define BIT_MGTFLT1EN_8197F BIT(1)
+#define BIT_MGTFLT0EN_8197F BIT(0)
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_RXFLTMAP_8197F (RX FILTER MAP GROUP 2) */
+#define BIT_DATAFLT15EN_8197F BIT(15)
+#define BIT_DATAFLT14EN_8197F BIT(14)
+#define BIT_DATAFLT13EN_8197F BIT(13)
+#define BIT_DATAFLT12EN_8197F BIT(12)
+#define BIT_DATAFLT11EN_8197F BIT(11)
+#define BIT_DATAFLT10EN_8197F BIT(10)
+#define BIT_DATAFLT9EN_8197F BIT(9)
+#define BIT_DATAFLT8EN_8197F BIT(8)
+#define BIT_DATAFLT7EN_8197F BIT(7)
+#define BIT_DATAFLT6EN_8197F BIT(6)
+#define BIT_DATAFLT5EN_8197F BIT(5)
+#define BIT_DATAFLT4EN_8197F BIT(4)
+#define BIT_DATAFLT3EN_8197F BIT(3)
+#define BIT_DATAFLT2EN_8197F BIT(2)
+#define BIT_DATAFLT1EN_8197F BIT(1)
+#define BIT_DATAFLT0EN_8197F BIT(0)
+
+/* 2 REG_BCN_PSR_RPT_8197F (BEACON PARSER REPORT REGISTER) */
+
+#define BIT_SHIFT_DTIM_CNT_8197F 24
+#define BIT_MASK_DTIM_CNT_8197F 0xff
+#define BIT_DTIM_CNT_8197F(x) \
+ (((x) & BIT_MASK_DTIM_CNT_8197F) << BIT_SHIFT_DTIM_CNT_8197F)
+#define BITS_DTIM_CNT_8197F \
+ (BIT_MASK_DTIM_CNT_8197F << BIT_SHIFT_DTIM_CNT_8197F)
+#define BIT_CLEAR_DTIM_CNT_8197F(x) ((x) & (~BITS_DTIM_CNT_8197F))
+#define BIT_GET_DTIM_CNT_8197F(x) \
+ (((x) >> BIT_SHIFT_DTIM_CNT_8197F) & BIT_MASK_DTIM_CNT_8197F)
+#define BIT_SET_DTIM_CNT_8197F(x, v) \
+ (BIT_CLEAR_DTIM_CNT_8197F(x) | BIT_DTIM_CNT_8197F(v))
+
+#define BIT_SHIFT_DTIM_PERIOD_8197F 16
+#define BIT_MASK_DTIM_PERIOD_8197F 0xff
+#define BIT_DTIM_PERIOD_8197F(x) \
+ (((x) & BIT_MASK_DTIM_PERIOD_8197F) << BIT_SHIFT_DTIM_PERIOD_8197F)
+#define BITS_DTIM_PERIOD_8197F \
+ (BIT_MASK_DTIM_PERIOD_8197F << BIT_SHIFT_DTIM_PERIOD_8197F)
+#define BIT_CLEAR_DTIM_PERIOD_8197F(x) ((x) & (~BITS_DTIM_PERIOD_8197F))
+#define BIT_GET_DTIM_PERIOD_8197F(x) \
+ (((x) >> BIT_SHIFT_DTIM_PERIOD_8197F) & BIT_MASK_DTIM_PERIOD_8197F)
+#define BIT_SET_DTIM_PERIOD_8197F(x, v) \
+ (BIT_CLEAR_DTIM_PERIOD_8197F(x) | BIT_DTIM_PERIOD_8197F(v))
+
+#define BIT_DTIM_8197F BIT(15)
+#define BIT_TIM_8197F BIT(14)
+
+#define BIT_SHIFT_PS_AID_0_8197F 0
+#define BIT_MASK_PS_AID_0_8197F 0x7ff
+#define BIT_PS_AID_0_8197F(x) \
+ (((x) & BIT_MASK_PS_AID_0_8197F) << BIT_SHIFT_PS_AID_0_8197F)
+#define BITS_PS_AID_0_8197F \
+ (BIT_MASK_PS_AID_0_8197F << BIT_SHIFT_PS_AID_0_8197F)
+#define BIT_CLEAR_PS_AID_0_8197F(x) ((x) & (~BITS_PS_AID_0_8197F))
+#define BIT_GET_PS_AID_0_8197F(x) \
+ (((x) >> BIT_SHIFT_PS_AID_0_8197F) & BIT_MASK_PS_AID_0_8197F)
+#define BIT_SET_PS_AID_0_8197F(x, v) \
+ (BIT_CLEAR_PS_AID_0_8197F(x) | BIT_PS_AID_0_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+#define BIT_FLC_RPCT_V1_8197F BIT(7)
+#define BIT_MODE_8197F BIT(6)
+
+#define BIT_SHIFT_TRPCD_8197F 0
+#define BIT_MASK_TRPCD_8197F 0x3f
+#define BIT_TRPCD_8197F(x) \
+ (((x) & BIT_MASK_TRPCD_8197F) << BIT_SHIFT_TRPCD_8197F)
+#define BITS_TRPCD_8197F (BIT_MASK_TRPCD_8197F << BIT_SHIFT_TRPCD_8197F)
+#define BIT_CLEAR_TRPCD_8197F(x) ((x) & (~BITS_TRPCD_8197F))
+#define BIT_GET_TRPCD_8197F(x) \
+ (((x) >> BIT_SHIFT_TRPCD_8197F) & BIT_MASK_TRPCD_8197F)
+#define BIT_SET_TRPCD_8197F(x, v) \
+ (BIT_CLEAR_TRPCD_8197F(x) | BIT_TRPCD_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+#define BIT_CMF_8197F BIT(2)
+#define BIT_CCF_8197F BIT(1)
+#define BIT_CDF_8197F BIT(0)
+
+/* 2 REG_NOT_VALID_8197F */
+
+#define BIT_SHIFT_FLC_RPCT_8197F 0
+#define BIT_MASK_FLC_RPCT_8197F 0xff
+#define BIT_FLC_RPCT_8197F(x) \
+ (((x) & BIT_MASK_FLC_RPCT_8197F) << BIT_SHIFT_FLC_RPCT_8197F)
+#define BITS_FLC_RPCT_8197F \
+ (BIT_MASK_FLC_RPCT_8197F << BIT_SHIFT_FLC_RPCT_8197F)
+#define BIT_CLEAR_FLC_RPCT_8197F(x) ((x) & (~BITS_FLC_RPCT_8197F))
+#define BIT_GET_FLC_RPCT_8197F(x) \
+ (((x) >> BIT_SHIFT_FLC_RPCT_8197F) & BIT_MASK_FLC_RPCT_8197F)
+#define BIT_SET_FLC_RPCT_8197F(x, v) \
+ (BIT_CLEAR_FLC_RPCT_8197F(x) | BIT_FLC_RPCT_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+#define BIT_SHIFT_FLC_RPC_8197F 0
+#define BIT_MASK_FLC_RPC_8197F 0xff
+#define BIT_FLC_RPC_8197F(x) \
+ (((x) & BIT_MASK_FLC_RPC_8197F) << BIT_SHIFT_FLC_RPC_8197F)
+#define BITS_FLC_RPC_8197F (BIT_MASK_FLC_RPC_8197F << BIT_SHIFT_FLC_RPC_8197F)
+#define BIT_CLEAR_FLC_RPC_8197F(x) ((x) & (~BITS_FLC_RPC_8197F))
+#define BIT_GET_FLC_RPC_8197F(x) \
+ (((x) >> BIT_SHIFT_FLC_RPC_8197F) & BIT_MASK_FLC_RPC_8197F)
+#define BIT_SET_FLC_RPC_8197F(x, v) \
+ (BIT_CLEAR_FLC_RPC_8197F(x) | BIT_FLC_RPC_8197F(v))
+
+/* 2 REG_RXPKTMON_CTRL_8197F */
+
+#define BIT_SHIFT_RXBKQPKT_SEQ_8197F 20
+#define BIT_MASK_RXBKQPKT_SEQ_8197F 0xf
+#define BIT_RXBKQPKT_SEQ_8197F(x) \
+ (((x) & BIT_MASK_RXBKQPKT_SEQ_8197F) << BIT_SHIFT_RXBKQPKT_SEQ_8197F)
+#define BITS_RXBKQPKT_SEQ_8197F \
+ (BIT_MASK_RXBKQPKT_SEQ_8197F << BIT_SHIFT_RXBKQPKT_SEQ_8197F)
+#define BIT_CLEAR_RXBKQPKT_SEQ_8197F(x) ((x) & (~BITS_RXBKQPKT_SEQ_8197F))
+#define BIT_GET_RXBKQPKT_SEQ_8197F(x) \
+ (((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8197F) & BIT_MASK_RXBKQPKT_SEQ_8197F)
+#define BIT_SET_RXBKQPKT_SEQ_8197F(x, v) \
+ (BIT_CLEAR_RXBKQPKT_SEQ_8197F(x) | BIT_RXBKQPKT_SEQ_8197F(v))
+
+#define BIT_SHIFT_RXBEQPKT_SEQ_8197F 16
+#define BIT_MASK_RXBEQPKT_SEQ_8197F 0xf
+#define BIT_RXBEQPKT_SEQ_8197F(x) \
+ (((x) & BIT_MASK_RXBEQPKT_SEQ_8197F) << BIT_SHIFT_RXBEQPKT_SEQ_8197F)
+#define BITS_RXBEQPKT_SEQ_8197F \
+ (BIT_MASK_RXBEQPKT_SEQ_8197F << BIT_SHIFT_RXBEQPKT_SEQ_8197F)
+#define BIT_CLEAR_RXBEQPKT_SEQ_8197F(x) ((x) & (~BITS_RXBEQPKT_SEQ_8197F))
+#define BIT_GET_RXBEQPKT_SEQ_8197F(x) \
+ (((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8197F) & BIT_MASK_RXBEQPKT_SEQ_8197F)
+#define BIT_SET_RXBEQPKT_SEQ_8197F(x, v) \
+ (BIT_CLEAR_RXBEQPKT_SEQ_8197F(x) | BIT_RXBEQPKT_SEQ_8197F(v))
+
+#define BIT_SHIFT_RXVIQPKT_SEQ_8197F 12
+#define BIT_MASK_RXVIQPKT_SEQ_8197F 0xf
+#define BIT_RXVIQPKT_SEQ_8197F(x) \
+ (((x) & BIT_MASK_RXVIQPKT_SEQ_8197F) << BIT_SHIFT_RXVIQPKT_SEQ_8197F)
+#define BITS_RXVIQPKT_SEQ_8197F \
+ (BIT_MASK_RXVIQPKT_SEQ_8197F << BIT_SHIFT_RXVIQPKT_SEQ_8197F)
+#define BIT_CLEAR_RXVIQPKT_SEQ_8197F(x) ((x) & (~BITS_RXVIQPKT_SEQ_8197F))
+#define BIT_GET_RXVIQPKT_SEQ_8197F(x) \
+ (((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8197F) & BIT_MASK_RXVIQPKT_SEQ_8197F)
+#define BIT_SET_RXVIQPKT_SEQ_8197F(x, v) \
+ (BIT_CLEAR_RXVIQPKT_SEQ_8197F(x) | BIT_RXVIQPKT_SEQ_8197F(v))
+
+#define BIT_SHIFT_RXVOQPKT_SEQ_8197F 8
+#define BIT_MASK_RXVOQPKT_SEQ_8197F 0xf
+#define BIT_RXVOQPKT_SEQ_8197F(x) \
+ (((x) & BIT_MASK_RXVOQPKT_SEQ_8197F) << BIT_SHIFT_RXVOQPKT_SEQ_8197F)
+#define BITS_RXVOQPKT_SEQ_8197F \
+ (BIT_MASK_RXVOQPKT_SEQ_8197F << BIT_SHIFT_RXVOQPKT_SEQ_8197F)
+#define BIT_CLEAR_RXVOQPKT_SEQ_8197F(x) ((x) & (~BITS_RXVOQPKT_SEQ_8197F))
+#define BIT_GET_RXVOQPKT_SEQ_8197F(x) \
+ (((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8197F) & BIT_MASK_RXVOQPKT_SEQ_8197F)
+#define BIT_SET_RXVOQPKT_SEQ_8197F(x, v) \
+ (BIT_CLEAR_RXVOQPKT_SEQ_8197F(x) | BIT_RXVOQPKT_SEQ_8197F(v))
+
+#define BIT_RXBKQPKT_ERR_8197F BIT(7)
+#define BIT_RXBEQPKT_ERR_8197F BIT(6)
+#define BIT_RXVIQPKT_ERR_8197F BIT(5)
+#define BIT_RXVOQPKT_ERR_8197F BIT(4)
+#define BIT_RXDMA_MON_EN_8197F BIT(2)
+#define BIT_RXPKT_MON_RST_8197F BIT(1)
+#define BIT_RXPKT_MON_EN_8197F BIT(0)
+
+/* 2 REG_STATE_MON_8197F */
+
+#define BIT_SHIFT_STATE_SEL_8197F 24
+#define BIT_MASK_STATE_SEL_8197F 0x1f
+#define BIT_STATE_SEL_8197F(x) \
+ (((x) & BIT_MASK_STATE_SEL_8197F) << BIT_SHIFT_STATE_SEL_8197F)
+#define BITS_STATE_SEL_8197F \
+ (BIT_MASK_STATE_SEL_8197F << BIT_SHIFT_STATE_SEL_8197F)
+#define BIT_CLEAR_STATE_SEL_8197F(x) ((x) & (~BITS_STATE_SEL_8197F))
+#define BIT_GET_STATE_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_STATE_SEL_8197F) & BIT_MASK_STATE_SEL_8197F)
+#define BIT_SET_STATE_SEL_8197F(x, v) \
+ (BIT_CLEAR_STATE_SEL_8197F(x) | BIT_STATE_SEL_8197F(v))
+
+#define BIT_SHIFT_STATE_INFO_8197F 8
+#define BIT_MASK_STATE_INFO_8197F 0xff
+#define BIT_STATE_INFO_8197F(x) \
+ (((x) & BIT_MASK_STATE_INFO_8197F) << BIT_SHIFT_STATE_INFO_8197F)
+#define BITS_STATE_INFO_8197F \
+ (BIT_MASK_STATE_INFO_8197F << BIT_SHIFT_STATE_INFO_8197F)
+#define BIT_CLEAR_STATE_INFO_8197F(x) ((x) & (~BITS_STATE_INFO_8197F))
+#define BIT_GET_STATE_INFO_8197F(x) \
+ (((x) >> BIT_SHIFT_STATE_INFO_8197F) & BIT_MASK_STATE_INFO_8197F)
+#define BIT_SET_STATE_INFO_8197F(x, v) \
+ (BIT_CLEAR_STATE_INFO_8197F(x) | BIT_STATE_INFO_8197F(v))
+
+#define BIT_UPD_NXT_STATE_8197F BIT(7)
+
+#define BIT_SHIFT_CUR_STATE_8197F 0
+#define BIT_MASK_CUR_STATE_8197F 0x7f
+#define BIT_CUR_STATE_8197F(x) \
+ (((x) & BIT_MASK_CUR_STATE_8197F) << BIT_SHIFT_CUR_STATE_8197F)
+#define BITS_CUR_STATE_8197F \
+ (BIT_MASK_CUR_STATE_8197F << BIT_SHIFT_CUR_STATE_8197F)
+#define BIT_CLEAR_CUR_STATE_8197F(x) ((x) & (~BITS_CUR_STATE_8197F))
+#define BIT_GET_CUR_STATE_8197F(x) \
+ (((x) >> BIT_SHIFT_CUR_STATE_8197F) & BIT_MASK_CUR_STATE_8197F)
+#define BIT_SET_CUR_STATE_8197F(x, v) \
+ (BIT_CLEAR_CUR_STATE_8197F(x) | BIT_CUR_STATE_8197F(v))
+
+/* 2 REG_ERROR_MON_8197F */
+#define BIT_MACRX_ERR_1_8197F BIT(17)
+#define BIT_MACRX_ERR_0_8197F BIT(16)
+#define BIT_MACTX_ERR_3_8197F BIT(3)
+#define BIT_MACTX_ERR_2_8197F BIT(2)
+#define BIT_MACTX_ERR_1_8197F BIT(1)
+#define BIT_MACTX_ERR_0_8197F BIT(0)
+
+/* 2 REG_SEARCH_MACID_8197F */
+#define BIT_EN_TXRPTBUF_CLK_8197F BIT(31)
+
+#define BIT_SHIFT_INFO_INDEX_OFFSET_8197F 16
+#define BIT_MASK_INFO_INDEX_OFFSET_8197F 0x1fff
+#define BIT_INFO_INDEX_OFFSET_8197F(x) \
+ (((x) & BIT_MASK_INFO_INDEX_OFFSET_8197F) \
+ << BIT_SHIFT_INFO_INDEX_OFFSET_8197F)
+#define BITS_INFO_INDEX_OFFSET_8197F \
+ (BIT_MASK_INFO_INDEX_OFFSET_8197F << BIT_SHIFT_INFO_INDEX_OFFSET_8197F)
+#define BIT_CLEAR_INFO_INDEX_OFFSET_8197F(x) \
+ ((x) & (~BITS_INFO_INDEX_OFFSET_8197F))
+#define BIT_GET_INFO_INDEX_OFFSET_8197F(x) \
+ (((x) >> BIT_SHIFT_INFO_INDEX_OFFSET_8197F) & \
+ BIT_MASK_INFO_INDEX_OFFSET_8197F)
+#define BIT_SET_INFO_INDEX_OFFSET_8197F(x, v) \
+ (BIT_CLEAR_INFO_INDEX_OFFSET_8197F(x) | BIT_INFO_INDEX_OFFSET_8197F(v))
+
+#define BIT_DIS_INFOSRCH_8197F BIT(14)
+#define BIT_DISABLE_B0_8197F BIT(13)
+
+#define BIT_SHIFT_INFO_ADDR_OFFSET_8197F 0
+#define BIT_MASK_INFO_ADDR_OFFSET_8197F 0x1fff
+#define BIT_INFO_ADDR_OFFSET_8197F(x) \
+ (((x) & BIT_MASK_INFO_ADDR_OFFSET_8197F) \
+ << BIT_SHIFT_INFO_ADDR_OFFSET_8197F)
+#define BITS_INFO_ADDR_OFFSET_8197F \
+ (BIT_MASK_INFO_ADDR_OFFSET_8197F << BIT_SHIFT_INFO_ADDR_OFFSET_8197F)
+#define BIT_CLEAR_INFO_ADDR_OFFSET_8197F(x) \
+ ((x) & (~BITS_INFO_ADDR_OFFSET_8197F))
+#define BIT_GET_INFO_ADDR_OFFSET_8197F(x) \
+ (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8197F) & \
+ BIT_MASK_INFO_ADDR_OFFSET_8197F)
+#define BIT_SET_INFO_ADDR_OFFSET_8197F(x, v) \
+ (BIT_CLEAR_INFO_ADDR_OFFSET_8197F(x) | BIT_INFO_ADDR_OFFSET_8197F(v))
+
+/* 2 REG_BT_COEX_TABLE_8197F (BT-COEXISTENCE CONTROL REGISTER) */
+#define BIT_PRI_MASK_RX_RESP_8197F BIT(126)
+#define BIT_PRI_MASK_RXOFDM_8197F BIT(125)
+#define BIT_PRI_MASK_RXCCK_8197F BIT(124)
+
+#define BIT_SHIFT_PRI_MASK_TXAC_8197F (117 & CPU_OPT_WIDTH)
+#define BIT_MASK_PRI_MASK_TXAC_8197F 0x7f
+#define BIT_PRI_MASK_TXAC_8197F(x) \
+ (((x) & BIT_MASK_PRI_MASK_TXAC_8197F) << BIT_SHIFT_PRI_MASK_TXAC_8197F)
+#define BITS_PRI_MASK_TXAC_8197F \
+ (BIT_MASK_PRI_MASK_TXAC_8197F << BIT_SHIFT_PRI_MASK_TXAC_8197F)
+#define BIT_CLEAR_PRI_MASK_TXAC_8197F(x) ((x) & (~BITS_PRI_MASK_TXAC_8197F))
+#define BIT_GET_PRI_MASK_TXAC_8197F(x) \
+ (((x) >> BIT_SHIFT_PRI_MASK_TXAC_8197F) & BIT_MASK_PRI_MASK_TXAC_8197F)
+#define BIT_SET_PRI_MASK_TXAC_8197F(x, v) \
+ (BIT_CLEAR_PRI_MASK_TXAC_8197F(x) | BIT_PRI_MASK_TXAC_8197F(v))
+
+#define BIT_SHIFT_PRI_MASK_NAV_8197F (109 & CPU_OPT_WIDTH)
+#define BIT_MASK_PRI_MASK_NAV_8197F 0xff
+#define BIT_PRI_MASK_NAV_8197F(x) \
+ (((x) & BIT_MASK_PRI_MASK_NAV_8197F) << BIT_SHIFT_PRI_MASK_NAV_8197F)
+#define BITS_PRI_MASK_NAV_8197F \
+ (BIT_MASK_PRI_MASK_NAV_8197F << BIT_SHIFT_PRI_MASK_NAV_8197F)
+#define BIT_CLEAR_PRI_MASK_NAV_8197F(x) ((x) & (~BITS_PRI_MASK_NAV_8197F))
+#define BIT_GET_PRI_MASK_NAV_8197F(x) \
+ (((x) >> BIT_SHIFT_PRI_MASK_NAV_8197F) & BIT_MASK_PRI_MASK_NAV_8197F)
+#define BIT_SET_PRI_MASK_NAV_8197F(x, v) \
+ (BIT_CLEAR_PRI_MASK_NAV_8197F(x) | BIT_PRI_MASK_NAV_8197F(v))
+
+#define BIT_PRI_MASK_CCK_8197F BIT(108)
+#define BIT_PRI_MASK_OFDM_8197F BIT(107)
+#define BIT_PRI_MASK_RTY_8197F BIT(106)
+
+#define BIT_SHIFT_PRI_MASK_NUM_8197F (102 & CPU_OPT_WIDTH)
+#define BIT_MASK_PRI_MASK_NUM_8197F 0xf
+#define BIT_PRI_MASK_NUM_8197F(x) \
+ (((x) & BIT_MASK_PRI_MASK_NUM_8197F) << BIT_SHIFT_PRI_MASK_NUM_8197F)
+#define BITS_PRI_MASK_NUM_8197F \
+ (BIT_MASK_PRI_MASK_NUM_8197F << BIT_SHIFT_PRI_MASK_NUM_8197F)
+#define BIT_CLEAR_PRI_MASK_NUM_8197F(x) ((x) & (~BITS_PRI_MASK_NUM_8197F))
+#define BIT_GET_PRI_MASK_NUM_8197F(x) \
+ (((x) >> BIT_SHIFT_PRI_MASK_NUM_8197F) & BIT_MASK_PRI_MASK_NUM_8197F)
+#define BIT_SET_PRI_MASK_NUM_8197F(x, v) \
+ (BIT_CLEAR_PRI_MASK_NUM_8197F(x) | BIT_PRI_MASK_NUM_8197F(v))
+
+#define BIT_SHIFT_PRI_MASK_TYPE_8197F (98 & CPU_OPT_WIDTH)
+#define BIT_MASK_PRI_MASK_TYPE_8197F 0xf
+#define BIT_PRI_MASK_TYPE_8197F(x) \
+ (((x) & BIT_MASK_PRI_MASK_TYPE_8197F) << BIT_SHIFT_PRI_MASK_TYPE_8197F)
+#define BITS_PRI_MASK_TYPE_8197F \
+ (BIT_MASK_PRI_MASK_TYPE_8197F << BIT_SHIFT_PRI_MASK_TYPE_8197F)
+#define BIT_CLEAR_PRI_MASK_TYPE_8197F(x) ((x) & (~BITS_PRI_MASK_TYPE_8197F))
+#define BIT_GET_PRI_MASK_TYPE_8197F(x) \
+ (((x) >> BIT_SHIFT_PRI_MASK_TYPE_8197F) & BIT_MASK_PRI_MASK_TYPE_8197F)
+#define BIT_SET_PRI_MASK_TYPE_8197F(x, v) \
+ (BIT_CLEAR_PRI_MASK_TYPE_8197F(x) | BIT_PRI_MASK_TYPE_8197F(v))
+
+#define BIT_OOB_8197F BIT(97)
+#define BIT_ANT_SEL_8197F BIT(96)
+
+#define BIT_SHIFT_BREAK_TABLE_2_8197F (80 & CPU_OPT_WIDTH)
+#define BIT_MASK_BREAK_TABLE_2_8197F 0xffff
+#define BIT_BREAK_TABLE_2_8197F(x) \
+ (((x) & BIT_MASK_BREAK_TABLE_2_8197F) << BIT_SHIFT_BREAK_TABLE_2_8197F)
+#define BITS_BREAK_TABLE_2_8197F \
+ (BIT_MASK_BREAK_TABLE_2_8197F << BIT_SHIFT_BREAK_TABLE_2_8197F)
+#define BIT_CLEAR_BREAK_TABLE_2_8197F(x) ((x) & (~BITS_BREAK_TABLE_2_8197F))
+#define BIT_GET_BREAK_TABLE_2_8197F(x) \
+ (((x) >> BIT_SHIFT_BREAK_TABLE_2_8197F) & BIT_MASK_BREAK_TABLE_2_8197F)
+#define BIT_SET_BREAK_TABLE_2_8197F(x, v) \
+ (BIT_CLEAR_BREAK_TABLE_2_8197F(x) | BIT_BREAK_TABLE_2_8197F(v))
+
+#define BIT_SHIFT_BREAK_TABLE_1_8197F (64 & CPU_OPT_WIDTH)
+#define BIT_MASK_BREAK_TABLE_1_8197F 0xffff
+#define BIT_BREAK_TABLE_1_8197F(x) \
+ (((x) & BIT_MASK_BREAK_TABLE_1_8197F) << BIT_SHIFT_BREAK_TABLE_1_8197F)
+#define BITS_BREAK_TABLE_1_8197F \
+ (BIT_MASK_BREAK_TABLE_1_8197F << BIT_SHIFT_BREAK_TABLE_1_8197F)
+#define BIT_CLEAR_BREAK_TABLE_1_8197F(x) ((x) & (~BITS_BREAK_TABLE_1_8197F))
+#define BIT_GET_BREAK_TABLE_1_8197F(x) \
+ (((x) >> BIT_SHIFT_BREAK_TABLE_1_8197F) & BIT_MASK_BREAK_TABLE_1_8197F)
+#define BIT_SET_BREAK_TABLE_1_8197F(x, v) \
+ (BIT_CLEAR_BREAK_TABLE_1_8197F(x) | BIT_BREAK_TABLE_1_8197F(v))
+
+#define BIT_SHIFT_COEX_TABLE_2_8197F (32 & CPU_OPT_WIDTH)
+#define BIT_MASK_COEX_TABLE_2_8197F 0xffffffffL
+#define BIT_COEX_TABLE_2_8197F(x) \
+ (((x) & BIT_MASK_COEX_TABLE_2_8197F) << BIT_SHIFT_COEX_TABLE_2_8197F)
+#define BITS_COEX_TABLE_2_8197F \
+ (BIT_MASK_COEX_TABLE_2_8197F << BIT_SHIFT_COEX_TABLE_2_8197F)
+#define BIT_CLEAR_COEX_TABLE_2_8197F(x) ((x) & (~BITS_COEX_TABLE_2_8197F))
+#define BIT_GET_COEX_TABLE_2_8197F(x) \
+ (((x) >> BIT_SHIFT_COEX_TABLE_2_8197F) & BIT_MASK_COEX_TABLE_2_8197F)
+#define BIT_SET_COEX_TABLE_2_8197F(x, v) \
+ (BIT_CLEAR_COEX_TABLE_2_8197F(x) | BIT_COEX_TABLE_2_8197F(v))
+
+#define BIT_SHIFT_COEX_TABLE_1_8197F 0
+#define BIT_MASK_COEX_TABLE_1_8197F 0xffffffffL
+#define BIT_COEX_TABLE_1_8197F(x) \
+ (((x) & BIT_MASK_COEX_TABLE_1_8197F) << BIT_SHIFT_COEX_TABLE_1_8197F)
+#define BITS_COEX_TABLE_1_8197F \
+ (BIT_MASK_COEX_TABLE_1_8197F << BIT_SHIFT_COEX_TABLE_1_8197F)
+#define BIT_CLEAR_COEX_TABLE_1_8197F(x) ((x) & (~BITS_COEX_TABLE_1_8197F))
+#define BIT_GET_COEX_TABLE_1_8197F(x) \
+ (((x) >> BIT_SHIFT_COEX_TABLE_1_8197F) & BIT_MASK_COEX_TABLE_1_8197F)
+#define BIT_SET_COEX_TABLE_1_8197F(x, v) \
+ (BIT_CLEAR_COEX_TABLE_1_8197F(x) | BIT_COEX_TABLE_1_8197F(v))
+
+/* 2 REG_RXCMD_0_8197F */
+#define BIT_RXCMD_EN_8197F BIT(31)
+
+#define BIT_SHIFT_RXCMD_INFO_8197F 0
+#define BIT_MASK_RXCMD_INFO_8197F 0x7fffffffL
+#define BIT_RXCMD_INFO_8197F(x) \
+ (((x) & BIT_MASK_RXCMD_INFO_8197F) << BIT_SHIFT_RXCMD_INFO_8197F)
+#define BITS_RXCMD_INFO_8197F \
+ (BIT_MASK_RXCMD_INFO_8197F << BIT_SHIFT_RXCMD_INFO_8197F)
+#define BIT_CLEAR_RXCMD_INFO_8197F(x) ((x) & (~BITS_RXCMD_INFO_8197F))
+#define BIT_GET_RXCMD_INFO_8197F(x) \
+ (((x) >> BIT_SHIFT_RXCMD_INFO_8197F) & BIT_MASK_RXCMD_INFO_8197F)
+#define BIT_SET_RXCMD_INFO_8197F(x, v) \
+ (BIT_CLEAR_RXCMD_INFO_8197F(x) | BIT_RXCMD_INFO_8197F(v))
+
+/* 2 REG_RXCMD_1_8197F */
+
+#define BIT_SHIFT_RXCMD_PRD_8197F 0
+#define BIT_MASK_RXCMD_PRD_8197F 0xffff
+#define BIT_RXCMD_PRD_8197F(x) \
+ (((x) & BIT_MASK_RXCMD_PRD_8197F) << BIT_SHIFT_RXCMD_PRD_8197F)
+#define BITS_RXCMD_PRD_8197F \
+ (BIT_MASK_RXCMD_PRD_8197F << BIT_SHIFT_RXCMD_PRD_8197F)
+#define BIT_CLEAR_RXCMD_PRD_8197F(x) ((x) & (~BITS_RXCMD_PRD_8197F))
+#define BIT_GET_RXCMD_PRD_8197F(x) \
+ (((x) >> BIT_SHIFT_RXCMD_PRD_8197F) & BIT_MASK_RXCMD_PRD_8197F)
+#define BIT_SET_RXCMD_PRD_8197F(x, v) \
+ (BIT_CLEAR_RXCMD_PRD_8197F(x) | BIT_RXCMD_PRD_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_WMAC_RESP_TXINFO_8197F (RESPONSE TXINFO REGISTER) */
+
+#define BIT_SHIFT_WMAC_RESP_MFB_8197F 25
+#define BIT_MASK_WMAC_RESP_MFB_8197F 0x7f
+#define BIT_WMAC_RESP_MFB_8197F(x) \
+ (((x) & BIT_MASK_WMAC_RESP_MFB_8197F) << BIT_SHIFT_WMAC_RESP_MFB_8197F)
+#define BITS_WMAC_RESP_MFB_8197F \
+ (BIT_MASK_WMAC_RESP_MFB_8197F << BIT_SHIFT_WMAC_RESP_MFB_8197F)
+#define BIT_CLEAR_WMAC_RESP_MFB_8197F(x) ((x) & (~BITS_WMAC_RESP_MFB_8197F))
+#define BIT_GET_WMAC_RESP_MFB_8197F(x) \
+ (((x) >> BIT_SHIFT_WMAC_RESP_MFB_8197F) & BIT_MASK_WMAC_RESP_MFB_8197F)
+#define BIT_SET_WMAC_RESP_MFB_8197F(x, v) \
+ (BIT_CLEAR_WMAC_RESP_MFB_8197F(x) | BIT_WMAC_RESP_MFB_8197F(v))
+
+#define BIT_SHIFT_WMAC_ANTINF_SEL_8197F 23
+#define BIT_MASK_WMAC_ANTINF_SEL_8197F 0x3
+#define BIT_WMAC_ANTINF_SEL_8197F(x) \
+ (((x) & BIT_MASK_WMAC_ANTINF_SEL_8197F) \
+ << BIT_SHIFT_WMAC_ANTINF_SEL_8197F)
+#define BITS_WMAC_ANTINF_SEL_8197F \
+ (BIT_MASK_WMAC_ANTINF_SEL_8197F << BIT_SHIFT_WMAC_ANTINF_SEL_8197F)
+#define BIT_CLEAR_WMAC_ANTINF_SEL_8197F(x) ((x) & (~BITS_WMAC_ANTINF_SEL_8197F))
+#define BIT_GET_WMAC_ANTINF_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8197F) & \
+ BIT_MASK_WMAC_ANTINF_SEL_8197F)
+#define BIT_SET_WMAC_ANTINF_SEL_8197F(x, v) \
+ (BIT_CLEAR_WMAC_ANTINF_SEL_8197F(x) | BIT_WMAC_ANTINF_SEL_8197F(v))
+
+#define BIT_SHIFT_WMAC_ANTSEL_SEL_8197F 21
+#define BIT_MASK_WMAC_ANTSEL_SEL_8197F 0x3
+#define BIT_WMAC_ANTSEL_SEL_8197F(x) \
+ (((x) & BIT_MASK_WMAC_ANTSEL_SEL_8197F) \
+ << BIT_SHIFT_WMAC_ANTSEL_SEL_8197F)
+#define BITS_WMAC_ANTSEL_SEL_8197F \
+ (BIT_MASK_WMAC_ANTSEL_SEL_8197F << BIT_SHIFT_WMAC_ANTSEL_SEL_8197F)
+#define BIT_CLEAR_WMAC_ANTSEL_SEL_8197F(x) ((x) & (~BITS_WMAC_ANTSEL_SEL_8197F))
+#define BIT_GET_WMAC_ANTSEL_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8197F) & \
+ BIT_MASK_WMAC_ANTSEL_SEL_8197F)
+#define BIT_SET_WMAC_ANTSEL_SEL_8197F(x, v) \
+ (BIT_CLEAR_WMAC_ANTSEL_SEL_8197F(x) | BIT_WMAC_ANTSEL_SEL_8197F(v))
+
+#define BIT_SHIFT_R_WMAC_RESP_TXPOWER_8197F 18
+#define BIT_MASK_R_WMAC_RESP_TXPOWER_8197F 0x7
+#define BIT_R_WMAC_RESP_TXPOWER_8197F(x) \
+ (((x) & BIT_MASK_R_WMAC_RESP_TXPOWER_8197F) \
+ << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8197F)
+#define BITS_R_WMAC_RESP_TXPOWER_8197F \
+ (BIT_MASK_R_WMAC_RESP_TXPOWER_8197F \
+ << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8197F)
+#define BIT_CLEAR_R_WMAC_RESP_TXPOWER_8197F(x) \
+ ((x) & (~BITS_R_WMAC_RESP_TXPOWER_8197F))
+#define BIT_GET_R_WMAC_RESP_TXPOWER_8197F(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER_8197F) & \
+ BIT_MASK_R_WMAC_RESP_TXPOWER_8197F)
+#define BIT_SET_R_WMAC_RESP_TXPOWER_8197F(x, v) \
+ (BIT_CLEAR_R_WMAC_RESP_TXPOWER_8197F(x) | \
+ BIT_R_WMAC_RESP_TXPOWER_8197F(v))
+
+#define BIT_SHIFT_WMAC_RESP_TXANT_8197F 0
+#define BIT_MASK_WMAC_RESP_TXANT_8197F 0x3ffff
+#define BIT_WMAC_RESP_TXANT_8197F(x) \
+ (((x) & BIT_MASK_WMAC_RESP_TXANT_8197F) \
+ << BIT_SHIFT_WMAC_RESP_TXANT_8197F)
+#define BITS_WMAC_RESP_TXANT_8197F \
+ (BIT_MASK_WMAC_RESP_TXANT_8197F << BIT_SHIFT_WMAC_RESP_TXANT_8197F)
+#define BIT_CLEAR_WMAC_RESP_TXANT_8197F(x) ((x) & (~BITS_WMAC_RESP_TXANT_8197F))
+#define BIT_GET_WMAC_RESP_TXANT_8197F(x) \
+ (((x) >> BIT_SHIFT_WMAC_RESP_TXANT_8197F) & \
+ BIT_MASK_WMAC_RESP_TXANT_8197F)
+#define BIT_SET_WMAC_RESP_TXANT_8197F(x, v) \
+ (BIT_CLEAR_WMAC_RESP_TXANT_8197F(x) | BIT_WMAC_RESP_TXANT_8197F(v))
+
+/* 2 REG_BBPSF_CTRL_8197F */
+#define BIT_CTL_IDLE_CLR_CSI_RPT_8197F BIT(31)
+#define BIT_WMAC_USE_NDPARATE_8197F BIT(30)
+
+#define BIT_SHIFT_WMAC_CSI_RATE_8197F 24
+#define BIT_MASK_WMAC_CSI_RATE_8197F 0x3f
+#define BIT_WMAC_CSI_RATE_8197F(x) \
+ (((x) & BIT_MASK_WMAC_CSI_RATE_8197F) << BIT_SHIFT_WMAC_CSI_RATE_8197F)
+#define BITS_WMAC_CSI_RATE_8197F \
+ (BIT_MASK_WMAC_CSI_RATE_8197F << BIT_SHIFT_WMAC_CSI_RATE_8197F)
+#define BIT_CLEAR_WMAC_CSI_RATE_8197F(x) ((x) & (~BITS_WMAC_CSI_RATE_8197F))
+#define BIT_GET_WMAC_CSI_RATE_8197F(x) \
+ (((x) >> BIT_SHIFT_WMAC_CSI_RATE_8197F) & BIT_MASK_WMAC_CSI_RATE_8197F)
+#define BIT_SET_WMAC_CSI_RATE_8197F(x, v) \
+ (BIT_CLEAR_WMAC_CSI_RATE_8197F(x) | BIT_WMAC_CSI_RATE_8197F(v))
+
+#define BIT_SHIFT_WMAC_RESP_TXRATE_8197F 16
+#define BIT_MASK_WMAC_RESP_TXRATE_8197F 0xff
+#define BIT_WMAC_RESP_TXRATE_8197F(x) \
+ (((x) & BIT_MASK_WMAC_RESP_TXRATE_8197F) \
+ << BIT_SHIFT_WMAC_RESP_TXRATE_8197F)
+#define BITS_WMAC_RESP_TXRATE_8197F \
+ (BIT_MASK_WMAC_RESP_TXRATE_8197F << BIT_SHIFT_WMAC_RESP_TXRATE_8197F)
+#define BIT_CLEAR_WMAC_RESP_TXRATE_8197F(x) \
+ ((x) & (~BITS_WMAC_RESP_TXRATE_8197F))
+#define BIT_GET_WMAC_RESP_TXRATE_8197F(x) \
+ (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8197F) & \
+ BIT_MASK_WMAC_RESP_TXRATE_8197F)
+#define BIT_SET_WMAC_RESP_TXRATE_8197F(x, v) \
+ (BIT_CLEAR_WMAC_RESP_TXRATE_8197F(x) | BIT_WMAC_RESP_TXRATE_8197F(v))
+
+#define BIT_BBPSF_MPDUCHKEN_8197F BIT(5)
+#define BIT_BBPSF_MHCHKEN_8197F BIT(4)
+#define BIT_BBPSF_ERRCHKEN_8197F BIT(3)
+
+#define BIT_SHIFT_BBPSF_ERRTHR_8197F 0
+#define BIT_MASK_BBPSF_ERRTHR_8197F 0x7
+#define BIT_BBPSF_ERRTHR_8197F(x) \
+ (((x) & BIT_MASK_BBPSF_ERRTHR_8197F) << BIT_SHIFT_BBPSF_ERRTHR_8197F)
+#define BITS_BBPSF_ERRTHR_8197F \
+ (BIT_MASK_BBPSF_ERRTHR_8197F << BIT_SHIFT_BBPSF_ERRTHR_8197F)
+#define BIT_CLEAR_BBPSF_ERRTHR_8197F(x) ((x) & (~BITS_BBPSF_ERRTHR_8197F))
+#define BIT_GET_BBPSF_ERRTHR_8197F(x) \
+ (((x) >> BIT_SHIFT_BBPSF_ERRTHR_8197F) & BIT_MASK_BBPSF_ERRTHR_8197F)
+#define BIT_SET_BBPSF_ERRTHR_8197F(x, v) \
+ (BIT_CLEAR_BBPSF_ERRTHR_8197F(x) | BIT_BBPSF_ERRTHR_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_P2P_RX_BCN_NOA_8197F (P2P RX BEACON NOA REGISTER) */
+#define BIT_NOA_PARSER_EN_8197F BIT(15)
+
+#define BIT_SHIFT_BSSID_SEL_V1_8197F 12
+#define BIT_MASK_BSSID_SEL_V1_8197F 0x7
+#define BIT_BSSID_SEL_V1_8197F(x) \
+ (((x) & BIT_MASK_BSSID_SEL_V1_8197F) << BIT_SHIFT_BSSID_SEL_V1_8197F)
+#define BITS_BSSID_SEL_V1_8197F \
+ (BIT_MASK_BSSID_SEL_V1_8197F << BIT_SHIFT_BSSID_SEL_V1_8197F)
+#define BIT_CLEAR_BSSID_SEL_V1_8197F(x) ((x) & (~BITS_BSSID_SEL_V1_8197F))
+#define BIT_GET_BSSID_SEL_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_BSSID_SEL_V1_8197F) & BIT_MASK_BSSID_SEL_V1_8197F)
+#define BIT_SET_BSSID_SEL_V1_8197F(x, v) \
+ (BIT_CLEAR_BSSID_SEL_V1_8197F(x) | BIT_BSSID_SEL_V1_8197F(v))
+
+#define BIT_SHIFT_P2P_OUI_TYPE_8197F 0
+#define BIT_MASK_P2P_OUI_TYPE_8197F 0xff
+#define BIT_P2P_OUI_TYPE_8197F(x) \
+ (((x) & BIT_MASK_P2P_OUI_TYPE_8197F) << BIT_SHIFT_P2P_OUI_TYPE_8197F)
+#define BITS_P2P_OUI_TYPE_8197F \
+ (BIT_MASK_P2P_OUI_TYPE_8197F << BIT_SHIFT_P2P_OUI_TYPE_8197F)
+#define BIT_CLEAR_P2P_OUI_TYPE_8197F(x) ((x) & (~BITS_P2P_OUI_TYPE_8197F))
+#define BIT_GET_P2P_OUI_TYPE_8197F(x) \
+ (((x) >> BIT_SHIFT_P2P_OUI_TYPE_8197F) & BIT_MASK_P2P_OUI_TYPE_8197F)
+#define BIT_SET_P2P_OUI_TYPE_8197F(x, v) \
+ (BIT_CLEAR_P2P_OUI_TYPE_8197F(x) | BIT_P2P_OUI_TYPE_8197F(v))
+
+/* 2 REG_ASSOCIATED_BFMER0_INFO_8197F (ASSOCIATED BEAMFORMER0 INFO REGISTER) */
+
+#define BIT_SHIFT_R_WMAC_TXCSI_AID0_8197F (48 & CPU_OPT_WIDTH)
+#define BIT_MASK_R_WMAC_TXCSI_AID0_8197F 0x1ff
+#define BIT_R_WMAC_TXCSI_AID0_8197F(x) \
+ (((x) & BIT_MASK_R_WMAC_TXCSI_AID0_8197F) \
+ << BIT_SHIFT_R_WMAC_TXCSI_AID0_8197F)
+#define BITS_R_WMAC_TXCSI_AID0_8197F \
+ (BIT_MASK_R_WMAC_TXCSI_AID0_8197F << BIT_SHIFT_R_WMAC_TXCSI_AID0_8197F)
+#define BIT_CLEAR_R_WMAC_TXCSI_AID0_8197F(x) \
+ ((x) & (~BITS_R_WMAC_TXCSI_AID0_8197F))
+#define BIT_GET_R_WMAC_TXCSI_AID0_8197F(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8197F) & \
+ BIT_MASK_R_WMAC_TXCSI_AID0_8197F)
+#define BIT_SET_R_WMAC_TXCSI_AID0_8197F(x, v) \
+ (BIT_CLEAR_R_WMAC_TXCSI_AID0_8197F(x) | BIT_R_WMAC_TXCSI_AID0_8197F(v))
+
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8197F 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8197F 0xffffffffffffL
+#define BIT_R_WMAC_SOUNDING_RXADD_R0_8197F(x) \
+ (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8197F) \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8197F)
+#define BITS_R_WMAC_SOUNDING_RXADD_R0_8197F \
+ (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8197F \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8197F)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_8197F(x) \
+ ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_8197F))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_8197F(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8197F) & \
+ BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8197F)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_8197F(x, v) \
+ (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_8197F(x) | \
+ BIT_R_WMAC_SOUNDING_RXADD_R0_8197F(v))
+
+/* 2 REG_ASSOCIATED_BFMER1_INFO_8197F (ASSOCIATED BEAMFORMER1 INFO REGISTER) */
+
+#define BIT_SHIFT_R_WMAC_TXCSI_AID1_8197F (48 & CPU_OPT_WIDTH)
+#define BIT_MASK_R_WMAC_TXCSI_AID1_8197F 0x1ff
+#define BIT_R_WMAC_TXCSI_AID1_8197F(x) \
+ (((x) & BIT_MASK_R_WMAC_TXCSI_AID1_8197F) \
+ << BIT_SHIFT_R_WMAC_TXCSI_AID1_8197F)
+#define BITS_R_WMAC_TXCSI_AID1_8197F \
+ (BIT_MASK_R_WMAC_TXCSI_AID1_8197F << BIT_SHIFT_R_WMAC_TXCSI_AID1_8197F)
+#define BIT_CLEAR_R_WMAC_TXCSI_AID1_8197F(x) \
+ ((x) & (~BITS_R_WMAC_TXCSI_AID1_8197F))
+#define BIT_GET_R_WMAC_TXCSI_AID1_8197F(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8197F) & \
+ BIT_MASK_R_WMAC_TXCSI_AID1_8197F)
+#define BIT_SET_R_WMAC_TXCSI_AID1_8197F(x, v) \
+ (BIT_CLEAR_R_WMAC_TXCSI_AID1_8197F(x) | BIT_R_WMAC_TXCSI_AID1_8197F(v))
+
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8197F 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8197F 0xffffffffffffL
+#define BIT_R_WMAC_SOUNDING_RXADD_R1_8197F(x) \
+ (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8197F) \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8197F)
+#define BITS_R_WMAC_SOUNDING_RXADD_R1_8197F \
+ (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8197F \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8197F)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_8197F(x) \
+ ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_8197F))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_8197F(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8197F) & \
+ BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8197F)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_8197F(x, v) \
+ (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_8197F(x) | \
+ BIT_R_WMAC_SOUNDING_RXADD_R1_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_TX_CSI_RPT_PARAM_BW20_8197F (TX CSI REPORT PARAMETER_BW20 REGISTER) */
+
+#define BIT_SHIFT_R_WMAC_BFINFO_20M_1_8197F 16
+#define BIT_MASK_R_WMAC_BFINFO_20M_1_8197F 0xfff
+#define BIT_R_WMAC_BFINFO_20M_1_8197F(x) \
+ (((x) & BIT_MASK_R_WMAC_BFINFO_20M_1_8197F) \
+ << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8197F)
+#define BITS_R_WMAC_BFINFO_20M_1_8197F \
+ (BIT_MASK_R_WMAC_BFINFO_20M_1_8197F \
+ << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8197F)
+#define BIT_CLEAR_R_WMAC_BFINFO_20M_1_8197F(x) \
+ ((x) & (~BITS_R_WMAC_BFINFO_20M_1_8197F))
+#define BIT_GET_R_WMAC_BFINFO_20M_1_8197F(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8197F) & \
+ BIT_MASK_R_WMAC_BFINFO_20M_1_8197F)
+#define BIT_SET_R_WMAC_BFINFO_20M_1_8197F(x, v) \
+ (BIT_CLEAR_R_WMAC_BFINFO_20M_1_8197F(x) | \
+ BIT_R_WMAC_BFINFO_20M_1_8197F(v))
+
+#define BIT_SHIFT_R_WMAC_BFINFO_20M_0_8197F 0
+#define BIT_MASK_R_WMAC_BFINFO_20M_0_8197F 0xfff
+#define BIT_R_WMAC_BFINFO_20M_0_8197F(x) \
+ (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8197F) \
+ << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8197F)
+#define BITS_R_WMAC_BFINFO_20M_0_8197F \
+ (BIT_MASK_R_WMAC_BFINFO_20M_0_8197F \
+ << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8197F)
+#define BIT_CLEAR_R_WMAC_BFINFO_20M_0_8197F(x) \
+ ((x) & (~BITS_R_WMAC_BFINFO_20M_0_8197F))
+#define BIT_GET_R_WMAC_BFINFO_20M_0_8197F(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8197F) & \
+ BIT_MASK_R_WMAC_BFINFO_20M_0_8197F)
+#define BIT_SET_R_WMAC_BFINFO_20M_0_8197F(x, v) \
+ (BIT_CLEAR_R_WMAC_BFINFO_20M_0_8197F(x) | \
+ BIT_R_WMAC_BFINFO_20M_0_8197F(v))
+
+/* 2 REG_TX_CSI_RPT_PARAM_BW40_8197F (TX CSI REPORT PARAMETER_BW40 REGISTER) */
+
+#define BIT_SHIFT_WMAC_RESP_ANTCD_8197F 0
+#define BIT_MASK_WMAC_RESP_ANTCD_8197F 0xf
+#define BIT_WMAC_RESP_ANTCD_8197F(x) \
+ (((x) & BIT_MASK_WMAC_RESP_ANTCD_8197F) \
+ << BIT_SHIFT_WMAC_RESP_ANTCD_8197F)
+#define BITS_WMAC_RESP_ANTCD_8197F \
+ (BIT_MASK_WMAC_RESP_ANTCD_8197F << BIT_SHIFT_WMAC_RESP_ANTCD_8197F)
+#define BIT_CLEAR_WMAC_RESP_ANTCD_8197F(x) ((x) & (~BITS_WMAC_RESP_ANTCD_8197F))
+#define BIT_GET_WMAC_RESP_ANTCD_8197F(x) \
+ (((x) >> BIT_SHIFT_WMAC_RESP_ANTCD_8197F) & \
+ BIT_MASK_WMAC_RESP_ANTCD_8197F)
+#define BIT_SET_WMAC_RESP_ANTCD_8197F(x, v) \
+ (BIT_CLEAR_WMAC_RESP_ANTCD_8197F(x) | BIT_WMAC_RESP_ANTCD_8197F(v))
+
+/* 2 REG_TX_CSI_RPT_PARAM_BW80_8197F (TX CSI REPORT PARAMETER_BW80 REGISTER) */
+
+/* 2 REG_BCN_PSR_RPT2_8197F (BEACON PARSER REPORT REGISTER2) */
+
+#define BIT_SHIFT_DTIM_CNT2_8197F 24
+#define BIT_MASK_DTIM_CNT2_8197F 0xff
+#define BIT_DTIM_CNT2_8197F(x) \
+ (((x) & BIT_MASK_DTIM_CNT2_8197F) << BIT_SHIFT_DTIM_CNT2_8197F)
+#define BITS_DTIM_CNT2_8197F \
+ (BIT_MASK_DTIM_CNT2_8197F << BIT_SHIFT_DTIM_CNT2_8197F)
+#define BIT_CLEAR_DTIM_CNT2_8197F(x) ((x) & (~BITS_DTIM_CNT2_8197F))
+#define BIT_GET_DTIM_CNT2_8197F(x) \
+ (((x) >> BIT_SHIFT_DTIM_CNT2_8197F) & BIT_MASK_DTIM_CNT2_8197F)
+#define BIT_SET_DTIM_CNT2_8197F(x, v) \
+ (BIT_CLEAR_DTIM_CNT2_8197F(x) | BIT_DTIM_CNT2_8197F(v))
+
+#define BIT_SHIFT_DTIM_PERIOD2_8197F 16
+#define BIT_MASK_DTIM_PERIOD2_8197F 0xff
+#define BIT_DTIM_PERIOD2_8197F(x) \
+ (((x) & BIT_MASK_DTIM_PERIOD2_8197F) << BIT_SHIFT_DTIM_PERIOD2_8197F)
+#define BITS_DTIM_PERIOD2_8197F \
+ (BIT_MASK_DTIM_PERIOD2_8197F << BIT_SHIFT_DTIM_PERIOD2_8197F)
+#define BIT_CLEAR_DTIM_PERIOD2_8197F(x) ((x) & (~BITS_DTIM_PERIOD2_8197F))
+#define BIT_GET_DTIM_PERIOD2_8197F(x) \
+ (((x) >> BIT_SHIFT_DTIM_PERIOD2_8197F) & BIT_MASK_DTIM_PERIOD2_8197F)
+#define BIT_SET_DTIM_PERIOD2_8197F(x, v) \
+ (BIT_CLEAR_DTIM_PERIOD2_8197F(x) | BIT_DTIM_PERIOD2_8197F(v))
+
+#define BIT_DTIM2_8197F BIT(15)
+#define BIT_TIM2_8197F BIT(14)
+
+#define BIT_SHIFT_PS_AID_2_8197F 0
+#define BIT_MASK_PS_AID_2_8197F 0x7ff
+#define BIT_PS_AID_2_8197F(x) \
+ (((x) & BIT_MASK_PS_AID_2_8197F) << BIT_SHIFT_PS_AID_2_8197F)
+#define BITS_PS_AID_2_8197F \
+ (BIT_MASK_PS_AID_2_8197F << BIT_SHIFT_PS_AID_2_8197F)
+#define BIT_CLEAR_PS_AID_2_8197F(x) ((x) & (~BITS_PS_AID_2_8197F))
+#define BIT_GET_PS_AID_2_8197F(x) \
+ (((x) >> BIT_SHIFT_PS_AID_2_8197F) & BIT_MASK_PS_AID_2_8197F)
+#define BIT_SET_PS_AID_2_8197F(x, v) \
+ (BIT_CLEAR_PS_AID_2_8197F(x) | BIT_PS_AID_2_8197F(v))
+
+/* 2 REG_BCN_PSR_RPT3_8197F (BEACON PARSER REPORT REGISTER3) */
+
+#define BIT_SHIFT_DTIM_CNT3_8197F 24
+#define BIT_MASK_DTIM_CNT3_8197F 0xff
+#define BIT_DTIM_CNT3_8197F(x) \
+ (((x) & BIT_MASK_DTIM_CNT3_8197F) << BIT_SHIFT_DTIM_CNT3_8197F)
+#define BITS_DTIM_CNT3_8197F \
+ (BIT_MASK_DTIM_CNT3_8197F << BIT_SHIFT_DTIM_CNT3_8197F)
+#define BIT_CLEAR_DTIM_CNT3_8197F(x) ((x) & (~BITS_DTIM_CNT3_8197F))
+#define BIT_GET_DTIM_CNT3_8197F(x) \
+ (((x) >> BIT_SHIFT_DTIM_CNT3_8197F) & BIT_MASK_DTIM_CNT3_8197F)
+#define BIT_SET_DTIM_CNT3_8197F(x, v) \
+ (BIT_CLEAR_DTIM_CNT3_8197F(x) | BIT_DTIM_CNT3_8197F(v))
+
+#define BIT_SHIFT_DTIM_PERIOD3_8197F 16
+#define BIT_MASK_DTIM_PERIOD3_8197F 0xff
+#define BIT_DTIM_PERIOD3_8197F(x) \
+ (((x) & BIT_MASK_DTIM_PERIOD3_8197F) << BIT_SHIFT_DTIM_PERIOD3_8197F)
+#define BITS_DTIM_PERIOD3_8197F \
+ (BIT_MASK_DTIM_PERIOD3_8197F << BIT_SHIFT_DTIM_PERIOD3_8197F)
+#define BIT_CLEAR_DTIM_PERIOD3_8197F(x) ((x) & (~BITS_DTIM_PERIOD3_8197F))
+#define BIT_GET_DTIM_PERIOD3_8197F(x) \
+ (((x) >> BIT_SHIFT_DTIM_PERIOD3_8197F) & BIT_MASK_DTIM_PERIOD3_8197F)
+#define BIT_SET_DTIM_PERIOD3_8197F(x, v) \
+ (BIT_CLEAR_DTIM_PERIOD3_8197F(x) | BIT_DTIM_PERIOD3_8197F(v))
+
+#define BIT_DTIM3_8197F BIT(15)
+#define BIT_TIM3_8197F BIT(14)
+
+#define BIT_SHIFT_PS_AID_3_8197F 0
+#define BIT_MASK_PS_AID_3_8197F 0x7ff
+#define BIT_PS_AID_3_8197F(x) \
+ (((x) & BIT_MASK_PS_AID_3_8197F) << BIT_SHIFT_PS_AID_3_8197F)
+#define BITS_PS_AID_3_8197F \
+ (BIT_MASK_PS_AID_3_8197F << BIT_SHIFT_PS_AID_3_8197F)
+#define BIT_CLEAR_PS_AID_3_8197F(x) ((x) & (~BITS_PS_AID_3_8197F))
+#define BIT_GET_PS_AID_3_8197F(x) \
+ (((x) >> BIT_SHIFT_PS_AID_3_8197F) & BIT_MASK_PS_AID_3_8197F)
+#define BIT_SET_PS_AID_3_8197F(x, v) \
+ (BIT_CLEAR_PS_AID_3_8197F(x) | BIT_PS_AID_3_8197F(v))
+
+/* 2 REG_BCN_PSR_RPT4_8197F (BEACON PARSER REPORT REGISTER4) */
+
+#define BIT_SHIFT_DTIM_CNT4_8197F 24
+#define BIT_MASK_DTIM_CNT4_8197F 0xff
+#define BIT_DTIM_CNT4_8197F(x) \
+ (((x) & BIT_MASK_DTIM_CNT4_8197F) << BIT_SHIFT_DTIM_CNT4_8197F)
+#define BITS_DTIM_CNT4_8197F \
+ (BIT_MASK_DTIM_CNT4_8197F << BIT_SHIFT_DTIM_CNT4_8197F)
+#define BIT_CLEAR_DTIM_CNT4_8197F(x) ((x) & (~BITS_DTIM_CNT4_8197F))
+#define BIT_GET_DTIM_CNT4_8197F(x) \
+ (((x) >> BIT_SHIFT_DTIM_CNT4_8197F) & BIT_MASK_DTIM_CNT4_8197F)
+#define BIT_SET_DTIM_CNT4_8197F(x, v) \
+ (BIT_CLEAR_DTIM_CNT4_8197F(x) | BIT_DTIM_CNT4_8197F(v))
+
+#define BIT_SHIFT_DTIM_PERIOD4_8197F 16
+#define BIT_MASK_DTIM_PERIOD4_8197F 0xff
+#define BIT_DTIM_PERIOD4_8197F(x) \
+ (((x) & BIT_MASK_DTIM_PERIOD4_8197F) << BIT_SHIFT_DTIM_PERIOD4_8197F)
+#define BITS_DTIM_PERIOD4_8197F \
+ (BIT_MASK_DTIM_PERIOD4_8197F << BIT_SHIFT_DTIM_PERIOD4_8197F)
+#define BIT_CLEAR_DTIM_PERIOD4_8197F(x) ((x) & (~BITS_DTIM_PERIOD4_8197F))
+#define BIT_GET_DTIM_PERIOD4_8197F(x) \
+ (((x) >> BIT_SHIFT_DTIM_PERIOD4_8197F) & BIT_MASK_DTIM_PERIOD4_8197F)
+#define BIT_SET_DTIM_PERIOD4_8197F(x, v) \
+ (BIT_CLEAR_DTIM_PERIOD4_8197F(x) | BIT_DTIM_PERIOD4_8197F(v))
+
+#define BIT_DTIM4_8197F BIT(15)
+#define BIT_TIM4_8197F BIT(14)
+
+#define BIT_SHIFT_PS_AID_4_8197F 0
+#define BIT_MASK_PS_AID_4_8197F 0x7ff
+#define BIT_PS_AID_4_8197F(x) \
+ (((x) & BIT_MASK_PS_AID_4_8197F) << BIT_SHIFT_PS_AID_4_8197F)
+#define BITS_PS_AID_4_8197F \
+ (BIT_MASK_PS_AID_4_8197F << BIT_SHIFT_PS_AID_4_8197F)
+#define BIT_CLEAR_PS_AID_4_8197F(x) ((x) & (~BITS_PS_AID_4_8197F))
+#define BIT_GET_PS_AID_4_8197F(x) \
+ (((x) >> BIT_SHIFT_PS_AID_4_8197F) & BIT_MASK_PS_AID_4_8197F)
+#define BIT_SET_PS_AID_4_8197F(x, v) \
+ (BIT_CLEAR_PS_AID_4_8197F(x) | BIT_PS_AID_4_8197F(v))
+
+/* 2 REG_A1_ADDR_MASK_8197F (A1 ADDR MASK REGISTER) */
+
+#define BIT_SHIFT_A1_ADDR_MASK_8197F 0
+#define BIT_MASK_A1_ADDR_MASK_8197F 0xffffffffL
+#define BIT_A1_ADDR_MASK_8197F(x) \
+ (((x) & BIT_MASK_A1_ADDR_MASK_8197F) << BIT_SHIFT_A1_ADDR_MASK_8197F)
+#define BITS_A1_ADDR_MASK_8197F \
+ (BIT_MASK_A1_ADDR_MASK_8197F << BIT_SHIFT_A1_ADDR_MASK_8197F)
+#define BIT_CLEAR_A1_ADDR_MASK_8197F(x) ((x) & (~BITS_A1_ADDR_MASK_8197F))
+#define BIT_GET_A1_ADDR_MASK_8197F(x) \
+ (((x) >> BIT_SHIFT_A1_ADDR_MASK_8197F) & BIT_MASK_A1_ADDR_MASK_8197F)
+#define BIT_SET_A1_ADDR_MASK_8197F(x, v) \
+ (BIT_CLEAR_A1_ADDR_MASK_8197F(x) | BIT_A1_ADDR_MASK_8197F(v))
+
+/* 2 REG_MACID2_8197F (MAC ID2 REGISTER) */
+
+#define BIT_SHIFT_MACID2_8197F 0
+#define BIT_MASK_MACID2_8197F 0xffffffffffffL
+#define BIT_MACID2_8197F(x) \
+ (((x) & BIT_MASK_MACID2_8197F) << BIT_SHIFT_MACID2_8197F)
+#define BITS_MACID2_8197F (BIT_MASK_MACID2_8197F << BIT_SHIFT_MACID2_8197F)
+#define BIT_CLEAR_MACID2_8197F(x) ((x) & (~BITS_MACID2_8197F))
+#define BIT_GET_MACID2_8197F(x) \
+ (((x) >> BIT_SHIFT_MACID2_8197F) & BIT_MASK_MACID2_8197F)
+#define BIT_SET_MACID2_8197F(x, v) \
+ (BIT_CLEAR_MACID2_8197F(x) | BIT_MACID2_8197F(v))
+
+/* 2 REG_BSSID2_8197F (BSSID2 REGISTER) */
+
+#define BIT_SHIFT_BSSID2_8197F 0
+#define BIT_MASK_BSSID2_8197F 0xffffffffffffL
+#define BIT_BSSID2_8197F(x) \
+ (((x) & BIT_MASK_BSSID2_8197F) << BIT_SHIFT_BSSID2_8197F)
+#define BITS_BSSID2_8197F (BIT_MASK_BSSID2_8197F << BIT_SHIFT_BSSID2_8197F)
+#define BIT_CLEAR_BSSID2_8197F(x) ((x) & (~BITS_BSSID2_8197F))
+#define BIT_GET_BSSID2_8197F(x) \
+ (((x) >> BIT_SHIFT_BSSID2_8197F) & BIT_MASK_BSSID2_8197F)
+#define BIT_SET_BSSID2_8197F(x, v) \
+ (BIT_CLEAR_BSSID2_8197F(x) | BIT_BSSID2_8197F(v))
+
+/* 2 REG_MACID3_8197F (MAC ID3 REGISTER) */
+
+#define BIT_SHIFT_MACID3_8197F 0
+#define BIT_MASK_MACID3_8197F 0xffffffffffffL
+#define BIT_MACID3_8197F(x) \
+ (((x) & BIT_MASK_MACID3_8197F) << BIT_SHIFT_MACID3_8197F)
+#define BITS_MACID3_8197F (BIT_MASK_MACID3_8197F << BIT_SHIFT_MACID3_8197F)
+#define BIT_CLEAR_MACID3_8197F(x) ((x) & (~BITS_MACID3_8197F))
+#define BIT_GET_MACID3_8197F(x) \
+ (((x) >> BIT_SHIFT_MACID3_8197F) & BIT_MASK_MACID3_8197F)
+#define BIT_SET_MACID3_8197F(x, v) \
+ (BIT_CLEAR_MACID3_8197F(x) | BIT_MACID3_8197F(v))
+
+/* 2 REG_BSSID3_8197F (BSSID3 REGISTER) */
+
+#define BIT_SHIFT_BSSID3_8197F 0
+#define BIT_MASK_BSSID3_8197F 0xffffffffffffL
+#define BIT_BSSID3_8197F(x) \
+ (((x) & BIT_MASK_BSSID3_8197F) << BIT_SHIFT_BSSID3_8197F)
+#define BITS_BSSID3_8197F (BIT_MASK_BSSID3_8197F << BIT_SHIFT_BSSID3_8197F)
+#define BIT_CLEAR_BSSID3_8197F(x) ((x) & (~BITS_BSSID3_8197F))
+#define BIT_GET_BSSID3_8197F(x) \
+ (((x) >> BIT_SHIFT_BSSID3_8197F) & BIT_MASK_BSSID3_8197F)
+#define BIT_SET_BSSID3_8197F(x, v) \
+ (BIT_CLEAR_BSSID3_8197F(x) | BIT_BSSID3_8197F(v))
+
+/* 2 REG_MACID4_8197F (MAC ID4 REGISTER) */
+
+#define BIT_SHIFT_MACID4_8197F 0
+#define BIT_MASK_MACID4_8197F 0xffffffffffffL
+#define BIT_MACID4_8197F(x) \
+ (((x) & BIT_MASK_MACID4_8197F) << BIT_SHIFT_MACID4_8197F)
+#define BITS_MACID4_8197F (BIT_MASK_MACID4_8197F << BIT_SHIFT_MACID4_8197F)
+#define BIT_CLEAR_MACID4_8197F(x) ((x) & (~BITS_MACID4_8197F))
+#define BIT_GET_MACID4_8197F(x) \
+ (((x) >> BIT_SHIFT_MACID4_8197F) & BIT_MASK_MACID4_8197F)
+#define BIT_SET_MACID4_8197F(x, v) \
+ (BIT_CLEAR_MACID4_8197F(x) | BIT_MACID4_8197F(v))
+
+/* 2 REG_BSSID4_8197F (BSSID4 REGISTER) */
+
+#define BIT_SHIFT_BSSID4_8197F 0
+#define BIT_MASK_BSSID4_8197F 0xffffffffffffL
+#define BIT_BSSID4_8197F(x) \
+ (((x) & BIT_MASK_BSSID4_8197F) << BIT_SHIFT_BSSID4_8197F)
+#define BITS_BSSID4_8197F (BIT_MASK_BSSID4_8197F << BIT_SHIFT_BSSID4_8197F)
+#define BIT_CLEAR_BSSID4_8197F(x) ((x) & (~BITS_BSSID4_8197F))
+#define BIT_GET_BSSID4_8197F(x) \
+ (((x) >> BIT_SHIFT_BSSID4_8197F) & BIT_MASK_BSSID4_8197F)
+#define BIT_SET_BSSID4_8197F(x, v) \
+ (BIT_CLEAR_BSSID4_8197F(x) | BIT_BSSID4_8197F(v))
+
+/* 2 REG_NOA_REPORT_8197F */
+
+/* 2 REG_PWRBIT_SETTING_8197F */
+#define BIT_CLI3_PWRBIT_OW_EN_8197F BIT(7)
+#define BIT_CLI3_PWR_ST_8197F BIT(6)
+#define BIT_CLI2_PWRBIT_OW_EN_8197F BIT(5)
+#define BIT_CLI2_PWR_ST_8197F BIT(4)
+#define BIT_CLI1_PWRBIT_OW_EN_8197F BIT(3)
+#define BIT_CLI1_PWR_ST_8197F BIT(2)
+#define BIT_CLI0_PWRBIT_OW_EN_8197F BIT(1)
+#define BIT_CLI0_PWR_ST_8197F BIT(0)
+
+/* 2 REG_WMAC_MU_BF_OPTION_8197F */
+#define BIT_WMAC_RESP_NONSTA1_DIS_8197F BIT(7)
+#define BIT_BIT_WMAC_TXMU_ACKPOLICY_EN_8197F BIT(6)
+
+#define BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8197F 4
+#define BIT_MASK_WMAC_TXMU_ACKPOLICY_8197F 0x3
+#define BIT_WMAC_TXMU_ACKPOLICY_8197F(x) \
+ (((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8197F) \
+ << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8197F)
+#define BITS_WMAC_TXMU_ACKPOLICY_8197F \
+ (BIT_MASK_WMAC_TXMU_ACKPOLICY_8197F \
+ << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8197F)
+#define BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8197F(x) \
+ ((x) & (~BITS_WMAC_TXMU_ACKPOLICY_8197F))
+#define BIT_GET_WMAC_TXMU_ACKPOLICY_8197F(x) \
+ (((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8197F) & \
+ BIT_MASK_WMAC_TXMU_ACKPOLICY_8197F)
+#define BIT_SET_WMAC_TXMU_ACKPOLICY_8197F(x, v) \
+ (BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8197F(x) | \
+ BIT_WMAC_TXMU_ACKPOLICY_8197F(v))
+
+#define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8197F 1
+#define BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8197F 0x7
+#define BIT_WMAC_MU_BFEE_PORT_SEL_8197F(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8197F) \
+ << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8197F)
+#define BITS_WMAC_MU_BFEE_PORT_SEL_8197F \
+ (BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8197F \
+ << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8197F)
+#define BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8197F(x) \
+ ((x) & (~BITS_WMAC_MU_BFEE_PORT_SEL_8197F))
+#define BIT_GET_WMAC_MU_BFEE_PORT_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8197F) & \
+ BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8197F)
+#define BIT_SET_WMAC_MU_BFEE_PORT_SEL_8197F(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8197F(x) | \
+ BIT_WMAC_MU_BFEE_PORT_SEL_8197F(v))
+
+#define BIT_WMAC_MU_BFEE_DIS_8197F BIT(0)
+
+/* 2 REG_WMAC_PAUSE_BB_CLR_TH_8197F */
+
+#define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8197F 0
+#define BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8197F 0xff
+#define BIT_WMAC_PAUSE_BB_CLR_TH_8197F(x) \
+ (((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8197F) \
+ << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8197F)
+#define BITS_WMAC_PAUSE_BB_CLR_TH_8197F \
+ (BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8197F \
+ << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8197F)
+#define BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8197F(x) \
+ ((x) & (~BITS_WMAC_PAUSE_BB_CLR_TH_8197F))
+#define BIT_GET_WMAC_PAUSE_BB_CLR_TH_8197F(x) \
+ (((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8197F) & \
+ BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8197F)
+#define BIT_SET_WMAC_PAUSE_BB_CLR_TH_8197F(x, v) \
+ (BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8197F(x) | \
+ BIT_WMAC_PAUSE_BB_CLR_TH_8197F(v))
+
+/* 2 REG_WMAC_MU_ARB_8197F */
+#define BIT_WMAC_ARB_HW_ADAPT_EN_8197F BIT(7)
+#define BIT_WMAC_ARB_SW_EN_8197F BIT(6)
+
+#define BIT_SHIFT_WMAC_ARB_SW_STATE_8197F 0
+#define BIT_MASK_WMAC_ARB_SW_STATE_8197F 0x3f
+#define BIT_WMAC_ARB_SW_STATE_8197F(x) \
+ (((x) & BIT_MASK_WMAC_ARB_SW_STATE_8197F) \
+ << BIT_SHIFT_WMAC_ARB_SW_STATE_8197F)
+#define BITS_WMAC_ARB_SW_STATE_8197F \
+ (BIT_MASK_WMAC_ARB_SW_STATE_8197F << BIT_SHIFT_WMAC_ARB_SW_STATE_8197F)
+#define BIT_CLEAR_WMAC_ARB_SW_STATE_8197F(x) \
+ ((x) & (~BITS_WMAC_ARB_SW_STATE_8197F))
+#define BIT_GET_WMAC_ARB_SW_STATE_8197F(x) \
+ (((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE_8197F) & \
+ BIT_MASK_WMAC_ARB_SW_STATE_8197F)
+#define BIT_SET_WMAC_ARB_SW_STATE_8197F(x, v) \
+ (BIT_CLEAR_WMAC_ARB_SW_STATE_8197F(x) | BIT_WMAC_ARB_SW_STATE_8197F(v))
+
+/* 2 REG_WMAC_MU_OPTION_8197F */
+
+#define BIT_SHIFT_WMAC_MU_DBGSEL_8197F 5
+#define BIT_MASK_WMAC_MU_DBGSEL_8197F 0x3
+#define BIT_WMAC_MU_DBGSEL_8197F(x) \
+ (((x) & BIT_MASK_WMAC_MU_DBGSEL_8197F) \
+ << BIT_SHIFT_WMAC_MU_DBGSEL_8197F)
+#define BITS_WMAC_MU_DBGSEL_8197F \
+ (BIT_MASK_WMAC_MU_DBGSEL_8197F << BIT_SHIFT_WMAC_MU_DBGSEL_8197F)
+#define BIT_CLEAR_WMAC_MU_DBGSEL_8197F(x) ((x) & (~BITS_WMAC_MU_DBGSEL_8197F))
+#define BIT_GET_WMAC_MU_DBGSEL_8197F(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_8197F) & \
+ BIT_MASK_WMAC_MU_DBGSEL_8197F)
+#define BIT_SET_WMAC_MU_DBGSEL_8197F(x, v) \
+ (BIT_CLEAR_WMAC_MU_DBGSEL_8197F(x) | BIT_WMAC_MU_DBGSEL_8197F(v))
+
+#define BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8197F 0
+#define BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8197F 0x1f
+#define BIT_WMAC_MU_CPRD_TIMEOUT_8197F(x) \
+ (((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8197F) \
+ << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8197F)
+#define BITS_WMAC_MU_CPRD_TIMEOUT_8197F \
+ (BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8197F \
+ << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8197F)
+#define BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT_8197F(x) \
+ ((x) & (~BITS_WMAC_MU_CPRD_TIMEOUT_8197F))
+#define BIT_GET_WMAC_MU_CPRD_TIMEOUT_8197F(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8197F) & \
+ BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8197F)
+#define BIT_SET_WMAC_MU_CPRD_TIMEOUT_8197F(x, v) \
+ (BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT_8197F(x) | \
+ BIT_WMAC_MU_CPRD_TIMEOUT_8197F(v))
+
+/* 2 REG_WMAC_MU_BF_CTL_8197F */
+#define BIT_WMAC_INVLD_BFPRT_CHK_8197F BIT(15)
+#define BIT_WMAC_RETXBFRPTSEQ_UPD_8197F BIT(14)
+
+#define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8197F 12
+#define BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8197F 0x3
+#define BIT_WMAC_MU_BFRPTSEG_SEL_8197F(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8197F) \
+ << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8197F)
+#define BITS_WMAC_MU_BFRPTSEG_SEL_8197F \
+ (BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8197F \
+ << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8197F)
+#define BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8197F(x) \
+ ((x) & (~BITS_WMAC_MU_BFRPTSEG_SEL_8197F))
+#define BIT_GET_WMAC_MU_BFRPTSEG_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8197F) & \
+ BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8197F)
+#define BIT_SET_WMAC_MU_BFRPTSEG_SEL_8197F(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8197F(x) | \
+ BIT_WMAC_MU_BFRPTSEG_SEL_8197F(v))
+
+#define BIT_SHIFT_WMAC_MU_BF_MYAID_8197F 0
+#define BIT_MASK_WMAC_MU_BF_MYAID_8197F 0xfff
+#define BIT_WMAC_MU_BF_MYAID_8197F(x) \
+ (((x) & BIT_MASK_WMAC_MU_BF_MYAID_8197F) \
+ << BIT_SHIFT_WMAC_MU_BF_MYAID_8197F)
+#define BITS_WMAC_MU_BF_MYAID_8197F \
+ (BIT_MASK_WMAC_MU_BF_MYAID_8197F << BIT_SHIFT_WMAC_MU_BF_MYAID_8197F)
+#define BIT_CLEAR_WMAC_MU_BF_MYAID_8197F(x) \
+ ((x) & (~BITS_WMAC_MU_BF_MYAID_8197F))
+#define BIT_GET_WMAC_MU_BF_MYAID_8197F(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID_8197F) & \
+ BIT_MASK_WMAC_MU_BF_MYAID_8197F)
+#define BIT_SET_WMAC_MU_BF_MYAID_8197F(x, v) \
+ (BIT_CLEAR_WMAC_MU_BF_MYAID_8197F(x) | BIT_WMAC_MU_BF_MYAID_8197F(v))
+
+/* 2 REG_WMAC_MU_BFRPT_PARA_8197F */
+
+#define BIT_SHIFT_BFRPT_PARA_USERID_SEL_8197F 12
+#define BIT_MASK_BFRPT_PARA_USERID_SEL_8197F 0x7
+#define BIT_BFRPT_PARA_USERID_SEL_8197F(x) \
+ (((x) & BIT_MASK_BFRPT_PARA_USERID_SEL_8197F) \
+ << BIT_SHIFT_BFRPT_PARA_USERID_SEL_8197F)
+#define BITS_BFRPT_PARA_USERID_SEL_8197F \
+ (BIT_MASK_BFRPT_PARA_USERID_SEL_8197F \
+ << BIT_SHIFT_BFRPT_PARA_USERID_SEL_8197F)
+#define BIT_CLEAR_BFRPT_PARA_USERID_SEL_8197F(x) \
+ ((x) & (~BITS_BFRPT_PARA_USERID_SEL_8197F))
+#define BIT_GET_BFRPT_PARA_USERID_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL_8197F) & \
+ BIT_MASK_BFRPT_PARA_USERID_SEL_8197F)
+#define BIT_SET_BFRPT_PARA_USERID_SEL_8197F(x, v) \
+ (BIT_CLEAR_BFRPT_PARA_USERID_SEL_8197F(x) | \
+ BIT_BFRPT_PARA_USERID_SEL_8197F(v))
+
+#define BIT_SHIFT_BFRPT_PARA_8197F 0
+#define BIT_MASK_BFRPT_PARA_8197F 0xfff
+#define BIT_BFRPT_PARA_8197F(x) \
+ (((x) & BIT_MASK_BFRPT_PARA_8197F) << BIT_SHIFT_BFRPT_PARA_8197F)
+#define BITS_BFRPT_PARA_8197F \
+ (BIT_MASK_BFRPT_PARA_8197F << BIT_SHIFT_BFRPT_PARA_8197F)
+#define BIT_CLEAR_BFRPT_PARA_8197F(x) ((x) & (~BITS_BFRPT_PARA_8197F))
+#define BIT_GET_BFRPT_PARA_8197F(x) \
+ (((x) >> BIT_SHIFT_BFRPT_PARA_8197F) & BIT_MASK_BFRPT_PARA_8197F)
+#define BIT_SET_BFRPT_PARA_8197F(x, v) \
+ (BIT_CLEAR_BFRPT_PARA_8197F(x) | BIT_BFRPT_PARA_8197F(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2_8197F */
+#define BIT_STATUS_BFEE2_8197F BIT(10)
+#define BIT_WMAC_MU_BFEE2_EN_8197F BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE2_AID_8197F 0
+#define BIT_MASK_WMAC_MU_BFEE2_AID_8197F 0x1ff
+#define BIT_WMAC_MU_BFEE2_AID_8197F(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE2_AID_8197F) \
+ << BIT_SHIFT_WMAC_MU_BFEE2_AID_8197F)
+#define BITS_WMAC_MU_BFEE2_AID_8197F \
+ (BIT_MASK_WMAC_MU_BFEE2_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE2_AID_8197F)
+#define BIT_CLEAR_WMAC_MU_BFEE2_AID_8197F(x) \
+ ((x) & (~BITS_WMAC_MU_BFEE2_AID_8197F))
+#define BIT_GET_WMAC_MU_BFEE2_AID_8197F(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID_8197F) & \
+ BIT_MASK_WMAC_MU_BFEE2_AID_8197F)
+#define BIT_SET_WMAC_MU_BFEE2_AID_8197F(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE2_AID_8197F(x) | BIT_WMAC_MU_BFEE2_AID_8197F(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3_8197F */
+#define BIT_STATUS_BFEE3_8197F BIT(10)
+#define BIT_WMAC_MU_BFEE3_EN_8197F BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE3_AID_8197F 0
+#define BIT_MASK_WMAC_MU_BFEE3_AID_8197F 0x1ff
+#define BIT_WMAC_MU_BFEE3_AID_8197F(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE3_AID_8197F) \
+ << BIT_SHIFT_WMAC_MU_BFEE3_AID_8197F)
+#define BITS_WMAC_MU_BFEE3_AID_8197F \
+ (BIT_MASK_WMAC_MU_BFEE3_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE3_AID_8197F)
+#define BIT_CLEAR_WMAC_MU_BFEE3_AID_8197F(x) \
+ ((x) & (~BITS_WMAC_MU_BFEE3_AID_8197F))
+#define BIT_GET_WMAC_MU_BFEE3_AID_8197F(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID_8197F) & \
+ BIT_MASK_WMAC_MU_BFEE3_AID_8197F)
+#define BIT_SET_WMAC_MU_BFEE3_AID_8197F(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE3_AID_8197F(x) | BIT_WMAC_MU_BFEE3_AID_8197F(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4_8197F */
+#define BIT_STATUS_BFEE4_8197F BIT(10)
+#define BIT_WMAC_MU_BFEE4_EN_8197F BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE4_AID_8197F 0
+#define BIT_MASK_WMAC_MU_BFEE4_AID_8197F 0x1ff
+#define BIT_WMAC_MU_BFEE4_AID_8197F(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE4_AID_8197F) \
+ << BIT_SHIFT_WMAC_MU_BFEE4_AID_8197F)
+#define BITS_WMAC_MU_BFEE4_AID_8197F \
+ (BIT_MASK_WMAC_MU_BFEE4_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE4_AID_8197F)
+#define BIT_CLEAR_WMAC_MU_BFEE4_AID_8197F(x) \
+ ((x) & (~BITS_WMAC_MU_BFEE4_AID_8197F))
+#define BIT_GET_WMAC_MU_BFEE4_AID_8197F(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID_8197F) & \
+ BIT_MASK_WMAC_MU_BFEE4_AID_8197F)
+#define BIT_SET_WMAC_MU_BFEE4_AID_8197F(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE4_AID_8197F(x) | BIT_WMAC_MU_BFEE4_AID_8197F(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5_8197F */
+#define BIT_STATUS_BFEE5_8197F BIT(10)
+#define BIT_WMAC_MU_BFEE5_EN_8197F BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE5_AID_8197F 0
+#define BIT_MASK_WMAC_MU_BFEE5_AID_8197F 0x1ff
+#define BIT_WMAC_MU_BFEE5_AID_8197F(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE5_AID_8197F) \
+ << BIT_SHIFT_WMAC_MU_BFEE5_AID_8197F)
+#define BITS_WMAC_MU_BFEE5_AID_8197F \
+ (BIT_MASK_WMAC_MU_BFEE5_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE5_AID_8197F)
+#define BIT_CLEAR_WMAC_MU_BFEE5_AID_8197F(x) \
+ ((x) & (~BITS_WMAC_MU_BFEE5_AID_8197F))
+#define BIT_GET_WMAC_MU_BFEE5_AID_8197F(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID_8197F) & \
+ BIT_MASK_WMAC_MU_BFEE5_AID_8197F)
+#define BIT_SET_WMAC_MU_BFEE5_AID_8197F(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE5_AID_8197F(x) | BIT_WMAC_MU_BFEE5_AID_8197F(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6_8197F */
+#define BIT_STATUS_BFEE6_8197F BIT(10)
+#define BIT_WMAC_MU_BFEE6_EN_8197F BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE6_AID_8197F 0
+#define BIT_MASK_WMAC_MU_BFEE6_AID_8197F 0x1ff
+#define BIT_WMAC_MU_BFEE6_AID_8197F(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE6_AID_8197F) \
+ << BIT_SHIFT_WMAC_MU_BFEE6_AID_8197F)
+#define BITS_WMAC_MU_BFEE6_AID_8197F \
+ (BIT_MASK_WMAC_MU_BFEE6_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE6_AID_8197F)
+#define BIT_CLEAR_WMAC_MU_BFEE6_AID_8197F(x) \
+ ((x) & (~BITS_WMAC_MU_BFEE6_AID_8197F))
+#define BIT_GET_WMAC_MU_BFEE6_AID_8197F(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID_8197F) & \
+ BIT_MASK_WMAC_MU_BFEE6_AID_8197F)
+#define BIT_SET_WMAC_MU_BFEE6_AID_8197F(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE6_AID_8197F(x) | BIT_WMAC_MU_BFEE6_AID_8197F(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7_8197F */
+#define BIT_BIT_STATUS_BFEE4_8197F BIT(10)
+#define BIT_WMAC_MU_BFEE7_EN_8197F BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE7_AID_8197F 0
+#define BIT_MASK_WMAC_MU_BFEE7_AID_8197F 0x1ff
+#define BIT_WMAC_MU_BFEE7_AID_8197F(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE7_AID_8197F) \
+ << BIT_SHIFT_WMAC_MU_BFEE7_AID_8197F)
+#define BITS_WMAC_MU_BFEE7_AID_8197F \
+ (BIT_MASK_WMAC_MU_BFEE7_AID_8197F << BIT_SHIFT_WMAC_MU_BFEE7_AID_8197F)
+#define BIT_CLEAR_WMAC_MU_BFEE7_AID_8197F(x) \
+ ((x) & (~BITS_WMAC_MU_BFEE7_AID_8197F))
+#define BIT_GET_WMAC_MU_BFEE7_AID_8197F(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID_8197F) & \
+ BIT_MASK_WMAC_MU_BFEE7_AID_8197F)
+#define BIT_SET_WMAC_MU_BFEE7_AID_8197F(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE7_AID_8197F(x) | BIT_WMAC_MU_BFEE7_AID_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+#define BIT_RST_ALL_COUNTER_8197F BIT(31)
+
+#define BIT_SHIFT_ABORT_RX_VBON_COUNTER_8197F 16
+#define BIT_MASK_ABORT_RX_VBON_COUNTER_8197F 0xff
+#define BIT_ABORT_RX_VBON_COUNTER_8197F(x) \
+ (((x) & BIT_MASK_ABORT_RX_VBON_COUNTER_8197F) \
+ << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8197F)
+#define BITS_ABORT_RX_VBON_COUNTER_8197F \
+ (BIT_MASK_ABORT_RX_VBON_COUNTER_8197F \
+ << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8197F)
+#define BIT_CLEAR_ABORT_RX_VBON_COUNTER_8197F(x) \
+ ((x) & (~BITS_ABORT_RX_VBON_COUNTER_8197F))
+#define BIT_GET_ABORT_RX_VBON_COUNTER_8197F(x) \
+ (((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER_8197F) & \
+ BIT_MASK_ABORT_RX_VBON_COUNTER_8197F)
+#define BIT_SET_ABORT_RX_VBON_COUNTER_8197F(x, v) \
+ (BIT_CLEAR_ABORT_RX_VBON_COUNTER_8197F(x) | \
+ BIT_ABORT_RX_VBON_COUNTER_8197F(v))
+
+#define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8197F 8
+#define BIT_MASK_ABORT_RX_RDRDY_COUNTER_8197F 0xff
+#define BIT_ABORT_RX_RDRDY_COUNTER_8197F(x) \
+ (((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8197F) \
+ << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8197F)
+#define BITS_ABORT_RX_RDRDY_COUNTER_8197F \
+ (BIT_MASK_ABORT_RX_RDRDY_COUNTER_8197F \
+ << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8197F)
+#define BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8197F(x) \
+ ((x) & (~BITS_ABORT_RX_RDRDY_COUNTER_8197F))
+#define BIT_GET_ABORT_RX_RDRDY_COUNTER_8197F(x) \
+ (((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8197F) & \
+ BIT_MASK_ABORT_RX_RDRDY_COUNTER_8197F)
+#define BIT_SET_ABORT_RX_RDRDY_COUNTER_8197F(x, v) \
+ (BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8197F(x) | \
+ BIT_ABORT_RX_RDRDY_COUNTER_8197F(v))
+
+#define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8197F 0
+#define BIT_MASK_VBON_EARLY_FALLING_COUNTER_8197F 0xff
+#define BIT_VBON_EARLY_FALLING_COUNTER_8197F(x) \
+ (((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8197F) \
+ << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8197F)
+#define BITS_VBON_EARLY_FALLING_COUNTER_8197F \
+ (BIT_MASK_VBON_EARLY_FALLING_COUNTER_8197F \
+ << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8197F)
+#define BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8197F(x) \
+ ((x) & (~BITS_VBON_EARLY_FALLING_COUNTER_8197F))
+#define BIT_GET_VBON_EARLY_FALLING_COUNTER_8197F(x) \
+ (((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8197F) & \
+ BIT_MASK_VBON_EARLY_FALLING_COUNTER_8197F)
+#define BIT_SET_VBON_EARLY_FALLING_COUNTER_8197F(x, v) \
+ (BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8197F(x) | \
+ BIT_VBON_EARLY_FALLING_COUNTER_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+#define BIT_WMAC_PLCP_TRX_SEL_8197F BIT(31)
+
+#define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8197F 28
+#define BIT_MASK_WMAC_PLCP_RDSIG_SEL_8197F 0x7
+#define BIT_WMAC_PLCP_RDSIG_SEL_8197F(x) \
+ (((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8197F) \
+ << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8197F)
+#define BITS_WMAC_PLCP_RDSIG_SEL_8197F \
+ (BIT_MASK_WMAC_PLCP_RDSIG_SEL_8197F \
+ << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8197F)
+#define BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8197F(x) \
+ ((x) & (~BITS_WMAC_PLCP_RDSIG_SEL_8197F))
+#define BIT_GET_WMAC_PLCP_RDSIG_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8197F) & \
+ BIT_MASK_WMAC_PLCP_RDSIG_SEL_8197F)
+#define BIT_SET_WMAC_PLCP_RDSIG_SEL_8197F(x, v) \
+ (BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8197F(x) | \
+ BIT_WMAC_PLCP_RDSIG_SEL_8197F(v))
+
+#define BIT_SHIFT_WMAC_RATE_IDX_8197F 24
+#define BIT_MASK_WMAC_RATE_IDX_8197F 0xf
+#define BIT_WMAC_RATE_IDX_8197F(x) \
+ (((x) & BIT_MASK_WMAC_RATE_IDX_8197F) << BIT_SHIFT_WMAC_RATE_IDX_8197F)
+#define BITS_WMAC_RATE_IDX_8197F \
+ (BIT_MASK_WMAC_RATE_IDX_8197F << BIT_SHIFT_WMAC_RATE_IDX_8197F)
+#define BIT_CLEAR_WMAC_RATE_IDX_8197F(x) ((x) & (~BITS_WMAC_RATE_IDX_8197F))
+#define BIT_GET_WMAC_RATE_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_WMAC_RATE_IDX_8197F) & BIT_MASK_WMAC_RATE_IDX_8197F)
+#define BIT_SET_WMAC_RATE_IDX_8197F(x, v) \
+ (BIT_CLEAR_WMAC_RATE_IDX_8197F(x) | BIT_WMAC_RATE_IDX_8197F(v))
+
+#define BIT_SHIFT_WMAC_PLCP_RDSIG_8197F 0
+#define BIT_MASK_WMAC_PLCP_RDSIG_8197F 0xffffff
+#define BIT_WMAC_PLCP_RDSIG_8197F(x) \
+ (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8197F) \
+ << BIT_SHIFT_WMAC_PLCP_RDSIG_8197F)
+#define BITS_WMAC_PLCP_RDSIG_8197F \
+ (BIT_MASK_WMAC_PLCP_RDSIG_8197F << BIT_SHIFT_WMAC_PLCP_RDSIG_8197F)
+#define BIT_CLEAR_WMAC_PLCP_RDSIG_8197F(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8197F))
+#define BIT_GET_WMAC_PLCP_RDSIG_8197F(x) \
+ (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8197F) & \
+ BIT_MASK_WMAC_PLCP_RDSIG_8197F)
+#define BIT_SET_WMAC_PLCP_RDSIG_8197F(x, v) \
+ (BIT_CLEAR_WMAC_PLCP_RDSIG_8197F(x) | BIT_WMAC_PLCP_RDSIG_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_TRANSMIT_ADDRSS_0_8197F (TA0 REGISTER) */
+
+#define BIT_SHIFT_TA0_8197F 0
+#define BIT_MASK_TA0_8197F 0xffffffffffffL
+#define BIT_TA0_8197F(x) (((x) & BIT_MASK_TA0_8197F) << BIT_SHIFT_TA0_8197F)
+#define BITS_TA0_8197F (BIT_MASK_TA0_8197F << BIT_SHIFT_TA0_8197F)
+#define BIT_CLEAR_TA0_8197F(x) ((x) & (~BITS_TA0_8197F))
+#define BIT_GET_TA0_8197F(x) (((x) >> BIT_SHIFT_TA0_8197F) & BIT_MASK_TA0_8197F)
+#define BIT_SET_TA0_8197F(x, v) (BIT_CLEAR_TA0_8197F(x) | BIT_TA0_8197F(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_1_8197F (TA1 REGISTER) */
+
+#define BIT_SHIFT_TA1_8197F 0
+#define BIT_MASK_TA1_8197F 0xffffffffffffL
+#define BIT_TA1_8197F(x) (((x) & BIT_MASK_TA1_8197F) << BIT_SHIFT_TA1_8197F)
+#define BITS_TA1_8197F (BIT_MASK_TA1_8197F << BIT_SHIFT_TA1_8197F)
+#define BIT_CLEAR_TA1_8197F(x) ((x) & (~BITS_TA1_8197F))
+#define BIT_GET_TA1_8197F(x) (((x) >> BIT_SHIFT_TA1_8197F) & BIT_MASK_TA1_8197F)
+#define BIT_SET_TA1_8197F(x, v) (BIT_CLEAR_TA1_8197F(x) | BIT_TA1_8197F(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_2_8197F (TA2 REGISTER) */
+
+#define BIT_SHIFT_TA2_8197F 0
+#define BIT_MASK_TA2_8197F 0xffffffffffffL
+#define BIT_TA2_8197F(x) (((x) & BIT_MASK_TA2_8197F) << BIT_SHIFT_TA2_8197F)
+#define BITS_TA2_8197F (BIT_MASK_TA2_8197F << BIT_SHIFT_TA2_8197F)
+#define BIT_CLEAR_TA2_8197F(x) ((x) & (~BITS_TA2_8197F))
+#define BIT_GET_TA2_8197F(x) (((x) >> BIT_SHIFT_TA2_8197F) & BIT_MASK_TA2_8197F)
+#define BIT_SET_TA2_8197F(x, v) (BIT_CLEAR_TA2_8197F(x) | BIT_TA2_8197F(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_3_8197F (TA3 REGISTER) */
+
+#define BIT_SHIFT_TA3_8197F 0
+#define BIT_MASK_TA3_8197F 0xffffffffffffL
+#define BIT_TA3_8197F(x) (((x) & BIT_MASK_TA3_8197F) << BIT_SHIFT_TA3_8197F)
+#define BITS_TA3_8197F (BIT_MASK_TA3_8197F << BIT_SHIFT_TA3_8197F)
+#define BIT_CLEAR_TA3_8197F(x) ((x) & (~BITS_TA3_8197F))
+#define BIT_GET_TA3_8197F(x) (((x) >> BIT_SHIFT_TA3_8197F) & BIT_MASK_TA3_8197F)
+#define BIT_SET_TA3_8197F(x, v) (BIT_CLEAR_TA3_8197F(x) | BIT_TA3_8197F(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_4_8197F (TA4 REGISTER) */
+
+#define BIT_SHIFT_TA4_8197F 0
+#define BIT_MASK_TA4_8197F 0xffffffffffffL
+#define BIT_TA4_8197F(x) (((x) & BIT_MASK_TA4_8197F) << BIT_SHIFT_TA4_8197F)
+#define BITS_TA4_8197F (BIT_MASK_TA4_8197F << BIT_SHIFT_TA4_8197F)
+#define BIT_CLEAR_TA4_8197F(x) ((x) & (~BITS_TA4_8197F))
+#define BIT_GET_TA4_8197F(x) (((x) >> BIT_SHIFT_TA4_8197F) & BIT_MASK_TA4_8197F)
+#define BIT_SET_TA4_8197F(x, v) (BIT_CLEAR_TA4_8197F(x) | BIT_TA4_8197F(v))
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_MACID1_8197F */
+
+#define BIT_SHIFT_MACID1_8197F 0
+#define BIT_MASK_MACID1_8197F 0xffffffffffffL
+#define BIT_MACID1_8197F(x) \
+ (((x) & BIT_MASK_MACID1_8197F) << BIT_SHIFT_MACID1_8197F)
+#define BITS_MACID1_8197F (BIT_MASK_MACID1_8197F << BIT_SHIFT_MACID1_8197F)
+#define BIT_CLEAR_MACID1_8197F(x) ((x) & (~BITS_MACID1_8197F))
+#define BIT_GET_MACID1_8197F(x) \
+ (((x) >> BIT_SHIFT_MACID1_8197F) & BIT_MASK_MACID1_8197F)
+#define BIT_SET_MACID1_8197F(x, v) \
+ (BIT_CLEAR_MACID1_8197F(x) | BIT_MACID1_8197F(v))
+
+/* 2 REG_BSSID1_8197F */
+
+#define BIT_SHIFT_BSSID1_8197F 0
+#define BIT_MASK_BSSID1_8197F 0xffffffffffffL
+#define BIT_BSSID1_8197F(x) \
+ (((x) & BIT_MASK_BSSID1_8197F) << BIT_SHIFT_BSSID1_8197F)
+#define BITS_BSSID1_8197F (BIT_MASK_BSSID1_8197F << BIT_SHIFT_BSSID1_8197F)
+#define BIT_CLEAR_BSSID1_8197F(x) ((x) & (~BITS_BSSID1_8197F))
+#define BIT_GET_BSSID1_8197F(x) \
+ (((x) >> BIT_SHIFT_BSSID1_8197F) & BIT_MASK_BSSID1_8197F)
+#define BIT_SET_BSSID1_8197F(x, v) \
+ (BIT_CLEAR_BSSID1_8197F(x) | BIT_BSSID1_8197F(v))
+
+/* 2 REG_BCN_PSR_RPT1_8197F */
+
+#define BIT_SHIFT_DTIM_CNT1_8197F 24
+#define BIT_MASK_DTIM_CNT1_8197F 0xff
+#define BIT_DTIM_CNT1_8197F(x) \
+ (((x) & BIT_MASK_DTIM_CNT1_8197F) << BIT_SHIFT_DTIM_CNT1_8197F)
+#define BITS_DTIM_CNT1_8197F \
+ (BIT_MASK_DTIM_CNT1_8197F << BIT_SHIFT_DTIM_CNT1_8197F)
+#define BIT_CLEAR_DTIM_CNT1_8197F(x) ((x) & (~BITS_DTIM_CNT1_8197F))
+#define BIT_GET_DTIM_CNT1_8197F(x) \
+ (((x) >> BIT_SHIFT_DTIM_CNT1_8197F) & BIT_MASK_DTIM_CNT1_8197F)
+#define BIT_SET_DTIM_CNT1_8197F(x, v) \
+ (BIT_CLEAR_DTIM_CNT1_8197F(x) | BIT_DTIM_CNT1_8197F(v))
+
+#define BIT_SHIFT_DTIM_PERIOD1_8197F 16
+#define BIT_MASK_DTIM_PERIOD1_8197F 0xff
+#define BIT_DTIM_PERIOD1_8197F(x) \
+ (((x) & BIT_MASK_DTIM_PERIOD1_8197F) << BIT_SHIFT_DTIM_PERIOD1_8197F)
+#define BITS_DTIM_PERIOD1_8197F \
+ (BIT_MASK_DTIM_PERIOD1_8197F << BIT_SHIFT_DTIM_PERIOD1_8197F)
+#define BIT_CLEAR_DTIM_PERIOD1_8197F(x) ((x) & (~BITS_DTIM_PERIOD1_8197F))
+#define BIT_GET_DTIM_PERIOD1_8197F(x) \
+ (((x) >> BIT_SHIFT_DTIM_PERIOD1_8197F) & BIT_MASK_DTIM_PERIOD1_8197F)
+#define BIT_SET_DTIM_PERIOD1_8197F(x, v) \
+ (BIT_CLEAR_DTIM_PERIOD1_8197F(x) | BIT_DTIM_PERIOD1_8197F(v))
+
+#define BIT_DTIM1_8197F BIT(15)
+#define BIT_TIM1_8197F BIT(14)
+
+#define BIT_SHIFT_PS_AID_1_8197F 0
+#define BIT_MASK_PS_AID_1_8197F 0x7ff
+#define BIT_PS_AID_1_8197F(x) \
+ (((x) & BIT_MASK_PS_AID_1_8197F) << BIT_SHIFT_PS_AID_1_8197F)
+#define BITS_PS_AID_1_8197F \
+ (BIT_MASK_PS_AID_1_8197F << BIT_SHIFT_PS_AID_1_8197F)
+#define BIT_CLEAR_PS_AID_1_8197F(x) ((x) & (~BITS_PS_AID_1_8197F))
+#define BIT_GET_PS_AID_1_8197F(x) \
+ (((x) >> BIT_SHIFT_PS_AID_1_8197F) & BIT_MASK_PS_AID_1_8197F)
+#define BIT_SET_PS_AID_1_8197F(x, v) \
+ (BIT_CLEAR_PS_AID_1_8197F(x) | BIT_PS_AID_1_8197F(v))
+
+/* 2 REG_ASSOCIATED_BFMEE_SEL_8197F */
+#define BIT_TXUSER_ID1_8197F BIT(25)
+
+#define BIT_SHIFT_AID1_8197F 16
+#define BIT_MASK_AID1_8197F 0x1ff
+#define BIT_AID1_8197F(x) (((x) & BIT_MASK_AID1_8197F) << BIT_SHIFT_AID1_8197F)
+#define BITS_AID1_8197F (BIT_MASK_AID1_8197F << BIT_SHIFT_AID1_8197F)
+#define BIT_CLEAR_AID1_8197F(x) ((x) & (~BITS_AID1_8197F))
+#define BIT_GET_AID1_8197F(x) \
+ (((x) >> BIT_SHIFT_AID1_8197F) & BIT_MASK_AID1_8197F)
+#define BIT_SET_AID1_8197F(x, v) (BIT_CLEAR_AID1_8197F(x) | BIT_AID1_8197F(v))
+
+#define BIT_TXUSER_ID0_8197F BIT(9)
+
+#define BIT_SHIFT_AID0_8197F 0
+#define BIT_MASK_AID0_8197F 0x1ff
+#define BIT_AID0_8197F(x) (((x) & BIT_MASK_AID0_8197F) << BIT_SHIFT_AID0_8197F)
+#define BITS_AID0_8197F (BIT_MASK_AID0_8197F << BIT_SHIFT_AID0_8197F)
+#define BIT_CLEAR_AID0_8197F(x) ((x) & (~BITS_AID0_8197F))
+#define BIT_GET_AID0_8197F(x) \
+ (((x) >> BIT_SHIFT_AID0_8197F) & BIT_MASK_AID0_8197F)
+#define BIT_SET_AID0_8197F(x, v) (BIT_CLEAR_AID0_8197F(x) | BIT_AID0_8197F(v))
+
+/* 2 REG_SND_PTCL_CTRL_8197F */
+
+#define BIT_SHIFT_NDP_RX_STANDBY_TIMER_8197F 24
+#define BIT_MASK_NDP_RX_STANDBY_TIMER_8197F 0xff
+#define BIT_NDP_RX_STANDBY_TIMER_8197F(x) \
+ (((x) & BIT_MASK_NDP_RX_STANDBY_TIMER_8197F) \
+ << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8197F)
+#define BITS_NDP_RX_STANDBY_TIMER_8197F \
+ (BIT_MASK_NDP_RX_STANDBY_TIMER_8197F \
+ << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8197F)
+#define BIT_CLEAR_NDP_RX_STANDBY_TIMER_8197F(x) \
+ ((x) & (~BITS_NDP_RX_STANDBY_TIMER_8197F))
+#define BIT_GET_NDP_RX_STANDBY_TIMER_8197F(x) \
+ (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8197F) & \
+ BIT_MASK_NDP_RX_STANDBY_TIMER_8197F)
+#define BIT_SET_NDP_RX_STANDBY_TIMER_8197F(x, v) \
+ (BIT_CLEAR_NDP_RX_STANDBY_TIMER_8197F(x) | \
+ BIT_NDP_RX_STANDBY_TIMER_8197F(v))
+
+#define BIT_SHIFT_CSI_RPT_OFFSET_HT_8197F 16
+#define BIT_MASK_CSI_RPT_OFFSET_HT_8197F 0xff
+#define BIT_CSI_RPT_OFFSET_HT_8197F(x) \
+ (((x) & BIT_MASK_CSI_RPT_OFFSET_HT_8197F) \
+ << BIT_SHIFT_CSI_RPT_OFFSET_HT_8197F)
+#define BITS_CSI_RPT_OFFSET_HT_8197F \
+ (BIT_MASK_CSI_RPT_OFFSET_HT_8197F << BIT_SHIFT_CSI_RPT_OFFSET_HT_8197F)
+#define BIT_CLEAR_CSI_RPT_OFFSET_HT_8197F(x) \
+ ((x) & (~BITS_CSI_RPT_OFFSET_HT_8197F))
+#define BIT_GET_CSI_RPT_OFFSET_HT_8197F(x) \
+ (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_8197F) & \
+ BIT_MASK_CSI_RPT_OFFSET_HT_8197F)
+#define BIT_SET_CSI_RPT_OFFSET_HT_8197F(x, v) \
+ (BIT_CLEAR_CSI_RPT_OFFSET_HT_8197F(x) | BIT_CSI_RPT_OFFSET_HT_8197F(v))
+
+#define BIT_SHIFT_CSI_RPT_OFFSET_VHT_8197F 8
+#define BIT_MASK_CSI_RPT_OFFSET_VHT_8197F 0xff
+#define BIT_CSI_RPT_OFFSET_VHT_8197F(x) \
+ (((x) & BIT_MASK_CSI_RPT_OFFSET_VHT_8197F) \
+ << BIT_SHIFT_CSI_RPT_OFFSET_VHT_8197F)
+#define BITS_CSI_RPT_OFFSET_VHT_8197F \
+ (BIT_MASK_CSI_RPT_OFFSET_VHT_8197F \
+ << BIT_SHIFT_CSI_RPT_OFFSET_VHT_8197F)
+#define BIT_CLEAR_CSI_RPT_OFFSET_VHT_8197F(x) \
+ ((x) & (~BITS_CSI_RPT_OFFSET_VHT_8197F))
+#define BIT_GET_CSI_RPT_OFFSET_VHT_8197F(x) \
+ (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_VHT_8197F) & \
+ BIT_MASK_CSI_RPT_OFFSET_VHT_8197F)
+#define BIT_SET_CSI_RPT_OFFSET_VHT_8197F(x, v) \
+ (BIT_CLEAR_CSI_RPT_OFFSET_VHT_8197F(x) | \
+ BIT_CSI_RPT_OFFSET_VHT_8197F(v))
+
+#define BIT_R_WMAC_USE_NSTS_8197F BIT(7)
+#define BIT_R_DISABLE_CHECK_VHTSIGB_CRC_8197F BIT(6)
+#define BIT_R_DISABLE_CHECK_VHTSIGA_CRC_8197F BIT(5)
+#define BIT_R_WMAC_BFPARAM_SEL_8197F BIT(4)
+#define BIT_R_WMAC_CSISEQ_SEL_8197F BIT(3)
+#define BIT_R_WMAC_CSI_WITHHTC_EN_8197F BIT(2)
+#define BIT_R_WMAC_HT_NDPA_EN_8197F BIT(1)
+#define BIT_R_WMAC_VHT_NDPA_EN_8197F BIT(0)
+
+/* 2 REG_RX_CSI_RPT_INFO_8197F */
+
+/* 2 REG_NS_ARP_CTRL_8197F */
+#define BIT_R_WMAC_NSARP_RSPEN_8197F BIT(15)
+#define BIT_R_WMAC_NSARP_RARP_8197F BIT(9)
+#define BIT_R_WMAC_NSARP_RIPV6_8197F BIT(8)
+
+#define BIT_SHIFT_R_WMAC_NSARP_MODEN_8197F 6
+#define BIT_MASK_R_WMAC_NSARP_MODEN_8197F 0x3
+#define BIT_R_WMAC_NSARP_MODEN_8197F(x) \
+ (((x) & BIT_MASK_R_WMAC_NSARP_MODEN_8197F) \
+ << BIT_SHIFT_R_WMAC_NSARP_MODEN_8197F)
+#define BITS_R_WMAC_NSARP_MODEN_8197F \
+ (BIT_MASK_R_WMAC_NSARP_MODEN_8197F \
+ << BIT_SHIFT_R_WMAC_NSARP_MODEN_8197F)
+#define BIT_CLEAR_R_WMAC_NSARP_MODEN_8197F(x) \
+ ((x) & (~BITS_R_WMAC_NSARP_MODEN_8197F))
+#define BIT_GET_R_WMAC_NSARP_MODEN_8197F(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8197F) & \
+ BIT_MASK_R_WMAC_NSARP_MODEN_8197F)
+#define BIT_SET_R_WMAC_NSARP_MODEN_8197F(x, v) \
+ (BIT_CLEAR_R_WMAC_NSARP_MODEN_8197F(x) | \
+ BIT_R_WMAC_NSARP_MODEN_8197F(v))
+
+#define BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8197F 4
+#define BIT_MASK_R_WMAC_NSARP_RSPFTP_8197F 0x3
+#define BIT_R_WMAC_NSARP_RSPFTP_8197F(x) \
+ (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8197F) \
+ << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8197F)
+#define BITS_R_WMAC_NSARP_RSPFTP_8197F \
+ (BIT_MASK_R_WMAC_NSARP_RSPFTP_8197F \
+ << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8197F)
+#define BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8197F(x) \
+ ((x) & (~BITS_R_WMAC_NSARP_RSPFTP_8197F))
+#define BIT_GET_R_WMAC_NSARP_RSPFTP_8197F(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8197F) & \
+ BIT_MASK_R_WMAC_NSARP_RSPFTP_8197F)
+#define BIT_SET_R_WMAC_NSARP_RSPFTP_8197F(x, v) \
+ (BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8197F(x) | \
+ BIT_R_WMAC_NSARP_RSPFTP_8197F(v))
+
+#define BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8197F 0
+#define BIT_MASK_R_WMAC_NSARP_RSPSEC_8197F 0xf
+#define BIT_R_WMAC_NSARP_RSPSEC_8197F(x) \
+ (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8197F) \
+ << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8197F)
+#define BITS_R_WMAC_NSARP_RSPSEC_8197F \
+ (BIT_MASK_R_WMAC_NSARP_RSPSEC_8197F \
+ << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8197F)
+#define BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8197F(x) \
+ ((x) & (~BITS_R_WMAC_NSARP_RSPSEC_8197F))
+#define BIT_GET_R_WMAC_NSARP_RSPSEC_8197F(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8197F) & \
+ BIT_MASK_R_WMAC_NSARP_RSPSEC_8197F)
+#define BIT_SET_R_WMAC_NSARP_RSPSEC_8197F(x, v) \
+ (BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8197F(x) | \
+ BIT_R_WMAC_NSARP_RSPSEC_8197F(v))
+
+/* 2 REG_NS_ARP_INFO_8197F */
+
+/* 2 REG_BEAMFORMING_INFO_NSARP_V1_8197F */
+
+/* 2 REG_BEAMFORMING_INFO_NSARP_8197F */
+
+/* 2 REG_NOT_VALID_8197F */
+
+/* 2 REG_RSVD_0X740_8197F */
+
+/* 2 REG_WMAC_RTX_CTX_SUBTYPE_CFG_8197F */
+
+#define BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8197F 4
+#define BIT_MASK_R_WMAC_CTX_SUBTYPE_8197F 0xf
+#define BIT_R_WMAC_CTX_SUBTYPE_8197F(x) \
+ (((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8197F) \
+ << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8197F)
+#define BITS_R_WMAC_CTX_SUBTYPE_8197F \
+ (BIT_MASK_R_WMAC_CTX_SUBTYPE_8197F \
+ << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8197F)
+#define BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8197F(x) \
+ ((x) & (~BITS_R_WMAC_CTX_SUBTYPE_8197F))
+#define BIT_GET_R_WMAC_CTX_SUBTYPE_8197F(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8197F) & \
+ BIT_MASK_R_WMAC_CTX_SUBTYPE_8197F)
+#define BIT_SET_R_WMAC_CTX_SUBTYPE_8197F(x, v) \
+ (BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8197F(x) | \
+ BIT_R_WMAC_CTX_SUBTYPE_8197F(v))
+
+#define BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8197F 0
+#define BIT_MASK_R_WMAC_RTX_SUBTYPE_8197F 0xf
+#define BIT_R_WMAC_RTX_SUBTYPE_8197F(x) \
+ (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8197F) \
+ << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8197F)
+#define BITS_R_WMAC_RTX_SUBTYPE_8197F \
+ (BIT_MASK_R_WMAC_RTX_SUBTYPE_8197F \
+ << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8197F)
+#define BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8197F(x) \
+ ((x) & (~BITS_R_WMAC_RTX_SUBTYPE_8197F))
+#define BIT_GET_R_WMAC_RTX_SUBTYPE_8197F(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8197F) & \
+ BIT_MASK_R_WMAC_RTX_SUBTYPE_8197F)
+#define BIT_SET_R_WMAC_RTX_SUBTYPE_8197F(x, v) \
+ (BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8197F(x) | \
+ BIT_R_WMAC_RTX_SUBTYPE_8197F(v))
+
+/* 2 REG_WMAC_SWAES_CFG_8197F */
+
+/* 2 REG_BT_COEX_V2_8197F */
+#define BIT_GNT_BT_POLARITY_8197F BIT(12)
+#define BIT_GNT_BT_BYPASS_PRIORITY_8197F BIT(8)
+
+#define BIT_SHIFT_TIMER_8197F 0
+#define BIT_MASK_TIMER_8197F 0xff
+#define BIT_TIMER_8197F(x) \
+ (((x) & BIT_MASK_TIMER_8197F) << BIT_SHIFT_TIMER_8197F)
+#define BITS_TIMER_8197F (BIT_MASK_TIMER_8197F << BIT_SHIFT_TIMER_8197F)
+#define BIT_CLEAR_TIMER_8197F(x) ((x) & (~BITS_TIMER_8197F))
+#define BIT_GET_TIMER_8197F(x) \
+ (((x) >> BIT_SHIFT_TIMER_8197F) & BIT_MASK_TIMER_8197F)
+#define BIT_SET_TIMER_8197F(x, v) \
+ (BIT_CLEAR_TIMER_8197F(x) | BIT_TIMER_8197F(v))
+
+/* 2 REG_BT_COEX_8197F */
+#define BIT_R_GNT_BT_RFC_SW_8197F BIT(12)
+#define BIT_R_GNT_BT_RFC_SW_EN_8197F BIT(11)
+#define BIT_R_GNT_BT_BB_SW_8197F BIT(10)
+#define BIT_R_GNT_BT_BB_SW_EN_8197F BIT(9)
+#define BIT_R_BT_CNT_THREN_8197F BIT(8)
+
+#define BIT_SHIFT_R_BT_CNT_THR_8197F 0
+#define BIT_MASK_R_BT_CNT_THR_8197F 0xff
+#define BIT_R_BT_CNT_THR_8197F(x) \
+ (((x) & BIT_MASK_R_BT_CNT_THR_8197F) << BIT_SHIFT_R_BT_CNT_THR_8197F)
+#define BITS_R_BT_CNT_THR_8197F \
+ (BIT_MASK_R_BT_CNT_THR_8197F << BIT_SHIFT_R_BT_CNT_THR_8197F)
+#define BIT_CLEAR_R_BT_CNT_THR_8197F(x) ((x) & (~BITS_R_BT_CNT_THR_8197F))
+#define BIT_GET_R_BT_CNT_THR_8197F(x) \
+ (((x) >> BIT_SHIFT_R_BT_CNT_THR_8197F) & BIT_MASK_R_BT_CNT_THR_8197F)
+#define BIT_SET_R_BT_CNT_THR_8197F(x, v) \
+ (BIT_CLEAR_R_BT_CNT_THR_8197F(x) | BIT_R_BT_CNT_THR_8197F(v))
+
+/* 2 REG_WLAN_ACT_MASK_CTRL_8197F */
+#define BIT_WLRX_TER_BY_CTL_8197F BIT(43)
+#define BIT_WLRX_TER_BY_AD_8197F BIT(42)
+#define BIT_ANT_DIVERSITY_SEL_8197F BIT(41)
+#define BIT_ANTSEL_FOR_BT_CTRL_EN_8197F BIT(40)
+#define BIT_WLACT_LOW_GNTWL_EN_8197F BIT(34)
+#define BIT_WLACT_HIGH_GNTBT_EN_8197F BIT(33)
+
+#define BIT_SHIFT_RXMYRTS_NAV_V1_8197F 8
+#define BIT_MASK_RXMYRTS_NAV_V1_8197F 0xff
+#define BIT_RXMYRTS_NAV_V1_8197F(x) \
+ (((x) & BIT_MASK_RXMYRTS_NAV_V1_8197F) \
+ << BIT_SHIFT_RXMYRTS_NAV_V1_8197F)
+#define BITS_RXMYRTS_NAV_V1_8197F \
+ (BIT_MASK_RXMYRTS_NAV_V1_8197F << BIT_SHIFT_RXMYRTS_NAV_V1_8197F)
+#define BIT_CLEAR_RXMYRTS_NAV_V1_8197F(x) ((x) & (~BITS_RXMYRTS_NAV_V1_8197F))
+#define BIT_GET_RXMYRTS_NAV_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8197F) & \
+ BIT_MASK_RXMYRTS_NAV_V1_8197F)
+#define BIT_SET_RXMYRTS_NAV_V1_8197F(x, v) \
+ (BIT_CLEAR_RXMYRTS_NAV_V1_8197F(x) | BIT_RXMYRTS_NAV_V1_8197F(v))
+
+#define BIT_SHIFT_RTSRST_V1_8197F 0
+#define BIT_MASK_RTSRST_V1_8197F 0xff
+#define BIT_RTSRST_V1_8197F(x) \
+ (((x) & BIT_MASK_RTSRST_V1_8197F) << BIT_SHIFT_RTSRST_V1_8197F)
+#define BITS_RTSRST_V1_8197F \
+ (BIT_MASK_RTSRST_V1_8197F << BIT_SHIFT_RTSRST_V1_8197F)
+#define BIT_CLEAR_RTSRST_V1_8197F(x) ((x) & (~BITS_RTSRST_V1_8197F))
+#define BIT_GET_RTSRST_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_RTSRST_V1_8197F) & BIT_MASK_RTSRST_V1_8197F)
+#define BIT_SET_RTSRST_V1_8197F(x, v) \
+ (BIT_CLEAR_RTSRST_V1_8197F(x) | BIT_RTSRST_V1_8197F(v))
+
+/* 2 REG_BT_COEX_ENHANCED_INTR_CTRL_8197F */
+
+#define BIT_SHIFT_BT_STAT_DELAY_8197F 12
+#define BIT_MASK_BT_STAT_DELAY_8197F 0xf
+#define BIT_BT_STAT_DELAY_8197F(x) \
+ (((x) & BIT_MASK_BT_STAT_DELAY_8197F) << BIT_SHIFT_BT_STAT_DELAY_8197F)
+#define BITS_BT_STAT_DELAY_8197F \
+ (BIT_MASK_BT_STAT_DELAY_8197F << BIT_SHIFT_BT_STAT_DELAY_8197F)
+#define BIT_CLEAR_BT_STAT_DELAY_8197F(x) ((x) & (~BITS_BT_STAT_DELAY_8197F))
+#define BIT_GET_BT_STAT_DELAY_8197F(x) \
+ (((x) >> BIT_SHIFT_BT_STAT_DELAY_8197F) & BIT_MASK_BT_STAT_DELAY_8197F)
+#define BIT_SET_BT_STAT_DELAY_8197F(x, v) \
+ (BIT_CLEAR_BT_STAT_DELAY_8197F(x) | BIT_BT_STAT_DELAY_8197F(v))
+
+#define BIT_SHIFT_BT_TRX_INIT_DETECT_8197F 8
+#define BIT_MASK_BT_TRX_INIT_DETECT_8197F 0xf
+#define BIT_BT_TRX_INIT_DETECT_8197F(x) \
+ (((x) & BIT_MASK_BT_TRX_INIT_DETECT_8197F) \
+ << BIT_SHIFT_BT_TRX_INIT_DETECT_8197F)
+#define BITS_BT_TRX_INIT_DETECT_8197F \
+ (BIT_MASK_BT_TRX_INIT_DETECT_8197F \
+ << BIT_SHIFT_BT_TRX_INIT_DETECT_8197F)
+#define BIT_CLEAR_BT_TRX_INIT_DETECT_8197F(x) \
+ ((x) & (~BITS_BT_TRX_INIT_DETECT_8197F))
+#define BIT_GET_BT_TRX_INIT_DETECT_8197F(x) \
+ (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8197F) & \
+ BIT_MASK_BT_TRX_INIT_DETECT_8197F)
+#define BIT_SET_BT_TRX_INIT_DETECT_8197F(x, v) \
+ (BIT_CLEAR_BT_TRX_INIT_DETECT_8197F(x) | \
+ BIT_BT_TRX_INIT_DETECT_8197F(v))
+
+#define BIT_SHIFT_BT_PRI_DETECT_TO_8197F 4
+#define BIT_MASK_BT_PRI_DETECT_TO_8197F 0xf
+#define BIT_BT_PRI_DETECT_TO_8197F(x) \
+ (((x) & BIT_MASK_BT_PRI_DETECT_TO_8197F) \
+ << BIT_SHIFT_BT_PRI_DETECT_TO_8197F)
+#define BITS_BT_PRI_DETECT_TO_8197F \
+ (BIT_MASK_BT_PRI_DETECT_TO_8197F << BIT_SHIFT_BT_PRI_DETECT_TO_8197F)
+#define BIT_CLEAR_BT_PRI_DETECT_TO_8197F(x) \
+ ((x) & (~BITS_BT_PRI_DETECT_TO_8197F))
+#define BIT_GET_BT_PRI_DETECT_TO_8197F(x) \
+ (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8197F) & \
+ BIT_MASK_BT_PRI_DETECT_TO_8197F)
+#define BIT_SET_BT_PRI_DETECT_TO_8197F(x, v) \
+ (BIT_CLEAR_BT_PRI_DETECT_TO_8197F(x) | BIT_BT_PRI_DETECT_TO_8197F(v))
+
+#define BIT_R_GRANTALL_WLMASK_8197F BIT(3)
+#define BIT_STATIS_BT_EN_8197F BIT(2)
+#define BIT_WL_ACT_MASK_ENABLE_8197F BIT(1)
+#define BIT_ENHANCED_BT_8197F BIT(0)
+
+/* 2 REG_BT_ACT_STATISTICS_8197F */
+
+#define BIT_SHIFT_STATIS_BT_LO_RX_8197F (48 & CPU_OPT_WIDTH)
+#define BIT_MASK_STATIS_BT_LO_RX_8197F 0xffff
+#define BIT_STATIS_BT_LO_RX_8197F(x) \
+ (((x) & BIT_MASK_STATIS_BT_LO_RX_8197F) \
+ << BIT_SHIFT_STATIS_BT_LO_RX_8197F)
+#define BITS_STATIS_BT_LO_RX_8197F \
+ (BIT_MASK_STATIS_BT_LO_RX_8197F << BIT_SHIFT_STATIS_BT_LO_RX_8197F)
+#define BIT_CLEAR_STATIS_BT_LO_RX_8197F(x) ((x) & (~BITS_STATIS_BT_LO_RX_8197F))
+#define BIT_GET_STATIS_BT_LO_RX_8197F(x) \
+ (((x) >> BIT_SHIFT_STATIS_BT_LO_RX_8197F) & \
+ BIT_MASK_STATIS_BT_LO_RX_8197F)
+#define BIT_SET_STATIS_BT_LO_RX_8197F(x, v) \
+ (BIT_CLEAR_STATIS_BT_LO_RX_8197F(x) | BIT_STATIS_BT_LO_RX_8197F(v))
+
+#define BIT_SHIFT_STATIS_BT_LO_TX_8197F (32 & CPU_OPT_WIDTH)
+#define BIT_MASK_STATIS_BT_LO_TX_8197F 0xffff
+#define BIT_STATIS_BT_LO_TX_8197F(x) \
+ (((x) & BIT_MASK_STATIS_BT_LO_TX_8197F) \
+ << BIT_SHIFT_STATIS_BT_LO_TX_8197F)
+#define BITS_STATIS_BT_LO_TX_8197F \
+ (BIT_MASK_STATIS_BT_LO_TX_8197F << BIT_SHIFT_STATIS_BT_LO_TX_8197F)
+#define BIT_CLEAR_STATIS_BT_LO_TX_8197F(x) ((x) & (~BITS_STATIS_BT_LO_TX_8197F))
+#define BIT_GET_STATIS_BT_LO_TX_8197F(x) \
+ (((x) >> BIT_SHIFT_STATIS_BT_LO_TX_8197F) & \
+ BIT_MASK_STATIS_BT_LO_TX_8197F)
+#define BIT_SET_STATIS_BT_LO_TX_8197F(x, v) \
+ (BIT_CLEAR_STATIS_BT_LO_TX_8197F(x) | BIT_STATIS_BT_LO_TX_8197F(v))
+
+#define BIT_SHIFT_STATIS_BT_HI_RX_8197F 16
+#define BIT_MASK_STATIS_BT_HI_RX_8197F 0xffff
+#define BIT_STATIS_BT_HI_RX_8197F(x) \
+ (((x) & BIT_MASK_STATIS_BT_HI_RX_8197F) \
+ << BIT_SHIFT_STATIS_BT_HI_RX_8197F)
+#define BITS_STATIS_BT_HI_RX_8197F \
+ (BIT_MASK_STATIS_BT_HI_RX_8197F << BIT_SHIFT_STATIS_BT_HI_RX_8197F)
+#define BIT_CLEAR_STATIS_BT_HI_RX_8197F(x) ((x) & (~BITS_STATIS_BT_HI_RX_8197F))
+#define BIT_GET_STATIS_BT_HI_RX_8197F(x) \
+ (((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8197F) & \
+ BIT_MASK_STATIS_BT_HI_RX_8197F)
+#define BIT_SET_STATIS_BT_HI_RX_8197F(x, v) \
+ (BIT_CLEAR_STATIS_BT_HI_RX_8197F(x) | BIT_STATIS_BT_HI_RX_8197F(v))
+
+#define BIT_SHIFT_STATIS_BT_HI_TX_8197F 0
+#define BIT_MASK_STATIS_BT_HI_TX_8197F 0xffff
+#define BIT_STATIS_BT_HI_TX_8197F(x) \
+ (((x) & BIT_MASK_STATIS_BT_HI_TX_8197F) \
+ << BIT_SHIFT_STATIS_BT_HI_TX_8197F)
+#define BITS_STATIS_BT_HI_TX_8197F \
+ (BIT_MASK_STATIS_BT_HI_TX_8197F << BIT_SHIFT_STATIS_BT_HI_TX_8197F)
+#define BIT_CLEAR_STATIS_BT_HI_TX_8197F(x) ((x) & (~BITS_STATIS_BT_HI_TX_8197F))
+#define BIT_GET_STATIS_BT_HI_TX_8197F(x) \
+ (((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8197F) & \
+ BIT_MASK_STATIS_BT_HI_TX_8197F)
+#define BIT_SET_STATIS_BT_HI_TX_8197F(x, v) \
+ (BIT_CLEAR_STATIS_BT_HI_TX_8197F(x) | BIT_STATIS_BT_HI_TX_8197F(v))
+
+/* 2 REG_BT_STATISTICS_CONTROL_REGISTER_8197F */
+
+#define BIT_SHIFT_R_BT_CMD_RPT_8197F 16
+#define BIT_MASK_R_BT_CMD_RPT_8197F 0xffff
+#define BIT_R_BT_CMD_RPT_8197F(x) \
+ (((x) & BIT_MASK_R_BT_CMD_RPT_8197F) << BIT_SHIFT_R_BT_CMD_RPT_8197F)
+#define BITS_R_BT_CMD_RPT_8197F \
+ (BIT_MASK_R_BT_CMD_RPT_8197F << BIT_SHIFT_R_BT_CMD_RPT_8197F)
+#define BIT_CLEAR_R_BT_CMD_RPT_8197F(x) ((x) & (~BITS_R_BT_CMD_RPT_8197F))
+#define BIT_GET_R_BT_CMD_RPT_8197F(x) \
+ (((x) >> BIT_SHIFT_R_BT_CMD_RPT_8197F) & BIT_MASK_R_BT_CMD_RPT_8197F)
+#define BIT_SET_R_BT_CMD_RPT_8197F(x, v) \
+ (BIT_CLEAR_R_BT_CMD_RPT_8197F(x) | BIT_R_BT_CMD_RPT_8197F(v))
+
+#define BIT_SHIFT_R_RPT_FROM_BT_8197F 8
+#define BIT_MASK_R_RPT_FROM_BT_8197F 0xff
+#define BIT_R_RPT_FROM_BT_8197F(x) \
+ (((x) & BIT_MASK_R_RPT_FROM_BT_8197F) << BIT_SHIFT_R_RPT_FROM_BT_8197F)
+#define BITS_R_RPT_FROM_BT_8197F \
+ (BIT_MASK_R_RPT_FROM_BT_8197F << BIT_SHIFT_R_RPT_FROM_BT_8197F)
+#define BIT_CLEAR_R_RPT_FROM_BT_8197F(x) ((x) & (~BITS_R_RPT_FROM_BT_8197F))
+#define BIT_GET_R_RPT_FROM_BT_8197F(x) \
+ (((x) >> BIT_SHIFT_R_RPT_FROM_BT_8197F) & BIT_MASK_R_RPT_FROM_BT_8197F)
+#define BIT_SET_R_RPT_FROM_BT_8197F(x, v) \
+ (BIT_CLEAR_R_RPT_FROM_BT_8197F(x) | BIT_R_RPT_FROM_BT_8197F(v))
+
+#define BIT_SHIFT_BT_HID_ISR_SET_8197F 6
+#define BIT_MASK_BT_HID_ISR_SET_8197F 0x3
+#define BIT_BT_HID_ISR_SET_8197F(x) \
+ (((x) & BIT_MASK_BT_HID_ISR_SET_8197F) \
+ << BIT_SHIFT_BT_HID_ISR_SET_8197F)
+#define BITS_BT_HID_ISR_SET_8197F \
+ (BIT_MASK_BT_HID_ISR_SET_8197F << BIT_SHIFT_BT_HID_ISR_SET_8197F)
+#define BIT_CLEAR_BT_HID_ISR_SET_8197F(x) ((x) & (~BITS_BT_HID_ISR_SET_8197F))
+#define BIT_GET_BT_HID_ISR_SET_8197F(x) \
+ (((x) >> BIT_SHIFT_BT_HID_ISR_SET_8197F) & \
+ BIT_MASK_BT_HID_ISR_SET_8197F)
+#define BIT_SET_BT_HID_ISR_SET_8197F(x, v) \
+ (BIT_CLEAR_BT_HID_ISR_SET_8197F(x) | BIT_BT_HID_ISR_SET_8197F(v))
+
+#define BIT_TDMA_BT_START_NOTIFY_8197F BIT(5)
+#define BIT_ENABLE_TDMA_FW_MODE_8197F BIT(4)
+#define BIT_ENABLE_PTA_TDMA_MODE_8197F BIT(3)
+#define BIT_ENABLE_COEXIST_TAB_IN_TDMA_8197F BIT(2)
+#define BIT_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA_8197F BIT(1)
+#define BIT_RTK_BT_ENABLE_8197F BIT(0)
+
+/* 2 REG_BT_STATUS_REPORT_REGISTER_8197F */
+
+#define BIT_SHIFT_BT_PROFILE_8197F 24
+#define BIT_MASK_BT_PROFILE_8197F 0xff
+#define BIT_BT_PROFILE_8197F(x) \
+ (((x) & BIT_MASK_BT_PROFILE_8197F) << BIT_SHIFT_BT_PROFILE_8197F)
+#define BITS_BT_PROFILE_8197F \
+ (BIT_MASK_BT_PROFILE_8197F << BIT_SHIFT_BT_PROFILE_8197F)
+#define BIT_CLEAR_BT_PROFILE_8197F(x) ((x) & (~BITS_BT_PROFILE_8197F))
+#define BIT_GET_BT_PROFILE_8197F(x) \
+ (((x) >> BIT_SHIFT_BT_PROFILE_8197F) & BIT_MASK_BT_PROFILE_8197F)
+#define BIT_SET_BT_PROFILE_8197F(x, v) \
+ (BIT_CLEAR_BT_PROFILE_8197F(x) | BIT_BT_PROFILE_8197F(v))
+
+#define BIT_SHIFT_BT_POWER_8197F 16
+#define BIT_MASK_BT_POWER_8197F 0xff
+#define BIT_BT_POWER_8197F(x) \
+ (((x) & BIT_MASK_BT_POWER_8197F) << BIT_SHIFT_BT_POWER_8197F)
+#define BITS_BT_POWER_8197F \
+ (BIT_MASK_BT_POWER_8197F << BIT_SHIFT_BT_POWER_8197F)
+#define BIT_CLEAR_BT_POWER_8197F(x) ((x) & (~BITS_BT_POWER_8197F))
+#define BIT_GET_BT_POWER_8197F(x) \
+ (((x) >> BIT_SHIFT_BT_POWER_8197F) & BIT_MASK_BT_POWER_8197F)
+#define BIT_SET_BT_POWER_8197F(x, v) \
+ (BIT_CLEAR_BT_POWER_8197F(x) | BIT_BT_POWER_8197F(v))
+
+#define BIT_SHIFT_BT_PREDECT_STATUS_8197F 8
+#define BIT_MASK_BT_PREDECT_STATUS_8197F 0xff
+#define BIT_BT_PREDECT_STATUS_8197F(x) \
+ (((x) & BIT_MASK_BT_PREDECT_STATUS_8197F) \
+ << BIT_SHIFT_BT_PREDECT_STATUS_8197F)
+#define BITS_BT_PREDECT_STATUS_8197F \
+ (BIT_MASK_BT_PREDECT_STATUS_8197F << BIT_SHIFT_BT_PREDECT_STATUS_8197F)
+#define BIT_CLEAR_BT_PREDECT_STATUS_8197F(x) \
+ ((x) & (~BITS_BT_PREDECT_STATUS_8197F))
+#define BIT_GET_BT_PREDECT_STATUS_8197F(x) \
+ (((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8197F) & \
+ BIT_MASK_BT_PREDECT_STATUS_8197F)
+#define BIT_SET_BT_PREDECT_STATUS_8197F(x, v) \
+ (BIT_CLEAR_BT_PREDECT_STATUS_8197F(x) | BIT_BT_PREDECT_STATUS_8197F(v))
+
+#define BIT_SHIFT_BT_CMD_INFO_8197F 0
+#define BIT_MASK_BT_CMD_INFO_8197F 0xff
+#define BIT_BT_CMD_INFO_8197F(x) \
+ (((x) & BIT_MASK_BT_CMD_INFO_8197F) << BIT_SHIFT_BT_CMD_INFO_8197F)
+#define BITS_BT_CMD_INFO_8197F \
+ (BIT_MASK_BT_CMD_INFO_8197F << BIT_SHIFT_BT_CMD_INFO_8197F)
+#define BIT_CLEAR_BT_CMD_INFO_8197F(x) ((x) & (~BITS_BT_CMD_INFO_8197F))
+#define BIT_GET_BT_CMD_INFO_8197F(x) \
+ (((x) >> BIT_SHIFT_BT_CMD_INFO_8197F) & BIT_MASK_BT_CMD_INFO_8197F)
+#define BIT_SET_BT_CMD_INFO_8197F(x, v) \
+ (BIT_CLEAR_BT_CMD_INFO_8197F(x) | BIT_BT_CMD_INFO_8197F(v))
+
+/* 2 REG_BT_INTERRUPT_CONTROL_REGISTER_8197F */
+#define BIT_EN_MAC_NULL_PKT_NOTIFY_8197F BIT(31)
+#define BIT_EN_WLAN_RPT_AND_BT_QUERY_8197F BIT(30)
+#define BIT_EN_BT_STSTUS_RPT_8197F BIT(29)
+#define BIT_EN_BT_POWER_8197F BIT(28)
+#define BIT_EN_BT_CHANNEL_8197F BIT(27)
+#define BIT_EN_BT_SLOT_CHANGE_8197F BIT(26)
+#define BIT_EN_BT_PROFILE_OR_HID_8197F BIT(25)
+#define BIT_WLAN_RPT_NOTIFY_8197F BIT(24)
+
+#define BIT_SHIFT_WLAN_RPT_DATA_8197F 16
+#define BIT_MASK_WLAN_RPT_DATA_8197F 0xff
+#define BIT_WLAN_RPT_DATA_8197F(x) \
+ (((x) & BIT_MASK_WLAN_RPT_DATA_8197F) << BIT_SHIFT_WLAN_RPT_DATA_8197F)
+#define BITS_WLAN_RPT_DATA_8197F \
+ (BIT_MASK_WLAN_RPT_DATA_8197F << BIT_SHIFT_WLAN_RPT_DATA_8197F)
+#define BIT_CLEAR_WLAN_RPT_DATA_8197F(x) ((x) & (~BITS_WLAN_RPT_DATA_8197F))
+#define BIT_GET_WLAN_RPT_DATA_8197F(x) \
+ (((x) >> BIT_SHIFT_WLAN_RPT_DATA_8197F) & BIT_MASK_WLAN_RPT_DATA_8197F)
+#define BIT_SET_WLAN_RPT_DATA_8197F(x, v) \
+ (BIT_CLEAR_WLAN_RPT_DATA_8197F(x) | BIT_WLAN_RPT_DATA_8197F(v))
+
+#define BIT_SHIFT_CMD_ID_8197F 8
+#define BIT_MASK_CMD_ID_8197F 0xff
+#define BIT_CMD_ID_8197F(x) \
+ (((x) & BIT_MASK_CMD_ID_8197F) << BIT_SHIFT_CMD_ID_8197F)
+#define BITS_CMD_ID_8197F (BIT_MASK_CMD_ID_8197F << BIT_SHIFT_CMD_ID_8197F)
+#define BIT_CLEAR_CMD_ID_8197F(x) ((x) & (~BITS_CMD_ID_8197F))
+#define BIT_GET_CMD_ID_8197F(x) \
+ (((x) >> BIT_SHIFT_CMD_ID_8197F) & BIT_MASK_CMD_ID_8197F)
+#define BIT_SET_CMD_ID_8197F(x, v) \
+ (BIT_CLEAR_CMD_ID_8197F(x) | BIT_CMD_ID_8197F(v))
+
+#define BIT_SHIFT_BT_DATA_8197F 0
+#define BIT_MASK_BT_DATA_8197F 0xff
+#define BIT_BT_DATA_8197F(x) \
+ (((x) & BIT_MASK_BT_DATA_8197F) << BIT_SHIFT_BT_DATA_8197F)
+#define BITS_BT_DATA_8197F (BIT_MASK_BT_DATA_8197F << BIT_SHIFT_BT_DATA_8197F)
+#define BIT_CLEAR_BT_DATA_8197F(x) ((x) & (~BITS_BT_DATA_8197F))
+#define BIT_GET_BT_DATA_8197F(x) \
+ (((x) >> BIT_SHIFT_BT_DATA_8197F) & BIT_MASK_BT_DATA_8197F)
+#define BIT_SET_BT_DATA_8197F(x, v) \
+ (BIT_CLEAR_BT_DATA_8197F(x) | BIT_BT_DATA_8197F(v))
+
+/* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8197F */
+
+#define BIT_SHIFT_WLAN_RPT_TO_8197F 0
+#define BIT_MASK_WLAN_RPT_TO_8197F 0xff
+#define BIT_WLAN_RPT_TO_8197F(x) \
+ (((x) & BIT_MASK_WLAN_RPT_TO_8197F) << BIT_SHIFT_WLAN_RPT_TO_8197F)
+#define BITS_WLAN_RPT_TO_8197F \
+ (BIT_MASK_WLAN_RPT_TO_8197F << BIT_SHIFT_WLAN_RPT_TO_8197F)
+#define BIT_CLEAR_WLAN_RPT_TO_8197F(x) ((x) & (~BITS_WLAN_RPT_TO_8197F))
+#define BIT_GET_WLAN_RPT_TO_8197F(x) \
+ (((x) >> BIT_SHIFT_WLAN_RPT_TO_8197F) & BIT_MASK_WLAN_RPT_TO_8197F)
+#define BIT_SET_WLAN_RPT_TO_8197F(x, v) \
+ (BIT_CLEAR_WLAN_RPT_TO_8197F(x) | BIT_WLAN_RPT_TO_8197F(v))
+
+/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8197F */
+
+#define BIT_SHIFT_ISOLATION_CHK_8197F 1
+#define BIT_MASK_ISOLATION_CHK_8197F 0x7fffffffffffffffffffL
+#define BIT_ISOLATION_CHK_8197F(x) \
+ (((x) & BIT_MASK_ISOLATION_CHK_8197F) << BIT_SHIFT_ISOLATION_CHK_8197F)
+#define BITS_ISOLATION_CHK_8197F \
+ (BIT_MASK_ISOLATION_CHK_8197F << BIT_SHIFT_ISOLATION_CHK_8197F)
+#define BIT_CLEAR_ISOLATION_CHK_8197F(x) ((x) & (~BITS_ISOLATION_CHK_8197F))
+#define BIT_GET_ISOLATION_CHK_8197F(x) \
+ (((x) >> BIT_SHIFT_ISOLATION_CHK_8197F) & BIT_MASK_ISOLATION_CHK_8197F)
+#define BIT_SET_ISOLATION_CHK_8197F(x, v) \
+ (BIT_CLEAR_ISOLATION_CHK_8197F(x) | BIT_ISOLATION_CHK_8197F(v))
+
+#define BIT_ISOLATION_EN_8197F BIT(0)
+
+/* 2 REG_BT_INTERRUPT_STATUS_REGISTER_8197F */
+#define BIT_BT_HID_ISR_8197F BIT(7)
+#define BIT_BT_QUERY_ISR_8197F BIT(6)
+#define BIT_MAC_NULL_PKT_NOTIFY_ISR_8197F BIT(5)
+#define BIT_WLAN_RPT_ISR_8197F BIT(4)
+#define BIT_BT_POWER_ISR_8197F BIT(3)
+#define BIT_BT_CHANNEL_ISR_8197F BIT(2)
+#define BIT_BT_SLOT_CHANGE_ISR_8197F BIT(1)
+#define BIT_BT_PROFILE_ISR_8197F BIT(0)
+
+/* 2 REG_BT_TDMA_TIME_REGISTER_8197F */
+
+#define BIT_SHIFT_BT_TIME_8197F 6
+#define BIT_MASK_BT_TIME_8197F 0x3ffffff
+#define BIT_BT_TIME_8197F(x) \
+ (((x) & BIT_MASK_BT_TIME_8197F) << BIT_SHIFT_BT_TIME_8197F)
+#define BITS_BT_TIME_8197F (BIT_MASK_BT_TIME_8197F << BIT_SHIFT_BT_TIME_8197F)
+#define BIT_CLEAR_BT_TIME_8197F(x) ((x) & (~BITS_BT_TIME_8197F))
+#define BIT_GET_BT_TIME_8197F(x) \
+ (((x) >> BIT_SHIFT_BT_TIME_8197F) & BIT_MASK_BT_TIME_8197F)
+#define BIT_SET_BT_TIME_8197F(x, v) \
+ (BIT_CLEAR_BT_TIME_8197F(x) | BIT_BT_TIME_8197F(v))
+
+#define BIT_SHIFT_BT_RPT_SAMPLE_RATE_8197F 0
+#define BIT_MASK_BT_RPT_SAMPLE_RATE_8197F 0x3f
+#define BIT_BT_RPT_SAMPLE_RATE_8197F(x) \
+ (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8197F) \
+ << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8197F)
+#define BITS_BT_RPT_SAMPLE_RATE_8197F \
+ (BIT_MASK_BT_RPT_SAMPLE_RATE_8197F \
+ << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8197F)
+#define BIT_CLEAR_BT_RPT_SAMPLE_RATE_8197F(x) \
+ ((x) & (~BITS_BT_RPT_SAMPLE_RATE_8197F))
+#define BIT_GET_BT_RPT_SAMPLE_RATE_8197F(x) \
+ (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8197F) & \
+ BIT_MASK_BT_RPT_SAMPLE_RATE_8197F)
+#define BIT_SET_BT_RPT_SAMPLE_RATE_8197F(x, v) \
+ (BIT_CLEAR_BT_RPT_SAMPLE_RATE_8197F(x) | \
+ BIT_BT_RPT_SAMPLE_RATE_8197F(v))
+
+/* 2 REG_BT_ACT_REGISTER_8197F */
+
+#define BIT_SHIFT_BT_EISR_EN_8197F 16
+#define BIT_MASK_BT_EISR_EN_8197F 0xff
+#define BIT_BT_EISR_EN_8197F(x) \
+ (((x) & BIT_MASK_BT_EISR_EN_8197F) << BIT_SHIFT_BT_EISR_EN_8197F)
+#define BITS_BT_EISR_EN_8197F \
+ (BIT_MASK_BT_EISR_EN_8197F << BIT_SHIFT_BT_EISR_EN_8197F)
+#define BIT_CLEAR_BT_EISR_EN_8197F(x) ((x) & (~BITS_BT_EISR_EN_8197F))
+#define BIT_GET_BT_EISR_EN_8197F(x) \
+ (((x) >> BIT_SHIFT_BT_EISR_EN_8197F) & BIT_MASK_BT_EISR_EN_8197F)
+#define BIT_SET_BT_EISR_EN_8197F(x, v) \
+ (BIT_CLEAR_BT_EISR_EN_8197F(x) | BIT_BT_EISR_EN_8197F(v))
+
+#define BIT_BT_ACT_FALLING_ISR_8197F BIT(10)
+#define BIT_BT_ACT_RISING_ISR_8197F BIT(9)
+#define BIT_TDMA_TO_ISR_8197F BIT(8)
+
+#define BIT_SHIFT_BT_CH_8197F 0
+#define BIT_MASK_BT_CH_8197F 0xff
+#define BIT_BT_CH_8197F(x) \
+ (((x) & BIT_MASK_BT_CH_8197F) << BIT_SHIFT_BT_CH_8197F)
+#define BITS_BT_CH_8197F (BIT_MASK_BT_CH_8197F << BIT_SHIFT_BT_CH_8197F)
+#define BIT_CLEAR_BT_CH_8197F(x) ((x) & (~BITS_BT_CH_8197F))
+#define BIT_GET_BT_CH_8197F(x) \
+ (((x) >> BIT_SHIFT_BT_CH_8197F) & BIT_MASK_BT_CH_8197F)
+#define BIT_SET_BT_CH_8197F(x, v) \
+ (BIT_CLEAR_BT_CH_8197F(x) | BIT_BT_CH_8197F(v))
+
+/* 2 REG_OBFF_CTRL_BASIC_8197F */
+#define BIT_OBFF_EN_V1_8197F BIT(31)
+
+#define BIT_SHIFT_OBFF_STATE_V1_8197F 28
+#define BIT_MASK_OBFF_STATE_V1_8197F 0x3
+#define BIT_OBFF_STATE_V1_8197F(x) \
+ (((x) & BIT_MASK_OBFF_STATE_V1_8197F) << BIT_SHIFT_OBFF_STATE_V1_8197F)
+#define BITS_OBFF_STATE_V1_8197F \
+ (BIT_MASK_OBFF_STATE_V1_8197F << BIT_SHIFT_OBFF_STATE_V1_8197F)
+#define BIT_CLEAR_OBFF_STATE_V1_8197F(x) ((x) & (~BITS_OBFF_STATE_V1_8197F))
+#define BIT_GET_OBFF_STATE_V1_8197F(x) \
+ (((x) >> BIT_SHIFT_OBFF_STATE_V1_8197F) & BIT_MASK_OBFF_STATE_V1_8197F)
+#define BIT_SET_OBFF_STATE_V1_8197F(x, v) \
+ (BIT_CLEAR_OBFF_STATE_V1_8197F(x) | BIT_OBFF_STATE_V1_8197F(v))
+
+#define BIT_OBFF_ACT_RXDMA_EN_8197F BIT(27)
+#define BIT_OBFF_BLOCK_INT_EN_8197F BIT(26)
+#define BIT_OBFF_AUTOACT_EN_8197F BIT(25)
+#define BIT_OBFF_AUTOIDLE_EN_8197F BIT(24)
+
+#define BIT_SHIFT_WAKE_MAX_PLS_8197F 20
+#define BIT_MASK_WAKE_MAX_PLS_8197F 0x7
+#define BIT_WAKE_MAX_PLS_8197F(x) \
+ (((x) & BIT_MASK_WAKE_MAX_PLS_8197F) << BIT_SHIFT_WAKE_MAX_PLS_8197F)
+#define BITS_WAKE_MAX_PLS_8197F \
+ (BIT_MASK_WAKE_MAX_PLS_8197F << BIT_SHIFT_WAKE_MAX_PLS_8197F)
+#define BIT_CLEAR_WAKE_MAX_PLS_8197F(x) ((x) & (~BITS_WAKE_MAX_PLS_8197F))
+#define BIT_GET_WAKE_MAX_PLS_8197F(x) \
+ (((x) >> BIT_SHIFT_WAKE_MAX_PLS_8197F) & BIT_MASK_WAKE_MAX_PLS_8197F)
+#define BIT_SET_WAKE_MAX_PLS_8197F(x, v) \
+ (BIT_CLEAR_WAKE_MAX_PLS_8197F(x) | BIT_WAKE_MAX_PLS_8197F(v))
+
+#define BIT_SHIFT_WAKE_MIN_PLS_8197F 16
+#define BIT_MASK_WAKE_MIN_PLS_8197F 0x7
+#define BIT_WAKE_MIN_PLS_8197F(x) \
+ (((x) & BIT_MASK_WAKE_MIN_PLS_8197F) << BIT_SHIFT_WAKE_MIN_PLS_8197F)
+#define BITS_WAKE_MIN_PLS_8197F \
+ (BIT_MASK_WAKE_MIN_PLS_8197F << BIT_SHIFT_WAKE_MIN_PLS_8197F)
+#define BIT_CLEAR_WAKE_MIN_PLS_8197F(x) ((x) & (~BITS_WAKE_MIN_PLS_8197F))
+#define BIT_GET_WAKE_MIN_PLS_8197F(x) \
+ (((x) >> BIT_SHIFT_WAKE_MIN_PLS_8197F) & BIT_MASK_WAKE_MIN_PLS_8197F)
+#define BIT_SET_WAKE_MIN_PLS_8197F(x, v) \
+ (BIT_CLEAR_WAKE_MIN_PLS_8197F(x) | BIT_WAKE_MIN_PLS_8197F(v))
+
+#define BIT_SHIFT_WAKE_MAX_F2F_8197F 12
+#define BIT_MASK_WAKE_MAX_F2F_8197F 0x7
+#define BIT_WAKE_MAX_F2F_8197F(x) \
+ (((x) & BIT_MASK_WAKE_MAX_F2F_8197F) << BIT_SHIFT_WAKE_MAX_F2F_8197F)
+#define BITS_WAKE_MAX_F2F_8197F \
+ (BIT_MASK_WAKE_MAX_F2F_8197F << BIT_SHIFT_WAKE_MAX_F2F_8197F)
+#define BIT_CLEAR_WAKE_MAX_F2F_8197F(x) ((x) & (~BITS_WAKE_MAX_F2F_8197F))
+#define BIT_GET_WAKE_MAX_F2F_8197F(x) \
+ (((x) >> BIT_SHIFT_WAKE_MAX_F2F_8197F) & BIT_MASK_WAKE_MAX_F2F_8197F)
+#define BIT_SET_WAKE_MAX_F2F_8197F(x, v) \
+ (BIT_CLEAR_WAKE_MAX_F2F_8197F(x) | BIT_WAKE_MAX_F2F_8197F(v))
+
+#define BIT_SHIFT_WAKE_MIN_F2F_8197F 8
+#define BIT_MASK_WAKE_MIN_F2F_8197F 0x7
+#define BIT_WAKE_MIN_F2F_8197F(x) \
+ (((x) & BIT_MASK_WAKE_MIN_F2F_8197F) << BIT_SHIFT_WAKE_MIN_F2F_8197F)
+#define BITS_WAKE_MIN_F2F_8197F \
+ (BIT_MASK_WAKE_MIN_F2F_8197F << BIT_SHIFT_WAKE_MIN_F2F_8197F)
+#define BIT_CLEAR_WAKE_MIN_F2F_8197F(x) ((x) & (~BITS_WAKE_MIN_F2F_8197F))
+#define BIT_GET_WAKE_MIN_F2F_8197F(x) \
+ (((x) >> BIT_SHIFT_WAKE_MIN_F2F_8197F) & BIT_MASK_WAKE_MIN_F2F_8197F)
+#define BIT_SET_WAKE_MIN_F2F_8197F(x, v) \
+ (BIT_CLEAR_WAKE_MIN_F2F_8197F(x) | BIT_WAKE_MIN_F2F_8197F(v))
+
+#define BIT_APP_CPU_ACT_V1_8197F BIT(3)
+#define BIT_APP_OBFF_V1_8197F BIT(2)
+#define BIT_APP_IDLE_V1_8197F BIT(1)
+#define BIT_APP_INIT_V1_8197F BIT(0)
+
+/* 2 REG_OBFF_CTRL2_TIMER_8197F */
+
+#define BIT_SHIFT_RX_HIGH_TIMER_IDX_8197F 24
+#define BIT_MASK_RX_HIGH_TIMER_IDX_8197F 0x7
+#define BIT_RX_HIGH_TIMER_IDX_8197F(x) \
+ (((x) & BIT_MASK_RX_HIGH_TIMER_IDX_8197F) \
+ << BIT_SHIFT_RX_HIGH_TIMER_IDX_8197F)
+#define BITS_RX_HIGH_TIMER_IDX_8197F \
+ (BIT_MASK_RX_HIGH_TIMER_IDX_8197F << BIT_SHIFT_RX_HIGH_TIMER_IDX_8197F)
+#define BIT_CLEAR_RX_HIGH_TIMER_IDX_8197F(x) \
+ ((x) & (~BITS_RX_HIGH_TIMER_IDX_8197F))
+#define BIT_GET_RX_HIGH_TIMER_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8197F) & \
+ BIT_MASK_RX_HIGH_TIMER_IDX_8197F)
+#define BIT_SET_RX_HIGH_TIMER_IDX_8197F(x, v) \
+ (BIT_CLEAR_RX_HIGH_TIMER_IDX_8197F(x) | BIT_RX_HIGH_TIMER_IDX_8197F(v))
+
+#define BIT_SHIFT_RX_MED_TIMER_IDX_8197F 16
+#define BIT_MASK_RX_MED_TIMER_IDX_8197F 0x7
+#define BIT_RX_MED_TIMER_IDX_8197F(x) \
+ (((x) & BIT_MASK_RX_MED_TIMER_IDX_8197F) \
+ << BIT_SHIFT_RX_MED_TIMER_IDX_8197F)
+#define BITS_RX_MED_TIMER_IDX_8197F \
+ (BIT_MASK_RX_MED_TIMER_IDX_8197F << BIT_SHIFT_RX_MED_TIMER_IDX_8197F)
+#define BIT_CLEAR_RX_MED_TIMER_IDX_8197F(x) \
+ ((x) & (~BITS_RX_MED_TIMER_IDX_8197F))
+#define BIT_GET_RX_MED_TIMER_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8197F) & \
+ BIT_MASK_RX_MED_TIMER_IDX_8197F)
+#define BIT_SET_RX_MED_TIMER_IDX_8197F(x, v) \
+ (BIT_CLEAR_RX_MED_TIMER_IDX_8197F(x) | BIT_RX_MED_TIMER_IDX_8197F(v))
+
+#define BIT_SHIFT_RX_LOW_TIMER_IDX_8197F 8
+#define BIT_MASK_RX_LOW_TIMER_IDX_8197F 0x7
+#define BIT_RX_LOW_TIMER_IDX_8197F(x) \
+ (((x) & BIT_MASK_RX_LOW_TIMER_IDX_8197F) \
+ << BIT_SHIFT_RX_LOW_TIMER_IDX_8197F)
+#define BITS_RX_LOW_TIMER_IDX_8197F \
+ (BIT_MASK_RX_LOW_TIMER_IDX_8197F << BIT_SHIFT_RX_LOW_TIMER_IDX_8197F)
+#define BIT_CLEAR_RX_LOW_TIMER_IDX_8197F(x) \
+ ((x) & (~BITS_RX_LOW_TIMER_IDX_8197F))
+#define BIT_GET_RX_LOW_TIMER_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8197F) & \
+ BIT_MASK_RX_LOW_TIMER_IDX_8197F)
+#define BIT_SET_RX_LOW_TIMER_IDX_8197F(x, v) \
+ (BIT_CLEAR_RX_LOW_TIMER_IDX_8197F(x) | BIT_RX_LOW_TIMER_IDX_8197F(v))
+
+#define BIT_SHIFT_OBFF_INT_TIMER_IDX_8197F 0
+#define BIT_MASK_OBFF_INT_TIMER_IDX_8197F 0x7
+#define BIT_OBFF_INT_TIMER_IDX_8197F(x) \
+ (((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8197F) \
+ << BIT_SHIFT_OBFF_INT_TIMER_IDX_8197F)
+#define BITS_OBFF_INT_TIMER_IDX_8197F \
+ (BIT_MASK_OBFF_INT_TIMER_IDX_8197F \
+ << BIT_SHIFT_OBFF_INT_TIMER_IDX_8197F)
+#define BIT_CLEAR_OBFF_INT_TIMER_IDX_8197F(x) \
+ ((x) & (~BITS_OBFF_INT_TIMER_IDX_8197F))
+#define BIT_GET_OBFF_INT_TIMER_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8197F) & \
+ BIT_MASK_OBFF_INT_TIMER_IDX_8197F)
+#define BIT_SET_OBFF_INT_TIMER_IDX_8197F(x, v) \
+ (BIT_CLEAR_OBFF_INT_TIMER_IDX_8197F(x) | \
+ BIT_OBFF_INT_TIMER_IDX_8197F(v))
+
+/* 2 REG_LTR_CTRL_BASIC_8197F */
+#define BIT_LTR_EN_V1_8197F BIT(31)
+#define BIT_LTR_HW_EN_V1_8197F BIT(30)
+#define BIT_LRT_ACT_CTS_EN_8197F BIT(29)
+#define BIT_LTR_ACT_RXPKT_EN_8197F BIT(28)
+#define BIT_LTR_ACT_RXDMA_EN_8197F BIT(27)
+#define BIT_LTR_IDLE_NO_SNOOP_8197F BIT(26)
+#define BIT_SPDUP_MGTPKT_8197F BIT(25)
+#define BIT_RX_AGG_EN_8197F BIT(24)
+#define BIT_APP_LTR_ACT_8197F BIT(23)
+#define BIT_APP_LTR_IDLE_8197F BIT(22)
+
+#define BIT_SHIFT_HIGH_RATE_TRIG_SEL_8197F 20
+#define BIT_MASK_HIGH_RATE_TRIG_SEL_8197F 0x3
+#define BIT_HIGH_RATE_TRIG_SEL_8197F(x) \
+ (((x) & BIT_MASK_HIGH_RATE_TRIG_SEL_8197F) \
+ << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8197F)
+#define BITS_HIGH_RATE_TRIG_SEL_8197F \
+ (BIT_MASK_HIGH_RATE_TRIG_SEL_8197F \
+ << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8197F)
+#define BIT_CLEAR_HIGH_RATE_TRIG_SEL_8197F(x) \
+ ((x) & (~BITS_HIGH_RATE_TRIG_SEL_8197F))
+#define BIT_GET_HIGH_RATE_TRIG_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8197F) & \
+ BIT_MASK_HIGH_RATE_TRIG_SEL_8197F)
+#define BIT_SET_HIGH_RATE_TRIG_SEL_8197F(x, v) \
+ (BIT_CLEAR_HIGH_RATE_TRIG_SEL_8197F(x) | \
+ BIT_HIGH_RATE_TRIG_SEL_8197F(v))
+
+#define BIT_SHIFT_MED_RATE_TRIG_SEL_8197F 18
+#define BIT_MASK_MED_RATE_TRIG_SEL_8197F 0x3
+#define BIT_MED_RATE_TRIG_SEL_8197F(x) \
+ (((x) & BIT_MASK_MED_RATE_TRIG_SEL_8197F) \
+ << BIT_SHIFT_MED_RATE_TRIG_SEL_8197F)
+#define BITS_MED_RATE_TRIG_SEL_8197F \
+ (BIT_MASK_MED_RATE_TRIG_SEL_8197F << BIT_SHIFT_MED_RATE_TRIG_SEL_8197F)
+#define BIT_CLEAR_MED_RATE_TRIG_SEL_8197F(x) \
+ ((x) & (~BITS_MED_RATE_TRIG_SEL_8197F))
+#define BIT_GET_MED_RATE_TRIG_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8197F) & \
+ BIT_MASK_MED_RATE_TRIG_SEL_8197F)
+#define BIT_SET_MED_RATE_TRIG_SEL_8197F(x, v) \
+ (BIT_CLEAR_MED_RATE_TRIG_SEL_8197F(x) | BIT_MED_RATE_TRIG_SEL_8197F(v))
+
+#define BIT_SHIFT_LOW_RATE_TRIG_SEL_8197F 16
+#define BIT_MASK_LOW_RATE_TRIG_SEL_8197F 0x3
+#define BIT_LOW_RATE_TRIG_SEL_8197F(x) \
+ (((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8197F) \
+ << BIT_SHIFT_LOW_RATE_TRIG_SEL_8197F)
+#define BITS_LOW_RATE_TRIG_SEL_8197F \
+ (BIT_MASK_LOW_RATE_TRIG_SEL_8197F << BIT_SHIFT_LOW_RATE_TRIG_SEL_8197F)
+#define BIT_CLEAR_LOW_RATE_TRIG_SEL_8197F(x) \
+ ((x) & (~BITS_LOW_RATE_TRIG_SEL_8197F))
+#define BIT_GET_LOW_RATE_TRIG_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8197F) & \
+ BIT_MASK_LOW_RATE_TRIG_SEL_8197F)
+#define BIT_SET_LOW_RATE_TRIG_SEL_8197F(x, v) \
+ (BIT_CLEAR_LOW_RATE_TRIG_SEL_8197F(x) | BIT_LOW_RATE_TRIG_SEL_8197F(v))
+
+#define BIT_SHIFT_HIGH_RATE_BD_IDX_8197F 8
+#define BIT_MASK_HIGH_RATE_BD_IDX_8197F 0x7f
+#define BIT_HIGH_RATE_BD_IDX_8197F(x) \
+ (((x) & BIT_MASK_HIGH_RATE_BD_IDX_8197F) \
+ << BIT_SHIFT_HIGH_RATE_BD_IDX_8197F)
+#define BITS_HIGH_RATE_BD_IDX_8197F \
+ (BIT_MASK_HIGH_RATE_BD_IDX_8197F << BIT_SHIFT_HIGH_RATE_BD_IDX_8197F)
+#define BIT_CLEAR_HIGH_RATE_BD_IDX_8197F(x) \
+ ((x) & (~BITS_HIGH_RATE_BD_IDX_8197F))
+#define BIT_GET_HIGH_RATE_BD_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8197F) & \
+ BIT_MASK_HIGH_RATE_BD_IDX_8197F)
+#define BIT_SET_HIGH_RATE_BD_IDX_8197F(x, v) \
+ (BIT_CLEAR_HIGH_RATE_BD_IDX_8197F(x) | BIT_HIGH_RATE_BD_IDX_8197F(v))
+
+#define BIT_SHIFT_LOW_RATE_BD_IDX_8197F 0
+#define BIT_MASK_LOW_RATE_BD_IDX_8197F 0x7f
+#define BIT_LOW_RATE_BD_IDX_8197F(x) \
+ (((x) & BIT_MASK_LOW_RATE_BD_IDX_8197F) \
+ << BIT_SHIFT_LOW_RATE_BD_IDX_8197F)
+#define BITS_LOW_RATE_BD_IDX_8197F \
+ (BIT_MASK_LOW_RATE_BD_IDX_8197F << BIT_SHIFT_LOW_RATE_BD_IDX_8197F)
+#define BIT_CLEAR_LOW_RATE_BD_IDX_8197F(x) ((x) & (~BITS_LOW_RATE_BD_IDX_8197F))
+#define BIT_GET_LOW_RATE_BD_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8197F) & \
+ BIT_MASK_LOW_RATE_BD_IDX_8197F)
+#define BIT_SET_LOW_RATE_BD_IDX_8197F(x, v) \
+ (BIT_CLEAR_LOW_RATE_BD_IDX_8197F(x) | BIT_LOW_RATE_BD_IDX_8197F(v))
+
+/* 2 REG_LTR_CTRL2_TIMER_THRESHOLD_8197F */
+
+#define BIT_SHIFT_RX_EMPTY_TIMER_IDX_8197F 24
+#define BIT_MASK_RX_EMPTY_TIMER_IDX_8197F 0x7
+#define BIT_RX_EMPTY_TIMER_IDX_8197F(x) \
+ (((x) & BIT_MASK_RX_EMPTY_TIMER_IDX_8197F) \
+ << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8197F)
+#define BITS_RX_EMPTY_TIMER_IDX_8197F \
+ (BIT_MASK_RX_EMPTY_TIMER_IDX_8197F \
+ << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8197F)
+#define BIT_CLEAR_RX_EMPTY_TIMER_IDX_8197F(x) \
+ ((x) & (~BITS_RX_EMPTY_TIMER_IDX_8197F))
+#define BIT_GET_RX_EMPTY_TIMER_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8197F) & \
+ BIT_MASK_RX_EMPTY_TIMER_IDX_8197F)
+#define BIT_SET_RX_EMPTY_TIMER_IDX_8197F(x, v) \
+ (BIT_CLEAR_RX_EMPTY_TIMER_IDX_8197F(x) | \
+ BIT_RX_EMPTY_TIMER_IDX_8197F(v))
+
+#define BIT_SHIFT_RX_AFULL_TH_IDX_8197F 20
+#define BIT_MASK_RX_AFULL_TH_IDX_8197F 0x7
+#define BIT_RX_AFULL_TH_IDX_8197F(x) \
+ (((x) & BIT_MASK_RX_AFULL_TH_IDX_8197F) \
+ << BIT_SHIFT_RX_AFULL_TH_IDX_8197F)
+#define BITS_RX_AFULL_TH_IDX_8197F \
+ (BIT_MASK_RX_AFULL_TH_IDX_8197F << BIT_SHIFT_RX_AFULL_TH_IDX_8197F)
+#define BIT_CLEAR_RX_AFULL_TH_IDX_8197F(x) ((x) & (~BITS_RX_AFULL_TH_IDX_8197F))
+#define BIT_GET_RX_AFULL_TH_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8197F) & \
+ BIT_MASK_RX_AFULL_TH_IDX_8197F)
+#define BIT_SET_RX_AFULL_TH_IDX_8197F(x, v) \
+ (BIT_CLEAR_RX_AFULL_TH_IDX_8197F(x) | BIT_RX_AFULL_TH_IDX_8197F(v))
+
+#define BIT_SHIFT_RX_HIGH_TH_IDX_8197F 16
+#define BIT_MASK_RX_HIGH_TH_IDX_8197F 0x7
+#define BIT_RX_HIGH_TH_IDX_8197F(x) \
+ (((x) & BIT_MASK_RX_HIGH_TH_IDX_8197F) \
+ << BIT_SHIFT_RX_HIGH_TH_IDX_8197F)
+#define BITS_RX_HIGH_TH_IDX_8197F \
+ (BIT_MASK_RX_HIGH_TH_IDX_8197F << BIT_SHIFT_RX_HIGH_TH_IDX_8197F)
+#define BIT_CLEAR_RX_HIGH_TH_IDX_8197F(x) ((x) & (~BITS_RX_HIGH_TH_IDX_8197F))
+#define BIT_GET_RX_HIGH_TH_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8197F) & \
+ BIT_MASK_RX_HIGH_TH_IDX_8197F)
+#define BIT_SET_RX_HIGH_TH_IDX_8197F(x, v) \
+ (BIT_CLEAR_RX_HIGH_TH_IDX_8197F(x) | BIT_RX_HIGH_TH_IDX_8197F(v))
+
+#define BIT_SHIFT_RX_MED_TH_IDX_8197F 12
+#define BIT_MASK_RX_MED_TH_IDX_8197F 0x7
+#define BIT_RX_MED_TH_IDX_8197F(x) \
+ (((x) & BIT_MASK_RX_MED_TH_IDX_8197F) << BIT_SHIFT_RX_MED_TH_IDX_8197F)
+#define BITS_RX_MED_TH_IDX_8197F \
+ (BIT_MASK_RX_MED_TH_IDX_8197F << BIT_SHIFT_RX_MED_TH_IDX_8197F)
+#define BIT_CLEAR_RX_MED_TH_IDX_8197F(x) ((x) & (~BITS_RX_MED_TH_IDX_8197F))
+#define BIT_GET_RX_MED_TH_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_RX_MED_TH_IDX_8197F) & BIT_MASK_RX_MED_TH_IDX_8197F)
+#define BIT_SET_RX_MED_TH_IDX_8197F(x, v) \
+ (BIT_CLEAR_RX_MED_TH_IDX_8197F(x) | BIT_RX_MED_TH_IDX_8197F(v))
+
+#define BIT_SHIFT_RX_LOW_TH_IDX_8197F 8
+#define BIT_MASK_RX_LOW_TH_IDX_8197F 0x7
+#define BIT_RX_LOW_TH_IDX_8197F(x) \
+ (((x) & BIT_MASK_RX_LOW_TH_IDX_8197F) << BIT_SHIFT_RX_LOW_TH_IDX_8197F)
+#define BITS_RX_LOW_TH_IDX_8197F \
+ (BIT_MASK_RX_LOW_TH_IDX_8197F << BIT_SHIFT_RX_LOW_TH_IDX_8197F)
+#define BIT_CLEAR_RX_LOW_TH_IDX_8197F(x) ((x) & (~BITS_RX_LOW_TH_IDX_8197F))
+#define BIT_GET_RX_LOW_TH_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8197F) & BIT_MASK_RX_LOW_TH_IDX_8197F)
+#define BIT_SET_RX_LOW_TH_IDX_8197F(x, v) \
+ (BIT_CLEAR_RX_LOW_TH_IDX_8197F(x) | BIT_RX_LOW_TH_IDX_8197F(v))
+
+#define BIT_SHIFT_LTR_SPACE_IDX_8197F 4
+#define BIT_MASK_LTR_SPACE_IDX_8197F 0x3
+#define BIT_LTR_SPACE_IDX_8197F(x) \
+ (((x) & BIT_MASK_LTR_SPACE_IDX_8197F) << BIT_SHIFT_LTR_SPACE_IDX_8197F)
+#define BITS_LTR_SPACE_IDX_8197F \
+ (BIT_MASK_LTR_SPACE_IDX_8197F << BIT_SHIFT_LTR_SPACE_IDX_8197F)
+#define BIT_CLEAR_LTR_SPACE_IDX_8197F(x) ((x) & (~BITS_LTR_SPACE_IDX_8197F))
+#define BIT_GET_LTR_SPACE_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_LTR_SPACE_IDX_8197F) & BIT_MASK_LTR_SPACE_IDX_8197F)
+#define BIT_SET_LTR_SPACE_IDX_8197F(x, v) \
+ (BIT_CLEAR_LTR_SPACE_IDX_8197F(x) | BIT_LTR_SPACE_IDX_8197F(v))
+
+#define BIT_SHIFT_LTR_IDLE_TIMER_IDX_8197F 0
+#define BIT_MASK_LTR_IDLE_TIMER_IDX_8197F 0x7
+#define BIT_LTR_IDLE_TIMER_IDX_8197F(x) \
+ (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8197F) \
+ << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8197F)
+#define BITS_LTR_IDLE_TIMER_IDX_8197F \
+ (BIT_MASK_LTR_IDLE_TIMER_IDX_8197F \
+ << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8197F)
+#define BIT_CLEAR_LTR_IDLE_TIMER_IDX_8197F(x) \
+ ((x) & (~BITS_LTR_IDLE_TIMER_IDX_8197F))
+#define BIT_GET_LTR_IDLE_TIMER_IDX_8197F(x) \
+ (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8197F) & \
+ BIT_MASK_LTR_IDLE_TIMER_IDX_8197F)
+#define BIT_SET_LTR_IDLE_TIMER_IDX_8197F(x, v) \
+ (BIT_CLEAR_LTR_IDLE_TIMER_IDX_8197F(x) | \
+ BIT_LTR_IDLE_TIMER_IDX_8197F(v))
+
+/* 2 REG_LTR_IDLE_LATENCY_V1_8197F */
+
+#define BIT_SHIFT_LTR_IDLE_L_8197F 0
+#define BIT_MASK_LTR_IDLE_L_8197F 0xffffffffL
+#define BIT_LTR_IDLE_L_8197F(x) \
+ (((x) & BIT_MASK_LTR_IDLE_L_8197F) << BIT_SHIFT_LTR_IDLE_L_8197F)
+#define BITS_LTR_IDLE_L_8197F \
+ (BIT_MASK_LTR_IDLE_L_8197F << BIT_SHIFT_LTR_IDLE_L_8197F)
+#define BIT_CLEAR_LTR_IDLE_L_8197F(x) ((x) & (~BITS_LTR_IDLE_L_8197F))
+#define BIT_GET_LTR_IDLE_L_8197F(x) \
+ (((x) >> BIT_SHIFT_LTR_IDLE_L_8197F) & BIT_MASK_LTR_IDLE_L_8197F)
+#define BIT_SET_LTR_IDLE_L_8197F(x, v) \
+ (BIT_CLEAR_LTR_IDLE_L_8197F(x) | BIT_LTR_IDLE_L_8197F(v))
+
+/* 2 REG_LTR_ACTIVE_LATENCY_V1_8197F */
+
+#define BIT_SHIFT_LTR_ACT_L_8197F 0
+#define BIT_MASK_LTR_ACT_L_8197F 0xffffffffL
+#define BIT_LTR_ACT_L_8197F(x) \
+ (((x) & BIT_MASK_LTR_ACT_L_8197F) << BIT_SHIFT_LTR_ACT_L_8197F)
+#define BITS_LTR_ACT_L_8197F \
+ (BIT_MASK_LTR_ACT_L_8197F << BIT_SHIFT_LTR_ACT_L_8197F)
+#define BIT_CLEAR_LTR_ACT_L_8197F(x) ((x) & (~BITS_LTR_ACT_L_8197F))
+#define BIT_GET_LTR_ACT_L_8197F(x) \
+ (((x) >> BIT_SHIFT_LTR_ACT_L_8197F) & BIT_MASK_LTR_ACT_L_8197F)
+#define BIT_SET_LTR_ACT_L_8197F(x, v) \
+ (BIT_CLEAR_LTR_ACT_L_8197F(x) | BIT_LTR_ACT_L_8197F(v))
+
+/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_8197F */
+#define BIT_APPEND_MACID_IN_RESP_EN_8197F BIT(50)
+#define BIT_ADDR2_MATCH_EN_8197F BIT(49)
+#define BIT_ANTTRN_EN_8197F BIT(48)
+
+#define BIT_SHIFT_TRAIN_STA_ADDR_8197F 0
+#define BIT_MASK_TRAIN_STA_ADDR_8197F 0xffffffffffffL
+#define BIT_TRAIN_STA_ADDR_8197F(x) \
+ (((x) & BIT_MASK_TRAIN_STA_ADDR_8197F) \
+ << BIT_SHIFT_TRAIN_STA_ADDR_8197F)
+#define BITS_TRAIN_STA_ADDR_8197F \
+ (BIT_MASK_TRAIN_STA_ADDR_8197F << BIT_SHIFT_TRAIN_STA_ADDR_8197F)
+#define BIT_CLEAR_TRAIN_STA_ADDR_8197F(x) ((x) & (~BITS_TRAIN_STA_ADDR_8197F))
+#define BIT_GET_TRAIN_STA_ADDR_8197F(x) \
+ (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_8197F) & \
+ BIT_MASK_TRAIN_STA_ADDR_8197F)
+#define BIT_SET_TRAIN_STA_ADDR_8197F(x, v) \
+ (BIT_CLEAR_TRAIN_STA_ADDR_8197F(x) | BIT_TRAIN_STA_ADDR_8197F(v))
+
+/* 2 REG_RSVD_0X7B4_8197F */
+
+/* 2 REG_WMAC_PKTCNT_RWD_8197F */
+
+#define BIT_SHIFT_PKTCNT_BSSIDMAP_8197F 4
+#define BIT_MASK_PKTCNT_BSSIDMAP_8197F 0xf
+#define BIT_PKTCNT_BSSIDMAP_8197F(x) \
+ (((x) & BIT_MASK_PKTCNT_BSSIDMAP_8197F) \
+ << BIT_SHIFT_PKTCNT_BSSIDMAP_8197F)
+#define BITS_PKTCNT_BSSIDMAP_8197F \
+ (BIT_MASK_PKTCNT_BSSIDMAP_8197F << BIT_SHIFT_PKTCNT_BSSIDMAP_8197F)
+#define BIT_CLEAR_PKTCNT_BSSIDMAP_8197F(x) ((x) & (~BITS_PKTCNT_BSSIDMAP_8197F))
+#define BIT_GET_PKTCNT_BSSIDMAP_8197F(x) \
+ (((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP_8197F) & \
+ BIT_MASK_PKTCNT_BSSIDMAP_8197F)
+#define BIT_SET_PKTCNT_BSSIDMAP_8197F(x, v) \
+ (BIT_CLEAR_PKTCNT_BSSIDMAP_8197F(x) | BIT_PKTCNT_BSSIDMAP_8197F(v))
+
+#define BIT_PKTCNT_CNTRST_8197F BIT(1)
+#define BIT_PKTCNT_CNTEN_8197F BIT(0)
+
+/* 2 REG_WMAC_PKTCNT_CTRL_8197F */
+#define BIT_WMAC_PKTCNT_TRST_8197F BIT(9)
+#define BIT_WMAC_PKTCNT_FEN_8197F BIT(8)
+
+#define BIT_SHIFT_WMAC_PKTCNT_CFGAD_8197F 0
+#define BIT_MASK_WMAC_PKTCNT_CFGAD_8197F 0xff
+#define BIT_WMAC_PKTCNT_CFGAD_8197F(x) \
+ (((x) & BIT_MASK_WMAC_PKTCNT_CFGAD_8197F) \
+ << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8197F)
+#define BITS_WMAC_PKTCNT_CFGAD_8197F \
+ (BIT_MASK_WMAC_PKTCNT_CFGAD_8197F << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8197F)
+#define BIT_CLEAR_WMAC_PKTCNT_CFGAD_8197F(x) \
+ ((x) & (~BITS_WMAC_PKTCNT_CFGAD_8197F))
+#define BIT_GET_WMAC_PKTCNT_CFGAD_8197F(x) \
+ (((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD_8197F) & \
+ BIT_MASK_WMAC_PKTCNT_CFGAD_8197F)
+#define BIT_SET_WMAC_PKTCNT_CFGAD_8197F(x, v) \
+ (BIT_CLEAR_WMAC_PKTCNT_CFGAD_8197F(x) | BIT_WMAC_PKTCNT_CFGAD_8197F(v))
+
+/* 2 REG_IQ_DUMP_8197F */
+
+#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8197F (64 & CPU_OPT_WIDTH)
+#define BIT_MASK_R_WMAC_MATCH_REF_MAC_8197F 0xffffffffL
+#define BIT_R_WMAC_MATCH_REF_MAC_8197F(x) \
+ (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_8197F) \
+ << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8197F)
+#define BITS_R_WMAC_MATCH_REF_MAC_8197F \
+ (BIT_MASK_R_WMAC_MATCH_REF_MAC_8197F \
+ << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8197F)
+#define BIT_CLEAR_R_WMAC_MATCH_REF_MAC_8197F(x) \
+ ((x) & (~BITS_R_WMAC_MATCH_REF_MAC_8197F))
+#define BIT_GET_R_WMAC_MATCH_REF_MAC_8197F(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8197F) & \
+ BIT_MASK_R_WMAC_MATCH_REF_MAC_8197F)
+#define BIT_SET_R_WMAC_MATCH_REF_MAC_8197F(x, v) \
+ (BIT_CLEAR_R_WMAC_MATCH_REF_MAC_8197F(x) | \
+ BIT_R_WMAC_MATCH_REF_MAC_8197F(v))
+
+#define BIT_SHIFT_R_WMAC_MASK_LA_MAC_8197F (32 & CPU_OPT_WIDTH)
+#define BIT_MASK_R_WMAC_MASK_LA_MAC_8197F 0xffffffffL
+#define BIT_R_WMAC_MASK_LA_MAC_8197F(x) \
+ (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_8197F) \
+ << BIT_SHIFT_R_WMAC_MASK_LA_MAC_8197F)
+#define BITS_R_WMAC_MASK_LA_MAC_8197F \
+ (BIT_MASK_R_WMAC_MASK_LA_MAC_8197F \
+ << BIT_SHIFT_R_WMAC_MASK_LA_MAC_8197F)
+#define BIT_CLEAR_R_WMAC_MASK_LA_MAC_8197F(x) \
+ ((x) & (~BITS_R_WMAC_MASK_LA_MAC_8197F))
+#define BIT_GET_R_WMAC_MASK_LA_MAC_8197F(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_8197F) & \
+ BIT_MASK_R_WMAC_MASK_LA_MAC_8197F)
+#define BIT_SET_R_WMAC_MASK_LA_MAC_8197F(x, v) \
+ (BIT_CLEAR_R_WMAC_MASK_LA_MAC_8197F(x) | \
+ BIT_R_WMAC_MASK_LA_MAC_8197F(v))
+
+#define BIT_SHIFT_DUMP_OK_ADDR_8197F 16
+#define BIT_MASK_DUMP_OK_ADDR_8197F 0xffff
+#define BIT_DUMP_OK_ADDR_8197F(x) \
+ (((x) & BIT_MASK_DUMP_OK_ADDR_8197F) << BIT_SHIFT_DUMP_OK_ADDR_8197F)
+#define BITS_DUMP_OK_ADDR_8197F \
+ (BIT_MASK_DUMP_OK_ADDR_8197F << BIT_SHIFT_DUMP_OK_ADDR_8197F)
+#define BIT_CLEAR_DUMP_OK_ADDR_8197F(x) ((x) & (~BITS_DUMP_OK_ADDR_8197F))
+#define BIT_GET_DUMP_OK_ADDR_8197F(x) \
+ (((x) >> BIT_SHIFT_DUMP_OK_ADDR_8197F) & BIT_MASK_DUMP_OK_ADDR_8197F)
+#define BIT_SET_DUMP_OK_ADDR_8197F(x, v) \
+ (BIT_CLEAR_DUMP_OK_ADDR_8197F(x) | BIT_DUMP_OK_ADDR_8197F(v))
+
+#define BIT_SHIFT_R_TRIG_TIME_SEL_8197F 8
+#define BIT_MASK_R_TRIG_TIME_SEL_8197F 0x7f
+#define BIT_R_TRIG_TIME_SEL_8197F(x) \
+ (((x) & BIT_MASK_R_TRIG_TIME_SEL_8197F) \
+ << BIT_SHIFT_R_TRIG_TIME_SEL_8197F)
+#define BITS_R_TRIG_TIME_SEL_8197F \
+ (BIT_MASK_R_TRIG_TIME_SEL_8197F << BIT_SHIFT_R_TRIG_TIME_SEL_8197F)
+#define BIT_CLEAR_R_TRIG_TIME_SEL_8197F(x) ((x) & (~BITS_R_TRIG_TIME_SEL_8197F))
+#define BIT_GET_R_TRIG_TIME_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8197F) & \
+ BIT_MASK_R_TRIG_TIME_SEL_8197F)
+#define BIT_SET_R_TRIG_TIME_SEL_8197F(x, v) \
+ (BIT_CLEAR_R_TRIG_TIME_SEL_8197F(x) | BIT_R_TRIG_TIME_SEL_8197F(v))
+
+#define BIT_SHIFT_R_MAC_TRIG_SEL_8197F 6
+#define BIT_MASK_R_MAC_TRIG_SEL_8197F 0x3
+#define BIT_R_MAC_TRIG_SEL_8197F(x) \
+ (((x) & BIT_MASK_R_MAC_TRIG_SEL_8197F) \
+ << BIT_SHIFT_R_MAC_TRIG_SEL_8197F)
+#define BITS_R_MAC_TRIG_SEL_8197F \
+ (BIT_MASK_R_MAC_TRIG_SEL_8197F << BIT_SHIFT_R_MAC_TRIG_SEL_8197F)
+#define BIT_CLEAR_R_MAC_TRIG_SEL_8197F(x) ((x) & (~BITS_R_MAC_TRIG_SEL_8197F))
+#define BIT_GET_R_MAC_TRIG_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8197F) & \
+ BIT_MASK_R_MAC_TRIG_SEL_8197F)
+#define BIT_SET_R_MAC_TRIG_SEL_8197F(x, v) \
+ (BIT_CLEAR_R_MAC_TRIG_SEL_8197F(x) | BIT_R_MAC_TRIG_SEL_8197F(v))
+
+#define BIT_MAC_TRIG_REG_8197F BIT(5)
+
+#define BIT_SHIFT_R_LEVEL_PULSE_SEL_8197F 3
+#define BIT_MASK_R_LEVEL_PULSE_SEL_8197F 0x3
+#define BIT_R_LEVEL_PULSE_SEL_8197F(x) \
+ (((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8197F) \
+ << BIT_SHIFT_R_LEVEL_PULSE_SEL_8197F)
+#define BITS_R_LEVEL_PULSE_SEL_8197F \
+ (BIT_MASK_R_LEVEL_PULSE_SEL_8197F << BIT_SHIFT_R_LEVEL_PULSE_SEL_8197F)
+#define BIT_CLEAR_R_LEVEL_PULSE_SEL_8197F(x) \
+ ((x) & (~BITS_R_LEVEL_PULSE_SEL_8197F))
+#define BIT_GET_R_LEVEL_PULSE_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8197F) & \
+ BIT_MASK_R_LEVEL_PULSE_SEL_8197F)
+#define BIT_SET_R_LEVEL_PULSE_SEL_8197F(x, v) \
+ (BIT_CLEAR_R_LEVEL_PULSE_SEL_8197F(x) | BIT_R_LEVEL_PULSE_SEL_8197F(v))
+
+#define BIT_EN_LA_MAC_8197F BIT(2)
+#define BIT_R_EN_IQDUMP_8197F BIT(1)
+#define BIT_R_IQDATA_DUMP_8197F BIT(0)
+
+/* 2 REG_WMAC_FTM_CTL_8197F */
+#define BIT_RXFTM_TXACK_SC_8197F BIT(6)
+#define BIT_RXFTM_TXACK_BW_8197F BIT(5)
+#define BIT_RXFTM_EN_8197F BIT(3)
+#define BIT_RXFTMREQ_BYDRV_8197F BIT(2)
+#define BIT_RXFTMREQ_EN_8197F BIT(1)
+#define BIT_FTM_EN_8197F BIT(0)
+
+/* 2 REG_IQ_DUMP_EXT_8197F */
+
+#define BIT_SHIFT_R_TIME_UNIT_SEL_8197F 0
+#define BIT_MASK_R_TIME_UNIT_SEL_8197F 0x7
+#define BIT_R_TIME_UNIT_SEL_8197F(x) \
+ (((x) & BIT_MASK_R_TIME_UNIT_SEL_8197F) \
+ << BIT_SHIFT_R_TIME_UNIT_SEL_8197F)
+#define BITS_R_TIME_UNIT_SEL_8197F \
+ (BIT_MASK_R_TIME_UNIT_SEL_8197F << BIT_SHIFT_R_TIME_UNIT_SEL_8197F)
+#define BIT_CLEAR_R_TIME_UNIT_SEL_8197F(x) ((x) & (~BITS_R_TIME_UNIT_SEL_8197F))
+#define BIT_GET_R_TIME_UNIT_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_R_TIME_UNIT_SEL_8197F) & \
+ BIT_MASK_R_TIME_UNIT_SEL_8197F)
+#define BIT_SET_R_TIME_UNIT_SEL_8197F(x, v) \
+ (BIT_CLEAR_R_TIME_UNIT_SEL_8197F(x) | BIT_R_TIME_UNIT_SEL_8197F(v))
+
+/* 2 REG_OFDM_CCK_LEN_MASK_8197F */
+
+#define BIT_SHIFT_R_WMAC_RX_FIL_LEN_8197F (64 & CPU_OPT_WIDTH)
+#define BIT_MASK_R_WMAC_RX_FIL_LEN_8197F 0xffff
+#define BIT_R_WMAC_RX_FIL_LEN_8197F(x) \
+ (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_8197F) \
+ << BIT_SHIFT_R_WMAC_RX_FIL_LEN_8197F)
+#define BITS_R_WMAC_RX_FIL_LEN_8197F \
+ (BIT_MASK_R_WMAC_RX_FIL_LEN_8197F << BIT_SHIFT_R_WMAC_RX_FIL_LEN_8197F)
+#define BIT_CLEAR_R_WMAC_RX_FIL_LEN_8197F(x) \
+ ((x) & (~BITS_R_WMAC_RX_FIL_LEN_8197F))
+#define BIT_GET_R_WMAC_RX_FIL_LEN_8197F(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_8197F) & \
+ BIT_MASK_R_WMAC_RX_FIL_LEN_8197F)
+#define BIT_SET_R_WMAC_RX_FIL_LEN_8197F(x, v) \
+ (BIT_CLEAR_R_WMAC_RX_FIL_LEN_8197F(x) | BIT_R_WMAC_RX_FIL_LEN_8197F(v))
+
+#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8197F (56 & CPU_OPT_WIDTH)
+#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8197F 0xff
+#define BIT_R_WMAC_RXFIFO_FULL_TH_8197F(x) \
+ (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8197F) \
+ << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8197F)
+#define BITS_R_WMAC_RXFIFO_FULL_TH_8197F \
+ (BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8197F \
+ << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8197F)
+#define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_8197F(x) \
+ ((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH_8197F))
+#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_8197F(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8197F) & \
+ BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8197F)
+#define BIT_SET_R_WMAC_RXFIFO_FULL_TH_8197F(x, v) \
+ (BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_8197F(x) | \
+ BIT_R_WMAC_RXFIFO_FULL_TH_8197F(v))
+
+#define BIT_R_WMAC_RX_SYNCFIFO_SYNC_8197F BIT(55)
+#define BIT_R_WMAC_RXRST_DLY_8197F BIT(54)
+#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP_8197F BIT(53)
+#define BIT_R_WMAC_SRCH_TXRPT_UA1_8197F BIT(52)
+#define BIT_R_WMAC_SRCH_TXRPT_TYPE_8197F BIT(51)
+#define BIT_R_WMAC_NDP_RST_8197F BIT(50)
+#define BIT_R_WMAC_POWINT_EN_8197F BIT(49)
+#define BIT_R_WMAC_SRCH_TXRPT_PERPKT_8197F BIT(48)
+#define BIT_R_WMAC_SRCH_TXRPT_MID_8197F BIT(47)
+#define BIT_R_WMAC_PFIN_TOEN_8197F BIT(46)
+#define BIT_R_WMAC_FIL_SECERR_8197F BIT(45)
+#define BIT_R_WMAC_FIL_CTLPKTLEN_8197F BIT(44)
+#define BIT_R_WMAC_FIL_FCTYPE_8197F BIT(43)
+#define BIT_R_WMAC_FIL_FCPROVER_8197F BIT(42)
+#define BIT_R_WMAC_PHYSTS_SNIF_8197F BIT(41)
+#define BIT_R_WMAC_PHYSTS_PLCP_8197F BIT(40)
+#define BIT_R_MAC_TCR_VBONF_RD_8197F BIT(39)
+#define BIT_R_WMAC_TCR_MPAR_NDP_8197F BIT(38)
+#define BIT_R_WMAC_NDP_FILTER_8197F BIT(37)
+#define BIT_R_WMAC_RXLEN_SEL_8197F BIT(36)
+#define BIT_R_WMAC_RXLEN_SEL1_8197F BIT(35)
+#define BIT_R_OFDM_FILTER_8197F BIT(34)
+#define BIT_R_WMAC_CHK_OFDM_LEN_8197F BIT(33)
+#define BIT_R_WMAC_CHK_CCK_LEN_8197F BIT(32)
+
+#define BIT_SHIFT_R_OFDM_LEN_8197F 26
+#define BIT_MASK_R_OFDM_LEN_8197F 0x3f
+#define BIT_R_OFDM_LEN_8197F(x) \
+ (((x) & BIT_MASK_R_OFDM_LEN_8197F) << BIT_SHIFT_R_OFDM_LEN_8197F)
+#define BITS_R_OFDM_LEN_8197F \
+ (BIT_MASK_R_OFDM_LEN_8197F << BIT_SHIFT_R_OFDM_LEN_8197F)
+#define BIT_CLEAR_R_OFDM_LEN_8197F(x) ((x) & (~BITS_R_OFDM_LEN_8197F))
+#define BIT_GET_R_OFDM_LEN_8197F(x) \
+ (((x) >> BIT_SHIFT_R_OFDM_LEN_8197F) & BIT_MASK_R_OFDM_LEN_8197F)
+#define BIT_SET_R_OFDM_LEN_8197F(x, v) \
+ (BIT_CLEAR_R_OFDM_LEN_8197F(x) | BIT_R_OFDM_LEN_8197F(v))
+
+#define BIT_SHIFT_R_CCK_LEN_8197F 0
+#define BIT_MASK_R_CCK_LEN_8197F 0xffff
+#define BIT_R_CCK_LEN_8197F(x) \
+ (((x) & BIT_MASK_R_CCK_LEN_8197F) << BIT_SHIFT_R_CCK_LEN_8197F)
+#define BITS_R_CCK_LEN_8197F \
+ (BIT_MASK_R_CCK_LEN_8197F << BIT_SHIFT_R_CCK_LEN_8197F)
+#define BIT_CLEAR_R_CCK_LEN_8197F(x) ((x) & (~BITS_R_CCK_LEN_8197F))
+#define BIT_GET_R_CCK_LEN_8197F(x) \
+ (((x) >> BIT_SHIFT_R_CCK_LEN_8197F) & BIT_MASK_R_CCK_LEN_8197F)
+#define BIT_SET_R_CCK_LEN_8197F(x, v) \
+ (BIT_CLEAR_R_CCK_LEN_8197F(x) | BIT_R_CCK_LEN_8197F(v))
+
+/* 2 REG_RX_FILTER_FUNCTION_8197F */
+#define BIT_R_WMAC_RXHANG_EN_8197F BIT(15)
+#define BIT_R_WMAC_MHRDDY_LATCH_8197F BIT(14)
+#define BIT_R_MHRDDY_CLR_8197F BIT(13)
+#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY1_8197F BIT(12)
+#define BIT_R_WMAC_DIS_VHT_PLCP_CHK_MU_8197F BIT(11)
+#define BIT_R_CHK_DELIMIT_LEN_8197F BIT(10)
+#define BIT_R_REAPTER_ADDR_MATCH_8197F BIT(9)
+#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY_8197F BIT(8)
+#define BIT_R_LATCH_MACHRDY_8197F BIT(7)
+#define BIT_R_WMAC_RXFIL_REND_8197F BIT(6)
+#define BIT_R_WMAC_MPDURDY_CLR_8197F BIT(5)
+#define BIT_R_WMAC_CLRRXSEC_8197F BIT(4)
+#define BIT_R_WMAC_RXFIL_RDEL_8197F BIT(3)
+#define BIT_R_WMAC_RXFIL_FCSE_8197F BIT(2)
+#define BIT_R_WMAC_RXFIL_MESH_DEL_8197F BIT(1)
+#define BIT_R_WMAC_RXFIL_MASKM_8197F BIT(0)
+
+/* 2 REG_NDP_SIG_8197F */
+
+#define BIT_SHIFT_R_WMAC_TXNDP_SIGB_8197F 0
+#define BIT_MASK_R_WMAC_TXNDP_SIGB_8197F 0x1fffff
+#define BIT_R_WMAC_TXNDP_SIGB_8197F(x) \
+ (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB_8197F) \
+ << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8197F)
+#define BITS_R_WMAC_TXNDP_SIGB_8197F \
+ (BIT_MASK_R_WMAC_TXNDP_SIGB_8197F << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8197F)
+#define BIT_CLEAR_R_WMAC_TXNDP_SIGB_8197F(x) \
+ ((x) & (~BITS_R_WMAC_TXNDP_SIGB_8197F))
+#define BIT_GET_R_WMAC_TXNDP_SIGB_8197F(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8197F) & \
+ BIT_MASK_R_WMAC_TXNDP_SIGB_8197F)
+#define BIT_SET_R_WMAC_TXNDP_SIGB_8197F(x, v) \
+ (BIT_CLEAR_R_WMAC_TXNDP_SIGB_8197F(x) | BIT_R_WMAC_TXNDP_SIGB_8197F(v))
+
+/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_8197F */
+
+#define BIT_SHIFT_R_MAC_DEBUG_8197F (32 & CPU_OPT_WIDTH)
+#define BIT_MASK_R_MAC_DEBUG_8197F 0xffffffffL
+#define BIT_R_MAC_DEBUG_8197F(x) \
+ (((x) & BIT_MASK_R_MAC_DEBUG_8197F) << BIT_SHIFT_R_MAC_DEBUG_8197F)
+#define BITS_R_MAC_DEBUG_8197F \
+ (BIT_MASK_R_MAC_DEBUG_8197F << BIT_SHIFT_R_MAC_DEBUG_8197F)
+#define BIT_CLEAR_R_MAC_DEBUG_8197F(x) ((x) & (~BITS_R_MAC_DEBUG_8197F))
+#define BIT_GET_R_MAC_DEBUG_8197F(x) \
+ (((x) >> BIT_SHIFT_R_MAC_DEBUG_8197F) & BIT_MASK_R_MAC_DEBUG_8197F)
+#define BIT_SET_R_MAC_DEBUG_8197F(x, v) \
+ (BIT_CLEAR_R_MAC_DEBUG_8197F(x) | BIT_R_MAC_DEBUG_8197F(v))
+
+#define BIT_SHIFT_R_MAC_DBG_SHIFT_8197F 8
+#define BIT_MASK_R_MAC_DBG_SHIFT_8197F 0x7
+#define BIT_R_MAC_DBG_SHIFT_8197F(x) \
+ (((x) & BIT_MASK_R_MAC_DBG_SHIFT_8197F) \
+ << BIT_SHIFT_R_MAC_DBG_SHIFT_8197F)
+#define BITS_R_MAC_DBG_SHIFT_8197F \
+ (BIT_MASK_R_MAC_DBG_SHIFT_8197F << BIT_SHIFT_R_MAC_DBG_SHIFT_8197F)
+#define BIT_CLEAR_R_MAC_DBG_SHIFT_8197F(x) ((x) & (~BITS_R_MAC_DBG_SHIFT_8197F))
+#define BIT_GET_R_MAC_DBG_SHIFT_8197F(x) \
+ (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8197F) & \
+ BIT_MASK_R_MAC_DBG_SHIFT_8197F)
+#define BIT_SET_R_MAC_DBG_SHIFT_8197F(x, v) \
+ (BIT_CLEAR_R_MAC_DBG_SHIFT_8197F(x) | BIT_R_MAC_DBG_SHIFT_8197F(v))
+
+#define BIT_SHIFT_R_MAC_DBG_SEL_8197F 0
+#define BIT_MASK_R_MAC_DBG_SEL_8197F 0x3
+#define BIT_R_MAC_DBG_SEL_8197F(x) \
+ (((x) & BIT_MASK_R_MAC_DBG_SEL_8197F) << BIT_SHIFT_R_MAC_DBG_SEL_8197F)
+#define BITS_R_MAC_DBG_SEL_8197F \
+ (BIT_MASK_R_MAC_DBG_SEL_8197F << BIT_SHIFT_R_MAC_DBG_SEL_8197F)
+#define BIT_CLEAR_R_MAC_DBG_SEL_8197F(x) ((x) & (~BITS_R_MAC_DBG_SEL_8197F))
+#define BIT_GET_R_MAC_DBG_SEL_8197F(x) \
+ (((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8197F) & BIT_MASK_R_MAC_DBG_SEL_8197F)
+#define BIT_SET_R_MAC_DBG_SEL_8197F(x, v) \
+ (BIT_CLEAR_R_MAC_DBG_SEL_8197F(x) | BIT_R_MAC_DBG_SEL_8197F(v))
+
+/* 2 REG_SEC_OPT_V2_8197F */
+#define BIT_MASK_IV_8197F BIT(18)
+#define BIT_EIVL_ENDIAN_8197F BIT(17)
+#define BIT_EIVH_ENDIAN_8197F BIT(16)
+
+#define BIT_SHIFT_BT_TIME_CNT_8197F 0
+#define BIT_MASK_BT_TIME_CNT_8197F 0xff
+#define BIT_BT_TIME_CNT_8197F(x) \
+ (((x) & BIT_MASK_BT_TIME_CNT_8197F) << BIT_SHIFT_BT_TIME_CNT_8197F)
+#define BITS_BT_TIME_CNT_8197F \
+ (BIT_MASK_BT_TIME_CNT_8197F << BIT_SHIFT_BT_TIME_CNT_8197F)
+#define BIT_CLEAR_BT_TIME_CNT_8197F(x) ((x) & (~BITS_BT_TIME_CNT_8197F))
+#define BIT_GET_BT_TIME_CNT_8197F(x) \
+ (((x) >> BIT_SHIFT_BT_TIME_CNT_8197F) & BIT_MASK_BT_TIME_CNT_8197F)
+#define BIT_SET_BT_TIME_CNT_8197F(x, v) \
+ (BIT_CLEAR_BT_TIME_CNT_8197F(x) | BIT_BT_TIME_CNT_8197F(v))
+
+/* 2 REG_RTS_ADDRESS_0_8197F */
+
+/* 2 REG_RTS_ADDRESS_1_8197F */
+
+#endif
diff --git a/hal/halmac/halmac_bit_8814b.h b/hal/halmac/halmac_bit_8814b.h
new file mode 100644
index 0000000..928e37e
--- /dev/null
+++ b/hal/halmac/halmac_bit_8814b.h
@@ -0,0 +1,26472 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef __INC_HALMAC_BIT_8814B_H
+#define __INC_HALMAC_BIT_8814B_H
+
+#define CPU_OPT_WIDTH 0x1F
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_SYS_ISO_CTRL_8814B */
+#define BIT_PWC_EV12V_8814B BIT(15)
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_PA33V_EN_8814B BIT(13)
+#define BIT_PA12V_EN_8814B BIT(12)
+#define BIT_UA33V_EN_8814B BIT(11)
+#define BIT_UA12V_EN_8814B BIT(10)
+#define BIT_ISO_RFDIO_8814B BIT(9)
+#define BIT_ISO_EB2CORE_8814B BIT(8)
+#define BIT_ISO_DIOE_8814B BIT(7)
+#define BIT_ISO_WLPON2PP_8814B BIT(6)
+#define BIT_ISO_IP2MAC_WA2PP_8814B BIT(5)
+#define BIT_ISO_PD2CORE_8814B BIT(4)
+#define BIT_ISO_PA2PCIE_8814B BIT(3)
+#define BIT_ISO_UD2CORE_8814B BIT(2)
+#define BIT_ISO_UA2USB_8814B BIT(1)
+#define BIT_ISO_WD2PP_8814B BIT(0)
+
+/* 2 REG_SYS_FUNC_EN_8814B */
+#define BIT_FEN_MREGEN_8814B BIT(15)
+#define BIT_FEN_HWPDN_8814B BIT(14)
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_FEN_ELDR_8814B BIT(12)
+#define BIT_FEN_DCORE_8814B BIT(11)
+#define BIT_FEN_CPUEN_8814B BIT(10)
+#define BIT_FEN_DIOE_8814B BIT(9)
+#define BIT_FEN_PCIED_8814B BIT(8)
+#define BIT_FEN_PPLL_8814B BIT(7)
+#define BIT_FEN_PCIEA_8814B BIT(6)
+#define BIT_FEN_DIO_PCIE_8814B BIT(5)
+#define BIT_FEN_USBD_8814B BIT(4)
+#define BIT_FEN_UPLL_8814B BIT(3)
+#define BIT_FEN_USBA_8814B BIT(2)
+#define BIT_FEN_BB_GLB_RSTN_8814B BIT(1)
+#define BIT_FEN_BBRSTB_8814B BIT(0)
+
+/* 2 REG_SYS_PW_CTRL_8814B */
+#define BIT_SOP_EABM_8814B BIT(31)
+#define BIT_SOP_ACKF_8814B BIT(30)
+#define BIT_SOP_ERCK_8814B BIT(29)
+#define BIT_SOP_ESWR_8814B BIT(28)
+#define BIT_SOP_PWMM_8814B BIT(27)
+#define BIT_SOP_EECK_8814B BIT(26)
+#define BIT_SOP_EXTL_8814B BIT(24)
+#define BIT_SYM_OP_RING_12M_8814B BIT(22)
+#define BIT_ROP_SWPR_8814B BIT(21)
+#define BIT_DIS_HW_LPLDM_8814B BIT(20)
+#define BIT_OPT_SWRST_WLMCU_8814B BIT(19)
+#define BIT_RDY_SYSPWR_8814B BIT(17)
+#define BIT_EN_WLON_8814B BIT(16)
+#define BIT_APDM_HPDN_8814B BIT(15)
+#define BIT_AFSM_PCIE_SUS_EN_8814B BIT(12)
+#define BIT_AFSM_WLSUS_EN_8814B BIT(11)
+#define BIT_APFM_SWLPS_8814B BIT(10)
+#define BIT_APFM_OFFMAC_8814B BIT(9)
+#define BIT_APFN_ONMAC_8814B BIT(8)
+#define BIT_CHIP_PDN_EN_8814B BIT(7)
+#define BIT_RDY_MACDIS_8814B BIT(6)
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_PFM_WOWL_8814B BIT(3)
+#define BIT_PFM_LDKP_8814B BIT(2)
+#define BIT_WL_HCI_ALD_8814B BIT(1)
+#define BIT_PFM_LDALL_8814B BIT(0)
+
+/* 2 REG_SYS_CLK_CTRL_8814B */
+#define BIT_DATA_CPU_CLK_EN_8814B BIT(15)
+#define BIT_CPU_CLK_EN_8814B BIT(14)
+#define BIT_SYMREG_CLK_EN_8814B BIT(13)
+#define BIT_HCI_CLK_EN_8814B BIT(12)
+#define BIT_MAC_CLK_EN_8814B BIT(11)
+#define BIT_SEC_CLK_EN_8814B BIT(10)
+#define BIT_PHY_SSC_RSTB_8814B BIT(9)
+#define BIT_EXT_32K_EN_8814B BIT(8)
+#define BIT_WL_CLK_TEST_8814B BIT(7)
+#define BIT_OP_SPS_PWM_EN_8814B BIT(6)
+#define BIT_LOADER_CLK_EN_8814B BIT(5)
+#define BIT_MACSLP_8814B BIT(4)
+#define BIT_WAKEPAD_EN_8814B BIT(3)
+#define BIT_ROMD16V_EN_8814B BIT(2)
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_CNTD16V_EN_8814B BIT(0)
+
+/* 2 REG_SYS_EEPROM_CTRL_8814B */
+
+#define BIT_SHIFT_VPDIDX_8814B 8
+#define BIT_MASK_VPDIDX_8814B 0xff
+#define BIT_VPDIDX_8814B(x) \
+ (((x) & BIT_MASK_VPDIDX_8814B) << BIT_SHIFT_VPDIDX_8814B)
+#define BITS_VPDIDX_8814B (BIT_MASK_VPDIDX_8814B << BIT_SHIFT_VPDIDX_8814B)
+#define BIT_CLEAR_VPDIDX_8814B(x) ((x) & (~BITS_VPDIDX_8814B))
+#define BIT_GET_VPDIDX_8814B(x) \
+ (((x) >> BIT_SHIFT_VPDIDX_8814B) & BIT_MASK_VPDIDX_8814B)
+#define BIT_SET_VPDIDX_8814B(x, v) \
+ (BIT_CLEAR_VPDIDX_8814B(x) | BIT_VPDIDX_8814B(v))
+
+#define BIT_SHIFT_EEM1_0_8814B 6
+#define BIT_MASK_EEM1_0_8814B 0x3
+#define BIT_EEM1_0_8814B(x) \
+ (((x) & BIT_MASK_EEM1_0_8814B) << BIT_SHIFT_EEM1_0_8814B)
+#define BITS_EEM1_0_8814B (BIT_MASK_EEM1_0_8814B << BIT_SHIFT_EEM1_0_8814B)
+#define BIT_CLEAR_EEM1_0_8814B(x) ((x) & (~BITS_EEM1_0_8814B))
+#define BIT_GET_EEM1_0_8814B(x) \
+ (((x) >> BIT_SHIFT_EEM1_0_8814B) & BIT_MASK_EEM1_0_8814B)
+#define BIT_SET_EEM1_0_8814B(x, v) \
+ (BIT_CLEAR_EEM1_0_8814B(x) | BIT_EEM1_0_8814B(v))
+
+#define BIT_AUTOLOAD_SUS_8814B BIT(5)
+#define BIT_EERPOMSEL_8814B BIT(4)
+#define BIT_EECS_V1_8814B BIT(3)
+#define BIT_EESK_V1_8814B BIT(2)
+#define BIT_EEDI_V1_8814B BIT(1)
+#define BIT_EEDO_V1_8814B BIT(0)
+
+/* 2 REG_EE_VPD_8814B */
+
+#define BIT_SHIFT_VPD_DATA_8814B 0
+#define BIT_MASK_VPD_DATA_8814B 0xffffffffL
+#define BIT_VPD_DATA_8814B(x) \
+ (((x) & BIT_MASK_VPD_DATA_8814B) << BIT_SHIFT_VPD_DATA_8814B)
+#define BITS_VPD_DATA_8814B \
+ (BIT_MASK_VPD_DATA_8814B << BIT_SHIFT_VPD_DATA_8814B)
+#define BIT_CLEAR_VPD_DATA_8814B(x) ((x) & (~BITS_VPD_DATA_8814B))
+#define BIT_GET_VPD_DATA_8814B(x) \
+ (((x) >> BIT_SHIFT_VPD_DATA_8814B) & BIT_MASK_VPD_DATA_8814B)
+#define BIT_SET_VPD_DATA_8814B(x, v) \
+ (BIT_CLEAR_VPD_DATA_8814B(x) | BIT_VPD_DATA_8814B(v))
+
+/* 2 REG_SYS_SWR_CTRL1_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_CTRL_SPS_PWM_FREQ_8814B BIT(10)
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_DISABLE_OPEN_SPS_LDO_8814B BIT(8)
+#define BIT_MAC_ID_EN_8814B BIT(7)
+#define BIT_WL_CTRL_XTAL_CADJ_8814B BIT(6)
+#define BIT_AFE_BGEN_PCIE_OP_8814B BIT(2)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_SYS_SWR_CTRL2_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_SYS_SWR_CTRL3_8814B */
+#define BIT_SPS18_OCP_DIS_8814B BIT(31)
+
+#define BIT_SHIFT_SPS18_OCP_TH_8814B 16
+#define BIT_MASK_SPS18_OCP_TH_8814B 0x7fff
+#define BIT_SPS18_OCP_TH_8814B(x) \
+ (((x) & BIT_MASK_SPS18_OCP_TH_8814B) << BIT_SHIFT_SPS18_OCP_TH_8814B)
+#define BITS_SPS18_OCP_TH_8814B \
+ (BIT_MASK_SPS18_OCP_TH_8814B << BIT_SHIFT_SPS18_OCP_TH_8814B)
+#define BIT_CLEAR_SPS18_OCP_TH_8814B(x) ((x) & (~BITS_SPS18_OCP_TH_8814B))
+#define BIT_GET_SPS18_OCP_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_SPS18_OCP_TH_8814B) & BIT_MASK_SPS18_OCP_TH_8814B)
+#define BIT_SET_SPS18_OCP_TH_8814B(x, v) \
+ (BIT_CLEAR_SPS18_OCP_TH_8814B(x) | BIT_SPS18_OCP_TH_8814B(v))
+
+#define BIT_SHIFT_OCP_WINDOW_8814B 0
+#define BIT_MASK_OCP_WINDOW_8814B 0xffff
+#define BIT_OCP_WINDOW_8814B(x) \
+ (((x) & BIT_MASK_OCP_WINDOW_8814B) << BIT_SHIFT_OCP_WINDOW_8814B)
+#define BITS_OCP_WINDOW_8814B \
+ (BIT_MASK_OCP_WINDOW_8814B << BIT_SHIFT_OCP_WINDOW_8814B)
+#define BIT_CLEAR_OCP_WINDOW_8814B(x) ((x) & (~BITS_OCP_WINDOW_8814B))
+#define BIT_GET_OCP_WINDOW_8814B(x) \
+ (((x) >> BIT_SHIFT_OCP_WINDOW_8814B) & BIT_MASK_OCP_WINDOW_8814B)
+#define BIT_SET_OCP_WINDOW_8814B(x, v) \
+ (BIT_CLEAR_OCP_WINDOW_8814B(x) | BIT_OCP_WINDOW_8814B(v))
+
+/* 2 REG_RSV_CTRL_8814B */
+
+#define BIT_SHIFT_HREG_DBG_V1_8814B 12
+#define BIT_MASK_HREG_DBG_V1_8814B 0xfff
+#define BIT_HREG_DBG_V1_8814B(x) \
+ (((x) & BIT_MASK_HREG_DBG_V1_8814B) << BIT_SHIFT_HREG_DBG_V1_8814B)
+#define BITS_HREG_DBG_V1_8814B \
+ (BIT_MASK_HREG_DBG_V1_8814B << BIT_SHIFT_HREG_DBG_V1_8814B)
+#define BIT_CLEAR_HREG_DBG_V1_8814B(x) ((x) & (~BITS_HREG_DBG_V1_8814B))
+#define BIT_GET_HREG_DBG_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_HREG_DBG_V1_8814B) & BIT_MASK_HREG_DBG_V1_8814B)
+#define BIT_SET_HREG_DBG_V1_8814B(x, v) \
+ (BIT_CLEAR_HREG_DBG_V1_8814B(x) | BIT_HREG_DBG_V1_8814B(v))
+
+#define BIT_WLMCUIOIF_8814B BIT(8)
+#define BIT_LOCK_ALL_EN_8814B BIT(7)
+#define BIT_R_DIS_PRST_8814B BIT(6)
+#define BIT_WLOCK_1C_B6_8814B BIT(5)
+#define BIT_WLOCK_40_8814B BIT(4)
+#define BIT_WLOCK_08_8814B BIT(3)
+#define BIT_WLOCK_04_8814B BIT(2)
+#define BIT_WLOCK_00_8814B BIT(1)
+#define BIT_WLOCK_ALL_8814B BIT(0)
+
+/* 2 REG_RF_CTRL_8814B */
+#define BIT_RF_SDMRSTB_8814B BIT(2)
+#define BIT_RF_RSTB_8814B BIT(1)
+#define BIT_RF_EN_8814B BIT(0)
+
+/* 2 REG_AFE_LDO_CTRL_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_CPHY_LDO_CL_EN_8814B BIT(19)
+#define BIT_CPHY_LDO_OK_8814B BIT(18)
+#define BIT_PCIE_CALIB_EN_8814B BIT(17)
+#define BIT_LDH12_EN_8814B BIT(16)
+#define BIT_DATA_CPU_PWC_8814B BIT(15)
+#define BIT_WLBBOFF_BIG_PWC_EN_8814B BIT(14)
+#define BIT_WLBBOFF_SMALL_PWC_EN_8814B BIT(13)
+#define BIT_WLMACOFF_BIG_PWC_EN_8814B BIT(12)
+#define BIT_WLPON_PWC_EN_8814B BIT(11)
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_LDOV12W_EN_8814B BIT(8)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_AFE_CTRL1_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_MAC_CLK_SEL_8814B 20
+#define BIT_MASK_MAC_CLK_SEL_8814B 0x3
+#define BIT_MAC_CLK_SEL_8814B(x) \
+ (((x) & BIT_MASK_MAC_CLK_SEL_8814B) << BIT_SHIFT_MAC_CLK_SEL_8814B)
+#define BITS_MAC_CLK_SEL_8814B \
+ (BIT_MASK_MAC_CLK_SEL_8814B << BIT_SHIFT_MAC_CLK_SEL_8814B)
+#define BIT_CLEAR_MAC_CLK_SEL_8814B(x) ((x) & (~BITS_MAC_CLK_SEL_8814B))
+#define BIT_GET_MAC_CLK_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_MAC_CLK_SEL_8814B) & BIT_MASK_MAC_CLK_SEL_8814B)
+#define BIT_SET_MAC_CLK_SEL_8814B(x, v) \
+ (BIT_CLEAR_MAC_CLK_SEL_8814B(x) | BIT_MAC_CLK_SEL_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_ANAPARSW_POW_MAC_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_ENB_LDO_DIODE_L_8814B BIT(3)
+#define BIT_POW_LDO15_8814B BIT(2)
+#define BIT_POW_SW_8814B BIT(1)
+#define BIT_POW_LDO14_8814B BIT(0)
+
+/* 2 REG_ANAPARLDO_POW_MAC_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_LDOE25_POW_L_8814B BIT(0)
+
+/* 2 REG_ANAPAR_POW_MAC_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_POW_PC_LDO3_8814B BIT(5)
+#define BIT_POW_PC_LDO2_8814B BIT(4)
+#define BIT_POW_PC_LDO1_8814B BIT(3)
+#define BIT_POW_PC_LDO0_8814B BIT(2)
+#define BIT_POW_PLL_V1_8814B BIT(1)
+#define BIT_POW_POWER_CUT_8814B BIT(0)
+
+/* 2 REG_ANAPAR_POW_XTAL_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_POW_XTAL_8814B BIT(1)
+#define BIT_POW_BG_8814B BIT(0)
+
+/* 2 REG_ANAPARLDO_MAC_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_EFUSE_CTRL_8814B */
+#define BIT_EF_FLAG_8814B BIT(31)
+
+#define BIT_SHIFT_EF_PGPD_8814B 28
+#define BIT_MASK_EF_PGPD_8814B 0x7
+#define BIT_EF_PGPD_8814B(x) \
+ (((x) & BIT_MASK_EF_PGPD_8814B) << BIT_SHIFT_EF_PGPD_8814B)
+#define BITS_EF_PGPD_8814B (BIT_MASK_EF_PGPD_8814B << BIT_SHIFT_EF_PGPD_8814B)
+#define BIT_CLEAR_EF_PGPD_8814B(x) ((x) & (~BITS_EF_PGPD_8814B))
+#define BIT_GET_EF_PGPD_8814B(x) \
+ (((x) >> BIT_SHIFT_EF_PGPD_8814B) & BIT_MASK_EF_PGPD_8814B)
+#define BIT_SET_EF_PGPD_8814B(x, v) \
+ (BIT_CLEAR_EF_PGPD_8814B(x) | BIT_EF_PGPD_8814B(v))
+
+#define BIT_SHIFT_EF_RDT_8814B 24
+#define BIT_MASK_EF_RDT_8814B 0xf
+#define BIT_EF_RDT_8814B(x) \
+ (((x) & BIT_MASK_EF_RDT_8814B) << BIT_SHIFT_EF_RDT_8814B)
+#define BITS_EF_RDT_8814B (BIT_MASK_EF_RDT_8814B << BIT_SHIFT_EF_RDT_8814B)
+#define BIT_CLEAR_EF_RDT_8814B(x) ((x) & (~BITS_EF_RDT_8814B))
+#define BIT_GET_EF_RDT_8814B(x) \
+ (((x) >> BIT_SHIFT_EF_RDT_8814B) & BIT_MASK_EF_RDT_8814B)
+#define BIT_SET_EF_RDT_8814B(x, v) \
+ (BIT_CLEAR_EF_RDT_8814B(x) | BIT_EF_RDT_8814B(v))
+
+#define BIT_SHIFT_EF_PGTS_8814B 20
+#define BIT_MASK_EF_PGTS_8814B 0xf
+#define BIT_EF_PGTS_8814B(x) \
+ (((x) & BIT_MASK_EF_PGTS_8814B) << BIT_SHIFT_EF_PGTS_8814B)
+#define BITS_EF_PGTS_8814B (BIT_MASK_EF_PGTS_8814B << BIT_SHIFT_EF_PGTS_8814B)
+#define BIT_CLEAR_EF_PGTS_8814B(x) ((x) & (~BITS_EF_PGTS_8814B))
+#define BIT_GET_EF_PGTS_8814B(x) \
+ (((x) >> BIT_SHIFT_EF_PGTS_8814B) & BIT_MASK_EF_PGTS_8814B)
+#define BIT_SET_EF_PGTS_8814B(x, v) \
+ (BIT_CLEAR_EF_PGTS_8814B(x) | BIT_EF_PGTS_8814B(v))
+
+#define BIT_EF_PDWN_8814B BIT(19)
+#define BIT_EF_ALDEN_8814B BIT(18)
+
+#define BIT_SHIFT_EF_ADDR_8814B 8
+#define BIT_MASK_EF_ADDR_8814B 0x3ff
+#define BIT_EF_ADDR_8814B(x) \
+ (((x) & BIT_MASK_EF_ADDR_8814B) << BIT_SHIFT_EF_ADDR_8814B)
+#define BITS_EF_ADDR_8814B (BIT_MASK_EF_ADDR_8814B << BIT_SHIFT_EF_ADDR_8814B)
+#define BIT_CLEAR_EF_ADDR_8814B(x) ((x) & (~BITS_EF_ADDR_8814B))
+#define BIT_GET_EF_ADDR_8814B(x) \
+ (((x) >> BIT_SHIFT_EF_ADDR_8814B) & BIT_MASK_EF_ADDR_8814B)
+#define BIT_SET_EF_ADDR_8814B(x, v) \
+ (BIT_CLEAR_EF_ADDR_8814B(x) | BIT_EF_ADDR_8814B(v))
+
+#define BIT_SHIFT_EF_DATA_8814B 0
+#define BIT_MASK_EF_DATA_8814B 0xff
+#define BIT_EF_DATA_8814B(x) \
+ (((x) & BIT_MASK_EF_DATA_8814B) << BIT_SHIFT_EF_DATA_8814B)
+#define BITS_EF_DATA_8814B (BIT_MASK_EF_DATA_8814B << BIT_SHIFT_EF_DATA_8814B)
+#define BIT_CLEAR_EF_DATA_8814B(x) ((x) & (~BITS_EF_DATA_8814B))
+#define BIT_GET_EF_DATA_8814B(x) \
+ (((x) >> BIT_SHIFT_EF_DATA_8814B) & BIT_MASK_EF_DATA_8814B)
+#define BIT_SET_EF_DATA_8814B(x, v) \
+ (BIT_CLEAR_EF_DATA_8814B(x) | BIT_EF_DATA_8814B(v))
+
+/* 2 REG_LDO_EFUSE_CTRL_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_EF_CRES_SEL_8814B BIT(26)
+
+#define BIT_SHIFT_EF_SCAN_START_V1_8814B 16
+#define BIT_MASK_EF_SCAN_START_V1_8814B 0x3ff
+#define BIT_EF_SCAN_START_V1_8814B(x) \
+ (((x) & BIT_MASK_EF_SCAN_START_V1_8814B) \
+ << BIT_SHIFT_EF_SCAN_START_V1_8814B)
+#define BITS_EF_SCAN_START_V1_8814B \
+ (BIT_MASK_EF_SCAN_START_V1_8814B << BIT_SHIFT_EF_SCAN_START_V1_8814B)
+#define BIT_CLEAR_EF_SCAN_START_V1_8814B(x) \
+ ((x) & (~BITS_EF_SCAN_START_V1_8814B))
+#define BIT_GET_EF_SCAN_START_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_EF_SCAN_START_V1_8814B) & \
+ BIT_MASK_EF_SCAN_START_V1_8814B)
+#define BIT_SET_EF_SCAN_START_V1_8814B(x, v) \
+ (BIT_CLEAR_EF_SCAN_START_V1_8814B(x) | BIT_EF_SCAN_START_V1_8814B(v))
+
+#define BIT_SHIFT_EF_SCAN_END_8814B 12
+#define BIT_MASK_EF_SCAN_END_8814B 0xf
+#define BIT_EF_SCAN_END_8814B(x) \
+ (((x) & BIT_MASK_EF_SCAN_END_8814B) << BIT_SHIFT_EF_SCAN_END_8814B)
+#define BITS_EF_SCAN_END_8814B \
+ (BIT_MASK_EF_SCAN_END_8814B << BIT_SHIFT_EF_SCAN_END_8814B)
+#define BIT_CLEAR_EF_SCAN_END_8814B(x) ((x) & (~BITS_EF_SCAN_END_8814B))
+#define BIT_GET_EF_SCAN_END_8814B(x) \
+ (((x) >> BIT_SHIFT_EF_SCAN_END_8814B) & BIT_MASK_EF_SCAN_END_8814B)
+#define BIT_SET_EF_SCAN_END_8814B(x, v) \
+ (BIT_CLEAR_EF_SCAN_END_8814B(x) | BIT_EF_SCAN_END_8814B(v))
+
+#define BIT_EF_PD_DIS_8814B BIT(11)
+
+#define BIT_SHIFT_EF_CELL_SEL_8814B 8
+#define BIT_MASK_EF_CELL_SEL_8814B 0x3
+#define BIT_EF_CELL_SEL_8814B(x) \
+ (((x) & BIT_MASK_EF_CELL_SEL_8814B) << BIT_SHIFT_EF_CELL_SEL_8814B)
+#define BITS_EF_CELL_SEL_8814B \
+ (BIT_MASK_EF_CELL_SEL_8814B << BIT_SHIFT_EF_CELL_SEL_8814B)
+#define BIT_CLEAR_EF_CELL_SEL_8814B(x) ((x) & (~BITS_EF_CELL_SEL_8814B))
+#define BIT_GET_EF_CELL_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_EF_CELL_SEL_8814B) & BIT_MASK_EF_CELL_SEL_8814B)
+#define BIT_SET_EF_CELL_SEL_8814B(x, v) \
+ (BIT_CLEAR_EF_CELL_SEL_8814B(x) | BIT_EF_CELL_SEL_8814B(v))
+
+#define BIT_EF_TRPT_8814B BIT(7)
+
+#define BIT_SHIFT_EF_TTHD_8814B 0
+#define BIT_MASK_EF_TTHD_8814B 0x7f
+#define BIT_EF_TTHD_8814B(x) \
+ (((x) & BIT_MASK_EF_TTHD_8814B) << BIT_SHIFT_EF_TTHD_8814B)
+#define BITS_EF_TTHD_8814B (BIT_MASK_EF_TTHD_8814B << BIT_SHIFT_EF_TTHD_8814B)
+#define BIT_CLEAR_EF_TTHD_8814B(x) ((x) & (~BITS_EF_TTHD_8814B))
+#define BIT_GET_EF_TTHD_8814B(x) \
+ (((x) >> BIT_SHIFT_EF_TTHD_8814B) & BIT_MASK_EF_TTHD_8814B)
+#define BIT_SET_EF_TTHD_8814B(x, v) \
+ (BIT_CLEAR_EF_TTHD_8814B(x) | BIT_EF_TTHD_8814B(v))
+
+/* 2 REG_PWR_OPTION_CTRL_8814B */
+
+#define BIT_SHIFT_DBG_SEL_V1_8814B 16
+#define BIT_MASK_DBG_SEL_V1_8814B 0xff
+#define BIT_DBG_SEL_V1_8814B(x) \
+ (((x) & BIT_MASK_DBG_SEL_V1_8814B) << BIT_SHIFT_DBG_SEL_V1_8814B)
+#define BITS_DBG_SEL_V1_8814B \
+ (BIT_MASK_DBG_SEL_V1_8814B << BIT_SHIFT_DBG_SEL_V1_8814B)
+#define BIT_CLEAR_DBG_SEL_V1_8814B(x) ((x) & (~BITS_DBG_SEL_V1_8814B))
+#define BIT_GET_DBG_SEL_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_DBG_SEL_V1_8814B) & BIT_MASK_DBG_SEL_V1_8814B)
+#define BIT_SET_DBG_SEL_V1_8814B(x, v) \
+ (BIT_CLEAR_DBG_SEL_V1_8814B(x) | BIT_DBG_SEL_V1_8814B(v))
+
+#define BIT_SHIFT_DBG_SEL_BYTE_8814B 14
+#define BIT_MASK_DBG_SEL_BYTE_8814B 0x3
+#define BIT_DBG_SEL_BYTE_8814B(x) \
+ (((x) & BIT_MASK_DBG_SEL_BYTE_8814B) << BIT_SHIFT_DBG_SEL_BYTE_8814B)
+#define BITS_DBG_SEL_BYTE_8814B \
+ (BIT_MASK_DBG_SEL_BYTE_8814B << BIT_SHIFT_DBG_SEL_BYTE_8814B)
+#define BIT_CLEAR_DBG_SEL_BYTE_8814B(x) ((x) & (~BITS_DBG_SEL_BYTE_8814B))
+#define BIT_GET_DBG_SEL_BYTE_8814B(x) \
+ (((x) >> BIT_SHIFT_DBG_SEL_BYTE_8814B) & BIT_MASK_DBG_SEL_BYTE_8814B)
+#define BIT_SET_DBG_SEL_BYTE_8814B(x, v) \
+ (BIT_CLEAR_DBG_SEL_BYTE_8814B(x) | BIT_DBG_SEL_BYTE_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_SYSON_DBG_PAD_E2_8814B BIT(11)
+#define BIT_SYSON_LED_PAD_E2_8814B BIT(10)
+#define BIT_SYSON_GPEE_PAD_E2_8814B BIT(9)
+#define BIT_SYSON_PCI_PAD_E2_8814B BIT(8)
+#define BIT_AUTO_SW_LDO_VOL_EN_8814B BIT(7)
+
+#define BIT_SHIFT_SYSON_SPS0WWV_WT_8814B 4
+#define BIT_MASK_SYSON_SPS0WWV_WT_8814B 0x3
+#define BIT_SYSON_SPS0WWV_WT_8814B(x) \
+ (((x) & BIT_MASK_SYSON_SPS0WWV_WT_8814B) \
+ << BIT_SHIFT_SYSON_SPS0WWV_WT_8814B)
+#define BITS_SYSON_SPS0WWV_WT_8814B \
+ (BIT_MASK_SYSON_SPS0WWV_WT_8814B << BIT_SHIFT_SYSON_SPS0WWV_WT_8814B)
+#define BIT_CLEAR_SYSON_SPS0WWV_WT_8814B(x) \
+ ((x) & (~BITS_SYSON_SPS0WWV_WT_8814B))
+#define BIT_GET_SYSON_SPS0WWV_WT_8814B(x) \
+ (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8814B) & \
+ BIT_MASK_SYSON_SPS0WWV_WT_8814B)
+#define BIT_SET_SYSON_SPS0WWV_WT_8814B(x, v) \
+ (BIT_CLEAR_SYSON_SPS0WWV_WT_8814B(x) | BIT_SYSON_SPS0WWV_WT_8814B(v))
+
+#define BIT_SHIFT_SYSON_SPS0LDO_WT_8814B 2
+#define BIT_MASK_SYSON_SPS0LDO_WT_8814B 0x3
+#define BIT_SYSON_SPS0LDO_WT_8814B(x) \
+ (((x) & BIT_MASK_SYSON_SPS0LDO_WT_8814B) \
+ << BIT_SHIFT_SYSON_SPS0LDO_WT_8814B)
+#define BITS_SYSON_SPS0LDO_WT_8814B \
+ (BIT_MASK_SYSON_SPS0LDO_WT_8814B << BIT_SHIFT_SYSON_SPS0LDO_WT_8814B)
+#define BIT_CLEAR_SYSON_SPS0LDO_WT_8814B(x) \
+ ((x) & (~BITS_SYSON_SPS0LDO_WT_8814B))
+#define BIT_GET_SYSON_SPS0LDO_WT_8814B(x) \
+ (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8814B) & \
+ BIT_MASK_SYSON_SPS0LDO_WT_8814B)
+#define BIT_SET_SYSON_SPS0LDO_WT_8814B(x, v) \
+ (BIT_CLEAR_SYSON_SPS0LDO_WT_8814B(x) | BIT_SYSON_SPS0LDO_WT_8814B(v))
+
+#define BIT_SHIFT_SYSON_RCLK_SCALE_8814B 0
+#define BIT_MASK_SYSON_RCLK_SCALE_8814B 0x3
+#define BIT_SYSON_RCLK_SCALE_8814B(x) \
+ (((x) & BIT_MASK_SYSON_RCLK_SCALE_8814B) \
+ << BIT_SHIFT_SYSON_RCLK_SCALE_8814B)
+#define BITS_SYSON_RCLK_SCALE_8814B \
+ (BIT_MASK_SYSON_RCLK_SCALE_8814B << BIT_SHIFT_SYSON_RCLK_SCALE_8814B)
+#define BIT_CLEAR_SYSON_RCLK_SCALE_8814B(x) \
+ ((x) & (~BITS_SYSON_RCLK_SCALE_8814B))
+#define BIT_GET_SYSON_RCLK_SCALE_8814B(x) \
+ (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8814B) & \
+ BIT_MASK_SYSON_RCLK_SCALE_8814B)
+#define BIT_SET_SYSON_RCLK_SCALE_8814B(x, v) \
+ (BIT_CLEAR_SYSON_RCLK_SCALE_8814B(x) | BIT_SYSON_RCLK_SCALE_8814B(v))
+
+/* 2 REG_CAL_TIMER_8814B */
+
+#define BIT_SHIFT_MATCH_CNT_8814B 8
+#define BIT_MASK_MATCH_CNT_8814B 0xff
+#define BIT_MATCH_CNT_8814B(x) \
+ (((x) & BIT_MASK_MATCH_CNT_8814B) << BIT_SHIFT_MATCH_CNT_8814B)
+#define BITS_MATCH_CNT_8814B \
+ (BIT_MASK_MATCH_CNT_8814B << BIT_SHIFT_MATCH_CNT_8814B)
+#define BIT_CLEAR_MATCH_CNT_8814B(x) ((x) & (~BITS_MATCH_CNT_8814B))
+#define BIT_GET_MATCH_CNT_8814B(x) \
+ (((x) >> BIT_SHIFT_MATCH_CNT_8814B) & BIT_MASK_MATCH_CNT_8814B)
+#define BIT_SET_MATCH_CNT_8814B(x, v) \
+ (BIT_CLEAR_MATCH_CNT_8814B(x) | BIT_MATCH_CNT_8814B(v))
+
+#define BIT_SHIFT_CAL_SCAL_8814B 0
+#define BIT_MASK_CAL_SCAL_8814B 0xff
+#define BIT_CAL_SCAL_8814B(x) \
+ (((x) & BIT_MASK_CAL_SCAL_8814B) << BIT_SHIFT_CAL_SCAL_8814B)
+#define BITS_CAL_SCAL_8814B \
+ (BIT_MASK_CAL_SCAL_8814B << BIT_SHIFT_CAL_SCAL_8814B)
+#define BIT_CLEAR_CAL_SCAL_8814B(x) ((x) & (~BITS_CAL_SCAL_8814B))
+#define BIT_GET_CAL_SCAL_8814B(x) \
+ (((x) >> BIT_SHIFT_CAL_SCAL_8814B) & BIT_MASK_CAL_SCAL_8814B)
+#define BIT_SET_CAL_SCAL_8814B(x, v) \
+ (BIT_CLEAR_CAL_SCAL_8814B(x) | BIT_CAL_SCAL_8814B(v))
+
+/* 2 REG_ACLK_MON_8814B */
+
+#define BIT_SHIFT_RCLK_MON_8814B 5
+#define BIT_MASK_RCLK_MON_8814B 0x7ff
+#define BIT_RCLK_MON_8814B(x) \
+ (((x) & BIT_MASK_RCLK_MON_8814B) << BIT_SHIFT_RCLK_MON_8814B)
+#define BITS_RCLK_MON_8814B \
+ (BIT_MASK_RCLK_MON_8814B << BIT_SHIFT_RCLK_MON_8814B)
+#define BIT_CLEAR_RCLK_MON_8814B(x) ((x) & (~BITS_RCLK_MON_8814B))
+#define BIT_GET_RCLK_MON_8814B(x) \
+ (((x) >> BIT_SHIFT_RCLK_MON_8814B) & BIT_MASK_RCLK_MON_8814B)
+#define BIT_SET_RCLK_MON_8814B(x, v) \
+ (BIT_CLEAR_RCLK_MON_8814B(x) | BIT_RCLK_MON_8814B(v))
+
+#define BIT_CAL_EN_8814B BIT(4)
+
+#define BIT_SHIFT_DPSTU_8814B 2
+#define BIT_MASK_DPSTU_8814B 0x3
+#define BIT_DPSTU_8814B(x) \
+ (((x) & BIT_MASK_DPSTU_8814B) << BIT_SHIFT_DPSTU_8814B)
+#define BITS_DPSTU_8814B (BIT_MASK_DPSTU_8814B << BIT_SHIFT_DPSTU_8814B)
+#define BIT_CLEAR_DPSTU_8814B(x) ((x) & (~BITS_DPSTU_8814B))
+#define BIT_GET_DPSTU_8814B(x) \
+ (((x) >> BIT_SHIFT_DPSTU_8814B) & BIT_MASK_DPSTU_8814B)
+#define BIT_SET_DPSTU_8814B(x, v) \
+ (BIT_CLEAR_DPSTU_8814B(x) | BIT_DPSTU_8814B(v))
+
+#define BIT_SUS_16X_8814B BIT(1)
+
+/* 2 REG_GPIO_MUXCFG_8814B */
+#define BIT_EN_DATACPU_GPIO2_8814B BIT(24)
+#define BIT_EN_DATACPU_GPIO_8814B BIT(23)
+#define BIT_EN_DATACPU_UART_8814B BIT(22)
+#define BIT_DATACPU_FSPI_EN_8814B BIT(21)
+#define BIT_EN_GPIO8_UART_OUT_8814B BIT(20)
+#define BIT_FSPI_EN_8814B BIT(19)
+#define BIT_WL_RTS_EXT_32K_SEL_8814B BIT(18)
+#define BIT_WLGP_SPI_EN_8814B BIT(16)
+#define BIT_SIC_LBK_8814B BIT(15)
+#define BIT_ENHTP_8814B BIT(14)
+#define BIT_ENSIC_8814B BIT(12)
+#define BIT_SIC_SWRST_8814B BIT(11)
+#define BIT_PO_WIFI_PTA_PINS_8814B BIT(10)
+#define BIT_PO_BT_PTA_PINS_8814B BIT(9)
+#define BIT_ENUART_8814B BIT(8)
+
+#define BIT_SHIFT_BTMODE_8814B 6
+#define BIT_MASK_BTMODE_8814B 0x3
+#define BIT_BTMODE_8814B(x) \
+ (((x) & BIT_MASK_BTMODE_8814B) << BIT_SHIFT_BTMODE_8814B)
+#define BITS_BTMODE_8814B (BIT_MASK_BTMODE_8814B << BIT_SHIFT_BTMODE_8814B)
+#define BIT_CLEAR_BTMODE_8814B(x) ((x) & (~BITS_BTMODE_8814B))
+#define BIT_GET_BTMODE_8814B(x) \
+ (((x) >> BIT_SHIFT_BTMODE_8814B) & BIT_MASK_BTMODE_8814B)
+#define BIT_SET_BTMODE_8814B(x, v) \
+ (BIT_CLEAR_BTMODE_8814B(x) | BIT_BTMODE_8814B(v))
+
+#define BIT_ENBT_8814B BIT(5)
+#define BIT_EROM_EN_8814B BIT(4)
+#define BIT_WLRFE_6_7_EN_8814B BIT(3)
+#define BIT_WLRFE_4_5_EN_8814B BIT(2)
+
+#define BIT_SHIFT_GPIOSEL_8814B 0
+#define BIT_MASK_GPIOSEL_8814B 0x3
+#define BIT_GPIOSEL_8814B(x) \
+ (((x) & BIT_MASK_GPIOSEL_8814B) << BIT_SHIFT_GPIOSEL_8814B)
+#define BITS_GPIOSEL_8814B (BIT_MASK_GPIOSEL_8814B << BIT_SHIFT_GPIOSEL_8814B)
+#define BIT_CLEAR_GPIOSEL_8814B(x) ((x) & (~BITS_GPIOSEL_8814B))
+#define BIT_GET_GPIOSEL_8814B(x) \
+ (((x) >> BIT_SHIFT_GPIOSEL_8814B) & BIT_MASK_GPIOSEL_8814B)
+#define BIT_SET_GPIOSEL_8814B(x, v) \
+ (BIT_CLEAR_GPIOSEL_8814B(x) | BIT_GPIOSEL_8814B(v))
+
+/* 2 REG_GPIO_PIN_CTRL_8814B */
+
+#define BIT_SHIFT_GPIO_MOD_7_TO_0_8814B 24
+#define BIT_MASK_GPIO_MOD_7_TO_0_8814B 0xff
+#define BIT_GPIO_MOD_7_TO_0_8814B(x) \
+ (((x) & BIT_MASK_GPIO_MOD_7_TO_0_8814B) \
+ << BIT_SHIFT_GPIO_MOD_7_TO_0_8814B)
+#define BITS_GPIO_MOD_7_TO_0_8814B \
+ (BIT_MASK_GPIO_MOD_7_TO_0_8814B << BIT_SHIFT_GPIO_MOD_7_TO_0_8814B)
+#define BIT_CLEAR_GPIO_MOD_7_TO_0_8814B(x) ((x) & (~BITS_GPIO_MOD_7_TO_0_8814B))
+#define BIT_GET_GPIO_MOD_7_TO_0_8814B(x) \
+ (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8814B) & \
+ BIT_MASK_GPIO_MOD_7_TO_0_8814B)
+#define BIT_SET_GPIO_MOD_7_TO_0_8814B(x, v) \
+ (BIT_CLEAR_GPIO_MOD_7_TO_0_8814B(x) | BIT_GPIO_MOD_7_TO_0_8814B(v))
+
+#define BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8814B 16
+#define BIT_MASK_GPIO_IO_SEL_7_TO_0_8814B 0xff
+#define BIT_GPIO_IO_SEL_7_TO_0_8814B(x) \
+ (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8814B) \
+ << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8814B)
+#define BITS_GPIO_IO_SEL_7_TO_0_8814B \
+ (BIT_MASK_GPIO_IO_SEL_7_TO_0_8814B \
+ << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8814B)
+#define BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8814B(x) \
+ ((x) & (~BITS_GPIO_IO_SEL_7_TO_0_8814B))
+#define BIT_GET_GPIO_IO_SEL_7_TO_0_8814B(x) \
+ (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8814B) & \
+ BIT_MASK_GPIO_IO_SEL_7_TO_0_8814B)
+#define BIT_SET_GPIO_IO_SEL_7_TO_0_8814B(x, v) \
+ (BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8814B(x) | \
+ BIT_GPIO_IO_SEL_7_TO_0_8814B(v))
+
+#define BIT_SHIFT_GPIO_OUT_7_TO_0_8814B 8
+#define BIT_MASK_GPIO_OUT_7_TO_0_8814B 0xff
+#define BIT_GPIO_OUT_7_TO_0_8814B(x) \
+ (((x) & BIT_MASK_GPIO_OUT_7_TO_0_8814B) \
+ << BIT_SHIFT_GPIO_OUT_7_TO_0_8814B)
+#define BITS_GPIO_OUT_7_TO_0_8814B \
+ (BIT_MASK_GPIO_OUT_7_TO_0_8814B << BIT_SHIFT_GPIO_OUT_7_TO_0_8814B)
+#define BIT_CLEAR_GPIO_OUT_7_TO_0_8814B(x) ((x) & (~BITS_GPIO_OUT_7_TO_0_8814B))
+#define BIT_GET_GPIO_OUT_7_TO_0_8814B(x) \
+ (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8814B) & \
+ BIT_MASK_GPIO_OUT_7_TO_0_8814B)
+#define BIT_SET_GPIO_OUT_7_TO_0_8814B(x, v) \
+ (BIT_CLEAR_GPIO_OUT_7_TO_0_8814B(x) | BIT_GPIO_OUT_7_TO_0_8814B(v))
+
+#define BIT_SHIFT_GPIO_IN_7_TO_0_8814B 0
+#define BIT_MASK_GPIO_IN_7_TO_0_8814B 0xff
+#define BIT_GPIO_IN_7_TO_0_8814B(x) \
+ (((x) & BIT_MASK_GPIO_IN_7_TO_0_8814B) \
+ << BIT_SHIFT_GPIO_IN_7_TO_0_8814B)
+#define BITS_GPIO_IN_7_TO_0_8814B \
+ (BIT_MASK_GPIO_IN_7_TO_0_8814B << BIT_SHIFT_GPIO_IN_7_TO_0_8814B)
+#define BIT_CLEAR_GPIO_IN_7_TO_0_8814B(x) ((x) & (~BITS_GPIO_IN_7_TO_0_8814B))
+#define BIT_GET_GPIO_IN_7_TO_0_8814B(x) \
+ (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8814B) & \
+ BIT_MASK_GPIO_IN_7_TO_0_8814B)
+#define BIT_SET_GPIO_IN_7_TO_0_8814B(x, v) \
+ (BIT_CLEAR_GPIO_IN_7_TO_0_8814B(x) | BIT_GPIO_IN_7_TO_0_8814B(v))
+
+/* 2 REG_GPIO_INTM_8814B */
+
+#define BIT_SHIFT_MUXDBG_SEL_8814B 30
+#define BIT_MASK_MUXDBG_SEL_8814B 0x3
+#define BIT_MUXDBG_SEL_8814B(x) \
+ (((x) & BIT_MASK_MUXDBG_SEL_8814B) << BIT_SHIFT_MUXDBG_SEL_8814B)
+#define BITS_MUXDBG_SEL_8814B \
+ (BIT_MASK_MUXDBG_SEL_8814B << BIT_SHIFT_MUXDBG_SEL_8814B)
+#define BIT_CLEAR_MUXDBG_SEL_8814B(x) ((x) & (~BITS_MUXDBG_SEL_8814B))
+#define BIT_GET_MUXDBG_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_MUXDBG_SEL_8814B) & BIT_MASK_MUXDBG_SEL_8814B)
+#define BIT_SET_MUXDBG_SEL_8814B(x, v) \
+ (BIT_CLEAR_MUXDBG_SEL_8814B(x) | BIT_MUXDBG_SEL_8814B(v))
+
+#define BIT_EXTWOL_SEL_8814B BIT(17)
+#define BIT_EXTWOL_EN_8814B BIT(16)
+#define BIT_GPIOF_INT_MD_8814B BIT(15)
+#define BIT_GPIOE_INT_MD_8814B BIT(14)
+#define BIT_GPIOD_INT_MD_8814B BIT(13)
+#define BIT_GPIOF_INT_MD_8814B BIT(15)
+#define BIT_GPIOE_INT_MD_8814B BIT(14)
+#define BIT_GPIOD_INT_MD_8814B BIT(13)
+#define BIT_GPIOC_INT_MD_8814B BIT(12)
+#define BIT_GPIOB_INT_MD_8814B BIT(11)
+#define BIT_GPIOA_INT_MD_8814B BIT(10)
+#define BIT_GPIO9_INT_MD_8814B BIT(9)
+#define BIT_GPIO8_INT_MD_8814B BIT(8)
+#define BIT_GPIO7_INT_MD_8814B BIT(7)
+#define BIT_GPIO6_INT_MD_8814B BIT(6)
+#define BIT_GPIO5_INT_MD_8814B BIT(5)
+#define BIT_GPIO4_INT_MD_8814B BIT(4)
+#define BIT_GPIO3_INT_MD_8814B BIT(3)
+#define BIT_GPIO2_INT_MD_8814B BIT(2)
+#define BIT_GPIO1_INT_MD_8814B BIT(1)
+#define BIT_GPIO0_INT_MD_8814B BIT(0)
+
+/* 2 REG_LED_CFG_8814B */
+#define BIT_GPIO3_WL_CTRL_EN_8814B BIT(27)
+#define BIT_LNAON_SEL_EN_8814B BIT(26)
+#define BIT_PAPE_SEL_EN_8814B BIT(25)
+#define BIT_DPDT_WLBT_SEL_8814B BIT(24)
+#define BIT_DPDT_SEL_EN_8814B BIT(23)
+#define BIT_GPIO13_14_WL_CTRL_EN_8814B BIT(22)
+#define BIT_LED2DIS_8814B BIT(21)
+#define BIT_LED2PL_8814B BIT(20)
+#define BIT_LED2SV_8814B BIT(19)
+
+#define BIT_SHIFT_LED2CM_8814B 16
+#define BIT_MASK_LED2CM_8814B 0x7
+#define BIT_LED2CM_8814B(x) \
+ (((x) & BIT_MASK_LED2CM_8814B) << BIT_SHIFT_LED2CM_8814B)
+#define BITS_LED2CM_8814B (BIT_MASK_LED2CM_8814B << BIT_SHIFT_LED2CM_8814B)
+#define BIT_CLEAR_LED2CM_8814B(x) ((x) & (~BITS_LED2CM_8814B))
+#define BIT_GET_LED2CM_8814B(x) \
+ (((x) >> BIT_SHIFT_LED2CM_8814B) & BIT_MASK_LED2CM_8814B)
+#define BIT_SET_LED2CM_8814B(x, v) \
+ (BIT_CLEAR_LED2CM_8814B(x) | BIT_LED2CM_8814B(v))
+
+#define BIT_LED1DIS_8814B BIT(15)
+#define BIT_LED1PL_8814B BIT(12)
+#define BIT_LED1SV_8814B BIT(11)
+
+#define BIT_SHIFT_LED1CM_8814B 8
+#define BIT_MASK_LED1CM_8814B 0x7
+#define BIT_LED1CM_8814B(x) \
+ (((x) & BIT_MASK_LED1CM_8814B) << BIT_SHIFT_LED1CM_8814B)
+#define BITS_LED1CM_8814B (BIT_MASK_LED1CM_8814B << BIT_SHIFT_LED1CM_8814B)
+#define BIT_CLEAR_LED1CM_8814B(x) ((x) & (~BITS_LED1CM_8814B))
+#define BIT_GET_LED1CM_8814B(x) \
+ (((x) >> BIT_SHIFT_LED1CM_8814B) & BIT_MASK_LED1CM_8814B)
+#define BIT_SET_LED1CM_8814B(x, v) \
+ (BIT_CLEAR_LED1CM_8814B(x) | BIT_LED1CM_8814B(v))
+
+#define BIT_LED0DIS_8814B BIT(7)
+
+#define BIT_SHIFT_AFE_LDO_SWR_CHECK_8814B 5
+#define BIT_MASK_AFE_LDO_SWR_CHECK_8814B 0x3
+#define BIT_AFE_LDO_SWR_CHECK_8814B(x) \
+ (((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8814B) \
+ << BIT_SHIFT_AFE_LDO_SWR_CHECK_8814B)
+#define BITS_AFE_LDO_SWR_CHECK_8814B \
+ (BIT_MASK_AFE_LDO_SWR_CHECK_8814B << BIT_SHIFT_AFE_LDO_SWR_CHECK_8814B)
+#define BIT_CLEAR_AFE_LDO_SWR_CHECK_8814B(x) \
+ ((x) & (~BITS_AFE_LDO_SWR_CHECK_8814B))
+#define BIT_GET_AFE_LDO_SWR_CHECK_8814B(x) \
+ (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8814B) & \
+ BIT_MASK_AFE_LDO_SWR_CHECK_8814B)
+#define BIT_SET_AFE_LDO_SWR_CHECK_8814B(x, v) \
+ (BIT_CLEAR_AFE_LDO_SWR_CHECK_8814B(x) | BIT_AFE_LDO_SWR_CHECK_8814B(v))
+
+#define BIT_LED0PL_8814B BIT(4)
+#define BIT_LED0SV_8814B BIT(3)
+
+#define BIT_SHIFT_LED0CM_8814B 0
+#define BIT_MASK_LED0CM_8814B 0x7
+#define BIT_LED0CM_8814B(x) \
+ (((x) & BIT_MASK_LED0CM_8814B) << BIT_SHIFT_LED0CM_8814B)
+#define BITS_LED0CM_8814B (BIT_MASK_LED0CM_8814B << BIT_SHIFT_LED0CM_8814B)
+#define BIT_CLEAR_LED0CM_8814B(x) ((x) & (~BITS_LED0CM_8814B))
+#define BIT_GET_LED0CM_8814B(x) \
+ (((x) >> BIT_SHIFT_LED0CM_8814B) & BIT_MASK_LED0CM_8814B)
+#define BIT_SET_LED0CM_8814B(x, v) \
+ (BIT_CLEAR_LED0CM_8814B(x) | BIT_LED0CM_8814B(v))
+
+/* 2 REG_FSIMR_8814B */
+#define BIT_FS_PDNINT_EN_8814B BIT(31)
+#define BIT_NFC_INT_PAD_EN_8814B BIT(30)
+#define BIT_FS_SPS_OCP_INT_EN_8814B BIT(29)
+#define BIT_FS_PWMERR_INT_EN_8814B BIT(28)
+#define BIT_FS_GPIOF_INT_EN_8814B BIT(27)
+#define BIT_FS_GPIOE_INT_EN_8814B BIT(26)
+#define BIT_FS_GPIOD_INT_EN_8814B BIT(25)
+#define BIT_FS_GPIOC_INT_EN_8814B BIT(24)
+#define BIT_FS_GPIOB_INT_EN_8814B BIT(23)
+#define BIT_FS_GPIOA_INT_EN_8814B BIT(22)
+#define BIT_FS_GPIO9_INT_EN_8814B BIT(21)
+#define BIT_FS_GPIO8_INT_EN_8814B BIT(20)
+#define BIT_FS_GPIO7_INT_EN_8814B BIT(19)
+#define BIT_FS_GPIO6_INT_EN_8814B BIT(18)
+#define BIT_FS_GPIO5_INT_EN_8814B BIT(17)
+#define BIT_FS_GPIO4_INT_EN_8814B BIT(16)
+#define BIT_FS_GPIO3_INT_EN_8814B BIT(15)
+#define BIT_FS_GPIO2_INT_EN_8814B BIT(14)
+#define BIT_FS_GPIO1_INT_EN_8814B BIT(13)
+#define BIT_FS_GPIO0_INT_EN_8814B BIT(12)
+#define BIT_FS_HCI_SUS_EN_8814B BIT(11)
+#define BIT_FS_HCI_RES_EN_8814B BIT(10)
+#define BIT_FS_HCI_RESET_EN_8814B BIT(9)
+#define BIT_USB_SCSI_CMD_EN_8814B BIT(8)
+#define BIT_FS_BTON_STS_UPDATE_MSK_EN_8814B BIT(7)
+#define BIT_ACT2RECOVERY_INT_EN_V1_8814B BIT(6)
+#define BIT_GEN1GEN2_SWITCH_8814B BIT(5)
+#define BIT_HCI_TXDMA_REQ_HIMR_8814B BIT(4)
+#define BIT_FS_32K_LEAVE_SETTING_MAK_8814B BIT(3)
+#define BIT_FS_32K_ENTER_SETTING_MAK_8814B BIT(2)
+#define BIT_FS_USB_LPMRSM_MSK_8814B BIT(1)
+#define BIT_FS_USB_LPMINT_MSK_8814B BIT(0)
+
+/* 2 REG_FSISR_8814B */
+#define BIT_FS_PDNINT_8814B BIT(31)
+#define BIT_FS_SPS_OCP_INT_8814B BIT(29)
+#define BIT_FS_PWMERR_INT_8814B BIT(28)
+#define BIT_FS_GPIOF_INT_8814B BIT(27)
+#define BIT_FS_GPIOE_INT_8814B BIT(26)
+#define BIT_FS_GPIOD_INT_8814B BIT(25)
+#define BIT_FS_GPIOC_INT_8814B BIT(24)
+#define BIT_FS_GPIOB_INT_8814B BIT(23)
+#define BIT_FS_GPIOA_INT_8814B BIT(22)
+#define BIT_FS_GPIO9_INT_8814B BIT(21)
+#define BIT_FS_GPIO8_INT_8814B BIT(20)
+#define BIT_FS_GPIO7_INT_8814B BIT(19)
+#define BIT_FS_GPIO6_INT_8814B BIT(18)
+#define BIT_FS_GPIO5_INT_8814B BIT(17)
+#define BIT_FS_GPIO4_INT_8814B BIT(16)
+#define BIT_FS_GPIO3_INT_8814B BIT(15)
+#define BIT_FS_GPIO2_INT_8814B BIT(14)
+#define BIT_FS_GPIO1_INT_8814B BIT(13)
+#define BIT_FS_GPIO0_INT_8814B BIT(12)
+#define BIT_FS_HCI_SUS_INT_8814B BIT(11)
+#define BIT_FS_HCI_RES_INT_8814B BIT(10)
+#define BIT_FS_HCI_RESET_INT_8814B BIT(9)
+#define BIT_USB_SCSI_CMD_INT_8814B BIT(8)
+#define BIT_FS_BTON_STS_UPDATE_INT_8814B BIT(7)
+#define BIT_ACT2RECOVERY_8814B BIT(6)
+#define BIT_GEN1GEN2_SWITCH_8814B BIT(5)
+#define BIT_HCI_TXDMA_REQ_HISR_8814B BIT(4)
+#define BIT_FS_32K_LEAVE_SETTING_INT_8814B BIT(3)
+#define BIT_FS_32K_ENTER_SETTING_INT_8814B BIT(2)
+#define BIT_FS_USB_LPMRSM_INT_8814B BIT(1)
+#define BIT_FS_USB_LPMINT_INT_8814B BIT(0)
+
+/* 2 REG_HSIMR_8814B */
+#define BIT_GPIOF_INT_EN_8814B BIT(31)
+#define BIT_GPIOE_INT_EN_8814B BIT(30)
+#define BIT_GPIOD_INT_EN_8814B BIT(29)
+#define BIT_GPIOC_INT_EN_8814B BIT(28)
+#define BIT_GPIOB_INT_EN_8814B BIT(27)
+#define BIT_GPIOA_INT_EN_8814B BIT(26)
+#define BIT_GPIO9_INT_EN_8814B BIT(25)
+#define BIT_GPIO8_INT_EN_8814B BIT(24)
+#define BIT_GPIO7_INT_EN_8814B BIT(23)
+#define BIT_GPIO6_INT_EN_8814B BIT(22)
+#define BIT_GPIO5_INT_EN_8814B BIT(21)
+#define BIT_GPIO4_INT_EN_8814B BIT(20)
+#define BIT_GPIO3_INT_EN_8814B BIT(19)
+#define BIT_GPIO2_INT_EN_V1_8814B BIT(18)
+#define BIT_GPIO1_INT_EN_8814B BIT(17)
+#define BIT_GPIO0_INT_EN_8814B BIT(16)
+#define BIT_PDNINT_EN_8814B BIT(7)
+#define BIT_RON_INT_EN_8814B BIT(6)
+#define BIT_SPS_OCP_INT_EN_8814B BIT(5)
+#define BIT_GPIO15_0_INT_EN_8814B BIT(0)
+
+/* 2 REG_HSISR_8814B */
+#define BIT_GPIOF_INT_8814B BIT(31)
+#define BIT_GPIOE_INT_8814B BIT(30)
+#define BIT_GPIOD_INT_8814B BIT(29)
+#define BIT_GPIOC_INT_8814B BIT(28)
+#define BIT_GPIOB_INT_8814B BIT(27)
+#define BIT_GPIOA_INT_8814B BIT(26)
+#define BIT_GPIO9_INT_8814B BIT(25)
+#define BIT_GPIO8_INT_8814B BIT(24)
+#define BIT_GPIO7_INT_8814B BIT(23)
+#define BIT_GPIO6_INT_8814B BIT(22)
+#define BIT_GPIO5_INT_8814B BIT(21)
+#define BIT_GPIO4_INT_8814B BIT(20)
+#define BIT_GPIO3_INT_8814B BIT(19)
+#define BIT_GPIO2_INT_V1_8814B BIT(18)
+#define BIT_GPIO1_INT_8814B BIT(17)
+#define BIT_GPIO0_INT_8814B BIT(16)
+#define BIT_PDNINT_8814B BIT(7)
+#define BIT_RON_INT_8814B BIT(6)
+#define BIT_SPS_OCP_INT_8814B BIT(5)
+#define BIT_GPIO15_0_INT_8814B BIT(0)
+
+/* 2 REG_GPIO_EXT_CTRL_8814B */
+
+#define BIT_SHIFT_GPIO_MOD_15_TO_8_8814B 24
+#define BIT_MASK_GPIO_MOD_15_TO_8_8814B 0xff
+#define BIT_GPIO_MOD_15_TO_8_8814B(x) \
+ (((x) & BIT_MASK_GPIO_MOD_15_TO_8_8814B) \
+ << BIT_SHIFT_GPIO_MOD_15_TO_8_8814B)
+#define BITS_GPIO_MOD_15_TO_8_8814B \
+ (BIT_MASK_GPIO_MOD_15_TO_8_8814B << BIT_SHIFT_GPIO_MOD_15_TO_8_8814B)
+#define BIT_CLEAR_GPIO_MOD_15_TO_8_8814B(x) \
+ ((x) & (~BITS_GPIO_MOD_15_TO_8_8814B))
+#define BIT_GET_GPIO_MOD_15_TO_8_8814B(x) \
+ (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8814B) & \
+ BIT_MASK_GPIO_MOD_15_TO_8_8814B)
+#define BIT_SET_GPIO_MOD_15_TO_8_8814B(x, v) \
+ (BIT_CLEAR_GPIO_MOD_15_TO_8_8814B(x) | BIT_GPIO_MOD_15_TO_8_8814B(v))
+
+#define BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8814B 16
+#define BIT_MASK_GPIO_IO_SEL_15_TO_8_8814B 0xff
+#define BIT_GPIO_IO_SEL_15_TO_8_8814B(x) \
+ (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8814B) \
+ << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8814B)
+#define BITS_GPIO_IO_SEL_15_TO_8_8814B \
+ (BIT_MASK_GPIO_IO_SEL_15_TO_8_8814B \
+ << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8814B)
+#define BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8814B(x) \
+ ((x) & (~BITS_GPIO_IO_SEL_15_TO_8_8814B))
+#define BIT_GET_GPIO_IO_SEL_15_TO_8_8814B(x) \
+ (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8814B) & \
+ BIT_MASK_GPIO_IO_SEL_15_TO_8_8814B)
+#define BIT_SET_GPIO_IO_SEL_15_TO_8_8814B(x, v) \
+ (BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8814B(x) | \
+ BIT_GPIO_IO_SEL_15_TO_8_8814B(v))
+
+#define BIT_SHIFT_GPIO_OUT_15_TO_8_8814B 8
+#define BIT_MASK_GPIO_OUT_15_TO_8_8814B 0xff
+#define BIT_GPIO_OUT_15_TO_8_8814B(x) \
+ (((x) & BIT_MASK_GPIO_OUT_15_TO_8_8814B) \
+ << BIT_SHIFT_GPIO_OUT_15_TO_8_8814B)
+#define BITS_GPIO_OUT_15_TO_8_8814B \
+ (BIT_MASK_GPIO_OUT_15_TO_8_8814B << BIT_SHIFT_GPIO_OUT_15_TO_8_8814B)
+#define BIT_CLEAR_GPIO_OUT_15_TO_8_8814B(x) \
+ ((x) & (~BITS_GPIO_OUT_15_TO_8_8814B))
+#define BIT_GET_GPIO_OUT_15_TO_8_8814B(x) \
+ (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8814B) & \
+ BIT_MASK_GPIO_OUT_15_TO_8_8814B)
+#define BIT_SET_GPIO_OUT_15_TO_8_8814B(x, v) \
+ (BIT_CLEAR_GPIO_OUT_15_TO_8_8814B(x) | BIT_GPIO_OUT_15_TO_8_8814B(v))
+
+#define BIT_SHIFT_GPIO_IN_15_TO_8_8814B 0
+#define BIT_MASK_GPIO_IN_15_TO_8_8814B 0xff
+#define BIT_GPIO_IN_15_TO_8_8814B(x) \
+ (((x) & BIT_MASK_GPIO_IN_15_TO_8_8814B) \
+ << BIT_SHIFT_GPIO_IN_15_TO_8_8814B)
+#define BITS_GPIO_IN_15_TO_8_8814B \
+ (BIT_MASK_GPIO_IN_15_TO_8_8814B << BIT_SHIFT_GPIO_IN_15_TO_8_8814B)
+#define BIT_CLEAR_GPIO_IN_15_TO_8_8814B(x) ((x) & (~BITS_GPIO_IN_15_TO_8_8814B))
+#define BIT_GET_GPIO_IN_15_TO_8_8814B(x) \
+ (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8814B) & \
+ BIT_MASK_GPIO_IN_15_TO_8_8814B)
+#define BIT_SET_GPIO_IN_15_TO_8_8814B(x, v) \
+ (BIT_CLEAR_GPIO_IN_15_TO_8_8814B(x) | BIT_GPIO_IN_15_TO_8_8814B(v))
+
+/* 2 REG_PAD_CTRL1_8814B */
+#define BIT_DATA_CPU_JTAG_8814B BIT(30)
+#define BIT_PAPE_WLBT_SEL_8814B BIT(29)
+#define BIT_LNAON_WLBT_SEL_8814B BIT(28)
+#define BIT_BTGP_GPG3_FEN_8814B BIT(26)
+#define BIT_BTGP_GPG2_FEN_8814B BIT(25)
+#define BIT_BTGP_JTAG_EN_8814B BIT(24)
+#define BIT_XTAL_CLK_EXTARNAL_EN_8814B BIT(23)
+#define BIT_BTGP_UART0_EN_8814B BIT(22)
+#define BIT_BTGP_UART1_EN_8814B BIT(21)
+#define BIT_BTGP_SPI_EN_8814B BIT(20)
+#define BIT_BTGP_GPIO_E2_8814B BIT(19)
+#define BIT_BTGP_GPIO_EN_8814B BIT(18)
+
+#define BIT_SHIFT_BTGP_GPIO_SL_8814B 16
+#define BIT_MASK_BTGP_GPIO_SL_8814B 0x3
+#define BIT_BTGP_GPIO_SL_8814B(x) \
+ (((x) & BIT_MASK_BTGP_GPIO_SL_8814B) << BIT_SHIFT_BTGP_GPIO_SL_8814B)
+#define BITS_BTGP_GPIO_SL_8814B \
+ (BIT_MASK_BTGP_GPIO_SL_8814B << BIT_SHIFT_BTGP_GPIO_SL_8814B)
+#define BIT_CLEAR_BTGP_GPIO_SL_8814B(x) ((x) & (~BITS_BTGP_GPIO_SL_8814B))
+#define BIT_GET_BTGP_GPIO_SL_8814B(x) \
+ (((x) >> BIT_SHIFT_BTGP_GPIO_SL_8814B) & BIT_MASK_BTGP_GPIO_SL_8814B)
+#define BIT_SET_BTGP_GPIO_SL_8814B(x, v) \
+ (BIT_CLEAR_BTGP_GPIO_SL_8814B(x) | BIT_BTGP_GPIO_SL_8814B(v))
+
+#define BIT_WL_JTAG_8814B BIT(15)
+#define BIT_PAD_SDIO_SR_8814B BIT(14)
+#define BIT_GPIO14_OUTPUT_PL_8814B BIT(13)
+#define BIT_HOST_WAKE_PAD_PULL_EN_8814B BIT(12)
+#define BIT_HOST_WAKE_PAD_SL_8814B BIT(11)
+#define BIT_SW_LNAON_G_SEL_DATA_8814B BIT(8)
+#define BIT_SW_LNAON_A_SEL_DATA_8814B BIT(7)
+#define BIT_SW_PAPE_G_SEL_DATA_8814B BIT(4)
+#define BIT_SW_PAPE_A_SEL_DATA_8814B BIT(3)
+#define BIT_SW_DPDT_SEL_DATA_8814B BIT(0)
+
+/* 2 REG_WL_BT_PWR_CTRL_8814B */
+#define BIT_ISO_BD2PP_8814B BIT(31)
+#define BIT_LDOV12B_EN_8814B BIT(30)
+#define BIT_CKEN_BTGPS_8814B BIT(29)
+#define BIT_FEN_BTGPS_8814B BIT(28)
+#define BIT_BTCPU_BOOTSEL_8814B BIT(27)
+#define BIT_SPI_SPEEDUP_8814B BIT(26)
+#define BIT_BT_SUS_8814B BIT(25)
+#define BIT_DEVWAKE_PAD_TYPE_SEL_8814B BIT(24)
+#define BIT_CLKREQ_PAD_TYPE_SEL_8814B BIT(23)
+#define BIT_ISO_BTPON2PP_8814B BIT(22)
+#define BIT_BTCOEX_CMD_8814B BIT(21)
+#define BIT_BT_UART_INTF_8814B BIT(20)
+#define BIT_BT_HWROF_EN_8814B BIT(19)
+#define BIT_BT_FUNC_EN_8814B BIT(18)
+#define BIT_BT_HWPDN_SL_8814B BIT(17)
+#define BIT_BT_DISN_EN_8814B BIT(16)
+#define BIT_BT_PDN_PULL_EN_8814B BIT(15)
+#define BIT_WL_PDN_PULL_EN_8814B BIT(14)
+#define BIT_EXTERNAL_REQUEST_PL_8814B BIT(13)
+#define BIT_GPIO0_2_3_PULL_LOW_EN_8814B BIT(12)
+#define BIT_ISO_BA2PP_8814B BIT(11)
+#define BIT_BT_AFE_LDO_EN_8814B BIT(10)
+#define BIT_BT_AFE_PLL_EN_8814B BIT(9)
+#define BIT_BT_DIG_CLK_EN_8814B BIT(8)
+#define BIT_UART_BRIDGE_8814B BIT(7)
+#define BIT_OSC32K_CTRL_SEL_8814B BIT(6)
+#define BIT_WL_DRV_EXIST_IDX_8814B BIT(5)
+#define BIT_DOP_EHPAD_8814B BIT(4)
+#define BIT_WL_HWROF_EN_8814B BIT(3)
+#define BIT_WL_FUNC_EN_8814B BIT(2)
+#define BIT_WL_HWPDN_SL_8814B BIT(1)
+#define BIT_WL_HWPDN_EN_8814B BIT(0)
+
+/* 2 REG_SDM_DEBUG_8814B */
+#define BIT_BT_WAKE_DEV_EN_V1_8814B BIT(19)
+#define BIT_BT_WAKE_HST_EN_V1_8814B BIT(18)
+#define BIT_BT_WAKE_HST_PL_V1_8814B BIT(17)
+#define BIT_BT_CLKREQ_EN_V1_8814B BIT(16)
+
+#define BIT_SHIFT_WLCLK_PHASE_8814B 0
+#define BIT_MASK_WLCLK_PHASE_8814B 0x1f
+#define BIT_WLCLK_PHASE_8814B(x) \
+ (((x) & BIT_MASK_WLCLK_PHASE_8814B) << BIT_SHIFT_WLCLK_PHASE_8814B)
+#define BITS_WLCLK_PHASE_8814B \
+ (BIT_MASK_WLCLK_PHASE_8814B << BIT_SHIFT_WLCLK_PHASE_8814B)
+#define BIT_CLEAR_WLCLK_PHASE_8814B(x) ((x) & (~BITS_WLCLK_PHASE_8814B))
+#define BIT_GET_WLCLK_PHASE_8814B(x) \
+ (((x) >> BIT_SHIFT_WLCLK_PHASE_8814B) & BIT_MASK_WLCLK_PHASE_8814B)
+#define BIT_SET_WLCLK_PHASE_8814B(x, v) \
+ (BIT_CLEAR_WLCLK_PHASE_8814B(x) | BIT_WLCLK_PHASE_8814B(v))
+
+/* 2 REG_SYS_SDIO_CTRL_8814B */
+#define BIT_DBG_GNT_WL_BT_8814B BIT(27)
+#define BIT_LTE_MUX_CTRL_PATH_8814B BIT(26)
+#define BIT_LTE_COEX_UART_8814B BIT(25)
+#define BIT_3W_LTE_WL_GPIO_8814B BIT(24)
+#define BIT_SDIO_INT_POLARITY_8814B BIT(19)
+#define BIT_SDIO_INT_8814B BIT(18)
+#define BIT_SDIO_OFF_EN_8814B BIT(17)
+#define BIT_SDIO_ON_EN_8814B BIT(16)
+#define BIT_PCIE_WAIT_TIMEOUT_EVENT_8814B BIT(10)
+#define BIT_PCIE_WAIT_TIME_8814B BIT(9)
+#define BIT_MPCIE_REFCLK_XTAL_SEL_8814B BIT(8)
+#define BIT_BT_CLKREQ_EN_8814B BIT(6)
+
+#define BIT_SHIFT_USB_CKREF_CML_R_8814B 4
+#define BIT_MASK_USB_CKREF_CML_R_8814B 0x3
+#define BIT_USB_CKREF_CML_R_8814B(x) \
+ (((x) & BIT_MASK_USB_CKREF_CML_R_8814B) \
+ << BIT_SHIFT_USB_CKREF_CML_R_8814B)
+#define BITS_USB_CKREF_CML_R_8814B \
+ (BIT_MASK_USB_CKREF_CML_R_8814B << BIT_SHIFT_USB_CKREF_CML_R_8814B)
+#define BIT_CLEAR_USB_CKREF_CML_R_8814B(x) ((x) & (~BITS_USB_CKREF_CML_R_8814B))
+#define BIT_GET_USB_CKREF_CML_R_8814B(x) \
+ (((x) >> BIT_SHIFT_USB_CKREF_CML_R_8814B) & \
+ BIT_MASK_USB_CKREF_CML_R_8814B)
+#define BIT_SET_USB_CKREF_CML_R_8814B(x, v) \
+ (BIT_CLEAR_USB_CKREF_CML_R_8814B(x) | BIT_USB_CKREF_CML_R_8814B(v))
+
+#define BIT_SHIFT_USB_CKREF_D2S_I_8814B 2
+#define BIT_MASK_USB_CKREF_D2S_I_8814B 0x3
+#define BIT_USB_CKREF_D2S_I_8814B(x) \
+ (((x) & BIT_MASK_USB_CKREF_D2S_I_8814B) \
+ << BIT_SHIFT_USB_CKREF_D2S_I_8814B)
+#define BITS_USB_CKREF_D2S_I_8814B \
+ (BIT_MASK_USB_CKREF_D2S_I_8814B << BIT_SHIFT_USB_CKREF_D2S_I_8814B)
+#define BIT_CLEAR_USB_CKREF_D2S_I_8814B(x) ((x) & (~BITS_USB_CKREF_D2S_I_8814B))
+#define BIT_GET_USB_CKREF_D2S_I_8814B(x) \
+ (((x) >> BIT_SHIFT_USB_CKREF_D2S_I_8814B) & \
+ BIT_MASK_USB_CKREF_D2S_I_8814B)
+#define BIT_SET_USB_CKREF_D2S_I_8814B(x, v) \
+ (BIT_CLEAR_USB_CKREF_D2S_I_8814B(x) | BIT_USB_CKREF_D2S_I_8814B(v))
+
+#define BIT_RES_USB_MASS_STORAGE_DESC_8814B BIT(1)
+#define BIT_USB_WAIT_TIME_8814B BIT(0)
+
+/* 2 REG_HCI_OPT_CTRL_8814B */
+
+#define BIT_SHIFT_TSFT_SEL_8814B 29
+#define BIT_MASK_TSFT_SEL_8814B 0x7
+#define BIT_TSFT_SEL_8814B(x) \
+ (((x) & BIT_MASK_TSFT_SEL_8814B) << BIT_SHIFT_TSFT_SEL_8814B)
+#define BITS_TSFT_SEL_8814B \
+ (BIT_MASK_TSFT_SEL_8814B << BIT_SHIFT_TSFT_SEL_8814B)
+#define BIT_CLEAR_TSFT_SEL_8814B(x) ((x) & (~BITS_TSFT_SEL_8814B))
+#define BIT_GET_TSFT_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_TSFT_SEL_8814B) & BIT_MASK_TSFT_SEL_8814B)
+#define BIT_SET_TSFT_SEL_8814B(x, v) \
+ (BIT_CLEAR_TSFT_SEL_8814B(x) | BIT_TSFT_SEL_8814B(v))
+
+#define BIT_TSFT_BAND_SEL_8814B BIT(28)
+#define BIT_USB_HOST_PWR_OFF_EN_8814B BIT(12)
+#define BIT_SYM_LPS_BLOCK_EN_8814B BIT(11)
+#define BIT_USB_LPM_ACT_EN_8814B BIT(10)
+#define BIT_USB_LPM_NY_8814B BIT(9)
+#define BIT_USB_SUS_DIS_8814B BIT(8)
+
+#define BIT_SHIFT_SDIO_PAD_E_8814B 5
+#define BIT_MASK_SDIO_PAD_E_8814B 0x7
+#define BIT_SDIO_PAD_E_8814B(x) \
+ (((x) & BIT_MASK_SDIO_PAD_E_8814B) << BIT_SHIFT_SDIO_PAD_E_8814B)
+#define BITS_SDIO_PAD_E_8814B \
+ (BIT_MASK_SDIO_PAD_E_8814B << BIT_SHIFT_SDIO_PAD_E_8814B)
+#define BIT_CLEAR_SDIO_PAD_E_8814B(x) ((x) & (~BITS_SDIO_PAD_E_8814B))
+#define BIT_GET_SDIO_PAD_E_8814B(x) \
+ (((x) >> BIT_SHIFT_SDIO_PAD_E_8814B) & BIT_MASK_SDIO_PAD_E_8814B)
+#define BIT_SET_SDIO_PAD_E_8814B(x, v) \
+ (BIT_CLEAR_SDIO_PAD_E_8814B(x) | BIT_SDIO_PAD_E_8814B(v))
+
+#define BIT_USB_LPPLL_EN_8814B BIT(4)
+#define BIT_ROP_SW15_8814B BIT(2)
+#define BIT_PCI_CKRDY_OPT_8814B BIT(1)
+#define BIT_PCI_VAUX_EN_8814B BIT(0)
+
+/* 2 REG_AFE_CTRL4_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_LDO_SWR_CTRL_8814B */
+#define BIT_ZCD_HW_AUTO_EN_8814B BIT(27)
+#define BIT_ZCD_REGSEL_8814B BIT(26)
+
+#define BIT_SHIFT_AUTO_ZCD_IN_CODE_8814B 21
+#define BIT_MASK_AUTO_ZCD_IN_CODE_8814B 0x1f
+#define BIT_AUTO_ZCD_IN_CODE_8814B(x) \
+ (((x) & BIT_MASK_AUTO_ZCD_IN_CODE_8814B) \
+ << BIT_SHIFT_AUTO_ZCD_IN_CODE_8814B)
+#define BITS_AUTO_ZCD_IN_CODE_8814B \
+ (BIT_MASK_AUTO_ZCD_IN_CODE_8814B << BIT_SHIFT_AUTO_ZCD_IN_CODE_8814B)
+#define BIT_CLEAR_AUTO_ZCD_IN_CODE_8814B(x) \
+ ((x) & (~BITS_AUTO_ZCD_IN_CODE_8814B))
+#define BIT_GET_AUTO_ZCD_IN_CODE_8814B(x) \
+ (((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE_8814B) & \
+ BIT_MASK_AUTO_ZCD_IN_CODE_8814B)
+#define BIT_SET_AUTO_ZCD_IN_CODE_8814B(x, v) \
+ (BIT_CLEAR_AUTO_ZCD_IN_CODE_8814B(x) | BIT_AUTO_ZCD_IN_CODE_8814B(v))
+
+#define BIT_SHIFT_ZCD_CODE_IN_L_8814B 16
+#define BIT_MASK_ZCD_CODE_IN_L_8814B 0x1f
+#define BIT_ZCD_CODE_IN_L_8814B(x) \
+ (((x) & BIT_MASK_ZCD_CODE_IN_L_8814B) << BIT_SHIFT_ZCD_CODE_IN_L_8814B)
+#define BITS_ZCD_CODE_IN_L_8814B \
+ (BIT_MASK_ZCD_CODE_IN_L_8814B << BIT_SHIFT_ZCD_CODE_IN_L_8814B)
+#define BIT_CLEAR_ZCD_CODE_IN_L_8814B(x) ((x) & (~BITS_ZCD_CODE_IN_L_8814B))
+#define BIT_GET_ZCD_CODE_IN_L_8814B(x) \
+ (((x) >> BIT_SHIFT_ZCD_CODE_IN_L_8814B) & BIT_MASK_ZCD_CODE_IN_L_8814B)
+#define BIT_SET_ZCD_CODE_IN_L_8814B(x, v) \
+ (BIT_CLEAR_ZCD_CODE_IN_L_8814B(x) | BIT_ZCD_CODE_IN_L_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_MCUFW_CTRL_8814B */
+
+#define BIT_SHIFT_RPWM_8814B 24
+#define BIT_MASK_RPWM_8814B 0xff
+#define BIT_RPWM_8814B(x) (((x) & BIT_MASK_RPWM_8814B) << BIT_SHIFT_RPWM_8814B)
+#define BITS_RPWM_8814B (BIT_MASK_RPWM_8814B << BIT_SHIFT_RPWM_8814B)
+#define BIT_CLEAR_RPWM_8814B(x) ((x) & (~BITS_RPWM_8814B))
+#define BIT_GET_RPWM_8814B(x) \
+ (((x) >> BIT_SHIFT_RPWM_8814B) & BIT_MASK_RPWM_8814B)
+#define BIT_SET_RPWM_8814B(x, v) (BIT_CLEAR_RPWM_8814B(x) | BIT_RPWM_8814B(v))
+
+#define BIT_ANA_PORT_EN_8814B BIT(22)
+#define BIT_MAC_PORT_EN_8814B BIT(21)
+#define BIT_BOOT_FSPI_EN_8814B BIT(20)
+#define BIT_ROM_DLEN_8814B BIT(19)
+
+#define BIT_SHIFT_ROM_PGE_8814B 16
+#define BIT_MASK_ROM_PGE_8814B 0x7
+#define BIT_ROM_PGE_8814B(x) \
+ (((x) & BIT_MASK_ROM_PGE_8814B) << BIT_SHIFT_ROM_PGE_8814B)
+#define BITS_ROM_PGE_8814B (BIT_MASK_ROM_PGE_8814B << BIT_SHIFT_ROM_PGE_8814B)
+#define BIT_CLEAR_ROM_PGE_8814B(x) ((x) & (~BITS_ROM_PGE_8814B))
+#define BIT_GET_ROM_PGE_8814B(x) \
+ (((x) >> BIT_SHIFT_ROM_PGE_8814B) & BIT_MASK_ROM_PGE_8814B)
+#define BIT_SET_ROM_PGE_8814B(x, v) \
+ (BIT_CLEAR_ROM_PGE_8814B(x) | BIT_ROM_PGE_8814B(v))
+
+#define BIT_FW_INIT_RDY_8814B BIT(15)
+#define BIT_FW_DW_RDY_8814B BIT(14)
+
+#define BIT_SHIFT_CPU_CLK_SEL_8814B 12
+#define BIT_MASK_CPU_CLK_SEL_8814B 0x3
+#define BIT_CPU_CLK_SEL_8814B(x) \
+ (((x) & BIT_MASK_CPU_CLK_SEL_8814B) << BIT_SHIFT_CPU_CLK_SEL_8814B)
+#define BITS_CPU_CLK_SEL_8814B \
+ (BIT_MASK_CPU_CLK_SEL_8814B << BIT_SHIFT_CPU_CLK_SEL_8814B)
+#define BIT_CLEAR_CPU_CLK_SEL_8814B(x) ((x) & (~BITS_CPU_CLK_SEL_8814B))
+#define BIT_GET_CPU_CLK_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_CPU_CLK_SEL_8814B) & BIT_MASK_CPU_CLK_SEL_8814B)
+#define BIT_SET_CPU_CLK_SEL_8814B(x, v) \
+ (BIT_CLEAR_CPU_CLK_SEL_8814B(x) | BIT_CPU_CLK_SEL_8814B(v))
+
+#define BIT_CCLK_CHG_MASK_8814B BIT(11)
+#define BIT_EMEM__TXBUF_CHKSUM_OK_8814B BIT(10)
+#define BIT_EMEM_TXBUF_DW_RDY_8814B BIT(9)
+#define BIT_EMEM_CHKSUM_OK_8814B BIT(8)
+#define BIT_EMEM_DW_OK_8814B BIT(7)
+#define BIT_DMEM_CHKSUM_OK_8814B BIT(6)
+#define BIT_DMEM_DW_OK_8814B BIT(5)
+#define BIT_IMEM_CHKSUM_OK_8814B BIT(4)
+#define BIT_IMEM_DW_OK_8814B BIT(3)
+#define BIT_IMEM_BOOT_LOAD_CHKSUM_OK_8814B BIT(2)
+#define BIT_IMEM_BOOT_LOAD_DW_OK_8814B BIT(1)
+#define BIT_MCUFWDL_EN_8814B BIT(0)
+
+/* 2 REG_MCU_TST_CFG_8814B */
+
+#define BIT_SHIFT_C2H_MSG_8814B 0
+#define BIT_MASK_C2H_MSG_8814B 0xffff
+#define BIT_C2H_MSG_8814B(x) \
+ (((x) & BIT_MASK_C2H_MSG_8814B) << BIT_SHIFT_C2H_MSG_8814B)
+#define BITS_C2H_MSG_8814B (BIT_MASK_C2H_MSG_8814B << BIT_SHIFT_C2H_MSG_8814B)
+#define BIT_CLEAR_C2H_MSG_8814B(x) ((x) & (~BITS_C2H_MSG_8814B))
+#define BIT_GET_C2H_MSG_8814B(x) \
+ (((x) >> BIT_SHIFT_C2H_MSG_8814B) & BIT_MASK_C2H_MSG_8814B)
+#define BIT_SET_C2H_MSG_8814B(x, v) \
+ (BIT_CLEAR_C2H_MSG_8814B(x) | BIT_C2H_MSG_8814B(v))
+
+/* 2 REG_HMEBOX_E0_E1_8814B */
+
+#define BIT_SHIFT_HOST_MSG_E1_8814B 16
+#define BIT_MASK_HOST_MSG_E1_8814B 0xffff
+#define BIT_HOST_MSG_E1_8814B(x) \
+ (((x) & BIT_MASK_HOST_MSG_E1_8814B) << BIT_SHIFT_HOST_MSG_E1_8814B)
+#define BITS_HOST_MSG_E1_8814B \
+ (BIT_MASK_HOST_MSG_E1_8814B << BIT_SHIFT_HOST_MSG_E1_8814B)
+#define BIT_CLEAR_HOST_MSG_E1_8814B(x) ((x) & (~BITS_HOST_MSG_E1_8814B))
+#define BIT_GET_HOST_MSG_E1_8814B(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_E1_8814B) & BIT_MASK_HOST_MSG_E1_8814B)
+#define BIT_SET_HOST_MSG_E1_8814B(x, v) \
+ (BIT_CLEAR_HOST_MSG_E1_8814B(x) | BIT_HOST_MSG_E1_8814B(v))
+
+#define BIT_SHIFT_HOST_MSG_E0_8814B 0
+#define BIT_MASK_HOST_MSG_E0_8814B 0xffff
+#define BIT_HOST_MSG_E0_8814B(x) \
+ (((x) & BIT_MASK_HOST_MSG_E0_8814B) << BIT_SHIFT_HOST_MSG_E0_8814B)
+#define BITS_HOST_MSG_E0_8814B \
+ (BIT_MASK_HOST_MSG_E0_8814B << BIT_SHIFT_HOST_MSG_E0_8814B)
+#define BIT_CLEAR_HOST_MSG_E0_8814B(x) ((x) & (~BITS_HOST_MSG_E0_8814B))
+#define BIT_GET_HOST_MSG_E0_8814B(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_E0_8814B) & BIT_MASK_HOST_MSG_E0_8814B)
+#define BIT_SET_HOST_MSG_E0_8814B(x, v) \
+ (BIT_CLEAR_HOST_MSG_E0_8814B(x) | BIT_HOST_MSG_E0_8814B(v))
+
+/* 2 REG_HMEBOX_E2_E3_8814B */
+
+#define BIT_SHIFT_HOST_MSG_E3_8814B 16
+#define BIT_MASK_HOST_MSG_E3_8814B 0xffff
+#define BIT_HOST_MSG_E3_8814B(x) \
+ (((x) & BIT_MASK_HOST_MSG_E3_8814B) << BIT_SHIFT_HOST_MSG_E3_8814B)
+#define BITS_HOST_MSG_E3_8814B \
+ (BIT_MASK_HOST_MSG_E3_8814B << BIT_SHIFT_HOST_MSG_E3_8814B)
+#define BIT_CLEAR_HOST_MSG_E3_8814B(x) ((x) & (~BITS_HOST_MSG_E3_8814B))
+#define BIT_GET_HOST_MSG_E3_8814B(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_E3_8814B) & BIT_MASK_HOST_MSG_E3_8814B)
+#define BIT_SET_HOST_MSG_E3_8814B(x, v) \
+ (BIT_CLEAR_HOST_MSG_E3_8814B(x) | BIT_HOST_MSG_E3_8814B(v))
+
+#define BIT_SHIFT_HOST_MSG_E2_8814B 0
+#define BIT_MASK_HOST_MSG_E2_8814B 0xffff
+#define BIT_HOST_MSG_E2_8814B(x) \
+ (((x) & BIT_MASK_HOST_MSG_E2_8814B) << BIT_SHIFT_HOST_MSG_E2_8814B)
+#define BITS_HOST_MSG_E2_8814B \
+ (BIT_MASK_HOST_MSG_E2_8814B << BIT_SHIFT_HOST_MSG_E2_8814B)
+#define BIT_CLEAR_HOST_MSG_E2_8814B(x) ((x) & (~BITS_HOST_MSG_E2_8814B))
+#define BIT_GET_HOST_MSG_E2_8814B(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_E2_8814B) & BIT_MASK_HOST_MSG_E2_8814B)
+#define BIT_SET_HOST_MSG_E2_8814B(x, v) \
+ (BIT_CLEAR_HOST_MSG_E2_8814B(x) | BIT_HOST_MSG_E2_8814B(v))
+
+/* 2 REG_WLLPS_CTRL_8814B */
+#define BIT_WLLPSOP_EABM_8814B BIT(31)
+#define BIT_WLLPSOP_ACKF_8814B BIT(30)
+#define BIT_WLLPSOP_DLDM_8814B BIT(29)
+#define BIT_WLLPSOP_ESWR_8814B BIT(28)
+#define BIT_WLLPSOP_PWMM_8814B BIT(27)
+#define BIT_WLLPSOP_EECK_8814B BIT(26)
+#define BIT_WLLPSOP_WLMACOFF_8814B BIT(25)
+#define BIT_WLLPSOP_EXTAL_8814B BIT(24)
+#define BIT_WL_SYNPON_VOLTSPDN_8814B BIT(23)
+#define BIT_WLLPSOP_WLBBOFF_8814B BIT(22)
+#define BIT_WLLPSOP_WLMEM_DS_8814B BIT(21)
+
+#define BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8814B 12
+#define BIT_MASK_LPLDH12_VADJ_STEP_DN_8814B 0xf
+#define BIT_LPLDH12_VADJ_STEP_DN_8814B(x) \
+ (((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8814B) \
+ << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8814B)
+#define BITS_LPLDH12_VADJ_STEP_DN_8814B \
+ (BIT_MASK_LPLDH12_VADJ_STEP_DN_8814B \
+ << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8814B)
+#define BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8814B(x) \
+ ((x) & (~BITS_LPLDH12_VADJ_STEP_DN_8814B))
+#define BIT_GET_LPLDH12_VADJ_STEP_DN_8814B(x) \
+ (((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8814B) & \
+ BIT_MASK_LPLDH12_VADJ_STEP_DN_8814B)
+#define BIT_SET_LPLDH12_VADJ_STEP_DN_8814B(x, v) \
+ (BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8814B(x) | \
+ BIT_LPLDH12_VADJ_STEP_DN_8814B(v))
+
+#define BIT_SHIFT_V15ADJ_L1_STEP_DN_8814B 8
+#define BIT_MASK_V15ADJ_L1_STEP_DN_8814B 0x7
+#define BIT_V15ADJ_L1_STEP_DN_8814B(x) \
+ (((x) & BIT_MASK_V15ADJ_L1_STEP_DN_8814B) \
+ << BIT_SHIFT_V15ADJ_L1_STEP_DN_8814B)
+#define BITS_V15ADJ_L1_STEP_DN_8814B \
+ (BIT_MASK_V15ADJ_L1_STEP_DN_8814B << BIT_SHIFT_V15ADJ_L1_STEP_DN_8814B)
+#define BIT_CLEAR_V15ADJ_L1_STEP_DN_8814B(x) \
+ ((x) & (~BITS_V15ADJ_L1_STEP_DN_8814B))
+#define BIT_GET_V15ADJ_L1_STEP_DN_8814B(x) \
+ (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN_8814B) & \
+ BIT_MASK_V15ADJ_L1_STEP_DN_8814B)
+#define BIT_SET_V15ADJ_L1_STEP_DN_8814B(x, v) \
+ (BIT_CLEAR_V15ADJ_L1_STEP_DN_8814B(x) | BIT_V15ADJ_L1_STEP_DN_8814B(v))
+
+#define BIT_REGU_32K_CLK_EN_8814B BIT(1)
+#define BIT_WL_LPS_EN_8814B BIT(0)
+
+/* 2 REG_AFE_CTRL5_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_GPIO_DEBOUNCE_CTRL_8814B */
+#define BIT_WLGP_DBC1EN_8814B BIT(15)
+
+#define BIT_SHIFT_WLGP_DBC1_8814B 8
+#define BIT_MASK_WLGP_DBC1_8814B 0xf
+#define BIT_WLGP_DBC1_8814B(x) \
+ (((x) & BIT_MASK_WLGP_DBC1_8814B) << BIT_SHIFT_WLGP_DBC1_8814B)
+#define BITS_WLGP_DBC1_8814B \
+ (BIT_MASK_WLGP_DBC1_8814B << BIT_SHIFT_WLGP_DBC1_8814B)
+#define BIT_CLEAR_WLGP_DBC1_8814B(x) ((x) & (~BITS_WLGP_DBC1_8814B))
+#define BIT_GET_WLGP_DBC1_8814B(x) \
+ (((x) >> BIT_SHIFT_WLGP_DBC1_8814B) & BIT_MASK_WLGP_DBC1_8814B)
+#define BIT_SET_WLGP_DBC1_8814B(x, v) \
+ (BIT_CLEAR_WLGP_DBC1_8814B(x) | BIT_WLGP_DBC1_8814B(v))
+
+#define BIT_WLGP_DBC0EN_8814B BIT(7)
+
+#define BIT_SHIFT_WLGP_DBC0_8814B 0
+#define BIT_MASK_WLGP_DBC0_8814B 0xf
+#define BIT_WLGP_DBC0_8814B(x) \
+ (((x) & BIT_MASK_WLGP_DBC0_8814B) << BIT_SHIFT_WLGP_DBC0_8814B)
+#define BITS_WLGP_DBC0_8814B \
+ (BIT_MASK_WLGP_DBC0_8814B << BIT_SHIFT_WLGP_DBC0_8814B)
+#define BIT_CLEAR_WLGP_DBC0_8814B(x) ((x) & (~BITS_WLGP_DBC0_8814B))
+#define BIT_GET_WLGP_DBC0_8814B(x) \
+ (((x) >> BIT_SHIFT_WLGP_DBC0_8814B) & BIT_MASK_WLGP_DBC0_8814B)
+#define BIT_SET_WLGP_DBC0_8814B(x, v) \
+ (BIT_CLEAR_WLGP_DBC0_8814B(x) | BIT_WLGP_DBC0_8814B(v))
+
+/* 2 REG_RPWM2_8814B */
+
+#define BIT_SHIFT_RPWM2_8814B 16
+#define BIT_MASK_RPWM2_8814B 0xffff
+#define BIT_RPWM2_8814B(x) \
+ (((x) & BIT_MASK_RPWM2_8814B) << BIT_SHIFT_RPWM2_8814B)
+#define BITS_RPWM2_8814B (BIT_MASK_RPWM2_8814B << BIT_SHIFT_RPWM2_8814B)
+#define BIT_CLEAR_RPWM2_8814B(x) ((x) & (~BITS_RPWM2_8814B))
+#define BIT_GET_RPWM2_8814B(x) \
+ (((x) >> BIT_SHIFT_RPWM2_8814B) & BIT_MASK_RPWM2_8814B)
+#define BIT_SET_RPWM2_8814B(x, v) \
+ (BIT_CLEAR_RPWM2_8814B(x) | BIT_RPWM2_8814B(v))
+
+/* 2 REG_SYSON_FSM_MON_8814B */
+
+#define BIT_SHIFT_FSM_MON_SEL_8814B 24
+#define BIT_MASK_FSM_MON_SEL_8814B 0x7
+#define BIT_FSM_MON_SEL_8814B(x) \
+ (((x) & BIT_MASK_FSM_MON_SEL_8814B) << BIT_SHIFT_FSM_MON_SEL_8814B)
+#define BITS_FSM_MON_SEL_8814B \
+ (BIT_MASK_FSM_MON_SEL_8814B << BIT_SHIFT_FSM_MON_SEL_8814B)
+#define BIT_CLEAR_FSM_MON_SEL_8814B(x) ((x) & (~BITS_FSM_MON_SEL_8814B))
+#define BIT_GET_FSM_MON_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_FSM_MON_SEL_8814B) & BIT_MASK_FSM_MON_SEL_8814B)
+#define BIT_SET_FSM_MON_SEL_8814B(x, v) \
+ (BIT_CLEAR_FSM_MON_SEL_8814B(x) | BIT_FSM_MON_SEL_8814B(v))
+
+#define BIT_DOP_ELDO_8814B BIT(23)
+#define BIT_FSM_MON_UPD_8814B BIT(15)
+
+#define BIT_SHIFT_FSM_PAR_8814B 0
+#define BIT_MASK_FSM_PAR_8814B 0x7fff
+#define BIT_FSM_PAR_8814B(x) \
+ (((x) & BIT_MASK_FSM_PAR_8814B) << BIT_SHIFT_FSM_PAR_8814B)
+#define BITS_FSM_PAR_8814B (BIT_MASK_FSM_PAR_8814B << BIT_SHIFT_FSM_PAR_8814B)
+#define BIT_CLEAR_FSM_PAR_8814B(x) ((x) & (~BITS_FSM_PAR_8814B))
+#define BIT_GET_FSM_PAR_8814B(x) \
+ (((x) >> BIT_SHIFT_FSM_PAR_8814B) & BIT_MASK_FSM_PAR_8814B)
+#define BIT_SET_FSM_PAR_8814B(x, v) \
+ (BIT_CLEAR_FSM_PAR_8814B(x) | BIT_FSM_PAR_8814B(v))
+
+/* 2 REG_AFE_CTRL6_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_PMC_DBG_CTRL1_8814B */
+#define BIT_BT_INT_EN_8814B BIT(31)
+
+#define BIT_SHIFT_RD_WR_WIFI_BT_INFO_8814B 16
+#define BIT_MASK_RD_WR_WIFI_BT_INFO_8814B 0x7fff
+#define BIT_RD_WR_WIFI_BT_INFO_8814B(x) \
+ (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8814B) \
+ << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8814B)
+#define BITS_RD_WR_WIFI_BT_INFO_8814B \
+ (BIT_MASK_RD_WR_WIFI_BT_INFO_8814B \
+ << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8814B)
+#define BIT_CLEAR_RD_WR_WIFI_BT_INFO_8814B(x) \
+ ((x) & (~BITS_RD_WR_WIFI_BT_INFO_8814B))
+#define BIT_GET_RD_WR_WIFI_BT_INFO_8814B(x) \
+ (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8814B) & \
+ BIT_MASK_RD_WR_WIFI_BT_INFO_8814B)
+#define BIT_SET_RD_WR_WIFI_BT_INFO_8814B(x, v) \
+ (BIT_CLEAR_RD_WR_WIFI_BT_INFO_8814B(x) | \
+ BIT_RD_WR_WIFI_BT_INFO_8814B(v))
+
+#define BIT_PMC_WR_OVF_8814B BIT(8)
+
+#define BIT_SHIFT_WLPMC_ERRINT_8814B 0
+#define BIT_MASK_WLPMC_ERRINT_8814B 0xff
+#define BIT_WLPMC_ERRINT_8814B(x) \
+ (((x) & BIT_MASK_WLPMC_ERRINT_8814B) << BIT_SHIFT_WLPMC_ERRINT_8814B)
+#define BITS_WLPMC_ERRINT_8814B \
+ (BIT_MASK_WLPMC_ERRINT_8814B << BIT_SHIFT_WLPMC_ERRINT_8814B)
+#define BIT_CLEAR_WLPMC_ERRINT_8814B(x) ((x) & (~BITS_WLPMC_ERRINT_8814B))
+#define BIT_GET_WLPMC_ERRINT_8814B(x) \
+ (((x) >> BIT_SHIFT_WLPMC_ERRINT_8814B) & BIT_MASK_WLPMC_ERRINT_8814B)
+#define BIT_SET_WLPMC_ERRINT_8814B(x, v) \
+ (BIT_CLEAR_WLPMC_ERRINT_8814B(x) | BIT_WLPMC_ERRINT_8814B(v))
+
+/* 2 REG_AFE_CTRL7_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_HIMR0_8814B */
+#define BIT_PSTIMER_2_MSK_8814B BIT(31)
+#define BIT_PSTIMER_1_MSK_8814B BIT(30)
+#define BIT_PSTIMER_0_MSK_8814B BIT(29)
+#define BIT_GTINT4_MSK_8814B BIT(28)
+#define BIT_GTINT3_MSK_8814B BIT(27)
+#define BIT_TXBCN0ERR_MSK_8814B BIT(26)
+#define BIT_TXBCN0OK_MSK_8814B BIT(25)
+#define BIT_TSF_BIT32_TOGGLE_MSK_8814B BIT(24)
+#define BIT_TXDMA_START_INT_MSK_8814B BIT(23)
+#define BIT_TXDMA_STOP_INT_MSK_8814B BIT(22)
+#define BIT_HISR7_IND_MSK_8814B BIT(21)
+#define BIT_BCNDMAINT0_MSK_8814B BIT(20)
+#define BIT_HISR6_IND_MSK_8814B BIT(19)
+#define BIT_HISR5_IND_MSK_8814B BIT(18)
+#define BIT_HISR4_IND_MSK_8814B BIT(17)
+#define BIT_BCNDERR0_MSK_8814B BIT(16)
+#define BIT_HSISR_IND_ON_INT_MSK_8814B BIT(15)
+#define BIT_HISR3_IND_MSK_8814B BIT(14)
+#define BIT_HISR2_IND_MSK_8814B BIT(13)
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_HISR1_IND_MSK_8814B BIT(11)
+#define BIT_C2HCMD_MSK_8814B BIT(10)
+#define BIT_CPWM2_MSK_8814B BIT(9)
+#define BIT_CPWM_MSK_8814B BIT(8)
+#define BIT_TXDMAOK_CHANNEL15_MSK_8814B BIT(7)
+#define BIT_TXDMAOK_CHANNEL14_MSK_8814B BIT(6)
+#define BIT_TXDMAOK_CHANNEL3_MSK_8814B BIT(5)
+#define BIT_TXDMAOK_CHANNEL2_MSK_8814B BIT(4)
+#define BIT_TXDMAOK_CHANNEL1_MSK_8814B BIT(3)
+#define BIT_TXDMAOK_CHANNEL0_MSK_8814B BIT(2)
+#define BIT_RDU_MSK_8814B BIT(1)
+#define BIT_RXOK_MSK_8814B BIT(0)
+
+/* 2 REG_HISR0_8814B */
+#define BIT_PSTIMER_2_8814B BIT(31)
+#define BIT_PSTIMER_1_8814B BIT(30)
+#define BIT_PSTIMER_0_8814B BIT(29)
+#define BIT_GTINT4_8814B BIT(28)
+#define BIT_GTINT3_8814B BIT(27)
+#define BIT_TXBCN0ERR_8814B BIT(26)
+#define BIT_TXBCN0OK_8814B BIT(25)
+#define BIT_TSF_BIT32_TOGGLE_8814B BIT(24)
+#define BIT_TXDMA_START_INT_8814B BIT(23)
+#define BIT_TXDMA_STOP_INT_8814B BIT(22)
+#define BIT_HISR7_IND_8814B BIT(21)
+#define BIT_BCNDMAINT0_8814B BIT(20)
+#define BIT_HISR6_IND_8814B BIT(19)
+#define BIT_HISR5_IND_8814B BIT(18)
+#define BIT_HISR4_IND_8814B BIT(17)
+#define BIT_BCNDERR0_8814B BIT(16)
+#define BIT_HSISR_IND_ON_INT_8814B BIT(15)
+#define BIT_HISR3_IND_8814B BIT(14)
+#define BIT_HISR2_IND_8814B BIT(13)
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_HISR1_IND_8814B BIT(11)
+#define BIT_C2HCMD_8814B BIT(10)
+#define BIT_CPWM2_8814B BIT(9)
+#define BIT_CPWM_8814B BIT(8)
+#define BIT_TXDMAOK_CHANNEL15_8814B BIT(7)
+#define BIT_TXDMAOK_CHANNEL14_8814B BIT(6)
+#define BIT_TXDMAOK_CHANNEL3_8814B BIT(5)
+#define BIT_TXDMAOK_CHANNEL2_8814B BIT(4)
+#define BIT_TXDMAOK_CHANNEL1_8814B BIT(3)
+#define BIT_TXDMAOK_CHANNEL0_8814B BIT(2)
+#define BIT_RDU_8814B BIT(1)
+#define BIT_RXOK_8814B BIT(0)
+
+/* 2 REG_HIMR1_8814B */
+#define BIT_PRE_TX_ERR_INT_MSK_8814B BIT(31)
+#define BIT_TXFIFO_TH_INT_8814B BIT(30)
+#define BIT_BTON_STS_UPDATE_MASK_8814B BIT(29)
+#define BIT_BCNDMAINT7__MSK_8814B BIT(27)
+#define BIT_BCNDMAINT6__MSK_8814B BIT(26)
+#define BIT_BCNDMAINT5__MSK_8814B BIT(25)
+#define BIT_BCNDMAINT4__MSK_8814B BIT(24)
+#define BIT_BCNDMAINT3_MSK_8814B BIT(23)
+#define BIT_BCNDMAINT2_MSK_8814B BIT(22)
+#define BIT_BCNDMAINT1_MSK_8814B BIT(21)
+#define BIT_BCNDERR7_MSK_8814B BIT(20)
+#define BIT_BCNDERR6_MSK_8814B BIT(19)
+#define BIT_BCNDERR5_MSK_8814B BIT(18)
+#define BIT_BCNDERR4_MSK_8814B BIT(17)
+#define BIT_BCNDERR3_MSK_8814B BIT(16)
+#define BIT_BCNDERR2_MSK_8814B BIT(15)
+#define BIT_BCNDERR1_MSK_8814B BIT(14)
+#define BIT_ATIMEND__MSK_8814B BIT(12)
+#define BIT_TXERR_MSK_8814B BIT(11)
+#define BIT_RXERR_MSK_8814B BIT(10)
+#define BIT_TXFOVW_MSK_8814B BIT(9)
+#define BIT_FOVW_MSK_8814B BIT(8)
+#define BIT_CPU_MGQ_EARLY_INT_MSK_8814B BIT(6)
+#define BIT_CPU_MGQ_TXDONE_MSK_8814B BIT(5)
+#define BIT_PSTIMER_5_MSK_8814B BIT(4)
+#define BIT_PSTIMER_4_MSK_8814B BIT(3)
+#define BIT_PSTIMER_3_MSK_8814B BIT(2)
+#define BIT_CPUMGQ_TX_TIMER_MSK_8814B BIT(1)
+#define BIT_BB_STOPRX_INT_MSK_8814B BIT(0)
+
+/* 2 REG_HISR1_8814B */
+#define BIT_PRE_TX_ERR_INT_8814B BIT(31)
+#define BIT_TXFIFO_TH_INT_8814B BIT(30)
+#define BIT_BTON_STS_UPDATE_INT_8814B BIT(29)
+#define BIT_BCNDMAINT7_8814B BIT(27)
+#define BIT_BCNDMAINT6_8814B BIT(26)
+#define BIT_BCNDMAINT5_8814B BIT(25)
+#define BIT_BCNDMAINT4_8814B BIT(24)
+#define BIT_BCNDMAINT3_8814B BIT(23)
+#define BIT_BCNDMAINT2_8814B BIT(22)
+#define BIT_BCNDMAINT1_8814B BIT(21)
+#define BIT_BCNDERR7_8814B BIT(20)
+#define BIT_BCNDERR6_8814B BIT(19)
+#define BIT_BCNDERR5_8814B BIT(18)
+#define BIT_BCNDERR4_8814B BIT(17)
+#define BIT_BCNDERR3_8814B BIT(16)
+#define BIT_BCNDERR2_8814B BIT(15)
+#define BIT_BCNDERR1_8814B BIT(14)
+#define BIT_ATIMEND_8814B BIT(12)
+#define BIT_TXERR_INT_8814B BIT(11)
+#define BIT_RXERR_INT_8814B BIT(10)
+#define BIT_TXFOVW_8814B BIT(9)
+#define BIT_FOVW_8814B BIT(8)
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_CPU_MGQ_EARLY_INT_8814B BIT(6)
+#define BIT_CPU_MGQ_TXDONE_8814B BIT(5)
+#define BIT_PSTIMER_5_8814B BIT(4)
+#define BIT_PSTIMER_4_8814B BIT(3)
+#define BIT_PSTIMER_3_8814B BIT(2)
+#define BIT_CPUMGQ_TX_TIMER_8814B BIT(1)
+#define BIT_BB_STOPRX_INT_8814B BIT(0)
+
+/* 2 REG_DBG_PORT_SEL_8814B */
+
+#define BIT_SHIFT_DEBUG_ST_8814B 0
+#define BIT_MASK_DEBUG_ST_8814B 0xffffffffL
+#define BIT_DEBUG_ST_8814B(x) \
+ (((x) & BIT_MASK_DEBUG_ST_8814B) << BIT_SHIFT_DEBUG_ST_8814B)
+#define BITS_DEBUG_ST_8814B \
+ (BIT_MASK_DEBUG_ST_8814B << BIT_SHIFT_DEBUG_ST_8814B)
+#define BIT_CLEAR_DEBUG_ST_8814B(x) ((x) & (~BITS_DEBUG_ST_8814B))
+#define BIT_GET_DEBUG_ST_8814B(x) \
+ (((x) >> BIT_SHIFT_DEBUG_ST_8814B) & BIT_MASK_DEBUG_ST_8814B)
+#define BIT_SET_DEBUG_ST_8814B(x, v) \
+ (BIT_CLEAR_DEBUG_ST_8814B(x) | BIT_DEBUG_ST_8814B(v))
+
+/* 2 REG_PAD_CTRL2_8814B */
+#define BIT_USB3_USB2_TRANSITION_8814B BIT(20)
+
+#define BIT_SHIFT_USB23_SW_MODE_V1_8814B 18
+#define BIT_MASK_USB23_SW_MODE_V1_8814B 0x3
+#define BIT_USB23_SW_MODE_V1_8814B(x) \
+ (((x) & BIT_MASK_USB23_SW_MODE_V1_8814B) \
+ << BIT_SHIFT_USB23_SW_MODE_V1_8814B)
+#define BITS_USB23_SW_MODE_V1_8814B \
+ (BIT_MASK_USB23_SW_MODE_V1_8814B << BIT_SHIFT_USB23_SW_MODE_V1_8814B)
+#define BIT_CLEAR_USB23_SW_MODE_V1_8814B(x) \
+ ((x) & (~BITS_USB23_SW_MODE_V1_8814B))
+#define BIT_GET_USB23_SW_MODE_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_USB23_SW_MODE_V1_8814B) & \
+ BIT_MASK_USB23_SW_MODE_V1_8814B)
+#define BIT_SET_USB23_SW_MODE_V1_8814B(x, v) \
+ (BIT_CLEAR_USB23_SW_MODE_V1_8814B(x) | BIT_USB23_SW_MODE_V1_8814B(v))
+
+#define BIT_NO_PDN_CHIPOFF_V1_8814B BIT(17)
+#define BIT_RSM_EN_V1_8814B BIT(16)
+
+#define BIT_SHIFT_MATCH_CNT_8814B 8
+#define BIT_MASK_MATCH_CNT_8814B 0xff
+#define BIT_MATCH_CNT_8814B(x) \
+ (((x) & BIT_MASK_MATCH_CNT_8814B) << BIT_SHIFT_MATCH_CNT_8814B)
+#define BITS_MATCH_CNT_8814B \
+ (BIT_MASK_MATCH_CNT_8814B << BIT_SHIFT_MATCH_CNT_8814B)
+#define BIT_CLEAR_MATCH_CNT_8814B(x) ((x) & (~BITS_MATCH_CNT_8814B))
+#define BIT_GET_MATCH_CNT_8814B(x) \
+ (((x) >> BIT_SHIFT_MATCH_CNT_8814B) & BIT_MASK_MATCH_CNT_8814B)
+#define BIT_SET_MATCH_CNT_8814B(x, v) \
+ (BIT_CLEAR_MATCH_CNT_8814B(x) | BIT_MATCH_CNT_8814B(v))
+
+#define BIT_LD_B12V_EN_8814B BIT(7)
+#define BIT_EECS_IOSEL_V1_8814B BIT(6)
+#define BIT_EECS_DATA_O_V1_8814B BIT(5)
+#define BIT_EECS_DATA_I_V1_8814B BIT(4)
+#define BIT_EESK_IOSEL_V1_8814B BIT(2)
+#define BIT_EESK_DATA_O_V1_8814B BIT(1)
+#define BIT_EESK_DATA_I_V1_8814B BIT(0)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_PMC_DBG_CTRL2_8814B */
+
+#define BIT_SHIFT_EFUSE_BURN_GNT_8814B 24
+#define BIT_MASK_EFUSE_BURN_GNT_8814B 0xff
+#define BIT_EFUSE_BURN_GNT_8814B(x) \
+ (((x) & BIT_MASK_EFUSE_BURN_GNT_8814B) \
+ << BIT_SHIFT_EFUSE_BURN_GNT_8814B)
+#define BITS_EFUSE_BURN_GNT_8814B \
+ (BIT_MASK_EFUSE_BURN_GNT_8814B << BIT_SHIFT_EFUSE_BURN_GNT_8814B)
+#define BIT_CLEAR_EFUSE_BURN_GNT_8814B(x) ((x) & (~BITS_EFUSE_BURN_GNT_8814B))
+#define BIT_GET_EFUSE_BURN_GNT_8814B(x) \
+ (((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8814B) & \
+ BIT_MASK_EFUSE_BURN_GNT_8814B)
+#define BIT_SET_EFUSE_BURN_GNT_8814B(x, v) \
+ (BIT_CLEAR_EFUSE_BURN_GNT_8814B(x) | BIT_EFUSE_BURN_GNT_8814B(v))
+
+#define BIT_STOP_WL_PMC_8814B BIT(9)
+#define BIT_STOP_SYM_PMC_8814B BIT(8)
+#define BIT_BT_ACCESS_WL_PAGE0_8814B BIT(6)
+#define BIT_REG_RST_WLPMC_8814B BIT(5)
+#define BIT_REG_RST_PD12N_8814B BIT(4)
+#define BIT_SYSON_DIS_WLREG_WRMSK_8814B BIT(3)
+#define BIT_SYSON_DIS_PMCREG_WRMSK_8814B BIT(2)
+
+#define BIT_SHIFT_SYSON_REG_ARB_8814B 0
+#define BIT_MASK_SYSON_REG_ARB_8814B 0x3
+#define BIT_SYSON_REG_ARB_8814B(x) \
+ (((x) & BIT_MASK_SYSON_REG_ARB_8814B) << BIT_SHIFT_SYSON_REG_ARB_8814B)
+#define BITS_SYSON_REG_ARB_8814B \
+ (BIT_MASK_SYSON_REG_ARB_8814B << BIT_SHIFT_SYSON_REG_ARB_8814B)
+#define BIT_CLEAR_SYSON_REG_ARB_8814B(x) ((x) & (~BITS_SYSON_REG_ARB_8814B))
+#define BIT_GET_SYSON_REG_ARB_8814B(x) \
+ (((x) >> BIT_SHIFT_SYSON_REG_ARB_8814B) & BIT_MASK_SYSON_REG_ARB_8814B)
+#define BIT_SET_SYSON_REG_ARB_8814B(x, v) \
+ (BIT_CLEAR_SYSON_REG_ARB_8814B(x) | BIT_SYSON_REG_ARB_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_MEM_CTRL_8814B */
+#define BIT_UMEM_RME_8814B BIT(31)
+
+#define BIT_SHIFT_BT_SPRAM_8814B 28
+#define BIT_MASK_BT_SPRAM_8814B 0x3
+#define BIT_BT_SPRAM_8814B(x) \
+ (((x) & BIT_MASK_BT_SPRAM_8814B) << BIT_SHIFT_BT_SPRAM_8814B)
+#define BITS_BT_SPRAM_8814B \
+ (BIT_MASK_BT_SPRAM_8814B << BIT_SHIFT_BT_SPRAM_8814B)
+#define BIT_CLEAR_BT_SPRAM_8814B(x) ((x) & (~BITS_BT_SPRAM_8814B))
+#define BIT_GET_BT_SPRAM_8814B(x) \
+ (((x) >> BIT_SHIFT_BT_SPRAM_8814B) & BIT_MASK_BT_SPRAM_8814B)
+#define BIT_SET_BT_SPRAM_8814B(x, v) \
+ (BIT_CLEAR_BT_SPRAM_8814B(x) | BIT_BT_SPRAM_8814B(v))
+
+#define BIT_SHIFT_BT_ROM_8814B 24
+#define BIT_MASK_BT_ROM_8814B 0xf
+#define BIT_BT_ROM_8814B(x) \
+ (((x) & BIT_MASK_BT_ROM_8814B) << BIT_SHIFT_BT_ROM_8814B)
+#define BITS_BT_ROM_8814B (BIT_MASK_BT_ROM_8814B << BIT_SHIFT_BT_ROM_8814B)
+#define BIT_CLEAR_BT_ROM_8814B(x) ((x) & (~BITS_BT_ROM_8814B))
+#define BIT_GET_BT_ROM_8814B(x) \
+ (((x) >> BIT_SHIFT_BT_ROM_8814B) & BIT_MASK_BT_ROM_8814B)
+#define BIT_SET_BT_ROM_8814B(x, v) \
+ (BIT_CLEAR_BT_ROM_8814B(x) | BIT_BT_ROM_8814B(v))
+
+#define BIT_SHIFT_PCI_DPRAM_8814B 10
+#define BIT_MASK_PCI_DPRAM_8814B 0x3
+#define BIT_PCI_DPRAM_8814B(x) \
+ (((x) & BIT_MASK_PCI_DPRAM_8814B) << BIT_SHIFT_PCI_DPRAM_8814B)
+#define BITS_PCI_DPRAM_8814B \
+ (BIT_MASK_PCI_DPRAM_8814B << BIT_SHIFT_PCI_DPRAM_8814B)
+#define BIT_CLEAR_PCI_DPRAM_8814B(x) ((x) & (~BITS_PCI_DPRAM_8814B))
+#define BIT_GET_PCI_DPRAM_8814B(x) \
+ (((x) >> BIT_SHIFT_PCI_DPRAM_8814B) & BIT_MASK_PCI_DPRAM_8814B)
+#define BIT_SET_PCI_DPRAM_8814B(x, v) \
+ (BIT_CLEAR_PCI_DPRAM_8814B(x) | BIT_PCI_DPRAM_8814B(v))
+
+#define BIT_SHIFT_PCI_SPRAM_8814B 8
+#define BIT_MASK_PCI_SPRAM_8814B 0x3
+#define BIT_PCI_SPRAM_8814B(x) \
+ (((x) & BIT_MASK_PCI_SPRAM_8814B) << BIT_SHIFT_PCI_SPRAM_8814B)
+#define BITS_PCI_SPRAM_8814B \
+ (BIT_MASK_PCI_SPRAM_8814B << BIT_SHIFT_PCI_SPRAM_8814B)
+#define BIT_CLEAR_PCI_SPRAM_8814B(x) ((x) & (~BITS_PCI_SPRAM_8814B))
+#define BIT_GET_PCI_SPRAM_8814B(x) \
+ (((x) >> BIT_SHIFT_PCI_SPRAM_8814B) & BIT_MASK_PCI_SPRAM_8814B)
+#define BIT_SET_PCI_SPRAM_8814B(x, v) \
+ (BIT_CLEAR_PCI_SPRAM_8814B(x) | BIT_PCI_SPRAM_8814B(v))
+
+#define BIT_SHIFT_USB_SPRAM_8814B 6
+#define BIT_MASK_USB_SPRAM_8814B 0x3
+#define BIT_USB_SPRAM_8814B(x) \
+ (((x) & BIT_MASK_USB_SPRAM_8814B) << BIT_SHIFT_USB_SPRAM_8814B)
+#define BITS_USB_SPRAM_8814B \
+ (BIT_MASK_USB_SPRAM_8814B << BIT_SHIFT_USB_SPRAM_8814B)
+#define BIT_CLEAR_USB_SPRAM_8814B(x) ((x) & (~BITS_USB_SPRAM_8814B))
+#define BIT_GET_USB_SPRAM_8814B(x) \
+ (((x) >> BIT_SHIFT_USB_SPRAM_8814B) & BIT_MASK_USB_SPRAM_8814B)
+#define BIT_SET_USB_SPRAM_8814B(x, v) \
+ (BIT_CLEAR_USB_SPRAM_8814B(x) | BIT_USB_SPRAM_8814B(v))
+
+#define BIT_SHIFT_USB_SPRF_8814B 4
+#define BIT_MASK_USB_SPRF_8814B 0x3
+#define BIT_USB_SPRF_8814B(x) \
+ (((x) & BIT_MASK_USB_SPRF_8814B) << BIT_SHIFT_USB_SPRF_8814B)
+#define BITS_USB_SPRF_8814B \
+ (BIT_MASK_USB_SPRF_8814B << BIT_SHIFT_USB_SPRF_8814B)
+#define BIT_CLEAR_USB_SPRF_8814B(x) ((x) & (~BITS_USB_SPRF_8814B))
+#define BIT_GET_USB_SPRF_8814B(x) \
+ (((x) >> BIT_SHIFT_USB_SPRF_8814B) & BIT_MASK_USB_SPRF_8814B)
+#define BIT_SET_USB_SPRF_8814B(x, v) \
+ (BIT_CLEAR_USB_SPRF_8814B(x) | BIT_USB_SPRF_8814B(v))
+
+#define BIT_SHIFT_MCU_ROM_8814B 0
+#define BIT_MASK_MCU_ROM_8814B 0xf
+#define BIT_MCU_ROM_8814B(x) \
+ (((x) & BIT_MASK_MCU_ROM_8814B) << BIT_SHIFT_MCU_ROM_8814B)
+#define BITS_MCU_ROM_8814B (BIT_MASK_MCU_ROM_8814B << BIT_SHIFT_MCU_ROM_8814B)
+#define BIT_CLEAR_MCU_ROM_8814B(x) ((x) & (~BITS_MCU_ROM_8814B))
+#define BIT_GET_MCU_ROM_8814B(x) \
+ (((x) >> BIT_SHIFT_MCU_ROM_8814B) & BIT_MASK_MCU_ROM_8814B)
+#define BIT_SET_MCU_ROM_8814B(x, v) \
+ (BIT_CLEAR_MCU_ROM_8814B(x) | BIT_MCU_ROM_8814B(v))
+
+/* 2 REG_SYN_RFC_CTRL_8814B */
+
+#define BIT_SHIFT_SYN_RF1_CTRL_8814B 8
+#define BIT_MASK_SYN_RF1_CTRL_8814B 0xff
+#define BIT_SYN_RF1_CTRL_8814B(x) \
+ (((x) & BIT_MASK_SYN_RF1_CTRL_8814B) << BIT_SHIFT_SYN_RF1_CTRL_8814B)
+#define BITS_SYN_RF1_CTRL_8814B \
+ (BIT_MASK_SYN_RF1_CTRL_8814B << BIT_SHIFT_SYN_RF1_CTRL_8814B)
+#define BIT_CLEAR_SYN_RF1_CTRL_8814B(x) ((x) & (~BITS_SYN_RF1_CTRL_8814B))
+#define BIT_GET_SYN_RF1_CTRL_8814B(x) \
+ (((x) >> BIT_SHIFT_SYN_RF1_CTRL_8814B) & BIT_MASK_SYN_RF1_CTRL_8814B)
+#define BIT_SET_SYN_RF1_CTRL_8814B(x, v) \
+ (BIT_CLEAR_SYN_RF1_CTRL_8814B(x) | BIT_SYN_RF1_CTRL_8814B(v))
+
+#define BIT_SHIFT_SYN_RF0_CTRL_8814B 0
+#define BIT_MASK_SYN_RF0_CTRL_8814B 0xff
+#define BIT_SYN_RF0_CTRL_8814B(x) \
+ (((x) & BIT_MASK_SYN_RF0_CTRL_8814B) << BIT_SHIFT_SYN_RF0_CTRL_8814B)
+#define BITS_SYN_RF0_CTRL_8814B \
+ (BIT_MASK_SYN_RF0_CTRL_8814B << BIT_SHIFT_SYN_RF0_CTRL_8814B)
+#define BIT_CLEAR_SYN_RF0_CTRL_8814B(x) ((x) & (~BITS_SYN_RF0_CTRL_8814B))
+#define BIT_GET_SYN_RF0_CTRL_8814B(x) \
+ (((x) >> BIT_SHIFT_SYN_RF0_CTRL_8814B) & BIT_MASK_SYN_RF0_CTRL_8814B)
+#define BIT_SET_SYN_RF0_CTRL_8814B(x, v) \
+ (BIT_CLEAR_SYN_RF0_CTRL_8814B(x) | BIT_SYN_RF0_CTRL_8814B(v))
+
+/* 2 REG_USB_SIE_INTF_8814B */
+#define BIT_RD_SEL_8814B BIT(31)
+#define BIT_USB_SIE_INTF_WE_V1_8814B BIT(30)
+#define BIT_USB_SIE_INTF_BYIOREG_V1_8814B BIT(29)
+#define BIT_USB_SIE_SELECT_8814B BIT(28)
+
+#define BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8814B 16
+#define BIT_MASK_USB_SIE_INTF_ADDR_V1_8814B 0x1ff
+#define BIT_USB_SIE_INTF_ADDR_V1_8814B(x) \
+ (((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8814B) \
+ << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8814B)
+#define BITS_USB_SIE_INTF_ADDR_V1_8814B \
+ (BIT_MASK_USB_SIE_INTF_ADDR_V1_8814B \
+ << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8814B)
+#define BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8814B(x) \
+ ((x) & (~BITS_USB_SIE_INTF_ADDR_V1_8814B))
+#define BIT_GET_USB_SIE_INTF_ADDR_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8814B) & \
+ BIT_MASK_USB_SIE_INTF_ADDR_V1_8814B)
+#define BIT_SET_USB_SIE_INTF_ADDR_V1_8814B(x, v) \
+ (BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8814B(x) | \
+ BIT_USB_SIE_INTF_ADDR_V1_8814B(v))
+
+#define BIT_SHIFT_USB_SIE_INTF_RD_8814B 8
+#define BIT_MASK_USB_SIE_INTF_RD_8814B 0xff
+#define BIT_USB_SIE_INTF_RD_8814B(x) \
+ (((x) & BIT_MASK_USB_SIE_INTF_RD_8814B) \
+ << BIT_SHIFT_USB_SIE_INTF_RD_8814B)
+#define BITS_USB_SIE_INTF_RD_8814B \
+ (BIT_MASK_USB_SIE_INTF_RD_8814B << BIT_SHIFT_USB_SIE_INTF_RD_8814B)
+#define BIT_CLEAR_USB_SIE_INTF_RD_8814B(x) ((x) & (~BITS_USB_SIE_INTF_RD_8814B))
+#define BIT_GET_USB_SIE_INTF_RD_8814B(x) \
+ (((x) >> BIT_SHIFT_USB_SIE_INTF_RD_8814B) & \
+ BIT_MASK_USB_SIE_INTF_RD_8814B)
+#define BIT_SET_USB_SIE_INTF_RD_8814B(x, v) \
+ (BIT_CLEAR_USB_SIE_INTF_RD_8814B(x) | BIT_USB_SIE_INTF_RD_8814B(v))
+
+#define BIT_SHIFT_USB_SIE_INTF_WD_8814B 0
+#define BIT_MASK_USB_SIE_INTF_WD_8814B 0xff
+#define BIT_USB_SIE_INTF_WD_8814B(x) \
+ (((x) & BIT_MASK_USB_SIE_INTF_WD_8814B) \
+ << BIT_SHIFT_USB_SIE_INTF_WD_8814B)
+#define BITS_USB_SIE_INTF_WD_8814B \
+ (BIT_MASK_USB_SIE_INTF_WD_8814B << BIT_SHIFT_USB_SIE_INTF_WD_8814B)
+#define BIT_CLEAR_USB_SIE_INTF_WD_8814B(x) ((x) & (~BITS_USB_SIE_INTF_WD_8814B))
+#define BIT_GET_USB_SIE_INTF_WD_8814B(x) \
+ (((x) >> BIT_SHIFT_USB_SIE_INTF_WD_8814B) & \
+ BIT_MASK_USB_SIE_INTF_WD_8814B)
+#define BIT_SET_USB_SIE_INTF_WD_8814B(x, v) \
+ (BIT_CLEAR_USB_SIE_INTF_WD_8814B(x) | BIT_USB_SIE_INTF_WD_8814B(v))
+
+/* 2 REG_PCIE_MIO_INTF_8814B */
+
+#define BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8814B 16
+#define BIT_MASK_PCIE_MIO_ADDR_PAGE_8814B 0x3
+#define BIT_PCIE_MIO_ADDR_PAGE_8814B(x) \
+ (((x) & BIT_MASK_PCIE_MIO_ADDR_PAGE_8814B) \
+ << BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8814B)
+#define BITS_PCIE_MIO_ADDR_PAGE_8814B \
+ (BIT_MASK_PCIE_MIO_ADDR_PAGE_8814B \
+ << BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8814B)
+#define BIT_CLEAR_PCIE_MIO_ADDR_PAGE_8814B(x) \
+ ((x) & (~BITS_PCIE_MIO_ADDR_PAGE_8814B))
+#define BIT_GET_PCIE_MIO_ADDR_PAGE_8814B(x) \
+ (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8814B) & \
+ BIT_MASK_PCIE_MIO_ADDR_PAGE_8814B)
+#define BIT_SET_PCIE_MIO_ADDR_PAGE_8814B(x, v) \
+ (BIT_CLEAR_PCIE_MIO_ADDR_PAGE_8814B(x) | \
+ BIT_PCIE_MIO_ADDR_PAGE_8814B(v))
+
+#define BIT_PCIE_MIO_BYIOREG_8814B BIT(13)
+#define BIT_PCIE_MIO_RE_8814B BIT(12)
+
+#define BIT_SHIFT_PCIE_MIO_WE_8814B 8
+#define BIT_MASK_PCIE_MIO_WE_8814B 0xf
+#define BIT_PCIE_MIO_WE_8814B(x) \
+ (((x) & BIT_MASK_PCIE_MIO_WE_8814B) << BIT_SHIFT_PCIE_MIO_WE_8814B)
+#define BITS_PCIE_MIO_WE_8814B \
+ (BIT_MASK_PCIE_MIO_WE_8814B << BIT_SHIFT_PCIE_MIO_WE_8814B)
+#define BIT_CLEAR_PCIE_MIO_WE_8814B(x) ((x) & (~BITS_PCIE_MIO_WE_8814B))
+#define BIT_GET_PCIE_MIO_WE_8814B(x) \
+ (((x) >> BIT_SHIFT_PCIE_MIO_WE_8814B) & BIT_MASK_PCIE_MIO_WE_8814B)
+#define BIT_SET_PCIE_MIO_WE_8814B(x, v) \
+ (BIT_CLEAR_PCIE_MIO_WE_8814B(x) | BIT_PCIE_MIO_WE_8814B(v))
+
+#define BIT_SHIFT_PCIE_MIO_ADDR_8814B 0
+#define BIT_MASK_PCIE_MIO_ADDR_8814B 0xff
+#define BIT_PCIE_MIO_ADDR_8814B(x) \
+ (((x) & BIT_MASK_PCIE_MIO_ADDR_8814B) << BIT_SHIFT_PCIE_MIO_ADDR_8814B)
+#define BITS_PCIE_MIO_ADDR_8814B \
+ (BIT_MASK_PCIE_MIO_ADDR_8814B << BIT_SHIFT_PCIE_MIO_ADDR_8814B)
+#define BIT_CLEAR_PCIE_MIO_ADDR_8814B(x) ((x) & (~BITS_PCIE_MIO_ADDR_8814B))
+#define BIT_GET_PCIE_MIO_ADDR_8814B(x) \
+ (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8814B) & BIT_MASK_PCIE_MIO_ADDR_8814B)
+#define BIT_SET_PCIE_MIO_ADDR_8814B(x, v) \
+ (BIT_CLEAR_PCIE_MIO_ADDR_8814B(x) | BIT_PCIE_MIO_ADDR_8814B(v))
+
+/* 2 REG_PCIE_MIO_INTD_8814B */
+
+#define BIT_SHIFT_PCIE_MIO_DATA_8814B 0
+#define BIT_MASK_PCIE_MIO_DATA_8814B 0xffffffffL
+#define BIT_PCIE_MIO_DATA_8814B(x) \
+ (((x) & BIT_MASK_PCIE_MIO_DATA_8814B) << BIT_SHIFT_PCIE_MIO_DATA_8814B)
+#define BITS_PCIE_MIO_DATA_8814B \
+ (BIT_MASK_PCIE_MIO_DATA_8814B << BIT_SHIFT_PCIE_MIO_DATA_8814B)
+#define BIT_CLEAR_PCIE_MIO_DATA_8814B(x) ((x) & (~BITS_PCIE_MIO_DATA_8814B))
+#define BIT_GET_PCIE_MIO_DATA_8814B(x) \
+ (((x) >> BIT_SHIFT_PCIE_MIO_DATA_8814B) & BIT_MASK_PCIE_MIO_DATA_8814B)
+#define BIT_SET_PCIE_MIO_DATA_8814B(x, v) \
+ (BIT_CLEAR_PCIE_MIO_DATA_8814B(x) | BIT_PCIE_MIO_DATA_8814B(v))
+
+/* 2 REG_WLRF1_8814B */
+
+#define BIT_SHIFT_WLRF1_CTRL_8814B 24
+#define BIT_MASK_WLRF1_CTRL_8814B 0xff
+#define BIT_WLRF1_CTRL_8814B(x) \
+ (((x) & BIT_MASK_WLRF1_CTRL_8814B) << BIT_SHIFT_WLRF1_CTRL_8814B)
+#define BITS_WLRF1_CTRL_8814B \
+ (BIT_MASK_WLRF1_CTRL_8814B << BIT_SHIFT_WLRF1_CTRL_8814B)
+#define BIT_CLEAR_WLRF1_CTRL_8814B(x) ((x) & (~BITS_WLRF1_CTRL_8814B))
+#define BIT_GET_WLRF1_CTRL_8814B(x) \
+ (((x) >> BIT_SHIFT_WLRF1_CTRL_8814B) & BIT_MASK_WLRF1_CTRL_8814B)
+#define BIT_SET_WLRF1_CTRL_8814B(x, v) \
+ (BIT_CLEAR_WLRF1_CTRL_8814B(x) | BIT_WLRF1_CTRL_8814B(v))
+
+#define BIT_SHIFT_WLRF2_CTRL_8814B 16
+#define BIT_MASK_WLRF2_CTRL_8814B 0xff
+#define BIT_WLRF2_CTRL_8814B(x) \
+ (((x) & BIT_MASK_WLRF2_CTRL_8814B) << BIT_SHIFT_WLRF2_CTRL_8814B)
+#define BITS_WLRF2_CTRL_8814B \
+ (BIT_MASK_WLRF2_CTRL_8814B << BIT_SHIFT_WLRF2_CTRL_8814B)
+#define BIT_CLEAR_WLRF2_CTRL_8814B(x) ((x) & (~BITS_WLRF2_CTRL_8814B))
+#define BIT_GET_WLRF2_CTRL_8814B(x) \
+ (((x) >> BIT_SHIFT_WLRF2_CTRL_8814B) & BIT_MASK_WLRF2_CTRL_8814B)
+#define BIT_SET_WLRF2_CTRL_8814B(x, v) \
+ (BIT_CLEAR_WLRF2_CTRL_8814B(x) | BIT_WLRF2_CTRL_8814B(v))
+
+#define BIT_SHIFT_WLRF3_CTRL_8814B 8
+#define BIT_MASK_WLRF3_CTRL_8814B 0xff
+#define BIT_WLRF3_CTRL_8814B(x) \
+ (((x) & BIT_MASK_WLRF3_CTRL_8814B) << BIT_SHIFT_WLRF3_CTRL_8814B)
+#define BITS_WLRF3_CTRL_8814B \
+ (BIT_MASK_WLRF3_CTRL_8814B << BIT_SHIFT_WLRF3_CTRL_8814B)
+#define BIT_CLEAR_WLRF3_CTRL_8814B(x) ((x) & (~BITS_WLRF3_CTRL_8814B))
+#define BIT_GET_WLRF3_CTRL_8814B(x) \
+ (((x) >> BIT_SHIFT_WLRF3_CTRL_8814B) & BIT_MASK_WLRF3_CTRL_8814B)
+#define BIT_SET_WLRF3_CTRL_8814B(x, v) \
+ (BIT_CLEAR_WLRF3_CTRL_8814B(x) | BIT_WLRF3_CTRL_8814B(v))
+
+/* 2 REG_SYS_CFG1_8814B */
+
+#define BIT_SHIFT_TRP_ICFG_8814B 28
+#define BIT_MASK_TRP_ICFG_8814B 0xf
+#define BIT_TRP_ICFG_8814B(x) \
+ (((x) & BIT_MASK_TRP_ICFG_8814B) << BIT_SHIFT_TRP_ICFG_8814B)
+#define BITS_TRP_ICFG_8814B \
+ (BIT_MASK_TRP_ICFG_8814B << BIT_SHIFT_TRP_ICFG_8814B)
+#define BIT_CLEAR_TRP_ICFG_8814B(x) ((x) & (~BITS_TRP_ICFG_8814B))
+#define BIT_GET_TRP_ICFG_8814B(x) \
+ (((x) >> BIT_SHIFT_TRP_ICFG_8814B) & BIT_MASK_TRP_ICFG_8814B)
+#define BIT_SET_TRP_ICFG_8814B(x, v) \
+ (BIT_CLEAR_TRP_ICFG_8814B(x) | BIT_TRP_ICFG_8814B(v))
+
+#define BIT_RF_TYPE_ID_8814B BIT(27)
+#define BIT_BD_HCI_SEL_8814B BIT(26)
+#define BIT_BD_PKG_SEL_8814B BIT(25)
+#define BIT_SPSLDO_SEL_8814B BIT(24)
+#define BIT_RTL_ID_8814B BIT(23)
+#define BIT_PAD_HWPD_IDN_8814B BIT(22)
+#define BIT_TESTMODE_8814B BIT(20)
+
+#define BIT_SHIFT_VENDOR_ID_8814B 16
+#define BIT_MASK_VENDOR_ID_8814B 0xf
+#define BIT_VENDOR_ID_8814B(x) \
+ (((x) & BIT_MASK_VENDOR_ID_8814B) << BIT_SHIFT_VENDOR_ID_8814B)
+#define BITS_VENDOR_ID_8814B \
+ (BIT_MASK_VENDOR_ID_8814B << BIT_SHIFT_VENDOR_ID_8814B)
+#define BIT_CLEAR_VENDOR_ID_8814B(x) ((x) & (~BITS_VENDOR_ID_8814B))
+#define BIT_GET_VENDOR_ID_8814B(x) \
+ (((x) >> BIT_SHIFT_VENDOR_ID_8814B) & BIT_MASK_VENDOR_ID_8814B)
+#define BIT_SET_VENDOR_ID_8814B(x, v) \
+ (BIT_CLEAR_VENDOR_ID_8814B(x) | BIT_VENDOR_ID_8814B(v))
+
+#define BIT_SHIFT_CHIP_VER_8814B 12
+#define BIT_MASK_CHIP_VER_8814B 0xf
+#define BIT_CHIP_VER_8814B(x) \
+ (((x) & BIT_MASK_CHIP_VER_8814B) << BIT_SHIFT_CHIP_VER_8814B)
+#define BITS_CHIP_VER_8814B \
+ (BIT_MASK_CHIP_VER_8814B << BIT_SHIFT_CHIP_VER_8814B)
+#define BIT_CLEAR_CHIP_VER_8814B(x) ((x) & (~BITS_CHIP_VER_8814B))
+#define BIT_GET_CHIP_VER_8814B(x) \
+ (((x) >> BIT_SHIFT_CHIP_VER_8814B) & BIT_MASK_CHIP_VER_8814B)
+#define BIT_SET_CHIP_VER_8814B(x, v) \
+ (BIT_CLEAR_CHIP_VER_8814B(x) | BIT_CHIP_VER_8814B(v))
+
+#define BIT_BD_MAC3_8814B BIT(11)
+#define BIT_BD_MAC1_8814B BIT(10)
+#define BIT_BD_MAC2_8814B BIT(9)
+#define BIT_SIC_IDLE_8814B BIT(8)
+#define BIT_SW_OFFLOAD_EN_8814B BIT(7)
+#define BIT_OCP_SHUTDN_8814B BIT(6)
+#define BIT_V15_VLD_8814B BIT(5)
+#define BIT_PCIRSTB_8814B BIT(4)
+#define BIT_PCLK_VLD_8814B BIT(3)
+#define BIT_UCLK_VLD_8814B BIT(2)
+#define BIT_ACLK_VLD_8814B BIT(1)
+#define BIT_XCLK_VLD_8814B BIT(0)
+
+/* 2 REG_SYS_STATUS1_8814B */
+
+#define BIT_SHIFT_RF_RL_ID_8814B 28
+#define BIT_MASK_RF_RL_ID_8814B 0xf
+#define BIT_RF_RL_ID_8814B(x) \
+ (((x) & BIT_MASK_RF_RL_ID_8814B) << BIT_SHIFT_RF_RL_ID_8814B)
+#define BITS_RF_RL_ID_8814B \
+ (BIT_MASK_RF_RL_ID_8814B << BIT_SHIFT_RF_RL_ID_8814B)
+#define BIT_CLEAR_RF_RL_ID_8814B(x) ((x) & (~BITS_RF_RL_ID_8814B))
+#define BIT_GET_RF_RL_ID_8814B(x) \
+ (((x) >> BIT_SHIFT_RF_RL_ID_8814B) & BIT_MASK_RF_RL_ID_8814B)
+#define BIT_SET_RF_RL_ID_8814B(x, v) \
+ (BIT_CLEAR_RF_RL_ID_8814B(x) | BIT_RF_RL_ID_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_XTAL_SEL_8814B 25
+#define BIT_MASK_XTAL_SEL_8814B 0x3
+#define BIT_XTAL_SEL_8814B(x) \
+ (((x) & BIT_MASK_XTAL_SEL_8814B) << BIT_SHIFT_XTAL_SEL_8814B)
+#define BITS_XTAL_SEL_8814B \
+ (BIT_MASK_XTAL_SEL_8814B << BIT_SHIFT_XTAL_SEL_8814B)
+#define BIT_CLEAR_XTAL_SEL_8814B(x) ((x) & (~BITS_XTAL_SEL_8814B))
+#define BIT_GET_XTAL_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_XTAL_SEL_8814B) & BIT_MASK_XTAL_SEL_8814B)
+#define BIT_SET_XTAL_SEL_8814B(x, v) \
+ (BIT_CLEAR_XTAL_SEL_8814B(x) | BIT_XTAL_SEL_8814B(v))
+
+#define BIT_HPHY_ICFG_8814B BIT(19)
+
+#define BIT_SHIFT_SEL_0XC0_8814B 16
+#define BIT_MASK_SEL_0XC0_8814B 0x3
+#define BIT_SEL_0XC0_8814B(x) \
+ (((x) & BIT_MASK_SEL_0XC0_8814B) << BIT_SHIFT_SEL_0XC0_8814B)
+#define BITS_SEL_0XC0_8814B \
+ (BIT_MASK_SEL_0XC0_8814B << BIT_SHIFT_SEL_0XC0_8814B)
+#define BIT_CLEAR_SEL_0XC0_8814B(x) ((x) & (~BITS_SEL_0XC0_8814B))
+#define BIT_GET_SEL_0XC0_8814B(x) \
+ (((x) >> BIT_SHIFT_SEL_0XC0_8814B) & BIT_MASK_SEL_0XC0_8814B)
+#define BIT_SET_SEL_0XC0_8814B(x, v) \
+ (BIT_CLEAR_SEL_0XC0_8814B(x) | BIT_SEL_0XC0_8814B(v))
+
+#define BIT_SHIFT_HCI_SEL_V4_8814B 12
+#define BIT_MASK_HCI_SEL_V4_8814B 0x3
+#define BIT_HCI_SEL_V4_8814B(x) \
+ (((x) & BIT_MASK_HCI_SEL_V4_8814B) << BIT_SHIFT_HCI_SEL_V4_8814B)
+#define BITS_HCI_SEL_V4_8814B \
+ (BIT_MASK_HCI_SEL_V4_8814B << BIT_SHIFT_HCI_SEL_V4_8814B)
+#define BIT_CLEAR_HCI_SEL_V4_8814B(x) ((x) & (~BITS_HCI_SEL_V4_8814B))
+#define BIT_GET_HCI_SEL_V4_8814B(x) \
+ (((x) >> BIT_SHIFT_HCI_SEL_V4_8814B) & BIT_MASK_HCI_SEL_V4_8814B)
+#define BIT_SET_HCI_SEL_V4_8814B(x, v) \
+ (BIT_CLEAR_HCI_SEL_V4_8814B(x) | BIT_HCI_SEL_V4_8814B(v))
+
+#define BIT_USB_OPERATION_MODE_8814B BIT(10)
+#define BIT_BT_PDN_8814B BIT(9)
+#define BIT_AUTO_WLPON_8814B BIT(8)
+#define BIT_WL_MODE_8814B BIT(7)
+#define BIT_PKG_SEL_HCI_8814B BIT(6)
+
+#define BIT_SHIFT_PAD_HCI_SEL_V2_8814B 3
+#define BIT_MASK_PAD_HCI_SEL_V2_8814B 0x3
+#define BIT_PAD_HCI_SEL_V2_8814B(x) \
+ (((x) & BIT_MASK_PAD_HCI_SEL_V2_8814B) \
+ << BIT_SHIFT_PAD_HCI_SEL_V2_8814B)
+#define BITS_PAD_HCI_SEL_V2_8814B \
+ (BIT_MASK_PAD_HCI_SEL_V2_8814B << BIT_SHIFT_PAD_HCI_SEL_V2_8814B)
+#define BIT_CLEAR_PAD_HCI_SEL_V2_8814B(x) ((x) & (~BITS_PAD_HCI_SEL_V2_8814B))
+#define BIT_GET_PAD_HCI_SEL_V2_8814B(x) \
+ (((x) >> BIT_SHIFT_PAD_HCI_SEL_V2_8814B) & \
+ BIT_MASK_PAD_HCI_SEL_V2_8814B)
+#define BIT_SET_PAD_HCI_SEL_V2_8814B(x, v) \
+ (BIT_CLEAR_PAD_HCI_SEL_V2_8814B(x) | BIT_PAD_HCI_SEL_V2_8814B(v))
+
+#define BIT_SHIFT_EFS_HCI_SEL_8814B 0
+#define BIT_MASK_EFS_HCI_SEL_8814B 0x3
+#define BIT_EFS_HCI_SEL_8814B(x) \
+ (((x) & BIT_MASK_EFS_HCI_SEL_8814B) << BIT_SHIFT_EFS_HCI_SEL_8814B)
+#define BITS_EFS_HCI_SEL_8814B \
+ (BIT_MASK_EFS_HCI_SEL_8814B << BIT_SHIFT_EFS_HCI_SEL_8814B)
+#define BIT_CLEAR_EFS_HCI_SEL_8814B(x) ((x) & (~BITS_EFS_HCI_SEL_8814B))
+#define BIT_GET_EFS_HCI_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_EFS_HCI_SEL_8814B) & BIT_MASK_EFS_HCI_SEL_8814B)
+#define BIT_SET_EFS_HCI_SEL_8814B(x, v) \
+ (BIT_CLEAR_EFS_HCI_SEL_8814B(x) | BIT_EFS_HCI_SEL_8814B(v))
+
+/* 2 REG_SYS_STATUS2_8814B */
+#define BIT_SIO_ALDN_8814B BIT(19)
+#define BIT_USB_ALDN_8814B BIT(18)
+#define BIT_PCI_ALDN_8814B BIT(17)
+#define BIT_SYS_ALDN_8814B BIT(16)
+
+#define BIT_SHIFT_EPVID1_8814B 8
+#define BIT_MASK_EPVID1_8814B 0xff
+#define BIT_EPVID1_8814B(x) \
+ (((x) & BIT_MASK_EPVID1_8814B) << BIT_SHIFT_EPVID1_8814B)
+#define BITS_EPVID1_8814B (BIT_MASK_EPVID1_8814B << BIT_SHIFT_EPVID1_8814B)
+#define BIT_CLEAR_EPVID1_8814B(x) ((x) & (~BITS_EPVID1_8814B))
+#define BIT_GET_EPVID1_8814B(x) \
+ (((x) >> BIT_SHIFT_EPVID1_8814B) & BIT_MASK_EPVID1_8814B)
+#define BIT_SET_EPVID1_8814B(x, v) \
+ (BIT_CLEAR_EPVID1_8814B(x) | BIT_EPVID1_8814B(v))
+
+#define BIT_SHIFT_EPVID0_8814B 0
+#define BIT_MASK_EPVID0_8814B 0xff
+#define BIT_EPVID0_8814B(x) \
+ (((x) & BIT_MASK_EPVID0_8814B) << BIT_SHIFT_EPVID0_8814B)
+#define BITS_EPVID0_8814B (BIT_MASK_EPVID0_8814B << BIT_SHIFT_EPVID0_8814B)
+#define BIT_CLEAR_EPVID0_8814B(x) ((x) & (~BITS_EPVID0_8814B))
+#define BIT_GET_EPVID0_8814B(x) \
+ (((x) >> BIT_SHIFT_EPVID0_8814B) & BIT_MASK_EPVID0_8814B)
+#define BIT_SET_EPVID0_8814B(x, v) \
+ (BIT_CLEAR_EPVID0_8814B(x) | BIT_EPVID0_8814B(v))
+
+/* 2 REG_SYS_CFG2_8814B */
+#define BIT_USB2_SEL_8814B BIT(31)
+#define BIT_U3PHY_RST_V1_8814B BIT(30)
+#define BIT_U3_TERM_DETECT_8814B BIT(29)
+
+#define BIT_SHIFT_HW_ID_8814B 0
+#define BIT_MASK_HW_ID_8814B 0xff
+#define BIT_HW_ID_8814B(x) \
+ (((x) & BIT_MASK_HW_ID_8814B) << BIT_SHIFT_HW_ID_8814B)
+#define BITS_HW_ID_8814B (BIT_MASK_HW_ID_8814B << BIT_SHIFT_HW_ID_8814B)
+#define BIT_CLEAR_HW_ID_8814B(x) ((x) & (~BITS_HW_ID_8814B))
+#define BIT_GET_HW_ID_8814B(x) \
+ (((x) >> BIT_SHIFT_HW_ID_8814B) & BIT_MASK_HW_ID_8814B)
+#define BIT_SET_HW_ID_8814B(x, v) \
+ (BIT_CLEAR_HW_ID_8814B(x) | BIT_HW_ID_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_FEN_WLMAC_OFF_8814B BIT(31)
+#define BIT_PWC_MA33V_8814B BIT(15)
+#define BIT_PWC_MA12V_8814B BIT(14)
+#define BIT_PWC_MD12V_8814B BIT(13)
+#define BIT_PWC_PD12V_8814B BIT(12)
+#define BIT_PWC_UD12V_8814B BIT(11)
+#define BIT_ISO_BB2PP_8814B BIT(7)
+#define BIT_ISO_DENG2PP_8814B BIT(6)
+#define BIT_ISO_MA2MD_8814B BIT(1)
+#define BIT_ISO_MD2PP_8814B BIT(0)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_ANAPARSW_MAC_0_8814B */
+#define BIT_OCP_L_0_8814B BIT(31)
+#define BIT_POWOCP_L_8814B BIT(30)
+
+#define BIT_SHIFT_CF_L_1_0_8814B 28
+#define BIT_MASK_CF_L_1_0_8814B 0x3
+#define BIT_CF_L_1_0_8814B(x) \
+ (((x) & BIT_MASK_CF_L_1_0_8814B) << BIT_SHIFT_CF_L_1_0_8814B)
+#define BITS_CF_L_1_0_8814B \
+ (BIT_MASK_CF_L_1_0_8814B << BIT_SHIFT_CF_L_1_0_8814B)
+#define BIT_CLEAR_CF_L_1_0_8814B(x) ((x) & (~BITS_CF_L_1_0_8814B))
+#define BIT_GET_CF_L_1_0_8814B(x) \
+ (((x) >> BIT_SHIFT_CF_L_1_0_8814B) & BIT_MASK_CF_L_1_0_8814B)
+#define BIT_SET_CF_L_1_0_8814B(x, v) \
+ (BIT_CLEAR_CF_L_1_0_8814B(x) | BIT_CF_L_1_0_8814B(v))
+
+#define BIT_SHIFT_CFC_L_1_0_8814B 26
+#define BIT_MASK_CFC_L_1_0_8814B 0x3
+#define BIT_CFC_L_1_0_8814B(x) \
+ (((x) & BIT_MASK_CFC_L_1_0_8814B) << BIT_SHIFT_CFC_L_1_0_8814B)
+#define BITS_CFC_L_1_0_8814B \
+ (BIT_MASK_CFC_L_1_0_8814B << BIT_SHIFT_CFC_L_1_0_8814B)
+#define BIT_CLEAR_CFC_L_1_0_8814B(x) ((x) & (~BITS_CFC_L_1_0_8814B))
+#define BIT_GET_CFC_L_1_0_8814B(x) \
+ (((x) >> BIT_SHIFT_CFC_L_1_0_8814B) & BIT_MASK_CFC_L_1_0_8814B)
+#define BIT_SET_CFC_L_1_0_8814B(x, v) \
+ (BIT_CLEAR_CFC_L_1_0_8814B(x) | BIT_CFC_L_1_0_8814B(v))
+
+#define BIT_SHIFT_R3_L_1_0_8814B 24
+#define BIT_MASK_R3_L_1_0_8814B 0x3
+#define BIT_R3_L_1_0_8814B(x) \
+ (((x) & BIT_MASK_R3_L_1_0_8814B) << BIT_SHIFT_R3_L_1_0_8814B)
+#define BITS_R3_L_1_0_8814B \
+ (BIT_MASK_R3_L_1_0_8814B << BIT_SHIFT_R3_L_1_0_8814B)
+#define BIT_CLEAR_R3_L_1_0_8814B(x) ((x) & (~BITS_R3_L_1_0_8814B))
+#define BIT_GET_R3_L_1_0_8814B(x) \
+ (((x) >> BIT_SHIFT_R3_L_1_0_8814B) & BIT_MASK_R3_L_1_0_8814B)
+#define BIT_SET_R3_L_1_0_8814B(x, v) \
+ (BIT_CLEAR_R3_L_1_0_8814B(x) | BIT_R3_L_1_0_8814B(v))
+
+#define BIT_SHIFT_R2_L_1_0_8814B 22
+#define BIT_MASK_R2_L_1_0_8814B 0x3
+#define BIT_R2_L_1_0_8814B(x) \
+ (((x) & BIT_MASK_R2_L_1_0_8814B) << BIT_SHIFT_R2_L_1_0_8814B)
+#define BITS_R2_L_1_0_8814B \
+ (BIT_MASK_R2_L_1_0_8814B << BIT_SHIFT_R2_L_1_0_8814B)
+#define BIT_CLEAR_R2_L_1_0_8814B(x) ((x) & (~BITS_R2_L_1_0_8814B))
+#define BIT_GET_R2_L_1_0_8814B(x) \
+ (((x) >> BIT_SHIFT_R2_L_1_0_8814B) & BIT_MASK_R2_L_1_0_8814B)
+#define BIT_SET_R2_L_1_0_8814B(x, v) \
+ (BIT_CLEAR_R2_L_1_0_8814B(x) | BIT_R2_L_1_0_8814B(v))
+
+#define BIT_SHIFT_R1_L_1_0_8814B 20
+#define BIT_MASK_R1_L_1_0_8814B 0x3
+#define BIT_R1_L_1_0_8814B(x) \
+ (((x) & BIT_MASK_R1_L_1_0_8814B) << BIT_SHIFT_R1_L_1_0_8814B)
+#define BITS_R1_L_1_0_8814B \
+ (BIT_MASK_R1_L_1_0_8814B << BIT_SHIFT_R1_L_1_0_8814B)
+#define BIT_CLEAR_R1_L_1_0_8814B(x) ((x) & (~BITS_R1_L_1_0_8814B))
+#define BIT_GET_R1_L_1_0_8814B(x) \
+ (((x) >> BIT_SHIFT_R1_L_1_0_8814B) & BIT_MASK_R1_L_1_0_8814B)
+#define BIT_SET_R1_L_1_0_8814B(x, v) \
+ (BIT_CLEAR_R1_L_1_0_8814B(x) | BIT_R1_L_1_0_8814B(v))
+
+#define BIT_SHIFT_C3_L_1_0_8814B 18
+#define BIT_MASK_C3_L_1_0_8814B 0x3
+#define BIT_C3_L_1_0_8814B(x) \
+ (((x) & BIT_MASK_C3_L_1_0_8814B) << BIT_SHIFT_C3_L_1_0_8814B)
+#define BITS_C3_L_1_0_8814B \
+ (BIT_MASK_C3_L_1_0_8814B << BIT_SHIFT_C3_L_1_0_8814B)
+#define BIT_CLEAR_C3_L_1_0_8814B(x) ((x) & (~BITS_C3_L_1_0_8814B))
+#define BIT_GET_C3_L_1_0_8814B(x) \
+ (((x) >> BIT_SHIFT_C3_L_1_0_8814B) & BIT_MASK_C3_L_1_0_8814B)
+#define BIT_SET_C3_L_1_0_8814B(x, v) \
+ (BIT_CLEAR_C3_L_1_0_8814B(x) | BIT_C3_L_1_0_8814B(v))
+
+#define BIT_SHIFT_C2_L_1_0_8814B 16
+#define BIT_MASK_C2_L_1_0_8814B 0x3
+#define BIT_C2_L_1_0_8814B(x) \
+ (((x) & BIT_MASK_C2_L_1_0_8814B) << BIT_SHIFT_C2_L_1_0_8814B)
+#define BITS_C2_L_1_0_8814B \
+ (BIT_MASK_C2_L_1_0_8814B << BIT_SHIFT_C2_L_1_0_8814B)
+#define BIT_CLEAR_C2_L_1_0_8814B(x) ((x) & (~BITS_C2_L_1_0_8814B))
+#define BIT_GET_C2_L_1_0_8814B(x) \
+ (((x) >> BIT_SHIFT_C2_L_1_0_8814B) & BIT_MASK_C2_L_1_0_8814B)
+#define BIT_SET_C2_L_1_0_8814B(x, v) \
+ (BIT_CLEAR_C2_L_1_0_8814B(x) | BIT_C2_L_1_0_8814B(v))
+
+#define BIT_SHIFT_C1_L_1_0_8814B 14
+#define BIT_MASK_C1_L_1_0_8814B 0x3
+#define BIT_C1_L_1_0_8814B(x) \
+ (((x) & BIT_MASK_C1_L_1_0_8814B) << BIT_SHIFT_C1_L_1_0_8814B)
+#define BITS_C1_L_1_0_8814B \
+ (BIT_MASK_C1_L_1_0_8814B << BIT_SHIFT_C1_L_1_0_8814B)
+#define BIT_CLEAR_C1_L_1_0_8814B(x) ((x) & (~BITS_C1_L_1_0_8814B))
+#define BIT_GET_C1_L_1_0_8814B(x) \
+ (((x) >> BIT_SHIFT_C1_L_1_0_8814B) & BIT_MASK_C1_L_1_0_8814B)
+#define BIT_SET_C1_L_1_0_8814B(x, v) \
+ (BIT_CLEAR_C1_L_1_0_8814B(x) | BIT_C1_L_1_0_8814B(v))
+
+#define BIT_REG_TYPE_L_V2_8814B BIT(13)
+#define BIT_REG_PWM_L_8814B BIT(12)
+
+#define BIT_SHIFT_V15ADJ_L_2_0_8814B 9
+#define BIT_MASK_V15ADJ_L_2_0_8814B 0x7
+#define BIT_V15ADJ_L_2_0_8814B(x) \
+ (((x) & BIT_MASK_V15ADJ_L_2_0_8814B) << BIT_SHIFT_V15ADJ_L_2_0_8814B)
+#define BITS_V15ADJ_L_2_0_8814B \
+ (BIT_MASK_V15ADJ_L_2_0_8814B << BIT_SHIFT_V15ADJ_L_2_0_8814B)
+#define BIT_CLEAR_V15ADJ_L_2_0_8814B(x) ((x) & (~BITS_V15ADJ_L_2_0_8814B))
+#define BIT_GET_V15ADJ_L_2_0_8814B(x) \
+ (((x) >> BIT_SHIFT_V15ADJ_L_2_0_8814B) & BIT_MASK_V15ADJ_L_2_0_8814B)
+#define BIT_SET_V15ADJ_L_2_0_8814B(x, v) \
+ (BIT_CLEAR_V15ADJ_L_2_0_8814B(x) | BIT_V15ADJ_L_2_0_8814B(v))
+
+#define BIT_SHIFT_IN_L_2_0_8814B 6
+#define BIT_MASK_IN_L_2_0_8814B 0x7
+#define BIT_IN_L_2_0_8814B(x) \
+ (((x) & BIT_MASK_IN_L_2_0_8814B) << BIT_SHIFT_IN_L_2_0_8814B)
+#define BITS_IN_L_2_0_8814B \
+ (BIT_MASK_IN_L_2_0_8814B << BIT_SHIFT_IN_L_2_0_8814B)
+#define BIT_CLEAR_IN_L_2_0_8814B(x) ((x) & (~BITS_IN_L_2_0_8814B))
+#define BIT_GET_IN_L_2_0_8814B(x) \
+ (((x) >> BIT_SHIFT_IN_L_2_0_8814B) & BIT_MASK_IN_L_2_0_8814B)
+#define BIT_SET_IN_L_2_0_8814B(x, v) \
+ (BIT_CLEAR_IN_L_2_0_8814B(x) | BIT_IN_L_2_0_8814B(v))
+
+#define BIT_SHIFT_STD_L_1_0_8814B 4
+#define BIT_MASK_STD_L_1_0_8814B 0x3
+#define BIT_STD_L_1_0_8814B(x) \
+ (((x) & BIT_MASK_STD_L_1_0_8814B) << BIT_SHIFT_STD_L_1_0_8814B)
+#define BITS_STD_L_1_0_8814B \
+ (BIT_MASK_STD_L_1_0_8814B << BIT_SHIFT_STD_L_1_0_8814B)
+#define BIT_CLEAR_STD_L_1_0_8814B(x) ((x) & (~BITS_STD_L_1_0_8814B))
+#define BIT_GET_STD_L_1_0_8814B(x) \
+ (((x) >> BIT_SHIFT_STD_L_1_0_8814B) & BIT_MASK_STD_L_1_0_8814B)
+#define BIT_SET_STD_L_1_0_8814B(x, v) \
+ (BIT_CLEAR_STD_L_1_0_8814B(x) | BIT_STD_L_1_0_8814B(v))
+
+#define BIT_SHIFT_VOL_L_3_0_8814B 0
+#define BIT_MASK_VOL_L_3_0_8814B 0xf
+#define BIT_VOL_L_3_0_8814B(x) \
+ (((x) & BIT_MASK_VOL_L_3_0_8814B) << BIT_SHIFT_VOL_L_3_0_8814B)
+#define BITS_VOL_L_3_0_8814B \
+ (BIT_MASK_VOL_L_3_0_8814B << BIT_SHIFT_VOL_L_3_0_8814B)
+#define BIT_CLEAR_VOL_L_3_0_8814B(x) ((x) & (~BITS_VOL_L_3_0_8814B))
+#define BIT_GET_VOL_L_3_0_8814B(x) \
+ (((x) >> BIT_SHIFT_VOL_L_3_0_8814B) & BIT_MASK_VOL_L_3_0_8814B)
+#define BIT_SET_VOL_L_3_0_8814B(x, v) \
+ (BIT_CLEAR_VOL_L_3_0_8814B(x) | BIT_VOL_L_3_0_8814B(v))
+
+/* 2 REG_ANAPARSW_MAC_1_8814B */
+
+#define BIT_SHIFT_REG_FREQ_L_V1_8814B 20
+#define BIT_MASK_REG_FREQ_L_V1_8814B 0x7
+#define BIT_REG_FREQ_L_V1_8814B(x) \
+ (((x) & BIT_MASK_REG_FREQ_L_V1_8814B) << BIT_SHIFT_REG_FREQ_L_V1_8814B)
+#define BITS_REG_FREQ_L_V1_8814B \
+ (BIT_MASK_REG_FREQ_L_V1_8814B << BIT_SHIFT_REG_FREQ_L_V1_8814B)
+#define BIT_CLEAR_REG_FREQ_L_V1_8814B(x) ((x) & (~BITS_REG_FREQ_L_V1_8814B))
+#define BIT_GET_REG_FREQ_L_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_REG_FREQ_L_V1_8814B) & BIT_MASK_REG_FREQ_L_V1_8814B)
+#define BIT_SET_REG_FREQ_L_V1_8814B(x, v) \
+ (BIT_CLEAR_REG_FREQ_L_V1_8814B(x) | BIT_REG_FREQ_L_V1_8814B(v))
+
+#define BIT_EN_DUTY_8814B BIT(19)
+
+#define BIT_SHIFT_REG_MOS_HALF_8814B 17
+#define BIT_MASK_REG_MOS_HALF_8814B 0x3
+#define BIT_REG_MOS_HALF_8814B(x) \
+ (((x) & BIT_MASK_REG_MOS_HALF_8814B) << BIT_SHIFT_REG_MOS_HALF_8814B)
+#define BITS_REG_MOS_HALF_8814B \
+ (BIT_MASK_REG_MOS_HALF_8814B << BIT_SHIFT_REG_MOS_HALF_8814B)
+#define BIT_CLEAR_REG_MOS_HALF_8814B(x) ((x) & (~BITS_REG_MOS_HALF_8814B))
+#define BIT_GET_REG_MOS_HALF_8814B(x) \
+ (((x) >> BIT_SHIFT_REG_MOS_HALF_8814B) & BIT_MASK_REG_MOS_HALF_8814B)
+#define BIT_SET_REG_MOS_HALF_8814B(x, v) \
+ (BIT_CLEAR_REG_MOS_HALF_8814B(x) | BIT_REG_MOS_HALF_8814B(v))
+
+#define BIT_EN_SP_8814B BIT(16)
+#define BIT_REG_AUTO_L_V1_8814B BIT(15)
+#define BIT_REG_LDOF_L_V2_8814B BIT(14)
+#define BIT_REG_OCPS_L_V2_8814B BIT(13)
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_ARENB_L_V1_8814B BIT(11)
+
+#define BIT_SHIFT_TBOX_L1_1_0_8814B 9
+#define BIT_MASK_TBOX_L1_1_0_8814B 0x3
+#define BIT_TBOX_L1_1_0_8814B(x) \
+ (((x) & BIT_MASK_TBOX_L1_1_0_8814B) << BIT_SHIFT_TBOX_L1_1_0_8814B)
+#define BITS_TBOX_L1_1_0_8814B \
+ (BIT_MASK_TBOX_L1_1_0_8814B << BIT_SHIFT_TBOX_L1_1_0_8814B)
+#define BIT_CLEAR_TBOX_L1_1_0_8814B(x) ((x) & (~BITS_TBOX_L1_1_0_8814B))
+#define BIT_GET_TBOX_L1_1_0_8814B(x) \
+ (((x) >> BIT_SHIFT_TBOX_L1_1_0_8814B) & BIT_MASK_TBOX_L1_1_0_8814B)
+#define BIT_SET_TBOX_L1_1_0_8814B(x, v) \
+ (BIT_CLEAR_TBOX_L1_1_0_8814B(x) | BIT_TBOX_L1_1_0_8814B(v))
+
+#define BIT_SHIFT_REG_DELAY_L_1_0_8814B 7
+#define BIT_MASK_REG_DELAY_L_1_0_8814B 0x3
+#define BIT_REG_DELAY_L_1_0_8814B(x) \
+ (((x) & BIT_MASK_REG_DELAY_L_1_0_8814B) \
+ << BIT_SHIFT_REG_DELAY_L_1_0_8814B)
+#define BITS_REG_DELAY_L_1_0_8814B \
+ (BIT_MASK_REG_DELAY_L_1_0_8814B << BIT_SHIFT_REG_DELAY_L_1_0_8814B)
+#define BIT_CLEAR_REG_DELAY_L_1_0_8814B(x) ((x) & (~BITS_REG_DELAY_L_1_0_8814B))
+#define BIT_GET_REG_DELAY_L_1_0_8814B(x) \
+ (((x) >> BIT_SHIFT_REG_DELAY_L_1_0_8814B) & \
+ BIT_MASK_REG_DELAY_L_1_0_8814B)
+#define BIT_SET_REG_DELAY_L_1_0_8814B(x, v) \
+ (BIT_CLEAR_REG_DELAY_L_1_0_8814B(x) | BIT_REG_DELAY_L_1_0_8814B(v))
+
+#define BIT_REG_CLAMP_D_L_8814B BIT(6)
+#define BIT_REG_BYPASS_L_V1_8814B BIT(5)
+#define BIT_REG_AUTOZCD_L_8814B BIT(4)
+#define BIT_POW_ZCD_L_V1_8814B BIT(3)
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_OCP_L_2_1_8814B 0
+#define BIT_MASK_OCP_L_2_1_8814B 0x3
+#define BIT_OCP_L_2_1_8814B(x) \
+ (((x) & BIT_MASK_OCP_L_2_1_8814B) << BIT_SHIFT_OCP_L_2_1_8814B)
+#define BITS_OCP_L_2_1_8814B \
+ (BIT_MASK_OCP_L_2_1_8814B << BIT_SHIFT_OCP_L_2_1_8814B)
+#define BIT_CLEAR_OCP_L_2_1_8814B(x) ((x) & (~BITS_OCP_L_2_1_8814B))
+#define BIT_GET_OCP_L_2_1_8814B(x) \
+ (((x) >> BIT_SHIFT_OCP_L_2_1_8814B) & BIT_MASK_OCP_L_2_1_8814B)
+#define BIT_SET_OCP_L_2_1_8814B(x, v) \
+ (BIT_CLEAR_OCP_L_2_1_8814B(x) | BIT_OCP_L_2_1_8814B(v))
+
+/* 2 REG_ANAPAR_MAC_0_8814B */
+
+#define BIT_SHIFT_LPF_C2_1_0_8814B 30
+#define BIT_MASK_LPF_C2_1_0_8814B 0x3
+#define BIT_LPF_C2_1_0_8814B(x) \
+ (((x) & BIT_MASK_LPF_C2_1_0_8814B) << BIT_SHIFT_LPF_C2_1_0_8814B)
+#define BITS_LPF_C2_1_0_8814B \
+ (BIT_MASK_LPF_C2_1_0_8814B << BIT_SHIFT_LPF_C2_1_0_8814B)
+#define BIT_CLEAR_LPF_C2_1_0_8814B(x) ((x) & (~BITS_LPF_C2_1_0_8814B))
+#define BIT_GET_LPF_C2_1_0_8814B(x) \
+ (((x) >> BIT_SHIFT_LPF_C2_1_0_8814B) & BIT_MASK_LPF_C2_1_0_8814B)
+#define BIT_SET_LPF_C2_1_0_8814B(x, v) \
+ (BIT_CLEAR_LPF_C2_1_0_8814B(x) | BIT_LPF_C2_1_0_8814B(v))
+
+#define BIT_SHIFT_LPF_C1_5_0_8814B 24
+#define BIT_MASK_LPF_C1_5_0_8814B 0x3f
+#define BIT_LPF_C1_5_0_8814B(x) \
+ (((x) & BIT_MASK_LPF_C1_5_0_8814B) << BIT_SHIFT_LPF_C1_5_0_8814B)
+#define BITS_LPF_C1_5_0_8814B \
+ (BIT_MASK_LPF_C1_5_0_8814B << BIT_SHIFT_LPF_C1_5_0_8814B)
+#define BIT_CLEAR_LPF_C1_5_0_8814B(x) ((x) & (~BITS_LPF_C1_5_0_8814B))
+#define BIT_GET_LPF_C1_5_0_8814B(x) \
+ (((x) >> BIT_SHIFT_LPF_C1_5_0_8814B) & BIT_MASK_LPF_C1_5_0_8814B)
+#define BIT_SET_LPF_C1_5_0_8814B(x, v) \
+ (BIT_CLEAR_LPF_C1_5_0_8814B(x) | BIT_LPF_C1_5_0_8814B(v))
+
+#define BIT_LPF_TIEL_8814B BIT(23)
+#define BIT_LPF_TIEH_8814B BIT(22)
+
+#define BIT_SHIFT_LOCKDET_VREF_L_1_0_8814B 20
+#define BIT_MASK_LOCKDET_VREF_L_1_0_8814B 0x3
+#define BIT_LOCKDET_VREF_L_1_0_8814B(x) \
+ (((x) & BIT_MASK_LOCKDET_VREF_L_1_0_8814B) \
+ << BIT_SHIFT_LOCKDET_VREF_L_1_0_8814B)
+#define BITS_LOCKDET_VREF_L_1_0_8814B \
+ (BIT_MASK_LOCKDET_VREF_L_1_0_8814B \
+ << BIT_SHIFT_LOCKDET_VREF_L_1_0_8814B)
+#define BIT_CLEAR_LOCKDET_VREF_L_1_0_8814B(x) \
+ ((x) & (~BITS_LOCKDET_VREF_L_1_0_8814B))
+#define BIT_GET_LOCKDET_VREF_L_1_0_8814B(x) \
+ (((x) >> BIT_SHIFT_LOCKDET_VREF_L_1_0_8814B) & \
+ BIT_MASK_LOCKDET_VREF_L_1_0_8814B)
+#define BIT_SET_LOCKDET_VREF_L_1_0_8814B(x, v) \
+ (BIT_CLEAR_LOCKDET_VREF_L_1_0_8814B(x) | \
+ BIT_LOCKDET_VREF_L_1_0_8814B(v))
+
+#define BIT_SHIFT_LOCKDET_VREF_H_1_0_8814B 18
+#define BIT_MASK_LOCKDET_VREF_H_1_0_8814B 0x3
+#define BIT_LOCKDET_VREF_H_1_0_8814B(x) \
+ (((x) & BIT_MASK_LOCKDET_VREF_H_1_0_8814B) \
+ << BIT_SHIFT_LOCKDET_VREF_H_1_0_8814B)
+#define BITS_LOCKDET_VREF_H_1_0_8814B \
+ (BIT_MASK_LOCKDET_VREF_H_1_0_8814B \
+ << BIT_SHIFT_LOCKDET_VREF_H_1_0_8814B)
+#define BIT_CLEAR_LOCKDET_VREF_H_1_0_8814B(x) \
+ ((x) & (~BITS_LOCKDET_VREF_H_1_0_8814B))
+#define BIT_GET_LOCKDET_VREF_H_1_0_8814B(x) \
+ (((x) >> BIT_SHIFT_LOCKDET_VREF_H_1_0_8814B) & \
+ BIT_MASK_LOCKDET_VREF_H_1_0_8814B)
+#define BIT_SET_LOCKDET_VREF_H_1_0_8814B(x, v) \
+ (BIT_CLEAR_LOCKDET_VREF_H_1_0_8814B(x) | \
+ BIT_LOCKDET_VREF_H_1_0_8814B(v))
+
+#define BIT_SHIFT_LDO_SEL_1_0_8814B 16
+#define BIT_MASK_LDO_SEL_1_0_8814B 0x3
+#define BIT_LDO_SEL_1_0_8814B(x) \
+ (((x) & BIT_MASK_LDO_SEL_1_0_8814B) << BIT_SHIFT_LDO_SEL_1_0_8814B)
+#define BITS_LDO_SEL_1_0_8814B \
+ (BIT_MASK_LDO_SEL_1_0_8814B << BIT_SHIFT_LDO_SEL_1_0_8814B)
+#define BIT_CLEAR_LDO_SEL_1_0_8814B(x) ((x) & (~BITS_LDO_SEL_1_0_8814B))
+#define BIT_GET_LDO_SEL_1_0_8814B(x) \
+ (((x) >> BIT_SHIFT_LDO_SEL_1_0_8814B) & BIT_MASK_LDO_SEL_1_0_8814B)
+#define BIT_SET_LDO_SEL_1_0_8814B(x, v) \
+ (BIT_CLEAR_LDO_SEL_1_0_8814B(x) | BIT_LDO_SEL_1_0_8814B(v))
+
+#define BIT_SHIFT_IOFFSET_5_0_8814B 10
+#define BIT_MASK_IOFFSET_5_0_8814B 0x3f
+#define BIT_IOFFSET_5_0_8814B(x) \
+ (((x) & BIT_MASK_IOFFSET_5_0_8814B) << BIT_SHIFT_IOFFSET_5_0_8814B)
+#define BITS_IOFFSET_5_0_8814B \
+ (BIT_MASK_IOFFSET_5_0_8814B << BIT_SHIFT_IOFFSET_5_0_8814B)
+#define BIT_CLEAR_IOFFSET_5_0_8814B(x) ((x) & (~BITS_IOFFSET_5_0_8814B))
+#define BIT_GET_IOFFSET_5_0_8814B(x) \
+ (((x) >> BIT_SHIFT_IOFFSET_5_0_8814B) & BIT_MASK_IOFFSET_5_0_8814B)
+#define BIT_SET_IOFFSET_5_0_8814B(x, v) \
+ (BIT_CLEAR_IOFFSET_5_0_8814B(x) | BIT_IOFFSET_5_0_8814B(v))
+
+#define BIT_CP_ICPX2_8814B BIT(9)
+
+#define BIT_SHIFT_CP_ICP_SEL_4_0_8814B 4
+#define BIT_MASK_CP_ICP_SEL_4_0_8814B 0x1f
+#define BIT_CP_ICP_SEL_4_0_8814B(x) \
+ (((x) & BIT_MASK_CP_ICP_SEL_4_0_8814B) \
+ << BIT_SHIFT_CP_ICP_SEL_4_0_8814B)
+#define BITS_CP_ICP_SEL_4_0_8814B \
+ (BIT_MASK_CP_ICP_SEL_4_0_8814B << BIT_SHIFT_CP_ICP_SEL_4_0_8814B)
+#define BIT_CLEAR_CP_ICP_SEL_4_0_8814B(x) ((x) & (~BITS_CP_ICP_SEL_4_0_8814B))
+#define BIT_GET_CP_ICP_SEL_4_0_8814B(x) \
+ (((x) >> BIT_SHIFT_CP_ICP_SEL_4_0_8814B) & \
+ BIT_MASK_CP_ICP_SEL_4_0_8814B)
+#define BIT_SET_CP_ICP_SEL_4_0_8814B(x, v) \
+ (BIT_CLEAR_CP_ICP_SEL_4_0_8814B(x) | BIT_CP_ICP_SEL_4_0_8814B(v))
+
+#define BIT_SHIFT_IB_PI_1_0_8814B 2
+#define BIT_MASK_IB_PI_1_0_8814B 0x3
+#define BIT_IB_PI_1_0_8814B(x) \
+ (((x) & BIT_MASK_IB_PI_1_0_8814B) << BIT_SHIFT_IB_PI_1_0_8814B)
+#define BITS_IB_PI_1_0_8814B \
+ (BIT_MASK_IB_PI_1_0_8814B << BIT_SHIFT_IB_PI_1_0_8814B)
+#define BIT_CLEAR_IB_PI_1_0_8814B(x) ((x) & (~BITS_IB_PI_1_0_8814B))
+#define BIT_GET_IB_PI_1_0_8814B(x) \
+ (((x) >> BIT_SHIFT_IB_PI_1_0_8814B) & BIT_MASK_IB_PI_1_0_8814B)
+#define BIT_SET_IB_PI_1_0_8814B(x, v) \
+ (BIT_CLEAR_IB_PI_1_0_8814B(x) | BIT_IB_PI_1_0_8814B(v))
+
+#define BIT_SHIFT_LDO_VSEL_8814B 0
+#define BIT_MASK_LDO_VSEL_8814B 0x3
+#define BIT_LDO_VSEL_8814B(x) \
+ (((x) & BIT_MASK_LDO_VSEL_8814B) << BIT_SHIFT_LDO_VSEL_8814B)
+#define BITS_LDO_VSEL_8814B \
+ (BIT_MASK_LDO_VSEL_8814B << BIT_SHIFT_LDO_VSEL_8814B)
+#define BIT_CLEAR_LDO_VSEL_8814B(x) ((x) & (~BITS_LDO_VSEL_8814B))
+#define BIT_GET_LDO_VSEL_8814B(x) \
+ (((x) >> BIT_SHIFT_LDO_VSEL_8814B) & BIT_MASK_LDO_VSEL_8814B)
+#define BIT_SET_LDO_VSEL_8814B(x, v) \
+ (BIT_CLEAR_LDO_VSEL_8814B(x) | BIT_LDO_VSEL_8814B(v))
+
+/* 2 REG_ANAPAR_MAC_1_8814B */
+
+#define BIT_SHIFT_CKX_USB_IB_SEL_8814B 29
+#define BIT_MASK_CKX_USB_IB_SEL_8814B 0x7
+#define BIT_CKX_USB_IB_SEL_8814B(x) \
+ (((x) & BIT_MASK_CKX_USB_IB_SEL_8814B) \
+ << BIT_SHIFT_CKX_USB_IB_SEL_8814B)
+#define BITS_CKX_USB_IB_SEL_8814B \
+ (BIT_MASK_CKX_USB_IB_SEL_8814B << BIT_SHIFT_CKX_USB_IB_SEL_8814B)
+#define BIT_CLEAR_CKX_USB_IB_SEL_8814B(x) ((x) & (~BITS_CKX_USB_IB_SEL_8814B))
+#define BIT_GET_CKX_USB_IB_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_CKX_USB_IB_SEL_8814B) & \
+ BIT_MASK_CKX_USB_IB_SEL_8814B)
+#define BIT_SET_CKX_USB_IB_SEL_8814B(x, v) \
+ (BIT_CLEAR_CKX_USB_IB_SEL_8814B(x) | BIT_CKX_USB_IB_SEL_8814B(v))
+
+#define BIT_PFD_DN_GATED_8814B BIT(28)
+#define BIT_PFD_UP_GATED_8814B BIT(27)
+#define BIT_PFD_RESET_GATED_8814B BIT(26)
+
+#define BIT_SHIFT_PFD_OUT_DRV_1_0_8814B 24
+#define BIT_MASK_PFD_OUT_DRV_1_0_8814B 0x3
+#define BIT_PFD_OUT_DRV_1_0_8814B(x) \
+ (((x) & BIT_MASK_PFD_OUT_DRV_1_0_8814B) \
+ << BIT_SHIFT_PFD_OUT_DRV_1_0_8814B)
+#define BITS_PFD_OUT_DRV_1_0_8814B \
+ (BIT_MASK_PFD_OUT_DRV_1_0_8814B << BIT_SHIFT_PFD_OUT_DRV_1_0_8814B)
+#define BIT_CLEAR_PFD_OUT_DRV_1_0_8814B(x) ((x) & (~BITS_PFD_OUT_DRV_1_0_8814B))
+#define BIT_GET_PFD_OUT_DRV_1_0_8814B(x) \
+ (((x) >> BIT_SHIFT_PFD_OUT_DRV_1_0_8814B) & \
+ BIT_MASK_PFD_OUT_DRV_1_0_8814B)
+#define BIT_SET_PFD_OUT_DRV_1_0_8814B(x, v) \
+ (BIT_CLEAR_PFD_OUT_DRV_1_0_8814B(x) | BIT_PFD_OUT_DRV_1_0_8814B(v))
+
+#define BIT_SHIFT_LPF_TIEMID_2_0_8814B 20
+#define BIT_MASK_LPF_TIEMID_2_0_8814B 0x7
+#define BIT_LPF_TIEMID_2_0_8814B(x) \
+ (((x) & BIT_MASK_LPF_TIEMID_2_0_8814B) \
+ << BIT_SHIFT_LPF_TIEMID_2_0_8814B)
+#define BITS_LPF_TIEMID_2_0_8814B \
+ (BIT_MASK_LPF_TIEMID_2_0_8814B << BIT_SHIFT_LPF_TIEMID_2_0_8814B)
+#define BIT_CLEAR_LPF_TIEMID_2_0_8814B(x) ((x) & (~BITS_LPF_TIEMID_2_0_8814B))
+#define BIT_GET_LPF_TIEMID_2_0_8814B(x) \
+ (((x) >> BIT_SHIFT_LPF_TIEMID_2_0_8814B) & \
+ BIT_MASK_LPF_TIEMID_2_0_8814B)
+#define BIT_SET_LPF_TIEMID_2_0_8814B(x, v) \
+ (BIT_CLEAR_LPF_TIEMID_2_0_8814B(x) | BIT_LPF_TIEMID_2_0_8814B(v))
+
+#define BIT_SHIFT_LPF_R3_4_0_8814B 15
+#define BIT_MASK_LPF_R3_4_0_8814B 0x1f
+#define BIT_LPF_R3_4_0_8814B(x) \
+ (((x) & BIT_MASK_LPF_R3_4_0_8814B) << BIT_SHIFT_LPF_R3_4_0_8814B)
+#define BITS_LPF_R3_4_0_8814B \
+ (BIT_MASK_LPF_R3_4_0_8814B << BIT_SHIFT_LPF_R3_4_0_8814B)
+#define BIT_CLEAR_LPF_R3_4_0_8814B(x) ((x) & (~BITS_LPF_R3_4_0_8814B))
+#define BIT_GET_LPF_R3_4_0_8814B(x) \
+ (((x) >> BIT_SHIFT_LPF_R3_4_0_8814B) & BIT_MASK_LPF_R3_4_0_8814B)
+#define BIT_SET_LPF_R3_4_0_8814B(x, v) \
+ (BIT_CLEAR_LPF_R3_4_0_8814B(x) | BIT_LPF_R3_4_0_8814B(v))
+
+#define BIT_SHIFT_LPF_R2_4_0_8814B 10
+#define BIT_MASK_LPF_R2_4_0_8814B 0x1f
+#define BIT_LPF_R2_4_0_8814B(x) \
+ (((x) & BIT_MASK_LPF_R2_4_0_8814B) << BIT_SHIFT_LPF_R2_4_0_8814B)
+#define BITS_LPF_R2_4_0_8814B \
+ (BIT_MASK_LPF_R2_4_0_8814B << BIT_SHIFT_LPF_R2_4_0_8814B)
+#define BIT_CLEAR_LPF_R2_4_0_8814B(x) ((x) & (~BITS_LPF_R2_4_0_8814B))
+#define BIT_GET_LPF_R2_4_0_8814B(x) \
+ (((x) >> BIT_SHIFT_LPF_R2_4_0_8814B) & BIT_MASK_LPF_R2_4_0_8814B)
+#define BIT_SET_LPF_R2_4_0_8814B(x, v) \
+ (BIT_CLEAR_LPF_R2_4_0_8814B(x) | BIT_LPF_R2_4_0_8814B(v))
+
+#define BIT_SHIFT_LPF_C3_5_0_8814B 4
+#define BIT_MASK_LPF_C3_5_0_8814B 0x3f
+#define BIT_LPF_C3_5_0_8814B(x) \
+ (((x) & BIT_MASK_LPF_C3_5_0_8814B) << BIT_SHIFT_LPF_C3_5_0_8814B)
+#define BITS_LPF_C3_5_0_8814B \
+ (BIT_MASK_LPF_C3_5_0_8814B << BIT_SHIFT_LPF_C3_5_0_8814B)
+#define BIT_CLEAR_LPF_C3_5_0_8814B(x) ((x) & (~BITS_LPF_C3_5_0_8814B))
+#define BIT_GET_LPF_C3_5_0_8814B(x) \
+ (((x) >> BIT_SHIFT_LPF_C3_5_0_8814B) & BIT_MASK_LPF_C3_5_0_8814B)
+#define BIT_SET_LPF_C3_5_0_8814B(x, v) \
+ (BIT_CLEAR_LPF_C3_5_0_8814B(x) | BIT_LPF_C3_5_0_8814B(v))
+
+#define BIT_SHIFT_LPF_C2_5_2_8814B 0
+#define BIT_MASK_LPF_C2_5_2_8814B 0xf
+#define BIT_LPF_C2_5_2_8814B(x) \
+ (((x) & BIT_MASK_LPF_C2_5_2_8814B) << BIT_SHIFT_LPF_C2_5_2_8814B)
+#define BITS_LPF_C2_5_2_8814B \
+ (BIT_MASK_LPF_C2_5_2_8814B << BIT_SHIFT_LPF_C2_5_2_8814B)
+#define BIT_CLEAR_LPF_C2_5_2_8814B(x) ((x) & (~BITS_LPF_C2_5_2_8814B))
+#define BIT_GET_LPF_C2_5_2_8814B(x) \
+ (((x) >> BIT_SHIFT_LPF_C2_5_2_8814B) & BIT_MASK_LPF_C2_5_2_8814B)
+#define BIT_SET_LPF_C2_5_2_8814B(x, v) \
+ (BIT_CLEAR_LPF_C2_5_2_8814B(x) | BIT_LPF_C2_5_2_8814B(v))
+
+/* 2 REG_ANAPAR_MAC_2_8814B */
+#define BIT_CK_PHASE_SEL_8814B BIT(31)
+#define BIT_CK960M_EN_8814B BIT(30)
+#define BIT_CK640M_EN_8814B BIT(29)
+#define BIT_CK240M_EN_8814B BIT(28)
+
+#define BIT_SHIFT_CK_MON_SEL_2_0_8814B 25
+#define BIT_MASK_CK_MON_SEL_2_0_8814B 0x7
+#define BIT_CK_MON_SEL_2_0_8814B(x) \
+ (((x) & BIT_MASK_CK_MON_SEL_2_0_8814B) \
+ << BIT_SHIFT_CK_MON_SEL_2_0_8814B)
+#define BITS_CK_MON_SEL_2_0_8814B \
+ (BIT_MASK_CK_MON_SEL_2_0_8814B << BIT_SHIFT_CK_MON_SEL_2_0_8814B)
+#define BIT_CLEAR_CK_MON_SEL_2_0_8814B(x) ((x) & (~BITS_CK_MON_SEL_2_0_8814B))
+#define BIT_GET_CK_MON_SEL_2_0_8814B(x) \
+ (((x) >> BIT_SHIFT_CK_MON_SEL_2_0_8814B) & \
+ BIT_MASK_CK_MON_SEL_2_0_8814B)
+#define BIT_SET_CK_MON_SEL_2_0_8814B(x, v) \
+ (BIT_CLEAR_CK_MON_SEL_2_0_8814B(x) | BIT_CK_MON_SEL_2_0_8814B(v))
+
+#define BIT_CK_MON_EN_V1_8814B BIT(24)
+#define BIT_XTAL_SOURCE_SEL_8814B BIT(23)
+#define BIT_XTAL_FREQ_SEL_8814B BIT(22)
+#define BIT_XTAL_EDGE_SEL_8814B BIT(21)
+#define BIT_XTAL_BUF_SEL_8814B BIT(20)
+
+#define BIT_SHIFT_VCO_CV_7_0_8814B 4
+#define BIT_MASK_VCO_CV_7_0_8814B 0xff
+#define BIT_VCO_CV_7_0_8814B(x) \
+ (((x) & BIT_MASK_VCO_CV_7_0_8814B) << BIT_SHIFT_VCO_CV_7_0_8814B)
+#define BITS_VCO_CV_7_0_8814B \
+ (BIT_MASK_VCO_CV_7_0_8814B << BIT_SHIFT_VCO_CV_7_0_8814B)
+#define BIT_CLEAR_VCO_CV_7_0_8814B(x) ((x) & (~BITS_VCO_CV_7_0_8814B))
+#define BIT_GET_VCO_CV_7_0_8814B(x) \
+ (((x) >> BIT_SHIFT_VCO_CV_7_0_8814B) & BIT_MASK_VCO_CV_7_0_8814B)
+#define BIT_SET_VCO_CV_7_0_8814B(x, v) \
+ (BIT_CLEAR_VCO_CV_7_0_8814B(x) | BIT_VCO_CV_7_0_8814B(v))
+
+#define BIT_VCO_KVCO_8814B BIT(3)
+#define BIT_SDM_EDGE_SEL_8814B BIT(2)
+#define BIT_SDM_CK_SEL_8814B BIT(1)
+#define BIT_SDM_CK_GATED_8814B BIT(0)
+
+/* 2 REG_ANAPAR_MAC_3_8814B */
+
+#define BIT_SHIFT_LCK_WAIT_CYCLE_2_0_8814B 28
+#define BIT_MASK_LCK_WAIT_CYCLE_2_0_8814B 0x7
+#define BIT_LCK_WAIT_CYCLE_2_0_8814B(x) \
+ (((x) & BIT_MASK_LCK_WAIT_CYCLE_2_0_8814B) \
+ << BIT_SHIFT_LCK_WAIT_CYCLE_2_0_8814B)
+#define BITS_LCK_WAIT_CYCLE_2_0_8814B \
+ (BIT_MASK_LCK_WAIT_CYCLE_2_0_8814B \
+ << BIT_SHIFT_LCK_WAIT_CYCLE_2_0_8814B)
+#define BIT_CLEAR_LCK_WAIT_CYCLE_2_0_8814B(x) \
+ ((x) & (~BITS_LCK_WAIT_CYCLE_2_0_8814B))
+#define BIT_GET_LCK_WAIT_CYCLE_2_0_8814B(x) \
+ (((x) >> BIT_SHIFT_LCK_WAIT_CYCLE_2_0_8814B) & \
+ BIT_MASK_LCK_WAIT_CYCLE_2_0_8814B)
+#define BIT_SET_LCK_WAIT_CYCLE_2_0_8814B(x, v) \
+ (BIT_CLEAR_LCK_WAIT_CYCLE_2_0_8814B(x) | \
+ BIT_LCK_WAIT_CYCLE_2_0_8814B(v))
+
+#define BIT_SHIFT_LCK_VCO_DIVISOR_1_0_8814B 26
+#define BIT_MASK_LCK_VCO_DIVISOR_1_0_8814B 0x3
+#define BIT_LCK_VCO_DIVISOR_1_0_8814B(x) \
+ (((x) & BIT_MASK_LCK_VCO_DIVISOR_1_0_8814B) \
+ << BIT_SHIFT_LCK_VCO_DIVISOR_1_0_8814B)
+#define BITS_LCK_VCO_DIVISOR_1_0_8814B \
+ (BIT_MASK_LCK_VCO_DIVISOR_1_0_8814B \
+ << BIT_SHIFT_LCK_VCO_DIVISOR_1_0_8814B)
+#define BIT_CLEAR_LCK_VCO_DIVISOR_1_0_8814B(x) \
+ ((x) & (~BITS_LCK_VCO_DIVISOR_1_0_8814B))
+#define BIT_GET_LCK_VCO_DIVISOR_1_0_8814B(x) \
+ (((x) >> BIT_SHIFT_LCK_VCO_DIVISOR_1_0_8814B) & \
+ BIT_MASK_LCK_VCO_DIVISOR_1_0_8814B)
+#define BIT_SET_LCK_VCO_DIVISOR_1_0_8814B(x, v) \
+ (BIT_CLEAR_LCK_VCO_DIVISOR_1_0_8814B(x) | \
+ BIT_LCK_VCO_DIVISOR_1_0_8814B(v))
+
+#define BIT_SHIFT_LCK_SEARCH_MODE_1_0_8814B 24
+#define BIT_MASK_LCK_SEARCH_MODE_1_0_8814B 0x3
+#define BIT_LCK_SEARCH_MODE_1_0_8814B(x) \
+ (((x) & BIT_MASK_LCK_SEARCH_MODE_1_0_8814B) \
+ << BIT_SHIFT_LCK_SEARCH_MODE_1_0_8814B)
+#define BITS_LCK_SEARCH_MODE_1_0_8814B \
+ (BIT_MASK_LCK_SEARCH_MODE_1_0_8814B \
+ << BIT_SHIFT_LCK_SEARCH_MODE_1_0_8814B)
+#define BIT_CLEAR_LCK_SEARCH_MODE_1_0_8814B(x) \
+ ((x) & (~BITS_LCK_SEARCH_MODE_1_0_8814B))
+#define BIT_GET_LCK_SEARCH_MODE_1_0_8814B(x) \
+ (((x) >> BIT_SHIFT_LCK_SEARCH_MODE_1_0_8814B) & \
+ BIT_MASK_LCK_SEARCH_MODE_1_0_8814B)
+#define BIT_SET_LCK_SEARCH_MODE_1_0_8814B(x, v) \
+ (BIT_CLEAR_LCK_SEARCH_MODE_1_0_8814B(x) | \
+ BIT_LCK_SEARCH_MODE_1_0_8814B(v))
+
+#define BIT_SHIFT_LS_CV_OFFSET_3_0_8814B 12
+#define BIT_MASK_LS_CV_OFFSET_3_0_8814B 0xf
+#define BIT_LS_CV_OFFSET_3_0_8814B(x) \
+ (((x) & BIT_MASK_LS_CV_OFFSET_3_0_8814B) \
+ << BIT_SHIFT_LS_CV_OFFSET_3_0_8814B)
+#define BITS_LS_CV_OFFSET_3_0_8814B \
+ (BIT_MASK_LS_CV_OFFSET_3_0_8814B << BIT_SHIFT_LS_CV_OFFSET_3_0_8814B)
+#define BIT_CLEAR_LS_CV_OFFSET_3_0_8814B(x) \
+ ((x) & (~BITS_LS_CV_OFFSET_3_0_8814B))
+#define BIT_GET_LS_CV_OFFSET_3_0_8814B(x) \
+ (((x) >> BIT_SHIFT_LS_CV_OFFSET_3_0_8814B) & \
+ BIT_MASK_LS_CV_OFFSET_3_0_8814B)
+#define BIT_SET_LS_CV_OFFSET_3_0_8814B(x, v) \
+ (BIT_CLEAR_LS_CV_OFFSET_3_0_8814B(x) | BIT_LS_CV_OFFSET_3_0_8814B(v))
+
+#define BIT_LS_EN_LC_CK40M_8814B BIT(11)
+#define BIT_LS__CV_MANUAL_8814B BIT(10)
+#define BIT_LS_PYPASS_PI_8814B BIT(9)
+#define BIT_MBIASE_8814B BIT(4)
+
+/* 2 REG_ANAPAR_MAC_4_8814B */
+#define BIT_LS_TIE_MID_MODE_8814B BIT(28)
+
+#define BIT_SHIFT_LS_SYNC_CYCLE_1_0_8814B 26
+#define BIT_MASK_LS_SYNC_CYCLE_1_0_8814B 0x3
+#define BIT_LS_SYNC_CYCLE_1_0_8814B(x) \
+ (((x) & BIT_MASK_LS_SYNC_CYCLE_1_0_8814B) \
+ << BIT_SHIFT_LS_SYNC_CYCLE_1_0_8814B)
+#define BITS_LS_SYNC_CYCLE_1_0_8814B \
+ (BIT_MASK_LS_SYNC_CYCLE_1_0_8814B << BIT_SHIFT_LS_SYNC_CYCLE_1_0_8814B)
+#define BIT_CLEAR_LS_SYNC_CYCLE_1_0_8814B(x) \
+ ((x) & (~BITS_LS_SYNC_CYCLE_1_0_8814B))
+#define BIT_GET_LS_SYNC_CYCLE_1_0_8814B(x) \
+ (((x) >> BIT_SHIFT_LS_SYNC_CYCLE_1_0_8814B) & \
+ BIT_MASK_LS_SYNC_CYCLE_1_0_8814B)
+#define BIT_SET_LS_SYNC_CYCLE_1_0_8814B(x, v) \
+ (BIT_CLEAR_LS_SYNC_CYCLE_1_0_8814B(x) | BIT_LS_SYNC_CYCLE_1_0_8814B(v))
+
+#define BIT_LS_SDM_ORDER_8814B BIT(25)
+#define BIT_LS_RST_LC_CAL_8814B BIT(14)
+#define BIT_LS_RSTB_8814B BIT(13)
+#define BIT_LS_POW_LC_CAL_PREP_8814B BIT(11)
+
+#define BIT_SHIFT_LCK_XTAL_DIVISOR_1_0_8814B 0
+#define BIT_MASK_LCK_XTAL_DIVISOR_1_0_8814B 0x3
+#define BIT_LCK_XTAL_DIVISOR_1_0_8814B(x) \
+ (((x) & BIT_MASK_LCK_XTAL_DIVISOR_1_0_8814B) \
+ << BIT_SHIFT_LCK_XTAL_DIVISOR_1_0_8814B)
+#define BITS_LCK_XTAL_DIVISOR_1_0_8814B \
+ (BIT_MASK_LCK_XTAL_DIVISOR_1_0_8814B \
+ << BIT_SHIFT_LCK_XTAL_DIVISOR_1_0_8814B)
+#define BIT_CLEAR_LCK_XTAL_DIVISOR_1_0_8814B(x) \
+ ((x) & (~BITS_LCK_XTAL_DIVISOR_1_0_8814B))
+#define BIT_GET_LCK_XTAL_DIVISOR_1_0_8814B(x) \
+ (((x) >> BIT_SHIFT_LCK_XTAL_DIVISOR_1_0_8814B) & \
+ BIT_MASK_LCK_XTAL_DIVISOR_1_0_8814B)
+#define BIT_SET_LCK_XTAL_DIVISOR_1_0_8814B(x, v) \
+ (BIT_CLEAR_LCK_XTAL_DIVISOR_1_0_8814B(x) | \
+ BIT_LCK_XTAL_DIVISOR_1_0_8814B(v))
+
+/* 2 REG_ANAPAR_MAC_5_8814B */
+
+#define BIT_SHIFT_LS_XTAL_SEL_3_0_8814B 0
+#define BIT_MASK_LS_XTAL_SEL_3_0_8814B 0xf
+#define BIT_LS_XTAL_SEL_3_0_8814B(x) \
+ (((x) & BIT_MASK_LS_XTAL_SEL_3_0_8814B) \
+ << BIT_SHIFT_LS_XTAL_SEL_3_0_8814B)
+#define BITS_LS_XTAL_SEL_3_0_8814B \
+ (BIT_MASK_LS_XTAL_SEL_3_0_8814B << BIT_SHIFT_LS_XTAL_SEL_3_0_8814B)
+#define BIT_CLEAR_LS_XTAL_SEL_3_0_8814B(x) ((x) & (~BITS_LS_XTAL_SEL_3_0_8814B))
+#define BIT_GET_LS_XTAL_SEL_3_0_8814B(x) \
+ (((x) >> BIT_SHIFT_LS_XTAL_SEL_3_0_8814B) & \
+ BIT_MASK_LS_XTAL_SEL_3_0_8814B)
+#define BIT_SET_LS_XTAL_SEL_3_0_8814B(x, v) \
+ (BIT_CLEAR_LS_XTAL_SEL_3_0_8814B(x) | BIT_LS_XTAL_SEL_3_0_8814B(v))
+
+/* 2 REG_ANAPAR_MAC_6_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_ANAPAR_MAC_7_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_ANAPAR_MAC_8_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_ANAPAR_XTAL_0_8814B */
+#define BIT_XTAL_DRV_RF1_0_8814B BIT(31)
+#define BIT_XTAL_GATED_RF1N_8814B BIT(30)
+#define BIT_XTAL_GATED_RF1P_8814B BIT(29)
+#define BIT_XTAL_GM_SEP_V2_8814B BIT(28)
+
+#define BIT_SHIFT_XTAL_LDO_1_0_8814B 26
+#define BIT_MASK_XTAL_LDO_1_0_8814B 0x3
+#define BIT_XTAL_LDO_1_0_8814B(x) \
+ (((x) & BIT_MASK_XTAL_LDO_1_0_8814B) << BIT_SHIFT_XTAL_LDO_1_0_8814B)
+#define BITS_XTAL_LDO_1_0_8814B \
+ (BIT_MASK_XTAL_LDO_1_0_8814B << BIT_SHIFT_XTAL_LDO_1_0_8814B)
+#define BIT_CLEAR_XTAL_LDO_1_0_8814B(x) ((x) & (~BITS_XTAL_LDO_1_0_8814B))
+#define BIT_GET_XTAL_LDO_1_0_8814B(x) \
+ (((x) >> BIT_SHIFT_XTAL_LDO_1_0_8814B) & BIT_MASK_XTAL_LDO_1_0_8814B)
+#define BIT_SET_XTAL_LDO_1_0_8814B(x, v) \
+ (BIT_CLEAR_XTAL_LDO_1_0_8814B(x) | BIT_XTAL_LDO_1_0_8814B(v))
+
+#define BIT_XQSEL_V1_8814B BIT(25)
+#define BIT_GATED_XTAL_OK0_8814B BIT(24)
+
+#define BIT_SHIFT_XTAL_SC_XO_6_0_8814B 17
+#define BIT_MASK_XTAL_SC_XO_6_0_8814B 0x7f
+#define BIT_XTAL_SC_XO_6_0_8814B(x) \
+ (((x) & BIT_MASK_XTAL_SC_XO_6_0_8814B) \
+ << BIT_SHIFT_XTAL_SC_XO_6_0_8814B)
+#define BITS_XTAL_SC_XO_6_0_8814B \
+ (BIT_MASK_XTAL_SC_XO_6_0_8814B << BIT_SHIFT_XTAL_SC_XO_6_0_8814B)
+#define BIT_CLEAR_XTAL_SC_XO_6_0_8814B(x) ((x) & (~BITS_XTAL_SC_XO_6_0_8814B))
+#define BIT_GET_XTAL_SC_XO_6_0_8814B(x) \
+ (((x) >> BIT_SHIFT_XTAL_SC_XO_6_0_8814B) & \
+ BIT_MASK_XTAL_SC_XO_6_0_8814B)
+#define BIT_SET_XTAL_SC_XO_6_0_8814B(x, v) \
+ (BIT_CLEAR_XTAL_SC_XO_6_0_8814B(x) | BIT_XTAL_SC_XO_6_0_8814B(v))
+
+#define BIT_SHIFT_XTAL_SC_XI_6_0_8814B 10
+#define BIT_MASK_XTAL_SC_XI_6_0_8814B 0x7f
+#define BIT_XTAL_SC_XI_6_0_8814B(x) \
+ (((x) & BIT_MASK_XTAL_SC_XI_6_0_8814B) \
+ << BIT_SHIFT_XTAL_SC_XI_6_0_8814B)
+#define BITS_XTAL_SC_XI_6_0_8814B \
+ (BIT_MASK_XTAL_SC_XI_6_0_8814B << BIT_SHIFT_XTAL_SC_XI_6_0_8814B)
+#define BIT_CLEAR_XTAL_SC_XI_6_0_8814B(x) ((x) & (~BITS_XTAL_SC_XI_6_0_8814B))
+#define BIT_GET_XTAL_SC_XI_6_0_8814B(x) \
+ (((x) >> BIT_SHIFT_XTAL_SC_XI_6_0_8814B) & \
+ BIT_MASK_XTAL_SC_XI_6_0_8814B)
+#define BIT_SET_XTAL_SC_XI_6_0_8814B(x, v) \
+ (BIT_CLEAR_XTAL_SC_XI_6_0_8814B(x) | BIT_XTAL_SC_XI_6_0_8814B(v))
+
+#define BIT_SHIFT_XTAL_GMN_4_0_8814B 5
+#define BIT_MASK_XTAL_GMN_4_0_8814B 0x1f
+#define BIT_XTAL_GMN_4_0_8814B(x) \
+ (((x) & BIT_MASK_XTAL_GMN_4_0_8814B) << BIT_SHIFT_XTAL_GMN_4_0_8814B)
+#define BITS_XTAL_GMN_4_0_8814B \
+ (BIT_MASK_XTAL_GMN_4_0_8814B << BIT_SHIFT_XTAL_GMN_4_0_8814B)
+#define BIT_CLEAR_XTAL_GMN_4_0_8814B(x) ((x) & (~BITS_XTAL_GMN_4_0_8814B))
+#define BIT_GET_XTAL_GMN_4_0_8814B(x) \
+ (((x) >> BIT_SHIFT_XTAL_GMN_4_0_8814B) & BIT_MASK_XTAL_GMN_4_0_8814B)
+#define BIT_SET_XTAL_GMN_4_0_8814B(x, v) \
+ (BIT_CLEAR_XTAL_GMN_4_0_8814B(x) | BIT_XTAL_GMN_4_0_8814B(v))
+
+#define BIT_SHIFT_XTAL_GMP_4_0_8814B 0
+#define BIT_MASK_XTAL_GMP_4_0_8814B 0x1f
+#define BIT_XTAL_GMP_4_0_8814B(x) \
+ (((x) & BIT_MASK_XTAL_GMP_4_0_8814B) << BIT_SHIFT_XTAL_GMP_4_0_8814B)
+#define BITS_XTAL_GMP_4_0_8814B \
+ (BIT_MASK_XTAL_GMP_4_0_8814B << BIT_SHIFT_XTAL_GMP_4_0_8814B)
+#define BIT_CLEAR_XTAL_GMP_4_0_8814B(x) ((x) & (~BITS_XTAL_GMP_4_0_8814B))
+#define BIT_GET_XTAL_GMP_4_0_8814B(x) \
+ (((x) >> BIT_SHIFT_XTAL_GMP_4_0_8814B) & BIT_MASK_XTAL_GMP_4_0_8814B)
+#define BIT_SET_XTAL_GMP_4_0_8814B(x, v) \
+ (BIT_CLEAR_XTAL_GMP_4_0_8814B(x) | BIT_XTAL_GMP_4_0_8814B(v))
+
+/* 2 REG_ANAPAR_XTAL_1_8814B */
+
+#define BIT_SHIFT_XTAL_LDO_OK_1_0_8814B 30
+#define BIT_MASK_XTAL_LDO_OK_1_0_8814B 0x3
+#define BIT_XTAL_LDO_OK_1_0_8814B(x) \
+ (((x) & BIT_MASK_XTAL_LDO_OK_1_0_8814B) \
+ << BIT_SHIFT_XTAL_LDO_OK_1_0_8814B)
+#define BITS_XTAL_LDO_OK_1_0_8814B \
+ (BIT_MASK_XTAL_LDO_OK_1_0_8814B << BIT_SHIFT_XTAL_LDO_OK_1_0_8814B)
+#define BIT_CLEAR_XTAL_LDO_OK_1_0_8814B(x) ((x) & (~BITS_XTAL_LDO_OK_1_0_8814B))
+#define BIT_GET_XTAL_LDO_OK_1_0_8814B(x) \
+ (((x) >> BIT_SHIFT_XTAL_LDO_OK_1_0_8814B) & \
+ BIT_MASK_XTAL_LDO_OK_1_0_8814B)
+#define BIT_SET_XTAL_LDO_OK_1_0_8814B(x, v) \
+ (BIT_CLEAR_XTAL_LDO_OK_1_0_8814B(x) | BIT_XTAL_LDO_OK_1_0_8814B(v))
+
+#define BIT_SHIFT_XTAL_XORES_SEL_2_0_8814B 27
+#define BIT_MASK_XTAL_XORES_SEL_2_0_8814B 0x7
+#define BIT_XTAL_XORES_SEL_2_0_8814B(x) \
+ (((x) & BIT_MASK_XTAL_XORES_SEL_2_0_8814B) \
+ << BIT_SHIFT_XTAL_XORES_SEL_2_0_8814B)
+#define BITS_XTAL_XORES_SEL_2_0_8814B \
+ (BIT_MASK_XTAL_XORES_SEL_2_0_8814B \
+ << BIT_SHIFT_XTAL_XORES_SEL_2_0_8814B)
+#define BIT_CLEAR_XTAL_XORES_SEL_2_0_8814B(x) \
+ ((x) & (~BITS_XTAL_XORES_SEL_2_0_8814B))
+#define BIT_GET_XTAL_XORES_SEL_2_0_8814B(x) \
+ (((x) >> BIT_SHIFT_XTAL_XORES_SEL_2_0_8814B) & \
+ BIT_MASK_XTAL_XORES_SEL_2_0_8814B)
+#define BIT_SET_XTAL_XORES_SEL_2_0_8814B(x, v) \
+ (BIT_CLEAR_XTAL_XORES_SEL_2_0_8814B(x) | \
+ BIT_XTAL_XORES_SEL_2_0_8814B(v))
+
+#define BIT_SHIFT_XTAL_AAC_PK_SEL_1_0_8814B 25
+#define BIT_MASK_XTAL_AAC_PK_SEL_1_0_8814B 0x3
+#define BIT_XTAL_AAC_PK_SEL_1_0_8814B(x) \
+ (((x) & BIT_MASK_XTAL_AAC_PK_SEL_1_0_8814B) \
+ << BIT_SHIFT_XTAL_AAC_PK_SEL_1_0_8814B)
+#define BITS_XTAL_AAC_PK_SEL_1_0_8814B \
+ (BIT_MASK_XTAL_AAC_PK_SEL_1_0_8814B \
+ << BIT_SHIFT_XTAL_AAC_PK_SEL_1_0_8814B)
+#define BIT_CLEAR_XTAL_AAC_PK_SEL_1_0_8814B(x) \
+ ((x) & (~BITS_XTAL_AAC_PK_SEL_1_0_8814B))
+#define BIT_GET_XTAL_AAC_PK_SEL_1_0_8814B(x) \
+ (((x) >> BIT_SHIFT_XTAL_AAC_PK_SEL_1_0_8814B) & \
+ BIT_MASK_XTAL_AAC_PK_SEL_1_0_8814B)
+#define BIT_SET_XTAL_AAC_PK_SEL_1_0_8814B(x, v) \
+ (BIT_CLEAR_XTAL_AAC_PK_SEL_1_0_8814B(x) | \
+ BIT_XTAL_AAC_PK_SEL_1_0_8814B(v))
+
+#define BIT_EN_XTAL_AAC_PKDET_8814B BIT(24)
+#define BIT_EN_XTAL_AAC_GM_8814B BIT(23)
+#define BIT_XTAL_LPMODE_8814B BIT(22)
+
+#define BIT_SHIFT_XTAL_SEL_TOK_2_0_8814B 19
+#define BIT_MASK_XTAL_SEL_TOK_2_0_8814B 0x7
+#define BIT_XTAL_SEL_TOK_2_0_8814B(x) \
+ (((x) & BIT_MASK_XTAL_SEL_TOK_2_0_8814B) \
+ << BIT_SHIFT_XTAL_SEL_TOK_2_0_8814B)
+#define BITS_XTAL_SEL_TOK_2_0_8814B \
+ (BIT_MASK_XTAL_SEL_TOK_2_0_8814B << BIT_SHIFT_XTAL_SEL_TOK_2_0_8814B)
+#define BIT_CLEAR_XTAL_SEL_TOK_2_0_8814B(x) \
+ ((x) & (~BITS_XTAL_SEL_TOK_2_0_8814B))
+#define BIT_GET_XTAL_SEL_TOK_2_0_8814B(x) \
+ (((x) >> BIT_SHIFT_XTAL_SEL_TOK_2_0_8814B) & \
+ BIT_MASK_XTAL_SEL_TOK_2_0_8814B)
+#define BIT_SET_XTAL_SEL_TOK_2_0_8814B(x, v) \
+ (BIT_CLEAR_XTAL_SEL_TOK_2_0_8814B(x) | BIT_XTAL_SEL_TOK_2_0_8814B(v))
+
+#define BIT_XQSEL_RF_AWAKE_V2_8814B BIT(18)
+#define BIT_XQSEL_RF_INITIAL_V2_8814B BIT(17)
+#define BIT_XTAL_DELAY_USB_V1_8814B BIT(16)
+#define BIT_XTAL_DELAY_DIGI_V1_8814B BIT(15)
+#define BIT_XTAL_DELAY_AFE_V1_8814B BIT(14)
+#define BIT_XTAL_DRV_RF_LATCH_V3_8814B BIT(13)
+
+#define BIT_SHIFT_XTAL_DRV_DIGI_1_0_8814B 11
+#define BIT_MASK_XTAL_DRV_DIGI_1_0_8814B 0x3
+#define BIT_XTAL_DRV_DIGI_1_0_8814B(x) \
+ (((x) & BIT_MASK_XTAL_DRV_DIGI_1_0_8814B) \
+ << BIT_SHIFT_XTAL_DRV_DIGI_1_0_8814B)
+#define BITS_XTAL_DRV_DIGI_1_0_8814B \
+ (BIT_MASK_XTAL_DRV_DIGI_1_0_8814B << BIT_SHIFT_XTAL_DRV_DIGI_1_0_8814B)
+#define BIT_CLEAR_XTAL_DRV_DIGI_1_0_8814B(x) \
+ ((x) & (~BITS_XTAL_DRV_DIGI_1_0_8814B))
+#define BIT_GET_XTAL_DRV_DIGI_1_0_8814B(x) \
+ (((x) >> BIT_SHIFT_XTAL_DRV_DIGI_1_0_8814B) & \
+ BIT_MASK_XTAL_DRV_DIGI_1_0_8814B)
+#define BIT_SET_XTAL_DRV_DIGI_1_0_8814B(x, v) \
+ (BIT_CLEAR_XTAL_DRV_DIGI_1_0_8814B(x) | BIT_XTAL_DRV_DIGI_1_0_8814B(v))
+
+#define BIT_XTAL_GATED_DIGIN_8814B BIT(10)
+#define BIT_XTAL_GATED_DIGIP_8814B BIT(9)
+
+#define BIT_SHIFT_XTAL_DRV_USB_1_0_8814B 7
+#define BIT_MASK_XTAL_DRV_USB_1_0_8814B 0x3
+#define BIT_XTAL_DRV_USB_1_0_8814B(x) \
+ (((x) & BIT_MASK_XTAL_DRV_USB_1_0_8814B) \
+ << BIT_SHIFT_XTAL_DRV_USB_1_0_8814B)
+#define BITS_XTAL_DRV_USB_1_0_8814B \
+ (BIT_MASK_XTAL_DRV_USB_1_0_8814B << BIT_SHIFT_XTAL_DRV_USB_1_0_8814B)
+#define BIT_CLEAR_XTAL_DRV_USB_1_0_8814B(x) \
+ ((x) & (~BITS_XTAL_DRV_USB_1_0_8814B))
+#define BIT_GET_XTAL_DRV_USB_1_0_8814B(x) \
+ (((x) >> BIT_SHIFT_XTAL_DRV_USB_1_0_8814B) & \
+ BIT_MASK_XTAL_DRV_USB_1_0_8814B)
+#define BIT_SET_XTAL_DRV_USB_1_0_8814B(x, v) \
+ (BIT_CLEAR_XTAL_DRV_USB_1_0_8814B(x) | BIT_XTAL_DRV_USB_1_0_8814B(v))
+
+#define BIT_XTAL_GATED_USBN_8814B BIT(6)
+#define BIT_XTAL_GATED_USBP_8814B BIT(5)
+
+#define BIT_SHIFT_XTAL_DRV_AFE_1_0_8814B 3
+#define BIT_MASK_XTAL_DRV_AFE_1_0_8814B 0x3
+#define BIT_XTAL_DRV_AFE_1_0_8814B(x) \
+ (((x) & BIT_MASK_XTAL_DRV_AFE_1_0_8814B) \
+ << BIT_SHIFT_XTAL_DRV_AFE_1_0_8814B)
+#define BITS_XTAL_DRV_AFE_1_0_8814B \
+ (BIT_MASK_XTAL_DRV_AFE_1_0_8814B << BIT_SHIFT_XTAL_DRV_AFE_1_0_8814B)
+#define BIT_CLEAR_XTAL_DRV_AFE_1_0_8814B(x) \
+ ((x) & (~BITS_XTAL_DRV_AFE_1_0_8814B))
+#define BIT_GET_XTAL_DRV_AFE_1_0_8814B(x) \
+ (((x) >> BIT_SHIFT_XTAL_DRV_AFE_1_0_8814B) & \
+ BIT_MASK_XTAL_DRV_AFE_1_0_8814B)
+#define BIT_SET_XTAL_DRV_AFE_1_0_8814B(x, v) \
+ (BIT_CLEAR_XTAL_DRV_AFE_1_0_8814B(x) | BIT_XTAL_DRV_AFE_1_0_8814B(v))
+
+#define BIT_XTAL_GATED_AFEN_8814B BIT(2)
+#define BIT_XTAL_GATED_AFEP_8814B BIT(1)
+#define BIT_XTAL_DRV_RF1_1_8814B BIT(0)
+
+/* 2 REG_ANAPAR_XTAL_2_8814B */
+#define BIT_XTAL_DRV_RF2_LATCH_8814B BIT(6)
+
+#define BIT_SHIFT_XTAL_DRV_RF2_1_0_8814B 4
+#define BIT_MASK_XTAL_DRV_RF2_1_0_8814B 0x3
+#define BIT_XTAL_DRV_RF2_1_0_8814B(x) \
+ (((x) & BIT_MASK_XTAL_DRV_RF2_1_0_8814B) \
+ << BIT_SHIFT_XTAL_DRV_RF2_1_0_8814B)
+#define BITS_XTAL_DRV_RF2_1_0_8814B \
+ (BIT_MASK_XTAL_DRV_RF2_1_0_8814B << BIT_SHIFT_XTAL_DRV_RF2_1_0_8814B)
+#define BIT_CLEAR_XTAL_DRV_RF2_1_0_8814B(x) \
+ ((x) & (~BITS_XTAL_DRV_RF2_1_0_8814B))
+#define BIT_GET_XTAL_DRV_RF2_1_0_8814B(x) \
+ (((x) >> BIT_SHIFT_XTAL_DRV_RF2_1_0_8814B) & \
+ BIT_MASK_XTAL_DRV_RF2_1_0_8814B)
+#define BIT_SET_XTAL_DRV_RF2_1_0_8814B(x, v) \
+ (BIT_CLEAR_XTAL_DRV_RF2_1_0_8814B(x) | BIT_XTAL_DRV_RF2_1_0_8814B(v))
+
+#define BIT_XTAL_GATED_RF2N_8814B BIT(3)
+#define BIT_XTAL_GATED_RF2P_8814B BIT(2)
+#define BIT_XTAL_LDO_DI_8814B BIT(1)
+#define BIT_XTAL_SEL_PWR_8814B BIT(0)
+
+/* 2 REG_ANAPAR_XTAL_AAC_8814B */
+#define BIT_EN_XTAL_AAC_TRIG_8814B BIT(28)
+#define BIT_EN_XTAL_AAC_8814B BIT(27)
+#define BIT_EN_XTAL_AAC_DIGI_8814B BIT(26)
+
+#define BIT_SHIFT_GM_MANUAL_4_0_8814B 21
+#define BIT_MASK_GM_MANUAL_4_0_8814B 0x1f
+#define BIT_GM_MANUAL_4_0_8814B(x) \
+ (((x) & BIT_MASK_GM_MANUAL_4_0_8814B) << BIT_SHIFT_GM_MANUAL_4_0_8814B)
+#define BITS_GM_MANUAL_4_0_8814B \
+ (BIT_MASK_GM_MANUAL_4_0_8814B << BIT_SHIFT_GM_MANUAL_4_0_8814B)
+#define BIT_CLEAR_GM_MANUAL_4_0_8814B(x) ((x) & (~BITS_GM_MANUAL_4_0_8814B))
+#define BIT_GET_GM_MANUAL_4_0_8814B(x) \
+ (((x) >> BIT_SHIFT_GM_MANUAL_4_0_8814B) & BIT_MASK_GM_MANUAL_4_0_8814B)
+#define BIT_SET_GM_MANUAL_4_0_8814B(x, v) \
+ (BIT_CLEAR_GM_MANUAL_4_0_8814B(x) | BIT_GM_MANUAL_4_0_8814B(v))
+
+#define BIT_SHIFT_GM_STUP_4_0_8814B 16
+#define BIT_MASK_GM_STUP_4_0_8814B 0x1f
+#define BIT_GM_STUP_4_0_8814B(x) \
+ (((x) & BIT_MASK_GM_STUP_4_0_8814B) << BIT_SHIFT_GM_STUP_4_0_8814B)
+#define BITS_GM_STUP_4_0_8814B \
+ (BIT_MASK_GM_STUP_4_0_8814B << BIT_SHIFT_GM_STUP_4_0_8814B)
+#define BIT_CLEAR_GM_STUP_4_0_8814B(x) ((x) & (~BITS_GM_STUP_4_0_8814B))
+#define BIT_GET_GM_STUP_4_0_8814B(x) \
+ (((x) >> BIT_SHIFT_GM_STUP_4_0_8814B) & BIT_MASK_GM_STUP_4_0_8814B)
+#define BIT_SET_GM_STUP_4_0_8814B(x, v) \
+ (BIT_CLEAR_GM_STUP_4_0_8814B(x) | BIT_GM_STUP_4_0_8814B(v))
+
+#define BIT_SHIFT_XTAL_CK_SET_2_0_8814B 13
+#define BIT_MASK_XTAL_CK_SET_2_0_8814B 0x7
+#define BIT_XTAL_CK_SET_2_0_8814B(x) \
+ (((x) & BIT_MASK_XTAL_CK_SET_2_0_8814B) \
+ << BIT_SHIFT_XTAL_CK_SET_2_0_8814B)
+#define BITS_XTAL_CK_SET_2_0_8814B \
+ (BIT_MASK_XTAL_CK_SET_2_0_8814B << BIT_SHIFT_XTAL_CK_SET_2_0_8814B)
+#define BIT_CLEAR_XTAL_CK_SET_2_0_8814B(x) ((x) & (~BITS_XTAL_CK_SET_2_0_8814B))
+#define BIT_GET_XTAL_CK_SET_2_0_8814B(x) \
+ (((x) >> BIT_SHIFT_XTAL_CK_SET_2_0_8814B) & \
+ BIT_MASK_XTAL_CK_SET_2_0_8814B)
+#define BIT_SET_XTAL_CK_SET_2_0_8814B(x, v) \
+ (BIT_CLEAR_XTAL_CK_SET_2_0_8814B(x) | BIT_XTAL_CK_SET_2_0_8814B(v))
+
+#define BIT_SHIFT_GM_INIT_4_0_8814B 8
+#define BIT_MASK_GM_INIT_4_0_8814B 0x1f
+#define BIT_GM_INIT_4_0_8814B(x) \
+ (((x) & BIT_MASK_GM_INIT_4_0_8814B) << BIT_SHIFT_GM_INIT_4_0_8814B)
+#define BITS_GM_INIT_4_0_8814B \
+ (BIT_MASK_GM_INIT_4_0_8814B << BIT_SHIFT_GM_INIT_4_0_8814B)
+#define BIT_CLEAR_GM_INIT_4_0_8814B(x) ((x) & (~BITS_GM_INIT_4_0_8814B))
+#define BIT_GET_GM_INIT_4_0_8814B(x) \
+ (((x) >> BIT_SHIFT_GM_INIT_4_0_8814B) & BIT_MASK_GM_INIT_4_0_8814B)
+#define BIT_SET_GM_INIT_4_0_8814B(x, v) \
+ (BIT_CLEAR_GM_INIT_4_0_8814B(x) | BIT_GM_INIT_4_0_8814B(v))
+
+#define BIT_GM_STEP_8814B BIT(7)
+
+#define BIT_SHIFT_XAAC_GM_OFFSET_4_0_8814B 2
+#define BIT_MASK_XAAC_GM_OFFSET_4_0_8814B 0x1f
+#define BIT_XAAC_GM_OFFSET_4_0_8814B(x) \
+ (((x) & BIT_MASK_XAAC_GM_OFFSET_4_0_8814B) \
+ << BIT_SHIFT_XAAC_GM_OFFSET_4_0_8814B)
+#define BITS_XAAC_GM_OFFSET_4_0_8814B \
+ (BIT_MASK_XAAC_GM_OFFSET_4_0_8814B \
+ << BIT_SHIFT_XAAC_GM_OFFSET_4_0_8814B)
+#define BIT_CLEAR_XAAC_GM_OFFSET_4_0_8814B(x) \
+ ((x) & (~BITS_XAAC_GM_OFFSET_4_0_8814B))
+#define BIT_GET_XAAC_GM_OFFSET_4_0_8814B(x) \
+ (((x) >> BIT_SHIFT_XAAC_GM_OFFSET_4_0_8814B) & \
+ BIT_MASK_XAAC_GM_OFFSET_4_0_8814B)
+#define BIT_SET_XAAC_GM_OFFSET_4_0_8814B(x, v) \
+ (BIT_CLEAR_XAAC_GM_OFFSET_4_0_8814B(x) | \
+ BIT_XAAC_GM_OFFSET_4_0_8814B(v))
+
+#define BIT_OFFSET_PLUS_8814B BIT(1)
+#define BIT_RESET_N_8814B BIT(0)
+
+/* 2 REG_ANAPAR_XTAL_R_ONLY_8814B */
+#define BIT_XTAL_PKDET_OUT_8814B BIT(6)
+
+#define BIT_SHIFT_XTAL_GM_AAC_4_0_8814B 1
+#define BIT_MASK_XTAL_GM_AAC_4_0_8814B 0x1f
+#define BIT_XTAL_GM_AAC_4_0_8814B(x) \
+ (((x) & BIT_MASK_XTAL_GM_AAC_4_0_8814B) \
+ << BIT_SHIFT_XTAL_GM_AAC_4_0_8814B)
+#define BITS_XTAL_GM_AAC_4_0_8814B \
+ (BIT_MASK_XTAL_GM_AAC_4_0_8814B << BIT_SHIFT_XTAL_GM_AAC_4_0_8814B)
+#define BIT_CLEAR_XTAL_GM_AAC_4_0_8814B(x) ((x) & (~BITS_XTAL_GM_AAC_4_0_8814B))
+#define BIT_GET_XTAL_GM_AAC_4_0_8814B(x) \
+ (((x) >> BIT_SHIFT_XTAL_GM_AAC_4_0_8814B) & \
+ BIT_MASK_XTAL_GM_AAC_4_0_8814B)
+#define BIT_SET_XTAL_GM_AAC_4_0_8814B(x, v) \
+ (BIT_CLEAR_XTAL_GM_AAC_4_0_8814B(x) | BIT_XTAL_GM_AAC_4_0_8814B(v))
+
+#define BIT_XAAC_READY_8814B BIT(0)
+
+/* 2 REG_CPHY_LDO_8814B */
+
+#define BIT_SHIFT_CPHY_LDO_PD_8814B 12
+#define BIT_MASK_CPHY_LDO_PD_8814B 0x3
+#define BIT_CPHY_LDO_PD_8814B(x) \
+ (((x) & BIT_MASK_CPHY_LDO_PD_8814B) << BIT_SHIFT_CPHY_LDO_PD_8814B)
+#define BITS_CPHY_LDO_PD_8814B \
+ (BIT_MASK_CPHY_LDO_PD_8814B << BIT_SHIFT_CPHY_LDO_PD_8814B)
+#define BIT_CLEAR_CPHY_LDO_PD_8814B(x) ((x) & (~BITS_CPHY_LDO_PD_8814B))
+#define BIT_GET_CPHY_LDO_PD_8814B(x) \
+ (((x) >> BIT_SHIFT_CPHY_LDO_PD_8814B) & BIT_MASK_CPHY_LDO_PD_8814B)
+#define BIT_SET_CPHY_LDO_PD_8814B(x, v) \
+ (BIT_CLEAR_CPHY_LDO_PD_8814B(x) | BIT_CPHY_LDO_PD_8814B(v))
+
+#define BIT_SHIFT_CPHY_LDO_SR_8814B 10
+#define BIT_MASK_CPHY_LDO_SR_8814B 0x3
+#define BIT_CPHY_LDO_SR_8814B(x) \
+ (((x) & BIT_MASK_CPHY_LDO_SR_8814B) << BIT_SHIFT_CPHY_LDO_SR_8814B)
+#define BITS_CPHY_LDO_SR_8814B \
+ (BIT_MASK_CPHY_LDO_SR_8814B << BIT_SHIFT_CPHY_LDO_SR_8814B)
+#define BIT_CLEAR_CPHY_LDO_SR_8814B(x) ((x) & (~BITS_CPHY_LDO_SR_8814B))
+#define BIT_GET_CPHY_LDO_SR_8814B(x) \
+ (((x) >> BIT_SHIFT_CPHY_LDO_SR_8814B) & BIT_MASK_CPHY_LDO_SR_8814B)
+#define BIT_SET_CPHY_LDO_SR_8814B(x, v) \
+ (BIT_CLEAR_CPHY_LDO_SR_8814B(x) | BIT_CPHY_LDO_SR_8814B(v))
+
+#define BIT_SHIFT_CPHY_LDO_TUNEREF_8814B 8
+#define BIT_MASK_CPHY_LDO_TUNEREF_8814B 0x3
+#define BIT_CPHY_LDO_TUNEREF_8814B(x) \
+ (((x) & BIT_MASK_CPHY_LDO_TUNEREF_8814B) \
+ << BIT_SHIFT_CPHY_LDO_TUNEREF_8814B)
+#define BITS_CPHY_LDO_TUNEREF_8814B \
+ (BIT_MASK_CPHY_LDO_TUNEREF_8814B << BIT_SHIFT_CPHY_LDO_TUNEREF_8814B)
+#define BIT_CLEAR_CPHY_LDO_TUNEREF_8814B(x) \
+ ((x) & (~BITS_CPHY_LDO_TUNEREF_8814B))
+#define BIT_GET_CPHY_LDO_TUNEREF_8814B(x) \
+ (((x) >> BIT_SHIFT_CPHY_LDO_TUNEREF_8814B) & \
+ BIT_MASK_CPHY_LDO_TUNEREF_8814B)
+#define BIT_SET_CPHY_LDO_TUNEREF_8814B(x, v) \
+ (BIT_CLEAR_CPHY_LDO_TUNEREF_8814B(x) | BIT_CPHY_LDO_TUNEREF_8814B(v))
+
+#define BIT_SHIFT_CPHY_LDO_TUNE_VO_8814B 5
+#define BIT_MASK_CPHY_LDO_TUNE_VO_8814B 0x7
+#define BIT_CPHY_LDO_TUNE_VO_8814B(x) \
+ (((x) & BIT_MASK_CPHY_LDO_TUNE_VO_8814B) \
+ << BIT_SHIFT_CPHY_LDO_TUNE_VO_8814B)
+#define BITS_CPHY_LDO_TUNE_VO_8814B \
+ (BIT_MASK_CPHY_LDO_TUNE_VO_8814B << BIT_SHIFT_CPHY_LDO_TUNE_VO_8814B)
+#define BIT_CLEAR_CPHY_LDO_TUNE_VO_8814B(x) \
+ ((x) & (~BITS_CPHY_LDO_TUNE_VO_8814B))
+#define BIT_GET_CPHY_LDO_TUNE_VO_8814B(x) \
+ (((x) >> BIT_SHIFT_CPHY_LDO_TUNE_VO_8814B) & \
+ BIT_MASK_CPHY_LDO_TUNE_VO_8814B)
+#define BIT_SET_CPHY_LDO_TUNE_VO_8814B(x, v) \
+ (BIT_CLEAR_CPHY_LDO_TUNE_VO_8814B(x) | BIT_CPHY_LDO_TUNE_VO_8814B(v))
+
+#define BIT_SHIFT_CPHY_LDO_OCP_VTH_8814B 2
+#define BIT_MASK_CPHY_LDO_OCP_VTH_8814B 0x7
+#define BIT_CPHY_LDO_OCP_VTH_8814B(x) \
+ (((x) & BIT_MASK_CPHY_LDO_OCP_VTH_8814B) \
+ << BIT_SHIFT_CPHY_LDO_OCP_VTH_8814B)
+#define BITS_CPHY_LDO_OCP_VTH_8814B \
+ (BIT_MASK_CPHY_LDO_OCP_VTH_8814B << BIT_SHIFT_CPHY_LDO_OCP_VTH_8814B)
+#define BIT_CLEAR_CPHY_LDO_OCP_VTH_8814B(x) \
+ ((x) & (~BITS_CPHY_LDO_OCP_VTH_8814B))
+#define BIT_GET_CPHY_LDO_OCP_VTH_8814B(x) \
+ (((x) >> BIT_SHIFT_CPHY_LDO_OCP_VTH_8814B) & \
+ BIT_MASK_CPHY_LDO_OCP_VTH_8814B)
+#define BIT_SET_CPHY_LDO_OCP_VTH_8814B(x, v) \
+ (BIT_CLEAR_CPHY_LDO_OCP_VTH_8814B(x) | BIT_CPHY_LDO_OCP_VTH_8814B(v))
+
+#define BIT_SHIFT_VREF_LDO_OK_8814B 0
+#define BIT_MASK_VREF_LDO_OK_8814B 0x3
+#define BIT_VREF_LDO_OK_8814B(x) \
+ (((x) & BIT_MASK_VREF_LDO_OK_8814B) << BIT_SHIFT_VREF_LDO_OK_8814B)
+#define BITS_VREF_LDO_OK_8814B \
+ (BIT_MASK_VREF_LDO_OK_8814B << BIT_SHIFT_VREF_LDO_OK_8814B)
+#define BIT_CLEAR_VREF_LDO_OK_8814B(x) ((x) & (~BITS_VREF_LDO_OK_8814B))
+#define BIT_GET_VREF_LDO_OK_8814B(x) \
+ (((x) >> BIT_SHIFT_VREF_LDO_OK_8814B) & BIT_MASK_VREF_LDO_OK_8814B)
+#define BIT_SET_VREF_LDO_OK_8814B(x, v) \
+ (BIT_CLEAR_VREF_LDO_OK_8814B(x) | BIT_VREF_LDO_OK_8814B(v))
+
+/* 2 REG_CPHY_BG_8814B */
+
+#define BIT_SHIFT_BG_8814B 0
+#define BIT_MASK_BG_8814B 0x7
+#define BIT_BG_8814B(x) (((x) & BIT_MASK_BG_8814B) << BIT_SHIFT_BG_8814B)
+#define BITS_BG_8814B (BIT_MASK_BG_8814B << BIT_SHIFT_BG_8814B)
+#define BIT_CLEAR_BG_8814B(x) ((x) & (~BITS_BG_8814B))
+#define BIT_GET_BG_8814B(x) (((x) >> BIT_SHIFT_BG_8814B) & BIT_MASK_BG_8814B)
+#define BIT_SET_BG_8814B(x, v) (BIT_CLEAR_BG_8814B(x) | BIT_BG_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_HIMR_4_8814B */
+#define BIT_TXBCN_OK_PORT4_8814B BIT(31)
+#define BIT_TXBCN_OK_PORT3_8814B BIT(30)
+#define BIT_TXBCN_OK_PORT2_8814B BIT(29)
+#define BIT_TXBCN_OK_PORT1_8814B BIT(28)
+#define BIT_TXBCN15OK_8814B BIT(23)
+#define BIT_TXBCN14OK_8814B BIT(22)
+#define BIT_TXBCN13OK_8814B BIT(21)
+#define BIT_TXBCN12OK_8814B BIT(20)
+#define BIT_TXBCN11OK_8814B BIT(19)
+#define BIT_TXBCN10OK_8814B BIT(18)
+#define BIT_TXBCN9OK_8814B BIT(17)
+#define BIT_TXBCN8OK_8814B BIT(16)
+#define BIT_BCNDERR_PORT4_8814B BIT(15)
+#define BIT_BCNDERR_PORT3_8814B BIT(14)
+#define BIT_BCNDERR_PORT2_8814B BIT(13)
+#define BIT_BCNDERR_PORT1_8814B BIT(12)
+#define BIT_TXBCN15ERR_8814B BIT(7)
+#define BIT_TXBCN14ERR_8814B BIT(6)
+#define BIT_TXBCN13ERR_8814B BIT(5)
+#define BIT_TXBCN12ERR_8814B BIT(4)
+#define BIT_TXBCN11ERR_8814B BIT(3)
+#define BIT_TXBCN10ERR_8814B BIT(2)
+#define BIT_TXBCN9ERR_8814B BIT(1)
+#define BIT_TXBCN8ERR_8814B BIT(0)
+
+/* 2 REG_HISR_4_8814B */
+#define BIT_TXBCN_OK_PORT4_8814B BIT(31)
+#define BIT_TXBCN_OK_PORT3_8814B BIT(30)
+#define BIT_TXBCN_OK_PORT2_8814B BIT(29)
+#define BIT_TXBCN_OK_PORT1_8814B BIT(28)
+#define BIT_TXBCN15OK_8814B BIT(23)
+#define BIT_TXBCN14OK_8814B BIT(22)
+#define BIT_TXBCN13OK_8814B BIT(21)
+#define BIT_TXBCN12OK_8814B BIT(20)
+#define BIT_TXBCN11OK_8814B BIT(19)
+#define BIT_TXBCN10OK_8814B BIT(18)
+#define BIT_TXBCN9OK_8814B BIT(17)
+#define BIT_TXBCN8OK_8814B BIT(16)
+#define BIT_BCNDERR_PORT4_8814B BIT(15)
+#define BIT_BCNDERR_PORT3_8814B BIT(14)
+#define BIT_BCNDERR_PORT2_8814B BIT(13)
+#define BIT_BCNDERR_PORT1_8814B BIT(12)
+#define BIT_TXBCN15ERR_8814B BIT(7)
+#define BIT_TXBCN14ERR_8814B BIT(6)
+#define BIT_TXBCN13ERR_8814B BIT(5)
+#define BIT_TXBCN12ERR_8814B BIT(4)
+#define BIT_TXBCN11ERR_8814B BIT(3)
+#define BIT_TXBCN10ERR_8814B BIT(2)
+#define BIT_TXBCN9ERR_8814B BIT(1)
+#define BIT_TXBCN8ERR_8814B BIT(0)
+
+/* 2 REG_HIMR_5_8814B */
+#define BIT_BCNDMAINT15_8814B BIT(23)
+#define BIT_BCNDMAINT14_8814B BIT(22)
+#define BIT_BCNDMAINT13_8814B BIT(21)
+#define BIT_BCNDMAINT12_8814B BIT(20)
+#define BIT_BCNDMAINT11_8814B BIT(19)
+#define BIT_BCNDMAINT10_8814B BIT(18)
+#define BIT_BCNDMAINT9_8814B BIT(17)
+#define BIT_BCNDMAINT8_8814B BIT(16)
+#define BIT_BCNDERR_PORT4_8814B BIT(15)
+#define BIT_BCNDERR_PORT3_8814B BIT(14)
+#define BIT_BCNDERR_PORT2_8814B BIT(13)
+#define BIT_BCNDERR_PORT1_8814B BIT(12)
+#define BIT_BCNDERR15_8814B BIT(7)
+#define BIT_BCNDERR14_8814B BIT(6)
+#define BIT_BCNDERR13_8814B BIT(5)
+#define BIT_BCNDERR12_8814B BIT(4)
+#define BIT_BCNDERR11_8814B BIT(3)
+#define BIT_BCNDERR10_8814B BIT(2)
+#define BIT_BCNDERR9_8814B BIT(1)
+#define BIT_BCNDERR8_8814B BIT(0)
+
+/* 2 REG_HISR_5_8814B */
+#define BIT_BCNDMAINT15_8814B BIT(23)
+#define BIT_BCNDMAINT14_8814B BIT(22)
+#define BIT_BCNDMAINT13_8814B BIT(21)
+#define BIT_BCNDMAINT12_8814B BIT(20)
+#define BIT_BCNDMAINT11_8814B BIT(19)
+#define BIT_BCNDMAINT10_8814B BIT(18)
+#define BIT_BCNDMAINT9_8814B BIT(17)
+#define BIT_BCNDMAINT8_8814B BIT(16)
+#define BIT_BCNDERR_PORT4_8814B BIT(15)
+#define BIT_BCNDERR_PORT3_8814B BIT(14)
+#define BIT_BCNDERR_PORT2_8814B BIT(13)
+#define BIT_BCNDERR_PORT1_8814B BIT(12)
+#define BIT_BCNDERR15_8814B BIT(7)
+#define BIT_BCNDERR14_8814B BIT(6)
+#define BIT_BCNDERR13_8814B BIT(5)
+#define BIT_BCNDERR12_8814B BIT(4)
+#define BIT_BCNDERR11_8814B BIT(3)
+#define BIT_BCNDERR10_8814B BIT(2)
+#define BIT_BCNDERR9_8814B BIT(1)
+#define BIT_BCNDERR8_8814B BIT(0)
+
+/* 2 REG_SYS_CFG5_8814B */
+#define BIT_LPS_STATUS_8814B BIT(3)
+#define BIT_HCI_TXDMA_BUSY_8814B BIT(2)
+#define BIT_HCI_TXDMA_ALLOW_8814B BIT(1)
+#define BIT_FW_CTRL_HCI_TXDMA_EN_8814B BIT(0)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_HIMR_6_8814B */
+#define BIT_ATIMEND_PORT4_8814B BIT(31)
+#define BIT_ATIMEND_PORT3_8814B BIT(30)
+#define BIT_ATIMEND_PORT2_8814B BIT(29)
+#define BIT_ATIMEND_PORT1_8814B BIT(28)
+#define BIT_ATIMEND15_8814B BIT(23)
+#define BIT_ATIMEND14_8814B BIT(22)
+#define BIT_ATIMEND13_8814B BIT(21)
+#define BIT_ATIMEND12_8814B BIT(20)
+#define BIT_ATIMEND11_8814B BIT(19)
+#define BIT_ATIMEND10_8814B BIT(18)
+#define BIT_ATIMEND9_8814B BIT(17)
+#define BIT_ATIMEND8_8814B BIT(16)
+#define BIT_PS_TIMER_EARLY_INT_5_8814B BIT(5)
+#define BIT_PS_TIMER_EARLY_INT_4_8814B BIT(4)
+#define BIT_PS_TIMER_EARLY_INT_3_8814B BIT(3)
+#define BIT_PS_TIMER_EARLY_INT_2_8814B BIT(2)
+#define BIT_PS_TIMER_EARLY_INT_1_8814B BIT(1)
+#define BIT_PS_TIMER_EARLY_INT_0_8814B BIT(0)
+
+/* 2 REG_HISR_6_8814B */
+#define BIT_ATIMEND_PORT4_8814B BIT(31)
+#define BIT_ATIMEND_PORT3_8814B BIT(30)
+#define BIT_ATIMEND_PORT2_8814B BIT(29)
+#define BIT_ATIMEND_PORT1_8814B BIT(28)
+#define BIT_ATIMEND15_8814B BIT(23)
+#define BIT_ATIMEND14_8814B BIT(22)
+#define BIT_ATIMEND13_8814B BIT(21)
+#define BIT_ATIMEND12_8814B BIT(20)
+#define BIT_ATIMEND11_8814B BIT(19)
+#define BIT_ATIMEND10_8814B BIT(18)
+#define BIT_ATIMEND9_8814B BIT(17)
+#define BIT_ATIMEND8_8814B BIT(16)
+#define BIT_PS_TIMER_EARLY_INT_5_8814B BIT(5)
+#define BIT_PS_TIMER_EARLY_INT_4_8814B BIT(4)
+#define BIT_PS_TIMER_EARLY_INT_3_8814B BIT(3)
+#define BIT_PS_TIMER_EARLY_INT_2_8814B BIT(2)
+#define BIT_PS_TIMER_EARLY_INT_1_8814B BIT(1)
+#define BIT_PS_TIMER_EARLY_INT_0_8814B BIT(0)
+
+/* 2 REG_CPU_DMEM_CON_8814B */
+#define BIT_WDT_AUTO_MODE_8814B BIT(22)
+#define BIT_WDT_PLATFORM_EN_8814B BIT(21)
+#define BIT_WDT_CPU_EN_8814B BIT(20)
+#define BIT_WDT_OPT_IOWRAPPER_8814B BIT(19)
+#define BIT_ANA_PORT_IDLE_8814B BIT(18)
+#define BIT_MAC_PORT_IDLE_8814B BIT(17)
+#define BIT_WL_PLATFORM_RST_8814B BIT(16)
+#define BIT_WL_SECURITY_CLK_8814B BIT(15)
+#define BIT_DDMA_EN_8814B BIT(8)
+
+#define BIT_SHIFT_CPU_DMEM_CON_8814B 0
+#define BIT_MASK_CPU_DMEM_CON_8814B 0xff
+#define BIT_CPU_DMEM_CON_8814B(x) \
+ (((x) & BIT_MASK_CPU_DMEM_CON_8814B) << BIT_SHIFT_CPU_DMEM_CON_8814B)
+#define BITS_CPU_DMEM_CON_8814B \
+ (BIT_MASK_CPU_DMEM_CON_8814B << BIT_SHIFT_CPU_DMEM_CON_8814B)
+#define BIT_CLEAR_CPU_DMEM_CON_8814B(x) ((x) & (~BITS_CPU_DMEM_CON_8814B))
+#define BIT_GET_CPU_DMEM_CON_8814B(x) \
+ (((x) >> BIT_SHIFT_CPU_DMEM_CON_8814B) & BIT_MASK_CPU_DMEM_CON_8814B)
+#define BIT_SET_CPU_DMEM_CON_8814B(x, v) \
+ (BIT_CLEAR_CPU_DMEM_CON_8814B(x) | BIT_CPU_DMEM_CON_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_BOOT_REASON_8814B */
+
+#define BIT_SHIFT_BOOT_REASON_V1_8814B 0
+#define BIT_MASK_BOOT_REASON_V1_8814B 0x7
+#define BIT_BOOT_REASON_V1_8814B(x) \
+ (((x) & BIT_MASK_BOOT_REASON_V1_8814B) \
+ << BIT_SHIFT_BOOT_REASON_V1_8814B)
+#define BITS_BOOT_REASON_V1_8814B \
+ (BIT_MASK_BOOT_REASON_V1_8814B << BIT_SHIFT_BOOT_REASON_V1_8814B)
+#define BIT_CLEAR_BOOT_REASON_V1_8814B(x) ((x) & (~BITS_BOOT_REASON_V1_8814B))
+#define BIT_GET_BOOT_REASON_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_BOOT_REASON_V1_8814B) & \
+ BIT_MASK_BOOT_REASON_V1_8814B)
+#define BIT_SET_BOOT_REASON_V1_8814B(x, v) \
+ (BIT_CLEAR_BOOT_REASON_V1_8814B(x) | BIT_BOOT_REASON_V1_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_DATA_CPU_CTL0_8814B */
+#define BIT_DATA_FW_READY_8814B BIT(31)
+#define BIT_WDT_SYS_RST_8814B BIT(13)
+#define BIT_WDT_ENABLE_8814B BIT(12)
+
+#define BIT_SHIFT_BOOT_SEL_8814B 6
+#define BIT_MASK_BOOT_SEL_8814B 0x3
+#define BIT_BOOT_SEL_8814B(x) \
+ (((x) & BIT_MASK_BOOT_SEL_8814B) << BIT_SHIFT_BOOT_SEL_8814B)
+#define BITS_BOOT_SEL_8814B \
+ (BIT_MASK_BOOT_SEL_8814B << BIT_SHIFT_BOOT_SEL_8814B)
+#define BIT_CLEAR_BOOT_SEL_8814B(x) ((x) & (~BITS_BOOT_SEL_8814B))
+#define BIT_GET_BOOT_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_BOOT_SEL_8814B) & BIT_MASK_BOOT_SEL_8814B)
+#define BIT_SET_BOOT_SEL_8814B(x, v) \
+ (BIT_CLEAR_BOOT_SEL_8814B(x) | BIT_BOOT_SEL_8814B(v))
+
+#define BIT_CLK_SEL_8814B BIT(4)
+#define BIT_DATA_PLATFORM_RST_8814B BIT(1)
+#define BIT_DATA_CPU_RST_8814B BIT(0)
+
+/* 2 REG_DATA_CPU_CTL1_8814B */
+#define BIT_HOST_INTERFACE_IO_PATH_8814B BIT(7)
+#define BIT_EN_TXDMA_OFLD_8814B BIT(6)
+#define BIT_EN_RXDMA_OFLD_8814B BIT(5)
+#define BIT_EN_HCI_DMA_TX_8814B BIT(4)
+#define BIT_EN_HCI_DMA_RX_8814B BIT(3)
+#define BIT_EN_AXI_DMA_TX_8814B BIT(2)
+#define BIT_EN_AXI_DMA_RX_8814B BIT(1)
+#define BIT_EN_PKT_ENG_8814B BIT(0)
+
+/* 2 REG_TXDMA_STOP_HIMR_8814B */
+
+#define BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK_8814B 0
+#define BIT_MASK_NTH_TXDMA_STOP_INT_MSK_8814B 0x1ffff
+#define BIT_NTH_TXDMA_STOP_INT_MSK_8814B(x) \
+ (((x) & BIT_MASK_NTH_TXDMA_STOP_INT_MSK_8814B) \
+ << BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK_8814B)
+#define BITS_NTH_TXDMA_STOP_INT_MSK_8814B \
+ (BIT_MASK_NTH_TXDMA_STOP_INT_MSK_8814B \
+ << BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK_8814B)
+#define BIT_CLEAR_NTH_TXDMA_STOP_INT_MSK_8814B(x) \
+ ((x) & (~BITS_NTH_TXDMA_STOP_INT_MSK_8814B))
+#define BIT_GET_NTH_TXDMA_STOP_INT_MSK_8814B(x) \
+ (((x) >> BIT_SHIFT_NTH_TXDMA_STOP_INT_MSK_8814B) & \
+ BIT_MASK_NTH_TXDMA_STOP_INT_MSK_8814B)
+#define BIT_SET_NTH_TXDMA_STOP_INT_MSK_8814B(x, v) \
+ (BIT_CLEAR_NTH_TXDMA_STOP_INT_MSK_8814B(x) | \
+ BIT_NTH_TXDMA_STOP_INT_MSK_8814B(v))
+
+/* 2 REG_TXDMA_STOP_HISR_8814B */
+
+#define BIT_SHIFT_NTH_TXDMA_STOP_INT_8814B 0
+#define BIT_MASK_NTH_TXDMA_STOP_INT_8814B 0x1ffff
+#define BIT_NTH_TXDMA_STOP_INT_8814B(x) \
+ (((x) & BIT_MASK_NTH_TXDMA_STOP_INT_8814B) \
+ << BIT_SHIFT_NTH_TXDMA_STOP_INT_8814B)
+#define BITS_NTH_TXDMA_STOP_INT_8814B \
+ (BIT_MASK_NTH_TXDMA_STOP_INT_8814B \
+ << BIT_SHIFT_NTH_TXDMA_STOP_INT_8814B)
+#define BIT_CLEAR_NTH_TXDMA_STOP_INT_8814B(x) \
+ ((x) & (~BITS_NTH_TXDMA_STOP_INT_8814B))
+#define BIT_GET_NTH_TXDMA_STOP_INT_8814B(x) \
+ (((x) >> BIT_SHIFT_NTH_TXDMA_STOP_INT_8814B) & \
+ BIT_MASK_NTH_TXDMA_STOP_INT_8814B)
+#define BIT_SET_NTH_TXDMA_STOP_INT_8814B(x, v) \
+ (BIT_CLEAR_NTH_TXDMA_STOP_INT_8814B(x) | \
+ BIT_NTH_TXDMA_STOP_INT_8814B(v))
+
+/* 2 REG_TXDMA_START_HIMR_8814B */
+
+#define BIT_SHIFT_NTH_TXDMA_START_INT_MSK_8814B 0
+#define BIT_MASK_NTH_TXDMA_START_INT_MSK_8814B 0x1ffff
+#define BIT_NTH_TXDMA_START_INT_MSK_8814B(x) \
+ (((x) & BIT_MASK_NTH_TXDMA_START_INT_MSK_8814B) \
+ << BIT_SHIFT_NTH_TXDMA_START_INT_MSK_8814B)
+#define BITS_NTH_TXDMA_START_INT_MSK_8814B \
+ (BIT_MASK_NTH_TXDMA_START_INT_MSK_8814B \
+ << BIT_SHIFT_NTH_TXDMA_START_INT_MSK_8814B)
+#define BIT_CLEAR_NTH_TXDMA_START_INT_MSK_8814B(x) \
+ ((x) & (~BITS_NTH_TXDMA_START_INT_MSK_8814B))
+#define BIT_GET_NTH_TXDMA_START_INT_MSK_8814B(x) \
+ (((x) >> BIT_SHIFT_NTH_TXDMA_START_INT_MSK_8814B) & \
+ BIT_MASK_NTH_TXDMA_START_INT_MSK_8814B)
+#define BIT_SET_NTH_TXDMA_START_INT_MSK_8814B(x, v) \
+ (BIT_CLEAR_NTH_TXDMA_START_INT_MSK_8814B(x) | \
+ BIT_NTH_TXDMA_START_INT_MSK_8814B(v))
+
+/* 2 REG_TXDMA_START_HISR_8814B */
+
+#define BIT_SHIFT_NTH_TXDMA_START_INT_8814B 0
+#define BIT_MASK_NTH_TXDMA_START_INT_8814B 0x1ffff
+#define BIT_NTH_TXDMA_START_INT_8814B(x) \
+ (((x) & BIT_MASK_NTH_TXDMA_START_INT_8814B) \
+ << BIT_SHIFT_NTH_TXDMA_START_INT_8814B)
+#define BITS_NTH_TXDMA_START_INT_8814B \
+ (BIT_MASK_NTH_TXDMA_START_INT_8814B \
+ << BIT_SHIFT_NTH_TXDMA_START_INT_8814B)
+#define BIT_CLEAR_NTH_TXDMA_START_INT_8814B(x) \
+ ((x) & (~BITS_NTH_TXDMA_START_INT_8814B))
+#define BIT_GET_NTH_TXDMA_START_INT_8814B(x) \
+ (((x) >> BIT_SHIFT_NTH_TXDMA_START_INT_8814B) & \
+ BIT_MASK_NTH_TXDMA_START_INT_8814B)
+#define BIT_SET_NTH_TXDMA_START_INT_8814B(x, v) \
+ (BIT_CLEAR_NTH_TXDMA_START_INT_8814B(x) | \
+ BIT_NTH_TXDMA_START_INT_8814B(v))
+
+/* 2 REG_NFCPAD_CTRL_8814B */
+#define BIT_PAD_SHUTDW_8814B BIT(18)
+#define BIT_SYSON_NFC_PAD_8814B BIT(17)
+#define BIT_NFC_INT_PAD_CTRL_8814B BIT(16)
+#define BIT_NFC_RFDIS_PAD_CTRL_8814B BIT(15)
+#define BIT_NFC_CLK_PAD_CTRL_8814B BIT(14)
+#define BIT_NFC_DATA_PAD_CTRL_8814B BIT(13)
+#define BIT_NFC_PAD_PULL_CTRL_8814B BIT(12)
+
+#define BIT_SHIFT_NFCPAD_IO_SEL_8814B 8
+#define BIT_MASK_NFCPAD_IO_SEL_8814B 0xf
+#define BIT_NFCPAD_IO_SEL_8814B(x) \
+ (((x) & BIT_MASK_NFCPAD_IO_SEL_8814B) << BIT_SHIFT_NFCPAD_IO_SEL_8814B)
+#define BITS_NFCPAD_IO_SEL_8814B \
+ (BIT_MASK_NFCPAD_IO_SEL_8814B << BIT_SHIFT_NFCPAD_IO_SEL_8814B)
+#define BIT_CLEAR_NFCPAD_IO_SEL_8814B(x) ((x) & (~BITS_NFCPAD_IO_SEL_8814B))
+#define BIT_GET_NFCPAD_IO_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_NFCPAD_IO_SEL_8814B) & BIT_MASK_NFCPAD_IO_SEL_8814B)
+#define BIT_SET_NFCPAD_IO_SEL_8814B(x, v) \
+ (BIT_CLEAR_NFCPAD_IO_SEL_8814B(x) | BIT_NFCPAD_IO_SEL_8814B(v))
+
+#define BIT_SHIFT_NFCPAD_OUT_8814B 4
+#define BIT_MASK_NFCPAD_OUT_8814B 0xf
+#define BIT_NFCPAD_OUT_8814B(x) \
+ (((x) & BIT_MASK_NFCPAD_OUT_8814B) << BIT_SHIFT_NFCPAD_OUT_8814B)
+#define BITS_NFCPAD_OUT_8814B \
+ (BIT_MASK_NFCPAD_OUT_8814B << BIT_SHIFT_NFCPAD_OUT_8814B)
+#define BIT_CLEAR_NFCPAD_OUT_8814B(x) ((x) & (~BITS_NFCPAD_OUT_8814B))
+#define BIT_GET_NFCPAD_OUT_8814B(x) \
+ (((x) >> BIT_SHIFT_NFCPAD_OUT_8814B) & BIT_MASK_NFCPAD_OUT_8814B)
+#define BIT_SET_NFCPAD_OUT_8814B(x, v) \
+ (BIT_CLEAR_NFCPAD_OUT_8814B(x) | BIT_NFCPAD_OUT_8814B(v))
+
+#define BIT_SHIFT_NFCPAD_IN_8814B 0
+#define BIT_MASK_NFCPAD_IN_8814B 0xf
+#define BIT_NFCPAD_IN_8814B(x) \
+ (((x) & BIT_MASK_NFCPAD_IN_8814B) << BIT_SHIFT_NFCPAD_IN_8814B)
+#define BITS_NFCPAD_IN_8814B \
+ (BIT_MASK_NFCPAD_IN_8814B << BIT_SHIFT_NFCPAD_IN_8814B)
+#define BIT_CLEAR_NFCPAD_IN_8814B(x) ((x) & (~BITS_NFCPAD_IN_8814B))
+#define BIT_GET_NFCPAD_IN_8814B(x) \
+ (((x) >> BIT_SHIFT_NFCPAD_IN_8814B) & BIT_MASK_NFCPAD_IN_8814B)
+#define BIT_SET_NFCPAD_IN_8814B(x, v) \
+ (BIT_CLEAR_NFCPAD_IN_8814B(x) | BIT_NFCPAD_IN_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_HIMR2_8814B */
+#define BIT_BCNDMAINT_P4_MSK_8814B BIT(31)
+#define BIT_BCNDMAINT_P3_MSK_8814B BIT(30)
+#define BIT_BCNDMAINT_P2_MSK_8814B BIT(29)
+#define BIT_BCNDMAINT_P1_MSK_8814B BIT(28)
+#define BIT_SCH_PHY_TXOP_SIFS_INT_MSK_8814B BIT(23)
+#define BIT_ATIMEND7_MSK_8814B BIT(22)
+#define BIT_ATIMEND6_MSK_8814B BIT(21)
+#define BIT_ATIMEND5_MSK_8814B BIT(20)
+#define BIT_ATIMEND4_MSK_8814B BIT(19)
+#define BIT_ATIMEND3_MSK_8814B BIT(18)
+#define BIT_ATIMEND2_MSK_8814B BIT(17)
+#define BIT_ATIMEND1_MSK_8814B BIT(16)
+#define BIT_TXBCN7OK_MSK_8814B BIT(14)
+#define BIT_TXBCN6OK_MSK_8814B BIT(13)
+#define BIT_TXBCN5OK_MSK_8814B BIT(12)
+#define BIT_TXBCN4OK_MSK_8814B BIT(11)
+#define BIT_TXBCN3OK_MSK_8814B BIT(10)
+#define BIT_TXBCN2OK_MSK_8814B BIT(9)
+#define BIT_TXBCN1OK_MSK_V1_8814B BIT(8)
+#define BIT_TXBCN7ERR_MSK_8814B BIT(6)
+#define BIT_TXBCN6ERR_MSK_8814B BIT(5)
+#define BIT_TXBCN5ERR_MSK_8814B BIT(4)
+#define BIT_TXBCN4ERR_MSK_8814B BIT(3)
+#define BIT_TXBCN3ERR_MSK_8814B BIT(2)
+#define BIT_TXBCN2ERR_MSK_8814B BIT(1)
+#define BIT_TXBCN1ERR_MSK_V1_8814B BIT(0)
+
+/* 2 REG_HISR2_8814B */
+#define BIT_BCNDMAINT_P4_8814B BIT(31)
+#define BIT_BCNDMAINT_P3_8814B BIT(30)
+#define BIT_BCNDMAINT_P2_8814B BIT(29)
+#define BIT_BCNDMAINT_P1_8814B BIT(28)
+#define BIT_SCH_PHY_TXOP_SIFS_INT_8814B BIT(23)
+#define BIT_ATIMEND7_8814B BIT(22)
+#define BIT_ATIMEND6_8814B BIT(21)
+#define BIT_ATIMEND5_8814B BIT(20)
+#define BIT_ATIMEND4_8814B BIT(19)
+#define BIT_ATIMEND3_8814B BIT(18)
+#define BIT_ATIMEND2_8814B BIT(17)
+#define BIT_ATIMEND1_8814B BIT(16)
+#define BIT_TXBCN7OK_8814B BIT(14)
+#define BIT_TXBCN6OK_8814B BIT(13)
+#define BIT_TXBCN5OK_8814B BIT(12)
+#define BIT_TXBCN4OK_8814B BIT(11)
+#define BIT_TXBCN3OK_8814B BIT(10)
+#define BIT_TXBCN2OK_8814B BIT(9)
+#define BIT_TXBCN1OK_8814B BIT(8)
+#define BIT_TXBCN7ERR_8814B BIT(6)
+#define BIT_TXBCN6ERR_8814B BIT(5)
+#define BIT_TXBCN5ERR_8814B BIT(4)
+#define BIT_TXBCN4ERR_8814B BIT(3)
+#define BIT_TXBCN3ERR_8814B BIT(2)
+#define BIT_TXBCN2ERR_8814B BIT(1)
+#define BIT_TXBCN1ERR_8814B BIT(0)
+
+/* 2 REG_HIMR3_8814B */
+#define BIT_GTINT12_MSK_8814B BIT(24)
+#define BIT_GTINT11_MSK_8814B BIT(23)
+#define BIT_GTINT10_MSK_8814B BIT(22)
+#define BIT_GTINT9_MSK_8814B BIT(21)
+#define BIT_RX_DESC_BUF_FULL_MSK_8814B BIT(20)
+#define BIT_CPHY_LDO_OCP_DET_INT_MSK_8814B BIT(19)
+#define BIT_WDT_PLATFORM_INT_MSK_8814B BIT(18)
+#define BIT_WDT_CPU_INT_MSK_8814B BIT(17)
+#define BIT_SETH2CDOK_MASK_8814B BIT(16)
+#define BIT_H2C_CMD_FULL_MASK_8814B BIT(15)
+#define BIT_PKT_TRANS_ERR_MASK_8814B BIT(14)
+#define BIT_TXSHORTCUT_TXDESUPDATEOK_MASK_8814B BIT(13)
+#define BIT_TXSHORTCUT_BKUPDATEOK_MASK_8814B BIT(12)
+#define BIT_TXSHORTCUT_BEUPDATEOK_MASK_8814B BIT(11)
+#define BIT_TXSHORTCUT_VIUPDATEOK_MAS_8814B BIT(10)
+#define BIT_TXSHORTCUT_VOUPDATEOK_MASK_8814B BIT(9)
+#define BIT_SEARCH_FAIL_MSK_8814B BIT(8)
+#define BIT_PWR_INT_127TO96_MASK_8814B BIT(7)
+#define BIT_PWR_INT_95TO64_MASK_8814B BIT(6)
+#define BIT_PWR_INT_63TO32_MASK_8814B BIT(5)
+#define BIT_PWR_INT_31TO0_MASK_8814B BIT(4)
+#define BIT_RX_DMA_STUCK_MSK_8814B BIT(3)
+#define BIT_TX_DMA_STUCK_MSK_8814B BIT(2)
+#define BIT_DDMA0_LP_INT_MSK_8814B BIT(1)
+#define BIT_DDMA0_HP_INT_MSK_8814B BIT(0)
+
+/* 2 REG_HISR3_8814B */
+#define BIT_GTINT12_8814B BIT(24)
+#define BIT_GTINT11_8814B BIT(23)
+#define BIT_GTINT10_8814B BIT(22)
+#define BIT_GTINT9_8814B BIT(21)
+#define BIT_RX_DESC_BUF_FULL_8814B BIT(20)
+#define BIT_CPHY_LDO_OCP_DET_INT_8814B BIT(19)
+#define BIT_WDT_PLATFORM_INT_8814B BIT(18)
+#define BIT_WDT_CPU_INT_8814B BIT(17)
+#define BIT_SETH2CDOK_8814B BIT(16)
+#define BIT_H2C_CMD_FULL_8814B BIT(15)
+#define BIT_PKT_TRANS_ERR_8814B BIT(14)
+#define BIT_TXSHORTCUT_TXDESUPDATEOK_8814B BIT(13)
+#define BIT_TXSHORTCUT_BKUPDATEOK_8814B BIT(12)
+#define BIT_TXSHORTCUT_BEUPDATEOK_8814B BIT(11)
+#define BIT_TXSHORTCUT_VIUPDATEOK_8814B BIT(10)
+#define BIT_TXSHORTCUT_VOUPDATEOK_8814B BIT(9)
+#define BIT_SEARCH_FAIL_8814B BIT(8)
+#define BIT_PWR_INT_127TO96_8814B BIT(7)
+#define BIT_PWR_INT_95TO64_8814B BIT(6)
+#define BIT_PWR_INT_63TO32_8814B BIT(5)
+#define BIT_PWR_INT_31TO0_8814B BIT(4)
+#define BIT_RX_DMA_STUCK_8814B BIT(3)
+#define BIT_TX_DMA_STUCK_8814B BIT(2)
+#define BIT_DDMA0_LP_INT_8814B BIT(1)
+#define BIT_DDMA0_HP_INT_8814B BIT(0)
+
+/* 2 REG_SW_MDIO_8814B */
+#define BIT_DIS_TIMEOUT_IO_8814B BIT(24)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_HIMR_7_8814B */
+#define BIT_DATA_CPU_WDT_INT_MSK_8814B BIT(31)
+#define BIT_OFLD_TXDMA_ERR_MSK_8814B BIT(30)
+#define BIT_OFLD_TXDMA_FULL_MSK_8814B BIT(29)
+#define BIT_OFLD_RXDMA_OVR_MSK_8814B BIT(28)
+#define BIT_OFLD_RXDMA_ERR_MSK_8814B BIT(27)
+#define BIT_OFLD_RXDMA_DES_UA_MSK_8814B BIT(26)
+#define BIT_TXDMAOK_CHANNEL_16_MSK_8814B BIT(16)
+#define BIT_TXDMAOK_CHANNEL_13_MSK_8814B BIT(13)
+#define BIT_TXDMAOK_CHANNEL_12_MSK_8814B BIT(12)
+#define BIT_TXDMAOK_CHANNEL_11_MSK_8814B BIT(11)
+#define BIT_TXDMAOK_CHANNEL_10_MSK_8814B BIT(10)
+#define BIT_TXDMAOK_CHANNEL_9_MSK_8814B BIT(9)
+#define BIT_TXDMAOK_CHANNEL_8_MSK_8814B BIT(8)
+#define BIT_TXDMAOK_CHANNEL_7_MSK_8814B BIT(7)
+#define BIT_TXDMAOK_CHANNEL_6_MSK_8814B BIT(6)
+#define BIT_TXDMAOK_CHANNEL_5_MSK_8814B BIT(5)
+#define BIT_TXDMAOK_CHANNEL_4_MSK_8814B BIT(4)
+
+/* 2 REG_HISR_7_8814B */
+#define BIT_DATA_CPU_WDT_INT_8814B BIT(31)
+#define BIT_OFLD_TXDMA_ERR_8814B BIT(30)
+#define BIT_OFLD_TXDMA_FULL_8814B BIT(29)
+#define BIT_OFLD_RXDMA_OVR_8814B BIT(28)
+#define BIT_OFLD_RXDMA_ERR_8814B BIT(27)
+#define BIT_OFLD_RXDMA_DES_UA_8814B BIT(26)
+#define BIT_TXDMAOK_CHANNEL_16_8814B BIT(16)
+#define BIT_TXDMAOK_CHANNEL_13_8814B BIT(13)
+#define BIT_TXDMAOK_CHANNEL_12_8814B BIT(12)
+#define BIT_TXDMAOK_CHANNEL_11_8814B BIT(11)
+#define BIT_TXDMAOK_CHANNEL_10_8814B BIT(10)
+#define BIT_TXDMAOK_CHANNEL_9_8814B BIT(9)
+#define BIT_TXDMAOK_CHANNEL_8_8814B BIT(8)
+#define BIT_TXDMAOK_CHANNEL_7_8814B BIT(7)
+#define BIT_TXDMAOK_CHANNEL_6_8814B BIT(6)
+#define BIT_TXDMAOK_CHANNEL_5_8814B BIT(5)
+#define BIT_TXDMAOK_CHANNEL_4_8814B BIT(4)
+
+/* 2 REG_H2C_PKT_READADDR_8814B */
+
+#define BIT_SHIFT_H2C_PKT_READADDR_8814B 0
+#define BIT_MASK_H2C_PKT_READADDR_8814B 0x3ffff
+#define BIT_H2C_PKT_READADDR_8814B(x) \
+ (((x) & BIT_MASK_H2C_PKT_READADDR_8814B) \
+ << BIT_SHIFT_H2C_PKT_READADDR_8814B)
+#define BITS_H2C_PKT_READADDR_8814B \
+ (BIT_MASK_H2C_PKT_READADDR_8814B << BIT_SHIFT_H2C_PKT_READADDR_8814B)
+#define BIT_CLEAR_H2C_PKT_READADDR_8814B(x) \
+ ((x) & (~BITS_H2C_PKT_READADDR_8814B))
+#define BIT_GET_H2C_PKT_READADDR_8814B(x) \
+ (((x) >> BIT_SHIFT_H2C_PKT_READADDR_8814B) & \
+ BIT_MASK_H2C_PKT_READADDR_8814B)
+#define BIT_SET_H2C_PKT_READADDR_8814B(x, v) \
+ (BIT_CLEAR_H2C_PKT_READADDR_8814B(x) | BIT_H2C_PKT_READADDR_8814B(v))
+
+/* 2 REG_H2C_PKT_WRITEADDR_8814B */
+
+#define BIT_SHIFT_H2C_PKT_WRITEADDR_8814B 0
+#define BIT_MASK_H2C_PKT_WRITEADDR_8814B 0x3ffff
+#define BIT_H2C_PKT_WRITEADDR_8814B(x) \
+ (((x) & BIT_MASK_H2C_PKT_WRITEADDR_8814B) \
+ << BIT_SHIFT_H2C_PKT_WRITEADDR_8814B)
+#define BITS_H2C_PKT_WRITEADDR_8814B \
+ (BIT_MASK_H2C_PKT_WRITEADDR_8814B << BIT_SHIFT_H2C_PKT_WRITEADDR_8814B)
+#define BIT_CLEAR_H2C_PKT_WRITEADDR_8814B(x) \
+ ((x) & (~BITS_H2C_PKT_WRITEADDR_8814B))
+#define BIT_GET_H2C_PKT_WRITEADDR_8814B(x) \
+ (((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR_8814B) & \
+ BIT_MASK_H2C_PKT_WRITEADDR_8814B)
+#define BIT_SET_H2C_PKT_WRITEADDR_8814B(x, v) \
+ (BIT_CLEAR_H2C_PKT_WRITEADDR_8814B(x) | BIT_H2C_PKT_WRITEADDR_8814B(v))
+
+/* 2 REG_MEM_PWR_CRTL_8814B */
+#define BIT_MEM_BB_SD_8814B BIT(17)
+#define BIT_MEM_BB_DS_8814B BIT(16)
+#define BIT_MEM_DENG_LS_8814B BIT(13)
+#define BIT_MEM_DENG_DS_8814B BIT(12)
+#define BIT_MEM_BT_DS_8814B BIT(10)
+#define BIT_MEM_SDIO_LS_8814B BIT(9)
+#define BIT_MEM_SDIO_DS_8814B BIT(8)
+#define BIT_MEM_USB_LS_8814B BIT(7)
+#define BIT_MEM_USB_DS_8814B BIT(6)
+#define BIT_MEM_PCI_LS_8814B BIT(5)
+#define BIT_MEM_PCI_DS_8814B BIT(4)
+#define BIT_MEM_WLMAC_LS_8814B BIT(3)
+#define BIT_MEM_WLMAC_DS_8814B BIT(2)
+#define BIT_MEM_WLMCU_LS_8814B BIT(1)
+#define BIT_MEM_WLMCU_DS_8814B BIT(0)
+
+/* 2 REG_FW_DRV_HANDSHAKE_8814B */
+
+#define BIT_SHIFT_FW_DRV_HANDSHAKE_8814B 0
+#define BIT_MASK_FW_DRV_HANDSHAKE_8814B 0xffffffffL
+#define BIT_FW_DRV_HANDSHAKE_8814B(x) \
+ (((x) & BIT_MASK_FW_DRV_HANDSHAKE_8814B) \
+ << BIT_SHIFT_FW_DRV_HANDSHAKE_8814B)
+#define BITS_FW_DRV_HANDSHAKE_8814B \
+ (BIT_MASK_FW_DRV_HANDSHAKE_8814B << BIT_SHIFT_FW_DRV_HANDSHAKE_8814B)
+#define BIT_CLEAR_FW_DRV_HANDSHAKE_8814B(x) \
+ ((x) & (~BITS_FW_DRV_HANDSHAKE_8814B))
+#define BIT_GET_FW_DRV_HANDSHAKE_8814B(x) \
+ (((x) >> BIT_SHIFT_FW_DRV_HANDSHAKE_8814B) & \
+ BIT_MASK_FW_DRV_HANDSHAKE_8814B)
+#define BIT_SET_FW_DRV_HANDSHAKE_8814B(x, v) \
+ (BIT_CLEAR_FW_DRV_HANDSHAKE_8814B(x) | BIT_FW_DRV_HANDSHAKE_8814B(v))
+
+/* 2 REG_FW_DBG0_8814B */
+
+#define BIT_SHIFT_FW_DBG0_8814B 0
+#define BIT_MASK_FW_DBG0_8814B 0xffffffffL
+#define BIT_FW_DBG0_8814B(x) \
+ (((x) & BIT_MASK_FW_DBG0_8814B) << BIT_SHIFT_FW_DBG0_8814B)
+#define BITS_FW_DBG0_8814B (BIT_MASK_FW_DBG0_8814B << BIT_SHIFT_FW_DBG0_8814B)
+#define BIT_CLEAR_FW_DBG0_8814B(x) ((x) & (~BITS_FW_DBG0_8814B))
+#define BIT_GET_FW_DBG0_8814B(x) \
+ (((x) >> BIT_SHIFT_FW_DBG0_8814B) & BIT_MASK_FW_DBG0_8814B)
+#define BIT_SET_FW_DBG0_8814B(x, v) \
+ (BIT_CLEAR_FW_DBG0_8814B(x) | BIT_FW_DBG0_8814B(v))
+
+/* 2 REG_FW_DBG1_8814B */
+
+#define BIT_SHIFT_FW_DBG1_8814B 0
+#define BIT_MASK_FW_DBG1_8814B 0xffffffffL
+#define BIT_FW_DBG1_8814B(x) \
+ (((x) & BIT_MASK_FW_DBG1_8814B) << BIT_SHIFT_FW_DBG1_8814B)
+#define BITS_FW_DBG1_8814B (BIT_MASK_FW_DBG1_8814B << BIT_SHIFT_FW_DBG1_8814B)
+#define BIT_CLEAR_FW_DBG1_8814B(x) ((x) & (~BITS_FW_DBG1_8814B))
+#define BIT_GET_FW_DBG1_8814B(x) \
+ (((x) >> BIT_SHIFT_FW_DBG1_8814B) & BIT_MASK_FW_DBG1_8814B)
+#define BIT_SET_FW_DBG1_8814B(x, v) \
+ (BIT_CLEAR_FW_DBG1_8814B(x) | BIT_FW_DBG1_8814B(v))
+
+/* 2 REG_FW_DBG2_8814B */
+
+#define BIT_SHIFT_FW_DBG2_8814B 0
+#define BIT_MASK_FW_DBG2_8814B 0xffffffffL
+#define BIT_FW_DBG2_8814B(x) \
+ (((x) & BIT_MASK_FW_DBG2_8814B) << BIT_SHIFT_FW_DBG2_8814B)
+#define BITS_FW_DBG2_8814B (BIT_MASK_FW_DBG2_8814B << BIT_SHIFT_FW_DBG2_8814B)
+#define BIT_CLEAR_FW_DBG2_8814B(x) ((x) & (~BITS_FW_DBG2_8814B))
+#define BIT_GET_FW_DBG2_8814B(x) \
+ (((x) >> BIT_SHIFT_FW_DBG2_8814B) & BIT_MASK_FW_DBG2_8814B)
+#define BIT_SET_FW_DBG2_8814B(x, v) \
+ (BIT_CLEAR_FW_DBG2_8814B(x) | BIT_FW_DBG2_8814B(v))
+
+/* 2 REG_FW_DBG3_8814B */
+
+#define BIT_SHIFT_FW_DBG3_8814B 0
+#define BIT_MASK_FW_DBG3_8814B 0xffffffffL
+#define BIT_FW_DBG3_8814B(x) \
+ (((x) & BIT_MASK_FW_DBG3_8814B) << BIT_SHIFT_FW_DBG3_8814B)
+#define BITS_FW_DBG3_8814B (BIT_MASK_FW_DBG3_8814B << BIT_SHIFT_FW_DBG3_8814B)
+#define BIT_CLEAR_FW_DBG3_8814B(x) ((x) & (~BITS_FW_DBG3_8814B))
+#define BIT_GET_FW_DBG3_8814B(x) \
+ (((x) >> BIT_SHIFT_FW_DBG3_8814B) & BIT_MASK_FW_DBG3_8814B)
+#define BIT_SET_FW_DBG3_8814B(x, v) \
+ (BIT_CLEAR_FW_DBG3_8814B(x) | BIT_FW_DBG3_8814B(v))
+
+/* 2 REG_FW_DBG4_8814B */
+
+#define BIT_SHIFT_FW_DBG4_8814B 0
+#define BIT_MASK_FW_DBG4_8814B 0xffffffffL
+#define BIT_FW_DBG4_8814B(x) \
+ (((x) & BIT_MASK_FW_DBG4_8814B) << BIT_SHIFT_FW_DBG4_8814B)
+#define BITS_FW_DBG4_8814B (BIT_MASK_FW_DBG4_8814B << BIT_SHIFT_FW_DBG4_8814B)
+#define BIT_CLEAR_FW_DBG4_8814B(x) ((x) & (~BITS_FW_DBG4_8814B))
+#define BIT_GET_FW_DBG4_8814B(x) \
+ (((x) >> BIT_SHIFT_FW_DBG4_8814B) & BIT_MASK_FW_DBG4_8814B)
+#define BIT_SET_FW_DBG4_8814B(x, v) \
+ (BIT_CLEAR_FW_DBG4_8814B(x) | BIT_FW_DBG4_8814B(v))
+
+/* 2 REG_FW_DBG5_8814B */
+
+#define BIT_SHIFT_FW_DBG5_8814B 0
+#define BIT_MASK_FW_DBG5_8814B 0xffffffffL
+#define BIT_FW_DBG5_8814B(x) \
+ (((x) & BIT_MASK_FW_DBG5_8814B) << BIT_SHIFT_FW_DBG5_8814B)
+#define BITS_FW_DBG5_8814B (BIT_MASK_FW_DBG5_8814B << BIT_SHIFT_FW_DBG5_8814B)
+#define BIT_CLEAR_FW_DBG5_8814B(x) ((x) & (~BITS_FW_DBG5_8814B))
+#define BIT_GET_FW_DBG5_8814B(x) \
+ (((x) >> BIT_SHIFT_FW_DBG5_8814B) & BIT_MASK_FW_DBG5_8814B)
+#define BIT_SET_FW_DBG5_8814B(x, v) \
+ (BIT_CLEAR_FW_DBG5_8814B(x) | BIT_FW_DBG5_8814B(v))
+
+/* 2 REG_FW_DBG6_8814B */
+
+#define BIT_SHIFT_FW_DBG6_8814B 0
+#define BIT_MASK_FW_DBG6_8814B 0xffffffffL
+#define BIT_FW_DBG6_8814B(x) \
+ (((x) & BIT_MASK_FW_DBG6_8814B) << BIT_SHIFT_FW_DBG6_8814B)
+#define BITS_FW_DBG6_8814B (BIT_MASK_FW_DBG6_8814B << BIT_SHIFT_FW_DBG6_8814B)
+#define BIT_CLEAR_FW_DBG6_8814B(x) ((x) & (~BITS_FW_DBG6_8814B))
+#define BIT_GET_FW_DBG6_8814B(x) \
+ (((x) >> BIT_SHIFT_FW_DBG6_8814B) & BIT_MASK_FW_DBG6_8814B)
+#define BIT_SET_FW_DBG6_8814B(x, v) \
+ (BIT_CLEAR_FW_DBG6_8814B(x) | BIT_FW_DBG6_8814B(v))
+
+/* 2 REG_FW_DBG7_8814B */
+
+#define BIT_SHIFT_FW_DBG7_8814B 0
+#define BIT_MASK_FW_DBG7_8814B 0xffffffffL
+#define BIT_FW_DBG7_8814B(x) \
+ (((x) & BIT_MASK_FW_DBG7_8814B) << BIT_SHIFT_FW_DBG7_8814B)
+#define BITS_FW_DBG7_8814B (BIT_MASK_FW_DBG7_8814B << BIT_SHIFT_FW_DBG7_8814B)
+#define BIT_CLEAR_FW_DBG7_8814B(x) ((x) & (~BITS_FW_DBG7_8814B))
+#define BIT_GET_FW_DBG7_8814B(x) \
+ (((x) >> BIT_SHIFT_FW_DBG7_8814B) & BIT_MASK_FW_DBG7_8814B)
+#define BIT_SET_FW_DBG7_8814B(x, v) \
+ (BIT_CLEAR_FW_DBG7_8814B(x) | BIT_FW_DBG7_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_CR_8814B */
+
+#define BIT_SHIFT_LBMODE_8814B 24
+#define BIT_MASK_LBMODE_8814B 0x1f
+#define BIT_LBMODE_8814B(x) \
+ (((x) & BIT_MASK_LBMODE_8814B) << BIT_SHIFT_LBMODE_8814B)
+#define BITS_LBMODE_8814B (BIT_MASK_LBMODE_8814B << BIT_SHIFT_LBMODE_8814B)
+#define BIT_CLEAR_LBMODE_8814B(x) ((x) & (~BITS_LBMODE_8814B))
+#define BIT_GET_LBMODE_8814B(x) \
+ (((x) >> BIT_SHIFT_LBMODE_8814B) & BIT_MASK_LBMODE_8814B)
+#define BIT_SET_LBMODE_8814B(x, v) \
+ (BIT_CLEAR_LBMODE_8814B(x) | BIT_LBMODE_8814B(v))
+
+#define BIT_SHIFT_NETYPE1_8814B 18
+#define BIT_MASK_NETYPE1_8814B 0x3
+#define BIT_NETYPE1_8814B(x) \
+ (((x) & BIT_MASK_NETYPE1_8814B) << BIT_SHIFT_NETYPE1_8814B)
+#define BITS_NETYPE1_8814B (BIT_MASK_NETYPE1_8814B << BIT_SHIFT_NETYPE1_8814B)
+#define BIT_CLEAR_NETYPE1_8814B(x) ((x) & (~BITS_NETYPE1_8814B))
+#define BIT_GET_NETYPE1_8814B(x) \
+ (((x) >> BIT_SHIFT_NETYPE1_8814B) & BIT_MASK_NETYPE1_8814B)
+#define BIT_SET_NETYPE1_8814B(x, v) \
+ (BIT_CLEAR_NETYPE1_8814B(x) | BIT_NETYPE1_8814B(v))
+
+#define BIT_SHIFT_NETYPE0_8814B 16
+#define BIT_MASK_NETYPE0_8814B 0x3
+#define BIT_NETYPE0_8814B(x) \
+ (((x) & BIT_MASK_NETYPE0_8814B) << BIT_SHIFT_NETYPE0_8814B)
+#define BITS_NETYPE0_8814B (BIT_MASK_NETYPE0_8814B << BIT_SHIFT_NETYPE0_8814B)
+#define BIT_CLEAR_NETYPE0_8814B(x) ((x) & (~BITS_NETYPE0_8814B))
+#define BIT_GET_NETYPE0_8814B(x) \
+ (((x) >> BIT_SHIFT_NETYPE0_8814B) & BIT_MASK_NETYPE0_8814B)
+#define BIT_SET_NETYPE0_8814B(x, v) \
+ (BIT_CLEAR_NETYPE0_8814B(x) | BIT_NETYPE0_8814B(v))
+
+#define BIT_COUNTER_STS_EN_8814B BIT(13)
+#define BIT_I2C_MAILBOX_EN_8814B BIT(12)
+#define BIT_SHCUT_EN_8814B BIT(11)
+#define BIT_32K_CAL_TMR_EN_8814B BIT(10)
+#define BIT_MAC_SEC_EN_8814B BIT(9)
+#define BIT_ENSWBCN_8814B BIT(8)
+#define BIT_MACRXEN_8814B BIT(7)
+#define BIT_MACTXEN_8814B BIT(6)
+#define BIT_SCHEDULE_EN_8814B BIT(5)
+#define BIT_PROTOCOL_EN_8814B BIT(4)
+#define BIT_RXDMA_EN_8814B BIT(3)
+#define BIT_TXDMA_EN_8814B BIT(2)
+#define BIT_HCI_RXDMA_EN_8814B BIT(1)
+#define BIT_HCI_TXDMA_EN_8814B BIT(0)
+
+/* 2 REG_PG_SIZE_8814B */
+
+#define BIT_SHIFT_DBG_FIFO_SEL_8814B 16
+#define BIT_MASK_DBG_FIFO_SEL_8814B 0xff
+#define BIT_DBG_FIFO_SEL_8814B(x) \
+ (((x) & BIT_MASK_DBG_FIFO_SEL_8814B) << BIT_SHIFT_DBG_FIFO_SEL_8814B)
+#define BITS_DBG_FIFO_SEL_8814B \
+ (BIT_MASK_DBG_FIFO_SEL_8814B << BIT_SHIFT_DBG_FIFO_SEL_8814B)
+#define BIT_CLEAR_DBG_FIFO_SEL_8814B(x) ((x) & (~BITS_DBG_FIFO_SEL_8814B))
+#define BIT_GET_DBG_FIFO_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_DBG_FIFO_SEL_8814B) & BIT_MASK_DBG_FIFO_SEL_8814B)
+#define BIT_SET_DBG_FIFO_SEL_8814B(x, v) \
+ (BIT_CLEAR_DBG_FIFO_SEL_8814B(x) | BIT_DBG_FIFO_SEL_8814B(v))
+
+/* 2 REG_PKT_BUFF_ACCESS_CTRL_8814B */
+
+#define BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8814B 0
+#define BIT_MASK_PKT_BUFF_ACCESS_CTRL_8814B 0xff
+#define BIT_PKT_BUFF_ACCESS_CTRL_8814B(x) \
+ (((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL_8814B) \
+ << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8814B)
+#define BITS_PKT_BUFF_ACCESS_CTRL_8814B \
+ (BIT_MASK_PKT_BUFF_ACCESS_CTRL_8814B \
+ << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8814B)
+#define BIT_CLEAR_PKT_BUFF_ACCESS_CTRL_8814B(x) \
+ ((x) & (~BITS_PKT_BUFF_ACCESS_CTRL_8814B))
+#define BIT_GET_PKT_BUFF_ACCESS_CTRL_8814B(x) \
+ (((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8814B) & \
+ BIT_MASK_PKT_BUFF_ACCESS_CTRL_8814B)
+#define BIT_SET_PKT_BUFF_ACCESS_CTRL_8814B(x, v) \
+ (BIT_CLEAR_PKT_BUFF_ACCESS_CTRL_8814B(x) | \
+ BIT_PKT_BUFF_ACCESS_CTRL_8814B(v))
+
+/* 2 REG_TSF_CLK_STATE_8814B */
+#define BIT_TSF_CLK_STABLE_8814B BIT(15)
+
+/* 2 REG_TXDMA_PQ_MAP_8814B */
+
+#define BIT_SHIFT_TXDMA_H2C_MAP_8814B 16
+#define BIT_MASK_TXDMA_H2C_MAP_8814B 0x3
+#define BIT_TXDMA_H2C_MAP_8814B(x) \
+ (((x) & BIT_MASK_TXDMA_H2C_MAP_8814B) << BIT_SHIFT_TXDMA_H2C_MAP_8814B)
+#define BITS_TXDMA_H2C_MAP_8814B \
+ (BIT_MASK_TXDMA_H2C_MAP_8814B << BIT_SHIFT_TXDMA_H2C_MAP_8814B)
+#define BIT_CLEAR_TXDMA_H2C_MAP_8814B(x) ((x) & (~BITS_TXDMA_H2C_MAP_8814B))
+#define BIT_GET_TXDMA_H2C_MAP_8814B(x) \
+ (((x) >> BIT_SHIFT_TXDMA_H2C_MAP_8814B) & BIT_MASK_TXDMA_H2C_MAP_8814B)
+#define BIT_SET_TXDMA_H2C_MAP_8814B(x, v) \
+ (BIT_CLEAR_TXDMA_H2C_MAP_8814B(x) | BIT_TXDMA_H2C_MAP_8814B(v))
+
+#define BIT_SHIFT_TXDMA_HIQ_MAP_8814B 14
+#define BIT_MASK_TXDMA_HIQ_MAP_8814B 0x3
+#define BIT_TXDMA_HIQ_MAP_8814B(x) \
+ (((x) & BIT_MASK_TXDMA_HIQ_MAP_8814B) << BIT_SHIFT_TXDMA_HIQ_MAP_8814B)
+#define BITS_TXDMA_HIQ_MAP_8814B \
+ (BIT_MASK_TXDMA_HIQ_MAP_8814B << BIT_SHIFT_TXDMA_HIQ_MAP_8814B)
+#define BIT_CLEAR_TXDMA_HIQ_MAP_8814B(x) ((x) & (~BITS_TXDMA_HIQ_MAP_8814B))
+#define BIT_GET_TXDMA_HIQ_MAP_8814B(x) \
+ (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8814B) & BIT_MASK_TXDMA_HIQ_MAP_8814B)
+#define BIT_SET_TXDMA_HIQ_MAP_8814B(x, v) \
+ (BIT_CLEAR_TXDMA_HIQ_MAP_8814B(x) | BIT_TXDMA_HIQ_MAP_8814B(v))
+
+#define BIT_SHIFT_TXDMA_MGQ_MAP_8814B 12
+#define BIT_MASK_TXDMA_MGQ_MAP_8814B 0x3
+#define BIT_TXDMA_MGQ_MAP_8814B(x) \
+ (((x) & BIT_MASK_TXDMA_MGQ_MAP_8814B) << BIT_SHIFT_TXDMA_MGQ_MAP_8814B)
+#define BITS_TXDMA_MGQ_MAP_8814B \
+ (BIT_MASK_TXDMA_MGQ_MAP_8814B << BIT_SHIFT_TXDMA_MGQ_MAP_8814B)
+#define BIT_CLEAR_TXDMA_MGQ_MAP_8814B(x) ((x) & (~BITS_TXDMA_MGQ_MAP_8814B))
+#define BIT_GET_TXDMA_MGQ_MAP_8814B(x) \
+ (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8814B) & BIT_MASK_TXDMA_MGQ_MAP_8814B)
+#define BIT_SET_TXDMA_MGQ_MAP_8814B(x, v) \
+ (BIT_CLEAR_TXDMA_MGQ_MAP_8814B(x) | BIT_TXDMA_MGQ_MAP_8814B(v))
+
+#define BIT_SHIFT_TXDMA_BKQ_MAP_8814B 10
+#define BIT_MASK_TXDMA_BKQ_MAP_8814B 0x3
+#define BIT_TXDMA_BKQ_MAP_8814B(x) \
+ (((x) & BIT_MASK_TXDMA_BKQ_MAP_8814B) << BIT_SHIFT_TXDMA_BKQ_MAP_8814B)
+#define BITS_TXDMA_BKQ_MAP_8814B \
+ (BIT_MASK_TXDMA_BKQ_MAP_8814B << BIT_SHIFT_TXDMA_BKQ_MAP_8814B)
+#define BIT_CLEAR_TXDMA_BKQ_MAP_8814B(x) ((x) & (~BITS_TXDMA_BKQ_MAP_8814B))
+#define BIT_GET_TXDMA_BKQ_MAP_8814B(x) \
+ (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8814B) & BIT_MASK_TXDMA_BKQ_MAP_8814B)
+#define BIT_SET_TXDMA_BKQ_MAP_8814B(x, v) \
+ (BIT_CLEAR_TXDMA_BKQ_MAP_8814B(x) | BIT_TXDMA_BKQ_MAP_8814B(v))
+
+#define BIT_SHIFT_TXDMA_BEQ_MAP_8814B 8
+#define BIT_MASK_TXDMA_BEQ_MAP_8814B 0x3
+#define BIT_TXDMA_BEQ_MAP_8814B(x) \
+ (((x) & BIT_MASK_TXDMA_BEQ_MAP_8814B) << BIT_SHIFT_TXDMA_BEQ_MAP_8814B)
+#define BITS_TXDMA_BEQ_MAP_8814B \
+ (BIT_MASK_TXDMA_BEQ_MAP_8814B << BIT_SHIFT_TXDMA_BEQ_MAP_8814B)
+#define BIT_CLEAR_TXDMA_BEQ_MAP_8814B(x) ((x) & (~BITS_TXDMA_BEQ_MAP_8814B))
+#define BIT_GET_TXDMA_BEQ_MAP_8814B(x) \
+ (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8814B) & BIT_MASK_TXDMA_BEQ_MAP_8814B)
+#define BIT_SET_TXDMA_BEQ_MAP_8814B(x, v) \
+ (BIT_CLEAR_TXDMA_BEQ_MAP_8814B(x) | BIT_TXDMA_BEQ_MAP_8814B(v))
+
+#define BIT_SHIFT_TXDMA_VIQ_MAP_8814B 6
+#define BIT_MASK_TXDMA_VIQ_MAP_8814B 0x3
+#define BIT_TXDMA_VIQ_MAP_8814B(x) \
+ (((x) & BIT_MASK_TXDMA_VIQ_MAP_8814B) << BIT_SHIFT_TXDMA_VIQ_MAP_8814B)
+#define BITS_TXDMA_VIQ_MAP_8814B \
+ (BIT_MASK_TXDMA_VIQ_MAP_8814B << BIT_SHIFT_TXDMA_VIQ_MAP_8814B)
+#define BIT_CLEAR_TXDMA_VIQ_MAP_8814B(x) ((x) & (~BITS_TXDMA_VIQ_MAP_8814B))
+#define BIT_GET_TXDMA_VIQ_MAP_8814B(x) \
+ (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8814B) & BIT_MASK_TXDMA_VIQ_MAP_8814B)
+#define BIT_SET_TXDMA_VIQ_MAP_8814B(x, v) \
+ (BIT_CLEAR_TXDMA_VIQ_MAP_8814B(x) | BIT_TXDMA_VIQ_MAP_8814B(v))
+
+#define BIT_SHIFT_TXDMA_VOQ_MAP_8814B 4
+#define BIT_MASK_TXDMA_VOQ_MAP_8814B 0x3
+#define BIT_TXDMA_VOQ_MAP_8814B(x) \
+ (((x) & BIT_MASK_TXDMA_VOQ_MAP_8814B) << BIT_SHIFT_TXDMA_VOQ_MAP_8814B)
+#define BITS_TXDMA_VOQ_MAP_8814B \
+ (BIT_MASK_TXDMA_VOQ_MAP_8814B << BIT_SHIFT_TXDMA_VOQ_MAP_8814B)
+#define BIT_CLEAR_TXDMA_VOQ_MAP_8814B(x) ((x) & (~BITS_TXDMA_VOQ_MAP_8814B))
+#define BIT_GET_TXDMA_VOQ_MAP_8814B(x) \
+ (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8814B) & BIT_MASK_TXDMA_VOQ_MAP_8814B)
+#define BIT_SET_TXDMA_VOQ_MAP_8814B(x, v) \
+ (BIT_CLEAR_TXDMA_VOQ_MAP_8814B(x) | BIT_TXDMA_VOQ_MAP_8814B(v))
+
+#define BIT_RXDMA_AGG_EN_8814B BIT(2)
+#define BIT_RXSHFT_EN_8814B BIT(1)
+#define BIT_RXDMA_ARBBW_EN_8814B BIT(0)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_TRXFF_BNDY_8814B */
+
+#define BIT_SHIFT_FWFFOVFL_RSV_8814B 16
+#define BIT_MASK_FWFFOVFL_RSV_8814B 0xf
+#define BIT_FWFFOVFL_RSV_8814B(x) \
+ (((x) & BIT_MASK_FWFFOVFL_RSV_8814B) << BIT_SHIFT_FWFFOVFL_RSV_8814B)
+#define BITS_FWFFOVFL_RSV_8814B \
+ (BIT_MASK_FWFFOVFL_RSV_8814B << BIT_SHIFT_FWFFOVFL_RSV_8814B)
+#define BIT_CLEAR_FWFFOVFL_RSV_8814B(x) ((x) & (~BITS_FWFFOVFL_RSV_8814B))
+#define BIT_GET_FWFFOVFL_RSV_8814B(x) \
+ (((x) >> BIT_SHIFT_FWFFOVFL_RSV_8814B) & BIT_MASK_FWFFOVFL_RSV_8814B)
+#define BIT_SET_FWFFOVFL_RSV_8814B(x, v) \
+ (BIT_CLEAR_FWFFOVFL_RSV_8814B(x) | BIT_FWFFOVFL_RSV_8814B(v))
+
+#define BIT_SHIFT_RXFFOVFL_RSV_V2_8814B 8
+#define BIT_MASK_RXFFOVFL_RSV_V2_8814B 0xf
+#define BIT_RXFFOVFL_RSV_V2_8814B(x) \
+ (((x) & BIT_MASK_RXFFOVFL_RSV_V2_8814B) \
+ << BIT_SHIFT_RXFFOVFL_RSV_V2_8814B)
+#define BITS_RXFFOVFL_RSV_V2_8814B \
+ (BIT_MASK_RXFFOVFL_RSV_V2_8814B << BIT_SHIFT_RXFFOVFL_RSV_V2_8814B)
+#define BIT_CLEAR_RXFFOVFL_RSV_V2_8814B(x) ((x) & (~BITS_RXFFOVFL_RSV_V2_8814B))
+#define BIT_GET_RXFFOVFL_RSV_V2_8814B(x) \
+ (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8814B) & \
+ BIT_MASK_RXFFOVFL_RSV_V2_8814B)
+#define BIT_SET_RXFFOVFL_RSV_V2_8814B(x, v) \
+ (BIT_CLEAR_RXFFOVFL_RSV_V2_8814B(x) | BIT_RXFFOVFL_RSV_V2_8814B(v))
+
+/* 2 REG_PTA_I2C_MBOX_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_I2C_M_STATUS_8814B 8
+#define BIT_MASK_I2C_M_STATUS_8814B 0xf
+#define BIT_I2C_M_STATUS_8814B(x) \
+ (((x) & BIT_MASK_I2C_M_STATUS_8814B) << BIT_SHIFT_I2C_M_STATUS_8814B)
+#define BITS_I2C_M_STATUS_8814B \
+ (BIT_MASK_I2C_M_STATUS_8814B << BIT_SHIFT_I2C_M_STATUS_8814B)
+#define BIT_CLEAR_I2C_M_STATUS_8814B(x) ((x) & (~BITS_I2C_M_STATUS_8814B))
+#define BIT_GET_I2C_M_STATUS_8814B(x) \
+ (((x) >> BIT_SHIFT_I2C_M_STATUS_8814B) & BIT_MASK_I2C_M_STATUS_8814B)
+#define BIT_SET_I2C_M_STATUS_8814B(x, v) \
+ (BIT_CLEAR_I2C_M_STATUS_8814B(x) | BIT_I2C_M_STATUS_8814B(v))
+
+#define BIT_SHIFT_I2C_M_BUS_GNT_FW_8814B 4
+#define BIT_MASK_I2C_M_BUS_GNT_FW_8814B 0x7
+#define BIT_I2C_M_BUS_GNT_FW_8814B(x) \
+ (((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8814B) \
+ << BIT_SHIFT_I2C_M_BUS_GNT_FW_8814B)
+#define BITS_I2C_M_BUS_GNT_FW_8814B \
+ (BIT_MASK_I2C_M_BUS_GNT_FW_8814B << BIT_SHIFT_I2C_M_BUS_GNT_FW_8814B)
+#define BIT_CLEAR_I2C_M_BUS_GNT_FW_8814B(x) \
+ ((x) & (~BITS_I2C_M_BUS_GNT_FW_8814B))
+#define BIT_GET_I2C_M_BUS_GNT_FW_8814B(x) \
+ (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8814B) & \
+ BIT_MASK_I2C_M_BUS_GNT_FW_8814B)
+#define BIT_SET_I2C_M_BUS_GNT_FW_8814B(x, v) \
+ (BIT_CLEAR_I2C_M_BUS_GNT_FW_8814B(x) | BIT_I2C_M_BUS_GNT_FW_8814B(v))
+
+#define BIT_I2C_M_GNT_FW_8814B BIT(3)
+
+#define BIT_SHIFT_I2C_M_SPEED_8814B 1
+#define BIT_MASK_I2C_M_SPEED_8814B 0x3
+#define BIT_I2C_M_SPEED_8814B(x) \
+ (((x) & BIT_MASK_I2C_M_SPEED_8814B) << BIT_SHIFT_I2C_M_SPEED_8814B)
+#define BITS_I2C_M_SPEED_8814B \
+ (BIT_MASK_I2C_M_SPEED_8814B << BIT_SHIFT_I2C_M_SPEED_8814B)
+#define BIT_CLEAR_I2C_M_SPEED_8814B(x) ((x) & (~BITS_I2C_M_SPEED_8814B))
+#define BIT_GET_I2C_M_SPEED_8814B(x) \
+ (((x) >> BIT_SHIFT_I2C_M_SPEED_8814B) & BIT_MASK_I2C_M_SPEED_8814B)
+#define BIT_SET_I2C_M_SPEED_8814B(x, v) \
+ (BIT_CLEAR_I2C_M_SPEED_8814B(x) | BIT_I2C_M_SPEED_8814B(v))
+
+#define BIT_I2C_M_UNLOCK_8814B BIT(0)
+
+/* 2 REG_RXFF_BNDY_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_RXFF0_BNDY_V2_8814B 0
+#define BIT_MASK_RXFF0_BNDY_V2_8814B 0x3ffff
+#define BIT_RXFF0_BNDY_V2_8814B(x) \
+ (((x) & BIT_MASK_RXFF0_BNDY_V2_8814B) << BIT_SHIFT_RXFF0_BNDY_V2_8814B)
+#define BITS_RXFF0_BNDY_V2_8814B \
+ (BIT_MASK_RXFF0_BNDY_V2_8814B << BIT_SHIFT_RXFF0_BNDY_V2_8814B)
+#define BIT_CLEAR_RXFF0_BNDY_V2_8814B(x) ((x) & (~BITS_RXFF0_BNDY_V2_8814B))
+#define BIT_GET_RXFF0_BNDY_V2_8814B(x) \
+ (((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8814B) & BIT_MASK_RXFF0_BNDY_V2_8814B)
+#define BIT_SET_RXFF0_BNDY_V2_8814B(x, v) \
+ (BIT_CLEAR_RXFF0_BNDY_V2_8814B(x) | BIT_RXFF0_BNDY_V2_8814B(v))
+
+/* 2 REG_FE1IMR_8814B */
+#define BIT_CPUMGQ_DROP_BY_HOLD_TIME_INT_EN_8814B BIT(31)
+#define BIT_FWFF_FULL_INT_EN_8814B BIT(30)
+#define BIT_BB_STOP_RX_INT_EN_8814B BIT(29)
+#define BIT_FS_RXDMA2_DONE_INT_EN_8814B BIT(28)
+#define BIT_FS_RXDONE3_INT_EN_8814B BIT(27)
+#define BIT_FS_RXDONE2_INT_EN_8814B BIT(26)
+#define BIT_FS_RX_BCN_P4_INT_EN_8814B BIT(25)
+#define BIT_FS_RX_BCN_P3_INT_EN_8814B BIT(24)
+#define BIT_FS_RX_BCN_P2_INT_EN_8814B BIT(23)
+#define BIT_FS_RX_BCN_P1_INT_EN_8814B BIT(22)
+#define BIT_FS_RX_BCN_P0_INT_EN_8814B BIT(21)
+#define BIT_FS_RX_UMD0_INT_EN_8814B BIT(20)
+#define BIT_FS_RX_UMD1_INT_EN_8814B BIT(19)
+#define BIT_FS_RX_BMD0_INT_EN_8814B BIT(18)
+#define BIT_FS_RX_BMD1_INT_EN_8814B BIT(17)
+#define BIT_FS_RXDONE_INT_EN_8814B BIT(16)
+#define BIT_FS_WWLAN_INT_EN_8814B BIT(15)
+#define BIT_FS_SOUND_DONE_INT_EN_8814B BIT(14)
+#define BIT_FS_TRL_MTR_INT_EN_8814B BIT(12)
+#define BIT_FS_BF1_PRETO_INT_EN_8814B BIT(11)
+#define BIT_FS_BF0_PRETO_INT_EN_8814B BIT(10)
+#define BIT_FS_PTCL_RELEASE_MACID_INT_EN_8814B BIT(9)
+#define BIT_PRETX_ERRHLD_INT_EN_8814B BIT(8)
+#define BIT_FS_GTRD_INT_EN_8814B BIT(7)
+#define BIT_FS_LTE_COEX_EN_8814B BIT(6)
+#define BIT_FS_WLACTOFF_INT_EN_8814B BIT(5)
+#define BIT_FS_WLACTON_INT_EN_8814B BIT(4)
+#define BIT_FS_BTCMD_INT_EN_8814B BIT(3)
+#define BIT_FS_REG_MAILBOX_TO_I2C_INT_EN_8814B BIT(2)
+#define BIT_FS_TRPC_TO_INT_EN_V1_8814B BIT(1)
+#define BIT_FS_RPC_O_T_INT_EN_V1_8814B BIT(0)
+
+/* 2 REG_FE1ISR_8814B */
+#define BIT_CPUMGQ_DROP_BY_HOLD_TIME_INT_8814B BIT(31)
+#define BIT_FWFF_FULL_INT_8814B BIT(30)
+#define BIT_BB_STOP_RX_INT_8814B BIT(29)
+#define BIT_FS_RXDMA2_DONE_INT_8814B BIT(28)
+#define BIT_FS_RXDONE3_INT_INT_8814B BIT(27)
+#define BIT_FS_RXDONE2_INT_8814B BIT(26)
+#define BIT_FS_RX_BCN_P4_INT_8814B BIT(25)
+#define BIT_FS_RX_BCN_P3_INT_8814B BIT(24)
+#define BIT_FS_RX_BCN_P2_INT_8814B BIT(23)
+#define BIT_FS_RX_BCN_P1_INT_8814B BIT(22)
+#define BIT_FS_RX_BCN_P0_INT_8814B BIT(21)
+#define BIT_FS_RX_UMD0_INT_8814B BIT(20)
+#define BIT_FS_RX_UMD1_INT_8814B BIT(19)
+#define BIT_FS_RX_BMD0_INT_8814B BIT(18)
+#define BIT_FS_RX_BMD1_INT_8814B BIT(17)
+#define BIT_FS_RXDONE_INT_8814B BIT(16)
+#define BIT_FS_WWLAN_INT_8814B BIT(15)
+#define BIT_FS_SOUND_DONE_INT_8814B BIT(14)
+#define BIT_FS_TRL_MTR_INT_8814B BIT(12)
+#define BIT_FS_BF1_PRETO_INT_8814B BIT(11)
+#define BIT_FS_BF0_PRETO_INT_8814B BIT(10)
+#define BIT_FS_PTCL_RELEASE_MACID_INT_8814B BIT(9)
+#define BIT_PRETX_ERRHLD_INT_8814B BIT(8)
+#define BIT_SND_RDY_INT_8814B BIT(7)
+#define BIT_FS_LTE_COEX_INT_8814B BIT(6)
+#define BIT_FS_WLACTOFF_INT_8814B BIT(5)
+#define BIT_FS_WLACTON_INT_8814B BIT(4)
+#define BIT_BT_CMD_INT_8814B BIT(3)
+#define BIT_FS_MAILBOX_TO_I2C_INT_8814B BIT(2)
+#define BIT_FS_TRPC_TO_INT_8814B BIT(1)
+#define BIT_FS_RPC_O_T_INT_8814B BIT(0)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_CPWM_8814B */
+#define BIT_CPWM_TOGGLING_8814B BIT(31)
+
+#define BIT_SHIFT_CPWM_MOD_8814B 24
+#define BIT_MASK_CPWM_MOD_8814B 0x7f
+#define BIT_CPWM_MOD_8814B(x) \
+ (((x) & BIT_MASK_CPWM_MOD_8814B) << BIT_SHIFT_CPWM_MOD_8814B)
+#define BITS_CPWM_MOD_8814B \
+ (BIT_MASK_CPWM_MOD_8814B << BIT_SHIFT_CPWM_MOD_8814B)
+#define BIT_CLEAR_CPWM_MOD_8814B(x) ((x) & (~BITS_CPWM_MOD_8814B))
+#define BIT_GET_CPWM_MOD_8814B(x) \
+ (((x) >> BIT_SHIFT_CPWM_MOD_8814B) & BIT_MASK_CPWM_MOD_8814B)
+#define BIT_SET_CPWM_MOD_8814B(x, v) \
+ (BIT_CLEAR_CPWM_MOD_8814B(x) | BIT_CPWM_MOD_8814B(v))
+
+/* 2 REG_FWIMR_8814B */
+#define BIT_FS_TXBCNOK_MB7_INT_EN_8814B BIT(31)
+#define BIT_FS_TXBCNOK_MB6_INT_EN_8814B BIT(30)
+#define BIT_FS_TXBCNOK_MB5_INT_EN_8814B BIT(29)
+#define BIT_FS_TXBCNOK_MB4_INT_EN_8814B BIT(28)
+#define BIT_FS_TXBCNOK_MB3_INT_EN_8814B BIT(27)
+#define BIT_FS_TXBCNOK_MB2_INT_EN_8814B BIT(26)
+#define BIT_FS_TXBCNOK_MB1_INT_EN_8814B BIT(25)
+#define BIT_FS_TXBCNOK_MB0_INT_EN_8814B BIT(24)
+#define BIT_FS_TXBCNERR_MB7_INT_EN_8814B BIT(23)
+#define BIT_FS_TXBCNERR_MB6_INT_EN_8814B BIT(22)
+#define BIT_FS_TXBCNERR_MB5_INT_EN_8814B BIT(21)
+#define BIT_FS_TXBCNERR_MB4_INT_EN_8814B BIT(20)
+#define BIT_FS_TXBCNERR_MB3_INT_EN_8814B BIT(19)
+#define BIT_FS_TXBCNERR_MB2_INT_EN_8814B BIT(18)
+#define BIT_FS_TXBCNERR_MB1_INT_EN_8814B BIT(17)
+#define BIT_FS_TXBCNERR_MB0_INT_EN_8814B BIT(16)
+#define BIT_CPU_MGQ_TXDONE_INT_EN_8814B BIT(15)
+#define BIT_SIFS_OVERSPEC_INT_EN_8814B BIT(14)
+#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_EN_8814B BIT(13)
+#define BIT_FS_MGNTQFF_TO_INT_EN_8814B BIT(12)
+#define BIT_FS_CPUMGQ_ERR_INT_EN_8814B BIT(11)
+#define BIT_FS_DDMA0_LP_INT_EN_8814B BIT(9)
+#define BIT_FS_DDMA0_HP_INT_EN_8814B BIT(8)
+#define BIT_FS_TRXRPT_INT_EN_8814B BIT(7)
+#define BIT_FS_C2H_W_READY_INT_EN_8814B BIT(6)
+#define BIT_FS_HRCV_INT_EN_8814B BIT(5)
+#define BIT_FS_H2CCMD_INT_EN_8814B BIT(4)
+#define BIT_FS_TXPKTIN_INT_EN_8814B BIT(3)
+#define BIT_FS_ERRORHDL_INT_EN_8814B BIT(2)
+#define BIT_FS_TXCCX_INT_EN_8814B BIT(1)
+#define BIT_FS_TXCLOSE_INT_EN_8814B BIT(0)
+
+/* 2 REG_FWISR_8814B */
+#define BIT_FS_TXBCNOK_MB7_INT_8814B BIT(31)
+#define BIT_FS_TXBCNOK_MB6_INT_8814B BIT(30)
+#define BIT_FS_TXBCNOK_MB5_INT_8814B BIT(29)
+#define BIT_FS_TXBCNOK_MB4_INT_8814B BIT(28)
+#define BIT_FS_TXBCNOK_MB3_INT_8814B BIT(27)
+#define BIT_FS_TXBCNOK_MB2_INT_8814B BIT(26)
+#define BIT_FS_TXBCNOK_MB1_INT_8814B BIT(25)
+#define BIT_FS_TXBCNOK_MB0_INT_8814B BIT(24)
+#define BIT_FS_TXBCNERR_MB7_INT_8814B BIT(23)
+#define BIT_FS_TXBCNERR_MB6_INT_8814B BIT(22)
+#define BIT_FS_TXBCNERR_MB5_INT_8814B BIT(21)
+#define BIT_FS_TXBCNERR_MB4_INT_8814B BIT(20)
+#define BIT_FS_TXBCNERR_MB3_INT_8814B BIT(19)
+#define BIT_FS_TXBCNERR_MB2_INT_8814B BIT(18)
+#define BIT_FS_TXBCNERR_MB1_INT_8814B BIT(17)
+#define BIT_FS_TXBCNERR_MB0_INT_8814B BIT(16)
+#define BIT_CPU_MGQ_TXDONE_INT_8814B BIT(15)
+#define BIT_SIFS_OVERSPEC_INT_8814B BIT(14)
+#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_8814B BIT(13)
+#define BIT_FS_MGNTQFF_TO_INT_8814B BIT(12)
+#define BIT_FS_CPUMGQ_ERR_INT_8814B BIT(11)
+#define BIT_FWCMD_PKTIN_INT_8814B BIT(10)
+#define BIT_FS_DDMA0_LP_INT_8814B BIT(9)
+#define BIT_FS_DDMA0_HP_INT_8814B BIT(8)
+#define BIT_FS_TRXRPT_INT_8814B BIT(7)
+#define BIT_FS_C2H_W_READY_INT_8814B BIT(6)
+#define BIT_FS_HRCV_INT_8814B BIT(5)
+#define BIT_FS_H2CCMD_INT_8814B BIT(4)
+#define BIT_FS_TXPKTIN_INT_8814B BIT(3)
+#define BIT_FS_ERRORHDL_INT_8814B BIT(2)
+#define BIT_FS_TXCCX_INT_8814B BIT(1)
+#define BIT_FS_TXCLOSE_INT_8814B BIT(0)
+
+/* 2 REG_FTIMR_8814B */
+#define BIT_PS_TIMER_C_EARLY_INT_EN_8814B BIT(23)
+#define BIT_PS_TIMER_B_EARLY_INT_EN_8814B BIT(22)
+#define BIT_PS_TIMER_A_EARLY_INT_EN_8814B BIT(21)
+#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_EN_8814B BIT(20)
+#define BIT_PS_TIMER_C_INT_EN_8814B BIT(19)
+#define BIT_PS_TIMER_B_INT_EN_8814B BIT(18)
+#define BIT_PS_TIMER_A_INT_EN_8814B BIT(17)
+#define BIT_CPUMGQ_TX_TIMER_INT_EN_8814B BIT(16)
+#define BIT_FS_PS_TIMEOUT2_EN_8814B BIT(15)
+#define BIT_FS_PS_TIMEOUT1_EN_8814B BIT(14)
+#define BIT_FS_PS_TIMEOUT0_EN_8814B BIT(13)
+#define BIT_FS_GTINT12_EN_8814B BIT(12)
+#define BIT_FS_GTINT11_EN_8814B BIT(11)
+#define BIT_FS_GTINT10_EN_8814B BIT(10)
+#define BIT_FS_GTINT9_EN_8814B BIT(9)
+#define BIT_FS_GTINT8_EN_8814B BIT(8)
+#define BIT_FS_GTINT7_EN_8814B BIT(7)
+#define BIT_FS_GTINT6_EN_8814B BIT(6)
+#define BIT_FS_GTINT5_EN_8814B BIT(5)
+#define BIT_FS_GTINT4_EN_8814B BIT(4)
+#define BIT_FS_GTINT3_EN_8814B BIT(3)
+#define BIT_FS_GTINT2_EN_8814B BIT(2)
+#define BIT_FS_GTINT1_EN_8814B BIT(1)
+#define BIT_FS_GTINT0_EN_8814B BIT(0)
+
+/* 2 REG_FTISR_8814B */
+#define BIT_PS_TIMER_5_EARLY__INT_8814B BIT(26)
+#define BIT_PS_TIMER_4_EARLY__INT_8814B BIT(25)
+#define BIT_PS_TIMER_3_EARLY__INT_8814B BIT(24)
+#define BIT_PS_TIMER_2_EARLY__INT_8814B BIT(23)
+#define BIT_PS_TIMER_1_EARLY__INT_8814B BIT(22)
+#define BIT_PS_TIMER_0_EARLY__INT_8814B BIT(21)
+#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_8814B BIT(20)
+#define BIT_PS_TIMER_5_INT_8814B BIT(19)
+#define BIT_PS_TIMER_4_INT_8814B BIT(18)
+#define BIT_PS_TIMER_3_INT_8814B BIT(17)
+#define BIT_CPUMGQ_TX_TIMER_INT_8814B BIT(16)
+#define BIT_PS_TIMER_2_INT_8814B BIT(15)
+#define BIT_PS_TIMER_1_INT_8814B BIT(14)
+#define BIT_PS_TIMER_0_INT_8814B BIT(13)
+#define BIT_FS_GTINT12_INT_8814B BIT(12)
+#define BIT_FS_GTINT11_INT_8814B BIT(11)
+#define BIT_FS_GTINT10_INT_8814B BIT(10)
+#define BIT_FS_GTINT9_INT_8814B BIT(9)
+#define BIT_FS_GTINT8_INT_8814B BIT(8)
+#define BIT_FS_GTINT7_INT_8814B BIT(7)
+#define BIT_FS_GTINT6_INT_8814B BIT(6)
+#define BIT_FS_GTINT5_INT_8814B BIT(5)
+#define BIT_FS_GTINT4_INT_8814B BIT(4)
+#define BIT_FS_GTINT3_INT_8814B BIT(3)
+#define BIT_FS_GTINT2_INT_8814B BIT(2)
+#define BIT_FS_GTINT1_INT_8814B BIT(1)
+#define BIT_FS_GTINT0_INT_8814B BIT(0)
+
+/* 2 REG_PKTBUF_DBG_CTRL_8814B */
+
+#define BIT_SHIFT_PKTBUF_WRITE_EN_8814B 24
+#define BIT_MASK_PKTBUF_WRITE_EN_8814B 0xff
+#define BIT_PKTBUF_WRITE_EN_8814B(x) \
+ (((x) & BIT_MASK_PKTBUF_WRITE_EN_8814B) \
+ << BIT_SHIFT_PKTBUF_WRITE_EN_8814B)
+#define BITS_PKTBUF_WRITE_EN_8814B \
+ (BIT_MASK_PKTBUF_WRITE_EN_8814B << BIT_SHIFT_PKTBUF_WRITE_EN_8814B)
+#define BIT_CLEAR_PKTBUF_WRITE_EN_8814B(x) ((x) & (~BITS_PKTBUF_WRITE_EN_8814B))
+#define BIT_GET_PKTBUF_WRITE_EN_8814B(x) \
+ (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8814B) & \
+ BIT_MASK_PKTBUF_WRITE_EN_8814B)
+#define BIT_SET_PKTBUF_WRITE_EN_8814B(x, v) \
+ (BIT_CLEAR_PKTBUF_WRITE_EN_8814B(x) | BIT_PKTBUF_WRITE_EN_8814B(v))
+
+#define BIT_TXRPTBUF_DBG_8814B BIT(23)
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_TXPKTBUF_DBG_V2_8814B BIT(20)
+#define BIT_RXPKTBUF_DBG_8814B BIT(16)
+
+#define BIT_SHIFT_PKTBUF_DBG_ADDR_8814B 0
+#define BIT_MASK_PKTBUF_DBG_ADDR_8814B 0x1fff
+#define BIT_PKTBUF_DBG_ADDR_8814B(x) \
+ (((x) & BIT_MASK_PKTBUF_DBG_ADDR_8814B) \
+ << BIT_SHIFT_PKTBUF_DBG_ADDR_8814B)
+#define BITS_PKTBUF_DBG_ADDR_8814B \
+ (BIT_MASK_PKTBUF_DBG_ADDR_8814B << BIT_SHIFT_PKTBUF_DBG_ADDR_8814B)
+#define BIT_CLEAR_PKTBUF_DBG_ADDR_8814B(x) ((x) & (~BITS_PKTBUF_DBG_ADDR_8814B))
+#define BIT_GET_PKTBUF_DBG_ADDR_8814B(x) \
+ (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8814B) & \
+ BIT_MASK_PKTBUF_DBG_ADDR_8814B)
+#define BIT_SET_PKTBUF_DBG_ADDR_8814B(x, v) \
+ (BIT_CLEAR_PKTBUF_DBG_ADDR_8814B(x) | BIT_PKTBUF_DBG_ADDR_8814B(v))
+
+/* 2 REG_PKTBUF_DBG_DATA_L_8814B */
+
+#define BIT_SHIFT_PKTBUF_DBG_DATA_L_8814B 0
+#define BIT_MASK_PKTBUF_DBG_DATA_L_8814B 0xffffffffL
+#define BIT_PKTBUF_DBG_DATA_L_8814B(x) \
+ (((x) & BIT_MASK_PKTBUF_DBG_DATA_L_8814B) \
+ << BIT_SHIFT_PKTBUF_DBG_DATA_L_8814B)
+#define BITS_PKTBUF_DBG_DATA_L_8814B \
+ (BIT_MASK_PKTBUF_DBG_DATA_L_8814B << BIT_SHIFT_PKTBUF_DBG_DATA_L_8814B)
+#define BIT_CLEAR_PKTBUF_DBG_DATA_L_8814B(x) \
+ ((x) & (~BITS_PKTBUF_DBG_DATA_L_8814B))
+#define BIT_GET_PKTBUF_DBG_DATA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8814B) & \
+ BIT_MASK_PKTBUF_DBG_DATA_L_8814B)
+#define BIT_SET_PKTBUF_DBG_DATA_L_8814B(x, v) \
+ (BIT_CLEAR_PKTBUF_DBG_DATA_L_8814B(x) | BIT_PKTBUF_DBG_DATA_L_8814B(v))
+
+/* 2 REG_PKTBUF_DBG_DATA_H_8814B */
+
+#define BIT_SHIFT_PKTBUF_DBG_DATA_H_8814B 0
+#define BIT_MASK_PKTBUF_DBG_DATA_H_8814B 0xffffffffL
+#define BIT_PKTBUF_DBG_DATA_H_8814B(x) \
+ (((x) & BIT_MASK_PKTBUF_DBG_DATA_H_8814B) \
+ << BIT_SHIFT_PKTBUF_DBG_DATA_H_8814B)
+#define BITS_PKTBUF_DBG_DATA_H_8814B \
+ (BIT_MASK_PKTBUF_DBG_DATA_H_8814B << BIT_SHIFT_PKTBUF_DBG_DATA_H_8814B)
+#define BIT_CLEAR_PKTBUF_DBG_DATA_H_8814B(x) \
+ ((x) & (~BITS_PKTBUF_DBG_DATA_H_8814B))
+#define BIT_GET_PKTBUF_DBG_DATA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8814B) & \
+ BIT_MASK_PKTBUF_DBG_DATA_H_8814B)
+#define BIT_SET_PKTBUF_DBG_DATA_H_8814B(x, v) \
+ (BIT_CLEAR_PKTBUF_DBG_DATA_H_8814B(x) | BIT_PKTBUF_DBG_DATA_H_8814B(v))
+
+/* 2 REG_CPWM2_8814B */
+
+#define BIT_SHIFT_L0S_TO_RCVY_NUM_8814B 16
+#define BIT_MASK_L0S_TO_RCVY_NUM_8814B 0xff
+#define BIT_L0S_TO_RCVY_NUM_8814B(x) \
+ (((x) & BIT_MASK_L0S_TO_RCVY_NUM_8814B) \
+ << BIT_SHIFT_L0S_TO_RCVY_NUM_8814B)
+#define BITS_L0S_TO_RCVY_NUM_8814B \
+ (BIT_MASK_L0S_TO_RCVY_NUM_8814B << BIT_SHIFT_L0S_TO_RCVY_NUM_8814B)
+#define BIT_CLEAR_L0S_TO_RCVY_NUM_8814B(x) ((x) & (~BITS_L0S_TO_RCVY_NUM_8814B))
+#define BIT_GET_L0S_TO_RCVY_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8814B) & \
+ BIT_MASK_L0S_TO_RCVY_NUM_8814B)
+#define BIT_SET_L0S_TO_RCVY_NUM_8814B(x, v) \
+ (BIT_CLEAR_L0S_TO_RCVY_NUM_8814B(x) | BIT_L0S_TO_RCVY_NUM_8814B(v))
+
+#define BIT_CPWM2_TOGGLING_8814B BIT(15)
+
+#define BIT_SHIFT_CPWM2_MOD_8814B 0
+#define BIT_MASK_CPWM2_MOD_8814B 0x7fff
+#define BIT_CPWM2_MOD_8814B(x) \
+ (((x) & BIT_MASK_CPWM2_MOD_8814B) << BIT_SHIFT_CPWM2_MOD_8814B)
+#define BITS_CPWM2_MOD_8814B \
+ (BIT_MASK_CPWM2_MOD_8814B << BIT_SHIFT_CPWM2_MOD_8814B)
+#define BIT_CLEAR_CPWM2_MOD_8814B(x) ((x) & (~BITS_CPWM2_MOD_8814B))
+#define BIT_GET_CPWM2_MOD_8814B(x) \
+ (((x) >> BIT_SHIFT_CPWM2_MOD_8814B) & BIT_MASK_CPWM2_MOD_8814B)
+#define BIT_SET_CPWM2_MOD_8814B(x, v) \
+ (BIT_CLEAR_CPWM2_MOD_8814B(x) | BIT_CPWM2_MOD_8814B(v))
+
+/* 2 REG_TC0_CTRL_8814B */
+#define BIT_TC0INT_EN_8814B BIT(26)
+#define BIT_TC0MODE_8814B BIT(25)
+#define BIT_TC0EN_8814B BIT(24)
+
+#define BIT_SHIFT_TC0DATA_8814B 0
+#define BIT_MASK_TC0DATA_8814B 0xffffff
+#define BIT_TC0DATA_8814B(x) \
+ (((x) & BIT_MASK_TC0DATA_8814B) << BIT_SHIFT_TC0DATA_8814B)
+#define BITS_TC0DATA_8814B (BIT_MASK_TC0DATA_8814B << BIT_SHIFT_TC0DATA_8814B)
+#define BIT_CLEAR_TC0DATA_8814B(x) ((x) & (~BITS_TC0DATA_8814B))
+#define BIT_GET_TC0DATA_8814B(x) \
+ (((x) >> BIT_SHIFT_TC0DATA_8814B) & BIT_MASK_TC0DATA_8814B)
+#define BIT_SET_TC0DATA_8814B(x, v) \
+ (BIT_CLEAR_TC0DATA_8814B(x) | BIT_TC0DATA_8814B(v))
+
+/* 2 REG_TC1_CTRL_8814B */
+#define BIT_TC1INT_EN_8814B BIT(26)
+#define BIT_TC1MODE_8814B BIT(25)
+#define BIT_TC1EN_8814B BIT(24)
+
+#define BIT_SHIFT_TC1DATA_8814B 0
+#define BIT_MASK_TC1DATA_8814B 0xffffff
+#define BIT_TC1DATA_8814B(x) \
+ (((x) & BIT_MASK_TC1DATA_8814B) << BIT_SHIFT_TC1DATA_8814B)
+#define BITS_TC1DATA_8814B (BIT_MASK_TC1DATA_8814B << BIT_SHIFT_TC1DATA_8814B)
+#define BIT_CLEAR_TC1DATA_8814B(x) ((x) & (~BITS_TC1DATA_8814B))
+#define BIT_GET_TC1DATA_8814B(x) \
+ (((x) >> BIT_SHIFT_TC1DATA_8814B) & BIT_MASK_TC1DATA_8814B)
+#define BIT_SET_TC1DATA_8814B(x, v) \
+ (BIT_CLEAR_TC1DATA_8814B(x) | BIT_TC1DATA_8814B(v))
+
+/* 2 REG_TC2_CTRL_8814B */
+#define BIT_TC2INT_EN_8814B BIT(26)
+#define BIT_TC2MODE_8814B BIT(25)
+#define BIT_TC2EN_8814B BIT(24)
+
+#define BIT_SHIFT_TC2DATA_8814B 0
+#define BIT_MASK_TC2DATA_8814B 0xffffff
+#define BIT_TC2DATA_8814B(x) \
+ (((x) & BIT_MASK_TC2DATA_8814B) << BIT_SHIFT_TC2DATA_8814B)
+#define BITS_TC2DATA_8814B (BIT_MASK_TC2DATA_8814B << BIT_SHIFT_TC2DATA_8814B)
+#define BIT_CLEAR_TC2DATA_8814B(x) ((x) & (~BITS_TC2DATA_8814B))
+#define BIT_GET_TC2DATA_8814B(x) \
+ (((x) >> BIT_SHIFT_TC2DATA_8814B) & BIT_MASK_TC2DATA_8814B)
+#define BIT_SET_TC2DATA_8814B(x, v) \
+ (BIT_CLEAR_TC2DATA_8814B(x) | BIT_TC2DATA_8814B(v))
+
+/* 2 REG_TC3_CTRL_8814B */
+#define BIT_TC3INT_EN_8814B BIT(26)
+#define BIT_TC3MODE_8814B BIT(25)
+#define BIT_TC3EN_8814B BIT(24)
+
+#define BIT_SHIFT_TC3DATA_8814B 0
+#define BIT_MASK_TC3DATA_8814B 0xffffff
+#define BIT_TC3DATA_8814B(x) \
+ (((x) & BIT_MASK_TC3DATA_8814B) << BIT_SHIFT_TC3DATA_8814B)
+#define BITS_TC3DATA_8814B (BIT_MASK_TC3DATA_8814B << BIT_SHIFT_TC3DATA_8814B)
+#define BIT_CLEAR_TC3DATA_8814B(x) ((x) & (~BITS_TC3DATA_8814B))
+#define BIT_GET_TC3DATA_8814B(x) \
+ (((x) >> BIT_SHIFT_TC3DATA_8814B) & BIT_MASK_TC3DATA_8814B)
+#define BIT_SET_TC3DATA_8814B(x, v) \
+ (BIT_CLEAR_TC3DATA_8814B(x) | BIT_TC3DATA_8814B(v))
+
+/* 2 REG_TC4_CTRL_8814B */
+#define BIT_TC4INT_EN_8814B BIT(26)
+#define BIT_TC4MODE_8814B BIT(25)
+#define BIT_TC4EN_8814B BIT(24)
+
+#define BIT_SHIFT_TC4DATA_8814B 0
+#define BIT_MASK_TC4DATA_8814B 0xffffff
+#define BIT_TC4DATA_8814B(x) \
+ (((x) & BIT_MASK_TC4DATA_8814B) << BIT_SHIFT_TC4DATA_8814B)
+#define BITS_TC4DATA_8814B (BIT_MASK_TC4DATA_8814B << BIT_SHIFT_TC4DATA_8814B)
+#define BIT_CLEAR_TC4DATA_8814B(x) ((x) & (~BITS_TC4DATA_8814B))
+#define BIT_GET_TC4DATA_8814B(x) \
+ (((x) >> BIT_SHIFT_TC4DATA_8814B) & BIT_MASK_TC4DATA_8814B)
+#define BIT_SET_TC4DATA_8814B(x, v) \
+ (BIT_CLEAR_TC4DATA_8814B(x) | BIT_TC4DATA_8814B(v))
+
+/* 2 REG_TCUNIT_BASE_8814B */
+
+#define BIT_SHIFT_TCUNIT_BASE_8814B 0
+#define BIT_MASK_TCUNIT_BASE_8814B 0x3fff
+#define BIT_TCUNIT_BASE_8814B(x) \
+ (((x) & BIT_MASK_TCUNIT_BASE_8814B) << BIT_SHIFT_TCUNIT_BASE_8814B)
+#define BITS_TCUNIT_BASE_8814B \
+ (BIT_MASK_TCUNIT_BASE_8814B << BIT_SHIFT_TCUNIT_BASE_8814B)
+#define BIT_CLEAR_TCUNIT_BASE_8814B(x) ((x) & (~BITS_TCUNIT_BASE_8814B))
+#define BIT_GET_TCUNIT_BASE_8814B(x) \
+ (((x) >> BIT_SHIFT_TCUNIT_BASE_8814B) & BIT_MASK_TCUNIT_BASE_8814B)
+#define BIT_SET_TCUNIT_BASE_8814B(x, v) \
+ (BIT_CLEAR_TCUNIT_BASE_8814B(x) | BIT_TCUNIT_BASE_8814B(v))
+
+/* 2 REG_TC5_CTRL_8814B */
+#define BIT_TC5INT_EN_8814B BIT(26)
+#define BIT_TC5MODE_8814B BIT(25)
+#define BIT_TC5EN_8814B BIT(24)
+
+#define BIT_SHIFT_TC5DATA_8814B 0
+#define BIT_MASK_TC5DATA_8814B 0xffffff
+#define BIT_TC5DATA_8814B(x) \
+ (((x) & BIT_MASK_TC5DATA_8814B) << BIT_SHIFT_TC5DATA_8814B)
+#define BITS_TC5DATA_8814B (BIT_MASK_TC5DATA_8814B << BIT_SHIFT_TC5DATA_8814B)
+#define BIT_CLEAR_TC5DATA_8814B(x) ((x) & (~BITS_TC5DATA_8814B))
+#define BIT_GET_TC5DATA_8814B(x) \
+ (((x) >> BIT_SHIFT_TC5DATA_8814B) & BIT_MASK_TC5DATA_8814B)
+#define BIT_SET_TC5DATA_8814B(x, v) \
+ (BIT_CLEAR_TC5DATA_8814B(x) | BIT_TC5DATA_8814B(v))
+
+/* 2 REG_TC6_CTRL_8814B */
+#define BIT_TC6INT_EN_8814B BIT(26)
+#define BIT_TC6MODE_8814B BIT(25)
+#define BIT_TC6EN_8814B BIT(24)
+
+#define BIT_SHIFT_TC6DATA_8814B 0
+#define BIT_MASK_TC6DATA_8814B 0xffffff
+#define BIT_TC6DATA_8814B(x) \
+ (((x) & BIT_MASK_TC6DATA_8814B) << BIT_SHIFT_TC6DATA_8814B)
+#define BITS_TC6DATA_8814B (BIT_MASK_TC6DATA_8814B << BIT_SHIFT_TC6DATA_8814B)
+#define BIT_CLEAR_TC6DATA_8814B(x) ((x) & (~BITS_TC6DATA_8814B))
+#define BIT_GET_TC6DATA_8814B(x) \
+ (((x) >> BIT_SHIFT_TC6DATA_8814B) & BIT_MASK_TC6DATA_8814B)
+#define BIT_SET_TC6DATA_8814B(x, v) \
+ (BIT_CLEAR_TC6DATA_8814B(x) | BIT_TC6DATA_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_AES_DECRPT_DATA_8814B */
+
+#define BIT_SHIFT_IPS_CFG_ADDR_8814B 0
+#define BIT_MASK_IPS_CFG_ADDR_8814B 0xff
+#define BIT_IPS_CFG_ADDR_8814B(x) \
+ (((x) & BIT_MASK_IPS_CFG_ADDR_8814B) << BIT_SHIFT_IPS_CFG_ADDR_8814B)
+#define BITS_IPS_CFG_ADDR_8814B \
+ (BIT_MASK_IPS_CFG_ADDR_8814B << BIT_SHIFT_IPS_CFG_ADDR_8814B)
+#define BIT_CLEAR_IPS_CFG_ADDR_8814B(x) ((x) & (~BITS_IPS_CFG_ADDR_8814B))
+#define BIT_GET_IPS_CFG_ADDR_8814B(x) \
+ (((x) >> BIT_SHIFT_IPS_CFG_ADDR_8814B) & BIT_MASK_IPS_CFG_ADDR_8814B)
+#define BIT_SET_IPS_CFG_ADDR_8814B(x, v) \
+ (BIT_CLEAR_IPS_CFG_ADDR_8814B(x) | BIT_IPS_CFG_ADDR_8814B(v))
+
+/* 2 REG_AES_DECRPT_CFG_8814B */
+
+#define BIT_SHIFT_IPS_CFG_DATA_8814B 0
+#define BIT_MASK_IPS_CFG_DATA_8814B 0xffffffffL
+#define BIT_IPS_CFG_DATA_8814B(x) \
+ (((x) & BIT_MASK_IPS_CFG_DATA_8814B) << BIT_SHIFT_IPS_CFG_DATA_8814B)
+#define BITS_IPS_CFG_DATA_8814B \
+ (BIT_MASK_IPS_CFG_DATA_8814B << BIT_SHIFT_IPS_CFG_DATA_8814B)
+#define BIT_CLEAR_IPS_CFG_DATA_8814B(x) ((x) & (~BITS_IPS_CFG_DATA_8814B))
+#define BIT_GET_IPS_CFG_DATA_8814B(x) \
+ (((x) >> BIT_SHIFT_IPS_CFG_DATA_8814B) & BIT_MASK_IPS_CFG_DATA_8814B)
+#define BIT_SET_IPS_CFG_DATA_8814B(x, v) \
+ (BIT_CLEAR_IPS_CFG_DATA_8814B(x) | BIT_IPS_CFG_DATA_8814B(v))
+
+/* 2 REG_HIOE_CTRL_8814B */
+#define BIT_HIOE_WRITE_REQ_8814B BIT(30)
+#define BIT_HIOE_READ_REQ_8814B BIT(29)
+#define BIT_INST_FORMAT_ERR_8814B BIT(25)
+#define BIT_OP_TIMEOUT_ERR_8814B BIT(24)
+
+#define BIT_SHIFT_HIOE_OP_TIMEOUT_8814B 16
+#define BIT_MASK_HIOE_OP_TIMEOUT_8814B 0xff
+#define BIT_HIOE_OP_TIMEOUT_8814B(x) \
+ (((x) & BIT_MASK_HIOE_OP_TIMEOUT_8814B) \
+ << BIT_SHIFT_HIOE_OP_TIMEOUT_8814B)
+#define BITS_HIOE_OP_TIMEOUT_8814B \
+ (BIT_MASK_HIOE_OP_TIMEOUT_8814B << BIT_SHIFT_HIOE_OP_TIMEOUT_8814B)
+#define BIT_CLEAR_HIOE_OP_TIMEOUT_8814B(x) ((x) & (~BITS_HIOE_OP_TIMEOUT_8814B))
+#define BIT_GET_HIOE_OP_TIMEOUT_8814B(x) \
+ (((x) >> BIT_SHIFT_HIOE_OP_TIMEOUT_8814B) & \
+ BIT_MASK_HIOE_OP_TIMEOUT_8814B)
+#define BIT_SET_HIOE_OP_TIMEOUT_8814B(x, v) \
+ (BIT_CLEAR_HIOE_OP_TIMEOUT_8814B(x) | BIT_HIOE_OP_TIMEOUT_8814B(v))
+
+#define BIT_SHIFT_BITDATA_CHECKSUM_8814B 0
+#define BIT_MASK_BITDATA_CHECKSUM_8814B 0xffff
+#define BIT_BITDATA_CHECKSUM_8814B(x) \
+ (((x) & BIT_MASK_BITDATA_CHECKSUM_8814B) \
+ << BIT_SHIFT_BITDATA_CHECKSUM_8814B)
+#define BITS_BITDATA_CHECKSUM_8814B \
+ (BIT_MASK_BITDATA_CHECKSUM_8814B << BIT_SHIFT_BITDATA_CHECKSUM_8814B)
+#define BIT_CLEAR_BITDATA_CHECKSUM_8814B(x) \
+ ((x) & (~BITS_BITDATA_CHECKSUM_8814B))
+#define BIT_GET_BITDATA_CHECKSUM_8814B(x) \
+ (((x) >> BIT_SHIFT_BITDATA_CHECKSUM_8814B) & \
+ BIT_MASK_BITDATA_CHECKSUM_8814B)
+#define BIT_SET_BITDATA_CHECKSUM_8814B(x, v) \
+ (BIT_CLEAR_BITDATA_CHECKSUM_8814B(x) | BIT_BITDATA_CHECKSUM_8814B(v))
+
+/* 2 REG_HIOE_CFG_FILE_8814B */
+
+#define BIT_SHIFT_TXBF_END_ADDR_8814B 16
+#define BIT_MASK_TXBF_END_ADDR_8814B 0xffff
+#define BIT_TXBF_END_ADDR_8814B(x) \
+ (((x) & BIT_MASK_TXBF_END_ADDR_8814B) << BIT_SHIFT_TXBF_END_ADDR_8814B)
+#define BITS_TXBF_END_ADDR_8814B \
+ (BIT_MASK_TXBF_END_ADDR_8814B << BIT_SHIFT_TXBF_END_ADDR_8814B)
+#define BIT_CLEAR_TXBF_END_ADDR_8814B(x) ((x) & (~BITS_TXBF_END_ADDR_8814B))
+#define BIT_GET_TXBF_END_ADDR_8814B(x) \
+ (((x) >> BIT_SHIFT_TXBF_END_ADDR_8814B) & BIT_MASK_TXBF_END_ADDR_8814B)
+#define BIT_SET_TXBF_END_ADDR_8814B(x, v) \
+ (BIT_CLEAR_TXBF_END_ADDR_8814B(x) | BIT_TXBF_END_ADDR_8814B(v))
+
+#define BIT_SHIFT_TXBF_STR_ADDR_8814B 0
+#define BIT_MASK_TXBF_STR_ADDR_8814B 0xffff
+#define BIT_TXBF_STR_ADDR_8814B(x) \
+ (((x) & BIT_MASK_TXBF_STR_ADDR_8814B) << BIT_SHIFT_TXBF_STR_ADDR_8814B)
+#define BITS_TXBF_STR_ADDR_8814B \
+ (BIT_MASK_TXBF_STR_ADDR_8814B << BIT_SHIFT_TXBF_STR_ADDR_8814B)
+#define BIT_CLEAR_TXBF_STR_ADDR_8814B(x) ((x) & (~BITS_TXBF_STR_ADDR_8814B))
+#define BIT_GET_TXBF_STR_ADDR_8814B(x) \
+ (((x) >> BIT_SHIFT_TXBF_STR_ADDR_8814B) & BIT_MASK_TXBF_STR_ADDR_8814B)
+#define BIT_SET_TXBF_STR_ADDR_8814B(x, v) \
+ (BIT_CLEAR_TXBF_STR_ADDR_8814B(x) | BIT_TXBF_STR_ADDR_8814B(v))
+
+/* 2 REG_TMETER_8814B */
+#define BIT_TEMP_VALID_8814B BIT(31)
+
+#define BIT_SHIFT_TEMP_VALUE_8814B 24
+#define BIT_MASK_TEMP_VALUE_8814B 0x3f
+#define BIT_TEMP_VALUE_8814B(x) \
+ (((x) & BIT_MASK_TEMP_VALUE_8814B) << BIT_SHIFT_TEMP_VALUE_8814B)
+#define BITS_TEMP_VALUE_8814B \
+ (BIT_MASK_TEMP_VALUE_8814B << BIT_SHIFT_TEMP_VALUE_8814B)
+#define BIT_CLEAR_TEMP_VALUE_8814B(x) ((x) & (~BITS_TEMP_VALUE_8814B))
+#define BIT_GET_TEMP_VALUE_8814B(x) \
+ (((x) >> BIT_SHIFT_TEMP_VALUE_8814B) & BIT_MASK_TEMP_VALUE_8814B)
+#define BIT_SET_TEMP_VALUE_8814B(x, v) \
+ (BIT_CLEAR_TEMP_VALUE_8814B(x) | BIT_TEMP_VALUE_8814B(v))
+
+#define BIT_SHIFT_REG_TMETER_TIMER_8814B 8
+#define BIT_MASK_REG_TMETER_TIMER_8814B 0xfff
+#define BIT_REG_TMETER_TIMER_8814B(x) \
+ (((x) & BIT_MASK_REG_TMETER_TIMER_8814B) \
+ << BIT_SHIFT_REG_TMETER_TIMER_8814B)
+#define BITS_REG_TMETER_TIMER_8814B \
+ (BIT_MASK_REG_TMETER_TIMER_8814B << BIT_SHIFT_REG_TMETER_TIMER_8814B)
+#define BIT_CLEAR_REG_TMETER_TIMER_8814B(x) \
+ ((x) & (~BITS_REG_TMETER_TIMER_8814B))
+#define BIT_GET_REG_TMETER_TIMER_8814B(x) \
+ (((x) >> BIT_SHIFT_REG_TMETER_TIMER_8814B) & \
+ BIT_MASK_REG_TMETER_TIMER_8814B)
+#define BIT_SET_REG_TMETER_TIMER_8814B(x, v) \
+ (BIT_CLEAR_REG_TMETER_TIMER_8814B(x) | BIT_REG_TMETER_TIMER_8814B(v))
+
+#define BIT_SHIFT_REG_TEMP_DELTA_8814B 2
+#define BIT_MASK_REG_TEMP_DELTA_8814B 0x3f
+#define BIT_REG_TEMP_DELTA_8814B(x) \
+ (((x) & BIT_MASK_REG_TEMP_DELTA_8814B) \
+ << BIT_SHIFT_REG_TEMP_DELTA_8814B)
+#define BITS_REG_TEMP_DELTA_8814B \
+ (BIT_MASK_REG_TEMP_DELTA_8814B << BIT_SHIFT_REG_TEMP_DELTA_8814B)
+#define BIT_CLEAR_REG_TEMP_DELTA_8814B(x) ((x) & (~BITS_REG_TEMP_DELTA_8814B))
+#define BIT_GET_REG_TEMP_DELTA_8814B(x) \
+ (((x) >> BIT_SHIFT_REG_TEMP_DELTA_8814B) & \
+ BIT_MASK_REG_TEMP_DELTA_8814B)
+#define BIT_SET_REG_TEMP_DELTA_8814B(x, v) \
+ (BIT_CLEAR_REG_TEMP_DELTA_8814B(x) | BIT_REG_TEMP_DELTA_8814B(v))
+
+#define BIT_REG_TMETER_EN_8814B BIT(0)
+
+/* 2 REG_OSC_32K_CTRL_8814B */
+
+#define BIT_SHIFT_OSC_32K_CLKGEN_0_8814B 16
+#define BIT_MASK_OSC_32K_CLKGEN_0_8814B 0xffff
+#define BIT_OSC_32K_CLKGEN_0_8814B(x) \
+ (((x) & BIT_MASK_OSC_32K_CLKGEN_0_8814B) \
+ << BIT_SHIFT_OSC_32K_CLKGEN_0_8814B)
+#define BITS_OSC_32K_CLKGEN_0_8814B \
+ (BIT_MASK_OSC_32K_CLKGEN_0_8814B << BIT_SHIFT_OSC_32K_CLKGEN_0_8814B)
+#define BIT_CLEAR_OSC_32K_CLKGEN_0_8814B(x) \
+ ((x) & (~BITS_OSC_32K_CLKGEN_0_8814B))
+#define BIT_GET_OSC_32K_CLKGEN_0_8814B(x) \
+ (((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0_8814B) & \
+ BIT_MASK_OSC_32K_CLKGEN_0_8814B)
+#define BIT_SET_OSC_32K_CLKGEN_0_8814B(x, v) \
+ (BIT_CLEAR_OSC_32K_CLKGEN_0_8814B(x) | BIT_OSC_32K_CLKGEN_0_8814B(v))
+
+#define BIT_SHIFT_OSC_32K_RES_COMP_8814B 4
+#define BIT_MASK_OSC_32K_RES_COMP_8814B 0x3
+#define BIT_OSC_32K_RES_COMP_8814B(x) \
+ (((x) & BIT_MASK_OSC_32K_RES_COMP_8814B) \
+ << BIT_SHIFT_OSC_32K_RES_COMP_8814B)
+#define BITS_OSC_32K_RES_COMP_8814B \
+ (BIT_MASK_OSC_32K_RES_COMP_8814B << BIT_SHIFT_OSC_32K_RES_COMP_8814B)
+#define BIT_CLEAR_OSC_32K_RES_COMP_8814B(x) \
+ ((x) & (~BITS_OSC_32K_RES_COMP_8814B))
+#define BIT_GET_OSC_32K_RES_COMP_8814B(x) \
+ (((x) >> BIT_SHIFT_OSC_32K_RES_COMP_8814B) & \
+ BIT_MASK_OSC_32K_RES_COMP_8814B)
+#define BIT_SET_OSC_32K_RES_COMP_8814B(x, v) \
+ (BIT_CLEAR_OSC_32K_RES_COMP_8814B(x) | BIT_OSC_32K_RES_COMP_8814B(v))
+
+#define BIT_OSC_32K_OUT_SEL_8814B BIT(3)
+#define BIT_ISO_WL_2_OSC_32K_8814B BIT(1)
+#define BIT_POW_CKGEN_8814B BIT(0)
+
+/* 2 REG_32K_CAL_REG1_8814B */
+#define BIT_CAL_32K_REG_WR_8814B BIT(31)
+#define BIT_CAL_32K_DBG_SEL_8814B BIT(22)
+
+#define BIT_SHIFT_CAL_32K_REG_ADDR_8814B 16
+#define BIT_MASK_CAL_32K_REG_ADDR_8814B 0x3f
+#define BIT_CAL_32K_REG_ADDR_8814B(x) \
+ (((x) & BIT_MASK_CAL_32K_REG_ADDR_8814B) \
+ << BIT_SHIFT_CAL_32K_REG_ADDR_8814B)
+#define BITS_CAL_32K_REG_ADDR_8814B \
+ (BIT_MASK_CAL_32K_REG_ADDR_8814B << BIT_SHIFT_CAL_32K_REG_ADDR_8814B)
+#define BIT_CLEAR_CAL_32K_REG_ADDR_8814B(x) \
+ ((x) & (~BITS_CAL_32K_REG_ADDR_8814B))
+#define BIT_GET_CAL_32K_REG_ADDR_8814B(x) \
+ (((x) >> BIT_SHIFT_CAL_32K_REG_ADDR_8814B) & \
+ BIT_MASK_CAL_32K_REG_ADDR_8814B)
+#define BIT_SET_CAL_32K_REG_ADDR_8814B(x, v) \
+ (BIT_CLEAR_CAL_32K_REG_ADDR_8814B(x) | BIT_CAL_32K_REG_ADDR_8814B(v))
+
+#define BIT_SHIFT_CAL_32K_REG_DATA_8814B 0
+#define BIT_MASK_CAL_32K_REG_DATA_8814B 0xffff
+#define BIT_CAL_32K_REG_DATA_8814B(x) \
+ (((x) & BIT_MASK_CAL_32K_REG_DATA_8814B) \
+ << BIT_SHIFT_CAL_32K_REG_DATA_8814B)
+#define BITS_CAL_32K_REG_DATA_8814B \
+ (BIT_MASK_CAL_32K_REG_DATA_8814B << BIT_SHIFT_CAL_32K_REG_DATA_8814B)
+#define BIT_CLEAR_CAL_32K_REG_DATA_8814B(x) \
+ ((x) & (~BITS_CAL_32K_REG_DATA_8814B))
+#define BIT_GET_CAL_32K_REG_DATA_8814B(x) \
+ (((x) >> BIT_SHIFT_CAL_32K_REG_DATA_8814B) & \
+ BIT_MASK_CAL_32K_REG_DATA_8814B)
+#define BIT_SET_CAL_32K_REG_DATA_8814B(x, v) \
+ (BIT_CLEAR_CAL_32K_REG_DATA_8814B(x) | BIT_CAL_32K_REG_DATA_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_C2HEVT_8814B */
+
+#define BIT_SHIFT_C2HEVT_MSG_V1_8814B 0
+#define BIT_MASK_C2HEVT_MSG_V1_8814B 0xffffffffL
+#define BIT_C2HEVT_MSG_V1_8814B(x) \
+ (((x) & BIT_MASK_C2HEVT_MSG_V1_8814B) << BIT_SHIFT_C2HEVT_MSG_V1_8814B)
+#define BITS_C2HEVT_MSG_V1_8814B \
+ (BIT_MASK_C2HEVT_MSG_V1_8814B << BIT_SHIFT_C2HEVT_MSG_V1_8814B)
+#define BIT_CLEAR_C2HEVT_MSG_V1_8814B(x) ((x) & (~BITS_C2HEVT_MSG_V1_8814B))
+#define BIT_GET_C2HEVT_MSG_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_C2HEVT_MSG_V1_8814B) & BIT_MASK_C2HEVT_MSG_V1_8814B)
+#define BIT_SET_C2HEVT_MSG_V1_8814B(x, v) \
+ (BIT_CLEAR_C2HEVT_MSG_V1_8814B(x) | BIT_C2HEVT_MSG_V1_8814B(v))
+
+/* 2 REG_C2HEVT_1_8814B */
+
+#define BIT_SHIFT_C2HEVT_MSG_1_8814B 0
+#define BIT_MASK_C2HEVT_MSG_1_8814B 0xffffffffL
+#define BIT_C2HEVT_MSG_1_8814B(x) \
+ (((x) & BIT_MASK_C2HEVT_MSG_1_8814B) << BIT_SHIFT_C2HEVT_MSG_1_8814B)
+#define BITS_C2HEVT_MSG_1_8814B \
+ (BIT_MASK_C2HEVT_MSG_1_8814B << BIT_SHIFT_C2HEVT_MSG_1_8814B)
+#define BIT_CLEAR_C2HEVT_MSG_1_8814B(x) ((x) & (~BITS_C2HEVT_MSG_1_8814B))
+#define BIT_GET_C2HEVT_MSG_1_8814B(x) \
+ (((x) >> BIT_SHIFT_C2HEVT_MSG_1_8814B) & BIT_MASK_C2HEVT_MSG_1_8814B)
+#define BIT_SET_C2HEVT_MSG_1_8814B(x, v) \
+ (BIT_CLEAR_C2HEVT_MSG_1_8814B(x) | BIT_C2HEVT_MSG_1_8814B(v))
+
+/* 2 REG_C2HEVT_2_8814B */
+
+#define BIT_SHIFT_C2HEVT_MSG_2_8814B 0
+#define BIT_MASK_C2HEVT_MSG_2_8814B 0xffffffffL
+#define BIT_C2HEVT_MSG_2_8814B(x) \
+ (((x) & BIT_MASK_C2HEVT_MSG_2_8814B) << BIT_SHIFT_C2HEVT_MSG_2_8814B)
+#define BITS_C2HEVT_MSG_2_8814B \
+ (BIT_MASK_C2HEVT_MSG_2_8814B << BIT_SHIFT_C2HEVT_MSG_2_8814B)
+#define BIT_CLEAR_C2HEVT_MSG_2_8814B(x) ((x) & (~BITS_C2HEVT_MSG_2_8814B))
+#define BIT_GET_C2HEVT_MSG_2_8814B(x) \
+ (((x) >> BIT_SHIFT_C2HEVT_MSG_2_8814B) & BIT_MASK_C2HEVT_MSG_2_8814B)
+#define BIT_SET_C2HEVT_MSG_2_8814B(x, v) \
+ (BIT_CLEAR_C2HEVT_MSG_2_8814B(x) | BIT_C2HEVT_MSG_2_8814B(v))
+
+/* 2 REG_C2HEVT_3_8814B */
+
+#define BIT_SHIFT_C2HEVT_MSG_3_8814B 0
+#define BIT_MASK_C2HEVT_MSG_3_8814B 0xffffffffL
+#define BIT_C2HEVT_MSG_3_8814B(x) \
+ (((x) & BIT_MASK_C2HEVT_MSG_3_8814B) << BIT_SHIFT_C2HEVT_MSG_3_8814B)
+#define BITS_C2HEVT_MSG_3_8814B \
+ (BIT_MASK_C2HEVT_MSG_3_8814B << BIT_SHIFT_C2HEVT_MSG_3_8814B)
+#define BIT_CLEAR_C2HEVT_MSG_3_8814B(x) ((x) & (~BITS_C2HEVT_MSG_3_8814B))
+#define BIT_GET_C2HEVT_MSG_3_8814B(x) \
+ (((x) >> BIT_SHIFT_C2HEVT_MSG_3_8814B) & BIT_MASK_C2HEVT_MSG_3_8814B)
+#define BIT_SET_C2HEVT_MSG_3_8814B(x, v) \
+ (BIT_CLEAR_C2HEVT_MSG_3_8814B(x) | BIT_C2HEVT_MSG_3_8814B(v))
+
+/* 2 REG_RXDESC_BUFF_RPTR_8814B */
+
+#define BIT_SHIFT_RXDESC_BUFF_RPTR_8814B 0
+#define BIT_MASK_RXDESC_BUFF_RPTR_8814B 0xffffffffL
+#define BIT_RXDESC_BUFF_RPTR_8814B(x) \
+ (((x) & BIT_MASK_RXDESC_BUFF_RPTR_8814B) \
+ << BIT_SHIFT_RXDESC_BUFF_RPTR_8814B)
+#define BITS_RXDESC_BUFF_RPTR_8814B \
+ (BIT_MASK_RXDESC_BUFF_RPTR_8814B << BIT_SHIFT_RXDESC_BUFF_RPTR_8814B)
+#define BIT_CLEAR_RXDESC_BUFF_RPTR_8814B(x) \
+ ((x) & (~BITS_RXDESC_BUFF_RPTR_8814B))
+#define BIT_GET_RXDESC_BUFF_RPTR_8814B(x) \
+ (((x) >> BIT_SHIFT_RXDESC_BUFF_RPTR_8814B) & \
+ BIT_MASK_RXDESC_BUFF_RPTR_8814B)
+#define BIT_SET_RXDESC_BUFF_RPTR_8814B(x, v) \
+ (BIT_CLEAR_RXDESC_BUFF_RPTR_8814B(x) | BIT_RXDESC_BUFF_RPTR_8814B(v))
+
+/* 2 REG_RXDESC_BUFF_WPTR_8814B */
+
+#define BIT_SHIFT_RXDESC_BUFF_WPTR_8814B 0
+#define BIT_MASK_RXDESC_BUFF_WPTR_8814B 0xffffffffL
+#define BIT_RXDESC_BUFF_WPTR_8814B(x) \
+ (((x) & BIT_MASK_RXDESC_BUFF_WPTR_8814B) \
+ << BIT_SHIFT_RXDESC_BUFF_WPTR_8814B)
+#define BITS_RXDESC_BUFF_WPTR_8814B \
+ (BIT_MASK_RXDESC_BUFF_WPTR_8814B << BIT_SHIFT_RXDESC_BUFF_WPTR_8814B)
+#define BIT_CLEAR_RXDESC_BUFF_WPTR_8814B(x) \
+ ((x) & (~BITS_RXDESC_BUFF_WPTR_8814B))
+#define BIT_GET_RXDESC_BUFF_WPTR_8814B(x) \
+ (((x) >> BIT_SHIFT_RXDESC_BUFF_WPTR_8814B) & \
+ BIT_MASK_RXDESC_BUFF_WPTR_8814B)
+#define BIT_SET_RXDESC_BUFF_WPTR_8814B(x, v) \
+ (BIT_CLEAR_RXDESC_BUFF_WPTR_8814B(x) | BIT_RXDESC_BUFF_WPTR_8814B(v))
+
+/* 2 REG_SW_DEFINED_PAGE1_8814B */
+
+#define BIT_SHIFT_SW_DEFINED_PAGE1_V1_8814B 0
+#define BIT_MASK_SW_DEFINED_PAGE1_V1_8814B 0xffffffffL
+#define BIT_SW_DEFINED_PAGE1_V1_8814B(x) \
+ (((x) & BIT_MASK_SW_DEFINED_PAGE1_V1_8814B) \
+ << BIT_SHIFT_SW_DEFINED_PAGE1_V1_8814B)
+#define BITS_SW_DEFINED_PAGE1_V1_8814B \
+ (BIT_MASK_SW_DEFINED_PAGE1_V1_8814B \
+ << BIT_SHIFT_SW_DEFINED_PAGE1_V1_8814B)
+#define BIT_CLEAR_SW_DEFINED_PAGE1_V1_8814B(x) \
+ ((x) & (~BITS_SW_DEFINED_PAGE1_V1_8814B))
+#define BIT_GET_SW_DEFINED_PAGE1_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_V1_8814B) & \
+ BIT_MASK_SW_DEFINED_PAGE1_V1_8814B)
+#define BIT_SET_SW_DEFINED_PAGE1_V1_8814B(x, v) \
+ (BIT_CLEAR_SW_DEFINED_PAGE1_V1_8814B(x) | \
+ BIT_SW_DEFINED_PAGE1_V1_8814B(v))
+
+/* 2 REG_SW_DEFINED_PAGE2_8814B */
+
+#define BIT_SHIFT_SW_DEFINED_PAGE2_8814B 0
+#define BIT_MASK_SW_DEFINED_PAGE2_8814B 0xffffffffL
+#define BIT_SW_DEFINED_PAGE2_8814B(x) \
+ (((x) & BIT_MASK_SW_DEFINED_PAGE2_8814B) \
+ << BIT_SHIFT_SW_DEFINED_PAGE2_8814B)
+#define BITS_SW_DEFINED_PAGE2_8814B \
+ (BIT_MASK_SW_DEFINED_PAGE2_8814B << BIT_SHIFT_SW_DEFINED_PAGE2_8814B)
+#define BIT_CLEAR_SW_DEFINED_PAGE2_8814B(x) \
+ ((x) & (~BITS_SW_DEFINED_PAGE2_8814B))
+#define BIT_GET_SW_DEFINED_PAGE2_8814B(x) \
+ (((x) >> BIT_SHIFT_SW_DEFINED_PAGE2_8814B) & \
+ BIT_MASK_SW_DEFINED_PAGE2_8814B)
+#define BIT_SET_SW_DEFINED_PAGE2_8814B(x, v) \
+ (BIT_CLEAR_SW_DEFINED_PAGE2_8814B(x) | BIT_SW_DEFINED_PAGE2_8814B(v))
+
+/* 2 REG_MCUTST_I_8814B */
+
+#define BIT_SHIFT_MCUDMSG_I_8814B 0
+#define BIT_MASK_MCUDMSG_I_8814B 0xffffffffL
+#define BIT_MCUDMSG_I_8814B(x) \
+ (((x) & BIT_MASK_MCUDMSG_I_8814B) << BIT_SHIFT_MCUDMSG_I_8814B)
+#define BITS_MCUDMSG_I_8814B \
+ (BIT_MASK_MCUDMSG_I_8814B << BIT_SHIFT_MCUDMSG_I_8814B)
+#define BIT_CLEAR_MCUDMSG_I_8814B(x) ((x) & (~BITS_MCUDMSG_I_8814B))
+#define BIT_GET_MCUDMSG_I_8814B(x) \
+ (((x) >> BIT_SHIFT_MCUDMSG_I_8814B) & BIT_MASK_MCUDMSG_I_8814B)
+#define BIT_SET_MCUDMSG_I_8814B(x, v) \
+ (BIT_CLEAR_MCUDMSG_I_8814B(x) | BIT_MCUDMSG_I_8814B(v))
+
+/* 2 REG_MCUTST_II_8814B */
+
+#define BIT_SHIFT_MCUDMSG_II_8814B 0
+#define BIT_MASK_MCUDMSG_II_8814B 0xffffffffL
+#define BIT_MCUDMSG_II_8814B(x) \
+ (((x) & BIT_MASK_MCUDMSG_II_8814B) << BIT_SHIFT_MCUDMSG_II_8814B)
+#define BITS_MCUDMSG_II_8814B \
+ (BIT_MASK_MCUDMSG_II_8814B << BIT_SHIFT_MCUDMSG_II_8814B)
+#define BIT_CLEAR_MCUDMSG_II_8814B(x) ((x) & (~BITS_MCUDMSG_II_8814B))
+#define BIT_GET_MCUDMSG_II_8814B(x) \
+ (((x) >> BIT_SHIFT_MCUDMSG_II_8814B) & BIT_MASK_MCUDMSG_II_8814B)
+#define BIT_SET_MCUDMSG_II_8814B(x, v) \
+ (BIT_CLEAR_MCUDMSG_II_8814B(x) | BIT_MCUDMSG_II_8814B(v))
+
+/* 2 REG_FMETHR_8814B */
+#define BIT_FMSG_INT_8814B BIT(31)
+
+#define BIT_SHIFT_FW_MSG_8814B 0
+#define BIT_MASK_FW_MSG_8814B 0xffffffffL
+#define BIT_FW_MSG_8814B(x) \
+ (((x) & BIT_MASK_FW_MSG_8814B) << BIT_SHIFT_FW_MSG_8814B)
+#define BITS_FW_MSG_8814B (BIT_MASK_FW_MSG_8814B << BIT_SHIFT_FW_MSG_8814B)
+#define BIT_CLEAR_FW_MSG_8814B(x) ((x) & (~BITS_FW_MSG_8814B))
+#define BIT_GET_FW_MSG_8814B(x) \
+ (((x) >> BIT_SHIFT_FW_MSG_8814B) & BIT_MASK_FW_MSG_8814B)
+#define BIT_SET_FW_MSG_8814B(x, v) \
+ (BIT_CLEAR_FW_MSG_8814B(x) | BIT_FW_MSG_8814B(v))
+
+/* 2 REG_HMETFR_8814B */
+
+#define BIT_SHIFT_HRCV_MSG_8814B 24
+#define BIT_MASK_HRCV_MSG_8814B 0xff
+#define BIT_HRCV_MSG_8814B(x) \
+ (((x) & BIT_MASK_HRCV_MSG_8814B) << BIT_SHIFT_HRCV_MSG_8814B)
+#define BITS_HRCV_MSG_8814B \
+ (BIT_MASK_HRCV_MSG_8814B << BIT_SHIFT_HRCV_MSG_8814B)
+#define BIT_CLEAR_HRCV_MSG_8814B(x) ((x) & (~BITS_HRCV_MSG_8814B))
+#define BIT_GET_HRCV_MSG_8814B(x) \
+ (((x) >> BIT_SHIFT_HRCV_MSG_8814B) & BIT_MASK_HRCV_MSG_8814B)
+#define BIT_SET_HRCV_MSG_8814B(x, v) \
+ (BIT_CLEAR_HRCV_MSG_8814B(x) | BIT_HRCV_MSG_8814B(v))
+
+#define BIT_INT_BOX3_8814B BIT(3)
+#define BIT_INT_BOX2_8814B BIT(2)
+#define BIT_INT_BOX1_8814B BIT(1)
+#define BIT_INT_BOX0_8814B BIT(0)
+
+/* 2 REG_HMEBOX0_8814B */
+
+#define BIT_SHIFT_HOST_MSG_0_8814B 0
+#define BIT_MASK_HOST_MSG_0_8814B 0xffffffffL
+#define BIT_HOST_MSG_0_8814B(x) \
+ (((x) & BIT_MASK_HOST_MSG_0_8814B) << BIT_SHIFT_HOST_MSG_0_8814B)
+#define BITS_HOST_MSG_0_8814B \
+ (BIT_MASK_HOST_MSG_0_8814B << BIT_SHIFT_HOST_MSG_0_8814B)
+#define BIT_CLEAR_HOST_MSG_0_8814B(x) ((x) & (~BITS_HOST_MSG_0_8814B))
+#define BIT_GET_HOST_MSG_0_8814B(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_0_8814B) & BIT_MASK_HOST_MSG_0_8814B)
+#define BIT_SET_HOST_MSG_0_8814B(x, v) \
+ (BIT_CLEAR_HOST_MSG_0_8814B(x) | BIT_HOST_MSG_0_8814B(v))
+
+/* 2 REG_HMEBOX1_8814B */
+
+#define BIT_SHIFT_HOST_MSG_1_8814B 0
+#define BIT_MASK_HOST_MSG_1_8814B 0xffffffffL
+#define BIT_HOST_MSG_1_8814B(x) \
+ (((x) & BIT_MASK_HOST_MSG_1_8814B) << BIT_SHIFT_HOST_MSG_1_8814B)
+#define BITS_HOST_MSG_1_8814B \
+ (BIT_MASK_HOST_MSG_1_8814B << BIT_SHIFT_HOST_MSG_1_8814B)
+#define BIT_CLEAR_HOST_MSG_1_8814B(x) ((x) & (~BITS_HOST_MSG_1_8814B))
+#define BIT_GET_HOST_MSG_1_8814B(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_1_8814B) & BIT_MASK_HOST_MSG_1_8814B)
+#define BIT_SET_HOST_MSG_1_8814B(x, v) \
+ (BIT_CLEAR_HOST_MSG_1_8814B(x) | BIT_HOST_MSG_1_8814B(v))
+
+/* 2 REG_HMEBOX2_8814B */
+
+#define BIT_SHIFT_HOST_MSG_2_8814B 0
+#define BIT_MASK_HOST_MSG_2_8814B 0xffffffffL
+#define BIT_HOST_MSG_2_8814B(x) \
+ (((x) & BIT_MASK_HOST_MSG_2_8814B) << BIT_SHIFT_HOST_MSG_2_8814B)
+#define BITS_HOST_MSG_2_8814B \
+ (BIT_MASK_HOST_MSG_2_8814B << BIT_SHIFT_HOST_MSG_2_8814B)
+#define BIT_CLEAR_HOST_MSG_2_8814B(x) ((x) & (~BITS_HOST_MSG_2_8814B))
+#define BIT_GET_HOST_MSG_2_8814B(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_2_8814B) & BIT_MASK_HOST_MSG_2_8814B)
+#define BIT_SET_HOST_MSG_2_8814B(x, v) \
+ (BIT_CLEAR_HOST_MSG_2_8814B(x) | BIT_HOST_MSG_2_8814B(v))
+
+/* 2 REG_HMEBOX3_8814B */
+
+#define BIT_SHIFT_HOST_MSG_3_8814B 0
+#define BIT_MASK_HOST_MSG_3_8814B 0xffffffffL
+#define BIT_HOST_MSG_3_8814B(x) \
+ (((x) & BIT_MASK_HOST_MSG_3_8814B) << BIT_SHIFT_HOST_MSG_3_8814B)
+#define BITS_HOST_MSG_3_8814B \
+ (BIT_MASK_HOST_MSG_3_8814B << BIT_SHIFT_HOST_MSG_3_8814B)
+#define BIT_CLEAR_HOST_MSG_3_8814B(x) ((x) & (~BITS_HOST_MSG_3_8814B))
+#define BIT_GET_HOST_MSG_3_8814B(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_3_8814B) & BIT_MASK_HOST_MSG_3_8814B)
+#define BIT_SET_HOST_MSG_3_8814B(x, v) \
+ (BIT_CLEAR_HOST_MSG_3_8814B(x) | BIT_HOST_MSG_3_8814B(v))
+
+/* 2 REG_RXDESC_BUFF_BNDY_8814B */
+
+#define BIT_SHIFT_RXDESC_BUFF_BNDY_8814B 0
+#define BIT_MASK_RXDESC_BUFF_BNDY_8814B 0xffffffffL
+#define BIT_RXDESC_BUFF_BNDY_8814B(x) \
+ (((x) & BIT_MASK_RXDESC_BUFF_BNDY_8814B) \
+ << BIT_SHIFT_RXDESC_BUFF_BNDY_8814B)
+#define BITS_RXDESC_BUFF_BNDY_8814B \
+ (BIT_MASK_RXDESC_BUFF_BNDY_8814B << BIT_SHIFT_RXDESC_BUFF_BNDY_8814B)
+#define BIT_CLEAR_RXDESC_BUFF_BNDY_8814B(x) \
+ ((x) & (~BITS_RXDESC_BUFF_BNDY_8814B))
+#define BIT_GET_RXDESC_BUFF_BNDY_8814B(x) \
+ (((x) >> BIT_SHIFT_RXDESC_BUFF_BNDY_8814B) & \
+ BIT_MASK_RXDESC_BUFF_BNDY_8814B)
+#define BIT_SET_RXDESC_BUFF_BNDY_8814B(x, v) \
+ (BIT_CLEAR_RXDESC_BUFF_BNDY_8814B(x) | BIT_RXDESC_BUFF_BNDY_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_BB_ACCESS_CTRL_8814B */
+
+#define BIT_SHIFT_BB_WRITE_READ_8814B 30
+#define BIT_MASK_BB_WRITE_READ_8814B 0x3
+#define BIT_BB_WRITE_READ_8814B(x) \
+ (((x) & BIT_MASK_BB_WRITE_READ_8814B) << BIT_SHIFT_BB_WRITE_READ_8814B)
+#define BITS_BB_WRITE_READ_8814B \
+ (BIT_MASK_BB_WRITE_READ_8814B << BIT_SHIFT_BB_WRITE_READ_8814B)
+#define BIT_CLEAR_BB_WRITE_READ_8814B(x) ((x) & (~BITS_BB_WRITE_READ_8814B))
+#define BIT_GET_BB_WRITE_READ_8814B(x) \
+ (((x) >> BIT_SHIFT_BB_WRITE_READ_8814B) & BIT_MASK_BB_WRITE_READ_8814B)
+#define BIT_SET_BB_WRITE_READ_8814B(x, v) \
+ (BIT_CLEAR_BB_WRITE_READ_8814B(x) | BIT_BB_WRITE_READ_8814B(v))
+
+#define BIT_SHIFT_BB_WRITE_EN_8814B 12
+#define BIT_MASK_BB_WRITE_EN_8814B 0xf
+#define BIT_BB_WRITE_EN_8814B(x) \
+ (((x) & BIT_MASK_BB_WRITE_EN_8814B) << BIT_SHIFT_BB_WRITE_EN_8814B)
+#define BITS_BB_WRITE_EN_8814B \
+ (BIT_MASK_BB_WRITE_EN_8814B << BIT_SHIFT_BB_WRITE_EN_8814B)
+#define BIT_CLEAR_BB_WRITE_EN_8814B(x) ((x) & (~BITS_BB_WRITE_EN_8814B))
+#define BIT_GET_BB_WRITE_EN_8814B(x) \
+ (((x) >> BIT_SHIFT_BB_WRITE_EN_8814B) & BIT_MASK_BB_WRITE_EN_8814B)
+#define BIT_SET_BB_WRITE_EN_8814B(x, v) \
+ (BIT_CLEAR_BB_WRITE_EN_8814B(x) | BIT_BB_WRITE_EN_8814B(v))
+
+#define BIT_SHIFT_BB_ADDR_8814B 2
+#define BIT_MASK_BB_ADDR_8814B 0x1ff
+#define BIT_BB_ADDR_8814B(x) \
+ (((x) & BIT_MASK_BB_ADDR_8814B) << BIT_SHIFT_BB_ADDR_8814B)
+#define BITS_BB_ADDR_8814B (BIT_MASK_BB_ADDR_8814B << BIT_SHIFT_BB_ADDR_8814B)
+#define BIT_CLEAR_BB_ADDR_8814B(x) ((x) & (~BITS_BB_ADDR_8814B))
+#define BIT_GET_BB_ADDR_8814B(x) \
+ (((x) >> BIT_SHIFT_BB_ADDR_8814B) & BIT_MASK_BB_ADDR_8814B)
+#define BIT_SET_BB_ADDR_8814B(x, v) \
+ (BIT_CLEAR_BB_ADDR_8814B(x) | BIT_BB_ADDR_8814B(v))
+
+#define BIT_BB_ERRACC_8814B BIT(0)
+
+/* 2 REG_BB_ACCESS_DATA_8814B */
+
+#define BIT_SHIFT_BB_DATA_8814B 0
+#define BIT_MASK_BB_DATA_8814B 0xffffffffL
+#define BIT_BB_DATA_8814B(x) \
+ (((x) & BIT_MASK_BB_DATA_8814B) << BIT_SHIFT_BB_DATA_8814B)
+#define BITS_BB_DATA_8814B (BIT_MASK_BB_DATA_8814B << BIT_SHIFT_BB_DATA_8814B)
+#define BIT_CLEAR_BB_DATA_8814B(x) ((x) & (~BITS_BB_DATA_8814B))
+#define BIT_GET_BB_DATA_8814B(x) \
+ (((x) >> BIT_SHIFT_BB_DATA_8814B) & BIT_MASK_BB_DATA_8814B)
+#define BIT_SET_BB_DATA_8814B(x, v) \
+ (BIT_CLEAR_BB_DATA_8814B(x) | BIT_BB_DATA_8814B(v))
+
+/* 2 REG_HMEBOX_E0_8814B */
+
+#define BIT_SHIFT_HMEBOX_E0_8814B 0
+#define BIT_MASK_HMEBOX_E0_8814B 0xffffffffL
+#define BIT_HMEBOX_E0_8814B(x) \
+ (((x) & BIT_MASK_HMEBOX_E0_8814B) << BIT_SHIFT_HMEBOX_E0_8814B)
+#define BITS_HMEBOX_E0_8814B \
+ (BIT_MASK_HMEBOX_E0_8814B << BIT_SHIFT_HMEBOX_E0_8814B)
+#define BIT_CLEAR_HMEBOX_E0_8814B(x) ((x) & (~BITS_HMEBOX_E0_8814B))
+#define BIT_GET_HMEBOX_E0_8814B(x) \
+ (((x) >> BIT_SHIFT_HMEBOX_E0_8814B) & BIT_MASK_HMEBOX_E0_8814B)
+#define BIT_SET_HMEBOX_E0_8814B(x, v) \
+ (BIT_CLEAR_HMEBOX_E0_8814B(x) | BIT_HMEBOX_E0_8814B(v))
+
+/* 2 REG_HMEBOX_E1_8814B */
+
+#define BIT_SHIFT_HMEBOX_E1_8814B 0
+#define BIT_MASK_HMEBOX_E1_8814B 0xffffffffL
+#define BIT_HMEBOX_E1_8814B(x) \
+ (((x) & BIT_MASK_HMEBOX_E1_8814B) << BIT_SHIFT_HMEBOX_E1_8814B)
+#define BITS_HMEBOX_E1_8814B \
+ (BIT_MASK_HMEBOX_E1_8814B << BIT_SHIFT_HMEBOX_E1_8814B)
+#define BIT_CLEAR_HMEBOX_E1_8814B(x) ((x) & (~BITS_HMEBOX_E1_8814B))
+#define BIT_GET_HMEBOX_E1_8814B(x) \
+ (((x) >> BIT_SHIFT_HMEBOX_E1_8814B) & BIT_MASK_HMEBOX_E1_8814B)
+#define BIT_SET_HMEBOX_E1_8814B(x, v) \
+ (BIT_CLEAR_HMEBOX_E1_8814B(x) | BIT_HMEBOX_E1_8814B(v))
+
+/* 2 REG_HMEBOX_E2_8814B */
+
+#define BIT_SHIFT_HMEBOX_E2_8814B 0
+#define BIT_MASK_HMEBOX_E2_8814B 0xffffffffL
+#define BIT_HMEBOX_E2_8814B(x) \
+ (((x) & BIT_MASK_HMEBOX_E2_8814B) << BIT_SHIFT_HMEBOX_E2_8814B)
+#define BITS_HMEBOX_E2_8814B \
+ (BIT_MASK_HMEBOX_E2_8814B << BIT_SHIFT_HMEBOX_E2_8814B)
+#define BIT_CLEAR_HMEBOX_E2_8814B(x) ((x) & (~BITS_HMEBOX_E2_8814B))
+#define BIT_GET_HMEBOX_E2_8814B(x) \
+ (((x) >> BIT_SHIFT_HMEBOX_E2_8814B) & BIT_MASK_HMEBOX_E2_8814B)
+#define BIT_SET_HMEBOX_E2_8814B(x, v) \
+ (BIT_CLEAR_HMEBOX_E2_8814B(x) | BIT_HMEBOX_E2_8814B(v))
+
+/* 2 REG_HMEBOX_E3_8814B */
+
+#define BIT_SHIFT_HMEBOX_E3_8814B 0
+#define BIT_MASK_HMEBOX_E3_8814B 0xffffffffL
+#define BIT_HMEBOX_E3_8814B(x) \
+ (((x) & BIT_MASK_HMEBOX_E3_8814B) << BIT_SHIFT_HMEBOX_E3_8814B)
+#define BITS_HMEBOX_E3_8814B \
+ (BIT_MASK_HMEBOX_E3_8814B << BIT_SHIFT_HMEBOX_E3_8814B)
+#define BIT_CLEAR_HMEBOX_E3_8814B(x) ((x) & (~BITS_HMEBOX_E3_8814B))
+#define BIT_GET_HMEBOX_E3_8814B(x) \
+ (((x) >> BIT_SHIFT_HMEBOX_E3_8814B) & BIT_MASK_HMEBOX_E3_8814B)
+#define BIT_SET_HMEBOX_E3_8814B(x, v) \
+ (BIT_CLEAR_HMEBOX_E3_8814B(x) | BIT_HMEBOX_E3_8814B(v))
+
+/* 2 REG_CR_EXT_8814B */
+
+#define BIT_SHIFT_PHY_REQ_DELAY_8814B 24
+#define BIT_MASK_PHY_REQ_DELAY_8814B 0xf
+#define BIT_PHY_REQ_DELAY_8814B(x) \
+ (((x) & BIT_MASK_PHY_REQ_DELAY_8814B) << BIT_SHIFT_PHY_REQ_DELAY_8814B)
+#define BITS_PHY_REQ_DELAY_8814B \
+ (BIT_MASK_PHY_REQ_DELAY_8814B << BIT_SHIFT_PHY_REQ_DELAY_8814B)
+#define BIT_CLEAR_PHY_REQ_DELAY_8814B(x) ((x) & (~BITS_PHY_REQ_DELAY_8814B))
+#define BIT_GET_PHY_REQ_DELAY_8814B(x) \
+ (((x) >> BIT_SHIFT_PHY_REQ_DELAY_8814B) & BIT_MASK_PHY_REQ_DELAY_8814B)
+#define BIT_SET_PHY_REQ_DELAY_8814B(x, v) \
+ (BIT_CLEAR_PHY_REQ_DELAY_8814B(x) | BIT_PHY_REQ_DELAY_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_FW_FIFO_PTR_RST_8814B BIT(18)
+#define BIT_PHY_FIFO_PTR_RST_8814B BIT(17)
+#define BIT_SPD_DOWN_8814B BIT(16)
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_NETYPE4_8814B 4
+#define BIT_MASK_NETYPE4_8814B 0x3
+#define BIT_NETYPE4_8814B(x) \
+ (((x) & BIT_MASK_NETYPE4_8814B) << BIT_SHIFT_NETYPE4_8814B)
+#define BITS_NETYPE4_8814B (BIT_MASK_NETYPE4_8814B << BIT_SHIFT_NETYPE4_8814B)
+#define BIT_CLEAR_NETYPE4_8814B(x) ((x) & (~BITS_NETYPE4_8814B))
+#define BIT_GET_NETYPE4_8814B(x) \
+ (((x) >> BIT_SHIFT_NETYPE4_8814B) & BIT_MASK_NETYPE4_8814B)
+#define BIT_SET_NETYPE4_8814B(x, v) \
+ (BIT_CLEAR_NETYPE4_8814B(x) | BIT_NETYPE4_8814B(v))
+
+#define BIT_SHIFT_NETYPE3_8814B 2
+#define BIT_MASK_NETYPE3_8814B 0x3
+#define BIT_NETYPE3_8814B(x) \
+ (((x) & BIT_MASK_NETYPE3_8814B) << BIT_SHIFT_NETYPE3_8814B)
+#define BITS_NETYPE3_8814B (BIT_MASK_NETYPE3_8814B << BIT_SHIFT_NETYPE3_8814B)
+#define BIT_CLEAR_NETYPE3_8814B(x) ((x) & (~BITS_NETYPE3_8814B))
+#define BIT_GET_NETYPE3_8814B(x) \
+ (((x) >> BIT_SHIFT_NETYPE3_8814B) & BIT_MASK_NETYPE3_8814B)
+#define BIT_SET_NETYPE3_8814B(x, v) \
+ (BIT_CLEAR_NETYPE3_8814B(x) | BIT_NETYPE3_8814B(v))
+
+#define BIT_SHIFT_NETYPE2_8814B 0
+#define BIT_MASK_NETYPE2_8814B 0x3
+#define BIT_NETYPE2_8814B(x) \
+ (((x) & BIT_MASK_NETYPE2_8814B) << BIT_SHIFT_NETYPE2_8814B)
+#define BITS_NETYPE2_8814B (BIT_MASK_NETYPE2_8814B << BIT_SHIFT_NETYPE2_8814B)
+#define BIT_CLEAR_NETYPE2_8814B(x) ((x) & (~BITS_NETYPE2_8814B))
+#define BIT_GET_NETYPE2_8814B(x) \
+ (((x) >> BIT_SHIFT_NETYPE2_8814B) & BIT_MASK_NETYPE2_8814B)
+#define BIT_SET_NETYPE2_8814B(x, v) \
+ (BIT_CLEAR_NETYPE2_8814B(x) | BIT_NETYPE2_8814B(v))
+
+/* 2 REG_TC9_CTRL_8814B */
+#define BIT_TC9INT_EN_8814B BIT(26)
+#define BIT_TC9MODE_8814B BIT(25)
+#define BIT_TC9EN_8814B BIT(24)
+
+#define BIT_SHIFT_TC9DATA_8814B 0
+#define BIT_MASK_TC9DATA_8814B 0xffffff
+#define BIT_TC9DATA_8814B(x) \
+ (((x) & BIT_MASK_TC9DATA_8814B) << BIT_SHIFT_TC9DATA_8814B)
+#define BITS_TC9DATA_8814B (BIT_MASK_TC9DATA_8814B << BIT_SHIFT_TC9DATA_8814B)
+#define BIT_CLEAR_TC9DATA_8814B(x) ((x) & (~BITS_TC9DATA_8814B))
+#define BIT_GET_TC9DATA_8814B(x) \
+ (((x) >> BIT_SHIFT_TC9DATA_8814B) & BIT_MASK_TC9DATA_8814B)
+#define BIT_SET_TC9DATA_8814B(x, v) \
+ (BIT_CLEAR_TC9DATA_8814B(x) | BIT_TC9DATA_8814B(v))
+
+/* 2 REG_TC10_CTRL_8814B */
+#define BIT_TC10INT_EN_8814B BIT(26)
+#define BIT_TC10MODE_8814B BIT(25)
+#define BIT_TC10EN_8814B BIT(24)
+
+#define BIT_SHIFT_TC10DATA_8814B 0
+#define BIT_MASK_TC10DATA_8814B 0xffffff
+#define BIT_TC10DATA_8814B(x) \
+ (((x) & BIT_MASK_TC10DATA_8814B) << BIT_SHIFT_TC10DATA_8814B)
+#define BITS_TC10DATA_8814B \
+ (BIT_MASK_TC10DATA_8814B << BIT_SHIFT_TC10DATA_8814B)
+#define BIT_CLEAR_TC10DATA_8814B(x) ((x) & (~BITS_TC10DATA_8814B))
+#define BIT_GET_TC10DATA_8814B(x) \
+ (((x) >> BIT_SHIFT_TC10DATA_8814B) & BIT_MASK_TC10DATA_8814B)
+#define BIT_SET_TC10DATA_8814B(x, v) \
+ (BIT_CLEAR_TC10DATA_8814B(x) | BIT_TC10DATA_8814B(v))
+
+/* 2 REG_TC11_CTRL_8814B */
+#define BIT_TC11INT_EN_8814B BIT(26)
+#define BIT_TC11MODE_8814B BIT(25)
+#define BIT_TC11EN_8814B BIT(24)
+
+#define BIT_SHIFT_TC11DATA_8814B 0
+#define BIT_MASK_TC11DATA_8814B 0xffffff
+#define BIT_TC11DATA_8814B(x) \
+ (((x) & BIT_MASK_TC11DATA_8814B) << BIT_SHIFT_TC11DATA_8814B)
+#define BITS_TC11DATA_8814B \
+ (BIT_MASK_TC11DATA_8814B << BIT_SHIFT_TC11DATA_8814B)
+#define BIT_CLEAR_TC11DATA_8814B(x) ((x) & (~BITS_TC11DATA_8814B))
+#define BIT_GET_TC11DATA_8814B(x) \
+ (((x) >> BIT_SHIFT_TC11DATA_8814B) & BIT_MASK_TC11DATA_8814B)
+#define BIT_SET_TC11DATA_8814B(x, v) \
+ (BIT_CLEAR_TC11DATA_8814B(x) | BIT_TC11DATA_8814B(v))
+
+/* 2 REG_TC12_CTRL_8814B */
+#define BIT_TC12INT_EN_8814B BIT(26)
+#define BIT_TC12MODE_8814B BIT(25)
+#define BIT_TC12EN_8814B BIT(24)
+
+#define BIT_SHIFT_TC12DATA_8814B 0
+#define BIT_MASK_TC12DATA_8814B 0xffffff
+#define BIT_TC12DATA_8814B(x) \
+ (((x) & BIT_MASK_TC12DATA_8814B) << BIT_SHIFT_TC12DATA_8814B)
+#define BITS_TC12DATA_8814B \
+ (BIT_MASK_TC12DATA_8814B << BIT_SHIFT_TC12DATA_8814B)
+#define BIT_CLEAR_TC12DATA_8814B(x) ((x) & (~BITS_TC12DATA_8814B))
+#define BIT_GET_TC12DATA_8814B(x) \
+ (((x) >> BIT_SHIFT_TC12DATA_8814B) & BIT_MASK_TC12DATA_8814B)
+#define BIT_SET_TC12DATA_8814B(x, v) \
+ (BIT_CLEAR_TC12DATA_8814B(x) | BIT_TC12DATA_8814B(v))
+
+/* 2 REG_FWFF_8814B */
+
+#define BIT_SHIFT_PKTNUM_TH_V1_8814B 24
+#define BIT_MASK_PKTNUM_TH_V1_8814B 0xff
+#define BIT_PKTNUM_TH_V1_8814B(x) \
+ (((x) & BIT_MASK_PKTNUM_TH_V1_8814B) << BIT_SHIFT_PKTNUM_TH_V1_8814B)
+#define BITS_PKTNUM_TH_V1_8814B \
+ (BIT_MASK_PKTNUM_TH_V1_8814B << BIT_SHIFT_PKTNUM_TH_V1_8814B)
+#define BIT_CLEAR_PKTNUM_TH_V1_8814B(x) ((x) & (~BITS_PKTNUM_TH_V1_8814B))
+#define BIT_GET_PKTNUM_TH_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_PKTNUM_TH_V1_8814B) & BIT_MASK_PKTNUM_TH_V1_8814B)
+#define BIT_SET_PKTNUM_TH_V1_8814B(x, v) \
+ (BIT_CLEAR_PKTNUM_TH_V1_8814B(x) | BIT_PKTNUM_TH_V1_8814B(v))
+
+#define BIT_SHIFT_TIMER_TH_8814B 16
+#define BIT_MASK_TIMER_TH_8814B 0xff
+#define BIT_TIMER_TH_8814B(x) \
+ (((x) & BIT_MASK_TIMER_TH_8814B) << BIT_SHIFT_TIMER_TH_8814B)
+#define BITS_TIMER_TH_8814B \
+ (BIT_MASK_TIMER_TH_8814B << BIT_SHIFT_TIMER_TH_8814B)
+#define BIT_CLEAR_TIMER_TH_8814B(x) ((x) & (~BITS_TIMER_TH_8814B))
+#define BIT_GET_TIMER_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_TIMER_TH_8814B) & BIT_MASK_TIMER_TH_8814B)
+#define BIT_SET_TIMER_TH_8814B(x, v) \
+ (BIT_CLEAR_TIMER_TH_8814B(x) | BIT_TIMER_TH_8814B(v))
+
+#define BIT_SHIFT_RXPKT1ENADDR_8814B 0
+#define BIT_MASK_RXPKT1ENADDR_8814B 0xffff
+#define BIT_RXPKT1ENADDR_8814B(x) \
+ (((x) & BIT_MASK_RXPKT1ENADDR_8814B) << BIT_SHIFT_RXPKT1ENADDR_8814B)
+#define BITS_RXPKT1ENADDR_8814B \
+ (BIT_MASK_RXPKT1ENADDR_8814B << BIT_SHIFT_RXPKT1ENADDR_8814B)
+#define BIT_CLEAR_RXPKT1ENADDR_8814B(x) ((x) & (~BITS_RXPKT1ENADDR_8814B))
+#define BIT_GET_RXPKT1ENADDR_8814B(x) \
+ (((x) >> BIT_SHIFT_RXPKT1ENADDR_8814B) & BIT_MASK_RXPKT1ENADDR_8814B)
+#define BIT_SET_RXPKT1ENADDR_8814B(x, v) \
+ (BIT_CLEAR_RXPKT1ENADDR_8814B(x) | BIT_RXPKT1ENADDR_8814B(v))
+
+/* 2 REG_RXFF_PTR_V1_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_RXFF0_RDPTR_V2_8814B 0
+#define BIT_MASK_RXFF0_RDPTR_V2_8814B 0x3ffff
+#define BIT_RXFF0_RDPTR_V2_8814B(x) \
+ (((x) & BIT_MASK_RXFF0_RDPTR_V2_8814B) \
+ << BIT_SHIFT_RXFF0_RDPTR_V2_8814B)
+#define BITS_RXFF0_RDPTR_V2_8814B \
+ (BIT_MASK_RXFF0_RDPTR_V2_8814B << BIT_SHIFT_RXFF0_RDPTR_V2_8814B)
+#define BIT_CLEAR_RXFF0_RDPTR_V2_8814B(x) ((x) & (~BITS_RXFF0_RDPTR_V2_8814B))
+#define BIT_GET_RXFF0_RDPTR_V2_8814B(x) \
+ (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8814B) & \
+ BIT_MASK_RXFF0_RDPTR_V2_8814B)
+#define BIT_SET_RXFF0_RDPTR_V2_8814B(x, v) \
+ (BIT_CLEAR_RXFF0_RDPTR_V2_8814B(x) | BIT_RXFF0_RDPTR_V2_8814B(v))
+
+/* 2 REG_RXFF_WTR_V1_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_RXFF0_WTPTR_V2_8814B 0
+#define BIT_MASK_RXFF0_WTPTR_V2_8814B 0x3ffff
+#define BIT_RXFF0_WTPTR_V2_8814B(x) \
+ (((x) & BIT_MASK_RXFF0_WTPTR_V2_8814B) \
+ << BIT_SHIFT_RXFF0_WTPTR_V2_8814B)
+#define BITS_RXFF0_WTPTR_V2_8814B \
+ (BIT_MASK_RXFF0_WTPTR_V2_8814B << BIT_SHIFT_RXFF0_WTPTR_V2_8814B)
+#define BIT_CLEAR_RXFF0_WTPTR_V2_8814B(x) ((x) & (~BITS_RXFF0_WTPTR_V2_8814B))
+#define BIT_GET_RXFF0_WTPTR_V2_8814B(x) \
+ (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8814B) & \
+ BIT_MASK_RXFF0_WTPTR_V2_8814B)
+#define BIT_SET_RXFF0_WTPTR_V2_8814B(x, v) \
+ (BIT_CLEAR_RXFF0_WTPTR_V2_8814B(x) | BIT_RXFF0_WTPTR_V2_8814B(v))
+
+/* 2 REG_FE2IMR_8814B */
+#define BIT__FE4ISR__IND_MSK_8814B BIT(29)
+#define BIT_FS_TXSC_DESC_DONE_INT_EN_8814B BIT(28)
+#define BIT_FS_TXSC_BKDONE_INT_EN_8814B BIT(27)
+#define BIT_FS_TXSC_BEDONE_INT_EN_8814B BIT(26)
+#define BIT_FS_TXSC_VIDONE_INT_EN_8814B BIT(25)
+#define BIT_FS_TXSC_VODONE_INT_EN_8814B BIT(24)
+#define BIT_FS_ATIM_MB7_INT_EN_8814B BIT(23)
+#define BIT_FS_ATIM_MB6_INT_EN_8814B BIT(22)
+#define BIT_FS_ATIM_MB5_INT_EN_8814B BIT(21)
+#define BIT_FS_ATIM_MB4_INT_EN_8814B BIT(20)
+#define BIT_FS_ATIM_MB3_INT_EN_8814B BIT(19)
+#define BIT_FS_ATIM_MB2_INT_EN_8814B BIT(18)
+#define BIT_FS_ATIM_MB1_INT_EN_8814B BIT(17)
+#define BIT_FS_ATIM_MB0_INT_EN_8814B BIT(16)
+#define BIT_FS_TBTT4INT_EN_8814B BIT(11)
+#define BIT_FS_TBTT3INT_EN_8814B BIT(10)
+#define BIT_FS_TBTT2INT_EN_8814B BIT(9)
+#define BIT_FS_TBTT1INT_EN_8814B BIT(8)
+#define BIT_FS_TBTT0_MB7INT_EN_8814B BIT(7)
+#define BIT_FS_TBTT0_MB6INT_EN_8814B BIT(6)
+#define BIT_FS_TBTT0_MB5INT_EN_8814B BIT(5)
+#define BIT_FS_TBTT0_MB4INT_EN_8814B BIT(4)
+#define BIT_FS_TBTT0_MB3INT_EN_8814B BIT(3)
+#define BIT_FS_TBTT0_MB2INT_EN_8814B BIT(2)
+#define BIT_FS_TBTT0_MB1INT_EN_8814B BIT(1)
+#define BIT_FS_TBTT0_INT_EN_8814B BIT(0)
+
+/* 2 REG_FE2ISR_8814B */
+#define BIT__FE4ISR__IND_INT_8814B BIT(29)
+#define BIT_FS_TXSC_DESC_DONE_INT_8814B BIT(28)
+#define BIT_FS_TXSC_BKDONE_INT_8814B BIT(27)
+#define BIT_FS_TXSC_BEDONE_INT_8814B BIT(26)
+#define BIT_FS_TXSC_VIDONE_INT_8814B BIT(25)
+#define BIT_FS_TXSC_VODONE_INT_8814B BIT(24)
+#define BIT_FS_ATIM_MB7_INT_8814B BIT(23)
+#define BIT_FS_ATIM_MB6_INT_8814B BIT(22)
+#define BIT_FS_ATIM_MB5_INT_8814B BIT(21)
+#define BIT_FS_ATIM_MB4_INT_8814B BIT(20)
+#define BIT_FS_ATIM_MB3_INT_8814B BIT(19)
+#define BIT_FS_ATIM_MB2_INT_8814B BIT(18)
+#define BIT_FS_ATIM_MB1_INT_8814B BIT(17)
+#define BIT_FS_ATIM_MB0_INT_8814B BIT(16)
+#define BIT_FS_TBTT4INT_8814B BIT(11)
+#define BIT_FS_TBTT3INT_8814B BIT(10)
+#define BIT_FS_TBTT2INT_8814B BIT(9)
+#define BIT_FS_TBTT1INT_8814B BIT(8)
+#define BIT_FS_TBTT0_MB7INT_8814B BIT(7)
+#define BIT_FS_TBTT0_MB6INT_8814B BIT(6)
+#define BIT_FS_TBTT0_MB5INT_8814B BIT(5)
+#define BIT_FS_TBTT0_MB4INT_8814B BIT(4)
+#define BIT_FS_TBTT0_MB3INT_8814B BIT(3)
+#define BIT_FS_TBTT0_MB2INT_8814B BIT(2)
+#define BIT_FS_TBTT0_MB1INT_8814B BIT(1)
+#define BIT_FS_TBTT0_INT_8814B BIT(0)
+
+/* 2 REG_FE3IMR_8814B */
+#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT__EN_8814B BIT(31)
+#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT__EN_8814B BIT(30)
+#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT__EN_8814B BIT(29)
+#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT__EN_8814B BIT(28)
+#define BIT_FS_BCNDMA4_INT_EN_8814B BIT(27)
+#define BIT_FS_BCNDMA3_INT_EN_8814B BIT(26)
+#define BIT_FS_BCNDMA2_INT_EN_8814B BIT(25)
+#define BIT_FS_BCNDMA1_INT_EN_8814B BIT(24)
+#define BIT_FS_BCNDMA0_MB7_INT_EN_8814B BIT(23)
+#define BIT_FS_BCNDMA0_MB6_INT_EN_8814B BIT(22)
+#define BIT_FS_BCNDMA0_MB5_INT_EN_8814B BIT(21)
+#define BIT_FS_BCNDMA0_MB4_INT_EN_8814B BIT(20)
+#define BIT_FS_BCNDMA0_MB3_INT_EN_8814B BIT(19)
+#define BIT_FS_BCNDMA0_MB2_INT_EN_8814B BIT(18)
+#define BIT_FS_BCNDMA0_MB1_INT_EN_8814B BIT(17)
+#define BIT_FS_BCNDMA0_INT_EN_8814B BIT(16)
+#define BIT_FS_MTI_BCNIVLEAR_INT__EN_8814B BIT(15)
+#define BIT_FS_BCNERLY4_INT_EN_8814B BIT(11)
+#define BIT_FS_BCNERLY3_INT_EN_8814B BIT(10)
+#define BIT_FS_BCNERLY2_INT_EN_8814B BIT(9)
+#define BIT_FS_BCNERLY1_INT_EN_8814B BIT(8)
+#define BIT_FS_BCNERLY0_MB7INT_EN_8814B BIT(7)
+#define BIT_FS_BCNERLY0_MB6INT_EN_8814B BIT(6)
+#define BIT_FS_BCNERLY0_MB5INT_EN_8814B BIT(5)
+#define BIT_FS_BCNERLY0_MB4INT_EN_8814B BIT(4)
+#define BIT_FS_BCNERLY0_MB3INT_EN_8814B BIT(3)
+#define BIT_FS_BCNERLY0_MB2INT_EN_8814B BIT(2)
+#define BIT_FS_BCNERLY0_MB1INT_EN_8814B BIT(1)
+#define BIT_FS_BCNERLY0_INT_EN_8814B BIT(0)
+
+/* 2 REG_FE3ISR_8814B */
+#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT_8814B BIT(31)
+#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT_8814B BIT(30)
+#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT_8814B BIT(29)
+#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT_8814B BIT(28)
+#define BIT_FS_BCNDMA4_INT_8814B BIT(27)
+#define BIT_FS_BCNDMA3_INT_8814B BIT(26)
+#define BIT_FS_BCNDMA2_INT_8814B BIT(25)
+#define BIT_FS_BCNDMA1_INT_8814B BIT(24)
+#define BIT_FS_BCNDMA0_MB7_INT_8814B BIT(23)
+#define BIT_FS_BCNDMA0_MB6_INT_8814B BIT(22)
+#define BIT_FS_BCNDMA0_MB5_INT_8814B BIT(21)
+#define BIT_FS_BCNDMA0_MB4_INT_8814B BIT(20)
+#define BIT_FS_BCNDMA0_MB3_INT_8814B BIT(19)
+#define BIT_FS_BCNDMA0_MB2_INT_8814B BIT(18)
+#define BIT_FS_BCNDMA0_MB1_INT_8814B BIT(17)
+#define BIT_FS_BCNDMA0_INT_8814B BIT(16)
+#define BIT_FS_MTI_BCNIVLEAR_INT_8814B BIT(15)
+#define BIT_FS_BCNERLY4_INT_8814B BIT(11)
+#define BIT_FS_BCNERLY3_INT_8814B BIT(10)
+#define BIT_FS_BCNERLY2_INT_8814B BIT(9)
+#define BIT_FS_BCNERLY1_INT_8814B BIT(8)
+#define BIT_FS_BCNERLY0_MB7INT_8814B BIT(7)
+#define BIT_FS_BCNERLY0_MB6INT_8814B BIT(6)
+#define BIT_FS_BCNERLY0_MB5INT_8814B BIT(5)
+#define BIT_FS_BCNERLY0_MB4INT_8814B BIT(4)
+#define BIT_FS_BCNERLY0_MB3INT_8814B BIT(3)
+#define BIT_FS_BCNERLY0_MB2INT_8814B BIT(2)
+#define BIT_FS_BCNERLY0_MB1INT_8814B BIT(1)
+#define BIT_FS_BCNERLY0_INT_8814B BIT(0)
+
+/* 2 REG_FE4IMR_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_FS_CLI3_TXPKTIN_INT_EN_8814B BIT(19)
+#define BIT_FS_CLI2_TXPKTIN_INT_EN_8814B BIT(18)
+#define BIT_FS_CLI1_TXPKTIN_INT_EN_8814B BIT(17)
+#define BIT_FS_CLI0_TXPKTIN_INT_EN_8814B BIT(16)
+#define BIT_FS_CLI3_RX_UMD0_INT_EN_8814B BIT(15)
+#define BIT_FS_CLI3_RX_UMD1_INT_EN_8814B BIT(14)
+#define BIT_FS_CLI3_RX_BMD0_INT_EN_8814B BIT(13)
+#define BIT_FS_CLI3_RX_BMD1_INT_EN_8814B BIT(12)
+#define BIT_FS_CLI2_RX_UMD0_INT_EN_8814B BIT(11)
+#define BIT_FS_CLI2_RX_UMD1_INT_EN_8814B BIT(10)
+#define BIT_FS_CLI2_RX_BMD0_INT_EN_8814B BIT(9)
+#define BIT_FS_CLI2_RX_BMD1_INT_EN_8814B BIT(8)
+#define BIT_FS_CLI1_RX_UMD0_INT_EN_8814B BIT(7)
+#define BIT_FS_CLI1_RX_UMD1_INT_EN_8814B BIT(6)
+#define BIT_FS_CLI1_RX_BMD0_INT_EN_8814B BIT(5)
+#define BIT_FS_CLI1_RX_BMD1_INT_EN_8814B BIT(4)
+#define BIT_FS_CLI0_RX_UMD0_INT_EN_8814B BIT(3)
+#define BIT_FS_CLI0_RX_UMD1_INT_EN_8814B BIT(2)
+#define BIT_FS_CLI0_RX_BMD0_INT_EN_8814B BIT(1)
+#define BIT_FS_CLI0_RX_BMD1_INT_EN_8814B BIT(0)
+
+/* 2 REG_FE4ISR_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_P2P_PWROFF_NOA2_ERLY_INT_8814B BIT(22)
+#define BIT_P2P_PWROFF_NOA1_ERLY_INT_8814B BIT(21)
+#define BIT_P2P_PWROFF_NOA0_ERLY_INT_8814B BIT(20)
+#define BIT_FS_CLI3_TXPKTIN_INT_8814B BIT(19)
+#define BIT_FS_CLI2_TXPKTIN_INT_8814B BIT(18)
+#define BIT_FS_CLI1_TXPKTIN_INT_8814B BIT(17)
+#define BIT_FS_CLI0_TXPKTIN_INT_8814B BIT(16)
+#define BIT_FS_CLI3_RX_UMD0_INT_8814B BIT(15)
+#define BIT_FS_CLI3_RX_UMD1_INT_8814B BIT(14)
+#define BIT_FS_CLI3_RX_BMD0_INT_8814B BIT(13)
+#define BIT_FS_CLI3_RX_BMD1_INT_8814B BIT(12)
+#define BIT_FS_CLI2_RX_UMD0_INT_8814B BIT(11)
+#define BIT_FS_CLI2_RX_UMD1_INT_8814B BIT(10)
+#define BIT_FS_CLI2_RX_BMD0_INT_8814B BIT(9)
+#define BIT_FS_CLI2_RX_BMD1_INT_8814B BIT(8)
+#define BIT_FS_CLI1_RX_UMD0_INT_8814B BIT(7)
+#define BIT_FS_CLI1_RX_UMD1_INT_8814B BIT(6)
+#define BIT_FS_CLI1_RX_BMD0_INT_8814B BIT(5)
+#define BIT_FS_CLI1_RX_BMD1_INT_8814B BIT(4)
+#define BIT_FS_CLI0_RX_UMD0_INT_8814B BIT(3)
+#define BIT_FS_CLI0_RX_UMD1_INT_8814B BIT(2)
+#define BIT_FS_CLI0_RX_BMD0_INT_8814B BIT(1)
+#define BIT_FS_CLI0_RX_BMD1_INT_8814B BIT(0)
+
+/* 2 REG_FT1IMR_8814B */
+#define BIT__FT2ISR__IND_MSK_8814B BIT(30)
+#define BIT_FTM_PTT_INT_EN_8814B BIT(29)
+#define BIT_RXFTMREQ_INT_EN_8814B BIT(28)
+#define BIT_RXFTM_INT_EN_8814B BIT(27)
+#define BIT_TXFTM_INT_EN_8814B BIT(26)
+#define BIT_FS_H2C_CMD_OK_INT_EN_8814B BIT(25)
+#define BIT_FS_H2C_CMD_FULL_INT_EN_8814B BIT(24)
+#define BIT_FS_MACID_SEARCH_FAIL_INT_EN_8814B BIT(22)
+#define BIT_FS_MACID_PWRCHANGE3_INT_EN_8814B BIT(21)
+#define BIT_FS_MACID_PWRCHANGE2_INT_EN_8814B BIT(20)
+#define BIT_FS_MACID_PWRCHANGE1_INT_EN_8814B BIT(19)
+#define BIT_FS_MACID_PWRCHANGE0_INT_EN_8814B BIT(18)
+#define BIT_FS_CTWEND2_INT_EN_8814B BIT(17)
+#define BIT_FS_CTWEND1_INT_EN_8814B BIT(16)
+#define BIT_FS_CTWEND0_INT_EN_8814B BIT(15)
+#define BIT_FS_TX_NULL1_INT_EN_8814B BIT(14)
+#define BIT_FS_TX_NULL0_INT_EN_8814B BIT(13)
+#define BIT_FS_TSF_BIT32_TOGGLE_EN_8814B BIT(12)
+#define BIT_FS_P2P_RFON2_INT_EN_8814B BIT(11)
+#define BIT_FS_P2P_RFOFF2_INT_EN_8814B BIT(10)
+#define BIT_FS_P2P_RFON1_INT_EN_8814B BIT(9)
+#define BIT_FS_P2P_RFOFF1_INT_EN_8814B BIT(8)
+#define BIT_FS_P2P_RFON0_INT_EN_8814B BIT(7)
+#define BIT_FS_P2P_RFOFF0_INT_EN_8814B BIT(6)
+#define BIT_FS_RX_UAPSDMD1_EN_8814B BIT(5)
+#define BIT_FS_RX_UAPSDMD0_EN_8814B BIT(4)
+#define BIT_FS_TRIGGER_PKT_EN_8814B BIT(3)
+#define BIT_FS_EOSP_INT_EN_8814B BIT(2)
+#define BIT_FS_RPWM2_INT_EN_8814B BIT(1)
+#define BIT_FS_RPWM_INT_EN_8814B BIT(0)
+
+/* 2 REG_FT1ISR_8814B */
+#define BIT__FT2ISR__IND_INT_8814B BIT(30)
+#define BIT_FTM_PTT_INT_8814B BIT(29)
+#define BIT_RXFTMREQ_INT_8814B BIT(28)
+#define BIT_RXFTM_INT_8814B BIT(27)
+#define BIT_TXFTM_INT_8814B BIT(26)
+#define BIT_FS_H2C_CMD_OK_INT_8814B BIT(25)
+#define BIT_FS_H2C_CMD_FULL_INT_8814B BIT(24)
+#define BIT_FS_MACID_SEARCH_FAIL_INT_8814B BIT(22)
+#define BIT_FS_MACID_PWRCHANGE3_INT_8814B BIT(21)
+#define BIT_FS_MACID_PWRCHANGE2_INT_8814B BIT(20)
+#define BIT_FS_MACID_PWRCHANGE1_INT_8814B BIT(19)
+#define BIT_FS_MACID_PWRCHANGE0_INT_8814B BIT(18)
+#define BIT_FS_CTWEND2_INT_8814B BIT(17)
+#define BIT_FS_CTWEND1_INT_8814B BIT(16)
+#define BIT_FS_CTWEND0_INT_8814B BIT(15)
+#define BIT_FS_TX_NULL1_INT_8814B BIT(14)
+#define BIT_FS_TX_NULL0_INT_8814B BIT(13)
+#define BIT_FS_TSF_BIT32_TOGGLE_INT_8814B BIT(12)
+#define BIT_FS_P2P_RFON2_INT_8814B BIT(11)
+#define BIT_FS_P2P_RFOFF2_INT_8814B BIT(10)
+#define BIT_FS_P2P_RFON1_INT_8814B BIT(9)
+#define BIT_FS_P2P_RFOFF1_INT_8814B BIT(8)
+#define BIT_FS_P2P_RFON0_INT_8814B BIT(7)
+#define BIT_FS_P2P_RFOFF0_INT_8814B BIT(6)
+#define BIT_FS_RX_UAPSDMD1_INT_8814B BIT(5)
+#define BIT_FS_RX_UAPSDMD0_INT_8814B BIT(4)
+#define BIT_FS_TRIGGER_PKT_INT_8814B BIT(3)
+#define BIT_FS_EOSP_INT_8814B BIT(2)
+#define BIT_FS_RPWM2_INT_8814B BIT(1)
+#define BIT_FS_RPWM_INT_8814B BIT(0)
+
+/* 2 REG_SPWR0_8814B */
+
+#define BIT_SHIFT_MID_31TO0_8814B 0
+#define BIT_MASK_MID_31TO0_8814B 0xffffffffL
+#define BIT_MID_31TO0_8814B(x) \
+ (((x) & BIT_MASK_MID_31TO0_8814B) << BIT_SHIFT_MID_31TO0_8814B)
+#define BITS_MID_31TO0_8814B \
+ (BIT_MASK_MID_31TO0_8814B << BIT_SHIFT_MID_31TO0_8814B)
+#define BIT_CLEAR_MID_31TO0_8814B(x) ((x) & (~BITS_MID_31TO0_8814B))
+#define BIT_GET_MID_31TO0_8814B(x) \
+ (((x) >> BIT_SHIFT_MID_31TO0_8814B) & BIT_MASK_MID_31TO0_8814B)
+#define BIT_SET_MID_31TO0_8814B(x, v) \
+ (BIT_CLEAR_MID_31TO0_8814B(x) | BIT_MID_31TO0_8814B(v))
+
+/* 2 REG_SPWR1_8814B */
+
+#define BIT_SHIFT_MID_63TO32_8814B 0
+#define BIT_MASK_MID_63TO32_8814B 0xffffffffL
+#define BIT_MID_63TO32_8814B(x) \
+ (((x) & BIT_MASK_MID_63TO32_8814B) << BIT_SHIFT_MID_63TO32_8814B)
+#define BITS_MID_63TO32_8814B \
+ (BIT_MASK_MID_63TO32_8814B << BIT_SHIFT_MID_63TO32_8814B)
+#define BIT_CLEAR_MID_63TO32_8814B(x) ((x) & (~BITS_MID_63TO32_8814B))
+#define BIT_GET_MID_63TO32_8814B(x) \
+ (((x) >> BIT_SHIFT_MID_63TO32_8814B) & BIT_MASK_MID_63TO32_8814B)
+#define BIT_SET_MID_63TO32_8814B(x, v) \
+ (BIT_CLEAR_MID_63TO32_8814B(x) | BIT_MID_63TO32_8814B(v))
+
+/* 2 REG_SPWR2_8814B */
+
+#define BIT_SHIFT_MID_95O64_8814B 0
+#define BIT_MASK_MID_95O64_8814B 0xffffffffL
+#define BIT_MID_95O64_8814B(x) \
+ (((x) & BIT_MASK_MID_95O64_8814B) << BIT_SHIFT_MID_95O64_8814B)
+#define BITS_MID_95O64_8814B \
+ (BIT_MASK_MID_95O64_8814B << BIT_SHIFT_MID_95O64_8814B)
+#define BIT_CLEAR_MID_95O64_8814B(x) ((x) & (~BITS_MID_95O64_8814B))
+#define BIT_GET_MID_95O64_8814B(x) \
+ (((x) >> BIT_SHIFT_MID_95O64_8814B) & BIT_MASK_MID_95O64_8814B)
+#define BIT_SET_MID_95O64_8814B(x, v) \
+ (BIT_CLEAR_MID_95O64_8814B(x) | BIT_MID_95O64_8814B(v))
+
+/* 2 REG_SPWR3_8814B */
+
+#define BIT_SHIFT_MID_127TO96_8814B 0
+#define BIT_MASK_MID_127TO96_8814B 0xffffffffL
+#define BIT_MID_127TO96_8814B(x) \
+ (((x) & BIT_MASK_MID_127TO96_8814B) << BIT_SHIFT_MID_127TO96_8814B)
+#define BITS_MID_127TO96_8814B \
+ (BIT_MASK_MID_127TO96_8814B << BIT_SHIFT_MID_127TO96_8814B)
+#define BIT_CLEAR_MID_127TO96_8814B(x) ((x) & (~BITS_MID_127TO96_8814B))
+#define BIT_GET_MID_127TO96_8814B(x) \
+ (((x) >> BIT_SHIFT_MID_127TO96_8814B) & BIT_MASK_MID_127TO96_8814B)
+#define BIT_SET_MID_127TO96_8814B(x, v) \
+ (BIT_CLEAR_MID_127TO96_8814B(x) | BIT_MID_127TO96_8814B(v))
+
+/* 2 REG_POWSEQ_8814B */
+
+#define BIT_SHIFT_SEQNUM_MID_8814B 16
+#define BIT_MASK_SEQNUM_MID_8814B 0xffff
+#define BIT_SEQNUM_MID_8814B(x) \
+ (((x) & BIT_MASK_SEQNUM_MID_8814B) << BIT_SHIFT_SEQNUM_MID_8814B)
+#define BITS_SEQNUM_MID_8814B \
+ (BIT_MASK_SEQNUM_MID_8814B << BIT_SHIFT_SEQNUM_MID_8814B)
+#define BIT_CLEAR_SEQNUM_MID_8814B(x) ((x) & (~BITS_SEQNUM_MID_8814B))
+#define BIT_GET_SEQNUM_MID_8814B(x) \
+ (((x) >> BIT_SHIFT_SEQNUM_MID_8814B) & BIT_MASK_SEQNUM_MID_8814B)
+#define BIT_SET_SEQNUM_MID_8814B(x, v) \
+ (BIT_CLEAR_SEQNUM_MID_8814B(x) | BIT_SEQNUM_MID_8814B(v))
+
+#define BIT_SHIFT_REF_MID_8814B 0
+#define BIT_MASK_REF_MID_8814B 0x7f
+#define BIT_REF_MID_8814B(x) \
+ (((x) & BIT_MASK_REF_MID_8814B) << BIT_SHIFT_REF_MID_8814B)
+#define BITS_REF_MID_8814B (BIT_MASK_REF_MID_8814B << BIT_SHIFT_REF_MID_8814B)
+#define BIT_CLEAR_REF_MID_8814B(x) ((x) & (~BITS_REF_MID_8814B))
+#define BIT_GET_REF_MID_8814B(x) \
+ (((x) >> BIT_SHIFT_REF_MID_8814B) & BIT_MASK_REF_MID_8814B)
+#define BIT_SET_REF_MID_8814B(x, v) \
+ (BIT_CLEAR_REF_MID_8814B(x) | BIT_REF_MID_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_TC7_CTRL_V1_8814B */
+#define BIT_TC7INT_EN_8814B BIT(26)
+#define BIT_TC7MODE_8814B BIT(25)
+#define BIT_TC7EN_8814B BIT(24)
+
+#define BIT_SHIFT_TC7DATA_8814B 0
+#define BIT_MASK_TC7DATA_8814B 0xffffff
+#define BIT_TC7DATA_8814B(x) \
+ (((x) & BIT_MASK_TC7DATA_8814B) << BIT_SHIFT_TC7DATA_8814B)
+#define BITS_TC7DATA_8814B (BIT_MASK_TC7DATA_8814B << BIT_SHIFT_TC7DATA_8814B)
+#define BIT_CLEAR_TC7DATA_8814B(x) ((x) & (~BITS_TC7DATA_8814B))
+#define BIT_GET_TC7DATA_8814B(x) \
+ (((x) >> BIT_SHIFT_TC7DATA_8814B) & BIT_MASK_TC7DATA_8814B)
+#define BIT_SET_TC7DATA_8814B(x, v) \
+ (BIT_CLEAR_TC7DATA_8814B(x) | BIT_TC7DATA_8814B(v))
+
+/* 2 REG_TC8_CTRL_V1_8814B */
+#define BIT_TC8INT_EN_8814B BIT(26)
+#define BIT_TC8MODE_8814B BIT(25)
+#define BIT_TC8EN_8814B BIT(24)
+
+#define BIT_SHIFT_TC8DATA_8814B 0
+#define BIT_MASK_TC8DATA_8814B 0xffffff
+#define BIT_TC8DATA_8814B(x) \
+ (((x) & BIT_MASK_TC8DATA_8814B) << BIT_SHIFT_TC8DATA_8814B)
+#define BITS_TC8DATA_8814B (BIT_MASK_TC8DATA_8814B << BIT_SHIFT_TC8DATA_8814B)
+#define BIT_CLEAR_TC8DATA_8814B(x) ((x) & (~BITS_TC8DATA_8814B))
+#define BIT_GET_TC8DATA_8814B(x) \
+ (((x) >> BIT_SHIFT_TC8DATA_8814B) & BIT_MASK_TC8DATA_8814B)
+#define BIT_SET_TC8DATA_8814B(x, v) \
+ (BIT_CLEAR_TC8DATA_8814B(x) | BIT_TC8DATA_8814B(v))
+
+/* 2 REG_RX_BCN_TBTT_ITVL0_8814B */
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8814B 24
+#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8814B 0xff
+#define BIT_RX_BCN_TBTT_ITVL_CLIENT2_8814B(x) \
+ (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8814B) \
+ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8814B)
+#define BITS_RX_BCN_TBTT_ITVL_CLIENT2_8814B \
+ (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8814B \
+ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8814B)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2_8814B(x) \
+ ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT2_8814B))
+#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT2_8814B(x) \
+ (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8814B) & \
+ BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8814B)
+#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT2_8814B(x, v) \
+ (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2_8814B(x) | \
+ BIT_RX_BCN_TBTT_ITVL_CLIENT2_8814B(v))
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8814B 16
+#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8814B 0xff
+#define BIT_RX_BCN_TBTT_ITVL_CLIENT1_8814B(x) \
+ (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8814B) \
+ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8814B)
+#define BITS_RX_BCN_TBTT_ITVL_CLIENT1_8814B \
+ (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8814B \
+ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8814B)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1_8814B(x) \
+ ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT1_8814B))
+#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT1_8814B(x) \
+ (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8814B) & \
+ BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8814B)
+#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT1_8814B(x, v) \
+ (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1_8814B(x) | \
+ BIT_RX_BCN_TBTT_ITVL_CLIENT1_8814B(v))
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8814B 8
+#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8814B 0xff
+#define BIT_RX_BCN_TBTT_ITVL_CLIENT0_8814B(x) \
+ (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8814B) \
+ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8814B)
+#define BITS_RX_BCN_TBTT_ITVL_CLIENT0_8814B \
+ (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8814B \
+ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8814B)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0_8814B(x) \
+ ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT0_8814B))
+#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT0_8814B(x) \
+ (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8814B) & \
+ BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8814B)
+#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT0_8814B(x, v) \
+ (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0_8814B(x) | \
+ BIT_RX_BCN_TBTT_ITVL_CLIENT0_8814B(v))
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8814B 0
+#define BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8814B 0xff
+#define BIT_RX_BCN_TBTT_ITVL_PORT0_8814B(x) \
+ (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8814B) \
+ << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8814B)
+#define BITS_RX_BCN_TBTT_ITVL_PORT0_8814B \
+ (BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8814B \
+ << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8814B)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0_8814B(x) \
+ ((x) & (~BITS_RX_BCN_TBTT_ITVL_PORT0_8814B))
+#define BIT_GET_RX_BCN_TBTT_ITVL_PORT0_8814B(x) \
+ (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8814B) & \
+ BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8814B)
+#define BIT_SET_RX_BCN_TBTT_ITVL_PORT0_8814B(x, v) \
+ (BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0_8814B(x) | \
+ BIT_RX_BCN_TBTT_ITVL_PORT0_8814B(v))
+
+/* 2 REG_RX_BCN_TBTT_ITVL1_8814B */
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8814B 0
+#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8814B 0xff
+#define BIT_RX_BCN_TBTT_ITVL_CLIENT3_8814B(x) \
+ (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8814B) \
+ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8814B)
+#define BITS_RX_BCN_TBTT_ITVL_CLIENT3_8814B \
+ (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8814B \
+ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8814B)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3_8814B(x) \
+ ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT3_8814B))
+#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT3_8814B(x) \
+ (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8814B) & \
+ BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8814B)
+#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT3_8814B(x, v) \
+ (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3_8814B(x) | \
+ BIT_RX_BCN_TBTT_ITVL_CLIENT3_8814B(v))
+
+/* 2 REG_FWIMR1_8814B */
+#define BIT_FS_ATIM_MB15_INT_EN_8814B BIT(31)
+#define BIT_FS_ATIM_MB14_INT_EN_8814B BIT(30)
+#define BIT_FS_ATIM_MB13_INT_EN_8814B BIT(29)
+#define BIT_FS_ATIM_MB12_INT_EN_8814B BIT(28)
+#define BIT_FS_ATIM_MB11_INT_EN_8814B BIT(27)
+#define BIT_FS_ATIM_MB10_INT_EN_8814B BIT(26)
+#define BIT_FS_ATIM_MB9_INT_EN_8814B BIT(25)
+#define BIT_FS_ATIM_MB8_INT_EN_8814B BIT(24)
+#define BIT_FS_TXBCNERR_MB15_INT_EN_8814B BIT(23)
+#define BIT_FS_TXBCNERR_MB14_INT_EN_8814B BIT(22)
+#define BIT_FS_TXBCNERR_MB13_INT_EN_8814B BIT(21)
+#define BIT_FS_TXBCNERR_MB12_INT_EN_8814B BIT(20)
+#define BIT_FS_TXBCNERR_MB11_INT_EN_8814B BIT(19)
+#define BIT_FS_TXBCNERR_MB10_INT_EN_8814B BIT(18)
+#define BIT_FS_TXBCNERR_MB9_INT_EN_8814B BIT(17)
+#define BIT_FS_TXBCNERR_MB8_INT_EN_8814B BIT(16)
+#define BIT_FS_TXBCNOK_MB15_INT_EN_8814B BIT(15)
+#define BIT_FS_TXBCNOK_MB14_INT_EN_8814B BIT(14)
+#define BIT_FS_TXBCNOK_MB13_INT_EN_8814B BIT(13)
+#define BIT_FS_TXBCNOK_MB12_INT_EN_8814B BIT(12)
+#define BIT_FS_TXBCNOK_MB11_INT_EN_8814B BIT(11)
+#define BIT_FS_TXBCNOK_MB10_INT_EN_8814B BIT(10)
+#define BIT_FS_TXBCNOK_MB9_INT_EN_8814B BIT(9)
+#define BIT_FS_TXBCNOK_MB8_INT_EN_8814B BIT(8)
+#define BIT_FS_BCNERLY0_MB15INT_EN_8814B BIT(7)
+#define BIT_FS_BCNERLY0_MB14INT_EN_8814B BIT(6)
+#define BIT_FS_BCNERLY0_MB13INT_EN_8814B BIT(5)
+#define BIT_FS_BCNERLY0_MB12INT_EN_8814B BIT(4)
+#define BIT_FS_BCNERLY0_MB11INT_EN_8814B BIT(3)
+#define BIT_FS_BCNERLY0_MB10INT_EN_8814B BIT(2)
+#define BIT_FS_BCNERLY0_MB9INT_EN_8814B BIT(1)
+#define BIT_FS_BCNERLY0_MB8INT_EN_8814B BIT(0)
+
+/* 2 REG_FWISR1_8814B */
+#define BIT_FS_ATIM_MB15_INT_8814B BIT(31)
+#define BIT_FS_ATIM_MB14_INT_8814B BIT(30)
+#define BIT_FS_ATIM_MB13_INT_8814B BIT(29)
+#define BIT_FS_ATIM_MB12_INT_8814B BIT(28)
+#define BIT_FS_ATIM_MB11_INT_8814B BIT(27)
+#define BIT_FS_ATIM_MB10_INT_8814B BIT(26)
+#define BIT_FS_ATIM_MB9_INT_8814B BIT(25)
+#define BIT_FS_ATIM_MB8_INT_8814B BIT(24)
+#define BIT_FS_TXBCNERR_MB15_INT_8814B BIT(23)
+#define BIT_FS_TXBCNERR_MB14_INT_8814B BIT(22)
+#define BIT_FS_TXBCNERR_MB13_INT_8814B BIT(21)
+#define BIT_FS_TXBCNERR_MB12_INT_8814B BIT(20)
+#define BIT_FS_TXBCNERR_MB11_INT_8814B BIT(19)
+#define BIT_FS_TXBCNERR_MB10_INT_8814B BIT(18)
+#define BIT_FS_TXBCNERR_MB9_INT_8814B BIT(17)
+#define BIT_FS_TXBCNERR_MB8_INT_8814B BIT(16)
+#define BIT_FS_TXBCNOK_MB15_INT_8814B BIT(15)
+#define BIT_FS_TXBCNOK_MB14_INT_8814B BIT(14)
+#define BIT_FS_TXBCNOK_MB13_INT_8814B BIT(13)
+#define BIT_FS_TXBCNOK_MB12_INT_8814B BIT(12)
+#define BIT_FS_TXBCNOK_MB11_INT_8814B BIT(11)
+#define BIT_FS_TXBCNOK_MB10_INT_8814B BIT(10)
+#define BIT_FS_TXBCNOK_MB9_INT_8814B BIT(9)
+#define BIT_FS_TXBCNOK_MB8_INT_8814B BIT(8)
+#define BIT_FS_BCNERLY0_MB15INT_8814B BIT(7)
+#define BIT_FS_BCNERLY0_MB14INT_8814B BIT(6)
+#define BIT_FS_BCNERLY0_MB13INT_8814B BIT(5)
+#define BIT_FS_BCNERLY0_MB12INT_8814B BIT(4)
+#define BIT_FS_BCNERLY0_MB11INT_8814B BIT(3)
+#define BIT_FS_BCNERLY0_MB10INT_8814B BIT(2)
+#define BIT_FS_BCNERLY0_MB9INT_8814B BIT(1)
+#define BIT_FS_BCNERLY0_MB8INT_8814B BIT(0)
+
+/* 2 REG_FWIMR2_8814B */
+#define BIT_FS_BCNDMA0_MB15_INT_EN_8814B BIT(15)
+#define BIT_FS_BCNDMA0_MB14_INT_EN_8814B BIT(14)
+#define BIT_FS_BCNDMA0_MB13_INT_EN_8814B BIT(13)
+#define BIT_FS_BCNDMA0_MB12_INT_EN_8814B BIT(12)
+#define BIT_FS_BCNDMA0_MB11_INT_EN_8814B BIT(11)
+#define BIT_FS_BCNDMA0_MB10_INT_EN_8814B BIT(10)
+#define BIT_FS_BCNDMA0_MB9_INT_EN_8814B BIT(9)
+#define BIT_FS_BCNDMA0_MB8_INT_EN_8814B BIT(8)
+#define BIT_FS_TBTT0_MB15INT_EN_8814B BIT(7)
+#define BIT_FS_TBTT0_MB14INT_EN_8814B BIT(6)
+#define BIT_FS_TBTT0_MB13INT_EN_8814B BIT(5)
+#define BIT_FS_TBTT0_MB12INT_EN_8814B BIT(4)
+#define BIT_FS_TBTT0_MB11INT_EN_8814B BIT(3)
+#define BIT_FS_TBTT0_MB10INT_EN_8814B BIT(2)
+#define BIT_FS_TBTT0_MB9INT_EN_8814B BIT(1)
+#define BIT_FS_TBTT0_MB8INT_EN_8814B BIT(0)
+
+/* 2 REG_FWISR2_8814B */
+#define BIT_FS_BCNDMA0_MB15_INT_8814B BIT(15)
+#define BIT_FS_BCNDMA0_MB14_INT_8814B BIT(14)
+#define BIT_FS_BCNDMA0_MB13_INT_8814B BIT(13)
+#define BIT_FS_BCNDMA0_MB12_INT_8814B BIT(12)
+#define BIT_FS_BCNDMA0_MB11_INT_8814B BIT(11)
+#define BIT_FS_BCNDMA0_MB10_INT_8814B BIT(10)
+#define BIT_FS_BCNDMA0_MB9_INT_8814B BIT(9)
+#define BIT_FS_BCNDMA0_MB8_INT_8814B BIT(8)
+#define BIT_FS_TBTT0_MB15INT_8814B BIT(7)
+#define BIT_FS_TBTT0_MB14INT_8814B BIT(6)
+#define BIT_FS_TBTT0_MB13INT_8814B BIT(5)
+#define BIT_FS_TBTT0_MB12INT_8814B BIT(4)
+#define BIT_FS_TBTT0_MB11INT_8814B BIT(3)
+#define BIT_FS_TBTT0_MB10INT_8814B BIT(2)
+#define BIT_FS_TBTT0_MB9INT_8814B BIT(1)
+#define BIT_FS_TBTT0_MB8INT_8814B BIT(0)
+
+/* 2 REG_FWIMR3_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_FS_TXBCNOK_PORT4_INT_EN_8814B BIT(11)
+#define BIT_FS_TXBCNOK_PORT3_INT_EN_8814B BIT(10)
+#define BIT_FS_TXBCNOK_PORT2_INT_EN_8814B BIT(9)
+#define BIT_FS_TXBCNOK_PORT1_INT_EN_8814B BIT(8)
+#define BIT_FS_TXBCNERR_PORT4_INT_EN_8814B BIT(7)
+#define BIT_FS_TXBCNERR_PORT3_INT_EN_8814B BIT(6)
+#define BIT_FS_TXBCNERR_PORT2_INT_EN_8814B BIT(5)
+#define BIT_FS_TXBCNERR_PORT1_INT_EN_8814B BIT(4)
+#define BIT_FS_ATIM_PORT4_INT_EN_8814B BIT(3)
+#define BIT_FS_ATIM_PORT3_INT_EN_8814B BIT(2)
+#define BIT_FS_ATIM_PORT2_INT_EN_8814B BIT(1)
+#define BIT_FS_ATIM_PORT1_INT_EN_8814B BIT(0)
+
+/* 2 REG_FWISR3_8814B */
+#define BIT_FS_TXBCNOK_PORT4_INT_8814B BIT(11)
+#define BIT_FS_TXBCNOK_PORT3_INT_8814B BIT(10)
+#define BIT_FS_TXBCNOK_PORT2_INT_8814B BIT(9)
+#define BIT_FS_TXBCNOK_PORT1_INT_8814B BIT(8)
+#define BIT_FS_TXBCNERR_PORT4_INT_8814B BIT(7)
+#define BIT_FS_TXBCNERR_PORT3_INT_8814B BIT(6)
+#define BIT_FS_TXBCNERR_PORT2_INT_8814B BIT(5)
+#define BIT_FS_TXBCNERR_PORT1_INT_8814B BIT(4)
+#define BIT_FS_ATIM_PORT4_INT_8814B BIT(3)
+#define BIT_FS_ATIM_PORT3_INT_8814B BIT(2)
+#define BIT_FS_ATIM_PORT2_INT_8814B BIT(1)
+#define BIT_FS_ATIM_PORT1_INT_8814B BIT(0)
+
+/* 2 REG_SPEED_SENSOR_8814B */
+#define BIT_DSS_1_RST_N_8814B BIT(31)
+#define BIT_DSS_1_SPEED_EN_8814B BIT(30)
+#define BIT_DSS_1_WIRE_SEL_8814B BIT(29)
+#define BIT_DSS_ENCLK_8814B BIT(28)
+
+#define BIT_SHIFT_DSS_1_RO_SEL_8814B 24
+#define BIT_MASK_DSS_1_RO_SEL_8814B 0x7
+#define BIT_DSS_1_RO_SEL_8814B(x) \
+ (((x) & BIT_MASK_DSS_1_RO_SEL_8814B) << BIT_SHIFT_DSS_1_RO_SEL_8814B)
+#define BITS_DSS_1_RO_SEL_8814B \
+ (BIT_MASK_DSS_1_RO_SEL_8814B << BIT_SHIFT_DSS_1_RO_SEL_8814B)
+#define BIT_CLEAR_DSS_1_RO_SEL_8814B(x) ((x) & (~BITS_DSS_1_RO_SEL_8814B))
+#define BIT_GET_DSS_1_RO_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_DSS_1_RO_SEL_8814B) & BIT_MASK_DSS_1_RO_SEL_8814B)
+#define BIT_SET_DSS_1_RO_SEL_8814B(x, v) \
+ (BIT_CLEAR_DSS_1_RO_SEL_8814B(x) | BIT_DSS_1_RO_SEL_8814B(v))
+
+#define BIT_SHIFT_DSS_1_DATA_IN_8814B 0
+#define BIT_MASK_DSS_1_DATA_IN_8814B 0xfffff
+#define BIT_DSS_1_DATA_IN_8814B(x) \
+ (((x) & BIT_MASK_DSS_1_DATA_IN_8814B) << BIT_SHIFT_DSS_1_DATA_IN_8814B)
+#define BITS_DSS_1_DATA_IN_8814B \
+ (BIT_MASK_DSS_1_DATA_IN_8814B << BIT_SHIFT_DSS_1_DATA_IN_8814B)
+#define BIT_CLEAR_DSS_1_DATA_IN_8814B(x) ((x) & (~BITS_DSS_1_DATA_IN_8814B))
+#define BIT_GET_DSS_1_DATA_IN_8814B(x) \
+ (((x) >> BIT_SHIFT_DSS_1_DATA_IN_8814B) & BIT_MASK_DSS_1_DATA_IN_8814B)
+#define BIT_SET_DSS_1_DATA_IN_8814B(x, v) \
+ (BIT_CLEAR_DSS_1_DATA_IN_8814B(x) | BIT_DSS_1_DATA_IN_8814B(v))
+
+/* 2 REG_SPEED_SENSOR1_8814B */
+#define BIT_DSS_1_READY_8814B BIT(31)
+#define BIT_DSS_1_WSORT_GO_8814B BIT(30)
+
+#define BIT_SHIFT_DSS_1_COUNT_OUT_8814B 0
+#define BIT_MASK_DSS_1_COUNT_OUT_8814B 0xfffff
+#define BIT_DSS_1_COUNT_OUT_8814B(x) \
+ (((x) & BIT_MASK_DSS_1_COUNT_OUT_8814B) \
+ << BIT_SHIFT_DSS_1_COUNT_OUT_8814B)
+#define BITS_DSS_1_COUNT_OUT_8814B \
+ (BIT_MASK_DSS_1_COUNT_OUT_8814B << BIT_SHIFT_DSS_1_COUNT_OUT_8814B)
+#define BIT_CLEAR_DSS_1_COUNT_OUT_8814B(x) ((x) & (~BITS_DSS_1_COUNT_OUT_8814B))
+#define BIT_GET_DSS_1_COUNT_OUT_8814B(x) \
+ (((x) >> BIT_SHIFT_DSS_1_COUNT_OUT_8814B) & \
+ BIT_MASK_DSS_1_COUNT_OUT_8814B)
+#define BIT_SET_DSS_1_COUNT_OUT_8814B(x, v) \
+ (BIT_CLEAR_DSS_1_COUNT_OUT_8814B(x) | BIT_DSS_1_COUNT_OUT_8814B(v))
+
+/* 2 REG_SPEED_SENSOR2_8814B */
+#define BIT_DSS_2_RST_N_8814B BIT(31)
+#define BIT_DSS_2_SPEED_EN_8814B BIT(30)
+#define BIT_DSS_2_WIRE_SEL_8814B BIT(29)
+#define BIT_DSS_ENCLK_8814B BIT(28)
+
+#define BIT_SHIFT_DSS_2_RO_SEL_8814B 24
+#define BIT_MASK_DSS_2_RO_SEL_8814B 0x7
+#define BIT_DSS_2_RO_SEL_8814B(x) \
+ (((x) & BIT_MASK_DSS_2_RO_SEL_8814B) << BIT_SHIFT_DSS_2_RO_SEL_8814B)
+#define BITS_DSS_2_RO_SEL_8814B \
+ (BIT_MASK_DSS_2_RO_SEL_8814B << BIT_SHIFT_DSS_2_RO_SEL_8814B)
+#define BIT_CLEAR_DSS_2_RO_SEL_8814B(x) ((x) & (~BITS_DSS_2_RO_SEL_8814B))
+#define BIT_GET_DSS_2_RO_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_DSS_2_RO_SEL_8814B) & BIT_MASK_DSS_2_RO_SEL_8814B)
+#define BIT_SET_DSS_2_RO_SEL_8814B(x, v) \
+ (BIT_CLEAR_DSS_2_RO_SEL_8814B(x) | BIT_DSS_2_RO_SEL_8814B(v))
+
+#define BIT_SHIFT_DSS_2_DATA_IN_8814B 0
+#define BIT_MASK_DSS_2_DATA_IN_8814B 0xfffff
+#define BIT_DSS_2_DATA_IN_8814B(x) \
+ (((x) & BIT_MASK_DSS_2_DATA_IN_8814B) << BIT_SHIFT_DSS_2_DATA_IN_8814B)
+#define BITS_DSS_2_DATA_IN_8814B \
+ (BIT_MASK_DSS_2_DATA_IN_8814B << BIT_SHIFT_DSS_2_DATA_IN_8814B)
+#define BIT_CLEAR_DSS_2_DATA_IN_8814B(x) ((x) & (~BITS_DSS_2_DATA_IN_8814B))
+#define BIT_GET_DSS_2_DATA_IN_8814B(x) \
+ (((x) >> BIT_SHIFT_DSS_2_DATA_IN_8814B) & BIT_MASK_DSS_2_DATA_IN_8814B)
+#define BIT_SET_DSS_2_DATA_IN_8814B(x, v) \
+ (BIT_CLEAR_DSS_2_DATA_IN_8814B(x) | BIT_DSS_2_DATA_IN_8814B(v))
+
+/* 2 REG_SPEED_SENSOR3_8814B */
+#define BIT_DSS_2_READY_8814B BIT(31)
+#define BIT_DSS_2_WSORT_GO_8814B BIT(30)
+
+#define BIT_SHIFT_DSS_2_COUNT_OUT_8814B 0
+#define BIT_MASK_DSS_2_COUNT_OUT_8814B 0xfffff
+#define BIT_DSS_2_COUNT_OUT_8814B(x) \
+ (((x) & BIT_MASK_DSS_2_COUNT_OUT_8814B) \
+ << BIT_SHIFT_DSS_2_COUNT_OUT_8814B)
+#define BITS_DSS_2_COUNT_OUT_8814B \
+ (BIT_MASK_DSS_2_COUNT_OUT_8814B << BIT_SHIFT_DSS_2_COUNT_OUT_8814B)
+#define BIT_CLEAR_DSS_2_COUNT_OUT_8814B(x) ((x) & (~BITS_DSS_2_COUNT_OUT_8814B))
+#define BIT_GET_DSS_2_COUNT_OUT_8814B(x) \
+ (((x) >> BIT_SHIFT_DSS_2_COUNT_OUT_8814B) & \
+ BIT_MASK_DSS_2_COUNT_OUT_8814B)
+#define BIT_SET_DSS_2_COUNT_OUT_8814B(x, v) \
+ (BIT_CLEAR_DSS_2_COUNT_OUT_8814B(x) | BIT_DSS_2_COUNT_OUT_8814B(v))
+
+/* 2 REG_SPEED_SENSOR4_8814B */
+#define BIT_DSS_3_RST_N_8814B BIT(31)
+#define BIT_DSS_3_SPEED_EN_8814B BIT(30)
+#define BIT_DSS_3_WIRE_SEL_8814B BIT(29)
+#define BIT_DSS_ENCLK_8814B BIT(28)
+
+#define BIT_SHIFT_DSS_3_RO_SEL_8814B 24
+#define BIT_MASK_DSS_3_RO_SEL_8814B 0x7
+#define BIT_DSS_3_RO_SEL_8814B(x) \
+ (((x) & BIT_MASK_DSS_3_RO_SEL_8814B) << BIT_SHIFT_DSS_3_RO_SEL_8814B)
+#define BITS_DSS_3_RO_SEL_8814B \
+ (BIT_MASK_DSS_3_RO_SEL_8814B << BIT_SHIFT_DSS_3_RO_SEL_8814B)
+#define BIT_CLEAR_DSS_3_RO_SEL_8814B(x) ((x) & (~BITS_DSS_3_RO_SEL_8814B))
+#define BIT_GET_DSS_3_RO_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_DSS_3_RO_SEL_8814B) & BIT_MASK_DSS_3_RO_SEL_8814B)
+#define BIT_SET_DSS_3_RO_SEL_8814B(x, v) \
+ (BIT_CLEAR_DSS_3_RO_SEL_8814B(x) | BIT_DSS_3_RO_SEL_8814B(v))
+
+#define BIT_SHIFT_DSS_3_DATA_IN_8814B 0
+#define BIT_MASK_DSS_3_DATA_IN_8814B 0xfffff
+#define BIT_DSS_3_DATA_IN_8814B(x) \
+ (((x) & BIT_MASK_DSS_3_DATA_IN_8814B) << BIT_SHIFT_DSS_3_DATA_IN_8814B)
+#define BITS_DSS_3_DATA_IN_8814B \
+ (BIT_MASK_DSS_3_DATA_IN_8814B << BIT_SHIFT_DSS_3_DATA_IN_8814B)
+#define BIT_CLEAR_DSS_3_DATA_IN_8814B(x) ((x) & (~BITS_DSS_3_DATA_IN_8814B))
+#define BIT_GET_DSS_3_DATA_IN_8814B(x) \
+ (((x) >> BIT_SHIFT_DSS_3_DATA_IN_8814B) & BIT_MASK_DSS_3_DATA_IN_8814B)
+#define BIT_SET_DSS_3_DATA_IN_8814B(x, v) \
+ (BIT_CLEAR_DSS_3_DATA_IN_8814B(x) | BIT_DSS_3_DATA_IN_8814B(v))
+
+/* 2 REG_SPEED_SENSOR5_8814B */
+#define BIT_DSS_3_READY_8814B BIT(31)
+#define BIT_DSS_3_WSORT_GO_8814B BIT(30)
+
+#define BIT_SHIFT_DSS_3_COUNT_OUT_8814B 0
+#define BIT_MASK_DSS_3_COUNT_OUT_8814B 0xfffff
+#define BIT_DSS_3_COUNT_OUT_8814B(x) \
+ (((x) & BIT_MASK_DSS_3_COUNT_OUT_8814B) \
+ << BIT_SHIFT_DSS_3_COUNT_OUT_8814B)
+#define BITS_DSS_3_COUNT_OUT_8814B \
+ (BIT_MASK_DSS_3_COUNT_OUT_8814B << BIT_SHIFT_DSS_3_COUNT_OUT_8814B)
+#define BIT_CLEAR_DSS_3_COUNT_OUT_8814B(x) ((x) & (~BITS_DSS_3_COUNT_OUT_8814B))
+#define BIT_GET_DSS_3_COUNT_OUT_8814B(x) \
+ (((x) >> BIT_SHIFT_DSS_3_COUNT_OUT_8814B) & \
+ BIT_MASK_DSS_3_COUNT_OUT_8814B)
+#define BIT_SET_DSS_3_COUNT_OUT_8814B(x, v) \
+ (BIT_CLEAR_DSS_3_COUNT_OUT_8814B(x) | BIT_DSS_3_COUNT_OUT_8814B(v))
+
+/* 2 REG_RXPKTBUF_1_MAX_ADDR_8814B */
+
+#define BIT_SHIFT_RXPKTBUF_SIZE_8814B 30
+#define BIT_MASK_RXPKTBUF_SIZE_8814B 0x3
+#define BIT_RXPKTBUF_SIZE_8814B(x) \
+ (((x) & BIT_MASK_RXPKTBUF_SIZE_8814B) << BIT_SHIFT_RXPKTBUF_SIZE_8814B)
+#define BITS_RXPKTBUF_SIZE_8814B \
+ (BIT_MASK_RXPKTBUF_SIZE_8814B << BIT_SHIFT_RXPKTBUF_SIZE_8814B)
+#define BIT_CLEAR_RXPKTBUF_SIZE_8814B(x) ((x) & (~BITS_RXPKTBUF_SIZE_8814B))
+#define BIT_GET_RXPKTBUF_SIZE_8814B(x) \
+ (((x) >> BIT_SHIFT_RXPKTBUF_SIZE_8814B) & BIT_MASK_RXPKTBUF_SIZE_8814B)
+#define BIT_SET_RXPKTBUF_SIZE_8814B(x, v) \
+ (BIT_CLEAR_RXPKTBUF_SIZE_8814B(x) | BIT_RXPKTBUF_SIZE_8814B(v))
+
+#define BIT_RXPKTBUF_DBG_SEL_8814B BIT(29)
+
+#define BIT_SHIFT_RXPKTBUF_1_MAX_ADDR_8814B 0
+#define BIT_MASK_RXPKTBUF_1_MAX_ADDR_8814B 0x3ffff
+#define BIT_RXPKTBUF_1_MAX_ADDR_8814B(x) \
+ (((x) & BIT_MASK_RXPKTBUF_1_MAX_ADDR_8814B) \
+ << BIT_SHIFT_RXPKTBUF_1_MAX_ADDR_8814B)
+#define BITS_RXPKTBUF_1_MAX_ADDR_8814B \
+ (BIT_MASK_RXPKTBUF_1_MAX_ADDR_8814B \
+ << BIT_SHIFT_RXPKTBUF_1_MAX_ADDR_8814B)
+#define BIT_CLEAR_RXPKTBUF_1_MAX_ADDR_8814B(x) \
+ ((x) & (~BITS_RXPKTBUF_1_MAX_ADDR_8814B))
+#define BIT_GET_RXPKTBUF_1_MAX_ADDR_8814B(x) \
+ (((x) >> BIT_SHIFT_RXPKTBUF_1_MAX_ADDR_8814B) & \
+ BIT_MASK_RXPKTBUF_1_MAX_ADDR_8814B)
+#define BIT_SET_RXPKTBUF_1_MAX_ADDR_8814B(x, v) \
+ (BIT_CLEAR_RXPKTBUF_1_MAX_ADDR_8814B(x) | \
+ BIT_RXPKTBUF_1_MAX_ADDR_8814B(v))
+
+/* 2 REG_RXFWBUF_1_MAX_ADDR_8814B */
+
+#define BIT_SHIFT_RXFWBUF_1_MAX_ADDR_8814B 0
+#define BIT_MASK_RXFWBUF_1_MAX_ADDR_8814B 0xffff
+#define BIT_RXFWBUF_1_MAX_ADDR_8814B(x) \
+ (((x) & BIT_MASK_RXFWBUF_1_MAX_ADDR_8814B) \
+ << BIT_SHIFT_RXFWBUF_1_MAX_ADDR_8814B)
+#define BITS_RXFWBUF_1_MAX_ADDR_8814B \
+ (BIT_MASK_RXFWBUF_1_MAX_ADDR_8814B \
+ << BIT_SHIFT_RXFWBUF_1_MAX_ADDR_8814B)
+#define BIT_CLEAR_RXFWBUF_1_MAX_ADDR_8814B(x) \
+ ((x) & (~BITS_RXFWBUF_1_MAX_ADDR_8814B))
+#define BIT_GET_RXFWBUF_1_MAX_ADDR_8814B(x) \
+ (((x) >> BIT_SHIFT_RXFWBUF_1_MAX_ADDR_8814B) & \
+ BIT_MASK_RXFWBUF_1_MAX_ADDR_8814B)
+#define BIT_SET_RXFWBUF_1_MAX_ADDR_8814B(x, v) \
+ (BIT_CLEAR_RXFWBUF_1_MAX_ADDR_8814B(x) | \
+ BIT_RXFWBUF_1_MAX_ADDR_8814B(v))
+
+/* 2 REG_IO_WRAP_ERR_FLAG_V1_8814B */
+#define BIT_IO_WRAP_ERR_8814B BIT(0)
+
+/* 2 REG_RXPKTBUF_1_READ_8814B */
+
+#define BIT_SHIFT_RXPKTBUF_1_READ_8814B 0
+#define BIT_MASK_RXPKTBUF_1_READ_8814B 0x3ffff
+#define BIT_RXPKTBUF_1_READ_8814B(x) \
+ (((x) & BIT_MASK_RXPKTBUF_1_READ_8814B) \
+ << BIT_SHIFT_RXPKTBUF_1_READ_8814B)
+#define BITS_RXPKTBUF_1_READ_8814B \
+ (BIT_MASK_RXPKTBUF_1_READ_8814B << BIT_SHIFT_RXPKTBUF_1_READ_8814B)
+#define BIT_CLEAR_RXPKTBUF_1_READ_8814B(x) ((x) & (~BITS_RXPKTBUF_1_READ_8814B))
+#define BIT_GET_RXPKTBUF_1_READ_8814B(x) \
+ (((x) >> BIT_SHIFT_RXPKTBUF_1_READ_8814B) & \
+ BIT_MASK_RXPKTBUF_1_READ_8814B)
+#define BIT_SET_RXPKTBUF_1_READ_8814B(x, v) \
+ (BIT_CLEAR_RXPKTBUF_1_READ_8814B(x) | BIT_RXPKTBUF_1_READ_8814B(v))
+
+/* 2 REG_RXPKTBUF_1_WRITE_8814B */
+
+#define BIT_SHIFT_RXPKTBUF_1_WRITE_8814B 0
+#define BIT_MASK_RXPKTBUF_1_WRITE_8814B 0x3ffff
+#define BIT_RXPKTBUF_1_WRITE_8814B(x) \
+ (((x) & BIT_MASK_RXPKTBUF_1_WRITE_8814B) \
+ << BIT_SHIFT_RXPKTBUF_1_WRITE_8814B)
+#define BITS_RXPKTBUF_1_WRITE_8814B \
+ (BIT_MASK_RXPKTBUF_1_WRITE_8814B << BIT_SHIFT_RXPKTBUF_1_WRITE_8814B)
+#define BIT_CLEAR_RXPKTBUF_1_WRITE_8814B(x) \
+ ((x) & (~BITS_RXPKTBUF_1_WRITE_8814B))
+#define BIT_GET_RXPKTBUF_1_WRITE_8814B(x) \
+ (((x) >> BIT_SHIFT_RXPKTBUF_1_WRITE_8814B) & \
+ BIT_MASK_RXPKTBUF_1_WRITE_8814B)
+#define BIT_SET_RXPKTBUF_1_WRITE_8814B(x, v) \
+ (BIT_CLEAR_RXPKTBUF_1_WRITE_8814B(x) | BIT_RXPKTBUF_1_WRITE_8814B(v))
+
+/* 2 REG_BUFF_DBGUG_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_R_OQT_DBG_SEL_8814B 16
+#define BIT_MASK_R_OQT_DBG_SEL_8814B 0xff
+#define BIT_R_OQT_DBG_SEL_8814B(x) \
+ (((x) & BIT_MASK_R_OQT_DBG_SEL_8814B) << BIT_SHIFT_R_OQT_DBG_SEL_8814B)
+#define BITS_R_OQT_DBG_SEL_8814B \
+ (BIT_MASK_R_OQT_DBG_SEL_8814B << BIT_SHIFT_R_OQT_DBG_SEL_8814B)
+#define BIT_CLEAR_R_OQT_DBG_SEL_8814B(x) ((x) & (~BITS_R_OQT_DBG_SEL_8814B))
+#define BIT_GET_R_OQT_DBG_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_R_OQT_DBG_SEL_8814B) & BIT_MASK_R_OQT_DBG_SEL_8814B)
+#define BIT_SET_R_OQT_DBG_SEL_8814B(x, v) \
+ (BIT_CLEAR_R_OQT_DBG_SEL_8814B(x) | BIT_R_OQT_DBG_SEL_8814B(v))
+
+#define BIT_SHIFT_R_TXPKTBF_DBG_SEL_8814B 8
+#define BIT_MASK_R_TXPKTBF_DBG_SEL_8814B 0x7
+#define BIT_R_TXPKTBF_DBG_SEL_8814B(x) \
+ (((x) & BIT_MASK_R_TXPKTBF_DBG_SEL_8814B) \
+ << BIT_SHIFT_R_TXPKTBF_DBG_SEL_8814B)
+#define BITS_R_TXPKTBF_DBG_SEL_8814B \
+ (BIT_MASK_R_TXPKTBF_DBG_SEL_8814B << BIT_SHIFT_R_TXPKTBF_DBG_SEL_8814B)
+#define BIT_CLEAR_R_TXPKTBF_DBG_SEL_8814B(x) \
+ ((x) & (~BITS_R_TXPKTBF_DBG_SEL_8814B))
+#define BIT_GET_R_TXPKTBF_DBG_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_R_TXPKTBF_DBG_SEL_8814B) & \
+ BIT_MASK_R_TXPKTBF_DBG_SEL_8814B)
+#define BIT_SET_R_TXPKTBF_DBG_SEL_8814B(x, v) \
+ (BIT_CLEAR_R_TXPKTBF_DBG_SEL_8814B(x) | BIT_R_TXPKTBF_DBG_SEL_8814B(v))
+
+#define BIT_SHIFT_R_RXPKT_DBG_SEL_8814B 6
+#define BIT_MASK_R_RXPKT_DBG_SEL_8814B 0x3
+#define BIT_R_RXPKT_DBG_SEL_8814B(x) \
+ (((x) & BIT_MASK_R_RXPKT_DBG_SEL_8814B) \
+ << BIT_SHIFT_R_RXPKT_DBG_SEL_8814B)
+#define BITS_R_RXPKT_DBG_SEL_8814B \
+ (BIT_MASK_R_RXPKT_DBG_SEL_8814B << BIT_SHIFT_R_RXPKT_DBG_SEL_8814B)
+#define BIT_CLEAR_R_RXPKT_DBG_SEL_8814B(x) ((x) & (~BITS_R_RXPKT_DBG_SEL_8814B))
+#define BIT_GET_R_RXPKT_DBG_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_R_RXPKT_DBG_SEL_8814B) & \
+ BIT_MASK_R_RXPKT_DBG_SEL_8814B)
+#define BIT_SET_R_RXPKT_DBG_SEL_8814B(x, v) \
+ (BIT_CLEAR_R_RXPKT_DBG_SEL_8814B(x) | BIT_R_RXPKT_DBG_SEL_8814B(v))
+
+#define BIT_SHIFT_R_RXPKTBF_DBG_SEL_8814B 0
+#define BIT_MASK_R_RXPKTBF_DBG_SEL_8814B 0x3
+#define BIT_R_RXPKTBF_DBG_SEL_8814B(x) \
+ (((x) & BIT_MASK_R_RXPKTBF_DBG_SEL_8814B) \
+ << BIT_SHIFT_R_RXPKTBF_DBG_SEL_8814B)
+#define BITS_R_RXPKTBF_DBG_SEL_8814B \
+ (BIT_MASK_R_RXPKTBF_DBG_SEL_8814B << BIT_SHIFT_R_RXPKTBF_DBG_SEL_8814B)
+#define BIT_CLEAR_R_RXPKTBF_DBG_SEL_8814B(x) \
+ ((x) & (~BITS_R_RXPKTBF_DBG_SEL_8814B))
+#define BIT_GET_R_RXPKTBF_DBG_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_R_RXPKTBF_DBG_SEL_8814B) & \
+ BIT_MASK_R_RXPKTBF_DBG_SEL_8814B)
+#define BIT_SET_R_RXPKTBF_DBG_SEL_8814B(x, v) \
+ (BIT_CLEAR_R_RXPKTBF_DBG_SEL_8814B(x) | BIT_R_RXPKTBF_DBG_SEL_8814B(v))
+
+/* 2 REG_RFE_CTRL_PAD_E2_8814B */
+#define BIT_RFE_CTRL_ANTSW_E2_8814B BIT(16)
+#define BIT_RFE_CTRL_PIN15_E2_8814B BIT(15)
+#define BIT_RFE_CTRL_PIN14_E2_8814B BIT(14)
+#define BIT_RFE_CTRL_PIN13_E2_8814B BIT(13)
+#define BIT_RFE_CTRL_PIN12_E2_8814B BIT(12)
+#define BIT_RFE_CTRL_PIN11_E2_8814B BIT(11)
+#define BIT_RFE_CTRL_PIN10_E2_8814B BIT(10)
+#define BIT_RFE_CTRL_PIN9_E2_8814B BIT(9)
+#define BIT_RFE_CTRL_PIN8_E2_8814B BIT(8)
+#define BIT_RFE_CTRL_PIN7_E2_8814B BIT(7)
+#define BIT_RFE_CTRL_PIN6_E2_8814B BIT(6)
+#define BIT_RFE_CTRL_PIN5_E2_8814B BIT(5)
+#define BIT_RFE_CTRL_PIN4_E2_8814B BIT(4)
+#define BIT_RFE_CTRL_PIN3_E2_8814B BIT(3)
+#define BIT_RFE_CTRL_PIN2_E2_8814B BIT(2)
+#define BIT_RFE_CTRL_PIN1_E2_8814B BIT(1)
+#define BIT_RFE_CTRL_PIN0_E2_8814B BIT(0)
+
+/* 2 REG_RFE_CTRL_PAD_SR_8814B */
+#define BIT_RFE_CTRL_ANTSW_SR_8814B BIT(16)
+#define BIT_RFE_CTRL_PIN15_SR_8814B BIT(15)
+#define BIT_RFE_CTRL_PIN14_SR_8814B BIT(14)
+#define BIT_RFE_CTRL_PIN13_SR_8814B BIT(13)
+#define BIT_RFE_CTRL_PIN12_SR_8814B BIT(12)
+#define BIT_RFE_CTRL_PIN11_SR_8814B BIT(11)
+#define BIT_RFE_CTRL_PIN10_SR_8814B BIT(10)
+#define BIT_RFE_CTRL_PIN9_SR_8814B BIT(9)
+#define BIT_RFE_CTRL_PIN8_SR_8814B BIT(8)
+#define BIT_RFE_CTRL_PIN7_SR_8814B BIT(7)
+#define BIT_RFE_CTRL_PIN6_SR_8814B BIT(6)
+#define BIT_RFE_CTRL_PIN5_SR_8814B BIT(5)
+#define BIT_RFE_CTRL_PIN4_SR_8814B BIT(4)
+#define BIT_RFE_CTRL_PIN3_SR_8814B BIT(3)
+#define BIT_RFE_CTRL_PIN2_SR_8814B BIT(2)
+#define BIT_RFE_CTRL_PIN1_SR_8814B BIT(1)
+#define BIT_RFE_CTRL_PIN0_SR_8814B BIT(0)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_H2C_PRIORITY_SEL_8814B */
+
+#define BIT_SHIFT_H2C_PRIORITY_SEL_8814B 0
+#define BIT_MASK_H2C_PRIORITY_SEL_8814B 0x3
+#define BIT_H2C_PRIORITY_SEL_8814B(x) \
+ (((x) & BIT_MASK_H2C_PRIORITY_SEL_8814B) \
+ << BIT_SHIFT_H2C_PRIORITY_SEL_8814B)
+#define BITS_H2C_PRIORITY_SEL_8814B \
+ (BIT_MASK_H2C_PRIORITY_SEL_8814B << BIT_SHIFT_H2C_PRIORITY_SEL_8814B)
+#define BIT_CLEAR_H2C_PRIORITY_SEL_8814B(x) \
+ ((x) & (~BITS_H2C_PRIORITY_SEL_8814B))
+#define BIT_GET_H2C_PRIORITY_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_H2C_PRIORITY_SEL_8814B) & \
+ BIT_MASK_H2C_PRIORITY_SEL_8814B)
+#define BIT_SET_H2C_PRIORITY_SEL_8814B(x, v) \
+ (BIT_CLEAR_H2C_PRIORITY_SEL_8814B(x) | BIT_H2C_PRIORITY_SEL_8814B(v))
+
+/* 2 REG_COUNTER_CTRL_8814B */
+
+#define BIT_SHIFT_COUNTER_BASE_8814B 16
+#define BIT_MASK_COUNTER_BASE_8814B 0x1fff
+#define BIT_COUNTER_BASE_8814B(x) \
+ (((x) & BIT_MASK_COUNTER_BASE_8814B) << BIT_SHIFT_COUNTER_BASE_8814B)
+#define BITS_COUNTER_BASE_8814B \
+ (BIT_MASK_COUNTER_BASE_8814B << BIT_SHIFT_COUNTER_BASE_8814B)
+#define BIT_CLEAR_COUNTER_BASE_8814B(x) ((x) & (~BITS_COUNTER_BASE_8814B))
+#define BIT_GET_COUNTER_BASE_8814B(x) \
+ (((x) >> BIT_SHIFT_COUNTER_BASE_8814B) & BIT_MASK_COUNTER_BASE_8814B)
+#define BIT_SET_COUNTER_BASE_8814B(x, v) \
+ (BIT_CLEAR_COUNTER_BASE_8814B(x) | BIT_COUNTER_BASE_8814B(v))
+
+#define BIT_EN_RTS_REQ_8814B BIT(9)
+#define BIT_EN_EDCA_REQ_8814B BIT(8)
+#define BIT_EN_PTCL_REQ_8814B BIT(7)
+#define BIT_EN_SCH_REQ_8814B BIT(6)
+#define BIT_USB_COUNT_EN_8814B BIT(5)
+#define BIT_PCIE_COUNT_EN_8814B BIT(4)
+#define BIT_RQPN_COUNT_EN_8814B BIT(3)
+#define BIT_RDE_COUNT_EN_8814B BIT(2)
+#define BIT_TDE_COUNT_EN_8814B BIT(1)
+#define BIT_DISABLE_COUNTER_8814B BIT(0)
+
+/* 2 REG_COUNTER_THRESHOLD_8814B */
+#define BIT_SEL_ALL_MACID_8814B BIT(31)
+
+#define BIT_SHIFT_COUNTER_MACID_8814B 24
+#define BIT_MASK_COUNTER_MACID_8814B 0x7f
+#define BIT_COUNTER_MACID_8814B(x) \
+ (((x) & BIT_MASK_COUNTER_MACID_8814B) << BIT_SHIFT_COUNTER_MACID_8814B)
+#define BITS_COUNTER_MACID_8814B \
+ (BIT_MASK_COUNTER_MACID_8814B << BIT_SHIFT_COUNTER_MACID_8814B)
+#define BIT_CLEAR_COUNTER_MACID_8814B(x) ((x) & (~BITS_COUNTER_MACID_8814B))
+#define BIT_GET_COUNTER_MACID_8814B(x) \
+ (((x) >> BIT_SHIFT_COUNTER_MACID_8814B) & BIT_MASK_COUNTER_MACID_8814B)
+#define BIT_SET_COUNTER_MACID_8814B(x, v) \
+ (BIT_CLEAR_COUNTER_MACID_8814B(x) | BIT_COUNTER_MACID_8814B(v))
+
+#define BIT_SHIFT_AGG_VALUE2_8814B 16
+#define BIT_MASK_AGG_VALUE2_8814B 0x7f
+#define BIT_AGG_VALUE2_8814B(x) \
+ (((x) & BIT_MASK_AGG_VALUE2_8814B) << BIT_SHIFT_AGG_VALUE2_8814B)
+#define BITS_AGG_VALUE2_8814B \
+ (BIT_MASK_AGG_VALUE2_8814B << BIT_SHIFT_AGG_VALUE2_8814B)
+#define BIT_CLEAR_AGG_VALUE2_8814B(x) ((x) & (~BITS_AGG_VALUE2_8814B))
+#define BIT_GET_AGG_VALUE2_8814B(x) \
+ (((x) >> BIT_SHIFT_AGG_VALUE2_8814B) & BIT_MASK_AGG_VALUE2_8814B)
+#define BIT_SET_AGG_VALUE2_8814B(x, v) \
+ (BIT_CLEAR_AGG_VALUE2_8814B(x) | BIT_AGG_VALUE2_8814B(v))
+
+#define BIT_SHIFT_AGG_VALUE1_8814B 8
+#define BIT_MASK_AGG_VALUE1_8814B 0x7f
+#define BIT_AGG_VALUE1_8814B(x) \
+ (((x) & BIT_MASK_AGG_VALUE1_8814B) << BIT_SHIFT_AGG_VALUE1_8814B)
+#define BITS_AGG_VALUE1_8814B \
+ (BIT_MASK_AGG_VALUE1_8814B << BIT_SHIFT_AGG_VALUE1_8814B)
+#define BIT_CLEAR_AGG_VALUE1_8814B(x) ((x) & (~BITS_AGG_VALUE1_8814B))
+#define BIT_GET_AGG_VALUE1_8814B(x) \
+ (((x) >> BIT_SHIFT_AGG_VALUE1_8814B) & BIT_MASK_AGG_VALUE1_8814B)
+#define BIT_SET_AGG_VALUE1_8814B(x, v) \
+ (BIT_CLEAR_AGG_VALUE1_8814B(x) | BIT_AGG_VALUE1_8814B(v))
+
+#define BIT_SHIFT_AGG_VALUE0_8814B 0
+#define BIT_MASK_AGG_VALUE0_8814B 0x7f
+#define BIT_AGG_VALUE0_8814B(x) \
+ (((x) & BIT_MASK_AGG_VALUE0_8814B) << BIT_SHIFT_AGG_VALUE0_8814B)
+#define BITS_AGG_VALUE0_8814B \
+ (BIT_MASK_AGG_VALUE0_8814B << BIT_SHIFT_AGG_VALUE0_8814B)
+#define BIT_CLEAR_AGG_VALUE0_8814B(x) ((x) & (~BITS_AGG_VALUE0_8814B))
+#define BIT_GET_AGG_VALUE0_8814B(x) \
+ (((x) >> BIT_SHIFT_AGG_VALUE0_8814B) & BIT_MASK_AGG_VALUE0_8814B)
+#define BIT_SET_AGG_VALUE0_8814B(x, v) \
+ (BIT_CLEAR_AGG_VALUE0_8814B(x) | BIT_AGG_VALUE0_8814B(v))
+
+/* 2 REG_COUNTER_SET_8814B */
+
+#define BIT_SHIFT_REQUEST_RESET_8814B 16
+#define BIT_MASK_REQUEST_RESET_8814B 0xffff
+#define BIT_REQUEST_RESET_8814B(x) \
+ (((x) & BIT_MASK_REQUEST_RESET_8814B) << BIT_SHIFT_REQUEST_RESET_8814B)
+#define BITS_REQUEST_RESET_8814B \
+ (BIT_MASK_REQUEST_RESET_8814B << BIT_SHIFT_REQUEST_RESET_8814B)
+#define BIT_CLEAR_REQUEST_RESET_8814B(x) ((x) & (~BITS_REQUEST_RESET_8814B))
+#define BIT_GET_REQUEST_RESET_8814B(x) \
+ (((x) >> BIT_SHIFT_REQUEST_RESET_8814B) & BIT_MASK_REQUEST_RESET_8814B)
+#define BIT_SET_REQUEST_RESET_8814B(x, v) \
+ (BIT_CLEAR_REQUEST_RESET_8814B(x) | BIT_REQUEST_RESET_8814B(v))
+
+#define BIT_SHIFT_REQUEST_START_8814B 0
+#define BIT_MASK_REQUEST_START_8814B 0xffff
+#define BIT_REQUEST_START_8814B(x) \
+ (((x) & BIT_MASK_REQUEST_START_8814B) << BIT_SHIFT_REQUEST_START_8814B)
+#define BITS_REQUEST_START_8814B \
+ (BIT_MASK_REQUEST_START_8814B << BIT_SHIFT_REQUEST_START_8814B)
+#define BIT_CLEAR_REQUEST_START_8814B(x) ((x) & (~BITS_REQUEST_START_8814B))
+#define BIT_GET_REQUEST_START_8814B(x) \
+ (((x) >> BIT_SHIFT_REQUEST_START_8814B) & BIT_MASK_REQUEST_START_8814B)
+#define BIT_SET_REQUEST_START_8814B(x, v) \
+ (BIT_CLEAR_REQUEST_START_8814B(x) | BIT_REQUEST_START_8814B(v))
+
+/* 2 REG_COUNTER_OVERFLOW_8814B */
+
+#define BIT_SHIFT_CNT_OVF_REG_8814B 0
+#define BIT_MASK_CNT_OVF_REG_8814B 0xffff
+#define BIT_CNT_OVF_REG_8814B(x) \
+ (((x) & BIT_MASK_CNT_OVF_REG_8814B) << BIT_SHIFT_CNT_OVF_REG_8814B)
+#define BITS_CNT_OVF_REG_8814B \
+ (BIT_MASK_CNT_OVF_REG_8814B << BIT_SHIFT_CNT_OVF_REG_8814B)
+#define BIT_CLEAR_CNT_OVF_REG_8814B(x) ((x) & (~BITS_CNT_OVF_REG_8814B))
+#define BIT_GET_CNT_OVF_REG_8814B(x) \
+ (((x) >> BIT_SHIFT_CNT_OVF_REG_8814B) & BIT_MASK_CNT_OVF_REG_8814B)
+#define BIT_SET_CNT_OVF_REG_8814B(x, v) \
+ (BIT_CLEAR_CNT_OVF_REG_8814B(x) | BIT_CNT_OVF_REG_8814B(v))
+
+/* 2 REG_TXDMA_LEN_THRESHOLD_8814B */
+
+#define BIT_SHIFT_TDE_LEN_TH1_8814B 16
+#define BIT_MASK_TDE_LEN_TH1_8814B 0xffff
+#define BIT_TDE_LEN_TH1_8814B(x) \
+ (((x) & BIT_MASK_TDE_LEN_TH1_8814B) << BIT_SHIFT_TDE_LEN_TH1_8814B)
+#define BITS_TDE_LEN_TH1_8814B \
+ (BIT_MASK_TDE_LEN_TH1_8814B << BIT_SHIFT_TDE_LEN_TH1_8814B)
+#define BIT_CLEAR_TDE_LEN_TH1_8814B(x) ((x) & (~BITS_TDE_LEN_TH1_8814B))
+#define BIT_GET_TDE_LEN_TH1_8814B(x) \
+ (((x) >> BIT_SHIFT_TDE_LEN_TH1_8814B) & BIT_MASK_TDE_LEN_TH1_8814B)
+#define BIT_SET_TDE_LEN_TH1_8814B(x, v) \
+ (BIT_CLEAR_TDE_LEN_TH1_8814B(x) | BIT_TDE_LEN_TH1_8814B(v))
+
+#define BIT_SHIFT_TDE_LEN_TH0_8814B 0
+#define BIT_MASK_TDE_LEN_TH0_8814B 0xffff
+#define BIT_TDE_LEN_TH0_8814B(x) \
+ (((x) & BIT_MASK_TDE_LEN_TH0_8814B) << BIT_SHIFT_TDE_LEN_TH0_8814B)
+#define BITS_TDE_LEN_TH0_8814B \
+ (BIT_MASK_TDE_LEN_TH0_8814B << BIT_SHIFT_TDE_LEN_TH0_8814B)
+#define BIT_CLEAR_TDE_LEN_TH0_8814B(x) ((x) & (~BITS_TDE_LEN_TH0_8814B))
+#define BIT_GET_TDE_LEN_TH0_8814B(x) \
+ (((x) >> BIT_SHIFT_TDE_LEN_TH0_8814B) & BIT_MASK_TDE_LEN_TH0_8814B)
+#define BIT_SET_TDE_LEN_TH0_8814B(x, v) \
+ (BIT_CLEAR_TDE_LEN_TH0_8814B(x) | BIT_TDE_LEN_TH0_8814B(v))
+
+/* 2 REG_RXDMA_LEN_THRESHOLD_8814B */
+
+#define BIT_SHIFT_RDE_LEN_TH1_8814B 16
+#define BIT_MASK_RDE_LEN_TH1_8814B 0xffff
+#define BIT_RDE_LEN_TH1_8814B(x) \
+ (((x) & BIT_MASK_RDE_LEN_TH1_8814B) << BIT_SHIFT_RDE_LEN_TH1_8814B)
+#define BITS_RDE_LEN_TH1_8814B \
+ (BIT_MASK_RDE_LEN_TH1_8814B << BIT_SHIFT_RDE_LEN_TH1_8814B)
+#define BIT_CLEAR_RDE_LEN_TH1_8814B(x) ((x) & (~BITS_RDE_LEN_TH1_8814B))
+#define BIT_GET_RDE_LEN_TH1_8814B(x) \
+ (((x) >> BIT_SHIFT_RDE_LEN_TH1_8814B) & BIT_MASK_RDE_LEN_TH1_8814B)
+#define BIT_SET_RDE_LEN_TH1_8814B(x, v) \
+ (BIT_CLEAR_RDE_LEN_TH1_8814B(x) | BIT_RDE_LEN_TH1_8814B(v))
+
+#define BIT_SHIFT_RDE_LEN_TH0_8814B 0
+#define BIT_MASK_RDE_LEN_TH0_8814B 0xffff
+#define BIT_RDE_LEN_TH0_8814B(x) \
+ (((x) & BIT_MASK_RDE_LEN_TH0_8814B) << BIT_SHIFT_RDE_LEN_TH0_8814B)
+#define BITS_RDE_LEN_TH0_8814B \
+ (BIT_MASK_RDE_LEN_TH0_8814B << BIT_SHIFT_RDE_LEN_TH0_8814B)
+#define BIT_CLEAR_RDE_LEN_TH0_8814B(x) ((x) & (~BITS_RDE_LEN_TH0_8814B))
+#define BIT_GET_RDE_LEN_TH0_8814B(x) \
+ (((x) >> BIT_SHIFT_RDE_LEN_TH0_8814B) & BIT_MASK_RDE_LEN_TH0_8814B)
+#define BIT_SET_RDE_LEN_TH0_8814B(x, v) \
+ (BIT_CLEAR_RDE_LEN_TH0_8814B(x) | BIT_RDE_LEN_TH0_8814B(v))
+
+/* 2 REG_PCIE_EXEC_TIME_THRESHOLD_8814B */
+
+#define BIT_SHIFT_COUNT_INT_SEL_8814B 16
+#define BIT_MASK_COUNT_INT_SEL_8814B 0x3
+#define BIT_COUNT_INT_SEL_8814B(x) \
+ (((x) & BIT_MASK_COUNT_INT_SEL_8814B) << BIT_SHIFT_COUNT_INT_SEL_8814B)
+#define BITS_COUNT_INT_SEL_8814B \
+ (BIT_MASK_COUNT_INT_SEL_8814B << BIT_SHIFT_COUNT_INT_SEL_8814B)
+#define BIT_CLEAR_COUNT_INT_SEL_8814B(x) ((x) & (~BITS_COUNT_INT_SEL_8814B))
+#define BIT_GET_COUNT_INT_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_COUNT_INT_SEL_8814B) & BIT_MASK_COUNT_INT_SEL_8814B)
+#define BIT_SET_COUNT_INT_SEL_8814B(x, v) \
+ (BIT_CLEAR_COUNT_INT_SEL_8814B(x) | BIT_COUNT_INT_SEL_8814B(v))
+
+#define BIT_SHIFT_EXEC_TIME_TH_8814B 0
+#define BIT_MASK_EXEC_TIME_TH_8814B 0xffff
+#define BIT_EXEC_TIME_TH_8814B(x) \
+ (((x) & BIT_MASK_EXEC_TIME_TH_8814B) << BIT_SHIFT_EXEC_TIME_TH_8814B)
+#define BITS_EXEC_TIME_TH_8814B \
+ (BIT_MASK_EXEC_TIME_TH_8814B << BIT_SHIFT_EXEC_TIME_TH_8814B)
+#define BIT_CLEAR_EXEC_TIME_TH_8814B(x) ((x) & (~BITS_EXEC_TIME_TH_8814B))
+#define BIT_GET_EXEC_TIME_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_EXEC_TIME_TH_8814B) & BIT_MASK_EXEC_TIME_TH_8814B)
+#define BIT_SET_EXEC_TIME_TH_8814B(x, v) \
+ (BIT_CLEAR_EXEC_TIME_TH_8814B(x) | BIT_EXEC_TIME_TH_8814B(v))
+
+/* 2 REG_FT2IMR_8814B */
+#define BIT_FS_CLI3_RX_UAPSDMD1_EN_8814B BIT(31)
+#define BIT_FS_CLI3_RX_UAPSDMD0_EN_8814B BIT(30)
+#define BIT_FS_CLI3_TRIGGER_PKT_EN_8814B BIT(29)
+#define BIT_FS_CLI3_EOSP_INT_EN_8814B BIT(28)
+#define BIT_FS_CLI2_RX_UAPSDMD1_EN_8814B BIT(27)
+#define BIT_FS_CLI2_RX_UAPSDMD0_EN_8814B BIT(26)
+#define BIT_FS_CLI2_TRIGGER_PKT_EN_8814B BIT(25)
+#define BIT_FS_CLI2_EOSP_INT_EN_8814B BIT(24)
+#define BIT_FS_CLI1_RX_UAPSDMD1_EN_8814B BIT(23)
+#define BIT_FS_CLI1_RX_UAPSDMD0_EN_8814B BIT(22)
+#define BIT_FS_CLI1_TRIGGER_PKT_EN_8814B BIT(21)
+#define BIT_FS_CLI1_EOSP_INT_EN_8814B BIT(20)
+#define BIT_FS_CLI0_RX_UAPSDMD1_EN_8814B BIT(19)
+#define BIT_FS_CLI0_RX_UAPSDMD0_EN_8814B BIT(18)
+#define BIT_FS_CLI0_TRIGGER_PKT_EN_8814B BIT(17)
+#define BIT_FS_CLI0_EOSP_INT_EN_8814B BIT(16)
+#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_EN_8814B BIT(9)
+#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_EN_8814B BIT(8)
+#define BIT_FS_CLI3_TX_NULL1_INT_EN_8814B BIT(7)
+#define BIT_FS_CLI3_TX_NULL0_INT_EN_8814B BIT(6)
+#define BIT_FS_CLI2_TX_NULL1_INT_EN_8814B BIT(5)
+#define BIT_FS_CLI2_TX_NULL0_INT_EN_8814B BIT(4)
+#define BIT_FS_CLI1_TX_NULL1_INT_EN_8814B BIT(3)
+#define BIT_FS_CLI1_TX_NULL0_INT_EN_8814B BIT(2)
+#define BIT_FS_CLI0_TX_NULL1_INT_EN_8814B BIT(1)
+#define BIT_FS_CLI0_TX_NULL0_INT_EN_8814B BIT(0)
+
+/* 2 REG_FT2ISR_8814B */
+#define BIT_FS_CLI3_RX_UAPSDMD1_INT_8814B BIT(31)
+#define BIT_FS_CLI3_RX_UAPSDMD0_INT_8814B BIT(30)
+#define BIT_FS_CLI3_TRIGGER_PKT_INT_8814B BIT(29)
+#define BIT_FS_CLI3_EOSP_INT_8814B BIT(28)
+#define BIT_FS_CLI2_RX_UAPSDMD1_INT_8814B BIT(27)
+#define BIT_FS_CLI2_RX_UAPSDMD0_INT_8814B BIT(26)
+#define BIT_FS_CLI2_TRIGGER_PKT_INT_8814B BIT(25)
+#define BIT_FS_CLI2_EOSP_INT_8814B BIT(24)
+#define BIT_FS_CLI1_RX_UAPSDMD1_INT_8814B BIT(23)
+#define BIT_FS_CLI1_RX_UAPSDMD0_INT_8814B BIT(22)
+#define BIT_FS_CLI1_TRIGGER_PKT_INT_8814B BIT(21)
+#define BIT_FS_CLI1_EOSP_INT_8814B BIT(20)
+#define BIT_FS_CLI0_RX_UAPSDMD1_INT_8814B BIT(19)
+#define BIT_FS_CLI0_RX_UAPSDMD0_INT_8814B BIT(18)
+#define BIT_FS_CLI0_TRIGGER_PKT_INT_8814B BIT(17)
+#define BIT_FS_CLI0_EOSP_INT_8814B BIT(16)
+#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_INT_8814B BIT(9)
+#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_INT_8814B BIT(8)
+#define BIT_FS_CLI3_TX_NULL1_INT_8814B BIT(7)
+#define BIT_FS_CLI3_TX_NULL0_INT_8814B BIT(6)
+#define BIT_FS_CLI2_TX_NULL1_INT_8814B BIT(5)
+#define BIT_FS_CLI2_TX_NULL0_INT_8814B BIT(4)
+#define BIT_FS_CLI1_TX_NULL1_INT_8814B BIT(3)
+#define BIT_FS_CLI1_TX_NULL0_INT_8814B BIT(2)
+#define BIT_FS_CLI0_TX_NULL1_INT_8814B BIT(1)
+#define BIT_FS_CLI0_TX_NULL0_INT_8814B BIT(0)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_MSG2_8814B */
+
+#define BIT_SHIFT_FW_MSG2_8814B 0
+#define BIT_MASK_FW_MSG2_8814B 0xffffffffL
+#define BIT_FW_MSG2_8814B(x) \
+ (((x) & BIT_MASK_FW_MSG2_8814B) << BIT_SHIFT_FW_MSG2_8814B)
+#define BITS_FW_MSG2_8814B (BIT_MASK_FW_MSG2_8814B << BIT_SHIFT_FW_MSG2_8814B)
+#define BIT_CLEAR_FW_MSG2_8814B(x) ((x) & (~BITS_FW_MSG2_8814B))
+#define BIT_GET_FW_MSG2_8814B(x) \
+ (((x) >> BIT_SHIFT_FW_MSG2_8814B) & BIT_MASK_FW_MSG2_8814B)
+#define BIT_SET_FW_MSG2_8814B(x, v) \
+ (BIT_CLEAR_FW_MSG2_8814B(x) | BIT_FW_MSG2_8814B(v))
+
+/* 2 REG_MSG3_8814B */
+
+#define BIT_SHIFT_FW_MSG3_8814B 0
+#define BIT_MASK_FW_MSG3_8814B 0xffffffffL
+#define BIT_FW_MSG3_8814B(x) \
+ (((x) & BIT_MASK_FW_MSG3_8814B) << BIT_SHIFT_FW_MSG3_8814B)
+#define BITS_FW_MSG3_8814B (BIT_MASK_FW_MSG3_8814B << BIT_SHIFT_FW_MSG3_8814B)
+#define BIT_CLEAR_FW_MSG3_8814B(x) ((x) & (~BITS_FW_MSG3_8814B))
+#define BIT_GET_FW_MSG3_8814B(x) \
+ (((x) >> BIT_SHIFT_FW_MSG3_8814B) & BIT_MASK_FW_MSG3_8814B)
+#define BIT_SET_FW_MSG3_8814B(x, v) \
+ (BIT_CLEAR_FW_MSG3_8814B(x) | BIT_FW_MSG3_8814B(v))
+
+/* 2 REG_MSG4_8814B */
+
+#define BIT_SHIFT_FW_MSG4_8814B 0
+#define BIT_MASK_FW_MSG4_8814B 0xffffffffL
+#define BIT_FW_MSG4_8814B(x) \
+ (((x) & BIT_MASK_FW_MSG4_8814B) << BIT_SHIFT_FW_MSG4_8814B)
+#define BITS_FW_MSG4_8814B (BIT_MASK_FW_MSG4_8814B << BIT_SHIFT_FW_MSG4_8814B)
+#define BIT_CLEAR_FW_MSG4_8814B(x) ((x) & (~BITS_FW_MSG4_8814B))
+#define BIT_GET_FW_MSG4_8814B(x) \
+ (((x) >> BIT_SHIFT_FW_MSG4_8814B) & BIT_MASK_FW_MSG4_8814B)
+#define BIT_SET_FW_MSG4_8814B(x, v) \
+ (BIT_CLEAR_FW_MSG4_8814B(x) | BIT_FW_MSG4_8814B(v))
+
+/* 2 REG_MSG5_8814B */
+
+#define BIT_SHIFT_FW_MSG5_8814B 0
+#define BIT_MASK_FW_MSG5_8814B 0xffffffffL
+#define BIT_FW_MSG5_8814B(x) \
+ (((x) & BIT_MASK_FW_MSG5_8814B) << BIT_SHIFT_FW_MSG5_8814B)
+#define BITS_FW_MSG5_8814B (BIT_MASK_FW_MSG5_8814B << BIT_SHIFT_FW_MSG5_8814B)
+#define BIT_CLEAR_FW_MSG5_8814B(x) ((x) & (~BITS_FW_MSG5_8814B))
+#define BIT_GET_FW_MSG5_8814B(x) \
+ (((x) >> BIT_SHIFT_FW_MSG5_8814B) & BIT_MASK_FW_MSG5_8814B)
+#define BIT_SET_FW_MSG5_8814B(x, v) \
+ (BIT_CLEAR_FW_MSG5_8814B(x) | BIT_FW_MSG5_8814B(v))
+
+/* 2 REG_BIST_RSTN0_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_BIST_RSTN2_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_BIST_MODE_NRML0_8814B */
+
+/* 2 REG_BIST_MODE_NRML1_8814B */
+
+/* 2 REG_BIST_MODE_NRML2_8814B */
+
+/* 2 REG_BIST_MODE_NRML3_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_BIST_DONE_NRML_MAC_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_BIST_DONE_NRML1_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_BIST_DONE_DRF_MAC_8814B */
+
+/* 2 REG_BIST_DONE_DRF_8814B */
+
+/* 2 REG_BIST_DONE_DRF1_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_BIST_FAIL_NRML_MAC_8814B */
+
+/* 2 REG_BIST_FAIL_NRML_8814B */
+
+/* 2 REG_BIST_FAIL_NRML1_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_BIST_FAIL_NRML_MAC_V1_8814B */
+
+/* 2 REG_BIST_FAIL_NRML_V1_8814B */
+
+/* 2 REG_BIST_FAIL_NRML1_V1_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_BIST_MISR_DATAOUT_8814B */
+
+/* 2 REG_BIST_MISR_DATAOUT1_8814B */
+
+/* 2 REG_BIST_MISR_DATAOUT_CPU_8814B */
+
+/* 2 REG_BIST_MISR_DATAOUT_CPU1_8814B */
+
+/* 2 REG_BIST_MISR_DATAOUT_CPU2_8814B */
+
+/* 2 REG_BIST_MISR_DATOUT_CPU3_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_BCN_CTRL_0_8814B */
+#define BIT_BCN1_VALID_8814B BIT(31)
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_BCN1_HEAD_8814B 16
+#define BIT_MASK_BCN1_HEAD_8814B 0xfff
+#define BIT_BCN1_HEAD_8814B(x) \
+ (((x) & BIT_MASK_BCN1_HEAD_8814B) << BIT_SHIFT_BCN1_HEAD_8814B)
+#define BITS_BCN1_HEAD_8814B \
+ (BIT_MASK_BCN1_HEAD_8814B << BIT_SHIFT_BCN1_HEAD_8814B)
+#define BIT_CLEAR_BCN1_HEAD_8814B(x) ((x) & (~BITS_BCN1_HEAD_8814B))
+#define BIT_GET_BCN1_HEAD_8814B(x) \
+ (((x) >> BIT_SHIFT_BCN1_HEAD_8814B) & BIT_MASK_BCN1_HEAD_8814B)
+#define BIT_SET_BCN1_HEAD_8814B(x, v) \
+ (BIT_CLEAR_BCN1_HEAD_8814B(x) | BIT_BCN1_HEAD_8814B(v))
+
+#define BIT_BCN0_VALID_8814B BIT(15)
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_BCN0_HEAD_8814B 0
+#define BIT_MASK_BCN0_HEAD_8814B 0xfff
+#define BIT_BCN0_HEAD_8814B(x) \
+ (((x) & BIT_MASK_BCN0_HEAD_8814B) << BIT_SHIFT_BCN0_HEAD_8814B)
+#define BITS_BCN0_HEAD_8814B \
+ (BIT_MASK_BCN0_HEAD_8814B << BIT_SHIFT_BCN0_HEAD_8814B)
+#define BIT_CLEAR_BCN0_HEAD_8814B(x) ((x) & (~BITS_BCN0_HEAD_8814B))
+#define BIT_GET_BCN0_HEAD_8814B(x) \
+ (((x) >> BIT_SHIFT_BCN0_HEAD_8814B) & BIT_MASK_BCN0_HEAD_8814B)
+#define BIT_SET_BCN0_HEAD_8814B(x, v) \
+ (BIT_CLEAR_BCN0_HEAD_8814B(x) | BIT_BCN0_HEAD_8814B(v))
+
+/* 2 REG_BCN_CTRL_1_8814B */
+#define BIT_BCN3_VALID_8814B BIT(31)
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_BCN3_HEAD_8814B 16
+#define BIT_MASK_BCN3_HEAD_8814B 0xfff
+#define BIT_BCN3_HEAD_8814B(x) \
+ (((x) & BIT_MASK_BCN3_HEAD_8814B) << BIT_SHIFT_BCN3_HEAD_8814B)
+#define BITS_BCN3_HEAD_8814B \
+ (BIT_MASK_BCN3_HEAD_8814B << BIT_SHIFT_BCN3_HEAD_8814B)
+#define BIT_CLEAR_BCN3_HEAD_8814B(x) ((x) & (~BITS_BCN3_HEAD_8814B))
+#define BIT_GET_BCN3_HEAD_8814B(x) \
+ (((x) >> BIT_SHIFT_BCN3_HEAD_8814B) & BIT_MASK_BCN3_HEAD_8814B)
+#define BIT_SET_BCN3_HEAD_8814B(x, v) \
+ (BIT_CLEAR_BCN3_HEAD_8814B(x) | BIT_BCN3_HEAD_8814B(v))
+
+#define BIT_BCN2_VALID_8814B BIT(15)
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_BCN2_HEAD_8814B 0
+#define BIT_MASK_BCN2_HEAD_8814B 0xfff
+#define BIT_BCN2_HEAD_8814B(x) \
+ (((x) & BIT_MASK_BCN2_HEAD_8814B) << BIT_SHIFT_BCN2_HEAD_8814B)
+#define BITS_BCN2_HEAD_8814B \
+ (BIT_MASK_BCN2_HEAD_8814B << BIT_SHIFT_BCN2_HEAD_8814B)
+#define BIT_CLEAR_BCN2_HEAD_8814B(x) ((x) & (~BITS_BCN2_HEAD_8814B))
+#define BIT_GET_BCN2_HEAD_8814B(x) \
+ (((x) >> BIT_SHIFT_BCN2_HEAD_8814B) & BIT_MASK_BCN2_HEAD_8814B)
+#define BIT_SET_BCN2_HEAD_8814B(x, v) \
+ (BIT_CLEAR_BCN2_HEAD_8814B(x) | BIT_BCN2_HEAD_8814B(v))
+
+/* 2 REG_AUTO_LLT_V1_8814B */
+
+#define BIT_SHIFT_MAX_TX_PKT_V1_8814B 24
+#define BIT_MASK_MAX_TX_PKT_V1_8814B 0xff
+#define BIT_MAX_TX_PKT_V1_8814B(x) \
+ (((x) & BIT_MASK_MAX_TX_PKT_V1_8814B) << BIT_SHIFT_MAX_TX_PKT_V1_8814B)
+#define BITS_MAX_TX_PKT_V1_8814B \
+ (BIT_MASK_MAX_TX_PKT_V1_8814B << BIT_SHIFT_MAX_TX_PKT_V1_8814B)
+#define BIT_CLEAR_MAX_TX_PKT_V1_8814B(x) ((x) & (~BITS_MAX_TX_PKT_V1_8814B))
+#define BIT_GET_MAX_TX_PKT_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_MAX_TX_PKT_V1_8814B) & BIT_MASK_MAX_TX_PKT_V1_8814B)
+#define BIT_SET_MAX_TX_PKT_V1_8814B(x, v) \
+ (BIT_CLEAR_MAX_TX_PKT_V1_8814B(x) | BIT_MAX_TX_PKT_V1_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_R_BCN_HEAD_SEL_V1_8814B 20
+#define BIT_MASK_R_BCN_HEAD_SEL_V1_8814B 0x7
+#define BIT_R_BCN_HEAD_SEL_V1_8814B(x) \
+ (((x) & BIT_MASK_R_BCN_HEAD_SEL_V1_8814B) \
+ << BIT_SHIFT_R_BCN_HEAD_SEL_V1_8814B)
+#define BITS_R_BCN_HEAD_SEL_V1_8814B \
+ (BIT_MASK_R_BCN_HEAD_SEL_V1_8814B << BIT_SHIFT_R_BCN_HEAD_SEL_V1_8814B)
+#define BIT_CLEAR_R_BCN_HEAD_SEL_V1_8814B(x) \
+ ((x) & (~BITS_R_BCN_HEAD_SEL_V1_8814B))
+#define BIT_GET_R_BCN_HEAD_SEL_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_R_BCN_HEAD_SEL_V1_8814B) & \
+ BIT_MASK_R_BCN_HEAD_SEL_V1_8814B)
+#define BIT_SET_R_BCN_HEAD_SEL_V1_8814B(x, v) \
+ (BIT_CLEAR_R_BCN_HEAD_SEL_V1_8814B(x) | BIT_R_BCN_HEAD_SEL_V1_8814B(v))
+
+#define BIT_SHIFT_LLT_FREE_PAGE_V2_8814B 8
+#define BIT_MASK_LLT_FREE_PAGE_V2_8814B 0xfff
+#define BIT_LLT_FREE_PAGE_V2_8814B(x) \
+ (((x) & BIT_MASK_LLT_FREE_PAGE_V2_8814B) \
+ << BIT_SHIFT_LLT_FREE_PAGE_V2_8814B)
+#define BITS_LLT_FREE_PAGE_V2_8814B \
+ (BIT_MASK_LLT_FREE_PAGE_V2_8814B << BIT_SHIFT_LLT_FREE_PAGE_V2_8814B)
+#define BIT_CLEAR_LLT_FREE_PAGE_V2_8814B(x) \
+ ((x) & (~BITS_LLT_FREE_PAGE_V2_8814B))
+#define BIT_GET_LLT_FREE_PAGE_V2_8814B(x) \
+ (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V2_8814B) & \
+ BIT_MASK_LLT_FREE_PAGE_V2_8814B)
+#define BIT_SET_LLT_FREE_PAGE_V2_8814B(x, v) \
+ (BIT_CLEAR_LLT_FREE_PAGE_V2_8814B(x) | BIT_LLT_FREE_PAGE_V2_8814B(v))
+
+#define BIT_SHIFT_BLK_DESC_NUM_8814B 4
+#define BIT_MASK_BLK_DESC_NUM_8814B 0xf
+#define BIT_BLK_DESC_NUM_8814B(x) \
+ (((x) & BIT_MASK_BLK_DESC_NUM_8814B) << BIT_SHIFT_BLK_DESC_NUM_8814B)
+#define BITS_BLK_DESC_NUM_8814B \
+ (BIT_MASK_BLK_DESC_NUM_8814B << BIT_SHIFT_BLK_DESC_NUM_8814B)
+#define BIT_CLEAR_BLK_DESC_NUM_8814B(x) ((x) & (~BITS_BLK_DESC_NUM_8814B))
+#define BIT_GET_BLK_DESC_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_BLK_DESC_NUM_8814B) & BIT_MASK_BLK_DESC_NUM_8814B)
+#define BIT_SET_BLK_DESC_NUM_8814B(x, v) \
+ (BIT_CLEAR_BLK_DESC_NUM_8814B(x) | BIT_BLK_DESC_NUM_8814B(v))
+
+#define BIT_TDE_ERROR_STOP_8814B BIT(3)
+#define BIT_R_EN_BCN_SW_HEAD_SEL_8814B BIT(2)
+#define BIT_LLT_DBG_SEL_8814B BIT(1)
+#define BIT_AUTO_INIT_LLT_V1_8814B BIT(0)
+
+/* 2 REG_TXDMA_OFFSET_CHK_8814B */
+#define BIT_EM_CHKSUM_FIN_8814B BIT(31)
+#define BIT_EMN_PCIE_DMA_MOD_8814B BIT(30)
+#define BIT_EN_TXQUE_CLR_8814B BIT(29)
+#define BIT_EN_PCIE_FIFO_MODE_8814B BIT(28)
+
+#define BIT_SHIFT_PG_UNDER_TH_V1_8814B 16
+#define BIT_MASK_PG_UNDER_TH_V1_8814B 0xfff
+#define BIT_PG_UNDER_TH_V1_8814B(x) \
+ (((x) & BIT_MASK_PG_UNDER_TH_V1_8814B) \
+ << BIT_SHIFT_PG_UNDER_TH_V1_8814B)
+#define BITS_PG_UNDER_TH_V1_8814B \
+ (BIT_MASK_PG_UNDER_TH_V1_8814B << BIT_SHIFT_PG_UNDER_TH_V1_8814B)
+#define BIT_CLEAR_PG_UNDER_TH_V1_8814B(x) ((x) & (~BITS_PG_UNDER_TH_V1_8814B))
+#define BIT_GET_PG_UNDER_TH_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8814B) & \
+ BIT_MASK_PG_UNDER_TH_V1_8814B)
+#define BIT_SET_PG_UNDER_TH_V1_8814B(x, v) \
+ (BIT_CLEAR_PG_UNDER_TH_V1_8814B(x) | BIT_PG_UNDER_TH_V1_8814B(v))
+
+#define BIT_R_EN_RESET_RESTORE_H2C_8814B BIT(15)
+#define BIT_SDIO_TDE_FINISH_8814B BIT(14)
+#define BIT_SDIO_TXDESC_CHKSUM_EN_8814B BIT(13)
+#define BIT_RST_RDPTR_8814B BIT(12)
+#define BIT_RST_WRPTR_8814B BIT(11)
+#define BIT_CHK_PG_TH_EN_8814B BIT(10)
+#define BIT_DROP_DATA_EN_8814B BIT(9)
+#define BIT_CHECK_OFFSET_EN_8814B BIT(8)
+
+#define BIT_SHIFT_CHECK_OFFSET_8814B 0
+#define BIT_MASK_CHECK_OFFSET_8814B 0xff
+#define BIT_CHECK_OFFSET_8814B(x) \
+ (((x) & BIT_MASK_CHECK_OFFSET_8814B) << BIT_SHIFT_CHECK_OFFSET_8814B)
+#define BITS_CHECK_OFFSET_8814B \
+ (BIT_MASK_CHECK_OFFSET_8814B << BIT_SHIFT_CHECK_OFFSET_8814B)
+#define BIT_CLEAR_CHECK_OFFSET_8814B(x) ((x) & (~BITS_CHECK_OFFSET_8814B))
+#define BIT_GET_CHECK_OFFSET_8814B(x) \
+ (((x) >> BIT_SHIFT_CHECK_OFFSET_8814B) & BIT_MASK_CHECK_OFFSET_8814B)
+#define BIT_SET_CHECK_OFFSET_8814B(x, v) \
+ (BIT_CLEAR_CHECK_OFFSET_8814B(x) | BIT_CHECK_OFFSET_8814B(v))
+
+/* 2 REG_TXDMA_STATUS_8814B */
+#define BIT_AMSDU_PKT_SIZE_ERR_8814B BIT(31)
+#define BIT_AMSDU_EN_ERR_8814B BIT(30)
+#define BIT_CHKSUM_AMSDU_EN_ERR_8814B BIT(29)
+#define BIT_TXPKTBF_REQ_ERR_8814B BIT(28)
+#define BIT_OQT_UDN_16_8814B BIT(27)
+#define BIT_OQT_OVF_16_8814B BIT(26)
+#define BIT_OQT_UDN_14_15_8814B BIT(25)
+#define BIT_OQT_OVF_14_15_8814B BIT(24)
+#define BIT_OQT_UDN_13_8814B BIT(23)
+#define BIT_OQT_OVF_13_8814B BIT(22)
+#define BIT_OQT_UDN_12_8814B BIT(21)
+#define BIT_OQT_OVF_12_8814B BIT(20)
+#define BIT_OQT_UDN_8_11_8814B BIT(19)
+#define BIT_OQT_OVF_8_11_8814B BIT(18)
+#define BIT_OQT_UDN_4_7_8814B BIT(17)
+#define BIT_OQT_OVF_4_7_8814B BIT(16)
+#define BIT_PAYLOAD_CHKSUM_ERR_8814B BIT(15)
+#define BIT_PAYLOAD_UDN_8814B BIT(14)
+#define BIT_PAYLOAD_OVF_8814B BIT(13)
+#define BIT_DSC_CHKSUM_FAIL_8814B BIT(12)
+#define BIT_EP_QSEL_DIFF_8814B BIT(10)
+#define BIT_TX_OFFS_UNMATCH_8814B BIT(9)
+#define BIT_TXOQT_UDN_0_3_8814B BIT(8)
+#define BIT_TXOQT_OVF_0_3_8814B BIT(7)
+#define BIT_TXDMA_SFF_UDN_8814B BIT(6)
+#define BIT_TXDMA_SFF_OVF_8814B BIT(5)
+#define BIT_LLT_NULL_PG_8814B BIT(4)
+#define BIT_PAGE_UDN_8814B BIT(3)
+#define BIT_PAGE_OVF_8814B BIT(2)
+#define BIT_TXFF_PG_UDN_8814B BIT(1)
+#define BIT_TXFF_PG_OVF_8814B BIT(0)
+
+/* 2 REG_TX_DMA_DBG_8814B */
+
+/* 2 REG_DMA_RQPN_INFO_PUB_8814B */
+
+#define BIT_SHIFT_PUB_AVAL_PG_8814B 16
+#define BIT_MASK_PUB_AVAL_PG_8814B 0xfff
+#define BIT_PUB_AVAL_PG_8814B(x) \
+ (((x) & BIT_MASK_PUB_AVAL_PG_8814B) << BIT_SHIFT_PUB_AVAL_PG_8814B)
+#define BITS_PUB_AVAL_PG_8814B \
+ (BIT_MASK_PUB_AVAL_PG_8814B << BIT_SHIFT_PUB_AVAL_PG_8814B)
+#define BIT_CLEAR_PUB_AVAL_PG_8814B(x) ((x) & (~BITS_PUB_AVAL_PG_8814B))
+#define BIT_GET_PUB_AVAL_PG_8814B(x) \
+ (((x) >> BIT_SHIFT_PUB_AVAL_PG_8814B) & BIT_MASK_PUB_AVAL_PG_8814B)
+#define BIT_SET_PUB_AVAL_PG_8814B(x, v) \
+ (BIT_CLEAR_PUB_AVAL_PG_8814B(x) | BIT_PUB_AVAL_PG_8814B(v))
+
+#define BIT_SHIFT_PUB_RSVD_PG_8814B 0
+#define BIT_MASK_PUB_RSVD_PG_8814B 0xfff
+#define BIT_PUB_RSVD_PG_8814B(x) \
+ (((x) & BIT_MASK_PUB_RSVD_PG_8814B) << BIT_SHIFT_PUB_RSVD_PG_8814B)
+#define BITS_PUB_RSVD_PG_8814B \
+ (BIT_MASK_PUB_RSVD_PG_8814B << BIT_SHIFT_PUB_RSVD_PG_8814B)
+#define BIT_CLEAR_PUB_RSVD_PG_8814B(x) ((x) & (~BITS_PUB_RSVD_PG_8814B))
+#define BIT_GET_PUB_RSVD_PG_8814B(x) \
+ (((x) >> BIT_SHIFT_PUB_RSVD_PG_8814B) & BIT_MASK_PUB_RSVD_PG_8814B)
+#define BIT_SET_PUB_RSVD_PG_8814B(x, v) \
+ (BIT_CLEAR_PUB_RSVD_PG_8814B(x) | BIT_PUB_RSVD_PG_8814B(v))
+
+/* 2 REG_RQPN_CTRL_2_V1_8814B */
+#define BIT_LD_RQPN_V1_8814B BIT(31)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_CH16_PUBLIC_DIS_8814B BIT(16)
+#define BIT_CH15_PUBLIC_DIS_8814B BIT(15)
+#define BIT_CH14_PUBLIC_DIS_8814B BIT(14)
+#define BIT_CH13_PUBLIC_DIS_8814B BIT(13)
+#define BIT_CH12_PUBLIC_DIS_8814B BIT(12)
+#define BIT_CH11_PUBLIC_DIS_8814B BIT(11)
+#define BIT_CH10_PUBLIC_DIS_8814B BIT(10)
+#define BIT_CH9_PUBLIC_DIS_8814B BIT(9)
+#define BIT_CH8_PUBLIC_DIS_8814B BIT(8)
+#define BIT_CH7_PUBLIC_DIS_8814B BIT(7)
+#define BIT_CH6_PUBLIC_DIS_8814B BIT(6)
+#define BIT_CH5_PUBLIC_DIS_8814B BIT(5)
+#define BIT_CH4_PUBLIC_DIS_8814B BIT(4)
+#define BIT_CH3_PUBLIC_DIS_8814B BIT(3)
+#define BIT_CH2_PUBLIC_DIS_8814B BIT(2)
+#define BIT_CH1_PUBLIC_DIS_8814B BIT(1)
+#define BIT_CH0_PUBLIC_DIS_8814B BIT(0)
+
+/* 2 REG_BCN_CTRL_2_8814B */
+#define BIT_BCN0_EXT_VALID_8814B BIT(31)
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_BCN0_EXT_HEAD_8814B 16
+#define BIT_MASK_BCN0_EXT_HEAD_8814B 0xfff
+#define BIT_BCN0_EXT_HEAD_8814B(x) \
+ (((x) & BIT_MASK_BCN0_EXT_HEAD_8814B) << BIT_SHIFT_BCN0_EXT_HEAD_8814B)
+#define BITS_BCN0_EXT_HEAD_8814B \
+ (BIT_MASK_BCN0_EXT_HEAD_8814B << BIT_SHIFT_BCN0_EXT_HEAD_8814B)
+#define BIT_CLEAR_BCN0_EXT_HEAD_8814B(x) ((x) & (~BITS_BCN0_EXT_HEAD_8814B))
+#define BIT_GET_BCN0_EXT_HEAD_8814B(x) \
+ (((x) >> BIT_SHIFT_BCN0_EXT_HEAD_8814B) & BIT_MASK_BCN0_EXT_HEAD_8814B)
+#define BIT_SET_BCN0_EXT_HEAD_8814B(x, v) \
+ (BIT_CLEAR_BCN0_EXT_HEAD_8814B(x) | BIT_BCN0_EXT_HEAD_8814B(v))
+
+#define BIT_BCN4_VALID_8814B BIT(15)
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_BCN4_HEAD_8814B 0
+#define BIT_MASK_BCN4_HEAD_8814B 0xfff
+#define BIT_BCN4_HEAD_8814B(x) \
+ (((x) & BIT_MASK_BCN4_HEAD_8814B) << BIT_SHIFT_BCN4_HEAD_8814B)
+#define BITS_BCN4_HEAD_8814B \
+ (BIT_MASK_BCN4_HEAD_8814B << BIT_SHIFT_BCN4_HEAD_8814B)
+#define BIT_CLEAR_BCN4_HEAD_8814B(x) ((x) & (~BITS_BCN4_HEAD_8814B))
+#define BIT_GET_BCN4_HEAD_8814B(x) \
+ (((x) >> BIT_SHIFT_BCN4_HEAD_8814B) & BIT_MASK_BCN4_HEAD_8814B)
+#define BIT_SET_BCN4_HEAD_8814B(x, v) \
+ (BIT_CLEAR_BCN4_HEAD_8814B(x) | BIT_BCN4_HEAD_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_TXPKTNUM_0_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_TXPKTNUM_CH4_7_8814B 16
+#define BIT_MASK_TXPKTNUM_CH4_7_8814B 0xfff
+#define BIT_TXPKTNUM_CH4_7_8814B(x) \
+ (((x) & BIT_MASK_TXPKTNUM_CH4_7_8814B) \
+ << BIT_SHIFT_TXPKTNUM_CH4_7_8814B)
+#define BITS_TXPKTNUM_CH4_7_8814B \
+ (BIT_MASK_TXPKTNUM_CH4_7_8814B << BIT_SHIFT_TXPKTNUM_CH4_7_8814B)
+#define BIT_CLEAR_TXPKTNUM_CH4_7_8814B(x) ((x) & (~BITS_TXPKTNUM_CH4_7_8814B))
+#define BIT_GET_TXPKTNUM_CH4_7_8814B(x) \
+ (((x) >> BIT_SHIFT_TXPKTNUM_CH4_7_8814B) & \
+ BIT_MASK_TXPKTNUM_CH4_7_8814B)
+#define BIT_SET_TXPKTNUM_CH4_7_8814B(x, v) \
+ (BIT_CLEAR_TXPKTNUM_CH4_7_8814B(x) | BIT_TXPKTNUM_CH4_7_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_TXPKTNUM_CH0_3_8814B 0
+#define BIT_MASK_TXPKTNUM_CH0_3_8814B 0xfff
+#define BIT_TXPKTNUM_CH0_3_8814B(x) \
+ (((x) & BIT_MASK_TXPKTNUM_CH0_3_8814B) \
+ << BIT_SHIFT_TXPKTNUM_CH0_3_8814B)
+#define BITS_TXPKTNUM_CH0_3_8814B \
+ (BIT_MASK_TXPKTNUM_CH0_3_8814B << BIT_SHIFT_TXPKTNUM_CH0_3_8814B)
+#define BIT_CLEAR_TXPKTNUM_CH0_3_8814B(x) ((x) & (~BITS_TXPKTNUM_CH0_3_8814B))
+#define BIT_GET_TXPKTNUM_CH0_3_8814B(x) \
+ (((x) >> BIT_SHIFT_TXPKTNUM_CH0_3_8814B) & \
+ BIT_MASK_TXPKTNUM_CH0_3_8814B)
+#define BIT_SET_TXPKTNUM_CH0_3_8814B(x, v) \
+ (BIT_CLEAR_TXPKTNUM_CH0_3_8814B(x) | BIT_TXPKTNUM_CH0_3_8814B(v))
+
+/* 2 REG_TXPKTNUM_1_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_TXPKTNUM_CH12_8814B 16
+#define BIT_MASK_TXPKTNUM_CH12_8814B 0xfff
+#define BIT_TXPKTNUM_CH12_8814B(x) \
+ (((x) & BIT_MASK_TXPKTNUM_CH12_8814B) << BIT_SHIFT_TXPKTNUM_CH12_8814B)
+#define BITS_TXPKTNUM_CH12_8814B \
+ (BIT_MASK_TXPKTNUM_CH12_8814B << BIT_SHIFT_TXPKTNUM_CH12_8814B)
+#define BIT_CLEAR_TXPKTNUM_CH12_8814B(x) ((x) & (~BITS_TXPKTNUM_CH12_8814B))
+#define BIT_GET_TXPKTNUM_CH12_8814B(x) \
+ (((x) >> BIT_SHIFT_TXPKTNUM_CH12_8814B) & BIT_MASK_TXPKTNUM_CH12_8814B)
+#define BIT_SET_TXPKTNUM_CH12_8814B(x, v) \
+ (BIT_CLEAR_TXPKTNUM_CH12_8814B(x) | BIT_TXPKTNUM_CH12_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_TXPKTNUM_CH8_11_8814B 0
+#define BIT_MASK_TXPKTNUM_CH8_11_8814B 0xfff
+#define BIT_TXPKTNUM_CH8_11_8814B(x) \
+ (((x) & BIT_MASK_TXPKTNUM_CH8_11_8814B) \
+ << BIT_SHIFT_TXPKTNUM_CH8_11_8814B)
+#define BITS_TXPKTNUM_CH8_11_8814B \
+ (BIT_MASK_TXPKTNUM_CH8_11_8814B << BIT_SHIFT_TXPKTNUM_CH8_11_8814B)
+#define BIT_CLEAR_TXPKTNUM_CH8_11_8814B(x) ((x) & (~BITS_TXPKTNUM_CH8_11_8814B))
+#define BIT_GET_TXPKTNUM_CH8_11_8814B(x) \
+ (((x) >> BIT_SHIFT_TXPKTNUM_CH8_11_8814B) & \
+ BIT_MASK_TXPKTNUM_CH8_11_8814B)
+#define BIT_SET_TXPKTNUM_CH8_11_8814B(x, v) \
+ (BIT_CLEAR_TXPKTNUM_CH8_11_8814B(x) | BIT_TXPKTNUM_CH8_11_8814B(v))
+
+/* 2 REG_TXPKTNUM_2_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_TXPKTNUM_CH14_15_8814B 16
+#define BIT_MASK_TXPKTNUM_CH14_15_8814B 0xfff
+#define BIT_TXPKTNUM_CH14_15_8814B(x) \
+ (((x) & BIT_MASK_TXPKTNUM_CH14_15_8814B) \
+ << BIT_SHIFT_TXPKTNUM_CH14_15_8814B)
+#define BITS_TXPKTNUM_CH14_15_8814B \
+ (BIT_MASK_TXPKTNUM_CH14_15_8814B << BIT_SHIFT_TXPKTNUM_CH14_15_8814B)
+#define BIT_CLEAR_TXPKTNUM_CH14_15_8814B(x) \
+ ((x) & (~BITS_TXPKTNUM_CH14_15_8814B))
+#define BIT_GET_TXPKTNUM_CH14_15_8814B(x) \
+ (((x) >> BIT_SHIFT_TXPKTNUM_CH14_15_8814B) & \
+ BIT_MASK_TXPKTNUM_CH14_15_8814B)
+#define BIT_SET_TXPKTNUM_CH14_15_8814B(x, v) \
+ (BIT_CLEAR_TXPKTNUM_CH14_15_8814B(x) | BIT_TXPKTNUM_CH14_15_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_TXPKTNUM_CH13_8814B 0
+#define BIT_MASK_TXPKTNUM_CH13_8814B 0xfff
+#define BIT_TXPKTNUM_CH13_8814B(x) \
+ (((x) & BIT_MASK_TXPKTNUM_CH13_8814B) << BIT_SHIFT_TXPKTNUM_CH13_8814B)
+#define BITS_TXPKTNUM_CH13_8814B \
+ (BIT_MASK_TXPKTNUM_CH13_8814B << BIT_SHIFT_TXPKTNUM_CH13_8814B)
+#define BIT_CLEAR_TXPKTNUM_CH13_8814B(x) ((x) & (~BITS_TXPKTNUM_CH13_8814B))
+#define BIT_GET_TXPKTNUM_CH13_8814B(x) \
+ (((x) >> BIT_SHIFT_TXPKTNUM_CH13_8814B) & BIT_MASK_TXPKTNUM_CH13_8814B)
+#define BIT_SET_TXPKTNUM_CH13_8814B(x, v) \
+ (BIT_CLEAR_TXPKTNUM_CH13_8814B(x) | BIT_TXPKTNUM_CH13_8814B(v))
+
+/* 2 REG_TXPKTNUM_3_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_TXPKTNUM_CH16_8814B 0
+#define BIT_MASK_TXPKTNUM_CH16_8814B 0xfff
+#define BIT_TXPKTNUM_CH16_8814B(x) \
+ (((x) & BIT_MASK_TXPKTNUM_CH16_8814B) << BIT_SHIFT_TXPKTNUM_CH16_8814B)
+#define BITS_TXPKTNUM_CH16_8814B \
+ (BIT_MASK_TXPKTNUM_CH16_8814B << BIT_SHIFT_TXPKTNUM_CH16_8814B)
+#define BIT_CLEAR_TXPKTNUM_CH16_8814B(x) ((x) & (~BITS_TXPKTNUM_CH16_8814B))
+#define BIT_GET_TXPKTNUM_CH16_8814B(x) \
+ (((x) >> BIT_SHIFT_TXPKTNUM_CH16_8814B) & BIT_MASK_TXPKTNUM_CH16_8814B)
+#define BIT_SET_TXPKTNUM_CH16_8814B(x, v) \
+ (BIT_CLEAR_TXPKTNUM_CH16_8814B(x) | BIT_TXPKTNUM_CH16_8814B(v))
+
+/* 2 REG_TX_AGG_ALIGN_8814B */
+
+#define BIT_SHIFT_HW_FLOW_CTL_EN_8814B 16
+#define BIT_MASK_HW_FLOW_CTL_EN_8814B 0xffff
+#define BIT_HW_FLOW_CTL_EN_8814B(x) \
+ (((x) & BIT_MASK_HW_FLOW_CTL_EN_8814B) \
+ << BIT_SHIFT_HW_FLOW_CTL_EN_8814B)
+#define BITS_HW_FLOW_CTL_EN_8814B \
+ (BIT_MASK_HW_FLOW_CTL_EN_8814B << BIT_SHIFT_HW_FLOW_CTL_EN_8814B)
+#define BIT_CLEAR_HW_FLOW_CTL_EN_8814B(x) ((x) & (~BITS_HW_FLOW_CTL_EN_8814B))
+#define BIT_GET_HW_FLOW_CTL_EN_8814B(x) \
+ (((x) >> BIT_SHIFT_HW_FLOW_CTL_EN_8814B) & \
+ BIT_MASK_HW_FLOW_CTL_EN_8814B)
+#define BIT_SET_HW_FLOW_CTL_EN_8814B(x, v) \
+ (BIT_CLEAR_HW_FLOW_CTL_EN_8814B(x) | BIT_HW_FLOW_CTL_EN_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_SDIO_TXAGG_ALIGN_ADJUST_EN_V1_8814B BIT(15)
+
+#define BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1_8814B 0
+#define BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1_8814B 0xfff
+#define BIT_SDIO_TXAGG_ALIGN_SIZE_V1_8814B(x) \
+ (((x) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1_8814B) \
+ << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1_8814B)
+#define BITS_SDIO_TXAGG_ALIGN_SIZE_V1_8814B \
+ (BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1_8814B \
+ << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1_8814B)
+#define BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_V1_8814B(x) \
+ ((x) & (~BITS_SDIO_TXAGG_ALIGN_SIZE_V1_8814B))
+#define BIT_GET_SDIO_TXAGG_ALIGN_SIZE_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_V1_8814B) & \
+ BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_V1_8814B)
+#define BIT_SET_SDIO_TXAGG_ALIGN_SIZE_V1_8814B(x, v) \
+ (BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_V1_8814B(x) | \
+ BIT_SDIO_TXAGG_ALIGN_SIZE_V1_8814B(v))
+
+/* 2 REG_H2C_HEAD_8814B */
+
+#define BIT_SHIFT_H2C_HEAD_V1_8814B 0
+#define BIT_MASK_H2C_HEAD_V1_8814B 0x7ffff
+#define BIT_H2C_HEAD_V1_8814B(x) \
+ (((x) & BIT_MASK_H2C_HEAD_V1_8814B) << BIT_SHIFT_H2C_HEAD_V1_8814B)
+#define BITS_H2C_HEAD_V1_8814B \
+ (BIT_MASK_H2C_HEAD_V1_8814B << BIT_SHIFT_H2C_HEAD_V1_8814B)
+#define BIT_CLEAR_H2C_HEAD_V1_8814B(x) ((x) & (~BITS_H2C_HEAD_V1_8814B))
+#define BIT_GET_H2C_HEAD_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_H2C_HEAD_V1_8814B) & BIT_MASK_H2C_HEAD_V1_8814B)
+#define BIT_SET_H2C_HEAD_V1_8814B(x, v) \
+ (BIT_CLEAR_H2C_HEAD_V1_8814B(x) | BIT_H2C_HEAD_V1_8814B(v))
+
+/* 2 REG_H2C_TAIL_8814B */
+
+#define BIT_SHIFT_H2C_TAIL_V1_8814B 0
+#define BIT_MASK_H2C_TAIL_V1_8814B 0x7ffff
+#define BIT_H2C_TAIL_V1_8814B(x) \
+ (((x) & BIT_MASK_H2C_TAIL_V1_8814B) << BIT_SHIFT_H2C_TAIL_V1_8814B)
+#define BITS_H2C_TAIL_V1_8814B \
+ (BIT_MASK_H2C_TAIL_V1_8814B << BIT_SHIFT_H2C_TAIL_V1_8814B)
+#define BIT_CLEAR_H2C_TAIL_V1_8814B(x) ((x) & (~BITS_H2C_TAIL_V1_8814B))
+#define BIT_GET_H2C_TAIL_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_H2C_TAIL_V1_8814B) & BIT_MASK_H2C_TAIL_V1_8814B)
+#define BIT_SET_H2C_TAIL_V1_8814B(x, v) \
+ (BIT_CLEAR_H2C_TAIL_V1_8814B(x) | BIT_H2C_TAIL_V1_8814B(v))
+
+/* 2 REG_H2C_READ_ADDR_8814B */
+
+#define BIT_SHIFT_H2C_READ_ADDR_V1_8814B 0
+#define BIT_MASK_H2C_READ_ADDR_V1_8814B 0x7ffff
+#define BIT_H2C_READ_ADDR_V1_8814B(x) \
+ (((x) & BIT_MASK_H2C_READ_ADDR_V1_8814B) \
+ << BIT_SHIFT_H2C_READ_ADDR_V1_8814B)
+#define BITS_H2C_READ_ADDR_V1_8814B \
+ (BIT_MASK_H2C_READ_ADDR_V1_8814B << BIT_SHIFT_H2C_READ_ADDR_V1_8814B)
+#define BIT_CLEAR_H2C_READ_ADDR_V1_8814B(x) \
+ ((x) & (~BITS_H2C_READ_ADDR_V1_8814B))
+#define BIT_GET_H2C_READ_ADDR_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_H2C_READ_ADDR_V1_8814B) & \
+ BIT_MASK_H2C_READ_ADDR_V1_8814B)
+#define BIT_SET_H2C_READ_ADDR_V1_8814B(x, v) \
+ (BIT_CLEAR_H2C_READ_ADDR_V1_8814B(x) | BIT_H2C_READ_ADDR_V1_8814B(v))
+
+/* 2 REG_H2C_WR_ADDR_8814B */
+
+#define BIT_SHIFT_H2C_WR_ADDR_V1_8814B 0
+#define BIT_MASK_H2C_WR_ADDR_V1_8814B 0x7ffff
+#define BIT_H2C_WR_ADDR_V1_8814B(x) \
+ (((x) & BIT_MASK_H2C_WR_ADDR_V1_8814B) \
+ << BIT_SHIFT_H2C_WR_ADDR_V1_8814B)
+#define BITS_H2C_WR_ADDR_V1_8814B \
+ (BIT_MASK_H2C_WR_ADDR_V1_8814B << BIT_SHIFT_H2C_WR_ADDR_V1_8814B)
+#define BIT_CLEAR_H2C_WR_ADDR_V1_8814B(x) ((x) & (~BITS_H2C_WR_ADDR_V1_8814B))
+#define BIT_GET_H2C_WR_ADDR_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_H2C_WR_ADDR_V1_8814B) & \
+ BIT_MASK_H2C_WR_ADDR_V1_8814B)
+#define BIT_SET_H2C_WR_ADDR_V1_8814B(x, v) \
+ (BIT_CLEAR_H2C_WR_ADDR_V1_8814B(x) | BIT_H2C_WR_ADDR_V1_8814B(v))
+
+/* 2 REG_H2C_INFO_8814B */
+#define BIT_H2C_SPACE_VLD_8814B BIT(3)
+#define BIT_H2C_WR_ADDR_RST_8814B BIT(2)
+
+#define BIT_SHIFT_H2C_LEN_SEL_8814B 0
+#define BIT_MASK_H2C_LEN_SEL_8814B 0x3
+#define BIT_H2C_LEN_SEL_8814B(x) \
+ (((x) & BIT_MASK_H2C_LEN_SEL_8814B) << BIT_SHIFT_H2C_LEN_SEL_8814B)
+#define BITS_H2C_LEN_SEL_8814B \
+ (BIT_MASK_H2C_LEN_SEL_8814B << BIT_SHIFT_H2C_LEN_SEL_8814B)
+#define BIT_CLEAR_H2C_LEN_SEL_8814B(x) ((x) & (~BITS_H2C_LEN_SEL_8814B))
+#define BIT_GET_H2C_LEN_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_H2C_LEN_SEL_8814B) & BIT_MASK_H2C_LEN_SEL_8814B)
+#define BIT_SET_H2C_LEN_SEL_8814B(x, v) \
+ (BIT_CLEAR_H2C_LEN_SEL_8814B(x) | BIT_H2C_LEN_SEL_8814B(v))
+
+/* 2 REG_DMA_OQT_0_8814B */
+
+#define BIT_SHIFT_TX_OQT_12_FREE_SPACE_8814B 24
+#define BIT_MASK_TX_OQT_12_FREE_SPACE_8814B 0xff
+#define BIT_TX_OQT_12_FREE_SPACE_8814B(x) \
+ (((x) & BIT_MASK_TX_OQT_12_FREE_SPACE_8814B) \
+ << BIT_SHIFT_TX_OQT_12_FREE_SPACE_8814B)
+#define BITS_TX_OQT_12_FREE_SPACE_8814B \
+ (BIT_MASK_TX_OQT_12_FREE_SPACE_8814B \
+ << BIT_SHIFT_TX_OQT_12_FREE_SPACE_8814B)
+#define BIT_CLEAR_TX_OQT_12_FREE_SPACE_8814B(x) \
+ ((x) & (~BITS_TX_OQT_12_FREE_SPACE_8814B))
+#define BIT_GET_TX_OQT_12_FREE_SPACE_8814B(x) \
+ (((x) >> BIT_SHIFT_TX_OQT_12_FREE_SPACE_8814B) & \
+ BIT_MASK_TX_OQT_12_FREE_SPACE_8814B)
+#define BIT_SET_TX_OQT_12_FREE_SPACE_8814B(x, v) \
+ (BIT_CLEAR_TX_OQT_12_FREE_SPACE_8814B(x) | \
+ BIT_TX_OQT_12_FREE_SPACE_8814B(v))
+
+#define BIT_SHIFT_TX_OQT_8_11_FREE_SPACE_8814B 16
+#define BIT_MASK_TX_OQT_8_11_FREE_SPACE_8814B 0xff
+#define BIT_TX_OQT_8_11_FREE_SPACE_8814B(x) \
+ (((x) & BIT_MASK_TX_OQT_8_11_FREE_SPACE_8814B) \
+ << BIT_SHIFT_TX_OQT_8_11_FREE_SPACE_8814B)
+#define BITS_TX_OQT_8_11_FREE_SPACE_8814B \
+ (BIT_MASK_TX_OQT_8_11_FREE_SPACE_8814B \
+ << BIT_SHIFT_TX_OQT_8_11_FREE_SPACE_8814B)
+#define BIT_CLEAR_TX_OQT_8_11_FREE_SPACE_8814B(x) \
+ ((x) & (~BITS_TX_OQT_8_11_FREE_SPACE_8814B))
+#define BIT_GET_TX_OQT_8_11_FREE_SPACE_8814B(x) \
+ (((x) >> BIT_SHIFT_TX_OQT_8_11_FREE_SPACE_8814B) & \
+ BIT_MASK_TX_OQT_8_11_FREE_SPACE_8814B)
+#define BIT_SET_TX_OQT_8_11_FREE_SPACE_8814B(x, v) \
+ (BIT_CLEAR_TX_OQT_8_11_FREE_SPACE_8814B(x) | \
+ BIT_TX_OQT_8_11_FREE_SPACE_8814B(v))
+
+#define BIT_SHIFT_TX_OQT_4_7_FREE_SPACE_8814B 8
+#define BIT_MASK_TX_OQT_4_7_FREE_SPACE_8814B 0xff
+#define BIT_TX_OQT_4_7_FREE_SPACE_8814B(x) \
+ (((x) & BIT_MASK_TX_OQT_4_7_FREE_SPACE_8814B) \
+ << BIT_SHIFT_TX_OQT_4_7_FREE_SPACE_8814B)
+#define BITS_TX_OQT_4_7_FREE_SPACE_8814B \
+ (BIT_MASK_TX_OQT_4_7_FREE_SPACE_8814B \
+ << BIT_SHIFT_TX_OQT_4_7_FREE_SPACE_8814B)
+#define BIT_CLEAR_TX_OQT_4_7_FREE_SPACE_8814B(x) \
+ ((x) & (~BITS_TX_OQT_4_7_FREE_SPACE_8814B))
+#define BIT_GET_TX_OQT_4_7_FREE_SPACE_8814B(x) \
+ (((x) >> BIT_SHIFT_TX_OQT_4_7_FREE_SPACE_8814B) & \
+ BIT_MASK_TX_OQT_4_7_FREE_SPACE_8814B)
+#define BIT_SET_TX_OQT_4_7_FREE_SPACE_8814B(x, v) \
+ (BIT_CLEAR_TX_OQT_4_7_FREE_SPACE_8814B(x) | \
+ BIT_TX_OQT_4_7_FREE_SPACE_8814B(v))
+
+#define BIT_SHIFT_TX_OQT_0_3_FREE_SPACE_8814B 0
+#define BIT_MASK_TX_OQT_0_3_FREE_SPACE_8814B 0xff
+#define BIT_TX_OQT_0_3_FREE_SPACE_8814B(x) \
+ (((x) & BIT_MASK_TX_OQT_0_3_FREE_SPACE_8814B) \
+ << BIT_SHIFT_TX_OQT_0_3_FREE_SPACE_8814B)
+#define BITS_TX_OQT_0_3_FREE_SPACE_8814B \
+ (BIT_MASK_TX_OQT_0_3_FREE_SPACE_8814B \
+ << BIT_SHIFT_TX_OQT_0_3_FREE_SPACE_8814B)
+#define BIT_CLEAR_TX_OQT_0_3_FREE_SPACE_8814B(x) \
+ ((x) & (~BITS_TX_OQT_0_3_FREE_SPACE_8814B))
+#define BIT_GET_TX_OQT_0_3_FREE_SPACE_8814B(x) \
+ (((x) >> BIT_SHIFT_TX_OQT_0_3_FREE_SPACE_8814B) & \
+ BIT_MASK_TX_OQT_0_3_FREE_SPACE_8814B)
+#define BIT_SET_TX_OQT_0_3_FREE_SPACE_8814B(x, v) \
+ (BIT_CLEAR_TX_OQT_0_3_FREE_SPACE_8814B(x) | \
+ BIT_TX_OQT_0_3_FREE_SPACE_8814B(v))
+
+/* 2 REG_DMA_OQT_1_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_TX_OQT_16_FREE_SPACE_8814B 16
+#define BIT_MASK_TX_OQT_16_FREE_SPACE_8814B 0xff
+#define BIT_TX_OQT_16_FREE_SPACE_8814B(x) \
+ (((x) & BIT_MASK_TX_OQT_16_FREE_SPACE_8814B) \
+ << BIT_SHIFT_TX_OQT_16_FREE_SPACE_8814B)
+#define BITS_TX_OQT_16_FREE_SPACE_8814B \
+ (BIT_MASK_TX_OQT_16_FREE_SPACE_8814B \
+ << BIT_SHIFT_TX_OQT_16_FREE_SPACE_8814B)
+#define BIT_CLEAR_TX_OQT_16_FREE_SPACE_8814B(x) \
+ ((x) & (~BITS_TX_OQT_16_FREE_SPACE_8814B))
+#define BIT_GET_TX_OQT_16_FREE_SPACE_8814B(x) \
+ (((x) >> BIT_SHIFT_TX_OQT_16_FREE_SPACE_8814B) & \
+ BIT_MASK_TX_OQT_16_FREE_SPACE_8814B)
+#define BIT_SET_TX_OQT_16_FREE_SPACE_8814B(x, v) \
+ (BIT_CLEAR_TX_OQT_16_FREE_SPACE_8814B(x) | \
+ BIT_TX_OQT_16_FREE_SPACE_8814B(v))
+
+#define BIT_SHIFT_TX_OQT_14_15_FREE_SPACE_8814B 8
+#define BIT_MASK_TX_OQT_14_15_FREE_SPACE_8814B 0xff
+#define BIT_TX_OQT_14_15_FREE_SPACE_8814B(x) \
+ (((x) & BIT_MASK_TX_OQT_14_15_FREE_SPACE_8814B) \
+ << BIT_SHIFT_TX_OQT_14_15_FREE_SPACE_8814B)
+#define BITS_TX_OQT_14_15_FREE_SPACE_8814B \
+ (BIT_MASK_TX_OQT_14_15_FREE_SPACE_8814B \
+ << BIT_SHIFT_TX_OQT_14_15_FREE_SPACE_8814B)
+#define BIT_CLEAR_TX_OQT_14_15_FREE_SPACE_8814B(x) \
+ ((x) & (~BITS_TX_OQT_14_15_FREE_SPACE_8814B))
+#define BIT_GET_TX_OQT_14_15_FREE_SPACE_8814B(x) \
+ (((x) >> BIT_SHIFT_TX_OQT_14_15_FREE_SPACE_8814B) & \
+ BIT_MASK_TX_OQT_14_15_FREE_SPACE_8814B)
+#define BIT_SET_TX_OQT_14_15_FREE_SPACE_8814B(x, v) \
+ (BIT_CLEAR_TX_OQT_14_15_FREE_SPACE_8814B(x) | \
+ BIT_TX_OQT_14_15_FREE_SPACE_8814B(v))
+
+#define BIT_SHIFT_TX_OQT_13_FREE_SPACE_8814B 0
+#define BIT_MASK_TX_OQT_13_FREE_SPACE_8814B 0xff
+#define BIT_TX_OQT_13_FREE_SPACE_8814B(x) \
+ (((x) & BIT_MASK_TX_OQT_13_FREE_SPACE_8814B) \
+ << BIT_SHIFT_TX_OQT_13_FREE_SPACE_8814B)
+#define BITS_TX_OQT_13_FREE_SPACE_8814B \
+ (BIT_MASK_TX_OQT_13_FREE_SPACE_8814B \
+ << BIT_SHIFT_TX_OQT_13_FREE_SPACE_8814B)
+#define BIT_CLEAR_TX_OQT_13_FREE_SPACE_8814B(x) \
+ ((x) & (~BITS_TX_OQT_13_FREE_SPACE_8814B))
+#define BIT_GET_TX_OQT_13_FREE_SPACE_8814B(x) \
+ (((x) >> BIT_SHIFT_TX_OQT_13_FREE_SPACE_8814B) & \
+ BIT_MASK_TX_OQT_13_FREE_SPACE_8814B)
+#define BIT_SET_TX_OQT_13_FREE_SPACE_8814B(x, v) \
+ (BIT_CLEAR_TX_OQT_13_FREE_SPACE_8814B(x) | \
+ BIT_TX_OQT_13_FREE_SPACE_8814B(v))
+
+/* 2 REG_RXDMA_AGG_PG_TH_8814B */
+#define BIT_DMA_STORE_8814B BIT(31)
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_EN_PRE_CALC_8814B BIT(29)
+#define BIT_RXAGG_SW_EN_8814B BIT(28)
+#define BIT_RXAGG_SW_TRIG_8814B BIT(27)
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_DMA_AGG_TO_V1_8814B 8
+#define BIT_MASK_DMA_AGG_TO_V1_8814B 0xff
+#define BIT_DMA_AGG_TO_V1_8814B(x) \
+ (((x) & BIT_MASK_DMA_AGG_TO_V1_8814B) << BIT_SHIFT_DMA_AGG_TO_V1_8814B)
+#define BITS_DMA_AGG_TO_V1_8814B \
+ (BIT_MASK_DMA_AGG_TO_V1_8814B << BIT_SHIFT_DMA_AGG_TO_V1_8814B)
+#define BIT_CLEAR_DMA_AGG_TO_V1_8814B(x) ((x) & (~BITS_DMA_AGG_TO_V1_8814B))
+#define BIT_GET_DMA_AGG_TO_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_DMA_AGG_TO_V1_8814B) & BIT_MASK_DMA_AGG_TO_V1_8814B)
+#define BIT_SET_DMA_AGG_TO_V1_8814B(x, v) \
+ (BIT_CLEAR_DMA_AGG_TO_V1_8814B(x) | BIT_DMA_AGG_TO_V1_8814B(v))
+
+#define BIT_SHIFT_RXDMA_AGG_PG_TH_8814B 0
+#define BIT_MASK_RXDMA_AGG_PG_TH_8814B 0xff
+#define BIT_RXDMA_AGG_PG_TH_8814B(x) \
+ (((x) & BIT_MASK_RXDMA_AGG_PG_TH_8814B) \
+ << BIT_SHIFT_RXDMA_AGG_PG_TH_8814B)
+#define BITS_RXDMA_AGG_PG_TH_8814B \
+ (BIT_MASK_RXDMA_AGG_PG_TH_8814B << BIT_SHIFT_RXDMA_AGG_PG_TH_8814B)
+#define BIT_CLEAR_RXDMA_AGG_PG_TH_8814B(x) ((x) & (~BITS_RXDMA_AGG_PG_TH_8814B))
+#define BIT_GET_RXDMA_AGG_PG_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_8814B) & \
+ BIT_MASK_RXDMA_AGG_PG_TH_8814B)
+#define BIT_SET_RXDMA_AGG_PG_TH_8814B(x, v) \
+ (BIT_CLEAR_RXDMA_AGG_PG_TH_8814B(x) | BIT_RXDMA_AGG_PG_TH_8814B(v))
+
+/* 2 REG_RXDMA_CTRL_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8814B 20
+#define BIT_MASK_FW_UPD_RDPTR19_TO_16_8814B 0xf
+#define BIT_FW_UPD_RDPTR19_TO_16_8814B(x) \
+ (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8814B) \
+ << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8814B)
+#define BITS_FW_UPD_RDPTR19_TO_16_8814B \
+ (BIT_MASK_FW_UPD_RDPTR19_TO_16_8814B \
+ << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8814B)
+#define BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8814B(x) \
+ ((x) & (~BITS_FW_UPD_RDPTR19_TO_16_8814B))
+#define BIT_GET_FW_UPD_RDPTR19_TO_16_8814B(x) \
+ (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8814B) & \
+ BIT_MASK_FW_UPD_RDPTR19_TO_16_8814B)
+#define BIT_SET_FW_UPD_RDPTR19_TO_16_8814B(x, v) \
+ (BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8814B(x) | \
+ BIT_FW_UPD_RDPTR19_TO_16_8814B(v))
+
+#define BIT_RXDMA_REQ_8814B BIT(19)
+#define BIT_RW_RELEASE_EN_8814B BIT(18)
+#define BIT_RXDMA_IDLE_8814B BIT(17)
+#define BIT_RXPKT_RELEASE_POLL_8814B BIT(16)
+
+#define BIT_SHIFT_FW_UPD_RDPTR_8814B 0
+#define BIT_MASK_FW_UPD_RDPTR_8814B 0xffff
+#define BIT_FW_UPD_RDPTR_8814B(x) \
+ (((x) & BIT_MASK_FW_UPD_RDPTR_8814B) << BIT_SHIFT_FW_UPD_RDPTR_8814B)
+#define BITS_FW_UPD_RDPTR_8814B \
+ (BIT_MASK_FW_UPD_RDPTR_8814B << BIT_SHIFT_FW_UPD_RDPTR_8814B)
+#define BIT_CLEAR_FW_UPD_RDPTR_8814B(x) ((x) & (~BITS_FW_UPD_RDPTR_8814B))
+#define BIT_GET_FW_UPD_RDPTR_8814B(x) \
+ (((x) >> BIT_SHIFT_FW_UPD_RDPTR_8814B) & BIT_MASK_FW_UPD_RDPTR_8814B)
+#define BIT_SET_FW_UPD_RDPTR_8814B(x, v) \
+ (BIT_CLEAR_FW_UPD_RDPTR_8814B(x) | BIT_FW_UPD_RDPTR_8814B(v))
+
+/* 2 REG_RXDMA_STATUS_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_C2H_PKT_OVF_8814B BIT(7)
+#define BIT_AGG_CONFGI_ISSUE_8814B BIT(6)
+#define BIT_FW_POLL_ISSUE_8814B BIT(5)
+#define BIT_RX_DATA_UDN_8814B BIT(4)
+#define BIT_RX_SFF_UDN_8814B BIT(3)
+#define BIT_RX_SFF_OVF_8814B BIT(2)
+#define BIT_RXPKT_OVF_8814B BIT(0)
+
+/* 2 REG_RXDMA_DPR_8814B */
+
+#define BIT_SHIFT_RDE_DEBUG_8814B 0
+#define BIT_MASK_RDE_DEBUG_8814B 0xffffffffL
+#define BIT_RDE_DEBUG_8814B(x) \
+ (((x) & BIT_MASK_RDE_DEBUG_8814B) << BIT_SHIFT_RDE_DEBUG_8814B)
+#define BITS_RDE_DEBUG_8814B \
+ (BIT_MASK_RDE_DEBUG_8814B << BIT_SHIFT_RDE_DEBUG_8814B)
+#define BIT_CLEAR_RDE_DEBUG_8814B(x) ((x) & (~BITS_RDE_DEBUG_8814B))
+#define BIT_GET_RDE_DEBUG_8814B(x) \
+ (((x) >> BIT_SHIFT_RDE_DEBUG_8814B) & BIT_MASK_RDE_DEBUG_8814B)
+#define BIT_SET_RDE_DEBUG_8814B(x, v) \
+ (BIT_CLEAR_RDE_DEBUG_8814B(x) | BIT_RDE_DEBUG_8814B(v))
+
+/* 2 REG_RXDMA_MODE_8814B */
+
+#define BIT_SHIFT_PKTNUM_TH_V2_8814B 24
+#define BIT_MASK_PKTNUM_TH_V2_8814B 0x1f
+#define BIT_PKTNUM_TH_V2_8814B(x) \
+ (((x) & BIT_MASK_PKTNUM_TH_V2_8814B) << BIT_SHIFT_PKTNUM_TH_V2_8814B)
+#define BITS_PKTNUM_TH_V2_8814B \
+ (BIT_MASK_PKTNUM_TH_V2_8814B << BIT_SHIFT_PKTNUM_TH_V2_8814B)
+#define BIT_CLEAR_PKTNUM_TH_V2_8814B(x) ((x) & (~BITS_PKTNUM_TH_V2_8814B))
+#define BIT_GET_PKTNUM_TH_V2_8814B(x) \
+ (((x) >> BIT_SHIFT_PKTNUM_TH_V2_8814B) & BIT_MASK_PKTNUM_TH_V2_8814B)
+#define BIT_SET_PKTNUM_TH_V2_8814B(x, v) \
+ (BIT_CLEAR_PKTNUM_TH_V2_8814B(x) | BIT_PKTNUM_TH_V2_8814B(v))
+
+#define BIT_TXBA_BREAK_USBAGG_8814B BIT(23)
+
+#define BIT_SHIFT_PKTLEN_PARA_8814B 16
+#define BIT_MASK_PKTLEN_PARA_8814B 0x7
+#define BIT_PKTLEN_PARA_8814B(x) \
+ (((x) & BIT_MASK_PKTLEN_PARA_8814B) << BIT_SHIFT_PKTLEN_PARA_8814B)
+#define BITS_PKTLEN_PARA_8814B \
+ (BIT_MASK_PKTLEN_PARA_8814B << BIT_SHIFT_PKTLEN_PARA_8814B)
+#define BIT_CLEAR_PKTLEN_PARA_8814B(x) ((x) & (~BITS_PKTLEN_PARA_8814B))
+#define BIT_GET_PKTLEN_PARA_8814B(x) \
+ (((x) >> BIT_SHIFT_PKTLEN_PARA_8814B) & BIT_MASK_PKTLEN_PARA_8814B)
+#define BIT_SET_PKTLEN_PARA_8814B(x, v) \
+ (BIT_CLEAR_PKTLEN_PARA_8814B(x) | BIT_PKTLEN_PARA_8814B(v))
+
+#define BIT_RX_DBG_SEL_8814B BIT(7)
+#define BIT_EN_SPD_8814B BIT(6)
+
+#define BIT_SHIFT_BURST_SIZE_8814B 4
+#define BIT_MASK_BURST_SIZE_8814B 0x3
+#define BIT_BURST_SIZE_8814B(x) \
+ (((x) & BIT_MASK_BURST_SIZE_8814B) << BIT_SHIFT_BURST_SIZE_8814B)
+#define BITS_BURST_SIZE_8814B \
+ (BIT_MASK_BURST_SIZE_8814B << BIT_SHIFT_BURST_SIZE_8814B)
+#define BIT_CLEAR_BURST_SIZE_8814B(x) ((x) & (~BITS_BURST_SIZE_8814B))
+#define BIT_GET_BURST_SIZE_8814B(x) \
+ (((x) >> BIT_SHIFT_BURST_SIZE_8814B) & BIT_MASK_BURST_SIZE_8814B)
+#define BIT_SET_BURST_SIZE_8814B(x, v) \
+ (BIT_CLEAR_BURST_SIZE_8814B(x) | BIT_BURST_SIZE_8814B(v))
+
+#define BIT_SHIFT_BURST_CNT_8814B 2
+#define BIT_MASK_BURST_CNT_8814B 0x3
+#define BIT_BURST_CNT_8814B(x) \
+ (((x) & BIT_MASK_BURST_CNT_8814B) << BIT_SHIFT_BURST_CNT_8814B)
+#define BITS_BURST_CNT_8814B \
+ (BIT_MASK_BURST_CNT_8814B << BIT_SHIFT_BURST_CNT_8814B)
+#define BIT_CLEAR_BURST_CNT_8814B(x) ((x) & (~BITS_BURST_CNT_8814B))
+#define BIT_GET_BURST_CNT_8814B(x) \
+ (((x) >> BIT_SHIFT_BURST_CNT_8814B) & BIT_MASK_BURST_CNT_8814B)
+#define BIT_SET_BURST_CNT_8814B(x, v) \
+ (BIT_CLEAR_BURST_CNT_8814B(x) | BIT_BURST_CNT_8814B(v))
+
+#define BIT_DMA_MODE_8814B BIT(1)
+
+/* 2 REG_C2H_PKT_8814B */
+
+#define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8814B 24
+#define BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8814B 0xf
+#define BIT_R_C2H_STR_ADDR_16_TO_19_8814B(x) \
+ (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8814B) \
+ << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8814B)
+#define BITS_R_C2H_STR_ADDR_16_TO_19_8814B \
+ (BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8814B \
+ << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8814B)
+#define BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8814B(x) \
+ ((x) & (~BITS_R_C2H_STR_ADDR_16_TO_19_8814B))
+#define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8814B(x) \
+ (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8814B) & \
+ BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8814B)
+#define BIT_SET_R_C2H_STR_ADDR_16_TO_19_8814B(x, v) \
+ (BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8814B(x) | \
+ BIT_R_C2H_STR_ADDR_16_TO_19_8814B(v))
+
+#define BIT_R_C2H_PKT_REQ_8814B BIT(16)
+
+#define BIT_SHIFT_R_C2H_STR_ADDR_8814B 0
+#define BIT_MASK_R_C2H_STR_ADDR_8814B 0xffff
+#define BIT_R_C2H_STR_ADDR_8814B(x) \
+ (((x) & BIT_MASK_R_C2H_STR_ADDR_8814B) \
+ << BIT_SHIFT_R_C2H_STR_ADDR_8814B)
+#define BITS_R_C2H_STR_ADDR_8814B \
+ (BIT_MASK_R_C2H_STR_ADDR_8814B << BIT_SHIFT_R_C2H_STR_ADDR_8814B)
+#define BIT_CLEAR_R_C2H_STR_ADDR_8814B(x) ((x) & (~BITS_R_C2H_STR_ADDR_8814B))
+#define BIT_GET_R_C2H_STR_ADDR_8814B(x) \
+ (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8814B) & \
+ BIT_MASK_R_C2H_STR_ADDR_8814B)
+#define BIT_SET_R_C2H_STR_ADDR_8814B(x, v) \
+ (BIT_CLEAR_R_C2H_STR_ADDR_8814B(x) | BIT_R_C2H_STR_ADDR_8814B(v))
+
+/* 2 REG_FWFF_C2H_8814B */
+
+#define BIT_SHIFT_C2H_DMA_ADDR_8814B 0
+#define BIT_MASK_C2H_DMA_ADDR_8814B 0x3ffff
+#define BIT_C2H_DMA_ADDR_8814B(x) \
+ (((x) & BIT_MASK_C2H_DMA_ADDR_8814B) << BIT_SHIFT_C2H_DMA_ADDR_8814B)
+#define BITS_C2H_DMA_ADDR_8814B \
+ (BIT_MASK_C2H_DMA_ADDR_8814B << BIT_SHIFT_C2H_DMA_ADDR_8814B)
+#define BIT_CLEAR_C2H_DMA_ADDR_8814B(x) ((x) & (~BITS_C2H_DMA_ADDR_8814B))
+#define BIT_GET_C2H_DMA_ADDR_8814B(x) \
+ (((x) >> BIT_SHIFT_C2H_DMA_ADDR_8814B) & BIT_MASK_C2H_DMA_ADDR_8814B)
+#define BIT_SET_C2H_DMA_ADDR_8814B(x, v) \
+ (BIT_CLEAR_C2H_DMA_ADDR_8814B(x) | BIT_C2H_DMA_ADDR_8814B(v))
+
+/* 2 REG_FWFF_CTRL_8814B */
+#define BIT_FWFF_DMAPKT_REQ_8814B BIT(31)
+
+#define BIT_SHIFT_FWFF_DMA_PKT_NUM_V1_8814B 16
+#define BIT_MASK_FWFF_DMA_PKT_NUM_V1_8814B 0x7fff
+#define BIT_FWFF_DMA_PKT_NUM_V1_8814B(x) \
+ (((x) & BIT_MASK_FWFF_DMA_PKT_NUM_V1_8814B) \
+ << BIT_SHIFT_FWFF_DMA_PKT_NUM_V1_8814B)
+#define BITS_FWFF_DMA_PKT_NUM_V1_8814B \
+ (BIT_MASK_FWFF_DMA_PKT_NUM_V1_8814B \
+ << BIT_SHIFT_FWFF_DMA_PKT_NUM_V1_8814B)
+#define BIT_CLEAR_FWFF_DMA_PKT_NUM_V1_8814B(x) \
+ ((x) & (~BITS_FWFF_DMA_PKT_NUM_V1_8814B))
+#define BIT_GET_FWFF_DMA_PKT_NUM_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_V1_8814B) & \
+ BIT_MASK_FWFF_DMA_PKT_NUM_V1_8814B)
+#define BIT_SET_FWFF_DMA_PKT_NUM_V1_8814B(x, v) \
+ (BIT_CLEAR_FWFF_DMA_PKT_NUM_V1_8814B(x) | \
+ BIT_FWFF_DMA_PKT_NUM_V1_8814B(v))
+
+#define BIT_SHIFT_FWFF_STR_ADDR_8814B 0
+#define BIT_MASK_FWFF_STR_ADDR_8814B 0xffff
+#define BIT_FWFF_STR_ADDR_8814B(x) \
+ (((x) & BIT_MASK_FWFF_STR_ADDR_8814B) << BIT_SHIFT_FWFF_STR_ADDR_8814B)
+#define BITS_FWFF_STR_ADDR_8814B \
+ (BIT_MASK_FWFF_STR_ADDR_8814B << BIT_SHIFT_FWFF_STR_ADDR_8814B)
+#define BIT_CLEAR_FWFF_STR_ADDR_8814B(x) ((x) & (~BITS_FWFF_STR_ADDR_8814B))
+#define BIT_GET_FWFF_STR_ADDR_8814B(x) \
+ (((x) >> BIT_SHIFT_FWFF_STR_ADDR_8814B) & BIT_MASK_FWFF_STR_ADDR_8814B)
+#define BIT_SET_FWFF_STR_ADDR_8814B(x, v) \
+ (BIT_CLEAR_FWFF_STR_ADDR_8814B(x) | BIT_FWFF_STR_ADDR_8814B(v))
+
+/* 2 REG_FWFF_PKT_INFO_8814B */
+
+#define BIT_SHIFT_FWFF_PKT_READ_ADDR_8814B 16
+#define BIT_MASK_FWFF_PKT_READ_ADDR_8814B 0xffff
+#define BIT_FWFF_PKT_READ_ADDR_8814B(x) \
+ (((x) & BIT_MASK_FWFF_PKT_READ_ADDR_8814B) \
+ << BIT_SHIFT_FWFF_PKT_READ_ADDR_8814B)
+#define BITS_FWFF_PKT_READ_ADDR_8814B \
+ (BIT_MASK_FWFF_PKT_READ_ADDR_8814B \
+ << BIT_SHIFT_FWFF_PKT_READ_ADDR_8814B)
+#define BIT_CLEAR_FWFF_PKT_READ_ADDR_8814B(x) \
+ ((x) & (~BITS_FWFF_PKT_READ_ADDR_8814B))
+#define BIT_GET_FWFF_PKT_READ_ADDR_8814B(x) \
+ (((x) >> BIT_SHIFT_FWFF_PKT_READ_ADDR_8814B) & \
+ BIT_MASK_FWFF_PKT_READ_ADDR_8814B)
+#define BIT_SET_FWFF_PKT_READ_ADDR_8814B(x, v) \
+ (BIT_CLEAR_FWFF_PKT_READ_ADDR_8814B(x) | \
+ BIT_FWFF_PKT_READ_ADDR_8814B(v))
+
+#define BIT_SHIFT_FWFF_PKT_WRITE_ADDR_8814B 0
+#define BIT_MASK_FWFF_PKT_WRITE_ADDR_8814B 0xffff
+#define BIT_FWFF_PKT_WRITE_ADDR_8814B(x) \
+ (((x) & BIT_MASK_FWFF_PKT_WRITE_ADDR_8814B) \
+ << BIT_SHIFT_FWFF_PKT_WRITE_ADDR_8814B)
+#define BITS_FWFF_PKT_WRITE_ADDR_8814B \
+ (BIT_MASK_FWFF_PKT_WRITE_ADDR_8814B \
+ << BIT_SHIFT_FWFF_PKT_WRITE_ADDR_8814B)
+#define BIT_CLEAR_FWFF_PKT_WRITE_ADDR_8814B(x) \
+ ((x) & (~BITS_FWFF_PKT_WRITE_ADDR_8814B))
+#define BIT_GET_FWFF_PKT_WRITE_ADDR_8814B(x) \
+ (((x) >> BIT_SHIFT_FWFF_PKT_WRITE_ADDR_8814B) & \
+ BIT_MASK_FWFF_PKT_WRITE_ADDR_8814B)
+#define BIT_SET_FWFF_PKT_WRITE_ADDR_8814B(x, v) \
+ (BIT_CLEAR_FWFF_PKT_WRITE_ADDR_8814B(x) | \
+ BIT_FWFF_PKT_WRITE_ADDR_8814B(v))
+
+/* 2 REG_FWFF_PKT_INFO2_8814B */
+
+#define BIT_SHIFT_FWFF_PKT_QUEUED_V1_8814B 0
+#define BIT_MASK_FWFF_PKT_QUEUED_V1_8814B 0xffff
+#define BIT_FWFF_PKT_QUEUED_V1_8814B(x) \
+ (((x) & BIT_MASK_FWFF_PKT_QUEUED_V1_8814B) \
+ << BIT_SHIFT_FWFF_PKT_QUEUED_V1_8814B)
+#define BITS_FWFF_PKT_QUEUED_V1_8814B \
+ (BIT_MASK_FWFF_PKT_QUEUED_V1_8814B \
+ << BIT_SHIFT_FWFF_PKT_QUEUED_V1_8814B)
+#define BIT_CLEAR_FWFF_PKT_QUEUED_V1_8814B(x) \
+ ((x) & (~BITS_FWFF_PKT_QUEUED_V1_8814B))
+#define BIT_GET_FWFF_PKT_QUEUED_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_V1_8814B) & \
+ BIT_MASK_FWFF_PKT_QUEUED_V1_8814B)
+#define BIT_SET_FWFF_PKT_QUEUED_V1_8814B(x, v) \
+ (BIT_CLEAR_FWFF_PKT_QUEUED_V1_8814B(x) | \
+ BIT_FWFF_PKT_QUEUED_V1_8814B(v))
+
+/* 2 REG_RXPKTNUM_8814B */
+
+#define BIT_SHIFT_PKT_NUM_WOL_V1_8814B 16
+#define BIT_MASK_PKT_NUM_WOL_V1_8814B 0xffff
+#define BIT_PKT_NUM_WOL_V1_8814B(x) \
+ (((x) & BIT_MASK_PKT_NUM_WOL_V1_8814B) \
+ << BIT_SHIFT_PKT_NUM_WOL_V1_8814B)
+#define BITS_PKT_NUM_WOL_V1_8814B \
+ (BIT_MASK_PKT_NUM_WOL_V1_8814B << BIT_SHIFT_PKT_NUM_WOL_V1_8814B)
+#define BIT_CLEAR_PKT_NUM_WOL_V1_8814B(x) ((x) & (~BITS_PKT_NUM_WOL_V1_8814B))
+#define BIT_GET_PKT_NUM_WOL_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_PKT_NUM_WOL_V1_8814B) & \
+ BIT_MASK_PKT_NUM_WOL_V1_8814B)
+#define BIT_SET_PKT_NUM_WOL_V1_8814B(x, v) \
+ (BIT_CLEAR_PKT_NUM_WOL_V1_8814B(x) | BIT_PKT_NUM_WOL_V1_8814B(v))
+
+#define BIT_SHIFT_RXPKT_NUM_V1_8814B 0
+#define BIT_MASK_RXPKT_NUM_V1_8814B 0xffff
+#define BIT_RXPKT_NUM_V1_8814B(x) \
+ (((x) & BIT_MASK_RXPKT_NUM_V1_8814B) << BIT_SHIFT_RXPKT_NUM_V1_8814B)
+#define BITS_RXPKT_NUM_V1_8814B \
+ (BIT_MASK_RXPKT_NUM_V1_8814B << BIT_SHIFT_RXPKT_NUM_V1_8814B)
+#define BIT_CLEAR_RXPKT_NUM_V1_8814B(x) ((x) & (~BITS_RXPKT_NUM_V1_8814B))
+#define BIT_GET_RXPKT_NUM_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_RXPKT_NUM_V1_8814B) & BIT_MASK_RXPKT_NUM_V1_8814B)
+#define BIT_SET_RXPKT_NUM_V1_8814B(x, v) \
+ (BIT_CLEAR_RXPKT_NUM_V1_8814B(x) | BIT_RXPKT_NUM_V1_8814B(v))
+
+/* 2 REG_RXPKTNUM_TH_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_RXPKT_NUM_TH_8814B 0
+#define BIT_MASK_RXPKT_NUM_TH_8814B 0xff
+#define BIT_RXPKT_NUM_TH_8814B(x) \
+ (((x) & BIT_MASK_RXPKT_NUM_TH_8814B) << BIT_SHIFT_RXPKT_NUM_TH_8814B)
+#define BITS_RXPKT_NUM_TH_8814B \
+ (BIT_MASK_RXPKT_NUM_TH_8814B << BIT_SHIFT_RXPKT_NUM_TH_8814B)
+#define BIT_CLEAR_RXPKT_NUM_TH_8814B(x) ((x) & (~BITS_RXPKT_NUM_TH_8814B))
+#define BIT_GET_RXPKT_NUM_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_RXPKT_NUM_TH_8814B) & BIT_MASK_RXPKT_NUM_TH_8814B)
+#define BIT_SET_RXPKT_NUM_TH_8814B(x, v) \
+ (BIT_CLEAR_RXPKT_NUM_TH_8814B(x) | BIT_RXPKT_NUM_TH_8814B(v))
+
+/* 2 REG_FW_UPD_RXDES_RDPTR_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_FW_UPD_RXDES_RD_PTR_8814B 0
+#define BIT_MASK_FW_UPD_RXDES_RD_PTR_8814B 0x3ffff
+#define BIT_FW_UPD_RXDES_RD_PTR_8814B(x) \
+ (((x) & BIT_MASK_FW_UPD_RXDES_RD_PTR_8814B) \
+ << BIT_SHIFT_FW_UPD_RXDES_RD_PTR_8814B)
+#define BITS_FW_UPD_RXDES_RD_PTR_8814B \
+ (BIT_MASK_FW_UPD_RXDES_RD_PTR_8814B \
+ << BIT_SHIFT_FW_UPD_RXDES_RD_PTR_8814B)
+#define BIT_CLEAR_FW_UPD_RXDES_RD_PTR_8814B(x) \
+ ((x) & (~BITS_FW_UPD_RXDES_RD_PTR_8814B))
+#define BIT_GET_FW_UPD_RXDES_RD_PTR_8814B(x) \
+ (((x) >> BIT_SHIFT_FW_UPD_RXDES_RD_PTR_8814B) & \
+ BIT_MASK_FW_UPD_RXDES_RD_PTR_8814B)
+#define BIT_SET_FW_UPD_RXDES_RD_PTR_8814B(x, v) \
+ (BIT_CLEAR_FW_UPD_RXDES_RD_PTR_8814B(x) | \
+ BIT_FW_UPD_RXDES_RD_PTR_8814B(v))
+
+/* 2 REG_DDMA_CH0SA_8814B */
+
+#define BIT_SHIFT_DDMACH0_SA_8814B 0
+#define BIT_MASK_DDMACH0_SA_8814B 0xffffffffL
+#define BIT_DDMACH0_SA_8814B(x) \
+ (((x) & BIT_MASK_DDMACH0_SA_8814B) << BIT_SHIFT_DDMACH0_SA_8814B)
+#define BITS_DDMACH0_SA_8814B \
+ (BIT_MASK_DDMACH0_SA_8814B << BIT_SHIFT_DDMACH0_SA_8814B)
+#define BIT_CLEAR_DDMACH0_SA_8814B(x) ((x) & (~BITS_DDMACH0_SA_8814B))
+#define BIT_GET_DDMACH0_SA_8814B(x) \
+ (((x) >> BIT_SHIFT_DDMACH0_SA_8814B) & BIT_MASK_DDMACH0_SA_8814B)
+#define BIT_SET_DDMACH0_SA_8814B(x, v) \
+ (BIT_CLEAR_DDMACH0_SA_8814B(x) | BIT_DDMACH0_SA_8814B(v))
+
+/* 2 REG_DDMA_CH0DA_8814B */
+
+#define BIT_SHIFT_DDMACH0_DA_8814B 0
+#define BIT_MASK_DDMACH0_DA_8814B 0xffffffffL
+#define BIT_DDMACH0_DA_8814B(x) \
+ (((x) & BIT_MASK_DDMACH0_DA_8814B) << BIT_SHIFT_DDMACH0_DA_8814B)
+#define BITS_DDMACH0_DA_8814B \
+ (BIT_MASK_DDMACH0_DA_8814B << BIT_SHIFT_DDMACH0_DA_8814B)
+#define BIT_CLEAR_DDMACH0_DA_8814B(x) ((x) & (~BITS_DDMACH0_DA_8814B))
+#define BIT_GET_DDMACH0_DA_8814B(x) \
+ (((x) >> BIT_SHIFT_DDMACH0_DA_8814B) & BIT_MASK_DDMACH0_DA_8814B)
+#define BIT_SET_DDMACH0_DA_8814B(x, v) \
+ (BIT_CLEAR_DDMACH0_DA_8814B(x) | BIT_DDMACH0_DA_8814B(v))
+
+/* 2 REG_DDMA_CH0CTRL_8814B */
+#define BIT_DDMACH0_OWN_8814B BIT(31)
+#define BIT_DDMACH0_IDMEM_ERR_8814B BIT(30)
+#define BIT_DDMACH0_CHKSUM_EN_8814B BIT(29)
+#define BIT_DDMACH0_DA_W_DISABLE_8814B BIT(28)
+#define BIT_DDMACH0_CHKSUM_STS_8814B BIT(27)
+#define BIT_DDMACH0_DDMA_MODE_8814B BIT(26)
+#define BIT_DDMACH0_RESET_CHKSUM_STS_8814B BIT(25)
+#define BIT_DDMACH0_CHKSUM_CONT_8814B BIT(24)
+
+#define BIT_SHIFT_DDMACH0_DLEN_8814B 0
+#define BIT_MASK_DDMACH0_DLEN_8814B 0x3ffff
+#define BIT_DDMACH0_DLEN_8814B(x) \
+ (((x) & BIT_MASK_DDMACH0_DLEN_8814B) << BIT_SHIFT_DDMACH0_DLEN_8814B)
+#define BITS_DDMACH0_DLEN_8814B \
+ (BIT_MASK_DDMACH0_DLEN_8814B << BIT_SHIFT_DDMACH0_DLEN_8814B)
+#define BIT_CLEAR_DDMACH0_DLEN_8814B(x) ((x) & (~BITS_DDMACH0_DLEN_8814B))
+#define BIT_GET_DDMACH0_DLEN_8814B(x) \
+ (((x) >> BIT_SHIFT_DDMACH0_DLEN_8814B) & BIT_MASK_DDMACH0_DLEN_8814B)
+#define BIT_SET_DDMACH0_DLEN_8814B(x, v) \
+ (BIT_CLEAR_DDMACH0_DLEN_8814B(x) | BIT_DDMACH0_DLEN_8814B(v))
+
+/* 2 REG_DDMA_CH1SA_8814B */
+
+#define BIT_SHIFT_DDMACH1_SA_8814B 0
+#define BIT_MASK_DDMACH1_SA_8814B 0xffffffffL
+#define BIT_DDMACH1_SA_8814B(x) \
+ (((x) & BIT_MASK_DDMACH1_SA_8814B) << BIT_SHIFT_DDMACH1_SA_8814B)
+#define BITS_DDMACH1_SA_8814B \
+ (BIT_MASK_DDMACH1_SA_8814B << BIT_SHIFT_DDMACH1_SA_8814B)
+#define BIT_CLEAR_DDMACH1_SA_8814B(x) ((x) & (~BITS_DDMACH1_SA_8814B))
+#define BIT_GET_DDMACH1_SA_8814B(x) \
+ (((x) >> BIT_SHIFT_DDMACH1_SA_8814B) & BIT_MASK_DDMACH1_SA_8814B)
+#define BIT_SET_DDMACH1_SA_8814B(x, v) \
+ (BIT_CLEAR_DDMACH1_SA_8814B(x) | BIT_DDMACH1_SA_8814B(v))
+
+/* 2 REG_DDMA_CH1DA_8814B */
+
+#define BIT_SHIFT_DDMACH1_DA_8814B 0
+#define BIT_MASK_DDMACH1_DA_8814B 0xffffffffL
+#define BIT_DDMACH1_DA_8814B(x) \
+ (((x) & BIT_MASK_DDMACH1_DA_8814B) << BIT_SHIFT_DDMACH1_DA_8814B)
+#define BITS_DDMACH1_DA_8814B \
+ (BIT_MASK_DDMACH1_DA_8814B << BIT_SHIFT_DDMACH1_DA_8814B)
+#define BIT_CLEAR_DDMACH1_DA_8814B(x) ((x) & (~BITS_DDMACH1_DA_8814B))
+#define BIT_GET_DDMACH1_DA_8814B(x) \
+ (((x) >> BIT_SHIFT_DDMACH1_DA_8814B) & BIT_MASK_DDMACH1_DA_8814B)
+#define BIT_SET_DDMACH1_DA_8814B(x, v) \
+ (BIT_CLEAR_DDMACH1_DA_8814B(x) | BIT_DDMACH1_DA_8814B(v))
+
+/* 2 REG_DDMA_CH1CTRL_8814B */
+#define BIT_DDMACH1_OWN_8814B BIT(31)
+#define BIT_DDMACH1_IDMEM_ERR_8814B BIT(30)
+#define BIT_DDMACH1_CHKSUM_EN_8814B BIT(29)
+#define BIT_DDMACH1_DA_W_DISABLE_8814B BIT(28)
+#define BIT_DDMACH1_CHKSUM_STS_8814B BIT(27)
+#define BIT_DDMACH1_DDMA_MODE_8814B BIT(26)
+#define BIT_DDMACH1_RESET_CHKSUM_STS_8814B BIT(25)
+#define BIT_DDMACH1_CHKSUM_CONT_8814B BIT(24)
+
+#define BIT_SHIFT_DDMACH1_DLEN_8814B 0
+#define BIT_MASK_DDMACH1_DLEN_8814B 0x3ffff
+#define BIT_DDMACH1_DLEN_8814B(x) \
+ (((x) & BIT_MASK_DDMACH1_DLEN_8814B) << BIT_SHIFT_DDMACH1_DLEN_8814B)
+#define BITS_DDMACH1_DLEN_8814B \
+ (BIT_MASK_DDMACH1_DLEN_8814B << BIT_SHIFT_DDMACH1_DLEN_8814B)
+#define BIT_CLEAR_DDMACH1_DLEN_8814B(x) ((x) & (~BITS_DDMACH1_DLEN_8814B))
+#define BIT_GET_DDMACH1_DLEN_8814B(x) \
+ (((x) >> BIT_SHIFT_DDMACH1_DLEN_8814B) & BIT_MASK_DDMACH1_DLEN_8814B)
+#define BIT_SET_DDMACH1_DLEN_8814B(x, v) \
+ (BIT_CLEAR_DDMACH1_DLEN_8814B(x) | BIT_DDMACH1_DLEN_8814B(v))
+
+/* 2 REG_DDMA_CH2SA_8814B */
+
+#define BIT_SHIFT_DDMACH2_SA_8814B 0
+#define BIT_MASK_DDMACH2_SA_8814B 0xffffffffL
+#define BIT_DDMACH2_SA_8814B(x) \
+ (((x) & BIT_MASK_DDMACH2_SA_8814B) << BIT_SHIFT_DDMACH2_SA_8814B)
+#define BITS_DDMACH2_SA_8814B \
+ (BIT_MASK_DDMACH2_SA_8814B << BIT_SHIFT_DDMACH2_SA_8814B)
+#define BIT_CLEAR_DDMACH2_SA_8814B(x) ((x) & (~BITS_DDMACH2_SA_8814B))
+#define BIT_GET_DDMACH2_SA_8814B(x) \
+ (((x) >> BIT_SHIFT_DDMACH2_SA_8814B) & BIT_MASK_DDMACH2_SA_8814B)
+#define BIT_SET_DDMACH2_SA_8814B(x, v) \
+ (BIT_CLEAR_DDMACH2_SA_8814B(x) | BIT_DDMACH2_SA_8814B(v))
+
+/* 2 REG_DDMA_CH2DA_8814B */
+
+#define BIT_SHIFT_DDMACH2_DA_8814B 0
+#define BIT_MASK_DDMACH2_DA_8814B 0xffffffffL
+#define BIT_DDMACH2_DA_8814B(x) \
+ (((x) & BIT_MASK_DDMACH2_DA_8814B) << BIT_SHIFT_DDMACH2_DA_8814B)
+#define BITS_DDMACH2_DA_8814B \
+ (BIT_MASK_DDMACH2_DA_8814B << BIT_SHIFT_DDMACH2_DA_8814B)
+#define BIT_CLEAR_DDMACH2_DA_8814B(x) ((x) & (~BITS_DDMACH2_DA_8814B))
+#define BIT_GET_DDMACH2_DA_8814B(x) \
+ (((x) >> BIT_SHIFT_DDMACH2_DA_8814B) & BIT_MASK_DDMACH2_DA_8814B)
+#define BIT_SET_DDMACH2_DA_8814B(x, v) \
+ (BIT_CLEAR_DDMACH2_DA_8814B(x) | BIT_DDMACH2_DA_8814B(v))
+
+/* 2 REG_DDMA_CH2CTRL_8814B */
+#define BIT_DDMACH2_OWN_8814B BIT(31)
+#define BIT_DDMACH2_IDMEM_ERR_8814B BIT(30)
+#define BIT_DDMACH2_CHKSUM_EN_8814B BIT(29)
+#define BIT_DDMACH2_DA_W_DISABLE_8814B BIT(28)
+#define BIT_DDMACH2_CHKSUM_STS_8814B BIT(27)
+#define BIT_DDMACH2_DDMA_MODE_8814B BIT(26)
+#define BIT_DDMACH2_RESET_CHKSUM_STS_8814B BIT(25)
+#define BIT_DDMACH2_CHKSUM_CONT_8814B BIT(24)
+
+#define BIT_SHIFT_DDMACH2_DLEN_8814B 0
+#define BIT_MASK_DDMACH2_DLEN_8814B 0x3ffff
+#define BIT_DDMACH2_DLEN_8814B(x) \
+ (((x) & BIT_MASK_DDMACH2_DLEN_8814B) << BIT_SHIFT_DDMACH2_DLEN_8814B)
+#define BITS_DDMACH2_DLEN_8814B \
+ (BIT_MASK_DDMACH2_DLEN_8814B << BIT_SHIFT_DDMACH2_DLEN_8814B)
+#define BIT_CLEAR_DDMACH2_DLEN_8814B(x) ((x) & (~BITS_DDMACH2_DLEN_8814B))
+#define BIT_GET_DDMACH2_DLEN_8814B(x) \
+ (((x) >> BIT_SHIFT_DDMACH2_DLEN_8814B) & BIT_MASK_DDMACH2_DLEN_8814B)
+#define BIT_SET_DDMACH2_DLEN_8814B(x, v) \
+ (BIT_CLEAR_DDMACH2_DLEN_8814B(x) | BIT_DDMACH2_DLEN_8814B(v))
+
+/* 2 REG_DDMA_CH3SA_8814B */
+
+#define BIT_SHIFT_DDMACH3_SA_8814B 0
+#define BIT_MASK_DDMACH3_SA_8814B 0xffffffffL
+#define BIT_DDMACH3_SA_8814B(x) \
+ (((x) & BIT_MASK_DDMACH3_SA_8814B) << BIT_SHIFT_DDMACH3_SA_8814B)
+#define BITS_DDMACH3_SA_8814B \
+ (BIT_MASK_DDMACH3_SA_8814B << BIT_SHIFT_DDMACH3_SA_8814B)
+#define BIT_CLEAR_DDMACH3_SA_8814B(x) ((x) & (~BITS_DDMACH3_SA_8814B))
+#define BIT_GET_DDMACH3_SA_8814B(x) \
+ (((x) >> BIT_SHIFT_DDMACH3_SA_8814B) & BIT_MASK_DDMACH3_SA_8814B)
+#define BIT_SET_DDMACH3_SA_8814B(x, v) \
+ (BIT_CLEAR_DDMACH3_SA_8814B(x) | BIT_DDMACH3_SA_8814B(v))
+
+/* 2 REG_DDMA_CH3DA_8814B */
+
+#define BIT_SHIFT_DDMACH3_DA_8814B 0
+#define BIT_MASK_DDMACH3_DA_8814B 0xffffffffL
+#define BIT_DDMACH3_DA_8814B(x) \
+ (((x) & BIT_MASK_DDMACH3_DA_8814B) << BIT_SHIFT_DDMACH3_DA_8814B)
+#define BITS_DDMACH3_DA_8814B \
+ (BIT_MASK_DDMACH3_DA_8814B << BIT_SHIFT_DDMACH3_DA_8814B)
+#define BIT_CLEAR_DDMACH3_DA_8814B(x) ((x) & (~BITS_DDMACH3_DA_8814B))
+#define BIT_GET_DDMACH3_DA_8814B(x) \
+ (((x) >> BIT_SHIFT_DDMACH3_DA_8814B) & BIT_MASK_DDMACH3_DA_8814B)
+#define BIT_SET_DDMACH3_DA_8814B(x, v) \
+ (BIT_CLEAR_DDMACH3_DA_8814B(x) | BIT_DDMACH3_DA_8814B(v))
+
+/* 2 REG_DDMA_CH3CTRL_8814B */
+#define BIT_DDMACH3_OWN_8814B BIT(31)
+#define BIT_DDMACH3_IDMEM_ERR_8814B BIT(30)
+#define BIT_DDMACH3_CHKSUM_EN_8814B BIT(29)
+#define BIT_DDMACH3_DA_W_DISABLE_8814B BIT(28)
+#define BIT_DDMACH3_CHKSUM_STS_8814B BIT(27)
+#define BIT_DDMACH3_DDMA_MODE_8814B BIT(26)
+#define BIT_DDMACH3_RESET_CHKSUM_STS_8814B BIT(25)
+#define BIT_DDMACH3_CHKSUM_CONT_8814B BIT(24)
+
+#define BIT_SHIFT_DDMACH3_DLEN_8814B 0
+#define BIT_MASK_DDMACH3_DLEN_8814B 0x3ffff
+#define BIT_DDMACH3_DLEN_8814B(x) \
+ (((x) & BIT_MASK_DDMACH3_DLEN_8814B) << BIT_SHIFT_DDMACH3_DLEN_8814B)
+#define BITS_DDMACH3_DLEN_8814B \
+ (BIT_MASK_DDMACH3_DLEN_8814B << BIT_SHIFT_DDMACH3_DLEN_8814B)
+#define BIT_CLEAR_DDMACH3_DLEN_8814B(x) ((x) & (~BITS_DDMACH3_DLEN_8814B))
+#define BIT_GET_DDMACH3_DLEN_8814B(x) \
+ (((x) >> BIT_SHIFT_DDMACH3_DLEN_8814B) & BIT_MASK_DDMACH3_DLEN_8814B)
+#define BIT_SET_DDMACH3_DLEN_8814B(x, v) \
+ (BIT_CLEAR_DDMACH3_DLEN_8814B(x) | BIT_DDMACH3_DLEN_8814B(v))
+
+/* 2 REG_DDMA_CH4SA_8814B */
+
+#define BIT_SHIFT_DDMACH4_SA_8814B 0
+#define BIT_MASK_DDMACH4_SA_8814B 0xffffffffL
+#define BIT_DDMACH4_SA_8814B(x) \
+ (((x) & BIT_MASK_DDMACH4_SA_8814B) << BIT_SHIFT_DDMACH4_SA_8814B)
+#define BITS_DDMACH4_SA_8814B \
+ (BIT_MASK_DDMACH4_SA_8814B << BIT_SHIFT_DDMACH4_SA_8814B)
+#define BIT_CLEAR_DDMACH4_SA_8814B(x) ((x) & (~BITS_DDMACH4_SA_8814B))
+#define BIT_GET_DDMACH4_SA_8814B(x) \
+ (((x) >> BIT_SHIFT_DDMACH4_SA_8814B) & BIT_MASK_DDMACH4_SA_8814B)
+#define BIT_SET_DDMACH4_SA_8814B(x, v) \
+ (BIT_CLEAR_DDMACH4_SA_8814B(x) | BIT_DDMACH4_SA_8814B(v))
+
+/* 2 REG_DDMA_CH4DA_8814B */
+
+#define BIT_SHIFT_DDMACH4_DA_8814B 0
+#define BIT_MASK_DDMACH4_DA_8814B 0xffffffffL
+#define BIT_DDMACH4_DA_8814B(x) \
+ (((x) & BIT_MASK_DDMACH4_DA_8814B) << BIT_SHIFT_DDMACH4_DA_8814B)
+#define BITS_DDMACH4_DA_8814B \
+ (BIT_MASK_DDMACH4_DA_8814B << BIT_SHIFT_DDMACH4_DA_8814B)
+#define BIT_CLEAR_DDMACH4_DA_8814B(x) ((x) & (~BITS_DDMACH4_DA_8814B))
+#define BIT_GET_DDMACH4_DA_8814B(x) \
+ (((x) >> BIT_SHIFT_DDMACH4_DA_8814B) & BIT_MASK_DDMACH4_DA_8814B)
+#define BIT_SET_DDMACH4_DA_8814B(x, v) \
+ (BIT_CLEAR_DDMACH4_DA_8814B(x) | BIT_DDMACH4_DA_8814B(v))
+
+/* 2 REG_DDMA_CH4CTRL_8814B */
+#define BIT_DDMACH4_OWN_8814B BIT(31)
+#define BIT_DDMACH4_IDMEM_ERR_8814B BIT(30)
+#define BIT_DDMACH4_CHKSUM_EN_8814B BIT(29)
+#define BIT_DDMACH4_DA_W_DISABLE_8814B BIT(28)
+#define BIT_DDMACH4_CHKSUM_STS_8814B BIT(27)
+#define BIT_DDMACH4_DDMA_MODE_8814B BIT(26)
+#define BIT_DDMACH4_RESET_CHKSUM_STS_8814B BIT(25)
+#define BIT_DDMACH4_CHKSUM_CONT_8814B BIT(24)
+
+#define BIT_SHIFT_DDMACH4_DLEN_8814B 0
+#define BIT_MASK_DDMACH4_DLEN_8814B 0x3ffff
+#define BIT_DDMACH4_DLEN_8814B(x) \
+ (((x) & BIT_MASK_DDMACH4_DLEN_8814B) << BIT_SHIFT_DDMACH4_DLEN_8814B)
+#define BITS_DDMACH4_DLEN_8814B \
+ (BIT_MASK_DDMACH4_DLEN_8814B << BIT_SHIFT_DDMACH4_DLEN_8814B)
+#define BIT_CLEAR_DDMACH4_DLEN_8814B(x) ((x) & (~BITS_DDMACH4_DLEN_8814B))
+#define BIT_GET_DDMACH4_DLEN_8814B(x) \
+ (((x) >> BIT_SHIFT_DDMACH4_DLEN_8814B) & BIT_MASK_DDMACH4_DLEN_8814B)
+#define BIT_SET_DDMACH4_DLEN_8814B(x, v) \
+ (BIT_CLEAR_DDMACH4_DLEN_8814B(x) | BIT_DDMACH4_DLEN_8814B(v))
+
+/* 2 REG_DDMA_CH5SA_8814B */
+
+#define BIT_SHIFT_DDMACH5_SA_8814B 0
+#define BIT_MASK_DDMACH5_SA_8814B 0xffffffffL
+#define BIT_DDMACH5_SA_8814B(x) \
+ (((x) & BIT_MASK_DDMACH5_SA_8814B) << BIT_SHIFT_DDMACH5_SA_8814B)
+#define BITS_DDMACH5_SA_8814B \
+ (BIT_MASK_DDMACH5_SA_8814B << BIT_SHIFT_DDMACH5_SA_8814B)
+#define BIT_CLEAR_DDMACH5_SA_8814B(x) ((x) & (~BITS_DDMACH5_SA_8814B))
+#define BIT_GET_DDMACH5_SA_8814B(x) \
+ (((x) >> BIT_SHIFT_DDMACH5_SA_8814B) & BIT_MASK_DDMACH5_SA_8814B)
+#define BIT_SET_DDMACH5_SA_8814B(x, v) \
+ (BIT_CLEAR_DDMACH5_SA_8814B(x) | BIT_DDMACH5_SA_8814B(v))
+
+/* 2 REG_DDMA_CH5DA_8814B */
+
+#define BIT_SHIFT_DDMACH5_DA_8814B 0
+#define BIT_MASK_DDMACH5_DA_8814B 0xffffffffL
+#define BIT_DDMACH5_DA_8814B(x) \
+ (((x) & BIT_MASK_DDMACH5_DA_8814B) << BIT_SHIFT_DDMACH5_DA_8814B)
+#define BITS_DDMACH5_DA_8814B \
+ (BIT_MASK_DDMACH5_DA_8814B << BIT_SHIFT_DDMACH5_DA_8814B)
+#define BIT_CLEAR_DDMACH5_DA_8814B(x) ((x) & (~BITS_DDMACH5_DA_8814B))
+#define BIT_GET_DDMACH5_DA_8814B(x) \
+ (((x) >> BIT_SHIFT_DDMACH5_DA_8814B) & BIT_MASK_DDMACH5_DA_8814B)
+#define BIT_SET_DDMACH5_DA_8814B(x, v) \
+ (BIT_CLEAR_DDMACH5_DA_8814B(x) | BIT_DDMACH5_DA_8814B(v))
+
+/* 2 REG_DDMA_CH5CTRL_8814B */
+#define BIT_DDMACH5_OWN_8814B BIT(31)
+#define BIT_DDMACH5_IDMEM_ERR_8814B BIT(30)
+#define BIT_DDMACH5_CHKSUM_EN_8814B BIT(29)
+#define BIT_DDMACH5_DA_W_DISABLE_8814B BIT(28)
+#define BIT_DDMACH5_CHKSUM_STS_8814B BIT(27)
+#define BIT_DDMACH5_DDMA_MODE_8814B BIT(26)
+#define BIT_DDMACH5_RESET_CHKSUM_STS_8814B BIT(25)
+#define BIT_DDMACH5_CHKSUM_CONT_8814B BIT(24)
+
+#define BIT_SHIFT_DDMACH5_DLEN_8814B 0
+#define BIT_MASK_DDMACH5_DLEN_8814B 0x3ffff
+#define BIT_DDMACH5_DLEN_8814B(x) \
+ (((x) & BIT_MASK_DDMACH5_DLEN_8814B) << BIT_SHIFT_DDMACH5_DLEN_8814B)
+#define BITS_DDMACH5_DLEN_8814B \
+ (BIT_MASK_DDMACH5_DLEN_8814B << BIT_SHIFT_DDMACH5_DLEN_8814B)
+#define BIT_CLEAR_DDMACH5_DLEN_8814B(x) ((x) & (~BITS_DDMACH5_DLEN_8814B))
+#define BIT_GET_DDMACH5_DLEN_8814B(x) \
+ (((x) >> BIT_SHIFT_DDMACH5_DLEN_8814B) & BIT_MASK_DDMACH5_DLEN_8814B)
+#define BIT_SET_DDMACH5_DLEN_8814B(x, v) \
+ (BIT_CLEAR_DDMACH5_DLEN_8814B(x) | BIT_DDMACH5_DLEN_8814B(v))
+
+/* 2 REG_DDMA_INT_MSK_8814B */
+#define BIT_DDMACH5_MSK_8814B BIT(5)
+#define BIT_DDMACH4_MSK_8814B BIT(4)
+#define BIT_DDMACH3_MSK_8814B BIT(3)
+#define BIT_DDMACH2_MSK_8814B BIT(2)
+#define BIT_DDMACH1_MSK_8814B BIT(1)
+#define BIT_DDMACH0_MSK_8814B BIT(0)
+
+/* 2 REG_DDMA_CHSTATUS_8814B */
+#define BIT_DDMACH5_BUSY_8814B BIT(5)
+#define BIT_DDMACH4_BUSY_8814B BIT(4)
+#define BIT_DDMACH3_BUSY_8814B BIT(3)
+#define BIT_DDMACH2_BUSY_8814B BIT(2)
+#define BIT_DDMACH1_BUSY_8814B BIT(1)
+#define BIT_DDMACH0_BUSY_8814B BIT(0)
+
+/* 2 REG_DDMA_CHKSUM_8814B */
+
+#define BIT_SHIFT_IDDMA0_CHKSUM_8814B 0
+#define BIT_MASK_IDDMA0_CHKSUM_8814B 0xffff
+#define BIT_IDDMA0_CHKSUM_8814B(x) \
+ (((x) & BIT_MASK_IDDMA0_CHKSUM_8814B) << BIT_SHIFT_IDDMA0_CHKSUM_8814B)
+#define BITS_IDDMA0_CHKSUM_8814B \
+ (BIT_MASK_IDDMA0_CHKSUM_8814B << BIT_SHIFT_IDDMA0_CHKSUM_8814B)
+#define BIT_CLEAR_IDDMA0_CHKSUM_8814B(x) ((x) & (~BITS_IDDMA0_CHKSUM_8814B))
+#define BIT_GET_IDDMA0_CHKSUM_8814B(x) \
+ (((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8814B) & BIT_MASK_IDDMA0_CHKSUM_8814B)
+#define BIT_SET_IDDMA0_CHKSUM_8814B(x, v) \
+ (BIT_CLEAR_IDDMA0_CHKSUM_8814B(x) | BIT_IDDMA0_CHKSUM_8814B(v))
+
+/* 2 REG_DDMA_MONITOR_8814B */
+#define BIT_IDDMA0_PERMU_UNDERFLOW_8814B BIT(14)
+#define BIT_IDDMA0_FIFO_UNDERFLOW_8814B BIT(13)
+#define BIT_IDDMA0_FIFO_OVERFLOW_8814B BIT(12)
+#define BIT_CH5_ERR_8814B BIT(5)
+#define BIT_CH4_ERR_8814B BIT(4)
+#define BIT_CH3_ERR_8814B BIT(3)
+#define BIT_CH2_ERR_8814B BIT(2)
+#define BIT_CH1_ERR_8814B BIT(1)
+#define BIT_CH0_ERR_8814B BIT(0)
+
+/* 2 REG_DMA_RQPN_INFO_0_8814B */
+
+#define BIT_SHIFT_CH0_AVAL_PG_8814B 16
+#define BIT_MASK_CH0_AVAL_PG_8814B 0xfff
+#define BIT_CH0_AVAL_PG_8814B(x) \
+ (((x) & BIT_MASK_CH0_AVAL_PG_8814B) << BIT_SHIFT_CH0_AVAL_PG_8814B)
+#define BITS_CH0_AVAL_PG_8814B \
+ (BIT_MASK_CH0_AVAL_PG_8814B << BIT_SHIFT_CH0_AVAL_PG_8814B)
+#define BIT_CLEAR_CH0_AVAL_PG_8814B(x) ((x) & (~BITS_CH0_AVAL_PG_8814B))
+#define BIT_GET_CH0_AVAL_PG_8814B(x) \
+ (((x) >> BIT_SHIFT_CH0_AVAL_PG_8814B) & BIT_MASK_CH0_AVAL_PG_8814B)
+#define BIT_SET_CH0_AVAL_PG_8814B(x, v) \
+ (BIT_CLEAR_CH0_AVAL_PG_8814B(x) | BIT_CH0_AVAL_PG_8814B(v))
+
+#define BIT_SHIFT_CH0_RSVD_PG_8814B 0
+#define BIT_MASK_CH0_RSVD_PG_8814B 0xfff
+#define BIT_CH0_RSVD_PG_8814B(x) \
+ (((x) & BIT_MASK_CH0_RSVD_PG_8814B) << BIT_SHIFT_CH0_RSVD_PG_8814B)
+#define BITS_CH0_RSVD_PG_8814B \
+ (BIT_MASK_CH0_RSVD_PG_8814B << BIT_SHIFT_CH0_RSVD_PG_8814B)
+#define BIT_CLEAR_CH0_RSVD_PG_8814B(x) ((x) & (~BITS_CH0_RSVD_PG_8814B))
+#define BIT_GET_CH0_RSVD_PG_8814B(x) \
+ (((x) >> BIT_SHIFT_CH0_RSVD_PG_8814B) & BIT_MASK_CH0_RSVD_PG_8814B)
+#define BIT_SET_CH0_RSVD_PG_8814B(x, v) \
+ (BIT_CLEAR_CH0_RSVD_PG_8814B(x) | BIT_CH0_RSVD_PG_8814B(v))
+
+/* 2 REG_DMA_RQPN_INFO_1_8814B */
+
+#define BIT_SHIFT_CH1_AVAL_PG_8814B 16
+#define BIT_MASK_CH1_AVAL_PG_8814B 0xfff
+#define BIT_CH1_AVAL_PG_8814B(x) \
+ (((x) & BIT_MASK_CH1_AVAL_PG_8814B) << BIT_SHIFT_CH1_AVAL_PG_8814B)
+#define BITS_CH1_AVAL_PG_8814B \
+ (BIT_MASK_CH1_AVAL_PG_8814B << BIT_SHIFT_CH1_AVAL_PG_8814B)
+#define BIT_CLEAR_CH1_AVAL_PG_8814B(x) ((x) & (~BITS_CH1_AVAL_PG_8814B))
+#define BIT_GET_CH1_AVAL_PG_8814B(x) \
+ (((x) >> BIT_SHIFT_CH1_AVAL_PG_8814B) & BIT_MASK_CH1_AVAL_PG_8814B)
+#define BIT_SET_CH1_AVAL_PG_8814B(x, v) \
+ (BIT_CLEAR_CH1_AVAL_PG_8814B(x) | BIT_CH1_AVAL_PG_8814B(v))
+
+#define BIT_SHIFT_CH1_RSVD_PG_8814B 0
+#define BIT_MASK_CH1_RSVD_PG_8814B 0xfff
+#define BIT_CH1_RSVD_PG_8814B(x) \
+ (((x) & BIT_MASK_CH1_RSVD_PG_8814B) << BIT_SHIFT_CH1_RSVD_PG_8814B)
+#define BITS_CH1_RSVD_PG_8814B \
+ (BIT_MASK_CH1_RSVD_PG_8814B << BIT_SHIFT_CH1_RSVD_PG_8814B)
+#define BIT_CLEAR_CH1_RSVD_PG_8814B(x) ((x) & (~BITS_CH1_RSVD_PG_8814B))
+#define BIT_GET_CH1_RSVD_PG_8814B(x) \
+ (((x) >> BIT_SHIFT_CH1_RSVD_PG_8814B) & BIT_MASK_CH1_RSVD_PG_8814B)
+#define BIT_SET_CH1_RSVD_PG_8814B(x, v) \
+ (BIT_CLEAR_CH1_RSVD_PG_8814B(x) | BIT_CH1_RSVD_PG_8814B(v))
+
+/* 2 REG_DMA_RQPN_INFO_2_8814B */
+
+#define BIT_SHIFT_CH2_AVAL_PG_8814B 16
+#define BIT_MASK_CH2_AVAL_PG_8814B 0xfff
+#define BIT_CH2_AVAL_PG_8814B(x) \
+ (((x) & BIT_MASK_CH2_AVAL_PG_8814B) << BIT_SHIFT_CH2_AVAL_PG_8814B)
+#define BITS_CH2_AVAL_PG_8814B \
+ (BIT_MASK_CH2_AVAL_PG_8814B << BIT_SHIFT_CH2_AVAL_PG_8814B)
+#define BIT_CLEAR_CH2_AVAL_PG_8814B(x) ((x) & (~BITS_CH2_AVAL_PG_8814B))
+#define BIT_GET_CH2_AVAL_PG_8814B(x) \
+ (((x) >> BIT_SHIFT_CH2_AVAL_PG_8814B) & BIT_MASK_CH2_AVAL_PG_8814B)
+#define BIT_SET_CH2_AVAL_PG_8814B(x, v) \
+ (BIT_CLEAR_CH2_AVAL_PG_8814B(x) | BIT_CH2_AVAL_PG_8814B(v))
+
+#define BIT_SHIFT_CH2_RSVD_PG_8814B 0
+#define BIT_MASK_CH2_RSVD_PG_8814B 0xfff
+#define BIT_CH2_RSVD_PG_8814B(x) \
+ (((x) & BIT_MASK_CH2_RSVD_PG_8814B) << BIT_SHIFT_CH2_RSVD_PG_8814B)
+#define BITS_CH2_RSVD_PG_8814B \
+ (BIT_MASK_CH2_RSVD_PG_8814B << BIT_SHIFT_CH2_RSVD_PG_8814B)
+#define BIT_CLEAR_CH2_RSVD_PG_8814B(x) ((x) & (~BITS_CH2_RSVD_PG_8814B))
+#define BIT_GET_CH2_RSVD_PG_8814B(x) \
+ (((x) >> BIT_SHIFT_CH2_RSVD_PG_8814B) & BIT_MASK_CH2_RSVD_PG_8814B)
+#define BIT_SET_CH2_RSVD_PG_8814B(x, v) \
+ (BIT_CLEAR_CH2_RSVD_PG_8814B(x) | BIT_CH2_RSVD_PG_8814B(v))
+
+/* 2 REG_DMA_RQPN_INFO_3_8814B */
+
+#define BIT_SHIFT_CH3_AVAL_PG_8814B 16
+#define BIT_MASK_CH3_AVAL_PG_8814B 0xfff
+#define BIT_CH3_AVAL_PG_8814B(x) \
+ (((x) & BIT_MASK_CH3_AVAL_PG_8814B) << BIT_SHIFT_CH3_AVAL_PG_8814B)
+#define BITS_CH3_AVAL_PG_8814B \
+ (BIT_MASK_CH3_AVAL_PG_8814B << BIT_SHIFT_CH3_AVAL_PG_8814B)
+#define BIT_CLEAR_CH3_AVAL_PG_8814B(x) ((x) & (~BITS_CH3_AVAL_PG_8814B))
+#define BIT_GET_CH3_AVAL_PG_8814B(x) \
+ (((x) >> BIT_SHIFT_CH3_AVAL_PG_8814B) & BIT_MASK_CH3_AVAL_PG_8814B)
+#define BIT_SET_CH3_AVAL_PG_8814B(x, v) \
+ (BIT_CLEAR_CH3_AVAL_PG_8814B(x) | BIT_CH3_AVAL_PG_8814B(v))
+
+#define BIT_SHIFT_CH3_RSVD_PG_8814B 0
+#define BIT_MASK_CH3_RSVD_PG_8814B 0xfff
+#define BIT_CH3_RSVD_PG_8814B(x) \
+ (((x) & BIT_MASK_CH3_RSVD_PG_8814B) << BIT_SHIFT_CH3_RSVD_PG_8814B)
+#define BITS_CH3_RSVD_PG_8814B \
+ (BIT_MASK_CH3_RSVD_PG_8814B << BIT_SHIFT_CH3_RSVD_PG_8814B)
+#define BIT_CLEAR_CH3_RSVD_PG_8814B(x) ((x) & (~BITS_CH3_RSVD_PG_8814B))
+#define BIT_GET_CH3_RSVD_PG_8814B(x) \
+ (((x) >> BIT_SHIFT_CH3_RSVD_PG_8814B) & BIT_MASK_CH3_RSVD_PG_8814B)
+#define BIT_SET_CH3_RSVD_PG_8814B(x, v) \
+ (BIT_CLEAR_CH3_RSVD_PG_8814B(x) | BIT_CH3_RSVD_PG_8814B(v))
+
+/* 2 REG_DMA_RQPN_INFO_4_8814B */
+
+#define BIT_SHIFT_CH4_AVAL_PG_8814B 16
+#define BIT_MASK_CH4_AVAL_PG_8814B 0xfff
+#define BIT_CH4_AVAL_PG_8814B(x) \
+ (((x) & BIT_MASK_CH4_AVAL_PG_8814B) << BIT_SHIFT_CH4_AVAL_PG_8814B)
+#define BITS_CH4_AVAL_PG_8814B \
+ (BIT_MASK_CH4_AVAL_PG_8814B << BIT_SHIFT_CH4_AVAL_PG_8814B)
+#define BIT_CLEAR_CH4_AVAL_PG_8814B(x) ((x) & (~BITS_CH4_AVAL_PG_8814B))
+#define BIT_GET_CH4_AVAL_PG_8814B(x) \
+ (((x) >> BIT_SHIFT_CH4_AVAL_PG_8814B) & BIT_MASK_CH4_AVAL_PG_8814B)
+#define BIT_SET_CH4_AVAL_PG_8814B(x, v) \
+ (BIT_CLEAR_CH4_AVAL_PG_8814B(x) | BIT_CH4_AVAL_PG_8814B(v))
+
+#define BIT_SHIFT_CH4_RSVD_PG_8814B 0
+#define BIT_MASK_CH4_RSVD_PG_8814B 0xfff
+#define BIT_CH4_RSVD_PG_8814B(x) \
+ (((x) & BIT_MASK_CH4_RSVD_PG_8814B) << BIT_SHIFT_CH4_RSVD_PG_8814B)
+#define BITS_CH4_RSVD_PG_8814B \
+ (BIT_MASK_CH4_RSVD_PG_8814B << BIT_SHIFT_CH4_RSVD_PG_8814B)
+#define BIT_CLEAR_CH4_RSVD_PG_8814B(x) ((x) & (~BITS_CH4_RSVD_PG_8814B))
+#define BIT_GET_CH4_RSVD_PG_8814B(x) \
+ (((x) >> BIT_SHIFT_CH4_RSVD_PG_8814B) & BIT_MASK_CH4_RSVD_PG_8814B)
+#define BIT_SET_CH4_RSVD_PG_8814B(x, v) \
+ (BIT_CLEAR_CH4_RSVD_PG_8814B(x) | BIT_CH4_RSVD_PG_8814B(v))
+
+/* 2 REG_DMA_RQPN_INFO_5_8814B */
+
+#define BIT_SHIFT_CH5_AVAL_PG_8814B 16
+#define BIT_MASK_CH5_AVAL_PG_8814B 0xfff
+#define BIT_CH5_AVAL_PG_8814B(x) \
+ (((x) & BIT_MASK_CH5_AVAL_PG_8814B) << BIT_SHIFT_CH5_AVAL_PG_8814B)
+#define BITS_CH5_AVAL_PG_8814B \
+ (BIT_MASK_CH5_AVAL_PG_8814B << BIT_SHIFT_CH5_AVAL_PG_8814B)
+#define BIT_CLEAR_CH5_AVAL_PG_8814B(x) ((x) & (~BITS_CH5_AVAL_PG_8814B))
+#define BIT_GET_CH5_AVAL_PG_8814B(x) \
+ (((x) >> BIT_SHIFT_CH5_AVAL_PG_8814B) & BIT_MASK_CH5_AVAL_PG_8814B)
+#define BIT_SET_CH5_AVAL_PG_8814B(x, v) \
+ (BIT_CLEAR_CH5_AVAL_PG_8814B(x) | BIT_CH5_AVAL_PG_8814B(v))
+
+#define BIT_SHIFT_CH5_RSVD_PG_8814B 0
+#define BIT_MASK_CH5_RSVD_PG_8814B 0xfff
+#define BIT_CH5_RSVD_PG_8814B(x) \
+ (((x) & BIT_MASK_CH5_RSVD_PG_8814B) << BIT_SHIFT_CH5_RSVD_PG_8814B)
+#define BITS_CH5_RSVD_PG_8814B \
+ (BIT_MASK_CH5_RSVD_PG_8814B << BIT_SHIFT_CH5_RSVD_PG_8814B)
+#define BIT_CLEAR_CH5_RSVD_PG_8814B(x) ((x) & (~BITS_CH5_RSVD_PG_8814B))
+#define BIT_GET_CH5_RSVD_PG_8814B(x) \
+ (((x) >> BIT_SHIFT_CH5_RSVD_PG_8814B) & BIT_MASK_CH5_RSVD_PG_8814B)
+#define BIT_SET_CH5_RSVD_PG_8814B(x, v) \
+ (BIT_CLEAR_CH5_RSVD_PG_8814B(x) | BIT_CH5_RSVD_PG_8814B(v))
+
+/* 2 REG_DMA_RQPN_INFO_6_8814B */
+
+#define BIT_SHIFT_CH6_AVAL_PG_8814B 16
+#define BIT_MASK_CH6_AVAL_PG_8814B 0xfff
+#define BIT_CH6_AVAL_PG_8814B(x) \
+ (((x) & BIT_MASK_CH6_AVAL_PG_8814B) << BIT_SHIFT_CH6_AVAL_PG_8814B)
+#define BITS_CH6_AVAL_PG_8814B \
+ (BIT_MASK_CH6_AVAL_PG_8814B << BIT_SHIFT_CH6_AVAL_PG_8814B)
+#define BIT_CLEAR_CH6_AVAL_PG_8814B(x) ((x) & (~BITS_CH6_AVAL_PG_8814B))
+#define BIT_GET_CH6_AVAL_PG_8814B(x) \
+ (((x) >> BIT_SHIFT_CH6_AVAL_PG_8814B) & BIT_MASK_CH6_AVAL_PG_8814B)
+#define BIT_SET_CH6_AVAL_PG_8814B(x, v) \
+ (BIT_CLEAR_CH6_AVAL_PG_8814B(x) | BIT_CH6_AVAL_PG_8814B(v))
+
+#define BIT_SHIFT_CH6_RSVD_PG_8814B 0
+#define BIT_MASK_CH6_RSVD_PG_8814B 0xfff
+#define BIT_CH6_RSVD_PG_8814B(x) \
+ (((x) & BIT_MASK_CH6_RSVD_PG_8814B) << BIT_SHIFT_CH6_RSVD_PG_8814B)
+#define BITS_CH6_RSVD_PG_8814B \
+ (BIT_MASK_CH6_RSVD_PG_8814B << BIT_SHIFT_CH6_RSVD_PG_8814B)
+#define BIT_CLEAR_CH6_RSVD_PG_8814B(x) ((x) & (~BITS_CH6_RSVD_PG_8814B))
+#define BIT_GET_CH6_RSVD_PG_8814B(x) \
+ (((x) >> BIT_SHIFT_CH6_RSVD_PG_8814B) & BIT_MASK_CH6_RSVD_PG_8814B)
+#define BIT_SET_CH6_RSVD_PG_8814B(x, v) \
+ (BIT_CLEAR_CH6_RSVD_PG_8814B(x) | BIT_CH6_RSVD_PG_8814B(v))
+
+/* 2 REG_DMA_RQPN_INFO_7_8814B */
+
+#define BIT_SHIFT_CH7_AVAL_PG_8814B 16
+#define BIT_MASK_CH7_AVAL_PG_8814B 0xfff
+#define BIT_CH7_AVAL_PG_8814B(x) \
+ (((x) & BIT_MASK_CH7_AVAL_PG_8814B) << BIT_SHIFT_CH7_AVAL_PG_8814B)
+#define BITS_CH7_AVAL_PG_8814B \
+ (BIT_MASK_CH7_AVAL_PG_8814B << BIT_SHIFT_CH7_AVAL_PG_8814B)
+#define BIT_CLEAR_CH7_AVAL_PG_8814B(x) ((x) & (~BITS_CH7_AVAL_PG_8814B))
+#define BIT_GET_CH7_AVAL_PG_8814B(x) \
+ (((x) >> BIT_SHIFT_CH7_AVAL_PG_8814B) & BIT_MASK_CH7_AVAL_PG_8814B)
+#define BIT_SET_CH7_AVAL_PG_8814B(x, v) \
+ (BIT_CLEAR_CH7_AVAL_PG_8814B(x) | BIT_CH7_AVAL_PG_8814B(v))
+
+#define BIT_SHIFT_CH7_RSVD_PG_8814B 0
+#define BIT_MASK_CH7_RSVD_PG_8814B 0xfff
+#define BIT_CH7_RSVD_PG_8814B(x) \
+ (((x) & BIT_MASK_CH7_RSVD_PG_8814B) << BIT_SHIFT_CH7_RSVD_PG_8814B)
+#define BITS_CH7_RSVD_PG_8814B \
+ (BIT_MASK_CH7_RSVD_PG_8814B << BIT_SHIFT_CH7_RSVD_PG_8814B)
+#define BIT_CLEAR_CH7_RSVD_PG_8814B(x) ((x) & (~BITS_CH7_RSVD_PG_8814B))
+#define BIT_GET_CH7_RSVD_PG_8814B(x) \
+ (((x) >> BIT_SHIFT_CH7_RSVD_PG_8814B) & BIT_MASK_CH7_RSVD_PG_8814B)
+#define BIT_SET_CH7_RSVD_PG_8814B(x, v) \
+ (BIT_CLEAR_CH7_RSVD_PG_8814B(x) | BIT_CH7_RSVD_PG_8814B(v))
+
+/* 2 REG_DMA_RQPN_INFO_8_8814B */
+
+#define BIT_SHIFT_CH8_AVAL_PG_8814B 16
+#define BIT_MASK_CH8_AVAL_PG_8814B 0xfff
+#define BIT_CH8_AVAL_PG_8814B(x) \
+ (((x) & BIT_MASK_CH8_AVAL_PG_8814B) << BIT_SHIFT_CH8_AVAL_PG_8814B)
+#define BITS_CH8_AVAL_PG_8814B \
+ (BIT_MASK_CH8_AVAL_PG_8814B << BIT_SHIFT_CH8_AVAL_PG_8814B)
+#define BIT_CLEAR_CH8_AVAL_PG_8814B(x) ((x) & (~BITS_CH8_AVAL_PG_8814B))
+#define BIT_GET_CH8_AVAL_PG_8814B(x) \
+ (((x) >> BIT_SHIFT_CH8_AVAL_PG_8814B) & BIT_MASK_CH8_AVAL_PG_8814B)
+#define BIT_SET_CH8_AVAL_PG_8814B(x, v) \
+ (BIT_CLEAR_CH8_AVAL_PG_8814B(x) | BIT_CH8_AVAL_PG_8814B(v))
+
+#define BIT_SHIFT_CH8_RSVD_PG_8814B 0
+#define BIT_MASK_CH8_RSVD_PG_8814B 0xfff
+#define BIT_CH8_RSVD_PG_8814B(x) \
+ (((x) & BIT_MASK_CH8_RSVD_PG_8814B) << BIT_SHIFT_CH8_RSVD_PG_8814B)
+#define BITS_CH8_RSVD_PG_8814B \
+ (BIT_MASK_CH8_RSVD_PG_8814B << BIT_SHIFT_CH8_RSVD_PG_8814B)
+#define BIT_CLEAR_CH8_RSVD_PG_8814B(x) ((x) & (~BITS_CH8_RSVD_PG_8814B))
+#define BIT_GET_CH8_RSVD_PG_8814B(x) \
+ (((x) >> BIT_SHIFT_CH8_RSVD_PG_8814B) & BIT_MASK_CH8_RSVD_PG_8814B)
+#define BIT_SET_CH8_RSVD_PG_8814B(x, v) \
+ (BIT_CLEAR_CH8_RSVD_PG_8814B(x) | BIT_CH8_RSVD_PG_8814B(v))
+
+/* 2 REG_DMA_RQPN_INFO_9_8814B */
+
+#define BIT_SHIFT_CH9_AVAL_PG_8814B 16
+#define BIT_MASK_CH9_AVAL_PG_8814B 0xfff
+#define BIT_CH9_AVAL_PG_8814B(x) \
+ (((x) & BIT_MASK_CH9_AVAL_PG_8814B) << BIT_SHIFT_CH9_AVAL_PG_8814B)
+#define BITS_CH9_AVAL_PG_8814B \
+ (BIT_MASK_CH9_AVAL_PG_8814B << BIT_SHIFT_CH9_AVAL_PG_8814B)
+#define BIT_CLEAR_CH9_AVAL_PG_8814B(x) ((x) & (~BITS_CH9_AVAL_PG_8814B))
+#define BIT_GET_CH9_AVAL_PG_8814B(x) \
+ (((x) >> BIT_SHIFT_CH9_AVAL_PG_8814B) & BIT_MASK_CH9_AVAL_PG_8814B)
+#define BIT_SET_CH9_AVAL_PG_8814B(x, v) \
+ (BIT_CLEAR_CH9_AVAL_PG_8814B(x) | BIT_CH9_AVAL_PG_8814B(v))
+
+#define BIT_SHIFT_CH9_RSVD_PG_8814B 0
+#define BIT_MASK_CH9_RSVD_PG_8814B 0xfff
+#define BIT_CH9_RSVD_PG_8814B(x) \
+ (((x) & BIT_MASK_CH9_RSVD_PG_8814B) << BIT_SHIFT_CH9_RSVD_PG_8814B)
+#define BITS_CH9_RSVD_PG_8814B \
+ (BIT_MASK_CH9_RSVD_PG_8814B << BIT_SHIFT_CH9_RSVD_PG_8814B)
+#define BIT_CLEAR_CH9_RSVD_PG_8814B(x) ((x) & (~BITS_CH9_RSVD_PG_8814B))
+#define BIT_GET_CH9_RSVD_PG_8814B(x) \
+ (((x) >> BIT_SHIFT_CH9_RSVD_PG_8814B) & BIT_MASK_CH9_RSVD_PG_8814B)
+#define BIT_SET_CH9_RSVD_PG_8814B(x, v) \
+ (BIT_CLEAR_CH9_RSVD_PG_8814B(x) | BIT_CH9_RSVD_PG_8814B(v))
+
+/* 2 REG_DMA_RQPN_INFO_10_8814B */
+
+#define BIT_SHIFT_CH10_AVAL_PG_8814B 16
+#define BIT_MASK_CH10_AVAL_PG_8814B 0xfff
+#define BIT_CH10_AVAL_PG_8814B(x) \
+ (((x) & BIT_MASK_CH10_AVAL_PG_8814B) << BIT_SHIFT_CH10_AVAL_PG_8814B)
+#define BITS_CH10_AVAL_PG_8814B \
+ (BIT_MASK_CH10_AVAL_PG_8814B << BIT_SHIFT_CH10_AVAL_PG_8814B)
+#define BIT_CLEAR_CH10_AVAL_PG_8814B(x) ((x) & (~BITS_CH10_AVAL_PG_8814B))
+#define BIT_GET_CH10_AVAL_PG_8814B(x) \
+ (((x) >> BIT_SHIFT_CH10_AVAL_PG_8814B) & BIT_MASK_CH10_AVAL_PG_8814B)
+#define BIT_SET_CH10_AVAL_PG_8814B(x, v) \
+ (BIT_CLEAR_CH10_AVAL_PG_8814B(x) | BIT_CH10_AVAL_PG_8814B(v))
+
+#define BIT_SHIFT_CH10_RSVD_PG_8814B 0
+#define BIT_MASK_CH10_RSVD_PG_8814B 0xfff
+#define BIT_CH10_RSVD_PG_8814B(x) \
+ (((x) & BIT_MASK_CH10_RSVD_PG_8814B) << BIT_SHIFT_CH10_RSVD_PG_8814B)
+#define BITS_CH10_RSVD_PG_8814B \
+ (BIT_MASK_CH10_RSVD_PG_8814B << BIT_SHIFT_CH10_RSVD_PG_8814B)
+#define BIT_CLEAR_CH10_RSVD_PG_8814B(x) ((x) & (~BITS_CH10_RSVD_PG_8814B))
+#define BIT_GET_CH10_RSVD_PG_8814B(x) \
+ (((x) >> BIT_SHIFT_CH10_RSVD_PG_8814B) & BIT_MASK_CH10_RSVD_PG_8814B)
+#define BIT_SET_CH10_RSVD_PG_8814B(x, v) \
+ (BIT_CLEAR_CH10_RSVD_PG_8814B(x) | BIT_CH10_RSVD_PG_8814B(v))
+
+/* 2 REG_DMA_RQPN_INFO_11_8814B */
+
+#define BIT_SHIFT_CH11_AVAL_PG_8814B 16
+#define BIT_MASK_CH11_AVAL_PG_8814B 0xfff
+#define BIT_CH11_AVAL_PG_8814B(x) \
+ (((x) & BIT_MASK_CH11_AVAL_PG_8814B) << BIT_SHIFT_CH11_AVAL_PG_8814B)
+#define BITS_CH11_AVAL_PG_8814B \
+ (BIT_MASK_CH11_AVAL_PG_8814B << BIT_SHIFT_CH11_AVAL_PG_8814B)
+#define BIT_CLEAR_CH11_AVAL_PG_8814B(x) ((x) & (~BITS_CH11_AVAL_PG_8814B))
+#define BIT_GET_CH11_AVAL_PG_8814B(x) \
+ (((x) >> BIT_SHIFT_CH11_AVAL_PG_8814B) & BIT_MASK_CH11_AVAL_PG_8814B)
+#define BIT_SET_CH11_AVAL_PG_8814B(x, v) \
+ (BIT_CLEAR_CH11_AVAL_PG_8814B(x) | BIT_CH11_AVAL_PG_8814B(v))
+
+#define BIT_SHIFT_CH11_RSVD_PG_8814B 0
+#define BIT_MASK_CH11_RSVD_PG_8814B 0xfff
+#define BIT_CH11_RSVD_PG_8814B(x) \
+ (((x) & BIT_MASK_CH11_RSVD_PG_8814B) << BIT_SHIFT_CH11_RSVD_PG_8814B)
+#define BITS_CH11_RSVD_PG_8814B \
+ (BIT_MASK_CH11_RSVD_PG_8814B << BIT_SHIFT_CH11_RSVD_PG_8814B)
+#define BIT_CLEAR_CH11_RSVD_PG_8814B(x) ((x) & (~BITS_CH11_RSVD_PG_8814B))
+#define BIT_GET_CH11_RSVD_PG_8814B(x) \
+ (((x) >> BIT_SHIFT_CH11_RSVD_PG_8814B) & BIT_MASK_CH11_RSVD_PG_8814B)
+#define BIT_SET_CH11_RSVD_PG_8814B(x, v) \
+ (BIT_CLEAR_CH11_RSVD_PG_8814B(x) | BIT_CH11_RSVD_PG_8814B(v))
+
+/* 2 REG_DMA_RQPN_INFO_12_8814B */
+
+#define BIT_SHIFT_CH12_AVAL_PG_8814B 16
+#define BIT_MASK_CH12_AVAL_PG_8814B 0xfff
+#define BIT_CH12_AVAL_PG_8814B(x) \
+ (((x) & BIT_MASK_CH12_AVAL_PG_8814B) << BIT_SHIFT_CH12_AVAL_PG_8814B)
+#define BITS_CH12_AVAL_PG_8814B \
+ (BIT_MASK_CH12_AVAL_PG_8814B << BIT_SHIFT_CH12_AVAL_PG_8814B)
+#define BIT_CLEAR_CH12_AVAL_PG_8814B(x) ((x) & (~BITS_CH12_AVAL_PG_8814B))
+#define BIT_GET_CH12_AVAL_PG_8814B(x) \
+ (((x) >> BIT_SHIFT_CH12_AVAL_PG_8814B) & BIT_MASK_CH12_AVAL_PG_8814B)
+#define BIT_SET_CH12_AVAL_PG_8814B(x, v) \
+ (BIT_CLEAR_CH12_AVAL_PG_8814B(x) | BIT_CH12_AVAL_PG_8814B(v))
+
+#define BIT_SHIFT_CH12_RSVD_PG_8814B 0
+#define BIT_MASK_CH12_RSVD_PG_8814B 0xfff
+#define BIT_CH12_RSVD_PG_8814B(x) \
+ (((x) & BIT_MASK_CH12_RSVD_PG_8814B) << BIT_SHIFT_CH12_RSVD_PG_8814B)
+#define BITS_CH12_RSVD_PG_8814B \
+ (BIT_MASK_CH12_RSVD_PG_8814B << BIT_SHIFT_CH12_RSVD_PG_8814B)
+#define BIT_CLEAR_CH12_RSVD_PG_8814B(x) ((x) & (~BITS_CH12_RSVD_PG_8814B))
+#define BIT_GET_CH12_RSVD_PG_8814B(x) \
+ (((x) >> BIT_SHIFT_CH12_RSVD_PG_8814B) & BIT_MASK_CH12_RSVD_PG_8814B)
+#define BIT_SET_CH12_RSVD_PG_8814B(x, v) \
+ (BIT_CLEAR_CH12_RSVD_PG_8814B(x) | BIT_CH12_RSVD_PG_8814B(v))
+
+/* 2 REG_DMA_RQPN_INFO_13_8814B */
+
+#define BIT_SHIFT_CH13_AVAL_PG_8814B 16
+#define BIT_MASK_CH13_AVAL_PG_8814B 0xfff
+#define BIT_CH13_AVAL_PG_8814B(x) \
+ (((x) & BIT_MASK_CH13_AVAL_PG_8814B) << BIT_SHIFT_CH13_AVAL_PG_8814B)
+#define BITS_CH13_AVAL_PG_8814B \
+ (BIT_MASK_CH13_AVAL_PG_8814B << BIT_SHIFT_CH13_AVAL_PG_8814B)
+#define BIT_CLEAR_CH13_AVAL_PG_8814B(x) ((x) & (~BITS_CH13_AVAL_PG_8814B))
+#define BIT_GET_CH13_AVAL_PG_8814B(x) \
+ (((x) >> BIT_SHIFT_CH13_AVAL_PG_8814B) & BIT_MASK_CH13_AVAL_PG_8814B)
+#define BIT_SET_CH13_AVAL_PG_8814B(x, v) \
+ (BIT_CLEAR_CH13_AVAL_PG_8814B(x) | BIT_CH13_AVAL_PG_8814B(v))
+
+#define BIT_SHIFT_CH13_RSVD_PG_8814B 0
+#define BIT_MASK_CH13_RSVD_PG_8814B 0xfff
+#define BIT_CH13_RSVD_PG_8814B(x) \
+ (((x) & BIT_MASK_CH13_RSVD_PG_8814B) << BIT_SHIFT_CH13_RSVD_PG_8814B)
+#define BITS_CH13_RSVD_PG_8814B \
+ (BIT_MASK_CH13_RSVD_PG_8814B << BIT_SHIFT_CH13_RSVD_PG_8814B)
+#define BIT_CLEAR_CH13_RSVD_PG_8814B(x) ((x) & (~BITS_CH13_RSVD_PG_8814B))
+#define BIT_GET_CH13_RSVD_PG_8814B(x) \
+ (((x) >> BIT_SHIFT_CH13_RSVD_PG_8814B) & BIT_MASK_CH13_RSVD_PG_8814B)
+#define BIT_SET_CH13_RSVD_PG_8814B(x, v) \
+ (BIT_CLEAR_CH13_RSVD_PG_8814B(x) | BIT_CH13_RSVD_PG_8814B(v))
+
+/* 2 REG_DMA_RQPN_INFO_14_8814B */
+
+#define BIT_SHIFT_CH14_AVAL_PG_8814B 16
+#define BIT_MASK_CH14_AVAL_PG_8814B 0xfff
+#define BIT_CH14_AVAL_PG_8814B(x) \
+ (((x) & BIT_MASK_CH14_AVAL_PG_8814B) << BIT_SHIFT_CH14_AVAL_PG_8814B)
+#define BITS_CH14_AVAL_PG_8814B \
+ (BIT_MASK_CH14_AVAL_PG_8814B << BIT_SHIFT_CH14_AVAL_PG_8814B)
+#define BIT_CLEAR_CH14_AVAL_PG_8814B(x) ((x) & (~BITS_CH14_AVAL_PG_8814B))
+#define BIT_GET_CH14_AVAL_PG_8814B(x) \
+ (((x) >> BIT_SHIFT_CH14_AVAL_PG_8814B) & BIT_MASK_CH14_AVAL_PG_8814B)
+#define BIT_SET_CH14_AVAL_PG_8814B(x, v) \
+ (BIT_CLEAR_CH14_AVAL_PG_8814B(x) | BIT_CH14_AVAL_PG_8814B(v))
+
+#define BIT_SHIFT_CH14_RSVD_PG_8814B 0
+#define BIT_MASK_CH14_RSVD_PG_8814B 0xfff
+#define BIT_CH14_RSVD_PG_8814B(x) \
+ (((x) & BIT_MASK_CH14_RSVD_PG_8814B) << BIT_SHIFT_CH14_RSVD_PG_8814B)
+#define BITS_CH14_RSVD_PG_8814B \
+ (BIT_MASK_CH14_RSVD_PG_8814B << BIT_SHIFT_CH14_RSVD_PG_8814B)
+#define BIT_CLEAR_CH14_RSVD_PG_8814B(x) ((x) & (~BITS_CH14_RSVD_PG_8814B))
+#define BIT_GET_CH14_RSVD_PG_8814B(x) \
+ (((x) >> BIT_SHIFT_CH14_RSVD_PG_8814B) & BIT_MASK_CH14_RSVD_PG_8814B)
+#define BIT_SET_CH14_RSVD_PG_8814B(x, v) \
+ (BIT_CLEAR_CH14_RSVD_PG_8814B(x) | BIT_CH14_RSVD_PG_8814B(v))
+
+/* 2 REG_DMA_RQPN_INFO_15_8814B */
+
+#define BIT_SHIFT_CH15_AVAL_PG_8814B 16
+#define BIT_MASK_CH15_AVAL_PG_8814B 0xfff
+#define BIT_CH15_AVAL_PG_8814B(x) \
+ (((x) & BIT_MASK_CH15_AVAL_PG_8814B) << BIT_SHIFT_CH15_AVAL_PG_8814B)
+#define BITS_CH15_AVAL_PG_8814B \
+ (BIT_MASK_CH15_AVAL_PG_8814B << BIT_SHIFT_CH15_AVAL_PG_8814B)
+#define BIT_CLEAR_CH15_AVAL_PG_8814B(x) ((x) & (~BITS_CH15_AVAL_PG_8814B))
+#define BIT_GET_CH15_AVAL_PG_8814B(x) \
+ (((x) >> BIT_SHIFT_CH15_AVAL_PG_8814B) & BIT_MASK_CH15_AVAL_PG_8814B)
+#define BIT_SET_CH15_AVAL_PG_8814B(x, v) \
+ (BIT_CLEAR_CH15_AVAL_PG_8814B(x) | BIT_CH15_AVAL_PG_8814B(v))
+
+#define BIT_SHIFT_CH15_RSVD_PG_8814B 0
+#define BIT_MASK_CH15_RSVD_PG_8814B 0xfff
+#define BIT_CH15_RSVD_PG_8814B(x) \
+ (((x) & BIT_MASK_CH15_RSVD_PG_8814B) << BIT_SHIFT_CH15_RSVD_PG_8814B)
+#define BITS_CH15_RSVD_PG_8814B \
+ (BIT_MASK_CH15_RSVD_PG_8814B << BIT_SHIFT_CH15_RSVD_PG_8814B)
+#define BIT_CLEAR_CH15_RSVD_PG_8814B(x) ((x) & (~BITS_CH15_RSVD_PG_8814B))
+#define BIT_GET_CH15_RSVD_PG_8814B(x) \
+ (((x) >> BIT_SHIFT_CH15_RSVD_PG_8814B) & BIT_MASK_CH15_RSVD_PG_8814B)
+#define BIT_SET_CH15_RSVD_PG_8814B(x, v) \
+ (BIT_CLEAR_CH15_RSVD_PG_8814B(x) | BIT_CH15_RSVD_PG_8814B(v))
+
+/* 2 REG_DMA_RQPN_INFO_16_8814B */
+
+#define BIT_SHIFT_CH16_AVAL_PG_8814B 16
+#define BIT_MASK_CH16_AVAL_PG_8814B 0xfff
+#define BIT_CH16_AVAL_PG_8814B(x) \
+ (((x) & BIT_MASK_CH16_AVAL_PG_8814B) << BIT_SHIFT_CH16_AVAL_PG_8814B)
+#define BITS_CH16_AVAL_PG_8814B \
+ (BIT_MASK_CH16_AVAL_PG_8814B << BIT_SHIFT_CH16_AVAL_PG_8814B)
+#define BIT_CLEAR_CH16_AVAL_PG_8814B(x) ((x) & (~BITS_CH16_AVAL_PG_8814B))
+#define BIT_GET_CH16_AVAL_PG_8814B(x) \
+ (((x) >> BIT_SHIFT_CH16_AVAL_PG_8814B) & BIT_MASK_CH16_AVAL_PG_8814B)
+#define BIT_SET_CH16_AVAL_PG_8814B(x, v) \
+ (BIT_CLEAR_CH16_AVAL_PG_8814B(x) | BIT_CH16_AVAL_PG_8814B(v))
+
+#define BIT_SHIFT_CH16_RSVD_PG_8814B 0
+#define BIT_MASK_CH16_RSVD_PG_8814B 0xfff
+#define BIT_CH16_RSVD_PG_8814B(x) \
+ (((x) & BIT_MASK_CH16_RSVD_PG_8814B) << BIT_SHIFT_CH16_RSVD_PG_8814B)
+#define BITS_CH16_RSVD_PG_8814B \
+ (BIT_MASK_CH16_RSVD_PG_8814B << BIT_SHIFT_CH16_RSVD_PG_8814B)
+#define BIT_CLEAR_CH16_RSVD_PG_8814B(x) ((x) & (~BITS_CH16_RSVD_PG_8814B))
+#define BIT_GET_CH16_RSVD_PG_8814B(x) \
+ (((x) >> BIT_SHIFT_CH16_RSVD_PG_8814B) & BIT_MASK_CH16_RSVD_PG_8814B)
+#define BIT_SET_CH16_RSVD_PG_8814B(x, v) \
+ (BIT_CLEAR_CH16_RSVD_PG_8814B(x) | BIT_CH16_RSVD_PG_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_HWAMSDU_CTL1_8814B */
+
+#define BIT_SHIFT_HWAMSDU_PKTNUM_8814B 8
+#define BIT_MASK_HWAMSDU_PKTNUM_8814B 0x3f
+#define BIT_HWAMSDU_PKTNUM_8814B(x) \
+ (((x) & BIT_MASK_HWAMSDU_PKTNUM_8814B) \
+ << BIT_SHIFT_HWAMSDU_PKTNUM_8814B)
+#define BITS_HWAMSDU_PKTNUM_8814B \
+ (BIT_MASK_HWAMSDU_PKTNUM_8814B << BIT_SHIFT_HWAMSDU_PKTNUM_8814B)
+#define BIT_CLEAR_HWAMSDU_PKTNUM_8814B(x) ((x) & (~BITS_HWAMSDU_PKTNUM_8814B))
+#define BIT_GET_HWAMSDU_PKTNUM_8814B(x) \
+ (((x) >> BIT_SHIFT_HWAMSDU_PKTNUM_8814B) & \
+ BIT_MASK_HWAMSDU_PKTNUM_8814B)
+#define BIT_SET_HWAMSDU_PKTNUM_8814B(x, v) \
+ (BIT_CLEAR_HWAMSDU_PKTNUM_8814B(x) | BIT_HWAMSDU_PKTNUM_8814B(v))
+
+#define BIT_HWAMSDU_BUSY_8814B BIT(7)
+#define BIT_SINGLE_AMSDU_8814B BIT(2)
+#define BIT_HWAMSDU_PADDING_MODE_8814B BIT(1)
+#define BIT_HWAMSDU_EN_8814B BIT(0)
+
+/* 2 REG_HWAMSDU_CTL2_8814B */
+
+#define BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT_8814B 16
+#define BIT_MASK_HWAMSDU_AMSDU_TIMEOUT_8814B 0xffff
+#define BIT_HWAMSDU_AMSDU_TIMEOUT_8814B(x) \
+ (((x) & BIT_MASK_HWAMSDU_AMSDU_TIMEOUT_8814B) \
+ << BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT_8814B)
+#define BITS_HWAMSDU_AMSDU_TIMEOUT_8814B \
+ (BIT_MASK_HWAMSDU_AMSDU_TIMEOUT_8814B \
+ << BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT_8814B)
+#define BIT_CLEAR_HWAMSDU_AMSDU_TIMEOUT_8814B(x) \
+ ((x) & (~BITS_HWAMSDU_AMSDU_TIMEOUT_8814B))
+#define BIT_GET_HWAMSDU_AMSDU_TIMEOUT_8814B(x) \
+ (((x) >> BIT_SHIFT_HWAMSDU_AMSDU_TIMEOUT_8814B) & \
+ BIT_MASK_HWAMSDU_AMSDU_TIMEOUT_8814B)
+#define BIT_SET_HWAMSDU_AMSDU_TIMEOUT_8814B(x, v) \
+ (BIT_CLEAR_HWAMSDU_AMSDU_TIMEOUT_8814B(x) | \
+ BIT_HWAMSDU_AMSDU_TIMEOUT_8814B(v))
+
+#define BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT_8814B 0
+#define BIT_MASK_HWAMSDU_MSDU_TIMEOUT_8814B 0xffff
+#define BIT_HWAMSDU_MSDU_TIMEOUT_8814B(x) \
+ (((x) & BIT_MASK_HWAMSDU_MSDU_TIMEOUT_8814B) \
+ << BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT_8814B)
+#define BITS_HWAMSDU_MSDU_TIMEOUT_8814B \
+ (BIT_MASK_HWAMSDU_MSDU_TIMEOUT_8814B \
+ << BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT_8814B)
+#define BIT_CLEAR_HWAMSDU_MSDU_TIMEOUT_8814B(x) \
+ ((x) & (~BITS_HWAMSDU_MSDU_TIMEOUT_8814B))
+#define BIT_GET_HWAMSDU_MSDU_TIMEOUT_8814B(x) \
+ (((x) >> BIT_SHIFT_HWAMSDU_MSDU_TIMEOUT_8814B) & \
+ BIT_MASK_HWAMSDU_MSDU_TIMEOUT_8814B)
+#define BIT_SET_HWAMSDU_MSDU_TIMEOUT_8814B(x, v) \
+ (BIT_CLEAR_HWAMSDU_MSDU_TIMEOUT_8814B(x) | \
+ BIT_HWAMSDU_MSDU_TIMEOUT_8814B(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_0_8814B */
+#define BIT_CH0_INT_EN_8814B BIT(31)
+
+#define BIT_SHIFT_CH0_HIGH_TH_8814B 16
+#define BIT_MASK_CH0_HIGH_TH_8814B 0xfff
+#define BIT_CH0_HIGH_TH_8814B(x) \
+ (((x) & BIT_MASK_CH0_HIGH_TH_8814B) << BIT_SHIFT_CH0_HIGH_TH_8814B)
+#define BITS_CH0_HIGH_TH_8814B \
+ (BIT_MASK_CH0_HIGH_TH_8814B << BIT_SHIFT_CH0_HIGH_TH_8814B)
+#define BIT_CLEAR_CH0_HIGH_TH_8814B(x) ((x) & (~BITS_CH0_HIGH_TH_8814B))
+#define BIT_GET_CH0_HIGH_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_CH0_HIGH_TH_8814B) & BIT_MASK_CH0_HIGH_TH_8814B)
+#define BIT_SET_CH0_HIGH_TH_8814B(x, v) \
+ (BIT_CLEAR_CH0_HIGH_TH_8814B(x) | BIT_CH0_HIGH_TH_8814B(v))
+
+#define BIT_SHIFT_CH0_LOW_TH_8814B 0
+#define BIT_MASK_CH0_LOW_TH_8814B 0xfff
+#define BIT_CH0_LOW_TH_8814B(x) \
+ (((x) & BIT_MASK_CH0_LOW_TH_8814B) << BIT_SHIFT_CH0_LOW_TH_8814B)
+#define BITS_CH0_LOW_TH_8814B \
+ (BIT_MASK_CH0_LOW_TH_8814B << BIT_SHIFT_CH0_LOW_TH_8814B)
+#define BIT_CLEAR_CH0_LOW_TH_8814B(x) ((x) & (~BITS_CH0_LOW_TH_8814B))
+#define BIT_GET_CH0_LOW_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_CH0_LOW_TH_8814B) & BIT_MASK_CH0_LOW_TH_8814B)
+#define BIT_SET_CH0_LOW_TH_8814B(x, v) \
+ (BIT_CLEAR_CH0_LOW_TH_8814B(x) | BIT_CH0_LOW_TH_8814B(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_1_8814B */
+#define BIT_CH1_INT_EN_8814B BIT(31)
+
+#define BIT_SHIFT_CH1_HIGH_TH_8814B 16
+#define BIT_MASK_CH1_HIGH_TH_8814B 0xfff
+#define BIT_CH1_HIGH_TH_8814B(x) \
+ (((x) & BIT_MASK_CH1_HIGH_TH_8814B) << BIT_SHIFT_CH1_HIGH_TH_8814B)
+#define BITS_CH1_HIGH_TH_8814B \
+ (BIT_MASK_CH1_HIGH_TH_8814B << BIT_SHIFT_CH1_HIGH_TH_8814B)
+#define BIT_CLEAR_CH1_HIGH_TH_8814B(x) ((x) & (~BITS_CH1_HIGH_TH_8814B))
+#define BIT_GET_CH1_HIGH_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_CH1_HIGH_TH_8814B) & BIT_MASK_CH1_HIGH_TH_8814B)
+#define BIT_SET_CH1_HIGH_TH_8814B(x, v) \
+ (BIT_CLEAR_CH1_HIGH_TH_8814B(x) | BIT_CH1_HIGH_TH_8814B(v))
+
+#define BIT_SHIFT_CH1_LOW_TH_8814B 0
+#define BIT_MASK_CH1_LOW_TH_8814B 0xfff
+#define BIT_CH1_LOW_TH_8814B(x) \
+ (((x) & BIT_MASK_CH1_LOW_TH_8814B) << BIT_SHIFT_CH1_LOW_TH_8814B)
+#define BITS_CH1_LOW_TH_8814B \
+ (BIT_MASK_CH1_LOW_TH_8814B << BIT_SHIFT_CH1_LOW_TH_8814B)
+#define BIT_CLEAR_CH1_LOW_TH_8814B(x) ((x) & (~BITS_CH1_LOW_TH_8814B))
+#define BIT_GET_CH1_LOW_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_CH1_LOW_TH_8814B) & BIT_MASK_CH1_LOW_TH_8814B)
+#define BIT_SET_CH1_LOW_TH_8814B(x, v) \
+ (BIT_CLEAR_CH1_LOW_TH_8814B(x) | BIT_CH1_LOW_TH_8814B(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_2_8814B */
+#define BIT_CH2_INT_EN_8814B BIT(31)
+
+#define BIT_SHIFT_CH2_HIGH_TH_8814B 16
+#define BIT_MASK_CH2_HIGH_TH_8814B 0xfff
+#define BIT_CH2_HIGH_TH_8814B(x) \
+ (((x) & BIT_MASK_CH2_HIGH_TH_8814B) << BIT_SHIFT_CH2_HIGH_TH_8814B)
+#define BITS_CH2_HIGH_TH_8814B \
+ (BIT_MASK_CH2_HIGH_TH_8814B << BIT_SHIFT_CH2_HIGH_TH_8814B)
+#define BIT_CLEAR_CH2_HIGH_TH_8814B(x) ((x) & (~BITS_CH2_HIGH_TH_8814B))
+#define BIT_GET_CH2_HIGH_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_CH2_HIGH_TH_8814B) & BIT_MASK_CH2_HIGH_TH_8814B)
+#define BIT_SET_CH2_HIGH_TH_8814B(x, v) \
+ (BIT_CLEAR_CH2_HIGH_TH_8814B(x) | BIT_CH2_HIGH_TH_8814B(v))
+
+#define BIT_SHIFT_CH2_LOW_TH_8814B 0
+#define BIT_MASK_CH2_LOW_TH_8814B 0xfff
+#define BIT_CH2_LOW_TH_8814B(x) \
+ (((x) & BIT_MASK_CH2_LOW_TH_8814B) << BIT_SHIFT_CH2_LOW_TH_8814B)
+#define BITS_CH2_LOW_TH_8814B \
+ (BIT_MASK_CH2_LOW_TH_8814B << BIT_SHIFT_CH2_LOW_TH_8814B)
+#define BIT_CLEAR_CH2_LOW_TH_8814B(x) ((x) & (~BITS_CH2_LOW_TH_8814B))
+#define BIT_GET_CH2_LOW_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_CH2_LOW_TH_8814B) & BIT_MASK_CH2_LOW_TH_8814B)
+#define BIT_SET_CH2_LOW_TH_8814B(x, v) \
+ (BIT_CLEAR_CH2_LOW_TH_8814B(x) | BIT_CH2_LOW_TH_8814B(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_3_8814B */
+#define BIT_CH3_INT_EN_8814B BIT(31)
+
+#define BIT_SHIFT_CH3_HIGH_TH_8814B 16
+#define BIT_MASK_CH3_HIGH_TH_8814B 0xfff
+#define BIT_CH3_HIGH_TH_8814B(x) \
+ (((x) & BIT_MASK_CH3_HIGH_TH_8814B) << BIT_SHIFT_CH3_HIGH_TH_8814B)
+#define BITS_CH3_HIGH_TH_8814B \
+ (BIT_MASK_CH3_HIGH_TH_8814B << BIT_SHIFT_CH3_HIGH_TH_8814B)
+#define BIT_CLEAR_CH3_HIGH_TH_8814B(x) ((x) & (~BITS_CH3_HIGH_TH_8814B))
+#define BIT_GET_CH3_HIGH_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_CH3_HIGH_TH_8814B) & BIT_MASK_CH3_HIGH_TH_8814B)
+#define BIT_SET_CH3_HIGH_TH_8814B(x, v) \
+ (BIT_CLEAR_CH3_HIGH_TH_8814B(x) | BIT_CH3_HIGH_TH_8814B(v))
+
+#define BIT_SHIFT_CH3_LOW_TH_8814B 0
+#define BIT_MASK_CH3_LOW_TH_8814B 0xfff
+#define BIT_CH3_LOW_TH_8814B(x) \
+ (((x) & BIT_MASK_CH3_LOW_TH_8814B) << BIT_SHIFT_CH3_LOW_TH_8814B)
+#define BITS_CH3_LOW_TH_8814B \
+ (BIT_MASK_CH3_LOW_TH_8814B << BIT_SHIFT_CH3_LOW_TH_8814B)
+#define BIT_CLEAR_CH3_LOW_TH_8814B(x) ((x) & (~BITS_CH3_LOW_TH_8814B))
+#define BIT_GET_CH3_LOW_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_CH3_LOW_TH_8814B) & BIT_MASK_CH3_LOW_TH_8814B)
+#define BIT_SET_CH3_LOW_TH_8814B(x, v) \
+ (BIT_CLEAR_CH3_LOW_TH_8814B(x) | BIT_CH3_LOW_TH_8814B(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_4_8814B */
+#define BIT_CH4_INT_EN_8814B BIT(31)
+
+#define BIT_SHIFT_CH4_HIGH_TH_8814B 16
+#define BIT_MASK_CH4_HIGH_TH_8814B 0xfff
+#define BIT_CH4_HIGH_TH_8814B(x) \
+ (((x) & BIT_MASK_CH4_HIGH_TH_8814B) << BIT_SHIFT_CH4_HIGH_TH_8814B)
+#define BITS_CH4_HIGH_TH_8814B \
+ (BIT_MASK_CH4_HIGH_TH_8814B << BIT_SHIFT_CH4_HIGH_TH_8814B)
+#define BIT_CLEAR_CH4_HIGH_TH_8814B(x) ((x) & (~BITS_CH4_HIGH_TH_8814B))
+#define BIT_GET_CH4_HIGH_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_CH4_HIGH_TH_8814B) & BIT_MASK_CH4_HIGH_TH_8814B)
+#define BIT_SET_CH4_HIGH_TH_8814B(x, v) \
+ (BIT_CLEAR_CH4_HIGH_TH_8814B(x) | BIT_CH4_HIGH_TH_8814B(v))
+
+#define BIT_SHIFT_CH4_LOW_TH_8814B 0
+#define BIT_MASK_CH4_LOW_TH_8814B 0xfff
+#define BIT_CH4_LOW_TH_8814B(x) \
+ (((x) & BIT_MASK_CH4_LOW_TH_8814B) << BIT_SHIFT_CH4_LOW_TH_8814B)
+#define BITS_CH4_LOW_TH_8814B \
+ (BIT_MASK_CH4_LOW_TH_8814B << BIT_SHIFT_CH4_LOW_TH_8814B)
+#define BIT_CLEAR_CH4_LOW_TH_8814B(x) ((x) & (~BITS_CH4_LOW_TH_8814B))
+#define BIT_GET_CH4_LOW_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_CH4_LOW_TH_8814B) & BIT_MASK_CH4_LOW_TH_8814B)
+#define BIT_SET_CH4_LOW_TH_8814B(x, v) \
+ (BIT_CLEAR_CH4_LOW_TH_8814B(x) | BIT_CH4_LOW_TH_8814B(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_5_8814B */
+#define BIT_CH5_INT_EN_8814B BIT(31)
+
+#define BIT_SHIFT_CH5_HIGH_TH_8814B 16
+#define BIT_MASK_CH5_HIGH_TH_8814B 0xfff
+#define BIT_CH5_HIGH_TH_8814B(x) \
+ (((x) & BIT_MASK_CH5_HIGH_TH_8814B) << BIT_SHIFT_CH5_HIGH_TH_8814B)
+#define BITS_CH5_HIGH_TH_8814B \
+ (BIT_MASK_CH5_HIGH_TH_8814B << BIT_SHIFT_CH5_HIGH_TH_8814B)
+#define BIT_CLEAR_CH5_HIGH_TH_8814B(x) ((x) & (~BITS_CH5_HIGH_TH_8814B))
+#define BIT_GET_CH5_HIGH_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_CH5_HIGH_TH_8814B) & BIT_MASK_CH5_HIGH_TH_8814B)
+#define BIT_SET_CH5_HIGH_TH_8814B(x, v) \
+ (BIT_CLEAR_CH5_HIGH_TH_8814B(x) | BIT_CH5_HIGH_TH_8814B(v))
+
+#define BIT_SHIFT_CH5_LOW_TH_8814B 0
+#define BIT_MASK_CH5_LOW_TH_8814B 0xfff
+#define BIT_CH5_LOW_TH_8814B(x) \
+ (((x) & BIT_MASK_CH5_LOW_TH_8814B) << BIT_SHIFT_CH5_LOW_TH_8814B)
+#define BITS_CH5_LOW_TH_8814B \
+ (BIT_MASK_CH5_LOW_TH_8814B << BIT_SHIFT_CH5_LOW_TH_8814B)
+#define BIT_CLEAR_CH5_LOW_TH_8814B(x) ((x) & (~BITS_CH5_LOW_TH_8814B))
+#define BIT_GET_CH5_LOW_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_CH5_LOW_TH_8814B) & BIT_MASK_CH5_LOW_TH_8814B)
+#define BIT_SET_CH5_LOW_TH_8814B(x, v) \
+ (BIT_CLEAR_CH5_LOW_TH_8814B(x) | BIT_CH5_LOW_TH_8814B(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_6_8814B */
+#define BIT_CH6_INT_EN_8814B BIT(31)
+
+#define BIT_SHIFT_CH6_HIGH_TH_8814B 16
+#define BIT_MASK_CH6_HIGH_TH_8814B 0xfff
+#define BIT_CH6_HIGH_TH_8814B(x) \
+ (((x) & BIT_MASK_CH6_HIGH_TH_8814B) << BIT_SHIFT_CH6_HIGH_TH_8814B)
+#define BITS_CH6_HIGH_TH_8814B \
+ (BIT_MASK_CH6_HIGH_TH_8814B << BIT_SHIFT_CH6_HIGH_TH_8814B)
+#define BIT_CLEAR_CH6_HIGH_TH_8814B(x) ((x) & (~BITS_CH6_HIGH_TH_8814B))
+#define BIT_GET_CH6_HIGH_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_CH6_HIGH_TH_8814B) & BIT_MASK_CH6_HIGH_TH_8814B)
+#define BIT_SET_CH6_HIGH_TH_8814B(x, v) \
+ (BIT_CLEAR_CH6_HIGH_TH_8814B(x) | BIT_CH6_HIGH_TH_8814B(v))
+
+#define BIT_SHIFT_CH6_LOW_TH_8814B 0
+#define BIT_MASK_CH6_LOW_TH_8814B 0xfff
+#define BIT_CH6_LOW_TH_8814B(x) \
+ (((x) & BIT_MASK_CH6_LOW_TH_8814B) << BIT_SHIFT_CH6_LOW_TH_8814B)
+#define BITS_CH6_LOW_TH_8814B \
+ (BIT_MASK_CH6_LOW_TH_8814B << BIT_SHIFT_CH6_LOW_TH_8814B)
+#define BIT_CLEAR_CH6_LOW_TH_8814B(x) ((x) & (~BITS_CH6_LOW_TH_8814B))
+#define BIT_GET_CH6_LOW_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_CH6_LOW_TH_8814B) & BIT_MASK_CH6_LOW_TH_8814B)
+#define BIT_SET_CH6_LOW_TH_8814B(x, v) \
+ (BIT_CLEAR_CH6_LOW_TH_8814B(x) | BIT_CH6_LOW_TH_8814B(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_7_8814B */
+#define BIT_CH7_INT_EN_8814B BIT(31)
+
+#define BIT_SHIFT_CH7_HIGH_TH_8814B 16
+#define BIT_MASK_CH7_HIGH_TH_8814B 0xfff
+#define BIT_CH7_HIGH_TH_8814B(x) \
+ (((x) & BIT_MASK_CH7_HIGH_TH_8814B) << BIT_SHIFT_CH7_HIGH_TH_8814B)
+#define BITS_CH7_HIGH_TH_8814B \
+ (BIT_MASK_CH7_HIGH_TH_8814B << BIT_SHIFT_CH7_HIGH_TH_8814B)
+#define BIT_CLEAR_CH7_HIGH_TH_8814B(x) ((x) & (~BITS_CH7_HIGH_TH_8814B))
+#define BIT_GET_CH7_HIGH_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_CH7_HIGH_TH_8814B) & BIT_MASK_CH7_HIGH_TH_8814B)
+#define BIT_SET_CH7_HIGH_TH_8814B(x, v) \
+ (BIT_CLEAR_CH7_HIGH_TH_8814B(x) | BIT_CH7_HIGH_TH_8814B(v))
+
+#define BIT_SHIFT_CH7_LOW_TH_8814B 0
+#define BIT_MASK_CH7_LOW_TH_8814B 0xfff
+#define BIT_CH7_LOW_TH_8814B(x) \
+ (((x) & BIT_MASK_CH7_LOW_TH_8814B) << BIT_SHIFT_CH7_LOW_TH_8814B)
+#define BITS_CH7_LOW_TH_8814B \
+ (BIT_MASK_CH7_LOW_TH_8814B << BIT_SHIFT_CH7_LOW_TH_8814B)
+#define BIT_CLEAR_CH7_LOW_TH_8814B(x) ((x) & (~BITS_CH7_LOW_TH_8814B))
+#define BIT_GET_CH7_LOW_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_CH7_LOW_TH_8814B) & BIT_MASK_CH7_LOW_TH_8814B)
+#define BIT_SET_CH7_LOW_TH_8814B(x, v) \
+ (BIT_CLEAR_CH7_LOW_TH_8814B(x) | BIT_CH7_LOW_TH_8814B(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_8_8814B */
+#define BIT_CH8_INT_EN_8814B BIT(31)
+
+#define BIT_SHIFT_CH8_HIGH_TH_8814B 16
+#define BIT_MASK_CH8_HIGH_TH_8814B 0xfff
+#define BIT_CH8_HIGH_TH_8814B(x) \
+ (((x) & BIT_MASK_CH8_HIGH_TH_8814B) << BIT_SHIFT_CH8_HIGH_TH_8814B)
+#define BITS_CH8_HIGH_TH_8814B \
+ (BIT_MASK_CH8_HIGH_TH_8814B << BIT_SHIFT_CH8_HIGH_TH_8814B)
+#define BIT_CLEAR_CH8_HIGH_TH_8814B(x) ((x) & (~BITS_CH8_HIGH_TH_8814B))
+#define BIT_GET_CH8_HIGH_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_CH8_HIGH_TH_8814B) & BIT_MASK_CH8_HIGH_TH_8814B)
+#define BIT_SET_CH8_HIGH_TH_8814B(x, v) \
+ (BIT_CLEAR_CH8_HIGH_TH_8814B(x) | BIT_CH8_HIGH_TH_8814B(v))
+
+#define BIT_SHIFT_CH8_LOW_TH_8814B 0
+#define BIT_MASK_CH8_LOW_TH_8814B 0xfff
+#define BIT_CH8_LOW_TH_8814B(x) \
+ (((x) & BIT_MASK_CH8_LOW_TH_8814B) << BIT_SHIFT_CH8_LOW_TH_8814B)
+#define BITS_CH8_LOW_TH_8814B \
+ (BIT_MASK_CH8_LOW_TH_8814B << BIT_SHIFT_CH8_LOW_TH_8814B)
+#define BIT_CLEAR_CH8_LOW_TH_8814B(x) ((x) & (~BITS_CH8_LOW_TH_8814B))
+#define BIT_GET_CH8_LOW_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_CH8_LOW_TH_8814B) & BIT_MASK_CH8_LOW_TH_8814B)
+#define BIT_SET_CH8_LOW_TH_8814B(x, v) \
+ (BIT_CLEAR_CH8_LOW_TH_8814B(x) | BIT_CH8_LOW_TH_8814B(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_9_8814B */
+#define BIT_CH9_INT_EN_8814B BIT(31)
+
+#define BIT_SHIFT_CH9_HIGH_TH_8814B 16
+#define BIT_MASK_CH9_HIGH_TH_8814B 0xfff
+#define BIT_CH9_HIGH_TH_8814B(x) \
+ (((x) & BIT_MASK_CH9_HIGH_TH_8814B) << BIT_SHIFT_CH9_HIGH_TH_8814B)
+#define BITS_CH9_HIGH_TH_8814B \
+ (BIT_MASK_CH9_HIGH_TH_8814B << BIT_SHIFT_CH9_HIGH_TH_8814B)
+#define BIT_CLEAR_CH9_HIGH_TH_8814B(x) ((x) & (~BITS_CH9_HIGH_TH_8814B))
+#define BIT_GET_CH9_HIGH_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_CH9_HIGH_TH_8814B) & BIT_MASK_CH9_HIGH_TH_8814B)
+#define BIT_SET_CH9_HIGH_TH_8814B(x, v) \
+ (BIT_CLEAR_CH9_HIGH_TH_8814B(x) | BIT_CH9_HIGH_TH_8814B(v))
+
+#define BIT_SHIFT_CH9_LOW_TH_8814B 0
+#define BIT_MASK_CH9_LOW_TH_8814B 0xfff
+#define BIT_CH9_LOW_TH_8814B(x) \
+ (((x) & BIT_MASK_CH9_LOW_TH_8814B) << BIT_SHIFT_CH9_LOW_TH_8814B)
+#define BITS_CH9_LOW_TH_8814B \
+ (BIT_MASK_CH9_LOW_TH_8814B << BIT_SHIFT_CH9_LOW_TH_8814B)
+#define BIT_CLEAR_CH9_LOW_TH_8814B(x) ((x) & (~BITS_CH9_LOW_TH_8814B))
+#define BIT_GET_CH9_LOW_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_CH9_LOW_TH_8814B) & BIT_MASK_CH9_LOW_TH_8814B)
+#define BIT_SET_CH9_LOW_TH_8814B(x, v) \
+ (BIT_CLEAR_CH9_LOW_TH_8814B(x) | BIT_CH9_LOW_TH_8814B(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_10_8814B */
+#define BIT_CH10_INT_EN_8814B BIT(31)
+
+#define BIT_SHIFT_CH10_HIGH_TH_8814B 16
+#define BIT_MASK_CH10_HIGH_TH_8814B 0xfff
+#define BIT_CH10_HIGH_TH_8814B(x) \
+ (((x) & BIT_MASK_CH10_HIGH_TH_8814B) << BIT_SHIFT_CH10_HIGH_TH_8814B)
+#define BITS_CH10_HIGH_TH_8814B \
+ (BIT_MASK_CH10_HIGH_TH_8814B << BIT_SHIFT_CH10_HIGH_TH_8814B)
+#define BIT_CLEAR_CH10_HIGH_TH_8814B(x) ((x) & (~BITS_CH10_HIGH_TH_8814B))
+#define BIT_GET_CH10_HIGH_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_CH10_HIGH_TH_8814B) & BIT_MASK_CH10_HIGH_TH_8814B)
+#define BIT_SET_CH10_HIGH_TH_8814B(x, v) \
+ (BIT_CLEAR_CH10_HIGH_TH_8814B(x) | BIT_CH10_HIGH_TH_8814B(v))
+
+#define BIT_SHIFT_CH10_LOW_TH_8814B 0
+#define BIT_MASK_CH10_LOW_TH_8814B 0xfff
+#define BIT_CH10_LOW_TH_8814B(x) \
+ (((x) & BIT_MASK_CH10_LOW_TH_8814B) << BIT_SHIFT_CH10_LOW_TH_8814B)
+#define BITS_CH10_LOW_TH_8814B \
+ (BIT_MASK_CH10_LOW_TH_8814B << BIT_SHIFT_CH10_LOW_TH_8814B)
+#define BIT_CLEAR_CH10_LOW_TH_8814B(x) ((x) & (~BITS_CH10_LOW_TH_8814B))
+#define BIT_GET_CH10_LOW_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_CH10_LOW_TH_8814B) & BIT_MASK_CH10_LOW_TH_8814B)
+#define BIT_SET_CH10_LOW_TH_8814B(x, v) \
+ (BIT_CLEAR_CH10_LOW_TH_8814B(x) | BIT_CH10_LOW_TH_8814B(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_11_8814B */
+#define BIT_CH11_INT_EN_8814B BIT(31)
+
+#define BIT_SHIFT_CH11_HIGH_TH_8814B 16
+#define BIT_MASK_CH11_HIGH_TH_8814B 0xfff
+#define BIT_CH11_HIGH_TH_8814B(x) \
+ (((x) & BIT_MASK_CH11_HIGH_TH_8814B) << BIT_SHIFT_CH11_HIGH_TH_8814B)
+#define BITS_CH11_HIGH_TH_8814B \
+ (BIT_MASK_CH11_HIGH_TH_8814B << BIT_SHIFT_CH11_HIGH_TH_8814B)
+#define BIT_CLEAR_CH11_HIGH_TH_8814B(x) ((x) & (~BITS_CH11_HIGH_TH_8814B))
+#define BIT_GET_CH11_HIGH_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_CH11_HIGH_TH_8814B) & BIT_MASK_CH11_HIGH_TH_8814B)
+#define BIT_SET_CH11_HIGH_TH_8814B(x, v) \
+ (BIT_CLEAR_CH11_HIGH_TH_8814B(x) | BIT_CH11_HIGH_TH_8814B(v))
+
+#define BIT_SHIFT_CH11_LOW_TH_8814B 0
+#define BIT_MASK_CH11_LOW_TH_8814B 0xfff
+#define BIT_CH11_LOW_TH_8814B(x) \
+ (((x) & BIT_MASK_CH11_LOW_TH_8814B) << BIT_SHIFT_CH11_LOW_TH_8814B)
+#define BITS_CH11_LOW_TH_8814B \
+ (BIT_MASK_CH11_LOW_TH_8814B << BIT_SHIFT_CH11_LOW_TH_8814B)
+#define BIT_CLEAR_CH11_LOW_TH_8814B(x) ((x) & (~BITS_CH11_LOW_TH_8814B))
+#define BIT_GET_CH11_LOW_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_CH11_LOW_TH_8814B) & BIT_MASK_CH11_LOW_TH_8814B)
+#define BIT_SET_CH11_LOW_TH_8814B(x, v) \
+ (BIT_CLEAR_CH11_LOW_TH_8814B(x) | BIT_CH11_LOW_TH_8814B(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_12_8814B */
+#define BIT_CH12_INT_EN_8814B BIT(31)
+
+#define BIT_SHIFT_CH12_HIGH_TH_8814B 16
+#define BIT_MASK_CH12_HIGH_TH_8814B 0xfff
+#define BIT_CH12_HIGH_TH_8814B(x) \
+ (((x) & BIT_MASK_CH12_HIGH_TH_8814B) << BIT_SHIFT_CH12_HIGH_TH_8814B)
+#define BITS_CH12_HIGH_TH_8814B \
+ (BIT_MASK_CH12_HIGH_TH_8814B << BIT_SHIFT_CH12_HIGH_TH_8814B)
+#define BIT_CLEAR_CH12_HIGH_TH_8814B(x) ((x) & (~BITS_CH12_HIGH_TH_8814B))
+#define BIT_GET_CH12_HIGH_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_CH12_HIGH_TH_8814B) & BIT_MASK_CH12_HIGH_TH_8814B)
+#define BIT_SET_CH12_HIGH_TH_8814B(x, v) \
+ (BIT_CLEAR_CH12_HIGH_TH_8814B(x) | BIT_CH12_HIGH_TH_8814B(v))
+
+#define BIT_SHIFT_CH12_LOW_TH_8814B 0
+#define BIT_MASK_CH12_LOW_TH_8814B 0xfff
+#define BIT_CH12_LOW_TH_8814B(x) \
+ (((x) & BIT_MASK_CH12_LOW_TH_8814B) << BIT_SHIFT_CH12_LOW_TH_8814B)
+#define BITS_CH12_LOW_TH_8814B \
+ (BIT_MASK_CH12_LOW_TH_8814B << BIT_SHIFT_CH12_LOW_TH_8814B)
+#define BIT_CLEAR_CH12_LOW_TH_8814B(x) ((x) & (~BITS_CH12_LOW_TH_8814B))
+#define BIT_GET_CH12_LOW_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_CH12_LOW_TH_8814B) & BIT_MASK_CH12_LOW_TH_8814B)
+#define BIT_SET_CH12_LOW_TH_8814B(x, v) \
+ (BIT_CLEAR_CH12_LOW_TH_8814B(x) | BIT_CH12_LOW_TH_8814B(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_13_8814B */
+#define BIT_CH13_INT_EN_8814B BIT(31)
+
+#define BIT_SHIFT_CH13_HIGH_TH_8814B 16
+#define BIT_MASK_CH13_HIGH_TH_8814B 0xfff
+#define BIT_CH13_HIGH_TH_8814B(x) \
+ (((x) & BIT_MASK_CH13_HIGH_TH_8814B) << BIT_SHIFT_CH13_HIGH_TH_8814B)
+#define BITS_CH13_HIGH_TH_8814B \
+ (BIT_MASK_CH13_HIGH_TH_8814B << BIT_SHIFT_CH13_HIGH_TH_8814B)
+#define BIT_CLEAR_CH13_HIGH_TH_8814B(x) ((x) & (~BITS_CH13_HIGH_TH_8814B))
+#define BIT_GET_CH13_HIGH_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_CH13_HIGH_TH_8814B) & BIT_MASK_CH13_HIGH_TH_8814B)
+#define BIT_SET_CH13_HIGH_TH_8814B(x, v) \
+ (BIT_CLEAR_CH13_HIGH_TH_8814B(x) | BIT_CH13_HIGH_TH_8814B(v))
+
+#define BIT_SHIFT_CH13_LOW_TH_8814B 0
+#define BIT_MASK_CH13_LOW_TH_8814B 0xfff
+#define BIT_CH13_LOW_TH_8814B(x) \
+ (((x) & BIT_MASK_CH13_LOW_TH_8814B) << BIT_SHIFT_CH13_LOW_TH_8814B)
+#define BITS_CH13_LOW_TH_8814B \
+ (BIT_MASK_CH13_LOW_TH_8814B << BIT_SHIFT_CH13_LOW_TH_8814B)
+#define BIT_CLEAR_CH13_LOW_TH_8814B(x) ((x) & (~BITS_CH13_LOW_TH_8814B))
+#define BIT_GET_CH13_LOW_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_CH13_LOW_TH_8814B) & BIT_MASK_CH13_LOW_TH_8814B)
+#define BIT_SET_CH13_LOW_TH_8814B(x, v) \
+ (BIT_CLEAR_CH13_LOW_TH_8814B(x) | BIT_CH13_LOW_TH_8814B(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_14_8814B */
+#define BIT_CH14_INT_EN_8814B BIT(31)
+
+#define BIT_SHIFT_CH14_HIGH_TH_8814B 16
+#define BIT_MASK_CH14_HIGH_TH_8814B 0xfff
+#define BIT_CH14_HIGH_TH_8814B(x) \
+ (((x) & BIT_MASK_CH14_HIGH_TH_8814B) << BIT_SHIFT_CH14_HIGH_TH_8814B)
+#define BITS_CH14_HIGH_TH_8814B \
+ (BIT_MASK_CH14_HIGH_TH_8814B << BIT_SHIFT_CH14_HIGH_TH_8814B)
+#define BIT_CLEAR_CH14_HIGH_TH_8814B(x) ((x) & (~BITS_CH14_HIGH_TH_8814B))
+#define BIT_GET_CH14_HIGH_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_CH14_HIGH_TH_8814B) & BIT_MASK_CH14_HIGH_TH_8814B)
+#define BIT_SET_CH14_HIGH_TH_8814B(x, v) \
+ (BIT_CLEAR_CH14_HIGH_TH_8814B(x) | BIT_CH14_HIGH_TH_8814B(v))
+
+#define BIT_SHIFT_CH14_LOW_TH_8814B 0
+#define BIT_MASK_CH14_LOW_TH_8814B 0xfff
+#define BIT_CH14_LOW_TH_8814B(x) \
+ (((x) & BIT_MASK_CH14_LOW_TH_8814B) << BIT_SHIFT_CH14_LOW_TH_8814B)
+#define BITS_CH14_LOW_TH_8814B \
+ (BIT_MASK_CH14_LOW_TH_8814B << BIT_SHIFT_CH14_LOW_TH_8814B)
+#define BIT_CLEAR_CH14_LOW_TH_8814B(x) ((x) & (~BITS_CH14_LOW_TH_8814B))
+#define BIT_GET_CH14_LOW_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_CH14_LOW_TH_8814B) & BIT_MASK_CH14_LOW_TH_8814B)
+#define BIT_SET_CH14_LOW_TH_8814B(x, v) \
+ (BIT_CLEAR_CH14_LOW_TH_8814B(x) | BIT_CH14_LOW_TH_8814B(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_15_8814B */
+#define BIT_CH15_INT_EN_8814B BIT(31)
+
+#define BIT_SHIFT_CH15_HIGH_TH_8814B 16
+#define BIT_MASK_CH15_HIGH_TH_8814B 0xfff
+#define BIT_CH15_HIGH_TH_8814B(x) \
+ (((x) & BIT_MASK_CH15_HIGH_TH_8814B) << BIT_SHIFT_CH15_HIGH_TH_8814B)
+#define BITS_CH15_HIGH_TH_8814B \
+ (BIT_MASK_CH15_HIGH_TH_8814B << BIT_SHIFT_CH15_HIGH_TH_8814B)
+#define BIT_CLEAR_CH15_HIGH_TH_8814B(x) ((x) & (~BITS_CH15_HIGH_TH_8814B))
+#define BIT_GET_CH15_HIGH_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_CH15_HIGH_TH_8814B) & BIT_MASK_CH15_HIGH_TH_8814B)
+#define BIT_SET_CH15_HIGH_TH_8814B(x, v) \
+ (BIT_CLEAR_CH15_HIGH_TH_8814B(x) | BIT_CH15_HIGH_TH_8814B(v))
+
+#define BIT_SHIFT_CH15_LOW_TH_8814B 0
+#define BIT_MASK_CH15_LOW_TH_8814B 0xfff
+#define BIT_CH15_LOW_TH_8814B(x) \
+ (((x) & BIT_MASK_CH15_LOW_TH_8814B) << BIT_SHIFT_CH15_LOW_TH_8814B)
+#define BITS_CH15_LOW_TH_8814B \
+ (BIT_MASK_CH15_LOW_TH_8814B << BIT_SHIFT_CH15_LOW_TH_8814B)
+#define BIT_CLEAR_CH15_LOW_TH_8814B(x) ((x) & (~BITS_CH15_LOW_TH_8814B))
+#define BIT_GET_CH15_LOW_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_CH15_LOW_TH_8814B) & BIT_MASK_CH15_LOW_TH_8814B)
+#define BIT_SET_CH15_LOW_TH_8814B(x, v) \
+ (BIT_CLEAR_CH15_LOW_TH_8814B(x) | BIT_CH15_LOW_TH_8814B(v))
+
+/* 2 REG_TXPAGE_INT_CTRL_16_8814B */
+#define BIT_CH16_INT_EN_8814B BIT(31)
+
+#define BIT_SHIFT_CH16_HIGH_TH_8814B 16
+#define BIT_MASK_CH16_HIGH_TH_8814B 0xfff
+#define BIT_CH16_HIGH_TH_8814B(x) \
+ (((x) & BIT_MASK_CH16_HIGH_TH_8814B) << BIT_SHIFT_CH16_HIGH_TH_8814B)
+#define BITS_CH16_HIGH_TH_8814B \
+ (BIT_MASK_CH16_HIGH_TH_8814B << BIT_SHIFT_CH16_HIGH_TH_8814B)
+#define BIT_CLEAR_CH16_HIGH_TH_8814B(x) ((x) & (~BITS_CH16_HIGH_TH_8814B))
+#define BIT_GET_CH16_HIGH_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_CH16_HIGH_TH_8814B) & BIT_MASK_CH16_HIGH_TH_8814B)
+#define BIT_SET_CH16_HIGH_TH_8814B(x, v) \
+ (BIT_CLEAR_CH16_HIGH_TH_8814B(x) | BIT_CH16_HIGH_TH_8814B(v))
+
+#define BIT_SHIFT_CH16_LOW_TH_8814B 0
+#define BIT_MASK_CH16_LOW_TH_8814B 0xfff
+#define BIT_CH16_LOW_TH_8814B(x) \
+ (((x) & BIT_MASK_CH16_LOW_TH_8814B) << BIT_SHIFT_CH16_LOW_TH_8814B)
+#define BITS_CH16_LOW_TH_8814B \
+ (BIT_MASK_CH16_LOW_TH_8814B << BIT_SHIFT_CH16_LOW_TH_8814B)
+#define BIT_CLEAR_CH16_LOW_TH_8814B(x) ((x) & (~BITS_CH16_LOW_TH_8814B))
+#define BIT_GET_CH16_LOW_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_CH16_LOW_TH_8814B) & BIT_MASK_CH16_LOW_TH_8814B)
+#define BIT_SET_CH16_LOW_TH_8814B(x, v) \
+ (BIT_CLEAR_CH16_LOW_TH_8814B(x) | BIT_CH16_LOW_TH_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_PCIE_CTRL_8814B */
+#define BIT_PCIEIO_PERSTB_SEL_8814B BIT(31)
+
+#define BIT_SHIFT_PCIE_MAX_RXDMA_8814B 28
+#define BIT_MASK_PCIE_MAX_RXDMA_8814B 0x7
+#define BIT_PCIE_MAX_RXDMA_8814B(x) \
+ (((x) & BIT_MASK_PCIE_MAX_RXDMA_8814B) \
+ << BIT_SHIFT_PCIE_MAX_RXDMA_8814B)
+#define BITS_PCIE_MAX_RXDMA_8814B \
+ (BIT_MASK_PCIE_MAX_RXDMA_8814B << BIT_SHIFT_PCIE_MAX_RXDMA_8814B)
+#define BIT_CLEAR_PCIE_MAX_RXDMA_8814B(x) ((x) & (~BITS_PCIE_MAX_RXDMA_8814B))
+#define BIT_GET_PCIE_MAX_RXDMA_8814B(x) \
+ (((x) >> BIT_SHIFT_PCIE_MAX_RXDMA_8814B) & \
+ BIT_MASK_PCIE_MAX_RXDMA_8814B)
+#define BIT_SET_PCIE_MAX_RXDMA_8814B(x, v) \
+ (BIT_CLEAR_PCIE_MAX_RXDMA_8814B(x) | BIT_PCIE_MAX_RXDMA_8814B(v))
+
+#define BIT_MULRW_8814B BIT(27)
+
+#define BIT_SHIFT_PCIE_MAX_TXDMA_8814B 24
+#define BIT_MASK_PCIE_MAX_TXDMA_8814B 0x7
+#define BIT_PCIE_MAX_TXDMA_8814B(x) \
+ (((x) & BIT_MASK_PCIE_MAX_TXDMA_8814B) \
+ << BIT_SHIFT_PCIE_MAX_TXDMA_8814B)
+#define BITS_PCIE_MAX_TXDMA_8814B \
+ (BIT_MASK_PCIE_MAX_TXDMA_8814B << BIT_SHIFT_PCIE_MAX_TXDMA_8814B)
+#define BIT_CLEAR_PCIE_MAX_TXDMA_8814B(x) ((x) & (~BITS_PCIE_MAX_TXDMA_8814B))
+#define BIT_GET_PCIE_MAX_TXDMA_8814B(x) \
+ (((x) >> BIT_SHIFT_PCIE_MAX_TXDMA_8814B) & \
+ BIT_MASK_PCIE_MAX_TXDMA_8814B)
+#define BIT_SET_PCIE_MAX_TXDMA_8814B(x, v) \
+ (BIT_CLEAR_PCIE_MAX_TXDMA_8814B(x) | BIT_PCIE_MAX_TXDMA_8814B(v))
+
+#define BIT_PWR_SCALE_START_PS_8814B BIT(23)
+#define BIT_EN_CPL_TIMEOUT_PS_8814B BIT(22)
+#define BIT_REG_TXDMA_FAIL_PS_8814B BIT(21)
+#define BIT_PCIE_RST_TRXDMA_INTF_8814B BIT(20)
+#define BIT_EN_HWENTR_L1_8814B BIT(19)
+#define BIT_EN_ADV_CLKGATE_8814B BIT(18)
+#define BIT_PCIE_EN_SWENT_L23_8814B BIT(17)
+#define BIT_PCIE_EN_HWEXT_L1_8814B BIT(16)
+#define BIT_STOP_P0_MPRT_BCNQ4_8814B BIT(6)
+#define BIT_STOP_P0_MPRT_BCNQ3_8814B BIT(4)
+#define BIT_STOP_P0_MPRT_BCNQ2_8814B BIT(2)
+#define BIT_STOP_P0_MPRT_BCNQ1_8814B BIT(0)
+
+/* 2 REG_ACH_CTRL_8814B */
+#define BIT_STOP_P0HIQ19_8814B BIT(27)
+#define BIT_STOP_P0HIQ18_8814B BIT(26)
+#define BIT_STOP_P0HIQ17_8814B BIT(25)
+#define BIT_STOP_P0HIQ16_8814B BIT(24)
+#define BIT_RX_CLOSE_EN_V1_8814B BIT(21)
+#define BIT_STOP_FWCMDQ_8814B BIT(20)
+#define BIT_STOP_P0BCNQ_8814B BIT(18)
+#define BIT_STOP_P0MGQ_8814B BIT(16)
+#define BIT_STOP_ACH13_8814B BIT(15)
+#define BIT_STOP_ACH12_8814B BIT(14)
+#define BIT_STOP_ACH11_8814B BIT(13)
+#define BIT_STOP_ACH10_8814B BIT(12)
+#define BIT_STOP_ACH9_8814B BIT(11)
+#define BIT_STOP_ACH8_8814B BIT(10)
+#define BIT_STOP_ACH7_8814B BIT(9)
+#define BIT_STOP_ACH6_8814B BIT(8)
+#define BIT_STOP_ACH5_8814B BIT(7)
+#define BIT_STOP_ACH4_8814B BIT(6)
+#define BIT_STOP_ACH3_8814B BIT(5)
+#define BIT_STOP_ACH2_8814B BIT(4)
+#define BIT_STOP_ACH1_8814B BIT(3)
+#define BIT_STOP_ACH0_8814B BIT(2)
+#define BIT_STOP_P0RX_8814B BIT(0)
+
+/* 2 REG_HIQ_CTRL_8814B */
+#define BIT_STOP_P0HIQ15_8814B BIT(15)
+#define BIT_STOP_P0HIQ14_8814B BIT(14)
+#define BIT_STOP_P0HIQ13_8814B BIT(13)
+#define BIT_STOP_P0HIQ12_8814B BIT(12)
+#define BIT_STOP_P0HIQ11_8814B BIT(11)
+#define BIT_STOP_P0HIQ10_8814B BIT(10)
+#define BIT_STOP_P0HIQ9_8814B BIT(9)
+#define BIT_STOP_P0HIQ8_8814B BIT(8)
+#define BIT_STOP_P0HIQ7_8814B BIT(7)
+#define BIT_STOP_P0HIQ6_8814B BIT(6)
+#define BIT_STOP_P0HIQ5_8814B BIT(5)
+#define BIT_STOP_P0HIQ4_8814B BIT(4)
+#define BIT_STOP_P0HIQ3_8814B BIT(3)
+#define BIT_STOP_P0HIQ2_8814B BIT(2)
+#define BIT_STOP_P0HIQ1_8814B BIT(1)
+#define BIT_STOP_P0HIQ0_8814B BIT(0)
+
+/* 2 REG_INT_MIG_V1_8814B */
+
+#define BIT_SHIFT_TXTTIMER_MATCH_NUM_8814B 28
+#define BIT_MASK_TXTTIMER_MATCH_NUM_8814B 0xf
+#define BIT_TXTTIMER_MATCH_NUM_8814B(x) \
+ (((x) & BIT_MASK_TXTTIMER_MATCH_NUM_8814B) \
+ << BIT_SHIFT_TXTTIMER_MATCH_NUM_8814B)
+#define BITS_TXTTIMER_MATCH_NUM_8814B \
+ (BIT_MASK_TXTTIMER_MATCH_NUM_8814B \
+ << BIT_SHIFT_TXTTIMER_MATCH_NUM_8814B)
+#define BIT_CLEAR_TXTTIMER_MATCH_NUM_8814B(x) \
+ ((x) & (~BITS_TXTTIMER_MATCH_NUM_8814B))
+#define BIT_GET_TXTTIMER_MATCH_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM_8814B) & \
+ BIT_MASK_TXTTIMER_MATCH_NUM_8814B)
+#define BIT_SET_TXTTIMER_MATCH_NUM_8814B(x, v) \
+ (BIT_CLEAR_TXTTIMER_MATCH_NUM_8814B(x) | \
+ BIT_TXTTIMER_MATCH_NUM_8814B(v))
+
+#define BIT_SHIFT_TXPKT_NUM_MATCH_8814B 24
+#define BIT_MASK_TXPKT_NUM_MATCH_8814B 0xf
+#define BIT_TXPKT_NUM_MATCH_8814B(x) \
+ (((x) & BIT_MASK_TXPKT_NUM_MATCH_8814B) \
+ << BIT_SHIFT_TXPKT_NUM_MATCH_8814B)
+#define BITS_TXPKT_NUM_MATCH_8814B \
+ (BIT_MASK_TXPKT_NUM_MATCH_8814B << BIT_SHIFT_TXPKT_NUM_MATCH_8814B)
+#define BIT_CLEAR_TXPKT_NUM_MATCH_8814B(x) ((x) & (~BITS_TXPKT_NUM_MATCH_8814B))
+#define BIT_GET_TXPKT_NUM_MATCH_8814B(x) \
+ (((x) >> BIT_SHIFT_TXPKT_NUM_MATCH_8814B) & \
+ BIT_MASK_TXPKT_NUM_MATCH_8814B)
+#define BIT_SET_TXPKT_NUM_MATCH_8814B(x, v) \
+ (BIT_CLEAR_TXPKT_NUM_MATCH_8814B(x) | BIT_TXPKT_NUM_MATCH_8814B(v))
+
+#define BIT_SHIFT_RXTTIMER_MATCH_NUM_8814B 20
+#define BIT_MASK_RXTTIMER_MATCH_NUM_8814B 0xf
+#define BIT_RXTTIMER_MATCH_NUM_8814B(x) \
+ (((x) & BIT_MASK_RXTTIMER_MATCH_NUM_8814B) \
+ << BIT_SHIFT_RXTTIMER_MATCH_NUM_8814B)
+#define BITS_RXTTIMER_MATCH_NUM_8814B \
+ (BIT_MASK_RXTTIMER_MATCH_NUM_8814B \
+ << BIT_SHIFT_RXTTIMER_MATCH_NUM_8814B)
+#define BIT_CLEAR_RXTTIMER_MATCH_NUM_8814B(x) \
+ ((x) & (~BITS_RXTTIMER_MATCH_NUM_8814B))
+#define BIT_GET_RXTTIMER_MATCH_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM_8814B) & \
+ BIT_MASK_RXTTIMER_MATCH_NUM_8814B)
+#define BIT_SET_RXTTIMER_MATCH_NUM_8814B(x, v) \
+ (BIT_CLEAR_RXTTIMER_MATCH_NUM_8814B(x) | \
+ BIT_RXTTIMER_MATCH_NUM_8814B(v))
+
+#define BIT_SHIFT_RXPKT_NUM_MATCH_8814B 16
+#define BIT_MASK_RXPKT_NUM_MATCH_8814B 0xf
+#define BIT_RXPKT_NUM_MATCH_8814B(x) \
+ (((x) & BIT_MASK_RXPKT_NUM_MATCH_8814B) \
+ << BIT_SHIFT_RXPKT_NUM_MATCH_8814B)
+#define BITS_RXPKT_NUM_MATCH_8814B \
+ (BIT_MASK_RXPKT_NUM_MATCH_8814B << BIT_SHIFT_RXPKT_NUM_MATCH_8814B)
+#define BIT_CLEAR_RXPKT_NUM_MATCH_8814B(x) ((x) & (~BITS_RXPKT_NUM_MATCH_8814B))
+#define BIT_GET_RXPKT_NUM_MATCH_8814B(x) \
+ (((x) >> BIT_SHIFT_RXPKT_NUM_MATCH_8814B) & \
+ BIT_MASK_RXPKT_NUM_MATCH_8814B)
+#define BIT_SET_RXPKT_NUM_MATCH_8814B(x, v) \
+ (BIT_CLEAR_RXPKT_NUM_MATCH_8814B(x) | BIT_RXPKT_NUM_MATCH_8814B(v))
+
+#define BIT_SHIFT_MIGRATE_TIMER_8814B 0
+#define BIT_MASK_MIGRATE_TIMER_8814B 0xffff
+#define BIT_MIGRATE_TIMER_8814B(x) \
+ (((x) & BIT_MASK_MIGRATE_TIMER_8814B) << BIT_SHIFT_MIGRATE_TIMER_8814B)
+#define BITS_MIGRATE_TIMER_8814B \
+ (BIT_MASK_MIGRATE_TIMER_8814B << BIT_SHIFT_MIGRATE_TIMER_8814B)
+#define BIT_CLEAR_MIGRATE_TIMER_8814B(x) ((x) & (~BITS_MIGRATE_TIMER_8814B))
+#define BIT_GET_MIGRATE_TIMER_8814B(x) \
+ (((x) >> BIT_SHIFT_MIGRATE_TIMER_8814B) & BIT_MASK_MIGRATE_TIMER_8814B)
+#define BIT_SET_MIGRATE_TIMER_8814B(x, v) \
+ (BIT_CLEAR_MIGRATE_TIMER_8814B(x) | BIT_MIGRATE_TIMER_8814B(v))
+
+/* 2 REG_P0MGQ_TXBD_DESA_L_8814B */
+
+/* 2 REG_P0MGQ_TXBD_DESA_H_8814B */
+
+/* 2 REG_ACH0_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_ACH0_TXBD_DESA_L_8814B 0
+#define BIT_MASK_ACH0_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_ACH0_TXBD_DESA_L_8814B(x) \
+ (((x) & BIT_MASK_ACH0_TXBD_DESA_L_8814B) \
+ << BIT_SHIFT_ACH0_TXBD_DESA_L_8814B)
+#define BITS_ACH0_TXBD_DESA_L_8814B \
+ (BIT_MASK_ACH0_TXBD_DESA_L_8814B << BIT_SHIFT_ACH0_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_ACH0_TXBD_DESA_L_8814B(x) \
+ ((x) & (~BITS_ACH0_TXBD_DESA_L_8814B))
+#define BIT_GET_ACH0_TXBD_DESA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH0_TXBD_DESA_L_8814B) & \
+ BIT_MASK_ACH0_TXBD_DESA_L_8814B)
+#define BIT_SET_ACH0_TXBD_DESA_L_8814B(x, v) \
+ (BIT_CLEAR_ACH0_TXBD_DESA_L_8814B(x) | BIT_ACH0_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_ACH0_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_ACH0_TXBD_DESA_H_8814B 0
+#define BIT_MASK_ACH0_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_ACH0_TXBD_DESA_H_8814B(x) \
+ (((x) & BIT_MASK_ACH0_TXBD_DESA_H_8814B) \
+ << BIT_SHIFT_ACH0_TXBD_DESA_H_8814B)
+#define BITS_ACH0_TXBD_DESA_H_8814B \
+ (BIT_MASK_ACH0_TXBD_DESA_H_8814B << BIT_SHIFT_ACH0_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_ACH0_TXBD_DESA_H_8814B(x) \
+ ((x) & (~BITS_ACH0_TXBD_DESA_H_8814B))
+#define BIT_GET_ACH0_TXBD_DESA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH0_TXBD_DESA_H_8814B) & \
+ BIT_MASK_ACH0_TXBD_DESA_H_8814B)
+#define BIT_SET_ACH0_TXBD_DESA_H_8814B(x, v) \
+ (BIT_CLEAR_ACH0_TXBD_DESA_H_8814B(x) | BIT_ACH0_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_ACH1_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_ACH1_TXBD_DESA_L_8814B 0
+#define BIT_MASK_ACH1_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_ACH1_TXBD_DESA_L_8814B(x) \
+ (((x) & BIT_MASK_ACH1_TXBD_DESA_L_8814B) \
+ << BIT_SHIFT_ACH1_TXBD_DESA_L_8814B)
+#define BITS_ACH1_TXBD_DESA_L_8814B \
+ (BIT_MASK_ACH1_TXBD_DESA_L_8814B << BIT_SHIFT_ACH1_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_ACH1_TXBD_DESA_L_8814B(x) \
+ ((x) & (~BITS_ACH1_TXBD_DESA_L_8814B))
+#define BIT_GET_ACH1_TXBD_DESA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH1_TXBD_DESA_L_8814B) & \
+ BIT_MASK_ACH1_TXBD_DESA_L_8814B)
+#define BIT_SET_ACH1_TXBD_DESA_L_8814B(x, v) \
+ (BIT_CLEAR_ACH1_TXBD_DESA_L_8814B(x) | BIT_ACH1_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_ACH1_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_ACH1_TXBD_DESA_H_8814B 0
+#define BIT_MASK_ACH1_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_ACH1_TXBD_DESA_H_8814B(x) \
+ (((x) & BIT_MASK_ACH1_TXBD_DESA_H_8814B) \
+ << BIT_SHIFT_ACH1_TXBD_DESA_H_8814B)
+#define BITS_ACH1_TXBD_DESA_H_8814B \
+ (BIT_MASK_ACH1_TXBD_DESA_H_8814B << BIT_SHIFT_ACH1_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_ACH1_TXBD_DESA_H_8814B(x) \
+ ((x) & (~BITS_ACH1_TXBD_DESA_H_8814B))
+#define BIT_GET_ACH1_TXBD_DESA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH1_TXBD_DESA_H_8814B) & \
+ BIT_MASK_ACH1_TXBD_DESA_H_8814B)
+#define BIT_SET_ACH1_TXBD_DESA_H_8814B(x, v) \
+ (BIT_CLEAR_ACH1_TXBD_DESA_H_8814B(x) | BIT_ACH1_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_ACH2_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_ACH2_TXBD_DESA_L_8814B 0
+#define BIT_MASK_ACH2_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_ACH2_TXBD_DESA_L_8814B(x) \
+ (((x) & BIT_MASK_ACH2_TXBD_DESA_L_8814B) \
+ << BIT_SHIFT_ACH2_TXBD_DESA_L_8814B)
+#define BITS_ACH2_TXBD_DESA_L_8814B \
+ (BIT_MASK_ACH2_TXBD_DESA_L_8814B << BIT_SHIFT_ACH2_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_ACH2_TXBD_DESA_L_8814B(x) \
+ ((x) & (~BITS_ACH2_TXBD_DESA_L_8814B))
+#define BIT_GET_ACH2_TXBD_DESA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH2_TXBD_DESA_L_8814B) & \
+ BIT_MASK_ACH2_TXBD_DESA_L_8814B)
+#define BIT_SET_ACH2_TXBD_DESA_L_8814B(x, v) \
+ (BIT_CLEAR_ACH2_TXBD_DESA_L_8814B(x) | BIT_ACH2_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_ACH2_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_ACH2_TXBD_DESA_H_8814B 0
+#define BIT_MASK_ACH2_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_ACH2_TXBD_DESA_H_8814B(x) \
+ (((x) & BIT_MASK_ACH2_TXBD_DESA_H_8814B) \
+ << BIT_SHIFT_ACH2_TXBD_DESA_H_8814B)
+#define BITS_ACH2_TXBD_DESA_H_8814B \
+ (BIT_MASK_ACH2_TXBD_DESA_H_8814B << BIT_SHIFT_ACH2_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_ACH2_TXBD_DESA_H_8814B(x) \
+ ((x) & (~BITS_ACH2_TXBD_DESA_H_8814B))
+#define BIT_GET_ACH2_TXBD_DESA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH2_TXBD_DESA_H_8814B) & \
+ BIT_MASK_ACH2_TXBD_DESA_H_8814B)
+#define BIT_SET_ACH2_TXBD_DESA_H_8814B(x, v) \
+ (BIT_CLEAR_ACH2_TXBD_DESA_H_8814B(x) | BIT_ACH2_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_ACH3_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_ACH3_TXBD_DESA_L_8814B 0
+#define BIT_MASK_ACH3_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_ACH3_TXBD_DESA_L_8814B(x) \
+ (((x) & BIT_MASK_ACH3_TXBD_DESA_L_8814B) \
+ << BIT_SHIFT_ACH3_TXBD_DESA_L_8814B)
+#define BITS_ACH3_TXBD_DESA_L_8814B \
+ (BIT_MASK_ACH3_TXBD_DESA_L_8814B << BIT_SHIFT_ACH3_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_ACH3_TXBD_DESA_L_8814B(x) \
+ ((x) & (~BITS_ACH3_TXBD_DESA_L_8814B))
+#define BIT_GET_ACH3_TXBD_DESA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH3_TXBD_DESA_L_8814B) & \
+ BIT_MASK_ACH3_TXBD_DESA_L_8814B)
+#define BIT_SET_ACH3_TXBD_DESA_L_8814B(x, v) \
+ (BIT_CLEAR_ACH3_TXBD_DESA_L_8814B(x) | BIT_ACH3_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_ACH3_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_ACH3_TXBD_DESA_H_8814B 0
+#define BIT_MASK_ACH3_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_ACH3_TXBD_DESA_H_8814B(x) \
+ (((x) & BIT_MASK_ACH3_TXBD_DESA_H_8814B) \
+ << BIT_SHIFT_ACH3_TXBD_DESA_H_8814B)
+#define BITS_ACH3_TXBD_DESA_H_8814B \
+ (BIT_MASK_ACH3_TXBD_DESA_H_8814B << BIT_SHIFT_ACH3_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_ACH3_TXBD_DESA_H_8814B(x) \
+ ((x) & (~BITS_ACH3_TXBD_DESA_H_8814B))
+#define BIT_GET_ACH3_TXBD_DESA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH3_TXBD_DESA_H_8814B) & \
+ BIT_MASK_ACH3_TXBD_DESA_H_8814B)
+#define BIT_SET_ACH3_TXBD_DESA_H_8814B(x, v) \
+ (BIT_CLEAR_ACH3_TXBD_DESA_H_8814B(x) | BIT_ACH3_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_P0RXQ_RXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_P0RXQ_RXBD_DESA_L_8814B 0
+#define BIT_MASK_P0RXQ_RXBD_DESA_L_8814B 0xffffffffL
+#define BIT_P0RXQ_RXBD_DESA_L_8814B(x) \
+ (((x) & BIT_MASK_P0RXQ_RXBD_DESA_L_8814B) \
+ << BIT_SHIFT_P0RXQ_RXBD_DESA_L_8814B)
+#define BITS_P0RXQ_RXBD_DESA_L_8814B \
+ (BIT_MASK_P0RXQ_RXBD_DESA_L_8814B << BIT_SHIFT_P0RXQ_RXBD_DESA_L_8814B)
+#define BIT_CLEAR_P0RXQ_RXBD_DESA_L_8814B(x) \
+ ((x) & (~BITS_P0RXQ_RXBD_DESA_L_8814B))
+#define BIT_GET_P0RXQ_RXBD_DESA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_P0RXQ_RXBD_DESA_L_8814B) & \
+ BIT_MASK_P0RXQ_RXBD_DESA_L_8814B)
+#define BIT_SET_P0RXQ_RXBD_DESA_L_8814B(x, v) \
+ (BIT_CLEAR_P0RXQ_RXBD_DESA_L_8814B(x) | BIT_P0RXQ_RXBD_DESA_L_8814B(v))
+
+/* 2 REG_P0RXQ_RXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_P0RXQ_RXBD_DESA_H_8814B 0
+#define BIT_MASK_P0RXQ_RXBD_DESA_H_8814B 0xffffffffL
+#define BIT_P0RXQ_RXBD_DESA_H_8814B(x) \
+ (((x) & BIT_MASK_P0RXQ_RXBD_DESA_H_8814B) \
+ << BIT_SHIFT_P0RXQ_RXBD_DESA_H_8814B)
+#define BITS_P0RXQ_RXBD_DESA_H_8814B \
+ (BIT_MASK_P0RXQ_RXBD_DESA_H_8814B << BIT_SHIFT_P0RXQ_RXBD_DESA_H_8814B)
+#define BIT_CLEAR_P0RXQ_RXBD_DESA_H_8814B(x) \
+ ((x) & (~BITS_P0RXQ_RXBD_DESA_H_8814B))
+#define BIT_GET_P0RXQ_RXBD_DESA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_P0RXQ_RXBD_DESA_H_8814B) & \
+ BIT_MASK_P0RXQ_RXBD_DESA_H_8814B)
+#define BIT_SET_P0RXQ_RXBD_DESA_H_8814B(x, v) \
+ (BIT_CLEAR_P0RXQ_RXBD_DESA_H_8814B(x) | BIT_P0RXQ_RXBD_DESA_H_8814B(v))
+
+/* 2 REG_P0BCNQ_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_P0BCNQ_TXBD_DESA_L_8814B 0
+#define BIT_MASK_P0BCNQ_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_P0BCNQ_TXBD_DESA_L_8814B(x) \
+ (((x) & BIT_MASK_P0BCNQ_TXBD_DESA_L_8814B) \
+ << BIT_SHIFT_P0BCNQ_TXBD_DESA_L_8814B)
+#define BITS_P0BCNQ_TXBD_DESA_L_8814B \
+ (BIT_MASK_P0BCNQ_TXBD_DESA_L_8814B \
+ << BIT_SHIFT_P0BCNQ_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_P0BCNQ_TXBD_DESA_L_8814B(x) \
+ ((x) & (~BITS_P0BCNQ_TXBD_DESA_L_8814B))
+#define BIT_GET_P0BCNQ_TXBD_DESA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_P0BCNQ_TXBD_DESA_L_8814B) & \
+ BIT_MASK_P0BCNQ_TXBD_DESA_L_8814B)
+#define BIT_SET_P0BCNQ_TXBD_DESA_L_8814B(x, v) \
+ (BIT_CLEAR_P0BCNQ_TXBD_DESA_L_8814B(x) | \
+ BIT_P0BCNQ_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_P0BCNQ_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_P0BCNQ_TXBD_DESA_H_8814B 0
+#define BIT_MASK_P0BCNQ_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_P0BCNQ_TXBD_DESA_H_8814B(x) \
+ (((x) & BIT_MASK_P0BCNQ_TXBD_DESA_H_8814B) \
+ << BIT_SHIFT_P0BCNQ_TXBD_DESA_H_8814B)
+#define BITS_P0BCNQ_TXBD_DESA_H_8814B \
+ (BIT_MASK_P0BCNQ_TXBD_DESA_H_8814B \
+ << BIT_SHIFT_P0BCNQ_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_P0BCNQ_TXBD_DESA_H_8814B(x) \
+ ((x) & (~BITS_P0BCNQ_TXBD_DESA_H_8814B))
+#define BIT_GET_P0BCNQ_TXBD_DESA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_P0BCNQ_TXBD_DESA_H_8814B) & \
+ BIT_MASK_P0BCNQ_TXBD_DESA_H_8814B)
+#define BIT_SET_P0BCNQ_TXBD_DESA_H_8814B(x, v) \
+ (BIT_CLEAR_P0BCNQ_TXBD_DESA_H_8814B(x) | \
+ BIT_P0BCNQ_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_FWCMDQ_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_FWCMDQ_TXBD_DESA_L_8814B 0
+#define BIT_MASK_FWCMDQ_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_FWCMDQ_TXBD_DESA_L_8814B(x) \
+ (((x) & BIT_MASK_FWCMDQ_TXBD_DESA_L_8814B) \
+ << BIT_SHIFT_FWCMDQ_TXBD_DESA_L_8814B)
+#define BITS_FWCMDQ_TXBD_DESA_L_8814B \
+ (BIT_MASK_FWCMDQ_TXBD_DESA_L_8814B \
+ << BIT_SHIFT_FWCMDQ_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_FWCMDQ_TXBD_DESA_L_8814B(x) \
+ ((x) & (~BITS_FWCMDQ_TXBD_DESA_L_8814B))
+#define BIT_GET_FWCMDQ_TXBD_DESA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_FWCMDQ_TXBD_DESA_L_8814B) & \
+ BIT_MASK_FWCMDQ_TXBD_DESA_L_8814B)
+#define BIT_SET_FWCMDQ_TXBD_DESA_L_8814B(x, v) \
+ (BIT_CLEAR_FWCMDQ_TXBD_DESA_L_8814B(x) | \
+ BIT_FWCMDQ_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_FWCMDQ_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_FWCMDQ_TXBD_DESA_H_8814B 0
+#define BIT_MASK_FWCMDQ_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_FWCMDQ_TXBD_DESA_H_8814B(x) \
+ (((x) & BIT_MASK_FWCMDQ_TXBD_DESA_H_8814B) \
+ << BIT_SHIFT_FWCMDQ_TXBD_DESA_H_8814B)
+#define BITS_FWCMDQ_TXBD_DESA_H_8814B \
+ (BIT_MASK_FWCMDQ_TXBD_DESA_H_8814B \
+ << BIT_SHIFT_FWCMDQ_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_FWCMDQ_TXBD_DESA_H_8814B(x) \
+ ((x) & (~BITS_FWCMDQ_TXBD_DESA_H_8814B))
+#define BIT_GET_FWCMDQ_TXBD_DESA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_FWCMDQ_TXBD_DESA_H_8814B) & \
+ BIT_MASK_FWCMDQ_TXBD_DESA_H_8814B)
+#define BIT_SET_FWCMDQ_TXBD_DESA_H_8814B(x, v) \
+ (BIT_CLEAR_FWCMDQ_TXBD_DESA_H_8814B(x) | \
+ BIT_FWCMDQ_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_PCIE_HRPWM1_HCPWM1_DCPU_8814B */
+
+#define BIT_SHIFT_PCIE_HCPWM1_DCPU_8814B 16
+#define BIT_MASK_PCIE_HCPWM1_DCPU_8814B 0xff
+#define BIT_PCIE_HCPWM1_DCPU_8814B(x) \
+ (((x) & BIT_MASK_PCIE_HCPWM1_DCPU_8814B) \
+ << BIT_SHIFT_PCIE_HCPWM1_DCPU_8814B)
+#define BITS_PCIE_HCPWM1_DCPU_8814B \
+ (BIT_MASK_PCIE_HCPWM1_DCPU_8814B << BIT_SHIFT_PCIE_HCPWM1_DCPU_8814B)
+#define BIT_CLEAR_PCIE_HCPWM1_DCPU_8814B(x) \
+ ((x) & (~BITS_PCIE_HCPWM1_DCPU_8814B))
+#define BIT_GET_PCIE_HCPWM1_DCPU_8814B(x) \
+ (((x) >> BIT_SHIFT_PCIE_HCPWM1_DCPU_8814B) & \
+ BIT_MASK_PCIE_HCPWM1_DCPU_8814B)
+#define BIT_SET_PCIE_HCPWM1_DCPU_8814B(x, v) \
+ (BIT_CLEAR_PCIE_HCPWM1_DCPU_8814B(x) | BIT_PCIE_HCPWM1_DCPU_8814B(v))
+
+#define BIT_SHIFT_PCIE_HRPWM1_DCPU_8814B 8
+#define BIT_MASK_PCIE_HRPWM1_DCPU_8814B 0xff
+#define BIT_PCIE_HRPWM1_DCPU_8814B(x) \
+ (((x) & BIT_MASK_PCIE_HRPWM1_DCPU_8814B) \
+ << BIT_SHIFT_PCIE_HRPWM1_DCPU_8814B)
+#define BITS_PCIE_HRPWM1_DCPU_8814B \
+ (BIT_MASK_PCIE_HRPWM1_DCPU_8814B << BIT_SHIFT_PCIE_HRPWM1_DCPU_8814B)
+#define BIT_CLEAR_PCIE_HRPWM1_DCPU_8814B(x) \
+ ((x) & (~BITS_PCIE_HRPWM1_DCPU_8814B))
+#define BIT_GET_PCIE_HRPWM1_DCPU_8814B(x) \
+ (((x) >> BIT_SHIFT_PCIE_HRPWM1_DCPU_8814B) & \
+ BIT_MASK_PCIE_HRPWM1_DCPU_8814B)
+#define BIT_SET_PCIE_HRPWM1_DCPU_8814B(x, v) \
+ (BIT_CLEAR_PCIE_HRPWM1_DCPU_8814B(x) | BIT_PCIE_HRPWM1_DCPU_8814B(v))
+
+/* 2 REG_P0_MPRT_BCNQ_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L_8814B 0
+#define BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_P0_MPRT_BCNQ_TXBD_DESA_L_8814B(x) \
+ (((x) & BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L_8814B) \
+ << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L_8814B)
+#define BITS_P0_MPRT_BCNQ_TXBD_DESA_L_8814B \
+ (BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L_8814B \
+ << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_L_8814B(x) \
+ ((x) & (~BITS_P0_MPRT_BCNQ_TXBD_DESA_L_8814B))
+#define BIT_GET_P0_MPRT_BCNQ_TXBD_DESA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_L_8814B) & \
+ BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_L_8814B)
+#define BIT_SET_P0_MPRT_BCNQ_TXBD_DESA_L_8814B(x, v) \
+ (BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_L_8814B(x) | \
+ BIT_P0_MPRT_BCNQ_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_P0_MPRT_BCNQ_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H_8814B 0
+#define BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_P0_MPRT_BCNQ_TXBD_DESA_H_8814B(x) \
+ (((x) & BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H_8814B) \
+ << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H_8814B)
+#define BITS_P0_MPRT_BCNQ_TXBD_DESA_H_8814B \
+ (BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H_8814B \
+ << BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_H_8814B(x) \
+ ((x) & (~BITS_P0_MPRT_BCNQ_TXBD_DESA_H_8814B))
+#define BIT_GET_P0_MPRT_BCNQ_TXBD_DESA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_P0_MPRT_BCNQ_TXBD_DESA_H_8814B) & \
+ BIT_MASK_P0_MPRT_BCNQ_TXBD_DESA_H_8814B)
+#define BIT_SET_P0_MPRT_BCNQ_TXBD_DESA_H_8814B(x, v) \
+ (BIT_CLEAR_P0_MPRT_BCNQ_TXBD_DESA_H_8814B(x) | \
+ BIT_P0_MPRT_BCNQ_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_P0_MPRT_BCNQ_TXRXBD_NUM_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE_8814B 13
+#define BIT_MASK_P0_MPRT_BCNQ_DESC_MODE_8814B 0x3
+#define BIT_P0_MPRT_BCNQ_DESC_MODE_8814B(x) \
+ (((x) & BIT_MASK_P0_MPRT_BCNQ_DESC_MODE_8814B) \
+ << BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE_8814B)
+#define BITS_P0_MPRT_BCNQ_DESC_MODE_8814B \
+ (BIT_MASK_P0_MPRT_BCNQ_DESC_MODE_8814B \
+ << BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE_8814B)
+#define BIT_CLEAR_P0_MPRT_BCNQ_DESC_MODE_8814B(x) \
+ ((x) & (~BITS_P0_MPRT_BCNQ_DESC_MODE_8814B))
+#define BIT_GET_P0_MPRT_BCNQ_DESC_MODE_8814B(x) \
+ (((x) >> BIT_SHIFT_P0_MPRT_BCNQ_DESC_MODE_8814B) & \
+ BIT_MASK_P0_MPRT_BCNQ_DESC_MODE_8814B)
+#define BIT_SET_P0_MPRT_BCNQ_DESC_MODE_8814B(x, v) \
+ (BIT_CLEAR_P0_MPRT_BCNQ_DESC_MODE_8814B(x) | \
+ BIT_P0_MPRT_BCNQ_DESC_MODE_8814B(v))
+
+#define BIT_PCIE_P0MPRT_BCNQ4_FLAG_8814B BIT(11)
+#define BIT_PCIE_P0MPRT_BCNQ3_FLAG_8814B BIT(10)
+#define BIT_PCIE_P0MPRT_BCNQ2_FLAG_8814B BIT(9)
+#define BIT_PCIE_P0MPRT_BCNQ1_FLAG_8814B BIT(8)
+#define BIT_EPHY_CAL_DONE_8814B BIT(1)
+#define BIT_RESET_APHY_8814B BIT(0)
+
+/* 2 REG_BD_RWPTR_CLR2_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_CLR_ACH7_HW_IDX_8814B BIT(21)
+#define BIT_CLR_ACH6_HW_IDX_8814B BIT(20)
+#define BIT_CLR_ACH5_HW_IDX_8814B BIT(19)
+#define BIT_CLR_ACH4_HW_IDX_8814B BIT(18)
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_CLR_ACH7_HOST_IDX_8814B BIT(5)
+#define BIT_CLR_ACH6_HOST_IDX_8814B BIT(4)
+#define BIT_CLR_ACH5_HOST_IDX_8814B BIT(3)
+#define BIT_CLR_ACH4_HOST_IDX_8814B BIT(2)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_BD_RWPTR_CLR3_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_CLR_P0HI15Q_HW_IDX_8814B BIT(29)
+#define BIT_CLR_P0HI14Q_HW_IDX_8814B BIT(28)
+#define BIT_CLR_P0HI13Q_HW_IDX_8814B BIT(27)
+#define BIT_CLR_P0HI12Q_HW_IDX_8814B BIT(26)
+#define BIT_CLR_P0HI11Q_HW_IDX_8814B BIT(25)
+#define BIT_CLR_P0HI10Q_HW_IDX_8814B BIT(24)
+#define BIT_CLR_P0HI9Q_HW_IDX_8814B BIT(23)
+#define BIT_CLR_P0HI8Q_HW_IDX_8814B BIT(22)
+#define BIT_CLR_ACH13_HW_IDX_8814B BIT(21)
+#define BIT_CLR_ACH12_HW_IDX_8814B BIT(20)
+#define BIT_CLR_ACH11_HW_IDX_8814B BIT(19)
+#define BIT_CLR_ACH10_HW_IDX_8814B BIT(18)
+#define BIT_CLR_ACH9_HW_IDX_8814B BIT(17)
+#define BIT_CLR_ACH8_HW_IDX_8814B BIT(16)
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_CLR_P0HI15Q_HOST_IDX_8814B BIT(13)
+#define BIT_CLR_P0HI14Q_HOST_IDX_8814B BIT(12)
+#define BIT_CLR_P0HI13Q_HOST_IDX_8814B BIT(11)
+#define BIT_CLR_P0HI12Q_HOST_IDX_8814B BIT(10)
+#define BIT_CLR_P0HI11Q_HOST_IDX_8814B BIT(9)
+#define BIT_CLR_P0HI10Q_HOST_IDX_8814B BIT(8)
+#define BIT_CLR_P0HI9Q_HOST_IDX_8814B BIT(7)
+#define BIT_CLR_P0HI8Q_HOST_IDX_8814B BIT(6)
+#define BIT_CLR_ACH13_HOST_IDX_8814B BIT(5)
+#define BIT_CLR_ACH12_HOST_IDX_8814B BIT(4)
+#define BIT_CLR_ACH11_HOST_IDX_8814B BIT(3)
+#define BIT_CLR_ACH10_HOST_IDX_8814B BIT(2)
+#define BIT_CLR_ACH9_HOST_IDX_8814B BIT(1)
+#define BIT_CLR_ACH8_HOST_IDX_8814B BIT(0)
+
+/* 2 REG_P0MGQ_RXQ_TXRXBD_NUM_8814B */
+#define BIT_SYS_32_64_V1_8814B BIT(31)
+
+#define BIT_SHIFT_P0BCNQ_DESC_MODE_8814B 29
+#define BIT_MASK_P0BCNQ_DESC_MODE_8814B 0x3
+#define BIT_P0BCNQ_DESC_MODE_8814B(x) \
+ (((x) & BIT_MASK_P0BCNQ_DESC_MODE_8814B) \
+ << BIT_SHIFT_P0BCNQ_DESC_MODE_8814B)
+#define BITS_P0BCNQ_DESC_MODE_8814B \
+ (BIT_MASK_P0BCNQ_DESC_MODE_8814B << BIT_SHIFT_P0BCNQ_DESC_MODE_8814B)
+#define BIT_CLEAR_P0BCNQ_DESC_MODE_8814B(x) \
+ ((x) & (~BITS_P0BCNQ_DESC_MODE_8814B))
+#define BIT_GET_P0BCNQ_DESC_MODE_8814B(x) \
+ (((x) >> BIT_SHIFT_P0BCNQ_DESC_MODE_8814B) & \
+ BIT_MASK_P0BCNQ_DESC_MODE_8814B)
+#define BIT_SET_P0BCNQ_DESC_MODE_8814B(x, v) \
+ (BIT_CLEAR_P0BCNQ_DESC_MODE_8814B(x) | BIT_P0BCNQ_DESC_MODE_8814B(v))
+
+#define BIT_PCIE_P0BCNQ_FLAG_8814B BIT(28)
+
+#define BIT_SHIFT_P0RXQ_DESC_NUM_8814B 16
+#define BIT_MASK_P0RXQ_DESC_NUM_8814B 0xfff
+#define BIT_P0RXQ_DESC_NUM_8814B(x) \
+ (((x) & BIT_MASK_P0RXQ_DESC_NUM_8814B) \
+ << BIT_SHIFT_P0RXQ_DESC_NUM_8814B)
+#define BITS_P0RXQ_DESC_NUM_8814B \
+ (BIT_MASK_P0RXQ_DESC_NUM_8814B << BIT_SHIFT_P0RXQ_DESC_NUM_8814B)
+#define BIT_CLEAR_P0RXQ_DESC_NUM_8814B(x) ((x) & (~BITS_P0RXQ_DESC_NUM_8814B))
+#define BIT_GET_P0RXQ_DESC_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_P0RXQ_DESC_NUM_8814B) & \
+ BIT_MASK_P0RXQ_DESC_NUM_8814B)
+#define BIT_SET_P0RXQ_DESC_NUM_8814B(x, v) \
+ (BIT_CLEAR_P0RXQ_DESC_NUM_8814B(x) | BIT_P0RXQ_DESC_NUM_8814B(v))
+
+#define BIT_PCIE_P0MGQ_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_P0MGQ_DESC_MODE_8814B 12
+#define BIT_MASK_P0MGQ_DESC_MODE_8814B 0x3
+#define BIT_P0MGQ_DESC_MODE_8814B(x) \
+ (((x) & BIT_MASK_P0MGQ_DESC_MODE_8814B) \
+ << BIT_SHIFT_P0MGQ_DESC_MODE_8814B)
+#define BITS_P0MGQ_DESC_MODE_8814B \
+ (BIT_MASK_P0MGQ_DESC_MODE_8814B << BIT_SHIFT_P0MGQ_DESC_MODE_8814B)
+#define BIT_CLEAR_P0MGQ_DESC_MODE_8814B(x) ((x) & (~BITS_P0MGQ_DESC_MODE_8814B))
+#define BIT_GET_P0MGQ_DESC_MODE_8814B(x) \
+ (((x) >> BIT_SHIFT_P0MGQ_DESC_MODE_8814B) & \
+ BIT_MASK_P0MGQ_DESC_MODE_8814B)
+#define BIT_SET_P0MGQ_DESC_MODE_8814B(x, v) \
+ (BIT_CLEAR_P0MGQ_DESC_MODE_8814B(x) | BIT_P0MGQ_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0MGQ_DESC_NUM_8814B 0
+#define BIT_MASK_P0MGQ_DESC_NUM_8814B 0xfff
+#define BIT_P0MGQ_DESC_NUM_8814B(x) \
+ (((x) & BIT_MASK_P0MGQ_DESC_NUM_8814B) \
+ << BIT_SHIFT_P0MGQ_DESC_NUM_8814B)
+#define BITS_P0MGQ_DESC_NUM_8814B \
+ (BIT_MASK_P0MGQ_DESC_NUM_8814B << BIT_SHIFT_P0MGQ_DESC_NUM_8814B)
+#define BIT_CLEAR_P0MGQ_DESC_NUM_8814B(x) ((x) & (~BITS_P0MGQ_DESC_NUM_8814B))
+#define BIT_GET_P0MGQ_DESC_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_P0MGQ_DESC_NUM_8814B) & \
+ BIT_MASK_P0MGQ_DESC_NUM_8814B)
+#define BIT_SET_P0MGQ_DESC_NUM_8814B(x, v) \
+ (BIT_CLEAR_P0MGQ_DESC_NUM_8814B(x) | BIT_P0MGQ_DESC_NUM_8814B(v))
+
+/* 2 REG_CHNL_DMA_CFG_8814B */
+#define BIT_TXHCI_EN_8814B BIT(26)
+#define BIT_TXHCI_IDLE_8814B BIT(25)
+#define BIT_DMA_PRI_EN_8814B BIT(24)
+
+/* 2 REG_FWCMDQ_TXBD_NUM_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_PCIE_FWCMDQ_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_FWCMDQ_DESC_MODE_8814B 12
+#define BIT_MASK_FWCMDQ_DESC_MODE_8814B 0x3
+#define BIT_FWCMDQ_DESC_MODE_8814B(x) \
+ (((x) & BIT_MASK_FWCMDQ_DESC_MODE_8814B) \
+ << BIT_SHIFT_FWCMDQ_DESC_MODE_8814B)
+#define BITS_FWCMDQ_DESC_MODE_8814B \
+ (BIT_MASK_FWCMDQ_DESC_MODE_8814B << BIT_SHIFT_FWCMDQ_DESC_MODE_8814B)
+#define BIT_CLEAR_FWCMDQ_DESC_MODE_8814B(x) \
+ ((x) & (~BITS_FWCMDQ_DESC_MODE_8814B))
+#define BIT_GET_FWCMDQ_DESC_MODE_8814B(x) \
+ (((x) >> BIT_SHIFT_FWCMDQ_DESC_MODE_8814B) & \
+ BIT_MASK_FWCMDQ_DESC_MODE_8814B)
+#define BIT_SET_FWCMDQ_DESC_MODE_8814B(x, v) \
+ (BIT_CLEAR_FWCMDQ_DESC_MODE_8814B(x) | BIT_FWCMDQ_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_FWCMDQ_DESC_NUM_8814B 0
+#define BIT_MASK_FWCMDQ_DESC_NUM_8814B 0xfff
+#define BIT_FWCMDQ_DESC_NUM_8814B(x) \
+ (((x) & BIT_MASK_FWCMDQ_DESC_NUM_8814B) \
+ << BIT_SHIFT_FWCMDQ_DESC_NUM_8814B)
+#define BITS_FWCMDQ_DESC_NUM_8814B \
+ (BIT_MASK_FWCMDQ_DESC_NUM_8814B << BIT_SHIFT_FWCMDQ_DESC_NUM_8814B)
+#define BIT_CLEAR_FWCMDQ_DESC_NUM_8814B(x) ((x) & (~BITS_FWCMDQ_DESC_NUM_8814B))
+#define BIT_GET_FWCMDQ_DESC_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_FWCMDQ_DESC_NUM_8814B) & \
+ BIT_MASK_FWCMDQ_DESC_NUM_8814B)
+#define BIT_SET_FWCMDQ_DESC_NUM_8814B(x, v) \
+ (BIT_CLEAR_FWCMDQ_DESC_NUM_8814B(x) | BIT_FWCMDQ_DESC_NUM_8814B(v))
+
+/* 2 REG_ACH0_ACH1_TXBD_NUM_8814B */
+#define BIT_PCIE_ACH1_FLAG_V1_8814B BIT(30)
+
+#define BIT_SHIFT_ACH1_DESC_MODE_V1_8814B 28
+#define BIT_MASK_ACH1_DESC_MODE_V1_8814B 0x3
+#define BIT_ACH1_DESC_MODE_V1_8814B(x) \
+ (((x) & BIT_MASK_ACH1_DESC_MODE_V1_8814B) \
+ << BIT_SHIFT_ACH1_DESC_MODE_V1_8814B)
+#define BITS_ACH1_DESC_MODE_V1_8814B \
+ (BIT_MASK_ACH1_DESC_MODE_V1_8814B << BIT_SHIFT_ACH1_DESC_MODE_V1_8814B)
+#define BIT_CLEAR_ACH1_DESC_MODE_V1_8814B(x) \
+ ((x) & (~BITS_ACH1_DESC_MODE_V1_8814B))
+#define BIT_GET_ACH1_DESC_MODE_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH1_DESC_MODE_V1_8814B) & \
+ BIT_MASK_ACH1_DESC_MODE_V1_8814B)
+#define BIT_SET_ACH1_DESC_MODE_V1_8814B(x, v) \
+ (BIT_CLEAR_ACH1_DESC_MODE_V1_8814B(x) | BIT_ACH1_DESC_MODE_V1_8814B(v))
+
+#define BIT_SHIFT_ACH1_DESC_NUM_V1_8814B 16
+#define BIT_MASK_ACH1_DESC_NUM_V1_8814B 0xfff
+#define BIT_ACH1_DESC_NUM_V1_8814B(x) \
+ (((x) & BIT_MASK_ACH1_DESC_NUM_V1_8814B) \
+ << BIT_SHIFT_ACH1_DESC_NUM_V1_8814B)
+#define BITS_ACH1_DESC_NUM_V1_8814B \
+ (BIT_MASK_ACH1_DESC_NUM_V1_8814B << BIT_SHIFT_ACH1_DESC_NUM_V1_8814B)
+#define BIT_CLEAR_ACH1_DESC_NUM_V1_8814B(x) \
+ ((x) & (~BITS_ACH1_DESC_NUM_V1_8814B))
+#define BIT_GET_ACH1_DESC_NUM_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH1_DESC_NUM_V1_8814B) & \
+ BIT_MASK_ACH1_DESC_NUM_V1_8814B)
+#define BIT_SET_ACH1_DESC_NUM_V1_8814B(x, v) \
+ (BIT_CLEAR_ACH1_DESC_NUM_V1_8814B(x) | BIT_ACH1_DESC_NUM_V1_8814B(v))
+
+#define BIT_PCIE_ACH0_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_ACH0_DESC_MODE_8814B 12
+#define BIT_MASK_ACH0_DESC_MODE_8814B 0x3
+#define BIT_ACH0_DESC_MODE_8814B(x) \
+ (((x) & BIT_MASK_ACH0_DESC_MODE_8814B) \
+ << BIT_SHIFT_ACH0_DESC_MODE_8814B)
+#define BITS_ACH0_DESC_MODE_8814B \
+ (BIT_MASK_ACH0_DESC_MODE_8814B << BIT_SHIFT_ACH0_DESC_MODE_8814B)
+#define BIT_CLEAR_ACH0_DESC_MODE_8814B(x) ((x) & (~BITS_ACH0_DESC_MODE_8814B))
+#define BIT_GET_ACH0_DESC_MODE_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH0_DESC_MODE_8814B) & \
+ BIT_MASK_ACH0_DESC_MODE_8814B)
+#define BIT_SET_ACH0_DESC_MODE_8814B(x, v) \
+ (BIT_CLEAR_ACH0_DESC_MODE_8814B(x) | BIT_ACH0_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_ACH0_DESC_NUM_8814B 0
+#define BIT_MASK_ACH0_DESC_NUM_8814B 0xfff
+#define BIT_ACH0_DESC_NUM_8814B(x) \
+ (((x) & BIT_MASK_ACH0_DESC_NUM_8814B) << BIT_SHIFT_ACH0_DESC_NUM_8814B)
+#define BITS_ACH0_DESC_NUM_8814B \
+ (BIT_MASK_ACH0_DESC_NUM_8814B << BIT_SHIFT_ACH0_DESC_NUM_8814B)
+#define BIT_CLEAR_ACH0_DESC_NUM_8814B(x) ((x) & (~BITS_ACH0_DESC_NUM_8814B))
+#define BIT_GET_ACH0_DESC_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH0_DESC_NUM_8814B) & BIT_MASK_ACH0_DESC_NUM_8814B)
+#define BIT_SET_ACH0_DESC_NUM_8814B(x, v) \
+ (BIT_CLEAR_ACH0_DESC_NUM_8814B(x) | BIT_ACH0_DESC_NUM_8814B(v))
+
+/* 2 REG_ACH2_ACH3_TXBD_NUM_8814B */
+#define BIT_PCIE_ACH3_FLAG_V1_8814B BIT(30)
+
+#define BIT_SHIFT_ACH3_DESC_MODE_V1_8814B 28
+#define BIT_MASK_ACH3_DESC_MODE_V1_8814B 0x3
+#define BIT_ACH3_DESC_MODE_V1_8814B(x) \
+ (((x) & BIT_MASK_ACH3_DESC_MODE_V1_8814B) \
+ << BIT_SHIFT_ACH3_DESC_MODE_V1_8814B)
+#define BITS_ACH3_DESC_MODE_V1_8814B \
+ (BIT_MASK_ACH3_DESC_MODE_V1_8814B << BIT_SHIFT_ACH3_DESC_MODE_V1_8814B)
+#define BIT_CLEAR_ACH3_DESC_MODE_V1_8814B(x) \
+ ((x) & (~BITS_ACH3_DESC_MODE_V1_8814B))
+#define BIT_GET_ACH3_DESC_MODE_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH3_DESC_MODE_V1_8814B) & \
+ BIT_MASK_ACH3_DESC_MODE_V1_8814B)
+#define BIT_SET_ACH3_DESC_MODE_V1_8814B(x, v) \
+ (BIT_CLEAR_ACH3_DESC_MODE_V1_8814B(x) | BIT_ACH3_DESC_MODE_V1_8814B(v))
+
+#define BIT_SHIFT_ACH3_DESC_NUM_V1_8814B 16
+#define BIT_MASK_ACH3_DESC_NUM_V1_8814B 0xfff
+#define BIT_ACH3_DESC_NUM_V1_8814B(x) \
+ (((x) & BIT_MASK_ACH3_DESC_NUM_V1_8814B) \
+ << BIT_SHIFT_ACH3_DESC_NUM_V1_8814B)
+#define BITS_ACH3_DESC_NUM_V1_8814B \
+ (BIT_MASK_ACH3_DESC_NUM_V1_8814B << BIT_SHIFT_ACH3_DESC_NUM_V1_8814B)
+#define BIT_CLEAR_ACH3_DESC_NUM_V1_8814B(x) \
+ ((x) & (~BITS_ACH3_DESC_NUM_V1_8814B))
+#define BIT_GET_ACH3_DESC_NUM_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH3_DESC_NUM_V1_8814B) & \
+ BIT_MASK_ACH3_DESC_NUM_V1_8814B)
+#define BIT_SET_ACH3_DESC_NUM_V1_8814B(x, v) \
+ (BIT_CLEAR_ACH3_DESC_NUM_V1_8814B(x) | BIT_ACH3_DESC_NUM_V1_8814B(v))
+
+#define BIT_PCIE_ACH2_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_ACH2_DESC_MODE_8814B 12
+#define BIT_MASK_ACH2_DESC_MODE_8814B 0x3
+#define BIT_ACH2_DESC_MODE_8814B(x) \
+ (((x) & BIT_MASK_ACH2_DESC_MODE_8814B) \
+ << BIT_SHIFT_ACH2_DESC_MODE_8814B)
+#define BITS_ACH2_DESC_MODE_8814B \
+ (BIT_MASK_ACH2_DESC_MODE_8814B << BIT_SHIFT_ACH2_DESC_MODE_8814B)
+#define BIT_CLEAR_ACH2_DESC_MODE_8814B(x) ((x) & (~BITS_ACH2_DESC_MODE_8814B))
+#define BIT_GET_ACH2_DESC_MODE_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH2_DESC_MODE_8814B) & \
+ BIT_MASK_ACH2_DESC_MODE_8814B)
+#define BIT_SET_ACH2_DESC_MODE_8814B(x, v) \
+ (BIT_CLEAR_ACH2_DESC_MODE_8814B(x) | BIT_ACH2_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_ACH2_DESC_NUM_8814B 0
+#define BIT_MASK_ACH2_DESC_NUM_8814B 0xfff
+#define BIT_ACH2_DESC_NUM_8814B(x) \
+ (((x) & BIT_MASK_ACH2_DESC_NUM_8814B) << BIT_SHIFT_ACH2_DESC_NUM_8814B)
+#define BITS_ACH2_DESC_NUM_8814B \
+ (BIT_MASK_ACH2_DESC_NUM_8814B << BIT_SHIFT_ACH2_DESC_NUM_8814B)
+#define BIT_CLEAR_ACH2_DESC_NUM_8814B(x) ((x) & (~BITS_ACH2_DESC_NUM_8814B))
+#define BIT_GET_ACH2_DESC_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH2_DESC_NUM_8814B) & BIT_MASK_ACH2_DESC_NUM_8814B)
+#define BIT_SET_ACH2_DESC_NUM_8814B(x, v) \
+ (BIT_CLEAR_ACH2_DESC_NUM_8814B(x) | BIT_ACH2_DESC_NUM_8814B(v))
+
+/* 2 REG_P0HI0Q_HI1Q_TXBD_NUM_8814B */
+#define BIT_P0HI1Q_FLAG_8814B BIT(30)
+
+#define BIT_SHIFT_P0HI1Q_DESC_MODE_8814B 28
+#define BIT_MASK_P0HI1Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI1Q_DESC_MODE_8814B(x) \
+ (((x) & BIT_MASK_P0HI1Q_DESC_MODE_8814B) \
+ << BIT_SHIFT_P0HI1Q_DESC_MODE_8814B)
+#define BITS_P0HI1Q_DESC_MODE_8814B \
+ (BIT_MASK_P0HI1Q_DESC_MODE_8814B << BIT_SHIFT_P0HI1Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI1Q_DESC_MODE_8814B(x) \
+ ((x) & (~BITS_P0HI1Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI1Q_DESC_MODE_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI1Q_DESC_MODE_8814B) & \
+ BIT_MASK_P0HI1Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI1Q_DESC_MODE_8814B(x, v) \
+ (BIT_CLEAR_P0HI1Q_DESC_MODE_8814B(x) | BIT_P0HI1Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI1Q_DESC_NUM_8814B 16
+#define BIT_MASK_P0HI1Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI1Q_DESC_NUM_8814B(x) \
+ (((x) & BIT_MASK_P0HI1Q_DESC_NUM_8814B) \
+ << BIT_SHIFT_P0HI1Q_DESC_NUM_8814B)
+#define BITS_P0HI1Q_DESC_NUM_8814B \
+ (BIT_MASK_P0HI1Q_DESC_NUM_8814B << BIT_SHIFT_P0HI1Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI1Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI1Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI1Q_DESC_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI1Q_DESC_NUM_8814B) & \
+ BIT_MASK_P0HI1Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI1Q_DESC_NUM_8814B(x, v) \
+ (BIT_CLEAR_P0HI1Q_DESC_NUM_8814B(x) | BIT_P0HI1Q_DESC_NUM_8814B(v))
+
+#define BIT_P0HI0Q_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_P0HI0Q_DESC_MODE_8814B 12
+#define BIT_MASK_P0HI0Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI0Q_DESC_MODE_8814B(x) \
+ (((x) & BIT_MASK_P0HI0Q_DESC_MODE_8814B) \
+ << BIT_SHIFT_P0HI0Q_DESC_MODE_8814B)
+#define BITS_P0HI0Q_DESC_MODE_8814B \
+ (BIT_MASK_P0HI0Q_DESC_MODE_8814B << BIT_SHIFT_P0HI0Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI0Q_DESC_MODE_8814B(x) \
+ ((x) & (~BITS_P0HI0Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI0Q_DESC_MODE_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI0Q_DESC_MODE_8814B) & \
+ BIT_MASK_P0HI0Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI0Q_DESC_MODE_8814B(x, v) \
+ (BIT_CLEAR_P0HI0Q_DESC_MODE_8814B(x) | BIT_P0HI0Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI0Q_DESC_NUM_8814B 0
+#define BIT_MASK_P0HI0Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI0Q_DESC_NUM_8814B(x) \
+ (((x) & BIT_MASK_P0HI0Q_DESC_NUM_8814B) \
+ << BIT_SHIFT_P0HI0Q_DESC_NUM_8814B)
+#define BITS_P0HI0Q_DESC_NUM_8814B \
+ (BIT_MASK_P0HI0Q_DESC_NUM_8814B << BIT_SHIFT_P0HI0Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI0Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI0Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI0Q_DESC_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI0Q_DESC_NUM_8814B) & \
+ BIT_MASK_P0HI0Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI0Q_DESC_NUM_8814B(x, v) \
+ (BIT_CLEAR_P0HI0Q_DESC_NUM_8814B(x) | BIT_P0HI0Q_DESC_NUM_8814B(v))
+
+/* 2 REG_P0HI2Q_HI3Q_TXBD_NUM_8814B */
+#define BIT_P0HI3Q_FLAG_8814B BIT(30)
+
+#define BIT_SHIFT_P0HI3Q_DESC_MODE_8814B 28
+#define BIT_MASK_P0HI3Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI3Q_DESC_MODE_8814B(x) \
+ (((x) & BIT_MASK_P0HI3Q_DESC_MODE_8814B) \
+ << BIT_SHIFT_P0HI3Q_DESC_MODE_8814B)
+#define BITS_P0HI3Q_DESC_MODE_8814B \
+ (BIT_MASK_P0HI3Q_DESC_MODE_8814B << BIT_SHIFT_P0HI3Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI3Q_DESC_MODE_8814B(x) \
+ ((x) & (~BITS_P0HI3Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI3Q_DESC_MODE_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI3Q_DESC_MODE_8814B) & \
+ BIT_MASK_P0HI3Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI3Q_DESC_MODE_8814B(x, v) \
+ (BIT_CLEAR_P0HI3Q_DESC_MODE_8814B(x) | BIT_P0HI3Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI3Q_DESC_NUM_8814B 16
+#define BIT_MASK_P0HI3Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI3Q_DESC_NUM_8814B(x) \
+ (((x) & BIT_MASK_P0HI3Q_DESC_NUM_8814B) \
+ << BIT_SHIFT_P0HI3Q_DESC_NUM_8814B)
+#define BITS_P0HI3Q_DESC_NUM_8814B \
+ (BIT_MASK_P0HI3Q_DESC_NUM_8814B << BIT_SHIFT_P0HI3Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI3Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI3Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI3Q_DESC_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI3Q_DESC_NUM_8814B) & \
+ BIT_MASK_P0HI3Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI3Q_DESC_NUM_8814B(x, v) \
+ (BIT_CLEAR_P0HI3Q_DESC_NUM_8814B(x) | BIT_P0HI3Q_DESC_NUM_8814B(v))
+
+#define BIT_P0HI2Q_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_P0HI2Q_DESC_MODE_8814B 12
+#define BIT_MASK_P0HI2Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI2Q_DESC_MODE_8814B(x) \
+ (((x) & BIT_MASK_P0HI2Q_DESC_MODE_8814B) \
+ << BIT_SHIFT_P0HI2Q_DESC_MODE_8814B)
+#define BITS_P0HI2Q_DESC_MODE_8814B \
+ (BIT_MASK_P0HI2Q_DESC_MODE_8814B << BIT_SHIFT_P0HI2Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI2Q_DESC_MODE_8814B(x) \
+ ((x) & (~BITS_P0HI2Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI2Q_DESC_MODE_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI2Q_DESC_MODE_8814B) & \
+ BIT_MASK_P0HI2Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI2Q_DESC_MODE_8814B(x, v) \
+ (BIT_CLEAR_P0HI2Q_DESC_MODE_8814B(x) | BIT_P0HI2Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI2Q_DESC_NUM_8814B 0
+#define BIT_MASK_P0HI2Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI2Q_DESC_NUM_8814B(x) \
+ (((x) & BIT_MASK_P0HI2Q_DESC_NUM_8814B) \
+ << BIT_SHIFT_P0HI2Q_DESC_NUM_8814B)
+#define BITS_P0HI2Q_DESC_NUM_8814B \
+ (BIT_MASK_P0HI2Q_DESC_NUM_8814B << BIT_SHIFT_P0HI2Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI2Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI2Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI2Q_DESC_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI2Q_DESC_NUM_8814B) & \
+ BIT_MASK_P0HI2Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI2Q_DESC_NUM_8814B(x, v) \
+ (BIT_CLEAR_P0HI2Q_DESC_NUM_8814B(x) | BIT_P0HI2Q_DESC_NUM_8814B(v))
+
+/* 2 REG_P0HI4Q_HI5Q_TXBD_NUM_8814B */
+#define BIT_P0HI5Q_FLAG_8814B BIT(30)
+
+#define BIT_SHIFT_P0HI5Q_DESC_MODE_8814B 28
+#define BIT_MASK_P0HI5Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI5Q_DESC_MODE_8814B(x) \
+ (((x) & BIT_MASK_P0HI5Q_DESC_MODE_8814B) \
+ << BIT_SHIFT_P0HI5Q_DESC_MODE_8814B)
+#define BITS_P0HI5Q_DESC_MODE_8814B \
+ (BIT_MASK_P0HI5Q_DESC_MODE_8814B << BIT_SHIFT_P0HI5Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI5Q_DESC_MODE_8814B(x) \
+ ((x) & (~BITS_P0HI5Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI5Q_DESC_MODE_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI5Q_DESC_MODE_8814B) & \
+ BIT_MASK_P0HI5Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI5Q_DESC_MODE_8814B(x, v) \
+ (BIT_CLEAR_P0HI5Q_DESC_MODE_8814B(x) | BIT_P0HI5Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI5Q_DESC_NUM_8814B 16
+#define BIT_MASK_P0HI5Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI5Q_DESC_NUM_8814B(x) \
+ (((x) & BIT_MASK_P0HI5Q_DESC_NUM_8814B) \
+ << BIT_SHIFT_P0HI5Q_DESC_NUM_8814B)
+#define BITS_P0HI5Q_DESC_NUM_8814B \
+ (BIT_MASK_P0HI5Q_DESC_NUM_8814B << BIT_SHIFT_P0HI5Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI5Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI5Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI5Q_DESC_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI5Q_DESC_NUM_8814B) & \
+ BIT_MASK_P0HI5Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI5Q_DESC_NUM_8814B(x, v) \
+ (BIT_CLEAR_P0HI5Q_DESC_NUM_8814B(x) | BIT_P0HI5Q_DESC_NUM_8814B(v))
+
+#define BIT_P0HI4Q_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_P0HI4Q_DESC_MODE_8814B 12
+#define BIT_MASK_P0HI4Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI4Q_DESC_MODE_8814B(x) \
+ (((x) & BIT_MASK_P0HI4Q_DESC_MODE_8814B) \
+ << BIT_SHIFT_P0HI4Q_DESC_MODE_8814B)
+#define BITS_P0HI4Q_DESC_MODE_8814B \
+ (BIT_MASK_P0HI4Q_DESC_MODE_8814B << BIT_SHIFT_P0HI4Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI4Q_DESC_MODE_8814B(x) \
+ ((x) & (~BITS_P0HI4Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI4Q_DESC_MODE_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI4Q_DESC_MODE_8814B) & \
+ BIT_MASK_P0HI4Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI4Q_DESC_MODE_8814B(x, v) \
+ (BIT_CLEAR_P0HI4Q_DESC_MODE_8814B(x) | BIT_P0HI4Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI4Q_DESC_NUM_8814B 0
+#define BIT_MASK_P0HI4Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI4Q_DESC_NUM_8814B(x) \
+ (((x) & BIT_MASK_P0HI4Q_DESC_NUM_8814B) \
+ << BIT_SHIFT_P0HI4Q_DESC_NUM_8814B)
+#define BITS_P0HI4Q_DESC_NUM_8814B \
+ (BIT_MASK_P0HI4Q_DESC_NUM_8814B << BIT_SHIFT_P0HI4Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI4Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI4Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI4Q_DESC_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI4Q_DESC_NUM_8814B) & \
+ BIT_MASK_P0HI4Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI4Q_DESC_NUM_8814B(x, v) \
+ (BIT_CLEAR_P0HI4Q_DESC_NUM_8814B(x) | BIT_P0HI4Q_DESC_NUM_8814B(v))
+
+/* 2 REG_P0HI6Q_HI7Q_TXBD_NUM_8814B */
+#define BIT_P0HI7Q_FLAG_8814B BIT(30)
+
+#define BIT_SHIFT_P0HI7Q_DESC_MODE_8814B 28
+#define BIT_MASK_P0HI7Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI7Q_DESC_MODE_8814B(x) \
+ (((x) & BIT_MASK_P0HI7Q_DESC_MODE_8814B) \
+ << BIT_SHIFT_P0HI7Q_DESC_MODE_8814B)
+#define BITS_P0HI7Q_DESC_MODE_8814B \
+ (BIT_MASK_P0HI7Q_DESC_MODE_8814B << BIT_SHIFT_P0HI7Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI7Q_DESC_MODE_8814B(x) \
+ ((x) & (~BITS_P0HI7Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI7Q_DESC_MODE_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI7Q_DESC_MODE_8814B) & \
+ BIT_MASK_P0HI7Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI7Q_DESC_MODE_8814B(x, v) \
+ (BIT_CLEAR_P0HI7Q_DESC_MODE_8814B(x) | BIT_P0HI7Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI7Q_DESC_NUM_8814B 16
+#define BIT_MASK_P0HI7Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI7Q_DESC_NUM_8814B(x) \
+ (((x) & BIT_MASK_P0HI7Q_DESC_NUM_8814B) \
+ << BIT_SHIFT_P0HI7Q_DESC_NUM_8814B)
+#define BITS_P0HI7Q_DESC_NUM_8814B \
+ (BIT_MASK_P0HI7Q_DESC_NUM_8814B << BIT_SHIFT_P0HI7Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI7Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI7Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI7Q_DESC_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI7Q_DESC_NUM_8814B) & \
+ BIT_MASK_P0HI7Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI7Q_DESC_NUM_8814B(x, v) \
+ (BIT_CLEAR_P0HI7Q_DESC_NUM_8814B(x) | BIT_P0HI7Q_DESC_NUM_8814B(v))
+
+#define BIT_P0HI6Q_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_P0HI6Q_DESC_MODE_8814B 12
+#define BIT_MASK_P0HI6Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI6Q_DESC_MODE_8814B(x) \
+ (((x) & BIT_MASK_P0HI6Q_DESC_MODE_8814B) \
+ << BIT_SHIFT_P0HI6Q_DESC_MODE_8814B)
+#define BITS_P0HI6Q_DESC_MODE_8814B \
+ (BIT_MASK_P0HI6Q_DESC_MODE_8814B << BIT_SHIFT_P0HI6Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI6Q_DESC_MODE_8814B(x) \
+ ((x) & (~BITS_P0HI6Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI6Q_DESC_MODE_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI6Q_DESC_MODE_8814B) & \
+ BIT_MASK_P0HI6Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI6Q_DESC_MODE_8814B(x, v) \
+ (BIT_CLEAR_P0HI6Q_DESC_MODE_8814B(x) | BIT_P0HI6Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI6Q_DESC_NUM_8814B 0
+#define BIT_MASK_P0HI6Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI6Q_DESC_NUM_8814B(x) \
+ (((x) & BIT_MASK_P0HI6Q_DESC_NUM_8814B) \
+ << BIT_SHIFT_P0HI6Q_DESC_NUM_8814B)
+#define BITS_P0HI6Q_DESC_NUM_8814B \
+ (BIT_MASK_P0HI6Q_DESC_NUM_8814B << BIT_SHIFT_P0HI6Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI6Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI6Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI6Q_DESC_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI6Q_DESC_NUM_8814B) & \
+ BIT_MASK_P0HI6Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI6Q_DESC_NUM_8814B(x, v) \
+ (BIT_CLEAR_P0HI6Q_DESC_NUM_8814B(x) | BIT_P0HI6Q_DESC_NUM_8814B(v))
+
+/* 2 REG_BD_RWPTR_CLR1_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_CLR_FWCMDQ_HW_IDX_8814B BIT(30)
+#define BIT_CLR_P0HI7Q_HW_IDX_8814B BIT(29)
+#define BIT_CLR_P0HI6Q_HW_IDX_8814B BIT(28)
+#define BIT_CLR_P0HI5Q_HW_IDX_8814B BIT(27)
+#define BIT_CLR_P0HI4Q_HW_IDX_8814B BIT(26)
+#define BIT_CLR_P0HI3Q_HW_IDX_8814B BIT(25)
+#define BIT_CLR_P0HI2Q_HW_IDX_8814B BIT(24)
+#define BIT_CLR_P0HI1Q_HW_IDX_8814B BIT(23)
+#define BIT_CLR_P0HI0Q_HW_IDX_8814B BIT(22)
+#define BIT_CLR_ACH3_HW_IDX_8814B BIT(21)
+#define BIT_CLR_ACH2_HW_IDX_8814B BIT(20)
+#define BIT_CLR_ACH1_HW_IDX_8814B BIT(19)
+#define BIT_CLR_ACH0_HW_IDX_8814B BIT(18)
+#define BIT_CLR_P0MGQ_HW_IDX_8814B BIT(17)
+#define BIT_CLR_P0RXQ_HW_IDX_8814B BIT(16)
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_CLR_PFWCMDQ_HOST_IDX_8814B BIT(14)
+#define BIT_CLR_P0HI7Q_HOST_IDX_8814B BIT(13)
+#define BIT_CLR_P0HI6Q_HOST_IDX_8814B BIT(12)
+#define BIT_CLR_P0HI5Q_HOST_IDX_8814B BIT(11)
+#define BIT_CLR_P0HI4Q_HOST_IDX_8814B BIT(10)
+#define BIT_CLR_P0HI3Q_HOST_IDX_8814B BIT(9)
+#define BIT_CLR_P0HI2Q_HOST_IDX_8814B BIT(8)
+#define BIT_CLR_P0HI1Q_HOST_IDX_8814B BIT(7)
+#define BIT_CLR_P0HI0Q_HOST_IDX_8814B BIT(6)
+#define BIT_CLR_ACH3_HOST_IDX_8814B BIT(5)
+#define BIT_CLR_ACH2_HOST_IDX_8814B BIT(4)
+#define BIT_CLR_ACH1_HOST_IDX_8814B BIT(3)
+#define BIT_CLR_ACH0_HOST_IDX_8814B BIT(2)
+#define BIT_CLR_P0MGQ_HOST_IDX_8814B BIT(1)
+#define BIT_CLR_P0RXQ_HOST_IDX_8814B BIT(0)
+
+/* 2 REG_TSFTIMER_HCI_8814B */
+
+#define BIT_SHIFT_TSFT2_HCI_8814B 16
+#define BIT_MASK_TSFT2_HCI_8814B 0xffff
+#define BIT_TSFT2_HCI_8814B(x) \
+ (((x) & BIT_MASK_TSFT2_HCI_8814B) << BIT_SHIFT_TSFT2_HCI_8814B)
+#define BITS_TSFT2_HCI_8814B \
+ (BIT_MASK_TSFT2_HCI_8814B << BIT_SHIFT_TSFT2_HCI_8814B)
+#define BIT_CLEAR_TSFT2_HCI_8814B(x) ((x) & (~BITS_TSFT2_HCI_8814B))
+#define BIT_GET_TSFT2_HCI_8814B(x) \
+ (((x) >> BIT_SHIFT_TSFT2_HCI_8814B) & BIT_MASK_TSFT2_HCI_8814B)
+#define BIT_SET_TSFT2_HCI_8814B(x, v) \
+ (BIT_CLEAR_TSFT2_HCI_8814B(x) | BIT_TSFT2_HCI_8814B(v))
+
+#define BIT_SHIFT_TSFT1_HCI_8814B 0
+#define BIT_MASK_TSFT1_HCI_8814B 0xffff
+#define BIT_TSFT1_HCI_8814B(x) \
+ (((x) & BIT_MASK_TSFT1_HCI_8814B) << BIT_SHIFT_TSFT1_HCI_8814B)
+#define BITS_TSFT1_HCI_8814B \
+ (BIT_MASK_TSFT1_HCI_8814B << BIT_SHIFT_TSFT1_HCI_8814B)
+#define BIT_CLEAR_TSFT1_HCI_8814B(x) ((x) & (~BITS_TSFT1_HCI_8814B))
+#define BIT_GET_TSFT1_HCI_8814B(x) \
+ (((x) >> BIT_SHIFT_TSFT1_HCI_8814B) & BIT_MASK_TSFT1_HCI_8814B)
+#define BIT_SET_TSFT1_HCI_8814B(x, v) \
+ (BIT_CLEAR_TSFT1_HCI_8814B(x) | BIT_TSFT1_HCI_8814B(v))
+
+/* 2 REG_ACH0_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_ACH0_HW_IDX_8814B 16
+#define BIT_MASK_ACH0_HW_IDX_8814B 0xfff
+#define BIT_ACH0_HW_IDX_8814B(x) \
+ (((x) & BIT_MASK_ACH0_HW_IDX_8814B) << BIT_SHIFT_ACH0_HW_IDX_8814B)
+#define BITS_ACH0_HW_IDX_8814B \
+ (BIT_MASK_ACH0_HW_IDX_8814B << BIT_SHIFT_ACH0_HW_IDX_8814B)
+#define BIT_CLEAR_ACH0_HW_IDX_8814B(x) ((x) & (~BITS_ACH0_HW_IDX_8814B))
+#define BIT_GET_ACH0_HW_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH0_HW_IDX_8814B) & BIT_MASK_ACH0_HW_IDX_8814B)
+#define BIT_SET_ACH0_HW_IDX_8814B(x, v) \
+ (BIT_CLEAR_ACH0_HW_IDX_8814B(x) | BIT_ACH0_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_ACH0_HOST_IDX_8814B 0
+#define BIT_MASK_ACH0_HOST_IDX_8814B 0xfff
+#define BIT_ACH0_HOST_IDX_8814B(x) \
+ (((x) & BIT_MASK_ACH0_HOST_IDX_8814B) << BIT_SHIFT_ACH0_HOST_IDX_8814B)
+#define BITS_ACH0_HOST_IDX_8814B \
+ (BIT_MASK_ACH0_HOST_IDX_8814B << BIT_SHIFT_ACH0_HOST_IDX_8814B)
+#define BIT_CLEAR_ACH0_HOST_IDX_8814B(x) ((x) & (~BITS_ACH0_HOST_IDX_8814B))
+#define BIT_GET_ACH0_HOST_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH0_HOST_IDX_8814B) & BIT_MASK_ACH0_HOST_IDX_8814B)
+#define BIT_SET_ACH0_HOST_IDX_8814B(x, v) \
+ (BIT_CLEAR_ACH0_HOST_IDX_8814B(x) | BIT_ACH0_HOST_IDX_8814B(v))
+
+/* 2 REG_ACH1_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_ACH1_HW_IDX_8814B 16
+#define BIT_MASK_ACH1_HW_IDX_8814B 0xfff
+#define BIT_ACH1_HW_IDX_8814B(x) \
+ (((x) & BIT_MASK_ACH1_HW_IDX_8814B) << BIT_SHIFT_ACH1_HW_IDX_8814B)
+#define BITS_ACH1_HW_IDX_8814B \
+ (BIT_MASK_ACH1_HW_IDX_8814B << BIT_SHIFT_ACH1_HW_IDX_8814B)
+#define BIT_CLEAR_ACH1_HW_IDX_8814B(x) ((x) & (~BITS_ACH1_HW_IDX_8814B))
+#define BIT_GET_ACH1_HW_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH1_HW_IDX_8814B) & BIT_MASK_ACH1_HW_IDX_8814B)
+#define BIT_SET_ACH1_HW_IDX_8814B(x, v) \
+ (BIT_CLEAR_ACH1_HW_IDX_8814B(x) | BIT_ACH1_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_ACH1_HOST_IDX_8814B 0
+#define BIT_MASK_ACH1_HOST_IDX_8814B 0xfff
+#define BIT_ACH1_HOST_IDX_8814B(x) \
+ (((x) & BIT_MASK_ACH1_HOST_IDX_8814B) << BIT_SHIFT_ACH1_HOST_IDX_8814B)
+#define BITS_ACH1_HOST_IDX_8814B \
+ (BIT_MASK_ACH1_HOST_IDX_8814B << BIT_SHIFT_ACH1_HOST_IDX_8814B)
+#define BIT_CLEAR_ACH1_HOST_IDX_8814B(x) ((x) & (~BITS_ACH1_HOST_IDX_8814B))
+#define BIT_GET_ACH1_HOST_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH1_HOST_IDX_8814B) & BIT_MASK_ACH1_HOST_IDX_8814B)
+#define BIT_SET_ACH1_HOST_IDX_8814B(x, v) \
+ (BIT_CLEAR_ACH1_HOST_IDX_8814B(x) | BIT_ACH1_HOST_IDX_8814B(v))
+
+/* 2 REG_ACH2_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_ACH2_HW_IDX_8814B 16
+#define BIT_MASK_ACH2_HW_IDX_8814B 0xfff
+#define BIT_ACH2_HW_IDX_8814B(x) \
+ (((x) & BIT_MASK_ACH2_HW_IDX_8814B) << BIT_SHIFT_ACH2_HW_IDX_8814B)
+#define BITS_ACH2_HW_IDX_8814B \
+ (BIT_MASK_ACH2_HW_IDX_8814B << BIT_SHIFT_ACH2_HW_IDX_8814B)
+#define BIT_CLEAR_ACH2_HW_IDX_8814B(x) ((x) & (~BITS_ACH2_HW_IDX_8814B))
+#define BIT_GET_ACH2_HW_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH2_HW_IDX_8814B) & BIT_MASK_ACH2_HW_IDX_8814B)
+#define BIT_SET_ACH2_HW_IDX_8814B(x, v) \
+ (BIT_CLEAR_ACH2_HW_IDX_8814B(x) | BIT_ACH2_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_ACH2_HOST_IDX_8814B 0
+#define BIT_MASK_ACH2_HOST_IDX_8814B 0xfff
+#define BIT_ACH2_HOST_IDX_8814B(x) \
+ (((x) & BIT_MASK_ACH2_HOST_IDX_8814B) << BIT_SHIFT_ACH2_HOST_IDX_8814B)
+#define BITS_ACH2_HOST_IDX_8814B \
+ (BIT_MASK_ACH2_HOST_IDX_8814B << BIT_SHIFT_ACH2_HOST_IDX_8814B)
+#define BIT_CLEAR_ACH2_HOST_IDX_8814B(x) ((x) & (~BITS_ACH2_HOST_IDX_8814B))
+#define BIT_GET_ACH2_HOST_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH2_HOST_IDX_8814B) & BIT_MASK_ACH2_HOST_IDX_8814B)
+#define BIT_SET_ACH2_HOST_IDX_8814B(x, v) \
+ (BIT_CLEAR_ACH2_HOST_IDX_8814B(x) | BIT_ACH2_HOST_IDX_8814B(v))
+
+/* 2 REG_ACH3_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_ACH3_HW_IDX_8814B 16
+#define BIT_MASK_ACH3_HW_IDX_8814B 0xfff
+#define BIT_ACH3_HW_IDX_8814B(x) \
+ (((x) & BIT_MASK_ACH3_HW_IDX_8814B) << BIT_SHIFT_ACH3_HW_IDX_8814B)
+#define BITS_ACH3_HW_IDX_8814B \
+ (BIT_MASK_ACH3_HW_IDX_8814B << BIT_SHIFT_ACH3_HW_IDX_8814B)
+#define BIT_CLEAR_ACH3_HW_IDX_8814B(x) ((x) & (~BITS_ACH3_HW_IDX_8814B))
+#define BIT_GET_ACH3_HW_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH3_HW_IDX_8814B) & BIT_MASK_ACH3_HW_IDX_8814B)
+#define BIT_SET_ACH3_HW_IDX_8814B(x, v) \
+ (BIT_CLEAR_ACH3_HW_IDX_8814B(x) | BIT_ACH3_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_ACH3_HOST_IDX_8814B 0
+#define BIT_MASK_ACH3_HOST_IDX_8814B 0xfff
+#define BIT_ACH3_HOST_IDX_8814B(x) \
+ (((x) & BIT_MASK_ACH3_HOST_IDX_8814B) << BIT_SHIFT_ACH3_HOST_IDX_8814B)
+#define BITS_ACH3_HOST_IDX_8814B \
+ (BIT_MASK_ACH3_HOST_IDX_8814B << BIT_SHIFT_ACH3_HOST_IDX_8814B)
+#define BIT_CLEAR_ACH3_HOST_IDX_8814B(x) ((x) & (~BITS_ACH3_HOST_IDX_8814B))
+#define BIT_GET_ACH3_HOST_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH3_HOST_IDX_8814B) & BIT_MASK_ACH3_HOST_IDX_8814B)
+#define BIT_SET_ACH3_HOST_IDX_8814B(x, v) \
+ (BIT_CLEAR_ACH3_HOST_IDX_8814B(x) | BIT_ACH3_HOST_IDX_8814B(v))
+
+/* 2 REG_P0MGQ_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0MGQ_HW_IDX_8814B 16
+#define BIT_MASK_P0MGQ_HW_IDX_8814B 0xfff
+#define BIT_P0MGQ_HW_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0MGQ_HW_IDX_8814B) << BIT_SHIFT_P0MGQ_HW_IDX_8814B)
+#define BITS_P0MGQ_HW_IDX_8814B \
+ (BIT_MASK_P0MGQ_HW_IDX_8814B << BIT_SHIFT_P0MGQ_HW_IDX_8814B)
+#define BIT_CLEAR_P0MGQ_HW_IDX_8814B(x) ((x) & (~BITS_P0MGQ_HW_IDX_8814B))
+#define BIT_GET_P0MGQ_HW_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0MGQ_HW_IDX_8814B) & BIT_MASK_P0MGQ_HW_IDX_8814B)
+#define BIT_SET_P0MGQ_HW_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0MGQ_HW_IDX_8814B(x) | BIT_P0MGQ_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0MGQ_HOST_IDX_8814B 0
+#define BIT_MASK_P0MGQ_HOST_IDX_8814B 0xfff
+#define BIT_P0MGQ_HOST_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0MGQ_HOST_IDX_8814B) \
+ << BIT_SHIFT_P0MGQ_HOST_IDX_8814B)
+#define BITS_P0MGQ_HOST_IDX_8814B \
+ (BIT_MASK_P0MGQ_HOST_IDX_8814B << BIT_SHIFT_P0MGQ_HOST_IDX_8814B)
+#define BIT_CLEAR_P0MGQ_HOST_IDX_8814B(x) ((x) & (~BITS_P0MGQ_HOST_IDX_8814B))
+#define BIT_GET_P0MGQ_HOST_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0MGQ_HOST_IDX_8814B) & \
+ BIT_MASK_P0MGQ_HOST_IDX_8814B)
+#define BIT_SET_P0MGQ_HOST_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0MGQ_HOST_IDX_8814B(x) | BIT_P0MGQ_HOST_IDX_8814B(v))
+
+/* 2 REG_P0RXQ_RXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0RXQ_HW_IDX_8814B 16
+#define BIT_MASK_P0RXQ_HW_IDX_8814B 0xfff
+#define BIT_P0RXQ_HW_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0RXQ_HW_IDX_8814B) << BIT_SHIFT_P0RXQ_HW_IDX_8814B)
+#define BITS_P0RXQ_HW_IDX_8814B \
+ (BIT_MASK_P0RXQ_HW_IDX_8814B << BIT_SHIFT_P0RXQ_HW_IDX_8814B)
+#define BIT_CLEAR_P0RXQ_HW_IDX_8814B(x) ((x) & (~BITS_P0RXQ_HW_IDX_8814B))
+#define BIT_GET_P0RXQ_HW_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0RXQ_HW_IDX_8814B) & BIT_MASK_P0RXQ_HW_IDX_8814B)
+#define BIT_SET_P0RXQ_HW_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0RXQ_HW_IDX_8814B(x) | BIT_P0RXQ_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0RXQ_HOST_IDX_8814B 0
+#define BIT_MASK_P0RXQ_HOST_IDX_8814B 0xfff
+#define BIT_P0RXQ_HOST_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0RXQ_HOST_IDX_8814B) \
+ << BIT_SHIFT_P0RXQ_HOST_IDX_8814B)
+#define BITS_P0RXQ_HOST_IDX_8814B \
+ (BIT_MASK_P0RXQ_HOST_IDX_8814B << BIT_SHIFT_P0RXQ_HOST_IDX_8814B)
+#define BIT_CLEAR_P0RXQ_HOST_IDX_8814B(x) ((x) & (~BITS_P0RXQ_HOST_IDX_8814B))
+#define BIT_GET_P0RXQ_HOST_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0RXQ_HOST_IDX_8814B) & \
+ BIT_MASK_P0RXQ_HOST_IDX_8814B)
+#define BIT_SET_P0RXQ_HOST_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0RXQ_HOST_IDX_8814B(x) | BIT_P0RXQ_HOST_IDX_8814B(v))
+
+/* 2 REG_P0HI0Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI0Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI0Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI0Q_HW_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI0Q_HW_IDX_8814B) << BIT_SHIFT_P0HI0Q_HW_IDX_8814B)
+#define BITS_P0HI0Q_HW_IDX_8814B \
+ (BIT_MASK_P0HI0Q_HW_IDX_8814B << BIT_SHIFT_P0HI0Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI0Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI0Q_HW_IDX_8814B))
+#define BIT_GET_P0HI0Q_HW_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI0Q_HW_IDX_8814B) & BIT_MASK_P0HI0Q_HW_IDX_8814B)
+#define BIT_SET_P0HI0Q_HW_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI0Q_HW_IDX_8814B(x) | BIT_P0HI0Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI0Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI0Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI0Q_HOST_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI0Q_HOST_IDX_8814B) \
+ << BIT_SHIFT_P0HI0Q_HOST_IDX_8814B)
+#define BITS_P0HI0Q_HOST_IDX_8814B \
+ (BIT_MASK_P0HI0Q_HOST_IDX_8814B << BIT_SHIFT_P0HI0Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI0Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI0Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI0Q_HOST_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI0Q_HOST_IDX_8814B) & \
+ BIT_MASK_P0HI0Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI0Q_HOST_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI0Q_HOST_IDX_8814B(x) | BIT_P0HI0Q_HOST_IDX_8814B(v))
+
+/* 2 REG_P0HI1Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI1Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI1Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI1Q_HW_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI1Q_HW_IDX_8814B) << BIT_SHIFT_P0HI1Q_HW_IDX_8814B)
+#define BITS_P0HI1Q_HW_IDX_8814B \
+ (BIT_MASK_P0HI1Q_HW_IDX_8814B << BIT_SHIFT_P0HI1Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI1Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI1Q_HW_IDX_8814B))
+#define BIT_GET_P0HI1Q_HW_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI1Q_HW_IDX_8814B) & BIT_MASK_P0HI1Q_HW_IDX_8814B)
+#define BIT_SET_P0HI1Q_HW_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI1Q_HW_IDX_8814B(x) | BIT_P0HI1Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI1Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI1Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI1Q_HOST_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI1Q_HOST_IDX_8814B) \
+ << BIT_SHIFT_P0HI1Q_HOST_IDX_8814B)
+#define BITS_P0HI1Q_HOST_IDX_8814B \
+ (BIT_MASK_P0HI1Q_HOST_IDX_8814B << BIT_SHIFT_P0HI1Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI1Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI1Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI1Q_HOST_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI1Q_HOST_IDX_8814B) & \
+ BIT_MASK_P0HI1Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI1Q_HOST_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI1Q_HOST_IDX_8814B(x) | BIT_P0HI1Q_HOST_IDX_8814B(v))
+
+/* 2 REG_P0HI2Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI2Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI2Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI2Q_HW_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI2Q_HW_IDX_8814B) << BIT_SHIFT_P0HI2Q_HW_IDX_8814B)
+#define BITS_P0HI2Q_HW_IDX_8814B \
+ (BIT_MASK_P0HI2Q_HW_IDX_8814B << BIT_SHIFT_P0HI2Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI2Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI2Q_HW_IDX_8814B))
+#define BIT_GET_P0HI2Q_HW_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI2Q_HW_IDX_8814B) & BIT_MASK_P0HI2Q_HW_IDX_8814B)
+#define BIT_SET_P0HI2Q_HW_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI2Q_HW_IDX_8814B(x) | BIT_P0HI2Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI2Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI2Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI2Q_HOST_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI2Q_HOST_IDX_8814B) \
+ << BIT_SHIFT_P0HI2Q_HOST_IDX_8814B)
+#define BITS_P0HI2Q_HOST_IDX_8814B \
+ (BIT_MASK_P0HI2Q_HOST_IDX_8814B << BIT_SHIFT_P0HI2Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI2Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI2Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI2Q_HOST_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI2Q_HOST_IDX_8814B) & \
+ BIT_MASK_P0HI2Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI2Q_HOST_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI2Q_HOST_IDX_8814B(x) | BIT_P0HI2Q_HOST_IDX_8814B(v))
+
+/* 2 REG_P0HI3Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI3Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI3Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI3Q_HW_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI3Q_HW_IDX_8814B) << BIT_SHIFT_P0HI3Q_HW_IDX_8814B)
+#define BITS_P0HI3Q_HW_IDX_8814B \
+ (BIT_MASK_P0HI3Q_HW_IDX_8814B << BIT_SHIFT_P0HI3Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI3Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI3Q_HW_IDX_8814B))
+#define BIT_GET_P0HI3Q_HW_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI3Q_HW_IDX_8814B) & BIT_MASK_P0HI3Q_HW_IDX_8814B)
+#define BIT_SET_P0HI3Q_HW_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI3Q_HW_IDX_8814B(x) | BIT_P0HI3Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI3Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI3Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI3Q_HOST_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI3Q_HOST_IDX_8814B) \
+ << BIT_SHIFT_P0HI3Q_HOST_IDX_8814B)
+#define BITS_P0HI3Q_HOST_IDX_8814B \
+ (BIT_MASK_P0HI3Q_HOST_IDX_8814B << BIT_SHIFT_P0HI3Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI3Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI3Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI3Q_HOST_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI3Q_HOST_IDX_8814B) & \
+ BIT_MASK_P0HI3Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI3Q_HOST_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI3Q_HOST_IDX_8814B(x) | BIT_P0HI3Q_HOST_IDX_8814B(v))
+
+/* 2 REG_P0HI4Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI4Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI4Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI4Q_HW_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI4Q_HW_IDX_8814B) << BIT_SHIFT_P0HI4Q_HW_IDX_8814B)
+#define BITS_P0HI4Q_HW_IDX_8814B \
+ (BIT_MASK_P0HI4Q_HW_IDX_8814B << BIT_SHIFT_P0HI4Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI4Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI4Q_HW_IDX_8814B))
+#define BIT_GET_P0HI4Q_HW_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI4Q_HW_IDX_8814B) & BIT_MASK_P0HI4Q_HW_IDX_8814B)
+#define BIT_SET_P0HI4Q_HW_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI4Q_HW_IDX_8814B(x) | BIT_P0HI4Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI4Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI4Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI4Q_HOST_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI4Q_HOST_IDX_8814B) \
+ << BIT_SHIFT_P0HI4Q_HOST_IDX_8814B)
+#define BITS_P0HI4Q_HOST_IDX_8814B \
+ (BIT_MASK_P0HI4Q_HOST_IDX_8814B << BIT_SHIFT_P0HI4Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI4Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI4Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI4Q_HOST_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI4Q_HOST_IDX_8814B) & \
+ BIT_MASK_P0HI4Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI4Q_HOST_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI4Q_HOST_IDX_8814B(x) | BIT_P0HI4Q_HOST_IDX_8814B(v))
+
+/* 2 REG_P0HI5Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI5Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI5Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI5Q_HW_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI5Q_HW_IDX_8814B) << BIT_SHIFT_P0HI5Q_HW_IDX_8814B)
+#define BITS_P0HI5Q_HW_IDX_8814B \
+ (BIT_MASK_P0HI5Q_HW_IDX_8814B << BIT_SHIFT_P0HI5Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI5Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI5Q_HW_IDX_8814B))
+#define BIT_GET_P0HI5Q_HW_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI5Q_HW_IDX_8814B) & BIT_MASK_P0HI5Q_HW_IDX_8814B)
+#define BIT_SET_P0HI5Q_HW_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI5Q_HW_IDX_8814B(x) | BIT_P0HI5Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI5Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI5Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI5Q_HOST_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI5Q_HOST_IDX_8814B) \
+ << BIT_SHIFT_P0HI5Q_HOST_IDX_8814B)
+#define BITS_P0HI5Q_HOST_IDX_8814B \
+ (BIT_MASK_P0HI5Q_HOST_IDX_8814B << BIT_SHIFT_P0HI5Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI5Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI5Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI5Q_HOST_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI5Q_HOST_IDX_8814B) & \
+ BIT_MASK_P0HI5Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI5Q_HOST_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI5Q_HOST_IDX_8814B(x) | BIT_P0HI5Q_HOST_IDX_8814B(v))
+
+/* 2 REG_P0HI6Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI6Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI6Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI6Q_HW_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI6Q_HW_IDX_8814B) << BIT_SHIFT_P0HI6Q_HW_IDX_8814B)
+#define BITS_P0HI6Q_HW_IDX_8814B \
+ (BIT_MASK_P0HI6Q_HW_IDX_8814B << BIT_SHIFT_P0HI6Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI6Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI6Q_HW_IDX_8814B))
+#define BIT_GET_P0HI6Q_HW_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI6Q_HW_IDX_8814B) & BIT_MASK_P0HI6Q_HW_IDX_8814B)
+#define BIT_SET_P0HI6Q_HW_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI6Q_HW_IDX_8814B(x) | BIT_P0HI6Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI6Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI6Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI6Q_HOST_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI6Q_HOST_IDX_8814B) \
+ << BIT_SHIFT_P0HI6Q_HOST_IDX_8814B)
+#define BITS_P0HI6Q_HOST_IDX_8814B \
+ (BIT_MASK_P0HI6Q_HOST_IDX_8814B << BIT_SHIFT_P0HI6Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI6Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI6Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI6Q_HOST_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI6Q_HOST_IDX_8814B) & \
+ BIT_MASK_P0HI6Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI6Q_HOST_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI6Q_HOST_IDX_8814B(x) | BIT_P0HI6Q_HOST_IDX_8814B(v))
+
+/* 2 REG_P0HI7Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI7Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI7Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI7Q_HW_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI7Q_HW_IDX_8814B) << BIT_SHIFT_P0HI7Q_HW_IDX_8814B)
+#define BITS_P0HI7Q_HW_IDX_8814B \
+ (BIT_MASK_P0HI7Q_HW_IDX_8814B << BIT_SHIFT_P0HI7Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI7Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI7Q_HW_IDX_8814B))
+#define BIT_GET_P0HI7Q_HW_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI7Q_HW_IDX_8814B) & BIT_MASK_P0HI7Q_HW_IDX_8814B)
+#define BIT_SET_P0HI7Q_HW_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI7Q_HW_IDX_8814B(x) | BIT_P0HI7Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI7Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI7Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI7Q_HOST_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI7Q_HOST_IDX_8814B) \
+ << BIT_SHIFT_P0HI7Q_HOST_IDX_8814B)
+#define BITS_P0HI7Q_HOST_IDX_8814B \
+ (BIT_MASK_P0HI7Q_HOST_IDX_8814B << BIT_SHIFT_P0HI7Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI7Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI7Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI7Q_HOST_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI7Q_HOST_IDX_8814B) & \
+ BIT_MASK_P0HI7Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI7Q_HOST_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI7Q_HOST_IDX_8814B(x) | BIT_P0HI7Q_HOST_IDX_8814B(v))
+
+/* 2 REG_DBGSEL_PCIE_HRPWM1_HCPWM1_V1_8814B */
+#define BIT_DIS_TXDMA_PRE_V1_8814B BIT(31)
+#define BIT_DIS_RXDMA_PRE_V1_8814B BIT(30)
+
+#define BIT_SHIFT_HPS_CLKR_PCIE_V1_8814B 28
+#define BIT_MASK_HPS_CLKR_PCIE_V1_8814B 0x3
+#define BIT_HPS_CLKR_PCIE_V1_8814B(x) \
+ (((x) & BIT_MASK_HPS_CLKR_PCIE_V1_8814B) \
+ << BIT_SHIFT_HPS_CLKR_PCIE_V1_8814B)
+#define BITS_HPS_CLKR_PCIE_V1_8814B \
+ (BIT_MASK_HPS_CLKR_PCIE_V1_8814B << BIT_SHIFT_HPS_CLKR_PCIE_V1_8814B)
+#define BIT_CLEAR_HPS_CLKR_PCIE_V1_8814B(x) \
+ ((x) & (~BITS_HPS_CLKR_PCIE_V1_8814B))
+#define BIT_GET_HPS_CLKR_PCIE_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_HPS_CLKR_PCIE_V1_8814B) & \
+ BIT_MASK_HPS_CLKR_PCIE_V1_8814B)
+#define BIT_SET_HPS_CLKR_PCIE_V1_8814B(x, v) \
+ (BIT_CLEAR_HPS_CLKR_PCIE_V1_8814B(x) | BIT_HPS_CLKR_PCIE_V1_8814B(v))
+
+#define BIT_PCIE_INT_V1_8814B BIT(27)
+#define BIT_TXFLAG_EXIT_L1_EN_V1_8814B BIT(26)
+#define BIT_EN_RXDMA_ALIGN_V2_8814B BIT(25)
+#define BIT_EN_TXDMA_ALIGN_V2_8814B BIT(24)
+
+#define BIT_SHIFT_PCIE_HCPWM_V1_8814B 16
+#define BIT_MASK_PCIE_HCPWM_V1_8814B 0xff
+#define BIT_PCIE_HCPWM_V1_8814B(x) \
+ (((x) & BIT_MASK_PCIE_HCPWM_V1_8814B) << BIT_SHIFT_PCIE_HCPWM_V1_8814B)
+#define BITS_PCIE_HCPWM_V1_8814B \
+ (BIT_MASK_PCIE_HCPWM_V1_8814B << BIT_SHIFT_PCIE_HCPWM_V1_8814B)
+#define BIT_CLEAR_PCIE_HCPWM_V1_8814B(x) ((x) & (~BITS_PCIE_HCPWM_V1_8814B))
+#define BIT_GET_PCIE_HCPWM_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_PCIE_HCPWM_V1_8814B) & BIT_MASK_PCIE_HCPWM_V1_8814B)
+#define BIT_SET_PCIE_HCPWM_V1_8814B(x, v) \
+ (BIT_CLEAR_PCIE_HCPWM_V1_8814B(x) | BIT_PCIE_HCPWM_V1_8814B(v))
+
+#define BIT_SHIFT_PCIE_HRPWM_V1_8814B 8
+#define BIT_MASK_PCIE_HRPWM_V1_8814B 0xff
+#define BIT_PCIE_HRPWM_V1_8814B(x) \
+ (((x) & BIT_MASK_PCIE_HRPWM_V1_8814B) << BIT_SHIFT_PCIE_HRPWM_V1_8814B)
+#define BITS_PCIE_HRPWM_V1_8814B \
+ (BIT_MASK_PCIE_HRPWM_V1_8814B << BIT_SHIFT_PCIE_HRPWM_V1_8814B)
+#define BIT_CLEAR_PCIE_HRPWM_V1_8814B(x) ((x) & (~BITS_PCIE_HRPWM_V1_8814B))
+#define BIT_GET_PCIE_HRPWM_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_PCIE_HRPWM_V1_8814B) & BIT_MASK_PCIE_HRPWM_V1_8814B)
+#define BIT_SET_PCIE_HRPWM_V1_8814B(x, v) \
+ (BIT_CLEAR_PCIE_HRPWM_V1_8814B(x) | BIT_PCIE_HRPWM_V1_8814B(v))
+
+#define BIT_SHIFT_DBG_SEL_8814B 0
+#define BIT_MASK_DBG_SEL_8814B 0xff
+#define BIT_DBG_SEL_8814B(x) \
+ (((x) & BIT_MASK_DBG_SEL_8814B) << BIT_SHIFT_DBG_SEL_8814B)
+#define BITS_DBG_SEL_8814B (BIT_MASK_DBG_SEL_8814B << BIT_SHIFT_DBG_SEL_8814B)
+#define BIT_CLEAR_DBG_SEL_8814B(x) ((x) & (~BITS_DBG_SEL_8814B))
+#define BIT_GET_DBG_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_DBG_SEL_8814B) & BIT_MASK_DBG_SEL_8814B)
+#define BIT_SET_DBG_SEL_8814B(x, v) \
+ (BIT_CLEAR_DBG_SEL_8814B(x) | BIT_DBG_SEL_8814B(v))
+
+/* 2 REG_PCIE_HRPWM2_HCPWM2_V1_8814B */
+
+#define BIT_SHIFT_PCIE_HCPWM2_V1_8814B 16
+#define BIT_MASK_PCIE_HCPWM2_V1_8814B 0xffff
+#define BIT_PCIE_HCPWM2_V1_8814B(x) \
+ (((x) & BIT_MASK_PCIE_HCPWM2_V1_8814B) \
+ << BIT_SHIFT_PCIE_HCPWM2_V1_8814B)
+#define BITS_PCIE_HCPWM2_V1_8814B \
+ (BIT_MASK_PCIE_HCPWM2_V1_8814B << BIT_SHIFT_PCIE_HCPWM2_V1_8814B)
+#define BIT_CLEAR_PCIE_HCPWM2_V1_8814B(x) ((x) & (~BITS_PCIE_HCPWM2_V1_8814B))
+#define BIT_GET_PCIE_HCPWM2_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_PCIE_HCPWM2_V1_8814B) & \
+ BIT_MASK_PCIE_HCPWM2_V1_8814B)
+#define BIT_SET_PCIE_HCPWM2_V1_8814B(x, v) \
+ (BIT_CLEAR_PCIE_HCPWM2_V1_8814B(x) | BIT_PCIE_HCPWM2_V1_8814B(v))
+
+#define BIT_SHIFT_PCIE_HRPWM2_8814B 0
+#define BIT_MASK_PCIE_HRPWM2_8814B 0xffff
+#define BIT_PCIE_HRPWM2_8814B(x) \
+ (((x) & BIT_MASK_PCIE_HRPWM2_8814B) << BIT_SHIFT_PCIE_HRPWM2_8814B)
+#define BITS_PCIE_HRPWM2_8814B \
+ (BIT_MASK_PCIE_HRPWM2_8814B << BIT_SHIFT_PCIE_HRPWM2_8814B)
+#define BIT_CLEAR_PCIE_HRPWM2_8814B(x) ((x) & (~BITS_PCIE_HRPWM2_8814B))
+#define BIT_GET_PCIE_HRPWM2_8814B(x) \
+ (((x) >> BIT_SHIFT_PCIE_HRPWM2_8814B) & BIT_MASK_PCIE_HRPWM2_8814B)
+#define BIT_SET_PCIE_HRPWM2_8814B(x, v) \
+ (BIT_CLEAR_PCIE_HRPWM2_8814B(x) | BIT_PCIE_HRPWM2_8814B(v))
+
+/* 2 REG_PCIE_H2C_MSG_V1_8814B */
+
+#define BIT_SHIFT_DRV2FW_INFO_8814B 0
+#define BIT_MASK_DRV2FW_INFO_8814B 0xffffffffL
+#define BIT_DRV2FW_INFO_8814B(x) \
+ (((x) & BIT_MASK_DRV2FW_INFO_8814B) << BIT_SHIFT_DRV2FW_INFO_8814B)
+#define BITS_DRV2FW_INFO_8814B \
+ (BIT_MASK_DRV2FW_INFO_8814B << BIT_SHIFT_DRV2FW_INFO_8814B)
+#define BIT_CLEAR_DRV2FW_INFO_8814B(x) ((x) & (~BITS_DRV2FW_INFO_8814B))
+#define BIT_GET_DRV2FW_INFO_8814B(x) \
+ (((x) >> BIT_SHIFT_DRV2FW_INFO_8814B) & BIT_MASK_DRV2FW_INFO_8814B)
+#define BIT_SET_DRV2FW_INFO_8814B(x, v) \
+ (BIT_CLEAR_DRV2FW_INFO_8814B(x) | BIT_DRV2FW_INFO_8814B(v))
+
+/* 2 REG_PCIE_C2H_MSG_V1_8814B */
+
+#define BIT_SHIFT_HCI_PCIE_C2H_MSG_8814B 0
+#define BIT_MASK_HCI_PCIE_C2H_MSG_8814B 0xffffffffL
+#define BIT_HCI_PCIE_C2H_MSG_8814B(x) \
+ (((x) & BIT_MASK_HCI_PCIE_C2H_MSG_8814B) \
+ << BIT_SHIFT_HCI_PCIE_C2H_MSG_8814B)
+#define BITS_HCI_PCIE_C2H_MSG_8814B \
+ (BIT_MASK_HCI_PCIE_C2H_MSG_8814B << BIT_SHIFT_HCI_PCIE_C2H_MSG_8814B)
+#define BIT_CLEAR_HCI_PCIE_C2H_MSG_8814B(x) \
+ ((x) & (~BITS_HCI_PCIE_C2H_MSG_8814B))
+#define BIT_GET_HCI_PCIE_C2H_MSG_8814B(x) \
+ (((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG_8814B) & \
+ BIT_MASK_HCI_PCIE_C2H_MSG_8814B)
+#define BIT_SET_HCI_PCIE_C2H_MSG_8814B(x, v) \
+ (BIT_CLEAR_HCI_PCIE_C2H_MSG_8814B(x) | BIT_HCI_PCIE_C2H_MSG_8814B(v))
+
+/* 2 REG_DBI_WDATA_V1_8814B */
+
+#define BIT_SHIFT_DBI_WDATA_8814B 0
+#define BIT_MASK_DBI_WDATA_8814B 0xffffffffL
+#define BIT_DBI_WDATA_8814B(x) \
+ (((x) & BIT_MASK_DBI_WDATA_8814B) << BIT_SHIFT_DBI_WDATA_8814B)
+#define BITS_DBI_WDATA_8814B \
+ (BIT_MASK_DBI_WDATA_8814B << BIT_SHIFT_DBI_WDATA_8814B)
+#define BIT_CLEAR_DBI_WDATA_8814B(x) ((x) & (~BITS_DBI_WDATA_8814B))
+#define BIT_GET_DBI_WDATA_8814B(x) \
+ (((x) >> BIT_SHIFT_DBI_WDATA_8814B) & BIT_MASK_DBI_WDATA_8814B)
+#define BIT_SET_DBI_WDATA_8814B(x, v) \
+ (BIT_CLEAR_DBI_WDATA_8814B(x) | BIT_DBI_WDATA_8814B(v))
+
+/* 2 REG_DBI_RDATA_V1_8814B */
+
+#define BIT_SHIFT_DBI_RDATA_8814B 0
+#define BIT_MASK_DBI_RDATA_8814B 0xffffffffL
+#define BIT_DBI_RDATA_8814B(x) \
+ (((x) & BIT_MASK_DBI_RDATA_8814B) << BIT_SHIFT_DBI_RDATA_8814B)
+#define BITS_DBI_RDATA_8814B \
+ (BIT_MASK_DBI_RDATA_8814B << BIT_SHIFT_DBI_RDATA_8814B)
+#define BIT_CLEAR_DBI_RDATA_8814B(x) ((x) & (~BITS_DBI_RDATA_8814B))
+#define BIT_GET_DBI_RDATA_8814B(x) \
+ (((x) >> BIT_SHIFT_DBI_RDATA_8814B) & BIT_MASK_DBI_RDATA_8814B)
+#define BIT_SET_DBI_RDATA_8814B(x, v) \
+ (BIT_CLEAR_DBI_RDATA_8814B(x) | BIT_DBI_RDATA_8814B(v))
+
+/* 2 REG_DBI_FLAG_V1_8814B */
+
+#define BIT_SHIFT_LOOPBACK_DBG_SEL_8814B 28
+#define BIT_MASK_LOOPBACK_DBG_SEL_8814B 0xf
+#define BIT_LOOPBACK_DBG_SEL_8814B(x) \
+ (((x) & BIT_MASK_LOOPBACK_DBG_SEL_8814B) \
+ << BIT_SHIFT_LOOPBACK_DBG_SEL_8814B)
+#define BITS_LOOPBACK_DBG_SEL_8814B \
+ (BIT_MASK_LOOPBACK_DBG_SEL_8814B << BIT_SHIFT_LOOPBACK_DBG_SEL_8814B)
+#define BIT_CLEAR_LOOPBACK_DBG_SEL_8814B(x) \
+ ((x) & (~BITS_LOOPBACK_DBG_SEL_8814B))
+#define BIT_GET_LOOPBACK_DBG_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_LOOPBACK_DBG_SEL_8814B) & \
+ BIT_MASK_LOOPBACK_DBG_SEL_8814B)
+#define BIT_SET_LOOPBACK_DBG_SEL_8814B(x, v) \
+ (BIT_CLEAR_LOOPBACK_DBG_SEL_8814B(x) | BIT_LOOPBACK_DBG_SEL_8814B(v))
+
+#define BIT_EN_STUCK_DBG_8814B BIT(26)
+#define BIT_RX_STUCK_8814B BIT(25)
+#define BIT_TX_STUCK_8814B BIT(24)
+#define BIT_DBI_RFLAG_8814B BIT(17)
+#define BIT_DBI_WFLAG_8814B BIT(16)
+
+#define BIT_SHIFT_DBI_WREN_8814B 12
+#define BIT_MASK_DBI_WREN_8814B 0xf
+#define BIT_DBI_WREN_8814B(x) \
+ (((x) & BIT_MASK_DBI_WREN_8814B) << BIT_SHIFT_DBI_WREN_8814B)
+#define BITS_DBI_WREN_8814B \
+ (BIT_MASK_DBI_WREN_8814B << BIT_SHIFT_DBI_WREN_8814B)
+#define BIT_CLEAR_DBI_WREN_8814B(x) ((x) & (~BITS_DBI_WREN_8814B))
+#define BIT_GET_DBI_WREN_8814B(x) \
+ (((x) >> BIT_SHIFT_DBI_WREN_8814B) & BIT_MASK_DBI_WREN_8814B)
+#define BIT_SET_DBI_WREN_8814B(x, v) \
+ (BIT_CLEAR_DBI_WREN_8814B(x) | BIT_DBI_WREN_8814B(v))
+
+#define BIT_SHIFT_DBI_ADDR_8814B 0
+#define BIT_MASK_DBI_ADDR_8814B 0xfff
+#define BIT_DBI_ADDR_8814B(x) \
+ (((x) & BIT_MASK_DBI_ADDR_8814B) << BIT_SHIFT_DBI_ADDR_8814B)
+#define BITS_DBI_ADDR_8814B \
+ (BIT_MASK_DBI_ADDR_8814B << BIT_SHIFT_DBI_ADDR_8814B)
+#define BIT_CLEAR_DBI_ADDR_8814B(x) ((x) & (~BITS_DBI_ADDR_8814B))
+#define BIT_GET_DBI_ADDR_8814B(x) \
+ (((x) >> BIT_SHIFT_DBI_ADDR_8814B) & BIT_MASK_DBI_ADDR_8814B)
+#define BIT_SET_DBI_ADDR_8814B(x, v) \
+ (BIT_CLEAR_DBI_ADDR_8814B(x) | BIT_DBI_ADDR_8814B(v))
+
+/* 2 REG_MDIO_V1_8814B */
+
+#define BIT_SHIFT_MDIO_RDATA_8814B 16
+#define BIT_MASK_MDIO_RDATA_8814B 0xffff
+#define BIT_MDIO_RDATA_8814B(x) \
+ (((x) & BIT_MASK_MDIO_RDATA_8814B) << BIT_SHIFT_MDIO_RDATA_8814B)
+#define BITS_MDIO_RDATA_8814B \
+ (BIT_MASK_MDIO_RDATA_8814B << BIT_SHIFT_MDIO_RDATA_8814B)
+#define BIT_CLEAR_MDIO_RDATA_8814B(x) ((x) & (~BITS_MDIO_RDATA_8814B))
+#define BIT_GET_MDIO_RDATA_8814B(x) \
+ (((x) >> BIT_SHIFT_MDIO_RDATA_8814B) & BIT_MASK_MDIO_RDATA_8814B)
+#define BIT_SET_MDIO_RDATA_8814B(x, v) \
+ (BIT_CLEAR_MDIO_RDATA_8814B(x) | BIT_MDIO_RDATA_8814B(v))
+
+#define BIT_SHIFT_MDIO_WDATA_8814B 0
+#define BIT_MASK_MDIO_WDATA_8814B 0xffff
+#define BIT_MDIO_WDATA_8814B(x) \
+ (((x) & BIT_MASK_MDIO_WDATA_8814B) << BIT_SHIFT_MDIO_WDATA_8814B)
+#define BITS_MDIO_WDATA_8814B \
+ (BIT_MASK_MDIO_WDATA_8814B << BIT_SHIFT_MDIO_WDATA_8814B)
+#define BIT_CLEAR_MDIO_WDATA_8814B(x) ((x) & (~BITS_MDIO_WDATA_8814B))
+#define BIT_GET_MDIO_WDATA_8814B(x) \
+ (((x) >> BIT_SHIFT_MDIO_WDATA_8814B) & BIT_MASK_MDIO_WDATA_8814B)
+#define BIT_SET_MDIO_WDATA_8814B(x, v) \
+ (BIT_CLEAR_MDIO_WDATA_8814B(x) | BIT_MDIO_WDATA_8814B(v))
+
+/* 2 REG_PCIE_MIX_CFG_8814B */
+
+#define BIT_SHIFT_MDIO_PHY_ADDR_8814B 24
+#define BIT_MASK_MDIO_PHY_ADDR_8814B 0x1f
+#define BIT_MDIO_PHY_ADDR_8814B(x) \
+ (((x) & BIT_MASK_MDIO_PHY_ADDR_8814B) << BIT_SHIFT_MDIO_PHY_ADDR_8814B)
+#define BITS_MDIO_PHY_ADDR_8814B \
+ (BIT_MASK_MDIO_PHY_ADDR_8814B << BIT_SHIFT_MDIO_PHY_ADDR_8814B)
+#define BIT_CLEAR_MDIO_PHY_ADDR_8814B(x) ((x) & (~BITS_MDIO_PHY_ADDR_8814B))
+#define BIT_GET_MDIO_PHY_ADDR_8814B(x) \
+ (((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8814B) & BIT_MASK_MDIO_PHY_ADDR_8814B)
+#define BIT_SET_MDIO_PHY_ADDR_8814B(x, v) \
+ (BIT_CLEAR_MDIO_PHY_ADDR_8814B(x) | BIT_MDIO_PHY_ADDR_8814B(v))
+
+#define BIT_SHIFT_WATCH_DOG_RECORD_V1_8814B 10
+#define BIT_MASK_WATCH_DOG_RECORD_V1_8814B 0x3fff
+#define BIT_WATCH_DOG_RECORD_V1_8814B(x) \
+ (((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8814B) \
+ << BIT_SHIFT_WATCH_DOG_RECORD_V1_8814B)
+#define BITS_WATCH_DOG_RECORD_V1_8814B \
+ (BIT_MASK_WATCH_DOG_RECORD_V1_8814B \
+ << BIT_SHIFT_WATCH_DOG_RECORD_V1_8814B)
+#define BIT_CLEAR_WATCH_DOG_RECORD_V1_8814B(x) \
+ ((x) & (~BITS_WATCH_DOG_RECORD_V1_8814B))
+#define BIT_GET_WATCH_DOG_RECORD_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8814B) & \
+ BIT_MASK_WATCH_DOG_RECORD_V1_8814B)
+#define BIT_SET_WATCH_DOG_RECORD_V1_8814B(x, v) \
+ (BIT_CLEAR_WATCH_DOG_RECORD_V1_8814B(x) | \
+ BIT_WATCH_DOG_RECORD_V1_8814B(v))
+
+#define BIT_R_IO_TIMEOUT_FLAG_V1_8814B BIT(9)
+#define BIT_EN_WATCH_DOG_8814B BIT(8)
+#define BIT_ECRC_EN_8814B BIT(7)
+#define BIT_MDIO_RFLAG_8814B BIT(6)
+#define BIT_MDIO_WFLAG_8814B BIT(5)
+
+#define BIT_SHIFT_MDIO_REG_ADDR_8814B 0
+#define BIT_MASK_MDIO_REG_ADDR_8814B 0x1f
+#define BIT_MDIO_REG_ADDR_8814B(x) \
+ (((x) & BIT_MASK_MDIO_REG_ADDR_8814B) << BIT_SHIFT_MDIO_REG_ADDR_8814B)
+#define BITS_MDIO_REG_ADDR_8814B \
+ (BIT_MASK_MDIO_REG_ADDR_8814B << BIT_SHIFT_MDIO_REG_ADDR_8814B)
+#define BIT_CLEAR_MDIO_REG_ADDR_8814B(x) ((x) & (~BITS_MDIO_REG_ADDR_8814B))
+#define BIT_GET_MDIO_REG_ADDR_8814B(x) \
+ (((x) >> BIT_SHIFT_MDIO_REG_ADDR_8814B) & BIT_MASK_MDIO_REG_ADDR_8814B)
+#define BIT_SET_MDIO_REG_ADDR_8814B(x, v) \
+ (BIT_CLEAR_MDIO_REG_ADDR_8814B(x) | BIT_MDIO_REG_ADDR_8814B(v))
+
+/* 2 REG_HCI_MIX_CFG_8814B */
+#define BIT_EN_ALIGN_MTU_8814B BIT(23)
+
+#define BIT_SHIFT_LATENCY_CONTROL_8814B 21
+#define BIT_MASK_LATENCY_CONTROL_8814B 0x3
+#define BIT_LATENCY_CONTROL_8814B(x) \
+ (((x) & BIT_MASK_LATENCY_CONTROL_8814B) \
+ << BIT_SHIFT_LATENCY_CONTROL_8814B)
+#define BITS_LATENCY_CONTROL_8814B \
+ (BIT_MASK_LATENCY_CONTROL_8814B << BIT_SHIFT_LATENCY_CONTROL_8814B)
+#define BIT_CLEAR_LATENCY_CONTROL_8814B(x) ((x) & (~BITS_LATENCY_CONTROL_8814B))
+#define BIT_GET_LATENCY_CONTROL_8814B(x) \
+ (((x) >> BIT_SHIFT_LATENCY_CONTROL_8814B) & \
+ BIT_MASK_LATENCY_CONTROL_8814B)
+#define BIT_SET_LATENCY_CONTROL_8814B(x, v) \
+ (BIT_CLEAR_LATENCY_CONTROL_8814B(x) | BIT_LATENCY_CONTROL_8814B(v))
+
+#define BIT_HOST_GEN2_SUPPORT_8814B BIT(20)
+
+#define BIT_SHIFT_TXDMA_ERR_FLAG_V1_8814B 15
+#define BIT_MASK_TXDMA_ERR_FLAG_V1_8814B 0x1f
+#define BIT_TXDMA_ERR_FLAG_V1_8814B(x) \
+ (((x) & BIT_MASK_TXDMA_ERR_FLAG_V1_8814B) \
+ << BIT_SHIFT_TXDMA_ERR_FLAG_V1_8814B)
+#define BITS_TXDMA_ERR_FLAG_V1_8814B \
+ (BIT_MASK_TXDMA_ERR_FLAG_V1_8814B << BIT_SHIFT_TXDMA_ERR_FLAG_V1_8814B)
+#define BIT_CLEAR_TXDMA_ERR_FLAG_V1_8814B(x) \
+ ((x) & (~BITS_TXDMA_ERR_FLAG_V1_8814B))
+#define BIT_GET_TXDMA_ERR_FLAG_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_V1_8814B) & \
+ BIT_MASK_TXDMA_ERR_FLAG_V1_8814B)
+#define BIT_SET_TXDMA_ERR_FLAG_V1_8814B(x, v) \
+ (BIT_CLEAR_TXDMA_ERR_FLAG_V1_8814B(x) | BIT_TXDMA_ERR_FLAG_V1_8814B(v))
+
+#define BIT_EPHY_RX50_EN_8814B BIT(11)
+
+#define BIT_SHIFT_MSI_TIMEOUT_ID_V1_8814B 8
+#define BIT_MASK_MSI_TIMEOUT_ID_V1_8814B 0x7
+#define BIT_MSI_TIMEOUT_ID_V1_8814B(x) \
+ (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8814B) \
+ << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8814B)
+#define BITS_MSI_TIMEOUT_ID_V1_8814B \
+ (BIT_MASK_MSI_TIMEOUT_ID_V1_8814B << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8814B)
+#define BIT_CLEAR_MSI_TIMEOUT_ID_V1_8814B(x) \
+ ((x) & (~BITS_MSI_TIMEOUT_ID_V1_8814B))
+#define BIT_GET_MSI_TIMEOUT_ID_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8814B) & \
+ BIT_MASK_MSI_TIMEOUT_ID_V1_8814B)
+#define BIT_SET_MSI_TIMEOUT_ID_V1_8814B(x, v) \
+ (BIT_CLEAR_MSI_TIMEOUT_ID_V1_8814B(x) | BIT_MSI_TIMEOUT_ID_V1_8814B(v))
+
+#define BIT_RADDR_RD_8814B BIT(7)
+#define BIT_L0S_LINK_OFF_8814B BIT(4)
+#define BIT_ACT_LINK_OFF_8814B BIT(3)
+#define BIT_EN_SLOW_MAC_TX_8814B BIT(2)
+#define BIT_EN_SLOW_MAC_RX_8814B BIT(1)
+#define BIT_EN_SLOW_MAC_HW_8814B BIT(0)
+
+/* 2 REG_STC_INT_CS_8814B(PCIE STATE CHANGE INTERRUPT CONTROL AND STATUS) */
+#define BIT_STC_INT_EN_8814B BIT(31)
+
+#define BIT_SHIFT_STC_INT_FLAG_8814B 16
+#define BIT_MASK_STC_INT_FLAG_8814B 0xff
+#define BIT_STC_INT_FLAG_8814B(x) \
+ (((x) & BIT_MASK_STC_INT_FLAG_8814B) << BIT_SHIFT_STC_INT_FLAG_8814B)
+#define BITS_STC_INT_FLAG_8814B \
+ (BIT_MASK_STC_INT_FLAG_8814B << BIT_SHIFT_STC_INT_FLAG_8814B)
+#define BIT_CLEAR_STC_INT_FLAG_8814B(x) ((x) & (~BITS_STC_INT_FLAG_8814B))
+#define BIT_GET_STC_INT_FLAG_8814B(x) \
+ (((x) >> BIT_SHIFT_STC_INT_FLAG_8814B) & BIT_MASK_STC_INT_FLAG_8814B)
+#define BIT_SET_STC_INT_FLAG_8814B(x, v) \
+ (BIT_CLEAR_STC_INT_FLAG_8814B(x) | BIT_STC_INT_FLAG_8814B(v))
+
+#define BIT_SHIFT_STC_INT_IDX_8814B 8
+#define BIT_MASK_STC_INT_IDX_8814B 0x7
+#define BIT_STC_INT_IDX_8814B(x) \
+ (((x) & BIT_MASK_STC_INT_IDX_8814B) << BIT_SHIFT_STC_INT_IDX_8814B)
+#define BITS_STC_INT_IDX_8814B \
+ (BIT_MASK_STC_INT_IDX_8814B << BIT_SHIFT_STC_INT_IDX_8814B)
+#define BIT_CLEAR_STC_INT_IDX_8814B(x) ((x) & (~BITS_STC_INT_IDX_8814B))
+#define BIT_GET_STC_INT_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_STC_INT_IDX_8814B) & BIT_MASK_STC_INT_IDX_8814B)
+#define BIT_SET_STC_INT_IDX_8814B(x, v) \
+ (BIT_CLEAR_STC_INT_IDX_8814B(x) | BIT_STC_INT_IDX_8814B(v))
+
+#define BIT_SHIFT_STC_INT_REALTIME_CS_8814B 0
+#define BIT_MASK_STC_INT_REALTIME_CS_8814B 0x3f
+#define BIT_STC_INT_REALTIME_CS_8814B(x) \
+ (((x) & BIT_MASK_STC_INT_REALTIME_CS_8814B) \
+ << BIT_SHIFT_STC_INT_REALTIME_CS_8814B)
+#define BITS_STC_INT_REALTIME_CS_8814B \
+ (BIT_MASK_STC_INT_REALTIME_CS_8814B \
+ << BIT_SHIFT_STC_INT_REALTIME_CS_8814B)
+#define BIT_CLEAR_STC_INT_REALTIME_CS_8814B(x) \
+ ((x) & (~BITS_STC_INT_REALTIME_CS_8814B))
+#define BIT_GET_STC_INT_REALTIME_CS_8814B(x) \
+ (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8814B) & \
+ BIT_MASK_STC_INT_REALTIME_CS_8814B)
+#define BIT_SET_STC_INT_REALTIME_CS_8814B(x, v) \
+ (BIT_CLEAR_STC_INT_REALTIME_CS_8814B(x) | \
+ BIT_STC_INT_REALTIME_CS_8814B(v))
+
+/* 2 REG_ST_INT_CFG_8814B(PCIE STATE CHANGE INTERRUPT CONFIGURATION) */
+#define BIT_STC_INT_GRP_EN_8814B BIT(31)
+
+#define BIT_SHIFT_STC_INT_EXPECT_LS_8814B 8
+#define BIT_MASK_STC_INT_EXPECT_LS_8814B 0x3f
+#define BIT_STC_INT_EXPECT_LS_8814B(x) \
+ (((x) & BIT_MASK_STC_INT_EXPECT_LS_8814B) \
+ << BIT_SHIFT_STC_INT_EXPECT_LS_8814B)
+#define BITS_STC_INT_EXPECT_LS_8814B \
+ (BIT_MASK_STC_INT_EXPECT_LS_8814B << BIT_SHIFT_STC_INT_EXPECT_LS_8814B)
+#define BIT_CLEAR_STC_INT_EXPECT_LS_8814B(x) \
+ ((x) & (~BITS_STC_INT_EXPECT_LS_8814B))
+#define BIT_GET_STC_INT_EXPECT_LS_8814B(x) \
+ (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8814B) & \
+ BIT_MASK_STC_INT_EXPECT_LS_8814B)
+#define BIT_SET_STC_INT_EXPECT_LS_8814B(x, v) \
+ (BIT_CLEAR_STC_INT_EXPECT_LS_8814B(x) | BIT_STC_INT_EXPECT_LS_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_STC_INT_EXPECT_CS_8814B 0
+#define BIT_MASK_STC_INT_EXPECT_CS_8814B 0x3f
+#define BIT_STC_INT_EXPECT_CS_8814B(x) \
+ (((x) & BIT_MASK_STC_INT_EXPECT_CS_8814B) \
+ << BIT_SHIFT_STC_INT_EXPECT_CS_8814B)
+#define BITS_STC_INT_EXPECT_CS_8814B \
+ (BIT_MASK_STC_INT_EXPECT_CS_8814B << BIT_SHIFT_STC_INT_EXPECT_CS_8814B)
+#define BIT_CLEAR_STC_INT_EXPECT_CS_8814B(x) \
+ ((x) & (~BITS_STC_INT_EXPECT_CS_8814B))
+#define BIT_GET_STC_INT_EXPECT_CS_8814B(x) \
+ (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8814B) & \
+ BIT_MASK_STC_INT_EXPECT_CS_8814B)
+#define BIT_SET_STC_INT_EXPECT_CS_8814B(x, v) \
+ (BIT_CLEAR_STC_INT_EXPECT_CS_8814B(x) | BIT_STC_INT_EXPECT_CS_8814B(v))
+
+/* 2 REG_ACH4_ACH5_TXBD_NUM_8814B */
+#define BIT_PCIE_ACH5_FLAG_8814B BIT(30)
+
+#define BIT_SHIFT_ACH5_DESC_MODE_8814B 28
+#define BIT_MASK_ACH5_DESC_MODE_8814B 0x3
+#define BIT_ACH5_DESC_MODE_8814B(x) \
+ (((x) & BIT_MASK_ACH5_DESC_MODE_8814B) \
+ << BIT_SHIFT_ACH5_DESC_MODE_8814B)
+#define BITS_ACH5_DESC_MODE_8814B \
+ (BIT_MASK_ACH5_DESC_MODE_8814B << BIT_SHIFT_ACH5_DESC_MODE_8814B)
+#define BIT_CLEAR_ACH5_DESC_MODE_8814B(x) ((x) & (~BITS_ACH5_DESC_MODE_8814B))
+#define BIT_GET_ACH5_DESC_MODE_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH5_DESC_MODE_8814B) & \
+ BIT_MASK_ACH5_DESC_MODE_8814B)
+#define BIT_SET_ACH5_DESC_MODE_8814B(x, v) \
+ (BIT_CLEAR_ACH5_DESC_MODE_8814B(x) | BIT_ACH5_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_ACH5_DESC_NUM_8814B 16
+#define BIT_MASK_ACH5_DESC_NUM_8814B 0xfff
+#define BIT_ACH5_DESC_NUM_8814B(x) \
+ (((x) & BIT_MASK_ACH5_DESC_NUM_8814B) << BIT_SHIFT_ACH5_DESC_NUM_8814B)
+#define BITS_ACH5_DESC_NUM_8814B \
+ (BIT_MASK_ACH5_DESC_NUM_8814B << BIT_SHIFT_ACH5_DESC_NUM_8814B)
+#define BIT_CLEAR_ACH5_DESC_NUM_8814B(x) ((x) & (~BITS_ACH5_DESC_NUM_8814B))
+#define BIT_GET_ACH5_DESC_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH5_DESC_NUM_8814B) & BIT_MASK_ACH5_DESC_NUM_8814B)
+#define BIT_SET_ACH5_DESC_NUM_8814B(x, v) \
+ (BIT_CLEAR_ACH5_DESC_NUM_8814B(x) | BIT_ACH5_DESC_NUM_8814B(v))
+
+#define BIT_PCIE_ACH4_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_ACH4_DESC_MODE_8814B 12
+#define BIT_MASK_ACH4_DESC_MODE_8814B 0x3
+#define BIT_ACH4_DESC_MODE_8814B(x) \
+ (((x) & BIT_MASK_ACH4_DESC_MODE_8814B) \
+ << BIT_SHIFT_ACH4_DESC_MODE_8814B)
+#define BITS_ACH4_DESC_MODE_8814B \
+ (BIT_MASK_ACH4_DESC_MODE_8814B << BIT_SHIFT_ACH4_DESC_MODE_8814B)
+#define BIT_CLEAR_ACH4_DESC_MODE_8814B(x) ((x) & (~BITS_ACH4_DESC_MODE_8814B))
+#define BIT_GET_ACH4_DESC_MODE_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH4_DESC_MODE_8814B) & \
+ BIT_MASK_ACH4_DESC_MODE_8814B)
+#define BIT_SET_ACH4_DESC_MODE_8814B(x, v) \
+ (BIT_CLEAR_ACH4_DESC_MODE_8814B(x) | BIT_ACH4_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_ACH4_DESC_NUM_8814B 0
+#define BIT_MASK_ACH4_DESC_NUM_8814B 0xfff
+#define BIT_ACH4_DESC_NUM_8814B(x) \
+ (((x) & BIT_MASK_ACH4_DESC_NUM_8814B) << BIT_SHIFT_ACH4_DESC_NUM_8814B)
+#define BITS_ACH4_DESC_NUM_8814B \
+ (BIT_MASK_ACH4_DESC_NUM_8814B << BIT_SHIFT_ACH4_DESC_NUM_8814B)
+#define BIT_CLEAR_ACH4_DESC_NUM_8814B(x) ((x) & (~BITS_ACH4_DESC_NUM_8814B))
+#define BIT_GET_ACH4_DESC_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH4_DESC_NUM_8814B) & BIT_MASK_ACH4_DESC_NUM_8814B)
+#define BIT_SET_ACH4_DESC_NUM_8814B(x, v) \
+ (BIT_CLEAR_ACH4_DESC_NUM_8814B(x) | BIT_ACH4_DESC_NUM_8814B(v))
+
+/* 2 REG_FWCMDQ_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_FWCMDQ_HW_IDX_8814B 16
+#define BIT_MASK_FWCMDQ_HW_IDX_8814B 0xfff
+#define BIT_FWCMDQ_HW_IDX_8814B(x) \
+ (((x) & BIT_MASK_FWCMDQ_HW_IDX_8814B) << BIT_SHIFT_FWCMDQ_HW_IDX_8814B)
+#define BITS_FWCMDQ_HW_IDX_8814B \
+ (BIT_MASK_FWCMDQ_HW_IDX_8814B << BIT_SHIFT_FWCMDQ_HW_IDX_8814B)
+#define BIT_CLEAR_FWCMDQ_HW_IDX_8814B(x) ((x) & (~BITS_FWCMDQ_HW_IDX_8814B))
+#define BIT_GET_FWCMDQ_HW_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_FWCMDQ_HW_IDX_8814B) & BIT_MASK_FWCMDQ_HW_IDX_8814B)
+#define BIT_SET_FWCMDQ_HW_IDX_8814B(x, v) \
+ (BIT_CLEAR_FWCMDQ_HW_IDX_8814B(x) | BIT_FWCMDQ_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_FWCMDQ_HOST_IDX_8814B 0
+#define BIT_MASK_FWCMDQ_HOST_IDX_8814B 0xfff
+#define BIT_FWCMDQ_HOST_IDX_8814B(x) \
+ (((x) & BIT_MASK_FWCMDQ_HOST_IDX_8814B) \
+ << BIT_SHIFT_FWCMDQ_HOST_IDX_8814B)
+#define BITS_FWCMDQ_HOST_IDX_8814B \
+ (BIT_MASK_FWCMDQ_HOST_IDX_8814B << BIT_SHIFT_FWCMDQ_HOST_IDX_8814B)
+#define BIT_CLEAR_FWCMDQ_HOST_IDX_8814B(x) ((x) & (~BITS_FWCMDQ_HOST_IDX_8814B))
+#define BIT_GET_FWCMDQ_HOST_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_FWCMDQ_HOST_IDX_8814B) & \
+ BIT_MASK_FWCMDQ_HOST_IDX_8814B)
+#define BIT_SET_FWCMDQ_HOST_IDX_8814B(x, v) \
+ (BIT_CLEAR_FWCMDQ_HOST_IDX_8814B(x) | BIT_FWCMDQ_HOST_IDX_8814B(v))
+
+/* 2 REG_P0HI8Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI8Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI8Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI8Q_HW_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI8Q_HW_IDX_8814B) << BIT_SHIFT_P0HI8Q_HW_IDX_8814B)
+#define BITS_P0HI8Q_HW_IDX_8814B \
+ (BIT_MASK_P0HI8Q_HW_IDX_8814B << BIT_SHIFT_P0HI8Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI8Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI8Q_HW_IDX_8814B))
+#define BIT_GET_P0HI8Q_HW_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI8Q_HW_IDX_8814B) & BIT_MASK_P0HI8Q_HW_IDX_8814B)
+#define BIT_SET_P0HI8Q_HW_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI8Q_HW_IDX_8814B(x) | BIT_P0HI8Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI8Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI8Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI8Q_HOST_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI8Q_HOST_IDX_8814B) \
+ << BIT_SHIFT_P0HI8Q_HOST_IDX_8814B)
+#define BITS_P0HI8Q_HOST_IDX_8814B \
+ (BIT_MASK_P0HI8Q_HOST_IDX_8814B << BIT_SHIFT_P0HI8Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI8Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI8Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI8Q_HOST_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI8Q_HOST_IDX_8814B) & \
+ BIT_MASK_P0HI8Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI8Q_HOST_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI8Q_HOST_IDX_8814B(x) | BIT_P0HI8Q_HOST_IDX_8814B(v))
+
+/* 2 REG_H2CQ_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_H2CQ_TXBD_DESA_L_8814B 0
+#define BIT_MASK_H2CQ_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_H2CQ_TXBD_DESA_L_8814B(x) \
+ (((x) & BIT_MASK_H2CQ_TXBD_DESA_L_8814B) \
+ << BIT_SHIFT_H2CQ_TXBD_DESA_L_8814B)
+#define BITS_H2CQ_TXBD_DESA_L_8814B \
+ (BIT_MASK_H2CQ_TXBD_DESA_L_8814B << BIT_SHIFT_H2CQ_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_H2CQ_TXBD_DESA_L_8814B(x) \
+ ((x) & (~BITS_H2CQ_TXBD_DESA_L_8814B))
+#define BIT_GET_H2CQ_TXBD_DESA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_L_8814B) & \
+ BIT_MASK_H2CQ_TXBD_DESA_L_8814B)
+#define BIT_SET_H2CQ_TXBD_DESA_L_8814B(x, v) \
+ (BIT_CLEAR_H2CQ_TXBD_DESA_L_8814B(x) | BIT_H2CQ_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_H2CQ_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_H2CQ_TXBD_DESA_H_8814B 0
+#define BIT_MASK_H2CQ_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_H2CQ_TXBD_DESA_H_8814B(x) \
+ (((x) & BIT_MASK_H2CQ_TXBD_DESA_H_8814B) \
+ << BIT_SHIFT_H2CQ_TXBD_DESA_H_8814B)
+#define BITS_H2CQ_TXBD_DESA_H_8814B \
+ (BIT_MASK_H2CQ_TXBD_DESA_H_8814B << BIT_SHIFT_H2CQ_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_H2CQ_TXBD_DESA_H_8814B(x) \
+ ((x) & (~BITS_H2CQ_TXBD_DESA_H_8814B))
+#define BIT_GET_H2CQ_TXBD_DESA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_H_8814B) & \
+ BIT_MASK_H2CQ_TXBD_DESA_H_8814B)
+#define BIT_SET_H2CQ_TXBD_DESA_H_8814B(x, v) \
+ (BIT_CLEAR_H2CQ_TXBD_DESA_H_8814B(x) | BIT_H2CQ_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_H2CQ_TXBD_NUM_8814B */
+#define BIT_PCIE_H2CQ_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_H2CQ_DESC_MODE_8814B 12
+#define BIT_MASK_H2CQ_DESC_MODE_8814B 0x3
+#define BIT_H2CQ_DESC_MODE_8814B(x) \
+ (((x) & BIT_MASK_H2CQ_DESC_MODE_8814B) \
+ << BIT_SHIFT_H2CQ_DESC_MODE_8814B)
+#define BITS_H2CQ_DESC_MODE_8814B \
+ (BIT_MASK_H2CQ_DESC_MODE_8814B << BIT_SHIFT_H2CQ_DESC_MODE_8814B)
+#define BIT_CLEAR_H2CQ_DESC_MODE_8814B(x) ((x) & (~BITS_H2CQ_DESC_MODE_8814B))
+#define BIT_GET_H2CQ_DESC_MODE_8814B(x) \
+ (((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8814B) & \
+ BIT_MASK_H2CQ_DESC_MODE_8814B)
+#define BIT_SET_H2CQ_DESC_MODE_8814B(x, v) \
+ (BIT_CLEAR_H2CQ_DESC_MODE_8814B(x) | BIT_H2CQ_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_H2CQ_DESC_NUM_8814B 0
+#define BIT_MASK_H2CQ_DESC_NUM_8814B 0xfff
+#define BIT_H2CQ_DESC_NUM_8814B(x) \
+ (((x) & BIT_MASK_H2CQ_DESC_NUM_8814B) << BIT_SHIFT_H2CQ_DESC_NUM_8814B)
+#define BITS_H2CQ_DESC_NUM_8814B \
+ (BIT_MASK_H2CQ_DESC_NUM_8814B << BIT_SHIFT_H2CQ_DESC_NUM_8814B)
+#define BIT_CLEAR_H2CQ_DESC_NUM_8814B(x) ((x) & (~BITS_H2CQ_DESC_NUM_8814B))
+#define BIT_GET_H2CQ_DESC_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8814B) & BIT_MASK_H2CQ_DESC_NUM_8814B)
+#define BIT_SET_H2CQ_DESC_NUM_8814B(x, v) \
+ (BIT_CLEAR_H2CQ_DESC_NUM_8814B(x) | BIT_H2CQ_DESC_NUM_8814B(v))
+
+/* 2 REG_H2CQ_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_H2CQ_HW_IDX_8814B 16
+#define BIT_MASK_H2CQ_HW_IDX_8814B 0xfff
+#define BIT_H2CQ_HW_IDX_8814B(x) \
+ (((x) & BIT_MASK_H2CQ_HW_IDX_8814B) << BIT_SHIFT_H2CQ_HW_IDX_8814B)
+#define BITS_H2CQ_HW_IDX_8814B \
+ (BIT_MASK_H2CQ_HW_IDX_8814B << BIT_SHIFT_H2CQ_HW_IDX_8814B)
+#define BIT_CLEAR_H2CQ_HW_IDX_8814B(x) ((x) & (~BITS_H2CQ_HW_IDX_8814B))
+#define BIT_GET_H2CQ_HW_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_H2CQ_HW_IDX_8814B) & BIT_MASK_H2CQ_HW_IDX_8814B)
+#define BIT_SET_H2CQ_HW_IDX_8814B(x, v) \
+ (BIT_CLEAR_H2CQ_HW_IDX_8814B(x) | BIT_H2CQ_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_H2CQ_HOST_IDX_8814B 0
+#define BIT_MASK_H2CQ_HOST_IDX_8814B 0xfff
+#define BIT_H2CQ_HOST_IDX_8814B(x) \
+ (((x) & BIT_MASK_H2CQ_HOST_IDX_8814B) << BIT_SHIFT_H2CQ_HOST_IDX_8814B)
+#define BITS_H2CQ_HOST_IDX_8814B \
+ (BIT_MASK_H2CQ_HOST_IDX_8814B << BIT_SHIFT_H2CQ_HOST_IDX_8814B)
+#define BIT_CLEAR_H2CQ_HOST_IDX_8814B(x) ((x) & (~BITS_H2CQ_HOST_IDX_8814B))
+#define BIT_GET_H2CQ_HOST_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8814B) & BIT_MASK_H2CQ_HOST_IDX_8814B)
+#define BIT_SET_H2CQ_HOST_IDX_8814B(x, v) \
+ (BIT_CLEAR_H2CQ_HOST_IDX_8814B(x) | BIT_H2CQ_HOST_IDX_8814B(v))
+
+/* 2 REG_H2CQ_CSR_8814B[31:0] (H2CQ CONTROL AND STATUS) */
+#define BIT_H2CQ_FULL_8814B BIT(31)
+#define BIT_CLR_H2CQ_HOST_IDX_8814B BIT(16)
+#define BIT_CLR_H2CQ_HW_IDX_8814B BIT(8)
+#define BIT_STOP_H2CQ_8814B BIT(0)
+
+/* 2 REG_P0HI9Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI9Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI9Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI9Q_HW_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI9Q_HW_IDX_8814B) << BIT_SHIFT_P0HI9Q_HW_IDX_8814B)
+#define BITS_P0HI9Q_HW_IDX_8814B \
+ (BIT_MASK_P0HI9Q_HW_IDX_8814B << BIT_SHIFT_P0HI9Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI9Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI9Q_HW_IDX_8814B))
+#define BIT_GET_P0HI9Q_HW_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI9Q_HW_IDX_8814B) & BIT_MASK_P0HI9Q_HW_IDX_8814B)
+#define BIT_SET_P0HI9Q_HW_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI9Q_HW_IDX_8814B(x) | BIT_P0HI9Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI9Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI9Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI9Q_HOST_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI9Q_HOST_IDX_8814B) \
+ << BIT_SHIFT_P0HI9Q_HOST_IDX_8814B)
+#define BITS_P0HI9Q_HOST_IDX_8814B \
+ (BIT_MASK_P0HI9Q_HOST_IDX_8814B << BIT_SHIFT_P0HI9Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI9Q_HOST_IDX_8814B(x) ((x) & (~BITS_P0HI9Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI9Q_HOST_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI9Q_HOST_IDX_8814B) & \
+ BIT_MASK_P0HI9Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI9Q_HOST_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI9Q_HOST_IDX_8814B(x) | BIT_P0HI9Q_HOST_IDX_8814B(v))
+
+/* 2 REG_P0HI10Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI10Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI10Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI10Q_HW_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI10Q_HW_IDX_8814B) \
+ << BIT_SHIFT_P0HI10Q_HW_IDX_8814B)
+#define BITS_P0HI10Q_HW_IDX_8814B \
+ (BIT_MASK_P0HI10Q_HW_IDX_8814B << BIT_SHIFT_P0HI10Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI10Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI10Q_HW_IDX_8814B))
+#define BIT_GET_P0HI10Q_HW_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI10Q_HW_IDX_8814B) & \
+ BIT_MASK_P0HI10Q_HW_IDX_8814B)
+#define BIT_SET_P0HI10Q_HW_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI10Q_HW_IDX_8814B(x) | BIT_P0HI10Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI10Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI10Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI10Q_HOST_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI10Q_HOST_IDX_8814B) \
+ << BIT_SHIFT_P0HI10Q_HOST_IDX_8814B)
+#define BITS_P0HI10Q_HOST_IDX_8814B \
+ (BIT_MASK_P0HI10Q_HOST_IDX_8814B << BIT_SHIFT_P0HI10Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI10Q_HOST_IDX_8814B(x) \
+ ((x) & (~BITS_P0HI10Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI10Q_HOST_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI10Q_HOST_IDX_8814B) & \
+ BIT_MASK_P0HI10Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI10Q_HOST_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI10Q_HOST_IDX_8814B(x) | BIT_P0HI10Q_HOST_IDX_8814B(v))
+
+/* 2 REG_P0HI11Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI11Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI11Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI11Q_HW_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI11Q_HW_IDX_8814B) \
+ << BIT_SHIFT_P0HI11Q_HW_IDX_8814B)
+#define BITS_P0HI11Q_HW_IDX_8814B \
+ (BIT_MASK_P0HI11Q_HW_IDX_8814B << BIT_SHIFT_P0HI11Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI11Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI11Q_HW_IDX_8814B))
+#define BIT_GET_P0HI11Q_HW_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI11Q_HW_IDX_8814B) & \
+ BIT_MASK_P0HI11Q_HW_IDX_8814B)
+#define BIT_SET_P0HI11Q_HW_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI11Q_HW_IDX_8814B(x) | BIT_P0HI11Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI11Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI11Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI11Q_HOST_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI11Q_HOST_IDX_8814B) \
+ << BIT_SHIFT_P0HI11Q_HOST_IDX_8814B)
+#define BITS_P0HI11Q_HOST_IDX_8814B \
+ (BIT_MASK_P0HI11Q_HOST_IDX_8814B << BIT_SHIFT_P0HI11Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI11Q_HOST_IDX_8814B(x) \
+ ((x) & (~BITS_P0HI11Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI11Q_HOST_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI11Q_HOST_IDX_8814B) & \
+ BIT_MASK_P0HI11Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI11Q_HOST_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI11Q_HOST_IDX_8814B(x) | BIT_P0HI11Q_HOST_IDX_8814B(v))
+
+/* 2 REG_P0HI12Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI12Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI12Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI12Q_HW_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI12Q_HW_IDX_8814B) \
+ << BIT_SHIFT_P0HI12Q_HW_IDX_8814B)
+#define BITS_P0HI12Q_HW_IDX_8814B \
+ (BIT_MASK_P0HI12Q_HW_IDX_8814B << BIT_SHIFT_P0HI12Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI12Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI12Q_HW_IDX_8814B))
+#define BIT_GET_P0HI12Q_HW_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI12Q_HW_IDX_8814B) & \
+ BIT_MASK_P0HI12Q_HW_IDX_8814B)
+#define BIT_SET_P0HI12Q_HW_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI12Q_HW_IDX_8814B(x) | BIT_P0HI12Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI12Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI12Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI12Q_HOST_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI12Q_HOST_IDX_8814B) \
+ << BIT_SHIFT_P0HI12Q_HOST_IDX_8814B)
+#define BITS_P0HI12Q_HOST_IDX_8814B \
+ (BIT_MASK_P0HI12Q_HOST_IDX_8814B << BIT_SHIFT_P0HI12Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI12Q_HOST_IDX_8814B(x) \
+ ((x) & (~BITS_P0HI12Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI12Q_HOST_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI12Q_HOST_IDX_8814B) & \
+ BIT_MASK_P0HI12Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI12Q_HOST_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI12Q_HOST_IDX_8814B(x) | BIT_P0HI12Q_HOST_IDX_8814B(v))
+
+/* 2 REG_P0HI13Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI13Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI13Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI13Q_HW_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI13Q_HW_IDX_8814B) \
+ << BIT_SHIFT_P0HI13Q_HW_IDX_8814B)
+#define BITS_P0HI13Q_HW_IDX_8814B \
+ (BIT_MASK_P0HI13Q_HW_IDX_8814B << BIT_SHIFT_P0HI13Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI13Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI13Q_HW_IDX_8814B))
+#define BIT_GET_P0HI13Q_HW_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI13Q_HW_IDX_8814B) & \
+ BIT_MASK_P0HI13Q_HW_IDX_8814B)
+#define BIT_SET_P0HI13Q_HW_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI13Q_HW_IDX_8814B(x) | BIT_P0HI13Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI13Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI13Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI13Q_HOST_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI13Q_HOST_IDX_8814B) \
+ << BIT_SHIFT_P0HI13Q_HOST_IDX_8814B)
+#define BITS_P0HI13Q_HOST_IDX_8814B \
+ (BIT_MASK_P0HI13Q_HOST_IDX_8814B << BIT_SHIFT_P0HI13Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI13Q_HOST_IDX_8814B(x) \
+ ((x) & (~BITS_P0HI13Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI13Q_HOST_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI13Q_HOST_IDX_8814B) & \
+ BIT_MASK_P0HI13Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI13Q_HOST_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI13Q_HOST_IDX_8814B(x) | BIT_P0HI13Q_HOST_IDX_8814B(v))
+
+/* 2 REG_P0HI14Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI14Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI14Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI14Q_HW_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI14Q_HW_IDX_8814B) \
+ << BIT_SHIFT_P0HI14Q_HW_IDX_8814B)
+#define BITS_P0HI14Q_HW_IDX_8814B \
+ (BIT_MASK_P0HI14Q_HW_IDX_8814B << BIT_SHIFT_P0HI14Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI14Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI14Q_HW_IDX_8814B))
+#define BIT_GET_P0HI14Q_HW_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI14Q_HW_IDX_8814B) & \
+ BIT_MASK_P0HI14Q_HW_IDX_8814B)
+#define BIT_SET_P0HI14Q_HW_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI14Q_HW_IDX_8814B(x) | BIT_P0HI14Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI14Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI14Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI14Q_HOST_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI14Q_HOST_IDX_8814B) \
+ << BIT_SHIFT_P0HI14Q_HOST_IDX_8814B)
+#define BITS_P0HI14Q_HOST_IDX_8814B \
+ (BIT_MASK_P0HI14Q_HOST_IDX_8814B << BIT_SHIFT_P0HI14Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI14Q_HOST_IDX_8814B(x) \
+ ((x) & (~BITS_P0HI14Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI14Q_HOST_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI14Q_HOST_IDX_8814B) & \
+ BIT_MASK_P0HI14Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI14Q_HOST_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI14Q_HOST_IDX_8814B(x) | BIT_P0HI14Q_HOST_IDX_8814B(v))
+
+/* 2 REG_P0HI15Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI15Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI15Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI15Q_HW_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI15Q_HW_IDX_8814B) \
+ << BIT_SHIFT_P0HI15Q_HW_IDX_8814B)
+#define BITS_P0HI15Q_HW_IDX_8814B \
+ (BIT_MASK_P0HI15Q_HW_IDX_8814B << BIT_SHIFT_P0HI15Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI15Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI15Q_HW_IDX_8814B))
+#define BIT_GET_P0HI15Q_HW_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI15Q_HW_IDX_8814B) & \
+ BIT_MASK_P0HI15Q_HW_IDX_8814B)
+#define BIT_SET_P0HI15Q_HW_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI15Q_HW_IDX_8814B(x) | BIT_P0HI15Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI15Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI15Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI15Q_HOST_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI15Q_HOST_IDX_8814B) \
+ << BIT_SHIFT_P0HI15Q_HOST_IDX_8814B)
+#define BITS_P0HI15Q_HOST_IDX_8814B \
+ (BIT_MASK_P0HI15Q_HOST_IDX_8814B << BIT_SHIFT_P0HI15Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI15Q_HOST_IDX_8814B(x) \
+ ((x) & (~BITS_P0HI15Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI15Q_HOST_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI15Q_HOST_IDX_8814B) & \
+ BIT_MASK_P0HI15Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI15Q_HOST_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI15Q_HOST_IDX_8814B(x) | BIT_P0HI15Q_HOST_IDX_8814B(v))
+
+/* 2 REG_CHANGE_PCIE_SPEED_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_RXDMA_ERR_CNT_8814B 8
+#define BIT_MASK_RXDMA_ERR_CNT_8814B 0xff
+#define BIT_RXDMA_ERR_CNT_8814B(x) \
+ (((x) & BIT_MASK_RXDMA_ERR_CNT_8814B) << BIT_SHIFT_RXDMA_ERR_CNT_8814B)
+#define BITS_RXDMA_ERR_CNT_8814B \
+ (BIT_MASK_RXDMA_ERR_CNT_8814B << BIT_SHIFT_RXDMA_ERR_CNT_8814B)
+#define BIT_CLEAR_RXDMA_ERR_CNT_8814B(x) ((x) & (~BITS_RXDMA_ERR_CNT_8814B))
+#define BIT_GET_RXDMA_ERR_CNT_8814B(x) \
+ (((x) >> BIT_SHIFT_RXDMA_ERR_CNT_8814B) & BIT_MASK_RXDMA_ERR_CNT_8814B)
+#define BIT_SET_RXDMA_ERR_CNT_8814B(x, v) \
+ (BIT_CLEAR_RXDMA_ERR_CNT_8814B(x) | BIT_RXDMA_ERR_CNT_8814B(v))
+
+#define BIT_TXDMA_ERR_HANDLE_REQ_8814B BIT(7)
+#define BIT_TXDMA_ERROR_PS_8814B BIT(6)
+#define BIT_EN_TXDMA_STUCK_ERR_HANDLE_8814B BIT(5)
+#define BIT_EN_TXDMA_RTN_ERR_HANDLE_8814B BIT(4)
+#define BIT_RXDMA_ERR_HANDLE_REQ_8814B BIT(3)
+#define BIT_RXDMA_ERROR_PS_8814B BIT(2)
+#define BIT_EN_RXDMA_STUCK_ERR_HANDLE_8814B BIT(1)
+#define BIT_EN_RXDMA_RTN_ERR_HANDLE_8814B BIT(0)
+
+/* 2 REG_DEBUG_STATE1_8814B */
+
+#define BIT_SHIFT_DEBUG_STATE1_8814B 0
+#define BIT_MASK_DEBUG_STATE1_8814B 0xffffffffL
+#define BIT_DEBUG_STATE1_8814B(x) \
+ (((x) & BIT_MASK_DEBUG_STATE1_8814B) << BIT_SHIFT_DEBUG_STATE1_8814B)
+#define BITS_DEBUG_STATE1_8814B \
+ (BIT_MASK_DEBUG_STATE1_8814B << BIT_SHIFT_DEBUG_STATE1_8814B)
+#define BIT_CLEAR_DEBUG_STATE1_8814B(x) ((x) & (~BITS_DEBUG_STATE1_8814B))
+#define BIT_GET_DEBUG_STATE1_8814B(x) \
+ (((x) >> BIT_SHIFT_DEBUG_STATE1_8814B) & BIT_MASK_DEBUG_STATE1_8814B)
+#define BIT_SET_DEBUG_STATE1_8814B(x, v) \
+ (BIT_CLEAR_DEBUG_STATE1_8814B(x) | BIT_DEBUG_STATE1_8814B(v))
+
+/* 2 REG_DEBUG_STATE2_8814B */
+
+#define BIT_SHIFT_DEBUG_STATE2_8814B 0
+#define BIT_MASK_DEBUG_STATE2_8814B 0xffffffffL
+#define BIT_DEBUG_STATE2_8814B(x) \
+ (((x) & BIT_MASK_DEBUG_STATE2_8814B) << BIT_SHIFT_DEBUG_STATE2_8814B)
+#define BITS_DEBUG_STATE2_8814B \
+ (BIT_MASK_DEBUG_STATE2_8814B << BIT_SHIFT_DEBUG_STATE2_8814B)
+#define BIT_CLEAR_DEBUG_STATE2_8814B(x) ((x) & (~BITS_DEBUG_STATE2_8814B))
+#define BIT_GET_DEBUG_STATE2_8814B(x) \
+ (((x) >> BIT_SHIFT_DEBUG_STATE2_8814B) & BIT_MASK_DEBUG_STATE2_8814B)
+#define BIT_SET_DEBUG_STATE2_8814B(x, v) \
+ (BIT_CLEAR_DEBUG_STATE2_8814B(x) | BIT_DEBUG_STATE2_8814B(v))
+
+/* 2 REG_DEBUG_STATE3_8814B */
+
+#define BIT_SHIFT_DEBUG_STATE3_8814B 0
+#define BIT_MASK_DEBUG_STATE3_8814B 0xffffffffL
+#define BIT_DEBUG_STATE3_8814B(x) \
+ (((x) & BIT_MASK_DEBUG_STATE3_8814B) << BIT_SHIFT_DEBUG_STATE3_8814B)
+#define BITS_DEBUG_STATE3_8814B \
+ (BIT_MASK_DEBUG_STATE3_8814B << BIT_SHIFT_DEBUG_STATE3_8814B)
+#define BIT_CLEAR_DEBUG_STATE3_8814B(x) ((x) & (~BITS_DEBUG_STATE3_8814B))
+#define BIT_GET_DEBUG_STATE3_8814B(x) \
+ (((x) >> BIT_SHIFT_DEBUG_STATE3_8814B) & BIT_MASK_DEBUG_STATE3_8814B)
+#define BIT_SET_DEBUG_STATE3_8814B(x, v) \
+ (BIT_CLEAR_DEBUG_STATE3_8814B(x) | BIT_DEBUG_STATE3_8814B(v))
+
+/* 2 REG_ACH5_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_ACH5_TXBD_DESA_L_8814B 0
+#define BIT_MASK_ACH5_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_ACH5_TXBD_DESA_L_8814B(x) \
+ (((x) & BIT_MASK_ACH5_TXBD_DESA_L_8814B) \
+ << BIT_SHIFT_ACH5_TXBD_DESA_L_8814B)
+#define BITS_ACH5_TXBD_DESA_L_8814B \
+ (BIT_MASK_ACH5_TXBD_DESA_L_8814B << BIT_SHIFT_ACH5_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_ACH5_TXBD_DESA_L_8814B(x) \
+ ((x) & (~BITS_ACH5_TXBD_DESA_L_8814B))
+#define BIT_GET_ACH5_TXBD_DESA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH5_TXBD_DESA_L_8814B) & \
+ BIT_MASK_ACH5_TXBD_DESA_L_8814B)
+#define BIT_SET_ACH5_TXBD_DESA_L_8814B(x, v) \
+ (BIT_CLEAR_ACH5_TXBD_DESA_L_8814B(x) | BIT_ACH5_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_ACH5_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_ACH5_TXBD_DESA_H_8814B 0
+#define BIT_MASK_ACH5_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_ACH5_TXBD_DESA_H_8814B(x) \
+ (((x) & BIT_MASK_ACH5_TXBD_DESA_H_8814B) \
+ << BIT_SHIFT_ACH5_TXBD_DESA_H_8814B)
+#define BITS_ACH5_TXBD_DESA_H_8814B \
+ (BIT_MASK_ACH5_TXBD_DESA_H_8814B << BIT_SHIFT_ACH5_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_ACH5_TXBD_DESA_H_8814B(x) \
+ ((x) & (~BITS_ACH5_TXBD_DESA_H_8814B))
+#define BIT_GET_ACH5_TXBD_DESA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH5_TXBD_DESA_H_8814B) & \
+ BIT_MASK_ACH5_TXBD_DESA_H_8814B)
+#define BIT_SET_ACH5_TXBD_DESA_H_8814B(x, v) \
+ (BIT_CLEAR_ACH5_TXBD_DESA_H_8814B(x) | BIT_ACH5_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_ACH6_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_ACH6_TXBD_DESA_L_8814B 0
+#define BIT_MASK_ACH6_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_ACH6_TXBD_DESA_L_8814B(x) \
+ (((x) & BIT_MASK_ACH6_TXBD_DESA_L_8814B) \
+ << BIT_SHIFT_ACH6_TXBD_DESA_L_8814B)
+#define BITS_ACH6_TXBD_DESA_L_8814B \
+ (BIT_MASK_ACH6_TXBD_DESA_L_8814B << BIT_SHIFT_ACH6_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_ACH6_TXBD_DESA_L_8814B(x) \
+ ((x) & (~BITS_ACH6_TXBD_DESA_L_8814B))
+#define BIT_GET_ACH6_TXBD_DESA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH6_TXBD_DESA_L_8814B) & \
+ BIT_MASK_ACH6_TXBD_DESA_L_8814B)
+#define BIT_SET_ACH6_TXBD_DESA_L_8814B(x, v) \
+ (BIT_CLEAR_ACH6_TXBD_DESA_L_8814B(x) | BIT_ACH6_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_ACH6_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_ACH6_TXBD_DESA_H_8814B 0
+#define BIT_MASK_ACH6_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_ACH6_TXBD_DESA_H_8814B(x) \
+ (((x) & BIT_MASK_ACH6_TXBD_DESA_H_8814B) \
+ << BIT_SHIFT_ACH6_TXBD_DESA_H_8814B)
+#define BITS_ACH6_TXBD_DESA_H_8814B \
+ (BIT_MASK_ACH6_TXBD_DESA_H_8814B << BIT_SHIFT_ACH6_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_ACH6_TXBD_DESA_H_8814B(x) \
+ ((x) & (~BITS_ACH6_TXBD_DESA_H_8814B))
+#define BIT_GET_ACH6_TXBD_DESA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH6_TXBD_DESA_H_8814B) & \
+ BIT_MASK_ACH6_TXBD_DESA_H_8814B)
+#define BIT_SET_ACH6_TXBD_DESA_H_8814B(x, v) \
+ (BIT_CLEAR_ACH6_TXBD_DESA_H_8814B(x) | BIT_ACH6_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_ACH7_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_ACH7_TXBD_DESA_L_8814B 0
+#define BIT_MASK_ACH7_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_ACH7_TXBD_DESA_L_8814B(x) \
+ (((x) & BIT_MASK_ACH7_TXBD_DESA_L_8814B) \
+ << BIT_SHIFT_ACH7_TXBD_DESA_L_8814B)
+#define BITS_ACH7_TXBD_DESA_L_8814B \
+ (BIT_MASK_ACH7_TXBD_DESA_L_8814B << BIT_SHIFT_ACH7_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_ACH7_TXBD_DESA_L_8814B(x) \
+ ((x) & (~BITS_ACH7_TXBD_DESA_L_8814B))
+#define BIT_GET_ACH7_TXBD_DESA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH7_TXBD_DESA_L_8814B) & \
+ BIT_MASK_ACH7_TXBD_DESA_L_8814B)
+#define BIT_SET_ACH7_TXBD_DESA_L_8814B(x, v) \
+ (BIT_CLEAR_ACH7_TXBD_DESA_L_8814B(x) | BIT_ACH7_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_ACH7_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_ACH7_TXBD_DESA_H_8814B 0
+#define BIT_MASK_ACH7_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_ACH7_TXBD_DESA_H_8814B(x) \
+ (((x) & BIT_MASK_ACH7_TXBD_DESA_H_8814B) \
+ << BIT_SHIFT_ACH7_TXBD_DESA_H_8814B)
+#define BITS_ACH7_TXBD_DESA_H_8814B \
+ (BIT_MASK_ACH7_TXBD_DESA_H_8814B << BIT_SHIFT_ACH7_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_ACH7_TXBD_DESA_H_8814B(x) \
+ ((x) & (~BITS_ACH7_TXBD_DESA_H_8814B))
+#define BIT_GET_ACH7_TXBD_DESA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH7_TXBD_DESA_H_8814B) & \
+ BIT_MASK_ACH7_TXBD_DESA_H_8814B)
+#define BIT_SET_ACH7_TXBD_DESA_H_8814B(x, v) \
+ (BIT_CLEAR_ACH7_TXBD_DESA_H_8814B(x) | BIT_ACH7_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_ACH8_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_ACH8_TXBD_DESA_L_8814B 0
+#define BIT_MASK_ACH8_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_ACH8_TXBD_DESA_L_8814B(x) \
+ (((x) & BIT_MASK_ACH8_TXBD_DESA_L_8814B) \
+ << BIT_SHIFT_ACH8_TXBD_DESA_L_8814B)
+#define BITS_ACH8_TXBD_DESA_L_8814B \
+ (BIT_MASK_ACH8_TXBD_DESA_L_8814B << BIT_SHIFT_ACH8_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_ACH8_TXBD_DESA_L_8814B(x) \
+ ((x) & (~BITS_ACH8_TXBD_DESA_L_8814B))
+#define BIT_GET_ACH8_TXBD_DESA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH8_TXBD_DESA_L_8814B) & \
+ BIT_MASK_ACH8_TXBD_DESA_L_8814B)
+#define BIT_SET_ACH8_TXBD_DESA_L_8814B(x, v) \
+ (BIT_CLEAR_ACH8_TXBD_DESA_L_8814B(x) | BIT_ACH8_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_ACH8_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_ACH8_TXBD_DESA_H_8814B 0
+#define BIT_MASK_ACH8_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_ACH8_TXBD_DESA_H_8814B(x) \
+ (((x) & BIT_MASK_ACH8_TXBD_DESA_H_8814B) \
+ << BIT_SHIFT_ACH8_TXBD_DESA_H_8814B)
+#define BITS_ACH8_TXBD_DESA_H_8814B \
+ (BIT_MASK_ACH8_TXBD_DESA_H_8814B << BIT_SHIFT_ACH8_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_ACH8_TXBD_DESA_H_8814B(x) \
+ ((x) & (~BITS_ACH8_TXBD_DESA_H_8814B))
+#define BIT_GET_ACH8_TXBD_DESA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH8_TXBD_DESA_H_8814B) & \
+ BIT_MASK_ACH8_TXBD_DESA_H_8814B)
+#define BIT_SET_ACH8_TXBD_DESA_H_8814B(x, v) \
+ (BIT_CLEAR_ACH8_TXBD_DESA_H_8814B(x) | BIT_ACH8_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_ACH9_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_ACH9_TXBD_DESA_L_8814B 0
+#define BIT_MASK_ACH9_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_ACH9_TXBD_DESA_L_8814B(x) \
+ (((x) & BIT_MASK_ACH9_TXBD_DESA_L_8814B) \
+ << BIT_SHIFT_ACH9_TXBD_DESA_L_8814B)
+#define BITS_ACH9_TXBD_DESA_L_8814B \
+ (BIT_MASK_ACH9_TXBD_DESA_L_8814B << BIT_SHIFT_ACH9_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_ACH9_TXBD_DESA_L_8814B(x) \
+ ((x) & (~BITS_ACH9_TXBD_DESA_L_8814B))
+#define BIT_GET_ACH9_TXBD_DESA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH9_TXBD_DESA_L_8814B) & \
+ BIT_MASK_ACH9_TXBD_DESA_L_8814B)
+#define BIT_SET_ACH9_TXBD_DESA_L_8814B(x, v) \
+ (BIT_CLEAR_ACH9_TXBD_DESA_L_8814B(x) | BIT_ACH9_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_ACH9_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_ACH9_TXBD_DESA_H_8814B 0
+#define BIT_MASK_ACH9_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_ACH9_TXBD_DESA_H_8814B(x) \
+ (((x) & BIT_MASK_ACH9_TXBD_DESA_H_8814B) \
+ << BIT_SHIFT_ACH9_TXBD_DESA_H_8814B)
+#define BITS_ACH9_TXBD_DESA_H_8814B \
+ (BIT_MASK_ACH9_TXBD_DESA_H_8814B << BIT_SHIFT_ACH9_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_ACH9_TXBD_DESA_H_8814B(x) \
+ ((x) & (~BITS_ACH9_TXBD_DESA_H_8814B))
+#define BIT_GET_ACH9_TXBD_DESA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH9_TXBD_DESA_H_8814B) & \
+ BIT_MASK_ACH9_TXBD_DESA_H_8814B)
+#define BIT_SET_ACH9_TXBD_DESA_H_8814B(x, v) \
+ (BIT_CLEAR_ACH9_TXBD_DESA_H_8814B(x) | BIT_ACH9_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_ACH10_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_ACH10_TXBD_DESA_L_8814B 0
+#define BIT_MASK_ACH10_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_ACH10_TXBD_DESA_L_8814B(x) \
+ (((x) & BIT_MASK_ACH10_TXBD_DESA_L_8814B) \
+ << BIT_SHIFT_ACH10_TXBD_DESA_L_8814B)
+#define BITS_ACH10_TXBD_DESA_L_8814B \
+ (BIT_MASK_ACH10_TXBD_DESA_L_8814B << BIT_SHIFT_ACH10_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_ACH10_TXBD_DESA_L_8814B(x) \
+ ((x) & (~BITS_ACH10_TXBD_DESA_L_8814B))
+#define BIT_GET_ACH10_TXBD_DESA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH10_TXBD_DESA_L_8814B) & \
+ BIT_MASK_ACH10_TXBD_DESA_L_8814B)
+#define BIT_SET_ACH10_TXBD_DESA_L_8814B(x, v) \
+ (BIT_CLEAR_ACH10_TXBD_DESA_L_8814B(x) | BIT_ACH10_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_ACH10_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_ACH10_TXBD_DESA_H_8814B 0
+#define BIT_MASK_ACH10_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_ACH10_TXBD_DESA_H_8814B(x) \
+ (((x) & BIT_MASK_ACH10_TXBD_DESA_H_8814B) \
+ << BIT_SHIFT_ACH10_TXBD_DESA_H_8814B)
+#define BITS_ACH10_TXBD_DESA_H_8814B \
+ (BIT_MASK_ACH10_TXBD_DESA_H_8814B << BIT_SHIFT_ACH10_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_ACH10_TXBD_DESA_H_8814B(x) \
+ ((x) & (~BITS_ACH10_TXBD_DESA_H_8814B))
+#define BIT_GET_ACH10_TXBD_DESA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH10_TXBD_DESA_H_8814B) & \
+ BIT_MASK_ACH10_TXBD_DESA_H_8814B)
+#define BIT_SET_ACH10_TXBD_DESA_H_8814B(x, v) \
+ (BIT_CLEAR_ACH10_TXBD_DESA_H_8814B(x) | BIT_ACH10_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_ACH11_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_ACH11_TXBD_DESA_L_8814B 0
+#define BIT_MASK_ACH11_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_ACH11_TXBD_DESA_L_8814B(x) \
+ (((x) & BIT_MASK_ACH11_TXBD_DESA_L_8814B) \
+ << BIT_SHIFT_ACH11_TXBD_DESA_L_8814B)
+#define BITS_ACH11_TXBD_DESA_L_8814B \
+ (BIT_MASK_ACH11_TXBD_DESA_L_8814B << BIT_SHIFT_ACH11_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_ACH11_TXBD_DESA_L_8814B(x) \
+ ((x) & (~BITS_ACH11_TXBD_DESA_L_8814B))
+#define BIT_GET_ACH11_TXBD_DESA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH11_TXBD_DESA_L_8814B) & \
+ BIT_MASK_ACH11_TXBD_DESA_L_8814B)
+#define BIT_SET_ACH11_TXBD_DESA_L_8814B(x, v) \
+ (BIT_CLEAR_ACH11_TXBD_DESA_L_8814B(x) | BIT_ACH11_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_ACH11_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_ACH11_TXBD_DESA_H_8814B 0
+#define BIT_MASK_ACH11_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_ACH11_TXBD_DESA_H_8814B(x) \
+ (((x) & BIT_MASK_ACH11_TXBD_DESA_H_8814B) \
+ << BIT_SHIFT_ACH11_TXBD_DESA_H_8814B)
+#define BITS_ACH11_TXBD_DESA_H_8814B \
+ (BIT_MASK_ACH11_TXBD_DESA_H_8814B << BIT_SHIFT_ACH11_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_ACH11_TXBD_DESA_H_8814B(x) \
+ ((x) & (~BITS_ACH11_TXBD_DESA_H_8814B))
+#define BIT_GET_ACH11_TXBD_DESA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH11_TXBD_DESA_H_8814B) & \
+ BIT_MASK_ACH11_TXBD_DESA_H_8814B)
+#define BIT_SET_ACH11_TXBD_DESA_H_8814B(x, v) \
+ (BIT_CLEAR_ACH11_TXBD_DESA_H_8814B(x) | BIT_ACH11_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_ACH12_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_ACH12_TXBD_DESA_L_8814B 0
+#define BIT_MASK_ACH12_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_ACH12_TXBD_DESA_L_8814B(x) \
+ (((x) & BIT_MASK_ACH12_TXBD_DESA_L_8814B) \
+ << BIT_SHIFT_ACH12_TXBD_DESA_L_8814B)
+#define BITS_ACH12_TXBD_DESA_L_8814B \
+ (BIT_MASK_ACH12_TXBD_DESA_L_8814B << BIT_SHIFT_ACH12_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_ACH12_TXBD_DESA_L_8814B(x) \
+ ((x) & (~BITS_ACH12_TXBD_DESA_L_8814B))
+#define BIT_GET_ACH12_TXBD_DESA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH12_TXBD_DESA_L_8814B) & \
+ BIT_MASK_ACH12_TXBD_DESA_L_8814B)
+#define BIT_SET_ACH12_TXBD_DESA_L_8814B(x, v) \
+ (BIT_CLEAR_ACH12_TXBD_DESA_L_8814B(x) | BIT_ACH12_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_ACH12_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_ACH12_TXBD_DESA_H_8814B 0
+#define BIT_MASK_ACH12_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_ACH12_TXBD_DESA_H_8814B(x) \
+ (((x) & BIT_MASK_ACH12_TXBD_DESA_H_8814B) \
+ << BIT_SHIFT_ACH12_TXBD_DESA_H_8814B)
+#define BITS_ACH12_TXBD_DESA_H_8814B \
+ (BIT_MASK_ACH12_TXBD_DESA_H_8814B << BIT_SHIFT_ACH12_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_ACH12_TXBD_DESA_H_8814B(x) \
+ ((x) & (~BITS_ACH12_TXBD_DESA_H_8814B))
+#define BIT_GET_ACH12_TXBD_DESA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH12_TXBD_DESA_H_8814B) & \
+ BIT_MASK_ACH12_TXBD_DESA_H_8814B)
+#define BIT_SET_ACH12_TXBD_DESA_H_8814B(x, v) \
+ (BIT_CLEAR_ACH12_TXBD_DESA_H_8814B(x) | BIT_ACH12_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_ACH13_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_ACH13_TXBD_DESA_L_8814B 0
+#define BIT_MASK_ACH13_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_ACH13_TXBD_DESA_L_8814B(x) \
+ (((x) & BIT_MASK_ACH13_TXBD_DESA_L_8814B) \
+ << BIT_SHIFT_ACH13_TXBD_DESA_L_8814B)
+#define BITS_ACH13_TXBD_DESA_L_8814B \
+ (BIT_MASK_ACH13_TXBD_DESA_L_8814B << BIT_SHIFT_ACH13_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_ACH13_TXBD_DESA_L_8814B(x) \
+ ((x) & (~BITS_ACH13_TXBD_DESA_L_8814B))
+#define BIT_GET_ACH13_TXBD_DESA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH13_TXBD_DESA_L_8814B) & \
+ BIT_MASK_ACH13_TXBD_DESA_L_8814B)
+#define BIT_SET_ACH13_TXBD_DESA_L_8814B(x, v) \
+ (BIT_CLEAR_ACH13_TXBD_DESA_L_8814B(x) | BIT_ACH13_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_ACH13_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_ACH13_TXBD_DESA_H_8814B 0
+#define BIT_MASK_ACH13_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_ACH13_TXBD_DESA_H_8814B(x) \
+ (((x) & BIT_MASK_ACH13_TXBD_DESA_H_8814B) \
+ << BIT_SHIFT_ACH13_TXBD_DESA_H_8814B)
+#define BITS_ACH13_TXBD_DESA_H_8814B \
+ (BIT_MASK_ACH13_TXBD_DESA_H_8814B << BIT_SHIFT_ACH13_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_ACH13_TXBD_DESA_H_8814B(x) \
+ ((x) & (~BITS_ACH13_TXBD_DESA_H_8814B))
+#define BIT_GET_ACH13_TXBD_DESA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH13_TXBD_DESA_H_8814B) & \
+ BIT_MASK_ACH13_TXBD_DESA_H_8814B)
+#define BIT_SET_ACH13_TXBD_DESA_H_8814B(x, v) \
+ (BIT_CLEAR_ACH13_TXBD_DESA_H_8814B(x) | BIT_ACH13_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI0Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI0Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI0Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI0Q_TXBD_DESA_L_8814B(x) \
+ (((x) & BIT_MASK_HI0Q_TXBD_DESA_L_8814B) \
+ << BIT_SHIFT_HI0Q_TXBD_DESA_L_8814B)
+#define BITS_HI0Q_TXBD_DESA_L_8814B \
+ (BIT_MASK_HI0Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI0Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI0Q_TXBD_DESA_L_8814B(x) \
+ ((x) & (~BITS_HI0Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI0Q_TXBD_DESA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_L_8814B) & \
+ BIT_MASK_HI0Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI0Q_TXBD_DESA_L_8814B(x, v) \
+ (BIT_CLEAR_HI0Q_TXBD_DESA_L_8814B(x) | BIT_HI0Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI0Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI0Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI0Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI0Q_TXBD_DESA_H_8814B(x) \
+ (((x) & BIT_MASK_HI0Q_TXBD_DESA_H_8814B) \
+ << BIT_SHIFT_HI0Q_TXBD_DESA_H_8814B)
+#define BITS_HI0Q_TXBD_DESA_H_8814B \
+ (BIT_MASK_HI0Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI0Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI0Q_TXBD_DESA_H_8814B(x) \
+ ((x) & (~BITS_HI0Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI0Q_TXBD_DESA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_H_8814B) & \
+ BIT_MASK_HI0Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI0Q_TXBD_DESA_H_8814B(x, v) \
+ (BIT_CLEAR_HI0Q_TXBD_DESA_H_8814B(x) | BIT_HI0Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI1Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI1Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI1Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI1Q_TXBD_DESA_L_8814B(x) \
+ (((x) & BIT_MASK_HI1Q_TXBD_DESA_L_8814B) \
+ << BIT_SHIFT_HI1Q_TXBD_DESA_L_8814B)
+#define BITS_HI1Q_TXBD_DESA_L_8814B \
+ (BIT_MASK_HI1Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI1Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI1Q_TXBD_DESA_L_8814B(x) \
+ ((x) & (~BITS_HI1Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI1Q_TXBD_DESA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_L_8814B) & \
+ BIT_MASK_HI1Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI1Q_TXBD_DESA_L_8814B(x, v) \
+ (BIT_CLEAR_HI1Q_TXBD_DESA_L_8814B(x) | BIT_HI1Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI1Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI1Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI1Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI1Q_TXBD_DESA_H_8814B(x) \
+ (((x) & BIT_MASK_HI1Q_TXBD_DESA_H_8814B) \
+ << BIT_SHIFT_HI1Q_TXBD_DESA_H_8814B)
+#define BITS_HI1Q_TXBD_DESA_H_8814B \
+ (BIT_MASK_HI1Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI1Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI1Q_TXBD_DESA_H_8814B(x) \
+ ((x) & (~BITS_HI1Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI1Q_TXBD_DESA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_H_8814B) & \
+ BIT_MASK_HI1Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI1Q_TXBD_DESA_H_8814B(x, v) \
+ (BIT_CLEAR_HI1Q_TXBD_DESA_H_8814B(x) | BIT_HI1Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI2Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI2Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI2Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI2Q_TXBD_DESA_L_8814B(x) \
+ (((x) & BIT_MASK_HI2Q_TXBD_DESA_L_8814B) \
+ << BIT_SHIFT_HI2Q_TXBD_DESA_L_8814B)
+#define BITS_HI2Q_TXBD_DESA_L_8814B \
+ (BIT_MASK_HI2Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI2Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI2Q_TXBD_DESA_L_8814B(x) \
+ ((x) & (~BITS_HI2Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI2Q_TXBD_DESA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_L_8814B) & \
+ BIT_MASK_HI2Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI2Q_TXBD_DESA_L_8814B(x, v) \
+ (BIT_CLEAR_HI2Q_TXBD_DESA_L_8814B(x) | BIT_HI2Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI2Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI2Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI2Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI2Q_TXBD_DESA_H_8814B(x) \
+ (((x) & BIT_MASK_HI2Q_TXBD_DESA_H_8814B) \
+ << BIT_SHIFT_HI2Q_TXBD_DESA_H_8814B)
+#define BITS_HI2Q_TXBD_DESA_H_8814B \
+ (BIT_MASK_HI2Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI2Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI2Q_TXBD_DESA_H_8814B(x) \
+ ((x) & (~BITS_HI2Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI2Q_TXBD_DESA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_H_8814B) & \
+ BIT_MASK_HI2Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI2Q_TXBD_DESA_H_8814B(x, v) \
+ (BIT_CLEAR_HI2Q_TXBD_DESA_H_8814B(x) | BIT_HI2Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI3Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI3Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI3Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI3Q_TXBD_DESA_L_8814B(x) \
+ (((x) & BIT_MASK_HI3Q_TXBD_DESA_L_8814B) \
+ << BIT_SHIFT_HI3Q_TXBD_DESA_L_8814B)
+#define BITS_HI3Q_TXBD_DESA_L_8814B \
+ (BIT_MASK_HI3Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI3Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI3Q_TXBD_DESA_L_8814B(x) \
+ ((x) & (~BITS_HI3Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI3Q_TXBD_DESA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_L_8814B) & \
+ BIT_MASK_HI3Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI3Q_TXBD_DESA_L_8814B(x, v) \
+ (BIT_CLEAR_HI3Q_TXBD_DESA_L_8814B(x) | BIT_HI3Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI3Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI3Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI3Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI3Q_TXBD_DESA_H_8814B(x) \
+ (((x) & BIT_MASK_HI3Q_TXBD_DESA_H_8814B) \
+ << BIT_SHIFT_HI3Q_TXBD_DESA_H_8814B)
+#define BITS_HI3Q_TXBD_DESA_H_8814B \
+ (BIT_MASK_HI3Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI3Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI3Q_TXBD_DESA_H_8814B(x) \
+ ((x) & (~BITS_HI3Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI3Q_TXBD_DESA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_H_8814B) & \
+ BIT_MASK_HI3Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI3Q_TXBD_DESA_H_8814B(x, v) \
+ (BIT_CLEAR_HI3Q_TXBD_DESA_H_8814B(x) | BIT_HI3Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI4Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI4Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI4Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI4Q_TXBD_DESA_L_8814B(x) \
+ (((x) & BIT_MASK_HI4Q_TXBD_DESA_L_8814B) \
+ << BIT_SHIFT_HI4Q_TXBD_DESA_L_8814B)
+#define BITS_HI4Q_TXBD_DESA_L_8814B \
+ (BIT_MASK_HI4Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI4Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI4Q_TXBD_DESA_L_8814B(x) \
+ ((x) & (~BITS_HI4Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI4Q_TXBD_DESA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_L_8814B) & \
+ BIT_MASK_HI4Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI4Q_TXBD_DESA_L_8814B(x, v) \
+ (BIT_CLEAR_HI4Q_TXBD_DESA_L_8814B(x) | BIT_HI4Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI4Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI4Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI4Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI4Q_TXBD_DESA_H_8814B(x) \
+ (((x) & BIT_MASK_HI4Q_TXBD_DESA_H_8814B) \
+ << BIT_SHIFT_HI4Q_TXBD_DESA_H_8814B)
+#define BITS_HI4Q_TXBD_DESA_H_8814B \
+ (BIT_MASK_HI4Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI4Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI4Q_TXBD_DESA_H_8814B(x) \
+ ((x) & (~BITS_HI4Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI4Q_TXBD_DESA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_H_8814B) & \
+ BIT_MASK_HI4Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI4Q_TXBD_DESA_H_8814B(x, v) \
+ (BIT_CLEAR_HI4Q_TXBD_DESA_H_8814B(x) | BIT_HI4Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI5Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI5Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI5Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI5Q_TXBD_DESA_L_8814B(x) \
+ (((x) & BIT_MASK_HI5Q_TXBD_DESA_L_8814B) \
+ << BIT_SHIFT_HI5Q_TXBD_DESA_L_8814B)
+#define BITS_HI5Q_TXBD_DESA_L_8814B \
+ (BIT_MASK_HI5Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI5Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI5Q_TXBD_DESA_L_8814B(x) \
+ ((x) & (~BITS_HI5Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI5Q_TXBD_DESA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_L_8814B) & \
+ BIT_MASK_HI5Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI5Q_TXBD_DESA_L_8814B(x, v) \
+ (BIT_CLEAR_HI5Q_TXBD_DESA_L_8814B(x) | BIT_HI5Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI5Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI5Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI5Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI5Q_TXBD_DESA_H_8814B(x) \
+ (((x) & BIT_MASK_HI5Q_TXBD_DESA_H_8814B) \
+ << BIT_SHIFT_HI5Q_TXBD_DESA_H_8814B)
+#define BITS_HI5Q_TXBD_DESA_H_8814B \
+ (BIT_MASK_HI5Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI5Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI5Q_TXBD_DESA_H_8814B(x) \
+ ((x) & (~BITS_HI5Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI5Q_TXBD_DESA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_H_8814B) & \
+ BIT_MASK_HI5Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI5Q_TXBD_DESA_H_8814B(x, v) \
+ (BIT_CLEAR_HI5Q_TXBD_DESA_H_8814B(x) | BIT_HI5Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI6Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI6Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI6Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI6Q_TXBD_DESA_L_8814B(x) \
+ (((x) & BIT_MASK_HI6Q_TXBD_DESA_L_8814B) \
+ << BIT_SHIFT_HI6Q_TXBD_DESA_L_8814B)
+#define BITS_HI6Q_TXBD_DESA_L_8814B \
+ (BIT_MASK_HI6Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI6Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI6Q_TXBD_DESA_L_8814B(x) \
+ ((x) & (~BITS_HI6Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI6Q_TXBD_DESA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_L_8814B) & \
+ BIT_MASK_HI6Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI6Q_TXBD_DESA_L_8814B(x, v) \
+ (BIT_CLEAR_HI6Q_TXBD_DESA_L_8814B(x) | BIT_HI6Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI6Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI6Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI6Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI6Q_TXBD_DESA_H_8814B(x) \
+ (((x) & BIT_MASK_HI6Q_TXBD_DESA_H_8814B) \
+ << BIT_SHIFT_HI6Q_TXBD_DESA_H_8814B)
+#define BITS_HI6Q_TXBD_DESA_H_8814B \
+ (BIT_MASK_HI6Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI6Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI6Q_TXBD_DESA_H_8814B(x) \
+ ((x) & (~BITS_HI6Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI6Q_TXBD_DESA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_H_8814B) & \
+ BIT_MASK_HI6Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI6Q_TXBD_DESA_H_8814B(x, v) \
+ (BIT_CLEAR_HI6Q_TXBD_DESA_H_8814B(x) | BIT_HI6Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI7Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI7Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI7Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI7Q_TXBD_DESA_L_8814B(x) \
+ (((x) & BIT_MASK_HI7Q_TXBD_DESA_L_8814B) \
+ << BIT_SHIFT_HI7Q_TXBD_DESA_L_8814B)
+#define BITS_HI7Q_TXBD_DESA_L_8814B \
+ (BIT_MASK_HI7Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI7Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI7Q_TXBD_DESA_L_8814B(x) \
+ ((x) & (~BITS_HI7Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI7Q_TXBD_DESA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_L_8814B) & \
+ BIT_MASK_HI7Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI7Q_TXBD_DESA_L_8814B(x, v) \
+ (BIT_CLEAR_HI7Q_TXBD_DESA_L_8814B(x) | BIT_HI7Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI7Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI7Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI7Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI7Q_TXBD_DESA_H_8814B(x) \
+ (((x) & BIT_MASK_HI7Q_TXBD_DESA_H_8814B) \
+ << BIT_SHIFT_HI7Q_TXBD_DESA_H_8814B)
+#define BITS_HI7Q_TXBD_DESA_H_8814B \
+ (BIT_MASK_HI7Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI7Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI7Q_TXBD_DESA_H_8814B(x) \
+ ((x) & (~BITS_HI7Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI7Q_TXBD_DESA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_H_8814B) & \
+ BIT_MASK_HI7Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI7Q_TXBD_DESA_H_8814B(x, v) \
+ (BIT_CLEAR_HI7Q_TXBD_DESA_H_8814B(x) | BIT_HI7Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_ACH8_ACH9_TXBD_NUM_8814B */
+#define BIT_PCIE_ACH9_FLAG_8814B BIT(30)
+
+#define BIT_SHIFT_ACH9_DESC_MODE_8814B 28
+#define BIT_MASK_ACH9_DESC_MODE_8814B 0x3
+#define BIT_ACH9_DESC_MODE_8814B(x) \
+ (((x) & BIT_MASK_ACH9_DESC_MODE_8814B) \
+ << BIT_SHIFT_ACH9_DESC_MODE_8814B)
+#define BITS_ACH9_DESC_MODE_8814B \
+ (BIT_MASK_ACH9_DESC_MODE_8814B << BIT_SHIFT_ACH9_DESC_MODE_8814B)
+#define BIT_CLEAR_ACH9_DESC_MODE_8814B(x) ((x) & (~BITS_ACH9_DESC_MODE_8814B))
+#define BIT_GET_ACH9_DESC_MODE_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH9_DESC_MODE_8814B) & \
+ BIT_MASK_ACH9_DESC_MODE_8814B)
+#define BIT_SET_ACH9_DESC_MODE_8814B(x, v) \
+ (BIT_CLEAR_ACH9_DESC_MODE_8814B(x) | BIT_ACH9_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_ACH9_DESC_NUM_8814B 16
+#define BIT_MASK_ACH9_DESC_NUM_8814B 0xfff
+#define BIT_ACH9_DESC_NUM_8814B(x) \
+ (((x) & BIT_MASK_ACH9_DESC_NUM_8814B) << BIT_SHIFT_ACH9_DESC_NUM_8814B)
+#define BITS_ACH9_DESC_NUM_8814B \
+ (BIT_MASK_ACH9_DESC_NUM_8814B << BIT_SHIFT_ACH9_DESC_NUM_8814B)
+#define BIT_CLEAR_ACH9_DESC_NUM_8814B(x) ((x) & (~BITS_ACH9_DESC_NUM_8814B))
+#define BIT_GET_ACH9_DESC_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH9_DESC_NUM_8814B) & BIT_MASK_ACH9_DESC_NUM_8814B)
+#define BIT_SET_ACH9_DESC_NUM_8814B(x, v) \
+ (BIT_CLEAR_ACH9_DESC_NUM_8814B(x) | BIT_ACH9_DESC_NUM_8814B(v))
+
+#define BIT_PCIE_ACH8_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_ACH8_DESC_MODE_8814B 12
+#define BIT_MASK_ACH8_DESC_MODE_8814B 0x3
+#define BIT_ACH8_DESC_MODE_8814B(x) \
+ (((x) & BIT_MASK_ACH8_DESC_MODE_8814B) \
+ << BIT_SHIFT_ACH8_DESC_MODE_8814B)
+#define BITS_ACH8_DESC_MODE_8814B \
+ (BIT_MASK_ACH8_DESC_MODE_8814B << BIT_SHIFT_ACH8_DESC_MODE_8814B)
+#define BIT_CLEAR_ACH8_DESC_MODE_8814B(x) ((x) & (~BITS_ACH8_DESC_MODE_8814B))
+#define BIT_GET_ACH8_DESC_MODE_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH8_DESC_MODE_8814B) & \
+ BIT_MASK_ACH8_DESC_MODE_8814B)
+#define BIT_SET_ACH8_DESC_MODE_8814B(x, v) \
+ (BIT_CLEAR_ACH8_DESC_MODE_8814B(x) | BIT_ACH8_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_ACH8_DESC_NUM_8814B 0
+#define BIT_MASK_ACH8_DESC_NUM_8814B 0xfff
+#define BIT_ACH8_DESC_NUM_8814B(x) \
+ (((x) & BIT_MASK_ACH8_DESC_NUM_8814B) << BIT_SHIFT_ACH8_DESC_NUM_8814B)
+#define BITS_ACH8_DESC_NUM_8814B \
+ (BIT_MASK_ACH8_DESC_NUM_8814B << BIT_SHIFT_ACH8_DESC_NUM_8814B)
+#define BIT_CLEAR_ACH8_DESC_NUM_8814B(x) ((x) & (~BITS_ACH8_DESC_NUM_8814B))
+#define BIT_GET_ACH8_DESC_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH8_DESC_NUM_8814B) & BIT_MASK_ACH8_DESC_NUM_8814B)
+#define BIT_SET_ACH8_DESC_NUM_8814B(x, v) \
+ (BIT_CLEAR_ACH8_DESC_NUM_8814B(x) | BIT_ACH8_DESC_NUM_8814B(v))
+
+/* 2 REG_ACH10_ACH11_TXBD_NUM_8814B */
+#define BIT_PCIE_ACH11_FLAG_8814B BIT(30)
+
+#define BIT_SHIFT_ACH11_DESC_MODE_8814B 28
+#define BIT_MASK_ACH11_DESC_MODE_8814B 0x3
+#define BIT_ACH11_DESC_MODE_8814B(x) \
+ (((x) & BIT_MASK_ACH11_DESC_MODE_8814B) \
+ << BIT_SHIFT_ACH11_DESC_MODE_8814B)
+#define BITS_ACH11_DESC_MODE_8814B \
+ (BIT_MASK_ACH11_DESC_MODE_8814B << BIT_SHIFT_ACH11_DESC_MODE_8814B)
+#define BIT_CLEAR_ACH11_DESC_MODE_8814B(x) ((x) & (~BITS_ACH11_DESC_MODE_8814B))
+#define BIT_GET_ACH11_DESC_MODE_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH11_DESC_MODE_8814B) & \
+ BIT_MASK_ACH11_DESC_MODE_8814B)
+#define BIT_SET_ACH11_DESC_MODE_8814B(x, v) \
+ (BIT_CLEAR_ACH11_DESC_MODE_8814B(x) | BIT_ACH11_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_ACH11_DESC_NUM_8814B 16
+#define BIT_MASK_ACH11_DESC_NUM_8814B 0xfff
+#define BIT_ACH11_DESC_NUM_8814B(x) \
+ (((x) & BIT_MASK_ACH11_DESC_NUM_8814B) \
+ << BIT_SHIFT_ACH11_DESC_NUM_8814B)
+#define BITS_ACH11_DESC_NUM_8814B \
+ (BIT_MASK_ACH11_DESC_NUM_8814B << BIT_SHIFT_ACH11_DESC_NUM_8814B)
+#define BIT_CLEAR_ACH11_DESC_NUM_8814B(x) ((x) & (~BITS_ACH11_DESC_NUM_8814B))
+#define BIT_GET_ACH11_DESC_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH11_DESC_NUM_8814B) & \
+ BIT_MASK_ACH11_DESC_NUM_8814B)
+#define BIT_SET_ACH11_DESC_NUM_8814B(x, v) \
+ (BIT_CLEAR_ACH11_DESC_NUM_8814B(x) | BIT_ACH11_DESC_NUM_8814B(v))
+
+#define BIT_PCIE_ACH10_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_ACH10_DESC_MODE_8814B 12
+#define BIT_MASK_ACH10_DESC_MODE_8814B 0x3
+#define BIT_ACH10_DESC_MODE_8814B(x) \
+ (((x) & BIT_MASK_ACH10_DESC_MODE_8814B) \
+ << BIT_SHIFT_ACH10_DESC_MODE_8814B)
+#define BITS_ACH10_DESC_MODE_8814B \
+ (BIT_MASK_ACH10_DESC_MODE_8814B << BIT_SHIFT_ACH10_DESC_MODE_8814B)
+#define BIT_CLEAR_ACH10_DESC_MODE_8814B(x) ((x) & (~BITS_ACH10_DESC_MODE_8814B))
+#define BIT_GET_ACH10_DESC_MODE_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH10_DESC_MODE_8814B) & \
+ BIT_MASK_ACH10_DESC_MODE_8814B)
+#define BIT_SET_ACH10_DESC_MODE_8814B(x, v) \
+ (BIT_CLEAR_ACH10_DESC_MODE_8814B(x) | BIT_ACH10_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_ACH10_DESC_NUM_8814B 0
+#define BIT_MASK_ACH10_DESC_NUM_8814B 0xfff
+#define BIT_ACH10_DESC_NUM_8814B(x) \
+ (((x) & BIT_MASK_ACH10_DESC_NUM_8814B) \
+ << BIT_SHIFT_ACH10_DESC_NUM_8814B)
+#define BITS_ACH10_DESC_NUM_8814B \
+ (BIT_MASK_ACH10_DESC_NUM_8814B << BIT_SHIFT_ACH10_DESC_NUM_8814B)
+#define BIT_CLEAR_ACH10_DESC_NUM_8814B(x) ((x) & (~BITS_ACH10_DESC_NUM_8814B))
+#define BIT_GET_ACH10_DESC_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH10_DESC_NUM_8814B) & \
+ BIT_MASK_ACH10_DESC_NUM_8814B)
+#define BIT_SET_ACH10_DESC_NUM_8814B(x, v) \
+ (BIT_CLEAR_ACH10_DESC_NUM_8814B(x) | BIT_ACH10_DESC_NUM_8814B(v))
+
+/* 2 REG_ACH12_ACH13_TXBD_NUM_8814B */
+#define BIT_PCIE_ACH13_FLAG_8814B BIT(30)
+
+#define BIT_SHIFT_ACH13_DESC_MODE_8814B 28
+#define BIT_MASK_ACH13_DESC_MODE_8814B 0x3
+#define BIT_ACH13_DESC_MODE_8814B(x) \
+ (((x) & BIT_MASK_ACH13_DESC_MODE_8814B) \
+ << BIT_SHIFT_ACH13_DESC_MODE_8814B)
+#define BITS_ACH13_DESC_MODE_8814B \
+ (BIT_MASK_ACH13_DESC_MODE_8814B << BIT_SHIFT_ACH13_DESC_MODE_8814B)
+#define BIT_CLEAR_ACH13_DESC_MODE_8814B(x) ((x) & (~BITS_ACH13_DESC_MODE_8814B))
+#define BIT_GET_ACH13_DESC_MODE_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH13_DESC_MODE_8814B) & \
+ BIT_MASK_ACH13_DESC_MODE_8814B)
+#define BIT_SET_ACH13_DESC_MODE_8814B(x, v) \
+ (BIT_CLEAR_ACH13_DESC_MODE_8814B(x) | BIT_ACH13_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_ACH13_DESC_NUM_8814B 16
+#define BIT_MASK_ACH13_DESC_NUM_8814B 0xfff
+#define BIT_ACH13_DESC_NUM_8814B(x) \
+ (((x) & BIT_MASK_ACH13_DESC_NUM_8814B) \
+ << BIT_SHIFT_ACH13_DESC_NUM_8814B)
+#define BITS_ACH13_DESC_NUM_8814B \
+ (BIT_MASK_ACH13_DESC_NUM_8814B << BIT_SHIFT_ACH13_DESC_NUM_8814B)
+#define BIT_CLEAR_ACH13_DESC_NUM_8814B(x) ((x) & (~BITS_ACH13_DESC_NUM_8814B))
+#define BIT_GET_ACH13_DESC_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH13_DESC_NUM_8814B) & \
+ BIT_MASK_ACH13_DESC_NUM_8814B)
+#define BIT_SET_ACH13_DESC_NUM_8814B(x, v) \
+ (BIT_CLEAR_ACH13_DESC_NUM_8814B(x) | BIT_ACH13_DESC_NUM_8814B(v))
+
+#define BIT_PCIE_ACH12_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_ACH12_DESC_MODE_8814B 12
+#define BIT_MASK_ACH12_DESC_MODE_8814B 0x3
+#define BIT_ACH12_DESC_MODE_8814B(x) \
+ (((x) & BIT_MASK_ACH12_DESC_MODE_8814B) \
+ << BIT_SHIFT_ACH12_DESC_MODE_8814B)
+#define BITS_ACH12_DESC_MODE_8814B \
+ (BIT_MASK_ACH12_DESC_MODE_8814B << BIT_SHIFT_ACH12_DESC_MODE_8814B)
+#define BIT_CLEAR_ACH12_DESC_MODE_8814B(x) ((x) & (~BITS_ACH12_DESC_MODE_8814B))
+#define BIT_GET_ACH12_DESC_MODE_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH12_DESC_MODE_8814B) & \
+ BIT_MASK_ACH12_DESC_MODE_8814B)
+#define BIT_SET_ACH12_DESC_MODE_8814B(x, v) \
+ (BIT_CLEAR_ACH12_DESC_MODE_8814B(x) | BIT_ACH12_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_ACH12_DESC_NUM_8814B 0
+#define BIT_MASK_ACH12_DESC_NUM_8814B 0xfff
+#define BIT_ACH12_DESC_NUM_8814B(x) \
+ (((x) & BIT_MASK_ACH12_DESC_NUM_8814B) \
+ << BIT_SHIFT_ACH12_DESC_NUM_8814B)
+#define BITS_ACH12_DESC_NUM_8814B \
+ (BIT_MASK_ACH12_DESC_NUM_8814B << BIT_SHIFT_ACH12_DESC_NUM_8814B)
+#define BIT_CLEAR_ACH12_DESC_NUM_8814B(x) ((x) & (~BITS_ACH12_DESC_NUM_8814B))
+#define BIT_GET_ACH12_DESC_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH12_DESC_NUM_8814B) & \
+ BIT_MASK_ACH12_DESC_NUM_8814B)
+#define BIT_SET_ACH12_DESC_NUM_8814B(x, v) \
+ (BIT_CLEAR_ACH12_DESC_NUM_8814B(x) | BIT_ACH12_DESC_NUM_8814B(v))
+
+/* 2 REG_OLD_DEHANG_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_OLD_DEHANG_8814B BIT(1)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_ACH4_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_ACH4_TXBD_DESA_L_8814B 0
+#define BIT_MASK_ACH4_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_ACH4_TXBD_DESA_L_8814B(x) \
+ (((x) & BIT_MASK_ACH4_TXBD_DESA_L_8814B) \
+ << BIT_SHIFT_ACH4_TXBD_DESA_L_8814B)
+#define BITS_ACH4_TXBD_DESA_L_8814B \
+ (BIT_MASK_ACH4_TXBD_DESA_L_8814B << BIT_SHIFT_ACH4_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_ACH4_TXBD_DESA_L_8814B(x) \
+ ((x) & (~BITS_ACH4_TXBD_DESA_L_8814B))
+#define BIT_GET_ACH4_TXBD_DESA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH4_TXBD_DESA_L_8814B) & \
+ BIT_MASK_ACH4_TXBD_DESA_L_8814B)
+#define BIT_SET_ACH4_TXBD_DESA_L_8814B(x, v) \
+ (BIT_CLEAR_ACH4_TXBD_DESA_L_8814B(x) | BIT_ACH4_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_ACH4_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_ACH4_TXBD_DESA_H_8814B 0
+#define BIT_MASK_ACH4_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_ACH4_TXBD_DESA_H_8814B(x) \
+ (((x) & BIT_MASK_ACH4_TXBD_DESA_H_8814B) \
+ << BIT_SHIFT_ACH4_TXBD_DESA_H_8814B)
+#define BITS_ACH4_TXBD_DESA_H_8814B \
+ (BIT_MASK_ACH4_TXBD_DESA_H_8814B << BIT_SHIFT_ACH4_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_ACH4_TXBD_DESA_H_8814B(x) \
+ ((x) & (~BITS_ACH4_TXBD_DESA_H_8814B))
+#define BIT_GET_ACH4_TXBD_DESA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH4_TXBD_DESA_H_8814B) & \
+ BIT_MASK_ACH4_TXBD_DESA_H_8814B)
+#define BIT_SET_ACH4_TXBD_DESA_H_8814B(x, v) \
+ (BIT_CLEAR_ACH4_TXBD_DESA_H_8814B(x) | BIT_ACH4_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI8Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI8Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI8Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI8Q_TXBD_DESA_L_8814B(x) \
+ (((x) & BIT_MASK_HI8Q_TXBD_DESA_L_8814B) \
+ << BIT_SHIFT_HI8Q_TXBD_DESA_L_8814B)
+#define BITS_HI8Q_TXBD_DESA_L_8814B \
+ (BIT_MASK_HI8Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI8Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI8Q_TXBD_DESA_L_8814B(x) \
+ ((x) & (~BITS_HI8Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI8Q_TXBD_DESA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_HI8Q_TXBD_DESA_L_8814B) & \
+ BIT_MASK_HI8Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI8Q_TXBD_DESA_L_8814B(x, v) \
+ (BIT_CLEAR_HI8Q_TXBD_DESA_L_8814B(x) | BIT_HI8Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI8Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI8Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI8Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI8Q_TXBD_DESA_H_8814B(x) \
+ (((x) & BIT_MASK_HI8Q_TXBD_DESA_H_8814B) \
+ << BIT_SHIFT_HI8Q_TXBD_DESA_H_8814B)
+#define BITS_HI8Q_TXBD_DESA_H_8814B \
+ (BIT_MASK_HI8Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI8Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI8Q_TXBD_DESA_H_8814B(x) \
+ ((x) & (~BITS_HI8Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI8Q_TXBD_DESA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_HI8Q_TXBD_DESA_H_8814B) & \
+ BIT_MASK_HI8Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI8Q_TXBD_DESA_H_8814B(x, v) \
+ (BIT_CLEAR_HI8Q_TXBD_DESA_H_8814B(x) | BIT_HI8Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI9Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI9Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI9Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI9Q_TXBD_DESA_L_8814B(x) \
+ (((x) & BIT_MASK_HI9Q_TXBD_DESA_L_8814B) \
+ << BIT_SHIFT_HI9Q_TXBD_DESA_L_8814B)
+#define BITS_HI9Q_TXBD_DESA_L_8814B \
+ (BIT_MASK_HI9Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI9Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI9Q_TXBD_DESA_L_8814B(x) \
+ ((x) & (~BITS_HI9Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI9Q_TXBD_DESA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_HI9Q_TXBD_DESA_L_8814B) & \
+ BIT_MASK_HI9Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI9Q_TXBD_DESA_L_8814B(x, v) \
+ (BIT_CLEAR_HI9Q_TXBD_DESA_L_8814B(x) | BIT_HI9Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI9Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI9Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI9Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI9Q_TXBD_DESA_H_8814B(x) \
+ (((x) & BIT_MASK_HI9Q_TXBD_DESA_H_8814B) \
+ << BIT_SHIFT_HI9Q_TXBD_DESA_H_8814B)
+#define BITS_HI9Q_TXBD_DESA_H_8814B \
+ (BIT_MASK_HI9Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI9Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI9Q_TXBD_DESA_H_8814B(x) \
+ ((x) & (~BITS_HI9Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI9Q_TXBD_DESA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_HI9Q_TXBD_DESA_H_8814B) & \
+ BIT_MASK_HI9Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI9Q_TXBD_DESA_H_8814B(x, v) \
+ (BIT_CLEAR_HI9Q_TXBD_DESA_H_8814B(x) | BIT_HI9Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI10Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI10Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI10Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI10Q_TXBD_DESA_L_8814B(x) \
+ (((x) & BIT_MASK_HI10Q_TXBD_DESA_L_8814B) \
+ << BIT_SHIFT_HI10Q_TXBD_DESA_L_8814B)
+#define BITS_HI10Q_TXBD_DESA_L_8814B \
+ (BIT_MASK_HI10Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI10Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI10Q_TXBD_DESA_L_8814B(x) \
+ ((x) & (~BITS_HI10Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI10Q_TXBD_DESA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_HI10Q_TXBD_DESA_L_8814B) & \
+ BIT_MASK_HI10Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI10Q_TXBD_DESA_L_8814B(x, v) \
+ (BIT_CLEAR_HI10Q_TXBD_DESA_L_8814B(x) | BIT_HI10Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI10Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI10Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI10Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI10Q_TXBD_DESA_H_8814B(x) \
+ (((x) & BIT_MASK_HI10Q_TXBD_DESA_H_8814B) \
+ << BIT_SHIFT_HI10Q_TXBD_DESA_H_8814B)
+#define BITS_HI10Q_TXBD_DESA_H_8814B \
+ (BIT_MASK_HI10Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI10Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI10Q_TXBD_DESA_H_8814B(x) \
+ ((x) & (~BITS_HI10Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI10Q_TXBD_DESA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_HI10Q_TXBD_DESA_H_8814B) & \
+ BIT_MASK_HI10Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI10Q_TXBD_DESA_H_8814B(x, v) \
+ (BIT_CLEAR_HI10Q_TXBD_DESA_H_8814B(x) | BIT_HI10Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI11Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI11Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI11Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI11Q_TXBD_DESA_L_8814B(x) \
+ (((x) & BIT_MASK_HI11Q_TXBD_DESA_L_8814B) \
+ << BIT_SHIFT_HI11Q_TXBD_DESA_L_8814B)
+#define BITS_HI11Q_TXBD_DESA_L_8814B \
+ (BIT_MASK_HI11Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI11Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI11Q_TXBD_DESA_L_8814B(x) \
+ ((x) & (~BITS_HI11Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI11Q_TXBD_DESA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_HI11Q_TXBD_DESA_L_8814B) & \
+ BIT_MASK_HI11Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI11Q_TXBD_DESA_L_8814B(x, v) \
+ (BIT_CLEAR_HI11Q_TXBD_DESA_L_8814B(x) | BIT_HI11Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI11Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI11Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI11Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI11Q_TXBD_DESA_H_8814B(x) \
+ (((x) & BIT_MASK_HI11Q_TXBD_DESA_H_8814B) \
+ << BIT_SHIFT_HI11Q_TXBD_DESA_H_8814B)
+#define BITS_HI11Q_TXBD_DESA_H_8814B \
+ (BIT_MASK_HI11Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI11Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI11Q_TXBD_DESA_H_8814B(x) \
+ ((x) & (~BITS_HI11Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI11Q_TXBD_DESA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_HI11Q_TXBD_DESA_H_8814B) & \
+ BIT_MASK_HI11Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI11Q_TXBD_DESA_H_8814B(x, v) \
+ (BIT_CLEAR_HI11Q_TXBD_DESA_H_8814B(x) | BIT_HI11Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI12Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI12Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI12Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI12Q_TXBD_DESA_L_8814B(x) \
+ (((x) & BIT_MASK_HI12Q_TXBD_DESA_L_8814B) \
+ << BIT_SHIFT_HI12Q_TXBD_DESA_L_8814B)
+#define BITS_HI12Q_TXBD_DESA_L_8814B \
+ (BIT_MASK_HI12Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI12Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI12Q_TXBD_DESA_L_8814B(x) \
+ ((x) & (~BITS_HI12Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI12Q_TXBD_DESA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_HI12Q_TXBD_DESA_L_8814B) & \
+ BIT_MASK_HI12Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI12Q_TXBD_DESA_L_8814B(x, v) \
+ (BIT_CLEAR_HI12Q_TXBD_DESA_L_8814B(x) | BIT_HI12Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI12Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI12Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI12Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI12Q_TXBD_DESA_H_8814B(x) \
+ (((x) & BIT_MASK_HI12Q_TXBD_DESA_H_8814B) \
+ << BIT_SHIFT_HI12Q_TXBD_DESA_H_8814B)
+#define BITS_HI12Q_TXBD_DESA_H_8814B \
+ (BIT_MASK_HI12Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI12Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI12Q_TXBD_DESA_H_8814B(x) \
+ ((x) & (~BITS_HI12Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI12Q_TXBD_DESA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_HI12Q_TXBD_DESA_H_8814B) & \
+ BIT_MASK_HI12Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI12Q_TXBD_DESA_H_8814B(x, v) \
+ (BIT_CLEAR_HI12Q_TXBD_DESA_H_8814B(x) | BIT_HI12Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI13Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI13Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI13Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI13Q_TXBD_DESA_L_8814B(x) \
+ (((x) & BIT_MASK_HI13Q_TXBD_DESA_L_8814B) \
+ << BIT_SHIFT_HI13Q_TXBD_DESA_L_8814B)
+#define BITS_HI13Q_TXBD_DESA_L_8814B \
+ (BIT_MASK_HI13Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI13Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI13Q_TXBD_DESA_L_8814B(x) \
+ ((x) & (~BITS_HI13Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI13Q_TXBD_DESA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_HI13Q_TXBD_DESA_L_8814B) & \
+ BIT_MASK_HI13Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI13Q_TXBD_DESA_L_8814B(x, v) \
+ (BIT_CLEAR_HI13Q_TXBD_DESA_L_8814B(x) | BIT_HI13Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI13Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI13Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI13Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI13Q_TXBD_DESA_H_8814B(x) \
+ (((x) & BIT_MASK_HI13Q_TXBD_DESA_H_8814B) \
+ << BIT_SHIFT_HI13Q_TXBD_DESA_H_8814B)
+#define BITS_HI13Q_TXBD_DESA_H_8814B \
+ (BIT_MASK_HI13Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI13Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI13Q_TXBD_DESA_H_8814B(x) \
+ ((x) & (~BITS_HI13Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI13Q_TXBD_DESA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_HI13Q_TXBD_DESA_H_8814B) & \
+ BIT_MASK_HI13Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI13Q_TXBD_DESA_H_8814B(x, v) \
+ (BIT_CLEAR_HI13Q_TXBD_DESA_H_8814B(x) | BIT_HI13Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI14Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI14Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI14Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI14Q_TXBD_DESA_L_8814B(x) \
+ (((x) & BIT_MASK_HI14Q_TXBD_DESA_L_8814B) \
+ << BIT_SHIFT_HI14Q_TXBD_DESA_L_8814B)
+#define BITS_HI14Q_TXBD_DESA_L_8814B \
+ (BIT_MASK_HI14Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI14Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI14Q_TXBD_DESA_L_8814B(x) \
+ ((x) & (~BITS_HI14Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI14Q_TXBD_DESA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_HI14Q_TXBD_DESA_L_8814B) & \
+ BIT_MASK_HI14Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI14Q_TXBD_DESA_L_8814B(x, v) \
+ (BIT_CLEAR_HI14Q_TXBD_DESA_L_8814B(x) | BIT_HI14Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI14Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI14Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI14Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI14Q_TXBD_DESA_H_8814B(x) \
+ (((x) & BIT_MASK_HI14Q_TXBD_DESA_H_8814B) \
+ << BIT_SHIFT_HI14Q_TXBD_DESA_H_8814B)
+#define BITS_HI14Q_TXBD_DESA_H_8814B \
+ (BIT_MASK_HI14Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI14Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI14Q_TXBD_DESA_H_8814B(x) \
+ ((x) & (~BITS_HI14Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI14Q_TXBD_DESA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_HI14Q_TXBD_DESA_H_8814B) & \
+ BIT_MASK_HI14Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI14Q_TXBD_DESA_H_8814B(x, v) \
+ (BIT_CLEAR_HI14Q_TXBD_DESA_H_8814B(x) | BIT_HI14Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI15Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI15Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI15Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI15Q_TXBD_DESA_L_8814B(x) \
+ (((x) & BIT_MASK_HI15Q_TXBD_DESA_L_8814B) \
+ << BIT_SHIFT_HI15Q_TXBD_DESA_L_8814B)
+#define BITS_HI15Q_TXBD_DESA_L_8814B \
+ (BIT_MASK_HI15Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI15Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI15Q_TXBD_DESA_L_8814B(x) \
+ ((x) & (~BITS_HI15Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI15Q_TXBD_DESA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_HI15Q_TXBD_DESA_L_8814B) & \
+ BIT_MASK_HI15Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI15Q_TXBD_DESA_L_8814B(x, v) \
+ (BIT_CLEAR_HI15Q_TXBD_DESA_L_8814B(x) | BIT_HI15Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI15Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI15Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI15Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI15Q_TXBD_DESA_H_8814B(x) \
+ (((x) & BIT_MASK_HI15Q_TXBD_DESA_H_8814B) \
+ << BIT_SHIFT_HI15Q_TXBD_DESA_H_8814B)
+#define BITS_HI15Q_TXBD_DESA_H_8814B \
+ (BIT_MASK_HI15Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI15Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI15Q_TXBD_DESA_H_8814B(x) \
+ ((x) & (~BITS_HI15Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI15Q_TXBD_DESA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_HI15Q_TXBD_DESA_H_8814B) & \
+ BIT_MASK_HI15Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI15Q_TXBD_DESA_H_8814B(x, v) \
+ (BIT_CLEAR_HI15Q_TXBD_DESA_H_8814B(x) | BIT_HI15Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI16Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI16Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI16Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI16Q_TXBD_DESA_L_8814B(x) \
+ (((x) & BIT_MASK_HI16Q_TXBD_DESA_L_8814B) \
+ << BIT_SHIFT_HI16Q_TXBD_DESA_L_8814B)
+#define BITS_HI16Q_TXBD_DESA_L_8814B \
+ (BIT_MASK_HI16Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI16Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI16Q_TXBD_DESA_L_8814B(x) \
+ ((x) & (~BITS_HI16Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI16Q_TXBD_DESA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_HI16Q_TXBD_DESA_L_8814B) & \
+ BIT_MASK_HI16Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI16Q_TXBD_DESA_L_8814B(x, v) \
+ (BIT_CLEAR_HI16Q_TXBD_DESA_L_8814B(x) | BIT_HI16Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI16Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI16Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI16Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI16Q_TXBD_DESA_H_8814B(x) \
+ (((x) & BIT_MASK_HI16Q_TXBD_DESA_H_8814B) \
+ << BIT_SHIFT_HI16Q_TXBD_DESA_H_8814B)
+#define BITS_HI16Q_TXBD_DESA_H_8814B \
+ (BIT_MASK_HI16Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI16Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI16Q_TXBD_DESA_H_8814B(x) \
+ ((x) & (~BITS_HI16Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI16Q_TXBD_DESA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_HI16Q_TXBD_DESA_H_8814B) & \
+ BIT_MASK_HI16Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI16Q_TXBD_DESA_H_8814B(x, v) \
+ (BIT_CLEAR_HI16Q_TXBD_DESA_H_8814B(x) | BIT_HI16Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI17Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI17Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI17Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI17Q_TXBD_DESA_L_8814B(x) \
+ (((x) & BIT_MASK_HI17Q_TXBD_DESA_L_8814B) \
+ << BIT_SHIFT_HI17Q_TXBD_DESA_L_8814B)
+#define BITS_HI17Q_TXBD_DESA_L_8814B \
+ (BIT_MASK_HI17Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI17Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI17Q_TXBD_DESA_L_8814B(x) \
+ ((x) & (~BITS_HI17Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI17Q_TXBD_DESA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_HI17Q_TXBD_DESA_L_8814B) & \
+ BIT_MASK_HI17Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI17Q_TXBD_DESA_L_8814B(x, v) \
+ (BIT_CLEAR_HI17Q_TXBD_DESA_L_8814B(x) | BIT_HI17Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI17Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI17Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI17Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI17Q_TXBD_DESA_H_8814B(x) \
+ (((x) & BIT_MASK_HI17Q_TXBD_DESA_H_8814B) \
+ << BIT_SHIFT_HI17Q_TXBD_DESA_H_8814B)
+#define BITS_HI17Q_TXBD_DESA_H_8814B \
+ (BIT_MASK_HI17Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI17Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI17Q_TXBD_DESA_H_8814B(x) \
+ ((x) & (~BITS_HI17Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI17Q_TXBD_DESA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_HI17Q_TXBD_DESA_H_8814B) & \
+ BIT_MASK_HI17Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI17Q_TXBD_DESA_H_8814B(x, v) \
+ (BIT_CLEAR_HI17Q_TXBD_DESA_H_8814B(x) | BIT_HI17Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI18Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI18Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI18Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI18Q_TXBD_DESA_L_8814B(x) \
+ (((x) & BIT_MASK_HI18Q_TXBD_DESA_L_8814B) \
+ << BIT_SHIFT_HI18Q_TXBD_DESA_L_8814B)
+#define BITS_HI18Q_TXBD_DESA_L_8814B \
+ (BIT_MASK_HI18Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI18Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI18Q_TXBD_DESA_L_8814B(x) \
+ ((x) & (~BITS_HI18Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI18Q_TXBD_DESA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_HI18Q_TXBD_DESA_L_8814B) & \
+ BIT_MASK_HI18Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI18Q_TXBD_DESA_L_8814B(x, v) \
+ (BIT_CLEAR_HI18Q_TXBD_DESA_L_8814B(x) | BIT_HI18Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI18Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI18Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI18Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI18Q_TXBD_DESA_H_8814B(x) \
+ (((x) & BIT_MASK_HI18Q_TXBD_DESA_H_8814B) \
+ << BIT_SHIFT_HI18Q_TXBD_DESA_H_8814B)
+#define BITS_HI18Q_TXBD_DESA_H_8814B \
+ (BIT_MASK_HI18Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI18Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI18Q_TXBD_DESA_H_8814B(x) \
+ ((x) & (~BITS_HI18Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI18Q_TXBD_DESA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_HI18Q_TXBD_DESA_H_8814B) & \
+ BIT_MASK_HI18Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI18Q_TXBD_DESA_H_8814B(x, v) \
+ (BIT_CLEAR_HI18Q_TXBD_DESA_H_8814B(x) | BIT_HI18Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_HI19Q_TXBD_DESA_L_8814B */
+
+#define BIT_SHIFT_HI19Q_TXBD_DESA_L_8814B 0
+#define BIT_MASK_HI19Q_TXBD_DESA_L_8814B 0xffffffffL
+#define BIT_HI19Q_TXBD_DESA_L_8814B(x) \
+ (((x) & BIT_MASK_HI19Q_TXBD_DESA_L_8814B) \
+ << BIT_SHIFT_HI19Q_TXBD_DESA_L_8814B)
+#define BITS_HI19Q_TXBD_DESA_L_8814B \
+ (BIT_MASK_HI19Q_TXBD_DESA_L_8814B << BIT_SHIFT_HI19Q_TXBD_DESA_L_8814B)
+#define BIT_CLEAR_HI19Q_TXBD_DESA_L_8814B(x) \
+ ((x) & (~BITS_HI19Q_TXBD_DESA_L_8814B))
+#define BIT_GET_HI19Q_TXBD_DESA_L_8814B(x) \
+ (((x) >> BIT_SHIFT_HI19Q_TXBD_DESA_L_8814B) & \
+ BIT_MASK_HI19Q_TXBD_DESA_L_8814B)
+#define BIT_SET_HI19Q_TXBD_DESA_L_8814B(x, v) \
+ (BIT_CLEAR_HI19Q_TXBD_DESA_L_8814B(x) | BIT_HI19Q_TXBD_DESA_L_8814B(v))
+
+/* 2 REG_HI19Q_TXBD_DESA_H_8814B */
+
+#define BIT_SHIFT_HI19Q_TXBD_DESA_H_8814B 0
+#define BIT_MASK_HI19Q_TXBD_DESA_H_8814B 0xffffffffL
+#define BIT_HI19Q_TXBD_DESA_H_8814B(x) \
+ (((x) & BIT_MASK_HI19Q_TXBD_DESA_H_8814B) \
+ << BIT_SHIFT_HI19Q_TXBD_DESA_H_8814B)
+#define BITS_HI19Q_TXBD_DESA_H_8814B \
+ (BIT_MASK_HI19Q_TXBD_DESA_H_8814B << BIT_SHIFT_HI19Q_TXBD_DESA_H_8814B)
+#define BIT_CLEAR_HI19Q_TXBD_DESA_H_8814B(x) \
+ ((x) & (~BITS_HI19Q_TXBD_DESA_H_8814B))
+#define BIT_GET_HI19Q_TXBD_DESA_H_8814B(x) \
+ (((x) >> BIT_SHIFT_HI19Q_TXBD_DESA_H_8814B) & \
+ BIT_MASK_HI19Q_TXBD_DESA_H_8814B)
+#define BIT_SET_HI19Q_TXBD_DESA_H_8814B(x, v) \
+ (BIT_CLEAR_HI19Q_TXBD_DESA_H_8814B(x) | BIT_HI19Q_TXBD_DESA_H_8814B(v))
+
+/* 2 REG_BD_RWPTR_CLR6_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_CLR_P0HI19Q_HW_IDX_8814B BIT(25)
+#define BIT_CLR_P0HI18Q_HW_IDX_8814B BIT(24)
+#define BIT_CLR_P0HI17Q_HW_IDX_8814B BIT(23)
+#define BIT_CLR_P0HI16Q_HW_IDX_8814B BIT(22)
+
+/* 2 REG_NOT_VALID_8814B */
+#define BIT_CLR_P0HI19Q_HOST_IDX_8814B BIT(9)
+#define BIT_CLR_P0HI18Q_HOST_IDX_8814B BIT(8)
+#define BIT_CLR_P0HI17Q_HOST_IDX_8814B BIT(7)
+#define BIT_CLR_P0HI16Q_HOST_IDX_8814B BIT(6)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_P0HI16Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI16Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI16Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI16Q_HW_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI16Q_HW_IDX_8814B) \
+ << BIT_SHIFT_P0HI16Q_HW_IDX_8814B)
+#define BITS_P0HI16Q_HW_IDX_8814B \
+ (BIT_MASK_P0HI16Q_HW_IDX_8814B << BIT_SHIFT_P0HI16Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI16Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI16Q_HW_IDX_8814B))
+#define BIT_GET_P0HI16Q_HW_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI16Q_HW_IDX_8814B) & \
+ BIT_MASK_P0HI16Q_HW_IDX_8814B)
+#define BIT_SET_P0HI16Q_HW_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI16Q_HW_IDX_8814B(x) | BIT_P0HI16Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI16Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI16Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI16Q_HOST_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI16Q_HOST_IDX_8814B) \
+ << BIT_SHIFT_P0HI16Q_HOST_IDX_8814B)
+#define BITS_P0HI16Q_HOST_IDX_8814B \
+ (BIT_MASK_P0HI16Q_HOST_IDX_8814B << BIT_SHIFT_P0HI16Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI16Q_HOST_IDX_8814B(x) \
+ ((x) & (~BITS_P0HI16Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI16Q_HOST_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI16Q_HOST_IDX_8814B) & \
+ BIT_MASK_P0HI16Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI16Q_HOST_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI16Q_HOST_IDX_8814B(x) | BIT_P0HI16Q_HOST_IDX_8814B(v))
+
+/* 2 REG_P0HI17Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI17Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI17Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI17Q_HW_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI17Q_HW_IDX_8814B) \
+ << BIT_SHIFT_P0HI17Q_HW_IDX_8814B)
+#define BITS_P0HI17Q_HW_IDX_8814B \
+ (BIT_MASK_P0HI17Q_HW_IDX_8814B << BIT_SHIFT_P0HI17Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI17Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI17Q_HW_IDX_8814B))
+#define BIT_GET_P0HI17Q_HW_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI17Q_HW_IDX_8814B) & \
+ BIT_MASK_P0HI17Q_HW_IDX_8814B)
+#define BIT_SET_P0HI17Q_HW_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI17Q_HW_IDX_8814B(x) | BIT_P0HI17Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI17Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI17Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI17Q_HOST_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI17Q_HOST_IDX_8814B) \
+ << BIT_SHIFT_P0HI17Q_HOST_IDX_8814B)
+#define BITS_P0HI17Q_HOST_IDX_8814B \
+ (BIT_MASK_P0HI17Q_HOST_IDX_8814B << BIT_SHIFT_P0HI17Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI17Q_HOST_IDX_8814B(x) \
+ ((x) & (~BITS_P0HI17Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI17Q_HOST_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI17Q_HOST_IDX_8814B) & \
+ BIT_MASK_P0HI17Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI17Q_HOST_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI17Q_HOST_IDX_8814B(x) | BIT_P0HI17Q_HOST_IDX_8814B(v))
+
+/* 2 REG_P0HI18Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI18Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI18Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI18Q_HW_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI18Q_HW_IDX_8814B) \
+ << BIT_SHIFT_P0HI18Q_HW_IDX_8814B)
+#define BITS_P0HI18Q_HW_IDX_8814B \
+ (BIT_MASK_P0HI18Q_HW_IDX_8814B << BIT_SHIFT_P0HI18Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI18Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI18Q_HW_IDX_8814B))
+#define BIT_GET_P0HI18Q_HW_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI18Q_HW_IDX_8814B) & \
+ BIT_MASK_P0HI18Q_HW_IDX_8814B)
+#define BIT_SET_P0HI18Q_HW_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI18Q_HW_IDX_8814B(x) | BIT_P0HI18Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI18Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI18Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI18Q_HOST_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI18Q_HOST_IDX_8814B) \
+ << BIT_SHIFT_P0HI18Q_HOST_IDX_8814B)
+#define BITS_P0HI18Q_HOST_IDX_8814B \
+ (BIT_MASK_P0HI18Q_HOST_IDX_8814B << BIT_SHIFT_P0HI18Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI18Q_HOST_IDX_8814B(x) \
+ ((x) & (~BITS_P0HI18Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI18Q_HOST_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI18Q_HOST_IDX_8814B) & \
+ BIT_MASK_P0HI18Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI18Q_HOST_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI18Q_HOST_IDX_8814B(x) | BIT_P0HI18Q_HOST_IDX_8814B(v))
+
+/* 2 REG_P0HI19Q_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_P0HI19Q_HW_IDX_8814B 16
+#define BIT_MASK_P0HI19Q_HW_IDX_8814B 0xfff
+#define BIT_P0HI19Q_HW_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI19Q_HW_IDX_8814B) \
+ << BIT_SHIFT_P0HI19Q_HW_IDX_8814B)
+#define BITS_P0HI19Q_HW_IDX_8814B \
+ (BIT_MASK_P0HI19Q_HW_IDX_8814B << BIT_SHIFT_P0HI19Q_HW_IDX_8814B)
+#define BIT_CLEAR_P0HI19Q_HW_IDX_8814B(x) ((x) & (~BITS_P0HI19Q_HW_IDX_8814B))
+#define BIT_GET_P0HI19Q_HW_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI19Q_HW_IDX_8814B) & \
+ BIT_MASK_P0HI19Q_HW_IDX_8814B)
+#define BIT_SET_P0HI19Q_HW_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI19Q_HW_IDX_8814B(x) | BIT_P0HI19Q_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_P0HI19Q_HOST_IDX_8814B 0
+#define BIT_MASK_P0HI19Q_HOST_IDX_8814B 0xfff
+#define BIT_P0HI19Q_HOST_IDX_8814B(x) \
+ (((x) & BIT_MASK_P0HI19Q_HOST_IDX_8814B) \
+ << BIT_SHIFT_P0HI19Q_HOST_IDX_8814B)
+#define BITS_P0HI19Q_HOST_IDX_8814B \
+ (BIT_MASK_P0HI19Q_HOST_IDX_8814B << BIT_SHIFT_P0HI19Q_HOST_IDX_8814B)
+#define BIT_CLEAR_P0HI19Q_HOST_IDX_8814B(x) \
+ ((x) & (~BITS_P0HI19Q_HOST_IDX_8814B))
+#define BIT_GET_P0HI19Q_HOST_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI19Q_HOST_IDX_8814B) & \
+ BIT_MASK_P0HI19Q_HOST_IDX_8814B)
+#define BIT_SET_P0HI19Q_HOST_IDX_8814B(x, v) \
+ (BIT_CLEAR_P0HI19Q_HOST_IDX_8814B(x) | BIT_P0HI19Q_HOST_IDX_8814B(v))
+
+/* 2 REG_P0HI16Q_HI17Q_TXBD_NUM_8814B */
+#define BIT_P0HI17Q_FLAG_8814B BIT(30)
+
+#define BIT_SHIFT_P0HI17Q_DESC_MODE_8814B 28
+#define BIT_MASK_P0HI17Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI17Q_DESC_MODE_8814B(x) \
+ (((x) & BIT_MASK_P0HI17Q_DESC_MODE_8814B) \
+ << BIT_SHIFT_P0HI17Q_DESC_MODE_8814B)
+#define BITS_P0HI17Q_DESC_MODE_8814B \
+ (BIT_MASK_P0HI17Q_DESC_MODE_8814B << BIT_SHIFT_P0HI17Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI17Q_DESC_MODE_8814B(x) \
+ ((x) & (~BITS_P0HI17Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI17Q_DESC_MODE_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI17Q_DESC_MODE_8814B) & \
+ BIT_MASK_P0HI17Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI17Q_DESC_MODE_8814B(x, v) \
+ (BIT_CLEAR_P0HI17Q_DESC_MODE_8814B(x) | BIT_P0HI17Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI17Q_DESC_NUM_8814B 16
+#define BIT_MASK_P0HI17Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI17Q_DESC_NUM_8814B(x) \
+ (((x) & BIT_MASK_P0HI17Q_DESC_NUM_8814B) \
+ << BIT_SHIFT_P0HI17Q_DESC_NUM_8814B)
+#define BITS_P0HI17Q_DESC_NUM_8814B \
+ (BIT_MASK_P0HI17Q_DESC_NUM_8814B << BIT_SHIFT_P0HI17Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI17Q_DESC_NUM_8814B(x) \
+ ((x) & (~BITS_P0HI17Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI17Q_DESC_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI17Q_DESC_NUM_8814B) & \
+ BIT_MASK_P0HI17Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI17Q_DESC_NUM_8814B(x, v) \
+ (BIT_CLEAR_P0HI17Q_DESC_NUM_8814B(x) | BIT_P0HI17Q_DESC_NUM_8814B(v))
+
+#define BIT_P0HI16Q_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_P0HI16Q_DESC_MODE_8814B 12
+#define BIT_MASK_P0HI16Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI16Q_DESC_MODE_8814B(x) \
+ (((x) & BIT_MASK_P0HI16Q_DESC_MODE_8814B) \
+ << BIT_SHIFT_P0HI16Q_DESC_MODE_8814B)
+#define BITS_P0HI16Q_DESC_MODE_8814B \
+ (BIT_MASK_P0HI16Q_DESC_MODE_8814B << BIT_SHIFT_P0HI16Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI16Q_DESC_MODE_8814B(x) \
+ ((x) & (~BITS_P0HI16Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI16Q_DESC_MODE_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI16Q_DESC_MODE_8814B) & \
+ BIT_MASK_P0HI16Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI16Q_DESC_MODE_8814B(x, v) \
+ (BIT_CLEAR_P0HI16Q_DESC_MODE_8814B(x) | BIT_P0HI16Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI16Q_DESC_NUM_8814B 0
+#define BIT_MASK_P0HI16Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI16Q_DESC_NUM_8814B(x) \
+ (((x) & BIT_MASK_P0HI16Q_DESC_NUM_8814B) \
+ << BIT_SHIFT_P0HI16Q_DESC_NUM_8814B)
+#define BITS_P0HI16Q_DESC_NUM_8814B \
+ (BIT_MASK_P0HI16Q_DESC_NUM_8814B << BIT_SHIFT_P0HI16Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI16Q_DESC_NUM_8814B(x) \
+ ((x) & (~BITS_P0HI16Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI16Q_DESC_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI16Q_DESC_NUM_8814B) & \
+ BIT_MASK_P0HI16Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI16Q_DESC_NUM_8814B(x, v) \
+ (BIT_CLEAR_P0HI16Q_DESC_NUM_8814B(x) | BIT_P0HI16Q_DESC_NUM_8814B(v))
+
+/* 2 REG_P0HI18Q_HI19Q_TXBD_NUM_8814B */
+#define BIT_P0HI19Q_FLAG_8814B BIT(30)
+
+#define BIT_SHIFT_P0HI19Q_DESC_MODE_8814B 28
+#define BIT_MASK_P0HI19Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI19Q_DESC_MODE_8814B(x) \
+ (((x) & BIT_MASK_P0HI19Q_DESC_MODE_8814B) \
+ << BIT_SHIFT_P0HI19Q_DESC_MODE_8814B)
+#define BITS_P0HI19Q_DESC_MODE_8814B \
+ (BIT_MASK_P0HI19Q_DESC_MODE_8814B << BIT_SHIFT_P0HI19Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI19Q_DESC_MODE_8814B(x) \
+ ((x) & (~BITS_P0HI19Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI19Q_DESC_MODE_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI19Q_DESC_MODE_8814B) & \
+ BIT_MASK_P0HI19Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI19Q_DESC_MODE_8814B(x, v) \
+ (BIT_CLEAR_P0HI19Q_DESC_MODE_8814B(x) | BIT_P0HI19Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI19Q_DESC_NUM_8814B 16
+#define BIT_MASK_P0HI19Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI19Q_DESC_NUM_8814B(x) \
+ (((x) & BIT_MASK_P0HI19Q_DESC_NUM_8814B) \
+ << BIT_SHIFT_P0HI19Q_DESC_NUM_8814B)
+#define BITS_P0HI19Q_DESC_NUM_8814B \
+ (BIT_MASK_P0HI19Q_DESC_NUM_8814B << BIT_SHIFT_P0HI19Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI19Q_DESC_NUM_8814B(x) \
+ ((x) & (~BITS_P0HI19Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI19Q_DESC_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI19Q_DESC_NUM_8814B) & \
+ BIT_MASK_P0HI19Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI19Q_DESC_NUM_8814B(x, v) \
+ (BIT_CLEAR_P0HI19Q_DESC_NUM_8814B(x) | BIT_P0HI19Q_DESC_NUM_8814B(v))
+
+#define BIT_P0HI18Q_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_P0HI18Q_DESC_MODE_8814B 12
+#define BIT_MASK_P0HI18Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI18Q_DESC_MODE_8814B(x) \
+ (((x) & BIT_MASK_P0HI18Q_DESC_MODE_8814B) \
+ << BIT_SHIFT_P0HI18Q_DESC_MODE_8814B)
+#define BITS_P0HI18Q_DESC_MODE_8814B \
+ (BIT_MASK_P0HI18Q_DESC_MODE_8814B << BIT_SHIFT_P0HI18Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI18Q_DESC_MODE_8814B(x) \
+ ((x) & (~BITS_P0HI18Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI18Q_DESC_MODE_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI18Q_DESC_MODE_8814B) & \
+ BIT_MASK_P0HI18Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI18Q_DESC_MODE_8814B(x, v) \
+ (BIT_CLEAR_P0HI18Q_DESC_MODE_8814B(x) | BIT_P0HI18Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI18Q_DESC_NUM_8814B 0
+#define BIT_MASK_P0HI18Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI18Q_DESC_NUM_8814B(x) \
+ (((x) & BIT_MASK_P0HI18Q_DESC_NUM_8814B) \
+ << BIT_SHIFT_P0HI18Q_DESC_NUM_8814B)
+#define BITS_P0HI18Q_DESC_NUM_8814B \
+ (BIT_MASK_P0HI18Q_DESC_NUM_8814B << BIT_SHIFT_P0HI18Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI18Q_DESC_NUM_8814B(x) \
+ ((x) & (~BITS_P0HI18Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI18Q_DESC_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI18Q_DESC_NUM_8814B) & \
+ BIT_MASK_P0HI18Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI18Q_DESC_NUM_8814B(x, v) \
+ (BIT_CLEAR_P0HI18Q_DESC_NUM_8814B(x) | BIT_P0HI18Q_DESC_NUM_8814B(v))
+
+/* 2 REG_PCIE_HISR0_8814B */
+#define BIT_PSTIMER_2_8814B BIT(31)
+#define BIT_PSTIMER_1_8814B BIT(30)
+#define BIT_PSTIMER_0_8814B BIT(29)
+#define BIT_GTINT4_8814B BIT(28)
+#define BIT_GTINT3_8814B BIT(27)
+#define BIT_TXBCN0ERR_8814B BIT(26)
+#define BIT_TXBCN0OK_8814B BIT(25)
+#define BIT_TSF_BIT32_TOGGLE_8814B BIT(24)
+#define BIT_TXDMA_START_INT_8814B BIT(23)
+#define BIT_TXDMA_STOP_INT_8814B BIT(22)
+#define BIT_HISR7_IND_8814B BIT(21)
+#define BIT_BCNDMAINT0_8814B BIT(20)
+#define BIT_HISR6_IND_8814B BIT(19)
+#define BIT_HISR5_IND_8814B BIT(18)
+#define BIT_HISR4_IND_8814B BIT(17)
+#define BIT_BCNDERR0_8814B BIT(16)
+#define BIT_HSISR_IND_ON_INT_8814B BIT(15)
+#define BIT_HISR3_IND_8814B BIT(14)
+#define BIT_HISR2_IND_8814B BIT(13)
+#define BIT_HISR1_IND_8814B BIT(11)
+#define BIT_C2HCMD_8814B BIT(10)
+#define BIT_CPWM2_8814B BIT(9)
+#define BIT_CPWM_8814B BIT(8)
+#define BIT_TXDMAOK_CHANNEL15_8814B BIT(7)
+#define BIT_TXDMAOK_CHANNEL14_8814B BIT(6)
+#define BIT_TXDMAOK_CHANNEL3_8814B BIT(5)
+#define BIT_TXDMAOK_CHANNEL2_8814B BIT(4)
+#define BIT_TXDMAOK_CHANNEL1_8814B BIT(3)
+#define BIT_TXDMAOK_CHANNEL0_8814B BIT(2)
+#define BIT_RDU_8814B BIT(1)
+#define BIT_RXOK_8814B BIT(0)
+
+/* 2 REG_PCIE_HISR1_8814B */
+#define BIT_PRE_TX_ERR_INT_8814B BIT(31)
+#define BIT_TXFIFO_TH_INT_8814B BIT(30)
+#define BIT_BTON_STS_UPDATE_INT_8814B BIT(29)
+#define BIT_BCNDMAINT7_8814B BIT(27)
+#define BIT_BCNDMAINT6_8814B BIT(26)
+#define BIT_BCNDMAINT5_8814B BIT(25)
+#define BIT_BCNDMAINT4_8814B BIT(24)
+#define BIT_BCNDMAINT3_8814B BIT(23)
+#define BIT_BCNDMAINT2_8814B BIT(22)
+#define BIT_BCNDMAINT1_8814B BIT(21)
+#define BIT_BCNDERR7_8814B BIT(20)
+#define BIT_BCNDERR6_8814B BIT(19)
+#define BIT_BCNDERR5_8814B BIT(18)
+#define BIT_BCNDERR4_8814B BIT(17)
+#define BIT_BCNDERR3_8814B BIT(16)
+#define BIT_BCNDERR2_8814B BIT(15)
+#define BIT_BCNDERR1_8814B BIT(14)
+#define BIT_ATIMEND_8814B BIT(12)
+#define BIT_TXERR_INT_8814B BIT(11)
+#define BIT_RXERR_INT_8814B BIT(10)
+#define BIT_TXFOVW_8814B BIT(9)
+#define BIT_FOVW_8814B BIT(8)
+#define BIT_CPU_MGQ_EARLY_INT_8814B BIT(6)
+#define BIT_CPU_MGQ_TXDONE_8814B BIT(5)
+#define BIT_PSTIMER_5_8814B BIT(4)
+#define BIT_PSTIMER_4_8814B BIT(3)
+#define BIT_PSTIMER_3_8814B BIT(2)
+#define BIT_CPUMGQ_TX_TIMER_8814B BIT(1)
+#define BIT_BB_STOPRX_INT_8814B BIT(0)
+
+/* 2 REG_P0HI8Q_HI9Q_TXBD_NUM_8814B */
+#define BIT_P0HI9Q_FLAG_8814B BIT(30)
+
+#define BIT_SHIFT_P0HI9Q_DESC_MODE_8814B 28
+#define BIT_MASK_P0HI9Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI9Q_DESC_MODE_8814B(x) \
+ (((x) & BIT_MASK_P0HI9Q_DESC_MODE_8814B) \
+ << BIT_SHIFT_P0HI9Q_DESC_MODE_8814B)
+#define BITS_P0HI9Q_DESC_MODE_8814B \
+ (BIT_MASK_P0HI9Q_DESC_MODE_8814B << BIT_SHIFT_P0HI9Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI9Q_DESC_MODE_8814B(x) \
+ ((x) & (~BITS_P0HI9Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI9Q_DESC_MODE_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI9Q_DESC_MODE_8814B) & \
+ BIT_MASK_P0HI9Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI9Q_DESC_MODE_8814B(x, v) \
+ (BIT_CLEAR_P0HI9Q_DESC_MODE_8814B(x) | BIT_P0HI9Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI9Q_DESC_NUM_8814B 16
+#define BIT_MASK_P0HI9Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI9Q_DESC_NUM_8814B(x) \
+ (((x) & BIT_MASK_P0HI9Q_DESC_NUM_8814B) \
+ << BIT_SHIFT_P0HI9Q_DESC_NUM_8814B)
+#define BITS_P0HI9Q_DESC_NUM_8814B \
+ (BIT_MASK_P0HI9Q_DESC_NUM_8814B << BIT_SHIFT_P0HI9Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI9Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI9Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI9Q_DESC_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI9Q_DESC_NUM_8814B) & \
+ BIT_MASK_P0HI9Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI9Q_DESC_NUM_8814B(x, v) \
+ (BIT_CLEAR_P0HI9Q_DESC_NUM_8814B(x) | BIT_P0HI9Q_DESC_NUM_8814B(v))
+
+#define BIT_P0HI8Q_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_P0HI8Q_DESC_MODE_8814B 12
+#define BIT_MASK_P0HI8Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI8Q_DESC_MODE_8814B(x) \
+ (((x) & BIT_MASK_P0HI8Q_DESC_MODE_8814B) \
+ << BIT_SHIFT_P0HI8Q_DESC_MODE_8814B)
+#define BITS_P0HI8Q_DESC_MODE_8814B \
+ (BIT_MASK_P0HI8Q_DESC_MODE_8814B << BIT_SHIFT_P0HI8Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI8Q_DESC_MODE_8814B(x) \
+ ((x) & (~BITS_P0HI8Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI8Q_DESC_MODE_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI8Q_DESC_MODE_8814B) & \
+ BIT_MASK_P0HI8Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI8Q_DESC_MODE_8814B(x, v) \
+ (BIT_CLEAR_P0HI8Q_DESC_MODE_8814B(x) | BIT_P0HI8Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI8Q_DESC_NUM_8814B 0
+#define BIT_MASK_P0HI8Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI8Q_DESC_NUM_8814B(x) \
+ (((x) & BIT_MASK_P0HI8Q_DESC_NUM_8814B) \
+ << BIT_SHIFT_P0HI8Q_DESC_NUM_8814B)
+#define BITS_P0HI8Q_DESC_NUM_8814B \
+ (BIT_MASK_P0HI8Q_DESC_NUM_8814B << BIT_SHIFT_P0HI8Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI8Q_DESC_NUM_8814B(x) ((x) & (~BITS_P0HI8Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI8Q_DESC_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI8Q_DESC_NUM_8814B) & \
+ BIT_MASK_P0HI8Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI8Q_DESC_NUM_8814B(x, v) \
+ (BIT_CLEAR_P0HI8Q_DESC_NUM_8814B(x) | BIT_P0HI8Q_DESC_NUM_8814B(v))
+
+/* 2 REG_P0HI10Q_HI11Q_TXBD_NUM_8814B */
+#define BIT_P0HI11Q_FLAG_8814B BIT(30)
+
+#define BIT_SHIFT_P0HI11Q_DESC_MODE_8814B 28
+#define BIT_MASK_P0HI11Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI11Q_DESC_MODE_8814B(x) \
+ (((x) & BIT_MASK_P0HI11Q_DESC_MODE_8814B) \
+ << BIT_SHIFT_P0HI11Q_DESC_MODE_8814B)
+#define BITS_P0HI11Q_DESC_MODE_8814B \
+ (BIT_MASK_P0HI11Q_DESC_MODE_8814B << BIT_SHIFT_P0HI11Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI11Q_DESC_MODE_8814B(x) \
+ ((x) & (~BITS_P0HI11Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI11Q_DESC_MODE_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI11Q_DESC_MODE_8814B) & \
+ BIT_MASK_P0HI11Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI11Q_DESC_MODE_8814B(x, v) \
+ (BIT_CLEAR_P0HI11Q_DESC_MODE_8814B(x) | BIT_P0HI11Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI11Q_DESC_NUM_8814B 16
+#define BIT_MASK_P0HI11Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI11Q_DESC_NUM_8814B(x) \
+ (((x) & BIT_MASK_P0HI11Q_DESC_NUM_8814B) \
+ << BIT_SHIFT_P0HI11Q_DESC_NUM_8814B)
+#define BITS_P0HI11Q_DESC_NUM_8814B \
+ (BIT_MASK_P0HI11Q_DESC_NUM_8814B << BIT_SHIFT_P0HI11Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI11Q_DESC_NUM_8814B(x) \
+ ((x) & (~BITS_P0HI11Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI11Q_DESC_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI11Q_DESC_NUM_8814B) & \
+ BIT_MASK_P0HI11Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI11Q_DESC_NUM_8814B(x, v) \
+ (BIT_CLEAR_P0HI11Q_DESC_NUM_8814B(x) | BIT_P0HI11Q_DESC_NUM_8814B(v))
+
+#define BIT_P0HI10Q_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_P0HI10Q_DESC_MODE_8814B 12
+#define BIT_MASK_P0HI10Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI10Q_DESC_MODE_8814B(x) \
+ (((x) & BIT_MASK_P0HI10Q_DESC_MODE_8814B) \
+ << BIT_SHIFT_P0HI10Q_DESC_MODE_8814B)
+#define BITS_P0HI10Q_DESC_MODE_8814B \
+ (BIT_MASK_P0HI10Q_DESC_MODE_8814B << BIT_SHIFT_P0HI10Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI10Q_DESC_MODE_8814B(x) \
+ ((x) & (~BITS_P0HI10Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI10Q_DESC_MODE_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI10Q_DESC_MODE_8814B) & \
+ BIT_MASK_P0HI10Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI10Q_DESC_MODE_8814B(x, v) \
+ (BIT_CLEAR_P0HI10Q_DESC_MODE_8814B(x) | BIT_P0HI10Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI10Q_DESC_NUM_8814B 0
+#define BIT_MASK_P0HI10Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI10Q_DESC_NUM_8814B(x) \
+ (((x) & BIT_MASK_P0HI10Q_DESC_NUM_8814B) \
+ << BIT_SHIFT_P0HI10Q_DESC_NUM_8814B)
+#define BITS_P0HI10Q_DESC_NUM_8814B \
+ (BIT_MASK_P0HI10Q_DESC_NUM_8814B << BIT_SHIFT_P0HI10Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI10Q_DESC_NUM_8814B(x) \
+ ((x) & (~BITS_P0HI10Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI10Q_DESC_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI10Q_DESC_NUM_8814B) & \
+ BIT_MASK_P0HI10Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI10Q_DESC_NUM_8814B(x, v) \
+ (BIT_CLEAR_P0HI10Q_DESC_NUM_8814B(x) | BIT_P0HI10Q_DESC_NUM_8814B(v))
+
+/* 2 REG_P0HI12Q_HI13Q_TXBD_NUM_8814B */
+#define BIT_P0HI13Q_FLAG_8814B BIT(30)
+
+#define BIT_SHIFT_P0HI13Q_DESC_MODE_8814B 28
+#define BIT_MASK_P0HI13Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI13Q_DESC_MODE_8814B(x) \
+ (((x) & BIT_MASK_P0HI13Q_DESC_MODE_8814B) \
+ << BIT_SHIFT_P0HI13Q_DESC_MODE_8814B)
+#define BITS_P0HI13Q_DESC_MODE_8814B \
+ (BIT_MASK_P0HI13Q_DESC_MODE_8814B << BIT_SHIFT_P0HI13Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI13Q_DESC_MODE_8814B(x) \
+ ((x) & (~BITS_P0HI13Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI13Q_DESC_MODE_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI13Q_DESC_MODE_8814B) & \
+ BIT_MASK_P0HI13Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI13Q_DESC_MODE_8814B(x, v) \
+ (BIT_CLEAR_P0HI13Q_DESC_MODE_8814B(x) | BIT_P0HI13Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI13Q_DESC_NUM_8814B 16
+#define BIT_MASK_P0HI13Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI13Q_DESC_NUM_8814B(x) \
+ (((x) & BIT_MASK_P0HI13Q_DESC_NUM_8814B) \
+ << BIT_SHIFT_P0HI13Q_DESC_NUM_8814B)
+#define BITS_P0HI13Q_DESC_NUM_8814B \
+ (BIT_MASK_P0HI13Q_DESC_NUM_8814B << BIT_SHIFT_P0HI13Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI13Q_DESC_NUM_8814B(x) \
+ ((x) & (~BITS_P0HI13Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI13Q_DESC_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI13Q_DESC_NUM_8814B) & \
+ BIT_MASK_P0HI13Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI13Q_DESC_NUM_8814B(x, v) \
+ (BIT_CLEAR_P0HI13Q_DESC_NUM_8814B(x) | BIT_P0HI13Q_DESC_NUM_8814B(v))
+
+#define BIT_P0HI12Q_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_P0HI12Q_DESC_MODE_8814B 12
+#define BIT_MASK_P0HI12Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI12Q_DESC_MODE_8814B(x) \
+ (((x) & BIT_MASK_P0HI12Q_DESC_MODE_8814B) \
+ << BIT_SHIFT_P0HI12Q_DESC_MODE_8814B)
+#define BITS_P0HI12Q_DESC_MODE_8814B \
+ (BIT_MASK_P0HI12Q_DESC_MODE_8814B << BIT_SHIFT_P0HI12Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI12Q_DESC_MODE_8814B(x) \
+ ((x) & (~BITS_P0HI12Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI12Q_DESC_MODE_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI12Q_DESC_MODE_8814B) & \
+ BIT_MASK_P0HI12Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI12Q_DESC_MODE_8814B(x, v) \
+ (BIT_CLEAR_P0HI12Q_DESC_MODE_8814B(x) | BIT_P0HI12Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI12Q_DESC_NUM_8814B 0
+#define BIT_MASK_P0HI12Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI12Q_DESC_NUM_8814B(x) \
+ (((x) & BIT_MASK_P0HI12Q_DESC_NUM_8814B) \
+ << BIT_SHIFT_P0HI12Q_DESC_NUM_8814B)
+#define BITS_P0HI12Q_DESC_NUM_8814B \
+ (BIT_MASK_P0HI12Q_DESC_NUM_8814B << BIT_SHIFT_P0HI12Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI12Q_DESC_NUM_8814B(x) \
+ ((x) & (~BITS_P0HI12Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI12Q_DESC_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI12Q_DESC_NUM_8814B) & \
+ BIT_MASK_P0HI12Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI12Q_DESC_NUM_8814B(x, v) \
+ (BIT_CLEAR_P0HI12Q_DESC_NUM_8814B(x) | BIT_P0HI12Q_DESC_NUM_8814B(v))
+
+/* 2 REG_P0HI14Q_HI15Q_TXBD_NUM_8814B */
+#define BIT_P0HI15Q_FLAG_8814B BIT(30)
+
+#define BIT_SHIFT_P0HI15Q_DESC_MODE_8814B 28
+#define BIT_MASK_P0HI15Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI15Q_DESC_MODE_8814B(x) \
+ (((x) & BIT_MASK_P0HI15Q_DESC_MODE_8814B) \
+ << BIT_SHIFT_P0HI15Q_DESC_MODE_8814B)
+#define BITS_P0HI15Q_DESC_MODE_8814B \
+ (BIT_MASK_P0HI15Q_DESC_MODE_8814B << BIT_SHIFT_P0HI15Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI15Q_DESC_MODE_8814B(x) \
+ ((x) & (~BITS_P0HI15Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI15Q_DESC_MODE_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI15Q_DESC_MODE_8814B) & \
+ BIT_MASK_P0HI15Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI15Q_DESC_MODE_8814B(x, v) \
+ (BIT_CLEAR_P0HI15Q_DESC_MODE_8814B(x) | BIT_P0HI15Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI15Q_DESC_NUM_8814B 16
+#define BIT_MASK_P0HI15Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI15Q_DESC_NUM_8814B(x) \
+ (((x) & BIT_MASK_P0HI15Q_DESC_NUM_8814B) \
+ << BIT_SHIFT_P0HI15Q_DESC_NUM_8814B)
+#define BITS_P0HI15Q_DESC_NUM_8814B \
+ (BIT_MASK_P0HI15Q_DESC_NUM_8814B << BIT_SHIFT_P0HI15Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI15Q_DESC_NUM_8814B(x) \
+ ((x) & (~BITS_P0HI15Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI15Q_DESC_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI15Q_DESC_NUM_8814B) & \
+ BIT_MASK_P0HI15Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI15Q_DESC_NUM_8814B(x, v) \
+ (BIT_CLEAR_P0HI15Q_DESC_NUM_8814B(x) | BIT_P0HI15Q_DESC_NUM_8814B(v))
+
+#define BIT_P0HI14Q_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_P0HI14Q_DESC_MODE_8814B 12
+#define BIT_MASK_P0HI14Q_DESC_MODE_8814B 0x3
+#define BIT_P0HI14Q_DESC_MODE_8814B(x) \
+ (((x) & BIT_MASK_P0HI14Q_DESC_MODE_8814B) \
+ << BIT_SHIFT_P0HI14Q_DESC_MODE_8814B)
+#define BITS_P0HI14Q_DESC_MODE_8814B \
+ (BIT_MASK_P0HI14Q_DESC_MODE_8814B << BIT_SHIFT_P0HI14Q_DESC_MODE_8814B)
+#define BIT_CLEAR_P0HI14Q_DESC_MODE_8814B(x) \
+ ((x) & (~BITS_P0HI14Q_DESC_MODE_8814B))
+#define BIT_GET_P0HI14Q_DESC_MODE_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI14Q_DESC_MODE_8814B) & \
+ BIT_MASK_P0HI14Q_DESC_MODE_8814B)
+#define BIT_SET_P0HI14Q_DESC_MODE_8814B(x, v) \
+ (BIT_CLEAR_P0HI14Q_DESC_MODE_8814B(x) | BIT_P0HI14Q_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_P0HI14Q_DESC_NUM_8814B 0
+#define BIT_MASK_P0HI14Q_DESC_NUM_8814B 0xfff
+#define BIT_P0HI14Q_DESC_NUM_8814B(x) \
+ (((x) & BIT_MASK_P0HI14Q_DESC_NUM_8814B) \
+ << BIT_SHIFT_P0HI14Q_DESC_NUM_8814B)
+#define BITS_P0HI14Q_DESC_NUM_8814B \
+ (BIT_MASK_P0HI14Q_DESC_NUM_8814B << BIT_SHIFT_P0HI14Q_DESC_NUM_8814B)
+#define BIT_CLEAR_P0HI14Q_DESC_NUM_8814B(x) \
+ ((x) & (~BITS_P0HI14Q_DESC_NUM_8814B))
+#define BIT_GET_P0HI14Q_DESC_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_P0HI14Q_DESC_NUM_8814B) & \
+ BIT_MASK_P0HI14Q_DESC_NUM_8814B)
+#define BIT_SET_P0HI14Q_DESC_NUM_8814B(x, v) \
+ (BIT_CLEAR_P0HI14Q_DESC_NUM_8814B(x) | BIT_P0HI14Q_DESC_NUM_8814B(v))
+
+/* 2 REG_ACH6_ACH7_TXBD_NUM_8814B */
+#define BIT_PCIE_ACH7_FLAG_8814B BIT(30)
+
+#define BIT_SHIFT_ACH7_DESC_MODE_8814B 28
+#define BIT_MASK_ACH7_DESC_MODE_8814B 0x3
+#define BIT_ACH7_DESC_MODE_8814B(x) \
+ (((x) & BIT_MASK_ACH7_DESC_MODE_8814B) \
+ << BIT_SHIFT_ACH7_DESC_MODE_8814B)
+#define BITS_ACH7_DESC_MODE_8814B \
+ (BIT_MASK_ACH7_DESC_MODE_8814B << BIT_SHIFT_ACH7_DESC_MODE_8814B)
+#define BIT_CLEAR_ACH7_DESC_MODE_8814B(x) ((x) & (~BITS_ACH7_DESC_MODE_8814B))
+#define BIT_GET_ACH7_DESC_MODE_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH7_DESC_MODE_8814B) & \
+ BIT_MASK_ACH7_DESC_MODE_8814B)
+#define BIT_SET_ACH7_DESC_MODE_8814B(x, v) \
+ (BIT_CLEAR_ACH7_DESC_MODE_8814B(x) | BIT_ACH7_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_ACH7_DESC_NUM_8814B 16
+#define BIT_MASK_ACH7_DESC_NUM_8814B 0xfff
+#define BIT_ACH7_DESC_NUM_8814B(x) \
+ (((x) & BIT_MASK_ACH7_DESC_NUM_8814B) << BIT_SHIFT_ACH7_DESC_NUM_8814B)
+#define BITS_ACH7_DESC_NUM_8814B \
+ (BIT_MASK_ACH7_DESC_NUM_8814B << BIT_SHIFT_ACH7_DESC_NUM_8814B)
+#define BIT_CLEAR_ACH7_DESC_NUM_8814B(x) ((x) & (~BITS_ACH7_DESC_NUM_8814B))
+#define BIT_GET_ACH7_DESC_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH7_DESC_NUM_8814B) & BIT_MASK_ACH7_DESC_NUM_8814B)
+#define BIT_SET_ACH7_DESC_NUM_8814B(x, v) \
+ (BIT_CLEAR_ACH7_DESC_NUM_8814B(x) | BIT_ACH7_DESC_NUM_8814B(v))
+
+#define BIT_PCIE_ACH6_FLAG_8814B BIT(14)
+
+#define BIT_SHIFT_ACH6_DESC_MODE_8814B 12
+#define BIT_MASK_ACH6_DESC_MODE_8814B 0x3
+#define BIT_ACH6_DESC_MODE_8814B(x) \
+ (((x) & BIT_MASK_ACH6_DESC_MODE_8814B) \
+ << BIT_SHIFT_ACH6_DESC_MODE_8814B)
+#define BITS_ACH6_DESC_MODE_8814B \
+ (BIT_MASK_ACH6_DESC_MODE_8814B << BIT_SHIFT_ACH6_DESC_MODE_8814B)
+#define BIT_CLEAR_ACH6_DESC_MODE_8814B(x) ((x) & (~BITS_ACH6_DESC_MODE_8814B))
+#define BIT_GET_ACH6_DESC_MODE_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH6_DESC_MODE_8814B) & \
+ BIT_MASK_ACH6_DESC_MODE_8814B)
+#define BIT_SET_ACH6_DESC_MODE_8814B(x, v) \
+ (BIT_CLEAR_ACH6_DESC_MODE_8814B(x) | BIT_ACH6_DESC_MODE_8814B(v))
+
+#define BIT_SHIFT_ACH6_DESC_NUM_8814B 0
+#define BIT_MASK_ACH6_DESC_NUM_8814B 0xfff
+#define BIT_ACH6_DESC_NUM_8814B(x) \
+ (((x) & BIT_MASK_ACH6_DESC_NUM_8814B) << BIT_SHIFT_ACH6_DESC_NUM_8814B)
+#define BITS_ACH6_DESC_NUM_8814B \
+ (BIT_MASK_ACH6_DESC_NUM_8814B << BIT_SHIFT_ACH6_DESC_NUM_8814B)
+#define BIT_CLEAR_ACH6_DESC_NUM_8814B(x) ((x) & (~BITS_ACH6_DESC_NUM_8814B))
+#define BIT_GET_ACH6_DESC_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH6_DESC_NUM_8814B) & BIT_MASK_ACH6_DESC_NUM_8814B)
+#define BIT_SET_ACH6_DESC_NUM_8814B(x, v) \
+ (BIT_CLEAR_ACH6_DESC_NUM_8814B(x) | BIT_ACH6_DESC_NUM_8814B(v))
+
+/* 2 REG_ACH4_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_ACH4_HW_IDX_8814B 16
+#define BIT_MASK_ACH4_HW_IDX_8814B 0xfff
+#define BIT_ACH4_HW_IDX_8814B(x) \
+ (((x) & BIT_MASK_ACH4_HW_IDX_8814B) << BIT_SHIFT_ACH4_HW_IDX_8814B)
+#define BITS_ACH4_HW_IDX_8814B \
+ (BIT_MASK_ACH4_HW_IDX_8814B << BIT_SHIFT_ACH4_HW_IDX_8814B)
+#define BIT_CLEAR_ACH4_HW_IDX_8814B(x) ((x) & (~BITS_ACH4_HW_IDX_8814B))
+#define BIT_GET_ACH4_HW_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH4_HW_IDX_8814B) & BIT_MASK_ACH4_HW_IDX_8814B)
+#define BIT_SET_ACH4_HW_IDX_8814B(x, v) \
+ (BIT_CLEAR_ACH4_HW_IDX_8814B(x) | BIT_ACH4_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_ACH4_HOST_IDX_8814B 0
+#define BIT_MASK_ACH4_HOST_IDX_8814B 0xfff
+#define BIT_ACH4_HOST_IDX_8814B(x) \
+ (((x) & BIT_MASK_ACH4_HOST_IDX_8814B) << BIT_SHIFT_ACH4_HOST_IDX_8814B)
+#define BITS_ACH4_HOST_IDX_8814B \
+ (BIT_MASK_ACH4_HOST_IDX_8814B << BIT_SHIFT_ACH4_HOST_IDX_8814B)
+#define BIT_CLEAR_ACH4_HOST_IDX_8814B(x) ((x) & (~BITS_ACH4_HOST_IDX_8814B))
+#define BIT_GET_ACH4_HOST_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH4_HOST_IDX_8814B) & BIT_MASK_ACH4_HOST_IDX_8814B)
+#define BIT_SET_ACH4_HOST_IDX_8814B(x, v) \
+ (BIT_CLEAR_ACH4_HOST_IDX_8814B(x) | BIT_ACH4_HOST_IDX_8814B(v))
+
+/* 2 REG_ACH5_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_ACH5_HW_IDX_8814B 16
+#define BIT_MASK_ACH5_HW_IDX_8814B 0xfff
+#define BIT_ACH5_HW_IDX_8814B(x) \
+ (((x) & BIT_MASK_ACH5_HW_IDX_8814B) << BIT_SHIFT_ACH5_HW_IDX_8814B)
+#define BITS_ACH5_HW_IDX_8814B \
+ (BIT_MASK_ACH5_HW_IDX_8814B << BIT_SHIFT_ACH5_HW_IDX_8814B)
+#define BIT_CLEAR_ACH5_HW_IDX_8814B(x) ((x) & (~BITS_ACH5_HW_IDX_8814B))
+#define BIT_GET_ACH5_HW_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH5_HW_IDX_8814B) & BIT_MASK_ACH5_HW_IDX_8814B)
+#define BIT_SET_ACH5_HW_IDX_8814B(x, v) \
+ (BIT_CLEAR_ACH5_HW_IDX_8814B(x) | BIT_ACH5_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_ACH5_HOST_IDX_8814B 0
+#define BIT_MASK_ACH5_HOST_IDX_8814B 0xfff
+#define BIT_ACH5_HOST_IDX_8814B(x) \
+ (((x) & BIT_MASK_ACH5_HOST_IDX_8814B) << BIT_SHIFT_ACH5_HOST_IDX_8814B)
+#define BITS_ACH5_HOST_IDX_8814B \
+ (BIT_MASK_ACH5_HOST_IDX_8814B << BIT_SHIFT_ACH5_HOST_IDX_8814B)
+#define BIT_CLEAR_ACH5_HOST_IDX_8814B(x) ((x) & (~BITS_ACH5_HOST_IDX_8814B))
+#define BIT_GET_ACH5_HOST_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH5_HOST_IDX_8814B) & BIT_MASK_ACH5_HOST_IDX_8814B)
+#define BIT_SET_ACH5_HOST_IDX_8814B(x, v) \
+ (BIT_CLEAR_ACH5_HOST_IDX_8814B(x) | BIT_ACH5_HOST_IDX_8814B(v))
+
+/* 2 REG_ACH6_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_ACH6_HW_IDX_8814B 16
+#define BIT_MASK_ACH6_HW_IDX_8814B 0xfff
+#define BIT_ACH6_HW_IDX_8814B(x) \
+ (((x) & BIT_MASK_ACH6_HW_IDX_8814B) << BIT_SHIFT_ACH6_HW_IDX_8814B)
+#define BITS_ACH6_HW_IDX_8814B \
+ (BIT_MASK_ACH6_HW_IDX_8814B << BIT_SHIFT_ACH6_HW_IDX_8814B)
+#define BIT_CLEAR_ACH6_HW_IDX_8814B(x) ((x) & (~BITS_ACH6_HW_IDX_8814B))
+#define BIT_GET_ACH6_HW_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH6_HW_IDX_8814B) & BIT_MASK_ACH6_HW_IDX_8814B)
+#define BIT_SET_ACH6_HW_IDX_8814B(x, v) \
+ (BIT_CLEAR_ACH6_HW_IDX_8814B(x) | BIT_ACH6_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_ACH6_HOST_IDX_8814B 0
+#define BIT_MASK_ACH6_HOST_IDX_8814B 0xfff
+#define BIT_ACH6_HOST_IDX_8814B(x) \
+ (((x) & BIT_MASK_ACH6_HOST_IDX_8814B) << BIT_SHIFT_ACH6_HOST_IDX_8814B)
+#define BITS_ACH6_HOST_IDX_8814B \
+ (BIT_MASK_ACH6_HOST_IDX_8814B << BIT_SHIFT_ACH6_HOST_IDX_8814B)
+#define BIT_CLEAR_ACH6_HOST_IDX_8814B(x) ((x) & (~BITS_ACH6_HOST_IDX_8814B))
+#define BIT_GET_ACH6_HOST_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH6_HOST_IDX_8814B) & BIT_MASK_ACH6_HOST_IDX_8814B)
+#define BIT_SET_ACH6_HOST_IDX_8814B(x, v) \
+ (BIT_CLEAR_ACH6_HOST_IDX_8814B(x) | BIT_ACH6_HOST_IDX_8814B(v))
+
+/* 2 REG_ACH7_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_ACH7_HW_IDX_8814B 16
+#define BIT_MASK_ACH7_HW_IDX_8814B 0xfff
+#define BIT_ACH7_HW_IDX_8814B(x) \
+ (((x) & BIT_MASK_ACH7_HW_IDX_8814B) << BIT_SHIFT_ACH7_HW_IDX_8814B)
+#define BITS_ACH7_HW_IDX_8814B \
+ (BIT_MASK_ACH7_HW_IDX_8814B << BIT_SHIFT_ACH7_HW_IDX_8814B)
+#define BIT_CLEAR_ACH7_HW_IDX_8814B(x) ((x) & (~BITS_ACH7_HW_IDX_8814B))
+#define BIT_GET_ACH7_HW_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH7_HW_IDX_8814B) & BIT_MASK_ACH7_HW_IDX_8814B)
+#define BIT_SET_ACH7_HW_IDX_8814B(x, v) \
+ (BIT_CLEAR_ACH7_HW_IDX_8814B(x) | BIT_ACH7_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_ACH7_HOST_IDX_8814B 0
+#define BIT_MASK_ACH7_HOST_IDX_8814B 0xfff
+#define BIT_ACH7_HOST_IDX_8814B(x) \
+ (((x) & BIT_MASK_ACH7_HOST_IDX_8814B) << BIT_SHIFT_ACH7_HOST_IDX_8814B)
+#define BITS_ACH7_HOST_IDX_8814B \
+ (BIT_MASK_ACH7_HOST_IDX_8814B << BIT_SHIFT_ACH7_HOST_IDX_8814B)
+#define BIT_CLEAR_ACH7_HOST_IDX_8814B(x) ((x) & (~BITS_ACH7_HOST_IDX_8814B))
+#define BIT_GET_ACH7_HOST_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH7_HOST_IDX_8814B) & BIT_MASK_ACH7_HOST_IDX_8814B)
+#define BIT_SET_ACH7_HOST_IDX_8814B(x, v) \
+ (BIT_CLEAR_ACH7_HOST_IDX_8814B(x) | BIT_ACH7_HOST_IDX_8814B(v))
+
+/* 2 REG_ACH8_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_ACH8_HW_IDX_8814B 16
+#define BIT_MASK_ACH8_HW_IDX_8814B 0xfff
+#define BIT_ACH8_HW_IDX_8814B(x) \
+ (((x) & BIT_MASK_ACH8_HW_IDX_8814B) << BIT_SHIFT_ACH8_HW_IDX_8814B)
+#define BITS_ACH8_HW_IDX_8814B \
+ (BIT_MASK_ACH8_HW_IDX_8814B << BIT_SHIFT_ACH8_HW_IDX_8814B)
+#define BIT_CLEAR_ACH8_HW_IDX_8814B(x) ((x) & (~BITS_ACH8_HW_IDX_8814B))
+#define BIT_GET_ACH8_HW_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH8_HW_IDX_8814B) & BIT_MASK_ACH8_HW_IDX_8814B)
+#define BIT_SET_ACH8_HW_IDX_8814B(x, v) \
+ (BIT_CLEAR_ACH8_HW_IDX_8814B(x) | BIT_ACH8_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_ACH8_HOST_IDX_8814B 0
+#define BIT_MASK_ACH8_HOST_IDX_8814B 0xfff
+#define BIT_ACH8_HOST_IDX_8814B(x) \
+ (((x) & BIT_MASK_ACH8_HOST_IDX_8814B) << BIT_SHIFT_ACH8_HOST_IDX_8814B)
+#define BITS_ACH8_HOST_IDX_8814B \
+ (BIT_MASK_ACH8_HOST_IDX_8814B << BIT_SHIFT_ACH8_HOST_IDX_8814B)
+#define BIT_CLEAR_ACH8_HOST_IDX_8814B(x) ((x) & (~BITS_ACH8_HOST_IDX_8814B))
+#define BIT_GET_ACH8_HOST_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH8_HOST_IDX_8814B) & BIT_MASK_ACH8_HOST_IDX_8814B)
+#define BIT_SET_ACH8_HOST_IDX_8814B(x, v) \
+ (BIT_CLEAR_ACH8_HOST_IDX_8814B(x) | BIT_ACH8_HOST_IDX_8814B(v))
+
+/* 2 REG_ACH9_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_ACH9_HW_IDX_8814B 16
+#define BIT_MASK_ACH9_HW_IDX_8814B 0xfff
+#define BIT_ACH9_HW_IDX_8814B(x) \
+ (((x) & BIT_MASK_ACH9_HW_IDX_8814B) << BIT_SHIFT_ACH9_HW_IDX_8814B)
+#define BITS_ACH9_HW_IDX_8814B \
+ (BIT_MASK_ACH9_HW_IDX_8814B << BIT_SHIFT_ACH9_HW_IDX_8814B)
+#define BIT_CLEAR_ACH9_HW_IDX_8814B(x) ((x) & (~BITS_ACH9_HW_IDX_8814B))
+#define BIT_GET_ACH9_HW_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH9_HW_IDX_8814B) & BIT_MASK_ACH9_HW_IDX_8814B)
+#define BIT_SET_ACH9_HW_IDX_8814B(x, v) \
+ (BIT_CLEAR_ACH9_HW_IDX_8814B(x) | BIT_ACH9_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_ACH9_HOST_IDX_8814B 0
+#define BIT_MASK_ACH9_HOST_IDX_8814B 0xfff
+#define BIT_ACH9_HOST_IDX_8814B(x) \
+ (((x) & BIT_MASK_ACH9_HOST_IDX_8814B) << BIT_SHIFT_ACH9_HOST_IDX_8814B)
+#define BITS_ACH9_HOST_IDX_8814B \
+ (BIT_MASK_ACH9_HOST_IDX_8814B << BIT_SHIFT_ACH9_HOST_IDX_8814B)
+#define BIT_CLEAR_ACH9_HOST_IDX_8814B(x) ((x) & (~BITS_ACH9_HOST_IDX_8814B))
+#define BIT_GET_ACH9_HOST_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH9_HOST_IDX_8814B) & BIT_MASK_ACH9_HOST_IDX_8814B)
+#define BIT_SET_ACH9_HOST_IDX_8814B(x, v) \
+ (BIT_CLEAR_ACH9_HOST_IDX_8814B(x) | BIT_ACH9_HOST_IDX_8814B(v))
+
+/* 2 REG_ACH10_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_ACH10_HW_IDX_8814B 16
+#define BIT_MASK_ACH10_HW_IDX_8814B 0xfff
+#define BIT_ACH10_HW_IDX_8814B(x) \
+ (((x) & BIT_MASK_ACH10_HW_IDX_8814B) << BIT_SHIFT_ACH10_HW_IDX_8814B)
+#define BITS_ACH10_HW_IDX_8814B \
+ (BIT_MASK_ACH10_HW_IDX_8814B << BIT_SHIFT_ACH10_HW_IDX_8814B)
+#define BIT_CLEAR_ACH10_HW_IDX_8814B(x) ((x) & (~BITS_ACH10_HW_IDX_8814B))
+#define BIT_GET_ACH10_HW_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH10_HW_IDX_8814B) & BIT_MASK_ACH10_HW_IDX_8814B)
+#define BIT_SET_ACH10_HW_IDX_8814B(x, v) \
+ (BIT_CLEAR_ACH10_HW_IDX_8814B(x) | BIT_ACH10_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_ACH10_HOST_IDX_8814B 0
+#define BIT_MASK_ACH10_HOST_IDX_8814B 0xfff
+#define BIT_ACH10_HOST_IDX_8814B(x) \
+ (((x) & BIT_MASK_ACH10_HOST_IDX_8814B) \
+ << BIT_SHIFT_ACH10_HOST_IDX_8814B)
+#define BITS_ACH10_HOST_IDX_8814B \
+ (BIT_MASK_ACH10_HOST_IDX_8814B << BIT_SHIFT_ACH10_HOST_IDX_8814B)
+#define BIT_CLEAR_ACH10_HOST_IDX_8814B(x) ((x) & (~BITS_ACH10_HOST_IDX_8814B))
+#define BIT_GET_ACH10_HOST_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH10_HOST_IDX_8814B) & \
+ BIT_MASK_ACH10_HOST_IDX_8814B)
+#define BIT_SET_ACH10_HOST_IDX_8814B(x, v) \
+ (BIT_CLEAR_ACH10_HOST_IDX_8814B(x) | BIT_ACH10_HOST_IDX_8814B(v))
+
+/* 2 REG_ACH11_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_ACH11_HW_IDX_8814B 16
+#define BIT_MASK_ACH11_HW_IDX_8814B 0xfff
+#define BIT_ACH11_HW_IDX_8814B(x) \
+ (((x) & BIT_MASK_ACH11_HW_IDX_8814B) << BIT_SHIFT_ACH11_HW_IDX_8814B)
+#define BITS_ACH11_HW_IDX_8814B \
+ (BIT_MASK_ACH11_HW_IDX_8814B << BIT_SHIFT_ACH11_HW_IDX_8814B)
+#define BIT_CLEAR_ACH11_HW_IDX_8814B(x) ((x) & (~BITS_ACH11_HW_IDX_8814B))
+#define BIT_GET_ACH11_HW_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH11_HW_IDX_8814B) & BIT_MASK_ACH11_HW_IDX_8814B)
+#define BIT_SET_ACH11_HW_IDX_8814B(x, v) \
+ (BIT_CLEAR_ACH11_HW_IDX_8814B(x) | BIT_ACH11_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_ACH11_HOST_IDX_8814B 0
+#define BIT_MASK_ACH11_HOST_IDX_8814B 0xfff
+#define BIT_ACH11_HOST_IDX_8814B(x) \
+ (((x) & BIT_MASK_ACH11_HOST_IDX_8814B) \
+ << BIT_SHIFT_ACH11_HOST_IDX_8814B)
+#define BITS_ACH11_HOST_IDX_8814B \
+ (BIT_MASK_ACH11_HOST_IDX_8814B << BIT_SHIFT_ACH11_HOST_IDX_8814B)
+#define BIT_CLEAR_ACH11_HOST_IDX_8814B(x) ((x) & (~BITS_ACH11_HOST_IDX_8814B))
+#define BIT_GET_ACH11_HOST_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH11_HOST_IDX_8814B) & \
+ BIT_MASK_ACH11_HOST_IDX_8814B)
+#define BIT_SET_ACH11_HOST_IDX_8814B(x, v) \
+ (BIT_CLEAR_ACH11_HOST_IDX_8814B(x) | BIT_ACH11_HOST_IDX_8814B(v))
+
+/* 2 REG_ACH12_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_ACH12_HW_IDX_8814B 16
+#define BIT_MASK_ACH12_HW_IDX_8814B 0xfff
+#define BIT_ACH12_HW_IDX_8814B(x) \
+ (((x) & BIT_MASK_ACH12_HW_IDX_8814B) << BIT_SHIFT_ACH12_HW_IDX_8814B)
+#define BITS_ACH12_HW_IDX_8814B \
+ (BIT_MASK_ACH12_HW_IDX_8814B << BIT_SHIFT_ACH12_HW_IDX_8814B)
+#define BIT_CLEAR_ACH12_HW_IDX_8814B(x) ((x) & (~BITS_ACH12_HW_IDX_8814B))
+#define BIT_GET_ACH12_HW_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH12_HW_IDX_8814B) & BIT_MASK_ACH12_HW_IDX_8814B)
+#define BIT_SET_ACH12_HW_IDX_8814B(x, v) \
+ (BIT_CLEAR_ACH12_HW_IDX_8814B(x) | BIT_ACH12_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_ACH12_HOST_IDX_8814B 0
+#define BIT_MASK_ACH12_HOST_IDX_8814B 0xfff
+#define BIT_ACH12_HOST_IDX_8814B(x) \
+ (((x) & BIT_MASK_ACH12_HOST_IDX_8814B) \
+ << BIT_SHIFT_ACH12_HOST_IDX_8814B)
+#define BITS_ACH12_HOST_IDX_8814B \
+ (BIT_MASK_ACH12_HOST_IDX_8814B << BIT_SHIFT_ACH12_HOST_IDX_8814B)
+#define BIT_CLEAR_ACH12_HOST_IDX_8814B(x) ((x) & (~BITS_ACH12_HOST_IDX_8814B))
+#define BIT_GET_ACH12_HOST_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH12_HOST_IDX_8814B) & \
+ BIT_MASK_ACH12_HOST_IDX_8814B)
+#define BIT_SET_ACH12_HOST_IDX_8814B(x, v) \
+ (BIT_CLEAR_ACH12_HOST_IDX_8814B(x) | BIT_ACH12_HOST_IDX_8814B(v))
+
+/* 2 REG_ACH13_TXBD_IDX_8814B */
+
+#define BIT_SHIFT_ACH13_HW_IDX_8814B 16
+#define BIT_MASK_ACH13_HW_IDX_8814B 0xfff
+#define BIT_ACH13_HW_IDX_8814B(x) \
+ (((x) & BIT_MASK_ACH13_HW_IDX_8814B) << BIT_SHIFT_ACH13_HW_IDX_8814B)
+#define BITS_ACH13_HW_IDX_8814B \
+ (BIT_MASK_ACH13_HW_IDX_8814B << BIT_SHIFT_ACH13_HW_IDX_8814B)
+#define BIT_CLEAR_ACH13_HW_IDX_8814B(x) ((x) & (~BITS_ACH13_HW_IDX_8814B))
+#define BIT_GET_ACH13_HW_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH13_HW_IDX_8814B) & BIT_MASK_ACH13_HW_IDX_8814B)
+#define BIT_SET_ACH13_HW_IDX_8814B(x, v) \
+ (BIT_CLEAR_ACH13_HW_IDX_8814B(x) | BIT_ACH13_HW_IDX_8814B(v))
+
+#define BIT_SHIFT_ACH13_HOST_IDX_8814B 0
+#define BIT_MASK_ACH13_HOST_IDX_8814B 0xfff
+#define BIT_ACH13_HOST_IDX_8814B(x) \
+ (((x) & BIT_MASK_ACH13_HOST_IDX_8814B) \
+ << BIT_SHIFT_ACH13_HOST_IDX_8814B)
+#define BITS_ACH13_HOST_IDX_8814B \
+ (BIT_MASK_ACH13_HOST_IDX_8814B << BIT_SHIFT_ACH13_HOST_IDX_8814B)
+#define BIT_CLEAR_ACH13_HOST_IDX_8814B(x) ((x) & (~BITS_ACH13_HOST_IDX_8814B))
+#define BIT_GET_ACH13_HOST_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_ACH13_HOST_IDX_8814B) & \
+ BIT_MASK_ACH13_HOST_IDX_8814B)
+#define BIT_SET_ACH13_HOST_IDX_8814B(x, v) \
+ (BIT_CLEAR_ACH13_HOST_IDX_8814B(x) | BIT_ACH13_HOST_IDX_8814B(v))
+
+/* 2 REG_AC_CHANNEL0_WEIGHT_8814B */
+
+#define BIT_SHIFT_AC_CHANNEL0_WEIGHT_8814B 0
+#define BIT_MASK_AC_CHANNEL0_WEIGHT_8814B 0xff
+#define BIT_AC_CHANNEL0_WEIGHT_8814B(x) \
+ (((x) & BIT_MASK_AC_CHANNEL0_WEIGHT_8814B) \
+ << BIT_SHIFT_AC_CHANNEL0_WEIGHT_8814B)
+#define BITS_AC_CHANNEL0_WEIGHT_8814B \
+ (BIT_MASK_AC_CHANNEL0_WEIGHT_8814B \
+ << BIT_SHIFT_AC_CHANNEL0_WEIGHT_8814B)
+#define BIT_CLEAR_AC_CHANNEL0_WEIGHT_8814B(x) \
+ ((x) & (~BITS_AC_CHANNEL0_WEIGHT_8814B))
+#define BIT_GET_AC_CHANNEL0_WEIGHT_8814B(x) \
+ (((x) >> BIT_SHIFT_AC_CHANNEL0_WEIGHT_8814B) & \
+ BIT_MASK_AC_CHANNEL0_WEIGHT_8814B)
+#define BIT_SET_AC_CHANNEL0_WEIGHT_8814B(x, v) \
+ (BIT_CLEAR_AC_CHANNEL0_WEIGHT_8814B(x) | \
+ BIT_AC_CHANNEL0_WEIGHT_8814B(v))
+
+/* 2 REG_AC_CHANNEL1_WEIGHT_8814B */
+
+#define BIT_SHIFT_AC_CHANNEL1_WEIGHT_8814B 0
+#define BIT_MASK_AC_CHANNEL1_WEIGHT_8814B 0xff
+#define BIT_AC_CHANNEL1_WEIGHT_8814B(x) \
+ (((x) & BIT_MASK_AC_CHANNEL1_WEIGHT_8814B) \
+ << BIT_SHIFT_AC_CHANNEL1_WEIGHT_8814B)
+#define BITS_AC_CHANNEL1_WEIGHT_8814B \
+ (BIT_MASK_AC_CHANNEL1_WEIGHT_8814B \
+ << BIT_SHIFT_AC_CHANNEL1_WEIGHT_8814B)
+#define BIT_CLEAR_AC_CHANNEL1_WEIGHT_8814B(x) \
+ ((x) & (~BITS_AC_CHANNEL1_WEIGHT_8814B))
+#define BIT_GET_AC_CHANNEL1_WEIGHT_8814B(x) \
+ (((x) >> BIT_SHIFT_AC_CHANNEL1_WEIGHT_8814B) & \
+ BIT_MASK_AC_CHANNEL1_WEIGHT_8814B)
+#define BIT_SET_AC_CHANNEL1_WEIGHT_8814B(x, v) \
+ (BIT_CLEAR_AC_CHANNEL1_WEIGHT_8814B(x) | \
+ BIT_AC_CHANNEL1_WEIGHT_8814B(v))
+
+/* 2 REG_AC_CHANNEL2_WEIGHT_8814B */
+
+#define BIT_SHIFT_AC_CHANNEL2_WEIGHT_8814B 0
+#define BIT_MASK_AC_CHANNEL2_WEIGHT_8814B 0xff
+#define BIT_AC_CHANNEL2_WEIGHT_8814B(x) \
+ (((x) & BIT_MASK_AC_CHANNEL2_WEIGHT_8814B) \
+ << BIT_SHIFT_AC_CHANNEL2_WEIGHT_8814B)
+#define BITS_AC_CHANNEL2_WEIGHT_8814B \
+ (BIT_MASK_AC_CHANNEL2_WEIGHT_8814B \
+ << BIT_SHIFT_AC_CHANNEL2_WEIGHT_8814B)
+#define BIT_CLEAR_AC_CHANNEL2_WEIGHT_8814B(x) \
+ ((x) & (~BITS_AC_CHANNEL2_WEIGHT_8814B))
+#define BIT_GET_AC_CHANNEL2_WEIGHT_8814B(x) \
+ (((x) >> BIT_SHIFT_AC_CHANNEL2_WEIGHT_8814B) & \
+ BIT_MASK_AC_CHANNEL2_WEIGHT_8814B)
+#define BIT_SET_AC_CHANNEL2_WEIGHT_8814B(x, v) \
+ (BIT_CLEAR_AC_CHANNEL2_WEIGHT_8814B(x) | \
+ BIT_AC_CHANNEL2_WEIGHT_8814B(v))
+
+/* 2 REG_AC_CHANNEL3_WEIGHT_8814B */
+
+#define BIT_SHIFT_AC_CHANNEL3_WEIGHT_8814B 0
+#define BIT_MASK_AC_CHANNEL3_WEIGHT_8814B 0xff
+#define BIT_AC_CHANNEL3_WEIGHT_8814B(x) \
+ (((x) & BIT_MASK_AC_CHANNEL3_WEIGHT_8814B) \
+ << BIT_SHIFT_AC_CHANNEL3_WEIGHT_8814B)
+#define BITS_AC_CHANNEL3_WEIGHT_8814B \
+ (BIT_MASK_AC_CHANNEL3_WEIGHT_8814B \
+ << BIT_SHIFT_AC_CHANNEL3_WEIGHT_8814B)
+#define BIT_CLEAR_AC_CHANNEL3_WEIGHT_8814B(x) \
+ ((x) & (~BITS_AC_CHANNEL3_WEIGHT_8814B))
+#define BIT_GET_AC_CHANNEL3_WEIGHT_8814B(x) \
+ (((x) >> BIT_SHIFT_AC_CHANNEL3_WEIGHT_8814B) & \
+ BIT_MASK_AC_CHANNEL3_WEIGHT_8814B)
+#define BIT_SET_AC_CHANNEL3_WEIGHT_8814B(x, v) \
+ (BIT_CLEAR_AC_CHANNEL3_WEIGHT_8814B(x) | \
+ BIT_AC_CHANNEL3_WEIGHT_8814B(v))
+
+/* 2 REG_AC_CHANNEL4_WEIGHT_8814B */
+
+#define BIT_SHIFT_AC_CHANNEL4_WEIGHT_8814B 0
+#define BIT_MASK_AC_CHANNEL4_WEIGHT_8814B 0xff
+#define BIT_AC_CHANNEL4_WEIGHT_8814B(x) \
+ (((x) & BIT_MASK_AC_CHANNEL4_WEIGHT_8814B) \
+ << BIT_SHIFT_AC_CHANNEL4_WEIGHT_8814B)
+#define BITS_AC_CHANNEL4_WEIGHT_8814B \
+ (BIT_MASK_AC_CHANNEL4_WEIGHT_8814B \
+ << BIT_SHIFT_AC_CHANNEL4_WEIGHT_8814B)
+#define BIT_CLEAR_AC_CHANNEL4_WEIGHT_8814B(x) \
+ ((x) & (~BITS_AC_CHANNEL4_WEIGHT_8814B))
+#define BIT_GET_AC_CHANNEL4_WEIGHT_8814B(x) \
+ (((x) >> BIT_SHIFT_AC_CHANNEL4_WEIGHT_8814B) & \
+ BIT_MASK_AC_CHANNEL4_WEIGHT_8814B)
+#define BIT_SET_AC_CHANNEL4_WEIGHT_8814B(x, v) \
+ (BIT_CLEAR_AC_CHANNEL4_WEIGHT_8814B(x) | \
+ BIT_AC_CHANNEL4_WEIGHT_8814B(v))
+
+/* 2 REG_AC_CHANNEL5_WEIGHT_8814B */
+
+#define BIT_SHIFT_AC_CHANNEL5_WEIGHT_8814B 0
+#define BIT_MASK_AC_CHANNEL5_WEIGHT_8814B 0xff
+#define BIT_AC_CHANNEL5_WEIGHT_8814B(x) \
+ (((x) & BIT_MASK_AC_CHANNEL5_WEIGHT_8814B) \
+ << BIT_SHIFT_AC_CHANNEL5_WEIGHT_8814B)
+#define BITS_AC_CHANNEL5_WEIGHT_8814B \
+ (BIT_MASK_AC_CHANNEL5_WEIGHT_8814B \
+ << BIT_SHIFT_AC_CHANNEL5_WEIGHT_8814B)
+#define BIT_CLEAR_AC_CHANNEL5_WEIGHT_8814B(x) \
+ ((x) & (~BITS_AC_CHANNEL5_WEIGHT_8814B))
+#define BIT_GET_AC_CHANNEL5_WEIGHT_8814B(x) \
+ (((x) >> BIT_SHIFT_AC_CHANNEL5_WEIGHT_8814B) & \
+ BIT_MASK_AC_CHANNEL5_WEIGHT_8814B)
+#define BIT_SET_AC_CHANNEL5_WEIGHT_8814B(x, v) \
+ (BIT_CLEAR_AC_CHANNEL5_WEIGHT_8814B(x) | \
+ BIT_AC_CHANNEL5_WEIGHT_8814B(v))
+
+/* 2 REG_AC_CHANNEL6_WEIGHT_8814B */
+
+#define BIT_SHIFT_AC_CHANNEL6_WEIGHT_8814B 0
+#define BIT_MASK_AC_CHANNEL6_WEIGHT_8814B 0xff
+#define BIT_AC_CHANNEL6_WEIGHT_8814B(x) \
+ (((x) & BIT_MASK_AC_CHANNEL6_WEIGHT_8814B) \
+ << BIT_SHIFT_AC_CHANNEL6_WEIGHT_8814B)
+#define BITS_AC_CHANNEL6_WEIGHT_8814B \
+ (BIT_MASK_AC_CHANNEL6_WEIGHT_8814B \
+ << BIT_SHIFT_AC_CHANNEL6_WEIGHT_8814B)
+#define BIT_CLEAR_AC_CHANNEL6_WEIGHT_8814B(x) \
+ ((x) & (~BITS_AC_CHANNEL6_WEIGHT_8814B))
+#define BIT_GET_AC_CHANNEL6_WEIGHT_8814B(x) \
+ (((x) >> BIT_SHIFT_AC_CHANNEL6_WEIGHT_8814B) & \
+ BIT_MASK_AC_CHANNEL6_WEIGHT_8814B)
+#define BIT_SET_AC_CHANNEL6_WEIGHT_8814B(x, v) \
+ (BIT_CLEAR_AC_CHANNEL6_WEIGHT_8814B(x) | \
+ BIT_AC_CHANNEL6_WEIGHT_8814B(v))
+
+/* 2 REG_AC_CHANNEL7_WEIGHT_8814B */
+
+#define BIT_SHIFT_AC_CHANNEL7_WEIGHT_8814B 0
+#define BIT_MASK_AC_CHANNEL7_WEIGHT_8814B 0xff
+#define BIT_AC_CHANNEL7_WEIGHT_8814B(x) \
+ (((x) & BIT_MASK_AC_CHANNEL7_WEIGHT_8814B) \
+ << BIT_SHIFT_AC_CHANNEL7_WEIGHT_8814B)
+#define BITS_AC_CHANNEL7_WEIGHT_8814B \
+ (BIT_MASK_AC_CHANNEL7_WEIGHT_8814B \
+ << BIT_SHIFT_AC_CHANNEL7_WEIGHT_8814B)
+#define BIT_CLEAR_AC_CHANNEL7_WEIGHT_8814B(x) \
+ ((x) & (~BITS_AC_CHANNEL7_WEIGHT_8814B))
+#define BIT_GET_AC_CHANNEL7_WEIGHT_8814B(x) \
+ (((x) >> BIT_SHIFT_AC_CHANNEL7_WEIGHT_8814B) & \
+ BIT_MASK_AC_CHANNEL7_WEIGHT_8814B)
+#define BIT_SET_AC_CHANNEL7_WEIGHT_8814B(x, v) \
+ (BIT_CLEAR_AC_CHANNEL7_WEIGHT_8814B(x) | \
+ BIT_AC_CHANNEL7_WEIGHT_8814B(v))
+
+/* 2 REG_AC_CHANNEL8_WEIGHT_8814B */
+
+#define BIT_SHIFT_AC_CHANNEL8_WEIGHT_8814B 0
+#define BIT_MASK_AC_CHANNEL8_WEIGHT_8814B 0xff
+#define BIT_AC_CHANNEL8_WEIGHT_8814B(x) \
+ (((x) & BIT_MASK_AC_CHANNEL8_WEIGHT_8814B) \
+ << BIT_SHIFT_AC_CHANNEL8_WEIGHT_8814B)
+#define BITS_AC_CHANNEL8_WEIGHT_8814B \
+ (BIT_MASK_AC_CHANNEL8_WEIGHT_8814B \
+ << BIT_SHIFT_AC_CHANNEL8_WEIGHT_8814B)
+#define BIT_CLEAR_AC_CHANNEL8_WEIGHT_8814B(x) \
+ ((x) & (~BITS_AC_CHANNEL8_WEIGHT_8814B))
+#define BIT_GET_AC_CHANNEL8_WEIGHT_8814B(x) \
+ (((x) >> BIT_SHIFT_AC_CHANNEL8_WEIGHT_8814B) & \
+ BIT_MASK_AC_CHANNEL8_WEIGHT_8814B)
+#define BIT_SET_AC_CHANNEL8_WEIGHT_8814B(x, v) \
+ (BIT_CLEAR_AC_CHANNEL8_WEIGHT_8814B(x) | \
+ BIT_AC_CHANNEL8_WEIGHT_8814B(v))
+
+/* 2 REG_AC_CHANNEL9_WEIGHT_8814B */
+
+#define BIT_SHIFT_AC_CHANNEL9_WEIGHT_8814B 0
+#define BIT_MASK_AC_CHANNEL9_WEIGHT_8814B 0xff
+#define BIT_AC_CHANNEL9_WEIGHT_8814B(x) \
+ (((x) & BIT_MASK_AC_CHANNEL9_WEIGHT_8814B) \
+ << BIT_SHIFT_AC_CHANNEL9_WEIGHT_8814B)
+#define BITS_AC_CHANNEL9_WEIGHT_8814B \
+ (BIT_MASK_AC_CHANNEL9_WEIGHT_8814B \
+ << BIT_SHIFT_AC_CHANNEL9_WEIGHT_8814B)
+#define BIT_CLEAR_AC_CHANNEL9_WEIGHT_8814B(x) \
+ ((x) & (~BITS_AC_CHANNEL9_WEIGHT_8814B))
+#define BIT_GET_AC_CHANNEL9_WEIGHT_8814B(x) \
+ (((x) >> BIT_SHIFT_AC_CHANNEL9_WEIGHT_8814B) & \
+ BIT_MASK_AC_CHANNEL9_WEIGHT_8814B)
+#define BIT_SET_AC_CHANNEL9_WEIGHT_8814B(x, v) \
+ (BIT_CLEAR_AC_CHANNEL9_WEIGHT_8814B(x) | \
+ BIT_AC_CHANNEL9_WEIGHT_8814B(v))
+
+/* 2 REG_AC_CHANNEL10_WEIGHT_8814B */
+
+#define BIT_SHIFT_AC_CHANNEL10_WEIGHT_8814B 0
+#define BIT_MASK_AC_CHANNEL10_WEIGHT_8814B 0xff
+#define BIT_AC_CHANNEL10_WEIGHT_8814B(x) \
+ (((x) & BIT_MASK_AC_CHANNEL10_WEIGHT_8814B) \
+ << BIT_SHIFT_AC_CHANNEL10_WEIGHT_8814B)
+#define BITS_AC_CHANNEL10_WEIGHT_8814B \
+ (BIT_MASK_AC_CHANNEL10_WEIGHT_8814B \
+ << BIT_SHIFT_AC_CHANNEL10_WEIGHT_8814B)
+#define BIT_CLEAR_AC_CHANNEL10_WEIGHT_8814B(x) \
+ ((x) & (~BITS_AC_CHANNEL10_WEIGHT_8814B))
+#define BIT_GET_AC_CHANNEL10_WEIGHT_8814B(x) \
+ (((x) >> BIT_SHIFT_AC_CHANNEL10_WEIGHT_8814B) & \
+ BIT_MASK_AC_CHANNEL10_WEIGHT_8814B)
+#define BIT_SET_AC_CHANNEL10_WEIGHT_8814B(x, v) \
+ (BIT_CLEAR_AC_CHANNEL10_WEIGHT_8814B(x) | \
+ BIT_AC_CHANNEL10_WEIGHT_8814B(v))
+
+/* 2 REG_AC_CHANNEL11_WEIGHT_8814B */
+
+#define BIT_SHIFT_AC_CHANNEL11_WEIGHT_8814B 0
+#define BIT_MASK_AC_CHANNEL11_WEIGHT_8814B 0xff
+#define BIT_AC_CHANNEL11_WEIGHT_8814B(x) \
+ (((x) & BIT_MASK_AC_CHANNEL11_WEIGHT_8814B) \
+ << BIT_SHIFT_AC_CHANNEL11_WEIGHT_8814B)
+#define BITS_AC_CHANNEL11_WEIGHT_8814B \
+ (BIT_MASK_AC_CHANNEL11_WEIGHT_8814B \
+ << BIT_SHIFT_AC_CHANNEL11_WEIGHT_8814B)
+#define BIT_CLEAR_AC_CHANNEL11_WEIGHT_8814B(x) \
+ ((x) & (~BITS_AC_CHANNEL11_WEIGHT_8814B))
+#define BIT_GET_AC_CHANNEL11_WEIGHT_8814B(x) \
+ (((x) >> BIT_SHIFT_AC_CHANNEL11_WEIGHT_8814B) & \
+ BIT_MASK_AC_CHANNEL11_WEIGHT_8814B)
+#define BIT_SET_AC_CHANNEL11_WEIGHT_8814B(x, v) \
+ (BIT_CLEAR_AC_CHANNEL11_WEIGHT_8814B(x) | \
+ BIT_AC_CHANNEL11_WEIGHT_8814B(v))
+
+/* 2 REG_AC_CHANNEL12_WEIGHT_8814B */
+
+#define BIT_SHIFT_AC_CHANNEL12_WEIGHT_8814B 0
+#define BIT_MASK_AC_CHANNEL12_WEIGHT_8814B 0xff
+#define BIT_AC_CHANNEL12_WEIGHT_8814B(x) \
+ (((x) & BIT_MASK_AC_CHANNEL12_WEIGHT_8814B) \
+ << BIT_SHIFT_AC_CHANNEL12_WEIGHT_8814B)
+#define BITS_AC_CHANNEL12_WEIGHT_8814B \
+ (BIT_MASK_AC_CHANNEL12_WEIGHT_8814B \
+ << BIT_SHIFT_AC_CHANNEL12_WEIGHT_8814B)
+#define BIT_CLEAR_AC_CHANNEL12_WEIGHT_8814B(x) \
+ ((x) & (~BITS_AC_CHANNEL12_WEIGHT_8814B))
+#define BIT_GET_AC_CHANNEL12_WEIGHT_8814B(x) \
+ (((x) >> BIT_SHIFT_AC_CHANNEL12_WEIGHT_8814B) & \
+ BIT_MASK_AC_CHANNEL12_WEIGHT_8814B)
+#define BIT_SET_AC_CHANNEL12_WEIGHT_8814B(x, v) \
+ (BIT_CLEAR_AC_CHANNEL12_WEIGHT_8814B(x) | \
+ BIT_AC_CHANNEL12_WEIGHT_8814B(v))
+
+/* 2 REG_AC_CHANNEL13_WEIGHT_8814B */
+
+#define BIT_SHIFT_AC_CHANNEL13_WEIGHT_8814B 0
+#define BIT_MASK_AC_CHANNEL13_WEIGHT_8814B 0xff
+#define BIT_AC_CHANNEL13_WEIGHT_8814B(x) \
+ (((x) & BIT_MASK_AC_CHANNEL13_WEIGHT_8814B) \
+ << BIT_SHIFT_AC_CHANNEL13_WEIGHT_8814B)
+#define BITS_AC_CHANNEL13_WEIGHT_8814B \
+ (BIT_MASK_AC_CHANNEL13_WEIGHT_8814B \
+ << BIT_SHIFT_AC_CHANNEL13_WEIGHT_8814B)
+#define BIT_CLEAR_AC_CHANNEL13_WEIGHT_8814B(x) \
+ ((x) & (~BITS_AC_CHANNEL13_WEIGHT_8814B))
+#define BIT_GET_AC_CHANNEL13_WEIGHT_8814B(x) \
+ (((x) >> BIT_SHIFT_AC_CHANNEL13_WEIGHT_8814B) & \
+ BIT_MASK_AC_CHANNEL13_WEIGHT_8814B)
+#define BIT_SET_AC_CHANNEL13_WEIGHT_8814B(x, v) \
+ (BIT_CLEAR_AC_CHANNEL13_WEIGHT_8814B(x) | \
+ BIT_AC_CHANNEL13_WEIGHT_8814B(v))
+
+/* 2 REG_PCIE_HISR2_8814B */
+#define BIT_BCNDMAINT_P4_8814B BIT(31)
+#define BIT_BCNDMAINT_P3_8814B BIT(30)
+#define BIT_BCNDMAINT_P2_8814B BIT(29)
+#define BIT_BCNDMAINT_P1_8814B BIT(28)
+#define BIT_SCH_PHY_TXOP_SIFS_INT_8814B BIT(23)
+#define BIT_ATIMEND7_8814B BIT(22)
+#define BIT_ATIMEND6_8814B BIT(21)
+#define BIT_ATIMEND5_8814B BIT(20)
+#define BIT_ATIMEND4_8814B BIT(19)
+#define BIT_ATIMEND3_8814B BIT(18)
+#define BIT_ATIMEND2_8814B BIT(17)
+#define BIT_ATIMEND1_8814B BIT(16)
+#define BIT_TXBCN7OK_8814B BIT(14)
+#define BIT_TXBCN6OK_8814B BIT(13)
+#define BIT_TXBCN5OK_8814B BIT(12)
+#define BIT_TXBCN4OK_8814B BIT(11)
+#define BIT_TXBCN3OK_8814B BIT(10)
+#define BIT_TXBCN2OK_8814B BIT(9)
+#define BIT_TXBCN1OK_8814B BIT(8)
+#define BIT_TXBCN7ERR_8814B BIT(6)
+#define BIT_TXBCN6ERR_8814B BIT(5)
+#define BIT_TXBCN5ERR_8814B BIT(4)
+#define BIT_TXBCN4ERR_8814B BIT(3)
+#define BIT_TXBCN3ERR_8814B BIT(2)
+#define BIT_TXBCN2ERR_8814B BIT(1)
+#define BIT_TXBCN1ERR_8814B BIT(0)
+
+/* 2 REG_PCIE_HISR3_8814B */
+#define BIT_GTINT12_8814B BIT(24)
+#define BIT_GTINT11_8814B BIT(23)
+#define BIT_GTINT10_8814B BIT(22)
+#define BIT_GTINT9_8814B BIT(21)
+#define BIT_RX_DESC_BUF_FULL_8814B BIT(20)
+#define BIT_CPHY_LDO_OCP_DET_INT_8814B BIT(19)
+#define BIT_WDT_PLATFORM_INT_8814B BIT(18)
+#define BIT_WDT_CPU_INT_8814B BIT(17)
+#define BIT_SETH2CDOK_8814B BIT(16)
+#define BIT_H2C_CMD_FULL_8814B BIT(15)
+#define BIT_PKT_TRANS_ERR_8814B BIT(14)
+#define BIT_TXSHORTCUT_TXDESUPDATEOK_8814B BIT(13)
+#define BIT_TXSHORTCUT_BKUPDATEOK_8814B BIT(12)
+#define BIT_TXSHORTCUT_BEUPDATEOK_8814B BIT(11)
+#define BIT_TXSHORTCUT_VIUPDATEOK_8814B BIT(10)
+#define BIT_TXSHORTCUT_VOUPDATEOK_8814B BIT(9)
+#define BIT_SEARCH_FAIL_8814B BIT(8)
+#define BIT_PWR_INT_127TO96_8814B BIT(7)
+#define BIT_PWR_INT_95TO64_8814B BIT(6)
+#define BIT_PWR_INT_63TO32_8814B BIT(5)
+#define BIT_PWR_INT_31TO0_8814B BIT(4)
+#define BIT_RX_DMA_STUCK_8814B BIT(3)
+#define BIT_TX_DMA_STUCK_8814B BIT(2)
+#define BIT_DDMA0_LP_INT_8814B BIT(1)
+#define BIT_DDMA0_HP_INT_8814B BIT(0)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_QUEUELIST_INFO0_8814B */
+
+#define BIT_SHIFT_QINFO0_8814B 0
+#define BIT_MASK_QINFO0_8814B 0xffffffffL
+#define BIT_QINFO0_8814B(x) \
+ (((x) & BIT_MASK_QINFO0_8814B) << BIT_SHIFT_QINFO0_8814B)
+#define BITS_QINFO0_8814B (BIT_MASK_QINFO0_8814B << BIT_SHIFT_QINFO0_8814B)
+#define BIT_CLEAR_QINFO0_8814B(x) ((x) & (~BITS_QINFO0_8814B))
+#define BIT_GET_QINFO0_8814B(x) \
+ (((x) >> BIT_SHIFT_QINFO0_8814B) & BIT_MASK_QINFO0_8814B)
+#define BIT_SET_QINFO0_8814B(x, v) \
+ (BIT_CLEAR_QINFO0_8814B(x) | BIT_QINFO0_8814B(v))
+
+/* 2 REG_QUEUELIST_INFO1_8814B */
+
+#define BIT_SHIFT_QINFO1_8814B 0
+#define BIT_MASK_QINFO1_8814B 0xffffffffL
+#define BIT_QINFO1_8814B(x) \
+ (((x) & BIT_MASK_QINFO1_8814B) << BIT_SHIFT_QINFO1_8814B)
+#define BITS_QINFO1_8814B (BIT_MASK_QINFO1_8814B << BIT_SHIFT_QINFO1_8814B)
+#define BIT_CLEAR_QINFO1_8814B(x) ((x) & (~BITS_QINFO1_8814B))
+#define BIT_GET_QINFO1_8814B(x) \
+ (((x) >> BIT_SHIFT_QINFO1_8814B) & BIT_MASK_QINFO1_8814B)
+#define BIT_SET_QINFO1_8814B(x, v) \
+ (BIT_CLEAR_QINFO1_8814B(x) | BIT_QINFO1_8814B(v))
+
+/* 2 REG_QUEUELIST_INFO2_8814B */
+
+#define BIT_SHIFT_QINFO2_8814B 0
+#define BIT_MASK_QINFO2_8814B 0xffffffffL
+#define BIT_QINFO2_8814B(x) \
+ (((x) & BIT_MASK_QINFO2_8814B) << BIT_SHIFT_QINFO2_8814B)
+#define BITS_QINFO2_8814B (BIT_MASK_QINFO2_8814B << BIT_SHIFT_QINFO2_8814B)
+#define BIT_CLEAR_QINFO2_8814B(x) ((x) & (~BITS_QINFO2_8814B))
+#define BIT_GET_QINFO2_8814B(x) \
+ (((x) >> BIT_SHIFT_QINFO2_8814B) & BIT_MASK_QINFO2_8814B)
+#define BIT_SET_QINFO2_8814B(x, v) \
+ (BIT_CLEAR_QINFO2_8814B(x) | BIT_QINFO2_8814B(v))
+
+/* 2 REG_QUEUELIST_INFO3_8814B */
+
+#define BIT_SHIFT_QINFO3_8814B 0
+#define BIT_MASK_QINFO3_8814B 0xffffffffL
+#define BIT_QINFO3_8814B(x) \
+ (((x) & BIT_MASK_QINFO3_8814B) << BIT_SHIFT_QINFO3_8814B)
+#define BITS_QINFO3_8814B (BIT_MASK_QINFO3_8814B << BIT_SHIFT_QINFO3_8814B)
+#define BIT_CLEAR_QINFO3_8814B(x) ((x) & (~BITS_QINFO3_8814B))
+#define BIT_GET_QINFO3_8814B(x) \
+ (((x) >> BIT_SHIFT_QINFO3_8814B) & BIT_MASK_QINFO3_8814B)
+#define BIT_SET_QINFO3_8814B(x, v) \
+ (BIT_CLEAR_QINFO3_8814B(x) | BIT_QINFO3_8814B(v))
+
+/* 2 REG_QUEUELIST_INFO_EMPTY_8814B */
+#define BIT_FWCMDQ_EMPTY_8814B BIT(31)
+#define BIT_MGQ_CPU_EMPTY_V1_8814B BIT(30)
+#define BIT_BCNQ_EMPTY_EXTP0_8814B BIT(29)
+#define BIT_BCNQ_EMPTY_PORT4_8814B BIT(28)
+#define BIT_BCNQ_EMPTY_PORT3_8814B BIT(27)
+#define BIT_BCNQ_EMPTY_PORT2_8814B BIT(26)
+#define BIT_BCNQ_EMPTY_PORT1_8814B BIT(25)
+#define BIT_BCNQ_EMPTY_PORT0_8814B BIT(24)
+#define BIT_HQQ_EMPTY_V1_8814B BIT(23)
+#define BIT_MQQ_EMPTY_V2_8814B BIT(22)
+#define BIT_S1_EMPTY_8814B BIT(21)
+#define BIT_S0_EMPTY_8814B BIT(20)
+#define BIT_AC19Q_EMPTY_8814B BIT(19)
+#define BIT_AC18Q_EMPTY_8814B BIT(18)
+#define BIT_AC17Q_EMPTY_8814B BIT(17)
+#define BIT_AC16Q_EMPTY_8814B BIT(16)
+#define BIT_AC15Q_EMPTY_8814B BIT(15)
+#define BIT_AC14Q_EMPTY_8814B BIT(14)
+#define BIT_AC13Q_EMPTY_8814B BIT(13)
+#define BIT_AC12Q_EMPTY_8814B BIT(12)
+#define BIT_AC11Q_EMPTY_8814B BIT(11)
+#define BIT_AC10Q_EMPTY_8814B BIT(10)
+#define BIT_AC9Q_EMPTY_8814B BIT(9)
+#define BIT_AC8Q_EMPTY_8814B BIT(8)
+#define BIT_AC7Q_EMPTY_8814B BIT(7)
+#define BIT_AC6Q_EMPTY_8814B BIT(6)
+#define BIT_AC5Q_EMPTY_8814B BIT(5)
+#define BIT_AC4Q_EMPTY_8814B BIT(4)
+#define BIT_AC3Q_EMPTY_8814B BIT(3)
+#define BIT_AC2Q_EMPTY_8814B BIT(2)
+#define BIT_AC1Q_EMPTY_8814B BIT(1)
+#define BIT_AC0Q_EMPTY_8814B BIT(0)
+
+/* 2 REG_QUEUELIST_ACQ_EN_8814B */
+
+#define BIT_SHIFT_QINFO_CTRL_8814B 24
+#define BIT_MASK_QINFO_CTRL_8814B 0x3f
+#define BIT_QINFO_CTRL_8814B(x) \
+ (((x) & BIT_MASK_QINFO_CTRL_8814B) << BIT_SHIFT_QINFO_CTRL_8814B)
+#define BITS_QINFO_CTRL_8814B \
+ (BIT_MASK_QINFO_CTRL_8814B << BIT_SHIFT_QINFO_CTRL_8814B)
+#define BIT_CLEAR_QINFO_CTRL_8814B(x) ((x) & (~BITS_QINFO_CTRL_8814B))
+#define BIT_GET_QINFO_CTRL_8814B(x) \
+ (((x) >> BIT_SHIFT_QINFO_CTRL_8814B) & BIT_MASK_QINFO_CTRL_8814B)
+#define BIT_SET_QINFO_CTRL_8814B(x, v) \
+ (BIT_CLEAR_QINFO_CTRL_8814B(x) | BIT_QINFO_CTRL_8814B(v))
+
+#define BIT_SHIFT_QINFO_MODE_BAND_8814B 20
+#define BIT_MASK_QINFO_MODE_BAND_8814B 0x7
+#define BIT_QINFO_MODE_BAND_8814B(x) \
+ (((x) & BIT_MASK_QINFO_MODE_BAND_8814B) \
+ << BIT_SHIFT_QINFO_MODE_BAND_8814B)
+#define BITS_QINFO_MODE_BAND_8814B \
+ (BIT_MASK_QINFO_MODE_BAND_8814B << BIT_SHIFT_QINFO_MODE_BAND_8814B)
+#define BIT_CLEAR_QINFO_MODE_BAND_8814B(x) ((x) & (~BITS_QINFO_MODE_BAND_8814B))
+#define BIT_GET_QINFO_MODE_BAND_8814B(x) \
+ (((x) >> BIT_SHIFT_QINFO_MODE_BAND_8814B) & \
+ BIT_MASK_QINFO_MODE_BAND_8814B)
+#define BIT_SET_QINFO_MODE_BAND_8814B(x, v) \
+ (BIT_CLEAR_QINFO_MODE_BAND_8814B(x) | BIT_QINFO_MODE_BAND_8814B(v))
+
+#define BIT_ACQ19_ENABLE_8814B BIT(19)
+#define BIT_ACQ18_ENABLE_8814B BIT(18)
+#define BIT_ACQ17_ENABLE_8814B BIT(17)
+#define BIT_ACQ16_ENABLE_8814B BIT(16)
+#define BIT_ACQ15_ENABLE_8814B BIT(15)
+#define BIT_ACQ14_ENABLE_8814B BIT(14)
+#define BIT_ACQ13_ENABLE_8814B BIT(13)
+#define BIT_ACQ12_ENABLE_8814B BIT(12)
+#define BIT_ACQ11_ENABLE_8814B BIT(11)
+#define BIT_ACQ10_ENABLE_8814B BIT(10)
+#define BIT_ACQ9_ENABLE_8814B BIT(9)
+#define BIT_ACQ8_ENABLE_8814B BIT(8)
+#define BIT_ACQ7_ENABLE_8814B BIT(7)
+#define BIT_ACQ6_ENABLE_8814B BIT(6)
+#define BIT_ACQ5_ENABLE_8814B BIT(5)
+#define BIT_ACQ4_ENABLE_8814B BIT(4)
+#define BIT_ACQ3_ENABLE_8814B BIT(3)
+#define BIT_ACQ2_ENABLE_8814B BIT(2)
+#define BIT_ACQ1_ENABLE_8814B BIT(1)
+#define BIT_ACQ0_ENABLE_8814B BIT(0)
+
+/* 2 REG_BCNQ_BDNY_V2_8814B */
+
+#define BIT_SHIFT_BCNQ_PGBNDY_WSEL_8814B 28
+#define BIT_MASK_BCNQ_PGBNDY_WSEL_8814B 0x7
+#define BIT_BCNQ_PGBNDY_WSEL_8814B(x) \
+ (((x) & BIT_MASK_BCNQ_PGBNDY_WSEL_8814B) \
+ << BIT_SHIFT_BCNQ_PGBNDY_WSEL_8814B)
+#define BITS_BCNQ_PGBNDY_WSEL_8814B \
+ (BIT_MASK_BCNQ_PGBNDY_WSEL_8814B << BIT_SHIFT_BCNQ_PGBNDY_WSEL_8814B)
+#define BIT_CLEAR_BCNQ_PGBNDY_WSEL_8814B(x) \
+ ((x) & (~BITS_BCNQ_PGBNDY_WSEL_8814B))
+#define BIT_GET_BCNQ_PGBNDY_WSEL_8814B(x) \
+ (((x) >> BIT_SHIFT_BCNQ_PGBNDY_WSEL_8814B) & \
+ BIT_MASK_BCNQ_PGBNDY_WSEL_8814B)
+#define BIT_SET_BCNQ_PGBNDY_WSEL_8814B(x, v) \
+ (BIT_CLEAR_BCNQ_PGBNDY_WSEL_8814B(x) | BIT_BCNQ_PGBNDY_WSEL_8814B(v))
+
+#define BIT_SHIFT_BCNQ_PGBNDY_RCONTENT_8814B 12
+#define BIT_MASK_BCNQ_PGBNDY_RCONTENT_8814B 0xfff
+#define BIT_BCNQ_PGBNDY_RCONTENT_8814B(x) \
+ (((x) & BIT_MASK_BCNQ_PGBNDY_RCONTENT_8814B) \
+ << BIT_SHIFT_BCNQ_PGBNDY_RCONTENT_8814B)
+#define BITS_BCNQ_PGBNDY_RCONTENT_8814B \
+ (BIT_MASK_BCNQ_PGBNDY_RCONTENT_8814B \
+ << BIT_SHIFT_BCNQ_PGBNDY_RCONTENT_8814B)
+#define BIT_CLEAR_BCNQ_PGBNDY_RCONTENT_8814B(x) \
+ ((x) & (~BITS_BCNQ_PGBNDY_RCONTENT_8814B))
+#define BIT_GET_BCNQ_PGBNDY_RCONTENT_8814B(x) \
+ (((x) >> BIT_SHIFT_BCNQ_PGBNDY_RCONTENT_8814B) & \
+ BIT_MASK_BCNQ_PGBNDY_RCONTENT_8814B)
+#define BIT_SET_BCNQ_PGBNDY_RCONTENT_8814B(x, v) \
+ (BIT_CLEAR_BCNQ_PGBNDY_RCONTENT_8814B(x) | \
+ BIT_BCNQ_PGBNDY_RCONTENT_8814B(v))
+
+#define BIT_SHIFT_BCNQ_PGBNDY_WCONTENT_8814B 0
+#define BIT_MASK_BCNQ_PGBNDY_WCONTENT_8814B 0xfff
+#define BIT_BCNQ_PGBNDY_WCONTENT_8814B(x) \
+ (((x) & BIT_MASK_BCNQ_PGBNDY_WCONTENT_8814B) \
+ << BIT_SHIFT_BCNQ_PGBNDY_WCONTENT_8814B)
+#define BITS_BCNQ_PGBNDY_WCONTENT_8814B \
+ (BIT_MASK_BCNQ_PGBNDY_WCONTENT_8814B \
+ << BIT_SHIFT_BCNQ_PGBNDY_WCONTENT_8814B)
+#define BIT_CLEAR_BCNQ_PGBNDY_WCONTENT_8814B(x) \
+ ((x) & (~BITS_BCNQ_PGBNDY_WCONTENT_8814B))
+#define BIT_GET_BCNQ_PGBNDY_WCONTENT_8814B(x) \
+ (((x) >> BIT_SHIFT_BCNQ_PGBNDY_WCONTENT_8814B) & \
+ BIT_MASK_BCNQ_PGBNDY_WCONTENT_8814B)
+#define BIT_SET_BCNQ_PGBNDY_WCONTENT_8814B(x, v) \
+ (BIT_CLEAR_BCNQ_PGBNDY_WCONTENT_8814B(x) | \
+ BIT_BCNQ_PGBNDY_WCONTENT_8814B(v))
+
+/* 2 REG_CPU_MGQ_INFO_8814B */
+#define BIT_CPUMGT_CLR_V1_8814B BIT(30)
+#define BIT_CPUMGT_POLL_8814B BIT(29)
+#define BIT_BCN_EXT_POLL_8814B BIT(21)
+#define BIT_BCN4_POLL_8814B BIT(20)
+#define BIT_BCN3_POLL_8814B BIT(19)
+#define BIT_BCN2_POLL_8814B BIT(18)
+#define BIT_BCN1_POLL_V1_8814B BIT(17)
+#define BIT_BCN_POLL_V1_8814B BIT(16)
+
+#define BIT_SHIFT_FREE_TAIL_PAGE_8814B 0
+#define BIT_MASK_FREE_TAIL_PAGE_8814B 0xfff
+#define BIT_FREE_TAIL_PAGE_8814B(x) \
+ (((x) & BIT_MASK_FREE_TAIL_PAGE_8814B) \
+ << BIT_SHIFT_FREE_TAIL_PAGE_8814B)
+#define BITS_FREE_TAIL_PAGE_8814B \
+ (BIT_MASK_FREE_TAIL_PAGE_8814B << BIT_SHIFT_FREE_TAIL_PAGE_8814B)
+#define BIT_CLEAR_FREE_TAIL_PAGE_8814B(x) ((x) & (~BITS_FREE_TAIL_PAGE_8814B))
+#define BIT_GET_FREE_TAIL_PAGE_8814B(x) \
+ (((x) >> BIT_SHIFT_FREE_TAIL_PAGE_8814B) & \
+ BIT_MASK_FREE_TAIL_PAGE_8814B)
+#define BIT_SET_FREE_TAIL_PAGE_8814B(x, v) \
+ (BIT_CLEAR_FREE_TAIL_PAGE_8814B(x) | BIT_FREE_TAIL_PAGE_8814B(v))
+
+/* 2 REG_FWHW_TXQ_CTRL_8814B */
+#define BIT_RTS_LIMIT_IN_OFDM_8814B BIT(23)
+#define BIT_EN_RD_RESP_NAV_BK_8814B BIT(21)
+#define BIT_EN_WR_FREE_TAIL_8814B BIT(20)
+#define BIT_NOTXRPT_USERATE_EN_8814B BIT(19)
+#define BIT_DIS_TXFAIL_RPT_8814B BIT(18)
+#define BIT_FTM_TIMEOUT_BYPASS_8814B BIT(16)
+#define BIT_EN_BCNQ_DL5_8814B BIT(13)
+#define BIT_EN_BCNQ_DL4_8814B BIT(12)
+#define BIT_EN_BCNQ_DL3_8814B BIT(11)
+#define BIT_EN_BCNQ_DL2_8814B BIT(10)
+#define BIT_EN_BCNQ_DL1_8814B BIT(9)
+#define BIT_EN_BCNQ_DL0_8814B BIT(8)
+#define BIT_EN_RTY_BK_8814B BIT(7)
+#define BIT_EN_USE_INI_RAT_8814B BIT(6)
+#define BIT_EN_RTS_NAV_BK_8814B BIT(5)
+#define BIT_DIS_SSN_CHECK_8814B BIT(4)
+#define BIT_MACID_MATCH_RTS_8814B BIT(3)
+#define BIT_EN_BCN_TRXRPT_V1_8814B BIT(2)
+#define BIT_EN_FTMRPT_V1_8814B BIT(1)
+#define BIT_BMC_NAV_PROTECT_8814B BIT(0)
+
+/* 2 REG_DATAFB_SEL_8814B */
+#define BIT_BROADCAST_RTY_EN_8814B BIT(3)
+#define BIT_EN_RTY_BK_COD_8814B BIT(2)
+
+#define BIT_SHIFT__DATA_FALLBACK_SEL_8814B 0
+#define BIT_MASK__DATA_FALLBACK_SEL_8814B 0x3
+#define BIT__DATA_FALLBACK_SEL_8814B(x) \
+ (((x) & BIT_MASK__DATA_FALLBACK_SEL_8814B) \
+ << BIT_SHIFT__DATA_FALLBACK_SEL_8814B)
+#define BITS__DATA_FALLBACK_SEL_8814B \
+ (BIT_MASK__DATA_FALLBACK_SEL_8814B \
+ << BIT_SHIFT__DATA_FALLBACK_SEL_8814B)
+#define BIT_CLEAR__DATA_FALLBACK_SEL_8814B(x) \
+ ((x) & (~BITS__DATA_FALLBACK_SEL_8814B))
+#define BIT_GET__DATA_FALLBACK_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT__DATA_FALLBACK_SEL_8814B) & \
+ BIT_MASK__DATA_FALLBACK_SEL_8814B)
+#define BIT_SET__DATA_FALLBACK_SEL_8814B(x, v) \
+ (BIT_CLEAR__DATA_FALLBACK_SEL_8814B(x) | \
+ BIT__DATA_FALLBACK_SEL_8814B(v))
+
+/* 2 REG_TXBDNY_8814B */
+
+#define BIT_SHIFT_TXBNDY_8814B 0
+#define BIT_MASK_TXBNDY_8814B 0xfff
+#define BIT_TXBNDY_8814B(x) \
+ (((x) & BIT_MASK_TXBNDY_8814B) << BIT_SHIFT_TXBNDY_8814B)
+#define BITS_TXBNDY_8814B (BIT_MASK_TXBNDY_8814B << BIT_SHIFT_TXBNDY_8814B)
+#define BIT_CLEAR_TXBNDY_8814B(x) ((x) & (~BITS_TXBNDY_8814B))
+#define BIT_GET_TXBNDY_8814B(x) \
+ (((x) >> BIT_SHIFT_TXBNDY_8814B) & BIT_MASK_TXBNDY_8814B)
+#define BIT_SET_TXBNDY_8814B(x, v) \
+ (BIT_CLEAR_TXBNDY_8814B(x) | BIT_TXBNDY_8814B(v))
+
+/* 2 REG_LIFETIME_EN_8814B */
+#define BIT_BT_INT_CPU_8814B BIT(7)
+#define BIT_BT_INT_PTA_8814B BIT(6)
+#define BIT_EN_CTRL_RTYBIT_8814B BIT(4)
+#define BIT_LIFETIME_BK_EN_8814B BIT(3)
+#define BIT_LIFETIME_BE_EN_8814B BIT(2)
+#define BIT_LIFETIME_VI_EN_8814B BIT(1)
+#define BIT_LIFETIME_VO_EN_8814B BIT(0)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_SPEC_SIFS_8814B */
+
+#define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8814B 8
+#define BIT_MASK_SPEC_SIFS_OFDM_PTCL_8814B 0xff
+#define BIT_SPEC_SIFS_OFDM_PTCL_8814B(x) \
+ (((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8814B) \
+ << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8814B)
+#define BITS_SPEC_SIFS_OFDM_PTCL_8814B \
+ (BIT_MASK_SPEC_SIFS_OFDM_PTCL_8814B \
+ << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8814B)
+#define BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8814B(x) \
+ ((x) & (~BITS_SPEC_SIFS_OFDM_PTCL_8814B))
+#define BIT_GET_SPEC_SIFS_OFDM_PTCL_8814B(x) \
+ (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8814B) & \
+ BIT_MASK_SPEC_SIFS_OFDM_PTCL_8814B)
+#define BIT_SET_SPEC_SIFS_OFDM_PTCL_8814B(x, v) \
+ (BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8814B(x) | \
+ BIT_SPEC_SIFS_OFDM_PTCL_8814B(v))
+
+#define BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8814B 0
+#define BIT_MASK_SPEC_SIFS_CCK_PTCL_8814B 0xff
+#define BIT_SPEC_SIFS_CCK_PTCL_8814B(x) \
+ (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8814B) \
+ << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8814B)
+#define BITS_SPEC_SIFS_CCK_PTCL_8814B \
+ (BIT_MASK_SPEC_SIFS_CCK_PTCL_8814B \
+ << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8814B)
+#define BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8814B(x) \
+ ((x) & (~BITS_SPEC_SIFS_CCK_PTCL_8814B))
+#define BIT_GET_SPEC_SIFS_CCK_PTCL_8814B(x) \
+ (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8814B) & \
+ BIT_MASK_SPEC_SIFS_CCK_PTCL_8814B)
+#define BIT_SET_SPEC_SIFS_CCK_PTCL_8814B(x, v) \
+ (BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8814B(x) | \
+ BIT_SPEC_SIFS_CCK_PTCL_8814B(v))
+
+/* 2 REG_RETRY_LIMIT_8814B */
+
+#define BIT_SHIFT_SRL_8814B 8
+#define BIT_MASK_SRL_8814B 0x3f
+#define BIT_SRL_8814B(x) (((x) & BIT_MASK_SRL_8814B) << BIT_SHIFT_SRL_8814B)
+#define BITS_SRL_8814B (BIT_MASK_SRL_8814B << BIT_SHIFT_SRL_8814B)
+#define BIT_CLEAR_SRL_8814B(x) ((x) & (~BITS_SRL_8814B))
+#define BIT_GET_SRL_8814B(x) (((x) >> BIT_SHIFT_SRL_8814B) & BIT_MASK_SRL_8814B)
+#define BIT_SET_SRL_8814B(x, v) (BIT_CLEAR_SRL_8814B(x) | BIT_SRL_8814B(v))
+
+#define BIT_SHIFT_LRL_8814B 0
+#define BIT_MASK_LRL_8814B 0x3f
+#define BIT_LRL_8814B(x) (((x) & BIT_MASK_LRL_8814B) << BIT_SHIFT_LRL_8814B)
+#define BITS_LRL_8814B (BIT_MASK_LRL_8814B << BIT_SHIFT_LRL_8814B)
+#define BIT_CLEAR_LRL_8814B(x) ((x) & (~BITS_LRL_8814B))
+#define BIT_GET_LRL_8814B(x) (((x) >> BIT_SHIFT_LRL_8814B) & BIT_MASK_LRL_8814B)
+#define BIT_SET_LRL_8814B(x, v) (BIT_CLEAR_LRL_8814B(x) | BIT_LRL_8814B(v))
+
+/* 2 REG_TXBF_CTRL_8814B */
+#define BIT_ENABLE_NDPA_8814B BIT(31)
+#define BIT_NDPA_PARA_8814B BIT(30)
+#define BIT_PROP_TXBF_8814B BIT(29)
+#define BIT_EN_NDPA_INT_8814B BIT(28)
+#define BIT_TXBF1_80M_160M_8814B BIT(27)
+#define BIT_TXBF1_40M_8814B BIT(26)
+#define BIT_TXBF1_20M_8814B BIT(25)
+
+#define BIT_SHIFT_TXBF1_AID_8814B 16
+#define BIT_MASK_TXBF1_AID_8814B 0x1ff
+#define BIT_TXBF1_AID_8814B(x) \
+ (((x) & BIT_MASK_TXBF1_AID_8814B) << BIT_SHIFT_TXBF1_AID_8814B)
+#define BITS_TXBF1_AID_8814B \
+ (BIT_MASK_TXBF1_AID_8814B << BIT_SHIFT_TXBF1_AID_8814B)
+#define BIT_CLEAR_TXBF1_AID_8814B(x) ((x) & (~BITS_TXBF1_AID_8814B))
+#define BIT_GET_TXBF1_AID_8814B(x) \
+ (((x) >> BIT_SHIFT_TXBF1_AID_8814B) & BIT_MASK_TXBF1_AID_8814B)
+#define BIT_SET_TXBF1_AID_8814B(x, v) \
+ (BIT_CLEAR_TXBF1_AID_8814B(x) | BIT_TXBF1_AID_8814B(v))
+
+#define BIT_DIS_NDP_BFEN_8814B BIT(15)
+#define BIT_TXBCN_NOBLOCK_NDP_8814B BIT(14)
+#define BIT_TXBF0_80M_160M_8814B BIT(11)
+#define BIT_TXBF0_40M_8814B BIT(10)
+#define BIT_TXBF0_20M_8814B BIT(9)
+
+#define BIT_SHIFT_TXBF0_AID_8814B 0
+#define BIT_MASK_TXBF0_AID_8814B 0x1ff
+#define BIT_TXBF0_AID_8814B(x) \
+ (((x) & BIT_MASK_TXBF0_AID_8814B) << BIT_SHIFT_TXBF0_AID_8814B)
+#define BITS_TXBF0_AID_8814B \
+ (BIT_MASK_TXBF0_AID_8814B << BIT_SHIFT_TXBF0_AID_8814B)
+#define BIT_CLEAR_TXBF0_AID_8814B(x) ((x) & (~BITS_TXBF0_AID_8814B))
+#define BIT_GET_TXBF0_AID_8814B(x) \
+ (((x) >> BIT_SHIFT_TXBF0_AID_8814B) & BIT_MASK_TXBF0_AID_8814B)
+#define BIT_SET_TXBF0_AID_8814B(x, v) \
+ (BIT_CLEAR_TXBF0_AID_8814B(x) | BIT_TXBF0_AID_8814B(v))
+
+/* 2 REG_DARFRC_8814B */
+
+#define BIT_SHIFT_DARF_RC4_V1_8814B 24
+#define BIT_MASK_DARF_RC4_V1_8814B 0x3f
+#define BIT_DARF_RC4_V1_8814B(x) \
+ (((x) & BIT_MASK_DARF_RC4_V1_8814B) << BIT_SHIFT_DARF_RC4_V1_8814B)
+#define BITS_DARF_RC4_V1_8814B \
+ (BIT_MASK_DARF_RC4_V1_8814B << BIT_SHIFT_DARF_RC4_V1_8814B)
+#define BIT_CLEAR_DARF_RC4_V1_8814B(x) ((x) & (~BITS_DARF_RC4_V1_8814B))
+#define BIT_GET_DARF_RC4_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_DARF_RC4_V1_8814B) & BIT_MASK_DARF_RC4_V1_8814B)
+#define BIT_SET_DARF_RC4_V1_8814B(x, v) \
+ (BIT_CLEAR_DARF_RC4_V1_8814B(x) | BIT_DARF_RC4_V1_8814B(v))
+
+#define BIT_SHIFT_DARF_RC3_V1_8814B 16
+#define BIT_MASK_DARF_RC3_V1_8814B 0x3f
+#define BIT_DARF_RC3_V1_8814B(x) \
+ (((x) & BIT_MASK_DARF_RC3_V1_8814B) << BIT_SHIFT_DARF_RC3_V1_8814B)
+#define BITS_DARF_RC3_V1_8814B \
+ (BIT_MASK_DARF_RC3_V1_8814B << BIT_SHIFT_DARF_RC3_V1_8814B)
+#define BIT_CLEAR_DARF_RC3_V1_8814B(x) ((x) & (~BITS_DARF_RC3_V1_8814B))
+#define BIT_GET_DARF_RC3_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_DARF_RC3_V1_8814B) & BIT_MASK_DARF_RC3_V1_8814B)
+#define BIT_SET_DARF_RC3_V1_8814B(x, v) \
+ (BIT_CLEAR_DARF_RC3_V1_8814B(x) | BIT_DARF_RC3_V1_8814B(v))
+
+#define BIT_SHIFT_DARF_RC2_V1_8814B 8
+#define BIT_MASK_DARF_RC2_V1_8814B 0x3f
+#define BIT_DARF_RC2_V1_8814B(x) \
+ (((x) & BIT_MASK_DARF_RC2_V1_8814B) << BIT_SHIFT_DARF_RC2_V1_8814B)
+#define BITS_DARF_RC2_V1_8814B \
+ (BIT_MASK_DARF_RC2_V1_8814B << BIT_SHIFT_DARF_RC2_V1_8814B)
+#define BIT_CLEAR_DARF_RC2_V1_8814B(x) ((x) & (~BITS_DARF_RC2_V1_8814B))
+#define BIT_GET_DARF_RC2_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_DARF_RC2_V1_8814B) & BIT_MASK_DARF_RC2_V1_8814B)
+#define BIT_SET_DARF_RC2_V1_8814B(x, v) \
+ (BIT_CLEAR_DARF_RC2_V1_8814B(x) | BIT_DARF_RC2_V1_8814B(v))
+
+#define BIT_SHIFT_DARF_RC1_V1_8814B 0
+#define BIT_MASK_DARF_RC1_V1_8814B 0x3f
+#define BIT_DARF_RC1_V1_8814B(x) \
+ (((x) & BIT_MASK_DARF_RC1_V1_8814B) << BIT_SHIFT_DARF_RC1_V1_8814B)
+#define BITS_DARF_RC1_V1_8814B \
+ (BIT_MASK_DARF_RC1_V1_8814B << BIT_SHIFT_DARF_RC1_V1_8814B)
+#define BIT_CLEAR_DARF_RC1_V1_8814B(x) ((x) & (~BITS_DARF_RC1_V1_8814B))
+#define BIT_GET_DARF_RC1_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_DARF_RC1_V1_8814B) & BIT_MASK_DARF_RC1_V1_8814B)
+#define BIT_SET_DARF_RC1_V1_8814B(x, v) \
+ (BIT_CLEAR_DARF_RC1_V1_8814B(x) | BIT_DARF_RC1_V1_8814B(v))
+
+/* 2 REG_DARFRCH_8814B */
+
+#define BIT_SHIFT_DARF_RC8_V2_8814B 24
+#define BIT_MASK_DARF_RC8_V2_8814B 0x3f
+#define BIT_DARF_RC8_V2_8814B(x) \
+ (((x) & BIT_MASK_DARF_RC8_V2_8814B) << BIT_SHIFT_DARF_RC8_V2_8814B)
+#define BITS_DARF_RC8_V2_8814B \
+ (BIT_MASK_DARF_RC8_V2_8814B << BIT_SHIFT_DARF_RC8_V2_8814B)
+#define BIT_CLEAR_DARF_RC8_V2_8814B(x) ((x) & (~BITS_DARF_RC8_V2_8814B))
+#define BIT_GET_DARF_RC8_V2_8814B(x) \
+ (((x) >> BIT_SHIFT_DARF_RC8_V2_8814B) & BIT_MASK_DARF_RC8_V2_8814B)
+#define BIT_SET_DARF_RC8_V2_8814B(x, v) \
+ (BIT_CLEAR_DARF_RC8_V2_8814B(x) | BIT_DARF_RC8_V2_8814B(v))
+
+#define BIT_SHIFT_DARF_RC7_V2_8814B 16
+#define BIT_MASK_DARF_RC7_V2_8814B 0x3f
+#define BIT_DARF_RC7_V2_8814B(x) \
+ (((x) & BIT_MASK_DARF_RC7_V2_8814B) << BIT_SHIFT_DARF_RC7_V2_8814B)
+#define BITS_DARF_RC7_V2_8814B \
+ (BIT_MASK_DARF_RC7_V2_8814B << BIT_SHIFT_DARF_RC7_V2_8814B)
+#define BIT_CLEAR_DARF_RC7_V2_8814B(x) ((x) & (~BITS_DARF_RC7_V2_8814B))
+#define BIT_GET_DARF_RC7_V2_8814B(x) \
+ (((x) >> BIT_SHIFT_DARF_RC7_V2_8814B) & BIT_MASK_DARF_RC7_V2_8814B)
+#define BIT_SET_DARF_RC7_V2_8814B(x, v) \
+ (BIT_CLEAR_DARF_RC7_V2_8814B(x) | BIT_DARF_RC7_V2_8814B(v))
+
+#define BIT_SHIFT_DARF_RC6_V2_8814B 8
+#define BIT_MASK_DARF_RC6_V2_8814B 0x3f
+#define BIT_DARF_RC6_V2_8814B(x) \
+ (((x) & BIT_MASK_DARF_RC6_V2_8814B) << BIT_SHIFT_DARF_RC6_V2_8814B)
+#define BITS_DARF_RC6_V2_8814B \
+ (BIT_MASK_DARF_RC6_V2_8814B << BIT_SHIFT_DARF_RC6_V2_8814B)
+#define BIT_CLEAR_DARF_RC6_V2_8814B(x) ((x) & (~BITS_DARF_RC6_V2_8814B))
+#define BIT_GET_DARF_RC6_V2_8814B(x) \
+ (((x) >> BIT_SHIFT_DARF_RC6_V2_8814B) & BIT_MASK_DARF_RC6_V2_8814B)
+#define BIT_SET_DARF_RC6_V2_8814B(x, v) \
+ (BIT_CLEAR_DARF_RC6_V2_8814B(x) | BIT_DARF_RC6_V2_8814B(v))
+
+#define BIT_SHIFT_DARF_RC5_V2_8814B 0
+#define BIT_MASK_DARF_RC5_V2_8814B 0x3f
+#define BIT_DARF_RC5_V2_8814B(x) \
+ (((x) & BIT_MASK_DARF_RC5_V2_8814B) << BIT_SHIFT_DARF_RC5_V2_8814B)
+#define BITS_DARF_RC5_V2_8814B \
+ (BIT_MASK_DARF_RC5_V2_8814B << BIT_SHIFT_DARF_RC5_V2_8814B)
+#define BIT_CLEAR_DARF_RC5_V2_8814B(x) ((x) & (~BITS_DARF_RC5_V2_8814B))
+#define BIT_GET_DARF_RC5_V2_8814B(x) \
+ (((x) >> BIT_SHIFT_DARF_RC5_V2_8814B) & BIT_MASK_DARF_RC5_V2_8814B)
+#define BIT_SET_DARF_RC5_V2_8814B(x, v) \
+ (BIT_CLEAR_DARF_RC5_V2_8814B(x) | BIT_DARF_RC5_V2_8814B(v))
+
+/* 2 REG_RARFRC_8814B */
+
+#define BIT_SHIFT_RARF_RC4_8814B 24
+#define BIT_MASK_RARF_RC4_8814B 0x1f
+#define BIT_RARF_RC4_8814B(x) \
+ (((x) & BIT_MASK_RARF_RC4_8814B) << BIT_SHIFT_RARF_RC4_8814B)
+#define BITS_RARF_RC4_8814B \
+ (BIT_MASK_RARF_RC4_8814B << BIT_SHIFT_RARF_RC4_8814B)
+#define BIT_CLEAR_RARF_RC4_8814B(x) ((x) & (~BITS_RARF_RC4_8814B))
+#define BIT_GET_RARF_RC4_8814B(x) \
+ (((x) >> BIT_SHIFT_RARF_RC4_8814B) & BIT_MASK_RARF_RC4_8814B)
+#define BIT_SET_RARF_RC4_8814B(x, v) \
+ (BIT_CLEAR_RARF_RC4_8814B(x) | BIT_RARF_RC4_8814B(v))
+
+#define BIT_SHIFT_RARF_RC3_8814B 16
+#define BIT_MASK_RARF_RC3_8814B 0x1f
+#define BIT_RARF_RC3_8814B(x) \
+ (((x) & BIT_MASK_RARF_RC3_8814B) << BIT_SHIFT_RARF_RC3_8814B)
+#define BITS_RARF_RC3_8814B \
+ (BIT_MASK_RARF_RC3_8814B << BIT_SHIFT_RARF_RC3_8814B)
+#define BIT_CLEAR_RARF_RC3_8814B(x) ((x) & (~BITS_RARF_RC3_8814B))
+#define BIT_GET_RARF_RC3_8814B(x) \
+ (((x) >> BIT_SHIFT_RARF_RC3_8814B) & BIT_MASK_RARF_RC3_8814B)
+#define BIT_SET_RARF_RC3_8814B(x, v) \
+ (BIT_CLEAR_RARF_RC3_8814B(x) | BIT_RARF_RC3_8814B(v))
+
+#define BIT_SHIFT_RARF_RC2_8814B 8
+#define BIT_MASK_RARF_RC2_8814B 0x1f
+#define BIT_RARF_RC2_8814B(x) \
+ (((x) & BIT_MASK_RARF_RC2_8814B) << BIT_SHIFT_RARF_RC2_8814B)
+#define BITS_RARF_RC2_8814B \
+ (BIT_MASK_RARF_RC2_8814B << BIT_SHIFT_RARF_RC2_8814B)
+#define BIT_CLEAR_RARF_RC2_8814B(x) ((x) & (~BITS_RARF_RC2_8814B))
+#define BIT_GET_RARF_RC2_8814B(x) \
+ (((x) >> BIT_SHIFT_RARF_RC2_8814B) & BIT_MASK_RARF_RC2_8814B)
+#define BIT_SET_RARF_RC2_8814B(x, v) \
+ (BIT_CLEAR_RARF_RC2_8814B(x) | BIT_RARF_RC2_8814B(v))
+
+#define BIT_SHIFT_RARF_RC1_8814B 0
+#define BIT_MASK_RARF_RC1_8814B 0x1f
+#define BIT_RARF_RC1_8814B(x) \
+ (((x) & BIT_MASK_RARF_RC1_8814B) << BIT_SHIFT_RARF_RC1_8814B)
+#define BITS_RARF_RC1_8814B \
+ (BIT_MASK_RARF_RC1_8814B << BIT_SHIFT_RARF_RC1_8814B)
+#define BIT_CLEAR_RARF_RC1_8814B(x) ((x) & (~BITS_RARF_RC1_8814B))
+#define BIT_GET_RARF_RC1_8814B(x) \
+ (((x) >> BIT_SHIFT_RARF_RC1_8814B) & BIT_MASK_RARF_RC1_8814B)
+#define BIT_SET_RARF_RC1_8814B(x, v) \
+ (BIT_CLEAR_RARF_RC1_8814B(x) | BIT_RARF_RC1_8814B(v))
+
+/* 2 REG_RARFRCH_8814B */
+
+#define BIT_SHIFT_RARF_RC8_V1_8814B 24
+#define BIT_MASK_RARF_RC8_V1_8814B 0x1f
+#define BIT_RARF_RC8_V1_8814B(x) \
+ (((x) & BIT_MASK_RARF_RC8_V1_8814B) << BIT_SHIFT_RARF_RC8_V1_8814B)
+#define BITS_RARF_RC8_V1_8814B \
+ (BIT_MASK_RARF_RC8_V1_8814B << BIT_SHIFT_RARF_RC8_V1_8814B)
+#define BIT_CLEAR_RARF_RC8_V1_8814B(x) ((x) & (~BITS_RARF_RC8_V1_8814B))
+#define BIT_GET_RARF_RC8_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_RARF_RC8_V1_8814B) & BIT_MASK_RARF_RC8_V1_8814B)
+#define BIT_SET_RARF_RC8_V1_8814B(x, v) \
+ (BIT_CLEAR_RARF_RC8_V1_8814B(x) | BIT_RARF_RC8_V1_8814B(v))
+
+#define BIT_SHIFT_RARF_RC7_V1_8814B 16
+#define BIT_MASK_RARF_RC7_V1_8814B 0x1f
+#define BIT_RARF_RC7_V1_8814B(x) \
+ (((x) & BIT_MASK_RARF_RC7_V1_8814B) << BIT_SHIFT_RARF_RC7_V1_8814B)
+#define BITS_RARF_RC7_V1_8814B \
+ (BIT_MASK_RARF_RC7_V1_8814B << BIT_SHIFT_RARF_RC7_V1_8814B)
+#define BIT_CLEAR_RARF_RC7_V1_8814B(x) ((x) & (~BITS_RARF_RC7_V1_8814B))
+#define BIT_GET_RARF_RC7_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_RARF_RC7_V1_8814B) & BIT_MASK_RARF_RC7_V1_8814B)
+#define BIT_SET_RARF_RC7_V1_8814B(x, v) \
+ (BIT_CLEAR_RARF_RC7_V1_8814B(x) | BIT_RARF_RC7_V1_8814B(v))
+
+#define BIT_SHIFT_RARF_RC6_V1_8814B 8
+#define BIT_MASK_RARF_RC6_V1_8814B 0x1f
+#define BIT_RARF_RC6_V1_8814B(x) \
+ (((x) & BIT_MASK_RARF_RC6_V1_8814B) << BIT_SHIFT_RARF_RC6_V1_8814B)
+#define BITS_RARF_RC6_V1_8814B \
+ (BIT_MASK_RARF_RC6_V1_8814B << BIT_SHIFT_RARF_RC6_V1_8814B)
+#define BIT_CLEAR_RARF_RC6_V1_8814B(x) ((x) & (~BITS_RARF_RC6_V1_8814B))
+#define BIT_GET_RARF_RC6_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_RARF_RC6_V1_8814B) & BIT_MASK_RARF_RC6_V1_8814B)
+#define BIT_SET_RARF_RC6_V1_8814B(x, v) \
+ (BIT_CLEAR_RARF_RC6_V1_8814B(x) | BIT_RARF_RC6_V1_8814B(v))
+
+#define BIT_SHIFT_RARF_RC5_V1_8814B 0
+#define BIT_MASK_RARF_RC5_V1_8814B 0x1f
+#define BIT_RARF_RC5_V1_8814B(x) \
+ (((x) & BIT_MASK_RARF_RC5_V1_8814B) << BIT_SHIFT_RARF_RC5_V1_8814B)
+#define BITS_RARF_RC5_V1_8814B \
+ (BIT_MASK_RARF_RC5_V1_8814B << BIT_SHIFT_RARF_RC5_V1_8814B)
+#define BIT_CLEAR_RARF_RC5_V1_8814B(x) ((x) & (~BITS_RARF_RC5_V1_8814B))
+#define BIT_GET_RARF_RC5_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_RARF_RC5_V1_8814B) & BIT_MASK_RARF_RC5_V1_8814B)
+#define BIT_SET_RARF_RC5_V1_8814B(x, v) \
+ (BIT_CLEAR_RARF_RC5_V1_8814B(x) | BIT_RARF_RC5_V1_8814B(v))
+
+/* 2 REG_RRSR_8814B */
+
+#define BIT_SHIFT_RRSR_RSC_8814B 21
+#define BIT_MASK_RRSR_RSC_8814B 0x3
+#define BIT_RRSR_RSC_8814B(x) \
+ (((x) & BIT_MASK_RRSR_RSC_8814B) << BIT_SHIFT_RRSR_RSC_8814B)
+#define BITS_RRSR_RSC_8814B \
+ (BIT_MASK_RRSR_RSC_8814B << BIT_SHIFT_RRSR_RSC_8814B)
+#define BIT_CLEAR_RRSR_RSC_8814B(x) ((x) & (~BITS_RRSR_RSC_8814B))
+#define BIT_GET_RRSR_RSC_8814B(x) \
+ (((x) >> BIT_SHIFT_RRSR_RSC_8814B) & BIT_MASK_RRSR_RSC_8814B)
+#define BIT_SET_RRSR_RSC_8814B(x, v) \
+ (BIT_CLEAR_RRSR_RSC_8814B(x) | BIT_RRSR_RSC_8814B(v))
+
+#define BIT_SHIFT_RRSC_BITMAP_8814B 0
+#define BIT_MASK_RRSC_BITMAP_8814B 0xfffff
+#define BIT_RRSC_BITMAP_8814B(x) \
+ (((x) & BIT_MASK_RRSC_BITMAP_8814B) << BIT_SHIFT_RRSC_BITMAP_8814B)
+#define BITS_RRSC_BITMAP_8814B \
+ (BIT_MASK_RRSC_BITMAP_8814B << BIT_SHIFT_RRSC_BITMAP_8814B)
+#define BIT_CLEAR_RRSC_BITMAP_8814B(x) ((x) & (~BITS_RRSC_BITMAP_8814B))
+#define BIT_GET_RRSC_BITMAP_8814B(x) \
+ (((x) >> BIT_SHIFT_RRSC_BITMAP_8814B) & BIT_MASK_RRSC_BITMAP_8814B)
+#define BIT_SET_RRSC_BITMAP_8814B(x, v) \
+ (BIT_CLEAR_RRSC_BITMAP_8814B(x) | BIT_RRSC_BITMAP_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_ARFR0_8814B */
+
+#define BIT_SHIFT_ARFRL0_8814B 0
+#define BIT_MASK_ARFRL0_8814B 0xffffffffL
+#define BIT_ARFRL0_8814B(x) \
+ (((x) & BIT_MASK_ARFRL0_8814B) << BIT_SHIFT_ARFRL0_8814B)
+#define BITS_ARFRL0_8814B (BIT_MASK_ARFRL0_8814B << BIT_SHIFT_ARFRL0_8814B)
+#define BIT_CLEAR_ARFRL0_8814B(x) ((x) & (~BITS_ARFRL0_8814B))
+#define BIT_GET_ARFRL0_8814B(x) \
+ (((x) >> BIT_SHIFT_ARFRL0_8814B) & BIT_MASK_ARFRL0_8814B)
+#define BIT_SET_ARFRL0_8814B(x, v) \
+ (BIT_CLEAR_ARFRL0_8814B(x) | BIT_ARFRL0_8814B(v))
+
+/* 2 REG_ARFRH0_8814B */
+
+#define BIT_SHIFT_ARFRH0_8814B 0
+#define BIT_MASK_ARFRH0_8814B 0xffffffffL
+#define BIT_ARFRH0_8814B(x) \
+ (((x) & BIT_MASK_ARFRH0_8814B) << BIT_SHIFT_ARFRH0_8814B)
+#define BITS_ARFRH0_8814B (BIT_MASK_ARFRH0_8814B << BIT_SHIFT_ARFRH0_8814B)
+#define BIT_CLEAR_ARFRH0_8814B(x) ((x) & (~BITS_ARFRH0_8814B))
+#define BIT_GET_ARFRH0_8814B(x) \
+ (((x) >> BIT_SHIFT_ARFRH0_8814B) & BIT_MASK_ARFRH0_8814B)
+#define BIT_SET_ARFRH0_8814B(x, v) \
+ (BIT_CLEAR_ARFRH0_8814B(x) | BIT_ARFRH0_8814B(v))
+
+/* 2 REG_REG_ARFR_WT0_8814B */
+
+#define BIT_SHIFT_RATE7_WEIGHTING_8814B 28
+#define BIT_MASK_RATE7_WEIGHTING_8814B 0xf
+#define BIT_RATE7_WEIGHTING_8814B(x) \
+ (((x) & BIT_MASK_RATE7_WEIGHTING_8814B) \
+ << BIT_SHIFT_RATE7_WEIGHTING_8814B)
+#define BITS_RATE7_WEIGHTING_8814B \
+ (BIT_MASK_RATE7_WEIGHTING_8814B << BIT_SHIFT_RATE7_WEIGHTING_8814B)
+#define BIT_CLEAR_RATE7_WEIGHTING_8814B(x) ((x) & (~BITS_RATE7_WEIGHTING_8814B))
+#define BIT_GET_RATE7_WEIGHTING_8814B(x) \
+ (((x) >> BIT_SHIFT_RATE7_WEIGHTING_8814B) & \
+ BIT_MASK_RATE7_WEIGHTING_8814B)
+#define BIT_SET_RATE7_WEIGHTING_8814B(x, v) \
+ (BIT_CLEAR_RATE7_WEIGHTING_8814B(x) | BIT_RATE7_WEIGHTING_8814B(v))
+
+#define BIT_SHIFT_RATE6_WEIGHTING_8814B 24
+#define BIT_MASK_RATE6_WEIGHTING_8814B 0xf
+#define BIT_RATE6_WEIGHTING_8814B(x) \
+ (((x) & BIT_MASK_RATE6_WEIGHTING_8814B) \
+ << BIT_SHIFT_RATE6_WEIGHTING_8814B)
+#define BITS_RATE6_WEIGHTING_8814B \
+ (BIT_MASK_RATE6_WEIGHTING_8814B << BIT_SHIFT_RATE6_WEIGHTING_8814B)
+#define BIT_CLEAR_RATE6_WEIGHTING_8814B(x) ((x) & (~BITS_RATE6_WEIGHTING_8814B))
+#define BIT_GET_RATE6_WEIGHTING_8814B(x) \
+ (((x) >> BIT_SHIFT_RATE6_WEIGHTING_8814B) & \
+ BIT_MASK_RATE6_WEIGHTING_8814B)
+#define BIT_SET_RATE6_WEIGHTING_8814B(x, v) \
+ (BIT_CLEAR_RATE6_WEIGHTING_8814B(x) | BIT_RATE6_WEIGHTING_8814B(v))
+
+#define BIT_SHIFT_RATE5_WEIGHTING_8814B 20
+#define BIT_MASK_RATE5_WEIGHTING_8814B 0xf
+#define BIT_RATE5_WEIGHTING_8814B(x) \
+ (((x) & BIT_MASK_RATE5_WEIGHTING_8814B) \
+ << BIT_SHIFT_RATE5_WEIGHTING_8814B)
+#define BITS_RATE5_WEIGHTING_8814B \
+ (BIT_MASK_RATE5_WEIGHTING_8814B << BIT_SHIFT_RATE5_WEIGHTING_8814B)
+#define BIT_CLEAR_RATE5_WEIGHTING_8814B(x) ((x) & (~BITS_RATE5_WEIGHTING_8814B))
+#define BIT_GET_RATE5_WEIGHTING_8814B(x) \
+ (((x) >> BIT_SHIFT_RATE5_WEIGHTING_8814B) & \
+ BIT_MASK_RATE5_WEIGHTING_8814B)
+#define BIT_SET_RATE5_WEIGHTING_8814B(x, v) \
+ (BIT_CLEAR_RATE5_WEIGHTING_8814B(x) | BIT_RATE5_WEIGHTING_8814B(v))
+
+#define BIT_SHIFT_RATE4_WEIGHTING_8814B 16
+#define BIT_MASK_RATE4_WEIGHTING_8814B 0xf
+#define BIT_RATE4_WEIGHTING_8814B(x) \
+ (((x) & BIT_MASK_RATE4_WEIGHTING_8814B) \
+ << BIT_SHIFT_RATE4_WEIGHTING_8814B)
+#define BITS_RATE4_WEIGHTING_8814B \
+ (BIT_MASK_RATE4_WEIGHTING_8814B << BIT_SHIFT_RATE4_WEIGHTING_8814B)
+#define BIT_CLEAR_RATE4_WEIGHTING_8814B(x) ((x) & (~BITS_RATE4_WEIGHTING_8814B))
+#define BIT_GET_RATE4_WEIGHTING_8814B(x) \
+ (((x) >> BIT_SHIFT_RATE4_WEIGHTING_8814B) & \
+ BIT_MASK_RATE4_WEIGHTING_8814B)
+#define BIT_SET_RATE4_WEIGHTING_8814B(x, v) \
+ (BIT_CLEAR_RATE4_WEIGHTING_8814B(x) | BIT_RATE4_WEIGHTING_8814B(v))
+
+#define BIT_SHIFT_RATE3_WEIGHTING_8814B 12
+#define BIT_MASK_RATE3_WEIGHTING_8814B 0xf
+#define BIT_RATE3_WEIGHTING_8814B(x) \
+ (((x) & BIT_MASK_RATE3_WEIGHTING_8814B) \
+ << BIT_SHIFT_RATE3_WEIGHTING_8814B)
+#define BITS_RATE3_WEIGHTING_8814B \
+ (BIT_MASK_RATE3_WEIGHTING_8814B << BIT_SHIFT_RATE3_WEIGHTING_8814B)
+#define BIT_CLEAR_RATE3_WEIGHTING_8814B(x) ((x) & (~BITS_RATE3_WEIGHTING_8814B))
+#define BIT_GET_RATE3_WEIGHTING_8814B(x) \
+ (((x) >> BIT_SHIFT_RATE3_WEIGHTING_8814B) & \
+ BIT_MASK_RATE3_WEIGHTING_8814B)
+#define BIT_SET_RATE3_WEIGHTING_8814B(x, v) \
+ (BIT_CLEAR_RATE3_WEIGHTING_8814B(x) | BIT_RATE3_WEIGHTING_8814B(v))
+
+#define BIT_SHIFT_RATE2_WEIGHTING_8814B 8
+#define BIT_MASK_RATE2_WEIGHTING_8814B 0xf
+#define BIT_RATE2_WEIGHTING_8814B(x) \
+ (((x) & BIT_MASK_RATE2_WEIGHTING_8814B) \
+ << BIT_SHIFT_RATE2_WEIGHTING_8814B)
+#define BITS_RATE2_WEIGHTING_8814B \
+ (BIT_MASK_RATE2_WEIGHTING_8814B << BIT_SHIFT_RATE2_WEIGHTING_8814B)
+#define BIT_CLEAR_RATE2_WEIGHTING_8814B(x) ((x) & (~BITS_RATE2_WEIGHTING_8814B))
+#define BIT_GET_RATE2_WEIGHTING_8814B(x) \
+ (((x) >> BIT_SHIFT_RATE2_WEIGHTING_8814B) & \
+ BIT_MASK_RATE2_WEIGHTING_8814B)
+#define BIT_SET_RATE2_WEIGHTING_8814B(x, v) \
+ (BIT_CLEAR_RATE2_WEIGHTING_8814B(x) | BIT_RATE2_WEIGHTING_8814B(v))
+
+#define BIT_SHIFT_RATE1_WEIGHTING_8814B 4
+#define BIT_MASK_RATE1_WEIGHTING_8814B 0xf
+#define BIT_RATE1_WEIGHTING_8814B(x) \
+ (((x) & BIT_MASK_RATE1_WEIGHTING_8814B) \
+ << BIT_SHIFT_RATE1_WEIGHTING_8814B)
+#define BITS_RATE1_WEIGHTING_8814B \
+ (BIT_MASK_RATE1_WEIGHTING_8814B << BIT_SHIFT_RATE1_WEIGHTING_8814B)
+#define BIT_CLEAR_RATE1_WEIGHTING_8814B(x) ((x) & (~BITS_RATE1_WEIGHTING_8814B))
+#define BIT_GET_RATE1_WEIGHTING_8814B(x) \
+ (((x) >> BIT_SHIFT_RATE1_WEIGHTING_8814B) & \
+ BIT_MASK_RATE1_WEIGHTING_8814B)
+#define BIT_SET_RATE1_WEIGHTING_8814B(x, v) \
+ (BIT_CLEAR_RATE1_WEIGHTING_8814B(x) | BIT_RATE1_WEIGHTING_8814B(v))
+
+#define BIT_SHIFT_RATE0_WEIGHTING_8814B 0
+#define BIT_MASK_RATE0_WEIGHTING_8814B 0xf
+#define BIT_RATE0_WEIGHTING_8814B(x) \
+ (((x) & BIT_MASK_RATE0_WEIGHTING_8814B) \
+ << BIT_SHIFT_RATE0_WEIGHTING_8814B)
+#define BITS_RATE0_WEIGHTING_8814B \
+ (BIT_MASK_RATE0_WEIGHTING_8814B << BIT_SHIFT_RATE0_WEIGHTING_8814B)
+#define BIT_CLEAR_RATE0_WEIGHTING_8814B(x) ((x) & (~BITS_RATE0_WEIGHTING_8814B))
+#define BIT_GET_RATE0_WEIGHTING_8814B(x) \
+ (((x) >> BIT_SHIFT_RATE0_WEIGHTING_8814B) & \
+ BIT_MASK_RATE0_WEIGHTING_8814B)
+#define BIT_SET_RATE0_WEIGHTING_8814B(x, v) \
+ (BIT_CLEAR_RATE0_WEIGHTING_8814B(x) | BIT_RATE0_WEIGHTING_8814B(v))
+
+/* 2 REG_REG_ARFR_WT1_8814B */
+
+#define BIT_SHIFT_RATE15_WEIGHTING_8814B 28
+#define BIT_MASK_RATE15_WEIGHTING_8814B 0xf
+#define BIT_RATE15_WEIGHTING_8814B(x) \
+ (((x) & BIT_MASK_RATE15_WEIGHTING_8814B) \
+ << BIT_SHIFT_RATE15_WEIGHTING_8814B)
+#define BITS_RATE15_WEIGHTING_8814B \
+ (BIT_MASK_RATE15_WEIGHTING_8814B << BIT_SHIFT_RATE15_WEIGHTING_8814B)
+#define BIT_CLEAR_RATE15_WEIGHTING_8814B(x) \
+ ((x) & (~BITS_RATE15_WEIGHTING_8814B))
+#define BIT_GET_RATE15_WEIGHTING_8814B(x) \
+ (((x) >> BIT_SHIFT_RATE15_WEIGHTING_8814B) & \
+ BIT_MASK_RATE15_WEIGHTING_8814B)
+#define BIT_SET_RATE15_WEIGHTING_8814B(x, v) \
+ (BIT_CLEAR_RATE15_WEIGHTING_8814B(x) | BIT_RATE15_WEIGHTING_8814B(v))
+
+#define BIT_SHIFT_RATE14_WEIGHTING_8814B 24
+#define BIT_MASK_RATE14_WEIGHTING_8814B 0xf
+#define BIT_RATE14_WEIGHTING_8814B(x) \
+ (((x) & BIT_MASK_RATE14_WEIGHTING_8814B) \
+ << BIT_SHIFT_RATE14_WEIGHTING_8814B)
+#define BITS_RATE14_WEIGHTING_8814B \
+ (BIT_MASK_RATE14_WEIGHTING_8814B << BIT_SHIFT_RATE14_WEIGHTING_8814B)
+#define BIT_CLEAR_RATE14_WEIGHTING_8814B(x) \
+ ((x) & (~BITS_RATE14_WEIGHTING_8814B))
+#define BIT_GET_RATE14_WEIGHTING_8814B(x) \
+ (((x) >> BIT_SHIFT_RATE14_WEIGHTING_8814B) & \
+ BIT_MASK_RATE14_WEIGHTING_8814B)
+#define BIT_SET_RATE14_WEIGHTING_8814B(x, v) \
+ (BIT_CLEAR_RATE14_WEIGHTING_8814B(x) | BIT_RATE14_WEIGHTING_8814B(v))
+
+#define BIT_SHIFT_RATE13_WEIGHTING_8814B 20
+#define BIT_MASK_RATE13_WEIGHTING_8814B 0xf
+#define BIT_RATE13_WEIGHTING_8814B(x) \
+ (((x) & BIT_MASK_RATE13_WEIGHTING_8814B) \
+ << BIT_SHIFT_RATE13_WEIGHTING_8814B)
+#define BITS_RATE13_WEIGHTING_8814B \
+ (BIT_MASK_RATE13_WEIGHTING_8814B << BIT_SHIFT_RATE13_WEIGHTING_8814B)
+#define BIT_CLEAR_RATE13_WEIGHTING_8814B(x) \
+ ((x) & (~BITS_RATE13_WEIGHTING_8814B))
+#define BIT_GET_RATE13_WEIGHTING_8814B(x) \
+ (((x) >> BIT_SHIFT_RATE13_WEIGHTING_8814B) & \
+ BIT_MASK_RATE13_WEIGHTING_8814B)
+#define BIT_SET_RATE13_WEIGHTING_8814B(x, v) \
+ (BIT_CLEAR_RATE13_WEIGHTING_8814B(x) | BIT_RATE13_WEIGHTING_8814B(v))
+
+#define BIT_SHIFT_RATE12_WEIGHTING_8814B 16
+#define BIT_MASK_RATE12_WEIGHTING_8814B 0xf
+#define BIT_RATE12_WEIGHTING_8814B(x) \
+ (((x) & BIT_MASK_RATE12_WEIGHTING_8814B) \
+ << BIT_SHIFT_RATE12_WEIGHTING_8814B)
+#define BITS_RATE12_WEIGHTING_8814B \
+ (BIT_MASK_RATE12_WEIGHTING_8814B << BIT_SHIFT_RATE12_WEIGHTING_8814B)
+#define BIT_CLEAR_RATE12_WEIGHTING_8814B(x) \
+ ((x) & (~BITS_RATE12_WEIGHTING_8814B))
+#define BIT_GET_RATE12_WEIGHTING_8814B(x) \
+ (((x) >> BIT_SHIFT_RATE12_WEIGHTING_8814B) & \
+ BIT_MASK_RATE12_WEIGHTING_8814B)
+#define BIT_SET_RATE12_WEIGHTING_8814B(x, v) \
+ (BIT_CLEAR_RATE12_WEIGHTING_8814B(x) | BIT_RATE12_WEIGHTING_8814B(v))
+
+#define BIT_SHIFT_RATE11_WEIGHTING_8814B 12
+#define BIT_MASK_RATE11_WEIGHTING_8814B 0xf
+#define BIT_RATE11_WEIGHTING_8814B(x) \
+ (((x) & BIT_MASK_RATE11_WEIGHTING_8814B) \
+ << BIT_SHIFT_RATE11_WEIGHTING_8814B)
+#define BITS_RATE11_WEIGHTING_8814B \
+ (BIT_MASK_RATE11_WEIGHTING_8814B << BIT_SHIFT_RATE11_WEIGHTING_8814B)
+#define BIT_CLEAR_RATE11_WEIGHTING_8814B(x) \
+ ((x) & (~BITS_RATE11_WEIGHTING_8814B))
+#define BIT_GET_RATE11_WEIGHTING_8814B(x) \
+ (((x) >> BIT_SHIFT_RATE11_WEIGHTING_8814B) & \
+ BIT_MASK_RATE11_WEIGHTING_8814B)
+#define BIT_SET_RATE11_WEIGHTING_8814B(x, v) \
+ (BIT_CLEAR_RATE11_WEIGHTING_8814B(x) | BIT_RATE11_WEIGHTING_8814B(v))
+
+#define BIT_SHIFT_RATE10_WEIGHTING_8814B 8
+#define BIT_MASK_RATE10_WEIGHTING_8814B 0xf
+#define BIT_RATE10_WEIGHTING_8814B(x) \
+ (((x) & BIT_MASK_RATE10_WEIGHTING_8814B) \
+ << BIT_SHIFT_RATE10_WEIGHTING_8814B)
+#define BITS_RATE10_WEIGHTING_8814B \
+ (BIT_MASK_RATE10_WEIGHTING_8814B << BIT_SHIFT_RATE10_WEIGHTING_8814B)
+#define BIT_CLEAR_RATE10_WEIGHTING_8814B(x) \
+ ((x) & (~BITS_RATE10_WEIGHTING_8814B))
+#define BIT_GET_RATE10_WEIGHTING_8814B(x) \
+ (((x) >> BIT_SHIFT_RATE10_WEIGHTING_8814B) & \
+ BIT_MASK_RATE10_WEIGHTING_8814B)
+#define BIT_SET_RATE10_WEIGHTING_8814B(x, v) \
+ (BIT_CLEAR_RATE10_WEIGHTING_8814B(x) | BIT_RATE10_WEIGHTING_8814B(v))
+
+#define BIT_SHIFT_RATE9_WEIGHTING_8814B 4
+#define BIT_MASK_RATE9_WEIGHTING_8814B 0xf
+#define BIT_RATE9_WEIGHTING_8814B(x) \
+ (((x) & BIT_MASK_RATE9_WEIGHTING_8814B) \
+ << BIT_SHIFT_RATE9_WEIGHTING_8814B)
+#define BITS_RATE9_WEIGHTING_8814B \
+ (BIT_MASK_RATE9_WEIGHTING_8814B << BIT_SHIFT_RATE9_WEIGHTING_8814B)
+#define BIT_CLEAR_RATE9_WEIGHTING_8814B(x) ((x) & (~BITS_RATE9_WEIGHTING_8814B))
+#define BIT_GET_RATE9_WEIGHTING_8814B(x) \
+ (((x) >> BIT_SHIFT_RATE9_WEIGHTING_8814B) & \
+ BIT_MASK_RATE9_WEIGHTING_8814B)
+#define BIT_SET_RATE9_WEIGHTING_8814B(x, v) \
+ (BIT_CLEAR_RATE9_WEIGHTING_8814B(x) | BIT_RATE9_WEIGHTING_8814B(v))
+
+#define BIT_SHIFT_RATE8_WEIGHTING_8814B 0
+#define BIT_MASK_RATE8_WEIGHTING_8814B 0xf
+#define BIT_RATE8_WEIGHTING_8814B(x) \
+ (((x) & BIT_MASK_RATE8_WEIGHTING_8814B) \
+ << BIT_SHIFT_RATE8_WEIGHTING_8814B)
+#define BITS_RATE8_WEIGHTING_8814B \
+ (BIT_MASK_RATE8_WEIGHTING_8814B << BIT_SHIFT_RATE8_WEIGHTING_8814B)
+#define BIT_CLEAR_RATE8_WEIGHTING_8814B(x) ((x) & (~BITS_RATE8_WEIGHTING_8814B))
+#define BIT_GET_RATE8_WEIGHTING_8814B(x) \
+ (((x) >> BIT_SHIFT_RATE8_WEIGHTING_8814B) & \
+ BIT_MASK_RATE8_WEIGHTING_8814B)
+#define BIT_SET_RATE8_WEIGHTING_8814B(x, v) \
+ (BIT_CLEAR_RATE8_WEIGHTING_8814B(x) | BIT_RATE8_WEIGHTING_8814B(v))
+
+/* 2 REG_CCK_CHECK_8814B */
+#define BIT_CHECK_CCK_EN_8814B BIT(7)
+#define BIT_EN_BCN_PKT_REL_P0_8814B BIT(6)
+#define BIT_BCN_PORT_SEL_8814B BIT(5)
+#define BIT_MOREDATA_BYPASS_8814B BIT(4)
+#define BIT_EN_CLR_CMD_REL_BCN_PKT_P0_8814B BIT(3)
+#define BIT_EN_SET_MOREDATA_8814B BIT(2)
+#define BIT__R_DIS_CLEAR_MACID_RELEASE_8814B BIT(1)
+#define BIT__R_MACID_RELEASE_EN_8814B BIT(0)
+
+/* 2 REG_AMPDU_MAX_TIME_V1_8814B */
+
+#define BIT_SHIFT_AMPDU_MAX_TIME_8814B 0
+#define BIT_MASK_AMPDU_MAX_TIME_8814B 0xff
+#define BIT_AMPDU_MAX_TIME_8814B(x) \
+ (((x) & BIT_MASK_AMPDU_MAX_TIME_8814B) \
+ << BIT_SHIFT_AMPDU_MAX_TIME_8814B)
+#define BITS_AMPDU_MAX_TIME_8814B \
+ (BIT_MASK_AMPDU_MAX_TIME_8814B << BIT_SHIFT_AMPDU_MAX_TIME_8814B)
+#define BIT_CLEAR_AMPDU_MAX_TIME_8814B(x) ((x) & (~BITS_AMPDU_MAX_TIME_8814B))
+#define BIT_GET_AMPDU_MAX_TIME_8814B(x) \
+ (((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8814B) & \
+ BIT_MASK_AMPDU_MAX_TIME_8814B)
+#define BIT_SET_AMPDU_MAX_TIME_8814B(x, v) \
+ (BIT_CLEAR_AMPDU_MAX_TIME_8814B(x) | BIT_AMPDU_MAX_TIME_8814B(v))
+
+/* 2 REG_TAB_SEL_8814B */
+
+#define BIT_SHIFT_RATE_SEL_8814B 0
+#define BIT_MASK_RATE_SEL_8814B 0xf
+#define BIT_RATE_SEL_8814B(x) \
+ (((x) & BIT_MASK_RATE_SEL_8814B) << BIT_SHIFT_RATE_SEL_8814B)
+#define BITS_RATE_SEL_8814B \
+ (BIT_MASK_RATE_SEL_8814B << BIT_SHIFT_RATE_SEL_8814B)
+#define BIT_CLEAR_RATE_SEL_8814B(x) ((x) & (~BITS_RATE_SEL_8814B))
+#define BIT_GET_RATE_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_RATE_SEL_8814B) & BIT_MASK_RATE_SEL_8814B)
+#define BIT_SET_RATE_SEL_8814B(x, v) \
+ (BIT_CLEAR_RATE_SEL_8814B(x) | BIT_RATE_SEL_8814B(v))
+
+/* 2 REG_BCN_INVALID_CTRL_8814B */
+#define BIT_EN_CLR_CMD_REL_BCN_PKT_P4_8814B BIT(7)
+#define BIT_EN_BCN_PKT_REL_P4_8814B BIT(6)
+#define BIT_EN_CLR_CMD_REL_BCN_PKT_P3_8814B BIT(5)
+#define BIT_EN_BCN_PKT_REL_P3_8814B BIT(4)
+#define BIT_EN_CLR_CMD_REL_BCN_PKT_P2_8814B BIT(3)
+#define BIT_EN_BCN_PKT_REL_P2_8814B BIT(2)
+#define BIT_EN_CLR_CMD_REL_BCN_PKT_P1_8814B BIT(1)
+#define BIT_EN_BCN_PKT_REL_P1_8814B BIT(0)
+
+/* 2 REG_AMPDU_MAX_LENGTH_HT_8814B */
+
+#define BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8814B 0
+#define BIT_MASK_AMPDU_MAX_LENGTH_HT_8814B 0xffff
+#define BIT_AMPDU_MAX_LENGTH_HT_8814B(x) \
+ (((x) & BIT_MASK_AMPDU_MAX_LENGTH_HT_8814B) \
+ << BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8814B)
+#define BITS_AMPDU_MAX_LENGTH_HT_8814B \
+ (BIT_MASK_AMPDU_MAX_LENGTH_HT_8814B \
+ << BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8814B)
+#define BIT_CLEAR_AMPDU_MAX_LENGTH_HT_8814B(x) \
+ ((x) & (~BITS_AMPDU_MAX_LENGTH_HT_8814B))
+#define BIT_GET_AMPDU_MAX_LENGTH_HT_8814B(x) \
+ (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8814B) & \
+ BIT_MASK_AMPDU_MAX_LENGTH_HT_8814B)
+#define BIT_SET_AMPDU_MAX_LENGTH_HT_8814B(x, v) \
+ (BIT_CLEAR_AMPDU_MAX_LENGTH_HT_8814B(x) | \
+ BIT_AMPDU_MAX_LENGTH_HT_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NDPA_RATE_8814B */
+
+#define BIT_SHIFT_R_NDPA_RATE_V1_8814B 0
+#define BIT_MASK_R_NDPA_RATE_V1_8814B 0xff
+#define BIT_R_NDPA_RATE_V1_8814B(x) \
+ (((x) & BIT_MASK_R_NDPA_RATE_V1_8814B) \
+ << BIT_SHIFT_R_NDPA_RATE_V1_8814B)
+#define BITS_R_NDPA_RATE_V1_8814B \
+ (BIT_MASK_R_NDPA_RATE_V1_8814B << BIT_SHIFT_R_NDPA_RATE_V1_8814B)
+#define BIT_CLEAR_R_NDPA_RATE_V1_8814B(x) ((x) & (~BITS_R_NDPA_RATE_V1_8814B))
+#define BIT_GET_R_NDPA_RATE_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8814B) & \
+ BIT_MASK_R_NDPA_RATE_V1_8814B)
+#define BIT_SET_R_NDPA_RATE_V1_8814B(x, v) \
+ (BIT_CLEAR_R_NDPA_RATE_V1_8814B(x) | BIT_R_NDPA_RATE_V1_8814B(v))
+
+/* 2 REG_TX_HANG_CTRL_8814B */
+#define BIT_EN_GNT_BT_AWAKE_8814B BIT(3)
+#define BIT_EN_EOF_V1_8814B BIT(2)
+#define BIT_DIS_OQT_BLOCK_8814B BIT(1)
+#define BIT_SEARCH_QUEUE_EN_8814B BIT(0)
+
+/* 2 REG_NDPA_OPT_CTRL_8814B */
+#define BIT_DIS_MACID_RELEASE_RTY_8814B BIT(5)
+
+#define BIT_SHIFT_BW_SIGTA_8814B 3
+#define BIT_MASK_BW_SIGTA_8814B 0x3
+#define BIT_BW_SIGTA_8814B(x) \
+ (((x) & BIT_MASK_BW_SIGTA_8814B) << BIT_SHIFT_BW_SIGTA_8814B)
+#define BITS_BW_SIGTA_8814B \
+ (BIT_MASK_BW_SIGTA_8814B << BIT_SHIFT_BW_SIGTA_8814B)
+#define BIT_CLEAR_BW_SIGTA_8814B(x) ((x) & (~BITS_BW_SIGTA_8814B))
+#define BIT_GET_BW_SIGTA_8814B(x) \
+ (((x) >> BIT_SHIFT_BW_SIGTA_8814B) & BIT_MASK_BW_SIGTA_8814B)
+#define BIT_SET_BW_SIGTA_8814B(x, v) \
+ (BIT_CLEAR_BW_SIGTA_8814B(x) | BIT_BW_SIGTA_8814B(v))
+
+#define BIT_EN_BAR_SIGTA_8814B BIT(2)
+
+#define BIT_SHIFT_NDPA_BW_8814B 0
+#define BIT_MASK_NDPA_BW_8814B 0x3
+#define BIT_NDPA_BW_8814B(x) \
+ (((x) & BIT_MASK_NDPA_BW_8814B) << BIT_SHIFT_NDPA_BW_8814B)
+#define BITS_NDPA_BW_8814B (BIT_MASK_NDPA_BW_8814B << BIT_SHIFT_NDPA_BW_8814B)
+#define BIT_CLEAR_NDPA_BW_8814B(x) ((x) & (~BITS_NDPA_BW_8814B))
+#define BIT_GET_NDPA_BW_8814B(x) \
+ (((x) >> BIT_SHIFT_NDPA_BW_8814B) & BIT_MASK_NDPA_BW_8814B)
+#define BIT_SET_NDPA_BW_8814B(x, v) \
+ (BIT_CLEAR_NDPA_BW_8814B(x) | BIT_NDPA_BW_8814B(v))
+
+/* 2 REG_AMPDU_MAX_LENGTH_VHT_8814B */
+
+#define BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_8814B 0
+#define BIT_MASK_AMPDU_MAX_LENGTH_VHT_8814B 0x3ffff
+#define BIT_AMPDU_MAX_LENGTH_VHT_8814B(x) \
+ (((x) & BIT_MASK_AMPDU_MAX_LENGTH_VHT_8814B) \
+ << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_8814B)
+#define BITS_AMPDU_MAX_LENGTH_VHT_8814B \
+ (BIT_MASK_AMPDU_MAX_LENGTH_VHT_8814B \
+ << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_8814B)
+#define BIT_CLEAR_AMPDU_MAX_LENGTH_VHT_8814B(x) \
+ ((x) & (~BITS_AMPDU_MAX_LENGTH_VHT_8814B))
+#define BIT_GET_AMPDU_MAX_LENGTH_VHT_8814B(x) \
+ (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_8814B) & \
+ BIT_MASK_AMPDU_MAX_LENGTH_VHT_8814B)
+#define BIT_SET_AMPDU_MAX_LENGTH_VHT_8814B(x, v) \
+ (BIT_CLEAR_AMPDU_MAX_LENGTH_VHT_8814B(x) | \
+ BIT_AMPDU_MAX_LENGTH_VHT_8814B(v))
+
+/* 2 REG_RD_RESP_PKT_TH_8814B */
+
+#define BIT_SHIFT_RD_RESP_PKT_TH_V1_8814B 0
+#define BIT_MASK_RD_RESP_PKT_TH_V1_8814B 0x3f
+#define BIT_RD_RESP_PKT_TH_V1_8814B(x) \
+ (((x) & BIT_MASK_RD_RESP_PKT_TH_V1_8814B) \
+ << BIT_SHIFT_RD_RESP_PKT_TH_V1_8814B)
+#define BITS_RD_RESP_PKT_TH_V1_8814B \
+ (BIT_MASK_RD_RESP_PKT_TH_V1_8814B << BIT_SHIFT_RD_RESP_PKT_TH_V1_8814B)
+#define BIT_CLEAR_RD_RESP_PKT_TH_V1_8814B(x) \
+ ((x) & (~BITS_RD_RESP_PKT_TH_V1_8814B))
+#define BIT_GET_RD_RESP_PKT_TH_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8814B) & \
+ BIT_MASK_RD_RESP_PKT_TH_V1_8814B)
+#define BIT_SET_RD_RESP_PKT_TH_V1_8814B(x, v) \
+ (BIT_CLEAR_RD_RESP_PKT_TH_V1_8814B(x) | BIT_RD_RESP_PKT_TH_V1_8814B(v))
+
+/* 2 REG_NEW_EDCA_CTRL_V1_8814B */
+
+#define BIT_SHIFT_RANDOM_VALUE_SHIFT_8814B 9
+#define BIT_MASK_RANDOM_VALUE_SHIFT_8814B 0x7
+#define BIT_RANDOM_VALUE_SHIFT_8814B(x) \
+ (((x) & BIT_MASK_RANDOM_VALUE_SHIFT_8814B) \
+ << BIT_SHIFT_RANDOM_VALUE_SHIFT_8814B)
+#define BITS_RANDOM_VALUE_SHIFT_8814B \
+ (BIT_MASK_RANDOM_VALUE_SHIFT_8814B \
+ << BIT_SHIFT_RANDOM_VALUE_SHIFT_8814B)
+#define BIT_CLEAR_RANDOM_VALUE_SHIFT_8814B(x) \
+ ((x) & (~BITS_RANDOM_VALUE_SHIFT_8814B))
+#define BIT_GET_RANDOM_VALUE_SHIFT_8814B(x) \
+ (((x) >> BIT_SHIFT_RANDOM_VALUE_SHIFT_8814B) & \
+ BIT_MASK_RANDOM_VALUE_SHIFT_8814B)
+#define BIT_SET_RANDOM_VALUE_SHIFT_8814B(x, v) \
+ (BIT_CLEAR_RANDOM_VALUE_SHIFT_8814B(x) | \
+ BIT_RANDOM_VALUE_SHIFT_8814B(v))
+
+#define BIT_ENABLE_NEW_EDCA_8814B BIT(8)
+
+#define BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER_8814B 0
+#define BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER_8814B 0xff
+#define BIT_MEDIUM_HAS_IDKE_TRIGGER_8814B(x) \
+ (((x) & BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER_8814B) \
+ << BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER_8814B)
+#define BITS_MEDIUM_HAS_IDKE_TRIGGER_8814B \
+ (BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER_8814B \
+ << BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER_8814B)
+#define BIT_CLEAR_MEDIUM_HAS_IDKE_TRIGGER_8814B(x) \
+ ((x) & (~BITS_MEDIUM_HAS_IDKE_TRIGGER_8814B))
+#define BIT_GET_MEDIUM_HAS_IDKE_TRIGGER_8814B(x) \
+ (((x) >> BIT_SHIFT_MEDIUM_HAS_IDKE_TRIGGER_8814B) & \
+ BIT_MASK_MEDIUM_HAS_IDKE_TRIGGER_8814B)
+#define BIT_SET_MEDIUM_HAS_IDKE_TRIGGER_8814B(x, v) \
+ (BIT_CLEAR_MEDIUM_HAS_IDKE_TRIGGER_8814B(x) | \
+ BIT_MEDIUM_HAS_IDKE_TRIGGER_8814B(v))
+
+/* 2 REG_ACQ_STOP_V2_8814B */
+#define BIT_AC19Q_STOP_8814B BIT(19)
+#define BIT_AC18Q_STOP_8814B BIT(18)
+#define BIT_AC17Q_STOP_8814B BIT(17)
+#define BIT_AC16Q_STOP_8814B BIT(16)
+#define BIT_AC15Q_STOP_8814B BIT(15)
+#define BIT_AC14Q_STOP_8814B BIT(14)
+#define BIT_AC13Q_STOP_8814B BIT(13)
+#define BIT_AC12Q_STOP_8814B BIT(12)
+#define BIT_AC11Q_STOP_8814B BIT(11)
+#define BIT_AC10Q_STOP_8814B BIT(10)
+#define BIT_AC9Q_STOP_8814B BIT(9)
+#define BIT_AC8Q_STOP_8814B BIT(8)
+#define BIT_AC7Q_STOP_8814B BIT(7)
+#define BIT_AC6Q_STOP_8814B BIT(6)
+#define BIT_AC5Q_STOP_8814B BIT(5)
+#define BIT_AC4Q_STOP_8814B BIT(4)
+#define BIT_AC3Q_STOP_8814B BIT(3)
+#define BIT_AC2Q_STOP_8814B BIT(2)
+#define BIT_AC1Q_STOP_8814B BIT(1)
+#define BIT_AC0Q_STOP_8814B BIT(0)
+
+/* 2 REG_WMAC_LBK_BUF_HD_V1_8814B */
+
+#define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8814B 0
+#define BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8814B 0xfff
+#define BIT_WMAC_LBK_BUF_HEAD_V1_8814B(x) \
+ (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8814B) \
+ << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8814B)
+#define BITS_WMAC_LBK_BUF_HEAD_V1_8814B \
+ (BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8814B \
+ << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8814B)
+#define BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8814B(x) \
+ ((x) & (~BITS_WMAC_LBK_BUF_HEAD_V1_8814B))
+#define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8814B) & \
+ BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8814B)
+#define BIT_SET_WMAC_LBK_BUF_HEAD_V1_8814B(x, v) \
+ (BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8814B(x) | \
+ BIT_WMAC_LBK_BUF_HEAD_V1_8814B(v))
+
+/* 2 REG_MGQ_BDNY_V1_8814B */
+
+#define BIT_SHIFT_MGQ_PGBNDY_V1_8814B 0
+#define BIT_MASK_MGQ_PGBNDY_V1_8814B 0xfff
+#define BIT_MGQ_PGBNDY_V1_8814B(x) \
+ (((x) & BIT_MASK_MGQ_PGBNDY_V1_8814B) << BIT_SHIFT_MGQ_PGBNDY_V1_8814B)
+#define BITS_MGQ_PGBNDY_V1_8814B \
+ (BIT_MASK_MGQ_PGBNDY_V1_8814B << BIT_SHIFT_MGQ_PGBNDY_V1_8814B)
+#define BIT_CLEAR_MGQ_PGBNDY_V1_8814B(x) ((x) & (~BITS_MGQ_PGBNDY_V1_8814B))
+#define BIT_GET_MGQ_PGBNDY_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8814B) & BIT_MASK_MGQ_PGBNDY_V1_8814B)
+#define BIT_SET_MGQ_PGBNDY_V1_8814B(x, v) \
+ (BIT_CLEAR_MGQ_PGBNDY_V1_8814B(x) | BIT_MGQ_PGBNDY_V1_8814B(v))
+
+/* 2 REG_TXRPT_CTRL_8814B */
+
+#define BIT_SHIFT_TRXRPT_TIMER_TH_8814B 24
+#define BIT_MASK_TRXRPT_TIMER_TH_8814B 0xff
+#define BIT_TRXRPT_TIMER_TH_8814B(x) \
+ (((x) & BIT_MASK_TRXRPT_TIMER_TH_8814B) \
+ << BIT_SHIFT_TRXRPT_TIMER_TH_8814B)
+#define BITS_TRXRPT_TIMER_TH_8814B \
+ (BIT_MASK_TRXRPT_TIMER_TH_8814B << BIT_SHIFT_TRXRPT_TIMER_TH_8814B)
+#define BIT_CLEAR_TRXRPT_TIMER_TH_8814B(x) ((x) & (~BITS_TRXRPT_TIMER_TH_8814B))
+#define BIT_GET_TRXRPT_TIMER_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8814B) & \
+ BIT_MASK_TRXRPT_TIMER_TH_8814B)
+#define BIT_SET_TRXRPT_TIMER_TH_8814B(x, v) \
+ (BIT_CLEAR_TRXRPT_TIMER_TH_8814B(x) | BIT_TRXRPT_TIMER_TH_8814B(v))
+
+#define BIT_SHIFT_TRXRPT_LEN_TH_8814B 16
+#define BIT_MASK_TRXRPT_LEN_TH_8814B 0xff
+#define BIT_TRXRPT_LEN_TH_8814B(x) \
+ (((x) & BIT_MASK_TRXRPT_LEN_TH_8814B) << BIT_SHIFT_TRXRPT_LEN_TH_8814B)
+#define BITS_TRXRPT_LEN_TH_8814B \
+ (BIT_MASK_TRXRPT_LEN_TH_8814B << BIT_SHIFT_TRXRPT_LEN_TH_8814B)
+#define BIT_CLEAR_TRXRPT_LEN_TH_8814B(x) ((x) & (~BITS_TRXRPT_LEN_TH_8814B))
+#define BIT_GET_TRXRPT_LEN_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8814B) & BIT_MASK_TRXRPT_LEN_TH_8814B)
+#define BIT_SET_TRXRPT_LEN_TH_8814B(x, v) \
+ (BIT_CLEAR_TRXRPT_LEN_TH_8814B(x) | BIT_TRXRPT_LEN_TH_8814B(v))
+
+#define BIT_SHIFT_TRXRPT_READ_PTR_8814B 8
+#define BIT_MASK_TRXRPT_READ_PTR_8814B 0xff
+#define BIT_TRXRPT_READ_PTR_8814B(x) \
+ (((x) & BIT_MASK_TRXRPT_READ_PTR_8814B) \
+ << BIT_SHIFT_TRXRPT_READ_PTR_8814B)
+#define BITS_TRXRPT_READ_PTR_8814B \
+ (BIT_MASK_TRXRPT_READ_PTR_8814B << BIT_SHIFT_TRXRPT_READ_PTR_8814B)
+#define BIT_CLEAR_TRXRPT_READ_PTR_8814B(x) ((x) & (~BITS_TRXRPT_READ_PTR_8814B))
+#define BIT_GET_TRXRPT_READ_PTR_8814B(x) \
+ (((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8814B) & \
+ BIT_MASK_TRXRPT_READ_PTR_8814B)
+#define BIT_SET_TRXRPT_READ_PTR_8814B(x, v) \
+ (BIT_CLEAR_TRXRPT_READ_PTR_8814B(x) | BIT_TRXRPT_READ_PTR_8814B(v))
+
+#define BIT_SHIFT_TRXRPT_WRITE_PTR_8814B 0
+#define BIT_MASK_TRXRPT_WRITE_PTR_8814B 0xff
+#define BIT_TRXRPT_WRITE_PTR_8814B(x) \
+ (((x) & BIT_MASK_TRXRPT_WRITE_PTR_8814B) \
+ << BIT_SHIFT_TRXRPT_WRITE_PTR_8814B)
+#define BITS_TRXRPT_WRITE_PTR_8814B \
+ (BIT_MASK_TRXRPT_WRITE_PTR_8814B << BIT_SHIFT_TRXRPT_WRITE_PTR_8814B)
+#define BIT_CLEAR_TRXRPT_WRITE_PTR_8814B(x) \
+ ((x) & (~BITS_TRXRPT_WRITE_PTR_8814B))
+#define BIT_GET_TRXRPT_WRITE_PTR_8814B(x) \
+ (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8814B) & \
+ BIT_MASK_TRXRPT_WRITE_PTR_8814B)
+#define BIT_SET_TRXRPT_WRITE_PTR_8814B(x, v) \
+ (BIT_CLEAR_TRXRPT_WRITE_PTR_8814B(x) | BIT_TRXRPT_WRITE_PTR_8814B(v))
+
+/* 2 REG_INIRTS_RATE_SEL_8814B */
+#define BIT_LEAG_RTS_BW_DUP_8814B BIT(5)
+
+/* 2 REG_BASIC_CFEND_RATE_8814B */
+
+#define BIT_SHIFT_BASIC_CFEND_RATE_8814B 0
+#define BIT_MASK_BASIC_CFEND_RATE_8814B 0x1f
+#define BIT_BASIC_CFEND_RATE_8814B(x) \
+ (((x) & BIT_MASK_BASIC_CFEND_RATE_8814B) \
+ << BIT_SHIFT_BASIC_CFEND_RATE_8814B)
+#define BITS_BASIC_CFEND_RATE_8814B \
+ (BIT_MASK_BASIC_CFEND_RATE_8814B << BIT_SHIFT_BASIC_CFEND_RATE_8814B)
+#define BIT_CLEAR_BASIC_CFEND_RATE_8814B(x) \
+ ((x) & (~BITS_BASIC_CFEND_RATE_8814B))
+#define BIT_GET_BASIC_CFEND_RATE_8814B(x) \
+ (((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8814B) & \
+ BIT_MASK_BASIC_CFEND_RATE_8814B)
+#define BIT_SET_BASIC_CFEND_RATE_8814B(x, v) \
+ (BIT_CLEAR_BASIC_CFEND_RATE_8814B(x) | BIT_BASIC_CFEND_RATE_8814B(v))
+
+/* 2 REG_STBC_CFEND_RATE_8814B */
+
+#define BIT_SHIFT_STBC_CFEND_RATE_8814B 0
+#define BIT_MASK_STBC_CFEND_RATE_8814B 0x1f
+#define BIT_STBC_CFEND_RATE_8814B(x) \
+ (((x) & BIT_MASK_STBC_CFEND_RATE_8814B) \
+ << BIT_SHIFT_STBC_CFEND_RATE_8814B)
+#define BITS_STBC_CFEND_RATE_8814B \
+ (BIT_MASK_STBC_CFEND_RATE_8814B << BIT_SHIFT_STBC_CFEND_RATE_8814B)
+#define BIT_CLEAR_STBC_CFEND_RATE_8814B(x) ((x) & (~BITS_STBC_CFEND_RATE_8814B))
+#define BIT_GET_STBC_CFEND_RATE_8814B(x) \
+ (((x) >> BIT_SHIFT_STBC_CFEND_RATE_8814B) & \
+ BIT_MASK_STBC_CFEND_RATE_8814B)
+#define BIT_SET_STBC_CFEND_RATE_8814B(x, v) \
+ (BIT_CLEAR_STBC_CFEND_RATE_8814B(x) | BIT_STBC_CFEND_RATE_8814B(v))
+
+/* 2 REG_DATA_SC_8814B */
+
+#define BIT_SHIFT_TXSC_40M_8814B 4
+#define BIT_MASK_TXSC_40M_8814B 0xf
+#define BIT_TXSC_40M_8814B(x) \
+ (((x) & BIT_MASK_TXSC_40M_8814B) << BIT_SHIFT_TXSC_40M_8814B)
+#define BITS_TXSC_40M_8814B \
+ (BIT_MASK_TXSC_40M_8814B << BIT_SHIFT_TXSC_40M_8814B)
+#define BIT_CLEAR_TXSC_40M_8814B(x) ((x) & (~BITS_TXSC_40M_8814B))
+#define BIT_GET_TXSC_40M_8814B(x) \
+ (((x) >> BIT_SHIFT_TXSC_40M_8814B) & BIT_MASK_TXSC_40M_8814B)
+#define BIT_SET_TXSC_40M_8814B(x, v) \
+ (BIT_CLEAR_TXSC_40M_8814B(x) | BIT_TXSC_40M_8814B(v))
+
+#define BIT_SHIFT_TXSC_20M_8814B 0
+#define BIT_MASK_TXSC_20M_8814B 0xf
+#define BIT_TXSC_20M_8814B(x) \
+ (((x) & BIT_MASK_TXSC_20M_8814B) << BIT_SHIFT_TXSC_20M_8814B)
+#define BITS_TXSC_20M_8814B \
+ (BIT_MASK_TXSC_20M_8814B << BIT_SHIFT_TXSC_20M_8814B)
+#define BIT_CLEAR_TXSC_20M_8814B(x) ((x) & (~BITS_TXSC_20M_8814B))
+#define BIT_GET_TXSC_20M_8814B(x) \
+ (((x) >> BIT_SHIFT_TXSC_20M_8814B) & BIT_MASK_TXSC_20M_8814B)
+#define BIT_SET_TXSC_20M_8814B(x, v) \
+ (BIT_CLEAR_TXSC_20M_8814B(x) | BIT_TXSC_20M_8814B(v))
+
+/* 2 REG_MOREDATA_V1_8814B */
+#define BIT_MOREDATA_CTRL2_EN_V1_8814B BIT(3)
+#define BIT_MOREDATA_CTRL1_EN_V1_8814B BIT(2)
+#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE_V1_8814B BIT(0)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_DATA_SC1_8814B */
+
+#define BIT_SHIFT_TXSC_160M_8814B 4
+#define BIT_MASK_TXSC_160M_8814B 0xf
+#define BIT_TXSC_160M_8814B(x) \
+ (((x) & BIT_MASK_TXSC_160M_8814B) << BIT_SHIFT_TXSC_160M_8814B)
+#define BITS_TXSC_160M_8814B \
+ (BIT_MASK_TXSC_160M_8814B << BIT_SHIFT_TXSC_160M_8814B)
+#define BIT_CLEAR_TXSC_160M_8814B(x) ((x) & (~BITS_TXSC_160M_8814B))
+#define BIT_GET_TXSC_160M_8814B(x) \
+ (((x) >> BIT_SHIFT_TXSC_160M_8814B) & BIT_MASK_TXSC_160M_8814B)
+#define BIT_SET_TXSC_160M_8814B(x, v) \
+ (BIT_CLEAR_TXSC_160M_8814B(x) | BIT_TXSC_160M_8814B(v))
+
+#define BIT_SHIFT_TXSC_80M_8814B 0
+#define BIT_MASK_TXSC_80M_8814B 0xf
+#define BIT_TXSC_80M_8814B(x) \
+ (((x) & BIT_MASK_TXSC_80M_8814B) << BIT_SHIFT_TXSC_80M_8814B)
+#define BITS_TXSC_80M_8814B \
+ (BIT_MASK_TXSC_80M_8814B << BIT_SHIFT_TXSC_80M_8814B)
+#define BIT_CLEAR_TXSC_80M_8814B(x) ((x) & (~BITS_TXSC_80M_8814B))
+#define BIT_GET_TXSC_80M_8814B(x) \
+ (((x) >> BIT_SHIFT_TXSC_80M_8814B) & BIT_MASK_TXSC_80M_8814B)
+#define BIT_SET_TXSC_80M_8814B(x, v) \
+ (BIT_CLEAR_TXSC_80M_8814B(x) | BIT_TXSC_80M_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_TXRPT_START_OFFSET_8814B */
+#define BIT_RPTFIFO_RPTNUM_OPT_8814B BIT(31)
+
+#define BIT_SHIFT_MISSED_RPT_NUM_8814B 28
+#define BIT_MASK_MISSED_RPT_NUM_8814B 0x7
+#define BIT_MISSED_RPT_NUM_8814B(x) \
+ (((x) & BIT_MASK_MISSED_RPT_NUM_8814B) \
+ << BIT_SHIFT_MISSED_RPT_NUM_8814B)
+#define BITS_MISSED_RPT_NUM_8814B \
+ (BIT_MASK_MISSED_RPT_NUM_8814B << BIT_SHIFT_MISSED_RPT_NUM_8814B)
+#define BIT_CLEAR_MISSED_RPT_NUM_8814B(x) ((x) & (~BITS_MISSED_RPT_NUM_8814B))
+#define BIT_GET_MISSED_RPT_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_MISSED_RPT_NUM_8814B) & \
+ BIT_MASK_MISSED_RPT_NUM_8814B)
+#define BIT_SET_MISSED_RPT_NUM_8814B(x, v) \
+ (BIT_CLEAR_MISSED_RPT_NUM_8814B(x) | BIT_MISSED_RPT_NUM_8814B(v))
+
+#define BIT_SHIFT_MACID_CTRL_OFFSET_V1_8814B 16
+#define BIT_MASK_MACID_CTRL_OFFSET_V1_8814B 0x1ff
+#define BIT_MACID_CTRL_OFFSET_V1_8814B(x) \
+ (((x) & BIT_MASK_MACID_CTRL_OFFSET_V1_8814B) \
+ << BIT_SHIFT_MACID_CTRL_OFFSET_V1_8814B)
+#define BITS_MACID_CTRL_OFFSET_V1_8814B \
+ (BIT_MASK_MACID_CTRL_OFFSET_V1_8814B \
+ << BIT_SHIFT_MACID_CTRL_OFFSET_V1_8814B)
+#define BIT_CLEAR_MACID_CTRL_OFFSET_V1_8814B(x) \
+ ((x) & (~BITS_MACID_CTRL_OFFSET_V1_8814B))
+#define BIT_GET_MACID_CTRL_OFFSET_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_V1_8814B) & \
+ BIT_MASK_MACID_CTRL_OFFSET_V1_8814B)
+#define BIT_SET_MACID_CTRL_OFFSET_V1_8814B(x, v) \
+ (BIT_CLEAR_MACID_CTRL_OFFSET_V1_8814B(x) | \
+ BIT_MACID_CTRL_OFFSET_V1_8814B(v))
+
+#define BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1_8814B 0
+#define BIT_MASK_AMPDU_TXRPT_OFFSET_V1_8814B 0x1ff
+#define BIT_AMPDU_TXRPT_OFFSET_V1_8814B(x) \
+ (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_V1_8814B) \
+ << BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1_8814B)
+#define BITS_AMPDU_TXRPT_OFFSET_V1_8814B \
+ (BIT_MASK_AMPDU_TXRPT_OFFSET_V1_8814B \
+ << BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1_8814B)
+#define BIT_CLEAR_AMPDU_TXRPT_OFFSET_V1_8814B(x) \
+ ((x) & (~BITS_AMPDU_TXRPT_OFFSET_V1_8814B))
+#define BIT_GET_AMPDU_TXRPT_OFFSET_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_V1_8814B) & \
+ BIT_MASK_AMPDU_TXRPT_OFFSET_V1_8814B)
+#define BIT_SET_AMPDU_TXRPT_OFFSET_V1_8814B(x, v) \
+ (BIT_CLEAR_AMPDU_TXRPT_OFFSET_V1_8814B(x) | \
+ BIT_AMPDU_TXRPT_OFFSET_V1_8814B(v))
+
+/* 2 REG_POWER_STAGE1_8814B */
+#define BIT_PTA_WL_PRI_MASK_CPU_MGQ_8814B BIT(31)
+#define BIT_PTA_WL_PRI_MASK_BCNQ_8814B BIT(30)
+#define BIT_PTA_WL_PRI_MASK_HIQ_8814B BIT(29)
+#define BIT_PTA_WL_PRI_MASK_MGQ_8814B BIT(28)
+#define BIT_PTA_WL_PRI_MASK_BK_8814B BIT(27)
+#define BIT_PTA_WL_PRI_MASK_BE_8814B BIT(26)
+#define BIT_PTA_WL_PRI_MASK_VI_8814B BIT(25)
+#define BIT_PTA_WL_PRI_MASK_VO_8814B BIT(24)
+
+#define BIT_SHIFT_POWER_STAGE1_8814B 0
+#define BIT_MASK_POWER_STAGE1_8814B 0xffffff
+#define BIT_POWER_STAGE1_8814B(x) \
+ (((x) & BIT_MASK_POWER_STAGE1_8814B) << BIT_SHIFT_POWER_STAGE1_8814B)
+#define BITS_POWER_STAGE1_8814B \
+ (BIT_MASK_POWER_STAGE1_8814B << BIT_SHIFT_POWER_STAGE1_8814B)
+#define BIT_CLEAR_POWER_STAGE1_8814B(x) ((x) & (~BITS_POWER_STAGE1_8814B))
+#define BIT_GET_POWER_STAGE1_8814B(x) \
+ (((x) >> BIT_SHIFT_POWER_STAGE1_8814B) & BIT_MASK_POWER_STAGE1_8814B)
+#define BIT_SET_POWER_STAGE1_8814B(x, v) \
+ (BIT_CLEAR_POWER_STAGE1_8814B(x) | BIT_POWER_STAGE1_8814B(v))
+
+/* 2 REG_POWER_STAGE2_8814B */
+#define BIT__CTRL_PKT_POW_ADJ_8814B BIT(24)
+
+#define BIT_SHIFT_POWER_STAGE2_8814B 0
+#define BIT_MASK_POWER_STAGE2_8814B 0xffffff
+#define BIT_POWER_STAGE2_8814B(x) \
+ (((x) & BIT_MASK_POWER_STAGE2_8814B) << BIT_SHIFT_POWER_STAGE2_8814B)
+#define BITS_POWER_STAGE2_8814B \
+ (BIT_MASK_POWER_STAGE2_8814B << BIT_SHIFT_POWER_STAGE2_8814B)
+#define BIT_CLEAR_POWER_STAGE2_8814B(x) ((x) & (~BITS_POWER_STAGE2_8814B))
+#define BIT_GET_POWER_STAGE2_8814B(x) \
+ (((x) >> BIT_SHIFT_POWER_STAGE2_8814B) & BIT_MASK_POWER_STAGE2_8814B)
+#define BIT_SET_POWER_STAGE2_8814B(x, v) \
+ (BIT_CLEAR_POWER_STAGE2_8814B(x) | BIT_POWER_STAGE2_8814B(v))
+
+/* 2 REG_SW_AMPDU_BURST_MODE_CTRL_8814B */
+#define BIT_DMA_THIS_QUEUE_BK_8814B BIT(23)
+#define BIT_DMA_THIS_QUEUE_BE_8814B BIT(22)
+#define BIT_DMA_THIS_QUEUE_VI_8814B BIT(21)
+#define BIT_DMA_THIS_QUEUE_VO_8814B BIT(20)
+
+#define BIT_SHIFT_TOTAL_LEN_TH_8814B 8
+#define BIT_MASK_TOTAL_LEN_TH_8814B 0xfff
+#define BIT_TOTAL_LEN_TH_8814B(x) \
+ (((x) & BIT_MASK_TOTAL_LEN_TH_8814B) << BIT_SHIFT_TOTAL_LEN_TH_8814B)
+#define BITS_TOTAL_LEN_TH_8814B \
+ (BIT_MASK_TOTAL_LEN_TH_8814B << BIT_SHIFT_TOTAL_LEN_TH_8814B)
+#define BIT_CLEAR_TOTAL_LEN_TH_8814B(x) ((x) & (~BITS_TOTAL_LEN_TH_8814B))
+#define BIT_GET_TOTAL_LEN_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_TOTAL_LEN_TH_8814B) & BIT_MASK_TOTAL_LEN_TH_8814B)
+#define BIT_SET_TOTAL_LEN_TH_8814B(x, v) \
+ (BIT_CLEAR_TOTAL_LEN_TH_8814B(x) | BIT_TOTAL_LEN_TH_8814B(v))
+
+#define BIT_PRE_TX_CMD_8814B BIT(6)
+
+#define BIT_SHIFT_NUM_SCL_EN_8814B 4
+#define BIT_MASK_NUM_SCL_EN_8814B 0x3
+#define BIT_NUM_SCL_EN_8814B(x) \
+ (((x) & BIT_MASK_NUM_SCL_EN_8814B) << BIT_SHIFT_NUM_SCL_EN_8814B)
+#define BITS_NUM_SCL_EN_8814B \
+ (BIT_MASK_NUM_SCL_EN_8814B << BIT_SHIFT_NUM_SCL_EN_8814B)
+#define BIT_CLEAR_NUM_SCL_EN_8814B(x) ((x) & (~BITS_NUM_SCL_EN_8814B))
+#define BIT_GET_NUM_SCL_EN_8814B(x) \
+ (((x) >> BIT_SHIFT_NUM_SCL_EN_8814B) & BIT_MASK_NUM_SCL_EN_8814B)
+#define BIT_SET_NUM_SCL_EN_8814B(x, v) \
+ (BIT_CLEAR_NUM_SCL_EN_8814B(x) | BIT_NUM_SCL_EN_8814B(v))
+
+#define BIT_BK_EN_8814B BIT(3)
+#define BIT_BE_EN_8814B BIT(2)
+#define BIT_VI_EN_8814B BIT(1)
+#define BIT_VO_EN_8814B BIT(0)
+
+/* 2 REG_PKT_LIFE_TIME_8814B */
+
+#define BIT_SHIFT_PKT_LIFTIME_BEBK_8814B 16
+#define BIT_MASK_PKT_LIFTIME_BEBK_8814B 0xffff
+#define BIT_PKT_LIFTIME_BEBK_8814B(x) \
+ (((x) & BIT_MASK_PKT_LIFTIME_BEBK_8814B) \
+ << BIT_SHIFT_PKT_LIFTIME_BEBK_8814B)
+#define BITS_PKT_LIFTIME_BEBK_8814B \
+ (BIT_MASK_PKT_LIFTIME_BEBK_8814B << BIT_SHIFT_PKT_LIFTIME_BEBK_8814B)
+#define BIT_CLEAR_PKT_LIFTIME_BEBK_8814B(x) \
+ ((x) & (~BITS_PKT_LIFTIME_BEBK_8814B))
+#define BIT_GET_PKT_LIFTIME_BEBK_8814B(x) \
+ (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8814B) & \
+ BIT_MASK_PKT_LIFTIME_BEBK_8814B)
+#define BIT_SET_PKT_LIFTIME_BEBK_8814B(x, v) \
+ (BIT_CLEAR_PKT_LIFTIME_BEBK_8814B(x) | BIT_PKT_LIFTIME_BEBK_8814B(v))
+
+#define BIT_SHIFT_PKT_LIFTIME_VOVI_8814B 0
+#define BIT_MASK_PKT_LIFTIME_VOVI_8814B 0xffff
+#define BIT_PKT_LIFTIME_VOVI_8814B(x) \
+ (((x) & BIT_MASK_PKT_LIFTIME_VOVI_8814B) \
+ << BIT_SHIFT_PKT_LIFTIME_VOVI_8814B)
+#define BITS_PKT_LIFTIME_VOVI_8814B \
+ (BIT_MASK_PKT_LIFTIME_VOVI_8814B << BIT_SHIFT_PKT_LIFTIME_VOVI_8814B)
+#define BIT_CLEAR_PKT_LIFTIME_VOVI_8814B(x) \
+ ((x) & (~BITS_PKT_LIFTIME_VOVI_8814B))
+#define BIT_GET_PKT_LIFTIME_VOVI_8814B(x) \
+ (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8814B) & \
+ BIT_MASK_PKT_LIFTIME_VOVI_8814B)
+#define BIT_SET_PKT_LIFTIME_VOVI_8814B(x, v) \
+ (BIT_CLEAR_PKT_LIFTIME_VOVI_8814B(x) | BIT_PKT_LIFTIME_VOVI_8814B(v))
+
+/* 2 REG_STBC_SETTING_8814B */
+
+#define BIT_SHIFT_CDEND_TXTIME_L_8814B 4
+#define BIT_MASK_CDEND_TXTIME_L_8814B 0xf
+#define BIT_CDEND_TXTIME_L_8814B(x) \
+ (((x) & BIT_MASK_CDEND_TXTIME_L_8814B) \
+ << BIT_SHIFT_CDEND_TXTIME_L_8814B)
+#define BITS_CDEND_TXTIME_L_8814B \
+ (BIT_MASK_CDEND_TXTIME_L_8814B << BIT_SHIFT_CDEND_TXTIME_L_8814B)
+#define BIT_CLEAR_CDEND_TXTIME_L_8814B(x) ((x) & (~BITS_CDEND_TXTIME_L_8814B))
+#define BIT_GET_CDEND_TXTIME_L_8814B(x) \
+ (((x) >> BIT_SHIFT_CDEND_TXTIME_L_8814B) & \
+ BIT_MASK_CDEND_TXTIME_L_8814B)
+#define BIT_SET_CDEND_TXTIME_L_8814B(x, v) \
+ (BIT_CLEAR_CDEND_TXTIME_L_8814B(x) | BIT_CDEND_TXTIME_L_8814B(v))
+
+#define BIT_SHIFT_NESS_8814B 2
+#define BIT_MASK_NESS_8814B 0x3
+#define BIT_NESS_8814B(x) (((x) & BIT_MASK_NESS_8814B) << BIT_SHIFT_NESS_8814B)
+#define BITS_NESS_8814B (BIT_MASK_NESS_8814B << BIT_SHIFT_NESS_8814B)
+#define BIT_CLEAR_NESS_8814B(x) ((x) & (~BITS_NESS_8814B))
+#define BIT_GET_NESS_8814B(x) \
+ (((x) >> BIT_SHIFT_NESS_8814B) & BIT_MASK_NESS_8814B)
+#define BIT_SET_NESS_8814B(x, v) (BIT_CLEAR_NESS_8814B(x) | BIT_NESS_8814B(v))
+
+#define BIT_SHIFT_STBC_CFEND_8814B 0
+#define BIT_MASK_STBC_CFEND_8814B 0x3
+#define BIT_STBC_CFEND_8814B(x) \
+ (((x) & BIT_MASK_STBC_CFEND_8814B) << BIT_SHIFT_STBC_CFEND_8814B)
+#define BITS_STBC_CFEND_8814B \
+ (BIT_MASK_STBC_CFEND_8814B << BIT_SHIFT_STBC_CFEND_8814B)
+#define BIT_CLEAR_STBC_CFEND_8814B(x) ((x) & (~BITS_STBC_CFEND_8814B))
+#define BIT_GET_STBC_CFEND_8814B(x) \
+ (((x) >> BIT_SHIFT_STBC_CFEND_8814B) & BIT_MASK_STBC_CFEND_8814B)
+#define BIT_SET_STBC_CFEND_8814B(x, v) \
+ (BIT_CLEAR_STBC_CFEND_8814B(x) | BIT_STBC_CFEND_8814B(v))
+
+/* 2 REG_STBC_SETTING2_8814B */
+
+#define BIT_SHIFT_CDEND_TXTIME_H_8814B 0
+#define BIT_MASK_CDEND_TXTIME_H_8814B 0x1f
+#define BIT_CDEND_TXTIME_H_8814B(x) \
+ (((x) & BIT_MASK_CDEND_TXTIME_H_8814B) \
+ << BIT_SHIFT_CDEND_TXTIME_H_8814B)
+#define BITS_CDEND_TXTIME_H_8814B \
+ (BIT_MASK_CDEND_TXTIME_H_8814B << BIT_SHIFT_CDEND_TXTIME_H_8814B)
+#define BIT_CLEAR_CDEND_TXTIME_H_8814B(x) ((x) & (~BITS_CDEND_TXTIME_H_8814B))
+#define BIT_GET_CDEND_TXTIME_H_8814B(x) \
+ (((x) >> BIT_SHIFT_CDEND_TXTIME_H_8814B) & \
+ BIT_MASK_CDEND_TXTIME_H_8814B)
+#define BIT_SET_CDEND_TXTIME_H_8814B(x, v) \
+ (BIT_CLEAR_CDEND_TXTIME_H_8814B(x) | BIT_CDEND_TXTIME_H_8814B(v))
+
+/* 2 REG_QUEUE_CTRL_8814B */
+#define BIT_FORCE_RND_PRI_8814B BIT(6)
+#define BIT_PTA_EDCCA_EN_8814B BIT(5)
+#define BIT_PTA_WL_TX_EN_8814B BIT(4)
+#define BIT_USE_DATA_BW_8814B BIT(3)
+#define BIT_TRI_PKT_INT_MODE1_8814B BIT(2)
+#define BIT_TRI_PKT_INT_MODE0_8814B BIT(1)
+#define BIT_ACQ_MODE_SEL_8814B BIT(0)
+
+/* 2 REG_SINGLE_AMPDU_CTRL_8814B */
+#define BIT_EN_SINGLE_APMDU_8814B BIT(7)
+
+/* 2 REG_PROT_MODE_CTRL_8814B */
+
+#define BIT_SHIFT_RTS_MAX_AGG_NUM_8814B 24
+#define BIT_MASK_RTS_MAX_AGG_NUM_8814B 0x3f
+#define BIT_RTS_MAX_AGG_NUM_8814B(x) \
+ (((x) & BIT_MASK_RTS_MAX_AGG_NUM_8814B) \
+ << BIT_SHIFT_RTS_MAX_AGG_NUM_8814B)
+#define BITS_RTS_MAX_AGG_NUM_8814B \
+ (BIT_MASK_RTS_MAX_AGG_NUM_8814B << BIT_SHIFT_RTS_MAX_AGG_NUM_8814B)
+#define BIT_CLEAR_RTS_MAX_AGG_NUM_8814B(x) ((x) & (~BITS_RTS_MAX_AGG_NUM_8814B))
+#define BIT_GET_RTS_MAX_AGG_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8814B) & \
+ BIT_MASK_RTS_MAX_AGG_NUM_8814B)
+#define BIT_SET_RTS_MAX_AGG_NUM_8814B(x, v) \
+ (BIT_CLEAR_RTS_MAX_AGG_NUM_8814B(x) | BIT_RTS_MAX_AGG_NUM_8814B(v))
+
+#define BIT_SHIFT_MAX_AGG_NUM_8814B 16
+#define BIT_MASK_MAX_AGG_NUM_8814B 0x3f
+#define BIT_MAX_AGG_NUM_8814B(x) \
+ (((x) & BIT_MASK_MAX_AGG_NUM_8814B) << BIT_SHIFT_MAX_AGG_NUM_8814B)
+#define BITS_MAX_AGG_NUM_8814B \
+ (BIT_MASK_MAX_AGG_NUM_8814B << BIT_SHIFT_MAX_AGG_NUM_8814B)
+#define BIT_CLEAR_MAX_AGG_NUM_8814B(x) ((x) & (~BITS_MAX_AGG_NUM_8814B))
+#define BIT_GET_MAX_AGG_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_MAX_AGG_NUM_8814B) & BIT_MASK_MAX_AGG_NUM_8814B)
+#define BIT_SET_MAX_AGG_NUM_8814B(x, v) \
+ (BIT_CLEAR_MAX_AGG_NUM_8814B(x) | BIT_MAX_AGG_NUM_8814B(v))
+
+#define BIT_SHIFT_RTS_TXTIME_TH_8814B 8
+#define BIT_MASK_RTS_TXTIME_TH_8814B 0xff
+#define BIT_RTS_TXTIME_TH_8814B(x) \
+ (((x) & BIT_MASK_RTS_TXTIME_TH_8814B) << BIT_SHIFT_RTS_TXTIME_TH_8814B)
+#define BITS_RTS_TXTIME_TH_8814B \
+ (BIT_MASK_RTS_TXTIME_TH_8814B << BIT_SHIFT_RTS_TXTIME_TH_8814B)
+#define BIT_CLEAR_RTS_TXTIME_TH_8814B(x) ((x) & (~BITS_RTS_TXTIME_TH_8814B))
+#define BIT_GET_RTS_TXTIME_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_RTS_TXTIME_TH_8814B) & BIT_MASK_RTS_TXTIME_TH_8814B)
+#define BIT_SET_RTS_TXTIME_TH_8814B(x, v) \
+ (BIT_CLEAR_RTS_TXTIME_TH_8814B(x) | BIT_RTS_TXTIME_TH_8814B(v))
+
+#define BIT_SHIFT_RTS_LEN_TH_8814B 0
+#define BIT_MASK_RTS_LEN_TH_8814B 0xff
+#define BIT_RTS_LEN_TH_8814B(x) \
+ (((x) & BIT_MASK_RTS_LEN_TH_8814B) << BIT_SHIFT_RTS_LEN_TH_8814B)
+#define BITS_RTS_LEN_TH_8814B \
+ (BIT_MASK_RTS_LEN_TH_8814B << BIT_SHIFT_RTS_LEN_TH_8814B)
+#define BIT_CLEAR_RTS_LEN_TH_8814B(x) ((x) & (~BITS_RTS_LEN_TH_8814B))
+#define BIT_GET_RTS_LEN_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_RTS_LEN_TH_8814B) & BIT_MASK_RTS_LEN_TH_8814B)
+#define BIT_SET_RTS_LEN_TH_8814B(x, v) \
+ (BIT_CLEAR_RTS_LEN_TH_8814B(x) | BIT_RTS_LEN_TH_8814B(v))
+
+/* 2 REG_BAR_MODE_CTRL_8814B */
+
+#define BIT_SHIFT_BAR_RTY_LMT_8814B 16
+#define BIT_MASK_BAR_RTY_LMT_8814B 0x3
+#define BIT_BAR_RTY_LMT_8814B(x) \
+ (((x) & BIT_MASK_BAR_RTY_LMT_8814B) << BIT_SHIFT_BAR_RTY_LMT_8814B)
+#define BITS_BAR_RTY_LMT_8814B \
+ (BIT_MASK_BAR_RTY_LMT_8814B << BIT_SHIFT_BAR_RTY_LMT_8814B)
+#define BIT_CLEAR_BAR_RTY_LMT_8814B(x) ((x) & (~BITS_BAR_RTY_LMT_8814B))
+#define BIT_GET_BAR_RTY_LMT_8814B(x) \
+ (((x) >> BIT_SHIFT_BAR_RTY_LMT_8814B) & BIT_MASK_BAR_RTY_LMT_8814B)
+#define BIT_SET_BAR_RTY_LMT_8814B(x, v) \
+ (BIT_CLEAR_BAR_RTY_LMT_8814B(x) | BIT_BAR_RTY_LMT_8814B(v))
+
+#define BIT_SHIFT_BAR_PKT_TXTIME_TH_8814B 8
+#define BIT_MASK_BAR_PKT_TXTIME_TH_8814B 0xff
+#define BIT_BAR_PKT_TXTIME_TH_8814B(x) \
+ (((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8814B) \
+ << BIT_SHIFT_BAR_PKT_TXTIME_TH_8814B)
+#define BITS_BAR_PKT_TXTIME_TH_8814B \
+ (BIT_MASK_BAR_PKT_TXTIME_TH_8814B << BIT_SHIFT_BAR_PKT_TXTIME_TH_8814B)
+#define BIT_CLEAR_BAR_PKT_TXTIME_TH_8814B(x) \
+ ((x) & (~BITS_BAR_PKT_TXTIME_TH_8814B))
+#define BIT_GET_BAR_PKT_TXTIME_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8814B) & \
+ BIT_MASK_BAR_PKT_TXTIME_TH_8814B)
+#define BIT_SET_BAR_PKT_TXTIME_TH_8814B(x, v) \
+ (BIT_CLEAR_BAR_PKT_TXTIME_TH_8814B(x) | BIT_BAR_PKT_TXTIME_TH_8814B(v))
+
+#define BIT_BAR_EN_V1_8814B BIT(6)
+
+#define BIT_SHIFT_BAR_PKTNUM_TH_V1_8814B 0
+#define BIT_MASK_BAR_PKTNUM_TH_V1_8814B 0x3f
+#define BIT_BAR_PKTNUM_TH_V1_8814B(x) \
+ (((x) & BIT_MASK_BAR_PKTNUM_TH_V1_8814B) \
+ << BIT_SHIFT_BAR_PKTNUM_TH_V1_8814B)
+#define BITS_BAR_PKTNUM_TH_V1_8814B \
+ (BIT_MASK_BAR_PKTNUM_TH_V1_8814B << BIT_SHIFT_BAR_PKTNUM_TH_V1_8814B)
+#define BIT_CLEAR_BAR_PKTNUM_TH_V1_8814B(x) \
+ ((x) & (~BITS_BAR_PKTNUM_TH_V1_8814B))
+#define BIT_GET_BAR_PKTNUM_TH_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8814B) & \
+ BIT_MASK_BAR_PKTNUM_TH_V1_8814B)
+#define BIT_SET_BAR_PKTNUM_TH_V1_8814B(x, v) \
+ (BIT_CLEAR_BAR_PKTNUM_TH_V1_8814B(x) | BIT_BAR_PKTNUM_TH_V1_8814B(v))
+
+/* 2 REG_RA_TRY_RATE_AGG_LMT_8814B */
+
+#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8814B 0
+#define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8814B 0x3f
+#define BIT_RA_TRY_RATE_AGG_LMT_V1_8814B(x) \
+ (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8814B) \
+ << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8814B)
+#define BITS_RA_TRY_RATE_AGG_LMT_V1_8814B \
+ (BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8814B \
+ << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8814B)
+#define BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8814B(x) \
+ ((x) & (~BITS_RA_TRY_RATE_AGG_LMT_V1_8814B))
+#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8814B) & \
+ BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8814B)
+#define BIT_SET_RA_TRY_RATE_AGG_LMT_V1_8814B(x, v) \
+ (BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8814B(x) | \
+ BIT_RA_TRY_RATE_AGG_LMT_V1_8814B(v))
+
+/* 2 REG_MACID_SLEEP_CTRL_8814B */
+
+#define BIT_SHIFT_DEBUG_PROTOCOL_8814B 24
+#define BIT_MASK_DEBUG_PROTOCOL_8814B 0xff
+#define BIT_DEBUG_PROTOCOL_8814B(x) \
+ (((x) & BIT_MASK_DEBUG_PROTOCOL_8814B) \
+ << BIT_SHIFT_DEBUG_PROTOCOL_8814B)
+#define BITS_DEBUG_PROTOCOL_8814B \
+ (BIT_MASK_DEBUG_PROTOCOL_8814B << BIT_SHIFT_DEBUG_PROTOCOL_8814B)
+#define BIT_CLEAR_DEBUG_PROTOCOL_8814B(x) ((x) & (~BITS_DEBUG_PROTOCOL_8814B))
+#define BIT_GET_DEBUG_PROTOCOL_8814B(x) \
+ (((x) >> BIT_SHIFT_DEBUG_PROTOCOL_8814B) & \
+ BIT_MASK_DEBUG_PROTOCOL_8814B)
+#define BIT_SET_DEBUG_PROTOCOL_8814B(x, v) \
+ (BIT_CLEAR_DEBUG_PROTOCOL_8814B(x) | BIT_DEBUG_PROTOCOL_8814B(v))
+
+#define BIT_SHIFT_BCNQ_PGBNDY_RSEL_8814B 16
+#define BIT_MASK_BCNQ_PGBNDY_RSEL_8814B 0x7
+#define BIT_BCNQ_PGBNDY_RSEL_8814B(x) \
+ (((x) & BIT_MASK_BCNQ_PGBNDY_RSEL_8814B) \
+ << BIT_SHIFT_BCNQ_PGBNDY_RSEL_8814B)
+#define BITS_BCNQ_PGBNDY_RSEL_8814B \
+ (BIT_MASK_BCNQ_PGBNDY_RSEL_8814B << BIT_SHIFT_BCNQ_PGBNDY_RSEL_8814B)
+#define BIT_CLEAR_BCNQ_PGBNDY_RSEL_8814B(x) \
+ ((x) & (~BITS_BCNQ_PGBNDY_RSEL_8814B))
+#define BIT_GET_BCNQ_PGBNDY_RSEL_8814B(x) \
+ (((x) >> BIT_SHIFT_BCNQ_PGBNDY_RSEL_8814B) & \
+ BIT_MASK_BCNQ_PGBNDY_RSEL_8814B)
+#define BIT_SET_BCNQ_PGBNDY_RSEL_8814B(x, v) \
+ (BIT_CLEAR_BCNQ_PGBNDY_RSEL_8814B(x) | BIT_BCNQ_PGBNDY_RSEL_8814B(v))
+
+#define BIT_SHIFT_MACID_SLEEP_SEL_8814B 0
+#define BIT_MASK_MACID_SLEEP_SEL_8814B 0x7
+#define BIT_MACID_SLEEP_SEL_8814B(x) \
+ (((x) & BIT_MASK_MACID_SLEEP_SEL_8814B) \
+ << BIT_SHIFT_MACID_SLEEP_SEL_8814B)
+#define BITS_MACID_SLEEP_SEL_8814B \
+ (BIT_MASK_MACID_SLEEP_SEL_8814B << BIT_SHIFT_MACID_SLEEP_SEL_8814B)
+#define BIT_CLEAR_MACID_SLEEP_SEL_8814B(x) ((x) & (~BITS_MACID_SLEEP_SEL_8814B))
+#define BIT_GET_MACID_SLEEP_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_MACID_SLEEP_SEL_8814B) & \
+ BIT_MASK_MACID_SLEEP_SEL_8814B)
+#define BIT_SET_MACID_SLEEP_SEL_8814B(x, v) \
+ (BIT_CLEAR_MACID_SLEEP_SEL_8814B(x) | BIT_MACID_SLEEP_SEL_8814B(v))
+
+/* 2 REG_MACID_SLEEP_INFO_8814B */
+
+#define BIT_SHIFT_MACID_SLEEP_INFO_8814B 0
+#define BIT_MASK_MACID_SLEEP_INFO_8814B 0xffffffffL
+#define BIT_MACID_SLEEP_INFO_8814B(x) \
+ (((x) & BIT_MASK_MACID_SLEEP_INFO_8814B) \
+ << BIT_SHIFT_MACID_SLEEP_INFO_8814B)
+#define BITS_MACID_SLEEP_INFO_8814B \
+ (BIT_MASK_MACID_SLEEP_INFO_8814B << BIT_SHIFT_MACID_SLEEP_INFO_8814B)
+#define BIT_CLEAR_MACID_SLEEP_INFO_8814B(x) \
+ ((x) & (~BITS_MACID_SLEEP_INFO_8814B))
+#define BIT_GET_MACID_SLEEP_INFO_8814B(x) \
+ (((x) >> BIT_SHIFT_MACID_SLEEP_INFO_8814B) & \
+ BIT_MASK_MACID_SLEEP_INFO_8814B)
+#define BIT_SET_MACID_SLEEP_INFO_8814B(x, v) \
+ (BIT_CLEAR_MACID_SLEEP_INFO_8814B(x) | BIT_MACID_SLEEP_INFO_8814B(v))
+
+/* 2 REG_HW_SEQ0_8814B */
+
+#define BIT_SHIFT_HW_SSN_SEQ0_8814B 0
+#define BIT_MASK_HW_SSN_SEQ0_8814B 0xfff
+#define BIT_HW_SSN_SEQ0_8814B(x) \
+ (((x) & BIT_MASK_HW_SSN_SEQ0_8814B) << BIT_SHIFT_HW_SSN_SEQ0_8814B)
+#define BITS_HW_SSN_SEQ0_8814B \
+ (BIT_MASK_HW_SSN_SEQ0_8814B << BIT_SHIFT_HW_SSN_SEQ0_8814B)
+#define BIT_CLEAR_HW_SSN_SEQ0_8814B(x) ((x) & (~BITS_HW_SSN_SEQ0_8814B))
+#define BIT_GET_HW_SSN_SEQ0_8814B(x) \
+ (((x) >> BIT_SHIFT_HW_SSN_SEQ0_8814B) & BIT_MASK_HW_SSN_SEQ0_8814B)
+#define BIT_SET_HW_SSN_SEQ0_8814B(x, v) \
+ (BIT_CLEAR_HW_SSN_SEQ0_8814B(x) | BIT_HW_SSN_SEQ0_8814B(v))
+
+/* 2 REG_HW_SEQ1_8814B */
+
+#define BIT_SHIFT_HW_SSN_SEQ1_8814B 0
+#define BIT_MASK_HW_SSN_SEQ1_8814B 0xfff
+#define BIT_HW_SSN_SEQ1_8814B(x) \
+ (((x) & BIT_MASK_HW_SSN_SEQ1_8814B) << BIT_SHIFT_HW_SSN_SEQ1_8814B)
+#define BITS_HW_SSN_SEQ1_8814B \
+ (BIT_MASK_HW_SSN_SEQ1_8814B << BIT_SHIFT_HW_SSN_SEQ1_8814B)
+#define BIT_CLEAR_HW_SSN_SEQ1_8814B(x) ((x) & (~BITS_HW_SSN_SEQ1_8814B))
+#define BIT_GET_HW_SSN_SEQ1_8814B(x) \
+ (((x) >> BIT_SHIFT_HW_SSN_SEQ1_8814B) & BIT_MASK_HW_SSN_SEQ1_8814B)
+#define BIT_SET_HW_SSN_SEQ1_8814B(x, v) \
+ (BIT_CLEAR_HW_SSN_SEQ1_8814B(x) | BIT_HW_SSN_SEQ1_8814B(v))
+
+/* 2 REG_HW_SEQ2_8814B */
+
+#define BIT_SHIFT_HW_SSN_SEQ2_8814B 0
+#define BIT_MASK_HW_SSN_SEQ2_8814B 0xfff
+#define BIT_HW_SSN_SEQ2_8814B(x) \
+ (((x) & BIT_MASK_HW_SSN_SEQ2_8814B) << BIT_SHIFT_HW_SSN_SEQ2_8814B)
+#define BITS_HW_SSN_SEQ2_8814B \
+ (BIT_MASK_HW_SSN_SEQ2_8814B << BIT_SHIFT_HW_SSN_SEQ2_8814B)
+#define BIT_CLEAR_HW_SSN_SEQ2_8814B(x) ((x) & (~BITS_HW_SSN_SEQ2_8814B))
+#define BIT_GET_HW_SSN_SEQ2_8814B(x) \
+ (((x) >> BIT_SHIFT_HW_SSN_SEQ2_8814B) & BIT_MASK_HW_SSN_SEQ2_8814B)
+#define BIT_SET_HW_SSN_SEQ2_8814B(x, v) \
+ (BIT_CLEAR_HW_SSN_SEQ2_8814B(x) | BIT_HW_SSN_SEQ2_8814B(v))
+
+/* 2 REG_HW_SEQ3_8814B */
+
+#define BIT_SHIFT_CSI_HWSEQ_SEL_8814B 12
+#define BIT_MASK_CSI_HWSEQ_SEL_8814B 0x3
+#define BIT_CSI_HWSEQ_SEL_8814B(x) \
+ (((x) & BIT_MASK_CSI_HWSEQ_SEL_8814B) << BIT_SHIFT_CSI_HWSEQ_SEL_8814B)
+#define BITS_CSI_HWSEQ_SEL_8814B \
+ (BIT_MASK_CSI_HWSEQ_SEL_8814B << BIT_SHIFT_CSI_HWSEQ_SEL_8814B)
+#define BIT_CLEAR_CSI_HWSEQ_SEL_8814B(x) ((x) & (~BITS_CSI_HWSEQ_SEL_8814B))
+#define BIT_GET_CSI_HWSEQ_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_CSI_HWSEQ_SEL_8814B) & BIT_MASK_CSI_HWSEQ_SEL_8814B)
+#define BIT_SET_CSI_HWSEQ_SEL_8814B(x, v) \
+ (BIT_CLEAR_CSI_HWSEQ_SEL_8814B(x) | BIT_CSI_HWSEQ_SEL_8814B(v))
+
+#define BIT_SHIFT_HW_SSN_SEQ3_8814B 0
+#define BIT_MASK_HW_SSN_SEQ3_8814B 0xfff
+#define BIT_HW_SSN_SEQ3_8814B(x) \
+ (((x) & BIT_MASK_HW_SSN_SEQ3_8814B) << BIT_SHIFT_HW_SSN_SEQ3_8814B)
+#define BITS_HW_SSN_SEQ3_8814B \
+ (BIT_MASK_HW_SSN_SEQ3_8814B << BIT_SHIFT_HW_SSN_SEQ3_8814B)
+#define BIT_CLEAR_HW_SSN_SEQ3_8814B(x) ((x) & (~BITS_HW_SSN_SEQ3_8814B))
+#define BIT_GET_HW_SSN_SEQ3_8814B(x) \
+ (((x) >> BIT_SHIFT_HW_SSN_SEQ3_8814B) & BIT_MASK_HW_SSN_SEQ3_8814B)
+#define BIT_SET_HW_SSN_SEQ3_8814B(x, v) \
+ (BIT_CLEAR_HW_SSN_SEQ3_8814B(x) | BIT_HW_SSN_SEQ3_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_PTCL_TOTAL_PG_V3_8814B 0
+#define BIT_MASK_PTCL_TOTAL_PG_V3_8814B 0x1fff
+#define BIT_PTCL_TOTAL_PG_V3_8814B(x) \
+ (((x) & BIT_MASK_PTCL_TOTAL_PG_V3_8814B) \
+ << BIT_SHIFT_PTCL_TOTAL_PG_V3_8814B)
+#define BITS_PTCL_TOTAL_PG_V3_8814B \
+ (BIT_MASK_PTCL_TOTAL_PG_V3_8814B << BIT_SHIFT_PTCL_TOTAL_PG_V3_8814B)
+#define BIT_CLEAR_PTCL_TOTAL_PG_V3_8814B(x) \
+ ((x) & (~BITS_PTCL_TOTAL_PG_V3_8814B))
+#define BIT_GET_PTCL_TOTAL_PG_V3_8814B(x) \
+ (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V3_8814B) & \
+ BIT_MASK_PTCL_TOTAL_PG_V3_8814B)
+#define BIT_SET_PTCL_TOTAL_PG_V3_8814B(x, v) \
+ (BIT_CLEAR_PTCL_TOTAL_PG_V3_8814B(x) | BIT_PTCL_TOTAL_PG_V3_8814B(v))
+
+/* 2 REG_PTCL_ERR_STATUS_V1_8814B */
+#define BIT_MUARB_SEARCH_ERR_8814B BIT(14)
+#define BIT_MU_BFEN_ERR_8814B BIT(12)
+#define BIT_NDPA_DROPNULL_ERR_8814B BIT(11)
+#define BIT_NDPA_DROPPKT_ERR_8814B BIT(10)
+#define BIT_PTCL_PKYIN_ERR_8814B BIT(9)
+#define BIT_PTCL_QSELCNL_ERR_8814B BIT(8)
+#define BIT_PTCL_RATE_TABLE_INVALID_8814B BIT(7)
+#define BIT_FTM_T2R_ERROR_8814B BIT(6)
+#define BIT_TXTIMEOUT_ERR_8814B BIT(5)
+#define BIT_NULLPAGE_ERR_8814B BIT(4)
+#define BIT_CONTENTION_ERR_8814B BIT(3)
+#define BIT_HEADNULL_ERR_8814B BIT(2)
+#define BIT_OVERFLOW_ERR_8814B BIT(1)
+#define BIT_QUEUE_INDEX_ERR_8814B BIT(0)
+
+/* 2 REG_NULL_PKT_STATUS_V2_8814B */
+#define BIT_HIQ_DROP_8814B BIT(7)
+#define BIT_MGQ_DROP_8814B BIT(6)
+#define BIT_TX_NULL_1_V1_8814B BIT(1)
+#define BIT_TX_NULL_0_V1_8814B BIT(0)
+
+/* 2 REG_PRECNT_CTRL_8814B */
+#define BIT_EN_PRECNT_8814B BIT(11)
+
+#define BIT_SHIFT_PRECNT_TH_8814B 0
+#define BIT_MASK_PRECNT_TH_8814B 0x7ff
+#define BIT_PRECNT_TH_8814B(x) \
+ (((x) & BIT_MASK_PRECNT_TH_8814B) << BIT_SHIFT_PRECNT_TH_8814B)
+#define BITS_PRECNT_TH_8814B \
+ (BIT_MASK_PRECNT_TH_8814B << BIT_SHIFT_PRECNT_TH_8814B)
+#define BIT_CLEAR_PRECNT_TH_8814B(x) ((x) & (~BITS_PRECNT_TH_8814B))
+#define BIT_GET_PRECNT_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_PRECNT_TH_8814B) & BIT_MASK_PRECNT_TH_8814B)
+#define BIT_SET_PRECNT_TH_8814B(x, v) \
+ (BIT_CLEAR_PRECNT_TH_8814B(x) | BIT_PRECNT_TH_8814B(v))
+
+/* 2 REG_NULL_PKT_STATUS_EXTEND_V1_8814B */
+#define BIT_CLI3_TX_NULL_1_V1_8814B BIT(7)
+#define BIT_CLI3_TX_NULL_0_V1_8814B BIT(6)
+#define BIT_CLI2_TX_NULL_1_V1_8814B BIT(5)
+#define BIT_CLI2_TX_NULL_0_V1_8814B BIT(4)
+#define BIT_CLI1_TX_NULL_1_V1_8814B BIT(3)
+#define BIT_CLI1_TX_NULL_0_V1_8814B BIT(2)
+#define BIT_CLI0_TX_NULL_1_V1_8814B BIT(1)
+#define BIT_CLI0_TX_NULL_0_V1_8814B BIT(0)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_PTCL_DBG_V1_8814B */
+
+#define BIT_SHIFT_PTCL_DBG_8814B 0
+#define BIT_MASK_PTCL_DBG_8814B 0xffffffffL
+#define BIT_PTCL_DBG_8814B(x) \
+ (((x) & BIT_MASK_PTCL_DBG_8814B) << BIT_SHIFT_PTCL_DBG_8814B)
+#define BITS_PTCL_DBG_8814B \
+ (BIT_MASK_PTCL_DBG_8814B << BIT_SHIFT_PTCL_DBG_8814B)
+#define BIT_CLEAR_PTCL_DBG_8814B(x) ((x) & (~BITS_PTCL_DBG_8814B))
+#define BIT_GET_PTCL_DBG_8814B(x) \
+ (((x) >> BIT_SHIFT_PTCL_DBG_8814B) & BIT_MASK_PTCL_DBG_8814B)
+#define BIT_SET_PTCL_DBG_8814B(x, v) \
+ (BIT_CLEAR_PTCL_DBG_8814B(x) | BIT_PTCL_DBG_8814B(v))
+
+/* 2 REG_BT_POLLUTE_PKTCNT_8814B */
+
+#define BIT_SHIFT_BT_POLLUTE_PKTCNT_8814B 0
+#define BIT_MASK_BT_POLLUTE_PKTCNT_8814B 0xffff
+#define BIT_BT_POLLUTE_PKTCNT_8814B(x) \
+ (((x) & BIT_MASK_BT_POLLUTE_PKTCNT_8814B) \
+ << BIT_SHIFT_BT_POLLUTE_PKTCNT_8814B)
+#define BITS_BT_POLLUTE_PKTCNT_8814B \
+ (BIT_MASK_BT_POLLUTE_PKTCNT_8814B << BIT_SHIFT_BT_POLLUTE_PKTCNT_8814B)
+#define BIT_CLEAR_BT_POLLUTE_PKTCNT_8814B(x) \
+ ((x) & (~BITS_BT_POLLUTE_PKTCNT_8814B))
+#define BIT_GET_BT_POLLUTE_PKTCNT_8814B(x) \
+ (((x) >> BIT_SHIFT_BT_POLLUTE_PKTCNT_8814B) & \
+ BIT_MASK_BT_POLLUTE_PKTCNT_8814B)
+#define BIT_SET_BT_POLLUTE_PKTCNT_8814B(x, v) \
+ (BIT_CLEAR_BT_POLLUTE_PKTCNT_8814B(x) | BIT_BT_POLLUTE_PKTCNT_8814B(v))
+
+/* 2 REG_CPUMGQ_TIMER_CTRL2_8814B */
+
+#define BIT_SHIFT_TRI_HEAD_ADDR_8814B 16
+#define BIT_MASK_TRI_HEAD_ADDR_8814B 0xfff
+#define BIT_TRI_HEAD_ADDR_8814B(x) \
+ (((x) & BIT_MASK_TRI_HEAD_ADDR_8814B) << BIT_SHIFT_TRI_HEAD_ADDR_8814B)
+#define BITS_TRI_HEAD_ADDR_8814B \
+ (BIT_MASK_TRI_HEAD_ADDR_8814B << BIT_SHIFT_TRI_HEAD_ADDR_8814B)
+#define BIT_CLEAR_TRI_HEAD_ADDR_8814B(x) ((x) & (~BITS_TRI_HEAD_ADDR_8814B))
+#define BIT_GET_TRI_HEAD_ADDR_8814B(x) \
+ (((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8814B) & BIT_MASK_TRI_HEAD_ADDR_8814B)
+#define BIT_SET_TRI_HEAD_ADDR_8814B(x, v) \
+ (BIT_CLEAR_TRI_HEAD_ADDR_8814B(x) | BIT_TRI_HEAD_ADDR_8814B(v))
+
+#define BIT_DROP_TH_EN_8814B BIT(8)
+
+#define BIT_SHIFT_DROP_TH_8814B 0
+#define BIT_MASK_DROP_TH_8814B 0xff
+#define BIT_DROP_TH_8814B(x) \
+ (((x) & BIT_MASK_DROP_TH_8814B) << BIT_SHIFT_DROP_TH_8814B)
+#define BITS_DROP_TH_8814B (BIT_MASK_DROP_TH_8814B << BIT_SHIFT_DROP_TH_8814B)
+#define BIT_CLEAR_DROP_TH_8814B(x) ((x) & (~BITS_DROP_TH_8814B))
+#define BIT_GET_DROP_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_DROP_TH_8814B) & BIT_MASK_DROP_TH_8814B)
+#define BIT_SET_DROP_TH_8814B(x, v) \
+ (BIT_CLEAR_DROP_TH_8814B(x) | BIT_DROP_TH_8814B(v))
+
+/* 2 REG_PTCL_DBG_OUT_8814B */
+
+#define BIT_SHIFT_PTCL_DBG_OUT_8814B 0
+#define BIT_MASK_PTCL_DBG_OUT_8814B 0xffffffffL
+#define BIT_PTCL_DBG_OUT_8814B(x) \
+ (((x) & BIT_MASK_PTCL_DBG_OUT_8814B) << BIT_SHIFT_PTCL_DBG_OUT_8814B)
+#define BITS_PTCL_DBG_OUT_8814B \
+ (BIT_MASK_PTCL_DBG_OUT_8814B << BIT_SHIFT_PTCL_DBG_OUT_8814B)
+#define BIT_CLEAR_PTCL_DBG_OUT_8814B(x) ((x) & (~BITS_PTCL_DBG_OUT_8814B))
+#define BIT_GET_PTCL_DBG_OUT_8814B(x) \
+ (((x) >> BIT_SHIFT_PTCL_DBG_OUT_8814B) & BIT_MASK_PTCL_DBG_OUT_8814B)
+#define BIT_SET_PTCL_DBG_OUT_8814B(x, v) \
+ (BIT_CLEAR_PTCL_DBG_OUT_8814B(x) | BIT_PTCL_DBG_OUT_8814B(v))
+
+/* 2 REG_DUMMY_PAGE4_V1_8814B */
+
+/* 2 REG_DUMMY_PAGE4_1_8814B */
+
+/* 2 REG_MU_OFFSET_8814B */
+
+#define BIT_SHIFT_MU_RATETABLE_OFFSET_8814B 16
+#define BIT_MASK_MU_RATETABLE_OFFSET_8814B 0x1ff
+#define BIT_MU_RATETABLE_OFFSET_8814B(x) \
+ (((x) & BIT_MASK_MU_RATETABLE_OFFSET_8814B) \
+ << BIT_SHIFT_MU_RATETABLE_OFFSET_8814B)
+#define BITS_MU_RATETABLE_OFFSET_8814B \
+ (BIT_MASK_MU_RATETABLE_OFFSET_8814B \
+ << BIT_SHIFT_MU_RATETABLE_OFFSET_8814B)
+#define BIT_CLEAR_MU_RATETABLE_OFFSET_8814B(x) \
+ ((x) & (~BITS_MU_RATETABLE_OFFSET_8814B))
+#define BIT_GET_MU_RATETABLE_OFFSET_8814B(x) \
+ (((x) >> BIT_SHIFT_MU_RATETABLE_OFFSET_8814B) & \
+ BIT_MASK_MU_RATETABLE_OFFSET_8814B)
+#define BIT_SET_MU_RATETABLE_OFFSET_8814B(x, v) \
+ (BIT_CLEAR_MU_RATETABLE_OFFSET_8814B(x) | \
+ BIT_MU_RATETABLE_OFFSET_8814B(v))
+
+#define BIT_SHIFT_MU_SCORETABLE_OFFSET_8814B 0
+#define BIT_MASK_MU_SCORETABLE_OFFSET_8814B 0x1ff
+#define BIT_MU_SCORETABLE_OFFSET_8814B(x) \
+ (((x) & BIT_MASK_MU_SCORETABLE_OFFSET_8814B) \
+ << BIT_SHIFT_MU_SCORETABLE_OFFSET_8814B)
+#define BITS_MU_SCORETABLE_OFFSET_8814B \
+ (BIT_MASK_MU_SCORETABLE_OFFSET_8814B \
+ << BIT_SHIFT_MU_SCORETABLE_OFFSET_8814B)
+#define BIT_CLEAR_MU_SCORETABLE_OFFSET_8814B(x) \
+ ((x) & (~BITS_MU_SCORETABLE_OFFSET_8814B))
+#define BIT_GET_MU_SCORETABLE_OFFSET_8814B(x) \
+ (((x) >> BIT_SHIFT_MU_SCORETABLE_OFFSET_8814B) & \
+ BIT_MASK_MU_SCORETABLE_OFFSET_8814B)
+#define BIT_SET_MU_SCORETABLE_OFFSET_8814B(x, v) \
+ (BIT_CLEAR_MU_SCORETABLE_OFFSET_8814B(x) | \
+ BIT_MU_SCORETABLE_OFFSET_8814B(v))
+
+/* 2 REG_USEREG_SETTING_8814B */
+
+/* 2 REG_BF0_TIME_SETTING_8814B */
+#define BIT_BF0_TIMER_SET_8814B BIT(31)
+#define BIT_BF0_TIMER_CLR_8814B BIT(30)
+#define BIT_BF0_UPDATE_EN_8814B BIT(29)
+#define BIT_BF0_TIMER_EN_8814B BIT(28)
+
+#define BIT_SHIFT_BF0_PRETIME_OVER_8814B 16
+#define BIT_MASK_BF0_PRETIME_OVER_8814B 0xfff
+#define BIT_BF0_PRETIME_OVER_8814B(x) \
+ (((x) & BIT_MASK_BF0_PRETIME_OVER_8814B) \
+ << BIT_SHIFT_BF0_PRETIME_OVER_8814B)
+#define BITS_BF0_PRETIME_OVER_8814B \
+ (BIT_MASK_BF0_PRETIME_OVER_8814B << BIT_SHIFT_BF0_PRETIME_OVER_8814B)
+#define BIT_CLEAR_BF0_PRETIME_OVER_8814B(x) \
+ ((x) & (~BITS_BF0_PRETIME_OVER_8814B))
+#define BIT_GET_BF0_PRETIME_OVER_8814B(x) \
+ (((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8814B) & \
+ BIT_MASK_BF0_PRETIME_OVER_8814B)
+#define BIT_SET_BF0_PRETIME_OVER_8814B(x, v) \
+ (BIT_CLEAR_BF0_PRETIME_OVER_8814B(x) | BIT_BF0_PRETIME_OVER_8814B(v))
+
+#define BIT_SHIFT_BF0_LIFETIME_8814B 0
+#define BIT_MASK_BF0_LIFETIME_8814B 0xffff
+#define BIT_BF0_LIFETIME_8814B(x) \
+ (((x) & BIT_MASK_BF0_LIFETIME_8814B) << BIT_SHIFT_BF0_LIFETIME_8814B)
+#define BITS_BF0_LIFETIME_8814B \
+ (BIT_MASK_BF0_LIFETIME_8814B << BIT_SHIFT_BF0_LIFETIME_8814B)
+#define BIT_CLEAR_BF0_LIFETIME_8814B(x) ((x) & (~BITS_BF0_LIFETIME_8814B))
+#define BIT_GET_BF0_LIFETIME_8814B(x) \
+ (((x) >> BIT_SHIFT_BF0_LIFETIME_8814B) & BIT_MASK_BF0_LIFETIME_8814B)
+#define BIT_SET_BF0_LIFETIME_8814B(x, v) \
+ (BIT_CLEAR_BF0_LIFETIME_8814B(x) | BIT_BF0_LIFETIME_8814B(v))
+
+/* 2 REG_BF1_TIME_SETTING_8814B */
+#define BIT_BF1_TIMER_SET_8814B BIT(31)
+#define BIT_BF1_TIMER_CLR_8814B BIT(30)
+#define BIT_BF1_UPDATE_EN_8814B BIT(29)
+#define BIT_BF1_TIMER_EN_8814B BIT(28)
+
+#define BIT_SHIFT_BF1_PRETIME_OVER_8814B 16
+#define BIT_MASK_BF1_PRETIME_OVER_8814B 0xfff
+#define BIT_BF1_PRETIME_OVER_8814B(x) \
+ (((x) & BIT_MASK_BF1_PRETIME_OVER_8814B) \
+ << BIT_SHIFT_BF1_PRETIME_OVER_8814B)
+#define BITS_BF1_PRETIME_OVER_8814B \
+ (BIT_MASK_BF1_PRETIME_OVER_8814B << BIT_SHIFT_BF1_PRETIME_OVER_8814B)
+#define BIT_CLEAR_BF1_PRETIME_OVER_8814B(x) \
+ ((x) & (~BITS_BF1_PRETIME_OVER_8814B))
+#define BIT_GET_BF1_PRETIME_OVER_8814B(x) \
+ (((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8814B) & \
+ BIT_MASK_BF1_PRETIME_OVER_8814B)
+#define BIT_SET_BF1_PRETIME_OVER_8814B(x, v) \
+ (BIT_CLEAR_BF1_PRETIME_OVER_8814B(x) | BIT_BF1_PRETIME_OVER_8814B(v))
+
+#define BIT_SHIFT_BF1_LIFETIME_8814B 0
+#define BIT_MASK_BF1_LIFETIME_8814B 0xffff
+#define BIT_BF1_LIFETIME_8814B(x) \
+ (((x) & BIT_MASK_BF1_LIFETIME_8814B) << BIT_SHIFT_BF1_LIFETIME_8814B)
+#define BITS_BF1_LIFETIME_8814B \
+ (BIT_MASK_BF1_LIFETIME_8814B << BIT_SHIFT_BF1_LIFETIME_8814B)
+#define BIT_CLEAR_BF1_LIFETIME_8814B(x) ((x) & (~BITS_BF1_LIFETIME_8814B))
+#define BIT_GET_BF1_LIFETIME_8814B(x) \
+ (((x) >> BIT_SHIFT_BF1_LIFETIME_8814B) & BIT_MASK_BF1_LIFETIME_8814B)
+#define BIT_SET_BF1_LIFETIME_8814B(x, v) \
+ (BIT_CLEAR_BF1_LIFETIME_8814B(x) | BIT_BF1_LIFETIME_8814B(v))
+
+/* 2 REG_BF_TIMEOUT_EN_8814B */
+#define BIT_EN_VHT_LDPC_8814B BIT(9)
+#define BIT_EN_HT_LDPC_8814B BIT(8)
+#define BIT_BF1_TIMEOUT_EN_8814B BIT(1)
+#define BIT_BF0_TIMEOUT_EN_8814B BIT(0)
+
+/* 2 REG_MACID_RELEASE_INFO_8814B */
+
+#define BIT_SHIFT_MACID_RELEASE_INFO_8814B 0
+#define BIT_MASK_MACID_RELEASE_INFO_8814B 0xffffffffL
+#define BIT_MACID_RELEASE_INFO_8814B(x) \
+ (((x) & BIT_MASK_MACID_RELEASE_INFO_8814B) \
+ << BIT_SHIFT_MACID_RELEASE_INFO_8814B)
+#define BITS_MACID_RELEASE_INFO_8814B \
+ (BIT_MASK_MACID_RELEASE_INFO_8814B \
+ << BIT_SHIFT_MACID_RELEASE_INFO_8814B)
+#define BIT_CLEAR_MACID_RELEASE_INFO_8814B(x) \
+ ((x) & (~BITS_MACID_RELEASE_INFO_8814B))
+#define BIT_GET_MACID_RELEASE_INFO_8814B(x) \
+ (((x) >> BIT_SHIFT_MACID_RELEASE_INFO_8814B) & \
+ BIT_MASK_MACID_RELEASE_INFO_8814B)
+#define BIT_SET_MACID_RELEASE_INFO_8814B(x, v) \
+ (BIT_CLEAR_MACID_RELEASE_INFO_8814B(x) | \
+ BIT_MACID_RELEASE_INFO_8814B(v))
+
+/* 2 REG_MACID_RELEASE_SUCCESS_INFO_8814B */
+
+#define BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO_8814B 0
+#define BIT_MASK_MACID_RELEASE_SUCCESS_INFO_8814B 0xffffffffL
+#define BIT_MACID_RELEASE_SUCCESS_INFO_8814B(x) \
+ (((x) & BIT_MASK_MACID_RELEASE_SUCCESS_INFO_8814B) \
+ << BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO_8814B)
+#define BITS_MACID_RELEASE_SUCCESS_INFO_8814B \
+ (BIT_MASK_MACID_RELEASE_SUCCESS_INFO_8814B \
+ << BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO_8814B)
+#define BIT_CLEAR_MACID_RELEASE_SUCCESS_INFO_8814B(x) \
+ ((x) & (~BITS_MACID_RELEASE_SUCCESS_INFO_8814B))
+#define BIT_GET_MACID_RELEASE_SUCCESS_INFO_8814B(x) \
+ (((x) >> BIT_SHIFT_MACID_RELEASE_SUCCESS_INFO_8814B) & \
+ BIT_MASK_MACID_RELEASE_SUCCESS_INFO_8814B)
+#define BIT_SET_MACID_RELEASE_SUCCESS_INFO_8814B(x, v) \
+ (BIT_CLEAR_MACID_RELEASE_SUCCESS_INFO_8814B(x) | \
+ BIT_MACID_RELEASE_SUCCESS_INFO_8814B(v))
+
+/* 2 REG_MACID_RELEASE_CTRL_8814B */
+
+#define BIT_SHIFT_MACID_RELEASE_SEL_8814B 24
+#define BIT_MASK_MACID_RELEASE_SEL_8814B 0x7
+#define BIT_MACID_RELEASE_SEL_8814B(x) \
+ (((x) & BIT_MASK_MACID_RELEASE_SEL_8814B) \
+ << BIT_SHIFT_MACID_RELEASE_SEL_8814B)
+#define BITS_MACID_RELEASE_SEL_8814B \
+ (BIT_MASK_MACID_RELEASE_SEL_8814B << BIT_SHIFT_MACID_RELEASE_SEL_8814B)
+#define BIT_CLEAR_MACID_RELEASE_SEL_8814B(x) \
+ ((x) & (~BITS_MACID_RELEASE_SEL_8814B))
+#define BIT_GET_MACID_RELEASE_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_MACID_RELEASE_SEL_8814B) & \
+ BIT_MASK_MACID_RELEASE_SEL_8814B)
+#define BIT_SET_MACID_RELEASE_SEL_8814B(x, v) \
+ (BIT_CLEAR_MACID_RELEASE_SEL_8814B(x) | BIT_MACID_RELEASE_SEL_8814B(v))
+
+#define BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET_8814B 16
+#define BIT_MASK_MACID_RELEASE_CLEAR_OFFSET_8814B 0xff
+#define BIT_MACID_RELEASE_CLEAR_OFFSET_8814B(x) \
+ (((x) & BIT_MASK_MACID_RELEASE_CLEAR_OFFSET_8814B) \
+ << BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET_8814B)
+#define BITS_MACID_RELEASE_CLEAR_OFFSET_8814B \
+ (BIT_MASK_MACID_RELEASE_CLEAR_OFFSET_8814B \
+ << BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET_8814B)
+#define BIT_CLEAR_MACID_RELEASE_CLEAR_OFFSET_8814B(x) \
+ ((x) & (~BITS_MACID_RELEASE_CLEAR_OFFSET_8814B))
+#define BIT_GET_MACID_RELEASE_CLEAR_OFFSET_8814B(x) \
+ (((x) >> BIT_SHIFT_MACID_RELEASE_CLEAR_OFFSET_8814B) & \
+ BIT_MASK_MACID_RELEASE_CLEAR_OFFSET_8814B)
+#define BIT_SET_MACID_RELEASE_CLEAR_OFFSET_8814B(x, v) \
+ (BIT_CLEAR_MACID_RELEASE_CLEAR_OFFSET_8814B(x) | \
+ BIT_MACID_RELEASE_CLEAR_OFFSET_8814B(v))
+
+#define BIT_MACID_RELEASE_VALUE_8814B BIT(8)
+
+#define BIT_SHIFT_MACID_RELEASE_OFFSET_8814B 0
+#define BIT_MASK_MACID_RELEASE_OFFSET_8814B 0xff
+#define BIT_MACID_RELEASE_OFFSET_8814B(x) \
+ (((x) & BIT_MASK_MACID_RELEASE_OFFSET_8814B) \
+ << BIT_SHIFT_MACID_RELEASE_OFFSET_8814B)
+#define BITS_MACID_RELEASE_OFFSET_8814B \
+ (BIT_MASK_MACID_RELEASE_OFFSET_8814B \
+ << BIT_SHIFT_MACID_RELEASE_OFFSET_8814B)
+#define BIT_CLEAR_MACID_RELEASE_OFFSET_8814B(x) \
+ ((x) & (~BITS_MACID_RELEASE_OFFSET_8814B))
+#define BIT_GET_MACID_RELEASE_OFFSET_8814B(x) \
+ (((x) >> BIT_SHIFT_MACID_RELEASE_OFFSET_8814B) & \
+ BIT_MASK_MACID_RELEASE_OFFSET_8814B)
+#define BIT_SET_MACID_RELEASE_OFFSET_8814B(x, v) \
+ (BIT_CLEAR_MACID_RELEASE_OFFSET_8814B(x) | \
+ BIT_MACID_RELEASE_OFFSET_8814B(v))
+
+/* 2 REG_FAST_EDCA_VOVI_SETTING_8814B */
+
+#define BIT_SHIFT_VI_FAST_EDCA_TO_8814B 24
+#define BIT_MASK_VI_FAST_EDCA_TO_8814B 0xff
+#define BIT_VI_FAST_EDCA_TO_8814B(x) \
+ (((x) & BIT_MASK_VI_FAST_EDCA_TO_8814B) \
+ << BIT_SHIFT_VI_FAST_EDCA_TO_8814B)
+#define BITS_VI_FAST_EDCA_TO_8814B \
+ (BIT_MASK_VI_FAST_EDCA_TO_8814B << BIT_SHIFT_VI_FAST_EDCA_TO_8814B)
+#define BIT_CLEAR_VI_FAST_EDCA_TO_8814B(x) ((x) & (~BITS_VI_FAST_EDCA_TO_8814B))
+#define BIT_GET_VI_FAST_EDCA_TO_8814B(x) \
+ (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8814B) & \
+ BIT_MASK_VI_FAST_EDCA_TO_8814B)
+#define BIT_SET_VI_FAST_EDCA_TO_8814B(x, v) \
+ (BIT_CLEAR_VI_FAST_EDCA_TO_8814B(x) | BIT_VI_FAST_EDCA_TO_8814B(v))
+
+#define BIT_VI_THRESHOLD_SEL_8814B BIT(23)
+
+#define BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8814B 16
+#define BIT_MASK_VI_FAST_EDCA_PKT_TH_8814B 0x7f
+#define BIT_VI_FAST_EDCA_PKT_TH_8814B(x) \
+ (((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8814B) \
+ << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8814B)
+#define BITS_VI_FAST_EDCA_PKT_TH_8814B \
+ (BIT_MASK_VI_FAST_EDCA_PKT_TH_8814B \
+ << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8814B)
+#define BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8814B(x) \
+ ((x) & (~BITS_VI_FAST_EDCA_PKT_TH_8814B))
+#define BIT_GET_VI_FAST_EDCA_PKT_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8814B) & \
+ BIT_MASK_VI_FAST_EDCA_PKT_TH_8814B)
+#define BIT_SET_VI_FAST_EDCA_PKT_TH_8814B(x, v) \
+ (BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8814B(x) | \
+ BIT_VI_FAST_EDCA_PKT_TH_8814B(v))
+
+#define BIT_SHIFT_VO_FAST_EDCA_TO_8814B 8
+#define BIT_MASK_VO_FAST_EDCA_TO_8814B 0xff
+#define BIT_VO_FAST_EDCA_TO_8814B(x) \
+ (((x) & BIT_MASK_VO_FAST_EDCA_TO_8814B) \
+ << BIT_SHIFT_VO_FAST_EDCA_TO_8814B)
+#define BITS_VO_FAST_EDCA_TO_8814B \
+ (BIT_MASK_VO_FAST_EDCA_TO_8814B << BIT_SHIFT_VO_FAST_EDCA_TO_8814B)
+#define BIT_CLEAR_VO_FAST_EDCA_TO_8814B(x) ((x) & (~BITS_VO_FAST_EDCA_TO_8814B))
+#define BIT_GET_VO_FAST_EDCA_TO_8814B(x) \
+ (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8814B) & \
+ BIT_MASK_VO_FAST_EDCA_TO_8814B)
+#define BIT_SET_VO_FAST_EDCA_TO_8814B(x, v) \
+ (BIT_CLEAR_VO_FAST_EDCA_TO_8814B(x) | BIT_VO_FAST_EDCA_TO_8814B(v))
+
+#define BIT_VO_THRESHOLD_SEL_8814B BIT(7)
+
+#define BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8814B 0
+#define BIT_MASK_VO_FAST_EDCA_PKT_TH_8814B 0x7f
+#define BIT_VO_FAST_EDCA_PKT_TH_8814B(x) \
+ (((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8814B) \
+ << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8814B)
+#define BITS_VO_FAST_EDCA_PKT_TH_8814B \
+ (BIT_MASK_VO_FAST_EDCA_PKT_TH_8814B \
+ << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8814B)
+#define BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8814B(x) \
+ ((x) & (~BITS_VO_FAST_EDCA_PKT_TH_8814B))
+#define BIT_GET_VO_FAST_EDCA_PKT_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8814B) & \
+ BIT_MASK_VO_FAST_EDCA_PKT_TH_8814B)
+#define BIT_SET_VO_FAST_EDCA_PKT_TH_8814B(x, v) \
+ (BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8814B(x) | \
+ BIT_VO_FAST_EDCA_PKT_TH_8814B(v))
+
+/* 2 REG_FAST_EDCA_BEBK_SETTING_8814B */
+
+#define BIT_SHIFT_BK_FAST_EDCA_TO_8814B 24
+#define BIT_MASK_BK_FAST_EDCA_TO_8814B 0xff
+#define BIT_BK_FAST_EDCA_TO_8814B(x) \
+ (((x) & BIT_MASK_BK_FAST_EDCA_TO_8814B) \
+ << BIT_SHIFT_BK_FAST_EDCA_TO_8814B)
+#define BITS_BK_FAST_EDCA_TO_8814B \
+ (BIT_MASK_BK_FAST_EDCA_TO_8814B << BIT_SHIFT_BK_FAST_EDCA_TO_8814B)
+#define BIT_CLEAR_BK_FAST_EDCA_TO_8814B(x) ((x) & (~BITS_BK_FAST_EDCA_TO_8814B))
+#define BIT_GET_BK_FAST_EDCA_TO_8814B(x) \
+ (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8814B) & \
+ BIT_MASK_BK_FAST_EDCA_TO_8814B)
+#define BIT_SET_BK_FAST_EDCA_TO_8814B(x, v) \
+ (BIT_CLEAR_BK_FAST_EDCA_TO_8814B(x) | BIT_BK_FAST_EDCA_TO_8814B(v))
+
+#define BIT_BK_THRESHOLD_SEL_8814B BIT(23)
+
+#define BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8814B 16
+#define BIT_MASK_BK_FAST_EDCA_PKT_TH_8814B 0x7f
+#define BIT_BK_FAST_EDCA_PKT_TH_8814B(x) \
+ (((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8814B) \
+ << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8814B)
+#define BITS_BK_FAST_EDCA_PKT_TH_8814B \
+ (BIT_MASK_BK_FAST_EDCA_PKT_TH_8814B \
+ << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8814B)
+#define BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8814B(x) \
+ ((x) & (~BITS_BK_FAST_EDCA_PKT_TH_8814B))
+#define BIT_GET_BK_FAST_EDCA_PKT_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8814B) & \
+ BIT_MASK_BK_FAST_EDCA_PKT_TH_8814B)
+#define BIT_SET_BK_FAST_EDCA_PKT_TH_8814B(x, v) \
+ (BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8814B(x) | \
+ BIT_BK_FAST_EDCA_PKT_TH_8814B(v))
+
+#define BIT_SHIFT_BE_FAST_EDCA_TO_8814B 8
+#define BIT_MASK_BE_FAST_EDCA_TO_8814B 0xff
+#define BIT_BE_FAST_EDCA_TO_8814B(x) \
+ (((x) & BIT_MASK_BE_FAST_EDCA_TO_8814B) \
+ << BIT_SHIFT_BE_FAST_EDCA_TO_8814B)
+#define BITS_BE_FAST_EDCA_TO_8814B \
+ (BIT_MASK_BE_FAST_EDCA_TO_8814B << BIT_SHIFT_BE_FAST_EDCA_TO_8814B)
+#define BIT_CLEAR_BE_FAST_EDCA_TO_8814B(x) ((x) & (~BITS_BE_FAST_EDCA_TO_8814B))
+#define BIT_GET_BE_FAST_EDCA_TO_8814B(x) \
+ (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8814B) & \
+ BIT_MASK_BE_FAST_EDCA_TO_8814B)
+#define BIT_SET_BE_FAST_EDCA_TO_8814B(x, v) \
+ (BIT_CLEAR_BE_FAST_EDCA_TO_8814B(x) | BIT_BE_FAST_EDCA_TO_8814B(v))
+
+#define BIT_BE_THRESHOLD_SEL_8814B BIT(7)
+
+#define BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8814B 0
+#define BIT_MASK_BE_FAST_EDCA_PKT_TH_8814B 0x7f
+#define BIT_BE_FAST_EDCA_PKT_TH_8814B(x) \
+ (((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8814B) \
+ << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8814B)
+#define BITS_BE_FAST_EDCA_PKT_TH_8814B \
+ (BIT_MASK_BE_FAST_EDCA_PKT_TH_8814B \
+ << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8814B)
+#define BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8814B(x) \
+ ((x) & (~BITS_BE_FAST_EDCA_PKT_TH_8814B))
+#define BIT_GET_BE_FAST_EDCA_PKT_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8814B) & \
+ BIT_MASK_BE_FAST_EDCA_PKT_TH_8814B)
+#define BIT_SET_BE_FAST_EDCA_PKT_TH_8814B(x, v) \
+ (BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8814B(x) | \
+ BIT_BE_FAST_EDCA_PKT_TH_8814B(v))
+
+/* 2 REG_MACID_DROP_INFO_8814B */
+
+#define BIT_SHIFT_MACID_DROP_INFO_8814B 0
+#define BIT_MASK_MACID_DROP_INFO_8814B 0xffffffffL
+#define BIT_MACID_DROP_INFO_8814B(x) \
+ (((x) & BIT_MASK_MACID_DROP_INFO_8814B) \
+ << BIT_SHIFT_MACID_DROP_INFO_8814B)
+#define BITS_MACID_DROP_INFO_8814B \
+ (BIT_MASK_MACID_DROP_INFO_8814B << BIT_SHIFT_MACID_DROP_INFO_8814B)
+#define BIT_CLEAR_MACID_DROP_INFO_8814B(x) ((x) & (~BITS_MACID_DROP_INFO_8814B))
+#define BIT_GET_MACID_DROP_INFO_8814B(x) \
+ (((x) >> BIT_SHIFT_MACID_DROP_INFO_8814B) & \
+ BIT_MASK_MACID_DROP_INFO_8814B)
+#define BIT_SET_MACID_DROP_INFO_8814B(x, v) \
+ (BIT_CLEAR_MACID_DROP_INFO_8814B(x) | BIT_MACID_DROP_INFO_8814B(v))
+
+/* 2 REG_MACID_DROP_CTRL_8814B */
+
+#define BIT_SHIFT_MACID_DROP_SEL_8814B 0
+#define BIT_MASK_MACID_DROP_SEL_8814B 0x7
+#define BIT_MACID_DROP_SEL_8814B(x) \
+ (((x) & BIT_MASK_MACID_DROP_SEL_8814B) \
+ << BIT_SHIFT_MACID_DROP_SEL_8814B)
+#define BITS_MACID_DROP_SEL_8814B \
+ (BIT_MASK_MACID_DROP_SEL_8814B << BIT_SHIFT_MACID_DROP_SEL_8814B)
+#define BIT_CLEAR_MACID_DROP_SEL_8814B(x) ((x) & (~BITS_MACID_DROP_SEL_8814B))
+#define BIT_GET_MACID_DROP_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_MACID_DROP_SEL_8814B) & \
+ BIT_MASK_MACID_DROP_SEL_8814B)
+#define BIT_SET_MACID_DROP_SEL_8814B(x, v) \
+ (BIT_CLEAR_MACID_DROP_SEL_8814B(x) | BIT_MACID_DROP_SEL_8814B(v))
+
+/* 2 REG_MGQ_FIFO_WRITE_POINTER_8814B */
+#define BIT_MGQ_FIFO_OV_8814B BIT(7)
+#define BIT_MGQ_FIFO_WPTR_ERROR_8814B BIT(6)
+#define BIT_EN_MGQ_FIFO_LIFETIME_8814B BIT(5)
+
+#define BIT_SHIFT_MGQ_FIFO_WPTR_8814B 0
+#define BIT_MASK_MGQ_FIFO_WPTR_8814B 0x1f
+#define BIT_MGQ_FIFO_WPTR_8814B(x) \
+ (((x) & BIT_MASK_MGQ_FIFO_WPTR_8814B) << BIT_SHIFT_MGQ_FIFO_WPTR_8814B)
+#define BITS_MGQ_FIFO_WPTR_8814B \
+ (BIT_MASK_MGQ_FIFO_WPTR_8814B << BIT_SHIFT_MGQ_FIFO_WPTR_8814B)
+#define BIT_CLEAR_MGQ_FIFO_WPTR_8814B(x) ((x) & (~BITS_MGQ_FIFO_WPTR_8814B))
+#define BIT_GET_MGQ_FIFO_WPTR_8814B(x) \
+ (((x) >> BIT_SHIFT_MGQ_FIFO_WPTR_8814B) & BIT_MASK_MGQ_FIFO_WPTR_8814B)
+#define BIT_SET_MGQ_FIFO_WPTR_8814B(x, v) \
+ (BIT_CLEAR_MGQ_FIFO_WPTR_8814B(x) | BIT_MGQ_FIFO_WPTR_8814B(v))
+
+/* 2 REG_MGQ_FIFO_READ_POINTER_8814B */
+
+#define BIT_SHIFT_MGQ_FIFO_SIZE_8814B 14
+#define BIT_MASK_MGQ_FIFO_SIZE_8814B 0x3
+#define BIT_MGQ_FIFO_SIZE_8814B(x) \
+ (((x) & BIT_MASK_MGQ_FIFO_SIZE_8814B) << BIT_SHIFT_MGQ_FIFO_SIZE_8814B)
+#define BITS_MGQ_FIFO_SIZE_8814B \
+ (BIT_MASK_MGQ_FIFO_SIZE_8814B << BIT_SHIFT_MGQ_FIFO_SIZE_8814B)
+#define BIT_CLEAR_MGQ_FIFO_SIZE_8814B(x) ((x) & (~BITS_MGQ_FIFO_SIZE_8814B))
+#define BIT_GET_MGQ_FIFO_SIZE_8814B(x) \
+ (((x) >> BIT_SHIFT_MGQ_FIFO_SIZE_8814B) & BIT_MASK_MGQ_FIFO_SIZE_8814B)
+#define BIT_SET_MGQ_FIFO_SIZE_8814B(x, v) \
+ (BIT_CLEAR_MGQ_FIFO_SIZE_8814B(x) | BIT_MGQ_FIFO_SIZE_8814B(v))
+
+#define BIT_MGQ_FIFO_PAUSE_8814B BIT(13)
+
+#define BIT_SHIFT_MGQ_FIFO_RPTR_8814B 8
+#define BIT_MASK_MGQ_FIFO_RPTR_8814B 0x1f
+#define BIT_MGQ_FIFO_RPTR_8814B(x) \
+ (((x) & BIT_MASK_MGQ_FIFO_RPTR_8814B) << BIT_SHIFT_MGQ_FIFO_RPTR_8814B)
+#define BITS_MGQ_FIFO_RPTR_8814B \
+ (BIT_MASK_MGQ_FIFO_RPTR_8814B << BIT_SHIFT_MGQ_FIFO_RPTR_8814B)
+#define BIT_CLEAR_MGQ_FIFO_RPTR_8814B(x) ((x) & (~BITS_MGQ_FIFO_RPTR_8814B))
+#define BIT_GET_MGQ_FIFO_RPTR_8814B(x) \
+ (((x) >> BIT_SHIFT_MGQ_FIFO_RPTR_8814B) & BIT_MASK_MGQ_FIFO_RPTR_8814B)
+#define BIT_SET_MGQ_FIFO_RPTR_8814B(x, v) \
+ (BIT_CLEAR_MGQ_FIFO_RPTR_8814B(x) | BIT_MGQ_FIFO_RPTR_8814B(v))
+
+/* 2 REG_MGQ_FIFO_ENABLE_8814B */
+#define BIT_MGQ_FIFO_EN_V1_8814B BIT(15)
+
+#define BIT_SHIFT_MGQ_FIFO_PG_SIZE_8814B 12
+#define BIT_MASK_MGQ_FIFO_PG_SIZE_8814B 0x7
+#define BIT_MGQ_FIFO_PG_SIZE_8814B(x) \
+ (((x) & BIT_MASK_MGQ_FIFO_PG_SIZE_8814B) \
+ << BIT_SHIFT_MGQ_FIFO_PG_SIZE_8814B)
+#define BITS_MGQ_FIFO_PG_SIZE_8814B \
+ (BIT_MASK_MGQ_FIFO_PG_SIZE_8814B << BIT_SHIFT_MGQ_FIFO_PG_SIZE_8814B)
+#define BIT_CLEAR_MGQ_FIFO_PG_SIZE_8814B(x) \
+ ((x) & (~BITS_MGQ_FIFO_PG_SIZE_8814B))
+#define BIT_GET_MGQ_FIFO_PG_SIZE_8814B(x) \
+ (((x) >> BIT_SHIFT_MGQ_FIFO_PG_SIZE_8814B) & \
+ BIT_MASK_MGQ_FIFO_PG_SIZE_8814B)
+#define BIT_SET_MGQ_FIFO_PG_SIZE_8814B(x, v) \
+ (BIT_CLEAR_MGQ_FIFO_PG_SIZE_8814B(x) | BIT_MGQ_FIFO_PG_SIZE_8814B(v))
+
+#define BIT_SHIFT_MGQ_FIFO_START_PG_8814B 0
+#define BIT_MASK_MGQ_FIFO_START_PG_8814B 0xfff
+#define BIT_MGQ_FIFO_START_PG_8814B(x) \
+ (((x) & BIT_MASK_MGQ_FIFO_START_PG_8814B) \
+ << BIT_SHIFT_MGQ_FIFO_START_PG_8814B)
+#define BITS_MGQ_FIFO_START_PG_8814B \
+ (BIT_MASK_MGQ_FIFO_START_PG_8814B << BIT_SHIFT_MGQ_FIFO_START_PG_8814B)
+#define BIT_CLEAR_MGQ_FIFO_START_PG_8814B(x) \
+ ((x) & (~BITS_MGQ_FIFO_START_PG_8814B))
+#define BIT_GET_MGQ_FIFO_START_PG_8814B(x) \
+ (((x) >> BIT_SHIFT_MGQ_FIFO_START_PG_8814B) & \
+ BIT_MASK_MGQ_FIFO_START_PG_8814B)
+#define BIT_SET_MGQ_FIFO_START_PG_8814B(x, v) \
+ (BIT_CLEAR_MGQ_FIFO_START_PG_8814B(x) | BIT_MGQ_FIFO_START_PG_8814B(v))
+
+/* 2 REG_MGQ_FIFO_RELEASE_INT_MASK_8814B */
+
+#define BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8814B 0
+#define BIT_MASK_MGQ_FIFO_REL_INT_MASK_8814B 0xffff
+#define BIT_MGQ_FIFO_REL_INT_MASK_8814B(x) \
+ (((x) & BIT_MASK_MGQ_FIFO_REL_INT_MASK_8814B) \
+ << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8814B)
+#define BITS_MGQ_FIFO_REL_INT_MASK_8814B \
+ (BIT_MASK_MGQ_FIFO_REL_INT_MASK_8814B \
+ << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8814B)
+#define BIT_CLEAR_MGQ_FIFO_REL_INT_MASK_8814B(x) \
+ ((x) & (~BITS_MGQ_FIFO_REL_INT_MASK_8814B))
+#define BIT_GET_MGQ_FIFO_REL_INT_MASK_8814B(x) \
+ (((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8814B) & \
+ BIT_MASK_MGQ_FIFO_REL_INT_MASK_8814B)
+#define BIT_SET_MGQ_FIFO_REL_INT_MASK_8814B(x, v) \
+ (BIT_CLEAR_MGQ_FIFO_REL_INT_MASK_8814B(x) | \
+ BIT_MGQ_FIFO_REL_INT_MASK_8814B(v))
+
+/* 2 REG_MGQ_FIFO_RELEASE_INT_FLAG_8814B */
+
+#define BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8814B 0
+#define BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8814B 0xffff
+#define BIT_MGQ_FIFO_REL_INT_FLAG_8814B(x) \
+ (((x) & BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8814B) \
+ << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8814B)
+#define BITS_MGQ_FIFO_REL_INT_FLAG_8814B \
+ (BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8814B \
+ << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8814B)
+#define BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG_8814B(x) \
+ ((x) & (~BITS_MGQ_FIFO_REL_INT_FLAG_8814B))
+#define BIT_GET_MGQ_FIFO_REL_INT_FLAG_8814B(x) \
+ (((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8814B) & \
+ BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8814B)
+#define BIT_SET_MGQ_FIFO_REL_INT_FLAG_8814B(x, v) \
+ (BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG_8814B(x) | \
+ BIT_MGQ_FIFO_REL_INT_FLAG_8814B(v))
+
+/* 2 REG_MGQ_FIFO_VALID_MAP_8814B */
+
+#define BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8814B 0
+#define BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8814B 0xffff
+#define BIT_MGQ_FIFO_PKT_VALID_MAP_8814B(x) \
+ (((x) & BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8814B) \
+ << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8814B)
+#define BITS_MGQ_FIFO_PKT_VALID_MAP_8814B \
+ (BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8814B \
+ << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8814B)
+#define BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP_8814B(x) \
+ ((x) & (~BITS_MGQ_FIFO_PKT_VALID_MAP_8814B))
+#define BIT_GET_MGQ_FIFO_PKT_VALID_MAP_8814B(x) \
+ (((x) >> BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8814B) & \
+ BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8814B)
+#define BIT_SET_MGQ_FIFO_PKT_VALID_MAP_8814B(x, v) \
+ (BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP_8814B(x) | \
+ BIT_MGQ_FIFO_PKT_VALID_MAP_8814B(v))
+
+/* 2 REG_MGQ_FIFO_LIFETIME_8814B */
+
+#define BIT_SHIFT_MGQ_FIFO_LIFETIME_8814B 0
+#define BIT_MASK_MGQ_FIFO_LIFETIME_8814B 0xffff
+#define BIT_MGQ_FIFO_LIFETIME_8814B(x) \
+ (((x) & BIT_MASK_MGQ_FIFO_LIFETIME_8814B) \
+ << BIT_SHIFT_MGQ_FIFO_LIFETIME_8814B)
+#define BITS_MGQ_FIFO_LIFETIME_8814B \
+ (BIT_MASK_MGQ_FIFO_LIFETIME_8814B << BIT_SHIFT_MGQ_FIFO_LIFETIME_8814B)
+#define BIT_CLEAR_MGQ_FIFO_LIFETIME_8814B(x) \
+ ((x) & (~BITS_MGQ_FIFO_LIFETIME_8814B))
+#define BIT_GET_MGQ_FIFO_LIFETIME_8814B(x) \
+ (((x) >> BIT_SHIFT_MGQ_FIFO_LIFETIME_8814B) & \
+ BIT_MASK_MGQ_FIFO_LIFETIME_8814B)
+#define BIT_SET_MGQ_FIFO_LIFETIME_8814B(x, v) \
+ (BIT_CLEAR_MGQ_FIFO_LIFETIME_8814B(x) | BIT_MGQ_FIFO_LIFETIME_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_PKT_TRANS_8814B */
+
+#define BIT_SHIFT_IE_DESC_OFFSET_8814B 16
+#define BIT_MASK_IE_DESC_OFFSET_8814B 0x1ff
+#define BIT_IE_DESC_OFFSET_8814B(x) \
+ (((x) & BIT_MASK_IE_DESC_OFFSET_8814B) \
+ << BIT_SHIFT_IE_DESC_OFFSET_8814B)
+#define BITS_IE_DESC_OFFSET_8814B \
+ (BIT_MASK_IE_DESC_OFFSET_8814B << BIT_SHIFT_IE_DESC_OFFSET_8814B)
+#define BIT_CLEAR_IE_DESC_OFFSET_8814B(x) ((x) & (~BITS_IE_DESC_OFFSET_8814B))
+#define BIT_GET_IE_DESC_OFFSET_8814B(x) \
+ (((x) >> BIT_SHIFT_IE_DESC_OFFSET_8814B) & \
+ BIT_MASK_IE_DESC_OFFSET_8814B)
+#define BIT_SET_IE_DESC_OFFSET_8814B(x, v) \
+ (BIT_CLEAR_IE_DESC_OFFSET_8814B(x) | BIT_IE_DESC_OFFSET_8814B(v))
+
+#define BIT_DIS_FWCMD_PATH_ERRCHK_8814B BIT(13)
+#define BIT_MAC_HDR_CONVERT_EN_8814B BIT(12)
+#define BIT_TXDESC_TRANS_EN_8814B BIT(8)
+#define BIT_PKT_TRANS_ERRINT_EN_8814B BIT(7)
+
+#define BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL_8814B 4
+#define BIT_MASK_PKT_TRANS_ERR_MACID_SEL_8814B 0x3
+#define BIT_PKT_TRANS_ERR_MACID_SEL_8814B(x) \
+ (((x) & BIT_MASK_PKT_TRANS_ERR_MACID_SEL_8814B) \
+ << BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL_8814B)
+#define BITS_PKT_TRANS_ERR_MACID_SEL_8814B \
+ (BIT_MASK_PKT_TRANS_ERR_MACID_SEL_8814B \
+ << BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL_8814B)
+#define BIT_CLEAR_PKT_TRANS_ERR_MACID_SEL_8814B(x) \
+ ((x) & (~BITS_PKT_TRANS_ERR_MACID_SEL_8814B))
+#define BIT_GET_PKT_TRANS_ERR_MACID_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_PKT_TRANS_ERR_MACID_SEL_8814B) & \
+ BIT_MASK_PKT_TRANS_ERR_MACID_SEL_8814B)
+#define BIT_SET_PKT_TRANS_ERR_MACID_SEL_8814B(x, v) \
+ (BIT_CLEAR_PKT_TRANS_ERR_MACID_SEL_8814B(x) | \
+ BIT_PKT_TRANS_ERR_MACID_SEL_8814B(v))
+
+#define BIT_PKT_TRANS_IEINIT_ERR_8814B BIT(3)
+#define BIT_PKT_TRANS_IENUM_ERR_8814B BIT(2)
+#define BIT_PKT_TRANS_IECNT_ERR1_8814B BIT(1)
+#define BIT_PKT_TRANS_IECNT_ERR0_8814B BIT(0)
+
+/* 2 REG_SHCUT_LLC_ETH_TYPE0_8814B */
+
+/* 2 REG_SHCUT_LLC_ETH_TYPE1_8814B */
+
+#define BIT_SHIFT_SHCUT_MHDR_OFFSET_8814B 16
+#define BIT_MASK_SHCUT_MHDR_OFFSET_8814B 0x1ff
+#define BIT_SHCUT_MHDR_OFFSET_8814B(x) \
+ (((x) & BIT_MASK_SHCUT_MHDR_OFFSET_8814B) \
+ << BIT_SHIFT_SHCUT_MHDR_OFFSET_8814B)
+#define BITS_SHCUT_MHDR_OFFSET_8814B \
+ (BIT_MASK_SHCUT_MHDR_OFFSET_8814B << BIT_SHIFT_SHCUT_MHDR_OFFSET_8814B)
+#define BIT_CLEAR_SHCUT_MHDR_OFFSET_8814B(x) \
+ ((x) & (~BITS_SHCUT_MHDR_OFFSET_8814B))
+#define BIT_GET_SHCUT_MHDR_OFFSET_8814B(x) \
+ (((x) >> BIT_SHIFT_SHCUT_MHDR_OFFSET_8814B) & \
+ BIT_MASK_SHCUT_MHDR_OFFSET_8814B)
+#define BIT_SET_SHCUT_MHDR_OFFSET_8814B(x, v) \
+ (BIT_CLEAR_SHCUT_MHDR_OFFSET_8814B(x) | BIT_SHCUT_MHDR_OFFSET_8814B(v))
+
+/* 2 REG_SHCUT_LLC_OUI0_8814B */
+
+/* 2 REG_SHCUT_LLC_OUI1_8814B */
+
+/* 2 REG_SHCUT_LLC_OUI2_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_PKT_TRANS_ERR_MACID_8814B 0
+#define BIT_MASK_PKT_TRANS_ERR_MACID_8814B 0xffffffffL
+#define BIT_PKT_TRANS_ERR_MACID_8814B(x) \
+ (((x) & BIT_MASK_PKT_TRANS_ERR_MACID_8814B) \
+ << BIT_SHIFT_PKT_TRANS_ERR_MACID_8814B)
+#define BITS_PKT_TRANS_ERR_MACID_8814B \
+ (BIT_MASK_PKT_TRANS_ERR_MACID_8814B \
+ << BIT_SHIFT_PKT_TRANS_ERR_MACID_8814B)
+#define BIT_CLEAR_PKT_TRANS_ERR_MACID_8814B(x) \
+ ((x) & (~BITS_PKT_TRANS_ERR_MACID_8814B))
+#define BIT_GET_PKT_TRANS_ERR_MACID_8814B(x) \
+ (((x) >> BIT_SHIFT_PKT_TRANS_ERR_MACID_8814B) & \
+ BIT_MASK_PKT_TRANS_ERR_MACID_8814B)
+#define BIT_SET_PKT_TRANS_ERR_MACID_8814B(x, v) \
+ (BIT_CLEAR_PKT_TRANS_ERR_MACID_8814B(x) | \
+ BIT_PKT_TRANS_ERR_MACID_8814B(v))
+
+/* 2 REG_FWCMDQ_CTRL_8814B */
+#define BIT_FW_RELEASEPKT_POLLING_8814B BIT(31)
+
+#define BIT_SHIFT_FWCMDQ_RELEASE_HEAD_8814B 16
+#define BIT_MASK_FWCMDQ_RELEASE_HEAD_8814B 0xfff
+#define BIT_FWCMDQ_RELEASE_HEAD_8814B(x) \
+ (((x) & BIT_MASK_FWCMDQ_RELEASE_HEAD_8814B) \
+ << BIT_SHIFT_FWCMDQ_RELEASE_HEAD_8814B)
+#define BITS_FWCMDQ_RELEASE_HEAD_8814B \
+ (BIT_MASK_FWCMDQ_RELEASE_HEAD_8814B \
+ << BIT_SHIFT_FWCMDQ_RELEASE_HEAD_8814B)
+#define BIT_CLEAR_FWCMDQ_RELEASE_HEAD_8814B(x) \
+ ((x) & (~BITS_FWCMDQ_RELEASE_HEAD_8814B))
+#define BIT_GET_FWCMDQ_RELEASE_HEAD_8814B(x) \
+ (((x) >> BIT_SHIFT_FWCMDQ_RELEASE_HEAD_8814B) & \
+ BIT_MASK_FWCMDQ_RELEASE_HEAD_8814B)
+#define BIT_SET_FWCMDQ_RELEASE_HEAD_8814B(x, v) \
+ (BIT_CLEAR_FWCMDQ_RELEASE_HEAD_8814B(x) | \
+ BIT_FWCMDQ_RELEASE_HEAD_8814B(v))
+
+#define BIT_FW_GETPKTT_POLLING_8814B BIT(15)
+
+#define BIT_SHIFT_FWCMDQ_H_8814B 0
+#define BIT_MASK_FWCMDQ_H_8814B 0xfff
+#define BIT_FWCMDQ_H_8814B(x) \
+ (((x) & BIT_MASK_FWCMDQ_H_8814B) << BIT_SHIFT_FWCMDQ_H_8814B)
+#define BITS_FWCMDQ_H_8814B \
+ (BIT_MASK_FWCMDQ_H_8814B << BIT_SHIFT_FWCMDQ_H_8814B)
+#define BIT_CLEAR_FWCMDQ_H_8814B(x) ((x) & (~BITS_FWCMDQ_H_8814B))
+#define BIT_GET_FWCMDQ_H_8814B(x) \
+ (((x) >> BIT_SHIFT_FWCMDQ_H_8814B) & BIT_MASK_FWCMDQ_H_8814B)
+#define BIT_SET_FWCMDQ_H_8814B(x, v) \
+ (BIT_CLEAR_FWCMDQ_H_8814B(x) | BIT_FWCMDQ_H_8814B(v))
+
+/* 2 REG_FWCMDQ_PAGE_8814B */
+
+#define BIT_SHIFT_FWCMDQ_TOTAL_PAGE_8814B 16
+#define BIT_MASK_FWCMDQ_TOTAL_PAGE_8814B 0xfff
+#define BIT_FWCMDQ_TOTAL_PAGE_8814B(x) \
+ (((x) & BIT_MASK_FWCMDQ_TOTAL_PAGE_8814B) \
+ << BIT_SHIFT_FWCMDQ_TOTAL_PAGE_8814B)
+#define BITS_FWCMDQ_TOTAL_PAGE_8814B \
+ (BIT_MASK_FWCMDQ_TOTAL_PAGE_8814B << BIT_SHIFT_FWCMDQ_TOTAL_PAGE_8814B)
+#define BIT_CLEAR_FWCMDQ_TOTAL_PAGE_8814B(x) \
+ ((x) & (~BITS_FWCMDQ_TOTAL_PAGE_8814B))
+#define BIT_GET_FWCMDQ_TOTAL_PAGE_8814B(x) \
+ (((x) >> BIT_SHIFT_FWCMDQ_TOTAL_PAGE_8814B) & \
+ BIT_MASK_FWCMDQ_TOTAL_PAGE_8814B)
+#define BIT_SET_FWCMDQ_TOTAL_PAGE_8814B(x, v) \
+ (BIT_CLEAR_FWCMDQ_TOTAL_PAGE_8814B(x) | BIT_FWCMDQ_TOTAL_PAGE_8814B(v))
+
+#define BIT_SHIFT_FWCMDQ_QUEUE_PAGE_8814B 0
+#define BIT_MASK_FWCMDQ_QUEUE_PAGE_8814B 0xfff
+#define BIT_FWCMDQ_QUEUE_PAGE_8814B(x) \
+ (((x) & BIT_MASK_FWCMDQ_QUEUE_PAGE_8814B) \
+ << BIT_SHIFT_FWCMDQ_QUEUE_PAGE_8814B)
+#define BITS_FWCMDQ_QUEUE_PAGE_8814B \
+ (BIT_MASK_FWCMDQ_QUEUE_PAGE_8814B << BIT_SHIFT_FWCMDQ_QUEUE_PAGE_8814B)
+#define BIT_CLEAR_FWCMDQ_QUEUE_PAGE_8814B(x) \
+ ((x) & (~BITS_FWCMDQ_QUEUE_PAGE_8814B))
+#define BIT_GET_FWCMDQ_QUEUE_PAGE_8814B(x) \
+ (((x) >> BIT_SHIFT_FWCMDQ_QUEUE_PAGE_8814B) & \
+ BIT_MASK_FWCMDQ_QUEUE_PAGE_8814B)
+#define BIT_SET_FWCMDQ_QUEUE_PAGE_8814B(x, v) \
+ (BIT_CLEAR_FWCMDQ_QUEUE_PAGE_8814B(x) | BIT_FWCMDQ_QUEUE_PAGE_8814B(v))
+
+/* 2 REG_FWCMDQ_INFO_8814B */
+#define BIT_FWCMD_READY_8814B BIT(31)
+#define BIT_FWCMDQ_OVERFLOW_8814B BIT(30)
+#define BIT_FWCMDQ_UNDERFLOW_8814B BIT(29)
+#define BIT_FWCMDQ_RELEASE_MISS_8814B BIT(28)
+
+#define BIT_SHIFT_FWCMDQ_TOTAL_PKT_8814B 16
+#define BIT_MASK_FWCMDQ_TOTAL_PKT_8814B 0xfff
+#define BIT_FWCMDQ_TOTAL_PKT_8814B(x) \
+ (((x) & BIT_MASK_FWCMDQ_TOTAL_PKT_8814B) \
+ << BIT_SHIFT_FWCMDQ_TOTAL_PKT_8814B)
+#define BITS_FWCMDQ_TOTAL_PKT_8814B \
+ (BIT_MASK_FWCMDQ_TOTAL_PKT_8814B << BIT_SHIFT_FWCMDQ_TOTAL_PKT_8814B)
+#define BIT_CLEAR_FWCMDQ_TOTAL_PKT_8814B(x) \
+ ((x) & (~BITS_FWCMDQ_TOTAL_PKT_8814B))
+#define BIT_GET_FWCMDQ_TOTAL_PKT_8814B(x) \
+ (((x) >> BIT_SHIFT_FWCMDQ_TOTAL_PKT_8814B) & \
+ BIT_MASK_FWCMDQ_TOTAL_PKT_8814B)
+#define BIT_SET_FWCMDQ_TOTAL_PKT_8814B(x, v) \
+ (BIT_CLEAR_FWCMDQ_TOTAL_PKT_8814B(x) | BIT_FWCMDQ_TOTAL_PKT_8814B(v))
+
+#define BIT_SHIFT_FWCMDQ_QUEUE_PKT_8814B 0
+#define BIT_MASK_FWCMDQ_QUEUE_PKT_8814B 0xfff
+#define BIT_FWCMDQ_QUEUE_PKT_8814B(x) \
+ (((x) & BIT_MASK_FWCMDQ_QUEUE_PKT_8814B) \
+ << BIT_SHIFT_FWCMDQ_QUEUE_PKT_8814B)
+#define BITS_FWCMDQ_QUEUE_PKT_8814B \
+ (BIT_MASK_FWCMDQ_QUEUE_PKT_8814B << BIT_SHIFT_FWCMDQ_QUEUE_PKT_8814B)
+#define BIT_CLEAR_FWCMDQ_QUEUE_PKT_8814B(x) \
+ ((x) & (~BITS_FWCMDQ_QUEUE_PKT_8814B))
+#define BIT_GET_FWCMDQ_QUEUE_PKT_8814B(x) \
+ (((x) >> BIT_SHIFT_FWCMDQ_QUEUE_PKT_8814B) & \
+ BIT_MASK_FWCMDQ_QUEUE_PKT_8814B)
+#define BIT_SET_FWCMDQ_QUEUE_PKT_8814B(x, v) \
+ (BIT_CLEAR_FWCMDQ_QUEUE_PKT_8814B(x) | BIT_FWCMDQ_QUEUE_PKT_8814B(v))
+
+/* 2 REG_FWCMDQ_HOLD_PKTNUM_8814B */
+
+#define BIT_SHIFT_FWCMDQ_HOLD__PKTNUM_8814B 0
+#define BIT_MASK_FWCMDQ_HOLD__PKTNUM_8814B 0xfff
+#define BIT_FWCMDQ_HOLD__PKTNUM_8814B(x) \
+ (((x) & BIT_MASK_FWCMDQ_HOLD__PKTNUM_8814B) \
+ << BIT_SHIFT_FWCMDQ_HOLD__PKTNUM_8814B)
+#define BITS_FWCMDQ_HOLD__PKTNUM_8814B \
+ (BIT_MASK_FWCMDQ_HOLD__PKTNUM_8814B \
+ << BIT_SHIFT_FWCMDQ_HOLD__PKTNUM_8814B)
+#define BIT_CLEAR_FWCMDQ_HOLD__PKTNUM_8814B(x) \
+ ((x) & (~BITS_FWCMDQ_HOLD__PKTNUM_8814B))
+#define BIT_GET_FWCMDQ_HOLD__PKTNUM_8814B(x) \
+ (((x) >> BIT_SHIFT_FWCMDQ_HOLD__PKTNUM_8814B) & \
+ BIT_MASK_FWCMDQ_HOLD__PKTNUM_8814B)
+#define BIT_SET_FWCMDQ_HOLD__PKTNUM_8814B(x, v) \
+ (BIT_CLEAR_FWCMDQ_HOLD__PKTNUM_8814B(x) | \
+ BIT_FWCMDQ_HOLD__PKTNUM_8814B(v))
+
+/* 2 REG_MU_TX_CTRL_8814B */
+#define BIT_SEARCH_DONE_RDY_8814B BIT(31)
+#define BIT_MU_EN_8814B BIT(30)
+#define BIT_MU_SECONDARY_WAITMODE_EN_8814B BIT(29)
+#define BIT_MU_BB_SCORE_EN_8814B BIT(28)
+#define BIT_MU_SECONDARY_ANT_COUNT_EN_8814B BIT(27)
+#define BIT_MUARB_SEARCH_ERR_EN_8814B BIT(26)
+
+#define BIT_SHIFT_DIS_SU_TXBF_8814B 16
+#define BIT_MASK_DIS_SU_TXBF_8814B 0x3f
+#define BIT_DIS_SU_TXBF_8814B(x) \
+ (((x) & BIT_MASK_DIS_SU_TXBF_8814B) << BIT_SHIFT_DIS_SU_TXBF_8814B)
+#define BITS_DIS_SU_TXBF_8814B \
+ (BIT_MASK_DIS_SU_TXBF_8814B << BIT_SHIFT_DIS_SU_TXBF_8814B)
+#define BIT_CLEAR_DIS_SU_TXBF_8814B(x) ((x) & (~BITS_DIS_SU_TXBF_8814B))
+#define BIT_GET_DIS_SU_TXBF_8814B(x) \
+ (((x) >> BIT_SHIFT_DIS_SU_TXBF_8814B) & BIT_MASK_DIS_SU_TXBF_8814B)
+#define BIT_SET_DIS_SU_TXBF_8814B(x, v) \
+ (BIT_CLEAR_DIS_SU_TXBF_8814B(x) | BIT_DIS_SU_TXBF_8814B(v))
+
+#define BIT_SHIFT_MU_RL_8814B 12
+#define BIT_MASK_MU_RL_8814B 0xf
+#define BIT_MU_RL_8814B(x) \
+ (((x) & BIT_MASK_MU_RL_8814B) << BIT_SHIFT_MU_RL_8814B)
+#define BITS_MU_RL_8814B (BIT_MASK_MU_RL_8814B << BIT_SHIFT_MU_RL_8814B)
+#define BIT_CLEAR_MU_RL_8814B(x) ((x) & (~BITS_MU_RL_8814B))
+#define BIT_GET_MU_RL_8814B(x) \
+ (((x) >> BIT_SHIFT_MU_RL_8814B) & BIT_MASK_MU_RL_8814B)
+#define BIT_SET_MU_RL_8814B(x, v) \
+ (BIT_CLEAR_MU_RL_8814B(x) | BIT_MU_RL_8814B(v))
+
+#define BIT_SHIFT_MU_TAB_SEL_8814B 8
+#define BIT_MASK_MU_TAB_SEL_8814B 0xf
+#define BIT_MU_TAB_SEL_8814B(x) \
+ (((x) & BIT_MASK_MU_TAB_SEL_8814B) << BIT_SHIFT_MU_TAB_SEL_8814B)
+#define BITS_MU_TAB_SEL_8814B \
+ (BIT_MASK_MU_TAB_SEL_8814B << BIT_SHIFT_MU_TAB_SEL_8814B)
+#define BIT_CLEAR_MU_TAB_SEL_8814B(x) ((x) & (~BITS_MU_TAB_SEL_8814B))
+#define BIT_GET_MU_TAB_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_MU_TAB_SEL_8814B) & BIT_MASK_MU_TAB_SEL_8814B)
+#define BIT_SET_MU_TAB_SEL_8814B(x, v) \
+ (BIT_CLEAR_MU_TAB_SEL_8814B(x) | BIT_MU_TAB_SEL_8814B(v))
+
+#define BIT_SHIFT_MU_TAB_VALID_8814B 0
+#define BIT_MASK_MU_TAB_VALID_8814B 0x3f
+#define BIT_MU_TAB_VALID_8814B(x) \
+ (((x) & BIT_MASK_MU_TAB_VALID_8814B) << BIT_SHIFT_MU_TAB_VALID_8814B)
+#define BITS_MU_TAB_VALID_8814B \
+ (BIT_MASK_MU_TAB_VALID_8814B << BIT_SHIFT_MU_TAB_VALID_8814B)
+#define BIT_CLEAR_MU_TAB_VALID_8814B(x) ((x) & (~BITS_MU_TAB_VALID_8814B))
+#define BIT_GET_MU_TAB_VALID_8814B(x) \
+ (((x) >> BIT_SHIFT_MU_TAB_VALID_8814B) & BIT_MASK_MU_TAB_VALID_8814B)
+#define BIT_SET_MU_TAB_VALID_8814B(x, v) \
+ (BIT_CLEAR_MU_TAB_VALID_8814B(x) | BIT_MU_TAB_VALID_8814B(v))
+
+/* 2 REG_MU_STA_GID_VLD_8814B */
+
+#define BIT_SHIFT_MU_STA_GTAB_VALID_8814B 0
+#define BIT_MASK_MU_STA_GTAB_VALID_8814B 0xffffffffL
+#define BIT_MU_STA_GTAB_VALID_8814B(x) \
+ (((x) & BIT_MASK_MU_STA_GTAB_VALID_8814B) \
+ << BIT_SHIFT_MU_STA_GTAB_VALID_8814B)
+#define BITS_MU_STA_GTAB_VALID_8814B \
+ (BIT_MASK_MU_STA_GTAB_VALID_8814B << BIT_SHIFT_MU_STA_GTAB_VALID_8814B)
+#define BIT_CLEAR_MU_STA_GTAB_VALID_8814B(x) \
+ ((x) & (~BITS_MU_STA_GTAB_VALID_8814B))
+#define BIT_GET_MU_STA_GTAB_VALID_8814B(x) \
+ (((x) >> BIT_SHIFT_MU_STA_GTAB_VALID_8814B) & \
+ BIT_MASK_MU_STA_GTAB_VALID_8814B)
+#define BIT_SET_MU_STA_GTAB_VALID_8814B(x, v) \
+ (BIT_CLEAR_MU_STA_GTAB_VALID_8814B(x) | BIT_MU_STA_GTAB_VALID_8814B(v))
+
+/* 2 REG_MU_STA_USER_POS_INFO_8814B */
+
+#define BIT_SHIFT_MU_STA_GTAB_POSITION_L_8814B 0
+#define BIT_MASK_MU_STA_GTAB_POSITION_L_8814B 0xffffffffL
+#define BIT_MU_STA_GTAB_POSITION_L_8814B(x) \
+ (((x) & BIT_MASK_MU_STA_GTAB_POSITION_L_8814B) \
+ << BIT_SHIFT_MU_STA_GTAB_POSITION_L_8814B)
+#define BITS_MU_STA_GTAB_POSITION_L_8814B \
+ (BIT_MASK_MU_STA_GTAB_POSITION_L_8814B \
+ << BIT_SHIFT_MU_STA_GTAB_POSITION_L_8814B)
+#define BIT_CLEAR_MU_STA_GTAB_POSITION_L_8814B(x) \
+ ((x) & (~BITS_MU_STA_GTAB_POSITION_L_8814B))
+#define BIT_GET_MU_STA_GTAB_POSITION_L_8814B(x) \
+ (((x) >> BIT_SHIFT_MU_STA_GTAB_POSITION_L_8814B) & \
+ BIT_MASK_MU_STA_GTAB_POSITION_L_8814B)
+#define BIT_SET_MU_STA_GTAB_POSITION_L_8814B(x, v) \
+ (BIT_CLEAR_MU_STA_GTAB_POSITION_L_8814B(x) | \
+ BIT_MU_STA_GTAB_POSITION_L_8814B(v))
+
+/* 2 REG_MU_STA_USER_POS_INFO_H_8814B */
+
+#define BIT_SHIFT_MU_STA_GTAB_POSITION_H_8814B 0
+#define BIT_MASK_MU_STA_GTAB_POSITION_H_8814B 0xffffffffL
+#define BIT_MU_STA_GTAB_POSITION_H_8814B(x) \
+ (((x) & BIT_MASK_MU_STA_GTAB_POSITION_H_8814B) \
+ << BIT_SHIFT_MU_STA_GTAB_POSITION_H_8814B)
+#define BITS_MU_STA_GTAB_POSITION_H_8814B \
+ (BIT_MASK_MU_STA_GTAB_POSITION_H_8814B \
+ << BIT_SHIFT_MU_STA_GTAB_POSITION_H_8814B)
+#define BIT_CLEAR_MU_STA_GTAB_POSITION_H_8814B(x) \
+ ((x) & (~BITS_MU_STA_GTAB_POSITION_H_8814B))
+#define BIT_GET_MU_STA_GTAB_POSITION_H_8814B(x) \
+ (((x) >> BIT_SHIFT_MU_STA_GTAB_POSITION_H_8814B) & \
+ BIT_MASK_MU_STA_GTAB_POSITION_H_8814B)
+#define BIT_SET_MU_STA_GTAB_POSITION_H_8814B(x, v) \
+ (BIT_CLEAR_MU_STA_GTAB_POSITION_H_8814B(x) | \
+ BIT_MU_STA_GTAB_POSITION_H_8814B(v))
+
+/* 2 REG_CHNL_INFO_CTRL_8814B */
+#define BIT_CHNL_REF_RXNAV_8814B BIT(7)
+#define BIT_CHNL_REF_VBON_8814B BIT(6)
+#define BIT_CHNL_REF_EDCA_8814B BIT(5)
+#define BIT_CHNL_REF_CCA_8814B BIT(4)
+#define BIT_RST_CHNL_BUSY_8814B BIT(3)
+#define BIT_RST_CHNL_IDLE_8814B BIT(2)
+#define BIT_CHNL_INFO_RST_8814B BIT(1)
+#define BIT_ATM_AIRTIME_EN_8814B BIT(0)
+
+/* 2 REG_CHNL_IDLE_TIME_8814B */
+
+#define BIT_SHIFT_CHNL_IDLE_TIME_8814B 0
+#define BIT_MASK_CHNL_IDLE_TIME_8814B 0xffffffffL
+#define BIT_CHNL_IDLE_TIME_8814B(x) \
+ (((x) & BIT_MASK_CHNL_IDLE_TIME_8814B) \
+ << BIT_SHIFT_CHNL_IDLE_TIME_8814B)
+#define BITS_CHNL_IDLE_TIME_8814B \
+ (BIT_MASK_CHNL_IDLE_TIME_8814B << BIT_SHIFT_CHNL_IDLE_TIME_8814B)
+#define BIT_CLEAR_CHNL_IDLE_TIME_8814B(x) ((x) & (~BITS_CHNL_IDLE_TIME_8814B))
+#define BIT_GET_CHNL_IDLE_TIME_8814B(x) \
+ (((x) >> BIT_SHIFT_CHNL_IDLE_TIME_8814B) & \
+ BIT_MASK_CHNL_IDLE_TIME_8814B)
+#define BIT_SET_CHNL_IDLE_TIME_8814B(x, v) \
+ (BIT_CLEAR_CHNL_IDLE_TIME_8814B(x) | BIT_CHNL_IDLE_TIME_8814B(v))
+
+/* 2 REG_CHNL_BUSY_TIME_8814B */
+
+#define BIT_SHIFT_CHNL_BUSY_TIME_8814B 0
+#define BIT_MASK_CHNL_BUSY_TIME_8814B 0xffffffffL
+#define BIT_CHNL_BUSY_TIME_8814B(x) \
+ (((x) & BIT_MASK_CHNL_BUSY_TIME_8814B) \
+ << BIT_SHIFT_CHNL_BUSY_TIME_8814B)
+#define BITS_CHNL_BUSY_TIME_8814B \
+ (BIT_MASK_CHNL_BUSY_TIME_8814B << BIT_SHIFT_CHNL_BUSY_TIME_8814B)
+#define BIT_CLEAR_CHNL_BUSY_TIME_8814B(x) ((x) & (~BITS_CHNL_BUSY_TIME_8814B))
+#define BIT_GET_CHNL_BUSY_TIME_8814B(x) \
+ (((x) >> BIT_SHIFT_CHNL_BUSY_TIME_8814B) & \
+ BIT_MASK_CHNL_BUSY_TIME_8814B)
+#define BIT_SET_CHNL_BUSY_TIME_8814B(x, v) \
+ (BIT_CLEAR_CHNL_BUSY_TIME_8814B(x) | BIT_CHNL_BUSY_TIME_8814B(v))
+
+/* 2 REG_MU_TRX_DBG_CNT_V1_8814B */
+#define BIT_FORCE_SND_STS_EN_8814B BIT(31)
+
+#define BIT_SHIFT_SND_STS_VALUE_8814B 24
+#define BIT_MASK_SND_STS_VALUE_8814B 0x3f
+#define BIT_SND_STS_VALUE_8814B(x) \
+ (((x) & BIT_MASK_SND_STS_VALUE_8814B) << BIT_SHIFT_SND_STS_VALUE_8814B)
+#define BITS_SND_STS_VALUE_8814B \
+ (BIT_MASK_SND_STS_VALUE_8814B << BIT_SHIFT_SND_STS_VALUE_8814B)
+#define BIT_CLEAR_SND_STS_VALUE_8814B(x) ((x) & (~BITS_SND_STS_VALUE_8814B))
+#define BIT_GET_SND_STS_VALUE_8814B(x) \
+ (((x) >> BIT_SHIFT_SND_STS_VALUE_8814B) & BIT_MASK_SND_STS_VALUE_8814B)
+#define BIT_SET_SND_STS_VALUE_8814B(x, v) \
+ (BIT_CLEAR_SND_STS_VALUE_8814B(x) | BIT_SND_STS_VALUE_8814B(v))
+
+#define BIT_MU_DNGCNT_RST_8814B BIT(20)
+
+#define BIT_SHIFT_MU_DNGCNT_SEL_8814B 16
+#define BIT_MASK_MU_DNGCNT_SEL_8814B 0xf
+#define BIT_MU_DNGCNT_SEL_8814B(x) \
+ (((x) & BIT_MASK_MU_DNGCNT_SEL_8814B) << BIT_SHIFT_MU_DNGCNT_SEL_8814B)
+#define BITS_MU_DNGCNT_SEL_8814B \
+ (BIT_MASK_MU_DNGCNT_SEL_8814B << BIT_SHIFT_MU_DNGCNT_SEL_8814B)
+#define BIT_CLEAR_MU_DNGCNT_SEL_8814B(x) ((x) & (~BITS_MU_DNGCNT_SEL_8814B))
+#define BIT_GET_MU_DNGCNT_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_MU_DNGCNT_SEL_8814B) & BIT_MASK_MU_DNGCNT_SEL_8814B)
+#define BIT_SET_MU_DNGCNT_SEL_8814B(x, v) \
+ (BIT_CLEAR_MU_DNGCNT_SEL_8814B(x) | BIT_MU_DNGCNT_SEL_8814B(v))
+
+#define BIT_SHIFT_MU_DNGCNT_8814B 0
+#define BIT_MASK_MU_DNGCNT_8814B 0xffff
+#define BIT_MU_DNGCNT_8814B(x) \
+ (((x) & BIT_MASK_MU_DNGCNT_8814B) << BIT_SHIFT_MU_DNGCNT_8814B)
+#define BITS_MU_DNGCNT_8814B \
+ (BIT_MASK_MU_DNGCNT_8814B << BIT_SHIFT_MU_DNGCNT_8814B)
+#define BIT_CLEAR_MU_DNGCNT_8814B(x) ((x) & (~BITS_MU_DNGCNT_8814B))
+#define BIT_GET_MU_DNGCNT_8814B(x) \
+ (((x) >> BIT_SHIFT_MU_DNGCNT_8814B) & BIT_MASK_MU_DNGCNT_8814B)
+#define BIT_SET_MU_DNGCNT_8814B(x, v) \
+ (BIT_CLEAR_MU_DNGCNT_8814B(x) | BIT_MU_DNGCNT_8814B(v))
+
+/* 2 REG_SWPS_CTRL_8814B */
+
+#define BIT_SHIFT_SWPS_RPT_LENGTH_8814B 8
+#define BIT_MASK_SWPS_RPT_LENGTH_8814B 0x7f
+#define BIT_SWPS_RPT_LENGTH_8814B(x) \
+ (((x) & BIT_MASK_SWPS_RPT_LENGTH_8814B) \
+ << BIT_SHIFT_SWPS_RPT_LENGTH_8814B)
+#define BITS_SWPS_RPT_LENGTH_8814B \
+ (BIT_MASK_SWPS_RPT_LENGTH_8814B << BIT_SHIFT_SWPS_RPT_LENGTH_8814B)
+#define BIT_CLEAR_SWPS_RPT_LENGTH_8814B(x) ((x) & (~BITS_SWPS_RPT_LENGTH_8814B))
+#define BIT_GET_SWPS_RPT_LENGTH_8814B(x) \
+ (((x) >> BIT_SHIFT_SWPS_RPT_LENGTH_8814B) & \
+ BIT_MASK_SWPS_RPT_LENGTH_8814B)
+#define BIT_SET_SWPS_RPT_LENGTH_8814B(x, v) \
+ (BIT_CLEAR_SWPS_RPT_LENGTH_8814B(x) | BIT_SWPS_RPT_LENGTH_8814B(v))
+
+#define BIT_SHIFT_MACID_SWPS_EN_SEL_8814B 2
+#define BIT_MASK_MACID_SWPS_EN_SEL_8814B 0x3
+#define BIT_MACID_SWPS_EN_SEL_8814B(x) \
+ (((x) & BIT_MASK_MACID_SWPS_EN_SEL_8814B) \
+ << BIT_SHIFT_MACID_SWPS_EN_SEL_8814B)
+#define BITS_MACID_SWPS_EN_SEL_8814B \
+ (BIT_MASK_MACID_SWPS_EN_SEL_8814B << BIT_SHIFT_MACID_SWPS_EN_SEL_8814B)
+#define BIT_CLEAR_MACID_SWPS_EN_SEL_8814B(x) \
+ ((x) & (~BITS_MACID_SWPS_EN_SEL_8814B))
+#define BIT_GET_MACID_SWPS_EN_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_MACID_SWPS_EN_SEL_8814B) & \
+ BIT_MASK_MACID_SWPS_EN_SEL_8814B)
+#define BIT_SET_MACID_SWPS_EN_SEL_8814B(x, v) \
+ (BIT_CLEAR_MACID_SWPS_EN_SEL_8814B(x) | BIT_MACID_SWPS_EN_SEL_8814B(v))
+
+#define BIT_SWPS_MANUALL_POLLING_8814B BIT(1)
+#define BIT_SWPS_EN_8814B BIT(0)
+
+/* 2 REG_SWPS_PKT_TH_8814B */
+
+#define BIT_SHIFT_SWPS_PKT_TH_8814B 0
+#define BIT_MASK_SWPS_PKT_TH_8814B 0xffff
+#define BIT_SWPS_PKT_TH_8814B(x) \
+ (((x) & BIT_MASK_SWPS_PKT_TH_8814B) << BIT_SHIFT_SWPS_PKT_TH_8814B)
+#define BITS_SWPS_PKT_TH_8814B \
+ (BIT_MASK_SWPS_PKT_TH_8814B << BIT_SHIFT_SWPS_PKT_TH_8814B)
+#define BIT_CLEAR_SWPS_PKT_TH_8814B(x) ((x) & (~BITS_SWPS_PKT_TH_8814B))
+#define BIT_GET_SWPS_PKT_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_SWPS_PKT_TH_8814B) & BIT_MASK_SWPS_PKT_TH_8814B)
+#define BIT_SET_SWPS_PKT_TH_8814B(x, v) \
+ (BIT_CLEAR_SWPS_PKT_TH_8814B(x) | BIT_SWPS_PKT_TH_8814B(v))
+
+/* 2 REG_SWPS_TIME_TH_8814B */
+
+#define BIT_SHIFT_SWPS_PSTIME_TH_8814B 16
+#define BIT_MASK_SWPS_PSTIME_TH_8814B 0xffff
+#define BIT_SWPS_PSTIME_TH_8814B(x) \
+ (((x) & BIT_MASK_SWPS_PSTIME_TH_8814B) \
+ << BIT_SHIFT_SWPS_PSTIME_TH_8814B)
+#define BITS_SWPS_PSTIME_TH_8814B \
+ (BIT_MASK_SWPS_PSTIME_TH_8814B << BIT_SHIFT_SWPS_PSTIME_TH_8814B)
+#define BIT_CLEAR_SWPS_PSTIME_TH_8814B(x) ((x) & (~BITS_SWPS_PSTIME_TH_8814B))
+#define BIT_GET_SWPS_PSTIME_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_SWPS_PSTIME_TH_8814B) & \
+ BIT_MASK_SWPS_PSTIME_TH_8814B)
+#define BIT_SET_SWPS_PSTIME_TH_8814B(x, v) \
+ (BIT_CLEAR_SWPS_PSTIME_TH_8814B(x) | BIT_SWPS_PSTIME_TH_8814B(v))
+
+#define BIT_SHIFT_SWPS_TIME_TH_8814B 0
+#define BIT_MASK_SWPS_TIME_TH_8814B 0xffff
+#define BIT_SWPS_TIME_TH_8814B(x) \
+ (((x) & BIT_MASK_SWPS_TIME_TH_8814B) << BIT_SHIFT_SWPS_TIME_TH_8814B)
+#define BITS_SWPS_TIME_TH_8814B \
+ (BIT_MASK_SWPS_TIME_TH_8814B << BIT_SHIFT_SWPS_TIME_TH_8814B)
+#define BIT_CLEAR_SWPS_TIME_TH_8814B(x) ((x) & (~BITS_SWPS_TIME_TH_8814B))
+#define BIT_GET_SWPS_TIME_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_SWPS_TIME_TH_8814B) & BIT_MASK_SWPS_TIME_TH_8814B)
+#define BIT_SET_SWPS_TIME_TH_8814B(x, v) \
+ (BIT_CLEAR_SWPS_TIME_TH_8814B(x) | BIT_SWPS_TIME_TH_8814B(v))
+
+/* 2 REG_MACID_SWPS_EN_8814B */
+
+#define BIT_SHIFT_MACID_SWPS_EN_8814B 0
+#define BIT_MASK_MACID_SWPS_EN_8814B 0xffffffffL
+#define BIT_MACID_SWPS_EN_8814B(x) \
+ (((x) & BIT_MASK_MACID_SWPS_EN_8814B) << BIT_SHIFT_MACID_SWPS_EN_8814B)
+#define BITS_MACID_SWPS_EN_8814B \
+ (BIT_MASK_MACID_SWPS_EN_8814B << BIT_SHIFT_MACID_SWPS_EN_8814B)
+#define BIT_CLEAR_MACID_SWPS_EN_8814B(x) ((x) & (~BITS_MACID_SWPS_EN_8814B))
+#define BIT_GET_MACID_SWPS_EN_8814B(x) \
+ (((x) >> BIT_SHIFT_MACID_SWPS_EN_8814B) & BIT_MASK_MACID_SWPS_EN_8814B)
+#define BIT_SET_MACID_SWPS_EN_8814B(x, v) \
+ (BIT_CLEAR_MACID_SWPS_EN_8814B(x) | BIT_MACID_SWPS_EN_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_EDCA_VO_PARAM_8814B */
+
+#define BIT_SHIFT_TXOPLIMIT_8814B 16
+#define BIT_MASK_TXOPLIMIT_8814B 0x7ff
+#define BIT_TXOPLIMIT_8814B(x) \
+ (((x) & BIT_MASK_TXOPLIMIT_8814B) << BIT_SHIFT_TXOPLIMIT_8814B)
+#define BITS_TXOPLIMIT_8814B \
+ (BIT_MASK_TXOPLIMIT_8814B << BIT_SHIFT_TXOPLIMIT_8814B)
+#define BIT_CLEAR_TXOPLIMIT_8814B(x) ((x) & (~BITS_TXOPLIMIT_8814B))
+#define BIT_GET_TXOPLIMIT_8814B(x) \
+ (((x) >> BIT_SHIFT_TXOPLIMIT_8814B) & BIT_MASK_TXOPLIMIT_8814B)
+#define BIT_SET_TXOPLIMIT_8814B(x, v) \
+ (BIT_CLEAR_TXOPLIMIT_8814B(x) | BIT_TXOPLIMIT_8814B(v))
+
+#define BIT_SHIFT_CW_8814B 8
+#define BIT_MASK_CW_8814B 0xff
+#define BIT_CW_8814B(x) (((x) & BIT_MASK_CW_8814B) << BIT_SHIFT_CW_8814B)
+#define BITS_CW_8814B (BIT_MASK_CW_8814B << BIT_SHIFT_CW_8814B)
+#define BIT_CLEAR_CW_8814B(x) ((x) & (~BITS_CW_8814B))
+#define BIT_GET_CW_8814B(x) (((x) >> BIT_SHIFT_CW_8814B) & BIT_MASK_CW_8814B)
+#define BIT_SET_CW_8814B(x, v) (BIT_CLEAR_CW_8814B(x) | BIT_CW_8814B(v))
+
+#define BIT_SHIFT_AIFS_8814B 0
+#define BIT_MASK_AIFS_8814B 0xff
+#define BIT_AIFS_8814B(x) (((x) & BIT_MASK_AIFS_8814B) << BIT_SHIFT_AIFS_8814B)
+#define BITS_AIFS_8814B (BIT_MASK_AIFS_8814B << BIT_SHIFT_AIFS_8814B)
+#define BIT_CLEAR_AIFS_8814B(x) ((x) & (~BITS_AIFS_8814B))
+#define BIT_GET_AIFS_8814B(x) \
+ (((x) >> BIT_SHIFT_AIFS_8814B) & BIT_MASK_AIFS_8814B)
+#define BIT_SET_AIFS_8814B(x, v) (BIT_CLEAR_AIFS_8814B(x) | BIT_AIFS_8814B(v))
+
+/* 2 REG_EDCA_VI_PARAM_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_TXOPLIMIT_8814B 16
+#define BIT_MASK_TXOPLIMIT_8814B 0x7ff
+#define BIT_TXOPLIMIT_8814B(x) \
+ (((x) & BIT_MASK_TXOPLIMIT_8814B) << BIT_SHIFT_TXOPLIMIT_8814B)
+#define BITS_TXOPLIMIT_8814B \
+ (BIT_MASK_TXOPLIMIT_8814B << BIT_SHIFT_TXOPLIMIT_8814B)
+#define BIT_CLEAR_TXOPLIMIT_8814B(x) ((x) & (~BITS_TXOPLIMIT_8814B))
+#define BIT_GET_TXOPLIMIT_8814B(x) \
+ (((x) >> BIT_SHIFT_TXOPLIMIT_8814B) & BIT_MASK_TXOPLIMIT_8814B)
+#define BIT_SET_TXOPLIMIT_8814B(x, v) \
+ (BIT_CLEAR_TXOPLIMIT_8814B(x) | BIT_TXOPLIMIT_8814B(v))
+
+#define BIT_SHIFT_CW_8814B 8
+#define BIT_MASK_CW_8814B 0xff
+#define BIT_CW_8814B(x) (((x) & BIT_MASK_CW_8814B) << BIT_SHIFT_CW_8814B)
+#define BITS_CW_8814B (BIT_MASK_CW_8814B << BIT_SHIFT_CW_8814B)
+#define BIT_CLEAR_CW_8814B(x) ((x) & (~BITS_CW_8814B))
+#define BIT_GET_CW_8814B(x) (((x) >> BIT_SHIFT_CW_8814B) & BIT_MASK_CW_8814B)
+#define BIT_SET_CW_8814B(x, v) (BIT_CLEAR_CW_8814B(x) | BIT_CW_8814B(v))
+
+#define BIT_SHIFT_AIFS_8814B 0
+#define BIT_MASK_AIFS_8814B 0xff
+#define BIT_AIFS_8814B(x) (((x) & BIT_MASK_AIFS_8814B) << BIT_SHIFT_AIFS_8814B)
+#define BITS_AIFS_8814B (BIT_MASK_AIFS_8814B << BIT_SHIFT_AIFS_8814B)
+#define BIT_CLEAR_AIFS_8814B(x) ((x) & (~BITS_AIFS_8814B))
+#define BIT_GET_AIFS_8814B(x) \
+ (((x) >> BIT_SHIFT_AIFS_8814B) & BIT_MASK_AIFS_8814B)
+#define BIT_SET_AIFS_8814B(x, v) (BIT_CLEAR_AIFS_8814B(x) | BIT_AIFS_8814B(v))
+
+/* 2 REG_EDCA_BE_PARAM_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_TXOPLIMIT_8814B 16
+#define BIT_MASK_TXOPLIMIT_8814B 0x7ff
+#define BIT_TXOPLIMIT_8814B(x) \
+ (((x) & BIT_MASK_TXOPLIMIT_8814B) << BIT_SHIFT_TXOPLIMIT_8814B)
+#define BITS_TXOPLIMIT_8814B \
+ (BIT_MASK_TXOPLIMIT_8814B << BIT_SHIFT_TXOPLIMIT_8814B)
+#define BIT_CLEAR_TXOPLIMIT_8814B(x) ((x) & (~BITS_TXOPLIMIT_8814B))
+#define BIT_GET_TXOPLIMIT_8814B(x) \
+ (((x) >> BIT_SHIFT_TXOPLIMIT_8814B) & BIT_MASK_TXOPLIMIT_8814B)
+#define BIT_SET_TXOPLIMIT_8814B(x, v) \
+ (BIT_CLEAR_TXOPLIMIT_8814B(x) | BIT_TXOPLIMIT_8814B(v))
+
+#define BIT_SHIFT_CW_8814B 8
+#define BIT_MASK_CW_8814B 0xff
+#define BIT_CW_8814B(x) (((x) & BIT_MASK_CW_8814B) << BIT_SHIFT_CW_8814B)
+#define BITS_CW_8814B (BIT_MASK_CW_8814B << BIT_SHIFT_CW_8814B)
+#define BIT_CLEAR_CW_8814B(x) ((x) & (~BITS_CW_8814B))
+#define BIT_GET_CW_8814B(x) (((x) >> BIT_SHIFT_CW_8814B) & BIT_MASK_CW_8814B)
+#define BIT_SET_CW_8814B(x, v) (BIT_CLEAR_CW_8814B(x) | BIT_CW_8814B(v))
+
+#define BIT_SHIFT_AIFS_8814B 0
+#define BIT_MASK_AIFS_8814B 0xff
+#define BIT_AIFS_8814B(x) (((x) & BIT_MASK_AIFS_8814B) << BIT_SHIFT_AIFS_8814B)
+#define BITS_AIFS_8814B (BIT_MASK_AIFS_8814B << BIT_SHIFT_AIFS_8814B)
+#define BIT_CLEAR_AIFS_8814B(x) ((x) & (~BITS_AIFS_8814B))
+#define BIT_GET_AIFS_8814B(x) \
+ (((x) >> BIT_SHIFT_AIFS_8814B) & BIT_MASK_AIFS_8814B)
+#define BIT_SET_AIFS_8814B(x, v) (BIT_CLEAR_AIFS_8814B(x) | BIT_AIFS_8814B(v))
+
+/* 2 REG_EDCA_BK_PARAM_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_TXOPLIMIT_8814B 16
+#define BIT_MASK_TXOPLIMIT_8814B 0x7ff
+#define BIT_TXOPLIMIT_8814B(x) \
+ (((x) & BIT_MASK_TXOPLIMIT_8814B) << BIT_SHIFT_TXOPLIMIT_8814B)
+#define BITS_TXOPLIMIT_8814B \
+ (BIT_MASK_TXOPLIMIT_8814B << BIT_SHIFT_TXOPLIMIT_8814B)
+#define BIT_CLEAR_TXOPLIMIT_8814B(x) ((x) & (~BITS_TXOPLIMIT_8814B))
+#define BIT_GET_TXOPLIMIT_8814B(x) \
+ (((x) >> BIT_SHIFT_TXOPLIMIT_8814B) & BIT_MASK_TXOPLIMIT_8814B)
+#define BIT_SET_TXOPLIMIT_8814B(x, v) \
+ (BIT_CLEAR_TXOPLIMIT_8814B(x) | BIT_TXOPLIMIT_8814B(v))
+
+#define BIT_SHIFT_CW_8814B 8
+#define BIT_MASK_CW_8814B 0xff
+#define BIT_CW_8814B(x) (((x) & BIT_MASK_CW_8814B) << BIT_SHIFT_CW_8814B)
+#define BITS_CW_8814B (BIT_MASK_CW_8814B << BIT_SHIFT_CW_8814B)
+#define BIT_CLEAR_CW_8814B(x) ((x) & (~BITS_CW_8814B))
+#define BIT_GET_CW_8814B(x) (((x) >> BIT_SHIFT_CW_8814B) & BIT_MASK_CW_8814B)
+#define BIT_SET_CW_8814B(x, v) (BIT_CLEAR_CW_8814B(x) | BIT_CW_8814B(v))
+
+#define BIT_SHIFT_AIFS_8814B 0
+#define BIT_MASK_AIFS_8814B 0xff
+#define BIT_AIFS_8814B(x) (((x) & BIT_MASK_AIFS_8814B) << BIT_SHIFT_AIFS_8814B)
+#define BITS_AIFS_8814B (BIT_MASK_AIFS_8814B << BIT_SHIFT_AIFS_8814B)
+#define BIT_CLEAR_AIFS_8814B(x) ((x) & (~BITS_AIFS_8814B))
+#define BIT_GET_AIFS_8814B(x) \
+ (((x) >> BIT_SHIFT_AIFS_8814B) & BIT_MASK_AIFS_8814B)
+#define BIT_SET_AIFS_8814B(x, v) (BIT_CLEAR_AIFS_8814B(x) | BIT_AIFS_8814B(v))
+
+/* 2 REG_BCNTCFG_8814B */
+
+#define BIT_SHIFT_BCNCW_MAX_8814B 12
+#define BIT_MASK_BCNCW_MAX_8814B 0xf
+#define BIT_BCNCW_MAX_8814B(x) \
+ (((x) & BIT_MASK_BCNCW_MAX_8814B) << BIT_SHIFT_BCNCW_MAX_8814B)
+#define BITS_BCNCW_MAX_8814B \
+ (BIT_MASK_BCNCW_MAX_8814B << BIT_SHIFT_BCNCW_MAX_8814B)
+#define BIT_CLEAR_BCNCW_MAX_8814B(x) ((x) & (~BITS_BCNCW_MAX_8814B))
+#define BIT_GET_BCNCW_MAX_8814B(x) \
+ (((x) >> BIT_SHIFT_BCNCW_MAX_8814B) & BIT_MASK_BCNCW_MAX_8814B)
+#define BIT_SET_BCNCW_MAX_8814B(x, v) \
+ (BIT_CLEAR_BCNCW_MAX_8814B(x) | BIT_BCNCW_MAX_8814B(v))
+
+#define BIT_SHIFT_BCNCW_MIN_8814B 8
+#define BIT_MASK_BCNCW_MIN_8814B 0xf
+#define BIT_BCNCW_MIN_8814B(x) \
+ (((x) & BIT_MASK_BCNCW_MIN_8814B) << BIT_SHIFT_BCNCW_MIN_8814B)
+#define BITS_BCNCW_MIN_8814B \
+ (BIT_MASK_BCNCW_MIN_8814B << BIT_SHIFT_BCNCW_MIN_8814B)
+#define BIT_CLEAR_BCNCW_MIN_8814B(x) ((x) & (~BITS_BCNCW_MIN_8814B))
+#define BIT_GET_BCNCW_MIN_8814B(x) \
+ (((x) >> BIT_SHIFT_BCNCW_MIN_8814B) & BIT_MASK_BCNCW_MIN_8814B)
+#define BIT_SET_BCNCW_MIN_8814B(x, v) \
+ (BIT_CLEAR_BCNCW_MIN_8814B(x) | BIT_BCNCW_MIN_8814B(v))
+
+#define BIT_SHIFT_BCNIFS_8814B 0
+#define BIT_MASK_BCNIFS_8814B 0xff
+#define BIT_BCNIFS_8814B(x) \
+ (((x) & BIT_MASK_BCNIFS_8814B) << BIT_SHIFT_BCNIFS_8814B)
+#define BITS_BCNIFS_8814B (BIT_MASK_BCNIFS_8814B << BIT_SHIFT_BCNIFS_8814B)
+#define BIT_CLEAR_BCNIFS_8814B(x) ((x) & (~BITS_BCNIFS_8814B))
+#define BIT_GET_BCNIFS_8814B(x) \
+ (((x) >> BIT_SHIFT_BCNIFS_8814B) & BIT_MASK_BCNIFS_8814B)
+#define BIT_SET_BCNIFS_8814B(x, v) \
+ (BIT_CLEAR_BCNIFS_8814B(x) | BIT_BCNIFS_8814B(v))
+
+/* 2 REG_PIFS_8814B */
+
+#define BIT_SHIFT_PIFS_8814B 0
+#define BIT_MASK_PIFS_8814B 0xff
+#define BIT_PIFS_8814B(x) (((x) & BIT_MASK_PIFS_8814B) << BIT_SHIFT_PIFS_8814B)
+#define BITS_PIFS_8814B (BIT_MASK_PIFS_8814B << BIT_SHIFT_PIFS_8814B)
+#define BIT_CLEAR_PIFS_8814B(x) ((x) & (~BITS_PIFS_8814B))
+#define BIT_GET_PIFS_8814B(x) \
+ (((x) >> BIT_SHIFT_PIFS_8814B) & BIT_MASK_PIFS_8814B)
+#define BIT_SET_PIFS_8814B(x, v) (BIT_CLEAR_PIFS_8814B(x) | BIT_PIFS_8814B(v))
+
+/* 2 REG_RDG_PIFS_8814B */
+
+#define BIT_SHIFT_RDG_PIFS_8814B 0
+#define BIT_MASK_RDG_PIFS_8814B 0xff
+#define BIT_RDG_PIFS_8814B(x) \
+ (((x) & BIT_MASK_RDG_PIFS_8814B) << BIT_SHIFT_RDG_PIFS_8814B)
+#define BITS_RDG_PIFS_8814B \
+ (BIT_MASK_RDG_PIFS_8814B << BIT_SHIFT_RDG_PIFS_8814B)
+#define BIT_CLEAR_RDG_PIFS_8814B(x) ((x) & (~BITS_RDG_PIFS_8814B))
+#define BIT_GET_RDG_PIFS_8814B(x) \
+ (((x) >> BIT_SHIFT_RDG_PIFS_8814B) & BIT_MASK_RDG_PIFS_8814B)
+#define BIT_SET_RDG_PIFS_8814B(x, v) \
+ (BIT_CLEAR_RDG_PIFS_8814B(x) | BIT_RDG_PIFS_8814B(v))
+
+/* 2 REG_SIFS_8814B */
+
+#define BIT_SHIFT_SIFS_OFDM_TRX_8814B 24
+#define BIT_MASK_SIFS_OFDM_TRX_8814B 0xff
+#define BIT_SIFS_OFDM_TRX_8814B(x) \
+ (((x) & BIT_MASK_SIFS_OFDM_TRX_8814B) << BIT_SHIFT_SIFS_OFDM_TRX_8814B)
+#define BITS_SIFS_OFDM_TRX_8814B \
+ (BIT_MASK_SIFS_OFDM_TRX_8814B << BIT_SHIFT_SIFS_OFDM_TRX_8814B)
+#define BIT_CLEAR_SIFS_OFDM_TRX_8814B(x) ((x) & (~BITS_SIFS_OFDM_TRX_8814B))
+#define BIT_GET_SIFS_OFDM_TRX_8814B(x) \
+ (((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8814B) & BIT_MASK_SIFS_OFDM_TRX_8814B)
+#define BIT_SET_SIFS_OFDM_TRX_8814B(x, v) \
+ (BIT_CLEAR_SIFS_OFDM_TRX_8814B(x) | BIT_SIFS_OFDM_TRX_8814B(v))
+
+#define BIT_SHIFT_SIFS_CCK_TRX_8814B 16
+#define BIT_MASK_SIFS_CCK_TRX_8814B 0xff
+#define BIT_SIFS_CCK_TRX_8814B(x) \
+ (((x) & BIT_MASK_SIFS_CCK_TRX_8814B) << BIT_SHIFT_SIFS_CCK_TRX_8814B)
+#define BITS_SIFS_CCK_TRX_8814B \
+ (BIT_MASK_SIFS_CCK_TRX_8814B << BIT_SHIFT_SIFS_CCK_TRX_8814B)
+#define BIT_CLEAR_SIFS_CCK_TRX_8814B(x) ((x) & (~BITS_SIFS_CCK_TRX_8814B))
+#define BIT_GET_SIFS_CCK_TRX_8814B(x) \
+ (((x) >> BIT_SHIFT_SIFS_CCK_TRX_8814B) & BIT_MASK_SIFS_CCK_TRX_8814B)
+#define BIT_SET_SIFS_CCK_TRX_8814B(x, v) \
+ (BIT_CLEAR_SIFS_CCK_TRX_8814B(x) | BIT_SIFS_CCK_TRX_8814B(v))
+
+#define BIT_SHIFT_SIFS_OFDM_CTX_8814B 8
+#define BIT_MASK_SIFS_OFDM_CTX_8814B 0xff
+#define BIT_SIFS_OFDM_CTX_8814B(x) \
+ (((x) & BIT_MASK_SIFS_OFDM_CTX_8814B) << BIT_SHIFT_SIFS_OFDM_CTX_8814B)
+#define BITS_SIFS_OFDM_CTX_8814B \
+ (BIT_MASK_SIFS_OFDM_CTX_8814B << BIT_SHIFT_SIFS_OFDM_CTX_8814B)
+#define BIT_CLEAR_SIFS_OFDM_CTX_8814B(x) ((x) & (~BITS_SIFS_OFDM_CTX_8814B))
+#define BIT_GET_SIFS_OFDM_CTX_8814B(x) \
+ (((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8814B) & BIT_MASK_SIFS_OFDM_CTX_8814B)
+#define BIT_SET_SIFS_OFDM_CTX_8814B(x, v) \
+ (BIT_CLEAR_SIFS_OFDM_CTX_8814B(x) | BIT_SIFS_OFDM_CTX_8814B(v))
+
+#define BIT_SHIFT_SIFS_CCK_CTX_8814B 0
+#define BIT_MASK_SIFS_CCK_CTX_8814B 0xff
+#define BIT_SIFS_CCK_CTX_8814B(x) \
+ (((x) & BIT_MASK_SIFS_CCK_CTX_8814B) << BIT_SHIFT_SIFS_CCK_CTX_8814B)
+#define BITS_SIFS_CCK_CTX_8814B \
+ (BIT_MASK_SIFS_CCK_CTX_8814B << BIT_SHIFT_SIFS_CCK_CTX_8814B)
+#define BIT_CLEAR_SIFS_CCK_CTX_8814B(x) ((x) & (~BITS_SIFS_CCK_CTX_8814B))
+#define BIT_GET_SIFS_CCK_CTX_8814B(x) \
+ (((x) >> BIT_SHIFT_SIFS_CCK_CTX_8814B) & BIT_MASK_SIFS_CCK_CTX_8814B)
+#define BIT_SET_SIFS_CCK_CTX_8814B(x, v) \
+ (BIT_CLEAR_SIFS_CCK_CTX_8814B(x) | BIT_SIFS_CCK_CTX_8814B(v))
+
+/* 2 REG_FORCE_BCN_IFS_V1_8814B */
+
+#define BIT_SHIFT_FORCE_BCN_IFS_8814B 0
+#define BIT_MASK_FORCE_BCN_IFS_8814B 0xff
+#define BIT_FORCE_BCN_IFS_8814B(x) \
+ (((x) & BIT_MASK_FORCE_BCN_IFS_8814B) << BIT_SHIFT_FORCE_BCN_IFS_8814B)
+#define BITS_FORCE_BCN_IFS_8814B \
+ (BIT_MASK_FORCE_BCN_IFS_8814B << BIT_SHIFT_FORCE_BCN_IFS_8814B)
+#define BIT_CLEAR_FORCE_BCN_IFS_8814B(x) ((x) & (~BITS_FORCE_BCN_IFS_8814B))
+#define BIT_GET_FORCE_BCN_IFS_8814B(x) \
+ (((x) >> BIT_SHIFT_FORCE_BCN_IFS_8814B) & BIT_MASK_FORCE_BCN_IFS_8814B)
+#define BIT_SET_FORCE_BCN_IFS_8814B(x, v) \
+ (BIT_CLEAR_FORCE_BCN_IFS_8814B(x) | BIT_FORCE_BCN_IFS_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_AGGR_BREAK_TIME_8814B */
+
+#define BIT_SHIFT_AGGR_BK_TIME_8814B 0
+#define BIT_MASK_AGGR_BK_TIME_8814B 0xff
+#define BIT_AGGR_BK_TIME_8814B(x) \
+ (((x) & BIT_MASK_AGGR_BK_TIME_8814B) << BIT_SHIFT_AGGR_BK_TIME_8814B)
+#define BITS_AGGR_BK_TIME_8814B \
+ (BIT_MASK_AGGR_BK_TIME_8814B << BIT_SHIFT_AGGR_BK_TIME_8814B)
+#define BIT_CLEAR_AGGR_BK_TIME_8814B(x) ((x) & (~BITS_AGGR_BK_TIME_8814B))
+#define BIT_GET_AGGR_BK_TIME_8814B(x) \
+ (((x) >> BIT_SHIFT_AGGR_BK_TIME_8814B) & BIT_MASK_AGGR_BK_TIME_8814B)
+#define BIT_SET_AGGR_BK_TIME_8814B(x, v) \
+ (BIT_CLEAR_AGGR_BK_TIME_8814B(x) | BIT_AGGR_BK_TIME_8814B(v))
+
+/* 2 REG_SLOT_8814B */
+
+#define BIT_SHIFT_SLOT_8814B 0
+#define BIT_MASK_SLOT_8814B 0xff
+#define BIT_SLOT_8814B(x) (((x) & BIT_MASK_SLOT_8814B) << BIT_SHIFT_SLOT_8814B)
+#define BITS_SLOT_8814B (BIT_MASK_SLOT_8814B << BIT_SHIFT_SLOT_8814B)
+#define BIT_CLEAR_SLOT_8814B(x) ((x) & (~BITS_SLOT_8814B))
+#define BIT_GET_SLOT_8814B(x) \
+ (((x) >> BIT_SHIFT_SLOT_8814B) & BIT_MASK_SLOT_8814B)
+#define BIT_SET_SLOT_8814B(x, v) (BIT_CLEAR_SLOT_8814B(x) | BIT_SLOT_8814B(v))
+
+/* 2 REG_EDCA_CPUMGQ_PARAM_8814B */
+
+#define BIT_SHIFT_CW_V1_8814B 8
+#define BIT_MASK_CW_V1_8814B 0xff
+#define BIT_CW_V1_8814B(x) \
+ (((x) & BIT_MASK_CW_V1_8814B) << BIT_SHIFT_CW_V1_8814B)
+#define BITS_CW_V1_8814B (BIT_MASK_CW_V1_8814B << BIT_SHIFT_CW_V1_8814B)
+#define BIT_CLEAR_CW_V1_8814B(x) ((x) & (~BITS_CW_V1_8814B))
+#define BIT_GET_CW_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_CW_V1_8814B) & BIT_MASK_CW_V1_8814B)
+#define BIT_SET_CW_V1_8814B(x, v) \
+ (BIT_CLEAR_CW_V1_8814B(x) | BIT_CW_V1_8814B(v))
+
+#define BIT_SHIFT_AIFS_V1_8814B 0
+#define BIT_MASK_AIFS_V1_8814B 0xff
+#define BIT_AIFS_V1_8814B(x) \
+ (((x) & BIT_MASK_AIFS_V1_8814B) << BIT_SHIFT_AIFS_V1_8814B)
+#define BITS_AIFS_V1_8814B (BIT_MASK_AIFS_V1_8814B << BIT_SHIFT_AIFS_V1_8814B)
+#define BIT_CLEAR_AIFS_V1_8814B(x) ((x) & (~BITS_AIFS_V1_8814B))
+#define BIT_GET_AIFS_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_AIFS_V1_8814B) & BIT_MASK_AIFS_V1_8814B)
+#define BIT_SET_AIFS_V1_8814B(x, v) \
+ (BIT_CLEAR_AIFS_V1_8814B(x) | BIT_AIFS_V1_8814B(v))
+
+/* 2 REG_CPUMGQ_PAUSE_8814B */
+#define BIT_MAC_STOP_CPUMGQ_V1_8814B BIT(0)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_TX_PTCL_CTRL_8814B */
+#define BIT_DIS_EDCCA_8814B BIT(15)
+#define BIT_DIS_CCA_8814B BIT(14)
+#define BIT_LSIG_TXOP_TXCMD_NAV_8814B BIT(13)
+#define BIT_SIFS_BK_EN_8814B BIT(12)
+
+#define BIT_SHIFT_TXQ_NAV_MSK_8814B 8
+#define BIT_MASK_TXQ_NAV_MSK_8814B 0xf
+#define BIT_TXQ_NAV_MSK_8814B(x) \
+ (((x) & BIT_MASK_TXQ_NAV_MSK_8814B) << BIT_SHIFT_TXQ_NAV_MSK_8814B)
+#define BITS_TXQ_NAV_MSK_8814B \
+ (BIT_MASK_TXQ_NAV_MSK_8814B << BIT_SHIFT_TXQ_NAV_MSK_8814B)
+#define BIT_CLEAR_TXQ_NAV_MSK_8814B(x) ((x) & (~BITS_TXQ_NAV_MSK_8814B))
+#define BIT_GET_TXQ_NAV_MSK_8814B(x) \
+ (((x) >> BIT_SHIFT_TXQ_NAV_MSK_8814B) & BIT_MASK_TXQ_NAV_MSK_8814B)
+#define BIT_SET_TXQ_NAV_MSK_8814B(x, v) \
+ (BIT_CLEAR_TXQ_NAV_MSK_8814B(x) | BIT_TXQ_NAV_MSK_8814B(v))
+
+#define BIT_DIS_CW_8814B BIT(7)
+#define BIT_NAV_END_TXOP_8814B BIT(6)
+#define BIT_RDG_END_TXOP_8814B BIT(5)
+#define BIT_AC_INBCN_HOLD_8814B BIT(4)
+#define BIT_MGTQ_TXOP_EN_8814B BIT(3)
+#define BIT_MGTQ_RTSMF_EN_8814B BIT(2)
+#define BIT_HIQ_RTSMF_EN_8814B BIT(1)
+#define BIT_BCN_RTSMF_EN_8814B BIT(0)
+
+/* 2 REG_TXPAUSE_8814B */
+#define BIT_STOP_BCN_HI_MGT_8814B BIT(7)
+#define BIT_MAC_STOPBCNQ_8814B BIT(6)
+#define BIT_MAC_STOPHIQ_8814B BIT(5)
+#define BIT_MAC_STOPMGQ_8814B BIT(4)
+#define BIT_MAC_STOPBK_8814B BIT(3)
+#define BIT_MAC_STOPBE_8814B BIT(2)
+#define BIT_MAC_STOPVI_8814B BIT(1)
+#define BIT_MAC_STOPVO_8814B BIT(0)
+
+/* 2 REG_DIS_TXREQ_CLR_8814B */
+#define BIT_DIS_BT_CCA_8814B BIT(7)
+#define BIT_DIS_TXREQ_CLR_HI_8814B BIT(5)
+#define BIT_DIS_TXREQ_CLR_MGQ_8814B BIT(4)
+#define BIT_DIS_TXREQ_CLR_VO_8814B BIT(3)
+#define BIT_DIS_TXREQ_CLR_VI_8814B BIT(2)
+#define BIT_DIS_TXREQ_CLR_BE_8814B BIT(1)
+#define BIT_DIS_TXREQ_CLR_BK_8814B BIT(0)
+
+/* 2 REG_RD_CTRL_8814B */
+#define BIT_EN_CLR_TXREQ_INCCA_8814B BIT(15)
+#define BIT_DIS_TX_OVER_BCNQ_8814B BIT(14)
+#define BIT_EN_BCNERR_INCCCA_8814B BIT(13)
+#define BIT_EDCCA_MSK_CNTDOWN_EN_8814B BIT(11)
+#define BIT_DIS_TXOP_CFE_8814B BIT(10)
+#define BIT_DIS_LSIG_CFE_8814B BIT(9)
+#define BIT_BKQ_RD_INIT_EN_8814B BIT(7)
+#define BIT_BEQ_RD_INIT_EN_8814B BIT(6)
+#define BIT_VIQ_RD_INIT_EN_8814B BIT(5)
+#define BIT_VOQ_RD_INIT_EN_8814B BIT(4)
+#define BIT_BKQ_RD_RESP_EN_8814B BIT(3)
+#define BIT_BEQ_RD_RESP_EN_8814B BIT(2)
+#define BIT_VIQ_RD_RESP_EN_8814B BIT(1)
+#define BIT_VOQ_RD_RESP_EN_8814B BIT(0)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_PKT_LIFETIME_CTRL_8814B */
+#define BIT_EN_P2P_CTWND1_8814B BIT(23)
+#define BIT_EN_BKF_CLR_TXREQ_8814B BIT(22)
+#define BIT_EN_BCN_TX_BTCCA_8814B BIT(20)
+#define BIT_DIS_PKT_TX_ATIM_8814B BIT(19)
+#define BIT_DIS_BCN_DIS_CTN_8814B BIT(18)
+#define BIT_EN_NAVEND_RST_TXOP_8814B BIT(17)
+#define BIT_EN_FILTER_CCA_8814B BIT(16)
+
+#define BIT_SHIFT_CCA_FILTER_THRS_8814B 8
+#define BIT_MASK_CCA_FILTER_THRS_8814B 0xff
+#define BIT_CCA_FILTER_THRS_8814B(x) \
+ (((x) & BIT_MASK_CCA_FILTER_THRS_8814B) \
+ << BIT_SHIFT_CCA_FILTER_THRS_8814B)
+#define BITS_CCA_FILTER_THRS_8814B \
+ (BIT_MASK_CCA_FILTER_THRS_8814B << BIT_SHIFT_CCA_FILTER_THRS_8814B)
+#define BIT_CLEAR_CCA_FILTER_THRS_8814B(x) ((x) & (~BITS_CCA_FILTER_THRS_8814B))
+#define BIT_GET_CCA_FILTER_THRS_8814B(x) \
+ (((x) >> BIT_SHIFT_CCA_FILTER_THRS_8814B) & \
+ BIT_MASK_CCA_FILTER_THRS_8814B)
+#define BIT_SET_CCA_FILTER_THRS_8814B(x, v) \
+ (BIT_CLEAR_CCA_FILTER_THRS_8814B(x) | BIT_CCA_FILTER_THRS_8814B(v))
+
+#define BIT_SHIFT_EDCCA_THRS_8814B 0
+#define BIT_MASK_EDCCA_THRS_8814B 0xff
+#define BIT_EDCCA_THRS_8814B(x) \
+ (((x) & BIT_MASK_EDCCA_THRS_8814B) << BIT_SHIFT_EDCCA_THRS_8814B)
+#define BITS_EDCCA_THRS_8814B \
+ (BIT_MASK_EDCCA_THRS_8814B << BIT_SHIFT_EDCCA_THRS_8814B)
+#define BIT_CLEAR_EDCCA_THRS_8814B(x) ((x) & (~BITS_EDCCA_THRS_8814B))
+#define BIT_GET_EDCCA_THRS_8814B(x) \
+ (((x) >> BIT_SHIFT_EDCCA_THRS_8814B) & BIT_MASK_EDCCA_THRS_8814B)
+#define BIT_SET_EDCCA_THRS_8814B(x, v) \
+ (BIT_CLEAR_EDCCA_THRS_8814B(x) | BIT_EDCCA_THRS_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_TXOP_LIMIT_CTRL_8814B */
+
+#define BIT_SHIFT_TXOP_TBTT_CNT_8814B 24
+#define BIT_MASK_TXOP_TBTT_CNT_8814B 0xff
+#define BIT_TXOP_TBTT_CNT_8814B(x) \
+ (((x) & BIT_MASK_TXOP_TBTT_CNT_8814B) << BIT_SHIFT_TXOP_TBTT_CNT_8814B)
+#define BITS_TXOP_TBTT_CNT_8814B \
+ (BIT_MASK_TXOP_TBTT_CNT_8814B << BIT_SHIFT_TXOP_TBTT_CNT_8814B)
+#define BIT_CLEAR_TXOP_TBTT_CNT_8814B(x) ((x) & (~BITS_TXOP_TBTT_CNT_8814B))
+#define BIT_GET_TXOP_TBTT_CNT_8814B(x) \
+ (((x) >> BIT_SHIFT_TXOP_TBTT_CNT_8814B) & BIT_MASK_TXOP_TBTT_CNT_8814B)
+#define BIT_SET_TXOP_TBTT_CNT_8814B(x, v) \
+ (BIT_CLEAR_TXOP_TBTT_CNT_8814B(x) | BIT_TXOP_TBTT_CNT_8814B(v))
+
+#define BIT_SHIFT_TXOP_TBTT_CNT_SEL_8814B 20
+#define BIT_MASK_TXOP_TBTT_CNT_SEL_8814B 0xf
+#define BIT_TXOP_TBTT_CNT_SEL_8814B(x) \
+ (((x) & BIT_MASK_TXOP_TBTT_CNT_SEL_8814B) \
+ << BIT_SHIFT_TXOP_TBTT_CNT_SEL_8814B)
+#define BITS_TXOP_TBTT_CNT_SEL_8814B \
+ (BIT_MASK_TXOP_TBTT_CNT_SEL_8814B << BIT_SHIFT_TXOP_TBTT_CNT_SEL_8814B)
+#define BIT_CLEAR_TXOP_TBTT_CNT_SEL_8814B(x) \
+ ((x) & (~BITS_TXOP_TBTT_CNT_SEL_8814B))
+#define BIT_GET_TXOP_TBTT_CNT_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_TXOP_TBTT_CNT_SEL_8814B) & \
+ BIT_MASK_TXOP_TBTT_CNT_SEL_8814B)
+#define BIT_SET_TXOP_TBTT_CNT_SEL_8814B(x, v) \
+ (BIT_CLEAR_TXOP_TBTT_CNT_SEL_8814B(x) | BIT_TXOP_TBTT_CNT_SEL_8814B(v))
+
+#define BIT_SHIFT_TXOP_LMT_EN_8814B 16
+#define BIT_MASK_TXOP_LMT_EN_8814B 0xf
+#define BIT_TXOP_LMT_EN_8814B(x) \
+ (((x) & BIT_MASK_TXOP_LMT_EN_8814B) << BIT_SHIFT_TXOP_LMT_EN_8814B)
+#define BITS_TXOP_LMT_EN_8814B \
+ (BIT_MASK_TXOP_LMT_EN_8814B << BIT_SHIFT_TXOP_LMT_EN_8814B)
+#define BIT_CLEAR_TXOP_LMT_EN_8814B(x) ((x) & (~BITS_TXOP_LMT_EN_8814B))
+#define BIT_GET_TXOP_LMT_EN_8814B(x) \
+ (((x) >> BIT_SHIFT_TXOP_LMT_EN_8814B) & BIT_MASK_TXOP_LMT_EN_8814B)
+#define BIT_SET_TXOP_LMT_EN_8814B(x, v) \
+ (BIT_CLEAR_TXOP_LMT_EN_8814B(x) | BIT_TXOP_LMT_EN_8814B(v))
+
+#define BIT_SHIFT_TXOP_LMT_TX_TIME_8814B 8
+#define BIT_MASK_TXOP_LMT_TX_TIME_8814B 0xff
+#define BIT_TXOP_LMT_TX_TIME_8814B(x) \
+ (((x) & BIT_MASK_TXOP_LMT_TX_TIME_8814B) \
+ << BIT_SHIFT_TXOP_LMT_TX_TIME_8814B)
+#define BITS_TXOP_LMT_TX_TIME_8814B \
+ (BIT_MASK_TXOP_LMT_TX_TIME_8814B << BIT_SHIFT_TXOP_LMT_TX_TIME_8814B)
+#define BIT_CLEAR_TXOP_LMT_TX_TIME_8814B(x) \
+ ((x) & (~BITS_TXOP_LMT_TX_TIME_8814B))
+#define BIT_GET_TXOP_LMT_TX_TIME_8814B(x) \
+ (((x) >> BIT_SHIFT_TXOP_LMT_TX_TIME_8814B) & \
+ BIT_MASK_TXOP_LMT_TX_TIME_8814B)
+#define BIT_SET_TXOP_LMT_TX_TIME_8814B(x, v) \
+ (BIT_CLEAR_TXOP_LMT_TX_TIME_8814B(x) | BIT_TXOP_LMT_TX_TIME_8814B(v))
+
+#define BIT_TXOP_CNT_TRIGGER_RESET_8814B BIT(7)
+
+#define BIT_SHIFT_TXOP_LMT_PKT_NUM_8814B 0
+#define BIT_MASK_TXOP_LMT_PKT_NUM_8814B 0x3f
+#define BIT_TXOP_LMT_PKT_NUM_8814B(x) \
+ (((x) & BIT_MASK_TXOP_LMT_PKT_NUM_8814B) \
+ << BIT_SHIFT_TXOP_LMT_PKT_NUM_8814B)
+#define BITS_TXOP_LMT_PKT_NUM_8814B \
+ (BIT_MASK_TXOP_LMT_PKT_NUM_8814B << BIT_SHIFT_TXOP_LMT_PKT_NUM_8814B)
+#define BIT_CLEAR_TXOP_LMT_PKT_NUM_8814B(x) \
+ ((x) & (~BITS_TXOP_LMT_PKT_NUM_8814B))
+#define BIT_GET_TXOP_LMT_PKT_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_TXOP_LMT_PKT_NUM_8814B) & \
+ BIT_MASK_TXOP_LMT_PKT_NUM_8814B)
+#define BIT_SET_TXOP_LMT_PKT_NUM_8814B(x, v) \
+ (BIT_CLEAR_TXOP_LMT_PKT_NUM_8814B(x) | BIT_TXOP_LMT_PKT_NUM_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_CCA_TXEN_CNT_8814B */
+#define BIT_CCA_TXEN_CNT_SWITCH_8814B BIT(17)
+#define BIT_CCA_TXEN_CNT_EN_8814B BIT(16)
+
+#define BIT_SHIFT_CCA_TXEN_BIG_CNT_8814B 8
+#define BIT_MASK_CCA_TXEN_BIG_CNT_8814B 0xff
+#define BIT_CCA_TXEN_BIG_CNT_8814B(x) \
+ (((x) & BIT_MASK_CCA_TXEN_BIG_CNT_8814B) \
+ << BIT_SHIFT_CCA_TXEN_BIG_CNT_8814B)
+#define BITS_CCA_TXEN_BIG_CNT_8814B \
+ (BIT_MASK_CCA_TXEN_BIG_CNT_8814B << BIT_SHIFT_CCA_TXEN_BIG_CNT_8814B)
+#define BIT_CLEAR_CCA_TXEN_BIG_CNT_8814B(x) \
+ ((x) & (~BITS_CCA_TXEN_BIG_CNT_8814B))
+#define BIT_GET_CCA_TXEN_BIG_CNT_8814B(x) \
+ (((x) >> BIT_SHIFT_CCA_TXEN_BIG_CNT_8814B) & \
+ BIT_MASK_CCA_TXEN_BIG_CNT_8814B)
+#define BIT_SET_CCA_TXEN_BIG_CNT_8814B(x, v) \
+ (BIT_CLEAR_CCA_TXEN_BIG_CNT_8814B(x) | BIT_CCA_TXEN_BIG_CNT_8814B(v))
+
+#define BIT_SHIFT_CCA_TXEN_SMALL_CNT_8814B 0
+#define BIT_MASK_CCA_TXEN_SMALL_CNT_8814B 0xff
+#define BIT_CCA_TXEN_SMALL_CNT_8814B(x) \
+ (((x) & BIT_MASK_CCA_TXEN_SMALL_CNT_8814B) \
+ << BIT_SHIFT_CCA_TXEN_SMALL_CNT_8814B)
+#define BITS_CCA_TXEN_SMALL_CNT_8814B \
+ (BIT_MASK_CCA_TXEN_SMALL_CNT_8814B \
+ << BIT_SHIFT_CCA_TXEN_SMALL_CNT_8814B)
+#define BIT_CLEAR_CCA_TXEN_SMALL_CNT_8814B(x) \
+ ((x) & (~BITS_CCA_TXEN_SMALL_CNT_8814B))
+#define BIT_GET_CCA_TXEN_SMALL_CNT_8814B(x) \
+ (((x) >> BIT_SHIFT_CCA_TXEN_SMALL_CNT_8814B) & \
+ BIT_MASK_CCA_TXEN_SMALL_CNT_8814B)
+#define BIT_SET_CCA_TXEN_SMALL_CNT_8814B(x, v) \
+ (BIT_CLEAR_CCA_TXEN_SMALL_CNT_8814B(x) | \
+ BIT_CCA_TXEN_SMALL_CNT_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_MAX_INTER_COLLISION_8814B */
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_BK_8814B 24
+#define BIT_MASK_MAX_INTER_COLLISION_BK_8814B 0xff
+#define BIT_MAX_INTER_COLLISION_BK_8814B(x) \
+ (((x) & BIT_MASK_MAX_INTER_COLLISION_BK_8814B) \
+ << BIT_SHIFT_MAX_INTER_COLLISION_BK_8814B)
+#define BITS_MAX_INTER_COLLISION_BK_8814B \
+ (BIT_MASK_MAX_INTER_COLLISION_BK_8814B \
+ << BIT_SHIFT_MAX_INTER_COLLISION_BK_8814B)
+#define BIT_CLEAR_MAX_INTER_COLLISION_BK_8814B(x) \
+ ((x) & (~BITS_MAX_INTER_COLLISION_BK_8814B))
+#define BIT_GET_MAX_INTER_COLLISION_BK_8814B(x) \
+ (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_BK_8814B) & \
+ BIT_MASK_MAX_INTER_COLLISION_BK_8814B)
+#define BIT_SET_MAX_INTER_COLLISION_BK_8814B(x, v) \
+ (BIT_CLEAR_MAX_INTER_COLLISION_BK_8814B(x) | \
+ BIT_MAX_INTER_COLLISION_BK_8814B(v))
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_BE_8814B 16
+#define BIT_MASK_MAX_INTER_COLLISION_BE_8814B 0xff
+#define BIT_MAX_INTER_COLLISION_BE_8814B(x) \
+ (((x) & BIT_MASK_MAX_INTER_COLLISION_BE_8814B) \
+ << BIT_SHIFT_MAX_INTER_COLLISION_BE_8814B)
+#define BITS_MAX_INTER_COLLISION_BE_8814B \
+ (BIT_MASK_MAX_INTER_COLLISION_BE_8814B \
+ << BIT_SHIFT_MAX_INTER_COLLISION_BE_8814B)
+#define BIT_CLEAR_MAX_INTER_COLLISION_BE_8814B(x) \
+ ((x) & (~BITS_MAX_INTER_COLLISION_BE_8814B))
+#define BIT_GET_MAX_INTER_COLLISION_BE_8814B(x) \
+ (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_BE_8814B) & \
+ BIT_MASK_MAX_INTER_COLLISION_BE_8814B)
+#define BIT_SET_MAX_INTER_COLLISION_BE_8814B(x, v) \
+ (BIT_CLEAR_MAX_INTER_COLLISION_BE_8814B(x) | \
+ BIT_MAX_INTER_COLLISION_BE_8814B(v))
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_VI_8814B 8
+#define BIT_MASK_MAX_INTER_COLLISION_VI_8814B 0xff
+#define BIT_MAX_INTER_COLLISION_VI_8814B(x) \
+ (((x) & BIT_MASK_MAX_INTER_COLLISION_VI_8814B) \
+ << BIT_SHIFT_MAX_INTER_COLLISION_VI_8814B)
+#define BITS_MAX_INTER_COLLISION_VI_8814B \
+ (BIT_MASK_MAX_INTER_COLLISION_VI_8814B \
+ << BIT_SHIFT_MAX_INTER_COLLISION_VI_8814B)
+#define BIT_CLEAR_MAX_INTER_COLLISION_VI_8814B(x) \
+ ((x) & (~BITS_MAX_INTER_COLLISION_VI_8814B))
+#define BIT_GET_MAX_INTER_COLLISION_VI_8814B(x) \
+ (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_VI_8814B) & \
+ BIT_MASK_MAX_INTER_COLLISION_VI_8814B)
+#define BIT_SET_MAX_INTER_COLLISION_VI_8814B(x, v) \
+ (BIT_CLEAR_MAX_INTER_COLLISION_VI_8814B(x) | \
+ BIT_MAX_INTER_COLLISION_VI_8814B(v))
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_VO_8814B 0
+#define BIT_MASK_MAX_INTER_COLLISION_VO_8814B 0xff
+#define BIT_MAX_INTER_COLLISION_VO_8814B(x) \
+ (((x) & BIT_MASK_MAX_INTER_COLLISION_VO_8814B) \
+ << BIT_SHIFT_MAX_INTER_COLLISION_VO_8814B)
+#define BITS_MAX_INTER_COLLISION_VO_8814B \
+ (BIT_MASK_MAX_INTER_COLLISION_VO_8814B \
+ << BIT_SHIFT_MAX_INTER_COLLISION_VO_8814B)
+#define BIT_CLEAR_MAX_INTER_COLLISION_VO_8814B(x) \
+ ((x) & (~BITS_MAX_INTER_COLLISION_VO_8814B))
+#define BIT_GET_MAX_INTER_COLLISION_VO_8814B(x) \
+ (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_VO_8814B) & \
+ BIT_MASK_MAX_INTER_COLLISION_VO_8814B)
+#define BIT_SET_MAX_INTER_COLLISION_VO_8814B(x, v) \
+ (BIT_CLEAR_MAX_INTER_COLLISION_VO_8814B(x) | \
+ BIT_MAX_INTER_COLLISION_VO_8814B(v))
+
+/* 2 REG_MAX_INTER_COLLISION_CNT_8814B */
+#define BIT_MAX_INTER_COLLISION_EN_8814B BIT(16)
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8814B 12
+#define BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8814B 0xf
+#define BIT_MAX_INTER_COLLISION_CNT_BK_8814B(x) \
+ (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8814B) \
+ << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8814B)
+#define BITS_MAX_INTER_COLLISION_CNT_BK_8814B \
+ (BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8814B \
+ << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8814B)
+#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_BK_8814B(x) \
+ ((x) & (~BITS_MAX_INTER_COLLISION_CNT_BK_8814B))
+#define BIT_GET_MAX_INTER_COLLISION_CNT_BK_8814B(x) \
+ (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8814B) & \
+ BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8814B)
+#define BIT_SET_MAX_INTER_COLLISION_CNT_BK_8814B(x, v) \
+ (BIT_CLEAR_MAX_INTER_COLLISION_CNT_BK_8814B(x) | \
+ BIT_MAX_INTER_COLLISION_CNT_BK_8814B(v))
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8814B 8
+#define BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8814B 0xf
+#define BIT_MAX_INTER_COLLISION_CNT_BE_8814B(x) \
+ (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8814B) \
+ << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8814B)
+#define BITS_MAX_INTER_COLLISION_CNT_BE_8814B \
+ (BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8814B \
+ << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8814B)
+#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_BE_8814B(x) \
+ ((x) & (~BITS_MAX_INTER_COLLISION_CNT_BE_8814B))
+#define BIT_GET_MAX_INTER_COLLISION_CNT_BE_8814B(x) \
+ (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8814B) & \
+ BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8814B)
+#define BIT_SET_MAX_INTER_COLLISION_CNT_BE_8814B(x, v) \
+ (BIT_CLEAR_MAX_INTER_COLLISION_CNT_BE_8814B(x) | \
+ BIT_MAX_INTER_COLLISION_CNT_BE_8814B(v))
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8814B 4
+#define BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8814B 0xf
+#define BIT_MAX_INTER_COLLISION_CNT_VI_8814B(x) \
+ (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8814B) \
+ << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8814B)
+#define BITS_MAX_INTER_COLLISION_CNT_VI_8814B \
+ (BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8814B \
+ << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8814B)
+#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_VI_8814B(x) \
+ ((x) & (~BITS_MAX_INTER_COLLISION_CNT_VI_8814B))
+#define BIT_GET_MAX_INTER_COLLISION_CNT_VI_8814B(x) \
+ (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8814B) & \
+ BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8814B)
+#define BIT_SET_MAX_INTER_COLLISION_CNT_VI_8814B(x, v) \
+ (BIT_CLEAR_MAX_INTER_COLLISION_CNT_VI_8814B(x) | \
+ BIT_MAX_INTER_COLLISION_CNT_VI_8814B(v))
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8814B 0
+#define BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8814B 0xf
+#define BIT_MAX_INTER_COLLISION_CNT_VO_8814B(x) \
+ (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8814B) \
+ << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8814B)
+#define BITS_MAX_INTER_COLLISION_CNT_VO_8814B \
+ (BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8814B \
+ << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8814B)
+#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_VO_8814B(x) \
+ ((x) & (~BITS_MAX_INTER_COLLISION_CNT_VO_8814B))
+#define BIT_GET_MAX_INTER_COLLISION_CNT_VO_8814B(x) \
+ (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8814B) & \
+ BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8814B)
+#define BIT_SET_MAX_INTER_COLLISION_CNT_VO_8814B(x, v) \
+ (BIT_CLEAR_MAX_INTER_COLLISION_CNT_VO_8814B(x) | \
+ BIT_MAX_INTER_COLLISION_CNT_VO_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_RD_NAV_NXT_8814B */
+
+#define BIT_SHIFT_RD_NAV_PROT_NXT_8814B 0
+#define BIT_MASK_RD_NAV_PROT_NXT_8814B 0xffff
+#define BIT_RD_NAV_PROT_NXT_8814B(x) \
+ (((x) & BIT_MASK_RD_NAV_PROT_NXT_8814B) \
+ << BIT_SHIFT_RD_NAV_PROT_NXT_8814B)
+#define BITS_RD_NAV_PROT_NXT_8814B \
+ (BIT_MASK_RD_NAV_PROT_NXT_8814B << BIT_SHIFT_RD_NAV_PROT_NXT_8814B)
+#define BIT_CLEAR_RD_NAV_PROT_NXT_8814B(x) ((x) & (~BITS_RD_NAV_PROT_NXT_8814B))
+#define BIT_GET_RD_NAV_PROT_NXT_8814B(x) \
+ (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8814B) & \
+ BIT_MASK_RD_NAV_PROT_NXT_8814B)
+#define BIT_SET_RD_NAV_PROT_NXT_8814B(x, v) \
+ (BIT_CLEAR_RD_NAV_PROT_NXT_8814B(x) | BIT_RD_NAV_PROT_NXT_8814B(v))
+
+/* 2 REG_NAV_PROT_LEN_8814B */
+
+#define BIT_SHIFT_NAV_PROT_LEN_8814B 0
+#define BIT_MASK_NAV_PROT_LEN_8814B 0xffff
+#define BIT_NAV_PROT_LEN_8814B(x) \
+ (((x) & BIT_MASK_NAV_PROT_LEN_8814B) << BIT_SHIFT_NAV_PROT_LEN_8814B)
+#define BITS_NAV_PROT_LEN_8814B \
+ (BIT_MASK_NAV_PROT_LEN_8814B << BIT_SHIFT_NAV_PROT_LEN_8814B)
+#define BIT_CLEAR_NAV_PROT_LEN_8814B(x) ((x) & (~BITS_NAV_PROT_LEN_8814B))
+#define BIT_GET_NAV_PROT_LEN_8814B(x) \
+ (((x) >> BIT_SHIFT_NAV_PROT_LEN_8814B) & BIT_MASK_NAV_PROT_LEN_8814B)
+#define BIT_SET_NAV_PROT_LEN_8814B(x, v) \
+ (BIT_CLEAR_NAV_PROT_LEN_8814B(x) | BIT_NAV_PROT_LEN_8814B(v))
+
+/* 2 REG_FTM_PTT_8814B */
+
+#define BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8814B 22
+#define BIT_MASK_FTM_PTT_TSF_R2T_SEL_8814B 0x7
+#define BIT_FTM_PTT_TSF_R2T_SEL_8814B(x) \
+ (((x) & BIT_MASK_FTM_PTT_TSF_R2T_SEL_8814B) \
+ << BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8814B)
+#define BITS_FTM_PTT_TSF_R2T_SEL_8814B \
+ (BIT_MASK_FTM_PTT_TSF_R2T_SEL_8814B \
+ << BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8814B)
+#define BIT_CLEAR_FTM_PTT_TSF_R2T_SEL_8814B(x) \
+ ((x) & (~BITS_FTM_PTT_TSF_R2T_SEL_8814B))
+#define BIT_GET_FTM_PTT_TSF_R2T_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8814B) & \
+ BIT_MASK_FTM_PTT_TSF_R2T_SEL_8814B)
+#define BIT_SET_FTM_PTT_TSF_R2T_SEL_8814B(x, v) \
+ (BIT_CLEAR_FTM_PTT_TSF_R2T_SEL_8814B(x) | \
+ BIT_FTM_PTT_TSF_R2T_SEL_8814B(v))
+
+#define BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8814B 19
+#define BIT_MASK_FTM_PTT_TSF_T2R_SEL_8814B 0x7
+#define BIT_FTM_PTT_TSF_T2R_SEL_8814B(x) \
+ (((x) & BIT_MASK_FTM_PTT_TSF_T2R_SEL_8814B) \
+ << BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8814B)
+#define BITS_FTM_PTT_TSF_T2R_SEL_8814B \
+ (BIT_MASK_FTM_PTT_TSF_T2R_SEL_8814B \
+ << BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8814B)
+#define BIT_CLEAR_FTM_PTT_TSF_T2R_SEL_8814B(x) \
+ ((x) & (~BITS_FTM_PTT_TSF_T2R_SEL_8814B))
+#define BIT_GET_FTM_PTT_TSF_T2R_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8814B) & \
+ BIT_MASK_FTM_PTT_TSF_T2R_SEL_8814B)
+#define BIT_SET_FTM_PTT_TSF_T2R_SEL_8814B(x, v) \
+ (BIT_CLEAR_FTM_PTT_TSF_T2R_SEL_8814B(x) | \
+ BIT_FTM_PTT_TSF_T2R_SEL_8814B(v))
+
+#define BIT_SHIFT_FTM_PTT_TSF_SEL_8814B 16
+#define BIT_MASK_FTM_PTT_TSF_SEL_8814B 0x7
+#define BIT_FTM_PTT_TSF_SEL_8814B(x) \
+ (((x) & BIT_MASK_FTM_PTT_TSF_SEL_8814B) \
+ << BIT_SHIFT_FTM_PTT_TSF_SEL_8814B)
+#define BITS_FTM_PTT_TSF_SEL_8814B \
+ (BIT_MASK_FTM_PTT_TSF_SEL_8814B << BIT_SHIFT_FTM_PTT_TSF_SEL_8814B)
+#define BIT_CLEAR_FTM_PTT_TSF_SEL_8814B(x) ((x) & (~BITS_FTM_PTT_TSF_SEL_8814B))
+#define BIT_GET_FTM_PTT_TSF_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_FTM_PTT_TSF_SEL_8814B) & \
+ BIT_MASK_FTM_PTT_TSF_SEL_8814B)
+#define BIT_SET_FTM_PTT_TSF_SEL_8814B(x, v) \
+ (BIT_CLEAR_FTM_PTT_TSF_SEL_8814B(x) | BIT_FTM_PTT_TSF_SEL_8814B(v))
+
+#define BIT_SHIFT_FTM_PTT_VALUE_8814B 0
+#define BIT_MASK_FTM_PTT_VALUE_8814B 0xffff
+#define BIT_FTM_PTT_VALUE_8814B(x) \
+ (((x) & BIT_MASK_FTM_PTT_VALUE_8814B) << BIT_SHIFT_FTM_PTT_VALUE_8814B)
+#define BITS_FTM_PTT_VALUE_8814B \
+ (BIT_MASK_FTM_PTT_VALUE_8814B << BIT_SHIFT_FTM_PTT_VALUE_8814B)
+#define BIT_CLEAR_FTM_PTT_VALUE_8814B(x) ((x) & (~BITS_FTM_PTT_VALUE_8814B))
+#define BIT_GET_FTM_PTT_VALUE_8814B(x) \
+ (((x) >> BIT_SHIFT_FTM_PTT_VALUE_8814B) & BIT_MASK_FTM_PTT_VALUE_8814B)
+#define BIT_SET_FTM_PTT_VALUE_8814B(x, v) \
+ (BIT_CLEAR_FTM_PTT_VALUE_8814B(x) | BIT_FTM_PTT_VALUE_8814B(v))
+
+/* 2 REG_FTM_TSF_8814B */
+
+#define BIT_SHIFT_FTM_T2_TSF_8814B 16
+#define BIT_MASK_FTM_T2_TSF_8814B 0xffff
+#define BIT_FTM_T2_TSF_8814B(x) \
+ (((x) & BIT_MASK_FTM_T2_TSF_8814B) << BIT_SHIFT_FTM_T2_TSF_8814B)
+#define BITS_FTM_T2_TSF_8814B \
+ (BIT_MASK_FTM_T2_TSF_8814B << BIT_SHIFT_FTM_T2_TSF_8814B)
+#define BIT_CLEAR_FTM_T2_TSF_8814B(x) ((x) & (~BITS_FTM_T2_TSF_8814B))
+#define BIT_GET_FTM_T2_TSF_8814B(x) \
+ (((x) >> BIT_SHIFT_FTM_T2_TSF_8814B) & BIT_MASK_FTM_T2_TSF_8814B)
+#define BIT_SET_FTM_T2_TSF_8814B(x, v) \
+ (BIT_CLEAR_FTM_T2_TSF_8814B(x) | BIT_FTM_T2_TSF_8814B(v))
+
+#define BIT_SHIFT_FTM_T1_TSF_8814B 0
+#define BIT_MASK_FTM_T1_TSF_8814B 0xffff
+#define BIT_FTM_T1_TSF_8814B(x) \
+ (((x) & BIT_MASK_FTM_T1_TSF_8814B) << BIT_SHIFT_FTM_T1_TSF_8814B)
+#define BITS_FTM_T1_TSF_8814B \
+ (BIT_MASK_FTM_T1_TSF_8814B << BIT_SHIFT_FTM_T1_TSF_8814B)
+#define BIT_CLEAR_FTM_T1_TSF_8814B(x) ((x) & (~BITS_FTM_T1_TSF_8814B))
+#define BIT_GET_FTM_T1_TSF_8814B(x) \
+ (((x) >> BIT_SHIFT_FTM_T1_TSF_8814B) & BIT_MASK_FTM_T1_TSF_8814B)
+#define BIT_SET_FTM_T1_TSF_8814B(x, v) \
+ (BIT_CLEAR_FTM_T1_TSF_8814B(x) | BIT_FTM_T1_TSF_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_HGQ_TIMEOUT_PERIOD_8814B */
+
+#define BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8814B 0
+#define BIT_MASK_HGQ_TIMEOUT_PERIOD_8814B 0xff
+#define BIT_HGQ_TIMEOUT_PERIOD_8814B(x) \
+ (((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8814B) \
+ << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8814B)
+#define BITS_HGQ_TIMEOUT_PERIOD_8814B \
+ (BIT_MASK_HGQ_TIMEOUT_PERIOD_8814B \
+ << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8814B)
+#define BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8814B(x) \
+ ((x) & (~BITS_HGQ_TIMEOUT_PERIOD_8814B))
+#define BIT_GET_HGQ_TIMEOUT_PERIOD_8814B(x) \
+ (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8814B) & \
+ BIT_MASK_HGQ_TIMEOUT_PERIOD_8814B)
+#define BIT_SET_HGQ_TIMEOUT_PERIOD_8814B(x, v) \
+ (BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8814B(x) | \
+ BIT_HGQ_TIMEOUT_PERIOD_8814B(v))
+
+/* 2 REG_TXCMD_TIMEOUT_PERIOD_8814B */
+
+#define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8814B 0
+#define BIT_MASK_TXCMD_TIMEOUT_PERIOD_8814B 0xff
+#define BIT_TXCMD_TIMEOUT_PERIOD_8814B(x) \
+ (((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8814B) \
+ << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8814B)
+#define BITS_TXCMD_TIMEOUT_PERIOD_8814B \
+ (BIT_MASK_TXCMD_TIMEOUT_PERIOD_8814B \
+ << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8814B)
+#define BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8814B(x) \
+ ((x) & (~BITS_TXCMD_TIMEOUT_PERIOD_8814B))
+#define BIT_GET_TXCMD_TIMEOUT_PERIOD_8814B(x) \
+ (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8814B) & \
+ BIT_MASK_TXCMD_TIMEOUT_PERIOD_8814B)
+#define BIT_SET_TXCMD_TIMEOUT_PERIOD_8814B(x, v) \
+ (BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8814B(x) | \
+ BIT_TXCMD_TIMEOUT_PERIOD_8814B(v))
+
+/* 2 REG_MISC_CTRL_8814B */
+#define BIT_DIS_SECONDARY_CCA_80M_8814B BIT(2)
+#define BIT_DIS_SECONDARY_CCA_40M_8814B BIT(1)
+#define BIT_DIS_SECONDARY_CCA_20M_8814B BIT(0)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_TXOP_MIN_8814B */
+#define BIT_HIQ_NAV_BREAK_EN_8814B BIT(15)
+#define BIT_MGQ_NAV_BREAK_EN_8814B BIT(14)
+
+#define BIT_SHIFT_TXOP_MIN_8814B 0
+#define BIT_MASK_TXOP_MIN_8814B 0x3fff
+#define BIT_TXOP_MIN_8814B(x) \
+ (((x) & BIT_MASK_TXOP_MIN_8814B) << BIT_SHIFT_TXOP_MIN_8814B)
+#define BITS_TXOP_MIN_8814B \
+ (BIT_MASK_TXOP_MIN_8814B << BIT_SHIFT_TXOP_MIN_8814B)
+#define BIT_CLEAR_TXOP_MIN_8814B(x) ((x) & (~BITS_TXOP_MIN_8814B))
+#define BIT_GET_TXOP_MIN_8814B(x) \
+ (((x) >> BIT_SHIFT_TXOP_MIN_8814B) & BIT_MASK_TXOP_MIN_8814B)
+#define BIT_SET_TXOP_MIN_8814B(x, v) \
+ (BIT_CLEAR_TXOP_MIN_8814B(x) | BIT_TXOP_MIN_8814B(v))
+
+/* 2 REG_PRE_BKF_TIME_8814B */
+
+#define BIT_SHIFT_PRE_BKF_TIME_8814B 0
+#define BIT_MASK_PRE_BKF_TIME_8814B 0xff
+#define BIT_PRE_BKF_TIME_8814B(x) \
+ (((x) & BIT_MASK_PRE_BKF_TIME_8814B) << BIT_SHIFT_PRE_BKF_TIME_8814B)
+#define BITS_PRE_BKF_TIME_8814B \
+ (BIT_MASK_PRE_BKF_TIME_8814B << BIT_SHIFT_PRE_BKF_TIME_8814B)
+#define BIT_CLEAR_PRE_BKF_TIME_8814B(x) ((x) & (~BITS_PRE_BKF_TIME_8814B))
+#define BIT_GET_PRE_BKF_TIME_8814B(x) \
+ (((x) >> BIT_SHIFT_PRE_BKF_TIME_8814B) & BIT_MASK_PRE_BKF_TIME_8814B)
+#define BIT_SET_PRE_BKF_TIME_8814B(x, v) \
+ (BIT_CLEAR_PRE_BKF_TIME_8814B(x) | BIT_PRE_BKF_TIME_8814B(v))
+
+/* 2 REG_CROSS_TXOP_CTRL_8814B */
+#define BIT_TBTT_RETRY_8814B BIT(4)
+#define BIT_TXFAIL_BREACK_TXOP_EN_8814B BIT(3)
+#define BIT_RTS_NAV_TXOP_8814B BIT(1)
+#define BIT_NOT_CROSS_TXOP_8814B BIT(0)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_ACMHWCTRL_8814B */
+#define BIT_BEQ_ACM_STATUS_8814B BIT(7)
+#define BIT_VIQ_ACM_STATUS_8814B BIT(6)
+#define BIT_VOQ_ACM_STATUS_8814B BIT(5)
+#define BIT_BEQ_ACM_EN_8814B BIT(3)
+#define BIT_VIQ_ACM_EN_8814B BIT(2)
+#define BIT_VOQ_ACM_EN_8814B BIT(1)
+#define BIT_ACMHWEN_8814B BIT(0)
+
+/* 2 REG_ACMRSTCTRL_8814B */
+#define BIT_BE_ACM_RESET_USED_TIME_8814B BIT(2)
+#define BIT_VI_ACM_RESET_USED_TIME_8814B BIT(1)
+#define BIT_VO_ACM_RESET_USED_TIME_8814B BIT(0)
+
+/* 2 REG_ACMAVG_8814B */
+
+#define BIT_SHIFT_AVGPERIOD_8814B 0
+#define BIT_MASK_AVGPERIOD_8814B 0xffff
+#define BIT_AVGPERIOD_8814B(x) \
+ (((x) & BIT_MASK_AVGPERIOD_8814B) << BIT_SHIFT_AVGPERIOD_8814B)
+#define BITS_AVGPERIOD_8814B \
+ (BIT_MASK_AVGPERIOD_8814B << BIT_SHIFT_AVGPERIOD_8814B)
+#define BIT_CLEAR_AVGPERIOD_8814B(x) ((x) & (~BITS_AVGPERIOD_8814B))
+#define BIT_GET_AVGPERIOD_8814B(x) \
+ (((x) >> BIT_SHIFT_AVGPERIOD_8814B) & BIT_MASK_AVGPERIOD_8814B)
+#define BIT_SET_AVGPERIOD_8814B(x, v) \
+ (BIT_CLEAR_AVGPERIOD_8814B(x) | BIT_AVGPERIOD_8814B(v))
+
+/* 2 REG_VO_ADMTIME_8814B */
+
+#define BIT_SHIFT_VO_ADMITTED_TIME_8814B 0
+#define BIT_MASK_VO_ADMITTED_TIME_8814B 0xffff
+#define BIT_VO_ADMITTED_TIME_8814B(x) \
+ (((x) & BIT_MASK_VO_ADMITTED_TIME_8814B) \
+ << BIT_SHIFT_VO_ADMITTED_TIME_8814B)
+#define BITS_VO_ADMITTED_TIME_8814B \
+ (BIT_MASK_VO_ADMITTED_TIME_8814B << BIT_SHIFT_VO_ADMITTED_TIME_8814B)
+#define BIT_CLEAR_VO_ADMITTED_TIME_8814B(x) \
+ ((x) & (~BITS_VO_ADMITTED_TIME_8814B))
+#define BIT_GET_VO_ADMITTED_TIME_8814B(x) \
+ (((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8814B) & \
+ BIT_MASK_VO_ADMITTED_TIME_8814B)
+#define BIT_SET_VO_ADMITTED_TIME_8814B(x, v) \
+ (BIT_CLEAR_VO_ADMITTED_TIME_8814B(x) | BIT_VO_ADMITTED_TIME_8814B(v))
+
+/* 2 REG_VI_ADMTIME_8814B */
+
+#define BIT_SHIFT_VI_ADMITTED_TIME_8814B 0
+#define BIT_MASK_VI_ADMITTED_TIME_8814B 0xffff
+#define BIT_VI_ADMITTED_TIME_8814B(x) \
+ (((x) & BIT_MASK_VI_ADMITTED_TIME_8814B) \
+ << BIT_SHIFT_VI_ADMITTED_TIME_8814B)
+#define BITS_VI_ADMITTED_TIME_8814B \
+ (BIT_MASK_VI_ADMITTED_TIME_8814B << BIT_SHIFT_VI_ADMITTED_TIME_8814B)
+#define BIT_CLEAR_VI_ADMITTED_TIME_8814B(x) \
+ ((x) & (~BITS_VI_ADMITTED_TIME_8814B))
+#define BIT_GET_VI_ADMITTED_TIME_8814B(x) \
+ (((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8814B) & \
+ BIT_MASK_VI_ADMITTED_TIME_8814B)
+#define BIT_SET_VI_ADMITTED_TIME_8814B(x, v) \
+ (BIT_CLEAR_VI_ADMITTED_TIME_8814B(x) | BIT_VI_ADMITTED_TIME_8814B(v))
+
+/* 2 REG_BE_ADMTIME_8814B */
+
+#define BIT_SHIFT_BE_ADMITTED_TIME_8814B 0
+#define BIT_MASK_BE_ADMITTED_TIME_8814B 0xffff
+#define BIT_BE_ADMITTED_TIME_8814B(x) \
+ (((x) & BIT_MASK_BE_ADMITTED_TIME_8814B) \
+ << BIT_SHIFT_BE_ADMITTED_TIME_8814B)
+#define BITS_BE_ADMITTED_TIME_8814B \
+ (BIT_MASK_BE_ADMITTED_TIME_8814B << BIT_SHIFT_BE_ADMITTED_TIME_8814B)
+#define BIT_CLEAR_BE_ADMITTED_TIME_8814B(x) \
+ ((x) & (~BITS_BE_ADMITTED_TIME_8814B))
+#define BIT_GET_BE_ADMITTED_TIME_8814B(x) \
+ (((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8814B) & \
+ BIT_MASK_BE_ADMITTED_TIME_8814B)
+#define BIT_SET_BE_ADMITTED_TIME_8814B(x, v) \
+ (BIT_CLEAR_BE_ADMITTED_TIME_8814B(x) | BIT_BE_ADMITTED_TIME_8814B(v))
+
+/* 2 REG_MAC_HEADER_NAV_OFFSET_8814B */
+
+#define BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8814B 0
+#define BIT_MASK_MAC_HEADER_NAV_OFFSET_8814B 0xff
+#define BIT_MAC_HEADER_NAV_OFFSET_8814B(x) \
+ (((x) & BIT_MASK_MAC_HEADER_NAV_OFFSET_8814B) \
+ << BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8814B)
+#define BITS_MAC_HEADER_NAV_OFFSET_8814B \
+ (BIT_MASK_MAC_HEADER_NAV_OFFSET_8814B \
+ << BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8814B)
+#define BIT_CLEAR_MAC_HEADER_NAV_OFFSET_8814B(x) \
+ ((x) & (~BITS_MAC_HEADER_NAV_OFFSET_8814B))
+#define BIT_GET_MAC_HEADER_NAV_OFFSET_8814B(x) \
+ (((x) >> BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8814B) & \
+ BIT_MASK_MAC_HEADER_NAV_OFFSET_8814B)
+#define BIT_SET_MAC_HEADER_NAV_OFFSET_8814B(x, v) \
+ (BIT_CLEAR_MAC_HEADER_NAV_OFFSET_8814B(x) | \
+ BIT_MAC_HEADER_NAV_OFFSET_8814B(v))
+
+/* 2 REG_DIS_NDPA_NAV_CHECK_8814B */
+#define BIT_DIS_NDPA_NAV_CHECK_8814B BIT(0)
+
+/* 2 REG_EDCA_RANDOM_GEN_8814B */
+
+#define BIT_SHIFT_RANDOM_GEN_8814B 0
+#define BIT_MASK_RANDOM_GEN_8814B 0xffffff
+#define BIT_RANDOM_GEN_8814B(x) \
+ (((x) & BIT_MASK_RANDOM_GEN_8814B) << BIT_SHIFT_RANDOM_GEN_8814B)
+#define BITS_RANDOM_GEN_8814B \
+ (BIT_MASK_RANDOM_GEN_8814B << BIT_SHIFT_RANDOM_GEN_8814B)
+#define BIT_CLEAR_RANDOM_GEN_8814B(x) ((x) & (~BITS_RANDOM_GEN_8814B))
+#define BIT_GET_RANDOM_GEN_8814B(x) \
+ (((x) >> BIT_SHIFT_RANDOM_GEN_8814B) & BIT_MASK_RANDOM_GEN_8814B)
+#define BIT_SET_RANDOM_GEN_8814B(x, v) \
+ (BIT_CLEAR_RANDOM_GEN_8814B(x) | BIT_RANDOM_GEN_8814B(v))
+
+/* 2 REG_TXCMD_SEL_8814B */
+
+#define BIT_SHIFT_TXCMD_SEG_SEL_8814B 0
+#define BIT_MASK_TXCMD_SEG_SEL_8814B 0xf
+#define BIT_TXCMD_SEG_SEL_8814B(x) \
+ (((x) & BIT_MASK_TXCMD_SEG_SEL_8814B) << BIT_SHIFT_TXCMD_SEG_SEL_8814B)
+#define BITS_TXCMD_SEG_SEL_8814B \
+ (BIT_MASK_TXCMD_SEG_SEL_8814B << BIT_SHIFT_TXCMD_SEG_SEL_8814B)
+#define BIT_CLEAR_TXCMD_SEG_SEL_8814B(x) ((x) & (~BITS_TXCMD_SEG_SEL_8814B))
+#define BIT_GET_TXCMD_SEG_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8814B) & BIT_MASK_TXCMD_SEG_SEL_8814B)
+#define BIT_SET_TXCMD_SEG_SEL_8814B(x, v) \
+ (BIT_CLEAR_TXCMD_SEG_SEL_8814B(x) | BIT_TXCMD_SEG_SEL_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_MU_DBG_INFO_8814B */
+
+#define BIT_SHIFT_MU_DBG_INFO_8814B 0
+#define BIT_MASK_MU_DBG_INFO_8814B 0xffffffffL
+#define BIT_MU_DBG_INFO_8814B(x) \
+ (((x) & BIT_MASK_MU_DBG_INFO_8814B) << BIT_SHIFT_MU_DBG_INFO_8814B)
+#define BITS_MU_DBG_INFO_8814B \
+ (BIT_MASK_MU_DBG_INFO_8814B << BIT_SHIFT_MU_DBG_INFO_8814B)
+#define BIT_CLEAR_MU_DBG_INFO_8814B(x) ((x) & (~BITS_MU_DBG_INFO_8814B))
+#define BIT_GET_MU_DBG_INFO_8814B(x) \
+ (((x) >> BIT_SHIFT_MU_DBG_INFO_8814B) & BIT_MASK_MU_DBG_INFO_8814B)
+#define BIT_SET_MU_DBG_INFO_8814B(x, v) \
+ (BIT_CLEAR_MU_DBG_INFO_8814B(x) | BIT_MU_DBG_INFO_8814B(v))
+
+/* 2 REG_MU_DBG_INFO_1_8814B */
+
+#define BIT_SHIFT_MU_DBG_INFO_1_8814B 0
+#define BIT_MASK_MU_DBG_INFO_1_8814B 0xffffffffL
+#define BIT_MU_DBG_INFO_1_8814B(x) \
+ (((x) & BIT_MASK_MU_DBG_INFO_1_8814B) << BIT_SHIFT_MU_DBG_INFO_1_8814B)
+#define BITS_MU_DBG_INFO_1_8814B \
+ (BIT_MASK_MU_DBG_INFO_1_8814B << BIT_SHIFT_MU_DBG_INFO_1_8814B)
+#define BIT_CLEAR_MU_DBG_INFO_1_8814B(x) ((x) & (~BITS_MU_DBG_INFO_1_8814B))
+#define BIT_GET_MU_DBG_INFO_1_8814B(x) \
+ (((x) >> BIT_SHIFT_MU_DBG_INFO_1_8814B) & BIT_MASK_MU_DBG_INFO_1_8814B)
+#define BIT_SET_MU_DBG_INFO_1_8814B(x, v) \
+ (BIT_CLEAR_MU_DBG_INFO_1_8814B(x) | BIT_MU_DBG_INFO_1_8814B(v))
+
+/* 2 REG_SCH_DBG_SEL_8814B */
+
+#define BIT_SHIFT_SCH_DBG_SEL_8814B 0
+#define BIT_MASK_SCH_DBG_SEL_8814B 0xff
+#define BIT_SCH_DBG_SEL_8814B(x) \
+ (((x) & BIT_MASK_SCH_DBG_SEL_8814B) << BIT_SHIFT_SCH_DBG_SEL_8814B)
+#define BITS_SCH_DBG_SEL_8814B \
+ (BIT_MASK_SCH_DBG_SEL_8814B << BIT_SHIFT_SCH_DBG_SEL_8814B)
+#define BIT_CLEAR_SCH_DBG_SEL_8814B(x) ((x) & (~BITS_SCH_DBG_SEL_8814B))
+#define BIT_GET_SCH_DBG_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_SCH_DBG_SEL_8814B) & BIT_MASK_SCH_DBG_SEL_8814B)
+#define BIT_SET_SCH_DBG_SEL_8814B(x, v) \
+ (BIT_CLEAR_SCH_DBG_SEL_8814B(x) | BIT_SCH_DBG_SEL_8814B(v))
+
+/* 2 REG_SCHEDULER_RST_8814B */
+#define BIT_SCHEDULER_RST_V1_8814B BIT(0)
+
+/* 2 REG_MU_DBG_ERR_FLAG_8814B */
+#define BIT_BCN_PORTID_ERR_8814B BIT(2)
+
+#define BIT_SHIFT_MU_DBG_ERR_FLAG_8814B 0
+#define BIT_MASK_MU_DBG_ERR_FLAG_8814B 0x3
+#define BIT_MU_DBG_ERR_FLAG_8814B(x) \
+ (((x) & BIT_MASK_MU_DBG_ERR_FLAG_8814B) \
+ << BIT_SHIFT_MU_DBG_ERR_FLAG_8814B)
+#define BITS_MU_DBG_ERR_FLAG_8814B \
+ (BIT_MASK_MU_DBG_ERR_FLAG_8814B << BIT_SHIFT_MU_DBG_ERR_FLAG_8814B)
+#define BIT_CLEAR_MU_DBG_ERR_FLAG_8814B(x) ((x) & (~BITS_MU_DBG_ERR_FLAG_8814B))
+#define BIT_GET_MU_DBG_ERR_FLAG_8814B(x) \
+ (((x) >> BIT_SHIFT_MU_DBG_ERR_FLAG_8814B) & \
+ BIT_MASK_MU_DBG_ERR_FLAG_8814B)
+#define BIT_SET_MU_DBG_ERR_FLAG_8814B(x, v) \
+ (BIT_CLEAR_MU_DBG_ERR_FLAG_8814B(x) | BIT_MU_DBG_ERR_FLAG_8814B(v))
+
+/* 2 REG_TX_ERR_RECOVERY_RST_8814B */
+
+#define BIT_SHIFT_ERR_RECOVER_CNT_8814B 4
+#define BIT_MASK_ERR_RECOVER_CNT_8814B 0xf
+#define BIT_ERR_RECOVER_CNT_8814B(x) \
+ (((x) & BIT_MASK_ERR_RECOVER_CNT_8814B) \
+ << BIT_SHIFT_ERR_RECOVER_CNT_8814B)
+#define BITS_ERR_RECOVER_CNT_8814B \
+ (BIT_MASK_ERR_RECOVER_CNT_8814B << BIT_SHIFT_ERR_RECOVER_CNT_8814B)
+#define BIT_CLEAR_ERR_RECOVER_CNT_8814B(x) ((x) & (~BITS_ERR_RECOVER_CNT_8814B))
+#define BIT_GET_ERR_RECOVER_CNT_8814B(x) \
+ (((x) >> BIT_SHIFT_ERR_RECOVER_CNT_8814B) & \
+ BIT_MASK_ERR_RECOVER_CNT_8814B)
+#define BIT_SET_ERR_RECOVER_CNT_8814B(x, v) \
+ (BIT_CLEAR_ERR_RECOVER_CNT_8814B(x) | BIT_ERR_RECOVER_CNT_8814B(v))
+
+#define BIT_RX_HANG_ERR_8814B BIT(2)
+#define BIT_TX_HANG_ERR_8814B BIT(1)
+#define BIT_TX_ERR_RECOVERY_RST_8814B BIT(0)
+
+/* 2 REG_SCH_DBG_VALUE_8814B */
+
+#define BIT_SHIFT_SCH_DBG_VALUE_8814B 0
+#define BIT_MASK_SCH_DBG_VALUE_8814B 0xffffffffL
+#define BIT_SCH_DBG_VALUE_8814B(x) \
+ (((x) & BIT_MASK_SCH_DBG_VALUE_8814B) << BIT_SHIFT_SCH_DBG_VALUE_8814B)
+#define BITS_SCH_DBG_VALUE_8814B \
+ (BIT_MASK_SCH_DBG_VALUE_8814B << BIT_SHIFT_SCH_DBG_VALUE_8814B)
+#define BIT_CLEAR_SCH_DBG_VALUE_8814B(x) ((x) & (~BITS_SCH_DBG_VALUE_8814B))
+#define BIT_GET_SCH_DBG_VALUE_8814B(x) \
+ (((x) >> BIT_SHIFT_SCH_DBG_VALUE_8814B) & BIT_MASK_SCH_DBG_VALUE_8814B)
+#define BIT_SET_SCH_DBG_VALUE_8814B(x, v) \
+ (BIT_CLEAR_SCH_DBG_VALUE_8814B(x) | BIT_SCH_DBG_VALUE_8814B(v))
+
+/* 2 REG_SCH_TXCMD_8814B */
+
+#define BIT_SHIFT_SCH_TXCMD_8814B 0
+#define BIT_MASK_SCH_TXCMD_8814B 0xffffffffL
+#define BIT_SCH_TXCMD_8814B(x) \
+ (((x) & BIT_MASK_SCH_TXCMD_8814B) << BIT_SHIFT_SCH_TXCMD_8814B)
+#define BITS_SCH_TXCMD_8814B \
+ (BIT_MASK_SCH_TXCMD_8814B << BIT_SHIFT_SCH_TXCMD_8814B)
+#define BIT_CLEAR_SCH_TXCMD_8814B(x) ((x) & (~BITS_SCH_TXCMD_8814B))
+#define BIT_GET_SCH_TXCMD_8814B(x) \
+ (((x) >> BIT_SHIFT_SCH_TXCMD_8814B) & BIT_MASK_SCH_TXCMD_8814B)
+#define BIT_SET_SCH_TXCMD_8814B(x, v) \
+ (BIT_CLEAR_SCH_TXCMD_8814B(x) | BIT_SCH_TXCMD_8814B(v))
+
+/* 2 REG_PAGE5_DUMMY_8814B */
+
+/* 2 REG_PORT_CTRL_SEL_8814B */
+
+#define BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1_8814B 4
+#define BIT_MASK_BCN_TIMER_SEL_FWRD_V1_8814B 0x7
+#define BIT_BCN_TIMER_SEL_FWRD_V1_8814B(x) \
+ (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_V1_8814B) \
+ << BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1_8814B)
+#define BITS_BCN_TIMER_SEL_FWRD_V1_8814B \
+ (BIT_MASK_BCN_TIMER_SEL_FWRD_V1_8814B \
+ << BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1_8814B)
+#define BIT_CLEAR_BCN_TIMER_SEL_FWRD_V1_8814B(x) \
+ ((x) & (~BITS_BCN_TIMER_SEL_FWRD_V1_8814B))
+#define BIT_GET_BCN_TIMER_SEL_FWRD_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_V1_8814B) & \
+ BIT_MASK_BCN_TIMER_SEL_FWRD_V1_8814B)
+#define BIT_SET_BCN_TIMER_SEL_FWRD_V1_8814B(x, v) \
+ (BIT_CLEAR_BCN_TIMER_SEL_FWRD_V1_8814B(x) | \
+ BIT_BCN_TIMER_SEL_FWRD_V1_8814B(v))
+
+#define BIT_SHIFT_PORT_CTRL_SEL_8814B 0
+#define BIT_MASK_PORT_CTRL_SEL_8814B 0x7
+#define BIT_PORT_CTRL_SEL_8814B(x) \
+ (((x) & BIT_MASK_PORT_CTRL_SEL_8814B) << BIT_SHIFT_PORT_CTRL_SEL_8814B)
+#define BITS_PORT_CTRL_SEL_8814B \
+ (BIT_MASK_PORT_CTRL_SEL_8814B << BIT_SHIFT_PORT_CTRL_SEL_8814B)
+#define BIT_CLEAR_PORT_CTRL_SEL_8814B(x) ((x) & (~BITS_PORT_CTRL_SEL_8814B))
+#define BIT_GET_PORT_CTRL_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_PORT_CTRL_SEL_8814B) & BIT_MASK_PORT_CTRL_SEL_8814B)
+#define BIT_SET_PORT_CTRL_SEL_8814B(x, v) \
+ (BIT_CLEAR_PORT_CTRL_SEL_8814B(x) | BIT_PORT_CTRL_SEL_8814B(v))
+
+/* 2 REG_PORT_CTRL_CFG_8814B */
+#define BIT_BCNERR_CNT_EN_V1_8814B BIT(11)
+#define BIT_DIS_TRX_CAL_BCN_V1_8814B BIT(10)
+#define BIT_DIS_TX_CAL_TBTT_V1_8814B BIT(9)
+#define BIT_BCN_AGGRESSION_V1_8814B BIT(8)
+#define BIT_TSFTR_RST_V1_8814B BIT(7)
+#define BIT_DIS_RX_BSSID_FIT_8814B BIT(6)
+#define BIT_EN_TXBCN_RPT_V1_8814B BIT(5)
+#define BIT_DIS_TSF_UDT_8814B BIT(4)
+#define BIT_EN_PORT_FUNCTION_8814B BIT(3)
+#define BIT_EN_RXBCN_RPT_8814B BIT(2)
+#define BIT_EN_P2P_CTWINDOW_8814B BIT(1)
+#define BIT_EN_P2P_BCNQ_AREA_8814B BIT(0)
+
+/* 2 REG_TBTT_PROHIBIT_CFG_8814B */
+#define BIT_MASK_PROHIBIT_8814B BIT(23)
+
+#define BIT_SHIFT_TBTT_HOLD_TIME_8814B 8
+#define BIT_MASK_TBTT_HOLD_TIME_8814B 0xfff
+#define BIT_TBTT_HOLD_TIME_8814B(x) \
+ (((x) & BIT_MASK_TBTT_HOLD_TIME_8814B) \
+ << BIT_SHIFT_TBTT_HOLD_TIME_8814B)
+#define BITS_TBTT_HOLD_TIME_8814B \
+ (BIT_MASK_TBTT_HOLD_TIME_8814B << BIT_SHIFT_TBTT_HOLD_TIME_8814B)
+#define BIT_CLEAR_TBTT_HOLD_TIME_8814B(x) ((x) & (~BITS_TBTT_HOLD_TIME_8814B))
+#define BIT_GET_TBTT_HOLD_TIME_8814B(x) \
+ (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_8814B) & \
+ BIT_MASK_TBTT_HOLD_TIME_8814B)
+#define BIT_SET_TBTT_HOLD_TIME_8814B(x, v) \
+ (BIT_CLEAR_TBTT_HOLD_TIME_8814B(x) | BIT_TBTT_HOLD_TIME_8814B(v))
+
+#define BIT_SHIFT_TBTT_PROHIBIT_SETUP_8814B 0
+#define BIT_MASK_TBTT_PROHIBIT_SETUP_8814B 0xf
+#define BIT_TBTT_PROHIBIT_SETUP_8814B(x) \
+ (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8814B) \
+ << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8814B)
+#define BITS_TBTT_PROHIBIT_SETUP_8814B \
+ (BIT_MASK_TBTT_PROHIBIT_SETUP_8814B \
+ << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8814B)
+#define BIT_CLEAR_TBTT_PROHIBIT_SETUP_8814B(x) \
+ ((x) & (~BITS_TBTT_PROHIBIT_SETUP_8814B))
+#define BIT_GET_TBTT_PROHIBIT_SETUP_8814B(x) \
+ (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8814B) & \
+ BIT_MASK_TBTT_PROHIBIT_SETUP_8814B)
+#define BIT_SET_TBTT_PROHIBIT_SETUP_8814B(x, v) \
+ (BIT_CLEAR_TBTT_PROHIBIT_SETUP_8814B(x) | \
+ BIT_TBTT_PROHIBIT_SETUP_8814B(v))
+
+/* 2 REG_DRVERLYINT_CFG_8814B */
+
+#define BIT_SHIFT_DRVERLYITV_8814B 0
+#define BIT_MASK_DRVERLYITV_8814B 0xff
+#define BIT_DRVERLYITV_8814B(x) \
+ (((x) & BIT_MASK_DRVERLYITV_8814B) << BIT_SHIFT_DRVERLYITV_8814B)
+#define BITS_DRVERLYITV_8814B \
+ (BIT_MASK_DRVERLYITV_8814B << BIT_SHIFT_DRVERLYITV_8814B)
+#define BIT_CLEAR_DRVERLYITV_8814B(x) ((x) & (~BITS_DRVERLYITV_8814B))
+#define BIT_GET_DRVERLYITV_8814B(x) \
+ (((x) >> BIT_SHIFT_DRVERLYITV_8814B) & BIT_MASK_DRVERLYITV_8814B)
+#define BIT_SET_DRVERLYITV_8814B(x, v) \
+ (BIT_CLEAR_DRVERLYITV_8814B(x) | BIT_DRVERLYITV_8814B(v))
+
+/* 2 REG_BCNDMATIM_CFG_8814B */
+
+#define BIT_SHIFT_BCNDMATIM_8814B 0
+#define BIT_MASK_BCNDMATIM_8814B 0xff
+#define BIT_BCNDMATIM_8814B(x) \
+ (((x) & BIT_MASK_BCNDMATIM_8814B) << BIT_SHIFT_BCNDMATIM_8814B)
+#define BITS_BCNDMATIM_8814B \
+ (BIT_MASK_BCNDMATIM_8814B << BIT_SHIFT_BCNDMATIM_8814B)
+#define BIT_CLEAR_BCNDMATIM_8814B(x) ((x) & (~BITS_BCNDMATIM_8814B))
+#define BIT_GET_BCNDMATIM_8814B(x) \
+ (((x) >> BIT_SHIFT_BCNDMATIM_8814B) & BIT_MASK_BCNDMATIM_8814B)
+#define BIT_SET_BCNDMATIM_8814B(x, v) \
+ (BIT_CLEAR_BCNDMATIM_8814B(x) | BIT_BCNDMATIM_8814B(v))
+
+/* 2 REG_CTWND_CFG_8814B */
+
+#define BIT_SHIFT_CTWND_8814B 0
+#define BIT_MASK_CTWND_8814B 0xff
+#define BIT_CTWND_8814B(x) \
+ (((x) & BIT_MASK_CTWND_8814B) << BIT_SHIFT_CTWND_8814B)
+#define BITS_CTWND_8814B (BIT_MASK_CTWND_8814B << BIT_SHIFT_CTWND_8814B)
+#define BIT_CLEAR_CTWND_8814B(x) ((x) & (~BITS_CTWND_8814B))
+#define BIT_GET_CTWND_8814B(x) \
+ (((x) >> BIT_SHIFT_CTWND_8814B) & BIT_MASK_CTWND_8814B)
+#define BIT_SET_CTWND_8814B(x, v) \
+ (BIT_CLEAR_CTWND_8814B(x) | BIT_CTWND_8814B(v))
+
+/* 2 REG_BCNIVLCUNT_CFG_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_BCNIVLCUNT_8814B 0
+#define BIT_MASK_BCNIVLCUNT_8814B 0x7f
+#define BIT_BCNIVLCUNT_8814B(x) \
+ (((x) & BIT_MASK_BCNIVLCUNT_8814B) << BIT_SHIFT_BCNIVLCUNT_8814B)
+#define BITS_BCNIVLCUNT_8814B \
+ (BIT_MASK_BCNIVLCUNT_8814B << BIT_SHIFT_BCNIVLCUNT_8814B)
+#define BIT_CLEAR_BCNIVLCUNT_8814B(x) ((x) & (~BITS_BCNIVLCUNT_8814B))
+#define BIT_GET_BCNIVLCUNT_8814B(x) \
+ (((x) >> BIT_SHIFT_BCNIVLCUNT_8814B) & BIT_MASK_BCNIVLCUNT_8814B)
+#define BIT_SET_BCNIVLCUNT_8814B(x, v) \
+ (BIT_CLEAR_BCNIVLCUNT_8814B(x) | BIT_BCNIVLCUNT_8814B(v))
+
+/* 2 REG_EARLY_128US_CFG_8814B */
+
+#define BIT_SHIFT_EARLY_128US_8814B 0
+#define BIT_MASK_EARLY_128US_8814B 0x7
+#define BIT_EARLY_128US_8814B(x) \
+ (((x) & BIT_MASK_EARLY_128US_8814B) << BIT_SHIFT_EARLY_128US_8814B)
+#define BITS_EARLY_128US_8814B \
+ (BIT_MASK_EARLY_128US_8814B << BIT_SHIFT_EARLY_128US_8814B)
+#define BIT_CLEAR_EARLY_128US_8814B(x) ((x) & (~BITS_EARLY_128US_8814B))
+#define BIT_GET_EARLY_128US_8814B(x) \
+ (((x) >> BIT_SHIFT_EARLY_128US_8814B) & BIT_MASK_EARLY_128US_8814B)
+#define BIT_SET_EARLY_128US_8814B(x, v) \
+ (BIT_CLEAR_EARLY_128US_8814B(x) | BIT_EARLY_128US_8814B(v))
+
+/* 2 REG_TSFTR_SYNC_OFFSET_CFG_8814B */
+
+#define BIT_SHIFT_TSFTR_SNC_OFFSET_V1_8814B 0
+#define BIT_MASK_TSFTR_SNC_OFFSET_V1_8814B 0xffffff
+#define BIT_TSFTR_SNC_OFFSET_V1_8814B(x) \
+ (((x) & BIT_MASK_TSFTR_SNC_OFFSET_V1_8814B) \
+ << BIT_SHIFT_TSFTR_SNC_OFFSET_V1_8814B)
+#define BITS_TSFTR_SNC_OFFSET_V1_8814B \
+ (BIT_MASK_TSFTR_SNC_OFFSET_V1_8814B \
+ << BIT_SHIFT_TSFTR_SNC_OFFSET_V1_8814B)
+#define BIT_CLEAR_TSFTR_SNC_OFFSET_V1_8814B(x) \
+ ((x) & (~BITS_TSFTR_SNC_OFFSET_V1_8814B))
+#define BIT_GET_TSFTR_SNC_OFFSET_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_V1_8814B) & \
+ BIT_MASK_TSFTR_SNC_OFFSET_V1_8814B)
+#define BIT_SET_TSFTR_SNC_OFFSET_V1_8814B(x, v) \
+ (BIT_CLEAR_TSFTR_SNC_OFFSET_V1_8814B(x) | \
+ BIT_TSFTR_SNC_OFFSET_V1_8814B(v))
+
+/* 2 REG_TSFTR_SYNC_CTRL_CFG_8814B */
+#define BIT_SYNC_TSF_NOW_V1_8814B BIT(5)
+#define BIT_SYNC_TSF_ONCE_8814B BIT(4)
+#define BIT_SYNC_TSF_AUTO_8814B BIT(3)
+
+#define BIT_SHIFT_SYNC_PORT_SEL_8814B 0
+#define BIT_MASK_SYNC_PORT_SEL_8814B 0x7
+#define BIT_SYNC_PORT_SEL_8814B(x) \
+ (((x) & BIT_MASK_SYNC_PORT_SEL_8814B) << BIT_SHIFT_SYNC_PORT_SEL_8814B)
+#define BITS_SYNC_PORT_SEL_8814B \
+ (BIT_MASK_SYNC_PORT_SEL_8814B << BIT_SHIFT_SYNC_PORT_SEL_8814B)
+#define BIT_CLEAR_SYNC_PORT_SEL_8814B(x) ((x) & (~BITS_SYNC_PORT_SEL_8814B))
+#define BIT_GET_SYNC_PORT_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_SYNC_PORT_SEL_8814B) & BIT_MASK_SYNC_PORT_SEL_8814B)
+#define BIT_SET_SYNC_PORT_SEL_8814B(x, v) \
+ (BIT_CLEAR_SYNC_PORT_SEL_8814B(x) | BIT_SYNC_PORT_SEL_8814B(v))
+
+/* 2 REG_BCN_SPACE_CFG_8814B */
+
+#define BIT_SHIFT_BCN_SPACE_8814B 0
+#define BIT_MASK_BCN_SPACE_8814B 0xffff
+#define BIT_BCN_SPACE_8814B(x) \
+ (((x) & BIT_MASK_BCN_SPACE_8814B) << BIT_SHIFT_BCN_SPACE_8814B)
+#define BITS_BCN_SPACE_8814B \
+ (BIT_MASK_BCN_SPACE_8814B << BIT_SHIFT_BCN_SPACE_8814B)
+#define BIT_CLEAR_BCN_SPACE_8814B(x) ((x) & (~BITS_BCN_SPACE_8814B))
+#define BIT_GET_BCN_SPACE_8814B(x) \
+ (((x) >> BIT_SHIFT_BCN_SPACE_8814B) & BIT_MASK_BCN_SPACE_8814B)
+#define BIT_SET_BCN_SPACE_8814B(x, v) \
+ (BIT_CLEAR_BCN_SPACE_8814B(x) | BIT_BCN_SPACE_8814B(v))
+
+/* 2 REG_EARLY_INT_ADJUST_CFG_8814B */
+
+#define BIT_SHIFT_EARLY_INT_ADJUST_8814B 0
+#define BIT_MASK_EARLY_INT_ADJUST_8814B 0xffff
+#define BIT_EARLY_INT_ADJUST_8814B(x) \
+ (((x) & BIT_MASK_EARLY_INT_ADJUST_8814B) \
+ << BIT_SHIFT_EARLY_INT_ADJUST_8814B)
+#define BITS_EARLY_INT_ADJUST_8814B \
+ (BIT_MASK_EARLY_INT_ADJUST_8814B << BIT_SHIFT_EARLY_INT_ADJUST_8814B)
+#define BIT_CLEAR_EARLY_INT_ADJUST_8814B(x) \
+ ((x) & (~BITS_EARLY_INT_ADJUST_8814B))
+#define BIT_GET_EARLY_INT_ADJUST_8814B(x) \
+ (((x) >> BIT_SHIFT_EARLY_INT_ADJUST_8814B) & \
+ BIT_MASK_EARLY_INT_ADJUST_8814B)
+#define BIT_SET_EARLY_INT_ADJUST_8814B(x, v) \
+ (BIT_CLEAR_EARLY_INT_ADJUST_8814B(x) | BIT_EARLY_INT_ADJUST_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_SW_TBTT_TSF_INFO_8814B */
+
+#define BIT_SHIFT_SW_TBTT_TSF_INFO_8814B 0
+#define BIT_MASK_SW_TBTT_TSF_INFO_8814B 0xffffffffL
+#define BIT_SW_TBTT_TSF_INFO_8814B(x) \
+ (((x) & BIT_MASK_SW_TBTT_TSF_INFO_8814B) \
+ << BIT_SHIFT_SW_TBTT_TSF_INFO_8814B)
+#define BITS_SW_TBTT_TSF_INFO_8814B \
+ (BIT_MASK_SW_TBTT_TSF_INFO_8814B << BIT_SHIFT_SW_TBTT_TSF_INFO_8814B)
+#define BIT_CLEAR_SW_TBTT_TSF_INFO_8814B(x) \
+ ((x) & (~BITS_SW_TBTT_TSF_INFO_8814B))
+#define BIT_GET_SW_TBTT_TSF_INFO_8814B(x) \
+ (((x) >> BIT_SHIFT_SW_TBTT_TSF_INFO_8814B) & \
+ BIT_MASK_SW_TBTT_TSF_INFO_8814B)
+#define BIT_SET_SW_TBTT_TSF_INFO_8814B(x, v) \
+ (BIT_CLEAR_SW_TBTT_TSF_INFO_8814B(x) | BIT_SW_TBTT_TSF_INFO_8814B(v))
+
+/* 2 REG_TSFTR_LOW_8814B */
+
+#define BIT_SHIFT_TSF_TIMER_LOW_8814B 0
+#define BIT_MASK_TSF_TIMER_LOW_8814B 0xffffffffL
+#define BIT_TSF_TIMER_LOW_8814B(x) \
+ (((x) & BIT_MASK_TSF_TIMER_LOW_8814B) << BIT_SHIFT_TSF_TIMER_LOW_8814B)
+#define BITS_TSF_TIMER_LOW_8814B \
+ (BIT_MASK_TSF_TIMER_LOW_8814B << BIT_SHIFT_TSF_TIMER_LOW_8814B)
+#define BIT_CLEAR_TSF_TIMER_LOW_8814B(x) ((x) & (~BITS_TSF_TIMER_LOW_8814B))
+#define BIT_GET_TSF_TIMER_LOW_8814B(x) \
+ (((x) >> BIT_SHIFT_TSF_TIMER_LOW_8814B) & BIT_MASK_TSF_TIMER_LOW_8814B)
+#define BIT_SET_TSF_TIMER_LOW_8814B(x, v) \
+ (BIT_CLEAR_TSF_TIMER_LOW_8814B(x) | BIT_TSF_TIMER_LOW_8814B(v))
+
+/* 2 REG_TSFTR_HIGH_8814B */
+
+#define BIT_SHIFT_TSF_TIMER_HIGH_8814B 0
+#define BIT_MASK_TSF_TIMER_HIGH_8814B 0xffffffffL
+#define BIT_TSF_TIMER_HIGH_8814B(x) \
+ (((x) & BIT_MASK_TSF_TIMER_HIGH_8814B) \
+ << BIT_SHIFT_TSF_TIMER_HIGH_8814B)
+#define BITS_TSF_TIMER_HIGH_8814B \
+ (BIT_MASK_TSF_TIMER_HIGH_8814B << BIT_SHIFT_TSF_TIMER_HIGH_8814B)
+#define BIT_CLEAR_TSF_TIMER_HIGH_8814B(x) ((x) & (~BITS_TSF_TIMER_HIGH_8814B))
+#define BIT_GET_TSF_TIMER_HIGH_8814B(x) \
+ (((x) >> BIT_SHIFT_TSF_TIMER_HIGH_8814B) & \
+ BIT_MASK_TSF_TIMER_HIGH_8814B)
+#define BIT_SET_TSF_TIMER_HIGH_8814B(x, v) \
+ (BIT_CLEAR_TSF_TIMER_HIGH_8814B(x) | BIT_TSF_TIMER_HIGH_8814B(v))
+
+/* 2 REG_BCN_ERR_CNT_MAC_8814B */
+
+#define BIT_SHIFT_BCN_ERR_CNT_MAC_8814B 0
+#define BIT_MASK_BCN_ERR_CNT_MAC_8814B 0xff
+#define BIT_BCN_ERR_CNT_MAC_8814B(x) \
+ (((x) & BIT_MASK_BCN_ERR_CNT_MAC_8814B) \
+ << BIT_SHIFT_BCN_ERR_CNT_MAC_8814B)
+#define BITS_BCN_ERR_CNT_MAC_8814B \
+ (BIT_MASK_BCN_ERR_CNT_MAC_8814B << BIT_SHIFT_BCN_ERR_CNT_MAC_8814B)
+#define BIT_CLEAR_BCN_ERR_CNT_MAC_8814B(x) ((x) & (~BITS_BCN_ERR_CNT_MAC_8814B))
+#define BIT_GET_BCN_ERR_CNT_MAC_8814B(x) \
+ (((x) >> BIT_SHIFT_BCN_ERR_CNT_MAC_8814B) & \
+ BIT_MASK_BCN_ERR_CNT_MAC_8814B)
+#define BIT_SET_BCN_ERR_CNT_MAC_8814B(x, v) \
+ (BIT_CLEAR_BCN_ERR_CNT_MAC_8814B(x) | BIT_BCN_ERR_CNT_MAC_8814B(v))
+
+/* 2 REG_BCN_ERR_CNT_EDCCA_8814B */
+
+#define BIT_SHIFT_BCN_ERR_CNT_EDCCA_8814B 0
+#define BIT_MASK_BCN_ERR_CNT_EDCCA_8814B 0xff
+#define BIT_BCN_ERR_CNT_EDCCA_8814B(x) \
+ (((x) & BIT_MASK_BCN_ERR_CNT_EDCCA_8814B) \
+ << BIT_SHIFT_BCN_ERR_CNT_EDCCA_8814B)
+#define BITS_BCN_ERR_CNT_EDCCA_8814B \
+ (BIT_MASK_BCN_ERR_CNT_EDCCA_8814B << BIT_SHIFT_BCN_ERR_CNT_EDCCA_8814B)
+#define BIT_CLEAR_BCN_ERR_CNT_EDCCA_8814B(x) \
+ ((x) & (~BITS_BCN_ERR_CNT_EDCCA_8814B))
+#define BIT_GET_BCN_ERR_CNT_EDCCA_8814B(x) \
+ (((x) >> BIT_SHIFT_BCN_ERR_CNT_EDCCA_8814B) & \
+ BIT_MASK_BCN_ERR_CNT_EDCCA_8814B)
+#define BIT_SET_BCN_ERR_CNT_EDCCA_8814B(x, v) \
+ (BIT_CLEAR_BCN_ERR_CNT_EDCCA_8814B(x) | BIT_BCN_ERR_CNT_EDCCA_8814B(v))
+
+/* 2 REG_BCN_ERR_CNT_CCA_8814B */
+
+#define BIT_SHIFT_BCN_ERR_CNT_CCA_8814B 0
+#define BIT_MASK_BCN_ERR_CNT_CCA_8814B 0xff
+#define BIT_BCN_ERR_CNT_CCA_8814B(x) \
+ (((x) & BIT_MASK_BCN_ERR_CNT_CCA_8814B) \
+ << BIT_SHIFT_BCN_ERR_CNT_CCA_8814B)
+#define BITS_BCN_ERR_CNT_CCA_8814B \
+ (BIT_MASK_BCN_ERR_CNT_CCA_8814B << BIT_SHIFT_BCN_ERR_CNT_CCA_8814B)
+#define BIT_CLEAR_BCN_ERR_CNT_CCA_8814B(x) ((x) & (~BITS_BCN_ERR_CNT_CCA_8814B))
+#define BIT_GET_BCN_ERR_CNT_CCA_8814B(x) \
+ (((x) >> BIT_SHIFT_BCN_ERR_CNT_CCA_8814B) & \
+ BIT_MASK_BCN_ERR_CNT_CCA_8814B)
+#define BIT_SET_BCN_ERR_CNT_CCA_8814B(x, v) \
+ (BIT_CLEAR_BCN_ERR_CNT_CCA_8814B(x) | BIT_BCN_ERR_CNT_CCA_8814B(v))
+
+/* 2 REG_BCN_ERR_CNT_INVALID_8814B */
+
+#define BIT_SHIFT_BCN_ERR_CNT_INVALID_8814B 0
+#define BIT_MASK_BCN_ERR_CNT_INVALID_8814B 0xff
+#define BIT_BCN_ERR_CNT_INVALID_8814B(x) \
+ (((x) & BIT_MASK_BCN_ERR_CNT_INVALID_8814B) \
+ << BIT_SHIFT_BCN_ERR_CNT_INVALID_8814B)
+#define BITS_BCN_ERR_CNT_INVALID_8814B \
+ (BIT_MASK_BCN_ERR_CNT_INVALID_8814B \
+ << BIT_SHIFT_BCN_ERR_CNT_INVALID_8814B)
+#define BIT_CLEAR_BCN_ERR_CNT_INVALID_8814B(x) \
+ ((x) & (~BITS_BCN_ERR_CNT_INVALID_8814B))
+#define BIT_GET_BCN_ERR_CNT_INVALID_8814B(x) \
+ (((x) >> BIT_SHIFT_BCN_ERR_CNT_INVALID_8814B) & \
+ BIT_MASK_BCN_ERR_CNT_INVALID_8814B)
+#define BIT_SET_BCN_ERR_CNT_INVALID_8814B(x, v) \
+ (BIT_CLEAR_BCN_ERR_CNT_INVALID_8814B(x) | \
+ BIT_BCN_ERR_CNT_INVALID_8814B(v))
+
+/* 2 REG_BCN_ERR_CNT_OTHERS_8814B */
+
+#define BIT_SHIFT_BCN_ERR_CNT_OTHERS_8814B 0
+#define BIT_MASK_BCN_ERR_CNT_OTHERS_8814B 0xff
+#define BIT_BCN_ERR_CNT_OTHERS_8814B(x) \
+ (((x) & BIT_MASK_BCN_ERR_CNT_OTHERS_8814B) \
+ << BIT_SHIFT_BCN_ERR_CNT_OTHERS_8814B)
+#define BITS_BCN_ERR_CNT_OTHERS_8814B \
+ (BIT_MASK_BCN_ERR_CNT_OTHERS_8814B \
+ << BIT_SHIFT_BCN_ERR_CNT_OTHERS_8814B)
+#define BIT_CLEAR_BCN_ERR_CNT_OTHERS_8814B(x) \
+ ((x) & (~BITS_BCN_ERR_CNT_OTHERS_8814B))
+#define BIT_GET_BCN_ERR_CNT_OTHERS_8814B(x) \
+ (((x) >> BIT_SHIFT_BCN_ERR_CNT_OTHERS_8814B) & \
+ BIT_MASK_BCN_ERR_CNT_OTHERS_8814B)
+#define BIT_SET_BCN_ERR_CNT_OTHERS_8814B(x, v) \
+ (BIT_CLEAR_BCN_ERR_CNT_OTHERS_8814B(x) | \
+ BIT_BCN_ERR_CNT_OTHERS_8814B(v))
+
+/* 2 REG_RX_BCN_TIMER_8814B */
+
+#define BIT_SHIFT_RX_BCN_TIMER_8814B 0
+#define BIT_MASK_RX_BCN_TIMER_8814B 0xffff
+#define BIT_RX_BCN_TIMER_8814B(x) \
+ (((x) & BIT_MASK_RX_BCN_TIMER_8814B) << BIT_SHIFT_RX_BCN_TIMER_8814B)
+#define BITS_RX_BCN_TIMER_8814B \
+ (BIT_MASK_RX_BCN_TIMER_8814B << BIT_SHIFT_RX_BCN_TIMER_8814B)
+#define BIT_CLEAR_RX_BCN_TIMER_8814B(x) ((x) & (~BITS_RX_BCN_TIMER_8814B))
+#define BIT_GET_RX_BCN_TIMER_8814B(x) \
+ (((x) >> BIT_SHIFT_RX_BCN_TIMER_8814B) & BIT_MASK_RX_BCN_TIMER_8814B)
+#define BIT_SET_RX_BCN_TIMER_8814B(x, v) \
+ (BIT_CLEAR_RX_BCN_TIMER_8814B(x) | BIT_RX_BCN_TIMER_8814B(v))
+
+/* 2 REG_TBTT_CTN_AREA_V1_8814B */
+
+#define BIT_SHIFT_TBTT_CTN_AREA_8814B 0
+#define BIT_MASK_TBTT_CTN_AREA_8814B 0xff
+#define BIT_TBTT_CTN_AREA_8814B(x) \
+ (((x) & BIT_MASK_TBTT_CTN_AREA_8814B) << BIT_SHIFT_TBTT_CTN_AREA_8814B)
+#define BITS_TBTT_CTN_AREA_8814B \
+ (BIT_MASK_TBTT_CTN_AREA_8814B << BIT_SHIFT_TBTT_CTN_AREA_8814B)
+#define BIT_CLEAR_TBTT_CTN_AREA_8814B(x) ((x) & (~BITS_TBTT_CTN_AREA_8814B))
+#define BIT_GET_TBTT_CTN_AREA_8814B(x) \
+ (((x) >> BIT_SHIFT_TBTT_CTN_AREA_8814B) & BIT_MASK_TBTT_CTN_AREA_8814B)
+#define BIT_SET_TBTT_CTN_AREA_8814B(x, v) \
+ (BIT_CLEAR_TBTT_CTN_AREA_8814B(x) | BIT_TBTT_CTN_AREA_8814B(v))
+
+/* 2 REG_BCN_MAX_ERR_V1_8814B */
+
+#define BIT_SHIFT_BCN_MAX_ERR_8814B 0
+#define BIT_MASK_BCN_MAX_ERR_8814B 0xff
+#define BIT_BCN_MAX_ERR_8814B(x) \
+ (((x) & BIT_MASK_BCN_MAX_ERR_8814B) << BIT_SHIFT_BCN_MAX_ERR_8814B)
+#define BITS_BCN_MAX_ERR_8814B \
+ (BIT_MASK_BCN_MAX_ERR_8814B << BIT_SHIFT_BCN_MAX_ERR_8814B)
+#define BIT_CLEAR_BCN_MAX_ERR_8814B(x) ((x) & (~BITS_BCN_MAX_ERR_8814B))
+#define BIT_GET_BCN_MAX_ERR_8814B(x) \
+ (((x) >> BIT_SHIFT_BCN_MAX_ERR_8814B) & BIT_MASK_BCN_MAX_ERR_8814B)
+#define BIT_SET_BCN_MAX_ERR_8814B(x, v) \
+ (BIT_CLEAR_BCN_MAX_ERR_8814B(x) | BIT_BCN_MAX_ERR_8814B(v))
+
+/* 2 REG_RXTSF_OFFSET_CCK_V1_8814B */
+
+#define BIT_SHIFT_CCK_RXTSF_OFFSET_8814B 0
+#define BIT_MASK_CCK_RXTSF_OFFSET_8814B 0xff
+#define BIT_CCK_RXTSF_OFFSET_8814B(x) \
+ (((x) & BIT_MASK_CCK_RXTSF_OFFSET_8814B) \
+ << BIT_SHIFT_CCK_RXTSF_OFFSET_8814B)
+#define BITS_CCK_RXTSF_OFFSET_8814B \
+ (BIT_MASK_CCK_RXTSF_OFFSET_8814B << BIT_SHIFT_CCK_RXTSF_OFFSET_8814B)
+#define BIT_CLEAR_CCK_RXTSF_OFFSET_8814B(x) \
+ ((x) & (~BITS_CCK_RXTSF_OFFSET_8814B))
+#define BIT_GET_CCK_RXTSF_OFFSET_8814B(x) \
+ (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8814B) & \
+ BIT_MASK_CCK_RXTSF_OFFSET_8814B)
+#define BIT_SET_CCK_RXTSF_OFFSET_8814B(x, v) \
+ (BIT_CLEAR_CCK_RXTSF_OFFSET_8814B(x) | BIT_CCK_RXTSF_OFFSET_8814B(v))
+
+/* 2 REG_RXTSF_OFFSET_OFDM_V1_8814B */
+
+#define BIT_SHIFT_OFDM_RXTSF_OFFSET_8814B 0
+#define BIT_MASK_OFDM_RXTSF_OFFSET_8814B 0xff
+#define BIT_OFDM_RXTSF_OFFSET_8814B(x) \
+ (((x) & BIT_MASK_OFDM_RXTSF_OFFSET_8814B) \
+ << BIT_SHIFT_OFDM_RXTSF_OFFSET_8814B)
+#define BITS_OFDM_RXTSF_OFFSET_8814B \
+ (BIT_MASK_OFDM_RXTSF_OFFSET_8814B << BIT_SHIFT_OFDM_RXTSF_OFFSET_8814B)
+#define BIT_CLEAR_OFDM_RXTSF_OFFSET_8814B(x) \
+ ((x) & (~BITS_OFDM_RXTSF_OFFSET_8814B))
+#define BIT_GET_OFDM_RXTSF_OFFSET_8814B(x) \
+ (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8814B) & \
+ BIT_MASK_OFDM_RXTSF_OFFSET_8814B)
+#define BIT_SET_OFDM_RXTSF_OFFSET_8814B(x, v) \
+ (BIT_CLEAR_OFDM_RXTSF_OFFSET_8814B(x) | BIT_OFDM_RXTSF_OFFSET_8814B(v))
+
+/* 2 REG_SUB_BCN_SPACE_8814B */
+
+#define BIT_SHIFT_SUB_BCN_SPACE_V2_8814B 0
+#define BIT_MASK_SUB_BCN_SPACE_V2_8814B 0xff
+#define BIT_SUB_BCN_SPACE_V2_8814B(x) \
+ (((x) & BIT_MASK_SUB_BCN_SPACE_V2_8814B) \
+ << BIT_SHIFT_SUB_BCN_SPACE_V2_8814B)
+#define BITS_SUB_BCN_SPACE_V2_8814B \
+ (BIT_MASK_SUB_BCN_SPACE_V2_8814B << BIT_SHIFT_SUB_BCN_SPACE_V2_8814B)
+#define BIT_CLEAR_SUB_BCN_SPACE_V2_8814B(x) \
+ ((x) & (~BITS_SUB_BCN_SPACE_V2_8814B))
+#define BIT_GET_SUB_BCN_SPACE_V2_8814B(x) \
+ (((x) >> BIT_SHIFT_SUB_BCN_SPACE_V2_8814B) & \
+ BIT_MASK_SUB_BCN_SPACE_V2_8814B)
+#define BIT_SET_SUB_BCN_SPACE_V2_8814B(x, v) \
+ (BIT_CLEAR_SUB_BCN_SPACE_V2_8814B(x) | BIT_SUB_BCN_SPACE_V2_8814B(v))
+
+/* 2 REG_MBID_NUM_V1_8814B */
+
+#define BIT_SHIFT_BCN_ERR_PORT_SEL_8814B 4
+#define BIT_MASK_BCN_ERR_PORT_SEL_8814B 0xf
+#define BIT_BCN_ERR_PORT_SEL_8814B(x) \
+ (((x) & BIT_MASK_BCN_ERR_PORT_SEL_8814B) \
+ << BIT_SHIFT_BCN_ERR_PORT_SEL_8814B)
+#define BITS_BCN_ERR_PORT_SEL_8814B \
+ (BIT_MASK_BCN_ERR_PORT_SEL_8814B << BIT_SHIFT_BCN_ERR_PORT_SEL_8814B)
+#define BIT_CLEAR_BCN_ERR_PORT_SEL_8814B(x) \
+ ((x) & (~BITS_BCN_ERR_PORT_SEL_8814B))
+#define BIT_GET_BCN_ERR_PORT_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_BCN_ERR_PORT_SEL_8814B) & \
+ BIT_MASK_BCN_ERR_PORT_SEL_8814B)
+#define BIT_SET_BCN_ERR_PORT_SEL_8814B(x, v) \
+ (BIT_CLEAR_BCN_ERR_PORT_SEL_8814B(x) | BIT_BCN_ERR_PORT_SEL_8814B(v))
+
+#define BIT_SHIFT_MBID_BCN_NUM_V1_8814B 0
+#define BIT_MASK_MBID_BCN_NUM_V1_8814B 0xf
+#define BIT_MBID_BCN_NUM_V1_8814B(x) \
+ (((x) & BIT_MASK_MBID_BCN_NUM_V1_8814B) \
+ << BIT_SHIFT_MBID_BCN_NUM_V1_8814B)
+#define BITS_MBID_BCN_NUM_V1_8814B \
+ (BIT_MASK_MBID_BCN_NUM_V1_8814B << BIT_SHIFT_MBID_BCN_NUM_V1_8814B)
+#define BIT_CLEAR_MBID_BCN_NUM_V1_8814B(x) ((x) & (~BITS_MBID_BCN_NUM_V1_8814B))
+#define BIT_GET_MBID_BCN_NUM_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_MBID_BCN_NUM_V1_8814B) & \
+ BIT_MASK_MBID_BCN_NUM_V1_8814B)
+#define BIT_SET_MBID_BCN_NUM_V1_8814B(x, v) \
+ (BIT_CLEAR_MBID_BCN_NUM_V1_8814B(x) | BIT_MBID_BCN_NUM_V1_8814B(v))
+
+/* 2 REG_MBSSID_CTRL_V1_8814B */
+#define BIT_MBID_BCNQ15_EN_8814B BIT(15)
+#define BIT_MBID_BCNQ14_EN_8814B BIT(14)
+#define BIT_MBID_BCNQ13_EN_8814B BIT(13)
+#define BIT_MBID_BCNQ12_EN_8814B BIT(12)
+#define BIT_MBID_BCNQ11_EN_8814B BIT(11)
+#define BIT_MBID_BCNQ10_EN_8814B BIT(10)
+#define BIT_MBID_BCNQ9_EN_8814B BIT(9)
+#define BIT_MBID_BCNQ8_EN_8814B BIT(8)
+#define BIT_MBID_BCNQ7_EN_8814B BIT(7)
+#define BIT_MBID_BCNQ6_EN_8814B BIT(6)
+#define BIT_MBID_BCNQ5_EN_8814B BIT(5)
+#define BIT_MBID_BCNQ4_EN_8814B BIT(4)
+#define BIT_MBID_BCNQ3_EN_8814B BIT(3)
+#define BIT_MBID_BCNQ2_EN_8814B BIT(2)
+#define BIT_MBID_BCNQ1_EN_8814B BIT(1)
+#define BIT_MBID_BCNQ0_EN_8814B BIT(0)
+
+/* 2 REG_USTIME_TSF_V1_8814B */
+
+#define BIT_SHIFT_USTIME_TSF_V1_8814B 0
+#define BIT_MASK_USTIME_TSF_V1_8814B 0xff
+#define BIT_USTIME_TSF_V1_8814B(x) \
+ (((x) & BIT_MASK_USTIME_TSF_V1_8814B) << BIT_SHIFT_USTIME_TSF_V1_8814B)
+#define BITS_USTIME_TSF_V1_8814B \
+ (BIT_MASK_USTIME_TSF_V1_8814B << BIT_SHIFT_USTIME_TSF_V1_8814B)
+#define BIT_CLEAR_USTIME_TSF_V1_8814B(x) ((x) & (~BITS_USTIME_TSF_V1_8814B))
+#define BIT_GET_USTIME_TSF_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_USTIME_TSF_V1_8814B) & BIT_MASK_USTIME_TSF_V1_8814B)
+#define BIT_SET_USTIME_TSF_V1_8814B(x, v) \
+ (BIT_CLEAR_USTIME_TSF_V1_8814B(x) | BIT_USTIME_TSF_V1_8814B(v))
+
+/* 2 REG_BW_CFG_8814B */
+#define BIT_SLEEP_32K_EN_8814B BIT(3)
+#define BIT_DIS_MARK_TSF_US_V1_8814B BIT(2)
+
+#define BIT_SHIFT_BW_CFG_8814B 0
+#define BIT_MASK_BW_CFG_8814B 0x3
+#define BIT_BW_CFG_8814B(x) \
+ (((x) & BIT_MASK_BW_CFG_8814B) << BIT_SHIFT_BW_CFG_8814B)
+#define BITS_BW_CFG_8814B (BIT_MASK_BW_CFG_8814B << BIT_SHIFT_BW_CFG_8814B)
+#define BIT_CLEAR_BW_CFG_8814B(x) ((x) & (~BITS_BW_CFG_8814B))
+#define BIT_GET_BW_CFG_8814B(x) \
+ (((x) >> BIT_SHIFT_BW_CFG_8814B) & BIT_MASK_BW_CFG_8814B)
+#define BIT_SET_BW_CFG_8814B(x, v) \
+ (BIT_CLEAR_BW_CFG_8814B(x) | BIT_BW_CFG_8814B(v))
+
+/* 2 REG_ATIMWND_CFG_8814B */
+
+#define BIT_SHIFT_ATIMWND_V1_8814B 0
+#define BIT_MASK_ATIMWND_V1_8814B 0xff
+#define BIT_ATIMWND_V1_8814B(x) \
+ (((x) & BIT_MASK_ATIMWND_V1_8814B) << BIT_SHIFT_ATIMWND_V1_8814B)
+#define BITS_ATIMWND_V1_8814B \
+ (BIT_MASK_ATIMWND_V1_8814B << BIT_SHIFT_ATIMWND_V1_8814B)
+#define BIT_CLEAR_ATIMWND_V1_8814B(x) ((x) & (~BITS_ATIMWND_V1_8814B))
+#define BIT_GET_ATIMWND_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_ATIMWND_V1_8814B) & BIT_MASK_ATIMWND_V1_8814B)
+#define BIT_SET_ATIMWND_V1_8814B(x, v) \
+ (BIT_CLEAR_ATIMWND_V1_8814B(x) | BIT_ATIMWND_V1_8814B(v))
+
+/* 2 REG_DTIM_COUNTER_CFG_8814B */
+
+#define BIT_SHIFT_DTIM_COUNT_8814B 0
+#define BIT_MASK_DTIM_COUNT_8814B 0xff
+#define BIT_DTIM_COUNT_8814B(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_8814B) << BIT_SHIFT_DTIM_COUNT_8814B)
+#define BITS_DTIM_COUNT_8814B \
+ (BIT_MASK_DTIM_COUNT_8814B << BIT_SHIFT_DTIM_COUNT_8814B)
+#define BIT_CLEAR_DTIM_COUNT_8814B(x) ((x) & (~BITS_DTIM_COUNT_8814B))
+#define BIT_GET_DTIM_COUNT_8814B(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_8814B) & BIT_MASK_DTIM_COUNT_8814B)
+#define BIT_SET_DTIM_COUNT_8814B(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_8814B(x) | BIT_DTIM_COUNT_8814B(v))
+
+/* 2 REG_ATIM_DTIM_CTRL_SEL_8814B */
+#define BIT_DTIM_BYPASS_V1_8814B BIT(7)
+
+#define BIT_SHIFT_ATIM_DTIM_SEL_8814B 0
+#define BIT_MASK_ATIM_DTIM_SEL_8814B 0x1f
+#define BIT_ATIM_DTIM_SEL_8814B(x) \
+ (((x) & BIT_MASK_ATIM_DTIM_SEL_8814B) << BIT_SHIFT_ATIM_DTIM_SEL_8814B)
+#define BITS_ATIM_DTIM_SEL_8814B \
+ (BIT_MASK_ATIM_DTIM_SEL_8814B << BIT_SHIFT_ATIM_DTIM_SEL_8814B)
+#define BIT_CLEAR_ATIM_DTIM_SEL_8814B(x) ((x) & (~BITS_ATIM_DTIM_SEL_8814B))
+#define BIT_GET_ATIM_DTIM_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_ATIM_DTIM_SEL_8814B) & BIT_MASK_ATIM_DTIM_SEL_8814B)
+#define BIT_SET_ATIM_DTIM_SEL_8814B(x, v) \
+ (BIT_CLEAR_ATIM_DTIM_SEL_8814B(x) | BIT_ATIM_DTIM_SEL_8814B(v))
+
+/* 2 REG_ATIMUGT_V1_8814B */
+
+#define BIT_SHIFT_ATIM_URGENT_8814B 0
+#define BIT_MASK_ATIM_URGENT_8814B 0xff
+#define BIT_ATIM_URGENT_8814B(x) \
+ (((x) & BIT_MASK_ATIM_URGENT_8814B) << BIT_SHIFT_ATIM_URGENT_8814B)
+#define BITS_ATIM_URGENT_8814B \
+ (BIT_MASK_ATIM_URGENT_8814B << BIT_SHIFT_ATIM_URGENT_8814B)
+#define BIT_CLEAR_ATIM_URGENT_8814B(x) ((x) & (~BITS_ATIM_URGENT_8814B))
+#define BIT_GET_ATIM_URGENT_8814B(x) \
+ (((x) >> BIT_SHIFT_ATIM_URGENT_8814B) & BIT_MASK_ATIM_URGENT_8814B)
+#define BIT_SET_ATIM_URGENT_8814B(x, v) \
+ (BIT_CLEAR_ATIM_URGENT_8814B(x) | BIT_ATIM_URGENT_8814B(v))
+
+/* 2 REG_BCNDROPCTRL_V1_8814B */
+#define BIT_BEACON_DROP_EN_8814B BIT(7)
+
+#define BIT_SHIFT_BEACON_DROP_IVL_8814B 0
+#define BIT_MASK_BEACON_DROP_IVL_8814B 0x7f
+#define BIT_BEACON_DROP_IVL_8814B(x) \
+ (((x) & BIT_MASK_BEACON_DROP_IVL_8814B) \
+ << BIT_SHIFT_BEACON_DROP_IVL_8814B)
+#define BITS_BEACON_DROP_IVL_8814B \
+ (BIT_MASK_BEACON_DROP_IVL_8814B << BIT_SHIFT_BEACON_DROP_IVL_8814B)
+#define BIT_CLEAR_BEACON_DROP_IVL_8814B(x) ((x) & (~BITS_BEACON_DROP_IVL_8814B))
+#define BIT_GET_BEACON_DROP_IVL_8814B(x) \
+ (((x) >> BIT_SHIFT_BEACON_DROP_IVL_8814B) & \
+ BIT_MASK_BEACON_DROP_IVL_8814B)
+#define BIT_SET_BEACON_DROP_IVL_8814B(x, v) \
+ (BIT_CLEAR_BEACON_DROP_IVL_8814B(x) | BIT_BEACON_DROP_IVL_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_DIS_ATIM_V1_8814B */
+#define BIT_DIS_ATIM_P4_8814B BIT(19)
+#define BIT_DIS_ATIM_P3_8814B BIT(18)
+#define BIT_DIS_ATIM_P2_8814B BIT(17)
+#define BIT_DIS_ATIM_P1_8814B BIT(16)
+#define BIT_DIS_ATIM_VAP15_8814B BIT(15)
+#define BIT_DIS_ATIM_VAP14_8814B BIT(14)
+#define BIT_DIS_ATIM_VAP13_8814B BIT(13)
+#define BIT_DIS_ATIM_VAP12_8814B BIT(12)
+#define BIT_DIS_ATIM_VAP11_8814B BIT(11)
+#define BIT_DIS_ATIM_VAP10_8814B BIT(10)
+#define BIT_DIS_ATIM_VAP9_8814B BIT(9)
+#define BIT_DIS_ATIM_VAP8_8814B BIT(8)
+#define BIT_DIS_ATIM_VAP7_8814B BIT(7)
+#define BIT_DIS_ATIM_VAP6_8814B BIT(6)
+#define BIT_DIS_ATIM_VAP5_8814B BIT(5)
+#define BIT_DIS_ATIM_VAP4_8814B BIT(4)
+#define BIT_DIS_ATIM_VAP3_8814B BIT(3)
+#define BIT_DIS_ATIM_VAP2_8814B BIT(2)
+#define BIT_DIS_ATIM_VAP1_8814B BIT(1)
+#define BIT_DIS_ATIM_ROOT_P0_8814B BIT(0)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_HIQ_NO_LMT_EN_V1_8814B */
+#define BIT_HIQ_NO_LMT_EN_P4_8814B BIT(19)
+#define BIT_HIQ_NO_LMT_EN_P3_8814B BIT(18)
+#define BIT_HIQ_NO_LMT_EN_P2_8814B BIT(17)
+#define BIT_HIQ_NO_LMT_EN_P1_8814B BIT(16)
+#define BIT_HIQ_NO_LMT_EN_VAP15_8814B BIT(15)
+#define BIT_HIQ_NO_LMT_EN_VAP14_8814B BIT(14)
+#define BIT_HIQ_NO_LMT_EN_VAP13_8814B BIT(13)
+#define BIT_HIQ_NO_LMT_EN_VAP12_8814B BIT(12)
+#define BIT_HIQ_NO_LMT_EN_VAP11_8814B BIT(11)
+#define BIT_HIQ_NO_LMT_EN_VAP10_8814B BIT(10)
+#define BIT_HIQ_NO_LMT_EN_VAP9_8814B BIT(9)
+#define BIT_HIQ_NO_LMT_EN_VAP8_8814B BIT(8)
+#define BIT_HIQ_NO_LMT_EN_VAP7_8814B BIT(7)
+#define BIT_HIQ_NO_LMT_EN_VAP6_8814B BIT(6)
+#define BIT_HIQ_NO_LMT_EN_VAP5_8814B BIT(5)
+#define BIT_HIQ_NO_LMT_EN_VAP4_8814B BIT(4)
+#define BIT_HIQ_NO_LMT_EN_VAP3_8814B BIT(3)
+#define BIT_HIQ_NO_LMT_EN_VAP2_8814B BIT(2)
+#define BIT_HIQ_NO_LMT_EN_VAP1_8814B BIT(1)
+#define BIT_HIQ_NO_LMT_EN_ROOT_P0_8814B BIT(0)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_P2PPS_CTRL_V1_8814B */
+#define BIT_P2P_PWR_RST1_V2_8814B BIT(15)
+#define BIT_P2P_PWR_RST0_V2_8814B BIT(14)
+#define BIT_EN_TSFBIT32_RST_P2P_V1_8814B BIT(13)
+
+#define BIT_SHIFT_NOA_UNIT0_SEL_V1_8814B 8
+#define BIT_MASK_NOA_UNIT0_SEL_V1_8814B 0x7
+#define BIT_NOA_UNIT0_SEL_V1_8814B(x) \
+ (((x) & BIT_MASK_NOA_UNIT0_SEL_V1_8814B) \
+ << BIT_SHIFT_NOA_UNIT0_SEL_V1_8814B)
+#define BITS_NOA_UNIT0_SEL_V1_8814B \
+ (BIT_MASK_NOA_UNIT0_SEL_V1_8814B << BIT_SHIFT_NOA_UNIT0_SEL_V1_8814B)
+#define BIT_CLEAR_NOA_UNIT0_SEL_V1_8814B(x) \
+ ((x) & (~BITS_NOA_UNIT0_SEL_V1_8814B))
+#define BIT_GET_NOA_UNIT0_SEL_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_NOA_UNIT0_SEL_V1_8814B) & \
+ BIT_MASK_NOA_UNIT0_SEL_V1_8814B)
+#define BIT_SET_NOA_UNIT0_SEL_V1_8814B(x, v) \
+ (BIT_CLEAR_NOA_UNIT0_SEL_V1_8814B(x) | BIT_NOA_UNIT0_SEL_V1_8814B(v))
+
+#define BIT_P2P_CTW_ALLSTASLEEP_V1_8814B BIT(7)
+#define BIT_P2P_OFF_DISTX_EN_V1_8814B BIT(6)
+#define BIT_PWR_MGT_EN_V1_8814B BIT(5)
+#define BIT_P2P_NOA1_EN_V1_8814B BIT(2)
+#define BIT_P2P_NOA0_EN_V1_8814B BIT(1)
+
+/* 2 REG_P2PPS_SPEC_STATE_V1_8814B */
+#define BIT_SPEC_POWER_STATE_8814B BIT(7)
+#define BIT_SPEC_CTWINDOW_ON_8814B BIT(6)
+#define BIT_SPEC_BEACON_AREA_ON_8814B BIT(5)
+#define BIT_SPEC_CTWIN_EARLY_DISTX_8814B BIT(4)
+#define BIT_SPEC_NOA1_OFF_PERIOD_8814B BIT(3)
+#define BIT_SPEC_FORCE_DOZE1_8814B BIT(2)
+#define BIT_SPEC_NOA0_OFF_PERIOD_8814B BIT(1)
+#define BIT_SPEC_FORCE_DOZE0_8814B BIT(0)
+
+/* 2 REG_P2PPS_STATE_V1_8814B */
+#define BIT_POWER_STATE_8814B BIT(7)
+#define BIT_CTWINDOW_ON_8814B BIT(6)
+#define BIT_BEACON_AREA_ON_8814B BIT(5)
+#define BIT_CTWIN_EARLY_DISTX_8814B BIT(4)
+#define BIT_NOA1_OFF_PERIOD_8814B BIT(3)
+#define BIT_FORCE_DOZE1_8814B BIT(2)
+#define BIT_NOA0_OFF_PERIOD_8814B BIT(1)
+#define BIT_FORCE_DOZE0_8814B BIT(0)
+
+/* 2 REG_P2PPS1_CTRL_V1_8814B */
+#define BIT_P2P1_PWR_RST1_V2_8814B BIT(15)
+#define BIT_P2P1_PWR_RST0_V2_8814B BIT(14)
+#define BIT_EN_TSFBIT32_RST_P2P1_V1_8814B BIT(13)
+
+#define BIT_SHIFT_NOA_UNIT1_SEL_V1_8814B 8
+#define BIT_MASK_NOA_UNIT1_SEL_V1_8814B 0x7
+#define BIT_NOA_UNIT1_SEL_V1_8814B(x) \
+ (((x) & BIT_MASK_NOA_UNIT1_SEL_V1_8814B) \
+ << BIT_SHIFT_NOA_UNIT1_SEL_V1_8814B)
+#define BITS_NOA_UNIT1_SEL_V1_8814B \
+ (BIT_MASK_NOA_UNIT1_SEL_V1_8814B << BIT_SHIFT_NOA_UNIT1_SEL_V1_8814B)
+#define BIT_CLEAR_NOA_UNIT1_SEL_V1_8814B(x) \
+ ((x) & (~BITS_NOA_UNIT1_SEL_V1_8814B))
+#define BIT_GET_NOA_UNIT1_SEL_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_NOA_UNIT1_SEL_V1_8814B) & \
+ BIT_MASK_NOA_UNIT1_SEL_V1_8814B)
+#define BIT_SET_NOA_UNIT1_SEL_V1_8814B(x, v) \
+ (BIT_CLEAR_NOA_UNIT1_SEL_V1_8814B(x) | BIT_NOA_UNIT1_SEL_V1_8814B(v))
+
+#define BIT_P2P1_CTW_ALLSTASLEEP_V1_8814B BIT(7)
+#define BIT_P2P1_OFF_DISTX_EN_8814B BIT(6)
+#define BIT_P2P1_PWR_MGT_EN_V1_8814B BIT(5)
+#define BIT_P2P1_NOA1_EN_V1_8814B BIT(2)
+#define BIT_P2P1_NOA0_EN_V1_8814B BIT(1)
+
+/* 2 REG_P2PPS1_SPEC_STATE_V1_8814B */
+#define BIT_P2P1_SPEC_POWER_STATEP_8814B BIT(7)
+#define BIT_P2P1_SPEC_CTWINDOW_ON_8814B BIT(6)
+#define BIT_P2P1_SPEC_BEACON_AREA_ON_8814B BIT(5)
+#define BIT_P2P1_SPEC_CTWIN_EARLY_DISTX_8814B BIT(4)
+#define BIT_P2P1_SPEC_NOA1_OFF_PERIOD_8814B BIT(3)
+#define BIT_P2P1_SPEC_FORCE_DOZE1_8814B BIT(2)
+#define BIT_P2P1_SPEC_NOA0_OFF_PERIOD_8814B BIT(1)
+#define BIT_P2P1_SPEC_FORCE_DOZE0_8814B BIT(0)
+
+/* 2 REG_P2PPS1_STATE_V1_8814B */
+#define BIT_P2P1_POWER_STATE_8814B BIT(7)
+#define BIT_P2P1_CTWINDOW_ON_8814B BIT(6)
+#define BIT_P2P1_BEACON_AREA_ON_8814B BIT(5)
+#define BIT_P2P1_CTWIN_EARLY_DISTX_8814B BIT(4)
+#define BIT_P2P1_NOA1_OFF_PERIOD_8814B BIT(3)
+#define BIT_P2P1_FORCE_DOZE1_8814B BIT(2)
+#define BIT_P2P1_NOA0_OFF_PERIOD_8814B BIT(1)
+#define BIT_P2P1_FORCE_DOZE0_8814B BIT(0)
+
+/* 2 REG_P2PPS2_CTRL_V1_8814B */
+#define BIT_P2P2_PWR_RST1_V2_8814B BIT(15)
+#define BIT_P2P2_PWR_RST0_V2_8814B BIT(14)
+#define BIT_EN_TSFBIT32_RST_P2P2_V1_8814B BIT(13)
+
+#define BIT_SHIFT_NOA_UNIT2_SEL_V1_8814B 8
+#define BIT_MASK_NOA_UNIT2_SEL_V1_8814B 0x7
+#define BIT_NOA_UNIT2_SEL_V1_8814B(x) \
+ (((x) & BIT_MASK_NOA_UNIT2_SEL_V1_8814B) \
+ << BIT_SHIFT_NOA_UNIT2_SEL_V1_8814B)
+#define BITS_NOA_UNIT2_SEL_V1_8814B \
+ (BIT_MASK_NOA_UNIT2_SEL_V1_8814B << BIT_SHIFT_NOA_UNIT2_SEL_V1_8814B)
+#define BIT_CLEAR_NOA_UNIT2_SEL_V1_8814B(x) \
+ ((x) & (~BITS_NOA_UNIT2_SEL_V1_8814B))
+#define BIT_GET_NOA_UNIT2_SEL_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_NOA_UNIT2_SEL_V1_8814B) & \
+ BIT_MASK_NOA_UNIT2_SEL_V1_8814B)
+#define BIT_SET_NOA_UNIT2_SEL_V1_8814B(x, v) \
+ (BIT_CLEAR_NOA_UNIT2_SEL_V1_8814B(x) | BIT_NOA_UNIT2_SEL_V1_8814B(v))
+
+#define BIT_P2P2_CTW_ALLSTASLEEP_V1_8814B BIT(7)
+#define BIT_P2P2_OFF_DISTX_EN_V1_8814B BIT(6)
+#define BIT_P2P2_PWR_MGT_EN_V1_8814B BIT(5)
+#define BIT_P2P2_NOA1_EN_V1_8814B BIT(2)
+#define BIT_P2P2_NOA0_EN_V1_8814B BIT(1)
+
+/* 2 REG_P2PPS2_SPEC_STATE_V1_8814B */
+#define BIT_P2P2_SPEC_POWER_STATEP_8814B BIT(7)
+#define BIT_P2P2_SPEC_CTWINDOW_ON_8814B BIT(6)
+#define BIT_P2P2_SPEC_BEACON_AREA_ON_8814B BIT(5)
+#define BIT_P2P2_SPEC_CTWIN_EARLY_DISTX_8814B BIT(4)
+#define BIT_P2P2_SPEC_NOA1_OFF_PERIOD_8814B BIT(3)
+#define BIT_P2P2_SPEC_FORCE_DOZE1_8814B BIT(2)
+#define BIT_P2P2_SPEC_NOA0_OFF_PERIOD_8814B BIT(1)
+#define BIT_P2P2_SPEC_FORCE_DOZE0_8814B BIT(0)
+
+/* 2 REG_P2PPS2_STATE_V1_8814B */
+#define BIT_P2P2_POWER_STATE_8814B BIT(7)
+#define BIT_P2P2_CTWINDOW_ON_8814B BIT(6)
+#define BIT_P2P2_BEACON_AREA_ON_8814B BIT(5)
+#define BIT_P2P2_CTWIN_EARLY_DISTX_8814B BIT(4)
+#define BIT_P2P2_NOA1_OFF_PERIOD_8814B BIT(3)
+#define BIT_P2P2_FORCE_DOZE1_8814B BIT(2)
+#define BIT_P2P2_NOA0_OFF_PERIOD_8814B BIT(1)
+#define BIT_P2P2_FORCE_DOZE0_8814B BIT(0)
+
+/* 2 REG_P2PON_DIS_TXTIME_V1_8814B */
+
+#define BIT_SHIFT_P2PON_DIS_TXTIME_8814B 0
+#define BIT_MASK_P2PON_DIS_TXTIME_8814B 0xff
+#define BIT_P2PON_DIS_TXTIME_8814B(x) \
+ (((x) & BIT_MASK_P2PON_DIS_TXTIME_8814B) \
+ << BIT_SHIFT_P2PON_DIS_TXTIME_8814B)
+#define BITS_P2PON_DIS_TXTIME_8814B \
+ (BIT_MASK_P2PON_DIS_TXTIME_8814B << BIT_SHIFT_P2PON_DIS_TXTIME_8814B)
+#define BIT_CLEAR_P2PON_DIS_TXTIME_8814B(x) \
+ ((x) & (~BITS_P2PON_DIS_TXTIME_8814B))
+#define BIT_GET_P2PON_DIS_TXTIME_8814B(x) \
+ (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8814B) & \
+ BIT_MASK_P2PON_DIS_TXTIME_8814B)
+#define BIT_SET_P2PON_DIS_TXTIME_8814B(x, v) \
+ (BIT_CLEAR_P2PON_DIS_TXTIME_8814B(x) | BIT_P2PON_DIS_TXTIME_8814B(v))
+
+/* 2 REG_P2POFF_DIS_TXTIME_V1_8814B */
+
+#define BIT_SHIFT_P2POFF_DIS_TXTIME_8814B 0
+#define BIT_MASK_P2POFF_DIS_TXTIME_8814B 0xff
+#define BIT_P2POFF_DIS_TXTIME_8814B(x) \
+ (((x) & BIT_MASK_P2POFF_DIS_TXTIME_8814B) \
+ << BIT_SHIFT_P2POFF_DIS_TXTIME_8814B)
+#define BITS_P2POFF_DIS_TXTIME_8814B \
+ (BIT_MASK_P2POFF_DIS_TXTIME_8814B << BIT_SHIFT_P2POFF_DIS_TXTIME_8814B)
+#define BIT_CLEAR_P2POFF_DIS_TXTIME_8814B(x) \
+ ((x) & (~BITS_P2POFF_DIS_TXTIME_8814B))
+#define BIT_GET_P2POFF_DIS_TXTIME_8814B(x) \
+ (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8814B) & \
+ BIT_MASK_P2POFF_DIS_TXTIME_8814B)
+#define BIT_SET_P2POFF_DIS_TXTIME_8814B(x, v) \
+ (BIT_CLEAR_P2POFF_DIS_TXTIME_8814B(x) | BIT_P2POFF_DIS_TXTIME_8814B(v))
+
+/* 2 REG_CHG_POWER_BCN_AREA_8814B */
+#define BIT_CHG_POWER_BCN_AREA_8814B BIT(0)
+
+/* 2 REG_NOA_SEL_8814B */
+
+#define BIT_SHIFT_NOA_SEL_V1_8814B 0
+#define BIT_MASK_NOA_SEL_V1_8814B 0x7
+#define BIT_NOA_SEL_V1_8814B(x) \
+ (((x) & BIT_MASK_NOA_SEL_V1_8814B) << BIT_SHIFT_NOA_SEL_V1_8814B)
+#define BITS_NOA_SEL_V1_8814B \
+ (BIT_MASK_NOA_SEL_V1_8814B << BIT_SHIFT_NOA_SEL_V1_8814B)
+#define BIT_CLEAR_NOA_SEL_V1_8814B(x) ((x) & (~BITS_NOA_SEL_V1_8814B))
+#define BIT_GET_NOA_SEL_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_NOA_SEL_V1_8814B) & BIT_MASK_NOA_SEL_V1_8814B)
+#define BIT_SET_NOA_SEL_V1_8814B(x, v) \
+ (BIT_CLEAR_NOA_SEL_V1_8814B(x) | BIT_NOA_SEL_V1_8814B(v))
+
+/* 2 REG_NOA_PARAM_V1_8814B */
+
+#define BIT_SHIFT_NOA_DURATION_8814B 0
+#define BIT_MASK_NOA_DURATION_8814B 0xffffffffL
+#define BIT_NOA_DURATION_8814B(x) \
+ (((x) & BIT_MASK_NOA_DURATION_8814B) << BIT_SHIFT_NOA_DURATION_8814B)
+#define BITS_NOA_DURATION_8814B \
+ (BIT_MASK_NOA_DURATION_8814B << BIT_SHIFT_NOA_DURATION_8814B)
+#define BIT_CLEAR_NOA_DURATION_8814B(x) ((x) & (~BITS_NOA_DURATION_8814B))
+#define BIT_GET_NOA_DURATION_8814B(x) \
+ (((x) >> BIT_SHIFT_NOA_DURATION_8814B) & BIT_MASK_NOA_DURATION_8814B)
+#define BIT_SET_NOA_DURATION_8814B(x, v) \
+ (BIT_CLEAR_NOA_DURATION_8814B(x) | BIT_NOA_DURATION_8814B(v))
+
+/* 2 REG_NOA_PARAM_1_V1_8814B */
+
+#define BIT_SHIFT_NOA_INTERVAL_8814B 0
+#define BIT_MASK_NOA_INTERVAL_8814B 0xffffffffL
+#define BIT_NOA_INTERVAL_8814B(x) \
+ (((x) & BIT_MASK_NOA_INTERVAL_8814B) << BIT_SHIFT_NOA_INTERVAL_8814B)
+#define BITS_NOA_INTERVAL_8814B \
+ (BIT_MASK_NOA_INTERVAL_8814B << BIT_SHIFT_NOA_INTERVAL_8814B)
+#define BIT_CLEAR_NOA_INTERVAL_8814B(x) ((x) & (~BITS_NOA_INTERVAL_8814B))
+#define BIT_GET_NOA_INTERVAL_8814B(x) \
+ (((x) >> BIT_SHIFT_NOA_INTERVAL_8814B) & BIT_MASK_NOA_INTERVAL_8814B)
+#define BIT_SET_NOA_INTERVAL_8814B(x, v) \
+ (BIT_CLEAR_NOA_INTERVAL_8814B(x) | BIT_NOA_INTERVAL_8814B(v))
+
+/* 2 REG_NOA_PARAM_2_V1_8814B */
+
+#define BIT_SHIFT_NOA_START_TIME_8814B 0
+#define BIT_MASK_NOA_START_TIME_8814B 0xffffffffL
+#define BIT_NOA_START_TIME_8814B(x) \
+ (((x) & BIT_MASK_NOA_START_TIME_8814B) \
+ << BIT_SHIFT_NOA_START_TIME_8814B)
+#define BITS_NOA_START_TIME_8814B \
+ (BIT_MASK_NOA_START_TIME_8814B << BIT_SHIFT_NOA_START_TIME_8814B)
+#define BIT_CLEAR_NOA_START_TIME_8814B(x) ((x) & (~BITS_NOA_START_TIME_8814B))
+#define BIT_GET_NOA_START_TIME_8814B(x) \
+ (((x) >> BIT_SHIFT_NOA_START_TIME_8814B) & \
+ BIT_MASK_NOA_START_TIME_8814B)
+#define BIT_SET_NOA_START_TIME_8814B(x, v) \
+ (BIT_CLEAR_NOA_START_TIME_8814B(x) | BIT_NOA_START_TIME_8814B(v))
+
+/* 2 REG_NOA_PARAM_3_V1_8814B */
+
+#define BIT_SHIFT_NOA_COUNT_V2_8814B 0
+#define BIT_MASK_NOA_COUNT_V2_8814B 0xffffffffL
+#define BIT_NOA_COUNT_V2_8814B(x) \
+ (((x) & BIT_MASK_NOA_COUNT_V2_8814B) << BIT_SHIFT_NOA_COUNT_V2_8814B)
+#define BITS_NOA_COUNT_V2_8814B \
+ (BIT_MASK_NOA_COUNT_V2_8814B << BIT_SHIFT_NOA_COUNT_V2_8814B)
+#define BIT_CLEAR_NOA_COUNT_V2_8814B(x) ((x) & (~BITS_NOA_COUNT_V2_8814B))
+#define BIT_GET_NOA_COUNT_V2_8814B(x) \
+ (((x) >> BIT_SHIFT_NOA_COUNT_V2_8814B) & BIT_MASK_NOA_COUNT_V2_8814B)
+#define BIT_SET_NOA_COUNT_V2_8814B(x, v) \
+ (BIT_CLEAR_NOA_COUNT_V2_8814B(x) | BIT_NOA_COUNT_V2_8814B(v))
+
+/* 2 REG_NOA_ON_ERLY_TIME_V1_8814B */
+
+#define BIT_SHIFT__NOA_ON_ERLY_TIME_8814B 0
+#define BIT_MASK__NOA_ON_ERLY_TIME_8814B 0xff
+#define BIT__NOA_ON_ERLY_TIME_8814B(x) \
+ (((x) & BIT_MASK__NOA_ON_ERLY_TIME_8814B) \
+ << BIT_SHIFT__NOA_ON_ERLY_TIME_8814B)
+#define BITS__NOA_ON_ERLY_TIME_8814B \
+ (BIT_MASK__NOA_ON_ERLY_TIME_8814B << BIT_SHIFT__NOA_ON_ERLY_TIME_8814B)
+#define BIT_CLEAR__NOA_ON_ERLY_TIME_8814B(x) \
+ ((x) & (~BITS__NOA_ON_ERLY_TIME_8814B))
+#define BIT_GET__NOA_ON_ERLY_TIME_8814B(x) \
+ (((x) >> BIT_SHIFT__NOA_ON_ERLY_TIME_8814B) & \
+ BIT_MASK__NOA_ON_ERLY_TIME_8814B)
+#define BIT_SET__NOA_ON_ERLY_TIME_8814B(x, v) \
+ (BIT_CLEAR__NOA_ON_ERLY_TIME_8814B(x) | BIT__NOA_ON_ERLY_TIME_8814B(v))
+
+/* 2 REG_NOA_OFF_ERLY_TIME_V1_8814B */
+
+#define BIT_SHIFT__NOA_OFF_ERLY_TIME_8814B 0
+#define BIT_MASK__NOA_OFF_ERLY_TIME_8814B 0xff
+#define BIT__NOA_OFF_ERLY_TIME_8814B(x) \
+ (((x) & BIT_MASK__NOA_OFF_ERLY_TIME_8814B) \
+ << BIT_SHIFT__NOA_OFF_ERLY_TIME_8814B)
+#define BITS__NOA_OFF_ERLY_TIME_8814B \
+ (BIT_MASK__NOA_OFF_ERLY_TIME_8814B \
+ << BIT_SHIFT__NOA_OFF_ERLY_TIME_8814B)
+#define BIT_CLEAR__NOA_OFF_ERLY_TIME_8814B(x) \
+ ((x) & (~BITS__NOA_OFF_ERLY_TIME_8814B))
+#define BIT_GET__NOA_OFF_ERLY_TIME_8814B(x) \
+ (((x) >> BIT_SHIFT__NOA_OFF_ERLY_TIME_8814B) & \
+ BIT_MASK__NOA_OFF_ERLY_TIME_8814B)
+#define BIT_SET__NOA_OFF_ERLY_TIME_8814B(x, v) \
+ (BIT_CLEAR__NOA_OFF_ERLY_TIME_8814B(x) | \
+ BIT__NOA_OFF_ERLY_TIME_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_P2PPS_HW_AUTO_PAUSE_CTRL_8814B */
+#define BIT_P2PPS_NOA_STOP_TX_HANG_8814B BIT(31)
+#define BIT_P2PPS_MACID_PAUSE_EN_8814B BIT(11)
+#define BIT_P2PPS__MGQ_PAUSE_8814B BIT(10)
+#define BIT_P2PPS__HIQ_PAUSE_8814B BIT(9)
+#define BIT_P2PPS__BCNQ_PAUSE_8814B BIT(8)
+
+#define BIT_SHIFT_P2PPS_MACID_PAUSE_8814B 0
+#define BIT_MASK_P2PPS_MACID_PAUSE_8814B 0xff
+#define BIT_P2PPS_MACID_PAUSE_8814B(x) \
+ (((x) & BIT_MASK_P2PPS_MACID_PAUSE_8814B) \
+ << BIT_SHIFT_P2PPS_MACID_PAUSE_8814B)
+#define BITS_P2PPS_MACID_PAUSE_8814B \
+ (BIT_MASK_P2PPS_MACID_PAUSE_8814B << BIT_SHIFT_P2PPS_MACID_PAUSE_8814B)
+#define BIT_CLEAR_P2PPS_MACID_PAUSE_8814B(x) \
+ ((x) & (~BITS_P2PPS_MACID_PAUSE_8814B))
+#define BIT_GET_P2PPS_MACID_PAUSE_8814B(x) \
+ (((x) >> BIT_SHIFT_P2PPS_MACID_PAUSE_8814B) & \
+ BIT_MASK_P2PPS_MACID_PAUSE_8814B)
+#define BIT_SET_P2PPS_MACID_PAUSE_8814B(x, v) \
+ (BIT_CLEAR_P2PPS_MACID_PAUSE_8814B(x) | BIT_P2PPS_MACID_PAUSE_8814B(v))
+
+/* 2 REG_P2PPS1_HW_AUTO_PAUSE_CTRL_8814B */
+#define BIT_P2PPS1_NOA_STOP_TX_HANG_8814B BIT(31)
+#define BIT_P2PPS1_MACID_PAUSE_EN_8814B BIT(11)
+#define BIT_P2PPS1__MGQ_PAUSE_8814B BIT(10)
+#define BIT_P2PPS1__HIQ_PAUSE_8814B BIT(9)
+#define BIT_P2PPS1__BCNQ_PAUSE_8814B BIT(8)
+
+#define BIT_SHIFT_P2PPS1_MACID_PAUSE_8814B 0
+#define BIT_MASK_P2PPS1_MACID_PAUSE_8814B 0xff
+#define BIT_P2PPS1_MACID_PAUSE_8814B(x) \
+ (((x) & BIT_MASK_P2PPS1_MACID_PAUSE_8814B) \
+ << BIT_SHIFT_P2PPS1_MACID_PAUSE_8814B)
+#define BITS_P2PPS1_MACID_PAUSE_8814B \
+ (BIT_MASK_P2PPS1_MACID_PAUSE_8814B \
+ << BIT_SHIFT_P2PPS1_MACID_PAUSE_8814B)
+#define BIT_CLEAR_P2PPS1_MACID_PAUSE_8814B(x) \
+ ((x) & (~BITS_P2PPS1_MACID_PAUSE_8814B))
+#define BIT_GET_P2PPS1_MACID_PAUSE_8814B(x) \
+ (((x) >> BIT_SHIFT_P2PPS1_MACID_PAUSE_8814B) & \
+ BIT_MASK_P2PPS1_MACID_PAUSE_8814B)
+#define BIT_SET_P2PPS1_MACID_PAUSE_8814B(x, v) \
+ (BIT_CLEAR_P2PPS1_MACID_PAUSE_8814B(x) | \
+ BIT_P2PPS1_MACID_PAUSE_8814B(v))
+
+/* 2 REG_P2PPS2_HW_AUTO_PAUSE_CTRL_8814B */
+#define BIT_P2PPS2_NOA_STOP_TX_HANG_8814B BIT(31)
+#define BIT_P2PPS2_MACID_PAUSE_EN_8814B BIT(11)
+#define BIT_P2PPS2__MGQ_PAUSE_8814B BIT(10)
+#define BIT_P2PPS2__HIQ_PAUSE_8814B BIT(9)
+#define BIT_P2PPS2__BCNQ_PAUSE_8814B BIT(8)
+
+#define BIT_SHIFT_P2PPS2_MACID_PAUSE_8814B 0
+#define BIT_MASK_P2PPS2_MACID_PAUSE_8814B 0xff
+#define BIT_P2PPS2_MACID_PAUSE_8814B(x) \
+ (((x) & BIT_MASK_P2PPS2_MACID_PAUSE_8814B) \
+ << BIT_SHIFT_P2PPS2_MACID_PAUSE_8814B)
+#define BITS_P2PPS2_MACID_PAUSE_8814B \
+ (BIT_MASK_P2PPS2_MACID_PAUSE_8814B \
+ << BIT_SHIFT_P2PPS2_MACID_PAUSE_8814B)
+#define BIT_CLEAR_P2PPS2_MACID_PAUSE_8814B(x) \
+ ((x) & (~BITS_P2PPS2_MACID_PAUSE_8814B))
+#define BIT_GET_P2PPS2_MACID_PAUSE_8814B(x) \
+ (((x) >> BIT_SHIFT_P2PPS2_MACID_PAUSE_8814B) & \
+ BIT_MASK_P2PPS2_MACID_PAUSE_8814B)
+#define BIT_SET_P2PPS2_MACID_PAUSE_8814B(x, v) \
+ (BIT_CLEAR_P2PPS2_MACID_PAUSE_8814B(x) | \
+ BIT_P2PPS2_MACID_PAUSE_8814B(v))
+
+/* 2 REG_RX_TBTT_SHIFT_8814B */
+
+#define BIT_SHIFT_RX_TBTT_SHIFT_SEL_8814B 24
+#define BIT_MASK_RX_TBTT_SHIFT_SEL_8814B 0x7
+#define BIT_RX_TBTT_SHIFT_SEL_8814B(x) \
+ (((x) & BIT_MASK_RX_TBTT_SHIFT_SEL_8814B) \
+ << BIT_SHIFT_RX_TBTT_SHIFT_SEL_8814B)
+#define BITS_RX_TBTT_SHIFT_SEL_8814B \
+ (BIT_MASK_RX_TBTT_SHIFT_SEL_8814B << BIT_SHIFT_RX_TBTT_SHIFT_SEL_8814B)
+#define BIT_CLEAR_RX_TBTT_SHIFT_SEL_8814B(x) \
+ ((x) & (~BITS_RX_TBTT_SHIFT_SEL_8814B))
+#define BIT_GET_RX_TBTT_SHIFT_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_RX_TBTT_SHIFT_SEL_8814B) & \
+ BIT_MASK_RX_TBTT_SHIFT_SEL_8814B)
+#define BIT_SET_RX_TBTT_SHIFT_SEL_8814B(x, v) \
+ (BIT_CLEAR_RX_TBTT_SHIFT_SEL_8814B(x) | BIT_RX_TBTT_SHIFT_SEL_8814B(v))
+
+#define BIT_RX_TBTT_SHIFT_RW_FLAG_8814B BIT(15)
+
+#define BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_8814B 0
+#define BIT_MASK_RX_TBTT_SHIFT_OFFSET_8814B 0xfff
+#define BIT_RX_TBTT_SHIFT_OFFSET_8814B(x) \
+ (((x) & BIT_MASK_RX_TBTT_SHIFT_OFFSET_8814B) \
+ << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_8814B)
+#define BITS_RX_TBTT_SHIFT_OFFSET_8814B \
+ (BIT_MASK_RX_TBTT_SHIFT_OFFSET_8814B \
+ << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_8814B)
+#define BIT_CLEAR_RX_TBTT_SHIFT_OFFSET_8814B(x) \
+ ((x) & (~BITS_RX_TBTT_SHIFT_OFFSET_8814B))
+#define BIT_GET_RX_TBTT_SHIFT_OFFSET_8814B(x) \
+ (((x) >> BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_8814B) & \
+ BIT_MASK_RX_TBTT_SHIFT_OFFSET_8814B)
+#define BIT_SET_RX_TBTT_SHIFT_OFFSET_8814B(x, v) \
+ (BIT_CLEAR_RX_TBTT_SHIFT_OFFSET_8814B(x) | \
+ BIT_RX_TBTT_SHIFT_OFFSET_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_FREERUN_CNT_LOW_8814B */
+
+#define BIT_SHIFT_FREERUN_CNT_LOW_8814B 0
+#define BIT_MASK_FREERUN_CNT_LOW_8814B 0xffffffffL
+#define BIT_FREERUN_CNT_LOW_8814B(x) \
+ (((x) & BIT_MASK_FREERUN_CNT_LOW_8814B) \
+ << BIT_SHIFT_FREERUN_CNT_LOW_8814B)
+#define BITS_FREERUN_CNT_LOW_8814B \
+ (BIT_MASK_FREERUN_CNT_LOW_8814B << BIT_SHIFT_FREERUN_CNT_LOW_8814B)
+#define BIT_CLEAR_FREERUN_CNT_LOW_8814B(x) ((x) & (~BITS_FREERUN_CNT_LOW_8814B))
+#define BIT_GET_FREERUN_CNT_LOW_8814B(x) \
+ (((x) >> BIT_SHIFT_FREERUN_CNT_LOW_8814B) & \
+ BIT_MASK_FREERUN_CNT_LOW_8814B)
+#define BIT_SET_FREERUN_CNT_LOW_8814B(x, v) \
+ (BIT_CLEAR_FREERUN_CNT_LOW_8814B(x) | BIT_FREERUN_CNT_LOW_8814B(v))
+
+/* 2 REG_FREERUN_CNT_HIGH_8814B */
+
+#define BIT_SHIFT_FREERUN_CNT_HIGH_8814B 0
+#define BIT_MASK_FREERUN_CNT_HIGH_8814B 0xffffffffL
+#define BIT_FREERUN_CNT_HIGH_8814B(x) \
+ (((x) & BIT_MASK_FREERUN_CNT_HIGH_8814B) \
+ << BIT_SHIFT_FREERUN_CNT_HIGH_8814B)
+#define BITS_FREERUN_CNT_HIGH_8814B \
+ (BIT_MASK_FREERUN_CNT_HIGH_8814B << BIT_SHIFT_FREERUN_CNT_HIGH_8814B)
+#define BIT_CLEAR_FREERUN_CNT_HIGH_8814B(x) \
+ ((x) & (~BITS_FREERUN_CNT_HIGH_8814B))
+#define BIT_GET_FREERUN_CNT_HIGH_8814B(x) \
+ (((x) >> BIT_SHIFT_FREERUN_CNT_HIGH_8814B) & \
+ BIT_MASK_FREERUN_CNT_HIGH_8814B)
+#define BIT_SET_FREERUN_CNT_HIGH_8814B(x, v) \
+ (BIT_CLEAR_FREERUN_CNT_HIGH_8814B(x) | BIT_FREERUN_CNT_HIGH_8814B(v))
+
+/* 2 REG_CPUMGQ_TX_TIMER_V1_8814B */
+
+#define BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8814B 0
+#define BIT_MASK_CPUMGQ_TX_TIMER_V1_8814B 0xffffffffL
+#define BIT_CPUMGQ_TX_TIMER_V1_8814B(x) \
+ (((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8814B) \
+ << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8814B)
+#define BITS_CPUMGQ_TX_TIMER_V1_8814B \
+ (BIT_MASK_CPUMGQ_TX_TIMER_V1_8814B \
+ << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8814B)
+#define BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8814B(x) \
+ ((x) & (~BITS_CPUMGQ_TX_TIMER_V1_8814B))
+#define BIT_GET_CPUMGQ_TX_TIMER_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8814B) & \
+ BIT_MASK_CPUMGQ_TX_TIMER_V1_8814B)
+#define BIT_SET_CPUMGQ_TX_TIMER_V1_8814B(x, v) \
+ (BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8814B(x) | \
+ BIT_CPUMGQ_TX_TIMER_V1_8814B(v))
+
+/* 2 REG_PS_TIMER_0_8814B */
+
+#define BIT_SHIFT_PS_TIMER_0_8814B 0
+#define BIT_MASK_PS_TIMER_0_8814B 0xffffffffL
+#define BIT_PS_TIMER_0_8814B(x) \
+ (((x) & BIT_MASK_PS_TIMER_0_8814B) << BIT_SHIFT_PS_TIMER_0_8814B)
+#define BITS_PS_TIMER_0_8814B \
+ (BIT_MASK_PS_TIMER_0_8814B << BIT_SHIFT_PS_TIMER_0_8814B)
+#define BIT_CLEAR_PS_TIMER_0_8814B(x) ((x) & (~BITS_PS_TIMER_0_8814B))
+#define BIT_GET_PS_TIMER_0_8814B(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_0_8814B) & BIT_MASK_PS_TIMER_0_8814B)
+#define BIT_SET_PS_TIMER_0_8814B(x, v) \
+ (BIT_CLEAR_PS_TIMER_0_8814B(x) | BIT_PS_TIMER_0_8814B(v))
+
+/* 2 REG_PS_TIMER_1_8814B */
+
+#define BIT_SHIFT_PS_TIMER_1_8814B 0
+#define BIT_MASK_PS_TIMER_1_8814B 0xffffffffL
+#define BIT_PS_TIMER_1_8814B(x) \
+ (((x) & BIT_MASK_PS_TIMER_1_8814B) << BIT_SHIFT_PS_TIMER_1_8814B)
+#define BITS_PS_TIMER_1_8814B \
+ (BIT_MASK_PS_TIMER_1_8814B << BIT_SHIFT_PS_TIMER_1_8814B)
+#define BIT_CLEAR_PS_TIMER_1_8814B(x) ((x) & (~BITS_PS_TIMER_1_8814B))
+#define BIT_GET_PS_TIMER_1_8814B(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_1_8814B) & BIT_MASK_PS_TIMER_1_8814B)
+#define BIT_SET_PS_TIMER_1_8814B(x, v) \
+ (BIT_CLEAR_PS_TIMER_1_8814B(x) | BIT_PS_TIMER_1_8814B(v))
+
+/* 2 REG_PS_TIMER_2_8814B */
+
+#define BIT_SHIFT_PS_TIMER_2_8814B 0
+#define BIT_MASK_PS_TIMER_2_8814B 0xffffffffL
+#define BIT_PS_TIMER_2_8814B(x) \
+ (((x) & BIT_MASK_PS_TIMER_2_8814B) << BIT_SHIFT_PS_TIMER_2_8814B)
+#define BITS_PS_TIMER_2_8814B \
+ (BIT_MASK_PS_TIMER_2_8814B << BIT_SHIFT_PS_TIMER_2_8814B)
+#define BIT_CLEAR_PS_TIMER_2_8814B(x) ((x) & (~BITS_PS_TIMER_2_8814B))
+#define BIT_GET_PS_TIMER_2_8814B(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_2_8814B) & BIT_MASK_PS_TIMER_2_8814B)
+#define BIT_SET_PS_TIMER_2_8814B(x, v) \
+ (BIT_CLEAR_PS_TIMER_2_8814B(x) | BIT_PS_TIMER_2_8814B(v))
+
+/* 2 REG_PS_TIMER_3_8814B */
+
+#define BIT_SHIFT_PS_TIMER_3_8814B 0
+#define BIT_MASK_PS_TIMER_3_8814B 0xffffffffL
+#define BIT_PS_TIMER_3_8814B(x) \
+ (((x) & BIT_MASK_PS_TIMER_3_8814B) << BIT_SHIFT_PS_TIMER_3_8814B)
+#define BITS_PS_TIMER_3_8814B \
+ (BIT_MASK_PS_TIMER_3_8814B << BIT_SHIFT_PS_TIMER_3_8814B)
+#define BIT_CLEAR_PS_TIMER_3_8814B(x) ((x) & (~BITS_PS_TIMER_3_8814B))
+#define BIT_GET_PS_TIMER_3_8814B(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_3_8814B) & BIT_MASK_PS_TIMER_3_8814B)
+#define BIT_SET_PS_TIMER_3_8814B(x, v) \
+ (BIT_CLEAR_PS_TIMER_3_8814B(x) | BIT_PS_TIMER_3_8814B(v))
+
+/* 2 REG_PS_TIMER_4_8814B */
+
+#define BIT_SHIFT_PS_TIMER_4_8814B 0
+#define BIT_MASK_PS_TIMER_4_8814B 0xffffffffL
+#define BIT_PS_TIMER_4_8814B(x) \
+ (((x) & BIT_MASK_PS_TIMER_4_8814B) << BIT_SHIFT_PS_TIMER_4_8814B)
+#define BITS_PS_TIMER_4_8814B \
+ (BIT_MASK_PS_TIMER_4_8814B << BIT_SHIFT_PS_TIMER_4_8814B)
+#define BIT_CLEAR_PS_TIMER_4_8814B(x) ((x) & (~BITS_PS_TIMER_4_8814B))
+#define BIT_GET_PS_TIMER_4_8814B(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_4_8814B) & BIT_MASK_PS_TIMER_4_8814B)
+#define BIT_SET_PS_TIMER_4_8814B(x, v) \
+ (BIT_CLEAR_PS_TIMER_4_8814B(x) | BIT_PS_TIMER_4_8814B(v))
+
+/* 2 REG_PS_TIMER_5_8814B */
+
+#define BIT_SHIFT_PS_TIMER_5_8814B 0
+#define BIT_MASK_PS_TIMER_5_8814B 0xffffffffL
+#define BIT_PS_TIMER_5_8814B(x) \
+ (((x) & BIT_MASK_PS_TIMER_5_8814B) << BIT_SHIFT_PS_TIMER_5_8814B)
+#define BITS_PS_TIMER_5_8814B \
+ (BIT_MASK_PS_TIMER_5_8814B << BIT_SHIFT_PS_TIMER_5_8814B)
+#define BIT_CLEAR_PS_TIMER_5_8814B(x) ((x) & (~BITS_PS_TIMER_5_8814B))
+#define BIT_GET_PS_TIMER_5_8814B(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_5_8814B) & BIT_MASK_PS_TIMER_5_8814B)
+#define BIT_SET_PS_TIMER_5_8814B(x, v) \
+ (BIT_CLEAR_PS_TIMER_5_8814B(x) | BIT_PS_TIMER_5_8814B(v))
+
+/* 2 REG_PS_TIMER_01_CTRL_8814B */
+
+#define BIT_SHIFT_PS_TIMER_1_EARLY_TIME_8814B 24
+#define BIT_MASK_PS_TIMER_1_EARLY_TIME_8814B 0xff
+#define BIT_PS_TIMER_1_EARLY_TIME_8814B(x) \
+ (((x) & BIT_MASK_PS_TIMER_1_EARLY_TIME_8814B) \
+ << BIT_SHIFT_PS_TIMER_1_EARLY_TIME_8814B)
+#define BITS_PS_TIMER_1_EARLY_TIME_8814B \
+ (BIT_MASK_PS_TIMER_1_EARLY_TIME_8814B \
+ << BIT_SHIFT_PS_TIMER_1_EARLY_TIME_8814B)
+#define BIT_CLEAR_PS_TIMER_1_EARLY_TIME_8814B(x) \
+ ((x) & (~BITS_PS_TIMER_1_EARLY_TIME_8814B))
+#define BIT_GET_PS_TIMER_1_EARLY_TIME_8814B(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_1_EARLY_TIME_8814B) & \
+ BIT_MASK_PS_TIMER_1_EARLY_TIME_8814B)
+#define BIT_SET_PS_TIMER_1_EARLY_TIME_8814B(x, v) \
+ (BIT_CLEAR_PS_TIMER_1_EARLY_TIME_8814B(x) | \
+ BIT_PS_TIMER_1_EARLY_TIME_8814B(v))
+
+#define BIT_PS_TIMER_1_EN_8814B BIT(23)
+
+#define BIT_SHIFT_PS_TIMER_1_TSF_SEL_8814B 16
+#define BIT_MASK_PS_TIMER_1_TSF_SEL_8814B 0x7
+#define BIT_PS_TIMER_1_TSF_SEL_8814B(x) \
+ (((x) & BIT_MASK_PS_TIMER_1_TSF_SEL_8814B) \
+ << BIT_SHIFT_PS_TIMER_1_TSF_SEL_8814B)
+#define BITS_PS_TIMER_1_TSF_SEL_8814B \
+ (BIT_MASK_PS_TIMER_1_TSF_SEL_8814B \
+ << BIT_SHIFT_PS_TIMER_1_TSF_SEL_8814B)
+#define BIT_CLEAR_PS_TIMER_1_TSF_SEL_8814B(x) \
+ ((x) & (~BITS_PS_TIMER_1_TSF_SEL_8814B))
+#define BIT_GET_PS_TIMER_1_TSF_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_1_TSF_SEL_8814B) & \
+ BIT_MASK_PS_TIMER_1_TSF_SEL_8814B)
+#define BIT_SET_PS_TIMER_1_TSF_SEL_8814B(x, v) \
+ (BIT_CLEAR_PS_TIMER_1_TSF_SEL_8814B(x) | \
+ BIT_PS_TIMER_1_TSF_SEL_8814B(v))
+
+#define BIT_SHIFT_PS_TIMER_0_EARLY_TIME_8814B 8
+#define BIT_MASK_PS_TIMER_0_EARLY_TIME_8814B 0xff
+#define BIT_PS_TIMER_0_EARLY_TIME_8814B(x) \
+ (((x) & BIT_MASK_PS_TIMER_0_EARLY_TIME_8814B) \
+ << BIT_SHIFT_PS_TIMER_0_EARLY_TIME_8814B)
+#define BITS_PS_TIMER_0_EARLY_TIME_8814B \
+ (BIT_MASK_PS_TIMER_0_EARLY_TIME_8814B \
+ << BIT_SHIFT_PS_TIMER_0_EARLY_TIME_8814B)
+#define BIT_CLEAR_PS_TIMER_0_EARLY_TIME_8814B(x) \
+ ((x) & (~BITS_PS_TIMER_0_EARLY_TIME_8814B))
+#define BIT_GET_PS_TIMER_0_EARLY_TIME_8814B(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_0_EARLY_TIME_8814B) & \
+ BIT_MASK_PS_TIMER_0_EARLY_TIME_8814B)
+#define BIT_SET_PS_TIMER_0_EARLY_TIME_8814B(x, v) \
+ (BIT_CLEAR_PS_TIMER_0_EARLY_TIME_8814B(x) | \
+ BIT_PS_TIMER_0_EARLY_TIME_8814B(v))
+
+#define BIT_PS_TIMER_0_EN_8814B BIT(7)
+
+#define BIT_SHIFT_PS_TIMER_0_TSF_SEL_8814B 0
+#define BIT_MASK_PS_TIMER_0_TSF_SEL_8814B 0x7
+#define BIT_PS_TIMER_0_TSF_SEL_8814B(x) \
+ (((x) & BIT_MASK_PS_TIMER_0_TSF_SEL_8814B) \
+ << BIT_SHIFT_PS_TIMER_0_TSF_SEL_8814B)
+#define BITS_PS_TIMER_0_TSF_SEL_8814B \
+ (BIT_MASK_PS_TIMER_0_TSF_SEL_8814B \
+ << BIT_SHIFT_PS_TIMER_0_TSF_SEL_8814B)
+#define BIT_CLEAR_PS_TIMER_0_TSF_SEL_8814B(x) \
+ ((x) & (~BITS_PS_TIMER_0_TSF_SEL_8814B))
+#define BIT_GET_PS_TIMER_0_TSF_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_0_TSF_SEL_8814B) & \
+ BIT_MASK_PS_TIMER_0_TSF_SEL_8814B)
+#define BIT_SET_PS_TIMER_0_TSF_SEL_8814B(x, v) \
+ (BIT_CLEAR_PS_TIMER_0_TSF_SEL_8814B(x) | \
+ BIT_PS_TIMER_0_TSF_SEL_8814B(v))
+
+/* 2 REG_PS_TIMER_23_CTRL_8814B */
+
+#define BIT_SHIFT_PS_TIMER_3_EARLY_TIME_8814B 24
+#define BIT_MASK_PS_TIMER_3_EARLY_TIME_8814B 0xff
+#define BIT_PS_TIMER_3_EARLY_TIME_8814B(x) \
+ (((x) & BIT_MASK_PS_TIMER_3_EARLY_TIME_8814B) \
+ << BIT_SHIFT_PS_TIMER_3_EARLY_TIME_8814B)
+#define BITS_PS_TIMER_3_EARLY_TIME_8814B \
+ (BIT_MASK_PS_TIMER_3_EARLY_TIME_8814B \
+ << BIT_SHIFT_PS_TIMER_3_EARLY_TIME_8814B)
+#define BIT_CLEAR_PS_TIMER_3_EARLY_TIME_8814B(x) \
+ ((x) & (~BITS_PS_TIMER_3_EARLY_TIME_8814B))
+#define BIT_GET_PS_TIMER_3_EARLY_TIME_8814B(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_3_EARLY_TIME_8814B) & \
+ BIT_MASK_PS_TIMER_3_EARLY_TIME_8814B)
+#define BIT_SET_PS_TIMER_3_EARLY_TIME_8814B(x, v) \
+ (BIT_CLEAR_PS_TIMER_3_EARLY_TIME_8814B(x) | \
+ BIT_PS_TIMER_3_EARLY_TIME_8814B(v))
+
+#define BIT_PS_TIMER_3_EN_8814B BIT(23)
+
+#define BIT_SHIFT_PS_TIMER_3_TSF_SEL_8814B 16
+#define BIT_MASK_PS_TIMER_3_TSF_SEL_8814B 0x7
+#define BIT_PS_TIMER_3_TSF_SEL_8814B(x) \
+ (((x) & BIT_MASK_PS_TIMER_3_TSF_SEL_8814B) \
+ << BIT_SHIFT_PS_TIMER_3_TSF_SEL_8814B)
+#define BITS_PS_TIMER_3_TSF_SEL_8814B \
+ (BIT_MASK_PS_TIMER_3_TSF_SEL_8814B \
+ << BIT_SHIFT_PS_TIMER_3_TSF_SEL_8814B)
+#define BIT_CLEAR_PS_TIMER_3_TSF_SEL_8814B(x) \
+ ((x) & (~BITS_PS_TIMER_3_TSF_SEL_8814B))
+#define BIT_GET_PS_TIMER_3_TSF_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_3_TSF_SEL_8814B) & \
+ BIT_MASK_PS_TIMER_3_TSF_SEL_8814B)
+#define BIT_SET_PS_TIMER_3_TSF_SEL_8814B(x, v) \
+ (BIT_CLEAR_PS_TIMER_3_TSF_SEL_8814B(x) | \
+ BIT_PS_TIMER_3_TSF_SEL_8814B(v))
+
+#define BIT_SHIFT_PS_TIMER_2_EARLY_TIME_8814B 8
+#define BIT_MASK_PS_TIMER_2_EARLY_TIME_8814B 0xff
+#define BIT_PS_TIMER_2_EARLY_TIME_8814B(x) \
+ (((x) & BIT_MASK_PS_TIMER_2_EARLY_TIME_8814B) \
+ << BIT_SHIFT_PS_TIMER_2_EARLY_TIME_8814B)
+#define BITS_PS_TIMER_2_EARLY_TIME_8814B \
+ (BIT_MASK_PS_TIMER_2_EARLY_TIME_8814B \
+ << BIT_SHIFT_PS_TIMER_2_EARLY_TIME_8814B)
+#define BIT_CLEAR_PS_TIMER_2_EARLY_TIME_8814B(x) \
+ ((x) & (~BITS_PS_TIMER_2_EARLY_TIME_8814B))
+#define BIT_GET_PS_TIMER_2_EARLY_TIME_8814B(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_2_EARLY_TIME_8814B) & \
+ BIT_MASK_PS_TIMER_2_EARLY_TIME_8814B)
+#define BIT_SET_PS_TIMER_2_EARLY_TIME_8814B(x, v) \
+ (BIT_CLEAR_PS_TIMER_2_EARLY_TIME_8814B(x) | \
+ BIT_PS_TIMER_2_EARLY_TIME_8814B(v))
+
+#define BIT_PS_TIMER_2_EN_8814B BIT(7)
+
+#define BIT_SHIFT_PS_TIMER_2_TSF_SEL_8814B 0
+#define BIT_MASK_PS_TIMER_2_TSF_SEL_8814B 0x7
+#define BIT_PS_TIMER_2_TSF_SEL_8814B(x) \
+ (((x) & BIT_MASK_PS_TIMER_2_TSF_SEL_8814B) \
+ << BIT_SHIFT_PS_TIMER_2_TSF_SEL_8814B)
+#define BITS_PS_TIMER_2_TSF_SEL_8814B \
+ (BIT_MASK_PS_TIMER_2_TSF_SEL_8814B \
+ << BIT_SHIFT_PS_TIMER_2_TSF_SEL_8814B)
+#define BIT_CLEAR_PS_TIMER_2_TSF_SEL_8814B(x) \
+ ((x) & (~BITS_PS_TIMER_2_TSF_SEL_8814B))
+#define BIT_GET_PS_TIMER_2_TSF_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_2_TSF_SEL_8814B) & \
+ BIT_MASK_PS_TIMER_2_TSF_SEL_8814B)
+#define BIT_SET_PS_TIMER_2_TSF_SEL_8814B(x, v) \
+ (BIT_CLEAR_PS_TIMER_2_TSF_SEL_8814B(x) | \
+ BIT_PS_TIMER_2_TSF_SEL_8814B(v))
+
+/* 2 REG_PS_TIMER_45_CTRL_8814B */
+
+#define BIT_SHIFT_PS_TIMER_5_EARLY_TIME_8814B 24
+#define BIT_MASK_PS_TIMER_5_EARLY_TIME_8814B 0xff
+#define BIT_PS_TIMER_5_EARLY_TIME_8814B(x) \
+ (((x) & BIT_MASK_PS_TIMER_5_EARLY_TIME_8814B) \
+ << BIT_SHIFT_PS_TIMER_5_EARLY_TIME_8814B)
+#define BITS_PS_TIMER_5_EARLY_TIME_8814B \
+ (BIT_MASK_PS_TIMER_5_EARLY_TIME_8814B \
+ << BIT_SHIFT_PS_TIMER_5_EARLY_TIME_8814B)
+#define BIT_CLEAR_PS_TIMER_5_EARLY_TIME_8814B(x) \
+ ((x) & (~BITS_PS_TIMER_5_EARLY_TIME_8814B))
+#define BIT_GET_PS_TIMER_5_EARLY_TIME_8814B(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_5_EARLY_TIME_8814B) & \
+ BIT_MASK_PS_TIMER_5_EARLY_TIME_8814B)
+#define BIT_SET_PS_TIMER_5_EARLY_TIME_8814B(x, v) \
+ (BIT_CLEAR_PS_TIMER_5_EARLY_TIME_8814B(x) | \
+ BIT_PS_TIMER_5_EARLY_TIME_8814B(v))
+
+#define BIT_PS_TIMER_5_EN_8814B BIT(23)
+
+#define BIT_SHIFT_PS_TIMER_5_TSF_SEL_8814B 16
+#define BIT_MASK_PS_TIMER_5_TSF_SEL_8814B 0x7
+#define BIT_PS_TIMER_5_TSF_SEL_8814B(x) \
+ (((x) & BIT_MASK_PS_TIMER_5_TSF_SEL_8814B) \
+ << BIT_SHIFT_PS_TIMER_5_TSF_SEL_8814B)
+#define BITS_PS_TIMER_5_TSF_SEL_8814B \
+ (BIT_MASK_PS_TIMER_5_TSF_SEL_8814B \
+ << BIT_SHIFT_PS_TIMER_5_TSF_SEL_8814B)
+#define BIT_CLEAR_PS_TIMER_5_TSF_SEL_8814B(x) \
+ ((x) & (~BITS_PS_TIMER_5_TSF_SEL_8814B))
+#define BIT_GET_PS_TIMER_5_TSF_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_5_TSF_SEL_8814B) & \
+ BIT_MASK_PS_TIMER_5_TSF_SEL_8814B)
+#define BIT_SET_PS_TIMER_5_TSF_SEL_8814B(x, v) \
+ (BIT_CLEAR_PS_TIMER_5_TSF_SEL_8814B(x) | \
+ BIT_PS_TIMER_5_TSF_SEL_8814B(v))
+
+#define BIT_SHIFT_PS_TIMER_4_EARLY_TIME_8814B 8
+#define BIT_MASK_PS_TIMER_4_EARLY_TIME_8814B 0xff
+#define BIT_PS_TIMER_4_EARLY_TIME_8814B(x) \
+ (((x) & BIT_MASK_PS_TIMER_4_EARLY_TIME_8814B) \
+ << BIT_SHIFT_PS_TIMER_4_EARLY_TIME_8814B)
+#define BITS_PS_TIMER_4_EARLY_TIME_8814B \
+ (BIT_MASK_PS_TIMER_4_EARLY_TIME_8814B \
+ << BIT_SHIFT_PS_TIMER_4_EARLY_TIME_8814B)
+#define BIT_CLEAR_PS_TIMER_4_EARLY_TIME_8814B(x) \
+ ((x) & (~BITS_PS_TIMER_4_EARLY_TIME_8814B))
+#define BIT_GET_PS_TIMER_4_EARLY_TIME_8814B(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_4_EARLY_TIME_8814B) & \
+ BIT_MASK_PS_TIMER_4_EARLY_TIME_8814B)
+#define BIT_SET_PS_TIMER_4_EARLY_TIME_8814B(x, v) \
+ (BIT_CLEAR_PS_TIMER_4_EARLY_TIME_8814B(x) | \
+ BIT_PS_TIMER_4_EARLY_TIME_8814B(v))
+
+#define BIT_PS_TIMER_4_EN_8814B BIT(7)
+
+#define BIT_SHIFT_PS_TIMER_4_TSF_SEL_8814B 0
+#define BIT_MASK_PS_TIMER_4_TSF_SEL_8814B 0x7
+#define BIT_PS_TIMER_4_TSF_SEL_8814B(x) \
+ (((x) & BIT_MASK_PS_TIMER_4_TSF_SEL_8814B) \
+ << BIT_SHIFT_PS_TIMER_4_TSF_SEL_8814B)
+#define BITS_PS_TIMER_4_TSF_SEL_8814B \
+ (BIT_MASK_PS_TIMER_4_TSF_SEL_8814B \
+ << BIT_SHIFT_PS_TIMER_4_TSF_SEL_8814B)
+#define BIT_CLEAR_PS_TIMER_4_TSF_SEL_8814B(x) \
+ ((x) & (~BITS_PS_TIMER_4_TSF_SEL_8814B))
+#define BIT_GET_PS_TIMER_4_TSF_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_4_TSF_SEL_8814B) & \
+ BIT_MASK_PS_TIMER_4_TSF_SEL_8814B)
+#define BIT_SET_PS_TIMER_4_TSF_SEL_8814B(x, v) \
+ (BIT_CLEAR_PS_TIMER_4_TSF_SEL_8814B(x) | \
+ BIT_PS_TIMER_4_TSF_SEL_8814B(v))
+
+/* 2 REG_CPUMGQ_FREERUN_TIMER_CTRL_8814B */
+#define BIT_FREECNT_RST_V1_8814B BIT(23)
+#define BIT_EN_FREECNT_V1_8814B BIT(16)
+
+#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1_8814B 8
+#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1_8814B 0xff
+#define BIT_CPUMGQ_TX_TIMER_EARLY_V1_8814B(x) \
+ (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1_8814B) \
+ << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1_8814B)
+#define BITS_CPUMGQ_TX_TIMER_EARLY_V1_8814B \
+ (BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1_8814B \
+ << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1_8814B)
+#define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_V1_8814B(x) \
+ ((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY_V1_8814B))
+#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_V1_8814B) & \
+ BIT_MASK_CPUMGQ_TX_TIMER_EARLY_V1_8814B)
+#define BIT_SET_CPUMGQ_TX_TIMER_EARLY_V1_8814B(x, v) \
+ (BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_V1_8814B(x) | \
+ BIT_CPUMGQ_TX_TIMER_EARLY_V1_8814B(v))
+
+#define BIT_CPUMGQ_TIMER_EN_V1_8814B BIT(7)
+#define BIT_CPUMGQ_DROP_BY_HOLDTIME_8814B BIT(5)
+#define BIT_CPUMGQ_TX_EN_V1_8814B BIT(4)
+
+#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1_8814B 0
+#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1_8814B 0x7
+#define BIT_CPUMGQ_TIMER_TSF_SEL_V1_8814B(x) \
+ (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1_8814B) \
+ << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1_8814B)
+#define BITS_CPUMGQ_TIMER_TSF_SEL_V1_8814B \
+ (BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1_8814B \
+ << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1_8814B)
+#define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_V1_8814B(x) \
+ ((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL_V1_8814B))
+#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_V1_8814B) & \
+ BIT_MASK_CPUMGQ_TIMER_TSF_SEL_V1_8814B)
+#define BIT_SET_CPUMGQ_TIMER_TSF_SEL_V1_8814B(x, v) \
+ (BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_V1_8814B(x) | \
+ BIT_CPUMGQ_TIMER_TSF_SEL_V1_8814B(v))
+
+/* 2 REG_CPUMGQ_PROHIBIT_8814B */
+
+#define BIT_SHIFT_CPUMGQ_HOLD_TIME_8814B 8
+#define BIT_MASK_CPUMGQ_HOLD_TIME_8814B 0xfff
+#define BIT_CPUMGQ_HOLD_TIME_8814B(x) \
+ (((x) & BIT_MASK_CPUMGQ_HOLD_TIME_8814B) \
+ << BIT_SHIFT_CPUMGQ_HOLD_TIME_8814B)
+#define BITS_CPUMGQ_HOLD_TIME_8814B \
+ (BIT_MASK_CPUMGQ_HOLD_TIME_8814B << BIT_SHIFT_CPUMGQ_HOLD_TIME_8814B)
+#define BIT_CLEAR_CPUMGQ_HOLD_TIME_8814B(x) \
+ ((x) & (~BITS_CPUMGQ_HOLD_TIME_8814B))
+#define BIT_GET_CPUMGQ_HOLD_TIME_8814B(x) \
+ (((x) >> BIT_SHIFT_CPUMGQ_HOLD_TIME_8814B) & \
+ BIT_MASK_CPUMGQ_HOLD_TIME_8814B)
+#define BIT_SET_CPUMGQ_HOLD_TIME_8814B(x, v) \
+ (BIT_CLEAR_CPUMGQ_HOLD_TIME_8814B(x) | BIT_CPUMGQ_HOLD_TIME_8814B(v))
+
+#define BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP_8814B 0
+#define BIT_MASK_CPUMGQ_PROHIBIT_SETUP_8814B 0xf
+#define BIT_CPUMGQ_PROHIBIT_SETUP_8814B(x) \
+ (((x) & BIT_MASK_CPUMGQ_PROHIBIT_SETUP_8814B) \
+ << BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP_8814B)
+#define BITS_CPUMGQ_PROHIBIT_SETUP_8814B \
+ (BIT_MASK_CPUMGQ_PROHIBIT_SETUP_8814B \
+ << BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP_8814B)
+#define BIT_CLEAR_CPUMGQ_PROHIBIT_SETUP_8814B(x) \
+ ((x) & (~BITS_CPUMGQ_PROHIBIT_SETUP_8814B))
+#define BIT_GET_CPUMGQ_PROHIBIT_SETUP_8814B(x) \
+ (((x) >> BIT_SHIFT_CPUMGQ_PROHIBIT_SETUP_8814B) & \
+ BIT_MASK_CPUMGQ_PROHIBIT_SETUP_8814B)
+#define BIT_SET_CPUMGQ_PROHIBIT_SETUP_8814B(x, v) \
+ (BIT_CLEAR_CPUMGQ_PROHIBIT_SETUP_8814B(x) | \
+ BIT_CPUMGQ_PROHIBIT_SETUP_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_TIMER_COMPARE_8814B */
+#define BIT_COMP_TRIGGER_8814B BIT(7)
+
+#define BIT_SHIFT_Y_COMP_8814B 4
+#define BIT_MASK_Y_COMP_8814B 0x7
+#define BIT_Y_COMP_8814B(x) \
+ (((x) & BIT_MASK_Y_COMP_8814B) << BIT_SHIFT_Y_COMP_8814B)
+#define BITS_Y_COMP_8814B (BIT_MASK_Y_COMP_8814B << BIT_SHIFT_Y_COMP_8814B)
+#define BIT_CLEAR_Y_COMP_8814B(x) ((x) & (~BITS_Y_COMP_8814B))
+#define BIT_GET_Y_COMP_8814B(x) \
+ (((x) >> BIT_SHIFT_Y_COMP_8814B) & BIT_MASK_Y_COMP_8814B)
+#define BIT_SET_Y_COMP_8814B(x, v) \
+ (BIT_CLEAR_Y_COMP_8814B(x) | BIT_Y_COMP_8814B(v))
+
+#define BIT_X_COMP_Y_OVERFLOW_8814B BIT(3)
+
+#define BIT_SHIFT_X_COMP_8814B 0
+#define BIT_MASK_X_COMP_8814B 0x7
+#define BIT_X_COMP_8814B(x) \
+ (((x) & BIT_MASK_X_COMP_8814B) << BIT_SHIFT_X_COMP_8814B)
+#define BITS_X_COMP_8814B (BIT_MASK_X_COMP_8814B << BIT_SHIFT_X_COMP_8814B)
+#define BIT_CLEAR_X_COMP_8814B(x) ((x) & (~BITS_X_COMP_8814B))
+#define BIT_GET_X_COMP_8814B(x) \
+ (((x) >> BIT_SHIFT_X_COMP_8814B) & BIT_MASK_X_COMP_8814B)
+#define BIT_SET_X_COMP_8814B(x, v) \
+ (BIT_CLEAR_X_COMP_8814B(x) | BIT_X_COMP_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_TIMER_COMPARE_VALUE_LOW_8814B */
+
+#define BIT_SHIFT_COMP_VALUE_LOW_8814B 0
+#define BIT_MASK_COMP_VALUE_LOW_8814B 0xffffffffL
+#define BIT_COMP_VALUE_LOW_8814B(x) \
+ (((x) & BIT_MASK_COMP_VALUE_LOW_8814B) \
+ << BIT_SHIFT_COMP_VALUE_LOW_8814B)
+#define BITS_COMP_VALUE_LOW_8814B \
+ (BIT_MASK_COMP_VALUE_LOW_8814B << BIT_SHIFT_COMP_VALUE_LOW_8814B)
+#define BIT_CLEAR_COMP_VALUE_LOW_8814B(x) ((x) & (~BITS_COMP_VALUE_LOW_8814B))
+#define BIT_GET_COMP_VALUE_LOW_8814B(x) \
+ (((x) >> BIT_SHIFT_COMP_VALUE_LOW_8814B) & \
+ BIT_MASK_COMP_VALUE_LOW_8814B)
+#define BIT_SET_COMP_VALUE_LOW_8814B(x, v) \
+ (BIT_CLEAR_COMP_VALUE_LOW_8814B(x) | BIT_COMP_VALUE_LOW_8814B(v))
+
+/* 2 REG_TIMER_COMPARE_VALUE_HIGH_8814B */
+
+#define BIT_SHIFT_COMP_VALUE_HIGH_8814B 0
+#define BIT_MASK_COMP_VALUE_HIGH_8814B 0xffffffffL
+#define BIT_COMP_VALUE_HIGH_8814B(x) \
+ (((x) & BIT_MASK_COMP_VALUE_HIGH_8814B) \
+ << BIT_SHIFT_COMP_VALUE_HIGH_8814B)
+#define BITS_COMP_VALUE_HIGH_8814B \
+ (BIT_MASK_COMP_VALUE_HIGH_8814B << BIT_SHIFT_COMP_VALUE_HIGH_8814B)
+#define BIT_CLEAR_COMP_VALUE_HIGH_8814B(x) ((x) & (~BITS_COMP_VALUE_HIGH_8814B))
+#define BIT_GET_COMP_VALUE_HIGH_8814B(x) \
+ (((x) >> BIT_SHIFT_COMP_VALUE_HIGH_8814B) & \
+ BIT_MASK_COMP_VALUE_HIGH_8814B)
+#define BIT_SET_COMP_VALUE_HIGH_8814B(x, v) \
+ (BIT_CLEAR_COMP_VALUE_HIGH_8814B(x) | BIT_COMP_VALUE_HIGH_8814B(v))
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_WMAC_CR_8814B (WMAC CR AND APSD CONTROL REGISTER) */
+#define BIT_IC_MACPHY_M_8814B BIT(0)
+
+/* 2 REG_WMAC_FWPKT_CR_8814B */
+#define BIT_FWEN_8814B BIT(7)
+#define BIT_PHYSTS_PKT_CTRL_8814B BIT(6)
+#define BIT_FWFULL_TO_RXFF_EN_8814B BIT(5)
+#define BIT_APPHDR_MIDSRCH_FAIL_8814B BIT(4)
+#define BIT_FWPARSING_EN_8814B BIT(3)
+
+#define BIT_SHIFT_APPEND_MHDR_LEN_8814B 0
+#define BIT_MASK_APPEND_MHDR_LEN_8814B 0x7
+#define BIT_APPEND_MHDR_LEN_8814B(x) \
+ (((x) & BIT_MASK_APPEND_MHDR_LEN_8814B) \
+ << BIT_SHIFT_APPEND_MHDR_LEN_8814B)
+#define BITS_APPEND_MHDR_LEN_8814B \
+ (BIT_MASK_APPEND_MHDR_LEN_8814B << BIT_SHIFT_APPEND_MHDR_LEN_8814B)
+#define BIT_CLEAR_APPEND_MHDR_LEN_8814B(x) ((x) & (~BITS_APPEND_MHDR_LEN_8814B))
+#define BIT_GET_APPEND_MHDR_LEN_8814B(x) \
+ (((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8814B) & \
+ BIT_MASK_APPEND_MHDR_LEN_8814B)
+#define BIT_SET_APPEND_MHDR_LEN_8814B(x, v) \
+ (BIT_CLEAR_APPEND_MHDR_LEN_8814B(x) | BIT_APPEND_MHDR_LEN_8814B(v))
+
+/* 2 REG_FW_STS_FILTER_8814B */
+#define BIT_DATA_FW_STS_FILTER_8814B BIT(2)
+#define BIT_CTRL_FW_STS_FILTER_8814B BIT(1)
+#define BIT_MGNT_FW_STS_FILTER_8814B BIT(0)
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_TCR_8814B (TRANSMISSION CONFIGURATION REGISTER) */
+#define BIT_WMAC_EN_RTS_ADDR_8814B BIT(31)
+#define BIT_WMAC_DISABLE_CCK_8814B BIT(30)
+#define BIT_WMAC_RAW_LEN_8814B BIT(29)
+#define BIT_WMAC_NOTX_IN_RXNDP_8814B BIT(28)
+#define BIT_WMAC_EN_EOF_8814B BIT(27)
+#define BIT_WMAC_BF_SEL_8814B BIT(26)
+#define BIT_WMAC_TCRPWRMGT_HWCTL_EN_8814B BIT(24)
+#define BIT_WMAC_SMOOTH_VAL_8814B BIT(23)
+#define BIT_WMAC_EN_SCRAM_INC_8814B BIT(22)
+#define BIT_UNDERFLOWEN_CMPLEN_SEL_8814B BIT(21)
+#define BIT_FETCH_MPDU_AFTER_WSEC_RDY_8814B BIT(20)
+#define BIT_WMAC_TCR_EN_20MST_8814B BIT(19)
+#define BIT_WMAC_DIS_SIGTA_8814B BIT(18)
+#define BIT_WMAC_DIS_A2B0_8814B BIT(17)
+#define BIT_WMAC_MSK_SIGBCRC_8814B BIT(16)
+#define BIT_WMAC_TCR_ERRSTEN_3_8814B BIT(15)
+#define BIT_WMAC_TCR_ERRSTEN_2_8814B BIT(14)
+#define BIT_WMAC_TCR_ERRSTEN_1_8814B BIT(13)
+#define BIT_WMAC_TCR_ERRSTEN_0_8814B BIT(12)
+#define BIT_WMAC_TCR_TXSK_PERPKT_8814B BIT(11)
+#define BIT_ICV_8814B BIT(10)
+#define BIT_CRC_8814B BIT(8)
+#define BIT_WMAC_TCRPWRMGT_HWDATA_EN_8814B BIT(7)
+#define BIT_PWR_ST_8814B BIT(6)
+#define BIT_WMAC_TCR_UPD_TIMIE_8814B BIT(5)
+#define BIT_WMAC_TCR_UPD_HGQMD_8814B BIT(4)
+#define BIT_VHTSIGA1_TXPS_8814B BIT(3)
+#define BIT_PAD_SEL_8814B BIT(2)
+#define BIT_DIS_GCLK_8814B BIT(1)
+#define BIT_WMAC_TCRPWRMGT_HWACT_EN_8814B BIT(0)
+
+/* 2 REG_RCR_8814B (RECEIVE CONFIGURATION REGISTER) */
+#define BIT_APP_FCS_8814B BIT(31)
+#define BIT_APP_MIC_8814B BIT(30)
+#define BIT_APP_ICV_8814B BIT(29)
+#define BIT_APP_PHYSTS_8814B BIT(28)
+#define BIT_APP_BASSN_8814B BIT(27)
+#define BIT_VHT_DACK_8814B BIT(26)
+#define BIT_TCPOFLD_EN_8814B BIT(25)
+#define BIT_ENADDRCAM_8814B BIT(24)
+#define BIT_LSIGEN_8814B BIT(23)
+#define BIT_MFBEN_8814B BIT(22)
+#define BIT_DISCHKPPDLLEN_8814B BIT(21)
+#define BIT_PKTCTL_DLEN_8814B BIT(20)
+#define BIT_DISGCLK_8814B BIT(19)
+#define BIT_TIM_PARSER_EN_8814B BIT(18)
+#define BIT_BC_MD_EN_8814B BIT(17)
+#define BIT_UC_MD_EN_8814B BIT(16)
+#define BIT_RXSK_PERPKT_8814B BIT(15)
+#define BIT_HTC_LOC_CTRL_8814B BIT(14)
+#define BIT_ACK_WITH_CBSSID_DATA_OPTION_8814B BIT(13)
+#define BIT_RPFM_CAM_ENABLE_8814B BIT(12)
+#define BIT_TA_BCN_8814B BIT(11)
+#define BIT_DISDECMYPKT_8814B BIT(10)
+#define BIT_AICV_8814B BIT(9)
+#define BIT_ACRC32_8814B BIT(8)
+#define BIT_CBSSID_BCN_8814B BIT(7)
+#define BIT_CBSSID_DATA_8814B BIT(6)
+#define BIT_APWRMGT_8814B BIT(5)
+#define BIT_ADD3_8814B BIT(4)
+#define BIT_AB_8814B BIT(3)
+#define BIT_AM_8814B BIT(2)
+#define BIT_APM_8814B BIT(1)
+#define BIT_AAP_8814B BIT(0)
+
+/* 2 REG_RX_PKT_LIMIT_8814B (RX PACKET LENGTH LIMIT REGISTER) */
+
+#define BIT_SHIFT_RXPKTLMT_8814B 0
+#define BIT_MASK_RXPKTLMT_8814B 0x3f
+#define BIT_RXPKTLMT_8814B(x) \
+ (((x) & BIT_MASK_RXPKTLMT_8814B) << BIT_SHIFT_RXPKTLMT_8814B)
+#define BITS_RXPKTLMT_8814B \
+ (BIT_MASK_RXPKTLMT_8814B << BIT_SHIFT_RXPKTLMT_8814B)
+#define BIT_CLEAR_RXPKTLMT_8814B(x) ((x) & (~BITS_RXPKTLMT_8814B))
+#define BIT_GET_RXPKTLMT_8814B(x) \
+ (((x) >> BIT_SHIFT_RXPKTLMT_8814B) & BIT_MASK_RXPKTLMT_8814B)
+#define BIT_SET_RXPKTLMT_8814B(x, v) \
+ (BIT_CLEAR_RXPKTLMT_8814B(x) | BIT_RXPKTLMT_8814B(v))
+
+/* 2 REG_RX_DLK_TIME_8814B (RX DEADLOCK TIME REGISTER) */
+
+#define BIT_SHIFT_RX_DLK_TIME_8814B 0
+#define BIT_MASK_RX_DLK_TIME_8814B 0xff
+#define BIT_RX_DLK_TIME_8814B(x) \
+ (((x) & BIT_MASK_RX_DLK_TIME_8814B) << BIT_SHIFT_RX_DLK_TIME_8814B)
+#define BITS_RX_DLK_TIME_8814B \
+ (BIT_MASK_RX_DLK_TIME_8814B << BIT_SHIFT_RX_DLK_TIME_8814B)
+#define BIT_CLEAR_RX_DLK_TIME_8814B(x) ((x) & (~BITS_RX_DLK_TIME_8814B))
+#define BIT_GET_RX_DLK_TIME_8814B(x) \
+ (((x) >> BIT_SHIFT_RX_DLK_TIME_8814B) & BIT_MASK_RX_DLK_TIME_8814B)
+#define BIT_SET_RX_DLK_TIME_8814B(x, v) \
+ (BIT_CLEAR_RX_DLK_TIME_8814B(x) | BIT_RX_DLK_TIME_8814B(v))
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RX_DRVINFO_SZ_8814B (RX DRIVER INFO SIZE REGISTER) */
+#define BIT_PHYSTS_PER_PKT_MODE_8814B BIT(7)
+
+#define BIT_SHIFT_DRVINFO_SZ_V1_8814B 0
+#define BIT_MASK_DRVINFO_SZ_V1_8814B 0xf
+#define BIT_DRVINFO_SZ_V1_8814B(x) \
+ (((x) & BIT_MASK_DRVINFO_SZ_V1_8814B) << BIT_SHIFT_DRVINFO_SZ_V1_8814B)
+#define BITS_DRVINFO_SZ_V1_8814B \
+ (BIT_MASK_DRVINFO_SZ_V1_8814B << BIT_SHIFT_DRVINFO_SZ_V1_8814B)
+#define BIT_CLEAR_DRVINFO_SZ_V1_8814B(x) ((x) & (~BITS_DRVINFO_SZ_V1_8814B))
+#define BIT_GET_DRVINFO_SZ_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8814B) & BIT_MASK_DRVINFO_SZ_V1_8814B)
+#define BIT_SET_DRVINFO_SZ_V1_8814B(x, v) \
+ (BIT_CLEAR_DRVINFO_SZ_V1_8814B(x) | BIT_DRVINFO_SZ_V1_8814B(v))
+
+/* 2 REG_MACID_8814B (MAC ID REGISTER) */
+
+#define BIT_SHIFT_MACID_V1_8814B 0
+#define BIT_MASK_MACID_V1_8814B 0xffffffffL
+#define BIT_MACID_V1_8814B(x) \
+ (((x) & BIT_MASK_MACID_V1_8814B) << BIT_SHIFT_MACID_V1_8814B)
+#define BITS_MACID_V1_8814B \
+ (BIT_MASK_MACID_V1_8814B << BIT_SHIFT_MACID_V1_8814B)
+#define BIT_CLEAR_MACID_V1_8814B(x) ((x) & (~BITS_MACID_V1_8814B))
+#define BIT_GET_MACID_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_MACID_V1_8814B) & BIT_MASK_MACID_V1_8814B)
+#define BIT_SET_MACID_V1_8814B(x, v) \
+ (BIT_CLEAR_MACID_V1_8814B(x) | BIT_MACID_V1_8814B(v))
+
+/* 2 REG_MACID_H_8814B (MAC ID REGISTER) */
+
+#define BIT_SHIFT_MACID_H_V1_8814B 0
+#define BIT_MASK_MACID_H_V1_8814B 0xffff
+#define BIT_MACID_H_V1_8814B(x) \
+ (((x) & BIT_MASK_MACID_H_V1_8814B) << BIT_SHIFT_MACID_H_V1_8814B)
+#define BITS_MACID_H_V1_8814B \
+ (BIT_MASK_MACID_H_V1_8814B << BIT_SHIFT_MACID_H_V1_8814B)
+#define BIT_CLEAR_MACID_H_V1_8814B(x) ((x) & (~BITS_MACID_H_V1_8814B))
+#define BIT_GET_MACID_H_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_MACID_H_V1_8814B) & BIT_MASK_MACID_H_V1_8814B)
+#define BIT_SET_MACID_H_V1_8814B(x, v) \
+ (BIT_CLEAR_MACID_H_V1_8814B(x) | BIT_MACID_H_V1_8814B(v))
+
+/* 2 REG_BSSID_8814B (BSSID REGISTER) */
+
+#define BIT_SHIFT_BSSID_V1_8814B 0
+#define BIT_MASK_BSSID_V1_8814B 0xffffffffL
+#define BIT_BSSID_V1_8814B(x) \
+ (((x) & BIT_MASK_BSSID_V1_8814B) << BIT_SHIFT_BSSID_V1_8814B)
+#define BITS_BSSID_V1_8814B \
+ (BIT_MASK_BSSID_V1_8814B << BIT_SHIFT_BSSID_V1_8814B)
+#define BIT_CLEAR_BSSID_V1_8814B(x) ((x) & (~BITS_BSSID_V1_8814B))
+#define BIT_GET_BSSID_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_BSSID_V1_8814B) & BIT_MASK_BSSID_V1_8814B)
+#define BIT_SET_BSSID_V1_8814B(x, v) \
+ (BIT_CLEAR_BSSID_V1_8814B(x) | BIT_BSSID_V1_8814B(v))
+
+/* 2 REG_BSSID_H_8814B (BSSID REGISTER) */
+
+/* 2 REG_NOT_VALID_8814B */
+
+#define BIT_SHIFT_BSSID_H_V1_8814B 0
+#define BIT_MASK_BSSID_H_V1_8814B 0xffff
+#define BIT_BSSID_H_V1_8814B(x) \
+ (((x) & BIT_MASK_BSSID_H_V1_8814B) << BIT_SHIFT_BSSID_H_V1_8814B)
+#define BITS_BSSID_H_V1_8814B \
+ (BIT_MASK_BSSID_H_V1_8814B << BIT_SHIFT_BSSID_H_V1_8814B)
+#define BIT_CLEAR_BSSID_H_V1_8814B(x) ((x) & (~BITS_BSSID_H_V1_8814B))
+#define BIT_GET_BSSID_H_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_BSSID_H_V1_8814B) & BIT_MASK_BSSID_H_V1_8814B)
+#define BIT_SET_BSSID_H_V1_8814B(x, v) \
+ (BIT_CLEAR_BSSID_H_V1_8814B(x) | BIT_BSSID_H_V1_8814B(v))
+
+/* 2 REG_MAR_8814B (MULTICAST ADDRESS REGISTER) */
+
+#define BIT_SHIFT_MAR_V1_8814B 0
+#define BIT_MASK_MAR_V1_8814B 0xffffffffL
+#define BIT_MAR_V1_8814B(x) \
+ (((x) & BIT_MASK_MAR_V1_8814B) << BIT_SHIFT_MAR_V1_8814B)
+#define BITS_MAR_V1_8814B (BIT_MASK_MAR_V1_8814B << BIT_SHIFT_MAR_V1_8814B)
+#define BIT_CLEAR_MAR_V1_8814B(x) ((x) & (~BITS_MAR_V1_8814B))
+#define BIT_GET_MAR_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_MAR_V1_8814B) & BIT_MASK_MAR_V1_8814B)
+#define BIT_SET_MAR_V1_8814B(x, v) \
+ (BIT_CLEAR_MAR_V1_8814B(x) | BIT_MAR_V1_8814B(v))
+
+/* 2 REG_MAR_H_8814B (MULTICAST ADDRESS REGISTER) */
+
+#define BIT_SHIFT_MAR_H_V1_8814B 0
+#define BIT_MASK_MAR_H_V1_8814B 0xffffffffL
+#define BIT_MAR_H_V1_8814B(x) \
+ (((x) & BIT_MASK_MAR_H_V1_8814B) << BIT_SHIFT_MAR_H_V1_8814B)
+#define BITS_MAR_H_V1_8814B \
+ (BIT_MASK_MAR_H_V1_8814B << BIT_SHIFT_MAR_H_V1_8814B)
+#define BIT_CLEAR_MAR_H_V1_8814B(x) ((x) & (~BITS_MAR_H_V1_8814B))
+#define BIT_GET_MAR_H_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_MAR_H_V1_8814B) & BIT_MASK_MAR_H_V1_8814B)
+#define BIT_SET_MAR_H_V1_8814B(x, v) \
+ (BIT_CLEAR_MAR_H_V1_8814B(x) | BIT_MAR_H_V1_8814B(v))
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_WMAC_DEBUG_SEL_8814B */
+
+#define BIT_SHIFT_WMAC_ARB_DBG_SEL_8814B 3
+#define BIT_MASK_WMAC_ARB_DBG_SEL_8814B 0x3
+#define BIT_WMAC_ARB_DBG_SEL_8814B(x) \
+ (((x) & BIT_MASK_WMAC_ARB_DBG_SEL_8814B) \
+ << BIT_SHIFT_WMAC_ARB_DBG_SEL_8814B)
+#define BITS_WMAC_ARB_DBG_SEL_8814B \
+ (BIT_MASK_WMAC_ARB_DBG_SEL_8814B << BIT_SHIFT_WMAC_ARB_DBG_SEL_8814B)
+#define BIT_CLEAR_WMAC_ARB_DBG_SEL_8814B(x) \
+ ((x) & (~BITS_WMAC_ARB_DBG_SEL_8814B))
+#define BIT_GET_WMAC_ARB_DBG_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_WMAC_ARB_DBG_SEL_8814B) & \
+ BIT_MASK_WMAC_ARB_DBG_SEL_8814B)
+#define BIT_SET_WMAC_ARB_DBG_SEL_8814B(x, v) \
+ (BIT_CLEAR_WMAC_ARB_DBG_SEL_8814B(x) | BIT_WMAC_ARB_DBG_SEL_8814B(v))
+
+#define BIT_WMAC_EXT_DBG_SEL_8814B BIT(2)
+
+#define BIT_SHIFT_WMAC_MU_DBGSEL_V1_8814B 0
+#define BIT_MASK_WMAC_MU_DBGSEL_V1_8814B 0x3
+#define BIT_WMAC_MU_DBGSEL_V1_8814B(x) \
+ (((x) & BIT_MASK_WMAC_MU_DBGSEL_V1_8814B) \
+ << BIT_SHIFT_WMAC_MU_DBGSEL_V1_8814B)
+#define BITS_WMAC_MU_DBGSEL_V1_8814B \
+ (BIT_MASK_WMAC_MU_DBGSEL_V1_8814B << BIT_SHIFT_WMAC_MU_DBGSEL_V1_8814B)
+#define BIT_CLEAR_WMAC_MU_DBGSEL_V1_8814B(x) \
+ ((x) & (~BITS_WMAC_MU_DBGSEL_V1_8814B))
+#define BIT_GET_WMAC_MU_DBGSEL_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_V1_8814B) & \
+ BIT_MASK_WMAC_MU_DBGSEL_V1_8814B)
+#define BIT_SET_WMAC_MU_DBGSEL_V1_8814B(x, v) \
+ (BIT_CLEAR_WMAC_MU_DBGSEL_V1_8814B(x) | BIT_WMAC_MU_DBGSEL_V1_8814B(v))
+
+/* 2 REG_WMAC_TCR_TSFT_OFS_8814B */
+
+#define BIT_SHIFT_WMAC_TCR_TSFT_OFS_8814B 0
+#define BIT_MASK_WMAC_TCR_TSFT_OFS_8814B 0xffff
+#define BIT_WMAC_TCR_TSFT_OFS_8814B(x) \
+ (((x) & BIT_MASK_WMAC_TCR_TSFT_OFS_8814B) \
+ << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8814B)
+#define BITS_WMAC_TCR_TSFT_OFS_8814B \
+ (BIT_MASK_WMAC_TCR_TSFT_OFS_8814B << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8814B)
+#define BIT_CLEAR_WMAC_TCR_TSFT_OFS_8814B(x) \
+ ((x) & (~BITS_WMAC_TCR_TSFT_OFS_8814B))
+#define BIT_GET_WMAC_TCR_TSFT_OFS_8814B(x) \
+ (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8814B) & \
+ BIT_MASK_WMAC_TCR_TSFT_OFS_8814B)
+#define BIT_SET_WMAC_TCR_TSFT_OFS_8814B(x, v) \
+ (BIT_CLEAR_WMAC_TCR_TSFT_OFS_8814B(x) | BIT_WMAC_TCR_TSFT_OFS_8814B(v))
+
+/* 2 REG_UDF_THSD_8814B */
+#define BIT_UDF_THSD_V1_8814B BIT(7)
+
+#define BIT_SHIFT_UDF_THSD_VALUE_8814B 0
+#define BIT_MASK_UDF_THSD_VALUE_8814B 0x7f
+#define BIT_UDF_THSD_VALUE_8814B(x) \
+ (((x) & BIT_MASK_UDF_THSD_VALUE_8814B) \
+ << BIT_SHIFT_UDF_THSD_VALUE_8814B)
+#define BITS_UDF_THSD_VALUE_8814B \
+ (BIT_MASK_UDF_THSD_VALUE_8814B << BIT_SHIFT_UDF_THSD_VALUE_8814B)
+#define BIT_CLEAR_UDF_THSD_VALUE_8814B(x) ((x) & (~BITS_UDF_THSD_VALUE_8814B))
+#define BIT_GET_UDF_THSD_VALUE_8814B(x) \
+ (((x) >> BIT_SHIFT_UDF_THSD_VALUE_8814B) & \
+ BIT_MASK_UDF_THSD_VALUE_8814B)
+#define BIT_SET_UDF_THSD_VALUE_8814B(x, v) \
+ (BIT_CLEAR_UDF_THSD_VALUE_8814B(x) | BIT_UDF_THSD_VALUE_8814B(v))
+
+/* 2 REG_ZLD_NUM_8814B */
+
+#define BIT_SHIFT_ZLD_NUM_8814B 0
+#define BIT_MASK_ZLD_NUM_8814B 0xff
+#define BIT_ZLD_NUM_8814B(x) \
+ (((x) & BIT_MASK_ZLD_NUM_8814B) << BIT_SHIFT_ZLD_NUM_8814B)
+#define BITS_ZLD_NUM_8814B (BIT_MASK_ZLD_NUM_8814B << BIT_SHIFT_ZLD_NUM_8814B)
+#define BIT_CLEAR_ZLD_NUM_8814B(x) ((x) & (~BITS_ZLD_NUM_8814B))
+#define BIT_GET_ZLD_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_ZLD_NUM_8814B) & BIT_MASK_ZLD_NUM_8814B)
+#define BIT_SET_ZLD_NUM_8814B(x, v) \
+ (BIT_CLEAR_ZLD_NUM_8814B(x) | BIT_ZLD_NUM_8814B(v))
+
+/* 2 REG_STMP_THSD_8814B */
+
+#define BIT_SHIFT_STMP_THSD_8814B 0
+#define BIT_MASK_STMP_THSD_8814B 0xff
+#define BIT_STMP_THSD_8814B(x) \
+ (((x) & BIT_MASK_STMP_THSD_8814B) << BIT_SHIFT_STMP_THSD_8814B)
+#define BITS_STMP_THSD_8814B \
+ (BIT_MASK_STMP_THSD_8814B << BIT_SHIFT_STMP_THSD_8814B)
+#define BIT_CLEAR_STMP_THSD_8814B(x) ((x) & (~BITS_STMP_THSD_8814B))
+#define BIT_GET_STMP_THSD_8814B(x) \
+ (((x) >> BIT_SHIFT_STMP_THSD_8814B) & BIT_MASK_STMP_THSD_8814B)
+#define BIT_SET_STMP_THSD_8814B(x, v) \
+ (BIT_CLEAR_STMP_THSD_8814B(x) | BIT_STMP_THSD_8814B(v))
+
+/* 2 REG_WMAC_TXTIMEOUT_8814B */
+
+#define BIT_SHIFT_WMAC_TXTIMEOUT_8814B 0
+#define BIT_MASK_WMAC_TXTIMEOUT_8814B 0xff
+#define BIT_WMAC_TXTIMEOUT_8814B(x) \
+ (((x) & BIT_MASK_WMAC_TXTIMEOUT_8814B) \
+ << BIT_SHIFT_WMAC_TXTIMEOUT_8814B)
+#define BITS_WMAC_TXTIMEOUT_8814B \
+ (BIT_MASK_WMAC_TXTIMEOUT_8814B << BIT_SHIFT_WMAC_TXTIMEOUT_8814B)
+#define BIT_CLEAR_WMAC_TXTIMEOUT_8814B(x) ((x) & (~BITS_WMAC_TXTIMEOUT_8814B))
+#define BIT_GET_WMAC_TXTIMEOUT_8814B(x) \
+ (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8814B) & \
+ BIT_MASK_WMAC_TXTIMEOUT_8814B)
+#define BIT_SET_WMAC_TXTIMEOUT_8814B(x, v) \
+ (BIT_CLEAR_WMAC_TXTIMEOUT_8814B(x) | BIT_WMAC_TXTIMEOUT_8814B(v))
+
+/* 2 REG_MCU_TEST_2_V1_8814B */
+
+#define BIT_SHIFT_MCU_RSVD_2_V1_8814B 0
+#define BIT_MASK_MCU_RSVD_2_V1_8814B 0xffff
+#define BIT_MCU_RSVD_2_V1_8814B(x) \
+ (((x) & BIT_MASK_MCU_RSVD_2_V1_8814B) << BIT_SHIFT_MCU_RSVD_2_V1_8814B)
+#define BITS_MCU_RSVD_2_V1_8814B \
+ (BIT_MASK_MCU_RSVD_2_V1_8814B << BIT_SHIFT_MCU_RSVD_2_V1_8814B)
+#define BIT_CLEAR_MCU_RSVD_2_V1_8814B(x) ((x) & (~BITS_MCU_RSVD_2_V1_8814B))
+#define BIT_GET_MCU_RSVD_2_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_MCU_RSVD_2_V1_8814B) & BIT_MASK_MCU_RSVD_2_V1_8814B)
+#define BIT_SET_MCU_RSVD_2_V1_8814B(x, v) \
+ (BIT_CLEAR_MCU_RSVD_2_V1_8814B(x) | BIT_MCU_RSVD_2_V1_8814B(v))
+
+/* 2 REG_USTIME_EDCA_8814B (US TIME TUNING FOR EDCA REGISTER) */
+
+#define BIT_SHIFT_USTIME_EDCA_8814B 0
+#define BIT_MASK_USTIME_EDCA_8814B 0xff
+#define BIT_USTIME_EDCA_8814B(x) \
+ (((x) & BIT_MASK_USTIME_EDCA_8814B) << BIT_SHIFT_USTIME_EDCA_8814B)
+#define BITS_USTIME_EDCA_8814B \
+ (BIT_MASK_USTIME_EDCA_8814B << BIT_SHIFT_USTIME_EDCA_8814B)
+#define BIT_CLEAR_USTIME_EDCA_8814B(x) ((x) & (~BITS_USTIME_EDCA_8814B))
+#define BIT_GET_USTIME_EDCA_8814B(x) \
+ (((x) >> BIT_SHIFT_USTIME_EDCA_8814B) & BIT_MASK_USTIME_EDCA_8814B)
+#define BIT_SET_USTIME_EDCA_8814B(x, v) \
+ (BIT_CLEAR_USTIME_EDCA_8814B(x) | BIT_USTIME_EDCA_8814B(v))
+
+/* 2 REG_ACKTO_CCK_8814B (ACK TIMEOUT REGISTER FOR CCK RATE) */
+
+#define BIT_SHIFT_ACKTO_CCK_8814B 0
+#define BIT_MASK_ACKTO_CCK_8814B 0xff
+#define BIT_ACKTO_CCK_8814B(x) \
+ (((x) & BIT_MASK_ACKTO_CCK_8814B) << BIT_SHIFT_ACKTO_CCK_8814B)
+#define BITS_ACKTO_CCK_8814B \
+ (BIT_MASK_ACKTO_CCK_8814B << BIT_SHIFT_ACKTO_CCK_8814B)
+#define BIT_CLEAR_ACKTO_CCK_8814B(x) ((x) & (~BITS_ACKTO_CCK_8814B))
+#define BIT_GET_ACKTO_CCK_8814B(x) \
+ (((x) >> BIT_SHIFT_ACKTO_CCK_8814B) & BIT_MASK_ACKTO_CCK_8814B)
+#define BIT_SET_ACKTO_CCK_8814B(x, v) \
+ (BIT_CLEAR_ACKTO_CCK_8814B(x) | BIT_ACKTO_CCK_8814B(v))
+
+/* 2 REG_MAC_SPEC_SIFS_8814B (SPECIFICATION SIFS REGISTER) */
+
+#define BIT_SHIFT_SPEC_SIFS_OFDM_8814B 8
+#define BIT_MASK_SPEC_SIFS_OFDM_8814B 0xff
+#define BIT_SPEC_SIFS_OFDM_8814B(x) \
+ (((x) & BIT_MASK_SPEC_SIFS_OFDM_8814B) \
+ << BIT_SHIFT_SPEC_SIFS_OFDM_8814B)
+#define BITS_SPEC_SIFS_OFDM_8814B \
+ (BIT_MASK_SPEC_SIFS_OFDM_8814B << BIT_SHIFT_SPEC_SIFS_OFDM_8814B)
+#define BIT_CLEAR_SPEC_SIFS_OFDM_8814B(x) ((x) & (~BITS_SPEC_SIFS_OFDM_8814B))
+#define BIT_GET_SPEC_SIFS_OFDM_8814B(x) \
+ (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8814B) & \
+ BIT_MASK_SPEC_SIFS_OFDM_8814B)
+#define BIT_SET_SPEC_SIFS_OFDM_8814B(x, v) \
+ (BIT_CLEAR_SPEC_SIFS_OFDM_8814B(x) | BIT_SPEC_SIFS_OFDM_8814B(v))
+
+#define BIT_SHIFT_SPEC_SIFS_CCK_8814B 0
+#define BIT_MASK_SPEC_SIFS_CCK_8814B 0xff
+#define BIT_SPEC_SIFS_CCK_8814B(x) \
+ (((x) & BIT_MASK_SPEC_SIFS_CCK_8814B) << BIT_SHIFT_SPEC_SIFS_CCK_8814B)
+#define BITS_SPEC_SIFS_CCK_8814B \
+ (BIT_MASK_SPEC_SIFS_CCK_8814B << BIT_SHIFT_SPEC_SIFS_CCK_8814B)
+#define BIT_CLEAR_SPEC_SIFS_CCK_8814B(x) ((x) & (~BITS_SPEC_SIFS_CCK_8814B))
+#define BIT_GET_SPEC_SIFS_CCK_8814B(x) \
+ (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8814B) & BIT_MASK_SPEC_SIFS_CCK_8814B)
+#define BIT_SET_SPEC_SIFS_CCK_8814B(x, v) \
+ (BIT_CLEAR_SPEC_SIFS_CCK_8814B(x) | BIT_SPEC_SIFS_CCK_8814B(v))
+
+/* 2 REG_RESP_SIFS_CCK_8814B (RESPONSE SIFS FOR CCK REGISTER) */
+
+#define BIT_SHIFT_SIFS_R2T_CCK_8814B 8
+#define BIT_MASK_SIFS_R2T_CCK_8814B 0xff
+#define BIT_SIFS_R2T_CCK_8814B(x) \
+ (((x) & BIT_MASK_SIFS_R2T_CCK_8814B) << BIT_SHIFT_SIFS_R2T_CCK_8814B)
+#define BITS_SIFS_R2T_CCK_8814B \
+ (BIT_MASK_SIFS_R2T_CCK_8814B << BIT_SHIFT_SIFS_R2T_CCK_8814B)
+#define BIT_CLEAR_SIFS_R2T_CCK_8814B(x) ((x) & (~BITS_SIFS_R2T_CCK_8814B))
+#define BIT_GET_SIFS_R2T_CCK_8814B(x) \
+ (((x) >> BIT_SHIFT_SIFS_R2T_CCK_8814B) & BIT_MASK_SIFS_R2T_CCK_8814B)
+#define BIT_SET_SIFS_R2T_CCK_8814B(x, v) \
+ (BIT_CLEAR_SIFS_R2T_CCK_8814B(x) | BIT_SIFS_R2T_CCK_8814B(v))
+
+#define BIT_SHIFT_SIFS_T2T_CCK_8814B 0
+#define BIT_MASK_SIFS_T2T_CCK_8814B 0xff
+#define BIT_SIFS_T2T_CCK_8814B(x) \
+ (((x) & BIT_MASK_SIFS_T2T_CCK_8814B) << BIT_SHIFT_SIFS_T2T_CCK_8814B)
+#define BITS_SIFS_T2T_CCK_8814B \
+ (BIT_MASK_SIFS_T2T_CCK_8814B << BIT_SHIFT_SIFS_T2T_CCK_8814B)
+#define BIT_CLEAR_SIFS_T2T_CCK_8814B(x) ((x) & (~BITS_SIFS_T2T_CCK_8814B))
+#define BIT_GET_SIFS_T2T_CCK_8814B(x) \
+ (((x) >> BIT_SHIFT_SIFS_T2T_CCK_8814B) & BIT_MASK_SIFS_T2T_CCK_8814B)
+#define BIT_SET_SIFS_T2T_CCK_8814B(x, v) \
+ (BIT_CLEAR_SIFS_T2T_CCK_8814B(x) | BIT_SIFS_T2T_CCK_8814B(v))
+
+/* 2 REG_RESP_SIFS_OFDM_8814B (RESPONSE SIFS FOR OFDM REGISTER) */
+
+#define BIT_SHIFT_SIFS_R2T_OFDM_8814B 8
+#define BIT_MASK_SIFS_R2T_OFDM_8814B 0xff
+#define BIT_SIFS_R2T_OFDM_8814B(x) \
+ (((x) & BIT_MASK_SIFS_R2T_OFDM_8814B) << BIT_SHIFT_SIFS_R2T_OFDM_8814B)
+#define BITS_SIFS_R2T_OFDM_8814B \
+ (BIT_MASK_SIFS_R2T_OFDM_8814B << BIT_SHIFT_SIFS_R2T_OFDM_8814B)
+#define BIT_CLEAR_SIFS_R2T_OFDM_8814B(x) ((x) & (~BITS_SIFS_R2T_OFDM_8814B))
+#define BIT_GET_SIFS_R2T_OFDM_8814B(x) \
+ (((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8814B) & BIT_MASK_SIFS_R2T_OFDM_8814B)
+#define BIT_SET_SIFS_R2T_OFDM_8814B(x, v) \
+ (BIT_CLEAR_SIFS_R2T_OFDM_8814B(x) | BIT_SIFS_R2T_OFDM_8814B(v))
+
+#define BIT_SHIFT_SIFS_T2T_OFDM_8814B 0
+#define BIT_MASK_SIFS_T2T_OFDM_8814B 0xff
+#define BIT_SIFS_T2T_OFDM_8814B(x) \
+ (((x) & BIT_MASK_SIFS_T2T_OFDM_8814B) << BIT_SHIFT_SIFS_T2T_OFDM_8814B)
+#define BITS_SIFS_T2T_OFDM_8814B \
+ (BIT_MASK_SIFS_T2T_OFDM_8814B << BIT_SHIFT_SIFS_T2T_OFDM_8814B)
+#define BIT_CLEAR_SIFS_T2T_OFDM_8814B(x) ((x) & (~BITS_SIFS_T2T_OFDM_8814B))
+#define BIT_GET_SIFS_T2T_OFDM_8814B(x) \
+ (((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8814B) & BIT_MASK_SIFS_T2T_OFDM_8814B)
+#define BIT_SET_SIFS_T2T_OFDM_8814B(x, v) \
+ (BIT_CLEAR_SIFS_T2T_OFDM_8814B(x) | BIT_SIFS_T2T_OFDM_8814B(v))
+
+/* 2 REG_ACKTO_8814B (ACK TIMEOUT REGISTER) */
+
+#define BIT_SHIFT_ACKTO_8814B 0
+#define BIT_MASK_ACKTO_8814B 0xff
+#define BIT_ACKTO_8814B(x) \
+ (((x) & BIT_MASK_ACKTO_8814B) << BIT_SHIFT_ACKTO_8814B)
+#define BITS_ACKTO_8814B (BIT_MASK_ACKTO_8814B << BIT_SHIFT_ACKTO_8814B)
+#define BIT_CLEAR_ACKTO_8814B(x) ((x) & (~BITS_ACKTO_8814B))
+#define BIT_GET_ACKTO_8814B(x) \
+ (((x) >> BIT_SHIFT_ACKTO_8814B) & BIT_MASK_ACKTO_8814B)
+#define BIT_SET_ACKTO_8814B(x, v) \
+ (BIT_CLEAR_ACKTO_8814B(x) | BIT_ACKTO_8814B(v))
+
+/* 2 REG_CTS2TO_8814B (CTS2 TIMEOUT REGISTER) */
+
+#define BIT_SHIFT_CTS2TO_8814B 0
+#define BIT_MASK_CTS2TO_8814B 0xff
+#define BIT_CTS2TO_8814B(x) \
+ (((x) & BIT_MASK_CTS2TO_8814B) << BIT_SHIFT_CTS2TO_8814B)
+#define BITS_CTS2TO_8814B (BIT_MASK_CTS2TO_8814B << BIT_SHIFT_CTS2TO_8814B)
+#define BIT_CLEAR_CTS2TO_8814B(x) ((x) & (~BITS_CTS2TO_8814B))
+#define BIT_GET_CTS2TO_8814B(x) \
+ (((x) >> BIT_SHIFT_CTS2TO_8814B) & BIT_MASK_CTS2TO_8814B)
+#define BIT_SET_CTS2TO_8814B(x, v) \
+ (BIT_CLEAR_CTS2TO_8814B(x) | BIT_CTS2TO_8814B(v))
+
+/* 2 REG_EIFS_8814B (EIFS REGISTER) */
+
+#define BIT_SHIFT_EIFS_8814B 0
+#define BIT_MASK_EIFS_8814B 0xffff
+#define BIT_EIFS_8814B(x) (((x) & BIT_MASK_EIFS_8814B) << BIT_SHIFT_EIFS_8814B)
+#define BITS_EIFS_8814B (BIT_MASK_EIFS_8814B << BIT_SHIFT_EIFS_8814B)
+#define BIT_CLEAR_EIFS_8814B(x) ((x) & (~BITS_EIFS_8814B))
+#define BIT_GET_EIFS_8814B(x) \
+ (((x) >> BIT_SHIFT_EIFS_8814B) & BIT_MASK_EIFS_8814B)
+#define BIT_SET_EIFS_8814B(x, v) (BIT_CLEAR_EIFS_8814B(x) | BIT_EIFS_8814B(v))
+
+/* 2 REG_RPFM_MAP0_8814B */
+#define BIT_MGT_RPFM15EN_8814B BIT(15)
+#define BIT_MGT_RPFM14EN_8814B BIT(14)
+#define BIT_MGT_RPFM13EN_8814B BIT(13)
+#define BIT_MGT_RPFM12EN_8814B BIT(12)
+#define BIT_MGT_RPFM11EN_8814B BIT(11)
+#define BIT_MGT_RPFM10EN_8814B BIT(10)
+#define BIT_MGT_RPFM9EN_8814B BIT(9)
+#define BIT_MGT_RPFM8EN_8814B BIT(8)
+#define BIT_MGT_RPFM7EN_8814B BIT(7)
+#define BIT_MGT_RPFM6EN_8814B BIT(6)
+#define BIT_MGT_RPFM5EN_8814B BIT(5)
+#define BIT_MGT_RPFM4EN_8814B BIT(4)
+#define BIT_MGT_RPFM3EN_8814B BIT(3)
+#define BIT_MGT_RPFM2EN_8814B BIT(2)
+#define BIT_MGT_RPFM1EN_8814B BIT(1)
+#define BIT_MGT_RPFM0EN_8814B BIT(0)
+
+/* 2 REG_RPFM_MAP1_V1_8814B */
+#define BIT_DATA_RPFM15EN_8814B BIT(15)
+#define BIT_DATA_RPFM14EN_8814B BIT(14)
+#define BIT_DATA_RPFM13EN_8814B BIT(13)
+#define BIT_DATA_RPFM12EN_8814B BIT(12)
+#define BIT_DATA_RPFM11EN_8814B BIT(11)
+#define BIT_DATA_RPFM10EN_8814B BIT(10)
+#define BIT_DATA_RPFM9EN_8814B BIT(9)
+#define BIT_DATA_RPFM8EN_8814B BIT(8)
+#define BIT_DATA_RPFM7EN_8814B BIT(7)
+#define BIT_DATA_RPFM6EN_8814B BIT(6)
+#define BIT_DATA_RPFM5EN_8814B BIT(5)
+#define BIT_DATA_RPFM4EN_8814B BIT(4)
+#define BIT_DATA_RPFM3EN_8814B BIT(3)
+#define BIT_DATA_RPFM2EN_8814B BIT(2)
+#define BIT_DATA_RPFM1EN_8814B BIT(1)
+#define BIT_DATA_RPFM0EN_8814B BIT(0)
+
+/* 2 REG_RPFM_CAM_CMD_8814B (RX PAYLOAD FRAME MASK CAM COMMAND REGISTER) */
+#define BIT_RPFM_CAM_POLLING_8814B BIT(31)
+#define BIT_RPFM_CAM_CLR_8814B BIT(30)
+#define BIT_RPFM_CAM_WE_8814B BIT(16)
+
+#define BIT_SHIFT_RPFM_CAM_ADDR_8814B 0
+#define BIT_MASK_RPFM_CAM_ADDR_8814B 0x7f
+#define BIT_RPFM_CAM_ADDR_8814B(x) \
+ (((x) & BIT_MASK_RPFM_CAM_ADDR_8814B) << BIT_SHIFT_RPFM_CAM_ADDR_8814B)
+#define BITS_RPFM_CAM_ADDR_8814B \
+ (BIT_MASK_RPFM_CAM_ADDR_8814B << BIT_SHIFT_RPFM_CAM_ADDR_8814B)
+#define BIT_CLEAR_RPFM_CAM_ADDR_8814B(x) ((x) & (~BITS_RPFM_CAM_ADDR_8814B))
+#define BIT_GET_RPFM_CAM_ADDR_8814B(x) \
+ (((x) >> BIT_SHIFT_RPFM_CAM_ADDR_8814B) & BIT_MASK_RPFM_CAM_ADDR_8814B)
+#define BIT_SET_RPFM_CAM_ADDR_8814B(x, v) \
+ (BIT_CLEAR_RPFM_CAM_ADDR_8814B(x) | BIT_RPFM_CAM_ADDR_8814B(v))
+
+/* 2 REG_RPFM_CAM_RWD_8814B (ACK TIMEOUT REGISTER) */
+
+#define BIT_SHIFT_RPFM_CAM_RWD_8814B 0
+#define BIT_MASK_RPFM_CAM_RWD_8814B 0xffffffffL
+#define BIT_RPFM_CAM_RWD_8814B(x) \
+ (((x) & BIT_MASK_RPFM_CAM_RWD_8814B) << BIT_SHIFT_RPFM_CAM_RWD_8814B)
+#define BITS_RPFM_CAM_RWD_8814B \
+ (BIT_MASK_RPFM_CAM_RWD_8814B << BIT_SHIFT_RPFM_CAM_RWD_8814B)
+#define BIT_CLEAR_RPFM_CAM_RWD_8814B(x) ((x) & (~BITS_RPFM_CAM_RWD_8814B))
+#define BIT_GET_RPFM_CAM_RWD_8814B(x) \
+ (((x) >> BIT_SHIFT_RPFM_CAM_RWD_8814B) & BIT_MASK_RPFM_CAM_RWD_8814B)
+#define BIT_SET_RPFM_CAM_RWD_8814B(x, v) \
+ (BIT_CLEAR_RPFM_CAM_RWD_8814B(x) | BIT_RPFM_CAM_RWD_8814B(v))
+
+/* 2 REG_NAV_CTRL_8814B (NAV CONTROL REGISTER) */
+
+#define BIT_SHIFT_NAV_UPPER_8814B 16
+#define BIT_MASK_NAV_UPPER_8814B 0xff
+#define BIT_NAV_UPPER_8814B(x) \
+ (((x) & BIT_MASK_NAV_UPPER_8814B) << BIT_SHIFT_NAV_UPPER_8814B)
+#define BITS_NAV_UPPER_8814B \
+ (BIT_MASK_NAV_UPPER_8814B << BIT_SHIFT_NAV_UPPER_8814B)
+#define BIT_CLEAR_NAV_UPPER_8814B(x) ((x) & (~BITS_NAV_UPPER_8814B))
+#define BIT_GET_NAV_UPPER_8814B(x) \
+ (((x) >> BIT_SHIFT_NAV_UPPER_8814B) & BIT_MASK_NAV_UPPER_8814B)
+#define BIT_SET_NAV_UPPER_8814B(x, v) \
+ (BIT_CLEAR_NAV_UPPER_8814B(x) | BIT_NAV_UPPER_8814B(v))
+
+#define BIT_SHIFT_RXMYRTS_NAV_8814B 8
+#define BIT_MASK_RXMYRTS_NAV_8814B 0xf
+#define BIT_RXMYRTS_NAV_8814B(x) \
+ (((x) & BIT_MASK_RXMYRTS_NAV_8814B) << BIT_SHIFT_RXMYRTS_NAV_8814B)
+#define BITS_RXMYRTS_NAV_8814B \
+ (BIT_MASK_RXMYRTS_NAV_8814B << BIT_SHIFT_RXMYRTS_NAV_8814B)
+#define BIT_CLEAR_RXMYRTS_NAV_8814B(x) ((x) & (~BITS_RXMYRTS_NAV_8814B))
+#define BIT_GET_RXMYRTS_NAV_8814B(x) \
+ (((x) >> BIT_SHIFT_RXMYRTS_NAV_8814B) & BIT_MASK_RXMYRTS_NAV_8814B)
+#define BIT_SET_RXMYRTS_NAV_8814B(x, v) \
+ (BIT_CLEAR_RXMYRTS_NAV_8814B(x) | BIT_RXMYRTS_NAV_8814B(v))
+
+#define BIT_SHIFT_RTSRST_8814B 0
+#define BIT_MASK_RTSRST_8814B 0xff
+#define BIT_RTSRST_8814B(x) \
+ (((x) & BIT_MASK_RTSRST_8814B) << BIT_SHIFT_RTSRST_8814B)
+#define BITS_RTSRST_8814B (BIT_MASK_RTSRST_8814B << BIT_SHIFT_RTSRST_8814B)
+#define BIT_CLEAR_RTSRST_8814B(x) ((x) & (~BITS_RTSRST_8814B))
+#define BIT_GET_RTSRST_8814B(x) \
+ (((x) >> BIT_SHIFT_RTSRST_8814B) & BIT_MASK_RTSRST_8814B)
+#define BIT_SET_RTSRST_8814B(x, v) \
+ (BIT_CLEAR_RTSRST_8814B(x) | BIT_RTSRST_8814B(v))
+
+/* 2 REG_BACAMCMD_8814B (BLOCK ACK CAM COMMAND REGISTER) */
+#define BIT_BACAM_POLL_8814B BIT(31)
+#define BIT_BACAM_RST_8814B BIT(17)
+#define BIT_BACAM_RW_8814B BIT(16)
+
+#define BIT_SHIFT_TXSBM_8814B 14
+#define BIT_MASK_TXSBM_8814B 0x3
+#define BIT_TXSBM_8814B(x) \
+ (((x) & BIT_MASK_TXSBM_8814B) << BIT_SHIFT_TXSBM_8814B)
+#define BITS_TXSBM_8814B (BIT_MASK_TXSBM_8814B << BIT_SHIFT_TXSBM_8814B)
+#define BIT_CLEAR_TXSBM_8814B(x) ((x) & (~BITS_TXSBM_8814B))
+#define BIT_GET_TXSBM_8814B(x) \
+ (((x) >> BIT_SHIFT_TXSBM_8814B) & BIT_MASK_TXSBM_8814B)
+#define BIT_SET_TXSBM_8814B(x, v) \
+ (BIT_CLEAR_TXSBM_8814B(x) | BIT_TXSBM_8814B(v))
+
+#define BIT_SHIFT_BACAM_ADDR_8814B 0
+#define BIT_MASK_BACAM_ADDR_8814B 0x3f
+#define BIT_BACAM_ADDR_8814B(x) \
+ (((x) & BIT_MASK_BACAM_ADDR_8814B) << BIT_SHIFT_BACAM_ADDR_8814B)
+#define BITS_BACAM_ADDR_8814B \
+ (BIT_MASK_BACAM_ADDR_8814B << BIT_SHIFT_BACAM_ADDR_8814B)
+#define BIT_CLEAR_BACAM_ADDR_8814B(x) ((x) & (~BITS_BACAM_ADDR_8814B))
+#define BIT_GET_BACAM_ADDR_8814B(x) \
+ (((x) >> BIT_SHIFT_BACAM_ADDR_8814B) & BIT_MASK_BACAM_ADDR_8814B)
+#define BIT_SET_BACAM_ADDR_8814B(x, v) \
+ (BIT_CLEAR_BACAM_ADDR_8814B(x) | BIT_BACAM_ADDR_8814B(v))
+
+/* 2 REG_BACAMCONTENT_8814B (BLOCK ACK CAM CONTENT REGISTER) */
+
+#define BIT_SHIFT_BA_CONTENT_L_8814B 0
+#define BIT_MASK_BA_CONTENT_L_8814B 0xffffffffL
+#define BIT_BA_CONTENT_L_8814B(x) \
+ (((x) & BIT_MASK_BA_CONTENT_L_8814B) << BIT_SHIFT_BA_CONTENT_L_8814B)
+#define BITS_BA_CONTENT_L_8814B \
+ (BIT_MASK_BA_CONTENT_L_8814B << BIT_SHIFT_BA_CONTENT_L_8814B)
+#define BIT_CLEAR_BA_CONTENT_L_8814B(x) ((x) & (~BITS_BA_CONTENT_L_8814B))
+#define BIT_GET_BA_CONTENT_L_8814B(x) \
+ (((x) >> BIT_SHIFT_BA_CONTENT_L_8814B) & BIT_MASK_BA_CONTENT_L_8814B)
+#define BIT_SET_BA_CONTENT_L_8814B(x, v) \
+ (BIT_CLEAR_BA_CONTENT_L_8814B(x) | BIT_BA_CONTENT_L_8814B(v))
+
+/* 2 REG_BACAMCONTENT_H_8814B (BLOCK ACK CAM CONTENT REGISTER) */
+
+#define BIT_SHIFT_BA_CONTENT_H_8814B 0
+#define BIT_MASK_BA_CONTENT_H_8814B 0xffffffffL
+#define BIT_BA_CONTENT_H_8814B(x) \
+ (((x) & BIT_MASK_BA_CONTENT_H_8814B) << BIT_SHIFT_BA_CONTENT_H_8814B)
+#define BITS_BA_CONTENT_H_8814B \
+ (BIT_MASK_BA_CONTENT_H_8814B << BIT_SHIFT_BA_CONTENT_H_8814B)
+#define BIT_CLEAR_BA_CONTENT_H_8814B(x) ((x) & (~BITS_BA_CONTENT_H_8814B))
+#define BIT_GET_BA_CONTENT_H_8814B(x) \
+ (((x) >> BIT_SHIFT_BA_CONTENT_H_8814B) & BIT_MASK_BA_CONTENT_H_8814B)
+#define BIT_SET_BA_CONTENT_H_8814B(x, v) \
+ (BIT_CLEAR_BA_CONTENT_H_8814B(x) | BIT_BA_CONTENT_H_8814B(v))
+
+/* 2 REG_LBDLY_8814B (LOOPBACK DELAY REGISTER) */
+
+#define BIT_SHIFT_LBDLY_8814B 0
+#define BIT_MASK_LBDLY_8814B 0x1f
+#define BIT_LBDLY_8814B(x) \
+ (((x) & BIT_MASK_LBDLY_8814B) << BIT_SHIFT_LBDLY_8814B)
+#define BITS_LBDLY_8814B (BIT_MASK_LBDLY_8814B << BIT_SHIFT_LBDLY_8814B)
+#define BIT_CLEAR_LBDLY_8814B(x) ((x) & (~BITS_LBDLY_8814B))
+#define BIT_GET_LBDLY_8814B(x) \
+ (((x) >> BIT_SHIFT_LBDLY_8814B) & BIT_MASK_LBDLY_8814B)
+#define BIT_SET_LBDLY_8814B(x, v) \
+ (BIT_CLEAR_LBDLY_8814B(x) | BIT_LBDLY_8814B(v))
+
+/* 2 REG_WMAC_BACAM_RPMEN_8814B */
+
+#define BIT_SHIFT_BITMAP_SSNBK_COUNTER_8814B 2
+#define BIT_MASK_BITMAP_SSNBK_COUNTER_8814B 0x3f
+#define BIT_BITMAP_SSNBK_COUNTER_8814B(x) \
+ (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8814B) \
+ << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8814B)
+#define BITS_BITMAP_SSNBK_COUNTER_8814B \
+ (BIT_MASK_BITMAP_SSNBK_COUNTER_8814B \
+ << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8814B)
+#define BIT_CLEAR_BITMAP_SSNBK_COUNTER_8814B(x) \
+ ((x) & (~BITS_BITMAP_SSNBK_COUNTER_8814B))
+#define BIT_GET_BITMAP_SSNBK_COUNTER_8814B(x) \
+ (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8814B) & \
+ BIT_MASK_BITMAP_SSNBK_COUNTER_8814B)
+#define BIT_SET_BITMAP_SSNBK_COUNTER_8814B(x, v) \
+ (BIT_CLEAR_BITMAP_SSNBK_COUNTER_8814B(x) | \
+ BIT_BITMAP_SSNBK_COUNTER_8814B(v))
+
+#define BIT_BITMAP_EN_8814B BIT(1)
+#define BIT_WMAC_BACAM_RPMEN_8814B BIT(0)
+
+/* 2 REG_TX_RX_8814B STATUS */
+
+#define BIT_SHIFT_RXPKT_TYPE_8814B 2
+#define BIT_MASK_RXPKT_TYPE_8814B 0x3f
+#define BIT_RXPKT_TYPE_8814B(x) \
+ (((x) & BIT_MASK_RXPKT_TYPE_8814B) << BIT_SHIFT_RXPKT_TYPE_8814B)
+#define BITS_RXPKT_TYPE_8814B \
+ (BIT_MASK_RXPKT_TYPE_8814B << BIT_SHIFT_RXPKT_TYPE_8814B)
+#define BIT_CLEAR_RXPKT_TYPE_8814B(x) ((x) & (~BITS_RXPKT_TYPE_8814B))
+#define BIT_GET_RXPKT_TYPE_8814B(x) \
+ (((x) >> BIT_SHIFT_RXPKT_TYPE_8814B) & BIT_MASK_RXPKT_TYPE_8814B)
+#define BIT_SET_RXPKT_TYPE_8814B(x, v) \
+ (BIT_CLEAR_RXPKT_TYPE_8814B(x) | BIT_RXPKT_TYPE_8814B(v))
+
+#define BIT_TXACT_IND_8814B BIT(1)
+#define BIT_RXACT_IND_8814B BIT(0)
+
+/* 2 REG_WMAC_BITMAP_CTL_8814B */
+#define BIT_BITMAP_VO_8814B BIT(7)
+#define BIT_BITMAP_VI_8814B BIT(6)
+#define BIT_BITMAP_BE_8814B BIT(5)
+#define BIT_BITMAP_BK_8814B BIT(4)
+
+#define BIT_SHIFT_BITMAP_CONDITION_8814B 2
+#define BIT_MASK_BITMAP_CONDITION_8814B 0x3
+#define BIT_BITMAP_CONDITION_8814B(x) \
+ (((x) & BIT_MASK_BITMAP_CONDITION_8814B) \
+ << BIT_SHIFT_BITMAP_CONDITION_8814B)
+#define BITS_BITMAP_CONDITION_8814B \
+ (BIT_MASK_BITMAP_CONDITION_8814B << BIT_SHIFT_BITMAP_CONDITION_8814B)
+#define BIT_CLEAR_BITMAP_CONDITION_8814B(x) \
+ ((x) & (~BITS_BITMAP_CONDITION_8814B))
+#define BIT_GET_BITMAP_CONDITION_8814B(x) \
+ (((x) >> BIT_SHIFT_BITMAP_CONDITION_8814B) & \
+ BIT_MASK_BITMAP_CONDITION_8814B)
+#define BIT_SET_BITMAP_CONDITION_8814B(x, v) \
+ (BIT_CLEAR_BITMAP_CONDITION_8814B(x) | BIT_BITMAP_CONDITION_8814B(v))
+
+#define BIT_BITMAP_SSNBK_COUNTER_CLR_8814B BIT(1)
+#define BIT_BITMAP_FORCE_8814B BIT(0)
+
+/* 2 REG_RXERR_RPT_8814B (RX ERROR REPORT REGISTER) */
+
+#define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8814B 28
+#define BIT_MASK_RXERR_RPT_SEL_V1_3_0_8814B 0xf
+#define BIT_RXERR_RPT_SEL_V1_3_0_8814B(x) \
+ (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8814B) \
+ << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8814B)
+#define BITS_RXERR_RPT_SEL_V1_3_0_8814B \
+ (BIT_MASK_RXERR_RPT_SEL_V1_3_0_8814B \
+ << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8814B)
+#define BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8814B(x) \
+ ((x) & (~BITS_RXERR_RPT_SEL_V1_3_0_8814B))
+#define BIT_GET_RXERR_RPT_SEL_V1_3_0_8814B(x) \
+ (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8814B) & \
+ BIT_MASK_RXERR_RPT_SEL_V1_3_0_8814B)
+#define BIT_SET_RXERR_RPT_SEL_V1_3_0_8814B(x, v) \
+ (BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8814B(x) | \
+ BIT_RXERR_RPT_SEL_V1_3_0_8814B(v))
+
+#define BIT_RXERR_RPT_RST_8814B BIT(27)
+#define BIT_RXERR_RPT_SEL_V1_4_8814B BIT(26)
+#define BIT_W1S_8814B BIT(23)
+#define BIT_UD_SELECT_BSSID_8814B BIT(22)
+
+#define BIT_SHIFT_UD_SUB_TYPE_8814B 18
+#define BIT_MASK_UD_SUB_TYPE_8814B 0xf
+#define BIT_UD_SUB_TYPE_8814B(x) \
+ (((x) & BIT_MASK_UD_SUB_TYPE_8814B) << BIT_SHIFT_UD_SUB_TYPE_8814B)
+#define BITS_UD_SUB_TYPE_8814B \
+ (BIT_MASK_UD_SUB_TYPE_8814B << BIT_SHIFT_UD_SUB_TYPE_8814B)
+#define BIT_CLEAR_UD_SUB_TYPE_8814B(x) ((x) & (~BITS_UD_SUB_TYPE_8814B))
+#define BIT_GET_UD_SUB_TYPE_8814B(x) \
+ (((x) >> BIT_SHIFT_UD_SUB_TYPE_8814B) & BIT_MASK_UD_SUB_TYPE_8814B)
+#define BIT_SET_UD_SUB_TYPE_8814B(x, v) \
+ (BIT_CLEAR_UD_SUB_TYPE_8814B(x) | BIT_UD_SUB_TYPE_8814B(v))
+
+#define BIT_SHIFT_UD_TYPE_8814B 16
+#define BIT_MASK_UD_TYPE_8814B 0x3
+#define BIT_UD_TYPE_8814B(x) \
+ (((x) & BIT_MASK_UD_TYPE_8814B) << BIT_SHIFT_UD_TYPE_8814B)
+#define BITS_UD_TYPE_8814B (BIT_MASK_UD_TYPE_8814B << BIT_SHIFT_UD_TYPE_8814B)
+#define BIT_CLEAR_UD_TYPE_8814B(x) ((x) & (~BITS_UD_TYPE_8814B))
+#define BIT_GET_UD_TYPE_8814B(x) \
+ (((x) >> BIT_SHIFT_UD_TYPE_8814B) & BIT_MASK_UD_TYPE_8814B)
+#define BIT_SET_UD_TYPE_8814B(x, v) \
+ (BIT_CLEAR_UD_TYPE_8814B(x) | BIT_UD_TYPE_8814B(v))
+
+#define BIT_SHIFT_RPT_COUNTER_8814B 0
+#define BIT_MASK_RPT_COUNTER_8814B 0xffff
+#define BIT_RPT_COUNTER_8814B(x) \
+ (((x) & BIT_MASK_RPT_COUNTER_8814B) << BIT_SHIFT_RPT_COUNTER_8814B)
+#define BITS_RPT_COUNTER_8814B \
+ (BIT_MASK_RPT_COUNTER_8814B << BIT_SHIFT_RPT_COUNTER_8814B)
+#define BIT_CLEAR_RPT_COUNTER_8814B(x) ((x) & (~BITS_RPT_COUNTER_8814B))
+#define BIT_GET_RPT_COUNTER_8814B(x) \
+ (((x) >> BIT_SHIFT_RPT_COUNTER_8814B) & BIT_MASK_RPT_COUNTER_8814B)
+#define BIT_SET_RPT_COUNTER_8814B(x, v) \
+ (BIT_CLEAR_RPT_COUNTER_8814B(x) | BIT_RPT_COUNTER_8814B(v))
+
+/* 2 REG_WMAC_TRXPTCL_CTL_8814B (WMAC TX/RX PROTOCOL CONTROL REGISTER) */
+#define BIT_EN_TXCTS_INTXOP_8814B BIT(32)
+#define BIT_BLK_EDCA_BBSLP_8814B BIT(31)
+#define BIT_BLK_EDCA_BBSBY_8814B BIT(30)
+#define BIT_ACKTO_BLOCK_SCH_EN_8814B BIT(27)
+#define BIT_EIFS_BLOCK_SCH_EN_8814B BIT(26)
+#define BIT_PLCPCHK_RST_EIFS_8814B BIT(25)
+#define BIT_CCA_RST_EIFS_8814B BIT(24)
+#define BIT_DIS_UPD_MYRXPKTNAV_8814B BIT(23)
+#define BIT_EARLY_TXBA_8814B BIT(22)
+
+#define BIT_SHIFT_RESP_CHNBUSY_8814B 20
+#define BIT_MASK_RESP_CHNBUSY_8814B 0x3
+#define BIT_RESP_CHNBUSY_8814B(x) \
+ (((x) & BIT_MASK_RESP_CHNBUSY_8814B) << BIT_SHIFT_RESP_CHNBUSY_8814B)
+#define BITS_RESP_CHNBUSY_8814B \
+ (BIT_MASK_RESP_CHNBUSY_8814B << BIT_SHIFT_RESP_CHNBUSY_8814B)
+#define BIT_CLEAR_RESP_CHNBUSY_8814B(x) ((x) & (~BITS_RESP_CHNBUSY_8814B))
+#define BIT_GET_RESP_CHNBUSY_8814B(x) \
+ (((x) >> BIT_SHIFT_RESP_CHNBUSY_8814B) & BIT_MASK_RESP_CHNBUSY_8814B)
+#define BIT_SET_RESP_CHNBUSY_8814B(x, v) \
+ (BIT_CLEAR_RESP_CHNBUSY_8814B(x) | BIT_RESP_CHNBUSY_8814B(v))
+
+#define BIT_RESP_DCTS_EN_8814B BIT(19)
+#define BIT_RESP_DCFE_EN_8814B BIT(18)
+#define BIT_RESP_SPLCPEN_8814B BIT(17)
+#define BIT_RESP_SGIEN_8814B BIT(16)
+#define BIT_RESP_LDPC_EN_8814B BIT(15)
+#define BIT_DIS_RESP_ACKINCCA_8814B BIT(14)
+#define BIT_DIS_RESP_CTSINCCA_8814B BIT(13)
+
+#define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8814B 10
+#define BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8814B 0x7
+#define BIT_R_WMAC_SECOND_CCA_TIMER_8814B(x) \
+ (((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8814B) \
+ << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8814B)
+#define BITS_R_WMAC_SECOND_CCA_TIMER_8814B \
+ (BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8814B \
+ << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8814B)
+#define BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8814B(x) \
+ ((x) & (~BITS_R_WMAC_SECOND_CCA_TIMER_8814B))
+#define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8814B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8814B) & \
+ BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8814B)
+#define BIT_SET_R_WMAC_SECOND_CCA_TIMER_8814B(x, v) \
+ (BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8814B(x) | \
+ BIT_R_WMAC_SECOND_CCA_TIMER_8814B(v))
+
+#define BIT_SHIFT_RFMOD_8814B 7
+#define BIT_MASK_RFMOD_8814B 0x3
+#define BIT_RFMOD_8814B(x) \
+ (((x) & BIT_MASK_RFMOD_8814B) << BIT_SHIFT_RFMOD_8814B)
+#define BITS_RFMOD_8814B (BIT_MASK_RFMOD_8814B << BIT_SHIFT_RFMOD_8814B)
+#define BIT_CLEAR_RFMOD_8814B(x) ((x) & (~BITS_RFMOD_8814B))
+#define BIT_GET_RFMOD_8814B(x) \
+ (((x) >> BIT_SHIFT_RFMOD_8814B) & BIT_MASK_RFMOD_8814B)
+#define BIT_SET_RFMOD_8814B(x, v) \
+ (BIT_CLEAR_RFMOD_8814B(x) | BIT_RFMOD_8814B(v))
+
+#define BIT_SHIFT_RESP_CTS_DYNBW_SEL_8814B 5
+#define BIT_MASK_RESP_CTS_DYNBW_SEL_8814B 0x3
+#define BIT_RESP_CTS_DYNBW_SEL_8814B(x) \
+ (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8814B) \
+ << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8814B)
+#define BITS_RESP_CTS_DYNBW_SEL_8814B \
+ (BIT_MASK_RESP_CTS_DYNBW_SEL_8814B \
+ << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8814B)
+#define BIT_CLEAR_RESP_CTS_DYNBW_SEL_8814B(x) \
+ ((x) & (~BITS_RESP_CTS_DYNBW_SEL_8814B))
+#define BIT_GET_RESP_CTS_DYNBW_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8814B) & \
+ BIT_MASK_RESP_CTS_DYNBW_SEL_8814B)
+#define BIT_SET_RESP_CTS_DYNBW_SEL_8814B(x, v) \
+ (BIT_CLEAR_RESP_CTS_DYNBW_SEL_8814B(x) | \
+ BIT_RESP_CTS_DYNBW_SEL_8814B(v))
+
+#define BIT_DLY_TX_WAIT_RXANTSEL_8814B BIT(4)
+#define BIT_TXRESP_BY_RXANTSEL_8814B BIT(3)
+
+#define BIT_SHIFT_ORIG_DCTS_CHK_8814B 0
+#define BIT_MASK_ORIG_DCTS_CHK_8814B 0x3
+#define BIT_ORIG_DCTS_CHK_8814B(x) \
+ (((x) & BIT_MASK_ORIG_DCTS_CHK_8814B) << BIT_SHIFT_ORIG_DCTS_CHK_8814B)
+#define BITS_ORIG_DCTS_CHK_8814B \
+ (BIT_MASK_ORIG_DCTS_CHK_8814B << BIT_SHIFT_ORIG_DCTS_CHK_8814B)
+#define BIT_CLEAR_ORIG_DCTS_CHK_8814B(x) ((x) & (~BITS_ORIG_DCTS_CHK_8814B))
+#define BIT_GET_ORIG_DCTS_CHK_8814B(x) \
+ (((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8814B) & BIT_MASK_ORIG_DCTS_CHK_8814B)
+#define BIT_SET_ORIG_DCTS_CHK_8814B(x, v) \
+ (BIT_CLEAR_ORIG_DCTS_CHK_8814B(x) | BIT_ORIG_DCTS_CHK_8814B(v))
+
+/* 2 REG_WMAC_TRXPTCL_CTL_H_8814B */
+
+#define BIT_SHIFT_ACKBA_TYPSEL_8814B 28
+#define BIT_MASK_ACKBA_TYPSEL_8814B 0xf
+#define BIT_ACKBA_TYPSEL_8814B(x) \
+ (((x) & BIT_MASK_ACKBA_TYPSEL_8814B) << BIT_SHIFT_ACKBA_TYPSEL_8814B)
+#define BITS_ACKBA_TYPSEL_8814B \
+ (BIT_MASK_ACKBA_TYPSEL_8814B << BIT_SHIFT_ACKBA_TYPSEL_8814B)
+#define BIT_CLEAR_ACKBA_TYPSEL_8814B(x) ((x) & (~BITS_ACKBA_TYPSEL_8814B))
+#define BIT_GET_ACKBA_TYPSEL_8814B(x) \
+ (((x) >> BIT_SHIFT_ACKBA_TYPSEL_8814B) & BIT_MASK_ACKBA_TYPSEL_8814B)
+#define BIT_SET_ACKBA_TYPSEL_8814B(x, v) \
+ (BIT_CLEAR_ACKBA_TYPSEL_8814B(x) | BIT_ACKBA_TYPSEL_8814B(v))
+
+#define BIT_SHIFT_ACKBA_ACKPCHK_8814B 24
+#define BIT_MASK_ACKBA_ACKPCHK_8814B 0xf
+#define BIT_ACKBA_ACKPCHK_8814B(x) \
+ (((x) & BIT_MASK_ACKBA_ACKPCHK_8814B) << BIT_SHIFT_ACKBA_ACKPCHK_8814B)
+#define BITS_ACKBA_ACKPCHK_8814B \
+ (BIT_MASK_ACKBA_ACKPCHK_8814B << BIT_SHIFT_ACKBA_ACKPCHK_8814B)
+#define BIT_CLEAR_ACKBA_ACKPCHK_8814B(x) ((x) & (~BITS_ACKBA_ACKPCHK_8814B))
+#define BIT_GET_ACKBA_ACKPCHK_8814B(x) \
+ (((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8814B) & BIT_MASK_ACKBA_ACKPCHK_8814B)
+#define BIT_SET_ACKBA_ACKPCHK_8814B(x, v) \
+ (BIT_CLEAR_ACKBA_ACKPCHK_8814B(x) | BIT_ACKBA_ACKPCHK_8814B(v))
+
+#define BIT_SHIFT_ACKBAR_TYPESEL_8814B 16
+#define BIT_MASK_ACKBAR_TYPESEL_8814B 0xff
+#define BIT_ACKBAR_TYPESEL_8814B(x) \
+ (((x) & BIT_MASK_ACKBAR_TYPESEL_8814B) \
+ << BIT_SHIFT_ACKBAR_TYPESEL_8814B)
+#define BITS_ACKBAR_TYPESEL_8814B \
+ (BIT_MASK_ACKBAR_TYPESEL_8814B << BIT_SHIFT_ACKBAR_TYPESEL_8814B)
+#define BIT_CLEAR_ACKBAR_TYPESEL_8814B(x) ((x) & (~BITS_ACKBAR_TYPESEL_8814B))
+#define BIT_GET_ACKBAR_TYPESEL_8814B(x) \
+ (((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8814B) & \
+ BIT_MASK_ACKBAR_TYPESEL_8814B)
+#define BIT_SET_ACKBAR_TYPESEL_8814B(x, v) \
+ (BIT_CLEAR_ACKBAR_TYPESEL_8814B(x) | BIT_ACKBAR_TYPESEL_8814B(v))
+
+#define BIT_SHIFT_ACKBAR_ACKPCHK_8814B 12
+#define BIT_MASK_ACKBAR_ACKPCHK_8814B 0xf
+#define BIT_ACKBAR_ACKPCHK_8814B(x) \
+ (((x) & BIT_MASK_ACKBAR_ACKPCHK_8814B) \
+ << BIT_SHIFT_ACKBAR_ACKPCHK_8814B)
+#define BITS_ACKBAR_ACKPCHK_8814B \
+ (BIT_MASK_ACKBAR_ACKPCHK_8814B << BIT_SHIFT_ACKBAR_ACKPCHK_8814B)
+#define BIT_CLEAR_ACKBAR_ACKPCHK_8814B(x) ((x) & (~BITS_ACKBAR_ACKPCHK_8814B))
+#define BIT_GET_ACKBAR_ACKPCHK_8814B(x) \
+ (((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8814B) & \
+ BIT_MASK_ACKBAR_ACKPCHK_8814B)
+#define BIT_SET_ACKBAR_ACKPCHK_8814B(x, v) \
+ (BIT_CLEAR_ACKBAR_ACKPCHK_8814B(x) | BIT_ACKBAR_ACKPCHK_8814B(v))
+
+#define BIT_RXBA_IGNOREA2_V1_8814B BIT(10)
+#define BIT_EN_SAVE_ALL_TXOPADDR_V1_8814B BIT(9)
+#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV_V1_8814B BIT(8)
+#define BIT_DIS_TXBA_AMPDUFCSERR_V1_8814B BIT(7)
+#define BIT_DIS_TXBA_RXBARINFULL_V1_8814B BIT(6)
+#define BIT_DIS_TXCFE_INFULL_V1_8814B BIT(5)
+#define BIT_DIS_TXCTS_INFULL_V1_8814B BIT(4)
+#define BIT_EN_TXACKBA_IN_TX_RDG_V1_8814B BIT(3)
+#define BIT_EN_TXACKBA_IN_TXOP_V1_8814B BIT(2)
+#define BIT_EN_TXCTS_IN_RXNAV_V1_8814B BIT(1)
+#define BIT_EN_TXCTS_INTXOP_V1_8814B BIT(0)
+
+/* 2 REG_CAMCMD_8814B (CAM COMMAND REGISTER) */
+#define BIT_SECCAM_POLLING_8814B BIT(31)
+#define BIT_SECCAM_CLR_8814B BIT(30)
+#define BIT_SECCAM_WE_8814B BIT(16)
+
+#define BIT_SHIFT_SECCAM_ADDR_V2_8814B 0
+#define BIT_MASK_SECCAM_ADDR_V2_8814B 0x3ff
+#define BIT_SECCAM_ADDR_V2_8814B(x) \
+ (((x) & BIT_MASK_SECCAM_ADDR_V2_8814B) \
+ << BIT_SHIFT_SECCAM_ADDR_V2_8814B)
+#define BITS_SECCAM_ADDR_V2_8814B \
+ (BIT_MASK_SECCAM_ADDR_V2_8814B << BIT_SHIFT_SECCAM_ADDR_V2_8814B)
+#define BIT_CLEAR_SECCAM_ADDR_V2_8814B(x) ((x) & (~BITS_SECCAM_ADDR_V2_8814B))
+#define BIT_GET_SECCAM_ADDR_V2_8814B(x) \
+ (((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8814B) & \
+ BIT_MASK_SECCAM_ADDR_V2_8814B)
+#define BIT_SET_SECCAM_ADDR_V2_8814B(x, v) \
+ (BIT_CLEAR_SECCAM_ADDR_V2_8814B(x) | BIT_SECCAM_ADDR_V2_8814B(v))
+
+/* 2 REG_CAMWRITE_8814B (CAM WRITE REGISTER) */
+
+#define BIT_SHIFT_CAMW_DATA_8814B 0
+#define BIT_MASK_CAMW_DATA_8814B 0xffffffffL
+#define BIT_CAMW_DATA_8814B(x) \
+ (((x) & BIT_MASK_CAMW_DATA_8814B) << BIT_SHIFT_CAMW_DATA_8814B)
+#define BITS_CAMW_DATA_8814B \
+ (BIT_MASK_CAMW_DATA_8814B << BIT_SHIFT_CAMW_DATA_8814B)
+#define BIT_CLEAR_CAMW_DATA_8814B(x) ((x) & (~BITS_CAMW_DATA_8814B))
+#define BIT_GET_CAMW_DATA_8814B(x) \
+ (((x) >> BIT_SHIFT_CAMW_DATA_8814B) & BIT_MASK_CAMW_DATA_8814B)
+#define BIT_SET_CAMW_DATA_8814B(x, v) \
+ (BIT_CLEAR_CAMW_DATA_8814B(x) | BIT_CAMW_DATA_8814B(v))
+
+/* 2 REG_CAMREAD_8814B (CAM READ REGISTER) */
+
+#define BIT_SHIFT_CAMR_DATA_8814B 0
+#define BIT_MASK_CAMR_DATA_8814B 0xffffffffL
+#define BIT_CAMR_DATA_8814B(x) \
+ (((x) & BIT_MASK_CAMR_DATA_8814B) << BIT_SHIFT_CAMR_DATA_8814B)
+#define BITS_CAMR_DATA_8814B \
+ (BIT_MASK_CAMR_DATA_8814B << BIT_SHIFT_CAMR_DATA_8814B)
+#define BIT_CLEAR_CAMR_DATA_8814B(x) ((x) & (~BITS_CAMR_DATA_8814B))
+#define BIT_GET_CAMR_DATA_8814B(x) \
+ (((x) >> BIT_SHIFT_CAMR_DATA_8814B) & BIT_MASK_CAMR_DATA_8814B)
+#define BIT_SET_CAMR_DATA_8814B(x, v) \
+ (BIT_CLEAR_CAMR_DATA_8814B(x) | BIT_CAMR_DATA_8814B(v))
+
+/* 2 REG_CAMDBG_8814B (CAM DEBUG REGISTER) */
+#define BIT_SECCAM_INFO_8814B BIT(31)
+#define BIT_SEC_KEYFOUND_8814B BIT(15)
+
+#define BIT_SHIFT_CAMDBG_SEC_TYPE_8814B 12
+#define BIT_MASK_CAMDBG_SEC_TYPE_8814B 0x7
+#define BIT_CAMDBG_SEC_TYPE_8814B(x) \
+ (((x) & BIT_MASK_CAMDBG_SEC_TYPE_8814B) \
+ << BIT_SHIFT_CAMDBG_SEC_TYPE_8814B)
+#define BITS_CAMDBG_SEC_TYPE_8814B \
+ (BIT_MASK_CAMDBG_SEC_TYPE_8814B << BIT_SHIFT_CAMDBG_SEC_TYPE_8814B)
+#define BIT_CLEAR_CAMDBG_SEC_TYPE_8814B(x) ((x) & (~BITS_CAMDBG_SEC_TYPE_8814B))
+#define BIT_GET_CAMDBG_SEC_TYPE_8814B(x) \
+ (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8814B) & \
+ BIT_MASK_CAMDBG_SEC_TYPE_8814B)
+#define BIT_SET_CAMDBG_SEC_TYPE_8814B(x, v) \
+ (BIT_CLEAR_CAMDBG_SEC_TYPE_8814B(x) | BIT_CAMDBG_SEC_TYPE_8814B(v))
+
+#define BIT_CAMDBG_EXT_SECTYPE_8814B BIT(11)
+
+#define BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8814B 5
+#define BIT_MASK_CAMDBG_MIC_KEY_IDX_8814B 0x1f
+#define BIT_CAMDBG_MIC_KEY_IDX_8814B(x) \
+ (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8814B) \
+ << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8814B)
+#define BITS_CAMDBG_MIC_KEY_IDX_8814B \
+ (BIT_MASK_CAMDBG_MIC_KEY_IDX_8814B \
+ << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8814B)
+#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8814B(x) \
+ ((x) & (~BITS_CAMDBG_MIC_KEY_IDX_8814B))
+#define BIT_GET_CAMDBG_MIC_KEY_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8814B) & \
+ BIT_MASK_CAMDBG_MIC_KEY_IDX_8814B)
+#define BIT_SET_CAMDBG_MIC_KEY_IDX_8814B(x, v) \
+ (BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8814B(x) | \
+ BIT_CAMDBG_MIC_KEY_IDX_8814B(v))
+
+#define BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8814B 0
+#define BIT_MASK_CAMDBG_SEC_KEY_IDX_8814B 0x1f
+#define BIT_CAMDBG_SEC_KEY_IDX_8814B(x) \
+ (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8814B) \
+ << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8814B)
+#define BITS_CAMDBG_SEC_KEY_IDX_8814B \
+ (BIT_MASK_CAMDBG_SEC_KEY_IDX_8814B \
+ << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8814B)
+#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8814B(x) \
+ ((x) & (~BITS_CAMDBG_SEC_KEY_IDX_8814B))
+#define BIT_GET_CAMDBG_SEC_KEY_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8814B) & \
+ BIT_MASK_CAMDBG_SEC_KEY_IDX_8814B)
+#define BIT_SET_CAMDBG_SEC_KEY_IDX_8814B(x, v) \
+ (BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8814B(x) | \
+ BIT_CAMDBG_SEC_KEY_IDX_8814B(v))
+
+/* 2 REG_SECCFG_8814B (SECURITY CONFIGURATION REGISTER) */
+#define BIT_DIS_GCLK_WAPI_8814B BIT(15)
+#define BIT_DIS_GCLK_AES_8814B BIT(14)
+#define BIT_DIS_GCLK_TKIP_8814B BIT(13)
+#define BIT_AES_SEL_QC_1_8814B BIT(12)
+#define BIT_AES_SEL_QC_0_8814B BIT(11)
+#define BIT_CHK_BMC_8814B BIT(9)
+#define BIT_CHK_KEYID_8814B BIT(8)
+#define BIT_RXBCUSEDK_8814B BIT(7)
+#define BIT_TXBCUSEDK_8814B BIT(6)
+#define BIT_NOSKMC_8814B BIT(5)
+#define BIT_SKBYA2_8814B BIT(4)
+#define BIT_RXDEC_8814B BIT(3)
+#define BIT_TXENC_8814B BIT(2)
+#define BIT_RXUHUSEDK_8814B BIT(1)
+#define BIT_TXUHUSEDK_8814B BIT(0)
+
+/* 2 REG_RXFILTER_CATEGORY_1_8814B */
+
+#define BIT_SHIFT_RXFILTER_CATEGORY_1_8814B 0
+#define BIT_MASK_RXFILTER_CATEGORY_1_8814B 0xff
+#define BIT_RXFILTER_CATEGORY_1_8814B(x) \
+ (((x) & BIT_MASK_RXFILTER_CATEGORY_1_8814B) \
+ << BIT_SHIFT_RXFILTER_CATEGORY_1_8814B)
+#define BITS_RXFILTER_CATEGORY_1_8814B \
+ (BIT_MASK_RXFILTER_CATEGORY_1_8814B \
+ << BIT_SHIFT_RXFILTER_CATEGORY_1_8814B)
+#define BIT_CLEAR_RXFILTER_CATEGORY_1_8814B(x) \
+ ((x) & (~BITS_RXFILTER_CATEGORY_1_8814B))
+#define BIT_GET_RXFILTER_CATEGORY_1_8814B(x) \
+ (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8814B) & \
+ BIT_MASK_RXFILTER_CATEGORY_1_8814B)
+#define BIT_SET_RXFILTER_CATEGORY_1_8814B(x, v) \
+ (BIT_CLEAR_RXFILTER_CATEGORY_1_8814B(x) | \
+ BIT_RXFILTER_CATEGORY_1_8814B(v))
+
+/* 2 REG_RXFILTER_ACTION_1_8814B */
+
+#define BIT_SHIFT_RXFILTER_ACTION_1_8814B 0
+#define BIT_MASK_RXFILTER_ACTION_1_8814B 0xff
+#define BIT_RXFILTER_ACTION_1_8814B(x) \
+ (((x) & BIT_MASK_RXFILTER_ACTION_1_8814B) \
+ << BIT_SHIFT_RXFILTER_ACTION_1_8814B)
+#define BITS_RXFILTER_ACTION_1_8814B \
+ (BIT_MASK_RXFILTER_ACTION_1_8814B << BIT_SHIFT_RXFILTER_ACTION_1_8814B)
+#define BIT_CLEAR_RXFILTER_ACTION_1_8814B(x) \
+ ((x) & (~BITS_RXFILTER_ACTION_1_8814B))
+#define BIT_GET_RXFILTER_ACTION_1_8814B(x) \
+ (((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8814B) & \
+ BIT_MASK_RXFILTER_ACTION_1_8814B)
+#define BIT_SET_RXFILTER_ACTION_1_8814B(x, v) \
+ (BIT_CLEAR_RXFILTER_ACTION_1_8814B(x) | BIT_RXFILTER_ACTION_1_8814B(v))
+
+/* 2 REG_RXFILTER_CATEGORY_2_8814B */
+
+#define BIT_SHIFT_RXFILTER_CATEGORY_2_8814B 0
+#define BIT_MASK_RXFILTER_CATEGORY_2_8814B 0xff
+#define BIT_RXFILTER_CATEGORY_2_8814B(x) \
+ (((x) & BIT_MASK_RXFILTER_CATEGORY_2_8814B) \
+ << BIT_SHIFT_RXFILTER_CATEGORY_2_8814B)
+#define BITS_RXFILTER_CATEGORY_2_8814B \
+ (BIT_MASK_RXFILTER_CATEGORY_2_8814B \
+ << BIT_SHIFT_RXFILTER_CATEGORY_2_8814B)
+#define BIT_CLEAR_RXFILTER_CATEGORY_2_8814B(x) \
+ ((x) & (~BITS_RXFILTER_CATEGORY_2_8814B))
+#define BIT_GET_RXFILTER_CATEGORY_2_8814B(x) \
+ (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8814B) & \
+ BIT_MASK_RXFILTER_CATEGORY_2_8814B)
+#define BIT_SET_RXFILTER_CATEGORY_2_8814B(x, v) \
+ (BIT_CLEAR_RXFILTER_CATEGORY_2_8814B(x) | \
+ BIT_RXFILTER_CATEGORY_2_8814B(v))
+
+/* 2 REG_RXFILTER_ACTION_2_8814B */
+
+#define BIT_SHIFT_RXFILTER_ACTION_2_8814B 0
+#define BIT_MASK_RXFILTER_ACTION_2_8814B 0xff
+#define BIT_RXFILTER_ACTION_2_8814B(x) \
+ (((x) & BIT_MASK_RXFILTER_ACTION_2_8814B) \
+ << BIT_SHIFT_RXFILTER_ACTION_2_8814B)
+#define BITS_RXFILTER_ACTION_2_8814B \
+ (BIT_MASK_RXFILTER_ACTION_2_8814B << BIT_SHIFT_RXFILTER_ACTION_2_8814B)
+#define BIT_CLEAR_RXFILTER_ACTION_2_8814B(x) \
+ ((x) & (~BITS_RXFILTER_ACTION_2_8814B))
+#define BIT_GET_RXFILTER_ACTION_2_8814B(x) \
+ (((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8814B) & \
+ BIT_MASK_RXFILTER_ACTION_2_8814B)
+#define BIT_SET_RXFILTER_ACTION_2_8814B(x, v) \
+ (BIT_CLEAR_RXFILTER_ACTION_2_8814B(x) | BIT_RXFILTER_ACTION_2_8814B(v))
+
+/* 2 REG_RXFILTER_CATEGORY_3_8814B */
+
+#define BIT_SHIFT_RXFILTER_CATEGORY_3_8814B 0
+#define BIT_MASK_RXFILTER_CATEGORY_3_8814B 0xff
+#define BIT_RXFILTER_CATEGORY_3_8814B(x) \
+ (((x) & BIT_MASK_RXFILTER_CATEGORY_3_8814B) \
+ << BIT_SHIFT_RXFILTER_CATEGORY_3_8814B)
+#define BITS_RXFILTER_CATEGORY_3_8814B \
+ (BIT_MASK_RXFILTER_CATEGORY_3_8814B \
+ << BIT_SHIFT_RXFILTER_CATEGORY_3_8814B)
+#define BIT_CLEAR_RXFILTER_CATEGORY_3_8814B(x) \
+ ((x) & (~BITS_RXFILTER_CATEGORY_3_8814B))
+#define BIT_GET_RXFILTER_CATEGORY_3_8814B(x) \
+ (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8814B) & \
+ BIT_MASK_RXFILTER_CATEGORY_3_8814B)
+#define BIT_SET_RXFILTER_CATEGORY_3_8814B(x, v) \
+ (BIT_CLEAR_RXFILTER_CATEGORY_3_8814B(x) | \
+ BIT_RXFILTER_CATEGORY_3_8814B(v))
+
+/* 2 REG_RXFILTER_ACTION_3_8814B */
+
+#define BIT_SHIFT_RXFILTER_ACTION_3_8814B 0
+#define BIT_MASK_RXFILTER_ACTION_3_8814B 0xff
+#define BIT_RXFILTER_ACTION_3_8814B(x) \
+ (((x) & BIT_MASK_RXFILTER_ACTION_3_8814B) \
+ << BIT_SHIFT_RXFILTER_ACTION_3_8814B)
+#define BITS_RXFILTER_ACTION_3_8814B \
+ (BIT_MASK_RXFILTER_ACTION_3_8814B << BIT_SHIFT_RXFILTER_ACTION_3_8814B)
+#define BIT_CLEAR_RXFILTER_ACTION_3_8814B(x) \
+ ((x) & (~BITS_RXFILTER_ACTION_3_8814B))
+#define BIT_GET_RXFILTER_ACTION_3_8814B(x) \
+ (((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8814B) & \
+ BIT_MASK_RXFILTER_ACTION_3_8814B)
+#define BIT_SET_RXFILTER_ACTION_3_8814B(x, v) \
+ (BIT_CLEAR_RXFILTER_ACTION_3_8814B(x) | BIT_RXFILTER_ACTION_3_8814B(v))
+
+/* 2 REG_RXFLTMAP3_8814B (RX FILTER MAP GROUP 3) */
+#define BIT_MGTFLT15EN_FW_8814B BIT(15)
+#define BIT_MGTFLT14EN_FW_8814B BIT(14)
+#define BIT_MGTFLT13EN_FW_8814B BIT(13)
+#define BIT_MGTFLT12EN_FW_8814B BIT(12)
+#define BIT_MGTFLT11EN_FW_8814B BIT(11)
+#define BIT_MGTFLT10EN_FW_8814B BIT(10)
+#define BIT_MGTFLT9EN_FW_8814B BIT(9)
+#define BIT_MGTFLT8EN_FW_8814B BIT(8)
+#define BIT_MGTFLT7EN_FW_8814B BIT(7)
+#define BIT_MGTFLT6EN_FW_8814B BIT(6)
+#define BIT_MGTFLT5EN_FW_8814B BIT(5)
+#define BIT_MGTFLT4EN_FW_8814B BIT(4)
+#define BIT_MGTFLT3EN_FW_8814B BIT(3)
+#define BIT_MGTFLT2EN_FW_8814B BIT(2)
+#define BIT_MGTFLT1EN_FW_8814B BIT(1)
+#define BIT_MGTFLT0EN_FW_8814B BIT(0)
+
+/* 2 REG_RXFLTMAP4_8814B (RX FILTER MAP GROUP 4) */
+#define BIT_CTRLFLT15EN_FW_8814B BIT(15)
+#define BIT_CTRLFLT14EN_FW_8814B BIT(14)
+#define BIT_CTRLFLT13EN_FW_8814B BIT(13)
+#define BIT_CTRLFLT12EN_FW_8814B BIT(12)
+#define BIT_CTRLFLT11EN_FW_8814B BIT(11)
+#define BIT_CTRLFLT10EN_FW_8814B BIT(10)
+#define BIT_CTRLFLT9EN_FW_8814B BIT(9)
+#define BIT_CTRLFLT8EN_FW_8814B BIT(8)
+#define BIT_CTRLFLT7EN_FW_8814B BIT(7)
+#define BIT_CTRLFLT6EN_FW_8814B BIT(6)
+#define BIT_CTRLFLT5EN_FW_8814B BIT(5)
+#define BIT_CTRLFLT4EN_FW_8814B BIT(4)
+#define BIT_CTRLFLT3EN_FW_8814B BIT(3)
+#define BIT_CTRLFLT2EN_FW_8814B BIT(2)
+#define BIT_CTRLFLT1EN_FW_8814B BIT(1)
+#define BIT_CTRLFLT0EN_FW_8814B BIT(0)
+
+/* 2 REG_RXFLTMAP5_8814B (RX FILTER MAP GROUP 5) */
+#define BIT_DATAFLT15EN_FW_8814B BIT(15)
+#define BIT_DATAFLT14EN_FW_8814B BIT(14)
+#define BIT_DATAFLT13EN_FW_8814B BIT(13)
+#define BIT_DATAFLT12EN_FW_8814B BIT(12)
+#define BIT_DATAFLT11EN_FW_8814B BIT(11)
+#define BIT_DATAFLT10EN_FW_8814B BIT(10)
+#define BIT_DATAFLT9EN_FW_8814B BIT(9)
+#define BIT_DATAFLT8EN_FW_8814B BIT(8)
+#define BIT_DATAFLT7EN_FW_8814B BIT(7)
+#define BIT_DATAFLT6EN_FW_8814B BIT(6)
+#define BIT_DATAFLT5EN_FW_8814B BIT(5)
+#define BIT_DATAFLT4EN_FW_8814B BIT(4)
+#define BIT_DATAFLT3EN_FW_8814B BIT(3)
+#define BIT_DATAFLT2EN_FW_8814B BIT(2)
+#define BIT_DATAFLT1EN_FW_8814B BIT(1)
+#define BIT_DATAFLT0EN_FW_8814B BIT(0)
+
+/* 2 REG_RXFLTMAP6_8814B (RX FILTER MAP GROUP 6) */
+#define BIT_ACTIONFLT15EN_FW_8814B BIT(15)
+#define BIT_ACTIONFLT14EN_FW_8814B BIT(14)
+#define BIT_ACTIONFLT13EN_FW_8814B BIT(13)
+#define BIT_ACTIONFLT12EN_FW_8814B BIT(12)
+#define BIT_ACTIONFLT11EN_FW_8814B BIT(11)
+#define BIT_ACTIONFLT10EN_FW_8814B BIT(10)
+#define BIT_ACTIONFLT9EN_FW_8814B BIT(9)
+#define BIT_ACTIONFLT8EN_FW_8814B BIT(8)
+#define BIT_ACTIONFLT7EN_FW_8814B BIT(7)
+#define BIT_ACTIONFLT6EN_FW_8814B BIT(6)
+#define BIT_ACTIONFLT5EN_FW_8814B BIT(5)
+#define BIT_ACTIONFLT4EN_FW_8814B BIT(4)
+#define BIT_ACTIONFLT3EN_FW_8814B BIT(3)
+#define BIT_ACTIONFLT2EN_FW_8814B BIT(2)
+#define BIT_ACTIONFLT1EN_FW_8814B BIT(1)
+#define BIT_ACTIONFLT0EN_FW_8814B BIT(0)
+
+/* 2 REG_WOW_CTRL_8814B (WAKE ON WLAN CONTROL REGISTER) */
+
+#define BIT_SHIFT_PSF_BSSIDSEL_B2B1_8814B 6
+#define BIT_MASK_PSF_BSSIDSEL_B2B1_8814B 0x3
+#define BIT_PSF_BSSIDSEL_B2B1_8814B(x) \
+ (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8814B) \
+ << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8814B)
+#define BITS_PSF_BSSIDSEL_B2B1_8814B \
+ (BIT_MASK_PSF_BSSIDSEL_B2B1_8814B << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8814B)
+#define BIT_CLEAR_PSF_BSSIDSEL_B2B1_8814B(x) \
+ ((x) & (~BITS_PSF_BSSIDSEL_B2B1_8814B))
+#define BIT_GET_PSF_BSSIDSEL_B2B1_8814B(x) \
+ (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8814B) & \
+ BIT_MASK_PSF_BSSIDSEL_B2B1_8814B)
+#define BIT_SET_PSF_BSSIDSEL_B2B1_8814B(x, v) \
+ (BIT_CLEAR_PSF_BSSIDSEL_B2B1_8814B(x) | BIT_PSF_BSSIDSEL_B2B1_8814B(v))
+
+#define BIT_WOWHCI_8814B BIT(5)
+#define BIT_PSF_BSSIDSEL_B0_8814B BIT(4)
+#define BIT_UWF_8814B BIT(3)
+#define BIT_MAGIC_8814B BIT(2)
+#define BIT_WOWEN_8814B BIT(1)
+#define BIT_FORCE_WAKEUP_8814B BIT(0)
+
+/* 2 REG_NAN_RX_TSF_FILTER_8814B(NAN_RX_TSF_ADDRESS_FILTER) */
+#define BIT_CHK_TSF_TA_8814B BIT(2)
+#define BIT_CHK_TSF_CBSSID_8814B BIT(1)
+#define BIT_CHK_TSF_EN_8814B BIT(0)
+
+/* 2 REG_PS_RX_INFO_8814B (POWER SAVE RX INFORMATION REGISTER) */
+
+#define BIT_SHIFT_PORTSEL__PS_RX_INFO_8814B 5
+#define BIT_MASK_PORTSEL__PS_RX_INFO_8814B 0x7
+#define BIT_PORTSEL__PS_RX_INFO_8814B(x) \
+ (((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8814B) \
+ << BIT_SHIFT_PORTSEL__PS_RX_INFO_8814B)
+#define BITS_PORTSEL__PS_RX_INFO_8814B \
+ (BIT_MASK_PORTSEL__PS_RX_INFO_8814B \
+ << BIT_SHIFT_PORTSEL__PS_RX_INFO_8814B)
+#define BIT_CLEAR_PORTSEL__PS_RX_INFO_8814B(x) \
+ ((x) & (~BITS_PORTSEL__PS_RX_INFO_8814B))
+#define BIT_GET_PORTSEL__PS_RX_INFO_8814B(x) \
+ (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8814B) & \
+ BIT_MASK_PORTSEL__PS_RX_INFO_8814B)
+#define BIT_SET_PORTSEL__PS_RX_INFO_8814B(x, v) \
+ (BIT_CLEAR_PORTSEL__PS_RX_INFO_8814B(x) | \
+ BIT_PORTSEL__PS_RX_INFO_8814B(v))
+
+#define BIT_RXCTRLIN0_8814B BIT(4)
+#define BIT_RXMGTIN0_8814B BIT(3)
+#define BIT_RXDATAIN2_8814B BIT(2)
+#define BIT_RXDATAIN1_8814B BIT(1)
+#define BIT_RXDATAIN0_8814B BIT(0)
+
+/* 2 REG_WMMPS_UAPSD_TID_8814B (WMM POWER SAVE UAPSD TID REGISTER) */
+#define BIT_WMMPS_UAPSD_TID7_8814B BIT(7)
+#define BIT_WMMPS_UAPSD_TID6_8814B BIT(6)
+#define BIT_WMMPS_UAPSD_TID5_8814B BIT(5)
+#define BIT_WMMPS_UAPSD_TID4_8814B BIT(4)
+#define BIT_WMMPS_UAPSD_TID3_8814B BIT(3)
+#define BIT_WMMPS_UAPSD_TID2_8814B BIT(2)
+#define BIT_WMMPS_UAPSD_TID1_8814B BIT(1)
+#define BIT_WMMPS_UAPSD_TID0_8814B BIT(0)
+
+/* 2 REG_LPNAV_CTRL_8814B (LOW POWER NAV CONTROL REGISTER) */
+
+/* 2 REG_WKFMCAM_CMD_8814B (WAKEUP FRAME CAM COMMAND REGISTER) */
+#define BIT_WKFCAM_POLLING_V1_8814B BIT(31)
+#define BIT_WKFCAM_CLR_V1_8814B BIT(30)
+#define BIT_WKFCAM_WE_8814B BIT(16)
+
+#define BIT_SHIFT_WKFCAM_ADDR_V2_8814B 8
+#define BIT_MASK_WKFCAM_ADDR_V2_8814B 0xff
+#define BIT_WKFCAM_ADDR_V2_8814B(x) \
+ (((x) & BIT_MASK_WKFCAM_ADDR_V2_8814B) \
+ << BIT_SHIFT_WKFCAM_ADDR_V2_8814B)
+#define BITS_WKFCAM_ADDR_V2_8814B \
+ (BIT_MASK_WKFCAM_ADDR_V2_8814B << BIT_SHIFT_WKFCAM_ADDR_V2_8814B)
+#define BIT_CLEAR_WKFCAM_ADDR_V2_8814B(x) ((x) & (~BITS_WKFCAM_ADDR_V2_8814B))
+#define BIT_GET_WKFCAM_ADDR_V2_8814B(x) \
+ (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2_8814B) & \
+ BIT_MASK_WKFCAM_ADDR_V2_8814B)
+#define BIT_SET_WKFCAM_ADDR_V2_8814B(x, v) \
+ (BIT_CLEAR_WKFCAM_ADDR_V2_8814B(x) | BIT_WKFCAM_ADDR_V2_8814B(v))
+
+#define BIT_SHIFT_WKFCAM_CAM_NUM_V1_8814B 0
+#define BIT_MASK_WKFCAM_CAM_NUM_V1_8814B 0xff
+#define BIT_WKFCAM_CAM_NUM_V1_8814B(x) \
+ (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1_8814B) \
+ << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8814B)
+#define BITS_WKFCAM_CAM_NUM_V1_8814B \
+ (BIT_MASK_WKFCAM_CAM_NUM_V1_8814B << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8814B)
+#define BIT_CLEAR_WKFCAM_CAM_NUM_V1_8814B(x) \
+ ((x) & (~BITS_WKFCAM_CAM_NUM_V1_8814B))
+#define BIT_GET_WKFCAM_CAM_NUM_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8814B) & \
+ BIT_MASK_WKFCAM_CAM_NUM_V1_8814B)
+#define BIT_SET_WKFCAM_CAM_NUM_V1_8814B(x, v) \
+ (BIT_CLEAR_WKFCAM_CAM_NUM_V1_8814B(x) | BIT_WKFCAM_CAM_NUM_V1_8814B(v))
+
+/* 2 REG_WKFMCAM_RWD_8814B (WAKEUP FRAME READ/WRITE DATA) */
+
+#define BIT_SHIFT_WKFMCAM_RWD_8814B 0
+#define BIT_MASK_WKFMCAM_RWD_8814B 0xffffffffL
+#define BIT_WKFMCAM_RWD_8814B(x) \
+ (((x) & BIT_MASK_WKFMCAM_RWD_8814B) << BIT_SHIFT_WKFMCAM_RWD_8814B)
+#define BITS_WKFMCAM_RWD_8814B \
+ (BIT_MASK_WKFMCAM_RWD_8814B << BIT_SHIFT_WKFMCAM_RWD_8814B)
+#define BIT_CLEAR_WKFMCAM_RWD_8814B(x) ((x) & (~BITS_WKFMCAM_RWD_8814B))
+#define BIT_GET_WKFMCAM_RWD_8814B(x) \
+ (((x) >> BIT_SHIFT_WKFMCAM_RWD_8814B) & BIT_MASK_WKFMCAM_RWD_8814B)
+#define BIT_SET_WKFMCAM_RWD_8814B(x, v) \
+ (BIT_CLEAR_WKFMCAM_RWD_8814B(x) | BIT_WKFMCAM_RWD_8814B(v))
+
+/* 2 REG_RXFLTMAP0_8814B (RX FILTER MAP GROUP 0) */
+#define BIT_MGTFLT15EN_8814B BIT(15)
+#define BIT_MGTFLT14EN_8814B BIT(14)
+#define BIT_MGTFLT13EN_8814B BIT(13)
+#define BIT_MGTFLT12EN_8814B BIT(12)
+#define BIT_MGTFLT11EN_8814B BIT(11)
+#define BIT_MGTFLT10EN_8814B BIT(10)
+#define BIT_MGTFLT9EN_8814B BIT(9)
+#define BIT_MGTFLT8EN_8814B BIT(8)
+#define BIT_MGTFLT7EN_8814B BIT(7)
+#define BIT_MGTFLT6EN_8814B BIT(6)
+#define BIT_MGTFLT5EN_8814B BIT(5)
+#define BIT_MGTFLT4EN_8814B BIT(4)
+#define BIT_MGTFLT3EN_8814B BIT(3)
+#define BIT_MGTFLT2EN_8814B BIT(2)
+#define BIT_MGTFLT1EN_8814B BIT(1)
+#define BIT_MGTFLT0EN_8814B BIT(0)
+
+/* 2 REG_RXFLTMAP1_8814B (RX FILTER MAP GROUP 1) */
+#define BIT_CTRLFLT15EN_8814B BIT(15)
+#define BIT_CTRLFLT14EN_8814B BIT(14)
+#define BIT_CTRLFLT13EN_8814B BIT(13)
+#define BIT_CTRLFLT12EN_8814B BIT(12)
+#define BIT_CTRLFLT11EN_8814B BIT(11)
+#define BIT_CTRLFLT10EN_8814B BIT(10)
+#define BIT_CTRLFLT9EN_8814B BIT(9)
+#define BIT_CTRLFLT8EN_8814B BIT(8)
+#define BIT_CTRLFLT7EN_8814B BIT(7)
+#define BIT_CTRLFLT6EN_8814B BIT(6)
+#define BIT_CTRLFLT5EN_8814B BIT(5)
+#define BIT_CTRLFLT4EN_8814B BIT(4)
+#define BIT_CTRLFLT3EN_8814B BIT(3)
+#define BIT_CTRLFLT2EN_8814B BIT(2)
+#define BIT_CTRLFLT1EN_8814B BIT(1)
+#define BIT_CTRLFLT0EN_8814B BIT(0)
+
+/* 2 REG_RXFLTMAP2_8814B (RX FILTER MAP GROUP 2) */
+#define BIT_DATAFLT15EN_8814B BIT(15)
+#define BIT_DATAFLT14EN_8814B BIT(14)
+#define BIT_DATAFLT13EN_8814B BIT(13)
+#define BIT_DATAFLT12EN_8814B BIT(12)
+#define BIT_DATAFLT11EN_8814B BIT(11)
+#define BIT_DATAFLT10EN_8814B BIT(10)
+#define BIT_DATAFLT9EN_8814B BIT(9)
+#define BIT_DATAFLT8EN_8814B BIT(8)
+#define BIT_DATAFLT7EN_8814B BIT(7)
+#define BIT_DATAFLT6EN_8814B BIT(6)
+#define BIT_DATAFLT5EN_8814B BIT(5)
+#define BIT_DATAFLT4EN_8814B BIT(4)
+#define BIT_DATAFLT3EN_8814B BIT(3)
+#define BIT_DATAFLT2EN_8814B BIT(2)
+#define BIT_DATAFLT1EN_8814B BIT(1)
+#define BIT_DATAFLT0EN_8814B BIT(0)
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_BCN_PSR_RPT_8814B (BEACON PARSER REPORT REGISTER) */
+
+#define BIT_SHIFT_DTIM_CNT_8814B 24
+#define BIT_MASK_DTIM_CNT_8814B 0xff
+#define BIT_DTIM_CNT_8814B(x) \
+ (((x) & BIT_MASK_DTIM_CNT_8814B) << BIT_SHIFT_DTIM_CNT_8814B)
+#define BITS_DTIM_CNT_8814B \
+ (BIT_MASK_DTIM_CNT_8814B << BIT_SHIFT_DTIM_CNT_8814B)
+#define BIT_CLEAR_DTIM_CNT_8814B(x) ((x) & (~BITS_DTIM_CNT_8814B))
+#define BIT_GET_DTIM_CNT_8814B(x) \
+ (((x) >> BIT_SHIFT_DTIM_CNT_8814B) & BIT_MASK_DTIM_CNT_8814B)
+#define BIT_SET_DTIM_CNT_8814B(x, v) \
+ (BIT_CLEAR_DTIM_CNT_8814B(x) | BIT_DTIM_CNT_8814B(v))
+
+#define BIT_SHIFT_DTIM_PERIOD_8814B 16
+#define BIT_MASK_DTIM_PERIOD_8814B 0xff
+#define BIT_DTIM_PERIOD_8814B(x) \
+ (((x) & BIT_MASK_DTIM_PERIOD_8814B) << BIT_SHIFT_DTIM_PERIOD_8814B)
+#define BITS_DTIM_PERIOD_8814B \
+ (BIT_MASK_DTIM_PERIOD_8814B << BIT_SHIFT_DTIM_PERIOD_8814B)
+#define BIT_CLEAR_DTIM_PERIOD_8814B(x) ((x) & (~BITS_DTIM_PERIOD_8814B))
+#define BIT_GET_DTIM_PERIOD_8814B(x) \
+ (((x) >> BIT_SHIFT_DTIM_PERIOD_8814B) & BIT_MASK_DTIM_PERIOD_8814B)
+#define BIT_SET_DTIM_PERIOD_8814B(x, v) \
+ (BIT_CLEAR_DTIM_PERIOD_8814B(x) | BIT_DTIM_PERIOD_8814B(v))
+
+#define BIT_DTIM_8814B BIT(15)
+#define BIT_TIM_8814B BIT(14)
+#define BIT_RPT_VALID_8814B BIT(13)
+
+#define BIT_SHIFT_PS_AID_0_8814B 0
+#define BIT_MASK_PS_AID_0_8814B 0x7ff
+#define BIT_PS_AID_0_8814B(x) \
+ (((x) & BIT_MASK_PS_AID_0_8814B) << BIT_SHIFT_PS_AID_0_8814B)
+#define BITS_PS_AID_0_8814B \
+ (BIT_MASK_PS_AID_0_8814B << BIT_SHIFT_PS_AID_0_8814B)
+#define BIT_CLEAR_PS_AID_0_8814B(x) ((x) & (~BITS_PS_AID_0_8814B))
+#define BIT_GET_PS_AID_0_8814B(x) \
+ (((x) >> BIT_SHIFT_PS_AID_0_8814B) & BIT_MASK_PS_AID_0_8814B)
+#define BIT_SET_PS_AID_0_8814B(x, v) \
+ (BIT_CLEAR_PS_AID_0_8814B(x) | BIT_PS_AID_0_8814B(v))
+
+/* 2 REG_FLC_RPC_8814B (FW LPS CONDITION -- RX PKT COUNTER) */
+
+#define BIT_SHIFT_FLC_RPC_8814B 0
+#define BIT_MASK_FLC_RPC_8814B 0xff
+#define BIT_FLC_RPC_8814B(x) \
+ (((x) & BIT_MASK_FLC_RPC_8814B) << BIT_SHIFT_FLC_RPC_8814B)
+#define BITS_FLC_RPC_8814B (BIT_MASK_FLC_RPC_8814B << BIT_SHIFT_FLC_RPC_8814B)
+#define BIT_CLEAR_FLC_RPC_8814B(x) ((x) & (~BITS_FLC_RPC_8814B))
+#define BIT_GET_FLC_RPC_8814B(x) \
+ (((x) >> BIT_SHIFT_FLC_RPC_8814B) & BIT_MASK_FLC_RPC_8814B)
+#define BIT_SET_FLC_RPC_8814B(x, v) \
+ (BIT_CLEAR_FLC_RPC_8814B(x) | BIT_FLC_RPC_8814B(v))
+
+/* 2 REG_FLC_RPCT_8814B (FLC_RPC THRESHOLD) */
+
+#define BIT_SHIFT_FLC_RPCT_8814B 0
+#define BIT_MASK_FLC_RPCT_8814B 0xff
+#define BIT_FLC_RPCT_8814B(x) \
+ (((x) & BIT_MASK_FLC_RPCT_8814B) << BIT_SHIFT_FLC_RPCT_8814B)
+#define BITS_FLC_RPCT_8814B \
+ (BIT_MASK_FLC_RPCT_8814B << BIT_SHIFT_FLC_RPCT_8814B)
+#define BIT_CLEAR_FLC_RPCT_8814B(x) ((x) & (~BITS_FLC_RPCT_8814B))
+#define BIT_GET_FLC_RPCT_8814B(x) \
+ (((x) >> BIT_SHIFT_FLC_RPCT_8814B) & BIT_MASK_FLC_RPCT_8814B)
+#define BIT_SET_FLC_RPCT_8814B(x, v) \
+ (BIT_CLEAR_FLC_RPCT_8814B(x) | BIT_FLC_RPCT_8814B(v))
+
+/* 2 REG_FLC_PTS_8814B (PKT TYPE SELECTION OF FLC_RPC T) */
+#define BIT_CMF_8814B BIT(2)
+#define BIT_CCF_8814B BIT(1)
+#define BIT_CDF_8814B BIT(0)
+
+/* 2 REG_FLC_TRPC_8814B (TIMER OF FLC_RPC) */
+#define BIT_FLC_RPCT_V1_8814B BIT(7)
+#define BIT_MODE_8814B BIT(6)
+
+#define BIT_SHIFT_TRPCD_8814B 0
+#define BIT_MASK_TRPCD_8814B 0x3f
+#define BIT_TRPCD_8814B(x) \
+ (((x) & BIT_MASK_TRPCD_8814B) << BIT_SHIFT_TRPCD_8814B)
+#define BITS_TRPCD_8814B (BIT_MASK_TRPCD_8814B << BIT_SHIFT_TRPCD_8814B)
+#define BIT_CLEAR_TRPCD_8814B(x) ((x) & (~BITS_TRPCD_8814B))
+#define BIT_GET_TRPCD_8814B(x) \
+ (((x) >> BIT_SHIFT_TRPCD_8814B) & BIT_MASK_TRPCD_8814B)
+#define BIT_SET_TRPCD_8814B(x, v) \
+ (BIT_CLEAR_TRPCD_8814B(x) | BIT_TRPCD_8814B(v))
+
+/* 2 REG_RXPKTMON_CTRL_8814B */
+
+#define BIT_SHIFT_RXBKQPKT_SEQ_8814B 20
+#define BIT_MASK_RXBKQPKT_SEQ_8814B 0xf
+#define BIT_RXBKQPKT_SEQ_8814B(x) \
+ (((x) & BIT_MASK_RXBKQPKT_SEQ_8814B) << BIT_SHIFT_RXBKQPKT_SEQ_8814B)
+#define BITS_RXBKQPKT_SEQ_8814B \
+ (BIT_MASK_RXBKQPKT_SEQ_8814B << BIT_SHIFT_RXBKQPKT_SEQ_8814B)
+#define BIT_CLEAR_RXBKQPKT_SEQ_8814B(x) ((x) & (~BITS_RXBKQPKT_SEQ_8814B))
+#define BIT_GET_RXBKQPKT_SEQ_8814B(x) \
+ (((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8814B) & BIT_MASK_RXBKQPKT_SEQ_8814B)
+#define BIT_SET_RXBKQPKT_SEQ_8814B(x, v) \
+ (BIT_CLEAR_RXBKQPKT_SEQ_8814B(x) | BIT_RXBKQPKT_SEQ_8814B(v))
+
+#define BIT_SHIFT_RXBEQPKT_SEQ_8814B 16
+#define BIT_MASK_RXBEQPKT_SEQ_8814B 0xf
+#define BIT_RXBEQPKT_SEQ_8814B(x) \
+ (((x) & BIT_MASK_RXBEQPKT_SEQ_8814B) << BIT_SHIFT_RXBEQPKT_SEQ_8814B)
+#define BITS_RXBEQPKT_SEQ_8814B \
+ (BIT_MASK_RXBEQPKT_SEQ_8814B << BIT_SHIFT_RXBEQPKT_SEQ_8814B)
+#define BIT_CLEAR_RXBEQPKT_SEQ_8814B(x) ((x) & (~BITS_RXBEQPKT_SEQ_8814B))
+#define BIT_GET_RXBEQPKT_SEQ_8814B(x) \
+ (((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8814B) & BIT_MASK_RXBEQPKT_SEQ_8814B)
+#define BIT_SET_RXBEQPKT_SEQ_8814B(x, v) \
+ (BIT_CLEAR_RXBEQPKT_SEQ_8814B(x) | BIT_RXBEQPKT_SEQ_8814B(v))
+
+#define BIT_SHIFT_RXVIQPKT_SEQ_8814B 12
+#define BIT_MASK_RXVIQPKT_SEQ_8814B 0xf
+#define BIT_RXVIQPKT_SEQ_8814B(x) \
+ (((x) & BIT_MASK_RXVIQPKT_SEQ_8814B) << BIT_SHIFT_RXVIQPKT_SEQ_8814B)
+#define BITS_RXVIQPKT_SEQ_8814B \
+ (BIT_MASK_RXVIQPKT_SEQ_8814B << BIT_SHIFT_RXVIQPKT_SEQ_8814B)
+#define BIT_CLEAR_RXVIQPKT_SEQ_8814B(x) ((x) & (~BITS_RXVIQPKT_SEQ_8814B))
+#define BIT_GET_RXVIQPKT_SEQ_8814B(x) \
+ (((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8814B) & BIT_MASK_RXVIQPKT_SEQ_8814B)
+#define BIT_SET_RXVIQPKT_SEQ_8814B(x, v) \
+ (BIT_CLEAR_RXVIQPKT_SEQ_8814B(x) | BIT_RXVIQPKT_SEQ_8814B(v))
+
+#define BIT_SHIFT_RXVOQPKT_SEQ_8814B 8
+#define BIT_MASK_RXVOQPKT_SEQ_8814B 0xf
+#define BIT_RXVOQPKT_SEQ_8814B(x) \
+ (((x) & BIT_MASK_RXVOQPKT_SEQ_8814B) << BIT_SHIFT_RXVOQPKT_SEQ_8814B)
+#define BITS_RXVOQPKT_SEQ_8814B \
+ (BIT_MASK_RXVOQPKT_SEQ_8814B << BIT_SHIFT_RXVOQPKT_SEQ_8814B)
+#define BIT_CLEAR_RXVOQPKT_SEQ_8814B(x) ((x) & (~BITS_RXVOQPKT_SEQ_8814B))
+#define BIT_GET_RXVOQPKT_SEQ_8814B(x) \
+ (((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8814B) & BIT_MASK_RXVOQPKT_SEQ_8814B)
+#define BIT_SET_RXVOQPKT_SEQ_8814B(x, v) \
+ (BIT_CLEAR_RXVOQPKT_SEQ_8814B(x) | BIT_RXVOQPKT_SEQ_8814B(v))
+
+#define BIT_RXBKQPKT_ERR_8814B BIT(7)
+#define BIT_RXBEQPKT_ERR_8814B BIT(6)
+#define BIT_RXVIQPKT_ERR_8814B BIT(5)
+#define BIT_RXVOQPKT_ERR_8814B BIT(4)
+#define BIT_RXDMA_MON_EN_8814B BIT(2)
+#define BIT_RXPKT_MON_RST_8814B BIT(1)
+#define BIT_RXPKT_MON_EN_8814B BIT(0)
+
+/* 2 REG_STATE_MON_8814B */
+
+#define BIT_SHIFT_STATE_SEL_8814B 24
+#define BIT_MASK_STATE_SEL_8814B 0x1f
+#define BIT_STATE_SEL_8814B(x) \
+ (((x) & BIT_MASK_STATE_SEL_8814B) << BIT_SHIFT_STATE_SEL_8814B)
+#define BITS_STATE_SEL_8814B \
+ (BIT_MASK_STATE_SEL_8814B << BIT_SHIFT_STATE_SEL_8814B)
+#define BIT_CLEAR_STATE_SEL_8814B(x) ((x) & (~BITS_STATE_SEL_8814B))
+#define BIT_GET_STATE_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_STATE_SEL_8814B) & BIT_MASK_STATE_SEL_8814B)
+#define BIT_SET_STATE_SEL_8814B(x, v) \
+ (BIT_CLEAR_STATE_SEL_8814B(x) | BIT_STATE_SEL_8814B(v))
+
+#define BIT_SHIFT_STATE_INFO_8814B 8
+#define BIT_MASK_STATE_INFO_8814B 0xff
+#define BIT_STATE_INFO_8814B(x) \
+ (((x) & BIT_MASK_STATE_INFO_8814B) << BIT_SHIFT_STATE_INFO_8814B)
+#define BITS_STATE_INFO_8814B \
+ (BIT_MASK_STATE_INFO_8814B << BIT_SHIFT_STATE_INFO_8814B)
+#define BIT_CLEAR_STATE_INFO_8814B(x) ((x) & (~BITS_STATE_INFO_8814B))
+#define BIT_GET_STATE_INFO_8814B(x) \
+ (((x) >> BIT_SHIFT_STATE_INFO_8814B) & BIT_MASK_STATE_INFO_8814B)
+#define BIT_SET_STATE_INFO_8814B(x, v) \
+ (BIT_CLEAR_STATE_INFO_8814B(x) | BIT_STATE_INFO_8814B(v))
+
+#define BIT_UPD_NXT_STATE_8814B BIT(7)
+
+#define BIT_SHIFT_CUR_STATE_8814B 0
+#define BIT_MASK_CUR_STATE_8814B 0x7f
+#define BIT_CUR_STATE_8814B(x) \
+ (((x) & BIT_MASK_CUR_STATE_8814B) << BIT_SHIFT_CUR_STATE_8814B)
+#define BITS_CUR_STATE_8814B \
+ (BIT_MASK_CUR_STATE_8814B << BIT_SHIFT_CUR_STATE_8814B)
+#define BIT_CLEAR_CUR_STATE_8814B(x) ((x) & (~BITS_CUR_STATE_8814B))
+#define BIT_GET_CUR_STATE_8814B(x) \
+ (((x) >> BIT_SHIFT_CUR_STATE_8814B) & BIT_MASK_CUR_STATE_8814B)
+#define BIT_SET_CUR_STATE_8814B(x, v) \
+ (BIT_CLEAR_CUR_STATE_8814B(x) | BIT_CUR_STATE_8814B(v))
+
+/* 2 REG_ERROR_MON_8814B */
+#define BIT_CSIRPT_LEN_BB_MORE_THAN_MAC_8814B BIT(23)
+#define BIT_CSI_CHKSUM_ERROR_8814B BIT(22)
+#define BIT_MACRX_ERR_5_8814B BIT(21)
+#define BIT_MACRX_ERR_4_8814B BIT(20)
+#define BIT_MACRX_ERR_3_8814B BIT(19)
+#define BIT_MACRX_ERR_2_8814B BIT(18)
+#define BIT_MACRX_ERR_1_8814B BIT(17)
+#define BIT_MACRX_ERR_0_8814B BIT(16)
+#define BIT_WMAC_PRETX_ERRHDL_EN_8814B BIT(15)
+#define BIT_MACTX_ERR_5_8814B BIT(5)
+#define BIT_MACTX_ERR_4_8814B BIT(4)
+#define BIT_MACTX_ERR_3_8814B BIT(3)
+#define BIT_MACTX_ERR_2_8814B BIT(2)
+#define BIT_MACTX_ERR_1_8814B BIT(1)
+#define BIT_MACTX_ERR_0_8814B BIT(0)
+
+/* 2 REG_SEARCH_MACID_8814B */
+#define BIT_EN_TXRPTBUF_CLK_8814B BIT(31)
+#define BIT_WMAC_SRCH_FIFOFULL_8814B BIT(15)
+#define BIT_DIS_INFOSRCH_8814B BIT(14)
+#define BIT_DISABLE_B0_8814B BIT(13)
+
+#define BIT_SHIFT_INFO_ADDR_OFFSET_8814B 0
+#define BIT_MASK_INFO_ADDR_OFFSET_8814B 0x1fff
+#define BIT_INFO_ADDR_OFFSET_8814B(x) \
+ (((x) & BIT_MASK_INFO_ADDR_OFFSET_8814B) \
+ << BIT_SHIFT_INFO_ADDR_OFFSET_8814B)
+#define BITS_INFO_ADDR_OFFSET_8814B \
+ (BIT_MASK_INFO_ADDR_OFFSET_8814B << BIT_SHIFT_INFO_ADDR_OFFSET_8814B)
+#define BIT_CLEAR_INFO_ADDR_OFFSET_8814B(x) \
+ ((x) & (~BITS_INFO_ADDR_OFFSET_8814B))
+#define BIT_GET_INFO_ADDR_OFFSET_8814B(x) \
+ (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8814B) & \
+ BIT_MASK_INFO_ADDR_OFFSET_8814B)
+#define BIT_SET_INFO_ADDR_OFFSET_8814B(x, v) \
+ (BIT_CLEAR_INFO_ADDR_OFFSET_8814B(x) | BIT_INFO_ADDR_OFFSET_8814B(v))
+
+/* 2 REG_BT_COEX_TABLE_8814B (BT-COEXISTENCE CONTROL REGISTER) */
+
+#define BIT_SHIFT_COEX_TABLE_1_8814B 0
+#define BIT_MASK_COEX_TABLE_1_8814B 0xffffffffL
+#define BIT_COEX_TABLE_1_8814B(x) \
+ (((x) & BIT_MASK_COEX_TABLE_1_8814B) << BIT_SHIFT_COEX_TABLE_1_8814B)
+#define BITS_COEX_TABLE_1_8814B \
+ (BIT_MASK_COEX_TABLE_1_8814B << BIT_SHIFT_COEX_TABLE_1_8814B)
+#define BIT_CLEAR_COEX_TABLE_1_8814B(x) ((x) & (~BITS_COEX_TABLE_1_8814B))
+#define BIT_GET_COEX_TABLE_1_8814B(x) \
+ (((x) >> BIT_SHIFT_COEX_TABLE_1_8814B) & BIT_MASK_COEX_TABLE_1_8814B)
+#define BIT_SET_COEX_TABLE_1_8814B(x, v) \
+ (BIT_CLEAR_COEX_TABLE_1_8814B(x) | BIT_COEX_TABLE_1_8814B(v))
+
+/* 2 REG_BT_COEX_TABLE2_8814B (BT-COEXISTENCE CONTROL REGISTER) */
+
+#define BIT_SHIFT_COEX_TABLE_2_8814B 0
+#define BIT_MASK_COEX_TABLE_2_8814B 0xffffffffL
+#define BIT_COEX_TABLE_2_8814B(x) \
+ (((x) & BIT_MASK_COEX_TABLE_2_8814B) << BIT_SHIFT_COEX_TABLE_2_8814B)
+#define BITS_COEX_TABLE_2_8814B \
+ (BIT_MASK_COEX_TABLE_2_8814B << BIT_SHIFT_COEX_TABLE_2_8814B)
+#define BIT_CLEAR_COEX_TABLE_2_8814B(x) ((x) & (~BITS_COEX_TABLE_2_8814B))
+#define BIT_GET_COEX_TABLE_2_8814B(x) \
+ (((x) >> BIT_SHIFT_COEX_TABLE_2_8814B) & BIT_MASK_COEX_TABLE_2_8814B)
+#define BIT_SET_COEX_TABLE_2_8814B(x, v) \
+ (BIT_CLEAR_COEX_TABLE_2_8814B(x) | BIT_COEX_TABLE_2_8814B(v))
+
+/* 2 REG_BT_COEX_BREAK_TABLE_8814B (BT-COEXISTENCE CONTROL REGISTER) */
+
+#define BIT_SHIFT_BREAK_TABLE_2_8814B 16
+#define BIT_MASK_BREAK_TABLE_2_8814B 0xffff
+#define BIT_BREAK_TABLE_2_8814B(x) \
+ (((x) & BIT_MASK_BREAK_TABLE_2_8814B) << BIT_SHIFT_BREAK_TABLE_2_8814B)
+#define BITS_BREAK_TABLE_2_8814B \
+ (BIT_MASK_BREAK_TABLE_2_8814B << BIT_SHIFT_BREAK_TABLE_2_8814B)
+#define BIT_CLEAR_BREAK_TABLE_2_8814B(x) ((x) & (~BITS_BREAK_TABLE_2_8814B))
+#define BIT_GET_BREAK_TABLE_2_8814B(x) \
+ (((x) >> BIT_SHIFT_BREAK_TABLE_2_8814B) & BIT_MASK_BREAK_TABLE_2_8814B)
+#define BIT_SET_BREAK_TABLE_2_8814B(x, v) \
+ (BIT_CLEAR_BREAK_TABLE_2_8814B(x) | BIT_BREAK_TABLE_2_8814B(v))
+
+#define BIT_SHIFT_BREAK_TABLE_1_8814B 0
+#define BIT_MASK_BREAK_TABLE_1_8814B 0xffff
+#define BIT_BREAK_TABLE_1_8814B(x) \
+ (((x) & BIT_MASK_BREAK_TABLE_1_8814B) << BIT_SHIFT_BREAK_TABLE_1_8814B)
+#define BITS_BREAK_TABLE_1_8814B \
+ (BIT_MASK_BREAK_TABLE_1_8814B << BIT_SHIFT_BREAK_TABLE_1_8814B)
+#define BIT_CLEAR_BREAK_TABLE_1_8814B(x) ((x) & (~BITS_BREAK_TABLE_1_8814B))
+#define BIT_GET_BREAK_TABLE_1_8814B(x) \
+ (((x) >> BIT_SHIFT_BREAK_TABLE_1_8814B) & BIT_MASK_BREAK_TABLE_1_8814B)
+#define BIT_SET_BREAK_TABLE_1_8814B(x, v) \
+ (BIT_CLEAR_BREAK_TABLE_1_8814B(x) | BIT_BREAK_TABLE_1_8814B(v))
+
+/* 2 REG_BT_COEX_TABLE_H_8814B (BT-COEXISTENCE CONTROL REGISTER) */
+#define BIT_PRI_MASK_RX_RESP_V1_8814B BIT(30)
+#define BIT_PRI_MASK_RXOFDM_V1_8814B BIT(29)
+#define BIT_PRI_MASK_RXCCK_V1_8814B BIT(28)
+
+#define BIT_SHIFT_PRI_MASK_TXAC_8814B 21
+#define BIT_MASK_PRI_MASK_TXAC_8814B 0x7f
+#define BIT_PRI_MASK_TXAC_8814B(x) \
+ (((x) & BIT_MASK_PRI_MASK_TXAC_8814B) << BIT_SHIFT_PRI_MASK_TXAC_8814B)
+#define BITS_PRI_MASK_TXAC_8814B \
+ (BIT_MASK_PRI_MASK_TXAC_8814B << BIT_SHIFT_PRI_MASK_TXAC_8814B)
+#define BIT_CLEAR_PRI_MASK_TXAC_8814B(x) ((x) & (~BITS_PRI_MASK_TXAC_8814B))
+#define BIT_GET_PRI_MASK_TXAC_8814B(x) \
+ (((x) >> BIT_SHIFT_PRI_MASK_TXAC_8814B) & BIT_MASK_PRI_MASK_TXAC_8814B)
+#define BIT_SET_PRI_MASK_TXAC_8814B(x, v) \
+ (BIT_CLEAR_PRI_MASK_TXAC_8814B(x) | BIT_PRI_MASK_TXAC_8814B(v))
+
+#define BIT_SHIFT_PRI_MASK_NAV_8814B 13
+#define BIT_MASK_PRI_MASK_NAV_8814B 0xff
+#define BIT_PRI_MASK_NAV_8814B(x) \
+ (((x) & BIT_MASK_PRI_MASK_NAV_8814B) << BIT_SHIFT_PRI_MASK_NAV_8814B)
+#define BITS_PRI_MASK_NAV_8814B \
+ (BIT_MASK_PRI_MASK_NAV_8814B << BIT_SHIFT_PRI_MASK_NAV_8814B)
+#define BIT_CLEAR_PRI_MASK_NAV_8814B(x) ((x) & (~BITS_PRI_MASK_NAV_8814B))
+#define BIT_GET_PRI_MASK_NAV_8814B(x) \
+ (((x) >> BIT_SHIFT_PRI_MASK_NAV_8814B) & BIT_MASK_PRI_MASK_NAV_8814B)
+#define BIT_SET_PRI_MASK_NAV_8814B(x, v) \
+ (BIT_CLEAR_PRI_MASK_NAV_8814B(x) | BIT_PRI_MASK_NAV_8814B(v))
+
+#define BIT_PRI_MASK_CCK_V1_8814B BIT(12)
+#define BIT_PRI_MASK_OFDM_V1_8814B BIT(11)
+#define BIT_PRI_MASK_RTY_V1_8814B BIT(10)
+
+#define BIT_SHIFT_PRI_MASK_NUM_8814B 6
+#define BIT_MASK_PRI_MASK_NUM_8814B 0xf
+#define BIT_PRI_MASK_NUM_8814B(x) \
+ (((x) & BIT_MASK_PRI_MASK_NUM_8814B) << BIT_SHIFT_PRI_MASK_NUM_8814B)
+#define BITS_PRI_MASK_NUM_8814B \
+ (BIT_MASK_PRI_MASK_NUM_8814B << BIT_SHIFT_PRI_MASK_NUM_8814B)
+#define BIT_CLEAR_PRI_MASK_NUM_8814B(x) ((x) & (~BITS_PRI_MASK_NUM_8814B))
+#define BIT_GET_PRI_MASK_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_PRI_MASK_NUM_8814B) & BIT_MASK_PRI_MASK_NUM_8814B)
+#define BIT_SET_PRI_MASK_NUM_8814B(x, v) \
+ (BIT_CLEAR_PRI_MASK_NUM_8814B(x) | BIT_PRI_MASK_NUM_8814B(v))
+
+#define BIT_SHIFT_PRI_MASK_TYPE_8814B 2
+#define BIT_MASK_PRI_MASK_TYPE_8814B 0xf
+#define BIT_PRI_MASK_TYPE_8814B(x) \
+ (((x) & BIT_MASK_PRI_MASK_TYPE_8814B) << BIT_SHIFT_PRI_MASK_TYPE_8814B)
+#define BITS_PRI_MASK_TYPE_8814B \
+ (BIT_MASK_PRI_MASK_TYPE_8814B << BIT_SHIFT_PRI_MASK_TYPE_8814B)
+#define BIT_CLEAR_PRI_MASK_TYPE_8814B(x) ((x) & (~BITS_PRI_MASK_TYPE_8814B))
+#define BIT_GET_PRI_MASK_TYPE_8814B(x) \
+ (((x) >> BIT_SHIFT_PRI_MASK_TYPE_8814B) & BIT_MASK_PRI_MASK_TYPE_8814B)
+#define BIT_SET_PRI_MASK_TYPE_8814B(x, v) \
+ (BIT_CLEAR_PRI_MASK_TYPE_8814B(x) | BIT_PRI_MASK_TYPE_8814B(v))
+
+#define BIT_OOB_V1_8814B BIT(1)
+#define BIT_ANT_SEL_V1_8814B BIT(0)
+
+/* 2 REG_RXCMD_0_8814B */
+#define BIT_RXCMD_EN_8814B BIT(31)
+
+#define BIT_SHIFT_RXCMD_INFO_8814B 0
+#define BIT_MASK_RXCMD_INFO_8814B 0x7fffffffL
+#define BIT_RXCMD_INFO_8814B(x) \
+ (((x) & BIT_MASK_RXCMD_INFO_8814B) << BIT_SHIFT_RXCMD_INFO_8814B)
+#define BITS_RXCMD_INFO_8814B \
+ (BIT_MASK_RXCMD_INFO_8814B << BIT_SHIFT_RXCMD_INFO_8814B)
+#define BIT_CLEAR_RXCMD_INFO_8814B(x) ((x) & (~BITS_RXCMD_INFO_8814B))
+#define BIT_GET_RXCMD_INFO_8814B(x) \
+ (((x) >> BIT_SHIFT_RXCMD_INFO_8814B) & BIT_MASK_RXCMD_INFO_8814B)
+#define BIT_SET_RXCMD_INFO_8814B(x, v) \
+ (BIT_CLEAR_RXCMD_INFO_8814B(x) | BIT_RXCMD_INFO_8814B(v))
+
+/* 2 REG_RXCMD_1_8814B */
+
+#define BIT_SHIFT_CSI_RADDR_LATCH_8814B 24
+#define BIT_MASK_CSI_RADDR_LATCH_8814B 0xff
+#define BIT_CSI_RADDR_LATCH_8814B(x) \
+ (((x) & BIT_MASK_CSI_RADDR_LATCH_8814B) \
+ << BIT_SHIFT_CSI_RADDR_LATCH_8814B)
+#define BITS_CSI_RADDR_LATCH_8814B \
+ (BIT_MASK_CSI_RADDR_LATCH_8814B << BIT_SHIFT_CSI_RADDR_LATCH_8814B)
+#define BIT_CLEAR_CSI_RADDR_LATCH_8814B(x) ((x) & (~BITS_CSI_RADDR_LATCH_8814B))
+#define BIT_GET_CSI_RADDR_LATCH_8814B(x) \
+ (((x) >> BIT_SHIFT_CSI_RADDR_LATCH_8814B) & \
+ BIT_MASK_CSI_RADDR_LATCH_8814B)
+#define BIT_SET_CSI_RADDR_LATCH_8814B(x, v) \
+ (BIT_CLEAR_CSI_RADDR_LATCH_8814B(x) | BIT_CSI_RADDR_LATCH_8814B(v))
+
+#define BIT_SHIFT_CSI_WADDR_LATCH_8814B 16
+#define BIT_MASK_CSI_WADDR_LATCH_8814B 0xff
+#define BIT_CSI_WADDR_LATCH_8814B(x) \
+ (((x) & BIT_MASK_CSI_WADDR_LATCH_8814B) \
+ << BIT_SHIFT_CSI_WADDR_LATCH_8814B)
+#define BITS_CSI_WADDR_LATCH_8814B \
+ (BIT_MASK_CSI_WADDR_LATCH_8814B << BIT_SHIFT_CSI_WADDR_LATCH_8814B)
+#define BIT_CLEAR_CSI_WADDR_LATCH_8814B(x) ((x) & (~BITS_CSI_WADDR_LATCH_8814B))
+#define BIT_GET_CSI_WADDR_LATCH_8814B(x) \
+ (((x) >> BIT_SHIFT_CSI_WADDR_LATCH_8814B) & \
+ BIT_MASK_CSI_WADDR_LATCH_8814B)
+#define BIT_SET_CSI_WADDR_LATCH_8814B(x, v) \
+ (BIT_CLEAR_CSI_WADDR_LATCH_8814B(x) | BIT_CSI_WADDR_LATCH_8814B(v))
+
+#define BIT_SHIFT_RXCMD_PRD_8814B 0
+#define BIT_MASK_RXCMD_PRD_8814B 0xffff
+#define BIT_RXCMD_PRD_8814B(x) \
+ (((x) & BIT_MASK_RXCMD_PRD_8814B) << BIT_SHIFT_RXCMD_PRD_8814B)
+#define BITS_RXCMD_PRD_8814B \
+ (BIT_MASK_RXCMD_PRD_8814B << BIT_SHIFT_RXCMD_PRD_8814B)
+#define BIT_CLEAR_RXCMD_PRD_8814B(x) ((x) & (~BITS_RXCMD_PRD_8814B))
+#define BIT_GET_RXCMD_PRD_8814B(x) \
+ (((x) >> BIT_SHIFT_RXCMD_PRD_8814B) & BIT_MASK_RXCMD_PRD_8814B)
+#define BIT_SET_RXCMD_PRD_8814B(x, v) \
+ (BIT_CLEAR_RXCMD_PRD_8814B(x) | BIT_RXCMD_PRD_8814B(v))
+
+/* 2 REG_WMAC_RESP_TXINFO_8814B (RESPONSE TXINFO REGISTER) */
+
+#define BIT_SHIFT_WMAC_RESP_MFB_8814B 25
+#define BIT_MASK_WMAC_RESP_MFB_8814B 0x7f
+#define BIT_WMAC_RESP_MFB_8814B(x) \
+ (((x) & BIT_MASK_WMAC_RESP_MFB_8814B) << BIT_SHIFT_WMAC_RESP_MFB_8814B)
+#define BITS_WMAC_RESP_MFB_8814B \
+ (BIT_MASK_WMAC_RESP_MFB_8814B << BIT_SHIFT_WMAC_RESP_MFB_8814B)
+#define BIT_CLEAR_WMAC_RESP_MFB_8814B(x) ((x) & (~BITS_WMAC_RESP_MFB_8814B))
+#define BIT_GET_WMAC_RESP_MFB_8814B(x) \
+ (((x) >> BIT_SHIFT_WMAC_RESP_MFB_8814B) & BIT_MASK_WMAC_RESP_MFB_8814B)
+#define BIT_SET_WMAC_RESP_MFB_8814B(x, v) \
+ (BIT_CLEAR_WMAC_RESP_MFB_8814B(x) | BIT_WMAC_RESP_MFB_8814B(v))
+
+#define BIT_SHIFT_WMAC_ANTINF_SEL_8814B 23
+#define BIT_MASK_WMAC_ANTINF_SEL_8814B 0x3
+#define BIT_WMAC_ANTINF_SEL_8814B(x) \
+ (((x) & BIT_MASK_WMAC_ANTINF_SEL_8814B) \
+ << BIT_SHIFT_WMAC_ANTINF_SEL_8814B)
+#define BITS_WMAC_ANTINF_SEL_8814B \
+ (BIT_MASK_WMAC_ANTINF_SEL_8814B << BIT_SHIFT_WMAC_ANTINF_SEL_8814B)
+#define BIT_CLEAR_WMAC_ANTINF_SEL_8814B(x) ((x) & (~BITS_WMAC_ANTINF_SEL_8814B))
+#define BIT_GET_WMAC_ANTINF_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8814B) & \
+ BIT_MASK_WMAC_ANTINF_SEL_8814B)
+#define BIT_SET_WMAC_ANTINF_SEL_8814B(x, v) \
+ (BIT_CLEAR_WMAC_ANTINF_SEL_8814B(x) | BIT_WMAC_ANTINF_SEL_8814B(v))
+
+#define BIT_SHIFT_WMAC_ANTSEL_SEL_8814B 21
+#define BIT_MASK_WMAC_ANTSEL_SEL_8814B 0x3
+#define BIT_WMAC_ANTSEL_SEL_8814B(x) \
+ (((x) & BIT_MASK_WMAC_ANTSEL_SEL_8814B) \
+ << BIT_SHIFT_WMAC_ANTSEL_SEL_8814B)
+#define BITS_WMAC_ANTSEL_SEL_8814B \
+ (BIT_MASK_WMAC_ANTSEL_SEL_8814B << BIT_SHIFT_WMAC_ANTSEL_SEL_8814B)
+#define BIT_CLEAR_WMAC_ANTSEL_SEL_8814B(x) ((x) & (~BITS_WMAC_ANTSEL_SEL_8814B))
+#define BIT_GET_WMAC_ANTSEL_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8814B) & \
+ BIT_MASK_WMAC_ANTSEL_SEL_8814B)
+#define BIT_SET_WMAC_ANTSEL_SEL_8814B(x, v) \
+ (BIT_CLEAR_WMAC_ANTSEL_SEL_8814B(x) | BIT_WMAC_ANTSEL_SEL_8814B(v))
+
+#define BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B 18
+#define BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B 0x3
+#define BIT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B(x) \
+ (((x) & BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B) \
+ << BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B)
+#define BITS_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B \
+ (BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B \
+ << BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B)
+#define BIT_CLEAR_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B(x) \
+ ((x) & (~BITS_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B))
+#define BIT_GET_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B(x) \
+ (((x) >> BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B) & \
+ BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B)
+#define BIT_SET_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B(x, v) \
+ (BIT_CLEAR_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B(x) | \
+ BIT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8814B(v))
+
+#define BIT_SHIFT_WMAC_RESP_TXANT_V1_8814B 6
+#define BIT_MASK_WMAC_RESP_TXANT_V1_8814B 0xfff
+#define BIT_WMAC_RESP_TXANT_V1_8814B(x) \
+ (((x) & BIT_MASK_WMAC_RESP_TXANT_V1_8814B) \
+ << BIT_SHIFT_WMAC_RESP_TXANT_V1_8814B)
+#define BITS_WMAC_RESP_TXANT_V1_8814B \
+ (BIT_MASK_WMAC_RESP_TXANT_V1_8814B \
+ << BIT_SHIFT_WMAC_RESP_TXANT_V1_8814B)
+#define BIT_CLEAR_WMAC_RESP_TXANT_V1_8814B(x) \
+ ((x) & (~BITS_WMAC_RESP_TXANT_V1_8814B))
+#define BIT_GET_WMAC_RESP_TXANT_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_WMAC_RESP_TXANT_V1_8814B) & \
+ BIT_MASK_WMAC_RESP_TXANT_V1_8814B)
+#define BIT_SET_WMAC_RESP_TXANT_V1_8814B(x, v) \
+ (BIT_CLEAR_WMAC_RESP_TXANT_V1_8814B(x) | \
+ BIT_WMAC_RESP_TXANT_V1_8814B(v))
+
+/* 2 REG_BBPSF_CTRL_8814B */
+#define BIT_CTL_IDLE_CLR_CSI_RPT_8814B BIT(31)
+#define BIT_WMAC_USE_NDPARATE_8814B BIT(30)
+
+#define BIT_SHIFT_WMAC_CSI_RATE_8814B 24
+#define BIT_MASK_WMAC_CSI_RATE_8814B 0x3f
+#define BIT_WMAC_CSI_RATE_8814B(x) \
+ (((x) & BIT_MASK_WMAC_CSI_RATE_8814B) << BIT_SHIFT_WMAC_CSI_RATE_8814B)
+#define BITS_WMAC_CSI_RATE_8814B \
+ (BIT_MASK_WMAC_CSI_RATE_8814B << BIT_SHIFT_WMAC_CSI_RATE_8814B)
+#define BIT_CLEAR_WMAC_CSI_RATE_8814B(x) ((x) & (~BITS_WMAC_CSI_RATE_8814B))
+#define BIT_GET_WMAC_CSI_RATE_8814B(x) \
+ (((x) >> BIT_SHIFT_WMAC_CSI_RATE_8814B) & BIT_MASK_WMAC_CSI_RATE_8814B)
+#define BIT_SET_WMAC_CSI_RATE_8814B(x, v) \
+ (BIT_CLEAR_WMAC_CSI_RATE_8814B(x) | BIT_WMAC_CSI_RATE_8814B(v))
+
+#define BIT_SHIFT_WMAC_RESP_TXRATE_8814B 16
+#define BIT_MASK_WMAC_RESP_TXRATE_8814B 0xff
+#define BIT_WMAC_RESP_TXRATE_8814B(x) \
+ (((x) & BIT_MASK_WMAC_RESP_TXRATE_8814B) \
+ << BIT_SHIFT_WMAC_RESP_TXRATE_8814B)
+#define BITS_WMAC_RESP_TXRATE_8814B \
+ (BIT_MASK_WMAC_RESP_TXRATE_8814B << BIT_SHIFT_WMAC_RESP_TXRATE_8814B)
+#define BIT_CLEAR_WMAC_RESP_TXRATE_8814B(x) \
+ ((x) & (~BITS_WMAC_RESP_TXRATE_8814B))
+#define BIT_GET_WMAC_RESP_TXRATE_8814B(x) \
+ (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8814B) & \
+ BIT_MASK_WMAC_RESP_TXRATE_8814B)
+#define BIT_SET_WMAC_RESP_TXRATE_8814B(x, v) \
+ (BIT_CLEAR_WMAC_RESP_TXRATE_8814B(x) | BIT_WMAC_RESP_TXRATE_8814B(v))
+
+#define BIT_CSI_FORCE_RATE_EN_8814B BIT(15)
+
+#define BIT_SHIFT_CSI_RSC_8814B 13
+#define BIT_MASK_CSI_RSC_8814B 0x3
+#define BIT_CSI_RSC_8814B(x) \
+ (((x) & BIT_MASK_CSI_RSC_8814B) << BIT_SHIFT_CSI_RSC_8814B)
+#define BITS_CSI_RSC_8814B (BIT_MASK_CSI_RSC_8814B << BIT_SHIFT_CSI_RSC_8814B)
+#define BIT_CLEAR_CSI_RSC_8814B(x) ((x) & (~BITS_CSI_RSC_8814B))
+#define BIT_GET_CSI_RSC_8814B(x) \
+ (((x) >> BIT_SHIFT_CSI_RSC_8814B) & BIT_MASK_CSI_RSC_8814B)
+#define BIT_SET_CSI_RSC_8814B(x, v) \
+ (BIT_CLEAR_CSI_RSC_8814B(x) | BIT_CSI_RSC_8814B(v))
+
+#define BIT_CSI_GID_SEL_8814B BIT(12)
+#define BIT_RDCSIMD_FLAG_TRIG_SEL_8814B BIT(11)
+#define BIT_NDPVLD_POS_RST_FFPTR_DIS_V1_8814B BIT(10)
+#define BIT_NDPVLD_PROTECT_RDRDY_DIS_8814B BIT(9)
+#define BIT_RDCSI_EMPTY_APPZERO_8814B BIT(8)
+#define BIT_CSI_RATE_FB_EN_8814B BIT(7)
+#define BIT_RXFIFO_WRPTR_WO_CHKSUM_8814B BIT(6)
+
+/* 2 REG_P2P_RX_BCN_NOA_8814B (P2P RX BEACON NOA REGISTER) */
+#define BIT_NOA_PARSER_EN_8814B BIT(15)
+
+#define BIT_SHIFT_BSSID_SEL_V1_8814B 12
+#define BIT_MASK_BSSID_SEL_V1_8814B 0x7
+#define BIT_BSSID_SEL_V1_8814B(x) \
+ (((x) & BIT_MASK_BSSID_SEL_V1_8814B) << BIT_SHIFT_BSSID_SEL_V1_8814B)
+#define BITS_BSSID_SEL_V1_8814B \
+ (BIT_MASK_BSSID_SEL_V1_8814B << BIT_SHIFT_BSSID_SEL_V1_8814B)
+#define BIT_CLEAR_BSSID_SEL_V1_8814B(x) ((x) & (~BITS_BSSID_SEL_V1_8814B))
+#define BIT_GET_BSSID_SEL_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_BSSID_SEL_V1_8814B) & BIT_MASK_BSSID_SEL_V1_8814B)
+#define BIT_SET_BSSID_SEL_V1_8814B(x, v) \
+ (BIT_CLEAR_BSSID_SEL_V1_8814B(x) | BIT_BSSID_SEL_V1_8814B(v))
+
+#define BIT_SHIFT_P2P_OUI_TYPE_8814B 0
+#define BIT_MASK_P2P_OUI_TYPE_8814B 0xff
+#define BIT_P2P_OUI_TYPE_8814B(x) \
+ (((x) & BIT_MASK_P2P_OUI_TYPE_8814B) << BIT_SHIFT_P2P_OUI_TYPE_8814B)
+#define BITS_P2P_OUI_TYPE_8814B \
+ (BIT_MASK_P2P_OUI_TYPE_8814B << BIT_SHIFT_P2P_OUI_TYPE_8814B)
+#define BIT_CLEAR_P2P_OUI_TYPE_8814B(x) ((x) & (~BITS_P2P_OUI_TYPE_8814B))
+#define BIT_GET_P2P_OUI_TYPE_8814B(x) \
+ (((x) >> BIT_SHIFT_P2P_OUI_TYPE_8814B) & BIT_MASK_P2P_OUI_TYPE_8814B)
+#define BIT_SET_P2P_OUI_TYPE_8814B(x, v) \
+ (BIT_CLEAR_P2P_OUI_TYPE_8814B(x) | BIT_P2P_OUI_TYPE_8814B(v))
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_ASSOCIATED_BFMER0_INFO_8814B (ASSOCIATED BEAMFORMER0 INFO REGISTER) */
+
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8814B 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8814B 0xffffffffL
+#define BIT_R_WMAC_SOUNDING_RXADD_R0_V1_8814B(x) \
+ (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8814B) \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8814B)
+#define BITS_R_WMAC_SOUNDING_RXADD_R0_V1_8814B \
+ (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8814B \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8814B)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1_8814B(x) \
+ ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_V1_8814B))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8814B) & \
+ BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8814B)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_V1_8814B(x, v) \
+ (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1_8814B(x) | \
+ BIT_R_WMAC_SOUNDING_RXADD_R0_V1_8814B(v))
+
+/* 2 REG_ASSOCIATED_BFMER0_INFO_H_8814B */
+
+#define BIT_SHIFT_R_WMAC_TXCSI_AID0_8814B 16
+#define BIT_MASK_R_WMAC_TXCSI_AID0_8814B 0x1ff
+#define BIT_R_WMAC_TXCSI_AID0_8814B(x) \
+ (((x) & BIT_MASK_R_WMAC_TXCSI_AID0_8814B) \
+ << BIT_SHIFT_R_WMAC_TXCSI_AID0_8814B)
+#define BITS_R_WMAC_TXCSI_AID0_8814B \
+ (BIT_MASK_R_WMAC_TXCSI_AID0_8814B << BIT_SHIFT_R_WMAC_TXCSI_AID0_8814B)
+#define BIT_CLEAR_R_WMAC_TXCSI_AID0_8814B(x) \
+ ((x) & (~BITS_R_WMAC_TXCSI_AID0_8814B))
+#define BIT_GET_R_WMAC_TXCSI_AID0_8814B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8814B) & \
+ BIT_MASK_R_WMAC_TXCSI_AID0_8814B)
+#define BIT_SET_R_WMAC_TXCSI_AID0_8814B(x, v) \
+ (BIT_CLEAR_R_WMAC_TXCSI_AID0_8814B(x) | BIT_R_WMAC_TXCSI_AID0_8814B(v))
+
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B 0xffff
+#define BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B(x) \
+ (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B) \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B)
+#define BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B \
+ (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B(x) \
+ ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B) & \
+ BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B(x, v) \
+ (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B(x) | \
+ BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8814B(v))
+
+/* 2 REG_ASSOCIATED_BFMER1_INFO_8814B (ASSOCIATED BEAMFORMER1 INFO REGISTER) */
+
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8814B 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8814B 0xffffffffL
+#define BIT_R_WMAC_SOUNDING_RXADD_R1_V1_8814B(x) \
+ (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8814B) \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8814B)
+#define BITS_R_WMAC_SOUNDING_RXADD_R1_V1_8814B \
+ (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8814B \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8814B)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1_8814B(x) \
+ ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_V1_8814B))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8814B) & \
+ BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8814B)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_V1_8814B(x, v) \
+ (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1_8814B(x) | \
+ BIT_R_WMAC_SOUNDING_RXADD_R1_V1_8814B(v))
+
+/* 2 REG_ASSOCIATED_BFMER1_INFO_H_8814B */
+
+#define BIT_SHIFT_R_WMAC_TXCSI_AID1_8814B 16
+#define BIT_MASK_R_WMAC_TXCSI_AID1_8814B 0x1ff
+#define BIT_R_WMAC_TXCSI_AID1_8814B(x) \
+ (((x) & BIT_MASK_R_WMAC_TXCSI_AID1_8814B) \
+ << BIT_SHIFT_R_WMAC_TXCSI_AID1_8814B)
+#define BITS_R_WMAC_TXCSI_AID1_8814B \
+ (BIT_MASK_R_WMAC_TXCSI_AID1_8814B << BIT_SHIFT_R_WMAC_TXCSI_AID1_8814B)
+#define BIT_CLEAR_R_WMAC_TXCSI_AID1_8814B(x) \
+ ((x) & (~BITS_R_WMAC_TXCSI_AID1_8814B))
+#define BIT_GET_R_WMAC_TXCSI_AID1_8814B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8814B) & \
+ BIT_MASK_R_WMAC_TXCSI_AID1_8814B)
+#define BIT_SET_R_WMAC_TXCSI_AID1_8814B(x, v) \
+ (BIT_CLEAR_R_WMAC_TXCSI_AID1_8814B(x) | BIT_R_WMAC_TXCSI_AID1_8814B(v))
+
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B 0xffff
+#define BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B(x) \
+ (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B) \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B)
+#define BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B \
+ (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B(x) \
+ ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B) & \
+ BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B(x, v) \
+ (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B(x) | \
+ BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8814B(v))
+
+/* 2 REG_TX_CSI_RPT_PARAM_BW20_8814B (TX CSI REPORT PARAMETER REGISTER) */
+
+#define BIT_SHIFT_R_WMAC_BFINFO_20M_1_8814B 16
+#define BIT_MASK_R_WMAC_BFINFO_20M_1_8814B 0xfff
+#define BIT_R_WMAC_BFINFO_20M_1_8814B(x) \
+ (((x) & BIT_MASK_R_WMAC_BFINFO_20M_1_8814B) \
+ << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8814B)
+#define BITS_R_WMAC_BFINFO_20M_1_8814B \
+ (BIT_MASK_R_WMAC_BFINFO_20M_1_8814B \
+ << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8814B)
+#define BIT_CLEAR_R_WMAC_BFINFO_20M_1_8814B(x) \
+ ((x) & (~BITS_R_WMAC_BFINFO_20M_1_8814B))
+#define BIT_GET_R_WMAC_BFINFO_20M_1_8814B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8814B) & \
+ BIT_MASK_R_WMAC_BFINFO_20M_1_8814B)
+#define BIT_SET_R_WMAC_BFINFO_20M_1_8814B(x, v) \
+ (BIT_CLEAR_R_WMAC_BFINFO_20M_1_8814B(x) | \
+ BIT_R_WMAC_BFINFO_20M_1_8814B(v))
+
+#define BIT_SHIFT_R_WMAC_BFINFO_20M_0_8814B 0
+#define BIT_MASK_R_WMAC_BFINFO_20M_0_8814B 0xfff
+#define BIT_R_WMAC_BFINFO_20M_0_8814B(x) \
+ (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8814B) \
+ << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8814B)
+#define BITS_R_WMAC_BFINFO_20M_0_8814B \
+ (BIT_MASK_R_WMAC_BFINFO_20M_0_8814B \
+ << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8814B)
+#define BIT_CLEAR_R_WMAC_BFINFO_20M_0_8814B(x) \
+ ((x) & (~BITS_R_WMAC_BFINFO_20M_0_8814B))
+#define BIT_GET_R_WMAC_BFINFO_20M_0_8814B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8814B) & \
+ BIT_MASK_R_WMAC_BFINFO_20M_0_8814B)
+#define BIT_SET_R_WMAC_BFINFO_20M_0_8814B(x, v) \
+ (BIT_CLEAR_R_WMAC_BFINFO_20M_0_8814B(x) | \
+ BIT_R_WMAC_BFINFO_20M_0_8814B(v))
+
+/* 2 REG_TX_CSI_RPT_PARAM_BW40_8814B (TX CSI REPORT PARAMETER_BW40 REGISTER) */
+
+#define BIT_SHIFT_WMAC_RESP_ANTD_8814B 12
+#define BIT_MASK_WMAC_RESP_ANTD_8814B 0xf
+#define BIT_WMAC_RESP_ANTD_8814B(x) \
+ (((x) & BIT_MASK_WMAC_RESP_ANTD_8814B) \
+ << BIT_SHIFT_WMAC_RESP_ANTD_8814B)
+#define BITS_WMAC_RESP_ANTD_8814B \
+ (BIT_MASK_WMAC_RESP_ANTD_8814B << BIT_SHIFT_WMAC_RESP_ANTD_8814B)
+#define BIT_CLEAR_WMAC_RESP_ANTD_8814B(x) ((x) & (~BITS_WMAC_RESP_ANTD_8814B))
+#define BIT_GET_WMAC_RESP_ANTD_8814B(x) \
+ (((x) >> BIT_SHIFT_WMAC_RESP_ANTD_8814B) & \
+ BIT_MASK_WMAC_RESP_ANTD_8814B)
+#define BIT_SET_WMAC_RESP_ANTD_8814B(x, v) \
+ (BIT_CLEAR_WMAC_RESP_ANTD_8814B(x) | BIT_WMAC_RESP_ANTD_8814B(v))
+
+#define BIT_SHIFT_WMAC_RESP_ANTC_8814B 8
+#define BIT_MASK_WMAC_RESP_ANTC_8814B 0xf
+#define BIT_WMAC_RESP_ANTC_8814B(x) \
+ (((x) & BIT_MASK_WMAC_RESP_ANTC_8814B) \
+ << BIT_SHIFT_WMAC_RESP_ANTC_8814B)
+#define BITS_WMAC_RESP_ANTC_8814B \
+ (BIT_MASK_WMAC_RESP_ANTC_8814B << BIT_SHIFT_WMAC_RESP_ANTC_8814B)
+#define BIT_CLEAR_WMAC_RESP_ANTC_8814B(x) ((x) & (~BITS_WMAC_RESP_ANTC_8814B))
+#define BIT_GET_WMAC_RESP_ANTC_8814B(x) \
+ (((x) >> BIT_SHIFT_WMAC_RESP_ANTC_8814B) & \
+ BIT_MASK_WMAC_RESP_ANTC_8814B)
+#define BIT_SET_WMAC_RESP_ANTC_8814B(x, v) \
+ (BIT_CLEAR_WMAC_RESP_ANTC_8814B(x) | BIT_WMAC_RESP_ANTC_8814B(v))
+
+#define BIT_SHIFT_WMAC_RESP_ANTB_8814B 4
+#define BIT_MASK_WMAC_RESP_ANTB_8814B 0xf
+#define BIT_WMAC_RESP_ANTB_8814B(x) \
+ (((x) & BIT_MASK_WMAC_RESP_ANTB_8814B) \
+ << BIT_SHIFT_WMAC_RESP_ANTB_8814B)
+#define BITS_WMAC_RESP_ANTB_8814B \
+ (BIT_MASK_WMAC_RESP_ANTB_8814B << BIT_SHIFT_WMAC_RESP_ANTB_8814B)
+#define BIT_CLEAR_WMAC_RESP_ANTB_8814B(x) ((x) & (~BITS_WMAC_RESP_ANTB_8814B))
+#define BIT_GET_WMAC_RESP_ANTB_8814B(x) \
+ (((x) >> BIT_SHIFT_WMAC_RESP_ANTB_8814B) & \
+ BIT_MASK_WMAC_RESP_ANTB_8814B)
+#define BIT_SET_WMAC_RESP_ANTB_8814B(x, v) \
+ (BIT_CLEAR_WMAC_RESP_ANTB_8814B(x) | BIT_WMAC_RESP_ANTB_8814B(v))
+
+#define BIT_SHIFT_WMAC_RESP_ANTA_8814B 0
+#define BIT_MASK_WMAC_RESP_ANTA_8814B 0xf
+#define BIT_WMAC_RESP_ANTA_8814B(x) \
+ (((x) & BIT_MASK_WMAC_RESP_ANTA_8814B) \
+ << BIT_SHIFT_WMAC_RESP_ANTA_8814B)
+#define BITS_WMAC_RESP_ANTA_8814B \
+ (BIT_MASK_WMAC_RESP_ANTA_8814B << BIT_SHIFT_WMAC_RESP_ANTA_8814B)
+#define BIT_CLEAR_WMAC_RESP_ANTA_8814B(x) ((x) & (~BITS_WMAC_RESP_ANTA_8814B))
+#define BIT_GET_WMAC_RESP_ANTA_8814B(x) \
+ (((x) >> BIT_SHIFT_WMAC_RESP_ANTA_8814B) & \
+ BIT_MASK_WMAC_RESP_ANTA_8814B)
+#define BIT_SET_WMAC_RESP_ANTA_8814B(x, v) \
+ (BIT_CLEAR_WMAC_RESP_ANTA_8814B(x) | BIT_WMAC_RESP_ANTA_8814B(v))
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_BCN_PSR_RPT2_8814B (BEACON PARSER REPORT REGISTER2) */
+
+#define BIT_SHIFT_DTIM_CNT2_8814B 24
+#define BIT_MASK_DTIM_CNT2_8814B 0xff
+#define BIT_DTIM_CNT2_8814B(x) \
+ (((x) & BIT_MASK_DTIM_CNT2_8814B) << BIT_SHIFT_DTIM_CNT2_8814B)
+#define BITS_DTIM_CNT2_8814B \
+ (BIT_MASK_DTIM_CNT2_8814B << BIT_SHIFT_DTIM_CNT2_8814B)
+#define BIT_CLEAR_DTIM_CNT2_8814B(x) ((x) & (~BITS_DTIM_CNT2_8814B))
+#define BIT_GET_DTIM_CNT2_8814B(x) \
+ (((x) >> BIT_SHIFT_DTIM_CNT2_8814B) & BIT_MASK_DTIM_CNT2_8814B)
+#define BIT_SET_DTIM_CNT2_8814B(x, v) \
+ (BIT_CLEAR_DTIM_CNT2_8814B(x) | BIT_DTIM_CNT2_8814B(v))
+
+#define BIT_SHIFT_DTIM_PERIOD2_8814B 16
+#define BIT_MASK_DTIM_PERIOD2_8814B 0xff
+#define BIT_DTIM_PERIOD2_8814B(x) \
+ (((x) & BIT_MASK_DTIM_PERIOD2_8814B) << BIT_SHIFT_DTIM_PERIOD2_8814B)
+#define BITS_DTIM_PERIOD2_8814B \
+ (BIT_MASK_DTIM_PERIOD2_8814B << BIT_SHIFT_DTIM_PERIOD2_8814B)
+#define BIT_CLEAR_DTIM_PERIOD2_8814B(x) ((x) & (~BITS_DTIM_PERIOD2_8814B))
+#define BIT_GET_DTIM_PERIOD2_8814B(x) \
+ (((x) >> BIT_SHIFT_DTIM_PERIOD2_8814B) & BIT_MASK_DTIM_PERIOD2_8814B)
+#define BIT_SET_DTIM_PERIOD2_8814B(x, v) \
+ (BIT_CLEAR_DTIM_PERIOD2_8814B(x) | BIT_DTIM_PERIOD2_8814B(v))
+
+#define BIT_DTIM2_8814B BIT(15)
+#define BIT_TIM2_8814B BIT(14)
+#define BIT_RPT_VALID_8814B BIT(13)
+
+#define BIT_SHIFT_PS_AID_2_8814B 0
+#define BIT_MASK_PS_AID_2_8814B 0x7ff
+#define BIT_PS_AID_2_8814B(x) \
+ (((x) & BIT_MASK_PS_AID_2_8814B) << BIT_SHIFT_PS_AID_2_8814B)
+#define BITS_PS_AID_2_8814B \
+ (BIT_MASK_PS_AID_2_8814B << BIT_SHIFT_PS_AID_2_8814B)
+#define BIT_CLEAR_PS_AID_2_8814B(x) ((x) & (~BITS_PS_AID_2_8814B))
+#define BIT_GET_PS_AID_2_8814B(x) \
+ (((x) >> BIT_SHIFT_PS_AID_2_8814B) & BIT_MASK_PS_AID_2_8814B)
+#define BIT_SET_PS_AID_2_8814B(x, v) \
+ (BIT_CLEAR_PS_AID_2_8814B(x) | BIT_PS_AID_2_8814B(v))
+
+/* 2 REG_BCN_PSR_RPT3_8814B (BEACON PARSER REPORT REGISTER3) */
+
+#define BIT_SHIFT_DTIM_CNT3_8814B 24
+#define BIT_MASK_DTIM_CNT3_8814B 0xff
+#define BIT_DTIM_CNT3_8814B(x) \
+ (((x) & BIT_MASK_DTIM_CNT3_8814B) << BIT_SHIFT_DTIM_CNT3_8814B)
+#define BITS_DTIM_CNT3_8814B \
+ (BIT_MASK_DTIM_CNT3_8814B << BIT_SHIFT_DTIM_CNT3_8814B)
+#define BIT_CLEAR_DTIM_CNT3_8814B(x) ((x) & (~BITS_DTIM_CNT3_8814B))
+#define BIT_GET_DTIM_CNT3_8814B(x) \
+ (((x) >> BIT_SHIFT_DTIM_CNT3_8814B) & BIT_MASK_DTIM_CNT3_8814B)
+#define BIT_SET_DTIM_CNT3_8814B(x, v) \
+ (BIT_CLEAR_DTIM_CNT3_8814B(x) | BIT_DTIM_CNT3_8814B(v))
+
+#define BIT_SHIFT_DTIM_PERIOD3_8814B 16
+#define BIT_MASK_DTIM_PERIOD3_8814B 0xff
+#define BIT_DTIM_PERIOD3_8814B(x) \
+ (((x) & BIT_MASK_DTIM_PERIOD3_8814B) << BIT_SHIFT_DTIM_PERIOD3_8814B)
+#define BITS_DTIM_PERIOD3_8814B \
+ (BIT_MASK_DTIM_PERIOD3_8814B << BIT_SHIFT_DTIM_PERIOD3_8814B)
+#define BIT_CLEAR_DTIM_PERIOD3_8814B(x) ((x) & (~BITS_DTIM_PERIOD3_8814B))
+#define BIT_GET_DTIM_PERIOD3_8814B(x) \
+ (((x) >> BIT_SHIFT_DTIM_PERIOD3_8814B) & BIT_MASK_DTIM_PERIOD3_8814B)
+#define BIT_SET_DTIM_PERIOD3_8814B(x, v) \
+ (BIT_CLEAR_DTIM_PERIOD3_8814B(x) | BIT_DTIM_PERIOD3_8814B(v))
+
+#define BIT_DTIM3_8814B BIT(15)
+#define BIT_TIM3_8814B BIT(14)
+#define BIT_RPT_VALID_8814B BIT(13)
+
+#define BIT_SHIFT_PS_AID_3_8814B 0
+#define BIT_MASK_PS_AID_3_8814B 0x7ff
+#define BIT_PS_AID_3_8814B(x) \
+ (((x) & BIT_MASK_PS_AID_3_8814B) << BIT_SHIFT_PS_AID_3_8814B)
+#define BITS_PS_AID_3_8814B \
+ (BIT_MASK_PS_AID_3_8814B << BIT_SHIFT_PS_AID_3_8814B)
+#define BIT_CLEAR_PS_AID_3_8814B(x) ((x) & (~BITS_PS_AID_3_8814B))
+#define BIT_GET_PS_AID_3_8814B(x) \
+ (((x) >> BIT_SHIFT_PS_AID_3_8814B) & BIT_MASK_PS_AID_3_8814B)
+#define BIT_SET_PS_AID_3_8814B(x, v) \
+ (BIT_CLEAR_PS_AID_3_8814B(x) | BIT_PS_AID_3_8814B(v))
+
+/* 2 REG_BCN_PSR_RPT4_8814B (BEACON PARSER REPORT REGISTER4) */
+
+#define BIT_SHIFT_DTIM_CNT4_8814B 24
+#define BIT_MASK_DTIM_CNT4_8814B 0xff
+#define BIT_DTIM_CNT4_8814B(x) \
+ (((x) & BIT_MASK_DTIM_CNT4_8814B) << BIT_SHIFT_DTIM_CNT4_8814B)
+#define BITS_DTIM_CNT4_8814B \
+ (BIT_MASK_DTIM_CNT4_8814B << BIT_SHIFT_DTIM_CNT4_8814B)
+#define BIT_CLEAR_DTIM_CNT4_8814B(x) ((x) & (~BITS_DTIM_CNT4_8814B))
+#define BIT_GET_DTIM_CNT4_8814B(x) \
+ (((x) >> BIT_SHIFT_DTIM_CNT4_8814B) & BIT_MASK_DTIM_CNT4_8814B)
+#define BIT_SET_DTIM_CNT4_8814B(x, v) \
+ (BIT_CLEAR_DTIM_CNT4_8814B(x) | BIT_DTIM_CNT4_8814B(v))
+
+#define BIT_SHIFT_DTIM_PERIOD4_8814B 16
+#define BIT_MASK_DTIM_PERIOD4_8814B 0xff
+#define BIT_DTIM_PERIOD4_8814B(x) \
+ (((x) & BIT_MASK_DTIM_PERIOD4_8814B) << BIT_SHIFT_DTIM_PERIOD4_8814B)
+#define BITS_DTIM_PERIOD4_8814B \
+ (BIT_MASK_DTIM_PERIOD4_8814B << BIT_SHIFT_DTIM_PERIOD4_8814B)
+#define BIT_CLEAR_DTIM_PERIOD4_8814B(x) ((x) & (~BITS_DTIM_PERIOD4_8814B))
+#define BIT_GET_DTIM_PERIOD4_8814B(x) \
+ (((x) >> BIT_SHIFT_DTIM_PERIOD4_8814B) & BIT_MASK_DTIM_PERIOD4_8814B)
+#define BIT_SET_DTIM_PERIOD4_8814B(x, v) \
+ (BIT_CLEAR_DTIM_PERIOD4_8814B(x) | BIT_DTIM_PERIOD4_8814B(v))
+
+#define BIT_DTIM4_8814B BIT(15)
+#define BIT_TIM4_8814B BIT(14)
+#define BIT_RPT_VALID_8814B BIT(13)
+
+#define BIT_SHIFT_PS_AID_4_8814B 0
+#define BIT_MASK_PS_AID_4_8814B 0x7ff
+#define BIT_PS_AID_4_8814B(x) \
+ (((x) & BIT_MASK_PS_AID_4_8814B) << BIT_SHIFT_PS_AID_4_8814B)
+#define BITS_PS_AID_4_8814B \
+ (BIT_MASK_PS_AID_4_8814B << BIT_SHIFT_PS_AID_4_8814B)
+#define BIT_CLEAR_PS_AID_4_8814B(x) ((x) & (~BITS_PS_AID_4_8814B))
+#define BIT_GET_PS_AID_4_8814B(x) \
+ (((x) >> BIT_SHIFT_PS_AID_4_8814B) & BIT_MASK_PS_AID_4_8814B)
+#define BIT_SET_PS_AID_4_8814B(x, v) \
+ (BIT_CLEAR_PS_AID_4_8814B(x) | BIT_PS_AID_4_8814B(v))
+
+/* 2 REG_A1_ADDR_MASK_8814B (A1 ADDR MASK REGISTER) */
+
+#define BIT_SHIFT_A1_ADDR_MASK_8814B 0
+#define BIT_MASK_A1_ADDR_MASK_8814B 0xffffffffL
+#define BIT_A1_ADDR_MASK_8814B(x) \
+ (((x) & BIT_MASK_A1_ADDR_MASK_8814B) << BIT_SHIFT_A1_ADDR_MASK_8814B)
+#define BITS_A1_ADDR_MASK_8814B \
+ (BIT_MASK_A1_ADDR_MASK_8814B << BIT_SHIFT_A1_ADDR_MASK_8814B)
+#define BIT_CLEAR_A1_ADDR_MASK_8814B(x) ((x) & (~BITS_A1_ADDR_MASK_8814B))
+#define BIT_GET_A1_ADDR_MASK_8814B(x) \
+ (((x) >> BIT_SHIFT_A1_ADDR_MASK_8814B) & BIT_MASK_A1_ADDR_MASK_8814B)
+#define BIT_SET_A1_ADDR_MASK_8814B(x, v) \
+ (BIT_CLEAR_A1_ADDR_MASK_8814B(x) | BIT_A1_ADDR_MASK_8814B(v))
+
+/* 2 REG_RXPSF_CTRL_8814B */
+#define BIT_RXGCK_FIFOTHR_EN_8814B BIT(28)
+
+#define BIT_SHIFT_RXGCK_VHT_FIFOTHR_8814B 26
+#define BIT_MASK_RXGCK_VHT_FIFOTHR_8814B 0x3
+#define BIT_RXGCK_VHT_FIFOTHR_8814B(x) \
+ (((x) & BIT_MASK_RXGCK_VHT_FIFOTHR_8814B) \
+ << BIT_SHIFT_RXGCK_VHT_FIFOTHR_8814B)
+#define BITS_RXGCK_VHT_FIFOTHR_8814B \
+ (BIT_MASK_RXGCK_VHT_FIFOTHR_8814B << BIT_SHIFT_RXGCK_VHT_FIFOTHR_8814B)
+#define BIT_CLEAR_RXGCK_VHT_FIFOTHR_8814B(x) \
+ ((x) & (~BITS_RXGCK_VHT_FIFOTHR_8814B))
+#define BIT_GET_RXGCK_VHT_FIFOTHR_8814B(x) \
+ (((x) >> BIT_SHIFT_RXGCK_VHT_FIFOTHR_8814B) & \
+ BIT_MASK_RXGCK_VHT_FIFOTHR_8814B)
+#define BIT_SET_RXGCK_VHT_FIFOTHR_8814B(x, v) \
+ (BIT_CLEAR_RXGCK_VHT_FIFOTHR_8814B(x) | BIT_RXGCK_VHT_FIFOTHR_8814B(v))
+
+#define BIT_SHIFT_RXGCK_HT_FIFOTHR_8814B 24
+#define BIT_MASK_RXGCK_HT_FIFOTHR_8814B 0x3
+#define BIT_RXGCK_HT_FIFOTHR_8814B(x) \
+ (((x) & BIT_MASK_RXGCK_HT_FIFOTHR_8814B) \
+ << BIT_SHIFT_RXGCK_HT_FIFOTHR_8814B)
+#define BITS_RXGCK_HT_FIFOTHR_8814B \
+ (BIT_MASK_RXGCK_HT_FIFOTHR_8814B << BIT_SHIFT_RXGCK_HT_FIFOTHR_8814B)
+#define BIT_CLEAR_RXGCK_HT_FIFOTHR_8814B(x) \
+ ((x) & (~BITS_RXGCK_HT_FIFOTHR_8814B))
+#define BIT_GET_RXGCK_HT_FIFOTHR_8814B(x) \
+ (((x) >> BIT_SHIFT_RXGCK_HT_FIFOTHR_8814B) & \
+ BIT_MASK_RXGCK_HT_FIFOTHR_8814B)
+#define BIT_SET_RXGCK_HT_FIFOTHR_8814B(x, v) \
+ (BIT_CLEAR_RXGCK_HT_FIFOTHR_8814B(x) | BIT_RXGCK_HT_FIFOTHR_8814B(v))
+
+#define BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8814B 22
+#define BIT_MASK_RXGCK_OFDM_FIFOTHR_8814B 0x3
+#define BIT_RXGCK_OFDM_FIFOTHR_8814B(x) \
+ (((x) & BIT_MASK_RXGCK_OFDM_FIFOTHR_8814B) \
+ << BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8814B)
+#define BITS_RXGCK_OFDM_FIFOTHR_8814B \
+ (BIT_MASK_RXGCK_OFDM_FIFOTHR_8814B \
+ << BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8814B)
+#define BIT_CLEAR_RXGCK_OFDM_FIFOTHR_8814B(x) \
+ ((x) & (~BITS_RXGCK_OFDM_FIFOTHR_8814B))
+#define BIT_GET_RXGCK_OFDM_FIFOTHR_8814B(x) \
+ (((x) >> BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8814B) & \
+ BIT_MASK_RXGCK_OFDM_FIFOTHR_8814B)
+#define BIT_SET_RXGCK_OFDM_FIFOTHR_8814B(x, v) \
+ (BIT_CLEAR_RXGCK_OFDM_FIFOTHR_8814B(x) | \
+ BIT_RXGCK_OFDM_FIFOTHR_8814B(v))
+
+#define BIT_SHIFT_RXGCK_CCK_FIFOTHR_8814B 20
+#define BIT_MASK_RXGCK_CCK_FIFOTHR_8814B 0x3
+#define BIT_RXGCK_CCK_FIFOTHR_8814B(x) \
+ (((x) & BIT_MASK_RXGCK_CCK_FIFOTHR_8814B) \
+ << BIT_SHIFT_RXGCK_CCK_FIFOTHR_8814B)
+#define BITS_RXGCK_CCK_FIFOTHR_8814B \
+ (BIT_MASK_RXGCK_CCK_FIFOTHR_8814B << BIT_SHIFT_RXGCK_CCK_FIFOTHR_8814B)
+#define BIT_CLEAR_RXGCK_CCK_FIFOTHR_8814B(x) \
+ ((x) & (~BITS_RXGCK_CCK_FIFOTHR_8814B))
+#define BIT_GET_RXGCK_CCK_FIFOTHR_8814B(x) \
+ (((x) >> BIT_SHIFT_RXGCK_CCK_FIFOTHR_8814B) & \
+ BIT_MASK_RXGCK_CCK_FIFOTHR_8814B)
+#define BIT_SET_RXGCK_CCK_FIFOTHR_8814B(x, v) \
+ (BIT_CLEAR_RXGCK_CCK_FIFOTHR_8814B(x) | BIT_RXGCK_CCK_FIFOTHR_8814B(v))
+
+#define BIT_SHIFT_RXGCK_ENTRY_DELAY_8814B 17
+#define BIT_MASK_RXGCK_ENTRY_DELAY_8814B 0x7
+#define BIT_RXGCK_ENTRY_DELAY_8814B(x) \
+ (((x) & BIT_MASK_RXGCK_ENTRY_DELAY_8814B) \
+ << BIT_SHIFT_RXGCK_ENTRY_DELAY_8814B)
+#define BITS_RXGCK_ENTRY_DELAY_8814B \
+ (BIT_MASK_RXGCK_ENTRY_DELAY_8814B << BIT_SHIFT_RXGCK_ENTRY_DELAY_8814B)
+#define BIT_CLEAR_RXGCK_ENTRY_DELAY_8814B(x) \
+ ((x) & (~BITS_RXGCK_ENTRY_DELAY_8814B))
+#define BIT_GET_RXGCK_ENTRY_DELAY_8814B(x) \
+ (((x) >> BIT_SHIFT_RXGCK_ENTRY_DELAY_8814B) & \
+ BIT_MASK_RXGCK_ENTRY_DELAY_8814B)
+#define BIT_SET_RXGCK_ENTRY_DELAY_8814B(x, v) \
+ (BIT_CLEAR_RXGCK_ENTRY_DELAY_8814B(x) | BIT_RXGCK_ENTRY_DELAY_8814B(v))
+
+#define BIT_RXGCK_OFDMCCA_EN_8814B BIT(16)
+
+#define BIT_SHIFT_RXPSF_PKTLENTHR_8814B 13
+#define BIT_MASK_RXPSF_PKTLENTHR_8814B 0x7
+#define BIT_RXPSF_PKTLENTHR_8814B(x) \
+ (((x) & BIT_MASK_RXPSF_PKTLENTHR_8814B) \
+ << BIT_SHIFT_RXPSF_PKTLENTHR_8814B)
+#define BITS_RXPSF_PKTLENTHR_8814B \
+ (BIT_MASK_RXPSF_PKTLENTHR_8814B << BIT_SHIFT_RXPSF_PKTLENTHR_8814B)
+#define BIT_CLEAR_RXPSF_PKTLENTHR_8814B(x) ((x) & (~BITS_RXPSF_PKTLENTHR_8814B))
+#define BIT_GET_RXPSF_PKTLENTHR_8814B(x) \
+ (((x) >> BIT_SHIFT_RXPSF_PKTLENTHR_8814B) & \
+ BIT_MASK_RXPSF_PKTLENTHR_8814B)
+#define BIT_SET_RXPSF_PKTLENTHR_8814B(x, v) \
+ (BIT_CLEAR_RXPSF_PKTLENTHR_8814B(x) | BIT_RXPSF_PKTLENTHR_8814B(v))
+
+#define BIT_RXPSF_CTRLEN_8814B BIT(12)
+#define BIT_RXPSF_VHTCHKEN_8814B BIT(11)
+#define BIT_RXPSF_HTCHKEN_8814B BIT(10)
+#define BIT_RXPSF_OFDMCHKEN_8814B BIT(9)
+#define BIT_RXPSF_CCKCHKEN_8814B BIT(8)
+#define BIT_RXPSF_OFDMRST_8814B BIT(7)
+#define BIT_RXPSF_CCKRST_8814B BIT(6)
+#define BIT_RXPSF_MHCHKEN_8814B BIT(5)
+#define BIT_RXPSF_CONT_ERRCHKEN_8814B BIT(4)
+#define BIT_RXPSF_ALL_ERRCHKEN_8814B BIT(3)
+
+#define BIT_SHIFT_RXPSF_ERRTHR_8814B 0
+#define BIT_MASK_RXPSF_ERRTHR_8814B 0x7
+#define BIT_RXPSF_ERRTHR_8814B(x) \
+ (((x) & BIT_MASK_RXPSF_ERRTHR_8814B) << BIT_SHIFT_RXPSF_ERRTHR_8814B)
+#define BITS_RXPSF_ERRTHR_8814B \
+ (BIT_MASK_RXPSF_ERRTHR_8814B << BIT_SHIFT_RXPSF_ERRTHR_8814B)
+#define BIT_CLEAR_RXPSF_ERRTHR_8814B(x) ((x) & (~BITS_RXPSF_ERRTHR_8814B))
+#define BIT_GET_RXPSF_ERRTHR_8814B(x) \
+ (((x) >> BIT_SHIFT_RXPSF_ERRTHR_8814B) & BIT_MASK_RXPSF_ERRTHR_8814B)
+#define BIT_SET_RXPSF_ERRTHR_8814B(x, v) \
+ (BIT_CLEAR_RXPSF_ERRTHR_8814B(x) | BIT_RXPSF_ERRTHR_8814B(v))
+
+/* 2 REG_RXPSF_TYPE_CTRL_8814B */
+#define BIT_RXPSF_DATA15EN_8814B BIT(31)
+#define BIT_RXPSF_DATA14EN_8814B BIT(30)
+#define BIT_RXPSF_DATA13EN_8814B BIT(29)
+#define BIT_RXPSF_DATA12EN_8814B BIT(28)
+#define BIT_RXPSF_DATA11EN_8814B BIT(27)
+#define BIT_RXPSF_DATA10EN_8814B BIT(26)
+#define BIT_RXPSF_DATA9EN_8814B BIT(25)
+#define BIT_RXPSF_DATA8EN_8814B BIT(24)
+#define BIT_RXPSF_DATA7EN_8814B BIT(23)
+#define BIT_RXPSF_DATA6EN_8814B BIT(22)
+#define BIT_RXPSF_DATA5EN_8814B BIT(21)
+#define BIT_RXPSF_DATA4EN_8814B BIT(20)
+#define BIT_RXPSF_DATA3EN_8814B BIT(19)
+#define BIT_RXPSF_DATA2EN_8814B BIT(18)
+#define BIT_RXPSF_DATA1EN_8814B BIT(17)
+#define BIT_RXPSF_DATA0EN_8814B BIT(16)
+#define BIT_RXPSF_MGT15EN_8814B BIT(15)
+#define BIT_RXPSF_MGT14EN_8814B BIT(14)
+#define BIT_RXPSF_MGT13EN_8814B BIT(13)
+#define BIT_RXPSF_MGT12EN_8814B BIT(12)
+#define BIT_RXPSF_MGT11EN_8814B BIT(11)
+#define BIT_RXPSF_MGT10EN_8814B BIT(10)
+#define BIT_RXPSF_MGT9EN_8814B BIT(9)
+#define BIT_RXPSF_MGT8EN_8814B BIT(8)
+#define BIT_RXPSF_MGT7EN_8814B BIT(7)
+#define BIT_RXPSF_MGT6EN_8814B BIT(6)
+#define BIT_RXPSF_MGT5EN_8814B BIT(5)
+#define BIT_RXPSF_MGT4EN_8814B BIT(4)
+#define BIT_RXPSF_MGT3EN_8814B BIT(3)
+#define BIT_RXPSF_MGT2EN_8814B BIT(2)
+#define BIT_RXPSF_MGT1EN_8814B BIT(1)
+#define BIT_RXPSF_MGT0EN_8814B BIT(0)
+
+/* 2 REG_CAM_ACCESS_CTRL_8814B */
+#define BIT_INDIRECT_ERR_8814B BIT(6)
+#define BIT_DIRECT_ERR_8814B BIT(5)
+#define BIT_DIR_ACCESS_EN_RX_BA_8814B BIT(4)
+#define BIT_DIR_ACCESS_EN_ADDRCAM_8814B BIT(3)
+#define BIT_DIR_ACCESS_EN_KEY_8814B BIT(2)
+#define BIT_DIR_ACCESS_EN_WOWLAN_8814B BIT(1)
+#define BIT_DIR_ACCESS_EN_FW_FILTER_8814B BIT(0)
+
+/* 2 REG_CUT_AMSDU_CTRL_8814B */
+#define BIT__CUT_AMSDU_CHKLEN_EN_8814B BIT(31)
+#define BIT_EN_CUT_AMSDU_8814B BIT(30)
+
+#define BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH_8814B 16
+#define BIT_MASK_CUT_AMSDU_CHKLEN_L_TH_8814B 0xff
+#define BIT_CUT_AMSDU_CHKLEN_L_TH_8814B(x) \
+ (((x) & BIT_MASK_CUT_AMSDU_CHKLEN_L_TH_8814B) \
+ << BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH_8814B)
+#define BITS_CUT_AMSDU_CHKLEN_L_TH_8814B \
+ (BIT_MASK_CUT_AMSDU_CHKLEN_L_TH_8814B \
+ << BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH_8814B)
+#define BIT_CLEAR_CUT_AMSDU_CHKLEN_L_TH_8814B(x) \
+ ((x) & (~BITS_CUT_AMSDU_CHKLEN_L_TH_8814B))
+#define BIT_GET_CUT_AMSDU_CHKLEN_L_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_CUT_AMSDU_CHKLEN_L_TH_8814B) & \
+ BIT_MASK_CUT_AMSDU_CHKLEN_L_TH_8814B)
+#define BIT_SET_CUT_AMSDU_CHKLEN_L_TH_8814B(x, v) \
+ (BIT_CLEAR_CUT_AMSDU_CHKLEN_L_TH_8814B(x) | \
+ BIT_CUT_AMSDU_CHKLEN_L_TH_8814B(v))
+
+#define BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH_8814B 0
+#define BIT_MASK_CUT_AMSDU_CHKLEN_H_TH_8814B 0xffff
+#define BIT_CUT_AMSDU_CHKLEN_H_TH_8814B(x) \
+ (((x) & BIT_MASK_CUT_AMSDU_CHKLEN_H_TH_8814B) \
+ << BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH_8814B)
+#define BITS_CUT_AMSDU_CHKLEN_H_TH_8814B \
+ (BIT_MASK_CUT_AMSDU_CHKLEN_H_TH_8814B \
+ << BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH_8814B)
+#define BIT_CLEAR_CUT_AMSDU_CHKLEN_H_TH_8814B(x) \
+ ((x) & (~BITS_CUT_AMSDU_CHKLEN_H_TH_8814B))
+#define BIT_GET_CUT_AMSDU_CHKLEN_H_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_CUT_AMSDU_CHKLEN_H_TH_8814B) & \
+ BIT_MASK_CUT_AMSDU_CHKLEN_H_TH_8814B)
+#define BIT_SET_CUT_AMSDU_CHKLEN_H_TH_8814B(x, v) \
+ (BIT_CLEAR_CUT_AMSDU_CHKLEN_H_TH_8814B(x) | \
+ BIT_CUT_AMSDU_CHKLEN_H_TH_8814B(v))
+
+/* 2 REG_MACID2_8814B (MAC ID2 REGISTER) */
+
+#define BIT_SHIFT_MACID2_V1_8814B 0
+#define BIT_MASK_MACID2_V1_8814B 0xffffffffL
+#define BIT_MACID2_V1_8814B(x) \
+ (((x) & BIT_MASK_MACID2_V1_8814B) << BIT_SHIFT_MACID2_V1_8814B)
+#define BITS_MACID2_V1_8814B \
+ (BIT_MASK_MACID2_V1_8814B << BIT_SHIFT_MACID2_V1_8814B)
+#define BIT_CLEAR_MACID2_V1_8814B(x) ((x) & (~BITS_MACID2_V1_8814B))
+#define BIT_GET_MACID2_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_MACID2_V1_8814B) & BIT_MASK_MACID2_V1_8814B)
+#define BIT_SET_MACID2_V1_8814B(x, v) \
+ (BIT_CLEAR_MACID2_V1_8814B(x) | BIT_MACID2_V1_8814B(v))
+
+/* 2 REG_MACID2_H_8814B (MAC ID2 REGISTER) */
+
+#define BIT_SHIFT_MACID2_H_V1_8814B 0
+#define BIT_MASK_MACID2_H_V1_8814B 0xffff
+#define BIT_MACID2_H_V1_8814B(x) \
+ (((x) & BIT_MASK_MACID2_H_V1_8814B) << BIT_SHIFT_MACID2_H_V1_8814B)
+#define BITS_MACID2_H_V1_8814B \
+ (BIT_MASK_MACID2_H_V1_8814B << BIT_SHIFT_MACID2_H_V1_8814B)
+#define BIT_CLEAR_MACID2_H_V1_8814B(x) ((x) & (~BITS_MACID2_H_V1_8814B))
+#define BIT_GET_MACID2_H_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_MACID2_H_V1_8814B) & BIT_MASK_MACID2_H_V1_8814B)
+#define BIT_SET_MACID2_H_V1_8814B(x, v) \
+ (BIT_CLEAR_MACID2_H_V1_8814B(x) | BIT_MACID2_H_V1_8814B(v))
+
+/* 2 REG_BSSID2_8814B (BSSID2 REGISTER) */
+
+#define BIT_SHIFT_BSSID2_V1_8814B 0
+#define BIT_MASK_BSSID2_V1_8814B 0xffffffffL
+#define BIT_BSSID2_V1_8814B(x) \
+ (((x) & BIT_MASK_BSSID2_V1_8814B) << BIT_SHIFT_BSSID2_V1_8814B)
+#define BITS_BSSID2_V1_8814B \
+ (BIT_MASK_BSSID2_V1_8814B << BIT_SHIFT_BSSID2_V1_8814B)
+#define BIT_CLEAR_BSSID2_V1_8814B(x) ((x) & (~BITS_BSSID2_V1_8814B))
+#define BIT_GET_BSSID2_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_BSSID2_V1_8814B) & BIT_MASK_BSSID2_V1_8814B)
+#define BIT_SET_BSSID2_V1_8814B(x, v) \
+ (BIT_CLEAR_BSSID2_V1_8814B(x) | BIT_BSSID2_V1_8814B(v))
+
+/* 2 REG_BSSID2_H_8814B (BSSID2 REGISTER) */
+
+#define BIT_SHIFT_BSSID2_H_V1_8814B 0
+#define BIT_MASK_BSSID2_H_V1_8814B 0xffff
+#define BIT_BSSID2_H_V1_8814B(x) \
+ (((x) & BIT_MASK_BSSID2_H_V1_8814B) << BIT_SHIFT_BSSID2_H_V1_8814B)
+#define BITS_BSSID2_H_V1_8814B \
+ (BIT_MASK_BSSID2_H_V1_8814B << BIT_SHIFT_BSSID2_H_V1_8814B)
+#define BIT_CLEAR_BSSID2_H_V1_8814B(x) ((x) & (~BITS_BSSID2_H_V1_8814B))
+#define BIT_GET_BSSID2_H_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_BSSID2_H_V1_8814B) & BIT_MASK_BSSID2_H_V1_8814B)
+#define BIT_SET_BSSID2_H_V1_8814B(x, v) \
+ (BIT_CLEAR_BSSID2_H_V1_8814B(x) | BIT_BSSID2_H_V1_8814B(v))
+
+/* 2 REG_MACID3_8814B (MAC ID3 REGISTER) */
+
+#define BIT_SHIFT_MACID3_V1_8814B 0
+#define BIT_MASK_MACID3_V1_8814B 0xffffffffL
+#define BIT_MACID3_V1_8814B(x) \
+ (((x) & BIT_MASK_MACID3_V1_8814B) << BIT_SHIFT_MACID3_V1_8814B)
+#define BITS_MACID3_V1_8814B \
+ (BIT_MASK_MACID3_V1_8814B << BIT_SHIFT_MACID3_V1_8814B)
+#define BIT_CLEAR_MACID3_V1_8814B(x) ((x) & (~BITS_MACID3_V1_8814B))
+#define BIT_GET_MACID3_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_MACID3_V1_8814B) & BIT_MASK_MACID3_V1_8814B)
+#define BIT_SET_MACID3_V1_8814B(x, v) \
+ (BIT_CLEAR_MACID3_V1_8814B(x) | BIT_MACID3_V1_8814B(v))
+
+/* 2 REG_MACID3_H_8814B (MAC ID3 REGISTER) */
+
+#define BIT_SHIFT_MACID3_H_V1_8814B 0
+#define BIT_MASK_MACID3_H_V1_8814B 0xffff
+#define BIT_MACID3_H_V1_8814B(x) \
+ (((x) & BIT_MASK_MACID3_H_V1_8814B) << BIT_SHIFT_MACID3_H_V1_8814B)
+#define BITS_MACID3_H_V1_8814B \
+ (BIT_MASK_MACID3_H_V1_8814B << BIT_SHIFT_MACID3_H_V1_8814B)
+#define BIT_CLEAR_MACID3_H_V1_8814B(x) ((x) & (~BITS_MACID3_H_V1_8814B))
+#define BIT_GET_MACID3_H_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_MACID3_H_V1_8814B) & BIT_MASK_MACID3_H_V1_8814B)
+#define BIT_SET_MACID3_H_V1_8814B(x, v) \
+ (BIT_CLEAR_MACID3_H_V1_8814B(x) | BIT_MACID3_H_V1_8814B(v))
+
+/* 2 REG_BSSID3_8814B (BSSID3 REGISTER) */
+
+#define BIT_SHIFT_BSSID3_V1_8814B 0
+#define BIT_MASK_BSSID3_V1_8814B 0xffffffffL
+#define BIT_BSSID3_V1_8814B(x) \
+ (((x) & BIT_MASK_BSSID3_V1_8814B) << BIT_SHIFT_BSSID3_V1_8814B)
+#define BITS_BSSID3_V1_8814B \
+ (BIT_MASK_BSSID3_V1_8814B << BIT_SHIFT_BSSID3_V1_8814B)
+#define BIT_CLEAR_BSSID3_V1_8814B(x) ((x) & (~BITS_BSSID3_V1_8814B))
+#define BIT_GET_BSSID3_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_BSSID3_V1_8814B) & BIT_MASK_BSSID3_V1_8814B)
+#define BIT_SET_BSSID3_V1_8814B(x, v) \
+ (BIT_CLEAR_BSSID3_V1_8814B(x) | BIT_BSSID3_V1_8814B(v))
+
+/* 2 REG_BSSID3_H_8814B (BSSID3 REGISTER) */
+
+#define BIT_SHIFT_BSSID3_H_V1_8814B 0
+#define BIT_MASK_BSSID3_H_V1_8814B 0xffff
+#define BIT_BSSID3_H_V1_8814B(x) \
+ (((x) & BIT_MASK_BSSID3_H_V1_8814B) << BIT_SHIFT_BSSID3_H_V1_8814B)
+#define BITS_BSSID3_H_V1_8814B \
+ (BIT_MASK_BSSID3_H_V1_8814B << BIT_SHIFT_BSSID3_H_V1_8814B)
+#define BIT_CLEAR_BSSID3_H_V1_8814B(x) ((x) & (~BITS_BSSID3_H_V1_8814B))
+#define BIT_GET_BSSID3_H_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_BSSID3_H_V1_8814B) & BIT_MASK_BSSID3_H_V1_8814B)
+#define BIT_SET_BSSID3_H_V1_8814B(x, v) \
+ (BIT_CLEAR_BSSID3_H_V1_8814B(x) | BIT_BSSID3_H_V1_8814B(v))
+
+/* 2 REG_MACID4_8814B (MAC ID4 REGISTER) */
+
+#define BIT_SHIFT_MACID4_V1_8814B 0
+#define BIT_MASK_MACID4_V1_8814B 0xffffffffL
+#define BIT_MACID4_V1_8814B(x) \
+ (((x) & BIT_MASK_MACID4_V1_8814B) << BIT_SHIFT_MACID4_V1_8814B)
+#define BITS_MACID4_V1_8814B \
+ (BIT_MASK_MACID4_V1_8814B << BIT_SHIFT_MACID4_V1_8814B)
+#define BIT_CLEAR_MACID4_V1_8814B(x) ((x) & (~BITS_MACID4_V1_8814B))
+#define BIT_GET_MACID4_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_MACID4_V1_8814B) & BIT_MASK_MACID4_V1_8814B)
+#define BIT_SET_MACID4_V1_8814B(x, v) \
+ (BIT_CLEAR_MACID4_V1_8814B(x) | BIT_MACID4_V1_8814B(v))
+
+/* 2 REG_MACID4_H_8814B (MAC ID4 REGISTER) */
+
+#define BIT_SHIFT_MACID4_H_V1_8814B 0
+#define BIT_MASK_MACID4_H_V1_8814B 0xffff
+#define BIT_MACID4_H_V1_8814B(x) \
+ (((x) & BIT_MASK_MACID4_H_V1_8814B) << BIT_SHIFT_MACID4_H_V1_8814B)
+#define BITS_MACID4_H_V1_8814B \
+ (BIT_MASK_MACID4_H_V1_8814B << BIT_SHIFT_MACID4_H_V1_8814B)
+#define BIT_CLEAR_MACID4_H_V1_8814B(x) ((x) & (~BITS_MACID4_H_V1_8814B))
+#define BIT_GET_MACID4_H_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_MACID4_H_V1_8814B) & BIT_MASK_MACID4_H_V1_8814B)
+#define BIT_SET_MACID4_H_V1_8814B(x, v) \
+ (BIT_CLEAR_MACID4_H_V1_8814B(x) | BIT_MACID4_H_V1_8814B(v))
+
+/* 2 REG_BSSID4_8814B (BSSID4 REGISTER) */
+
+#define BIT_SHIFT_BSSID4_V1_8814B 0
+#define BIT_MASK_BSSID4_V1_8814B 0xffffffffL
+#define BIT_BSSID4_V1_8814B(x) \
+ (((x) & BIT_MASK_BSSID4_V1_8814B) << BIT_SHIFT_BSSID4_V1_8814B)
+#define BITS_BSSID4_V1_8814B \
+ (BIT_MASK_BSSID4_V1_8814B << BIT_SHIFT_BSSID4_V1_8814B)
+#define BIT_CLEAR_BSSID4_V1_8814B(x) ((x) & (~BITS_BSSID4_V1_8814B))
+#define BIT_GET_BSSID4_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_BSSID4_V1_8814B) & BIT_MASK_BSSID4_V1_8814B)
+#define BIT_SET_BSSID4_V1_8814B(x, v) \
+ (BIT_CLEAR_BSSID4_V1_8814B(x) | BIT_BSSID4_V1_8814B(v))
+
+/* 2 REG_BSSID4_H_8814B (BSSID4 REGISTER) */
+
+#define BIT_SHIFT_BSSID4_H_V1_8814B 0
+#define BIT_MASK_BSSID4_H_V1_8814B 0xffff
+#define BIT_BSSID4_H_V1_8814B(x) \
+ (((x) & BIT_MASK_BSSID4_H_V1_8814B) << BIT_SHIFT_BSSID4_H_V1_8814B)
+#define BITS_BSSID4_H_V1_8814B \
+ (BIT_MASK_BSSID4_H_V1_8814B << BIT_SHIFT_BSSID4_H_V1_8814B)
+#define BIT_CLEAR_BSSID4_H_V1_8814B(x) ((x) & (~BITS_BSSID4_H_V1_8814B))
+#define BIT_GET_BSSID4_H_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_BSSID4_H_V1_8814B) & BIT_MASK_BSSID4_H_V1_8814B)
+#define BIT_SET_BSSID4_H_V1_8814B(x, v) \
+ (BIT_CLEAR_BSSID4_H_V1_8814B(x) | BIT_BSSID4_H_V1_8814B(v))
+
+/* 2 REG_NOA_REPORT_8814B */
+
+#define BIT_SHIFT_NOA_RPT_8814B 0
+#define BIT_MASK_NOA_RPT_8814B 0xffffffffL
+#define BIT_NOA_RPT_8814B(x) \
+ (((x) & BIT_MASK_NOA_RPT_8814B) << BIT_SHIFT_NOA_RPT_8814B)
+#define BITS_NOA_RPT_8814B (BIT_MASK_NOA_RPT_8814B << BIT_SHIFT_NOA_RPT_8814B)
+#define BIT_CLEAR_NOA_RPT_8814B(x) ((x) & (~BITS_NOA_RPT_8814B))
+#define BIT_GET_NOA_RPT_8814B(x) \
+ (((x) >> BIT_SHIFT_NOA_RPT_8814B) & BIT_MASK_NOA_RPT_8814B)
+#define BIT_SET_NOA_RPT_8814B(x, v) \
+ (BIT_CLEAR_NOA_RPT_8814B(x) | BIT_NOA_RPT_8814B(v))
+
+/* 2 REG_NOA_REPORT_1_8814B */
+
+#define BIT_SHIFT_NOA_RPT_1_8814B 0
+#define BIT_MASK_NOA_RPT_1_8814B 0xffffffffL
+#define BIT_NOA_RPT_1_8814B(x) \
+ (((x) & BIT_MASK_NOA_RPT_1_8814B) << BIT_SHIFT_NOA_RPT_1_8814B)
+#define BITS_NOA_RPT_1_8814B \
+ (BIT_MASK_NOA_RPT_1_8814B << BIT_SHIFT_NOA_RPT_1_8814B)
+#define BIT_CLEAR_NOA_RPT_1_8814B(x) ((x) & (~BITS_NOA_RPT_1_8814B))
+#define BIT_GET_NOA_RPT_1_8814B(x) \
+ (((x) >> BIT_SHIFT_NOA_RPT_1_8814B) & BIT_MASK_NOA_RPT_1_8814B)
+#define BIT_SET_NOA_RPT_1_8814B(x, v) \
+ (BIT_CLEAR_NOA_RPT_1_8814B(x) | BIT_NOA_RPT_1_8814B(v))
+
+/* 2 REG_NOA_REPORT_2_8814B */
+
+#define BIT_SHIFT_NOA_RPT_2_8814B 0
+#define BIT_MASK_NOA_RPT_2_8814B 0xffffffffL
+#define BIT_NOA_RPT_2_8814B(x) \
+ (((x) & BIT_MASK_NOA_RPT_2_8814B) << BIT_SHIFT_NOA_RPT_2_8814B)
+#define BITS_NOA_RPT_2_8814B \
+ (BIT_MASK_NOA_RPT_2_8814B << BIT_SHIFT_NOA_RPT_2_8814B)
+#define BIT_CLEAR_NOA_RPT_2_8814B(x) ((x) & (~BITS_NOA_RPT_2_8814B))
+#define BIT_GET_NOA_RPT_2_8814B(x) \
+ (((x) >> BIT_SHIFT_NOA_RPT_2_8814B) & BIT_MASK_NOA_RPT_2_8814B)
+#define BIT_SET_NOA_RPT_2_8814B(x, v) \
+ (BIT_CLEAR_NOA_RPT_2_8814B(x) | BIT_NOA_RPT_2_8814B(v))
+
+/* 2 REG_NOA_REPORT_3_8814B */
+
+#define BIT_SHIFT_NOA_RPT_3_8814B 0
+#define BIT_MASK_NOA_RPT_3_8814B 0xff
+#define BIT_NOA_RPT_3_8814B(x) \
+ (((x) & BIT_MASK_NOA_RPT_3_8814B) << BIT_SHIFT_NOA_RPT_3_8814B)
+#define BITS_NOA_RPT_3_8814B \
+ (BIT_MASK_NOA_RPT_3_8814B << BIT_SHIFT_NOA_RPT_3_8814B)
+#define BIT_CLEAR_NOA_RPT_3_8814B(x) ((x) & (~BITS_NOA_RPT_3_8814B))
+#define BIT_GET_NOA_RPT_3_8814B(x) \
+ (((x) >> BIT_SHIFT_NOA_RPT_3_8814B) & BIT_MASK_NOA_RPT_3_8814B)
+#define BIT_SET_NOA_RPT_3_8814B(x, v) \
+ (BIT_CLEAR_NOA_RPT_3_8814B(x) | BIT_NOA_RPT_3_8814B(v))
+
+/* 2 REG_PWRBIT_SETTING_8814B */
+#define BIT_CLI3_WMAC_TCRPWRMGT_HWCTL_EN_8814B BIT(15)
+#define BIT_CLI3_WMAC_TCRPWRMGT_HWDATA_EN_8814B BIT(14)
+#define BIT_CLI3_WMAC_TCRPWRMGT_HWACT_EN_8814B BIT(13)
+#define BIT_CLI3_PWR_ST_V1_8814B BIT(12)
+#define BIT_CLI2_WMAC_TCRPWRMGT_HWCTL_EN_8814B BIT(11)
+#define BIT_CLI2_WMAC_TCRPWRMGT_HWDATA_EN_8814B BIT(10)
+#define BIT_CLI2_WMAC_TCRPWRMGT_HWACT_EN_8814B BIT(9)
+#define BIT_CLI2_PWR_ST_V1_8814B BIT(8)
+#define BIT_CLI1_WMAC_TCRPWRMGT_HWCTL_EN_8814B BIT(7)
+#define BIT_CLI1_WMAC_TCRPWRMGT_HWDATA_EN_8814B BIT(6)
+#define BIT_CLI1_WMAC_TCRPWRMGT_HWACT_EN_8814B BIT(5)
+#define BIT_CLI1_PWR_ST_V1_8814B BIT(4)
+#define BIT_CLI0_WMAC_TCRPWRMGT_HWCTL_EN_8814B BIT(3)
+#define BIT_CLI0_WMAC_TCRPWRMGT_HWDATA_EN_8814B BIT(2)
+#define BIT_CLI0_WMAC_TCRPWRMGT_HWACT_EN_8814B BIT(1)
+#define BIT_CLI0_PWR_ST_V1_8814B BIT(0)
+
+/* 2 REG_GENERAL_OPTION_8814B */
+#define BIT_PATTERN_MATCH_FIX_EN_8814B BIT(3)
+#define BIT_TXSERV_FIELD_SEL_8814B BIT(2)
+#define BIT_RXVHT_LEN_SEL_8814B BIT(1)
+#define BIT_RXMIC_PROTECT_EN_8814B BIT(0)
+
+/* 2 REG_FWPHYFF_RCR_8814B */
+#define BIT_RCR2_AAMSDU_8814B BIT(25)
+#define BIT_RCR2_CBSSID_BCN_8814B BIT(24)
+#define BIT_RCR2_ACRC32_8814B BIT(23)
+#define BIT_RCR2_TA_BCN_8814B BIT(22)
+#define BIT_RCR2_CBSSID_DATA_8814B BIT(21)
+#define BIT_RCR2_ADD3_8814B BIT(20)
+#define BIT_RCR2_AB_8814B BIT(19)
+#define BIT_RCR2_AM_8814B BIT(18)
+#define BIT_RCR2_APM_8814B BIT(17)
+#define BIT_RCR2_AAP_8814B BIT(16)
+#define BIT_RCR1_AAMSDU_8814B BIT(9)
+#define BIT_RCR1_CBSSID_BCN_8814B BIT(8)
+#define BIT_RCR1_ACRC32_8814B BIT(7)
+#define BIT_RCR1_TA_BCN_8814B BIT(6)
+#define BIT_RCR1_CBSSID_DATA_8814B BIT(5)
+#define BIT_RCR1_ADD3_8814B BIT(4)
+#define BIT_RCR1_AB_8814B BIT(3)
+#define BIT_RCR1_AM_8814B BIT(2)
+#define BIT_RCR1_APM_8814B BIT(1)
+#define BIT_RCR1_AAP_8814B BIT(0)
+
+/* 2 REG_ADDRCAM_WRITE_CONTENT_8814B */
+
+#define BIT_SHIFT_ADDRCAM_WDATA_8814B 0
+#define BIT_MASK_ADDRCAM_WDATA_8814B 0xffffffffL
+#define BIT_ADDRCAM_WDATA_8814B(x) \
+ (((x) & BIT_MASK_ADDRCAM_WDATA_8814B) << BIT_SHIFT_ADDRCAM_WDATA_8814B)
+#define BITS_ADDRCAM_WDATA_8814B \
+ (BIT_MASK_ADDRCAM_WDATA_8814B << BIT_SHIFT_ADDRCAM_WDATA_8814B)
+#define BIT_CLEAR_ADDRCAM_WDATA_8814B(x) ((x) & (~BITS_ADDRCAM_WDATA_8814B))
+#define BIT_GET_ADDRCAM_WDATA_8814B(x) \
+ (((x) >> BIT_SHIFT_ADDRCAM_WDATA_8814B) & BIT_MASK_ADDRCAM_WDATA_8814B)
+#define BIT_SET_ADDRCAM_WDATA_8814B(x, v) \
+ (BIT_CLEAR_ADDRCAM_WDATA_8814B(x) | BIT_ADDRCAM_WDATA_8814B(v))
+
+/* 2 REG_ADDRCAM_READ_CONTENT_8814B */
+
+#define BIT_SHIFT_ADDRCAM_RDATA_8814B 0
+#define BIT_MASK_ADDRCAM_RDATA_8814B 0xffffffffL
+#define BIT_ADDRCAM_RDATA_8814B(x) \
+ (((x) & BIT_MASK_ADDRCAM_RDATA_8814B) << BIT_SHIFT_ADDRCAM_RDATA_8814B)
+#define BITS_ADDRCAM_RDATA_8814B \
+ (BIT_MASK_ADDRCAM_RDATA_8814B << BIT_SHIFT_ADDRCAM_RDATA_8814B)
+#define BIT_CLEAR_ADDRCAM_RDATA_8814B(x) ((x) & (~BITS_ADDRCAM_RDATA_8814B))
+#define BIT_GET_ADDRCAM_RDATA_8814B(x) \
+ (((x) >> BIT_SHIFT_ADDRCAM_RDATA_8814B) & BIT_MASK_ADDRCAM_RDATA_8814B)
+#define BIT_SET_ADDRCAM_RDATA_8814B(x, v) \
+ (BIT_CLEAR_ADDRCAM_RDATA_8814B(x) | BIT_ADDRCAM_RDATA_8814B(v))
+
+/* 2 REG_ADDRCAM_CFG_8814B */
+#define BIT_ADDRCAM_POLL_8814B BIT(31)
+#define BIT__ADDRCAM_WT_EN_8814B BIT(30)
+#define BIT_CLRADDRCAM_8814B BIT(29)
+
+#define BIT_SHIFT__ADDRCAM_ADDR_8814B 8
+#define BIT_MASK__ADDRCAM_ADDR_8814B 0x3ff
+#define BIT__ADDRCAM_ADDR_8814B(x) \
+ (((x) & BIT_MASK__ADDRCAM_ADDR_8814B) << BIT_SHIFT__ADDRCAM_ADDR_8814B)
+#define BITS__ADDRCAM_ADDR_8814B \
+ (BIT_MASK__ADDRCAM_ADDR_8814B << BIT_SHIFT__ADDRCAM_ADDR_8814B)
+#define BIT_CLEAR__ADDRCAM_ADDR_8814B(x) ((x) & (~BITS__ADDRCAM_ADDR_8814B))
+#define BIT_GET__ADDRCAM_ADDR_8814B(x) \
+ (((x) >> BIT_SHIFT__ADDRCAM_ADDR_8814B) & BIT_MASK__ADDRCAM_ADDR_8814B)
+#define BIT_SET__ADDRCAM_ADDR_8814B(x, v) \
+ (BIT_CLEAR__ADDRCAM_ADDR_8814B(x) | BIT__ADDRCAM_ADDR_8814B(v))
+
+#define BIT_SHIFT_ADDRCAM_RANGE_8814B 0
+#define BIT_MASK_ADDRCAM_RANGE_8814B 0x7f
+#define BIT_ADDRCAM_RANGE_8814B(x) \
+ (((x) & BIT_MASK_ADDRCAM_RANGE_8814B) << BIT_SHIFT_ADDRCAM_RANGE_8814B)
+#define BITS_ADDRCAM_RANGE_8814B \
+ (BIT_MASK_ADDRCAM_RANGE_8814B << BIT_SHIFT_ADDRCAM_RANGE_8814B)
+#define BIT_CLEAR_ADDRCAM_RANGE_8814B(x) ((x) & (~BITS_ADDRCAM_RANGE_8814B))
+#define BIT_GET_ADDRCAM_RANGE_8814B(x) \
+ (((x) >> BIT_SHIFT_ADDRCAM_RANGE_8814B) & BIT_MASK_ADDRCAM_RANGE_8814B)
+#define BIT_SET_ADDRCAM_RANGE_8814B(x, v) \
+ (BIT_CLEAR_ADDRCAM_RANGE_8814B(x) | BIT_ADDRCAM_RANGE_8814B(v))
+
+/* 2 REG_CSI_RRSR_8814B */
+#define BIT_CSI_LDPC_EN_8814B BIT(29)
+#define BIT_CSI_STBC_EN_8814B BIT(28)
+
+#define BIT_SHIFT_CSI_RRSC_BITMAP_8814B 4
+#define BIT_MASK_CSI_RRSC_BITMAP_8814B 0xffffff
+#define BIT_CSI_RRSC_BITMAP_8814B(x) \
+ (((x) & BIT_MASK_CSI_RRSC_BITMAP_8814B) \
+ << BIT_SHIFT_CSI_RRSC_BITMAP_8814B)
+#define BITS_CSI_RRSC_BITMAP_8814B \
+ (BIT_MASK_CSI_RRSC_BITMAP_8814B << BIT_SHIFT_CSI_RRSC_BITMAP_8814B)
+#define BIT_CLEAR_CSI_RRSC_BITMAP_8814B(x) ((x) & (~BITS_CSI_RRSC_BITMAP_8814B))
+#define BIT_GET_CSI_RRSC_BITMAP_8814B(x) \
+ (((x) >> BIT_SHIFT_CSI_RRSC_BITMAP_8814B) & \
+ BIT_MASK_CSI_RRSC_BITMAP_8814B)
+#define BIT_SET_CSI_RRSC_BITMAP_8814B(x, v) \
+ (BIT_CLEAR_CSI_RRSC_BITMAP_8814B(x) | BIT_CSI_RRSC_BITMAP_8814B(v))
+
+#define BIT_SHIFT_OFDM_LEN_TH_8814B 0
+#define BIT_MASK_OFDM_LEN_TH_8814B 0xf
+#define BIT_OFDM_LEN_TH_8814B(x) \
+ (((x) & BIT_MASK_OFDM_LEN_TH_8814B) << BIT_SHIFT_OFDM_LEN_TH_8814B)
+#define BITS_OFDM_LEN_TH_8814B \
+ (BIT_MASK_OFDM_LEN_TH_8814B << BIT_SHIFT_OFDM_LEN_TH_8814B)
+#define BIT_CLEAR_OFDM_LEN_TH_8814B(x) ((x) & (~BITS_OFDM_LEN_TH_8814B))
+#define BIT_GET_OFDM_LEN_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_OFDM_LEN_TH_8814B) & BIT_MASK_OFDM_LEN_TH_8814B)
+#define BIT_SET_OFDM_LEN_TH_8814B(x, v) \
+ (BIT_CLEAR_OFDM_LEN_TH_8814B(x) | BIT_OFDM_LEN_TH_8814B(v))
+
+/* 2 REG_MU_BF_OPTION_8814B */
+#define BIT_WMAC_RESP_NONSTA1_DIS_8814B BIT(7)
+#define BIT_WMAC_TXMU_ACKPOLICY_EN_8814B BIT(6)
+
+#define BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8814B 4
+#define BIT_MASK_WMAC_TXMU_ACKPOLICY_8814B 0x3
+#define BIT_WMAC_TXMU_ACKPOLICY_8814B(x) \
+ (((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8814B) \
+ << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8814B)
+#define BITS_WMAC_TXMU_ACKPOLICY_8814B \
+ (BIT_MASK_WMAC_TXMU_ACKPOLICY_8814B \
+ << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8814B)
+#define BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8814B(x) \
+ ((x) & (~BITS_WMAC_TXMU_ACKPOLICY_8814B))
+#define BIT_GET_WMAC_TXMU_ACKPOLICY_8814B(x) \
+ (((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8814B) & \
+ BIT_MASK_WMAC_TXMU_ACKPOLICY_8814B)
+#define BIT_SET_WMAC_TXMU_ACKPOLICY_8814B(x, v) \
+ (BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8814B(x) | \
+ BIT_WMAC_TXMU_ACKPOLICY_8814B(v))
+
+#define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8814B 1
+#define BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8814B 0x7
+#define BIT_WMAC_MU_BFEE_PORT_SEL_8814B(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8814B) \
+ << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8814B)
+#define BITS_WMAC_MU_BFEE_PORT_SEL_8814B \
+ (BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8814B \
+ << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8814B)
+#define BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8814B(x) \
+ ((x) & (~BITS_WMAC_MU_BFEE_PORT_SEL_8814B))
+#define BIT_GET_WMAC_MU_BFEE_PORT_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8814B) & \
+ BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8814B)
+#define BIT_SET_WMAC_MU_BFEE_PORT_SEL_8814B(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8814B(x) | \
+ BIT_WMAC_MU_BFEE_PORT_SEL_8814B(v))
+
+#define BIT_WMAC_MU_BFEE_DIS_8814B BIT(0)
+
+/* 2 REG_WMAC_PAUSE_BB_CLR_TH_8814B */
+
+#define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8814B 0
+#define BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8814B 0xff
+#define BIT_WMAC_PAUSE_BB_CLR_TH_8814B(x) \
+ (((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8814B) \
+ << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8814B)
+#define BITS_WMAC_PAUSE_BB_CLR_TH_8814B \
+ (BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8814B \
+ << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8814B)
+#define BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8814B(x) \
+ ((x) & (~BITS_WMAC_PAUSE_BB_CLR_TH_8814B))
+#define BIT_GET_WMAC_PAUSE_BB_CLR_TH_8814B(x) \
+ (((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8814B) & \
+ BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8814B)
+#define BIT_SET_WMAC_PAUSE_BB_CLR_TH_8814B(x, v) \
+ (BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8814B(x) | \
+ BIT_WMAC_PAUSE_BB_CLR_TH_8814B(v))
+
+/* 2 REG_WMAC_MULBK_BUF_8814B */
+
+#define BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8814B 0
+#define BIT_MASK_WMAC_MULBK_PAGE_SIZE_8814B 0xff
+#define BIT_WMAC_MULBK_PAGE_SIZE_8814B(x) \
+ (((x) & BIT_MASK_WMAC_MULBK_PAGE_SIZE_8814B) \
+ << BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8814B)
+#define BITS_WMAC_MULBK_PAGE_SIZE_8814B \
+ (BIT_MASK_WMAC_MULBK_PAGE_SIZE_8814B \
+ << BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8814B)
+#define BIT_CLEAR_WMAC_MULBK_PAGE_SIZE_8814B(x) \
+ ((x) & (~BITS_WMAC_MULBK_PAGE_SIZE_8814B))
+#define BIT_GET_WMAC_MULBK_PAGE_SIZE_8814B(x) \
+ (((x) >> BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8814B) & \
+ BIT_MASK_WMAC_MULBK_PAGE_SIZE_8814B)
+#define BIT_SET_WMAC_MULBK_PAGE_SIZE_8814B(x, v) \
+ (BIT_CLEAR_WMAC_MULBK_PAGE_SIZE_8814B(x) | \
+ BIT_WMAC_MULBK_PAGE_SIZE_8814B(v))
+
+/* 2 REG_WMAC_MU_OPTION_8814B */
+#define BIT_NOCHK_BFPOLL_BMP_8814B BIT(7)
+
+/* 2 REG_WMAC_MU_BF_CTL_8814B */
+#define BIT_WMAC_INVLD_BFPRT_CHK_8814B BIT(15)
+#define BIT_WMAC_RETXBFRPTSEQ_UPD_8814B BIT(14)
+
+#define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8814B 12
+#define BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8814B 0x3
+#define BIT_WMAC_MU_BFRPTSEG_SEL_8814B(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8814B) \
+ << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8814B)
+#define BITS_WMAC_MU_BFRPTSEG_SEL_8814B \
+ (BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8814B \
+ << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8814B)
+#define BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8814B(x) \
+ ((x) & (~BITS_WMAC_MU_BFRPTSEG_SEL_8814B))
+#define BIT_GET_WMAC_MU_BFRPTSEG_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8814B) & \
+ BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8814B)
+#define BIT_SET_WMAC_MU_BFRPTSEG_SEL_8814B(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8814B(x) | \
+ BIT_WMAC_MU_BFRPTSEG_SEL_8814B(v))
+
+#define BIT_SHIFT_WMAC_MU_BF_MYAID_8814B 0
+#define BIT_MASK_WMAC_MU_BF_MYAID_8814B 0xfff
+#define BIT_WMAC_MU_BF_MYAID_8814B(x) \
+ (((x) & BIT_MASK_WMAC_MU_BF_MYAID_8814B) \
+ << BIT_SHIFT_WMAC_MU_BF_MYAID_8814B)
+#define BITS_WMAC_MU_BF_MYAID_8814B \
+ (BIT_MASK_WMAC_MU_BF_MYAID_8814B << BIT_SHIFT_WMAC_MU_BF_MYAID_8814B)
+#define BIT_CLEAR_WMAC_MU_BF_MYAID_8814B(x) \
+ ((x) & (~BITS_WMAC_MU_BF_MYAID_8814B))
+#define BIT_GET_WMAC_MU_BF_MYAID_8814B(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID_8814B) & \
+ BIT_MASK_WMAC_MU_BF_MYAID_8814B)
+#define BIT_SET_WMAC_MU_BF_MYAID_8814B(x, v) \
+ (BIT_CLEAR_WMAC_MU_BF_MYAID_8814B(x) | BIT_WMAC_MU_BF_MYAID_8814B(v))
+
+/* 2 REG_WMAC_MU_BFRPT_PARA_8814B */
+
+#define BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8814B 13
+#define BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8814B 0x7
+#define BIT_BFRPT_PARA_USERID_SEL_V1_8814B(x) \
+ (((x) & BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8814B) \
+ << BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8814B)
+#define BITS_BFRPT_PARA_USERID_SEL_V1_8814B \
+ (BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8814B \
+ << BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8814B)
+#define BIT_CLEAR_BFRPT_PARA_USERID_SEL_V1_8814B(x) \
+ ((x) & (~BITS_BFRPT_PARA_USERID_SEL_V1_8814B))
+#define BIT_GET_BFRPT_PARA_USERID_SEL_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8814B) & \
+ BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8814B)
+#define BIT_SET_BFRPT_PARA_USERID_SEL_V1_8814B(x, v) \
+ (BIT_CLEAR_BFRPT_PARA_USERID_SEL_V1_8814B(x) | \
+ BIT_BFRPT_PARA_USERID_SEL_V1_8814B(v))
+
+#define BIT_SHIFT_BFRPT_PARA_V1_8814B 0
+#define BIT_MASK_BFRPT_PARA_V1_8814B 0x1fff
+#define BIT_BFRPT_PARA_V1_8814B(x) \
+ (((x) & BIT_MASK_BFRPT_PARA_V1_8814B) << BIT_SHIFT_BFRPT_PARA_V1_8814B)
+#define BITS_BFRPT_PARA_V1_8814B \
+ (BIT_MASK_BFRPT_PARA_V1_8814B << BIT_SHIFT_BFRPT_PARA_V1_8814B)
+#define BIT_CLEAR_BFRPT_PARA_V1_8814B(x) ((x) & (~BITS_BFRPT_PARA_V1_8814B))
+#define BIT_GET_BFRPT_PARA_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_BFRPT_PARA_V1_8814B) & BIT_MASK_BFRPT_PARA_V1_8814B)
+#define BIT_SET_BFRPT_PARA_V1_8814B(x, v) \
+ (BIT_CLEAR_BFRPT_PARA_V1_8814B(x) | BIT_BFRPT_PARA_V1_8814B(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2_8814B */
+#define BIT_STATUS_BFEE2_8814B BIT(10)
+#define BIT_WMAC_MU_BFEE2_EN_8814B BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE2_AID_8814B 0
+#define BIT_MASK_WMAC_MU_BFEE2_AID_8814B 0x1ff
+#define BIT_WMAC_MU_BFEE2_AID_8814B(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE2_AID_8814B) \
+ << BIT_SHIFT_WMAC_MU_BFEE2_AID_8814B)
+#define BITS_WMAC_MU_BFEE2_AID_8814B \
+ (BIT_MASK_WMAC_MU_BFEE2_AID_8814B << BIT_SHIFT_WMAC_MU_BFEE2_AID_8814B)
+#define BIT_CLEAR_WMAC_MU_BFEE2_AID_8814B(x) \
+ ((x) & (~BITS_WMAC_MU_BFEE2_AID_8814B))
+#define BIT_GET_WMAC_MU_BFEE2_AID_8814B(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID_8814B) & \
+ BIT_MASK_WMAC_MU_BFEE2_AID_8814B)
+#define BIT_SET_WMAC_MU_BFEE2_AID_8814B(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE2_AID_8814B(x) | BIT_WMAC_MU_BFEE2_AID_8814B(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3_8814B */
+#define BIT_STATUS_BFEE3_8814B BIT(10)
+#define BIT_WMAC_MU_BFEE3_EN_8814B BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE3_AID_8814B 0
+#define BIT_MASK_WMAC_MU_BFEE3_AID_8814B 0x1ff
+#define BIT_WMAC_MU_BFEE3_AID_8814B(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE3_AID_8814B) \
+ << BIT_SHIFT_WMAC_MU_BFEE3_AID_8814B)
+#define BITS_WMAC_MU_BFEE3_AID_8814B \
+ (BIT_MASK_WMAC_MU_BFEE3_AID_8814B << BIT_SHIFT_WMAC_MU_BFEE3_AID_8814B)
+#define BIT_CLEAR_WMAC_MU_BFEE3_AID_8814B(x) \
+ ((x) & (~BITS_WMAC_MU_BFEE3_AID_8814B))
+#define BIT_GET_WMAC_MU_BFEE3_AID_8814B(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID_8814B) & \
+ BIT_MASK_WMAC_MU_BFEE3_AID_8814B)
+#define BIT_SET_WMAC_MU_BFEE3_AID_8814B(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE3_AID_8814B(x) | BIT_WMAC_MU_BFEE3_AID_8814B(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4_8814B */
+#define BIT_STATUS_BFEE4_8814B BIT(10)
+#define BIT_WMAC_MU_BFEE4_EN_8814B BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE4_AID_8814B 0
+#define BIT_MASK_WMAC_MU_BFEE4_AID_8814B 0x1ff
+#define BIT_WMAC_MU_BFEE4_AID_8814B(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE4_AID_8814B) \
+ << BIT_SHIFT_WMAC_MU_BFEE4_AID_8814B)
+#define BITS_WMAC_MU_BFEE4_AID_8814B \
+ (BIT_MASK_WMAC_MU_BFEE4_AID_8814B << BIT_SHIFT_WMAC_MU_BFEE4_AID_8814B)
+#define BIT_CLEAR_WMAC_MU_BFEE4_AID_8814B(x) \
+ ((x) & (~BITS_WMAC_MU_BFEE4_AID_8814B))
+#define BIT_GET_WMAC_MU_BFEE4_AID_8814B(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID_8814B) & \
+ BIT_MASK_WMAC_MU_BFEE4_AID_8814B)
+#define BIT_SET_WMAC_MU_BFEE4_AID_8814B(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE4_AID_8814B(x) | BIT_WMAC_MU_BFEE4_AID_8814B(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5_8814B */
+#define BIT_BIT_STATUS_BFEE5_8814B BIT(10)
+#define BIT_WMAC_MU_BFEE5_EN_8814B BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE5_AID_8814B 0
+#define BIT_MASK_WMAC_MU_BFEE5_AID_8814B 0x1ff
+#define BIT_WMAC_MU_BFEE5_AID_8814B(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE5_AID_8814B) \
+ << BIT_SHIFT_WMAC_MU_BFEE5_AID_8814B)
+#define BITS_WMAC_MU_BFEE5_AID_8814B \
+ (BIT_MASK_WMAC_MU_BFEE5_AID_8814B << BIT_SHIFT_WMAC_MU_BFEE5_AID_8814B)
+#define BIT_CLEAR_WMAC_MU_BFEE5_AID_8814B(x) \
+ ((x) & (~BITS_WMAC_MU_BFEE5_AID_8814B))
+#define BIT_GET_WMAC_MU_BFEE5_AID_8814B(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID_8814B) & \
+ BIT_MASK_WMAC_MU_BFEE5_AID_8814B)
+#define BIT_SET_WMAC_MU_BFEE5_AID_8814B(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE5_AID_8814B(x) | BIT_WMAC_MU_BFEE5_AID_8814B(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6_8814B */
+#define BIT_STATUS_BFEE6_8814B BIT(10)
+#define BIT_WMAC_MU_BFEE6_EN_8814B BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE6_AID_8814B 0
+#define BIT_MASK_WMAC_MU_BFEE6_AID_8814B 0x1ff
+#define BIT_WMAC_MU_BFEE6_AID_8814B(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE6_AID_8814B) \
+ << BIT_SHIFT_WMAC_MU_BFEE6_AID_8814B)
+#define BITS_WMAC_MU_BFEE6_AID_8814B \
+ (BIT_MASK_WMAC_MU_BFEE6_AID_8814B << BIT_SHIFT_WMAC_MU_BFEE6_AID_8814B)
+#define BIT_CLEAR_WMAC_MU_BFEE6_AID_8814B(x) \
+ ((x) & (~BITS_WMAC_MU_BFEE6_AID_8814B))
+#define BIT_GET_WMAC_MU_BFEE6_AID_8814B(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID_8814B) & \
+ BIT_MASK_WMAC_MU_BFEE6_AID_8814B)
+#define BIT_SET_WMAC_MU_BFEE6_AID_8814B(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE6_AID_8814B(x) | BIT_WMAC_MU_BFEE6_AID_8814B(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7_8814B */
+#define BIT_STATUS_BFEE7_8814B BIT(10)
+#define BIT_WMAC_MU_BFEE7_EN_8814B BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE7_AID_8814B 0
+#define BIT_MASK_WMAC_MU_BFEE7_AID_8814B 0x1ff
+#define BIT_WMAC_MU_BFEE7_AID_8814B(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE7_AID_8814B) \
+ << BIT_SHIFT_WMAC_MU_BFEE7_AID_8814B)
+#define BITS_WMAC_MU_BFEE7_AID_8814B \
+ (BIT_MASK_WMAC_MU_BFEE7_AID_8814B << BIT_SHIFT_WMAC_MU_BFEE7_AID_8814B)
+#define BIT_CLEAR_WMAC_MU_BFEE7_AID_8814B(x) \
+ ((x) & (~BITS_WMAC_MU_BFEE7_AID_8814B))
+#define BIT_GET_WMAC_MU_BFEE7_AID_8814B(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID_8814B) & \
+ BIT_MASK_WMAC_MU_BFEE7_AID_8814B)
+#define BIT_SET_WMAC_MU_BFEE7_AID_8814B(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE7_AID_8814B(x) | BIT_WMAC_MU_BFEE7_AID_8814B(v))
+
+/* 2 REG_WMAC_BB_STOP_RX_COUNTER_8814B */
+#define BIT_RST_ALL_COUNTER_8814B BIT(31)
+
+#define BIT_SHIFT_ABORT_RX_VBON_COUNTER_8814B 16
+#define BIT_MASK_ABORT_RX_VBON_COUNTER_8814B 0xff
+#define BIT_ABORT_RX_VBON_COUNTER_8814B(x) \
+ (((x) & BIT_MASK_ABORT_RX_VBON_COUNTER_8814B) \
+ << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8814B)
+#define BITS_ABORT_RX_VBON_COUNTER_8814B \
+ (BIT_MASK_ABORT_RX_VBON_COUNTER_8814B \
+ << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8814B)
+#define BIT_CLEAR_ABORT_RX_VBON_COUNTER_8814B(x) \
+ ((x) & (~BITS_ABORT_RX_VBON_COUNTER_8814B))
+#define BIT_GET_ABORT_RX_VBON_COUNTER_8814B(x) \
+ (((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER_8814B) & \
+ BIT_MASK_ABORT_RX_VBON_COUNTER_8814B)
+#define BIT_SET_ABORT_RX_VBON_COUNTER_8814B(x, v) \
+ (BIT_CLEAR_ABORT_RX_VBON_COUNTER_8814B(x) | \
+ BIT_ABORT_RX_VBON_COUNTER_8814B(v))
+
+#define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8814B 8
+#define BIT_MASK_ABORT_RX_RDRDY_COUNTER_8814B 0xff
+#define BIT_ABORT_RX_RDRDY_COUNTER_8814B(x) \
+ (((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8814B) \
+ << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8814B)
+#define BITS_ABORT_RX_RDRDY_COUNTER_8814B \
+ (BIT_MASK_ABORT_RX_RDRDY_COUNTER_8814B \
+ << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8814B)
+#define BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8814B(x) \
+ ((x) & (~BITS_ABORT_RX_RDRDY_COUNTER_8814B))
+#define BIT_GET_ABORT_RX_RDRDY_COUNTER_8814B(x) \
+ (((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8814B) & \
+ BIT_MASK_ABORT_RX_RDRDY_COUNTER_8814B)
+#define BIT_SET_ABORT_RX_RDRDY_COUNTER_8814B(x, v) \
+ (BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8814B(x) | \
+ BIT_ABORT_RX_RDRDY_COUNTER_8814B(v))
+
+#define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8814B 0
+#define BIT_MASK_VBON_EARLY_FALLING_COUNTER_8814B 0xff
+#define BIT_VBON_EARLY_FALLING_COUNTER_8814B(x) \
+ (((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8814B) \
+ << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8814B)
+#define BITS_VBON_EARLY_FALLING_COUNTER_8814B \
+ (BIT_MASK_VBON_EARLY_FALLING_COUNTER_8814B \
+ << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8814B)
+#define BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8814B(x) \
+ ((x) & (~BITS_VBON_EARLY_FALLING_COUNTER_8814B))
+#define BIT_GET_VBON_EARLY_FALLING_COUNTER_8814B(x) \
+ (((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8814B) & \
+ BIT_MASK_VBON_EARLY_FALLING_COUNTER_8814B)
+#define BIT_SET_VBON_EARLY_FALLING_COUNTER_8814B(x, v) \
+ (BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8814B(x) | \
+ BIT_VBON_EARLY_FALLING_COUNTER_8814B(v))
+
+/* 2 REG_WMAC_PLCP_MONITOR_8814B */
+#define BIT_WMAC_PLCP_TRX_SEL_8814B BIT(31)
+
+#define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8814B 28
+#define BIT_MASK_WMAC_PLCP_RDSIG_SEL_8814B 0x7
+#define BIT_WMAC_PLCP_RDSIG_SEL_8814B(x) \
+ (((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8814B) \
+ << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8814B)
+#define BITS_WMAC_PLCP_RDSIG_SEL_8814B \
+ (BIT_MASK_WMAC_PLCP_RDSIG_SEL_8814B \
+ << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8814B)
+#define BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8814B(x) \
+ ((x) & (~BITS_WMAC_PLCP_RDSIG_SEL_8814B))
+#define BIT_GET_WMAC_PLCP_RDSIG_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8814B) & \
+ BIT_MASK_WMAC_PLCP_RDSIG_SEL_8814B)
+#define BIT_SET_WMAC_PLCP_RDSIG_SEL_8814B(x, v) \
+ (BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8814B(x) | \
+ BIT_WMAC_PLCP_RDSIG_SEL_8814B(v))
+
+#define BIT_SHIFT_WMAC_RATE_IDX_8814B 24
+#define BIT_MASK_WMAC_RATE_IDX_8814B 0xf
+#define BIT_WMAC_RATE_IDX_8814B(x) \
+ (((x) & BIT_MASK_WMAC_RATE_IDX_8814B) << BIT_SHIFT_WMAC_RATE_IDX_8814B)
+#define BITS_WMAC_RATE_IDX_8814B \
+ (BIT_MASK_WMAC_RATE_IDX_8814B << BIT_SHIFT_WMAC_RATE_IDX_8814B)
+#define BIT_CLEAR_WMAC_RATE_IDX_8814B(x) ((x) & (~BITS_WMAC_RATE_IDX_8814B))
+#define BIT_GET_WMAC_RATE_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_WMAC_RATE_IDX_8814B) & BIT_MASK_WMAC_RATE_IDX_8814B)
+#define BIT_SET_WMAC_RATE_IDX_8814B(x, v) \
+ (BIT_CLEAR_WMAC_RATE_IDX_8814B(x) | BIT_WMAC_RATE_IDX_8814B(v))
+
+#define BIT_SHIFT_WMAC_PLCP_RDSIG_8814B 0
+#define BIT_MASK_WMAC_PLCP_RDSIG_8814B 0xffffff
+#define BIT_WMAC_PLCP_RDSIG_8814B(x) \
+ (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8814B) \
+ << BIT_SHIFT_WMAC_PLCP_RDSIG_8814B)
+#define BITS_WMAC_PLCP_RDSIG_8814B \
+ (BIT_MASK_WMAC_PLCP_RDSIG_8814B << BIT_SHIFT_WMAC_PLCP_RDSIG_8814B)
+#define BIT_CLEAR_WMAC_PLCP_RDSIG_8814B(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8814B))
+#define BIT_GET_WMAC_PLCP_RDSIG_8814B(x) \
+ (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8814B) & \
+ BIT_MASK_WMAC_PLCP_RDSIG_8814B)
+#define BIT_SET_WMAC_PLCP_RDSIG_8814B(x, v) \
+ (BIT_CLEAR_WMAC_PLCP_RDSIG_8814B(x) | BIT_WMAC_PLCP_RDSIG_8814B(v))
+
+/* 2 REG_WMAC_DEBUG_PORT_8814B */
+
+#define BIT_SHIFT_WMAC_DEBUG_PORT_8814B 0
+#define BIT_MASK_WMAC_DEBUG_PORT_8814B 0xffffffffL
+#define BIT_WMAC_DEBUG_PORT_8814B(x) \
+ (((x) & BIT_MASK_WMAC_DEBUG_PORT_8814B) \
+ << BIT_SHIFT_WMAC_DEBUG_PORT_8814B)
+#define BITS_WMAC_DEBUG_PORT_8814B \
+ (BIT_MASK_WMAC_DEBUG_PORT_8814B << BIT_SHIFT_WMAC_DEBUG_PORT_8814B)
+#define BIT_CLEAR_WMAC_DEBUG_PORT_8814B(x) ((x) & (~BITS_WMAC_DEBUG_PORT_8814B))
+#define BIT_GET_WMAC_DEBUG_PORT_8814B(x) \
+ (((x) >> BIT_SHIFT_WMAC_DEBUG_PORT_8814B) & \
+ BIT_MASK_WMAC_DEBUG_PORT_8814B)
+#define BIT_SET_WMAC_DEBUG_PORT_8814B(x, v) \
+ (BIT_CLEAR_WMAC_DEBUG_PORT_8814B(x) | BIT_WMAC_DEBUG_PORT_8814B(v))
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_TRANSMIT_ADDRSS_0_8814B (TA0 REGISTER) */
+
+#define BIT_SHIFT_TA0_V1_8814B 0
+#define BIT_MASK_TA0_V1_8814B 0xffffffffL
+#define BIT_TA0_V1_8814B(x) \
+ (((x) & BIT_MASK_TA0_V1_8814B) << BIT_SHIFT_TA0_V1_8814B)
+#define BITS_TA0_V1_8814B (BIT_MASK_TA0_V1_8814B << BIT_SHIFT_TA0_V1_8814B)
+#define BIT_CLEAR_TA0_V1_8814B(x) ((x) & (~BITS_TA0_V1_8814B))
+#define BIT_GET_TA0_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_TA0_V1_8814B) & BIT_MASK_TA0_V1_8814B)
+#define BIT_SET_TA0_V1_8814B(x, v) \
+ (BIT_CLEAR_TA0_V1_8814B(x) | BIT_TA0_V1_8814B(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_0_H_8814B (TA0 REGISTER) */
+
+#define BIT_SHIFT_TA0_H_V1_8814B 0
+#define BIT_MASK_TA0_H_V1_8814B 0xffff
+#define BIT_TA0_H_V1_8814B(x) \
+ (((x) & BIT_MASK_TA0_H_V1_8814B) << BIT_SHIFT_TA0_H_V1_8814B)
+#define BITS_TA0_H_V1_8814B \
+ (BIT_MASK_TA0_H_V1_8814B << BIT_SHIFT_TA0_H_V1_8814B)
+#define BIT_CLEAR_TA0_H_V1_8814B(x) ((x) & (~BITS_TA0_H_V1_8814B))
+#define BIT_GET_TA0_H_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_TA0_H_V1_8814B) & BIT_MASK_TA0_H_V1_8814B)
+#define BIT_SET_TA0_H_V1_8814B(x, v) \
+ (BIT_CLEAR_TA0_H_V1_8814B(x) | BIT_TA0_H_V1_8814B(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_1_8814B (TA1 REGISTER) */
+
+#define BIT_SHIFT_TA1_V1_8814B 0
+#define BIT_MASK_TA1_V1_8814B 0xffffffffL
+#define BIT_TA1_V1_8814B(x) \
+ (((x) & BIT_MASK_TA1_V1_8814B) << BIT_SHIFT_TA1_V1_8814B)
+#define BITS_TA1_V1_8814B (BIT_MASK_TA1_V1_8814B << BIT_SHIFT_TA1_V1_8814B)
+#define BIT_CLEAR_TA1_V1_8814B(x) ((x) & (~BITS_TA1_V1_8814B))
+#define BIT_GET_TA1_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_TA1_V1_8814B) & BIT_MASK_TA1_V1_8814B)
+#define BIT_SET_TA1_V1_8814B(x, v) \
+ (BIT_CLEAR_TA1_V1_8814B(x) | BIT_TA1_V1_8814B(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_1_H_8814B (TA1 REGISTER) */
+
+#define BIT_SHIFT_TA1_H_V1_8814B 0
+#define BIT_MASK_TA1_H_V1_8814B 0xffff
+#define BIT_TA1_H_V1_8814B(x) \
+ (((x) & BIT_MASK_TA1_H_V1_8814B) << BIT_SHIFT_TA1_H_V1_8814B)
+#define BITS_TA1_H_V1_8814B \
+ (BIT_MASK_TA1_H_V1_8814B << BIT_SHIFT_TA1_H_V1_8814B)
+#define BIT_CLEAR_TA1_H_V1_8814B(x) ((x) & (~BITS_TA1_H_V1_8814B))
+#define BIT_GET_TA1_H_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_TA1_H_V1_8814B) & BIT_MASK_TA1_H_V1_8814B)
+#define BIT_SET_TA1_H_V1_8814B(x, v) \
+ (BIT_CLEAR_TA1_H_V1_8814B(x) | BIT_TA1_H_V1_8814B(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_2_8814B (TA2 REGISTER) */
+
+#define BIT_SHIFT_TA2_V1_8814B 0
+#define BIT_MASK_TA2_V1_8814B 0xffffffffL
+#define BIT_TA2_V1_8814B(x) \
+ (((x) & BIT_MASK_TA2_V1_8814B) << BIT_SHIFT_TA2_V1_8814B)
+#define BITS_TA2_V1_8814B (BIT_MASK_TA2_V1_8814B << BIT_SHIFT_TA2_V1_8814B)
+#define BIT_CLEAR_TA2_V1_8814B(x) ((x) & (~BITS_TA2_V1_8814B))
+#define BIT_GET_TA2_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_TA2_V1_8814B) & BIT_MASK_TA2_V1_8814B)
+#define BIT_SET_TA2_V1_8814B(x, v) \
+ (BIT_CLEAR_TA2_V1_8814B(x) | BIT_TA2_V1_8814B(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_2_H_8814B (TA2 REGISTER) */
+
+#define BIT_SHIFT_TA2_H_V1_8814B 0
+#define BIT_MASK_TA2_H_V1_8814B 0xffff
+#define BIT_TA2_H_V1_8814B(x) \
+ (((x) & BIT_MASK_TA2_H_V1_8814B) << BIT_SHIFT_TA2_H_V1_8814B)
+#define BITS_TA2_H_V1_8814B \
+ (BIT_MASK_TA2_H_V1_8814B << BIT_SHIFT_TA2_H_V1_8814B)
+#define BIT_CLEAR_TA2_H_V1_8814B(x) ((x) & (~BITS_TA2_H_V1_8814B))
+#define BIT_GET_TA2_H_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_TA2_H_V1_8814B) & BIT_MASK_TA2_H_V1_8814B)
+#define BIT_SET_TA2_H_V1_8814B(x, v) \
+ (BIT_CLEAR_TA2_H_V1_8814B(x) | BIT_TA2_H_V1_8814B(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_3_8814B (TA3 REGISTER) */
+
+#define BIT_SHIFT_TA2_V1_8814B 0
+#define BIT_MASK_TA2_V1_8814B 0xffffffffL
+#define BIT_TA2_V1_8814B(x) \
+ (((x) & BIT_MASK_TA2_V1_8814B) << BIT_SHIFT_TA2_V1_8814B)
+#define BITS_TA2_V1_8814B (BIT_MASK_TA2_V1_8814B << BIT_SHIFT_TA2_V1_8814B)
+#define BIT_CLEAR_TA2_V1_8814B(x) ((x) & (~BITS_TA2_V1_8814B))
+#define BIT_GET_TA2_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_TA2_V1_8814B) & BIT_MASK_TA2_V1_8814B)
+#define BIT_SET_TA2_V1_8814B(x, v) \
+ (BIT_CLEAR_TA2_V1_8814B(x) | BIT_TA2_V1_8814B(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_3_H_8814B (TA3 REGISTER) */
+
+#define BIT_SHIFT_TA3_H_V1_8814B 0
+#define BIT_MASK_TA3_H_V1_8814B 0xffff
+#define BIT_TA3_H_V1_8814B(x) \
+ (((x) & BIT_MASK_TA3_H_V1_8814B) << BIT_SHIFT_TA3_H_V1_8814B)
+#define BITS_TA3_H_V1_8814B \
+ (BIT_MASK_TA3_H_V1_8814B << BIT_SHIFT_TA3_H_V1_8814B)
+#define BIT_CLEAR_TA3_H_V1_8814B(x) ((x) & (~BITS_TA3_H_V1_8814B))
+#define BIT_GET_TA3_H_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_TA3_H_V1_8814B) & BIT_MASK_TA3_H_V1_8814B)
+#define BIT_SET_TA3_H_V1_8814B(x, v) \
+ (BIT_CLEAR_TA3_H_V1_8814B(x) | BIT_TA3_H_V1_8814B(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_4_8814B (TA4 REGISTER) */
+
+#define BIT_SHIFT_TA4_V1_8814B 0
+#define BIT_MASK_TA4_V1_8814B 0xffffffffL
+#define BIT_TA4_V1_8814B(x) \
+ (((x) & BIT_MASK_TA4_V1_8814B) << BIT_SHIFT_TA4_V1_8814B)
+#define BITS_TA4_V1_8814B (BIT_MASK_TA4_V1_8814B << BIT_SHIFT_TA4_V1_8814B)
+#define BIT_CLEAR_TA4_V1_8814B(x) ((x) & (~BITS_TA4_V1_8814B))
+#define BIT_GET_TA4_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_TA4_V1_8814B) & BIT_MASK_TA4_V1_8814B)
+#define BIT_SET_TA4_V1_8814B(x, v) \
+ (BIT_CLEAR_TA4_V1_8814B(x) | BIT_TA4_V1_8814B(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_4_H_8814B (TA4 REGISTER) */
+
+#define BIT_SHIFT_TA4_H_V1_8814B 0
+#define BIT_MASK_TA4_H_V1_8814B 0xffff
+#define BIT_TA4_H_V1_8814B(x) \
+ (((x) & BIT_MASK_TA4_H_V1_8814B) << BIT_SHIFT_TA4_H_V1_8814B)
+#define BITS_TA4_H_V1_8814B \
+ (BIT_MASK_TA4_H_V1_8814B << BIT_SHIFT_TA4_H_V1_8814B)
+#define BIT_CLEAR_TA4_H_V1_8814B(x) ((x) & (~BITS_TA4_H_V1_8814B))
+#define BIT_GET_TA4_H_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_TA4_H_V1_8814B) & BIT_MASK_TA4_H_V1_8814B)
+#define BIT_SET_TA4_H_V1_8814B(x, v) \
+ (BIT_CLEAR_TA4_H_V1_8814B(x) | BIT_TA4_H_V1_8814B(v))
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_RSVD_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_MACID1_8814B */
+
+#define BIT_SHIFT_MACID1_0_8814B 0
+#define BIT_MASK_MACID1_0_8814B 0xffffffffL
+#define BIT_MACID1_0_8814B(x) \
+ (((x) & BIT_MASK_MACID1_0_8814B) << BIT_SHIFT_MACID1_0_8814B)
+#define BITS_MACID1_0_8814B \
+ (BIT_MASK_MACID1_0_8814B << BIT_SHIFT_MACID1_0_8814B)
+#define BIT_CLEAR_MACID1_0_8814B(x) ((x) & (~BITS_MACID1_0_8814B))
+#define BIT_GET_MACID1_0_8814B(x) \
+ (((x) >> BIT_SHIFT_MACID1_0_8814B) & BIT_MASK_MACID1_0_8814B)
+#define BIT_SET_MACID1_0_8814B(x, v) \
+ (BIT_CLEAR_MACID1_0_8814B(x) | BIT_MACID1_0_8814B(v))
+
+/* 2 REG_MACID1_1_8814B */
+
+#define BIT_SHIFT_MACID1_1_8814B 0
+#define BIT_MASK_MACID1_1_8814B 0xffff
+#define BIT_MACID1_1_8814B(x) \
+ (((x) & BIT_MASK_MACID1_1_8814B) << BIT_SHIFT_MACID1_1_8814B)
+#define BITS_MACID1_1_8814B \
+ (BIT_MASK_MACID1_1_8814B << BIT_SHIFT_MACID1_1_8814B)
+#define BIT_CLEAR_MACID1_1_8814B(x) ((x) & (~BITS_MACID1_1_8814B))
+#define BIT_GET_MACID1_1_8814B(x) \
+ (((x) >> BIT_SHIFT_MACID1_1_8814B) & BIT_MASK_MACID1_1_8814B)
+#define BIT_SET_MACID1_1_8814B(x, v) \
+ (BIT_CLEAR_MACID1_1_8814B(x) | BIT_MACID1_1_8814B(v))
+
+/* 2 REG_BSSID1_8814B */
+
+#define BIT_SHIFT_BSSID1_0_8814B 0
+#define BIT_MASK_BSSID1_0_8814B 0xffffffffL
+#define BIT_BSSID1_0_8814B(x) \
+ (((x) & BIT_MASK_BSSID1_0_8814B) << BIT_SHIFT_BSSID1_0_8814B)
+#define BITS_BSSID1_0_8814B \
+ (BIT_MASK_BSSID1_0_8814B << BIT_SHIFT_BSSID1_0_8814B)
+#define BIT_CLEAR_BSSID1_0_8814B(x) ((x) & (~BITS_BSSID1_0_8814B))
+#define BIT_GET_BSSID1_0_8814B(x) \
+ (((x) >> BIT_SHIFT_BSSID1_0_8814B) & BIT_MASK_BSSID1_0_8814B)
+#define BIT_SET_BSSID1_0_8814B(x, v) \
+ (BIT_CLEAR_BSSID1_0_8814B(x) | BIT_BSSID1_0_8814B(v))
+
+/* 2 REG_BSSID1_1_8814B */
+
+#define BIT_SHIFT_BSSID1_1_8814B 0
+#define BIT_MASK_BSSID1_1_8814B 0xffff
+#define BIT_BSSID1_1_8814B(x) \
+ (((x) & BIT_MASK_BSSID1_1_8814B) << BIT_SHIFT_BSSID1_1_8814B)
+#define BITS_BSSID1_1_8814B \
+ (BIT_MASK_BSSID1_1_8814B << BIT_SHIFT_BSSID1_1_8814B)
+#define BIT_CLEAR_BSSID1_1_8814B(x) ((x) & (~BITS_BSSID1_1_8814B))
+#define BIT_GET_BSSID1_1_8814B(x) \
+ (((x) >> BIT_SHIFT_BSSID1_1_8814B) & BIT_MASK_BSSID1_1_8814B)
+#define BIT_SET_BSSID1_1_8814B(x, v) \
+ (BIT_CLEAR_BSSID1_1_8814B(x) | BIT_BSSID1_1_8814B(v))
+
+/* 2 REG_BCN_PSR_RPT1_8814B */
+
+#define BIT_SHIFT_DTIM_CNT1_8814B 24
+#define BIT_MASK_DTIM_CNT1_8814B 0xff
+#define BIT_DTIM_CNT1_8814B(x) \
+ (((x) & BIT_MASK_DTIM_CNT1_8814B) << BIT_SHIFT_DTIM_CNT1_8814B)
+#define BITS_DTIM_CNT1_8814B \
+ (BIT_MASK_DTIM_CNT1_8814B << BIT_SHIFT_DTIM_CNT1_8814B)
+#define BIT_CLEAR_DTIM_CNT1_8814B(x) ((x) & (~BITS_DTIM_CNT1_8814B))
+#define BIT_GET_DTIM_CNT1_8814B(x) \
+ (((x) >> BIT_SHIFT_DTIM_CNT1_8814B) & BIT_MASK_DTIM_CNT1_8814B)
+#define BIT_SET_DTIM_CNT1_8814B(x, v) \
+ (BIT_CLEAR_DTIM_CNT1_8814B(x) | BIT_DTIM_CNT1_8814B(v))
+
+#define BIT_SHIFT_DTIM_PERIOD1_8814B 16
+#define BIT_MASK_DTIM_PERIOD1_8814B 0xff
+#define BIT_DTIM_PERIOD1_8814B(x) \
+ (((x) & BIT_MASK_DTIM_PERIOD1_8814B) << BIT_SHIFT_DTIM_PERIOD1_8814B)
+#define BITS_DTIM_PERIOD1_8814B \
+ (BIT_MASK_DTIM_PERIOD1_8814B << BIT_SHIFT_DTIM_PERIOD1_8814B)
+#define BIT_CLEAR_DTIM_PERIOD1_8814B(x) ((x) & (~BITS_DTIM_PERIOD1_8814B))
+#define BIT_GET_DTIM_PERIOD1_8814B(x) \
+ (((x) >> BIT_SHIFT_DTIM_PERIOD1_8814B) & BIT_MASK_DTIM_PERIOD1_8814B)
+#define BIT_SET_DTIM_PERIOD1_8814B(x, v) \
+ (BIT_CLEAR_DTIM_PERIOD1_8814B(x) | BIT_DTIM_PERIOD1_8814B(v))
+
+#define BIT_DTIM1_8814B BIT(15)
+#define BIT_TIM1_8814B BIT(14)
+
+#define BIT_SHIFT_PS_AID_1_8814B 0
+#define BIT_MASK_PS_AID_1_8814B 0x7ff
+#define BIT_PS_AID_1_8814B(x) \
+ (((x) & BIT_MASK_PS_AID_1_8814B) << BIT_SHIFT_PS_AID_1_8814B)
+#define BITS_PS_AID_1_8814B \
+ (BIT_MASK_PS_AID_1_8814B << BIT_SHIFT_PS_AID_1_8814B)
+#define BIT_CLEAR_PS_AID_1_8814B(x) ((x) & (~BITS_PS_AID_1_8814B))
+#define BIT_GET_PS_AID_1_8814B(x) \
+ (((x) >> BIT_SHIFT_PS_AID_1_8814B) & BIT_MASK_PS_AID_1_8814B)
+#define BIT_SET_PS_AID_1_8814B(x, v) \
+ (BIT_CLEAR_PS_AID_1_8814B(x) | BIT_PS_AID_1_8814B(v))
+
+/* 2 REG_ASSOCIATED_BFMEE_SEL_8814B */
+#define BIT_TXUSER_ID1_8814B BIT(25)
+
+#define BIT_SHIFT_AID1_8814B 16
+#define BIT_MASK_AID1_8814B 0x1ff
+#define BIT_AID1_8814B(x) (((x) & BIT_MASK_AID1_8814B) << BIT_SHIFT_AID1_8814B)
+#define BITS_AID1_8814B (BIT_MASK_AID1_8814B << BIT_SHIFT_AID1_8814B)
+#define BIT_CLEAR_AID1_8814B(x) ((x) & (~BITS_AID1_8814B))
+#define BIT_GET_AID1_8814B(x) \
+ (((x) >> BIT_SHIFT_AID1_8814B) & BIT_MASK_AID1_8814B)
+#define BIT_SET_AID1_8814B(x, v) (BIT_CLEAR_AID1_8814B(x) | BIT_AID1_8814B(v))
+
+#define BIT_TXUSER_ID0_8814B BIT(9)
+
+#define BIT_SHIFT_AID0_8814B 0
+#define BIT_MASK_AID0_8814B 0x1ff
+#define BIT_AID0_8814B(x) (((x) & BIT_MASK_AID0_8814B) << BIT_SHIFT_AID0_8814B)
+#define BITS_AID0_8814B (BIT_MASK_AID0_8814B << BIT_SHIFT_AID0_8814B)
+#define BIT_CLEAR_AID0_8814B(x) ((x) & (~BITS_AID0_8814B))
+#define BIT_GET_AID0_8814B(x) \
+ (((x) >> BIT_SHIFT_AID0_8814B) & BIT_MASK_AID0_8814B)
+#define BIT_SET_AID0_8814B(x, v) (BIT_CLEAR_AID0_8814B(x) | BIT_AID0_8814B(v))
+
+/* 2 REG_SND_PTCL_CTRL_8814B */
+
+#define BIT_SHIFT_NDP_RX_STANDBY_TIMER_8814B 24
+#define BIT_MASK_NDP_RX_STANDBY_TIMER_8814B 0xff
+#define BIT_NDP_RX_STANDBY_TIMER_8814B(x) \
+ (((x) & BIT_MASK_NDP_RX_STANDBY_TIMER_8814B) \
+ << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8814B)
+#define BITS_NDP_RX_STANDBY_TIMER_8814B \
+ (BIT_MASK_NDP_RX_STANDBY_TIMER_8814B \
+ << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8814B)
+#define BIT_CLEAR_NDP_RX_STANDBY_TIMER_8814B(x) \
+ ((x) & (~BITS_NDP_RX_STANDBY_TIMER_8814B))
+#define BIT_GET_NDP_RX_STANDBY_TIMER_8814B(x) \
+ (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8814B) & \
+ BIT_MASK_NDP_RX_STANDBY_TIMER_8814B)
+#define BIT_SET_NDP_RX_STANDBY_TIMER_8814B(x, v) \
+ (BIT_CLEAR_NDP_RX_STANDBY_TIMER_8814B(x) | \
+ BIT_NDP_RX_STANDBY_TIMER_8814B(v))
+
+#define BIT_SHIFT_CSI_RPT_OFFSET_HT_8814B 16
+#define BIT_MASK_CSI_RPT_OFFSET_HT_8814B 0xff
+#define BIT_CSI_RPT_OFFSET_HT_8814B(x) \
+ (((x) & BIT_MASK_CSI_RPT_OFFSET_HT_8814B) \
+ << BIT_SHIFT_CSI_RPT_OFFSET_HT_8814B)
+#define BITS_CSI_RPT_OFFSET_HT_8814B \
+ (BIT_MASK_CSI_RPT_OFFSET_HT_8814B << BIT_SHIFT_CSI_RPT_OFFSET_HT_8814B)
+#define BIT_CLEAR_CSI_RPT_OFFSET_HT_8814B(x) \
+ ((x) & (~BITS_CSI_RPT_OFFSET_HT_8814B))
+#define BIT_GET_CSI_RPT_OFFSET_HT_8814B(x) \
+ (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_8814B) & \
+ BIT_MASK_CSI_RPT_OFFSET_HT_8814B)
+#define BIT_SET_CSI_RPT_OFFSET_HT_8814B(x, v) \
+ (BIT_CLEAR_CSI_RPT_OFFSET_HT_8814B(x) | BIT_CSI_RPT_OFFSET_HT_8814B(v))
+
+#define BIT_VHTNDP_RPTPOLL_CSI_STR_OFFSET_SEL_8814B BIT(15)
+#define BIT_R_WMAC_CSI_CHKSUM_DIS_8814B BIT(14)
+
+#define BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8814B 8
+#define BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8814B 0x3f
+#define BIT_R_CSI_RPT_OFFSET_VHT_V1_8814B(x) \
+ (((x) & BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8814B) \
+ << BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8814B)
+#define BITS_R_CSI_RPT_OFFSET_VHT_V1_8814B \
+ (BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8814B \
+ << BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8814B)
+#define BIT_CLEAR_R_CSI_RPT_OFFSET_VHT_V1_8814B(x) \
+ ((x) & (~BITS_R_CSI_RPT_OFFSET_VHT_V1_8814B))
+#define BIT_GET_R_CSI_RPT_OFFSET_VHT_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8814B) & \
+ BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8814B)
+#define BIT_SET_R_CSI_RPT_OFFSET_VHT_V1_8814B(x, v) \
+ (BIT_CLEAR_R_CSI_RPT_OFFSET_VHT_V1_8814B(x) | \
+ BIT_R_CSI_RPT_OFFSET_VHT_V1_8814B(v))
+
+#define BIT_R_WMAC_USE_NSTS_8814B BIT(7)
+#define BIT_R_DISABLE_CHECK_VHTSIGB_CRC_8814B BIT(6)
+#define BIT_R_DISABLE_CHECK_VHTSIGA_CRC_8814B BIT(5)
+#define BIT_R_WMAC_BFPARAM_SEL_8814B BIT(4)
+#define BIT_R_WMAC_CSISEQ_SEL_8814B BIT(3)
+#define BIT_R_WMAC_CSI_WITHHTC_EN_8814B BIT(2)
+#define BIT_R_WMAC_HT_NDPA_EN_8814B BIT(1)
+#define BIT_R_WMAC_VHT_NDPA_EN_8814B BIT(0)
+
+/* 2 REG_RX_CSI_RPT_INFO_8814B */
+#define BIT_WRITE_ENABLE_8814B BIT(31)
+#define BIT_WMAC_CHECK_SOUNDING_SEQ_8814B BIT(30)
+
+#define BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8814B 1
+#define BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8814B 0xffffff
+#define BIT_VHTHT_MIMO_CTRL_FIELD_8814B(x) \
+ (((x) & BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8814B) \
+ << BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8814B)
+#define BITS_VHTHT_MIMO_CTRL_FIELD_8814B \
+ (BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8814B \
+ << BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8814B)
+#define BIT_CLEAR_VHTHT_MIMO_CTRL_FIELD_8814B(x) \
+ ((x) & (~BITS_VHTHT_MIMO_CTRL_FIELD_8814B))
+#define BIT_GET_VHTHT_MIMO_CTRL_FIELD_8814B(x) \
+ (((x) >> BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8814B) & \
+ BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8814B)
+#define BIT_SET_VHTHT_MIMO_CTRL_FIELD_8814B(x, v) \
+ (BIT_CLEAR_VHTHT_MIMO_CTRL_FIELD_8814B(x) | \
+ BIT_VHTHT_MIMO_CTRL_FIELD_8814B(v))
+
+#define BIT_CSI_INTERRUPT_STATUS_8814B BIT(0)
+
+/* 2 REG_NS_ARP_CTRL_8814B */
+#define BIT_R_WMAC_NSARP_RSPEN_8814B BIT(15)
+#define BIT_R_WMAC_NSARP_RARP_8814B BIT(9)
+#define BIT_R_WMAC_NSARP_RIPV6_8814B BIT(8)
+
+#define BIT_SHIFT_R_WMAC_NSARP_MODEN_8814B 6
+#define BIT_MASK_R_WMAC_NSARP_MODEN_8814B 0x3
+#define BIT_R_WMAC_NSARP_MODEN_8814B(x) \
+ (((x) & BIT_MASK_R_WMAC_NSARP_MODEN_8814B) \
+ << BIT_SHIFT_R_WMAC_NSARP_MODEN_8814B)
+#define BITS_R_WMAC_NSARP_MODEN_8814B \
+ (BIT_MASK_R_WMAC_NSARP_MODEN_8814B \
+ << BIT_SHIFT_R_WMAC_NSARP_MODEN_8814B)
+#define BIT_CLEAR_R_WMAC_NSARP_MODEN_8814B(x) \
+ ((x) & (~BITS_R_WMAC_NSARP_MODEN_8814B))
+#define BIT_GET_R_WMAC_NSARP_MODEN_8814B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8814B) & \
+ BIT_MASK_R_WMAC_NSARP_MODEN_8814B)
+#define BIT_SET_R_WMAC_NSARP_MODEN_8814B(x, v) \
+ (BIT_CLEAR_R_WMAC_NSARP_MODEN_8814B(x) | \
+ BIT_R_WMAC_NSARP_MODEN_8814B(v))
+
+#define BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8814B 4
+#define BIT_MASK_R_WMAC_NSARP_RSPFTP_8814B 0x3
+#define BIT_R_WMAC_NSARP_RSPFTP_8814B(x) \
+ (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8814B) \
+ << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8814B)
+#define BITS_R_WMAC_NSARP_RSPFTP_8814B \
+ (BIT_MASK_R_WMAC_NSARP_RSPFTP_8814B \
+ << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8814B)
+#define BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8814B(x) \
+ ((x) & (~BITS_R_WMAC_NSARP_RSPFTP_8814B))
+#define BIT_GET_R_WMAC_NSARP_RSPFTP_8814B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8814B) & \
+ BIT_MASK_R_WMAC_NSARP_RSPFTP_8814B)
+#define BIT_SET_R_WMAC_NSARP_RSPFTP_8814B(x, v) \
+ (BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8814B(x) | \
+ BIT_R_WMAC_NSARP_RSPFTP_8814B(v))
+
+#define BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8814B 0
+#define BIT_MASK_R_WMAC_NSARP_RSPSEC_8814B 0xf
+#define BIT_R_WMAC_NSARP_RSPSEC_8814B(x) \
+ (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8814B) \
+ << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8814B)
+#define BITS_R_WMAC_NSARP_RSPSEC_8814B \
+ (BIT_MASK_R_WMAC_NSARP_RSPSEC_8814B \
+ << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8814B)
+#define BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8814B(x) \
+ ((x) & (~BITS_R_WMAC_NSARP_RSPSEC_8814B))
+#define BIT_GET_R_WMAC_NSARP_RSPSEC_8814B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8814B) & \
+ BIT_MASK_R_WMAC_NSARP_RSPSEC_8814B)
+#define BIT_SET_R_WMAC_NSARP_RSPSEC_8814B(x, v) \
+ (BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8814B(x) | \
+ BIT_R_WMAC_NSARP_RSPSEC_8814B(v))
+
+/* 2 REG_NS_ARP_INFO_8814B */
+#define BIT_REQ_IS_MCNS_8814B BIT(23)
+#define BIT_REQ_IS_UCNS_8814B BIT(22)
+#define BIT_REQ_IS_USNS_8814B BIT(21)
+#define BIT_REQ_IS_ARP_8814B BIT(20)
+#define BIT_EXPRSP_MH_WITHQC_8814B BIT(19)
+
+#define BIT_SHIFT_EXPRSP_SECTYPE_8814B 16
+#define BIT_MASK_EXPRSP_SECTYPE_8814B 0x7
+#define BIT_EXPRSP_SECTYPE_8814B(x) \
+ (((x) & BIT_MASK_EXPRSP_SECTYPE_8814B) \
+ << BIT_SHIFT_EXPRSP_SECTYPE_8814B)
+#define BITS_EXPRSP_SECTYPE_8814B \
+ (BIT_MASK_EXPRSP_SECTYPE_8814B << BIT_SHIFT_EXPRSP_SECTYPE_8814B)
+#define BIT_CLEAR_EXPRSP_SECTYPE_8814B(x) ((x) & (~BITS_EXPRSP_SECTYPE_8814B))
+#define BIT_GET_EXPRSP_SECTYPE_8814B(x) \
+ (((x) >> BIT_SHIFT_EXPRSP_SECTYPE_8814B) & \
+ BIT_MASK_EXPRSP_SECTYPE_8814B)
+#define BIT_SET_EXPRSP_SECTYPE_8814B(x, v) \
+ (BIT_CLEAR_EXPRSP_SECTYPE_8814B(x) | BIT_EXPRSP_SECTYPE_8814B(v))
+
+#define BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8814B 8
+#define BIT_MASK_EXPRSP_CHKSM_7_TO_0_8814B 0xff
+#define BIT_EXPRSP_CHKSM_7_TO_0_8814B(x) \
+ (((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8814B) \
+ << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8814B)
+#define BITS_EXPRSP_CHKSM_7_TO_0_8814B \
+ (BIT_MASK_EXPRSP_CHKSM_7_TO_0_8814B \
+ << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8814B)
+#define BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8814B(x) \
+ ((x) & (~BITS_EXPRSP_CHKSM_7_TO_0_8814B))
+#define BIT_GET_EXPRSP_CHKSM_7_TO_0_8814B(x) \
+ (((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8814B) & \
+ BIT_MASK_EXPRSP_CHKSM_7_TO_0_8814B)
+#define BIT_SET_EXPRSP_CHKSM_7_TO_0_8814B(x, v) \
+ (BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8814B(x) | \
+ BIT_EXPRSP_CHKSM_7_TO_0_8814B(v))
+
+#define BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8814B 0
+#define BIT_MASK_EXPRSP_CHKSM_15_TO_8_8814B 0xff
+#define BIT_EXPRSP_CHKSM_15_TO_8_8814B(x) \
+ (((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8814B) \
+ << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8814B)
+#define BITS_EXPRSP_CHKSM_15_TO_8_8814B \
+ (BIT_MASK_EXPRSP_CHKSM_15_TO_8_8814B \
+ << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8814B)
+#define BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8814B(x) \
+ ((x) & (~BITS_EXPRSP_CHKSM_15_TO_8_8814B))
+#define BIT_GET_EXPRSP_CHKSM_15_TO_8_8814B(x) \
+ (((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8814B) & \
+ BIT_MASK_EXPRSP_CHKSM_15_TO_8_8814B)
+#define BIT_SET_EXPRSP_CHKSM_15_TO_8_8814B(x, v) \
+ (BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8814B(x) | \
+ BIT_EXPRSP_CHKSM_15_TO_8_8814B(v))
+
+/* 2 REG_BEAMFORMING_INFO_NSARP_V1_8814B */
+
+#define BIT_SHIFT_WMAC_ARPIP_8814B 0
+#define BIT_MASK_WMAC_ARPIP_8814B 0xffffffffL
+#define BIT_WMAC_ARPIP_8814B(x) \
+ (((x) & BIT_MASK_WMAC_ARPIP_8814B) << BIT_SHIFT_WMAC_ARPIP_8814B)
+#define BITS_WMAC_ARPIP_8814B \
+ (BIT_MASK_WMAC_ARPIP_8814B << BIT_SHIFT_WMAC_ARPIP_8814B)
+#define BIT_CLEAR_WMAC_ARPIP_8814B(x) ((x) & (~BITS_WMAC_ARPIP_8814B))
+#define BIT_GET_WMAC_ARPIP_8814B(x) \
+ (((x) >> BIT_SHIFT_WMAC_ARPIP_8814B) & BIT_MASK_WMAC_ARPIP_8814B)
+#define BIT_SET_WMAC_ARPIP_8814B(x, v) \
+ (BIT_CLEAR_WMAC_ARPIP_8814B(x) | BIT_WMAC_ARPIP_8814B(v))
+
+/* 2 REG_BEAMFORMING_INFO_NSARP_8814B */
+
+#define BIT_SHIFT_BEAMFORMING_INFO_8814B 0
+#define BIT_MASK_BEAMFORMING_INFO_8814B 0xffffffffL
+#define BIT_BEAMFORMING_INFO_8814B(x) \
+ (((x) & BIT_MASK_BEAMFORMING_INFO_8814B) \
+ << BIT_SHIFT_BEAMFORMING_INFO_8814B)
+#define BITS_BEAMFORMING_INFO_8814B \
+ (BIT_MASK_BEAMFORMING_INFO_8814B << BIT_SHIFT_BEAMFORMING_INFO_8814B)
+#define BIT_CLEAR_BEAMFORMING_INFO_8814B(x) \
+ ((x) & (~BITS_BEAMFORMING_INFO_8814B))
+#define BIT_GET_BEAMFORMING_INFO_8814B(x) \
+ (((x) >> BIT_SHIFT_BEAMFORMING_INFO_8814B) & \
+ BIT_MASK_BEAMFORMING_INFO_8814B)
+#define BIT_SET_BEAMFORMING_INFO_8814B(x, v) \
+ (BIT_CLEAR_BEAMFORMING_INFO_8814B(x) | BIT_BEAMFORMING_INFO_8814B(v))
+
+/* 2 REG_IPV6_8814B */
+
+#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8814B 0
+#define BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8814B 0xffffffffL
+#define BIT_R_WMAC_IPV6_MYIPAD_0_8814B(x) \
+ (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8814B) \
+ << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8814B)
+#define BITS_R_WMAC_IPV6_MYIPAD_0_8814B \
+ (BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8814B \
+ << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8814B)
+#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0_8814B(x) \
+ ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_0_8814B))
+#define BIT_GET_R_WMAC_IPV6_MYIPAD_0_8814B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8814B) & \
+ BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8814B)
+#define BIT_SET_R_WMAC_IPV6_MYIPAD_0_8814B(x, v) \
+ (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0_8814B(x) | \
+ BIT_R_WMAC_IPV6_MYIPAD_0_8814B(v))
+
+/* 2 REG_IPV6_1_8814B */
+
+#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8814B 0
+#define BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8814B 0xffffffffL
+#define BIT_R_WMAC_IPV6_MYIPAD_1_8814B(x) \
+ (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8814B) \
+ << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8814B)
+#define BITS_R_WMAC_IPV6_MYIPAD_1_8814B \
+ (BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8814B \
+ << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8814B)
+#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1_8814B(x) \
+ ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_1_8814B))
+#define BIT_GET_R_WMAC_IPV6_MYIPAD_1_8814B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8814B) & \
+ BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8814B)
+#define BIT_SET_R_WMAC_IPV6_MYIPAD_1_8814B(x, v) \
+ (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1_8814B(x) | \
+ BIT_R_WMAC_IPV6_MYIPAD_1_8814B(v))
+
+/* 2 REG_IPV6_2_8814B */
+
+#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8814B 0
+#define BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8814B 0xffffffffL
+#define BIT_R_WMAC_IPV6_MYIPAD_2_8814B(x) \
+ (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8814B) \
+ << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8814B)
+#define BITS_R_WMAC_IPV6_MYIPAD_2_8814B \
+ (BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8814B \
+ << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8814B)
+#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2_8814B(x) \
+ ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_2_8814B))
+#define BIT_GET_R_WMAC_IPV6_MYIPAD_2_8814B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8814B) & \
+ BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8814B)
+#define BIT_SET_R_WMAC_IPV6_MYIPAD_2_8814B(x, v) \
+ (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2_8814B(x) | \
+ BIT_R_WMAC_IPV6_MYIPAD_2_8814B(v))
+
+/* 2 REG_IPV6_3_8814B */
+
+#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8814B 0
+#define BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8814B 0xffffffffL
+#define BIT_R_WMAC_IPV6_MYIPAD_3_8814B(x) \
+ (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8814B) \
+ << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8814B)
+#define BITS_R_WMAC_IPV6_MYIPAD_3_8814B \
+ (BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8814B \
+ << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8814B)
+#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3_8814B(x) \
+ ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_3_8814B))
+#define BIT_GET_R_WMAC_IPV6_MYIPAD_3_8814B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8814B) & \
+ BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8814B)
+#define BIT_SET_R_WMAC_IPV6_MYIPAD_3_8814B(x, v) \
+ (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3_8814B(x) | \
+ BIT_R_WMAC_IPV6_MYIPAD_3_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_WMAC_RTX_CTX_SUBTYPE_CFG_8814B */
+
+#define BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8814B 4
+#define BIT_MASK_R_WMAC_CTX_SUBTYPE_8814B 0xf
+#define BIT_R_WMAC_CTX_SUBTYPE_8814B(x) \
+ (((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8814B) \
+ << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8814B)
+#define BITS_R_WMAC_CTX_SUBTYPE_8814B \
+ (BIT_MASK_R_WMAC_CTX_SUBTYPE_8814B \
+ << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8814B)
+#define BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8814B(x) \
+ ((x) & (~BITS_R_WMAC_CTX_SUBTYPE_8814B))
+#define BIT_GET_R_WMAC_CTX_SUBTYPE_8814B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8814B) & \
+ BIT_MASK_R_WMAC_CTX_SUBTYPE_8814B)
+#define BIT_SET_R_WMAC_CTX_SUBTYPE_8814B(x, v) \
+ (BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8814B(x) | \
+ BIT_R_WMAC_CTX_SUBTYPE_8814B(v))
+
+#define BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8814B 0
+#define BIT_MASK_R_WMAC_RTX_SUBTYPE_8814B 0xf
+#define BIT_R_WMAC_RTX_SUBTYPE_8814B(x) \
+ (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8814B) \
+ << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8814B)
+#define BITS_R_WMAC_RTX_SUBTYPE_8814B \
+ (BIT_MASK_R_WMAC_RTX_SUBTYPE_8814B \
+ << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8814B)
+#define BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8814B(x) \
+ ((x) & (~BITS_R_WMAC_RTX_SUBTYPE_8814B))
+#define BIT_GET_R_WMAC_RTX_SUBTYPE_8814B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8814B) & \
+ BIT_MASK_R_WMAC_RTX_SUBTYPE_8814B)
+#define BIT_SET_R_WMAC_RTX_SUBTYPE_8814B(x, v) \
+ (BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8814B(x) | \
+ BIT_R_WMAC_RTX_SUBTYPE_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_WMAC_SWAES_CFG_8814B */
+
+/* 2 REG_BT_COEX_V2_8814B */
+#define BIT_GNT_BT_POLARITY_8814B BIT(12)
+#define BIT_GNT_BT_BYPASS_PRIORITY_8814B BIT(8)
+
+#define BIT_SHIFT_TIMER_8814B 0
+#define BIT_MASK_TIMER_8814B 0xff
+#define BIT_TIMER_8814B(x) \
+ (((x) & BIT_MASK_TIMER_8814B) << BIT_SHIFT_TIMER_8814B)
+#define BITS_TIMER_8814B (BIT_MASK_TIMER_8814B << BIT_SHIFT_TIMER_8814B)
+#define BIT_CLEAR_TIMER_8814B(x) ((x) & (~BITS_TIMER_8814B))
+#define BIT_GET_TIMER_8814B(x) \
+ (((x) >> BIT_SHIFT_TIMER_8814B) & BIT_MASK_TIMER_8814B)
+#define BIT_SET_TIMER_8814B(x, v) \
+ (BIT_CLEAR_TIMER_8814B(x) | BIT_TIMER_8814B(v))
+
+/* 2 REG_BT_COEX_8814B */
+#define BIT_R_GNT_BT_RFC_SW_8814B BIT(12)
+#define BIT_R_GNT_BT_RFC_SW_EN_8814B BIT(11)
+#define BIT_R_GNT_BT_BB_SW_8814B BIT(10)
+#define BIT_R_GNT_BT_BB_SW_EN_8814B BIT(9)
+#define BIT_R_BT_CNT_THREN_8814B BIT(8)
+
+#define BIT_SHIFT_R_BT_CNT_THR_8814B 0
+#define BIT_MASK_R_BT_CNT_THR_8814B 0xff
+#define BIT_R_BT_CNT_THR_8814B(x) \
+ (((x) & BIT_MASK_R_BT_CNT_THR_8814B) << BIT_SHIFT_R_BT_CNT_THR_8814B)
+#define BITS_R_BT_CNT_THR_8814B \
+ (BIT_MASK_R_BT_CNT_THR_8814B << BIT_SHIFT_R_BT_CNT_THR_8814B)
+#define BIT_CLEAR_R_BT_CNT_THR_8814B(x) ((x) & (~BITS_R_BT_CNT_THR_8814B))
+#define BIT_GET_R_BT_CNT_THR_8814B(x) \
+ (((x) >> BIT_SHIFT_R_BT_CNT_THR_8814B) & BIT_MASK_R_BT_CNT_THR_8814B)
+#define BIT_SET_R_BT_CNT_THR_8814B(x, v) \
+ (BIT_CLEAR_R_BT_CNT_THR_8814B(x) | BIT_R_BT_CNT_THR_8814B(v))
+
+/* 2 REG_WLAN_ACT_MASK_CTRL_8814B */
+
+#define BIT_SHIFT_RXMYRTS_NAV_V1_8814B 8
+#define BIT_MASK_RXMYRTS_NAV_V1_8814B 0xff
+#define BIT_RXMYRTS_NAV_V1_8814B(x) \
+ (((x) & BIT_MASK_RXMYRTS_NAV_V1_8814B) \
+ << BIT_SHIFT_RXMYRTS_NAV_V1_8814B)
+#define BITS_RXMYRTS_NAV_V1_8814B \
+ (BIT_MASK_RXMYRTS_NAV_V1_8814B << BIT_SHIFT_RXMYRTS_NAV_V1_8814B)
+#define BIT_CLEAR_RXMYRTS_NAV_V1_8814B(x) ((x) & (~BITS_RXMYRTS_NAV_V1_8814B))
+#define BIT_GET_RXMYRTS_NAV_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8814B) & \
+ BIT_MASK_RXMYRTS_NAV_V1_8814B)
+#define BIT_SET_RXMYRTS_NAV_V1_8814B(x, v) \
+ (BIT_CLEAR_RXMYRTS_NAV_V1_8814B(x) | BIT_RXMYRTS_NAV_V1_8814B(v))
+
+#define BIT_SHIFT_RTSRST_V1_8814B 0
+#define BIT_MASK_RTSRST_V1_8814B 0xff
+#define BIT_RTSRST_V1_8814B(x) \
+ (((x) & BIT_MASK_RTSRST_V1_8814B) << BIT_SHIFT_RTSRST_V1_8814B)
+#define BITS_RTSRST_V1_8814B \
+ (BIT_MASK_RTSRST_V1_8814B << BIT_SHIFT_RTSRST_V1_8814B)
+#define BIT_CLEAR_RTSRST_V1_8814B(x) ((x) & (~BITS_RTSRST_V1_8814B))
+#define BIT_GET_RTSRST_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_RTSRST_V1_8814B) & BIT_MASK_RTSRST_V1_8814B)
+#define BIT_SET_RTSRST_V1_8814B(x, v) \
+ (BIT_CLEAR_RTSRST_V1_8814B(x) | BIT_RTSRST_V1_8814B(v))
+
+/* 2 REG_WLAN_ACT_MASK_CTRL_1_8814B */
+#define BIT_WLRX_TER_BY_CTL_1_8814B BIT(11)
+#define BIT_WLRX_TER_BY_AD_1_8814B BIT(10)
+#define BIT_ANT_DIVERSITY_SEL_1_8814B BIT(9)
+#define BIT_ANTSEL_FOR_BT_CTRL_EN_1_8814B BIT(8)
+#define BIT_WLACT_LOW_GNTWL_EN_1_8814B BIT(2)
+#define BIT_WLACT_HIGH_GNTBT_EN_1_8814B BIT(1)
+#define BIT_NAV_UPPER_1_V1_8814B BIT(0)
+
+/* 2 REG_BT_COEX_ENHANCED_INTR_CTRL_8814B */
+
+#define BIT_SHIFT_BT_STAT_DELAY_8814B 12
+#define BIT_MASK_BT_STAT_DELAY_8814B 0xf
+#define BIT_BT_STAT_DELAY_8814B(x) \
+ (((x) & BIT_MASK_BT_STAT_DELAY_8814B) << BIT_SHIFT_BT_STAT_DELAY_8814B)
+#define BITS_BT_STAT_DELAY_8814B \
+ (BIT_MASK_BT_STAT_DELAY_8814B << BIT_SHIFT_BT_STAT_DELAY_8814B)
+#define BIT_CLEAR_BT_STAT_DELAY_8814B(x) ((x) & (~BITS_BT_STAT_DELAY_8814B))
+#define BIT_GET_BT_STAT_DELAY_8814B(x) \
+ (((x) >> BIT_SHIFT_BT_STAT_DELAY_8814B) & BIT_MASK_BT_STAT_DELAY_8814B)
+#define BIT_SET_BT_STAT_DELAY_8814B(x, v) \
+ (BIT_CLEAR_BT_STAT_DELAY_8814B(x) | BIT_BT_STAT_DELAY_8814B(v))
+
+#define BIT_SHIFT_BT_TRX_INIT_DETECT_8814B 8
+#define BIT_MASK_BT_TRX_INIT_DETECT_8814B 0xf
+#define BIT_BT_TRX_INIT_DETECT_8814B(x) \
+ (((x) & BIT_MASK_BT_TRX_INIT_DETECT_8814B) \
+ << BIT_SHIFT_BT_TRX_INIT_DETECT_8814B)
+#define BITS_BT_TRX_INIT_DETECT_8814B \
+ (BIT_MASK_BT_TRX_INIT_DETECT_8814B \
+ << BIT_SHIFT_BT_TRX_INIT_DETECT_8814B)
+#define BIT_CLEAR_BT_TRX_INIT_DETECT_8814B(x) \
+ ((x) & (~BITS_BT_TRX_INIT_DETECT_8814B))
+#define BIT_GET_BT_TRX_INIT_DETECT_8814B(x) \
+ (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8814B) & \
+ BIT_MASK_BT_TRX_INIT_DETECT_8814B)
+#define BIT_SET_BT_TRX_INIT_DETECT_8814B(x, v) \
+ (BIT_CLEAR_BT_TRX_INIT_DETECT_8814B(x) | \
+ BIT_BT_TRX_INIT_DETECT_8814B(v))
+
+#define BIT_SHIFT_BT_PRI_DETECT_TO_8814B 4
+#define BIT_MASK_BT_PRI_DETECT_TO_8814B 0xf
+#define BIT_BT_PRI_DETECT_TO_8814B(x) \
+ (((x) & BIT_MASK_BT_PRI_DETECT_TO_8814B) \
+ << BIT_SHIFT_BT_PRI_DETECT_TO_8814B)
+#define BITS_BT_PRI_DETECT_TO_8814B \
+ (BIT_MASK_BT_PRI_DETECT_TO_8814B << BIT_SHIFT_BT_PRI_DETECT_TO_8814B)
+#define BIT_CLEAR_BT_PRI_DETECT_TO_8814B(x) \
+ ((x) & (~BITS_BT_PRI_DETECT_TO_8814B))
+#define BIT_GET_BT_PRI_DETECT_TO_8814B(x) \
+ (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8814B) & \
+ BIT_MASK_BT_PRI_DETECT_TO_8814B)
+#define BIT_SET_BT_PRI_DETECT_TO_8814B(x, v) \
+ (BIT_CLEAR_BT_PRI_DETECT_TO_8814B(x) | BIT_BT_PRI_DETECT_TO_8814B(v))
+
+#define BIT_R_GRANTALL_WLMASK_8814B BIT(3)
+#define BIT_STATIS_BT_EN_8814B BIT(2)
+#define BIT_WL_ACT_MASK_ENABLE_8814B BIT(1)
+#define BIT_ENHANCED_BT_8814B BIT(0)
+
+/* 2 REG_BT_ACT_STATISTICS_8814B */
+
+#define BIT_SHIFT_STATIS_BT_HI_RX_8814B 16
+#define BIT_MASK_STATIS_BT_HI_RX_8814B 0xffff
+#define BIT_STATIS_BT_HI_RX_8814B(x) \
+ (((x) & BIT_MASK_STATIS_BT_HI_RX_8814B) \
+ << BIT_SHIFT_STATIS_BT_HI_RX_8814B)
+#define BITS_STATIS_BT_HI_RX_8814B \
+ (BIT_MASK_STATIS_BT_HI_RX_8814B << BIT_SHIFT_STATIS_BT_HI_RX_8814B)
+#define BIT_CLEAR_STATIS_BT_HI_RX_8814B(x) ((x) & (~BITS_STATIS_BT_HI_RX_8814B))
+#define BIT_GET_STATIS_BT_HI_RX_8814B(x) \
+ (((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8814B) & \
+ BIT_MASK_STATIS_BT_HI_RX_8814B)
+#define BIT_SET_STATIS_BT_HI_RX_8814B(x, v) \
+ (BIT_CLEAR_STATIS_BT_HI_RX_8814B(x) | BIT_STATIS_BT_HI_RX_8814B(v))
+
+#define BIT_SHIFT_STATIS_BT_HI_TX_8814B 0
+#define BIT_MASK_STATIS_BT_HI_TX_8814B 0xffff
+#define BIT_STATIS_BT_HI_TX_8814B(x) \
+ (((x) & BIT_MASK_STATIS_BT_HI_TX_8814B) \
+ << BIT_SHIFT_STATIS_BT_HI_TX_8814B)
+#define BITS_STATIS_BT_HI_TX_8814B \
+ (BIT_MASK_STATIS_BT_HI_TX_8814B << BIT_SHIFT_STATIS_BT_HI_TX_8814B)
+#define BIT_CLEAR_STATIS_BT_HI_TX_8814B(x) ((x) & (~BITS_STATIS_BT_HI_TX_8814B))
+#define BIT_GET_STATIS_BT_HI_TX_8814B(x) \
+ (((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8814B) & \
+ BIT_MASK_STATIS_BT_HI_TX_8814B)
+#define BIT_SET_STATIS_BT_HI_TX_8814B(x, v) \
+ (BIT_CLEAR_STATIS_BT_HI_TX_8814B(x) | BIT_STATIS_BT_HI_TX_8814B(v))
+
+/* 2 REG_BT_ACT_STATISTICS_1_8814B */
+
+#define BIT_SHIFT_STATIS_BT_LO_RX_1_8814B 16
+#define BIT_MASK_STATIS_BT_LO_RX_1_8814B 0xffff
+#define BIT_STATIS_BT_LO_RX_1_8814B(x) \
+ (((x) & BIT_MASK_STATIS_BT_LO_RX_1_8814B) \
+ << BIT_SHIFT_STATIS_BT_LO_RX_1_8814B)
+#define BITS_STATIS_BT_LO_RX_1_8814B \
+ (BIT_MASK_STATIS_BT_LO_RX_1_8814B << BIT_SHIFT_STATIS_BT_LO_RX_1_8814B)
+#define BIT_CLEAR_STATIS_BT_LO_RX_1_8814B(x) \
+ ((x) & (~BITS_STATIS_BT_LO_RX_1_8814B))
+#define BIT_GET_STATIS_BT_LO_RX_1_8814B(x) \
+ (((x) >> BIT_SHIFT_STATIS_BT_LO_RX_1_8814B) & \
+ BIT_MASK_STATIS_BT_LO_RX_1_8814B)
+#define BIT_SET_STATIS_BT_LO_RX_1_8814B(x, v) \
+ (BIT_CLEAR_STATIS_BT_LO_RX_1_8814B(x) | BIT_STATIS_BT_LO_RX_1_8814B(v))
+
+#define BIT_SHIFT_STATIS_BT_LO_TX_1_8814B 0
+#define BIT_MASK_STATIS_BT_LO_TX_1_8814B 0xffff
+#define BIT_STATIS_BT_LO_TX_1_8814B(x) \
+ (((x) & BIT_MASK_STATIS_BT_LO_TX_1_8814B) \
+ << BIT_SHIFT_STATIS_BT_LO_TX_1_8814B)
+#define BITS_STATIS_BT_LO_TX_1_8814B \
+ (BIT_MASK_STATIS_BT_LO_TX_1_8814B << BIT_SHIFT_STATIS_BT_LO_TX_1_8814B)
+#define BIT_CLEAR_STATIS_BT_LO_TX_1_8814B(x) \
+ ((x) & (~BITS_STATIS_BT_LO_TX_1_8814B))
+#define BIT_GET_STATIS_BT_LO_TX_1_8814B(x) \
+ (((x) >> BIT_SHIFT_STATIS_BT_LO_TX_1_8814B) & \
+ BIT_MASK_STATIS_BT_LO_TX_1_8814B)
+#define BIT_SET_STATIS_BT_LO_TX_1_8814B(x, v) \
+ (BIT_CLEAR_STATIS_BT_LO_TX_1_8814B(x) | BIT_STATIS_BT_LO_TX_1_8814B(v))
+
+/* 2 REG_BT_STATISTICS_CONTROL_REGISTER_8814B */
+
+#define BIT_SHIFT_R_BT_CMD_RPT_8814B 16
+#define BIT_MASK_R_BT_CMD_RPT_8814B 0xffff
+#define BIT_R_BT_CMD_RPT_8814B(x) \
+ (((x) & BIT_MASK_R_BT_CMD_RPT_8814B) << BIT_SHIFT_R_BT_CMD_RPT_8814B)
+#define BITS_R_BT_CMD_RPT_8814B \
+ (BIT_MASK_R_BT_CMD_RPT_8814B << BIT_SHIFT_R_BT_CMD_RPT_8814B)
+#define BIT_CLEAR_R_BT_CMD_RPT_8814B(x) ((x) & (~BITS_R_BT_CMD_RPT_8814B))
+#define BIT_GET_R_BT_CMD_RPT_8814B(x) \
+ (((x) >> BIT_SHIFT_R_BT_CMD_RPT_8814B) & BIT_MASK_R_BT_CMD_RPT_8814B)
+#define BIT_SET_R_BT_CMD_RPT_8814B(x, v) \
+ (BIT_CLEAR_R_BT_CMD_RPT_8814B(x) | BIT_R_BT_CMD_RPT_8814B(v))
+
+#define BIT_SHIFT_R_RPT_FROM_BT_8814B 8
+#define BIT_MASK_R_RPT_FROM_BT_8814B 0xff
+#define BIT_R_RPT_FROM_BT_8814B(x) \
+ (((x) & BIT_MASK_R_RPT_FROM_BT_8814B) << BIT_SHIFT_R_RPT_FROM_BT_8814B)
+#define BITS_R_RPT_FROM_BT_8814B \
+ (BIT_MASK_R_RPT_FROM_BT_8814B << BIT_SHIFT_R_RPT_FROM_BT_8814B)
+#define BIT_CLEAR_R_RPT_FROM_BT_8814B(x) ((x) & (~BITS_R_RPT_FROM_BT_8814B))
+#define BIT_GET_R_RPT_FROM_BT_8814B(x) \
+ (((x) >> BIT_SHIFT_R_RPT_FROM_BT_8814B) & BIT_MASK_R_RPT_FROM_BT_8814B)
+#define BIT_SET_R_RPT_FROM_BT_8814B(x, v) \
+ (BIT_CLEAR_R_RPT_FROM_BT_8814B(x) | BIT_R_RPT_FROM_BT_8814B(v))
+
+#define BIT_SHIFT_BT_HID_ISR_SET_8814B 6
+#define BIT_MASK_BT_HID_ISR_SET_8814B 0x3
+#define BIT_BT_HID_ISR_SET_8814B(x) \
+ (((x) & BIT_MASK_BT_HID_ISR_SET_8814B) \
+ << BIT_SHIFT_BT_HID_ISR_SET_8814B)
+#define BITS_BT_HID_ISR_SET_8814B \
+ (BIT_MASK_BT_HID_ISR_SET_8814B << BIT_SHIFT_BT_HID_ISR_SET_8814B)
+#define BIT_CLEAR_BT_HID_ISR_SET_8814B(x) ((x) & (~BITS_BT_HID_ISR_SET_8814B))
+#define BIT_GET_BT_HID_ISR_SET_8814B(x) \
+ (((x) >> BIT_SHIFT_BT_HID_ISR_SET_8814B) & \
+ BIT_MASK_BT_HID_ISR_SET_8814B)
+#define BIT_SET_BT_HID_ISR_SET_8814B(x, v) \
+ (BIT_CLEAR_BT_HID_ISR_SET_8814B(x) | BIT_BT_HID_ISR_SET_8814B(v))
+
+#define BIT_TDMA_BT_START_NOTIFY_8814B BIT(5)
+#define BIT_ENABLE_TDMA_FW_MODE_8814B BIT(4)
+#define BIT_ENABLE_PTA_TDMA_MODE_8814B BIT(3)
+#define BIT_ENABLE_COEXIST_TAB_IN_TDMA_8814B BIT(2)
+#define BIT_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA_8814B BIT(1)
+#define BIT_RTK_BT_ENABLE_8814B BIT(0)
+
+/* 2 REG_BT_STATUS_REPORT_REGISTER_8814B */
+
+#define BIT_SHIFT_BT_PROFILE_8814B 24
+#define BIT_MASK_BT_PROFILE_8814B 0xff
+#define BIT_BT_PROFILE_8814B(x) \
+ (((x) & BIT_MASK_BT_PROFILE_8814B) << BIT_SHIFT_BT_PROFILE_8814B)
+#define BITS_BT_PROFILE_8814B \
+ (BIT_MASK_BT_PROFILE_8814B << BIT_SHIFT_BT_PROFILE_8814B)
+#define BIT_CLEAR_BT_PROFILE_8814B(x) ((x) & (~BITS_BT_PROFILE_8814B))
+#define BIT_GET_BT_PROFILE_8814B(x) \
+ (((x) >> BIT_SHIFT_BT_PROFILE_8814B) & BIT_MASK_BT_PROFILE_8814B)
+#define BIT_SET_BT_PROFILE_8814B(x, v) \
+ (BIT_CLEAR_BT_PROFILE_8814B(x) | BIT_BT_PROFILE_8814B(v))
+
+#define BIT_SHIFT_BT_POWER_8814B 16
+#define BIT_MASK_BT_POWER_8814B 0xff
+#define BIT_BT_POWER_8814B(x) \
+ (((x) & BIT_MASK_BT_POWER_8814B) << BIT_SHIFT_BT_POWER_8814B)
+#define BITS_BT_POWER_8814B \
+ (BIT_MASK_BT_POWER_8814B << BIT_SHIFT_BT_POWER_8814B)
+#define BIT_CLEAR_BT_POWER_8814B(x) ((x) & (~BITS_BT_POWER_8814B))
+#define BIT_GET_BT_POWER_8814B(x) \
+ (((x) >> BIT_SHIFT_BT_POWER_8814B) & BIT_MASK_BT_POWER_8814B)
+#define BIT_SET_BT_POWER_8814B(x, v) \
+ (BIT_CLEAR_BT_POWER_8814B(x) | BIT_BT_POWER_8814B(v))
+
+#define BIT_SHIFT_BT_PREDECT_STATUS_8814B 8
+#define BIT_MASK_BT_PREDECT_STATUS_8814B 0xff
+#define BIT_BT_PREDECT_STATUS_8814B(x) \
+ (((x) & BIT_MASK_BT_PREDECT_STATUS_8814B) \
+ << BIT_SHIFT_BT_PREDECT_STATUS_8814B)
+#define BITS_BT_PREDECT_STATUS_8814B \
+ (BIT_MASK_BT_PREDECT_STATUS_8814B << BIT_SHIFT_BT_PREDECT_STATUS_8814B)
+#define BIT_CLEAR_BT_PREDECT_STATUS_8814B(x) \
+ ((x) & (~BITS_BT_PREDECT_STATUS_8814B))
+#define BIT_GET_BT_PREDECT_STATUS_8814B(x) \
+ (((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8814B) & \
+ BIT_MASK_BT_PREDECT_STATUS_8814B)
+#define BIT_SET_BT_PREDECT_STATUS_8814B(x, v) \
+ (BIT_CLEAR_BT_PREDECT_STATUS_8814B(x) | BIT_BT_PREDECT_STATUS_8814B(v))
+
+#define BIT_SHIFT_BT_CMD_INFO_8814B 0
+#define BIT_MASK_BT_CMD_INFO_8814B 0xff
+#define BIT_BT_CMD_INFO_8814B(x) \
+ (((x) & BIT_MASK_BT_CMD_INFO_8814B) << BIT_SHIFT_BT_CMD_INFO_8814B)
+#define BITS_BT_CMD_INFO_8814B \
+ (BIT_MASK_BT_CMD_INFO_8814B << BIT_SHIFT_BT_CMD_INFO_8814B)
+#define BIT_CLEAR_BT_CMD_INFO_8814B(x) ((x) & (~BITS_BT_CMD_INFO_8814B))
+#define BIT_GET_BT_CMD_INFO_8814B(x) \
+ (((x) >> BIT_SHIFT_BT_CMD_INFO_8814B) & BIT_MASK_BT_CMD_INFO_8814B)
+#define BIT_SET_BT_CMD_INFO_8814B(x, v) \
+ (BIT_CLEAR_BT_CMD_INFO_8814B(x) | BIT_BT_CMD_INFO_8814B(v))
+
+/* 2 REG_BT_INTERRUPT_CONTROL_REGISTER_8814B */
+#define BIT_EN_MAC_NULL_PKT_NOTIFY_8814B BIT(31)
+#define BIT_EN_WLAN_RPT_AND_BT_QUERY_8814B BIT(30)
+#define BIT_EN_BT_STSTUS_RPT_8814B BIT(29)
+#define BIT_EN_BT_POWER_8814B BIT(28)
+#define BIT_EN_BT_CHANNEL_8814B BIT(27)
+#define BIT_EN_BT_SLOT_CHANGE_8814B BIT(26)
+#define BIT_EN_BT_PROFILE_OR_HID_8814B BIT(25)
+#define BIT_WLAN_RPT_NOTIFY_8814B BIT(24)
+
+#define BIT_SHIFT_WLAN_RPT_DATA_8814B 16
+#define BIT_MASK_WLAN_RPT_DATA_8814B 0xff
+#define BIT_WLAN_RPT_DATA_8814B(x) \
+ (((x) & BIT_MASK_WLAN_RPT_DATA_8814B) << BIT_SHIFT_WLAN_RPT_DATA_8814B)
+#define BITS_WLAN_RPT_DATA_8814B \
+ (BIT_MASK_WLAN_RPT_DATA_8814B << BIT_SHIFT_WLAN_RPT_DATA_8814B)
+#define BIT_CLEAR_WLAN_RPT_DATA_8814B(x) ((x) & (~BITS_WLAN_RPT_DATA_8814B))
+#define BIT_GET_WLAN_RPT_DATA_8814B(x) \
+ (((x) >> BIT_SHIFT_WLAN_RPT_DATA_8814B) & BIT_MASK_WLAN_RPT_DATA_8814B)
+#define BIT_SET_WLAN_RPT_DATA_8814B(x, v) \
+ (BIT_CLEAR_WLAN_RPT_DATA_8814B(x) | BIT_WLAN_RPT_DATA_8814B(v))
+
+#define BIT_SHIFT_CMD_ID_8814B 8
+#define BIT_MASK_CMD_ID_8814B 0xff
+#define BIT_CMD_ID_8814B(x) \
+ (((x) & BIT_MASK_CMD_ID_8814B) << BIT_SHIFT_CMD_ID_8814B)
+#define BITS_CMD_ID_8814B (BIT_MASK_CMD_ID_8814B << BIT_SHIFT_CMD_ID_8814B)
+#define BIT_CLEAR_CMD_ID_8814B(x) ((x) & (~BITS_CMD_ID_8814B))
+#define BIT_GET_CMD_ID_8814B(x) \
+ (((x) >> BIT_SHIFT_CMD_ID_8814B) & BIT_MASK_CMD_ID_8814B)
+#define BIT_SET_CMD_ID_8814B(x, v) \
+ (BIT_CLEAR_CMD_ID_8814B(x) | BIT_CMD_ID_8814B(v))
+
+#define BIT_SHIFT_BT_DATA_8814B 0
+#define BIT_MASK_BT_DATA_8814B 0xff
+#define BIT_BT_DATA_8814B(x) \
+ (((x) & BIT_MASK_BT_DATA_8814B) << BIT_SHIFT_BT_DATA_8814B)
+#define BITS_BT_DATA_8814B (BIT_MASK_BT_DATA_8814B << BIT_SHIFT_BT_DATA_8814B)
+#define BIT_CLEAR_BT_DATA_8814B(x) ((x) & (~BITS_BT_DATA_8814B))
+#define BIT_GET_BT_DATA_8814B(x) \
+ (((x) >> BIT_SHIFT_BT_DATA_8814B) & BIT_MASK_BT_DATA_8814B)
+#define BIT_SET_BT_DATA_8814B(x, v) \
+ (BIT_CLEAR_BT_DATA_8814B(x) | BIT_BT_DATA_8814B(v))
+
+/* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8814B */
+
+#define BIT_SHIFT_WLAN_RPT_TO_8814B 0
+#define BIT_MASK_WLAN_RPT_TO_8814B 0xff
+#define BIT_WLAN_RPT_TO_8814B(x) \
+ (((x) & BIT_MASK_WLAN_RPT_TO_8814B) << BIT_SHIFT_WLAN_RPT_TO_8814B)
+#define BITS_WLAN_RPT_TO_8814B \
+ (BIT_MASK_WLAN_RPT_TO_8814B << BIT_SHIFT_WLAN_RPT_TO_8814B)
+#define BIT_CLEAR_WLAN_RPT_TO_8814B(x) ((x) & (~BITS_WLAN_RPT_TO_8814B))
+#define BIT_GET_WLAN_RPT_TO_8814B(x) \
+ (((x) >> BIT_SHIFT_WLAN_RPT_TO_8814B) & BIT_MASK_WLAN_RPT_TO_8814B)
+#define BIT_SET_WLAN_RPT_TO_8814B(x, v) \
+ (BIT_CLEAR_WLAN_RPT_TO_8814B(x) | BIT_WLAN_RPT_TO_8814B(v))
+
+/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8814B */
+
+#define BIT_SHIFT_ISOLATION_CHK_0_8814B 1
+#define BIT_MASK_ISOLATION_CHK_0_8814B 0x7fffff
+#define BIT_ISOLATION_CHK_0_8814B(x) \
+ (((x) & BIT_MASK_ISOLATION_CHK_0_8814B) \
+ << BIT_SHIFT_ISOLATION_CHK_0_8814B)
+#define BITS_ISOLATION_CHK_0_8814B \
+ (BIT_MASK_ISOLATION_CHK_0_8814B << BIT_SHIFT_ISOLATION_CHK_0_8814B)
+#define BIT_CLEAR_ISOLATION_CHK_0_8814B(x) ((x) & (~BITS_ISOLATION_CHK_0_8814B))
+#define BIT_GET_ISOLATION_CHK_0_8814B(x) \
+ (((x) >> BIT_SHIFT_ISOLATION_CHK_0_8814B) & \
+ BIT_MASK_ISOLATION_CHK_0_8814B)
+#define BIT_SET_ISOLATION_CHK_0_8814B(x, v) \
+ (BIT_CLEAR_ISOLATION_CHK_0_8814B(x) | BIT_ISOLATION_CHK_0_8814B(v))
+
+#define BIT_ISOLATION_EN_8814B BIT(0)
+
+/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1_8814B */
+
+#define BIT_SHIFT_ISOLATION_CHK_1_8814B 0
+#define BIT_MASK_ISOLATION_CHK_1_8814B 0xffffffffL
+#define BIT_ISOLATION_CHK_1_8814B(x) \
+ (((x) & BIT_MASK_ISOLATION_CHK_1_8814B) \
+ << BIT_SHIFT_ISOLATION_CHK_1_8814B)
+#define BITS_ISOLATION_CHK_1_8814B \
+ (BIT_MASK_ISOLATION_CHK_1_8814B << BIT_SHIFT_ISOLATION_CHK_1_8814B)
+#define BIT_CLEAR_ISOLATION_CHK_1_8814B(x) ((x) & (~BITS_ISOLATION_CHK_1_8814B))
+#define BIT_GET_ISOLATION_CHK_1_8814B(x) \
+ (((x) >> BIT_SHIFT_ISOLATION_CHK_1_8814B) & \
+ BIT_MASK_ISOLATION_CHK_1_8814B)
+#define BIT_SET_ISOLATION_CHK_1_8814B(x, v) \
+ (BIT_CLEAR_ISOLATION_CHK_1_8814B(x) | BIT_ISOLATION_CHK_1_8814B(v))
+
+/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2_8814B */
+
+#define BIT_SHIFT_ISOLATION_CHK_2_8814B 0
+#define BIT_MASK_ISOLATION_CHK_2_8814B 0xffffff
+#define BIT_ISOLATION_CHK_2_8814B(x) \
+ (((x) & BIT_MASK_ISOLATION_CHK_2_8814B) \
+ << BIT_SHIFT_ISOLATION_CHK_2_8814B)
+#define BITS_ISOLATION_CHK_2_8814B \
+ (BIT_MASK_ISOLATION_CHK_2_8814B << BIT_SHIFT_ISOLATION_CHK_2_8814B)
+#define BIT_CLEAR_ISOLATION_CHK_2_8814B(x) ((x) & (~BITS_ISOLATION_CHK_2_8814B))
+#define BIT_GET_ISOLATION_CHK_2_8814B(x) \
+ (((x) >> BIT_SHIFT_ISOLATION_CHK_2_8814B) & \
+ BIT_MASK_ISOLATION_CHK_2_8814B)
+#define BIT_SET_ISOLATION_CHK_2_8814B(x, v) \
+ (BIT_CLEAR_ISOLATION_CHK_2_8814B(x) | BIT_ISOLATION_CHK_2_8814B(v))
+
+/* 2 REG_BT_INTERRUPT_STATUS_REGISTER_8814B */
+#define BIT_BT_HID_ISR_8814B BIT(7)
+#define BIT_BT_QUERY_ISR_8814B BIT(6)
+#define BIT_MAC_NULL_PKT_NOTIFY_ISR_8814B BIT(5)
+#define BIT_WLAN_RPT_ISR_8814B BIT(4)
+#define BIT_BT_POWER_ISR_8814B BIT(3)
+#define BIT_BT_CHANNEL_ISR_8814B BIT(2)
+#define BIT_BT_SLOT_CHANGE_ISR_8814B BIT(1)
+#define BIT_BT_PROFILE_ISR_8814B BIT(0)
+
+/* 2 REG_BT_TDMA_TIME_REGISTER_8814B */
+
+#define BIT_SHIFT_BT_TIME_8814B 6
+#define BIT_MASK_BT_TIME_8814B 0x3ffffff
+#define BIT_BT_TIME_8814B(x) \
+ (((x) & BIT_MASK_BT_TIME_8814B) << BIT_SHIFT_BT_TIME_8814B)
+#define BITS_BT_TIME_8814B (BIT_MASK_BT_TIME_8814B << BIT_SHIFT_BT_TIME_8814B)
+#define BIT_CLEAR_BT_TIME_8814B(x) ((x) & (~BITS_BT_TIME_8814B))
+#define BIT_GET_BT_TIME_8814B(x) \
+ (((x) >> BIT_SHIFT_BT_TIME_8814B) & BIT_MASK_BT_TIME_8814B)
+#define BIT_SET_BT_TIME_8814B(x, v) \
+ (BIT_CLEAR_BT_TIME_8814B(x) | BIT_BT_TIME_8814B(v))
+
+#define BIT_SHIFT_BT_RPT_SAMPLE_RATE_8814B 0
+#define BIT_MASK_BT_RPT_SAMPLE_RATE_8814B 0x3f
+#define BIT_BT_RPT_SAMPLE_RATE_8814B(x) \
+ (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8814B) \
+ << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8814B)
+#define BITS_BT_RPT_SAMPLE_RATE_8814B \
+ (BIT_MASK_BT_RPT_SAMPLE_RATE_8814B \
+ << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8814B)
+#define BIT_CLEAR_BT_RPT_SAMPLE_RATE_8814B(x) \
+ ((x) & (~BITS_BT_RPT_SAMPLE_RATE_8814B))
+#define BIT_GET_BT_RPT_SAMPLE_RATE_8814B(x) \
+ (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8814B) & \
+ BIT_MASK_BT_RPT_SAMPLE_RATE_8814B)
+#define BIT_SET_BT_RPT_SAMPLE_RATE_8814B(x, v) \
+ (BIT_CLEAR_BT_RPT_SAMPLE_RATE_8814B(x) | \
+ BIT_BT_RPT_SAMPLE_RATE_8814B(v))
+
+/* 2 REG_BT_ACT_REGISTER_8814B */
+
+#define BIT_SHIFT_BT_EISR_EN_8814B 16
+#define BIT_MASK_BT_EISR_EN_8814B 0xff
+#define BIT_BT_EISR_EN_8814B(x) \
+ (((x) & BIT_MASK_BT_EISR_EN_8814B) << BIT_SHIFT_BT_EISR_EN_8814B)
+#define BITS_BT_EISR_EN_8814B \
+ (BIT_MASK_BT_EISR_EN_8814B << BIT_SHIFT_BT_EISR_EN_8814B)
+#define BIT_CLEAR_BT_EISR_EN_8814B(x) ((x) & (~BITS_BT_EISR_EN_8814B))
+#define BIT_GET_BT_EISR_EN_8814B(x) \
+ (((x) >> BIT_SHIFT_BT_EISR_EN_8814B) & BIT_MASK_BT_EISR_EN_8814B)
+#define BIT_SET_BT_EISR_EN_8814B(x, v) \
+ (BIT_CLEAR_BT_EISR_EN_8814B(x) | BIT_BT_EISR_EN_8814B(v))
+
+#define BIT_BT_ACT_FALLING_ISR_8814B BIT(10)
+#define BIT_BT_ACT_RISING_ISR_8814B BIT(9)
+#define BIT_TDMA_TO_ISR_8814B BIT(8)
+
+#define BIT_SHIFT_BT_CH_8814B 0
+#define BIT_MASK_BT_CH_8814B 0xff
+#define BIT_BT_CH_8814B(x) \
+ (((x) & BIT_MASK_BT_CH_8814B) << BIT_SHIFT_BT_CH_8814B)
+#define BITS_BT_CH_8814B (BIT_MASK_BT_CH_8814B << BIT_SHIFT_BT_CH_8814B)
+#define BIT_CLEAR_BT_CH_8814B(x) ((x) & (~BITS_BT_CH_8814B))
+#define BIT_GET_BT_CH_8814B(x) \
+ (((x) >> BIT_SHIFT_BT_CH_8814B) & BIT_MASK_BT_CH_8814B)
+#define BIT_SET_BT_CH_8814B(x, v) \
+ (BIT_CLEAR_BT_CH_8814B(x) | BIT_BT_CH_8814B(v))
+
+/* 2 REG_OBFF_CTRL_BASIC_8814B */
+#define BIT_OBFF_EN_V1_8814B BIT(31)
+
+#define BIT_SHIFT_OBFF_STATE_V1_8814B 28
+#define BIT_MASK_OBFF_STATE_V1_8814B 0x3
+#define BIT_OBFF_STATE_V1_8814B(x) \
+ (((x) & BIT_MASK_OBFF_STATE_V1_8814B) << BIT_SHIFT_OBFF_STATE_V1_8814B)
+#define BITS_OBFF_STATE_V1_8814B \
+ (BIT_MASK_OBFF_STATE_V1_8814B << BIT_SHIFT_OBFF_STATE_V1_8814B)
+#define BIT_CLEAR_OBFF_STATE_V1_8814B(x) ((x) & (~BITS_OBFF_STATE_V1_8814B))
+#define BIT_GET_OBFF_STATE_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_OBFF_STATE_V1_8814B) & BIT_MASK_OBFF_STATE_V1_8814B)
+#define BIT_SET_OBFF_STATE_V1_8814B(x, v) \
+ (BIT_CLEAR_OBFF_STATE_V1_8814B(x) | BIT_OBFF_STATE_V1_8814B(v))
+
+#define BIT_OBFF_ACT_RXDMA_EN_8814B BIT(27)
+#define BIT_OBFF_BLOCK_INT_EN_8814B BIT(26)
+#define BIT_OBFF_AUTOACT_EN_8814B BIT(25)
+#define BIT_OBFF_AUTOIDLE_EN_8814B BIT(24)
+
+#define BIT_SHIFT_WAKE_MAX_PLS_8814B 20
+#define BIT_MASK_WAKE_MAX_PLS_8814B 0x7
+#define BIT_WAKE_MAX_PLS_8814B(x) \
+ (((x) & BIT_MASK_WAKE_MAX_PLS_8814B) << BIT_SHIFT_WAKE_MAX_PLS_8814B)
+#define BITS_WAKE_MAX_PLS_8814B \
+ (BIT_MASK_WAKE_MAX_PLS_8814B << BIT_SHIFT_WAKE_MAX_PLS_8814B)
+#define BIT_CLEAR_WAKE_MAX_PLS_8814B(x) ((x) & (~BITS_WAKE_MAX_PLS_8814B))
+#define BIT_GET_WAKE_MAX_PLS_8814B(x) \
+ (((x) >> BIT_SHIFT_WAKE_MAX_PLS_8814B) & BIT_MASK_WAKE_MAX_PLS_8814B)
+#define BIT_SET_WAKE_MAX_PLS_8814B(x, v) \
+ (BIT_CLEAR_WAKE_MAX_PLS_8814B(x) | BIT_WAKE_MAX_PLS_8814B(v))
+
+#define BIT_SHIFT_WAKE_MIN_PLS_8814B 16
+#define BIT_MASK_WAKE_MIN_PLS_8814B 0x7
+#define BIT_WAKE_MIN_PLS_8814B(x) \
+ (((x) & BIT_MASK_WAKE_MIN_PLS_8814B) << BIT_SHIFT_WAKE_MIN_PLS_8814B)
+#define BITS_WAKE_MIN_PLS_8814B \
+ (BIT_MASK_WAKE_MIN_PLS_8814B << BIT_SHIFT_WAKE_MIN_PLS_8814B)
+#define BIT_CLEAR_WAKE_MIN_PLS_8814B(x) ((x) & (~BITS_WAKE_MIN_PLS_8814B))
+#define BIT_GET_WAKE_MIN_PLS_8814B(x) \
+ (((x) >> BIT_SHIFT_WAKE_MIN_PLS_8814B) & BIT_MASK_WAKE_MIN_PLS_8814B)
+#define BIT_SET_WAKE_MIN_PLS_8814B(x, v) \
+ (BIT_CLEAR_WAKE_MIN_PLS_8814B(x) | BIT_WAKE_MIN_PLS_8814B(v))
+
+#define BIT_SHIFT_WAKE_MAX_F2F_8814B 12
+#define BIT_MASK_WAKE_MAX_F2F_8814B 0x7
+#define BIT_WAKE_MAX_F2F_8814B(x) \
+ (((x) & BIT_MASK_WAKE_MAX_F2F_8814B) << BIT_SHIFT_WAKE_MAX_F2F_8814B)
+#define BITS_WAKE_MAX_F2F_8814B \
+ (BIT_MASK_WAKE_MAX_F2F_8814B << BIT_SHIFT_WAKE_MAX_F2F_8814B)
+#define BIT_CLEAR_WAKE_MAX_F2F_8814B(x) ((x) & (~BITS_WAKE_MAX_F2F_8814B))
+#define BIT_GET_WAKE_MAX_F2F_8814B(x) \
+ (((x) >> BIT_SHIFT_WAKE_MAX_F2F_8814B) & BIT_MASK_WAKE_MAX_F2F_8814B)
+#define BIT_SET_WAKE_MAX_F2F_8814B(x, v) \
+ (BIT_CLEAR_WAKE_MAX_F2F_8814B(x) | BIT_WAKE_MAX_F2F_8814B(v))
+
+#define BIT_SHIFT_WAKE_MIN_F2F_8814B 8
+#define BIT_MASK_WAKE_MIN_F2F_8814B 0x7
+#define BIT_WAKE_MIN_F2F_8814B(x) \
+ (((x) & BIT_MASK_WAKE_MIN_F2F_8814B) << BIT_SHIFT_WAKE_MIN_F2F_8814B)
+#define BITS_WAKE_MIN_F2F_8814B \
+ (BIT_MASK_WAKE_MIN_F2F_8814B << BIT_SHIFT_WAKE_MIN_F2F_8814B)
+#define BIT_CLEAR_WAKE_MIN_F2F_8814B(x) ((x) & (~BITS_WAKE_MIN_F2F_8814B))
+#define BIT_GET_WAKE_MIN_F2F_8814B(x) \
+ (((x) >> BIT_SHIFT_WAKE_MIN_F2F_8814B) & BIT_MASK_WAKE_MIN_F2F_8814B)
+#define BIT_SET_WAKE_MIN_F2F_8814B(x, v) \
+ (BIT_CLEAR_WAKE_MIN_F2F_8814B(x) | BIT_WAKE_MIN_F2F_8814B(v))
+
+#define BIT_APP_CPU_ACT_V1_8814B BIT(3)
+#define BIT_APP_OBFF_V1_8814B BIT(2)
+#define BIT_APP_IDLE_V1_8814B BIT(1)
+#define BIT_APP_INIT_V1_8814B BIT(0)
+
+/* 2 REG_OBFF_CTRL2_TIMER_8814B */
+
+#define BIT_SHIFT_RX_HIGH_TIMER_IDX_8814B 24
+#define BIT_MASK_RX_HIGH_TIMER_IDX_8814B 0x7
+#define BIT_RX_HIGH_TIMER_IDX_8814B(x) \
+ (((x) & BIT_MASK_RX_HIGH_TIMER_IDX_8814B) \
+ << BIT_SHIFT_RX_HIGH_TIMER_IDX_8814B)
+#define BITS_RX_HIGH_TIMER_IDX_8814B \
+ (BIT_MASK_RX_HIGH_TIMER_IDX_8814B << BIT_SHIFT_RX_HIGH_TIMER_IDX_8814B)
+#define BIT_CLEAR_RX_HIGH_TIMER_IDX_8814B(x) \
+ ((x) & (~BITS_RX_HIGH_TIMER_IDX_8814B))
+#define BIT_GET_RX_HIGH_TIMER_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8814B) & \
+ BIT_MASK_RX_HIGH_TIMER_IDX_8814B)
+#define BIT_SET_RX_HIGH_TIMER_IDX_8814B(x, v) \
+ (BIT_CLEAR_RX_HIGH_TIMER_IDX_8814B(x) | BIT_RX_HIGH_TIMER_IDX_8814B(v))
+
+#define BIT_SHIFT_RX_MED_TIMER_IDX_8814B 16
+#define BIT_MASK_RX_MED_TIMER_IDX_8814B 0x7
+#define BIT_RX_MED_TIMER_IDX_8814B(x) \
+ (((x) & BIT_MASK_RX_MED_TIMER_IDX_8814B) \
+ << BIT_SHIFT_RX_MED_TIMER_IDX_8814B)
+#define BITS_RX_MED_TIMER_IDX_8814B \
+ (BIT_MASK_RX_MED_TIMER_IDX_8814B << BIT_SHIFT_RX_MED_TIMER_IDX_8814B)
+#define BIT_CLEAR_RX_MED_TIMER_IDX_8814B(x) \
+ ((x) & (~BITS_RX_MED_TIMER_IDX_8814B))
+#define BIT_GET_RX_MED_TIMER_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8814B) & \
+ BIT_MASK_RX_MED_TIMER_IDX_8814B)
+#define BIT_SET_RX_MED_TIMER_IDX_8814B(x, v) \
+ (BIT_CLEAR_RX_MED_TIMER_IDX_8814B(x) | BIT_RX_MED_TIMER_IDX_8814B(v))
+
+#define BIT_SHIFT_RX_LOW_TIMER_IDX_8814B 8
+#define BIT_MASK_RX_LOW_TIMER_IDX_8814B 0x7
+#define BIT_RX_LOW_TIMER_IDX_8814B(x) \
+ (((x) & BIT_MASK_RX_LOW_TIMER_IDX_8814B) \
+ << BIT_SHIFT_RX_LOW_TIMER_IDX_8814B)
+#define BITS_RX_LOW_TIMER_IDX_8814B \
+ (BIT_MASK_RX_LOW_TIMER_IDX_8814B << BIT_SHIFT_RX_LOW_TIMER_IDX_8814B)
+#define BIT_CLEAR_RX_LOW_TIMER_IDX_8814B(x) \
+ ((x) & (~BITS_RX_LOW_TIMER_IDX_8814B))
+#define BIT_GET_RX_LOW_TIMER_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8814B) & \
+ BIT_MASK_RX_LOW_TIMER_IDX_8814B)
+#define BIT_SET_RX_LOW_TIMER_IDX_8814B(x, v) \
+ (BIT_CLEAR_RX_LOW_TIMER_IDX_8814B(x) | BIT_RX_LOW_TIMER_IDX_8814B(v))
+
+#define BIT_SHIFT_OBFF_INT_TIMER_IDX_8814B 0
+#define BIT_MASK_OBFF_INT_TIMER_IDX_8814B 0x7
+#define BIT_OBFF_INT_TIMER_IDX_8814B(x) \
+ (((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8814B) \
+ << BIT_SHIFT_OBFF_INT_TIMER_IDX_8814B)
+#define BITS_OBFF_INT_TIMER_IDX_8814B \
+ (BIT_MASK_OBFF_INT_TIMER_IDX_8814B \
+ << BIT_SHIFT_OBFF_INT_TIMER_IDX_8814B)
+#define BIT_CLEAR_OBFF_INT_TIMER_IDX_8814B(x) \
+ ((x) & (~BITS_OBFF_INT_TIMER_IDX_8814B))
+#define BIT_GET_OBFF_INT_TIMER_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8814B) & \
+ BIT_MASK_OBFF_INT_TIMER_IDX_8814B)
+#define BIT_SET_OBFF_INT_TIMER_IDX_8814B(x, v) \
+ (BIT_CLEAR_OBFF_INT_TIMER_IDX_8814B(x) | \
+ BIT_OBFF_INT_TIMER_IDX_8814B(v))
+
+/* 2 REG_LTR_CTRL_BASIC_8814B */
+#define BIT_LTR_EN_V1_8814B BIT(31)
+#define BIT_LTR_HW_EN_V1_8814B BIT(30)
+#define BIT_LRT_ACT_CTS_EN_8814B BIT(29)
+#define BIT_LTR_ACT_RXPKT_EN_8814B BIT(28)
+#define BIT_LTR_ACT_RXDMA_EN_8814B BIT(27)
+#define BIT_LTR_IDLE_NO_SNOOP_8814B BIT(26)
+#define BIT_SPDUP_MGTPKT_8814B BIT(25)
+#define BIT_RX_AGG_EN_8814B BIT(24)
+#define BIT_APP_LTR_ACT_8814B BIT(23)
+#define BIT_APP_LTR_IDLE_8814B BIT(22)
+
+#define BIT_SHIFT_HIGH_RATE_TRIG_SEL_8814B 20
+#define BIT_MASK_HIGH_RATE_TRIG_SEL_8814B 0x3
+#define BIT_HIGH_RATE_TRIG_SEL_8814B(x) \
+ (((x) & BIT_MASK_HIGH_RATE_TRIG_SEL_8814B) \
+ << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8814B)
+#define BITS_HIGH_RATE_TRIG_SEL_8814B \
+ (BIT_MASK_HIGH_RATE_TRIG_SEL_8814B \
+ << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8814B)
+#define BIT_CLEAR_HIGH_RATE_TRIG_SEL_8814B(x) \
+ ((x) & (~BITS_HIGH_RATE_TRIG_SEL_8814B))
+#define BIT_GET_HIGH_RATE_TRIG_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8814B) & \
+ BIT_MASK_HIGH_RATE_TRIG_SEL_8814B)
+#define BIT_SET_HIGH_RATE_TRIG_SEL_8814B(x, v) \
+ (BIT_CLEAR_HIGH_RATE_TRIG_SEL_8814B(x) | \
+ BIT_HIGH_RATE_TRIG_SEL_8814B(v))
+
+#define BIT_SHIFT_MED_RATE_TRIG_SEL_8814B 18
+#define BIT_MASK_MED_RATE_TRIG_SEL_8814B 0x3
+#define BIT_MED_RATE_TRIG_SEL_8814B(x) \
+ (((x) & BIT_MASK_MED_RATE_TRIG_SEL_8814B) \
+ << BIT_SHIFT_MED_RATE_TRIG_SEL_8814B)
+#define BITS_MED_RATE_TRIG_SEL_8814B \
+ (BIT_MASK_MED_RATE_TRIG_SEL_8814B << BIT_SHIFT_MED_RATE_TRIG_SEL_8814B)
+#define BIT_CLEAR_MED_RATE_TRIG_SEL_8814B(x) \
+ ((x) & (~BITS_MED_RATE_TRIG_SEL_8814B))
+#define BIT_GET_MED_RATE_TRIG_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8814B) & \
+ BIT_MASK_MED_RATE_TRIG_SEL_8814B)
+#define BIT_SET_MED_RATE_TRIG_SEL_8814B(x, v) \
+ (BIT_CLEAR_MED_RATE_TRIG_SEL_8814B(x) | BIT_MED_RATE_TRIG_SEL_8814B(v))
+
+#define BIT_SHIFT_LOW_RATE_TRIG_SEL_8814B 16
+#define BIT_MASK_LOW_RATE_TRIG_SEL_8814B 0x3
+#define BIT_LOW_RATE_TRIG_SEL_8814B(x) \
+ (((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8814B) \
+ << BIT_SHIFT_LOW_RATE_TRIG_SEL_8814B)
+#define BITS_LOW_RATE_TRIG_SEL_8814B \
+ (BIT_MASK_LOW_RATE_TRIG_SEL_8814B << BIT_SHIFT_LOW_RATE_TRIG_SEL_8814B)
+#define BIT_CLEAR_LOW_RATE_TRIG_SEL_8814B(x) \
+ ((x) & (~BITS_LOW_RATE_TRIG_SEL_8814B))
+#define BIT_GET_LOW_RATE_TRIG_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8814B) & \
+ BIT_MASK_LOW_RATE_TRIG_SEL_8814B)
+#define BIT_SET_LOW_RATE_TRIG_SEL_8814B(x, v) \
+ (BIT_CLEAR_LOW_RATE_TRIG_SEL_8814B(x) | BIT_LOW_RATE_TRIG_SEL_8814B(v))
+
+#define BIT_SHIFT_HIGH_RATE_BD_IDX_8814B 8
+#define BIT_MASK_HIGH_RATE_BD_IDX_8814B 0x7f
+#define BIT_HIGH_RATE_BD_IDX_8814B(x) \
+ (((x) & BIT_MASK_HIGH_RATE_BD_IDX_8814B) \
+ << BIT_SHIFT_HIGH_RATE_BD_IDX_8814B)
+#define BITS_HIGH_RATE_BD_IDX_8814B \
+ (BIT_MASK_HIGH_RATE_BD_IDX_8814B << BIT_SHIFT_HIGH_RATE_BD_IDX_8814B)
+#define BIT_CLEAR_HIGH_RATE_BD_IDX_8814B(x) \
+ ((x) & (~BITS_HIGH_RATE_BD_IDX_8814B))
+#define BIT_GET_HIGH_RATE_BD_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8814B) & \
+ BIT_MASK_HIGH_RATE_BD_IDX_8814B)
+#define BIT_SET_HIGH_RATE_BD_IDX_8814B(x, v) \
+ (BIT_CLEAR_HIGH_RATE_BD_IDX_8814B(x) | BIT_HIGH_RATE_BD_IDX_8814B(v))
+
+#define BIT_SHIFT_LOW_RATE_BD_IDX_8814B 0
+#define BIT_MASK_LOW_RATE_BD_IDX_8814B 0x7f
+#define BIT_LOW_RATE_BD_IDX_8814B(x) \
+ (((x) & BIT_MASK_LOW_RATE_BD_IDX_8814B) \
+ << BIT_SHIFT_LOW_RATE_BD_IDX_8814B)
+#define BITS_LOW_RATE_BD_IDX_8814B \
+ (BIT_MASK_LOW_RATE_BD_IDX_8814B << BIT_SHIFT_LOW_RATE_BD_IDX_8814B)
+#define BIT_CLEAR_LOW_RATE_BD_IDX_8814B(x) ((x) & (~BITS_LOW_RATE_BD_IDX_8814B))
+#define BIT_GET_LOW_RATE_BD_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8814B) & \
+ BIT_MASK_LOW_RATE_BD_IDX_8814B)
+#define BIT_SET_LOW_RATE_BD_IDX_8814B(x, v) \
+ (BIT_CLEAR_LOW_RATE_BD_IDX_8814B(x) | BIT_LOW_RATE_BD_IDX_8814B(v))
+
+/* 2 REG_LTR_CTRL2_TIMER_THRESHOLD_8814B */
+
+#define BIT_SHIFT_RX_EMPTY_TIMER_IDX_8814B 24
+#define BIT_MASK_RX_EMPTY_TIMER_IDX_8814B 0x7
+#define BIT_RX_EMPTY_TIMER_IDX_8814B(x) \
+ (((x) & BIT_MASK_RX_EMPTY_TIMER_IDX_8814B) \
+ << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8814B)
+#define BITS_RX_EMPTY_TIMER_IDX_8814B \
+ (BIT_MASK_RX_EMPTY_TIMER_IDX_8814B \
+ << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8814B)
+#define BIT_CLEAR_RX_EMPTY_TIMER_IDX_8814B(x) \
+ ((x) & (~BITS_RX_EMPTY_TIMER_IDX_8814B))
+#define BIT_GET_RX_EMPTY_TIMER_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8814B) & \
+ BIT_MASK_RX_EMPTY_TIMER_IDX_8814B)
+#define BIT_SET_RX_EMPTY_TIMER_IDX_8814B(x, v) \
+ (BIT_CLEAR_RX_EMPTY_TIMER_IDX_8814B(x) | \
+ BIT_RX_EMPTY_TIMER_IDX_8814B(v))
+
+#define BIT_SHIFT_RX_AFULL_TH_IDX_8814B 20
+#define BIT_MASK_RX_AFULL_TH_IDX_8814B 0x7
+#define BIT_RX_AFULL_TH_IDX_8814B(x) \
+ (((x) & BIT_MASK_RX_AFULL_TH_IDX_8814B) \
+ << BIT_SHIFT_RX_AFULL_TH_IDX_8814B)
+#define BITS_RX_AFULL_TH_IDX_8814B \
+ (BIT_MASK_RX_AFULL_TH_IDX_8814B << BIT_SHIFT_RX_AFULL_TH_IDX_8814B)
+#define BIT_CLEAR_RX_AFULL_TH_IDX_8814B(x) ((x) & (~BITS_RX_AFULL_TH_IDX_8814B))
+#define BIT_GET_RX_AFULL_TH_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8814B) & \
+ BIT_MASK_RX_AFULL_TH_IDX_8814B)
+#define BIT_SET_RX_AFULL_TH_IDX_8814B(x, v) \
+ (BIT_CLEAR_RX_AFULL_TH_IDX_8814B(x) | BIT_RX_AFULL_TH_IDX_8814B(v))
+
+#define BIT_SHIFT_RX_HIGH_TH_IDX_8814B 16
+#define BIT_MASK_RX_HIGH_TH_IDX_8814B 0x7
+#define BIT_RX_HIGH_TH_IDX_8814B(x) \
+ (((x) & BIT_MASK_RX_HIGH_TH_IDX_8814B) \
+ << BIT_SHIFT_RX_HIGH_TH_IDX_8814B)
+#define BITS_RX_HIGH_TH_IDX_8814B \
+ (BIT_MASK_RX_HIGH_TH_IDX_8814B << BIT_SHIFT_RX_HIGH_TH_IDX_8814B)
+#define BIT_CLEAR_RX_HIGH_TH_IDX_8814B(x) ((x) & (~BITS_RX_HIGH_TH_IDX_8814B))
+#define BIT_GET_RX_HIGH_TH_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8814B) & \
+ BIT_MASK_RX_HIGH_TH_IDX_8814B)
+#define BIT_SET_RX_HIGH_TH_IDX_8814B(x, v) \
+ (BIT_CLEAR_RX_HIGH_TH_IDX_8814B(x) | BIT_RX_HIGH_TH_IDX_8814B(v))
+
+#define BIT_SHIFT_RX_MED_TH_IDX_8814B 12
+#define BIT_MASK_RX_MED_TH_IDX_8814B 0x7
+#define BIT_RX_MED_TH_IDX_8814B(x) \
+ (((x) & BIT_MASK_RX_MED_TH_IDX_8814B) << BIT_SHIFT_RX_MED_TH_IDX_8814B)
+#define BITS_RX_MED_TH_IDX_8814B \
+ (BIT_MASK_RX_MED_TH_IDX_8814B << BIT_SHIFT_RX_MED_TH_IDX_8814B)
+#define BIT_CLEAR_RX_MED_TH_IDX_8814B(x) ((x) & (~BITS_RX_MED_TH_IDX_8814B))
+#define BIT_GET_RX_MED_TH_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_RX_MED_TH_IDX_8814B) & BIT_MASK_RX_MED_TH_IDX_8814B)
+#define BIT_SET_RX_MED_TH_IDX_8814B(x, v) \
+ (BIT_CLEAR_RX_MED_TH_IDX_8814B(x) | BIT_RX_MED_TH_IDX_8814B(v))
+
+#define BIT_SHIFT_RX_LOW_TH_IDX_8814B 8
+#define BIT_MASK_RX_LOW_TH_IDX_8814B 0x7
+#define BIT_RX_LOW_TH_IDX_8814B(x) \
+ (((x) & BIT_MASK_RX_LOW_TH_IDX_8814B) << BIT_SHIFT_RX_LOW_TH_IDX_8814B)
+#define BITS_RX_LOW_TH_IDX_8814B \
+ (BIT_MASK_RX_LOW_TH_IDX_8814B << BIT_SHIFT_RX_LOW_TH_IDX_8814B)
+#define BIT_CLEAR_RX_LOW_TH_IDX_8814B(x) ((x) & (~BITS_RX_LOW_TH_IDX_8814B))
+#define BIT_GET_RX_LOW_TH_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8814B) & BIT_MASK_RX_LOW_TH_IDX_8814B)
+#define BIT_SET_RX_LOW_TH_IDX_8814B(x, v) \
+ (BIT_CLEAR_RX_LOW_TH_IDX_8814B(x) | BIT_RX_LOW_TH_IDX_8814B(v))
+
+#define BIT_SHIFT_LTR_SPACE_IDX_8814B 4
+#define BIT_MASK_LTR_SPACE_IDX_8814B 0x3
+#define BIT_LTR_SPACE_IDX_8814B(x) \
+ (((x) & BIT_MASK_LTR_SPACE_IDX_8814B) << BIT_SHIFT_LTR_SPACE_IDX_8814B)
+#define BITS_LTR_SPACE_IDX_8814B \
+ (BIT_MASK_LTR_SPACE_IDX_8814B << BIT_SHIFT_LTR_SPACE_IDX_8814B)
+#define BIT_CLEAR_LTR_SPACE_IDX_8814B(x) ((x) & (~BITS_LTR_SPACE_IDX_8814B))
+#define BIT_GET_LTR_SPACE_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_LTR_SPACE_IDX_8814B) & BIT_MASK_LTR_SPACE_IDX_8814B)
+#define BIT_SET_LTR_SPACE_IDX_8814B(x, v) \
+ (BIT_CLEAR_LTR_SPACE_IDX_8814B(x) | BIT_LTR_SPACE_IDX_8814B(v))
+
+#define BIT_SHIFT_LTR_IDLE_TIMER_IDX_8814B 0
+#define BIT_MASK_LTR_IDLE_TIMER_IDX_8814B 0x7
+#define BIT_LTR_IDLE_TIMER_IDX_8814B(x) \
+ (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8814B) \
+ << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8814B)
+#define BITS_LTR_IDLE_TIMER_IDX_8814B \
+ (BIT_MASK_LTR_IDLE_TIMER_IDX_8814B \
+ << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8814B)
+#define BIT_CLEAR_LTR_IDLE_TIMER_IDX_8814B(x) \
+ ((x) & (~BITS_LTR_IDLE_TIMER_IDX_8814B))
+#define BIT_GET_LTR_IDLE_TIMER_IDX_8814B(x) \
+ (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8814B) & \
+ BIT_MASK_LTR_IDLE_TIMER_IDX_8814B)
+#define BIT_SET_LTR_IDLE_TIMER_IDX_8814B(x, v) \
+ (BIT_CLEAR_LTR_IDLE_TIMER_IDX_8814B(x) | \
+ BIT_LTR_IDLE_TIMER_IDX_8814B(v))
+
+/* 2 REG_LTR_IDLE_LATENCY_V1_8814B */
+
+#define BIT_SHIFT_LTR_IDLE_L_8814B 0
+#define BIT_MASK_LTR_IDLE_L_8814B 0xffffffffL
+#define BIT_LTR_IDLE_L_8814B(x) \
+ (((x) & BIT_MASK_LTR_IDLE_L_8814B) << BIT_SHIFT_LTR_IDLE_L_8814B)
+#define BITS_LTR_IDLE_L_8814B \
+ (BIT_MASK_LTR_IDLE_L_8814B << BIT_SHIFT_LTR_IDLE_L_8814B)
+#define BIT_CLEAR_LTR_IDLE_L_8814B(x) ((x) & (~BITS_LTR_IDLE_L_8814B))
+#define BIT_GET_LTR_IDLE_L_8814B(x) \
+ (((x) >> BIT_SHIFT_LTR_IDLE_L_8814B) & BIT_MASK_LTR_IDLE_L_8814B)
+#define BIT_SET_LTR_IDLE_L_8814B(x, v) \
+ (BIT_CLEAR_LTR_IDLE_L_8814B(x) | BIT_LTR_IDLE_L_8814B(v))
+
+/* 2 REG_LTR_ACTIVE_LATENCY_V1_8814B */
+
+#define BIT_SHIFT_LTR_ACT_L_8814B 0
+#define BIT_MASK_LTR_ACT_L_8814B 0xffffffffL
+#define BIT_LTR_ACT_L_8814B(x) \
+ (((x) & BIT_MASK_LTR_ACT_L_8814B) << BIT_SHIFT_LTR_ACT_L_8814B)
+#define BITS_LTR_ACT_L_8814B \
+ (BIT_MASK_LTR_ACT_L_8814B << BIT_SHIFT_LTR_ACT_L_8814B)
+#define BIT_CLEAR_LTR_ACT_L_8814B(x) ((x) & (~BITS_LTR_ACT_L_8814B))
+#define BIT_GET_LTR_ACT_L_8814B(x) \
+ (((x) >> BIT_SHIFT_LTR_ACT_L_8814B) & BIT_MASK_LTR_ACT_L_8814B)
+#define BIT_SET_LTR_ACT_L_8814B(x, v) \
+ (BIT_CLEAR_LTR_ACT_L_8814B(x) | BIT_LTR_ACT_L_8814B(v))
+
+#define BIT_SHIFT_ANT_ADDR2_1_8814B 0
+#define BIT_MASK_ANT_ADDR2_1_8814B 0xffffffffL
+#define BIT_ANT_ADDR2_1_8814B(x) \
+ (((x) & BIT_MASK_ANT_ADDR2_1_8814B) << BIT_SHIFT_ANT_ADDR2_1_8814B)
+#define BITS_ANT_ADDR2_1_8814B \
+ (BIT_MASK_ANT_ADDR2_1_8814B << BIT_SHIFT_ANT_ADDR2_1_8814B)
+#define BIT_CLEAR_ANT_ADDR2_1_8814B(x) ((x) & (~BITS_ANT_ADDR2_1_8814B))
+#define BIT_GET_ANT_ADDR2_1_8814B(x) \
+ (((x) >> BIT_SHIFT_ANT_ADDR2_1_8814B) & BIT_MASK_ANT_ADDR2_1_8814B)
+#define BIT_SET_ANT_ADDR2_1_8814B(x, v) \
+ (BIT_CLEAR_ANT_ADDR2_1_8814B(x) | BIT_ANT_ADDR2_1_8814B(v))
+
+/* 2 REG_SMART_ANT_CTRL_8814B */
+#define BIT_ANTTRN_SWITCH_8814B BIT(19)
+#define BIT_APPEND_MACID_IN_RESP_EN_1_8814B BIT(18)
+#define BIT_ADDR2_MATCH_EN_1_8814B BIT(17)
+#define BIT_ANTTRN_EN_1_8814B BIT(16)
+
+#define BIT_SHIFT_ANT_ADDR2_2_8814B 0
+#define BIT_MASK_ANT_ADDR2_2_8814B 0xffff
+#define BIT_ANT_ADDR2_2_8814B(x) \
+ (((x) & BIT_MASK_ANT_ADDR2_2_8814B) << BIT_SHIFT_ANT_ADDR2_2_8814B)
+#define BITS_ANT_ADDR2_2_8814B \
+ (BIT_MASK_ANT_ADDR2_2_8814B << BIT_SHIFT_ANT_ADDR2_2_8814B)
+#define BIT_CLEAR_ANT_ADDR2_2_8814B(x) ((x) & (~BITS_ANT_ADDR2_2_8814B))
+#define BIT_GET_ANT_ADDR2_2_8814B(x) \
+ (((x) >> BIT_SHIFT_ANT_ADDR2_2_8814B) & BIT_MASK_ANT_ADDR2_2_8814B)
+#define BIT_SET_ANT_ADDR2_2_8814B(x, v) \
+ (BIT_CLEAR_ANT_ADDR2_2_8814B(x) | BIT_ANT_ADDR2_2_8814B(v))
+
+/* 2 REG_CONTROL_FRAME_REPORT_8814B */
+
+#define BIT_SHIFT_CONTROL_FRAME_REPORT_8814B 0
+#define BIT_MASK_CONTROL_FRAME_REPORT_8814B 0xffffffffL
+#define BIT_CONTROL_FRAME_REPORT_8814B(x) \
+ (((x) & BIT_MASK_CONTROL_FRAME_REPORT_8814B) \
+ << BIT_SHIFT_CONTROL_FRAME_REPORT_8814B)
+#define BITS_CONTROL_FRAME_REPORT_8814B \
+ (BIT_MASK_CONTROL_FRAME_REPORT_8814B \
+ << BIT_SHIFT_CONTROL_FRAME_REPORT_8814B)
+#define BIT_CLEAR_CONTROL_FRAME_REPORT_8814B(x) \
+ ((x) & (~BITS_CONTROL_FRAME_REPORT_8814B))
+#define BIT_GET_CONTROL_FRAME_REPORT_8814B(x) \
+ (((x) >> BIT_SHIFT_CONTROL_FRAME_REPORT_8814B) & \
+ BIT_MASK_CONTROL_FRAME_REPORT_8814B)
+#define BIT_SET_CONTROL_FRAME_REPORT_8814B(x, v) \
+ (BIT_CLEAR_CONTROL_FRAME_REPORT_8814B(x) | \
+ BIT_CONTROL_FRAME_REPORT_8814B(v))
+
+/* 2 REG_CONTROL_FRAME_CNT_CTRL_8814B */
+#define BIT_ALLCNTRST_8814B BIT(9)
+#define BIT__ALLCNTEN_8814B BIT(8)
+
+#define BIT_SHIFT_ADDR_8814B 4
+#define BIT_MASK_ADDR_8814B 0xf
+#define BIT_ADDR_8814B(x) (((x) & BIT_MASK_ADDR_8814B) << BIT_SHIFT_ADDR_8814B)
+#define BITS_ADDR_8814B (BIT_MASK_ADDR_8814B << BIT_SHIFT_ADDR_8814B)
+#define BIT_CLEAR_ADDR_8814B(x) ((x) & (~BITS_ADDR_8814B))
+#define BIT_GET_ADDR_8814B(x) \
+ (((x) >> BIT_SHIFT_ADDR_8814B) & BIT_MASK_ADDR_8814B)
+#define BIT_SET_ADDR_8814B(x, v) (BIT_CLEAR_ADDR_8814B(x) | BIT_ADDR_8814B(v))
+
+#define BIT_SHIFT_CTRL_SEL_8814B 0
+#define BIT_MASK_CTRL_SEL_8814B 0xf
+#define BIT_CTRL_SEL_8814B(x) \
+ (((x) & BIT_MASK_CTRL_SEL_8814B) << BIT_SHIFT_CTRL_SEL_8814B)
+#define BITS_CTRL_SEL_8814B \
+ (BIT_MASK_CTRL_SEL_8814B << BIT_SHIFT_CTRL_SEL_8814B)
+#define BIT_CLEAR_CTRL_SEL_8814B(x) ((x) & (~BITS_CTRL_SEL_8814B))
+#define BIT_GET_CTRL_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_CTRL_SEL_8814B) & BIT_MASK_CTRL_SEL_8814B)
+#define BIT_SET_CTRL_SEL_8814B(x, v) \
+ (BIT_CLEAR_CTRL_SEL_8814B(x) | BIT_CTRL_SEL_8814B(v))
+
+/* 2 REG_IQ_DUMP_8814B */
+
+#define BIT_SHIFT_DUMP_OK_ADDR_8814B 16
+#define BIT_MASK_DUMP_OK_ADDR_8814B 0xffff
+#define BIT_DUMP_OK_ADDR_8814B(x) \
+ (((x) & BIT_MASK_DUMP_OK_ADDR_8814B) << BIT_SHIFT_DUMP_OK_ADDR_8814B)
+#define BITS_DUMP_OK_ADDR_8814B \
+ (BIT_MASK_DUMP_OK_ADDR_8814B << BIT_SHIFT_DUMP_OK_ADDR_8814B)
+#define BIT_CLEAR_DUMP_OK_ADDR_8814B(x) ((x) & (~BITS_DUMP_OK_ADDR_8814B))
+#define BIT_GET_DUMP_OK_ADDR_8814B(x) \
+ (((x) >> BIT_SHIFT_DUMP_OK_ADDR_8814B) & BIT_MASK_DUMP_OK_ADDR_8814B)
+#define BIT_SET_DUMP_OK_ADDR_8814B(x, v) \
+ (BIT_CLEAR_DUMP_OK_ADDR_8814B(x) | BIT_DUMP_OK_ADDR_8814B(v))
+
+#define BIT_SHIFT_R_TRIG_TIME_SEL_8814B 8
+#define BIT_MASK_R_TRIG_TIME_SEL_8814B 0x7f
+#define BIT_R_TRIG_TIME_SEL_8814B(x) \
+ (((x) & BIT_MASK_R_TRIG_TIME_SEL_8814B) \
+ << BIT_SHIFT_R_TRIG_TIME_SEL_8814B)
+#define BITS_R_TRIG_TIME_SEL_8814B \
+ (BIT_MASK_R_TRIG_TIME_SEL_8814B << BIT_SHIFT_R_TRIG_TIME_SEL_8814B)
+#define BIT_CLEAR_R_TRIG_TIME_SEL_8814B(x) ((x) & (~BITS_R_TRIG_TIME_SEL_8814B))
+#define BIT_GET_R_TRIG_TIME_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8814B) & \
+ BIT_MASK_R_TRIG_TIME_SEL_8814B)
+#define BIT_SET_R_TRIG_TIME_SEL_8814B(x, v) \
+ (BIT_CLEAR_R_TRIG_TIME_SEL_8814B(x) | BIT_R_TRIG_TIME_SEL_8814B(v))
+
+#define BIT_SHIFT_R_MAC_TRIG_SEL_8814B 6
+#define BIT_MASK_R_MAC_TRIG_SEL_8814B 0x3
+#define BIT_R_MAC_TRIG_SEL_8814B(x) \
+ (((x) & BIT_MASK_R_MAC_TRIG_SEL_8814B) \
+ << BIT_SHIFT_R_MAC_TRIG_SEL_8814B)
+#define BITS_R_MAC_TRIG_SEL_8814B \
+ (BIT_MASK_R_MAC_TRIG_SEL_8814B << BIT_SHIFT_R_MAC_TRIG_SEL_8814B)
+#define BIT_CLEAR_R_MAC_TRIG_SEL_8814B(x) ((x) & (~BITS_R_MAC_TRIG_SEL_8814B))
+#define BIT_GET_R_MAC_TRIG_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8814B) & \
+ BIT_MASK_R_MAC_TRIG_SEL_8814B)
+#define BIT_SET_R_MAC_TRIG_SEL_8814B(x, v) \
+ (BIT_CLEAR_R_MAC_TRIG_SEL_8814B(x) | BIT_R_MAC_TRIG_SEL_8814B(v))
+
+#define BIT_MAC_TRIG_REG_8814B BIT(5)
+
+#define BIT_SHIFT_R_LEVEL_PULSE_SEL_8814B 3
+#define BIT_MASK_R_LEVEL_PULSE_SEL_8814B 0x3
+#define BIT_R_LEVEL_PULSE_SEL_8814B(x) \
+ (((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8814B) \
+ << BIT_SHIFT_R_LEVEL_PULSE_SEL_8814B)
+#define BITS_R_LEVEL_PULSE_SEL_8814B \
+ (BIT_MASK_R_LEVEL_PULSE_SEL_8814B << BIT_SHIFT_R_LEVEL_PULSE_SEL_8814B)
+#define BIT_CLEAR_R_LEVEL_PULSE_SEL_8814B(x) \
+ ((x) & (~BITS_R_LEVEL_PULSE_SEL_8814B))
+#define BIT_GET_R_LEVEL_PULSE_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8814B) & \
+ BIT_MASK_R_LEVEL_PULSE_SEL_8814B)
+#define BIT_SET_R_LEVEL_PULSE_SEL_8814B(x, v) \
+ (BIT_CLEAR_R_LEVEL_PULSE_SEL_8814B(x) | BIT_R_LEVEL_PULSE_SEL_8814B(v))
+
+#define BIT_EN_LA_MAC_8814B BIT(2)
+#define BIT_R_EN_IQDUMP_8814B BIT(1)
+#define BIT_R_IQDATA_DUMP_8814B BIT(0)
+
+/* 2 REG_IQ_DUMP_1_8814B */
+
+#define BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8814B 0
+#define BIT_MASK_R_WMAC_MASK_LA_MAC_1_8814B 0xffffffffL
+#define BIT_R_WMAC_MASK_LA_MAC_1_8814B(x) \
+ (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_1_8814B) \
+ << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8814B)
+#define BITS_R_WMAC_MASK_LA_MAC_1_8814B \
+ (BIT_MASK_R_WMAC_MASK_LA_MAC_1_8814B \
+ << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8814B)
+#define BIT_CLEAR_R_WMAC_MASK_LA_MAC_1_8814B(x) \
+ ((x) & (~BITS_R_WMAC_MASK_LA_MAC_1_8814B))
+#define BIT_GET_R_WMAC_MASK_LA_MAC_1_8814B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8814B) & \
+ BIT_MASK_R_WMAC_MASK_LA_MAC_1_8814B)
+#define BIT_SET_R_WMAC_MASK_LA_MAC_1_8814B(x, v) \
+ (BIT_CLEAR_R_WMAC_MASK_LA_MAC_1_8814B(x) | \
+ BIT_R_WMAC_MASK_LA_MAC_1_8814B(v))
+
+/* 2 REG_IQ_DUMP_2_8814B */
+
+#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8814B 0
+#define BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8814B 0xffffffffL
+#define BIT_R_WMAC_MATCH_REF_MAC_2_8814B(x) \
+ (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8814B) \
+ << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8814B)
+#define BITS_R_WMAC_MATCH_REF_MAC_2_8814B \
+ (BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8814B \
+ << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8814B)
+#define BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2_8814B(x) \
+ ((x) & (~BITS_R_WMAC_MATCH_REF_MAC_2_8814B))
+#define BIT_GET_R_WMAC_MATCH_REF_MAC_2_8814B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8814B) & \
+ BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8814B)
+#define BIT_SET_R_WMAC_MATCH_REF_MAC_2_8814B(x, v) \
+ (BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2_8814B(x) | \
+ BIT_R_WMAC_MATCH_REF_MAC_2_8814B(v))
+
+/* 2 REG_WMAC_FTM_CTL_8814B */
+#define BIT_RXFTM_TXACK_SC_8814B BIT(6)
+#define BIT_RXFTM_TXACK_BW_8814B BIT(5)
+#define BIT_RXFTM_EN_8814B BIT(3)
+#define BIT_RXFTMREQ_BYDRV_8814B BIT(2)
+#define BIT_RXFTMREQ_EN_8814B BIT(1)
+#define BIT_FTM_EN_8814B BIT(0)
+
+/* 2 REG_WMAC_IQ_MDPK_FUNC_8814B */
+
+/* 2 REG_WMAC_OPTION_FUNCTION_8814B */
+
+#define BIT_SHIFT_R_OFDM_LEN_8814B 26
+#define BIT_MASK_R_OFDM_LEN_8814B 0x3f
+#define BIT_R_OFDM_LEN_8814B(x) \
+ (((x) & BIT_MASK_R_OFDM_LEN_8814B) << BIT_SHIFT_R_OFDM_LEN_8814B)
+#define BITS_R_OFDM_LEN_8814B \
+ (BIT_MASK_R_OFDM_LEN_8814B << BIT_SHIFT_R_OFDM_LEN_8814B)
+#define BIT_CLEAR_R_OFDM_LEN_8814B(x) ((x) & (~BITS_R_OFDM_LEN_8814B))
+#define BIT_GET_R_OFDM_LEN_8814B(x) \
+ (((x) >> BIT_SHIFT_R_OFDM_LEN_8814B) & BIT_MASK_R_OFDM_LEN_8814B)
+#define BIT_SET_R_OFDM_LEN_8814B(x, v) \
+ (BIT_CLEAR_R_OFDM_LEN_8814B(x) | BIT_R_OFDM_LEN_8814B(v))
+
+#define BIT_SHIFT_R_CCK_LEN_8814B 0
+#define BIT_MASK_R_CCK_LEN_8814B 0xffff
+#define BIT_R_CCK_LEN_8814B(x) \
+ (((x) & BIT_MASK_R_CCK_LEN_8814B) << BIT_SHIFT_R_CCK_LEN_8814B)
+#define BITS_R_CCK_LEN_8814B \
+ (BIT_MASK_R_CCK_LEN_8814B << BIT_SHIFT_R_CCK_LEN_8814B)
+#define BIT_CLEAR_R_CCK_LEN_8814B(x) ((x) & (~BITS_R_CCK_LEN_8814B))
+#define BIT_GET_R_CCK_LEN_8814B(x) \
+ (((x) >> BIT_SHIFT_R_CCK_LEN_8814B) & BIT_MASK_R_CCK_LEN_8814B)
+#define BIT_SET_R_CCK_LEN_8814B(x, v) \
+ (BIT_CLEAR_R_CCK_LEN_8814B(x) | BIT_R_CCK_LEN_8814B(v))
+
+/* 2 REG_WMAC_OPTION_FUNCTION_1_8814B */
+
+#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8814B 24
+#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8814B 0xff
+#define BIT_R_WMAC_RXFIFO_FULL_TH_1_8814B(x) \
+ (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8814B) \
+ << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8814B)
+#define BITS_R_WMAC_RXFIFO_FULL_TH_1_8814B \
+ (BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8814B \
+ << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8814B)
+#define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1_8814B(x) \
+ ((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH_1_8814B))
+#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_1_8814B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8814B) & \
+ BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8814B)
+#define BIT_SET_R_WMAC_RXFIFO_FULL_TH_1_8814B(x, v) \
+ (BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1_8814B(x) | \
+ BIT_R_WMAC_RXFIFO_FULL_TH_1_8814B(v))
+
+#define BIT_R_WMAC_RX_SYNCFIFO_SYNC_1_8814B BIT(23)
+#define BIT_R_WMAC_RXRST_DLY_1_8814B BIT(22)
+#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP_1_8814B BIT(21)
+#define BIT_R_WMAC_SRCH_TXRPT_UA1_1_8814B BIT(20)
+#define BIT_R_WMAC_SRCH_TXRPT_TYPE_1_8814B BIT(19)
+#define BIT_R_WMAC_NDP_RST_1_8814B BIT(18)
+#define BIT_R_WMAC_POWINT_EN_1_8814B BIT(17)
+#define BIT_R_WMAC_SRCH_TXRPT_PERPKT_1_8814B BIT(16)
+#define BIT_R_WMAC_SRCH_TXRPT_MID_1_8814B BIT(15)
+#define BIT_R_WMAC_PFIN_TOEN_1_8814B BIT(14)
+#define BIT_R_WMAC_FIL_SECERR_1_8814B BIT(13)
+#define BIT_R_WMAC_FIL_CTLPKTLEN_1_8814B BIT(12)
+#define BIT_R_WMAC_FIL_FCTYPE_1_8814B BIT(11)
+#define BIT_R_WMAC_FIL_FCPROVER_1_8814B BIT(10)
+#define BIT_R_WMAC_PHYSTS_SNIF_1_8814B BIT(9)
+#define BIT_R_WMAC_PHYSTS_PLCP_1_8814B BIT(8)
+#define BIT_R_MAC_TCR_VBONF_RD_1_8814B BIT(7)
+#define BIT_R_WMAC_TCR_MPAR_NDP_1_8814B BIT(6)
+#define BIT_R_WMAC_NDP_FILTER_1_8814B BIT(5)
+#define BIT_R_WMAC_RXLEN_SEL_1_8814B BIT(4)
+#define BIT_R_WMAC_RXLEN_SEL1_1_8814B BIT(3)
+#define BIT_R_OFDM_FILTER_1_8814B BIT(2)
+#define BIT_R_WMAC_CHK_OFDM_LEN_1_8814B BIT(1)
+#define BIT_R_WMAC_CHK_CCK_LEN_1_8814B BIT(0)
+
+/* 2 REG_WMAC_OPTION_FUNCTION_2_8814B */
+
+#define BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8814B 0
+#define BIT_MASK_R_WMAC_RX_FIL_LEN_2_8814B 0xffff
+#define BIT_R_WMAC_RX_FIL_LEN_2_8814B(x) \
+ (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_2_8814B) \
+ << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8814B)
+#define BITS_R_WMAC_RX_FIL_LEN_2_8814B \
+ (BIT_MASK_R_WMAC_RX_FIL_LEN_2_8814B \
+ << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8814B)
+#define BIT_CLEAR_R_WMAC_RX_FIL_LEN_2_8814B(x) \
+ ((x) & (~BITS_R_WMAC_RX_FIL_LEN_2_8814B))
+#define BIT_GET_R_WMAC_RX_FIL_LEN_2_8814B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8814B) & \
+ BIT_MASK_R_WMAC_RX_FIL_LEN_2_8814B)
+#define BIT_SET_R_WMAC_RX_FIL_LEN_2_8814B(x, v) \
+ (BIT_CLEAR_R_WMAC_RX_FIL_LEN_2_8814B(x) | \
+ BIT_R_WMAC_RX_FIL_LEN_2_8814B(v))
+
+/* 2 REG_RX_FILTER_FUNCTION_8814B */
+#define BIT_R_WMAC_MHRDDY_LATCH_8814B BIT(14)
+#define BIT_R_WMAC_MHRDDY_CLR_8814B BIT(13)
+#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY1_8814B BIT(12)
+#define BIT_WMAC_DIS_VHT_PLCP_CHK_MU_8814B BIT(11)
+#define BIT_R_CHK_DELIMIT_LEN_8814B BIT(10)
+#define BIT_R_REAPTER_ADDR_MATCH_8814B BIT(9)
+#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY_8814B BIT(8)
+#define BIT_R_LATCH_MACHRDY_8814B BIT(7)
+#define BIT_R_WMAC_RXFIL_REND_8814B BIT(6)
+#define BIT_R_WMAC_MPDURDY_CLR_8814B BIT(5)
+#define BIT_R_WMAC_CLRRXSEC_8814B BIT(4)
+#define BIT_R_WMAC_RXFIL_RDEL_8814B BIT(3)
+#define BIT_R_WMAC_RXFIL_FCSE_8814B BIT(2)
+#define BIT_R_WMAC_RXFIL_MESH_DEL_8814B BIT(1)
+#define BIT_R_WMAC_RXFIL_MASKM_8814B BIT(0)
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NDP_SIG_8814B */
+
+#define BIT_SHIFT_R_WMAC_TXNDP_SIGB_8814B 0
+#define BIT_MASK_R_WMAC_TXNDP_SIGB_8814B 0x1fffff
+#define BIT_R_WMAC_TXNDP_SIGB_8814B(x) \
+ (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB_8814B) \
+ << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8814B)
+#define BITS_R_WMAC_TXNDP_SIGB_8814B \
+ (BIT_MASK_R_WMAC_TXNDP_SIGB_8814B << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8814B)
+#define BIT_CLEAR_R_WMAC_TXNDP_SIGB_8814B(x) \
+ ((x) & (~BITS_R_WMAC_TXNDP_SIGB_8814B))
+#define BIT_GET_R_WMAC_TXNDP_SIGB_8814B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8814B) & \
+ BIT_MASK_R_WMAC_TXNDP_SIGB_8814B)
+#define BIT_SET_R_WMAC_TXNDP_SIGB_8814B(x, v) \
+ (BIT_CLEAR_R_WMAC_TXNDP_SIGB_8814B(x) | BIT_R_WMAC_TXNDP_SIGB_8814B(v))
+
+/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_8814B */
+
+#define BIT_SHIFT_R_MAC_DBG_SHIFT_8814B 8
+#define BIT_MASK_R_MAC_DBG_SHIFT_8814B 0x7
+#define BIT_R_MAC_DBG_SHIFT_8814B(x) \
+ (((x) & BIT_MASK_R_MAC_DBG_SHIFT_8814B) \
+ << BIT_SHIFT_R_MAC_DBG_SHIFT_8814B)
+#define BITS_R_MAC_DBG_SHIFT_8814B \
+ (BIT_MASK_R_MAC_DBG_SHIFT_8814B << BIT_SHIFT_R_MAC_DBG_SHIFT_8814B)
+#define BIT_CLEAR_R_MAC_DBG_SHIFT_8814B(x) ((x) & (~BITS_R_MAC_DBG_SHIFT_8814B))
+#define BIT_GET_R_MAC_DBG_SHIFT_8814B(x) \
+ (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8814B) & \
+ BIT_MASK_R_MAC_DBG_SHIFT_8814B)
+#define BIT_SET_R_MAC_DBG_SHIFT_8814B(x, v) \
+ (BIT_CLEAR_R_MAC_DBG_SHIFT_8814B(x) | BIT_R_MAC_DBG_SHIFT_8814B(v))
+
+#define BIT_SHIFT_R_MAC_DBG_SEL_8814B 0
+#define BIT_MASK_R_MAC_DBG_SEL_8814B 0x3
+#define BIT_R_MAC_DBG_SEL_8814B(x) \
+ (((x) & BIT_MASK_R_MAC_DBG_SEL_8814B) << BIT_SHIFT_R_MAC_DBG_SEL_8814B)
+#define BITS_R_MAC_DBG_SEL_8814B \
+ (BIT_MASK_R_MAC_DBG_SEL_8814B << BIT_SHIFT_R_MAC_DBG_SEL_8814B)
+#define BIT_CLEAR_R_MAC_DBG_SEL_8814B(x) ((x) & (~BITS_R_MAC_DBG_SEL_8814B))
+#define BIT_GET_R_MAC_DBG_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8814B) & BIT_MASK_R_MAC_DBG_SEL_8814B)
+#define BIT_SET_R_MAC_DBG_SEL_8814B(x, v) \
+ (BIT_CLEAR_R_MAC_DBG_SEL_8814B(x) | BIT_R_MAC_DBG_SEL_8814B(v))
+
+/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_1_8814B */
+
+#define BIT_SHIFT_R_MAC_DEBUG_1_8814B 0
+#define BIT_MASK_R_MAC_DEBUG_1_8814B 0xffffffffL
+#define BIT_R_MAC_DEBUG_1_8814B(x) \
+ (((x) & BIT_MASK_R_MAC_DEBUG_1_8814B) << BIT_SHIFT_R_MAC_DEBUG_1_8814B)
+#define BITS_R_MAC_DEBUG_1_8814B \
+ (BIT_MASK_R_MAC_DEBUG_1_8814B << BIT_SHIFT_R_MAC_DEBUG_1_8814B)
+#define BIT_CLEAR_R_MAC_DEBUG_1_8814B(x) ((x) & (~BITS_R_MAC_DEBUG_1_8814B))
+#define BIT_GET_R_MAC_DEBUG_1_8814B(x) \
+ (((x) >> BIT_SHIFT_R_MAC_DEBUG_1_8814B) & BIT_MASK_R_MAC_DEBUG_1_8814B)
+#define BIT_SET_R_MAC_DEBUG_1_8814B(x, v) \
+ (BIT_CLEAR_R_MAC_DEBUG_1_8814B(x) | BIT_R_MAC_DEBUG_1_8814B(v))
+
+/* 2 REG_WSEC_OPTION_8814B */
+#define BIT_RXDEC_BM_MGNT_8814B BIT(22)
+#define BIT_TXENC_BM_MGNT_8814B BIT(21)
+#define BIT_RXDEC_UNI_MGNT_8814B BIT(20)
+#define BIT_TXENC_UNI_MGNT_8814B BIT(19)
+
+/* 2 REG_RTS_ADDRESS_0_8814B */
+
+/* 2 REG_RTS_ADDRESS_0_1_8814B */
+
+/* 2 REG_RTS_ADDRESS_1_8814B */
+
+/* 2 REG_RTS_ADDRESS_1_1_8814B */
+
+/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8814B */
+#define BIT_LTECOEX_ACCESS_START_V1_8814B BIT(31)
+#define BIT_LTECOEX_WRITE_MODE_V1_8814B BIT(30)
+#define BIT_LTECOEX_READY_BIT_V1_8814B BIT(29)
+
+#define BIT_SHIFT_WRITE_BYTE_EN_V1_8814B 16
+#define BIT_MASK_WRITE_BYTE_EN_V1_8814B 0xf
+#define BIT_WRITE_BYTE_EN_V1_8814B(x) \
+ (((x) & BIT_MASK_WRITE_BYTE_EN_V1_8814B) \
+ << BIT_SHIFT_WRITE_BYTE_EN_V1_8814B)
+#define BITS_WRITE_BYTE_EN_V1_8814B \
+ (BIT_MASK_WRITE_BYTE_EN_V1_8814B << BIT_SHIFT_WRITE_BYTE_EN_V1_8814B)
+#define BIT_CLEAR_WRITE_BYTE_EN_V1_8814B(x) \
+ ((x) & (~BITS_WRITE_BYTE_EN_V1_8814B))
+#define BIT_GET_WRITE_BYTE_EN_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1_8814B) & \
+ BIT_MASK_WRITE_BYTE_EN_V1_8814B)
+#define BIT_SET_WRITE_BYTE_EN_V1_8814B(x, v) \
+ (BIT_CLEAR_WRITE_BYTE_EN_V1_8814B(x) | BIT_WRITE_BYTE_EN_V1_8814B(v))
+
+#define BIT_SHIFT_LTECOEX_REG_ADDR_V1_8814B 0
+#define BIT_MASK_LTECOEX_REG_ADDR_V1_8814B 0xffff
+#define BIT_LTECOEX_REG_ADDR_V1_8814B(x) \
+ (((x) & BIT_MASK_LTECOEX_REG_ADDR_V1_8814B) \
+ << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8814B)
+#define BITS_LTECOEX_REG_ADDR_V1_8814B \
+ (BIT_MASK_LTECOEX_REG_ADDR_V1_8814B \
+ << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8814B)
+#define BIT_CLEAR_LTECOEX_REG_ADDR_V1_8814B(x) \
+ ((x) & (~BITS_LTECOEX_REG_ADDR_V1_8814B))
+#define BIT_GET_LTECOEX_REG_ADDR_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1_8814B) & \
+ BIT_MASK_LTECOEX_REG_ADDR_V1_8814B)
+#define BIT_SET_LTECOEX_REG_ADDR_V1_8814B(x, v) \
+ (BIT_CLEAR_LTECOEX_REG_ADDR_V1_8814B(x) | \
+ BIT_LTECOEX_REG_ADDR_V1_8814B(v))
+
+/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8814B */
+
+#define BIT_SHIFT_LTECOEX_W_DATA_V1_8814B 0
+#define BIT_MASK_LTECOEX_W_DATA_V1_8814B 0xffffffffL
+#define BIT_LTECOEX_W_DATA_V1_8814B(x) \
+ (((x) & BIT_MASK_LTECOEX_W_DATA_V1_8814B) \
+ << BIT_SHIFT_LTECOEX_W_DATA_V1_8814B)
+#define BITS_LTECOEX_W_DATA_V1_8814B \
+ (BIT_MASK_LTECOEX_W_DATA_V1_8814B << BIT_SHIFT_LTECOEX_W_DATA_V1_8814B)
+#define BIT_CLEAR_LTECOEX_W_DATA_V1_8814B(x) \
+ ((x) & (~BITS_LTECOEX_W_DATA_V1_8814B))
+#define BIT_GET_LTECOEX_W_DATA_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1_8814B) & \
+ BIT_MASK_LTECOEX_W_DATA_V1_8814B)
+#define BIT_SET_LTECOEX_W_DATA_V1_8814B(x, v) \
+ (BIT_CLEAR_LTECOEX_W_DATA_V1_8814B(x) | BIT_LTECOEX_W_DATA_V1_8814B(v))
+
+/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8814B */
+
+#define BIT_SHIFT_LTECOEX_R_DATA_V1_8814B 0
+#define BIT_MASK_LTECOEX_R_DATA_V1_8814B 0xffffffffL
+#define BIT_LTECOEX_R_DATA_V1_8814B(x) \
+ (((x) & BIT_MASK_LTECOEX_R_DATA_V1_8814B) \
+ << BIT_SHIFT_LTECOEX_R_DATA_V1_8814B)
+#define BITS_LTECOEX_R_DATA_V1_8814B \
+ (BIT_MASK_LTECOEX_R_DATA_V1_8814B << BIT_SHIFT_LTECOEX_R_DATA_V1_8814B)
+#define BIT_CLEAR_LTECOEX_R_DATA_V1_8814B(x) \
+ ((x) & (~BITS_LTECOEX_R_DATA_V1_8814B))
+#define BIT_GET_LTECOEX_R_DATA_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1_8814B) & \
+ BIT_MASK_LTECOEX_R_DATA_V1_8814B)
+#define BIT_SET_LTECOEX_R_DATA_V1_8814B(x, v) \
+ (BIT_CLEAR_LTECOEX_R_DATA_V1_8814B(x) | BIT_LTECOEX_R_DATA_V1_8814B(v))
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_NOT_VALID_8814B */
+
+/* 2 REG_PCIE_CFG_FORCE_LINK_L_8814B */
+#define BIT_PCIE_CFG_FORCE_EN_8814B BIT(7)
+
+/* 2 REG_PCIE_CFG_FORCE_LINK_H_8814B */
+#define BIT_PCIE_CFG_TRXACT_DIS_IDLE_TIMER_8814B BIT(6)
+
+#define BIT_SHIFT_PCIE_CFG_LINK_STATE_8814B 0
+#define BIT_MASK_PCIE_CFG_LINK_STATE_8814B 0x3f
+#define BIT_PCIE_CFG_LINK_STATE_8814B(x) \
+ (((x) & BIT_MASK_PCIE_CFG_LINK_STATE_8814B) \
+ << BIT_SHIFT_PCIE_CFG_LINK_STATE_8814B)
+#define BITS_PCIE_CFG_LINK_STATE_8814B \
+ (BIT_MASK_PCIE_CFG_LINK_STATE_8814B \
+ << BIT_SHIFT_PCIE_CFG_LINK_STATE_8814B)
+#define BIT_CLEAR_PCIE_CFG_LINK_STATE_8814B(x) \
+ ((x) & (~BITS_PCIE_CFG_LINK_STATE_8814B))
+#define BIT_GET_PCIE_CFG_LINK_STATE_8814B(x) \
+ (((x) >> BIT_SHIFT_PCIE_CFG_LINK_STATE_8814B) & \
+ BIT_MASK_PCIE_CFG_LINK_STATE_8814B)
+#define BIT_SET_PCIE_CFG_LINK_STATE_8814B(x, v) \
+ (BIT_CLEAR_PCIE_CFG_LINK_STATE_8814B(x) | \
+ BIT_PCIE_CFG_LINK_STATE_8814B(v))
+
+/* 2 REG_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B */
+
+#define BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B 0
+#define BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B 0xff
+#define BIT_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B(x) \
+ (((x) & BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B) \
+ << BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B)
+#define BITS_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B \
+ (BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B \
+ << BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B)
+#define BIT_CLEAR_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B(x) \
+ ((x) & (~BITS_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B))
+#define BIT_GET_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B(x) \
+ (((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B) & \
+ BIT_MASK_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B)
+#define BIT_SET_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B(x, v) \
+ (BIT_CLEAR_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B(x) | \
+ BIT_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B(v))
+
+/* 2 REG_PCIE_CFG_CX_NFTS_8814B */
+
+#define BIT_SHIFT_PCIE_CFG_CX_NFTS_8814B 0
+#define BIT_MASK_PCIE_CFG_CX_NFTS_8814B 0xff
+#define BIT_PCIE_CFG_CX_NFTS_8814B(x) \
+ (((x) & BIT_MASK_PCIE_CFG_CX_NFTS_8814B) \
+ << BIT_SHIFT_PCIE_CFG_CX_NFTS_8814B)
+#define BITS_PCIE_CFG_CX_NFTS_8814B \
+ (BIT_MASK_PCIE_CFG_CX_NFTS_8814B << BIT_SHIFT_PCIE_CFG_CX_NFTS_8814B)
+#define BIT_CLEAR_PCIE_CFG_CX_NFTS_8814B(x) \
+ ((x) & (~BITS_PCIE_CFG_CX_NFTS_8814B))
+#define BIT_GET_PCIE_CFG_CX_NFTS_8814B(x) \
+ (((x) >> BIT_SHIFT_PCIE_CFG_CX_NFTS_8814B) & \
+ BIT_MASK_PCIE_CFG_CX_NFTS_8814B)
+#define BIT_SET_PCIE_CFG_CX_NFTS_8814B(x, v) \
+ (BIT_CLEAR_PCIE_CFG_CX_NFTS_8814B(x) | BIT_PCIE_CFG_CX_NFTS_8814B(v))
+
+/* 2 REG_PCIE_CFG_DEFAULT_ENTR_LATENCY_8814B */
+#define BIT_PCIE_CFG_REAL_EN_L0S_8814B BIT(7)
+#define BIT_PCIE_CFG_ENTER_ASPM_8814B BIT(6)
+
+#define BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B 3
+#define BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B 0x7
+#define BIT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B(x) \
+ (((x) & BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B) \
+ << BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B)
+#define BITS_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B \
+ (BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B \
+ << BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B)
+#define BIT_CLEAR_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B(x) \
+ ((x) & (~BITS_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B))
+#define BIT_GET_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B(x) \
+ (((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B) & \
+ BIT_MASK_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B)
+#define BIT_SET_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B(x, v) \
+ (BIT_CLEAR_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B(x) | \
+ BIT_PCIE_CFG_DEFAULT_L1_ENTR_LATENCY_8814B(v))
+
+#define BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B 0
+#define BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B 0x7
+#define BIT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B(x) \
+ (((x) & BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B) \
+ << BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B)
+#define BITS_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B \
+ (BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B \
+ << BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B)
+#define BIT_CLEAR_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B(x) \
+ ((x) & (~BITS_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B))
+#define BIT_GET_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B(x) \
+ (((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B) & \
+ BIT_MASK_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B)
+#define BIT_SET_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B(x, v) \
+ (BIT_CLEAR_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B(x) | \
+ BIT_PCIE_CFG_DEFAULT_L0S_ENTR_LATENCY_8814B(v))
+
+/* 2 REG_PCIE_CFG_L1_MISC_SEL_8814B */
+#define BIT_PCIE_CFG_L1_RIDLE_SEL_8814B BIT(6)
+#define BIT_PCIE_CFG_L1_TIMEOUT_SEL_8814B BIT(5)
+#define BIT_PCIE_CFG_L1_EIDLE_SEL_8814B BIT(4)
+
+#define BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE_8814B 0
+#define BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE_8814B 0xf
+#define BIT_PCIE_CFG_DEFAULT_LINK_RATE_8814B(x) \
+ (((x) & BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE_8814B) \
+ << BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE_8814B)
+#define BITS_PCIE_CFG_DEFAULT_LINK_RATE_8814B \
+ (BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE_8814B \
+ << BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE_8814B)
+#define BIT_CLEAR_PCIE_CFG_DEFAULT_LINK_RATE_8814B(x) \
+ ((x) & (~BITS_PCIE_CFG_DEFAULT_LINK_RATE_8814B))
+#define BIT_GET_PCIE_CFG_DEFAULT_LINK_RATE_8814B(x) \
+ (((x) >> BIT_SHIFT_PCIE_CFG_DEFAULT_LINK_RATE_8814B) & \
+ BIT_MASK_PCIE_CFG_DEFAULT_LINK_RATE_8814B)
+#define BIT_SET_PCIE_CFG_DEFAULT_LINK_RATE_8814B(x, v) \
+ (BIT_CLEAR_PCIE_CFG_DEFAULT_LINK_RATE_8814B(x) | \
+ BIT_PCIE_CFG_DEFAULT_LINK_RATE_8814B(v))
+
+/* 2 REG_PCIE_CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF_8814B */
+#define BIT_PCIE_CFG_REAL_PTM_ENABLE_8814B BIT(6)
+#define BIT_PCIE_CFG_REAL_EN_L1SUB_8814B BIT(5)
+
+#define BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM_8814B 0
+#define BIT_MASK_PCIE_CFG_MAX_FUNC_NUM_8814B 0x7
+#define BIT_PCIE_CFG_MAX_FUNC_NUM_8814B(x) \
+ (((x) & BIT_MASK_PCIE_CFG_MAX_FUNC_NUM_8814B) \
+ << BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM_8814B)
+#define BITS_PCIE_CFG_MAX_FUNC_NUM_8814B \
+ (BIT_MASK_PCIE_CFG_MAX_FUNC_NUM_8814B \
+ << BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM_8814B)
+#define BIT_CLEAR_PCIE_CFG_MAX_FUNC_NUM_8814B(x) \
+ ((x) & (~BITS_PCIE_CFG_MAX_FUNC_NUM_8814B))
+#define BIT_GET_PCIE_CFG_MAX_FUNC_NUM_8814B(x) \
+ (((x) >> BIT_SHIFT_PCIE_CFG_MAX_FUNC_NUM_8814B) & \
+ BIT_MASK_PCIE_CFG_MAX_FUNC_NUM_8814B)
+#define BIT_SET_PCIE_CFG_MAX_FUNC_NUM_8814B(x, v) \
+ (BIT_CLEAR_PCIE_CFG_MAX_FUNC_NUM_8814B(x) | \
+ BIT_PCIE_CFG_MAX_FUNC_NUM_8814B(v))
+
+/* 2 REG_PCIE_CFG_FORCE_CLKREQ_N_PAD_8814B */
+#define BIT_PCIE_CFG_REAL_EN_64BITS_8814B BIT(5)
+#define BIT_PCIE_CFG_REAL_EN_CLKREQ_8814B BIT(4)
+#define BIT_PCIE_CFG_REAL_EN_L1_8814B BIT(3)
+#define BIT_PCIE_CFG_WAKE_N_EN_8814B BIT(2)
+#define BIT_PCIE_CFG_BYPASS_LTR_OPTION_8814B BIT(1)
+#define BIT_PCIE_CFG_FORCE_CLKREQ_N_PAD_8814B BIT(0)
+
+/* 2 REG_PCIE_CFG_TIMER_MODIFIER_FOR_ACK_NAK_LATENCY_8814B */
+
+#define BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B 0
+#define BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B 0xff
+#define BIT_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B(x) \
+ (((x) & BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B) \
+ << BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B)
+#define BITS_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B \
+ (BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B \
+ << BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B)
+#define BIT_CLEAR_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B(x) \
+ ((x) & (~BITS_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B))
+#define BIT_GET_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B(x) \
+ (((x) >> BIT_SHIFT_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B) & \
+ BIT_MASK_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B)
+#define BIT_SET_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B(x, v) \
+ (BIT_CLEAR_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B(x) | \
+ BIT_PCIE_CFG_TIMER_MOD_ACK_NAK_8814B(v))
+
+/* 2 REG_PCIE_CFG_TIMER_MODIFIER_FOR_FLOW_CONTROL_WATCHDOG_8814B */
+#define BIT_PCIE_CFG_BYPASS_L1_SUBSTATE_OPTION_8814B BIT(7)
+
+#define BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B 5
+#define BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B 0x3
+#define BIT_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B(x) \
+ (((x) & BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B) \
+ << BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B)
+#define BITS_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B \
+ (BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B \
+ << BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B)
+#define BIT_CLEAR_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B(x) \
+ ((x) & (~BITS_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B))
+#define BIT_GET_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B(x) \
+ (((x) >> BIT_SHIFT_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B) & \
+ BIT_MASK_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B)
+#define BIT_SET_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B(x, v) \
+ (BIT_CLEAR_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B(x) | \
+ BIT_PCIE_CFG_FAST_LINK_SCALING_FACTOR_8814B(v))
+
+#define BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER_8814B 0
+#define BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER_8814B 0x1f
+#define BIT_PCIE_CFG_UPDATE_FREQ_TIMER_8814B(x) \
+ (((x) & BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER_8814B) \
+ << BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER_8814B)
+#define BITS_PCIE_CFG_UPDATE_FREQ_TIMER_8814B \
+ (BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER_8814B \
+ << BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER_8814B)
+#define BIT_CLEAR_PCIE_CFG_UPDATE_FREQ_TIMER_8814B(x) \
+ ((x) & (~BITS_PCIE_CFG_UPDATE_FREQ_TIMER_8814B))
+#define BIT_GET_PCIE_CFG_UPDATE_FREQ_TIMER_8814B(x) \
+ (((x) >> BIT_SHIFT_PCIE_CFG_UPDATE_FREQ_TIMER_8814B) & \
+ BIT_MASK_PCIE_CFG_UPDATE_FREQ_TIMER_8814B)
+#define BIT_SET_PCIE_CFG_UPDATE_FREQ_TIMER_8814B(x, v) \
+ (BIT_CLEAR_PCIE_CFG_UPDATE_FREQ_TIMER_8814B(x) | \
+ BIT_PCIE_CFG_UPDATE_FREQ_TIMER_8814B(v))
+
+/* 2 REG_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B */
+
+#define BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B 0
+#define BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B 0xff
+#define BIT_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B(x) \
+ (((x) & BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B) \
+ << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B)
+#define BITS_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B \
+ (BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B \
+ << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B)
+#define BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B(x) \
+ ((x) & (~BITS_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B))
+#define BIT_GET_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B(x) \
+ (((x) >> BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B) & \
+ BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B)
+#define BIT_SET_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B(x, v) \
+ (BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B(x) | \
+ BIT_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B(v))
+
+/* 2 REG_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B */
+#define BIT_PCIE_CFG_DISABLE_FC_WATCHDOG_TIMER_8814B BIT(7)
+
+#define BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B 0
+#define BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B 0x7
+#define BIT_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B(x) \
+ (((x) & BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B) \
+ << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B)
+#define BITS_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B \
+ (BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B \
+ << BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B)
+#define BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B(x) \
+ ((x) & (~BITS_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B))
+#define BIT_GET_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B(x) \
+ (((x) >> BIT_SHIFT_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B) & \
+ BIT_MASK_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B)
+#define BIT_SET_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B(x, v) \
+ (BIT_CLEAR_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B(x) | \
+ BIT_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B(v))
+
+/* 2 REG_PCIE_CFG_L1_UNIT_SEL_8814B */
+
+#define BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL_8814B 0
+#define BIT_MASK_PCIE_CFG_L1_UNIT_SEL_8814B 0xff
+#define BIT_PCIE_CFG_L1_UNIT_SEL_8814B(x) \
+ (((x) & BIT_MASK_PCIE_CFG_L1_UNIT_SEL_8814B) \
+ << BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL_8814B)
+#define BITS_PCIE_CFG_L1_UNIT_SEL_8814B \
+ (BIT_MASK_PCIE_CFG_L1_UNIT_SEL_8814B \
+ << BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL_8814B)
+#define BIT_CLEAR_PCIE_CFG_L1_UNIT_SEL_8814B(x) \
+ ((x) & (~BITS_PCIE_CFG_L1_UNIT_SEL_8814B))
+#define BIT_GET_PCIE_CFG_L1_UNIT_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_PCIE_CFG_L1_UNIT_SEL_8814B) & \
+ BIT_MASK_PCIE_CFG_L1_UNIT_SEL_8814B)
+#define BIT_SET_PCIE_CFG_L1_UNIT_SEL_8814B(x, v) \
+ (BIT_CLEAR_PCIE_CFG_L1_UNIT_SEL_8814B(x) | \
+ BIT_PCIE_CFG_L1_UNIT_SEL_8814B(v))
+
+/* 2 REG_PCIE_CFG_MIN_CLKREQ_SEL_8814B */
+
+#define BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL_8814B 0
+#define BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL_8814B 0xf
+#define BIT_PCIE_CFG_MIN_CLKREQ_SEL_8814B(x) \
+ (((x) & BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL_8814B) \
+ << BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL_8814B)
+#define BITS_PCIE_CFG_MIN_CLKREQ_SEL_8814B \
+ (BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL_8814B \
+ << BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL_8814B)
+#define BIT_CLEAR_PCIE_CFG_MIN_CLKREQ_SEL_8814B(x) \
+ ((x) & (~BITS_PCIE_CFG_MIN_CLKREQ_SEL_8814B))
+#define BIT_GET_PCIE_CFG_MIN_CLKREQ_SEL_8814B(x) \
+ (((x) >> BIT_SHIFT_PCIE_CFG_MIN_CLKREQ_SEL_8814B) & \
+ BIT_MASK_PCIE_CFG_MIN_CLKREQ_SEL_8814B)
+#define BIT_SET_PCIE_CFG_MIN_CLKREQ_SEL_8814B(x, v) \
+ (BIT_CLEAR_PCIE_CFG_MIN_CLKREQ_SEL_8814B(x) | \
+ BIT_PCIE_CFG_MIN_CLKREQ_SEL_8814B(v))
+
+/* 2 REG_SDIO_TX_CTRL_8814B */
+
+#define BIT_SHIFT_SDIO_INT_TIMEOUT_8814B 16
+#define BIT_MASK_SDIO_INT_TIMEOUT_8814B 0xffff
+#define BIT_SDIO_INT_TIMEOUT_8814B(x) \
+ (((x) & BIT_MASK_SDIO_INT_TIMEOUT_8814B) \
+ << BIT_SHIFT_SDIO_INT_TIMEOUT_8814B)
+#define BITS_SDIO_INT_TIMEOUT_8814B \
+ (BIT_MASK_SDIO_INT_TIMEOUT_8814B << BIT_SHIFT_SDIO_INT_TIMEOUT_8814B)
+#define BIT_CLEAR_SDIO_INT_TIMEOUT_8814B(x) \
+ ((x) & (~BITS_SDIO_INT_TIMEOUT_8814B))
+#define BIT_GET_SDIO_INT_TIMEOUT_8814B(x) \
+ (((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT_8814B) & \
+ BIT_MASK_SDIO_INT_TIMEOUT_8814B)
+#define BIT_SET_SDIO_INT_TIMEOUT_8814B(x, v) \
+ (BIT_CLEAR_SDIO_INT_TIMEOUT_8814B(x) | BIT_SDIO_INT_TIMEOUT_8814B(v))
+
+#define BIT_IO_ERR_STATUS_8814B BIT(15)
+#define BIT_REPLY_ERRCRC_IN_DATA_8814B BIT(9)
+#define BIT_EN_CMD53_OVERLAP_8814B BIT(8)
+#define BIT_REPLY_ERR_IN_R5_8814B BIT(7)
+#define BIT_R18A_EN_8814B BIT(6)
+#define BIT_SDIO_CMD_FORCE_VLD_8814B BIT(5)
+#define BIT_INIT_CMD_EN_8814B BIT(4)
+#define BIT_EN_RXDMA_MASK_INT_8814B BIT(2)
+#define BIT_EN_MASK_TIMER_8814B BIT(1)
+#define BIT_CMD_ERR_STOP_INT_EN_8814B BIT(0)
+
+/* 2 REG_SDIO_HIMR_8814B */
+#define BIT_SDIO_CRCERR_MSK_8814B BIT(31)
+#define BIT_SDIO_HSISR3_IND_MSK_8814B BIT(30)
+#define BIT_SDIO_HSISR2_IND_MSK_8814B BIT(29)
+#define BIT_SDIO_HEISR_IND_MSK_8814B BIT(28)
+#define BIT_SDIO_CTWEND_MSK_8814B BIT(27)
+#define BIT_SDIO_ATIMEND_E_MSK_8814B BIT(26)
+#define BIT_SDIIO_ATIMEND_MSK_8814B BIT(25)
+#define BIT_SDIO_OCPINT_MSK_8814B BIT(24)
+#define BIT_SDIO_PSTIMEOUT_MSK_8814B BIT(23)
+#define BIT_SDIO_GTINT4_MSK_8814B BIT(22)
+#define BIT_SDIO_GTINT3_MSK_8814B BIT(21)
+#define BIT_SDIO_HSISR_IND_MSK_8814B BIT(20)
+#define BIT_SDIO_CPWM2_MSK_8814B BIT(19)
+#define BIT_SDIO_CPWM1_MSK_8814B BIT(18)
+#define BIT_SDIO_C2HCMD_INT_MSK_8814B BIT(17)
+#define BIT_SDIO_BCNERLY_INT_MSK_8814B BIT(16)
+#define BIT_SDIO_TXBCNERR_MSK_8814B BIT(7)
+#define BIT_SDIO_TXBCNOK_MSK_8814B BIT(6)
+#define BIT_SDIO_RXFOVW_MSK_8814B BIT(5)
+#define BIT_SDIO_TXFOVW_MSK_8814B BIT(4)
+#define BIT_SDIO_RXERR_MSK_8814B BIT(3)
+#define BIT_SDIO_TXERR_MSK_8814B BIT(2)
+#define BIT_SDIO_AVAL_MSK_8814B BIT(1)
+#define BIT_RX_REQUEST_MSK_8814B BIT(0)
+
+/* 2 REG_SDIO_HISR_8814B */
+#define BIT_SDIO_CRCERR_8814B BIT(31)
+#define BIT_SDIO_HSISR3_IND_8814B BIT(30)
+#define BIT_SDIO_HSISR2_IND_8814B BIT(29)
+#define BIT_SDIO_HEISR_IND_8814B BIT(28)
+#define BIT_SDIO_CTWEND_8814B BIT(27)
+#define BIT_SDIO_ATIMEND_E_8814B BIT(26)
+#define BIT_SDIO_ATIMEND_8814B BIT(25)
+#define BIT_SDIO_OCPINT_8814B BIT(24)
+#define BIT_SDIO_PSTIMEOUT_8814B BIT(23)
+#define BIT_SDIO_GTINT4_8814B BIT(22)
+#define BIT_SDIO_GTINT3_8814B BIT(21)
+#define BIT_SDIO_HSISR_IND_8814B BIT(20)
+#define BIT_SDIO_CPWM2_8814B BIT(19)
+#define BIT_SDIO_CPWM1_8814B BIT(18)
+#define BIT_SDIO_C2HCMD_INT_8814B BIT(17)
+#define BIT_SDIO_BCNERLY_INT_8814B BIT(16)
+#define BIT_SDIO_TXBCNERR_8814B BIT(7)
+#define BIT_SDIO_TXBCNOK_8814B BIT(6)
+#define BIT_SDIO_RXFOVW_8814B BIT(5)
+#define BIT_SDIO_TXFOVW_8814B BIT(4)
+#define BIT_SDIO_RXERR_8814B BIT(3)
+#define BIT_SDIO_TXERR_8814B BIT(2)
+#define BIT_SDIO_AVAL_8814B BIT(1)
+#define BIT_RX_REQUEST_8814B BIT(0)
+
+/* 2 REG_SDIO_RX_REQ_LEN_8814B */
+
+#define BIT_SHIFT_RX_REQ_LEN_V1_8814B 0
+#define BIT_MASK_RX_REQ_LEN_V1_8814B 0x3ffff
+#define BIT_RX_REQ_LEN_V1_8814B(x) \
+ (((x) & BIT_MASK_RX_REQ_LEN_V1_8814B) << BIT_SHIFT_RX_REQ_LEN_V1_8814B)
+#define BITS_RX_REQ_LEN_V1_8814B \
+ (BIT_MASK_RX_REQ_LEN_V1_8814B << BIT_SHIFT_RX_REQ_LEN_V1_8814B)
+#define BIT_CLEAR_RX_REQ_LEN_V1_8814B(x) ((x) & (~BITS_RX_REQ_LEN_V1_8814B))
+#define BIT_GET_RX_REQ_LEN_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_RX_REQ_LEN_V1_8814B) & BIT_MASK_RX_REQ_LEN_V1_8814B)
+#define BIT_SET_RX_REQ_LEN_V1_8814B(x, v) \
+ (BIT_CLEAR_RX_REQ_LEN_V1_8814B(x) | BIT_RX_REQ_LEN_V1_8814B(v))
+
+/* 2 REG_SDIO_FREE_TXPG_SEQ_V1_8814B */
+
+#define BIT_SHIFT_FREE_TXPG_SEQ_8814B 0
+#define BIT_MASK_FREE_TXPG_SEQ_8814B 0xff
+#define BIT_FREE_TXPG_SEQ_8814B(x) \
+ (((x) & BIT_MASK_FREE_TXPG_SEQ_8814B) << BIT_SHIFT_FREE_TXPG_SEQ_8814B)
+#define BITS_FREE_TXPG_SEQ_8814B \
+ (BIT_MASK_FREE_TXPG_SEQ_8814B << BIT_SHIFT_FREE_TXPG_SEQ_8814B)
+#define BIT_CLEAR_FREE_TXPG_SEQ_8814B(x) ((x) & (~BITS_FREE_TXPG_SEQ_8814B))
+#define BIT_GET_FREE_TXPG_SEQ_8814B(x) \
+ (((x) >> BIT_SHIFT_FREE_TXPG_SEQ_8814B) & BIT_MASK_FREE_TXPG_SEQ_8814B)
+#define BIT_SET_FREE_TXPG_SEQ_8814B(x, v) \
+ (BIT_CLEAR_FREE_TXPG_SEQ_8814B(x) | BIT_FREE_TXPG_SEQ_8814B(v))
+
+/* 2 REG_SDIO_FREE_TXPG_8814B */
+
+#define BIT_SHIFT_MID_FREEPG_V1_8814B 16
+#define BIT_MASK_MID_FREEPG_V1_8814B 0xfff
+#define BIT_MID_FREEPG_V1_8814B(x) \
+ (((x) & BIT_MASK_MID_FREEPG_V1_8814B) << BIT_SHIFT_MID_FREEPG_V1_8814B)
+#define BITS_MID_FREEPG_V1_8814B \
+ (BIT_MASK_MID_FREEPG_V1_8814B << BIT_SHIFT_MID_FREEPG_V1_8814B)
+#define BIT_CLEAR_MID_FREEPG_V1_8814B(x) ((x) & (~BITS_MID_FREEPG_V1_8814B))
+#define BIT_GET_MID_FREEPG_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_MID_FREEPG_V1_8814B) & BIT_MASK_MID_FREEPG_V1_8814B)
+#define BIT_SET_MID_FREEPG_V1_8814B(x, v) \
+ (BIT_CLEAR_MID_FREEPG_V1_8814B(x) | BIT_MID_FREEPG_V1_8814B(v))
+
+#define BIT_SHIFT_HIQ_FREEPG_V1_8814B 0
+#define BIT_MASK_HIQ_FREEPG_V1_8814B 0xfff
+#define BIT_HIQ_FREEPG_V1_8814B(x) \
+ (((x) & BIT_MASK_HIQ_FREEPG_V1_8814B) << BIT_SHIFT_HIQ_FREEPG_V1_8814B)
+#define BITS_HIQ_FREEPG_V1_8814B \
+ (BIT_MASK_HIQ_FREEPG_V1_8814B << BIT_SHIFT_HIQ_FREEPG_V1_8814B)
+#define BIT_CLEAR_HIQ_FREEPG_V1_8814B(x) ((x) & (~BITS_HIQ_FREEPG_V1_8814B))
+#define BIT_GET_HIQ_FREEPG_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_HIQ_FREEPG_V1_8814B) & BIT_MASK_HIQ_FREEPG_V1_8814B)
+#define BIT_SET_HIQ_FREEPG_V1_8814B(x, v) \
+ (BIT_CLEAR_HIQ_FREEPG_V1_8814B(x) | BIT_HIQ_FREEPG_V1_8814B(v))
+
+/* 2 REG_SDIO_FREE_TXPG2_8814B */
+
+#define BIT_SHIFT_PUB_FREEPG_V1_8814B 16
+#define BIT_MASK_PUB_FREEPG_V1_8814B 0xfff
+#define BIT_PUB_FREEPG_V1_8814B(x) \
+ (((x) & BIT_MASK_PUB_FREEPG_V1_8814B) << BIT_SHIFT_PUB_FREEPG_V1_8814B)
+#define BITS_PUB_FREEPG_V1_8814B \
+ (BIT_MASK_PUB_FREEPG_V1_8814B << BIT_SHIFT_PUB_FREEPG_V1_8814B)
+#define BIT_CLEAR_PUB_FREEPG_V1_8814B(x) ((x) & (~BITS_PUB_FREEPG_V1_8814B))
+#define BIT_GET_PUB_FREEPG_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_PUB_FREEPG_V1_8814B) & BIT_MASK_PUB_FREEPG_V1_8814B)
+#define BIT_SET_PUB_FREEPG_V1_8814B(x, v) \
+ (BIT_CLEAR_PUB_FREEPG_V1_8814B(x) | BIT_PUB_FREEPG_V1_8814B(v))
+
+#define BIT_SHIFT_LOW_FREEPG_V1_8814B 0
+#define BIT_MASK_LOW_FREEPG_V1_8814B 0xfff
+#define BIT_LOW_FREEPG_V1_8814B(x) \
+ (((x) & BIT_MASK_LOW_FREEPG_V1_8814B) << BIT_SHIFT_LOW_FREEPG_V1_8814B)
+#define BITS_LOW_FREEPG_V1_8814B \
+ (BIT_MASK_LOW_FREEPG_V1_8814B << BIT_SHIFT_LOW_FREEPG_V1_8814B)
+#define BIT_CLEAR_LOW_FREEPG_V1_8814B(x) ((x) & (~BITS_LOW_FREEPG_V1_8814B))
+#define BIT_GET_LOW_FREEPG_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_LOW_FREEPG_V1_8814B) & BIT_MASK_LOW_FREEPG_V1_8814B)
+#define BIT_SET_LOW_FREEPG_V1_8814B(x, v) \
+ (BIT_CLEAR_LOW_FREEPG_V1_8814B(x) | BIT_LOW_FREEPG_V1_8814B(v))
+
+/* 2 REG_SDIO_OQT_FREE_TXPG_V1_8814B */
+
+#define BIT_SHIFT_NOAC_OQT_FREEPG_V1_8814B 24
+#define BIT_MASK_NOAC_OQT_FREEPG_V1_8814B 0xff
+#define BIT_NOAC_OQT_FREEPG_V1_8814B(x) \
+ (((x) & BIT_MASK_NOAC_OQT_FREEPG_V1_8814B) \
+ << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8814B)
+#define BITS_NOAC_OQT_FREEPG_V1_8814B \
+ (BIT_MASK_NOAC_OQT_FREEPG_V1_8814B \
+ << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8814B)
+#define BIT_CLEAR_NOAC_OQT_FREEPG_V1_8814B(x) \
+ ((x) & (~BITS_NOAC_OQT_FREEPG_V1_8814B))
+#define BIT_GET_NOAC_OQT_FREEPG_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1_8814B) & \
+ BIT_MASK_NOAC_OQT_FREEPG_V1_8814B)
+#define BIT_SET_NOAC_OQT_FREEPG_V1_8814B(x, v) \
+ (BIT_CLEAR_NOAC_OQT_FREEPG_V1_8814B(x) | \
+ BIT_NOAC_OQT_FREEPG_V1_8814B(v))
+
+#define BIT_SHIFT_AC_OQT_FREEPG_V1_8814B 16
+#define BIT_MASK_AC_OQT_FREEPG_V1_8814B 0xff
+#define BIT_AC_OQT_FREEPG_V1_8814B(x) \
+ (((x) & BIT_MASK_AC_OQT_FREEPG_V1_8814B) \
+ << BIT_SHIFT_AC_OQT_FREEPG_V1_8814B)
+#define BITS_AC_OQT_FREEPG_V1_8814B \
+ (BIT_MASK_AC_OQT_FREEPG_V1_8814B << BIT_SHIFT_AC_OQT_FREEPG_V1_8814B)
+#define BIT_CLEAR_AC_OQT_FREEPG_V1_8814B(x) \
+ ((x) & (~BITS_AC_OQT_FREEPG_V1_8814B))
+#define BIT_GET_AC_OQT_FREEPG_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1_8814B) & \
+ BIT_MASK_AC_OQT_FREEPG_V1_8814B)
+#define BIT_SET_AC_OQT_FREEPG_V1_8814B(x, v) \
+ (BIT_CLEAR_AC_OQT_FREEPG_V1_8814B(x) | BIT_AC_OQT_FREEPG_V1_8814B(v))
+
+#define BIT_SHIFT_EXQ_FREEPG_V1_8814B 0
+#define BIT_MASK_EXQ_FREEPG_V1_8814B 0xfff
+#define BIT_EXQ_FREEPG_V1_8814B(x) \
+ (((x) & BIT_MASK_EXQ_FREEPG_V1_8814B) << BIT_SHIFT_EXQ_FREEPG_V1_8814B)
+#define BITS_EXQ_FREEPG_V1_8814B \
+ (BIT_MASK_EXQ_FREEPG_V1_8814B << BIT_SHIFT_EXQ_FREEPG_V1_8814B)
+#define BIT_CLEAR_EXQ_FREEPG_V1_8814B(x) ((x) & (~BITS_EXQ_FREEPG_V1_8814B))
+#define BIT_GET_EXQ_FREEPG_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_EXQ_FREEPG_V1_8814B) & BIT_MASK_EXQ_FREEPG_V1_8814B)
+#define BIT_SET_EXQ_FREEPG_V1_8814B(x, v) \
+ (BIT_CLEAR_EXQ_FREEPG_V1_8814B(x) | BIT_EXQ_FREEPG_V1_8814B(v))
+
+/* 2 REG_SDIO_HTSFR_INFO_8814B */
+
+#define BIT_SHIFT_HTSFR1_8814B 16
+#define BIT_MASK_HTSFR1_8814B 0xffff
+#define BIT_HTSFR1_8814B(x) \
+ (((x) & BIT_MASK_HTSFR1_8814B) << BIT_SHIFT_HTSFR1_8814B)
+#define BITS_HTSFR1_8814B (BIT_MASK_HTSFR1_8814B << BIT_SHIFT_HTSFR1_8814B)
+#define BIT_CLEAR_HTSFR1_8814B(x) ((x) & (~BITS_HTSFR1_8814B))
+#define BIT_GET_HTSFR1_8814B(x) \
+ (((x) >> BIT_SHIFT_HTSFR1_8814B) & BIT_MASK_HTSFR1_8814B)
+#define BIT_SET_HTSFR1_8814B(x, v) \
+ (BIT_CLEAR_HTSFR1_8814B(x) | BIT_HTSFR1_8814B(v))
+
+#define BIT_SHIFT_HTSFR0_8814B 0
+#define BIT_MASK_HTSFR0_8814B 0xffff
+#define BIT_HTSFR0_8814B(x) \
+ (((x) & BIT_MASK_HTSFR0_8814B) << BIT_SHIFT_HTSFR0_8814B)
+#define BITS_HTSFR0_8814B (BIT_MASK_HTSFR0_8814B << BIT_SHIFT_HTSFR0_8814B)
+#define BIT_CLEAR_HTSFR0_8814B(x) ((x) & (~BITS_HTSFR0_8814B))
+#define BIT_GET_HTSFR0_8814B(x) \
+ (((x) >> BIT_SHIFT_HTSFR0_8814B) & BIT_MASK_HTSFR0_8814B)
+#define BIT_SET_HTSFR0_8814B(x, v) \
+ (BIT_CLEAR_HTSFR0_8814B(x) | BIT_HTSFR0_8814B(v))
+
+/* 2 REG_SDIO_HCPWM1_V2_8814B */
+#define BIT_TOGGLE_8814B BIT(7)
+#define BIT_CUR_PS_8814B BIT(0)
+
+/* 2 REG_SDIO_HCPWM2_V2_8814B */
+
+/* 2 REG_SDIO_INDIRECT_REG_CFG_8814B */
+#define BIT_INDIRECT_REG_RDY_8814B BIT(20)
+#define BIT_INDIRECT_REG_R_8814B BIT(19)
+#define BIT_INDIRECT_REG_W_8814B BIT(18)
+
+#define BIT_SHIFT_INDIRECT_REG_SIZE_8814B 16
+#define BIT_MASK_INDIRECT_REG_SIZE_8814B 0x3
+#define BIT_INDIRECT_REG_SIZE_8814B(x) \
+ (((x) & BIT_MASK_INDIRECT_REG_SIZE_8814B) \
+ << BIT_SHIFT_INDIRECT_REG_SIZE_8814B)
+#define BITS_INDIRECT_REG_SIZE_8814B \
+ (BIT_MASK_INDIRECT_REG_SIZE_8814B << BIT_SHIFT_INDIRECT_REG_SIZE_8814B)
+#define BIT_CLEAR_INDIRECT_REG_SIZE_8814B(x) \
+ ((x) & (~BITS_INDIRECT_REG_SIZE_8814B))
+#define BIT_GET_INDIRECT_REG_SIZE_8814B(x) \
+ (((x) >> BIT_SHIFT_INDIRECT_REG_SIZE_8814B) & \
+ BIT_MASK_INDIRECT_REG_SIZE_8814B)
+#define BIT_SET_INDIRECT_REG_SIZE_8814B(x, v) \
+ (BIT_CLEAR_INDIRECT_REG_SIZE_8814B(x) | BIT_INDIRECT_REG_SIZE_8814B(v))
+
+#define BIT_SHIFT_INDIRECT_REG_ADDR_8814B 0
+#define BIT_MASK_INDIRECT_REG_ADDR_8814B 0xffff
+#define BIT_INDIRECT_REG_ADDR_8814B(x) \
+ (((x) & BIT_MASK_INDIRECT_REG_ADDR_8814B) \
+ << BIT_SHIFT_INDIRECT_REG_ADDR_8814B)
+#define BITS_INDIRECT_REG_ADDR_8814B \
+ (BIT_MASK_INDIRECT_REG_ADDR_8814B << BIT_SHIFT_INDIRECT_REG_ADDR_8814B)
+#define BIT_CLEAR_INDIRECT_REG_ADDR_8814B(x) \
+ ((x) & (~BITS_INDIRECT_REG_ADDR_8814B))
+#define BIT_GET_INDIRECT_REG_ADDR_8814B(x) \
+ (((x) >> BIT_SHIFT_INDIRECT_REG_ADDR_8814B) & \
+ BIT_MASK_INDIRECT_REG_ADDR_8814B)
+#define BIT_SET_INDIRECT_REG_ADDR_8814B(x, v) \
+ (BIT_CLEAR_INDIRECT_REG_ADDR_8814B(x) | BIT_INDIRECT_REG_ADDR_8814B(v))
+
+/* 2 REG_SDIO_INDIRECT_REG_DATA_8814B */
+
+#define BIT_SHIFT_INDIRECT_REG_DATA_8814B 0
+#define BIT_MASK_INDIRECT_REG_DATA_8814B 0xffffffffL
+#define BIT_INDIRECT_REG_DATA_8814B(x) \
+ (((x) & BIT_MASK_INDIRECT_REG_DATA_8814B) \
+ << BIT_SHIFT_INDIRECT_REG_DATA_8814B)
+#define BITS_INDIRECT_REG_DATA_8814B \
+ (BIT_MASK_INDIRECT_REG_DATA_8814B << BIT_SHIFT_INDIRECT_REG_DATA_8814B)
+#define BIT_CLEAR_INDIRECT_REG_DATA_8814B(x) \
+ ((x) & (~BITS_INDIRECT_REG_DATA_8814B))
+#define BIT_GET_INDIRECT_REG_DATA_8814B(x) \
+ (((x) >> BIT_SHIFT_INDIRECT_REG_DATA_8814B) & \
+ BIT_MASK_INDIRECT_REG_DATA_8814B)
+#define BIT_SET_INDIRECT_REG_DATA_8814B(x, v) \
+ (BIT_CLEAR_INDIRECT_REG_DATA_8814B(x) | BIT_INDIRECT_REG_DATA_8814B(v))
+
+/* 2 REG_SDIO_H2C_8814B */
+
+#define BIT_SHIFT_SDIO_H2C_MSG_8814B 0
+#define BIT_MASK_SDIO_H2C_MSG_8814B 0xffffffffL
+#define BIT_SDIO_H2C_MSG_8814B(x) \
+ (((x) & BIT_MASK_SDIO_H2C_MSG_8814B) << BIT_SHIFT_SDIO_H2C_MSG_8814B)
+#define BITS_SDIO_H2C_MSG_8814B \
+ (BIT_MASK_SDIO_H2C_MSG_8814B << BIT_SHIFT_SDIO_H2C_MSG_8814B)
+#define BIT_CLEAR_SDIO_H2C_MSG_8814B(x) ((x) & (~BITS_SDIO_H2C_MSG_8814B))
+#define BIT_GET_SDIO_H2C_MSG_8814B(x) \
+ (((x) >> BIT_SHIFT_SDIO_H2C_MSG_8814B) & BIT_MASK_SDIO_H2C_MSG_8814B)
+#define BIT_SET_SDIO_H2C_MSG_8814B(x, v) \
+ (BIT_CLEAR_SDIO_H2C_MSG_8814B(x) | BIT_SDIO_H2C_MSG_8814B(v))
+
+/* 2 REG_SDIO_C2H_8814B */
+
+#define BIT_SHIFT_SDIO_C2H_MSG_8814B 0
+#define BIT_MASK_SDIO_C2H_MSG_8814B 0xffffffffL
+#define BIT_SDIO_C2H_MSG_8814B(x) \
+ (((x) & BIT_MASK_SDIO_C2H_MSG_8814B) << BIT_SHIFT_SDIO_C2H_MSG_8814B)
+#define BITS_SDIO_C2H_MSG_8814B \
+ (BIT_MASK_SDIO_C2H_MSG_8814B << BIT_SHIFT_SDIO_C2H_MSG_8814B)
+#define BIT_CLEAR_SDIO_C2H_MSG_8814B(x) ((x) & (~BITS_SDIO_C2H_MSG_8814B))
+#define BIT_GET_SDIO_C2H_MSG_8814B(x) \
+ (((x) >> BIT_SHIFT_SDIO_C2H_MSG_8814B) & BIT_MASK_SDIO_C2H_MSG_8814B)
+#define BIT_SET_SDIO_C2H_MSG_8814B(x, v) \
+ (BIT_CLEAR_SDIO_C2H_MSG_8814B(x) | BIT_SDIO_C2H_MSG_8814B(v))
+
+/* 2 REG_SDIO_HRPWM1_8814B */
+#define BIT_TOGGLE_8814B BIT(7)
+#define BIT_ACK_8814B BIT(6)
+#define BIT_REQ_PS_8814B BIT(0)
+
+/* 2 REG_SDIO_HRPWM2_8814B */
+
+/* 2 REG_SDIO_HPS_CLKR_8814B */
+
+/* 2 REG_SDIO_BUS_CTRL_8814B */
+#define BIT_PAD_CLK_XHGE_EN_8814B BIT(3)
+#define BIT_INTER_CLK_EN_8814B BIT(2)
+#define BIT_EN_RPT_TXCRC_8814B BIT(1)
+#define BIT_DIS_RXDMA_STS_8814B BIT(0)
+
+/* 2 REG_SDIO_HSUS_CTRL_8814B */
+#define BIT_INTR_CTRL_8814B BIT(4)
+#define BIT_SDIO_VOLTAGE_8814B BIT(3)
+#define BIT_BYPASS_INIT_8814B BIT(2)
+#define BIT_HCI_RESUME_RDY_8814B BIT(1)
+#define BIT_HCI_SUS_REQ_8814B BIT(0)
+
+/* 2 REG_SDIO_RESPONSE_TIMER_8814B */
+
+#define BIT_SHIFT_CMDIN_2RESP_TIMER_8814B 0
+#define BIT_MASK_CMDIN_2RESP_TIMER_8814B 0xffff
+#define BIT_CMDIN_2RESP_TIMER_8814B(x) \
+ (((x) & BIT_MASK_CMDIN_2RESP_TIMER_8814B) \
+ << BIT_SHIFT_CMDIN_2RESP_TIMER_8814B)
+#define BITS_CMDIN_2RESP_TIMER_8814B \
+ (BIT_MASK_CMDIN_2RESP_TIMER_8814B << BIT_SHIFT_CMDIN_2RESP_TIMER_8814B)
+#define BIT_CLEAR_CMDIN_2RESP_TIMER_8814B(x) \
+ ((x) & (~BITS_CMDIN_2RESP_TIMER_8814B))
+#define BIT_GET_CMDIN_2RESP_TIMER_8814B(x) \
+ (((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER_8814B) & \
+ BIT_MASK_CMDIN_2RESP_TIMER_8814B)
+#define BIT_SET_CMDIN_2RESP_TIMER_8814B(x, v) \
+ (BIT_CLEAR_CMDIN_2RESP_TIMER_8814B(x) | BIT_CMDIN_2RESP_TIMER_8814B(v))
+
+/* 2 REG_SDIO_CMD_CRC_8814B */
+
+#define BIT_SHIFT_SDIO_CMD_CRC_V1_8814B 0
+#define BIT_MASK_SDIO_CMD_CRC_V1_8814B 0xff
+#define BIT_SDIO_CMD_CRC_V1_8814B(x) \
+ (((x) & BIT_MASK_SDIO_CMD_CRC_V1_8814B) \
+ << BIT_SHIFT_SDIO_CMD_CRC_V1_8814B)
+#define BITS_SDIO_CMD_CRC_V1_8814B \
+ (BIT_MASK_SDIO_CMD_CRC_V1_8814B << BIT_SHIFT_SDIO_CMD_CRC_V1_8814B)
+#define BIT_CLEAR_SDIO_CMD_CRC_V1_8814B(x) ((x) & (~BITS_SDIO_CMD_CRC_V1_8814B))
+#define BIT_GET_SDIO_CMD_CRC_V1_8814B(x) \
+ (((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1_8814B) & \
+ BIT_MASK_SDIO_CMD_CRC_V1_8814B)
+#define BIT_SET_SDIO_CMD_CRC_V1_8814B(x, v) \
+ (BIT_CLEAR_SDIO_CMD_CRC_V1_8814B(x) | BIT_SDIO_CMD_CRC_V1_8814B(v))
+
+/* 2 REG_SDIO_HSISR_8814B */
+#define BIT_DRV_WLAN_INT_CLR_8814B BIT(1)
+#define BIT_DRV_WLAN_INT_8814B BIT(0)
+
+/* 2 REG_SDIO_ERR_RPT_8814B */
+#define BIT_HR_FF_OVF_8814B BIT(6)
+#define BIT_HR_FF_UDN_8814B BIT(5)
+#define BIT_TXDMA_BUSY_ERR_8814B BIT(4)
+#define BIT_TXDMA_VLD_ERR_8814B BIT(3)
+#define BIT_QSEL_UNKNOWN_ERR_8814B BIT(2)
+#define BIT_QSEL_MIS_ERR_8814B BIT(1)
+#define BIT_SDIO_OVERRD_ERR_8814B BIT(0)
+
+/* 2 REG_SDIO_CMD_ERRCNT_8814B */
+
+#define BIT_SHIFT_CMD_CRC_ERR_CNT_8814B 0
+#define BIT_MASK_CMD_CRC_ERR_CNT_8814B 0xff
+#define BIT_CMD_CRC_ERR_CNT_8814B(x) \
+ (((x) & BIT_MASK_CMD_CRC_ERR_CNT_8814B) \
+ << BIT_SHIFT_CMD_CRC_ERR_CNT_8814B)
+#define BITS_CMD_CRC_ERR_CNT_8814B \
+ (BIT_MASK_CMD_CRC_ERR_CNT_8814B << BIT_SHIFT_CMD_CRC_ERR_CNT_8814B)
+#define BIT_CLEAR_CMD_CRC_ERR_CNT_8814B(x) ((x) & (~BITS_CMD_CRC_ERR_CNT_8814B))
+#define BIT_GET_CMD_CRC_ERR_CNT_8814B(x) \
+ (((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT_8814B) & \
+ BIT_MASK_CMD_CRC_ERR_CNT_8814B)
+#define BIT_SET_CMD_CRC_ERR_CNT_8814B(x, v) \
+ (BIT_CLEAR_CMD_CRC_ERR_CNT_8814B(x) | BIT_CMD_CRC_ERR_CNT_8814B(v))
+
+/* 2 REG_SDIO_DATA_ERRCNT_8814B */
+
+#define BIT_SHIFT_DATA_CRC_ERR_CNT_8814B 0
+#define BIT_MASK_DATA_CRC_ERR_CNT_8814B 0xff
+#define BIT_DATA_CRC_ERR_CNT_8814B(x) \
+ (((x) & BIT_MASK_DATA_CRC_ERR_CNT_8814B) \
+ << BIT_SHIFT_DATA_CRC_ERR_CNT_8814B)
+#define BITS_DATA_CRC_ERR_CNT_8814B \
+ (BIT_MASK_DATA_CRC_ERR_CNT_8814B << BIT_SHIFT_DATA_CRC_ERR_CNT_8814B)
+#define BIT_CLEAR_DATA_CRC_ERR_CNT_8814B(x) \
+ ((x) & (~BITS_DATA_CRC_ERR_CNT_8814B))
+#define BIT_GET_DATA_CRC_ERR_CNT_8814B(x) \
+ (((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT_8814B) & \
+ BIT_MASK_DATA_CRC_ERR_CNT_8814B)
+#define BIT_SET_DATA_CRC_ERR_CNT_8814B(x, v) \
+ (BIT_CLEAR_DATA_CRC_ERR_CNT_8814B(x) | BIT_DATA_CRC_ERR_CNT_8814B(v))
+
+/* 2 REG_SDIO_CMD_ERR_CONTENT_8814B */
+
+#define BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8814B 0
+#define BIT_MASK_SDIO_CMD_ERR_CONTENT_8814B 0xffffffffffL
+#define BIT_SDIO_CMD_ERR_CONTENT_8814B(x) \
+ (((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8814B) \
+ << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8814B)
+#define BITS_SDIO_CMD_ERR_CONTENT_8814B \
+ (BIT_MASK_SDIO_CMD_ERR_CONTENT_8814B \
+ << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8814B)
+#define BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8814B(x) \
+ ((x) & (~BITS_SDIO_CMD_ERR_CONTENT_8814B))
+#define BIT_GET_SDIO_CMD_ERR_CONTENT_8814B(x) \
+ (((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8814B) & \
+ BIT_MASK_SDIO_CMD_ERR_CONTENT_8814B)
+#define BIT_SET_SDIO_CMD_ERR_CONTENT_8814B(x, v) \
+ (BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8814B(x) | \
+ BIT_SDIO_CMD_ERR_CONTENT_8814B(v))
+
+/* 2 REG_SDIO_CRC_ERR_IDX_8814B */
+#define BIT_D3_CRC_ERR_8814B BIT(4)
+#define BIT_D2_CRC_ERR_8814B BIT(3)
+#define BIT_D1_CRC_ERR_8814B BIT(2)
+#define BIT_D0_CRC_ERR_8814B BIT(1)
+#define BIT_CMD_CRC_ERR_8814B BIT(0)
+
+/* 2 REG_SDIO_DATA_CRC_8814B */
+
+#define BIT_SHIFT_SDIO_DATA_CRC_8814B 0
+#define BIT_MASK_SDIO_DATA_CRC_8814B 0xffff
+#define BIT_SDIO_DATA_CRC_8814B(x) \
+ (((x) & BIT_MASK_SDIO_DATA_CRC_8814B) << BIT_SHIFT_SDIO_DATA_CRC_8814B)
+#define BITS_SDIO_DATA_CRC_8814B \
+ (BIT_MASK_SDIO_DATA_CRC_8814B << BIT_SHIFT_SDIO_DATA_CRC_8814B)
+#define BIT_CLEAR_SDIO_DATA_CRC_8814B(x) ((x) & (~BITS_SDIO_DATA_CRC_8814B))
+#define BIT_GET_SDIO_DATA_CRC_8814B(x) \
+ (((x) >> BIT_SHIFT_SDIO_DATA_CRC_8814B) & BIT_MASK_SDIO_DATA_CRC_8814B)
+#define BIT_SET_SDIO_DATA_CRC_8814B(x, v) \
+ (BIT_CLEAR_SDIO_DATA_CRC_8814B(x) | BIT_SDIO_DATA_CRC_8814B(v))
+
+/* 2 REG_SDIO_DATA_REPLY_TIME_8814B */
+
+#define BIT_SHIFT_SDIO_DATA_REPLY_TIME_8814B 0
+#define BIT_MASK_SDIO_DATA_REPLY_TIME_8814B 0x7
+#define BIT_SDIO_DATA_REPLY_TIME_8814B(x) \
+ (((x) & BIT_MASK_SDIO_DATA_REPLY_TIME_8814B) \
+ << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8814B)
+#define BITS_SDIO_DATA_REPLY_TIME_8814B \
+ (BIT_MASK_SDIO_DATA_REPLY_TIME_8814B \
+ << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8814B)
+#define BIT_CLEAR_SDIO_DATA_REPLY_TIME_8814B(x) \
+ ((x) & (~BITS_SDIO_DATA_REPLY_TIME_8814B))
+#define BIT_GET_SDIO_DATA_REPLY_TIME_8814B(x) \
+ (((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME_8814B) & \
+ BIT_MASK_SDIO_DATA_REPLY_TIME_8814B)
+#define BIT_SET_SDIO_DATA_REPLY_TIME_8814B(x, v) \
+ (BIT_CLEAR_SDIO_DATA_REPLY_TIME_8814B(x) | \
+ BIT_SDIO_DATA_REPLY_TIME_8814B(v))
+
+#endif
diff --git a/hal/halmac/halmac_bit_8821c.h b/hal/halmac/halmac_bit_8821c.h
index 5081766..7538125 100644
--- a/hal/halmac/halmac_bit_8821c.h
+++ b/hal/halmac/halmac_bit_8821c.h
@@ -1,3 +1,18 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
#ifndef __INC_HALMAC_BIT_8821C_H
#define __INC_HALMAC_BIT_8821C_H
@@ -91,14 +106,25 @@
#define BIT_SHIFT_VPDIDX_8821C 8
#define BIT_MASK_VPDIDX_8821C 0xff
-#define BIT_VPDIDX_8821C(x) (((x) & BIT_MASK_VPDIDX_8821C) << BIT_SHIFT_VPDIDX_8821C)
-#define BIT_GET_VPDIDX_8821C(x) (((x) >> BIT_SHIFT_VPDIDX_8821C) & BIT_MASK_VPDIDX_8821C)
-
+#define BIT_VPDIDX_8821C(x) \
+ (((x) & BIT_MASK_VPDIDX_8821C) << BIT_SHIFT_VPDIDX_8821C)
+#define BITS_VPDIDX_8821C (BIT_MASK_VPDIDX_8821C << BIT_SHIFT_VPDIDX_8821C)
+#define BIT_CLEAR_VPDIDX_8821C(x) ((x) & (~BITS_VPDIDX_8821C))
+#define BIT_GET_VPDIDX_8821C(x) \
+ (((x) >> BIT_SHIFT_VPDIDX_8821C) & BIT_MASK_VPDIDX_8821C)
+#define BIT_SET_VPDIDX_8821C(x, v) \
+ (BIT_CLEAR_VPDIDX_8821C(x) | BIT_VPDIDX_8821C(v))
#define BIT_SHIFT_EEM1_0_8821C 6
#define BIT_MASK_EEM1_0_8821C 0x3
-#define BIT_EEM1_0_8821C(x) (((x) & BIT_MASK_EEM1_0_8821C) << BIT_SHIFT_EEM1_0_8821C)
-#define BIT_GET_EEM1_0_8821C(x) (((x) >> BIT_SHIFT_EEM1_0_8821C) & BIT_MASK_EEM1_0_8821C)
+#define BIT_EEM1_0_8821C(x) \
+ (((x) & BIT_MASK_EEM1_0_8821C) << BIT_SHIFT_EEM1_0_8821C)
+#define BITS_EEM1_0_8821C (BIT_MASK_EEM1_0_8821C << BIT_SHIFT_EEM1_0_8821C)
+#define BIT_CLEAR_EEM1_0_8821C(x) ((x) & (~BITS_EEM1_0_8821C))
+#define BIT_GET_EEM1_0_8821C(x) \
+ (((x) >> BIT_SHIFT_EEM1_0_8821C) & BIT_MASK_EEM1_0_8821C)
+#define BIT_SET_EEM1_0_8821C(x, v) \
+ (BIT_CLEAR_EEM1_0_8821C(x) | BIT_EEM1_0_8821C(v))
#define BIT_AUTOLOAD_SUS_8821C BIT(5)
#define BIT_EERPOMSEL_8821C BIT(4)
@@ -111,9 +137,15 @@
#define BIT_SHIFT_VPD_DATA_8821C 0
#define BIT_MASK_VPD_DATA_8821C 0xffffffffL
-#define BIT_VPD_DATA_8821C(x) (((x) & BIT_MASK_VPD_DATA_8821C) << BIT_SHIFT_VPD_DATA_8821C)
-#define BIT_GET_VPD_DATA_8821C(x) (((x) >> BIT_SHIFT_VPD_DATA_8821C) & BIT_MASK_VPD_DATA_8821C)
-
+#define BIT_VPD_DATA_8821C(x) \
+ (((x) & BIT_MASK_VPD_DATA_8821C) << BIT_SHIFT_VPD_DATA_8821C)
+#define BITS_VPD_DATA_8821C \
+ (BIT_MASK_VPD_DATA_8821C << BIT_SHIFT_VPD_DATA_8821C)
+#define BIT_CLEAR_VPD_DATA_8821C(x) ((x) & (~BITS_VPD_DATA_8821C))
+#define BIT_GET_VPD_DATA_8821C(x) \
+ (((x) >> BIT_SHIFT_VPD_DATA_8821C) & BIT_MASK_VPD_DATA_8821C)
+#define BIT_SET_VPD_DATA_8821C(x, v) \
+ (BIT_CLEAR_VPD_DATA_8821C(x) | BIT_VPD_DATA_8821C(v))
/* 2 REG_SYS_SWR_CTRL1_8821C */
#define BIT_C2_L_BIT0_8821C BIT(31)
@@ -121,20 +153,37 @@
#define BIT_SHIFT_C1_L_8821C 29
#define BIT_MASK_C1_L_8821C 0x3
#define BIT_C1_L_8821C(x) (((x) & BIT_MASK_C1_L_8821C) << BIT_SHIFT_C1_L_8821C)
-#define BIT_GET_C1_L_8821C(x) (((x) >> BIT_SHIFT_C1_L_8821C) & BIT_MASK_C1_L_8821C)
-
+#define BITS_C1_L_8821C (BIT_MASK_C1_L_8821C << BIT_SHIFT_C1_L_8821C)
+#define BIT_CLEAR_C1_L_8821C(x) ((x) & (~BITS_C1_L_8821C))
+#define BIT_GET_C1_L_8821C(x) \
+ (((x) >> BIT_SHIFT_C1_L_8821C) & BIT_MASK_C1_L_8821C)
+#define BIT_SET_C1_L_8821C(x, v) (BIT_CLEAR_C1_L_8821C(x) | BIT_C1_L_8821C(v))
#define BIT_SHIFT_REG_FREQ_L_8821C 25
#define BIT_MASK_REG_FREQ_L_8821C 0x7
-#define BIT_REG_FREQ_L_8821C(x) (((x) & BIT_MASK_REG_FREQ_L_8821C) << BIT_SHIFT_REG_FREQ_L_8821C)
-#define BIT_GET_REG_FREQ_L_8821C(x) (((x) >> BIT_SHIFT_REG_FREQ_L_8821C) & BIT_MASK_REG_FREQ_L_8821C)
+#define BIT_REG_FREQ_L_8821C(x) \
+ (((x) & BIT_MASK_REG_FREQ_L_8821C) << BIT_SHIFT_REG_FREQ_L_8821C)
+#define BITS_REG_FREQ_L_8821C \
+ (BIT_MASK_REG_FREQ_L_8821C << BIT_SHIFT_REG_FREQ_L_8821C)
+#define BIT_CLEAR_REG_FREQ_L_8821C(x) ((x) & (~BITS_REG_FREQ_L_8821C))
+#define BIT_GET_REG_FREQ_L_8821C(x) \
+ (((x) >> BIT_SHIFT_REG_FREQ_L_8821C) & BIT_MASK_REG_FREQ_L_8821C)
+#define BIT_SET_REG_FREQ_L_8821C(x, v) \
+ (BIT_CLEAR_REG_FREQ_L_8821C(x) | BIT_REG_FREQ_L_8821C(v))
#define BIT_REG_EN_DUTY_8821C BIT(24)
#define BIT_SHIFT_REG_MODE_8821C 22
#define BIT_MASK_REG_MODE_8821C 0x3
-#define BIT_REG_MODE_8821C(x) (((x) & BIT_MASK_REG_MODE_8821C) << BIT_SHIFT_REG_MODE_8821C)
-#define BIT_GET_REG_MODE_8821C(x) (((x) >> BIT_SHIFT_REG_MODE_8821C) & BIT_MASK_REG_MODE_8821C)
+#define BIT_REG_MODE_8821C(x) \
+ (((x) & BIT_MASK_REG_MODE_8821C) << BIT_SHIFT_REG_MODE_8821C)
+#define BITS_REG_MODE_8821C \
+ (BIT_MASK_REG_MODE_8821C << BIT_SHIFT_REG_MODE_8821C)
+#define BIT_CLEAR_REG_MODE_8821C(x) ((x) & (~BITS_REG_MODE_8821C))
+#define BIT_GET_REG_MODE_8821C(x) \
+ (((x) >> BIT_SHIFT_REG_MODE_8821C) & BIT_MASK_REG_MODE_8821C)
+#define BIT_SET_REG_MODE_8821C(x, v) \
+ (BIT_CLEAR_REG_MODE_8821C(x) | BIT_REG_MODE_8821C(v))
#define BIT_REG_EN_SP_8821C BIT(21)
#define BIT_REG_AUTO_L_8821C BIT(20)
@@ -143,14 +192,23 @@
#define BIT_SHIFT_OCP_L1_8821C 15
#define BIT_MASK_OCP_L1_8821C 0x7
-#define BIT_OCP_L1_8821C(x) (((x) & BIT_MASK_OCP_L1_8821C) << BIT_SHIFT_OCP_L1_8821C)
-#define BIT_GET_OCP_L1_8821C(x) (((x) >> BIT_SHIFT_OCP_L1_8821C) & BIT_MASK_OCP_L1_8821C)
-
+#define BIT_OCP_L1_8821C(x) \
+ (((x) & BIT_MASK_OCP_L1_8821C) << BIT_SHIFT_OCP_L1_8821C)
+#define BITS_OCP_L1_8821C (BIT_MASK_OCP_L1_8821C << BIT_SHIFT_OCP_L1_8821C)
+#define BIT_CLEAR_OCP_L1_8821C(x) ((x) & (~BITS_OCP_L1_8821C))
+#define BIT_GET_OCP_L1_8821C(x) \
+ (((x) >> BIT_SHIFT_OCP_L1_8821C) & BIT_MASK_OCP_L1_8821C)
+#define BIT_SET_OCP_L1_8821C(x, v) \
+ (BIT_CLEAR_OCP_L1_8821C(x) | BIT_OCP_L1_8821C(v))
#define BIT_SHIFT_CF_L_8821C 13
#define BIT_MASK_CF_L_8821C 0x3
#define BIT_CF_L_8821C(x) (((x) & BIT_MASK_CF_L_8821C) << BIT_SHIFT_CF_L_8821C)
-#define BIT_GET_CF_L_8821C(x) (((x) >> BIT_SHIFT_CF_L_8821C) & BIT_MASK_CF_L_8821C)
+#define BITS_CF_L_8821C (BIT_MASK_CF_L_8821C << BIT_SHIFT_CF_L_8821C)
+#define BIT_CLEAR_CF_L_8821C(x) ((x) & (~BITS_CF_L_8821C))
+#define BIT_GET_CF_L_8821C(x) \
+ (((x) >> BIT_SHIFT_CF_L_8821C) & BIT_MASK_CF_L_8821C)
+#define BIT_SET_CF_L_8821C(x, v) (BIT_CLEAR_CF_L_8821C(x) | BIT_CF_L_8821C(v))
#define BIT_SW18_FPWM_8821C BIT(11)
#define BIT_SW18_SWEN_8821C BIT(9)
@@ -164,32 +222,62 @@
#define BIT_SHIFT_REG_DELAY_8821C 28
#define BIT_MASK_REG_DELAY_8821C 0x3
-#define BIT_REG_DELAY_8821C(x) (((x) & BIT_MASK_REG_DELAY_8821C) << BIT_SHIFT_REG_DELAY_8821C)
-#define BIT_GET_REG_DELAY_8821C(x) (((x) >> BIT_SHIFT_REG_DELAY_8821C) & BIT_MASK_REG_DELAY_8821C)
-
+#define BIT_REG_DELAY_8821C(x) \
+ (((x) & BIT_MASK_REG_DELAY_8821C) << BIT_SHIFT_REG_DELAY_8821C)
+#define BITS_REG_DELAY_8821C \
+ (BIT_MASK_REG_DELAY_8821C << BIT_SHIFT_REG_DELAY_8821C)
+#define BIT_CLEAR_REG_DELAY_8821C(x) ((x) & (~BITS_REG_DELAY_8821C))
+#define BIT_GET_REG_DELAY_8821C(x) \
+ (((x) >> BIT_SHIFT_REG_DELAY_8821C) & BIT_MASK_REG_DELAY_8821C)
+#define BIT_SET_REG_DELAY_8821C(x, v) \
+ (BIT_CLEAR_REG_DELAY_8821C(x) | BIT_REG_DELAY_8821C(v))
#define BIT_SHIFT_V15ADJ_L1_V1_8821C 24
#define BIT_MASK_V15ADJ_L1_V1_8821C 0x7
-#define BIT_V15ADJ_L1_V1_8821C(x) (((x) & BIT_MASK_V15ADJ_L1_V1_8821C) << BIT_SHIFT_V15ADJ_L1_V1_8821C)
-#define BIT_GET_V15ADJ_L1_V1_8821C(x) (((x) >> BIT_SHIFT_V15ADJ_L1_V1_8821C) & BIT_MASK_V15ADJ_L1_V1_8821C)
-
+#define BIT_V15ADJ_L1_V1_8821C(x) \
+ (((x) & BIT_MASK_V15ADJ_L1_V1_8821C) << BIT_SHIFT_V15ADJ_L1_V1_8821C)
+#define BITS_V15ADJ_L1_V1_8821C \
+ (BIT_MASK_V15ADJ_L1_V1_8821C << BIT_SHIFT_V15ADJ_L1_V1_8821C)
+#define BIT_CLEAR_V15ADJ_L1_V1_8821C(x) ((x) & (~BITS_V15ADJ_L1_V1_8821C))
+#define BIT_GET_V15ADJ_L1_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_V15ADJ_L1_V1_8821C) & BIT_MASK_V15ADJ_L1_V1_8821C)
+#define BIT_SET_V15ADJ_L1_V1_8821C(x, v) \
+ (BIT_CLEAR_V15ADJ_L1_V1_8821C(x) | BIT_V15ADJ_L1_V1_8821C(v))
#define BIT_SHIFT_VOL_L1_V1_8821C 20
#define BIT_MASK_VOL_L1_V1_8821C 0xf
-#define BIT_VOL_L1_V1_8821C(x) (((x) & BIT_MASK_VOL_L1_V1_8821C) << BIT_SHIFT_VOL_L1_V1_8821C)
-#define BIT_GET_VOL_L1_V1_8821C(x) (((x) >> BIT_SHIFT_VOL_L1_V1_8821C) & BIT_MASK_VOL_L1_V1_8821C)
-
+#define BIT_VOL_L1_V1_8821C(x) \
+ (((x) & BIT_MASK_VOL_L1_V1_8821C) << BIT_SHIFT_VOL_L1_V1_8821C)
+#define BITS_VOL_L1_V1_8821C \
+ (BIT_MASK_VOL_L1_V1_8821C << BIT_SHIFT_VOL_L1_V1_8821C)
+#define BIT_CLEAR_VOL_L1_V1_8821C(x) ((x) & (~BITS_VOL_L1_V1_8821C))
+#define BIT_GET_VOL_L1_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_VOL_L1_V1_8821C) & BIT_MASK_VOL_L1_V1_8821C)
+#define BIT_SET_VOL_L1_V1_8821C(x, v) \
+ (BIT_CLEAR_VOL_L1_V1_8821C(x) | BIT_VOL_L1_V1_8821C(v))
#define BIT_SHIFT_IN_L1_V1_8821C 17
#define BIT_MASK_IN_L1_V1_8821C 0x7
-#define BIT_IN_L1_V1_8821C(x) (((x) & BIT_MASK_IN_L1_V1_8821C) << BIT_SHIFT_IN_L1_V1_8821C)
-#define BIT_GET_IN_L1_V1_8821C(x) (((x) >> BIT_SHIFT_IN_L1_V1_8821C) & BIT_MASK_IN_L1_V1_8821C)
-
+#define BIT_IN_L1_V1_8821C(x) \
+ (((x) & BIT_MASK_IN_L1_V1_8821C) << BIT_SHIFT_IN_L1_V1_8821C)
+#define BITS_IN_L1_V1_8821C \
+ (BIT_MASK_IN_L1_V1_8821C << BIT_SHIFT_IN_L1_V1_8821C)
+#define BIT_CLEAR_IN_L1_V1_8821C(x) ((x) & (~BITS_IN_L1_V1_8821C))
+#define BIT_GET_IN_L1_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_IN_L1_V1_8821C) & BIT_MASK_IN_L1_V1_8821C)
+#define BIT_SET_IN_L1_V1_8821C(x, v) \
+ (BIT_CLEAR_IN_L1_V1_8821C(x) | BIT_IN_L1_V1_8821C(v))
#define BIT_SHIFT_TBOX_L1_8821C 15
#define BIT_MASK_TBOX_L1_8821C 0x3
-#define BIT_TBOX_L1_8821C(x) (((x) & BIT_MASK_TBOX_L1_8821C) << BIT_SHIFT_TBOX_L1_8821C)
-#define BIT_GET_TBOX_L1_8821C(x) (((x) >> BIT_SHIFT_TBOX_L1_8821C) & BIT_MASK_TBOX_L1_8821C)
+#define BIT_TBOX_L1_8821C(x) \
+ (((x) & BIT_MASK_TBOX_L1_8821C) << BIT_SHIFT_TBOX_L1_8821C)
+#define BITS_TBOX_L1_8821C (BIT_MASK_TBOX_L1_8821C << BIT_SHIFT_TBOX_L1_8821C)
+#define BIT_CLEAR_TBOX_L1_8821C(x) ((x) & (~BITS_TBOX_L1_8821C))
+#define BIT_GET_TBOX_L1_8821C(x) \
+ (((x) >> BIT_SHIFT_TBOX_L1_8821C) & BIT_MASK_TBOX_L1_8821C)
+#define BIT_SET_TBOX_L1_8821C(x, v) \
+ (BIT_CLEAR_TBOX_L1_8821C(x) | BIT_TBOX_L1_8821C(v))
#define BIT_SW18_SEL_8821C BIT(13)
@@ -199,25 +287,44 @@
#define BIT_SHIFT_R3_L_8821C 7
#define BIT_MASK_R3_L_8821C 0x3
#define BIT_R3_L_8821C(x) (((x) & BIT_MASK_R3_L_8821C) << BIT_SHIFT_R3_L_8821C)
-#define BIT_GET_R3_L_8821C(x) (((x) >> BIT_SHIFT_R3_L_8821C) & BIT_MASK_R3_L_8821C)
-
+#define BITS_R3_L_8821C (BIT_MASK_R3_L_8821C << BIT_SHIFT_R3_L_8821C)
+#define BIT_CLEAR_R3_L_8821C(x) ((x) & (~BITS_R3_L_8821C))
+#define BIT_GET_R3_L_8821C(x) \
+ (((x) >> BIT_SHIFT_R3_L_8821C) & BIT_MASK_R3_L_8821C)
+#define BIT_SET_R3_L_8821C(x, v) (BIT_CLEAR_R3_L_8821C(x) | BIT_R3_L_8821C(v))
#define BIT_SHIFT_SW18_R2_8821C 5
#define BIT_MASK_SW18_R2_8821C 0x3
-#define BIT_SW18_R2_8821C(x) (((x) & BIT_MASK_SW18_R2_8821C) << BIT_SHIFT_SW18_R2_8821C)
-#define BIT_GET_SW18_R2_8821C(x) (((x) >> BIT_SHIFT_SW18_R2_8821C) & BIT_MASK_SW18_R2_8821C)
-
+#define BIT_SW18_R2_8821C(x) \
+ (((x) & BIT_MASK_SW18_R2_8821C) << BIT_SHIFT_SW18_R2_8821C)
+#define BITS_SW18_R2_8821C (BIT_MASK_SW18_R2_8821C << BIT_SHIFT_SW18_R2_8821C)
+#define BIT_CLEAR_SW18_R2_8821C(x) ((x) & (~BITS_SW18_R2_8821C))
+#define BIT_GET_SW18_R2_8821C(x) \
+ (((x) >> BIT_SHIFT_SW18_R2_8821C) & BIT_MASK_SW18_R2_8821C)
+#define BIT_SET_SW18_R2_8821C(x, v) \
+ (BIT_CLEAR_SW18_R2_8821C(x) | BIT_SW18_R2_8821C(v))
#define BIT_SHIFT_SW18_R1_8821C 3
#define BIT_MASK_SW18_R1_8821C 0x3
-#define BIT_SW18_R1_8821C(x) (((x) & BIT_MASK_SW18_R1_8821C) << BIT_SHIFT_SW18_R1_8821C)
-#define BIT_GET_SW18_R1_8821C(x) (((x) >> BIT_SHIFT_SW18_R1_8821C) & BIT_MASK_SW18_R1_8821C)
-
+#define BIT_SW18_R1_8821C(x) \
+ (((x) & BIT_MASK_SW18_R1_8821C) << BIT_SHIFT_SW18_R1_8821C)
+#define BITS_SW18_R1_8821C (BIT_MASK_SW18_R1_8821C << BIT_SHIFT_SW18_R1_8821C)
+#define BIT_CLEAR_SW18_R1_8821C(x) ((x) & (~BITS_SW18_R1_8821C))
+#define BIT_GET_SW18_R1_8821C(x) \
+ (((x) >> BIT_SHIFT_SW18_R1_8821C) & BIT_MASK_SW18_R1_8821C)
+#define BIT_SET_SW18_R1_8821C(x, v) \
+ (BIT_CLEAR_SW18_R1_8821C(x) | BIT_SW18_R1_8821C(v))
#define BIT_SHIFT_C3_L_C3_8821C 1
#define BIT_MASK_C3_L_C3_8821C 0x3
-#define BIT_C3_L_C3_8821C(x) (((x) & BIT_MASK_C3_L_C3_8821C) << BIT_SHIFT_C3_L_C3_8821C)
-#define BIT_GET_C3_L_C3_8821C(x) (((x) >> BIT_SHIFT_C3_L_C3_8821C) & BIT_MASK_C3_L_C3_8821C)
+#define BIT_C3_L_C3_8821C(x) \
+ (((x) & BIT_MASK_C3_L_C3_8821C) << BIT_SHIFT_C3_L_C3_8821C)
+#define BITS_C3_L_C3_8821C (BIT_MASK_C3_L_C3_8821C << BIT_SHIFT_C3_L_C3_8821C)
+#define BIT_CLEAR_C3_L_C3_8821C(x) ((x) & (~BITS_C3_L_C3_8821C))
+#define BIT_GET_C3_L_C3_8821C(x) \
+ (((x) >> BIT_SHIFT_C3_L_C3_8821C) & BIT_MASK_C3_L_C3_8821C)
+#define BIT_SET_C3_L_C3_8821C(x, v) \
+ (BIT_CLEAR_C3_L_C3_8821C(x) | BIT_C3_L_C3_8821C(v))
#define BIT_C2_L_BIT1_8821C BIT(0)
@@ -226,15 +333,27 @@
#define BIT_SHIFT_SPS18_OCP_TH_8821C 16
#define BIT_MASK_SPS18_OCP_TH_8821C 0x7fff
-#define BIT_SPS18_OCP_TH_8821C(x) (((x) & BIT_MASK_SPS18_OCP_TH_8821C) << BIT_SHIFT_SPS18_OCP_TH_8821C)
-#define BIT_GET_SPS18_OCP_TH_8821C(x) (((x) >> BIT_SHIFT_SPS18_OCP_TH_8821C) & BIT_MASK_SPS18_OCP_TH_8821C)
-
+#define BIT_SPS18_OCP_TH_8821C(x) \
+ (((x) & BIT_MASK_SPS18_OCP_TH_8821C) << BIT_SHIFT_SPS18_OCP_TH_8821C)
+#define BITS_SPS18_OCP_TH_8821C \
+ (BIT_MASK_SPS18_OCP_TH_8821C << BIT_SHIFT_SPS18_OCP_TH_8821C)
+#define BIT_CLEAR_SPS18_OCP_TH_8821C(x) ((x) & (~BITS_SPS18_OCP_TH_8821C))
+#define BIT_GET_SPS18_OCP_TH_8821C(x) \
+ (((x) >> BIT_SHIFT_SPS18_OCP_TH_8821C) & BIT_MASK_SPS18_OCP_TH_8821C)
+#define BIT_SET_SPS18_OCP_TH_8821C(x, v) \
+ (BIT_CLEAR_SPS18_OCP_TH_8821C(x) | BIT_SPS18_OCP_TH_8821C(v))
#define BIT_SHIFT_OCP_WINDOW_8821C 0
#define BIT_MASK_OCP_WINDOW_8821C 0xffff
-#define BIT_OCP_WINDOW_8821C(x) (((x) & BIT_MASK_OCP_WINDOW_8821C) << BIT_SHIFT_OCP_WINDOW_8821C)
-#define BIT_GET_OCP_WINDOW_8821C(x) (((x) >> BIT_SHIFT_OCP_WINDOW_8821C) & BIT_MASK_OCP_WINDOW_8821C)
-
+#define BIT_OCP_WINDOW_8821C(x) \
+ (((x) & BIT_MASK_OCP_WINDOW_8821C) << BIT_SHIFT_OCP_WINDOW_8821C)
+#define BITS_OCP_WINDOW_8821C \
+ (BIT_MASK_OCP_WINDOW_8821C << BIT_SHIFT_OCP_WINDOW_8821C)
+#define BIT_CLEAR_OCP_WINDOW_8821C(x) ((x) & (~BITS_OCP_WINDOW_8821C))
+#define BIT_GET_OCP_WINDOW_8821C(x) \
+ (((x) >> BIT_SHIFT_OCP_WINDOW_8821C) & BIT_MASK_OCP_WINDOW_8821C)
+#define BIT_SET_OCP_WINDOW_8821C(x, v) \
+ (BIT_CLEAR_OCP_WINDOW_8821C(x) | BIT_OCP_WINDOW_8821C(v))
/* 2 REG_RSV_CTRL_8821C */
#define BIT_HREG_DBG_8821C BIT(23)
@@ -257,15 +376,29 @@
#define BIT_SHIFT_LPLDH12_RSV_8821C 29
#define BIT_MASK_LPLDH12_RSV_8821C 0x7
-#define BIT_LPLDH12_RSV_8821C(x) (((x) & BIT_MASK_LPLDH12_RSV_8821C) << BIT_SHIFT_LPLDH12_RSV_8821C)
-#define BIT_GET_LPLDH12_RSV_8821C(x) (((x) >> BIT_SHIFT_LPLDH12_RSV_8821C) & BIT_MASK_LPLDH12_RSV_8821C)
+#define BIT_LPLDH12_RSV_8821C(x) \
+ (((x) & BIT_MASK_LPLDH12_RSV_8821C) << BIT_SHIFT_LPLDH12_RSV_8821C)
+#define BITS_LPLDH12_RSV_8821C \
+ (BIT_MASK_LPLDH12_RSV_8821C << BIT_SHIFT_LPLDH12_RSV_8821C)
+#define BIT_CLEAR_LPLDH12_RSV_8821C(x) ((x) & (~BITS_LPLDH12_RSV_8821C))
+#define BIT_GET_LPLDH12_RSV_8821C(x) \
+ (((x) >> BIT_SHIFT_LPLDH12_RSV_8821C) & BIT_MASK_LPLDH12_RSV_8821C)
+#define BIT_SET_LPLDH12_RSV_8821C(x, v) \
+ (BIT_CLEAR_LPLDH12_RSV_8821C(x) | BIT_LPLDH12_RSV_8821C(v))
#define BIT_LPLDH12_SLP_8821C BIT(28)
#define BIT_SHIFT_LPLDH12_VADJ_8821C 24
#define BIT_MASK_LPLDH12_VADJ_8821C 0xf
-#define BIT_LPLDH12_VADJ_8821C(x) (((x) & BIT_MASK_LPLDH12_VADJ_8821C) << BIT_SHIFT_LPLDH12_VADJ_8821C)
-#define BIT_GET_LPLDH12_VADJ_8821C(x) (((x) >> BIT_SHIFT_LPLDH12_VADJ_8821C) & BIT_MASK_LPLDH12_VADJ_8821C)
+#define BIT_LPLDH12_VADJ_8821C(x) \
+ (((x) & BIT_MASK_LPLDH12_VADJ_8821C) << BIT_SHIFT_LPLDH12_VADJ_8821C)
+#define BITS_LPLDH12_VADJ_8821C \
+ (BIT_MASK_LPLDH12_VADJ_8821C << BIT_SHIFT_LPLDH12_VADJ_8821C)
+#define BIT_CLEAR_LPLDH12_VADJ_8821C(x) ((x) & (~BITS_LPLDH12_VADJ_8821C))
+#define BIT_GET_LPLDH12_VADJ_8821C(x) \
+ (((x) >> BIT_SHIFT_LPLDH12_VADJ_8821C) & BIT_MASK_LPLDH12_VADJ_8821C)
+#define BIT_SET_LPLDH12_VADJ_8821C(x, v) \
+ (BIT_CLEAR_LPLDH12_VADJ_8821C(x) | BIT_LPLDH12_VADJ_8821C(v))
#define BIT_PCIE_CALIB_EN_8821C BIT(17)
#define BIT_LDH12_EN_8821C BIT(16)
@@ -290,40 +423,79 @@
#define BIT_SHIFT_XTAL_CAP_XI_8821C 25
#define BIT_MASK_XTAL_CAP_XI_8821C 0x3f
-#define BIT_XTAL_CAP_XI_8821C(x) (((x) & BIT_MASK_XTAL_CAP_XI_8821C) << BIT_SHIFT_XTAL_CAP_XI_8821C)
-#define BIT_GET_XTAL_CAP_XI_8821C(x) (((x) >> BIT_SHIFT_XTAL_CAP_XI_8821C) & BIT_MASK_XTAL_CAP_XI_8821C)
-
+#define BIT_XTAL_CAP_XI_8821C(x) \
+ (((x) & BIT_MASK_XTAL_CAP_XI_8821C) << BIT_SHIFT_XTAL_CAP_XI_8821C)
+#define BITS_XTAL_CAP_XI_8821C \
+ (BIT_MASK_XTAL_CAP_XI_8821C << BIT_SHIFT_XTAL_CAP_XI_8821C)
+#define BIT_CLEAR_XTAL_CAP_XI_8821C(x) ((x) & (~BITS_XTAL_CAP_XI_8821C))
+#define BIT_GET_XTAL_CAP_XI_8821C(x) \
+ (((x) >> BIT_SHIFT_XTAL_CAP_XI_8821C) & BIT_MASK_XTAL_CAP_XI_8821C)
+#define BIT_SET_XTAL_CAP_XI_8821C(x, v) \
+ (BIT_CLEAR_XTAL_CAP_XI_8821C(x) | BIT_XTAL_CAP_XI_8821C(v))
#define BIT_SHIFT_XTAL_DRV_DIGI_8821C 23
#define BIT_MASK_XTAL_DRV_DIGI_8821C 0x3
-#define BIT_XTAL_DRV_DIGI_8821C(x) (((x) & BIT_MASK_XTAL_DRV_DIGI_8821C) << BIT_SHIFT_XTAL_DRV_DIGI_8821C)
-#define BIT_GET_XTAL_DRV_DIGI_8821C(x) (((x) >> BIT_SHIFT_XTAL_DRV_DIGI_8821C) & BIT_MASK_XTAL_DRV_DIGI_8821C)
+#define BIT_XTAL_DRV_DIGI_8821C(x) \
+ (((x) & BIT_MASK_XTAL_DRV_DIGI_8821C) << BIT_SHIFT_XTAL_DRV_DIGI_8821C)
+#define BITS_XTAL_DRV_DIGI_8821C \
+ (BIT_MASK_XTAL_DRV_DIGI_8821C << BIT_SHIFT_XTAL_DRV_DIGI_8821C)
+#define BIT_CLEAR_XTAL_DRV_DIGI_8821C(x) ((x) & (~BITS_XTAL_DRV_DIGI_8821C))
+#define BIT_GET_XTAL_DRV_DIGI_8821C(x) \
+ (((x) >> BIT_SHIFT_XTAL_DRV_DIGI_8821C) & BIT_MASK_XTAL_DRV_DIGI_8821C)
+#define BIT_SET_XTAL_DRV_DIGI_8821C(x, v) \
+ (BIT_CLEAR_XTAL_DRV_DIGI_8821C(x) | BIT_XTAL_DRV_DIGI_8821C(v))
#define BIT_XTAL_DRV_USB_BIT1_8821C BIT(22)
#define BIT_SHIFT_MAC_CLK_SEL_8821C 20
#define BIT_MASK_MAC_CLK_SEL_8821C 0x3
-#define BIT_MAC_CLK_SEL_8821C(x) (((x) & BIT_MASK_MAC_CLK_SEL_8821C) << BIT_SHIFT_MAC_CLK_SEL_8821C)
-#define BIT_GET_MAC_CLK_SEL_8821C(x) (((x) >> BIT_SHIFT_MAC_CLK_SEL_8821C) & BIT_MASK_MAC_CLK_SEL_8821C)
+#define BIT_MAC_CLK_SEL_8821C(x) \
+ (((x) & BIT_MASK_MAC_CLK_SEL_8821C) << BIT_SHIFT_MAC_CLK_SEL_8821C)
+#define BITS_MAC_CLK_SEL_8821C \
+ (BIT_MASK_MAC_CLK_SEL_8821C << BIT_SHIFT_MAC_CLK_SEL_8821C)
+#define BIT_CLEAR_MAC_CLK_SEL_8821C(x) ((x) & (~BITS_MAC_CLK_SEL_8821C))
+#define BIT_GET_MAC_CLK_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_MAC_CLK_SEL_8821C) & BIT_MASK_MAC_CLK_SEL_8821C)
+#define BIT_SET_MAC_CLK_SEL_8821C(x, v) \
+ (BIT_CLEAR_MAC_CLK_SEL_8821C(x) | BIT_MAC_CLK_SEL_8821C(v))
#define BIT_XTAL_DRV_USB_BIT0_8821C BIT(19)
#define BIT_SHIFT_XTAL_DRV_AFE_8821C 17
#define BIT_MASK_XTAL_DRV_AFE_8821C 0x3
-#define BIT_XTAL_DRV_AFE_8821C(x) (((x) & BIT_MASK_XTAL_DRV_AFE_8821C) << BIT_SHIFT_XTAL_DRV_AFE_8821C)
-#define BIT_GET_XTAL_DRV_AFE_8821C(x) (((x) >> BIT_SHIFT_XTAL_DRV_AFE_8821C) & BIT_MASK_XTAL_DRV_AFE_8821C)
-
+#define BIT_XTAL_DRV_AFE_8821C(x) \
+ (((x) & BIT_MASK_XTAL_DRV_AFE_8821C) << BIT_SHIFT_XTAL_DRV_AFE_8821C)
+#define BITS_XTAL_DRV_AFE_8821C \
+ (BIT_MASK_XTAL_DRV_AFE_8821C << BIT_SHIFT_XTAL_DRV_AFE_8821C)
+#define BIT_CLEAR_XTAL_DRV_AFE_8821C(x) ((x) & (~BITS_XTAL_DRV_AFE_8821C))
+#define BIT_GET_XTAL_DRV_AFE_8821C(x) \
+ (((x) >> BIT_SHIFT_XTAL_DRV_AFE_8821C) & BIT_MASK_XTAL_DRV_AFE_8821C)
+#define BIT_SET_XTAL_DRV_AFE_8821C(x, v) \
+ (BIT_CLEAR_XTAL_DRV_AFE_8821C(x) | BIT_XTAL_DRV_AFE_8821C(v))
#define BIT_SHIFT_XTAL_DRV_RF2_8821C 15
#define BIT_MASK_XTAL_DRV_RF2_8821C 0x3
-#define BIT_XTAL_DRV_RF2_8821C(x) (((x) & BIT_MASK_XTAL_DRV_RF2_8821C) << BIT_SHIFT_XTAL_DRV_RF2_8821C)
-#define BIT_GET_XTAL_DRV_RF2_8821C(x) (((x) >> BIT_SHIFT_XTAL_DRV_RF2_8821C) & BIT_MASK_XTAL_DRV_RF2_8821C)
-
+#define BIT_XTAL_DRV_RF2_8821C(x) \
+ (((x) & BIT_MASK_XTAL_DRV_RF2_8821C) << BIT_SHIFT_XTAL_DRV_RF2_8821C)
+#define BITS_XTAL_DRV_RF2_8821C \
+ (BIT_MASK_XTAL_DRV_RF2_8821C << BIT_SHIFT_XTAL_DRV_RF2_8821C)
+#define BIT_CLEAR_XTAL_DRV_RF2_8821C(x) ((x) & (~BITS_XTAL_DRV_RF2_8821C))
+#define BIT_GET_XTAL_DRV_RF2_8821C(x) \
+ (((x) >> BIT_SHIFT_XTAL_DRV_RF2_8821C) & BIT_MASK_XTAL_DRV_RF2_8821C)
+#define BIT_SET_XTAL_DRV_RF2_8821C(x, v) \
+ (BIT_CLEAR_XTAL_DRV_RF2_8821C(x) | BIT_XTAL_DRV_RF2_8821C(v))
#define BIT_SHIFT_XTAL_DRV_RF1_8821C 13
#define BIT_MASK_XTAL_DRV_RF1_8821C 0x3
-#define BIT_XTAL_DRV_RF1_8821C(x) (((x) & BIT_MASK_XTAL_DRV_RF1_8821C) << BIT_SHIFT_XTAL_DRV_RF1_8821C)
-#define BIT_GET_XTAL_DRV_RF1_8821C(x) (((x) >> BIT_SHIFT_XTAL_DRV_RF1_8821C) & BIT_MASK_XTAL_DRV_RF1_8821C)
+#define BIT_XTAL_DRV_RF1_8821C(x) \
+ (((x) & BIT_MASK_XTAL_DRV_RF1_8821C) << BIT_SHIFT_XTAL_DRV_RF1_8821C)
+#define BITS_XTAL_DRV_RF1_8821C \
+ (BIT_MASK_XTAL_DRV_RF1_8821C << BIT_SHIFT_XTAL_DRV_RF1_8821C)
+#define BIT_CLEAR_XTAL_DRV_RF1_8821C(x) ((x) & (~BITS_XTAL_DRV_RF1_8821C))
+#define BIT_GET_XTAL_DRV_RF1_8821C(x) \
+ (((x) >> BIT_SHIFT_XTAL_DRV_RF1_8821C) & BIT_MASK_XTAL_DRV_RF1_8821C)
+#define BIT_SET_XTAL_DRV_RF1_8821C(x, v) \
+ (BIT_CLEAR_XTAL_DRV_RF1_8821C(x) | BIT_XTAL_DRV_RF1_8821C(v))
#define BIT_XTAL_DELAY_DIGI_8821C BIT(12)
#define BIT_XTAL_DELAY_USB_8821C BIT(11)
@@ -331,22 +503,42 @@
#define BIT_SHIFT_XTAL_LDO_VREF_8821C 7
#define BIT_MASK_XTAL_LDO_VREF_8821C 0x7
-#define BIT_XTAL_LDO_VREF_8821C(x) (((x) & BIT_MASK_XTAL_LDO_VREF_8821C) << BIT_SHIFT_XTAL_LDO_VREF_8821C)
-#define BIT_GET_XTAL_LDO_VREF_8821C(x) (((x) >> BIT_SHIFT_XTAL_LDO_VREF_8821C) & BIT_MASK_XTAL_LDO_VREF_8821C)
+#define BIT_XTAL_LDO_VREF_8821C(x) \
+ (((x) & BIT_MASK_XTAL_LDO_VREF_8821C) << BIT_SHIFT_XTAL_LDO_VREF_8821C)
+#define BITS_XTAL_LDO_VREF_8821C \
+ (BIT_MASK_XTAL_LDO_VREF_8821C << BIT_SHIFT_XTAL_LDO_VREF_8821C)
+#define BIT_CLEAR_XTAL_LDO_VREF_8821C(x) ((x) & (~BITS_XTAL_LDO_VREF_8821C))
+#define BIT_GET_XTAL_LDO_VREF_8821C(x) \
+ (((x) >> BIT_SHIFT_XTAL_LDO_VREF_8821C) & BIT_MASK_XTAL_LDO_VREF_8821C)
+#define BIT_SET_XTAL_LDO_VREF_8821C(x, v) \
+ (BIT_CLEAR_XTAL_LDO_VREF_8821C(x) | BIT_XTAL_LDO_VREF_8821C(v))
#define BIT_XTAL_XQSEL_RF_8821C BIT(6)
#define BIT_XTAL_XQSEL_8821C BIT(5)
#define BIT_SHIFT_XTAL_GMN_V2_8821C 3
#define BIT_MASK_XTAL_GMN_V2_8821C 0x3
-#define BIT_XTAL_GMN_V2_8821C(x) (((x) & BIT_MASK_XTAL_GMN_V2_8821C) << BIT_SHIFT_XTAL_GMN_V2_8821C)
-#define BIT_GET_XTAL_GMN_V2_8821C(x) (((x) >> BIT_SHIFT_XTAL_GMN_V2_8821C) & BIT_MASK_XTAL_GMN_V2_8821C)
-
+#define BIT_XTAL_GMN_V2_8821C(x) \
+ (((x) & BIT_MASK_XTAL_GMN_V2_8821C) << BIT_SHIFT_XTAL_GMN_V2_8821C)
+#define BITS_XTAL_GMN_V2_8821C \
+ (BIT_MASK_XTAL_GMN_V2_8821C << BIT_SHIFT_XTAL_GMN_V2_8821C)
+#define BIT_CLEAR_XTAL_GMN_V2_8821C(x) ((x) & (~BITS_XTAL_GMN_V2_8821C))
+#define BIT_GET_XTAL_GMN_V2_8821C(x) \
+ (((x) >> BIT_SHIFT_XTAL_GMN_V2_8821C) & BIT_MASK_XTAL_GMN_V2_8821C)
+#define BIT_SET_XTAL_GMN_V2_8821C(x, v) \
+ (BIT_CLEAR_XTAL_GMN_V2_8821C(x) | BIT_XTAL_GMN_V2_8821C(v))
#define BIT_SHIFT_XTAL_GMP_V2_8821C 1
#define BIT_MASK_XTAL_GMP_V2_8821C 0x3
-#define BIT_XTAL_GMP_V2_8821C(x) (((x) & BIT_MASK_XTAL_GMP_V2_8821C) << BIT_SHIFT_XTAL_GMP_V2_8821C)
-#define BIT_GET_XTAL_GMP_V2_8821C(x) (((x) >> BIT_SHIFT_XTAL_GMP_V2_8821C) & BIT_MASK_XTAL_GMP_V2_8821C)
+#define BIT_XTAL_GMP_V2_8821C(x) \
+ (((x) & BIT_MASK_XTAL_GMP_V2_8821C) << BIT_SHIFT_XTAL_GMP_V2_8821C)
+#define BITS_XTAL_GMP_V2_8821C \
+ (BIT_MASK_XTAL_GMP_V2_8821C << BIT_SHIFT_XTAL_GMP_V2_8821C)
+#define BIT_CLEAR_XTAL_GMP_V2_8821C(x) ((x) & (~BITS_XTAL_GMP_V2_8821C))
+#define BIT_GET_XTAL_GMP_V2_8821C(x) \
+ (((x) >> BIT_SHIFT_XTAL_GMP_V2_8821C) & BIT_MASK_XTAL_GMP_V2_8821C)
+#define BIT_SET_XTAL_GMP_V2_8821C(x, v) \
+ (BIT_CLEAR_XTAL_GMP_V2_8821C(x) | BIT_XTAL_GMP_V2_8821C(v))
#define BIT_XTAL_EN_8821C BIT(0)
@@ -354,33 +546,63 @@
#define BIT_SHIFT_REG_C3_V4_8821C 30
#define BIT_MASK_REG_C3_V4_8821C 0x3
-#define BIT_REG_C3_V4_8821C(x) (((x) & BIT_MASK_REG_C3_V4_8821C) << BIT_SHIFT_REG_C3_V4_8821C)
-#define BIT_GET_REG_C3_V4_8821C(x) (((x) >> BIT_SHIFT_REG_C3_V4_8821C) & BIT_MASK_REG_C3_V4_8821C)
+#define BIT_REG_C3_V4_8821C(x) \
+ (((x) & BIT_MASK_REG_C3_V4_8821C) << BIT_SHIFT_REG_C3_V4_8821C)
+#define BITS_REG_C3_V4_8821C \
+ (BIT_MASK_REG_C3_V4_8821C << BIT_SHIFT_REG_C3_V4_8821C)
+#define BIT_CLEAR_REG_C3_V4_8821C(x) ((x) & (~BITS_REG_C3_V4_8821C))
+#define BIT_GET_REG_C3_V4_8821C(x) \
+ (((x) >> BIT_SHIFT_REG_C3_V4_8821C) & BIT_MASK_REG_C3_V4_8821C)
+#define BIT_SET_REG_C3_V4_8821C(x, v) \
+ (BIT_CLEAR_REG_C3_V4_8821C(x) | BIT_REG_C3_V4_8821C(v))
#define BIT_REG_CP_BIT1_8821C BIT(29)
#define BIT_SHIFT_REG_RS_V4_8821C 26
#define BIT_MASK_REG_RS_V4_8821C 0x7
-#define BIT_REG_RS_V4_8821C(x) (((x) & BIT_MASK_REG_RS_V4_8821C) << BIT_SHIFT_REG_RS_V4_8821C)
-#define BIT_GET_REG_RS_V4_8821C(x) (((x) >> BIT_SHIFT_REG_RS_V4_8821C) & BIT_MASK_REG_RS_V4_8821C)
-
+#define BIT_REG_RS_V4_8821C(x) \
+ (((x) & BIT_MASK_REG_RS_V4_8821C) << BIT_SHIFT_REG_RS_V4_8821C)
+#define BITS_REG_RS_V4_8821C \
+ (BIT_MASK_REG_RS_V4_8821C << BIT_SHIFT_REG_RS_V4_8821C)
+#define BIT_CLEAR_REG_RS_V4_8821C(x) ((x) & (~BITS_REG_RS_V4_8821C))
+#define BIT_GET_REG_RS_V4_8821C(x) \
+ (((x) >> BIT_SHIFT_REG_RS_V4_8821C) & BIT_MASK_REG_RS_V4_8821C)
+#define BIT_SET_REG_RS_V4_8821C(x, v) \
+ (BIT_CLEAR_REG_RS_V4_8821C(x) | BIT_REG_RS_V4_8821C(v))
#define BIT_SHIFT_REG__CS_8821C 24
#define BIT_MASK_REG__CS_8821C 0x3
-#define BIT_REG__CS_8821C(x) (((x) & BIT_MASK_REG__CS_8821C) << BIT_SHIFT_REG__CS_8821C)
-#define BIT_GET_REG__CS_8821C(x) (((x) >> BIT_SHIFT_REG__CS_8821C) & BIT_MASK_REG__CS_8821C)
-
+#define BIT_REG__CS_8821C(x) \
+ (((x) & BIT_MASK_REG__CS_8821C) << BIT_SHIFT_REG__CS_8821C)
+#define BITS_REG__CS_8821C (BIT_MASK_REG__CS_8821C << BIT_SHIFT_REG__CS_8821C)
+#define BIT_CLEAR_REG__CS_8821C(x) ((x) & (~BITS_REG__CS_8821C))
+#define BIT_GET_REG__CS_8821C(x) \
+ (((x) >> BIT_SHIFT_REG__CS_8821C) & BIT_MASK_REG__CS_8821C)
+#define BIT_SET_REG__CS_8821C(x, v) \
+ (BIT_CLEAR_REG__CS_8821C(x) | BIT_REG__CS_8821C(v))
#define BIT_SHIFT_REG_CP_OFFSET_8821C 21
#define BIT_MASK_REG_CP_OFFSET_8821C 0x7
-#define BIT_REG_CP_OFFSET_8821C(x) (((x) & BIT_MASK_REG_CP_OFFSET_8821C) << BIT_SHIFT_REG_CP_OFFSET_8821C)
-#define BIT_GET_REG_CP_OFFSET_8821C(x) (((x) >> BIT_SHIFT_REG_CP_OFFSET_8821C) & BIT_MASK_REG_CP_OFFSET_8821C)
-
+#define BIT_REG_CP_OFFSET_8821C(x) \
+ (((x) & BIT_MASK_REG_CP_OFFSET_8821C) << BIT_SHIFT_REG_CP_OFFSET_8821C)
+#define BITS_REG_CP_OFFSET_8821C \
+ (BIT_MASK_REG_CP_OFFSET_8821C << BIT_SHIFT_REG_CP_OFFSET_8821C)
+#define BIT_CLEAR_REG_CP_OFFSET_8821C(x) ((x) & (~BITS_REG_CP_OFFSET_8821C))
+#define BIT_GET_REG_CP_OFFSET_8821C(x) \
+ (((x) >> BIT_SHIFT_REG_CP_OFFSET_8821C) & BIT_MASK_REG_CP_OFFSET_8821C)
+#define BIT_SET_REG_CP_OFFSET_8821C(x, v) \
+ (BIT_CLEAR_REG_CP_OFFSET_8821C(x) | BIT_REG_CP_OFFSET_8821C(v))
#define BIT_SHIFT_CP_BIAS_8821C 18
#define BIT_MASK_CP_BIAS_8821C 0x7
-#define BIT_CP_BIAS_8821C(x) (((x) & BIT_MASK_CP_BIAS_8821C) << BIT_SHIFT_CP_BIAS_8821C)
-#define BIT_GET_CP_BIAS_8821C(x) (((x) >> BIT_SHIFT_CP_BIAS_8821C) & BIT_MASK_CP_BIAS_8821C)
+#define BIT_CP_BIAS_8821C(x) \
+ (((x) & BIT_MASK_CP_BIAS_8821C) << BIT_SHIFT_CP_BIAS_8821C)
+#define BITS_CP_BIAS_8821C (BIT_MASK_CP_BIAS_8821C << BIT_SHIFT_CP_BIAS_8821C)
+#define BIT_CLEAR_CP_BIAS_8821C(x) ((x) & (~BITS_CP_BIAS_8821C))
+#define BIT_GET_CP_BIAS_8821C(x) \
+ (((x) >> BIT_SHIFT_CP_BIAS_8821C) & BIT_MASK_CP_BIAS_8821C)
+#define BIT_SET_CP_BIAS_8821C(x, v) \
+ (BIT_CLEAR_CP_BIAS_8821C(x) | BIT_CP_BIAS_8821C(v))
#define BIT_REG_IDOUBLE_V2_8821C BIT(17)
#define BIT_EN_SYN_8821C BIT(16)
@@ -388,27 +610,50 @@
#define BIT_SHIFT_MCCO_8821C 14
#define BIT_MASK_MCCO_8821C 0x3
#define BIT_MCCO_8821C(x) (((x) & BIT_MASK_MCCO_8821C) << BIT_SHIFT_MCCO_8821C)
-#define BIT_GET_MCCO_8821C(x) (((x) >> BIT_SHIFT_MCCO_8821C) & BIT_MASK_MCCO_8821C)
-
+#define BITS_MCCO_8821C (BIT_MASK_MCCO_8821C << BIT_SHIFT_MCCO_8821C)
+#define BIT_CLEAR_MCCO_8821C(x) ((x) & (~BITS_MCCO_8821C))
+#define BIT_GET_MCCO_8821C(x) \
+ (((x) >> BIT_SHIFT_MCCO_8821C) & BIT_MASK_MCCO_8821C)
+#define BIT_SET_MCCO_8821C(x, v) (BIT_CLEAR_MCCO_8821C(x) | BIT_MCCO_8821C(v))
#define BIT_SHIFT_REG_LDO_SEL_8821C 12
#define BIT_MASK_REG_LDO_SEL_8821C 0x3
-#define BIT_REG_LDO_SEL_8821C(x) (((x) & BIT_MASK_REG_LDO_SEL_8821C) << BIT_SHIFT_REG_LDO_SEL_8821C)
-#define BIT_GET_REG_LDO_SEL_8821C(x) (((x) >> BIT_SHIFT_REG_LDO_SEL_8821C) & BIT_MASK_REG_LDO_SEL_8821C)
+#define BIT_REG_LDO_SEL_8821C(x) \
+ (((x) & BIT_MASK_REG_LDO_SEL_8821C) << BIT_SHIFT_REG_LDO_SEL_8821C)
+#define BITS_REG_LDO_SEL_8821C \
+ (BIT_MASK_REG_LDO_SEL_8821C << BIT_SHIFT_REG_LDO_SEL_8821C)
+#define BIT_CLEAR_REG_LDO_SEL_8821C(x) ((x) & (~BITS_REG_LDO_SEL_8821C))
+#define BIT_GET_REG_LDO_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_REG_LDO_SEL_8821C) & BIT_MASK_REG_LDO_SEL_8821C)
+#define BIT_SET_REG_LDO_SEL_8821C(x, v) \
+ (BIT_CLEAR_REG_LDO_SEL_8821C(x) | BIT_REG_LDO_SEL_8821C(v))
#define BIT_REG_KVCO_V2_8821C BIT(10)
#define BIT_AGPIO_GPO_8821C BIT(9)
#define BIT_SHIFT_AGPIO_DRV_8821C 7
#define BIT_MASK_AGPIO_DRV_8821C 0x3
-#define BIT_AGPIO_DRV_8821C(x) (((x) & BIT_MASK_AGPIO_DRV_8821C) << BIT_SHIFT_AGPIO_DRV_8821C)
-#define BIT_GET_AGPIO_DRV_8821C(x) (((x) >> BIT_SHIFT_AGPIO_DRV_8821C) & BIT_MASK_AGPIO_DRV_8821C)
-
+#define BIT_AGPIO_DRV_8821C(x) \
+ (((x) & BIT_MASK_AGPIO_DRV_8821C) << BIT_SHIFT_AGPIO_DRV_8821C)
+#define BITS_AGPIO_DRV_8821C \
+ (BIT_MASK_AGPIO_DRV_8821C << BIT_SHIFT_AGPIO_DRV_8821C)
+#define BIT_CLEAR_AGPIO_DRV_8821C(x) ((x) & (~BITS_AGPIO_DRV_8821C))
+#define BIT_GET_AGPIO_DRV_8821C(x) \
+ (((x) >> BIT_SHIFT_AGPIO_DRV_8821C) & BIT_MASK_AGPIO_DRV_8821C)
+#define BIT_SET_AGPIO_DRV_8821C(x, v) \
+ (BIT_CLEAR_AGPIO_DRV_8821C(x) | BIT_AGPIO_DRV_8821C(v))
#define BIT_SHIFT_XTAL_CAP_XO_8821C 1
#define BIT_MASK_XTAL_CAP_XO_8821C 0x3f
-#define BIT_XTAL_CAP_XO_8821C(x) (((x) & BIT_MASK_XTAL_CAP_XO_8821C) << BIT_SHIFT_XTAL_CAP_XO_8821C)
-#define BIT_GET_XTAL_CAP_XO_8821C(x) (((x) >> BIT_SHIFT_XTAL_CAP_XO_8821C) & BIT_MASK_XTAL_CAP_XO_8821C)
+#define BIT_XTAL_CAP_XO_8821C(x) \
+ (((x) & BIT_MASK_XTAL_CAP_XO_8821C) << BIT_SHIFT_XTAL_CAP_XO_8821C)
+#define BITS_XTAL_CAP_XO_8821C \
+ (BIT_MASK_XTAL_CAP_XO_8821C << BIT_SHIFT_XTAL_CAP_XO_8821C)
+#define BIT_CLEAR_XTAL_CAP_XO_8821C(x) ((x) & (~BITS_XTAL_CAP_XO_8821C))
+#define BIT_GET_XTAL_CAP_XO_8821C(x) \
+ (((x) >> BIT_SHIFT_XTAL_CAP_XO_8821C) & BIT_MASK_XTAL_CAP_XO_8821C)
+#define BIT_SET_XTAL_CAP_XO_8821C(x, v) \
+ (BIT_CLEAR_XTAL_CAP_XO_8821C(x) | BIT_XTAL_CAP_XO_8821C(v))
#define BIT_POW_PLL_8821C BIT(0)
@@ -417,7 +662,10 @@
#define BIT_SHIFT_PS_8821C 7
#define BIT_MASK_PS_8821C 0x7
#define BIT_PS_8821C(x) (((x) & BIT_MASK_PS_8821C) << BIT_SHIFT_PS_8821C)
+#define BITS_PS_8821C (BIT_MASK_PS_8821C << BIT_SHIFT_PS_8821C)
+#define BIT_CLEAR_PS_8821C(x) ((x) & (~BITS_PS_8821C))
#define BIT_GET_PS_8821C(x) (((x) >> BIT_SHIFT_PS_8821C) & BIT_MASK_PS_8821C)
+#define BIT_SET_PS_8821C(x, v) (BIT_CLEAR_PS_8821C(x) | BIT_PS_8821C(v))
#define BIT_PSEN_8821C BIT(6)
#define BIT_DOGENB_8821C BIT(5)
@@ -425,8 +673,15 @@
#define BIT_SHIFT_REG_R3_V4_8821C 1
#define BIT_MASK_REG_R3_V4_8821C 0x7
-#define BIT_REG_R3_V4_8821C(x) (((x) & BIT_MASK_REG_R3_V4_8821C) << BIT_SHIFT_REG_R3_V4_8821C)
-#define BIT_GET_REG_R3_V4_8821C(x) (((x) >> BIT_SHIFT_REG_R3_V4_8821C) & BIT_MASK_REG_R3_V4_8821C)
+#define BIT_REG_R3_V4_8821C(x) \
+ (((x) & BIT_MASK_REG_R3_V4_8821C) << BIT_SHIFT_REG_R3_V4_8821C)
+#define BITS_REG_R3_V4_8821C \
+ (BIT_MASK_REG_R3_V4_8821C << BIT_SHIFT_REG_R3_V4_8821C)
+#define BIT_CLEAR_REG_R3_V4_8821C(x) ((x) & (~BITS_REG_R3_V4_8821C))
+#define BIT_GET_REG_R3_V4_8821C(x) \
+ (((x) >> BIT_SHIFT_REG_R3_V4_8821C) & BIT_MASK_REG_R3_V4_8821C)
+#define BIT_SET_REG_R3_V4_8821C(x, v) \
+ (BIT_CLEAR_REG_R3_V4_8821C(x) | BIT_REG_R3_V4_8821C(v))
#define BIT_REG_CP_BIT0_8821C BIT(0)
@@ -435,90 +690,172 @@
#define BIT_SHIFT_EF_PGPD_8821C 28
#define BIT_MASK_EF_PGPD_8821C 0x7
-#define BIT_EF_PGPD_8821C(x) (((x) & BIT_MASK_EF_PGPD_8821C) << BIT_SHIFT_EF_PGPD_8821C)
-#define BIT_GET_EF_PGPD_8821C(x) (((x) >> BIT_SHIFT_EF_PGPD_8821C) & BIT_MASK_EF_PGPD_8821C)
-
+#define BIT_EF_PGPD_8821C(x) \
+ (((x) & BIT_MASK_EF_PGPD_8821C) << BIT_SHIFT_EF_PGPD_8821C)
+#define BITS_EF_PGPD_8821C (BIT_MASK_EF_PGPD_8821C << BIT_SHIFT_EF_PGPD_8821C)
+#define BIT_CLEAR_EF_PGPD_8821C(x) ((x) & (~BITS_EF_PGPD_8821C))
+#define BIT_GET_EF_PGPD_8821C(x) \
+ (((x) >> BIT_SHIFT_EF_PGPD_8821C) & BIT_MASK_EF_PGPD_8821C)
+#define BIT_SET_EF_PGPD_8821C(x, v) \
+ (BIT_CLEAR_EF_PGPD_8821C(x) | BIT_EF_PGPD_8821C(v))
#define BIT_SHIFT_EF_RDT_8821C 24
#define BIT_MASK_EF_RDT_8821C 0xf
-#define BIT_EF_RDT_8821C(x) (((x) & BIT_MASK_EF_RDT_8821C) << BIT_SHIFT_EF_RDT_8821C)
-#define BIT_GET_EF_RDT_8821C(x) (((x) >> BIT_SHIFT_EF_RDT_8821C) & BIT_MASK_EF_RDT_8821C)
-
+#define BIT_EF_RDT_8821C(x) \
+ (((x) & BIT_MASK_EF_RDT_8821C) << BIT_SHIFT_EF_RDT_8821C)
+#define BITS_EF_RDT_8821C (BIT_MASK_EF_RDT_8821C << BIT_SHIFT_EF_RDT_8821C)
+#define BIT_CLEAR_EF_RDT_8821C(x) ((x) & (~BITS_EF_RDT_8821C))
+#define BIT_GET_EF_RDT_8821C(x) \
+ (((x) >> BIT_SHIFT_EF_RDT_8821C) & BIT_MASK_EF_RDT_8821C)
+#define BIT_SET_EF_RDT_8821C(x, v) \
+ (BIT_CLEAR_EF_RDT_8821C(x) | BIT_EF_RDT_8821C(v))
#define BIT_SHIFT_EF_PGTS_8821C 20
#define BIT_MASK_EF_PGTS_8821C 0xf
-#define BIT_EF_PGTS_8821C(x) (((x) & BIT_MASK_EF_PGTS_8821C) << BIT_SHIFT_EF_PGTS_8821C)
-#define BIT_GET_EF_PGTS_8821C(x) (((x) >> BIT_SHIFT_EF_PGTS_8821C) & BIT_MASK_EF_PGTS_8821C)
+#define BIT_EF_PGTS_8821C(x) \
+ (((x) & BIT_MASK_EF_PGTS_8821C) << BIT_SHIFT_EF_PGTS_8821C)
+#define BITS_EF_PGTS_8821C (BIT_MASK_EF_PGTS_8821C << BIT_SHIFT_EF_PGTS_8821C)
+#define BIT_CLEAR_EF_PGTS_8821C(x) ((x) & (~BITS_EF_PGTS_8821C))
+#define BIT_GET_EF_PGTS_8821C(x) \
+ (((x) >> BIT_SHIFT_EF_PGTS_8821C) & BIT_MASK_EF_PGTS_8821C)
+#define BIT_SET_EF_PGTS_8821C(x, v) \
+ (BIT_CLEAR_EF_PGTS_8821C(x) | BIT_EF_PGTS_8821C(v))
#define BIT_EF_PDWN_8821C BIT(19)
#define BIT_EF_ALDEN_8821C BIT(18)
#define BIT_SHIFT_EF_ADDR_8821C 8
#define BIT_MASK_EF_ADDR_8821C 0x3ff
-#define BIT_EF_ADDR_8821C(x) (((x) & BIT_MASK_EF_ADDR_8821C) << BIT_SHIFT_EF_ADDR_8821C)
-#define BIT_GET_EF_ADDR_8821C(x) (((x) >> BIT_SHIFT_EF_ADDR_8821C) & BIT_MASK_EF_ADDR_8821C)
-
+#define BIT_EF_ADDR_8821C(x) \
+ (((x) & BIT_MASK_EF_ADDR_8821C) << BIT_SHIFT_EF_ADDR_8821C)
+#define BITS_EF_ADDR_8821C (BIT_MASK_EF_ADDR_8821C << BIT_SHIFT_EF_ADDR_8821C)
+#define BIT_CLEAR_EF_ADDR_8821C(x) ((x) & (~BITS_EF_ADDR_8821C))
+#define BIT_GET_EF_ADDR_8821C(x) \
+ (((x) >> BIT_SHIFT_EF_ADDR_8821C) & BIT_MASK_EF_ADDR_8821C)
+#define BIT_SET_EF_ADDR_8821C(x, v) \
+ (BIT_CLEAR_EF_ADDR_8821C(x) | BIT_EF_ADDR_8821C(v))
#define BIT_SHIFT_EF_DATA_8821C 0
#define BIT_MASK_EF_DATA_8821C 0xff
-#define BIT_EF_DATA_8821C(x) (((x) & BIT_MASK_EF_DATA_8821C) << BIT_SHIFT_EF_DATA_8821C)
-#define BIT_GET_EF_DATA_8821C(x) (((x) >> BIT_SHIFT_EF_DATA_8821C) & BIT_MASK_EF_DATA_8821C)
-
+#define BIT_EF_DATA_8821C(x) \
+ (((x) & BIT_MASK_EF_DATA_8821C) << BIT_SHIFT_EF_DATA_8821C)
+#define BITS_EF_DATA_8821C (BIT_MASK_EF_DATA_8821C << BIT_SHIFT_EF_DATA_8821C)
+#define BIT_CLEAR_EF_DATA_8821C(x) ((x) & (~BITS_EF_DATA_8821C))
+#define BIT_GET_EF_DATA_8821C(x) \
+ (((x) >> BIT_SHIFT_EF_DATA_8821C) & BIT_MASK_EF_DATA_8821C)
+#define BIT_SET_EF_DATA_8821C(x, v) \
+ (BIT_CLEAR_EF_DATA_8821C(x) | BIT_EF_DATA_8821C(v))
/* 2 REG_LDO_EFUSE_CTRL_8821C */
#define BIT_LDOE25_EN_8821C BIT(31)
#define BIT_SHIFT_LDOE25_V12ADJ_L_8821C 27
#define BIT_MASK_LDOE25_V12ADJ_L_8821C 0xf
-#define BIT_LDOE25_V12ADJ_L_8821C(x) (((x) & BIT_MASK_LDOE25_V12ADJ_L_8821C) << BIT_SHIFT_LDOE25_V12ADJ_L_8821C)
-#define BIT_GET_LDOE25_V12ADJ_L_8821C(x) (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_8821C) & BIT_MASK_LDOE25_V12ADJ_L_8821C)
+#define BIT_LDOE25_V12ADJ_L_8821C(x) \
+ (((x) & BIT_MASK_LDOE25_V12ADJ_L_8821C) \
+ << BIT_SHIFT_LDOE25_V12ADJ_L_8821C)
+#define BITS_LDOE25_V12ADJ_L_8821C \
+ (BIT_MASK_LDOE25_V12ADJ_L_8821C << BIT_SHIFT_LDOE25_V12ADJ_L_8821C)
+#define BIT_CLEAR_LDOE25_V12ADJ_L_8821C(x) ((x) & (~BITS_LDOE25_V12ADJ_L_8821C))
+#define BIT_GET_LDOE25_V12ADJ_L_8821C(x) \
+ (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_8821C) & \
+ BIT_MASK_LDOE25_V12ADJ_L_8821C)
+#define BIT_SET_LDOE25_V12ADJ_L_8821C(x, v) \
+ (BIT_CLEAR_LDOE25_V12ADJ_L_8821C(x) | BIT_LDOE25_V12ADJ_L_8821C(v))
#define BIT_EF_CRES_SEL_8821C BIT(26)
#define BIT_SHIFT_EF_SCAN_START_V1_8821C 16
#define BIT_MASK_EF_SCAN_START_V1_8821C 0x3ff
-#define BIT_EF_SCAN_START_V1_8821C(x) (((x) & BIT_MASK_EF_SCAN_START_V1_8821C) << BIT_SHIFT_EF_SCAN_START_V1_8821C)
-#define BIT_GET_EF_SCAN_START_V1_8821C(x) (((x) >> BIT_SHIFT_EF_SCAN_START_V1_8821C) & BIT_MASK_EF_SCAN_START_V1_8821C)
-
+#define BIT_EF_SCAN_START_V1_8821C(x) \
+ (((x) & BIT_MASK_EF_SCAN_START_V1_8821C) \
+ << BIT_SHIFT_EF_SCAN_START_V1_8821C)
+#define BITS_EF_SCAN_START_V1_8821C \
+ (BIT_MASK_EF_SCAN_START_V1_8821C << BIT_SHIFT_EF_SCAN_START_V1_8821C)
+#define BIT_CLEAR_EF_SCAN_START_V1_8821C(x) \
+ ((x) & (~BITS_EF_SCAN_START_V1_8821C))
+#define BIT_GET_EF_SCAN_START_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_EF_SCAN_START_V1_8821C) & \
+ BIT_MASK_EF_SCAN_START_V1_8821C)
+#define BIT_SET_EF_SCAN_START_V1_8821C(x, v) \
+ (BIT_CLEAR_EF_SCAN_START_V1_8821C(x) | BIT_EF_SCAN_START_V1_8821C(v))
#define BIT_SHIFT_EF_SCAN_END_8821C 12
#define BIT_MASK_EF_SCAN_END_8821C 0xf
-#define BIT_EF_SCAN_END_8821C(x) (((x) & BIT_MASK_EF_SCAN_END_8821C) << BIT_SHIFT_EF_SCAN_END_8821C)
-#define BIT_GET_EF_SCAN_END_8821C(x) (((x) >> BIT_SHIFT_EF_SCAN_END_8821C) & BIT_MASK_EF_SCAN_END_8821C)
+#define BIT_EF_SCAN_END_8821C(x) \
+ (((x) & BIT_MASK_EF_SCAN_END_8821C) << BIT_SHIFT_EF_SCAN_END_8821C)
+#define BITS_EF_SCAN_END_8821C \
+ (BIT_MASK_EF_SCAN_END_8821C << BIT_SHIFT_EF_SCAN_END_8821C)
+#define BIT_CLEAR_EF_SCAN_END_8821C(x) ((x) & (~BITS_EF_SCAN_END_8821C))
+#define BIT_GET_EF_SCAN_END_8821C(x) \
+ (((x) >> BIT_SHIFT_EF_SCAN_END_8821C) & BIT_MASK_EF_SCAN_END_8821C)
+#define BIT_SET_EF_SCAN_END_8821C(x, v) \
+ (BIT_CLEAR_EF_SCAN_END_8821C(x) | BIT_EF_SCAN_END_8821C(v))
#define BIT_EF_PD_DIS_8821C BIT(11)
#define BIT_SHIFT_EF_CELL_SEL_8821C 8
#define BIT_MASK_EF_CELL_SEL_8821C 0x3
-#define BIT_EF_CELL_SEL_8821C(x) (((x) & BIT_MASK_EF_CELL_SEL_8821C) << BIT_SHIFT_EF_CELL_SEL_8821C)
-#define BIT_GET_EF_CELL_SEL_8821C(x) (((x) >> BIT_SHIFT_EF_CELL_SEL_8821C) & BIT_MASK_EF_CELL_SEL_8821C)
+#define BIT_EF_CELL_SEL_8821C(x) \
+ (((x) & BIT_MASK_EF_CELL_SEL_8821C) << BIT_SHIFT_EF_CELL_SEL_8821C)
+#define BITS_EF_CELL_SEL_8821C \
+ (BIT_MASK_EF_CELL_SEL_8821C << BIT_SHIFT_EF_CELL_SEL_8821C)
+#define BIT_CLEAR_EF_CELL_SEL_8821C(x) ((x) & (~BITS_EF_CELL_SEL_8821C))
+#define BIT_GET_EF_CELL_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_EF_CELL_SEL_8821C) & BIT_MASK_EF_CELL_SEL_8821C)
+#define BIT_SET_EF_CELL_SEL_8821C(x, v) \
+ (BIT_CLEAR_EF_CELL_SEL_8821C(x) | BIT_EF_CELL_SEL_8821C(v))
#define BIT_EF_TRPT_8821C BIT(7)
#define BIT_SHIFT_EF_TTHD_8821C 0
#define BIT_MASK_EF_TTHD_8821C 0x7f
-#define BIT_EF_TTHD_8821C(x) (((x) & BIT_MASK_EF_TTHD_8821C) << BIT_SHIFT_EF_TTHD_8821C)
-#define BIT_GET_EF_TTHD_8821C(x) (((x) >> BIT_SHIFT_EF_TTHD_8821C) & BIT_MASK_EF_TTHD_8821C)
-
+#define BIT_EF_TTHD_8821C(x) \
+ (((x) & BIT_MASK_EF_TTHD_8821C) << BIT_SHIFT_EF_TTHD_8821C)
+#define BITS_EF_TTHD_8821C (BIT_MASK_EF_TTHD_8821C << BIT_SHIFT_EF_TTHD_8821C)
+#define BIT_CLEAR_EF_TTHD_8821C(x) ((x) & (~BITS_EF_TTHD_8821C))
+#define BIT_GET_EF_TTHD_8821C(x) \
+ (((x) >> BIT_SHIFT_EF_TTHD_8821C) & BIT_MASK_EF_TTHD_8821C)
+#define BIT_SET_EF_TTHD_8821C(x, v) \
+ (BIT_CLEAR_EF_TTHD_8821C(x) | BIT_EF_TTHD_8821C(v))
/* 2 REG_PWR_OPTION_CTRL_8821C */
#define BIT_SHIFT_DBG_SEL_V1_8821C 16
#define BIT_MASK_DBG_SEL_V1_8821C 0xff
-#define BIT_DBG_SEL_V1_8821C(x) (((x) & BIT_MASK_DBG_SEL_V1_8821C) << BIT_SHIFT_DBG_SEL_V1_8821C)
-#define BIT_GET_DBG_SEL_V1_8821C(x) (((x) >> BIT_SHIFT_DBG_SEL_V1_8821C) & BIT_MASK_DBG_SEL_V1_8821C)
-
+#define BIT_DBG_SEL_V1_8821C(x) \
+ (((x) & BIT_MASK_DBG_SEL_V1_8821C) << BIT_SHIFT_DBG_SEL_V1_8821C)
+#define BITS_DBG_SEL_V1_8821C \
+ (BIT_MASK_DBG_SEL_V1_8821C << BIT_SHIFT_DBG_SEL_V1_8821C)
+#define BIT_CLEAR_DBG_SEL_V1_8821C(x) ((x) & (~BITS_DBG_SEL_V1_8821C))
+#define BIT_GET_DBG_SEL_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_DBG_SEL_V1_8821C) & BIT_MASK_DBG_SEL_V1_8821C)
+#define BIT_SET_DBG_SEL_V1_8821C(x, v) \
+ (BIT_CLEAR_DBG_SEL_V1_8821C(x) | BIT_DBG_SEL_V1_8821C(v))
#define BIT_SHIFT_DBG_SEL_BYTE_8821C 14
#define BIT_MASK_DBG_SEL_BYTE_8821C 0x3
-#define BIT_DBG_SEL_BYTE_8821C(x) (((x) & BIT_MASK_DBG_SEL_BYTE_8821C) << BIT_SHIFT_DBG_SEL_BYTE_8821C)
-#define BIT_GET_DBG_SEL_BYTE_8821C(x) (((x) >> BIT_SHIFT_DBG_SEL_BYTE_8821C) & BIT_MASK_DBG_SEL_BYTE_8821C)
-
+#define BIT_DBG_SEL_BYTE_8821C(x) \
+ (((x) & BIT_MASK_DBG_SEL_BYTE_8821C) << BIT_SHIFT_DBG_SEL_BYTE_8821C)
+#define BITS_DBG_SEL_BYTE_8821C \
+ (BIT_MASK_DBG_SEL_BYTE_8821C << BIT_SHIFT_DBG_SEL_BYTE_8821C)
+#define BIT_CLEAR_DBG_SEL_BYTE_8821C(x) ((x) & (~BITS_DBG_SEL_BYTE_8821C))
+#define BIT_GET_DBG_SEL_BYTE_8821C(x) \
+ (((x) >> BIT_SHIFT_DBG_SEL_BYTE_8821C) & BIT_MASK_DBG_SEL_BYTE_8821C)
+#define BIT_SET_DBG_SEL_BYTE_8821C(x, v) \
+ (BIT_CLEAR_DBG_SEL_BYTE_8821C(x) | BIT_DBG_SEL_BYTE_8821C(v))
#define BIT_SHIFT_STD_L1_V1_8821C 12
#define BIT_MASK_STD_L1_V1_8821C 0x3
-#define BIT_STD_L1_V1_8821C(x) (((x) & BIT_MASK_STD_L1_V1_8821C) << BIT_SHIFT_STD_L1_V1_8821C)
-#define BIT_GET_STD_L1_V1_8821C(x) (((x) >> BIT_SHIFT_STD_L1_V1_8821C) & BIT_MASK_STD_L1_V1_8821C)
+#define BIT_STD_L1_V1_8821C(x) \
+ (((x) & BIT_MASK_STD_L1_V1_8821C) << BIT_SHIFT_STD_L1_V1_8821C)
+#define BITS_STD_L1_V1_8821C \
+ (BIT_MASK_STD_L1_V1_8821C << BIT_SHIFT_STD_L1_V1_8821C)
+#define BIT_CLEAR_STD_L1_V1_8821C(x) ((x) & (~BITS_STD_L1_V1_8821C))
+#define BIT_GET_STD_L1_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_STD_L1_V1_8821C) & BIT_MASK_STD_L1_V1_8821C)
+#define BIT_SET_STD_L1_V1_8821C(x, v) \
+ (BIT_CLEAR_STD_L1_V1_8821C(x) | BIT_STD_L1_V1_8821C(v))
#define BIT_SYSON_DBG_PAD_E2_8821C BIT(11)
#define BIT_SYSON_LED_PAD_E2_8821C BIT(10)
@@ -528,49 +865,101 @@
#define BIT_SHIFT_SYSON_SPS0WWV_WT_8821C 4
#define BIT_MASK_SYSON_SPS0WWV_WT_8821C 0x3
-#define BIT_SYSON_SPS0WWV_WT_8821C(x) (((x) & BIT_MASK_SYSON_SPS0WWV_WT_8821C) << BIT_SHIFT_SYSON_SPS0WWV_WT_8821C)
-#define BIT_GET_SYSON_SPS0WWV_WT_8821C(x) (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8821C) & BIT_MASK_SYSON_SPS0WWV_WT_8821C)
-
+#define BIT_SYSON_SPS0WWV_WT_8821C(x) \
+ (((x) & BIT_MASK_SYSON_SPS0WWV_WT_8821C) \
+ << BIT_SHIFT_SYSON_SPS0WWV_WT_8821C)
+#define BITS_SYSON_SPS0WWV_WT_8821C \
+ (BIT_MASK_SYSON_SPS0WWV_WT_8821C << BIT_SHIFT_SYSON_SPS0WWV_WT_8821C)
+#define BIT_CLEAR_SYSON_SPS0WWV_WT_8821C(x) \
+ ((x) & (~BITS_SYSON_SPS0WWV_WT_8821C))
+#define BIT_GET_SYSON_SPS0WWV_WT_8821C(x) \
+ (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8821C) & \
+ BIT_MASK_SYSON_SPS0WWV_WT_8821C)
+#define BIT_SET_SYSON_SPS0WWV_WT_8821C(x, v) \
+ (BIT_CLEAR_SYSON_SPS0WWV_WT_8821C(x) | BIT_SYSON_SPS0WWV_WT_8821C(v))
#define BIT_SHIFT_SYSON_SPS0LDO_WT_8821C 2
#define BIT_MASK_SYSON_SPS0LDO_WT_8821C 0x3
-#define BIT_SYSON_SPS0LDO_WT_8821C(x) (((x) & BIT_MASK_SYSON_SPS0LDO_WT_8821C) << BIT_SHIFT_SYSON_SPS0LDO_WT_8821C)
-#define BIT_GET_SYSON_SPS0LDO_WT_8821C(x) (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8821C) & BIT_MASK_SYSON_SPS0LDO_WT_8821C)
-
+#define BIT_SYSON_SPS0LDO_WT_8821C(x) \
+ (((x) & BIT_MASK_SYSON_SPS0LDO_WT_8821C) \
+ << BIT_SHIFT_SYSON_SPS0LDO_WT_8821C)
+#define BITS_SYSON_SPS0LDO_WT_8821C \
+ (BIT_MASK_SYSON_SPS0LDO_WT_8821C << BIT_SHIFT_SYSON_SPS0LDO_WT_8821C)
+#define BIT_CLEAR_SYSON_SPS0LDO_WT_8821C(x) \
+ ((x) & (~BITS_SYSON_SPS0LDO_WT_8821C))
+#define BIT_GET_SYSON_SPS0LDO_WT_8821C(x) \
+ (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8821C) & \
+ BIT_MASK_SYSON_SPS0LDO_WT_8821C)
+#define BIT_SET_SYSON_SPS0LDO_WT_8821C(x, v) \
+ (BIT_CLEAR_SYSON_SPS0LDO_WT_8821C(x) | BIT_SYSON_SPS0LDO_WT_8821C(v))
#define BIT_SHIFT_SYSON_RCLK_SCALE_8821C 0
#define BIT_MASK_SYSON_RCLK_SCALE_8821C 0x3
-#define BIT_SYSON_RCLK_SCALE_8821C(x) (((x) & BIT_MASK_SYSON_RCLK_SCALE_8821C) << BIT_SHIFT_SYSON_RCLK_SCALE_8821C)
-#define BIT_GET_SYSON_RCLK_SCALE_8821C(x) (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8821C) & BIT_MASK_SYSON_RCLK_SCALE_8821C)
-
+#define BIT_SYSON_RCLK_SCALE_8821C(x) \
+ (((x) & BIT_MASK_SYSON_RCLK_SCALE_8821C) \
+ << BIT_SHIFT_SYSON_RCLK_SCALE_8821C)
+#define BITS_SYSON_RCLK_SCALE_8821C \
+ (BIT_MASK_SYSON_RCLK_SCALE_8821C << BIT_SHIFT_SYSON_RCLK_SCALE_8821C)
+#define BIT_CLEAR_SYSON_RCLK_SCALE_8821C(x) \
+ ((x) & (~BITS_SYSON_RCLK_SCALE_8821C))
+#define BIT_GET_SYSON_RCLK_SCALE_8821C(x) \
+ (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8821C) & \
+ BIT_MASK_SYSON_RCLK_SCALE_8821C)
+#define BIT_SET_SYSON_RCLK_SCALE_8821C(x, v) \
+ (BIT_CLEAR_SYSON_RCLK_SCALE_8821C(x) | BIT_SYSON_RCLK_SCALE_8821C(v))
/* 2 REG_CAL_TIMER_8821C */
#define BIT_SHIFT_MATCH_CNT_8821C 8
#define BIT_MASK_MATCH_CNT_8821C 0xff
-#define BIT_MATCH_CNT_8821C(x) (((x) & BIT_MASK_MATCH_CNT_8821C) << BIT_SHIFT_MATCH_CNT_8821C)
-#define BIT_GET_MATCH_CNT_8821C(x) (((x) >> BIT_SHIFT_MATCH_CNT_8821C) & BIT_MASK_MATCH_CNT_8821C)
-
+#define BIT_MATCH_CNT_8821C(x) \
+ (((x) & BIT_MASK_MATCH_CNT_8821C) << BIT_SHIFT_MATCH_CNT_8821C)
+#define BITS_MATCH_CNT_8821C \
+ (BIT_MASK_MATCH_CNT_8821C << BIT_SHIFT_MATCH_CNT_8821C)
+#define BIT_CLEAR_MATCH_CNT_8821C(x) ((x) & (~BITS_MATCH_CNT_8821C))
+#define BIT_GET_MATCH_CNT_8821C(x) \
+ (((x) >> BIT_SHIFT_MATCH_CNT_8821C) & BIT_MASK_MATCH_CNT_8821C)
+#define BIT_SET_MATCH_CNT_8821C(x, v) \
+ (BIT_CLEAR_MATCH_CNT_8821C(x) | BIT_MATCH_CNT_8821C(v))
#define BIT_SHIFT_CAL_SCAL_8821C 0
#define BIT_MASK_CAL_SCAL_8821C 0xff
-#define BIT_CAL_SCAL_8821C(x) (((x) & BIT_MASK_CAL_SCAL_8821C) << BIT_SHIFT_CAL_SCAL_8821C)
-#define BIT_GET_CAL_SCAL_8821C(x) (((x) >> BIT_SHIFT_CAL_SCAL_8821C) & BIT_MASK_CAL_SCAL_8821C)
-
+#define BIT_CAL_SCAL_8821C(x) \
+ (((x) & BIT_MASK_CAL_SCAL_8821C) << BIT_SHIFT_CAL_SCAL_8821C)
+#define BITS_CAL_SCAL_8821C \
+ (BIT_MASK_CAL_SCAL_8821C << BIT_SHIFT_CAL_SCAL_8821C)
+#define BIT_CLEAR_CAL_SCAL_8821C(x) ((x) & (~BITS_CAL_SCAL_8821C))
+#define BIT_GET_CAL_SCAL_8821C(x) \
+ (((x) >> BIT_SHIFT_CAL_SCAL_8821C) & BIT_MASK_CAL_SCAL_8821C)
+#define BIT_SET_CAL_SCAL_8821C(x, v) \
+ (BIT_CLEAR_CAL_SCAL_8821C(x) | BIT_CAL_SCAL_8821C(v))
/* 2 REG_ACLK_MON_8821C */
#define BIT_SHIFT_RCLK_MON_8821C 5
#define BIT_MASK_RCLK_MON_8821C 0x7ff
-#define BIT_RCLK_MON_8821C(x) (((x) & BIT_MASK_RCLK_MON_8821C) << BIT_SHIFT_RCLK_MON_8821C)
-#define BIT_GET_RCLK_MON_8821C(x) (((x) >> BIT_SHIFT_RCLK_MON_8821C) & BIT_MASK_RCLK_MON_8821C)
+#define BIT_RCLK_MON_8821C(x) \
+ (((x) & BIT_MASK_RCLK_MON_8821C) << BIT_SHIFT_RCLK_MON_8821C)
+#define BITS_RCLK_MON_8821C \
+ (BIT_MASK_RCLK_MON_8821C << BIT_SHIFT_RCLK_MON_8821C)
+#define BIT_CLEAR_RCLK_MON_8821C(x) ((x) & (~BITS_RCLK_MON_8821C))
+#define BIT_GET_RCLK_MON_8821C(x) \
+ (((x) >> BIT_SHIFT_RCLK_MON_8821C) & BIT_MASK_RCLK_MON_8821C)
+#define BIT_SET_RCLK_MON_8821C(x, v) \
+ (BIT_CLEAR_RCLK_MON_8821C(x) | BIT_RCLK_MON_8821C(v))
#define BIT_CAL_EN_8821C BIT(4)
#define BIT_SHIFT_DPSTU_8821C 2
#define BIT_MASK_DPSTU_8821C 0x3
-#define BIT_DPSTU_8821C(x) (((x) & BIT_MASK_DPSTU_8821C) << BIT_SHIFT_DPSTU_8821C)
-#define BIT_GET_DPSTU_8821C(x) (((x) >> BIT_SHIFT_DPSTU_8821C) & BIT_MASK_DPSTU_8821C)
+#define BIT_DPSTU_8821C(x) \
+ (((x) & BIT_MASK_DPSTU_8821C) << BIT_SHIFT_DPSTU_8821C)
+#define BITS_DPSTU_8821C (BIT_MASK_DPSTU_8821C << BIT_SHIFT_DPSTU_8821C)
+#define BIT_CLEAR_DPSTU_8821C(x) ((x) & (~BITS_DPSTU_8821C))
+#define BIT_GET_DPSTU_8821C(x) \
+ (((x) >> BIT_SHIFT_DPSTU_8821C) & BIT_MASK_DPSTU_8821C)
+#define BIT_SET_DPSTU_8821C(x, v) \
+ (BIT_CLEAR_DPSTU_8821C(x) | BIT_DPSTU_8821C(v))
#define BIT_SUS_16X_8821C BIT(1)
@@ -588,8 +977,14 @@
#define BIT_SHIFT_BTMODE_8821C 6
#define BIT_MASK_BTMODE_8821C 0x3
-#define BIT_BTMODE_8821C(x) (((x) & BIT_MASK_BTMODE_8821C) << BIT_SHIFT_BTMODE_8821C)
-#define BIT_GET_BTMODE_8821C(x) (((x) >> BIT_SHIFT_BTMODE_8821C) & BIT_MASK_BTMODE_8821C)
+#define BIT_BTMODE_8821C(x) \
+ (((x) & BIT_MASK_BTMODE_8821C) << BIT_SHIFT_BTMODE_8821C)
+#define BITS_BTMODE_8821C (BIT_MASK_BTMODE_8821C << BIT_SHIFT_BTMODE_8821C)
+#define BIT_CLEAR_BTMODE_8821C(x) ((x) & (~BITS_BTMODE_8821C))
+#define BIT_GET_BTMODE_8821C(x) \
+ (((x) >> BIT_SHIFT_BTMODE_8821C) & BIT_MASK_BTMODE_8821C)
+#define BIT_SET_BTMODE_8821C(x, v) \
+ (BIT_CLEAR_BTMODE_8821C(x) | BIT_BTMODE_8821C(v))
#define BIT_ENBT_8821C BIT(5)
#define BIT_EROM_EN_8821C BIT(4)
@@ -598,42 +993,89 @@
#define BIT_SHIFT_GPIOSEL_8821C 0
#define BIT_MASK_GPIOSEL_8821C 0x3
-#define BIT_GPIOSEL_8821C(x) (((x) & BIT_MASK_GPIOSEL_8821C) << BIT_SHIFT_GPIOSEL_8821C)
-#define BIT_GET_GPIOSEL_8821C(x) (((x) >> BIT_SHIFT_GPIOSEL_8821C) & BIT_MASK_GPIOSEL_8821C)
-
+#define BIT_GPIOSEL_8821C(x) \
+ (((x) & BIT_MASK_GPIOSEL_8821C) << BIT_SHIFT_GPIOSEL_8821C)
+#define BITS_GPIOSEL_8821C (BIT_MASK_GPIOSEL_8821C << BIT_SHIFT_GPIOSEL_8821C)
+#define BIT_CLEAR_GPIOSEL_8821C(x) ((x) & (~BITS_GPIOSEL_8821C))
+#define BIT_GET_GPIOSEL_8821C(x) \
+ (((x) >> BIT_SHIFT_GPIOSEL_8821C) & BIT_MASK_GPIOSEL_8821C)
+#define BIT_SET_GPIOSEL_8821C(x, v) \
+ (BIT_CLEAR_GPIOSEL_8821C(x) | BIT_GPIOSEL_8821C(v))
/* 2 REG_GPIO_PIN_CTRL_8821C */
#define BIT_SHIFT_GPIO_MOD_7_TO_0_8821C 24
#define BIT_MASK_GPIO_MOD_7_TO_0_8821C 0xff
-#define BIT_GPIO_MOD_7_TO_0_8821C(x) (((x) & BIT_MASK_GPIO_MOD_7_TO_0_8821C) << BIT_SHIFT_GPIO_MOD_7_TO_0_8821C)
-#define BIT_GET_GPIO_MOD_7_TO_0_8821C(x) (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8821C) & BIT_MASK_GPIO_MOD_7_TO_0_8821C)
-
+#define BIT_GPIO_MOD_7_TO_0_8821C(x) \
+ (((x) & BIT_MASK_GPIO_MOD_7_TO_0_8821C) \
+ << BIT_SHIFT_GPIO_MOD_7_TO_0_8821C)
+#define BITS_GPIO_MOD_7_TO_0_8821C \
+ (BIT_MASK_GPIO_MOD_7_TO_0_8821C << BIT_SHIFT_GPIO_MOD_7_TO_0_8821C)
+#define BIT_CLEAR_GPIO_MOD_7_TO_0_8821C(x) ((x) & (~BITS_GPIO_MOD_7_TO_0_8821C))
+#define BIT_GET_GPIO_MOD_7_TO_0_8821C(x) \
+ (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8821C) & \
+ BIT_MASK_GPIO_MOD_7_TO_0_8821C)
+#define BIT_SET_GPIO_MOD_7_TO_0_8821C(x, v) \
+ (BIT_CLEAR_GPIO_MOD_7_TO_0_8821C(x) | BIT_GPIO_MOD_7_TO_0_8821C(v))
#define BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8821C 16
#define BIT_MASK_GPIO_IO_SEL_7_TO_0_8821C 0xff
-#define BIT_GPIO_IO_SEL_7_TO_0_8821C(x) (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8821C) << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8821C)
-#define BIT_GET_GPIO_IO_SEL_7_TO_0_8821C(x) (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8821C) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8821C)
-
+#define BIT_GPIO_IO_SEL_7_TO_0_8821C(x) \
+ (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8821C) \
+ << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8821C)
+#define BITS_GPIO_IO_SEL_7_TO_0_8821C \
+ (BIT_MASK_GPIO_IO_SEL_7_TO_0_8821C \
+ << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8821C)
+#define BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8821C(x) \
+ ((x) & (~BITS_GPIO_IO_SEL_7_TO_0_8821C))
+#define BIT_GET_GPIO_IO_SEL_7_TO_0_8821C(x) \
+ (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8821C) & \
+ BIT_MASK_GPIO_IO_SEL_7_TO_0_8821C)
+#define BIT_SET_GPIO_IO_SEL_7_TO_0_8821C(x, v) \
+ (BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8821C(x) | \
+ BIT_GPIO_IO_SEL_7_TO_0_8821C(v))
#define BIT_SHIFT_GPIO_OUT_7_TO_0_8821C 8
#define BIT_MASK_GPIO_OUT_7_TO_0_8821C 0xff
-#define BIT_GPIO_OUT_7_TO_0_8821C(x) (((x) & BIT_MASK_GPIO_OUT_7_TO_0_8821C) << BIT_SHIFT_GPIO_OUT_7_TO_0_8821C)
-#define BIT_GET_GPIO_OUT_7_TO_0_8821C(x) (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8821C) & BIT_MASK_GPIO_OUT_7_TO_0_8821C)
-
+#define BIT_GPIO_OUT_7_TO_0_8821C(x) \
+ (((x) & BIT_MASK_GPIO_OUT_7_TO_0_8821C) \
+ << BIT_SHIFT_GPIO_OUT_7_TO_0_8821C)
+#define BITS_GPIO_OUT_7_TO_0_8821C \
+ (BIT_MASK_GPIO_OUT_7_TO_0_8821C << BIT_SHIFT_GPIO_OUT_7_TO_0_8821C)
+#define BIT_CLEAR_GPIO_OUT_7_TO_0_8821C(x) ((x) & (~BITS_GPIO_OUT_7_TO_0_8821C))
+#define BIT_GET_GPIO_OUT_7_TO_0_8821C(x) \
+ (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8821C) & \
+ BIT_MASK_GPIO_OUT_7_TO_0_8821C)
+#define BIT_SET_GPIO_OUT_7_TO_0_8821C(x, v) \
+ (BIT_CLEAR_GPIO_OUT_7_TO_0_8821C(x) | BIT_GPIO_OUT_7_TO_0_8821C(v))
#define BIT_SHIFT_GPIO_IN_7_TO_0_8821C 0
#define BIT_MASK_GPIO_IN_7_TO_0_8821C 0xff
-#define BIT_GPIO_IN_7_TO_0_8821C(x) (((x) & BIT_MASK_GPIO_IN_7_TO_0_8821C) << BIT_SHIFT_GPIO_IN_7_TO_0_8821C)
-#define BIT_GET_GPIO_IN_7_TO_0_8821C(x) (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8821C) & BIT_MASK_GPIO_IN_7_TO_0_8821C)
-
+#define BIT_GPIO_IN_7_TO_0_8821C(x) \
+ (((x) & BIT_MASK_GPIO_IN_7_TO_0_8821C) \
+ << BIT_SHIFT_GPIO_IN_7_TO_0_8821C)
+#define BITS_GPIO_IN_7_TO_0_8821C \
+ (BIT_MASK_GPIO_IN_7_TO_0_8821C << BIT_SHIFT_GPIO_IN_7_TO_0_8821C)
+#define BIT_CLEAR_GPIO_IN_7_TO_0_8821C(x) ((x) & (~BITS_GPIO_IN_7_TO_0_8821C))
+#define BIT_GET_GPIO_IN_7_TO_0_8821C(x) \
+ (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8821C) & \
+ BIT_MASK_GPIO_IN_7_TO_0_8821C)
+#define BIT_SET_GPIO_IN_7_TO_0_8821C(x, v) \
+ (BIT_CLEAR_GPIO_IN_7_TO_0_8821C(x) | BIT_GPIO_IN_7_TO_0_8821C(v))
/* 2 REG_GPIO_INTM_8821C */
#define BIT_SHIFT_MUXDBG_SEL_8821C 30
#define BIT_MASK_MUXDBG_SEL_8821C 0x3
-#define BIT_MUXDBG_SEL_8821C(x) (((x) & BIT_MASK_MUXDBG_SEL_8821C) << BIT_SHIFT_MUXDBG_SEL_8821C)
-#define BIT_GET_MUXDBG_SEL_8821C(x) (((x) >> BIT_SHIFT_MUXDBG_SEL_8821C) & BIT_MASK_MUXDBG_SEL_8821C)
+#define BIT_MUXDBG_SEL_8821C(x) \
+ (((x) & BIT_MASK_MUXDBG_SEL_8821C) << BIT_SHIFT_MUXDBG_SEL_8821C)
+#define BITS_MUXDBG_SEL_8821C \
+ (BIT_MASK_MUXDBG_SEL_8821C << BIT_SHIFT_MUXDBG_SEL_8821C)
+#define BIT_CLEAR_MUXDBG_SEL_8821C(x) ((x) & (~BITS_MUXDBG_SEL_8821C))
+#define BIT_GET_MUXDBG_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_MUXDBG_SEL_8821C) & BIT_MASK_MUXDBG_SEL_8821C)
+#define BIT_SET_MUXDBG_SEL_8821C(x, v) \
+ (BIT_CLEAR_MUXDBG_SEL_8821C(x) | BIT_MUXDBG_SEL_8821C(v))
#define BIT_EXTWOL_SEL_8821C BIT(17)
#define BIT_EXTWOL_EN_8821C BIT(16)
@@ -664,15 +1106,20 @@
#define BIT_DPDT_WLBT_SEL_8821C BIT(24)
#define BIT_DPDT_SEL_EN_8821C BIT(23)
#define BIT_GPIO13_14_WL_CTRL_EN_8821C BIT(22)
-#define BIT_GPIO13_14_WL_CTRL_EN_8821C BIT(22)
#define BIT_LED2DIS_8821C BIT(21)
#define BIT_LED2PL_8821C BIT(20)
#define BIT_LED2SV_8821C BIT(19)
#define BIT_SHIFT_LED2CM_8821C 16
#define BIT_MASK_LED2CM_8821C 0x7
-#define BIT_LED2CM_8821C(x) (((x) & BIT_MASK_LED2CM_8821C) << BIT_SHIFT_LED2CM_8821C)
-#define BIT_GET_LED2CM_8821C(x) (((x) >> BIT_SHIFT_LED2CM_8821C) & BIT_MASK_LED2CM_8821C)
+#define BIT_LED2CM_8821C(x) \
+ (((x) & BIT_MASK_LED2CM_8821C) << BIT_SHIFT_LED2CM_8821C)
+#define BITS_LED2CM_8821C (BIT_MASK_LED2CM_8821C << BIT_SHIFT_LED2CM_8821C)
+#define BIT_CLEAR_LED2CM_8821C(x) ((x) & (~BITS_LED2CM_8821C))
+#define BIT_GET_LED2CM_8821C(x) \
+ (((x) >> BIT_SHIFT_LED2CM_8821C) & BIT_MASK_LED2CM_8821C)
+#define BIT_SET_LED2CM_8821C(x, v) \
+ (BIT_CLEAR_LED2CM_8821C(x) | BIT_LED2CM_8821C(v))
#define BIT_LED1DIS_8821C BIT(15)
#define BIT_LED1PL_8821C BIT(12)
@@ -680,24 +1127,45 @@
#define BIT_SHIFT_LED1CM_8821C 8
#define BIT_MASK_LED1CM_8821C 0x7
-#define BIT_LED1CM_8821C(x) (((x) & BIT_MASK_LED1CM_8821C) << BIT_SHIFT_LED1CM_8821C)
-#define BIT_GET_LED1CM_8821C(x) (((x) >> BIT_SHIFT_LED1CM_8821C) & BIT_MASK_LED1CM_8821C)
+#define BIT_LED1CM_8821C(x) \
+ (((x) & BIT_MASK_LED1CM_8821C) << BIT_SHIFT_LED1CM_8821C)
+#define BITS_LED1CM_8821C (BIT_MASK_LED1CM_8821C << BIT_SHIFT_LED1CM_8821C)
+#define BIT_CLEAR_LED1CM_8821C(x) ((x) & (~BITS_LED1CM_8821C))
+#define BIT_GET_LED1CM_8821C(x) \
+ (((x) >> BIT_SHIFT_LED1CM_8821C) & BIT_MASK_LED1CM_8821C)
+#define BIT_SET_LED1CM_8821C(x, v) \
+ (BIT_CLEAR_LED1CM_8821C(x) | BIT_LED1CM_8821C(v))
#define BIT_LED0DIS_8821C BIT(7)
#define BIT_SHIFT_AFE_LDO_SWR_CHECK_8821C 5
#define BIT_MASK_AFE_LDO_SWR_CHECK_8821C 0x3
-#define BIT_AFE_LDO_SWR_CHECK_8821C(x) (((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8821C) << BIT_SHIFT_AFE_LDO_SWR_CHECK_8821C)
-#define BIT_GET_AFE_LDO_SWR_CHECK_8821C(x) (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8821C) & BIT_MASK_AFE_LDO_SWR_CHECK_8821C)
+#define BIT_AFE_LDO_SWR_CHECK_8821C(x) \
+ (((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8821C) \
+ << BIT_SHIFT_AFE_LDO_SWR_CHECK_8821C)
+#define BITS_AFE_LDO_SWR_CHECK_8821C \
+ (BIT_MASK_AFE_LDO_SWR_CHECK_8821C << BIT_SHIFT_AFE_LDO_SWR_CHECK_8821C)
+#define BIT_CLEAR_AFE_LDO_SWR_CHECK_8821C(x) \
+ ((x) & (~BITS_AFE_LDO_SWR_CHECK_8821C))
+#define BIT_GET_AFE_LDO_SWR_CHECK_8821C(x) \
+ (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8821C) & \
+ BIT_MASK_AFE_LDO_SWR_CHECK_8821C)
+#define BIT_SET_AFE_LDO_SWR_CHECK_8821C(x, v) \
+ (BIT_CLEAR_AFE_LDO_SWR_CHECK_8821C(x) | BIT_AFE_LDO_SWR_CHECK_8821C(v))
#define BIT_LED0PL_8821C BIT(4)
#define BIT_LED0SV_8821C BIT(3)
#define BIT_SHIFT_LED0CM_8821C 0
#define BIT_MASK_LED0CM_8821C 0x7
-#define BIT_LED0CM_8821C(x) (((x) & BIT_MASK_LED0CM_8821C) << BIT_SHIFT_LED0CM_8821C)
-#define BIT_GET_LED0CM_8821C(x) (((x) >> BIT_SHIFT_LED0CM_8821C) & BIT_MASK_LED0CM_8821C)
-
+#define BIT_LED0CM_8821C(x) \
+ (((x) & BIT_MASK_LED0CM_8821C) << BIT_SHIFT_LED0CM_8821C)
+#define BITS_LED0CM_8821C (BIT_MASK_LED0CM_8821C << BIT_SHIFT_LED0CM_8821C)
+#define BIT_CLEAR_LED0CM_8821C(x) ((x) & (~BITS_LED0CM_8821C))
+#define BIT_GET_LED0CM_8821C(x) \
+ (((x) >> BIT_SHIFT_LED0CM_8821C) & BIT_MASK_LED0CM_8821C)
+#define BIT_SET_LED0CM_8821C(x, v) \
+ (BIT_CLEAR_LED0CM_8821C(x) | BIT_LED0CM_8821C(v))
/* 2 REG_FSIMR_8821C */
#define BIT_FS_PDNINT_EN_8821C BIT(31)
@@ -779,7 +1247,7 @@
#define BIT_GPIO5_INT_EN_8821C BIT(21)
#define BIT_GPIO4_INT_EN_8821C BIT(20)
#define BIT_GPIO3_INT_EN_8821C BIT(19)
-#define BIT_GPIO2_INT_EN_V1_8821C BIT(16)
+#define BIT_GPIO2_INT_EN_V1_8821C BIT(18)
#define BIT_GPIO1_INT_EN_8821C BIT(17)
#define BIT_GPIO0_INT_EN_8821C BIT(16)
#define BIT_PDNINT_EN_8821C BIT(7)
@@ -801,7 +1269,7 @@
#define BIT_GPIO5_INT_8821C BIT(21)
#define BIT_GPIO4_INT_8821C BIT(20)
#define BIT_GPIO3_INT_8821C BIT(19)
-#define BIT_GPIO2_INT_V1_8821C BIT(16)
+#define BIT_GPIO2_INT_V1_8821C BIT(18)
#define BIT_GPIO1_INT_8821C BIT(17)
#define BIT_GPIO0_INT_8821C BIT(16)
#define BIT_PDNINT_8821C BIT(7)
@@ -813,27 +1281,64 @@
#define BIT_SHIFT_GPIO_MOD_15_TO_8_8821C 24
#define BIT_MASK_GPIO_MOD_15_TO_8_8821C 0xff
-#define BIT_GPIO_MOD_15_TO_8_8821C(x) (((x) & BIT_MASK_GPIO_MOD_15_TO_8_8821C) << BIT_SHIFT_GPIO_MOD_15_TO_8_8821C)
-#define BIT_GET_GPIO_MOD_15_TO_8_8821C(x) (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8821C) & BIT_MASK_GPIO_MOD_15_TO_8_8821C)
-
+#define BIT_GPIO_MOD_15_TO_8_8821C(x) \
+ (((x) & BIT_MASK_GPIO_MOD_15_TO_8_8821C) \
+ << BIT_SHIFT_GPIO_MOD_15_TO_8_8821C)
+#define BITS_GPIO_MOD_15_TO_8_8821C \
+ (BIT_MASK_GPIO_MOD_15_TO_8_8821C << BIT_SHIFT_GPIO_MOD_15_TO_8_8821C)
+#define BIT_CLEAR_GPIO_MOD_15_TO_8_8821C(x) \
+ ((x) & (~BITS_GPIO_MOD_15_TO_8_8821C))
+#define BIT_GET_GPIO_MOD_15_TO_8_8821C(x) \
+ (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8821C) & \
+ BIT_MASK_GPIO_MOD_15_TO_8_8821C)
+#define BIT_SET_GPIO_MOD_15_TO_8_8821C(x, v) \
+ (BIT_CLEAR_GPIO_MOD_15_TO_8_8821C(x) | BIT_GPIO_MOD_15_TO_8_8821C(v))
#define BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8821C 16
#define BIT_MASK_GPIO_IO_SEL_15_TO_8_8821C 0xff
-#define BIT_GPIO_IO_SEL_15_TO_8_8821C(x) (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8821C) << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8821C)
-#define BIT_GET_GPIO_IO_SEL_15_TO_8_8821C(x) (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8821C) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8821C)
-
+#define BIT_GPIO_IO_SEL_15_TO_8_8821C(x) \
+ (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8821C) \
+ << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8821C)
+#define BITS_GPIO_IO_SEL_15_TO_8_8821C \
+ (BIT_MASK_GPIO_IO_SEL_15_TO_8_8821C \
+ << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8821C)
+#define BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8821C(x) \
+ ((x) & (~BITS_GPIO_IO_SEL_15_TO_8_8821C))
+#define BIT_GET_GPIO_IO_SEL_15_TO_8_8821C(x) \
+ (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8821C) & \
+ BIT_MASK_GPIO_IO_SEL_15_TO_8_8821C)
+#define BIT_SET_GPIO_IO_SEL_15_TO_8_8821C(x, v) \
+ (BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8821C(x) | \
+ BIT_GPIO_IO_SEL_15_TO_8_8821C(v))
#define BIT_SHIFT_GPIO_OUT_15_TO_8_8821C 8
#define BIT_MASK_GPIO_OUT_15_TO_8_8821C 0xff
-#define BIT_GPIO_OUT_15_TO_8_8821C(x) (((x) & BIT_MASK_GPIO_OUT_15_TO_8_8821C) << BIT_SHIFT_GPIO_OUT_15_TO_8_8821C)
-#define BIT_GET_GPIO_OUT_15_TO_8_8821C(x) (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8821C) & BIT_MASK_GPIO_OUT_15_TO_8_8821C)
-
+#define BIT_GPIO_OUT_15_TO_8_8821C(x) \
+ (((x) & BIT_MASK_GPIO_OUT_15_TO_8_8821C) \
+ << BIT_SHIFT_GPIO_OUT_15_TO_8_8821C)
+#define BITS_GPIO_OUT_15_TO_8_8821C \
+ (BIT_MASK_GPIO_OUT_15_TO_8_8821C << BIT_SHIFT_GPIO_OUT_15_TO_8_8821C)
+#define BIT_CLEAR_GPIO_OUT_15_TO_8_8821C(x) \
+ ((x) & (~BITS_GPIO_OUT_15_TO_8_8821C))
+#define BIT_GET_GPIO_OUT_15_TO_8_8821C(x) \
+ (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8821C) & \
+ BIT_MASK_GPIO_OUT_15_TO_8_8821C)
+#define BIT_SET_GPIO_OUT_15_TO_8_8821C(x, v) \
+ (BIT_CLEAR_GPIO_OUT_15_TO_8_8821C(x) | BIT_GPIO_OUT_15_TO_8_8821C(v))
#define BIT_SHIFT_GPIO_IN_15_TO_8_8821C 0
#define BIT_MASK_GPIO_IN_15_TO_8_8821C 0xff
-#define BIT_GPIO_IN_15_TO_8_8821C(x) (((x) & BIT_MASK_GPIO_IN_15_TO_8_8821C) << BIT_SHIFT_GPIO_IN_15_TO_8_8821C)
-#define BIT_GET_GPIO_IN_15_TO_8_8821C(x) (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8821C) & BIT_MASK_GPIO_IN_15_TO_8_8821C)
-
+#define BIT_GPIO_IN_15_TO_8_8821C(x) \
+ (((x) & BIT_MASK_GPIO_IN_15_TO_8_8821C) \
+ << BIT_SHIFT_GPIO_IN_15_TO_8_8821C)
+#define BITS_GPIO_IN_15_TO_8_8821C \
+ (BIT_MASK_GPIO_IN_15_TO_8_8821C << BIT_SHIFT_GPIO_IN_15_TO_8_8821C)
+#define BIT_CLEAR_GPIO_IN_15_TO_8_8821C(x) ((x) & (~BITS_GPIO_IN_15_TO_8_8821C))
+#define BIT_GET_GPIO_IN_15_TO_8_8821C(x) \
+ (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8821C) & \
+ BIT_MASK_GPIO_IN_15_TO_8_8821C)
+#define BIT_SET_GPIO_IN_15_TO_8_8821C(x, v) \
+ (BIT_CLEAR_GPIO_IN_15_TO_8_8821C(x) | BIT_GPIO_IN_15_TO_8_8821C(v))
/* 2 REG_PAD_CTRL1_8821C */
#define BIT_PAPE_WLBT_SEL_8821C BIT(29)
@@ -850,8 +1355,15 @@
#define BIT_SHIFT_BTGP_GPIO_SL_8821C 16
#define BIT_MASK_BTGP_GPIO_SL_8821C 0x3
-#define BIT_BTGP_GPIO_SL_8821C(x) (((x) & BIT_MASK_BTGP_GPIO_SL_8821C) << BIT_SHIFT_BTGP_GPIO_SL_8821C)
-#define BIT_GET_BTGP_GPIO_SL_8821C(x) (((x) >> BIT_SHIFT_BTGP_GPIO_SL_8821C) & BIT_MASK_BTGP_GPIO_SL_8821C)
+#define BIT_BTGP_GPIO_SL_8821C(x) \
+ (((x) & BIT_MASK_BTGP_GPIO_SL_8821C) << BIT_SHIFT_BTGP_GPIO_SL_8821C)
+#define BITS_BTGP_GPIO_SL_8821C \
+ (BIT_MASK_BTGP_GPIO_SL_8821C << BIT_SHIFT_BTGP_GPIO_SL_8821C)
+#define BIT_CLEAR_BTGP_GPIO_SL_8821C(x) ((x) & (~BITS_BTGP_GPIO_SL_8821C))
+#define BIT_GET_BTGP_GPIO_SL_8821C(x) \
+ (((x) >> BIT_SHIFT_BTGP_GPIO_SL_8821C) & BIT_MASK_BTGP_GPIO_SL_8821C)
+#define BIT_SET_BTGP_GPIO_SL_8821C(x, v) \
+ (BIT_CLEAR_BTGP_GPIO_SL_8821C(x) | BIT_BTGP_GPIO_SL_8821C(v))
#define BIT_PAD_SDIO_SR_8821C BIT(14)
#define BIT_GPIO14_OUTPUT_PL_8821C BIT(13)
@@ -902,9 +1414,15 @@
#define BIT_SHIFT_WLCLK_PHASE_8821C 0
#define BIT_MASK_WLCLK_PHASE_8821C 0x1f
-#define BIT_WLCLK_PHASE_8821C(x) (((x) & BIT_MASK_WLCLK_PHASE_8821C) << BIT_SHIFT_WLCLK_PHASE_8821C)
-#define BIT_GET_WLCLK_PHASE_8821C(x) (((x) >> BIT_SHIFT_WLCLK_PHASE_8821C) & BIT_MASK_WLCLK_PHASE_8821C)
-
+#define BIT_WLCLK_PHASE_8821C(x) \
+ (((x) & BIT_MASK_WLCLK_PHASE_8821C) << BIT_SHIFT_WLCLK_PHASE_8821C)
+#define BITS_WLCLK_PHASE_8821C \
+ (BIT_MASK_WLCLK_PHASE_8821C << BIT_SHIFT_WLCLK_PHASE_8821C)
+#define BIT_CLEAR_WLCLK_PHASE_8821C(x) ((x) & (~BITS_WLCLK_PHASE_8821C))
+#define BIT_GET_WLCLK_PHASE_8821C(x) \
+ (((x) >> BIT_SHIFT_WLCLK_PHASE_8821C) & BIT_MASK_WLCLK_PHASE_8821C)
+#define BIT_SET_WLCLK_PHASE_8821C(x, v) \
+ (BIT_CLEAR_WLCLK_PHASE_8821C(x) | BIT_WLCLK_PHASE_8821C(v))
/* 2 REG_SYS_SDIO_CTRL_8821C */
#define BIT_DBG_GNT_WL_BT_8821C BIT(27)
@@ -925,9 +1443,17 @@
#define BIT_SHIFT_TSFT_SEL_8821C 29
#define BIT_MASK_TSFT_SEL_8821C 0x7
-#define BIT_TSFT_SEL_8821C(x) (((x) & BIT_MASK_TSFT_SEL_8821C) << BIT_SHIFT_TSFT_SEL_8821C)
-#define BIT_GET_TSFT_SEL_8821C(x) (((x) >> BIT_SHIFT_TSFT_SEL_8821C) & BIT_MASK_TSFT_SEL_8821C)
-
+#define BIT_TSFT_SEL_8821C(x) \
+ (((x) & BIT_MASK_TSFT_SEL_8821C) << BIT_SHIFT_TSFT_SEL_8821C)
+#define BITS_TSFT_SEL_8821C \
+ (BIT_MASK_TSFT_SEL_8821C << BIT_SHIFT_TSFT_SEL_8821C)
+#define BIT_CLEAR_TSFT_SEL_8821C(x) ((x) & (~BITS_TSFT_SEL_8821C))
+#define BIT_GET_TSFT_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_TSFT_SEL_8821C) & BIT_MASK_TSFT_SEL_8821C)
+#define BIT_SET_TSFT_SEL_8821C(x, v) \
+ (BIT_CLEAR_TSFT_SEL_8821C(x) | BIT_TSFT_SEL_8821C(v))
+
+#define BIT_SDIO_PAD_E5_8821C BIT(18)
#define BIT_USB_HOST_PWR_OFF_EN_8821C BIT(12)
#define BIT_SYM_LPS_BLOCK_EN_8821C BIT(11)
#define BIT_USB_LPM_ACT_EN_8821C BIT(10)
@@ -936,8 +1462,15 @@
#define BIT_SHIFT_SDIO_PAD_E_8821C 5
#define BIT_MASK_SDIO_PAD_E_8821C 0x7
-#define BIT_SDIO_PAD_E_8821C(x) (((x) & BIT_MASK_SDIO_PAD_E_8821C) << BIT_SHIFT_SDIO_PAD_E_8821C)
-#define BIT_GET_SDIO_PAD_E_8821C(x) (((x) >> BIT_SHIFT_SDIO_PAD_E_8821C) & BIT_MASK_SDIO_PAD_E_8821C)
+#define BIT_SDIO_PAD_E_8821C(x) \
+ (((x) & BIT_MASK_SDIO_PAD_E_8821C) << BIT_SHIFT_SDIO_PAD_E_8821C)
+#define BITS_SDIO_PAD_E_8821C \
+ (BIT_MASK_SDIO_PAD_E_8821C << BIT_SHIFT_SDIO_PAD_E_8821C)
+#define BIT_CLEAR_SDIO_PAD_E_8821C(x) ((x) & (~BITS_SDIO_PAD_E_8821C))
+#define BIT_GET_SDIO_PAD_E_8821C(x) \
+ (((x) >> BIT_SHIFT_SDIO_PAD_E_8821C) & BIT_MASK_SDIO_PAD_E_8821C)
+#define BIT_SET_SDIO_PAD_E_8821C(x, v) \
+ (BIT_CLEAR_SDIO_PAD_E_8821C(x) | BIT_SDIO_PAD_E_8821C(v))
#define BIT_USB_LPPLL_EN_8821C BIT(4)
#define BIT_ROP_SW15_8821C BIT(2)
@@ -952,38 +1485,93 @@
#define BIT_SHIFT_AUTO_ZCD_IN_CODE_8821C 21
#define BIT_MASK_AUTO_ZCD_IN_CODE_8821C 0x1f
-#define BIT_AUTO_ZCD_IN_CODE_8821C(x) (((x) & BIT_MASK_AUTO_ZCD_IN_CODE_8821C) << BIT_SHIFT_AUTO_ZCD_IN_CODE_8821C)
-#define BIT_GET_AUTO_ZCD_IN_CODE_8821C(x) (((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE_8821C) & BIT_MASK_AUTO_ZCD_IN_CODE_8821C)
-
+#define BIT_AUTO_ZCD_IN_CODE_8821C(x) \
+ (((x) & BIT_MASK_AUTO_ZCD_IN_CODE_8821C) \
+ << BIT_SHIFT_AUTO_ZCD_IN_CODE_8821C)
+#define BITS_AUTO_ZCD_IN_CODE_8821C \
+ (BIT_MASK_AUTO_ZCD_IN_CODE_8821C << BIT_SHIFT_AUTO_ZCD_IN_CODE_8821C)
+#define BIT_CLEAR_AUTO_ZCD_IN_CODE_8821C(x) \
+ ((x) & (~BITS_AUTO_ZCD_IN_CODE_8821C))
+#define BIT_GET_AUTO_ZCD_IN_CODE_8821C(x) \
+ (((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE_8821C) & \
+ BIT_MASK_AUTO_ZCD_IN_CODE_8821C)
+#define BIT_SET_AUTO_ZCD_IN_CODE_8821C(x, v) \
+ (BIT_CLEAR_AUTO_ZCD_IN_CODE_8821C(x) | BIT_AUTO_ZCD_IN_CODE_8821C(v))
#define BIT_SHIFT_ZCD_CODE_IN_L_8821C 16
#define BIT_MASK_ZCD_CODE_IN_L_8821C 0x1f
-#define BIT_ZCD_CODE_IN_L_8821C(x) (((x) & BIT_MASK_ZCD_CODE_IN_L_8821C) << BIT_SHIFT_ZCD_CODE_IN_L_8821C)
-#define BIT_GET_ZCD_CODE_IN_L_8821C(x) (((x) >> BIT_SHIFT_ZCD_CODE_IN_L_8821C) & BIT_MASK_ZCD_CODE_IN_L_8821C)
-
+#define BIT_ZCD_CODE_IN_L_8821C(x) \
+ (((x) & BIT_MASK_ZCD_CODE_IN_L_8821C) << BIT_SHIFT_ZCD_CODE_IN_L_8821C)
+#define BITS_ZCD_CODE_IN_L_8821C \
+ (BIT_MASK_ZCD_CODE_IN_L_8821C << BIT_SHIFT_ZCD_CODE_IN_L_8821C)
+#define BIT_CLEAR_ZCD_CODE_IN_L_8821C(x) ((x) & (~BITS_ZCD_CODE_IN_L_8821C))
+#define BIT_GET_ZCD_CODE_IN_L_8821C(x) \
+ (((x) >> BIT_SHIFT_ZCD_CODE_IN_L_8821C) & BIT_MASK_ZCD_CODE_IN_L_8821C)
+#define BIT_SET_ZCD_CODE_IN_L_8821C(x, v) \
+ (BIT_CLEAR_ZCD_CODE_IN_L_8821C(x) | BIT_ZCD_CODE_IN_L_8821C(v))
#define BIT_SHIFT_LDO_HV5_DUMMY_8821C 14
#define BIT_MASK_LDO_HV5_DUMMY_8821C 0x3
-#define BIT_LDO_HV5_DUMMY_8821C(x) (((x) & BIT_MASK_LDO_HV5_DUMMY_8821C) << BIT_SHIFT_LDO_HV5_DUMMY_8821C)
-#define BIT_GET_LDO_HV5_DUMMY_8821C(x) (((x) >> BIT_SHIFT_LDO_HV5_DUMMY_8821C) & BIT_MASK_LDO_HV5_DUMMY_8821C)
-
+#define BIT_LDO_HV5_DUMMY_8821C(x) \
+ (((x) & BIT_MASK_LDO_HV5_DUMMY_8821C) << BIT_SHIFT_LDO_HV5_DUMMY_8821C)
+#define BITS_LDO_HV5_DUMMY_8821C \
+ (BIT_MASK_LDO_HV5_DUMMY_8821C << BIT_SHIFT_LDO_HV5_DUMMY_8821C)
+#define BIT_CLEAR_LDO_HV5_DUMMY_8821C(x) ((x) & (~BITS_LDO_HV5_DUMMY_8821C))
+#define BIT_GET_LDO_HV5_DUMMY_8821C(x) \
+ (((x) >> BIT_SHIFT_LDO_HV5_DUMMY_8821C) & BIT_MASK_LDO_HV5_DUMMY_8821C)
+#define BIT_SET_LDO_HV5_DUMMY_8821C(x, v) \
+ (BIT_CLEAR_LDO_HV5_DUMMY_8821C(x) | BIT_LDO_HV5_DUMMY_8821C(v))
#define BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8821C 12
#define BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8821C 0x3
-#define BIT_REG_VTUNE33_BIT0_TO_BIT1_8821C(x) (((x) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8821C) << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8821C)
-#define BIT_GET_REG_VTUNE33_BIT0_TO_BIT1_8821C(x) (((x) >> BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8821C) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8821C)
-
+#define BIT_REG_VTUNE33_BIT0_TO_BIT1_8821C(x) \
+ (((x) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8821C) \
+ << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8821C)
+#define BITS_REG_VTUNE33_BIT0_TO_BIT1_8821C \
+ (BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8821C \
+ << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8821C)
+#define BIT_CLEAR_REG_VTUNE33_BIT0_TO_BIT1_8821C(x) \
+ ((x) & (~BITS_REG_VTUNE33_BIT0_TO_BIT1_8821C))
+#define BIT_GET_REG_VTUNE33_BIT0_TO_BIT1_8821C(x) \
+ (((x) >> BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8821C) & \
+ BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8821C)
+#define BIT_SET_REG_VTUNE33_BIT0_TO_BIT1_8821C(x, v) \
+ (BIT_CLEAR_REG_VTUNE33_BIT0_TO_BIT1_8821C(x) | \
+ BIT_REG_VTUNE33_BIT0_TO_BIT1_8821C(v))
#define BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8821C 10
#define BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8821C 0x3
-#define BIT_REG_STANDBY33_BIT0_TO_BIT1_8821C(x) (((x) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8821C) << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8821C)
-#define BIT_GET_REG_STANDBY33_BIT0_TO_BIT1_8821C(x) (((x) >> BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8821C) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8821C)
-
+#define BIT_REG_STANDBY33_BIT0_TO_BIT1_8821C(x) \
+ (((x) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8821C) \
+ << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8821C)
+#define BITS_REG_STANDBY33_BIT0_TO_BIT1_8821C \
+ (BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8821C \
+ << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8821C)
+#define BIT_CLEAR_REG_STANDBY33_BIT0_TO_BIT1_8821C(x) \
+ ((x) & (~BITS_REG_STANDBY33_BIT0_TO_BIT1_8821C))
+#define BIT_GET_REG_STANDBY33_BIT0_TO_BIT1_8821C(x) \
+ (((x) >> BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8821C) & \
+ BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8821C)
+#define BIT_SET_REG_STANDBY33_BIT0_TO_BIT1_8821C(x, v) \
+ (BIT_CLEAR_REG_STANDBY33_BIT0_TO_BIT1_8821C(x) | \
+ BIT_REG_STANDBY33_BIT0_TO_BIT1_8821C(v))
#define BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8821C 8
#define BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8821C 0x3
-#define BIT_REG_LOAD33_BIT0_TO_BIT1_8821C(x) (((x) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8821C) << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8821C)
-#define BIT_GET_REG_LOAD33_BIT0_TO_BIT1_8821C(x) (((x) >> BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8821C) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8821C)
+#define BIT_REG_LOAD33_BIT0_TO_BIT1_8821C(x) \
+ (((x) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8821C) \
+ << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8821C)
+#define BITS_REG_LOAD33_BIT0_TO_BIT1_8821C \
+ (BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8821C \
+ << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8821C)
+#define BIT_CLEAR_REG_LOAD33_BIT0_TO_BIT1_8821C(x) \
+ ((x) & (~BITS_REG_LOAD33_BIT0_TO_BIT1_8821C))
+#define BIT_GET_REG_LOAD33_BIT0_TO_BIT1_8821C(x) \
+ (((x) >> BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8821C) & \
+ BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8821C)
+#define BIT_SET_REG_LOAD33_BIT0_TO_BIT1_8821C(x, v) \
+ (BIT_CLEAR_REG_LOAD33_BIT0_TO_BIT1_8821C(x) | \
+ BIT_REG_LOAD33_BIT0_TO_BIT1_8821C(v))
#define BIT_REG_BYPASS_L_8821C BIT(7)
#define BIT_REG_LDOF_L_8821C BIT(6)
@@ -992,8 +1580,14 @@
#define BIT_SHIFT_CFC_L_8821C 1
#define BIT_MASK_CFC_L_8821C 0x3
-#define BIT_CFC_L_8821C(x) (((x) & BIT_MASK_CFC_L_8821C) << BIT_SHIFT_CFC_L_8821C)
-#define BIT_GET_CFC_L_8821C(x) (((x) >> BIT_SHIFT_CFC_L_8821C) & BIT_MASK_CFC_L_8821C)
+#define BIT_CFC_L_8821C(x) \
+ (((x) & BIT_MASK_CFC_L_8821C) << BIT_SHIFT_CFC_L_8821C)
+#define BITS_CFC_L_8821C (BIT_MASK_CFC_L_8821C << BIT_SHIFT_CFC_L_8821C)
+#define BIT_CLEAR_CFC_L_8821C(x) ((x) & (~BITS_CFC_L_8821C))
+#define BIT_GET_CFC_L_8821C(x) \
+ (((x) >> BIT_SHIFT_CFC_L_8821C) & BIT_MASK_CFC_L_8821C)
+#define BIT_SET_CFC_L_8821C(x, v) \
+ (BIT_CLEAR_CFC_L_8821C(x) | BIT_CFC_L_8821C(v))
#define BIT_REG_TYPE_L_8821C BIT(0)
@@ -1002,7 +1596,11 @@
#define BIT_SHIFT_RPWM_8821C 24
#define BIT_MASK_RPWM_8821C 0xff
#define BIT_RPWM_8821C(x) (((x) & BIT_MASK_RPWM_8821C) << BIT_SHIFT_RPWM_8821C)
-#define BIT_GET_RPWM_8821C(x) (((x) >> BIT_SHIFT_RPWM_8821C) & BIT_MASK_RPWM_8821C)
+#define BITS_RPWM_8821C (BIT_MASK_RPWM_8821C << BIT_SHIFT_RPWM_8821C)
+#define BIT_CLEAR_RPWM_8821C(x) ((x) & (~BITS_RPWM_8821C))
+#define BIT_GET_RPWM_8821C(x) \
+ (((x) >> BIT_SHIFT_RPWM_8821C) & BIT_MASK_RPWM_8821C)
+#define BIT_SET_RPWM_8821C(x, v) (BIT_CLEAR_RPWM_8821C(x) | BIT_RPWM_8821C(v))
#define BIT_ANA_PORT_EN_8821C BIT(22)
#define BIT_MAC_PORT_EN_8821C BIT(21)
@@ -1011,16 +1609,29 @@
#define BIT_SHIFT_ROM_PGE_8821C 16
#define BIT_MASK_ROM_PGE_8821C 0x7
-#define BIT_ROM_PGE_8821C(x) (((x) & BIT_MASK_ROM_PGE_8821C) << BIT_SHIFT_ROM_PGE_8821C)
-#define BIT_GET_ROM_PGE_8821C(x) (((x) >> BIT_SHIFT_ROM_PGE_8821C) & BIT_MASK_ROM_PGE_8821C)
+#define BIT_ROM_PGE_8821C(x) \
+ (((x) & BIT_MASK_ROM_PGE_8821C) << BIT_SHIFT_ROM_PGE_8821C)
+#define BITS_ROM_PGE_8821C (BIT_MASK_ROM_PGE_8821C << BIT_SHIFT_ROM_PGE_8821C)
+#define BIT_CLEAR_ROM_PGE_8821C(x) ((x) & (~BITS_ROM_PGE_8821C))
+#define BIT_GET_ROM_PGE_8821C(x) \
+ (((x) >> BIT_SHIFT_ROM_PGE_8821C) & BIT_MASK_ROM_PGE_8821C)
+#define BIT_SET_ROM_PGE_8821C(x, v) \
+ (BIT_CLEAR_ROM_PGE_8821C(x) | BIT_ROM_PGE_8821C(v))
#define BIT_FW_INIT_RDY_8821C BIT(15)
#define BIT_FW_DW_RDY_8821C BIT(14)
#define BIT_SHIFT_CPU_CLK_SEL_8821C 12
#define BIT_MASK_CPU_CLK_SEL_8821C 0x3
-#define BIT_CPU_CLK_SEL_8821C(x) (((x) & BIT_MASK_CPU_CLK_SEL_8821C) << BIT_SHIFT_CPU_CLK_SEL_8821C)
-#define BIT_GET_CPU_CLK_SEL_8821C(x) (((x) >> BIT_SHIFT_CPU_CLK_SEL_8821C) & BIT_MASK_CPU_CLK_SEL_8821C)
+#define BIT_CPU_CLK_SEL_8821C(x) \
+ (((x) & BIT_MASK_CPU_CLK_SEL_8821C) << BIT_SHIFT_CPU_CLK_SEL_8821C)
+#define BITS_CPU_CLK_SEL_8821C \
+ (BIT_MASK_CPU_CLK_SEL_8821C << BIT_SHIFT_CPU_CLK_SEL_8821C)
+#define BIT_CLEAR_CPU_CLK_SEL_8821C(x) ((x) & (~BITS_CPU_CLK_SEL_8821C))
+#define BIT_GET_CPU_CLK_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_CPU_CLK_SEL_8821C) & BIT_MASK_CPU_CLK_SEL_8821C)
+#define BIT_SET_CPU_CLK_SEL_8821C(x, v) \
+ (BIT_CLEAR_CPU_CLK_SEL_8821C(x) | BIT_CPU_CLK_SEL_8821C(v))
#define BIT_CCLK_CHG_MASK_8821C BIT(11)
#define BIT_EMEM__TXBUF_CHKSUM_OK_8821C BIT(10)
@@ -1037,39 +1648,68 @@
/* 2 REG_MCU_TST_CFG_8821C */
-#define BIT_SHIFT_LBKTST_8821C 0
-#define BIT_MASK_LBKTST_8821C 0xffff
-#define BIT_LBKTST_8821C(x) (((x) & BIT_MASK_LBKTST_8821C) << BIT_SHIFT_LBKTST_8821C)
-#define BIT_GET_LBKTST_8821C(x) (((x) >> BIT_SHIFT_LBKTST_8821C) & BIT_MASK_LBKTST_8821C)
-
+#define BIT_SHIFT_C2H_MSG_8821C 0
+#define BIT_MASK_C2H_MSG_8821C 0xffff
+#define BIT_C2H_MSG_8821C(x) \
+ (((x) & BIT_MASK_C2H_MSG_8821C) << BIT_SHIFT_C2H_MSG_8821C)
+#define BITS_C2H_MSG_8821C (BIT_MASK_C2H_MSG_8821C << BIT_SHIFT_C2H_MSG_8821C)
+#define BIT_CLEAR_C2H_MSG_8821C(x) ((x) & (~BITS_C2H_MSG_8821C))
+#define BIT_GET_C2H_MSG_8821C(x) \
+ (((x) >> BIT_SHIFT_C2H_MSG_8821C) & BIT_MASK_C2H_MSG_8821C)
+#define BIT_SET_C2H_MSG_8821C(x, v) \
+ (BIT_CLEAR_C2H_MSG_8821C(x) | BIT_C2H_MSG_8821C(v))
/* 2 REG_HMEBOX_E0_E1_8821C */
#define BIT_SHIFT_HOST_MSG_E1_8821C 16
#define BIT_MASK_HOST_MSG_E1_8821C 0xffff
-#define BIT_HOST_MSG_E1_8821C(x) (((x) & BIT_MASK_HOST_MSG_E1_8821C) << BIT_SHIFT_HOST_MSG_E1_8821C)
-#define BIT_GET_HOST_MSG_E1_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_E1_8821C) & BIT_MASK_HOST_MSG_E1_8821C)
-
+#define BIT_HOST_MSG_E1_8821C(x) \
+ (((x) & BIT_MASK_HOST_MSG_E1_8821C) << BIT_SHIFT_HOST_MSG_E1_8821C)
+#define BITS_HOST_MSG_E1_8821C \
+ (BIT_MASK_HOST_MSG_E1_8821C << BIT_SHIFT_HOST_MSG_E1_8821C)
+#define BIT_CLEAR_HOST_MSG_E1_8821C(x) ((x) & (~BITS_HOST_MSG_E1_8821C))
+#define BIT_GET_HOST_MSG_E1_8821C(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_E1_8821C) & BIT_MASK_HOST_MSG_E1_8821C)
+#define BIT_SET_HOST_MSG_E1_8821C(x, v) \
+ (BIT_CLEAR_HOST_MSG_E1_8821C(x) | BIT_HOST_MSG_E1_8821C(v))
#define BIT_SHIFT_HOST_MSG_E0_8821C 0
#define BIT_MASK_HOST_MSG_E0_8821C 0xffff
-#define BIT_HOST_MSG_E0_8821C(x) (((x) & BIT_MASK_HOST_MSG_E0_8821C) << BIT_SHIFT_HOST_MSG_E0_8821C)
-#define BIT_GET_HOST_MSG_E0_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_E0_8821C) & BIT_MASK_HOST_MSG_E0_8821C)
-
+#define BIT_HOST_MSG_E0_8821C(x) \
+ (((x) & BIT_MASK_HOST_MSG_E0_8821C) << BIT_SHIFT_HOST_MSG_E0_8821C)
+#define BITS_HOST_MSG_E0_8821C \
+ (BIT_MASK_HOST_MSG_E0_8821C << BIT_SHIFT_HOST_MSG_E0_8821C)
+#define BIT_CLEAR_HOST_MSG_E0_8821C(x) ((x) & (~BITS_HOST_MSG_E0_8821C))
+#define BIT_GET_HOST_MSG_E0_8821C(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_E0_8821C) & BIT_MASK_HOST_MSG_E0_8821C)
+#define BIT_SET_HOST_MSG_E0_8821C(x, v) \
+ (BIT_CLEAR_HOST_MSG_E0_8821C(x) | BIT_HOST_MSG_E0_8821C(v))
/* 2 REG_HMEBOX_E2_E3_8821C */
#define BIT_SHIFT_HOST_MSG_E3_8821C 16
#define BIT_MASK_HOST_MSG_E3_8821C 0xffff
-#define BIT_HOST_MSG_E3_8821C(x) (((x) & BIT_MASK_HOST_MSG_E3_8821C) << BIT_SHIFT_HOST_MSG_E3_8821C)
-#define BIT_GET_HOST_MSG_E3_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_E3_8821C) & BIT_MASK_HOST_MSG_E3_8821C)
-
+#define BIT_HOST_MSG_E3_8821C(x) \
+ (((x) & BIT_MASK_HOST_MSG_E3_8821C) << BIT_SHIFT_HOST_MSG_E3_8821C)
+#define BITS_HOST_MSG_E3_8821C \
+ (BIT_MASK_HOST_MSG_E3_8821C << BIT_SHIFT_HOST_MSG_E3_8821C)
+#define BIT_CLEAR_HOST_MSG_E3_8821C(x) ((x) & (~BITS_HOST_MSG_E3_8821C))
+#define BIT_GET_HOST_MSG_E3_8821C(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_E3_8821C) & BIT_MASK_HOST_MSG_E3_8821C)
+#define BIT_SET_HOST_MSG_E3_8821C(x, v) \
+ (BIT_CLEAR_HOST_MSG_E3_8821C(x) | BIT_HOST_MSG_E3_8821C(v))
#define BIT_SHIFT_HOST_MSG_E2_8821C 0
#define BIT_MASK_HOST_MSG_E2_8821C 0xffff
-#define BIT_HOST_MSG_E2_8821C(x) (((x) & BIT_MASK_HOST_MSG_E2_8821C) << BIT_SHIFT_HOST_MSG_E2_8821C)
-#define BIT_GET_HOST_MSG_E2_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_E2_8821C) & BIT_MASK_HOST_MSG_E2_8821C)
-
+#define BIT_HOST_MSG_E2_8821C(x) \
+ (((x) & BIT_MASK_HOST_MSG_E2_8821C) << BIT_SHIFT_HOST_MSG_E2_8821C)
+#define BITS_HOST_MSG_E2_8821C \
+ (BIT_MASK_HOST_MSG_E2_8821C << BIT_SHIFT_HOST_MSG_E2_8821C)
+#define BIT_CLEAR_HOST_MSG_E2_8821C(x) ((x) & (~BITS_HOST_MSG_E2_8821C))
+#define BIT_GET_HOST_MSG_E2_8821C(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_E2_8821C) & BIT_MASK_HOST_MSG_E2_8821C)
+#define BIT_SET_HOST_MSG_E2_8821C(x, v) \
+ (BIT_CLEAR_HOST_MSG_E2_8821C(x) | BIT_HOST_MSG_E2_8821C(v))
/* 2 REG_WLLPS_CTRL_8821C */
#define BIT_WLLPSOP_EABM_8821C BIT(31)
@@ -1086,14 +1726,35 @@
#define BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8821C 12
#define BIT_MASK_LPLDH12_VADJ_STEP_DN_8821C 0xf
-#define BIT_LPLDH12_VADJ_STEP_DN_8821C(x) (((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8821C) << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8821C)
-#define BIT_GET_LPLDH12_VADJ_STEP_DN_8821C(x) (((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8821C) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8821C)
-
+#define BIT_LPLDH12_VADJ_STEP_DN_8821C(x) \
+ (((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8821C) \
+ << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8821C)
+#define BITS_LPLDH12_VADJ_STEP_DN_8821C \
+ (BIT_MASK_LPLDH12_VADJ_STEP_DN_8821C \
+ << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8821C)
+#define BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8821C(x) \
+ ((x) & (~BITS_LPLDH12_VADJ_STEP_DN_8821C))
+#define BIT_GET_LPLDH12_VADJ_STEP_DN_8821C(x) \
+ (((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8821C) & \
+ BIT_MASK_LPLDH12_VADJ_STEP_DN_8821C)
+#define BIT_SET_LPLDH12_VADJ_STEP_DN_8821C(x, v) \
+ (BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8821C(x) | \
+ BIT_LPLDH12_VADJ_STEP_DN_8821C(v))
#define BIT_SHIFT_V15ADJ_L1_STEP_DN_8821C 8
#define BIT_MASK_V15ADJ_L1_STEP_DN_8821C 0x7
-#define BIT_V15ADJ_L1_STEP_DN_8821C(x) (((x) & BIT_MASK_V15ADJ_L1_STEP_DN_8821C) << BIT_SHIFT_V15ADJ_L1_STEP_DN_8821C)
-#define BIT_GET_V15ADJ_L1_STEP_DN_8821C(x) (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN_8821C) & BIT_MASK_V15ADJ_L1_STEP_DN_8821C)
+#define BIT_V15ADJ_L1_STEP_DN_8821C(x) \
+ (((x) & BIT_MASK_V15ADJ_L1_STEP_DN_8821C) \
+ << BIT_SHIFT_V15ADJ_L1_STEP_DN_8821C)
+#define BITS_V15ADJ_L1_STEP_DN_8821C \
+ (BIT_MASK_V15ADJ_L1_STEP_DN_8821C << BIT_SHIFT_V15ADJ_L1_STEP_DN_8821C)
+#define BIT_CLEAR_V15ADJ_L1_STEP_DN_8821C(x) \
+ ((x) & (~BITS_V15ADJ_L1_STEP_DN_8821C))
+#define BIT_GET_V15ADJ_L1_STEP_DN_8821C(x) \
+ (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN_8821C) & \
+ BIT_MASK_V15ADJ_L1_STEP_DN_8821C)
+#define BIT_SET_V15ADJ_L1_STEP_DN_8821C(x, v) \
+ (BIT_CLEAR_V15ADJ_L1_STEP_DN_8821C(x) | BIT_V15ADJ_L1_STEP_DN_8821C(v))
#define BIT_REGU_32K_CLK_EN_8821C BIT(1)
#define BIT_WL_LPS_EN_8821C BIT(0)
@@ -1105,105 +1766,198 @@
#define BIT_SHIFT_REF_SEL_8821C 25
#define BIT_MASK_REF_SEL_8821C 0xf
-#define BIT_REF_SEL_8821C(x) (((x) & BIT_MASK_REF_SEL_8821C) << BIT_SHIFT_REF_SEL_8821C)
-#define BIT_GET_REF_SEL_8821C(x) (((x) >> BIT_SHIFT_REF_SEL_8821C) & BIT_MASK_REF_SEL_8821C)
-
+#define BIT_REF_SEL_8821C(x) \
+ (((x) & BIT_MASK_REF_SEL_8821C) << BIT_SHIFT_REF_SEL_8821C)
+#define BITS_REF_SEL_8821C (BIT_MASK_REF_SEL_8821C << BIT_SHIFT_REF_SEL_8821C)
+#define BIT_CLEAR_REF_SEL_8821C(x) ((x) & (~BITS_REF_SEL_8821C))
+#define BIT_GET_REF_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_REF_SEL_8821C) & BIT_MASK_REF_SEL_8821C)
+#define BIT_SET_REF_SEL_8821C(x, v) \
+ (BIT_CLEAR_REF_SEL_8821C(x) | BIT_REF_SEL_8821C(v))
#define BIT_SHIFT_F0F_SDM_8821C 12
#define BIT_MASK_F0F_SDM_8821C 0x1fff
-#define BIT_F0F_SDM_8821C(x) (((x) & BIT_MASK_F0F_SDM_8821C) << BIT_SHIFT_F0F_SDM_8821C)
-#define BIT_GET_F0F_SDM_8821C(x) (((x) >> BIT_SHIFT_F0F_SDM_8821C) & BIT_MASK_F0F_SDM_8821C)
-
+#define BIT_F0F_SDM_8821C(x) \
+ (((x) & BIT_MASK_F0F_SDM_8821C) << BIT_SHIFT_F0F_SDM_8821C)
+#define BITS_F0F_SDM_8821C (BIT_MASK_F0F_SDM_8821C << BIT_SHIFT_F0F_SDM_8821C)
+#define BIT_CLEAR_F0F_SDM_8821C(x) ((x) & (~BITS_F0F_SDM_8821C))
+#define BIT_GET_F0F_SDM_8821C(x) \
+ (((x) >> BIT_SHIFT_F0F_SDM_8821C) & BIT_MASK_F0F_SDM_8821C)
+#define BIT_SET_F0F_SDM_8821C(x, v) \
+ (BIT_CLEAR_F0F_SDM_8821C(x) | BIT_F0F_SDM_8821C(v))
#define BIT_SHIFT_F0N_SDM_8821C 9
#define BIT_MASK_F0N_SDM_8821C 0x7
-#define BIT_F0N_SDM_8821C(x) (((x) & BIT_MASK_F0N_SDM_8821C) << BIT_SHIFT_F0N_SDM_8821C)
-#define BIT_GET_F0N_SDM_8821C(x) (((x) >> BIT_SHIFT_F0N_SDM_8821C) & BIT_MASK_F0N_SDM_8821C)
-
+#define BIT_F0N_SDM_8821C(x) \
+ (((x) & BIT_MASK_F0N_SDM_8821C) << BIT_SHIFT_F0N_SDM_8821C)
+#define BITS_F0N_SDM_8821C (BIT_MASK_F0N_SDM_8821C << BIT_SHIFT_F0N_SDM_8821C)
+#define BIT_CLEAR_F0N_SDM_8821C(x) ((x) & (~BITS_F0N_SDM_8821C))
+#define BIT_GET_F0N_SDM_8821C(x) \
+ (((x) >> BIT_SHIFT_F0N_SDM_8821C) & BIT_MASK_F0N_SDM_8821C)
+#define BIT_SET_F0N_SDM_8821C(x, v) \
+ (BIT_CLEAR_F0N_SDM_8821C(x) | BIT_F0N_SDM_8821C(v))
#define BIT_SHIFT_DIVN_SDM_8821C 3
#define BIT_MASK_DIVN_SDM_8821C 0x3f
-#define BIT_DIVN_SDM_8821C(x) (((x) & BIT_MASK_DIVN_SDM_8821C) << BIT_SHIFT_DIVN_SDM_8821C)
-#define BIT_GET_DIVN_SDM_8821C(x) (((x) >> BIT_SHIFT_DIVN_SDM_8821C) & BIT_MASK_DIVN_SDM_8821C)
-
+#define BIT_DIVN_SDM_8821C(x) \
+ (((x) & BIT_MASK_DIVN_SDM_8821C) << BIT_SHIFT_DIVN_SDM_8821C)
+#define BITS_DIVN_SDM_8821C \
+ (BIT_MASK_DIVN_SDM_8821C << BIT_SHIFT_DIVN_SDM_8821C)
+#define BIT_CLEAR_DIVN_SDM_8821C(x) ((x) & (~BITS_DIVN_SDM_8821C))
+#define BIT_GET_DIVN_SDM_8821C(x) \
+ (((x) >> BIT_SHIFT_DIVN_SDM_8821C) & BIT_MASK_DIVN_SDM_8821C)
+#define BIT_SET_DIVN_SDM_8821C(x, v) \
+ (BIT_CLEAR_DIVN_SDM_8821C(x) | BIT_DIVN_SDM_8821C(v))
/* 2 REG_GPIO_DEBOUNCE_CTRL_8821C */
#define BIT_WLGP_DBC1EN_8821C BIT(15)
#define BIT_SHIFT_WLGP_DBC1_8821C 8
#define BIT_MASK_WLGP_DBC1_8821C 0xf
-#define BIT_WLGP_DBC1_8821C(x) (((x) & BIT_MASK_WLGP_DBC1_8821C) << BIT_SHIFT_WLGP_DBC1_8821C)
-#define BIT_GET_WLGP_DBC1_8821C(x) (((x) >> BIT_SHIFT_WLGP_DBC1_8821C) & BIT_MASK_WLGP_DBC1_8821C)
+#define BIT_WLGP_DBC1_8821C(x) \
+ (((x) & BIT_MASK_WLGP_DBC1_8821C) << BIT_SHIFT_WLGP_DBC1_8821C)
+#define BITS_WLGP_DBC1_8821C \
+ (BIT_MASK_WLGP_DBC1_8821C << BIT_SHIFT_WLGP_DBC1_8821C)
+#define BIT_CLEAR_WLGP_DBC1_8821C(x) ((x) & (~BITS_WLGP_DBC1_8821C))
+#define BIT_GET_WLGP_DBC1_8821C(x) \
+ (((x) >> BIT_SHIFT_WLGP_DBC1_8821C) & BIT_MASK_WLGP_DBC1_8821C)
+#define BIT_SET_WLGP_DBC1_8821C(x, v) \
+ (BIT_CLEAR_WLGP_DBC1_8821C(x) | BIT_WLGP_DBC1_8821C(v))
#define BIT_WLGP_DBC0EN_8821C BIT(7)
#define BIT_SHIFT_WLGP_DBC0_8821C 0
#define BIT_MASK_WLGP_DBC0_8821C 0xf
-#define BIT_WLGP_DBC0_8821C(x) (((x) & BIT_MASK_WLGP_DBC0_8821C) << BIT_SHIFT_WLGP_DBC0_8821C)
-#define BIT_GET_WLGP_DBC0_8821C(x) (((x) >> BIT_SHIFT_WLGP_DBC0_8821C) & BIT_MASK_WLGP_DBC0_8821C)
-
+#define BIT_WLGP_DBC0_8821C(x) \
+ (((x) & BIT_MASK_WLGP_DBC0_8821C) << BIT_SHIFT_WLGP_DBC0_8821C)
+#define BITS_WLGP_DBC0_8821C \
+ (BIT_MASK_WLGP_DBC0_8821C << BIT_SHIFT_WLGP_DBC0_8821C)
+#define BIT_CLEAR_WLGP_DBC0_8821C(x) ((x) & (~BITS_WLGP_DBC0_8821C))
+#define BIT_GET_WLGP_DBC0_8821C(x) \
+ (((x) >> BIT_SHIFT_WLGP_DBC0_8821C) & BIT_MASK_WLGP_DBC0_8821C)
+#define BIT_SET_WLGP_DBC0_8821C(x, v) \
+ (BIT_CLEAR_WLGP_DBC0_8821C(x) | BIT_WLGP_DBC0_8821C(v))
/* 2 REG_RPWM2_8821C */
#define BIT_SHIFT_RPWM2_8821C 16
#define BIT_MASK_RPWM2_8821C 0xffff
-#define BIT_RPWM2_8821C(x) (((x) & BIT_MASK_RPWM2_8821C) << BIT_SHIFT_RPWM2_8821C)
-#define BIT_GET_RPWM2_8821C(x) (((x) >> BIT_SHIFT_RPWM2_8821C) & BIT_MASK_RPWM2_8821C)
-
+#define BIT_RPWM2_8821C(x) \
+ (((x) & BIT_MASK_RPWM2_8821C) << BIT_SHIFT_RPWM2_8821C)
+#define BITS_RPWM2_8821C (BIT_MASK_RPWM2_8821C << BIT_SHIFT_RPWM2_8821C)
+#define BIT_CLEAR_RPWM2_8821C(x) ((x) & (~BITS_RPWM2_8821C))
+#define BIT_GET_RPWM2_8821C(x) \
+ (((x) >> BIT_SHIFT_RPWM2_8821C) & BIT_MASK_RPWM2_8821C)
+#define BIT_SET_RPWM2_8821C(x, v) \
+ (BIT_CLEAR_RPWM2_8821C(x) | BIT_RPWM2_8821C(v))
/* 2 REG_SYSON_FSM_MON_8821C */
#define BIT_SHIFT_FSM_MON_SEL_8821C 24
#define BIT_MASK_FSM_MON_SEL_8821C 0x7
-#define BIT_FSM_MON_SEL_8821C(x) (((x) & BIT_MASK_FSM_MON_SEL_8821C) << BIT_SHIFT_FSM_MON_SEL_8821C)
-#define BIT_GET_FSM_MON_SEL_8821C(x) (((x) >> BIT_SHIFT_FSM_MON_SEL_8821C) & BIT_MASK_FSM_MON_SEL_8821C)
+#define BIT_FSM_MON_SEL_8821C(x) \
+ (((x) & BIT_MASK_FSM_MON_SEL_8821C) << BIT_SHIFT_FSM_MON_SEL_8821C)
+#define BITS_FSM_MON_SEL_8821C \
+ (BIT_MASK_FSM_MON_SEL_8821C << BIT_SHIFT_FSM_MON_SEL_8821C)
+#define BIT_CLEAR_FSM_MON_SEL_8821C(x) ((x) & (~BITS_FSM_MON_SEL_8821C))
+#define BIT_GET_FSM_MON_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_FSM_MON_SEL_8821C) & BIT_MASK_FSM_MON_SEL_8821C)
+#define BIT_SET_FSM_MON_SEL_8821C(x, v) \
+ (BIT_CLEAR_FSM_MON_SEL_8821C(x) | BIT_FSM_MON_SEL_8821C(v))
#define BIT_DOP_ELDO_8821C BIT(23)
#define BIT_FSM_MON_UPD_8821C BIT(15)
#define BIT_SHIFT_FSM_PAR_8821C 0
#define BIT_MASK_FSM_PAR_8821C 0x7fff
-#define BIT_FSM_PAR_8821C(x) (((x) & BIT_MASK_FSM_PAR_8821C) << BIT_SHIFT_FSM_PAR_8821C)
-#define BIT_GET_FSM_PAR_8821C(x) (((x) >> BIT_SHIFT_FSM_PAR_8821C) & BIT_MASK_FSM_PAR_8821C)
-
+#define BIT_FSM_PAR_8821C(x) \
+ (((x) & BIT_MASK_FSM_PAR_8821C) << BIT_SHIFT_FSM_PAR_8821C)
+#define BITS_FSM_PAR_8821C (BIT_MASK_FSM_PAR_8821C << BIT_SHIFT_FSM_PAR_8821C)
+#define BIT_CLEAR_FSM_PAR_8821C(x) ((x) & (~BITS_FSM_PAR_8821C))
+#define BIT_GET_FSM_PAR_8821C(x) \
+ (((x) >> BIT_SHIFT_FSM_PAR_8821C) & BIT_MASK_FSM_PAR_8821C)
+#define BIT_SET_FSM_PAR_8821C(x, v) \
+ (BIT_CLEAR_FSM_PAR_8821C(x) | BIT_FSM_PAR_8821C(v))
/* 2 REG_AFE_CTRL6_8821C */
#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C 0
#define BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C 0x7
-#define BIT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C(x) (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C) << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C)
-#define BIT_GET_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C(x) (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C)
-
+#define BIT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C(x) \
+ (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C) \
+ << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C)
+#define BITS_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C \
+ (BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C \
+ << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C)
+#define BIT_CLEAR_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C(x) \
+ ((x) & (~BITS_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C))
+#define BIT_GET_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C(x) \
+ (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C) & \
+ BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C)
+#define BIT_SET_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C(x, v) \
+ (BIT_CLEAR_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C(x) | \
+ BIT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C(v))
/* 2 REG_PMC_DBG_CTRL1_8821C */
#define BIT_BT_INT_EN_8821C BIT(31)
#define BIT_SHIFT_RD_WR_WIFI_BT_INFO_8821C 16
#define BIT_MASK_RD_WR_WIFI_BT_INFO_8821C 0x7fff
-#define BIT_RD_WR_WIFI_BT_INFO_8821C(x) (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8821C) << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8821C)
-#define BIT_GET_RD_WR_WIFI_BT_INFO_8821C(x) (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8821C) & BIT_MASK_RD_WR_WIFI_BT_INFO_8821C)
+#define BIT_RD_WR_WIFI_BT_INFO_8821C(x) \
+ (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8821C) \
+ << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8821C)
+#define BITS_RD_WR_WIFI_BT_INFO_8821C \
+ (BIT_MASK_RD_WR_WIFI_BT_INFO_8821C \
+ << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8821C)
+#define BIT_CLEAR_RD_WR_WIFI_BT_INFO_8821C(x) \
+ ((x) & (~BITS_RD_WR_WIFI_BT_INFO_8821C))
+#define BIT_GET_RD_WR_WIFI_BT_INFO_8821C(x) \
+ (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8821C) & \
+ BIT_MASK_RD_WR_WIFI_BT_INFO_8821C)
+#define BIT_SET_RD_WR_WIFI_BT_INFO_8821C(x, v) \
+ (BIT_CLEAR_RD_WR_WIFI_BT_INFO_8821C(x) | \
+ BIT_RD_WR_WIFI_BT_INFO_8821C(v))
#define BIT_PMC_WR_OVF_8821C BIT(8)
#define BIT_SHIFT_WLPMC_ERRINT_8821C 0
#define BIT_MASK_WLPMC_ERRINT_8821C 0xff
-#define BIT_WLPMC_ERRINT_8821C(x) (((x) & BIT_MASK_WLPMC_ERRINT_8821C) << BIT_SHIFT_WLPMC_ERRINT_8821C)
-#define BIT_GET_WLPMC_ERRINT_8821C(x) (((x) >> BIT_SHIFT_WLPMC_ERRINT_8821C) & BIT_MASK_WLPMC_ERRINT_8821C)
-
+#define BIT_WLPMC_ERRINT_8821C(x) \
+ (((x) & BIT_MASK_WLPMC_ERRINT_8821C) << BIT_SHIFT_WLPMC_ERRINT_8821C)
+#define BITS_WLPMC_ERRINT_8821C \
+ (BIT_MASK_WLPMC_ERRINT_8821C << BIT_SHIFT_WLPMC_ERRINT_8821C)
+#define BIT_CLEAR_WLPMC_ERRINT_8821C(x) ((x) & (~BITS_WLPMC_ERRINT_8821C))
+#define BIT_GET_WLPMC_ERRINT_8821C(x) \
+ (((x) >> BIT_SHIFT_WLPMC_ERRINT_8821C) & BIT_MASK_WLPMC_ERRINT_8821C)
+#define BIT_SET_WLPMC_ERRINT_8821C(x, v) \
+ (BIT_CLEAR_WLPMC_ERRINT_8821C(x) | BIT_WLPMC_ERRINT_8821C(v))
/* 2 REG_AFE_CTRL7_8821C */
#define BIT_SHIFT_SEL_V_8821C 30
#define BIT_MASK_SEL_V_8821C 0x3
-#define BIT_SEL_V_8821C(x) (((x) & BIT_MASK_SEL_V_8821C) << BIT_SHIFT_SEL_V_8821C)
-#define BIT_GET_SEL_V_8821C(x) (((x) >> BIT_SHIFT_SEL_V_8821C) & BIT_MASK_SEL_V_8821C)
+#define BIT_SEL_V_8821C(x) \
+ (((x) & BIT_MASK_SEL_V_8821C) << BIT_SHIFT_SEL_V_8821C)
+#define BITS_SEL_V_8821C (BIT_MASK_SEL_V_8821C << BIT_SHIFT_SEL_V_8821C)
+#define BIT_CLEAR_SEL_V_8821C(x) ((x) & (~BITS_SEL_V_8821C))
+#define BIT_GET_SEL_V_8821C(x) \
+ (((x) >> BIT_SHIFT_SEL_V_8821C) & BIT_MASK_SEL_V_8821C)
+#define BIT_SET_SEL_V_8821C(x, v) \
+ (BIT_CLEAR_SEL_V_8821C(x) | BIT_SEL_V_8821C(v))
#define BIT_SEL_LDO_PC_8821C BIT(29)
#define BIT_SHIFT_CK_MON_SEL_8821C 26
#define BIT_MASK_CK_MON_SEL_8821C 0x7
-#define BIT_CK_MON_SEL_8821C(x) (((x) & BIT_MASK_CK_MON_SEL_8821C) << BIT_SHIFT_CK_MON_SEL_8821C)
-#define BIT_GET_CK_MON_SEL_8821C(x) (((x) >> BIT_SHIFT_CK_MON_SEL_8821C) & BIT_MASK_CK_MON_SEL_8821C)
+#define BIT_CK_MON_SEL_8821C(x) \
+ (((x) & BIT_MASK_CK_MON_SEL_8821C) << BIT_SHIFT_CK_MON_SEL_8821C)
+#define BITS_CK_MON_SEL_8821C \
+ (BIT_MASK_CK_MON_SEL_8821C << BIT_SHIFT_CK_MON_SEL_8821C)
+#define BIT_CLEAR_CK_MON_SEL_8821C(x) ((x) & (~BITS_CK_MON_SEL_8821C))
+#define BIT_GET_CK_MON_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_CK_MON_SEL_8821C) & BIT_MASK_CK_MON_SEL_8821C)
+#define BIT_SET_CK_MON_SEL_8821C(x, v) \
+ (BIT_CLEAR_CK_MON_SEL_8821C(x) | BIT_CK_MON_SEL_8821C(v))
#define BIT_CK_MON_EN_8821C BIT(25)
#define BIT_FREF_EDGE_8821C BIT(24)
@@ -1239,8 +1993,8 @@
#define BIT_RXOK_MSK_8821C BIT(0)
/* 2 REG_HISR0_8821C */
-#define BIT_TIMEOUT_INTERRUPT2_8821C BIT(31)
-#define BIT_TIMEOUT_INTERRUTP1_8821C BIT(30)
+#define BIT_PSTIMEOUT2_8821C BIT(31)
+#define BIT_PSTIMEOUT1_8821C BIT(30)
#define BIT_PSTIMEOUT_8821C BIT(29)
#define BIT_GTINT4_8821C BIT(28)
#define BIT_GTINT3_8821C BIT(27)
@@ -1331,25 +2085,48 @@
#define BIT_SHIFT_DEBUG_ST_8821C 0
#define BIT_MASK_DEBUG_ST_8821C 0xffffffffL
-#define BIT_DEBUG_ST_8821C(x) (((x) & BIT_MASK_DEBUG_ST_8821C) << BIT_SHIFT_DEBUG_ST_8821C)
-#define BIT_GET_DEBUG_ST_8821C(x) (((x) >> BIT_SHIFT_DEBUG_ST_8821C) & BIT_MASK_DEBUG_ST_8821C)
-
+#define BIT_DEBUG_ST_8821C(x) \
+ (((x) & BIT_MASK_DEBUG_ST_8821C) << BIT_SHIFT_DEBUG_ST_8821C)
+#define BITS_DEBUG_ST_8821C \
+ (BIT_MASK_DEBUG_ST_8821C << BIT_SHIFT_DEBUG_ST_8821C)
+#define BIT_CLEAR_DEBUG_ST_8821C(x) ((x) & (~BITS_DEBUG_ST_8821C))
+#define BIT_GET_DEBUG_ST_8821C(x) \
+ (((x) >> BIT_SHIFT_DEBUG_ST_8821C) & BIT_MASK_DEBUG_ST_8821C)
+#define BIT_SET_DEBUG_ST_8821C(x, v) \
+ (BIT_CLEAR_DEBUG_ST_8821C(x) | BIT_DEBUG_ST_8821C(v))
/* 2 REG_PAD_CTRL2_8821C */
#define BIT_USB3_USB2_TRANSITION_8821C BIT(20)
#define BIT_SHIFT_USB23_SW_MODE_V1_8821C 18
#define BIT_MASK_USB23_SW_MODE_V1_8821C 0x3
-#define BIT_USB23_SW_MODE_V1_8821C(x) (((x) & BIT_MASK_USB23_SW_MODE_V1_8821C) << BIT_SHIFT_USB23_SW_MODE_V1_8821C)
-#define BIT_GET_USB23_SW_MODE_V1_8821C(x) (((x) >> BIT_SHIFT_USB23_SW_MODE_V1_8821C) & BIT_MASK_USB23_SW_MODE_V1_8821C)
+#define BIT_USB23_SW_MODE_V1_8821C(x) \
+ (((x) & BIT_MASK_USB23_SW_MODE_V1_8821C) \
+ << BIT_SHIFT_USB23_SW_MODE_V1_8821C)
+#define BITS_USB23_SW_MODE_V1_8821C \
+ (BIT_MASK_USB23_SW_MODE_V1_8821C << BIT_SHIFT_USB23_SW_MODE_V1_8821C)
+#define BIT_CLEAR_USB23_SW_MODE_V1_8821C(x) \
+ ((x) & (~BITS_USB23_SW_MODE_V1_8821C))
+#define BIT_GET_USB23_SW_MODE_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_USB23_SW_MODE_V1_8821C) & \
+ BIT_MASK_USB23_SW_MODE_V1_8821C)
+#define BIT_SET_USB23_SW_MODE_V1_8821C(x, v) \
+ (BIT_CLEAR_USB23_SW_MODE_V1_8821C(x) | BIT_USB23_SW_MODE_V1_8821C(v))
#define BIT_NO_PDN_CHIPOFF_V1_8821C BIT(17)
#define BIT_RSM_EN_V1_8821C BIT(16)
#define BIT_SHIFT_MATCH_CNT_8821C 8
#define BIT_MASK_MATCH_CNT_8821C 0xff
-#define BIT_MATCH_CNT_8821C(x) (((x) & BIT_MASK_MATCH_CNT_8821C) << BIT_SHIFT_MATCH_CNT_8821C)
-#define BIT_GET_MATCH_CNT_8821C(x) (((x) >> BIT_SHIFT_MATCH_CNT_8821C) & BIT_MASK_MATCH_CNT_8821C)
+#define BIT_MATCH_CNT_8821C(x) \
+ (((x) & BIT_MASK_MATCH_CNT_8821C) << BIT_SHIFT_MATCH_CNT_8821C)
+#define BITS_MATCH_CNT_8821C \
+ (BIT_MASK_MATCH_CNT_8821C << BIT_SHIFT_MATCH_CNT_8821C)
+#define BIT_CLEAR_MATCH_CNT_8821C(x) ((x) & (~BITS_MATCH_CNT_8821C))
+#define BIT_GET_MATCH_CNT_8821C(x) \
+ (((x) >> BIT_SHIFT_MATCH_CNT_8821C) & BIT_MASK_MATCH_CNT_8821C)
+#define BIT_SET_MATCH_CNT_8821C(x, v) \
+ (BIT_CLEAR_MATCH_CNT_8821C(x) | BIT_MATCH_CNT_8821C(v))
#define BIT_LD_B12V_EN_8821C BIT(7)
#define BIT_EECS_IOSEL_V1_8821C BIT(6)
@@ -1365,8 +2142,17 @@
#define BIT_SHIFT_EFUSE_BURN_GNT_8821C 24
#define BIT_MASK_EFUSE_BURN_GNT_8821C 0xff
-#define BIT_EFUSE_BURN_GNT_8821C(x) (((x) & BIT_MASK_EFUSE_BURN_GNT_8821C) << BIT_SHIFT_EFUSE_BURN_GNT_8821C)
-#define BIT_GET_EFUSE_BURN_GNT_8821C(x) (((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8821C) & BIT_MASK_EFUSE_BURN_GNT_8821C)
+#define BIT_EFUSE_BURN_GNT_8821C(x) \
+ (((x) & BIT_MASK_EFUSE_BURN_GNT_8821C) \
+ << BIT_SHIFT_EFUSE_BURN_GNT_8821C)
+#define BITS_EFUSE_BURN_GNT_8821C \
+ (BIT_MASK_EFUSE_BURN_GNT_8821C << BIT_SHIFT_EFUSE_BURN_GNT_8821C)
+#define BIT_CLEAR_EFUSE_BURN_GNT_8821C(x) ((x) & (~BITS_EFUSE_BURN_GNT_8821C))
+#define BIT_GET_EFUSE_BURN_GNT_8821C(x) \
+ (((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8821C) & \
+ BIT_MASK_EFUSE_BURN_GNT_8821C)
+#define BIT_SET_EFUSE_BURN_GNT_8821C(x, v) \
+ (BIT_CLEAR_EFUSE_BURN_GNT_8821C(x) | BIT_EFUSE_BURN_GNT_8821C(v))
#define BIT_STOP_WL_PMC_8821C BIT(9)
#define BIT_STOP_SYM_PMC_8821C BIT(8)
@@ -1378,9 +2164,15 @@
#define BIT_SHIFT_SYSON_REG_ARB_8821C 0
#define BIT_MASK_SYSON_REG_ARB_8821C 0x3
-#define BIT_SYSON_REG_ARB_8821C(x) (((x) & BIT_MASK_SYSON_REG_ARB_8821C) << BIT_SHIFT_SYSON_REG_ARB_8821C)
-#define BIT_GET_SYSON_REG_ARB_8821C(x) (((x) >> BIT_SHIFT_SYSON_REG_ARB_8821C) & BIT_MASK_SYSON_REG_ARB_8821C)
-
+#define BIT_SYSON_REG_ARB_8821C(x) \
+ (((x) & BIT_MASK_SYSON_REG_ARB_8821C) << BIT_SHIFT_SYSON_REG_ARB_8821C)
+#define BITS_SYSON_REG_ARB_8821C \
+ (BIT_MASK_SYSON_REG_ARB_8821C << BIT_SHIFT_SYSON_REG_ARB_8821C)
+#define BIT_CLEAR_SYSON_REG_ARB_8821C(x) ((x) & (~BITS_SYSON_REG_ARB_8821C))
+#define BIT_GET_SYSON_REG_ARB_8821C(x) \
+ (((x) >> BIT_SHIFT_SYSON_REG_ARB_8821C) & BIT_MASK_SYSON_REG_ARB_8821C)
+#define BIT_SET_SYSON_REG_ARB_8821C(x, v) \
+ (BIT_CLEAR_SYSON_REG_ARB_8821C(x) | BIT_SYSON_REG_ARB_8821C(v))
/* 2 REG_BIST_CTRL_8821C */
#define BIT_BIST_USB_DIS_8821C BIT(27)
@@ -1390,8 +2182,15 @@
#define BIT_SHIFT_BIST_RPT_SEL_8821C 16
#define BIT_MASK_BIST_RPT_SEL_8821C 0xf
-#define BIT_BIST_RPT_SEL_8821C(x) (((x) & BIT_MASK_BIST_RPT_SEL_8821C) << BIT_SHIFT_BIST_RPT_SEL_8821C)
-#define BIT_GET_BIST_RPT_SEL_8821C(x) (((x) >> BIT_SHIFT_BIST_RPT_SEL_8821C) & BIT_MASK_BIST_RPT_SEL_8821C)
+#define BIT_BIST_RPT_SEL_8821C(x) \
+ (((x) & BIT_MASK_BIST_RPT_SEL_8821C) << BIT_SHIFT_BIST_RPT_SEL_8821C)
+#define BITS_BIST_RPT_SEL_8821C \
+ (BIT_MASK_BIST_RPT_SEL_8821C << BIT_SHIFT_BIST_RPT_SEL_8821C)
+#define BIT_CLEAR_BIST_RPT_SEL_8821C(x) ((x) & (~BITS_BIST_RPT_SEL_8821C))
+#define BIT_GET_BIST_RPT_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_BIST_RPT_SEL_8821C) & BIT_MASK_BIST_RPT_SEL_8821C)
+#define BIT_SET_BIST_RPT_SEL_8821C(x, v) \
+ (BIT_CLEAR_BIST_RPT_SEL_8821C(x) | BIT_BIST_RPT_SEL_8821C(v))
#define BIT_BIST_RESUME_PS_8821C BIT(4)
#define BIT_BIST_RESUME_8821C BIT(3)
@@ -1403,54 +2202,100 @@
#define BIT_SHIFT_MBIST_REPORT_8821C 0
#define BIT_MASK_MBIST_REPORT_8821C 0xffffffffL
-#define BIT_MBIST_REPORT_8821C(x) (((x) & BIT_MASK_MBIST_REPORT_8821C) << BIT_SHIFT_MBIST_REPORT_8821C)
-#define BIT_GET_MBIST_REPORT_8821C(x) (((x) >> BIT_SHIFT_MBIST_REPORT_8821C) & BIT_MASK_MBIST_REPORT_8821C)
-
+#define BIT_MBIST_REPORT_8821C(x) \
+ (((x) & BIT_MASK_MBIST_REPORT_8821C) << BIT_SHIFT_MBIST_REPORT_8821C)
+#define BITS_MBIST_REPORT_8821C \
+ (BIT_MASK_MBIST_REPORT_8821C << BIT_SHIFT_MBIST_REPORT_8821C)
+#define BIT_CLEAR_MBIST_REPORT_8821C(x) ((x) & (~BITS_MBIST_REPORT_8821C))
+#define BIT_GET_MBIST_REPORT_8821C(x) \
+ (((x) >> BIT_SHIFT_MBIST_REPORT_8821C) & BIT_MASK_MBIST_REPORT_8821C)
+#define BIT_SET_MBIST_REPORT_8821C(x, v) \
+ (BIT_CLEAR_MBIST_REPORT_8821C(x) | BIT_MBIST_REPORT_8821C(v))
/* 2 REG_MEM_CTRL_8821C */
#define BIT_UMEM_RME_8821C BIT(31)
#define BIT_SHIFT_BT_SPRAM_8821C 28
#define BIT_MASK_BT_SPRAM_8821C 0x3
-#define BIT_BT_SPRAM_8821C(x) (((x) & BIT_MASK_BT_SPRAM_8821C) << BIT_SHIFT_BT_SPRAM_8821C)
-#define BIT_GET_BT_SPRAM_8821C(x) (((x) >> BIT_SHIFT_BT_SPRAM_8821C) & BIT_MASK_BT_SPRAM_8821C)
-
+#define BIT_BT_SPRAM_8821C(x) \
+ (((x) & BIT_MASK_BT_SPRAM_8821C) << BIT_SHIFT_BT_SPRAM_8821C)
+#define BITS_BT_SPRAM_8821C \
+ (BIT_MASK_BT_SPRAM_8821C << BIT_SHIFT_BT_SPRAM_8821C)
+#define BIT_CLEAR_BT_SPRAM_8821C(x) ((x) & (~BITS_BT_SPRAM_8821C))
+#define BIT_GET_BT_SPRAM_8821C(x) \
+ (((x) >> BIT_SHIFT_BT_SPRAM_8821C) & BIT_MASK_BT_SPRAM_8821C)
+#define BIT_SET_BT_SPRAM_8821C(x, v) \
+ (BIT_CLEAR_BT_SPRAM_8821C(x) | BIT_BT_SPRAM_8821C(v))
#define BIT_SHIFT_BT_ROM_8821C 24
#define BIT_MASK_BT_ROM_8821C 0xf
-#define BIT_BT_ROM_8821C(x) (((x) & BIT_MASK_BT_ROM_8821C) << BIT_SHIFT_BT_ROM_8821C)
-#define BIT_GET_BT_ROM_8821C(x) (((x) >> BIT_SHIFT_BT_ROM_8821C) & BIT_MASK_BT_ROM_8821C)
-
+#define BIT_BT_ROM_8821C(x) \
+ (((x) & BIT_MASK_BT_ROM_8821C) << BIT_SHIFT_BT_ROM_8821C)
+#define BITS_BT_ROM_8821C (BIT_MASK_BT_ROM_8821C << BIT_SHIFT_BT_ROM_8821C)
+#define BIT_CLEAR_BT_ROM_8821C(x) ((x) & (~BITS_BT_ROM_8821C))
+#define BIT_GET_BT_ROM_8821C(x) \
+ (((x) >> BIT_SHIFT_BT_ROM_8821C) & BIT_MASK_BT_ROM_8821C)
+#define BIT_SET_BT_ROM_8821C(x, v) \
+ (BIT_CLEAR_BT_ROM_8821C(x) | BIT_BT_ROM_8821C(v))
#define BIT_SHIFT_PCI_DPRAM_8821C 10
#define BIT_MASK_PCI_DPRAM_8821C 0x3
-#define BIT_PCI_DPRAM_8821C(x) (((x) & BIT_MASK_PCI_DPRAM_8821C) << BIT_SHIFT_PCI_DPRAM_8821C)
-#define BIT_GET_PCI_DPRAM_8821C(x) (((x) >> BIT_SHIFT_PCI_DPRAM_8821C) & BIT_MASK_PCI_DPRAM_8821C)
-
+#define BIT_PCI_DPRAM_8821C(x) \
+ (((x) & BIT_MASK_PCI_DPRAM_8821C) << BIT_SHIFT_PCI_DPRAM_8821C)
+#define BITS_PCI_DPRAM_8821C \
+ (BIT_MASK_PCI_DPRAM_8821C << BIT_SHIFT_PCI_DPRAM_8821C)
+#define BIT_CLEAR_PCI_DPRAM_8821C(x) ((x) & (~BITS_PCI_DPRAM_8821C))
+#define BIT_GET_PCI_DPRAM_8821C(x) \
+ (((x) >> BIT_SHIFT_PCI_DPRAM_8821C) & BIT_MASK_PCI_DPRAM_8821C)
+#define BIT_SET_PCI_DPRAM_8821C(x, v) \
+ (BIT_CLEAR_PCI_DPRAM_8821C(x) | BIT_PCI_DPRAM_8821C(v))
#define BIT_SHIFT_PCI_SPRAM_8821C 8
#define BIT_MASK_PCI_SPRAM_8821C 0x3
-#define BIT_PCI_SPRAM_8821C(x) (((x) & BIT_MASK_PCI_SPRAM_8821C) << BIT_SHIFT_PCI_SPRAM_8821C)
-#define BIT_GET_PCI_SPRAM_8821C(x) (((x) >> BIT_SHIFT_PCI_SPRAM_8821C) & BIT_MASK_PCI_SPRAM_8821C)
-
+#define BIT_PCI_SPRAM_8821C(x) \
+ (((x) & BIT_MASK_PCI_SPRAM_8821C) << BIT_SHIFT_PCI_SPRAM_8821C)
+#define BITS_PCI_SPRAM_8821C \
+ (BIT_MASK_PCI_SPRAM_8821C << BIT_SHIFT_PCI_SPRAM_8821C)
+#define BIT_CLEAR_PCI_SPRAM_8821C(x) ((x) & (~BITS_PCI_SPRAM_8821C))
+#define BIT_GET_PCI_SPRAM_8821C(x) \
+ (((x) >> BIT_SHIFT_PCI_SPRAM_8821C) & BIT_MASK_PCI_SPRAM_8821C)
+#define BIT_SET_PCI_SPRAM_8821C(x, v) \
+ (BIT_CLEAR_PCI_SPRAM_8821C(x) | BIT_PCI_SPRAM_8821C(v))
#define BIT_SHIFT_USB_SPRAM_8821C 6
#define BIT_MASK_USB_SPRAM_8821C 0x3
-#define BIT_USB_SPRAM_8821C(x) (((x) & BIT_MASK_USB_SPRAM_8821C) << BIT_SHIFT_USB_SPRAM_8821C)
-#define BIT_GET_USB_SPRAM_8821C(x) (((x) >> BIT_SHIFT_USB_SPRAM_8821C) & BIT_MASK_USB_SPRAM_8821C)
-
+#define BIT_USB_SPRAM_8821C(x) \
+ (((x) & BIT_MASK_USB_SPRAM_8821C) << BIT_SHIFT_USB_SPRAM_8821C)
+#define BITS_USB_SPRAM_8821C \
+ (BIT_MASK_USB_SPRAM_8821C << BIT_SHIFT_USB_SPRAM_8821C)
+#define BIT_CLEAR_USB_SPRAM_8821C(x) ((x) & (~BITS_USB_SPRAM_8821C))
+#define BIT_GET_USB_SPRAM_8821C(x) \
+ (((x) >> BIT_SHIFT_USB_SPRAM_8821C) & BIT_MASK_USB_SPRAM_8821C)
+#define BIT_SET_USB_SPRAM_8821C(x, v) \
+ (BIT_CLEAR_USB_SPRAM_8821C(x) | BIT_USB_SPRAM_8821C(v))
#define BIT_SHIFT_USB_SPRF_8821C 4
#define BIT_MASK_USB_SPRF_8821C 0x3
-#define BIT_USB_SPRF_8821C(x) (((x) & BIT_MASK_USB_SPRF_8821C) << BIT_SHIFT_USB_SPRF_8821C)
-#define BIT_GET_USB_SPRF_8821C(x) (((x) >> BIT_SHIFT_USB_SPRF_8821C) & BIT_MASK_USB_SPRF_8821C)
-
+#define BIT_USB_SPRF_8821C(x) \
+ (((x) & BIT_MASK_USB_SPRF_8821C) << BIT_SHIFT_USB_SPRF_8821C)
+#define BITS_USB_SPRF_8821C \
+ (BIT_MASK_USB_SPRF_8821C << BIT_SHIFT_USB_SPRF_8821C)
+#define BIT_CLEAR_USB_SPRF_8821C(x) ((x) & (~BITS_USB_SPRF_8821C))
+#define BIT_GET_USB_SPRF_8821C(x) \
+ (((x) >> BIT_SHIFT_USB_SPRF_8821C) & BIT_MASK_USB_SPRF_8821C)
+#define BIT_SET_USB_SPRF_8821C(x, v) \
+ (BIT_CLEAR_USB_SPRF_8821C(x) | BIT_USB_SPRF_8821C(v))
#define BIT_SHIFT_MCU_ROM_8821C 0
#define BIT_MASK_MCU_ROM_8821C 0xf
-#define BIT_MCU_ROM_8821C(x) (((x) & BIT_MASK_MCU_ROM_8821C) << BIT_SHIFT_MCU_ROM_8821C)
-#define BIT_GET_MCU_ROM_8821C(x) (((x) >> BIT_SHIFT_MCU_ROM_8821C) & BIT_MASK_MCU_ROM_8821C)
-
+#define BIT_MCU_ROM_8821C(x) \
+ (((x) & BIT_MASK_MCU_ROM_8821C) << BIT_SHIFT_MCU_ROM_8821C)
+#define BITS_MCU_ROM_8821C (BIT_MASK_MCU_ROM_8821C << BIT_SHIFT_MCU_ROM_8821C)
+#define BIT_CLEAR_MCU_ROM_8821C(x) ((x) & (~BITS_MCU_ROM_8821C))
+#define BIT_GET_MCU_ROM_8821C(x) \
+ (((x) >> BIT_SHIFT_MCU_ROM_8821C) & BIT_MASK_MCU_ROM_8821C)
+#define BIT_SET_MCU_ROM_8821C(x, v) \
+ (BIT_CLEAR_MCU_ROM_8821C(x) | BIT_MCU_ROM_8821C(v))
/* 2 REG_AFE_CTRL8_8821C */
#define BIT_SYN_AGPIO_8821C BIT(20)
@@ -1459,9 +2304,15 @@
#define BIT_SHIFT_XTAL_SEL_TOK_8821C 0
#define BIT_MASK_XTAL_SEL_TOK_8821C 0x7
-#define BIT_XTAL_SEL_TOK_8821C(x) (((x) & BIT_MASK_XTAL_SEL_TOK_8821C) << BIT_SHIFT_XTAL_SEL_TOK_8821C)
-#define BIT_GET_XTAL_SEL_TOK_8821C(x) (((x) >> BIT_SHIFT_XTAL_SEL_TOK_8821C) & BIT_MASK_XTAL_SEL_TOK_8821C)
-
+#define BIT_XTAL_SEL_TOK_8821C(x) \
+ (((x) & BIT_MASK_XTAL_SEL_TOK_8821C) << BIT_SHIFT_XTAL_SEL_TOK_8821C)
+#define BITS_XTAL_SEL_TOK_8821C \
+ (BIT_MASK_XTAL_SEL_TOK_8821C << BIT_SHIFT_XTAL_SEL_TOK_8821C)
+#define BIT_CLEAR_XTAL_SEL_TOK_8821C(x) ((x) & (~BITS_XTAL_SEL_TOK_8821C))
+#define BIT_GET_XTAL_SEL_TOK_8821C(x) \
+ (((x) >> BIT_SHIFT_XTAL_SEL_TOK_8821C) & BIT_MASK_XTAL_SEL_TOK_8821C)
+#define BIT_SET_XTAL_SEL_TOK_8821C(x, v) \
+ (BIT_CLEAR_XTAL_SEL_TOK_8821C(x) | BIT_XTAL_SEL_TOK_8821C(v))
/* 2 REG_USB_SIE_INTF_8821C */
#define BIT_RD_SEL_8821C BIT(31)
@@ -1471,60 +2322,136 @@
#define BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8821C 16
#define BIT_MASK_USB_SIE_INTF_ADDR_V1_8821C 0x1ff
-#define BIT_USB_SIE_INTF_ADDR_V1_8821C(x) (((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8821C) << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8821C)
-#define BIT_GET_USB_SIE_INTF_ADDR_V1_8821C(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8821C) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8821C)
-
+#define BIT_USB_SIE_INTF_ADDR_V1_8821C(x) \
+ (((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8821C) \
+ << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8821C)
+#define BITS_USB_SIE_INTF_ADDR_V1_8821C \
+ (BIT_MASK_USB_SIE_INTF_ADDR_V1_8821C \
+ << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8821C)
+#define BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8821C(x) \
+ ((x) & (~BITS_USB_SIE_INTF_ADDR_V1_8821C))
+#define BIT_GET_USB_SIE_INTF_ADDR_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8821C) & \
+ BIT_MASK_USB_SIE_INTF_ADDR_V1_8821C)
+#define BIT_SET_USB_SIE_INTF_ADDR_V1_8821C(x, v) \
+ (BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8821C(x) | \
+ BIT_USB_SIE_INTF_ADDR_V1_8821C(v))
#define BIT_SHIFT_USB_SIE_INTF_RD_8821C 8
#define BIT_MASK_USB_SIE_INTF_RD_8821C 0xff
-#define BIT_USB_SIE_INTF_RD_8821C(x) (((x) & BIT_MASK_USB_SIE_INTF_RD_8821C) << BIT_SHIFT_USB_SIE_INTF_RD_8821C)
-#define BIT_GET_USB_SIE_INTF_RD_8821C(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_RD_8821C) & BIT_MASK_USB_SIE_INTF_RD_8821C)
-
+#define BIT_USB_SIE_INTF_RD_8821C(x) \
+ (((x) & BIT_MASK_USB_SIE_INTF_RD_8821C) \
+ << BIT_SHIFT_USB_SIE_INTF_RD_8821C)
+#define BITS_USB_SIE_INTF_RD_8821C \
+ (BIT_MASK_USB_SIE_INTF_RD_8821C << BIT_SHIFT_USB_SIE_INTF_RD_8821C)
+#define BIT_CLEAR_USB_SIE_INTF_RD_8821C(x) ((x) & (~BITS_USB_SIE_INTF_RD_8821C))
+#define BIT_GET_USB_SIE_INTF_RD_8821C(x) \
+ (((x) >> BIT_SHIFT_USB_SIE_INTF_RD_8821C) & \
+ BIT_MASK_USB_SIE_INTF_RD_8821C)
+#define BIT_SET_USB_SIE_INTF_RD_8821C(x, v) \
+ (BIT_CLEAR_USB_SIE_INTF_RD_8821C(x) | BIT_USB_SIE_INTF_RD_8821C(v))
#define BIT_SHIFT_USB_SIE_INTF_WD_8821C 0
#define BIT_MASK_USB_SIE_INTF_WD_8821C 0xff
-#define BIT_USB_SIE_INTF_WD_8821C(x) (((x) & BIT_MASK_USB_SIE_INTF_WD_8821C) << BIT_SHIFT_USB_SIE_INTF_WD_8821C)
-#define BIT_GET_USB_SIE_INTF_WD_8821C(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_WD_8821C) & BIT_MASK_USB_SIE_INTF_WD_8821C)
-
+#define BIT_USB_SIE_INTF_WD_8821C(x) \
+ (((x) & BIT_MASK_USB_SIE_INTF_WD_8821C) \
+ << BIT_SHIFT_USB_SIE_INTF_WD_8821C)
+#define BITS_USB_SIE_INTF_WD_8821C \
+ (BIT_MASK_USB_SIE_INTF_WD_8821C << BIT_SHIFT_USB_SIE_INTF_WD_8821C)
+#define BIT_CLEAR_USB_SIE_INTF_WD_8821C(x) ((x) & (~BITS_USB_SIE_INTF_WD_8821C))
+#define BIT_GET_USB_SIE_INTF_WD_8821C(x) \
+ (((x) >> BIT_SHIFT_USB_SIE_INTF_WD_8821C) & \
+ BIT_MASK_USB_SIE_INTF_WD_8821C)
+#define BIT_SET_USB_SIE_INTF_WD_8821C(x, v) \
+ (BIT_CLEAR_USB_SIE_INTF_WD_8821C(x) | BIT_USB_SIE_INTF_WD_8821C(v))
/* 2 REG_PCIE_MIO_INTF_8821C */
+
+#define BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8821C 16
+#define BIT_MASK_PCIE_MIO_ADDR_PAGE_8821C 0x3
+#define BIT_PCIE_MIO_ADDR_PAGE_8821C(x) \
+ (((x) & BIT_MASK_PCIE_MIO_ADDR_PAGE_8821C) \
+ << BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8821C)
+#define BITS_PCIE_MIO_ADDR_PAGE_8821C \
+ (BIT_MASK_PCIE_MIO_ADDR_PAGE_8821C \
+ << BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8821C)
+#define BIT_CLEAR_PCIE_MIO_ADDR_PAGE_8821C(x) \
+ ((x) & (~BITS_PCIE_MIO_ADDR_PAGE_8821C))
+#define BIT_GET_PCIE_MIO_ADDR_PAGE_8821C(x) \
+ (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8821C) & \
+ BIT_MASK_PCIE_MIO_ADDR_PAGE_8821C)
+#define BIT_SET_PCIE_MIO_ADDR_PAGE_8821C(x, v) \
+ (BIT_CLEAR_PCIE_MIO_ADDR_PAGE_8821C(x) | \
+ BIT_PCIE_MIO_ADDR_PAGE_8821C(v))
+
#define BIT_PCIE_MIO_BYIOREG_8821C BIT(13)
#define BIT_PCIE_MIO_RE_8821C BIT(12)
#define BIT_SHIFT_PCIE_MIO_WE_8821C 8
#define BIT_MASK_PCIE_MIO_WE_8821C 0xf
-#define BIT_PCIE_MIO_WE_8821C(x) (((x) & BIT_MASK_PCIE_MIO_WE_8821C) << BIT_SHIFT_PCIE_MIO_WE_8821C)
-#define BIT_GET_PCIE_MIO_WE_8821C(x) (((x) >> BIT_SHIFT_PCIE_MIO_WE_8821C) & BIT_MASK_PCIE_MIO_WE_8821C)
-
+#define BIT_PCIE_MIO_WE_8821C(x) \
+ (((x) & BIT_MASK_PCIE_MIO_WE_8821C) << BIT_SHIFT_PCIE_MIO_WE_8821C)
+#define BITS_PCIE_MIO_WE_8821C \
+ (BIT_MASK_PCIE_MIO_WE_8821C << BIT_SHIFT_PCIE_MIO_WE_8821C)
+#define BIT_CLEAR_PCIE_MIO_WE_8821C(x) ((x) & (~BITS_PCIE_MIO_WE_8821C))
+#define BIT_GET_PCIE_MIO_WE_8821C(x) \
+ (((x) >> BIT_SHIFT_PCIE_MIO_WE_8821C) & BIT_MASK_PCIE_MIO_WE_8821C)
+#define BIT_SET_PCIE_MIO_WE_8821C(x, v) \
+ (BIT_CLEAR_PCIE_MIO_WE_8821C(x) | BIT_PCIE_MIO_WE_8821C(v))
#define BIT_SHIFT_PCIE_MIO_ADDR_8821C 0
#define BIT_MASK_PCIE_MIO_ADDR_8821C 0xff
-#define BIT_PCIE_MIO_ADDR_8821C(x) (((x) & BIT_MASK_PCIE_MIO_ADDR_8821C) << BIT_SHIFT_PCIE_MIO_ADDR_8821C)
-#define BIT_GET_PCIE_MIO_ADDR_8821C(x) (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8821C) & BIT_MASK_PCIE_MIO_ADDR_8821C)
-
+#define BIT_PCIE_MIO_ADDR_8821C(x) \
+ (((x) & BIT_MASK_PCIE_MIO_ADDR_8821C) << BIT_SHIFT_PCIE_MIO_ADDR_8821C)
+#define BITS_PCIE_MIO_ADDR_8821C \
+ (BIT_MASK_PCIE_MIO_ADDR_8821C << BIT_SHIFT_PCIE_MIO_ADDR_8821C)
+#define BIT_CLEAR_PCIE_MIO_ADDR_8821C(x) ((x) & (~BITS_PCIE_MIO_ADDR_8821C))
+#define BIT_GET_PCIE_MIO_ADDR_8821C(x) \
+ (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8821C) & BIT_MASK_PCIE_MIO_ADDR_8821C)
+#define BIT_SET_PCIE_MIO_ADDR_8821C(x, v) \
+ (BIT_CLEAR_PCIE_MIO_ADDR_8821C(x) | BIT_PCIE_MIO_ADDR_8821C(v))
/* 2 REG_PCIE_MIO_INTD_8821C */
#define BIT_SHIFT_PCIE_MIO_DATA_8821C 0
#define BIT_MASK_PCIE_MIO_DATA_8821C 0xffffffffL
-#define BIT_PCIE_MIO_DATA_8821C(x) (((x) & BIT_MASK_PCIE_MIO_DATA_8821C) << BIT_SHIFT_PCIE_MIO_DATA_8821C)
-#define BIT_GET_PCIE_MIO_DATA_8821C(x) (((x) >> BIT_SHIFT_PCIE_MIO_DATA_8821C) & BIT_MASK_PCIE_MIO_DATA_8821C)
-
+#define BIT_PCIE_MIO_DATA_8821C(x) \
+ (((x) & BIT_MASK_PCIE_MIO_DATA_8821C) << BIT_SHIFT_PCIE_MIO_DATA_8821C)
+#define BITS_PCIE_MIO_DATA_8821C \
+ (BIT_MASK_PCIE_MIO_DATA_8821C << BIT_SHIFT_PCIE_MIO_DATA_8821C)
+#define BIT_CLEAR_PCIE_MIO_DATA_8821C(x) ((x) & (~BITS_PCIE_MIO_DATA_8821C))
+#define BIT_GET_PCIE_MIO_DATA_8821C(x) \
+ (((x) >> BIT_SHIFT_PCIE_MIO_DATA_8821C) & BIT_MASK_PCIE_MIO_DATA_8821C)
+#define BIT_SET_PCIE_MIO_DATA_8821C(x, v) \
+ (BIT_CLEAR_PCIE_MIO_DATA_8821C(x) | BIT_PCIE_MIO_DATA_8821C(v))
/* 2 REG_WLRF1_8821C */
#define BIT_SHIFT_WLRF1_CTRL_8821C 24
#define BIT_MASK_WLRF1_CTRL_8821C 0xff
-#define BIT_WLRF1_CTRL_8821C(x) (((x) & BIT_MASK_WLRF1_CTRL_8821C) << BIT_SHIFT_WLRF1_CTRL_8821C)
-#define BIT_GET_WLRF1_CTRL_8821C(x) (((x) >> BIT_SHIFT_WLRF1_CTRL_8821C) & BIT_MASK_WLRF1_CTRL_8821C)
-
+#define BIT_WLRF1_CTRL_8821C(x) \
+ (((x) & BIT_MASK_WLRF1_CTRL_8821C) << BIT_SHIFT_WLRF1_CTRL_8821C)
+#define BITS_WLRF1_CTRL_8821C \
+ (BIT_MASK_WLRF1_CTRL_8821C << BIT_SHIFT_WLRF1_CTRL_8821C)
+#define BIT_CLEAR_WLRF1_CTRL_8821C(x) ((x) & (~BITS_WLRF1_CTRL_8821C))
+#define BIT_GET_WLRF1_CTRL_8821C(x) \
+ (((x) >> BIT_SHIFT_WLRF1_CTRL_8821C) & BIT_MASK_WLRF1_CTRL_8821C)
+#define BIT_SET_WLRF1_CTRL_8821C(x, v) \
+ (BIT_CLEAR_WLRF1_CTRL_8821C(x) | BIT_WLRF1_CTRL_8821C(v))
/* 2 REG_SYS_CFG1_8821C */
#define BIT_SHIFT_TRP_ICFG_8821C 28
#define BIT_MASK_TRP_ICFG_8821C 0xf
-#define BIT_TRP_ICFG_8821C(x) (((x) & BIT_MASK_TRP_ICFG_8821C) << BIT_SHIFT_TRP_ICFG_8821C)
-#define BIT_GET_TRP_ICFG_8821C(x) (((x) >> BIT_SHIFT_TRP_ICFG_8821C) & BIT_MASK_TRP_ICFG_8821C)
+#define BIT_TRP_ICFG_8821C(x) \
+ (((x) & BIT_MASK_TRP_ICFG_8821C) << BIT_SHIFT_TRP_ICFG_8821C)
+#define BITS_TRP_ICFG_8821C \
+ (BIT_MASK_TRP_ICFG_8821C << BIT_SHIFT_TRP_ICFG_8821C)
+#define BIT_CLEAR_TRP_ICFG_8821C(x) ((x) & (~BITS_TRP_ICFG_8821C))
+#define BIT_GET_TRP_ICFG_8821C(x) \
+ (((x) >> BIT_SHIFT_TRP_ICFG_8821C) & BIT_MASK_TRP_ICFG_8821C)
+#define BIT_SET_TRP_ICFG_8821C(x, v) \
+ (BIT_CLEAR_TRP_ICFG_8821C(x) | BIT_TRP_ICFG_8821C(v))
#define BIT_RF_TYPE_ID_8821C BIT(27)
#define BIT_BD_HCI_SEL_8821C BIT(26)
@@ -1536,14 +2463,27 @@
#define BIT_SHIFT_VENDOR_ID_8821C 16
#define BIT_MASK_VENDOR_ID_8821C 0xf
-#define BIT_VENDOR_ID_8821C(x) (((x) & BIT_MASK_VENDOR_ID_8821C) << BIT_SHIFT_VENDOR_ID_8821C)
-#define BIT_GET_VENDOR_ID_8821C(x) (((x) >> BIT_SHIFT_VENDOR_ID_8821C) & BIT_MASK_VENDOR_ID_8821C)
-
+#define BIT_VENDOR_ID_8821C(x) \
+ (((x) & BIT_MASK_VENDOR_ID_8821C) << BIT_SHIFT_VENDOR_ID_8821C)
+#define BITS_VENDOR_ID_8821C \
+ (BIT_MASK_VENDOR_ID_8821C << BIT_SHIFT_VENDOR_ID_8821C)
+#define BIT_CLEAR_VENDOR_ID_8821C(x) ((x) & (~BITS_VENDOR_ID_8821C))
+#define BIT_GET_VENDOR_ID_8821C(x) \
+ (((x) >> BIT_SHIFT_VENDOR_ID_8821C) & BIT_MASK_VENDOR_ID_8821C)
+#define BIT_SET_VENDOR_ID_8821C(x, v) \
+ (BIT_CLEAR_VENDOR_ID_8821C(x) | BIT_VENDOR_ID_8821C(v))
#define BIT_SHIFT_CHIP_VER_8821C 12
#define BIT_MASK_CHIP_VER_8821C 0xf
-#define BIT_CHIP_VER_8821C(x) (((x) & BIT_MASK_CHIP_VER_8821C) << BIT_SHIFT_CHIP_VER_8821C)
-#define BIT_GET_CHIP_VER_8821C(x) (((x) >> BIT_SHIFT_CHIP_VER_8821C) & BIT_MASK_CHIP_VER_8821C)
+#define BIT_CHIP_VER_8821C(x) \
+ (((x) & BIT_MASK_CHIP_VER_8821C) << BIT_SHIFT_CHIP_VER_8821C)
+#define BITS_CHIP_VER_8821C \
+ (BIT_MASK_CHIP_VER_8821C << BIT_SHIFT_CHIP_VER_8821C)
+#define BIT_CLEAR_CHIP_VER_8821C(x) ((x) & (~BITS_CHIP_VER_8821C))
+#define BIT_GET_CHIP_VER_8821C(x) \
+ (((x) >> BIT_SHIFT_CHIP_VER_8821C) & BIT_MASK_CHIP_VER_8821C)
+#define BIT_SET_CHIP_VER_8821C(x, v) \
+ (BIT_CLEAR_CHIP_VER_8821C(x) | BIT_CHIP_VER_8821C(v))
#define BIT_BD_MAC3_8821C BIT(11)
#define BIT_BD_MAC1_8821C BIT(10)
@@ -1562,15 +2502,41 @@
#define BIT_SHIFT_RF_RL_ID_8821C 28
#define BIT_MASK_RF_RL_ID_8821C 0xf
-#define BIT_RF_RL_ID_8821C(x) (((x) & BIT_MASK_RF_RL_ID_8821C) << BIT_SHIFT_RF_RL_ID_8821C)
-#define BIT_GET_RF_RL_ID_8821C(x) (((x) >> BIT_SHIFT_RF_RL_ID_8821C) & BIT_MASK_RF_RL_ID_8821C)
+#define BIT_RF_RL_ID_8821C(x) \
+ (((x) & BIT_MASK_RF_RL_ID_8821C) << BIT_SHIFT_RF_RL_ID_8821C)
+#define BITS_RF_RL_ID_8821C \
+ (BIT_MASK_RF_RL_ID_8821C << BIT_SHIFT_RF_RL_ID_8821C)
+#define BIT_CLEAR_RF_RL_ID_8821C(x) ((x) & (~BITS_RF_RL_ID_8821C))
+#define BIT_GET_RF_RL_ID_8821C(x) \
+ (((x) >> BIT_SHIFT_RF_RL_ID_8821C) & BIT_MASK_RF_RL_ID_8821C)
+#define BIT_SET_RF_RL_ID_8821C(x, v) \
+ (BIT_CLEAR_RF_RL_ID_8821C(x) | BIT_RF_RL_ID_8821C(v))
#define BIT_HPHY_ICFG_8821C BIT(19)
#define BIT_SHIFT_SEL_0XC0_8821C 16
#define BIT_MASK_SEL_0XC0_8821C 0x3
-#define BIT_SEL_0XC0_8821C(x) (((x) & BIT_MASK_SEL_0XC0_8821C) << BIT_SHIFT_SEL_0XC0_8821C)
-#define BIT_GET_SEL_0XC0_8821C(x) (((x) >> BIT_SHIFT_SEL_0XC0_8821C) & BIT_MASK_SEL_0XC0_8821C)
+#define BIT_SEL_0XC0_8821C(x) \
+ (((x) & BIT_MASK_SEL_0XC0_8821C) << BIT_SHIFT_SEL_0XC0_8821C)
+#define BITS_SEL_0XC0_8821C \
+ (BIT_MASK_SEL_0XC0_8821C << BIT_SHIFT_SEL_0XC0_8821C)
+#define BIT_CLEAR_SEL_0XC0_8821C(x) ((x) & (~BITS_SEL_0XC0_8821C))
+#define BIT_GET_SEL_0XC0_8821C(x) \
+ (((x) >> BIT_SHIFT_SEL_0XC0_8821C) & BIT_MASK_SEL_0XC0_8821C)
+#define BIT_SET_SEL_0XC0_8821C(x, v) \
+ (BIT_CLEAR_SEL_0XC0_8821C(x) | BIT_SEL_0XC0_8821C(v))
+
+#define BIT_SHIFT_HCI_SEL_V4_8821C 12
+#define BIT_MASK_HCI_SEL_V4_8821C 0x3
+#define BIT_HCI_SEL_V4_8821C(x) \
+ (((x) & BIT_MASK_HCI_SEL_V4_8821C) << BIT_SHIFT_HCI_SEL_V4_8821C)
+#define BITS_HCI_SEL_V4_8821C \
+ (BIT_MASK_HCI_SEL_V4_8821C << BIT_SHIFT_HCI_SEL_V4_8821C)
+#define BIT_CLEAR_HCI_SEL_V4_8821C(x) ((x) & (~BITS_HCI_SEL_V4_8821C))
+#define BIT_GET_HCI_SEL_V4_8821C(x) \
+ (((x) >> BIT_SHIFT_HCI_SEL_V4_8821C) & BIT_MASK_HCI_SEL_V4_8821C)
+#define BIT_SET_HCI_SEL_V4_8821C(x, v) \
+ (BIT_CLEAR_HCI_SEL_V4_8821C(x) | BIT_HCI_SEL_V4_8821C(v))
#define BIT_USB_OPERATION_MODE_8821C BIT(10)
#define BIT_BT_PDN_8821C BIT(9)
@@ -1578,23 +2544,31 @@
#define BIT_WL_MODE_8821C BIT(7)
#define BIT_PKG_SEL_HCI_8821C BIT(6)
-#define BIT_SHIFT_HCI_SEL_8821C 4
-#define BIT_MASK_HCI_SEL_8821C 0x3
-#define BIT_HCI_SEL_8821C(x) (((x) & BIT_MASK_HCI_SEL_8821C) << BIT_SHIFT_HCI_SEL_8821C)
-#define BIT_GET_HCI_SEL_8821C(x) (((x) >> BIT_SHIFT_HCI_SEL_8821C) & BIT_MASK_HCI_SEL_8821C)
-
-
-#define BIT_SHIFT_PAD_HCI_SEL_8821C 2
-#define BIT_MASK_PAD_HCI_SEL_8821C 0x3
-#define BIT_PAD_HCI_SEL_8821C(x) (((x) & BIT_MASK_PAD_HCI_SEL_8821C) << BIT_SHIFT_PAD_HCI_SEL_8821C)
-#define BIT_GET_PAD_HCI_SEL_8821C(x) (((x) >> BIT_SHIFT_PAD_HCI_SEL_8821C) & BIT_MASK_PAD_HCI_SEL_8821C)
-
+#define BIT_SHIFT_PAD_HCI_SEL_V2_8821C 3
+#define BIT_MASK_PAD_HCI_SEL_V2_8821C 0x3
+#define BIT_PAD_HCI_SEL_V2_8821C(x) \
+ (((x) & BIT_MASK_PAD_HCI_SEL_V2_8821C) \
+ << BIT_SHIFT_PAD_HCI_SEL_V2_8821C)
+#define BITS_PAD_HCI_SEL_V2_8821C \
+ (BIT_MASK_PAD_HCI_SEL_V2_8821C << BIT_SHIFT_PAD_HCI_SEL_V2_8821C)
+#define BIT_CLEAR_PAD_HCI_SEL_V2_8821C(x) ((x) & (~BITS_PAD_HCI_SEL_V2_8821C))
+#define BIT_GET_PAD_HCI_SEL_V2_8821C(x) \
+ (((x) >> BIT_SHIFT_PAD_HCI_SEL_V2_8821C) & \
+ BIT_MASK_PAD_HCI_SEL_V2_8821C)
+#define BIT_SET_PAD_HCI_SEL_V2_8821C(x, v) \
+ (BIT_CLEAR_PAD_HCI_SEL_V2_8821C(x) | BIT_PAD_HCI_SEL_V2_8821C(v))
#define BIT_SHIFT_EFS_HCI_SEL_8821C 0
#define BIT_MASK_EFS_HCI_SEL_8821C 0x3
-#define BIT_EFS_HCI_SEL_8821C(x) (((x) & BIT_MASK_EFS_HCI_SEL_8821C) << BIT_SHIFT_EFS_HCI_SEL_8821C)
-#define BIT_GET_EFS_HCI_SEL_8821C(x) (((x) >> BIT_SHIFT_EFS_HCI_SEL_8821C) & BIT_MASK_EFS_HCI_SEL_8821C)
-
+#define BIT_EFS_HCI_SEL_8821C(x) \
+ (((x) & BIT_MASK_EFS_HCI_SEL_8821C) << BIT_SHIFT_EFS_HCI_SEL_8821C)
+#define BITS_EFS_HCI_SEL_8821C \
+ (BIT_MASK_EFS_HCI_SEL_8821C << BIT_SHIFT_EFS_HCI_SEL_8821C)
+#define BIT_CLEAR_EFS_HCI_SEL_8821C(x) ((x) & (~BITS_EFS_HCI_SEL_8821C))
+#define BIT_GET_EFS_HCI_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_EFS_HCI_SEL_8821C) & BIT_MASK_EFS_HCI_SEL_8821C)
+#define BIT_SET_EFS_HCI_SEL_8821C(x, v) \
+ (BIT_CLEAR_EFS_HCI_SEL_8821C(x) | BIT_EFS_HCI_SEL_8821C(v))
/* 2 REG_SYS_STATUS2_8821C */
#define BIT_SIO_ALDN_8821C BIT(19)
@@ -1604,35 +2578,95 @@
#define BIT_SHIFT_EPVID1_8821C 8
#define BIT_MASK_EPVID1_8821C 0xff
-#define BIT_EPVID1_8821C(x) (((x) & BIT_MASK_EPVID1_8821C) << BIT_SHIFT_EPVID1_8821C)
-#define BIT_GET_EPVID1_8821C(x) (((x) >> BIT_SHIFT_EPVID1_8821C) & BIT_MASK_EPVID1_8821C)
-
+#define BIT_EPVID1_8821C(x) \
+ (((x) & BIT_MASK_EPVID1_8821C) << BIT_SHIFT_EPVID1_8821C)
+#define BITS_EPVID1_8821C (BIT_MASK_EPVID1_8821C << BIT_SHIFT_EPVID1_8821C)
+#define BIT_CLEAR_EPVID1_8821C(x) ((x) & (~BITS_EPVID1_8821C))
+#define BIT_GET_EPVID1_8821C(x) \
+ (((x) >> BIT_SHIFT_EPVID1_8821C) & BIT_MASK_EPVID1_8821C)
+#define BIT_SET_EPVID1_8821C(x, v) \
+ (BIT_CLEAR_EPVID1_8821C(x) | BIT_EPVID1_8821C(v))
#define BIT_SHIFT_EPVID0_8821C 0
#define BIT_MASK_EPVID0_8821C 0xff
-#define BIT_EPVID0_8821C(x) (((x) & BIT_MASK_EPVID0_8821C) << BIT_SHIFT_EPVID0_8821C)
-#define BIT_GET_EPVID0_8821C(x) (((x) >> BIT_SHIFT_EPVID0_8821C) & BIT_MASK_EPVID0_8821C)
-
+#define BIT_EPVID0_8821C(x) \
+ (((x) & BIT_MASK_EPVID0_8821C) << BIT_SHIFT_EPVID0_8821C)
+#define BITS_EPVID0_8821C (BIT_MASK_EPVID0_8821C << BIT_SHIFT_EPVID0_8821C)
+#define BIT_CLEAR_EPVID0_8821C(x) ((x) & (~BITS_EPVID0_8821C))
+#define BIT_GET_EPVID0_8821C(x) \
+ (((x) >> BIT_SHIFT_EPVID0_8821C) & BIT_MASK_EPVID0_8821C)
+#define BIT_SET_EPVID0_8821C(x, v) \
+ (BIT_CLEAR_EPVID0_8821C(x) | BIT_EPVID0_8821C(v))
/* 2 REG_SYS_CFG2_8821C */
-#define BIT_HCI_SEL_EMBEDED_8821C BIT(8)
+#define BIT_HCI_SEL_EMBEDDED_8821C BIT(8)
#define BIT_SHIFT_HW_ID_8821C 0
#define BIT_MASK_HW_ID_8821C 0xff
-#define BIT_HW_ID_8821C(x) (((x) & BIT_MASK_HW_ID_8821C) << BIT_SHIFT_HW_ID_8821C)
-#define BIT_GET_HW_ID_8821C(x) (((x) >> BIT_SHIFT_HW_ID_8821C) & BIT_MASK_HW_ID_8821C)
-
+#define BIT_HW_ID_8821C(x) \
+ (((x) & BIT_MASK_HW_ID_8821C) << BIT_SHIFT_HW_ID_8821C)
+#define BITS_HW_ID_8821C (BIT_MASK_HW_ID_8821C << BIT_SHIFT_HW_ID_8821C)
+#define BIT_CLEAR_HW_ID_8821C(x) ((x) & (~BITS_HW_ID_8821C))
+#define BIT_GET_HW_ID_8821C(x) \
+ (((x) >> BIT_SHIFT_HW_ID_8821C) & BIT_MASK_HW_ID_8821C)
+#define BIT_SET_HW_ID_8821C(x, v) \
+ (BIT_CLEAR_HW_ID_8821C(x) | BIT_HW_ID_8821C(v))
/* 2 REG_SYS_CFG3_8821C */
-#define BIT_PWC_MA33V_8821C BIT(15)
-#define BIT_PWC_MA12V_8821C BIT(14)
-#define BIT_PWC_MD12V_8821C BIT(13)
-#define BIT_PWC_PD12V_8821C BIT(12)
-#define BIT_PWC_UD12V_8821C BIT(11)
-#define BIT_ISO_MA2MD_8821C BIT(1)
-#define BIT_ISO_MD2PP_8821C BIT(0)
-/* 2 REG_SYS_CFG4_8821C */
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
/* 2 REG_SYS_CFG5_8821C */
#define BIT_LPS_STATUS_8821C BIT(3)
@@ -1640,6 +2674,12 @@
#define BIT_HCI_TXDMA_ALLOW_8821C BIT(1)
#define BIT_FW_CTRL_HCI_TXDMA_EN_8821C BIT(0)
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
/* 2 REG_CPU_DMEM_CON_8821C */
#define BIT_WDT_AUTO_MODE_8821C BIT(22)
#define BIT_WDT_PLATFORM_EN_8821C BIT(21)
@@ -1652,17 +2692,47 @@
#define BIT_SHIFT_CPU_DMEM_CON_8821C 0
#define BIT_MASK_CPU_DMEM_CON_8821C 0xff
-#define BIT_CPU_DMEM_CON_8821C(x) (((x) & BIT_MASK_CPU_DMEM_CON_8821C) << BIT_SHIFT_CPU_DMEM_CON_8821C)
-#define BIT_GET_CPU_DMEM_CON_8821C(x) (((x) >> BIT_SHIFT_CPU_DMEM_CON_8821C) & BIT_MASK_CPU_DMEM_CON_8821C)
+#define BIT_CPU_DMEM_CON_8821C(x) \
+ (((x) & BIT_MASK_CPU_DMEM_CON_8821C) << BIT_SHIFT_CPU_DMEM_CON_8821C)
+#define BITS_CPU_DMEM_CON_8821C \
+ (BIT_MASK_CPU_DMEM_CON_8821C << BIT_SHIFT_CPU_DMEM_CON_8821C)
+#define BIT_CLEAR_CPU_DMEM_CON_8821C(x) ((x) & (~BITS_CPU_DMEM_CON_8821C))
+#define BIT_GET_CPU_DMEM_CON_8821C(x) \
+ (((x) >> BIT_SHIFT_CPU_DMEM_CON_8821C) & BIT_MASK_CPU_DMEM_CON_8821C)
+#define BIT_SET_CPU_DMEM_CON_8821C(x, v) \
+ (BIT_CLEAR_CPU_DMEM_CON_8821C(x) | BIT_CPU_DMEM_CON_8821C(v))
+/* 2 REG_NOT_VALID_8821C */
/* 2 REG_BOOT_REASON_8821C */
-#define BIT_SHIFT_BOOT_REASON_8821C 0
-#define BIT_MASK_BOOT_REASON_8821C 0x7
-#define BIT_BOOT_REASON_8821C(x) (((x) & BIT_MASK_BOOT_REASON_8821C) << BIT_SHIFT_BOOT_REASON_8821C)
-#define BIT_GET_BOOT_REASON_8821C(x) (((x) >> BIT_SHIFT_BOOT_REASON_8821C) & BIT_MASK_BOOT_REASON_8821C)
+#define BIT_SHIFT_BOOT_REASON_V1_8821C 0
+#define BIT_MASK_BOOT_REASON_V1_8821C 0x7
+#define BIT_BOOT_REASON_V1_8821C(x) \
+ (((x) & BIT_MASK_BOOT_REASON_V1_8821C) \
+ << BIT_SHIFT_BOOT_REASON_V1_8821C)
+#define BITS_BOOT_REASON_V1_8821C \
+ (BIT_MASK_BOOT_REASON_V1_8821C << BIT_SHIFT_BOOT_REASON_V1_8821C)
+#define BIT_CLEAR_BOOT_REASON_V1_8821C(x) ((x) & (~BITS_BOOT_REASON_V1_8821C))
+#define BIT_GET_BOOT_REASON_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_BOOT_REASON_V1_8821C) & \
+ BIT_MASK_BOOT_REASON_V1_8821C)
+#define BIT_SET_BOOT_REASON_V1_8821C(x, v) \
+ (BIT_CLEAR_BOOT_REASON_V1_8821C(x) | BIT_BOOT_REASON_V1_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+/* 2 REG_NOT_VALID_8821C */
/* 2 REG_NFCPAD_CTRL_8821C */
#define BIT_PAD_SHUTDW_8821C BIT(18)
@@ -1675,21 +2745,41 @@
#define BIT_SHIFT_NFCPAD_IO_SEL_8821C 8
#define BIT_MASK_NFCPAD_IO_SEL_8821C 0xf
-#define BIT_NFCPAD_IO_SEL_8821C(x) (((x) & BIT_MASK_NFCPAD_IO_SEL_8821C) << BIT_SHIFT_NFCPAD_IO_SEL_8821C)
-#define BIT_GET_NFCPAD_IO_SEL_8821C(x) (((x) >> BIT_SHIFT_NFCPAD_IO_SEL_8821C) & BIT_MASK_NFCPAD_IO_SEL_8821C)
-
+#define BIT_NFCPAD_IO_SEL_8821C(x) \
+ (((x) & BIT_MASK_NFCPAD_IO_SEL_8821C) << BIT_SHIFT_NFCPAD_IO_SEL_8821C)
+#define BITS_NFCPAD_IO_SEL_8821C \
+ (BIT_MASK_NFCPAD_IO_SEL_8821C << BIT_SHIFT_NFCPAD_IO_SEL_8821C)
+#define BIT_CLEAR_NFCPAD_IO_SEL_8821C(x) ((x) & (~BITS_NFCPAD_IO_SEL_8821C))
+#define BIT_GET_NFCPAD_IO_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_NFCPAD_IO_SEL_8821C) & BIT_MASK_NFCPAD_IO_SEL_8821C)
+#define BIT_SET_NFCPAD_IO_SEL_8821C(x, v) \
+ (BIT_CLEAR_NFCPAD_IO_SEL_8821C(x) | BIT_NFCPAD_IO_SEL_8821C(v))
#define BIT_SHIFT_NFCPAD_OUT_8821C 4
#define BIT_MASK_NFCPAD_OUT_8821C 0xf
-#define BIT_NFCPAD_OUT_8821C(x) (((x) & BIT_MASK_NFCPAD_OUT_8821C) << BIT_SHIFT_NFCPAD_OUT_8821C)
-#define BIT_GET_NFCPAD_OUT_8821C(x) (((x) >> BIT_SHIFT_NFCPAD_OUT_8821C) & BIT_MASK_NFCPAD_OUT_8821C)
-
+#define BIT_NFCPAD_OUT_8821C(x) \
+ (((x) & BIT_MASK_NFCPAD_OUT_8821C) << BIT_SHIFT_NFCPAD_OUT_8821C)
+#define BITS_NFCPAD_OUT_8821C \
+ (BIT_MASK_NFCPAD_OUT_8821C << BIT_SHIFT_NFCPAD_OUT_8821C)
+#define BIT_CLEAR_NFCPAD_OUT_8821C(x) ((x) & (~BITS_NFCPAD_OUT_8821C))
+#define BIT_GET_NFCPAD_OUT_8821C(x) \
+ (((x) >> BIT_SHIFT_NFCPAD_OUT_8821C) & BIT_MASK_NFCPAD_OUT_8821C)
+#define BIT_SET_NFCPAD_OUT_8821C(x, v) \
+ (BIT_CLEAR_NFCPAD_OUT_8821C(x) | BIT_NFCPAD_OUT_8821C(v))
#define BIT_SHIFT_NFCPAD_IN_8821C 0
#define BIT_MASK_NFCPAD_IN_8821C 0xf
-#define BIT_NFCPAD_IN_8821C(x) (((x) & BIT_MASK_NFCPAD_IN_8821C) << BIT_SHIFT_NFCPAD_IN_8821C)
-#define BIT_GET_NFCPAD_IN_8821C(x) (((x) >> BIT_SHIFT_NFCPAD_IN_8821C) & BIT_MASK_NFCPAD_IN_8821C)
+#define BIT_NFCPAD_IN_8821C(x) \
+ (((x) & BIT_MASK_NFCPAD_IN_8821C) << BIT_SHIFT_NFCPAD_IN_8821C)
+#define BITS_NFCPAD_IN_8821C \
+ (BIT_MASK_NFCPAD_IN_8821C << BIT_SHIFT_NFCPAD_IN_8821C)
+#define BIT_CLEAR_NFCPAD_IN_8821C(x) ((x) & (~BITS_NFCPAD_IN_8821C))
+#define BIT_GET_NFCPAD_IN_8821C(x) \
+ (((x) >> BIT_SHIFT_NFCPAD_IN_8821C) & BIT_MASK_NFCPAD_IN_8821C)
+#define BIT_SET_NFCPAD_IN_8821C(x, v) \
+ (BIT_CLEAR_NFCPAD_IN_8821C(x) | BIT_NFCPAD_IN_8821C(v))
+/* 2 REG_NOT_VALID_8821C */
/* 2 REG_HIMR2_8821C */
#define BIT_BCNDMAINT_P4_MSK_8821C BIT(31)
@@ -1786,40 +2876,45 @@
/* 2 REG_SW_MDIO_8821C */
#define BIT_DIS_TIMEOUT_IO_8821C BIT(24)
-/* 2 REG_SW_FLUSH_8821C */
-#define BIT_FLUSH_HOLDN_EN_8821C BIT(25)
-#define BIT_FLUSH_WR_EN_8821C BIT(24)
-#define BIT_SW_FLASH_CONTROL_8821C BIT(23)
-#define BIT_SW_FLASH_WEN_E_8821C BIT(19)
-#define BIT_SW_FLASH_HOLDN_E_8821C BIT(18)
-#define BIT_SW_FLASH_SO_E_8821C BIT(17)
-#define BIT_SW_FLASH_SI_E_8821C BIT(16)
-#define BIT_SW_FLASH_SK_O_8821C BIT(13)
-#define BIT_SW_FLASH_CEN_O_8821C BIT(12)
-#define BIT_SW_FLASH_WEN_O_8821C BIT(11)
-#define BIT_SW_FLASH_HOLDN_O_8821C BIT(10)
-#define BIT_SW_FLASH_SO_O_8821C BIT(9)
-#define BIT_SW_FLASH_SI_O_8821C BIT(8)
-#define BIT_SW_FLASH_WEN_I_8821C BIT(3)
-#define BIT_SW_FLASH_HOLDN_I_8821C BIT(2)
-#define BIT_SW_FLASH_SO_I_8821C BIT(1)
-#define BIT_SW_FLASH_SI_I_8821C BIT(0)
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
/* 2 REG_H2C_PKT_READADDR_8821C */
#define BIT_SHIFT_H2C_PKT_READADDR_8821C 0
#define BIT_MASK_H2C_PKT_READADDR_8821C 0x3ffff
-#define BIT_H2C_PKT_READADDR_8821C(x) (((x) & BIT_MASK_H2C_PKT_READADDR_8821C) << BIT_SHIFT_H2C_PKT_READADDR_8821C)
-#define BIT_GET_H2C_PKT_READADDR_8821C(x) (((x) >> BIT_SHIFT_H2C_PKT_READADDR_8821C) & BIT_MASK_H2C_PKT_READADDR_8821C)
-
+#define BIT_H2C_PKT_READADDR_8821C(x) \
+ (((x) & BIT_MASK_H2C_PKT_READADDR_8821C) \
+ << BIT_SHIFT_H2C_PKT_READADDR_8821C)
+#define BITS_H2C_PKT_READADDR_8821C \
+ (BIT_MASK_H2C_PKT_READADDR_8821C << BIT_SHIFT_H2C_PKT_READADDR_8821C)
+#define BIT_CLEAR_H2C_PKT_READADDR_8821C(x) \
+ ((x) & (~BITS_H2C_PKT_READADDR_8821C))
+#define BIT_GET_H2C_PKT_READADDR_8821C(x) \
+ (((x) >> BIT_SHIFT_H2C_PKT_READADDR_8821C) & \
+ BIT_MASK_H2C_PKT_READADDR_8821C)
+#define BIT_SET_H2C_PKT_READADDR_8821C(x, v) \
+ (BIT_CLEAR_H2C_PKT_READADDR_8821C(x) | BIT_H2C_PKT_READADDR_8821C(v))
/* 2 REG_H2C_PKT_WRITEADDR_8821C */
#define BIT_SHIFT_H2C_PKT_WRITEADDR_8821C 0
#define BIT_MASK_H2C_PKT_WRITEADDR_8821C 0x3ffff
-#define BIT_H2C_PKT_WRITEADDR_8821C(x) (((x) & BIT_MASK_H2C_PKT_WRITEADDR_8821C) << BIT_SHIFT_H2C_PKT_WRITEADDR_8821C)
-#define BIT_GET_H2C_PKT_WRITEADDR_8821C(x) (((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR_8821C) & BIT_MASK_H2C_PKT_WRITEADDR_8821C)
-
+#define BIT_H2C_PKT_WRITEADDR_8821C(x) \
+ (((x) & BIT_MASK_H2C_PKT_WRITEADDR_8821C) \
+ << BIT_SHIFT_H2C_PKT_WRITEADDR_8821C)
+#define BITS_H2C_PKT_WRITEADDR_8821C \
+ (BIT_MASK_H2C_PKT_WRITEADDR_8821C << BIT_SHIFT_H2C_PKT_WRITEADDR_8821C)
+#define BIT_CLEAR_H2C_PKT_WRITEADDR_8821C(x) \
+ ((x) & (~BITS_H2C_PKT_WRITEADDR_8821C))
+#define BIT_GET_H2C_PKT_WRITEADDR_8821C(x) \
+ (((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR_8821C) & \
+ BIT_MASK_H2C_PKT_WRITEADDR_8821C)
+#define BIT_SET_H2C_PKT_WRITEADDR_8821C(x, v) \
+ (BIT_CLEAR_H2C_PKT_WRITEADDR_8821C(x) | BIT_H2C_PKT_WRITEADDR_8821C(v))
/* 2 REG_MEM_PWR_CRTL_8821C */
#define BIT_MEM_BB_SD_8821C BIT(17)
@@ -1836,174 +2931,369 @@
#define BIT_MEM_WLMCU_LS_8821C BIT(1)
#define BIT_MEM_WLMCU_DS_8821C BIT(0)
-/* 2 REG_FW_DBG0_8821C */
-
-#define BIT_SHIFT_FW_DBG0_8821C 0
-#define BIT_MASK_FW_DBG0_8821C 0xffffffffL
-#define BIT_FW_DBG0_8821C(x) (((x) & BIT_MASK_FW_DBG0_8821C) << BIT_SHIFT_FW_DBG0_8821C)
-#define BIT_GET_FW_DBG0_8821C(x) (((x) >> BIT_SHIFT_FW_DBG0_8821C) & BIT_MASK_FW_DBG0_8821C)
-
-
-/* 2 REG_FW_DBG1_8821C */
-
-#define BIT_SHIFT_FW_DBG1_8821C 0
-#define BIT_MASK_FW_DBG1_8821C 0xffffffffL
-#define BIT_FW_DBG1_8821C(x) (((x) & BIT_MASK_FW_DBG1_8821C) << BIT_SHIFT_FW_DBG1_8821C)
-#define BIT_GET_FW_DBG1_8821C(x) (((x) >> BIT_SHIFT_FW_DBG1_8821C) & BIT_MASK_FW_DBG1_8821C)
-
-
-/* 2 REG_FW_DBG2_8821C */
-
-#define BIT_SHIFT_FW_DBG2_8821C 0
-#define BIT_MASK_FW_DBG2_8821C 0xffffffffL
-#define BIT_FW_DBG2_8821C(x) (((x) & BIT_MASK_FW_DBG2_8821C) << BIT_SHIFT_FW_DBG2_8821C)
-#define BIT_GET_FW_DBG2_8821C(x) (((x) >> BIT_SHIFT_FW_DBG2_8821C) & BIT_MASK_FW_DBG2_8821C)
-
-
-/* 2 REG_FW_DBG3_8821C */
-
-#define BIT_SHIFT_FW_DBG3_8821C 0
-#define BIT_MASK_FW_DBG3_8821C 0xffffffffL
-#define BIT_FW_DBG3_8821C(x) (((x) & BIT_MASK_FW_DBG3_8821C) << BIT_SHIFT_FW_DBG3_8821C)
-#define BIT_GET_FW_DBG3_8821C(x) (((x) >> BIT_SHIFT_FW_DBG3_8821C) & BIT_MASK_FW_DBG3_8821C)
-
+/* 2 REG_NOT_VALID_8821C */
-/* 2 REG_FW_DBG4_8821C */
+/* 2 REG_NOT_VALID_8821C */
-#define BIT_SHIFT_FW_DBG4_8821C 0
-#define BIT_MASK_FW_DBG4_8821C 0xffffffffL
-#define BIT_FW_DBG4_8821C(x) (((x) & BIT_MASK_FW_DBG4_8821C) << BIT_SHIFT_FW_DBG4_8821C)
-#define BIT_GET_FW_DBG4_8821C(x) (((x) >> BIT_SHIFT_FW_DBG4_8821C) & BIT_MASK_FW_DBG4_8821C)
+/* 2 REG_NOT_VALID_8821C */
+/* 2 REG_NOT_VALID_8821C */
-/* 2 REG_FW_DBG5_8821C */
+/* 2 REG_NOT_VALID_8821C */
-#define BIT_SHIFT_FW_DBG5_8821C 0
-#define BIT_MASK_FW_DBG5_8821C 0xffffffffL
-#define BIT_FW_DBG5_8821C(x) (((x) & BIT_MASK_FW_DBG5_8821C) << BIT_SHIFT_FW_DBG5_8821C)
-#define BIT_GET_FW_DBG5_8821C(x) (((x) >> BIT_SHIFT_FW_DBG5_8821C) & BIT_MASK_FW_DBG5_8821C)
+/* 2 REG_NOT_VALID_8821C */
+/* 2 REG_NOT_VALID_8821C */
/* 2 REG_FW_DBG6_8821C */
#define BIT_SHIFT_FW_DBG6_8821C 0
#define BIT_MASK_FW_DBG6_8821C 0xffffffffL
-#define BIT_FW_DBG6_8821C(x) (((x) & BIT_MASK_FW_DBG6_8821C) << BIT_SHIFT_FW_DBG6_8821C)
-#define BIT_GET_FW_DBG6_8821C(x) (((x) >> BIT_SHIFT_FW_DBG6_8821C) & BIT_MASK_FW_DBG6_8821C)
-
+#define BIT_FW_DBG6_8821C(x) \
+ (((x) & BIT_MASK_FW_DBG6_8821C) << BIT_SHIFT_FW_DBG6_8821C)
+#define BITS_FW_DBG6_8821C (BIT_MASK_FW_DBG6_8821C << BIT_SHIFT_FW_DBG6_8821C)
+#define BIT_CLEAR_FW_DBG6_8821C(x) ((x) & (~BITS_FW_DBG6_8821C))
+#define BIT_GET_FW_DBG6_8821C(x) \
+ (((x) >> BIT_SHIFT_FW_DBG6_8821C) & BIT_MASK_FW_DBG6_8821C)
+#define BIT_SET_FW_DBG6_8821C(x, v) \
+ (BIT_CLEAR_FW_DBG6_8821C(x) | BIT_FW_DBG6_8821C(v))
/* 2 REG_FW_DBG7_8821C */
#define BIT_SHIFT_FW_DBG7_8821C 0
#define BIT_MASK_FW_DBG7_8821C 0xffffffffL
-#define BIT_FW_DBG7_8821C(x) (((x) & BIT_MASK_FW_DBG7_8821C) << BIT_SHIFT_FW_DBG7_8821C)
-#define BIT_GET_FW_DBG7_8821C(x) (((x) >> BIT_SHIFT_FW_DBG7_8821C) & BIT_MASK_FW_DBG7_8821C)
+#define BIT_FW_DBG7_8821C(x) \
+ (((x) & BIT_MASK_FW_DBG7_8821C) << BIT_SHIFT_FW_DBG7_8821C)
+#define BITS_FW_DBG7_8821C (BIT_MASK_FW_DBG7_8821C << BIT_SHIFT_FW_DBG7_8821C)
+#define BIT_CLEAR_FW_DBG7_8821C(x) ((x) & (~BITS_FW_DBG7_8821C))
+#define BIT_GET_FW_DBG7_8821C(x) \
+ (((x) >> BIT_SHIFT_FW_DBG7_8821C) & BIT_MASK_FW_DBG7_8821C)
+#define BIT_SET_FW_DBG7_8821C(x, v) \
+ (BIT_CLEAR_FW_DBG7_8821C(x) | BIT_FW_DBG7_8821C(v))
+/* 2 REG_NOT_VALID_8821C */
/* 2 REG_NOT_VALID_8821C */
-/* 2 REG_CR_8821C */
+/* 2 REG_NOT_VALID_8821C */
-#define BIT_SHIFT_LBMODE_8821C 24
-#define BIT_MASK_LBMODE_8821C 0x1f
-#define BIT_LBMODE_8821C(x) (((x) & BIT_MASK_LBMODE_8821C) << BIT_SHIFT_LBMODE_8821C)
-#define BIT_GET_LBMODE_8821C(x) (((x) >> BIT_SHIFT_LBMODE_8821C) & BIT_MASK_LBMODE_8821C)
+/* 2 REG_NOT_VALID_8821C */
+/* 2 REG_NOT_VALID_8821C */
-#define BIT_SHIFT_NETYPE1_8821C 18
-#define BIT_MASK_NETYPE1_8821C 0x3
-#define BIT_NETYPE1_8821C(x) (((x) & BIT_MASK_NETYPE1_8821C) << BIT_SHIFT_NETYPE1_8821C)
-#define BIT_GET_NETYPE1_8821C(x) (((x) >> BIT_SHIFT_NETYPE1_8821C) & BIT_MASK_NETYPE1_8821C)
+/* 2 REG_NOT_VALID_8821C */
+/* 2 REG_NOT_VALID_8821C */
-#define BIT_SHIFT_NETYPE0_8821C 16
-#define BIT_MASK_NETYPE0_8821C 0x3
-#define BIT_NETYPE0_8821C(x) (((x) & BIT_MASK_NETYPE0_8821C) << BIT_SHIFT_NETYPE0_8821C)
-#define BIT_GET_NETYPE0_8821C(x) (((x) >> BIT_SHIFT_NETYPE0_8821C) & BIT_MASK_NETYPE0_8821C)
+/* 2 REG_NOT_VALID_8821C */
-#define BIT_I2C_MAILBOX_EN_8821C BIT(12)
-#define BIT_SHCUT_EN_8821C BIT(11)
-#define BIT_32K_CAL_TMR_EN_8821C BIT(10)
-#define BIT_MAC_SEC_EN_8821C BIT(9)
-#define BIT_ENSWBCN_8821C BIT(8)
-#define BIT_MACRXEN_8821C BIT(7)
-#define BIT_MACTXEN_8821C BIT(6)
-#define BIT_SCHEDULE_EN_8821C BIT(5)
-#define BIT_PROTOCOL_EN_8821C BIT(4)
-#define BIT_RXDMA_EN_8821C BIT(3)
-#define BIT_TXDMA_EN_8821C BIT(2)
-#define BIT_HCI_RXDMA_EN_8821C BIT(1)
-#define BIT_HCI_TXDMA_EN_8821C BIT(0)
+/* 2 REG_NOT_VALID_8821C */
/* 2 REG_NOT_VALID_8821C */
-/* 2 REG_PKT_BUFF_ACCESS_CTRL_8821C */
+/* 2 REG_NOT_VALID_8821C */
-#define BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8821C 0
-#define BIT_MASK_PKT_BUFF_ACCESS_CTRL_8821C 0xff
-#define BIT_PKT_BUFF_ACCESS_CTRL_8821C(x) (((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL_8821C) << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8821C)
-#define BIT_GET_PKT_BUFF_ACCESS_CTRL_8821C(x) (((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8821C) & BIT_MASK_PKT_BUFF_ACCESS_CTRL_8821C)
+/* 2 REG_NOT_VALID_8821C */
+/* 2 REG_NOT_VALID_8821C */
/* 2 REG_NOT_VALID_8821C */
-/* 2 REG_TSF_CLK_STATE_8821C */
-#define BIT_TSF_CLK_STABLE_8821C BIT(15)
+/* 2 REG_NOT_VALID_8821C */
-/* 2 REG_TXDMA_PQ_MAP_8821C */
+/* 2 REG_NOT_VALID_8821C */
-#define BIT_SHIFT_TXDMA_HIQ_MAP_8821C 14
-#define BIT_MASK_TXDMA_HIQ_MAP_8821C 0x3
-#define BIT_TXDMA_HIQ_MAP_8821C(x) (((x) & BIT_MASK_TXDMA_HIQ_MAP_8821C) << BIT_SHIFT_TXDMA_HIQ_MAP_8821C)
-#define BIT_GET_TXDMA_HIQ_MAP_8821C(x) (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8821C) & BIT_MASK_TXDMA_HIQ_MAP_8821C)
+/* 2 REG_NOT_VALID_8821C */
+/* 2 REG_NOT_VALID_8821C */
-#define BIT_SHIFT_TXDMA_MGQ_MAP_8821C 12
-#define BIT_MASK_TXDMA_MGQ_MAP_8821C 0x3
-#define BIT_TXDMA_MGQ_MAP_8821C(x) (((x) & BIT_MASK_TXDMA_MGQ_MAP_8821C) << BIT_SHIFT_TXDMA_MGQ_MAP_8821C)
-#define BIT_GET_TXDMA_MGQ_MAP_8821C(x) (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8821C) & BIT_MASK_TXDMA_MGQ_MAP_8821C)
+/* 2 REG_NOT_VALID_8821C */
+/* 2 REG_NOT_VALID_8821C */
-#define BIT_SHIFT_TXDMA_BKQ_MAP_8821C 10
-#define BIT_MASK_TXDMA_BKQ_MAP_8821C 0x3
-#define BIT_TXDMA_BKQ_MAP_8821C(x) (((x) & BIT_MASK_TXDMA_BKQ_MAP_8821C) << BIT_SHIFT_TXDMA_BKQ_MAP_8821C)
-#define BIT_GET_TXDMA_BKQ_MAP_8821C(x) (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8821C) & BIT_MASK_TXDMA_BKQ_MAP_8821C)
+/* 2 REG_NOT_VALID_8821C */
+/* 2 REG_NOT_VALID_8821C */
-#define BIT_SHIFT_TXDMA_BEQ_MAP_8821C 8
-#define BIT_MASK_TXDMA_BEQ_MAP_8821C 0x3
-#define BIT_TXDMA_BEQ_MAP_8821C(x) (((x) & BIT_MASK_TXDMA_BEQ_MAP_8821C) << BIT_SHIFT_TXDMA_BEQ_MAP_8821C)
-#define BIT_GET_TXDMA_BEQ_MAP_8821C(x) (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8821C) & BIT_MASK_TXDMA_BEQ_MAP_8821C)
+/* 2 REG_NOT_VALID_8821C */
+/* 2 REG_NOT_VALID_8821C */
-#define BIT_SHIFT_TXDMA_VIQ_MAP_8821C 6
-#define BIT_MASK_TXDMA_VIQ_MAP_8821C 0x3
-#define BIT_TXDMA_VIQ_MAP_8821C(x) (((x) & BIT_MASK_TXDMA_VIQ_MAP_8821C) << BIT_SHIFT_TXDMA_VIQ_MAP_8821C)
-#define BIT_GET_TXDMA_VIQ_MAP_8821C(x) (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8821C) & BIT_MASK_TXDMA_VIQ_MAP_8821C)
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_CR_8821C */
+
+#define BIT_SHIFT_LBMODE_8821C 24
+#define BIT_MASK_LBMODE_8821C 0x1f
+#define BIT_LBMODE_8821C(x) \
+ (((x) & BIT_MASK_LBMODE_8821C) << BIT_SHIFT_LBMODE_8821C)
+#define BITS_LBMODE_8821C (BIT_MASK_LBMODE_8821C << BIT_SHIFT_LBMODE_8821C)
+#define BIT_CLEAR_LBMODE_8821C(x) ((x) & (~BITS_LBMODE_8821C))
+#define BIT_GET_LBMODE_8821C(x) \
+ (((x) >> BIT_SHIFT_LBMODE_8821C) & BIT_MASK_LBMODE_8821C)
+#define BIT_SET_LBMODE_8821C(x, v) \
+ (BIT_CLEAR_LBMODE_8821C(x) | BIT_LBMODE_8821C(v))
+
+#define BIT_SHIFT_NETYPE1_8821C 18
+#define BIT_MASK_NETYPE1_8821C 0x3
+#define BIT_NETYPE1_8821C(x) \
+ (((x) & BIT_MASK_NETYPE1_8821C) << BIT_SHIFT_NETYPE1_8821C)
+#define BITS_NETYPE1_8821C (BIT_MASK_NETYPE1_8821C << BIT_SHIFT_NETYPE1_8821C)
+#define BIT_CLEAR_NETYPE1_8821C(x) ((x) & (~BITS_NETYPE1_8821C))
+#define BIT_GET_NETYPE1_8821C(x) \
+ (((x) >> BIT_SHIFT_NETYPE1_8821C) & BIT_MASK_NETYPE1_8821C)
+#define BIT_SET_NETYPE1_8821C(x, v) \
+ (BIT_CLEAR_NETYPE1_8821C(x) | BIT_NETYPE1_8821C(v))
+
+#define BIT_SHIFT_NETYPE0_8821C 16
+#define BIT_MASK_NETYPE0_8821C 0x3
+#define BIT_NETYPE0_8821C(x) \
+ (((x) & BIT_MASK_NETYPE0_8821C) << BIT_SHIFT_NETYPE0_8821C)
+#define BITS_NETYPE0_8821C (BIT_MASK_NETYPE0_8821C << BIT_SHIFT_NETYPE0_8821C)
+#define BIT_CLEAR_NETYPE0_8821C(x) ((x) & (~BITS_NETYPE0_8821C))
+#define BIT_GET_NETYPE0_8821C(x) \
+ (((x) >> BIT_SHIFT_NETYPE0_8821C) & BIT_MASK_NETYPE0_8821C)
+#define BIT_SET_NETYPE0_8821C(x, v) \
+ (BIT_CLEAR_NETYPE0_8821C(x) | BIT_NETYPE0_8821C(v))
+
+#define BIT_COUNTER_STS_EN_8821C BIT(13)
+#define BIT_I2C_MAILBOX_EN_8821C BIT(12)
+#define BIT_SHCUT_EN_8821C BIT(11)
+#define BIT_32K_CAL_TMR_EN_8821C BIT(10)
+#define BIT_MAC_SEC_EN_8821C BIT(9)
+#define BIT_ENSWBCN_8821C BIT(8)
+#define BIT_MACRXEN_8821C BIT(7)
+#define BIT_MACTXEN_8821C BIT(6)
+#define BIT_SCHEDULE_EN_8821C BIT(5)
+#define BIT_PROTOCOL_EN_8821C BIT(4)
+#define BIT_RXDMA_EN_8821C BIT(3)
+#define BIT_TXDMA_EN_8821C BIT(2)
+#define BIT_HCI_RXDMA_EN_8821C BIT(1)
+#define BIT_HCI_TXDMA_EN_8821C BIT(0)
+
+/* 2 REG_PG_SIZE_8821C */
+
+#define BIT_SHIFT_DBG_FIFO_SEL_8821C 16
+#define BIT_MASK_DBG_FIFO_SEL_8821C 0xff
+#define BIT_DBG_FIFO_SEL_8821C(x) \
+ (((x) & BIT_MASK_DBG_FIFO_SEL_8821C) << BIT_SHIFT_DBG_FIFO_SEL_8821C)
+#define BITS_DBG_FIFO_SEL_8821C \
+ (BIT_MASK_DBG_FIFO_SEL_8821C << BIT_SHIFT_DBG_FIFO_SEL_8821C)
+#define BIT_CLEAR_DBG_FIFO_SEL_8821C(x) ((x) & (~BITS_DBG_FIFO_SEL_8821C))
+#define BIT_GET_DBG_FIFO_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_DBG_FIFO_SEL_8821C) & BIT_MASK_DBG_FIFO_SEL_8821C)
+#define BIT_SET_DBG_FIFO_SEL_8821C(x, v) \
+ (BIT_CLEAR_DBG_FIFO_SEL_8821C(x) | BIT_DBG_FIFO_SEL_8821C(v))
+
+/* 2 REG_PKT_BUFF_ACCESS_CTRL_8821C */
+
+#define BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8821C 0
+#define BIT_MASK_PKT_BUFF_ACCESS_CTRL_8821C 0xff
+#define BIT_PKT_BUFF_ACCESS_CTRL_8821C(x) \
+ (((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL_8821C) \
+ << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8821C)
+#define BITS_PKT_BUFF_ACCESS_CTRL_8821C \
+ (BIT_MASK_PKT_BUFF_ACCESS_CTRL_8821C \
+ << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8821C)
+#define BIT_CLEAR_PKT_BUFF_ACCESS_CTRL_8821C(x) \
+ ((x) & (~BITS_PKT_BUFF_ACCESS_CTRL_8821C))
+#define BIT_GET_PKT_BUFF_ACCESS_CTRL_8821C(x) \
+ (((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8821C) & \
+ BIT_MASK_PKT_BUFF_ACCESS_CTRL_8821C)
+#define BIT_SET_PKT_BUFF_ACCESS_CTRL_8821C(x, v) \
+ (BIT_CLEAR_PKT_BUFF_ACCESS_CTRL_8821C(x) | \
+ BIT_PKT_BUFF_ACCESS_CTRL_8821C(v))
+
+/* 2 REG_TSF_CLK_STATE_8821C */
+#define BIT_TSF_CLK_STABLE_8821C BIT(15)
+
+/* 2 REG_TXDMA_PQ_MAP_8821C */
+
+#define BIT_SHIFT_TXDMA_H2C_MAP_8821C 16
+#define BIT_MASK_TXDMA_H2C_MAP_8821C 0x3
+#define BIT_TXDMA_H2C_MAP_8821C(x) \
+ (((x) & BIT_MASK_TXDMA_H2C_MAP_8821C) << BIT_SHIFT_TXDMA_H2C_MAP_8821C)
+#define BITS_TXDMA_H2C_MAP_8821C \
+ (BIT_MASK_TXDMA_H2C_MAP_8821C << BIT_SHIFT_TXDMA_H2C_MAP_8821C)
+#define BIT_CLEAR_TXDMA_H2C_MAP_8821C(x) ((x) & (~BITS_TXDMA_H2C_MAP_8821C))
+#define BIT_GET_TXDMA_H2C_MAP_8821C(x) \
+ (((x) >> BIT_SHIFT_TXDMA_H2C_MAP_8821C) & BIT_MASK_TXDMA_H2C_MAP_8821C)
+#define BIT_SET_TXDMA_H2C_MAP_8821C(x, v) \
+ (BIT_CLEAR_TXDMA_H2C_MAP_8821C(x) | BIT_TXDMA_H2C_MAP_8821C(v))
+
+#define BIT_SHIFT_TXDMA_HIQ_MAP_8821C 14
+#define BIT_MASK_TXDMA_HIQ_MAP_8821C 0x3
+#define BIT_TXDMA_HIQ_MAP_8821C(x) \
+ (((x) & BIT_MASK_TXDMA_HIQ_MAP_8821C) << BIT_SHIFT_TXDMA_HIQ_MAP_8821C)
+#define BITS_TXDMA_HIQ_MAP_8821C \
+ (BIT_MASK_TXDMA_HIQ_MAP_8821C << BIT_SHIFT_TXDMA_HIQ_MAP_8821C)
+#define BIT_CLEAR_TXDMA_HIQ_MAP_8821C(x) ((x) & (~BITS_TXDMA_HIQ_MAP_8821C))
+#define BIT_GET_TXDMA_HIQ_MAP_8821C(x) \
+ (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8821C) & BIT_MASK_TXDMA_HIQ_MAP_8821C)
+#define BIT_SET_TXDMA_HIQ_MAP_8821C(x, v) \
+ (BIT_CLEAR_TXDMA_HIQ_MAP_8821C(x) | BIT_TXDMA_HIQ_MAP_8821C(v))
+
+#define BIT_SHIFT_TXDMA_MGQ_MAP_8821C 12
+#define BIT_MASK_TXDMA_MGQ_MAP_8821C 0x3
+#define BIT_TXDMA_MGQ_MAP_8821C(x) \
+ (((x) & BIT_MASK_TXDMA_MGQ_MAP_8821C) << BIT_SHIFT_TXDMA_MGQ_MAP_8821C)
+#define BITS_TXDMA_MGQ_MAP_8821C \
+ (BIT_MASK_TXDMA_MGQ_MAP_8821C << BIT_SHIFT_TXDMA_MGQ_MAP_8821C)
+#define BIT_CLEAR_TXDMA_MGQ_MAP_8821C(x) ((x) & (~BITS_TXDMA_MGQ_MAP_8821C))
+#define BIT_GET_TXDMA_MGQ_MAP_8821C(x) \
+ (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8821C) & BIT_MASK_TXDMA_MGQ_MAP_8821C)
+#define BIT_SET_TXDMA_MGQ_MAP_8821C(x, v) \
+ (BIT_CLEAR_TXDMA_MGQ_MAP_8821C(x) | BIT_TXDMA_MGQ_MAP_8821C(v))
+
+#define BIT_SHIFT_TXDMA_BKQ_MAP_8821C 10
+#define BIT_MASK_TXDMA_BKQ_MAP_8821C 0x3
+#define BIT_TXDMA_BKQ_MAP_8821C(x) \
+ (((x) & BIT_MASK_TXDMA_BKQ_MAP_8821C) << BIT_SHIFT_TXDMA_BKQ_MAP_8821C)
+#define BITS_TXDMA_BKQ_MAP_8821C \
+ (BIT_MASK_TXDMA_BKQ_MAP_8821C << BIT_SHIFT_TXDMA_BKQ_MAP_8821C)
+#define BIT_CLEAR_TXDMA_BKQ_MAP_8821C(x) ((x) & (~BITS_TXDMA_BKQ_MAP_8821C))
+#define BIT_GET_TXDMA_BKQ_MAP_8821C(x) \
+ (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8821C) & BIT_MASK_TXDMA_BKQ_MAP_8821C)
+#define BIT_SET_TXDMA_BKQ_MAP_8821C(x, v) \
+ (BIT_CLEAR_TXDMA_BKQ_MAP_8821C(x) | BIT_TXDMA_BKQ_MAP_8821C(v))
+
+#define BIT_SHIFT_TXDMA_BEQ_MAP_8821C 8
+#define BIT_MASK_TXDMA_BEQ_MAP_8821C 0x3
+#define BIT_TXDMA_BEQ_MAP_8821C(x) \
+ (((x) & BIT_MASK_TXDMA_BEQ_MAP_8821C) << BIT_SHIFT_TXDMA_BEQ_MAP_8821C)
+#define BITS_TXDMA_BEQ_MAP_8821C \
+ (BIT_MASK_TXDMA_BEQ_MAP_8821C << BIT_SHIFT_TXDMA_BEQ_MAP_8821C)
+#define BIT_CLEAR_TXDMA_BEQ_MAP_8821C(x) ((x) & (~BITS_TXDMA_BEQ_MAP_8821C))
+#define BIT_GET_TXDMA_BEQ_MAP_8821C(x) \
+ (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8821C) & BIT_MASK_TXDMA_BEQ_MAP_8821C)
+#define BIT_SET_TXDMA_BEQ_MAP_8821C(x, v) \
+ (BIT_CLEAR_TXDMA_BEQ_MAP_8821C(x) | BIT_TXDMA_BEQ_MAP_8821C(v))
+#define BIT_SHIFT_TXDMA_VIQ_MAP_8821C 6
+#define BIT_MASK_TXDMA_VIQ_MAP_8821C 0x3
+#define BIT_TXDMA_VIQ_MAP_8821C(x) \
+ (((x) & BIT_MASK_TXDMA_VIQ_MAP_8821C) << BIT_SHIFT_TXDMA_VIQ_MAP_8821C)
+#define BITS_TXDMA_VIQ_MAP_8821C \
+ (BIT_MASK_TXDMA_VIQ_MAP_8821C << BIT_SHIFT_TXDMA_VIQ_MAP_8821C)
+#define BIT_CLEAR_TXDMA_VIQ_MAP_8821C(x) ((x) & (~BITS_TXDMA_VIQ_MAP_8821C))
+#define BIT_GET_TXDMA_VIQ_MAP_8821C(x) \
+ (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8821C) & BIT_MASK_TXDMA_VIQ_MAP_8821C)
+#define BIT_SET_TXDMA_VIQ_MAP_8821C(x, v) \
+ (BIT_CLEAR_TXDMA_VIQ_MAP_8821C(x) | BIT_TXDMA_VIQ_MAP_8821C(v))
#define BIT_SHIFT_TXDMA_VOQ_MAP_8821C 4
#define BIT_MASK_TXDMA_VOQ_MAP_8821C 0x3
-#define BIT_TXDMA_VOQ_MAP_8821C(x) (((x) & BIT_MASK_TXDMA_VOQ_MAP_8821C) << BIT_SHIFT_TXDMA_VOQ_MAP_8821C)
-#define BIT_GET_TXDMA_VOQ_MAP_8821C(x) (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8821C) & BIT_MASK_TXDMA_VOQ_MAP_8821C)
+#define BIT_TXDMA_VOQ_MAP_8821C(x) \
+ (((x) & BIT_MASK_TXDMA_VOQ_MAP_8821C) << BIT_SHIFT_TXDMA_VOQ_MAP_8821C)
+#define BITS_TXDMA_VOQ_MAP_8821C \
+ (BIT_MASK_TXDMA_VOQ_MAP_8821C << BIT_SHIFT_TXDMA_VOQ_MAP_8821C)
+#define BIT_CLEAR_TXDMA_VOQ_MAP_8821C(x) ((x) & (~BITS_TXDMA_VOQ_MAP_8821C))
+#define BIT_GET_TXDMA_VOQ_MAP_8821C(x) \
+ (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8821C) & BIT_MASK_TXDMA_VOQ_MAP_8821C)
+#define BIT_SET_TXDMA_VOQ_MAP_8821C(x, v) \
+ (BIT_CLEAR_TXDMA_VOQ_MAP_8821C(x) | BIT_TXDMA_VOQ_MAP_8821C(v))
#define BIT_RXDMA_AGG_EN_8821C BIT(2)
#define BIT_RXSHFT_EN_8821C BIT(1)
#define BIT_RXDMA_ARBBW_EN_8821C BIT(0)
+/* 2 REG_NOT_VALID_8821C */
+
/* 2 REG_TRXFF_BNDY_8821C */
#define BIT_SHIFT_RXFFOVFL_RSV_V2_8821C 8
#define BIT_MASK_RXFFOVFL_RSV_V2_8821C 0xf
-#define BIT_RXFFOVFL_RSV_V2_8821C(x) (((x) & BIT_MASK_RXFFOVFL_RSV_V2_8821C) << BIT_SHIFT_RXFFOVFL_RSV_V2_8821C)
-#define BIT_GET_RXFFOVFL_RSV_V2_8821C(x) (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8821C) & BIT_MASK_RXFFOVFL_RSV_V2_8821C)
-
-
-#define BIT_SHIFT_TXPKTBUF_PGBNDY_8821C 0
-#define BIT_MASK_TXPKTBUF_PGBNDY_8821C 0xff
-#define BIT_TXPKTBUF_PGBNDY_8821C(x) (((x) & BIT_MASK_TXPKTBUF_PGBNDY_8821C) << BIT_SHIFT_TXPKTBUF_PGBNDY_8821C)
-#define BIT_GET_TXPKTBUF_PGBNDY_8821C(x) (((x) >> BIT_SHIFT_TXPKTBUF_PGBNDY_8821C) & BIT_MASK_TXPKTBUF_PGBNDY_8821C)
-
+#define BIT_RXFFOVFL_RSV_V2_8821C(x) \
+ (((x) & BIT_MASK_RXFFOVFL_RSV_V2_8821C) \
+ << BIT_SHIFT_RXFFOVFL_RSV_V2_8821C)
+#define BITS_RXFFOVFL_RSV_V2_8821C \
+ (BIT_MASK_RXFFOVFL_RSV_V2_8821C << BIT_SHIFT_RXFFOVFL_RSV_V2_8821C)
+#define BIT_CLEAR_RXFFOVFL_RSV_V2_8821C(x) ((x) & (~BITS_RXFFOVFL_RSV_V2_8821C))
+#define BIT_GET_RXFFOVFL_RSV_V2_8821C(x) \
+ (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8821C) & \
+ BIT_MASK_RXFFOVFL_RSV_V2_8821C)
+#define BIT_SET_RXFFOVFL_RSV_V2_8821C(x, v) \
+ (BIT_CLEAR_RXFFOVFL_RSV_V2_8821C(x) | BIT_RXFFOVFL_RSV_V2_8821C(v))
/* 2 REG_PTA_I2C_MBOX_8821C */
@@ -2011,21 +3301,44 @@
#define BIT_SHIFT_I2C_M_STATUS_8821C 8
#define BIT_MASK_I2C_M_STATUS_8821C 0xf
-#define BIT_I2C_M_STATUS_8821C(x) (((x) & BIT_MASK_I2C_M_STATUS_8821C) << BIT_SHIFT_I2C_M_STATUS_8821C)
-#define BIT_GET_I2C_M_STATUS_8821C(x) (((x) >> BIT_SHIFT_I2C_M_STATUS_8821C) & BIT_MASK_I2C_M_STATUS_8821C)
-
+#define BIT_I2C_M_STATUS_8821C(x) \
+ (((x) & BIT_MASK_I2C_M_STATUS_8821C) << BIT_SHIFT_I2C_M_STATUS_8821C)
+#define BITS_I2C_M_STATUS_8821C \
+ (BIT_MASK_I2C_M_STATUS_8821C << BIT_SHIFT_I2C_M_STATUS_8821C)
+#define BIT_CLEAR_I2C_M_STATUS_8821C(x) ((x) & (~BITS_I2C_M_STATUS_8821C))
+#define BIT_GET_I2C_M_STATUS_8821C(x) \
+ (((x) >> BIT_SHIFT_I2C_M_STATUS_8821C) & BIT_MASK_I2C_M_STATUS_8821C)
+#define BIT_SET_I2C_M_STATUS_8821C(x, v) \
+ (BIT_CLEAR_I2C_M_STATUS_8821C(x) | BIT_I2C_M_STATUS_8821C(v))
#define BIT_SHIFT_I2C_M_BUS_GNT_FW_8821C 4
#define BIT_MASK_I2C_M_BUS_GNT_FW_8821C 0x7
-#define BIT_I2C_M_BUS_GNT_FW_8821C(x) (((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8821C) << BIT_SHIFT_I2C_M_BUS_GNT_FW_8821C)
-#define BIT_GET_I2C_M_BUS_GNT_FW_8821C(x) (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8821C) & BIT_MASK_I2C_M_BUS_GNT_FW_8821C)
+#define BIT_I2C_M_BUS_GNT_FW_8821C(x) \
+ (((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8821C) \
+ << BIT_SHIFT_I2C_M_BUS_GNT_FW_8821C)
+#define BITS_I2C_M_BUS_GNT_FW_8821C \
+ (BIT_MASK_I2C_M_BUS_GNT_FW_8821C << BIT_SHIFT_I2C_M_BUS_GNT_FW_8821C)
+#define BIT_CLEAR_I2C_M_BUS_GNT_FW_8821C(x) \
+ ((x) & (~BITS_I2C_M_BUS_GNT_FW_8821C))
+#define BIT_GET_I2C_M_BUS_GNT_FW_8821C(x) \
+ (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8821C) & \
+ BIT_MASK_I2C_M_BUS_GNT_FW_8821C)
+#define BIT_SET_I2C_M_BUS_GNT_FW_8821C(x, v) \
+ (BIT_CLEAR_I2C_M_BUS_GNT_FW_8821C(x) | BIT_I2C_M_BUS_GNT_FW_8821C(v))
#define BIT_I2C_M_GNT_FW_8821C BIT(3)
#define BIT_SHIFT_I2C_M_SPEED_8821C 1
#define BIT_MASK_I2C_M_SPEED_8821C 0x3
-#define BIT_I2C_M_SPEED_8821C(x) (((x) & BIT_MASK_I2C_M_SPEED_8821C) << BIT_SHIFT_I2C_M_SPEED_8821C)
-#define BIT_GET_I2C_M_SPEED_8821C(x) (((x) >> BIT_SHIFT_I2C_M_SPEED_8821C) & BIT_MASK_I2C_M_SPEED_8821C)
+#define BIT_I2C_M_SPEED_8821C(x) \
+ (((x) & BIT_MASK_I2C_M_SPEED_8821C) << BIT_SHIFT_I2C_M_SPEED_8821C)
+#define BITS_I2C_M_SPEED_8821C \
+ (BIT_MASK_I2C_M_SPEED_8821C << BIT_SHIFT_I2C_M_SPEED_8821C)
+#define BIT_CLEAR_I2C_M_SPEED_8821C(x) ((x) & (~BITS_I2C_M_SPEED_8821C))
+#define BIT_GET_I2C_M_SPEED_8821C(x) \
+ (((x) >> BIT_SHIFT_I2C_M_SPEED_8821C) & BIT_MASK_I2C_M_SPEED_8821C)
+#define BIT_SET_I2C_M_SPEED_8821C(x, v) \
+ (BIT_CLEAR_I2C_M_SPEED_8821C(x) | BIT_I2C_M_SPEED_8821C(v))
#define BIT_I2C_M_UNLOCK_8821C BIT(0)
@@ -2035,9 +3348,15 @@
#define BIT_SHIFT_RXFF0_BNDY_V2_8821C 0
#define BIT_MASK_RXFF0_BNDY_V2_8821C 0x3ffff
-#define BIT_RXFF0_BNDY_V2_8821C(x) (((x) & BIT_MASK_RXFF0_BNDY_V2_8821C) << BIT_SHIFT_RXFF0_BNDY_V2_8821C)
-#define BIT_GET_RXFF0_BNDY_V2_8821C(x) (((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8821C) & BIT_MASK_RXFF0_BNDY_V2_8821C)
-
+#define BIT_RXFF0_BNDY_V2_8821C(x) \
+ (((x) & BIT_MASK_RXFF0_BNDY_V2_8821C) << BIT_SHIFT_RXFF0_BNDY_V2_8821C)
+#define BITS_RXFF0_BNDY_V2_8821C \
+ (BIT_MASK_RXFF0_BNDY_V2_8821C << BIT_SHIFT_RXFF0_BNDY_V2_8821C)
+#define BIT_CLEAR_RXFF0_BNDY_V2_8821C(x) ((x) & (~BITS_RXFF0_BNDY_V2_8821C))
+#define BIT_GET_RXFF0_BNDY_V2_8821C(x) \
+ (((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8821C) & BIT_MASK_RXFF0_BNDY_V2_8821C)
+#define BIT_SET_RXFF0_BNDY_V2_8821C(x, v) \
+ (BIT_CLEAR_RXFF0_BNDY_V2_8821C(x) | BIT_RXFF0_BNDY_V2_8821C(v))
/* 2 REG_FE1IMR_8821C */
#define BIT_FS_RXDMA2_DONE_INT_EN_8821C BIT(28)
@@ -2104,9 +3423,15 @@
#define BIT_SHIFT_CPWM_MOD_8821C 24
#define BIT_MASK_CPWM_MOD_8821C 0x7f
-#define BIT_CPWM_MOD_8821C(x) (((x) & BIT_MASK_CPWM_MOD_8821C) << BIT_SHIFT_CPWM_MOD_8821C)
-#define BIT_GET_CPWM_MOD_8821C(x) (((x) >> BIT_SHIFT_CPWM_MOD_8821C) & BIT_MASK_CPWM_MOD_8821C)
-
+#define BIT_CPWM_MOD_8821C(x) \
+ (((x) & BIT_MASK_CPWM_MOD_8821C) << BIT_SHIFT_CPWM_MOD_8821C)
+#define BITS_CPWM_MOD_8821C \
+ (BIT_MASK_CPWM_MOD_8821C << BIT_SHIFT_CPWM_MOD_8821C)
+#define BIT_CLEAR_CPWM_MOD_8821C(x) ((x) & (~BITS_CPWM_MOD_8821C))
+#define BIT_GET_CPWM_MOD_8821C(x) \
+ (((x) >> BIT_SHIFT_CPWM_MOD_8821C) & BIT_MASK_CPWM_MOD_8821C)
+#define BIT_SET_CPWM_MOD_8821C(x, v) \
+ (BIT_CLEAR_CPWM_MOD_8821C(x) | BIT_CPWM_MOD_8821C(v))
/* 2 REG_FWIMR_8821C */
#define BIT_FS_TXBCNOK_MB7_INT_EN_8821C BIT(31)
@@ -2224,8 +3549,17 @@
#define BIT_SHIFT_PKTBUF_WRITE_EN_8821C 24
#define BIT_MASK_PKTBUF_WRITE_EN_8821C 0xff
-#define BIT_PKTBUF_WRITE_EN_8821C(x) (((x) & BIT_MASK_PKTBUF_WRITE_EN_8821C) << BIT_SHIFT_PKTBUF_WRITE_EN_8821C)
-#define BIT_GET_PKTBUF_WRITE_EN_8821C(x) (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8821C) & BIT_MASK_PKTBUF_WRITE_EN_8821C)
+#define BIT_PKTBUF_WRITE_EN_8821C(x) \
+ (((x) & BIT_MASK_PKTBUF_WRITE_EN_8821C) \
+ << BIT_SHIFT_PKTBUF_WRITE_EN_8821C)
+#define BITS_PKTBUF_WRITE_EN_8821C \
+ (BIT_MASK_PKTBUF_WRITE_EN_8821C << BIT_SHIFT_PKTBUF_WRITE_EN_8821C)
+#define BIT_CLEAR_PKTBUF_WRITE_EN_8821C(x) ((x) & (~BITS_PKTBUF_WRITE_EN_8821C))
+#define BIT_GET_PKTBUF_WRITE_EN_8821C(x) \
+ (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8821C) & \
+ BIT_MASK_PKTBUF_WRITE_EN_8821C)
+#define BIT_SET_PKTBUF_WRITE_EN_8821C(x, v) \
+ (BIT_CLEAR_PKTBUF_WRITE_EN_8821C(x) | BIT_PKTBUF_WRITE_EN_8821C(v))
#define BIT_TXRPTBUF_DBG_8821C BIT(23)
@@ -2235,42 +3569,81 @@
#define BIT_SHIFT_PKTBUF_DBG_ADDR_8821C 0
#define BIT_MASK_PKTBUF_DBG_ADDR_8821C 0x1fff
-#define BIT_PKTBUF_DBG_ADDR_8821C(x) (((x) & BIT_MASK_PKTBUF_DBG_ADDR_8821C) << BIT_SHIFT_PKTBUF_DBG_ADDR_8821C)
-#define BIT_GET_PKTBUF_DBG_ADDR_8821C(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8821C) & BIT_MASK_PKTBUF_DBG_ADDR_8821C)
-
+#define BIT_PKTBUF_DBG_ADDR_8821C(x) \
+ (((x) & BIT_MASK_PKTBUF_DBG_ADDR_8821C) \
+ << BIT_SHIFT_PKTBUF_DBG_ADDR_8821C)
+#define BITS_PKTBUF_DBG_ADDR_8821C \
+ (BIT_MASK_PKTBUF_DBG_ADDR_8821C << BIT_SHIFT_PKTBUF_DBG_ADDR_8821C)
+#define BIT_CLEAR_PKTBUF_DBG_ADDR_8821C(x) ((x) & (~BITS_PKTBUF_DBG_ADDR_8821C))
+#define BIT_GET_PKTBUF_DBG_ADDR_8821C(x) \
+ (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8821C) & \
+ BIT_MASK_PKTBUF_DBG_ADDR_8821C)
+#define BIT_SET_PKTBUF_DBG_ADDR_8821C(x, v) \
+ (BIT_CLEAR_PKTBUF_DBG_ADDR_8821C(x) | BIT_PKTBUF_DBG_ADDR_8821C(v))
/* 2 REG_PKTBUF_DBG_DATA_L_8821C */
#define BIT_SHIFT_PKTBUF_DBG_DATA_L_8821C 0
#define BIT_MASK_PKTBUF_DBG_DATA_L_8821C 0xffffffffL
-#define BIT_PKTBUF_DBG_DATA_L_8821C(x) (((x) & BIT_MASK_PKTBUF_DBG_DATA_L_8821C) << BIT_SHIFT_PKTBUF_DBG_DATA_L_8821C)
-#define BIT_GET_PKTBUF_DBG_DATA_L_8821C(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8821C) & BIT_MASK_PKTBUF_DBG_DATA_L_8821C)
-
+#define BIT_PKTBUF_DBG_DATA_L_8821C(x) \
+ (((x) & BIT_MASK_PKTBUF_DBG_DATA_L_8821C) \
+ << BIT_SHIFT_PKTBUF_DBG_DATA_L_8821C)
+#define BITS_PKTBUF_DBG_DATA_L_8821C \
+ (BIT_MASK_PKTBUF_DBG_DATA_L_8821C << BIT_SHIFT_PKTBUF_DBG_DATA_L_8821C)
+#define BIT_CLEAR_PKTBUF_DBG_DATA_L_8821C(x) \
+ ((x) & (~BITS_PKTBUF_DBG_DATA_L_8821C))
+#define BIT_GET_PKTBUF_DBG_DATA_L_8821C(x) \
+ (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8821C) & \
+ BIT_MASK_PKTBUF_DBG_DATA_L_8821C)
+#define BIT_SET_PKTBUF_DBG_DATA_L_8821C(x, v) \
+ (BIT_CLEAR_PKTBUF_DBG_DATA_L_8821C(x) | BIT_PKTBUF_DBG_DATA_L_8821C(v))
/* 2 REG_PKTBUF_DBG_DATA_H_8821C */
#define BIT_SHIFT_PKTBUF_DBG_DATA_H_8821C 0
#define BIT_MASK_PKTBUF_DBG_DATA_H_8821C 0xffffffffL
-#define BIT_PKTBUF_DBG_DATA_H_8821C(x) (((x) & BIT_MASK_PKTBUF_DBG_DATA_H_8821C) << BIT_SHIFT_PKTBUF_DBG_DATA_H_8821C)
-#define BIT_GET_PKTBUF_DBG_DATA_H_8821C(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8821C) & BIT_MASK_PKTBUF_DBG_DATA_H_8821C)
-
+#define BIT_PKTBUF_DBG_DATA_H_8821C(x) \
+ (((x) & BIT_MASK_PKTBUF_DBG_DATA_H_8821C) \
+ << BIT_SHIFT_PKTBUF_DBG_DATA_H_8821C)
+#define BITS_PKTBUF_DBG_DATA_H_8821C \
+ (BIT_MASK_PKTBUF_DBG_DATA_H_8821C << BIT_SHIFT_PKTBUF_DBG_DATA_H_8821C)
+#define BIT_CLEAR_PKTBUF_DBG_DATA_H_8821C(x) \
+ ((x) & (~BITS_PKTBUF_DBG_DATA_H_8821C))
+#define BIT_GET_PKTBUF_DBG_DATA_H_8821C(x) \
+ (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8821C) & \
+ BIT_MASK_PKTBUF_DBG_DATA_H_8821C)
+#define BIT_SET_PKTBUF_DBG_DATA_H_8821C(x, v) \
+ (BIT_CLEAR_PKTBUF_DBG_DATA_H_8821C(x) | BIT_PKTBUF_DBG_DATA_H_8821C(v))
/* 2 REG_CPWM2_8821C */
#define BIT_SHIFT_L0S_TO_RCVY_NUM_8821C 16
#define BIT_MASK_L0S_TO_RCVY_NUM_8821C 0xff
-#define BIT_L0S_TO_RCVY_NUM_8821C(x) (((x) & BIT_MASK_L0S_TO_RCVY_NUM_8821C) << BIT_SHIFT_L0S_TO_RCVY_NUM_8821C)
-#define BIT_GET_L0S_TO_RCVY_NUM_8821C(x) (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8821C) & BIT_MASK_L0S_TO_RCVY_NUM_8821C)
+#define BIT_L0S_TO_RCVY_NUM_8821C(x) \
+ (((x) & BIT_MASK_L0S_TO_RCVY_NUM_8821C) \
+ << BIT_SHIFT_L0S_TO_RCVY_NUM_8821C)
+#define BITS_L0S_TO_RCVY_NUM_8821C \
+ (BIT_MASK_L0S_TO_RCVY_NUM_8821C << BIT_SHIFT_L0S_TO_RCVY_NUM_8821C)
+#define BIT_CLEAR_L0S_TO_RCVY_NUM_8821C(x) ((x) & (~BITS_L0S_TO_RCVY_NUM_8821C))
+#define BIT_GET_L0S_TO_RCVY_NUM_8821C(x) \
+ (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8821C) & \
+ BIT_MASK_L0S_TO_RCVY_NUM_8821C)
+#define BIT_SET_L0S_TO_RCVY_NUM_8821C(x, v) \
+ (BIT_CLEAR_L0S_TO_RCVY_NUM_8821C(x) | BIT_L0S_TO_RCVY_NUM_8821C(v))
#define BIT_CPWM2_TOGGLING_8821C BIT(15)
#define BIT_SHIFT_CPWM2_MOD_8821C 0
#define BIT_MASK_CPWM2_MOD_8821C 0x7fff
-#define BIT_CPWM2_MOD_8821C(x) (((x) & BIT_MASK_CPWM2_MOD_8821C) << BIT_SHIFT_CPWM2_MOD_8821C)
-#define BIT_GET_CPWM2_MOD_8821C(x) (((x) >> BIT_SHIFT_CPWM2_MOD_8821C) & BIT_MASK_CPWM2_MOD_8821C)
-
-
-/* 2 REG_NOT_VALID_8821C */
+#define BIT_CPWM2_MOD_8821C(x) \
+ (((x) & BIT_MASK_CPWM2_MOD_8821C) << BIT_SHIFT_CPWM2_MOD_8821C)
+#define BITS_CPWM2_MOD_8821C \
+ (BIT_MASK_CPWM2_MOD_8821C << BIT_SHIFT_CPWM2_MOD_8821C)
+#define BIT_CLEAR_CPWM2_MOD_8821C(x) ((x) & (~BITS_CPWM2_MOD_8821C))
+#define BIT_GET_CPWM2_MOD_8821C(x) \
+ (((x) >> BIT_SHIFT_CPWM2_MOD_8821C) & BIT_MASK_CPWM2_MOD_8821C)
+#define BIT_SET_CPWM2_MOD_8821C(x, v) \
+ (BIT_CLEAR_CPWM2_MOD_8821C(x) | BIT_CPWM2_MOD_8821C(v))
/* 2 REG_TC0_CTRL_8821C */
#define BIT_TC0INT_EN_8821C BIT(26)
@@ -2279,9 +3652,14 @@
#define BIT_SHIFT_TC0DATA_8821C 0
#define BIT_MASK_TC0DATA_8821C 0xffffff
-#define BIT_TC0DATA_8821C(x) (((x) & BIT_MASK_TC0DATA_8821C) << BIT_SHIFT_TC0DATA_8821C)
-#define BIT_GET_TC0DATA_8821C(x) (((x) >> BIT_SHIFT_TC0DATA_8821C) & BIT_MASK_TC0DATA_8821C)
-
+#define BIT_TC0DATA_8821C(x) \
+ (((x) & BIT_MASK_TC0DATA_8821C) << BIT_SHIFT_TC0DATA_8821C)
+#define BITS_TC0DATA_8821C (BIT_MASK_TC0DATA_8821C << BIT_SHIFT_TC0DATA_8821C)
+#define BIT_CLEAR_TC0DATA_8821C(x) ((x) & (~BITS_TC0DATA_8821C))
+#define BIT_GET_TC0DATA_8821C(x) \
+ (((x) >> BIT_SHIFT_TC0DATA_8821C) & BIT_MASK_TC0DATA_8821C)
+#define BIT_SET_TC0DATA_8821C(x, v) \
+ (BIT_CLEAR_TC0DATA_8821C(x) | BIT_TC0DATA_8821C(v))
/* 2 REG_TC1_CTRL_8821C */
#define BIT_TC1INT_EN_8821C BIT(26)
@@ -2290,9 +3668,14 @@
#define BIT_SHIFT_TC1DATA_8821C 0
#define BIT_MASK_TC1DATA_8821C 0xffffff
-#define BIT_TC1DATA_8821C(x) (((x) & BIT_MASK_TC1DATA_8821C) << BIT_SHIFT_TC1DATA_8821C)
-#define BIT_GET_TC1DATA_8821C(x) (((x) >> BIT_SHIFT_TC1DATA_8821C) & BIT_MASK_TC1DATA_8821C)
-
+#define BIT_TC1DATA_8821C(x) \
+ (((x) & BIT_MASK_TC1DATA_8821C) << BIT_SHIFT_TC1DATA_8821C)
+#define BITS_TC1DATA_8821C (BIT_MASK_TC1DATA_8821C << BIT_SHIFT_TC1DATA_8821C)
+#define BIT_CLEAR_TC1DATA_8821C(x) ((x) & (~BITS_TC1DATA_8821C))
+#define BIT_GET_TC1DATA_8821C(x) \
+ (((x) >> BIT_SHIFT_TC1DATA_8821C) & BIT_MASK_TC1DATA_8821C)
+#define BIT_SET_TC1DATA_8821C(x, v) \
+ (BIT_CLEAR_TC1DATA_8821C(x) | BIT_TC1DATA_8821C(v))
/* 2 REG_TC2_CTRL_8821C */
#define BIT_TC2INT_EN_8821C BIT(26)
@@ -2301,9 +3684,14 @@
#define BIT_SHIFT_TC2DATA_8821C 0
#define BIT_MASK_TC2DATA_8821C 0xffffff
-#define BIT_TC2DATA_8821C(x) (((x) & BIT_MASK_TC2DATA_8821C) << BIT_SHIFT_TC2DATA_8821C)
-#define BIT_GET_TC2DATA_8821C(x) (((x) >> BIT_SHIFT_TC2DATA_8821C) & BIT_MASK_TC2DATA_8821C)
-
+#define BIT_TC2DATA_8821C(x) \
+ (((x) & BIT_MASK_TC2DATA_8821C) << BIT_SHIFT_TC2DATA_8821C)
+#define BITS_TC2DATA_8821C (BIT_MASK_TC2DATA_8821C << BIT_SHIFT_TC2DATA_8821C)
+#define BIT_CLEAR_TC2DATA_8821C(x) ((x) & (~BITS_TC2DATA_8821C))
+#define BIT_GET_TC2DATA_8821C(x) \
+ (((x) >> BIT_SHIFT_TC2DATA_8821C) & BIT_MASK_TC2DATA_8821C)
+#define BIT_SET_TC2DATA_8821C(x, v) \
+ (BIT_CLEAR_TC2DATA_8821C(x) | BIT_TC2DATA_8821C(v))
/* 2 REG_TC3_CTRL_8821C */
#define BIT_TC3INT_EN_8821C BIT(26)
@@ -2312,9 +3700,14 @@
#define BIT_SHIFT_TC3DATA_8821C 0
#define BIT_MASK_TC3DATA_8821C 0xffffff
-#define BIT_TC3DATA_8821C(x) (((x) & BIT_MASK_TC3DATA_8821C) << BIT_SHIFT_TC3DATA_8821C)
-#define BIT_GET_TC3DATA_8821C(x) (((x) >> BIT_SHIFT_TC3DATA_8821C) & BIT_MASK_TC3DATA_8821C)
-
+#define BIT_TC3DATA_8821C(x) \
+ (((x) & BIT_MASK_TC3DATA_8821C) << BIT_SHIFT_TC3DATA_8821C)
+#define BITS_TC3DATA_8821C (BIT_MASK_TC3DATA_8821C << BIT_SHIFT_TC3DATA_8821C)
+#define BIT_CLEAR_TC3DATA_8821C(x) ((x) & (~BITS_TC3DATA_8821C))
+#define BIT_GET_TC3DATA_8821C(x) \
+ (((x) >> BIT_SHIFT_TC3DATA_8821C) & BIT_MASK_TC3DATA_8821C)
+#define BIT_SET_TC3DATA_8821C(x, v) \
+ (BIT_CLEAR_TC3DATA_8821C(x) | BIT_TC3DATA_8821C(v))
/* 2 REG_TC4_CTRL_8821C */
#define BIT_TC4INT_EN_8821C BIT(26)
@@ -2323,17 +3716,28 @@
#define BIT_SHIFT_TC4DATA_8821C 0
#define BIT_MASK_TC4DATA_8821C 0xffffff
-#define BIT_TC4DATA_8821C(x) (((x) & BIT_MASK_TC4DATA_8821C) << BIT_SHIFT_TC4DATA_8821C)
-#define BIT_GET_TC4DATA_8821C(x) (((x) >> BIT_SHIFT_TC4DATA_8821C) & BIT_MASK_TC4DATA_8821C)
-
+#define BIT_TC4DATA_8821C(x) \
+ (((x) & BIT_MASK_TC4DATA_8821C) << BIT_SHIFT_TC4DATA_8821C)
+#define BITS_TC4DATA_8821C (BIT_MASK_TC4DATA_8821C << BIT_SHIFT_TC4DATA_8821C)
+#define BIT_CLEAR_TC4DATA_8821C(x) ((x) & (~BITS_TC4DATA_8821C))
+#define BIT_GET_TC4DATA_8821C(x) \
+ (((x) >> BIT_SHIFT_TC4DATA_8821C) & BIT_MASK_TC4DATA_8821C)
+#define BIT_SET_TC4DATA_8821C(x, v) \
+ (BIT_CLEAR_TC4DATA_8821C(x) | BIT_TC4DATA_8821C(v))
/* 2 REG_TCUNIT_BASE_8821C */
#define BIT_SHIFT_TCUNIT_BASE_8821C 0
#define BIT_MASK_TCUNIT_BASE_8821C 0x3fff
-#define BIT_TCUNIT_BASE_8821C(x) (((x) & BIT_MASK_TCUNIT_BASE_8821C) << BIT_SHIFT_TCUNIT_BASE_8821C)
-#define BIT_GET_TCUNIT_BASE_8821C(x) (((x) >> BIT_SHIFT_TCUNIT_BASE_8821C) & BIT_MASK_TCUNIT_BASE_8821C)
-
+#define BIT_TCUNIT_BASE_8821C(x) \
+ (((x) & BIT_MASK_TCUNIT_BASE_8821C) << BIT_SHIFT_TCUNIT_BASE_8821C)
+#define BITS_TCUNIT_BASE_8821C \
+ (BIT_MASK_TCUNIT_BASE_8821C << BIT_SHIFT_TCUNIT_BASE_8821C)
+#define BIT_CLEAR_TCUNIT_BASE_8821C(x) ((x) & (~BITS_TCUNIT_BASE_8821C))
+#define BIT_GET_TCUNIT_BASE_8821C(x) \
+ (((x) >> BIT_SHIFT_TCUNIT_BASE_8821C) & BIT_MASK_TCUNIT_BASE_8821C)
+#define BIT_SET_TCUNIT_BASE_8821C(x, v) \
+ (BIT_CLEAR_TCUNIT_BASE_8821C(x) | BIT_TCUNIT_BASE_8821C(v))
/* 2 REG_TC5_CTRL_8821C */
#define BIT_TC5INT_EN_8821C BIT(26)
@@ -2342,9 +3746,14 @@
#define BIT_SHIFT_TC5DATA_8821C 0
#define BIT_MASK_TC5DATA_8821C 0xffffff
-#define BIT_TC5DATA_8821C(x) (((x) & BIT_MASK_TC5DATA_8821C) << BIT_SHIFT_TC5DATA_8821C)
-#define BIT_GET_TC5DATA_8821C(x) (((x) >> BIT_SHIFT_TC5DATA_8821C) & BIT_MASK_TC5DATA_8821C)
-
+#define BIT_TC5DATA_8821C(x) \
+ (((x) & BIT_MASK_TC5DATA_8821C) << BIT_SHIFT_TC5DATA_8821C)
+#define BITS_TC5DATA_8821C (BIT_MASK_TC5DATA_8821C << BIT_SHIFT_TC5DATA_8821C)
+#define BIT_CLEAR_TC5DATA_8821C(x) ((x) & (~BITS_TC5DATA_8821C))
+#define BIT_GET_TC5DATA_8821C(x) \
+ (((x) >> BIT_SHIFT_TC5DATA_8821C) & BIT_MASK_TC5DATA_8821C)
+#define BIT_SET_TC5DATA_8821C(x, v) \
+ (BIT_CLEAR_TC5DATA_8821C(x) | BIT_TC5DATA_8821C(v))
/* 2 REG_TC6_CTRL_8821C */
#define BIT_TC6INT_EN_8821C BIT(26)
@@ -2353,111 +3762,267 @@
#define BIT_SHIFT_TC6DATA_8821C 0
#define BIT_MASK_TC6DATA_8821C 0xffffff
-#define BIT_TC6DATA_8821C(x) (((x) & BIT_MASK_TC6DATA_8821C) << BIT_SHIFT_TC6DATA_8821C)
-#define BIT_GET_TC6DATA_8821C(x) (((x) >> BIT_SHIFT_TC6DATA_8821C) & BIT_MASK_TC6DATA_8821C)
-
-
-/* 2 REG_MBIST_FAIL_8821C */
-
-#define BIT_SHIFT_8051_MBIST_FAIL_8821C 26
-#define BIT_MASK_8051_MBIST_FAIL_8821C 0x7
-#define BIT_8051_MBIST_FAIL_8821C(x) (((x) & BIT_MASK_8051_MBIST_FAIL_8821C) << BIT_SHIFT_8051_MBIST_FAIL_8821C)
-#define BIT_GET_8051_MBIST_FAIL_8821C(x) (((x) >> BIT_SHIFT_8051_MBIST_FAIL_8821C) & BIT_MASK_8051_MBIST_FAIL_8821C)
-
-
-#define BIT_SHIFT_USB_MBIST_FAIL_8821C 24
-#define BIT_MASK_USB_MBIST_FAIL_8821C 0x3
-#define BIT_USB_MBIST_FAIL_8821C(x) (((x) & BIT_MASK_USB_MBIST_FAIL_8821C) << BIT_SHIFT_USB_MBIST_FAIL_8821C)
-#define BIT_GET_USB_MBIST_FAIL_8821C(x) (((x) >> BIT_SHIFT_USB_MBIST_FAIL_8821C) & BIT_MASK_USB_MBIST_FAIL_8821C)
-
-
-#define BIT_SHIFT_PCIE_MBIST_FAIL_8821C 16
-#define BIT_MASK_PCIE_MBIST_FAIL_8821C 0x3f
-#define BIT_PCIE_MBIST_FAIL_8821C(x) (((x) & BIT_MASK_PCIE_MBIST_FAIL_8821C) << BIT_SHIFT_PCIE_MBIST_FAIL_8821C)
-#define BIT_GET_PCIE_MBIST_FAIL_8821C(x) (((x) >> BIT_SHIFT_PCIE_MBIST_FAIL_8821C) & BIT_MASK_PCIE_MBIST_FAIL_8821C)
-
-
-#define BIT_SHIFT_MAC_MBIST_FAIL_8821C 0
-#define BIT_MASK_MAC_MBIST_FAIL_8821C 0xfff
-#define BIT_MAC_MBIST_FAIL_8821C(x) (((x) & BIT_MASK_MAC_MBIST_FAIL_8821C) << BIT_SHIFT_MAC_MBIST_FAIL_8821C)
-#define BIT_GET_MAC_MBIST_FAIL_8821C(x) (((x) >> BIT_SHIFT_MAC_MBIST_FAIL_8821C) & BIT_MASK_MAC_MBIST_FAIL_8821C)
-
+#define BIT_TC6DATA_8821C(x) \
+ (((x) & BIT_MASK_TC6DATA_8821C) << BIT_SHIFT_TC6DATA_8821C)
+#define BITS_TC6DATA_8821C (BIT_MASK_TC6DATA_8821C << BIT_SHIFT_TC6DATA_8821C)
+#define BIT_CLEAR_TC6DATA_8821C(x) ((x) & (~BITS_TC6DATA_8821C))
+#define BIT_GET_TC6DATA_8821C(x) \
+ (((x) >> BIT_SHIFT_TC6DATA_8821C) & BIT_MASK_TC6DATA_8821C)
+#define BIT_SET_TC6DATA_8821C(x, v) \
+ (BIT_CLEAR_TC6DATA_8821C(x) | BIT_TC6DATA_8821C(v))
+
+/* 2 REG_MBIST_DRF_FAIL_8821C */
+
+#define BIT_SHIFT_8051_MBIST_DRF_FAIL_8821C 26
+#define BIT_MASK_8051_MBIST_DRF_FAIL_8821C 0x3f
+#define BIT_8051_MBIST_DRF_FAIL_8821C(x) \
+ (((x) & BIT_MASK_8051_MBIST_DRF_FAIL_8821C) \
+ << BIT_SHIFT_8051_MBIST_DRF_FAIL_8821C)
+#define BITS_8051_MBIST_DRF_FAIL_8821C \
+ (BIT_MASK_8051_MBIST_DRF_FAIL_8821C \
+ << BIT_SHIFT_8051_MBIST_DRF_FAIL_8821C)
+#define BIT_CLEAR_8051_MBIST_DRF_FAIL_8821C(x) \
+ ((x) & (~BITS_8051_MBIST_DRF_FAIL_8821C))
+#define BIT_GET_8051_MBIST_DRF_FAIL_8821C(x) \
+ (((x) >> BIT_SHIFT_8051_MBIST_DRF_FAIL_8821C) & \
+ BIT_MASK_8051_MBIST_DRF_FAIL_8821C)
+#define BIT_SET_8051_MBIST_DRF_FAIL_8821C(x, v) \
+ (BIT_CLEAR_8051_MBIST_DRF_FAIL_8821C(x) | \
+ BIT_8051_MBIST_DRF_FAIL_8821C(v))
+
+#define BIT_SHIFT_USB_MBIST_DRF_FAIL_8821C 24
+#define BIT_MASK_USB_MBIST_DRF_FAIL_8821C 0x3
+#define BIT_USB_MBIST_DRF_FAIL_8821C(x) \
+ (((x) & BIT_MASK_USB_MBIST_DRF_FAIL_8821C) \
+ << BIT_SHIFT_USB_MBIST_DRF_FAIL_8821C)
+#define BITS_USB_MBIST_DRF_FAIL_8821C \
+ (BIT_MASK_USB_MBIST_DRF_FAIL_8821C \
+ << BIT_SHIFT_USB_MBIST_DRF_FAIL_8821C)
+#define BIT_CLEAR_USB_MBIST_DRF_FAIL_8821C(x) \
+ ((x) & (~BITS_USB_MBIST_DRF_FAIL_8821C))
+#define BIT_GET_USB_MBIST_DRF_FAIL_8821C(x) \
+ (((x) >> BIT_SHIFT_USB_MBIST_DRF_FAIL_8821C) & \
+ BIT_MASK_USB_MBIST_DRF_FAIL_8821C)
+#define BIT_SET_USB_MBIST_DRF_FAIL_8821C(x, v) \
+ (BIT_CLEAR_USB_MBIST_DRF_FAIL_8821C(x) | \
+ BIT_USB_MBIST_DRF_FAIL_8821C(v))
+
+#define BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8821C 18
+#define BIT_MASK_PCIE_MBIST_DRF_FAIL_8821C 0x3f
+#define BIT_PCIE_MBIST_DRF_FAIL_8821C(x) \
+ (((x) & BIT_MASK_PCIE_MBIST_DRF_FAIL_8821C) \
+ << BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8821C)
+#define BITS_PCIE_MBIST_DRF_FAIL_8821C \
+ (BIT_MASK_PCIE_MBIST_DRF_FAIL_8821C \
+ << BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8821C)
+#define BIT_CLEAR_PCIE_MBIST_DRF_FAIL_8821C(x) \
+ ((x) & (~BITS_PCIE_MBIST_DRF_FAIL_8821C))
+#define BIT_GET_PCIE_MBIST_DRF_FAIL_8821C(x) \
+ (((x) >> BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8821C) & \
+ BIT_MASK_PCIE_MBIST_DRF_FAIL_8821C)
+#define BIT_SET_PCIE_MBIST_DRF_FAIL_8821C(x, v) \
+ (BIT_CLEAR_PCIE_MBIST_DRF_FAIL_8821C(x) | \
+ BIT_PCIE_MBIST_DRF_FAIL_8821C(v))
+
+#define BIT_SHIFT_MAC_MBIST_DRF_FAIL_8821C 0
+#define BIT_MASK_MAC_MBIST_DRF_FAIL_8821C 0x3ffff
+#define BIT_MAC_MBIST_DRF_FAIL_8821C(x) \
+ (((x) & BIT_MASK_MAC_MBIST_DRF_FAIL_8821C) \
+ << BIT_SHIFT_MAC_MBIST_DRF_FAIL_8821C)
+#define BITS_MAC_MBIST_DRF_FAIL_8821C \
+ (BIT_MASK_MAC_MBIST_DRF_FAIL_8821C \
+ << BIT_SHIFT_MAC_MBIST_DRF_FAIL_8821C)
+#define BIT_CLEAR_MAC_MBIST_DRF_FAIL_8821C(x) \
+ ((x) & (~BITS_MAC_MBIST_DRF_FAIL_8821C))
+#define BIT_GET_MAC_MBIST_DRF_FAIL_8821C(x) \
+ (((x) >> BIT_SHIFT_MAC_MBIST_DRF_FAIL_8821C) & \
+ BIT_MASK_MAC_MBIST_DRF_FAIL_8821C)
+#define BIT_SET_MAC_MBIST_DRF_FAIL_8821C(x, v) \
+ (BIT_CLEAR_MAC_MBIST_DRF_FAIL_8821C(x) | \
+ BIT_MAC_MBIST_DRF_FAIL_8821C(v))
/* 2 REG_MBIST_START_PAUSE_8821C */
-#define BIT_SHIFT_8051_MBIST_START_PAUSE_8821C 26
-#define BIT_MASK_8051_MBIST_START_PAUSE_8821C 0x7
-#define BIT_8051_MBIST_START_PAUSE_8821C(x) (((x) & BIT_MASK_8051_MBIST_START_PAUSE_8821C) << BIT_SHIFT_8051_MBIST_START_PAUSE_8821C)
-#define BIT_GET_8051_MBIST_START_PAUSE_8821C(x) (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_8821C) & BIT_MASK_8051_MBIST_START_PAUSE_8821C)
-
-
-#define BIT_SHIFT_USB_MBIST_START_PAUSE_8821C 24
-#define BIT_MASK_USB_MBIST_START_PAUSE_8821C 0x3
-#define BIT_USB_MBIST_START_PAUSE_8821C(x) (((x) & BIT_MASK_USB_MBIST_START_PAUSE_8821C) << BIT_SHIFT_USB_MBIST_START_PAUSE_8821C)
-#define BIT_GET_USB_MBIST_START_PAUSE_8821C(x) (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_8821C) & BIT_MASK_USB_MBIST_START_PAUSE_8821C)
-
-
-#define BIT_SHIFT_PCIE_MBIST_START_PAUSE_8821C 16
-#define BIT_MASK_PCIE_MBIST_START_PAUSE_8821C 0x3f
-#define BIT_PCIE_MBIST_START_PAUSE_8821C(x) (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_8821C) << BIT_SHIFT_PCIE_MBIST_START_PAUSE_8821C)
-#define BIT_GET_PCIE_MBIST_START_PAUSE_8821C(x) (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_8821C) & BIT_MASK_PCIE_MBIST_START_PAUSE_8821C)
-
-
-#define BIT_SHIFT_MAC_MBIST_START_PAUSE_8821C 0
-#define BIT_MASK_MAC_MBIST_START_PAUSE_8821C 0xfff
-#define BIT_MAC_MBIST_START_PAUSE_8821C(x) (((x) & BIT_MASK_MAC_MBIST_START_PAUSE_8821C) << BIT_SHIFT_MAC_MBIST_START_PAUSE_8821C)
-#define BIT_GET_MAC_MBIST_START_PAUSE_8821C(x) (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_8821C) & BIT_MASK_MAC_MBIST_START_PAUSE_8821C)
-
+#define BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8821C 26
+#define BIT_MASK_8051_MBIST_START_PAUSE_V1_8821C 0x3f
+#define BIT_8051_MBIST_START_PAUSE_V1_8821C(x) \
+ (((x) & BIT_MASK_8051_MBIST_START_PAUSE_V1_8821C) \
+ << BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8821C)
+#define BITS_8051_MBIST_START_PAUSE_V1_8821C \
+ (BIT_MASK_8051_MBIST_START_PAUSE_V1_8821C \
+ << BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8821C)
+#define BIT_CLEAR_8051_MBIST_START_PAUSE_V1_8821C(x) \
+ ((x) & (~BITS_8051_MBIST_START_PAUSE_V1_8821C))
+#define BIT_GET_8051_MBIST_START_PAUSE_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8821C) & \
+ BIT_MASK_8051_MBIST_START_PAUSE_V1_8821C)
+#define BIT_SET_8051_MBIST_START_PAUSE_V1_8821C(x, v) \
+ (BIT_CLEAR_8051_MBIST_START_PAUSE_V1_8821C(x) | \
+ BIT_8051_MBIST_START_PAUSE_V1_8821C(v))
+
+#define BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8821C 24
+#define BIT_MASK_USB_MBIST_START_PAUSE_V1_8821C 0x3
+#define BIT_USB_MBIST_START_PAUSE_V1_8821C(x) \
+ (((x) & BIT_MASK_USB_MBIST_START_PAUSE_V1_8821C) \
+ << BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8821C)
+#define BITS_USB_MBIST_START_PAUSE_V1_8821C \
+ (BIT_MASK_USB_MBIST_START_PAUSE_V1_8821C \
+ << BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8821C)
+#define BIT_CLEAR_USB_MBIST_START_PAUSE_V1_8821C(x) \
+ ((x) & (~BITS_USB_MBIST_START_PAUSE_V1_8821C))
+#define BIT_GET_USB_MBIST_START_PAUSE_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8821C) & \
+ BIT_MASK_USB_MBIST_START_PAUSE_V1_8821C)
+#define BIT_SET_USB_MBIST_START_PAUSE_V1_8821C(x, v) \
+ (BIT_CLEAR_USB_MBIST_START_PAUSE_V1_8821C(x) | \
+ BIT_USB_MBIST_START_PAUSE_V1_8821C(v))
+
+#define BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8821C 18
+#define BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8821C 0x3f
+#define BIT_PCIE_MBIST_START_PAUSE_V1_8821C(x) \
+ (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8821C) \
+ << BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8821C)
+#define BITS_PCIE_MBIST_START_PAUSE_V1_8821C \
+ (BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8821C \
+ << BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8821C)
+#define BIT_CLEAR_PCIE_MBIST_START_PAUSE_V1_8821C(x) \
+ ((x) & (~BITS_PCIE_MBIST_START_PAUSE_V1_8821C))
+#define BIT_GET_PCIE_MBIST_START_PAUSE_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8821C) & \
+ BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8821C)
+#define BIT_SET_PCIE_MBIST_START_PAUSE_V1_8821C(x, v) \
+ (BIT_CLEAR_PCIE_MBIST_START_PAUSE_V1_8821C(x) | \
+ BIT_PCIE_MBIST_START_PAUSE_V1_8821C(v))
+
+#define BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8821C 0
+#define BIT_MASK_MAC_MBIST_START_PAUSE_V1_8821C 0x3ffff
+#define BIT_MAC_MBIST_START_PAUSE_V1_8821C(x) \
+ (((x) & BIT_MASK_MAC_MBIST_START_PAUSE_V1_8821C) \
+ << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8821C)
+#define BITS_MAC_MBIST_START_PAUSE_V1_8821C \
+ (BIT_MASK_MAC_MBIST_START_PAUSE_V1_8821C \
+ << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8821C)
+#define BIT_CLEAR_MAC_MBIST_START_PAUSE_V1_8821C(x) \
+ ((x) & (~BITS_MAC_MBIST_START_PAUSE_V1_8821C))
+#define BIT_GET_MAC_MBIST_START_PAUSE_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8821C) & \
+ BIT_MASK_MAC_MBIST_START_PAUSE_V1_8821C)
+#define BIT_SET_MAC_MBIST_START_PAUSE_V1_8821C(x, v) \
+ (BIT_CLEAR_MAC_MBIST_START_PAUSE_V1_8821C(x) | \
+ BIT_MAC_MBIST_START_PAUSE_V1_8821C(v))
/* 2 REG_MBIST_DONE_8821C */
-#define BIT_SHIFT_8051_MBIST_DONE_8821C 26
-#define BIT_MASK_8051_MBIST_DONE_8821C 0x7
-#define BIT_8051_MBIST_DONE_8821C(x) (((x) & BIT_MASK_8051_MBIST_DONE_8821C) << BIT_SHIFT_8051_MBIST_DONE_8821C)
-#define BIT_GET_8051_MBIST_DONE_8821C(x) (((x) >> BIT_SHIFT_8051_MBIST_DONE_8821C) & BIT_MASK_8051_MBIST_DONE_8821C)
-
-
-#define BIT_SHIFT_USB_MBIST_DONE_8821C 24
-#define BIT_MASK_USB_MBIST_DONE_8821C 0x3
-#define BIT_USB_MBIST_DONE_8821C(x) (((x) & BIT_MASK_USB_MBIST_DONE_8821C) << BIT_SHIFT_USB_MBIST_DONE_8821C)
-#define BIT_GET_USB_MBIST_DONE_8821C(x) (((x) >> BIT_SHIFT_USB_MBIST_DONE_8821C) & BIT_MASK_USB_MBIST_DONE_8821C)
-
-
-#define BIT_SHIFT_PCIE_MBIST_DONE_8821C 16
-#define BIT_MASK_PCIE_MBIST_DONE_8821C 0x3f
-#define BIT_PCIE_MBIST_DONE_8821C(x) (((x) & BIT_MASK_PCIE_MBIST_DONE_8821C) << BIT_SHIFT_PCIE_MBIST_DONE_8821C)
-#define BIT_GET_PCIE_MBIST_DONE_8821C(x) (((x) >> BIT_SHIFT_PCIE_MBIST_DONE_8821C) & BIT_MASK_PCIE_MBIST_DONE_8821C)
-
-
-#define BIT_SHIFT_MAC_MBIST_DONE_8821C 0
-#define BIT_MASK_MAC_MBIST_DONE_8821C 0xfff
-#define BIT_MAC_MBIST_DONE_8821C(x) (((x) & BIT_MASK_MAC_MBIST_DONE_8821C) << BIT_SHIFT_MAC_MBIST_DONE_8821C)
-#define BIT_GET_MAC_MBIST_DONE_8821C(x) (((x) >> BIT_SHIFT_MAC_MBIST_DONE_8821C) & BIT_MASK_MAC_MBIST_DONE_8821C)
-
-
-/* 2 REG_MBIST_FAIL_NRML_8821C */
-
-#define BIT_SHIFT_MBIST_FAIL_NRML_8821C 0
-#define BIT_MASK_MBIST_FAIL_NRML_8821C 0xffffffffL
-#define BIT_MBIST_FAIL_NRML_8821C(x) (((x) & BIT_MASK_MBIST_FAIL_NRML_8821C) << BIT_SHIFT_MBIST_FAIL_NRML_8821C)
-#define BIT_GET_MBIST_FAIL_NRML_8821C(x) (((x) >> BIT_SHIFT_MBIST_FAIL_NRML_8821C) & BIT_MASK_MBIST_FAIL_NRML_8821C)
-
+#define BIT_SHIFT_8051_MBIST_DONE_V1_8821C 26
+#define BIT_MASK_8051_MBIST_DONE_V1_8821C 0x3f
+#define BIT_8051_MBIST_DONE_V1_8821C(x) \
+ (((x) & BIT_MASK_8051_MBIST_DONE_V1_8821C) \
+ << BIT_SHIFT_8051_MBIST_DONE_V1_8821C)
+#define BITS_8051_MBIST_DONE_V1_8821C \
+ (BIT_MASK_8051_MBIST_DONE_V1_8821C \
+ << BIT_SHIFT_8051_MBIST_DONE_V1_8821C)
+#define BIT_CLEAR_8051_MBIST_DONE_V1_8821C(x) \
+ ((x) & (~BITS_8051_MBIST_DONE_V1_8821C))
+#define BIT_GET_8051_MBIST_DONE_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_8051_MBIST_DONE_V1_8821C) & \
+ BIT_MASK_8051_MBIST_DONE_V1_8821C)
+#define BIT_SET_8051_MBIST_DONE_V1_8821C(x, v) \
+ (BIT_CLEAR_8051_MBIST_DONE_V1_8821C(x) | \
+ BIT_8051_MBIST_DONE_V1_8821C(v))
+
+#define BIT_SHIFT_USB_MBIST_DONE_V1_8821C 24
+#define BIT_MASK_USB_MBIST_DONE_V1_8821C 0x3
+#define BIT_USB_MBIST_DONE_V1_8821C(x) \
+ (((x) & BIT_MASK_USB_MBIST_DONE_V1_8821C) \
+ << BIT_SHIFT_USB_MBIST_DONE_V1_8821C)
+#define BITS_USB_MBIST_DONE_V1_8821C \
+ (BIT_MASK_USB_MBIST_DONE_V1_8821C << BIT_SHIFT_USB_MBIST_DONE_V1_8821C)
+#define BIT_CLEAR_USB_MBIST_DONE_V1_8821C(x) \
+ ((x) & (~BITS_USB_MBIST_DONE_V1_8821C))
+#define BIT_GET_USB_MBIST_DONE_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_USB_MBIST_DONE_V1_8821C) & \
+ BIT_MASK_USB_MBIST_DONE_V1_8821C)
+#define BIT_SET_USB_MBIST_DONE_V1_8821C(x, v) \
+ (BIT_CLEAR_USB_MBIST_DONE_V1_8821C(x) | BIT_USB_MBIST_DONE_V1_8821C(v))
+
+#define BIT_SHIFT_PCIE_MBIST_DONE_V1_8821C 18
+#define BIT_MASK_PCIE_MBIST_DONE_V1_8821C 0x3f
+#define BIT_PCIE_MBIST_DONE_V1_8821C(x) \
+ (((x) & BIT_MASK_PCIE_MBIST_DONE_V1_8821C) \
+ << BIT_SHIFT_PCIE_MBIST_DONE_V1_8821C)
+#define BITS_PCIE_MBIST_DONE_V1_8821C \
+ (BIT_MASK_PCIE_MBIST_DONE_V1_8821C \
+ << BIT_SHIFT_PCIE_MBIST_DONE_V1_8821C)
+#define BIT_CLEAR_PCIE_MBIST_DONE_V1_8821C(x) \
+ ((x) & (~BITS_PCIE_MBIST_DONE_V1_8821C))
+#define BIT_GET_PCIE_MBIST_DONE_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_PCIE_MBIST_DONE_V1_8821C) & \
+ BIT_MASK_PCIE_MBIST_DONE_V1_8821C)
+#define BIT_SET_PCIE_MBIST_DONE_V1_8821C(x, v) \
+ (BIT_CLEAR_PCIE_MBIST_DONE_V1_8821C(x) | \
+ BIT_PCIE_MBIST_DONE_V1_8821C(v))
+
+#define BIT_SHIFT_MAC_MBIST_DONE_V1_8821C 0
+#define BIT_MASK_MAC_MBIST_DONE_V1_8821C 0x3ffff
+#define BIT_MAC_MBIST_DONE_V1_8821C(x) \
+ (((x) & BIT_MASK_MAC_MBIST_DONE_V1_8821C) \
+ << BIT_SHIFT_MAC_MBIST_DONE_V1_8821C)
+#define BITS_MAC_MBIST_DONE_V1_8821C \
+ (BIT_MASK_MAC_MBIST_DONE_V1_8821C << BIT_SHIFT_MAC_MBIST_DONE_V1_8821C)
+#define BIT_CLEAR_MAC_MBIST_DONE_V1_8821C(x) \
+ ((x) & (~BITS_MAC_MBIST_DONE_V1_8821C))
+#define BIT_GET_MAC_MBIST_DONE_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_MAC_MBIST_DONE_V1_8821C) & \
+ BIT_MASK_MAC_MBIST_DONE_V1_8821C)
+#define BIT_SET_MAC_MBIST_DONE_V1_8821C(x, v) \
+ (BIT_CLEAR_MAC_MBIST_DONE_V1_8821C(x) | BIT_MAC_MBIST_DONE_V1_8821C(v))
+
+/* 2 REG_MBIST_READ_BIST_RPT_8821C */
+
+#define BIT_SHIFT_MBIST_READ_BIST_RPT_8821C 0
+#define BIT_MASK_MBIST_READ_BIST_RPT_8821C 0xffffffffL
+#define BIT_MBIST_READ_BIST_RPT_8821C(x) \
+ (((x) & BIT_MASK_MBIST_READ_BIST_RPT_8821C) \
+ << BIT_SHIFT_MBIST_READ_BIST_RPT_8821C)
+#define BITS_MBIST_READ_BIST_RPT_8821C \
+ (BIT_MASK_MBIST_READ_BIST_RPT_8821C \
+ << BIT_SHIFT_MBIST_READ_BIST_RPT_8821C)
+#define BIT_CLEAR_MBIST_READ_BIST_RPT_8821C(x) \
+ ((x) & (~BITS_MBIST_READ_BIST_RPT_8821C))
+#define BIT_GET_MBIST_READ_BIST_RPT_8821C(x) \
+ (((x) >> BIT_SHIFT_MBIST_READ_BIST_RPT_8821C) & \
+ BIT_MASK_MBIST_READ_BIST_RPT_8821C)
+#define BIT_SET_MBIST_READ_BIST_RPT_8821C(x, v) \
+ (BIT_CLEAR_MBIST_READ_BIST_RPT_8821C(x) | \
+ BIT_MBIST_READ_BIST_RPT_8821C(v))
/* 2 REG_AES_DECRPT_DATA_8821C */
#define BIT_SHIFT_IPS_CFG_ADDR_8821C 0
#define BIT_MASK_IPS_CFG_ADDR_8821C 0xff
-#define BIT_IPS_CFG_ADDR_8821C(x) (((x) & BIT_MASK_IPS_CFG_ADDR_8821C) << BIT_SHIFT_IPS_CFG_ADDR_8821C)
-#define BIT_GET_IPS_CFG_ADDR_8821C(x) (((x) >> BIT_SHIFT_IPS_CFG_ADDR_8821C) & BIT_MASK_IPS_CFG_ADDR_8821C)
-
+#define BIT_IPS_CFG_ADDR_8821C(x) \
+ (((x) & BIT_MASK_IPS_CFG_ADDR_8821C) << BIT_SHIFT_IPS_CFG_ADDR_8821C)
+#define BITS_IPS_CFG_ADDR_8821C \
+ (BIT_MASK_IPS_CFG_ADDR_8821C << BIT_SHIFT_IPS_CFG_ADDR_8821C)
+#define BIT_CLEAR_IPS_CFG_ADDR_8821C(x) ((x) & (~BITS_IPS_CFG_ADDR_8821C))
+#define BIT_GET_IPS_CFG_ADDR_8821C(x) \
+ (((x) >> BIT_SHIFT_IPS_CFG_ADDR_8821C) & BIT_MASK_IPS_CFG_ADDR_8821C)
+#define BIT_SET_IPS_CFG_ADDR_8821C(x, v) \
+ (BIT_CLEAR_IPS_CFG_ADDR_8821C(x) | BIT_IPS_CFG_ADDR_8821C(v))
/* 2 REG_AES_DECRPT_CFG_8821C */
#define BIT_SHIFT_IPS_CFG_DATA_8821C 0
#define BIT_MASK_IPS_CFG_DATA_8821C 0xffffffffL
-#define BIT_IPS_CFG_DATA_8821C(x) (((x) & BIT_MASK_IPS_CFG_DATA_8821C) << BIT_SHIFT_IPS_CFG_DATA_8821C)
-#define BIT_GET_IPS_CFG_DATA_8821C(x) (((x) >> BIT_SHIFT_IPS_CFG_DATA_8821C) & BIT_MASK_IPS_CFG_DATA_8821C)
-
+#define BIT_IPS_CFG_DATA_8821C(x) \
+ (((x) & BIT_MASK_IPS_CFG_DATA_8821C) << BIT_SHIFT_IPS_CFG_DATA_8821C)
+#define BITS_IPS_CFG_DATA_8821C \
+ (BIT_MASK_IPS_CFG_DATA_8821C << BIT_SHIFT_IPS_CFG_DATA_8821C)
+#define BIT_CLEAR_IPS_CFG_DATA_8821C(x) ((x) & (~BITS_IPS_CFG_DATA_8821C))
+#define BIT_GET_IPS_CFG_DATA_8821C(x) \
+ (((x) >> BIT_SHIFT_IPS_CFG_DATA_8821C) & BIT_MASK_IPS_CFG_DATA_8821C)
+#define BIT_SET_IPS_CFG_DATA_8821C(x, v) \
+ (BIT_CLEAR_IPS_CFG_DATA_8821C(x) | BIT_IPS_CFG_DATA_8821C(v))
/* 2 REG_NOT_VALID_8821C */
@@ -2468,20 +4033,44 @@
#define BIT_SHIFT_TEMP_VALUE_8821C 24
#define BIT_MASK_TEMP_VALUE_8821C 0x3f
-#define BIT_TEMP_VALUE_8821C(x) (((x) & BIT_MASK_TEMP_VALUE_8821C) << BIT_SHIFT_TEMP_VALUE_8821C)
-#define BIT_GET_TEMP_VALUE_8821C(x) (((x) >> BIT_SHIFT_TEMP_VALUE_8821C) & BIT_MASK_TEMP_VALUE_8821C)
-
+#define BIT_TEMP_VALUE_8821C(x) \
+ (((x) & BIT_MASK_TEMP_VALUE_8821C) << BIT_SHIFT_TEMP_VALUE_8821C)
+#define BITS_TEMP_VALUE_8821C \
+ (BIT_MASK_TEMP_VALUE_8821C << BIT_SHIFT_TEMP_VALUE_8821C)
+#define BIT_CLEAR_TEMP_VALUE_8821C(x) ((x) & (~BITS_TEMP_VALUE_8821C))
+#define BIT_GET_TEMP_VALUE_8821C(x) \
+ (((x) >> BIT_SHIFT_TEMP_VALUE_8821C) & BIT_MASK_TEMP_VALUE_8821C)
+#define BIT_SET_TEMP_VALUE_8821C(x, v) \
+ (BIT_CLEAR_TEMP_VALUE_8821C(x) | BIT_TEMP_VALUE_8821C(v))
#define BIT_SHIFT_REG_TMETER_TIMER_8821C 8
#define BIT_MASK_REG_TMETER_TIMER_8821C 0xfff
-#define BIT_REG_TMETER_TIMER_8821C(x) (((x) & BIT_MASK_REG_TMETER_TIMER_8821C) << BIT_SHIFT_REG_TMETER_TIMER_8821C)
-#define BIT_GET_REG_TMETER_TIMER_8821C(x) (((x) >> BIT_SHIFT_REG_TMETER_TIMER_8821C) & BIT_MASK_REG_TMETER_TIMER_8821C)
-
+#define BIT_REG_TMETER_TIMER_8821C(x) \
+ (((x) & BIT_MASK_REG_TMETER_TIMER_8821C) \
+ << BIT_SHIFT_REG_TMETER_TIMER_8821C)
+#define BITS_REG_TMETER_TIMER_8821C \
+ (BIT_MASK_REG_TMETER_TIMER_8821C << BIT_SHIFT_REG_TMETER_TIMER_8821C)
+#define BIT_CLEAR_REG_TMETER_TIMER_8821C(x) \
+ ((x) & (~BITS_REG_TMETER_TIMER_8821C))
+#define BIT_GET_REG_TMETER_TIMER_8821C(x) \
+ (((x) >> BIT_SHIFT_REG_TMETER_TIMER_8821C) & \
+ BIT_MASK_REG_TMETER_TIMER_8821C)
+#define BIT_SET_REG_TMETER_TIMER_8821C(x, v) \
+ (BIT_CLEAR_REG_TMETER_TIMER_8821C(x) | BIT_REG_TMETER_TIMER_8821C(v))
#define BIT_SHIFT_REG_TEMP_DELTA_8821C 2
#define BIT_MASK_REG_TEMP_DELTA_8821C 0x3f
-#define BIT_REG_TEMP_DELTA_8821C(x) (((x) & BIT_MASK_REG_TEMP_DELTA_8821C) << BIT_SHIFT_REG_TEMP_DELTA_8821C)
-#define BIT_GET_REG_TEMP_DELTA_8821C(x) (((x) >> BIT_SHIFT_REG_TEMP_DELTA_8821C) & BIT_MASK_REG_TEMP_DELTA_8821C)
+#define BIT_REG_TEMP_DELTA_8821C(x) \
+ (((x) & BIT_MASK_REG_TEMP_DELTA_8821C) \
+ << BIT_SHIFT_REG_TEMP_DELTA_8821C)
+#define BITS_REG_TEMP_DELTA_8821C \
+ (BIT_MASK_REG_TEMP_DELTA_8821C << BIT_SHIFT_REG_TEMP_DELTA_8821C)
+#define BIT_CLEAR_REG_TEMP_DELTA_8821C(x) ((x) & (~BITS_REG_TEMP_DELTA_8821C))
+#define BIT_GET_REG_TEMP_DELTA_8821C(x) \
+ (((x) >> BIT_SHIFT_REG_TEMP_DELTA_8821C) & \
+ BIT_MASK_REG_TEMP_DELTA_8821C)
+#define BIT_SET_REG_TEMP_DELTA_8821C(x, v) \
+ (BIT_CLEAR_REG_TEMP_DELTA_8821C(x) | BIT_REG_TEMP_DELTA_8821C(v))
#define BIT_REG_TMETER_EN_8821C BIT(0)
@@ -2489,14 +4078,33 @@
#define BIT_SHIFT_OSC_32K_CLKGEN_0_8821C 16
#define BIT_MASK_OSC_32K_CLKGEN_0_8821C 0xffff
-#define BIT_OSC_32K_CLKGEN_0_8821C(x) (((x) & BIT_MASK_OSC_32K_CLKGEN_0_8821C) << BIT_SHIFT_OSC_32K_CLKGEN_0_8821C)
-#define BIT_GET_OSC_32K_CLKGEN_0_8821C(x) (((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0_8821C) & BIT_MASK_OSC_32K_CLKGEN_0_8821C)
-
+#define BIT_OSC_32K_CLKGEN_0_8821C(x) \
+ (((x) & BIT_MASK_OSC_32K_CLKGEN_0_8821C) \
+ << BIT_SHIFT_OSC_32K_CLKGEN_0_8821C)
+#define BITS_OSC_32K_CLKGEN_0_8821C \
+ (BIT_MASK_OSC_32K_CLKGEN_0_8821C << BIT_SHIFT_OSC_32K_CLKGEN_0_8821C)
+#define BIT_CLEAR_OSC_32K_CLKGEN_0_8821C(x) \
+ ((x) & (~BITS_OSC_32K_CLKGEN_0_8821C))
+#define BIT_GET_OSC_32K_CLKGEN_0_8821C(x) \
+ (((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0_8821C) & \
+ BIT_MASK_OSC_32K_CLKGEN_0_8821C)
+#define BIT_SET_OSC_32K_CLKGEN_0_8821C(x, v) \
+ (BIT_CLEAR_OSC_32K_CLKGEN_0_8821C(x) | BIT_OSC_32K_CLKGEN_0_8821C(v))
#define BIT_SHIFT_OSC_32K_RES_COMP_8821C 4
#define BIT_MASK_OSC_32K_RES_COMP_8821C 0x3
-#define BIT_OSC_32K_RES_COMP_8821C(x) (((x) & BIT_MASK_OSC_32K_RES_COMP_8821C) << BIT_SHIFT_OSC_32K_RES_COMP_8821C)
-#define BIT_GET_OSC_32K_RES_COMP_8821C(x) (((x) >> BIT_SHIFT_OSC_32K_RES_COMP_8821C) & BIT_MASK_OSC_32K_RES_COMP_8821C)
+#define BIT_OSC_32K_RES_COMP_8821C(x) \
+ (((x) & BIT_MASK_OSC_32K_RES_COMP_8821C) \
+ << BIT_SHIFT_OSC_32K_RES_COMP_8821C)
+#define BITS_OSC_32K_RES_COMP_8821C \
+ (BIT_MASK_OSC_32K_RES_COMP_8821C << BIT_SHIFT_OSC_32K_RES_COMP_8821C)
+#define BIT_CLEAR_OSC_32K_RES_COMP_8821C(x) \
+ ((x) & (~BITS_OSC_32K_RES_COMP_8821C))
+#define BIT_GET_OSC_32K_RES_COMP_8821C(x) \
+ (((x) >> BIT_SHIFT_OSC_32K_RES_COMP_8821C) & \
+ BIT_MASK_OSC_32K_RES_COMP_8821C)
+#define BIT_SET_OSC_32K_RES_COMP_8821C(x, v) \
+ (BIT_CLEAR_OSC_32K_RES_COMP_8821C(x) | BIT_OSC_32K_RES_COMP_8821C(v))
#define BIT_OSC_32K_OUT_SEL_8821C BIT(3)
#define BIT_ISO_WL_2_OSC_32K_8821C BIT(1)
@@ -2508,65 +4116,187 @@
#define BIT_SHIFT_CAL_32K_REG_ADDR_8821C 16
#define BIT_MASK_CAL_32K_REG_ADDR_8821C 0x3f
-#define BIT_CAL_32K_REG_ADDR_8821C(x) (((x) & BIT_MASK_CAL_32K_REG_ADDR_8821C) << BIT_SHIFT_CAL_32K_REG_ADDR_8821C)
-#define BIT_GET_CAL_32K_REG_ADDR_8821C(x) (((x) >> BIT_SHIFT_CAL_32K_REG_ADDR_8821C) & BIT_MASK_CAL_32K_REG_ADDR_8821C)
-
+#define BIT_CAL_32K_REG_ADDR_8821C(x) \
+ (((x) & BIT_MASK_CAL_32K_REG_ADDR_8821C) \
+ << BIT_SHIFT_CAL_32K_REG_ADDR_8821C)
+#define BITS_CAL_32K_REG_ADDR_8821C \
+ (BIT_MASK_CAL_32K_REG_ADDR_8821C << BIT_SHIFT_CAL_32K_REG_ADDR_8821C)
+#define BIT_CLEAR_CAL_32K_REG_ADDR_8821C(x) \
+ ((x) & (~BITS_CAL_32K_REG_ADDR_8821C))
+#define BIT_GET_CAL_32K_REG_ADDR_8821C(x) \
+ (((x) >> BIT_SHIFT_CAL_32K_REG_ADDR_8821C) & \
+ BIT_MASK_CAL_32K_REG_ADDR_8821C)
+#define BIT_SET_CAL_32K_REG_ADDR_8821C(x, v) \
+ (BIT_CLEAR_CAL_32K_REG_ADDR_8821C(x) | BIT_CAL_32K_REG_ADDR_8821C(v))
#define BIT_SHIFT_CAL_32K_REG_DATA_8821C 0
#define BIT_MASK_CAL_32K_REG_DATA_8821C 0xffff
-#define BIT_CAL_32K_REG_DATA_8821C(x) (((x) & BIT_MASK_CAL_32K_REG_DATA_8821C) << BIT_SHIFT_CAL_32K_REG_DATA_8821C)
-#define BIT_GET_CAL_32K_REG_DATA_8821C(x) (((x) >> BIT_SHIFT_CAL_32K_REG_DATA_8821C) & BIT_MASK_CAL_32K_REG_DATA_8821C)
-
+#define BIT_CAL_32K_REG_DATA_8821C(x) \
+ (((x) & BIT_MASK_CAL_32K_REG_DATA_8821C) \
+ << BIT_SHIFT_CAL_32K_REG_DATA_8821C)
+#define BITS_CAL_32K_REG_DATA_8821C \
+ (BIT_MASK_CAL_32K_REG_DATA_8821C << BIT_SHIFT_CAL_32K_REG_DATA_8821C)
+#define BIT_CLEAR_CAL_32K_REG_DATA_8821C(x) \
+ ((x) & (~BITS_CAL_32K_REG_DATA_8821C))
+#define BIT_GET_CAL_32K_REG_DATA_8821C(x) \
+ (((x) >> BIT_SHIFT_CAL_32K_REG_DATA_8821C) & \
+ BIT_MASK_CAL_32K_REG_DATA_8821C)
+#define BIT_SET_CAL_32K_REG_DATA_8821C(x, v) \
+ (BIT_CLEAR_CAL_32K_REG_DATA_8821C(x) | BIT_CAL_32K_REG_DATA_8821C(v))
/* 2 REG_NOT_VALID_8821C */
/* 2 REG_C2HEVT_8821C */
-#define BIT_SHIFT_C2HEVT_MSG_8821C 0
-#define BIT_MASK_C2HEVT_MSG_8821C 0xffffffffffffffffffffffffffffffffL
-#define BIT_C2HEVT_MSG_8821C(x) (((x) & BIT_MASK_C2HEVT_MSG_8821C) << BIT_SHIFT_C2HEVT_MSG_8821C)
-#define BIT_GET_C2HEVT_MSG_8821C(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_8821C) & BIT_MASK_C2HEVT_MSG_8821C)
+#define BIT_SHIFT_C2HEVT_MSG_V1_8821C 0
+#define BIT_MASK_C2HEVT_MSG_V1_8821C 0xffffffffL
+#define BIT_C2HEVT_MSG_V1_8821C(x) \
+ (((x) & BIT_MASK_C2HEVT_MSG_V1_8821C) << BIT_SHIFT_C2HEVT_MSG_V1_8821C)
+#define BITS_C2HEVT_MSG_V1_8821C \
+ (BIT_MASK_C2HEVT_MSG_V1_8821C << BIT_SHIFT_C2HEVT_MSG_V1_8821C)
+#define BIT_CLEAR_C2HEVT_MSG_V1_8821C(x) ((x) & (~BITS_C2HEVT_MSG_V1_8821C))
+#define BIT_GET_C2HEVT_MSG_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_C2HEVT_MSG_V1_8821C) & BIT_MASK_C2HEVT_MSG_V1_8821C)
+#define BIT_SET_C2HEVT_MSG_V1_8821C(x, v) \
+ (BIT_CLEAR_C2HEVT_MSG_V1_8821C(x) | BIT_C2HEVT_MSG_V1_8821C(v))
+
+/* 2 REG_C2HEVT_1_8821C */
+
+#define BIT_SHIFT_C2HEVT_MSG_1_8821C 0
+#define BIT_MASK_C2HEVT_MSG_1_8821C 0xffffffffL
+#define BIT_C2HEVT_MSG_1_8821C(x) \
+ (((x) & BIT_MASK_C2HEVT_MSG_1_8821C) << BIT_SHIFT_C2HEVT_MSG_1_8821C)
+#define BITS_C2HEVT_MSG_1_8821C \
+ (BIT_MASK_C2HEVT_MSG_1_8821C << BIT_SHIFT_C2HEVT_MSG_1_8821C)
+#define BIT_CLEAR_C2HEVT_MSG_1_8821C(x) ((x) & (~BITS_C2HEVT_MSG_1_8821C))
+#define BIT_GET_C2HEVT_MSG_1_8821C(x) \
+ (((x) >> BIT_SHIFT_C2HEVT_MSG_1_8821C) & BIT_MASK_C2HEVT_MSG_1_8821C)
+#define BIT_SET_C2HEVT_MSG_1_8821C(x, v) \
+ (BIT_CLEAR_C2HEVT_MSG_1_8821C(x) | BIT_C2HEVT_MSG_1_8821C(v))
+
+/* 2 REG_C2HEVT_2_8821C */
+
+#define BIT_SHIFT_C2HEVT_MSG_2_8821C 0
+#define BIT_MASK_C2HEVT_MSG_2_8821C 0xffffffffL
+#define BIT_C2HEVT_MSG_2_8821C(x) \
+ (((x) & BIT_MASK_C2HEVT_MSG_2_8821C) << BIT_SHIFT_C2HEVT_MSG_2_8821C)
+#define BITS_C2HEVT_MSG_2_8821C \
+ (BIT_MASK_C2HEVT_MSG_2_8821C << BIT_SHIFT_C2HEVT_MSG_2_8821C)
+#define BIT_CLEAR_C2HEVT_MSG_2_8821C(x) ((x) & (~BITS_C2HEVT_MSG_2_8821C))
+#define BIT_GET_C2HEVT_MSG_2_8821C(x) \
+ (((x) >> BIT_SHIFT_C2HEVT_MSG_2_8821C) & BIT_MASK_C2HEVT_MSG_2_8821C)
+#define BIT_SET_C2HEVT_MSG_2_8821C(x, v) \
+ (BIT_CLEAR_C2HEVT_MSG_2_8821C(x) | BIT_C2HEVT_MSG_2_8821C(v))
+
+/* 2 REG_C2HEVT_3_8821C */
+
+#define BIT_SHIFT_C2HEVT_MSG_3_8821C 0
+#define BIT_MASK_C2HEVT_MSG_3_8821C 0xffffffffL
+#define BIT_C2HEVT_MSG_3_8821C(x) \
+ (((x) & BIT_MASK_C2HEVT_MSG_3_8821C) << BIT_SHIFT_C2HEVT_MSG_3_8821C)
+#define BITS_C2HEVT_MSG_3_8821C \
+ (BIT_MASK_C2HEVT_MSG_3_8821C << BIT_SHIFT_C2HEVT_MSG_3_8821C)
+#define BIT_CLEAR_C2HEVT_MSG_3_8821C(x) ((x) & (~BITS_C2HEVT_MSG_3_8821C))
+#define BIT_GET_C2HEVT_MSG_3_8821C(x) \
+ (((x) >> BIT_SHIFT_C2HEVT_MSG_3_8821C) & BIT_MASK_C2HEVT_MSG_3_8821C)
+#define BIT_SET_C2HEVT_MSG_3_8821C(x, v) \
+ (BIT_CLEAR_C2HEVT_MSG_3_8821C(x) | BIT_C2HEVT_MSG_3_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+/* 2 REG_NOT_VALID_8821C */
/* 2 REG_SW_DEFINED_PAGE1_8821C */
-#define BIT_SHIFT_SW_DEFINED_PAGE1_8821C 0
-#define BIT_MASK_SW_DEFINED_PAGE1_8821C 0xffffffffffffffffL
-#define BIT_SW_DEFINED_PAGE1_8821C(x) (((x) & BIT_MASK_SW_DEFINED_PAGE1_8821C) << BIT_SHIFT_SW_DEFINED_PAGE1_8821C)
-#define BIT_GET_SW_DEFINED_PAGE1_8821C(x) (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_8821C) & BIT_MASK_SW_DEFINED_PAGE1_8821C)
-
+#define BIT_SHIFT_SW_DEFINED_PAGE1_V1_8821C 0
+#define BIT_MASK_SW_DEFINED_PAGE1_V1_8821C 0xffffffffL
+#define BIT_SW_DEFINED_PAGE1_V1_8821C(x) \
+ (((x) & BIT_MASK_SW_DEFINED_PAGE1_V1_8821C) \
+ << BIT_SHIFT_SW_DEFINED_PAGE1_V1_8821C)
+#define BITS_SW_DEFINED_PAGE1_V1_8821C \
+ (BIT_MASK_SW_DEFINED_PAGE1_V1_8821C \
+ << BIT_SHIFT_SW_DEFINED_PAGE1_V1_8821C)
+#define BIT_CLEAR_SW_DEFINED_PAGE1_V1_8821C(x) \
+ ((x) & (~BITS_SW_DEFINED_PAGE1_V1_8821C))
+#define BIT_GET_SW_DEFINED_PAGE1_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_V1_8821C) & \
+ BIT_MASK_SW_DEFINED_PAGE1_V1_8821C)
+#define BIT_SET_SW_DEFINED_PAGE1_V1_8821C(x, v) \
+ (BIT_CLEAR_SW_DEFINED_PAGE1_V1_8821C(x) | \
+ BIT_SW_DEFINED_PAGE1_V1_8821C(v))
+
+/* 2 REG_SW_DEFINED_PAGE2_8821C */
+
+#define BIT_SHIFT_SW_DEFINED_PAGE2_8821C 0
+#define BIT_MASK_SW_DEFINED_PAGE2_8821C 0xffffffffL
+#define BIT_SW_DEFINED_PAGE2_8821C(x) \
+ (((x) & BIT_MASK_SW_DEFINED_PAGE2_8821C) \
+ << BIT_SHIFT_SW_DEFINED_PAGE2_8821C)
+#define BITS_SW_DEFINED_PAGE2_8821C \
+ (BIT_MASK_SW_DEFINED_PAGE2_8821C << BIT_SHIFT_SW_DEFINED_PAGE2_8821C)
+#define BIT_CLEAR_SW_DEFINED_PAGE2_8821C(x) \
+ ((x) & (~BITS_SW_DEFINED_PAGE2_8821C))
+#define BIT_GET_SW_DEFINED_PAGE2_8821C(x) \
+ (((x) >> BIT_SHIFT_SW_DEFINED_PAGE2_8821C) & \
+ BIT_MASK_SW_DEFINED_PAGE2_8821C)
+#define BIT_SET_SW_DEFINED_PAGE2_8821C(x, v) \
+ (BIT_CLEAR_SW_DEFINED_PAGE2_8821C(x) | BIT_SW_DEFINED_PAGE2_8821C(v))
/* 2 REG_MCUTST_I_8821C */
#define BIT_SHIFT_MCUDMSG_I_8821C 0
#define BIT_MASK_MCUDMSG_I_8821C 0xffffffffL
-#define BIT_MCUDMSG_I_8821C(x) (((x) & BIT_MASK_MCUDMSG_I_8821C) << BIT_SHIFT_MCUDMSG_I_8821C)
-#define BIT_GET_MCUDMSG_I_8821C(x) (((x) >> BIT_SHIFT_MCUDMSG_I_8821C) & BIT_MASK_MCUDMSG_I_8821C)
-
+#define BIT_MCUDMSG_I_8821C(x) \
+ (((x) & BIT_MASK_MCUDMSG_I_8821C) << BIT_SHIFT_MCUDMSG_I_8821C)
+#define BITS_MCUDMSG_I_8821C \
+ (BIT_MASK_MCUDMSG_I_8821C << BIT_SHIFT_MCUDMSG_I_8821C)
+#define BIT_CLEAR_MCUDMSG_I_8821C(x) ((x) & (~BITS_MCUDMSG_I_8821C))
+#define BIT_GET_MCUDMSG_I_8821C(x) \
+ (((x) >> BIT_SHIFT_MCUDMSG_I_8821C) & BIT_MASK_MCUDMSG_I_8821C)
+#define BIT_SET_MCUDMSG_I_8821C(x, v) \
+ (BIT_CLEAR_MCUDMSG_I_8821C(x) | BIT_MCUDMSG_I_8821C(v))
/* 2 REG_MCUTST_II_8821C */
#define BIT_SHIFT_MCUDMSG_II_8821C 0
#define BIT_MASK_MCUDMSG_II_8821C 0xffffffffL
-#define BIT_MCUDMSG_II_8821C(x) (((x) & BIT_MASK_MCUDMSG_II_8821C) << BIT_SHIFT_MCUDMSG_II_8821C)
-#define BIT_GET_MCUDMSG_II_8821C(x) (((x) >> BIT_SHIFT_MCUDMSG_II_8821C) & BIT_MASK_MCUDMSG_II_8821C)
-
+#define BIT_MCUDMSG_II_8821C(x) \
+ (((x) & BIT_MASK_MCUDMSG_II_8821C) << BIT_SHIFT_MCUDMSG_II_8821C)
+#define BITS_MCUDMSG_II_8821C \
+ (BIT_MASK_MCUDMSG_II_8821C << BIT_SHIFT_MCUDMSG_II_8821C)
+#define BIT_CLEAR_MCUDMSG_II_8821C(x) ((x) & (~BITS_MCUDMSG_II_8821C))
+#define BIT_GET_MCUDMSG_II_8821C(x) \
+ (((x) >> BIT_SHIFT_MCUDMSG_II_8821C) & BIT_MASK_MCUDMSG_II_8821C)
+#define BIT_SET_MCUDMSG_II_8821C(x, v) \
+ (BIT_CLEAR_MCUDMSG_II_8821C(x) | BIT_MCUDMSG_II_8821C(v))
/* 2 REG_FMETHR_8821C */
#define BIT_FMSG_INT_8821C BIT(31)
#define BIT_SHIFT_FW_MSG_8821C 0
#define BIT_MASK_FW_MSG_8821C 0xffffffffL
-#define BIT_FW_MSG_8821C(x) (((x) & BIT_MASK_FW_MSG_8821C) << BIT_SHIFT_FW_MSG_8821C)
-#define BIT_GET_FW_MSG_8821C(x) (((x) >> BIT_SHIFT_FW_MSG_8821C) & BIT_MASK_FW_MSG_8821C)
-
+#define BIT_FW_MSG_8821C(x) \
+ (((x) & BIT_MASK_FW_MSG_8821C) << BIT_SHIFT_FW_MSG_8821C)
+#define BITS_FW_MSG_8821C (BIT_MASK_FW_MSG_8821C << BIT_SHIFT_FW_MSG_8821C)
+#define BIT_CLEAR_FW_MSG_8821C(x) ((x) & (~BITS_FW_MSG_8821C))
+#define BIT_GET_FW_MSG_8821C(x) \
+ (((x) >> BIT_SHIFT_FW_MSG_8821C) & BIT_MASK_FW_MSG_8821C)
+#define BIT_SET_FW_MSG_8821C(x, v) \
+ (BIT_CLEAR_FW_MSG_8821C(x) | BIT_FW_MSG_8821C(v))
/* 2 REG_HMETFR_8821C */
#define BIT_SHIFT_HRCV_MSG_8821C 24
#define BIT_MASK_HRCV_MSG_8821C 0xff
-#define BIT_HRCV_MSG_8821C(x) (((x) & BIT_MASK_HRCV_MSG_8821C) << BIT_SHIFT_HRCV_MSG_8821C)
-#define BIT_GET_HRCV_MSG_8821C(x) (((x) >> BIT_SHIFT_HRCV_MSG_8821C) & BIT_MASK_HRCV_MSG_8821C)
+#define BIT_HRCV_MSG_8821C(x) \
+ (((x) & BIT_MASK_HRCV_MSG_8821C) << BIT_SHIFT_HRCV_MSG_8821C)
+#define BITS_HRCV_MSG_8821C \
+ (BIT_MASK_HRCV_MSG_8821C << BIT_SHIFT_HRCV_MSG_8821C)
+#define BIT_CLEAR_HRCV_MSG_8821C(x) ((x) & (~BITS_HRCV_MSG_8821C))
+#define BIT_GET_HRCV_MSG_8821C(x) \
+ (((x) >> BIT_SHIFT_HRCV_MSG_8821C) & BIT_MASK_HRCV_MSG_8821C)
+#define BIT_SET_HRCV_MSG_8821C(x, v) \
+ (BIT_CLEAR_HRCV_MSG_8821C(x) | BIT_HRCV_MSG_8821C(v))
#define BIT_INT_BOX3_8821C BIT(3)
#define BIT_INT_BOX2_8821C BIT(2)
@@ -2577,80 +4307,98 @@
#define BIT_SHIFT_HOST_MSG_0_8821C 0
#define BIT_MASK_HOST_MSG_0_8821C 0xffffffffL
-#define BIT_HOST_MSG_0_8821C(x) (((x) & BIT_MASK_HOST_MSG_0_8821C) << BIT_SHIFT_HOST_MSG_0_8821C)
-#define BIT_GET_HOST_MSG_0_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_0_8821C) & BIT_MASK_HOST_MSG_0_8821C)
-
+#define BIT_HOST_MSG_0_8821C(x) \
+ (((x) & BIT_MASK_HOST_MSG_0_8821C) << BIT_SHIFT_HOST_MSG_0_8821C)
+#define BITS_HOST_MSG_0_8821C \
+ (BIT_MASK_HOST_MSG_0_8821C << BIT_SHIFT_HOST_MSG_0_8821C)
+#define BIT_CLEAR_HOST_MSG_0_8821C(x) ((x) & (~BITS_HOST_MSG_0_8821C))
+#define BIT_GET_HOST_MSG_0_8821C(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_0_8821C) & BIT_MASK_HOST_MSG_0_8821C)
+#define BIT_SET_HOST_MSG_0_8821C(x, v) \
+ (BIT_CLEAR_HOST_MSG_0_8821C(x) | BIT_HOST_MSG_0_8821C(v))
/* 2 REG_HMEBOX1_8821C */
#define BIT_SHIFT_HOST_MSG_1_8821C 0
#define BIT_MASK_HOST_MSG_1_8821C 0xffffffffL
-#define BIT_HOST_MSG_1_8821C(x) (((x) & BIT_MASK_HOST_MSG_1_8821C) << BIT_SHIFT_HOST_MSG_1_8821C)
-#define BIT_GET_HOST_MSG_1_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_1_8821C) & BIT_MASK_HOST_MSG_1_8821C)
-
+#define BIT_HOST_MSG_1_8821C(x) \
+ (((x) & BIT_MASK_HOST_MSG_1_8821C) << BIT_SHIFT_HOST_MSG_1_8821C)
+#define BITS_HOST_MSG_1_8821C \
+ (BIT_MASK_HOST_MSG_1_8821C << BIT_SHIFT_HOST_MSG_1_8821C)
+#define BIT_CLEAR_HOST_MSG_1_8821C(x) ((x) & (~BITS_HOST_MSG_1_8821C))
+#define BIT_GET_HOST_MSG_1_8821C(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_1_8821C) & BIT_MASK_HOST_MSG_1_8821C)
+#define BIT_SET_HOST_MSG_1_8821C(x, v) \
+ (BIT_CLEAR_HOST_MSG_1_8821C(x) | BIT_HOST_MSG_1_8821C(v))
/* 2 REG_HMEBOX2_8821C */
#define BIT_SHIFT_HOST_MSG_2_8821C 0
#define BIT_MASK_HOST_MSG_2_8821C 0xffffffffL
-#define BIT_HOST_MSG_2_8821C(x) (((x) & BIT_MASK_HOST_MSG_2_8821C) << BIT_SHIFT_HOST_MSG_2_8821C)
-#define BIT_GET_HOST_MSG_2_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_2_8821C) & BIT_MASK_HOST_MSG_2_8821C)
-
+#define BIT_HOST_MSG_2_8821C(x) \
+ (((x) & BIT_MASK_HOST_MSG_2_8821C) << BIT_SHIFT_HOST_MSG_2_8821C)
+#define BITS_HOST_MSG_2_8821C \
+ (BIT_MASK_HOST_MSG_2_8821C << BIT_SHIFT_HOST_MSG_2_8821C)
+#define BIT_CLEAR_HOST_MSG_2_8821C(x) ((x) & (~BITS_HOST_MSG_2_8821C))
+#define BIT_GET_HOST_MSG_2_8821C(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_2_8821C) & BIT_MASK_HOST_MSG_2_8821C)
+#define BIT_SET_HOST_MSG_2_8821C(x, v) \
+ (BIT_CLEAR_HOST_MSG_2_8821C(x) | BIT_HOST_MSG_2_8821C(v))
/* 2 REG_HMEBOX3_8821C */
#define BIT_SHIFT_HOST_MSG_3_8821C 0
#define BIT_MASK_HOST_MSG_3_8821C 0xffffffffL
-#define BIT_HOST_MSG_3_8821C(x) (((x) & BIT_MASK_HOST_MSG_3_8821C) << BIT_SHIFT_HOST_MSG_3_8821C)
-#define BIT_GET_HOST_MSG_3_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_3_8821C) & BIT_MASK_HOST_MSG_3_8821C)
-
-
-/* 2 REG_LLT_INIT_8821C */
-
-#define BIT_SHIFT_LLTE_RWM_8821C 30
-#define BIT_MASK_LLTE_RWM_8821C 0x3
-#define BIT_LLTE_RWM_8821C(x) (((x) & BIT_MASK_LLTE_RWM_8821C) << BIT_SHIFT_LLTE_RWM_8821C)
-#define BIT_GET_LLTE_RWM_8821C(x) (((x) >> BIT_SHIFT_LLTE_RWM_8821C) & BIT_MASK_LLTE_RWM_8821C)
+#define BIT_HOST_MSG_3_8821C(x) \
+ (((x) & BIT_MASK_HOST_MSG_3_8821C) << BIT_SHIFT_HOST_MSG_3_8821C)
+#define BITS_HOST_MSG_3_8821C \
+ (BIT_MASK_HOST_MSG_3_8821C << BIT_SHIFT_HOST_MSG_3_8821C)
+#define BIT_CLEAR_HOST_MSG_3_8821C(x) ((x) & (~BITS_HOST_MSG_3_8821C))
+#define BIT_GET_HOST_MSG_3_8821C(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_3_8821C) & BIT_MASK_HOST_MSG_3_8821C)
+#define BIT_SET_HOST_MSG_3_8821C(x, v) \
+ (BIT_CLEAR_HOST_MSG_3_8821C(x) | BIT_HOST_MSG_3_8821C(v))
+/* 2 REG_NOT_VALID_8821C */
-#define BIT_SHIFT_LLTINI_PDATA_V1_8821C 16
-#define BIT_MASK_LLTINI_PDATA_V1_8821C 0xfff
-#define BIT_LLTINI_PDATA_V1_8821C(x) (((x) & BIT_MASK_LLTINI_PDATA_V1_8821C) << BIT_SHIFT_LLTINI_PDATA_V1_8821C)
-#define BIT_GET_LLTINI_PDATA_V1_8821C(x) (((x) >> BIT_SHIFT_LLTINI_PDATA_V1_8821C) & BIT_MASK_LLTINI_PDATA_V1_8821C)
-
-
-#define BIT_SHIFT_LLTINI_HDATA_V1_8821C 0
-#define BIT_MASK_LLTINI_HDATA_V1_8821C 0xfff
-#define BIT_LLTINI_HDATA_V1_8821C(x) (((x) & BIT_MASK_LLTINI_HDATA_V1_8821C) << BIT_SHIFT_LLTINI_HDATA_V1_8821C)
-#define BIT_GET_LLTINI_HDATA_V1_8821C(x) (((x) >> BIT_SHIFT_LLTINI_HDATA_V1_8821C) & BIT_MASK_LLTINI_HDATA_V1_8821C)
-
-
-/* 2 REG_LLT_INIT_ADDR_8821C */
-
-#define BIT_SHIFT_LLTINI_ADDR_V1_8821C 0
-#define BIT_MASK_LLTINI_ADDR_V1_8821C 0xfff
-#define BIT_LLTINI_ADDR_V1_8821C(x) (((x) & BIT_MASK_LLTINI_ADDR_V1_8821C) << BIT_SHIFT_LLTINI_ADDR_V1_8821C)
-#define BIT_GET_LLTINI_ADDR_V1_8821C(x) (((x) >> BIT_SHIFT_LLTINI_ADDR_V1_8821C) & BIT_MASK_LLTINI_ADDR_V1_8821C)
-
+/* 2 REG_NOT_VALID_8821C */
/* 2 REG_BB_ACCESS_CTRL_8821C */
#define BIT_SHIFT_BB_WRITE_READ_8821C 30
#define BIT_MASK_BB_WRITE_READ_8821C 0x3
-#define BIT_BB_WRITE_READ_8821C(x) (((x) & BIT_MASK_BB_WRITE_READ_8821C) << BIT_SHIFT_BB_WRITE_READ_8821C)
-#define BIT_GET_BB_WRITE_READ_8821C(x) (((x) >> BIT_SHIFT_BB_WRITE_READ_8821C) & BIT_MASK_BB_WRITE_READ_8821C)
-
+#define BIT_BB_WRITE_READ_8821C(x) \
+ (((x) & BIT_MASK_BB_WRITE_READ_8821C) << BIT_SHIFT_BB_WRITE_READ_8821C)
+#define BITS_BB_WRITE_READ_8821C \
+ (BIT_MASK_BB_WRITE_READ_8821C << BIT_SHIFT_BB_WRITE_READ_8821C)
+#define BIT_CLEAR_BB_WRITE_READ_8821C(x) ((x) & (~BITS_BB_WRITE_READ_8821C))
+#define BIT_GET_BB_WRITE_READ_8821C(x) \
+ (((x) >> BIT_SHIFT_BB_WRITE_READ_8821C) & BIT_MASK_BB_WRITE_READ_8821C)
+#define BIT_SET_BB_WRITE_READ_8821C(x, v) \
+ (BIT_CLEAR_BB_WRITE_READ_8821C(x) | BIT_BB_WRITE_READ_8821C(v))
#define BIT_SHIFT_BB_WRITE_EN_8821C 12
#define BIT_MASK_BB_WRITE_EN_8821C 0xf
-#define BIT_BB_WRITE_EN_8821C(x) (((x) & BIT_MASK_BB_WRITE_EN_8821C) << BIT_SHIFT_BB_WRITE_EN_8821C)
-#define BIT_GET_BB_WRITE_EN_8821C(x) (((x) >> BIT_SHIFT_BB_WRITE_EN_8821C) & BIT_MASK_BB_WRITE_EN_8821C)
-
+#define BIT_BB_WRITE_EN_8821C(x) \
+ (((x) & BIT_MASK_BB_WRITE_EN_8821C) << BIT_SHIFT_BB_WRITE_EN_8821C)
+#define BITS_BB_WRITE_EN_8821C \
+ (BIT_MASK_BB_WRITE_EN_8821C << BIT_SHIFT_BB_WRITE_EN_8821C)
+#define BIT_CLEAR_BB_WRITE_EN_8821C(x) ((x) & (~BITS_BB_WRITE_EN_8821C))
+#define BIT_GET_BB_WRITE_EN_8821C(x) \
+ (((x) >> BIT_SHIFT_BB_WRITE_EN_8821C) & BIT_MASK_BB_WRITE_EN_8821C)
+#define BIT_SET_BB_WRITE_EN_8821C(x, v) \
+ (BIT_CLEAR_BB_WRITE_EN_8821C(x) | BIT_BB_WRITE_EN_8821C(v))
#define BIT_SHIFT_BB_ADDR_8821C 2
#define BIT_MASK_BB_ADDR_8821C 0x1ff
-#define BIT_BB_ADDR_8821C(x) (((x) & BIT_MASK_BB_ADDR_8821C) << BIT_SHIFT_BB_ADDR_8821C)
-#define BIT_GET_BB_ADDR_8821C(x) (((x) >> BIT_SHIFT_BB_ADDR_8821C) & BIT_MASK_BB_ADDR_8821C)
+#define BIT_BB_ADDR_8821C(x) \
+ (((x) & BIT_MASK_BB_ADDR_8821C) << BIT_SHIFT_BB_ADDR_8821C)
+#define BITS_BB_ADDR_8821C (BIT_MASK_BB_ADDR_8821C << BIT_SHIFT_BB_ADDR_8821C)
+#define BIT_CLEAR_BB_ADDR_8821C(x) ((x) & (~BITS_BB_ADDR_8821C))
+#define BIT_GET_BB_ADDR_8821C(x) \
+ (((x) >> BIT_SHIFT_BB_ADDR_8821C) & BIT_MASK_BB_ADDR_8821C)
+#define BIT_SET_BB_ADDR_8821C(x, v) \
+ (BIT_CLEAR_BB_ADDR_8821C(x) | BIT_BB_ADDR_8821C(v))
#define BIT_BB_ERRACC_8821C BIT(0)
@@ -2658,51 +4406,84 @@
#define BIT_SHIFT_BB_DATA_8821C 0
#define BIT_MASK_BB_DATA_8821C 0xffffffffL
-#define BIT_BB_DATA_8821C(x) (((x) & BIT_MASK_BB_DATA_8821C) << BIT_SHIFT_BB_DATA_8821C)
-#define BIT_GET_BB_DATA_8821C(x) (((x) >> BIT_SHIFT_BB_DATA_8821C) & BIT_MASK_BB_DATA_8821C)
-
+#define BIT_BB_DATA_8821C(x) \
+ (((x) & BIT_MASK_BB_DATA_8821C) << BIT_SHIFT_BB_DATA_8821C)
+#define BITS_BB_DATA_8821C (BIT_MASK_BB_DATA_8821C << BIT_SHIFT_BB_DATA_8821C)
+#define BIT_CLEAR_BB_DATA_8821C(x) ((x) & (~BITS_BB_DATA_8821C))
+#define BIT_GET_BB_DATA_8821C(x) \
+ (((x) >> BIT_SHIFT_BB_DATA_8821C) & BIT_MASK_BB_DATA_8821C)
+#define BIT_SET_BB_DATA_8821C(x, v) \
+ (BIT_CLEAR_BB_DATA_8821C(x) | BIT_BB_DATA_8821C(v))
/* 2 REG_HMEBOX_E0_8821C */
#define BIT_SHIFT_HMEBOX_E0_8821C 0
#define BIT_MASK_HMEBOX_E0_8821C 0xffffffffL
-#define BIT_HMEBOX_E0_8821C(x) (((x) & BIT_MASK_HMEBOX_E0_8821C) << BIT_SHIFT_HMEBOX_E0_8821C)
-#define BIT_GET_HMEBOX_E0_8821C(x) (((x) >> BIT_SHIFT_HMEBOX_E0_8821C) & BIT_MASK_HMEBOX_E0_8821C)
-
+#define BIT_HMEBOX_E0_8821C(x) \
+ (((x) & BIT_MASK_HMEBOX_E0_8821C) << BIT_SHIFT_HMEBOX_E0_8821C)
+#define BITS_HMEBOX_E0_8821C \
+ (BIT_MASK_HMEBOX_E0_8821C << BIT_SHIFT_HMEBOX_E0_8821C)
+#define BIT_CLEAR_HMEBOX_E0_8821C(x) ((x) & (~BITS_HMEBOX_E0_8821C))
+#define BIT_GET_HMEBOX_E0_8821C(x) \
+ (((x) >> BIT_SHIFT_HMEBOX_E0_8821C) & BIT_MASK_HMEBOX_E0_8821C)
+#define BIT_SET_HMEBOX_E0_8821C(x, v) \
+ (BIT_CLEAR_HMEBOX_E0_8821C(x) | BIT_HMEBOX_E0_8821C(v))
/* 2 REG_HMEBOX_E1_8821C */
#define BIT_SHIFT_HMEBOX_E1_8821C 0
#define BIT_MASK_HMEBOX_E1_8821C 0xffffffffL
-#define BIT_HMEBOX_E1_8821C(x) (((x) & BIT_MASK_HMEBOX_E1_8821C) << BIT_SHIFT_HMEBOX_E1_8821C)
-#define BIT_GET_HMEBOX_E1_8821C(x) (((x) >> BIT_SHIFT_HMEBOX_E1_8821C) & BIT_MASK_HMEBOX_E1_8821C)
-
+#define BIT_HMEBOX_E1_8821C(x) \
+ (((x) & BIT_MASK_HMEBOX_E1_8821C) << BIT_SHIFT_HMEBOX_E1_8821C)
+#define BITS_HMEBOX_E1_8821C \
+ (BIT_MASK_HMEBOX_E1_8821C << BIT_SHIFT_HMEBOX_E1_8821C)
+#define BIT_CLEAR_HMEBOX_E1_8821C(x) ((x) & (~BITS_HMEBOX_E1_8821C))
+#define BIT_GET_HMEBOX_E1_8821C(x) \
+ (((x) >> BIT_SHIFT_HMEBOX_E1_8821C) & BIT_MASK_HMEBOX_E1_8821C)
+#define BIT_SET_HMEBOX_E1_8821C(x, v) \
+ (BIT_CLEAR_HMEBOX_E1_8821C(x) | BIT_HMEBOX_E1_8821C(v))
/* 2 REG_HMEBOX_E2_8821C */
#define BIT_SHIFT_HMEBOX_E2_8821C 0
#define BIT_MASK_HMEBOX_E2_8821C 0xffffffffL
-#define BIT_HMEBOX_E2_8821C(x) (((x) & BIT_MASK_HMEBOX_E2_8821C) << BIT_SHIFT_HMEBOX_E2_8821C)
-#define BIT_GET_HMEBOX_E2_8821C(x) (((x) >> BIT_SHIFT_HMEBOX_E2_8821C) & BIT_MASK_HMEBOX_E2_8821C)
-
+#define BIT_HMEBOX_E2_8821C(x) \
+ (((x) & BIT_MASK_HMEBOX_E2_8821C) << BIT_SHIFT_HMEBOX_E2_8821C)
+#define BITS_HMEBOX_E2_8821C \
+ (BIT_MASK_HMEBOX_E2_8821C << BIT_SHIFT_HMEBOX_E2_8821C)
+#define BIT_CLEAR_HMEBOX_E2_8821C(x) ((x) & (~BITS_HMEBOX_E2_8821C))
+#define BIT_GET_HMEBOX_E2_8821C(x) \
+ (((x) >> BIT_SHIFT_HMEBOX_E2_8821C) & BIT_MASK_HMEBOX_E2_8821C)
+#define BIT_SET_HMEBOX_E2_8821C(x, v) \
+ (BIT_CLEAR_HMEBOX_E2_8821C(x) | BIT_HMEBOX_E2_8821C(v))
/* 2 REG_HMEBOX_E3_8821C */
#define BIT_SHIFT_HMEBOX_E3_8821C 0
#define BIT_MASK_HMEBOX_E3_8821C 0xffffffffL
-#define BIT_HMEBOX_E3_8821C(x) (((x) & BIT_MASK_HMEBOX_E3_8821C) << BIT_SHIFT_HMEBOX_E3_8821C)
-#define BIT_GET_HMEBOX_E3_8821C(x) (((x) >> BIT_SHIFT_HMEBOX_E3_8821C) & BIT_MASK_HMEBOX_E3_8821C)
-
-
-/* 2 REG_NOT_VALID_8821C */
+#define BIT_HMEBOX_E3_8821C(x) \
+ (((x) & BIT_MASK_HMEBOX_E3_8821C) << BIT_SHIFT_HMEBOX_E3_8821C)
+#define BITS_HMEBOX_E3_8821C \
+ (BIT_MASK_HMEBOX_E3_8821C << BIT_SHIFT_HMEBOX_E3_8821C)
+#define BIT_CLEAR_HMEBOX_E3_8821C(x) ((x) & (~BITS_HMEBOX_E3_8821C))
+#define BIT_GET_HMEBOX_E3_8821C(x) \
+ (((x) >> BIT_SHIFT_HMEBOX_E3_8821C) & BIT_MASK_HMEBOX_E3_8821C)
+#define BIT_SET_HMEBOX_E3_8821C(x, v) \
+ (BIT_CLEAR_HMEBOX_E3_8821C(x) | BIT_HMEBOX_E3_8821C(v))
/* 2 REG_CR_EXT_8821C */
#define BIT_SHIFT_PHY_REQ_DELAY_8821C 24
#define BIT_MASK_PHY_REQ_DELAY_8821C 0xf
-#define BIT_PHY_REQ_DELAY_8821C(x) (((x) & BIT_MASK_PHY_REQ_DELAY_8821C) << BIT_SHIFT_PHY_REQ_DELAY_8821C)
-#define BIT_GET_PHY_REQ_DELAY_8821C(x) (((x) >> BIT_SHIFT_PHY_REQ_DELAY_8821C) & BIT_MASK_PHY_REQ_DELAY_8821C)
-
+#define BIT_PHY_REQ_DELAY_8821C(x) \
+ (((x) & BIT_MASK_PHY_REQ_DELAY_8821C) << BIT_SHIFT_PHY_REQ_DELAY_8821C)
+#define BITS_PHY_REQ_DELAY_8821C \
+ (BIT_MASK_PHY_REQ_DELAY_8821C << BIT_SHIFT_PHY_REQ_DELAY_8821C)
+#define BIT_CLEAR_PHY_REQ_DELAY_8821C(x) ((x) & (~BITS_PHY_REQ_DELAY_8821C))
+#define BIT_GET_PHY_REQ_DELAY_8821C(x) \
+ (((x) >> BIT_SHIFT_PHY_REQ_DELAY_8821C) & BIT_MASK_PHY_REQ_DELAY_8821C)
+#define BIT_SET_PHY_REQ_DELAY_8821C(x, v) \
+ (BIT_CLEAR_PHY_REQ_DELAY_8821C(x) | BIT_PHY_REQ_DELAY_8821C(v))
/* 2 REG_NOT_VALID_8821C */
#define BIT_SPD_DOWN_8821C BIT(16)
@@ -2711,41 +4492,82 @@
#define BIT_SHIFT_NETYPE4_8821C 4
#define BIT_MASK_NETYPE4_8821C 0x3
-#define BIT_NETYPE4_8821C(x) (((x) & BIT_MASK_NETYPE4_8821C) << BIT_SHIFT_NETYPE4_8821C)
-#define BIT_GET_NETYPE4_8821C(x) (((x) >> BIT_SHIFT_NETYPE4_8821C) & BIT_MASK_NETYPE4_8821C)
-
+#define BIT_NETYPE4_8821C(x) \
+ (((x) & BIT_MASK_NETYPE4_8821C) << BIT_SHIFT_NETYPE4_8821C)
+#define BITS_NETYPE4_8821C (BIT_MASK_NETYPE4_8821C << BIT_SHIFT_NETYPE4_8821C)
+#define BIT_CLEAR_NETYPE4_8821C(x) ((x) & (~BITS_NETYPE4_8821C))
+#define BIT_GET_NETYPE4_8821C(x) \
+ (((x) >> BIT_SHIFT_NETYPE4_8821C) & BIT_MASK_NETYPE4_8821C)
+#define BIT_SET_NETYPE4_8821C(x, v) \
+ (BIT_CLEAR_NETYPE4_8821C(x) | BIT_NETYPE4_8821C(v))
#define BIT_SHIFT_NETYPE3_8821C 2
#define BIT_MASK_NETYPE3_8821C 0x3
-#define BIT_NETYPE3_8821C(x) (((x) & BIT_MASK_NETYPE3_8821C) << BIT_SHIFT_NETYPE3_8821C)
-#define BIT_GET_NETYPE3_8821C(x) (((x) >> BIT_SHIFT_NETYPE3_8821C) & BIT_MASK_NETYPE3_8821C)
-
+#define BIT_NETYPE3_8821C(x) \
+ (((x) & BIT_MASK_NETYPE3_8821C) << BIT_SHIFT_NETYPE3_8821C)
+#define BITS_NETYPE3_8821C (BIT_MASK_NETYPE3_8821C << BIT_SHIFT_NETYPE3_8821C)
+#define BIT_CLEAR_NETYPE3_8821C(x) ((x) & (~BITS_NETYPE3_8821C))
+#define BIT_GET_NETYPE3_8821C(x) \
+ (((x) >> BIT_SHIFT_NETYPE3_8821C) & BIT_MASK_NETYPE3_8821C)
+#define BIT_SET_NETYPE3_8821C(x, v) \
+ (BIT_CLEAR_NETYPE3_8821C(x) | BIT_NETYPE3_8821C(v))
#define BIT_SHIFT_NETYPE2_8821C 0
#define BIT_MASK_NETYPE2_8821C 0x3
-#define BIT_NETYPE2_8821C(x) (((x) & BIT_MASK_NETYPE2_8821C) << BIT_SHIFT_NETYPE2_8821C)
-#define BIT_GET_NETYPE2_8821C(x) (((x) >> BIT_SHIFT_NETYPE2_8821C) & BIT_MASK_NETYPE2_8821C)
+#define BIT_NETYPE2_8821C(x) \
+ (((x) & BIT_MASK_NETYPE2_8821C) << BIT_SHIFT_NETYPE2_8821C)
+#define BITS_NETYPE2_8821C (BIT_MASK_NETYPE2_8821C << BIT_SHIFT_NETYPE2_8821C)
+#define BIT_CLEAR_NETYPE2_8821C(x) ((x) & (~BITS_NETYPE2_8821C))
+#define BIT_GET_NETYPE2_8821C(x) \
+ (((x) >> BIT_SHIFT_NETYPE2_8821C) & BIT_MASK_NETYPE2_8821C)
+#define BIT_SET_NETYPE2_8821C(x, v) \
+ (BIT_CLEAR_NETYPE2_8821C(x) | BIT_NETYPE2_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
/* 2 REG_FWFF_8821C */
#define BIT_SHIFT_PKTNUM_TH_V1_8821C 24
#define BIT_MASK_PKTNUM_TH_V1_8821C 0xff
-#define BIT_PKTNUM_TH_V1_8821C(x) (((x) & BIT_MASK_PKTNUM_TH_V1_8821C) << BIT_SHIFT_PKTNUM_TH_V1_8821C)
-#define BIT_GET_PKTNUM_TH_V1_8821C(x) (((x) >> BIT_SHIFT_PKTNUM_TH_V1_8821C) & BIT_MASK_PKTNUM_TH_V1_8821C)
-
+#define BIT_PKTNUM_TH_V1_8821C(x) \
+ (((x) & BIT_MASK_PKTNUM_TH_V1_8821C) << BIT_SHIFT_PKTNUM_TH_V1_8821C)
+#define BITS_PKTNUM_TH_V1_8821C \
+ (BIT_MASK_PKTNUM_TH_V1_8821C << BIT_SHIFT_PKTNUM_TH_V1_8821C)
+#define BIT_CLEAR_PKTNUM_TH_V1_8821C(x) ((x) & (~BITS_PKTNUM_TH_V1_8821C))
+#define BIT_GET_PKTNUM_TH_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_PKTNUM_TH_V1_8821C) & BIT_MASK_PKTNUM_TH_V1_8821C)
+#define BIT_SET_PKTNUM_TH_V1_8821C(x, v) \
+ (BIT_CLEAR_PKTNUM_TH_V1_8821C(x) | BIT_PKTNUM_TH_V1_8821C(v))
#define BIT_SHIFT_TIMER_TH_8821C 16
#define BIT_MASK_TIMER_TH_8821C 0xff
-#define BIT_TIMER_TH_8821C(x) (((x) & BIT_MASK_TIMER_TH_8821C) << BIT_SHIFT_TIMER_TH_8821C)
-#define BIT_GET_TIMER_TH_8821C(x) (((x) >> BIT_SHIFT_TIMER_TH_8821C) & BIT_MASK_TIMER_TH_8821C)
-
+#define BIT_TIMER_TH_8821C(x) \
+ (((x) & BIT_MASK_TIMER_TH_8821C) << BIT_SHIFT_TIMER_TH_8821C)
+#define BITS_TIMER_TH_8821C \
+ (BIT_MASK_TIMER_TH_8821C << BIT_SHIFT_TIMER_TH_8821C)
+#define BIT_CLEAR_TIMER_TH_8821C(x) ((x) & (~BITS_TIMER_TH_8821C))
+#define BIT_GET_TIMER_TH_8821C(x) \
+ (((x) >> BIT_SHIFT_TIMER_TH_8821C) & BIT_MASK_TIMER_TH_8821C)
+#define BIT_SET_TIMER_TH_8821C(x, v) \
+ (BIT_CLEAR_TIMER_TH_8821C(x) | BIT_TIMER_TH_8821C(v))
#define BIT_SHIFT_RXPKT1ENADDR_8821C 0
#define BIT_MASK_RXPKT1ENADDR_8821C 0xffff
-#define BIT_RXPKT1ENADDR_8821C(x) (((x) & BIT_MASK_RXPKT1ENADDR_8821C) << BIT_SHIFT_RXPKT1ENADDR_8821C)
-#define BIT_GET_RXPKT1ENADDR_8821C(x) (((x) >> BIT_SHIFT_RXPKT1ENADDR_8821C) & BIT_MASK_RXPKT1ENADDR_8821C)
-
+#define BIT_RXPKT1ENADDR_8821C(x) \
+ (((x) & BIT_MASK_RXPKT1ENADDR_8821C) << BIT_SHIFT_RXPKT1ENADDR_8821C)
+#define BITS_RXPKT1ENADDR_8821C \
+ (BIT_MASK_RXPKT1ENADDR_8821C << BIT_SHIFT_RXPKT1ENADDR_8821C)
+#define BIT_CLEAR_RXPKT1ENADDR_8821C(x) ((x) & (~BITS_RXPKT1ENADDR_8821C))
+#define BIT_GET_RXPKT1ENADDR_8821C(x) \
+ (((x) >> BIT_SHIFT_RXPKT1ENADDR_8821C) & BIT_MASK_RXPKT1ENADDR_8821C)
+#define BIT_SET_RXPKT1ENADDR_8821C(x, v) \
+ (BIT_CLEAR_RXPKT1ENADDR_8821C(x) | BIT_RXPKT1ENADDR_8821C(v))
/* 2 REG_RXFF_PTR_V1_8821C */
@@ -2753,9 +4575,17 @@
#define BIT_SHIFT_RXFF0_RDPTR_V2_8821C 0
#define BIT_MASK_RXFF0_RDPTR_V2_8821C 0x3ffff
-#define BIT_RXFF0_RDPTR_V2_8821C(x) (((x) & BIT_MASK_RXFF0_RDPTR_V2_8821C) << BIT_SHIFT_RXFF0_RDPTR_V2_8821C)
-#define BIT_GET_RXFF0_RDPTR_V2_8821C(x) (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8821C) & BIT_MASK_RXFF0_RDPTR_V2_8821C)
-
+#define BIT_RXFF0_RDPTR_V2_8821C(x) \
+ (((x) & BIT_MASK_RXFF0_RDPTR_V2_8821C) \
+ << BIT_SHIFT_RXFF0_RDPTR_V2_8821C)
+#define BITS_RXFF0_RDPTR_V2_8821C \
+ (BIT_MASK_RXFF0_RDPTR_V2_8821C << BIT_SHIFT_RXFF0_RDPTR_V2_8821C)
+#define BIT_CLEAR_RXFF0_RDPTR_V2_8821C(x) ((x) & (~BITS_RXFF0_RDPTR_V2_8821C))
+#define BIT_GET_RXFF0_RDPTR_V2_8821C(x) \
+ (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8821C) & \
+ BIT_MASK_RXFF0_RDPTR_V2_8821C)
+#define BIT_SET_RXFF0_RDPTR_V2_8821C(x, v) \
+ (BIT_CLEAR_RXFF0_RDPTR_V2_8821C(x) | BIT_RXFF0_RDPTR_V2_8821C(v))
/* 2 REG_RXFF_WTR_V1_8821C */
@@ -2763,9 +4593,17 @@
#define BIT_SHIFT_RXFF0_WTPTR_V2_8821C 0
#define BIT_MASK_RXFF0_WTPTR_V2_8821C 0x3ffff
-#define BIT_RXFF0_WTPTR_V2_8821C(x) (((x) & BIT_MASK_RXFF0_WTPTR_V2_8821C) << BIT_SHIFT_RXFF0_WTPTR_V2_8821C)
-#define BIT_GET_RXFF0_WTPTR_V2_8821C(x) (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8821C) & BIT_MASK_RXFF0_WTPTR_V2_8821C)
-
+#define BIT_RXFF0_WTPTR_V2_8821C(x) \
+ (((x) & BIT_MASK_RXFF0_WTPTR_V2_8821C) \
+ << BIT_SHIFT_RXFF0_WTPTR_V2_8821C)
+#define BITS_RXFF0_WTPTR_V2_8821C \
+ (BIT_MASK_RXFF0_WTPTR_V2_8821C << BIT_SHIFT_RXFF0_WTPTR_V2_8821C)
+#define BIT_CLEAR_RXFF0_WTPTR_V2_8821C(x) ((x) & (~BITS_RXFF0_WTPTR_V2_8821C))
+#define BIT_GET_RXFF0_WTPTR_V2_8821C(x) \
+ (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8821C) & \
+ BIT_MASK_RXFF0_WTPTR_V2_8821C)
+#define BIT_SET_RXFF0_WTPTR_V2_8821C(x, v) \
+ (BIT_CLEAR_RXFF0_WTPTR_V2_8821C(x) | BIT_RXFF0_WTPTR_V2_8821C(v))
/* 2 REG_FE2IMR_8821C */
#define BIT__FE4ISR__IND_MSK_8821C BIT(29)
@@ -2999,47 +4837,84 @@
#define BIT_SHIFT_MID_31TO0_8821C 0
#define BIT_MASK_MID_31TO0_8821C 0xffffffffL
-#define BIT_MID_31TO0_8821C(x) (((x) & BIT_MASK_MID_31TO0_8821C) << BIT_SHIFT_MID_31TO0_8821C)
-#define BIT_GET_MID_31TO0_8821C(x) (((x) >> BIT_SHIFT_MID_31TO0_8821C) & BIT_MASK_MID_31TO0_8821C)
-
+#define BIT_MID_31TO0_8821C(x) \
+ (((x) & BIT_MASK_MID_31TO0_8821C) << BIT_SHIFT_MID_31TO0_8821C)
+#define BITS_MID_31TO0_8821C \
+ (BIT_MASK_MID_31TO0_8821C << BIT_SHIFT_MID_31TO0_8821C)
+#define BIT_CLEAR_MID_31TO0_8821C(x) ((x) & (~BITS_MID_31TO0_8821C))
+#define BIT_GET_MID_31TO0_8821C(x) \
+ (((x) >> BIT_SHIFT_MID_31TO0_8821C) & BIT_MASK_MID_31TO0_8821C)
+#define BIT_SET_MID_31TO0_8821C(x, v) \
+ (BIT_CLEAR_MID_31TO0_8821C(x) | BIT_MID_31TO0_8821C(v))
/* 2 REG_SPWR1_8821C */
#define BIT_SHIFT_MID_63TO32_8821C 0
#define BIT_MASK_MID_63TO32_8821C 0xffffffffL
-#define BIT_MID_63TO32_8821C(x) (((x) & BIT_MASK_MID_63TO32_8821C) << BIT_SHIFT_MID_63TO32_8821C)
-#define BIT_GET_MID_63TO32_8821C(x) (((x) >> BIT_SHIFT_MID_63TO32_8821C) & BIT_MASK_MID_63TO32_8821C)
-
+#define BIT_MID_63TO32_8821C(x) \
+ (((x) & BIT_MASK_MID_63TO32_8821C) << BIT_SHIFT_MID_63TO32_8821C)
+#define BITS_MID_63TO32_8821C \
+ (BIT_MASK_MID_63TO32_8821C << BIT_SHIFT_MID_63TO32_8821C)
+#define BIT_CLEAR_MID_63TO32_8821C(x) ((x) & (~BITS_MID_63TO32_8821C))
+#define BIT_GET_MID_63TO32_8821C(x) \
+ (((x) >> BIT_SHIFT_MID_63TO32_8821C) & BIT_MASK_MID_63TO32_8821C)
+#define BIT_SET_MID_63TO32_8821C(x, v) \
+ (BIT_CLEAR_MID_63TO32_8821C(x) | BIT_MID_63TO32_8821C(v))
/* 2 REG_SPWR2_8821C */
#define BIT_SHIFT_MID_95O64_8821C 0
#define BIT_MASK_MID_95O64_8821C 0xffffffffL
-#define BIT_MID_95O64_8821C(x) (((x) & BIT_MASK_MID_95O64_8821C) << BIT_SHIFT_MID_95O64_8821C)
-#define BIT_GET_MID_95O64_8821C(x) (((x) >> BIT_SHIFT_MID_95O64_8821C) & BIT_MASK_MID_95O64_8821C)
-
+#define BIT_MID_95O64_8821C(x) \
+ (((x) & BIT_MASK_MID_95O64_8821C) << BIT_SHIFT_MID_95O64_8821C)
+#define BITS_MID_95O64_8821C \
+ (BIT_MASK_MID_95O64_8821C << BIT_SHIFT_MID_95O64_8821C)
+#define BIT_CLEAR_MID_95O64_8821C(x) ((x) & (~BITS_MID_95O64_8821C))
+#define BIT_GET_MID_95O64_8821C(x) \
+ (((x) >> BIT_SHIFT_MID_95O64_8821C) & BIT_MASK_MID_95O64_8821C)
+#define BIT_SET_MID_95O64_8821C(x, v) \
+ (BIT_CLEAR_MID_95O64_8821C(x) | BIT_MID_95O64_8821C(v))
/* 2 REG_SPWR3_8821C */
#define BIT_SHIFT_MID_127TO96_8821C 0
#define BIT_MASK_MID_127TO96_8821C 0xffffffffL
-#define BIT_MID_127TO96_8821C(x) (((x) & BIT_MASK_MID_127TO96_8821C) << BIT_SHIFT_MID_127TO96_8821C)
-#define BIT_GET_MID_127TO96_8821C(x) (((x) >> BIT_SHIFT_MID_127TO96_8821C) & BIT_MASK_MID_127TO96_8821C)
-
+#define BIT_MID_127TO96_8821C(x) \
+ (((x) & BIT_MASK_MID_127TO96_8821C) << BIT_SHIFT_MID_127TO96_8821C)
+#define BITS_MID_127TO96_8821C \
+ (BIT_MASK_MID_127TO96_8821C << BIT_SHIFT_MID_127TO96_8821C)
+#define BIT_CLEAR_MID_127TO96_8821C(x) ((x) & (~BITS_MID_127TO96_8821C))
+#define BIT_GET_MID_127TO96_8821C(x) \
+ (((x) >> BIT_SHIFT_MID_127TO96_8821C) & BIT_MASK_MID_127TO96_8821C)
+#define BIT_SET_MID_127TO96_8821C(x, v) \
+ (BIT_CLEAR_MID_127TO96_8821C(x) | BIT_MID_127TO96_8821C(v))
/* 2 REG_POWSEQ_8821C */
#define BIT_SHIFT_SEQNUM_MID_8821C 16
#define BIT_MASK_SEQNUM_MID_8821C 0xffff
-#define BIT_SEQNUM_MID_8821C(x) (((x) & BIT_MASK_SEQNUM_MID_8821C) << BIT_SHIFT_SEQNUM_MID_8821C)
-#define BIT_GET_SEQNUM_MID_8821C(x) (((x) >> BIT_SHIFT_SEQNUM_MID_8821C) & BIT_MASK_SEQNUM_MID_8821C)
-
+#define BIT_SEQNUM_MID_8821C(x) \
+ (((x) & BIT_MASK_SEQNUM_MID_8821C) << BIT_SHIFT_SEQNUM_MID_8821C)
+#define BITS_SEQNUM_MID_8821C \
+ (BIT_MASK_SEQNUM_MID_8821C << BIT_SHIFT_SEQNUM_MID_8821C)
+#define BIT_CLEAR_SEQNUM_MID_8821C(x) ((x) & (~BITS_SEQNUM_MID_8821C))
+#define BIT_GET_SEQNUM_MID_8821C(x) \
+ (((x) >> BIT_SHIFT_SEQNUM_MID_8821C) & BIT_MASK_SEQNUM_MID_8821C)
+#define BIT_SET_SEQNUM_MID_8821C(x, v) \
+ (BIT_CLEAR_SEQNUM_MID_8821C(x) | BIT_SEQNUM_MID_8821C(v))
#define BIT_SHIFT_REF_MID_8821C 0
#define BIT_MASK_REF_MID_8821C 0x7f
-#define BIT_REF_MID_8821C(x) (((x) & BIT_MASK_REF_MID_8821C) << BIT_SHIFT_REF_MID_8821C)
-#define BIT_GET_REF_MID_8821C(x) (((x) >> BIT_SHIFT_REF_MID_8821C) & BIT_MASK_REF_MID_8821C)
+#define BIT_REF_MID_8821C(x) \
+ (((x) & BIT_MASK_REF_MID_8821C) << BIT_SHIFT_REF_MID_8821C)
+#define BITS_REF_MID_8821C (BIT_MASK_REF_MID_8821C << BIT_SHIFT_REF_MID_8821C)
+#define BIT_CLEAR_REF_MID_8821C(x) ((x) & (~BITS_REF_MID_8821C))
+#define BIT_GET_REF_MID_8821C(x) \
+ (((x) >> BIT_SHIFT_REF_MID_8821C) & BIT_MASK_REF_MID_8821C)
+#define BIT_SET_REF_MID_8821C(x, v) \
+ (BIT_CLEAR_REF_MID_8821C(x) | BIT_REF_MID_8821C(v))
+/* 2 REG_NOT_VALID_8821C */
/* 2 REG_TC7_CTRL_V1_8821C */
#define BIT_TC7INT_EN_8821C BIT(26)
@@ -3048,9 +4923,14 @@
#define BIT_SHIFT_TC7DATA_8821C 0
#define BIT_MASK_TC7DATA_8821C 0xffffff
-#define BIT_TC7DATA_8821C(x) (((x) & BIT_MASK_TC7DATA_8821C) << BIT_SHIFT_TC7DATA_8821C)
-#define BIT_GET_TC7DATA_8821C(x) (((x) >> BIT_SHIFT_TC7DATA_8821C) & BIT_MASK_TC7DATA_8821C)
-
+#define BIT_TC7DATA_8821C(x) \
+ (((x) & BIT_MASK_TC7DATA_8821C) << BIT_SHIFT_TC7DATA_8821C)
+#define BITS_TC7DATA_8821C (BIT_MASK_TC7DATA_8821C << BIT_SHIFT_TC7DATA_8821C)
+#define BIT_CLEAR_TC7DATA_8821C(x) ((x) & (~BITS_TC7DATA_8821C))
+#define BIT_GET_TC7DATA_8821C(x) \
+ (((x) >> BIT_SHIFT_TC7DATA_8821C) & BIT_MASK_TC7DATA_8821C)
+#define BIT_SET_TC7DATA_8821C(x, v) \
+ (BIT_CLEAR_TC7DATA_8821C(x) | BIT_TC7DATA_8821C(v))
/* 2 REG_TC8_CTRL_V1_8821C */
#define BIT_TC8INT_EN_8821C BIT(26)
@@ -3059,26 +4939,493 @@
#define BIT_SHIFT_TC8DATA_8821C 0
#define BIT_MASK_TC8DATA_8821C 0xffffff
-#define BIT_TC8DATA_8821C(x) (((x) & BIT_MASK_TC8DATA_8821C) << BIT_SHIFT_TC8DATA_8821C)
-#define BIT_GET_TC8DATA_8821C(x) (((x) >> BIT_SHIFT_TC8DATA_8821C) & BIT_MASK_TC8DATA_8821C)
+#define BIT_TC8DATA_8821C(x) \
+ (((x) & BIT_MASK_TC8DATA_8821C) << BIT_SHIFT_TC8DATA_8821C)
+#define BITS_TC8DATA_8821C (BIT_MASK_TC8DATA_8821C << BIT_SHIFT_TC8DATA_8821C)
+#define BIT_CLEAR_TC8DATA_8821C(x) ((x) & (~BITS_TC8DATA_8821C))
+#define BIT_GET_TC8DATA_8821C(x) \
+ (((x) >> BIT_SHIFT_TC8DATA_8821C) & BIT_MASK_TC8DATA_8821C)
+#define BIT_SET_TC8DATA_8821C(x, v) \
+ (BIT_CLEAR_TC8DATA_8821C(x) | BIT_TC8DATA_8821C(v))
+
+/* 2 REG_RX_BCN_TBTT_ITVL0_8821C */
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8821C 24
+#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8821C 0xff
+#define BIT_RX_BCN_TBTT_ITVL_CLIENT2_8821C(x) \
+ (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8821C) \
+ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8821C)
+#define BITS_RX_BCN_TBTT_ITVL_CLIENT2_8821C \
+ (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8821C \
+ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8821C)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2_8821C(x) \
+ ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT2_8821C))
+#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT2_8821C(x) \
+ (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8821C) & \
+ BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8821C)
+#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT2_8821C(x, v) \
+ (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2_8821C(x) | \
+ BIT_RX_BCN_TBTT_ITVL_CLIENT2_8821C(v))
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8821C 16
+#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8821C 0xff
+#define BIT_RX_BCN_TBTT_ITVL_CLIENT1_8821C(x) \
+ (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8821C) \
+ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8821C)
+#define BITS_RX_BCN_TBTT_ITVL_CLIENT1_8821C \
+ (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8821C \
+ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8821C)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1_8821C(x) \
+ ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT1_8821C))
+#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT1_8821C(x) \
+ (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8821C) & \
+ BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8821C)
+#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT1_8821C(x, v) \
+ (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1_8821C(x) | \
+ BIT_RX_BCN_TBTT_ITVL_CLIENT1_8821C(v))
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8821C 8
+#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8821C 0xff
+#define BIT_RX_BCN_TBTT_ITVL_CLIENT0_8821C(x) \
+ (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8821C) \
+ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8821C)
+#define BITS_RX_BCN_TBTT_ITVL_CLIENT0_8821C \
+ (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8821C \
+ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8821C)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0_8821C(x) \
+ ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT0_8821C))
+#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT0_8821C(x) \
+ (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8821C) & \
+ BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8821C)
+#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT0_8821C(x, v) \
+ (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0_8821C(x) | \
+ BIT_RX_BCN_TBTT_ITVL_CLIENT0_8821C(v))
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8821C 0
+#define BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8821C 0xff
+#define BIT_RX_BCN_TBTT_ITVL_PORT0_8821C(x) \
+ (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8821C) \
+ << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8821C)
+#define BITS_RX_BCN_TBTT_ITVL_PORT0_8821C \
+ (BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8821C \
+ << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8821C)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0_8821C(x) \
+ ((x) & (~BITS_RX_BCN_TBTT_ITVL_PORT0_8821C))
+#define BIT_GET_RX_BCN_TBTT_ITVL_PORT0_8821C(x) \
+ (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8821C) & \
+ BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8821C)
+#define BIT_SET_RX_BCN_TBTT_ITVL_PORT0_8821C(x, v) \
+ (BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0_8821C(x) | \
+ BIT_RX_BCN_TBTT_ITVL_PORT0_8821C(v))
+
+/* 2 REG_RX_BCN_TBTT_ITVL1_8821C */
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8821C 0
+#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8821C 0xff
+#define BIT_RX_BCN_TBTT_ITVL_CLIENT3_8821C(x) \
+ (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8821C) \
+ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8821C)
+#define BITS_RX_BCN_TBTT_ITVL_CLIENT3_8821C \
+ (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8821C \
+ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8821C)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3_8821C(x) \
+ ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT3_8821C))
+#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT3_8821C(x) \
+ (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8821C) & \
+ BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8821C)
+#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT3_8821C(x, v) \
+ (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3_8821C(x) | \
+ BIT_RX_BCN_TBTT_ITVL_CLIENT3_8821C(v))
+/* 2 REG_NOT_VALID_8821C */
-/* 2 REG_FT2IMR_8821C */
-#define BIT_FS_CLI3_RX_UAPSDMD1_EN_8821C BIT(31)
-#define BIT_FS_CLI3_RX_UAPSDMD0_EN_8821C BIT(30)
-#define BIT_FS_CLI3_TRIGGER_PKT_EN_8821C BIT(29)
-#define BIT_FS_CLI3_EOSP_INT_EN_8821C BIT(28)
-#define BIT_FS_CLI2_RX_UAPSDMD1_EN_8821C BIT(27)
-#define BIT_FS_CLI2_RX_UAPSDMD0_EN_8821C BIT(26)
-#define BIT_FS_CLI2_TRIGGER_PKT_EN_8821C BIT(25)
-#define BIT_FS_CLI2_EOSP_INT_EN_8821C BIT(24)
-#define BIT_FS_CLI1_RX_UAPSDMD1_EN_8821C BIT(23)
-#define BIT_FS_CLI1_RX_UAPSDMD0_EN_8821C BIT(22)
-#define BIT_FS_CLI1_TRIGGER_PKT_EN_8821C BIT(21)
-#define BIT_FS_CLI1_EOSP_INT_EN_8821C BIT(20)
-#define BIT_FS_CLI0_RX_UAPSDMD1_EN_8821C BIT(19)
-#define BIT_FS_CLI0_RX_UAPSDMD0_EN_8821C BIT(18)
-#define BIT_FS_CLI0_TRIGGER_PKT_EN_8821C BIT(17)
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_IO_WRAP_ERR_FLAG_8821C */
+#define BIT_IO_WRAP_ERR_8821C BIT(0)
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_SPEED_SENSOR_8821C */
+#define BIT_DSS_1_RST_N_8821C BIT(31)
+#define BIT_DSS_1_SPEED_EN_8821C BIT(30)
+#define BIT_DSS_1_WIRE_SEL_8821C BIT(29)
+#define BIT_DSS_ENCLK_8821C BIT(28)
+
+#define BIT_SHIFT_DSS_1_RO_SEL_8821C 24
+#define BIT_MASK_DSS_1_RO_SEL_8821C 0x7
+#define BIT_DSS_1_RO_SEL_8821C(x) \
+ (((x) & BIT_MASK_DSS_1_RO_SEL_8821C) << BIT_SHIFT_DSS_1_RO_SEL_8821C)
+#define BITS_DSS_1_RO_SEL_8821C \
+ (BIT_MASK_DSS_1_RO_SEL_8821C << BIT_SHIFT_DSS_1_RO_SEL_8821C)
+#define BIT_CLEAR_DSS_1_RO_SEL_8821C(x) ((x) & (~BITS_DSS_1_RO_SEL_8821C))
+#define BIT_GET_DSS_1_RO_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_DSS_1_RO_SEL_8821C) & BIT_MASK_DSS_1_RO_SEL_8821C)
+#define BIT_SET_DSS_1_RO_SEL_8821C(x, v) \
+ (BIT_CLEAR_DSS_1_RO_SEL_8821C(x) | BIT_DSS_1_RO_SEL_8821C(v))
+
+#define BIT_SHIFT_DSS_1_DATA_IN_8821C 0
+#define BIT_MASK_DSS_1_DATA_IN_8821C 0xfffff
+#define BIT_DSS_1_DATA_IN_8821C(x) \
+ (((x) & BIT_MASK_DSS_1_DATA_IN_8821C) << BIT_SHIFT_DSS_1_DATA_IN_8821C)
+#define BITS_DSS_1_DATA_IN_8821C \
+ (BIT_MASK_DSS_1_DATA_IN_8821C << BIT_SHIFT_DSS_1_DATA_IN_8821C)
+#define BIT_CLEAR_DSS_1_DATA_IN_8821C(x) ((x) & (~BITS_DSS_1_DATA_IN_8821C))
+#define BIT_GET_DSS_1_DATA_IN_8821C(x) \
+ (((x) >> BIT_SHIFT_DSS_1_DATA_IN_8821C) & BIT_MASK_DSS_1_DATA_IN_8821C)
+#define BIT_SET_DSS_1_DATA_IN_8821C(x, v) \
+ (BIT_CLEAR_DSS_1_DATA_IN_8821C(x) | BIT_DSS_1_DATA_IN_8821C(v))
+
+/* 2 REG_SPEED_SENSOR1_8821C */
+#define BIT_DSS_1_READY_8821C BIT(31)
+#define BIT_DSS_1_WSORT_GO_8821C BIT(30)
+
+#define BIT_SHIFT_DSS_1_COUNT_OUT_8821C 0
+#define BIT_MASK_DSS_1_COUNT_OUT_8821C 0xfffff
+#define BIT_DSS_1_COUNT_OUT_8821C(x) \
+ (((x) & BIT_MASK_DSS_1_COUNT_OUT_8821C) \
+ << BIT_SHIFT_DSS_1_COUNT_OUT_8821C)
+#define BITS_DSS_1_COUNT_OUT_8821C \
+ (BIT_MASK_DSS_1_COUNT_OUT_8821C << BIT_SHIFT_DSS_1_COUNT_OUT_8821C)
+#define BIT_CLEAR_DSS_1_COUNT_OUT_8821C(x) ((x) & (~BITS_DSS_1_COUNT_OUT_8821C))
+#define BIT_GET_DSS_1_COUNT_OUT_8821C(x) \
+ (((x) >> BIT_SHIFT_DSS_1_COUNT_OUT_8821C) & \
+ BIT_MASK_DSS_1_COUNT_OUT_8821C)
+#define BIT_SET_DSS_1_COUNT_OUT_8821C(x, v) \
+ (BIT_CLEAR_DSS_1_COUNT_OUT_8821C(x) | BIT_DSS_1_COUNT_OUT_8821C(v))
+
+/* 2 REG_SPEED_SENSOR2_8821C */
+#define BIT_DSS_2_RST_N_8821C BIT(31)
+#define BIT_DSS_2_SPEED_EN_8821C BIT(30)
+#define BIT_DSS_2_WIRE_SEL_8821C BIT(29)
+#define BIT_DSS_ENCLK_8821C BIT(28)
+
+#define BIT_SHIFT_DSS_2_RO_SEL_8821C 24
+#define BIT_MASK_DSS_2_RO_SEL_8821C 0x7
+#define BIT_DSS_2_RO_SEL_8821C(x) \
+ (((x) & BIT_MASK_DSS_2_RO_SEL_8821C) << BIT_SHIFT_DSS_2_RO_SEL_8821C)
+#define BITS_DSS_2_RO_SEL_8821C \
+ (BIT_MASK_DSS_2_RO_SEL_8821C << BIT_SHIFT_DSS_2_RO_SEL_8821C)
+#define BIT_CLEAR_DSS_2_RO_SEL_8821C(x) ((x) & (~BITS_DSS_2_RO_SEL_8821C))
+#define BIT_GET_DSS_2_RO_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_DSS_2_RO_SEL_8821C) & BIT_MASK_DSS_2_RO_SEL_8821C)
+#define BIT_SET_DSS_2_RO_SEL_8821C(x, v) \
+ (BIT_CLEAR_DSS_2_RO_SEL_8821C(x) | BIT_DSS_2_RO_SEL_8821C(v))
+
+#define BIT_SHIFT_DSS_2_DATA_IN_8821C 0
+#define BIT_MASK_DSS_2_DATA_IN_8821C 0xfffff
+#define BIT_DSS_2_DATA_IN_8821C(x) \
+ (((x) & BIT_MASK_DSS_2_DATA_IN_8821C) << BIT_SHIFT_DSS_2_DATA_IN_8821C)
+#define BITS_DSS_2_DATA_IN_8821C \
+ (BIT_MASK_DSS_2_DATA_IN_8821C << BIT_SHIFT_DSS_2_DATA_IN_8821C)
+#define BIT_CLEAR_DSS_2_DATA_IN_8821C(x) ((x) & (~BITS_DSS_2_DATA_IN_8821C))
+#define BIT_GET_DSS_2_DATA_IN_8821C(x) \
+ (((x) >> BIT_SHIFT_DSS_2_DATA_IN_8821C) & BIT_MASK_DSS_2_DATA_IN_8821C)
+#define BIT_SET_DSS_2_DATA_IN_8821C(x, v) \
+ (BIT_CLEAR_DSS_2_DATA_IN_8821C(x) | BIT_DSS_2_DATA_IN_8821C(v))
+
+/* 2 REG_SPEED_SENSOR3_8821C */
+#define BIT_DSS_2_READY_8821C BIT(31)
+#define BIT_DSS_2_WSORT_GO_8821C BIT(30)
+
+#define BIT_SHIFT_DSS_2_COUNT_OUT_8821C 0
+#define BIT_MASK_DSS_2_COUNT_OUT_8821C 0xfffff
+#define BIT_DSS_2_COUNT_OUT_8821C(x) \
+ (((x) & BIT_MASK_DSS_2_COUNT_OUT_8821C) \
+ << BIT_SHIFT_DSS_2_COUNT_OUT_8821C)
+#define BITS_DSS_2_COUNT_OUT_8821C \
+ (BIT_MASK_DSS_2_COUNT_OUT_8821C << BIT_SHIFT_DSS_2_COUNT_OUT_8821C)
+#define BIT_CLEAR_DSS_2_COUNT_OUT_8821C(x) ((x) & (~BITS_DSS_2_COUNT_OUT_8821C))
+#define BIT_GET_DSS_2_COUNT_OUT_8821C(x) \
+ (((x) >> BIT_SHIFT_DSS_2_COUNT_OUT_8821C) & \
+ BIT_MASK_DSS_2_COUNT_OUT_8821C)
+#define BIT_SET_DSS_2_COUNT_OUT_8821C(x, v) \
+ (BIT_CLEAR_DSS_2_COUNT_OUT_8821C(x) | BIT_DSS_2_COUNT_OUT_8821C(v))
+
+/* 2 REG_SPEED_SENSOR4_8821C */
+#define BIT_DSS_3_RST_N_8821C BIT(31)
+#define BIT_DSS_3_SPEED_EN_8821C BIT(30)
+#define BIT_DSS_3_WIRE_SEL_8821C BIT(29)
+#define BIT_DSS_ENCLK_8821C BIT(28)
+
+#define BIT_SHIFT_DSS_3_RO_SEL_8821C 24
+#define BIT_MASK_DSS_3_RO_SEL_8821C 0x7
+#define BIT_DSS_3_RO_SEL_8821C(x) \
+ (((x) & BIT_MASK_DSS_3_RO_SEL_8821C) << BIT_SHIFT_DSS_3_RO_SEL_8821C)
+#define BITS_DSS_3_RO_SEL_8821C \
+ (BIT_MASK_DSS_3_RO_SEL_8821C << BIT_SHIFT_DSS_3_RO_SEL_8821C)
+#define BIT_CLEAR_DSS_3_RO_SEL_8821C(x) ((x) & (~BITS_DSS_3_RO_SEL_8821C))
+#define BIT_GET_DSS_3_RO_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_DSS_3_RO_SEL_8821C) & BIT_MASK_DSS_3_RO_SEL_8821C)
+#define BIT_SET_DSS_3_RO_SEL_8821C(x, v) \
+ (BIT_CLEAR_DSS_3_RO_SEL_8821C(x) | BIT_DSS_3_RO_SEL_8821C(v))
+
+#define BIT_SHIFT_DSS_3_DATA_IN_8821C 0
+#define BIT_MASK_DSS_3_DATA_IN_8821C 0xfffff
+#define BIT_DSS_3_DATA_IN_8821C(x) \
+ (((x) & BIT_MASK_DSS_3_DATA_IN_8821C) << BIT_SHIFT_DSS_3_DATA_IN_8821C)
+#define BITS_DSS_3_DATA_IN_8821C \
+ (BIT_MASK_DSS_3_DATA_IN_8821C << BIT_SHIFT_DSS_3_DATA_IN_8821C)
+#define BIT_CLEAR_DSS_3_DATA_IN_8821C(x) ((x) & (~BITS_DSS_3_DATA_IN_8821C))
+#define BIT_GET_DSS_3_DATA_IN_8821C(x) \
+ (((x) >> BIT_SHIFT_DSS_3_DATA_IN_8821C) & BIT_MASK_DSS_3_DATA_IN_8821C)
+#define BIT_SET_DSS_3_DATA_IN_8821C(x, v) \
+ (BIT_CLEAR_DSS_3_DATA_IN_8821C(x) | BIT_DSS_3_DATA_IN_8821C(v))
+
+/* 2 REG_SPEED_SENSOR5_8821C */
+#define BIT_DSS_3_READY_8821C BIT(31)
+#define BIT_DSS_3_WSORT_GO_8821C BIT(30)
+
+#define BIT_SHIFT_DSS_3_COUNT_OUT_8821C 0
+#define BIT_MASK_DSS_3_COUNT_OUT_8821C 0xfffff
+#define BIT_DSS_3_COUNT_OUT_8821C(x) \
+ (((x) & BIT_MASK_DSS_3_COUNT_OUT_8821C) \
+ << BIT_SHIFT_DSS_3_COUNT_OUT_8821C)
+#define BITS_DSS_3_COUNT_OUT_8821C \
+ (BIT_MASK_DSS_3_COUNT_OUT_8821C << BIT_SHIFT_DSS_3_COUNT_OUT_8821C)
+#define BIT_CLEAR_DSS_3_COUNT_OUT_8821C(x) ((x) & (~BITS_DSS_3_COUNT_OUT_8821C))
+#define BIT_GET_DSS_3_COUNT_OUT_8821C(x) \
+ (((x) >> BIT_SHIFT_DSS_3_COUNT_OUT_8821C) & \
+ BIT_MASK_DSS_3_COUNT_OUT_8821C)
+#define BIT_SET_DSS_3_COUNT_OUT_8821C(x, v) \
+ (BIT_CLEAR_DSS_3_COUNT_OUT_8821C(x) | BIT_DSS_3_COUNT_OUT_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_COUNTER_CTRL_8821C */
+
+#define BIT_SHIFT_COUNTER_BASE_8821C 16
+#define BIT_MASK_COUNTER_BASE_8821C 0x1fff
+#define BIT_COUNTER_BASE_8821C(x) \
+ (((x) & BIT_MASK_COUNTER_BASE_8821C) << BIT_SHIFT_COUNTER_BASE_8821C)
+#define BITS_COUNTER_BASE_8821C \
+ (BIT_MASK_COUNTER_BASE_8821C << BIT_SHIFT_COUNTER_BASE_8821C)
+#define BIT_CLEAR_COUNTER_BASE_8821C(x) ((x) & (~BITS_COUNTER_BASE_8821C))
+#define BIT_GET_COUNTER_BASE_8821C(x) \
+ (((x) >> BIT_SHIFT_COUNTER_BASE_8821C) & BIT_MASK_COUNTER_BASE_8821C)
+#define BIT_SET_COUNTER_BASE_8821C(x, v) \
+ (BIT_CLEAR_COUNTER_BASE_8821C(x) | BIT_COUNTER_BASE_8821C(v))
+
+#define BIT_EN_RTS_REQ_8821C BIT(9)
+#define BIT_EN_EDCA_REQ_8821C BIT(8)
+#define BIT_EN_PTCL_REQ_8821C BIT(7)
+#define BIT_EN_SCH_REQ_8821C BIT(6)
+#define BIT_USB_COUNT_EN_8821C BIT(5)
+#define BIT_PCIE_COUNT_EN_8821C BIT(4)
+#define BIT_RQPN_COUNT_EN_8821C BIT(3)
+#define BIT_RDE_COUNT_EN_8821C BIT(2)
+#define BIT_TDE_COUNT_EN_8821C BIT(1)
+#define BIT_DISABLE_COUNTER_8821C BIT(0)
+
+/* 2 REG_COUNTER_THRESHOLD_8821C */
+#define BIT_SEL_ALL_MACID_8821C BIT(31)
+
+#define BIT_SHIFT_COUNTER_MACID_8821C 24
+#define BIT_MASK_COUNTER_MACID_8821C 0x7f
+#define BIT_COUNTER_MACID_8821C(x) \
+ (((x) & BIT_MASK_COUNTER_MACID_8821C) << BIT_SHIFT_COUNTER_MACID_8821C)
+#define BITS_COUNTER_MACID_8821C \
+ (BIT_MASK_COUNTER_MACID_8821C << BIT_SHIFT_COUNTER_MACID_8821C)
+#define BIT_CLEAR_COUNTER_MACID_8821C(x) ((x) & (~BITS_COUNTER_MACID_8821C))
+#define BIT_GET_COUNTER_MACID_8821C(x) \
+ (((x) >> BIT_SHIFT_COUNTER_MACID_8821C) & BIT_MASK_COUNTER_MACID_8821C)
+#define BIT_SET_COUNTER_MACID_8821C(x, v) \
+ (BIT_CLEAR_COUNTER_MACID_8821C(x) | BIT_COUNTER_MACID_8821C(v))
+
+#define BIT_SHIFT_AGG_VALUE2_8821C 16
+#define BIT_MASK_AGG_VALUE2_8821C 0x7f
+#define BIT_AGG_VALUE2_8821C(x) \
+ (((x) & BIT_MASK_AGG_VALUE2_8821C) << BIT_SHIFT_AGG_VALUE2_8821C)
+#define BITS_AGG_VALUE2_8821C \
+ (BIT_MASK_AGG_VALUE2_8821C << BIT_SHIFT_AGG_VALUE2_8821C)
+#define BIT_CLEAR_AGG_VALUE2_8821C(x) ((x) & (~BITS_AGG_VALUE2_8821C))
+#define BIT_GET_AGG_VALUE2_8821C(x) \
+ (((x) >> BIT_SHIFT_AGG_VALUE2_8821C) & BIT_MASK_AGG_VALUE2_8821C)
+#define BIT_SET_AGG_VALUE2_8821C(x, v) \
+ (BIT_CLEAR_AGG_VALUE2_8821C(x) | BIT_AGG_VALUE2_8821C(v))
+
+#define BIT_SHIFT_AGG_VALUE1_8821C 8
+#define BIT_MASK_AGG_VALUE1_8821C 0x7f
+#define BIT_AGG_VALUE1_8821C(x) \
+ (((x) & BIT_MASK_AGG_VALUE1_8821C) << BIT_SHIFT_AGG_VALUE1_8821C)
+#define BITS_AGG_VALUE1_8821C \
+ (BIT_MASK_AGG_VALUE1_8821C << BIT_SHIFT_AGG_VALUE1_8821C)
+#define BIT_CLEAR_AGG_VALUE1_8821C(x) ((x) & (~BITS_AGG_VALUE1_8821C))
+#define BIT_GET_AGG_VALUE1_8821C(x) \
+ (((x) >> BIT_SHIFT_AGG_VALUE1_8821C) & BIT_MASK_AGG_VALUE1_8821C)
+#define BIT_SET_AGG_VALUE1_8821C(x, v) \
+ (BIT_CLEAR_AGG_VALUE1_8821C(x) | BIT_AGG_VALUE1_8821C(v))
+
+#define BIT_SHIFT_AGG_VALUE0_8821C 0
+#define BIT_MASK_AGG_VALUE0_8821C 0x7f
+#define BIT_AGG_VALUE0_8821C(x) \
+ (((x) & BIT_MASK_AGG_VALUE0_8821C) << BIT_SHIFT_AGG_VALUE0_8821C)
+#define BITS_AGG_VALUE0_8821C \
+ (BIT_MASK_AGG_VALUE0_8821C << BIT_SHIFT_AGG_VALUE0_8821C)
+#define BIT_CLEAR_AGG_VALUE0_8821C(x) ((x) & (~BITS_AGG_VALUE0_8821C))
+#define BIT_GET_AGG_VALUE0_8821C(x) \
+ (((x) >> BIT_SHIFT_AGG_VALUE0_8821C) & BIT_MASK_AGG_VALUE0_8821C)
+#define BIT_SET_AGG_VALUE0_8821C(x, v) \
+ (BIT_CLEAR_AGG_VALUE0_8821C(x) | BIT_AGG_VALUE0_8821C(v))
+
+/* 2 REG_COUNTER_SET_8821C */
+
+#define BIT_SHIFT_REQUEST_RESET_8821C 16
+#define BIT_MASK_REQUEST_RESET_8821C 0xffff
+#define BIT_REQUEST_RESET_8821C(x) \
+ (((x) & BIT_MASK_REQUEST_RESET_8821C) << BIT_SHIFT_REQUEST_RESET_8821C)
+#define BITS_REQUEST_RESET_8821C \
+ (BIT_MASK_REQUEST_RESET_8821C << BIT_SHIFT_REQUEST_RESET_8821C)
+#define BIT_CLEAR_REQUEST_RESET_8821C(x) ((x) & (~BITS_REQUEST_RESET_8821C))
+#define BIT_GET_REQUEST_RESET_8821C(x) \
+ (((x) >> BIT_SHIFT_REQUEST_RESET_8821C) & BIT_MASK_REQUEST_RESET_8821C)
+#define BIT_SET_REQUEST_RESET_8821C(x, v) \
+ (BIT_CLEAR_REQUEST_RESET_8821C(x) | BIT_REQUEST_RESET_8821C(v))
+
+#define BIT_SHIFT_REQUEST_START_8821C 0
+#define BIT_MASK_REQUEST_START_8821C 0xffff
+#define BIT_REQUEST_START_8821C(x) \
+ (((x) & BIT_MASK_REQUEST_START_8821C) << BIT_SHIFT_REQUEST_START_8821C)
+#define BITS_REQUEST_START_8821C \
+ (BIT_MASK_REQUEST_START_8821C << BIT_SHIFT_REQUEST_START_8821C)
+#define BIT_CLEAR_REQUEST_START_8821C(x) ((x) & (~BITS_REQUEST_START_8821C))
+#define BIT_GET_REQUEST_START_8821C(x) \
+ (((x) >> BIT_SHIFT_REQUEST_START_8821C) & BIT_MASK_REQUEST_START_8821C)
+#define BIT_SET_REQUEST_START_8821C(x, v) \
+ (BIT_CLEAR_REQUEST_START_8821C(x) | BIT_REQUEST_START_8821C(v))
+
+/* 2 REG_COUNTER_OVERFLOW_8821C */
+
+#define BIT_SHIFT_CNT_OVF_REG_8821C 0
+#define BIT_MASK_CNT_OVF_REG_8821C 0xffff
+#define BIT_CNT_OVF_REG_8821C(x) \
+ (((x) & BIT_MASK_CNT_OVF_REG_8821C) << BIT_SHIFT_CNT_OVF_REG_8821C)
+#define BITS_CNT_OVF_REG_8821C \
+ (BIT_MASK_CNT_OVF_REG_8821C << BIT_SHIFT_CNT_OVF_REG_8821C)
+#define BIT_CLEAR_CNT_OVF_REG_8821C(x) ((x) & (~BITS_CNT_OVF_REG_8821C))
+#define BIT_GET_CNT_OVF_REG_8821C(x) \
+ (((x) >> BIT_SHIFT_CNT_OVF_REG_8821C) & BIT_MASK_CNT_OVF_REG_8821C)
+#define BIT_SET_CNT_OVF_REG_8821C(x, v) \
+ (BIT_CLEAR_CNT_OVF_REG_8821C(x) | BIT_CNT_OVF_REG_8821C(v))
+
+/* 2 REG_TXDMA_LEN_THRESHOLD_8821C */
+
+#define BIT_SHIFT_TDE_LEN_TH1_8821C 16
+#define BIT_MASK_TDE_LEN_TH1_8821C 0xffff
+#define BIT_TDE_LEN_TH1_8821C(x) \
+ (((x) & BIT_MASK_TDE_LEN_TH1_8821C) << BIT_SHIFT_TDE_LEN_TH1_8821C)
+#define BITS_TDE_LEN_TH1_8821C \
+ (BIT_MASK_TDE_LEN_TH1_8821C << BIT_SHIFT_TDE_LEN_TH1_8821C)
+#define BIT_CLEAR_TDE_LEN_TH1_8821C(x) ((x) & (~BITS_TDE_LEN_TH1_8821C))
+#define BIT_GET_TDE_LEN_TH1_8821C(x) \
+ (((x) >> BIT_SHIFT_TDE_LEN_TH1_8821C) & BIT_MASK_TDE_LEN_TH1_8821C)
+#define BIT_SET_TDE_LEN_TH1_8821C(x, v) \
+ (BIT_CLEAR_TDE_LEN_TH1_8821C(x) | BIT_TDE_LEN_TH1_8821C(v))
+
+#define BIT_SHIFT_TDE_LEN_TH0_8821C 0
+#define BIT_MASK_TDE_LEN_TH0_8821C 0xffff
+#define BIT_TDE_LEN_TH0_8821C(x) \
+ (((x) & BIT_MASK_TDE_LEN_TH0_8821C) << BIT_SHIFT_TDE_LEN_TH0_8821C)
+#define BITS_TDE_LEN_TH0_8821C \
+ (BIT_MASK_TDE_LEN_TH0_8821C << BIT_SHIFT_TDE_LEN_TH0_8821C)
+#define BIT_CLEAR_TDE_LEN_TH0_8821C(x) ((x) & (~BITS_TDE_LEN_TH0_8821C))
+#define BIT_GET_TDE_LEN_TH0_8821C(x) \
+ (((x) >> BIT_SHIFT_TDE_LEN_TH0_8821C) & BIT_MASK_TDE_LEN_TH0_8821C)
+#define BIT_SET_TDE_LEN_TH0_8821C(x, v) \
+ (BIT_CLEAR_TDE_LEN_TH0_8821C(x) | BIT_TDE_LEN_TH0_8821C(v))
+
+/* 2 REG_RXDMA_LEN_THRESHOLD_8821C */
+
+#define BIT_SHIFT_RDE_LEN_TH1_8821C 16
+#define BIT_MASK_RDE_LEN_TH1_8821C 0xffff
+#define BIT_RDE_LEN_TH1_8821C(x) \
+ (((x) & BIT_MASK_RDE_LEN_TH1_8821C) << BIT_SHIFT_RDE_LEN_TH1_8821C)
+#define BITS_RDE_LEN_TH1_8821C \
+ (BIT_MASK_RDE_LEN_TH1_8821C << BIT_SHIFT_RDE_LEN_TH1_8821C)
+#define BIT_CLEAR_RDE_LEN_TH1_8821C(x) ((x) & (~BITS_RDE_LEN_TH1_8821C))
+#define BIT_GET_RDE_LEN_TH1_8821C(x) \
+ (((x) >> BIT_SHIFT_RDE_LEN_TH1_8821C) & BIT_MASK_RDE_LEN_TH1_8821C)
+#define BIT_SET_RDE_LEN_TH1_8821C(x, v) \
+ (BIT_CLEAR_RDE_LEN_TH1_8821C(x) | BIT_RDE_LEN_TH1_8821C(v))
+
+#define BIT_SHIFT_RDE_LEN_TH0_8821C 0
+#define BIT_MASK_RDE_LEN_TH0_8821C 0xffff
+#define BIT_RDE_LEN_TH0_8821C(x) \
+ (((x) & BIT_MASK_RDE_LEN_TH0_8821C) << BIT_SHIFT_RDE_LEN_TH0_8821C)
+#define BITS_RDE_LEN_TH0_8821C \
+ (BIT_MASK_RDE_LEN_TH0_8821C << BIT_SHIFT_RDE_LEN_TH0_8821C)
+#define BIT_CLEAR_RDE_LEN_TH0_8821C(x) ((x) & (~BITS_RDE_LEN_TH0_8821C))
+#define BIT_GET_RDE_LEN_TH0_8821C(x) \
+ (((x) >> BIT_SHIFT_RDE_LEN_TH0_8821C) & BIT_MASK_RDE_LEN_TH0_8821C)
+#define BIT_SET_RDE_LEN_TH0_8821C(x, v) \
+ (BIT_CLEAR_RDE_LEN_TH0_8821C(x) | BIT_RDE_LEN_TH0_8821C(v))
+
+/* 2 REG_PCIE_EXEC_TIME_THRESHOLD_8821C */
+
+#define BIT_SHIFT_COUNT_INT_SEL_8821C 16
+#define BIT_MASK_COUNT_INT_SEL_8821C 0x3
+#define BIT_COUNT_INT_SEL_8821C(x) \
+ (((x) & BIT_MASK_COUNT_INT_SEL_8821C) << BIT_SHIFT_COUNT_INT_SEL_8821C)
+#define BITS_COUNT_INT_SEL_8821C \
+ (BIT_MASK_COUNT_INT_SEL_8821C << BIT_SHIFT_COUNT_INT_SEL_8821C)
+#define BIT_CLEAR_COUNT_INT_SEL_8821C(x) ((x) & (~BITS_COUNT_INT_SEL_8821C))
+#define BIT_GET_COUNT_INT_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_COUNT_INT_SEL_8821C) & BIT_MASK_COUNT_INT_SEL_8821C)
+#define BIT_SET_COUNT_INT_SEL_8821C(x, v) \
+ (BIT_CLEAR_COUNT_INT_SEL_8821C(x) | BIT_COUNT_INT_SEL_8821C(v))
+
+#define BIT_SHIFT_EXEC_TIME_TH_8821C 0
+#define BIT_MASK_EXEC_TIME_TH_8821C 0xffff
+#define BIT_EXEC_TIME_TH_8821C(x) \
+ (((x) & BIT_MASK_EXEC_TIME_TH_8821C) << BIT_SHIFT_EXEC_TIME_TH_8821C)
+#define BITS_EXEC_TIME_TH_8821C \
+ (BIT_MASK_EXEC_TIME_TH_8821C << BIT_SHIFT_EXEC_TIME_TH_8821C)
+#define BIT_CLEAR_EXEC_TIME_TH_8821C(x) ((x) & (~BITS_EXEC_TIME_TH_8821C))
+#define BIT_GET_EXEC_TIME_TH_8821C(x) \
+ (((x) >> BIT_SHIFT_EXEC_TIME_TH_8821C) & BIT_MASK_EXEC_TIME_TH_8821C)
+#define BIT_SET_EXEC_TIME_TH_8821C(x, v) \
+ (BIT_CLEAR_EXEC_TIME_TH_8821C(x) | BIT_EXEC_TIME_TH_8821C(v))
+
+/* 2 REG_FT2IMR_8821C */
+#define BIT_FS_CLI3_RX_UAPSDMD1_EN_8821C BIT(31)
+#define BIT_FS_CLI3_RX_UAPSDMD0_EN_8821C BIT(30)
+#define BIT_FS_CLI3_TRIGGER_PKT_EN_8821C BIT(29)
+#define BIT_FS_CLI3_EOSP_INT_EN_8821C BIT(28)
+#define BIT_FS_CLI2_RX_UAPSDMD1_EN_8821C BIT(27)
+#define BIT_FS_CLI2_RX_UAPSDMD0_EN_8821C BIT(26)
+#define BIT_FS_CLI2_TRIGGER_PKT_EN_8821C BIT(25)
+#define BIT_FS_CLI2_EOSP_INT_EN_8821C BIT(24)
+#define BIT_FS_CLI1_RX_UAPSDMD1_EN_8821C BIT(23)
+#define BIT_FS_CLI1_RX_UAPSDMD0_EN_8821C BIT(22)
+#define BIT_FS_CLI1_TRIGGER_PKT_EN_8821C BIT(21)
+#define BIT_FS_CLI1_EOSP_INT_EN_8821C BIT(20)
+#define BIT_FS_CLI0_RX_UAPSDMD1_EN_8821C BIT(19)
+#define BIT_FS_CLI0_RX_UAPSDMD0_EN_8821C BIT(18)
+#define BIT_FS_CLI0_TRIGGER_PKT_EN_8821C BIT(17)
#define BIT_FS_CLI0_EOSP_INT_EN_8821C BIT(16)
#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_EN_8821C BIT(9)
#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_EN_8821C BIT(8)
@@ -3119,88 +5466,438 @@
#define BIT_FS_CLI0_TX_NULL1_INT_8821C BIT(1)
#define BIT_FS_CLI0_TX_NULL0_INT_8821C BIT(0)
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
/* 2 REG_MSG2_8821C */
#define BIT_SHIFT_FW_MSG2_8821C 0
#define BIT_MASK_FW_MSG2_8821C 0xffffffffL
-#define BIT_FW_MSG2_8821C(x) (((x) & BIT_MASK_FW_MSG2_8821C) << BIT_SHIFT_FW_MSG2_8821C)
-#define BIT_GET_FW_MSG2_8821C(x) (((x) >> BIT_SHIFT_FW_MSG2_8821C) & BIT_MASK_FW_MSG2_8821C)
-
+#define BIT_FW_MSG2_8821C(x) \
+ (((x) & BIT_MASK_FW_MSG2_8821C) << BIT_SHIFT_FW_MSG2_8821C)
+#define BITS_FW_MSG2_8821C (BIT_MASK_FW_MSG2_8821C << BIT_SHIFT_FW_MSG2_8821C)
+#define BIT_CLEAR_FW_MSG2_8821C(x) ((x) & (~BITS_FW_MSG2_8821C))
+#define BIT_GET_FW_MSG2_8821C(x) \
+ (((x) >> BIT_SHIFT_FW_MSG2_8821C) & BIT_MASK_FW_MSG2_8821C)
+#define BIT_SET_FW_MSG2_8821C(x, v) \
+ (BIT_CLEAR_FW_MSG2_8821C(x) | BIT_FW_MSG2_8821C(v))
/* 2 REG_MSG3_8821C */
#define BIT_SHIFT_FW_MSG3_8821C 0
#define BIT_MASK_FW_MSG3_8821C 0xffffffffL
-#define BIT_FW_MSG3_8821C(x) (((x) & BIT_MASK_FW_MSG3_8821C) << BIT_SHIFT_FW_MSG3_8821C)
-#define BIT_GET_FW_MSG3_8821C(x) (((x) >> BIT_SHIFT_FW_MSG3_8821C) & BIT_MASK_FW_MSG3_8821C)
-
+#define BIT_FW_MSG3_8821C(x) \
+ (((x) & BIT_MASK_FW_MSG3_8821C) << BIT_SHIFT_FW_MSG3_8821C)
+#define BITS_FW_MSG3_8821C (BIT_MASK_FW_MSG3_8821C << BIT_SHIFT_FW_MSG3_8821C)
+#define BIT_CLEAR_FW_MSG3_8821C(x) ((x) & (~BITS_FW_MSG3_8821C))
+#define BIT_GET_FW_MSG3_8821C(x) \
+ (((x) >> BIT_SHIFT_FW_MSG3_8821C) & BIT_MASK_FW_MSG3_8821C)
+#define BIT_SET_FW_MSG3_8821C(x, v) \
+ (BIT_CLEAR_FW_MSG3_8821C(x) | BIT_FW_MSG3_8821C(v))
/* 2 REG_MSG4_8821C */
#define BIT_SHIFT_FW_MSG4_8821C 0
#define BIT_MASK_FW_MSG4_8821C 0xffffffffL
-#define BIT_FW_MSG4_8821C(x) (((x) & BIT_MASK_FW_MSG4_8821C) << BIT_SHIFT_FW_MSG4_8821C)
-#define BIT_GET_FW_MSG4_8821C(x) (((x) >> BIT_SHIFT_FW_MSG4_8821C) & BIT_MASK_FW_MSG4_8821C)
-
+#define BIT_FW_MSG4_8821C(x) \
+ (((x) & BIT_MASK_FW_MSG4_8821C) << BIT_SHIFT_FW_MSG4_8821C)
+#define BITS_FW_MSG4_8821C (BIT_MASK_FW_MSG4_8821C << BIT_SHIFT_FW_MSG4_8821C)
+#define BIT_CLEAR_FW_MSG4_8821C(x) ((x) & (~BITS_FW_MSG4_8821C))
+#define BIT_GET_FW_MSG4_8821C(x) \
+ (((x) >> BIT_SHIFT_FW_MSG4_8821C) & BIT_MASK_FW_MSG4_8821C)
+#define BIT_SET_FW_MSG4_8821C(x, v) \
+ (BIT_CLEAR_FW_MSG4_8821C(x) | BIT_FW_MSG4_8821C(v))
/* 2 REG_MSG5_8821C */
#define BIT_SHIFT_FW_MSG5_8821C 0
#define BIT_MASK_FW_MSG5_8821C 0xffffffffL
-#define BIT_FW_MSG5_8821C(x) (((x) & BIT_MASK_FW_MSG5_8821C) << BIT_SHIFT_FW_MSG5_8821C)
-#define BIT_GET_FW_MSG5_8821C(x) (((x) >> BIT_SHIFT_FW_MSG5_8821C) & BIT_MASK_FW_MSG5_8821C)
+#define BIT_FW_MSG5_8821C(x) \
+ (((x) & BIT_MASK_FW_MSG5_8821C) << BIT_SHIFT_FW_MSG5_8821C)
+#define BITS_FW_MSG5_8821C (BIT_MASK_FW_MSG5_8821C << BIT_SHIFT_FW_MSG5_8821C)
+#define BIT_CLEAR_FW_MSG5_8821C(x) ((x) & (~BITS_FW_MSG5_8821C))
+#define BIT_GET_FW_MSG5_8821C(x) \
+ (((x) >> BIT_SHIFT_FW_MSG5_8821C) & BIT_MASK_FW_MSG5_8821C)
+#define BIT_SET_FW_MSG5_8821C(x, v) \
+ (BIT_CLEAR_FW_MSG5_8821C(x) | BIT_FW_MSG5_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
/* 2 REG_NOT_VALID_8821C */
/* 2 REG_FIFOPAGE_CTRL_1_8821C */
+/* 2 REG_NOT_VALID_8821C */
+
#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8821C 16
#define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8821C 0xff
-#define BIT_TX_OQT_HE_FREE_SPACE_V1_8821C(x) (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8821C) << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8821C)
-#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1_8821C(x) (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8821C) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8821C)
+#define BIT_TX_OQT_HE_FREE_SPACE_V1_8821C(x) \
+ (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8821C) \
+ << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8821C)
+#define BITS_TX_OQT_HE_FREE_SPACE_V1_8821C \
+ (BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8821C \
+ << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8821C)
+#define BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8821C(x) \
+ ((x) & (~BITS_TX_OQT_HE_FREE_SPACE_V1_8821C))
+#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8821C) & \
+ BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8821C)
+#define BIT_SET_TX_OQT_HE_FREE_SPACE_V1_8821C(x, v) \
+ (BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8821C(x) | \
+ BIT_TX_OQT_HE_FREE_SPACE_V1_8821C(v))
+/* 2 REG_NOT_VALID_8821C */
#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8821C 0
#define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8821C 0xff
-#define BIT_TX_OQT_NL_FREE_SPACE_V1_8821C(x) (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8821C) << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8821C)
-#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1_8821C(x) (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8821C) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8821C)
-
+#define BIT_TX_OQT_NL_FREE_SPACE_V1_8821C(x) \
+ (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8821C) \
+ << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8821C)
+#define BITS_TX_OQT_NL_FREE_SPACE_V1_8821C \
+ (BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8821C \
+ << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8821C)
+#define BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8821C(x) \
+ ((x) & (~BITS_TX_OQT_NL_FREE_SPACE_V1_8821C))
+#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8821C) & \
+ BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8821C)
+#define BIT_SET_TX_OQT_NL_FREE_SPACE_V1_8821C(x, v) \
+ (BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8821C(x) | \
+ BIT_TX_OQT_NL_FREE_SPACE_V1_8821C(v))
/* 2 REG_FIFOPAGE_CTRL_2_8821C */
#define BIT_BCN_VALID_1_V1_8821C BIT(31)
+/* 2 REG_NOT_VALID_8821C */
+
#define BIT_SHIFT_BCN_HEAD_1_V1_8821C 16
#define BIT_MASK_BCN_HEAD_1_V1_8821C 0xfff
-#define BIT_BCN_HEAD_1_V1_8821C(x) (((x) & BIT_MASK_BCN_HEAD_1_V1_8821C) << BIT_SHIFT_BCN_HEAD_1_V1_8821C)
-#define BIT_GET_BCN_HEAD_1_V1_8821C(x) (((x) >> BIT_SHIFT_BCN_HEAD_1_V1_8821C) & BIT_MASK_BCN_HEAD_1_V1_8821C)
+#define BIT_BCN_HEAD_1_V1_8821C(x) \
+ (((x) & BIT_MASK_BCN_HEAD_1_V1_8821C) << BIT_SHIFT_BCN_HEAD_1_V1_8821C)
+#define BITS_BCN_HEAD_1_V1_8821C \
+ (BIT_MASK_BCN_HEAD_1_V1_8821C << BIT_SHIFT_BCN_HEAD_1_V1_8821C)
+#define BIT_CLEAR_BCN_HEAD_1_V1_8821C(x) ((x) & (~BITS_BCN_HEAD_1_V1_8821C))
+#define BIT_GET_BCN_HEAD_1_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_BCN_HEAD_1_V1_8821C) & BIT_MASK_BCN_HEAD_1_V1_8821C)
+#define BIT_SET_BCN_HEAD_1_V1_8821C(x, v) \
+ (BIT_CLEAR_BCN_HEAD_1_V1_8821C(x) | BIT_BCN_HEAD_1_V1_8821C(v))
#define BIT_BCN_VALID_V1_8821C BIT(15)
+/* 2 REG_NOT_VALID_8821C */
+
#define BIT_SHIFT_BCN_HEAD_V1_8821C 0
#define BIT_MASK_BCN_HEAD_V1_8821C 0xfff
-#define BIT_BCN_HEAD_V1_8821C(x) (((x) & BIT_MASK_BCN_HEAD_V1_8821C) << BIT_SHIFT_BCN_HEAD_V1_8821C)
-#define BIT_GET_BCN_HEAD_V1_8821C(x) (((x) >> BIT_SHIFT_BCN_HEAD_V1_8821C) & BIT_MASK_BCN_HEAD_V1_8821C)
-
+#define BIT_BCN_HEAD_V1_8821C(x) \
+ (((x) & BIT_MASK_BCN_HEAD_V1_8821C) << BIT_SHIFT_BCN_HEAD_V1_8821C)
+#define BITS_BCN_HEAD_V1_8821C \
+ (BIT_MASK_BCN_HEAD_V1_8821C << BIT_SHIFT_BCN_HEAD_V1_8821C)
+#define BIT_CLEAR_BCN_HEAD_V1_8821C(x) ((x) & (~BITS_BCN_HEAD_V1_8821C))
+#define BIT_GET_BCN_HEAD_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_BCN_HEAD_V1_8821C) & BIT_MASK_BCN_HEAD_V1_8821C)
+#define BIT_SET_BCN_HEAD_V1_8821C(x, v) \
+ (BIT_CLEAR_BCN_HEAD_V1_8821C(x) | BIT_BCN_HEAD_V1_8821C(v))
/* 2 REG_AUTO_LLT_V1_8821C */
#define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C 24
#define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C 0xff
-#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C(x) (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C) << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C)
-#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C(x) (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C)
-
+#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C(x) \
+ (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C) \
+ << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C)
+#define BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C \
+ (BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C \
+ << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C)
+#define BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C(x) \
+ ((x) & (~BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C))
+#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C) & \
+ BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C)
+#define BIT_SET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C(x, v) \
+ (BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C(x) | \
+ BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C(v))
#define BIT_SHIFT_LLT_FREE_PAGE_V1_8821C 8
#define BIT_MASK_LLT_FREE_PAGE_V1_8821C 0xffff
-#define BIT_LLT_FREE_PAGE_V1_8821C(x) (((x) & BIT_MASK_LLT_FREE_PAGE_V1_8821C) << BIT_SHIFT_LLT_FREE_PAGE_V1_8821C)
-#define BIT_GET_LLT_FREE_PAGE_V1_8821C(x) (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1_8821C) & BIT_MASK_LLT_FREE_PAGE_V1_8821C)
-
+#define BIT_LLT_FREE_PAGE_V1_8821C(x) \
+ (((x) & BIT_MASK_LLT_FREE_PAGE_V1_8821C) \
+ << BIT_SHIFT_LLT_FREE_PAGE_V1_8821C)
+#define BITS_LLT_FREE_PAGE_V1_8821C \
+ (BIT_MASK_LLT_FREE_PAGE_V1_8821C << BIT_SHIFT_LLT_FREE_PAGE_V1_8821C)
+#define BIT_CLEAR_LLT_FREE_PAGE_V1_8821C(x) \
+ ((x) & (~BITS_LLT_FREE_PAGE_V1_8821C))
+#define BIT_GET_LLT_FREE_PAGE_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1_8821C) & \
+ BIT_MASK_LLT_FREE_PAGE_V1_8821C)
+#define BIT_SET_LLT_FREE_PAGE_V1_8821C(x, v) \
+ (BIT_CLEAR_LLT_FREE_PAGE_V1_8821C(x) | BIT_LLT_FREE_PAGE_V1_8821C(v))
#define BIT_SHIFT_BLK_DESC_NUM_8821C 4
#define BIT_MASK_BLK_DESC_NUM_8821C 0xf
-#define BIT_BLK_DESC_NUM_8821C(x) (((x) & BIT_MASK_BLK_DESC_NUM_8821C) << BIT_SHIFT_BLK_DESC_NUM_8821C)
-#define BIT_GET_BLK_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_BLK_DESC_NUM_8821C) & BIT_MASK_BLK_DESC_NUM_8821C)
+#define BIT_BLK_DESC_NUM_8821C(x) \
+ (((x) & BIT_MASK_BLK_DESC_NUM_8821C) << BIT_SHIFT_BLK_DESC_NUM_8821C)
+#define BITS_BLK_DESC_NUM_8821C \
+ (BIT_MASK_BLK_DESC_NUM_8821C << BIT_SHIFT_BLK_DESC_NUM_8821C)
+#define BIT_CLEAR_BLK_DESC_NUM_8821C(x) ((x) & (~BITS_BLK_DESC_NUM_8821C))
+#define BIT_GET_BLK_DESC_NUM_8821C(x) \
+ (((x) >> BIT_SHIFT_BLK_DESC_NUM_8821C) & BIT_MASK_BLK_DESC_NUM_8821C)
+#define BIT_SET_BLK_DESC_NUM_8821C(x, v) \
+ (BIT_CLEAR_BLK_DESC_NUM_8821C(x) | BIT_BLK_DESC_NUM_8821C(v))
#define BIT_R_BCN_HEAD_SEL_8821C BIT(3)
#define BIT_R_EN_BCN_SW_HEAD_SEL_8821C BIT(2)
@@ -3215,9 +5912,19 @@
#define BIT_SHIFT_PG_UNDER_TH_V1_8821C 16
#define BIT_MASK_PG_UNDER_TH_V1_8821C 0xfff
-#define BIT_PG_UNDER_TH_V1_8821C(x) (((x) & BIT_MASK_PG_UNDER_TH_V1_8821C) << BIT_SHIFT_PG_UNDER_TH_V1_8821C)
-#define BIT_GET_PG_UNDER_TH_V1_8821C(x) (((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8821C) & BIT_MASK_PG_UNDER_TH_V1_8821C)
+#define BIT_PG_UNDER_TH_V1_8821C(x) \
+ (((x) & BIT_MASK_PG_UNDER_TH_V1_8821C) \
+ << BIT_SHIFT_PG_UNDER_TH_V1_8821C)
+#define BITS_PG_UNDER_TH_V1_8821C \
+ (BIT_MASK_PG_UNDER_TH_V1_8821C << BIT_SHIFT_PG_UNDER_TH_V1_8821C)
+#define BIT_CLEAR_PG_UNDER_TH_V1_8821C(x) ((x) & (~BITS_PG_UNDER_TH_V1_8821C))
+#define BIT_GET_PG_UNDER_TH_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8821C) & \
+ BIT_MASK_PG_UNDER_TH_V1_8821C)
+#define BIT_SET_PG_UNDER_TH_V1_8821C(x, v) \
+ (BIT_CLEAR_PG_UNDER_TH_V1_8821C(x) | BIT_PG_UNDER_TH_V1_8821C(v))
+/* 2 REG_NOT_VALID_8821C */
#define BIT_SDIO_TXDESC_CHKSUM_EN_8821C BIT(13)
#define BIT_RST_RDPTR_8821C BIT(12)
#define BIT_RST_WRPTR_8821C BIT(11)
@@ -3227,9 +5934,15 @@
#define BIT_SHIFT_CHECK_OFFSET_8821C 0
#define BIT_MASK_CHECK_OFFSET_8821C 0xff
-#define BIT_CHECK_OFFSET_8821C(x) (((x) & BIT_MASK_CHECK_OFFSET_8821C) << BIT_SHIFT_CHECK_OFFSET_8821C)
-#define BIT_GET_CHECK_OFFSET_8821C(x) (((x) >> BIT_SHIFT_CHECK_OFFSET_8821C) & BIT_MASK_CHECK_OFFSET_8821C)
-
+#define BIT_CHECK_OFFSET_8821C(x) \
+ (((x) & BIT_MASK_CHECK_OFFSET_8821C) << BIT_SHIFT_CHECK_OFFSET_8821C)
+#define BITS_CHECK_OFFSET_8821C \
+ (BIT_MASK_CHECK_OFFSET_8821C << BIT_SHIFT_CHECK_OFFSET_8821C)
+#define BIT_CLEAR_CHECK_OFFSET_8821C(x) ((x) & (~BITS_CHECK_OFFSET_8821C))
+#define BIT_GET_CHECK_OFFSET_8821C(x) \
+ (((x) >> BIT_SHIFT_CHECK_OFFSET_8821C) & BIT_MASK_CHECK_OFFSET_8821C)
+#define BIT_SET_CHECK_OFFSET_8821C(x, v) \
+ (BIT_CLEAR_CHECK_OFFSET_8821C(x) | BIT_CHECK_OFFSET_8821C(v))
/* 2 REG_TXDMA_STATUS_8821C */
#define BIT_TXPKTBUF_REQ_ERR_8821C BIT(18)
@@ -3255,74 +5968,146 @@
/* 2 REG_TX_DMA_DBG_8821C */
/* 2 REG_TQPNT1_8821C */
+#define BIT_HPQ_INT_EN_8821C BIT(31)
#define BIT_SHIFT_HPQ_HIGH_TH_V1_8821C 16
#define BIT_MASK_HPQ_HIGH_TH_V1_8821C 0xfff
-#define BIT_HPQ_HIGH_TH_V1_8821C(x) (((x) & BIT_MASK_HPQ_HIGH_TH_V1_8821C) << BIT_SHIFT_HPQ_HIGH_TH_V1_8821C)
-#define BIT_GET_HPQ_HIGH_TH_V1_8821C(x) (((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1_8821C) & BIT_MASK_HPQ_HIGH_TH_V1_8821C)
-
+#define BIT_HPQ_HIGH_TH_V1_8821C(x) \
+ (((x) & BIT_MASK_HPQ_HIGH_TH_V1_8821C) \
+ << BIT_SHIFT_HPQ_HIGH_TH_V1_8821C)
+#define BITS_HPQ_HIGH_TH_V1_8821C \
+ (BIT_MASK_HPQ_HIGH_TH_V1_8821C << BIT_SHIFT_HPQ_HIGH_TH_V1_8821C)
+#define BIT_CLEAR_HPQ_HIGH_TH_V1_8821C(x) ((x) & (~BITS_HPQ_HIGH_TH_V1_8821C))
+#define BIT_GET_HPQ_HIGH_TH_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1_8821C) & \
+ BIT_MASK_HPQ_HIGH_TH_V1_8821C)
+#define BIT_SET_HPQ_HIGH_TH_V1_8821C(x, v) \
+ (BIT_CLEAR_HPQ_HIGH_TH_V1_8821C(x) | BIT_HPQ_HIGH_TH_V1_8821C(v))
#define BIT_SHIFT_HPQ_LOW_TH_V1_8821C 0
#define BIT_MASK_HPQ_LOW_TH_V1_8821C 0xfff
-#define BIT_HPQ_LOW_TH_V1_8821C(x) (((x) & BIT_MASK_HPQ_LOW_TH_V1_8821C) << BIT_SHIFT_HPQ_LOW_TH_V1_8821C)
-#define BIT_GET_HPQ_LOW_TH_V1_8821C(x) (((x) >> BIT_SHIFT_HPQ_LOW_TH_V1_8821C) & BIT_MASK_HPQ_LOW_TH_V1_8821C)
-
+#define BIT_HPQ_LOW_TH_V1_8821C(x) \
+ (((x) & BIT_MASK_HPQ_LOW_TH_V1_8821C) << BIT_SHIFT_HPQ_LOW_TH_V1_8821C)
+#define BITS_HPQ_LOW_TH_V1_8821C \
+ (BIT_MASK_HPQ_LOW_TH_V1_8821C << BIT_SHIFT_HPQ_LOW_TH_V1_8821C)
+#define BIT_CLEAR_HPQ_LOW_TH_V1_8821C(x) ((x) & (~BITS_HPQ_LOW_TH_V1_8821C))
+#define BIT_GET_HPQ_LOW_TH_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_HPQ_LOW_TH_V1_8821C) & BIT_MASK_HPQ_LOW_TH_V1_8821C)
+#define BIT_SET_HPQ_LOW_TH_V1_8821C(x, v) \
+ (BIT_CLEAR_HPQ_LOW_TH_V1_8821C(x) | BIT_HPQ_LOW_TH_V1_8821C(v))
/* 2 REG_TQPNT2_8821C */
+#define BIT_NPQ_INT_EN_8821C BIT(31)
#define BIT_SHIFT_NPQ_HIGH_TH_V1_8821C 16
#define BIT_MASK_NPQ_HIGH_TH_V1_8821C 0xfff
-#define BIT_NPQ_HIGH_TH_V1_8821C(x) (((x) & BIT_MASK_NPQ_HIGH_TH_V1_8821C) << BIT_SHIFT_NPQ_HIGH_TH_V1_8821C)
-#define BIT_GET_NPQ_HIGH_TH_V1_8821C(x) (((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1_8821C) & BIT_MASK_NPQ_HIGH_TH_V1_8821C)
-
+#define BIT_NPQ_HIGH_TH_V1_8821C(x) \
+ (((x) & BIT_MASK_NPQ_HIGH_TH_V1_8821C) \
+ << BIT_SHIFT_NPQ_HIGH_TH_V1_8821C)
+#define BITS_NPQ_HIGH_TH_V1_8821C \
+ (BIT_MASK_NPQ_HIGH_TH_V1_8821C << BIT_SHIFT_NPQ_HIGH_TH_V1_8821C)
+#define BIT_CLEAR_NPQ_HIGH_TH_V1_8821C(x) ((x) & (~BITS_NPQ_HIGH_TH_V1_8821C))
+#define BIT_GET_NPQ_HIGH_TH_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1_8821C) & \
+ BIT_MASK_NPQ_HIGH_TH_V1_8821C)
+#define BIT_SET_NPQ_HIGH_TH_V1_8821C(x, v) \
+ (BIT_CLEAR_NPQ_HIGH_TH_V1_8821C(x) | BIT_NPQ_HIGH_TH_V1_8821C(v))
#define BIT_SHIFT_NPQ_LOW_TH_V1_8821C 0
#define BIT_MASK_NPQ_LOW_TH_V1_8821C 0xfff
-#define BIT_NPQ_LOW_TH_V1_8821C(x) (((x) & BIT_MASK_NPQ_LOW_TH_V1_8821C) << BIT_SHIFT_NPQ_LOW_TH_V1_8821C)
-#define BIT_GET_NPQ_LOW_TH_V1_8821C(x) (((x) >> BIT_SHIFT_NPQ_LOW_TH_V1_8821C) & BIT_MASK_NPQ_LOW_TH_V1_8821C)
-
+#define BIT_NPQ_LOW_TH_V1_8821C(x) \
+ (((x) & BIT_MASK_NPQ_LOW_TH_V1_8821C) << BIT_SHIFT_NPQ_LOW_TH_V1_8821C)
+#define BITS_NPQ_LOW_TH_V1_8821C \
+ (BIT_MASK_NPQ_LOW_TH_V1_8821C << BIT_SHIFT_NPQ_LOW_TH_V1_8821C)
+#define BIT_CLEAR_NPQ_LOW_TH_V1_8821C(x) ((x) & (~BITS_NPQ_LOW_TH_V1_8821C))
+#define BIT_GET_NPQ_LOW_TH_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_NPQ_LOW_TH_V1_8821C) & BIT_MASK_NPQ_LOW_TH_V1_8821C)
+#define BIT_SET_NPQ_LOW_TH_V1_8821C(x, v) \
+ (BIT_CLEAR_NPQ_LOW_TH_V1_8821C(x) | BIT_NPQ_LOW_TH_V1_8821C(v))
/* 2 REG_TQPNT3_8821C */
+#define BIT_LPQ_INT_EN_8821C BIT(31)
#define BIT_SHIFT_LPQ_HIGH_TH_V1_8821C 16
#define BIT_MASK_LPQ_HIGH_TH_V1_8821C 0xfff
-#define BIT_LPQ_HIGH_TH_V1_8821C(x) (((x) & BIT_MASK_LPQ_HIGH_TH_V1_8821C) << BIT_SHIFT_LPQ_HIGH_TH_V1_8821C)
-#define BIT_GET_LPQ_HIGH_TH_V1_8821C(x) (((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1_8821C) & BIT_MASK_LPQ_HIGH_TH_V1_8821C)
-
+#define BIT_LPQ_HIGH_TH_V1_8821C(x) \
+ (((x) & BIT_MASK_LPQ_HIGH_TH_V1_8821C) \
+ << BIT_SHIFT_LPQ_HIGH_TH_V1_8821C)
+#define BITS_LPQ_HIGH_TH_V1_8821C \
+ (BIT_MASK_LPQ_HIGH_TH_V1_8821C << BIT_SHIFT_LPQ_HIGH_TH_V1_8821C)
+#define BIT_CLEAR_LPQ_HIGH_TH_V1_8821C(x) ((x) & (~BITS_LPQ_HIGH_TH_V1_8821C))
+#define BIT_GET_LPQ_HIGH_TH_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1_8821C) & \
+ BIT_MASK_LPQ_HIGH_TH_V1_8821C)
+#define BIT_SET_LPQ_HIGH_TH_V1_8821C(x, v) \
+ (BIT_CLEAR_LPQ_HIGH_TH_V1_8821C(x) | BIT_LPQ_HIGH_TH_V1_8821C(v))
#define BIT_SHIFT_LPQ_LOW_TH_V1_8821C 0
#define BIT_MASK_LPQ_LOW_TH_V1_8821C 0xfff
-#define BIT_LPQ_LOW_TH_V1_8821C(x) (((x) & BIT_MASK_LPQ_LOW_TH_V1_8821C) << BIT_SHIFT_LPQ_LOW_TH_V1_8821C)
-#define BIT_GET_LPQ_LOW_TH_V1_8821C(x) (((x) >> BIT_SHIFT_LPQ_LOW_TH_V1_8821C) & BIT_MASK_LPQ_LOW_TH_V1_8821C)
-
+#define BIT_LPQ_LOW_TH_V1_8821C(x) \
+ (((x) & BIT_MASK_LPQ_LOW_TH_V1_8821C) << BIT_SHIFT_LPQ_LOW_TH_V1_8821C)
+#define BITS_LPQ_LOW_TH_V1_8821C \
+ (BIT_MASK_LPQ_LOW_TH_V1_8821C << BIT_SHIFT_LPQ_LOW_TH_V1_8821C)
+#define BIT_CLEAR_LPQ_LOW_TH_V1_8821C(x) ((x) & (~BITS_LPQ_LOW_TH_V1_8821C))
+#define BIT_GET_LPQ_LOW_TH_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_LPQ_LOW_TH_V1_8821C) & BIT_MASK_LPQ_LOW_TH_V1_8821C)
+#define BIT_SET_LPQ_LOW_TH_V1_8821C(x, v) \
+ (BIT_CLEAR_LPQ_LOW_TH_V1_8821C(x) | BIT_LPQ_LOW_TH_V1_8821C(v))
/* 2 REG_TQPNT4_8821C */
+#define BIT_EXQ_INT_EN_8821C BIT(31)
#define BIT_SHIFT_EXQ_HIGH_TH_V1_8821C 16
#define BIT_MASK_EXQ_HIGH_TH_V1_8821C 0xfff
-#define BIT_EXQ_HIGH_TH_V1_8821C(x) (((x) & BIT_MASK_EXQ_HIGH_TH_V1_8821C) << BIT_SHIFT_EXQ_HIGH_TH_V1_8821C)
-#define BIT_GET_EXQ_HIGH_TH_V1_8821C(x) (((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1_8821C) & BIT_MASK_EXQ_HIGH_TH_V1_8821C)
-
+#define BIT_EXQ_HIGH_TH_V1_8821C(x) \
+ (((x) & BIT_MASK_EXQ_HIGH_TH_V1_8821C) \
+ << BIT_SHIFT_EXQ_HIGH_TH_V1_8821C)
+#define BITS_EXQ_HIGH_TH_V1_8821C \
+ (BIT_MASK_EXQ_HIGH_TH_V1_8821C << BIT_SHIFT_EXQ_HIGH_TH_V1_8821C)
+#define BIT_CLEAR_EXQ_HIGH_TH_V1_8821C(x) ((x) & (~BITS_EXQ_HIGH_TH_V1_8821C))
+#define BIT_GET_EXQ_HIGH_TH_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1_8821C) & \
+ BIT_MASK_EXQ_HIGH_TH_V1_8821C)
+#define BIT_SET_EXQ_HIGH_TH_V1_8821C(x, v) \
+ (BIT_CLEAR_EXQ_HIGH_TH_V1_8821C(x) | BIT_EXQ_HIGH_TH_V1_8821C(v))
#define BIT_SHIFT_EXQ_LOW_TH_V1_8821C 0
#define BIT_MASK_EXQ_LOW_TH_V1_8821C 0xfff
-#define BIT_EXQ_LOW_TH_V1_8821C(x) (((x) & BIT_MASK_EXQ_LOW_TH_V1_8821C) << BIT_SHIFT_EXQ_LOW_TH_V1_8821C)
-#define BIT_GET_EXQ_LOW_TH_V1_8821C(x) (((x) >> BIT_SHIFT_EXQ_LOW_TH_V1_8821C) & BIT_MASK_EXQ_LOW_TH_V1_8821C)
-
+#define BIT_EXQ_LOW_TH_V1_8821C(x) \
+ (((x) & BIT_MASK_EXQ_LOW_TH_V1_8821C) << BIT_SHIFT_EXQ_LOW_TH_V1_8821C)
+#define BITS_EXQ_LOW_TH_V1_8821C \
+ (BIT_MASK_EXQ_LOW_TH_V1_8821C << BIT_SHIFT_EXQ_LOW_TH_V1_8821C)
+#define BIT_CLEAR_EXQ_LOW_TH_V1_8821C(x) ((x) & (~BITS_EXQ_LOW_TH_V1_8821C))
+#define BIT_GET_EXQ_LOW_TH_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_EXQ_LOW_TH_V1_8821C) & BIT_MASK_EXQ_LOW_TH_V1_8821C)
+#define BIT_SET_EXQ_LOW_TH_V1_8821C(x, v) \
+ (BIT_CLEAR_EXQ_LOW_TH_V1_8821C(x) | BIT_EXQ_LOW_TH_V1_8821C(v))
/* 2 REG_RQPN_CTRL_1_8821C */
#define BIT_SHIFT_TXPKTNUM_H_8821C 16
#define BIT_MASK_TXPKTNUM_H_8821C 0xffff
-#define BIT_TXPKTNUM_H_8821C(x) (((x) & BIT_MASK_TXPKTNUM_H_8821C) << BIT_SHIFT_TXPKTNUM_H_8821C)
-#define BIT_GET_TXPKTNUM_H_8821C(x) (((x) >> BIT_SHIFT_TXPKTNUM_H_8821C) & BIT_MASK_TXPKTNUM_H_8821C)
-
+#define BIT_TXPKTNUM_H_8821C(x) \
+ (((x) & BIT_MASK_TXPKTNUM_H_8821C) << BIT_SHIFT_TXPKTNUM_H_8821C)
+#define BITS_TXPKTNUM_H_8821C \
+ (BIT_MASK_TXPKTNUM_H_8821C << BIT_SHIFT_TXPKTNUM_H_8821C)
+#define BIT_CLEAR_TXPKTNUM_H_8821C(x) ((x) & (~BITS_TXPKTNUM_H_8821C))
+#define BIT_GET_TXPKTNUM_H_8821C(x) \
+ (((x) >> BIT_SHIFT_TXPKTNUM_H_8821C) & BIT_MASK_TXPKTNUM_H_8821C)
+#define BIT_SET_TXPKTNUM_H_8821C(x, v) \
+ (BIT_CLEAR_TXPKTNUM_H_8821C(x) | BIT_TXPKTNUM_H_8821C(v))
#define BIT_SHIFT_TXPKTNUM_V2_8821C 0
#define BIT_MASK_TXPKTNUM_V2_8821C 0xffff
-#define BIT_TXPKTNUM_V2_8821C(x) (((x) & BIT_MASK_TXPKTNUM_V2_8821C) << BIT_SHIFT_TXPKTNUM_V2_8821C)
-#define BIT_GET_TXPKTNUM_V2_8821C(x) (((x) >> BIT_SHIFT_TXPKTNUM_V2_8821C) & BIT_MASK_TXPKTNUM_V2_8821C)
-
+#define BIT_TXPKTNUM_V2_8821C(x) \
+ (((x) & BIT_MASK_TXPKTNUM_V2_8821C) << BIT_SHIFT_TXPKTNUM_V2_8821C)
+#define BITS_TXPKTNUM_V2_8821C \
+ (BIT_MASK_TXPKTNUM_V2_8821C << BIT_SHIFT_TXPKTNUM_V2_8821C)
+#define BIT_CLEAR_TXPKTNUM_V2_8821C(x) ((x) & (~BITS_TXPKTNUM_V2_8821C))
+#define BIT_GET_TXPKTNUM_V2_8821C(x) \
+ (((x) >> BIT_SHIFT_TXPKTNUM_V2_8821C) & BIT_MASK_TXPKTNUM_V2_8821C)
+#define BIT_SET_TXPKTNUM_V2_8821C(x, v) \
+ (BIT_CLEAR_TXPKTNUM_V2_8821C(x) | BIT_TXPKTNUM_V2_8821C(v))
/* 2 REG_RQPN_CTRL_2_8821C */
#define BIT_LD_RQPN_8821C BIT(31)
@@ -3334,111 +6119,211 @@
#define BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8821C 0
#define BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8821C 0xfff
-#define BIT_SDIO_TXAGG_ALIGN_SIZE_8821C(x) (((x) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8821C) << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8821C)
-#define BIT_GET_SDIO_TXAGG_ALIGN_SIZE_8821C(x) (((x) >> BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8821C) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8821C)
-
+#define BIT_SDIO_TXAGG_ALIGN_SIZE_8821C(x) \
+ (((x) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8821C) \
+ << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8821C)
+#define BITS_SDIO_TXAGG_ALIGN_SIZE_8821C \
+ (BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8821C \
+ << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8821C)
+#define BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_8821C(x) \
+ ((x) & (~BITS_SDIO_TXAGG_ALIGN_SIZE_8821C))
+#define BIT_GET_SDIO_TXAGG_ALIGN_SIZE_8821C(x) \
+ (((x) >> BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8821C) & \
+ BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8821C)
+#define BIT_SET_SDIO_TXAGG_ALIGN_SIZE_8821C(x, v) \
+ (BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_8821C(x) | \
+ BIT_SDIO_TXAGG_ALIGN_SIZE_8821C(v))
/* 2 REG_FIFOPAGE_INFO_1_8821C */
#define BIT_SHIFT_HPQ_AVAL_PG_V1_8821C 16
#define BIT_MASK_HPQ_AVAL_PG_V1_8821C 0xfff
-#define BIT_HPQ_AVAL_PG_V1_8821C(x) (((x) & BIT_MASK_HPQ_AVAL_PG_V1_8821C) << BIT_SHIFT_HPQ_AVAL_PG_V1_8821C)
-#define BIT_GET_HPQ_AVAL_PG_V1_8821C(x) (((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1_8821C) & BIT_MASK_HPQ_AVAL_PG_V1_8821C)
-
+#define BIT_HPQ_AVAL_PG_V1_8821C(x) \
+ (((x) & BIT_MASK_HPQ_AVAL_PG_V1_8821C) \
+ << BIT_SHIFT_HPQ_AVAL_PG_V1_8821C)
+#define BITS_HPQ_AVAL_PG_V1_8821C \
+ (BIT_MASK_HPQ_AVAL_PG_V1_8821C << BIT_SHIFT_HPQ_AVAL_PG_V1_8821C)
+#define BIT_CLEAR_HPQ_AVAL_PG_V1_8821C(x) ((x) & (~BITS_HPQ_AVAL_PG_V1_8821C))
+#define BIT_GET_HPQ_AVAL_PG_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1_8821C) & \
+ BIT_MASK_HPQ_AVAL_PG_V1_8821C)
+#define BIT_SET_HPQ_AVAL_PG_V1_8821C(x, v) \
+ (BIT_CLEAR_HPQ_AVAL_PG_V1_8821C(x) | BIT_HPQ_AVAL_PG_V1_8821C(v))
#define BIT_SHIFT_HPQ_V1_8821C 0
#define BIT_MASK_HPQ_V1_8821C 0xfff
-#define BIT_HPQ_V1_8821C(x) (((x) & BIT_MASK_HPQ_V1_8821C) << BIT_SHIFT_HPQ_V1_8821C)
-#define BIT_GET_HPQ_V1_8821C(x) (((x) >> BIT_SHIFT_HPQ_V1_8821C) & BIT_MASK_HPQ_V1_8821C)
-
+#define BIT_HPQ_V1_8821C(x) \
+ (((x) & BIT_MASK_HPQ_V1_8821C) << BIT_SHIFT_HPQ_V1_8821C)
+#define BITS_HPQ_V1_8821C (BIT_MASK_HPQ_V1_8821C << BIT_SHIFT_HPQ_V1_8821C)
+#define BIT_CLEAR_HPQ_V1_8821C(x) ((x) & (~BITS_HPQ_V1_8821C))
+#define BIT_GET_HPQ_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_HPQ_V1_8821C) & BIT_MASK_HPQ_V1_8821C)
+#define BIT_SET_HPQ_V1_8821C(x, v) \
+ (BIT_CLEAR_HPQ_V1_8821C(x) | BIT_HPQ_V1_8821C(v))
/* 2 REG_FIFOPAGE_INFO_2_8821C */
#define BIT_SHIFT_LPQ_AVAL_PG_V1_8821C 16
#define BIT_MASK_LPQ_AVAL_PG_V1_8821C 0xfff
-#define BIT_LPQ_AVAL_PG_V1_8821C(x) (((x) & BIT_MASK_LPQ_AVAL_PG_V1_8821C) << BIT_SHIFT_LPQ_AVAL_PG_V1_8821C)
-#define BIT_GET_LPQ_AVAL_PG_V1_8821C(x) (((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1_8821C) & BIT_MASK_LPQ_AVAL_PG_V1_8821C)
-
+#define BIT_LPQ_AVAL_PG_V1_8821C(x) \
+ (((x) & BIT_MASK_LPQ_AVAL_PG_V1_8821C) \
+ << BIT_SHIFT_LPQ_AVAL_PG_V1_8821C)
+#define BITS_LPQ_AVAL_PG_V1_8821C \
+ (BIT_MASK_LPQ_AVAL_PG_V1_8821C << BIT_SHIFT_LPQ_AVAL_PG_V1_8821C)
+#define BIT_CLEAR_LPQ_AVAL_PG_V1_8821C(x) ((x) & (~BITS_LPQ_AVAL_PG_V1_8821C))
+#define BIT_GET_LPQ_AVAL_PG_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1_8821C) & \
+ BIT_MASK_LPQ_AVAL_PG_V1_8821C)
+#define BIT_SET_LPQ_AVAL_PG_V1_8821C(x, v) \
+ (BIT_CLEAR_LPQ_AVAL_PG_V1_8821C(x) | BIT_LPQ_AVAL_PG_V1_8821C(v))
#define BIT_SHIFT_LPQ_V1_8821C 0
#define BIT_MASK_LPQ_V1_8821C 0xfff
-#define BIT_LPQ_V1_8821C(x) (((x) & BIT_MASK_LPQ_V1_8821C) << BIT_SHIFT_LPQ_V1_8821C)
-#define BIT_GET_LPQ_V1_8821C(x) (((x) >> BIT_SHIFT_LPQ_V1_8821C) & BIT_MASK_LPQ_V1_8821C)
-
+#define BIT_LPQ_V1_8821C(x) \
+ (((x) & BIT_MASK_LPQ_V1_8821C) << BIT_SHIFT_LPQ_V1_8821C)
+#define BITS_LPQ_V1_8821C (BIT_MASK_LPQ_V1_8821C << BIT_SHIFT_LPQ_V1_8821C)
+#define BIT_CLEAR_LPQ_V1_8821C(x) ((x) & (~BITS_LPQ_V1_8821C))
+#define BIT_GET_LPQ_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_LPQ_V1_8821C) & BIT_MASK_LPQ_V1_8821C)
+#define BIT_SET_LPQ_V1_8821C(x, v) \
+ (BIT_CLEAR_LPQ_V1_8821C(x) | BIT_LPQ_V1_8821C(v))
/* 2 REG_FIFOPAGE_INFO_3_8821C */
-#define BIT_SHIFT_NPQ_AVAL_PG_8821C 8
-#define BIT_MASK_NPQ_AVAL_PG_8821C 0xff
-#define BIT_NPQ_AVAL_PG_8821C(x) (((x) & BIT_MASK_NPQ_AVAL_PG_8821C) << BIT_SHIFT_NPQ_AVAL_PG_8821C)
-#define BIT_GET_NPQ_AVAL_PG_8821C(x) (((x) >> BIT_SHIFT_NPQ_AVAL_PG_8821C) & BIT_MASK_NPQ_AVAL_PG_8821C)
-
+#define BIT_SHIFT_NPQ_AVAL_PG_V1_8821C 16
+#define BIT_MASK_NPQ_AVAL_PG_V1_8821C 0xfff
+#define BIT_NPQ_AVAL_PG_V1_8821C(x) \
+ (((x) & BIT_MASK_NPQ_AVAL_PG_V1_8821C) \
+ << BIT_SHIFT_NPQ_AVAL_PG_V1_8821C)
+#define BITS_NPQ_AVAL_PG_V1_8821C \
+ (BIT_MASK_NPQ_AVAL_PG_V1_8821C << BIT_SHIFT_NPQ_AVAL_PG_V1_8821C)
+#define BIT_CLEAR_NPQ_AVAL_PG_V1_8821C(x) ((x) & (~BITS_NPQ_AVAL_PG_V1_8821C))
+#define BIT_GET_NPQ_AVAL_PG_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1_8821C) & \
+ BIT_MASK_NPQ_AVAL_PG_V1_8821C)
+#define BIT_SET_NPQ_AVAL_PG_V1_8821C(x, v) \
+ (BIT_CLEAR_NPQ_AVAL_PG_V1_8821C(x) | BIT_NPQ_AVAL_PG_V1_8821C(v))
#define BIT_SHIFT_NPQ_V1_8821C 0
#define BIT_MASK_NPQ_V1_8821C 0xfff
-#define BIT_NPQ_V1_8821C(x) (((x) & BIT_MASK_NPQ_V1_8821C) << BIT_SHIFT_NPQ_V1_8821C)
-#define BIT_GET_NPQ_V1_8821C(x) (((x) >> BIT_SHIFT_NPQ_V1_8821C) & BIT_MASK_NPQ_V1_8821C)
-
+#define BIT_NPQ_V1_8821C(x) \
+ (((x) & BIT_MASK_NPQ_V1_8821C) << BIT_SHIFT_NPQ_V1_8821C)
+#define BITS_NPQ_V1_8821C (BIT_MASK_NPQ_V1_8821C << BIT_SHIFT_NPQ_V1_8821C)
+#define BIT_CLEAR_NPQ_V1_8821C(x) ((x) & (~BITS_NPQ_V1_8821C))
+#define BIT_GET_NPQ_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_NPQ_V1_8821C) & BIT_MASK_NPQ_V1_8821C)
+#define BIT_SET_NPQ_V1_8821C(x, v) \
+ (BIT_CLEAR_NPQ_V1_8821C(x) | BIT_NPQ_V1_8821C(v))
/* 2 REG_FIFOPAGE_INFO_4_8821C */
#define BIT_SHIFT_EXQ_AVAL_PG_V1_8821C 16
#define BIT_MASK_EXQ_AVAL_PG_V1_8821C 0xfff
-#define BIT_EXQ_AVAL_PG_V1_8821C(x) (((x) & BIT_MASK_EXQ_AVAL_PG_V1_8821C) << BIT_SHIFT_EXQ_AVAL_PG_V1_8821C)
-#define BIT_GET_EXQ_AVAL_PG_V1_8821C(x) (((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1_8821C) & BIT_MASK_EXQ_AVAL_PG_V1_8821C)
-
+#define BIT_EXQ_AVAL_PG_V1_8821C(x) \
+ (((x) & BIT_MASK_EXQ_AVAL_PG_V1_8821C) \
+ << BIT_SHIFT_EXQ_AVAL_PG_V1_8821C)
+#define BITS_EXQ_AVAL_PG_V1_8821C \
+ (BIT_MASK_EXQ_AVAL_PG_V1_8821C << BIT_SHIFT_EXQ_AVAL_PG_V1_8821C)
+#define BIT_CLEAR_EXQ_AVAL_PG_V1_8821C(x) ((x) & (~BITS_EXQ_AVAL_PG_V1_8821C))
+#define BIT_GET_EXQ_AVAL_PG_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1_8821C) & \
+ BIT_MASK_EXQ_AVAL_PG_V1_8821C)
+#define BIT_SET_EXQ_AVAL_PG_V1_8821C(x, v) \
+ (BIT_CLEAR_EXQ_AVAL_PG_V1_8821C(x) | BIT_EXQ_AVAL_PG_V1_8821C(v))
#define BIT_SHIFT_EXQ_V1_8821C 0
#define BIT_MASK_EXQ_V1_8821C 0xfff
-#define BIT_EXQ_V1_8821C(x) (((x) & BIT_MASK_EXQ_V1_8821C) << BIT_SHIFT_EXQ_V1_8821C)
-#define BIT_GET_EXQ_V1_8821C(x) (((x) >> BIT_SHIFT_EXQ_V1_8821C) & BIT_MASK_EXQ_V1_8821C)
-
+#define BIT_EXQ_V1_8821C(x) \
+ (((x) & BIT_MASK_EXQ_V1_8821C) << BIT_SHIFT_EXQ_V1_8821C)
+#define BITS_EXQ_V1_8821C (BIT_MASK_EXQ_V1_8821C << BIT_SHIFT_EXQ_V1_8821C)
+#define BIT_CLEAR_EXQ_V1_8821C(x) ((x) & (~BITS_EXQ_V1_8821C))
+#define BIT_GET_EXQ_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_EXQ_V1_8821C) & BIT_MASK_EXQ_V1_8821C)
+#define BIT_SET_EXQ_V1_8821C(x, v) \
+ (BIT_CLEAR_EXQ_V1_8821C(x) | BIT_EXQ_V1_8821C(v))
/* 2 REG_FIFOPAGE_INFO_5_8821C */
#define BIT_SHIFT_PUBQ_AVAL_PG_V1_8821C 16
#define BIT_MASK_PUBQ_AVAL_PG_V1_8821C 0xfff
-#define BIT_PUBQ_AVAL_PG_V1_8821C(x) (((x) & BIT_MASK_PUBQ_AVAL_PG_V1_8821C) << BIT_SHIFT_PUBQ_AVAL_PG_V1_8821C)
-#define BIT_GET_PUBQ_AVAL_PG_V1_8821C(x) (((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1_8821C) & BIT_MASK_PUBQ_AVAL_PG_V1_8821C)
-
+#define BIT_PUBQ_AVAL_PG_V1_8821C(x) \
+ (((x) & BIT_MASK_PUBQ_AVAL_PG_V1_8821C) \
+ << BIT_SHIFT_PUBQ_AVAL_PG_V1_8821C)
+#define BITS_PUBQ_AVAL_PG_V1_8821C \
+ (BIT_MASK_PUBQ_AVAL_PG_V1_8821C << BIT_SHIFT_PUBQ_AVAL_PG_V1_8821C)
+#define BIT_CLEAR_PUBQ_AVAL_PG_V1_8821C(x) ((x) & (~BITS_PUBQ_AVAL_PG_V1_8821C))
+#define BIT_GET_PUBQ_AVAL_PG_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1_8821C) & \
+ BIT_MASK_PUBQ_AVAL_PG_V1_8821C)
+#define BIT_SET_PUBQ_AVAL_PG_V1_8821C(x, v) \
+ (BIT_CLEAR_PUBQ_AVAL_PG_V1_8821C(x) | BIT_PUBQ_AVAL_PG_V1_8821C(v))
#define BIT_SHIFT_PUBQ_V1_8821C 0
#define BIT_MASK_PUBQ_V1_8821C 0xfff
-#define BIT_PUBQ_V1_8821C(x) (((x) & BIT_MASK_PUBQ_V1_8821C) << BIT_SHIFT_PUBQ_V1_8821C)
-#define BIT_GET_PUBQ_V1_8821C(x) (((x) >> BIT_SHIFT_PUBQ_V1_8821C) & BIT_MASK_PUBQ_V1_8821C)
-
+#define BIT_PUBQ_V1_8821C(x) \
+ (((x) & BIT_MASK_PUBQ_V1_8821C) << BIT_SHIFT_PUBQ_V1_8821C)
+#define BITS_PUBQ_V1_8821C (BIT_MASK_PUBQ_V1_8821C << BIT_SHIFT_PUBQ_V1_8821C)
+#define BIT_CLEAR_PUBQ_V1_8821C(x) ((x) & (~BITS_PUBQ_V1_8821C))
+#define BIT_GET_PUBQ_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_PUBQ_V1_8821C) & BIT_MASK_PUBQ_V1_8821C)
+#define BIT_SET_PUBQ_V1_8821C(x, v) \
+ (BIT_CLEAR_PUBQ_V1_8821C(x) | BIT_PUBQ_V1_8821C(v))
/* 2 REG_H2C_HEAD_8821C */
#define BIT_SHIFT_H2C_HEAD_8821C 0
#define BIT_MASK_H2C_HEAD_8821C 0x3ffff
-#define BIT_H2C_HEAD_8821C(x) (((x) & BIT_MASK_H2C_HEAD_8821C) << BIT_SHIFT_H2C_HEAD_8821C)
-#define BIT_GET_H2C_HEAD_8821C(x) (((x) >> BIT_SHIFT_H2C_HEAD_8821C) & BIT_MASK_H2C_HEAD_8821C)
-
+#define BIT_H2C_HEAD_8821C(x) \
+ (((x) & BIT_MASK_H2C_HEAD_8821C) << BIT_SHIFT_H2C_HEAD_8821C)
+#define BITS_H2C_HEAD_8821C \
+ (BIT_MASK_H2C_HEAD_8821C << BIT_SHIFT_H2C_HEAD_8821C)
+#define BIT_CLEAR_H2C_HEAD_8821C(x) ((x) & (~BITS_H2C_HEAD_8821C))
+#define BIT_GET_H2C_HEAD_8821C(x) \
+ (((x) >> BIT_SHIFT_H2C_HEAD_8821C) & BIT_MASK_H2C_HEAD_8821C)
+#define BIT_SET_H2C_HEAD_8821C(x, v) \
+ (BIT_CLEAR_H2C_HEAD_8821C(x) | BIT_H2C_HEAD_8821C(v))
/* 2 REG_H2C_TAIL_8821C */
#define BIT_SHIFT_H2C_TAIL_8821C 0
#define BIT_MASK_H2C_TAIL_8821C 0x3ffff
-#define BIT_H2C_TAIL_8821C(x) (((x) & BIT_MASK_H2C_TAIL_8821C) << BIT_SHIFT_H2C_TAIL_8821C)
-#define BIT_GET_H2C_TAIL_8821C(x) (((x) >> BIT_SHIFT_H2C_TAIL_8821C) & BIT_MASK_H2C_TAIL_8821C)
-
+#define BIT_H2C_TAIL_8821C(x) \
+ (((x) & BIT_MASK_H2C_TAIL_8821C) << BIT_SHIFT_H2C_TAIL_8821C)
+#define BITS_H2C_TAIL_8821C \
+ (BIT_MASK_H2C_TAIL_8821C << BIT_SHIFT_H2C_TAIL_8821C)
+#define BIT_CLEAR_H2C_TAIL_8821C(x) ((x) & (~BITS_H2C_TAIL_8821C))
+#define BIT_GET_H2C_TAIL_8821C(x) \
+ (((x) >> BIT_SHIFT_H2C_TAIL_8821C) & BIT_MASK_H2C_TAIL_8821C)
+#define BIT_SET_H2C_TAIL_8821C(x, v) \
+ (BIT_CLEAR_H2C_TAIL_8821C(x) | BIT_H2C_TAIL_8821C(v))
/* 2 REG_H2C_READ_ADDR_8821C */
#define BIT_SHIFT_H2C_READ_ADDR_8821C 0
#define BIT_MASK_H2C_READ_ADDR_8821C 0x3ffff
-#define BIT_H2C_READ_ADDR_8821C(x) (((x) & BIT_MASK_H2C_READ_ADDR_8821C) << BIT_SHIFT_H2C_READ_ADDR_8821C)
-#define BIT_GET_H2C_READ_ADDR_8821C(x) (((x) >> BIT_SHIFT_H2C_READ_ADDR_8821C) & BIT_MASK_H2C_READ_ADDR_8821C)
-
+#define BIT_H2C_READ_ADDR_8821C(x) \
+ (((x) & BIT_MASK_H2C_READ_ADDR_8821C) << BIT_SHIFT_H2C_READ_ADDR_8821C)
+#define BITS_H2C_READ_ADDR_8821C \
+ (BIT_MASK_H2C_READ_ADDR_8821C << BIT_SHIFT_H2C_READ_ADDR_8821C)
+#define BIT_CLEAR_H2C_READ_ADDR_8821C(x) ((x) & (~BITS_H2C_READ_ADDR_8821C))
+#define BIT_GET_H2C_READ_ADDR_8821C(x) \
+ (((x) >> BIT_SHIFT_H2C_READ_ADDR_8821C) & BIT_MASK_H2C_READ_ADDR_8821C)
+#define BIT_SET_H2C_READ_ADDR_8821C(x, v) \
+ (BIT_CLEAR_H2C_READ_ADDR_8821C(x) | BIT_H2C_READ_ADDR_8821C(v))
/* 2 REG_H2C_WR_ADDR_8821C */
#define BIT_SHIFT_H2C_WR_ADDR_8821C 0
#define BIT_MASK_H2C_WR_ADDR_8821C 0x3ffff
-#define BIT_H2C_WR_ADDR_8821C(x) (((x) & BIT_MASK_H2C_WR_ADDR_8821C) << BIT_SHIFT_H2C_WR_ADDR_8821C)
-#define BIT_GET_H2C_WR_ADDR_8821C(x) (((x) >> BIT_SHIFT_H2C_WR_ADDR_8821C) & BIT_MASK_H2C_WR_ADDR_8821C)
-
+#define BIT_H2C_WR_ADDR_8821C(x) \
+ (((x) & BIT_MASK_H2C_WR_ADDR_8821C) << BIT_SHIFT_H2C_WR_ADDR_8821C)
+#define BITS_H2C_WR_ADDR_8821C \
+ (BIT_MASK_H2C_WR_ADDR_8821C << BIT_SHIFT_H2C_WR_ADDR_8821C)
+#define BIT_CLEAR_H2C_WR_ADDR_8821C(x) ((x) & (~BITS_H2C_WR_ADDR_8821C))
+#define BIT_GET_H2C_WR_ADDR_8821C(x) \
+ (((x) >> BIT_SHIFT_H2C_WR_ADDR_8821C) & BIT_MASK_H2C_WR_ADDR_8821C)
+#define BIT_SET_H2C_WR_ADDR_8821C(x, v) \
+ (BIT_CLEAR_H2C_WR_ADDR_8821C(x) | BIT_H2C_WR_ADDR_8821C(v))
/* 2 REG_H2C_INFO_8821C */
#define BIT_H2C_SPACE_VLD_8821C BIT(3)
@@ -3446,48 +6331,92 @@
#define BIT_SHIFT_H2C_LEN_SEL_8821C 0
#define BIT_MASK_H2C_LEN_SEL_8821C 0x3
-#define BIT_H2C_LEN_SEL_8821C(x) (((x) & BIT_MASK_H2C_LEN_SEL_8821C) << BIT_SHIFT_H2C_LEN_SEL_8821C)
-#define BIT_GET_H2C_LEN_SEL_8821C(x) (((x) >> BIT_SHIFT_H2C_LEN_SEL_8821C) & BIT_MASK_H2C_LEN_SEL_8821C)
-
+#define BIT_H2C_LEN_SEL_8821C(x) \
+ (((x) & BIT_MASK_H2C_LEN_SEL_8821C) << BIT_SHIFT_H2C_LEN_SEL_8821C)
+#define BITS_H2C_LEN_SEL_8821C \
+ (BIT_MASK_H2C_LEN_SEL_8821C << BIT_SHIFT_H2C_LEN_SEL_8821C)
+#define BIT_CLEAR_H2C_LEN_SEL_8821C(x) ((x) & (~BITS_H2C_LEN_SEL_8821C))
+#define BIT_GET_H2C_LEN_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_H2C_LEN_SEL_8821C) & BIT_MASK_H2C_LEN_SEL_8821C)
+#define BIT_SET_H2C_LEN_SEL_8821C(x, v) \
+ (BIT_CLEAR_H2C_LEN_SEL_8821C(x) | BIT_H2C_LEN_SEL_8821C(v))
/* 2 REG_RXDMA_AGG_PG_TH_8821C */
+#define BIT_USB_RXDMA_AGG_EN_8821C BIT(31)
+#define BIT_EN_PRE_CALC_8821C BIT(29)
+#define BIT_RXAGG_SW_EN_8821C BIT(28)
+#define BIT_RXAGG_SW_TRIG_8821C BIT(27)
-#define BIT_SHIFT_RXDMA_AGG_OLD_MOD_8821C 24
-#define BIT_MASK_RXDMA_AGG_OLD_MOD_8821C 0xff
-#define BIT_RXDMA_AGG_OLD_MOD_8821C(x) (((x) & BIT_MASK_RXDMA_AGG_OLD_MOD_8821C) << BIT_SHIFT_RXDMA_AGG_OLD_MOD_8821C)
-#define BIT_GET_RXDMA_AGG_OLD_MOD_8821C(x) (((x) >> BIT_SHIFT_RXDMA_AGG_OLD_MOD_8821C) & BIT_MASK_RXDMA_AGG_OLD_MOD_8821C)
-
+/* 2 REG_NOT_VALID_8821C */
#define BIT_SHIFT_PKT_NUM_WOL_8821C 16
#define BIT_MASK_PKT_NUM_WOL_8821C 0xff
-#define BIT_PKT_NUM_WOL_8821C(x) (((x) & BIT_MASK_PKT_NUM_WOL_8821C) << BIT_SHIFT_PKT_NUM_WOL_8821C)
-#define BIT_GET_PKT_NUM_WOL_8821C(x) (((x) >> BIT_SHIFT_PKT_NUM_WOL_8821C) & BIT_MASK_PKT_NUM_WOL_8821C)
-
-
-#define BIT_SHIFT_DMA_AGG_TO_8821C 8
-#define BIT_MASK_DMA_AGG_TO_8821C 0xf
-#define BIT_DMA_AGG_TO_8821C(x) (((x) & BIT_MASK_DMA_AGG_TO_8821C) << BIT_SHIFT_DMA_AGG_TO_8821C)
-#define BIT_GET_DMA_AGG_TO_8821C(x) (((x) >> BIT_SHIFT_DMA_AGG_TO_8821C) & BIT_MASK_DMA_AGG_TO_8821C)
-
-
-#define BIT_SHIFT_RXDMA_AGG_PG_TH_V1_8821C 0
-#define BIT_MASK_RXDMA_AGG_PG_TH_V1_8821C 0xf
-#define BIT_RXDMA_AGG_PG_TH_V1_8821C(x) (((x) & BIT_MASK_RXDMA_AGG_PG_TH_V1_8821C) << BIT_SHIFT_RXDMA_AGG_PG_TH_V1_8821C)
-#define BIT_GET_RXDMA_AGG_PG_TH_V1_8821C(x) (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_V1_8821C) & BIT_MASK_RXDMA_AGG_PG_TH_V1_8821C)
-
+#define BIT_PKT_NUM_WOL_8821C(x) \
+ (((x) & BIT_MASK_PKT_NUM_WOL_8821C) << BIT_SHIFT_PKT_NUM_WOL_8821C)
+#define BITS_PKT_NUM_WOL_8821C \
+ (BIT_MASK_PKT_NUM_WOL_8821C << BIT_SHIFT_PKT_NUM_WOL_8821C)
+#define BIT_CLEAR_PKT_NUM_WOL_8821C(x) ((x) & (~BITS_PKT_NUM_WOL_8821C))
+#define BIT_GET_PKT_NUM_WOL_8821C(x) \
+ (((x) >> BIT_SHIFT_PKT_NUM_WOL_8821C) & BIT_MASK_PKT_NUM_WOL_8821C)
+#define BIT_SET_PKT_NUM_WOL_8821C(x, v) \
+ (BIT_CLEAR_PKT_NUM_WOL_8821C(x) | BIT_PKT_NUM_WOL_8821C(v))
+
+#define BIT_SHIFT_DMA_AGG_TO_V1_8821C 8
+#define BIT_MASK_DMA_AGG_TO_V1_8821C 0xff
+#define BIT_DMA_AGG_TO_V1_8821C(x) \
+ (((x) & BIT_MASK_DMA_AGG_TO_V1_8821C) << BIT_SHIFT_DMA_AGG_TO_V1_8821C)
+#define BITS_DMA_AGG_TO_V1_8821C \
+ (BIT_MASK_DMA_AGG_TO_V1_8821C << BIT_SHIFT_DMA_AGG_TO_V1_8821C)
+#define BIT_CLEAR_DMA_AGG_TO_V1_8821C(x) ((x) & (~BITS_DMA_AGG_TO_V1_8821C))
+#define BIT_GET_DMA_AGG_TO_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_DMA_AGG_TO_V1_8821C) & BIT_MASK_DMA_AGG_TO_V1_8821C)
+#define BIT_SET_DMA_AGG_TO_V1_8821C(x, v) \
+ (BIT_CLEAR_DMA_AGG_TO_V1_8821C(x) | BIT_DMA_AGG_TO_V1_8821C(v))
+
+#define BIT_SHIFT_RXDMA_AGG_PG_TH_8821C 0
+#define BIT_MASK_RXDMA_AGG_PG_TH_8821C 0xff
+#define BIT_RXDMA_AGG_PG_TH_8821C(x) \
+ (((x) & BIT_MASK_RXDMA_AGG_PG_TH_8821C) \
+ << BIT_SHIFT_RXDMA_AGG_PG_TH_8821C)
+#define BITS_RXDMA_AGG_PG_TH_8821C \
+ (BIT_MASK_RXDMA_AGG_PG_TH_8821C << BIT_SHIFT_RXDMA_AGG_PG_TH_8821C)
+#define BIT_CLEAR_RXDMA_AGG_PG_TH_8821C(x) ((x) & (~BITS_RXDMA_AGG_PG_TH_8821C))
+#define BIT_GET_RXDMA_AGG_PG_TH_8821C(x) \
+ (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_8821C) & \
+ BIT_MASK_RXDMA_AGG_PG_TH_8821C)
+#define BIT_SET_RXDMA_AGG_PG_TH_8821C(x, v) \
+ (BIT_CLEAR_RXDMA_AGG_PG_TH_8821C(x) | BIT_RXDMA_AGG_PG_TH_8821C(v))
/* 2 REG_RXPKT_NUM_8821C */
#define BIT_SHIFT_RXPKT_NUM_8821C 24
#define BIT_MASK_RXPKT_NUM_8821C 0xff
-#define BIT_RXPKT_NUM_8821C(x) (((x) & BIT_MASK_RXPKT_NUM_8821C) << BIT_SHIFT_RXPKT_NUM_8821C)
-#define BIT_GET_RXPKT_NUM_8821C(x) (((x) >> BIT_SHIFT_RXPKT_NUM_8821C) & BIT_MASK_RXPKT_NUM_8821C)
-
+#define BIT_RXPKT_NUM_8821C(x) \
+ (((x) & BIT_MASK_RXPKT_NUM_8821C) << BIT_SHIFT_RXPKT_NUM_8821C)
+#define BITS_RXPKT_NUM_8821C \
+ (BIT_MASK_RXPKT_NUM_8821C << BIT_SHIFT_RXPKT_NUM_8821C)
+#define BIT_CLEAR_RXPKT_NUM_8821C(x) ((x) & (~BITS_RXPKT_NUM_8821C))
+#define BIT_GET_RXPKT_NUM_8821C(x) \
+ (((x) >> BIT_SHIFT_RXPKT_NUM_8821C) & BIT_MASK_RXPKT_NUM_8821C)
+#define BIT_SET_RXPKT_NUM_8821C(x, v) \
+ (BIT_CLEAR_RXPKT_NUM_8821C(x) | BIT_RXPKT_NUM_8821C(v))
#define BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8821C 20
#define BIT_MASK_FW_UPD_RDPTR19_TO_16_8821C 0xf
-#define BIT_FW_UPD_RDPTR19_TO_16_8821C(x) (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8821C) << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8821C)
-#define BIT_GET_FW_UPD_RDPTR19_TO_16_8821C(x) (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8821C) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8821C)
+#define BIT_FW_UPD_RDPTR19_TO_16_8821C(x) \
+ (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8821C) \
+ << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8821C)
+#define BITS_FW_UPD_RDPTR19_TO_16_8821C \
+ (BIT_MASK_FW_UPD_RDPTR19_TO_16_8821C \
+ << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8821C)
+#define BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8821C(x) \
+ ((x) & (~BITS_FW_UPD_RDPTR19_TO_16_8821C))
+#define BIT_GET_FW_UPD_RDPTR19_TO_16_8821C(x) \
+ (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8821C) & \
+ BIT_MASK_FW_UPD_RDPTR19_TO_16_8821C)
+#define BIT_SET_FW_UPD_RDPTR19_TO_16_8821C(x, v) \
+ (BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8821C(x) | \
+ BIT_FW_UPD_RDPTR19_TO_16_8821C(v))
#define BIT_RXDMA_REQ_8821C BIT(19)
#define BIT_RW_RELEASE_EN_8821C BIT(18)
@@ -3496,9 +6425,15 @@
#define BIT_SHIFT_FW_UPD_RDPTR_8821C 0
#define BIT_MASK_FW_UPD_RDPTR_8821C 0xffff
-#define BIT_FW_UPD_RDPTR_8821C(x) (((x) & BIT_MASK_FW_UPD_RDPTR_8821C) << BIT_SHIFT_FW_UPD_RDPTR_8821C)
-#define BIT_GET_FW_UPD_RDPTR_8821C(x) (((x) >> BIT_SHIFT_FW_UPD_RDPTR_8821C) & BIT_MASK_FW_UPD_RDPTR_8821C)
-
+#define BIT_FW_UPD_RDPTR_8821C(x) \
+ (((x) & BIT_MASK_FW_UPD_RDPTR_8821C) << BIT_SHIFT_FW_UPD_RDPTR_8821C)
+#define BITS_FW_UPD_RDPTR_8821C \
+ (BIT_MASK_FW_UPD_RDPTR_8821C << BIT_SHIFT_FW_UPD_RDPTR_8821C)
+#define BIT_CLEAR_FW_UPD_RDPTR_8821C(x) ((x) & (~BITS_FW_UPD_RDPTR_8821C))
+#define BIT_GET_FW_UPD_RDPTR_8821C(x) \
+ (((x) >> BIT_SHIFT_FW_UPD_RDPTR_8821C) & BIT_MASK_FW_UPD_RDPTR_8821C)
+#define BIT_SET_FW_UPD_RDPTR_8821C(x, v) \
+ (BIT_CLEAR_FW_UPD_RDPTR_8821C(x) | BIT_FW_UPD_RDPTR_8821C(v))
/* 2 REG_RXDMA_STATUS_8821C */
#define BIT_C2H_PKT_OVF_8821C BIT(7)
@@ -3513,41 +6448,67 @@
#define BIT_SHIFT_RDE_DEBUG_8821C 0
#define BIT_MASK_RDE_DEBUG_8821C 0xffffffffL
-#define BIT_RDE_DEBUG_8821C(x) (((x) & BIT_MASK_RDE_DEBUG_8821C) << BIT_SHIFT_RDE_DEBUG_8821C)
-#define BIT_GET_RDE_DEBUG_8821C(x) (((x) >> BIT_SHIFT_RDE_DEBUG_8821C) & BIT_MASK_RDE_DEBUG_8821C)
-
+#define BIT_RDE_DEBUG_8821C(x) \
+ (((x) & BIT_MASK_RDE_DEBUG_8821C) << BIT_SHIFT_RDE_DEBUG_8821C)
+#define BITS_RDE_DEBUG_8821C \
+ (BIT_MASK_RDE_DEBUG_8821C << BIT_SHIFT_RDE_DEBUG_8821C)
+#define BIT_CLEAR_RDE_DEBUG_8821C(x) ((x) & (~BITS_RDE_DEBUG_8821C))
+#define BIT_GET_RDE_DEBUG_8821C(x) \
+ (((x) >> BIT_SHIFT_RDE_DEBUG_8821C) & BIT_MASK_RDE_DEBUG_8821C)
+#define BIT_SET_RDE_DEBUG_8821C(x, v) \
+ (BIT_CLEAR_RDE_DEBUG_8821C(x) | BIT_RDE_DEBUG_8821C(v))
/* 2 REG_RXDMA_MODE_8821C */
#define BIT_SHIFT_PKTNUM_TH_V2_8821C 24
#define BIT_MASK_PKTNUM_TH_V2_8821C 0x1f
-#define BIT_PKTNUM_TH_V2_8821C(x) (((x) & BIT_MASK_PKTNUM_TH_V2_8821C) << BIT_SHIFT_PKTNUM_TH_V2_8821C)
-#define BIT_GET_PKTNUM_TH_V2_8821C(x) (((x) >> BIT_SHIFT_PKTNUM_TH_V2_8821C) & BIT_MASK_PKTNUM_TH_V2_8821C)
+#define BIT_PKTNUM_TH_V2_8821C(x) \
+ (((x) & BIT_MASK_PKTNUM_TH_V2_8821C) << BIT_SHIFT_PKTNUM_TH_V2_8821C)
+#define BITS_PKTNUM_TH_V2_8821C \
+ (BIT_MASK_PKTNUM_TH_V2_8821C << BIT_SHIFT_PKTNUM_TH_V2_8821C)
+#define BIT_CLEAR_PKTNUM_TH_V2_8821C(x) ((x) & (~BITS_PKTNUM_TH_V2_8821C))
+#define BIT_GET_PKTNUM_TH_V2_8821C(x) \
+ (((x) >> BIT_SHIFT_PKTNUM_TH_V2_8821C) & BIT_MASK_PKTNUM_TH_V2_8821C)
+#define BIT_SET_PKTNUM_TH_V2_8821C(x, v) \
+ (BIT_CLEAR_PKTNUM_TH_V2_8821C(x) | BIT_PKTNUM_TH_V2_8821C(v))
#define BIT_TXBA_BREAK_USBAGG_8821C BIT(23)
#define BIT_SHIFT_PKTLEN_PARA_8821C 16
#define BIT_MASK_PKTLEN_PARA_8821C 0x7
-#define BIT_PKTLEN_PARA_8821C(x) (((x) & BIT_MASK_PKTLEN_PARA_8821C) << BIT_SHIFT_PKTLEN_PARA_8821C)
-#define BIT_GET_PKTLEN_PARA_8821C(x) (((x) >> BIT_SHIFT_PKTLEN_PARA_8821C) & BIT_MASK_PKTLEN_PARA_8821C)
-
-
-/* 2 REG_NOT_VALID_8821C */
-
-/* 2 REG_NOT_VALID_8821C */
-
-/* 2 REG_NOT_VALID_8821C */
+#define BIT_PKTLEN_PARA_8821C(x) \
+ (((x) & BIT_MASK_PKTLEN_PARA_8821C) << BIT_SHIFT_PKTLEN_PARA_8821C)
+#define BITS_PKTLEN_PARA_8821C \
+ (BIT_MASK_PKTLEN_PARA_8821C << BIT_SHIFT_PKTLEN_PARA_8821C)
+#define BIT_CLEAR_PKTLEN_PARA_8821C(x) ((x) & (~BITS_PKTLEN_PARA_8821C))
+#define BIT_GET_PKTLEN_PARA_8821C(x) \
+ (((x) >> BIT_SHIFT_PKTLEN_PARA_8821C) & BIT_MASK_PKTLEN_PARA_8821C)
+#define BIT_SET_PKTLEN_PARA_8821C(x, v) \
+ (BIT_CLEAR_PKTLEN_PARA_8821C(x) | BIT_PKTLEN_PARA_8821C(v))
#define BIT_SHIFT_BURST_SIZE_8821C 4
#define BIT_MASK_BURST_SIZE_8821C 0x3
-#define BIT_BURST_SIZE_8821C(x) (((x) & BIT_MASK_BURST_SIZE_8821C) << BIT_SHIFT_BURST_SIZE_8821C)
-#define BIT_GET_BURST_SIZE_8821C(x) (((x) >> BIT_SHIFT_BURST_SIZE_8821C) & BIT_MASK_BURST_SIZE_8821C)
-
+#define BIT_BURST_SIZE_8821C(x) \
+ (((x) & BIT_MASK_BURST_SIZE_8821C) << BIT_SHIFT_BURST_SIZE_8821C)
+#define BITS_BURST_SIZE_8821C \
+ (BIT_MASK_BURST_SIZE_8821C << BIT_SHIFT_BURST_SIZE_8821C)
+#define BIT_CLEAR_BURST_SIZE_8821C(x) ((x) & (~BITS_BURST_SIZE_8821C))
+#define BIT_GET_BURST_SIZE_8821C(x) \
+ (((x) >> BIT_SHIFT_BURST_SIZE_8821C) & BIT_MASK_BURST_SIZE_8821C)
+#define BIT_SET_BURST_SIZE_8821C(x, v) \
+ (BIT_CLEAR_BURST_SIZE_8821C(x) | BIT_BURST_SIZE_8821C(v))
#define BIT_SHIFT_BURST_CNT_8821C 2
#define BIT_MASK_BURST_CNT_8821C 0x3
-#define BIT_BURST_CNT_8821C(x) (((x) & BIT_MASK_BURST_CNT_8821C) << BIT_SHIFT_BURST_CNT_8821C)
-#define BIT_GET_BURST_CNT_8821C(x) (((x) >> BIT_SHIFT_BURST_CNT_8821C) & BIT_MASK_BURST_CNT_8821C)
+#define BIT_BURST_CNT_8821C(x) \
+ (((x) & BIT_MASK_BURST_CNT_8821C) << BIT_SHIFT_BURST_CNT_8821C)
+#define BITS_BURST_CNT_8821C \
+ (BIT_MASK_BURST_CNT_8821C << BIT_SHIFT_BURST_CNT_8821C)
+#define BIT_CLEAR_BURST_CNT_8821C(x) ((x) & (~BITS_BURST_CNT_8821C))
+#define BIT_GET_BURST_CNT_8821C(x) \
+ (((x) >> BIT_SHIFT_BURST_CNT_8821C) & BIT_MASK_BURST_CNT_8821C)
+#define BIT_SET_BURST_CNT_8821C(x, v) \
+ (BIT_CLEAR_BURST_CNT_8821C(x) | BIT_BURST_CNT_8821C(v))
#define BIT_DMA_MODE_8821C BIT(1)
@@ -3555,74 +6516,143 @@
#define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8821C 24
#define BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8821C 0xf
-#define BIT_R_C2H_STR_ADDR_16_TO_19_8821C(x) (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8821C) << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8821C)
-#define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8821C(x) (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8821C) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8821C)
+#define BIT_R_C2H_STR_ADDR_16_TO_19_8821C(x) \
+ (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8821C) \
+ << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8821C)
+#define BITS_R_C2H_STR_ADDR_16_TO_19_8821C \
+ (BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8821C \
+ << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8821C)
+#define BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8821C(x) \
+ ((x) & (~BITS_R_C2H_STR_ADDR_16_TO_19_8821C))
+#define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8821C(x) \
+ (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8821C) & \
+ BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8821C)
+#define BIT_SET_R_C2H_STR_ADDR_16_TO_19_8821C(x, v) \
+ (BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8821C(x) | \
+ BIT_R_C2H_STR_ADDR_16_TO_19_8821C(v))
#define BIT_R_C2H_PKT_REQ_8821C BIT(16)
#define BIT_SHIFT_R_C2H_STR_ADDR_8821C 0
#define BIT_MASK_R_C2H_STR_ADDR_8821C 0xffff
-#define BIT_R_C2H_STR_ADDR_8821C(x) (((x) & BIT_MASK_R_C2H_STR_ADDR_8821C) << BIT_SHIFT_R_C2H_STR_ADDR_8821C)
-#define BIT_GET_R_C2H_STR_ADDR_8821C(x) (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8821C) & BIT_MASK_R_C2H_STR_ADDR_8821C)
-
+#define BIT_R_C2H_STR_ADDR_8821C(x) \
+ (((x) & BIT_MASK_R_C2H_STR_ADDR_8821C) \
+ << BIT_SHIFT_R_C2H_STR_ADDR_8821C)
+#define BITS_R_C2H_STR_ADDR_8821C \
+ (BIT_MASK_R_C2H_STR_ADDR_8821C << BIT_SHIFT_R_C2H_STR_ADDR_8821C)
+#define BIT_CLEAR_R_C2H_STR_ADDR_8821C(x) ((x) & (~BITS_R_C2H_STR_ADDR_8821C))
+#define BIT_GET_R_C2H_STR_ADDR_8821C(x) \
+ (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8821C) & \
+ BIT_MASK_R_C2H_STR_ADDR_8821C)
+#define BIT_SET_R_C2H_STR_ADDR_8821C(x, v) \
+ (BIT_CLEAR_R_C2H_STR_ADDR_8821C(x) | BIT_R_C2H_STR_ADDR_8821C(v))
/* 2 REG_FWFF_C2H_8821C */
#define BIT_SHIFT_C2H_DMA_ADDR_8821C 0
#define BIT_MASK_C2H_DMA_ADDR_8821C 0x3ffff
-#define BIT_C2H_DMA_ADDR_8821C(x) (((x) & BIT_MASK_C2H_DMA_ADDR_8821C) << BIT_SHIFT_C2H_DMA_ADDR_8821C)
-#define BIT_GET_C2H_DMA_ADDR_8821C(x) (((x) >> BIT_SHIFT_C2H_DMA_ADDR_8821C) & BIT_MASK_C2H_DMA_ADDR_8821C)
-
+#define BIT_C2H_DMA_ADDR_8821C(x) \
+ (((x) & BIT_MASK_C2H_DMA_ADDR_8821C) << BIT_SHIFT_C2H_DMA_ADDR_8821C)
+#define BITS_C2H_DMA_ADDR_8821C \
+ (BIT_MASK_C2H_DMA_ADDR_8821C << BIT_SHIFT_C2H_DMA_ADDR_8821C)
+#define BIT_CLEAR_C2H_DMA_ADDR_8821C(x) ((x) & (~BITS_C2H_DMA_ADDR_8821C))
+#define BIT_GET_C2H_DMA_ADDR_8821C(x) \
+ (((x) >> BIT_SHIFT_C2H_DMA_ADDR_8821C) & BIT_MASK_C2H_DMA_ADDR_8821C)
+#define BIT_SET_C2H_DMA_ADDR_8821C(x, v) \
+ (BIT_CLEAR_C2H_DMA_ADDR_8821C(x) | BIT_C2H_DMA_ADDR_8821C(v))
/* 2 REG_FWFF_CTRL_8821C */
#define BIT_FWFF_DMAPKT_REQ_8821C BIT(31)
#define BIT_SHIFT_FWFF_DMA_PKT_NUM_8821C 16
#define BIT_MASK_FWFF_DMA_PKT_NUM_8821C 0xff
-#define BIT_FWFF_DMA_PKT_NUM_8821C(x) (((x) & BIT_MASK_FWFF_DMA_PKT_NUM_8821C) << BIT_SHIFT_FWFF_DMA_PKT_NUM_8821C)
-#define BIT_GET_FWFF_DMA_PKT_NUM_8821C(x) (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_8821C) & BIT_MASK_FWFF_DMA_PKT_NUM_8821C)
-
+#define BIT_FWFF_DMA_PKT_NUM_8821C(x) \
+ (((x) & BIT_MASK_FWFF_DMA_PKT_NUM_8821C) \
+ << BIT_SHIFT_FWFF_DMA_PKT_NUM_8821C)
+#define BITS_FWFF_DMA_PKT_NUM_8821C \
+ (BIT_MASK_FWFF_DMA_PKT_NUM_8821C << BIT_SHIFT_FWFF_DMA_PKT_NUM_8821C)
+#define BIT_CLEAR_FWFF_DMA_PKT_NUM_8821C(x) \
+ ((x) & (~BITS_FWFF_DMA_PKT_NUM_8821C))
+#define BIT_GET_FWFF_DMA_PKT_NUM_8821C(x) \
+ (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_8821C) & \
+ BIT_MASK_FWFF_DMA_PKT_NUM_8821C)
+#define BIT_SET_FWFF_DMA_PKT_NUM_8821C(x, v) \
+ (BIT_CLEAR_FWFF_DMA_PKT_NUM_8821C(x) | BIT_FWFF_DMA_PKT_NUM_8821C(v))
#define BIT_SHIFT_FWFF_STR_ADDR_8821C 0
#define BIT_MASK_FWFF_STR_ADDR_8821C 0xffff
-#define BIT_FWFF_STR_ADDR_8821C(x) (((x) & BIT_MASK_FWFF_STR_ADDR_8821C) << BIT_SHIFT_FWFF_STR_ADDR_8821C)
-#define BIT_GET_FWFF_STR_ADDR_8821C(x) (((x) >> BIT_SHIFT_FWFF_STR_ADDR_8821C) & BIT_MASK_FWFF_STR_ADDR_8821C)
-
+#define BIT_FWFF_STR_ADDR_8821C(x) \
+ (((x) & BIT_MASK_FWFF_STR_ADDR_8821C) << BIT_SHIFT_FWFF_STR_ADDR_8821C)
+#define BITS_FWFF_STR_ADDR_8821C \
+ (BIT_MASK_FWFF_STR_ADDR_8821C << BIT_SHIFT_FWFF_STR_ADDR_8821C)
+#define BIT_CLEAR_FWFF_STR_ADDR_8821C(x) ((x) & (~BITS_FWFF_STR_ADDR_8821C))
+#define BIT_GET_FWFF_STR_ADDR_8821C(x) \
+ (((x) >> BIT_SHIFT_FWFF_STR_ADDR_8821C) & BIT_MASK_FWFF_STR_ADDR_8821C)
+#define BIT_SET_FWFF_STR_ADDR_8821C(x, v) \
+ (BIT_CLEAR_FWFF_STR_ADDR_8821C(x) | BIT_FWFF_STR_ADDR_8821C(v))
/* 2 REG_FWFF_PKT_INFO_8821C */
#define BIT_SHIFT_FWFF_PKT_QUEUED_8821C 16
#define BIT_MASK_FWFF_PKT_QUEUED_8821C 0xff
-#define BIT_FWFF_PKT_QUEUED_8821C(x) (((x) & BIT_MASK_FWFF_PKT_QUEUED_8821C) << BIT_SHIFT_FWFF_PKT_QUEUED_8821C)
-#define BIT_GET_FWFF_PKT_QUEUED_8821C(x) (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_8821C) & BIT_MASK_FWFF_PKT_QUEUED_8821C)
-
+#define BIT_FWFF_PKT_QUEUED_8821C(x) \
+ (((x) & BIT_MASK_FWFF_PKT_QUEUED_8821C) \
+ << BIT_SHIFT_FWFF_PKT_QUEUED_8821C)
+#define BITS_FWFF_PKT_QUEUED_8821C \
+ (BIT_MASK_FWFF_PKT_QUEUED_8821C << BIT_SHIFT_FWFF_PKT_QUEUED_8821C)
+#define BIT_CLEAR_FWFF_PKT_QUEUED_8821C(x) ((x) & (~BITS_FWFF_PKT_QUEUED_8821C))
+#define BIT_GET_FWFF_PKT_QUEUED_8821C(x) \
+ (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_8821C) & \
+ BIT_MASK_FWFF_PKT_QUEUED_8821C)
+#define BIT_SET_FWFF_PKT_QUEUED_8821C(x, v) \
+ (BIT_CLEAR_FWFF_PKT_QUEUED_8821C(x) | BIT_FWFF_PKT_QUEUED_8821C(v))
#define BIT_SHIFT_FWFF_PKT_STR_ADDR_8821C 0
#define BIT_MASK_FWFF_PKT_STR_ADDR_8821C 0xffff
-#define BIT_FWFF_PKT_STR_ADDR_8821C(x) (((x) & BIT_MASK_FWFF_PKT_STR_ADDR_8821C) << BIT_SHIFT_FWFF_PKT_STR_ADDR_8821C)
-#define BIT_GET_FWFF_PKT_STR_ADDR_8821C(x) (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_8821C) & BIT_MASK_FWFF_PKT_STR_ADDR_8821C)
-
-
-/* 2 REG_NOT_VALID_8821C */
+#define BIT_FWFF_PKT_STR_ADDR_8821C(x) \
+ (((x) & BIT_MASK_FWFF_PKT_STR_ADDR_8821C) \
+ << BIT_SHIFT_FWFF_PKT_STR_ADDR_8821C)
+#define BITS_FWFF_PKT_STR_ADDR_8821C \
+ (BIT_MASK_FWFF_PKT_STR_ADDR_8821C << BIT_SHIFT_FWFF_PKT_STR_ADDR_8821C)
+#define BIT_CLEAR_FWFF_PKT_STR_ADDR_8821C(x) \
+ ((x) & (~BITS_FWFF_PKT_STR_ADDR_8821C))
+#define BIT_GET_FWFF_PKT_STR_ADDR_8821C(x) \
+ (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_8821C) & \
+ BIT_MASK_FWFF_PKT_STR_ADDR_8821C)
+#define BIT_SET_FWFF_PKT_STR_ADDR_8821C(x, v) \
+ (BIT_CLEAR_FWFF_PKT_STR_ADDR_8821C(x) | BIT_FWFF_PKT_STR_ADDR_8821C(v))
/* 2 REG_DDMA_CH0SA_8821C */
#define BIT_SHIFT_DDMACH0_SA_8821C 0
#define BIT_MASK_DDMACH0_SA_8821C 0xffffffffL
-#define BIT_DDMACH0_SA_8821C(x) (((x) & BIT_MASK_DDMACH0_SA_8821C) << BIT_SHIFT_DDMACH0_SA_8821C)
-#define BIT_GET_DDMACH0_SA_8821C(x) (((x) >> BIT_SHIFT_DDMACH0_SA_8821C) & BIT_MASK_DDMACH0_SA_8821C)
-
+#define BIT_DDMACH0_SA_8821C(x) \
+ (((x) & BIT_MASK_DDMACH0_SA_8821C) << BIT_SHIFT_DDMACH0_SA_8821C)
+#define BITS_DDMACH0_SA_8821C \
+ (BIT_MASK_DDMACH0_SA_8821C << BIT_SHIFT_DDMACH0_SA_8821C)
+#define BIT_CLEAR_DDMACH0_SA_8821C(x) ((x) & (~BITS_DDMACH0_SA_8821C))
+#define BIT_GET_DDMACH0_SA_8821C(x) \
+ (((x) >> BIT_SHIFT_DDMACH0_SA_8821C) & BIT_MASK_DDMACH0_SA_8821C)
+#define BIT_SET_DDMACH0_SA_8821C(x, v) \
+ (BIT_CLEAR_DDMACH0_SA_8821C(x) | BIT_DDMACH0_SA_8821C(v))
/* 2 REG_DDMA_CH0DA_8821C */
#define BIT_SHIFT_DDMACH0_DA_8821C 0
#define BIT_MASK_DDMACH0_DA_8821C 0xffffffffL
-#define BIT_DDMACH0_DA_8821C(x) (((x) & BIT_MASK_DDMACH0_DA_8821C) << BIT_SHIFT_DDMACH0_DA_8821C)
-#define BIT_GET_DDMACH0_DA_8821C(x) (((x) >> BIT_SHIFT_DDMACH0_DA_8821C) & BIT_MASK_DDMACH0_DA_8821C)
-
+#define BIT_DDMACH0_DA_8821C(x) \
+ (((x) & BIT_MASK_DDMACH0_DA_8821C) << BIT_SHIFT_DDMACH0_DA_8821C)
+#define BITS_DDMACH0_DA_8821C \
+ (BIT_MASK_DDMACH0_DA_8821C << BIT_SHIFT_DDMACH0_DA_8821C)
+#define BIT_CLEAR_DDMACH0_DA_8821C(x) ((x) & (~BITS_DDMACH0_DA_8821C))
+#define BIT_GET_DDMACH0_DA_8821C(x) \
+ (((x) >> BIT_SHIFT_DDMACH0_DA_8821C) & BIT_MASK_DDMACH0_DA_8821C)
+#define BIT_SET_DDMACH0_DA_8821C(x, v) \
+ (BIT_CLEAR_DDMACH0_DA_8821C(x) | BIT_DDMACH0_DA_8821C(v))
/* 2 REG_DDMA_CH0CTRL_8821C */
#define BIT_DDMACH0_OWN_8821C BIT(31)
+#define BIT_DDMACH0_IDMEM_ERR_8821C BIT(30)
#define BIT_DDMACH0_CHKSUM_EN_8821C BIT(29)
#define BIT_DDMACH0_DA_W_DISABLE_8821C BIT(28)
#define BIT_DDMACH0_CHKSUM_STS_8821C BIT(27)
@@ -3632,28 +6662,47 @@
#define BIT_SHIFT_DDMACH0_DLEN_8821C 0
#define BIT_MASK_DDMACH0_DLEN_8821C 0x3ffff
-#define BIT_DDMACH0_DLEN_8821C(x) (((x) & BIT_MASK_DDMACH0_DLEN_8821C) << BIT_SHIFT_DDMACH0_DLEN_8821C)
-#define BIT_GET_DDMACH0_DLEN_8821C(x) (((x) >> BIT_SHIFT_DDMACH0_DLEN_8821C) & BIT_MASK_DDMACH0_DLEN_8821C)
-
+#define BIT_DDMACH0_DLEN_8821C(x) \
+ (((x) & BIT_MASK_DDMACH0_DLEN_8821C) << BIT_SHIFT_DDMACH0_DLEN_8821C)
+#define BITS_DDMACH0_DLEN_8821C \
+ (BIT_MASK_DDMACH0_DLEN_8821C << BIT_SHIFT_DDMACH0_DLEN_8821C)
+#define BIT_CLEAR_DDMACH0_DLEN_8821C(x) ((x) & (~BITS_DDMACH0_DLEN_8821C))
+#define BIT_GET_DDMACH0_DLEN_8821C(x) \
+ (((x) >> BIT_SHIFT_DDMACH0_DLEN_8821C) & BIT_MASK_DDMACH0_DLEN_8821C)
+#define BIT_SET_DDMACH0_DLEN_8821C(x, v) \
+ (BIT_CLEAR_DDMACH0_DLEN_8821C(x) | BIT_DDMACH0_DLEN_8821C(v))
/* 2 REG_DDMA_CH1SA_8821C */
#define BIT_SHIFT_DDMACH1_SA_8821C 0
#define BIT_MASK_DDMACH1_SA_8821C 0xffffffffL
-#define BIT_DDMACH1_SA_8821C(x) (((x) & BIT_MASK_DDMACH1_SA_8821C) << BIT_SHIFT_DDMACH1_SA_8821C)
-#define BIT_GET_DDMACH1_SA_8821C(x) (((x) >> BIT_SHIFT_DDMACH1_SA_8821C) & BIT_MASK_DDMACH1_SA_8821C)
-
+#define BIT_DDMACH1_SA_8821C(x) \
+ (((x) & BIT_MASK_DDMACH1_SA_8821C) << BIT_SHIFT_DDMACH1_SA_8821C)
+#define BITS_DDMACH1_SA_8821C \
+ (BIT_MASK_DDMACH1_SA_8821C << BIT_SHIFT_DDMACH1_SA_8821C)
+#define BIT_CLEAR_DDMACH1_SA_8821C(x) ((x) & (~BITS_DDMACH1_SA_8821C))
+#define BIT_GET_DDMACH1_SA_8821C(x) \
+ (((x) >> BIT_SHIFT_DDMACH1_SA_8821C) & BIT_MASK_DDMACH1_SA_8821C)
+#define BIT_SET_DDMACH1_SA_8821C(x, v) \
+ (BIT_CLEAR_DDMACH1_SA_8821C(x) | BIT_DDMACH1_SA_8821C(v))
/* 2 REG_DDMA_CH1DA_8821C */
#define BIT_SHIFT_DDMACH1_DA_8821C 0
#define BIT_MASK_DDMACH1_DA_8821C 0xffffffffL
-#define BIT_DDMACH1_DA_8821C(x) (((x) & BIT_MASK_DDMACH1_DA_8821C) << BIT_SHIFT_DDMACH1_DA_8821C)
-#define BIT_GET_DDMACH1_DA_8821C(x) (((x) >> BIT_SHIFT_DDMACH1_DA_8821C) & BIT_MASK_DDMACH1_DA_8821C)
-
+#define BIT_DDMACH1_DA_8821C(x) \
+ (((x) & BIT_MASK_DDMACH1_DA_8821C) << BIT_SHIFT_DDMACH1_DA_8821C)
+#define BITS_DDMACH1_DA_8821C \
+ (BIT_MASK_DDMACH1_DA_8821C << BIT_SHIFT_DDMACH1_DA_8821C)
+#define BIT_CLEAR_DDMACH1_DA_8821C(x) ((x) & (~BITS_DDMACH1_DA_8821C))
+#define BIT_GET_DDMACH1_DA_8821C(x) \
+ (((x) >> BIT_SHIFT_DDMACH1_DA_8821C) & BIT_MASK_DDMACH1_DA_8821C)
+#define BIT_SET_DDMACH1_DA_8821C(x, v) \
+ (BIT_CLEAR_DDMACH1_DA_8821C(x) | BIT_DDMACH1_DA_8821C(v))
/* 2 REG_DDMA_CH1CTRL_8821C */
#define BIT_DDMACH1_OWN_8821C BIT(31)
+#define BIT_DDMACH1_IDMEM_ERR_8821C BIT(30)
#define BIT_DDMACH1_CHKSUM_EN_8821C BIT(29)
#define BIT_DDMACH1_DA_W_DISABLE_8821C BIT(28)
#define BIT_DDMACH1_CHKSUM_STS_8821C BIT(27)
@@ -3663,28 +6712,47 @@
#define BIT_SHIFT_DDMACH1_DLEN_8821C 0
#define BIT_MASK_DDMACH1_DLEN_8821C 0x3ffff
-#define BIT_DDMACH1_DLEN_8821C(x) (((x) & BIT_MASK_DDMACH1_DLEN_8821C) << BIT_SHIFT_DDMACH1_DLEN_8821C)
-#define BIT_GET_DDMACH1_DLEN_8821C(x) (((x) >> BIT_SHIFT_DDMACH1_DLEN_8821C) & BIT_MASK_DDMACH1_DLEN_8821C)
-
+#define BIT_DDMACH1_DLEN_8821C(x) \
+ (((x) & BIT_MASK_DDMACH1_DLEN_8821C) << BIT_SHIFT_DDMACH1_DLEN_8821C)
+#define BITS_DDMACH1_DLEN_8821C \
+ (BIT_MASK_DDMACH1_DLEN_8821C << BIT_SHIFT_DDMACH1_DLEN_8821C)
+#define BIT_CLEAR_DDMACH1_DLEN_8821C(x) ((x) & (~BITS_DDMACH1_DLEN_8821C))
+#define BIT_GET_DDMACH1_DLEN_8821C(x) \
+ (((x) >> BIT_SHIFT_DDMACH1_DLEN_8821C) & BIT_MASK_DDMACH1_DLEN_8821C)
+#define BIT_SET_DDMACH1_DLEN_8821C(x, v) \
+ (BIT_CLEAR_DDMACH1_DLEN_8821C(x) | BIT_DDMACH1_DLEN_8821C(v))
/* 2 REG_DDMA_CH2SA_8821C */
#define BIT_SHIFT_DDMACH2_SA_8821C 0
#define BIT_MASK_DDMACH2_SA_8821C 0xffffffffL
-#define BIT_DDMACH2_SA_8821C(x) (((x) & BIT_MASK_DDMACH2_SA_8821C) << BIT_SHIFT_DDMACH2_SA_8821C)
-#define BIT_GET_DDMACH2_SA_8821C(x) (((x) >> BIT_SHIFT_DDMACH2_SA_8821C) & BIT_MASK_DDMACH2_SA_8821C)
-
+#define BIT_DDMACH2_SA_8821C(x) \
+ (((x) & BIT_MASK_DDMACH2_SA_8821C) << BIT_SHIFT_DDMACH2_SA_8821C)
+#define BITS_DDMACH2_SA_8821C \
+ (BIT_MASK_DDMACH2_SA_8821C << BIT_SHIFT_DDMACH2_SA_8821C)
+#define BIT_CLEAR_DDMACH2_SA_8821C(x) ((x) & (~BITS_DDMACH2_SA_8821C))
+#define BIT_GET_DDMACH2_SA_8821C(x) \
+ (((x) >> BIT_SHIFT_DDMACH2_SA_8821C) & BIT_MASK_DDMACH2_SA_8821C)
+#define BIT_SET_DDMACH2_SA_8821C(x, v) \
+ (BIT_CLEAR_DDMACH2_SA_8821C(x) | BIT_DDMACH2_SA_8821C(v))
/* 2 REG_DDMA_CH2DA_8821C */
#define BIT_SHIFT_DDMACH2_DA_8821C 0
#define BIT_MASK_DDMACH2_DA_8821C 0xffffffffL
-#define BIT_DDMACH2_DA_8821C(x) (((x) & BIT_MASK_DDMACH2_DA_8821C) << BIT_SHIFT_DDMACH2_DA_8821C)
-#define BIT_GET_DDMACH2_DA_8821C(x) (((x) >> BIT_SHIFT_DDMACH2_DA_8821C) & BIT_MASK_DDMACH2_DA_8821C)
-
+#define BIT_DDMACH2_DA_8821C(x) \
+ (((x) & BIT_MASK_DDMACH2_DA_8821C) << BIT_SHIFT_DDMACH2_DA_8821C)
+#define BITS_DDMACH2_DA_8821C \
+ (BIT_MASK_DDMACH2_DA_8821C << BIT_SHIFT_DDMACH2_DA_8821C)
+#define BIT_CLEAR_DDMACH2_DA_8821C(x) ((x) & (~BITS_DDMACH2_DA_8821C))
+#define BIT_GET_DDMACH2_DA_8821C(x) \
+ (((x) >> BIT_SHIFT_DDMACH2_DA_8821C) & BIT_MASK_DDMACH2_DA_8821C)
+#define BIT_SET_DDMACH2_DA_8821C(x, v) \
+ (BIT_CLEAR_DDMACH2_DA_8821C(x) | BIT_DDMACH2_DA_8821C(v))
/* 2 REG_DDMA_CH2CTRL_8821C */
#define BIT_DDMACH2_OWN_8821C BIT(31)
+#define BIT_DDMACH2_IDMEM_ERR_8821C BIT(30)
#define BIT_DDMACH2_CHKSUM_EN_8821C BIT(29)
#define BIT_DDMACH2_DA_W_DISABLE_8821C BIT(28)
#define BIT_DDMACH2_CHKSUM_STS_8821C BIT(27)
@@ -3694,28 +6762,47 @@
#define BIT_SHIFT_DDMACH2_DLEN_8821C 0
#define BIT_MASK_DDMACH2_DLEN_8821C 0x3ffff
-#define BIT_DDMACH2_DLEN_8821C(x) (((x) & BIT_MASK_DDMACH2_DLEN_8821C) << BIT_SHIFT_DDMACH2_DLEN_8821C)
-#define BIT_GET_DDMACH2_DLEN_8821C(x) (((x) >> BIT_SHIFT_DDMACH2_DLEN_8821C) & BIT_MASK_DDMACH2_DLEN_8821C)
-
+#define BIT_DDMACH2_DLEN_8821C(x) \
+ (((x) & BIT_MASK_DDMACH2_DLEN_8821C) << BIT_SHIFT_DDMACH2_DLEN_8821C)
+#define BITS_DDMACH2_DLEN_8821C \
+ (BIT_MASK_DDMACH2_DLEN_8821C << BIT_SHIFT_DDMACH2_DLEN_8821C)
+#define BIT_CLEAR_DDMACH2_DLEN_8821C(x) ((x) & (~BITS_DDMACH2_DLEN_8821C))
+#define BIT_GET_DDMACH2_DLEN_8821C(x) \
+ (((x) >> BIT_SHIFT_DDMACH2_DLEN_8821C) & BIT_MASK_DDMACH2_DLEN_8821C)
+#define BIT_SET_DDMACH2_DLEN_8821C(x, v) \
+ (BIT_CLEAR_DDMACH2_DLEN_8821C(x) | BIT_DDMACH2_DLEN_8821C(v))
/* 2 REG_DDMA_CH3SA_8821C */
#define BIT_SHIFT_DDMACH3_SA_8821C 0
#define BIT_MASK_DDMACH3_SA_8821C 0xffffffffL
-#define BIT_DDMACH3_SA_8821C(x) (((x) & BIT_MASK_DDMACH3_SA_8821C) << BIT_SHIFT_DDMACH3_SA_8821C)
-#define BIT_GET_DDMACH3_SA_8821C(x) (((x) >> BIT_SHIFT_DDMACH3_SA_8821C) & BIT_MASK_DDMACH3_SA_8821C)
-
+#define BIT_DDMACH3_SA_8821C(x) \
+ (((x) & BIT_MASK_DDMACH3_SA_8821C) << BIT_SHIFT_DDMACH3_SA_8821C)
+#define BITS_DDMACH3_SA_8821C \
+ (BIT_MASK_DDMACH3_SA_8821C << BIT_SHIFT_DDMACH3_SA_8821C)
+#define BIT_CLEAR_DDMACH3_SA_8821C(x) ((x) & (~BITS_DDMACH3_SA_8821C))
+#define BIT_GET_DDMACH3_SA_8821C(x) \
+ (((x) >> BIT_SHIFT_DDMACH3_SA_8821C) & BIT_MASK_DDMACH3_SA_8821C)
+#define BIT_SET_DDMACH3_SA_8821C(x, v) \
+ (BIT_CLEAR_DDMACH3_SA_8821C(x) | BIT_DDMACH3_SA_8821C(v))
/* 2 REG_DDMA_CH3DA_8821C */
#define BIT_SHIFT_DDMACH3_DA_8821C 0
#define BIT_MASK_DDMACH3_DA_8821C 0xffffffffL
-#define BIT_DDMACH3_DA_8821C(x) (((x) & BIT_MASK_DDMACH3_DA_8821C) << BIT_SHIFT_DDMACH3_DA_8821C)
-#define BIT_GET_DDMACH3_DA_8821C(x) (((x) >> BIT_SHIFT_DDMACH3_DA_8821C) & BIT_MASK_DDMACH3_DA_8821C)
-
+#define BIT_DDMACH3_DA_8821C(x) \
+ (((x) & BIT_MASK_DDMACH3_DA_8821C) << BIT_SHIFT_DDMACH3_DA_8821C)
+#define BITS_DDMACH3_DA_8821C \
+ (BIT_MASK_DDMACH3_DA_8821C << BIT_SHIFT_DDMACH3_DA_8821C)
+#define BIT_CLEAR_DDMACH3_DA_8821C(x) ((x) & (~BITS_DDMACH3_DA_8821C))
+#define BIT_GET_DDMACH3_DA_8821C(x) \
+ (((x) >> BIT_SHIFT_DDMACH3_DA_8821C) & BIT_MASK_DDMACH3_DA_8821C)
+#define BIT_SET_DDMACH3_DA_8821C(x, v) \
+ (BIT_CLEAR_DDMACH3_DA_8821C(x) | BIT_DDMACH3_DA_8821C(v))
/* 2 REG_DDMA_CH3CTRL_8821C */
#define BIT_DDMACH3_OWN_8821C BIT(31)
+#define BIT_DDMACH3_IDMEM_ERR_8821C BIT(30)
#define BIT_DDMACH3_CHKSUM_EN_8821C BIT(29)
#define BIT_DDMACH3_DA_W_DISABLE_8821C BIT(28)
#define BIT_DDMACH3_CHKSUM_STS_8821C BIT(27)
@@ -3725,28 +6812,47 @@
#define BIT_SHIFT_DDMACH3_DLEN_8821C 0
#define BIT_MASK_DDMACH3_DLEN_8821C 0x3ffff
-#define BIT_DDMACH3_DLEN_8821C(x) (((x) & BIT_MASK_DDMACH3_DLEN_8821C) << BIT_SHIFT_DDMACH3_DLEN_8821C)
-#define BIT_GET_DDMACH3_DLEN_8821C(x) (((x) >> BIT_SHIFT_DDMACH3_DLEN_8821C) & BIT_MASK_DDMACH3_DLEN_8821C)
-
+#define BIT_DDMACH3_DLEN_8821C(x) \
+ (((x) & BIT_MASK_DDMACH3_DLEN_8821C) << BIT_SHIFT_DDMACH3_DLEN_8821C)
+#define BITS_DDMACH3_DLEN_8821C \
+ (BIT_MASK_DDMACH3_DLEN_8821C << BIT_SHIFT_DDMACH3_DLEN_8821C)
+#define BIT_CLEAR_DDMACH3_DLEN_8821C(x) ((x) & (~BITS_DDMACH3_DLEN_8821C))
+#define BIT_GET_DDMACH3_DLEN_8821C(x) \
+ (((x) >> BIT_SHIFT_DDMACH3_DLEN_8821C) & BIT_MASK_DDMACH3_DLEN_8821C)
+#define BIT_SET_DDMACH3_DLEN_8821C(x, v) \
+ (BIT_CLEAR_DDMACH3_DLEN_8821C(x) | BIT_DDMACH3_DLEN_8821C(v))
/* 2 REG_DDMA_CH4SA_8821C */
#define BIT_SHIFT_DDMACH4_SA_8821C 0
#define BIT_MASK_DDMACH4_SA_8821C 0xffffffffL
-#define BIT_DDMACH4_SA_8821C(x) (((x) & BIT_MASK_DDMACH4_SA_8821C) << BIT_SHIFT_DDMACH4_SA_8821C)
-#define BIT_GET_DDMACH4_SA_8821C(x) (((x) >> BIT_SHIFT_DDMACH4_SA_8821C) & BIT_MASK_DDMACH4_SA_8821C)
-
+#define BIT_DDMACH4_SA_8821C(x) \
+ (((x) & BIT_MASK_DDMACH4_SA_8821C) << BIT_SHIFT_DDMACH4_SA_8821C)
+#define BITS_DDMACH4_SA_8821C \
+ (BIT_MASK_DDMACH4_SA_8821C << BIT_SHIFT_DDMACH4_SA_8821C)
+#define BIT_CLEAR_DDMACH4_SA_8821C(x) ((x) & (~BITS_DDMACH4_SA_8821C))
+#define BIT_GET_DDMACH4_SA_8821C(x) \
+ (((x) >> BIT_SHIFT_DDMACH4_SA_8821C) & BIT_MASK_DDMACH4_SA_8821C)
+#define BIT_SET_DDMACH4_SA_8821C(x, v) \
+ (BIT_CLEAR_DDMACH4_SA_8821C(x) | BIT_DDMACH4_SA_8821C(v))
/* 2 REG_DDMA_CH4DA_8821C */
#define BIT_SHIFT_DDMACH4_DA_8821C 0
#define BIT_MASK_DDMACH4_DA_8821C 0xffffffffL
-#define BIT_DDMACH4_DA_8821C(x) (((x) & BIT_MASK_DDMACH4_DA_8821C) << BIT_SHIFT_DDMACH4_DA_8821C)
-#define BIT_GET_DDMACH4_DA_8821C(x) (((x) >> BIT_SHIFT_DDMACH4_DA_8821C) & BIT_MASK_DDMACH4_DA_8821C)
-
+#define BIT_DDMACH4_DA_8821C(x) \
+ (((x) & BIT_MASK_DDMACH4_DA_8821C) << BIT_SHIFT_DDMACH4_DA_8821C)
+#define BITS_DDMACH4_DA_8821C \
+ (BIT_MASK_DDMACH4_DA_8821C << BIT_SHIFT_DDMACH4_DA_8821C)
+#define BIT_CLEAR_DDMACH4_DA_8821C(x) ((x) & (~BITS_DDMACH4_DA_8821C))
+#define BIT_GET_DDMACH4_DA_8821C(x) \
+ (((x) >> BIT_SHIFT_DDMACH4_DA_8821C) & BIT_MASK_DDMACH4_DA_8821C)
+#define BIT_SET_DDMACH4_DA_8821C(x, v) \
+ (BIT_CLEAR_DDMACH4_DA_8821C(x) | BIT_DDMACH4_DA_8821C(v))
/* 2 REG_DDMA_CH4CTRL_8821C */
#define BIT_DDMACH4_OWN_8821C BIT(31)
+#define BIT_DDMACH4_IDMEM_ERR_8821C BIT(30)
#define BIT_DDMACH4_CHKSUM_EN_8821C BIT(29)
#define BIT_DDMACH4_DA_W_DISABLE_8821C BIT(28)
#define BIT_DDMACH4_CHKSUM_STS_8821C BIT(27)
@@ -3756,28 +6862,47 @@
#define BIT_SHIFT_DDMACH4_DLEN_8821C 0
#define BIT_MASK_DDMACH4_DLEN_8821C 0x3ffff
-#define BIT_DDMACH4_DLEN_8821C(x) (((x) & BIT_MASK_DDMACH4_DLEN_8821C) << BIT_SHIFT_DDMACH4_DLEN_8821C)
-#define BIT_GET_DDMACH4_DLEN_8821C(x) (((x) >> BIT_SHIFT_DDMACH4_DLEN_8821C) & BIT_MASK_DDMACH4_DLEN_8821C)
-
+#define BIT_DDMACH4_DLEN_8821C(x) \
+ (((x) & BIT_MASK_DDMACH4_DLEN_8821C) << BIT_SHIFT_DDMACH4_DLEN_8821C)
+#define BITS_DDMACH4_DLEN_8821C \
+ (BIT_MASK_DDMACH4_DLEN_8821C << BIT_SHIFT_DDMACH4_DLEN_8821C)
+#define BIT_CLEAR_DDMACH4_DLEN_8821C(x) ((x) & (~BITS_DDMACH4_DLEN_8821C))
+#define BIT_GET_DDMACH4_DLEN_8821C(x) \
+ (((x) >> BIT_SHIFT_DDMACH4_DLEN_8821C) & BIT_MASK_DDMACH4_DLEN_8821C)
+#define BIT_SET_DDMACH4_DLEN_8821C(x, v) \
+ (BIT_CLEAR_DDMACH4_DLEN_8821C(x) | BIT_DDMACH4_DLEN_8821C(v))
/* 2 REG_DDMA_CH5SA_8821C */
#define BIT_SHIFT_DDMACH5_SA_8821C 0
#define BIT_MASK_DDMACH5_SA_8821C 0xffffffffL
-#define BIT_DDMACH5_SA_8821C(x) (((x) & BIT_MASK_DDMACH5_SA_8821C) << BIT_SHIFT_DDMACH5_SA_8821C)
-#define BIT_GET_DDMACH5_SA_8821C(x) (((x) >> BIT_SHIFT_DDMACH5_SA_8821C) & BIT_MASK_DDMACH5_SA_8821C)
-
+#define BIT_DDMACH5_SA_8821C(x) \
+ (((x) & BIT_MASK_DDMACH5_SA_8821C) << BIT_SHIFT_DDMACH5_SA_8821C)
+#define BITS_DDMACH5_SA_8821C \
+ (BIT_MASK_DDMACH5_SA_8821C << BIT_SHIFT_DDMACH5_SA_8821C)
+#define BIT_CLEAR_DDMACH5_SA_8821C(x) ((x) & (~BITS_DDMACH5_SA_8821C))
+#define BIT_GET_DDMACH5_SA_8821C(x) \
+ (((x) >> BIT_SHIFT_DDMACH5_SA_8821C) & BIT_MASK_DDMACH5_SA_8821C)
+#define BIT_SET_DDMACH5_SA_8821C(x, v) \
+ (BIT_CLEAR_DDMACH5_SA_8821C(x) | BIT_DDMACH5_SA_8821C(v))
/* 2 REG_DDMA_CH5DA_8821C */
#define BIT_SHIFT_DDMACH5_DA_8821C 0
#define BIT_MASK_DDMACH5_DA_8821C 0xffffffffL
-#define BIT_DDMACH5_DA_8821C(x) (((x) & BIT_MASK_DDMACH5_DA_8821C) << BIT_SHIFT_DDMACH5_DA_8821C)
-#define BIT_GET_DDMACH5_DA_8821C(x) (((x) >> BIT_SHIFT_DDMACH5_DA_8821C) & BIT_MASK_DDMACH5_DA_8821C)
-
-
-/* 2 REG_REG_DDMA_CH5CTRL_8821C */
+#define BIT_DDMACH5_DA_8821C(x) \
+ (((x) & BIT_MASK_DDMACH5_DA_8821C) << BIT_SHIFT_DDMACH5_DA_8821C)
+#define BITS_DDMACH5_DA_8821C \
+ (BIT_MASK_DDMACH5_DA_8821C << BIT_SHIFT_DDMACH5_DA_8821C)
+#define BIT_CLEAR_DDMACH5_DA_8821C(x) ((x) & (~BITS_DDMACH5_DA_8821C))
+#define BIT_GET_DDMACH5_DA_8821C(x) \
+ (((x) >> BIT_SHIFT_DDMACH5_DA_8821C) & BIT_MASK_DDMACH5_DA_8821C)
+#define BIT_SET_DDMACH5_DA_8821C(x, v) \
+ (BIT_CLEAR_DDMACH5_DA_8821C(x) | BIT_DDMACH5_DA_8821C(v))
+
+/* 2 REG_DDMA_CH5CTRL_8821C */
#define BIT_DDMACH5_OWN_8821C BIT(31)
+#define BIT_DDMACH5_IDMEM_ERR_8821C BIT(30)
#define BIT_DDMACH5_CHKSUM_EN_8821C BIT(29)
#define BIT_DDMACH5_DA_W_DISABLE_8821C BIT(28)
#define BIT_DDMACH5_CHKSUM_STS_8821C BIT(27)
@@ -3787,9 +6912,15 @@
#define BIT_SHIFT_DDMACH5_DLEN_8821C 0
#define BIT_MASK_DDMACH5_DLEN_8821C 0x3ffff
-#define BIT_DDMACH5_DLEN_8821C(x) (((x) & BIT_MASK_DDMACH5_DLEN_8821C) << BIT_SHIFT_DDMACH5_DLEN_8821C)
-#define BIT_GET_DDMACH5_DLEN_8821C(x) (((x) >> BIT_SHIFT_DDMACH5_DLEN_8821C) & BIT_MASK_DDMACH5_DLEN_8821C)
-
+#define BIT_DDMACH5_DLEN_8821C(x) \
+ (((x) & BIT_MASK_DDMACH5_DLEN_8821C) << BIT_SHIFT_DDMACH5_DLEN_8821C)
+#define BITS_DDMACH5_DLEN_8821C \
+ (BIT_MASK_DDMACH5_DLEN_8821C << BIT_SHIFT_DDMACH5_DLEN_8821C)
+#define BIT_CLEAR_DDMACH5_DLEN_8821C(x) ((x) & (~BITS_DDMACH5_DLEN_8821C))
+#define BIT_GET_DDMACH5_DLEN_8821C(x) \
+ (((x) >> BIT_SHIFT_DDMACH5_DLEN_8821C) & BIT_MASK_DDMACH5_DLEN_8821C)
+#define BIT_SET_DDMACH5_DLEN_8821C(x, v) \
+ (BIT_CLEAR_DDMACH5_DLEN_8821C(x) | BIT_DDMACH5_DLEN_8821C(v))
/* 2 REG_DDMA_INT_MSK_8821C */
#define BIT_DDMACH5_MSK_8821C BIT(5)
@@ -3811,9 +6942,15 @@
#define BIT_SHIFT_IDDMA0_CHKSUM_8821C 0
#define BIT_MASK_IDDMA0_CHKSUM_8821C 0xffff
-#define BIT_IDDMA0_CHKSUM_8821C(x) (((x) & BIT_MASK_IDDMA0_CHKSUM_8821C) << BIT_SHIFT_IDDMA0_CHKSUM_8821C)
-#define BIT_GET_IDDMA0_CHKSUM_8821C(x) (((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8821C) & BIT_MASK_IDDMA0_CHKSUM_8821C)
-
+#define BIT_IDDMA0_CHKSUM_8821C(x) \
+ (((x) & BIT_MASK_IDDMA0_CHKSUM_8821C) << BIT_SHIFT_IDDMA0_CHKSUM_8821C)
+#define BITS_IDDMA0_CHKSUM_8821C \
+ (BIT_MASK_IDDMA0_CHKSUM_8821C << BIT_SHIFT_IDDMA0_CHKSUM_8821C)
+#define BIT_CLEAR_IDDMA0_CHKSUM_8821C(x) ((x) & (~BITS_IDDMA0_CHKSUM_8821C))
+#define BIT_GET_IDDMA0_CHKSUM_8821C(x) \
+ (((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8821C) & BIT_MASK_IDDMA0_CHKSUM_8821C)
+#define BIT_SET_IDDMA0_CHKSUM_8821C(x, v) \
+ (BIT_CLEAR_IDDMA0_CHKSUM_8821C(x) | BIT_IDDMA0_CHKSUM_8821C(v))
/* 2 REG_DDMA_MONITOR_8821C */
#define BIT_IDDMA0_PERMU_UNDERFLOW_8821C BIT(14)
@@ -3833,15 +6970,33 @@
#define BIT_SHIFT_PCIE_MAX_RXDMA_8821C 28
#define BIT_MASK_PCIE_MAX_RXDMA_8821C 0x7
-#define BIT_PCIE_MAX_RXDMA_8821C(x) (((x) & BIT_MASK_PCIE_MAX_RXDMA_8821C) << BIT_SHIFT_PCIE_MAX_RXDMA_8821C)
-#define BIT_GET_PCIE_MAX_RXDMA_8821C(x) (((x) >> BIT_SHIFT_PCIE_MAX_RXDMA_8821C) & BIT_MASK_PCIE_MAX_RXDMA_8821C)
+#define BIT_PCIE_MAX_RXDMA_8821C(x) \
+ (((x) & BIT_MASK_PCIE_MAX_RXDMA_8821C) \
+ << BIT_SHIFT_PCIE_MAX_RXDMA_8821C)
+#define BITS_PCIE_MAX_RXDMA_8821C \
+ (BIT_MASK_PCIE_MAX_RXDMA_8821C << BIT_SHIFT_PCIE_MAX_RXDMA_8821C)
+#define BIT_CLEAR_PCIE_MAX_RXDMA_8821C(x) ((x) & (~BITS_PCIE_MAX_RXDMA_8821C))
+#define BIT_GET_PCIE_MAX_RXDMA_8821C(x) \
+ (((x) >> BIT_SHIFT_PCIE_MAX_RXDMA_8821C) & \
+ BIT_MASK_PCIE_MAX_RXDMA_8821C)
+#define BIT_SET_PCIE_MAX_RXDMA_8821C(x, v) \
+ (BIT_CLEAR_PCIE_MAX_RXDMA_8821C(x) | BIT_PCIE_MAX_RXDMA_8821C(v))
#define BIT_MULRW_8821C BIT(27)
#define BIT_SHIFT_PCIE_MAX_TXDMA_8821C 24
#define BIT_MASK_PCIE_MAX_TXDMA_8821C 0x7
-#define BIT_PCIE_MAX_TXDMA_8821C(x) (((x) & BIT_MASK_PCIE_MAX_TXDMA_8821C) << BIT_SHIFT_PCIE_MAX_TXDMA_8821C)
-#define BIT_GET_PCIE_MAX_TXDMA_8821C(x) (((x) >> BIT_SHIFT_PCIE_MAX_TXDMA_8821C) & BIT_MASK_PCIE_MAX_TXDMA_8821C)
+#define BIT_PCIE_MAX_TXDMA_8821C(x) \
+ (((x) & BIT_MASK_PCIE_MAX_TXDMA_8821C) \
+ << BIT_SHIFT_PCIE_MAX_TXDMA_8821C)
+#define BITS_PCIE_MAX_TXDMA_8821C \
+ (BIT_MASK_PCIE_MAX_TXDMA_8821C << BIT_SHIFT_PCIE_MAX_TXDMA_8821C)
+#define BIT_CLEAR_PCIE_MAX_TXDMA_8821C(x) ((x) & (~BITS_PCIE_MAX_TXDMA_8821C))
+#define BIT_GET_PCIE_MAX_TXDMA_8821C(x) \
+ (((x) >> BIT_SHIFT_PCIE_MAX_TXDMA_8821C) & \
+ BIT_MASK_PCIE_MAX_TXDMA_8821C)
+#define BIT_SET_PCIE_MAX_TXDMA_8821C(x, v) \
+ (BIT_CLEAR_PCIE_MAX_TXDMA_8821C(x) | BIT_PCIE_MAX_TXDMA_8821C(v))
#define BIT_EN_CPL_TIMEOUT_PS_8821C BIT(22)
#define BIT_REG_TXDMA_FAIL_PS_8821C BIT(21)
@@ -3871,378 +7026,729 @@
#define BIT_SHIFT_TXTTIMER_MATCH_NUM_8821C 28
#define BIT_MASK_TXTTIMER_MATCH_NUM_8821C 0xf
-#define BIT_TXTTIMER_MATCH_NUM_8821C(x) (((x) & BIT_MASK_TXTTIMER_MATCH_NUM_8821C) << BIT_SHIFT_TXTTIMER_MATCH_NUM_8821C)
-#define BIT_GET_TXTTIMER_MATCH_NUM_8821C(x) (((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM_8821C) & BIT_MASK_TXTTIMER_MATCH_NUM_8821C)
-
+#define BIT_TXTTIMER_MATCH_NUM_8821C(x) \
+ (((x) & BIT_MASK_TXTTIMER_MATCH_NUM_8821C) \
+ << BIT_SHIFT_TXTTIMER_MATCH_NUM_8821C)
+#define BITS_TXTTIMER_MATCH_NUM_8821C \
+ (BIT_MASK_TXTTIMER_MATCH_NUM_8821C \
+ << BIT_SHIFT_TXTTIMER_MATCH_NUM_8821C)
+#define BIT_CLEAR_TXTTIMER_MATCH_NUM_8821C(x) \
+ ((x) & (~BITS_TXTTIMER_MATCH_NUM_8821C))
+#define BIT_GET_TXTTIMER_MATCH_NUM_8821C(x) \
+ (((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM_8821C) & \
+ BIT_MASK_TXTTIMER_MATCH_NUM_8821C)
+#define BIT_SET_TXTTIMER_MATCH_NUM_8821C(x, v) \
+ (BIT_CLEAR_TXTTIMER_MATCH_NUM_8821C(x) | \
+ BIT_TXTTIMER_MATCH_NUM_8821C(v))
#define BIT_SHIFT_TXPKT_NUM_MATCH_8821C 24
#define BIT_MASK_TXPKT_NUM_MATCH_8821C 0xf
-#define BIT_TXPKT_NUM_MATCH_8821C(x) (((x) & BIT_MASK_TXPKT_NUM_MATCH_8821C) << BIT_SHIFT_TXPKT_NUM_MATCH_8821C)
-#define BIT_GET_TXPKT_NUM_MATCH_8821C(x) (((x) >> BIT_SHIFT_TXPKT_NUM_MATCH_8821C) & BIT_MASK_TXPKT_NUM_MATCH_8821C)
-
+#define BIT_TXPKT_NUM_MATCH_8821C(x) \
+ (((x) & BIT_MASK_TXPKT_NUM_MATCH_8821C) \
+ << BIT_SHIFT_TXPKT_NUM_MATCH_8821C)
+#define BITS_TXPKT_NUM_MATCH_8821C \
+ (BIT_MASK_TXPKT_NUM_MATCH_8821C << BIT_SHIFT_TXPKT_NUM_MATCH_8821C)
+#define BIT_CLEAR_TXPKT_NUM_MATCH_8821C(x) ((x) & (~BITS_TXPKT_NUM_MATCH_8821C))
+#define BIT_GET_TXPKT_NUM_MATCH_8821C(x) \
+ (((x) >> BIT_SHIFT_TXPKT_NUM_MATCH_8821C) & \
+ BIT_MASK_TXPKT_NUM_MATCH_8821C)
+#define BIT_SET_TXPKT_NUM_MATCH_8821C(x, v) \
+ (BIT_CLEAR_TXPKT_NUM_MATCH_8821C(x) | BIT_TXPKT_NUM_MATCH_8821C(v))
#define BIT_SHIFT_RXTTIMER_MATCH_NUM_8821C 20
#define BIT_MASK_RXTTIMER_MATCH_NUM_8821C 0xf
-#define BIT_RXTTIMER_MATCH_NUM_8821C(x) (((x) & BIT_MASK_RXTTIMER_MATCH_NUM_8821C) << BIT_SHIFT_RXTTIMER_MATCH_NUM_8821C)
-#define BIT_GET_RXTTIMER_MATCH_NUM_8821C(x) (((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM_8821C) & BIT_MASK_RXTTIMER_MATCH_NUM_8821C)
-
+#define BIT_RXTTIMER_MATCH_NUM_8821C(x) \
+ (((x) & BIT_MASK_RXTTIMER_MATCH_NUM_8821C) \
+ << BIT_SHIFT_RXTTIMER_MATCH_NUM_8821C)
+#define BITS_RXTTIMER_MATCH_NUM_8821C \
+ (BIT_MASK_RXTTIMER_MATCH_NUM_8821C \
+ << BIT_SHIFT_RXTTIMER_MATCH_NUM_8821C)
+#define BIT_CLEAR_RXTTIMER_MATCH_NUM_8821C(x) \
+ ((x) & (~BITS_RXTTIMER_MATCH_NUM_8821C))
+#define BIT_GET_RXTTIMER_MATCH_NUM_8821C(x) \
+ (((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM_8821C) & \
+ BIT_MASK_RXTTIMER_MATCH_NUM_8821C)
+#define BIT_SET_RXTTIMER_MATCH_NUM_8821C(x, v) \
+ (BIT_CLEAR_RXTTIMER_MATCH_NUM_8821C(x) | \
+ BIT_RXTTIMER_MATCH_NUM_8821C(v))
#define BIT_SHIFT_RXPKT_NUM_MATCH_8821C 16
#define BIT_MASK_RXPKT_NUM_MATCH_8821C 0xf
-#define BIT_RXPKT_NUM_MATCH_8821C(x) (((x) & BIT_MASK_RXPKT_NUM_MATCH_8821C) << BIT_SHIFT_RXPKT_NUM_MATCH_8821C)
-#define BIT_GET_RXPKT_NUM_MATCH_8821C(x) (((x) >> BIT_SHIFT_RXPKT_NUM_MATCH_8821C) & BIT_MASK_RXPKT_NUM_MATCH_8821C)
-
+#define BIT_RXPKT_NUM_MATCH_8821C(x) \
+ (((x) & BIT_MASK_RXPKT_NUM_MATCH_8821C) \
+ << BIT_SHIFT_RXPKT_NUM_MATCH_8821C)
+#define BITS_RXPKT_NUM_MATCH_8821C \
+ (BIT_MASK_RXPKT_NUM_MATCH_8821C << BIT_SHIFT_RXPKT_NUM_MATCH_8821C)
+#define BIT_CLEAR_RXPKT_NUM_MATCH_8821C(x) ((x) & (~BITS_RXPKT_NUM_MATCH_8821C))
+#define BIT_GET_RXPKT_NUM_MATCH_8821C(x) \
+ (((x) >> BIT_SHIFT_RXPKT_NUM_MATCH_8821C) & \
+ BIT_MASK_RXPKT_NUM_MATCH_8821C)
+#define BIT_SET_RXPKT_NUM_MATCH_8821C(x, v) \
+ (BIT_CLEAR_RXPKT_NUM_MATCH_8821C(x) | BIT_RXPKT_NUM_MATCH_8821C(v))
#define BIT_SHIFT_MIGRATE_TIMER_8821C 0
#define BIT_MASK_MIGRATE_TIMER_8821C 0xffff
-#define BIT_MIGRATE_TIMER_8821C(x) (((x) & BIT_MASK_MIGRATE_TIMER_8821C) << BIT_SHIFT_MIGRATE_TIMER_8821C)
-#define BIT_GET_MIGRATE_TIMER_8821C(x) (((x) >> BIT_SHIFT_MIGRATE_TIMER_8821C) & BIT_MASK_MIGRATE_TIMER_8821C)
-
+#define BIT_MIGRATE_TIMER_8821C(x) \
+ (((x) & BIT_MASK_MIGRATE_TIMER_8821C) << BIT_SHIFT_MIGRATE_TIMER_8821C)
+#define BITS_MIGRATE_TIMER_8821C \
+ (BIT_MASK_MIGRATE_TIMER_8821C << BIT_SHIFT_MIGRATE_TIMER_8821C)
+#define BIT_CLEAR_MIGRATE_TIMER_8821C(x) ((x) & (~BITS_MIGRATE_TIMER_8821C))
+#define BIT_GET_MIGRATE_TIMER_8821C(x) \
+ (((x) >> BIT_SHIFT_MIGRATE_TIMER_8821C) & BIT_MASK_MIGRATE_TIMER_8821C)
+#define BIT_SET_MIGRATE_TIMER_8821C(x, v) \
+ (BIT_CLEAR_MIGRATE_TIMER_8821C(x) | BIT_MIGRATE_TIMER_8821C(v))
/* 2 REG_BCNQ_TXBD_DESA_8821C */
#define BIT_SHIFT_BCNQ_TXBD_DESA_8821C 0
#define BIT_MASK_BCNQ_TXBD_DESA_8821C 0xffffffffffffffffL
-#define BIT_BCNQ_TXBD_DESA_8821C(x) (((x) & BIT_MASK_BCNQ_TXBD_DESA_8821C) << BIT_SHIFT_BCNQ_TXBD_DESA_8821C)
-#define BIT_GET_BCNQ_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_BCNQ_TXBD_DESA_8821C) & BIT_MASK_BCNQ_TXBD_DESA_8821C)
-
+#define BIT_BCNQ_TXBD_DESA_8821C(x) \
+ (((x) & BIT_MASK_BCNQ_TXBD_DESA_8821C) \
+ << BIT_SHIFT_BCNQ_TXBD_DESA_8821C)
+#define BITS_BCNQ_TXBD_DESA_8821C \
+ (BIT_MASK_BCNQ_TXBD_DESA_8821C << BIT_SHIFT_BCNQ_TXBD_DESA_8821C)
+#define BIT_CLEAR_BCNQ_TXBD_DESA_8821C(x) ((x) & (~BITS_BCNQ_TXBD_DESA_8821C))
+#define BIT_GET_BCNQ_TXBD_DESA_8821C(x) \
+ (((x) >> BIT_SHIFT_BCNQ_TXBD_DESA_8821C) & \
+ BIT_MASK_BCNQ_TXBD_DESA_8821C)
+#define BIT_SET_BCNQ_TXBD_DESA_8821C(x, v) \
+ (BIT_CLEAR_BCNQ_TXBD_DESA_8821C(x) | BIT_BCNQ_TXBD_DESA_8821C(v))
/* 2 REG_MGQ_TXBD_DESA_8821C */
#define BIT_SHIFT_MGQ_TXBD_DESA_8821C 0
#define BIT_MASK_MGQ_TXBD_DESA_8821C 0xffffffffffffffffL
-#define BIT_MGQ_TXBD_DESA_8821C(x) (((x) & BIT_MASK_MGQ_TXBD_DESA_8821C) << BIT_SHIFT_MGQ_TXBD_DESA_8821C)
-#define BIT_GET_MGQ_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_MGQ_TXBD_DESA_8821C) & BIT_MASK_MGQ_TXBD_DESA_8821C)
-
+#define BIT_MGQ_TXBD_DESA_8821C(x) \
+ (((x) & BIT_MASK_MGQ_TXBD_DESA_8821C) << BIT_SHIFT_MGQ_TXBD_DESA_8821C)
+#define BITS_MGQ_TXBD_DESA_8821C \
+ (BIT_MASK_MGQ_TXBD_DESA_8821C << BIT_SHIFT_MGQ_TXBD_DESA_8821C)
+#define BIT_CLEAR_MGQ_TXBD_DESA_8821C(x) ((x) & (~BITS_MGQ_TXBD_DESA_8821C))
+#define BIT_GET_MGQ_TXBD_DESA_8821C(x) \
+ (((x) >> BIT_SHIFT_MGQ_TXBD_DESA_8821C) & BIT_MASK_MGQ_TXBD_DESA_8821C)
+#define BIT_SET_MGQ_TXBD_DESA_8821C(x, v) \
+ (BIT_CLEAR_MGQ_TXBD_DESA_8821C(x) | BIT_MGQ_TXBD_DESA_8821C(v))
/* 2 REG_VOQ_TXBD_DESA_8821C */
#define BIT_SHIFT_VOQ_TXBD_DESA_8821C 0
#define BIT_MASK_VOQ_TXBD_DESA_8821C 0xffffffffffffffffL
-#define BIT_VOQ_TXBD_DESA_8821C(x) (((x) & BIT_MASK_VOQ_TXBD_DESA_8821C) << BIT_SHIFT_VOQ_TXBD_DESA_8821C)
-#define BIT_GET_VOQ_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_VOQ_TXBD_DESA_8821C) & BIT_MASK_VOQ_TXBD_DESA_8821C)
-
+#define BIT_VOQ_TXBD_DESA_8821C(x) \
+ (((x) & BIT_MASK_VOQ_TXBD_DESA_8821C) << BIT_SHIFT_VOQ_TXBD_DESA_8821C)
+#define BITS_VOQ_TXBD_DESA_8821C \
+ (BIT_MASK_VOQ_TXBD_DESA_8821C << BIT_SHIFT_VOQ_TXBD_DESA_8821C)
+#define BIT_CLEAR_VOQ_TXBD_DESA_8821C(x) ((x) & (~BITS_VOQ_TXBD_DESA_8821C))
+#define BIT_GET_VOQ_TXBD_DESA_8821C(x) \
+ (((x) >> BIT_SHIFT_VOQ_TXBD_DESA_8821C) & BIT_MASK_VOQ_TXBD_DESA_8821C)
+#define BIT_SET_VOQ_TXBD_DESA_8821C(x, v) \
+ (BIT_CLEAR_VOQ_TXBD_DESA_8821C(x) | BIT_VOQ_TXBD_DESA_8821C(v))
/* 2 REG_VIQ_TXBD_DESA_8821C */
#define BIT_SHIFT_VIQ_TXBD_DESA_8821C 0
#define BIT_MASK_VIQ_TXBD_DESA_8821C 0xffffffffffffffffL
-#define BIT_VIQ_TXBD_DESA_8821C(x) (((x) & BIT_MASK_VIQ_TXBD_DESA_8821C) << BIT_SHIFT_VIQ_TXBD_DESA_8821C)
-#define BIT_GET_VIQ_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_VIQ_TXBD_DESA_8821C) & BIT_MASK_VIQ_TXBD_DESA_8821C)
-
+#define BIT_VIQ_TXBD_DESA_8821C(x) \
+ (((x) & BIT_MASK_VIQ_TXBD_DESA_8821C) << BIT_SHIFT_VIQ_TXBD_DESA_8821C)
+#define BITS_VIQ_TXBD_DESA_8821C \
+ (BIT_MASK_VIQ_TXBD_DESA_8821C << BIT_SHIFT_VIQ_TXBD_DESA_8821C)
+#define BIT_CLEAR_VIQ_TXBD_DESA_8821C(x) ((x) & (~BITS_VIQ_TXBD_DESA_8821C))
+#define BIT_GET_VIQ_TXBD_DESA_8821C(x) \
+ (((x) >> BIT_SHIFT_VIQ_TXBD_DESA_8821C) & BIT_MASK_VIQ_TXBD_DESA_8821C)
+#define BIT_SET_VIQ_TXBD_DESA_8821C(x, v) \
+ (BIT_CLEAR_VIQ_TXBD_DESA_8821C(x) | BIT_VIQ_TXBD_DESA_8821C(v))
/* 2 REG_BEQ_TXBD_DESA_8821C */
#define BIT_SHIFT_BEQ_TXBD_DESA_8821C 0
#define BIT_MASK_BEQ_TXBD_DESA_8821C 0xffffffffffffffffL
-#define BIT_BEQ_TXBD_DESA_8821C(x) (((x) & BIT_MASK_BEQ_TXBD_DESA_8821C) << BIT_SHIFT_BEQ_TXBD_DESA_8821C)
-#define BIT_GET_BEQ_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_BEQ_TXBD_DESA_8821C) & BIT_MASK_BEQ_TXBD_DESA_8821C)
-
+#define BIT_BEQ_TXBD_DESA_8821C(x) \
+ (((x) & BIT_MASK_BEQ_TXBD_DESA_8821C) << BIT_SHIFT_BEQ_TXBD_DESA_8821C)
+#define BITS_BEQ_TXBD_DESA_8821C \
+ (BIT_MASK_BEQ_TXBD_DESA_8821C << BIT_SHIFT_BEQ_TXBD_DESA_8821C)
+#define BIT_CLEAR_BEQ_TXBD_DESA_8821C(x) ((x) & (~BITS_BEQ_TXBD_DESA_8821C))
+#define BIT_GET_BEQ_TXBD_DESA_8821C(x) \
+ (((x) >> BIT_SHIFT_BEQ_TXBD_DESA_8821C) & BIT_MASK_BEQ_TXBD_DESA_8821C)
+#define BIT_SET_BEQ_TXBD_DESA_8821C(x, v) \
+ (BIT_CLEAR_BEQ_TXBD_DESA_8821C(x) | BIT_BEQ_TXBD_DESA_8821C(v))
/* 2 REG_BKQ_TXBD_DESA_8821C */
#define BIT_SHIFT_BKQ_TXBD_DESA_8821C 0
#define BIT_MASK_BKQ_TXBD_DESA_8821C 0xffffffffffffffffL
-#define BIT_BKQ_TXBD_DESA_8821C(x) (((x) & BIT_MASK_BKQ_TXBD_DESA_8821C) << BIT_SHIFT_BKQ_TXBD_DESA_8821C)
-#define BIT_GET_BKQ_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_BKQ_TXBD_DESA_8821C) & BIT_MASK_BKQ_TXBD_DESA_8821C)
-
+#define BIT_BKQ_TXBD_DESA_8821C(x) \
+ (((x) & BIT_MASK_BKQ_TXBD_DESA_8821C) << BIT_SHIFT_BKQ_TXBD_DESA_8821C)
+#define BITS_BKQ_TXBD_DESA_8821C \
+ (BIT_MASK_BKQ_TXBD_DESA_8821C << BIT_SHIFT_BKQ_TXBD_DESA_8821C)
+#define BIT_CLEAR_BKQ_TXBD_DESA_8821C(x) ((x) & (~BITS_BKQ_TXBD_DESA_8821C))
+#define BIT_GET_BKQ_TXBD_DESA_8821C(x) \
+ (((x) >> BIT_SHIFT_BKQ_TXBD_DESA_8821C) & BIT_MASK_BKQ_TXBD_DESA_8821C)
+#define BIT_SET_BKQ_TXBD_DESA_8821C(x, v) \
+ (BIT_CLEAR_BKQ_TXBD_DESA_8821C(x) | BIT_BKQ_TXBD_DESA_8821C(v))
/* 2 REG_RXQ_RXBD_DESA_8821C */
#define BIT_SHIFT_RXQ_RXBD_DESA_8821C 0
#define BIT_MASK_RXQ_RXBD_DESA_8821C 0xffffffffffffffffL
-#define BIT_RXQ_RXBD_DESA_8821C(x) (((x) & BIT_MASK_RXQ_RXBD_DESA_8821C) << BIT_SHIFT_RXQ_RXBD_DESA_8821C)
-#define BIT_GET_RXQ_RXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_RXQ_RXBD_DESA_8821C) & BIT_MASK_RXQ_RXBD_DESA_8821C)
-
+#define BIT_RXQ_RXBD_DESA_8821C(x) \
+ (((x) & BIT_MASK_RXQ_RXBD_DESA_8821C) << BIT_SHIFT_RXQ_RXBD_DESA_8821C)
+#define BITS_RXQ_RXBD_DESA_8821C \
+ (BIT_MASK_RXQ_RXBD_DESA_8821C << BIT_SHIFT_RXQ_RXBD_DESA_8821C)
+#define BIT_CLEAR_RXQ_RXBD_DESA_8821C(x) ((x) & (~BITS_RXQ_RXBD_DESA_8821C))
+#define BIT_GET_RXQ_RXBD_DESA_8821C(x) \
+ (((x) >> BIT_SHIFT_RXQ_RXBD_DESA_8821C) & BIT_MASK_RXQ_RXBD_DESA_8821C)
+#define BIT_SET_RXQ_RXBD_DESA_8821C(x, v) \
+ (BIT_CLEAR_RXQ_RXBD_DESA_8821C(x) | BIT_RXQ_RXBD_DESA_8821C(v))
/* 2 REG_HI0Q_TXBD_DESA_8821C */
#define BIT_SHIFT_HI0Q_TXBD_DESA_8821C 0
#define BIT_MASK_HI0Q_TXBD_DESA_8821C 0xffffffffffffffffL
-#define BIT_HI0Q_TXBD_DESA_8821C(x) (((x) & BIT_MASK_HI0Q_TXBD_DESA_8821C) << BIT_SHIFT_HI0Q_TXBD_DESA_8821C)
-#define BIT_GET_HI0Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_8821C) & BIT_MASK_HI0Q_TXBD_DESA_8821C)
-
+#define BIT_HI0Q_TXBD_DESA_8821C(x) \
+ (((x) & BIT_MASK_HI0Q_TXBD_DESA_8821C) \
+ << BIT_SHIFT_HI0Q_TXBD_DESA_8821C)
+#define BITS_HI0Q_TXBD_DESA_8821C \
+ (BIT_MASK_HI0Q_TXBD_DESA_8821C << BIT_SHIFT_HI0Q_TXBD_DESA_8821C)
+#define BIT_CLEAR_HI0Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI0Q_TXBD_DESA_8821C))
+#define BIT_GET_HI0Q_TXBD_DESA_8821C(x) \
+ (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_8821C) & \
+ BIT_MASK_HI0Q_TXBD_DESA_8821C)
+#define BIT_SET_HI0Q_TXBD_DESA_8821C(x, v) \
+ (BIT_CLEAR_HI0Q_TXBD_DESA_8821C(x) | BIT_HI0Q_TXBD_DESA_8821C(v))
/* 2 REG_HI1Q_TXBD_DESA_8821C */
#define BIT_SHIFT_HI1Q_TXBD_DESA_8821C 0
#define BIT_MASK_HI1Q_TXBD_DESA_8821C 0xffffffffffffffffL
-#define BIT_HI1Q_TXBD_DESA_8821C(x) (((x) & BIT_MASK_HI1Q_TXBD_DESA_8821C) << BIT_SHIFT_HI1Q_TXBD_DESA_8821C)
-#define BIT_GET_HI1Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_8821C) & BIT_MASK_HI1Q_TXBD_DESA_8821C)
-
+#define BIT_HI1Q_TXBD_DESA_8821C(x) \
+ (((x) & BIT_MASK_HI1Q_TXBD_DESA_8821C) \
+ << BIT_SHIFT_HI1Q_TXBD_DESA_8821C)
+#define BITS_HI1Q_TXBD_DESA_8821C \
+ (BIT_MASK_HI1Q_TXBD_DESA_8821C << BIT_SHIFT_HI1Q_TXBD_DESA_8821C)
+#define BIT_CLEAR_HI1Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI1Q_TXBD_DESA_8821C))
+#define BIT_GET_HI1Q_TXBD_DESA_8821C(x) \
+ (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_8821C) & \
+ BIT_MASK_HI1Q_TXBD_DESA_8821C)
+#define BIT_SET_HI1Q_TXBD_DESA_8821C(x, v) \
+ (BIT_CLEAR_HI1Q_TXBD_DESA_8821C(x) | BIT_HI1Q_TXBD_DESA_8821C(v))
/* 2 REG_HI2Q_TXBD_DESA_8821C */
#define BIT_SHIFT_HI2Q_TXBD_DESA_8821C 0
#define BIT_MASK_HI2Q_TXBD_DESA_8821C 0xffffffffffffffffL
-#define BIT_HI2Q_TXBD_DESA_8821C(x) (((x) & BIT_MASK_HI2Q_TXBD_DESA_8821C) << BIT_SHIFT_HI2Q_TXBD_DESA_8821C)
-#define BIT_GET_HI2Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_8821C) & BIT_MASK_HI2Q_TXBD_DESA_8821C)
-
+#define BIT_HI2Q_TXBD_DESA_8821C(x) \
+ (((x) & BIT_MASK_HI2Q_TXBD_DESA_8821C) \
+ << BIT_SHIFT_HI2Q_TXBD_DESA_8821C)
+#define BITS_HI2Q_TXBD_DESA_8821C \
+ (BIT_MASK_HI2Q_TXBD_DESA_8821C << BIT_SHIFT_HI2Q_TXBD_DESA_8821C)
+#define BIT_CLEAR_HI2Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI2Q_TXBD_DESA_8821C))
+#define BIT_GET_HI2Q_TXBD_DESA_8821C(x) \
+ (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_8821C) & \
+ BIT_MASK_HI2Q_TXBD_DESA_8821C)
+#define BIT_SET_HI2Q_TXBD_DESA_8821C(x, v) \
+ (BIT_CLEAR_HI2Q_TXBD_DESA_8821C(x) | BIT_HI2Q_TXBD_DESA_8821C(v))
/* 2 REG_HI3Q_TXBD_DESA_8821C */
#define BIT_SHIFT_HI3Q_TXBD_DESA_8821C 0
#define BIT_MASK_HI3Q_TXBD_DESA_8821C 0xffffffffffffffffL
-#define BIT_HI3Q_TXBD_DESA_8821C(x) (((x) & BIT_MASK_HI3Q_TXBD_DESA_8821C) << BIT_SHIFT_HI3Q_TXBD_DESA_8821C)
-#define BIT_GET_HI3Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_8821C) & BIT_MASK_HI3Q_TXBD_DESA_8821C)
-
+#define BIT_HI3Q_TXBD_DESA_8821C(x) \
+ (((x) & BIT_MASK_HI3Q_TXBD_DESA_8821C) \
+ << BIT_SHIFT_HI3Q_TXBD_DESA_8821C)
+#define BITS_HI3Q_TXBD_DESA_8821C \
+ (BIT_MASK_HI3Q_TXBD_DESA_8821C << BIT_SHIFT_HI3Q_TXBD_DESA_8821C)
+#define BIT_CLEAR_HI3Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI3Q_TXBD_DESA_8821C))
+#define BIT_GET_HI3Q_TXBD_DESA_8821C(x) \
+ (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_8821C) & \
+ BIT_MASK_HI3Q_TXBD_DESA_8821C)
+#define BIT_SET_HI3Q_TXBD_DESA_8821C(x, v) \
+ (BIT_CLEAR_HI3Q_TXBD_DESA_8821C(x) | BIT_HI3Q_TXBD_DESA_8821C(v))
/* 2 REG_HI4Q_TXBD_DESA_8821C */
#define BIT_SHIFT_HI4Q_TXBD_DESA_8821C 0
#define BIT_MASK_HI4Q_TXBD_DESA_8821C 0xffffffffffffffffL
-#define BIT_HI4Q_TXBD_DESA_8821C(x) (((x) & BIT_MASK_HI4Q_TXBD_DESA_8821C) << BIT_SHIFT_HI4Q_TXBD_DESA_8821C)
-#define BIT_GET_HI4Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_8821C) & BIT_MASK_HI4Q_TXBD_DESA_8821C)
-
+#define BIT_HI4Q_TXBD_DESA_8821C(x) \
+ (((x) & BIT_MASK_HI4Q_TXBD_DESA_8821C) \
+ << BIT_SHIFT_HI4Q_TXBD_DESA_8821C)
+#define BITS_HI4Q_TXBD_DESA_8821C \
+ (BIT_MASK_HI4Q_TXBD_DESA_8821C << BIT_SHIFT_HI4Q_TXBD_DESA_8821C)
+#define BIT_CLEAR_HI4Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI4Q_TXBD_DESA_8821C))
+#define BIT_GET_HI4Q_TXBD_DESA_8821C(x) \
+ (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_8821C) & \
+ BIT_MASK_HI4Q_TXBD_DESA_8821C)
+#define BIT_SET_HI4Q_TXBD_DESA_8821C(x, v) \
+ (BIT_CLEAR_HI4Q_TXBD_DESA_8821C(x) | BIT_HI4Q_TXBD_DESA_8821C(v))
/* 2 REG_HI5Q_TXBD_DESA_8821C */
#define BIT_SHIFT_HI5Q_TXBD_DESA_8821C 0
#define BIT_MASK_HI5Q_TXBD_DESA_8821C 0xffffffffffffffffL
-#define BIT_HI5Q_TXBD_DESA_8821C(x) (((x) & BIT_MASK_HI5Q_TXBD_DESA_8821C) << BIT_SHIFT_HI5Q_TXBD_DESA_8821C)
-#define BIT_GET_HI5Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_8821C) & BIT_MASK_HI5Q_TXBD_DESA_8821C)
-
+#define BIT_HI5Q_TXBD_DESA_8821C(x) \
+ (((x) & BIT_MASK_HI5Q_TXBD_DESA_8821C) \
+ << BIT_SHIFT_HI5Q_TXBD_DESA_8821C)
+#define BITS_HI5Q_TXBD_DESA_8821C \
+ (BIT_MASK_HI5Q_TXBD_DESA_8821C << BIT_SHIFT_HI5Q_TXBD_DESA_8821C)
+#define BIT_CLEAR_HI5Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI5Q_TXBD_DESA_8821C))
+#define BIT_GET_HI5Q_TXBD_DESA_8821C(x) \
+ (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_8821C) & \
+ BIT_MASK_HI5Q_TXBD_DESA_8821C)
+#define BIT_SET_HI5Q_TXBD_DESA_8821C(x, v) \
+ (BIT_CLEAR_HI5Q_TXBD_DESA_8821C(x) | BIT_HI5Q_TXBD_DESA_8821C(v))
/* 2 REG_HI6Q_TXBD_DESA_8821C */
#define BIT_SHIFT_HI6Q_TXBD_DESA_8821C 0
#define BIT_MASK_HI6Q_TXBD_DESA_8821C 0xffffffffffffffffL
-#define BIT_HI6Q_TXBD_DESA_8821C(x) (((x) & BIT_MASK_HI6Q_TXBD_DESA_8821C) << BIT_SHIFT_HI6Q_TXBD_DESA_8821C)
-#define BIT_GET_HI6Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_8821C) & BIT_MASK_HI6Q_TXBD_DESA_8821C)
-
+#define BIT_HI6Q_TXBD_DESA_8821C(x) \
+ (((x) & BIT_MASK_HI6Q_TXBD_DESA_8821C) \
+ << BIT_SHIFT_HI6Q_TXBD_DESA_8821C)
+#define BITS_HI6Q_TXBD_DESA_8821C \
+ (BIT_MASK_HI6Q_TXBD_DESA_8821C << BIT_SHIFT_HI6Q_TXBD_DESA_8821C)
+#define BIT_CLEAR_HI6Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI6Q_TXBD_DESA_8821C))
+#define BIT_GET_HI6Q_TXBD_DESA_8821C(x) \
+ (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_8821C) & \
+ BIT_MASK_HI6Q_TXBD_DESA_8821C)
+#define BIT_SET_HI6Q_TXBD_DESA_8821C(x, v) \
+ (BIT_CLEAR_HI6Q_TXBD_DESA_8821C(x) | BIT_HI6Q_TXBD_DESA_8821C(v))
/* 2 REG_HI7Q_TXBD_DESA_8821C */
#define BIT_SHIFT_HI7Q_TXBD_DESA_8821C 0
#define BIT_MASK_HI7Q_TXBD_DESA_8821C 0xffffffffffffffffL
-#define BIT_HI7Q_TXBD_DESA_8821C(x) (((x) & BIT_MASK_HI7Q_TXBD_DESA_8821C) << BIT_SHIFT_HI7Q_TXBD_DESA_8821C)
-#define BIT_GET_HI7Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_8821C) & BIT_MASK_HI7Q_TXBD_DESA_8821C)
-
+#define BIT_HI7Q_TXBD_DESA_8821C(x) \
+ (((x) & BIT_MASK_HI7Q_TXBD_DESA_8821C) \
+ << BIT_SHIFT_HI7Q_TXBD_DESA_8821C)
+#define BITS_HI7Q_TXBD_DESA_8821C \
+ (BIT_MASK_HI7Q_TXBD_DESA_8821C << BIT_SHIFT_HI7Q_TXBD_DESA_8821C)
+#define BIT_CLEAR_HI7Q_TXBD_DESA_8821C(x) ((x) & (~BITS_HI7Q_TXBD_DESA_8821C))
+#define BIT_GET_HI7Q_TXBD_DESA_8821C(x) \
+ (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_8821C) & \
+ BIT_MASK_HI7Q_TXBD_DESA_8821C)
+#define BIT_SET_HI7Q_TXBD_DESA_8821C(x, v) \
+ (BIT_CLEAR_HI7Q_TXBD_DESA_8821C(x) | BIT_HI7Q_TXBD_DESA_8821C(v))
/* 2 REG_MGQ_TXBD_NUM_8821C */
#define BIT_PCIE_MGQ_FLAG_8821C BIT(14)
#define BIT_SHIFT_MGQ_DESC_MODE_8821C 12
#define BIT_MASK_MGQ_DESC_MODE_8821C 0x3
-#define BIT_MGQ_DESC_MODE_8821C(x) (((x) & BIT_MASK_MGQ_DESC_MODE_8821C) << BIT_SHIFT_MGQ_DESC_MODE_8821C)
-#define BIT_GET_MGQ_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_MGQ_DESC_MODE_8821C) & BIT_MASK_MGQ_DESC_MODE_8821C)
-
+#define BIT_MGQ_DESC_MODE_8821C(x) \
+ (((x) & BIT_MASK_MGQ_DESC_MODE_8821C) << BIT_SHIFT_MGQ_DESC_MODE_8821C)
+#define BITS_MGQ_DESC_MODE_8821C \
+ (BIT_MASK_MGQ_DESC_MODE_8821C << BIT_SHIFT_MGQ_DESC_MODE_8821C)
+#define BIT_CLEAR_MGQ_DESC_MODE_8821C(x) ((x) & (~BITS_MGQ_DESC_MODE_8821C))
+#define BIT_GET_MGQ_DESC_MODE_8821C(x) \
+ (((x) >> BIT_SHIFT_MGQ_DESC_MODE_8821C) & BIT_MASK_MGQ_DESC_MODE_8821C)
+#define BIT_SET_MGQ_DESC_MODE_8821C(x, v) \
+ (BIT_CLEAR_MGQ_DESC_MODE_8821C(x) | BIT_MGQ_DESC_MODE_8821C(v))
#define BIT_SHIFT_MGQ_DESC_NUM_8821C 0
#define BIT_MASK_MGQ_DESC_NUM_8821C 0xfff
-#define BIT_MGQ_DESC_NUM_8821C(x) (((x) & BIT_MASK_MGQ_DESC_NUM_8821C) << BIT_SHIFT_MGQ_DESC_NUM_8821C)
-#define BIT_GET_MGQ_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_MGQ_DESC_NUM_8821C) & BIT_MASK_MGQ_DESC_NUM_8821C)
-
+#define BIT_MGQ_DESC_NUM_8821C(x) \
+ (((x) & BIT_MASK_MGQ_DESC_NUM_8821C) << BIT_SHIFT_MGQ_DESC_NUM_8821C)
+#define BITS_MGQ_DESC_NUM_8821C \
+ (BIT_MASK_MGQ_DESC_NUM_8821C << BIT_SHIFT_MGQ_DESC_NUM_8821C)
+#define BIT_CLEAR_MGQ_DESC_NUM_8821C(x) ((x) & (~BITS_MGQ_DESC_NUM_8821C))
+#define BIT_GET_MGQ_DESC_NUM_8821C(x) \
+ (((x) >> BIT_SHIFT_MGQ_DESC_NUM_8821C) & BIT_MASK_MGQ_DESC_NUM_8821C)
+#define BIT_SET_MGQ_DESC_NUM_8821C(x, v) \
+ (BIT_CLEAR_MGQ_DESC_NUM_8821C(x) | BIT_MGQ_DESC_NUM_8821C(v))
/* 2 REG_RX_RXBD_NUM_8821C */
#define BIT_SYS_32_64_8821C BIT(15)
#define BIT_SHIFT_BCNQ_DESC_MODE_8821C 13
#define BIT_MASK_BCNQ_DESC_MODE_8821C 0x3
-#define BIT_BCNQ_DESC_MODE_8821C(x) (((x) & BIT_MASK_BCNQ_DESC_MODE_8821C) << BIT_SHIFT_BCNQ_DESC_MODE_8821C)
-#define BIT_GET_BCNQ_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_BCNQ_DESC_MODE_8821C) & BIT_MASK_BCNQ_DESC_MODE_8821C)
+#define BIT_BCNQ_DESC_MODE_8821C(x) \
+ (((x) & BIT_MASK_BCNQ_DESC_MODE_8821C) \
+ << BIT_SHIFT_BCNQ_DESC_MODE_8821C)
+#define BITS_BCNQ_DESC_MODE_8821C \
+ (BIT_MASK_BCNQ_DESC_MODE_8821C << BIT_SHIFT_BCNQ_DESC_MODE_8821C)
+#define BIT_CLEAR_BCNQ_DESC_MODE_8821C(x) ((x) & (~BITS_BCNQ_DESC_MODE_8821C))
+#define BIT_GET_BCNQ_DESC_MODE_8821C(x) \
+ (((x) >> BIT_SHIFT_BCNQ_DESC_MODE_8821C) & \
+ BIT_MASK_BCNQ_DESC_MODE_8821C)
+#define BIT_SET_BCNQ_DESC_MODE_8821C(x, v) \
+ (BIT_CLEAR_BCNQ_DESC_MODE_8821C(x) | BIT_BCNQ_DESC_MODE_8821C(v))
#define BIT_PCIE_BCNQ_FLAG_8821C BIT(12)
#define BIT_SHIFT_RXQ_DESC_NUM_8821C 0
#define BIT_MASK_RXQ_DESC_NUM_8821C 0xfff
-#define BIT_RXQ_DESC_NUM_8821C(x) (((x) & BIT_MASK_RXQ_DESC_NUM_8821C) << BIT_SHIFT_RXQ_DESC_NUM_8821C)
-#define BIT_GET_RXQ_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_RXQ_DESC_NUM_8821C) & BIT_MASK_RXQ_DESC_NUM_8821C)
-
+#define BIT_RXQ_DESC_NUM_8821C(x) \
+ (((x) & BIT_MASK_RXQ_DESC_NUM_8821C) << BIT_SHIFT_RXQ_DESC_NUM_8821C)
+#define BITS_RXQ_DESC_NUM_8821C \
+ (BIT_MASK_RXQ_DESC_NUM_8821C << BIT_SHIFT_RXQ_DESC_NUM_8821C)
+#define BIT_CLEAR_RXQ_DESC_NUM_8821C(x) ((x) & (~BITS_RXQ_DESC_NUM_8821C))
+#define BIT_GET_RXQ_DESC_NUM_8821C(x) \
+ (((x) >> BIT_SHIFT_RXQ_DESC_NUM_8821C) & BIT_MASK_RXQ_DESC_NUM_8821C)
+#define BIT_SET_RXQ_DESC_NUM_8821C(x, v) \
+ (BIT_CLEAR_RXQ_DESC_NUM_8821C(x) | BIT_RXQ_DESC_NUM_8821C(v))
/* 2 REG_VOQ_TXBD_NUM_8821C */
#define BIT_PCIE_VOQ_FLAG_8821C BIT(14)
#define BIT_SHIFT_VOQ_DESC_MODE_8821C 12
#define BIT_MASK_VOQ_DESC_MODE_8821C 0x3
-#define BIT_VOQ_DESC_MODE_8821C(x) (((x) & BIT_MASK_VOQ_DESC_MODE_8821C) << BIT_SHIFT_VOQ_DESC_MODE_8821C)
-#define BIT_GET_VOQ_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_VOQ_DESC_MODE_8821C) & BIT_MASK_VOQ_DESC_MODE_8821C)
-
+#define BIT_VOQ_DESC_MODE_8821C(x) \
+ (((x) & BIT_MASK_VOQ_DESC_MODE_8821C) << BIT_SHIFT_VOQ_DESC_MODE_8821C)
+#define BITS_VOQ_DESC_MODE_8821C \
+ (BIT_MASK_VOQ_DESC_MODE_8821C << BIT_SHIFT_VOQ_DESC_MODE_8821C)
+#define BIT_CLEAR_VOQ_DESC_MODE_8821C(x) ((x) & (~BITS_VOQ_DESC_MODE_8821C))
+#define BIT_GET_VOQ_DESC_MODE_8821C(x) \
+ (((x) >> BIT_SHIFT_VOQ_DESC_MODE_8821C) & BIT_MASK_VOQ_DESC_MODE_8821C)
+#define BIT_SET_VOQ_DESC_MODE_8821C(x, v) \
+ (BIT_CLEAR_VOQ_DESC_MODE_8821C(x) | BIT_VOQ_DESC_MODE_8821C(v))
#define BIT_SHIFT_VOQ_DESC_NUM_8821C 0
#define BIT_MASK_VOQ_DESC_NUM_8821C 0xfff
-#define BIT_VOQ_DESC_NUM_8821C(x) (((x) & BIT_MASK_VOQ_DESC_NUM_8821C) << BIT_SHIFT_VOQ_DESC_NUM_8821C)
-#define BIT_GET_VOQ_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_VOQ_DESC_NUM_8821C) & BIT_MASK_VOQ_DESC_NUM_8821C)
-
+#define BIT_VOQ_DESC_NUM_8821C(x) \
+ (((x) & BIT_MASK_VOQ_DESC_NUM_8821C) << BIT_SHIFT_VOQ_DESC_NUM_8821C)
+#define BITS_VOQ_DESC_NUM_8821C \
+ (BIT_MASK_VOQ_DESC_NUM_8821C << BIT_SHIFT_VOQ_DESC_NUM_8821C)
+#define BIT_CLEAR_VOQ_DESC_NUM_8821C(x) ((x) & (~BITS_VOQ_DESC_NUM_8821C))
+#define BIT_GET_VOQ_DESC_NUM_8821C(x) \
+ (((x) >> BIT_SHIFT_VOQ_DESC_NUM_8821C) & BIT_MASK_VOQ_DESC_NUM_8821C)
+#define BIT_SET_VOQ_DESC_NUM_8821C(x, v) \
+ (BIT_CLEAR_VOQ_DESC_NUM_8821C(x) | BIT_VOQ_DESC_NUM_8821C(v))
/* 2 REG_VIQ_TXBD_NUM_8821C */
#define BIT_PCIE_VIQ_FLAG_8821C BIT(14)
#define BIT_SHIFT_VIQ_DESC_MODE_8821C 12
#define BIT_MASK_VIQ_DESC_MODE_8821C 0x3
-#define BIT_VIQ_DESC_MODE_8821C(x) (((x) & BIT_MASK_VIQ_DESC_MODE_8821C) << BIT_SHIFT_VIQ_DESC_MODE_8821C)
-#define BIT_GET_VIQ_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_VIQ_DESC_MODE_8821C) & BIT_MASK_VIQ_DESC_MODE_8821C)
-
+#define BIT_VIQ_DESC_MODE_8821C(x) \
+ (((x) & BIT_MASK_VIQ_DESC_MODE_8821C) << BIT_SHIFT_VIQ_DESC_MODE_8821C)
+#define BITS_VIQ_DESC_MODE_8821C \
+ (BIT_MASK_VIQ_DESC_MODE_8821C << BIT_SHIFT_VIQ_DESC_MODE_8821C)
+#define BIT_CLEAR_VIQ_DESC_MODE_8821C(x) ((x) & (~BITS_VIQ_DESC_MODE_8821C))
+#define BIT_GET_VIQ_DESC_MODE_8821C(x) \
+ (((x) >> BIT_SHIFT_VIQ_DESC_MODE_8821C) & BIT_MASK_VIQ_DESC_MODE_8821C)
+#define BIT_SET_VIQ_DESC_MODE_8821C(x, v) \
+ (BIT_CLEAR_VIQ_DESC_MODE_8821C(x) | BIT_VIQ_DESC_MODE_8821C(v))
#define BIT_SHIFT_VIQ_DESC_NUM_8821C 0
#define BIT_MASK_VIQ_DESC_NUM_8821C 0xfff
-#define BIT_VIQ_DESC_NUM_8821C(x) (((x) & BIT_MASK_VIQ_DESC_NUM_8821C) << BIT_SHIFT_VIQ_DESC_NUM_8821C)
-#define BIT_GET_VIQ_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_VIQ_DESC_NUM_8821C) & BIT_MASK_VIQ_DESC_NUM_8821C)
-
+#define BIT_VIQ_DESC_NUM_8821C(x) \
+ (((x) & BIT_MASK_VIQ_DESC_NUM_8821C) << BIT_SHIFT_VIQ_DESC_NUM_8821C)
+#define BITS_VIQ_DESC_NUM_8821C \
+ (BIT_MASK_VIQ_DESC_NUM_8821C << BIT_SHIFT_VIQ_DESC_NUM_8821C)
+#define BIT_CLEAR_VIQ_DESC_NUM_8821C(x) ((x) & (~BITS_VIQ_DESC_NUM_8821C))
+#define BIT_GET_VIQ_DESC_NUM_8821C(x) \
+ (((x) >> BIT_SHIFT_VIQ_DESC_NUM_8821C) & BIT_MASK_VIQ_DESC_NUM_8821C)
+#define BIT_SET_VIQ_DESC_NUM_8821C(x, v) \
+ (BIT_CLEAR_VIQ_DESC_NUM_8821C(x) | BIT_VIQ_DESC_NUM_8821C(v))
/* 2 REG_BEQ_TXBD_NUM_8821C */
#define BIT_PCIE_BEQ_FLAG_8821C BIT(14)
#define BIT_SHIFT_BEQ_DESC_MODE_8821C 12
#define BIT_MASK_BEQ_DESC_MODE_8821C 0x3
-#define BIT_BEQ_DESC_MODE_8821C(x) (((x) & BIT_MASK_BEQ_DESC_MODE_8821C) << BIT_SHIFT_BEQ_DESC_MODE_8821C)
-#define BIT_GET_BEQ_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_BEQ_DESC_MODE_8821C) & BIT_MASK_BEQ_DESC_MODE_8821C)
-
+#define BIT_BEQ_DESC_MODE_8821C(x) \
+ (((x) & BIT_MASK_BEQ_DESC_MODE_8821C) << BIT_SHIFT_BEQ_DESC_MODE_8821C)
+#define BITS_BEQ_DESC_MODE_8821C \
+ (BIT_MASK_BEQ_DESC_MODE_8821C << BIT_SHIFT_BEQ_DESC_MODE_8821C)
+#define BIT_CLEAR_BEQ_DESC_MODE_8821C(x) ((x) & (~BITS_BEQ_DESC_MODE_8821C))
+#define BIT_GET_BEQ_DESC_MODE_8821C(x) \
+ (((x) >> BIT_SHIFT_BEQ_DESC_MODE_8821C) & BIT_MASK_BEQ_DESC_MODE_8821C)
+#define BIT_SET_BEQ_DESC_MODE_8821C(x, v) \
+ (BIT_CLEAR_BEQ_DESC_MODE_8821C(x) | BIT_BEQ_DESC_MODE_8821C(v))
#define BIT_SHIFT_BEQ_DESC_NUM_8821C 0
#define BIT_MASK_BEQ_DESC_NUM_8821C 0xfff
-#define BIT_BEQ_DESC_NUM_8821C(x) (((x) & BIT_MASK_BEQ_DESC_NUM_8821C) << BIT_SHIFT_BEQ_DESC_NUM_8821C)
-#define BIT_GET_BEQ_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_BEQ_DESC_NUM_8821C) & BIT_MASK_BEQ_DESC_NUM_8821C)
-
+#define BIT_BEQ_DESC_NUM_8821C(x) \
+ (((x) & BIT_MASK_BEQ_DESC_NUM_8821C) << BIT_SHIFT_BEQ_DESC_NUM_8821C)
+#define BITS_BEQ_DESC_NUM_8821C \
+ (BIT_MASK_BEQ_DESC_NUM_8821C << BIT_SHIFT_BEQ_DESC_NUM_8821C)
+#define BIT_CLEAR_BEQ_DESC_NUM_8821C(x) ((x) & (~BITS_BEQ_DESC_NUM_8821C))
+#define BIT_GET_BEQ_DESC_NUM_8821C(x) \
+ (((x) >> BIT_SHIFT_BEQ_DESC_NUM_8821C) & BIT_MASK_BEQ_DESC_NUM_8821C)
+#define BIT_SET_BEQ_DESC_NUM_8821C(x, v) \
+ (BIT_CLEAR_BEQ_DESC_NUM_8821C(x) | BIT_BEQ_DESC_NUM_8821C(v))
/* 2 REG_BKQ_TXBD_NUM_8821C */
#define BIT_PCIE_BKQ_FLAG_8821C BIT(14)
#define BIT_SHIFT_BKQ_DESC_MODE_8821C 12
#define BIT_MASK_BKQ_DESC_MODE_8821C 0x3
-#define BIT_BKQ_DESC_MODE_8821C(x) (((x) & BIT_MASK_BKQ_DESC_MODE_8821C) << BIT_SHIFT_BKQ_DESC_MODE_8821C)
-#define BIT_GET_BKQ_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_BKQ_DESC_MODE_8821C) & BIT_MASK_BKQ_DESC_MODE_8821C)
-
+#define BIT_BKQ_DESC_MODE_8821C(x) \
+ (((x) & BIT_MASK_BKQ_DESC_MODE_8821C) << BIT_SHIFT_BKQ_DESC_MODE_8821C)
+#define BITS_BKQ_DESC_MODE_8821C \
+ (BIT_MASK_BKQ_DESC_MODE_8821C << BIT_SHIFT_BKQ_DESC_MODE_8821C)
+#define BIT_CLEAR_BKQ_DESC_MODE_8821C(x) ((x) & (~BITS_BKQ_DESC_MODE_8821C))
+#define BIT_GET_BKQ_DESC_MODE_8821C(x) \
+ (((x) >> BIT_SHIFT_BKQ_DESC_MODE_8821C) & BIT_MASK_BKQ_DESC_MODE_8821C)
+#define BIT_SET_BKQ_DESC_MODE_8821C(x, v) \
+ (BIT_CLEAR_BKQ_DESC_MODE_8821C(x) | BIT_BKQ_DESC_MODE_8821C(v))
#define BIT_SHIFT_BKQ_DESC_NUM_8821C 0
#define BIT_MASK_BKQ_DESC_NUM_8821C 0xfff
-#define BIT_BKQ_DESC_NUM_8821C(x) (((x) & BIT_MASK_BKQ_DESC_NUM_8821C) << BIT_SHIFT_BKQ_DESC_NUM_8821C)
-#define BIT_GET_BKQ_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_BKQ_DESC_NUM_8821C) & BIT_MASK_BKQ_DESC_NUM_8821C)
-
+#define BIT_BKQ_DESC_NUM_8821C(x) \
+ (((x) & BIT_MASK_BKQ_DESC_NUM_8821C) << BIT_SHIFT_BKQ_DESC_NUM_8821C)
+#define BITS_BKQ_DESC_NUM_8821C \
+ (BIT_MASK_BKQ_DESC_NUM_8821C << BIT_SHIFT_BKQ_DESC_NUM_8821C)
+#define BIT_CLEAR_BKQ_DESC_NUM_8821C(x) ((x) & (~BITS_BKQ_DESC_NUM_8821C))
+#define BIT_GET_BKQ_DESC_NUM_8821C(x) \
+ (((x) >> BIT_SHIFT_BKQ_DESC_NUM_8821C) & BIT_MASK_BKQ_DESC_NUM_8821C)
+#define BIT_SET_BKQ_DESC_NUM_8821C(x, v) \
+ (BIT_CLEAR_BKQ_DESC_NUM_8821C(x) | BIT_BKQ_DESC_NUM_8821C(v))
/* 2 REG_HI0Q_TXBD_NUM_8821C */
#define BIT_HI0Q_FLAG_8821C BIT(14)
#define BIT_SHIFT_HI0Q_DESC_MODE_8821C 12
#define BIT_MASK_HI0Q_DESC_MODE_8821C 0x3
-#define BIT_HI0Q_DESC_MODE_8821C(x) (((x) & BIT_MASK_HI0Q_DESC_MODE_8821C) << BIT_SHIFT_HI0Q_DESC_MODE_8821C)
-#define BIT_GET_HI0Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI0Q_DESC_MODE_8821C) & BIT_MASK_HI0Q_DESC_MODE_8821C)
-
+#define BIT_HI0Q_DESC_MODE_8821C(x) \
+ (((x) & BIT_MASK_HI0Q_DESC_MODE_8821C) \
+ << BIT_SHIFT_HI0Q_DESC_MODE_8821C)
+#define BITS_HI0Q_DESC_MODE_8821C \
+ (BIT_MASK_HI0Q_DESC_MODE_8821C << BIT_SHIFT_HI0Q_DESC_MODE_8821C)
+#define BIT_CLEAR_HI0Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI0Q_DESC_MODE_8821C))
+#define BIT_GET_HI0Q_DESC_MODE_8821C(x) \
+ (((x) >> BIT_SHIFT_HI0Q_DESC_MODE_8821C) & \
+ BIT_MASK_HI0Q_DESC_MODE_8821C)
+#define BIT_SET_HI0Q_DESC_MODE_8821C(x, v) \
+ (BIT_CLEAR_HI0Q_DESC_MODE_8821C(x) | BIT_HI0Q_DESC_MODE_8821C(v))
#define BIT_SHIFT_HI0Q_DESC_NUM_8821C 0
#define BIT_MASK_HI0Q_DESC_NUM_8821C 0xfff
-#define BIT_HI0Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI0Q_DESC_NUM_8821C) << BIT_SHIFT_HI0Q_DESC_NUM_8821C)
-#define BIT_GET_HI0Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI0Q_DESC_NUM_8821C) & BIT_MASK_HI0Q_DESC_NUM_8821C)
-
+#define BIT_HI0Q_DESC_NUM_8821C(x) \
+ (((x) & BIT_MASK_HI0Q_DESC_NUM_8821C) << BIT_SHIFT_HI0Q_DESC_NUM_8821C)
+#define BITS_HI0Q_DESC_NUM_8821C \
+ (BIT_MASK_HI0Q_DESC_NUM_8821C << BIT_SHIFT_HI0Q_DESC_NUM_8821C)
+#define BIT_CLEAR_HI0Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI0Q_DESC_NUM_8821C))
+#define BIT_GET_HI0Q_DESC_NUM_8821C(x) \
+ (((x) >> BIT_SHIFT_HI0Q_DESC_NUM_8821C) & BIT_MASK_HI0Q_DESC_NUM_8821C)
+#define BIT_SET_HI0Q_DESC_NUM_8821C(x, v) \
+ (BIT_CLEAR_HI0Q_DESC_NUM_8821C(x) | BIT_HI0Q_DESC_NUM_8821C(v))
/* 2 REG_HI1Q_TXBD_NUM_8821C */
#define BIT_HI1Q_FLAG_8821C BIT(14)
#define BIT_SHIFT_HI1Q_DESC_MODE_8821C 12
#define BIT_MASK_HI1Q_DESC_MODE_8821C 0x3
-#define BIT_HI1Q_DESC_MODE_8821C(x) (((x) & BIT_MASK_HI1Q_DESC_MODE_8821C) << BIT_SHIFT_HI1Q_DESC_MODE_8821C)
-#define BIT_GET_HI1Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI1Q_DESC_MODE_8821C) & BIT_MASK_HI1Q_DESC_MODE_8821C)
-
+#define BIT_HI1Q_DESC_MODE_8821C(x) \
+ (((x) & BIT_MASK_HI1Q_DESC_MODE_8821C) \
+ << BIT_SHIFT_HI1Q_DESC_MODE_8821C)
+#define BITS_HI1Q_DESC_MODE_8821C \
+ (BIT_MASK_HI1Q_DESC_MODE_8821C << BIT_SHIFT_HI1Q_DESC_MODE_8821C)
+#define BIT_CLEAR_HI1Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI1Q_DESC_MODE_8821C))
+#define BIT_GET_HI1Q_DESC_MODE_8821C(x) \
+ (((x) >> BIT_SHIFT_HI1Q_DESC_MODE_8821C) & \
+ BIT_MASK_HI1Q_DESC_MODE_8821C)
+#define BIT_SET_HI1Q_DESC_MODE_8821C(x, v) \
+ (BIT_CLEAR_HI1Q_DESC_MODE_8821C(x) | BIT_HI1Q_DESC_MODE_8821C(v))
#define BIT_SHIFT_HI1Q_DESC_NUM_8821C 0
#define BIT_MASK_HI1Q_DESC_NUM_8821C 0xfff
-#define BIT_HI1Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI1Q_DESC_NUM_8821C) << BIT_SHIFT_HI1Q_DESC_NUM_8821C)
-#define BIT_GET_HI1Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI1Q_DESC_NUM_8821C) & BIT_MASK_HI1Q_DESC_NUM_8821C)
-
+#define BIT_HI1Q_DESC_NUM_8821C(x) \
+ (((x) & BIT_MASK_HI1Q_DESC_NUM_8821C) << BIT_SHIFT_HI1Q_DESC_NUM_8821C)
+#define BITS_HI1Q_DESC_NUM_8821C \
+ (BIT_MASK_HI1Q_DESC_NUM_8821C << BIT_SHIFT_HI1Q_DESC_NUM_8821C)
+#define BIT_CLEAR_HI1Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI1Q_DESC_NUM_8821C))
+#define BIT_GET_HI1Q_DESC_NUM_8821C(x) \
+ (((x) >> BIT_SHIFT_HI1Q_DESC_NUM_8821C) & BIT_MASK_HI1Q_DESC_NUM_8821C)
+#define BIT_SET_HI1Q_DESC_NUM_8821C(x, v) \
+ (BIT_CLEAR_HI1Q_DESC_NUM_8821C(x) | BIT_HI1Q_DESC_NUM_8821C(v))
/* 2 REG_HI2Q_TXBD_NUM_8821C */
#define BIT_HI2Q_FLAG_8821C BIT(14)
#define BIT_SHIFT_HI2Q_DESC_MODE_8821C 12
#define BIT_MASK_HI2Q_DESC_MODE_8821C 0x3
-#define BIT_HI2Q_DESC_MODE_8821C(x) (((x) & BIT_MASK_HI2Q_DESC_MODE_8821C) << BIT_SHIFT_HI2Q_DESC_MODE_8821C)
-#define BIT_GET_HI2Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI2Q_DESC_MODE_8821C) & BIT_MASK_HI2Q_DESC_MODE_8821C)
-
+#define BIT_HI2Q_DESC_MODE_8821C(x) \
+ (((x) & BIT_MASK_HI2Q_DESC_MODE_8821C) \
+ << BIT_SHIFT_HI2Q_DESC_MODE_8821C)
+#define BITS_HI2Q_DESC_MODE_8821C \
+ (BIT_MASK_HI2Q_DESC_MODE_8821C << BIT_SHIFT_HI2Q_DESC_MODE_8821C)
+#define BIT_CLEAR_HI2Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI2Q_DESC_MODE_8821C))
+#define BIT_GET_HI2Q_DESC_MODE_8821C(x) \
+ (((x) >> BIT_SHIFT_HI2Q_DESC_MODE_8821C) & \
+ BIT_MASK_HI2Q_DESC_MODE_8821C)
+#define BIT_SET_HI2Q_DESC_MODE_8821C(x, v) \
+ (BIT_CLEAR_HI2Q_DESC_MODE_8821C(x) | BIT_HI2Q_DESC_MODE_8821C(v))
#define BIT_SHIFT_HI2Q_DESC_NUM_8821C 0
#define BIT_MASK_HI2Q_DESC_NUM_8821C 0xfff
-#define BIT_HI2Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI2Q_DESC_NUM_8821C) << BIT_SHIFT_HI2Q_DESC_NUM_8821C)
-#define BIT_GET_HI2Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI2Q_DESC_NUM_8821C) & BIT_MASK_HI2Q_DESC_NUM_8821C)
-
+#define BIT_HI2Q_DESC_NUM_8821C(x) \
+ (((x) & BIT_MASK_HI2Q_DESC_NUM_8821C) << BIT_SHIFT_HI2Q_DESC_NUM_8821C)
+#define BITS_HI2Q_DESC_NUM_8821C \
+ (BIT_MASK_HI2Q_DESC_NUM_8821C << BIT_SHIFT_HI2Q_DESC_NUM_8821C)
+#define BIT_CLEAR_HI2Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI2Q_DESC_NUM_8821C))
+#define BIT_GET_HI2Q_DESC_NUM_8821C(x) \
+ (((x) >> BIT_SHIFT_HI2Q_DESC_NUM_8821C) & BIT_MASK_HI2Q_DESC_NUM_8821C)
+#define BIT_SET_HI2Q_DESC_NUM_8821C(x, v) \
+ (BIT_CLEAR_HI2Q_DESC_NUM_8821C(x) | BIT_HI2Q_DESC_NUM_8821C(v))
/* 2 REG_HI3Q_TXBD_NUM_8821C */
#define BIT_HI3Q_FLAG_8821C BIT(14)
#define BIT_SHIFT_HI3Q_DESC_MODE_8821C 12
#define BIT_MASK_HI3Q_DESC_MODE_8821C 0x3
-#define BIT_HI3Q_DESC_MODE_8821C(x) (((x) & BIT_MASK_HI3Q_DESC_MODE_8821C) << BIT_SHIFT_HI3Q_DESC_MODE_8821C)
-#define BIT_GET_HI3Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI3Q_DESC_MODE_8821C) & BIT_MASK_HI3Q_DESC_MODE_8821C)
-
+#define BIT_HI3Q_DESC_MODE_8821C(x) \
+ (((x) & BIT_MASK_HI3Q_DESC_MODE_8821C) \
+ << BIT_SHIFT_HI3Q_DESC_MODE_8821C)
+#define BITS_HI3Q_DESC_MODE_8821C \
+ (BIT_MASK_HI3Q_DESC_MODE_8821C << BIT_SHIFT_HI3Q_DESC_MODE_8821C)
+#define BIT_CLEAR_HI3Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI3Q_DESC_MODE_8821C))
+#define BIT_GET_HI3Q_DESC_MODE_8821C(x) \
+ (((x) >> BIT_SHIFT_HI3Q_DESC_MODE_8821C) & \
+ BIT_MASK_HI3Q_DESC_MODE_8821C)
+#define BIT_SET_HI3Q_DESC_MODE_8821C(x, v) \
+ (BIT_CLEAR_HI3Q_DESC_MODE_8821C(x) | BIT_HI3Q_DESC_MODE_8821C(v))
#define BIT_SHIFT_HI3Q_DESC_NUM_8821C 0
#define BIT_MASK_HI3Q_DESC_NUM_8821C 0xfff
-#define BIT_HI3Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI3Q_DESC_NUM_8821C) << BIT_SHIFT_HI3Q_DESC_NUM_8821C)
-#define BIT_GET_HI3Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI3Q_DESC_NUM_8821C) & BIT_MASK_HI3Q_DESC_NUM_8821C)
-
+#define BIT_HI3Q_DESC_NUM_8821C(x) \
+ (((x) & BIT_MASK_HI3Q_DESC_NUM_8821C) << BIT_SHIFT_HI3Q_DESC_NUM_8821C)
+#define BITS_HI3Q_DESC_NUM_8821C \
+ (BIT_MASK_HI3Q_DESC_NUM_8821C << BIT_SHIFT_HI3Q_DESC_NUM_8821C)
+#define BIT_CLEAR_HI3Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI3Q_DESC_NUM_8821C))
+#define BIT_GET_HI3Q_DESC_NUM_8821C(x) \
+ (((x) >> BIT_SHIFT_HI3Q_DESC_NUM_8821C) & BIT_MASK_HI3Q_DESC_NUM_8821C)
+#define BIT_SET_HI3Q_DESC_NUM_8821C(x, v) \
+ (BIT_CLEAR_HI3Q_DESC_NUM_8821C(x) | BIT_HI3Q_DESC_NUM_8821C(v))
/* 2 REG_HI4Q_TXBD_NUM_8821C */
#define BIT_HI4Q_FLAG_8821C BIT(14)
#define BIT_SHIFT_HI4Q_DESC_MODE_8821C 12
#define BIT_MASK_HI4Q_DESC_MODE_8821C 0x3
-#define BIT_HI4Q_DESC_MODE_8821C(x) (((x) & BIT_MASK_HI4Q_DESC_MODE_8821C) << BIT_SHIFT_HI4Q_DESC_MODE_8821C)
-#define BIT_GET_HI4Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI4Q_DESC_MODE_8821C) & BIT_MASK_HI4Q_DESC_MODE_8821C)
-
+#define BIT_HI4Q_DESC_MODE_8821C(x) \
+ (((x) & BIT_MASK_HI4Q_DESC_MODE_8821C) \
+ << BIT_SHIFT_HI4Q_DESC_MODE_8821C)
+#define BITS_HI4Q_DESC_MODE_8821C \
+ (BIT_MASK_HI4Q_DESC_MODE_8821C << BIT_SHIFT_HI4Q_DESC_MODE_8821C)
+#define BIT_CLEAR_HI4Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI4Q_DESC_MODE_8821C))
+#define BIT_GET_HI4Q_DESC_MODE_8821C(x) \
+ (((x) >> BIT_SHIFT_HI4Q_DESC_MODE_8821C) & \
+ BIT_MASK_HI4Q_DESC_MODE_8821C)
+#define BIT_SET_HI4Q_DESC_MODE_8821C(x, v) \
+ (BIT_CLEAR_HI4Q_DESC_MODE_8821C(x) | BIT_HI4Q_DESC_MODE_8821C(v))
#define BIT_SHIFT_HI4Q_DESC_NUM_8821C 0
#define BIT_MASK_HI4Q_DESC_NUM_8821C 0xfff
-#define BIT_HI4Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI4Q_DESC_NUM_8821C) << BIT_SHIFT_HI4Q_DESC_NUM_8821C)
-#define BIT_GET_HI4Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI4Q_DESC_NUM_8821C) & BIT_MASK_HI4Q_DESC_NUM_8821C)
-
+#define BIT_HI4Q_DESC_NUM_8821C(x) \
+ (((x) & BIT_MASK_HI4Q_DESC_NUM_8821C) << BIT_SHIFT_HI4Q_DESC_NUM_8821C)
+#define BITS_HI4Q_DESC_NUM_8821C \
+ (BIT_MASK_HI4Q_DESC_NUM_8821C << BIT_SHIFT_HI4Q_DESC_NUM_8821C)
+#define BIT_CLEAR_HI4Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI4Q_DESC_NUM_8821C))
+#define BIT_GET_HI4Q_DESC_NUM_8821C(x) \
+ (((x) >> BIT_SHIFT_HI4Q_DESC_NUM_8821C) & BIT_MASK_HI4Q_DESC_NUM_8821C)
+#define BIT_SET_HI4Q_DESC_NUM_8821C(x, v) \
+ (BIT_CLEAR_HI4Q_DESC_NUM_8821C(x) | BIT_HI4Q_DESC_NUM_8821C(v))
/* 2 REG_HI5Q_TXBD_NUM_8821C */
#define BIT_HI5Q_FLAG_8821C BIT(14)
#define BIT_SHIFT_HI5Q_DESC_MODE_8821C 12
#define BIT_MASK_HI5Q_DESC_MODE_8821C 0x3
-#define BIT_HI5Q_DESC_MODE_8821C(x) (((x) & BIT_MASK_HI5Q_DESC_MODE_8821C) << BIT_SHIFT_HI5Q_DESC_MODE_8821C)
-#define BIT_GET_HI5Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI5Q_DESC_MODE_8821C) & BIT_MASK_HI5Q_DESC_MODE_8821C)
-
+#define BIT_HI5Q_DESC_MODE_8821C(x) \
+ (((x) & BIT_MASK_HI5Q_DESC_MODE_8821C) \
+ << BIT_SHIFT_HI5Q_DESC_MODE_8821C)
+#define BITS_HI5Q_DESC_MODE_8821C \
+ (BIT_MASK_HI5Q_DESC_MODE_8821C << BIT_SHIFT_HI5Q_DESC_MODE_8821C)
+#define BIT_CLEAR_HI5Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI5Q_DESC_MODE_8821C))
+#define BIT_GET_HI5Q_DESC_MODE_8821C(x) \
+ (((x) >> BIT_SHIFT_HI5Q_DESC_MODE_8821C) & \
+ BIT_MASK_HI5Q_DESC_MODE_8821C)
+#define BIT_SET_HI5Q_DESC_MODE_8821C(x, v) \
+ (BIT_CLEAR_HI5Q_DESC_MODE_8821C(x) | BIT_HI5Q_DESC_MODE_8821C(v))
#define BIT_SHIFT_HI5Q_DESC_NUM_8821C 0
#define BIT_MASK_HI5Q_DESC_NUM_8821C 0xfff
-#define BIT_HI5Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI5Q_DESC_NUM_8821C) << BIT_SHIFT_HI5Q_DESC_NUM_8821C)
-#define BIT_GET_HI5Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI5Q_DESC_NUM_8821C) & BIT_MASK_HI5Q_DESC_NUM_8821C)
-
+#define BIT_HI5Q_DESC_NUM_8821C(x) \
+ (((x) & BIT_MASK_HI5Q_DESC_NUM_8821C) << BIT_SHIFT_HI5Q_DESC_NUM_8821C)
+#define BITS_HI5Q_DESC_NUM_8821C \
+ (BIT_MASK_HI5Q_DESC_NUM_8821C << BIT_SHIFT_HI5Q_DESC_NUM_8821C)
+#define BIT_CLEAR_HI5Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI5Q_DESC_NUM_8821C))
+#define BIT_GET_HI5Q_DESC_NUM_8821C(x) \
+ (((x) >> BIT_SHIFT_HI5Q_DESC_NUM_8821C) & BIT_MASK_HI5Q_DESC_NUM_8821C)
+#define BIT_SET_HI5Q_DESC_NUM_8821C(x, v) \
+ (BIT_CLEAR_HI5Q_DESC_NUM_8821C(x) | BIT_HI5Q_DESC_NUM_8821C(v))
/* 2 REG_HI6Q_TXBD_NUM_8821C */
#define BIT_HI6Q_FLAG_8821C BIT(14)
#define BIT_SHIFT_HI6Q_DESC_MODE_8821C 12
#define BIT_MASK_HI6Q_DESC_MODE_8821C 0x3
-#define BIT_HI6Q_DESC_MODE_8821C(x) (((x) & BIT_MASK_HI6Q_DESC_MODE_8821C) << BIT_SHIFT_HI6Q_DESC_MODE_8821C)
-#define BIT_GET_HI6Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI6Q_DESC_MODE_8821C) & BIT_MASK_HI6Q_DESC_MODE_8821C)
-
+#define BIT_HI6Q_DESC_MODE_8821C(x) \
+ (((x) & BIT_MASK_HI6Q_DESC_MODE_8821C) \
+ << BIT_SHIFT_HI6Q_DESC_MODE_8821C)
+#define BITS_HI6Q_DESC_MODE_8821C \
+ (BIT_MASK_HI6Q_DESC_MODE_8821C << BIT_SHIFT_HI6Q_DESC_MODE_8821C)
+#define BIT_CLEAR_HI6Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI6Q_DESC_MODE_8821C))
+#define BIT_GET_HI6Q_DESC_MODE_8821C(x) \
+ (((x) >> BIT_SHIFT_HI6Q_DESC_MODE_8821C) & \
+ BIT_MASK_HI6Q_DESC_MODE_8821C)
+#define BIT_SET_HI6Q_DESC_MODE_8821C(x, v) \
+ (BIT_CLEAR_HI6Q_DESC_MODE_8821C(x) | BIT_HI6Q_DESC_MODE_8821C(v))
#define BIT_SHIFT_HI6Q_DESC_NUM_8821C 0
#define BIT_MASK_HI6Q_DESC_NUM_8821C 0xfff
-#define BIT_HI6Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI6Q_DESC_NUM_8821C) << BIT_SHIFT_HI6Q_DESC_NUM_8821C)
-#define BIT_GET_HI6Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI6Q_DESC_NUM_8821C) & BIT_MASK_HI6Q_DESC_NUM_8821C)
-
+#define BIT_HI6Q_DESC_NUM_8821C(x) \
+ (((x) & BIT_MASK_HI6Q_DESC_NUM_8821C) << BIT_SHIFT_HI6Q_DESC_NUM_8821C)
+#define BITS_HI6Q_DESC_NUM_8821C \
+ (BIT_MASK_HI6Q_DESC_NUM_8821C << BIT_SHIFT_HI6Q_DESC_NUM_8821C)
+#define BIT_CLEAR_HI6Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI6Q_DESC_NUM_8821C))
+#define BIT_GET_HI6Q_DESC_NUM_8821C(x) \
+ (((x) >> BIT_SHIFT_HI6Q_DESC_NUM_8821C) & BIT_MASK_HI6Q_DESC_NUM_8821C)
+#define BIT_SET_HI6Q_DESC_NUM_8821C(x, v) \
+ (BIT_CLEAR_HI6Q_DESC_NUM_8821C(x) | BIT_HI6Q_DESC_NUM_8821C(v))
/* 2 REG_HI7Q_TXBD_NUM_8821C */
#define BIT_HI7Q_FLAG_8821C BIT(14)
#define BIT_SHIFT_HI7Q_DESC_MODE_8821C 12
#define BIT_MASK_HI7Q_DESC_MODE_8821C 0x3
-#define BIT_HI7Q_DESC_MODE_8821C(x) (((x) & BIT_MASK_HI7Q_DESC_MODE_8821C) << BIT_SHIFT_HI7Q_DESC_MODE_8821C)
-#define BIT_GET_HI7Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI7Q_DESC_MODE_8821C) & BIT_MASK_HI7Q_DESC_MODE_8821C)
-
+#define BIT_HI7Q_DESC_MODE_8821C(x) \
+ (((x) & BIT_MASK_HI7Q_DESC_MODE_8821C) \
+ << BIT_SHIFT_HI7Q_DESC_MODE_8821C)
+#define BITS_HI7Q_DESC_MODE_8821C \
+ (BIT_MASK_HI7Q_DESC_MODE_8821C << BIT_SHIFT_HI7Q_DESC_MODE_8821C)
+#define BIT_CLEAR_HI7Q_DESC_MODE_8821C(x) ((x) & (~BITS_HI7Q_DESC_MODE_8821C))
+#define BIT_GET_HI7Q_DESC_MODE_8821C(x) \
+ (((x) >> BIT_SHIFT_HI7Q_DESC_MODE_8821C) & \
+ BIT_MASK_HI7Q_DESC_MODE_8821C)
+#define BIT_SET_HI7Q_DESC_MODE_8821C(x, v) \
+ (BIT_CLEAR_HI7Q_DESC_MODE_8821C(x) | BIT_HI7Q_DESC_MODE_8821C(v))
#define BIT_SHIFT_HI7Q_DESC_NUM_8821C 0
#define BIT_MASK_HI7Q_DESC_NUM_8821C 0xfff
-#define BIT_HI7Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI7Q_DESC_NUM_8821C) << BIT_SHIFT_HI7Q_DESC_NUM_8821C)
-#define BIT_GET_HI7Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI7Q_DESC_NUM_8821C) & BIT_MASK_HI7Q_DESC_NUM_8821C)
-
+#define BIT_HI7Q_DESC_NUM_8821C(x) \
+ (((x) & BIT_MASK_HI7Q_DESC_NUM_8821C) << BIT_SHIFT_HI7Q_DESC_NUM_8821C)
+#define BITS_HI7Q_DESC_NUM_8821C \
+ (BIT_MASK_HI7Q_DESC_NUM_8821C << BIT_SHIFT_HI7Q_DESC_NUM_8821C)
+#define BIT_CLEAR_HI7Q_DESC_NUM_8821C(x) ((x) & (~BITS_HI7Q_DESC_NUM_8821C))
+#define BIT_GET_HI7Q_DESC_NUM_8821C(x) \
+ (((x) >> BIT_SHIFT_HI7Q_DESC_NUM_8821C) & BIT_MASK_HI7Q_DESC_NUM_8821C)
+#define BIT_SET_HI7Q_DESC_NUM_8821C(x, v) \
+ (BIT_CLEAR_HI7Q_DESC_NUM_8821C(x) | BIT_HI7Q_DESC_NUM_8821C(v))
/* 2 REG_TSFTIMER_HCI_8821C */
#define BIT_SHIFT_TSFT2_HCI_8821C 16
#define BIT_MASK_TSFT2_HCI_8821C 0xffff
-#define BIT_TSFT2_HCI_8821C(x) (((x) & BIT_MASK_TSFT2_HCI_8821C) << BIT_SHIFT_TSFT2_HCI_8821C)
-#define BIT_GET_TSFT2_HCI_8821C(x) (((x) >> BIT_SHIFT_TSFT2_HCI_8821C) & BIT_MASK_TSFT2_HCI_8821C)
-
+#define BIT_TSFT2_HCI_8821C(x) \
+ (((x) & BIT_MASK_TSFT2_HCI_8821C) << BIT_SHIFT_TSFT2_HCI_8821C)
+#define BITS_TSFT2_HCI_8821C \
+ (BIT_MASK_TSFT2_HCI_8821C << BIT_SHIFT_TSFT2_HCI_8821C)
+#define BIT_CLEAR_TSFT2_HCI_8821C(x) ((x) & (~BITS_TSFT2_HCI_8821C))
+#define BIT_GET_TSFT2_HCI_8821C(x) \
+ (((x) >> BIT_SHIFT_TSFT2_HCI_8821C) & BIT_MASK_TSFT2_HCI_8821C)
+#define BIT_SET_TSFT2_HCI_8821C(x, v) \
+ (BIT_CLEAR_TSFT2_HCI_8821C(x) | BIT_TSFT2_HCI_8821C(v))
#define BIT_SHIFT_TSFT1_HCI_8821C 0
#define BIT_MASK_TSFT1_HCI_8821C 0xffff
-#define BIT_TSFT1_HCI_8821C(x) (((x) & BIT_MASK_TSFT1_HCI_8821C) << BIT_SHIFT_TSFT1_HCI_8821C)
-#define BIT_GET_TSFT1_HCI_8821C(x) (((x) >> BIT_SHIFT_TSFT1_HCI_8821C) & BIT_MASK_TSFT1_HCI_8821C)
-
+#define BIT_TSFT1_HCI_8821C(x) \
+ (((x) & BIT_MASK_TSFT1_HCI_8821C) << BIT_SHIFT_TSFT1_HCI_8821C)
+#define BITS_TSFT1_HCI_8821C \
+ (BIT_MASK_TSFT1_HCI_8821C << BIT_SHIFT_TSFT1_HCI_8821C)
+#define BIT_CLEAR_TSFT1_HCI_8821C(x) ((x) & (~BITS_TSFT1_HCI_8821C))
+#define BIT_GET_TSFT1_HCI_8821C(x) \
+ (((x) >> BIT_SHIFT_TSFT1_HCI_8821C) & BIT_MASK_TSFT1_HCI_8821C)
+#define BIT_SET_TSFT1_HCI_8821C(x, v) \
+ (BIT_CLEAR_TSFT1_HCI_8821C(x) | BIT_TSFT1_HCI_8821C(v))
/* 2 REG_BD_RWPTR_CLR_8821C */
#define BIT_CLR_HI7Q_HW_IDX_8821C BIT(29)
@@ -4278,221 +7784,406 @@
#define BIT_SHIFT_VOQ_HW_IDX_8821C 16
#define BIT_MASK_VOQ_HW_IDX_8821C 0xfff
-#define BIT_VOQ_HW_IDX_8821C(x) (((x) & BIT_MASK_VOQ_HW_IDX_8821C) << BIT_SHIFT_VOQ_HW_IDX_8821C)
-#define BIT_GET_VOQ_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_VOQ_HW_IDX_8821C) & BIT_MASK_VOQ_HW_IDX_8821C)
-
+#define BIT_VOQ_HW_IDX_8821C(x) \
+ (((x) & BIT_MASK_VOQ_HW_IDX_8821C) << BIT_SHIFT_VOQ_HW_IDX_8821C)
+#define BITS_VOQ_HW_IDX_8821C \
+ (BIT_MASK_VOQ_HW_IDX_8821C << BIT_SHIFT_VOQ_HW_IDX_8821C)
+#define BIT_CLEAR_VOQ_HW_IDX_8821C(x) ((x) & (~BITS_VOQ_HW_IDX_8821C))
+#define BIT_GET_VOQ_HW_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_VOQ_HW_IDX_8821C) & BIT_MASK_VOQ_HW_IDX_8821C)
+#define BIT_SET_VOQ_HW_IDX_8821C(x, v) \
+ (BIT_CLEAR_VOQ_HW_IDX_8821C(x) | BIT_VOQ_HW_IDX_8821C(v))
#define BIT_SHIFT_VOQ_HOST_IDX_8821C 0
#define BIT_MASK_VOQ_HOST_IDX_8821C 0xfff
-#define BIT_VOQ_HOST_IDX_8821C(x) (((x) & BIT_MASK_VOQ_HOST_IDX_8821C) << BIT_SHIFT_VOQ_HOST_IDX_8821C)
-#define BIT_GET_VOQ_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_VOQ_HOST_IDX_8821C) & BIT_MASK_VOQ_HOST_IDX_8821C)
-
+#define BIT_VOQ_HOST_IDX_8821C(x) \
+ (((x) & BIT_MASK_VOQ_HOST_IDX_8821C) << BIT_SHIFT_VOQ_HOST_IDX_8821C)
+#define BITS_VOQ_HOST_IDX_8821C \
+ (BIT_MASK_VOQ_HOST_IDX_8821C << BIT_SHIFT_VOQ_HOST_IDX_8821C)
+#define BIT_CLEAR_VOQ_HOST_IDX_8821C(x) ((x) & (~BITS_VOQ_HOST_IDX_8821C))
+#define BIT_GET_VOQ_HOST_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_VOQ_HOST_IDX_8821C) & BIT_MASK_VOQ_HOST_IDX_8821C)
+#define BIT_SET_VOQ_HOST_IDX_8821C(x, v) \
+ (BIT_CLEAR_VOQ_HOST_IDX_8821C(x) | BIT_VOQ_HOST_IDX_8821C(v))
/* 2 REG_VIQ_TXBD_IDX_8821C */
#define BIT_SHIFT_VIQ_HW_IDX_8821C 16
#define BIT_MASK_VIQ_HW_IDX_8821C 0xfff
-#define BIT_VIQ_HW_IDX_8821C(x) (((x) & BIT_MASK_VIQ_HW_IDX_8821C) << BIT_SHIFT_VIQ_HW_IDX_8821C)
-#define BIT_GET_VIQ_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_VIQ_HW_IDX_8821C) & BIT_MASK_VIQ_HW_IDX_8821C)
-
+#define BIT_VIQ_HW_IDX_8821C(x) \
+ (((x) & BIT_MASK_VIQ_HW_IDX_8821C) << BIT_SHIFT_VIQ_HW_IDX_8821C)
+#define BITS_VIQ_HW_IDX_8821C \
+ (BIT_MASK_VIQ_HW_IDX_8821C << BIT_SHIFT_VIQ_HW_IDX_8821C)
+#define BIT_CLEAR_VIQ_HW_IDX_8821C(x) ((x) & (~BITS_VIQ_HW_IDX_8821C))
+#define BIT_GET_VIQ_HW_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_VIQ_HW_IDX_8821C) & BIT_MASK_VIQ_HW_IDX_8821C)
+#define BIT_SET_VIQ_HW_IDX_8821C(x, v) \
+ (BIT_CLEAR_VIQ_HW_IDX_8821C(x) | BIT_VIQ_HW_IDX_8821C(v))
#define BIT_SHIFT_VIQ_HOST_IDX_8821C 0
#define BIT_MASK_VIQ_HOST_IDX_8821C 0xfff
-#define BIT_VIQ_HOST_IDX_8821C(x) (((x) & BIT_MASK_VIQ_HOST_IDX_8821C) << BIT_SHIFT_VIQ_HOST_IDX_8821C)
-#define BIT_GET_VIQ_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_VIQ_HOST_IDX_8821C) & BIT_MASK_VIQ_HOST_IDX_8821C)
-
+#define BIT_VIQ_HOST_IDX_8821C(x) \
+ (((x) & BIT_MASK_VIQ_HOST_IDX_8821C) << BIT_SHIFT_VIQ_HOST_IDX_8821C)
+#define BITS_VIQ_HOST_IDX_8821C \
+ (BIT_MASK_VIQ_HOST_IDX_8821C << BIT_SHIFT_VIQ_HOST_IDX_8821C)
+#define BIT_CLEAR_VIQ_HOST_IDX_8821C(x) ((x) & (~BITS_VIQ_HOST_IDX_8821C))
+#define BIT_GET_VIQ_HOST_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_VIQ_HOST_IDX_8821C) & BIT_MASK_VIQ_HOST_IDX_8821C)
+#define BIT_SET_VIQ_HOST_IDX_8821C(x, v) \
+ (BIT_CLEAR_VIQ_HOST_IDX_8821C(x) | BIT_VIQ_HOST_IDX_8821C(v))
/* 2 REG_BEQ_TXBD_IDX_8821C */
#define BIT_SHIFT_BEQ_HW_IDX_8821C 16
#define BIT_MASK_BEQ_HW_IDX_8821C 0xfff
-#define BIT_BEQ_HW_IDX_8821C(x) (((x) & BIT_MASK_BEQ_HW_IDX_8821C) << BIT_SHIFT_BEQ_HW_IDX_8821C)
-#define BIT_GET_BEQ_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_BEQ_HW_IDX_8821C) & BIT_MASK_BEQ_HW_IDX_8821C)
-
+#define BIT_BEQ_HW_IDX_8821C(x) \
+ (((x) & BIT_MASK_BEQ_HW_IDX_8821C) << BIT_SHIFT_BEQ_HW_IDX_8821C)
+#define BITS_BEQ_HW_IDX_8821C \
+ (BIT_MASK_BEQ_HW_IDX_8821C << BIT_SHIFT_BEQ_HW_IDX_8821C)
+#define BIT_CLEAR_BEQ_HW_IDX_8821C(x) ((x) & (~BITS_BEQ_HW_IDX_8821C))
+#define BIT_GET_BEQ_HW_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_BEQ_HW_IDX_8821C) & BIT_MASK_BEQ_HW_IDX_8821C)
+#define BIT_SET_BEQ_HW_IDX_8821C(x, v) \
+ (BIT_CLEAR_BEQ_HW_IDX_8821C(x) | BIT_BEQ_HW_IDX_8821C(v))
#define BIT_SHIFT_BEQ_HOST_IDX_8821C 0
#define BIT_MASK_BEQ_HOST_IDX_8821C 0xfff
-#define BIT_BEQ_HOST_IDX_8821C(x) (((x) & BIT_MASK_BEQ_HOST_IDX_8821C) << BIT_SHIFT_BEQ_HOST_IDX_8821C)
-#define BIT_GET_BEQ_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_BEQ_HOST_IDX_8821C) & BIT_MASK_BEQ_HOST_IDX_8821C)
-
+#define BIT_BEQ_HOST_IDX_8821C(x) \
+ (((x) & BIT_MASK_BEQ_HOST_IDX_8821C) << BIT_SHIFT_BEQ_HOST_IDX_8821C)
+#define BITS_BEQ_HOST_IDX_8821C \
+ (BIT_MASK_BEQ_HOST_IDX_8821C << BIT_SHIFT_BEQ_HOST_IDX_8821C)
+#define BIT_CLEAR_BEQ_HOST_IDX_8821C(x) ((x) & (~BITS_BEQ_HOST_IDX_8821C))
+#define BIT_GET_BEQ_HOST_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_BEQ_HOST_IDX_8821C) & BIT_MASK_BEQ_HOST_IDX_8821C)
+#define BIT_SET_BEQ_HOST_IDX_8821C(x, v) \
+ (BIT_CLEAR_BEQ_HOST_IDX_8821C(x) | BIT_BEQ_HOST_IDX_8821C(v))
/* 2 REG_BKQ_TXBD_IDX_8821C */
#define BIT_SHIFT_BKQ_HW_IDX_8821C 16
#define BIT_MASK_BKQ_HW_IDX_8821C 0xfff
-#define BIT_BKQ_HW_IDX_8821C(x) (((x) & BIT_MASK_BKQ_HW_IDX_8821C) << BIT_SHIFT_BKQ_HW_IDX_8821C)
-#define BIT_GET_BKQ_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_BKQ_HW_IDX_8821C) & BIT_MASK_BKQ_HW_IDX_8821C)
-
+#define BIT_BKQ_HW_IDX_8821C(x) \
+ (((x) & BIT_MASK_BKQ_HW_IDX_8821C) << BIT_SHIFT_BKQ_HW_IDX_8821C)
+#define BITS_BKQ_HW_IDX_8821C \
+ (BIT_MASK_BKQ_HW_IDX_8821C << BIT_SHIFT_BKQ_HW_IDX_8821C)
+#define BIT_CLEAR_BKQ_HW_IDX_8821C(x) ((x) & (~BITS_BKQ_HW_IDX_8821C))
+#define BIT_GET_BKQ_HW_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_BKQ_HW_IDX_8821C) & BIT_MASK_BKQ_HW_IDX_8821C)
+#define BIT_SET_BKQ_HW_IDX_8821C(x, v) \
+ (BIT_CLEAR_BKQ_HW_IDX_8821C(x) | BIT_BKQ_HW_IDX_8821C(v))
#define BIT_SHIFT_BKQ_HOST_IDX_8821C 0
#define BIT_MASK_BKQ_HOST_IDX_8821C 0xfff
-#define BIT_BKQ_HOST_IDX_8821C(x) (((x) & BIT_MASK_BKQ_HOST_IDX_8821C) << BIT_SHIFT_BKQ_HOST_IDX_8821C)
-#define BIT_GET_BKQ_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_BKQ_HOST_IDX_8821C) & BIT_MASK_BKQ_HOST_IDX_8821C)
-
+#define BIT_BKQ_HOST_IDX_8821C(x) \
+ (((x) & BIT_MASK_BKQ_HOST_IDX_8821C) << BIT_SHIFT_BKQ_HOST_IDX_8821C)
+#define BITS_BKQ_HOST_IDX_8821C \
+ (BIT_MASK_BKQ_HOST_IDX_8821C << BIT_SHIFT_BKQ_HOST_IDX_8821C)
+#define BIT_CLEAR_BKQ_HOST_IDX_8821C(x) ((x) & (~BITS_BKQ_HOST_IDX_8821C))
+#define BIT_GET_BKQ_HOST_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_BKQ_HOST_IDX_8821C) & BIT_MASK_BKQ_HOST_IDX_8821C)
+#define BIT_SET_BKQ_HOST_IDX_8821C(x, v) \
+ (BIT_CLEAR_BKQ_HOST_IDX_8821C(x) | BIT_BKQ_HOST_IDX_8821C(v))
/* 2 REG_MGQ_TXBD_IDX_8821C */
#define BIT_SHIFT_MGQ_HW_IDX_8821C 16
#define BIT_MASK_MGQ_HW_IDX_8821C 0xfff
-#define BIT_MGQ_HW_IDX_8821C(x) (((x) & BIT_MASK_MGQ_HW_IDX_8821C) << BIT_SHIFT_MGQ_HW_IDX_8821C)
-#define BIT_GET_MGQ_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_MGQ_HW_IDX_8821C) & BIT_MASK_MGQ_HW_IDX_8821C)
-
+#define BIT_MGQ_HW_IDX_8821C(x) \
+ (((x) & BIT_MASK_MGQ_HW_IDX_8821C) << BIT_SHIFT_MGQ_HW_IDX_8821C)
+#define BITS_MGQ_HW_IDX_8821C \
+ (BIT_MASK_MGQ_HW_IDX_8821C << BIT_SHIFT_MGQ_HW_IDX_8821C)
+#define BIT_CLEAR_MGQ_HW_IDX_8821C(x) ((x) & (~BITS_MGQ_HW_IDX_8821C))
+#define BIT_GET_MGQ_HW_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_MGQ_HW_IDX_8821C) & BIT_MASK_MGQ_HW_IDX_8821C)
+#define BIT_SET_MGQ_HW_IDX_8821C(x, v) \
+ (BIT_CLEAR_MGQ_HW_IDX_8821C(x) | BIT_MGQ_HW_IDX_8821C(v))
#define BIT_SHIFT_MGQ_HOST_IDX_8821C 0
#define BIT_MASK_MGQ_HOST_IDX_8821C 0xfff
-#define BIT_MGQ_HOST_IDX_8821C(x) (((x) & BIT_MASK_MGQ_HOST_IDX_8821C) << BIT_SHIFT_MGQ_HOST_IDX_8821C)
-#define BIT_GET_MGQ_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_MGQ_HOST_IDX_8821C) & BIT_MASK_MGQ_HOST_IDX_8821C)
-
+#define BIT_MGQ_HOST_IDX_8821C(x) \
+ (((x) & BIT_MASK_MGQ_HOST_IDX_8821C) << BIT_SHIFT_MGQ_HOST_IDX_8821C)
+#define BITS_MGQ_HOST_IDX_8821C \
+ (BIT_MASK_MGQ_HOST_IDX_8821C << BIT_SHIFT_MGQ_HOST_IDX_8821C)
+#define BIT_CLEAR_MGQ_HOST_IDX_8821C(x) ((x) & (~BITS_MGQ_HOST_IDX_8821C))
+#define BIT_GET_MGQ_HOST_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_MGQ_HOST_IDX_8821C) & BIT_MASK_MGQ_HOST_IDX_8821C)
+#define BIT_SET_MGQ_HOST_IDX_8821C(x, v) \
+ (BIT_CLEAR_MGQ_HOST_IDX_8821C(x) | BIT_MGQ_HOST_IDX_8821C(v))
/* 2 REG_RXQ_RXBD_IDX_8821C */
#define BIT_SHIFT_RXQ_HW_IDX_8821C 16
#define BIT_MASK_RXQ_HW_IDX_8821C 0xfff
-#define BIT_RXQ_HW_IDX_8821C(x) (((x) & BIT_MASK_RXQ_HW_IDX_8821C) << BIT_SHIFT_RXQ_HW_IDX_8821C)
-#define BIT_GET_RXQ_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_RXQ_HW_IDX_8821C) & BIT_MASK_RXQ_HW_IDX_8821C)
-
+#define BIT_RXQ_HW_IDX_8821C(x) \
+ (((x) & BIT_MASK_RXQ_HW_IDX_8821C) << BIT_SHIFT_RXQ_HW_IDX_8821C)
+#define BITS_RXQ_HW_IDX_8821C \
+ (BIT_MASK_RXQ_HW_IDX_8821C << BIT_SHIFT_RXQ_HW_IDX_8821C)
+#define BIT_CLEAR_RXQ_HW_IDX_8821C(x) ((x) & (~BITS_RXQ_HW_IDX_8821C))
+#define BIT_GET_RXQ_HW_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_RXQ_HW_IDX_8821C) & BIT_MASK_RXQ_HW_IDX_8821C)
+#define BIT_SET_RXQ_HW_IDX_8821C(x, v) \
+ (BIT_CLEAR_RXQ_HW_IDX_8821C(x) | BIT_RXQ_HW_IDX_8821C(v))
#define BIT_SHIFT_RXQ_HOST_IDX_8821C 0
#define BIT_MASK_RXQ_HOST_IDX_8821C 0xfff
-#define BIT_RXQ_HOST_IDX_8821C(x) (((x) & BIT_MASK_RXQ_HOST_IDX_8821C) << BIT_SHIFT_RXQ_HOST_IDX_8821C)
-#define BIT_GET_RXQ_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_RXQ_HOST_IDX_8821C) & BIT_MASK_RXQ_HOST_IDX_8821C)
-
+#define BIT_RXQ_HOST_IDX_8821C(x) \
+ (((x) & BIT_MASK_RXQ_HOST_IDX_8821C) << BIT_SHIFT_RXQ_HOST_IDX_8821C)
+#define BITS_RXQ_HOST_IDX_8821C \
+ (BIT_MASK_RXQ_HOST_IDX_8821C << BIT_SHIFT_RXQ_HOST_IDX_8821C)
+#define BIT_CLEAR_RXQ_HOST_IDX_8821C(x) ((x) & (~BITS_RXQ_HOST_IDX_8821C))
+#define BIT_GET_RXQ_HOST_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_RXQ_HOST_IDX_8821C) & BIT_MASK_RXQ_HOST_IDX_8821C)
+#define BIT_SET_RXQ_HOST_IDX_8821C(x, v) \
+ (BIT_CLEAR_RXQ_HOST_IDX_8821C(x) | BIT_RXQ_HOST_IDX_8821C(v))
/* 2 REG_HI0Q_TXBD_IDX_8821C */
#define BIT_SHIFT_HI0Q_HW_IDX_8821C 16
#define BIT_MASK_HI0Q_HW_IDX_8821C 0xfff
-#define BIT_HI0Q_HW_IDX_8821C(x) (((x) & BIT_MASK_HI0Q_HW_IDX_8821C) << BIT_SHIFT_HI0Q_HW_IDX_8821C)
-#define BIT_GET_HI0Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI0Q_HW_IDX_8821C) & BIT_MASK_HI0Q_HW_IDX_8821C)
-
+#define BIT_HI0Q_HW_IDX_8821C(x) \
+ (((x) & BIT_MASK_HI0Q_HW_IDX_8821C) << BIT_SHIFT_HI0Q_HW_IDX_8821C)
+#define BITS_HI0Q_HW_IDX_8821C \
+ (BIT_MASK_HI0Q_HW_IDX_8821C << BIT_SHIFT_HI0Q_HW_IDX_8821C)
+#define BIT_CLEAR_HI0Q_HW_IDX_8821C(x) ((x) & (~BITS_HI0Q_HW_IDX_8821C))
+#define BIT_GET_HI0Q_HW_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_HI0Q_HW_IDX_8821C) & BIT_MASK_HI0Q_HW_IDX_8821C)
+#define BIT_SET_HI0Q_HW_IDX_8821C(x, v) \
+ (BIT_CLEAR_HI0Q_HW_IDX_8821C(x) | BIT_HI0Q_HW_IDX_8821C(v))
#define BIT_SHIFT_HI0Q_HOST_IDX_8821C 0
#define BIT_MASK_HI0Q_HOST_IDX_8821C 0xfff
-#define BIT_HI0Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI0Q_HOST_IDX_8821C) << BIT_SHIFT_HI0Q_HOST_IDX_8821C)
-#define BIT_GET_HI0Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI0Q_HOST_IDX_8821C) & BIT_MASK_HI0Q_HOST_IDX_8821C)
-
+#define BIT_HI0Q_HOST_IDX_8821C(x) \
+ (((x) & BIT_MASK_HI0Q_HOST_IDX_8821C) << BIT_SHIFT_HI0Q_HOST_IDX_8821C)
+#define BITS_HI0Q_HOST_IDX_8821C \
+ (BIT_MASK_HI0Q_HOST_IDX_8821C << BIT_SHIFT_HI0Q_HOST_IDX_8821C)
+#define BIT_CLEAR_HI0Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI0Q_HOST_IDX_8821C))
+#define BIT_GET_HI0Q_HOST_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_HI0Q_HOST_IDX_8821C) & BIT_MASK_HI0Q_HOST_IDX_8821C)
+#define BIT_SET_HI0Q_HOST_IDX_8821C(x, v) \
+ (BIT_CLEAR_HI0Q_HOST_IDX_8821C(x) | BIT_HI0Q_HOST_IDX_8821C(v))
/* 2 REG_HI1Q_TXBD_IDX_8821C */
#define BIT_SHIFT_HI1Q_HW_IDX_8821C 16
#define BIT_MASK_HI1Q_HW_IDX_8821C 0xfff
-#define BIT_HI1Q_HW_IDX_8821C(x) (((x) & BIT_MASK_HI1Q_HW_IDX_8821C) << BIT_SHIFT_HI1Q_HW_IDX_8821C)
-#define BIT_GET_HI1Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI1Q_HW_IDX_8821C) & BIT_MASK_HI1Q_HW_IDX_8821C)
-
+#define BIT_HI1Q_HW_IDX_8821C(x) \
+ (((x) & BIT_MASK_HI1Q_HW_IDX_8821C) << BIT_SHIFT_HI1Q_HW_IDX_8821C)
+#define BITS_HI1Q_HW_IDX_8821C \
+ (BIT_MASK_HI1Q_HW_IDX_8821C << BIT_SHIFT_HI1Q_HW_IDX_8821C)
+#define BIT_CLEAR_HI1Q_HW_IDX_8821C(x) ((x) & (~BITS_HI1Q_HW_IDX_8821C))
+#define BIT_GET_HI1Q_HW_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_HI1Q_HW_IDX_8821C) & BIT_MASK_HI1Q_HW_IDX_8821C)
+#define BIT_SET_HI1Q_HW_IDX_8821C(x, v) \
+ (BIT_CLEAR_HI1Q_HW_IDX_8821C(x) | BIT_HI1Q_HW_IDX_8821C(v))
#define BIT_SHIFT_HI1Q_HOST_IDX_8821C 0
#define BIT_MASK_HI1Q_HOST_IDX_8821C 0xfff
-#define BIT_HI1Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI1Q_HOST_IDX_8821C) << BIT_SHIFT_HI1Q_HOST_IDX_8821C)
-#define BIT_GET_HI1Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI1Q_HOST_IDX_8821C) & BIT_MASK_HI1Q_HOST_IDX_8821C)
-
+#define BIT_HI1Q_HOST_IDX_8821C(x) \
+ (((x) & BIT_MASK_HI1Q_HOST_IDX_8821C) << BIT_SHIFT_HI1Q_HOST_IDX_8821C)
+#define BITS_HI1Q_HOST_IDX_8821C \
+ (BIT_MASK_HI1Q_HOST_IDX_8821C << BIT_SHIFT_HI1Q_HOST_IDX_8821C)
+#define BIT_CLEAR_HI1Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI1Q_HOST_IDX_8821C))
+#define BIT_GET_HI1Q_HOST_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_HI1Q_HOST_IDX_8821C) & BIT_MASK_HI1Q_HOST_IDX_8821C)
+#define BIT_SET_HI1Q_HOST_IDX_8821C(x, v) \
+ (BIT_CLEAR_HI1Q_HOST_IDX_8821C(x) | BIT_HI1Q_HOST_IDX_8821C(v))
/* 2 REG_HI2Q_TXBD_IDX_8821C */
#define BIT_SHIFT_HI2Q_HW_IDX_8821C 16
#define BIT_MASK_HI2Q_HW_IDX_8821C 0xfff
-#define BIT_HI2Q_HW_IDX_8821C(x) (((x) & BIT_MASK_HI2Q_HW_IDX_8821C) << BIT_SHIFT_HI2Q_HW_IDX_8821C)
-#define BIT_GET_HI2Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI2Q_HW_IDX_8821C) & BIT_MASK_HI2Q_HW_IDX_8821C)
-
+#define BIT_HI2Q_HW_IDX_8821C(x) \
+ (((x) & BIT_MASK_HI2Q_HW_IDX_8821C) << BIT_SHIFT_HI2Q_HW_IDX_8821C)
+#define BITS_HI2Q_HW_IDX_8821C \
+ (BIT_MASK_HI2Q_HW_IDX_8821C << BIT_SHIFT_HI2Q_HW_IDX_8821C)
+#define BIT_CLEAR_HI2Q_HW_IDX_8821C(x) ((x) & (~BITS_HI2Q_HW_IDX_8821C))
+#define BIT_GET_HI2Q_HW_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_HI2Q_HW_IDX_8821C) & BIT_MASK_HI2Q_HW_IDX_8821C)
+#define BIT_SET_HI2Q_HW_IDX_8821C(x, v) \
+ (BIT_CLEAR_HI2Q_HW_IDX_8821C(x) | BIT_HI2Q_HW_IDX_8821C(v))
#define BIT_SHIFT_HI2Q_HOST_IDX_8821C 0
#define BIT_MASK_HI2Q_HOST_IDX_8821C 0xfff
-#define BIT_HI2Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI2Q_HOST_IDX_8821C) << BIT_SHIFT_HI2Q_HOST_IDX_8821C)
-#define BIT_GET_HI2Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI2Q_HOST_IDX_8821C) & BIT_MASK_HI2Q_HOST_IDX_8821C)
-
+#define BIT_HI2Q_HOST_IDX_8821C(x) \
+ (((x) & BIT_MASK_HI2Q_HOST_IDX_8821C) << BIT_SHIFT_HI2Q_HOST_IDX_8821C)
+#define BITS_HI2Q_HOST_IDX_8821C \
+ (BIT_MASK_HI2Q_HOST_IDX_8821C << BIT_SHIFT_HI2Q_HOST_IDX_8821C)
+#define BIT_CLEAR_HI2Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI2Q_HOST_IDX_8821C))
+#define BIT_GET_HI2Q_HOST_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_HI2Q_HOST_IDX_8821C) & BIT_MASK_HI2Q_HOST_IDX_8821C)
+#define BIT_SET_HI2Q_HOST_IDX_8821C(x, v) \
+ (BIT_CLEAR_HI2Q_HOST_IDX_8821C(x) | BIT_HI2Q_HOST_IDX_8821C(v))
/* 2 REG_HI3Q_TXBD_IDX_8821C */
#define BIT_SHIFT_HI3Q_HW_IDX_8821C 16
#define BIT_MASK_HI3Q_HW_IDX_8821C 0xfff
-#define BIT_HI3Q_HW_IDX_8821C(x) (((x) & BIT_MASK_HI3Q_HW_IDX_8821C) << BIT_SHIFT_HI3Q_HW_IDX_8821C)
-#define BIT_GET_HI3Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI3Q_HW_IDX_8821C) & BIT_MASK_HI3Q_HW_IDX_8821C)
-
+#define BIT_HI3Q_HW_IDX_8821C(x) \
+ (((x) & BIT_MASK_HI3Q_HW_IDX_8821C) << BIT_SHIFT_HI3Q_HW_IDX_8821C)
+#define BITS_HI3Q_HW_IDX_8821C \
+ (BIT_MASK_HI3Q_HW_IDX_8821C << BIT_SHIFT_HI3Q_HW_IDX_8821C)
+#define BIT_CLEAR_HI3Q_HW_IDX_8821C(x) ((x) & (~BITS_HI3Q_HW_IDX_8821C))
+#define BIT_GET_HI3Q_HW_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_HI3Q_HW_IDX_8821C) & BIT_MASK_HI3Q_HW_IDX_8821C)
+#define BIT_SET_HI3Q_HW_IDX_8821C(x, v) \
+ (BIT_CLEAR_HI3Q_HW_IDX_8821C(x) | BIT_HI3Q_HW_IDX_8821C(v))
#define BIT_SHIFT_HI3Q_HOST_IDX_8821C 0
#define BIT_MASK_HI3Q_HOST_IDX_8821C 0xfff
-#define BIT_HI3Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI3Q_HOST_IDX_8821C) << BIT_SHIFT_HI3Q_HOST_IDX_8821C)
-#define BIT_GET_HI3Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI3Q_HOST_IDX_8821C) & BIT_MASK_HI3Q_HOST_IDX_8821C)
-
+#define BIT_HI3Q_HOST_IDX_8821C(x) \
+ (((x) & BIT_MASK_HI3Q_HOST_IDX_8821C) << BIT_SHIFT_HI3Q_HOST_IDX_8821C)
+#define BITS_HI3Q_HOST_IDX_8821C \
+ (BIT_MASK_HI3Q_HOST_IDX_8821C << BIT_SHIFT_HI3Q_HOST_IDX_8821C)
+#define BIT_CLEAR_HI3Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI3Q_HOST_IDX_8821C))
+#define BIT_GET_HI3Q_HOST_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_HI3Q_HOST_IDX_8821C) & BIT_MASK_HI3Q_HOST_IDX_8821C)
+#define BIT_SET_HI3Q_HOST_IDX_8821C(x, v) \
+ (BIT_CLEAR_HI3Q_HOST_IDX_8821C(x) | BIT_HI3Q_HOST_IDX_8821C(v))
/* 2 REG_HI4Q_TXBD_IDX_8821C */
#define BIT_SHIFT_HI4Q_HW_IDX_8821C 16
#define BIT_MASK_HI4Q_HW_IDX_8821C 0xfff
-#define BIT_HI4Q_HW_IDX_8821C(x) (((x) & BIT_MASK_HI4Q_HW_IDX_8821C) << BIT_SHIFT_HI4Q_HW_IDX_8821C)
-#define BIT_GET_HI4Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI4Q_HW_IDX_8821C) & BIT_MASK_HI4Q_HW_IDX_8821C)
-
+#define BIT_HI4Q_HW_IDX_8821C(x) \
+ (((x) & BIT_MASK_HI4Q_HW_IDX_8821C) << BIT_SHIFT_HI4Q_HW_IDX_8821C)
+#define BITS_HI4Q_HW_IDX_8821C \
+ (BIT_MASK_HI4Q_HW_IDX_8821C << BIT_SHIFT_HI4Q_HW_IDX_8821C)
+#define BIT_CLEAR_HI4Q_HW_IDX_8821C(x) ((x) & (~BITS_HI4Q_HW_IDX_8821C))
+#define BIT_GET_HI4Q_HW_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_HI4Q_HW_IDX_8821C) & BIT_MASK_HI4Q_HW_IDX_8821C)
+#define BIT_SET_HI4Q_HW_IDX_8821C(x, v) \
+ (BIT_CLEAR_HI4Q_HW_IDX_8821C(x) | BIT_HI4Q_HW_IDX_8821C(v))
#define BIT_SHIFT_HI4Q_HOST_IDX_8821C 0
#define BIT_MASK_HI4Q_HOST_IDX_8821C 0xfff
-#define BIT_HI4Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI4Q_HOST_IDX_8821C) << BIT_SHIFT_HI4Q_HOST_IDX_8821C)
-#define BIT_GET_HI4Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI4Q_HOST_IDX_8821C) & BIT_MASK_HI4Q_HOST_IDX_8821C)
-
+#define BIT_HI4Q_HOST_IDX_8821C(x) \
+ (((x) & BIT_MASK_HI4Q_HOST_IDX_8821C) << BIT_SHIFT_HI4Q_HOST_IDX_8821C)
+#define BITS_HI4Q_HOST_IDX_8821C \
+ (BIT_MASK_HI4Q_HOST_IDX_8821C << BIT_SHIFT_HI4Q_HOST_IDX_8821C)
+#define BIT_CLEAR_HI4Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI4Q_HOST_IDX_8821C))
+#define BIT_GET_HI4Q_HOST_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_HI4Q_HOST_IDX_8821C) & BIT_MASK_HI4Q_HOST_IDX_8821C)
+#define BIT_SET_HI4Q_HOST_IDX_8821C(x, v) \
+ (BIT_CLEAR_HI4Q_HOST_IDX_8821C(x) | BIT_HI4Q_HOST_IDX_8821C(v))
/* 2 REG_HI5Q_TXBD_IDX_8821C */
#define BIT_SHIFT_HI5Q_HW_IDX_8821C 16
#define BIT_MASK_HI5Q_HW_IDX_8821C 0xfff
-#define BIT_HI5Q_HW_IDX_8821C(x) (((x) & BIT_MASK_HI5Q_HW_IDX_8821C) << BIT_SHIFT_HI5Q_HW_IDX_8821C)
-#define BIT_GET_HI5Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI5Q_HW_IDX_8821C) & BIT_MASK_HI5Q_HW_IDX_8821C)
-
+#define BIT_HI5Q_HW_IDX_8821C(x) \
+ (((x) & BIT_MASK_HI5Q_HW_IDX_8821C) << BIT_SHIFT_HI5Q_HW_IDX_8821C)
+#define BITS_HI5Q_HW_IDX_8821C \
+ (BIT_MASK_HI5Q_HW_IDX_8821C << BIT_SHIFT_HI5Q_HW_IDX_8821C)
+#define BIT_CLEAR_HI5Q_HW_IDX_8821C(x) ((x) & (~BITS_HI5Q_HW_IDX_8821C))
+#define BIT_GET_HI5Q_HW_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_HI5Q_HW_IDX_8821C) & BIT_MASK_HI5Q_HW_IDX_8821C)
+#define BIT_SET_HI5Q_HW_IDX_8821C(x, v) \
+ (BIT_CLEAR_HI5Q_HW_IDX_8821C(x) | BIT_HI5Q_HW_IDX_8821C(v))
#define BIT_SHIFT_HI5Q_HOST_IDX_8821C 0
#define BIT_MASK_HI5Q_HOST_IDX_8821C 0xfff
-#define BIT_HI5Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI5Q_HOST_IDX_8821C) << BIT_SHIFT_HI5Q_HOST_IDX_8821C)
-#define BIT_GET_HI5Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI5Q_HOST_IDX_8821C) & BIT_MASK_HI5Q_HOST_IDX_8821C)
-
+#define BIT_HI5Q_HOST_IDX_8821C(x) \
+ (((x) & BIT_MASK_HI5Q_HOST_IDX_8821C) << BIT_SHIFT_HI5Q_HOST_IDX_8821C)
+#define BITS_HI5Q_HOST_IDX_8821C \
+ (BIT_MASK_HI5Q_HOST_IDX_8821C << BIT_SHIFT_HI5Q_HOST_IDX_8821C)
+#define BIT_CLEAR_HI5Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI5Q_HOST_IDX_8821C))
+#define BIT_GET_HI5Q_HOST_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_HI5Q_HOST_IDX_8821C) & BIT_MASK_HI5Q_HOST_IDX_8821C)
+#define BIT_SET_HI5Q_HOST_IDX_8821C(x, v) \
+ (BIT_CLEAR_HI5Q_HOST_IDX_8821C(x) | BIT_HI5Q_HOST_IDX_8821C(v))
/* 2 REG_HI6Q_TXBD_IDX_8821C */
#define BIT_SHIFT_HI6Q_HW_IDX_8821C 16
#define BIT_MASK_HI6Q_HW_IDX_8821C 0xfff
-#define BIT_HI6Q_HW_IDX_8821C(x) (((x) & BIT_MASK_HI6Q_HW_IDX_8821C) << BIT_SHIFT_HI6Q_HW_IDX_8821C)
-#define BIT_GET_HI6Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI6Q_HW_IDX_8821C) & BIT_MASK_HI6Q_HW_IDX_8821C)
-
+#define BIT_HI6Q_HW_IDX_8821C(x) \
+ (((x) & BIT_MASK_HI6Q_HW_IDX_8821C) << BIT_SHIFT_HI6Q_HW_IDX_8821C)
+#define BITS_HI6Q_HW_IDX_8821C \
+ (BIT_MASK_HI6Q_HW_IDX_8821C << BIT_SHIFT_HI6Q_HW_IDX_8821C)
+#define BIT_CLEAR_HI6Q_HW_IDX_8821C(x) ((x) & (~BITS_HI6Q_HW_IDX_8821C))
+#define BIT_GET_HI6Q_HW_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_HI6Q_HW_IDX_8821C) & BIT_MASK_HI6Q_HW_IDX_8821C)
+#define BIT_SET_HI6Q_HW_IDX_8821C(x, v) \
+ (BIT_CLEAR_HI6Q_HW_IDX_8821C(x) | BIT_HI6Q_HW_IDX_8821C(v))
#define BIT_SHIFT_HI6Q_HOST_IDX_8821C 0
#define BIT_MASK_HI6Q_HOST_IDX_8821C 0xfff
-#define BIT_HI6Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI6Q_HOST_IDX_8821C) << BIT_SHIFT_HI6Q_HOST_IDX_8821C)
-#define BIT_GET_HI6Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI6Q_HOST_IDX_8821C) & BIT_MASK_HI6Q_HOST_IDX_8821C)
-
+#define BIT_HI6Q_HOST_IDX_8821C(x) \
+ (((x) & BIT_MASK_HI6Q_HOST_IDX_8821C) << BIT_SHIFT_HI6Q_HOST_IDX_8821C)
+#define BITS_HI6Q_HOST_IDX_8821C \
+ (BIT_MASK_HI6Q_HOST_IDX_8821C << BIT_SHIFT_HI6Q_HOST_IDX_8821C)
+#define BIT_CLEAR_HI6Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI6Q_HOST_IDX_8821C))
+#define BIT_GET_HI6Q_HOST_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_HI6Q_HOST_IDX_8821C) & BIT_MASK_HI6Q_HOST_IDX_8821C)
+#define BIT_SET_HI6Q_HOST_IDX_8821C(x, v) \
+ (BIT_CLEAR_HI6Q_HOST_IDX_8821C(x) | BIT_HI6Q_HOST_IDX_8821C(v))
/* 2 REG_HI7Q_TXBD_IDX_8821C */
#define BIT_SHIFT_HI7Q_HW_IDX_8821C 16
#define BIT_MASK_HI7Q_HW_IDX_8821C 0xfff
-#define BIT_HI7Q_HW_IDX_8821C(x) (((x) & BIT_MASK_HI7Q_HW_IDX_8821C) << BIT_SHIFT_HI7Q_HW_IDX_8821C)
-#define BIT_GET_HI7Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI7Q_HW_IDX_8821C) & BIT_MASK_HI7Q_HW_IDX_8821C)
-
+#define BIT_HI7Q_HW_IDX_8821C(x) \
+ (((x) & BIT_MASK_HI7Q_HW_IDX_8821C) << BIT_SHIFT_HI7Q_HW_IDX_8821C)
+#define BITS_HI7Q_HW_IDX_8821C \
+ (BIT_MASK_HI7Q_HW_IDX_8821C << BIT_SHIFT_HI7Q_HW_IDX_8821C)
+#define BIT_CLEAR_HI7Q_HW_IDX_8821C(x) ((x) & (~BITS_HI7Q_HW_IDX_8821C))
+#define BIT_GET_HI7Q_HW_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_HI7Q_HW_IDX_8821C) & BIT_MASK_HI7Q_HW_IDX_8821C)
+#define BIT_SET_HI7Q_HW_IDX_8821C(x, v) \
+ (BIT_CLEAR_HI7Q_HW_IDX_8821C(x) | BIT_HI7Q_HW_IDX_8821C(v))
#define BIT_SHIFT_HI7Q_HOST_IDX_8821C 0
#define BIT_MASK_HI7Q_HOST_IDX_8821C 0xfff
-#define BIT_HI7Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI7Q_HOST_IDX_8821C) << BIT_SHIFT_HI7Q_HOST_IDX_8821C)
-#define BIT_GET_HI7Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI7Q_HOST_IDX_8821C) & BIT_MASK_HI7Q_HOST_IDX_8821C)
-
+#define BIT_HI7Q_HOST_IDX_8821C(x) \
+ (((x) & BIT_MASK_HI7Q_HOST_IDX_8821C) << BIT_SHIFT_HI7Q_HOST_IDX_8821C)
+#define BITS_HI7Q_HOST_IDX_8821C \
+ (BIT_MASK_HI7Q_HOST_IDX_8821C << BIT_SHIFT_HI7Q_HOST_IDX_8821C)
+#define BIT_CLEAR_HI7Q_HOST_IDX_8821C(x) ((x) & (~BITS_HI7Q_HOST_IDX_8821C))
+#define BIT_GET_HI7Q_HOST_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_HI7Q_HOST_IDX_8821C) & BIT_MASK_HI7Q_HOST_IDX_8821C)
+#define BIT_SET_HI7Q_HOST_IDX_8821C(x, v) \
+ (BIT_CLEAR_HI7Q_HOST_IDX_8821C(x) | BIT_HI7Q_HOST_IDX_8821C(v))
/* 2 REG_DBG_SEL_V1_8821C */
#define BIT_SHIFT_DBG_SEL_8821C 0
#define BIT_MASK_DBG_SEL_8821C 0xff
-#define BIT_DBG_SEL_8821C(x) (((x) & BIT_MASK_DBG_SEL_8821C) << BIT_SHIFT_DBG_SEL_8821C)
-#define BIT_GET_DBG_SEL_8821C(x) (((x) >> BIT_SHIFT_DBG_SEL_8821C) & BIT_MASK_DBG_SEL_8821C)
-
+#define BIT_DBG_SEL_8821C(x) \
+ (((x) & BIT_MASK_DBG_SEL_8821C) << BIT_SHIFT_DBG_SEL_8821C)
+#define BITS_DBG_SEL_8821C (BIT_MASK_DBG_SEL_8821C << BIT_SHIFT_DBG_SEL_8821C)
+#define BIT_CLEAR_DBG_SEL_8821C(x) ((x) & (~BITS_DBG_SEL_8821C))
+#define BIT_GET_DBG_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_DBG_SEL_8821C) & BIT_MASK_DBG_SEL_8821C)
+#define BIT_SET_DBG_SEL_8821C(x, v) \
+ (BIT_CLEAR_DBG_SEL_8821C(x) | BIT_DBG_SEL_8821C(v))
/* 2 REG_PCIE_HRPWM1_V1_8821C */
#define BIT_SHIFT_PCIE_HRPWM_8821C 0
#define BIT_MASK_PCIE_HRPWM_8821C 0xff
-#define BIT_PCIE_HRPWM_8821C(x) (((x) & BIT_MASK_PCIE_HRPWM_8821C) << BIT_SHIFT_PCIE_HRPWM_8821C)
-#define BIT_GET_PCIE_HRPWM_8821C(x) (((x) >> BIT_SHIFT_PCIE_HRPWM_8821C) & BIT_MASK_PCIE_HRPWM_8821C)
-
+#define BIT_PCIE_HRPWM_8821C(x) \
+ (((x) & BIT_MASK_PCIE_HRPWM_8821C) << BIT_SHIFT_PCIE_HRPWM_8821C)
+#define BITS_PCIE_HRPWM_8821C \
+ (BIT_MASK_PCIE_HRPWM_8821C << BIT_SHIFT_PCIE_HRPWM_8821C)
+#define BIT_CLEAR_PCIE_HRPWM_8821C(x) ((x) & (~BITS_PCIE_HRPWM_8821C))
+#define BIT_GET_PCIE_HRPWM_8821C(x) \
+ (((x) >> BIT_SHIFT_PCIE_HRPWM_8821C) & BIT_MASK_PCIE_HRPWM_8821C)
+#define BIT_SET_PCIE_HRPWM_8821C(x, v) \
+ (BIT_CLEAR_PCIE_HRPWM_8821C(x) | BIT_PCIE_HRPWM_8821C(v))
/* 2 REG_PCIE_HCPWM1_V1_8821C */
#define BIT_SHIFT_PCIE_HCPWM_8821C 0
#define BIT_MASK_PCIE_HCPWM_8821C 0xff
-#define BIT_PCIE_HCPWM_8821C(x) (((x) & BIT_MASK_PCIE_HCPWM_8821C) << BIT_SHIFT_PCIE_HCPWM_8821C)
-#define BIT_GET_PCIE_HCPWM_8821C(x) (((x) >> BIT_SHIFT_PCIE_HCPWM_8821C) & BIT_MASK_PCIE_HCPWM_8821C)
-
+#define BIT_PCIE_HCPWM_8821C(x) \
+ (((x) & BIT_MASK_PCIE_HCPWM_8821C) << BIT_SHIFT_PCIE_HCPWM_8821C)
+#define BITS_PCIE_HCPWM_8821C \
+ (BIT_MASK_PCIE_HCPWM_8821C << BIT_SHIFT_PCIE_HCPWM_8821C)
+#define BIT_CLEAR_PCIE_HCPWM_8821C(x) ((x) & (~BITS_PCIE_HCPWM_8821C))
+#define BIT_GET_PCIE_HCPWM_8821C(x) \
+ (((x) >> BIT_SHIFT_PCIE_HCPWM_8821C) & BIT_MASK_PCIE_HCPWM_8821C)
+#define BIT_SET_PCIE_HCPWM_8821C(x, v) \
+ (BIT_CLEAR_PCIE_HCPWM_8821C(x) | BIT_PCIE_HCPWM_8821C(v))
/* 2 REG_PCIE_CTRL2_8821C */
#define BIT_DIS_TXDMA_PRE_8821C BIT(7)
@@ -4500,8 +8191,15 @@
#define BIT_SHIFT_HPS_CLKR_PCIE_8821C 4
#define BIT_MASK_HPS_CLKR_PCIE_8821C 0x3
-#define BIT_HPS_CLKR_PCIE_8821C(x) (((x) & BIT_MASK_HPS_CLKR_PCIE_8821C) << BIT_SHIFT_HPS_CLKR_PCIE_8821C)
-#define BIT_GET_HPS_CLKR_PCIE_8821C(x) (((x) >> BIT_SHIFT_HPS_CLKR_PCIE_8821C) & BIT_MASK_HPS_CLKR_PCIE_8821C)
+#define BIT_HPS_CLKR_PCIE_8821C(x) \
+ (((x) & BIT_MASK_HPS_CLKR_PCIE_8821C) << BIT_SHIFT_HPS_CLKR_PCIE_8821C)
+#define BITS_HPS_CLKR_PCIE_8821C \
+ (BIT_MASK_HPS_CLKR_PCIE_8821C << BIT_SHIFT_HPS_CLKR_PCIE_8821C)
+#define BIT_CLEAR_HPS_CLKR_PCIE_8821C(x) ((x) & (~BITS_HPS_CLKR_PCIE_8821C))
+#define BIT_GET_HPS_CLKR_PCIE_8821C(x) \
+ (((x) >> BIT_SHIFT_HPS_CLKR_PCIE_8821C) & BIT_MASK_HPS_CLKR_PCIE_8821C)
+#define BIT_SET_HPS_CLKR_PCIE_8821C(x, v) \
+ (BIT_CLEAR_HPS_CLKR_PCIE_8821C(x) | BIT_HPS_CLKR_PCIE_8821C(v))
#define BIT_PCIE_INT_8821C BIT(3)
#define BIT_TXFLAG_EXIT_L1_EN_8821C BIT(2)
@@ -4512,49 +8210,88 @@
#define BIT_SHIFT_PCIE_HRPWM2_8821C 0
#define BIT_MASK_PCIE_HRPWM2_8821C 0xffff
-#define BIT_PCIE_HRPWM2_8821C(x) (((x) & BIT_MASK_PCIE_HRPWM2_8821C) << BIT_SHIFT_PCIE_HRPWM2_8821C)
-#define BIT_GET_PCIE_HRPWM2_8821C(x) (((x) >> BIT_SHIFT_PCIE_HRPWM2_8821C) & BIT_MASK_PCIE_HRPWM2_8821C)
-
+#define BIT_PCIE_HRPWM2_8821C(x) \
+ (((x) & BIT_MASK_PCIE_HRPWM2_8821C) << BIT_SHIFT_PCIE_HRPWM2_8821C)
+#define BITS_PCIE_HRPWM2_8821C \
+ (BIT_MASK_PCIE_HRPWM2_8821C << BIT_SHIFT_PCIE_HRPWM2_8821C)
+#define BIT_CLEAR_PCIE_HRPWM2_8821C(x) ((x) & (~BITS_PCIE_HRPWM2_8821C))
+#define BIT_GET_PCIE_HRPWM2_8821C(x) \
+ (((x) >> BIT_SHIFT_PCIE_HRPWM2_8821C) & BIT_MASK_PCIE_HRPWM2_8821C)
+#define BIT_SET_PCIE_HRPWM2_8821C(x, v) \
+ (BIT_CLEAR_PCIE_HRPWM2_8821C(x) | BIT_PCIE_HRPWM2_8821C(v))
/* 2 REG_PCIE_HCPWM2_V1_8821C */
#define BIT_SHIFT_PCIE_HCPWM2_8821C 0
#define BIT_MASK_PCIE_HCPWM2_8821C 0xffff
-#define BIT_PCIE_HCPWM2_8821C(x) (((x) & BIT_MASK_PCIE_HCPWM2_8821C) << BIT_SHIFT_PCIE_HCPWM2_8821C)
-#define BIT_GET_PCIE_HCPWM2_8821C(x) (((x) >> BIT_SHIFT_PCIE_HCPWM2_8821C) & BIT_MASK_PCIE_HCPWM2_8821C)
-
+#define BIT_PCIE_HCPWM2_8821C(x) \
+ (((x) & BIT_MASK_PCIE_HCPWM2_8821C) << BIT_SHIFT_PCIE_HCPWM2_8821C)
+#define BITS_PCIE_HCPWM2_8821C \
+ (BIT_MASK_PCIE_HCPWM2_8821C << BIT_SHIFT_PCIE_HCPWM2_8821C)
+#define BIT_CLEAR_PCIE_HCPWM2_8821C(x) ((x) & (~BITS_PCIE_HCPWM2_8821C))
+#define BIT_GET_PCIE_HCPWM2_8821C(x) \
+ (((x) >> BIT_SHIFT_PCIE_HCPWM2_8821C) & BIT_MASK_PCIE_HCPWM2_8821C)
+#define BIT_SET_PCIE_HCPWM2_8821C(x, v) \
+ (BIT_CLEAR_PCIE_HCPWM2_8821C(x) | BIT_PCIE_HCPWM2_8821C(v))
/* 2 REG_PCIE_H2C_MSG_V1_8821C */
#define BIT_SHIFT_DRV2FW_INFO_8821C 0
#define BIT_MASK_DRV2FW_INFO_8821C 0xffffffffL
-#define BIT_DRV2FW_INFO_8821C(x) (((x) & BIT_MASK_DRV2FW_INFO_8821C) << BIT_SHIFT_DRV2FW_INFO_8821C)
-#define BIT_GET_DRV2FW_INFO_8821C(x) (((x) >> BIT_SHIFT_DRV2FW_INFO_8821C) & BIT_MASK_DRV2FW_INFO_8821C)
-
+#define BIT_DRV2FW_INFO_8821C(x) \
+ (((x) & BIT_MASK_DRV2FW_INFO_8821C) << BIT_SHIFT_DRV2FW_INFO_8821C)
+#define BITS_DRV2FW_INFO_8821C \
+ (BIT_MASK_DRV2FW_INFO_8821C << BIT_SHIFT_DRV2FW_INFO_8821C)
+#define BIT_CLEAR_DRV2FW_INFO_8821C(x) ((x) & (~BITS_DRV2FW_INFO_8821C))
+#define BIT_GET_DRV2FW_INFO_8821C(x) \
+ (((x) >> BIT_SHIFT_DRV2FW_INFO_8821C) & BIT_MASK_DRV2FW_INFO_8821C)
+#define BIT_SET_DRV2FW_INFO_8821C(x, v) \
+ (BIT_CLEAR_DRV2FW_INFO_8821C(x) | BIT_DRV2FW_INFO_8821C(v))
/* 2 REG_PCIE_C2H_MSG_V1_8821C */
#define BIT_SHIFT_HCI_PCIE_C2H_MSG_8821C 0
#define BIT_MASK_HCI_PCIE_C2H_MSG_8821C 0xffffffffL
-#define BIT_HCI_PCIE_C2H_MSG_8821C(x) (((x) & BIT_MASK_HCI_PCIE_C2H_MSG_8821C) << BIT_SHIFT_HCI_PCIE_C2H_MSG_8821C)
-#define BIT_GET_HCI_PCIE_C2H_MSG_8821C(x) (((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG_8821C) & BIT_MASK_HCI_PCIE_C2H_MSG_8821C)
-
+#define BIT_HCI_PCIE_C2H_MSG_8821C(x) \
+ (((x) & BIT_MASK_HCI_PCIE_C2H_MSG_8821C) \
+ << BIT_SHIFT_HCI_PCIE_C2H_MSG_8821C)
+#define BITS_HCI_PCIE_C2H_MSG_8821C \
+ (BIT_MASK_HCI_PCIE_C2H_MSG_8821C << BIT_SHIFT_HCI_PCIE_C2H_MSG_8821C)
+#define BIT_CLEAR_HCI_PCIE_C2H_MSG_8821C(x) \
+ ((x) & (~BITS_HCI_PCIE_C2H_MSG_8821C))
+#define BIT_GET_HCI_PCIE_C2H_MSG_8821C(x) \
+ (((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG_8821C) & \
+ BIT_MASK_HCI_PCIE_C2H_MSG_8821C)
+#define BIT_SET_HCI_PCIE_C2H_MSG_8821C(x, v) \
+ (BIT_CLEAR_HCI_PCIE_C2H_MSG_8821C(x) | BIT_HCI_PCIE_C2H_MSG_8821C(v))
/* 2 REG_DBI_WDATA_V1_8821C */
#define BIT_SHIFT_DBI_WDATA_8821C 0
#define BIT_MASK_DBI_WDATA_8821C 0xffffffffL
-#define BIT_DBI_WDATA_8821C(x) (((x) & BIT_MASK_DBI_WDATA_8821C) << BIT_SHIFT_DBI_WDATA_8821C)
-#define BIT_GET_DBI_WDATA_8821C(x) (((x) >> BIT_SHIFT_DBI_WDATA_8821C) & BIT_MASK_DBI_WDATA_8821C)
-
+#define BIT_DBI_WDATA_8821C(x) \
+ (((x) & BIT_MASK_DBI_WDATA_8821C) << BIT_SHIFT_DBI_WDATA_8821C)
+#define BITS_DBI_WDATA_8821C \
+ (BIT_MASK_DBI_WDATA_8821C << BIT_SHIFT_DBI_WDATA_8821C)
+#define BIT_CLEAR_DBI_WDATA_8821C(x) ((x) & (~BITS_DBI_WDATA_8821C))
+#define BIT_GET_DBI_WDATA_8821C(x) \
+ (((x) >> BIT_SHIFT_DBI_WDATA_8821C) & BIT_MASK_DBI_WDATA_8821C)
+#define BIT_SET_DBI_WDATA_8821C(x, v) \
+ (BIT_CLEAR_DBI_WDATA_8821C(x) | BIT_DBI_WDATA_8821C(v))
/* 2 REG_DBI_RDATA_V1_8821C */
#define BIT_SHIFT_DBI_RDATA_8821C 0
#define BIT_MASK_DBI_RDATA_8821C 0xffffffffL
-#define BIT_DBI_RDATA_8821C(x) (((x) & BIT_MASK_DBI_RDATA_8821C) << BIT_SHIFT_DBI_RDATA_8821C)
-#define BIT_GET_DBI_RDATA_8821C(x) (((x) >> BIT_SHIFT_DBI_RDATA_8821C) & BIT_MASK_DBI_RDATA_8821C)
-
+#define BIT_DBI_RDATA_8821C(x) \
+ (((x) & BIT_MASK_DBI_RDATA_8821C) << BIT_SHIFT_DBI_RDATA_8821C)
+#define BITS_DBI_RDATA_8821C \
+ (BIT_MASK_DBI_RDATA_8821C << BIT_SHIFT_DBI_RDATA_8821C)
+#define BIT_CLEAR_DBI_RDATA_8821C(x) ((x) & (~BITS_DBI_RDATA_8821C))
+#define BIT_GET_DBI_RDATA_8821C(x) \
+ (((x) >> BIT_SHIFT_DBI_RDATA_8821C) & BIT_MASK_DBI_RDATA_8821C)
+#define BIT_SET_DBI_RDATA_8821C(x, v) \
+ (BIT_CLEAR_DBI_RDATA_8821C(x) | BIT_DBI_RDATA_8821C(v))
/* 2 REG_DBI_FLAG_V1_8821C */
#define BIT_EN_STUCK_DBG_8821C BIT(26)
@@ -4565,42 +8302,84 @@
#define BIT_SHIFT_DBI_WREN_8821C 12
#define BIT_MASK_DBI_WREN_8821C 0xf
-#define BIT_DBI_WREN_8821C(x) (((x) & BIT_MASK_DBI_WREN_8821C) << BIT_SHIFT_DBI_WREN_8821C)
-#define BIT_GET_DBI_WREN_8821C(x) (((x) >> BIT_SHIFT_DBI_WREN_8821C) & BIT_MASK_DBI_WREN_8821C)
-
+#define BIT_DBI_WREN_8821C(x) \
+ (((x) & BIT_MASK_DBI_WREN_8821C) << BIT_SHIFT_DBI_WREN_8821C)
+#define BITS_DBI_WREN_8821C \
+ (BIT_MASK_DBI_WREN_8821C << BIT_SHIFT_DBI_WREN_8821C)
+#define BIT_CLEAR_DBI_WREN_8821C(x) ((x) & (~BITS_DBI_WREN_8821C))
+#define BIT_GET_DBI_WREN_8821C(x) \
+ (((x) >> BIT_SHIFT_DBI_WREN_8821C) & BIT_MASK_DBI_WREN_8821C)
+#define BIT_SET_DBI_WREN_8821C(x, v) \
+ (BIT_CLEAR_DBI_WREN_8821C(x) | BIT_DBI_WREN_8821C(v))
#define BIT_SHIFT_DBI_ADDR_8821C 0
#define BIT_MASK_DBI_ADDR_8821C 0xfff
-#define BIT_DBI_ADDR_8821C(x) (((x) & BIT_MASK_DBI_ADDR_8821C) << BIT_SHIFT_DBI_ADDR_8821C)
-#define BIT_GET_DBI_ADDR_8821C(x) (((x) >> BIT_SHIFT_DBI_ADDR_8821C) & BIT_MASK_DBI_ADDR_8821C)
-
+#define BIT_DBI_ADDR_8821C(x) \
+ (((x) & BIT_MASK_DBI_ADDR_8821C) << BIT_SHIFT_DBI_ADDR_8821C)
+#define BITS_DBI_ADDR_8821C \
+ (BIT_MASK_DBI_ADDR_8821C << BIT_SHIFT_DBI_ADDR_8821C)
+#define BIT_CLEAR_DBI_ADDR_8821C(x) ((x) & (~BITS_DBI_ADDR_8821C))
+#define BIT_GET_DBI_ADDR_8821C(x) \
+ (((x) >> BIT_SHIFT_DBI_ADDR_8821C) & BIT_MASK_DBI_ADDR_8821C)
+#define BIT_SET_DBI_ADDR_8821C(x, v) \
+ (BIT_CLEAR_DBI_ADDR_8821C(x) | BIT_DBI_ADDR_8821C(v))
/* 2 REG_MDIO_V1_8821C */
#define BIT_SHIFT_MDIO_RDATA_8821C 16
#define BIT_MASK_MDIO_RDATA_8821C 0xffff
-#define BIT_MDIO_RDATA_8821C(x) (((x) & BIT_MASK_MDIO_RDATA_8821C) << BIT_SHIFT_MDIO_RDATA_8821C)
-#define BIT_GET_MDIO_RDATA_8821C(x) (((x) >> BIT_SHIFT_MDIO_RDATA_8821C) & BIT_MASK_MDIO_RDATA_8821C)
-
+#define BIT_MDIO_RDATA_8821C(x) \
+ (((x) & BIT_MASK_MDIO_RDATA_8821C) << BIT_SHIFT_MDIO_RDATA_8821C)
+#define BITS_MDIO_RDATA_8821C \
+ (BIT_MASK_MDIO_RDATA_8821C << BIT_SHIFT_MDIO_RDATA_8821C)
+#define BIT_CLEAR_MDIO_RDATA_8821C(x) ((x) & (~BITS_MDIO_RDATA_8821C))
+#define BIT_GET_MDIO_RDATA_8821C(x) \
+ (((x) >> BIT_SHIFT_MDIO_RDATA_8821C) & BIT_MASK_MDIO_RDATA_8821C)
+#define BIT_SET_MDIO_RDATA_8821C(x, v) \
+ (BIT_CLEAR_MDIO_RDATA_8821C(x) | BIT_MDIO_RDATA_8821C(v))
#define BIT_SHIFT_MDIO_WDATA_8821C 0
#define BIT_MASK_MDIO_WDATA_8821C 0xffff
-#define BIT_MDIO_WDATA_8821C(x) (((x) & BIT_MASK_MDIO_WDATA_8821C) << BIT_SHIFT_MDIO_WDATA_8821C)
-#define BIT_GET_MDIO_WDATA_8821C(x) (((x) >> BIT_SHIFT_MDIO_WDATA_8821C) & BIT_MASK_MDIO_WDATA_8821C)
-
+#define BIT_MDIO_WDATA_8821C(x) \
+ (((x) & BIT_MASK_MDIO_WDATA_8821C) << BIT_SHIFT_MDIO_WDATA_8821C)
+#define BITS_MDIO_WDATA_8821C \
+ (BIT_MASK_MDIO_WDATA_8821C << BIT_SHIFT_MDIO_WDATA_8821C)
+#define BIT_CLEAR_MDIO_WDATA_8821C(x) ((x) & (~BITS_MDIO_WDATA_8821C))
+#define BIT_GET_MDIO_WDATA_8821C(x) \
+ (((x) >> BIT_SHIFT_MDIO_WDATA_8821C) & BIT_MASK_MDIO_WDATA_8821C)
+#define BIT_SET_MDIO_WDATA_8821C(x, v) \
+ (BIT_CLEAR_MDIO_WDATA_8821C(x) | BIT_MDIO_WDATA_8821C(v))
/* 2 REG_PCIE_MIX_CFG_8821C */
#define BIT_SHIFT_MDIO_PHY_ADDR_8821C 24
#define BIT_MASK_MDIO_PHY_ADDR_8821C 0x1f
-#define BIT_MDIO_PHY_ADDR_8821C(x) (((x) & BIT_MASK_MDIO_PHY_ADDR_8821C) << BIT_SHIFT_MDIO_PHY_ADDR_8821C)
-#define BIT_GET_MDIO_PHY_ADDR_8821C(x) (((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8821C) & BIT_MASK_MDIO_PHY_ADDR_8821C)
-
+#define BIT_MDIO_PHY_ADDR_8821C(x) \
+ (((x) & BIT_MASK_MDIO_PHY_ADDR_8821C) << BIT_SHIFT_MDIO_PHY_ADDR_8821C)
+#define BITS_MDIO_PHY_ADDR_8821C \
+ (BIT_MASK_MDIO_PHY_ADDR_8821C << BIT_SHIFT_MDIO_PHY_ADDR_8821C)
+#define BIT_CLEAR_MDIO_PHY_ADDR_8821C(x) ((x) & (~BITS_MDIO_PHY_ADDR_8821C))
+#define BIT_GET_MDIO_PHY_ADDR_8821C(x) \
+ (((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8821C) & BIT_MASK_MDIO_PHY_ADDR_8821C)
+#define BIT_SET_MDIO_PHY_ADDR_8821C(x, v) \
+ (BIT_CLEAR_MDIO_PHY_ADDR_8821C(x) | BIT_MDIO_PHY_ADDR_8821C(v))
#define BIT_SHIFT_WATCH_DOG_RECORD_V1_8821C 10
#define BIT_MASK_WATCH_DOG_RECORD_V1_8821C 0x3fff
-#define BIT_WATCH_DOG_RECORD_V1_8821C(x) (((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8821C) << BIT_SHIFT_WATCH_DOG_RECORD_V1_8821C)
-#define BIT_GET_WATCH_DOG_RECORD_V1_8821C(x) (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8821C) & BIT_MASK_WATCH_DOG_RECORD_V1_8821C)
+#define BIT_WATCH_DOG_RECORD_V1_8821C(x) \
+ (((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8821C) \
+ << BIT_SHIFT_WATCH_DOG_RECORD_V1_8821C)
+#define BITS_WATCH_DOG_RECORD_V1_8821C \
+ (BIT_MASK_WATCH_DOG_RECORD_V1_8821C \
+ << BIT_SHIFT_WATCH_DOG_RECORD_V1_8821C)
+#define BIT_CLEAR_WATCH_DOG_RECORD_V1_8821C(x) \
+ ((x) & (~BITS_WATCH_DOG_RECORD_V1_8821C))
+#define BIT_GET_WATCH_DOG_RECORD_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8821C) & \
+ BIT_MASK_WATCH_DOG_RECORD_V1_8821C)
+#define BIT_SET_WATCH_DOG_RECORD_V1_8821C(x, v) \
+ (BIT_CLEAR_WATCH_DOG_RECORD_V1_8821C(x) | \
+ BIT_WATCH_DOG_RECORD_V1_8821C(v))
#define BIT_R_IO_TIMEOUT_FLAG_V1_8821C BIT(9)
#define BIT_EN_WATCH_DOG_8821C BIT(8)
@@ -4610,30 +8389,66 @@
#define BIT_SHIFT_MDIO_REG_ADDR_V1_8821C 0
#define BIT_MASK_MDIO_REG_ADDR_V1_8821C 0x1f
-#define BIT_MDIO_REG_ADDR_V1_8821C(x) (((x) & BIT_MASK_MDIO_REG_ADDR_V1_8821C) << BIT_SHIFT_MDIO_REG_ADDR_V1_8821C)
-#define BIT_GET_MDIO_REG_ADDR_V1_8821C(x) (((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1_8821C) & BIT_MASK_MDIO_REG_ADDR_V1_8821C)
-
+#define BIT_MDIO_REG_ADDR_V1_8821C(x) \
+ (((x) & BIT_MASK_MDIO_REG_ADDR_V1_8821C) \
+ << BIT_SHIFT_MDIO_REG_ADDR_V1_8821C)
+#define BITS_MDIO_REG_ADDR_V1_8821C \
+ (BIT_MASK_MDIO_REG_ADDR_V1_8821C << BIT_SHIFT_MDIO_REG_ADDR_V1_8821C)
+#define BIT_CLEAR_MDIO_REG_ADDR_V1_8821C(x) \
+ ((x) & (~BITS_MDIO_REG_ADDR_V1_8821C))
+#define BIT_GET_MDIO_REG_ADDR_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1_8821C) & \
+ BIT_MASK_MDIO_REG_ADDR_V1_8821C)
+#define BIT_SET_MDIO_REG_ADDR_V1_8821C(x, v) \
+ (BIT_CLEAR_MDIO_REG_ADDR_V1_8821C(x) | BIT_MDIO_REG_ADDR_V1_8821C(v))
/* 2 REG_HCI_MIX_CFG_8821C */
#define BIT_HOST_GEN2_SUPPORT_8821C BIT(20)
#define BIT_SHIFT_TXDMA_ERR_FLAG_8821C 16
#define BIT_MASK_TXDMA_ERR_FLAG_8821C 0xf
-#define BIT_TXDMA_ERR_FLAG_8821C(x) (((x) & BIT_MASK_TXDMA_ERR_FLAG_8821C) << BIT_SHIFT_TXDMA_ERR_FLAG_8821C)
-#define BIT_GET_TXDMA_ERR_FLAG_8821C(x) (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_8821C) & BIT_MASK_TXDMA_ERR_FLAG_8821C)
-
+#define BIT_TXDMA_ERR_FLAG_8821C(x) \
+ (((x) & BIT_MASK_TXDMA_ERR_FLAG_8821C) \
+ << BIT_SHIFT_TXDMA_ERR_FLAG_8821C)
+#define BITS_TXDMA_ERR_FLAG_8821C \
+ (BIT_MASK_TXDMA_ERR_FLAG_8821C << BIT_SHIFT_TXDMA_ERR_FLAG_8821C)
+#define BIT_CLEAR_TXDMA_ERR_FLAG_8821C(x) ((x) & (~BITS_TXDMA_ERR_FLAG_8821C))
+#define BIT_GET_TXDMA_ERR_FLAG_8821C(x) \
+ (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_8821C) & \
+ BIT_MASK_TXDMA_ERR_FLAG_8821C)
+#define BIT_SET_TXDMA_ERR_FLAG_8821C(x, v) \
+ (BIT_CLEAR_TXDMA_ERR_FLAG_8821C(x) | BIT_TXDMA_ERR_FLAG_8821C(v))
#define BIT_SHIFT_EARLY_MODE_SEL_8821C 12
#define BIT_MASK_EARLY_MODE_SEL_8821C 0xf
-#define BIT_EARLY_MODE_SEL_8821C(x) (((x) & BIT_MASK_EARLY_MODE_SEL_8821C) << BIT_SHIFT_EARLY_MODE_SEL_8821C)
-#define BIT_GET_EARLY_MODE_SEL_8821C(x) (((x) >> BIT_SHIFT_EARLY_MODE_SEL_8821C) & BIT_MASK_EARLY_MODE_SEL_8821C)
+#define BIT_EARLY_MODE_SEL_8821C(x) \
+ (((x) & BIT_MASK_EARLY_MODE_SEL_8821C) \
+ << BIT_SHIFT_EARLY_MODE_SEL_8821C)
+#define BITS_EARLY_MODE_SEL_8821C \
+ (BIT_MASK_EARLY_MODE_SEL_8821C << BIT_SHIFT_EARLY_MODE_SEL_8821C)
+#define BIT_CLEAR_EARLY_MODE_SEL_8821C(x) ((x) & (~BITS_EARLY_MODE_SEL_8821C))
+#define BIT_GET_EARLY_MODE_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_EARLY_MODE_SEL_8821C) & \
+ BIT_MASK_EARLY_MODE_SEL_8821C)
+#define BIT_SET_EARLY_MODE_SEL_8821C(x, v) \
+ (BIT_CLEAR_EARLY_MODE_SEL_8821C(x) | BIT_EARLY_MODE_SEL_8821C(v))
#define BIT_EPHY_RX50_EN_8821C BIT(11)
#define BIT_SHIFT_MSI_TIMEOUT_ID_V1_8821C 8
#define BIT_MASK_MSI_TIMEOUT_ID_V1_8821C 0x7
-#define BIT_MSI_TIMEOUT_ID_V1_8821C(x) (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8821C) << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8821C)
-#define BIT_GET_MSI_TIMEOUT_ID_V1_8821C(x) (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8821C) & BIT_MASK_MSI_TIMEOUT_ID_V1_8821C)
+#define BIT_MSI_TIMEOUT_ID_V1_8821C(x) \
+ (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8821C) \
+ << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8821C)
+#define BITS_MSI_TIMEOUT_ID_V1_8821C \
+ (BIT_MASK_MSI_TIMEOUT_ID_V1_8821C << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8821C)
+#define BIT_CLEAR_MSI_TIMEOUT_ID_V1_8821C(x) \
+ ((x) & (~BITS_MSI_TIMEOUT_ID_V1_8821C))
+#define BIT_GET_MSI_TIMEOUT_ID_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8821C) & \
+ BIT_MASK_MSI_TIMEOUT_ID_V1_8821C)
+#define BIT_SET_MSI_TIMEOUT_ID_V1_8821C(x, v) \
+ (BIT_CLEAR_MSI_TIMEOUT_ID_V1_8821C(x) | BIT_MSI_TIMEOUT_ID_V1_8821C(v))
#define BIT_RADDR_RD_8821C BIT(7)
#define BIT_EN_MUL_TAG_8821C BIT(6)
@@ -4648,36 +8463,77 @@
#define BIT_SHIFT_STC_INT_FLAG_8821C 16
#define BIT_MASK_STC_INT_FLAG_8821C 0xff
-#define BIT_STC_INT_FLAG_8821C(x) (((x) & BIT_MASK_STC_INT_FLAG_8821C) << BIT_SHIFT_STC_INT_FLAG_8821C)
-#define BIT_GET_STC_INT_FLAG_8821C(x) (((x) >> BIT_SHIFT_STC_INT_FLAG_8821C) & BIT_MASK_STC_INT_FLAG_8821C)
-
+#define BIT_STC_INT_FLAG_8821C(x) \
+ (((x) & BIT_MASK_STC_INT_FLAG_8821C) << BIT_SHIFT_STC_INT_FLAG_8821C)
+#define BITS_STC_INT_FLAG_8821C \
+ (BIT_MASK_STC_INT_FLAG_8821C << BIT_SHIFT_STC_INT_FLAG_8821C)
+#define BIT_CLEAR_STC_INT_FLAG_8821C(x) ((x) & (~BITS_STC_INT_FLAG_8821C))
+#define BIT_GET_STC_INT_FLAG_8821C(x) \
+ (((x) >> BIT_SHIFT_STC_INT_FLAG_8821C) & BIT_MASK_STC_INT_FLAG_8821C)
+#define BIT_SET_STC_INT_FLAG_8821C(x, v) \
+ (BIT_CLEAR_STC_INT_FLAG_8821C(x) | BIT_STC_INT_FLAG_8821C(v))
#define BIT_SHIFT_STC_INT_IDX_8821C 8
#define BIT_MASK_STC_INT_IDX_8821C 0x7
-#define BIT_STC_INT_IDX_8821C(x) (((x) & BIT_MASK_STC_INT_IDX_8821C) << BIT_SHIFT_STC_INT_IDX_8821C)
-#define BIT_GET_STC_INT_IDX_8821C(x) (((x) >> BIT_SHIFT_STC_INT_IDX_8821C) & BIT_MASK_STC_INT_IDX_8821C)
-
+#define BIT_STC_INT_IDX_8821C(x) \
+ (((x) & BIT_MASK_STC_INT_IDX_8821C) << BIT_SHIFT_STC_INT_IDX_8821C)
+#define BITS_STC_INT_IDX_8821C \
+ (BIT_MASK_STC_INT_IDX_8821C << BIT_SHIFT_STC_INT_IDX_8821C)
+#define BIT_CLEAR_STC_INT_IDX_8821C(x) ((x) & (~BITS_STC_INT_IDX_8821C))
+#define BIT_GET_STC_INT_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_STC_INT_IDX_8821C) & BIT_MASK_STC_INT_IDX_8821C)
+#define BIT_SET_STC_INT_IDX_8821C(x, v) \
+ (BIT_CLEAR_STC_INT_IDX_8821C(x) | BIT_STC_INT_IDX_8821C(v))
#define BIT_SHIFT_STC_INT_REALTIME_CS_8821C 0
#define BIT_MASK_STC_INT_REALTIME_CS_8821C 0x3f
-#define BIT_STC_INT_REALTIME_CS_8821C(x) (((x) & BIT_MASK_STC_INT_REALTIME_CS_8821C) << BIT_SHIFT_STC_INT_REALTIME_CS_8821C)
-#define BIT_GET_STC_INT_REALTIME_CS_8821C(x) (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8821C) & BIT_MASK_STC_INT_REALTIME_CS_8821C)
-
+#define BIT_STC_INT_REALTIME_CS_8821C(x) \
+ (((x) & BIT_MASK_STC_INT_REALTIME_CS_8821C) \
+ << BIT_SHIFT_STC_INT_REALTIME_CS_8821C)
+#define BITS_STC_INT_REALTIME_CS_8821C \
+ (BIT_MASK_STC_INT_REALTIME_CS_8821C \
+ << BIT_SHIFT_STC_INT_REALTIME_CS_8821C)
+#define BIT_CLEAR_STC_INT_REALTIME_CS_8821C(x) \
+ ((x) & (~BITS_STC_INT_REALTIME_CS_8821C))
+#define BIT_GET_STC_INT_REALTIME_CS_8821C(x) \
+ (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8821C) & \
+ BIT_MASK_STC_INT_REALTIME_CS_8821C)
+#define BIT_SET_STC_INT_REALTIME_CS_8821C(x, v) \
+ (BIT_CLEAR_STC_INT_REALTIME_CS_8821C(x) | \
+ BIT_STC_INT_REALTIME_CS_8821C(v))
/* 2 REG_ST_INT_CFG_8821C(PCIE STATE CHANGE INTERRUPT CONFIGURATION) */
#define BIT_STC_INT_GRP_EN_8821C BIT(31)
#define BIT_SHIFT_STC_INT_EXPECT_LS_8821C 8
#define BIT_MASK_STC_INT_EXPECT_LS_8821C 0x3f
-#define BIT_STC_INT_EXPECT_LS_8821C(x) (((x) & BIT_MASK_STC_INT_EXPECT_LS_8821C) << BIT_SHIFT_STC_INT_EXPECT_LS_8821C)
-#define BIT_GET_STC_INT_EXPECT_LS_8821C(x) (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8821C) & BIT_MASK_STC_INT_EXPECT_LS_8821C)
-
+#define BIT_STC_INT_EXPECT_LS_8821C(x) \
+ (((x) & BIT_MASK_STC_INT_EXPECT_LS_8821C) \
+ << BIT_SHIFT_STC_INT_EXPECT_LS_8821C)
+#define BITS_STC_INT_EXPECT_LS_8821C \
+ (BIT_MASK_STC_INT_EXPECT_LS_8821C << BIT_SHIFT_STC_INT_EXPECT_LS_8821C)
+#define BIT_CLEAR_STC_INT_EXPECT_LS_8821C(x) \
+ ((x) & (~BITS_STC_INT_EXPECT_LS_8821C))
+#define BIT_GET_STC_INT_EXPECT_LS_8821C(x) \
+ (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8821C) & \
+ BIT_MASK_STC_INT_EXPECT_LS_8821C)
+#define BIT_SET_STC_INT_EXPECT_LS_8821C(x, v) \
+ (BIT_CLEAR_STC_INT_EXPECT_LS_8821C(x) | BIT_STC_INT_EXPECT_LS_8821C(v))
#define BIT_SHIFT_STC_INT_EXPECT_CS_8821C 0
#define BIT_MASK_STC_INT_EXPECT_CS_8821C 0x3f
-#define BIT_STC_INT_EXPECT_CS_8821C(x) (((x) & BIT_MASK_STC_INT_EXPECT_CS_8821C) << BIT_SHIFT_STC_INT_EXPECT_CS_8821C)
-#define BIT_GET_STC_INT_EXPECT_CS_8821C(x) (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8821C) & BIT_MASK_STC_INT_EXPECT_CS_8821C)
-
+#define BIT_STC_INT_EXPECT_CS_8821C(x) \
+ (((x) & BIT_MASK_STC_INT_EXPECT_CS_8821C) \
+ << BIT_SHIFT_STC_INT_EXPECT_CS_8821C)
+#define BITS_STC_INT_EXPECT_CS_8821C \
+ (BIT_MASK_STC_INT_EXPECT_CS_8821C << BIT_SHIFT_STC_INT_EXPECT_CS_8821C)
+#define BIT_CLEAR_STC_INT_EXPECT_CS_8821C(x) \
+ ((x) & (~BITS_STC_INT_EXPECT_CS_8821C))
+#define BIT_GET_STC_INT_EXPECT_CS_8821C(x) \
+ (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8821C) & \
+ BIT_MASK_STC_INT_EXPECT_CS_8821C)
+#define BIT_SET_STC_INT_EXPECT_CS_8821C(x, v) \
+ (BIT_CLEAR_STC_INT_EXPECT_CS_8821C(x) | BIT_STC_INT_EXPECT_CS_8821C(v))
/* 2 REG_CMU_DLY_CTRL_8821C(PCIE PHY CLOCK MGT UNIT DELAY CONTROL ) */
#define BIT_CMU_DLY_EN_8821C BIT(31)
@@ -4685,247 +8541,529 @@
#define BIT_SHIFT_CMU_DLY_PRE_DIV_8821C 0
#define BIT_MASK_CMU_DLY_PRE_DIV_8821C 0xff
-#define BIT_CMU_DLY_PRE_DIV_8821C(x) (((x) & BIT_MASK_CMU_DLY_PRE_DIV_8821C) << BIT_SHIFT_CMU_DLY_PRE_DIV_8821C)
-#define BIT_GET_CMU_DLY_PRE_DIV_8821C(x) (((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV_8821C) & BIT_MASK_CMU_DLY_PRE_DIV_8821C)
-
+#define BIT_CMU_DLY_PRE_DIV_8821C(x) \
+ (((x) & BIT_MASK_CMU_DLY_PRE_DIV_8821C) \
+ << BIT_SHIFT_CMU_DLY_PRE_DIV_8821C)
+#define BITS_CMU_DLY_PRE_DIV_8821C \
+ (BIT_MASK_CMU_DLY_PRE_DIV_8821C << BIT_SHIFT_CMU_DLY_PRE_DIV_8821C)
+#define BIT_CLEAR_CMU_DLY_PRE_DIV_8821C(x) ((x) & (~BITS_CMU_DLY_PRE_DIV_8821C))
+#define BIT_GET_CMU_DLY_PRE_DIV_8821C(x) \
+ (((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV_8821C) & \
+ BIT_MASK_CMU_DLY_PRE_DIV_8821C)
+#define BIT_SET_CMU_DLY_PRE_DIV_8821C(x, v) \
+ (BIT_CLEAR_CMU_DLY_PRE_DIV_8821C(x) | BIT_CMU_DLY_PRE_DIV_8821C(v))
/* 2 REG_CMU_DLY_CFG_8821C(PCIE PHY CLOCK MGT UNIT DELAY CONFIGURATION ) */
#define BIT_SHIFT_CMU_DLY_LTR_A2I_8821C 24
#define BIT_MASK_CMU_DLY_LTR_A2I_8821C 0xff
-#define BIT_CMU_DLY_LTR_A2I_8821C(x) (((x) & BIT_MASK_CMU_DLY_LTR_A2I_8821C) << BIT_SHIFT_CMU_DLY_LTR_A2I_8821C)
-#define BIT_GET_CMU_DLY_LTR_A2I_8821C(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I_8821C) & BIT_MASK_CMU_DLY_LTR_A2I_8821C)
-
+#define BIT_CMU_DLY_LTR_A2I_8821C(x) \
+ (((x) & BIT_MASK_CMU_DLY_LTR_A2I_8821C) \
+ << BIT_SHIFT_CMU_DLY_LTR_A2I_8821C)
+#define BITS_CMU_DLY_LTR_A2I_8821C \
+ (BIT_MASK_CMU_DLY_LTR_A2I_8821C << BIT_SHIFT_CMU_DLY_LTR_A2I_8821C)
+#define BIT_CLEAR_CMU_DLY_LTR_A2I_8821C(x) ((x) & (~BITS_CMU_DLY_LTR_A2I_8821C))
+#define BIT_GET_CMU_DLY_LTR_A2I_8821C(x) \
+ (((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I_8821C) & \
+ BIT_MASK_CMU_DLY_LTR_A2I_8821C)
+#define BIT_SET_CMU_DLY_LTR_A2I_8821C(x, v) \
+ (BIT_CLEAR_CMU_DLY_LTR_A2I_8821C(x) | BIT_CMU_DLY_LTR_A2I_8821C(v))
#define BIT_SHIFT_CMU_DLY_LTR_I2A_8821C 16
#define BIT_MASK_CMU_DLY_LTR_I2A_8821C 0xff
-#define BIT_CMU_DLY_LTR_I2A_8821C(x) (((x) & BIT_MASK_CMU_DLY_LTR_I2A_8821C) << BIT_SHIFT_CMU_DLY_LTR_I2A_8821C)
-#define BIT_GET_CMU_DLY_LTR_I2A_8821C(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A_8821C) & BIT_MASK_CMU_DLY_LTR_I2A_8821C)
-
+#define BIT_CMU_DLY_LTR_I2A_8821C(x) \
+ (((x) & BIT_MASK_CMU_DLY_LTR_I2A_8821C) \
+ << BIT_SHIFT_CMU_DLY_LTR_I2A_8821C)
+#define BITS_CMU_DLY_LTR_I2A_8821C \
+ (BIT_MASK_CMU_DLY_LTR_I2A_8821C << BIT_SHIFT_CMU_DLY_LTR_I2A_8821C)
+#define BIT_CLEAR_CMU_DLY_LTR_I2A_8821C(x) ((x) & (~BITS_CMU_DLY_LTR_I2A_8821C))
+#define BIT_GET_CMU_DLY_LTR_I2A_8821C(x) \
+ (((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A_8821C) & \
+ BIT_MASK_CMU_DLY_LTR_I2A_8821C)
+#define BIT_SET_CMU_DLY_LTR_I2A_8821C(x, v) \
+ (BIT_CLEAR_CMU_DLY_LTR_I2A_8821C(x) | BIT_CMU_DLY_LTR_I2A_8821C(v))
#define BIT_SHIFT_CMU_DLY_LTR_IDLE_8821C 8
#define BIT_MASK_CMU_DLY_LTR_IDLE_8821C 0xff
-#define BIT_CMU_DLY_LTR_IDLE_8821C(x) (((x) & BIT_MASK_CMU_DLY_LTR_IDLE_8821C) << BIT_SHIFT_CMU_DLY_LTR_IDLE_8821C)
-#define BIT_GET_CMU_DLY_LTR_IDLE_8821C(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE_8821C) & BIT_MASK_CMU_DLY_LTR_IDLE_8821C)
-
+#define BIT_CMU_DLY_LTR_IDLE_8821C(x) \
+ (((x) & BIT_MASK_CMU_DLY_LTR_IDLE_8821C) \
+ << BIT_SHIFT_CMU_DLY_LTR_IDLE_8821C)
+#define BITS_CMU_DLY_LTR_IDLE_8821C \
+ (BIT_MASK_CMU_DLY_LTR_IDLE_8821C << BIT_SHIFT_CMU_DLY_LTR_IDLE_8821C)
+#define BIT_CLEAR_CMU_DLY_LTR_IDLE_8821C(x) \
+ ((x) & (~BITS_CMU_DLY_LTR_IDLE_8821C))
+#define BIT_GET_CMU_DLY_LTR_IDLE_8821C(x) \
+ (((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE_8821C) & \
+ BIT_MASK_CMU_DLY_LTR_IDLE_8821C)
+#define BIT_SET_CMU_DLY_LTR_IDLE_8821C(x, v) \
+ (BIT_CLEAR_CMU_DLY_LTR_IDLE_8821C(x) | BIT_CMU_DLY_LTR_IDLE_8821C(v))
#define BIT_SHIFT_CMU_DLY_LTR_ACT_8821C 0
#define BIT_MASK_CMU_DLY_LTR_ACT_8821C 0xff
-#define BIT_CMU_DLY_LTR_ACT_8821C(x) (((x) & BIT_MASK_CMU_DLY_LTR_ACT_8821C) << BIT_SHIFT_CMU_DLY_LTR_ACT_8821C)
-#define BIT_GET_CMU_DLY_LTR_ACT_8821C(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT_8821C) & BIT_MASK_CMU_DLY_LTR_ACT_8821C)
-
+#define BIT_CMU_DLY_LTR_ACT_8821C(x) \
+ (((x) & BIT_MASK_CMU_DLY_LTR_ACT_8821C) \
+ << BIT_SHIFT_CMU_DLY_LTR_ACT_8821C)
+#define BITS_CMU_DLY_LTR_ACT_8821C \
+ (BIT_MASK_CMU_DLY_LTR_ACT_8821C << BIT_SHIFT_CMU_DLY_LTR_ACT_8821C)
+#define BIT_CLEAR_CMU_DLY_LTR_ACT_8821C(x) ((x) & (~BITS_CMU_DLY_LTR_ACT_8821C))
+#define BIT_GET_CMU_DLY_LTR_ACT_8821C(x) \
+ (((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT_8821C) & \
+ BIT_MASK_CMU_DLY_LTR_ACT_8821C)
+#define BIT_SET_CMU_DLY_LTR_ACT_8821C(x, v) \
+ (BIT_CLEAR_CMU_DLY_LTR_ACT_8821C(x) | BIT_CMU_DLY_LTR_ACT_8821C(v))
/* 2 REG_H2CQ_TXBD_DESA_8821C */
#define BIT_SHIFT_H2CQ_TXBD_DESA_8821C 0
#define BIT_MASK_H2CQ_TXBD_DESA_8821C 0xffffffffffffffffL
-#define BIT_H2CQ_TXBD_DESA_8821C(x) (((x) & BIT_MASK_H2CQ_TXBD_DESA_8821C) << BIT_SHIFT_H2CQ_TXBD_DESA_8821C)
-#define BIT_GET_H2CQ_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_8821C) & BIT_MASK_H2CQ_TXBD_DESA_8821C)
-
+#define BIT_H2CQ_TXBD_DESA_8821C(x) \
+ (((x) & BIT_MASK_H2CQ_TXBD_DESA_8821C) \
+ << BIT_SHIFT_H2CQ_TXBD_DESA_8821C)
+#define BITS_H2CQ_TXBD_DESA_8821C \
+ (BIT_MASK_H2CQ_TXBD_DESA_8821C << BIT_SHIFT_H2CQ_TXBD_DESA_8821C)
+#define BIT_CLEAR_H2CQ_TXBD_DESA_8821C(x) ((x) & (~BITS_H2CQ_TXBD_DESA_8821C))
+#define BIT_GET_H2CQ_TXBD_DESA_8821C(x) \
+ (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_8821C) & \
+ BIT_MASK_H2CQ_TXBD_DESA_8821C)
+#define BIT_SET_H2CQ_TXBD_DESA_8821C(x, v) \
+ (BIT_CLEAR_H2CQ_TXBD_DESA_8821C(x) | BIT_H2CQ_TXBD_DESA_8821C(v))
/* 2 REG_H2CQ_TXBD_NUM_8821C */
#define BIT_PCIE_H2CQ_FLAG_8821C BIT(14)
#define BIT_SHIFT_H2CQ_DESC_MODE_8821C 12
#define BIT_MASK_H2CQ_DESC_MODE_8821C 0x3
-#define BIT_H2CQ_DESC_MODE_8821C(x) (((x) & BIT_MASK_H2CQ_DESC_MODE_8821C) << BIT_SHIFT_H2CQ_DESC_MODE_8821C)
-#define BIT_GET_H2CQ_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8821C) & BIT_MASK_H2CQ_DESC_MODE_8821C)
-
+#define BIT_H2CQ_DESC_MODE_8821C(x) \
+ (((x) & BIT_MASK_H2CQ_DESC_MODE_8821C) \
+ << BIT_SHIFT_H2CQ_DESC_MODE_8821C)
+#define BITS_H2CQ_DESC_MODE_8821C \
+ (BIT_MASK_H2CQ_DESC_MODE_8821C << BIT_SHIFT_H2CQ_DESC_MODE_8821C)
+#define BIT_CLEAR_H2CQ_DESC_MODE_8821C(x) ((x) & (~BITS_H2CQ_DESC_MODE_8821C))
+#define BIT_GET_H2CQ_DESC_MODE_8821C(x) \
+ (((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8821C) & \
+ BIT_MASK_H2CQ_DESC_MODE_8821C)
+#define BIT_SET_H2CQ_DESC_MODE_8821C(x, v) \
+ (BIT_CLEAR_H2CQ_DESC_MODE_8821C(x) | BIT_H2CQ_DESC_MODE_8821C(v))
#define BIT_SHIFT_H2CQ_DESC_NUM_8821C 0
#define BIT_MASK_H2CQ_DESC_NUM_8821C 0xfff
-#define BIT_H2CQ_DESC_NUM_8821C(x) (((x) & BIT_MASK_H2CQ_DESC_NUM_8821C) << BIT_SHIFT_H2CQ_DESC_NUM_8821C)
-#define BIT_GET_H2CQ_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8821C) & BIT_MASK_H2CQ_DESC_NUM_8821C)
-
+#define BIT_H2CQ_DESC_NUM_8821C(x) \
+ (((x) & BIT_MASK_H2CQ_DESC_NUM_8821C) << BIT_SHIFT_H2CQ_DESC_NUM_8821C)
+#define BITS_H2CQ_DESC_NUM_8821C \
+ (BIT_MASK_H2CQ_DESC_NUM_8821C << BIT_SHIFT_H2CQ_DESC_NUM_8821C)
+#define BIT_CLEAR_H2CQ_DESC_NUM_8821C(x) ((x) & (~BITS_H2CQ_DESC_NUM_8821C))
+#define BIT_GET_H2CQ_DESC_NUM_8821C(x) \
+ (((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8821C) & BIT_MASK_H2CQ_DESC_NUM_8821C)
+#define BIT_SET_H2CQ_DESC_NUM_8821C(x, v) \
+ (BIT_CLEAR_H2CQ_DESC_NUM_8821C(x) | BIT_H2CQ_DESC_NUM_8821C(v))
/* 2 REG_H2CQ_TXBD_IDX_8821C */
#define BIT_SHIFT_H2CQ_HW_IDX_8821C 16
#define BIT_MASK_H2CQ_HW_IDX_8821C 0xfff
-#define BIT_H2CQ_HW_IDX_8821C(x) (((x) & BIT_MASK_H2CQ_HW_IDX_8821C) << BIT_SHIFT_H2CQ_HW_IDX_8821C)
-#define BIT_GET_H2CQ_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_H2CQ_HW_IDX_8821C) & BIT_MASK_H2CQ_HW_IDX_8821C)
-
+#define BIT_H2CQ_HW_IDX_8821C(x) \
+ (((x) & BIT_MASK_H2CQ_HW_IDX_8821C) << BIT_SHIFT_H2CQ_HW_IDX_8821C)
+#define BITS_H2CQ_HW_IDX_8821C \
+ (BIT_MASK_H2CQ_HW_IDX_8821C << BIT_SHIFT_H2CQ_HW_IDX_8821C)
+#define BIT_CLEAR_H2CQ_HW_IDX_8821C(x) ((x) & (~BITS_H2CQ_HW_IDX_8821C))
+#define BIT_GET_H2CQ_HW_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_H2CQ_HW_IDX_8821C) & BIT_MASK_H2CQ_HW_IDX_8821C)
+#define BIT_SET_H2CQ_HW_IDX_8821C(x, v) \
+ (BIT_CLEAR_H2CQ_HW_IDX_8821C(x) | BIT_H2CQ_HW_IDX_8821C(v))
#define BIT_SHIFT_H2CQ_HOST_IDX_8821C 0
#define BIT_MASK_H2CQ_HOST_IDX_8821C 0xfff
-#define BIT_H2CQ_HOST_IDX_8821C(x) (((x) & BIT_MASK_H2CQ_HOST_IDX_8821C) << BIT_SHIFT_H2CQ_HOST_IDX_8821C)
-#define BIT_GET_H2CQ_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8821C) & BIT_MASK_H2CQ_HOST_IDX_8821C)
-
+#define BIT_H2CQ_HOST_IDX_8821C(x) \
+ (((x) & BIT_MASK_H2CQ_HOST_IDX_8821C) << BIT_SHIFT_H2CQ_HOST_IDX_8821C)
+#define BITS_H2CQ_HOST_IDX_8821C \
+ (BIT_MASK_H2CQ_HOST_IDX_8821C << BIT_SHIFT_H2CQ_HOST_IDX_8821C)
+#define BIT_CLEAR_H2CQ_HOST_IDX_8821C(x) ((x) & (~BITS_H2CQ_HOST_IDX_8821C))
+#define BIT_GET_H2CQ_HOST_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8821C) & BIT_MASK_H2CQ_HOST_IDX_8821C)
+#define BIT_SET_H2CQ_HOST_IDX_8821C(x, v) \
+ (BIT_CLEAR_H2CQ_HOST_IDX_8821C(x) | BIT_H2CQ_HOST_IDX_8821C(v))
/* 2 REG_H2CQ_CSR_8821C[31:0] (H2CQ CONTROL AND STATUS) */
#define BIT_H2CQ_FULL_8821C BIT(31)
#define BIT_CLR_H2CQ_HOST_IDX_8821C BIT(16)
#define BIT_CLR_H2CQ_HW_IDX_8821C BIT(8)
+#define BIT_STOP_H2CQ_8821C BIT(0)
+
+/* 2 REG_NOT_VALID_8821C */
/* 2 REG_Q0_INFO_8821C */
#define BIT_SHIFT_QUEUEMACID_Q0_V1_8821C 25
#define BIT_MASK_QUEUEMACID_Q0_V1_8821C 0x7f
-#define BIT_QUEUEMACID_Q0_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_Q0_V1_8821C) << BIT_SHIFT_QUEUEMACID_Q0_V1_8821C)
-#define BIT_GET_QUEUEMACID_Q0_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1_8821C) & BIT_MASK_QUEUEMACID_Q0_V1_8821C)
-
+#define BIT_QUEUEMACID_Q0_V1_8821C(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q0_V1_8821C) \
+ << BIT_SHIFT_QUEUEMACID_Q0_V1_8821C)
+#define BITS_QUEUEMACID_Q0_V1_8821C \
+ (BIT_MASK_QUEUEMACID_Q0_V1_8821C << BIT_SHIFT_QUEUEMACID_Q0_V1_8821C)
+#define BIT_CLEAR_QUEUEMACID_Q0_V1_8821C(x) \
+ ((x) & (~BITS_QUEUEMACID_Q0_V1_8821C))
+#define BIT_GET_QUEUEMACID_Q0_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1_8821C) & \
+ BIT_MASK_QUEUEMACID_Q0_V1_8821C)
+#define BIT_SET_QUEUEMACID_Q0_V1_8821C(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q0_V1_8821C(x) | BIT_QUEUEMACID_Q0_V1_8821C(v))
#define BIT_SHIFT_QUEUEAC_Q0_V1_8821C 23
#define BIT_MASK_QUEUEAC_Q0_V1_8821C 0x3
-#define BIT_QUEUEAC_Q0_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q0_V1_8821C) << BIT_SHIFT_QUEUEAC_Q0_V1_8821C)
-#define BIT_GET_QUEUEAC_Q0_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q0_V1_8821C) & BIT_MASK_QUEUEAC_Q0_V1_8821C)
+#define BIT_QUEUEAC_Q0_V1_8821C(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q0_V1_8821C) << BIT_SHIFT_QUEUEAC_Q0_V1_8821C)
+#define BITS_QUEUEAC_Q0_V1_8821C \
+ (BIT_MASK_QUEUEAC_Q0_V1_8821C << BIT_SHIFT_QUEUEAC_Q0_V1_8821C)
+#define BIT_CLEAR_QUEUEAC_Q0_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q0_V1_8821C))
+#define BIT_GET_QUEUEAC_Q0_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q0_V1_8821C) & BIT_MASK_QUEUEAC_Q0_V1_8821C)
+#define BIT_SET_QUEUEAC_Q0_V1_8821C(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q0_V1_8821C(x) | BIT_QUEUEAC_Q0_V1_8821C(v))
#define BIT_TIDEMPTY_Q0_V1_8821C BIT(22)
#define BIT_SHIFT_TAIL_PKT_Q0_V2_8821C 11
#define BIT_MASK_TAIL_PKT_Q0_V2_8821C 0x7ff
-#define BIT_TAIL_PKT_Q0_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_Q0_V2_8821C) << BIT_SHIFT_TAIL_PKT_Q0_V2_8821C)
-#define BIT_GET_TAIL_PKT_Q0_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2_8821C) & BIT_MASK_TAIL_PKT_Q0_V2_8821C)
-
+#define BIT_TAIL_PKT_Q0_V2_8821C(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q0_V2_8821C) \
+ << BIT_SHIFT_TAIL_PKT_Q0_V2_8821C)
+#define BITS_TAIL_PKT_Q0_V2_8821C \
+ (BIT_MASK_TAIL_PKT_Q0_V2_8821C << BIT_SHIFT_TAIL_PKT_Q0_V2_8821C)
+#define BIT_CLEAR_TAIL_PKT_Q0_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q0_V2_8821C))
+#define BIT_GET_TAIL_PKT_Q0_V2_8821C(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2_8821C) & \
+ BIT_MASK_TAIL_PKT_Q0_V2_8821C)
+#define BIT_SET_TAIL_PKT_Q0_V2_8821C(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q0_V2_8821C(x) | BIT_TAIL_PKT_Q0_V2_8821C(v))
#define BIT_SHIFT_HEAD_PKT_Q0_V1_8821C 0
#define BIT_MASK_HEAD_PKT_Q0_V1_8821C 0x7ff
-#define BIT_HEAD_PKT_Q0_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q0_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q0_V1_8821C)
-#define BIT_GET_HEAD_PKT_Q0_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1_8821C) & BIT_MASK_HEAD_PKT_Q0_V1_8821C)
-
+#define BIT_HEAD_PKT_Q0_V1_8821C(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q0_V1_8821C) \
+ << BIT_SHIFT_HEAD_PKT_Q0_V1_8821C)
+#define BITS_HEAD_PKT_Q0_V1_8821C \
+ (BIT_MASK_HEAD_PKT_Q0_V1_8821C << BIT_SHIFT_HEAD_PKT_Q0_V1_8821C)
+#define BIT_CLEAR_HEAD_PKT_Q0_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q0_V1_8821C))
+#define BIT_GET_HEAD_PKT_Q0_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1_8821C) & \
+ BIT_MASK_HEAD_PKT_Q0_V1_8821C)
+#define BIT_SET_HEAD_PKT_Q0_V1_8821C(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q0_V1_8821C(x) | BIT_HEAD_PKT_Q0_V1_8821C(v))
/* 2 REG_Q1_INFO_8821C */
#define BIT_SHIFT_QUEUEMACID_Q1_V1_8821C 25
#define BIT_MASK_QUEUEMACID_Q1_V1_8821C 0x7f
-#define BIT_QUEUEMACID_Q1_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_Q1_V1_8821C) << BIT_SHIFT_QUEUEMACID_Q1_V1_8821C)
-#define BIT_GET_QUEUEMACID_Q1_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1_8821C) & BIT_MASK_QUEUEMACID_Q1_V1_8821C)
-
+#define BIT_QUEUEMACID_Q1_V1_8821C(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q1_V1_8821C) \
+ << BIT_SHIFT_QUEUEMACID_Q1_V1_8821C)
+#define BITS_QUEUEMACID_Q1_V1_8821C \
+ (BIT_MASK_QUEUEMACID_Q1_V1_8821C << BIT_SHIFT_QUEUEMACID_Q1_V1_8821C)
+#define BIT_CLEAR_QUEUEMACID_Q1_V1_8821C(x) \
+ ((x) & (~BITS_QUEUEMACID_Q1_V1_8821C))
+#define BIT_GET_QUEUEMACID_Q1_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1_8821C) & \
+ BIT_MASK_QUEUEMACID_Q1_V1_8821C)
+#define BIT_SET_QUEUEMACID_Q1_V1_8821C(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q1_V1_8821C(x) | BIT_QUEUEMACID_Q1_V1_8821C(v))
#define BIT_SHIFT_QUEUEAC_Q1_V1_8821C 23
#define BIT_MASK_QUEUEAC_Q1_V1_8821C 0x3
-#define BIT_QUEUEAC_Q1_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q1_V1_8821C) << BIT_SHIFT_QUEUEAC_Q1_V1_8821C)
-#define BIT_GET_QUEUEAC_Q1_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q1_V1_8821C) & BIT_MASK_QUEUEAC_Q1_V1_8821C)
+#define BIT_QUEUEAC_Q1_V1_8821C(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q1_V1_8821C) << BIT_SHIFT_QUEUEAC_Q1_V1_8821C)
+#define BITS_QUEUEAC_Q1_V1_8821C \
+ (BIT_MASK_QUEUEAC_Q1_V1_8821C << BIT_SHIFT_QUEUEAC_Q1_V1_8821C)
+#define BIT_CLEAR_QUEUEAC_Q1_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q1_V1_8821C))
+#define BIT_GET_QUEUEAC_Q1_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q1_V1_8821C) & BIT_MASK_QUEUEAC_Q1_V1_8821C)
+#define BIT_SET_QUEUEAC_Q1_V1_8821C(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q1_V1_8821C(x) | BIT_QUEUEAC_Q1_V1_8821C(v))
#define BIT_TIDEMPTY_Q1_V1_8821C BIT(22)
#define BIT_SHIFT_TAIL_PKT_Q1_V2_8821C 11
#define BIT_MASK_TAIL_PKT_Q1_V2_8821C 0x7ff
-#define BIT_TAIL_PKT_Q1_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_Q1_V2_8821C) << BIT_SHIFT_TAIL_PKT_Q1_V2_8821C)
-#define BIT_GET_TAIL_PKT_Q1_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2_8821C) & BIT_MASK_TAIL_PKT_Q1_V2_8821C)
-
+#define BIT_TAIL_PKT_Q1_V2_8821C(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q1_V2_8821C) \
+ << BIT_SHIFT_TAIL_PKT_Q1_V2_8821C)
+#define BITS_TAIL_PKT_Q1_V2_8821C \
+ (BIT_MASK_TAIL_PKT_Q1_V2_8821C << BIT_SHIFT_TAIL_PKT_Q1_V2_8821C)
+#define BIT_CLEAR_TAIL_PKT_Q1_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q1_V2_8821C))
+#define BIT_GET_TAIL_PKT_Q1_V2_8821C(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2_8821C) & \
+ BIT_MASK_TAIL_PKT_Q1_V2_8821C)
+#define BIT_SET_TAIL_PKT_Q1_V2_8821C(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q1_V2_8821C(x) | BIT_TAIL_PKT_Q1_V2_8821C(v))
#define BIT_SHIFT_HEAD_PKT_Q1_V1_8821C 0
#define BIT_MASK_HEAD_PKT_Q1_V1_8821C 0x7ff
-#define BIT_HEAD_PKT_Q1_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q1_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q1_V1_8821C)
-#define BIT_GET_HEAD_PKT_Q1_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1_8821C) & BIT_MASK_HEAD_PKT_Q1_V1_8821C)
-
+#define BIT_HEAD_PKT_Q1_V1_8821C(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q1_V1_8821C) \
+ << BIT_SHIFT_HEAD_PKT_Q1_V1_8821C)
+#define BITS_HEAD_PKT_Q1_V1_8821C \
+ (BIT_MASK_HEAD_PKT_Q1_V1_8821C << BIT_SHIFT_HEAD_PKT_Q1_V1_8821C)
+#define BIT_CLEAR_HEAD_PKT_Q1_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q1_V1_8821C))
+#define BIT_GET_HEAD_PKT_Q1_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1_8821C) & \
+ BIT_MASK_HEAD_PKT_Q1_V1_8821C)
+#define BIT_SET_HEAD_PKT_Q1_V1_8821C(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q1_V1_8821C(x) | BIT_HEAD_PKT_Q1_V1_8821C(v))
/* 2 REG_Q2_INFO_8821C */
#define BIT_SHIFT_QUEUEMACID_Q2_V1_8821C 25
#define BIT_MASK_QUEUEMACID_Q2_V1_8821C 0x7f
-#define BIT_QUEUEMACID_Q2_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_Q2_V1_8821C) << BIT_SHIFT_QUEUEMACID_Q2_V1_8821C)
-#define BIT_GET_QUEUEMACID_Q2_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1_8821C) & BIT_MASK_QUEUEMACID_Q2_V1_8821C)
-
+#define BIT_QUEUEMACID_Q2_V1_8821C(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q2_V1_8821C) \
+ << BIT_SHIFT_QUEUEMACID_Q2_V1_8821C)
+#define BITS_QUEUEMACID_Q2_V1_8821C \
+ (BIT_MASK_QUEUEMACID_Q2_V1_8821C << BIT_SHIFT_QUEUEMACID_Q2_V1_8821C)
+#define BIT_CLEAR_QUEUEMACID_Q2_V1_8821C(x) \
+ ((x) & (~BITS_QUEUEMACID_Q2_V1_8821C))
+#define BIT_GET_QUEUEMACID_Q2_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1_8821C) & \
+ BIT_MASK_QUEUEMACID_Q2_V1_8821C)
+#define BIT_SET_QUEUEMACID_Q2_V1_8821C(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q2_V1_8821C(x) | BIT_QUEUEMACID_Q2_V1_8821C(v))
#define BIT_SHIFT_QUEUEAC_Q2_V1_8821C 23
#define BIT_MASK_QUEUEAC_Q2_V1_8821C 0x3
-#define BIT_QUEUEAC_Q2_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q2_V1_8821C) << BIT_SHIFT_QUEUEAC_Q2_V1_8821C)
-#define BIT_GET_QUEUEAC_Q2_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q2_V1_8821C) & BIT_MASK_QUEUEAC_Q2_V1_8821C)
+#define BIT_QUEUEAC_Q2_V1_8821C(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q2_V1_8821C) << BIT_SHIFT_QUEUEAC_Q2_V1_8821C)
+#define BITS_QUEUEAC_Q2_V1_8821C \
+ (BIT_MASK_QUEUEAC_Q2_V1_8821C << BIT_SHIFT_QUEUEAC_Q2_V1_8821C)
+#define BIT_CLEAR_QUEUEAC_Q2_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q2_V1_8821C))
+#define BIT_GET_QUEUEAC_Q2_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q2_V1_8821C) & BIT_MASK_QUEUEAC_Q2_V1_8821C)
+#define BIT_SET_QUEUEAC_Q2_V1_8821C(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q2_V1_8821C(x) | BIT_QUEUEAC_Q2_V1_8821C(v))
#define BIT_TIDEMPTY_Q2_V1_8821C BIT(22)
#define BIT_SHIFT_TAIL_PKT_Q2_V2_8821C 11
#define BIT_MASK_TAIL_PKT_Q2_V2_8821C 0x7ff
-#define BIT_TAIL_PKT_Q2_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_Q2_V2_8821C) << BIT_SHIFT_TAIL_PKT_Q2_V2_8821C)
-#define BIT_GET_TAIL_PKT_Q2_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2_8821C) & BIT_MASK_TAIL_PKT_Q2_V2_8821C)
-
+#define BIT_TAIL_PKT_Q2_V2_8821C(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q2_V2_8821C) \
+ << BIT_SHIFT_TAIL_PKT_Q2_V2_8821C)
+#define BITS_TAIL_PKT_Q2_V2_8821C \
+ (BIT_MASK_TAIL_PKT_Q2_V2_8821C << BIT_SHIFT_TAIL_PKT_Q2_V2_8821C)
+#define BIT_CLEAR_TAIL_PKT_Q2_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q2_V2_8821C))
+#define BIT_GET_TAIL_PKT_Q2_V2_8821C(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2_8821C) & \
+ BIT_MASK_TAIL_PKT_Q2_V2_8821C)
+#define BIT_SET_TAIL_PKT_Q2_V2_8821C(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q2_V2_8821C(x) | BIT_TAIL_PKT_Q2_V2_8821C(v))
#define BIT_SHIFT_HEAD_PKT_Q2_V1_8821C 0
#define BIT_MASK_HEAD_PKT_Q2_V1_8821C 0x7ff
-#define BIT_HEAD_PKT_Q2_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q2_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q2_V1_8821C)
-#define BIT_GET_HEAD_PKT_Q2_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1_8821C) & BIT_MASK_HEAD_PKT_Q2_V1_8821C)
-
+#define BIT_HEAD_PKT_Q2_V1_8821C(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q2_V1_8821C) \
+ << BIT_SHIFT_HEAD_PKT_Q2_V1_8821C)
+#define BITS_HEAD_PKT_Q2_V1_8821C \
+ (BIT_MASK_HEAD_PKT_Q2_V1_8821C << BIT_SHIFT_HEAD_PKT_Q2_V1_8821C)
+#define BIT_CLEAR_HEAD_PKT_Q2_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q2_V1_8821C))
+#define BIT_GET_HEAD_PKT_Q2_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1_8821C) & \
+ BIT_MASK_HEAD_PKT_Q2_V1_8821C)
+#define BIT_SET_HEAD_PKT_Q2_V1_8821C(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q2_V1_8821C(x) | BIT_HEAD_PKT_Q2_V1_8821C(v))
/* 2 REG_Q3_INFO_8821C */
#define BIT_SHIFT_QUEUEMACID_Q3_V1_8821C 25
#define BIT_MASK_QUEUEMACID_Q3_V1_8821C 0x7f
-#define BIT_QUEUEMACID_Q3_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_Q3_V1_8821C) << BIT_SHIFT_QUEUEMACID_Q3_V1_8821C)
-#define BIT_GET_QUEUEMACID_Q3_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1_8821C) & BIT_MASK_QUEUEMACID_Q3_V1_8821C)
-
+#define BIT_QUEUEMACID_Q3_V1_8821C(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q3_V1_8821C) \
+ << BIT_SHIFT_QUEUEMACID_Q3_V1_8821C)
+#define BITS_QUEUEMACID_Q3_V1_8821C \
+ (BIT_MASK_QUEUEMACID_Q3_V1_8821C << BIT_SHIFT_QUEUEMACID_Q3_V1_8821C)
+#define BIT_CLEAR_QUEUEMACID_Q3_V1_8821C(x) \
+ ((x) & (~BITS_QUEUEMACID_Q3_V1_8821C))
+#define BIT_GET_QUEUEMACID_Q3_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1_8821C) & \
+ BIT_MASK_QUEUEMACID_Q3_V1_8821C)
+#define BIT_SET_QUEUEMACID_Q3_V1_8821C(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q3_V1_8821C(x) | BIT_QUEUEMACID_Q3_V1_8821C(v))
#define BIT_SHIFT_QUEUEAC_Q3_V1_8821C 23
#define BIT_MASK_QUEUEAC_Q3_V1_8821C 0x3
-#define BIT_QUEUEAC_Q3_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q3_V1_8821C) << BIT_SHIFT_QUEUEAC_Q3_V1_8821C)
-#define BIT_GET_QUEUEAC_Q3_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q3_V1_8821C) & BIT_MASK_QUEUEAC_Q3_V1_8821C)
+#define BIT_QUEUEAC_Q3_V1_8821C(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q3_V1_8821C) << BIT_SHIFT_QUEUEAC_Q3_V1_8821C)
+#define BITS_QUEUEAC_Q3_V1_8821C \
+ (BIT_MASK_QUEUEAC_Q3_V1_8821C << BIT_SHIFT_QUEUEAC_Q3_V1_8821C)
+#define BIT_CLEAR_QUEUEAC_Q3_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q3_V1_8821C))
+#define BIT_GET_QUEUEAC_Q3_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q3_V1_8821C) & BIT_MASK_QUEUEAC_Q3_V1_8821C)
+#define BIT_SET_QUEUEAC_Q3_V1_8821C(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q3_V1_8821C(x) | BIT_QUEUEAC_Q3_V1_8821C(v))
#define BIT_TIDEMPTY_Q3_V1_8821C BIT(22)
#define BIT_SHIFT_TAIL_PKT_Q3_V2_8821C 11
#define BIT_MASK_TAIL_PKT_Q3_V2_8821C 0x7ff
-#define BIT_TAIL_PKT_Q3_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_Q3_V2_8821C) << BIT_SHIFT_TAIL_PKT_Q3_V2_8821C)
-#define BIT_GET_TAIL_PKT_Q3_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2_8821C) & BIT_MASK_TAIL_PKT_Q3_V2_8821C)
-
+#define BIT_TAIL_PKT_Q3_V2_8821C(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q3_V2_8821C) \
+ << BIT_SHIFT_TAIL_PKT_Q3_V2_8821C)
+#define BITS_TAIL_PKT_Q3_V2_8821C \
+ (BIT_MASK_TAIL_PKT_Q3_V2_8821C << BIT_SHIFT_TAIL_PKT_Q3_V2_8821C)
+#define BIT_CLEAR_TAIL_PKT_Q3_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q3_V2_8821C))
+#define BIT_GET_TAIL_PKT_Q3_V2_8821C(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2_8821C) & \
+ BIT_MASK_TAIL_PKT_Q3_V2_8821C)
+#define BIT_SET_TAIL_PKT_Q3_V2_8821C(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q3_V2_8821C(x) | BIT_TAIL_PKT_Q3_V2_8821C(v))
#define BIT_SHIFT_HEAD_PKT_Q3_V1_8821C 0
#define BIT_MASK_HEAD_PKT_Q3_V1_8821C 0x7ff
-#define BIT_HEAD_PKT_Q3_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q3_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q3_V1_8821C)
-#define BIT_GET_HEAD_PKT_Q3_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1_8821C) & BIT_MASK_HEAD_PKT_Q3_V1_8821C)
-
+#define BIT_HEAD_PKT_Q3_V1_8821C(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q3_V1_8821C) \
+ << BIT_SHIFT_HEAD_PKT_Q3_V1_8821C)
+#define BITS_HEAD_PKT_Q3_V1_8821C \
+ (BIT_MASK_HEAD_PKT_Q3_V1_8821C << BIT_SHIFT_HEAD_PKT_Q3_V1_8821C)
+#define BIT_CLEAR_HEAD_PKT_Q3_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q3_V1_8821C))
+#define BIT_GET_HEAD_PKT_Q3_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1_8821C) & \
+ BIT_MASK_HEAD_PKT_Q3_V1_8821C)
+#define BIT_SET_HEAD_PKT_Q3_V1_8821C(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q3_V1_8821C(x) | BIT_HEAD_PKT_Q3_V1_8821C(v))
/* 2 REG_MGQ_INFO_8821C */
#define BIT_SHIFT_QUEUEMACID_MGQ_V1_8821C 25
#define BIT_MASK_QUEUEMACID_MGQ_V1_8821C 0x7f
-#define BIT_QUEUEMACID_MGQ_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_MGQ_V1_8821C) << BIT_SHIFT_QUEUEMACID_MGQ_V1_8821C)
-#define BIT_GET_QUEUEMACID_MGQ_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1_8821C) & BIT_MASK_QUEUEMACID_MGQ_V1_8821C)
-
+#define BIT_QUEUEMACID_MGQ_V1_8821C(x) \
+ (((x) & BIT_MASK_QUEUEMACID_MGQ_V1_8821C) \
+ << BIT_SHIFT_QUEUEMACID_MGQ_V1_8821C)
+#define BITS_QUEUEMACID_MGQ_V1_8821C \
+ (BIT_MASK_QUEUEMACID_MGQ_V1_8821C << BIT_SHIFT_QUEUEMACID_MGQ_V1_8821C)
+#define BIT_CLEAR_QUEUEMACID_MGQ_V1_8821C(x) \
+ ((x) & (~BITS_QUEUEMACID_MGQ_V1_8821C))
+#define BIT_GET_QUEUEMACID_MGQ_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1_8821C) & \
+ BIT_MASK_QUEUEMACID_MGQ_V1_8821C)
+#define BIT_SET_QUEUEMACID_MGQ_V1_8821C(x, v) \
+ (BIT_CLEAR_QUEUEMACID_MGQ_V1_8821C(x) | BIT_QUEUEMACID_MGQ_V1_8821C(v))
#define BIT_SHIFT_QUEUEAC_MGQ_V1_8821C 23
#define BIT_MASK_QUEUEAC_MGQ_V1_8821C 0x3
-#define BIT_QUEUEAC_MGQ_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_MGQ_V1_8821C) << BIT_SHIFT_QUEUEAC_MGQ_V1_8821C)
-#define BIT_GET_QUEUEAC_MGQ_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1_8821C) & BIT_MASK_QUEUEAC_MGQ_V1_8821C)
+#define BIT_QUEUEAC_MGQ_V1_8821C(x) \
+ (((x) & BIT_MASK_QUEUEAC_MGQ_V1_8821C) \
+ << BIT_SHIFT_QUEUEAC_MGQ_V1_8821C)
+#define BITS_QUEUEAC_MGQ_V1_8821C \
+ (BIT_MASK_QUEUEAC_MGQ_V1_8821C << BIT_SHIFT_QUEUEAC_MGQ_V1_8821C)
+#define BIT_CLEAR_QUEUEAC_MGQ_V1_8821C(x) ((x) & (~BITS_QUEUEAC_MGQ_V1_8821C))
+#define BIT_GET_QUEUEAC_MGQ_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1_8821C) & \
+ BIT_MASK_QUEUEAC_MGQ_V1_8821C)
+#define BIT_SET_QUEUEAC_MGQ_V1_8821C(x, v) \
+ (BIT_CLEAR_QUEUEAC_MGQ_V1_8821C(x) | BIT_QUEUEAC_MGQ_V1_8821C(v))
#define BIT_TIDEMPTY_MGQ_V1_8821C BIT(22)
#define BIT_SHIFT_TAIL_PKT_MGQ_V2_8821C 11
#define BIT_MASK_TAIL_PKT_MGQ_V2_8821C 0x7ff
-#define BIT_TAIL_PKT_MGQ_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_MGQ_V2_8821C) << BIT_SHIFT_TAIL_PKT_MGQ_V2_8821C)
-#define BIT_GET_TAIL_PKT_MGQ_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2_8821C) & BIT_MASK_TAIL_PKT_MGQ_V2_8821C)
-
+#define BIT_TAIL_PKT_MGQ_V2_8821C(x) \
+ (((x) & BIT_MASK_TAIL_PKT_MGQ_V2_8821C) \
+ << BIT_SHIFT_TAIL_PKT_MGQ_V2_8821C)
+#define BITS_TAIL_PKT_MGQ_V2_8821C \
+ (BIT_MASK_TAIL_PKT_MGQ_V2_8821C << BIT_SHIFT_TAIL_PKT_MGQ_V2_8821C)
+#define BIT_CLEAR_TAIL_PKT_MGQ_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_MGQ_V2_8821C))
+#define BIT_GET_TAIL_PKT_MGQ_V2_8821C(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2_8821C) & \
+ BIT_MASK_TAIL_PKT_MGQ_V2_8821C)
+#define BIT_SET_TAIL_PKT_MGQ_V2_8821C(x, v) \
+ (BIT_CLEAR_TAIL_PKT_MGQ_V2_8821C(x) | BIT_TAIL_PKT_MGQ_V2_8821C(v))
#define BIT_SHIFT_HEAD_PKT_MGQ_V1_8821C 0
#define BIT_MASK_HEAD_PKT_MGQ_V1_8821C 0x7ff
-#define BIT_HEAD_PKT_MGQ_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_MGQ_V1_8821C) << BIT_SHIFT_HEAD_PKT_MGQ_V1_8821C)
-#define BIT_GET_HEAD_PKT_MGQ_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1_8821C) & BIT_MASK_HEAD_PKT_MGQ_V1_8821C)
-
+#define BIT_HEAD_PKT_MGQ_V1_8821C(x) \
+ (((x) & BIT_MASK_HEAD_PKT_MGQ_V1_8821C) \
+ << BIT_SHIFT_HEAD_PKT_MGQ_V1_8821C)
+#define BITS_HEAD_PKT_MGQ_V1_8821C \
+ (BIT_MASK_HEAD_PKT_MGQ_V1_8821C << BIT_SHIFT_HEAD_PKT_MGQ_V1_8821C)
+#define BIT_CLEAR_HEAD_PKT_MGQ_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_MGQ_V1_8821C))
+#define BIT_GET_HEAD_PKT_MGQ_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1_8821C) & \
+ BIT_MASK_HEAD_PKT_MGQ_V1_8821C)
+#define BIT_SET_HEAD_PKT_MGQ_V1_8821C(x, v) \
+ (BIT_CLEAR_HEAD_PKT_MGQ_V1_8821C(x) | BIT_HEAD_PKT_MGQ_V1_8821C(v))
/* 2 REG_HIQ_INFO_8821C */
#define BIT_SHIFT_QUEUEMACID_HIQ_V1_8821C 25
#define BIT_MASK_QUEUEMACID_HIQ_V1_8821C 0x7f
-#define BIT_QUEUEMACID_HIQ_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_HIQ_V1_8821C) << BIT_SHIFT_QUEUEMACID_HIQ_V1_8821C)
-#define BIT_GET_QUEUEMACID_HIQ_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1_8821C) & BIT_MASK_QUEUEMACID_HIQ_V1_8821C)
-
+#define BIT_QUEUEMACID_HIQ_V1_8821C(x) \
+ (((x) & BIT_MASK_QUEUEMACID_HIQ_V1_8821C) \
+ << BIT_SHIFT_QUEUEMACID_HIQ_V1_8821C)
+#define BITS_QUEUEMACID_HIQ_V1_8821C \
+ (BIT_MASK_QUEUEMACID_HIQ_V1_8821C << BIT_SHIFT_QUEUEMACID_HIQ_V1_8821C)
+#define BIT_CLEAR_QUEUEMACID_HIQ_V1_8821C(x) \
+ ((x) & (~BITS_QUEUEMACID_HIQ_V1_8821C))
+#define BIT_GET_QUEUEMACID_HIQ_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1_8821C) & \
+ BIT_MASK_QUEUEMACID_HIQ_V1_8821C)
+#define BIT_SET_QUEUEMACID_HIQ_V1_8821C(x, v) \
+ (BIT_CLEAR_QUEUEMACID_HIQ_V1_8821C(x) | BIT_QUEUEMACID_HIQ_V1_8821C(v))
#define BIT_SHIFT_QUEUEAC_HIQ_V1_8821C 23
#define BIT_MASK_QUEUEAC_HIQ_V1_8821C 0x3
-#define BIT_QUEUEAC_HIQ_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_HIQ_V1_8821C) << BIT_SHIFT_QUEUEAC_HIQ_V1_8821C)
-#define BIT_GET_QUEUEAC_HIQ_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1_8821C) & BIT_MASK_QUEUEAC_HIQ_V1_8821C)
+#define BIT_QUEUEAC_HIQ_V1_8821C(x) \
+ (((x) & BIT_MASK_QUEUEAC_HIQ_V1_8821C) \
+ << BIT_SHIFT_QUEUEAC_HIQ_V1_8821C)
+#define BITS_QUEUEAC_HIQ_V1_8821C \
+ (BIT_MASK_QUEUEAC_HIQ_V1_8821C << BIT_SHIFT_QUEUEAC_HIQ_V1_8821C)
+#define BIT_CLEAR_QUEUEAC_HIQ_V1_8821C(x) ((x) & (~BITS_QUEUEAC_HIQ_V1_8821C))
+#define BIT_GET_QUEUEAC_HIQ_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1_8821C) & \
+ BIT_MASK_QUEUEAC_HIQ_V1_8821C)
+#define BIT_SET_QUEUEAC_HIQ_V1_8821C(x, v) \
+ (BIT_CLEAR_QUEUEAC_HIQ_V1_8821C(x) | BIT_QUEUEAC_HIQ_V1_8821C(v))
#define BIT_TIDEMPTY_HIQ_V1_8821C BIT(22)
#define BIT_SHIFT_TAIL_PKT_HIQ_V2_8821C 11
#define BIT_MASK_TAIL_PKT_HIQ_V2_8821C 0x7ff
-#define BIT_TAIL_PKT_HIQ_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_HIQ_V2_8821C) << BIT_SHIFT_TAIL_PKT_HIQ_V2_8821C)
-#define BIT_GET_TAIL_PKT_HIQ_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2_8821C) & BIT_MASK_TAIL_PKT_HIQ_V2_8821C)
-
+#define BIT_TAIL_PKT_HIQ_V2_8821C(x) \
+ (((x) & BIT_MASK_TAIL_PKT_HIQ_V2_8821C) \
+ << BIT_SHIFT_TAIL_PKT_HIQ_V2_8821C)
+#define BITS_TAIL_PKT_HIQ_V2_8821C \
+ (BIT_MASK_TAIL_PKT_HIQ_V2_8821C << BIT_SHIFT_TAIL_PKT_HIQ_V2_8821C)
+#define BIT_CLEAR_TAIL_PKT_HIQ_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_HIQ_V2_8821C))
+#define BIT_GET_TAIL_PKT_HIQ_V2_8821C(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2_8821C) & \
+ BIT_MASK_TAIL_PKT_HIQ_V2_8821C)
+#define BIT_SET_TAIL_PKT_HIQ_V2_8821C(x, v) \
+ (BIT_CLEAR_TAIL_PKT_HIQ_V2_8821C(x) | BIT_TAIL_PKT_HIQ_V2_8821C(v))
#define BIT_SHIFT_HEAD_PKT_HIQ_V1_8821C 0
#define BIT_MASK_HEAD_PKT_HIQ_V1_8821C 0x7ff
-#define BIT_HEAD_PKT_HIQ_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_HIQ_V1_8821C) << BIT_SHIFT_HEAD_PKT_HIQ_V1_8821C)
-#define BIT_GET_HEAD_PKT_HIQ_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1_8821C) & BIT_MASK_HEAD_PKT_HIQ_V1_8821C)
-
+#define BIT_HEAD_PKT_HIQ_V1_8821C(x) \
+ (((x) & BIT_MASK_HEAD_PKT_HIQ_V1_8821C) \
+ << BIT_SHIFT_HEAD_PKT_HIQ_V1_8821C)
+#define BITS_HEAD_PKT_HIQ_V1_8821C \
+ (BIT_MASK_HEAD_PKT_HIQ_V1_8821C << BIT_SHIFT_HEAD_PKT_HIQ_V1_8821C)
+#define BIT_CLEAR_HEAD_PKT_HIQ_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_HIQ_V1_8821C))
+#define BIT_GET_HEAD_PKT_HIQ_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1_8821C) & \
+ BIT_MASK_HEAD_PKT_HIQ_V1_8821C)
+#define BIT_SET_HEAD_PKT_HIQ_V1_8821C(x, v) \
+ (BIT_CLEAR_HEAD_PKT_HIQ_V1_8821C(x) | BIT_HEAD_PKT_HIQ_V1_8821C(v))
/* 2 REG_BCNQ_INFO_8821C */
#define BIT_SHIFT_BCNQ_HEAD_PG_V1_8821C 0
#define BIT_MASK_BCNQ_HEAD_PG_V1_8821C 0xfff
-#define BIT_BCNQ_HEAD_PG_V1_8821C(x) (((x) & BIT_MASK_BCNQ_HEAD_PG_V1_8821C) << BIT_SHIFT_BCNQ_HEAD_PG_V1_8821C)
-#define BIT_GET_BCNQ_HEAD_PG_V1_8821C(x) (((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1_8821C) & BIT_MASK_BCNQ_HEAD_PG_V1_8821C)
-
+#define BIT_BCNQ_HEAD_PG_V1_8821C(x) \
+ (((x) & BIT_MASK_BCNQ_HEAD_PG_V1_8821C) \
+ << BIT_SHIFT_BCNQ_HEAD_PG_V1_8821C)
+#define BITS_BCNQ_HEAD_PG_V1_8821C \
+ (BIT_MASK_BCNQ_HEAD_PG_V1_8821C << BIT_SHIFT_BCNQ_HEAD_PG_V1_8821C)
+#define BIT_CLEAR_BCNQ_HEAD_PG_V1_8821C(x) ((x) & (~BITS_BCNQ_HEAD_PG_V1_8821C))
+#define BIT_GET_BCNQ_HEAD_PG_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1_8821C) & \
+ BIT_MASK_BCNQ_HEAD_PG_V1_8821C)
+#define BIT_SET_BCNQ_HEAD_PG_V1_8821C(x, v) \
+ (BIT_CLEAR_BCNQ_HEAD_PG_V1_8821C(x) | BIT_BCNQ_HEAD_PG_V1_8821C(v))
/* 2 REG_TXPKT_EMPTY_8821C */
#define BIT_BCNQ_EMPTY_8821C BIT(11)
@@ -4949,9 +9087,17 @@
#define BIT_SHIFT_FW_FREE_TAIL_V1_8821C 0
#define BIT_MASK_FW_FREE_TAIL_V1_8821C 0xfff
-#define BIT_FW_FREE_TAIL_V1_8821C(x) (((x) & BIT_MASK_FW_FREE_TAIL_V1_8821C) << BIT_SHIFT_FW_FREE_TAIL_V1_8821C)
-#define BIT_GET_FW_FREE_TAIL_V1_8821C(x) (((x) >> BIT_SHIFT_FW_FREE_TAIL_V1_8821C) & BIT_MASK_FW_FREE_TAIL_V1_8821C)
-
+#define BIT_FW_FREE_TAIL_V1_8821C(x) \
+ (((x) & BIT_MASK_FW_FREE_TAIL_V1_8821C) \
+ << BIT_SHIFT_FW_FREE_TAIL_V1_8821C)
+#define BITS_FW_FREE_TAIL_V1_8821C \
+ (BIT_MASK_FW_FREE_TAIL_V1_8821C << BIT_SHIFT_FW_FREE_TAIL_V1_8821C)
+#define BIT_CLEAR_FW_FREE_TAIL_V1_8821C(x) ((x) & (~BITS_FW_FREE_TAIL_V1_8821C))
+#define BIT_GET_FW_FREE_TAIL_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_FW_FREE_TAIL_V1_8821C) & \
+ BIT_MASK_FW_FREE_TAIL_V1_8821C)
+#define BIT_SET_FW_FREE_TAIL_V1_8821C(x, v) \
+ (BIT_CLEAR_FW_FREE_TAIL_V1_8821C(x) | BIT_FW_FREE_TAIL_V1_8821C(v))
/* 2 REG_FWHW_TXQ_CTRL_8821C */
#define BIT_RTS_LIMIT_IN_OFDM_8821C BIT(23)
@@ -4961,8 +9107,15 @@
#define BIT_SHIFT_EN_QUEUE_RPT_8821C 8
#define BIT_MASK_EN_QUEUE_RPT_8821C 0xff
-#define BIT_EN_QUEUE_RPT_8821C(x) (((x) & BIT_MASK_EN_QUEUE_RPT_8821C) << BIT_SHIFT_EN_QUEUE_RPT_8821C)
-#define BIT_GET_EN_QUEUE_RPT_8821C(x) (((x) >> BIT_SHIFT_EN_QUEUE_RPT_8821C) & BIT_MASK_EN_QUEUE_RPT_8821C)
+#define BIT_EN_QUEUE_RPT_8821C(x) \
+ (((x) & BIT_MASK_EN_QUEUE_RPT_8821C) << BIT_SHIFT_EN_QUEUE_RPT_8821C)
+#define BITS_EN_QUEUE_RPT_8821C \
+ (BIT_MASK_EN_QUEUE_RPT_8821C << BIT_SHIFT_EN_QUEUE_RPT_8821C)
+#define BIT_CLEAR_EN_QUEUE_RPT_8821C(x) ((x) & (~BITS_EN_QUEUE_RPT_8821C))
+#define BIT_GET_EN_QUEUE_RPT_8821C(x) \
+ (((x) >> BIT_SHIFT_EN_QUEUE_RPT_8821C) & BIT_MASK_EN_QUEUE_RPT_8821C)
+#define BIT_SET_EN_QUEUE_RPT_8821C(x, v) \
+ (BIT_CLEAR_EN_QUEUE_RPT_8821C(x) | BIT_EN_QUEUE_RPT_8821C(v))
#define BIT_EN_RTY_BK_8821C BIT(7)
#define BIT_EN_USE_INI_RAT_8821C BIT(6)
@@ -4970,25 +9123,45 @@
#define BIT_DIS_SSN_CHECK_8821C BIT(4)
#define BIT_MACID_MATCH_RTS_8821C BIT(3)
#define BIT_EN_BCN_TRXRPT_V1_8821C BIT(2)
-#define BIT_R_EN_FTMRPT_8821C BIT(1)
+#define BIT_R_EN_FTMRPT_V1_8821C BIT(1)
#define BIT_R_BMC_NAV_PROTECT_8821C BIT(0)
/* 2 REG_DATAFB_SEL_8821C */
-#define BIT__R_EN_RTY_BK_COD_8821C BIT(2)
+#define BIT_BROADCAST_RTY_EN_8821C BIT(3)
+#define BIT_EN_RTY_BK_COD_8821C BIT(2)
#define BIT_SHIFT__R_DATA_FALLBACK_SEL_8821C 0
#define BIT_MASK__R_DATA_FALLBACK_SEL_8821C 0x3
-#define BIT__R_DATA_FALLBACK_SEL_8821C(x) (((x) & BIT_MASK__R_DATA_FALLBACK_SEL_8821C) << BIT_SHIFT__R_DATA_FALLBACK_SEL_8821C)
-#define BIT_GET__R_DATA_FALLBACK_SEL_8821C(x) (((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL_8821C) & BIT_MASK__R_DATA_FALLBACK_SEL_8821C)
-
+#define BIT__R_DATA_FALLBACK_SEL_8821C(x) \
+ (((x) & BIT_MASK__R_DATA_FALLBACK_SEL_8821C) \
+ << BIT_SHIFT__R_DATA_FALLBACK_SEL_8821C)
+#define BITS__R_DATA_FALLBACK_SEL_8821C \
+ (BIT_MASK__R_DATA_FALLBACK_SEL_8821C \
+ << BIT_SHIFT__R_DATA_FALLBACK_SEL_8821C)
+#define BIT_CLEAR__R_DATA_FALLBACK_SEL_8821C(x) \
+ ((x) & (~BITS__R_DATA_FALLBACK_SEL_8821C))
+#define BIT_GET__R_DATA_FALLBACK_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL_8821C) & \
+ BIT_MASK__R_DATA_FALLBACK_SEL_8821C)
+#define BIT_SET__R_DATA_FALLBACK_SEL_8821C(x, v) \
+ (BIT_CLEAR__R_DATA_FALLBACK_SEL_8821C(x) | \
+ BIT__R_DATA_FALLBACK_SEL_8821C(v))
/* 2 REG_BCNQ_BDNY_V1_8821C */
#define BIT_SHIFT_BCNQ_PGBNDY_V1_8821C 0
#define BIT_MASK_BCNQ_PGBNDY_V1_8821C 0xfff
-#define BIT_BCNQ_PGBNDY_V1_8821C(x) (((x) & BIT_MASK_BCNQ_PGBNDY_V1_8821C) << BIT_SHIFT_BCNQ_PGBNDY_V1_8821C)
-#define BIT_GET_BCNQ_PGBNDY_V1_8821C(x) (((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1_8821C) & BIT_MASK_BCNQ_PGBNDY_V1_8821C)
-
+#define BIT_BCNQ_PGBNDY_V1_8821C(x) \
+ (((x) & BIT_MASK_BCNQ_PGBNDY_V1_8821C) \
+ << BIT_SHIFT_BCNQ_PGBNDY_V1_8821C)
+#define BITS_BCNQ_PGBNDY_V1_8821C \
+ (BIT_MASK_BCNQ_PGBNDY_V1_8821C << BIT_SHIFT_BCNQ_PGBNDY_V1_8821C)
+#define BIT_CLEAR_BCNQ_PGBNDY_V1_8821C(x) ((x) & (~BITS_BCNQ_PGBNDY_V1_8821C))
+#define BIT_GET_BCNQ_PGBNDY_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1_8821C) & \
+ BIT_MASK_BCNQ_PGBNDY_V1_8821C)
+#define BIT_SET_BCNQ_PGBNDY_V1_8821C(x, v) \
+ (BIT_CLEAR_BCNQ_PGBNDY_V1_8821C(x) | BIT_BCNQ_PGBNDY_V1_8821C(v))
/* 2 REG_LIFETIME_EN_8821C */
#define BIT_BT_INT_CPU_8821C BIT(7)
@@ -5005,29 +9178,55 @@
#define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8821C 8
#define BIT_MASK_SPEC_SIFS_OFDM_PTCL_8821C 0xff
-#define BIT_SPEC_SIFS_OFDM_PTCL_8821C(x) (((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8821C) << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8821C)
-#define BIT_GET_SPEC_SIFS_OFDM_PTCL_8821C(x) (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8821C) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8821C)
-
+#define BIT_SPEC_SIFS_OFDM_PTCL_8821C(x) \
+ (((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8821C) \
+ << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8821C)
+#define BITS_SPEC_SIFS_OFDM_PTCL_8821C \
+ (BIT_MASK_SPEC_SIFS_OFDM_PTCL_8821C \
+ << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8821C)
+#define BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8821C(x) \
+ ((x) & (~BITS_SPEC_SIFS_OFDM_PTCL_8821C))
+#define BIT_GET_SPEC_SIFS_OFDM_PTCL_8821C(x) \
+ (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8821C) & \
+ BIT_MASK_SPEC_SIFS_OFDM_PTCL_8821C)
+#define BIT_SET_SPEC_SIFS_OFDM_PTCL_8821C(x, v) \
+ (BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8821C(x) | \
+ BIT_SPEC_SIFS_OFDM_PTCL_8821C(v))
#define BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8821C 0
#define BIT_MASK_SPEC_SIFS_CCK_PTCL_8821C 0xff
-#define BIT_SPEC_SIFS_CCK_PTCL_8821C(x) (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8821C) << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8821C)
-#define BIT_GET_SPEC_SIFS_CCK_PTCL_8821C(x) (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8821C) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8821C)
-
+#define BIT_SPEC_SIFS_CCK_PTCL_8821C(x) \
+ (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8821C) \
+ << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8821C)
+#define BITS_SPEC_SIFS_CCK_PTCL_8821C \
+ (BIT_MASK_SPEC_SIFS_CCK_PTCL_8821C \
+ << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8821C)
+#define BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8821C(x) \
+ ((x) & (~BITS_SPEC_SIFS_CCK_PTCL_8821C))
+#define BIT_GET_SPEC_SIFS_CCK_PTCL_8821C(x) \
+ (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8821C) & \
+ BIT_MASK_SPEC_SIFS_CCK_PTCL_8821C)
+#define BIT_SET_SPEC_SIFS_CCK_PTCL_8821C(x, v) \
+ (BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8821C(x) | \
+ BIT_SPEC_SIFS_CCK_PTCL_8821C(v))
/* 2 REG_RETRY_LIMIT_8821C */
#define BIT_SHIFT_SRL_8821C 8
#define BIT_MASK_SRL_8821C 0x3f
#define BIT_SRL_8821C(x) (((x) & BIT_MASK_SRL_8821C) << BIT_SHIFT_SRL_8821C)
+#define BITS_SRL_8821C (BIT_MASK_SRL_8821C << BIT_SHIFT_SRL_8821C)
+#define BIT_CLEAR_SRL_8821C(x) ((x) & (~BITS_SRL_8821C))
#define BIT_GET_SRL_8821C(x) (((x) >> BIT_SHIFT_SRL_8821C) & BIT_MASK_SRL_8821C)
-
+#define BIT_SET_SRL_8821C(x, v) (BIT_CLEAR_SRL_8821C(x) | BIT_SRL_8821C(v))
#define BIT_SHIFT_LRL_8821C 0
#define BIT_MASK_LRL_8821C 0x3f
#define BIT_LRL_8821C(x) (((x) & BIT_MASK_LRL_8821C) << BIT_SHIFT_LRL_8821C)
+#define BITS_LRL_8821C (BIT_MASK_LRL_8821C << BIT_SHIFT_LRL_8821C)
+#define BIT_CLEAR_LRL_8821C(x) ((x) & (~BITS_LRL_8821C))
#define BIT_GET_LRL_8821C(x) (((x) >> BIT_SHIFT_LRL_8821C) & BIT_MASK_LRL_8821C)
-
+#define BIT_SET_LRL_8821C(x, v) (BIT_CLEAR_LRL_8821C(x) | BIT_LRL_8821C(v))
/* 2 REG_TXBF_CTRL_8821C */
#define BIT_R_ENABLE_NDPA_8821C BIT(31)
@@ -5040,8 +9239,15 @@
#define BIT_SHIFT_R_TXBF1_AID_8821C 16
#define BIT_MASK_R_TXBF1_AID_8821C 0x1ff
-#define BIT_R_TXBF1_AID_8821C(x) (((x) & BIT_MASK_R_TXBF1_AID_8821C) << BIT_SHIFT_R_TXBF1_AID_8821C)
-#define BIT_GET_R_TXBF1_AID_8821C(x) (((x) >> BIT_SHIFT_R_TXBF1_AID_8821C) & BIT_MASK_R_TXBF1_AID_8821C)
+#define BIT_R_TXBF1_AID_8821C(x) \
+ (((x) & BIT_MASK_R_TXBF1_AID_8821C) << BIT_SHIFT_R_TXBF1_AID_8821C)
+#define BITS_R_TXBF1_AID_8821C \
+ (BIT_MASK_R_TXBF1_AID_8821C << BIT_SHIFT_R_TXBF1_AID_8821C)
+#define BIT_CLEAR_R_TXBF1_AID_8821C(x) ((x) & (~BITS_R_TXBF1_AID_8821C))
+#define BIT_GET_R_TXBF1_AID_8821C(x) \
+ (((x) >> BIT_SHIFT_R_TXBF1_AID_8821C) & BIT_MASK_R_TXBF1_AID_8821C)
+#define BIT_SET_R_TXBF1_AID_8821C(x, v) \
+ (BIT_CLEAR_R_TXBF1_AID_8821C(x) | BIT_R_TXBF1_AID_8821C(v))
#define BIT_DIS_NDP_BFEN_8821C BIT(15)
#define BIT_R_TXBCN_NOBLOCK_NDP_8821C BIT(14)
@@ -5051,140 +9257,295 @@
#define BIT_SHIFT_R_TXBF0_AID_8821C 0
#define BIT_MASK_R_TXBF0_AID_8821C 0x1ff
-#define BIT_R_TXBF0_AID_8821C(x) (((x) & BIT_MASK_R_TXBF0_AID_8821C) << BIT_SHIFT_R_TXBF0_AID_8821C)
-#define BIT_GET_R_TXBF0_AID_8821C(x) (((x) >> BIT_SHIFT_R_TXBF0_AID_8821C) & BIT_MASK_R_TXBF0_AID_8821C)
-
+#define BIT_R_TXBF0_AID_8821C(x) \
+ (((x) & BIT_MASK_R_TXBF0_AID_8821C) << BIT_SHIFT_R_TXBF0_AID_8821C)
+#define BITS_R_TXBF0_AID_8821C \
+ (BIT_MASK_R_TXBF0_AID_8821C << BIT_SHIFT_R_TXBF0_AID_8821C)
+#define BIT_CLEAR_R_TXBF0_AID_8821C(x) ((x) & (~BITS_R_TXBF0_AID_8821C))
+#define BIT_GET_R_TXBF0_AID_8821C(x) \
+ (((x) >> BIT_SHIFT_R_TXBF0_AID_8821C) & BIT_MASK_R_TXBF0_AID_8821C)
+#define BIT_SET_R_TXBF0_AID_8821C(x, v) \
+ (BIT_CLEAR_R_TXBF0_AID_8821C(x) | BIT_R_TXBF0_AID_8821C(v))
/* 2 REG_DARFRC_8821C */
-#define BIT_SHIFT_DARF_RC8_8821C (56 & CPU_OPT_WIDTH)
-#define BIT_MASK_DARF_RC8_8821C 0x1f
-#define BIT_DARF_RC8_8821C(x) (((x) & BIT_MASK_DARF_RC8_8821C) << BIT_SHIFT_DARF_RC8_8821C)
-#define BIT_GET_DARF_RC8_8821C(x) (((x) >> BIT_SHIFT_DARF_RC8_8821C) & BIT_MASK_DARF_RC8_8821C)
-
-
-#define BIT_SHIFT_DARF_RC7_8821C (48 & CPU_OPT_WIDTH)
-#define BIT_MASK_DARF_RC7_8821C 0x1f
-#define BIT_DARF_RC7_8821C(x) (((x) & BIT_MASK_DARF_RC7_8821C) << BIT_SHIFT_DARF_RC7_8821C)
-#define BIT_GET_DARF_RC7_8821C(x) (((x) >> BIT_SHIFT_DARF_RC7_8821C) & BIT_MASK_DARF_RC7_8821C)
-
-
-#define BIT_SHIFT_DARF_RC6_8821C (40 & CPU_OPT_WIDTH)
-#define BIT_MASK_DARF_RC6_8821C 0x1f
-#define BIT_DARF_RC6_8821C(x) (((x) & BIT_MASK_DARF_RC6_8821C) << BIT_SHIFT_DARF_RC6_8821C)
-#define BIT_GET_DARF_RC6_8821C(x) (((x) >> BIT_SHIFT_DARF_RC6_8821C) & BIT_MASK_DARF_RC6_8821C)
-
-
-#define BIT_SHIFT_DARF_RC5_8821C (32 & CPU_OPT_WIDTH)
-#define BIT_MASK_DARF_RC5_8821C 0x1f
-#define BIT_DARF_RC5_8821C(x) (((x) & BIT_MASK_DARF_RC5_8821C) << BIT_SHIFT_DARF_RC5_8821C)
-#define BIT_GET_DARF_RC5_8821C(x) (((x) >> BIT_SHIFT_DARF_RC5_8821C) & BIT_MASK_DARF_RC5_8821C)
-
-
#define BIT_SHIFT_DARF_RC4_8821C 24
#define BIT_MASK_DARF_RC4_8821C 0x1f
-#define BIT_DARF_RC4_8821C(x) (((x) & BIT_MASK_DARF_RC4_8821C) << BIT_SHIFT_DARF_RC4_8821C)
-#define BIT_GET_DARF_RC4_8821C(x) (((x) >> BIT_SHIFT_DARF_RC4_8821C) & BIT_MASK_DARF_RC4_8821C)
-
+#define BIT_DARF_RC4_8821C(x) \
+ (((x) & BIT_MASK_DARF_RC4_8821C) << BIT_SHIFT_DARF_RC4_8821C)
+#define BITS_DARF_RC4_8821C \
+ (BIT_MASK_DARF_RC4_8821C << BIT_SHIFT_DARF_RC4_8821C)
+#define BIT_CLEAR_DARF_RC4_8821C(x) ((x) & (~BITS_DARF_RC4_8821C))
+#define BIT_GET_DARF_RC4_8821C(x) \
+ (((x) >> BIT_SHIFT_DARF_RC4_8821C) & BIT_MASK_DARF_RC4_8821C)
+#define BIT_SET_DARF_RC4_8821C(x, v) \
+ (BIT_CLEAR_DARF_RC4_8821C(x) | BIT_DARF_RC4_8821C(v))
#define BIT_SHIFT_DARF_RC3_8821C 16
#define BIT_MASK_DARF_RC3_8821C 0x1f
-#define BIT_DARF_RC3_8821C(x) (((x) & BIT_MASK_DARF_RC3_8821C) << BIT_SHIFT_DARF_RC3_8821C)
-#define BIT_GET_DARF_RC3_8821C(x) (((x) >> BIT_SHIFT_DARF_RC3_8821C) & BIT_MASK_DARF_RC3_8821C)
-
+#define BIT_DARF_RC3_8821C(x) \
+ (((x) & BIT_MASK_DARF_RC3_8821C) << BIT_SHIFT_DARF_RC3_8821C)
+#define BITS_DARF_RC3_8821C \
+ (BIT_MASK_DARF_RC3_8821C << BIT_SHIFT_DARF_RC3_8821C)
+#define BIT_CLEAR_DARF_RC3_8821C(x) ((x) & (~BITS_DARF_RC3_8821C))
+#define BIT_GET_DARF_RC3_8821C(x) \
+ (((x) >> BIT_SHIFT_DARF_RC3_8821C) & BIT_MASK_DARF_RC3_8821C)
+#define BIT_SET_DARF_RC3_8821C(x, v) \
+ (BIT_CLEAR_DARF_RC3_8821C(x) | BIT_DARF_RC3_8821C(v))
#define BIT_SHIFT_DARF_RC2_8821C 8
#define BIT_MASK_DARF_RC2_8821C 0x1f
-#define BIT_DARF_RC2_8821C(x) (((x) & BIT_MASK_DARF_RC2_8821C) << BIT_SHIFT_DARF_RC2_8821C)
-#define BIT_GET_DARF_RC2_8821C(x) (((x) >> BIT_SHIFT_DARF_RC2_8821C) & BIT_MASK_DARF_RC2_8821C)
-
+#define BIT_DARF_RC2_8821C(x) \
+ (((x) & BIT_MASK_DARF_RC2_8821C) << BIT_SHIFT_DARF_RC2_8821C)
+#define BITS_DARF_RC2_8821C \
+ (BIT_MASK_DARF_RC2_8821C << BIT_SHIFT_DARF_RC2_8821C)
+#define BIT_CLEAR_DARF_RC2_8821C(x) ((x) & (~BITS_DARF_RC2_8821C))
+#define BIT_GET_DARF_RC2_8821C(x) \
+ (((x) >> BIT_SHIFT_DARF_RC2_8821C) & BIT_MASK_DARF_RC2_8821C)
+#define BIT_SET_DARF_RC2_8821C(x, v) \
+ (BIT_CLEAR_DARF_RC2_8821C(x) | BIT_DARF_RC2_8821C(v))
#define BIT_SHIFT_DARF_RC1_8821C 0
#define BIT_MASK_DARF_RC1_8821C 0x1f
-#define BIT_DARF_RC1_8821C(x) (((x) & BIT_MASK_DARF_RC1_8821C) << BIT_SHIFT_DARF_RC1_8821C)
-#define BIT_GET_DARF_RC1_8821C(x) (((x) >> BIT_SHIFT_DARF_RC1_8821C) & BIT_MASK_DARF_RC1_8821C)
-
+#define BIT_DARF_RC1_8821C(x) \
+ (((x) & BIT_MASK_DARF_RC1_8821C) << BIT_SHIFT_DARF_RC1_8821C)
+#define BITS_DARF_RC1_8821C \
+ (BIT_MASK_DARF_RC1_8821C << BIT_SHIFT_DARF_RC1_8821C)
+#define BIT_CLEAR_DARF_RC1_8821C(x) ((x) & (~BITS_DARF_RC1_8821C))
+#define BIT_GET_DARF_RC1_8821C(x) \
+ (((x) >> BIT_SHIFT_DARF_RC1_8821C) & BIT_MASK_DARF_RC1_8821C)
+#define BIT_SET_DARF_RC1_8821C(x, v) \
+ (BIT_CLEAR_DARF_RC1_8821C(x) | BIT_DARF_RC1_8821C(v))
+
+/* 2 REG_DARFRCH_8821C */
+
+#define BIT_SHIFT_DARF_RC8_V1_8821C 24
+#define BIT_MASK_DARF_RC8_V1_8821C 0x1f
+#define BIT_DARF_RC8_V1_8821C(x) \
+ (((x) & BIT_MASK_DARF_RC8_V1_8821C) << BIT_SHIFT_DARF_RC8_V1_8821C)
+#define BITS_DARF_RC8_V1_8821C \
+ (BIT_MASK_DARF_RC8_V1_8821C << BIT_SHIFT_DARF_RC8_V1_8821C)
+#define BIT_CLEAR_DARF_RC8_V1_8821C(x) ((x) & (~BITS_DARF_RC8_V1_8821C))
+#define BIT_GET_DARF_RC8_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_DARF_RC8_V1_8821C) & BIT_MASK_DARF_RC8_V1_8821C)
+#define BIT_SET_DARF_RC8_V1_8821C(x, v) \
+ (BIT_CLEAR_DARF_RC8_V1_8821C(x) | BIT_DARF_RC8_V1_8821C(v))
+
+#define BIT_SHIFT_DARF_RC7_V1_8821C 16
+#define BIT_MASK_DARF_RC7_V1_8821C 0x1f
+#define BIT_DARF_RC7_V1_8821C(x) \
+ (((x) & BIT_MASK_DARF_RC7_V1_8821C) << BIT_SHIFT_DARF_RC7_V1_8821C)
+#define BITS_DARF_RC7_V1_8821C \
+ (BIT_MASK_DARF_RC7_V1_8821C << BIT_SHIFT_DARF_RC7_V1_8821C)
+#define BIT_CLEAR_DARF_RC7_V1_8821C(x) ((x) & (~BITS_DARF_RC7_V1_8821C))
+#define BIT_GET_DARF_RC7_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_DARF_RC7_V1_8821C) & BIT_MASK_DARF_RC7_V1_8821C)
+#define BIT_SET_DARF_RC7_V1_8821C(x, v) \
+ (BIT_CLEAR_DARF_RC7_V1_8821C(x) | BIT_DARF_RC7_V1_8821C(v))
+
+#define BIT_SHIFT_DARF_RC6_V1_8821C 8
+#define BIT_MASK_DARF_RC6_V1_8821C 0x1f
+#define BIT_DARF_RC6_V1_8821C(x) \
+ (((x) & BIT_MASK_DARF_RC6_V1_8821C) << BIT_SHIFT_DARF_RC6_V1_8821C)
+#define BITS_DARF_RC6_V1_8821C \
+ (BIT_MASK_DARF_RC6_V1_8821C << BIT_SHIFT_DARF_RC6_V1_8821C)
+#define BIT_CLEAR_DARF_RC6_V1_8821C(x) ((x) & (~BITS_DARF_RC6_V1_8821C))
+#define BIT_GET_DARF_RC6_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_DARF_RC6_V1_8821C) & BIT_MASK_DARF_RC6_V1_8821C)
+#define BIT_SET_DARF_RC6_V1_8821C(x, v) \
+ (BIT_CLEAR_DARF_RC6_V1_8821C(x) | BIT_DARF_RC6_V1_8821C(v))
+
+#define BIT_SHIFT_DARF_RC5_V1_8821C 0
+#define BIT_MASK_DARF_RC5_V1_8821C 0x1f
+#define BIT_DARF_RC5_V1_8821C(x) \
+ (((x) & BIT_MASK_DARF_RC5_V1_8821C) << BIT_SHIFT_DARF_RC5_V1_8821C)
+#define BITS_DARF_RC5_V1_8821C \
+ (BIT_MASK_DARF_RC5_V1_8821C << BIT_SHIFT_DARF_RC5_V1_8821C)
+#define BIT_CLEAR_DARF_RC5_V1_8821C(x) ((x) & (~BITS_DARF_RC5_V1_8821C))
+#define BIT_GET_DARF_RC5_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_DARF_RC5_V1_8821C) & BIT_MASK_DARF_RC5_V1_8821C)
+#define BIT_SET_DARF_RC5_V1_8821C(x, v) \
+ (BIT_CLEAR_DARF_RC5_V1_8821C(x) | BIT_DARF_RC5_V1_8821C(v))
/* 2 REG_RARFRC_8821C */
-#define BIT_SHIFT_RARF_RC8_8821C (56 & CPU_OPT_WIDTH)
-#define BIT_MASK_RARF_RC8_8821C 0x1f
-#define BIT_RARF_RC8_8821C(x) (((x) & BIT_MASK_RARF_RC8_8821C) << BIT_SHIFT_RARF_RC8_8821C)
-#define BIT_GET_RARF_RC8_8821C(x) (((x) >> BIT_SHIFT_RARF_RC8_8821C) & BIT_MASK_RARF_RC8_8821C)
-
-
-#define BIT_SHIFT_RARF_RC7_8821C (48 & CPU_OPT_WIDTH)
-#define BIT_MASK_RARF_RC7_8821C 0x1f
-#define BIT_RARF_RC7_8821C(x) (((x) & BIT_MASK_RARF_RC7_8821C) << BIT_SHIFT_RARF_RC7_8821C)
-#define BIT_GET_RARF_RC7_8821C(x) (((x) >> BIT_SHIFT_RARF_RC7_8821C) & BIT_MASK_RARF_RC7_8821C)
-
-
-#define BIT_SHIFT_RARF_RC6_8821C (40 & CPU_OPT_WIDTH)
-#define BIT_MASK_RARF_RC6_8821C 0x1f
-#define BIT_RARF_RC6_8821C(x) (((x) & BIT_MASK_RARF_RC6_8821C) << BIT_SHIFT_RARF_RC6_8821C)
-#define BIT_GET_RARF_RC6_8821C(x) (((x) >> BIT_SHIFT_RARF_RC6_8821C) & BIT_MASK_RARF_RC6_8821C)
-
-
-#define BIT_SHIFT_RARF_RC5_8821C (32 & CPU_OPT_WIDTH)
-#define BIT_MASK_RARF_RC5_8821C 0x1f
-#define BIT_RARF_RC5_8821C(x) (((x) & BIT_MASK_RARF_RC5_8821C) << BIT_SHIFT_RARF_RC5_8821C)
-#define BIT_GET_RARF_RC5_8821C(x) (((x) >> BIT_SHIFT_RARF_RC5_8821C) & BIT_MASK_RARF_RC5_8821C)
-
-
#define BIT_SHIFT_RARF_RC4_8821C 24
#define BIT_MASK_RARF_RC4_8821C 0x1f
-#define BIT_RARF_RC4_8821C(x) (((x) & BIT_MASK_RARF_RC4_8821C) << BIT_SHIFT_RARF_RC4_8821C)
-#define BIT_GET_RARF_RC4_8821C(x) (((x) >> BIT_SHIFT_RARF_RC4_8821C) & BIT_MASK_RARF_RC4_8821C)
-
+#define BIT_RARF_RC4_8821C(x) \
+ (((x) & BIT_MASK_RARF_RC4_8821C) << BIT_SHIFT_RARF_RC4_8821C)
+#define BITS_RARF_RC4_8821C \
+ (BIT_MASK_RARF_RC4_8821C << BIT_SHIFT_RARF_RC4_8821C)
+#define BIT_CLEAR_RARF_RC4_8821C(x) ((x) & (~BITS_RARF_RC4_8821C))
+#define BIT_GET_RARF_RC4_8821C(x) \
+ (((x) >> BIT_SHIFT_RARF_RC4_8821C) & BIT_MASK_RARF_RC4_8821C)
+#define BIT_SET_RARF_RC4_8821C(x, v) \
+ (BIT_CLEAR_RARF_RC4_8821C(x) | BIT_RARF_RC4_8821C(v))
#define BIT_SHIFT_RARF_RC3_8821C 16
#define BIT_MASK_RARF_RC3_8821C 0x1f
-#define BIT_RARF_RC3_8821C(x) (((x) & BIT_MASK_RARF_RC3_8821C) << BIT_SHIFT_RARF_RC3_8821C)
-#define BIT_GET_RARF_RC3_8821C(x) (((x) >> BIT_SHIFT_RARF_RC3_8821C) & BIT_MASK_RARF_RC3_8821C)
-
+#define BIT_RARF_RC3_8821C(x) \
+ (((x) & BIT_MASK_RARF_RC3_8821C) << BIT_SHIFT_RARF_RC3_8821C)
+#define BITS_RARF_RC3_8821C \
+ (BIT_MASK_RARF_RC3_8821C << BIT_SHIFT_RARF_RC3_8821C)
+#define BIT_CLEAR_RARF_RC3_8821C(x) ((x) & (~BITS_RARF_RC3_8821C))
+#define BIT_GET_RARF_RC3_8821C(x) \
+ (((x) >> BIT_SHIFT_RARF_RC3_8821C) & BIT_MASK_RARF_RC3_8821C)
+#define BIT_SET_RARF_RC3_8821C(x, v) \
+ (BIT_CLEAR_RARF_RC3_8821C(x) | BIT_RARF_RC3_8821C(v))
#define BIT_SHIFT_RARF_RC2_8821C 8
#define BIT_MASK_RARF_RC2_8821C 0x1f
-#define BIT_RARF_RC2_8821C(x) (((x) & BIT_MASK_RARF_RC2_8821C) << BIT_SHIFT_RARF_RC2_8821C)
-#define BIT_GET_RARF_RC2_8821C(x) (((x) >> BIT_SHIFT_RARF_RC2_8821C) & BIT_MASK_RARF_RC2_8821C)
-
+#define BIT_RARF_RC2_8821C(x) \
+ (((x) & BIT_MASK_RARF_RC2_8821C) << BIT_SHIFT_RARF_RC2_8821C)
+#define BITS_RARF_RC2_8821C \
+ (BIT_MASK_RARF_RC2_8821C << BIT_SHIFT_RARF_RC2_8821C)
+#define BIT_CLEAR_RARF_RC2_8821C(x) ((x) & (~BITS_RARF_RC2_8821C))
+#define BIT_GET_RARF_RC2_8821C(x) \
+ (((x) >> BIT_SHIFT_RARF_RC2_8821C) & BIT_MASK_RARF_RC2_8821C)
+#define BIT_SET_RARF_RC2_8821C(x, v) \
+ (BIT_CLEAR_RARF_RC2_8821C(x) | BIT_RARF_RC2_8821C(v))
#define BIT_SHIFT_RARF_RC1_8821C 0
#define BIT_MASK_RARF_RC1_8821C 0x1f
-#define BIT_RARF_RC1_8821C(x) (((x) & BIT_MASK_RARF_RC1_8821C) << BIT_SHIFT_RARF_RC1_8821C)
-#define BIT_GET_RARF_RC1_8821C(x) (((x) >> BIT_SHIFT_RARF_RC1_8821C) & BIT_MASK_RARF_RC1_8821C)
-
+#define BIT_RARF_RC1_8821C(x) \
+ (((x) & BIT_MASK_RARF_RC1_8821C) << BIT_SHIFT_RARF_RC1_8821C)
+#define BITS_RARF_RC1_8821C \
+ (BIT_MASK_RARF_RC1_8821C << BIT_SHIFT_RARF_RC1_8821C)
+#define BIT_CLEAR_RARF_RC1_8821C(x) ((x) & (~BITS_RARF_RC1_8821C))
+#define BIT_GET_RARF_RC1_8821C(x) \
+ (((x) >> BIT_SHIFT_RARF_RC1_8821C) & BIT_MASK_RARF_RC1_8821C)
+#define BIT_SET_RARF_RC1_8821C(x, v) \
+ (BIT_CLEAR_RARF_RC1_8821C(x) | BIT_RARF_RC1_8821C(v))
+
+/* 2 REG_RARFRCH_8821C */
+
+#define BIT_SHIFT_RARF_RC8_V1_8821C 24
+#define BIT_MASK_RARF_RC8_V1_8821C 0x1f
+#define BIT_RARF_RC8_V1_8821C(x) \
+ (((x) & BIT_MASK_RARF_RC8_V1_8821C) << BIT_SHIFT_RARF_RC8_V1_8821C)
+#define BITS_RARF_RC8_V1_8821C \
+ (BIT_MASK_RARF_RC8_V1_8821C << BIT_SHIFT_RARF_RC8_V1_8821C)
+#define BIT_CLEAR_RARF_RC8_V1_8821C(x) ((x) & (~BITS_RARF_RC8_V1_8821C))
+#define BIT_GET_RARF_RC8_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_RARF_RC8_V1_8821C) & BIT_MASK_RARF_RC8_V1_8821C)
+#define BIT_SET_RARF_RC8_V1_8821C(x, v) \
+ (BIT_CLEAR_RARF_RC8_V1_8821C(x) | BIT_RARF_RC8_V1_8821C(v))
+
+#define BIT_SHIFT_RARF_RC7_V1_8821C 16
+#define BIT_MASK_RARF_RC7_V1_8821C 0x1f
+#define BIT_RARF_RC7_V1_8821C(x) \
+ (((x) & BIT_MASK_RARF_RC7_V1_8821C) << BIT_SHIFT_RARF_RC7_V1_8821C)
+#define BITS_RARF_RC7_V1_8821C \
+ (BIT_MASK_RARF_RC7_V1_8821C << BIT_SHIFT_RARF_RC7_V1_8821C)
+#define BIT_CLEAR_RARF_RC7_V1_8821C(x) ((x) & (~BITS_RARF_RC7_V1_8821C))
+#define BIT_GET_RARF_RC7_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_RARF_RC7_V1_8821C) & BIT_MASK_RARF_RC7_V1_8821C)
+#define BIT_SET_RARF_RC7_V1_8821C(x, v) \
+ (BIT_CLEAR_RARF_RC7_V1_8821C(x) | BIT_RARF_RC7_V1_8821C(v))
+
+#define BIT_SHIFT_RARF_RC6_V1_8821C 8
+#define BIT_MASK_RARF_RC6_V1_8821C 0x1f
+#define BIT_RARF_RC6_V1_8821C(x) \
+ (((x) & BIT_MASK_RARF_RC6_V1_8821C) << BIT_SHIFT_RARF_RC6_V1_8821C)
+#define BITS_RARF_RC6_V1_8821C \
+ (BIT_MASK_RARF_RC6_V1_8821C << BIT_SHIFT_RARF_RC6_V1_8821C)
+#define BIT_CLEAR_RARF_RC6_V1_8821C(x) ((x) & (~BITS_RARF_RC6_V1_8821C))
+#define BIT_GET_RARF_RC6_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_RARF_RC6_V1_8821C) & BIT_MASK_RARF_RC6_V1_8821C)
+#define BIT_SET_RARF_RC6_V1_8821C(x, v) \
+ (BIT_CLEAR_RARF_RC6_V1_8821C(x) | BIT_RARF_RC6_V1_8821C(v))
+
+#define BIT_SHIFT_RARF_RC5_V1_8821C 0
+#define BIT_MASK_RARF_RC5_V1_8821C 0x1f
+#define BIT_RARF_RC5_V1_8821C(x) \
+ (((x) & BIT_MASK_RARF_RC5_V1_8821C) << BIT_SHIFT_RARF_RC5_V1_8821C)
+#define BITS_RARF_RC5_V1_8821C \
+ (BIT_MASK_RARF_RC5_V1_8821C << BIT_SHIFT_RARF_RC5_V1_8821C)
+#define BIT_CLEAR_RARF_RC5_V1_8821C(x) ((x) & (~BITS_RARF_RC5_V1_8821C))
+#define BIT_GET_RARF_RC5_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_RARF_RC5_V1_8821C) & BIT_MASK_RARF_RC5_V1_8821C)
+#define BIT_SET_RARF_RC5_V1_8821C(x, v) \
+ (BIT_CLEAR_RARF_RC5_V1_8821C(x) | BIT_RARF_RC5_V1_8821C(v))
/* 2 REG_RRSR_8821C */
#define BIT_SHIFT_RRSR_RSC_8821C 21
#define BIT_MASK_RRSR_RSC_8821C 0x3
-#define BIT_RRSR_RSC_8821C(x) (((x) & BIT_MASK_RRSR_RSC_8821C) << BIT_SHIFT_RRSR_RSC_8821C)
-#define BIT_GET_RRSR_RSC_8821C(x) (((x) >> BIT_SHIFT_RRSR_RSC_8821C) & BIT_MASK_RRSR_RSC_8821C)
-
-#define BIT_RRSR_BW_8821C BIT(20)
+#define BIT_RRSR_RSC_8821C(x) \
+ (((x) & BIT_MASK_RRSR_RSC_8821C) << BIT_SHIFT_RRSR_RSC_8821C)
+#define BITS_RRSR_RSC_8821C \
+ (BIT_MASK_RRSR_RSC_8821C << BIT_SHIFT_RRSR_RSC_8821C)
+#define BIT_CLEAR_RRSR_RSC_8821C(x) ((x) & (~BITS_RRSR_RSC_8821C))
+#define BIT_GET_RRSR_RSC_8821C(x) \
+ (((x) >> BIT_SHIFT_RRSR_RSC_8821C) & BIT_MASK_RRSR_RSC_8821C)
+#define BIT_SET_RRSR_RSC_8821C(x, v) \
+ (BIT_CLEAR_RRSR_RSC_8821C(x) | BIT_RRSR_RSC_8821C(v))
#define BIT_SHIFT_RRSC_BITMAP_8821C 0
#define BIT_MASK_RRSC_BITMAP_8821C 0xfffff
-#define BIT_RRSC_BITMAP_8821C(x) (((x) & BIT_MASK_RRSC_BITMAP_8821C) << BIT_SHIFT_RRSC_BITMAP_8821C)
-#define BIT_GET_RRSC_BITMAP_8821C(x) (((x) >> BIT_SHIFT_RRSC_BITMAP_8821C) & BIT_MASK_RRSC_BITMAP_8821C)
+#define BIT_RRSC_BITMAP_8821C(x) \
+ (((x) & BIT_MASK_RRSC_BITMAP_8821C) << BIT_SHIFT_RRSC_BITMAP_8821C)
+#define BITS_RRSC_BITMAP_8821C \
+ (BIT_MASK_RRSC_BITMAP_8821C << BIT_SHIFT_RRSC_BITMAP_8821C)
+#define BIT_CLEAR_RRSC_BITMAP_8821C(x) ((x) & (~BITS_RRSC_BITMAP_8821C))
+#define BIT_GET_RRSC_BITMAP_8821C(x) \
+ (((x) >> BIT_SHIFT_RRSC_BITMAP_8821C) & BIT_MASK_RRSC_BITMAP_8821C)
+#define BIT_SET_RRSC_BITMAP_8821C(x, v) \
+ (BIT_CLEAR_RRSC_BITMAP_8821C(x) | BIT_RRSC_BITMAP_8821C(v))
+/* 2 REG_NOT_VALID_8821C */
/* 2 REG_ARFR0_8821C */
-#define BIT_SHIFT_ARFR0_V1_8821C 0
-#define BIT_MASK_ARFR0_V1_8821C 0xffffffffffffffffL
-#define BIT_ARFR0_V1_8821C(x) (((x) & BIT_MASK_ARFR0_V1_8821C) << BIT_SHIFT_ARFR0_V1_8821C)
-#define BIT_GET_ARFR0_V1_8821C(x) (((x) >> BIT_SHIFT_ARFR0_V1_8821C) & BIT_MASK_ARFR0_V1_8821C)
-
+#define BIT_SHIFT_ARFRL0_8821C 0
+#define BIT_MASK_ARFRL0_8821C 0xffffffffL
+#define BIT_ARFRL0_8821C(x) \
+ (((x) & BIT_MASK_ARFRL0_8821C) << BIT_SHIFT_ARFRL0_8821C)
+#define BITS_ARFRL0_8821C (BIT_MASK_ARFRL0_8821C << BIT_SHIFT_ARFRL0_8821C)
+#define BIT_CLEAR_ARFRL0_8821C(x) ((x) & (~BITS_ARFRL0_8821C))
+#define BIT_GET_ARFRL0_8821C(x) \
+ (((x) >> BIT_SHIFT_ARFRL0_8821C) & BIT_MASK_ARFRL0_8821C)
+#define BIT_SET_ARFRL0_8821C(x, v) \
+ (BIT_CLEAR_ARFRL0_8821C(x) | BIT_ARFRL0_8821C(v))
+
+/* 2 REG_ARFRH0_8821C */
+
+#define BIT_SHIFT_ARFRH0_8821C 0
+#define BIT_MASK_ARFRH0_8821C 0xffffffffL
+#define BIT_ARFRH0_8821C(x) \
+ (((x) & BIT_MASK_ARFRH0_8821C) << BIT_SHIFT_ARFRH0_8821C)
+#define BITS_ARFRH0_8821C (BIT_MASK_ARFRH0_8821C << BIT_SHIFT_ARFRH0_8821C)
+#define BIT_CLEAR_ARFRH0_8821C(x) ((x) & (~BITS_ARFRH0_8821C))
+#define BIT_GET_ARFRH0_8821C(x) \
+ (((x) >> BIT_SHIFT_ARFRH0_8821C) & BIT_MASK_ARFRH0_8821C)
+#define BIT_SET_ARFRH0_8821C(x, v) \
+ (BIT_CLEAR_ARFRH0_8821C(x) | BIT_ARFRH0_8821C(v))
/* 2 REG_ARFR1_V1_8821C */
-#define BIT_SHIFT_ARFR1_V1_8821C 0
-#define BIT_MASK_ARFR1_V1_8821C 0xffffffffffffffffL
-#define BIT_ARFR1_V1_8821C(x) (((x) & BIT_MASK_ARFR1_V1_8821C) << BIT_SHIFT_ARFR1_V1_8821C)
-#define BIT_GET_ARFR1_V1_8821C(x) (((x) >> BIT_SHIFT_ARFR1_V1_8821C) & BIT_MASK_ARFR1_V1_8821C)
-
+#define BIT_SHIFT_ARFRL1_8821C 0
+#define BIT_MASK_ARFRL1_8821C 0xffffffffL
+#define BIT_ARFRL1_8821C(x) \
+ (((x) & BIT_MASK_ARFRL1_8821C) << BIT_SHIFT_ARFRL1_8821C)
+#define BITS_ARFRL1_8821C (BIT_MASK_ARFRL1_8821C << BIT_SHIFT_ARFRL1_8821C)
+#define BIT_CLEAR_ARFRL1_8821C(x) ((x) & (~BITS_ARFRL1_8821C))
+#define BIT_GET_ARFRL1_8821C(x) \
+ (((x) >> BIT_SHIFT_ARFRL1_8821C) & BIT_MASK_ARFRL1_8821C)
+#define BIT_SET_ARFRL1_8821C(x, v) \
+ (BIT_CLEAR_ARFRL1_8821C(x) | BIT_ARFRL1_8821C(v))
+
+/* 2 REG_ARFRH1_V1_8821C */
+
+#define BIT_SHIFT_ARFRH1_8821C 0
+#define BIT_MASK_ARFRH1_8821C 0xffffffffL
+#define BIT_ARFRH1_8821C(x) \
+ (((x) & BIT_MASK_ARFRH1_8821C) << BIT_SHIFT_ARFRH1_8821C)
+#define BITS_ARFRH1_8821C (BIT_MASK_ARFRH1_8821C << BIT_SHIFT_ARFRH1_8821C)
+#define BIT_CLEAR_ARFRH1_8821C(x) ((x) & (~BITS_ARFRH1_8821C))
+#define BIT_GET_ARFRH1_8821C(x) \
+ (((x) >> BIT_SHIFT_ARFRH1_8821C) & BIT_MASK_ARFRH1_8821C)
+#define BIT_SET_ARFRH1_8821C(x, v) \
+ (BIT_CLEAR_ARFRH1_8821C(x) | BIT_ARFRH1_8821C(v))
/* 2 REG_CCK_CHECK_8821C */
#define BIT_CHECK_CCK_EN_8821C BIT(7)
@@ -5200,25 +9561,50 @@
#define BIT_SHIFT_AMPDU_MAX_TIME_8821C 0
#define BIT_MASK_AMPDU_MAX_TIME_8821C 0xff
-#define BIT_AMPDU_MAX_TIME_8821C(x) (((x) & BIT_MASK_AMPDU_MAX_TIME_8821C) << BIT_SHIFT_AMPDU_MAX_TIME_8821C)
-#define BIT_GET_AMPDU_MAX_TIME_8821C(x) (((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8821C) & BIT_MASK_AMPDU_MAX_TIME_8821C)
-
+#define BIT_AMPDU_MAX_TIME_8821C(x) \
+ (((x) & BIT_MASK_AMPDU_MAX_TIME_8821C) \
+ << BIT_SHIFT_AMPDU_MAX_TIME_8821C)
+#define BITS_AMPDU_MAX_TIME_8821C \
+ (BIT_MASK_AMPDU_MAX_TIME_8821C << BIT_SHIFT_AMPDU_MAX_TIME_8821C)
+#define BIT_CLEAR_AMPDU_MAX_TIME_8821C(x) ((x) & (~BITS_AMPDU_MAX_TIME_8821C))
+#define BIT_GET_AMPDU_MAX_TIME_8821C(x) \
+ (((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8821C) & \
+ BIT_MASK_AMPDU_MAX_TIME_8821C)
+#define BIT_SET_AMPDU_MAX_TIME_8821C(x, v) \
+ (BIT_CLEAR_AMPDU_MAX_TIME_8821C(x) | BIT_AMPDU_MAX_TIME_8821C(v))
/* 2 REG_BCNQ1_BDNY_V1_8821C */
#define BIT_SHIFT_BCNQ1_PGBNDY_V1_8821C 0
#define BIT_MASK_BCNQ1_PGBNDY_V1_8821C 0xfff
-#define BIT_BCNQ1_PGBNDY_V1_8821C(x) (((x) & BIT_MASK_BCNQ1_PGBNDY_V1_8821C) << BIT_SHIFT_BCNQ1_PGBNDY_V1_8821C)
-#define BIT_GET_BCNQ1_PGBNDY_V1_8821C(x) (((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1_8821C) & BIT_MASK_BCNQ1_PGBNDY_V1_8821C)
-
+#define BIT_BCNQ1_PGBNDY_V1_8821C(x) \
+ (((x) & BIT_MASK_BCNQ1_PGBNDY_V1_8821C) \
+ << BIT_SHIFT_BCNQ1_PGBNDY_V1_8821C)
+#define BITS_BCNQ1_PGBNDY_V1_8821C \
+ (BIT_MASK_BCNQ1_PGBNDY_V1_8821C << BIT_SHIFT_BCNQ1_PGBNDY_V1_8821C)
+#define BIT_CLEAR_BCNQ1_PGBNDY_V1_8821C(x) ((x) & (~BITS_BCNQ1_PGBNDY_V1_8821C))
+#define BIT_GET_BCNQ1_PGBNDY_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1_8821C) & \
+ BIT_MASK_BCNQ1_PGBNDY_V1_8821C)
+#define BIT_SET_BCNQ1_PGBNDY_V1_8821C(x, v) \
+ (BIT_CLEAR_BCNQ1_PGBNDY_V1_8821C(x) | BIT_BCNQ1_PGBNDY_V1_8821C(v))
/* 2 REG_AMPDU_MAX_LENGTH_8821C */
#define BIT_SHIFT_AMPDU_MAX_LENGTH_8821C 0
#define BIT_MASK_AMPDU_MAX_LENGTH_8821C 0xffffffffL
-#define BIT_AMPDU_MAX_LENGTH_8821C(x) (((x) & BIT_MASK_AMPDU_MAX_LENGTH_8821C) << BIT_SHIFT_AMPDU_MAX_LENGTH_8821C)
-#define BIT_GET_AMPDU_MAX_LENGTH_8821C(x) (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_8821C) & BIT_MASK_AMPDU_MAX_LENGTH_8821C)
-
+#define BIT_AMPDU_MAX_LENGTH_8821C(x) \
+ (((x) & BIT_MASK_AMPDU_MAX_LENGTH_8821C) \
+ << BIT_SHIFT_AMPDU_MAX_LENGTH_8821C)
+#define BITS_AMPDU_MAX_LENGTH_8821C \
+ (BIT_MASK_AMPDU_MAX_LENGTH_8821C << BIT_SHIFT_AMPDU_MAX_LENGTH_8821C)
+#define BIT_CLEAR_AMPDU_MAX_LENGTH_8821C(x) \
+ ((x) & (~BITS_AMPDU_MAX_LENGTH_8821C))
+#define BIT_GET_AMPDU_MAX_LENGTH_8821C(x) \
+ (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_8821C) & \
+ BIT_MASK_AMPDU_MAX_LENGTH_8821C)
+#define BIT_SET_AMPDU_MAX_LENGTH_8821C(x, v) \
+ (BIT_CLEAR_AMPDU_MAX_LENGTH_8821C(x) | BIT_AMPDU_MAX_LENGTH_8821C(v))
/* 2 REG_ACQ_STOP_8821C */
#define BIT_AC7Q_STOP_8821C BIT(7)
@@ -5234,9 +9620,17 @@
#define BIT_SHIFT_R_NDPA_RATE_V1_8821C 0
#define BIT_MASK_R_NDPA_RATE_V1_8821C 0xff
-#define BIT_R_NDPA_RATE_V1_8821C(x) (((x) & BIT_MASK_R_NDPA_RATE_V1_8821C) << BIT_SHIFT_R_NDPA_RATE_V1_8821C)
-#define BIT_GET_R_NDPA_RATE_V1_8821C(x) (((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8821C) & BIT_MASK_R_NDPA_RATE_V1_8821C)
-
+#define BIT_R_NDPA_RATE_V1_8821C(x) \
+ (((x) & BIT_MASK_R_NDPA_RATE_V1_8821C) \
+ << BIT_SHIFT_R_NDPA_RATE_V1_8821C)
+#define BITS_R_NDPA_RATE_V1_8821C \
+ (BIT_MASK_R_NDPA_RATE_V1_8821C << BIT_SHIFT_R_NDPA_RATE_V1_8821C)
+#define BIT_CLEAR_R_NDPA_RATE_V1_8821C(x) ((x) & (~BITS_R_NDPA_RATE_V1_8821C))
+#define BIT_GET_R_NDPA_RATE_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8821C) & \
+ BIT_MASK_R_NDPA_RATE_V1_8821C)
+#define BIT_SET_R_NDPA_RATE_V1_8821C(x, v) \
+ (BIT_CLEAR_R_NDPA_RATE_V1_8821C(x) | BIT_R_NDPA_RATE_V1_8821C(v))
/* 2 REG_TX_HANG_CTRL_8821C */
#define BIT_R_EN_GNT_BT_AWAKE_8821C BIT(3)
@@ -5249,18 +9643,29 @@
#define BIT_SHIFT_BW_SIGTA_8821C 3
#define BIT_MASK_BW_SIGTA_8821C 0x3
-#define BIT_BW_SIGTA_8821C(x) (((x) & BIT_MASK_BW_SIGTA_8821C) << BIT_SHIFT_BW_SIGTA_8821C)
-#define BIT_GET_BW_SIGTA_8821C(x) (((x) >> BIT_SHIFT_BW_SIGTA_8821C) & BIT_MASK_BW_SIGTA_8821C)
+#define BIT_BW_SIGTA_8821C(x) \
+ (((x) & BIT_MASK_BW_SIGTA_8821C) << BIT_SHIFT_BW_SIGTA_8821C)
+#define BITS_BW_SIGTA_8821C \
+ (BIT_MASK_BW_SIGTA_8821C << BIT_SHIFT_BW_SIGTA_8821C)
+#define BIT_CLEAR_BW_SIGTA_8821C(x) ((x) & (~BITS_BW_SIGTA_8821C))
+#define BIT_GET_BW_SIGTA_8821C(x) \
+ (((x) >> BIT_SHIFT_BW_SIGTA_8821C) & BIT_MASK_BW_SIGTA_8821C)
+#define BIT_SET_BW_SIGTA_8821C(x, v) \
+ (BIT_CLEAR_BW_SIGTA_8821C(x) | BIT_BW_SIGTA_8821C(v))
#define BIT_EN_BAR_SIGTA_8821C BIT(2)
#define BIT_SHIFT_R_NDPA_BW_8821C 0
#define BIT_MASK_R_NDPA_BW_8821C 0x3
-#define BIT_R_NDPA_BW_8821C(x) (((x) & BIT_MASK_R_NDPA_BW_8821C) << BIT_SHIFT_R_NDPA_BW_8821C)
-#define BIT_GET_R_NDPA_BW_8821C(x) (((x) >> BIT_SHIFT_R_NDPA_BW_8821C) & BIT_MASK_R_NDPA_BW_8821C)
-
-
-/* 2 REG_NOT_VALID_8821C */
+#define BIT_R_NDPA_BW_8821C(x) \
+ (((x) & BIT_MASK_R_NDPA_BW_8821C) << BIT_SHIFT_R_NDPA_BW_8821C)
+#define BITS_R_NDPA_BW_8821C \
+ (BIT_MASK_R_NDPA_BW_8821C << BIT_SHIFT_R_NDPA_BW_8821C)
+#define BIT_CLEAR_R_NDPA_BW_8821C(x) ((x) & (~BITS_R_NDPA_BW_8821C))
+#define BIT_GET_R_NDPA_BW_8821C(x) \
+ (((x) >> BIT_SHIFT_R_NDPA_BW_8821C) & BIT_MASK_R_NDPA_BW_8821C)
+#define BIT_SET_R_NDPA_BW_8821C(x, v) \
+ (BIT_CLEAR_R_NDPA_BW_8821C(x) | BIT_R_NDPA_BW_8821C(v))
/* 2 REG_NOT_VALID_8821C */
@@ -5268,186 +9673,408 @@
#define BIT_SHIFT_RD_RESP_PKT_TH_V1_8821C 0
#define BIT_MASK_RD_RESP_PKT_TH_V1_8821C 0x3f
-#define BIT_RD_RESP_PKT_TH_V1_8821C(x) (((x) & BIT_MASK_RD_RESP_PKT_TH_V1_8821C) << BIT_SHIFT_RD_RESP_PKT_TH_V1_8821C)
-#define BIT_GET_RD_RESP_PKT_TH_V1_8821C(x) (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8821C) & BIT_MASK_RD_RESP_PKT_TH_V1_8821C)
-
+#define BIT_RD_RESP_PKT_TH_V1_8821C(x) \
+ (((x) & BIT_MASK_RD_RESP_PKT_TH_V1_8821C) \
+ << BIT_SHIFT_RD_RESP_PKT_TH_V1_8821C)
+#define BITS_RD_RESP_PKT_TH_V1_8821C \
+ (BIT_MASK_RD_RESP_PKT_TH_V1_8821C << BIT_SHIFT_RD_RESP_PKT_TH_V1_8821C)
+#define BIT_CLEAR_RD_RESP_PKT_TH_V1_8821C(x) \
+ ((x) & (~BITS_RD_RESP_PKT_TH_V1_8821C))
+#define BIT_GET_RD_RESP_PKT_TH_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8821C) & \
+ BIT_MASK_RD_RESP_PKT_TH_V1_8821C)
+#define BIT_SET_RD_RESP_PKT_TH_V1_8821C(x, v) \
+ (BIT_CLEAR_RD_RESP_PKT_TH_V1_8821C(x) | BIT_RD_RESP_PKT_TH_V1_8821C(v))
/* 2 REG_CMDQ_INFO_8821C */
#define BIT_SHIFT_QUEUEMACID_CMDQ_V1_8821C 25
#define BIT_MASK_QUEUEMACID_CMDQ_V1_8821C 0x7f
-#define BIT_QUEUEMACID_CMDQ_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_CMDQ_V1_8821C) << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8821C)
-#define BIT_GET_QUEUEMACID_CMDQ_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1_8821C) & BIT_MASK_QUEUEMACID_CMDQ_V1_8821C)
-
+#define BIT_QUEUEMACID_CMDQ_V1_8821C(x) \
+ (((x) & BIT_MASK_QUEUEMACID_CMDQ_V1_8821C) \
+ << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8821C)
+#define BITS_QUEUEMACID_CMDQ_V1_8821C \
+ (BIT_MASK_QUEUEMACID_CMDQ_V1_8821C \
+ << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8821C)
+#define BIT_CLEAR_QUEUEMACID_CMDQ_V1_8821C(x) \
+ ((x) & (~BITS_QUEUEMACID_CMDQ_V1_8821C))
+#define BIT_GET_QUEUEMACID_CMDQ_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1_8821C) & \
+ BIT_MASK_QUEUEMACID_CMDQ_V1_8821C)
+#define BIT_SET_QUEUEMACID_CMDQ_V1_8821C(x, v) \
+ (BIT_CLEAR_QUEUEMACID_CMDQ_V1_8821C(x) | \
+ BIT_QUEUEMACID_CMDQ_V1_8821C(v))
#define BIT_SHIFT_QUEUEAC_CMDQ_V1_8821C 23
#define BIT_MASK_QUEUEAC_CMDQ_V1_8821C 0x3
-#define BIT_QUEUEAC_CMDQ_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_CMDQ_V1_8821C) << BIT_SHIFT_QUEUEAC_CMDQ_V1_8821C)
-#define BIT_GET_QUEUEAC_CMDQ_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1_8821C) & BIT_MASK_QUEUEAC_CMDQ_V1_8821C)
+#define BIT_QUEUEAC_CMDQ_V1_8821C(x) \
+ (((x) & BIT_MASK_QUEUEAC_CMDQ_V1_8821C) \
+ << BIT_SHIFT_QUEUEAC_CMDQ_V1_8821C)
+#define BITS_QUEUEAC_CMDQ_V1_8821C \
+ (BIT_MASK_QUEUEAC_CMDQ_V1_8821C << BIT_SHIFT_QUEUEAC_CMDQ_V1_8821C)
+#define BIT_CLEAR_QUEUEAC_CMDQ_V1_8821C(x) ((x) & (~BITS_QUEUEAC_CMDQ_V1_8821C))
+#define BIT_GET_QUEUEAC_CMDQ_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1_8821C) & \
+ BIT_MASK_QUEUEAC_CMDQ_V1_8821C)
+#define BIT_SET_QUEUEAC_CMDQ_V1_8821C(x, v) \
+ (BIT_CLEAR_QUEUEAC_CMDQ_V1_8821C(x) | BIT_QUEUEAC_CMDQ_V1_8821C(v))
#define BIT_TIDEMPTY_CMDQ_V1_8821C BIT(22)
-#define BIT_SHIFT_TAIL_PKT_CMDQ_V2_8821C 11
-#define BIT_MASK_TAIL_PKT_CMDQ_V2_8821C 0x7ff
-#define BIT_TAIL_PKT_CMDQ_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_CMDQ_V2_8821C) << BIT_SHIFT_TAIL_PKT_CMDQ_V2_8821C)
-#define BIT_GET_TAIL_PKT_CMDQ_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_CMDQ_V2_8821C) & BIT_MASK_TAIL_PKT_CMDQ_V2_8821C)
-
+#define BIT_SHIFT_TAIL_PKT_Q4_V2_8821C 11
+#define BIT_MASK_TAIL_PKT_Q4_V2_8821C 0x7ff
+#define BIT_TAIL_PKT_Q4_V2_8821C(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q4_V2_8821C) \
+ << BIT_SHIFT_TAIL_PKT_Q4_V2_8821C)
+#define BITS_TAIL_PKT_Q4_V2_8821C \
+ (BIT_MASK_TAIL_PKT_Q4_V2_8821C << BIT_SHIFT_TAIL_PKT_Q4_V2_8821C)
+#define BIT_CLEAR_TAIL_PKT_Q4_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q4_V2_8821C))
+#define BIT_GET_TAIL_PKT_Q4_V2_8821C(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8821C) & \
+ BIT_MASK_TAIL_PKT_Q4_V2_8821C)
+#define BIT_SET_TAIL_PKT_Q4_V2_8821C(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q4_V2_8821C(x) | BIT_TAIL_PKT_Q4_V2_8821C(v))
#define BIT_SHIFT_HEAD_PKT_CMDQ_V1_8821C 0
#define BIT_MASK_HEAD_PKT_CMDQ_V1_8821C 0x7ff
-#define BIT_HEAD_PKT_CMDQ_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_CMDQ_V1_8821C) << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8821C)
-#define BIT_GET_HEAD_PKT_CMDQ_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1_8821C) & BIT_MASK_HEAD_PKT_CMDQ_V1_8821C)
-
+#define BIT_HEAD_PKT_CMDQ_V1_8821C(x) \
+ (((x) & BIT_MASK_HEAD_PKT_CMDQ_V1_8821C) \
+ << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8821C)
+#define BITS_HEAD_PKT_CMDQ_V1_8821C \
+ (BIT_MASK_HEAD_PKT_CMDQ_V1_8821C << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8821C)
+#define BIT_CLEAR_HEAD_PKT_CMDQ_V1_8821C(x) \
+ ((x) & (~BITS_HEAD_PKT_CMDQ_V1_8821C))
+#define BIT_GET_HEAD_PKT_CMDQ_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1_8821C) & \
+ BIT_MASK_HEAD_PKT_CMDQ_V1_8821C)
+#define BIT_SET_HEAD_PKT_CMDQ_V1_8821C(x, v) \
+ (BIT_CLEAR_HEAD_PKT_CMDQ_V1_8821C(x) | BIT_HEAD_PKT_CMDQ_V1_8821C(v))
/* 2 REG_Q4_INFO_8821C */
#define BIT_SHIFT_QUEUEMACID_Q4_V1_8821C 25
#define BIT_MASK_QUEUEMACID_Q4_V1_8821C 0x7f
-#define BIT_QUEUEMACID_Q4_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_Q4_V1_8821C) << BIT_SHIFT_QUEUEMACID_Q4_V1_8821C)
-#define BIT_GET_QUEUEMACID_Q4_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1_8821C) & BIT_MASK_QUEUEMACID_Q4_V1_8821C)
-
+#define BIT_QUEUEMACID_Q4_V1_8821C(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q4_V1_8821C) \
+ << BIT_SHIFT_QUEUEMACID_Q4_V1_8821C)
+#define BITS_QUEUEMACID_Q4_V1_8821C \
+ (BIT_MASK_QUEUEMACID_Q4_V1_8821C << BIT_SHIFT_QUEUEMACID_Q4_V1_8821C)
+#define BIT_CLEAR_QUEUEMACID_Q4_V1_8821C(x) \
+ ((x) & (~BITS_QUEUEMACID_Q4_V1_8821C))
+#define BIT_GET_QUEUEMACID_Q4_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1_8821C) & \
+ BIT_MASK_QUEUEMACID_Q4_V1_8821C)
+#define BIT_SET_QUEUEMACID_Q4_V1_8821C(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q4_V1_8821C(x) | BIT_QUEUEMACID_Q4_V1_8821C(v))
#define BIT_SHIFT_QUEUEAC_Q4_V1_8821C 23
#define BIT_MASK_QUEUEAC_Q4_V1_8821C 0x3
-#define BIT_QUEUEAC_Q4_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q4_V1_8821C) << BIT_SHIFT_QUEUEAC_Q4_V1_8821C)
-#define BIT_GET_QUEUEAC_Q4_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q4_V1_8821C) & BIT_MASK_QUEUEAC_Q4_V1_8821C)
+#define BIT_QUEUEAC_Q4_V1_8821C(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q4_V1_8821C) << BIT_SHIFT_QUEUEAC_Q4_V1_8821C)
+#define BITS_QUEUEAC_Q4_V1_8821C \
+ (BIT_MASK_QUEUEAC_Q4_V1_8821C << BIT_SHIFT_QUEUEAC_Q4_V1_8821C)
+#define BIT_CLEAR_QUEUEAC_Q4_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q4_V1_8821C))
+#define BIT_GET_QUEUEAC_Q4_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q4_V1_8821C) & BIT_MASK_QUEUEAC_Q4_V1_8821C)
+#define BIT_SET_QUEUEAC_Q4_V1_8821C(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q4_V1_8821C(x) | BIT_QUEUEAC_Q4_V1_8821C(v))
#define BIT_TIDEMPTY_Q4_V1_8821C BIT(22)
#define BIT_SHIFT_TAIL_PKT_Q4_V2_8821C 11
#define BIT_MASK_TAIL_PKT_Q4_V2_8821C 0x7ff
-#define BIT_TAIL_PKT_Q4_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_Q4_V2_8821C) << BIT_SHIFT_TAIL_PKT_Q4_V2_8821C)
-#define BIT_GET_TAIL_PKT_Q4_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8821C) & BIT_MASK_TAIL_PKT_Q4_V2_8821C)
-
+#define BIT_TAIL_PKT_Q4_V2_8821C(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q4_V2_8821C) \
+ << BIT_SHIFT_TAIL_PKT_Q4_V2_8821C)
+#define BITS_TAIL_PKT_Q4_V2_8821C \
+ (BIT_MASK_TAIL_PKT_Q4_V2_8821C << BIT_SHIFT_TAIL_PKT_Q4_V2_8821C)
+#define BIT_CLEAR_TAIL_PKT_Q4_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q4_V2_8821C))
+#define BIT_GET_TAIL_PKT_Q4_V2_8821C(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8821C) & \
+ BIT_MASK_TAIL_PKT_Q4_V2_8821C)
+#define BIT_SET_TAIL_PKT_Q4_V2_8821C(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q4_V2_8821C(x) | BIT_TAIL_PKT_Q4_V2_8821C(v))
#define BIT_SHIFT_HEAD_PKT_Q4_V1_8821C 0
#define BIT_MASK_HEAD_PKT_Q4_V1_8821C 0x7ff
-#define BIT_HEAD_PKT_Q4_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q4_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q4_V1_8821C)
-#define BIT_GET_HEAD_PKT_Q4_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1_8821C) & BIT_MASK_HEAD_PKT_Q4_V1_8821C)
-
+#define BIT_HEAD_PKT_Q4_V1_8821C(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q4_V1_8821C) \
+ << BIT_SHIFT_HEAD_PKT_Q4_V1_8821C)
+#define BITS_HEAD_PKT_Q4_V1_8821C \
+ (BIT_MASK_HEAD_PKT_Q4_V1_8821C << BIT_SHIFT_HEAD_PKT_Q4_V1_8821C)
+#define BIT_CLEAR_HEAD_PKT_Q4_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q4_V1_8821C))
+#define BIT_GET_HEAD_PKT_Q4_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1_8821C) & \
+ BIT_MASK_HEAD_PKT_Q4_V1_8821C)
+#define BIT_SET_HEAD_PKT_Q4_V1_8821C(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q4_V1_8821C(x) | BIT_HEAD_PKT_Q4_V1_8821C(v))
/* 2 REG_Q5_INFO_8821C */
#define BIT_SHIFT_QUEUEMACID_Q5_V1_8821C 25
#define BIT_MASK_QUEUEMACID_Q5_V1_8821C 0x7f
-#define BIT_QUEUEMACID_Q5_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_Q5_V1_8821C) << BIT_SHIFT_QUEUEMACID_Q5_V1_8821C)
-#define BIT_GET_QUEUEMACID_Q5_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1_8821C) & BIT_MASK_QUEUEMACID_Q5_V1_8821C)
-
+#define BIT_QUEUEMACID_Q5_V1_8821C(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q5_V1_8821C) \
+ << BIT_SHIFT_QUEUEMACID_Q5_V1_8821C)
+#define BITS_QUEUEMACID_Q5_V1_8821C \
+ (BIT_MASK_QUEUEMACID_Q5_V1_8821C << BIT_SHIFT_QUEUEMACID_Q5_V1_8821C)
+#define BIT_CLEAR_QUEUEMACID_Q5_V1_8821C(x) \
+ ((x) & (~BITS_QUEUEMACID_Q5_V1_8821C))
+#define BIT_GET_QUEUEMACID_Q5_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1_8821C) & \
+ BIT_MASK_QUEUEMACID_Q5_V1_8821C)
+#define BIT_SET_QUEUEMACID_Q5_V1_8821C(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q5_V1_8821C(x) | BIT_QUEUEMACID_Q5_V1_8821C(v))
#define BIT_SHIFT_QUEUEAC_Q5_V1_8821C 23
#define BIT_MASK_QUEUEAC_Q5_V1_8821C 0x3
-#define BIT_QUEUEAC_Q5_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q5_V1_8821C) << BIT_SHIFT_QUEUEAC_Q5_V1_8821C)
-#define BIT_GET_QUEUEAC_Q5_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q5_V1_8821C) & BIT_MASK_QUEUEAC_Q5_V1_8821C)
+#define BIT_QUEUEAC_Q5_V1_8821C(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q5_V1_8821C) << BIT_SHIFT_QUEUEAC_Q5_V1_8821C)
+#define BITS_QUEUEAC_Q5_V1_8821C \
+ (BIT_MASK_QUEUEAC_Q5_V1_8821C << BIT_SHIFT_QUEUEAC_Q5_V1_8821C)
+#define BIT_CLEAR_QUEUEAC_Q5_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q5_V1_8821C))
+#define BIT_GET_QUEUEAC_Q5_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q5_V1_8821C) & BIT_MASK_QUEUEAC_Q5_V1_8821C)
+#define BIT_SET_QUEUEAC_Q5_V1_8821C(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q5_V1_8821C(x) | BIT_QUEUEAC_Q5_V1_8821C(v))
#define BIT_TIDEMPTY_Q5_V1_8821C BIT(22)
#define BIT_SHIFT_TAIL_PKT_Q5_V2_8821C 11
#define BIT_MASK_TAIL_PKT_Q5_V2_8821C 0x7ff
-#define BIT_TAIL_PKT_Q5_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_Q5_V2_8821C) << BIT_SHIFT_TAIL_PKT_Q5_V2_8821C)
-#define BIT_GET_TAIL_PKT_Q5_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2_8821C) & BIT_MASK_TAIL_PKT_Q5_V2_8821C)
-
+#define BIT_TAIL_PKT_Q5_V2_8821C(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q5_V2_8821C) \
+ << BIT_SHIFT_TAIL_PKT_Q5_V2_8821C)
+#define BITS_TAIL_PKT_Q5_V2_8821C \
+ (BIT_MASK_TAIL_PKT_Q5_V2_8821C << BIT_SHIFT_TAIL_PKT_Q5_V2_8821C)
+#define BIT_CLEAR_TAIL_PKT_Q5_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q5_V2_8821C))
+#define BIT_GET_TAIL_PKT_Q5_V2_8821C(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2_8821C) & \
+ BIT_MASK_TAIL_PKT_Q5_V2_8821C)
+#define BIT_SET_TAIL_PKT_Q5_V2_8821C(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q5_V2_8821C(x) | BIT_TAIL_PKT_Q5_V2_8821C(v))
#define BIT_SHIFT_HEAD_PKT_Q5_V1_8821C 0
#define BIT_MASK_HEAD_PKT_Q5_V1_8821C 0x7ff
-#define BIT_HEAD_PKT_Q5_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q5_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q5_V1_8821C)
-#define BIT_GET_HEAD_PKT_Q5_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1_8821C) & BIT_MASK_HEAD_PKT_Q5_V1_8821C)
-
+#define BIT_HEAD_PKT_Q5_V1_8821C(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q5_V1_8821C) \
+ << BIT_SHIFT_HEAD_PKT_Q5_V1_8821C)
+#define BITS_HEAD_PKT_Q5_V1_8821C \
+ (BIT_MASK_HEAD_PKT_Q5_V1_8821C << BIT_SHIFT_HEAD_PKT_Q5_V1_8821C)
+#define BIT_CLEAR_HEAD_PKT_Q5_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q5_V1_8821C))
+#define BIT_GET_HEAD_PKT_Q5_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1_8821C) & \
+ BIT_MASK_HEAD_PKT_Q5_V1_8821C)
+#define BIT_SET_HEAD_PKT_Q5_V1_8821C(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q5_V1_8821C(x) | BIT_HEAD_PKT_Q5_V1_8821C(v))
/* 2 REG_Q6_INFO_8821C */
#define BIT_SHIFT_QUEUEMACID_Q6_V1_8821C 25
#define BIT_MASK_QUEUEMACID_Q6_V1_8821C 0x7f
-#define BIT_QUEUEMACID_Q6_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_Q6_V1_8821C) << BIT_SHIFT_QUEUEMACID_Q6_V1_8821C)
-#define BIT_GET_QUEUEMACID_Q6_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1_8821C) & BIT_MASK_QUEUEMACID_Q6_V1_8821C)
-
+#define BIT_QUEUEMACID_Q6_V1_8821C(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q6_V1_8821C) \
+ << BIT_SHIFT_QUEUEMACID_Q6_V1_8821C)
+#define BITS_QUEUEMACID_Q6_V1_8821C \
+ (BIT_MASK_QUEUEMACID_Q6_V1_8821C << BIT_SHIFT_QUEUEMACID_Q6_V1_8821C)
+#define BIT_CLEAR_QUEUEMACID_Q6_V1_8821C(x) \
+ ((x) & (~BITS_QUEUEMACID_Q6_V1_8821C))
+#define BIT_GET_QUEUEMACID_Q6_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1_8821C) & \
+ BIT_MASK_QUEUEMACID_Q6_V1_8821C)
+#define BIT_SET_QUEUEMACID_Q6_V1_8821C(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q6_V1_8821C(x) | BIT_QUEUEMACID_Q6_V1_8821C(v))
#define BIT_SHIFT_QUEUEAC_Q6_V1_8821C 23
#define BIT_MASK_QUEUEAC_Q6_V1_8821C 0x3
-#define BIT_QUEUEAC_Q6_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q6_V1_8821C) << BIT_SHIFT_QUEUEAC_Q6_V1_8821C)
-#define BIT_GET_QUEUEAC_Q6_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q6_V1_8821C) & BIT_MASK_QUEUEAC_Q6_V1_8821C)
+#define BIT_QUEUEAC_Q6_V1_8821C(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q6_V1_8821C) << BIT_SHIFT_QUEUEAC_Q6_V1_8821C)
+#define BITS_QUEUEAC_Q6_V1_8821C \
+ (BIT_MASK_QUEUEAC_Q6_V1_8821C << BIT_SHIFT_QUEUEAC_Q6_V1_8821C)
+#define BIT_CLEAR_QUEUEAC_Q6_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q6_V1_8821C))
+#define BIT_GET_QUEUEAC_Q6_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q6_V1_8821C) & BIT_MASK_QUEUEAC_Q6_V1_8821C)
+#define BIT_SET_QUEUEAC_Q6_V1_8821C(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q6_V1_8821C(x) | BIT_QUEUEAC_Q6_V1_8821C(v))
#define BIT_TIDEMPTY_Q6_V1_8821C BIT(22)
#define BIT_SHIFT_TAIL_PKT_Q6_V2_8821C 11
#define BIT_MASK_TAIL_PKT_Q6_V2_8821C 0x7ff
-#define BIT_TAIL_PKT_Q6_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_Q6_V2_8821C) << BIT_SHIFT_TAIL_PKT_Q6_V2_8821C)
-#define BIT_GET_TAIL_PKT_Q6_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2_8821C) & BIT_MASK_TAIL_PKT_Q6_V2_8821C)
-
+#define BIT_TAIL_PKT_Q6_V2_8821C(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q6_V2_8821C) \
+ << BIT_SHIFT_TAIL_PKT_Q6_V2_8821C)
+#define BITS_TAIL_PKT_Q6_V2_8821C \
+ (BIT_MASK_TAIL_PKT_Q6_V2_8821C << BIT_SHIFT_TAIL_PKT_Q6_V2_8821C)
+#define BIT_CLEAR_TAIL_PKT_Q6_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q6_V2_8821C))
+#define BIT_GET_TAIL_PKT_Q6_V2_8821C(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2_8821C) & \
+ BIT_MASK_TAIL_PKT_Q6_V2_8821C)
+#define BIT_SET_TAIL_PKT_Q6_V2_8821C(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q6_V2_8821C(x) | BIT_TAIL_PKT_Q6_V2_8821C(v))
#define BIT_SHIFT_HEAD_PKT_Q6_V1_8821C 0
#define BIT_MASK_HEAD_PKT_Q6_V1_8821C 0x7ff
-#define BIT_HEAD_PKT_Q6_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q6_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q6_V1_8821C)
-#define BIT_GET_HEAD_PKT_Q6_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1_8821C) & BIT_MASK_HEAD_PKT_Q6_V1_8821C)
-
+#define BIT_HEAD_PKT_Q6_V1_8821C(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q6_V1_8821C) \
+ << BIT_SHIFT_HEAD_PKT_Q6_V1_8821C)
+#define BITS_HEAD_PKT_Q6_V1_8821C \
+ (BIT_MASK_HEAD_PKT_Q6_V1_8821C << BIT_SHIFT_HEAD_PKT_Q6_V1_8821C)
+#define BIT_CLEAR_HEAD_PKT_Q6_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q6_V1_8821C))
+#define BIT_GET_HEAD_PKT_Q6_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1_8821C) & \
+ BIT_MASK_HEAD_PKT_Q6_V1_8821C)
+#define BIT_SET_HEAD_PKT_Q6_V1_8821C(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q6_V1_8821C(x) | BIT_HEAD_PKT_Q6_V1_8821C(v))
/* 2 REG_Q7_INFO_8821C */
#define BIT_SHIFT_QUEUEMACID_Q7_V1_8821C 25
#define BIT_MASK_QUEUEMACID_Q7_V1_8821C 0x7f
-#define BIT_QUEUEMACID_Q7_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_Q7_V1_8821C) << BIT_SHIFT_QUEUEMACID_Q7_V1_8821C)
-#define BIT_GET_QUEUEMACID_Q7_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1_8821C) & BIT_MASK_QUEUEMACID_Q7_V1_8821C)
-
+#define BIT_QUEUEMACID_Q7_V1_8821C(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q7_V1_8821C) \
+ << BIT_SHIFT_QUEUEMACID_Q7_V1_8821C)
+#define BITS_QUEUEMACID_Q7_V1_8821C \
+ (BIT_MASK_QUEUEMACID_Q7_V1_8821C << BIT_SHIFT_QUEUEMACID_Q7_V1_8821C)
+#define BIT_CLEAR_QUEUEMACID_Q7_V1_8821C(x) \
+ ((x) & (~BITS_QUEUEMACID_Q7_V1_8821C))
+#define BIT_GET_QUEUEMACID_Q7_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1_8821C) & \
+ BIT_MASK_QUEUEMACID_Q7_V1_8821C)
+#define BIT_SET_QUEUEMACID_Q7_V1_8821C(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q7_V1_8821C(x) | BIT_QUEUEMACID_Q7_V1_8821C(v))
#define BIT_SHIFT_QUEUEAC_Q7_V1_8821C 23
#define BIT_MASK_QUEUEAC_Q7_V1_8821C 0x3
-#define BIT_QUEUEAC_Q7_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q7_V1_8821C) << BIT_SHIFT_QUEUEAC_Q7_V1_8821C)
-#define BIT_GET_QUEUEAC_Q7_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q7_V1_8821C) & BIT_MASK_QUEUEAC_Q7_V1_8821C)
+#define BIT_QUEUEAC_Q7_V1_8821C(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q7_V1_8821C) << BIT_SHIFT_QUEUEAC_Q7_V1_8821C)
+#define BITS_QUEUEAC_Q7_V1_8821C \
+ (BIT_MASK_QUEUEAC_Q7_V1_8821C << BIT_SHIFT_QUEUEAC_Q7_V1_8821C)
+#define BIT_CLEAR_QUEUEAC_Q7_V1_8821C(x) ((x) & (~BITS_QUEUEAC_Q7_V1_8821C))
+#define BIT_GET_QUEUEAC_Q7_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q7_V1_8821C) & BIT_MASK_QUEUEAC_Q7_V1_8821C)
+#define BIT_SET_QUEUEAC_Q7_V1_8821C(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q7_V1_8821C(x) | BIT_QUEUEAC_Q7_V1_8821C(v))
#define BIT_TIDEMPTY_Q7_V1_8821C BIT(22)
#define BIT_SHIFT_TAIL_PKT_Q7_V2_8821C 11
#define BIT_MASK_TAIL_PKT_Q7_V2_8821C 0x7ff
-#define BIT_TAIL_PKT_Q7_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_Q7_V2_8821C) << BIT_SHIFT_TAIL_PKT_Q7_V2_8821C)
-#define BIT_GET_TAIL_PKT_Q7_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2_8821C) & BIT_MASK_TAIL_PKT_Q7_V2_8821C)
-
+#define BIT_TAIL_PKT_Q7_V2_8821C(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q7_V2_8821C) \
+ << BIT_SHIFT_TAIL_PKT_Q7_V2_8821C)
+#define BITS_TAIL_PKT_Q7_V2_8821C \
+ (BIT_MASK_TAIL_PKT_Q7_V2_8821C << BIT_SHIFT_TAIL_PKT_Q7_V2_8821C)
+#define BIT_CLEAR_TAIL_PKT_Q7_V2_8821C(x) ((x) & (~BITS_TAIL_PKT_Q7_V2_8821C))
+#define BIT_GET_TAIL_PKT_Q7_V2_8821C(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2_8821C) & \
+ BIT_MASK_TAIL_PKT_Q7_V2_8821C)
+#define BIT_SET_TAIL_PKT_Q7_V2_8821C(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q7_V2_8821C(x) | BIT_TAIL_PKT_Q7_V2_8821C(v))
#define BIT_SHIFT_HEAD_PKT_Q7_V1_8821C 0
#define BIT_MASK_HEAD_PKT_Q7_V1_8821C 0x7ff
-#define BIT_HEAD_PKT_Q7_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q7_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q7_V1_8821C)
-#define BIT_GET_HEAD_PKT_Q7_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1_8821C) & BIT_MASK_HEAD_PKT_Q7_V1_8821C)
-
+#define BIT_HEAD_PKT_Q7_V1_8821C(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q7_V1_8821C) \
+ << BIT_SHIFT_HEAD_PKT_Q7_V1_8821C)
+#define BITS_HEAD_PKT_Q7_V1_8821C \
+ (BIT_MASK_HEAD_PKT_Q7_V1_8821C << BIT_SHIFT_HEAD_PKT_Q7_V1_8821C)
+#define BIT_CLEAR_HEAD_PKT_Q7_V1_8821C(x) ((x) & (~BITS_HEAD_PKT_Q7_V1_8821C))
+#define BIT_GET_HEAD_PKT_Q7_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1_8821C) & \
+ BIT_MASK_HEAD_PKT_Q7_V1_8821C)
+#define BIT_SET_HEAD_PKT_Q7_V1_8821C(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q7_V1_8821C(x) | BIT_HEAD_PKT_Q7_V1_8821C(v))
/* 2 REG_WMAC_LBK_BUF_HD_V1_8821C */
#define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8821C 0
#define BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8821C 0xfff
-#define BIT_WMAC_LBK_BUF_HEAD_V1_8821C(x) (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8821C) << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8821C)
-#define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8821C(x) (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8821C) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8821C)
-
+#define BIT_WMAC_LBK_BUF_HEAD_V1_8821C(x) \
+ (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8821C) \
+ << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8821C)
+#define BITS_WMAC_LBK_BUF_HEAD_V1_8821C \
+ (BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8821C \
+ << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8821C)
+#define BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8821C(x) \
+ ((x) & (~BITS_WMAC_LBK_BUF_HEAD_V1_8821C))
+#define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8821C) & \
+ BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8821C)
+#define BIT_SET_WMAC_LBK_BUF_HEAD_V1_8821C(x, v) \
+ (BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8821C(x) | \
+ BIT_WMAC_LBK_BUF_HEAD_V1_8821C(v))
/* 2 REG_MGQ_BDNY_V1_8821C */
#define BIT_SHIFT_MGQ_PGBNDY_V1_8821C 0
#define BIT_MASK_MGQ_PGBNDY_V1_8821C 0xfff
-#define BIT_MGQ_PGBNDY_V1_8821C(x) (((x) & BIT_MASK_MGQ_PGBNDY_V1_8821C) << BIT_SHIFT_MGQ_PGBNDY_V1_8821C)
-#define BIT_GET_MGQ_PGBNDY_V1_8821C(x) (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8821C) & BIT_MASK_MGQ_PGBNDY_V1_8821C)
-
+#define BIT_MGQ_PGBNDY_V1_8821C(x) \
+ (((x) & BIT_MASK_MGQ_PGBNDY_V1_8821C) << BIT_SHIFT_MGQ_PGBNDY_V1_8821C)
+#define BITS_MGQ_PGBNDY_V1_8821C \
+ (BIT_MASK_MGQ_PGBNDY_V1_8821C << BIT_SHIFT_MGQ_PGBNDY_V1_8821C)
+#define BIT_CLEAR_MGQ_PGBNDY_V1_8821C(x) ((x) & (~BITS_MGQ_PGBNDY_V1_8821C))
+#define BIT_GET_MGQ_PGBNDY_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8821C) & BIT_MASK_MGQ_PGBNDY_V1_8821C)
+#define BIT_SET_MGQ_PGBNDY_V1_8821C(x, v) \
+ (BIT_CLEAR_MGQ_PGBNDY_V1_8821C(x) | BIT_MGQ_PGBNDY_V1_8821C(v))
/* 2 REG_TXRPT_CTRL_8821C */
#define BIT_SHIFT_TRXRPT_TIMER_TH_8821C 24
#define BIT_MASK_TRXRPT_TIMER_TH_8821C 0xff
-#define BIT_TRXRPT_TIMER_TH_8821C(x) (((x) & BIT_MASK_TRXRPT_TIMER_TH_8821C) << BIT_SHIFT_TRXRPT_TIMER_TH_8821C)
-#define BIT_GET_TRXRPT_TIMER_TH_8821C(x) (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8821C) & BIT_MASK_TRXRPT_TIMER_TH_8821C)
-
+#define BIT_TRXRPT_TIMER_TH_8821C(x) \
+ (((x) & BIT_MASK_TRXRPT_TIMER_TH_8821C) \
+ << BIT_SHIFT_TRXRPT_TIMER_TH_8821C)
+#define BITS_TRXRPT_TIMER_TH_8821C \
+ (BIT_MASK_TRXRPT_TIMER_TH_8821C << BIT_SHIFT_TRXRPT_TIMER_TH_8821C)
+#define BIT_CLEAR_TRXRPT_TIMER_TH_8821C(x) ((x) & (~BITS_TRXRPT_TIMER_TH_8821C))
+#define BIT_GET_TRXRPT_TIMER_TH_8821C(x) \
+ (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8821C) & \
+ BIT_MASK_TRXRPT_TIMER_TH_8821C)
+#define BIT_SET_TRXRPT_TIMER_TH_8821C(x, v) \
+ (BIT_CLEAR_TRXRPT_TIMER_TH_8821C(x) | BIT_TRXRPT_TIMER_TH_8821C(v))
#define BIT_SHIFT_TRXRPT_LEN_TH_8821C 16
#define BIT_MASK_TRXRPT_LEN_TH_8821C 0xff
-#define BIT_TRXRPT_LEN_TH_8821C(x) (((x) & BIT_MASK_TRXRPT_LEN_TH_8821C) << BIT_SHIFT_TRXRPT_LEN_TH_8821C)
-#define BIT_GET_TRXRPT_LEN_TH_8821C(x) (((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8821C) & BIT_MASK_TRXRPT_LEN_TH_8821C)
-
+#define BIT_TRXRPT_LEN_TH_8821C(x) \
+ (((x) & BIT_MASK_TRXRPT_LEN_TH_8821C) << BIT_SHIFT_TRXRPT_LEN_TH_8821C)
+#define BITS_TRXRPT_LEN_TH_8821C \
+ (BIT_MASK_TRXRPT_LEN_TH_8821C << BIT_SHIFT_TRXRPT_LEN_TH_8821C)
+#define BIT_CLEAR_TRXRPT_LEN_TH_8821C(x) ((x) & (~BITS_TRXRPT_LEN_TH_8821C))
+#define BIT_GET_TRXRPT_LEN_TH_8821C(x) \
+ (((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8821C) & BIT_MASK_TRXRPT_LEN_TH_8821C)
+#define BIT_SET_TRXRPT_LEN_TH_8821C(x, v) \
+ (BIT_CLEAR_TRXRPT_LEN_TH_8821C(x) | BIT_TRXRPT_LEN_TH_8821C(v))
#define BIT_SHIFT_TRXRPT_READ_PTR_8821C 8
#define BIT_MASK_TRXRPT_READ_PTR_8821C 0xff
-#define BIT_TRXRPT_READ_PTR_8821C(x) (((x) & BIT_MASK_TRXRPT_READ_PTR_8821C) << BIT_SHIFT_TRXRPT_READ_PTR_8821C)
-#define BIT_GET_TRXRPT_READ_PTR_8821C(x) (((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8821C) & BIT_MASK_TRXRPT_READ_PTR_8821C)
-
+#define BIT_TRXRPT_READ_PTR_8821C(x) \
+ (((x) & BIT_MASK_TRXRPT_READ_PTR_8821C) \
+ << BIT_SHIFT_TRXRPT_READ_PTR_8821C)
+#define BITS_TRXRPT_READ_PTR_8821C \
+ (BIT_MASK_TRXRPT_READ_PTR_8821C << BIT_SHIFT_TRXRPT_READ_PTR_8821C)
+#define BIT_CLEAR_TRXRPT_READ_PTR_8821C(x) ((x) & (~BITS_TRXRPT_READ_PTR_8821C))
+#define BIT_GET_TRXRPT_READ_PTR_8821C(x) \
+ (((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8821C) & \
+ BIT_MASK_TRXRPT_READ_PTR_8821C)
+#define BIT_SET_TRXRPT_READ_PTR_8821C(x, v) \
+ (BIT_CLEAR_TRXRPT_READ_PTR_8821C(x) | BIT_TRXRPT_READ_PTR_8821C(v))
#define BIT_SHIFT_TRXRPT_WRITE_PTR_8821C 0
#define BIT_MASK_TRXRPT_WRITE_PTR_8821C 0xff
-#define BIT_TRXRPT_WRITE_PTR_8821C(x) (((x) & BIT_MASK_TRXRPT_WRITE_PTR_8821C) << BIT_SHIFT_TRXRPT_WRITE_PTR_8821C)
-#define BIT_GET_TRXRPT_WRITE_PTR_8821C(x) (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8821C) & BIT_MASK_TRXRPT_WRITE_PTR_8821C)
-
+#define BIT_TRXRPT_WRITE_PTR_8821C(x) \
+ (((x) & BIT_MASK_TRXRPT_WRITE_PTR_8821C) \
+ << BIT_SHIFT_TRXRPT_WRITE_PTR_8821C)
+#define BITS_TRXRPT_WRITE_PTR_8821C \
+ (BIT_MASK_TRXRPT_WRITE_PTR_8821C << BIT_SHIFT_TRXRPT_WRITE_PTR_8821C)
+#define BIT_CLEAR_TRXRPT_WRITE_PTR_8821C(x) \
+ ((x) & (~BITS_TRXRPT_WRITE_PTR_8821C))
+#define BIT_GET_TRXRPT_WRITE_PTR_8821C(x) \
+ (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8821C) & \
+ BIT_MASK_TRXRPT_WRITE_PTR_8821C)
+#define BIT_SET_TRXRPT_WRITE_PTR_8821C(x, v) \
+ (BIT_CLEAR_TRXRPT_WRITE_PTR_8821C(x) | BIT_TRXRPT_WRITE_PTR_8821C(v))
/* 2 REG_INIRTS_RATE_SEL_8821C */
#define BIT_LEAG_RTS_BW_DUP_8821C BIT(5)
@@ -5456,102 +10083,255 @@
#define BIT_SHIFT_BASIC_CFEND_RATE_8821C 0
#define BIT_MASK_BASIC_CFEND_RATE_8821C 0x1f
-#define BIT_BASIC_CFEND_RATE_8821C(x) (((x) & BIT_MASK_BASIC_CFEND_RATE_8821C) << BIT_SHIFT_BASIC_CFEND_RATE_8821C)
-#define BIT_GET_BASIC_CFEND_RATE_8821C(x) (((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8821C) & BIT_MASK_BASIC_CFEND_RATE_8821C)
-
+#define BIT_BASIC_CFEND_RATE_8821C(x) \
+ (((x) & BIT_MASK_BASIC_CFEND_RATE_8821C) \
+ << BIT_SHIFT_BASIC_CFEND_RATE_8821C)
+#define BITS_BASIC_CFEND_RATE_8821C \
+ (BIT_MASK_BASIC_CFEND_RATE_8821C << BIT_SHIFT_BASIC_CFEND_RATE_8821C)
+#define BIT_CLEAR_BASIC_CFEND_RATE_8821C(x) \
+ ((x) & (~BITS_BASIC_CFEND_RATE_8821C))
+#define BIT_GET_BASIC_CFEND_RATE_8821C(x) \
+ (((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8821C) & \
+ BIT_MASK_BASIC_CFEND_RATE_8821C)
+#define BIT_SET_BASIC_CFEND_RATE_8821C(x, v) \
+ (BIT_CLEAR_BASIC_CFEND_RATE_8821C(x) | BIT_BASIC_CFEND_RATE_8821C(v))
/* 2 REG_STBC_CFEND_RATE_8821C */
#define BIT_SHIFT_STBC_CFEND_RATE_8821C 0
#define BIT_MASK_STBC_CFEND_RATE_8821C 0x1f
-#define BIT_STBC_CFEND_RATE_8821C(x) (((x) & BIT_MASK_STBC_CFEND_RATE_8821C) << BIT_SHIFT_STBC_CFEND_RATE_8821C)
-#define BIT_GET_STBC_CFEND_RATE_8821C(x) (((x) >> BIT_SHIFT_STBC_CFEND_RATE_8821C) & BIT_MASK_STBC_CFEND_RATE_8821C)
-
+#define BIT_STBC_CFEND_RATE_8821C(x) \
+ (((x) & BIT_MASK_STBC_CFEND_RATE_8821C) \
+ << BIT_SHIFT_STBC_CFEND_RATE_8821C)
+#define BITS_STBC_CFEND_RATE_8821C \
+ (BIT_MASK_STBC_CFEND_RATE_8821C << BIT_SHIFT_STBC_CFEND_RATE_8821C)
+#define BIT_CLEAR_STBC_CFEND_RATE_8821C(x) ((x) & (~BITS_STBC_CFEND_RATE_8821C))
+#define BIT_GET_STBC_CFEND_RATE_8821C(x) \
+ (((x) >> BIT_SHIFT_STBC_CFEND_RATE_8821C) & \
+ BIT_MASK_STBC_CFEND_RATE_8821C)
+#define BIT_SET_STBC_CFEND_RATE_8821C(x, v) \
+ (BIT_CLEAR_STBC_CFEND_RATE_8821C(x) | BIT_STBC_CFEND_RATE_8821C(v))
/* 2 REG_DATA_SC_8821C */
#define BIT_SHIFT_TXSC_40M_8821C 4
#define BIT_MASK_TXSC_40M_8821C 0xf
-#define BIT_TXSC_40M_8821C(x) (((x) & BIT_MASK_TXSC_40M_8821C) << BIT_SHIFT_TXSC_40M_8821C)
-#define BIT_GET_TXSC_40M_8821C(x) (((x) >> BIT_SHIFT_TXSC_40M_8821C) & BIT_MASK_TXSC_40M_8821C)
-
+#define BIT_TXSC_40M_8821C(x) \
+ (((x) & BIT_MASK_TXSC_40M_8821C) << BIT_SHIFT_TXSC_40M_8821C)
+#define BITS_TXSC_40M_8821C \
+ (BIT_MASK_TXSC_40M_8821C << BIT_SHIFT_TXSC_40M_8821C)
+#define BIT_CLEAR_TXSC_40M_8821C(x) ((x) & (~BITS_TXSC_40M_8821C))
+#define BIT_GET_TXSC_40M_8821C(x) \
+ (((x) >> BIT_SHIFT_TXSC_40M_8821C) & BIT_MASK_TXSC_40M_8821C)
+#define BIT_SET_TXSC_40M_8821C(x, v) \
+ (BIT_CLEAR_TXSC_40M_8821C(x) | BIT_TXSC_40M_8821C(v))
#define BIT_SHIFT_TXSC_20M_8821C 0
#define BIT_MASK_TXSC_20M_8821C 0xf
-#define BIT_TXSC_20M_8821C(x) (((x) & BIT_MASK_TXSC_20M_8821C) << BIT_SHIFT_TXSC_20M_8821C)
-#define BIT_GET_TXSC_20M_8821C(x) (((x) >> BIT_SHIFT_TXSC_20M_8821C) & BIT_MASK_TXSC_20M_8821C)
-
+#define BIT_TXSC_20M_8821C(x) \
+ (((x) & BIT_MASK_TXSC_20M_8821C) << BIT_SHIFT_TXSC_20M_8821C)
+#define BITS_TXSC_20M_8821C \
+ (BIT_MASK_TXSC_20M_8821C << BIT_SHIFT_TXSC_20M_8821C)
+#define BIT_CLEAR_TXSC_20M_8821C(x) ((x) & (~BITS_TXSC_20M_8821C))
+#define BIT_GET_TXSC_20M_8821C(x) \
+ (((x) >> BIT_SHIFT_TXSC_20M_8821C) & BIT_MASK_TXSC_20M_8821C)
+#define BIT_SET_TXSC_20M_8821C(x, v) \
+ (BIT_CLEAR_TXSC_20M_8821C(x) | BIT_TXSC_20M_8821C(v))
/* 2 REG_MACID_SLEEP3_8821C */
#define BIT_SHIFT_MACID127_96_PKTSLEEP_8821C 0
#define BIT_MASK_MACID127_96_PKTSLEEP_8821C 0xffffffffL
-#define BIT_MACID127_96_PKTSLEEP_8821C(x) (((x) & BIT_MASK_MACID127_96_PKTSLEEP_8821C) << BIT_SHIFT_MACID127_96_PKTSLEEP_8821C)
-#define BIT_GET_MACID127_96_PKTSLEEP_8821C(x) (((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP_8821C) & BIT_MASK_MACID127_96_PKTSLEEP_8821C)
-
+#define BIT_MACID127_96_PKTSLEEP_8821C(x) \
+ (((x) & BIT_MASK_MACID127_96_PKTSLEEP_8821C) \
+ << BIT_SHIFT_MACID127_96_PKTSLEEP_8821C)
+#define BITS_MACID127_96_PKTSLEEP_8821C \
+ (BIT_MASK_MACID127_96_PKTSLEEP_8821C \
+ << BIT_SHIFT_MACID127_96_PKTSLEEP_8821C)
+#define BIT_CLEAR_MACID127_96_PKTSLEEP_8821C(x) \
+ ((x) & (~BITS_MACID127_96_PKTSLEEP_8821C))
+#define BIT_GET_MACID127_96_PKTSLEEP_8821C(x) \
+ (((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP_8821C) & \
+ BIT_MASK_MACID127_96_PKTSLEEP_8821C)
+#define BIT_SET_MACID127_96_PKTSLEEP_8821C(x, v) \
+ (BIT_CLEAR_MACID127_96_PKTSLEEP_8821C(x) | \
+ BIT_MACID127_96_PKTSLEEP_8821C(v))
/* 2 REG_MACID_SLEEP1_8821C */
#define BIT_SHIFT_MACID63_32_PKTSLEEP_8821C 0
#define BIT_MASK_MACID63_32_PKTSLEEP_8821C 0xffffffffL
-#define BIT_MACID63_32_PKTSLEEP_8821C(x) (((x) & BIT_MASK_MACID63_32_PKTSLEEP_8821C) << BIT_SHIFT_MACID63_32_PKTSLEEP_8821C)
-#define BIT_GET_MACID63_32_PKTSLEEP_8821C(x) (((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP_8821C) & BIT_MASK_MACID63_32_PKTSLEEP_8821C)
-
+#define BIT_MACID63_32_PKTSLEEP_8821C(x) \
+ (((x) & BIT_MASK_MACID63_32_PKTSLEEP_8821C) \
+ << BIT_SHIFT_MACID63_32_PKTSLEEP_8821C)
+#define BITS_MACID63_32_PKTSLEEP_8821C \
+ (BIT_MASK_MACID63_32_PKTSLEEP_8821C \
+ << BIT_SHIFT_MACID63_32_PKTSLEEP_8821C)
+#define BIT_CLEAR_MACID63_32_PKTSLEEP_8821C(x) \
+ ((x) & (~BITS_MACID63_32_PKTSLEEP_8821C))
+#define BIT_GET_MACID63_32_PKTSLEEP_8821C(x) \
+ (((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP_8821C) & \
+ BIT_MASK_MACID63_32_PKTSLEEP_8821C)
+#define BIT_SET_MACID63_32_PKTSLEEP_8821C(x, v) \
+ (BIT_CLEAR_MACID63_32_PKTSLEEP_8821C(x) | \
+ BIT_MACID63_32_PKTSLEEP_8821C(v))
/* 2 REG_ARFR2_V1_8821C */
-#define BIT_SHIFT_ARFR2_V1_8821C 0
-#define BIT_MASK_ARFR2_V1_8821C 0xffffffffffffffffL
-#define BIT_ARFR2_V1_8821C(x) (((x) & BIT_MASK_ARFR2_V1_8821C) << BIT_SHIFT_ARFR2_V1_8821C)
-#define BIT_GET_ARFR2_V1_8821C(x) (((x) >> BIT_SHIFT_ARFR2_V1_8821C) & BIT_MASK_ARFR2_V1_8821C)
-
+#define BIT_SHIFT_ARFRL2_8821C 0
+#define BIT_MASK_ARFRL2_8821C 0xffffffffL
+#define BIT_ARFRL2_8821C(x) \
+ (((x) & BIT_MASK_ARFRL2_8821C) << BIT_SHIFT_ARFRL2_8821C)
+#define BITS_ARFRL2_8821C (BIT_MASK_ARFRL2_8821C << BIT_SHIFT_ARFRL2_8821C)
+#define BIT_CLEAR_ARFRL2_8821C(x) ((x) & (~BITS_ARFRL2_8821C))
+#define BIT_GET_ARFRL2_8821C(x) \
+ (((x) >> BIT_SHIFT_ARFRL2_8821C) & BIT_MASK_ARFRL2_8821C)
+#define BIT_SET_ARFRL2_8821C(x, v) \
+ (BIT_CLEAR_ARFRL2_8821C(x) | BIT_ARFRL2_8821C(v))
+
+/* 2 REG_ARFRH2_V1_8821C */
+
+#define BIT_SHIFT_ARFRH2_8821C 0
+#define BIT_MASK_ARFRH2_8821C 0xffffffffL
+#define BIT_ARFRH2_8821C(x) \
+ (((x) & BIT_MASK_ARFRH2_8821C) << BIT_SHIFT_ARFRH2_8821C)
+#define BITS_ARFRH2_8821C (BIT_MASK_ARFRH2_8821C << BIT_SHIFT_ARFRH2_8821C)
+#define BIT_CLEAR_ARFRH2_8821C(x) ((x) & (~BITS_ARFRH2_8821C))
+#define BIT_GET_ARFRH2_8821C(x) \
+ (((x) >> BIT_SHIFT_ARFRH2_8821C) & BIT_MASK_ARFRH2_8821C)
+#define BIT_SET_ARFRH2_8821C(x, v) \
+ (BIT_CLEAR_ARFRH2_8821C(x) | BIT_ARFRH2_8821C(v))
/* 2 REG_ARFR3_V1_8821C */
-#define BIT_SHIFT_ARFR3_V1_8821C 0
-#define BIT_MASK_ARFR3_V1_8821C 0xffffffffffffffffL
-#define BIT_ARFR3_V1_8821C(x) (((x) & BIT_MASK_ARFR3_V1_8821C) << BIT_SHIFT_ARFR3_V1_8821C)
-#define BIT_GET_ARFR3_V1_8821C(x) (((x) >> BIT_SHIFT_ARFR3_V1_8821C) & BIT_MASK_ARFR3_V1_8821C)
-
+#define BIT_SHIFT_ARFRL3_8821C 0
+#define BIT_MASK_ARFRL3_8821C 0xffffffffL
+#define BIT_ARFRL3_8821C(x) \
+ (((x) & BIT_MASK_ARFRL3_8821C) << BIT_SHIFT_ARFRL3_8821C)
+#define BITS_ARFRL3_8821C (BIT_MASK_ARFRL3_8821C << BIT_SHIFT_ARFRL3_8821C)
+#define BIT_CLEAR_ARFRL3_8821C(x) ((x) & (~BITS_ARFRL3_8821C))
+#define BIT_GET_ARFRL3_8821C(x) \
+ (((x) >> BIT_SHIFT_ARFRL3_8821C) & BIT_MASK_ARFRL3_8821C)
+#define BIT_SET_ARFRL3_8821C(x, v) \
+ (BIT_CLEAR_ARFRL3_8821C(x) | BIT_ARFRL3_8821C(v))
+
+/* 2 REG_ARFRH3_V1_8821C */
+
+#define BIT_SHIFT_ARFRH3_8821C 0
+#define BIT_MASK_ARFRH3_8821C 0xffffffffL
+#define BIT_ARFRH3_8821C(x) \
+ (((x) & BIT_MASK_ARFRH3_8821C) << BIT_SHIFT_ARFRH3_8821C)
+#define BITS_ARFRH3_8821C (BIT_MASK_ARFRH3_8821C << BIT_SHIFT_ARFRH3_8821C)
+#define BIT_CLEAR_ARFRH3_8821C(x) ((x) & (~BITS_ARFRH3_8821C))
+#define BIT_GET_ARFRH3_8821C(x) \
+ (((x) >> BIT_SHIFT_ARFRH3_8821C) & BIT_MASK_ARFRH3_8821C)
+#define BIT_SET_ARFRH3_8821C(x, v) \
+ (BIT_CLEAR_ARFRH3_8821C(x) | BIT_ARFRH3_8821C(v))
/* 2 REG_ARFR4_8821C */
-#define BIT_SHIFT_ARFR4_8821C 0
-#define BIT_MASK_ARFR4_8821C 0xffffffffffffffffL
-#define BIT_ARFR4_8821C(x) (((x) & BIT_MASK_ARFR4_8821C) << BIT_SHIFT_ARFR4_8821C)
-#define BIT_GET_ARFR4_8821C(x) (((x) >> BIT_SHIFT_ARFR4_8821C) & BIT_MASK_ARFR4_8821C)
-
+#define BIT_SHIFT_ARFRL4_8821C 0
+#define BIT_MASK_ARFRL4_8821C 0xffffffffL
+#define BIT_ARFRL4_8821C(x) \
+ (((x) & BIT_MASK_ARFRL4_8821C) << BIT_SHIFT_ARFRL4_8821C)
+#define BITS_ARFRL4_8821C (BIT_MASK_ARFRL4_8821C << BIT_SHIFT_ARFRL4_8821C)
+#define BIT_CLEAR_ARFRL4_8821C(x) ((x) & (~BITS_ARFRL4_8821C))
+#define BIT_GET_ARFRL4_8821C(x) \
+ (((x) >> BIT_SHIFT_ARFRL4_8821C) & BIT_MASK_ARFRL4_8821C)
+#define BIT_SET_ARFRL4_8821C(x, v) \
+ (BIT_CLEAR_ARFRL4_8821C(x) | BIT_ARFRL4_8821C(v))
+
+/* 2 REG_ARFRH4_8821C */
+
+#define BIT_SHIFT_ARFRH4_8821C 0
+#define BIT_MASK_ARFRH4_8821C 0xffffffffL
+#define BIT_ARFRH4_8821C(x) \
+ (((x) & BIT_MASK_ARFRH4_8821C) << BIT_SHIFT_ARFRH4_8821C)
+#define BITS_ARFRH4_8821C (BIT_MASK_ARFRH4_8821C << BIT_SHIFT_ARFRH4_8821C)
+#define BIT_CLEAR_ARFRH4_8821C(x) ((x) & (~BITS_ARFRH4_8821C))
+#define BIT_GET_ARFRH4_8821C(x) \
+ (((x) >> BIT_SHIFT_ARFRH4_8821C) & BIT_MASK_ARFRH4_8821C)
+#define BIT_SET_ARFRH4_8821C(x, v) \
+ (BIT_CLEAR_ARFRH4_8821C(x) | BIT_ARFRH4_8821C(v))
/* 2 REG_ARFR5_8821C */
-#define BIT_SHIFT_ARFR5_8821C 0
-#define BIT_MASK_ARFR5_8821C 0xffffffffffffffffL
-#define BIT_ARFR5_8821C(x) (((x) & BIT_MASK_ARFR5_8821C) << BIT_SHIFT_ARFR5_8821C)
-#define BIT_GET_ARFR5_8821C(x) (((x) >> BIT_SHIFT_ARFR5_8821C) & BIT_MASK_ARFR5_8821C)
-
+#define BIT_SHIFT_ARFRL5_8821C 0
+#define BIT_MASK_ARFRL5_8821C 0xffffffffL
+#define BIT_ARFRL5_8821C(x) \
+ (((x) & BIT_MASK_ARFRL5_8821C) << BIT_SHIFT_ARFRL5_8821C)
+#define BITS_ARFRL5_8821C (BIT_MASK_ARFRL5_8821C << BIT_SHIFT_ARFRL5_8821C)
+#define BIT_CLEAR_ARFRL5_8821C(x) ((x) & (~BITS_ARFRL5_8821C))
+#define BIT_GET_ARFRL5_8821C(x) \
+ (((x) >> BIT_SHIFT_ARFRL5_8821C) & BIT_MASK_ARFRL5_8821C)
+#define BIT_SET_ARFRL5_8821C(x, v) \
+ (BIT_CLEAR_ARFRL5_8821C(x) | BIT_ARFRL5_8821C(v))
+
+/* 2 REG_ARFRH5_8821C */
+
+#define BIT_SHIFT_ARFRH5_8821C 0
+#define BIT_MASK_ARFRH5_8821C 0xffffffffL
+#define BIT_ARFRH5_8821C(x) \
+ (((x) & BIT_MASK_ARFRH5_8821C) << BIT_SHIFT_ARFRH5_8821C)
+#define BITS_ARFRH5_8821C (BIT_MASK_ARFRH5_8821C << BIT_SHIFT_ARFRH5_8821C)
+#define BIT_CLEAR_ARFRH5_8821C(x) ((x) & (~BITS_ARFRH5_8821C))
+#define BIT_GET_ARFRH5_8821C(x) \
+ (((x) >> BIT_SHIFT_ARFRH5_8821C) & BIT_MASK_ARFRH5_8821C)
+#define BIT_SET_ARFRH5_8821C(x, v) \
+ (BIT_CLEAR_ARFRH5_8821C(x) | BIT_ARFRH5_8821C(v))
/* 2 REG_TXRPT_START_OFFSET_8821C */
#define BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8821C 24
#define BIT_MASK_R_MUTAB_TXRPT_OFFSET_8821C 0xff
-#define BIT_R_MUTAB_TXRPT_OFFSET_8821C(x) (((x) & BIT_MASK_R_MUTAB_TXRPT_OFFSET_8821C) << BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8821C)
-#define BIT_GET_R_MUTAB_TXRPT_OFFSET_8821C(x) (((x) >> BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8821C) & BIT_MASK_R_MUTAB_TXRPT_OFFSET_8821C)
+#define BIT_R_MUTAB_TXRPT_OFFSET_8821C(x) \
+ (((x) & BIT_MASK_R_MUTAB_TXRPT_OFFSET_8821C) \
+ << BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8821C)
+#define BITS_R_MUTAB_TXRPT_OFFSET_8821C \
+ (BIT_MASK_R_MUTAB_TXRPT_OFFSET_8821C \
+ << BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8821C)
+#define BIT_CLEAR_R_MUTAB_TXRPT_OFFSET_8821C(x) \
+ ((x) & (~BITS_R_MUTAB_TXRPT_OFFSET_8821C))
+#define BIT_GET_R_MUTAB_TXRPT_OFFSET_8821C(x) \
+ (((x) >> BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8821C) & \
+ BIT_MASK_R_MUTAB_TXRPT_OFFSET_8821C)
+#define BIT_SET_R_MUTAB_TXRPT_OFFSET_8821C(x, v) \
+ (BIT_CLEAR_R_MUTAB_TXRPT_OFFSET_8821C(x) | \
+ BIT_R_MUTAB_TXRPT_OFFSET_8821C(v))
#define BIT__R_RPTFIFO_1K_8821C BIT(16)
#define BIT_SHIFT_MACID_CTRL_OFFSET_8821C 8
#define BIT_MASK_MACID_CTRL_OFFSET_8821C 0xff
-#define BIT_MACID_CTRL_OFFSET_8821C(x) (((x) & BIT_MASK_MACID_CTRL_OFFSET_8821C) << BIT_SHIFT_MACID_CTRL_OFFSET_8821C)
-#define BIT_GET_MACID_CTRL_OFFSET_8821C(x) (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_8821C) & BIT_MASK_MACID_CTRL_OFFSET_8821C)
-
+#define BIT_MACID_CTRL_OFFSET_8821C(x) \
+ (((x) & BIT_MASK_MACID_CTRL_OFFSET_8821C) \
+ << BIT_SHIFT_MACID_CTRL_OFFSET_8821C)
+#define BITS_MACID_CTRL_OFFSET_8821C \
+ (BIT_MASK_MACID_CTRL_OFFSET_8821C << BIT_SHIFT_MACID_CTRL_OFFSET_8821C)
+#define BIT_CLEAR_MACID_CTRL_OFFSET_8821C(x) \
+ ((x) & (~BITS_MACID_CTRL_OFFSET_8821C))
+#define BIT_GET_MACID_CTRL_OFFSET_8821C(x) \
+ (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_8821C) & \
+ BIT_MASK_MACID_CTRL_OFFSET_8821C)
+#define BIT_SET_MACID_CTRL_OFFSET_8821C(x, v) \
+ (BIT_CLEAR_MACID_CTRL_OFFSET_8821C(x) | BIT_MACID_CTRL_OFFSET_8821C(v))
#define BIT_SHIFT_AMPDU_TXRPT_OFFSET_8821C 0
#define BIT_MASK_AMPDU_TXRPT_OFFSET_8821C 0xff
-#define BIT_AMPDU_TXRPT_OFFSET_8821C(x) (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_8821C) << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8821C)
-#define BIT_GET_AMPDU_TXRPT_OFFSET_8821C(x) (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_8821C) & BIT_MASK_AMPDU_TXRPT_OFFSET_8821C)
-
-
-/* 2 REG_NOT_VALID_8821C */
+#define BIT_AMPDU_TXRPT_OFFSET_8821C(x) \
+ (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_8821C) \
+ << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8821C)
+#define BITS_AMPDU_TXRPT_OFFSET_8821C \
+ (BIT_MASK_AMPDU_TXRPT_OFFSET_8821C \
+ << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8821C)
+#define BIT_CLEAR_AMPDU_TXRPT_OFFSET_8821C(x) \
+ ((x) & (~BITS_AMPDU_TXRPT_OFFSET_8821C))
+#define BIT_GET_AMPDU_TXRPT_OFFSET_8821C(x) \
+ (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_8821C) & \
+ BIT_MASK_AMPDU_TXRPT_OFFSET_8821C)
+#define BIT_SET_AMPDU_TXRPT_OFFSET_8821C(x, v) \
+ (BIT_CLEAR_AMPDU_TXRPT_OFFSET_8821C(x) | \
+ BIT_AMPDU_TXRPT_OFFSET_8821C(v))
/* 2 REG_POWER_STAGE1_8821C */
#define BIT_PTA_WL_PRI_MASK_CPU_MGQ_8821C BIT(31)
@@ -5565,25 +10345,44 @@
#define BIT_SHIFT_POWER_STAGE1_8821C 0
#define BIT_MASK_POWER_STAGE1_8821C 0xffffff
-#define BIT_POWER_STAGE1_8821C(x) (((x) & BIT_MASK_POWER_STAGE1_8821C) << BIT_SHIFT_POWER_STAGE1_8821C)
-#define BIT_GET_POWER_STAGE1_8821C(x) (((x) >> BIT_SHIFT_POWER_STAGE1_8821C) & BIT_MASK_POWER_STAGE1_8821C)
-
+#define BIT_POWER_STAGE1_8821C(x) \
+ (((x) & BIT_MASK_POWER_STAGE1_8821C) << BIT_SHIFT_POWER_STAGE1_8821C)
+#define BITS_POWER_STAGE1_8821C \
+ (BIT_MASK_POWER_STAGE1_8821C << BIT_SHIFT_POWER_STAGE1_8821C)
+#define BIT_CLEAR_POWER_STAGE1_8821C(x) ((x) & (~BITS_POWER_STAGE1_8821C))
+#define BIT_GET_POWER_STAGE1_8821C(x) \
+ (((x) >> BIT_SHIFT_POWER_STAGE1_8821C) & BIT_MASK_POWER_STAGE1_8821C)
+#define BIT_SET_POWER_STAGE1_8821C(x, v) \
+ (BIT_CLEAR_POWER_STAGE1_8821C(x) | BIT_POWER_STAGE1_8821C(v))
/* 2 REG_POWER_STAGE2_8821C */
#define BIT__R_CTRL_PKT_POW_ADJ_8821C BIT(24)
#define BIT_SHIFT_POWER_STAGE2_8821C 0
#define BIT_MASK_POWER_STAGE2_8821C 0xffffff
-#define BIT_POWER_STAGE2_8821C(x) (((x) & BIT_MASK_POWER_STAGE2_8821C) << BIT_SHIFT_POWER_STAGE2_8821C)
-#define BIT_GET_POWER_STAGE2_8821C(x) (((x) >> BIT_SHIFT_POWER_STAGE2_8821C) & BIT_MASK_POWER_STAGE2_8821C)
-
+#define BIT_POWER_STAGE2_8821C(x) \
+ (((x) & BIT_MASK_POWER_STAGE2_8821C) << BIT_SHIFT_POWER_STAGE2_8821C)
+#define BITS_POWER_STAGE2_8821C \
+ (BIT_MASK_POWER_STAGE2_8821C << BIT_SHIFT_POWER_STAGE2_8821C)
+#define BIT_CLEAR_POWER_STAGE2_8821C(x) ((x) & (~BITS_POWER_STAGE2_8821C))
+#define BIT_GET_POWER_STAGE2_8821C(x) \
+ (((x) >> BIT_SHIFT_POWER_STAGE2_8821C) & BIT_MASK_POWER_STAGE2_8821C)
+#define BIT_SET_POWER_STAGE2_8821C(x, v) \
+ (BIT_CLEAR_POWER_STAGE2_8821C(x) | BIT_POWER_STAGE2_8821C(v))
/* 2 REG_SW_AMPDU_BURST_MODE_CTRL_8821C */
#define BIT_SHIFT_PAD_NUM_THRES_8821C 24
#define BIT_MASK_PAD_NUM_THRES_8821C 0x3f
-#define BIT_PAD_NUM_THRES_8821C(x) (((x) & BIT_MASK_PAD_NUM_THRES_8821C) << BIT_SHIFT_PAD_NUM_THRES_8821C)
-#define BIT_GET_PAD_NUM_THRES_8821C(x) (((x) >> BIT_SHIFT_PAD_NUM_THRES_8821C) & BIT_MASK_PAD_NUM_THRES_8821C)
+#define BIT_PAD_NUM_THRES_8821C(x) \
+ (((x) & BIT_MASK_PAD_NUM_THRES_8821C) << BIT_SHIFT_PAD_NUM_THRES_8821C)
+#define BITS_PAD_NUM_THRES_8821C \
+ (BIT_MASK_PAD_NUM_THRES_8821C << BIT_SHIFT_PAD_NUM_THRES_8821C)
+#define BIT_CLEAR_PAD_NUM_THRES_8821C(x) ((x) & (~BITS_PAD_NUM_THRES_8821C))
+#define BIT_GET_PAD_NUM_THRES_8821C(x) \
+ (((x) >> BIT_SHIFT_PAD_NUM_THRES_8821C) & BIT_MASK_PAD_NUM_THRES_8821C)
+#define BIT_SET_PAD_NUM_THRES_8821C(x, v) \
+ (BIT_CLEAR_PAD_NUM_THRES_8821C(x) | BIT_PAD_NUM_THRES_8821C(v))
#define BIT_R_DMA_THIS_QUEUE_BK_8821C BIT(23)
#define BIT_R_DMA_THIS_QUEUE_BE_8821C BIT(22)
@@ -5592,16 +10391,32 @@
#define BIT_SHIFT_R_TOTAL_LEN_TH_8821C 8
#define BIT_MASK_R_TOTAL_LEN_TH_8821C 0xfff
-#define BIT_R_TOTAL_LEN_TH_8821C(x) (((x) & BIT_MASK_R_TOTAL_LEN_TH_8821C) << BIT_SHIFT_R_TOTAL_LEN_TH_8821C)
-#define BIT_GET_R_TOTAL_LEN_TH_8821C(x) (((x) >> BIT_SHIFT_R_TOTAL_LEN_TH_8821C) & BIT_MASK_R_TOTAL_LEN_TH_8821C)
+#define BIT_R_TOTAL_LEN_TH_8821C(x) \
+ (((x) & BIT_MASK_R_TOTAL_LEN_TH_8821C) \
+ << BIT_SHIFT_R_TOTAL_LEN_TH_8821C)
+#define BITS_R_TOTAL_LEN_TH_8821C \
+ (BIT_MASK_R_TOTAL_LEN_TH_8821C << BIT_SHIFT_R_TOTAL_LEN_TH_8821C)
+#define BIT_CLEAR_R_TOTAL_LEN_TH_8821C(x) ((x) & (~BITS_R_TOTAL_LEN_TH_8821C))
+#define BIT_GET_R_TOTAL_LEN_TH_8821C(x) \
+ (((x) >> BIT_SHIFT_R_TOTAL_LEN_TH_8821C) & \
+ BIT_MASK_R_TOTAL_LEN_TH_8821C)
+#define BIT_SET_R_TOTAL_LEN_TH_8821C(x, v) \
+ (BIT_CLEAR_R_TOTAL_LEN_TH_8821C(x) | BIT_R_TOTAL_LEN_TH_8821C(v))
#define BIT_EN_NEW_EARLY_8821C BIT(7)
#define BIT_PRE_TX_CMD_8821C BIT(6)
#define BIT_SHIFT_NUM_SCL_EN_8821C 4
#define BIT_MASK_NUM_SCL_EN_8821C 0x3
-#define BIT_NUM_SCL_EN_8821C(x) (((x) & BIT_MASK_NUM_SCL_EN_8821C) << BIT_SHIFT_NUM_SCL_EN_8821C)
-#define BIT_GET_NUM_SCL_EN_8821C(x) (((x) >> BIT_SHIFT_NUM_SCL_EN_8821C) & BIT_MASK_NUM_SCL_EN_8821C)
+#define BIT_NUM_SCL_EN_8821C(x) \
+ (((x) & BIT_MASK_NUM_SCL_EN_8821C) << BIT_SHIFT_NUM_SCL_EN_8821C)
+#define BITS_NUM_SCL_EN_8821C \
+ (BIT_MASK_NUM_SCL_EN_8821C << BIT_SHIFT_NUM_SCL_EN_8821C)
+#define BIT_CLEAR_NUM_SCL_EN_8821C(x) ((x) & (~BITS_NUM_SCL_EN_8821C))
+#define BIT_GET_NUM_SCL_EN_8821C(x) \
+ (((x) >> BIT_SHIFT_NUM_SCL_EN_8821C) & BIT_MASK_NUM_SCL_EN_8821C)
+#define BIT_SET_NUM_SCL_EN_8821C(x, v) \
+ (BIT_CLEAR_NUM_SCL_EN_8821C(x) | BIT_NUM_SCL_EN_8821C(v))
#define BIT_BK_EN_8821C BIT(3)
#define BIT_BE_EN_8821C BIT(2)
@@ -5612,43 +10427,86 @@
#define BIT_SHIFT_PKT_LIFTIME_BEBK_8821C 16
#define BIT_MASK_PKT_LIFTIME_BEBK_8821C 0xffff
-#define BIT_PKT_LIFTIME_BEBK_8821C(x) (((x) & BIT_MASK_PKT_LIFTIME_BEBK_8821C) << BIT_SHIFT_PKT_LIFTIME_BEBK_8821C)
-#define BIT_GET_PKT_LIFTIME_BEBK_8821C(x) (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8821C) & BIT_MASK_PKT_LIFTIME_BEBK_8821C)
-
+#define BIT_PKT_LIFTIME_BEBK_8821C(x) \
+ (((x) & BIT_MASK_PKT_LIFTIME_BEBK_8821C) \
+ << BIT_SHIFT_PKT_LIFTIME_BEBK_8821C)
+#define BITS_PKT_LIFTIME_BEBK_8821C \
+ (BIT_MASK_PKT_LIFTIME_BEBK_8821C << BIT_SHIFT_PKT_LIFTIME_BEBK_8821C)
+#define BIT_CLEAR_PKT_LIFTIME_BEBK_8821C(x) \
+ ((x) & (~BITS_PKT_LIFTIME_BEBK_8821C))
+#define BIT_GET_PKT_LIFTIME_BEBK_8821C(x) \
+ (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8821C) & \
+ BIT_MASK_PKT_LIFTIME_BEBK_8821C)
+#define BIT_SET_PKT_LIFTIME_BEBK_8821C(x, v) \
+ (BIT_CLEAR_PKT_LIFTIME_BEBK_8821C(x) | BIT_PKT_LIFTIME_BEBK_8821C(v))
#define BIT_SHIFT_PKT_LIFTIME_VOVI_8821C 0
#define BIT_MASK_PKT_LIFTIME_VOVI_8821C 0xffff
-#define BIT_PKT_LIFTIME_VOVI_8821C(x) (((x) & BIT_MASK_PKT_LIFTIME_VOVI_8821C) << BIT_SHIFT_PKT_LIFTIME_VOVI_8821C)
-#define BIT_GET_PKT_LIFTIME_VOVI_8821C(x) (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8821C) & BIT_MASK_PKT_LIFTIME_VOVI_8821C)
-
+#define BIT_PKT_LIFTIME_VOVI_8821C(x) \
+ (((x) & BIT_MASK_PKT_LIFTIME_VOVI_8821C) \
+ << BIT_SHIFT_PKT_LIFTIME_VOVI_8821C)
+#define BITS_PKT_LIFTIME_VOVI_8821C \
+ (BIT_MASK_PKT_LIFTIME_VOVI_8821C << BIT_SHIFT_PKT_LIFTIME_VOVI_8821C)
+#define BIT_CLEAR_PKT_LIFTIME_VOVI_8821C(x) \
+ ((x) & (~BITS_PKT_LIFTIME_VOVI_8821C))
+#define BIT_GET_PKT_LIFTIME_VOVI_8821C(x) \
+ (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8821C) & \
+ BIT_MASK_PKT_LIFTIME_VOVI_8821C)
+#define BIT_SET_PKT_LIFTIME_VOVI_8821C(x, v) \
+ (BIT_CLEAR_PKT_LIFTIME_VOVI_8821C(x) | BIT_PKT_LIFTIME_VOVI_8821C(v))
/* 2 REG_STBC_SETTING_8821C */
#define BIT_SHIFT_CDEND_TXTIME_L_8821C 4
#define BIT_MASK_CDEND_TXTIME_L_8821C 0xf
-#define BIT_CDEND_TXTIME_L_8821C(x) (((x) & BIT_MASK_CDEND_TXTIME_L_8821C) << BIT_SHIFT_CDEND_TXTIME_L_8821C)
-#define BIT_GET_CDEND_TXTIME_L_8821C(x) (((x) >> BIT_SHIFT_CDEND_TXTIME_L_8821C) & BIT_MASK_CDEND_TXTIME_L_8821C)
-
+#define BIT_CDEND_TXTIME_L_8821C(x) \
+ (((x) & BIT_MASK_CDEND_TXTIME_L_8821C) \
+ << BIT_SHIFT_CDEND_TXTIME_L_8821C)
+#define BITS_CDEND_TXTIME_L_8821C \
+ (BIT_MASK_CDEND_TXTIME_L_8821C << BIT_SHIFT_CDEND_TXTIME_L_8821C)
+#define BIT_CLEAR_CDEND_TXTIME_L_8821C(x) ((x) & (~BITS_CDEND_TXTIME_L_8821C))
+#define BIT_GET_CDEND_TXTIME_L_8821C(x) \
+ (((x) >> BIT_SHIFT_CDEND_TXTIME_L_8821C) & \
+ BIT_MASK_CDEND_TXTIME_L_8821C)
+#define BIT_SET_CDEND_TXTIME_L_8821C(x, v) \
+ (BIT_CLEAR_CDEND_TXTIME_L_8821C(x) | BIT_CDEND_TXTIME_L_8821C(v))
#define BIT_SHIFT_NESS_8821C 2
#define BIT_MASK_NESS_8821C 0x3
#define BIT_NESS_8821C(x) (((x) & BIT_MASK_NESS_8821C) << BIT_SHIFT_NESS_8821C)
-#define BIT_GET_NESS_8821C(x) (((x) >> BIT_SHIFT_NESS_8821C) & BIT_MASK_NESS_8821C)
-
+#define BITS_NESS_8821C (BIT_MASK_NESS_8821C << BIT_SHIFT_NESS_8821C)
+#define BIT_CLEAR_NESS_8821C(x) ((x) & (~BITS_NESS_8821C))
+#define BIT_GET_NESS_8821C(x) \
+ (((x) >> BIT_SHIFT_NESS_8821C) & BIT_MASK_NESS_8821C)
+#define BIT_SET_NESS_8821C(x, v) (BIT_CLEAR_NESS_8821C(x) | BIT_NESS_8821C(v))
#define BIT_SHIFT_STBC_CFEND_8821C 0
#define BIT_MASK_STBC_CFEND_8821C 0x3
-#define BIT_STBC_CFEND_8821C(x) (((x) & BIT_MASK_STBC_CFEND_8821C) << BIT_SHIFT_STBC_CFEND_8821C)
-#define BIT_GET_STBC_CFEND_8821C(x) (((x) >> BIT_SHIFT_STBC_CFEND_8821C) & BIT_MASK_STBC_CFEND_8821C)
-
+#define BIT_STBC_CFEND_8821C(x) \
+ (((x) & BIT_MASK_STBC_CFEND_8821C) << BIT_SHIFT_STBC_CFEND_8821C)
+#define BITS_STBC_CFEND_8821C \
+ (BIT_MASK_STBC_CFEND_8821C << BIT_SHIFT_STBC_CFEND_8821C)
+#define BIT_CLEAR_STBC_CFEND_8821C(x) ((x) & (~BITS_STBC_CFEND_8821C))
+#define BIT_GET_STBC_CFEND_8821C(x) \
+ (((x) >> BIT_SHIFT_STBC_CFEND_8821C) & BIT_MASK_STBC_CFEND_8821C)
+#define BIT_SET_STBC_CFEND_8821C(x, v) \
+ (BIT_CLEAR_STBC_CFEND_8821C(x) | BIT_STBC_CFEND_8821C(v))
/* 2 REG_STBC_SETTING2_8821C */
#define BIT_SHIFT_CDEND_TXTIME_H_8821C 0
#define BIT_MASK_CDEND_TXTIME_H_8821C 0x1f
-#define BIT_CDEND_TXTIME_H_8821C(x) (((x) & BIT_MASK_CDEND_TXTIME_H_8821C) << BIT_SHIFT_CDEND_TXTIME_H_8821C)
-#define BIT_GET_CDEND_TXTIME_H_8821C(x) (((x) >> BIT_SHIFT_CDEND_TXTIME_H_8821C) & BIT_MASK_CDEND_TXTIME_H_8821C)
-
+#define BIT_CDEND_TXTIME_H_8821C(x) \
+ (((x) & BIT_MASK_CDEND_TXTIME_H_8821C) \
+ << BIT_SHIFT_CDEND_TXTIME_H_8821C)
+#define BITS_CDEND_TXTIME_H_8821C \
+ (BIT_MASK_CDEND_TXTIME_H_8821C << BIT_SHIFT_CDEND_TXTIME_H_8821C)
+#define BIT_CLEAR_CDEND_TXTIME_H_8821C(x) ((x) & (~BITS_CDEND_TXTIME_H_8821C))
+#define BIT_GET_CDEND_TXTIME_H_8821C(x) \
+ (((x) >> BIT_SHIFT_CDEND_TXTIME_H_8821C) & \
+ BIT_MASK_CDEND_TXTIME_H_8821C)
+#define BIT_SET_CDEND_TXTIME_H_8821C(x, v) \
+ (BIT_CLEAR_CDEND_TXTIME_H_8821C(x) | BIT_CDEND_TXTIME_H_8821C(v))
/* 2 REG_QUEUE_CTRL_8821C */
#define BIT_PTA_EDCCA_EN_8821C BIT(5)
@@ -5665,111 +10523,241 @@
#define BIT_SHIFT_RTS_MAX_AGG_NUM_8821C 24
#define BIT_MASK_RTS_MAX_AGG_NUM_8821C 0x3f
-#define BIT_RTS_MAX_AGG_NUM_8821C(x) (((x) & BIT_MASK_RTS_MAX_AGG_NUM_8821C) << BIT_SHIFT_RTS_MAX_AGG_NUM_8821C)
-#define BIT_GET_RTS_MAX_AGG_NUM_8821C(x) (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8821C) & BIT_MASK_RTS_MAX_AGG_NUM_8821C)
-
+#define BIT_RTS_MAX_AGG_NUM_8821C(x) \
+ (((x) & BIT_MASK_RTS_MAX_AGG_NUM_8821C) \
+ << BIT_SHIFT_RTS_MAX_AGG_NUM_8821C)
+#define BITS_RTS_MAX_AGG_NUM_8821C \
+ (BIT_MASK_RTS_MAX_AGG_NUM_8821C << BIT_SHIFT_RTS_MAX_AGG_NUM_8821C)
+#define BIT_CLEAR_RTS_MAX_AGG_NUM_8821C(x) ((x) & (~BITS_RTS_MAX_AGG_NUM_8821C))
+#define BIT_GET_RTS_MAX_AGG_NUM_8821C(x) \
+ (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8821C) & \
+ BIT_MASK_RTS_MAX_AGG_NUM_8821C)
+#define BIT_SET_RTS_MAX_AGG_NUM_8821C(x, v) \
+ (BIT_CLEAR_RTS_MAX_AGG_NUM_8821C(x) | BIT_RTS_MAX_AGG_NUM_8821C(v))
#define BIT_SHIFT_MAX_AGG_NUM_8821C 16
#define BIT_MASK_MAX_AGG_NUM_8821C 0x3f
-#define BIT_MAX_AGG_NUM_8821C(x) (((x) & BIT_MASK_MAX_AGG_NUM_8821C) << BIT_SHIFT_MAX_AGG_NUM_8821C)
-#define BIT_GET_MAX_AGG_NUM_8821C(x) (((x) >> BIT_SHIFT_MAX_AGG_NUM_8821C) & BIT_MASK_MAX_AGG_NUM_8821C)
-
+#define BIT_MAX_AGG_NUM_8821C(x) \
+ (((x) & BIT_MASK_MAX_AGG_NUM_8821C) << BIT_SHIFT_MAX_AGG_NUM_8821C)
+#define BITS_MAX_AGG_NUM_8821C \
+ (BIT_MASK_MAX_AGG_NUM_8821C << BIT_SHIFT_MAX_AGG_NUM_8821C)
+#define BIT_CLEAR_MAX_AGG_NUM_8821C(x) ((x) & (~BITS_MAX_AGG_NUM_8821C))
+#define BIT_GET_MAX_AGG_NUM_8821C(x) \
+ (((x) >> BIT_SHIFT_MAX_AGG_NUM_8821C) & BIT_MASK_MAX_AGG_NUM_8821C)
+#define BIT_SET_MAX_AGG_NUM_8821C(x, v) \
+ (BIT_CLEAR_MAX_AGG_NUM_8821C(x) | BIT_MAX_AGG_NUM_8821C(v))
#define BIT_SHIFT_RTS_TXTIME_TH_8821C 8
#define BIT_MASK_RTS_TXTIME_TH_8821C 0xff
-#define BIT_RTS_TXTIME_TH_8821C(x) (((x) & BIT_MASK_RTS_TXTIME_TH_8821C) << BIT_SHIFT_RTS_TXTIME_TH_8821C)
-#define BIT_GET_RTS_TXTIME_TH_8821C(x) (((x) >> BIT_SHIFT_RTS_TXTIME_TH_8821C) & BIT_MASK_RTS_TXTIME_TH_8821C)
-
+#define BIT_RTS_TXTIME_TH_8821C(x) \
+ (((x) & BIT_MASK_RTS_TXTIME_TH_8821C) << BIT_SHIFT_RTS_TXTIME_TH_8821C)
+#define BITS_RTS_TXTIME_TH_8821C \
+ (BIT_MASK_RTS_TXTIME_TH_8821C << BIT_SHIFT_RTS_TXTIME_TH_8821C)
+#define BIT_CLEAR_RTS_TXTIME_TH_8821C(x) ((x) & (~BITS_RTS_TXTIME_TH_8821C))
+#define BIT_GET_RTS_TXTIME_TH_8821C(x) \
+ (((x) >> BIT_SHIFT_RTS_TXTIME_TH_8821C) & BIT_MASK_RTS_TXTIME_TH_8821C)
+#define BIT_SET_RTS_TXTIME_TH_8821C(x, v) \
+ (BIT_CLEAR_RTS_TXTIME_TH_8821C(x) | BIT_RTS_TXTIME_TH_8821C(v))
#define BIT_SHIFT_RTS_LEN_TH_8821C 0
#define BIT_MASK_RTS_LEN_TH_8821C 0xff
-#define BIT_RTS_LEN_TH_8821C(x) (((x) & BIT_MASK_RTS_LEN_TH_8821C) << BIT_SHIFT_RTS_LEN_TH_8821C)
-#define BIT_GET_RTS_LEN_TH_8821C(x) (((x) >> BIT_SHIFT_RTS_LEN_TH_8821C) & BIT_MASK_RTS_LEN_TH_8821C)
-
+#define BIT_RTS_LEN_TH_8821C(x) \
+ (((x) & BIT_MASK_RTS_LEN_TH_8821C) << BIT_SHIFT_RTS_LEN_TH_8821C)
+#define BITS_RTS_LEN_TH_8821C \
+ (BIT_MASK_RTS_LEN_TH_8821C << BIT_SHIFT_RTS_LEN_TH_8821C)
+#define BIT_CLEAR_RTS_LEN_TH_8821C(x) ((x) & (~BITS_RTS_LEN_TH_8821C))
+#define BIT_GET_RTS_LEN_TH_8821C(x) \
+ (((x) >> BIT_SHIFT_RTS_LEN_TH_8821C) & BIT_MASK_RTS_LEN_TH_8821C)
+#define BIT_SET_RTS_LEN_TH_8821C(x, v) \
+ (BIT_CLEAR_RTS_LEN_TH_8821C(x) | BIT_RTS_LEN_TH_8821C(v))
/* 2 REG_BAR_MODE_CTRL_8821C */
#define BIT_SHIFT_BAR_RTY_LMT_8821C 16
#define BIT_MASK_BAR_RTY_LMT_8821C 0x3
-#define BIT_BAR_RTY_LMT_8821C(x) (((x) & BIT_MASK_BAR_RTY_LMT_8821C) << BIT_SHIFT_BAR_RTY_LMT_8821C)
-#define BIT_GET_BAR_RTY_LMT_8821C(x) (((x) >> BIT_SHIFT_BAR_RTY_LMT_8821C) & BIT_MASK_BAR_RTY_LMT_8821C)
-
+#define BIT_BAR_RTY_LMT_8821C(x) \
+ (((x) & BIT_MASK_BAR_RTY_LMT_8821C) << BIT_SHIFT_BAR_RTY_LMT_8821C)
+#define BITS_BAR_RTY_LMT_8821C \
+ (BIT_MASK_BAR_RTY_LMT_8821C << BIT_SHIFT_BAR_RTY_LMT_8821C)
+#define BIT_CLEAR_BAR_RTY_LMT_8821C(x) ((x) & (~BITS_BAR_RTY_LMT_8821C))
+#define BIT_GET_BAR_RTY_LMT_8821C(x) \
+ (((x) >> BIT_SHIFT_BAR_RTY_LMT_8821C) & BIT_MASK_BAR_RTY_LMT_8821C)
+#define BIT_SET_BAR_RTY_LMT_8821C(x, v) \
+ (BIT_CLEAR_BAR_RTY_LMT_8821C(x) | BIT_BAR_RTY_LMT_8821C(v))
#define BIT_SHIFT_BAR_PKT_TXTIME_TH_8821C 8
#define BIT_MASK_BAR_PKT_TXTIME_TH_8821C 0xff
-#define BIT_BAR_PKT_TXTIME_TH_8821C(x) (((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8821C) << BIT_SHIFT_BAR_PKT_TXTIME_TH_8821C)
-#define BIT_GET_BAR_PKT_TXTIME_TH_8821C(x) (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8821C) & BIT_MASK_BAR_PKT_TXTIME_TH_8821C)
+#define BIT_BAR_PKT_TXTIME_TH_8821C(x) \
+ (((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8821C) \
+ << BIT_SHIFT_BAR_PKT_TXTIME_TH_8821C)
+#define BITS_BAR_PKT_TXTIME_TH_8821C \
+ (BIT_MASK_BAR_PKT_TXTIME_TH_8821C << BIT_SHIFT_BAR_PKT_TXTIME_TH_8821C)
+#define BIT_CLEAR_BAR_PKT_TXTIME_TH_8821C(x) \
+ ((x) & (~BITS_BAR_PKT_TXTIME_TH_8821C))
+#define BIT_GET_BAR_PKT_TXTIME_TH_8821C(x) \
+ (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8821C) & \
+ BIT_MASK_BAR_PKT_TXTIME_TH_8821C)
+#define BIT_SET_BAR_PKT_TXTIME_TH_8821C(x, v) \
+ (BIT_CLEAR_BAR_PKT_TXTIME_TH_8821C(x) | BIT_BAR_PKT_TXTIME_TH_8821C(v))
#define BIT_BAR_EN_V1_8821C BIT(6)
#define BIT_SHIFT_BAR_PKTNUM_TH_V1_8821C 0
#define BIT_MASK_BAR_PKTNUM_TH_V1_8821C 0x3f
-#define BIT_BAR_PKTNUM_TH_V1_8821C(x) (((x) & BIT_MASK_BAR_PKTNUM_TH_V1_8821C) << BIT_SHIFT_BAR_PKTNUM_TH_V1_8821C)
-#define BIT_GET_BAR_PKTNUM_TH_V1_8821C(x) (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8821C) & BIT_MASK_BAR_PKTNUM_TH_V1_8821C)
-
+#define BIT_BAR_PKTNUM_TH_V1_8821C(x) \
+ (((x) & BIT_MASK_BAR_PKTNUM_TH_V1_8821C) \
+ << BIT_SHIFT_BAR_PKTNUM_TH_V1_8821C)
+#define BITS_BAR_PKTNUM_TH_V1_8821C \
+ (BIT_MASK_BAR_PKTNUM_TH_V1_8821C << BIT_SHIFT_BAR_PKTNUM_TH_V1_8821C)
+#define BIT_CLEAR_BAR_PKTNUM_TH_V1_8821C(x) \
+ ((x) & (~BITS_BAR_PKTNUM_TH_V1_8821C))
+#define BIT_GET_BAR_PKTNUM_TH_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8821C) & \
+ BIT_MASK_BAR_PKTNUM_TH_V1_8821C)
+#define BIT_SET_BAR_PKTNUM_TH_V1_8821C(x, v) \
+ (BIT_CLEAR_BAR_PKTNUM_TH_V1_8821C(x) | BIT_BAR_PKTNUM_TH_V1_8821C(v))
/* 2 REG_RA_TRY_RATE_AGG_LMT_8821C */
#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8821C 0
#define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8821C 0x3f
-#define BIT_RA_TRY_RATE_AGG_LMT_V1_8821C(x) (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8821C) << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8821C)
-#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8821C(x) (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8821C) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8821C)
-
+#define BIT_RA_TRY_RATE_AGG_LMT_V1_8821C(x) \
+ (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8821C) \
+ << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8821C)
+#define BITS_RA_TRY_RATE_AGG_LMT_V1_8821C \
+ (BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8821C \
+ << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8821C)
+#define BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8821C(x) \
+ ((x) & (~BITS_RA_TRY_RATE_AGG_LMT_V1_8821C))
+#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8821C) & \
+ BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8821C)
+#define BIT_SET_RA_TRY_RATE_AGG_LMT_V1_8821C(x, v) \
+ (BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8821C(x) | \
+ BIT_RA_TRY_RATE_AGG_LMT_V1_8821C(v))
/* 2 REG_MACID_SLEEP2_8821C */
#define BIT_SHIFT_MACID95_64PKTSLEEP_8821C 0
#define BIT_MASK_MACID95_64PKTSLEEP_8821C 0xffffffffL
-#define BIT_MACID95_64PKTSLEEP_8821C(x) (((x) & BIT_MASK_MACID95_64PKTSLEEP_8821C) << BIT_SHIFT_MACID95_64PKTSLEEP_8821C)
-#define BIT_GET_MACID95_64PKTSLEEP_8821C(x) (((x) >> BIT_SHIFT_MACID95_64PKTSLEEP_8821C) & BIT_MASK_MACID95_64PKTSLEEP_8821C)
-
+#define BIT_MACID95_64PKTSLEEP_8821C(x) \
+ (((x) & BIT_MASK_MACID95_64PKTSLEEP_8821C) \
+ << BIT_SHIFT_MACID95_64PKTSLEEP_8821C)
+#define BITS_MACID95_64PKTSLEEP_8821C \
+ (BIT_MASK_MACID95_64PKTSLEEP_8821C \
+ << BIT_SHIFT_MACID95_64PKTSLEEP_8821C)
+#define BIT_CLEAR_MACID95_64PKTSLEEP_8821C(x) \
+ ((x) & (~BITS_MACID95_64PKTSLEEP_8821C))
+#define BIT_GET_MACID95_64PKTSLEEP_8821C(x) \
+ (((x) >> BIT_SHIFT_MACID95_64PKTSLEEP_8821C) & \
+ BIT_MASK_MACID95_64PKTSLEEP_8821C)
+#define BIT_SET_MACID95_64PKTSLEEP_8821C(x, v) \
+ (BIT_CLEAR_MACID95_64PKTSLEEP_8821C(x) | \
+ BIT_MACID95_64PKTSLEEP_8821C(v))
/* 2 REG_MACID_SLEEP_8821C */
#define BIT_SHIFT_MACID31_0_PKTSLEEP_8821C 0
#define BIT_MASK_MACID31_0_PKTSLEEP_8821C 0xffffffffL
-#define BIT_MACID31_0_PKTSLEEP_8821C(x) (((x) & BIT_MASK_MACID31_0_PKTSLEEP_8821C) << BIT_SHIFT_MACID31_0_PKTSLEEP_8821C)
-#define BIT_GET_MACID31_0_PKTSLEEP_8821C(x) (((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP_8821C) & BIT_MASK_MACID31_0_PKTSLEEP_8821C)
-
+#define BIT_MACID31_0_PKTSLEEP_8821C(x) \
+ (((x) & BIT_MASK_MACID31_0_PKTSLEEP_8821C) \
+ << BIT_SHIFT_MACID31_0_PKTSLEEP_8821C)
+#define BITS_MACID31_0_PKTSLEEP_8821C \
+ (BIT_MASK_MACID31_0_PKTSLEEP_8821C \
+ << BIT_SHIFT_MACID31_0_PKTSLEEP_8821C)
+#define BIT_CLEAR_MACID31_0_PKTSLEEP_8821C(x) \
+ ((x) & (~BITS_MACID31_0_PKTSLEEP_8821C))
+#define BIT_GET_MACID31_0_PKTSLEEP_8821C(x) \
+ (((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP_8821C) & \
+ BIT_MASK_MACID31_0_PKTSLEEP_8821C)
+#define BIT_SET_MACID31_0_PKTSLEEP_8821C(x, v) \
+ (BIT_CLEAR_MACID31_0_PKTSLEEP_8821C(x) | \
+ BIT_MACID31_0_PKTSLEEP_8821C(v))
/* 2 REG_HW_SEQ0_8821C */
#define BIT_SHIFT_HW_SSN_SEQ0_8821C 0
#define BIT_MASK_HW_SSN_SEQ0_8821C 0xfff
-#define BIT_HW_SSN_SEQ0_8821C(x) (((x) & BIT_MASK_HW_SSN_SEQ0_8821C) << BIT_SHIFT_HW_SSN_SEQ0_8821C)
-#define BIT_GET_HW_SSN_SEQ0_8821C(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ0_8821C) & BIT_MASK_HW_SSN_SEQ0_8821C)
-
+#define BIT_HW_SSN_SEQ0_8821C(x) \
+ (((x) & BIT_MASK_HW_SSN_SEQ0_8821C) << BIT_SHIFT_HW_SSN_SEQ0_8821C)
+#define BITS_HW_SSN_SEQ0_8821C \
+ (BIT_MASK_HW_SSN_SEQ0_8821C << BIT_SHIFT_HW_SSN_SEQ0_8821C)
+#define BIT_CLEAR_HW_SSN_SEQ0_8821C(x) ((x) & (~BITS_HW_SSN_SEQ0_8821C))
+#define BIT_GET_HW_SSN_SEQ0_8821C(x) \
+ (((x) >> BIT_SHIFT_HW_SSN_SEQ0_8821C) & BIT_MASK_HW_SSN_SEQ0_8821C)
+#define BIT_SET_HW_SSN_SEQ0_8821C(x, v) \
+ (BIT_CLEAR_HW_SSN_SEQ0_8821C(x) | BIT_HW_SSN_SEQ0_8821C(v))
/* 2 REG_HW_SEQ1_8821C */
#define BIT_SHIFT_HW_SSN_SEQ1_8821C 0
#define BIT_MASK_HW_SSN_SEQ1_8821C 0xfff
-#define BIT_HW_SSN_SEQ1_8821C(x) (((x) & BIT_MASK_HW_SSN_SEQ1_8821C) << BIT_SHIFT_HW_SSN_SEQ1_8821C)
-#define BIT_GET_HW_SSN_SEQ1_8821C(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ1_8821C) & BIT_MASK_HW_SSN_SEQ1_8821C)
-
+#define BIT_HW_SSN_SEQ1_8821C(x) \
+ (((x) & BIT_MASK_HW_SSN_SEQ1_8821C) << BIT_SHIFT_HW_SSN_SEQ1_8821C)
+#define BITS_HW_SSN_SEQ1_8821C \
+ (BIT_MASK_HW_SSN_SEQ1_8821C << BIT_SHIFT_HW_SSN_SEQ1_8821C)
+#define BIT_CLEAR_HW_SSN_SEQ1_8821C(x) ((x) & (~BITS_HW_SSN_SEQ1_8821C))
+#define BIT_GET_HW_SSN_SEQ1_8821C(x) \
+ (((x) >> BIT_SHIFT_HW_SSN_SEQ1_8821C) & BIT_MASK_HW_SSN_SEQ1_8821C)
+#define BIT_SET_HW_SSN_SEQ1_8821C(x, v) \
+ (BIT_CLEAR_HW_SSN_SEQ1_8821C(x) | BIT_HW_SSN_SEQ1_8821C(v))
/* 2 REG_HW_SEQ2_8821C */
#define BIT_SHIFT_HW_SSN_SEQ2_8821C 0
#define BIT_MASK_HW_SSN_SEQ2_8821C 0xfff
-#define BIT_HW_SSN_SEQ2_8821C(x) (((x) & BIT_MASK_HW_SSN_SEQ2_8821C) << BIT_SHIFT_HW_SSN_SEQ2_8821C)
-#define BIT_GET_HW_SSN_SEQ2_8821C(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ2_8821C) & BIT_MASK_HW_SSN_SEQ2_8821C)
-
+#define BIT_HW_SSN_SEQ2_8821C(x) \
+ (((x) & BIT_MASK_HW_SSN_SEQ2_8821C) << BIT_SHIFT_HW_SSN_SEQ2_8821C)
+#define BITS_HW_SSN_SEQ2_8821C \
+ (BIT_MASK_HW_SSN_SEQ2_8821C << BIT_SHIFT_HW_SSN_SEQ2_8821C)
+#define BIT_CLEAR_HW_SSN_SEQ2_8821C(x) ((x) & (~BITS_HW_SSN_SEQ2_8821C))
+#define BIT_GET_HW_SSN_SEQ2_8821C(x) \
+ (((x) >> BIT_SHIFT_HW_SSN_SEQ2_8821C) & BIT_MASK_HW_SSN_SEQ2_8821C)
+#define BIT_SET_HW_SSN_SEQ2_8821C(x, v) \
+ (BIT_CLEAR_HW_SSN_SEQ2_8821C(x) | BIT_HW_SSN_SEQ2_8821C(v))
/* 2 REG_HW_SEQ3_8821C */
+#define BIT_SHIFT_CSI_HWSEQ_SEL_8821C 12
+#define BIT_MASK_CSI_HWSEQ_SEL_8821C 0x3
+#define BIT_CSI_HWSEQ_SEL_8821C(x) \
+ (((x) & BIT_MASK_CSI_HWSEQ_SEL_8821C) << BIT_SHIFT_CSI_HWSEQ_SEL_8821C)
+#define BITS_CSI_HWSEQ_SEL_8821C \
+ (BIT_MASK_CSI_HWSEQ_SEL_8821C << BIT_SHIFT_CSI_HWSEQ_SEL_8821C)
+#define BIT_CLEAR_CSI_HWSEQ_SEL_8821C(x) ((x) & (~BITS_CSI_HWSEQ_SEL_8821C))
+#define BIT_GET_CSI_HWSEQ_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_CSI_HWSEQ_SEL_8821C) & BIT_MASK_CSI_HWSEQ_SEL_8821C)
+#define BIT_SET_CSI_HWSEQ_SEL_8821C(x, v) \
+ (BIT_CLEAR_CSI_HWSEQ_SEL_8821C(x) | BIT_CSI_HWSEQ_SEL_8821C(v))
+
#define BIT_SHIFT_HW_SSN_SEQ3_8821C 0
#define BIT_MASK_HW_SSN_SEQ3_8821C 0xfff
-#define BIT_HW_SSN_SEQ3_8821C(x) (((x) & BIT_MASK_HW_SSN_SEQ3_8821C) << BIT_SHIFT_HW_SSN_SEQ3_8821C)
-#define BIT_GET_HW_SSN_SEQ3_8821C(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ3_8821C) & BIT_MASK_HW_SSN_SEQ3_8821C)
-
+#define BIT_HW_SSN_SEQ3_8821C(x) \
+ (((x) & BIT_MASK_HW_SSN_SEQ3_8821C) << BIT_SHIFT_HW_SSN_SEQ3_8821C)
+#define BITS_HW_SSN_SEQ3_8821C \
+ (BIT_MASK_HW_SSN_SEQ3_8821C << BIT_SHIFT_HW_SSN_SEQ3_8821C)
+#define BIT_CLEAR_HW_SSN_SEQ3_8821C(x) ((x) & (~BITS_HW_SSN_SEQ3_8821C))
+#define BIT_GET_HW_SSN_SEQ3_8821C(x) \
+ (((x) >> BIT_SHIFT_HW_SSN_SEQ3_8821C) & BIT_MASK_HW_SSN_SEQ3_8821C)
+#define BIT_SET_HW_SSN_SEQ3_8821C(x, v) \
+ (BIT_CLEAR_HW_SSN_SEQ3_8821C(x) | BIT_HW_SSN_SEQ3_8821C(v))
/* 2 REG_NULL_PKT_STATUS_V1_8821C */
#define BIT_SHIFT_PTCL_TOTAL_PG_V2_8821C 2
#define BIT_MASK_PTCL_TOTAL_PG_V2_8821C 0x3fff
-#define BIT_PTCL_TOTAL_PG_V2_8821C(x) (((x) & BIT_MASK_PTCL_TOTAL_PG_V2_8821C) << BIT_SHIFT_PTCL_TOTAL_PG_V2_8821C)
-#define BIT_GET_PTCL_TOTAL_PG_V2_8821C(x) (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2_8821C) & BIT_MASK_PTCL_TOTAL_PG_V2_8821C)
+#define BIT_PTCL_TOTAL_PG_V2_8821C(x) \
+ (((x) & BIT_MASK_PTCL_TOTAL_PG_V2_8821C) \
+ << BIT_SHIFT_PTCL_TOTAL_PG_V2_8821C)
+#define BITS_PTCL_TOTAL_PG_V2_8821C \
+ (BIT_MASK_PTCL_TOTAL_PG_V2_8821C << BIT_SHIFT_PTCL_TOTAL_PG_V2_8821C)
+#define BIT_CLEAR_PTCL_TOTAL_PG_V2_8821C(x) \
+ ((x) & (~BITS_PTCL_TOTAL_PG_V2_8821C))
+#define BIT_GET_PTCL_TOTAL_PG_V2_8821C(x) \
+ (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2_8821C) & \
+ BIT_MASK_PTCL_TOTAL_PG_V2_8821C)
+#define BIT_SET_PTCL_TOTAL_PG_V2_8821C(x, v) \
+ (BIT_CLEAR_PTCL_TOTAL_PG_V2_8821C(x) | BIT_PTCL_TOTAL_PG_V2_8821C(v))
#define BIT_TX_NULL_1_8821C BIT(1)
#define BIT_TX_NULL_0_8821C BIT(0)
@@ -5795,16 +10783,46 @@
#define BIT_CLI0_TX_NULL_0_8821C BIT(0)
/* 2 REG_VIDEO_ENHANCEMENT_FUN_8821C */
+#define BIT_HIQ_DROP_8821C BIT(7)
+#define BIT_MGQ_DROP_8821C BIT(6)
#define BIT_VIDEO_JUST_DROP_8821C BIT(1)
#define BIT_VIDEO_ENHANCEMENT_FUN_EN_8821C BIT(0)
+/* 2 REG_PRECNT_CTRL_8821C */
+#define BIT_EN_PRECNT_8821C BIT(11)
+
+#define BIT_SHIFT_PRECNT_TH_8821C 0
+#define BIT_MASK_PRECNT_TH_8821C 0x7ff
+#define BIT_PRECNT_TH_8821C(x) \
+ (((x) & BIT_MASK_PRECNT_TH_8821C) << BIT_SHIFT_PRECNT_TH_8821C)
+#define BITS_PRECNT_TH_8821C \
+ (BIT_MASK_PRECNT_TH_8821C << BIT_SHIFT_PRECNT_TH_8821C)
+#define BIT_CLEAR_PRECNT_TH_8821C(x) ((x) & (~BITS_PRECNT_TH_8821C))
+#define BIT_GET_PRECNT_TH_8821C(x) \
+ (((x) >> BIT_SHIFT_PRECNT_TH_8821C) & BIT_MASK_PRECNT_TH_8821C)
+#define BIT_SET_PRECNT_TH_8821C(x, v) \
+ (BIT_CLEAR_PRECNT_TH_8821C(x) | BIT_PRECNT_TH_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
/* 2 REG_BT_POLLUTE_PKT_CNT_8821C */
#define BIT_SHIFT_BT_POLLUTE_PKT_CNT_8821C 0
#define BIT_MASK_BT_POLLUTE_PKT_CNT_8821C 0xffff
-#define BIT_BT_POLLUTE_PKT_CNT_8821C(x) (((x) & BIT_MASK_BT_POLLUTE_PKT_CNT_8821C) << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8821C)
-#define BIT_GET_BT_POLLUTE_PKT_CNT_8821C(x) (((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT_8821C) & BIT_MASK_BT_POLLUTE_PKT_CNT_8821C)
-
+#define BIT_BT_POLLUTE_PKT_CNT_8821C(x) \
+ (((x) & BIT_MASK_BT_POLLUTE_PKT_CNT_8821C) \
+ << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8821C)
+#define BITS_BT_POLLUTE_PKT_CNT_8821C \
+ (BIT_MASK_BT_POLLUTE_PKT_CNT_8821C \
+ << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8821C)
+#define BIT_CLEAR_BT_POLLUTE_PKT_CNT_8821C(x) \
+ ((x) & (~BITS_BT_POLLUTE_PKT_CNT_8821C))
+#define BIT_GET_BT_POLLUTE_PKT_CNT_8821C(x) \
+ (((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT_8821C) & \
+ BIT_MASK_BT_POLLUTE_PKT_CNT_8821C)
+#define BIT_SET_BT_POLLUTE_PKT_CNT_8821C(x, v) \
+ (BIT_CLEAR_BT_POLLUTE_PKT_CNT_8821C(x) | \
+ BIT_BT_POLLUTE_PKT_CNT_8821C(v))
/* 2 REG_NOT_VALID_8821C */
@@ -5812,9 +10830,15 @@
#define BIT_SHIFT_PTCL_DBG_8821C 0
#define BIT_MASK_PTCL_DBG_8821C 0xffffffffL
-#define BIT_PTCL_DBG_8821C(x) (((x) & BIT_MASK_PTCL_DBG_8821C) << BIT_SHIFT_PTCL_DBG_8821C)
-#define BIT_GET_PTCL_DBG_8821C(x) (((x) >> BIT_SHIFT_PTCL_DBG_8821C) & BIT_MASK_PTCL_DBG_8821C)
-
+#define BIT_PTCL_DBG_8821C(x) \
+ (((x) & BIT_MASK_PTCL_DBG_8821C) << BIT_SHIFT_PTCL_DBG_8821C)
+#define BITS_PTCL_DBG_8821C \
+ (BIT_MASK_PTCL_DBG_8821C << BIT_SHIFT_PTCL_DBG_8821C)
+#define BIT_CLEAR_PTCL_DBG_8821C(x) ((x) & (~BITS_PTCL_DBG_8821C))
+#define BIT_GET_PTCL_DBG_8821C(x) \
+ (((x) >> BIT_SHIFT_PTCL_DBG_8821C) & BIT_MASK_PTCL_DBG_8821C)
+#define BIT_SET_PTCL_DBG_8821C(x, v) \
+ (BIT_CLEAR_PTCL_DBG_8821C(x) | BIT_PTCL_DBG_8821C(v))
/* 2 REG_NOT_VALID_8821C */
@@ -5822,16 +10846,28 @@
#define BIT_SHIFT_TRI_HEAD_ADDR_8821C 16
#define BIT_MASK_TRI_HEAD_ADDR_8821C 0xfff
-#define BIT_TRI_HEAD_ADDR_8821C(x) (((x) & BIT_MASK_TRI_HEAD_ADDR_8821C) << BIT_SHIFT_TRI_HEAD_ADDR_8821C)
-#define BIT_GET_TRI_HEAD_ADDR_8821C(x) (((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8821C) & BIT_MASK_TRI_HEAD_ADDR_8821C)
+#define BIT_TRI_HEAD_ADDR_8821C(x) \
+ (((x) & BIT_MASK_TRI_HEAD_ADDR_8821C) << BIT_SHIFT_TRI_HEAD_ADDR_8821C)
+#define BITS_TRI_HEAD_ADDR_8821C \
+ (BIT_MASK_TRI_HEAD_ADDR_8821C << BIT_SHIFT_TRI_HEAD_ADDR_8821C)
+#define BIT_CLEAR_TRI_HEAD_ADDR_8821C(x) ((x) & (~BITS_TRI_HEAD_ADDR_8821C))
+#define BIT_GET_TRI_HEAD_ADDR_8821C(x) \
+ (((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8821C) & BIT_MASK_TRI_HEAD_ADDR_8821C)
+#define BIT_SET_TRI_HEAD_ADDR_8821C(x, v) \
+ (BIT_CLEAR_TRI_HEAD_ADDR_8821C(x) | BIT_TRI_HEAD_ADDR_8821C(v))
#define BIT_DROP_TH_EN_8821C BIT(8)
#define BIT_SHIFT_DROP_TH_8821C 0
#define BIT_MASK_DROP_TH_8821C 0xff
-#define BIT_DROP_TH_8821C(x) (((x) & BIT_MASK_DROP_TH_8821C) << BIT_SHIFT_DROP_TH_8821C)
-#define BIT_GET_DROP_TH_8821C(x) (((x) >> BIT_SHIFT_DROP_TH_8821C) & BIT_MASK_DROP_TH_8821C)
-
+#define BIT_DROP_TH_8821C(x) \
+ (((x) & BIT_MASK_DROP_TH_8821C) << BIT_SHIFT_DROP_TH_8821C)
+#define BITS_DROP_TH_8821C (BIT_MASK_DROP_TH_8821C << BIT_SHIFT_DROP_TH_8821C)
+#define BIT_CLEAR_DROP_TH_8821C(x) ((x) & (~BITS_DROP_TH_8821C))
+#define BIT_GET_DROP_TH_8821C(x) \
+ (((x) >> BIT_SHIFT_DROP_TH_8821C) & BIT_MASK_DROP_TH_8821C)
+#define BIT_SET_DROP_TH_8821C(x, v) \
+ (BIT_CLEAR_DROP_TH_8821C(x) | BIT_DROP_TH_8821C(v))
/* 2 REG_NOT_VALID_8821C */
@@ -5842,161 +10878,292 @@
#define BIT_MOREDATA_CTRL1_EN_V1_8821C BIT(2)
#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE_V1_8821C BIT(0)
-/* 2 REG_NOT_VALID_8821C */
-
/* 2 REG_Q0_Q1_INFO_8821C */
#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8821C BIT(31)
#define BIT_SHIFT_GTAB_ID_8821C 28
#define BIT_MASK_GTAB_ID_8821C 0x7
-#define BIT_GTAB_ID_8821C(x) (((x) & BIT_MASK_GTAB_ID_8821C) << BIT_SHIFT_GTAB_ID_8821C)
-#define BIT_GET_GTAB_ID_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C)
-
+#define BIT_GTAB_ID_8821C(x) \
+ (((x) & BIT_MASK_GTAB_ID_8821C) << BIT_SHIFT_GTAB_ID_8821C)
+#define BITS_GTAB_ID_8821C (BIT_MASK_GTAB_ID_8821C << BIT_SHIFT_GTAB_ID_8821C)
+#define BIT_CLEAR_GTAB_ID_8821C(x) ((x) & (~BITS_GTAB_ID_8821C))
+#define BIT_GET_GTAB_ID_8821C(x) \
+ (((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C)
+#define BIT_SET_GTAB_ID_8821C(x, v) \
+ (BIT_CLEAR_GTAB_ID_8821C(x) | BIT_GTAB_ID_8821C(v))
#define BIT_SHIFT_AC1_PKT_INFO_8821C 16
#define BIT_MASK_AC1_PKT_INFO_8821C 0xfff
-#define BIT_AC1_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC1_PKT_INFO_8821C) << BIT_SHIFT_AC1_PKT_INFO_8821C)
-#define BIT_GET_AC1_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC1_PKT_INFO_8821C) & BIT_MASK_AC1_PKT_INFO_8821C)
+#define BIT_AC1_PKT_INFO_8821C(x) \
+ (((x) & BIT_MASK_AC1_PKT_INFO_8821C) << BIT_SHIFT_AC1_PKT_INFO_8821C)
+#define BITS_AC1_PKT_INFO_8821C \
+ (BIT_MASK_AC1_PKT_INFO_8821C << BIT_SHIFT_AC1_PKT_INFO_8821C)
+#define BIT_CLEAR_AC1_PKT_INFO_8821C(x) ((x) & (~BITS_AC1_PKT_INFO_8821C))
+#define BIT_GET_AC1_PKT_INFO_8821C(x) \
+ (((x) >> BIT_SHIFT_AC1_PKT_INFO_8821C) & BIT_MASK_AC1_PKT_INFO_8821C)
+#define BIT_SET_AC1_PKT_INFO_8821C(x, v) \
+ (BIT_CLEAR_AC1_PKT_INFO_8821C(x) | BIT_AC1_PKT_INFO_8821C(v))
#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8821C BIT(15)
#define BIT_SHIFT_GTAB_ID_V1_8821C 12
#define BIT_MASK_GTAB_ID_V1_8821C 0x7
-#define BIT_GTAB_ID_V1_8821C(x) (((x) & BIT_MASK_GTAB_ID_V1_8821C) << BIT_SHIFT_GTAB_ID_V1_8821C)
-#define BIT_GET_GTAB_ID_V1_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C)
-
+#define BIT_GTAB_ID_V1_8821C(x) \
+ (((x) & BIT_MASK_GTAB_ID_V1_8821C) << BIT_SHIFT_GTAB_ID_V1_8821C)
+#define BITS_GTAB_ID_V1_8821C \
+ (BIT_MASK_GTAB_ID_V1_8821C << BIT_SHIFT_GTAB_ID_V1_8821C)
+#define BIT_CLEAR_GTAB_ID_V1_8821C(x) ((x) & (~BITS_GTAB_ID_V1_8821C))
+#define BIT_GET_GTAB_ID_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C)
+#define BIT_SET_GTAB_ID_V1_8821C(x, v) \
+ (BIT_CLEAR_GTAB_ID_V1_8821C(x) | BIT_GTAB_ID_V1_8821C(v))
#define BIT_SHIFT_AC0_PKT_INFO_8821C 0
#define BIT_MASK_AC0_PKT_INFO_8821C 0xfff
-#define BIT_AC0_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC0_PKT_INFO_8821C) << BIT_SHIFT_AC0_PKT_INFO_8821C)
-#define BIT_GET_AC0_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC0_PKT_INFO_8821C) & BIT_MASK_AC0_PKT_INFO_8821C)
-
+#define BIT_AC0_PKT_INFO_8821C(x) \
+ (((x) & BIT_MASK_AC0_PKT_INFO_8821C) << BIT_SHIFT_AC0_PKT_INFO_8821C)
+#define BITS_AC0_PKT_INFO_8821C \
+ (BIT_MASK_AC0_PKT_INFO_8821C << BIT_SHIFT_AC0_PKT_INFO_8821C)
+#define BIT_CLEAR_AC0_PKT_INFO_8821C(x) ((x) & (~BITS_AC0_PKT_INFO_8821C))
+#define BIT_GET_AC0_PKT_INFO_8821C(x) \
+ (((x) >> BIT_SHIFT_AC0_PKT_INFO_8821C) & BIT_MASK_AC0_PKT_INFO_8821C)
+#define BIT_SET_AC0_PKT_INFO_8821C(x, v) \
+ (BIT_CLEAR_AC0_PKT_INFO_8821C(x) | BIT_AC0_PKT_INFO_8821C(v))
/* 2 REG_Q2_Q3_INFO_8821C */
#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8821C BIT(31)
#define BIT_SHIFT_GTAB_ID_8821C 28
#define BIT_MASK_GTAB_ID_8821C 0x7
-#define BIT_GTAB_ID_8821C(x) (((x) & BIT_MASK_GTAB_ID_8821C) << BIT_SHIFT_GTAB_ID_8821C)
-#define BIT_GET_GTAB_ID_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C)
-
+#define BIT_GTAB_ID_8821C(x) \
+ (((x) & BIT_MASK_GTAB_ID_8821C) << BIT_SHIFT_GTAB_ID_8821C)
+#define BITS_GTAB_ID_8821C (BIT_MASK_GTAB_ID_8821C << BIT_SHIFT_GTAB_ID_8821C)
+#define BIT_CLEAR_GTAB_ID_8821C(x) ((x) & (~BITS_GTAB_ID_8821C))
+#define BIT_GET_GTAB_ID_8821C(x) \
+ (((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C)
+#define BIT_SET_GTAB_ID_8821C(x, v) \
+ (BIT_CLEAR_GTAB_ID_8821C(x) | BIT_GTAB_ID_8821C(v))
#define BIT_SHIFT_AC3_PKT_INFO_8821C 16
#define BIT_MASK_AC3_PKT_INFO_8821C 0xfff
-#define BIT_AC3_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC3_PKT_INFO_8821C) << BIT_SHIFT_AC3_PKT_INFO_8821C)
-#define BIT_GET_AC3_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC3_PKT_INFO_8821C) & BIT_MASK_AC3_PKT_INFO_8821C)
+#define BIT_AC3_PKT_INFO_8821C(x) \
+ (((x) & BIT_MASK_AC3_PKT_INFO_8821C) << BIT_SHIFT_AC3_PKT_INFO_8821C)
+#define BITS_AC3_PKT_INFO_8821C \
+ (BIT_MASK_AC3_PKT_INFO_8821C << BIT_SHIFT_AC3_PKT_INFO_8821C)
+#define BIT_CLEAR_AC3_PKT_INFO_8821C(x) ((x) & (~BITS_AC3_PKT_INFO_8821C))
+#define BIT_GET_AC3_PKT_INFO_8821C(x) \
+ (((x) >> BIT_SHIFT_AC3_PKT_INFO_8821C) & BIT_MASK_AC3_PKT_INFO_8821C)
+#define BIT_SET_AC3_PKT_INFO_8821C(x, v) \
+ (BIT_CLEAR_AC3_PKT_INFO_8821C(x) | BIT_AC3_PKT_INFO_8821C(v))
#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8821C BIT(15)
#define BIT_SHIFT_GTAB_ID_V1_8821C 12
#define BIT_MASK_GTAB_ID_V1_8821C 0x7
-#define BIT_GTAB_ID_V1_8821C(x) (((x) & BIT_MASK_GTAB_ID_V1_8821C) << BIT_SHIFT_GTAB_ID_V1_8821C)
-#define BIT_GET_GTAB_ID_V1_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C)
-
+#define BIT_GTAB_ID_V1_8821C(x) \
+ (((x) & BIT_MASK_GTAB_ID_V1_8821C) << BIT_SHIFT_GTAB_ID_V1_8821C)
+#define BITS_GTAB_ID_V1_8821C \
+ (BIT_MASK_GTAB_ID_V1_8821C << BIT_SHIFT_GTAB_ID_V1_8821C)
+#define BIT_CLEAR_GTAB_ID_V1_8821C(x) ((x) & (~BITS_GTAB_ID_V1_8821C))
+#define BIT_GET_GTAB_ID_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C)
+#define BIT_SET_GTAB_ID_V1_8821C(x, v) \
+ (BIT_CLEAR_GTAB_ID_V1_8821C(x) | BIT_GTAB_ID_V1_8821C(v))
#define BIT_SHIFT_AC2_PKT_INFO_8821C 0
#define BIT_MASK_AC2_PKT_INFO_8821C 0xfff
-#define BIT_AC2_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC2_PKT_INFO_8821C) << BIT_SHIFT_AC2_PKT_INFO_8821C)
-#define BIT_GET_AC2_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC2_PKT_INFO_8821C) & BIT_MASK_AC2_PKT_INFO_8821C)
-
+#define BIT_AC2_PKT_INFO_8821C(x) \
+ (((x) & BIT_MASK_AC2_PKT_INFO_8821C) << BIT_SHIFT_AC2_PKT_INFO_8821C)
+#define BITS_AC2_PKT_INFO_8821C \
+ (BIT_MASK_AC2_PKT_INFO_8821C << BIT_SHIFT_AC2_PKT_INFO_8821C)
+#define BIT_CLEAR_AC2_PKT_INFO_8821C(x) ((x) & (~BITS_AC2_PKT_INFO_8821C))
+#define BIT_GET_AC2_PKT_INFO_8821C(x) \
+ (((x) >> BIT_SHIFT_AC2_PKT_INFO_8821C) & BIT_MASK_AC2_PKT_INFO_8821C)
+#define BIT_SET_AC2_PKT_INFO_8821C(x, v) \
+ (BIT_CLEAR_AC2_PKT_INFO_8821C(x) | BIT_AC2_PKT_INFO_8821C(v))
/* 2 REG_Q4_Q5_INFO_8821C */
#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8821C BIT(31)
#define BIT_SHIFT_GTAB_ID_8821C 28
#define BIT_MASK_GTAB_ID_8821C 0x7
-#define BIT_GTAB_ID_8821C(x) (((x) & BIT_MASK_GTAB_ID_8821C) << BIT_SHIFT_GTAB_ID_8821C)
-#define BIT_GET_GTAB_ID_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C)
-
+#define BIT_GTAB_ID_8821C(x) \
+ (((x) & BIT_MASK_GTAB_ID_8821C) << BIT_SHIFT_GTAB_ID_8821C)
+#define BITS_GTAB_ID_8821C (BIT_MASK_GTAB_ID_8821C << BIT_SHIFT_GTAB_ID_8821C)
+#define BIT_CLEAR_GTAB_ID_8821C(x) ((x) & (~BITS_GTAB_ID_8821C))
+#define BIT_GET_GTAB_ID_8821C(x) \
+ (((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C)
+#define BIT_SET_GTAB_ID_8821C(x, v) \
+ (BIT_CLEAR_GTAB_ID_8821C(x) | BIT_GTAB_ID_8821C(v))
#define BIT_SHIFT_AC5_PKT_INFO_8821C 16
#define BIT_MASK_AC5_PKT_INFO_8821C 0xfff
-#define BIT_AC5_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC5_PKT_INFO_8821C) << BIT_SHIFT_AC5_PKT_INFO_8821C)
-#define BIT_GET_AC5_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC5_PKT_INFO_8821C) & BIT_MASK_AC5_PKT_INFO_8821C)
+#define BIT_AC5_PKT_INFO_8821C(x) \
+ (((x) & BIT_MASK_AC5_PKT_INFO_8821C) << BIT_SHIFT_AC5_PKT_INFO_8821C)
+#define BITS_AC5_PKT_INFO_8821C \
+ (BIT_MASK_AC5_PKT_INFO_8821C << BIT_SHIFT_AC5_PKT_INFO_8821C)
+#define BIT_CLEAR_AC5_PKT_INFO_8821C(x) ((x) & (~BITS_AC5_PKT_INFO_8821C))
+#define BIT_GET_AC5_PKT_INFO_8821C(x) \
+ (((x) >> BIT_SHIFT_AC5_PKT_INFO_8821C) & BIT_MASK_AC5_PKT_INFO_8821C)
+#define BIT_SET_AC5_PKT_INFO_8821C(x, v) \
+ (BIT_CLEAR_AC5_PKT_INFO_8821C(x) | BIT_AC5_PKT_INFO_8821C(v))
#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8821C BIT(15)
#define BIT_SHIFT_GTAB_ID_V1_8821C 12
#define BIT_MASK_GTAB_ID_V1_8821C 0x7
-#define BIT_GTAB_ID_V1_8821C(x) (((x) & BIT_MASK_GTAB_ID_V1_8821C) << BIT_SHIFT_GTAB_ID_V1_8821C)
-#define BIT_GET_GTAB_ID_V1_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C)
-
+#define BIT_GTAB_ID_V1_8821C(x) \
+ (((x) & BIT_MASK_GTAB_ID_V1_8821C) << BIT_SHIFT_GTAB_ID_V1_8821C)
+#define BITS_GTAB_ID_V1_8821C \
+ (BIT_MASK_GTAB_ID_V1_8821C << BIT_SHIFT_GTAB_ID_V1_8821C)
+#define BIT_CLEAR_GTAB_ID_V1_8821C(x) ((x) & (~BITS_GTAB_ID_V1_8821C))
+#define BIT_GET_GTAB_ID_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C)
+#define BIT_SET_GTAB_ID_V1_8821C(x, v) \
+ (BIT_CLEAR_GTAB_ID_V1_8821C(x) | BIT_GTAB_ID_V1_8821C(v))
#define BIT_SHIFT_AC4_PKT_INFO_8821C 0
#define BIT_MASK_AC4_PKT_INFO_8821C 0xfff
-#define BIT_AC4_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC4_PKT_INFO_8821C) << BIT_SHIFT_AC4_PKT_INFO_8821C)
-#define BIT_GET_AC4_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC4_PKT_INFO_8821C) & BIT_MASK_AC4_PKT_INFO_8821C)
-
+#define BIT_AC4_PKT_INFO_8821C(x) \
+ (((x) & BIT_MASK_AC4_PKT_INFO_8821C) << BIT_SHIFT_AC4_PKT_INFO_8821C)
+#define BITS_AC4_PKT_INFO_8821C \
+ (BIT_MASK_AC4_PKT_INFO_8821C << BIT_SHIFT_AC4_PKT_INFO_8821C)
+#define BIT_CLEAR_AC4_PKT_INFO_8821C(x) ((x) & (~BITS_AC4_PKT_INFO_8821C))
+#define BIT_GET_AC4_PKT_INFO_8821C(x) \
+ (((x) >> BIT_SHIFT_AC4_PKT_INFO_8821C) & BIT_MASK_AC4_PKT_INFO_8821C)
+#define BIT_SET_AC4_PKT_INFO_8821C(x, v) \
+ (BIT_CLEAR_AC4_PKT_INFO_8821C(x) | BIT_AC4_PKT_INFO_8821C(v))
/* 2 REG_Q6_Q7_INFO_8821C */
#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8821C BIT(31)
#define BIT_SHIFT_GTAB_ID_8821C 28
#define BIT_MASK_GTAB_ID_8821C 0x7
-#define BIT_GTAB_ID_8821C(x) (((x) & BIT_MASK_GTAB_ID_8821C) << BIT_SHIFT_GTAB_ID_8821C)
-#define BIT_GET_GTAB_ID_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C)
-
+#define BIT_GTAB_ID_8821C(x) \
+ (((x) & BIT_MASK_GTAB_ID_8821C) << BIT_SHIFT_GTAB_ID_8821C)
+#define BITS_GTAB_ID_8821C (BIT_MASK_GTAB_ID_8821C << BIT_SHIFT_GTAB_ID_8821C)
+#define BIT_CLEAR_GTAB_ID_8821C(x) ((x) & (~BITS_GTAB_ID_8821C))
+#define BIT_GET_GTAB_ID_8821C(x) \
+ (((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C)
+#define BIT_SET_GTAB_ID_8821C(x, v) \
+ (BIT_CLEAR_GTAB_ID_8821C(x) | BIT_GTAB_ID_8821C(v))
#define BIT_SHIFT_AC7_PKT_INFO_8821C 16
#define BIT_MASK_AC7_PKT_INFO_8821C 0xfff
-#define BIT_AC7_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC7_PKT_INFO_8821C) << BIT_SHIFT_AC7_PKT_INFO_8821C)
-#define BIT_GET_AC7_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC7_PKT_INFO_8821C) & BIT_MASK_AC7_PKT_INFO_8821C)
+#define BIT_AC7_PKT_INFO_8821C(x) \
+ (((x) & BIT_MASK_AC7_PKT_INFO_8821C) << BIT_SHIFT_AC7_PKT_INFO_8821C)
+#define BITS_AC7_PKT_INFO_8821C \
+ (BIT_MASK_AC7_PKT_INFO_8821C << BIT_SHIFT_AC7_PKT_INFO_8821C)
+#define BIT_CLEAR_AC7_PKT_INFO_8821C(x) ((x) & (~BITS_AC7_PKT_INFO_8821C))
+#define BIT_GET_AC7_PKT_INFO_8821C(x) \
+ (((x) >> BIT_SHIFT_AC7_PKT_INFO_8821C) & BIT_MASK_AC7_PKT_INFO_8821C)
+#define BIT_SET_AC7_PKT_INFO_8821C(x, v) \
+ (BIT_CLEAR_AC7_PKT_INFO_8821C(x) | BIT_AC7_PKT_INFO_8821C(v))
#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8821C BIT(15)
#define BIT_SHIFT_GTAB_ID_V1_8821C 12
#define BIT_MASK_GTAB_ID_V1_8821C 0x7
-#define BIT_GTAB_ID_V1_8821C(x) (((x) & BIT_MASK_GTAB_ID_V1_8821C) << BIT_SHIFT_GTAB_ID_V1_8821C)
-#define BIT_GET_GTAB_ID_V1_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C)
-
+#define BIT_GTAB_ID_V1_8821C(x) \
+ (((x) & BIT_MASK_GTAB_ID_V1_8821C) << BIT_SHIFT_GTAB_ID_V1_8821C)
+#define BITS_GTAB_ID_V1_8821C \
+ (BIT_MASK_GTAB_ID_V1_8821C << BIT_SHIFT_GTAB_ID_V1_8821C)
+#define BIT_CLEAR_GTAB_ID_V1_8821C(x) ((x) & (~BITS_GTAB_ID_V1_8821C))
+#define BIT_GET_GTAB_ID_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C)
+#define BIT_SET_GTAB_ID_V1_8821C(x, v) \
+ (BIT_CLEAR_GTAB_ID_V1_8821C(x) | BIT_GTAB_ID_V1_8821C(v))
#define BIT_SHIFT_AC6_PKT_INFO_8821C 0
#define BIT_MASK_AC6_PKT_INFO_8821C 0xfff
-#define BIT_AC6_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC6_PKT_INFO_8821C) << BIT_SHIFT_AC6_PKT_INFO_8821C)
-#define BIT_GET_AC6_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC6_PKT_INFO_8821C) & BIT_MASK_AC6_PKT_INFO_8821C)
-
+#define BIT_AC6_PKT_INFO_8821C(x) \
+ (((x) & BIT_MASK_AC6_PKT_INFO_8821C) << BIT_SHIFT_AC6_PKT_INFO_8821C)
+#define BITS_AC6_PKT_INFO_8821C \
+ (BIT_MASK_AC6_PKT_INFO_8821C << BIT_SHIFT_AC6_PKT_INFO_8821C)
+#define BIT_CLEAR_AC6_PKT_INFO_8821C(x) ((x) & (~BITS_AC6_PKT_INFO_8821C))
+#define BIT_GET_AC6_PKT_INFO_8821C(x) \
+ (((x) >> BIT_SHIFT_AC6_PKT_INFO_8821C) & BIT_MASK_AC6_PKT_INFO_8821C)
+#define BIT_SET_AC6_PKT_INFO_8821C(x, v) \
+ (BIT_CLEAR_AC6_PKT_INFO_8821C(x) | BIT_AC6_PKT_INFO_8821C(v))
/* 2 REG_MGQ_HIQ_INFO_8821C */
#define BIT_SHIFT_HIQ_PKT_INFO_8821C 16
#define BIT_MASK_HIQ_PKT_INFO_8821C 0xfff
-#define BIT_HIQ_PKT_INFO_8821C(x) (((x) & BIT_MASK_HIQ_PKT_INFO_8821C) << BIT_SHIFT_HIQ_PKT_INFO_8821C)
-#define BIT_GET_HIQ_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_HIQ_PKT_INFO_8821C) & BIT_MASK_HIQ_PKT_INFO_8821C)
-
+#define BIT_HIQ_PKT_INFO_8821C(x) \
+ (((x) & BIT_MASK_HIQ_PKT_INFO_8821C) << BIT_SHIFT_HIQ_PKT_INFO_8821C)
+#define BITS_HIQ_PKT_INFO_8821C \
+ (BIT_MASK_HIQ_PKT_INFO_8821C << BIT_SHIFT_HIQ_PKT_INFO_8821C)
+#define BIT_CLEAR_HIQ_PKT_INFO_8821C(x) ((x) & (~BITS_HIQ_PKT_INFO_8821C))
+#define BIT_GET_HIQ_PKT_INFO_8821C(x) \
+ (((x) >> BIT_SHIFT_HIQ_PKT_INFO_8821C) & BIT_MASK_HIQ_PKT_INFO_8821C)
+#define BIT_SET_HIQ_PKT_INFO_8821C(x, v) \
+ (BIT_CLEAR_HIQ_PKT_INFO_8821C(x) | BIT_HIQ_PKT_INFO_8821C(v))
#define BIT_SHIFT_MGQ_PKT_INFO_8821C 0
#define BIT_MASK_MGQ_PKT_INFO_8821C 0xfff
-#define BIT_MGQ_PKT_INFO_8821C(x) (((x) & BIT_MASK_MGQ_PKT_INFO_8821C) << BIT_SHIFT_MGQ_PKT_INFO_8821C)
-#define BIT_GET_MGQ_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_MGQ_PKT_INFO_8821C) & BIT_MASK_MGQ_PKT_INFO_8821C)
-
+#define BIT_MGQ_PKT_INFO_8821C(x) \
+ (((x) & BIT_MASK_MGQ_PKT_INFO_8821C) << BIT_SHIFT_MGQ_PKT_INFO_8821C)
+#define BITS_MGQ_PKT_INFO_8821C \
+ (BIT_MASK_MGQ_PKT_INFO_8821C << BIT_SHIFT_MGQ_PKT_INFO_8821C)
+#define BIT_CLEAR_MGQ_PKT_INFO_8821C(x) ((x) & (~BITS_MGQ_PKT_INFO_8821C))
+#define BIT_GET_MGQ_PKT_INFO_8821C(x) \
+ (((x) >> BIT_SHIFT_MGQ_PKT_INFO_8821C) & BIT_MASK_MGQ_PKT_INFO_8821C)
+#define BIT_SET_MGQ_PKT_INFO_8821C(x, v) \
+ (BIT_CLEAR_MGQ_PKT_INFO_8821C(x) | BIT_MGQ_PKT_INFO_8821C(v))
/* 2 REG_CMDQ_BCNQ_INFO_8821C */
#define BIT_SHIFT_CMDQ_PKT_INFO_8821C 16
#define BIT_MASK_CMDQ_PKT_INFO_8821C 0xfff
-#define BIT_CMDQ_PKT_INFO_8821C(x) (((x) & BIT_MASK_CMDQ_PKT_INFO_8821C) << BIT_SHIFT_CMDQ_PKT_INFO_8821C)
-#define BIT_GET_CMDQ_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_CMDQ_PKT_INFO_8821C) & BIT_MASK_CMDQ_PKT_INFO_8821C)
-
+#define BIT_CMDQ_PKT_INFO_8821C(x) \
+ (((x) & BIT_MASK_CMDQ_PKT_INFO_8821C) << BIT_SHIFT_CMDQ_PKT_INFO_8821C)
+#define BITS_CMDQ_PKT_INFO_8821C \
+ (BIT_MASK_CMDQ_PKT_INFO_8821C << BIT_SHIFT_CMDQ_PKT_INFO_8821C)
+#define BIT_CLEAR_CMDQ_PKT_INFO_8821C(x) ((x) & (~BITS_CMDQ_PKT_INFO_8821C))
+#define BIT_GET_CMDQ_PKT_INFO_8821C(x) \
+ (((x) >> BIT_SHIFT_CMDQ_PKT_INFO_8821C) & BIT_MASK_CMDQ_PKT_INFO_8821C)
+#define BIT_SET_CMDQ_PKT_INFO_8821C(x, v) \
+ (BIT_CLEAR_CMDQ_PKT_INFO_8821C(x) | BIT_CMDQ_PKT_INFO_8821C(v))
#define BIT_SHIFT_BCNQ_PKT_INFO_8821C 0
#define BIT_MASK_BCNQ_PKT_INFO_8821C 0xfff
-#define BIT_BCNQ_PKT_INFO_8821C(x) (((x) & BIT_MASK_BCNQ_PKT_INFO_8821C) << BIT_SHIFT_BCNQ_PKT_INFO_8821C)
-#define BIT_GET_BCNQ_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_BCNQ_PKT_INFO_8821C) & BIT_MASK_BCNQ_PKT_INFO_8821C)
-
+#define BIT_BCNQ_PKT_INFO_8821C(x) \
+ (((x) & BIT_MASK_BCNQ_PKT_INFO_8821C) << BIT_SHIFT_BCNQ_PKT_INFO_8821C)
+#define BITS_BCNQ_PKT_INFO_8821C \
+ (BIT_MASK_BCNQ_PKT_INFO_8821C << BIT_SHIFT_BCNQ_PKT_INFO_8821C)
+#define BIT_CLEAR_BCNQ_PKT_INFO_8821C(x) ((x) & (~BITS_BCNQ_PKT_INFO_8821C))
+#define BIT_GET_BCNQ_PKT_INFO_8821C(x) \
+ (((x) >> BIT_SHIFT_BCNQ_PKT_INFO_8821C) & BIT_MASK_BCNQ_PKT_INFO_8821C)
+#define BIT_SET_BCNQ_PKT_INFO_8821C(x, v) \
+ (BIT_CLEAR_BCNQ_PKT_INFO_8821C(x) | BIT_BCNQ_PKT_INFO_8821C(v))
/* 2 REG_USEREG_SETTING_8821C */
#define BIT_NDPA_USEREG_8821C BIT(21)
#define BIT_SHIFT_RETRY_USEREG_8821C 19
#define BIT_MASK_RETRY_USEREG_8821C 0x3
-#define BIT_RETRY_USEREG_8821C(x) (((x) & BIT_MASK_RETRY_USEREG_8821C) << BIT_SHIFT_RETRY_USEREG_8821C)
-#define BIT_GET_RETRY_USEREG_8821C(x) (((x) >> BIT_SHIFT_RETRY_USEREG_8821C) & BIT_MASK_RETRY_USEREG_8821C)
-
+#define BIT_RETRY_USEREG_8821C(x) \
+ (((x) & BIT_MASK_RETRY_USEREG_8821C) << BIT_SHIFT_RETRY_USEREG_8821C)
+#define BITS_RETRY_USEREG_8821C \
+ (BIT_MASK_RETRY_USEREG_8821C << BIT_SHIFT_RETRY_USEREG_8821C)
+#define BIT_CLEAR_RETRY_USEREG_8821C(x) ((x) & (~BITS_RETRY_USEREG_8821C))
+#define BIT_GET_RETRY_USEREG_8821C(x) \
+ (((x) >> BIT_SHIFT_RETRY_USEREG_8821C) & BIT_MASK_RETRY_USEREG_8821C)
+#define BIT_SET_RETRY_USEREG_8821C(x, v) \
+ (BIT_CLEAR_RETRY_USEREG_8821C(x) | BIT_RETRY_USEREG_8821C(v))
#define BIT_SHIFT_TRYPKT_USEREG_8821C 17
#define BIT_MASK_TRYPKT_USEREG_8821C 0x3
-#define BIT_TRYPKT_USEREG_8821C(x) (((x) & BIT_MASK_TRYPKT_USEREG_8821C) << BIT_SHIFT_TRYPKT_USEREG_8821C)
-#define BIT_GET_TRYPKT_USEREG_8821C(x) (((x) >> BIT_SHIFT_TRYPKT_USEREG_8821C) & BIT_MASK_TRYPKT_USEREG_8821C)
+#define BIT_TRYPKT_USEREG_8821C(x) \
+ (((x) & BIT_MASK_TRYPKT_USEREG_8821C) << BIT_SHIFT_TRYPKT_USEREG_8821C)
+#define BITS_TRYPKT_USEREG_8821C \
+ (BIT_MASK_TRYPKT_USEREG_8821C << BIT_SHIFT_TRYPKT_USEREG_8821C)
+#define BIT_CLEAR_TRYPKT_USEREG_8821C(x) ((x) & (~BITS_TRYPKT_USEREG_8821C))
+#define BIT_GET_TRYPKT_USEREG_8821C(x) \
+ (((x) >> BIT_SHIFT_TRYPKT_USEREG_8821C) & BIT_MASK_TRYPKT_USEREG_8821C)
+#define BIT_SET_TRYPKT_USEREG_8821C(x, v) \
+ (BIT_CLEAR_TRYPKT_USEREG_8821C(x) | BIT_TRYPKT_USEREG_8821C(v))
#define BIT_CTLPKT_USEREG_8821C BIT(16)
@@ -6004,9 +11171,15 @@
#define BIT_SHIFT_AESIV_OFFSET_8821C 0
#define BIT_MASK_AESIV_OFFSET_8821C 0xfff
-#define BIT_AESIV_OFFSET_8821C(x) (((x) & BIT_MASK_AESIV_OFFSET_8821C) << BIT_SHIFT_AESIV_OFFSET_8821C)
-#define BIT_GET_AESIV_OFFSET_8821C(x) (((x) >> BIT_SHIFT_AESIV_OFFSET_8821C) & BIT_MASK_AESIV_OFFSET_8821C)
-
+#define BIT_AESIV_OFFSET_8821C(x) \
+ (((x) & BIT_MASK_AESIV_OFFSET_8821C) << BIT_SHIFT_AESIV_OFFSET_8821C)
+#define BITS_AESIV_OFFSET_8821C \
+ (BIT_MASK_AESIV_OFFSET_8821C << BIT_SHIFT_AESIV_OFFSET_8821C)
+#define BIT_CLEAR_AESIV_OFFSET_8821C(x) ((x) & (~BITS_AESIV_OFFSET_8821C))
+#define BIT_GET_AESIV_OFFSET_8821C(x) \
+ (((x) >> BIT_SHIFT_AESIV_OFFSET_8821C) & BIT_MASK_AESIV_OFFSET_8821C)
+#define BIT_SET_AESIV_OFFSET_8821C(x, v) \
+ (BIT_CLEAR_AESIV_OFFSET_8821C(x) | BIT_AESIV_OFFSET_8821C(v))
/* 2 REG_BF0_TIME_SETTING_8821C */
#define BIT_BF0_TIMER_SET_8821C BIT(31)
@@ -6016,15 +11189,30 @@
#define BIT_SHIFT_BF0_PRETIME_OVER_8821C 16
#define BIT_MASK_BF0_PRETIME_OVER_8821C 0xfff
-#define BIT_BF0_PRETIME_OVER_8821C(x) (((x) & BIT_MASK_BF0_PRETIME_OVER_8821C) << BIT_SHIFT_BF0_PRETIME_OVER_8821C)
-#define BIT_GET_BF0_PRETIME_OVER_8821C(x) (((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8821C) & BIT_MASK_BF0_PRETIME_OVER_8821C)
-
+#define BIT_BF0_PRETIME_OVER_8821C(x) \
+ (((x) & BIT_MASK_BF0_PRETIME_OVER_8821C) \
+ << BIT_SHIFT_BF0_PRETIME_OVER_8821C)
+#define BITS_BF0_PRETIME_OVER_8821C \
+ (BIT_MASK_BF0_PRETIME_OVER_8821C << BIT_SHIFT_BF0_PRETIME_OVER_8821C)
+#define BIT_CLEAR_BF0_PRETIME_OVER_8821C(x) \
+ ((x) & (~BITS_BF0_PRETIME_OVER_8821C))
+#define BIT_GET_BF0_PRETIME_OVER_8821C(x) \
+ (((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8821C) & \
+ BIT_MASK_BF0_PRETIME_OVER_8821C)
+#define BIT_SET_BF0_PRETIME_OVER_8821C(x, v) \
+ (BIT_CLEAR_BF0_PRETIME_OVER_8821C(x) | BIT_BF0_PRETIME_OVER_8821C(v))
#define BIT_SHIFT_BF0_LIFETIME_8821C 0
#define BIT_MASK_BF0_LIFETIME_8821C 0xffff
-#define BIT_BF0_LIFETIME_8821C(x) (((x) & BIT_MASK_BF0_LIFETIME_8821C) << BIT_SHIFT_BF0_LIFETIME_8821C)
-#define BIT_GET_BF0_LIFETIME_8821C(x) (((x) >> BIT_SHIFT_BF0_LIFETIME_8821C) & BIT_MASK_BF0_LIFETIME_8821C)
-
+#define BIT_BF0_LIFETIME_8821C(x) \
+ (((x) & BIT_MASK_BF0_LIFETIME_8821C) << BIT_SHIFT_BF0_LIFETIME_8821C)
+#define BITS_BF0_LIFETIME_8821C \
+ (BIT_MASK_BF0_LIFETIME_8821C << BIT_SHIFT_BF0_LIFETIME_8821C)
+#define BIT_CLEAR_BF0_LIFETIME_8821C(x) ((x) & (~BITS_BF0_LIFETIME_8821C))
+#define BIT_GET_BF0_LIFETIME_8821C(x) \
+ (((x) >> BIT_SHIFT_BF0_LIFETIME_8821C) & BIT_MASK_BF0_LIFETIME_8821C)
+#define BIT_SET_BF0_LIFETIME_8821C(x, v) \
+ (BIT_CLEAR_BF0_LIFETIME_8821C(x) | BIT_BF0_LIFETIME_8821C(v))
/* 2 REG_BF1_TIME_SETTING_8821C */
#define BIT_BF1_TIMER_SET_8821C BIT(31)
@@ -6034,15 +11222,30 @@
#define BIT_SHIFT_BF1_PRETIME_OVER_8821C 16
#define BIT_MASK_BF1_PRETIME_OVER_8821C 0xfff
-#define BIT_BF1_PRETIME_OVER_8821C(x) (((x) & BIT_MASK_BF1_PRETIME_OVER_8821C) << BIT_SHIFT_BF1_PRETIME_OVER_8821C)
-#define BIT_GET_BF1_PRETIME_OVER_8821C(x) (((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8821C) & BIT_MASK_BF1_PRETIME_OVER_8821C)
-
+#define BIT_BF1_PRETIME_OVER_8821C(x) \
+ (((x) & BIT_MASK_BF1_PRETIME_OVER_8821C) \
+ << BIT_SHIFT_BF1_PRETIME_OVER_8821C)
+#define BITS_BF1_PRETIME_OVER_8821C \
+ (BIT_MASK_BF1_PRETIME_OVER_8821C << BIT_SHIFT_BF1_PRETIME_OVER_8821C)
+#define BIT_CLEAR_BF1_PRETIME_OVER_8821C(x) \
+ ((x) & (~BITS_BF1_PRETIME_OVER_8821C))
+#define BIT_GET_BF1_PRETIME_OVER_8821C(x) \
+ (((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8821C) & \
+ BIT_MASK_BF1_PRETIME_OVER_8821C)
+#define BIT_SET_BF1_PRETIME_OVER_8821C(x, v) \
+ (BIT_CLEAR_BF1_PRETIME_OVER_8821C(x) | BIT_BF1_PRETIME_OVER_8821C(v))
#define BIT_SHIFT_BF1_LIFETIME_8821C 0
#define BIT_MASK_BF1_LIFETIME_8821C 0xffff
-#define BIT_BF1_LIFETIME_8821C(x) (((x) & BIT_MASK_BF1_LIFETIME_8821C) << BIT_SHIFT_BF1_LIFETIME_8821C)
-#define BIT_GET_BF1_LIFETIME_8821C(x) (((x) >> BIT_SHIFT_BF1_LIFETIME_8821C) & BIT_MASK_BF1_LIFETIME_8821C)
-
+#define BIT_BF1_LIFETIME_8821C(x) \
+ (((x) & BIT_MASK_BF1_LIFETIME_8821C) << BIT_SHIFT_BF1_LIFETIME_8821C)
+#define BITS_BF1_LIFETIME_8821C \
+ (BIT_MASK_BF1_LIFETIME_8821C << BIT_SHIFT_BF1_LIFETIME_8821C)
+#define BIT_CLEAR_BF1_LIFETIME_8821C(x) ((x) & (~BITS_BF1_LIFETIME_8821C))
+#define BIT_GET_BF1_LIFETIME_8821C(x) \
+ (((x) >> BIT_SHIFT_BF1_LIFETIME_8821C) & BIT_MASK_BF1_LIFETIME_8821C)
+#define BIT_SET_BF1_LIFETIME_8821C(x, v) \
+ (BIT_CLEAR_BF1_LIFETIME_8821C(x) | BIT_BF1_LIFETIME_8821C(v))
/* 2 REG_BF_TIMEOUT_EN_8821C */
#define BIT_EN_VHT_LDPC_8821C BIT(9)
@@ -6054,299 +11257,680 @@
#define BIT_SHIFT_MACID31_0_RELEASE_8821C 0
#define BIT_MASK_MACID31_0_RELEASE_8821C 0xffffffffL
-#define BIT_MACID31_0_RELEASE_8821C(x) (((x) & BIT_MASK_MACID31_0_RELEASE_8821C) << BIT_SHIFT_MACID31_0_RELEASE_8821C)
-#define BIT_GET_MACID31_0_RELEASE_8821C(x) (((x) >> BIT_SHIFT_MACID31_0_RELEASE_8821C) & BIT_MASK_MACID31_0_RELEASE_8821C)
-
+#define BIT_MACID31_0_RELEASE_8821C(x) \
+ (((x) & BIT_MASK_MACID31_0_RELEASE_8821C) \
+ << BIT_SHIFT_MACID31_0_RELEASE_8821C)
+#define BITS_MACID31_0_RELEASE_8821C \
+ (BIT_MASK_MACID31_0_RELEASE_8821C << BIT_SHIFT_MACID31_0_RELEASE_8821C)
+#define BIT_CLEAR_MACID31_0_RELEASE_8821C(x) \
+ ((x) & (~BITS_MACID31_0_RELEASE_8821C))
+#define BIT_GET_MACID31_0_RELEASE_8821C(x) \
+ (((x) >> BIT_SHIFT_MACID31_0_RELEASE_8821C) & \
+ BIT_MASK_MACID31_0_RELEASE_8821C)
+#define BIT_SET_MACID31_0_RELEASE_8821C(x, v) \
+ (BIT_CLEAR_MACID31_0_RELEASE_8821C(x) | BIT_MACID31_0_RELEASE_8821C(v))
/* 2 REG_MACID_RELEASE1_8821C */
#define BIT_SHIFT_MACID63_32_RELEASE_8821C 0
#define BIT_MASK_MACID63_32_RELEASE_8821C 0xffffffffL
-#define BIT_MACID63_32_RELEASE_8821C(x) (((x) & BIT_MASK_MACID63_32_RELEASE_8821C) << BIT_SHIFT_MACID63_32_RELEASE_8821C)
-#define BIT_GET_MACID63_32_RELEASE_8821C(x) (((x) >> BIT_SHIFT_MACID63_32_RELEASE_8821C) & BIT_MASK_MACID63_32_RELEASE_8821C)
-
+#define BIT_MACID63_32_RELEASE_8821C(x) \
+ (((x) & BIT_MASK_MACID63_32_RELEASE_8821C) \
+ << BIT_SHIFT_MACID63_32_RELEASE_8821C)
+#define BITS_MACID63_32_RELEASE_8821C \
+ (BIT_MASK_MACID63_32_RELEASE_8821C \
+ << BIT_SHIFT_MACID63_32_RELEASE_8821C)
+#define BIT_CLEAR_MACID63_32_RELEASE_8821C(x) \
+ ((x) & (~BITS_MACID63_32_RELEASE_8821C))
+#define BIT_GET_MACID63_32_RELEASE_8821C(x) \
+ (((x) >> BIT_SHIFT_MACID63_32_RELEASE_8821C) & \
+ BIT_MASK_MACID63_32_RELEASE_8821C)
+#define BIT_SET_MACID63_32_RELEASE_8821C(x, v) \
+ (BIT_CLEAR_MACID63_32_RELEASE_8821C(x) | \
+ BIT_MACID63_32_RELEASE_8821C(v))
/* 2 REG_MACID_RELEASE2_8821C */
#define BIT_SHIFT_MACID95_64_RELEASE_8821C 0
#define BIT_MASK_MACID95_64_RELEASE_8821C 0xffffffffL
-#define BIT_MACID95_64_RELEASE_8821C(x) (((x) & BIT_MASK_MACID95_64_RELEASE_8821C) << BIT_SHIFT_MACID95_64_RELEASE_8821C)
-#define BIT_GET_MACID95_64_RELEASE_8821C(x) (((x) >> BIT_SHIFT_MACID95_64_RELEASE_8821C) & BIT_MASK_MACID95_64_RELEASE_8821C)
-
+#define BIT_MACID95_64_RELEASE_8821C(x) \
+ (((x) & BIT_MASK_MACID95_64_RELEASE_8821C) \
+ << BIT_SHIFT_MACID95_64_RELEASE_8821C)
+#define BITS_MACID95_64_RELEASE_8821C \
+ (BIT_MASK_MACID95_64_RELEASE_8821C \
+ << BIT_SHIFT_MACID95_64_RELEASE_8821C)
+#define BIT_CLEAR_MACID95_64_RELEASE_8821C(x) \
+ ((x) & (~BITS_MACID95_64_RELEASE_8821C))
+#define BIT_GET_MACID95_64_RELEASE_8821C(x) \
+ (((x) >> BIT_SHIFT_MACID95_64_RELEASE_8821C) & \
+ BIT_MASK_MACID95_64_RELEASE_8821C)
+#define BIT_SET_MACID95_64_RELEASE_8821C(x, v) \
+ (BIT_CLEAR_MACID95_64_RELEASE_8821C(x) | \
+ BIT_MACID95_64_RELEASE_8821C(v))
/* 2 REG_MACID_RELEASE3_8821C */
#define BIT_SHIFT_MACID127_96_RELEASE_8821C 0
#define BIT_MASK_MACID127_96_RELEASE_8821C 0xffffffffL
-#define BIT_MACID127_96_RELEASE_8821C(x) (((x) & BIT_MASK_MACID127_96_RELEASE_8821C) << BIT_SHIFT_MACID127_96_RELEASE_8821C)
-#define BIT_GET_MACID127_96_RELEASE_8821C(x) (((x) >> BIT_SHIFT_MACID127_96_RELEASE_8821C) & BIT_MASK_MACID127_96_RELEASE_8821C)
-
+#define BIT_MACID127_96_RELEASE_8821C(x) \
+ (((x) & BIT_MASK_MACID127_96_RELEASE_8821C) \
+ << BIT_SHIFT_MACID127_96_RELEASE_8821C)
+#define BITS_MACID127_96_RELEASE_8821C \
+ (BIT_MASK_MACID127_96_RELEASE_8821C \
+ << BIT_SHIFT_MACID127_96_RELEASE_8821C)
+#define BIT_CLEAR_MACID127_96_RELEASE_8821C(x) \
+ ((x) & (~BITS_MACID127_96_RELEASE_8821C))
+#define BIT_GET_MACID127_96_RELEASE_8821C(x) \
+ (((x) >> BIT_SHIFT_MACID127_96_RELEASE_8821C) & \
+ BIT_MASK_MACID127_96_RELEASE_8821C)
+#define BIT_SET_MACID127_96_RELEASE_8821C(x, v) \
+ (BIT_CLEAR_MACID127_96_RELEASE_8821C(x) | \
+ BIT_MACID127_96_RELEASE_8821C(v))
/* 2 REG_MACID_RELEASE_SETTING_8821C */
#define BIT_MACID_VALUE_8821C BIT(7)
#define BIT_SHIFT_MACID_OFFSET_8821C 0
#define BIT_MASK_MACID_OFFSET_8821C 0x7f
-#define BIT_MACID_OFFSET_8821C(x) (((x) & BIT_MASK_MACID_OFFSET_8821C) << BIT_SHIFT_MACID_OFFSET_8821C)
-#define BIT_GET_MACID_OFFSET_8821C(x) (((x) >> BIT_SHIFT_MACID_OFFSET_8821C) & BIT_MASK_MACID_OFFSET_8821C)
-
+#define BIT_MACID_OFFSET_8821C(x) \
+ (((x) & BIT_MASK_MACID_OFFSET_8821C) << BIT_SHIFT_MACID_OFFSET_8821C)
+#define BITS_MACID_OFFSET_8821C \
+ (BIT_MASK_MACID_OFFSET_8821C << BIT_SHIFT_MACID_OFFSET_8821C)
+#define BIT_CLEAR_MACID_OFFSET_8821C(x) ((x) & (~BITS_MACID_OFFSET_8821C))
+#define BIT_GET_MACID_OFFSET_8821C(x) \
+ (((x) >> BIT_SHIFT_MACID_OFFSET_8821C) & BIT_MASK_MACID_OFFSET_8821C)
+#define BIT_SET_MACID_OFFSET_8821C(x, v) \
+ (BIT_CLEAR_MACID_OFFSET_8821C(x) | BIT_MACID_OFFSET_8821C(v))
/* 2 REG_FAST_EDCA_VOVI_SETTING_8821C */
#define BIT_SHIFT_VI_FAST_EDCA_TO_8821C 24
#define BIT_MASK_VI_FAST_EDCA_TO_8821C 0xff
-#define BIT_VI_FAST_EDCA_TO_8821C(x) (((x) & BIT_MASK_VI_FAST_EDCA_TO_8821C) << BIT_SHIFT_VI_FAST_EDCA_TO_8821C)
-#define BIT_GET_VI_FAST_EDCA_TO_8821C(x) (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8821C) & BIT_MASK_VI_FAST_EDCA_TO_8821C)
+#define BIT_VI_FAST_EDCA_TO_8821C(x) \
+ (((x) & BIT_MASK_VI_FAST_EDCA_TO_8821C) \
+ << BIT_SHIFT_VI_FAST_EDCA_TO_8821C)
+#define BITS_VI_FAST_EDCA_TO_8821C \
+ (BIT_MASK_VI_FAST_EDCA_TO_8821C << BIT_SHIFT_VI_FAST_EDCA_TO_8821C)
+#define BIT_CLEAR_VI_FAST_EDCA_TO_8821C(x) ((x) & (~BITS_VI_FAST_EDCA_TO_8821C))
+#define BIT_GET_VI_FAST_EDCA_TO_8821C(x) \
+ (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8821C) & \
+ BIT_MASK_VI_FAST_EDCA_TO_8821C)
+#define BIT_SET_VI_FAST_EDCA_TO_8821C(x, v) \
+ (BIT_CLEAR_VI_FAST_EDCA_TO_8821C(x) | BIT_VI_FAST_EDCA_TO_8821C(v))
#define BIT_VI_THRESHOLD_SEL_8821C BIT(23)
#define BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8821C 16
#define BIT_MASK_VI_FAST_EDCA_PKT_TH_8821C 0x7f
-#define BIT_VI_FAST_EDCA_PKT_TH_8821C(x) (((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8821C) << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8821C)
-#define BIT_GET_VI_FAST_EDCA_PKT_TH_8821C(x) (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8821C) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8821C)
-
+#define BIT_VI_FAST_EDCA_PKT_TH_8821C(x) \
+ (((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8821C) \
+ << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8821C)
+#define BITS_VI_FAST_EDCA_PKT_TH_8821C \
+ (BIT_MASK_VI_FAST_EDCA_PKT_TH_8821C \
+ << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8821C)
+#define BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8821C(x) \
+ ((x) & (~BITS_VI_FAST_EDCA_PKT_TH_8821C))
+#define BIT_GET_VI_FAST_EDCA_PKT_TH_8821C(x) \
+ (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8821C) & \
+ BIT_MASK_VI_FAST_EDCA_PKT_TH_8821C)
+#define BIT_SET_VI_FAST_EDCA_PKT_TH_8821C(x, v) \
+ (BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8821C(x) | \
+ BIT_VI_FAST_EDCA_PKT_TH_8821C(v))
#define BIT_SHIFT_VO_FAST_EDCA_TO_8821C 8
#define BIT_MASK_VO_FAST_EDCA_TO_8821C 0xff
-#define BIT_VO_FAST_EDCA_TO_8821C(x) (((x) & BIT_MASK_VO_FAST_EDCA_TO_8821C) << BIT_SHIFT_VO_FAST_EDCA_TO_8821C)
-#define BIT_GET_VO_FAST_EDCA_TO_8821C(x) (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8821C) & BIT_MASK_VO_FAST_EDCA_TO_8821C)
+#define BIT_VO_FAST_EDCA_TO_8821C(x) \
+ (((x) & BIT_MASK_VO_FAST_EDCA_TO_8821C) \
+ << BIT_SHIFT_VO_FAST_EDCA_TO_8821C)
+#define BITS_VO_FAST_EDCA_TO_8821C \
+ (BIT_MASK_VO_FAST_EDCA_TO_8821C << BIT_SHIFT_VO_FAST_EDCA_TO_8821C)
+#define BIT_CLEAR_VO_FAST_EDCA_TO_8821C(x) ((x) & (~BITS_VO_FAST_EDCA_TO_8821C))
+#define BIT_GET_VO_FAST_EDCA_TO_8821C(x) \
+ (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8821C) & \
+ BIT_MASK_VO_FAST_EDCA_TO_8821C)
+#define BIT_SET_VO_FAST_EDCA_TO_8821C(x, v) \
+ (BIT_CLEAR_VO_FAST_EDCA_TO_8821C(x) | BIT_VO_FAST_EDCA_TO_8821C(v))
#define BIT_VO_THRESHOLD_SEL_8821C BIT(7)
#define BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8821C 0
#define BIT_MASK_VO_FAST_EDCA_PKT_TH_8821C 0x7f
-#define BIT_VO_FAST_EDCA_PKT_TH_8821C(x) (((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8821C) << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8821C)
-#define BIT_GET_VO_FAST_EDCA_PKT_TH_8821C(x) (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8821C) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8821C)
-
+#define BIT_VO_FAST_EDCA_PKT_TH_8821C(x) \
+ (((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8821C) \
+ << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8821C)
+#define BITS_VO_FAST_EDCA_PKT_TH_8821C \
+ (BIT_MASK_VO_FAST_EDCA_PKT_TH_8821C \
+ << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8821C)
+#define BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8821C(x) \
+ ((x) & (~BITS_VO_FAST_EDCA_PKT_TH_8821C))
+#define BIT_GET_VO_FAST_EDCA_PKT_TH_8821C(x) \
+ (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8821C) & \
+ BIT_MASK_VO_FAST_EDCA_PKT_TH_8821C)
+#define BIT_SET_VO_FAST_EDCA_PKT_TH_8821C(x, v) \
+ (BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8821C(x) | \
+ BIT_VO_FAST_EDCA_PKT_TH_8821C(v))
/* 2 REG_FAST_EDCA_BEBK_SETTING_8821C */
#define BIT_SHIFT_BK_FAST_EDCA_TO_8821C 24
#define BIT_MASK_BK_FAST_EDCA_TO_8821C 0xff
-#define BIT_BK_FAST_EDCA_TO_8821C(x) (((x) & BIT_MASK_BK_FAST_EDCA_TO_8821C) << BIT_SHIFT_BK_FAST_EDCA_TO_8821C)
-#define BIT_GET_BK_FAST_EDCA_TO_8821C(x) (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8821C) & BIT_MASK_BK_FAST_EDCA_TO_8821C)
+#define BIT_BK_FAST_EDCA_TO_8821C(x) \
+ (((x) & BIT_MASK_BK_FAST_EDCA_TO_8821C) \
+ << BIT_SHIFT_BK_FAST_EDCA_TO_8821C)
+#define BITS_BK_FAST_EDCA_TO_8821C \
+ (BIT_MASK_BK_FAST_EDCA_TO_8821C << BIT_SHIFT_BK_FAST_EDCA_TO_8821C)
+#define BIT_CLEAR_BK_FAST_EDCA_TO_8821C(x) ((x) & (~BITS_BK_FAST_EDCA_TO_8821C))
+#define BIT_GET_BK_FAST_EDCA_TO_8821C(x) \
+ (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8821C) & \
+ BIT_MASK_BK_FAST_EDCA_TO_8821C)
+#define BIT_SET_BK_FAST_EDCA_TO_8821C(x, v) \
+ (BIT_CLEAR_BK_FAST_EDCA_TO_8821C(x) | BIT_BK_FAST_EDCA_TO_8821C(v))
#define BIT_BK_THRESHOLD_SEL_8821C BIT(23)
#define BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8821C 16
#define BIT_MASK_BK_FAST_EDCA_PKT_TH_8821C 0x7f
-#define BIT_BK_FAST_EDCA_PKT_TH_8821C(x) (((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8821C) << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8821C)
-#define BIT_GET_BK_FAST_EDCA_PKT_TH_8821C(x) (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8821C) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8821C)
-
+#define BIT_BK_FAST_EDCA_PKT_TH_8821C(x) \
+ (((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8821C) \
+ << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8821C)
+#define BITS_BK_FAST_EDCA_PKT_TH_8821C \
+ (BIT_MASK_BK_FAST_EDCA_PKT_TH_8821C \
+ << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8821C)
+#define BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8821C(x) \
+ ((x) & (~BITS_BK_FAST_EDCA_PKT_TH_8821C))
+#define BIT_GET_BK_FAST_EDCA_PKT_TH_8821C(x) \
+ (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8821C) & \
+ BIT_MASK_BK_FAST_EDCA_PKT_TH_8821C)
+#define BIT_SET_BK_FAST_EDCA_PKT_TH_8821C(x, v) \
+ (BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8821C(x) | \
+ BIT_BK_FAST_EDCA_PKT_TH_8821C(v))
#define BIT_SHIFT_BE_FAST_EDCA_TO_8821C 8
#define BIT_MASK_BE_FAST_EDCA_TO_8821C 0xff
-#define BIT_BE_FAST_EDCA_TO_8821C(x) (((x) & BIT_MASK_BE_FAST_EDCA_TO_8821C) << BIT_SHIFT_BE_FAST_EDCA_TO_8821C)
-#define BIT_GET_BE_FAST_EDCA_TO_8821C(x) (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8821C) & BIT_MASK_BE_FAST_EDCA_TO_8821C)
+#define BIT_BE_FAST_EDCA_TO_8821C(x) \
+ (((x) & BIT_MASK_BE_FAST_EDCA_TO_8821C) \
+ << BIT_SHIFT_BE_FAST_EDCA_TO_8821C)
+#define BITS_BE_FAST_EDCA_TO_8821C \
+ (BIT_MASK_BE_FAST_EDCA_TO_8821C << BIT_SHIFT_BE_FAST_EDCA_TO_8821C)
+#define BIT_CLEAR_BE_FAST_EDCA_TO_8821C(x) ((x) & (~BITS_BE_FAST_EDCA_TO_8821C))
+#define BIT_GET_BE_FAST_EDCA_TO_8821C(x) \
+ (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8821C) & \
+ BIT_MASK_BE_FAST_EDCA_TO_8821C)
+#define BIT_SET_BE_FAST_EDCA_TO_8821C(x, v) \
+ (BIT_CLEAR_BE_FAST_EDCA_TO_8821C(x) | BIT_BE_FAST_EDCA_TO_8821C(v))
#define BIT_BE_THRESHOLD_SEL_8821C BIT(7)
#define BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8821C 0
#define BIT_MASK_BE_FAST_EDCA_PKT_TH_8821C 0x7f
-#define BIT_BE_FAST_EDCA_PKT_TH_8821C(x) (((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8821C) << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8821C)
-#define BIT_GET_BE_FAST_EDCA_PKT_TH_8821C(x) (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8821C) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8821C)
-
+#define BIT_BE_FAST_EDCA_PKT_TH_8821C(x) \
+ (((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8821C) \
+ << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8821C)
+#define BITS_BE_FAST_EDCA_PKT_TH_8821C \
+ (BIT_MASK_BE_FAST_EDCA_PKT_TH_8821C \
+ << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8821C)
+#define BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8821C(x) \
+ ((x) & (~BITS_BE_FAST_EDCA_PKT_TH_8821C))
+#define BIT_GET_BE_FAST_EDCA_PKT_TH_8821C(x) \
+ (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8821C) & \
+ BIT_MASK_BE_FAST_EDCA_PKT_TH_8821C)
+#define BIT_SET_BE_FAST_EDCA_PKT_TH_8821C(x, v) \
+ (BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8821C(x) | \
+ BIT_BE_FAST_EDCA_PKT_TH_8821C(v))
/* 2 REG_MACID_DROP0_8821C */
#define BIT_SHIFT_MACID31_0_DROP_8821C 0
#define BIT_MASK_MACID31_0_DROP_8821C 0xffffffffL
-#define BIT_MACID31_0_DROP_8821C(x) (((x) & BIT_MASK_MACID31_0_DROP_8821C) << BIT_SHIFT_MACID31_0_DROP_8821C)
-#define BIT_GET_MACID31_0_DROP_8821C(x) (((x) >> BIT_SHIFT_MACID31_0_DROP_8821C) & BIT_MASK_MACID31_0_DROP_8821C)
-
+#define BIT_MACID31_0_DROP_8821C(x) \
+ (((x) & BIT_MASK_MACID31_0_DROP_8821C) \
+ << BIT_SHIFT_MACID31_0_DROP_8821C)
+#define BITS_MACID31_0_DROP_8821C \
+ (BIT_MASK_MACID31_0_DROP_8821C << BIT_SHIFT_MACID31_0_DROP_8821C)
+#define BIT_CLEAR_MACID31_0_DROP_8821C(x) ((x) & (~BITS_MACID31_0_DROP_8821C))
+#define BIT_GET_MACID31_0_DROP_8821C(x) \
+ (((x) >> BIT_SHIFT_MACID31_0_DROP_8821C) & \
+ BIT_MASK_MACID31_0_DROP_8821C)
+#define BIT_SET_MACID31_0_DROP_8821C(x, v) \
+ (BIT_CLEAR_MACID31_0_DROP_8821C(x) | BIT_MACID31_0_DROP_8821C(v))
/* 2 REG_MACID_DROP1_8821C */
#define BIT_SHIFT_MACID63_32_DROP_8821C 0
#define BIT_MASK_MACID63_32_DROP_8821C 0xffffffffL
-#define BIT_MACID63_32_DROP_8821C(x) (((x) & BIT_MASK_MACID63_32_DROP_8821C) << BIT_SHIFT_MACID63_32_DROP_8821C)
-#define BIT_GET_MACID63_32_DROP_8821C(x) (((x) >> BIT_SHIFT_MACID63_32_DROP_8821C) & BIT_MASK_MACID63_32_DROP_8821C)
-
+#define BIT_MACID63_32_DROP_8821C(x) \
+ (((x) & BIT_MASK_MACID63_32_DROP_8821C) \
+ << BIT_SHIFT_MACID63_32_DROP_8821C)
+#define BITS_MACID63_32_DROP_8821C \
+ (BIT_MASK_MACID63_32_DROP_8821C << BIT_SHIFT_MACID63_32_DROP_8821C)
+#define BIT_CLEAR_MACID63_32_DROP_8821C(x) ((x) & (~BITS_MACID63_32_DROP_8821C))
+#define BIT_GET_MACID63_32_DROP_8821C(x) \
+ (((x) >> BIT_SHIFT_MACID63_32_DROP_8821C) & \
+ BIT_MASK_MACID63_32_DROP_8821C)
+#define BIT_SET_MACID63_32_DROP_8821C(x, v) \
+ (BIT_CLEAR_MACID63_32_DROP_8821C(x) | BIT_MACID63_32_DROP_8821C(v))
/* 2 REG_MACID_DROP2_8821C */
#define BIT_SHIFT_MACID95_64_DROP_8821C 0
#define BIT_MASK_MACID95_64_DROP_8821C 0xffffffffL
-#define BIT_MACID95_64_DROP_8821C(x) (((x) & BIT_MASK_MACID95_64_DROP_8821C) << BIT_SHIFT_MACID95_64_DROP_8821C)
-#define BIT_GET_MACID95_64_DROP_8821C(x) (((x) >> BIT_SHIFT_MACID95_64_DROP_8821C) & BIT_MASK_MACID95_64_DROP_8821C)
-
+#define BIT_MACID95_64_DROP_8821C(x) \
+ (((x) & BIT_MASK_MACID95_64_DROP_8821C) \
+ << BIT_SHIFT_MACID95_64_DROP_8821C)
+#define BITS_MACID95_64_DROP_8821C \
+ (BIT_MASK_MACID95_64_DROP_8821C << BIT_SHIFT_MACID95_64_DROP_8821C)
+#define BIT_CLEAR_MACID95_64_DROP_8821C(x) ((x) & (~BITS_MACID95_64_DROP_8821C))
+#define BIT_GET_MACID95_64_DROP_8821C(x) \
+ (((x) >> BIT_SHIFT_MACID95_64_DROP_8821C) & \
+ BIT_MASK_MACID95_64_DROP_8821C)
+#define BIT_SET_MACID95_64_DROP_8821C(x, v) \
+ (BIT_CLEAR_MACID95_64_DROP_8821C(x) | BIT_MACID95_64_DROP_8821C(v))
/* 2 REG_MACID_DROP3_8821C */
#define BIT_SHIFT_MACID127_96_DROP_8821C 0
#define BIT_MASK_MACID127_96_DROP_8821C 0xffffffffL
-#define BIT_MACID127_96_DROP_8821C(x) (((x) & BIT_MASK_MACID127_96_DROP_8821C) << BIT_SHIFT_MACID127_96_DROP_8821C)
-#define BIT_GET_MACID127_96_DROP_8821C(x) (((x) >> BIT_SHIFT_MACID127_96_DROP_8821C) & BIT_MASK_MACID127_96_DROP_8821C)
-
+#define BIT_MACID127_96_DROP_8821C(x) \
+ (((x) & BIT_MASK_MACID127_96_DROP_8821C) \
+ << BIT_SHIFT_MACID127_96_DROP_8821C)
+#define BITS_MACID127_96_DROP_8821C \
+ (BIT_MASK_MACID127_96_DROP_8821C << BIT_SHIFT_MACID127_96_DROP_8821C)
+#define BIT_CLEAR_MACID127_96_DROP_8821C(x) \
+ ((x) & (~BITS_MACID127_96_DROP_8821C))
+#define BIT_GET_MACID127_96_DROP_8821C(x) \
+ (((x) >> BIT_SHIFT_MACID127_96_DROP_8821C) & \
+ BIT_MASK_MACID127_96_DROP_8821C)
+#define BIT_SET_MACID127_96_DROP_8821C(x, v) \
+ (BIT_CLEAR_MACID127_96_DROP_8821C(x) | BIT_MACID127_96_DROP_8821C(v))
/* 2 REG_R_MACID_RELEASE_SUCCESS_0_8821C */
#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8821C 0
#define BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8821C 0xffffffffL
-#define BIT_R_MACID_RELEASE_SUCCESS_0_8821C(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8821C) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8821C)
-#define BIT_GET_R_MACID_RELEASE_SUCCESS_0_8821C(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8821C) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8821C)
-
+#define BIT_R_MACID_RELEASE_SUCCESS_0_8821C(x) \
+ (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8821C) \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8821C)
+#define BITS_R_MACID_RELEASE_SUCCESS_0_8821C \
+ (BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8821C \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8821C)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8821C(x) \
+ ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_0_8821C))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_0_8821C(x) \
+ (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8821C) & \
+ BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8821C)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_0_8821C(x, v) \
+ (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8821C(x) | \
+ BIT_R_MACID_RELEASE_SUCCESS_0_8821C(v))
/* 2 REG_R_MACID_RELEASE_SUCCESS_1_8821C */
-#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8821C 0
-#define BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8821C 0xffffffffL
-#define BIT_R_MACID_RELEASE_SUCCESS_1_8821C(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8821C) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8821C)
-#define BIT_GET_R_MACID_RELEASE_SUCCESS_1_8821C(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8821C) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8821C)
-
-
-/* 2 REG_R_MACID_RELEASE_SUCCESS_2_8821C */
-
-#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8821C 0
-#define BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8821C 0xffffffffL
-#define BIT_R_MACID_RELEASE_SUCCESS_2_8821C(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8821C) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8821C)
-#define BIT_GET_R_MACID_RELEASE_SUCCESS_2_8821C(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8821C) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8821C)
-
-
-/* 2 REG_R_MACID_RELEASE_SUCCESS_3_8821C */
-
-#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8821C 0
-#define BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8821C 0xffffffffL
-#define BIT_R_MACID_RELEASE_SUCCESS_3_8821C(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8821C) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8821C)
-#define BIT_GET_R_MACID_RELEASE_SUCCESS_3_8821C(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8821C) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8821C)
-
-
-/* 2 REG_MGG_FIFO_CRTL_8821C */
-#define BIT_R_MGG_FIFO_EN_8821C BIT(31)
-
-#define BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8821C 28
-#define BIT_MASK_R_MGG_FIFO_PG_SIZE_8821C 0x7
-#define BIT_R_MGG_FIFO_PG_SIZE_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_PG_SIZE_8821C) << BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8821C)
-#define BIT_GET_R_MGG_FIFO_PG_SIZE_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8821C) & BIT_MASK_R_MGG_FIFO_PG_SIZE_8821C)
-
-
-#define BIT_SHIFT_R_MGG_FIFO_START_PG_8821C 16
-#define BIT_MASK_R_MGG_FIFO_START_PG_8821C 0xfff
-#define BIT_R_MGG_FIFO_START_PG_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_START_PG_8821C) << BIT_SHIFT_R_MGG_FIFO_START_PG_8821C)
-#define BIT_GET_R_MGG_FIFO_START_PG_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_START_PG_8821C) & BIT_MASK_R_MGG_FIFO_START_PG_8821C)
-
-
-#define BIT_SHIFT_R_MGG_FIFO_SIZE_8821C 14
-#define BIT_MASK_R_MGG_FIFO_SIZE_8821C 0x3
-#define BIT_R_MGG_FIFO_SIZE_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_SIZE_8821C) << BIT_SHIFT_R_MGG_FIFO_SIZE_8821C)
-#define BIT_GET_R_MGG_FIFO_SIZE_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_SIZE_8821C) & BIT_MASK_R_MGG_FIFO_SIZE_8821C)
-
-#define BIT_R_MGG_FIFO_PAUSE_8821C BIT(13)
-
-#define BIT_SHIFT_R_MGG_FIFO_RPTR_8821C 8
-#define BIT_MASK_R_MGG_FIFO_RPTR_8821C 0x1f
-#define BIT_R_MGG_FIFO_RPTR_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_RPTR_8821C) << BIT_SHIFT_R_MGG_FIFO_RPTR_8821C)
-#define BIT_GET_R_MGG_FIFO_RPTR_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_RPTR_8821C) & BIT_MASK_R_MGG_FIFO_RPTR_8821C)
-
-#define BIT_R_MGG_FIFO_OV_8821C BIT(7)
-#define BIT_R_MGG_FIFO_WPTR_ERROR_8821C BIT(6)
-#define BIT_R_EN_CPU_LIFETIME_8821C BIT(5)
-
-#define BIT_SHIFT_R_MGG_FIFO_WPTR_8821C 0
-#define BIT_MASK_R_MGG_FIFO_WPTR_8821C 0x1f
-#define BIT_R_MGG_FIFO_WPTR_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_WPTR_8821C) << BIT_SHIFT_R_MGG_FIFO_WPTR_8821C)
-#define BIT_GET_R_MGG_FIFO_WPTR_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_WPTR_8821C) & BIT_MASK_R_MGG_FIFO_WPTR_8821C)
-
-
-/* 2 REG_MGG_FIFO_INT_8821C */
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8821C 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8821C 0xffffffffL
+#define BIT_R_MACID_RELEASE_SUCCESS_1_8821C(x) \
+ (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8821C) \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8821C)
+#define BITS_R_MACID_RELEASE_SUCCESS_1_8821C \
+ (BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8821C \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8821C)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8821C(x) \
+ ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_1_8821C))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_1_8821C(x) \
+ (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8821C) & \
+ BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8821C)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_1_8821C(x, v) \
+ (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8821C(x) | \
+ BIT_R_MACID_RELEASE_SUCCESS_1_8821C(v))
-#define BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8821C 16
-#define BIT_MASK_R_MGG_FIFO_INT_FLAG_8821C 0xffff
-#define BIT_R_MGG_FIFO_INT_FLAG_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_INT_FLAG_8821C) << BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8821C)
-#define BIT_GET_R_MGG_FIFO_INT_FLAG_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8821C) & BIT_MASK_R_MGG_FIFO_INT_FLAG_8821C)
+/* 2 REG_R_MACID_RELEASE_SUCCESS_2_8821C */
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8821C 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8821C 0xffffffffL
+#define BIT_R_MACID_RELEASE_SUCCESS_2_8821C(x) \
+ (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8821C) \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8821C)
+#define BITS_R_MACID_RELEASE_SUCCESS_2_8821C \
+ (BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8821C \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8821C)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8821C(x) \
+ ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_2_8821C))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_2_8821C(x) \
+ (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8821C) & \
+ BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8821C)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_2_8821C(x, v) \
+ (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8821C(x) | \
+ BIT_R_MACID_RELEASE_SUCCESS_2_8821C(v))
-#define BIT_SHIFT_R_MGG_FIFO_INT_MASK_8821C 0
-#define BIT_MASK_R_MGG_FIFO_INT_MASK_8821C 0xffff
-#define BIT_R_MGG_FIFO_INT_MASK_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_INT_MASK_8821C) << BIT_SHIFT_R_MGG_FIFO_INT_MASK_8821C)
-#define BIT_GET_R_MGG_FIFO_INT_MASK_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_MASK_8821C) & BIT_MASK_R_MGG_FIFO_INT_MASK_8821C)
+/* 2 REG_R_MACID_RELEASE_SUCCESS_3_8821C */
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8821C 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8821C 0xffffffffL
+#define BIT_R_MACID_RELEASE_SUCCESS_3_8821C(x) \
+ (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8821C) \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8821C)
+#define BITS_R_MACID_RELEASE_SUCCESS_3_8821C \
+ (BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8821C \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8821C)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8821C(x) \
+ ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_3_8821C))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_3_8821C(x) \
+ (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8821C) & \
+ BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8821C)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_3_8821C(x, v) \
+ (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8821C(x) | \
+ BIT_R_MACID_RELEASE_SUCCESS_3_8821C(v))
+
+/* 2 REG_MGQ_FIFO_WRITE_POINTER_8821C */
+#define BIT_MGQ_FIFO_OV_8821C BIT(7)
+#define BIT_MGQ_FIFO_WPTR_ERROR_8821C BIT(6)
+#define BIT_EN_MGQ_FIFO_LIFETIME_8821C BIT(5)
+
+#define BIT_SHIFT_MGQ_FIFO_WPTR_8821C 0
+#define BIT_MASK_MGQ_FIFO_WPTR_8821C 0x1f
+#define BIT_MGQ_FIFO_WPTR_8821C(x) \
+ (((x) & BIT_MASK_MGQ_FIFO_WPTR_8821C) << BIT_SHIFT_MGQ_FIFO_WPTR_8821C)
+#define BITS_MGQ_FIFO_WPTR_8821C \
+ (BIT_MASK_MGQ_FIFO_WPTR_8821C << BIT_SHIFT_MGQ_FIFO_WPTR_8821C)
+#define BIT_CLEAR_MGQ_FIFO_WPTR_8821C(x) ((x) & (~BITS_MGQ_FIFO_WPTR_8821C))
+#define BIT_GET_MGQ_FIFO_WPTR_8821C(x) \
+ (((x) >> BIT_SHIFT_MGQ_FIFO_WPTR_8821C) & BIT_MASK_MGQ_FIFO_WPTR_8821C)
+#define BIT_SET_MGQ_FIFO_WPTR_8821C(x, v) \
+ (BIT_CLEAR_MGQ_FIFO_WPTR_8821C(x) | BIT_MGQ_FIFO_WPTR_8821C(v))
+
+/* 2 REG_MGQ_FIFO_READ_POINTER_8821C */
+
+#define BIT_SHIFT_MGQ_FIFO_SIZE_8821C 14
+#define BIT_MASK_MGQ_FIFO_SIZE_8821C 0x3
+#define BIT_MGQ_FIFO_SIZE_8821C(x) \
+ (((x) & BIT_MASK_MGQ_FIFO_SIZE_8821C) << BIT_SHIFT_MGQ_FIFO_SIZE_8821C)
+#define BITS_MGQ_FIFO_SIZE_8821C \
+ (BIT_MASK_MGQ_FIFO_SIZE_8821C << BIT_SHIFT_MGQ_FIFO_SIZE_8821C)
+#define BIT_CLEAR_MGQ_FIFO_SIZE_8821C(x) ((x) & (~BITS_MGQ_FIFO_SIZE_8821C))
+#define BIT_GET_MGQ_FIFO_SIZE_8821C(x) \
+ (((x) >> BIT_SHIFT_MGQ_FIFO_SIZE_8821C) & BIT_MASK_MGQ_FIFO_SIZE_8821C)
+#define BIT_SET_MGQ_FIFO_SIZE_8821C(x, v) \
+ (BIT_CLEAR_MGQ_FIFO_SIZE_8821C(x) | BIT_MGQ_FIFO_SIZE_8821C(v))
+
+#define BIT_MGQ_FIFO_PAUSE_8821C BIT(13)
+
+#define BIT_SHIFT_MGQ_FIFO_RPTR_8821C 8
+#define BIT_MASK_MGQ_FIFO_RPTR_8821C 0x1f
+#define BIT_MGQ_FIFO_RPTR_8821C(x) \
+ (((x) & BIT_MASK_MGQ_FIFO_RPTR_8821C) << BIT_SHIFT_MGQ_FIFO_RPTR_8821C)
+#define BITS_MGQ_FIFO_RPTR_8821C \
+ (BIT_MASK_MGQ_FIFO_RPTR_8821C << BIT_SHIFT_MGQ_FIFO_RPTR_8821C)
+#define BIT_CLEAR_MGQ_FIFO_RPTR_8821C(x) ((x) & (~BITS_MGQ_FIFO_RPTR_8821C))
+#define BIT_GET_MGQ_FIFO_RPTR_8821C(x) \
+ (((x) >> BIT_SHIFT_MGQ_FIFO_RPTR_8821C) & BIT_MASK_MGQ_FIFO_RPTR_8821C)
+#define BIT_SET_MGQ_FIFO_RPTR_8821C(x, v) \
+ (BIT_CLEAR_MGQ_FIFO_RPTR_8821C(x) | BIT_MGQ_FIFO_RPTR_8821C(v))
+
+/* 2 REG_MGQ_FIFO_ENABLE_8821C */
+#define BIT_MGQ_FIFO_EN_8821C BIT(15)
+
+#define BIT_SHIFT_MGQ_FIFO_PG_SIZE_8821C 12
+#define BIT_MASK_MGQ_FIFO_PG_SIZE_8821C 0x7
+#define BIT_MGQ_FIFO_PG_SIZE_8821C(x) \
+ (((x) & BIT_MASK_MGQ_FIFO_PG_SIZE_8821C) \
+ << BIT_SHIFT_MGQ_FIFO_PG_SIZE_8821C)
+#define BITS_MGQ_FIFO_PG_SIZE_8821C \
+ (BIT_MASK_MGQ_FIFO_PG_SIZE_8821C << BIT_SHIFT_MGQ_FIFO_PG_SIZE_8821C)
+#define BIT_CLEAR_MGQ_FIFO_PG_SIZE_8821C(x) \
+ ((x) & (~BITS_MGQ_FIFO_PG_SIZE_8821C))
+#define BIT_GET_MGQ_FIFO_PG_SIZE_8821C(x) \
+ (((x) >> BIT_SHIFT_MGQ_FIFO_PG_SIZE_8821C) & \
+ BIT_MASK_MGQ_FIFO_PG_SIZE_8821C)
+#define BIT_SET_MGQ_FIFO_PG_SIZE_8821C(x, v) \
+ (BIT_CLEAR_MGQ_FIFO_PG_SIZE_8821C(x) | BIT_MGQ_FIFO_PG_SIZE_8821C(v))
+
+#define BIT_SHIFT_MGQ_FIFO_START_PG_8821C 0
+#define BIT_MASK_MGQ_FIFO_START_PG_8821C 0xfff
+#define BIT_MGQ_FIFO_START_PG_8821C(x) \
+ (((x) & BIT_MASK_MGQ_FIFO_START_PG_8821C) \
+ << BIT_SHIFT_MGQ_FIFO_START_PG_8821C)
+#define BITS_MGQ_FIFO_START_PG_8821C \
+ (BIT_MASK_MGQ_FIFO_START_PG_8821C << BIT_SHIFT_MGQ_FIFO_START_PG_8821C)
+#define BIT_CLEAR_MGQ_FIFO_START_PG_8821C(x) \
+ ((x) & (~BITS_MGQ_FIFO_START_PG_8821C))
+#define BIT_GET_MGQ_FIFO_START_PG_8821C(x) \
+ (((x) >> BIT_SHIFT_MGQ_FIFO_START_PG_8821C) & \
+ BIT_MASK_MGQ_FIFO_START_PG_8821C)
+#define BIT_SET_MGQ_FIFO_START_PG_8821C(x, v) \
+ (BIT_CLEAR_MGQ_FIFO_START_PG_8821C(x) | BIT_MGQ_FIFO_START_PG_8821C(v))
+
+/* 2 REG_MGQ_FIFO_RELEASE_INT_MASK_8821C */
+
+#define BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8821C 0
+#define BIT_MASK_MGQ_FIFO_REL_INT_MASK_8821C 0xffff
+#define BIT_MGQ_FIFO_REL_INT_MASK_8821C(x) \
+ (((x) & BIT_MASK_MGQ_FIFO_REL_INT_MASK_8821C) \
+ << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8821C)
+#define BITS_MGQ_FIFO_REL_INT_MASK_8821C \
+ (BIT_MASK_MGQ_FIFO_REL_INT_MASK_8821C \
+ << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8821C)
+#define BIT_CLEAR_MGQ_FIFO_REL_INT_MASK_8821C(x) \
+ ((x) & (~BITS_MGQ_FIFO_REL_INT_MASK_8821C))
+#define BIT_GET_MGQ_FIFO_REL_INT_MASK_8821C(x) \
+ (((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8821C) & \
+ BIT_MASK_MGQ_FIFO_REL_INT_MASK_8821C)
+#define BIT_SET_MGQ_FIFO_REL_INT_MASK_8821C(x, v) \
+ (BIT_CLEAR_MGQ_FIFO_REL_INT_MASK_8821C(x) | \
+ BIT_MGQ_FIFO_REL_INT_MASK_8821C(v))
+
+/* 2 REG_MGQ_FIFO_RELEASE_INT_FLAG_8821C */
+
+#define BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8821C 0
+#define BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8821C 0xffff
+#define BIT_MGQ_FIFO_REL_INT_FLAG_8821C(x) \
+ (((x) & BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8821C) \
+ << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8821C)
+#define BITS_MGQ_FIFO_REL_INT_FLAG_8821C \
+ (BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8821C \
+ << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8821C)
+#define BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG_8821C(x) \
+ ((x) & (~BITS_MGQ_FIFO_REL_INT_FLAG_8821C))
+#define BIT_GET_MGQ_FIFO_REL_INT_FLAG_8821C(x) \
+ (((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8821C) & \
+ BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8821C)
+#define BIT_SET_MGQ_FIFO_REL_INT_FLAG_8821C(x, v) \
+ (BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG_8821C(x) | \
+ BIT_MGQ_FIFO_REL_INT_FLAG_8821C(v))
+
+/* 2 REG_MGQ_FIFO_VALID_MAP_8821C */
+
+#define BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8821C 0
+#define BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8821C 0xffff
+#define BIT_MGQ_FIFO_PKT_VALID_MAP_8821C(x) \
+ (((x) & BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8821C) \
+ << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8821C)
+#define BITS_MGQ_FIFO_PKT_VALID_MAP_8821C \
+ (BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8821C \
+ << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8821C)
+#define BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP_8821C(x) \
+ ((x) & (~BITS_MGQ_FIFO_PKT_VALID_MAP_8821C))
+#define BIT_GET_MGQ_FIFO_PKT_VALID_MAP_8821C(x) \
+ (((x) >> BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8821C) & \
+ BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8821C)
+#define BIT_SET_MGQ_FIFO_PKT_VALID_MAP_8821C(x, v) \
+ (BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP_8821C(x) | \
+ BIT_MGQ_FIFO_PKT_VALID_MAP_8821C(v))
+
+/* 2 REG_MGQ_FIFO_LIFETIME_8821C */
+
+#define BIT_SHIFT_MGQ_FIFO_LIFETIME_8821C 0
+#define BIT_MASK_MGQ_FIFO_LIFETIME_8821C 0xffff
+#define BIT_MGQ_FIFO_LIFETIME_8821C(x) \
+ (((x) & BIT_MASK_MGQ_FIFO_LIFETIME_8821C) \
+ << BIT_SHIFT_MGQ_FIFO_LIFETIME_8821C)
+#define BITS_MGQ_FIFO_LIFETIME_8821C \
+ (BIT_MASK_MGQ_FIFO_LIFETIME_8821C << BIT_SHIFT_MGQ_FIFO_LIFETIME_8821C)
+#define BIT_CLEAR_MGQ_FIFO_LIFETIME_8821C(x) \
+ ((x) & (~BITS_MGQ_FIFO_LIFETIME_8821C))
+#define BIT_GET_MGQ_FIFO_LIFETIME_8821C(x) \
+ (((x) >> BIT_SHIFT_MGQ_FIFO_LIFETIME_8821C) & \
+ BIT_MASK_MGQ_FIFO_LIFETIME_8821C)
+#define BIT_SET_MGQ_FIFO_LIFETIME_8821C(x, v) \
+ (BIT_CLEAR_MGQ_FIFO_LIFETIME_8821C(x) | BIT_MGQ_FIFO_LIFETIME_8821C(v))
-/* 2 REG_MGG_FIFO_LIFETIME_8821C */
+/* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C */
-#define BIT_SHIFT_R_MGG_FIFO_LIFETIME_8821C 16
-#define BIT_MASK_R_MGG_FIFO_LIFETIME_8821C 0xffff
-#define BIT_R_MGG_FIFO_LIFETIME_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_LIFETIME_8821C) << BIT_SHIFT_R_MGG_FIFO_LIFETIME_8821C)
-#define BIT_GET_R_MGG_FIFO_LIFETIME_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_LIFETIME_8821C) & BIT_MASK_R_MGG_FIFO_LIFETIME_8821C)
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C 0x7f
+#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C(x) \
+ (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C) \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C)
+#define BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C \
+ (BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C(x) \
+ ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C(x) \
+ (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C) & \
+ BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C(x, v) \
+ (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C(x) | \
+ BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C(v))
+/* 2 REG_SHCUT_SETTING_8821C */
-#define BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8821C 0
-#define BIT_MASK_R_MGG_FIFO_VALID_MAP_8821C 0xffff
-#define BIT_R_MGG_FIFO_VALID_MAP_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8821C) << BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8821C)
-#define BIT_GET_R_MGG_FIFO_VALID_MAP_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8821C) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8821C)
+/* 2 REG_SHCUT_LLC_ETH_TYPE0_8821C */
+/* 2 REG_SHCUT_LLC_ETH_TYPE1_8821C */
-/* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C */
+/* 2 REG_SHCUT_LLC_OUI0_8821C */
-#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C 0
-#define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C 0x7f
-#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C)
-#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C)
+/* 2 REG_SHCUT_LLC_OUI1_8821C */
+/* 2 REG_SHCUT_LLC_OUI2_8821C */
/* 2 REG_MU_TX_CTL_8821C */
+#define BIT_R_MU_P1_WAIT_STATE_EN_8821C BIT(16)
+
+#define BIT_SHIFT_R_MU_RL_8821C 12
+#define BIT_MASK_R_MU_RL_8821C 0xf
+#define BIT_R_MU_RL_8821C(x) \
+ (((x) & BIT_MASK_R_MU_RL_8821C) << BIT_SHIFT_R_MU_RL_8821C)
+#define BITS_R_MU_RL_8821C (BIT_MASK_R_MU_RL_8821C << BIT_SHIFT_R_MU_RL_8821C)
+#define BIT_CLEAR_R_MU_RL_8821C(x) ((x) & (~BITS_R_MU_RL_8821C))
+#define BIT_GET_R_MU_RL_8821C(x) \
+ (((x) >> BIT_SHIFT_R_MU_RL_8821C) & BIT_MASK_R_MU_RL_8821C)
+#define BIT_SET_R_MU_RL_8821C(x, v) \
+ (BIT_CLEAR_R_MU_RL_8821C(x) | BIT_R_MU_RL_8821C(v))
+
#define BIT_R_FORCE_P1_RATEDOWN_8821C BIT(11)
#define BIT_SHIFT_R_MU_TAB_SEL_8821C 8
#define BIT_MASK_R_MU_TAB_SEL_8821C 0x7
-#define BIT_R_MU_TAB_SEL_8821C(x) (((x) & BIT_MASK_R_MU_TAB_SEL_8821C) << BIT_SHIFT_R_MU_TAB_SEL_8821C)
-#define BIT_GET_R_MU_TAB_SEL_8821C(x) (((x) >> BIT_SHIFT_R_MU_TAB_SEL_8821C) & BIT_MASK_R_MU_TAB_SEL_8821C)
+#define BIT_R_MU_TAB_SEL_8821C(x) \
+ (((x) & BIT_MASK_R_MU_TAB_SEL_8821C) << BIT_SHIFT_R_MU_TAB_SEL_8821C)
+#define BITS_R_MU_TAB_SEL_8821C \
+ (BIT_MASK_R_MU_TAB_SEL_8821C << BIT_SHIFT_R_MU_TAB_SEL_8821C)
+#define BIT_CLEAR_R_MU_TAB_SEL_8821C(x) ((x) & (~BITS_R_MU_TAB_SEL_8821C))
+#define BIT_GET_R_MU_TAB_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_R_MU_TAB_SEL_8821C) & BIT_MASK_R_MU_TAB_SEL_8821C)
+#define BIT_SET_R_MU_TAB_SEL_8821C(x, v) \
+ (BIT_CLEAR_R_MU_TAB_SEL_8821C(x) | BIT_R_MU_TAB_SEL_8821C(v))
#define BIT_R_EN_MU_MIMO_8821C BIT(7)
#define BIT_R_EN_REVERS_GTAB_8821C BIT(6)
#define BIT_SHIFT_R_MU_TABLE_VALID_8821C 0
#define BIT_MASK_R_MU_TABLE_VALID_8821C 0x3f
-#define BIT_R_MU_TABLE_VALID_8821C(x) (((x) & BIT_MASK_R_MU_TABLE_VALID_8821C) << BIT_SHIFT_R_MU_TABLE_VALID_8821C)
-#define BIT_GET_R_MU_TABLE_VALID_8821C(x) (((x) >> BIT_SHIFT_R_MU_TABLE_VALID_8821C) & BIT_MASK_R_MU_TABLE_VALID_8821C)
-
+#define BIT_R_MU_TABLE_VALID_8821C(x) \
+ (((x) & BIT_MASK_R_MU_TABLE_VALID_8821C) \
+ << BIT_SHIFT_R_MU_TABLE_VALID_8821C)
+#define BITS_R_MU_TABLE_VALID_8821C \
+ (BIT_MASK_R_MU_TABLE_VALID_8821C << BIT_SHIFT_R_MU_TABLE_VALID_8821C)
+#define BIT_CLEAR_R_MU_TABLE_VALID_8821C(x) \
+ ((x) & (~BITS_R_MU_TABLE_VALID_8821C))
+#define BIT_GET_R_MU_TABLE_VALID_8821C(x) \
+ (((x) >> BIT_SHIFT_R_MU_TABLE_VALID_8821C) & \
+ BIT_MASK_R_MU_TABLE_VALID_8821C)
+#define BIT_SET_R_MU_TABLE_VALID_8821C(x, v) \
+ (BIT_CLEAR_R_MU_TABLE_VALID_8821C(x) | BIT_R_MU_TABLE_VALID_8821C(v))
/* 2 REG_MU_STA_GID_VLD_8821C */
-/* 2 REG_NOT_VALID_8821C */
-
-#define BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C 0
-#define BIT_MASK_R_MU_STA_GTAB_VALID_8821C 0xffffffffL
-#define BIT_R_MU_STA_GTAB_VALID_8821C(x) (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8821C) << BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C)
-#define BIT_GET_R_MU_STA_GTAB_VALID_8821C(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C) & BIT_MASK_R_MU_STA_GTAB_VALID_8821C)
-
-
#define BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C 0
#define BIT_MASK_R_MU_STA_GTAB_VALID_8821C 0xffffffffL
-#define BIT_R_MU_STA_GTAB_VALID_8821C(x) (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8821C) << BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C)
-#define BIT_GET_R_MU_STA_GTAB_VALID_8821C(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C) & BIT_MASK_R_MU_STA_GTAB_VALID_8821C)
-
+#define BIT_R_MU_STA_GTAB_VALID_8821C(x) \
+ (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8821C) \
+ << BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C)
+#define BITS_R_MU_STA_GTAB_VALID_8821C \
+ (BIT_MASK_R_MU_STA_GTAB_VALID_8821C \
+ << BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C)
+#define BIT_CLEAR_R_MU_STA_GTAB_VALID_8821C(x) \
+ ((x) & (~BITS_R_MU_STA_GTAB_VALID_8821C))
+#define BIT_GET_R_MU_STA_GTAB_VALID_8821C(x) \
+ (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C) & \
+ BIT_MASK_R_MU_STA_GTAB_VALID_8821C)
+#define BIT_SET_R_MU_STA_GTAB_VALID_8821C(x, v) \
+ (BIT_CLEAR_R_MU_STA_GTAB_VALID_8821C(x) | \
+ BIT_R_MU_STA_GTAB_VALID_8821C(v))
/* 2 REG_MU_STA_USER_POS_INFO_8821C */
-/* 2 REG_NOT_VALID_8821C */
-
-#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_8821C 0
-#define BIT_MASK_R_MU_STA_GTAB_POSITION_8821C 0xffffffffffffffffL
-#define BIT_R_MU_STA_GTAB_POSITION_8821C(x) (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8821C) << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8821C)
-#define BIT_GET_R_MU_STA_GTAB_POSITION_8821C(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8821C) & BIT_MASK_R_MU_STA_GTAB_POSITION_8821C)
-
-
-#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_8821C 0
-#define BIT_MASK_R_MU_STA_GTAB_POSITION_8821C 0xffffffffffffffffL
-#define BIT_R_MU_STA_GTAB_POSITION_8821C(x) (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8821C) << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8821C)
-#define BIT_GET_R_MU_STA_GTAB_POSITION_8821C(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8821C) & BIT_MASK_R_MU_STA_GTAB_POSITION_8821C)
-
+#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8821C 0
+#define BIT_MASK_R_MU_STA_GTAB_POSITION_L_8821C 0xffffffffL
+#define BIT_R_MU_STA_GTAB_POSITION_L_8821C(x) \
+ (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_L_8821C) \
+ << BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8821C)
+#define BITS_R_MU_STA_GTAB_POSITION_L_8821C \
+ (BIT_MASK_R_MU_STA_GTAB_POSITION_L_8821C \
+ << BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8821C)
+#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_L_8821C(x) \
+ ((x) & (~BITS_R_MU_STA_GTAB_POSITION_L_8821C))
+#define BIT_GET_R_MU_STA_GTAB_POSITION_L_8821C(x) \
+ (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8821C) & \
+ BIT_MASK_R_MU_STA_GTAB_POSITION_L_8821C)
+#define BIT_SET_R_MU_STA_GTAB_POSITION_L_8821C(x, v) \
+ (BIT_CLEAR_R_MU_STA_GTAB_POSITION_L_8821C(x) | \
+ BIT_R_MU_STA_GTAB_POSITION_L_8821C(v))
+
+/* 2 REG_MU_STA_USER_POS_INFO_H_8821C */
+
+#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8821C 0
+#define BIT_MASK_R_MU_STA_GTAB_POSITION_H_8821C 0xffffffffL
+#define BIT_R_MU_STA_GTAB_POSITION_H_8821C(x) \
+ (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_H_8821C) \
+ << BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8821C)
+#define BITS_R_MU_STA_GTAB_POSITION_H_8821C \
+ (BIT_MASK_R_MU_STA_GTAB_POSITION_H_8821C \
+ << BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8821C)
+#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_H_8821C(x) \
+ ((x) & (~BITS_R_MU_STA_GTAB_POSITION_H_8821C))
+#define BIT_GET_R_MU_STA_GTAB_POSITION_H_8821C(x) \
+ (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8821C) & \
+ BIT_MASK_R_MU_STA_GTAB_POSITION_H_8821C)
+#define BIT_SET_R_MU_STA_GTAB_POSITION_H_8821C(x, v) \
+ (BIT_CLEAR_R_MU_STA_GTAB_POSITION_H_8821C(x) | \
+ BIT_R_MU_STA_GTAB_POSITION_H_8821C(v))
/* 2 REG_MU_TRX_DBG_CNT_8821C */
#define BIT_MU_DNGCNT_RST_8821C BIT(20)
#define BIT_SHIFT_MU_DBGCNT_SEL_8821C 16
#define BIT_MASK_MU_DBGCNT_SEL_8821C 0xf
-#define BIT_MU_DBGCNT_SEL_8821C(x) (((x) & BIT_MASK_MU_DBGCNT_SEL_8821C) << BIT_SHIFT_MU_DBGCNT_SEL_8821C)
-#define BIT_GET_MU_DBGCNT_SEL_8821C(x) (((x) >> BIT_SHIFT_MU_DBGCNT_SEL_8821C) & BIT_MASK_MU_DBGCNT_SEL_8821C)
-
+#define BIT_MU_DBGCNT_SEL_8821C(x) \
+ (((x) & BIT_MASK_MU_DBGCNT_SEL_8821C) << BIT_SHIFT_MU_DBGCNT_SEL_8821C)
+#define BITS_MU_DBGCNT_SEL_8821C \
+ (BIT_MASK_MU_DBGCNT_SEL_8821C << BIT_SHIFT_MU_DBGCNT_SEL_8821C)
+#define BIT_CLEAR_MU_DBGCNT_SEL_8821C(x) ((x) & (~BITS_MU_DBGCNT_SEL_8821C))
+#define BIT_GET_MU_DBGCNT_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_MU_DBGCNT_SEL_8821C) & BIT_MASK_MU_DBGCNT_SEL_8821C)
+#define BIT_SET_MU_DBGCNT_SEL_8821C(x, v) \
+ (BIT_CLEAR_MU_DBGCNT_SEL_8821C(x) | BIT_MU_DBGCNT_SEL_8821C(v))
#define BIT_SHIFT_MU_DNGCNT_8821C 0
#define BIT_MASK_MU_DNGCNT_8821C 0xffff
-#define BIT_MU_DNGCNT_8821C(x) (((x) & BIT_MASK_MU_DNGCNT_8821C) << BIT_SHIFT_MU_DNGCNT_8821C)
-#define BIT_GET_MU_DNGCNT_8821C(x) (((x) >> BIT_SHIFT_MU_DNGCNT_8821C) & BIT_MASK_MU_DNGCNT_8821C)
-
+#define BIT_MU_DNGCNT_8821C(x) \
+ (((x) & BIT_MASK_MU_DNGCNT_8821C) << BIT_SHIFT_MU_DNGCNT_8821C)
+#define BITS_MU_DNGCNT_8821C \
+ (BIT_MASK_MU_DNGCNT_8821C << BIT_SHIFT_MU_DNGCNT_8821C)
+#define BIT_CLEAR_MU_DNGCNT_8821C(x) ((x) & (~BITS_MU_DNGCNT_8821C))
+#define BIT_GET_MU_DNGCNT_8821C(x) \
+ (((x) >> BIT_SHIFT_MU_DNGCNT_8821C) & BIT_MASK_MU_DNGCNT_8821C)
+#define BIT_SET_MU_DNGCNT_8821C(x, v) \
+ (BIT_CLEAR_MU_DNGCNT_8821C(x) | BIT_MU_DNGCNT_8821C(v))
/* 2 REG_NOT_VALID_8821C */
@@ -6354,21 +11938,32 @@
#define BIT_SHIFT_TXOPLIMIT_8821C 16
#define BIT_MASK_TXOPLIMIT_8821C 0x7ff
-#define BIT_TXOPLIMIT_8821C(x) (((x) & BIT_MASK_TXOPLIMIT_8821C) << BIT_SHIFT_TXOPLIMIT_8821C)
-#define BIT_GET_TXOPLIMIT_8821C(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C)
-
+#define BIT_TXOPLIMIT_8821C(x) \
+ (((x) & BIT_MASK_TXOPLIMIT_8821C) << BIT_SHIFT_TXOPLIMIT_8821C)
+#define BITS_TXOPLIMIT_8821C \
+ (BIT_MASK_TXOPLIMIT_8821C << BIT_SHIFT_TXOPLIMIT_8821C)
+#define BIT_CLEAR_TXOPLIMIT_8821C(x) ((x) & (~BITS_TXOPLIMIT_8821C))
+#define BIT_GET_TXOPLIMIT_8821C(x) \
+ (((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C)
+#define BIT_SET_TXOPLIMIT_8821C(x, v) \
+ (BIT_CLEAR_TXOPLIMIT_8821C(x) | BIT_TXOPLIMIT_8821C(v))
#define BIT_SHIFT_CW_8821C 8
#define BIT_MASK_CW_8821C 0xff
#define BIT_CW_8821C(x) (((x) & BIT_MASK_CW_8821C) << BIT_SHIFT_CW_8821C)
+#define BITS_CW_8821C (BIT_MASK_CW_8821C << BIT_SHIFT_CW_8821C)
+#define BIT_CLEAR_CW_8821C(x) ((x) & (~BITS_CW_8821C))
#define BIT_GET_CW_8821C(x) (((x) >> BIT_SHIFT_CW_8821C) & BIT_MASK_CW_8821C)
-
+#define BIT_SET_CW_8821C(x, v) (BIT_CLEAR_CW_8821C(x) | BIT_CW_8821C(v))
#define BIT_SHIFT_AIFS_8821C 0
#define BIT_MASK_AIFS_8821C 0xff
#define BIT_AIFS_8821C(x) (((x) & BIT_MASK_AIFS_8821C) << BIT_SHIFT_AIFS_8821C)
-#define BIT_GET_AIFS_8821C(x) (((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C)
-
+#define BITS_AIFS_8821C (BIT_MASK_AIFS_8821C << BIT_SHIFT_AIFS_8821C)
+#define BIT_CLEAR_AIFS_8821C(x) ((x) & (~BITS_AIFS_8821C))
+#define BIT_GET_AIFS_8821C(x) \
+ (((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C)
+#define BIT_SET_AIFS_8821C(x, v) (BIT_CLEAR_AIFS_8821C(x) | BIT_AIFS_8821C(v))
/* 2 REG_EDCA_VI_PARAM_8821C */
@@ -6376,21 +11971,32 @@
#define BIT_SHIFT_TXOPLIMIT_8821C 16
#define BIT_MASK_TXOPLIMIT_8821C 0x7ff
-#define BIT_TXOPLIMIT_8821C(x) (((x) & BIT_MASK_TXOPLIMIT_8821C) << BIT_SHIFT_TXOPLIMIT_8821C)
-#define BIT_GET_TXOPLIMIT_8821C(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C)
-
+#define BIT_TXOPLIMIT_8821C(x) \
+ (((x) & BIT_MASK_TXOPLIMIT_8821C) << BIT_SHIFT_TXOPLIMIT_8821C)
+#define BITS_TXOPLIMIT_8821C \
+ (BIT_MASK_TXOPLIMIT_8821C << BIT_SHIFT_TXOPLIMIT_8821C)
+#define BIT_CLEAR_TXOPLIMIT_8821C(x) ((x) & (~BITS_TXOPLIMIT_8821C))
+#define BIT_GET_TXOPLIMIT_8821C(x) \
+ (((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C)
+#define BIT_SET_TXOPLIMIT_8821C(x, v) \
+ (BIT_CLEAR_TXOPLIMIT_8821C(x) | BIT_TXOPLIMIT_8821C(v))
#define BIT_SHIFT_CW_8821C 8
#define BIT_MASK_CW_8821C 0xff
#define BIT_CW_8821C(x) (((x) & BIT_MASK_CW_8821C) << BIT_SHIFT_CW_8821C)
+#define BITS_CW_8821C (BIT_MASK_CW_8821C << BIT_SHIFT_CW_8821C)
+#define BIT_CLEAR_CW_8821C(x) ((x) & (~BITS_CW_8821C))
#define BIT_GET_CW_8821C(x) (((x) >> BIT_SHIFT_CW_8821C) & BIT_MASK_CW_8821C)
-
+#define BIT_SET_CW_8821C(x, v) (BIT_CLEAR_CW_8821C(x) | BIT_CW_8821C(v))
#define BIT_SHIFT_AIFS_8821C 0
#define BIT_MASK_AIFS_8821C 0xff
#define BIT_AIFS_8821C(x) (((x) & BIT_MASK_AIFS_8821C) << BIT_SHIFT_AIFS_8821C)
-#define BIT_GET_AIFS_8821C(x) (((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C)
-
+#define BITS_AIFS_8821C (BIT_MASK_AIFS_8821C << BIT_SHIFT_AIFS_8821C)
+#define BIT_CLEAR_AIFS_8821C(x) ((x) & (~BITS_AIFS_8821C))
+#define BIT_GET_AIFS_8821C(x) \
+ (((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C)
+#define BIT_SET_AIFS_8821C(x, v) (BIT_CLEAR_AIFS_8821C(x) | BIT_AIFS_8821C(v))
/* 2 REG_EDCA_BE_PARAM_8821C */
@@ -6398,21 +12004,32 @@
#define BIT_SHIFT_TXOPLIMIT_8821C 16
#define BIT_MASK_TXOPLIMIT_8821C 0x7ff
-#define BIT_TXOPLIMIT_8821C(x) (((x) & BIT_MASK_TXOPLIMIT_8821C) << BIT_SHIFT_TXOPLIMIT_8821C)
-#define BIT_GET_TXOPLIMIT_8821C(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C)
-
+#define BIT_TXOPLIMIT_8821C(x) \
+ (((x) & BIT_MASK_TXOPLIMIT_8821C) << BIT_SHIFT_TXOPLIMIT_8821C)
+#define BITS_TXOPLIMIT_8821C \
+ (BIT_MASK_TXOPLIMIT_8821C << BIT_SHIFT_TXOPLIMIT_8821C)
+#define BIT_CLEAR_TXOPLIMIT_8821C(x) ((x) & (~BITS_TXOPLIMIT_8821C))
+#define BIT_GET_TXOPLIMIT_8821C(x) \
+ (((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C)
+#define BIT_SET_TXOPLIMIT_8821C(x, v) \
+ (BIT_CLEAR_TXOPLIMIT_8821C(x) | BIT_TXOPLIMIT_8821C(v))
#define BIT_SHIFT_CW_8821C 8
#define BIT_MASK_CW_8821C 0xff
#define BIT_CW_8821C(x) (((x) & BIT_MASK_CW_8821C) << BIT_SHIFT_CW_8821C)
+#define BITS_CW_8821C (BIT_MASK_CW_8821C << BIT_SHIFT_CW_8821C)
+#define BIT_CLEAR_CW_8821C(x) ((x) & (~BITS_CW_8821C))
#define BIT_GET_CW_8821C(x) (((x) >> BIT_SHIFT_CW_8821C) & BIT_MASK_CW_8821C)
-
+#define BIT_SET_CW_8821C(x, v) (BIT_CLEAR_CW_8821C(x) | BIT_CW_8821C(v))
#define BIT_SHIFT_AIFS_8821C 0
#define BIT_MASK_AIFS_8821C 0xff
#define BIT_AIFS_8821C(x) (((x) & BIT_MASK_AIFS_8821C) << BIT_SHIFT_AIFS_8821C)
-#define BIT_GET_AIFS_8821C(x) (((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C)
-
+#define BITS_AIFS_8821C (BIT_MASK_AIFS_8821C << BIT_SHIFT_AIFS_8821C)
+#define BIT_CLEAR_AIFS_8821C(x) ((x) & (~BITS_AIFS_8821C))
+#define BIT_GET_AIFS_8821C(x) \
+ (((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C)
+#define BIT_SET_AIFS_8821C(x, v) (BIT_CLEAR_AIFS_8821C(x) | BIT_AIFS_8821C(v))
/* 2 REG_EDCA_BK_PARAM_8821C */
@@ -6420,107 +12037,228 @@
#define BIT_SHIFT_TXOPLIMIT_8821C 16
#define BIT_MASK_TXOPLIMIT_8821C 0x7ff
-#define BIT_TXOPLIMIT_8821C(x) (((x) & BIT_MASK_TXOPLIMIT_8821C) << BIT_SHIFT_TXOPLIMIT_8821C)
-#define BIT_GET_TXOPLIMIT_8821C(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C)
-
+#define BIT_TXOPLIMIT_8821C(x) \
+ (((x) & BIT_MASK_TXOPLIMIT_8821C) << BIT_SHIFT_TXOPLIMIT_8821C)
+#define BITS_TXOPLIMIT_8821C \
+ (BIT_MASK_TXOPLIMIT_8821C << BIT_SHIFT_TXOPLIMIT_8821C)
+#define BIT_CLEAR_TXOPLIMIT_8821C(x) ((x) & (~BITS_TXOPLIMIT_8821C))
+#define BIT_GET_TXOPLIMIT_8821C(x) \
+ (((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C)
+#define BIT_SET_TXOPLIMIT_8821C(x, v) \
+ (BIT_CLEAR_TXOPLIMIT_8821C(x) | BIT_TXOPLIMIT_8821C(v))
#define BIT_SHIFT_CW_8821C 8
#define BIT_MASK_CW_8821C 0xff
#define BIT_CW_8821C(x) (((x) & BIT_MASK_CW_8821C) << BIT_SHIFT_CW_8821C)
+#define BITS_CW_8821C (BIT_MASK_CW_8821C << BIT_SHIFT_CW_8821C)
+#define BIT_CLEAR_CW_8821C(x) ((x) & (~BITS_CW_8821C))
#define BIT_GET_CW_8821C(x) (((x) >> BIT_SHIFT_CW_8821C) & BIT_MASK_CW_8821C)
-
+#define BIT_SET_CW_8821C(x, v) (BIT_CLEAR_CW_8821C(x) | BIT_CW_8821C(v))
#define BIT_SHIFT_AIFS_8821C 0
#define BIT_MASK_AIFS_8821C 0xff
#define BIT_AIFS_8821C(x) (((x) & BIT_MASK_AIFS_8821C) << BIT_SHIFT_AIFS_8821C)
-#define BIT_GET_AIFS_8821C(x) (((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C)
-
+#define BITS_AIFS_8821C (BIT_MASK_AIFS_8821C << BIT_SHIFT_AIFS_8821C)
+#define BIT_CLEAR_AIFS_8821C(x) ((x) & (~BITS_AIFS_8821C))
+#define BIT_GET_AIFS_8821C(x) \
+ (((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C)
+#define BIT_SET_AIFS_8821C(x, v) (BIT_CLEAR_AIFS_8821C(x) | BIT_AIFS_8821C(v))
/* 2 REG_BCNTCFG_8821C */
#define BIT_SHIFT_BCNCW_MAX_8821C 12
#define BIT_MASK_BCNCW_MAX_8821C 0xf
-#define BIT_BCNCW_MAX_8821C(x) (((x) & BIT_MASK_BCNCW_MAX_8821C) << BIT_SHIFT_BCNCW_MAX_8821C)
-#define BIT_GET_BCNCW_MAX_8821C(x) (((x) >> BIT_SHIFT_BCNCW_MAX_8821C) & BIT_MASK_BCNCW_MAX_8821C)
-
+#define BIT_BCNCW_MAX_8821C(x) \
+ (((x) & BIT_MASK_BCNCW_MAX_8821C) << BIT_SHIFT_BCNCW_MAX_8821C)
+#define BITS_BCNCW_MAX_8821C \
+ (BIT_MASK_BCNCW_MAX_8821C << BIT_SHIFT_BCNCW_MAX_8821C)
+#define BIT_CLEAR_BCNCW_MAX_8821C(x) ((x) & (~BITS_BCNCW_MAX_8821C))
+#define BIT_GET_BCNCW_MAX_8821C(x) \
+ (((x) >> BIT_SHIFT_BCNCW_MAX_8821C) & BIT_MASK_BCNCW_MAX_8821C)
+#define BIT_SET_BCNCW_MAX_8821C(x, v) \
+ (BIT_CLEAR_BCNCW_MAX_8821C(x) | BIT_BCNCW_MAX_8821C(v))
#define BIT_SHIFT_BCNCW_MIN_8821C 8
#define BIT_MASK_BCNCW_MIN_8821C 0xf
-#define BIT_BCNCW_MIN_8821C(x) (((x) & BIT_MASK_BCNCW_MIN_8821C) << BIT_SHIFT_BCNCW_MIN_8821C)
-#define BIT_GET_BCNCW_MIN_8821C(x) (((x) >> BIT_SHIFT_BCNCW_MIN_8821C) & BIT_MASK_BCNCW_MIN_8821C)
-
+#define BIT_BCNCW_MIN_8821C(x) \
+ (((x) & BIT_MASK_BCNCW_MIN_8821C) << BIT_SHIFT_BCNCW_MIN_8821C)
+#define BITS_BCNCW_MIN_8821C \
+ (BIT_MASK_BCNCW_MIN_8821C << BIT_SHIFT_BCNCW_MIN_8821C)
+#define BIT_CLEAR_BCNCW_MIN_8821C(x) ((x) & (~BITS_BCNCW_MIN_8821C))
+#define BIT_GET_BCNCW_MIN_8821C(x) \
+ (((x) >> BIT_SHIFT_BCNCW_MIN_8821C) & BIT_MASK_BCNCW_MIN_8821C)
+#define BIT_SET_BCNCW_MIN_8821C(x, v) \
+ (BIT_CLEAR_BCNCW_MIN_8821C(x) | BIT_BCNCW_MIN_8821C(v))
#define BIT_SHIFT_BCNIFS_8821C 0
#define BIT_MASK_BCNIFS_8821C 0xff
-#define BIT_BCNIFS_8821C(x) (((x) & BIT_MASK_BCNIFS_8821C) << BIT_SHIFT_BCNIFS_8821C)
-#define BIT_GET_BCNIFS_8821C(x) (((x) >> BIT_SHIFT_BCNIFS_8821C) & BIT_MASK_BCNIFS_8821C)
+#define BIT_BCNIFS_8821C(x) \
+ (((x) & BIT_MASK_BCNIFS_8821C) << BIT_SHIFT_BCNIFS_8821C)
+#define BITS_BCNIFS_8821C (BIT_MASK_BCNIFS_8821C << BIT_SHIFT_BCNIFS_8821C)
+#define BIT_CLEAR_BCNIFS_8821C(x) ((x) & (~BITS_BCNIFS_8821C))
+#define BIT_GET_BCNIFS_8821C(x) \
+ (((x) >> BIT_SHIFT_BCNIFS_8821C) & BIT_MASK_BCNIFS_8821C)
+#define BIT_SET_BCNIFS_8821C(x, v) \
+ (BIT_CLEAR_BCNIFS_8821C(x) | BIT_BCNIFS_8821C(v))
+/* 2 REG_NOT_VALID_8821C */
/* 2 REG_PIFS_8821C */
#define BIT_SHIFT_PIFS_8821C 0
#define BIT_MASK_PIFS_8821C 0xff
#define BIT_PIFS_8821C(x) (((x) & BIT_MASK_PIFS_8821C) << BIT_SHIFT_PIFS_8821C)
-#define BIT_GET_PIFS_8821C(x) (((x) >> BIT_SHIFT_PIFS_8821C) & BIT_MASK_PIFS_8821C)
-
+#define BITS_PIFS_8821C (BIT_MASK_PIFS_8821C << BIT_SHIFT_PIFS_8821C)
+#define BIT_CLEAR_PIFS_8821C(x) ((x) & (~BITS_PIFS_8821C))
+#define BIT_GET_PIFS_8821C(x) \
+ (((x) >> BIT_SHIFT_PIFS_8821C) & BIT_MASK_PIFS_8821C)
+#define BIT_SET_PIFS_8821C(x, v) (BIT_CLEAR_PIFS_8821C(x) | BIT_PIFS_8821C(v))
/* 2 REG_RDG_PIFS_8821C */
#define BIT_SHIFT_RDG_PIFS_8821C 0
#define BIT_MASK_RDG_PIFS_8821C 0xff
-#define BIT_RDG_PIFS_8821C(x) (((x) & BIT_MASK_RDG_PIFS_8821C) << BIT_SHIFT_RDG_PIFS_8821C)
-#define BIT_GET_RDG_PIFS_8821C(x) (((x) >> BIT_SHIFT_RDG_PIFS_8821C) & BIT_MASK_RDG_PIFS_8821C)
-
+#define BIT_RDG_PIFS_8821C(x) \
+ (((x) & BIT_MASK_RDG_PIFS_8821C) << BIT_SHIFT_RDG_PIFS_8821C)
+#define BITS_RDG_PIFS_8821C \
+ (BIT_MASK_RDG_PIFS_8821C << BIT_SHIFT_RDG_PIFS_8821C)
+#define BIT_CLEAR_RDG_PIFS_8821C(x) ((x) & (~BITS_RDG_PIFS_8821C))
+#define BIT_GET_RDG_PIFS_8821C(x) \
+ (((x) >> BIT_SHIFT_RDG_PIFS_8821C) & BIT_MASK_RDG_PIFS_8821C)
+#define BIT_SET_RDG_PIFS_8821C(x, v) \
+ (BIT_CLEAR_RDG_PIFS_8821C(x) | BIT_RDG_PIFS_8821C(v))
/* 2 REG_SIFS_8821C */
#define BIT_SHIFT_SIFS_OFDM_TRX_8821C 24
#define BIT_MASK_SIFS_OFDM_TRX_8821C 0xff
-#define BIT_SIFS_OFDM_TRX_8821C(x) (((x) & BIT_MASK_SIFS_OFDM_TRX_8821C) << BIT_SHIFT_SIFS_OFDM_TRX_8821C)
-#define BIT_GET_SIFS_OFDM_TRX_8821C(x) (((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8821C) & BIT_MASK_SIFS_OFDM_TRX_8821C)
-
+#define BIT_SIFS_OFDM_TRX_8821C(x) \
+ (((x) & BIT_MASK_SIFS_OFDM_TRX_8821C) << BIT_SHIFT_SIFS_OFDM_TRX_8821C)
+#define BITS_SIFS_OFDM_TRX_8821C \
+ (BIT_MASK_SIFS_OFDM_TRX_8821C << BIT_SHIFT_SIFS_OFDM_TRX_8821C)
+#define BIT_CLEAR_SIFS_OFDM_TRX_8821C(x) ((x) & (~BITS_SIFS_OFDM_TRX_8821C))
+#define BIT_GET_SIFS_OFDM_TRX_8821C(x) \
+ (((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8821C) & BIT_MASK_SIFS_OFDM_TRX_8821C)
+#define BIT_SET_SIFS_OFDM_TRX_8821C(x, v) \
+ (BIT_CLEAR_SIFS_OFDM_TRX_8821C(x) | BIT_SIFS_OFDM_TRX_8821C(v))
#define BIT_SHIFT_SIFS_CCK_TRX_8821C 16
#define BIT_MASK_SIFS_CCK_TRX_8821C 0xff
-#define BIT_SIFS_CCK_TRX_8821C(x) (((x) & BIT_MASK_SIFS_CCK_TRX_8821C) << BIT_SHIFT_SIFS_CCK_TRX_8821C)
-#define BIT_GET_SIFS_CCK_TRX_8821C(x) (((x) >> BIT_SHIFT_SIFS_CCK_TRX_8821C) & BIT_MASK_SIFS_CCK_TRX_8821C)
-
+#define BIT_SIFS_CCK_TRX_8821C(x) \
+ (((x) & BIT_MASK_SIFS_CCK_TRX_8821C) << BIT_SHIFT_SIFS_CCK_TRX_8821C)
+#define BITS_SIFS_CCK_TRX_8821C \
+ (BIT_MASK_SIFS_CCK_TRX_8821C << BIT_SHIFT_SIFS_CCK_TRX_8821C)
+#define BIT_CLEAR_SIFS_CCK_TRX_8821C(x) ((x) & (~BITS_SIFS_CCK_TRX_8821C))
+#define BIT_GET_SIFS_CCK_TRX_8821C(x) \
+ (((x) >> BIT_SHIFT_SIFS_CCK_TRX_8821C) & BIT_MASK_SIFS_CCK_TRX_8821C)
+#define BIT_SET_SIFS_CCK_TRX_8821C(x, v) \
+ (BIT_CLEAR_SIFS_CCK_TRX_8821C(x) | BIT_SIFS_CCK_TRX_8821C(v))
#define BIT_SHIFT_SIFS_OFDM_CTX_8821C 8
#define BIT_MASK_SIFS_OFDM_CTX_8821C 0xff
-#define BIT_SIFS_OFDM_CTX_8821C(x) (((x) & BIT_MASK_SIFS_OFDM_CTX_8821C) << BIT_SHIFT_SIFS_OFDM_CTX_8821C)
-#define BIT_GET_SIFS_OFDM_CTX_8821C(x) (((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8821C) & BIT_MASK_SIFS_OFDM_CTX_8821C)
-
+#define BIT_SIFS_OFDM_CTX_8821C(x) \
+ (((x) & BIT_MASK_SIFS_OFDM_CTX_8821C) << BIT_SHIFT_SIFS_OFDM_CTX_8821C)
+#define BITS_SIFS_OFDM_CTX_8821C \
+ (BIT_MASK_SIFS_OFDM_CTX_8821C << BIT_SHIFT_SIFS_OFDM_CTX_8821C)
+#define BIT_CLEAR_SIFS_OFDM_CTX_8821C(x) ((x) & (~BITS_SIFS_OFDM_CTX_8821C))
+#define BIT_GET_SIFS_OFDM_CTX_8821C(x) \
+ (((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8821C) & BIT_MASK_SIFS_OFDM_CTX_8821C)
+#define BIT_SET_SIFS_OFDM_CTX_8821C(x, v) \
+ (BIT_CLEAR_SIFS_OFDM_CTX_8821C(x) | BIT_SIFS_OFDM_CTX_8821C(v))
#define BIT_SHIFT_SIFS_CCK_CTX_8821C 0
#define BIT_MASK_SIFS_CCK_CTX_8821C 0xff
-#define BIT_SIFS_CCK_CTX_8821C(x) (((x) & BIT_MASK_SIFS_CCK_CTX_8821C) << BIT_SHIFT_SIFS_CCK_CTX_8821C)
-#define BIT_GET_SIFS_CCK_CTX_8821C(x) (((x) >> BIT_SHIFT_SIFS_CCK_CTX_8821C) & BIT_MASK_SIFS_CCK_CTX_8821C)
-
+#define BIT_SIFS_CCK_CTX_8821C(x) \
+ (((x) & BIT_MASK_SIFS_CCK_CTX_8821C) << BIT_SHIFT_SIFS_CCK_CTX_8821C)
+#define BITS_SIFS_CCK_CTX_8821C \
+ (BIT_MASK_SIFS_CCK_CTX_8821C << BIT_SHIFT_SIFS_CCK_CTX_8821C)
+#define BIT_CLEAR_SIFS_CCK_CTX_8821C(x) ((x) & (~BITS_SIFS_CCK_CTX_8821C))
+#define BIT_GET_SIFS_CCK_CTX_8821C(x) \
+ (((x) >> BIT_SHIFT_SIFS_CCK_CTX_8821C) & BIT_MASK_SIFS_CCK_CTX_8821C)
+#define BIT_SET_SIFS_CCK_CTX_8821C(x, v) \
+ (BIT_CLEAR_SIFS_CCK_CTX_8821C(x) | BIT_SIFS_CCK_CTX_8821C(v))
/* 2 REG_TSFTR_SYN_OFFSET_8821C */
#define BIT_SHIFT_TSFTR_SNC_OFFSET_8821C 0
#define BIT_MASK_TSFTR_SNC_OFFSET_8821C 0xffff
-#define BIT_TSFTR_SNC_OFFSET_8821C(x) (((x) & BIT_MASK_TSFTR_SNC_OFFSET_8821C) << BIT_SHIFT_TSFTR_SNC_OFFSET_8821C)
-#define BIT_GET_TSFTR_SNC_OFFSET_8821C(x) (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_8821C) & BIT_MASK_TSFTR_SNC_OFFSET_8821C)
-
+#define BIT_TSFTR_SNC_OFFSET_8821C(x) \
+ (((x) & BIT_MASK_TSFTR_SNC_OFFSET_8821C) \
+ << BIT_SHIFT_TSFTR_SNC_OFFSET_8821C)
+#define BITS_TSFTR_SNC_OFFSET_8821C \
+ (BIT_MASK_TSFTR_SNC_OFFSET_8821C << BIT_SHIFT_TSFTR_SNC_OFFSET_8821C)
+#define BIT_CLEAR_TSFTR_SNC_OFFSET_8821C(x) \
+ ((x) & (~BITS_TSFTR_SNC_OFFSET_8821C))
+#define BIT_GET_TSFTR_SNC_OFFSET_8821C(x) \
+ (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_8821C) & \
+ BIT_MASK_TSFTR_SNC_OFFSET_8821C)
+#define BIT_SET_TSFTR_SNC_OFFSET_8821C(x, v) \
+ (BIT_CLEAR_TSFTR_SNC_OFFSET_8821C(x) | BIT_TSFTR_SNC_OFFSET_8821C(v))
/* 2 REG_AGGR_BREAK_TIME_8821C */
#define BIT_SHIFT_AGGR_BK_TIME_8821C 0
#define BIT_MASK_AGGR_BK_TIME_8821C 0xff
-#define BIT_AGGR_BK_TIME_8821C(x) (((x) & BIT_MASK_AGGR_BK_TIME_8821C) << BIT_SHIFT_AGGR_BK_TIME_8821C)
-#define BIT_GET_AGGR_BK_TIME_8821C(x) (((x) >> BIT_SHIFT_AGGR_BK_TIME_8821C) & BIT_MASK_AGGR_BK_TIME_8821C)
-
+#define BIT_AGGR_BK_TIME_8821C(x) \
+ (((x) & BIT_MASK_AGGR_BK_TIME_8821C) << BIT_SHIFT_AGGR_BK_TIME_8821C)
+#define BITS_AGGR_BK_TIME_8821C \
+ (BIT_MASK_AGGR_BK_TIME_8821C << BIT_SHIFT_AGGR_BK_TIME_8821C)
+#define BIT_CLEAR_AGGR_BK_TIME_8821C(x) ((x) & (~BITS_AGGR_BK_TIME_8821C))
+#define BIT_GET_AGGR_BK_TIME_8821C(x) \
+ (((x) >> BIT_SHIFT_AGGR_BK_TIME_8821C) & BIT_MASK_AGGR_BK_TIME_8821C)
+#define BIT_SET_AGGR_BK_TIME_8821C(x, v) \
+ (BIT_CLEAR_AGGR_BK_TIME_8821C(x) | BIT_AGGR_BK_TIME_8821C(v))
/* 2 REG_SLOT_8821C */
#define BIT_SHIFT_SLOT_8821C 0
#define BIT_MASK_SLOT_8821C 0xff
#define BIT_SLOT_8821C(x) (((x) & BIT_MASK_SLOT_8821C) << BIT_SHIFT_SLOT_8821C)
-#define BIT_GET_SLOT_8821C(x) (((x) >> BIT_SHIFT_SLOT_8821C) & BIT_MASK_SLOT_8821C)
+#define BITS_SLOT_8821C (BIT_MASK_SLOT_8821C << BIT_SHIFT_SLOT_8821C)
+#define BIT_CLEAR_SLOT_8821C(x) ((x) & (~BITS_SLOT_8821C))
+#define BIT_GET_SLOT_8821C(x) \
+ (((x) >> BIT_SHIFT_SLOT_8821C) & BIT_MASK_SLOT_8821C)
+#define BIT_SET_SLOT_8821C(x, v) (BIT_CLEAR_SLOT_8821C(x) | BIT_SLOT_8821C(v))
+
+/* 2 REG_NOA_ON_ERLY_TIME_8821C */
+
+#define BIT_SHIFT__NOA_ON_ERLY_TIME_8821C 0
+#define BIT_MASK__NOA_ON_ERLY_TIME_8821C 0xff
+#define BIT__NOA_ON_ERLY_TIME_8821C(x) \
+ (((x) & BIT_MASK__NOA_ON_ERLY_TIME_8821C) \
+ << BIT_SHIFT__NOA_ON_ERLY_TIME_8821C)
+#define BITS__NOA_ON_ERLY_TIME_8821C \
+ (BIT_MASK__NOA_ON_ERLY_TIME_8821C << BIT_SHIFT__NOA_ON_ERLY_TIME_8821C)
+#define BIT_CLEAR__NOA_ON_ERLY_TIME_8821C(x) \
+ ((x) & (~BITS__NOA_ON_ERLY_TIME_8821C))
+#define BIT_GET__NOA_ON_ERLY_TIME_8821C(x) \
+ (((x) >> BIT_SHIFT__NOA_ON_ERLY_TIME_8821C) & \
+ BIT_MASK__NOA_ON_ERLY_TIME_8821C)
+#define BIT_SET__NOA_ON_ERLY_TIME_8821C(x, v) \
+ (BIT_CLEAR__NOA_ON_ERLY_TIME_8821C(x) | BIT__NOA_ON_ERLY_TIME_8821C(v))
+
+/* 2 REG_NOA_OFF_ERLY_TIME_8821C */
+
+#define BIT_SHIFT__NOA_OFF_ERLY_TIME_8821C 0
+#define BIT_MASK__NOA_OFF_ERLY_TIME_8821C 0xff
+#define BIT__NOA_OFF_ERLY_TIME_8821C(x) \
+ (((x) & BIT_MASK__NOA_OFF_ERLY_TIME_8821C) \
+ << BIT_SHIFT__NOA_OFF_ERLY_TIME_8821C)
+#define BITS__NOA_OFF_ERLY_TIME_8821C \
+ (BIT_MASK__NOA_OFF_ERLY_TIME_8821C \
+ << BIT_SHIFT__NOA_OFF_ERLY_TIME_8821C)
+#define BIT_CLEAR__NOA_OFF_ERLY_TIME_8821C(x) \
+ ((x) & (~BITS__NOA_OFF_ERLY_TIME_8821C))
+#define BIT_GET__NOA_OFF_ERLY_TIME_8821C(x) \
+ (((x) >> BIT_SHIFT__NOA_OFF_ERLY_TIME_8821C) & \
+ BIT_MASK__NOA_OFF_ERLY_TIME_8821C)
+#define BIT_SET__NOA_OFF_ERLY_TIME_8821C(x, v) \
+ (BIT_CLEAR__NOA_OFF_ERLY_TIME_8821C(x) | \
+ BIT__NOA_OFF_ERLY_TIME_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+/* 2 REG_NOT_VALID_8821C */
/* 2 REG_TX_PTCL_CTRL_8821C */
#define BIT_DIS_EDCCA_8821C BIT(15)
@@ -6530,8 +12268,15 @@
#define BIT_SHIFT_TXQ_NAV_MSK_8821C 8
#define BIT_MASK_TXQ_NAV_MSK_8821C 0xf
-#define BIT_TXQ_NAV_MSK_8821C(x) (((x) & BIT_MASK_TXQ_NAV_MSK_8821C) << BIT_SHIFT_TXQ_NAV_MSK_8821C)
-#define BIT_GET_TXQ_NAV_MSK_8821C(x) (((x) >> BIT_SHIFT_TXQ_NAV_MSK_8821C) & BIT_MASK_TXQ_NAV_MSK_8821C)
+#define BIT_TXQ_NAV_MSK_8821C(x) \
+ (((x) & BIT_MASK_TXQ_NAV_MSK_8821C) << BIT_SHIFT_TXQ_NAV_MSK_8821C)
+#define BITS_TXQ_NAV_MSK_8821C \
+ (BIT_MASK_TXQ_NAV_MSK_8821C << BIT_SHIFT_TXQ_NAV_MSK_8821C)
+#define BIT_CLEAR_TXQ_NAV_MSK_8821C(x) ((x) & (~BITS_TXQ_NAV_MSK_8821C))
+#define BIT_GET_TXQ_NAV_MSK_8821C(x) \
+ (((x) >> BIT_SHIFT_TXQ_NAV_MSK_8821C) & BIT_MASK_TXQ_NAV_MSK_8821C)
+#define BIT_SET_TXQ_NAV_MSK_8821C(x, v) \
+ (BIT_CLEAR_TXQ_NAV_MSK_8821C(x) | BIT_TXQ_NAV_MSK_8821C(v))
#define BIT_DIS_CW_8821C BIT(7)
#define BIT_NAV_END_TXOP_8821C BIT(6)
@@ -6607,15 +12352,29 @@
#define BIT_SHIFT_CCA_FILTER_THRS_8821C 8
#define BIT_MASK_CCA_FILTER_THRS_8821C 0xff
-#define BIT_CCA_FILTER_THRS_8821C(x) (((x) & BIT_MASK_CCA_FILTER_THRS_8821C) << BIT_SHIFT_CCA_FILTER_THRS_8821C)
-#define BIT_GET_CCA_FILTER_THRS_8821C(x) (((x) >> BIT_SHIFT_CCA_FILTER_THRS_8821C) & BIT_MASK_CCA_FILTER_THRS_8821C)
-
+#define BIT_CCA_FILTER_THRS_8821C(x) \
+ (((x) & BIT_MASK_CCA_FILTER_THRS_8821C) \
+ << BIT_SHIFT_CCA_FILTER_THRS_8821C)
+#define BITS_CCA_FILTER_THRS_8821C \
+ (BIT_MASK_CCA_FILTER_THRS_8821C << BIT_SHIFT_CCA_FILTER_THRS_8821C)
+#define BIT_CLEAR_CCA_FILTER_THRS_8821C(x) ((x) & (~BITS_CCA_FILTER_THRS_8821C))
+#define BIT_GET_CCA_FILTER_THRS_8821C(x) \
+ (((x) >> BIT_SHIFT_CCA_FILTER_THRS_8821C) & \
+ BIT_MASK_CCA_FILTER_THRS_8821C)
+#define BIT_SET_CCA_FILTER_THRS_8821C(x, v) \
+ (BIT_CLEAR_CCA_FILTER_THRS_8821C(x) | BIT_CCA_FILTER_THRS_8821C(v))
#define BIT_SHIFT_EDCCA_THRS_8821C 0
#define BIT_MASK_EDCCA_THRS_8821C 0xff
-#define BIT_EDCCA_THRS_8821C(x) (((x) & BIT_MASK_EDCCA_THRS_8821C) << BIT_SHIFT_EDCCA_THRS_8821C)
-#define BIT_GET_EDCCA_THRS_8821C(x) (((x) >> BIT_SHIFT_EDCCA_THRS_8821C) & BIT_MASK_EDCCA_THRS_8821C)
-
+#define BIT_EDCCA_THRS_8821C(x) \
+ (((x) & BIT_MASK_EDCCA_THRS_8821C) << BIT_SHIFT_EDCCA_THRS_8821C)
+#define BITS_EDCCA_THRS_8821C \
+ (BIT_MASK_EDCCA_THRS_8821C << BIT_SHIFT_EDCCA_THRS_8821C)
+#define BIT_CLEAR_EDCCA_THRS_8821C(x) ((x) & (~BITS_EDCCA_THRS_8821C))
+#define BIT_GET_EDCCA_THRS_8821C(x) \
+ (((x) >> BIT_SHIFT_EDCCA_THRS_8821C) & BIT_MASK_EDCCA_THRS_8821C)
+#define BIT_SET_EDCCA_THRS_8821C(x, v) \
+ (BIT_CLEAR_EDCCA_THRS_8821C(x) | BIT_EDCCA_THRS_8821C(v))
/* 2 REG_P2PPS_SPEC_STATE_8821C */
#define BIT_SPEC_POWER_STATE_8821C BIT(7)
@@ -6627,29 +12386,70 @@
#define BIT_SPEC_NOA0_OFF_PERIOD_8821C BIT(1)
#define BIT_SPEC_FORCE_DOZE0_8821C BIT(0)
+/* 2 REG_NOT_VALID_8821C */
+
/* 2 REG_BAR_TX_CTRL_8821C */
-/* 2 REG_NOT_VALID_8821C */
+/* 2 REG_P2PON_DIS_TXTIME_8821C */
#define BIT_SHIFT_P2PON_DIS_TXTIME_8821C 0
#define BIT_MASK_P2PON_DIS_TXTIME_8821C 0xff
-#define BIT_P2PON_DIS_TXTIME_8821C(x) (((x) & BIT_MASK_P2PON_DIS_TXTIME_8821C) << BIT_SHIFT_P2PON_DIS_TXTIME_8821C)
-#define BIT_GET_P2PON_DIS_TXTIME_8821C(x) (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8821C) & BIT_MASK_P2PON_DIS_TXTIME_8821C)
+#define BIT_P2PON_DIS_TXTIME_8821C(x) \
+ (((x) & BIT_MASK_P2PON_DIS_TXTIME_8821C) \
+ << BIT_SHIFT_P2PON_DIS_TXTIME_8821C)
+#define BITS_P2PON_DIS_TXTIME_8821C \
+ (BIT_MASK_P2PON_DIS_TXTIME_8821C << BIT_SHIFT_P2PON_DIS_TXTIME_8821C)
+#define BIT_CLEAR_P2PON_DIS_TXTIME_8821C(x) \
+ ((x) & (~BITS_P2PON_DIS_TXTIME_8821C))
+#define BIT_GET_P2PON_DIS_TXTIME_8821C(x) \
+ (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8821C) & \
+ BIT_MASK_P2PON_DIS_TXTIME_8821C)
+#define BIT_SET_P2PON_DIS_TXTIME_8821C(x, v) \
+ (BIT_CLEAR_P2PON_DIS_TXTIME_8821C(x) | BIT_P2PON_DIS_TXTIME_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+/* 2 REG_NOT_VALID_8821C */
/* 2 REG_TBTT_PROHIBIT_8821C */
#define BIT_SHIFT_TBTT_HOLD_TIME_AP_8821C 8
#define BIT_MASK_TBTT_HOLD_TIME_AP_8821C 0xfff
-#define BIT_TBTT_HOLD_TIME_AP_8821C(x) (((x) & BIT_MASK_TBTT_HOLD_TIME_AP_8821C) << BIT_SHIFT_TBTT_HOLD_TIME_AP_8821C)
-#define BIT_GET_TBTT_HOLD_TIME_AP_8821C(x) (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP_8821C) & BIT_MASK_TBTT_HOLD_TIME_AP_8821C)
-
+#define BIT_TBTT_HOLD_TIME_AP_8821C(x) \
+ (((x) & BIT_MASK_TBTT_HOLD_TIME_AP_8821C) \
+ << BIT_SHIFT_TBTT_HOLD_TIME_AP_8821C)
+#define BITS_TBTT_HOLD_TIME_AP_8821C \
+ (BIT_MASK_TBTT_HOLD_TIME_AP_8821C << BIT_SHIFT_TBTT_HOLD_TIME_AP_8821C)
+#define BIT_CLEAR_TBTT_HOLD_TIME_AP_8821C(x) \
+ ((x) & (~BITS_TBTT_HOLD_TIME_AP_8821C))
+#define BIT_GET_TBTT_HOLD_TIME_AP_8821C(x) \
+ (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP_8821C) & \
+ BIT_MASK_TBTT_HOLD_TIME_AP_8821C)
+#define BIT_SET_TBTT_HOLD_TIME_AP_8821C(x, v) \
+ (BIT_CLEAR_TBTT_HOLD_TIME_AP_8821C(x) | BIT_TBTT_HOLD_TIME_AP_8821C(v))
#define BIT_SHIFT_TBTT_PROHIBIT_SETUP_8821C 0
#define BIT_MASK_TBTT_PROHIBIT_SETUP_8821C 0xf
-#define BIT_TBTT_PROHIBIT_SETUP_8821C(x) (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8821C) << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8821C)
-#define BIT_GET_TBTT_PROHIBIT_SETUP_8821C(x) (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8821C) & BIT_MASK_TBTT_PROHIBIT_SETUP_8821C)
-
+#define BIT_TBTT_PROHIBIT_SETUP_8821C(x) \
+ (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8821C) \
+ << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8821C)
+#define BITS_TBTT_PROHIBIT_SETUP_8821C \
+ (BIT_MASK_TBTT_PROHIBIT_SETUP_8821C \
+ << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8821C)
+#define BIT_CLEAR_TBTT_PROHIBIT_SETUP_8821C(x) \
+ ((x) & (~BITS_TBTT_PROHIBIT_SETUP_8821C))
+#define BIT_GET_TBTT_PROHIBIT_SETUP_8821C(x) \
+ (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8821C) & \
+ BIT_MASK_TBTT_PROHIBIT_SETUP_8821C)
+#define BIT_SET_TBTT_PROHIBIT_SETUP_8821C(x, v) \
+ (BIT_CLEAR_TBTT_PROHIBIT_SETUP_8821C(x) | \
+ BIT_TBTT_PROHIBIT_SETUP_8821C(v))
/* 2 REG_P2PPS_STATE_8821C */
#define BIT_POWER_STATE_8821C BIT(7)
@@ -6665,17 +12465,35 @@
#define BIT_SHIFT_RD_NAV_PROT_NXT_8821C 0
#define BIT_MASK_RD_NAV_PROT_NXT_8821C 0xffff
-#define BIT_RD_NAV_PROT_NXT_8821C(x) (((x) & BIT_MASK_RD_NAV_PROT_NXT_8821C) << BIT_SHIFT_RD_NAV_PROT_NXT_8821C)
-#define BIT_GET_RD_NAV_PROT_NXT_8821C(x) (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8821C) & BIT_MASK_RD_NAV_PROT_NXT_8821C)
-
+#define BIT_RD_NAV_PROT_NXT_8821C(x) \
+ (((x) & BIT_MASK_RD_NAV_PROT_NXT_8821C) \
+ << BIT_SHIFT_RD_NAV_PROT_NXT_8821C)
+#define BITS_RD_NAV_PROT_NXT_8821C \
+ (BIT_MASK_RD_NAV_PROT_NXT_8821C << BIT_SHIFT_RD_NAV_PROT_NXT_8821C)
+#define BIT_CLEAR_RD_NAV_PROT_NXT_8821C(x) ((x) & (~BITS_RD_NAV_PROT_NXT_8821C))
+#define BIT_GET_RD_NAV_PROT_NXT_8821C(x) \
+ (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8821C) & \
+ BIT_MASK_RD_NAV_PROT_NXT_8821C)
+#define BIT_SET_RD_NAV_PROT_NXT_8821C(x, v) \
+ (BIT_CLEAR_RD_NAV_PROT_NXT_8821C(x) | BIT_RD_NAV_PROT_NXT_8821C(v))
/* 2 REG_NAV_PROT_LEN_8821C */
#define BIT_SHIFT_NAV_PROT_LEN_8821C 0
#define BIT_MASK_NAV_PROT_LEN_8821C 0xffff
-#define BIT_NAV_PROT_LEN_8821C(x) (((x) & BIT_MASK_NAV_PROT_LEN_8821C) << BIT_SHIFT_NAV_PROT_LEN_8821C)
-#define BIT_GET_NAV_PROT_LEN_8821C(x) (((x) >> BIT_SHIFT_NAV_PROT_LEN_8821C) & BIT_MASK_NAV_PROT_LEN_8821C)
+#define BIT_NAV_PROT_LEN_8821C(x) \
+ (((x) & BIT_MASK_NAV_PROT_LEN_8821C) << BIT_SHIFT_NAV_PROT_LEN_8821C)
+#define BITS_NAV_PROT_LEN_8821C \
+ (BIT_MASK_NAV_PROT_LEN_8821C << BIT_SHIFT_NAV_PROT_LEN_8821C)
+#define BIT_CLEAR_NAV_PROT_LEN_8821C(x) ((x) & (~BITS_NAV_PROT_LEN_8821C))
+#define BIT_GET_NAV_PROT_LEN_8821C(x) \
+ (((x) >> BIT_SHIFT_NAV_PROT_LEN_8821C) & BIT_MASK_NAV_PROT_LEN_8821C)
+#define BIT_SET_NAV_PROT_LEN_8821C(x, v) \
+ (BIT_CLEAR_NAV_PROT_LEN_8821C(x) | BIT_NAV_PROT_LEN_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+/* 2 REG_NOT_VALID_8821C */
/* 2 REG_BCN_CTRL_8821C */
#define BIT_DIS_RX_BSSID_FIT_8821C BIT(6)
@@ -6699,9 +12517,15 @@
#define BIT_SHIFT_MBID_BCN_NUM_8821C 0
#define BIT_MASK_MBID_BCN_NUM_8821C 0x7
-#define BIT_MBID_BCN_NUM_8821C(x) (((x) & BIT_MASK_MBID_BCN_NUM_8821C) << BIT_SHIFT_MBID_BCN_NUM_8821C)
-#define BIT_GET_MBID_BCN_NUM_8821C(x) (((x) >> BIT_SHIFT_MBID_BCN_NUM_8821C) & BIT_MASK_MBID_BCN_NUM_8821C)
-
+#define BIT_MBID_BCN_NUM_8821C(x) \
+ (((x) & BIT_MASK_MBID_BCN_NUM_8821C) << BIT_SHIFT_MBID_BCN_NUM_8821C)
+#define BITS_MBID_BCN_NUM_8821C \
+ (BIT_MASK_MBID_BCN_NUM_8821C << BIT_SHIFT_MBID_BCN_NUM_8821C)
+#define BIT_CLEAR_MBID_BCN_NUM_8821C(x) ((x) & (~BITS_MBID_BCN_NUM_8821C))
+#define BIT_GET_MBID_BCN_NUM_8821C(x) \
+ (((x) >> BIT_SHIFT_MBID_BCN_NUM_8821C) & BIT_MASK_MBID_BCN_NUM_8821C)
+#define BIT_SET_MBID_BCN_NUM_8821C(x, v) \
+ (BIT_CLEAR_MBID_BCN_NUM_8821C(x) | BIT_MBID_BCN_NUM_8821C(v))
/* 2 REG_DUAL_TSF_RST_8821C */
#define BIT_FREECNT_RST_8821C BIT(5)
@@ -6715,152 +12539,329 @@
#define BIT_SHIFT_BCN_TIMER_SEL_FWRD_8821C 28
#define BIT_MASK_BCN_TIMER_SEL_FWRD_8821C 0x7
-#define BIT_BCN_TIMER_SEL_FWRD_8821C(x) (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_8821C) << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8821C)
-#define BIT_GET_BCN_TIMER_SEL_FWRD_8821C(x) (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_8821C) & BIT_MASK_BCN_TIMER_SEL_FWRD_8821C)
-
+#define BIT_BCN_TIMER_SEL_FWRD_8821C(x) \
+ (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_8821C) \
+ << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8821C)
+#define BITS_BCN_TIMER_SEL_FWRD_8821C \
+ (BIT_MASK_BCN_TIMER_SEL_FWRD_8821C \
+ << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8821C)
+#define BIT_CLEAR_BCN_TIMER_SEL_FWRD_8821C(x) \
+ ((x) & (~BITS_BCN_TIMER_SEL_FWRD_8821C))
+#define BIT_GET_BCN_TIMER_SEL_FWRD_8821C(x) \
+ (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_8821C) & \
+ BIT_MASK_BCN_TIMER_SEL_FWRD_8821C)
+#define BIT_SET_BCN_TIMER_SEL_FWRD_8821C(x, v) \
+ (BIT_CLEAR_BCN_TIMER_SEL_FWRD_8821C(x) | \
+ BIT_BCN_TIMER_SEL_FWRD_8821C(v))
#define BIT_SHIFT_BCN_SPACE_CLINT0_8821C 16
#define BIT_MASK_BCN_SPACE_CLINT0_8821C 0xfff
-#define BIT_BCN_SPACE_CLINT0_8821C(x) (((x) & BIT_MASK_BCN_SPACE_CLINT0_8821C) << BIT_SHIFT_BCN_SPACE_CLINT0_8821C)
-#define BIT_GET_BCN_SPACE_CLINT0_8821C(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT0_8821C) & BIT_MASK_BCN_SPACE_CLINT0_8821C)
-
+#define BIT_BCN_SPACE_CLINT0_8821C(x) \
+ (((x) & BIT_MASK_BCN_SPACE_CLINT0_8821C) \
+ << BIT_SHIFT_BCN_SPACE_CLINT0_8821C)
+#define BITS_BCN_SPACE_CLINT0_8821C \
+ (BIT_MASK_BCN_SPACE_CLINT0_8821C << BIT_SHIFT_BCN_SPACE_CLINT0_8821C)
+#define BIT_CLEAR_BCN_SPACE_CLINT0_8821C(x) \
+ ((x) & (~BITS_BCN_SPACE_CLINT0_8821C))
+#define BIT_GET_BCN_SPACE_CLINT0_8821C(x) \
+ (((x) >> BIT_SHIFT_BCN_SPACE_CLINT0_8821C) & \
+ BIT_MASK_BCN_SPACE_CLINT0_8821C)
+#define BIT_SET_BCN_SPACE_CLINT0_8821C(x, v) \
+ (BIT_CLEAR_BCN_SPACE_CLINT0_8821C(x) | BIT_BCN_SPACE_CLINT0_8821C(v))
#define BIT_SHIFT_BCN_SPACE0_8821C 0
#define BIT_MASK_BCN_SPACE0_8821C 0xffff
-#define BIT_BCN_SPACE0_8821C(x) (((x) & BIT_MASK_BCN_SPACE0_8821C) << BIT_SHIFT_BCN_SPACE0_8821C)
-#define BIT_GET_BCN_SPACE0_8821C(x) (((x) >> BIT_SHIFT_BCN_SPACE0_8821C) & BIT_MASK_BCN_SPACE0_8821C)
-
+#define BIT_BCN_SPACE0_8821C(x) \
+ (((x) & BIT_MASK_BCN_SPACE0_8821C) << BIT_SHIFT_BCN_SPACE0_8821C)
+#define BITS_BCN_SPACE0_8821C \
+ (BIT_MASK_BCN_SPACE0_8821C << BIT_SHIFT_BCN_SPACE0_8821C)
+#define BIT_CLEAR_BCN_SPACE0_8821C(x) ((x) & (~BITS_BCN_SPACE0_8821C))
+#define BIT_GET_BCN_SPACE0_8821C(x) \
+ (((x) >> BIT_SHIFT_BCN_SPACE0_8821C) & BIT_MASK_BCN_SPACE0_8821C)
+#define BIT_SET_BCN_SPACE0_8821C(x, v) \
+ (BIT_CLEAR_BCN_SPACE0_8821C(x) | BIT_BCN_SPACE0_8821C(v))
/* 2 REG_DRVERLYINT_8821C */
#define BIT_SHIFT_DRVERLYITV_8821C 0
#define BIT_MASK_DRVERLYITV_8821C 0xff
-#define BIT_DRVERLYITV_8821C(x) (((x) & BIT_MASK_DRVERLYITV_8821C) << BIT_SHIFT_DRVERLYITV_8821C)
-#define BIT_GET_DRVERLYITV_8821C(x) (((x) >> BIT_SHIFT_DRVERLYITV_8821C) & BIT_MASK_DRVERLYITV_8821C)
-
+#define BIT_DRVERLYITV_8821C(x) \
+ (((x) & BIT_MASK_DRVERLYITV_8821C) << BIT_SHIFT_DRVERLYITV_8821C)
+#define BITS_DRVERLYITV_8821C \
+ (BIT_MASK_DRVERLYITV_8821C << BIT_SHIFT_DRVERLYITV_8821C)
+#define BIT_CLEAR_DRVERLYITV_8821C(x) ((x) & (~BITS_DRVERLYITV_8821C))
+#define BIT_GET_DRVERLYITV_8821C(x) \
+ (((x) >> BIT_SHIFT_DRVERLYITV_8821C) & BIT_MASK_DRVERLYITV_8821C)
+#define BIT_SET_DRVERLYITV_8821C(x, v) \
+ (BIT_CLEAR_DRVERLYITV_8821C(x) | BIT_DRVERLYITV_8821C(v))
/* 2 REG_BCNDMATIM_8821C */
#define BIT_SHIFT_BCNDMATIM_8821C 0
#define BIT_MASK_BCNDMATIM_8821C 0xff
-#define BIT_BCNDMATIM_8821C(x) (((x) & BIT_MASK_BCNDMATIM_8821C) << BIT_SHIFT_BCNDMATIM_8821C)
-#define BIT_GET_BCNDMATIM_8821C(x) (((x) >> BIT_SHIFT_BCNDMATIM_8821C) & BIT_MASK_BCNDMATIM_8821C)
-
+#define BIT_BCNDMATIM_8821C(x) \
+ (((x) & BIT_MASK_BCNDMATIM_8821C) << BIT_SHIFT_BCNDMATIM_8821C)
+#define BITS_BCNDMATIM_8821C \
+ (BIT_MASK_BCNDMATIM_8821C << BIT_SHIFT_BCNDMATIM_8821C)
+#define BIT_CLEAR_BCNDMATIM_8821C(x) ((x) & (~BITS_BCNDMATIM_8821C))
+#define BIT_GET_BCNDMATIM_8821C(x) \
+ (((x) >> BIT_SHIFT_BCNDMATIM_8821C) & BIT_MASK_BCNDMATIM_8821C)
+#define BIT_SET_BCNDMATIM_8821C(x, v) \
+ (BIT_CLEAR_BCNDMATIM_8821C(x) | BIT_BCNDMATIM_8821C(v))
/* 2 REG_ATIMWND_8821C */
#define BIT_SHIFT_ATIMWND0_8821C 0
#define BIT_MASK_ATIMWND0_8821C 0xffff
-#define BIT_ATIMWND0_8821C(x) (((x) & BIT_MASK_ATIMWND0_8821C) << BIT_SHIFT_ATIMWND0_8821C)
-#define BIT_GET_ATIMWND0_8821C(x) (((x) >> BIT_SHIFT_ATIMWND0_8821C) & BIT_MASK_ATIMWND0_8821C)
-
+#define BIT_ATIMWND0_8821C(x) \
+ (((x) & BIT_MASK_ATIMWND0_8821C) << BIT_SHIFT_ATIMWND0_8821C)
+#define BITS_ATIMWND0_8821C \
+ (BIT_MASK_ATIMWND0_8821C << BIT_SHIFT_ATIMWND0_8821C)
+#define BIT_CLEAR_ATIMWND0_8821C(x) ((x) & (~BITS_ATIMWND0_8821C))
+#define BIT_GET_ATIMWND0_8821C(x) \
+ (((x) >> BIT_SHIFT_ATIMWND0_8821C) & BIT_MASK_ATIMWND0_8821C)
+#define BIT_SET_ATIMWND0_8821C(x, v) \
+ (BIT_CLEAR_ATIMWND0_8821C(x) | BIT_ATIMWND0_8821C(v))
/* 2 REG_USTIME_TSF_8821C */
#define BIT_SHIFT_USTIME_TSF_V1_8821C 0
#define BIT_MASK_USTIME_TSF_V1_8821C 0xff
-#define BIT_USTIME_TSF_V1_8821C(x) (((x) & BIT_MASK_USTIME_TSF_V1_8821C) << BIT_SHIFT_USTIME_TSF_V1_8821C)
-#define BIT_GET_USTIME_TSF_V1_8821C(x) (((x) >> BIT_SHIFT_USTIME_TSF_V1_8821C) & BIT_MASK_USTIME_TSF_V1_8821C)
-
+#define BIT_USTIME_TSF_V1_8821C(x) \
+ (((x) & BIT_MASK_USTIME_TSF_V1_8821C) << BIT_SHIFT_USTIME_TSF_V1_8821C)
+#define BITS_USTIME_TSF_V1_8821C \
+ (BIT_MASK_USTIME_TSF_V1_8821C << BIT_SHIFT_USTIME_TSF_V1_8821C)
+#define BIT_CLEAR_USTIME_TSF_V1_8821C(x) ((x) & (~BITS_USTIME_TSF_V1_8821C))
+#define BIT_GET_USTIME_TSF_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_USTIME_TSF_V1_8821C) & BIT_MASK_USTIME_TSF_V1_8821C)
+#define BIT_SET_USTIME_TSF_V1_8821C(x, v) \
+ (BIT_CLEAR_USTIME_TSF_V1_8821C(x) | BIT_USTIME_TSF_V1_8821C(v))
/* 2 REG_BCN_MAX_ERR_8821C */
#define BIT_SHIFT_BCN_MAX_ERR_8821C 0
#define BIT_MASK_BCN_MAX_ERR_8821C 0xff
-#define BIT_BCN_MAX_ERR_8821C(x) (((x) & BIT_MASK_BCN_MAX_ERR_8821C) << BIT_SHIFT_BCN_MAX_ERR_8821C)
-#define BIT_GET_BCN_MAX_ERR_8821C(x) (((x) >> BIT_SHIFT_BCN_MAX_ERR_8821C) & BIT_MASK_BCN_MAX_ERR_8821C)
-
+#define BIT_BCN_MAX_ERR_8821C(x) \
+ (((x) & BIT_MASK_BCN_MAX_ERR_8821C) << BIT_SHIFT_BCN_MAX_ERR_8821C)
+#define BITS_BCN_MAX_ERR_8821C \
+ (BIT_MASK_BCN_MAX_ERR_8821C << BIT_SHIFT_BCN_MAX_ERR_8821C)
+#define BIT_CLEAR_BCN_MAX_ERR_8821C(x) ((x) & (~BITS_BCN_MAX_ERR_8821C))
+#define BIT_GET_BCN_MAX_ERR_8821C(x) \
+ (((x) >> BIT_SHIFT_BCN_MAX_ERR_8821C) & BIT_MASK_BCN_MAX_ERR_8821C)
+#define BIT_SET_BCN_MAX_ERR_8821C(x, v) \
+ (BIT_CLEAR_BCN_MAX_ERR_8821C(x) | BIT_BCN_MAX_ERR_8821C(v))
/* 2 REG_RXTSF_OFFSET_CCK_8821C */
#define BIT_SHIFT_CCK_RXTSF_OFFSET_8821C 0
#define BIT_MASK_CCK_RXTSF_OFFSET_8821C 0xff
-#define BIT_CCK_RXTSF_OFFSET_8821C(x) (((x) & BIT_MASK_CCK_RXTSF_OFFSET_8821C) << BIT_SHIFT_CCK_RXTSF_OFFSET_8821C)
-#define BIT_GET_CCK_RXTSF_OFFSET_8821C(x) (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8821C) & BIT_MASK_CCK_RXTSF_OFFSET_8821C)
-
+#define BIT_CCK_RXTSF_OFFSET_8821C(x) \
+ (((x) & BIT_MASK_CCK_RXTSF_OFFSET_8821C) \
+ << BIT_SHIFT_CCK_RXTSF_OFFSET_8821C)
+#define BITS_CCK_RXTSF_OFFSET_8821C \
+ (BIT_MASK_CCK_RXTSF_OFFSET_8821C << BIT_SHIFT_CCK_RXTSF_OFFSET_8821C)
+#define BIT_CLEAR_CCK_RXTSF_OFFSET_8821C(x) \
+ ((x) & (~BITS_CCK_RXTSF_OFFSET_8821C))
+#define BIT_GET_CCK_RXTSF_OFFSET_8821C(x) \
+ (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8821C) & \
+ BIT_MASK_CCK_RXTSF_OFFSET_8821C)
+#define BIT_SET_CCK_RXTSF_OFFSET_8821C(x, v) \
+ (BIT_CLEAR_CCK_RXTSF_OFFSET_8821C(x) | BIT_CCK_RXTSF_OFFSET_8821C(v))
/* 2 REG_RXTSF_OFFSET_OFDM_8821C */
#define BIT_SHIFT_OFDM_RXTSF_OFFSET_8821C 0
#define BIT_MASK_OFDM_RXTSF_OFFSET_8821C 0xff
-#define BIT_OFDM_RXTSF_OFFSET_8821C(x) (((x) & BIT_MASK_OFDM_RXTSF_OFFSET_8821C) << BIT_SHIFT_OFDM_RXTSF_OFFSET_8821C)
-#define BIT_GET_OFDM_RXTSF_OFFSET_8821C(x) (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8821C) & BIT_MASK_OFDM_RXTSF_OFFSET_8821C)
-
+#define BIT_OFDM_RXTSF_OFFSET_8821C(x) \
+ (((x) & BIT_MASK_OFDM_RXTSF_OFFSET_8821C) \
+ << BIT_SHIFT_OFDM_RXTSF_OFFSET_8821C)
+#define BITS_OFDM_RXTSF_OFFSET_8821C \
+ (BIT_MASK_OFDM_RXTSF_OFFSET_8821C << BIT_SHIFT_OFDM_RXTSF_OFFSET_8821C)
+#define BIT_CLEAR_OFDM_RXTSF_OFFSET_8821C(x) \
+ ((x) & (~BITS_OFDM_RXTSF_OFFSET_8821C))
+#define BIT_GET_OFDM_RXTSF_OFFSET_8821C(x) \
+ (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8821C) & \
+ BIT_MASK_OFDM_RXTSF_OFFSET_8821C)
+#define BIT_SET_OFDM_RXTSF_OFFSET_8821C(x, v) \
+ (BIT_CLEAR_OFDM_RXTSF_OFFSET_8821C(x) | BIT_OFDM_RXTSF_OFFSET_8821C(v))
/* 2 REG_TSFTR_8821C */
-#define BIT_SHIFT_TSF_TIMER_8821C 0
-#define BIT_MASK_TSF_TIMER_8821C 0xffffffffffffffffL
-#define BIT_TSF_TIMER_8821C(x) (((x) & BIT_MASK_TSF_TIMER_8821C) << BIT_SHIFT_TSF_TIMER_8821C)
-#define BIT_GET_TSF_TIMER_8821C(x) (((x) >> BIT_SHIFT_TSF_TIMER_8821C) & BIT_MASK_TSF_TIMER_8821C)
-
+#define BIT_SHIFT_TSF_TIMER_V1_8821C 0
+#define BIT_MASK_TSF_TIMER_V1_8821C 0xffffffffL
+#define BIT_TSF_TIMER_V1_8821C(x) \
+ (((x) & BIT_MASK_TSF_TIMER_V1_8821C) << BIT_SHIFT_TSF_TIMER_V1_8821C)
+#define BITS_TSF_TIMER_V1_8821C \
+ (BIT_MASK_TSF_TIMER_V1_8821C << BIT_SHIFT_TSF_TIMER_V1_8821C)
+#define BIT_CLEAR_TSF_TIMER_V1_8821C(x) ((x) & (~BITS_TSF_TIMER_V1_8821C))
+#define BIT_GET_TSF_TIMER_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_TSF_TIMER_V1_8821C) & BIT_MASK_TSF_TIMER_V1_8821C)
+#define BIT_SET_TSF_TIMER_V1_8821C(x, v) \
+ (BIT_CLEAR_TSF_TIMER_V1_8821C(x) | BIT_TSF_TIMER_V1_8821C(v))
+
+/* 2 REG_TSFTR_1_8821C */
+
+#define BIT_SHIFT_TSF_TIMER_V2_8821C 0
+#define BIT_MASK_TSF_TIMER_V2_8821C 0xffffffffL
+#define BIT_TSF_TIMER_V2_8821C(x) \
+ (((x) & BIT_MASK_TSF_TIMER_V2_8821C) << BIT_SHIFT_TSF_TIMER_V2_8821C)
+#define BITS_TSF_TIMER_V2_8821C \
+ (BIT_MASK_TSF_TIMER_V2_8821C << BIT_SHIFT_TSF_TIMER_V2_8821C)
+#define BIT_CLEAR_TSF_TIMER_V2_8821C(x) ((x) & (~BITS_TSF_TIMER_V2_8821C))
+#define BIT_GET_TSF_TIMER_V2_8821C(x) \
+ (((x) >> BIT_SHIFT_TSF_TIMER_V2_8821C) & BIT_MASK_TSF_TIMER_V2_8821C)
+#define BIT_SET_TSF_TIMER_V2_8821C(x, v) \
+ (BIT_CLEAR_TSF_TIMER_V2_8821C(x) | BIT_TSF_TIMER_V2_8821C(v))
/* 2 REG_FREERUN_CNT_8821C */
-#define BIT_SHIFT_FREERUN_CNT_8821C 0
-#define BIT_MASK_FREERUN_CNT_8821C 0xffffffffffffffffL
-#define BIT_FREERUN_CNT_8821C(x) (((x) & BIT_MASK_FREERUN_CNT_8821C) << BIT_SHIFT_FREERUN_CNT_8821C)
-#define BIT_GET_FREERUN_CNT_8821C(x) (((x) >> BIT_SHIFT_FREERUN_CNT_8821C) & BIT_MASK_FREERUN_CNT_8821C)
-
+#define BIT_SHIFT_FREERUN_CNT_V1_8821C 0
+#define BIT_MASK_FREERUN_CNT_V1_8821C 0xffffffffL
+#define BIT_FREERUN_CNT_V1_8821C(x) \
+ (((x) & BIT_MASK_FREERUN_CNT_V1_8821C) \
+ << BIT_SHIFT_FREERUN_CNT_V1_8821C)
+#define BITS_FREERUN_CNT_V1_8821C \
+ (BIT_MASK_FREERUN_CNT_V1_8821C << BIT_SHIFT_FREERUN_CNT_V1_8821C)
+#define BIT_CLEAR_FREERUN_CNT_V1_8821C(x) ((x) & (~BITS_FREERUN_CNT_V1_8821C))
+#define BIT_GET_FREERUN_CNT_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_FREERUN_CNT_V1_8821C) & \
+ BIT_MASK_FREERUN_CNT_V1_8821C)
+#define BIT_SET_FREERUN_CNT_V1_8821C(x, v) \
+ (BIT_CLEAR_FREERUN_CNT_V1_8821C(x) | BIT_FREERUN_CNT_V1_8821C(v))
+
+/* 2 REG_FREERUN_CNT_1_8821C */
+
+#define BIT_SHIFT_FREERUN_CNT_V2_8821C 0
+#define BIT_MASK_FREERUN_CNT_V2_8821C 0xffffffffL
+#define BIT_FREERUN_CNT_V2_8821C(x) \
+ (((x) & BIT_MASK_FREERUN_CNT_V2_8821C) \
+ << BIT_SHIFT_FREERUN_CNT_V2_8821C)
+#define BITS_FREERUN_CNT_V2_8821C \
+ (BIT_MASK_FREERUN_CNT_V2_8821C << BIT_SHIFT_FREERUN_CNT_V2_8821C)
+#define BIT_CLEAR_FREERUN_CNT_V2_8821C(x) ((x) & (~BITS_FREERUN_CNT_V2_8821C))
+#define BIT_GET_FREERUN_CNT_V2_8821C(x) \
+ (((x) >> BIT_SHIFT_FREERUN_CNT_V2_8821C) & \
+ BIT_MASK_FREERUN_CNT_V2_8821C)
+#define BIT_SET_FREERUN_CNT_V2_8821C(x, v) \
+ (BIT_CLEAR_FREERUN_CNT_V2_8821C(x) | BIT_FREERUN_CNT_V2_8821C(v))
/* 2 REG_ATIMWND1_V1_8821C */
#define BIT_SHIFT_ATIMWND1_V1_8821C 0
#define BIT_MASK_ATIMWND1_V1_8821C 0xff
-#define BIT_ATIMWND1_V1_8821C(x) (((x) & BIT_MASK_ATIMWND1_V1_8821C) << BIT_SHIFT_ATIMWND1_V1_8821C)
-#define BIT_GET_ATIMWND1_V1_8821C(x) (((x) >> BIT_SHIFT_ATIMWND1_V1_8821C) & BIT_MASK_ATIMWND1_V1_8821C)
-
+#define BIT_ATIMWND1_V1_8821C(x) \
+ (((x) & BIT_MASK_ATIMWND1_V1_8821C) << BIT_SHIFT_ATIMWND1_V1_8821C)
+#define BITS_ATIMWND1_V1_8821C \
+ (BIT_MASK_ATIMWND1_V1_8821C << BIT_SHIFT_ATIMWND1_V1_8821C)
+#define BIT_CLEAR_ATIMWND1_V1_8821C(x) ((x) & (~BITS_ATIMWND1_V1_8821C))
+#define BIT_GET_ATIMWND1_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_ATIMWND1_V1_8821C) & BIT_MASK_ATIMWND1_V1_8821C)
+#define BIT_SET_ATIMWND1_V1_8821C(x, v) \
+ (BIT_CLEAR_ATIMWND1_V1_8821C(x) | BIT_ATIMWND1_V1_8821C(v))
/* 2 REG_TBTT_PROHIBIT_INFRA_8821C */
#define BIT_SHIFT_TBTT_PROHIBIT_INFRA_8821C 0
#define BIT_MASK_TBTT_PROHIBIT_INFRA_8821C 0xff
-#define BIT_TBTT_PROHIBIT_INFRA_8821C(x) (((x) & BIT_MASK_TBTT_PROHIBIT_INFRA_8821C) << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8821C)
-#define BIT_GET_TBTT_PROHIBIT_INFRA_8821C(x) (((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA_8821C) & BIT_MASK_TBTT_PROHIBIT_INFRA_8821C)
-
+#define BIT_TBTT_PROHIBIT_INFRA_8821C(x) \
+ (((x) & BIT_MASK_TBTT_PROHIBIT_INFRA_8821C) \
+ << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8821C)
+#define BITS_TBTT_PROHIBIT_INFRA_8821C \
+ (BIT_MASK_TBTT_PROHIBIT_INFRA_8821C \
+ << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8821C)
+#define BIT_CLEAR_TBTT_PROHIBIT_INFRA_8821C(x) \
+ ((x) & (~BITS_TBTT_PROHIBIT_INFRA_8821C))
+#define BIT_GET_TBTT_PROHIBIT_INFRA_8821C(x) \
+ (((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA_8821C) & \
+ BIT_MASK_TBTT_PROHIBIT_INFRA_8821C)
+#define BIT_SET_TBTT_PROHIBIT_INFRA_8821C(x, v) \
+ (BIT_CLEAR_TBTT_PROHIBIT_INFRA_8821C(x) | \
+ BIT_TBTT_PROHIBIT_INFRA_8821C(v))
/* 2 REG_CTWND_8821C */
#define BIT_SHIFT_CTWND_8821C 0
#define BIT_MASK_CTWND_8821C 0xff
-#define BIT_CTWND_8821C(x) (((x) & BIT_MASK_CTWND_8821C) << BIT_SHIFT_CTWND_8821C)
-#define BIT_GET_CTWND_8821C(x) (((x) >> BIT_SHIFT_CTWND_8821C) & BIT_MASK_CTWND_8821C)
-
+#define BIT_CTWND_8821C(x) \
+ (((x) & BIT_MASK_CTWND_8821C) << BIT_SHIFT_CTWND_8821C)
+#define BITS_CTWND_8821C (BIT_MASK_CTWND_8821C << BIT_SHIFT_CTWND_8821C)
+#define BIT_CLEAR_CTWND_8821C(x) ((x) & (~BITS_CTWND_8821C))
+#define BIT_GET_CTWND_8821C(x) \
+ (((x) >> BIT_SHIFT_CTWND_8821C) & BIT_MASK_CTWND_8821C)
+#define BIT_SET_CTWND_8821C(x, v) \
+ (BIT_CLEAR_CTWND_8821C(x) | BIT_CTWND_8821C(v))
/* 2 REG_BCNIVLCUNT_8821C */
#define BIT_SHIFT_BCNIVLCUNT_8821C 0
#define BIT_MASK_BCNIVLCUNT_8821C 0x7f
-#define BIT_BCNIVLCUNT_8821C(x) (((x) & BIT_MASK_BCNIVLCUNT_8821C) << BIT_SHIFT_BCNIVLCUNT_8821C)
-#define BIT_GET_BCNIVLCUNT_8821C(x) (((x) >> BIT_SHIFT_BCNIVLCUNT_8821C) & BIT_MASK_BCNIVLCUNT_8821C)
-
+#define BIT_BCNIVLCUNT_8821C(x) \
+ (((x) & BIT_MASK_BCNIVLCUNT_8821C) << BIT_SHIFT_BCNIVLCUNT_8821C)
+#define BITS_BCNIVLCUNT_8821C \
+ (BIT_MASK_BCNIVLCUNT_8821C << BIT_SHIFT_BCNIVLCUNT_8821C)
+#define BIT_CLEAR_BCNIVLCUNT_8821C(x) ((x) & (~BITS_BCNIVLCUNT_8821C))
+#define BIT_GET_BCNIVLCUNT_8821C(x) \
+ (((x) >> BIT_SHIFT_BCNIVLCUNT_8821C) & BIT_MASK_BCNIVLCUNT_8821C)
+#define BIT_SET_BCNIVLCUNT_8821C(x, v) \
+ (BIT_CLEAR_BCNIVLCUNT_8821C(x) | BIT_BCNIVLCUNT_8821C(v))
/* 2 REG_BCNDROPCTRL_8821C */
#define BIT_BEACON_DROP_EN_8821C BIT(7)
#define BIT_SHIFT_BEACON_DROP_IVL_8821C 0
#define BIT_MASK_BEACON_DROP_IVL_8821C 0x7f
-#define BIT_BEACON_DROP_IVL_8821C(x) (((x) & BIT_MASK_BEACON_DROP_IVL_8821C) << BIT_SHIFT_BEACON_DROP_IVL_8821C)
-#define BIT_GET_BEACON_DROP_IVL_8821C(x) (((x) >> BIT_SHIFT_BEACON_DROP_IVL_8821C) & BIT_MASK_BEACON_DROP_IVL_8821C)
-
+#define BIT_BEACON_DROP_IVL_8821C(x) \
+ (((x) & BIT_MASK_BEACON_DROP_IVL_8821C) \
+ << BIT_SHIFT_BEACON_DROP_IVL_8821C)
+#define BITS_BEACON_DROP_IVL_8821C \
+ (BIT_MASK_BEACON_DROP_IVL_8821C << BIT_SHIFT_BEACON_DROP_IVL_8821C)
+#define BIT_CLEAR_BEACON_DROP_IVL_8821C(x) ((x) & (~BITS_BEACON_DROP_IVL_8821C))
+#define BIT_GET_BEACON_DROP_IVL_8821C(x) \
+ (((x) >> BIT_SHIFT_BEACON_DROP_IVL_8821C) & \
+ BIT_MASK_BEACON_DROP_IVL_8821C)
+#define BIT_SET_BEACON_DROP_IVL_8821C(x, v) \
+ (BIT_CLEAR_BEACON_DROP_IVL_8821C(x) | BIT_BEACON_DROP_IVL_8821C(v))
/* 2 REG_HGQ_TIMEOUT_PERIOD_8821C */
#define BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8821C 0
#define BIT_MASK_HGQ_TIMEOUT_PERIOD_8821C 0xff
-#define BIT_HGQ_TIMEOUT_PERIOD_8821C(x) (((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8821C) << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8821C)
-#define BIT_GET_HGQ_TIMEOUT_PERIOD_8821C(x) (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8821C) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8821C)
-
+#define BIT_HGQ_TIMEOUT_PERIOD_8821C(x) \
+ (((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8821C) \
+ << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8821C)
+#define BITS_HGQ_TIMEOUT_PERIOD_8821C \
+ (BIT_MASK_HGQ_TIMEOUT_PERIOD_8821C \
+ << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8821C)
+#define BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8821C(x) \
+ ((x) & (~BITS_HGQ_TIMEOUT_PERIOD_8821C))
+#define BIT_GET_HGQ_TIMEOUT_PERIOD_8821C(x) \
+ (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8821C) & \
+ BIT_MASK_HGQ_TIMEOUT_PERIOD_8821C)
+#define BIT_SET_HGQ_TIMEOUT_PERIOD_8821C(x, v) \
+ (BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8821C(x) | \
+ BIT_HGQ_TIMEOUT_PERIOD_8821C(v))
/* 2 REG_TXCMD_TIMEOUT_PERIOD_8821C */
#define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8821C 0
#define BIT_MASK_TXCMD_TIMEOUT_PERIOD_8821C 0xff
-#define BIT_TXCMD_TIMEOUT_PERIOD_8821C(x) (((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8821C) << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8821C)
-#define BIT_GET_TXCMD_TIMEOUT_PERIOD_8821C(x) (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8821C) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8821C)
-
+#define BIT_TXCMD_TIMEOUT_PERIOD_8821C(x) \
+ (((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8821C) \
+ << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8821C)
+#define BITS_TXCMD_TIMEOUT_PERIOD_8821C \
+ (BIT_MASK_TXCMD_TIMEOUT_PERIOD_8821C \
+ << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8821C)
+#define BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8821C(x) \
+ ((x) & (~BITS_TXCMD_TIMEOUT_PERIOD_8821C))
+#define BIT_GET_TXCMD_TIMEOUT_PERIOD_8821C(x) \
+ (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8821C) & \
+ BIT_MASK_TXCMD_TIMEOUT_PERIOD_8821C)
+#define BIT_SET_TXCMD_TIMEOUT_PERIOD_8821C(x, v) \
+ (BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8821C(x) | \
+ BIT_TXCMD_TIMEOUT_PERIOD_8821C(v))
/* 2 REG_MISC_CTRL_8821C */
+#define BIT_AUTO_SYNC_BY_TBTT_8821C BIT(6)
#define BIT_DIS_TRX_CAL_BCN_8821C BIT(5)
#define BIT_DIS_TX_CAL_TBTT_8821C BIT(4)
#define BIT_EN_FREECNT_8821C BIT(3)
@@ -6868,9 +12869,18 @@
#define BIT_SHIFT_DIS_SECONDARY_CCA_8821C 0
#define BIT_MASK_DIS_SECONDARY_CCA_8821C 0x3
-#define BIT_DIS_SECONDARY_CCA_8821C(x) (((x) & BIT_MASK_DIS_SECONDARY_CCA_8821C) << BIT_SHIFT_DIS_SECONDARY_CCA_8821C)
-#define BIT_GET_DIS_SECONDARY_CCA_8821C(x) (((x) >> BIT_SHIFT_DIS_SECONDARY_CCA_8821C) & BIT_MASK_DIS_SECONDARY_CCA_8821C)
-
+#define BIT_DIS_SECONDARY_CCA_8821C(x) \
+ (((x) & BIT_MASK_DIS_SECONDARY_CCA_8821C) \
+ << BIT_SHIFT_DIS_SECONDARY_CCA_8821C)
+#define BITS_DIS_SECONDARY_CCA_8821C \
+ (BIT_MASK_DIS_SECONDARY_CCA_8821C << BIT_SHIFT_DIS_SECONDARY_CCA_8821C)
+#define BIT_CLEAR_DIS_SECONDARY_CCA_8821C(x) \
+ ((x) & (~BITS_DIS_SECONDARY_CCA_8821C))
+#define BIT_GET_DIS_SECONDARY_CCA_8821C(x) \
+ (((x) >> BIT_SHIFT_DIS_SECONDARY_CCA_8821C) & \
+ BIT_MASK_DIS_SECONDARY_CCA_8821C)
+#define BIT_SET_DIS_SECONDARY_CCA_8821C(x, v) \
+ (BIT_CLEAR_DIS_SECONDARY_CCA_8821C(x) | BIT_DIS_SECONDARY_CCA_8821C(v))
/* 2 REG_BCN_CTRL_CLINT1_8821C */
#define BIT_CLI1_DIS_RX_BSSID_FIT_8821C BIT(6)
@@ -6902,9 +12912,15 @@
#define BIT_SHIFT_PORT_SEL_8821C 0
#define BIT_MASK_PORT_SEL_8821C 0x7
-#define BIT_PORT_SEL_8821C(x) (((x) & BIT_MASK_PORT_SEL_8821C) << BIT_SHIFT_PORT_SEL_8821C)
-#define BIT_GET_PORT_SEL_8821C(x) (((x) >> BIT_SHIFT_PORT_SEL_8821C) & BIT_MASK_PORT_SEL_8821C)
-
+#define BIT_PORT_SEL_8821C(x) \
+ (((x) & BIT_MASK_PORT_SEL_8821C) << BIT_SHIFT_PORT_SEL_8821C)
+#define BITS_PORT_SEL_8821C \
+ (BIT_MASK_PORT_SEL_8821C << BIT_SHIFT_PORT_SEL_8821C)
+#define BIT_CLEAR_PORT_SEL_8821C(x) ((x) & (~BITS_PORT_SEL_8821C))
+#define BIT_GET_PORT_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_PORT_SEL_8821C) & BIT_MASK_PORT_SEL_8821C)
+#define BIT_SET_PORT_SEL_8821C(x, v) \
+ (BIT_CLEAR_PORT_SEL_8821C(x) | BIT_PORT_SEL_8821C(v))
/* 2 REG_P2PPS1_SPEC_STATE_8821C */
#define BIT_P2P1_SPEC_POWER_STATE_8821C BIT(7)
@@ -6950,57 +12966,103 @@
#define BIT_SHIFT_PSTIMER0_INT_8821C 5
#define BIT_MASK_PSTIMER0_INT_8821C 0x7ffffff
-#define BIT_PSTIMER0_INT_8821C(x) (((x) & BIT_MASK_PSTIMER0_INT_8821C) << BIT_SHIFT_PSTIMER0_INT_8821C)
-#define BIT_GET_PSTIMER0_INT_8821C(x) (((x) >> BIT_SHIFT_PSTIMER0_INT_8821C) & BIT_MASK_PSTIMER0_INT_8821C)
-
+#define BIT_PSTIMER0_INT_8821C(x) \
+ (((x) & BIT_MASK_PSTIMER0_INT_8821C) << BIT_SHIFT_PSTIMER0_INT_8821C)
+#define BITS_PSTIMER0_INT_8821C \
+ (BIT_MASK_PSTIMER0_INT_8821C << BIT_SHIFT_PSTIMER0_INT_8821C)
+#define BIT_CLEAR_PSTIMER0_INT_8821C(x) ((x) & (~BITS_PSTIMER0_INT_8821C))
+#define BIT_GET_PSTIMER0_INT_8821C(x) \
+ (((x) >> BIT_SHIFT_PSTIMER0_INT_8821C) & BIT_MASK_PSTIMER0_INT_8821C)
+#define BIT_SET_PSTIMER0_INT_8821C(x, v) \
+ (BIT_CLEAR_PSTIMER0_INT_8821C(x) | BIT_PSTIMER0_INT_8821C(v))
/* 2 REG_PS_TIMER1_8821C */
#define BIT_SHIFT_PSTIMER1_INT_8821C 5
#define BIT_MASK_PSTIMER1_INT_8821C 0x7ffffff
-#define BIT_PSTIMER1_INT_8821C(x) (((x) & BIT_MASK_PSTIMER1_INT_8821C) << BIT_SHIFT_PSTIMER1_INT_8821C)
-#define BIT_GET_PSTIMER1_INT_8821C(x) (((x) >> BIT_SHIFT_PSTIMER1_INT_8821C) & BIT_MASK_PSTIMER1_INT_8821C)
-
+#define BIT_PSTIMER1_INT_8821C(x) \
+ (((x) & BIT_MASK_PSTIMER1_INT_8821C) << BIT_SHIFT_PSTIMER1_INT_8821C)
+#define BITS_PSTIMER1_INT_8821C \
+ (BIT_MASK_PSTIMER1_INT_8821C << BIT_SHIFT_PSTIMER1_INT_8821C)
+#define BIT_CLEAR_PSTIMER1_INT_8821C(x) ((x) & (~BITS_PSTIMER1_INT_8821C))
+#define BIT_GET_PSTIMER1_INT_8821C(x) \
+ (((x) >> BIT_SHIFT_PSTIMER1_INT_8821C) & BIT_MASK_PSTIMER1_INT_8821C)
+#define BIT_SET_PSTIMER1_INT_8821C(x, v) \
+ (BIT_CLEAR_PSTIMER1_INT_8821C(x) | BIT_PSTIMER1_INT_8821C(v))
/* 2 REG_PS_TIMER2_8821C */
#define BIT_SHIFT_PSTIMER2_INT_8821C 5
#define BIT_MASK_PSTIMER2_INT_8821C 0x7ffffff
-#define BIT_PSTIMER2_INT_8821C(x) (((x) & BIT_MASK_PSTIMER2_INT_8821C) << BIT_SHIFT_PSTIMER2_INT_8821C)
-#define BIT_GET_PSTIMER2_INT_8821C(x) (((x) >> BIT_SHIFT_PSTIMER2_INT_8821C) & BIT_MASK_PSTIMER2_INT_8821C)
-
+#define BIT_PSTIMER2_INT_8821C(x) \
+ (((x) & BIT_MASK_PSTIMER2_INT_8821C) << BIT_SHIFT_PSTIMER2_INT_8821C)
+#define BITS_PSTIMER2_INT_8821C \
+ (BIT_MASK_PSTIMER2_INT_8821C << BIT_SHIFT_PSTIMER2_INT_8821C)
+#define BIT_CLEAR_PSTIMER2_INT_8821C(x) ((x) & (~BITS_PSTIMER2_INT_8821C))
+#define BIT_GET_PSTIMER2_INT_8821C(x) \
+ (((x) >> BIT_SHIFT_PSTIMER2_INT_8821C) & BIT_MASK_PSTIMER2_INT_8821C)
+#define BIT_SET_PSTIMER2_INT_8821C(x, v) \
+ (BIT_CLEAR_PSTIMER2_INT_8821C(x) | BIT_PSTIMER2_INT_8821C(v))
/* 2 REG_TBTT_CTN_AREA_8821C */
#define BIT_SHIFT_TBTT_CTN_AREA_8821C 0
#define BIT_MASK_TBTT_CTN_AREA_8821C 0xff
-#define BIT_TBTT_CTN_AREA_8821C(x) (((x) & BIT_MASK_TBTT_CTN_AREA_8821C) << BIT_SHIFT_TBTT_CTN_AREA_8821C)
-#define BIT_GET_TBTT_CTN_AREA_8821C(x) (((x) >> BIT_SHIFT_TBTT_CTN_AREA_8821C) & BIT_MASK_TBTT_CTN_AREA_8821C)
+#define BIT_TBTT_CTN_AREA_8821C(x) \
+ (((x) & BIT_MASK_TBTT_CTN_AREA_8821C) << BIT_SHIFT_TBTT_CTN_AREA_8821C)
+#define BITS_TBTT_CTN_AREA_8821C \
+ (BIT_MASK_TBTT_CTN_AREA_8821C << BIT_SHIFT_TBTT_CTN_AREA_8821C)
+#define BIT_CLEAR_TBTT_CTN_AREA_8821C(x) ((x) & (~BITS_TBTT_CTN_AREA_8821C))
+#define BIT_GET_TBTT_CTN_AREA_8821C(x) \
+ (((x) >> BIT_SHIFT_TBTT_CTN_AREA_8821C) & BIT_MASK_TBTT_CTN_AREA_8821C)
+#define BIT_SET_TBTT_CTN_AREA_8821C(x, v) \
+ (BIT_CLEAR_TBTT_CTN_AREA_8821C(x) | BIT_TBTT_CTN_AREA_8821C(v))
+/* 2 REG_NOT_VALID_8821C */
/* 2 REG_FORCE_BCN_IFS_8821C */
#define BIT_SHIFT_FORCE_BCN_IFS_8821C 0
#define BIT_MASK_FORCE_BCN_IFS_8821C 0xff
-#define BIT_FORCE_BCN_IFS_8821C(x) (((x) & BIT_MASK_FORCE_BCN_IFS_8821C) << BIT_SHIFT_FORCE_BCN_IFS_8821C)
-#define BIT_GET_FORCE_BCN_IFS_8821C(x) (((x) >> BIT_SHIFT_FORCE_BCN_IFS_8821C) & BIT_MASK_FORCE_BCN_IFS_8821C)
+#define BIT_FORCE_BCN_IFS_8821C(x) \
+ (((x) & BIT_MASK_FORCE_BCN_IFS_8821C) << BIT_SHIFT_FORCE_BCN_IFS_8821C)
+#define BITS_FORCE_BCN_IFS_8821C \
+ (BIT_MASK_FORCE_BCN_IFS_8821C << BIT_SHIFT_FORCE_BCN_IFS_8821C)
+#define BIT_CLEAR_FORCE_BCN_IFS_8821C(x) ((x) & (~BITS_FORCE_BCN_IFS_8821C))
+#define BIT_GET_FORCE_BCN_IFS_8821C(x) \
+ (((x) >> BIT_SHIFT_FORCE_BCN_IFS_8821C) & BIT_MASK_FORCE_BCN_IFS_8821C)
+#define BIT_SET_FORCE_BCN_IFS_8821C(x, v) \
+ (BIT_CLEAR_FORCE_BCN_IFS_8821C(x) | BIT_FORCE_BCN_IFS_8821C(v))
+/* 2 REG_NOT_VALID_8821C */
/* 2 REG_TXOP_MIN_8821C */
#define BIT_SHIFT_TXOP_MIN_8821C 0
#define BIT_MASK_TXOP_MIN_8821C 0x3fff
-#define BIT_TXOP_MIN_8821C(x) (((x) & BIT_MASK_TXOP_MIN_8821C) << BIT_SHIFT_TXOP_MIN_8821C)
-#define BIT_GET_TXOP_MIN_8821C(x) (((x) >> BIT_SHIFT_TXOP_MIN_8821C) & BIT_MASK_TXOP_MIN_8821C)
-
+#define BIT_TXOP_MIN_8821C(x) \
+ (((x) & BIT_MASK_TXOP_MIN_8821C) << BIT_SHIFT_TXOP_MIN_8821C)
+#define BITS_TXOP_MIN_8821C \
+ (BIT_MASK_TXOP_MIN_8821C << BIT_SHIFT_TXOP_MIN_8821C)
+#define BIT_CLEAR_TXOP_MIN_8821C(x) ((x) & (~BITS_TXOP_MIN_8821C))
+#define BIT_GET_TXOP_MIN_8821C(x) \
+ (((x) >> BIT_SHIFT_TXOP_MIN_8821C) & BIT_MASK_TXOP_MIN_8821C)
+#define BIT_SET_TXOP_MIN_8821C(x, v) \
+ (BIT_CLEAR_TXOP_MIN_8821C(x) | BIT_TXOP_MIN_8821C(v))
/* 2 REG_PRE_BKF_TIME_8821C */
#define BIT_SHIFT_PRE_BKF_TIME_8821C 0
#define BIT_MASK_PRE_BKF_TIME_8821C 0xff
-#define BIT_PRE_BKF_TIME_8821C(x) (((x) & BIT_MASK_PRE_BKF_TIME_8821C) << BIT_SHIFT_PRE_BKF_TIME_8821C)
-#define BIT_GET_PRE_BKF_TIME_8821C(x) (((x) >> BIT_SHIFT_PRE_BKF_TIME_8821C) & BIT_MASK_PRE_BKF_TIME_8821C)
-
+#define BIT_PRE_BKF_TIME_8821C(x) \
+ (((x) & BIT_MASK_PRE_BKF_TIME_8821C) << BIT_SHIFT_PRE_BKF_TIME_8821C)
+#define BITS_PRE_BKF_TIME_8821C \
+ (BIT_MASK_PRE_BKF_TIME_8821C << BIT_SHIFT_PRE_BKF_TIME_8821C)
+#define BIT_CLEAR_PRE_BKF_TIME_8821C(x) ((x) & (~BITS_PRE_BKF_TIME_8821C))
+#define BIT_GET_PRE_BKF_TIME_8821C(x) \
+ (((x) >> BIT_SHIFT_PRE_BKF_TIME_8821C) & BIT_MASK_PRE_BKF_TIME_8821C)
+#define BIT_SET_PRE_BKF_TIME_8821C(x, v) \
+ (BIT_CLEAR_PRE_BKF_TIME_8821C(x) | BIT_PRE_BKF_TIME_8821C(v))
/* 2 REG_CROSS_TXOP_CTRL_8821C */
#define BIT_TXFAIL_BREACK_TXOP_EN_8821C BIT(3)
@@ -7008,61 +13070,109 @@
#define BIT_RTS_NAV_TXOP_8821C BIT(1)
#define BIT_NOT_CROSS_TXOP_8821C BIT(0)
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
/* 2 REG_ATIMWND2_8821C */
#define BIT_SHIFT_ATIMWND2_8821C 0
#define BIT_MASK_ATIMWND2_8821C 0xff
-#define BIT_ATIMWND2_8821C(x) (((x) & BIT_MASK_ATIMWND2_8821C) << BIT_SHIFT_ATIMWND2_8821C)
-#define BIT_GET_ATIMWND2_8821C(x) (((x) >> BIT_SHIFT_ATIMWND2_8821C) & BIT_MASK_ATIMWND2_8821C)
-
+#define BIT_ATIMWND2_8821C(x) \
+ (((x) & BIT_MASK_ATIMWND2_8821C) << BIT_SHIFT_ATIMWND2_8821C)
+#define BITS_ATIMWND2_8821C \
+ (BIT_MASK_ATIMWND2_8821C << BIT_SHIFT_ATIMWND2_8821C)
+#define BIT_CLEAR_ATIMWND2_8821C(x) ((x) & (~BITS_ATIMWND2_8821C))
+#define BIT_GET_ATIMWND2_8821C(x) \
+ (((x) >> BIT_SHIFT_ATIMWND2_8821C) & BIT_MASK_ATIMWND2_8821C)
+#define BIT_SET_ATIMWND2_8821C(x, v) \
+ (BIT_CLEAR_ATIMWND2_8821C(x) | BIT_ATIMWND2_8821C(v))
/* 2 REG_ATIMWND3_8821C */
#define BIT_SHIFT_ATIMWND3_8821C 0
#define BIT_MASK_ATIMWND3_8821C 0xff
-#define BIT_ATIMWND3_8821C(x) (((x) & BIT_MASK_ATIMWND3_8821C) << BIT_SHIFT_ATIMWND3_8821C)
-#define BIT_GET_ATIMWND3_8821C(x) (((x) >> BIT_SHIFT_ATIMWND3_8821C) & BIT_MASK_ATIMWND3_8821C)
-
+#define BIT_ATIMWND3_8821C(x) \
+ (((x) & BIT_MASK_ATIMWND3_8821C) << BIT_SHIFT_ATIMWND3_8821C)
+#define BITS_ATIMWND3_8821C \
+ (BIT_MASK_ATIMWND3_8821C << BIT_SHIFT_ATIMWND3_8821C)
+#define BIT_CLEAR_ATIMWND3_8821C(x) ((x) & (~BITS_ATIMWND3_8821C))
+#define BIT_GET_ATIMWND3_8821C(x) \
+ (((x) >> BIT_SHIFT_ATIMWND3_8821C) & BIT_MASK_ATIMWND3_8821C)
+#define BIT_SET_ATIMWND3_8821C(x, v) \
+ (BIT_CLEAR_ATIMWND3_8821C(x) | BIT_ATIMWND3_8821C(v))
/* 2 REG_ATIMWND4_8821C */
#define BIT_SHIFT_ATIMWND4_8821C 0
#define BIT_MASK_ATIMWND4_8821C 0xff
-#define BIT_ATIMWND4_8821C(x) (((x) & BIT_MASK_ATIMWND4_8821C) << BIT_SHIFT_ATIMWND4_8821C)
-#define BIT_GET_ATIMWND4_8821C(x) (((x) >> BIT_SHIFT_ATIMWND4_8821C) & BIT_MASK_ATIMWND4_8821C)
-
+#define BIT_ATIMWND4_8821C(x) \
+ (((x) & BIT_MASK_ATIMWND4_8821C) << BIT_SHIFT_ATIMWND4_8821C)
+#define BITS_ATIMWND4_8821C \
+ (BIT_MASK_ATIMWND4_8821C << BIT_SHIFT_ATIMWND4_8821C)
+#define BIT_CLEAR_ATIMWND4_8821C(x) ((x) & (~BITS_ATIMWND4_8821C))
+#define BIT_GET_ATIMWND4_8821C(x) \
+ (((x) >> BIT_SHIFT_ATIMWND4_8821C) & BIT_MASK_ATIMWND4_8821C)
+#define BIT_SET_ATIMWND4_8821C(x, v) \
+ (BIT_CLEAR_ATIMWND4_8821C(x) | BIT_ATIMWND4_8821C(v))
/* 2 REG_ATIMWND5_8821C */
#define BIT_SHIFT_ATIMWND5_8821C 0
#define BIT_MASK_ATIMWND5_8821C 0xff
-#define BIT_ATIMWND5_8821C(x) (((x) & BIT_MASK_ATIMWND5_8821C) << BIT_SHIFT_ATIMWND5_8821C)
-#define BIT_GET_ATIMWND5_8821C(x) (((x) >> BIT_SHIFT_ATIMWND5_8821C) & BIT_MASK_ATIMWND5_8821C)
-
+#define BIT_ATIMWND5_8821C(x) \
+ (((x) & BIT_MASK_ATIMWND5_8821C) << BIT_SHIFT_ATIMWND5_8821C)
+#define BITS_ATIMWND5_8821C \
+ (BIT_MASK_ATIMWND5_8821C << BIT_SHIFT_ATIMWND5_8821C)
+#define BIT_CLEAR_ATIMWND5_8821C(x) ((x) & (~BITS_ATIMWND5_8821C))
+#define BIT_GET_ATIMWND5_8821C(x) \
+ (((x) >> BIT_SHIFT_ATIMWND5_8821C) & BIT_MASK_ATIMWND5_8821C)
+#define BIT_SET_ATIMWND5_8821C(x, v) \
+ (BIT_CLEAR_ATIMWND5_8821C(x) | BIT_ATIMWND5_8821C(v))
/* 2 REG_ATIMWND6_8821C */
#define BIT_SHIFT_ATIMWND6_8821C 0
#define BIT_MASK_ATIMWND6_8821C 0xff
-#define BIT_ATIMWND6_8821C(x) (((x) & BIT_MASK_ATIMWND6_8821C) << BIT_SHIFT_ATIMWND6_8821C)
-#define BIT_GET_ATIMWND6_8821C(x) (((x) >> BIT_SHIFT_ATIMWND6_8821C) & BIT_MASK_ATIMWND6_8821C)
-
+#define BIT_ATIMWND6_8821C(x) \
+ (((x) & BIT_MASK_ATIMWND6_8821C) << BIT_SHIFT_ATIMWND6_8821C)
+#define BITS_ATIMWND6_8821C \
+ (BIT_MASK_ATIMWND6_8821C << BIT_SHIFT_ATIMWND6_8821C)
+#define BIT_CLEAR_ATIMWND6_8821C(x) ((x) & (~BITS_ATIMWND6_8821C))
+#define BIT_GET_ATIMWND6_8821C(x) \
+ (((x) >> BIT_SHIFT_ATIMWND6_8821C) & BIT_MASK_ATIMWND6_8821C)
+#define BIT_SET_ATIMWND6_8821C(x, v) \
+ (BIT_CLEAR_ATIMWND6_8821C(x) | BIT_ATIMWND6_8821C(v))
/* 2 REG_ATIMWND7_8821C */
#define BIT_SHIFT_ATIMWND7_8821C 0
#define BIT_MASK_ATIMWND7_8821C 0xff
-#define BIT_ATIMWND7_8821C(x) (((x) & BIT_MASK_ATIMWND7_8821C) << BIT_SHIFT_ATIMWND7_8821C)
-#define BIT_GET_ATIMWND7_8821C(x) (((x) >> BIT_SHIFT_ATIMWND7_8821C) & BIT_MASK_ATIMWND7_8821C)
-
+#define BIT_ATIMWND7_8821C(x) \
+ (((x) & BIT_MASK_ATIMWND7_8821C) << BIT_SHIFT_ATIMWND7_8821C)
+#define BITS_ATIMWND7_8821C \
+ (BIT_MASK_ATIMWND7_8821C << BIT_SHIFT_ATIMWND7_8821C)
+#define BIT_CLEAR_ATIMWND7_8821C(x) ((x) & (~BITS_ATIMWND7_8821C))
+#define BIT_GET_ATIMWND7_8821C(x) \
+ (((x) >> BIT_SHIFT_ATIMWND7_8821C) & BIT_MASK_ATIMWND7_8821C)
+#define BIT_SET_ATIMWND7_8821C(x, v) \
+ (BIT_CLEAR_ATIMWND7_8821C(x) | BIT_ATIMWND7_8821C(v))
/* 2 REG_ATIMUGT_8821C */
#define BIT_SHIFT_ATIM_URGENT_8821C 0
#define BIT_MASK_ATIM_URGENT_8821C 0xff
-#define BIT_ATIM_URGENT_8821C(x) (((x) & BIT_MASK_ATIM_URGENT_8821C) << BIT_SHIFT_ATIM_URGENT_8821C)
-#define BIT_GET_ATIM_URGENT_8821C(x) (((x) >> BIT_SHIFT_ATIM_URGENT_8821C) & BIT_MASK_ATIM_URGENT_8821C)
-
+#define BIT_ATIM_URGENT_8821C(x) \
+ (((x) & BIT_MASK_ATIM_URGENT_8821C) << BIT_SHIFT_ATIM_URGENT_8821C)
+#define BITS_ATIM_URGENT_8821C \
+ (BIT_MASK_ATIM_URGENT_8821C << BIT_SHIFT_ATIM_URGENT_8821C)
+#define BIT_CLEAR_ATIM_URGENT_8821C(x) ((x) & (~BITS_ATIM_URGENT_8821C))
+#define BIT_GET_ATIM_URGENT_8821C(x) \
+ (((x) >> BIT_SHIFT_ATIM_URGENT_8821C) & BIT_MASK_ATIM_URGENT_8821C)
+#define BIT_SET_ATIM_URGENT_8821C(x, v) \
+ (BIT_CLEAR_ATIM_URGENT_8821C(x) | BIT_ATIM_URGENT_8821C(v))
/* 2 REG_HIQ_NO_LMT_EN_8821C */
#define BIT_HIQ_NO_LMT_EN_VAP7_8821C BIT(7)
@@ -7078,65 +13188,129 @@
#define BIT_SHIFT_DTIM_COUNT_ROOT_8821C 0
#define BIT_MASK_DTIM_COUNT_ROOT_8821C 0xff
-#define BIT_DTIM_COUNT_ROOT_8821C(x) (((x) & BIT_MASK_DTIM_COUNT_ROOT_8821C) << BIT_SHIFT_DTIM_COUNT_ROOT_8821C)
-#define BIT_GET_DTIM_COUNT_ROOT_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_ROOT_8821C) & BIT_MASK_DTIM_COUNT_ROOT_8821C)
-
+#define BIT_DTIM_COUNT_ROOT_8821C(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_ROOT_8821C) \
+ << BIT_SHIFT_DTIM_COUNT_ROOT_8821C)
+#define BITS_DTIM_COUNT_ROOT_8821C \
+ (BIT_MASK_DTIM_COUNT_ROOT_8821C << BIT_SHIFT_DTIM_COUNT_ROOT_8821C)
+#define BIT_CLEAR_DTIM_COUNT_ROOT_8821C(x) ((x) & (~BITS_DTIM_COUNT_ROOT_8821C))
+#define BIT_GET_DTIM_COUNT_ROOT_8821C(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_ROOT_8821C) & \
+ BIT_MASK_DTIM_COUNT_ROOT_8821C)
+#define BIT_SET_DTIM_COUNT_ROOT_8821C(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_ROOT_8821C(x) | BIT_DTIM_COUNT_ROOT_8821C(v))
/* 2 REG_DTIM_COUNTER_VAP1_8821C */
#define BIT_SHIFT_DTIM_COUNT_VAP1_8821C 0
#define BIT_MASK_DTIM_COUNT_VAP1_8821C 0xff
-#define BIT_DTIM_COUNT_VAP1_8821C(x) (((x) & BIT_MASK_DTIM_COUNT_VAP1_8821C) << BIT_SHIFT_DTIM_COUNT_VAP1_8821C)
-#define BIT_GET_DTIM_COUNT_VAP1_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP1_8821C) & BIT_MASK_DTIM_COUNT_VAP1_8821C)
-
+#define BIT_DTIM_COUNT_VAP1_8821C(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_VAP1_8821C) \
+ << BIT_SHIFT_DTIM_COUNT_VAP1_8821C)
+#define BITS_DTIM_COUNT_VAP1_8821C \
+ (BIT_MASK_DTIM_COUNT_VAP1_8821C << BIT_SHIFT_DTIM_COUNT_VAP1_8821C)
+#define BIT_CLEAR_DTIM_COUNT_VAP1_8821C(x) ((x) & (~BITS_DTIM_COUNT_VAP1_8821C))
+#define BIT_GET_DTIM_COUNT_VAP1_8821C(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP1_8821C) & \
+ BIT_MASK_DTIM_COUNT_VAP1_8821C)
+#define BIT_SET_DTIM_COUNT_VAP1_8821C(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_VAP1_8821C(x) | BIT_DTIM_COUNT_VAP1_8821C(v))
/* 2 REG_DTIM_COUNTER_VAP2_8821C */
#define BIT_SHIFT_DTIM_COUNT_VAP2_8821C 0
#define BIT_MASK_DTIM_COUNT_VAP2_8821C 0xff
-#define BIT_DTIM_COUNT_VAP2_8821C(x) (((x) & BIT_MASK_DTIM_COUNT_VAP2_8821C) << BIT_SHIFT_DTIM_COUNT_VAP2_8821C)
-#define BIT_GET_DTIM_COUNT_VAP2_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP2_8821C) & BIT_MASK_DTIM_COUNT_VAP2_8821C)
-
+#define BIT_DTIM_COUNT_VAP2_8821C(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_VAP2_8821C) \
+ << BIT_SHIFT_DTIM_COUNT_VAP2_8821C)
+#define BITS_DTIM_COUNT_VAP2_8821C \
+ (BIT_MASK_DTIM_COUNT_VAP2_8821C << BIT_SHIFT_DTIM_COUNT_VAP2_8821C)
+#define BIT_CLEAR_DTIM_COUNT_VAP2_8821C(x) ((x) & (~BITS_DTIM_COUNT_VAP2_8821C))
+#define BIT_GET_DTIM_COUNT_VAP2_8821C(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP2_8821C) & \
+ BIT_MASK_DTIM_COUNT_VAP2_8821C)
+#define BIT_SET_DTIM_COUNT_VAP2_8821C(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_VAP2_8821C(x) | BIT_DTIM_COUNT_VAP2_8821C(v))
/* 2 REG_DTIM_COUNTER_VAP3_8821C */
#define BIT_SHIFT_DTIM_COUNT_VAP3_8821C 0
#define BIT_MASK_DTIM_COUNT_VAP3_8821C 0xff
-#define BIT_DTIM_COUNT_VAP3_8821C(x) (((x) & BIT_MASK_DTIM_COUNT_VAP3_8821C) << BIT_SHIFT_DTIM_COUNT_VAP3_8821C)
-#define BIT_GET_DTIM_COUNT_VAP3_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP3_8821C) & BIT_MASK_DTIM_COUNT_VAP3_8821C)
-
+#define BIT_DTIM_COUNT_VAP3_8821C(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_VAP3_8821C) \
+ << BIT_SHIFT_DTIM_COUNT_VAP3_8821C)
+#define BITS_DTIM_COUNT_VAP3_8821C \
+ (BIT_MASK_DTIM_COUNT_VAP3_8821C << BIT_SHIFT_DTIM_COUNT_VAP3_8821C)
+#define BIT_CLEAR_DTIM_COUNT_VAP3_8821C(x) ((x) & (~BITS_DTIM_COUNT_VAP3_8821C))
+#define BIT_GET_DTIM_COUNT_VAP3_8821C(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP3_8821C) & \
+ BIT_MASK_DTIM_COUNT_VAP3_8821C)
+#define BIT_SET_DTIM_COUNT_VAP3_8821C(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_VAP3_8821C(x) | BIT_DTIM_COUNT_VAP3_8821C(v))
/* 2 REG_DTIM_COUNTER_VAP4_8821C */
#define BIT_SHIFT_DTIM_COUNT_VAP4_8821C 0
#define BIT_MASK_DTIM_COUNT_VAP4_8821C 0xff
-#define BIT_DTIM_COUNT_VAP4_8821C(x) (((x) & BIT_MASK_DTIM_COUNT_VAP4_8821C) << BIT_SHIFT_DTIM_COUNT_VAP4_8821C)
-#define BIT_GET_DTIM_COUNT_VAP4_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP4_8821C) & BIT_MASK_DTIM_COUNT_VAP4_8821C)
-
+#define BIT_DTIM_COUNT_VAP4_8821C(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_VAP4_8821C) \
+ << BIT_SHIFT_DTIM_COUNT_VAP4_8821C)
+#define BITS_DTIM_COUNT_VAP4_8821C \
+ (BIT_MASK_DTIM_COUNT_VAP4_8821C << BIT_SHIFT_DTIM_COUNT_VAP4_8821C)
+#define BIT_CLEAR_DTIM_COUNT_VAP4_8821C(x) ((x) & (~BITS_DTIM_COUNT_VAP4_8821C))
+#define BIT_GET_DTIM_COUNT_VAP4_8821C(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP4_8821C) & \
+ BIT_MASK_DTIM_COUNT_VAP4_8821C)
+#define BIT_SET_DTIM_COUNT_VAP4_8821C(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_VAP4_8821C(x) | BIT_DTIM_COUNT_VAP4_8821C(v))
/* 2 REG_DTIM_COUNTER_VAP5_8821C */
#define BIT_SHIFT_DTIM_COUNT_VAP5_8821C 0
#define BIT_MASK_DTIM_COUNT_VAP5_8821C 0xff
-#define BIT_DTIM_COUNT_VAP5_8821C(x) (((x) & BIT_MASK_DTIM_COUNT_VAP5_8821C) << BIT_SHIFT_DTIM_COUNT_VAP5_8821C)
-#define BIT_GET_DTIM_COUNT_VAP5_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP5_8821C) & BIT_MASK_DTIM_COUNT_VAP5_8821C)
-
+#define BIT_DTIM_COUNT_VAP5_8821C(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_VAP5_8821C) \
+ << BIT_SHIFT_DTIM_COUNT_VAP5_8821C)
+#define BITS_DTIM_COUNT_VAP5_8821C \
+ (BIT_MASK_DTIM_COUNT_VAP5_8821C << BIT_SHIFT_DTIM_COUNT_VAP5_8821C)
+#define BIT_CLEAR_DTIM_COUNT_VAP5_8821C(x) ((x) & (~BITS_DTIM_COUNT_VAP5_8821C))
+#define BIT_GET_DTIM_COUNT_VAP5_8821C(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP5_8821C) & \
+ BIT_MASK_DTIM_COUNT_VAP5_8821C)
+#define BIT_SET_DTIM_COUNT_VAP5_8821C(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_VAP5_8821C(x) | BIT_DTIM_COUNT_VAP5_8821C(v))
/* 2 REG_DTIM_COUNTER_VAP6_8821C */
#define BIT_SHIFT_DTIM_COUNT_VAP6_8821C 0
#define BIT_MASK_DTIM_COUNT_VAP6_8821C 0xff
-#define BIT_DTIM_COUNT_VAP6_8821C(x) (((x) & BIT_MASK_DTIM_COUNT_VAP6_8821C) << BIT_SHIFT_DTIM_COUNT_VAP6_8821C)
-#define BIT_GET_DTIM_COUNT_VAP6_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP6_8821C) & BIT_MASK_DTIM_COUNT_VAP6_8821C)
-
+#define BIT_DTIM_COUNT_VAP6_8821C(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_VAP6_8821C) \
+ << BIT_SHIFT_DTIM_COUNT_VAP6_8821C)
+#define BITS_DTIM_COUNT_VAP6_8821C \
+ (BIT_MASK_DTIM_COUNT_VAP6_8821C << BIT_SHIFT_DTIM_COUNT_VAP6_8821C)
+#define BIT_CLEAR_DTIM_COUNT_VAP6_8821C(x) ((x) & (~BITS_DTIM_COUNT_VAP6_8821C))
+#define BIT_GET_DTIM_COUNT_VAP6_8821C(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP6_8821C) & \
+ BIT_MASK_DTIM_COUNT_VAP6_8821C)
+#define BIT_SET_DTIM_COUNT_VAP6_8821C(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_VAP6_8821C(x) | BIT_DTIM_COUNT_VAP6_8821C(v))
/* 2 REG_DTIM_COUNTER_VAP7_8821C */
#define BIT_SHIFT_DTIM_COUNT_VAP7_8821C 0
#define BIT_MASK_DTIM_COUNT_VAP7_8821C 0xff
-#define BIT_DTIM_COUNT_VAP7_8821C(x) (((x) & BIT_MASK_DTIM_COUNT_VAP7_8821C) << BIT_SHIFT_DTIM_COUNT_VAP7_8821C)
-#define BIT_GET_DTIM_COUNT_VAP7_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP7_8821C) & BIT_MASK_DTIM_COUNT_VAP7_8821C)
-
+#define BIT_DTIM_COUNT_VAP7_8821C(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_VAP7_8821C) \
+ << BIT_SHIFT_DTIM_COUNT_VAP7_8821C)
+#define BITS_DTIM_COUNT_VAP7_8821C \
+ (BIT_MASK_DTIM_COUNT_VAP7_8821C << BIT_SHIFT_DTIM_COUNT_VAP7_8821C)
+#define BIT_CLEAR_DTIM_COUNT_VAP7_8821C(x) ((x) & (~BITS_DTIM_COUNT_VAP7_8821C))
+#define BIT_GET_DTIM_COUNT_VAP7_8821C(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP7_8821C) & \
+ BIT_MASK_DTIM_COUNT_VAP7_8821C)
+#define BIT_SET_DTIM_COUNT_VAP7_8821C(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_VAP7_8821C(x) | BIT_DTIM_COUNT_VAP7_8821C(v))
/* 2 REG_DIS_ATIM_8821C */
#define BIT_DIS_ATIM_VAP7_8821C BIT(7)
@@ -7152,15 +13326,29 @@
#define BIT_SHIFT_TSFT_SEL_TIMER1_8821C 3
#define BIT_MASK_TSFT_SEL_TIMER1_8821C 0x7
-#define BIT_TSFT_SEL_TIMER1_8821C(x) (((x) & BIT_MASK_TSFT_SEL_TIMER1_8821C) << BIT_SHIFT_TSFT_SEL_TIMER1_8821C)
-#define BIT_GET_TSFT_SEL_TIMER1_8821C(x) (((x) >> BIT_SHIFT_TSFT_SEL_TIMER1_8821C) & BIT_MASK_TSFT_SEL_TIMER1_8821C)
-
+#define BIT_TSFT_SEL_TIMER1_8821C(x) \
+ (((x) & BIT_MASK_TSFT_SEL_TIMER1_8821C) \
+ << BIT_SHIFT_TSFT_SEL_TIMER1_8821C)
+#define BITS_TSFT_SEL_TIMER1_8821C \
+ (BIT_MASK_TSFT_SEL_TIMER1_8821C << BIT_SHIFT_TSFT_SEL_TIMER1_8821C)
+#define BIT_CLEAR_TSFT_SEL_TIMER1_8821C(x) ((x) & (~BITS_TSFT_SEL_TIMER1_8821C))
+#define BIT_GET_TSFT_SEL_TIMER1_8821C(x) \
+ (((x) >> BIT_SHIFT_TSFT_SEL_TIMER1_8821C) & \
+ BIT_MASK_TSFT_SEL_TIMER1_8821C)
+#define BIT_SET_TSFT_SEL_TIMER1_8821C(x, v) \
+ (BIT_CLEAR_TSFT_SEL_TIMER1_8821C(x) | BIT_TSFT_SEL_TIMER1_8821C(v))
#define BIT_SHIFT_EARLY_128US_8821C 0
#define BIT_MASK_EARLY_128US_8821C 0x7
-#define BIT_EARLY_128US_8821C(x) (((x) & BIT_MASK_EARLY_128US_8821C) << BIT_SHIFT_EARLY_128US_8821C)
-#define BIT_GET_EARLY_128US_8821C(x) (((x) >> BIT_SHIFT_EARLY_128US_8821C) & BIT_MASK_EARLY_128US_8821C)
-
+#define BIT_EARLY_128US_8821C(x) \
+ (((x) & BIT_MASK_EARLY_128US_8821C) << BIT_SHIFT_EARLY_128US_8821C)
+#define BITS_EARLY_128US_8821C \
+ (BIT_MASK_EARLY_128US_8821C << BIT_SHIFT_EARLY_128US_8821C)
+#define BIT_CLEAR_EARLY_128US_8821C(x) ((x) & (~BITS_EARLY_128US_8821C))
+#define BIT_GET_EARLY_128US_8821C(x) \
+ (((x) >> BIT_SHIFT_EARLY_128US_8821C) & BIT_MASK_EARLY_128US_8821C)
+#define BIT_SET_EARLY_128US_8821C(x, v) \
+ (BIT_CLEAR_EARLY_128US_8821C(x) | BIT_EARLY_128US_8821C(v))
/* 2 REG_P2PPS1_CTRL_8821C */
#define BIT_P2P1_CTW_ALLSTASLEEP_8821C BIT(7)
@@ -7180,71 +13368,145 @@
#define BIT_SHIFT_SYNC_CLI_SEL_8821C 4
#define BIT_MASK_SYNC_CLI_SEL_8821C 0x7
-#define BIT_SYNC_CLI_SEL_8821C(x) (((x) & BIT_MASK_SYNC_CLI_SEL_8821C) << BIT_SHIFT_SYNC_CLI_SEL_8821C)
-#define BIT_GET_SYNC_CLI_SEL_8821C(x) (((x) >> BIT_SHIFT_SYNC_CLI_SEL_8821C) & BIT_MASK_SYNC_CLI_SEL_8821C)
-
+#define BIT_SYNC_CLI_SEL_8821C(x) \
+ (((x) & BIT_MASK_SYNC_CLI_SEL_8821C) << BIT_SHIFT_SYNC_CLI_SEL_8821C)
+#define BITS_SYNC_CLI_SEL_8821C \
+ (BIT_MASK_SYNC_CLI_SEL_8821C << BIT_SHIFT_SYNC_CLI_SEL_8821C)
+#define BIT_CLEAR_SYNC_CLI_SEL_8821C(x) ((x) & (~BITS_SYNC_CLI_SEL_8821C))
+#define BIT_GET_SYNC_CLI_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_SYNC_CLI_SEL_8821C) & BIT_MASK_SYNC_CLI_SEL_8821C)
+#define BIT_SET_SYNC_CLI_SEL_8821C(x, v) \
+ (BIT_CLEAR_SYNC_CLI_SEL_8821C(x) | BIT_SYNC_CLI_SEL_8821C(v))
#define BIT_SHIFT_TSFT_SEL_TIMER0_8821C 0
#define BIT_MASK_TSFT_SEL_TIMER0_8821C 0x7
-#define BIT_TSFT_SEL_TIMER0_8821C(x) (((x) & BIT_MASK_TSFT_SEL_TIMER0_8821C) << BIT_SHIFT_TSFT_SEL_TIMER0_8821C)
-#define BIT_GET_TSFT_SEL_TIMER0_8821C(x) (((x) >> BIT_SHIFT_TSFT_SEL_TIMER0_8821C) & BIT_MASK_TSFT_SEL_TIMER0_8821C)
-
+#define BIT_TSFT_SEL_TIMER0_8821C(x) \
+ (((x) & BIT_MASK_TSFT_SEL_TIMER0_8821C) \
+ << BIT_SHIFT_TSFT_SEL_TIMER0_8821C)
+#define BITS_TSFT_SEL_TIMER0_8821C \
+ (BIT_MASK_TSFT_SEL_TIMER0_8821C << BIT_SHIFT_TSFT_SEL_TIMER0_8821C)
+#define BIT_CLEAR_TSFT_SEL_TIMER0_8821C(x) ((x) & (~BITS_TSFT_SEL_TIMER0_8821C))
+#define BIT_GET_TSFT_SEL_TIMER0_8821C(x) \
+ (((x) >> BIT_SHIFT_TSFT_SEL_TIMER0_8821C) & \
+ BIT_MASK_TSFT_SEL_TIMER0_8821C)
+#define BIT_SET_TSFT_SEL_TIMER0_8821C(x, v) \
+ (BIT_CLEAR_TSFT_SEL_TIMER0_8821C(x) | BIT_TSFT_SEL_TIMER0_8821C(v))
/* 2 REG_NOA_UNIT_SEL_8821C */
#define BIT_SHIFT_NOA_UNIT2_SEL_8821C 8
#define BIT_MASK_NOA_UNIT2_SEL_8821C 0x7
-#define BIT_NOA_UNIT2_SEL_8821C(x) (((x) & BIT_MASK_NOA_UNIT2_SEL_8821C) << BIT_SHIFT_NOA_UNIT2_SEL_8821C)
-#define BIT_GET_NOA_UNIT2_SEL_8821C(x) (((x) >> BIT_SHIFT_NOA_UNIT2_SEL_8821C) & BIT_MASK_NOA_UNIT2_SEL_8821C)
-
+#define BIT_NOA_UNIT2_SEL_8821C(x) \
+ (((x) & BIT_MASK_NOA_UNIT2_SEL_8821C) << BIT_SHIFT_NOA_UNIT2_SEL_8821C)
+#define BITS_NOA_UNIT2_SEL_8821C \
+ (BIT_MASK_NOA_UNIT2_SEL_8821C << BIT_SHIFT_NOA_UNIT2_SEL_8821C)
+#define BIT_CLEAR_NOA_UNIT2_SEL_8821C(x) ((x) & (~BITS_NOA_UNIT2_SEL_8821C))
+#define BIT_GET_NOA_UNIT2_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_NOA_UNIT2_SEL_8821C) & BIT_MASK_NOA_UNIT2_SEL_8821C)
+#define BIT_SET_NOA_UNIT2_SEL_8821C(x, v) \
+ (BIT_CLEAR_NOA_UNIT2_SEL_8821C(x) | BIT_NOA_UNIT2_SEL_8821C(v))
#define BIT_SHIFT_NOA_UNIT1_SEL_8821C 4
#define BIT_MASK_NOA_UNIT1_SEL_8821C 0x7
-#define BIT_NOA_UNIT1_SEL_8821C(x) (((x) & BIT_MASK_NOA_UNIT1_SEL_8821C) << BIT_SHIFT_NOA_UNIT1_SEL_8821C)
-#define BIT_GET_NOA_UNIT1_SEL_8821C(x) (((x) >> BIT_SHIFT_NOA_UNIT1_SEL_8821C) & BIT_MASK_NOA_UNIT1_SEL_8821C)
-
+#define BIT_NOA_UNIT1_SEL_8821C(x) \
+ (((x) & BIT_MASK_NOA_UNIT1_SEL_8821C) << BIT_SHIFT_NOA_UNIT1_SEL_8821C)
+#define BITS_NOA_UNIT1_SEL_8821C \
+ (BIT_MASK_NOA_UNIT1_SEL_8821C << BIT_SHIFT_NOA_UNIT1_SEL_8821C)
+#define BIT_CLEAR_NOA_UNIT1_SEL_8821C(x) ((x) & (~BITS_NOA_UNIT1_SEL_8821C))
+#define BIT_GET_NOA_UNIT1_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_NOA_UNIT1_SEL_8821C) & BIT_MASK_NOA_UNIT1_SEL_8821C)
+#define BIT_SET_NOA_UNIT1_SEL_8821C(x, v) \
+ (BIT_CLEAR_NOA_UNIT1_SEL_8821C(x) | BIT_NOA_UNIT1_SEL_8821C(v))
#define BIT_SHIFT_NOA_UNIT0_SEL_8821C 0
#define BIT_MASK_NOA_UNIT0_SEL_8821C 0x7
-#define BIT_NOA_UNIT0_SEL_8821C(x) (((x) & BIT_MASK_NOA_UNIT0_SEL_8821C) << BIT_SHIFT_NOA_UNIT0_SEL_8821C)
-#define BIT_GET_NOA_UNIT0_SEL_8821C(x) (((x) >> BIT_SHIFT_NOA_UNIT0_SEL_8821C) & BIT_MASK_NOA_UNIT0_SEL_8821C)
-
+#define BIT_NOA_UNIT0_SEL_8821C(x) \
+ (((x) & BIT_MASK_NOA_UNIT0_SEL_8821C) << BIT_SHIFT_NOA_UNIT0_SEL_8821C)
+#define BITS_NOA_UNIT0_SEL_8821C \
+ (BIT_MASK_NOA_UNIT0_SEL_8821C << BIT_SHIFT_NOA_UNIT0_SEL_8821C)
+#define BIT_CLEAR_NOA_UNIT0_SEL_8821C(x) ((x) & (~BITS_NOA_UNIT0_SEL_8821C))
+#define BIT_GET_NOA_UNIT0_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_NOA_UNIT0_SEL_8821C) & BIT_MASK_NOA_UNIT0_SEL_8821C)
+#define BIT_SET_NOA_UNIT0_SEL_8821C(x, v) \
+ (BIT_CLEAR_NOA_UNIT0_SEL_8821C(x) | BIT_NOA_UNIT0_SEL_8821C(v))
/* 2 REG_P2POFF_DIS_TXTIME_8821C */
#define BIT_SHIFT_P2POFF_DIS_TXTIME_8821C 0
#define BIT_MASK_P2POFF_DIS_TXTIME_8821C 0xff
-#define BIT_P2POFF_DIS_TXTIME_8821C(x) (((x) & BIT_MASK_P2POFF_DIS_TXTIME_8821C) << BIT_SHIFT_P2POFF_DIS_TXTIME_8821C)
-#define BIT_GET_P2POFF_DIS_TXTIME_8821C(x) (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8821C) & BIT_MASK_P2POFF_DIS_TXTIME_8821C)
-
+#define BIT_P2POFF_DIS_TXTIME_8821C(x) \
+ (((x) & BIT_MASK_P2POFF_DIS_TXTIME_8821C) \
+ << BIT_SHIFT_P2POFF_DIS_TXTIME_8821C)
+#define BITS_P2POFF_DIS_TXTIME_8821C \
+ (BIT_MASK_P2POFF_DIS_TXTIME_8821C << BIT_SHIFT_P2POFF_DIS_TXTIME_8821C)
+#define BIT_CLEAR_P2POFF_DIS_TXTIME_8821C(x) \
+ ((x) & (~BITS_P2POFF_DIS_TXTIME_8821C))
+#define BIT_GET_P2POFF_DIS_TXTIME_8821C(x) \
+ (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8821C) & \
+ BIT_MASK_P2POFF_DIS_TXTIME_8821C)
+#define BIT_SET_P2POFF_DIS_TXTIME_8821C(x, v) \
+ (BIT_CLEAR_P2POFF_DIS_TXTIME_8821C(x) | BIT_P2POFF_DIS_TXTIME_8821C(v))
/* 2 REG_MBSSID_BCN_SPACE2_8821C */
#define BIT_SHIFT_BCN_SPACE_CLINT2_8821C 16
#define BIT_MASK_BCN_SPACE_CLINT2_8821C 0xfff
-#define BIT_BCN_SPACE_CLINT2_8821C(x) (((x) & BIT_MASK_BCN_SPACE_CLINT2_8821C) << BIT_SHIFT_BCN_SPACE_CLINT2_8821C)
-#define BIT_GET_BCN_SPACE_CLINT2_8821C(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT2_8821C) & BIT_MASK_BCN_SPACE_CLINT2_8821C)
-
+#define BIT_BCN_SPACE_CLINT2_8821C(x) \
+ (((x) & BIT_MASK_BCN_SPACE_CLINT2_8821C) \
+ << BIT_SHIFT_BCN_SPACE_CLINT2_8821C)
+#define BITS_BCN_SPACE_CLINT2_8821C \
+ (BIT_MASK_BCN_SPACE_CLINT2_8821C << BIT_SHIFT_BCN_SPACE_CLINT2_8821C)
+#define BIT_CLEAR_BCN_SPACE_CLINT2_8821C(x) \
+ ((x) & (~BITS_BCN_SPACE_CLINT2_8821C))
+#define BIT_GET_BCN_SPACE_CLINT2_8821C(x) \
+ (((x) >> BIT_SHIFT_BCN_SPACE_CLINT2_8821C) & \
+ BIT_MASK_BCN_SPACE_CLINT2_8821C)
+#define BIT_SET_BCN_SPACE_CLINT2_8821C(x, v) \
+ (BIT_CLEAR_BCN_SPACE_CLINT2_8821C(x) | BIT_BCN_SPACE_CLINT2_8821C(v))
#define BIT_SHIFT_BCN_SPACE_CLINT1_8821C 0
#define BIT_MASK_BCN_SPACE_CLINT1_8821C 0xfff
-#define BIT_BCN_SPACE_CLINT1_8821C(x) (((x) & BIT_MASK_BCN_SPACE_CLINT1_8821C) << BIT_SHIFT_BCN_SPACE_CLINT1_8821C)
-#define BIT_GET_BCN_SPACE_CLINT1_8821C(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT1_8821C) & BIT_MASK_BCN_SPACE_CLINT1_8821C)
-
+#define BIT_BCN_SPACE_CLINT1_8821C(x) \
+ (((x) & BIT_MASK_BCN_SPACE_CLINT1_8821C) \
+ << BIT_SHIFT_BCN_SPACE_CLINT1_8821C)
+#define BITS_BCN_SPACE_CLINT1_8821C \
+ (BIT_MASK_BCN_SPACE_CLINT1_8821C << BIT_SHIFT_BCN_SPACE_CLINT1_8821C)
+#define BIT_CLEAR_BCN_SPACE_CLINT1_8821C(x) \
+ ((x) & (~BITS_BCN_SPACE_CLINT1_8821C))
+#define BIT_GET_BCN_SPACE_CLINT1_8821C(x) \
+ (((x) >> BIT_SHIFT_BCN_SPACE_CLINT1_8821C) & \
+ BIT_MASK_BCN_SPACE_CLINT1_8821C)
+#define BIT_SET_BCN_SPACE_CLINT1_8821C(x, v) \
+ (BIT_CLEAR_BCN_SPACE_CLINT1_8821C(x) | BIT_BCN_SPACE_CLINT1_8821C(v))
/* 2 REG_MBSSID_BCN_SPACE3_8821C */
#define BIT_SHIFT_SUB_BCN_SPACE_8821C 16
#define BIT_MASK_SUB_BCN_SPACE_8821C 0xff
-#define BIT_SUB_BCN_SPACE_8821C(x) (((x) & BIT_MASK_SUB_BCN_SPACE_8821C) << BIT_SHIFT_SUB_BCN_SPACE_8821C)
-#define BIT_GET_SUB_BCN_SPACE_8821C(x) (((x) >> BIT_SHIFT_SUB_BCN_SPACE_8821C) & BIT_MASK_SUB_BCN_SPACE_8821C)
-
+#define BIT_SUB_BCN_SPACE_8821C(x) \
+ (((x) & BIT_MASK_SUB_BCN_SPACE_8821C) << BIT_SHIFT_SUB_BCN_SPACE_8821C)
+#define BITS_SUB_BCN_SPACE_8821C \
+ (BIT_MASK_SUB_BCN_SPACE_8821C << BIT_SHIFT_SUB_BCN_SPACE_8821C)
+#define BIT_CLEAR_SUB_BCN_SPACE_8821C(x) ((x) & (~BITS_SUB_BCN_SPACE_8821C))
+#define BIT_GET_SUB_BCN_SPACE_8821C(x) \
+ (((x) >> BIT_SHIFT_SUB_BCN_SPACE_8821C) & BIT_MASK_SUB_BCN_SPACE_8821C)
+#define BIT_SET_SUB_BCN_SPACE_8821C(x, v) \
+ (BIT_CLEAR_SUB_BCN_SPACE_8821C(x) | BIT_SUB_BCN_SPACE_8821C(v))
#define BIT_SHIFT_BCN_SPACE_CLINT3_8821C 0
#define BIT_MASK_BCN_SPACE_CLINT3_8821C 0xfff
-#define BIT_BCN_SPACE_CLINT3_8821C(x) (((x) & BIT_MASK_BCN_SPACE_CLINT3_8821C) << BIT_SHIFT_BCN_SPACE_CLINT3_8821C)
-#define BIT_GET_BCN_SPACE_CLINT3_8821C(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT3_8821C) & BIT_MASK_BCN_SPACE_CLINT3_8821C)
-
+#define BIT_BCN_SPACE_CLINT3_8821C(x) \
+ (((x) & BIT_MASK_BCN_SPACE_CLINT3_8821C) \
+ << BIT_SHIFT_BCN_SPACE_CLINT3_8821C)
+#define BITS_BCN_SPACE_CLINT3_8821C \
+ (BIT_MASK_BCN_SPACE_CLINT3_8821C << BIT_SHIFT_BCN_SPACE_CLINT3_8821C)
+#define BIT_CLEAR_BCN_SPACE_CLINT3_8821C(x) \
+ ((x) & (~BITS_BCN_SPACE_CLINT3_8821C))
+#define BIT_GET_BCN_SPACE_CLINT3_8821C(x) \
+ (((x) >> BIT_SHIFT_BCN_SPACE_CLINT3_8821C) & \
+ BIT_MASK_BCN_SPACE_CLINT3_8821C)
+#define BIT_SET_BCN_SPACE_CLINT3_8821C(x, v) \
+ (BIT_CLEAR_BCN_SPACE_CLINT3_8821C(x) | BIT_BCN_SPACE_CLINT3_8821C(v))
/* 2 REG_ACMHWCTRL_8821C */
#define BIT_BEQ_ACM_STATUS_8821C BIT(7)
@@ -7264,83 +13526,181 @@
#define BIT_SHIFT_AVGPERIOD_8821C 0
#define BIT_MASK_AVGPERIOD_8821C 0xffff
-#define BIT_AVGPERIOD_8821C(x) (((x) & BIT_MASK_AVGPERIOD_8821C) << BIT_SHIFT_AVGPERIOD_8821C)
-#define BIT_GET_AVGPERIOD_8821C(x) (((x) >> BIT_SHIFT_AVGPERIOD_8821C) & BIT_MASK_AVGPERIOD_8821C)
-
+#define BIT_AVGPERIOD_8821C(x) \
+ (((x) & BIT_MASK_AVGPERIOD_8821C) << BIT_SHIFT_AVGPERIOD_8821C)
+#define BITS_AVGPERIOD_8821C \
+ (BIT_MASK_AVGPERIOD_8821C << BIT_SHIFT_AVGPERIOD_8821C)
+#define BIT_CLEAR_AVGPERIOD_8821C(x) ((x) & (~BITS_AVGPERIOD_8821C))
+#define BIT_GET_AVGPERIOD_8821C(x) \
+ (((x) >> BIT_SHIFT_AVGPERIOD_8821C) & BIT_MASK_AVGPERIOD_8821C)
+#define BIT_SET_AVGPERIOD_8821C(x, v) \
+ (BIT_CLEAR_AVGPERIOD_8821C(x) | BIT_AVGPERIOD_8821C(v))
/* 2 REG_VO_ADMTIME_8821C */
#define BIT_SHIFT_VO_ADMITTED_TIME_8821C 0
#define BIT_MASK_VO_ADMITTED_TIME_8821C 0xffff
-#define BIT_VO_ADMITTED_TIME_8821C(x) (((x) & BIT_MASK_VO_ADMITTED_TIME_8821C) << BIT_SHIFT_VO_ADMITTED_TIME_8821C)
-#define BIT_GET_VO_ADMITTED_TIME_8821C(x) (((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8821C) & BIT_MASK_VO_ADMITTED_TIME_8821C)
-
+#define BIT_VO_ADMITTED_TIME_8821C(x) \
+ (((x) & BIT_MASK_VO_ADMITTED_TIME_8821C) \
+ << BIT_SHIFT_VO_ADMITTED_TIME_8821C)
+#define BITS_VO_ADMITTED_TIME_8821C \
+ (BIT_MASK_VO_ADMITTED_TIME_8821C << BIT_SHIFT_VO_ADMITTED_TIME_8821C)
+#define BIT_CLEAR_VO_ADMITTED_TIME_8821C(x) \
+ ((x) & (~BITS_VO_ADMITTED_TIME_8821C))
+#define BIT_GET_VO_ADMITTED_TIME_8821C(x) \
+ (((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8821C) & \
+ BIT_MASK_VO_ADMITTED_TIME_8821C)
+#define BIT_SET_VO_ADMITTED_TIME_8821C(x, v) \
+ (BIT_CLEAR_VO_ADMITTED_TIME_8821C(x) | BIT_VO_ADMITTED_TIME_8821C(v))
/* 2 REG_VI_ADMTIME_8821C */
#define BIT_SHIFT_VI_ADMITTED_TIME_8821C 0
#define BIT_MASK_VI_ADMITTED_TIME_8821C 0xffff
-#define BIT_VI_ADMITTED_TIME_8821C(x) (((x) & BIT_MASK_VI_ADMITTED_TIME_8821C) << BIT_SHIFT_VI_ADMITTED_TIME_8821C)
-#define BIT_GET_VI_ADMITTED_TIME_8821C(x) (((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8821C) & BIT_MASK_VI_ADMITTED_TIME_8821C)
-
+#define BIT_VI_ADMITTED_TIME_8821C(x) \
+ (((x) & BIT_MASK_VI_ADMITTED_TIME_8821C) \
+ << BIT_SHIFT_VI_ADMITTED_TIME_8821C)
+#define BITS_VI_ADMITTED_TIME_8821C \
+ (BIT_MASK_VI_ADMITTED_TIME_8821C << BIT_SHIFT_VI_ADMITTED_TIME_8821C)
+#define BIT_CLEAR_VI_ADMITTED_TIME_8821C(x) \
+ ((x) & (~BITS_VI_ADMITTED_TIME_8821C))
+#define BIT_GET_VI_ADMITTED_TIME_8821C(x) \
+ (((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8821C) & \
+ BIT_MASK_VI_ADMITTED_TIME_8821C)
+#define BIT_SET_VI_ADMITTED_TIME_8821C(x, v) \
+ (BIT_CLEAR_VI_ADMITTED_TIME_8821C(x) | BIT_VI_ADMITTED_TIME_8821C(v))
/* 2 REG_BE_ADMTIME_8821C */
#define BIT_SHIFT_BE_ADMITTED_TIME_8821C 0
#define BIT_MASK_BE_ADMITTED_TIME_8821C 0xffff
-#define BIT_BE_ADMITTED_TIME_8821C(x) (((x) & BIT_MASK_BE_ADMITTED_TIME_8821C) << BIT_SHIFT_BE_ADMITTED_TIME_8821C)
-#define BIT_GET_BE_ADMITTED_TIME_8821C(x) (((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8821C) & BIT_MASK_BE_ADMITTED_TIME_8821C)
+#define BIT_BE_ADMITTED_TIME_8821C(x) \
+ (((x) & BIT_MASK_BE_ADMITTED_TIME_8821C) \
+ << BIT_SHIFT_BE_ADMITTED_TIME_8821C)
+#define BITS_BE_ADMITTED_TIME_8821C \
+ (BIT_MASK_BE_ADMITTED_TIME_8821C << BIT_SHIFT_BE_ADMITTED_TIME_8821C)
+#define BIT_CLEAR_BE_ADMITTED_TIME_8821C(x) \
+ ((x) & (~BITS_BE_ADMITTED_TIME_8821C))
+#define BIT_GET_BE_ADMITTED_TIME_8821C(x) \
+ (((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8821C) & \
+ BIT_MASK_BE_ADMITTED_TIME_8821C)
+#define BIT_SET_BE_ADMITTED_TIME_8821C(x, v) \
+ (BIT_CLEAR_BE_ADMITTED_TIME_8821C(x) | BIT_BE_ADMITTED_TIME_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+/* 2 REG_NOT_VALID_8821C */
/* 2 REG_EDCA_RANDOM_GEN_8821C */
#define BIT_SHIFT_RANDOM_GEN_8821C 0
#define BIT_MASK_RANDOM_GEN_8821C 0xffffff
-#define BIT_RANDOM_GEN_8821C(x) (((x) & BIT_MASK_RANDOM_GEN_8821C) << BIT_SHIFT_RANDOM_GEN_8821C)
-#define BIT_GET_RANDOM_GEN_8821C(x) (((x) >> BIT_SHIFT_RANDOM_GEN_8821C) & BIT_MASK_RANDOM_GEN_8821C)
-
+#define BIT_RANDOM_GEN_8821C(x) \
+ (((x) & BIT_MASK_RANDOM_GEN_8821C) << BIT_SHIFT_RANDOM_GEN_8821C)
+#define BITS_RANDOM_GEN_8821C \
+ (BIT_MASK_RANDOM_GEN_8821C << BIT_SHIFT_RANDOM_GEN_8821C)
+#define BIT_CLEAR_RANDOM_GEN_8821C(x) ((x) & (~BITS_RANDOM_GEN_8821C))
+#define BIT_GET_RANDOM_GEN_8821C(x) \
+ (((x) >> BIT_SHIFT_RANDOM_GEN_8821C) & BIT_MASK_RANDOM_GEN_8821C)
+#define BIT_SET_RANDOM_GEN_8821C(x, v) \
+ (BIT_CLEAR_RANDOM_GEN_8821C(x) | BIT_RANDOM_GEN_8821C(v))
/* 2 REG_TXCMD_NOA_SEL_8821C */
-#define BIT_SHIFT_NOA_SEL_8821C 4
-#define BIT_MASK_NOA_SEL_8821C 0x7
-#define BIT_NOA_SEL_8821C(x) (((x) & BIT_MASK_NOA_SEL_8821C) << BIT_SHIFT_NOA_SEL_8821C)
-#define BIT_GET_NOA_SEL_8821C(x) (((x) >> BIT_SHIFT_NOA_SEL_8821C) & BIT_MASK_NOA_SEL_8821C)
-
+#define BIT_SHIFT_NOA_SEL_V2_8821C 4
+#define BIT_MASK_NOA_SEL_V2_8821C 0x7
+#define BIT_NOA_SEL_V2_8821C(x) \
+ (((x) & BIT_MASK_NOA_SEL_V2_8821C) << BIT_SHIFT_NOA_SEL_V2_8821C)
+#define BITS_NOA_SEL_V2_8821C \
+ (BIT_MASK_NOA_SEL_V2_8821C << BIT_SHIFT_NOA_SEL_V2_8821C)
+#define BIT_CLEAR_NOA_SEL_V2_8821C(x) ((x) & (~BITS_NOA_SEL_V2_8821C))
+#define BIT_GET_NOA_SEL_V2_8821C(x) \
+ (((x) >> BIT_SHIFT_NOA_SEL_V2_8821C) & BIT_MASK_NOA_SEL_V2_8821C)
+#define BIT_SET_NOA_SEL_V2_8821C(x, v) \
+ (BIT_CLEAR_NOA_SEL_V2_8821C(x) | BIT_NOA_SEL_V2_8821C(v))
#define BIT_SHIFT_TXCMD_SEG_SEL_8821C 0
#define BIT_MASK_TXCMD_SEG_SEL_8821C 0xf
-#define BIT_TXCMD_SEG_SEL_8821C(x) (((x) & BIT_MASK_TXCMD_SEG_SEL_8821C) << BIT_SHIFT_TXCMD_SEG_SEL_8821C)
-#define BIT_GET_TXCMD_SEG_SEL_8821C(x) (((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8821C) & BIT_MASK_TXCMD_SEG_SEL_8821C)
-
-
-/* 2 REG_NOA_PARAM_8821C */
-
-#define BIT_SHIFT_NOA_COUNT_8821C (96 & CPU_OPT_WIDTH)
-#define BIT_MASK_NOA_COUNT_8821C 0xff
-#define BIT_NOA_COUNT_8821C(x) (((x) & BIT_MASK_NOA_COUNT_8821C) << BIT_SHIFT_NOA_COUNT_8821C)
-#define BIT_GET_NOA_COUNT_8821C(x) (((x) >> BIT_SHIFT_NOA_COUNT_8821C) & BIT_MASK_NOA_COUNT_8821C)
-
-
-#define BIT_SHIFT_NOA_START_TIME_8821C (64 & CPU_OPT_WIDTH)
-#define BIT_MASK_NOA_START_TIME_8821C 0xffffffffL
-#define BIT_NOA_START_TIME_8821C(x) (((x) & BIT_MASK_NOA_START_TIME_8821C) << BIT_SHIFT_NOA_START_TIME_8821C)
-#define BIT_GET_NOA_START_TIME_8821C(x) (((x) >> BIT_SHIFT_NOA_START_TIME_8821C) & BIT_MASK_NOA_START_TIME_8821C)
+#define BIT_TXCMD_SEG_SEL_8821C(x) \
+ (((x) & BIT_MASK_TXCMD_SEG_SEL_8821C) << BIT_SHIFT_TXCMD_SEG_SEL_8821C)
+#define BITS_TXCMD_SEG_SEL_8821C \
+ (BIT_MASK_TXCMD_SEG_SEL_8821C << BIT_SHIFT_TXCMD_SEG_SEL_8821C)
+#define BIT_CLEAR_TXCMD_SEG_SEL_8821C(x) ((x) & (~BITS_TXCMD_SEG_SEL_8821C))
+#define BIT_GET_TXCMD_SEG_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8821C) & BIT_MASK_TXCMD_SEG_SEL_8821C)
+#define BIT_SET_TXCMD_SEG_SEL_8821C(x, v) \
+ (BIT_CLEAR_TXCMD_SEG_SEL_8821C(x) | BIT_TXCMD_SEG_SEL_8821C(v))
+/* 2 REG_NOT_VALID_8821C */
-#define BIT_SHIFT_NOA_INTERVAL_8821C (32 & CPU_OPT_WIDTH)
-#define BIT_MASK_NOA_INTERVAL_8821C 0xffffffffL
-#define BIT_NOA_INTERVAL_8821C(x) (((x) & BIT_MASK_NOA_INTERVAL_8821C) << BIT_SHIFT_NOA_INTERVAL_8821C)
-#define BIT_GET_NOA_INTERVAL_8821C(x) (((x) >> BIT_SHIFT_NOA_INTERVAL_8821C) & BIT_MASK_NOA_INTERVAL_8821C)
+/* 2 REG_NOT_VALID_8821C */
+/* 2 REG_NOT_VALID_8821C */
-#define BIT_SHIFT_NOA_DURATION_8821C 0
-#define BIT_MASK_NOA_DURATION_8821C 0xffffffffL
-#define BIT_NOA_DURATION_8821C(x) (((x) & BIT_MASK_NOA_DURATION_8821C) << BIT_SHIFT_NOA_DURATION_8821C)
-#define BIT_GET_NOA_DURATION_8821C(x) (((x) >> BIT_SHIFT_NOA_DURATION_8821C) & BIT_MASK_NOA_DURATION_8821C)
+/* 2 REG_NOT_VALID_8821C */
+/* 2 REG_NOA_PARAM_8821C */
-/* 2 REG_NOT_VALID_8821C */
+#define BIT_SHIFT_NOA_DURATION_V1_8821C 0
+#define BIT_MASK_NOA_DURATION_V1_8821C 0xffffffffL
+#define BIT_NOA_DURATION_V1_8821C(x) \
+ (((x) & BIT_MASK_NOA_DURATION_V1_8821C) \
+ << BIT_SHIFT_NOA_DURATION_V1_8821C)
+#define BITS_NOA_DURATION_V1_8821C \
+ (BIT_MASK_NOA_DURATION_V1_8821C << BIT_SHIFT_NOA_DURATION_V1_8821C)
+#define BIT_CLEAR_NOA_DURATION_V1_8821C(x) ((x) & (~BITS_NOA_DURATION_V1_8821C))
+#define BIT_GET_NOA_DURATION_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_NOA_DURATION_V1_8821C) & \
+ BIT_MASK_NOA_DURATION_V1_8821C)
+#define BIT_SET_NOA_DURATION_V1_8821C(x, v) \
+ (BIT_CLEAR_NOA_DURATION_V1_8821C(x) | BIT_NOA_DURATION_V1_8821C(v))
+
+/* 2 REG_NOA_PARAM_1_8821C */
+
+#define BIT_SHIFT_NOA_INTERVAL_V1_8821C 0
+#define BIT_MASK_NOA_INTERVAL_V1_8821C 0xffffffffL
+#define BIT_NOA_INTERVAL_V1_8821C(x) \
+ (((x) & BIT_MASK_NOA_INTERVAL_V1_8821C) \
+ << BIT_SHIFT_NOA_INTERVAL_V1_8821C)
+#define BITS_NOA_INTERVAL_V1_8821C \
+ (BIT_MASK_NOA_INTERVAL_V1_8821C << BIT_SHIFT_NOA_INTERVAL_V1_8821C)
+#define BIT_CLEAR_NOA_INTERVAL_V1_8821C(x) ((x) & (~BITS_NOA_INTERVAL_V1_8821C))
+#define BIT_GET_NOA_INTERVAL_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_NOA_INTERVAL_V1_8821C) & \
+ BIT_MASK_NOA_INTERVAL_V1_8821C)
+#define BIT_SET_NOA_INTERVAL_V1_8821C(x, v) \
+ (BIT_CLEAR_NOA_INTERVAL_V1_8821C(x) | BIT_NOA_INTERVAL_V1_8821C(v))
+
+/* 2 REG_NOA_PARAM_2_8821C */
+
+#define BIT_SHIFT_NOA_START_TIME_V1_8821C 0
+#define BIT_MASK_NOA_START_TIME_V1_8821C 0xffffffffL
+#define BIT_NOA_START_TIME_V1_8821C(x) \
+ (((x) & BIT_MASK_NOA_START_TIME_V1_8821C) \
+ << BIT_SHIFT_NOA_START_TIME_V1_8821C)
+#define BITS_NOA_START_TIME_V1_8821C \
+ (BIT_MASK_NOA_START_TIME_V1_8821C << BIT_SHIFT_NOA_START_TIME_V1_8821C)
+#define BIT_CLEAR_NOA_START_TIME_V1_8821C(x) \
+ ((x) & (~BITS_NOA_START_TIME_V1_8821C))
+#define BIT_GET_NOA_START_TIME_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_NOA_START_TIME_V1_8821C) & \
+ BIT_MASK_NOA_START_TIME_V1_8821C)
+#define BIT_SET_NOA_START_TIME_V1_8821C(x, v) \
+ (BIT_CLEAR_NOA_START_TIME_V1_8821C(x) | BIT_NOA_START_TIME_V1_8821C(v))
+
+/* 2 REG_NOA_PARAM_3_8821C */
+
+#define BIT_SHIFT_NOA_COUNT_V1_8821C 0
+#define BIT_MASK_NOA_COUNT_V1_8821C 0xffffffffL
+#define BIT_NOA_COUNT_V1_8821C(x) \
+ (((x) & BIT_MASK_NOA_COUNT_V1_8821C) << BIT_SHIFT_NOA_COUNT_V1_8821C)
+#define BITS_NOA_COUNT_V1_8821C \
+ (BIT_MASK_NOA_COUNT_V1_8821C << BIT_SHIFT_NOA_COUNT_V1_8821C)
+#define BIT_CLEAR_NOA_COUNT_V1_8821C(x) ((x) & (~BITS_NOA_COUNT_V1_8821C))
+#define BIT_GET_NOA_COUNT_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_NOA_COUNT_V1_8821C) & BIT_MASK_NOA_COUNT_V1_8821C)
+#define BIT_SET_NOA_COUNT_V1_8821C(x, v) \
+ (BIT_CLEAR_NOA_COUNT_V1_8821C(x) | BIT_NOA_COUNT_V1_8821C(v))
/* 2 REG_P2P_RST_8821C */
#define BIT_P2P2_PWR_RST1_8821C BIT(5)
@@ -7351,50 +13711,93 @@
#define BIT_P2P_PWR_RST0_V1_8821C BIT(0)
/* 2 REG_SCHEDULER_RST_8821C */
-#define BIT_SYNC_CLI_8821C BIT(1)
+#define BIT_SYNC_CLI_ONCE_RIGHT_NOW_8821C BIT(2)
+#define BIT_SYNC_CLI_ONCE_BY_TBTT_8821C BIT(1)
#define BIT_SCHEDULER_RST_V1_8821C BIT(0)
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
/* 2 REG_SCH_TXCMD_8821C */
#define BIT_SHIFT_SCH_TXCMD_8821C 0
#define BIT_MASK_SCH_TXCMD_8821C 0xffffffffL
-#define BIT_SCH_TXCMD_8821C(x) (((x) & BIT_MASK_SCH_TXCMD_8821C) << BIT_SHIFT_SCH_TXCMD_8821C)
-#define BIT_GET_SCH_TXCMD_8821C(x) (((x) >> BIT_SHIFT_SCH_TXCMD_8821C) & BIT_MASK_SCH_TXCMD_8821C)
-
+#define BIT_SCH_TXCMD_8821C(x) \
+ (((x) & BIT_MASK_SCH_TXCMD_8821C) << BIT_SHIFT_SCH_TXCMD_8821C)
+#define BITS_SCH_TXCMD_8821C \
+ (BIT_MASK_SCH_TXCMD_8821C << BIT_SHIFT_SCH_TXCMD_8821C)
+#define BIT_CLEAR_SCH_TXCMD_8821C(x) ((x) & (~BITS_SCH_TXCMD_8821C))
+#define BIT_GET_SCH_TXCMD_8821C(x) \
+ (((x) >> BIT_SHIFT_SCH_TXCMD_8821C) & BIT_MASK_SCH_TXCMD_8821C)
+#define BIT_SET_SCH_TXCMD_8821C(x, v) \
+ (BIT_CLEAR_SCH_TXCMD_8821C(x) | BIT_SCH_TXCMD_8821C(v))
/* 2 REG_PAGE5_DUMMY_8821C */
+#define BIT_ECO_TXOP_BREAK_FORCE_CFEND_8821C BIT(0)
/* 2 REG_CPUMGQ_TX_TIMER_8821C */
#define BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8821C 0
#define BIT_MASK_CPUMGQ_TX_TIMER_V1_8821C 0xffffffffL
-#define BIT_CPUMGQ_TX_TIMER_V1_8821C(x) (((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8821C) << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8821C)
-#define BIT_GET_CPUMGQ_TX_TIMER_V1_8821C(x) (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8821C) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8821C)
-
+#define BIT_CPUMGQ_TX_TIMER_V1_8821C(x) \
+ (((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8821C) \
+ << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8821C)
+#define BITS_CPUMGQ_TX_TIMER_V1_8821C \
+ (BIT_MASK_CPUMGQ_TX_TIMER_V1_8821C \
+ << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8821C)
+#define BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8821C(x) \
+ ((x) & (~BITS_CPUMGQ_TX_TIMER_V1_8821C))
+#define BIT_GET_CPUMGQ_TX_TIMER_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8821C) & \
+ BIT_MASK_CPUMGQ_TX_TIMER_V1_8821C)
+#define BIT_SET_CPUMGQ_TX_TIMER_V1_8821C(x, v) \
+ (BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8821C(x) | \
+ BIT_CPUMGQ_TX_TIMER_V1_8821C(v))
/* 2 REG_PS_TIMER_A_8821C */
#define BIT_SHIFT_PS_TIMER_A_V1_8821C 0
#define BIT_MASK_PS_TIMER_A_V1_8821C 0xffffffffL
-#define BIT_PS_TIMER_A_V1_8821C(x) (((x) & BIT_MASK_PS_TIMER_A_V1_8821C) << BIT_SHIFT_PS_TIMER_A_V1_8821C)
-#define BIT_GET_PS_TIMER_A_V1_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_A_V1_8821C) & BIT_MASK_PS_TIMER_A_V1_8821C)
-
+#define BIT_PS_TIMER_A_V1_8821C(x) \
+ (((x) & BIT_MASK_PS_TIMER_A_V1_8821C) << BIT_SHIFT_PS_TIMER_A_V1_8821C)
+#define BITS_PS_TIMER_A_V1_8821C \
+ (BIT_MASK_PS_TIMER_A_V1_8821C << BIT_SHIFT_PS_TIMER_A_V1_8821C)
+#define BIT_CLEAR_PS_TIMER_A_V1_8821C(x) ((x) & (~BITS_PS_TIMER_A_V1_8821C))
+#define BIT_GET_PS_TIMER_A_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_A_V1_8821C) & BIT_MASK_PS_TIMER_A_V1_8821C)
+#define BIT_SET_PS_TIMER_A_V1_8821C(x, v) \
+ (BIT_CLEAR_PS_TIMER_A_V1_8821C(x) | BIT_PS_TIMER_A_V1_8821C(v))
/* 2 REG_PS_TIMER_B_8821C */
#define BIT_SHIFT_PS_TIMER_B_V1_8821C 0
#define BIT_MASK_PS_TIMER_B_V1_8821C 0xffffffffL
-#define BIT_PS_TIMER_B_V1_8821C(x) (((x) & BIT_MASK_PS_TIMER_B_V1_8821C) << BIT_SHIFT_PS_TIMER_B_V1_8821C)
-#define BIT_GET_PS_TIMER_B_V1_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_B_V1_8821C) & BIT_MASK_PS_TIMER_B_V1_8821C)
-
+#define BIT_PS_TIMER_B_V1_8821C(x) \
+ (((x) & BIT_MASK_PS_TIMER_B_V1_8821C) << BIT_SHIFT_PS_TIMER_B_V1_8821C)
+#define BITS_PS_TIMER_B_V1_8821C \
+ (BIT_MASK_PS_TIMER_B_V1_8821C << BIT_SHIFT_PS_TIMER_B_V1_8821C)
+#define BIT_CLEAR_PS_TIMER_B_V1_8821C(x) ((x) & (~BITS_PS_TIMER_B_V1_8821C))
+#define BIT_GET_PS_TIMER_B_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_B_V1_8821C) & BIT_MASK_PS_TIMER_B_V1_8821C)
+#define BIT_SET_PS_TIMER_B_V1_8821C(x, v) \
+ (BIT_CLEAR_PS_TIMER_B_V1_8821C(x) | BIT_PS_TIMER_B_V1_8821C(v))
/* 2 REG_PS_TIMER_C_8821C */
#define BIT_SHIFT_PS_TIMER_C_V1_8821C 0
#define BIT_MASK_PS_TIMER_C_V1_8821C 0xffffffffL
-#define BIT_PS_TIMER_C_V1_8821C(x) (((x) & BIT_MASK_PS_TIMER_C_V1_8821C) << BIT_SHIFT_PS_TIMER_C_V1_8821C)
-#define BIT_GET_PS_TIMER_C_V1_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_C_V1_8821C) & BIT_MASK_PS_TIMER_C_V1_8821C)
-
+#define BIT_PS_TIMER_C_V1_8821C(x) \
+ (((x) & BIT_MASK_PS_TIMER_C_V1_8821C) << BIT_SHIFT_PS_TIMER_C_V1_8821C)
+#define BITS_PS_TIMER_C_V1_8821C \
+ (BIT_MASK_PS_TIMER_C_V1_8821C << BIT_SHIFT_PS_TIMER_C_V1_8821C)
+#define BIT_CLEAR_PS_TIMER_C_V1_8821C(x) ((x) & (~BITS_PS_TIMER_C_V1_8821C))
+#define BIT_GET_PS_TIMER_C_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_C_V1_8821C) & BIT_MASK_PS_TIMER_C_V1_8821C)
+#define BIT_SET_PS_TIMER_C_V1_8821C(x, v) \
+ (BIT_CLEAR_PS_TIMER_C_V1_8821C(x) | BIT_PS_TIMER_C_V1_8821C(v))
/* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8821C */
#define BIT_CPUMGQ_TIMER_EN_8821C BIT(31)
@@ -7402,86 +13805,316 @@
#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8821C 24
#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8821C 0x7
-#define BIT_CPUMGQ_TIMER_TSF_SEL_8821C(x) (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8821C) << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8821C)
-#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_8821C(x) (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8821C) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8821C)
+#define BIT_CPUMGQ_TIMER_TSF_SEL_8821C(x) \
+ (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8821C) \
+ << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8821C)
+#define BITS_CPUMGQ_TIMER_TSF_SEL_8821C \
+ (BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8821C \
+ << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8821C)
+#define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8821C(x) \
+ ((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL_8821C))
+#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8821C) & \
+ BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8821C)
+#define BIT_SET_CPUMGQ_TIMER_TSF_SEL_8821C(x, v) \
+ (BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8821C(x) | \
+ BIT_CPUMGQ_TIMER_TSF_SEL_8821C(v))
#define BIT_PS_TIMER_C_EN_8821C BIT(23)
#define BIT_SHIFT_PS_TIMER_C_TSF_SEL_8821C 16
#define BIT_MASK_PS_TIMER_C_TSF_SEL_8821C 0x7
-#define BIT_PS_TIMER_C_TSF_SEL_8821C(x) (((x) & BIT_MASK_PS_TIMER_C_TSF_SEL_8821C) << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8821C)
-#define BIT_GET_PS_TIMER_C_TSF_SEL_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL_8821C) & BIT_MASK_PS_TIMER_C_TSF_SEL_8821C)
+#define BIT_PS_TIMER_C_TSF_SEL_8821C(x) \
+ (((x) & BIT_MASK_PS_TIMER_C_TSF_SEL_8821C) \
+ << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8821C)
+#define BITS_PS_TIMER_C_TSF_SEL_8821C \
+ (BIT_MASK_PS_TIMER_C_TSF_SEL_8821C \
+ << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8821C)
+#define BIT_CLEAR_PS_TIMER_C_TSF_SEL_8821C(x) \
+ ((x) & (~BITS_PS_TIMER_C_TSF_SEL_8821C))
+#define BIT_GET_PS_TIMER_C_TSF_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL_8821C) & \
+ BIT_MASK_PS_TIMER_C_TSF_SEL_8821C)
+#define BIT_SET_PS_TIMER_C_TSF_SEL_8821C(x, v) \
+ (BIT_CLEAR_PS_TIMER_C_TSF_SEL_8821C(x) | \
+ BIT_PS_TIMER_C_TSF_SEL_8821C(v))
#define BIT_PS_TIMER_B_EN_8821C BIT(15)
#define BIT_SHIFT_PS_TIMER_B_TSF_SEL_8821C 8
#define BIT_MASK_PS_TIMER_B_TSF_SEL_8821C 0x7
-#define BIT_PS_TIMER_B_TSF_SEL_8821C(x) (((x) & BIT_MASK_PS_TIMER_B_TSF_SEL_8821C) << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8821C)
-#define BIT_GET_PS_TIMER_B_TSF_SEL_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL_8821C) & BIT_MASK_PS_TIMER_B_TSF_SEL_8821C)
+#define BIT_PS_TIMER_B_TSF_SEL_8821C(x) \
+ (((x) & BIT_MASK_PS_TIMER_B_TSF_SEL_8821C) \
+ << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8821C)
+#define BITS_PS_TIMER_B_TSF_SEL_8821C \
+ (BIT_MASK_PS_TIMER_B_TSF_SEL_8821C \
+ << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8821C)
+#define BIT_CLEAR_PS_TIMER_B_TSF_SEL_8821C(x) \
+ ((x) & (~BITS_PS_TIMER_B_TSF_SEL_8821C))
+#define BIT_GET_PS_TIMER_B_TSF_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL_8821C) & \
+ BIT_MASK_PS_TIMER_B_TSF_SEL_8821C)
+#define BIT_SET_PS_TIMER_B_TSF_SEL_8821C(x, v) \
+ (BIT_CLEAR_PS_TIMER_B_TSF_SEL_8821C(x) | \
+ BIT_PS_TIMER_B_TSF_SEL_8821C(v))
#define BIT_PS_TIMER_A_EN_8821C BIT(7)
#define BIT_SHIFT_PS_TIMER_A_TSF_SEL_8821C 0
#define BIT_MASK_PS_TIMER_A_TSF_SEL_8821C 0x7
-#define BIT_PS_TIMER_A_TSF_SEL_8821C(x) (((x) & BIT_MASK_PS_TIMER_A_TSF_SEL_8821C) << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8821C)
-#define BIT_GET_PS_TIMER_A_TSF_SEL_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL_8821C) & BIT_MASK_PS_TIMER_A_TSF_SEL_8821C)
+#define BIT_PS_TIMER_A_TSF_SEL_8821C(x) \
+ (((x) & BIT_MASK_PS_TIMER_A_TSF_SEL_8821C) \
+ << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8821C)
+#define BITS_PS_TIMER_A_TSF_SEL_8821C \
+ (BIT_MASK_PS_TIMER_A_TSF_SEL_8821C \
+ << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8821C)
+#define BIT_CLEAR_PS_TIMER_A_TSF_SEL_8821C(x) \
+ ((x) & (~BITS_PS_TIMER_A_TSF_SEL_8821C))
+#define BIT_GET_PS_TIMER_A_TSF_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL_8821C) & \
+ BIT_MASK_PS_TIMER_A_TSF_SEL_8821C)
+#define BIT_SET_PS_TIMER_A_TSF_SEL_8821C(x, v) \
+ (BIT_CLEAR_PS_TIMER_A_TSF_SEL_8821C(x) | \
+ BIT_PS_TIMER_A_TSF_SEL_8821C(v))
+
+/* 2 REG_CPUMGQ_TX_TIMER_EARLY_8821C */
+
+#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8821C 0
+#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8821C 0xff
+#define BIT_CPUMGQ_TX_TIMER_EARLY_8821C(x) \
+ (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8821C) \
+ << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8821C)
+#define BITS_CPUMGQ_TX_TIMER_EARLY_8821C \
+ (BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8821C \
+ << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8821C)
+#define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8821C(x) \
+ ((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY_8821C))
+#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_8821C(x) \
+ (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8821C) & \
+ BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8821C)
+#define BIT_SET_CPUMGQ_TX_TIMER_EARLY_8821C(x, v) \
+ (BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8821C(x) | \
+ BIT_CPUMGQ_TX_TIMER_EARLY_8821C(v))
+
+/* 2 REG_PS_TIMER_A_EARLY_8821C */
+
+#define BIT_SHIFT_PS_TIMER_A_EARLY_8821C 0
+#define BIT_MASK_PS_TIMER_A_EARLY_8821C 0xff
+#define BIT_PS_TIMER_A_EARLY_8821C(x) \
+ (((x) & BIT_MASK_PS_TIMER_A_EARLY_8821C) \
+ << BIT_SHIFT_PS_TIMER_A_EARLY_8821C)
+#define BITS_PS_TIMER_A_EARLY_8821C \
+ (BIT_MASK_PS_TIMER_A_EARLY_8821C << BIT_SHIFT_PS_TIMER_A_EARLY_8821C)
+#define BIT_CLEAR_PS_TIMER_A_EARLY_8821C(x) \
+ ((x) & (~BITS_PS_TIMER_A_EARLY_8821C))
+#define BIT_GET_PS_TIMER_A_EARLY_8821C(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_A_EARLY_8821C) & \
+ BIT_MASK_PS_TIMER_A_EARLY_8821C)
+#define BIT_SET_PS_TIMER_A_EARLY_8821C(x, v) \
+ (BIT_CLEAR_PS_TIMER_A_EARLY_8821C(x) | BIT_PS_TIMER_A_EARLY_8821C(v))
+
+/* 2 REG_PS_TIMER_B_EARLY_8821C */
+
+#define BIT_SHIFT_PS_TIMER_B_EARLY_8821C 0
+#define BIT_MASK_PS_TIMER_B_EARLY_8821C 0xff
+#define BIT_PS_TIMER_B_EARLY_8821C(x) \
+ (((x) & BIT_MASK_PS_TIMER_B_EARLY_8821C) \
+ << BIT_SHIFT_PS_TIMER_B_EARLY_8821C)
+#define BITS_PS_TIMER_B_EARLY_8821C \
+ (BIT_MASK_PS_TIMER_B_EARLY_8821C << BIT_SHIFT_PS_TIMER_B_EARLY_8821C)
+#define BIT_CLEAR_PS_TIMER_B_EARLY_8821C(x) \
+ ((x) & (~BITS_PS_TIMER_B_EARLY_8821C))
+#define BIT_GET_PS_TIMER_B_EARLY_8821C(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_B_EARLY_8821C) & \
+ BIT_MASK_PS_TIMER_B_EARLY_8821C)
+#define BIT_SET_PS_TIMER_B_EARLY_8821C(x, v) \
+ (BIT_CLEAR_PS_TIMER_B_EARLY_8821C(x) | BIT_PS_TIMER_B_EARLY_8821C(v))
+
+/* 2 REG_PS_TIMER_C_EARLY_8821C */
+
+#define BIT_SHIFT_PS_TIMER_C_EARLY_8821C 0
+#define BIT_MASK_PS_TIMER_C_EARLY_8821C 0xff
+#define BIT_PS_TIMER_C_EARLY_8821C(x) \
+ (((x) & BIT_MASK_PS_TIMER_C_EARLY_8821C) \
+ << BIT_SHIFT_PS_TIMER_C_EARLY_8821C)
+#define BITS_PS_TIMER_C_EARLY_8821C \
+ (BIT_MASK_PS_TIMER_C_EARLY_8821C << BIT_SHIFT_PS_TIMER_C_EARLY_8821C)
+#define BIT_CLEAR_PS_TIMER_C_EARLY_8821C(x) \
+ ((x) & (~BITS_PS_TIMER_C_EARLY_8821C))
+#define BIT_GET_PS_TIMER_C_EARLY_8821C(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_C_EARLY_8821C) & \
+ BIT_MASK_PS_TIMER_C_EARLY_8821C)
+#define BIT_SET_PS_TIMER_C_EARLY_8821C(x, v) \
+ (BIT_CLEAR_PS_TIMER_C_EARLY_8821C(x) | BIT_PS_TIMER_C_EARLY_8821C(v))
+
+/* 2 REG_CPUMGQ_PARAMETER_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+#define BIT_MAC_STOP_CPUMGQ_8821C BIT(16)
+
+#define BIT_SHIFT_CW_8821C 8
+#define BIT_MASK_CW_8821C 0xff
+#define BIT_CW_8821C(x) (((x) & BIT_MASK_CW_8821C) << BIT_SHIFT_CW_8821C)
+#define BITS_CW_8821C (BIT_MASK_CW_8821C << BIT_SHIFT_CW_8821C)
+#define BIT_CLEAR_CW_8821C(x) ((x) & (~BITS_CW_8821C))
+#define BIT_GET_CW_8821C(x) (((x) >> BIT_SHIFT_CW_8821C) & BIT_MASK_CW_8821C)
+#define BIT_SET_CW_8821C(x, v) (BIT_CLEAR_CW_8821C(x) | BIT_CW_8821C(v))
+
+#define BIT_SHIFT_AIFS_8821C 0
+#define BIT_MASK_AIFS_8821C 0xff
+#define BIT_AIFS_8821C(x) (((x) & BIT_MASK_AIFS_8821C) << BIT_SHIFT_AIFS_8821C)
+#define BITS_AIFS_8821C (BIT_MASK_AIFS_8821C << BIT_SHIFT_AIFS_8821C)
+#define BIT_CLEAR_AIFS_8821C(x) ((x) & (~BITS_AIFS_8821C))
+#define BIT_GET_AIFS_8821C(x) \
+ (((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C)
+#define BIT_SET_AIFS_8821C(x, v) (BIT_CLEAR_AIFS_8821C(x) | BIT_AIFS_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+/* 2 REG_RSVD_8821C */
-/* 2 REG_CPUMGQ_TX_TIMER_EARLY_8821C */
+/* 2 REG_RSVD_8821C */
-#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8821C 0
-#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8821C 0xff
-#define BIT_CPUMGQ_TX_TIMER_EARLY_8821C(x) (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8821C) << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8821C)
-#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_8821C(x) (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8821C) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8821C)
+/* 2 REG_RSVD_8821C */
+/* 2 REG_RSVD_8821C */
-/* 2 REG_PS_TIMER_A_EARLY_8821C */
+/* 2 REG_RSVD_8821C */
-#define BIT_SHIFT_PS_TIMER_A_EARLY_8821C 0
-#define BIT_MASK_PS_TIMER_A_EARLY_8821C 0xff
-#define BIT_PS_TIMER_A_EARLY_8821C(x) (((x) & BIT_MASK_PS_TIMER_A_EARLY_8821C) << BIT_SHIFT_PS_TIMER_A_EARLY_8821C)
-#define BIT_GET_PS_TIMER_A_EARLY_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_A_EARLY_8821C) & BIT_MASK_PS_TIMER_A_EARLY_8821C)
+/* 2 REG_RSVD_8821C */
+/* 2 REG_RSVD_8821C */
-/* 2 REG_PS_TIMER_B_EARLY_8821C */
+/* 2 REG_RSVD_8821C */
-#define BIT_SHIFT_PS_TIMER_B_EARLY_8821C 0
-#define BIT_MASK_PS_TIMER_B_EARLY_8821C 0xff
-#define BIT_PS_TIMER_B_EARLY_8821C(x) (((x) & BIT_MASK_PS_TIMER_B_EARLY_8821C) << BIT_SHIFT_PS_TIMER_B_EARLY_8821C)
-#define BIT_GET_PS_TIMER_B_EARLY_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_B_EARLY_8821C) & BIT_MASK_PS_TIMER_B_EARLY_8821C)
+/* 2 REG_RSVD_8821C */
+/* 2 REG_RSVD_8821C */
-/* 2 REG_PS_TIMER_C_EARLY_8821C */
+/* 2 REG_RSVD_8821C */
-#define BIT_SHIFT_PS_TIMER_C_EARLY_8821C 0
-#define BIT_MASK_PS_TIMER_C_EARLY_8821C 0xff
-#define BIT_PS_TIMER_C_EARLY_8821C(x) (((x) & BIT_MASK_PS_TIMER_C_EARLY_8821C) << BIT_SHIFT_PS_TIMER_C_EARLY_8821C)
-#define BIT_GET_PS_TIMER_C_EARLY_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_C_EARLY_8821C) & BIT_MASK_PS_TIMER_C_EARLY_8821C)
+/* 2 REG_RSVD_8821C */
+/* 2 REG_RSVD_8821C */
/* 2 REG_NOT_VALID_8821C */
-/* 2 REG_BWOPMODE_8821C (BW OPERATION MODE REGISTER) */
+/* 2 REG_WMAC_CR_8821C (WMAC CR AND APSD CONTROL REGISTER) */
+#define BIT_IC_MACPHY_M_8821C BIT(0)
/* 2 REG_WMAC_FWPKT_CR_8821C */
#define BIT_FWEN_8821C BIT(7)
#define BIT_PHYSTS_PKT_CTRL_8821C BIT(6)
+#define BIT_FWFULL_TO_RXFF_EN_8821C BIT(5)
#define BIT_APPHDR_MIDSRCH_FAIL_8821C BIT(4)
#define BIT_FWPARSING_EN_8821C BIT(3)
#define BIT_SHIFT_APPEND_MHDR_LEN_8821C 0
#define BIT_MASK_APPEND_MHDR_LEN_8821C 0x7
-#define BIT_APPEND_MHDR_LEN_8821C(x) (((x) & BIT_MASK_APPEND_MHDR_LEN_8821C) << BIT_SHIFT_APPEND_MHDR_LEN_8821C)
-#define BIT_GET_APPEND_MHDR_LEN_8821C(x) (((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8821C) & BIT_MASK_APPEND_MHDR_LEN_8821C)
-
+#define BIT_APPEND_MHDR_LEN_8821C(x) \
+ (((x) & BIT_MASK_APPEND_MHDR_LEN_8821C) \
+ << BIT_SHIFT_APPEND_MHDR_LEN_8821C)
+#define BITS_APPEND_MHDR_LEN_8821C \
+ (BIT_MASK_APPEND_MHDR_LEN_8821C << BIT_SHIFT_APPEND_MHDR_LEN_8821C)
+#define BIT_CLEAR_APPEND_MHDR_LEN_8821C(x) ((x) & (~BITS_APPEND_MHDR_LEN_8821C))
+#define BIT_GET_APPEND_MHDR_LEN_8821C(x) \
+ (((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8821C) & \
+ BIT_MASK_APPEND_MHDR_LEN_8821C)
+#define BIT_SET_APPEND_MHDR_LEN_8821C(x, v) \
+ (BIT_CLEAR_APPEND_MHDR_LEN_8821C(x) | BIT_APPEND_MHDR_LEN_8821C(v))
/* 2 REG_FW_STS_FILTER_8821C */
#define BIT_DATA_FW_STS_FILTER_8821C BIT(2)
#define BIT_CTRL_FW_STS_FILTER_8821C BIT(1)
#define BIT_MGNT_FW_STS_FILTER_8821C BIT(0)
-/* 2 REG_WMAC_CR_8821C (WMAC CR AND APSD CONTROL REGISTER) */
-#define BIT_IC_MACPHY_M_8821C BIT(0)
+/* 2 REG_RSVD_8821C */
/* 2 REG_TCR_8821C (TRANSMISSION CONFIGURATION REGISTER) */
#define BIT_WMAC_EN_RTS_ADDR_8821C BIT(31)
@@ -7546,62 +14179,152 @@
#define BIT_APM_8821C BIT(1)
#define BIT_AAP_8821C BIT(0)
-/* 2 REG_RX_DRVINFO_SZ_8821C (RX DRIVER INFO SIZE REGISTER) */
-#define BIT_PHYSTS_PER_PKT_MODE_8821C BIT(7)
-
-#define BIT_SHIFT_DRVINFO_SZ_V1_8821C 0
-#define BIT_MASK_DRVINFO_SZ_V1_8821C 0xf
-#define BIT_DRVINFO_SZ_V1_8821C(x) (((x) & BIT_MASK_DRVINFO_SZ_V1_8821C) << BIT_SHIFT_DRVINFO_SZ_V1_8821C)
-#define BIT_GET_DRVINFO_SZ_V1_8821C(x) (((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8821C) & BIT_MASK_DRVINFO_SZ_V1_8821C)
+/* 2 REG_RX_PKT_LIMIT_8821C (RX PACKET LENGTH LIMIT REGISTER) */
+#define BIT_SHIFT_RXPKTLMT_8821C 0
+#define BIT_MASK_RXPKTLMT_8821C 0x3f
+#define BIT_RXPKTLMT_8821C(x) \
+ (((x) & BIT_MASK_RXPKTLMT_8821C) << BIT_SHIFT_RXPKTLMT_8821C)
+#define BITS_RXPKTLMT_8821C \
+ (BIT_MASK_RXPKTLMT_8821C << BIT_SHIFT_RXPKTLMT_8821C)
+#define BIT_CLEAR_RXPKTLMT_8821C(x) ((x) & (~BITS_RXPKTLMT_8821C))
+#define BIT_GET_RXPKTLMT_8821C(x) \
+ (((x) >> BIT_SHIFT_RXPKTLMT_8821C) & BIT_MASK_RXPKTLMT_8821C)
+#define BIT_SET_RXPKTLMT_8821C(x, v) \
+ (BIT_CLEAR_RXPKTLMT_8821C(x) | BIT_RXPKTLMT_8821C(v))
/* 2 REG_RX_DLK_TIME_8821C (RX DEADLOCK TIME REGISTER) */
#define BIT_SHIFT_RX_DLK_TIME_8821C 0
#define BIT_MASK_RX_DLK_TIME_8821C 0xff
-#define BIT_RX_DLK_TIME_8821C(x) (((x) & BIT_MASK_RX_DLK_TIME_8821C) << BIT_SHIFT_RX_DLK_TIME_8821C)
-#define BIT_GET_RX_DLK_TIME_8821C(x) (((x) >> BIT_SHIFT_RX_DLK_TIME_8821C) & BIT_MASK_RX_DLK_TIME_8821C)
-
-
-/* 2 REG_RX_PKT_LIMIT_8821C (RX PACKET LENGTH LIMIT REGISTER) */
-
-#define BIT_SHIFT_RXPKTLMT_8821C 0
-#define BIT_MASK_RXPKTLMT_8821C 0x3f
-#define BIT_RXPKTLMT_8821C(x) (((x) & BIT_MASK_RXPKTLMT_8821C) << BIT_SHIFT_RXPKTLMT_8821C)
-#define BIT_GET_RXPKTLMT_8821C(x) (((x) >> BIT_SHIFT_RXPKTLMT_8821C) & BIT_MASK_RXPKTLMT_8821C)
+#define BIT_RX_DLK_TIME_8821C(x) \
+ (((x) & BIT_MASK_RX_DLK_TIME_8821C) << BIT_SHIFT_RX_DLK_TIME_8821C)
+#define BITS_RX_DLK_TIME_8821C \
+ (BIT_MASK_RX_DLK_TIME_8821C << BIT_SHIFT_RX_DLK_TIME_8821C)
+#define BIT_CLEAR_RX_DLK_TIME_8821C(x) ((x) & (~BITS_RX_DLK_TIME_8821C))
+#define BIT_GET_RX_DLK_TIME_8821C(x) \
+ (((x) >> BIT_SHIFT_RX_DLK_TIME_8821C) & BIT_MASK_RX_DLK_TIME_8821C)
+#define BIT_SET_RX_DLK_TIME_8821C(x, v) \
+ (BIT_CLEAR_RX_DLK_TIME_8821C(x) | BIT_RX_DLK_TIME_8821C(v))
+
+/* 2 REG_RSVD_8821C */
+/* 2 REG_RX_DRVINFO_SZ_8821C (RX DRIVER INFO SIZE REGISTER) */
+#define BIT_PHYSTS_PER_PKT_MODE_8821C BIT(7)
-/* 2 REG_MACID_8821C (MAC ID REGISTER) */
+#define BIT_SHIFT_DRVINFO_SZ_V1_8821C 0
+#define BIT_MASK_DRVINFO_SZ_V1_8821C 0xf
+#define BIT_DRVINFO_SZ_V1_8821C(x) \
+ (((x) & BIT_MASK_DRVINFO_SZ_V1_8821C) << BIT_SHIFT_DRVINFO_SZ_V1_8821C)
+#define BITS_DRVINFO_SZ_V1_8821C \
+ (BIT_MASK_DRVINFO_SZ_V1_8821C << BIT_SHIFT_DRVINFO_SZ_V1_8821C)
+#define BIT_CLEAR_DRVINFO_SZ_V1_8821C(x) ((x) & (~BITS_DRVINFO_SZ_V1_8821C))
+#define BIT_GET_DRVINFO_SZ_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8821C) & BIT_MASK_DRVINFO_SZ_V1_8821C)
+#define BIT_SET_DRVINFO_SZ_V1_8821C(x, v) \
+ (BIT_CLEAR_DRVINFO_SZ_V1_8821C(x) | BIT_DRVINFO_SZ_V1_8821C(v))
+
+/* 2 REG_MACID_8821C (MAC ID REGISTER) */
+
+#define BIT_SHIFT_MACID_V1_8821C 0
+#define BIT_MASK_MACID_V1_8821C 0xffffffffL
+#define BIT_MACID_V1_8821C(x) \
+ (((x) & BIT_MASK_MACID_V1_8821C) << BIT_SHIFT_MACID_V1_8821C)
+#define BITS_MACID_V1_8821C \
+ (BIT_MASK_MACID_V1_8821C << BIT_SHIFT_MACID_V1_8821C)
+#define BIT_CLEAR_MACID_V1_8821C(x) ((x) & (~BITS_MACID_V1_8821C))
+#define BIT_GET_MACID_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_MACID_V1_8821C) & BIT_MASK_MACID_V1_8821C)
+#define BIT_SET_MACID_V1_8821C(x, v) \
+ (BIT_CLEAR_MACID_V1_8821C(x) | BIT_MACID_V1_8821C(v))
+
+/* 2 REG_MACID_H_8821C (MAC ID REGISTER) */
+
+#define BIT_SHIFT_MACID_H_V1_8821C 0
+#define BIT_MASK_MACID_H_V1_8821C 0xffff
+#define BIT_MACID_H_V1_8821C(x) \
+ (((x) & BIT_MASK_MACID_H_V1_8821C) << BIT_SHIFT_MACID_H_V1_8821C)
+#define BITS_MACID_H_V1_8821C \
+ (BIT_MASK_MACID_H_V1_8821C << BIT_SHIFT_MACID_H_V1_8821C)
+#define BIT_CLEAR_MACID_H_V1_8821C(x) ((x) & (~BITS_MACID_H_V1_8821C))
+#define BIT_GET_MACID_H_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_MACID_H_V1_8821C) & BIT_MASK_MACID_H_V1_8821C)
+#define BIT_SET_MACID_H_V1_8821C(x, v) \
+ (BIT_CLEAR_MACID_H_V1_8821C(x) | BIT_MACID_H_V1_8821C(v))
-#define BIT_SHIFT_MACID_8821C 0
-#define BIT_MASK_MACID_8821C 0xffffffffffffL
-#define BIT_MACID_8821C(x) (((x) & BIT_MASK_MACID_8821C) << BIT_SHIFT_MACID_8821C)
-#define BIT_GET_MACID_8821C(x) (((x) >> BIT_SHIFT_MACID_8821C) & BIT_MASK_MACID_8821C)
+/* 2 REG_BSSID_8821C (BSSID REGISTER) */
+#define BIT_SHIFT_BSSID_V1_8821C 0
+#define BIT_MASK_BSSID_V1_8821C 0xffffffffL
+#define BIT_BSSID_V1_8821C(x) \
+ (((x) & BIT_MASK_BSSID_V1_8821C) << BIT_SHIFT_BSSID_V1_8821C)
+#define BITS_BSSID_V1_8821C \
+ (BIT_MASK_BSSID_V1_8821C << BIT_SHIFT_BSSID_V1_8821C)
+#define BIT_CLEAR_BSSID_V1_8821C(x) ((x) & (~BITS_BSSID_V1_8821C))
+#define BIT_GET_BSSID_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_BSSID_V1_8821C) & BIT_MASK_BSSID_V1_8821C)
+#define BIT_SET_BSSID_V1_8821C(x, v) \
+ (BIT_CLEAR_BSSID_V1_8821C(x) | BIT_BSSID_V1_8821C(v))
-/* 2 REG_BSSID_8821C (BSSID REGISTER) */
+/* 2 REG_BSSID_H_8821C (BSSID REGISTER) */
-#define BIT_SHIFT_BSSID_8821C 0
-#define BIT_MASK_BSSID_8821C 0xffffffffffffL
-#define BIT_BSSID_8821C(x) (((x) & BIT_MASK_BSSID_8821C) << BIT_SHIFT_BSSID_8821C)
-#define BIT_GET_BSSID_8821C(x) (((x) >> BIT_SHIFT_BSSID_8821C) & BIT_MASK_BSSID_8821C)
+/* 2 REG_NOT_VALID_8821C */
+#define BIT_SHIFT_BSSID_H_V1_8821C 0
+#define BIT_MASK_BSSID_H_V1_8821C 0xffff
+#define BIT_BSSID_H_V1_8821C(x) \
+ (((x) & BIT_MASK_BSSID_H_V1_8821C) << BIT_SHIFT_BSSID_H_V1_8821C)
+#define BITS_BSSID_H_V1_8821C \
+ (BIT_MASK_BSSID_H_V1_8821C << BIT_SHIFT_BSSID_H_V1_8821C)
+#define BIT_CLEAR_BSSID_H_V1_8821C(x) ((x) & (~BITS_BSSID_H_V1_8821C))
+#define BIT_GET_BSSID_H_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_BSSID_H_V1_8821C) & BIT_MASK_BSSID_H_V1_8821C)
+#define BIT_SET_BSSID_H_V1_8821C(x, v) \
+ (BIT_CLEAR_BSSID_H_V1_8821C(x) | BIT_BSSID_H_V1_8821C(v))
/* 2 REG_MAR_8821C (MULTICAST ADDRESS REGISTER) */
-#define BIT_SHIFT_MAR_8821C 0
-#define BIT_MASK_MAR_8821C 0xffffffffffffffffL
-#define BIT_MAR_8821C(x) (((x) & BIT_MASK_MAR_8821C) << BIT_SHIFT_MAR_8821C)
-#define BIT_GET_MAR_8821C(x) (((x) >> BIT_SHIFT_MAR_8821C) & BIT_MASK_MAR_8821C)
-
+#define BIT_SHIFT_MAR_V1_8821C 0
+#define BIT_MASK_MAR_V1_8821C 0xffffffffL
+#define BIT_MAR_V1_8821C(x) \
+ (((x) & BIT_MASK_MAR_V1_8821C) << BIT_SHIFT_MAR_V1_8821C)
+#define BITS_MAR_V1_8821C (BIT_MASK_MAR_V1_8821C << BIT_SHIFT_MAR_V1_8821C)
+#define BIT_CLEAR_MAR_V1_8821C(x) ((x) & (~BITS_MAR_V1_8821C))
+#define BIT_GET_MAR_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_MAR_V1_8821C) & BIT_MASK_MAR_V1_8821C)
+#define BIT_SET_MAR_V1_8821C(x, v) \
+ (BIT_CLEAR_MAR_V1_8821C(x) | BIT_MAR_V1_8821C(v))
+
+/* 2 REG_MAR_H_8821C (MULTICAST ADDRESS REGISTER) */
+
+#define BIT_SHIFT_MAR_H_V1_8821C 0
+#define BIT_MASK_MAR_H_V1_8821C 0xffffffffL
+#define BIT_MAR_H_V1_8821C(x) \
+ (((x) & BIT_MASK_MAR_H_V1_8821C) << BIT_SHIFT_MAR_H_V1_8821C)
+#define BITS_MAR_H_V1_8821C \
+ (BIT_MASK_MAR_H_V1_8821C << BIT_SHIFT_MAR_H_V1_8821C)
+#define BIT_CLEAR_MAR_H_V1_8821C(x) ((x) & (~BITS_MAR_H_V1_8821C))
+#define BIT_GET_MAR_H_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_MAR_H_V1_8821C) & BIT_MASK_MAR_H_V1_8821C)
+#define BIT_SET_MAR_H_V1_8821C(x, v) \
+ (BIT_CLEAR_MAR_H_V1_8821C(x) | BIT_MAR_H_V1_8821C(v))
/* 2 REG_MBIDCAMCFG_1_8821C (MBSSID CAM CONFIGURATION REGISTER) */
#define BIT_SHIFT_MBIDCAM_RWDATA_L_8821C 0
#define BIT_MASK_MBIDCAM_RWDATA_L_8821C 0xffffffffL
-#define BIT_MBIDCAM_RWDATA_L_8821C(x) (((x) & BIT_MASK_MBIDCAM_RWDATA_L_8821C) << BIT_SHIFT_MBIDCAM_RWDATA_L_8821C)
-#define BIT_GET_MBIDCAM_RWDATA_L_8821C(x) (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L_8821C) & BIT_MASK_MBIDCAM_RWDATA_L_8821C)
-
+#define BIT_MBIDCAM_RWDATA_L_8821C(x) \
+ (((x) & BIT_MASK_MBIDCAM_RWDATA_L_8821C) \
+ << BIT_SHIFT_MBIDCAM_RWDATA_L_8821C)
+#define BITS_MBIDCAM_RWDATA_L_8821C \
+ (BIT_MASK_MBIDCAM_RWDATA_L_8821C << BIT_SHIFT_MBIDCAM_RWDATA_L_8821C)
+#define BIT_CLEAR_MBIDCAM_RWDATA_L_8821C(x) \
+ ((x) & (~BITS_MBIDCAM_RWDATA_L_8821C))
+#define BIT_GET_MBIDCAM_RWDATA_L_8821C(x) \
+ (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L_8821C) & \
+ BIT_MASK_MBIDCAM_RWDATA_L_8821C)
+#define BIT_SET_MBIDCAM_RWDATA_L_8821C(x, v) \
+ (BIT_CLEAR_MBIDCAM_RWDATA_L_8821C(x) | BIT_MBIDCAM_RWDATA_L_8821C(v))
/* 2 REG_MBIDCAMCFG_2_8821C (MBSSID CAM CONFIGURATION REGISTER) */
#define BIT_MBIDCAM_POLL_8821C BIT(31)
@@ -7609,8 +14332,15 @@
#define BIT_SHIFT_MBIDCAM_ADDR_8821C 24
#define BIT_MASK_MBIDCAM_ADDR_8821C 0x1f
-#define BIT_MBIDCAM_ADDR_8821C(x) (((x) & BIT_MASK_MBIDCAM_ADDR_8821C) << BIT_SHIFT_MBIDCAM_ADDR_8821C)
-#define BIT_GET_MBIDCAM_ADDR_8821C(x) (((x) >> BIT_SHIFT_MBIDCAM_ADDR_8821C) & BIT_MASK_MBIDCAM_ADDR_8821C)
+#define BIT_MBIDCAM_ADDR_8821C(x) \
+ (((x) & BIT_MASK_MBIDCAM_ADDR_8821C) << BIT_SHIFT_MBIDCAM_ADDR_8821C)
+#define BITS_MBIDCAM_ADDR_8821C \
+ (BIT_MASK_MBIDCAM_ADDR_8821C << BIT_SHIFT_MBIDCAM_ADDR_8821C)
+#define BIT_CLEAR_MBIDCAM_ADDR_8821C(x) ((x) & (~BITS_MBIDCAM_ADDR_8821C))
+#define BIT_GET_MBIDCAM_ADDR_8821C(x) \
+ (((x) >> BIT_SHIFT_MBIDCAM_ADDR_8821C) & BIT_MASK_MBIDCAM_ADDR_8821C)
+#define BIT_SET_MBIDCAM_ADDR_8821C(x, v) \
+ (BIT_CLEAR_MBIDCAM_ADDR_8821C(x) | BIT_MBIDCAM_ADDR_8821C(v))
#define BIT_MBIDCAM_VALID_8821C BIT(23)
#define BIT_LSIC_TXOP_EN_8821C BIT(17)
@@ -7618,141 +14348,253 @@
#define BIT_SHIFT_MBIDCAM_RWDATA_H_8821C 0
#define BIT_MASK_MBIDCAM_RWDATA_H_8821C 0xffff
-#define BIT_MBIDCAM_RWDATA_H_8821C(x) (((x) & BIT_MASK_MBIDCAM_RWDATA_H_8821C) << BIT_SHIFT_MBIDCAM_RWDATA_H_8821C)
-#define BIT_GET_MBIDCAM_RWDATA_H_8821C(x) (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H_8821C) & BIT_MASK_MBIDCAM_RWDATA_H_8821C)
+#define BIT_MBIDCAM_RWDATA_H_8821C(x) \
+ (((x) & BIT_MASK_MBIDCAM_RWDATA_H_8821C) \
+ << BIT_SHIFT_MBIDCAM_RWDATA_H_8821C)
+#define BITS_MBIDCAM_RWDATA_H_8821C \
+ (BIT_MASK_MBIDCAM_RWDATA_H_8821C << BIT_SHIFT_MBIDCAM_RWDATA_H_8821C)
+#define BIT_CLEAR_MBIDCAM_RWDATA_H_8821C(x) \
+ ((x) & (~BITS_MBIDCAM_RWDATA_H_8821C))
+#define BIT_GET_MBIDCAM_RWDATA_H_8821C(x) \
+ (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H_8821C) & \
+ BIT_MASK_MBIDCAM_RWDATA_H_8821C)
+#define BIT_SET_MBIDCAM_RWDATA_H_8821C(x, v) \
+ (BIT_CLEAR_MBIDCAM_RWDATA_H_8821C(x) | BIT_MBIDCAM_RWDATA_H_8821C(v))
+/* 2 REG_WMAC_TCR_TSFT_OFS_8821C */
-/* 2 REG_ZLD_NUM_8821C */
-
-#define BIT_SHIFT_ZLD_NUM_8821C 0
-#define BIT_MASK_ZLD_NUM_8821C 0xff
-#define BIT_ZLD_NUM_8821C(x) (((x) & BIT_MASK_ZLD_NUM_8821C) << BIT_SHIFT_ZLD_NUM_8821C)
-#define BIT_GET_ZLD_NUM_8821C(x) (((x) >> BIT_SHIFT_ZLD_NUM_8821C) & BIT_MASK_ZLD_NUM_8821C)
-
+#define BIT_SHIFT_WMAC_TCR_TSFT_OFS_8821C 0
+#define BIT_MASK_WMAC_TCR_TSFT_OFS_8821C 0xffff
+#define BIT_WMAC_TCR_TSFT_OFS_8821C(x) \
+ (((x) & BIT_MASK_WMAC_TCR_TSFT_OFS_8821C) \
+ << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8821C)
+#define BITS_WMAC_TCR_TSFT_OFS_8821C \
+ (BIT_MASK_WMAC_TCR_TSFT_OFS_8821C << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8821C)
+#define BIT_CLEAR_WMAC_TCR_TSFT_OFS_8821C(x) \
+ ((x) & (~BITS_WMAC_TCR_TSFT_OFS_8821C))
+#define BIT_GET_WMAC_TCR_TSFT_OFS_8821C(x) \
+ (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8821C) & \
+ BIT_MASK_WMAC_TCR_TSFT_OFS_8821C)
+#define BIT_SET_WMAC_TCR_TSFT_OFS_8821C(x, v) \
+ (BIT_CLEAR_WMAC_TCR_TSFT_OFS_8821C(x) | BIT_WMAC_TCR_TSFT_OFS_8821C(v))
/* 2 REG_UDF_THSD_8821C */
#define BIT_SHIFT_UDF_THSD_8821C 0
#define BIT_MASK_UDF_THSD_8821C 0xff
-#define BIT_UDF_THSD_8821C(x) (((x) & BIT_MASK_UDF_THSD_8821C) << BIT_SHIFT_UDF_THSD_8821C)
-#define BIT_GET_UDF_THSD_8821C(x) (((x) >> BIT_SHIFT_UDF_THSD_8821C) & BIT_MASK_UDF_THSD_8821C)
-
-
-/* 2 REG_WMAC_TCR_TSFT_OFS_8821C */
-
-#define BIT_SHIFT_WMAC_TCR_TSFT_OFS_8821C 0
-#define BIT_MASK_WMAC_TCR_TSFT_OFS_8821C 0xffff
-#define BIT_WMAC_TCR_TSFT_OFS_8821C(x) (((x) & BIT_MASK_WMAC_TCR_TSFT_OFS_8821C) << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8821C)
-#define BIT_GET_WMAC_TCR_TSFT_OFS_8821C(x) (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8821C) & BIT_MASK_WMAC_TCR_TSFT_OFS_8821C)
+#define BIT_UDF_THSD_8821C(x) \
+ (((x) & BIT_MASK_UDF_THSD_8821C) << BIT_SHIFT_UDF_THSD_8821C)
+#define BITS_UDF_THSD_8821C \
+ (BIT_MASK_UDF_THSD_8821C << BIT_SHIFT_UDF_THSD_8821C)
+#define BIT_CLEAR_UDF_THSD_8821C(x) ((x) & (~BITS_UDF_THSD_8821C))
+#define BIT_GET_UDF_THSD_8821C(x) \
+ (((x) >> BIT_SHIFT_UDF_THSD_8821C) & BIT_MASK_UDF_THSD_8821C)
+#define BIT_SET_UDF_THSD_8821C(x, v) \
+ (BIT_CLEAR_UDF_THSD_8821C(x) | BIT_UDF_THSD_8821C(v))
+/* 2 REG_ZLD_NUM_8821C */
-/* 2 REG_MCU_TEST_2_V1_8821C */
+#define BIT_SHIFT_ZLD_NUM_8821C 0
+#define BIT_MASK_ZLD_NUM_8821C 0xff
+#define BIT_ZLD_NUM_8821C(x) \
+ (((x) & BIT_MASK_ZLD_NUM_8821C) << BIT_SHIFT_ZLD_NUM_8821C)
+#define BITS_ZLD_NUM_8821C (BIT_MASK_ZLD_NUM_8821C << BIT_SHIFT_ZLD_NUM_8821C)
+#define BIT_CLEAR_ZLD_NUM_8821C(x) ((x) & (~BITS_ZLD_NUM_8821C))
+#define BIT_GET_ZLD_NUM_8821C(x) \
+ (((x) >> BIT_SHIFT_ZLD_NUM_8821C) & BIT_MASK_ZLD_NUM_8821C)
+#define BIT_SET_ZLD_NUM_8821C(x, v) \
+ (BIT_CLEAR_ZLD_NUM_8821C(x) | BIT_ZLD_NUM_8821C(v))
-#define BIT_SHIFT_MCU_RSVD_2_V1_8821C 0
-#define BIT_MASK_MCU_RSVD_2_V1_8821C 0xffff
-#define BIT_MCU_RSVD_2_V1_8821C(x) (((x) & BIT_MASK_MCU_RSVD_2_V1_8821C) << BIT_SHIFT_MCU_RSVD_2_V1_8821C)
-#define BIT_GET_MCU_RSVD_2_V1_8821C(x) (((x) >> BIT_SHIFT_MCU_RSVD_2_V1_8821C) & BIT_MASK_MCU_RSVD_2_V1_8821C)
+/* 2 REG_STMP_THSD_8821C */
+#define BIT_SHIFT_STMP_THSD_8821C 0
+#define BIT_MASK_STMP_THSD_8821C 0xff
+#define BIT_STMP_THSD_8821C(x) \
+ (((x) & BIT_MASK_STMP_THSD_8821C) << BIT_SHIFT_STMP_THSD_8821C)
+#define BITS_STMP_THSD_8821C \
+ (BIT_MASK_STMP_THSD_8821C << BIT_SHIFT_STMP_THSD_8821C)
+#define BIT_CLEAR_STMP_THSD_8821C(x) ((x) & (~BITS_STMP_THSD_8821C))
+#define BIT_GET_STMP_THSD_8821C(x) \
+ (((x) >> BIT_SHIFT_STMP_THSD_8821C) & BIT_MASK_STMP_THSD_8821C)
+#define BIT_SET_STMP_THSD_8821C(x, v) \
+ (BIT_CLEAR_STMP_THSD_8821C(x) | BIT_STMP_THSD_8821C(v))
/* 2 REG_WMAC_TXTIMEOUT_8821C */
#define BIT_SHIFT_WMAC_TXTIMEOUT_8821C 0
#define BIT_MASK_WMAC_TXTIMEOUT_8821C 0xff
-#define BIT_WMAC_TXTIMEOUT_8821C(x) (((x) & BIT_MASK_WMAC_TXTIMEOUT_8821C) << BIT_SHIFT_WMAC_TXTIMEOUT_8821C)
-#define BIT_GET_WMAC_TXTIMEOUT_8821C(x) (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8821C) & BIT_MASK_WMAC_TXTIMEOUT_8821C)
+#define BIT_WMAC_TXTIMEOUT_8821C(x) \
+ (((x) & BIT_MASK_WMAC_TXTIMEOUT_8821C) \
+ << BIT_SHIFT_WMAC_TXTIMEOUT_8821C)
+#define BITS_WMAC_TXTIMEOUT_8821C \
+ (BIT_MASK_WMAC_TXTIMEOUT_8821C << BIT_SHIFT_WMAC_TXTIMEOUT_8821C)
+#define BIT_CLEAR_WMAC_TXTIMEOUT_8821C(x) ((x) & (~BITS_WMAC_TXTIMEOUT_8821C))
+#define BIT_GET_WMAC_TXTIMEOUT_8821C(x) \
+ (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8821C) & \
+ BIT_MASK_WMAC_TXTIMEOUT_8821C)
+#define BIT_SET_WMAC_TXTIMEOUT_8821C(x, v) \
+ (BIT_CLEAR_WMAC_TXTIMEOUT_8821C(x) | BIT_WMAC_TXTIMEOUT_8821C(v))
+
+/* 2 REG_MCU_TEST_2_V1_8821C */
+#define BIT_SHIFT_MCU_RSVD_2_V1_8821C 0
+#define BIT_MASK_MCU_RSVD_2_V1_8821C 0xffff
+#define BIT_MCU_RSVD_2_V1_8821C(x) \
+ (((x) & BIT_MASK_MCU_RSVD_2_V1_8821C) << BIT_SHIFT_MCU_RSVD_2_V1_8821C)
+#define BITS_MCU_RSVD_2_V1_8821C \
+ (BIT_MASK_MCU_RSVD_2_V1_8821C << BIT_SHIFT_MCU_RSVD_2_V1_8821C)
+#define BIT_CLEAR_MCU_RSVD_2_V1_8821C(x) ((x) & (~BITS_MCU_RSVD_2_V1_8821C))
+#define BIT_GET_MCU_RSVD_2_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_MCU_RSVD_2_V1_8821C) & BIT_MASK_MCU_RSVD_2_V1_8821C)
+#define BIT_SET_MCU_RSVD_2_V1_8821C(x, v) \
+ (BIT_CLEAR_MCU_RSVD_2_V1_8821C(x) | BIT_MCU_RSVD_2_V1_8821C(v))
-/* 2 REG_STMP_THSD_8821C */
+/* 2 REG_USTIME_EDCA_8821C (US TIME TUNING FOR EDCA REGISTER) */
-#define BIT_SHIFT_STMP_THSD_8821C 0
-#define BIT_MASK_STMP_THSD_8821C 0xff
-#define BIT_STMP_THSD_8821C(x) (((x) & BIT_MASK_STMP_THSD_8821C) << BIT_SHIFT_STMP_THSD_8821C)
-#define BIT_GET_STMP_THSD_8821C(x) (((x) >> BIT_SHIFT_STMP_THSD_8821C) & BIT_MASK_STMP_THSD_8821C)
+#define BIT_SHIFT_USTIME_EDCA_8821C 0
+#define BIT_MASK_USTIME_EDCA_8821C 0xff
+#define BIT_USTIME_EDCA_8821C(x) \
+ (((x) & BIT_MASK_USTIME_EDCA_8821C) << BIT_SHIFT_USTIME_EDCA_8821C)
+#define BITS_USTIME_EDCA_8821C \
+ (BIT_MASK_USTIME_EDCA_8821C << BIT_SHIFT_USTIME_EDCA_8821C)
+#define BIT_CLEAR_USTIME_EDCA_8821C(x) ((x) & (~BITS_USTIME_EDCA_8821C))
+#define BIT_GET_USTIME_EDCA_8821C(x) \
+ (((x) >> BIT_SHIFT_USTIME_EDCA_8821C) & BIT_MASK_USTIME_EDCA_8821C)
+#define BIT_SET_USTIME_EDCA_8821C(x, v) \
+ (BIT_CLEAR_USTIME_EDCA_8821C(x) | BIT_USTIME_EDCA_8821C(v))
+
+/* 2 REG_ACKTO_CCK_8821C (ACK TIMEOUT REGISTER FOR CCK RATE) */
+#define BIT_SHIFT_ACKTO_CCK_8821C 0
+#define BIT_MASK_ACKTO_CCK_8821C 0xff
+#define BIT_ACKTO_CCK_8821C(x) \
+ (((x) & BIT_MASK_ACKTO_CCK_8821C) << BIT_SHIFT_ACKTO_CCK_8821C)
+#define BITS_ACKTO_CCK_8821C \
+ (BIT_MASK_ACKTO_CCK_8821C << BIT_SHIFT_ACKTO_CCK_8821C)
+#define BIT_CLEAR_ACKTO_CCK_8821C(x) ((x) & (~BITS_ACKTO_CCK_8821C))
+#define BIT_GET_ACKTO_CCK_8821C(x) \
+ (((x) >> BIT_SHIFT_ACKTO_CCK_8821C) & BIT_MASK_ACKTO_CCK_8821C)
+#define BIT_SET_ACKTO_CCK_8821C(x, v) \
+ (BIT_CLEAR_ACKTO_CCK_8821C(x) | BIT_ACKTO_CCK_8821C(v))
/* 2 REG_MAC_SPEC_SIFS_8821C (SPECIFICATION SIFS REGISTER) */
#define BIT_SHIFT_SPEC_SIFS_OFDM_8821C 8
#define BIT_MASK_SPEC_SIFS_OFDM_8821C 0xff
-#define BIT_SPEC_SIFS_OFDM_8821C(x) (((x) & BIT_MASK_SPEC_SIFS_OFDM_8821C) << BIT_SHIFT_SPEC_SIFS_OFDM_8821C)
-#define BIT_GET_SPEC_SIFS_OFDM_8821C(x) (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8821C) & BIT_MASK_SPEC_SIFS_OFDM_8821C)
-
+#define BIT_SPEC_SIFS_OFDM_8821C(x) \
+ (((x) & BIT_MASK_SPEC_SIFS_OFDM_8821C) \
+ << BIT_SHIFT_SPEC_SIFS_OFDM_8821C)
+#define BITS_SPEC_SIFS_OFDM_8821C \
+ (BIT_MASK_SPEC_SIFS_OFDM_8821C << BIT_SHIFT_SPEC_SIFS_OFDM_8821C)
+#define BIT_CLEAR_SPEC_SIFS_OFDM_8821C(x) ((x) & (~BITS_SPEC_SIFS_OFDM_8821C))
+#define BIT_GET_SPEC_SIFS_OFDM_8821C(x) \
+ (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8821C) & \
+ BIT_MASK_SPEC_SIFS_OFDM_8821C)
+#define BIT_SET_SPEC_SIFS_OFDM_8821C(x, v) \
+ (BIT_CLEAR_SPEC_SIFS_OFDM_8821C(x) | BIT_SPEC_SIFS_OFDM_8821C(v))
#define BIT_SHIFT_SPEC_SIFS_CCK_8821C 0
#define BIT_MASK_SPEC_SIFS_CCK_8821C 0xff
-#define BIT_SPEC_SIFS_CCK_8821C(x) (((x) & BIT_MASK_SPEC_SIFS_CCK_8821C) << BIT_SHIFT_SPEC_SIFS_CCK_8821C)
-#define BIT_GET_SPEC_SIFS_CCK_8821C(x) (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8821C) & BIT_MASK_SPEC_SIFS_CCK_8821C)
-
-
-/* 2 REG_ACKTO_CCK_8821C (ACK TIMEOUT REGISTER FOR CCK RATE) */
-
-#define BIT_SHIFT_ACKTO_CCK_8821C 0
-#define BIT_MASK_ACKTO_CCK_8821C 0xff
-#define BIT_ACKTO_CCK_8821C(x) (((x) & BIT_MASK_ACKTO_CCK_8821C) << BIT_SHIFT_ACKTO_CCK_8821C)
-#define BIT_GET_ACKTO_CCK_8821C(x) (((x) >> BIT_SHIFT_ACKTO_CCK_8821C) & BIT_MASK_ACKTO_CCK_8821C)
+#define BIT_SPEC_SIFS_CCK_8821C(x) \
+ (((x) & BIT_MASK_SPEC_SIFS_CCK_8821C) << BIT_SHIFT_SPEC_SIFS_CCK_8821C)
+#define BITS_SPEC_SIFS_CCK_8821C \
+ (BIT_MASK_SPEC_SIFS_CCK_8821C << BIT_SHIFT_SPEC_SIFS_CCK_8821C)
+#define BIT_CLEAR_SPEC_SIFS_CCK_8821C(x) ((x) & (~BITS_SPEC_SIFS_CCK_8821C))
+#define BIT_GET_SPEC_SIFS_CCK_8821C(x) \
+ (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8821C) & BIT_MASK_SPEC_SIFS_CCK_8821C)
+#define BIT_SET_SPEC_SIFS_CCK_8821C(x, v) \
+ (BIT_CLEAR_SPEC_SIFS_CCK_8821C(x) | BIT_SPEC_SIFS_CCK_8821C(v))
+/* 2 REG_RESP_SIFS_CCK_8821C (RESPONSE SIFS FOR CCK REGISTER) */
-/* 2 REG_USTIME_EDCA_8821C (US TIME TUNING FOR EDCA REGISTER) */
-
-#define BIT_SHIFT_USTIME_EDCA_V1_8821C 0
-#define BIT_MASK_USTIME_EDCA_V1_8821C 0x1ff
-#define BIT_USTIME_EDCA_V1_8821C(x) (((x) & BIT_MASK_USTIME_EDCA_V1_8821C) << BIT_SHIFT_USTIME_EDCA_V1_8821C)
-#define BIT_GET_USTIME_EDCA_V1_8821C(x) (((x) >> BIT_SHIFT_USTIME_EDCA_V1_8821C) & BIT_MASK_USTIME_EDCA_V1_8821C)
+#define BIT_SHIFT_SIFS_R2T_CCK_8821C 8
+#define BIT_MASK_SIFS_R2T_CCK_8821C 0xff
+#define BIT_SIFS_R2T_CCK_8821C(x) \
+ (((x) & BIT_MASK_SIFS_R2T_CCK_8821C) << BIT_SHIFT_SIFS_R2T_CCK_8821C)
+#define BITS_SIFS_R2T_CCK_8821C \
+ (BIT_MASK_SIFS_R2T_CCK_8821C << BIT_SHIFT_SIFS_R2T_CCK_8821C)
+#define BIT_CLEAR_SIFS_R2T_CCK_8821C(x) ((x) & (~BITS_SIFS_R2T_CCK_8821C))
+#define BIT_GET_SIFS_R2T_CCK_8821C(x) \
+ (((x) >> BIT_SHIFT_SIFS_R2T_CCK_8821C) & BIT_MASK_SIFS_R2T_CCK_8821C)
+#define BIT_SET_SIFS_R2T_CCK_8821C(x, v) \
+ (BIT_CLEAR_SIFS_R2T_CCK_8821C(x) | BIT_SIFS_R2T_CCK_8821C(v))
+#define BIT_SHIFT_SIFS_T2T_CCK_8821C 0
+#define BIT_MASK_SIFS_T2T_CCK_8821C 0xff
+#define BIT_SIFS_T2T_CCK_8821C(x) \
+ (((x) & BIT_MASK_SIFS_T2T_CCK_8821C) << BIT_SHIFT_SIFS_T2T_CCK_8821C)
+#define BITS_SIFS_T2T_CCK_8821C \
+ (BIT_MASK_SIFS_T2T_CCK_8821C << BIT_SHIFT_SIFS_T2T_CCK_8821C)
+#define BIT_CLEAR_SIFS_T2T_CCK_8821C(x) ((x) & (~BITS_SIFS_T2T_CCK_8821C))
+#define BIT_GET_SIFS_T2T_CCK_8821C(x) \
+ (((x) >> BIT_SHIFT_SIFS_T2T_CCK_8821C) & BIT_MASK_SIFS_T2T_CCK_8821C)
+#define BIT_SET_SIFS_T2T_CCK_8821C(x, v) \
+ (BIT_CLEAR_SIFS_T2T_CCK_8821C(x) | BIT_SIFS_T2T_CCK_8821C(v))
/* 2 REG_RESP_SIFS_OFDM_8821C (RESPONSE SIFS FOR OFDM REGISTER) */
#define BIT_SHIFT_SIFS_R2T_OFDM_8821C 8
#define BIT_MASK_SIFS_R2T_OFDM_8821C 0xff
-#define BIT_SIFS_R2T_OFDM_8821C(x) (((x) & BIT_MASK_SIFS_R2T_OFDM_8821C) << BIT_SHIFT_SIFS_R2T_OFDM_8821C)
-#define BIT_GET_SIFS_R2T_OFDM_8821C(x) (((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8821C) & BIT_MASK_SIFS_R2T_OFDM_8821C)
-
+#define BIT_SIFS_R2T_OFDM_8821C(x) \
+ (((x) & BIT_MASK_SIFS_R2T_OFDM_8821C) << BIT_SHIFT_SIFS_R2T_OFDM_8821C)
+#define BITS_SIFS_R2T_OFDM_8821C \
+ (BIT_MASK_SIFS_R2T_OFDM_8821C << BIT_SHIFT_SIFS_R2T_OFDM_8821C)
+#define BIT_CLEAR_SIFS_R2T_OFDM_8821C(x) ((x) & (~BITS_SIFS_R2T_OFDM_8821C))
+#define BIT_GET_SIFS_R2T_OFDM_8821C(x) \
+ (((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8821C) & BIT_MASK_SIFS_R2T_OFDM_8821C)
+#define BIT_SET_SIFS_R2T_OFDM_8821C(x, v) \
+ (BIT_CLEAR_SIFS_R2T_OFDM_8821C(x) | BIT_SIFS_R2T_OFDM_8821C(v))
#define BIT_SHIFT_SIFS_T2T_OFDM_8821C 0
#define BIT_MASK_SIFS_T2T_OFDM_8821C 0xff
-#define BIT_SIFS_T2T_OFDM_8821C(x) (((x) & BIT_MASK_SIFS_T2T_OFDM_8821C) << BIT_SHIFT_SIFS_T2T_OFDM_8821C)
-#define BIT_GET_SIFS_T2T_OFDM_8821C(x) (((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8821C) & BIT_MASK_SIFS_T2T_OFDM_8821C)
-
-
-/* 2 REG_RESP_SIFS_CCK_8821C (RESPONSE SIFS FOR CCK REGISTER) */
+#define BIT_SIFS_T2T_OFDM_8821C(x) \
+ (((x) & BIT_MASK_SIFS_T2T_OFDM_8821C) << BIT_SHIFT_SIFS_T2T_OFDM_8821C)
+#define BITS_SIFS_T2T_OFDM_8821C \
+ (BIT_MASK_SIFS_T2T_OFDM_8821C << BIT_SHIFT_SIFS_T2T_OFDM_8821C)
+#define BIT_CLEAR_SIFS_T2T_OFDM_8821C(x) ((x) & (~BITS_SIFS_T2T_OFDM_8821C))
+#define BIT_GET_SIFS_T2T_OFDM_8821C(x) \
+ (((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8821C) & BIT_MASK_SIFS_T2T_OFDM_8821C)
+#define BIT_SET_SIFS_T2T_OFDM_8821C(x, v) \
+ (BIT_CLEAR_SIFS_T2T_OFDM_8821C(x) | BIT_SIFS_T2T_OFDM_8821C(v))
-#define BIT_SHIFT_SIFS_R2T_CCK_8821C 8
-#define BIT_MASK_SIFS_R2T_CCK_8821C 0xff
-#define BIT_SIFS_R2T_CCK_8821C(x) (((x) & BIT_MASK_SIFS_R2T_CCK_8821C) << BIT_SHIFT_SIFS_R2T_CCK_8821C)
-#define BIT_GET_SIFS_R2T_CCK_8821C(x) (((x) >> BIT_SHIFT_SIFS_R2T_CCK_8821C) & BIT_MASK_SIFS_R2T_CCK_8821C)
+/* 2 REG_ACKTO_8821C (ACK TIMEOUT REGISTER) */
+#define BIT_SHIFT_ACKTO_8821C 0
+#define BIT_MASK_ACKTO_8821C 0xff
+#define BIT_ACKTO_8821C(x) \
+ (((x) & BIT_MASK_ACKTO_8821C) << BIT_SHIFT_ACKTO_8821C)
+#define BITS_ACKTO_8821C (BIT_MASK_ACKTO_8821C << BIT_SHIFT_ACKTO_8821C)
+#define BIT_CLEAR_ACKTO_8821C(x) ((x) & (~BITS_ACKTO_8821C))
+#define BIT_GET_ACKTO_8821C(x) \
+ (((x) >> BIT_SHIFT_ACKTO_8821C) & BIT_MASK_ACKTO_8821C)
+#define BIT_SET_ACKTO_8821C(x, v) \
+ (BIT_CLEAR_ACKTO_8821C(x) | BIT_ACKTO_8821C(v))
-#define BIT_SHIFT_SIFS_T2T_CCK_8821C 0
-#define BIT_MASK_SIFS_T2T_CCK_8821C 0xff
-#define BIT_SIFS_T2T_CCK_8821C(x) (((x) & BIT_MASK_SIFS_T2T_CCK_8821C) << BIT_SHIFT_SIFS_T2T_CCK_8821C)
-#define BIT_GET_SIFS_T2T_CCK_8821C(x) (((x) >> BIT_SHIFT_SIFS_T2T_CCK_8821C) & BIT_MASK_SIFS_T2T_CCK_8821C)
+/* 2 REG_CTS2TO_8821C (CTS2 TIMEOUT REGISTER) */
+#define BIT_SHIFT_CTS2TO_8821C 0
+#define BIT_MASK_CTS2TO_8821C 0xff
+#define BIT_CTS2TO_8821C(x) \
+ (((x) & BIT_MASK_CTS2TO_8821C) << BIT_SHIFT_CTS2TO_8821C)
+#define BITS_CTS2TO_8821C (BIT_MASK_CTS2TO_8821C << BIT_SHIFT_CTS2TO_8821C)
+#define BIT_CLEAR_CTS2TO_8821C(x) ((x) & (~BITS_CTS2TO_8821C))
+#define BIT_GET_CTS2TO_8821C(x) \
+ (((x) >> BIT_SHIFT_CTS2TO_8821C) & BIT_MASK_CTS2TO_8821C)
+#define BIT_SET_CTS2TO_8821C(x, v) \
+ (BIT_CLEAR_CTS2TO_8821C(x) | BIT_CTS2TO_8821C(v))
/* 2 REG_EIFS_8821C (EIFS REGISTER) */
#define BIT_SHIFT_EIFS_8821C 0
#define BIT_MASK_EIFS_8821C 0xffff
#define BIT_EIFS_8821C(x) (((x) & BIT_MASK_EIFS_8821C) << BIT_SHIFT_EIFS_8821C)
-#define BIT_GET_EIFS_8821C(x) (((x) >> BIT_SHIFT_EIFS_8821C) & BIT_MASK_EIFS_8821C)
-
-
-/* 2 REG_CTS2TO_8821C (CTS2 TIMEOUT REGISTER) */
-
-#define BIT_SHIFT_CTS2TO_8821C 0
-#define BIT_MASK_CTS2TO_8821C 0xff
-#define BIT_CTS2TO_8821C(x) (((x) & BIT_MASK_CTS2TO_8821C) << BIT_SHIFT_CTS2TO_8821C)
-#define BIT_GET_CTS2TO_8821C(x) (((x) >> BIT_SHIFT_CTS2TO_8821C) & BIT_MASK_CTS2TO_8821C)
-
-
-/* 2 REG_ACKTO_8821C (ACK TIMEOUT REGISTER) */
+#define BITS_EIFS_8821C (BIT_MASK_EIFS_8821C << BIT_SHIFT_EIFS_8821C)
+#define BIT_CLEAR_EIFS_8821C(x) ((x) & (~BITS_EIFS_8821C))
+#define BIT_GET_EIFS_8821C(x) \
+ (((x) >> BIT_SHIFT_EIFS_8821C) & BIT_MASK_EIFS_8821C)
+#define BIT_SET_EIFS_8821C(x, v) (BIT_CLEAR_EIFS_8821C(x) | BIT_EIFS_8821C(v))
-#define BIT_SHIFT_ACKTO_8821C 0
-#define BIT_MASK_ACKTO_8821C 0xff
-#define BIT_ACKTO_8821C(x) (((x) & BIT_MASK_ACKTO_8821C) << BIT_SHIFT_ACKTO_8821C)
-#define BIT_GET_ACKTO_8821C(x) (((x) >> BIT_SHIFT_ACKTO_8821C) & BIT_MASK_ACKTO_8821C)
-
-
-/* 2 REG_RPFM_MAP0_8821C (RX PAYLOAD FILTER MAP FRAME TYPE CONTROL REGISTER GROUP 0) */
+/* 2 REG_RPFM_MAP0_8821C */
#define BIT_MGT_RPFM15EN_8821C BIT(15)
#define BIT_MGT_RPFM14EN_8821C BIT(14)
#define BIT_MGT_RPFM13EN_8821C BIT(13)
@@ -7770,7 +14612,7 @@
#define BIT_MGT_RPFM1EN_8821C BIT(1)
#define BIT_MGT_RPFM0EN_8821C BIT(0)
-/* 2 REG_RPFM_MAP1_8821C (RX PAYLOAD FILTER MAP FRAME TYPE CONTROL REGISTER GROUP 1) */
+/* 2 REG_RPFM_MAP1_V1_8821C */
#define BIT_DATA_RPFM15EN_8821C BIT(15)
#define BIT_DATA_RPFM14EN_8821C BIT(14)
#define BIT_DATA_RPFM13EN_8821C BIT(13)
@@ -7795,39 +14637,66 @@
#define BIT_SHIFT_RPFM_CAM_ADDR_8821C 0
#define BIT_MASK_RPFM_CAM_ADDR_8821C 0x7f
-#define BIT_RPFM_CAM_ADDR_8821C(x) (((x) & BIT_MASK_RPFM_CAM_ADDR_8821C) << BIT_SHIFT_RPFM_CAM_ADDR_8821C)
-#define BIT_GET_RPFM_CAM_ADDR_8821C(x) (((x) >> BIT_SHIFT_RPFM_CAM_ADDR_8821C) & BIT_MASK_RPFM_CAM_ADDR_8821C)
-
+#define BIT_RPFM_CAM_ADDR_8821C(x) \
+ (((x) & BIT_MASK_RPFM_CAM_ADDR_8821C) << BIT_SHIFT_RPFM_CAM_ADDR_8821C)
+#define BITS_RPFM_CAM_ADDR_8821C \
+ (BIT_MASK_RPFM_CAM_ADDR_8821C << BIT_SHIFT_RPFM_CAM_ADDR_8821C)
+#define BIT_CLEAR_RPFM_CAM_ADDR_8821C(x) ((x) & (~BITS_RPFM_CAM_ADDR_8821C))
+#define BIT_GET_RPFM_CAM_ADDR_8821C(x) \
+ (((x) >> BIT_SHIFT_RPFM_CAM_ADDR_8821C) & BIT_MASK_RPFM_CAM_ADDR_8821C)
+#define BIT_SET_RPFM_CAM_ADDR_8821C(x, v) \
+ (BIT_CLEAR_RPFM_CAM_ADDR_8821C(x) | BIT_RPFM_CAM_ADDR_8821C(v))
/* 2 REG_RPFM_CAM_RWD_8821C (ACK TIMEOUT REGISTER) */
#define BIT_SHIFT_RPFM_CAM_RWD_8821C 0
#define BIT_MASK_RPFM_CAM_RWD_8821C 0xffffffffL
-#define BIT_RPFM_CAM_RWD_8821C(x) (((x) & BIT_MASK_RPFM_CAM_RWD_8821C) << BIT_SHIFT_RPFM_CAM_RWD_8821C)
-#define BIT_GET_RPFM_CAM_RWD_8821C(x) (((x) >> BIT_SHIFT_RPFM_CAM_RWD_8821C) & BIT_MASK_RPFM_CAM_RWD_8821C)
-
-
-/* 2 REG_NOT_VALID_8821C */
+#define BIT_RPFM_CAM_RWD_8821C(x) \
+ (((x) & BIT_MASK_RPFM_CAM_RWD_8821C) << BIT_SHIFT_RPFM_CAM_RWD_8821C)
+#define BITS_RPFM_CAM_RWD_8821C \
+ (BIT_MASK_RPFM_CAM_RWD_8821C << BIT_SHIFT_RPFM_CAM_RWD_8821C)
+#define BIT_CLEAR_RPFM_CAM_RWD_8821C(x) ((x) & (~BITS_RPFM_CAM_RWD_8821C))
+#define BIT_GET_RPFM_CAM_RWD_8821C(x) \
+ (((x) >> BIT_SHIFT_RPFM_CAM_RWD_8821C) & BIT_MASK_RPFM_CAM_RWD_8821C)
+#define BIT_SET_RPFM_CAM_RWD_8821C(x, v) \
+ (BIT_CLEAR_RPFM_CAM_RWD_8821C(x) | BIT_RPFM_CAM_RWD_8821C(v))
/* 2 REG_NAV_CTRL_8821C (NAV CONTROL REGISTER) */
#define BIT_SHIFT_NAV_UPPER_8821C 16
#define BIT_MASK_NAV_UPPER_8821C 0xff
-#define BIT_NAV_UPPER_8821C(x) (((x) & BIT_MASK_NAV_UPPER_8821C) << BIT_SHIFT_NAV_UPPER_8821C)
-#define BIT_GET_NAV_UPPER_8821C(x) (((x) >> BIT_SHIFT_NAV_UPPER_8821C) & BIT_MASK_NAV_UPPER_8821C)
-
+#define BIT_NAV_UPPER_8821C(x) \
+ (((x) & BIT_MASK_NAV_UPPER_8821C) << BIT_SHIFT_NAV_UPPER_8821C)
+#define BITS_NAV_UPPER_8821C \
+ (BIT_MASK_NAV_UPPER_8821C << BIT_SHIFT_NAV_UPPER_8821C)
+#define BIT_CLEAR_NAV_UPPER_8821C(x) ((x) & (~BITS_NAV_UPPER_8821C))
+#define BIT_GET_NAV_UPPER_8821C(x) \
+ (((x) >> BIT_SHIFT_NAV_UPPER_8821C) & BIT_MASK_NAV_UPPER_8821C)
+#define BIT_SET_NAV_UPPER_8821C(x, v) \
+ (BIT_CLEAR_NAV_UPPER_8821C(x) | BIT_NAV_UPPER_8821C(v))
#define BIT_SHIFT_RXMYRTS_NAV_8821C 8
#define BIT_MASK_RXMYRTS_NAV_8821C 0xf
-#define BIT_RXMYRTS_NAV_8821C(x) (((x) & BIT_MASK_RXMYRTS_NAV_8821C) << BIT_SHIFT_RXMYRTS_NAV_8821C)
-#define BIT_GET_RXMYRTS_NAV_8821C(x) (((x) >> BIT_SHIFT_RXMYRTS_NAV_8821C) & BIT_MASK_RXMYRTS_NAV_8821C)
-
+#define BIT_RXMYRTS_NAV_8821C(x) \
+ (((x) & BIT_MASK_RXMYRTS_NAV_8821C) << BIT_SHIFT_RXMYRTS_NAV_8821C)
+#define BITS_RXMYRTS_NAV_8821C \
+ (BIT_MASK_RXMYRTS_NAV_8821C << BIT_SHIFT_RXMYRTS_NAV_8821C)
+#define BIT_CLEAR_RXMYRTS_NAV_8821C(x) ((x) & (~BITS_RXMYRTS_NAV_8821C))
+#define BIT_GET_RXMYRTS_NAV_8821C(x) \
+ (((x) >> BIT_SHIFT_RXMYRTS_NAV_8821C) & BIT_MASK_RXMYRTS_NAV_8821C)
+#define BIT_SET_RXMYRTS_NAV_8821C(x, v) \
+ (BIT_CLEAR_RXMYRTS_NAV_8821C(x) | BIT_RXMYRTS_NAV_8821C(v))
#define BIT_SHIFT_RTSRST_8821C 0
#define BIT_MASK_RTSRST_8821C 0xff
-#define BIT_RTSRST_8821C(x) (((x) & BIT_MASK_RTSRST_8821C) << BIT_SHIFT_RTSRST_8821C)
-#define BIT_GET_RTSRST_8821C(x) (((x) >> BIT_SHIFT_RTSRST_8821C) & BIT_MASK_RTSRST_8821C)
-
+#define BIT_RTSRST_8821C(x) \
+ (((x) & BIT_MASK_RTSRST_8821C) << BIT_SHIFT_RTSRST_8821C)
+#define BITS_RTSRST_8821C (BIT_MASK_RTSRST_8821C << BIT_SHIFT_RTSRST_8821C)
+#define BIT_CLEAR_RTSRST_8821C(x) ((x) & (~BITS_RTSRST_8821C))
+#define BIT_GET_RTSRST_8821C(x) \
+ (((x) >> BIT_SHIFT_RTSRST_8821C) & BIT_MASK_RTSRST_8821C)
+#define BIT_SET_RTSRST_8821C(x, v) \
+ (BIT_CLEAR_RTSRST_8821C(x) | BIT_RTSRST_8821C(v))
/* 2 REG_BACAMCMD_8821C (BLOCK ACK CAM COMMAND REGISTER) */
#define BIT_BACAM_POLL_8821C BIT(31)
@@ -7836,78 +14705,149 @@
#define BIT_SHIFT_TXSBM_8821C 14
#define BIT_MASK_TXSBM_8821C 0x3
-#define BIT_TXSBM_8821C(x) (((x) & BIT_MASK_TXSBM_8821C) << BIT_SHIFT_TXSBM_8821C)
-#define BIT_GET_TXSBM_8821C(x) (((x) >> BIT_SHIFT_TXSBM_8821C) & BIT_MASK_TXSBM_8821C)
-
+#define BIT_TXSBM_8821C(x) \
+ (((x) & BIT_MASK_TXSBM_8821C) << BIT_SHIFT_TXSBM_8821C)
+#define BITS_TXSBM_8821C (BIT_MASK_TXSBM_8821C << BIT_SHIFT_TXSBM_8821C)
+#define BIT_CLEAR_TXSBM_8821C(x) ((x) & (~BITS_TXSBM_8821C))
+#define BIT_GET_TXSBM_8821C(x) \
+ (((x) >> BIT_SHIFT_TXSBM_8821C) & BIT_MASK_TXSBM_8821C)
+#define BIT_SET_TXSBM_8821C(x, v) \
+ (BIT_CLEAR_TXSBM_8821C(x) | BIT_TXSBM_8821C(v))
#define BIT_SHIFT_BACAM_ADDR_8821C 0
#define BIT_MASK_BACAM_ADDR_8821C 0x3f
-#define BIT_BACAM_ADDR_8821C(x) (((x) & BIT_MASK_BACAM_ADDR_8821C) << BIT_SHIFT_BACAM_ADDR_8821C)
-#define BIT_GET_BACAM_ADDR_8821C(x) (((x) >> BIT_SHIFT_BACAM_ADDR_8821C) & BIT_MASK_BACAM_ADDR_8821C)
-
+#define BIT_BACAM_ADDR_8821C(x) \
+ (((x) & BIT_MASK_BACAM_ADDR_8821C) << BIT_SHIFT_BACAM_ADDR_8821C)
+#define BITS_BACAM_ADDR_8821C \
+ (BIT_MASK_BACAM_ADDR_8821C << BIT_SHIFT_BACAM_ADDR_8821C)
+#define BIT_CLEAR_BACAM_ADDR_8821C(x) ((x) & (~BITS_BACAM_ADDR_8821C))
+#define BIT_GET_BACAM_ADDR_8821C(x) \
+ (((x) >> BIT_SHIFT_BACAM_ADDR_8821C) & BIT_MASK_BACAM_ADDR_8821C)
+#define BIT_SET_BACAM_ADDR_8821C(x, v) \
+ (BIT_CLEAR_BACAM_ADDR_8821C(x) | BIT_BACAM_ADDR_8821C(v))
/* 2 REG_BACAMCONTENT_8821C (BLOCK ACK CAM CONTENT REGISTER) */
-#define BIT_SHIFT_BA_CONTENT_H_8821C (32 & CPU_OPT_WIDTH)
-#define BIT_MASK_BA_CONTENT_H_8821C 0xffffffffL
-#define BIT_BA_CONTENT_H_8821C(x) (((x) & BIT_MASK_BA_CONTENT_H_8821C) << BIT_SHIFT_BA_CONTENT_H_8821C)
-#define BIT_GET_BA_CONTENT_H_8821C(x) (((x) >> BIT_SHIFT_BA_CONTENT_H_8821C) & BIT_MASK_BA_CONTENT_H_8821C)
-
-
#define BIT_SHIFT_BA_CONTENT_L_8821C 0
#define BIT_MASK_BA_CONTENT_L_8821C 0xffffffffL
-#define BIT_BA_CONTENT_L_8821C(x) (((x) & BIT_MASK_BA_CONTENT_L_8821C) << BIT_SHIFT_BA_CONTENT_L_8821C)
-#define BIT_GET_BA_CONTENT_L_8821C(x) (((x) >> BIT_SHIFT_BA_CONTENT_L_8821C) & BIT_MASK_BA_CONTENT_L_8821C)
+#define BIT_BA_CONTENT_L_8821C(x) \
+ (((x) & BIT_MASK_BA_CONTENT_L_8821C) << BIT_SHIFT_BA_CONTENT_L_8821C)
+#define BITS_BA_CONTENT_L_8821C \
+ (BIT_MASK_BA_CONTENT_L_8821C << BIT_SHIFT_BA_CONTENT_L_8821C)
+#define BIT_CLEAR_BA_CONTENT_L_8821C(x) ((x) & (~BITS_BA_CONTENT_L_8821C))
+#define BIT_GET_BA_CONTENT_L_8821C(x) \
+ (((x) >> BIT_SHIFT_BA_CONTENT_L_8821C) & BIT_MASK_BA_CONTENT_L_8821C)
+#define BIT_SET_BA_CONTENT_L_8821C(x, v) \
+ (BIT_CLEAR_BA_CONTENT_L_8821C(x) | BIT_BA_CONTENT_L_8821C(v))
+
+/* 2 REG_BACAMCONTENT_H_8821C (BLOCK ACK CAM CONTENT REGISTER) */
+
+#define BIT_SHIFT_BA_CONTENT_H_8821C 0
+#define BIT_MASK_BA_CONTENT_H_8821C 0xffffffffL
+#define BIT_BA_CONTENT_H_8821C(x) \
+ (((x) & BIT_MASK_BA_CONTENT_H_8821C) << BIT_SHIFT_BA_CONTENT_H_8821C)
+#define BITS_BA_CONTENT_H_8821C \
+ (BIT_MASK_BA_CONTENT_H_8821C << BIT_SHIFT_BA_CONTENT_H_8821C)
+#define BIT_CLEAR_BA_CONTENT_H_8821C(x) ((x) & (~BITS_BA_CONTENT_H_8821C))
+#define BIT_GET_BA_CONTENT_H_8821C(x) \
+ (((x) >> BIT_SHIFT_BA_CONTENT_H_8821C) & BIT_MASK_BA_CONTENT_H_8821C)
+#define BIT_SET_BA_CONTENT_H_8821C(x, v) \
+ (BIT_CLEAR_BA_CONTENT_H_8821C(x) | BIT_BA_CONTENT_H_8821C(v))
+/* 2 REG_LBDLY_8821C (LOOPBACK DELAY REGISTER) */
-/* 2 REG_NOT_VALID_8821C */
-#define BIT_BITMAP_VO_8821C BIT(7)
-#define BIT_BITMAP_VI_8821C BIT(6)
-#define BIT_BITMAP_BE_8821C BIT(5)
-#define BIT_BITMAP_BK_8821C BIT(4)
+#define BIT_SHIFT_LBDLY_8821C 0
+#define BIT_MASK_LBDLY_8821C 0x1f
+#define BIT_LBDLY_8821C(x) \
+ (((x) & BIT_MASK_LBDLY_8821C) << BIT_SHIFT_LBDLY_8821C)
+#define BITS_LBDLY_8821C (BIT_MASK_LBDLY_8821C << BIT_SHIFT_LBDLY_8821C)
+#define BIT_CLEAR_LBDLY_8821C(x) ((x) & (~BITS_LBDLY_8821C))
+#define BIT_GET_LBDLY_8821C(x) \
+ (((x) >> BIT_SHIFT_LBDLY_8821C) & BIT_MASK_LBDLY_8821C)
+#define BIT_SET_LBDLY_8821C(x, v) \
+ (BIT_CLEAR_LBDLY_8821C(x) | BIT_LBDLY_8821C(v))
-#define BIT_SHIFT_BITMAP_CONDITION_8821C 2
-#define BIT_MASK_BITMAP_CONDITION_8821C 0x3
-#define BIT_BITMAP_CONDITION_8821C(x) (((x) & BIT_MASK_BITMAP_CONDITION_8821C) << BIT_SHIFT_BITMAP_CONDITION_8821C)
-#define BIT_GET_BITMAP_CONDITION_8821C(x) (((x) >> BIT_SHIFT_BITMAP_CONDITION_8821C) & BIT_MASK_BITMAP_CONDITION_8821C)
+/* 2 REG_WMAC_BACAM_RPMEN_8821C */
-#define BIT_BITMAP_SSNBK_COUNTER_CLR_8821C BIT(1)
-#define BIT_BITMAP_FORCE_8821C BIT(0)
+#define BIT_SHIFT_BITMAP_SSNBK_COUNTER_8821C 2
+#define BIT_MASK_BITMAP_SSNBK_COUNTER_8821C 0x3f
+#define BIT_BITMAP_SSNBK_COUNTER_8821C(x) \
+ (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8821C) \
+ << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8821C)
+#define BITS_BITMAP_SSNBK_COUNTER_8821C \
+ (BIT_MASK_BITMAP_SSNBK_COUNTER_8821C \
+ << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8821C)
+#define BIT_CLEAR_BITMAP_SSNBK_COUNTER_8821C(x) \
+ ((x) & (~BITS_BITMAP_SSNBK_COUNTER_8821C))
+#define BIT_GET_BITMAP_SSNBK_COUNTER_8821C(x) \
+ (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8821C) & \
+ BIT_MASK_BITMAP_SSNBK_COUNTER_8821C)
+#define BIT_SET_BITMAP_SSNBK_COUNTER_8821C(x, v) \
+ (BIT_CLEAR_BITMAP_SSNBK_COUNTER_8821C(x) | \
+ BIT_BITMAP_SSNBK_COUNTER_8821C(v))
+
+#define BIT_BITMAP_EN_8821C BIT(1)
+#define BIT_WMAC_BACAM_RPMEN_8821C BIT(0)
/* 2 REG_TX_RX_8821C STATUS */
#define BIT_SHIFT_RXPKT_TYPE_8821C 2
#define BIT_MASK_RXPKT_TYPE_8821C 0x3f
-#define BIT_RXPKT_TYPE_8821C(x) (((x) & BIT_MASK_RXPKT_TYPE_8821C) << BIT_SHIFT_RXPKT_TYPE_8821C)
-#define BIT_GET_RXPKT_TYPE_8821C(x) (((x) >> BIT_SHIFT_RXPKT_TYPE_8821C) & BIT_MASK_RXPKT_TYPE_8821C)
+#define BIT_RXPKT_TYPE_8821C(x) \
+ (((x) & BIT_MASK_RXPKT_TYPE_8821C) << BIT_SHIFT_RXPKT_TYPE_8821C)
+#define BITS_RXPKT_TYPE_8821C \
+ (BIT_MASK_RXPKT_TYPE_8821C << BIT_SHIFT_RXPKT_TYPE_8821C)
+#define BIT_CLEAR_RXPKT_TYPE_8821C(x) ((x) & (~BITS_RXPKT_TYPE_8821C))
+#define BIT_GET_RXPKT_TYPE_8821C(x) \
+ (((x) >> BIT_SHIFT_RXPKT_TYPE_8821C) & BIT_MASK_RXPKT_TYPE_8821C)
+#define BIT_SET_RXPKT_TYPE_8821C(x, v) \
+ (BIT_CLEAR_RXPKT_TYPE_8821C(x) | BIT_RXPKT_TYPE_8821C(v))
#define BIT_TXACT_IND_8821C BIT(1)
#define BIT_RXACT_IND_8821C BIT(0)
-/* 2 REG_WMAC_BACAM_RPMEN_8821C */
-
-#define BIT_SHIFT_BITMAP_SSNBK_COUNTER_8821C 2
-#define BIT_MASK_BITMAP_SSNBK_COUNTER_8821C 0x3f
-#define BIT_BITMAP_SSNBK_COUNTER_8821C(x) (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8821C) << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8821C)
-#define BIT_GET_BITMAP_SSNBK_COUNTER_8821C(x) (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8821C) & BIT_MASK_BITMAP_SSNBK_COUNTER_8821C)
-
-#define BIT_BITMAP_EN_8821C BIT(1)
-#define BIT_WMAC_BACAM_RPMEN_8821C BIT(0)
-
-/* 2 REG_LBDLY_8821C (LOOPBACK DELAY REGISTER) */
+/* 2 REG_WMAC_BITMAP_CTL_8821C */
+#define BIT_BITMAP_VO_8821C BIT(7)
+#define BIT_BITMAP_VI_8821C BIT(6)
+#define BIT_BITMAP_BE_8821C BIT(5)
+#define BIT_BITMAP_BK_8821C BIT(4)
-#define BIT_SHIFT_LBDLY_8821C 0
-#define BIT_MASK_LBDLY_8821C 0x1f
-#define BIT_LBDLY_8821C(x) (((x) & BIT_MASK_LBDLY_8821C) << BIT_SHIFT_LBDLY_8821C)
-#define BIT_GET_LBDLY_8821C(x) (((x) >> BIT_SHIFT_LBDLY_8821C) & BIT_MASK_LBDLY_8821C)
+#define BIT_SHIFT_BITMAP_CONDITION_8821C 2
+#define BIT_MASK_BITMAP_CONDITION_8821C 0x3
+#define BIT_BITMAP_CONDITION_8821C(x) \
+ (((x) & BIT_MASK_BITMAP_CONDITION_8821C) \
+ << BIT_SHIFT_BITMAP_CONDITION_8821C)
+#define BITS_BITMAP_CONDITION_8821C \
+ (BIT_MASK_BITMAP_CONDITION_8821C << BIT_SHIFT_BITMAP_CONDITION_8821C)
+#define BIT_CLEAR_BITMAP_CONDITION_8821C(x) \
+ ((x) & (~BITS_BITMAP_CONDITION_8821C))
+#define BIT_GET_BITMAP_CONDITION_8821C(x) \
+ (((x) >> BIT_SHIFT_BITMAP_CONDITION_8821C) & \
+ BIT_MASK_BITMAP_CONDITION_8821C)
+#define BIT_SET_BITMAP_CONDITION_8821C(x, v) \
+ (BIT_CLEAR_BITMAP_CONDITION_8821C(x) | BIT_BITMAP_CONDITION_8821C(v))
+#define BIT_BITMAP_SSNBK_COUNTER_CLR_8821C BIT(1)
+#define BIT_BITMAP_FORCE_8821C BIT(0)
/* 2 REG_RXERR_RPT_8821C (RX ERROR REPORT REGISTER) */
#define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8821C 28
#define BIT_MASK_RXERR_RPT_SEL_V1_3_0_8821C 0xf
-#define BIT_RXERR_RPT_SEL_V1_3_0_8821C(x) (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8821C) << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8821C)
-#define BIT_GET_RXERR_RPT_SEL_V1_3_0_8821C(x) (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8821C) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8821C)
+#define BIT_RXERR_RPT_SEL_V1_3_0_8821C(x) \
+ (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8821C) \
+ << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8821C)
+#define BITS_RXERR_RPT_SEL_V1_3_0_8821C \
+ (BIT_MASK_RXERR_RPT_SEL_V1_3_0_8821C \
+ << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8821C)
+#define BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8821C(x) \
+ ((x) & (~BITS_RXERR_RPT_SEL_V1_3_0_8821C))
+#define BIT_GET_RXERR_RPT_SEL_V1_3_0_8821C(x) \
+ (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8821C) & \
+ BIT_MASK_RXERR_RPT_SEL_V1_3_0_8821C)
+#define BIT_SET_RXERR_RPT_SEL_V1_3_0_8821C(x, v) \
+ (BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8821C(x) | \
+ BIT_RXERR_RPT_SEL_V1_3_0_8821C(v))
#define BIT_RXERR_RPT_RST_8821C BIT(27)
#define BIT_RXERR_RPT_SEL_V1_4_8821C BIT(26)
@@ -7916,57 +14856,40 @@
#define BIT_SHIFT_UD_SUB_TYPE_8821C 18
#define BIT_MASK_UD_SUB_TYPE_8821C 0xf
-#define BIT_UD_SUB_TYPE_8821C(x) (((x) & BIT_MASK_UD_SUB_TYPE_8821C) << BIT_SHIFT_UD_SUB_TYPE_8821C)
-#define BIT_GET_UD_SUB_TYPE_8821C(x) (((x) >> BIT_SHIFT_UD_SUB_TYPE_8821C) & BIT_MASK_UD_SUB_TYPE_8821C)
-
+#define BIT_UD_SUB_TYPE_8821C(x) \
+ (((x) & BIT_MASK_UD_SUB_TYPE_8821C) << BIT_SHIFT_UD_SUB_TYPE_8821C)
+#define BITS_UD_SUB_TYPE_8821C \
+ (BIT_MASK_UD_SUB_TYPE_8821C << BIT_SHIFT_UD_SUB_TYPE_8821C)
+#define BIT_CLEAR_UD_SUB_TYPE_8821C(x) ((x) & (~BITS_UD_SUB_TYPE_8821C))
+#define BIT_GET_UD_SUB_TYPE_8821C(x) \
+ (((x) >> BIT_SHIFT_UD_SUB_TYPE_8821C) & BIT_MASK_UD_SUB_TYPE_8821C)
+#define BIT_SET_UD_SUB_TYPE_8821C(x, v) \
+ (BIT_CLEAR_UD_SUB_TYPE_8821C(x) | BIT_UD_SUB_TYPE_8821C(v))
#define BIT_SHIFT_UD_TYPE_8821C 16
#define BIT_MASK_UD_TYPE_8821C 0x3
-#define BIT_UD_TYPE_8821C(x) (((x) & BIT_MASK_UD_TYPE_8821C) << BIT_SHIFT_UD_TYPE_8821C)
-#define BIT_GET_UD_TYPE_8821C(x) (((x) >> BIT_SHIFT_UD_TYPE_8821C) & BIT_MASK_UD_TYPE_8821C)
-
+#define BIT_UD_TYPE_8821C(x) \
+ (((x) & BIT_MASK_UD_TYPE_8821C) << BIT_SHIFT_UD_TYPE_8821C)
+#define BITS_UD_TYPE_8821C (BIT_MASK_UD_TYPE_8821C << BIT_SHIFT_UD_TYPE_8821C)
+#define BIT_CLEAR_UD_TYPE_8821C(x) ((x) & (~BITS_UD_TYPE_8821C))
+#define BIT_GET_UD_TYPE_8821C(x) \
+ (((x) >> BIT_SHIFT_UD_TYPE_8821C) & BIT_MASK_UD_TYPE_8821C)
+#define BIT_SET_UD_TYPE_8821C(x, v) \
+ (BIT_CLEAR_UD_TYPE_8821C(x) | BIT_UD_TYPE_8821C(v))
#define BIT_SHIFT_RPT_COUNTER_8821C 0
#define BIT_MASK_RPT_COUNTER_8821C 0xffff
-#define BIT_RPT_COUNTER_8821C(x) (((x) & BIT_MASK_RPT_COUNTER_8821C) << BIT_SHIFT_RPT_COUNTER_8821C)
-#define BIT_GET_RPT_COUNTER_8821C(x) (((x) >> BIT_SHIFT_RPT_COUNTER_8821C) & BIT_MASK_RPT_COUNTER_8821C)
-
-
-/* 2 REG_WMAC_TRXPTCL_CTL_8821C (WMAC TX/RX PROTOCOL CONTROL REGISTER) */
-
-#define BIT_SHIFT_ACKBA_TYPSEL_8821C (60 & CPU_OPT_WIDTH)
-#define BIT_MASK_ACKBA_TYPSEL_8821C 0xf
-#define BIT_ACKBA_TYPSEL_8821C(x) (((x) & BIT_MASK_ACKBA_TYPSEL_8821C) << BIT_SHIFT_ACKBA_TYPSEL_8821C)
-#define BIT_GET_ACKBA_TYPSEL_8821C(x) (((x) >> BIT_SHIFT_ACKBA_TYPSEL_8821C) & BIT_MASK_ACKBA_TYPSEL_8821C)
-
-
-#define BIT_SHIFT_ACKBA_ACKPCHK_8821C (56 & CPU_OPT_WIDTH)
-#define BIT_MASK_ACKBA_ACKPCHK_8821C 0xf
-#define BIT_ACKBA_ACKPCHK_8821C(x) (((x) & BIT_MASK_ACKBA_ACKPCHK_8821C) << BIT_SHIFT_ACKBA_ACKPCHK_8821C)
-#define BIT_GET_ACKBA_ACKPCHK_8821C(x) (((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8821C) & BIT_MASK_ACKBA_ACKPCHK_8821C)
-
-
-#define BIT_SHIFT_ACKBAR_TYPESEL_8821C (48 & CPU_OPT_WIDTH)
-#define BIT_MASK_ACKBAR_TYPESEL_8821C 0xff
-#define BIT_ACKBAR_TYPESEL_8821C(x) (((x) & BIT_MASK_ACKBAR_TYPESEL_8821C) << BIT_SHIFT_ACKBAR_TYPESEL_8821C)
-#define BIT_GET_ACKBAR_TYPESEL_8821C(x) (((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8821C) & BIT_MASK_ACKBAR_TYPESEL_8821C)
-
-
-#define BIT_SHIFT_ACKBAR_ACKPCHK_8821C (44 & CPU_OPT_WIDTH)
-#define BIT_MASK_ACKBAR_ACKPCHK_8821C 0xf
-#define BIT_ACKBAR_ACKPCHK_8821C(x) (((x) & BIT_MASK_ACKBAR_ACKPCHK_8821C) << BIT_SHIFT_ACKBAR_ACKPCHK_8821C)
-#define BIT_GET_ACKBAR_ACKPCHK_8821C(x) (((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8821C) & BIT_MASK_ACKBAR_ACKPCHK_8821C)
-
-#define BIT_RXBA_IGNOREA2_8821C BIT(42)
-#define BIT_EN_SAVE_ALL_TXOPADDR_8821C BIT(41)
-#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV_8821C BIT(40)
-#define BIT_DIS_TXBA_AMPDUFCSERR_8821C BIT(39)
-#define BIT_DIS_TXBA_RXBARINFULL_8821C BIT(38)
-#define BIT_DIS_TXCFE_INFULL_8821C BIT(37)
-#define BIT_DIS_TXCTS_INFULL_8821C BIT(36)
-#define BIT_EN_TXACKBA_IN_TX_RDG_8821C BIT(35)
-#define BIT_EN_TXACKBA_IN_TXOP_8821C BIT(34)
-#define BIT_EN_TXCTS_IN_RXNAV_8821C BIT(33)
+#define BIT_RPT_COUNTER_8821C(x) \
+ (((x) & BIT_MASK_RPT_COUNTER_8821C) << BIT_SHIFT_RPT_COUNTER_8821C)
+#define BITS_RPT_COUNTER_8821C \
+ (BIT_MASK_RPT_COUNTER_8821C << BIT_SHIFT_RPT_COUNTER_8821C)
+#define BIT_CLEAR_RPT_COUNTER_8821C(x) ((x) & (~BITS_RPT_COUNTER_8821C))
+#define BIT_GET_RPT_COUNTER_8821C(x) \
+ (((x) >> BIT_SHIFT_RPT_COUNTER_8821C) & BIT_MASK_RPT_COUNTER_8821C)
+#define BIT_SET_RPT_COUNTER_8821C(x, v) \
+ (BIT_CLEAR_RPT_COUNTER_8821C(x) | BIT_RPT_COUNTER_8821C(v))
+
+/* 2 REG_WMAC_TRXPTCL_CTL_8821C (WMAC TX/RX PROTOCOL CONTROL REGISTER) */
#define BIT_EN_TXCTS_INTXOP_8821C BIT(32)
#define BIT_BLK_EDCA_BBSLP_8821C BIT(31)
#define BIT_BLK_EDCA_BBSBY_8821C BIT(30)
@@ -7979,8 +14902,15 @@
#define BIT_SHIFT_RESP_CHNBUSY_8821C 20
#define BIT_MASK_RESP_CHNBUSY_8821C 0x3
-#define BIT_RESP_CHNBUSY_8821C(x) (((x) & BIT_MASK_RESP_CHNBUSY_8821C) << BIT_SHIFT_RESP_CHNBUSY_8821C)
-#define BIT_GET_RESP_CHNBUSY_8821C(x) (((x) >> BIT_SHIFT_RESP_CHNBUSY_8821C) & BIT_MASK_RESP_CHNBUSY_8821C)
+#define BIT_RESP_CHNBUSY_8821C(x) \
+ (((x) & BIT_MASK_RESP_CHNBUSY_8821C) << BIT_SHIFT_RESP_CHNBUSY_8821C)
+#define BITS_RESP_CHNBUSY_8821C \
+ (BIT_MASK_RESP_CHNBUSY_8821C << BIT_SHIFT_RESP_CHNBUSY_8821C)
+#define BIT_CLEAR_RESP_CHNBUSY_8821C(x) ((x) & (~BITS_RESP_CHNBUSY_8821C))
+#define BIT_GET_RESP_CHNBUSY_8821C(x) \
+ (((x) >> BIT_SHIFT_RESP_CHNBUSY_8821C) & BIT_MASK_RESP_CHNBUSY_8821C)
+#define BIT_SET_RESP_CHNBUSY_8821C(x, v) \
+ (BIT_CLEAR_RESP_CHNBUSY_8821C(x) | BIT_RESP_CHNBUSY_8821C(v))
#define BIT_RESP_DCTS_EN_8821C BIT(19)
#define BIT_RESP_DCFE_EN_8821C BIT(18)
@@ -7992,29 +14922,129 @@
#define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8821C 10
#define BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8821C 0x7
-#define BIT_R_WMAC_SECOND_CCA_TIMER_8821C(x) (((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8821C) << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8821C)
-#define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8821C) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8821C)
-
+#define BIT_R_WMAC_SECOND_CCA_TIMER_8821C(x) \
+ (((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8821C) \
+ << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8821C)
+#define BITS_R_WMAC_SECOND_CCA_TIMER_8821C \
+ (BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8821C \
+ << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8821C)
+#define BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8821C(x) \
+ ((x) & (~BITS_R_WMAC_SECOND_CCA_TIMER_8821C))
+#define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8821C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8821C) & \
+ BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8821C)
+#define BIT_SET_R_WMAC_SECOND_CCA_TIMER_8821C(x, v) \
+ (BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8821C(x) | \
+ BIT_R_WMAC_SECOND_CCA_TIMER_8821C(v))
#define BIT_SHIFT_RFMOD_8821C 7
#define BIT_MASK_RFMOD_8821C 0x3
-#define BIT_RFMOD_8821C(x) (((x) & BIT_MASK_RFMOD_8821C) << BIT_SHIFT_RFMOD_8821C)
-#define BIT_GET_RFMOD_8821C(x) (((x) >> BIT_SHIFT_RFMOD_8821C) & BIT_MASK_RFMOD_8821C)
-
+#define BIT_RFMOD_8821C(x) \
+ (((x) & BIT_MASK_RFMOD_8821C) << BIT_SHIFT_RFMOD_8821C)
+#define BITS_RFMOD_8821C (BIT_MASK_RFMOD_8821C << BIT_SHIFT_RFMOD_8821C)
+#define BIT_CLEAR_RFMOD_8821C(x) ((x) & (~BITS_RFMOD_8821C))
+#define BIT_GET_RFMOD_8821C(x) \
+ (((x) >> BIT_SHIFT_RFMOD_8821C) & BIT_MASK_RFMOD_8821C)
+#define BIT_SET_RFMOD_8821C(x, v) \
+ (BIT_CLEAR_RFMOD_8821C(x) | BIT_RFMOD_8821C(v))
#define BIT_SHIFT_RESP_CTS_DYNBW_SEL_8821C 5
#define BIT_MASK_RESP_CTS_DYNBW_SEL_8821C 0x3
-#define BIT_RESP_CTS_DYNBW_SEL_8821C(x) (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8821C) << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8821C)
-#define BIT_GET_RESP_CTS_DYNBW_SEL_8821C(x) (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8821C) & BIT_MASK_RESP_CTS_DYNBW_SEL_8821C)
+#define BIT_RESP_CTS_DYNBW_SEL_8821C(x) \
+ (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8821C) \
+ << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8821C)
+#define BITS_RESP_CTS_DYNBW_SEL_8821C \
+ (BIT_MASK_RESP_CTS_DYNBW_SEL_8821C \
+ << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8821C)
+#define BIT_CLEAR_RESP_CTS_DYNBW_SEL_8821C(x) \
+ ((x) & (~BITS_RESP_CTS_DYNBW_SEL_8821C))
+#define BIT_GET_RESP_CTS_DYNBW_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8821C) & \
+ BIT_MASK_RESP_CTS_DYNBW_SEL_8821C)
+#define BIT_SET_RESP_CTS_DYNBW_SEL_8821C(x, v) \
+ (BIT_CLEAR_RESP_CTS_DYNBW_SEL_8821C(x) | \
+ BIT_RESP_CTS_DYNBW_SEL_8821C(v))
#define BIT_DLY_TX_WAIT_RXANTSEL_8821C BIT(4)
#define BIT_TXRESP_BY_RXANTSEL_8821C BIT(3)
#define BIT_SHIFT_ORIG_DCTS_CHK_8821C 0
#define BIT_MASK_ORIG_DCTS_CHK_8821C 0x3
-#define BIT_ORIG_DCTS_CHK_8821C(x) (((x) & BIT_MASK_ORIG_DCTS_CHK_8821C) << BIT_SHIFT_ORIG_DCTS_CHK_8821C)
-#define BIT_GET_ORIG_DCTS_CHK_8821C(x) (((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8821C) & BIT_MASK_ORIG_DCTS_CHK_8821C)
-
+#define BIT_ORIG_DCTS_CHK_8821C(x) \
+ (((x) & BIT_MASK_ORIG_DCTS_CHK_8821C) << BIT_SHIFT_ORIG_DCTS_CHK_8821C)
+#define BITS_ORIG_DCTS_CHK_8821C \
+ (BIT_MASK_ORIG_DCTS_CHK_8821C << BIT_SHIFT_ORIG_DCTS_CHK_8821C)
+#define BIT_CLEAR_ORIG_DCTS_CHK_8821C(x) ((x) & (~BITS_ORIG_DCTS_CHK_8821C))
+#define BIT_GET_ORIG_DCTS_CHK_8821C(x) \
+ (((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8821C) & BIT_MASK_ORIG_DCTS_CHK_8821C)
+#define BIT_SET_ORIG_DCTS_CHK_8821C(x, v) \
+ (BIT_CLEAR_ORIG_DCTS_CHK_8821C(x) | BIT_ORIG_DCTS_CHK_8821C(v))
+
+/* 2 REG_WMAC_TRXPTCL_CTL_H_8821C */
+
+#define BIT_SHIFT_ACKBA_TYPSEL_8821C 28
+#define BIT_MASK_ACKBA_TYPSEL_8821C 0xf
+#define BIT_ACKBA_TYPSEL_8821C(x) \
+ (((x) & BIT_MASK_ACKBA_TYPSEL_8821C) << BIT_SHIFT_ACKBA_TYPSEL_8821C)
+#define BITS_ACKBA_TYPSEL_8821C \
+ (BIT_MASK_ACKBA_TYPSEL_8821C << BIT_SHIFT_ACKBA_TYPSEL_8821C)
+#define BIT_CLEAR_ACKBA_TYPSEL_8821C(x) ((x) & (~BITS_ACKBA_TYPSEL_8821C))
+#define BIT_GET_ACKBA_TYPSEL_8821C(x) \
+ (((x) >> BIT_SHIFT_ACKBA_TYPSEL_8821C) & BIT_MASK_ACKBA_TYPSEL_8821C)
+#define BIT_SET_ACKBA_TYPSEL_8821C(x, v) \
+ (BIT_CLEAR_ACKBA_TYPSEL_8821C(x) | BIT_ACKBA_TYPSEL_8821C(v))
+
+#define BIT_SHIFT_ACKBA_ACKPCHK_8821C 24
+#define BIT_MASK_ACKBA_ACKPCHK_8821C 0xf
+#define BIT_ACKBA_ACKPCHK_8821C(x) \
+ (((x) & BIT_MASK_ACKBA_ACKPCHK_8821C) << BIT_SHIFT_ACKBA_ACKPCHK_8821C)
+#define BITS_ACKBA_ACKPCHK_8821C \
+ (BIT_MASK_ACKBA_ACKPCHK_8821C << BIT_SHIFT_ACKBA_ACKPCHK_8821C)
+#define BIT_CLEAR_ACKBA_ACKPCHK_8821C(x) ((x) & (~BITS_ACKBA_ACKPCHK_8821C))
+#define BIT_GET_ACKBA_ACKPCHK_8821C(x) \
+ (((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8821C) & BIT_MASK_ACKBA_ACKPCHK_8821C)
+#define BIT_SET_ACKBA_ACKPCHK_8821C(x, v) \
+ (BIT_CLEAR_ACKBA_ACKPCHK_8821C(x) | BIT_ACKBA_ACKPCHK_8821C(v))
+
+#define BIT_SHIFT_ACKBAR_TYPESEL_8821C 16
+#define BIT_MASK_ACKBAR_TYPESEL_8821C 0xff
+#define BIT_ACKBAR_TYPESEL_8821C(x) \
+ (((x) & BIT_MASK_ACKBAR_TYPESEL_8821C) \
+ << BIT_SHIFT_ACKBAR_TYPESEL_8821C)
+#define BITS_ACKBAR_TYPESEL_8821C \
+ (BIT_MASK_ACKBAR_TYPESEL_8821C << BIT_SHIFT_ACKBAR_TYPESEL_8821C)
+#define BIT_CLEAR_ACKBAR_TYPESEL_8821C(x) ((x) & (~BITS_ACKBAR_TYPESEL_8821C))
+#define BIT_GET_ACKBAR_TYPESEL_8821C(x) \
+ (((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8821C) & \
+ BIT_MASK_ACKBAR_TYPESEL_8821C)
+#define BIT_SET_ACKBAR_TYPESEL_8821C(x, v) \
+ (BIT_CLEAR_ACKBAR_TYPESEL_8821C(x) | BIT_ACKBAR_TYPESEL_8821C(v))
+
+#define BIT_SHIFT_ACKBAR_ACKPCHK_8821C 12
+#define BIT_MASK_ACKBAR_ACKPCHK_8821C 0xf
+#define BIT_ACKBAR_ACKPCHK_8821C(x) \
+ (((x) & BIT_MASK_ACKBAR_ACKPCHK_8821C) \
+ << BIT_SHIFT_ACKBAR_ACKPCHK_8821C)
+#define BITS_ACKBAR_ACKPCHK_8821C \
+ (BIT_MASK_ACKBAR_ACKPCHK_8821C << BIT_SHIFT_ACKBAR_ACKPCHK_8821C)
+#define BIT_CLEAR_ACKBAR_ACKPCHK_8821C(x) ((x) & (~BITS_ACKBAR_ACKPCHK_8821C))
+#define BIT_GET_ACKBAR_ACKPCHK_8821C(x) \
+ (((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8821C) & \
+ BIT_MASK_ACKBAR_ACKPCHK_8821C)
+#define BIT_SET_ACKBAR_ACKPCHK_8821C(x, v) \
+ (BIT_CLEAR_ACKBAR_ACKPCHK_8821C(x) | BIT_ACKBAR_ACKPCHK_8821C(v))
+
+#define BIT_RXBA_IGNOREA2_V1_8821C BIT(10)
+#define BIT_EN_SAVE_ALL_TXOPADDR_V1_8821C BIT(9)
+#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV_V1_8821C BIT(8)
+#define BIT_DIS_TXBA_AMPDUFCSERR_V1_8821C BIT(7)
+#define BIT_DIS_TXBA_RXBARINFULL_V1_8821C BIT(6)
+#define BIT_DIS_TXCFE_INFULL_V1_8821C BIT(5)
+#define BIT_DIS_TXCTS_INFULL_V1_8821C BIT(4)
+#define BIT_EN_TXACKBA_IN_TX_RDG_V1_8821C BIT(3)
+#define BIT_EN_TXACKBA_IN_TXOP_V1_8821C BIT(2)
+#define BIT_EN_TXCTS_IN_RXNAV_V1_8821C BIT(1)
+#define BIT_EN_TXCTS_INTXOP_V1_8821C BIT(0)
/* 2 REG_CAMCMD_8821C (CAM COMMAND REGISTER) */
#define BIT_SECCAM_POLLING_8821C BIT(31)
@@ -8024,25 +15054,45 @@
#define BIT_SHIFT_SECCAM_ADDR_V2_8821C 0
#define BIT_MASK_SECCAM_ADDR_V2_8821C 0x3ff
-#define BIT_SECCAM_ADDR_V2_8821C(x) (((x) & BIT_MASK_SECCAM_ADDR_V2_8821C) << BIT_SHIFT_SECCAM_ADDR_V2_8821C)
-#define BIT_GET_SECCAM_ADDR_V2_8821C(x) (((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8821C) & BIT_MASK_SECCAM_ADDR_V2_8821C)
-
+#define BIT_SECCAM_ADDR_V2_8821C(x) \
+ (((x) & BIT_MASK_SECCAM_ADDR_V2_8821C) \
+ << BIT_SHIFT_SECCAM_ADDR_V2_8821C)
+#define BITS_SECCAM_ADDR_V2_8821C \
+ (BIT_MASK_SECCAM_ADDR_V2_8821C << BIT_SHIFT_SECCAM_ADDR_V2_8821C)
+#define BIT_CLEAR_SECCAM_ADDR_V2_8821C(x) ((x) & (~BITS_SECCAM_ADDR_V2_8821C))
+#define BIT_GET_SECCAM_ADDR_V2_8821C(x) \
+ (((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8821C) & \
+ BIT_MASK_SECCAM_ADDR_V2_8821C)
+#define BIT_SET_SECCAM_ADDR_V2_8821C(x, v) \
+ (BIT_CLEAR_SECCAM_ADDR_V2_8821C(x) | BIT_SECCAM_ADDR_V2_8821C(v))
/* 2 REG_CAMWRITE_8821C (CAM WRITE REGISTER) */
#define BIT_SHIFT_CAMW_DATA_8821C 0
#define BIT_MASK_CAMW_DATA_8821C 0xffffffffL
-#define BIT_CAMW_DATA_8821C(x) (((x) & BIT_MASK_CAMW_DATA_8821C) << BIT_SHIFT_CAMW_DATA_8821C)
-#define BIT_GET_CAMW_DATA_8821C(x) (((x) >> BIT_SHIFT_CAMW_DATA_8821C) & BIT_MASK_CAMW_DATA_8821C)
-
+#define BIT_CAMW_DATA_8821C(x) \
+ (((x) & BIT_MASK_CAMW_DATA_8821C) << BIT_SHIFT_CAMW_DATA_8821C)
+#define BITS_CAMW_DATA_8821C \
+ (BIT_MASK_CAMW_DATA_8821C << BIT_SHIFT_CAMW_DATA_8821C)
+#define BIT_CLEAR_CAMW_DATA_8821C(x) ((x) & (~BITS_CAMW_DATA_8821C))
+#define BIT_GET_CAMW_DATA_8821C(x) \
+ (((x) >> BIT_SHIFT_CAMW_DATA_8821C) & BIT_MASK_CAMW_DATA_8821C)
+#define BIT_SET_CAMW_DATA_8821C(x, v) \
+ (BIT_CLEAR_CAMW_DATA_8821C(x) | BIT_CAMW_DATA_8821C(v))
/* 2 REG_CAMREAD_8821C (CAM READ REGISTER) */
#define BIT_SHIFT_CAMR_DATA_8821C 0
#define BIT_MASK_CAMR_DATA_8821C 0xffffffffL
-#define BIT_CAMR_DATA_8821C(x) (((x) & BIT_MASK_CAMR_DATA_8821C) << BIT_SHIFT_CAMR_DATA_8821C)
-#define BIT_GET_CAMR_DATA_8821C(x) (((x) >> BIT_SHIFT_CAMR_DATA_8821C) & BIT_MASK_CAMR_DATA_8821C)
-
+#define BIT_CAMR_DATA_8821C(x) \
+ (((x) & BIT_MASK_CAMR_DATA_8821C) << BIT_SHIFT_CAMR_DATA_8821C)
+#define BITS_CAMR_DATA_8821C \
+ (BIT_MASK_CAMR_DATA_8821C << BIT_SHIFT_CAMR_DATA_8821C)
+#define BIT_CLEAR_CAMR_DATA_8821C(x) ((x) & (~BITS_CAMR_DATA_8821C))
+#define BIT_GET_CAMR_DATA_8821C(x) \
+ (((x) >> BIT_SHIFT_CAMR_DATA_8821C) & BIT_MASK_CAMR_DATA_8821C)
+#define BIT_SET_CAMR_DATA_8821C(x, v) \
+ (BIT_CLEAR_CAMR_DATA_8821C(x) | BIT_CAMR_DATA_8821C(v))
/* 2 REG_CAMDBG_8821C (CAM DEBUG REGISTER) */
#define BIT_SECCAM_INFO_8821C BIT(31)
@@ -8050,38 +15100,53 @@
#define BIT_SHIFT_CAMDBG_SEC_TYPE_8821C 12
#define BIT_MASK_CAMDBG_SEC_TYPE_8821C 0x7
-#define BIT_CAMDBG_SEC_TYPE_8821C(x) (((x) & BIT_MASK_CAMDBG_SEC_TYPE_8821C) << BIT_SHIFT_CAMDBG_SEC_TYPE_8821C)
-#define BIT_GET_CAMDBG_SEC_TYPE_8821C(x) (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8821C) & BIT_MASK_CAMDBG_SEC_TYPE_8821C)
+#define BIT_CAMDBG_SEC_TYPE_8821C(x) \
+ (((x) & BIT_MASK_CAMDBG_SEC_TYPE_8821C) \
+ << BIT_SHIFT_CAMDBG_SEC_TYPE_8821C)
+#define BITS_CAMDBG_SEC_TYPE_8821C \
+ (BIT_MASK_CAMDBG_SEC_TYPE_8821C << BIT_SHIFT_CAMDBG_SEC_TYPE_8821C)
+#define BIT_CLEAR_CAMDBG_SEC_TYPE_8821C(x) ((x) & (~BITS_CAMDBG_SEC_TYPE_8821C))
+#define BIT_GET_CAMDBG_SEC_TYPE_8821C(x) \
+ (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8821C) & \
+ BIT_MASK_CAMDBG_SEC_TYPE_8821C)
+#define BIT_SET_CAMDBG_SEC_TYPE_8821C(x, v) \
+ (BIT_CLEAR_CAMDBG_SEC_TYPE_8821C(x) | BIT_CAMDBG_SEC_TYPE_8821C(v))
#define BIT_CAMDBG_EXT_SECTYPE_8821C BIT(11)
#define BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8821C 5
#define BIT_MASK_CAMDBG_MIC_KEY_IDX_8821C 0x1f
-#define BIT_CAMDBG_MIC_KEY_IDX_8821C(x) (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8821C) << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8821C)
-#define BIT_GET_CAMDBG_MIC_KEY_IDX_8821C(x) (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8821C) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8821C)
-
+#define BIT_CAMDBG_MIC_KEY_IDX_8821C(x) \
+ (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8821C) \
+ << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8821C)
+#define BITS_CAMDBG_MIC_KEY_IDX_8821C \
+ (BIT_MASK_CAMDBG_MIC_KEY_IDX_8821C \
+ << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8821C)
+#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8821C(x) \
+ ((x) & (~BITS_CAMDBG_MIC_KEY_IDX_8821C))
+#define BIT_GET_CAMDBG_MIC_KEY_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8821C) & \
+ BIT_MASK_CAMDBG_MIC_KEY_IDX_8821C)
+#define BIT_SET_CAMDBG_MIC_KEY_IDX_8821C(x, v) \
+ (BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8821C(x) | \
+ BIT_CAMDBG_MIC_KEY_IDX_8821C(v))
#define BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8821C 0
#define BIT_MASK_CAMDBG_SEC_KEY_IDX_8821C 0x1f
-#define BIT_CAMDBG_SEC_KEY_IDX_8821C(x) (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8821C) << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8821C)
-#define BIT_GET_CAMDBG_SEC_KEY_IDX_8821C(x) (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8821C) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8821C)
-
-
-/* 2 REG_RXFILTER_ACTION_1_8821C */
-
-#define BIT_SHIFT_RXFILTER_ACTION_1_8821C 0
-#define BIT_MASK_RXFILTER_ACTION_1_8821C 0xff
-#define BIT_RXFILTER_ACTION_1_8821C(x) (((x) & BIT_MASK_RXFILTER_ACTION_1_8821C) << BIT_SHIFT_RXFILTER_ACTION_1_8821C)
-#define BIT_GET_RXFILTER_ACTION_1_8821C(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8821C) & BIT_MASK_RXFILTER_ACTION_1_8821C)
-
-
-/* 2 REG_RXFILTER_CATEGORY_1_8821C */
-
-#define BIT_SHIFT_RXFILTER_CATEGORY_1_8821C 0
-#define BIT_MASK_RXFILTER_CATEGORY_1_8821C 0xff
-#define BIT_RXFILTER_CATEGORY_1_8821C(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_1_8821C) << BIT_SHIFT_RXFILTER_CATEGORY_1_8821C)
-#define BIT_GET_RXFILTER_CATEGORY_1_8821C(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8821C) & BIT_MASK_RXFILTER_CATEGORY_1_8821C)
-
+#define BIT_CAMDBG_SEC_KEY_IDX_8821C(x) \
+ (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8821C) \
+ << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8821C)
+#define BITS_CAMDBG_SEC_KEY_IDX_8821C \
+ (BIT_MASK_CAMDBG_SEC_KEY_IDX_8821C \
+ << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8821C)
+#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8821C(x) \
+ ((x) & (~BITS_CAMDBG_SEC_KEY_IDX_8821C))
+#define BIT_GET_CAMDBG_SEC_KEY_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8821C) & \
+ BIT_MASK_CAMDBG_SEC_KEY_IDX_8821C)
+#define BIT_SET_CAMDBG_SEC_KEY_IDX_8821C(x, v) \
+ (BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8821C(x) | \
+ BIT_CAMDBG_SEC_KEY_IDX_8821C(v))
/* 2 REG_SECCFG_8821C (SECURITY CONFIGURATION REGISTER) */
#define BIT_DIS_GCLK_WAPI_8821C BIT(15)
@@ -8100,55 +15165,113 @@
#define BIT_RXUHUSEDK_8821C BIT(1)
#define BIT_TXUHUSEDK_8821C BIT(0)
-/* 2 REG_RXFILTER_ACTION_3_8821C */
+/* 2 REG_RXFILTER_CATEGORY_1_8821C */
-#define BIT_SHIFT_RXFILTER_ACTION_3_8821C 0
-#define BIT_MASK_RXFILTER_ACTION_3_8821C 0xff
-#define BIT_RXFILTER_ACTION_3_8821C(x) (((x) & BIT_MASK_RXFILTER_ACTION_3_8821C) << BIT_SHIFT_RXFILTER_ACTION_3_8821C)
-#define BIT_GET_RXFILTER_ACTION_3_8821C(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8821C) & BIT_MASK_RXFILTER_ACTION_3_8821C)
+#define BIT_SHIFT_RXFILTER_CATEGORY_1_8821C 0
+#define BIT_MASK_RXFILTER_CATEGORY_1_8821C 0xff
+#define BIT_RXFILTER_CATEGORY_1_8821C(x) \
+ (((x) & BIT_MASK_RXFILTER_CATEGORY_1_8821C) \
+ << BIT_SHIFT_RXFILTER_CATEGORY_1_8821C)
+#define BITS_RXFILTER_CATEGORY_1_8821C \
+ (BIT_MASK_RXFILTER_CATEGORY_1_8821C \
+ << BIT_SHIFT_RXFILTER_CATEGORY_1_8821C)
+#define BIT_CLEAR_RXFILTER_CATEGORY_1_8821C(x) \
+ ((x) & (~BITS_RXFILTER_CATEGORY_1_8821C))
+#define BIT_GET_RXFILTER_CATEGORY_1_8821C(x) \
+ (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8821C) & \
+ BIT_MASK_RXFILTER_CATEGORY_1_8821C)
+#define BIT_SET_RXFILTER_CATEGORY_1_8821C(x, v) \
+ (BIT_CLEAR_RXFILTER_CATEGORY_1_8821C(x) | \
+ BIT_RXFILTER_CATEGORY_1_8821C(v))
+/* 2 REG_RXFILTER_ACTION_1_8821C */
-/* 2 REG_RXFILTER_CATEGORY_3_8821C */
+#define BIT_SHIFT_RXFILTER_ACTION_1_8821C 0
+#define BIT_MASK_RXFILTER_ACTION_1_8821C 0xff
+#define BIT_RXFILTER_ACTION_1_8821C(x) \
+ (((x) & BIT_MASK_RXFILTER_ACTION_1_8821C) \
+ << BIT_SHIFT_RXFILTER_ACTION_1_8821C)
+#define BITS_RXFILTER_ACTION_1_8821C \
+ (BIT_MASK_RXFILTER_ACTION_1_8821C << BIT_SHIFT_RXFILTER_ACTION_1_8821C)
+#define BIT_CLEAR_RXFILTER_ACTION_1_8821C(x) \
+ ((x) & (~BITS_RXFILTER_ACTION_1_8821C))
+#define BIT_GET_RXFILTER_ACTION_1_8821C(x) \
+ (((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8821C) & \
+ BIT_MASK_RXFILTER_ACTION_1_8821C)
+#define BIT_SET_RXFILTER_ACTION_1_8821C(x, v) \
+ (BIT_CLEAR_RXFILTER_ACTION_1_8821C(x) | BIT_RXFILTER_ACTION_1_8821C(v))
-#define BIT_SHIFT_RXFILTER_CATEGORY_3_8821C 0
-#define BIT_MASK_RXFILTER_CATEGORY_3_8821C 0xff
-#define BIT_RXFILTER_CATEGORY_3_8821C(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_3_8821C) << BIT_SHIFT_RXFILTER_CATEGORY_3_8821C)
-#define BIT_GET_RXFILTER_CATEGORY_3_8821C(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8821C) & BIT_MASK_RXFILTER_CATEGORY_3_8821C)
+/* 2 REG_RXFILTER_CATEGORY_2_8821C */
+#define BIT_SHIFT_RXFILTER_CATEGORY_2_8821C 0
+#define BIT_MASK_RXFILTER_CATEGORY_2_8821C 0xff
+#define BIT_RXFILTER_CATEGORY_2_8821C(x) \
+ (((x) & BIT_MASK_RXFILTER_CATEGORY_2_8821C) \
+ << BIT_SHIFT_RXFILTER_CATEGORY_2_8821C)
+#define BITS_RXFILTER_CATEGORY_2_8821C \
+ (BIT_MASK_RXFILTER_CATEGORY_2_8821C \
+ << BIT_SHIFT_RXFILTER_CATEGORY_2_8821C)
+#define BIT_CLEAR_RXFILTER_CATEGORY_2_8821C(x) \
+ ((x) & (~BITS_RXFILTER_CATEGORY_2_8821C))
+#define BIT_GET_RXFILTER_CATEGORY_2_8821C(x) \
+ (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8821C) & \
+ BIT_MASK_RXFILTER_CATEGORY_2_8821C)
+#define BIT_SET_RXFILTER_CATEGORY_2_8821C(x, v) \
+ (BIT_CLEAR_RXFILTER_CATEGORY_2_8821C(x) | \
+ BIT_RXFILTER_CATEGORY_2_8821C(v))
/* 2 REG_RXFILTER_ACTION_2_8821C */
#define BIT_SHIFT_RXFILTER_ACTION_2_8821C 0
#define BIT_MASK_RXFILTER_ACTION_2_8821C 0xff
-#define BIT_RXFILTER_ACTION_2_8821C(x) (((x) & BIT_MASK_RXFILTER_ACTION_2_8821C) << BIT_SHIFT_RXFILTER_ACTION_2_8821C)
-#define BIT_GET_RXFILTER_ACTION_2_8821C(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8821C) & BIT_MASK_RXFILTER_ACTION_2_8821C)
+#define BIT_RXFILTER_ACTION_2_8821C(x) \
+ (((x) & BIT_MASK_RXFILTER_ACTION_2_8821C) \
+ << BIT_SHIFT_RXFILTER_ACTION_2_8821C)
+#define BITS_RXFILTER_ACTION_2_8821C \
+ (BIT_MASK_RXFILTER_ACTION_2_8821C << BIT_SHIFT_RXFILTER_ACTION_2_8821C)
+#define BIT_CLEAR_RXFILTER_ACTION_2_8821C(x) \
+ ((x) & (~BITS_RXFILTER_ACTION_2_8821C))
+#define BIT_GET_RXFILTER_ACTION_2_8821C(x) \
+ (((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8821C) & \
+ BIT_MASK_RXFILTER_ACTION_2_8821C)
+#define BIT_SET_RXFILTER_ACTION_2_8821C(x, v) \
+ (BIT_CLEAR_RXFILTER_ACTION_2_8821C(x) | BIT_RXFILTER_ACTION_2_8821C(v))
+/* 2 REG_RXFILTER_CATEGORY_3_8821C */
-/* 2 REG_RXFILTER_CATEGORY_2_8821C */
-
-#define BIT_SHIFT_RXFILTER_CATEGORY_2_8821C 0
-#define BIT_MASK_RXFILTER_CATEGORY_2_8821C 0xff
-#define BIT_RXFILTER_CATEGORY_2_8821C(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_2_8821C) << BIT_SHIFT_RXFILTER_CATEGORY_2_8821C)
-#define BIT_GET_RXFILTER_CATEGORY_2_8821C(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8821C) & BIT_MASK_RXFILTER_CATEGORY_2_8821C)
+#define BIT_SHIFT_RXFILTER_CATEGORY_3_8821C 0
+#define BIT_MASK_RXFILTER_CATEGORY_3_8821C 0xff
+#define BIT_RXFILTER_CATEGORY_3_8821C(x) \
+ (((x) & BIT_MASK_RXFILTER_CATEGORY_3_8821C) \
+ << BIT_SHIFT_RXFILTER_CATEGORY_3_8821C)
+#define BITS_RXFILTER_CATEGORY_3_8821C \
+ (BIT_MASK_RXFILTER_CATEGORY_3_8821C \
+ << BIT_SHIFT_RXFILTER_CATEGORY_3_8821C)
+#define BIT_CLEAR_RXFILTER_CATEGORY_3_8821C(x) \
+ ((x) & (~BITS_RXFILTER_CATEGORY_3_8821C))
+#define BIT_GET_RXFILTER_CATEGORY_3_8821C(x) \
+ (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8821C) & \
+ BIT_MASK_RXFILTER_CATEGORY_3_8821C)
+#define BIT_SET_RXFILTER_CATEGORY_3_8821C(x, v) \
+ (BIT_CLEAR_RXFILTER_CATEGORY_3_8821C(x) | \
+ BIT_RXFILTER_CATEGORY_3_8821C(v))
+/* 2 REG_RXFILTER_ACTION_3_8821C */
-/* 2 REG_RXFLTMAP4_8821C (RX FILTER MAP GROUP 4) */
-#define BIT_CTRLFLT15EN_FW_8821C BIT(15)
-#define BIT_CTRLFLT14EN_FW_8821C BIT(14)
-#define BIT_CTRLFLT13EN_FW_8821C BIT(13)
-#define BIT_CTRLFLT12EN_FW_8821C BIT(12)
-#define BIT_CTRLFLT11EN_FW_8821C BIT(11)
-#define BIT_CTRLFLT10EN_FW_8821C BIT(10)
-#define BIT_CTRLFLT9EN_FW_8821C BIT(9)
-#define BIT_CTRLFLT8EN_FW_8821C BIT(8)
-#define BIT_CTRLFLT7EN_FW_8821C BIT(7)
-#define BIT_CTRLFLT6EN_FW_8821C BIT(6)
-#define BIT_CTRLFLT5EN_FW_8821C BIT(5)
-#define BIT_CTRLFLT4EN_FW_8821C BIT(4)
-#define BIT_CTRLFLT3EN_FW_8821C BIT(3)
-#define BIT_CTRLFLT2EN_FW_8821C BIT(2)
-#define BIT_CTRLFLT1EN_FW_8821C BIT(1)
-#define BIT_CTRLFLT0EN_FW_8821C BIT(0)
+#define BIT_SHIFT_RXFILTER_ACTION_3_8821C 0
+#define BIT_MASK_RXFILTER_ACTION_3_8821C 0xff
+#define BIT_RXFILTER_ACTION_3_8821C(x) \
+ (((x) & BIT_MASK_RXFILTER_ACTION_3_8821C) \
+ << BIT_SHIFT_RXFILTER_ACTION_3_8821C)
+#define BITS_RXFILTER_ACTION_3_8821C \
+ (BIT_MASK_RXFILTER_ACTION_3_8821C << BIT_SHIFT_RXFILTER_ACTION_3_8821C)
+#define BIT_CLEAR_RXFILTER_ACTION_3_8821C(x) \
+ ((x) & (~BITS_RXFILTER_ACTION_3_8821C))
+#define BIT_GET_RXFILTER_ACTION_3_8821C(x) \
+ (((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8821C) & \
+ BIT_MASK_RXFILTER_ACTION_3_8821C)
+#define BIT_SET_RXFILTER_ACTION_3_8821C(x, v) \
+ (BIT_CLEAR_RXFILTER_ACTION_3_8821C(x) | BIT_RXFILTER_ACTION_3_8821C(v))
/* 2 REG_RXFLTMAP3_8821C (RX FILTER MAP GROUP 3) */
#define BIT_MGTFLT15EN_FW_8821C BIT(15)
@@ -8168,7 +15291,43 @@
#define BIT_MGTFLT1EN_FW_8821C BIT(1)
#define BIT_MGTFLT0EN_FW_8821C BIT(0)
-/* 2 REG_RXFLTMAP6_8821C (RX FILTER MAP GROUP 3) */
+/* 2 REG_RXFLTMAP4_8821C (RX FILTER MAP GROUP 4) */
+#define BIT_CTRLFLT15EN_FW_8821C BIT(15)
+#define BIT_CTRLFLT14EN_FW_8821C BIT(14)
+#define BIT_CTRLFLT13EN_FW_8821C BIT(13)
+#define BIT_CTRLFLT12EN_FW_8821C BIT(12)
+#define BIT_CTRLFLT11EN_FW_8821C BIT(11)
+#define BIT_CTRLFLT10EN_FW_8821C BIT(10)
+#define BIT_CTRLFLT9EN_FW_8821C BIT(9)
+#define BIT_CTRLFLT8EN_FW_8821C BIT(8)
+#define BIT_CTRLFLT7EN_FW_8821C BIT(7)
+#define BIT_CTRLFLT6EN_FW_8821C BIT(6)
+#define BIT_CTRLFLT5EN_FW_8821C BIT(5)
+#define BIT_CTRLFLT4EN_FW_8821C BIT(4)
+#define BIT_CTRLFLT3EN_FW_8821C BIT(3)
+#define BIT_CTRLFLT2EN_FW_8821C BIT(2)
+#define BIT_CTRLFLT1EN_FW_8821C BIT(1)
+#define BIT_CTRLFLT0EN_FW_8821C BIT(0)
+
+/* 2 REG_RXFLTMAP5_8821C (RX FILTER MAP GROUP 5) */
+#define BIT_DATAFLT15EN_FW_8821C BIT(15)
+#define BIT_DATAFLT14EN_FW_8821C BIT(14)
+#define BIT_DATAFLT13EN_FW_8821C BIT(13)
+#define BIT_DATAFLT12EN_FW_8821C BIT(12)
+#define BIT_DATAFLT11EN_FW_8821C BIT(11)
+#define BIT_DATAFLT10EN_FW_8821C BIT(10)
+#define BIT_DATAFLT9EN_FW_8821C BIT(9)
+#define BIT_DATAFLT8EN_FW_8821C BIT(8)
+#define BIT_DATAFLT7EN_FW_8821C BIT(7)
+#define BIT_DATAFLT6EN_FW_8821C BIT(6)
+#define BIT_DATAFLT5EN_FW_8821C BIT(5)
+#define BIT_DATAFLT4EN_FW_8821C BIT(4)
+#define BIT_DATAFLT3EN_FW_8821C BIT(3)
+#define BIT_DATAFLT2EN_FW_8821C BIT(2)
+#define BIT_DATAFLT1EN_FW_8821C BIT(1)
+#define BIT_DATAFLT0EN_FW_8821C BIT(0)
+
+/* 2 REG_RXFLTMAP6_8821C (RX FILTER MAP GROUP 6) */
#define BIT_ACTIONFLT15EN_FW_8821C BIT(15)
#define BIT_ACTIONFLT14EN_FW_8821C BIT(14)
#define BIT_ACTIONFLT13EN_FW_8821C BIT(13)
@@ -8186,40 +15345,53 @@
#define BIT_ACTIONFLT1EN_FW_8821C BIT(1)
#define BIT_ACTIONFLT0EN_FW_8821C BIT(0)
-/* 2 REG_RXFLTMAP5_8821C (RX FILTER MAP GROUP 3) */
-#define BIT_DATAFLT15EN_FW_8821C BIT(15)
-#define BIT_DATAFLT14EN_FW_8821C BIT(14)
-#define BIT_DATAFLT13EN_FW_8821C BIT(13)
-#define BIT_DATAFLT12EN_FW_8821C BIT(12)
-#define BIT_DATAFLT11EN_FW_8821C BIT(11)
-#define BIT_DATAFLT10EN_FW_8821C BIT(10)
-#define BIT_DATAFLT9EN_FW_8821C BIT(9)
-#define BIT_DATAFLT8EN_FW_8821C BIT(8)
-#define BIT_DATAFLT7EN_FW_8821C BIT(7)
-#define BIT_DATAFLT6EN_FW_8821C BIT(6)
-#define BIT_DATAFLT5EN_FW_8821C BIT(5)
-#define BIT_DATAFLT4EN_FW_8821C BIT(4)
-#define BIT_DATAFLT3EN_FW_8821C BIT(3)
-#define BIT_DATAFLT2EN_FW_8821C BIT(2)
-#define BIT_DATAFLT1EN_FW_8821C BIT(1)
-#define BIT_DATAFLT0EN_FW_8821C BIT(0)
+/* 2 REG_WOW_CTRL_8821C (WAKE ON WLAN CONTROL REGISTER) */
-/* 2 REG_WMMPS_UAPSD_TID_8821C (WMM POWER SAVE UAPSD TID REGISTER) */
-#define BIT_WMMPS_UAPSD_TID7_8821C BIT(7)
-#define BIT_WMMPS_UAPSD_TID6_8821C BIT(6)
-#define BIT_WMMPS_UAPSD_TID5_8821C BIT(5)
-#define BIT_WMMPS_UAPSD_TID4_8821C BIT(4)
-#define BIT_WMMPS_UAPSD_TID3_8821C BIT(3)
-#define BIT_WMMPS_UAPSD_TID2_8821C BIT(2)
-#define BIT_WMMPS_UAPSD_TID1_8821C BIT(1)
-#define BIT_WMMPS_UAPSD_TID0_8821C BIT(0)
+#define BIT_SHIFT_PSF_BSSIDSEL_B2B1_8821C 6
+#define BIT_MASK_PSF_BSSIDSEL_B2B1_8821C 0x3
+#define BIT_PSF_BSSIDSEL_B2B1_8821C(x) \
+ (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8821C) \
+ << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8821C)
+#define BITS_PSF_BSSIDSEL_B2B1_8821C \
+ (BIT_MASK_PSF_BSSIDSEL_B2B1_8821C << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8821C)
+#define BIT_CLEAR_PSF_BSSIDSEL_B2B1_8821C(x) \
+ ((x) & (~BITS_PSF_BSSIDSEL_B2B1_8821C))
+#define BIT_GET_PSF_BSSIDSEL_B2B1_8821C(x) \
+ (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8821C) & \
+ BIT_MASK_PSF_BSSIDSEL_B2B1_8821C)
+#define BIT_SET_PSF_BSSIDSEL_B2B1_8821C(x, v) \
+ (BIT_CLEAR_PSF_BSSIDSEL_B2B1_8821C(x) | BIT_PSF_BSSIDSEL_B2B1_8821C(v))
+
+#define BIT_WOWHCI_8821C BIT(5)
+#define BIT_PSF_BSSIDSEL_B0_8821C BIT(4)
+#define BIT_UWF_8821C BIT(3)
+#define BIT_MAGIC_8821C BIT(2)
+#define BIT_WOWEN_8821C BIT(1)
+#define BIT_FORCE_WAKEUP_8821C BIT(0)
+
+/* 2 REG_NAN_RX_TSF_FILTER_8821C(NAN_RX_TSF_ADDRESS_FILTER) */
+#define BIT_CHK_TSF_TA_8821C BIT(2)
+#define BIT_CHK_TSF_CBSSID_8821C BIT(1)
+#define BIT_CHK_TSF_EN_8821C BIT(0)
/* 2 REG_PS_RX_INFO_8821C (POWER SAVE RX INFORMATION REGISTER) */
#define BIT_SHIFT_PORTSEL__PS_RX_INFO_8821C 5
#define BIT_MASK_PORTSEL__PS_RX_INFO_8821C 0x7
-#define BIT_PORTSEL__PS_RX_INFO_8821C(x) (((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8821C) << BIT_SHIFT_PORTSEL__PS_RX_INFO_8821C)
-#define BIT_GET_PORTSEL__PS_RX_INFO_8821C(x) (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8821C) & BIT_MASK_PORTSEL__PS_RX_INFO_8821C)
+#define BIT_PORTSEL__PS_RX_INFO_8821C(x) \
+ (((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8821C) \
+ << BIT_SHIFT_PORTSEL__PS_RX_INFO_8821C)
+#define BITS_PORTSEL__PS_RX_INFO_8821C \
+ (BIT_MASK_PORTSEL__PS_RX_INFO_8821C \
+ << BIT_SHIFT_PORTSEL__PS_RX_INFO_8821C)
+#define BIT_CLEAR_PORTSEL__PS_RX_INFO_8821C(x) \
+ ((x) & (~BITS_PORTSEL__PS_RX_INFO_8821C))
+#define BIT_GET_PORTSEL__PS_RX_INFO_8821C(x) \
+ (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8821C) & \
+ BIT_MASK_PORTSEL__PS_RX_INFO_8821C)
+#define BIT_SET_PORTSEL__PS_RX_INFO_8821C(x, v) \
+ (BIT_CLEAR_PORTSEL__PS_RX_INFO_8821C(x) | \
+ BIT_PORTSEL__PS_RX_INFO_8821C(v))
#define BIT_RXCTRLIN0_8821C BIT(4)
#define BIT_RXMGTIN0_8821C BIT(3)
@@ -8227,82 +15399,90 @@
#define BIT_RXDATAIN1_8821C BIT(1)
#define BIT_RXDATAIN0_8821C BIT(0)
-/* 2 REG_NAN_RX_TSF_FILTER_8821C(NAN_RX_TSF_ADDRESS_FILTER) */
-#define BIT_CHK_TSF_TA_8821C BIT(2)
-#define BIT_CHK_TSF_CBSSID_8821C BIT(1)
-#define BIT_CHK_TSF_EN_8821C BIT(0)
-
-/* 2 REG_WOW_CTRL_8821C (WAKE ON WLAN CONTROL REGISTER) */
-
-#define BIT_SHIFT_PSF_BSSIDSEL_B2B1_8821C 6
-#define BIT_MASK_PSF_BSSIDSEL_B2B1_8821C 0x3
-#define BIT_PSF_BSSIDSEL_B2B1_8821C(x) (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8821C) << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8821C)
-#define BIT_GET_PSF_BSSIDSEL_B2B1_8821C(x) (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8821C) & BIT_MASK_PSF_BSSIDSEL_B2B1_8821C)
-
-#define BIT_WOWHCI_8821C BIT(5)
-#define BIT_PSF_BSSIDSEL_B0_8821C BIT(4)
-#define BIT_UWF_8821C BIT(3)
-#define BIT_MAGIC_8821C BIT(2)
-#define BIT_WOWEN_8821C BIT(1)
-#define BIT_FORCE_WAKEUP_8821C BIT(0)
+/* 2 REG_WMMPS_UAPSD_TID_8821C (WMM POWER SAVE UAPSD TID REGISTER) */
+#define BIT_WMMPS_UAPSD_TID7_8821C BIT(7)
+#define BIT_WMMPS_UAPSD_TID6_8821C BIT(6)
+#define BIT_WMMPS_UAPSD_TID5_8821C BIT(5)
+#define BIT_WMMPS_UAPSD_TID4_8821C BIT(4)
+#define BIT_WMMPS_UAPSD_TID3_8821C BIT(3)
+#define BIT_WMMPS_UAPSD_TID2_8821C BIT(2)
+#define BIT_WMMPS_UAPSD_TID1_8821C BIT(1)
+#define BIT_WMMPS_UAPSD_TID0_8821C BIT(0)
/* 2 REG_LPNAV_CTRL_8821C (LOW POWER NAV CONTROL REGISTER) */
#define BIT_LPNAV_EN_8821C BIT(31)
#define BIT_SHIFT_LPNAV_EARLY_8821C 16
#define BIT_MASK_LPNAV_EARLY_8821C 0x7fff
-#define BIT_LPNAV_EARLY_8821C(x) (((x) & BIT_MASK_LPNAV_EARLY_8821C) << BIT_SHIFT_LPNAV_EARLY_8821C)
-#define BIT_GET_LPNAV_EARLY_8821C(x) (((x) >> BIT_SHIFT_LPNAV_EARLY_8821C) & BIT_MASK_LPNAV_EARLY_8821C)
-
+#define BIT_LPNAV_EARLY_8821C(x) \
+ (((x) & BIT_MASK_LPNAV_EARLY_8821C) << BIT_SHIFT_LPNAV_EARLY_8821C)
+#define BITS_LPNAV_EARLY_8821C \
+ (BIT_MASK_LPNAV_EARLY_8821C << BIT_SHIFT_LPNAV_EARLY_8821C)
+#define BIT_CLEAR_LPNAV_EARLY_8821C(x) ((x) & (~BITS_LPNAV_EARLY_8821C))
+#define BIT_GET_LPNAV_EARLY_8821C(x) \
+ (((x) >> BIT_SHIFT_LPNAV_EARLY_8821C) & BIT_MASK_LPNAV_EARLY_8821C)
+#define BIT_SET_LPNAV_EARLY_8821C(x, v) \
+ (BIT_CLEAR_LPNAV_EARLY_8821C(x) | BIT_LPNAV_EARLY_8821C(v))
#define BIT_SHIFT_LPNAV_TH_8821C 0
#define BIT_MASK_LPNAV_TH_8821C 0xffff
-#define BIT_LPNAV_TH_8821C(x) (((x) & BIT_MASK_LPNAV_TH_8821C) << BIT_SHIFT_LPNAV_TH_8821C)
-#define BIT_GET_LPNAV_TH_8821C(x) (((x) >> BIT_SHIFT_LPNAV_TH_8821C) & BIT_MASK_LPNAV_TH_8821C)
-
+#define BIT_LPNAV_TH_8821C(x) \
+ (((x) & BIT_MASK_LPNAV_TH_8821C) << BIT_SHIFT_LPNAV_TH_8821C)
+#define BITS_LPNAV_TH_8821C \
+ (BIT_MASK_LPNAV_TH_8821C << BIT_SHIFT_LPNAV_TH_8821C)
+#define BIT_CLEAR_LPNAV_TH_8821C(x) ((x) & (~BITS_LPNAV_TH_8821C))
+#define BIT_GET_LPNAV_TH_8821C(x) \
+ (((x) >> BIT_SHIFT_LPNAV_TH_8821C) & BIT_MASK_LPNAV_TH_8821C)
+#define BIT_SET_LPNAV_TH_8821C(x, v) \
+ (BIT_CLEAR_LPNAV_TH_8821C(x) | BIT_LPNAV_TH_8821C(v))
/* 2 REG_WKFMCAM_CMD_8821C (WAKEUP FRAME CAM COMMAND REGISTER) */
#define BIT_WKFCAM_POLLING_V1_8821C BIT(31)
#define BIT_WKFCAM_CLR_V1_8821C BIT(30)
#define BIT_WKFCAM_WE_8821C BIT(16)
-#define BIT_SHIFT_WKFCAM_ADDR_V1_8821C 7
-#define BIT_MASK_WKFCAM_ADDR_V1_8821C 0x1ff
-#define BIT_WKFCAM_ADDR_V1_8821C(x) (((x) & BIT_MASK_WKFCAM_ADDR_V1_8821C) << BIT_SHIFT_WKFCAM_ADDR_V1_8821C)
-#define BIT_GET_WKFCAM_ADDR_V1_8821C(x) (((x) >> BIT_SHIFT_WKFCAM_ADDR_V1_8821C) & BIT_MASK_WKFCAM_ADDR_V1_8821C)
-
+#define BIT_SHIFT_WKFCAM_ADDR_V2_8821C 8
+#define BIT_MASK_WKFCAM_ADDR_V2_8821C 0xff
+#define BIT_WKFCAM_ADDR_V2_8821C(x) \
+ (((x) & BIT_MASK_WKFCAM_ADDR_V2_8821C) \
+ << BIT_SHIFT_WKFCAM_ADDR_V2_8821C)
+#define BITS_WKFCAM_ADDR_V2_8821C \
+ (BIT_MASK_WKFCAM_ADDR_V2_8821C << BIT_SHIFT_WKFCAM_ADDR_V2_8821C)
+#define BIT_CLEAR_WKFCAM_ADDR_V2_8821C(x) ((x) & (~BITS_WKFCAM_ADDR_V2_8821C))
+#define BIT_GET_WKFCAM_ADDR_V2_8821C(x) \
+ (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2_8821C) & \
+ BIT_MASK_WKFCAM_ADDR_V2_8821C)
+#define BIT_SET_WKFCAM_ADDR_V2_8821C(x, v) \
+ (BIT_CLEAR_WKFCAM_ADDR_V2_8821C(x) | BIT_WKFCAM_ADDR_V2_8821C(v))
#define BIT_SHIFT_WKFCAM_CAM_NUM_V1_8821C 0
#define BIT_MASK_WKFCAM_CAM_NUM_V1_8821C 0xff
-#define BIT_WKFCAM_CAM_NUM_V1_8821C(x) (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1_8821C) << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8821C)
-#define BIT_GET_WKFCAM_CAM_NUM_V1_8821C(x) (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8821C) & BIT_MASK_WKFCAM_CAM_NUM_V1_8821C)
-
+#define BIT_WKFCAM_CAM_NUM_V1_8821C(x) \
+ (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1_8821C) \
+ << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8821C)
+#define BITS_WKFCAM_CAM_NUM_V1_8821C \
+ (BIT_MASK_WKFCAM_CAM_NUM_V1_8821C << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8821C)
+#define BIT_CLEAR_WKFCAM_CAM_NUM_V1_8821C(x) \
+ ((x) & (~BITS_WKFCAM_CAM_NUM_V1_8821C))
+#define BIT_GET_WKFCAM_CAM_NUM_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8821C) & \
+ BIT_MASK_WKFCAM_CAM_NUM_V1_8821C)
+#define BIT_SET_WKFCAM_CAM_NUM_V1_8821C(x, v) \
+ (BIT_CLEAR_WKFCAM_CAM_NUM_V1_8821C(x) | BIT_WKFCAM_CAM_NUM_V1_8821C(v))
/* 2 REG_WKFMCAM_RWD_8821C (WAKEUP FRAME READ/WRITE DATA) */
#define BIT_SHIFT_WKFMCAM_RWD_8821C 0
#define BIT_MASK_WKFMCAM_RWD_8821C 0xffffffffL
-#define BIT_WKFMCAM_RWD_8821C(x) (((x) & BIT_MASK_WKFMCAM_RWD_8821C) << BIT_SHIFT_WKFMCAM_RWD_8821C)
-#define BIT_GET_WKFMCAM_RWD_8821C(x) (((x) >> BIT_SHIFT_WKFMCAM_RWD_8821C) & BIT_MASK_WKFMCAM_RWD_8821C)
-
-
-/* 2 REG_RXFLTMAP1_8821C (RX FILTER MAP GROUP 1) */
-#define BIT_CTRLFLT15EN_8821C BIT(15)
-#define BIT_CTRLFLT14EN_8821C BIT(14)
-#define BIT_CTRLFLT13EN_8821C BIT(13)
-#define BIT_CTRLFLT12EN_8821C BIT(12)
-#define BIT_CTRLFLT11EN_8821C BIT(11)
-#define BIT_CTRLFLT10EN_8821C BIT(10)
-#define BIT_CTRLFLT9EN_8821C BIT(9)
-#define BIT_CTRLFLT8EN_8821C BIT(8)
-#define BIT_CTRLFLT7EN_8821C BIT(7)
-#define BIT_CTRLFLT6EN_8821C BIT(6)
-#define BIT_CTRLFLT5EN_8821C BIT(5)
-#define BIT_CTRLFLT4EN_8821C BIT(4)
-#define BIT_CTRLFLT3EN_8821C BIT(3)
-#define BIT_CTRLFLT2EN_8821C BIT(2)
-#define BIT_CTRLFLT1EN_8821C BIT(1)
-#define BIT_CTRLFLT0EN_8821C BIT(0)
+#define BIT_WKFMCAM_RWD_8821C(x) \
+ (((x) & BIT_MASK_WKFMCAM_RWD_8821C) << BIT_SHIFT_WKFMCAM_RWD_8821C)
+#define BITS_WKFMCAM_RWD_8821C \
+ (BIT_MASK_WKFMCAM_RWD_8821C << BIT_SHIFT_WKFMCAM_RWD_8821C)
+#define BIT_CLEAR_WKFMCAM_RWD_8821C(x) ((x) & (~BITS_WKFMCAM_RWD_8821C))
+#define BIT_GET_WKFMCAM_RWD_8821C(x) \
+ (((x) >> BIT_SHIFT_WKFMCAM_RWD_8821C) & BIT_MASK_WKFMCAM_RWD_8821C)
+#define BIT_SET_WKFMCAM_RWD_8821C(x, v) \
+ (BIT_CLEAR_WKFMCAM_RWD_8821C(x) | BIT_WKFMCAM_RWD_8821C(v))
/* 2 REG_RXFLTMAP0_8821C (RX FILTER MAP GROUP 0) */
#define BIT_MGTFLT15EN_8821C BIT(15)
@@ -8322,9 +15502,25 @@
#define BIT_MGTFLT1EN_8821C BIT(1)
#define BIT_MGTFLT0EN_8821C BIT(0)
-/* 2 REG_NOT_VALID_8821C */
+/* 2 REG_RXFLTMAP1_8821C (RX FILTER MAP GROUP 1) */
+#define BIT_CTRLFLT15EN_8821C BIT(15)
+#define BIT_CTRLFLT14EN_8821C BIT(14)
+#define BIT_CTRLFLT13EN_8821C BIT(13)
+#define BIT_CTRLFLT12EN_8821C BIT(12)
+#define BIT_CTRLFLT11EN_8821C BIT(11)
+#define BIT_CTRLFLT10EN_8821C BIT(10)
+#define BIT_CTRLFLT9EN_8821C BIT(9)
+#define BIT_CTRLFLT8EN_8821C BIT(8)
+#define BIT_CTRLFLT7EN_8821C BIT(7)
+#define BIT_CTRLFLT6EN_8821C BIT(6)
+#define BIT_CTRLFLT5EN_8821C BIT(5)
+#define BIT_CTRLFLT4EN_8821C BIT(4)
+#define BIT_CTRLFLT3EN_8821C BIT(3)
+#define BIT_CTRLFLT2EN_8821C BIT(2)
+#define BIT_CTRLFLT1EN_8821C BIT(1)
+#define BIT_CTRLFLT0EN_8821C BIT(0)
-/* 2 REG_RXFLTMAP_8821C (RX FILTER MAP GROUP 2) */
+/* 2 REG_RXFLTMAP2_8821C (RX FILTER MAP GROUP 2) */
#define BIT_DATAFLT15EN_8821C BIT(15)
#define BIT_DATAFLT14EN_8821C BIT(14)
#define BIT_DATAFLT13EN_8821C BIT(13)
@@ -8342,83 +15538,146 @@
#define BIT_DATAFLT1EN_8821C BIT(1)
#define BIT_DATAFLT0EN_8821C BIT(0)
+/* 2 REG_RSVD_8821C */
+
/* 2 REG_BCN_PSR_RPT_8821C (BEACON PARSER REPORT REGISTER) */
#define BIT_SHIFT_DTIM_CNT_8821C 24
#define BIT_MASK_DTIM_CNT_8821C 0xff
-#define BIT_DTIM_CNT_8821C(x) (((x) & BIT_MASK_DTIM_CNT_8821C) << BIT_SHIFT_DTIM_CNT_8821C)
-#define BIT_GET_DTIM_CNT_8821C(x) (((x) >> BIT_SHIFT_DTIM_CNT_8821C) & BIT_MASK_DTIM_CNT_8821C)
-
+#define BIT_DTIM_CNT_8821C(x) \
+ (((x) & BIT_MASK_DTIM_CNT_8821C) << BIT_SHIFT_DTIM_CNT_8821C)
+#define BITS_DTIM_CNT_8821C \
+ (BIT_MASK_DTIM_CNT_8821C << BIT_SHIFT_DTIM_CNT_8821C)
+#define BIT_CLEAR_DTIM_CNT_8821C(x) ((x) & (~BITS_DTIM_CNT_8821C))
+#define BIT_GET_DTIM_CNT_8821C(x) \
+ (((x) >> BIT_SHIFT_DTIM_CNT_8821C) & BIT_MASK_DTIM_CNT_8821C)
+#define BIT_SET_DTIM_CNT_8821C(x, v) \
+ (BIT_CLEAR_DTIM_CNT_8821C(x) | BIT_DTIM_CNT_8821C(v))
#define BIT_SHIFT_DTIM_PERIOD_8821C 16
#define BIT_MASK_DTIM_PERIOD_8821C 0xff
-#define BIT_DTIM_PERIOD_8821C(x) (((x) & BIT_MASK_DTIM_PERIOD_8821C) << BIT_SHIFT_DTIM_PERIOD_8821C)
-#define BIT_GET_DTIM_PERIOD_8821C(x) (((x) >> BIT_SHIFT_DTIM_PERIOD_8821C) & BIT_MASK_DTIM_PERIOD_8821C)
+#define BIT_DTIM_PERIOD_8821C(x) \
+ (((x) & BIT_MASK_DTIM_PERIOD_8821C) << BIT_SHIFT_DTIM_PERIOD_8821C)
+#define BITS_DTIM_PERIOD_8821C \
+ (BIT_MASK_DTIM_PERIOD_8821C << BIT_SHIFT_DTIM_PERIOD_8821C)
+#define BIT_CLEAR_DTIM_PERIOD_8821C(x) ((x) & (~BITS_DTIM_PERIOD_8821C))
+#define BIT_GET_DTIM_PERIOD_8821C(x) \
+ (((x) >> BIT_SHIFT_DTIM_PERIOD_8821C) & BIT_MASK_DTIM_PERIOD_8821C)
+#define BIT_SET_DTIM_PERIOD_8821C(x, v) \
+ (BIT_CLEAR_DTIM_PERIOD_8821C(x) | BIT_DTIM_PERIOD_8821C(v))
#define BIT_DTIM_8821C BIT(15)
#define BIT_TIM_8821C BIT(14)
+#define BIT_RPT_VALID_8821C BIT(13)
#define BIT_SHIFT_PS_AID_0_8821C 0
#define BIT_MASK_PS_AID_0_8821C 0x7ff
-#define BIT_PS_AID_0_8821C(x) (((x) & BIT_MASK_PS_AID_0_8821C) << BIT_SHIFT_PS_AID_0_8821C)
-#define BIT_GET_PS_AID_0_8821C(x) (((x) >> BIT_SHIFT_PS_AID_0_8821C) & BIT_MASK_PS_AID_0_8821C)
+#define BIT_PS_AID_0_8821C(x) \
+ (((x) & BIT_MASK_PS_AID_0_8821C) << BIT_SHIFT_PS_AID_0_8821C)
+#define BITS_PS_AID_0_8821C \
+ (BIT_MASK_PS_AID_0_8821C << BIT_SHIFT_PS_AID_0_8821C)
+#define BIT_CLEAR_PS_AID_0_8821C(x) ((x) & (~BITS_PS_AID_0_8821C))
+#define BIT_GET_PS_AID_0_8821C(x) \
+ (((x) >> BIT_SHIFT_PS_AID_0_8821C) & BIT_MASK_PS_AID_0_8821C)
+#define BIT_SET_PS_AID_0_8821C(x, v) \
+ (BIT_CLEAR_PS_AID_0_8821C(x) | BIT_PS_AID_0_8821C(v))
+/* 2 REG_FLC_RPC_8821C (FW LPS CONDITION -- RX PKT COUNTER) */
-/* 2 REG_FLC_TRPC_8821C (TIMER OF FLC_RPC) */
-#define BIT_FLC_RPCT_V1_8821C BIT(7)
-#define BIT_MODE_8821C BIT(6)
+#define BIT_SHIFT_FLC_RPC_8821C 0
+#define BIT_MASK_FLC_RPC_8821C 0xff
+#define BIT_FLC_RPC_8821C(x) \
+ (((x) & BIT_MASK_FLC_RPC_8821C) << BIT_SHIFT_FLC_RPC_8821C)
+#define BITS_FLC_RPC_8821C (BIT_MASK_FLC_RPC_8821C << BIT_SHIFT_FLC_RPC_8821C)
+#define BIT_CLEAR_FLC_RPC_8821C(x) ((x) & (~BITS_FLC_RPC_8821C))
+#define BIT_GET_FLC_RPC_8821C(x) \
+ (((x) >> BIT_SHIFT_FLC_RPC_8821C) & BIT_MASK_FLC_RPC_8821C)
+#define BIT_SET_FLC_RPC_8821C(x, v) \
+ (BIT_CLEAR_FLC_RPC_8821C(x) | BIT_FLC_RPC_8821C(v))
-#define BIT_SHIFT_TRPCD_8821C 0
-#define BIT_MASK_TRPCD_8821C 0x3f
-#define BIT_TRPCD_8821C(x) (((x) & BIT_MASK_TRPCD_8821C) << BIT_SHIFT_TRPCD_8821C)
-#define BIT_GET_TRPCD_8821C(x) (((x) >> BIT_SHIFT_TRPCD_8821C) & BIT_MASK_TRPCD_8821C)
+/* 2 REG_FLC_RPCT_8821C (FLC_RPC THRESHOLD) */
+#define BIT_SHIFT_FLC_RPCT_8821C 0
+#define BIT_MASK_FLC_RPCT_8821C 0xff
+#define BIT_FLC_RPCT_8821C(x) \
+ (((x) & BIT_MASK_FLC_RPCT_8821C) << BIT_SHIFT_FLC_RPCT_8821C)
+#define BITS_FLC_RPCT_8821C \
+ (BIT_MASK_FLC_RPCT_8821C << BIT_SHIFT_FLC_RPCT_8821C)
+#define BIT_CLEAR_FLC_RPCT_8821C(x) ((x) & (~BITS_FLC_RPCT_8821C))
+#define BIT_GET_FLC_RPCT_8821C(x) \
+ (((x) >> BIT_SHIFT_FLC_RPCT_8821C) & BIT_MASK_FLC_RPCT_8821C)
+#define BIT_SET_FLC_RPCT_8821C(x, v) \
+ (BIT_CLEAR_FLC_RPCT_8821C(x) | BIT_FLC_RPCT_8821C(v))
/* 2 REG_FLC_PTS_8821C (PKT TYPE SELECTION OF FLC_RPC T) */
#define BIT_CMF_8821C BIT(2)
#define BIT_CCF_8821C BIT(1)
#define BIT_CDF_8821C BIT(0)
-/* 2 REG_FLC_RPCT_8821C (FLC_RPC THRESHOLD) */
-
-#define BIT_SHIFT_FLC_RPCT_8821C 0
-#define BIT_MASK_FLC_RPCT_8821C 0xff
-#define BIT_FLC_RPCT_8821C(x) (((x) & BIT_MASK_FLC_RPCT_8821C) << BIT_SHIFT_FLC_RPCT_8821C)
-#define BIT_GET_FLC_RPCT_8821C(x) (((x) >> BIT_SHIFT_FLC_RPCT_8821C) & BIT_MASK_FLC_RPCT_8821C)
-
-
-/* 2 REG_FLC_RPC_8821C (FW LPS CONDITION -- RX PKT COUNTER) */
-
-#define BIT_SHIFT_FLC_RPC_8821C 0
-#define BIT_MASK_FLC_RPC_8821C 0xff
-#define BIT_FLC_RPC_8821C(x) (((x) & BIT_MASK_FLC_RPC_8821C) << BIT_SHIFT_FLC_RPC_8821C)
-#define BIT_GET_FLC_RPC_8821C(x) (((x) >> BIT_SHIFT_FLC_RPC_8821C) & BIT_MASK_FLC_RPC_8821C)
+/* 2 REG_FLC_TRPC_8821C (TIMER OF FLC_RPC) */
+#define BIT_FLC_RPCT_V1_8821C BIT(7)
+#define BIT_MODE_8821C BIT(6)
+#define BIT_SHIFT_TRPCD_8821C 0
+#define BIT_MASK_TRPCD_8821C 0x3f
+#define BIT_TRPCD_8821C(x) \
+ (((x) & BIT_MASK_TRPCD_8821C) << BIT_SHIFT_TRPCD_8821C)
+#define BITS_TRPCD_8821C (BIT_MASK_TRPCD_8821C << BIT_SHIFT_TRPCD_8821C)
+#define BIT_CLEAR_TRPCD_8821C(x) ((x) & (~BITS_TRPCD_8821C))
+#define BIT_GET_TRPCD_8821C(x) \
+ (((x) >> BIT_SHIFT_TRPCD_8821C) & BIT_MASK_TRPCD_8821C)
+#define BIT_SET_TRPCD_8821C(x, v) \
+ (BIT_CLEAR_TRPCD_8821C(x) | BIT_TRPCD_8821C(v))
/* 2 REG_RXPKTMON_CTRL_8821C */
#define BIT_SHIFT_RXBKQPKT_SEQ_8821C 20
#define BIT_MASK_RXBKQPKT_SEQ_8821C 0xf
-#define BIT_RXBKQPKT_SEQ_8821C(x) (((x) & BIT_MASK_RXBKQPKT_SEQ_8821C) << BIT_SHIFT_RXBKQPKT_SEQ_8821C)
-#define BIT_GET_RXBKQPKT_SEQ_8821C(x) (((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8821C) & BIT_MASK_RXBKQPKT_SEQ_8821C)
-
+#define BIT_RXBKQPKT_SEQ_8821C(x) \
+ (((x) & BIT_MASK_RXBKQPKT_SEQ_8821C) << BIT_SHIFT_RXBKQPKT_SEQ_8821C)
+#define BITS_RXBKQPKT_SEQ_8821C \
+ (BIT_MASK_RXBKQPKT_SEQ_8821C << BIT_SHIFT_RXBKQPKT_SEQ_8821C)
+#define BIT_CLEAR_RXBKQPKT_SEQ_8821C(x) ((x) & (~BITS_RXBKQPKT_SEQ_8821C))
+#define BIT_GET_RXBKQPKT_SEQ_8821C(x) \
+ (((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8821C) & BIT_MASK_RXBKQPKT_SEQ_8821C)
+#define BIT_SET_RXBKQPKT_SEQ_8821C(x, v) \
+ (BIT_CLEAR_RXBKQPKT_SEQ_8821C(x) | BIT_RXBKQPKT_SEQ_8821C(v))
#define BIT_SHIFT_RXBEQPKT_SEQ_8821C 16
#define BIT_MASK_RXBEQPKT_SEQ_8821C 0xf
-#define BIT_RXBEQPKT_SEQ_8821C(x) (((x) & BIT_MASK_RXBEQPKT_SEQ_8821C) << BIT_SHIFT_RXBEQPKT_SEQ_8821C)
-#define BIT_GET_RXBEQPKT_SEQ_8821C(x) (((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8821C) & BIT_MASK_RXBEQPKT_SEQ_8821C)
-
+#define BIT_RXBEQPKT_SEQ_8821C(x) \
+ (((x) & BIT_MASK_RXBEQPKT_SEQ_8821C) << BIT_SHIFT_RXBEQPKT_SEQ_8821C)
+#define BITS_RXBEQPKT_SEQ_8821C \
+ (BIT_MASK_RXBEQPKT_SEQ_8821C << BIT_SHIFT_RXBEQPKT_SEQ_8821C)
+#define BIT_CLEAR_RXBEQPKT_SEQ_8821C(x) ((x) & (~BITS_RXBEQPKT_SEQ_8821C))
+#define BIT_GET_RXBEQPKT_SEQ_8821C(x) \
+ (((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8821C) & BIT_MASK_RXBEQPKT_SEQ_8821C)
+#define BIT_SET_RXBEQPKT_SEQ_8821C(x, v) \
+ (BIT_CLEAR_RXBEQPKT_SEQ_8821C(x) | BIT_RXBEQPKT_SEQ_8821C(v))
#define BIT_SHIFT_RXVIQPKT_SEQ_8821C 12
#define BIT_MASK_RXVIQPKT_SEQ_8821C 0xf
-#define BIT_RXVIQPKT_SEQ_8821C(x) (((x) & BIT_MASK_RXVIQPKT_SEQ_8821C) << BIT_SHIFT_RXVIQPKT_SEQ_8821C)
-#define BIT_GET_RXVIQPKT_SEQ_8821C(x) (((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8821C) & BIT_MASK_RXVIQPKT_SEQ_8821C)
-
+#define BIT_RXVIQPKT_SEQ_8821C(x) \
+ (((x) & BIT_MASK_RXVIQPKT_SEQ_8821C) << BIT_SHIFT_RXVIQPKT_SEQ_8821C)
+#define BITS_RXVIQPKT_SEQ_8821C \
+ (BIT_MASK_RXVIQPKT_SEQ_8821C << BIT_SHIFT_RXVIQPKT_SEQ_8821C)
+#define BIT_CLEAR_RXVIQPKT_SEQ_8821C(x) ((x) & (~BITS_RXVIQPKT_SEQ_8821C))
+#define BIT_GET_RXVIQPKT_SEQ_8821C(x) \
+ (((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8821C) & BIT_MASK_RXVIQPKT_SEQ_8821C)
+#define BIT_SET_RXVIQPKT_SEQ_8821C(x, v) \
+ (BIT_CLEAR_RXVIQPKT_SEQ_8821C(x) | BIT_RXVIQPKT_SEQ_8821C(v))
#define BIT_SHIFT_RXVOQPKT_SEQ_8821C 8
#define BIT_MASK_RXVOQPKT_SEQ_8821C 0xf
-#define BIT_RXVOQPKT_SEQ_8821C(x) (((x) & BIT_MASK_RXVOQPKT_SEQ_8821C) << BIT_SHIFT_RXVOQPKT_SEQ_8821C)
-#define BIT_GET_RXVOQPKT_SEQ_8821C(x) (((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8821C) & BIT_MASK_RXVOQPKT_SEQ_8821C)
+#define BIT_RXVOQPKT_SEQ_8821C(x) \
+ (((x) & BIT_MASK_RXVOQPKT_SEQ_8821C) << BIT_SHIFT_RXVOQPKT_SEQ_8821C)
+#define BITS_RXVOQPKT_SEQ_8821C \
+ (BIT_MASK_RXVOQPKT_SEQ_8821C << BIT_SHIFT_RXVOQPKT_SEQ_8821C)
+#define BIT_CLEAR_RXVOQPKT_SEQ_8821C(x) ((x) & (~BITS_RXVOQPKT_SEQ_8821C))
+#define BIT_GET_RXVOQPKT_SEQ_8821C(x) \
+ (((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8821C) & BIT_MASK_RXVOQPKT_SEQ_8821C)
+#define BIT_SET_RXVOQPKT_SEQ_8821C(x, v) \
+ (BIT_CLEAR_RXVOQPKT_SEQ_8821C(x) | BIT_RXVOQPKT_SEQ_8821C(v))
#define BIT_RXBKQPKT_ERR_8821C BIT(7)
#define BIT_RXBEQPKT_ERR_8821C BIT(6)
@@ -8432,22 +15691,41 @@
#define BIT_SHIFT_STATE_SEL_8821C 24
#define BIT_MASK_STATE_SEL_8821C 0x1f
-#define BIT_STATE_SEL_8821C(x) (((x) & BIT_MASK_STATE_SEL_8821C) << BIT_SHIFT_STATE_SEL_8821C)
-#define BIT_GET_STATE_SEL_8821C(x) (((x) >> BIT_SHIFT_STATE_SEL_8821C) & BIT_MASK_STATE_SEL_8821C)
-
+#define BIT_STATE_SEL_8821C(x) \
+ (((x) & BIT_MASK_STATE_SEL_8821C) << BIT_SHIFT_STATE_SEL_8821C)
+#define BITS_STATE_SEL_8821C \
+ (BIT_MASK_STATE_SEL_8821C << BIT_SHIFT_STATE_SEL_8821C)
+#define BIT_CLEAR_STATE_SEL_8821C(x) ((x) & (~BITS_STATE_SEL_8821C))
+#define BIT_GET_STATE_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_STATE_SEL_8821C) & BIT_MASK_STATE_SEL_8821C)
+#define BIT_SET_STATE_SEL_8821C(x, v) \
+ (BIT_CLEAR_STATE_SEL_8821C(x) | BIT_STATE_SEL_8821C(v))
#define BIT_SHIFT_STATE_INFO_8821C 8
#define BIT_MASK_STATE_INFO_8821C 0xff
-#define BIT_STATE_INFO_8821C(x) (((x) & BIT_MASK_STATE_INFO_8821C) << BIT_SHIFT_STATE_INFO_8821C)
-#define BIT_GET_STATE_INFO_8821C(x) (((x) >> BIT_SHIFT_STATE_INFO_8821C) & BIT_MASK_STATE_INFO_8821C)
+#define BIT_STATE_INFO_8821C(x) \
+ (((x) & BIT_MASK_STATE_INFO_8821C) << BIT_SHIFT_STATE_INFO_8821C)
+#define BITS_STATE_INFO_8821C \
+ (BIT_MASK_STATE_INFO_8821C << BIT_SHIFT_STATE_INFO_8821C)
+#define BIT_CLEAR_STATE_INFO_8821C(x) ((x) & (~BITS_STATE_INFO_8821C))
+#define BIT_GET_STATE_INFO_8821C(x) \
+ (((x) >> BIT_SHIFT_STATE_INFO_8821C) & BIT_MASK_STATE_INFO_8821C)
+#define BIT_SET_STATE_INFO_8821C(x, v) \
+ (BIT_CLEAR_STATE_INFO_8821C(x) | BIT_STATE_INFO_8821C(v))
#define BIT_UPD_NXT_STATE_8821C BIT(7)
#define BIT_SHIFT_CUR_STATE_8821C 0
#define BIT_MASK_CUR_STATE_8821C 0x7f
-#define BIT_CUR_STATE_8821C(x) (((x) & BIT_MASK_CUR_STATE_8821C) << BIT_SHIFT_CUR_STATE_8821C)
-#define BIT_GET_CUR_STATE_8821C(x) (((x) >> BIT_SHIFT_CUR_STATE_8821C) & BIT_MASK_CUR_STATE_8821C)
-
+#define BIT_CUR_STATE_8821C(x) \
+ (((x) & BIT_MASK_CUR_STATE_8821C) << BIT_SHIFT_CUR_STATE_8821C)
+#define BITS_CUR_STATE_8821C \
+ (BIT_MASK_CUR_STATE_8821C << BIT_SHIFT_CUR_STATE_8821C)
+#define BIT_CLEAR_CUR_STATE_8821C(x) ((x) & (~BITS_CUR_STATE_8821C))
+#define BIT_GET_CUR_STATE_8821C(x) \
+ (((x) >> BIT_SHIFT_CUR_STATE_8821C) & BIT_MASK_CUR_STATE_8821C)
+#define BIT_SET_CUR_STATE_8821C(x, v) \
+ (BIT_CLEAR_CUR_STATE_8821C(x) | BIT_CUR_STATE_8821C(v))
/* 2 REG_ERROR_MON_8821C */
#define BIT_MACRX_ERR_1_8821C BIT(17)
@@ -8462,8 +15740,18 @@
#define BIT_SHIFT_INFO_INDEX_OFFSET_8821C 16
#define BIT_MASK_INFO_INDEX_OFFSET_8821C 0x1fff
-#define BIT_INFO_INDEX_OFFSET_8821C(x) (((x) & BIT_MASK_INFO_INDEX_OFFSET_8821C) << BIT_SHIFT_INFO_INDEX_OFFSET_8821C)
-#define BIT_GET_INFO_INDEX_OFFSET_8821C(x) (((x) >> BIT_SHIFT_INFO_INDEX_OFFSET_8821C) & BIT_MASK_INFO_INDEX_OFFSET_8821C)
+#define BIT_INFO_INDEX_OFFSET_8821C(x) \
+ (((x) & BIT_MASK_INFO_INDEX_OFFSET_8821C) \
+ << BIT_SHIFT_INFO_INDEX_OFFSET_8821C)
+#define BITS_INFO_INDEX_OFFSET_8821C \
+ (BIT_MASK_INFO_INDEX_OFFSET_8821C << BIT_SHIFT_INFO_INDEX_OFFSET_8821C)
+#define BIT_CLEAR_INFO_INDEX_OFFSET_8821C(x) \
+ ((x) & (~BITS_INFO_INDEX_OFFSET_8821C))
+#define BIT_GET_INFO_INDEX_OFFSET_8821C(x) \
+ (((x) >> BIT_SHIFT_INFO_INDEX_OFFSET_8821C) & \
+ BIT_MASK_INFO_INDEX_OFFSET_8821C)
+#define BIT_SET_INFO_INDEX_OFFSET_8821C(x, v) \
+ (BIT_CLEAR_INFO_INDEX_OFFSET_8821C(x) | BIT_INFO_INDEX_OFFSET_8821C(v))
#define BIT_WMAC_SRCH_FIFOFULL_8821C BIT(15)
#define BIT_DIS_INFOSRCH_8821C BIT(14)
@@ -8471,118 +15759,262 @@
#define BIT_SHIFT_INFO_ADDR_OFFSET_8821C 0
#define BIT_MASK_INFO_ADDR_OFFSET_8821C 0x1fff
-#define BIT_INFO_ADDR_OFFSET_8821C(x) (((x) & BIT_MASK_INFO_ADDR_OFFSET_8821C) << BIT_SHIFT_INFO_ADDR_OFFSET_8821C)
-#define BIT_GET_INFO_ADDR_OFFSET_8821C(x) (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8821C) & BIT_MASK_INFO_ADDR_OFFSET_8821C)
-
+#define BIT_INFO_ADDR_OFFSET_8821C(x) \
+ (((x) & BIT_MASK_INFO_ADDR_OFFSET_8821C) \
+ << BIT_SHIFT_INFO_ADDR_OFFSET_8821C)
+#define BITS_INFO_ADDR_OFFSET_8821C \
+ (BIT_MASK_INFO_ADDR_OFFSET_8821C << BIT_SHIFT_INFO_ADDR_OFFSET_8821C)
+#define BIT_CLEAR_INFO_ADDR_OFFSET_8821C(x) \
+ ((x) & (~BITS_INFO_ADDR_OFFSET_8821C))
+#define BIT_GET_INFO_ADDR_OFFSET_8821C(x) \
+ (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8821C) & \
+ BIT_MASK_INFO_ADDR_OFFSET_8821C)
+#define BIT_SET_INFO_ADDR_OFFSET_8821C(x, v) \
+ (BIT_CLEAR_INFO_ADDR_OFFSET_8821C(x) | BIT_INFO_ADDR_OFFSET_8821C(v))
/* 2 REG_BT_COEX_TABLE_8821C (BT-COEXISTENCE CONTROL REGISTER) */
-#define BIT_PRI_MASK_RX_RESP_8821C BIT(126)
-#define BIT_PRI_MASK_RXOFDM_8821C BIT(125)
-#define BIT_PRI_MASK_RXCCK_8821C BIT(124)
-#define BIT_SHIFT_PRI_MASK_TXAC_8821C (117 & CPU_OPT_WIDTH)
+#define BIT_SHIFT_COEX_TABLE_1_8821C 0
+#define BIT_MASK_COEX_TABLE_1_8821C 0xffffffffL
+#define BIT_COEX_TABLE_1_8821C(x) \
+ (((x) & BIT_MASK_COEX_TABLE_1_8821C) << BIT_SHIFT_COEX_TABLE_1_8821C)
+#define BITS_COEX_TABLE_1_8821C \
+ (BIT_MASK_COEX_TABLE_1_8821C << BIT_SHIFT_COEX_TABLE_1_8821C)
+#define BIT_CLEAR_COEX_TABLE_1_8821C(x) ((x) & (~BITS_COEX_TABLE_1_8821C))
+#define BIT_GET_COEX_TABLE_1_8821C(x) \
+ (((x) >> BIT_SHIFT_COEX_TABLE_1_8821C) & BIT_MASK_COEX_TABLE_1_8821C)
+#define BIT_SET_COEX_TABLE_1_8821C(x, v) \
+ (BIT_CLEAR_COEX_TABLE_1_8821C(x) | BIT_COEX_TABLE_1_8821C(v))
+
+/* 2 REG_BT_COEX_TABLE2_8821C (BT-COEXISTENCE CONTROL REGISTER) */
+
+#define BIT_SHIFT_COEX_TABLE_2_8821C 0
+#define BIT_MASK_COEX_TABLE_2_8821C 0xffffffffL
+#define BIT_COEX_TABLE_2_8821C(x) \
+ (((x) & BIT_MASK_COEX_TABLE_2_8821C) << BIT_SHIFT_COEX_TABLE_2_8821C)
+#define BITS_COEX_TABLE_2_8821C \
+ (BIT_MASK_COEX_TABLE_2_8821C << BIT_SHIFT_COEX_TABLE_2_8821C)
+#define BIT_CLEAR_COEX_TABLE_2_8821C(x) ((x) & (~BITS_COEX_TABLE_2_8821C))
+#define BIT_GET_COEX_TABLE_2_8821C(x) \
+ (((x) >> BIT_SHIFT_COEX_TABLE_2_8821C) & BIT_MASK_COEX_TABLE_2_8821C)
+#define BIT_SET_COEX_TABLE_2_8821C(x, v) \
+ (BIT_CLEAR_COEX_TABLE_2_8821C(x) | BIT_COEX_TABLE_2_8821C(v))
+
+/* 2 REG_BT_COEX_BREAK_TABLE_8821C (BT-COEXISTENCE CONTROL REGISTER) */
+
+#define BIT_SHIFT_BREAK_TABLE_2_8821C 16
+#define BIT_MASK_BREAK_TABLE_2_8821C 0xffff
+#define BIT_BREAK_TABLE_2_8821C(x) \
+ (((x) & BIT_MASK_BREAK_TABLE_2_8821C) << BIT_SHIFT_BREAK_TABLE_2_8821C)
+#define BITS_BREAK_TABLE_2_8821C \
+ (BIT_MASK_BREAK_TABLE_2_8821C << BIT_SHIFT_BREAK_TABLE_2_8821C)
+#define BIT_CLEAR_BREAK_TABLE_2_8821C(x) ((x) & (~BITS_BREAK_TABLE_2_8821C))
+#define BIT_GET_BREAK_TABLE_2_8821C(x) \
+ (((x) >> BIT_SHIFT_BREAK_TABLE_2_8821C) & BIT_MASK_BREAK_TABLE_2_8821C)
+#define BIT_SET_BREAK_TABLE_2_8821C(x, v) \
+ (BIT_CLEAR_BREAK_TABLE_2_8821C(x) | BIT_BREAK_TABLE_2_8821C(v))
+
+#define BIT_SHIFT_BREAK_TABLE_1_8821C 0
+#define BIT_MASK_BREAK_TABLE_1_8821C 0xffff
+#define BIT_BREAK_TABLE_1_8821C(x) \
+ (((x) & BIT_MASK_BREAK_TABLE_1_8821C) << BIT_SHIFT_BREAK_TABLE_1_8821C)
+#define BITS_BREAK_TABLE_1_8821C \
+ (BIT_MASK_BREAK_TABLE_1_8821C << BIT_SHIFT_BREAK_TABLE_1_8821C)
+#define BIT_CLEAR_BREAK_TABLE_1_8821C(x) ((x) & (~BITS_BREAK_TABLE_1_8821C))
+#define BIT_GET_BREAK_TABLE_1_8821C(x) \
+ (((x) >> BIT_SHIFT_BREAK_TABLE_1_8821C) & BIT_MASK_BREAK_TABLE_1_8821C)
+#define BIT_SET_BREAK_TABLE_1_8821C(x, v) \
+ (BIT_CLEAR_BREAK_TABLE_1_8821C(x) | BIT_BREAK_TABLE_1_8821C(v))
+
+/* 2 REG_BT_COEX_TABLE_H_8821C (BT-COEXISTENCE CONTROL REGISTER) */
+#define BIT_PRI_MASK_RX_RESP_V1_8821C BIT(30)
+#define BIT_PRI_MASK_RXOFDM_V1_8821C BIT(29)
+#define BIT_PRI_MASK_RXCCK_V1_8821C BIT(28)
+
+#define BIT_SHIFT_PRI_MASK_TXAC_8821C 21
#define BIT_MASK_PRI_MASK_TXAC_8821C 0x7f
-#define BIT_PRI_MASK_TXAC_8821C(x) (((x) & BIT_MASK_PRI_MASK_TXAC_8821C) << BIT_SHIFT_PRI_MASK_TXAC_8821C)
-#define BIT_GET_PRI_MASK_TXAC_8821C(x) (((x) >> BIT_SHIFT_PRI_MASK_TXAC_8821C) & BIT_MASK_PRI_MASK_TXAC_8821C)
-
-
-#define BIT_SHIFT_PRI_MASK_NAV_8821C (109 & CPU_OPT_WIDTH)
+#define BIT_PRI_MASK_TXAC_8821C(x) \
+ (((x) & BIT_MASK_PRI_MASK_TXAC_8821C) << BIT_SHIFT_PRI_MASK_TXAC_8821C)
+#define BITS_PRI_MASK_TXAC_8821C \
+ (BIT_MASK_PRI_MASK_TXAC_8821C << BIT_SHIFT_PRI_MASK_TXAC_8821C)
+#define BIT_CLEAR_PRI_MASK_TXAC_8821C(x) ((x) & (~BITS_PRI_MASK_TXAC_8821C))
+#define BIT_GET_PRI_MASK_TXAC_8821C(x) \
+ (((x) >> BIT_SHIFT_PRI_MASK_TXAC_8821C) & BIT_MASK_PRI_MASK_TXAC_8821C)
+#define BIT_SET_PRI_MASK_TXAC_8821C(x, v) \
+ (BIT_CLEAR_PRI_MASK_TXAC_8821C(x) | BIT_PRI_MASK_TXAC_8821C(v))
+
+#define BIT_SHIFT_PRI_MASK_NAV_8821C 13
#define BIT_MASK_PRI_MASK_NAV_8821C 0xff
-#define BIT_PRI_MASK_NAV_8821C(x) (((x) & BIT_MASK_PRI_MASK_NAV_8821C) << BIT_SHIFT_PRI_MASK_NAV_8821C)
-#define BIT_GET_PRI_MASK_NAV_8821C(x) (((x) >> BIT_SHIFT_PRI_MASK_NAV_8821C) & BIT_MASK_PRI_MASK_NAV_8821C)
-
-#define BIT_PRI_MASK_CCK_8821C BIT(108)
-#define BIT_PRI_MASK_OFDM_8821C BIT(107)
-#define BIT_PRI_MASK_RTY_8821C BIT(106)
-
-#define BIT_SHIFT_PRI_MASK_NUM_8821C (102 & CPU_OPT_WIDTH)
+#define BIT_PRI_MASK_NAV_8821C(x) \
+ (((x) & BIT_MASK_PRI_MASK_NAV_8821C) << BIT_SHIFT_PRI_MASK_NAV_8821C)
+#define BITS_PRI_MASK_NAV_8821C \
+ (BIT_MASK_PRI_MASK_NAV_8821C << BIT_SHIFT_PRI_MASK_NAV_8821C)
+#define BIT_CLEAR_PRI_MASK_NAV_8821C(x) ((x) & (~BITS_PRI_MASK_NAV_8821C))
+#define BIT_GET_PRI_MASK_NAV_8821C(x) \
+ (((x) >> BIT_SHIFT_PRI_MASK_NAV_8821C) & BIT_MASK_PRI_MASK_NAV_8821C)
+#define BIT_SET_PRI_MASK_NAV_8821C(x, v) \
+ (BIT_CLEAR_PRI_MASK_NAV_8821C(x) | BIT_PRI_MASK_NAV_8821C(v))
+
+#define BIT_PRI_MASK_CCK_V1_8821C BIT(12)
+#define BIT_PRI_MASK_OFDM_V1_8821C BIT(11)
+#define BIT_PRI_MASK_RTY_V1_8821C BIT(10)
+
+#define BIT_SHIFT_PRI_MASK_NUM_8821C 6
#define BIT_MASK_PRI_MASK_NUM_8821C 0xf
-#define BIT_PRI_MASK_NUM_8821C(x) (((x) & BIT_MASK_PRI_MASK_NUM_8821C) << BIT_SHIFT_PRI_MASK_NUM_8821C)
-#define BIT_GET_PRI_MASK_NUM_8821C(x) (((x) >> BIT_SHIFT_PRI_MASK_NUM_8821C) & BIT_MASK_PRI_MASK_NUM_8821C)
-
-
-#define BIT_SHIFT_PRI_MASK_TYPE_8821C (98 & CPU_OPT_WIDTH)
+#define BIT_PRI_MASK_NUM_8821C(x) \
+ (((x) & BIT_MASK_PRI_MASK_NUM_8821C) << BIT_SHIFT_PRI_MASK_NUM_8821C)
+#define BITS_PRI_MASK_NUM_8821C \
+ (BIT_MASK_PRI_MASK_NUM_8821C << BIT_SHIFT_PRI_MASK_NUM_8821C)
+#define BIT_CLEAR_PRI_MASK_NUM_8821C(x) ((x) & (~BITS_PRI_MASK_NUM_8821C))
+#define BIT_GET_PRI_MASK_NUM_8821C(x) \
+ (((x) >> BIT_SHIFT_PRI_MASK_NUM_8821C) & BIT_MASK_PRI_MASK_NUM_8821C)
+#define BIT_SET_PRI_MASK_NUM_8821C(x, v) \
+ (BIT_CLEAR_PRI_MASK_NUM_8821C(x) | BIT_PRI_MASK_NUM_8821C(v))
+
+#define BIT_SHIFT_PRI_MASK_TYPE_8821C 2
#define BIT_MASK_PRI_MASK_TYPE_8821C 0xf
-#define BIT_PRI_MASK_TYPE_8821C(x) (((x) & BIT_MASK_PRI_MASK_TYPE_8821C) << BIT_SHIFT_PRI_MASK_TYPE_8821C)
-#define BIT_GET_PRI_MASK_TYPE_8821C(x) (((x) >> BIT_SHIFT_PRI_MASK_TYPE_8821C) & BIT_MASK_PRI_MASK_TYPE_8821C)
-
-#define BIT_OOB_8821C BIT(97)
-#define BIT_ANT_SEL_8821C BIT(96)
-
-#define BIT_SHIFT_BREAK_TABLE_2_8821C (80 & CPU_OPT_WIDTH)
-#define BIT_MASK_BREAK_TABLE_2_8821C 0xffff
-#define BIT_BREAK_TABLE_2_8821C(x) (((x) & BIT_MASK_BREAK_TABLE_2_8821C) << BIT_SHIFT_BREAK_TABLE_2_8821C)
-#define BIT_GET_BREAK_TABLE_2_8821C(x) (((x) >> BIT_SHIFT_BREAK_TABLE_2_8821C) & BIT_MASK_BREAK_TABLE_2_8821C)
-
-
-#define BIT_SHIFT_BREAK_TABLE_1_8821C (64 & CPU_OPT_WIDTH)
-#define BIT_MASK_BREAK_TABLE_1_8821C 0xffff
-#define BIT_BREAK_TABLE_1_8821C(x) (((x) & BIT_MASK_BREAK_TABLE_1_8821C) << BIT_SHIFT_BREAK_TABLE_1_8821C)
-#define BIT_GET_BREAK_TABLE_1_8821C(x) (((x) >> BIT_SHIFT_BREAK_TABLE_1_8821C) & BIT_MASK_BREAK_TABLE_1_8821C)
-
-
-#define BIT_SHIFT_COEX_TABLE_2_8821C (32 & CPU_OPT_WIDTH)
-#define BIT_MASK_COEX_TABLE_2_8821C 0xffffffffL
-#define BIT_COEX_TABLE_2_8821C(x) (((x) & BIT_MASK_COEX_TABLE_2_8821C) << BIT_SHIFT_COEX_TABLE_2_8821C)
-#define BIT_GET_COEX_TABLE_2_8821C(x) (((x) >> BIT_SHIFT_COEX_TABLE_2_8821C) & BIT_MASK_COEX_TABLE_2_8821C)
-
-
-#define BIT_SHIFT_COEX_TABLE_1_8821C 0
-#define BIT_MASK_COEX_TABLE_1_8821C 0xffffffffL
-#define BIT_COEX_TABLE_1_8821C(x) (((x) & BIT_MASK_COEX_TABLE_1_8821C) << BIT_SHIFT_COEX_TABLE_1_8821C)
-#define BIT_GET_COEX_TABLE_1_8821C(x) (((x) >> BIT_SHIFT_COEX_TABLE_1_8821C) & BIT_MASK_COEX_TABLE_1_8821C)
-
+#define BIT_PRI_MASK_TYPE_8821C(x) \
+ (((x) & BIT_MASK_PRI_MASK_TYPE_8821C) << BIT_SHIFT_PRI_MASK_TYPE_8821C)
+#define BITS_PRI_MASK_TYPE_8821C \
+ (BIT_MASK_PRI_MASK_TYPE_8821C << BIT_SHIFT_PRI_MASK_TYPE_8821C)
+#define BIT_CLEAR_PRI_MASK_TYPE_8821C(x) ((x) & (~BITS_PRI_MASK_TYPE_8821C))
+#define BIT_GET_PRI_MASK_TYPE_8821C(x) \
+ (((x) >> BIT_SHIFT_PRI_MASK_TYPE_8821C) & BIT_MASK_PRI_MASK_TYPE_8821C)
+#define BIT_SET_PRI_MASK_TYPE_8821C(x, v) \
+ (BIT_CLEAR_PRI_MASK_TYPE_8821C(x) | BIT_PRI_MASK_TYPE_8821C(v))
+
+#define BIT_OOB_V1_8821C BIT(1)
+#define BIT_ANT_SEL_V1_8821C BIT(0)
/* 2 REG_RXCMD_0_8821C */
#define BIT_RXCMD_EN_8821C BIT(31)
#define BIT_SHIFT_RXCMD_INFO_8821C 0
#define BIT_MASK_RXCMD_INFO_8821C 0x7fffffffL
-#define BIT_RXCMD_INFO_8821C(x) (((x) & BIT_MASK_RXCMD_INFO_8821C) << BIT_SHIFT_RXCMD_INFO_8821C)
-#define BIT_GET_RXCMD_INFO_8821C(x) (((x) >> BIT_SHIFT_RXCMD_INFO_8821C) & BIT_MASK_RXCMD_INFO_8821C)
-
+#define BIT_RXCMD_INFO_8821C(x) \
+ (((x) & BIT_MASK_RXCMD_INFO_8821C) << BIT_SHIFT_RXCMD_INFO_8821C)
+#define BITS_RXCMD_INFO_8821C \
+ (BIT_MASK_RXCMD_INFO_8821C << BIT_SHIFT_RXCMD_INFO_8821C)
+#define BIT_CLEAR_RXCMD_INFO_8821C(x) ((x) & (~BITS_RXCMD_INFO_8821C))
+#define BIT_GET_RXCMD_INFO_8821C(x) \
+ (((x) >> BIT_SHIFT_RXCMD_INFO_8821C) & BIT_MASK_RXCMD_INFO_8821C)
+#define BIT_SET_RXCMD_INFO_8821C(x, v) \
+ (BIT_CLEAR_RXCMD_INFO_8821C(x) | BIT_RXCMD_INFO_8821C(v))
/* 2 REG_RXCMD_1_8821C */
+#define BIT_SHIFT_CSI_RADDR_LATCH_8821C 24
+#define BIT_MASK_CSI_RADDR_LATCH_8821C 0xff
+#define BIT_CSI_RADDR_LATCH_8821C(x) \
+ (((x) & BIT_MASK_CSI_RADDR_LATCH_8821C) \
+ << BIT_SHIFT_CSI_RADDR_LATCH_8821C)
+#define BITS_CSI_RADDR_LATCH_8821C \
+ (BIT_MASK_CSI_RADDR_LATCH_8821C << BIT_SHIFT_CSI_RADDR_LATCH_8821C)
+#define BIT_CLEAR_CSI_RADDR_LATCH_8821C(x) ((x) & (~BITS_CSI_RADDR_LATCH_8821C))
+#define BIT_GET_CSI_RADDR_LATCH_8821C(x) \
+ (((x) >> BIT_SHIFT_CSI_RADDR_LATCH_8821C) & \
+ BIT_MASK_CSI_RADDR_LATCH_8821C)
+#define BIT_SET_CSI_RADDR_LATCH_8821C(x, v) \
+ (BIT_CLEAR_CSI_RADDR_LATCH_8821C(x) | BIT_CSI_RADDR_LATCH_8821C(v))
+
+#define BIT_SHIFT_CSI_WADDR_LATCH_8821C 16
+#define BIT_MASK_CSI_WADDR_LATCH_8821C 0xff
+#define BIT_CSI_WADDR_LATCH_8821C(x) \
+ (((x) & BIT_MASK_CSI_WADDR_LATCH_8821C) \
+ << BIT_SHIFT_CSI_WADDR_LATCH_8821C)
+#define BITS_CSI_WADDR_LATCH_8821C \
+ (BIT_MASK_CSI_WADDR_LATCH_8821C << BIT_SHIFT_CSI_WADDR_LATCH_8821C)
+#define BIT_CLEAR_CSI_WADDR_LATCH_8821C(x) ((x) & (~BITS_CSI_WADDR_LATCH_8821C))
+#define BIT_GET_CSI_WADDR_LATCH_8821C(x) \
+ (((x) >> BIT_SHIFT_CSI_WADDR_LATCH_8821C) & \
+ BIT_MASK_CSI_WADDR_LATCH_8821C)
+#define BIT_SET_CSI_WADDR_LATCH_8821C(x, v) \
+ (BIT_CLEAR_CSI_WADDR_LATCH_8821C(x) | BIT_CSI_WADDR_LATCH_8821C(v))
+
#define BIT_SHIFT_RXCMD_PRD_8821C 0
#define BIT_MASK_RXCMD_PRD_8821C 0xffff
-#define BIT_RXCMD_PRD_8821C(x) (((x) & BIT_MASK_RXCMD_PRD_8821C) << BIT_SHIFT_RXCMD_PRD_8821C)
-#define BIT_GET_RXCMD_PRD_8821C(x) (((x) >> BIT_SHIFT_RXCMD_PRD_8821C) & BIT_MASK_RXCMD_PRD_8821C)
-
-
-/* 2 REG_NOT_VALID_8821C */
+#define BIT_RXCMD_PRD_8821C(x) \
+ (((x) & BIT_MASK_RXCMD_PRD_8821C) << BIT_SHIFT_RXCMD_PRD_8821C)
+#define BITS_RXCMD_PRD_8821C \
+ (BIT_MASK_RXCMD_PRD_8821C << BIT_SHIFT_RXCMD_PRD_8821C)
+#define BIT_CLEAR_RXCMD_PRD_8821C(x) ((x) & (~BITS_RXCMD_PRD_8821C))
+#define BIT_GET_RXCMD_PRD_8821C(x) \
+ (((x) >> BIT_SHIFT_RXCMD_PRD_8821C) & BIT_MASK_RXCMD_PRD_8821C)
+#define BIT_SET_RXCMD_PRD_8821C(x, v) \
+ (BIT_CLEAR_RXCMD_PRD_8821C(x) | BIT_RXCMD_PRD_8821C(v))
/* 2 REG_WMAC_RESP_TXINFO_8821C (RESPONSE TXINFO REGISTER) */
#define BIT_SHIFT_WMAC_RESP_MFB_8821C 25
#define BIT_MASK_WMAC_RESP_MFB_8821C 0x7f
-#define BIT_WMAC_RESP_MFB_8821C(x) (((x) & BIT_MASK_WMAC_RESP_MFB_8821C) << BIT_SHIFT_WMAC_RESP_MFB_8821C)
-#define BIT_GET_WMAC_RESP_MFB_8821C(x) (((x) >> BIT_SHIFT_WMAC_RESP_MFB_8821C) & BIT_MASK_WMAC_RESP_MFB_8821C)
-
+#define BIT_WMAC_RESP_MFB_8821C(x) \
+ (((x) & BIT_MASK_WMAC_RESP_MFB_8821C) << BIT_SHIFT_WMAC_RESP_MFB_8821C)
+#define BITS_WMAC_RESP_MFB_8821C \
+ (BIT_MASK_WMAC_RESP_MFB_8821C << BIT_SHIFT_WMAC_RESP_MFB_8821C)
+#define BIT_CLEAR_WMAC_RESP_MFB_8821C(x) ((x) & (~BITS_WMAC_RESP_MFB_8821C))
+#define BIT_GET_WMAC_RESP_MFB_8821C(x) \
+ (((x) >> BIT_SHIFT_WMAC_RESP_MFB_8821C) & BIT_MASK_WMAC_RESP_MFB_8821C)
+#define BIT_SET_WMAC_RESP_MFB_8821C(x, v) \
+ (BIT_CLEAR_WMAC_RESP_MFB_8821C(x) | BIT_WMAC_RESP_MFB_8821C(v))
#define BIT_SHIFT_WMAC_ANTINF_SEL_8821C 23
#define BIT_MASK_WMAC_ANTINF_SEL_8821C 0x3
-#define BIT_WMAC_ANTINF_SEL_8821C(x) (((x) & BIT_MASK_WMAC_ANTINF_SEL_8821C) << BIT_SHIFT_WMAC_ANTINF_SEL_8821C)
-#define BIT_GET_WMAC_ANTINF_SEL_8821C(x) (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8821C) & BIT_MASK_WMAC_ANTINF_SEL_8821C)
-
+#define BIT_WMAC_ANTINF_SEL_8821C(x) \
+ (((x) & BIT_MASK_WMAC_ANTINF_SEL_8821C) \
+ << BIT_SHIFT_WMAC_ANTINF_SEL_8821C)
+#define BITS_WMAC_ANTINF_SEL_8821C \
+ (BIT_MASK_WMAC_ANTINF_SEL_8821C << BIT_SHIFT_WMAC_ANTINF_SEL_8821C)
+#define BIT_CLEAR_WMAC_ANTINF_SEL_8821C(x) ((x) & (~BITS_WMAC_ANTINF_SEL_8821C))
+#define BIT_GET_WMAC_ANTINF_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8821C) & \
+ BIT_MASK_WMAC_ANTINF_SEL_8821C)
+#define BIT_SET_WMAC_ANTINF_SEL_8821C(x, v) \
+ (BIT_CLEAR_WMAC_ANTINF_SEL_8821C(x) | BIT_WMAC_ANTINF_SEL_8821C(v))
#define BIT_SHIFT_WMAC_ANTSEL_SEL_8821C 21
#define BIT_MASK_WMAC_ANTSEL_SEL_8821C 0x3
-#define BIT_WMAC_ANTSEL_SEL_8821C(x) (((x) & BIT_MASK_WMAC_ANTSEL_SEL_8821C) << BIT_SHIFT_WMAC_ANTSEL_SEL_8821C)
-#define BIT_GET_WMAC_ANTSEL_SEL_8821C(x) (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8821C) & BIT_MASK_WMAC_ANTSEL_SEL_8821C)
-
+#define BIT_WMAC_ANTSEL_SEL_8821C(x) \
+ (((x) & BIT_MASK_WMAC_ANTSEL_SEL_8821C) \
+ << BIT_SHIFT_WMAC_ANTSEL_SEL_8821C)
+#define BITS_WMAC_ANTSEL_SEL_8821C \
+ (BIT_MASK_WMAC_ANTSEL_SEL_8821C << BIT_SHIFT_WMAC_ANTSEL_SEL_8821C)
+#define BIT_CLEAR_WMAC_ANTSEL_SEL_8821C(x) ((x) & (~BITS_WMAC_ANTSEL_SEL_8821C))
+#define BIT_GET_WMAC_ANTSEL_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8821C) & \
+ BIT_MASK_WMAC_ANTSEL_SEL_8821C)
+#define BIT_SET_WMAC_ANTSEL_SEL_8821C(x, v) \
+ (BIT_CLEAR_WMAC_ANTSEL_SEL_8821C(x) | BIT_WMAC_ANTSEL_SEL_8821C(v))
#define BIT_SHIFT_R_WMAC_RESP_TXPOWER_8821C 18
#define BIT_MASK_R_WMAC_RESP_TXPOWER_8821C 0x7
-#define BIT_R_WMAC_RESP_TXPOWER_8821C(x) (((x) & BIT_MASK_R_WMAC_RESP_TXPOWER_8821C) << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8821C)
-#define BIT_GET_R_WMAC_RESP_TXPOWER_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER_8821C) & BIT_MASK_R_WMAC_RESP_TXPOWER_8821C)
-
+#define BIT_R_WMAC_RESP_TXPOWER_8821C(x) \
+ (((x) & BIT_MASK_R_WMAC_RESP_TXPOWER_8821C) \
+ << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8821C)
+#define BITS_R_WMAC_RESP_TXPOWER_8821C \
+ (BIT_MASK_R_WMAC_RESP_TXPOWER_8821C \
+ << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8821C)
+#define BIT_CLEAR_R_WMAC_RESP_TXPOWER_8821C(x) \
+ ((x) & (~BITS_R_WMAC_RESP_TXPOWER_8821C))
+#define BIT_GET_R_WMAC_RESP_TXPOWER_8821C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER_8821C) & \
+ BIT_MASK_R_WMAC_RESP_TXPOWER_8821C)
+#define BIT_SET_R_WMAC_RESP_TXPOWER_8821C(x, v) \
+ (BIT_CLEAR_R_WMAC_RESP_TXPOWER_8821C(x) | \
+ BIT_R_WMAC_RESP_TXPOWER_8821C(v))
#define BIT_SHIFT_WMAC_RESP_TXANT_8821C 0
#define BIT_MASK_WMAC_RESP_TXANT_8821C 0x3ffff
-#define BIT_WMAC_RESP_TXANT_8821C(x) (((x) & BIT_MASK_WMAC_RESP_TXANT_8821C) << BIT_SHIFT_WMAC_RESP_TXANT_8821C)
-#define BIT_GET_WMAC_RESP_TXANT_8821C(x) (((x) >> BIT_SHIFT_WMAC_RESP_TXANT_8821C) & BIT_MASK_WMAC_RESP_TXANT_8821C)
-
+#define BIT_WMAC_RESP_TXANT_8821C(x) \
+ (((x) & BIT_MASK_WMAC_RESP_TXANT_8821C) \
+ << BIT_SHIFT_WMAC_RESP_TXANT_8821C)
+#define BITS_WMAC_RESP_TXANT_8821C \
+ (BIT_MASK_WMAC_RESP_TXANT_8821C << BIT_SHIFT_WMAC_RESP_TXANT_8821C)
+#define BIT_CLEAR_WMAC_RESP_TXANT_8821C(x) ((x) & (~BITS_WMAC_RESP_TXANT_8821C))
+#define BIT_GET_WMAC_RESP_TXANT_8821C(x) \
+ (((x) >> BIT_SHIFT_WMAC_RESP_TXANT_8821C) & \
+ BIT_MASK_WMAC_RESP_TXANT_8821C)
+#define BIT_SET_WMAC_RESP_TXANT_8821C(x, v) \
+ (BIT_CLEAR_WMAC_RESP_TXANT_8821C(x) | BIT_WMAC_RESP_TXANT_8821C(v))
/* 2 REG_BBPSF_CTRL_8821C */
#define BIT_CTL_IDLE_CLR_CSI_RPT_8821C BIT(31)
@@ -8590,26 +16022,64 @@
#define BIT_SHIFT_WMAC_CSI_RATE_8821C 24
#define BIT_MASK_WMAC_CSI_RATE_8821C 0x3f
-#define BIT_WMAC_CSI_RATE_8821C(x) (((x) & BIT_MASK_WMAC_CSI_RATE_8821C) << BIT_SHIFT_WMAC_CSI_RATE_8821C)
-#define BIT_GET_WMAC_CSI_RATE_8821C(x) (((x) >> BIT_SHIFT_WMAC_CSI_RATE_8821C) & BIT_MASK_WMAC_CSI_RATE_8821C)
-
+#define BIT_WMAC_CSI_RATE_8821C(x) \
+ (((x) & BIT_MASK_WMAC_CSI_RATE_8821C) << BIT_SHIFT_WMAC_CSI_RATE_8821C)
+#define BITS_WMAC_CSI_RATE_8821C \
+ (BIT_MASK_WMAC_CSI_RATE_8821C << BIT_SHIFT_WMAC_CSI_RATE_8821C)
+#define BIT_CLEAR_WMAC_CSI_RATE_8821C(x) ((x) & (~BITS_WMAC_CSI_RATE_8821C))
+#define BIT_GET_WMAC_CSI_RATE_8821C(x) \
+ (((x) >> BIT_SHIFT_WMAC_CSI_RATE_8821C) & BIT_MASK_WMAC_CSI_RATE_8821C)
+#define BIT_SET_WMAC_CSI_RATE_8821C(x, v) \
+ (BIT_CLEAR_WMAC_CSI_RATE_8821C(x) | BIT_WMAC_CSI_RATE_8821C(v))
#define BIT_SHIFT_WMAC_RESP_TXRATE_8821C 16
#define BIT_MASK_WMAC_RESP_TXRATE_8821C 0xff
-#define BIT_WMAC_RESP_TXRATE_8821C(x) (((x) & BIT_MASK_WMAC_RESP_TXRATE_8821C) << BIT_SHIFT_WMAC_RESP_TXRATE_8821C)
-#define BIT_GET_WMAC_RESP_TXRATE_8821C(x) (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8821C) & BIT_MASK_WMAC_RESP_TXRATE_8821C)
-
+#define BIT_WMAC_RESP_TXRATE_8821C(x) \
+ (((x) & BIT_MASK_WMAC_RESP_TXRATE_8821C) \
+ << BIT_SHIFT_WMAC_RESP_TXRATE_8821C)
+#define BITS_WMAC_RESP_TXRATE_8821C \
+ (BIT_MASK_WMAC_RESP_TXRATE_8821C << BIT_SHIFT_WMAC_RESP_TXRATE_8821C)
+#define BIT_CLEAR_WMAC_RESP_TXRATE_8821C(x) \
+ ((x) & (~BITS_WMAC_RESP_TXRATE_8821C))
+#define BIT_GET_WMAC_RESP_TXRATE_8821C(x) \
+ (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8821C) & \
+ BIT_MASK_WMAC_RESP_TXRATE_8821C)
+#define BIT_SET_WMAC_RESP_TXRATE_8821C(x, v) \
+ (BIT_CLEAR_WMAC_RESP_TXRATE_8821C(x) | BIT_WMAC_RESP_TXRATE_8821C(v))
+
+#define BIT_CSI_FORCE_RATE_EN_8821C BIT(15)
+
+#define BIT_SHIFT_CSI_RSC_8821C 13
+#define BIT_MASK_CSI_RSC_8821C 0x3
+#define BIT_CSI_RSC_8821C(x) \
+ (((x) & BIT_MASK_CSI_RSC_8821C) << BIT_SHIFT_CSI_RSC_8821C)
+#define BITS_CSI_RSC_8821C (BIT_MASK_CSI_RSC_8821C << BIT_SHIFT_CSI_RSC_8821C)
+#define BIT_CLEAR_CSI_RSC_8821C(x) ((x) & (~BITS_CSI_RSC_8821C))
+#define BIT_GET_CSI_RSC_8821C(x) \
+ (((x) >> BIT_SHIFT_CSI_RSC_8821C) & BIT_MASK_CSI_RSC_8821C)
+#define BIT_SET_CSI_RSC_8821C(x, v) \
+ (BIT_CLEAR_CSI_RSC_8821C(x) | BIT_CSI_RSC_8821C(v))
+
+#define BIT_CSI_GID_SEL_8821C BIT(12)
+#define BIT_RDCSIMD_FLAG_TRIG_SEL_8821C BIT(11)
+#define BIT_NDPVLD_POS_RST_FFPTR_DIS_V1_8821C BIT(10)
+#define BIT_NDPVLD_PROTECT_RDRDY_DIS_8821C BIT(9)
+#define BIT_RDCSI_EMPTY_APPZERO_8821C BIT(8)
#define BIT_BBPSF_MPDUCHKEN_8821C BIT(5)
#define BIT_BBPSF_MHCHKEN_8821C BIT(4)
#define BIT_BBPSF_ERRCHKEN_8821C BIT(3)
#define BIT_SHIFT_BBPSF_ERRTHR_8821C 0
#define BIT_MASK_BBPSF_ERRTHR_8821C 0x7
-#define BIT_BBPSF_ERRTHR_8821C(x) (((x) & BIT_MASK_BBPSF_ERRTHR_8821C) << BIT_SHIFT_BBPSF_ERRTHR_8821C)
-#define BIT_GET_BBPSF_ERRTHR_8821C(x) (((x) >> BIT_SHIFT_BBPSF_ERRTHR_8821C) & BIT_MASK_BBPSF_ERRTHR_8821C)
-
-
-/* 2 REG_NOT_VALID_8821C */
+#define BIT_BBPSF_ERRTHR_8821C(x) \
+ (((x) & BIT_MASK_BBPSF_ERRTHR_8821C) << BIT_SHIFT_BBPSF_ERRTHR_8821C)
+#define BITS_BBPSF_ERRTHR_8821C \
+ (BIT_MASK_BBPSF_ERRTHR_8821C << BIT_SHIFT_BBPSF_ERRTHR_8821C)
+#define BIT_CLEAR_BBPSF_ERRTHR_8821C(x) ((x) & (~BITS_BBPSF_ERRTHR_8821C))
+#define BIT_GET_BBPSF_ERRTHR_8821C(x) \
+ (((x) >> BIT_SHIFT_BBPSF_ERRTHR_8821C) & BIT_MASK_BBPSF_ERRTHR_8821C)
+#define BIT_SET_BBPSF_ERRTHR_8821C(x, v) \
+ (BIT_CLEAR_BBPSF_ERRTHR_8821C(x) | BIT_BBPSF_ERRTHR_8821C(v))
/* 2 REG_P2P_RX_BCN_NOA_8821C (P2P RX BEACON NOA REGISTER) */
#define BIT_NOA_PARSER_EN_8821C BIT(15)
@@ -8617,196 +16087,499 @@
#define BIT_SHIFT_P2P_OUI_TYPE_8821C 0
#define BIT_MASK_P2P_OUI_TYPE_8821C 0xff
-#define BIT_P2P_OUI_TYPE_8821C(x) (((x) & BIT_MASK_P2P_OUI_TYPE_8821C) << BIT_SHIFT_P2P_OUI_TYPE_8821C)
-#define BIT_GET_P2P_OUI_TYPE_8821C(x) (((x) >> BIT_SHIFT_P2P_OUI_TYPE_8821C) & BIT_MASK_P2P_OUI_TYPE_8821C)
-
+#define BIT_P2P_OUI_TYPE_8821C(x) \
+ (((x) & BIT_MASK_P2P_OUI_TYPE_8821C) << BIT_SHIFT_P2P_OUI_TYPE_8821C)
+#define BITS_P2P_OUI_TYPE_8821C \
+ (BIT_MASK_P2P_OUI_TYPE_8821C << BIT_SHIFT_P2P_OUI_TYPE_8821C)
+#define BIT_CLEAR_P2P_OUI_TYPE_8821C(x) ((x) & (~BITS_P2P_OUI_TYPE_8821C))
+#define BIT_GET_P2P_OUI_TYPE_8821C(x) \
+ (((x) >> BIT_SHIFT_P2P_OUI_TYPE_8821C) & BIT_MASK_P2P_OUI_TYPE_8821C)
+#define BIT_SET_P2P_OUI_TYPE_8821C(x, v) \
+ (BIT_CLEAR_P2P_OUI_TYPE_8821C(x) | BIT_P2P_OUI_TYPE_8821C(v))
+
+/* 2 REG_RSVD_8821C */
/* 2 REG_ASSOCIATED_BFMER0_INFO_8821C (ASSOCIATED BEAMFORMER0 INFO REGISTER) */
-#define BIT_SHIFT_R_WMAC_TXCSI_AID0_8821C (48 & CPU_OPT_WIDTH)
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8821C 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8821C 0xffffffffL
+#define BIT_R_WMAC_SOUNDING_RXADD_R0_V1_8821C(x) \
+ (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8821C) \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8821C)
+#define BITS_R_WMAC_SOUNDING_RXADD_R0_V1_8821C \
+ (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8821C \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8821C)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1_8821C(x) \
+ ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_V1_8821C))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8821C) & \
+ BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8821C)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_V1_8821C(x, v) \
+ (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1_8821C(x) | \
+ BIT_R_WMAC_SOUNDING_RXADD_R0_V1_8821C(v))
+
+/* 2 REG_ASSOCIATED_BFMER0_INFO_H_8821C */
+
+#define BIT_SHIFT_R_WMAC_TXCSI_AID0_8821C 16
#define BIT_MASK_R_WMAC_TXCSI_AID0_8821C 0x1ff
-#define BIT_R_WMAC_TXCSI_AID0_8821C(x) (((x) & BIT_MASK_R_WMAC_TXCSI_AID0_8821C) << BIT_SHIFT_R_WMAC_TXCSI_AID0_8821C)
-#define BIT_GET_R_WMAC_TXCSI_AID0_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8821C) & BIT_MASK_R_WMAC_TXCSI_AID0_8821C)
-
-
-#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8821C 0
-#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8821C 0xffffffffffffL
-#define BIT_R_WMAC_SOUNDING_RXADD_R0_8821C(x) (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8821C) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8821C)
-#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8821C) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8821C)
-
+#define BIT_R_WMAC_TXCSI_AID0_8821C(x) \
+ (((x) & BIT_MASK_R_WMAC_TXCSI_AID0_8821C) \
+ << BIT_SHIFT_R_WMAC_TXCSI_AID0_8821C)
+#define BITS_R_WMAC_TXCSI_AID0_8821C \
+ (BIT_MASK_R_WMAC_TXCSI_AID0_8821C << BIT_SHIFT_R_WMAC_TXCSI_AID0_8821C)
+#define BIT_CLEAR_R_WMAC_TXCSI_AID0_8821C(x) \
+ ((x) & (~BITS_R_WMAC_TXCSI_AID0_8821C))
+#define BIT_GET_R_WMAC_TXCSI_AID0_8821C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8821C) & \
+ BIT_MASK_R_WMAC_TXCSI_AID0_8821C)
+#define BIT_SET_R_WMAC_TXCSI_AID0_8821C(x, v) \
+ (BIT_CLEAR_R_WMAC_TXCSI_AID0_8821C(x) | BIT_R_WMAC_TXCSI_AID0_8821C(v))
+
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C 0xffff
+#define BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C(x) \
+ (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C) \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C)
+#define BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C \
+ (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C(x) \
+ ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C) & \
+ BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C(x, v) \
+ (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C(x) | \
+ BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8821C(v))
/* 2 REG_ASSOCIATED_BFMER1_INFO_8821C (ASSOCIATED BEAMFORMER1 INFO REGISTER) */
-#define BIT_SHIFT_R_WMAC_TXCSI_AID1_8821C (48 & CPU_OPT_WIDTH)
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8821C 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8821C 0xffffffffL
+#define BIT_R_WMAC_SOUNDING_RXADD_R1_V1_8821C(x) \
+ (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8821C) \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8821C)
+#define BITS_R_WMAC_SOUNDING_RXADD_R1_V1_8821C \
+ (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8821C \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8821C)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1_8821C(x) \
+ ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_V1_8821C))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8821C) & \
+ BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8821C)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_V1_8821C(x, v) \
+ (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1_8821C(x) | \
+ BIT_R_WMAC_SOUNDING_RXADD_R1_V1_8821C(v))
+
+/* 2 REG_ASSOCIATED_BFMER1_INFO_H_8821C */
+
+#define BIT_SHIFT_R_WMAC_TXCSI_AID1_8821C 16
#define BIT_MASK_R_WMAC_TXCSI_AID1_8821C 0x1ff
-#define BIT_R_WMAC_TXCSI_AID1_8821C(x) (((x) & BIT_MASK_R_WMAC_TXCSI_AID1_8821C) << BIT_SHIFT_R_WMAC_TXCSI_AID1_8821C)
-#define BIT_GET_R_WMAC_TXCSI_AID1_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8821C) & BIT_MASK_R_WMAC_TXCSI_AID1_8821C)
-
-
-#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8821C 0
-#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8821C 0xffffffffffffL
-#define BIT_R_WMAC_SOUNDING_RXADD_R1_8821C(x) (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8821C) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8821C)
-#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8821C) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8821C)
-
-
-/* 2 REG_NOT_VALID_8821C */
-
-/* 2 REG_NOT_VALID_8821C */
-
-/* 2 REG_NOT_VALID_8821C */
-
-/* 2 REG_NOT_VALID_8821C */
-
-/* 2 REG_NOT_VALID_8821C */
+#define BIT_R_WMAC_TXCSI_AID1_8821C(x) \
+ (((x) & BIT_MASK_R_WMAC_TXCSI_AID1_8821C) \
+ << BIT_SHIFT_R_WMAC_TXCSI_AID1_8821C)
+#define BITS_R_WMAC_TXCSI_AID1_8821C \
+ (BIT_MASK_R_WMAC_TXCSI_AID1_8821C << BIT_SHIFT_R_WMAC_TXCSI_AID1_8821C)
+#define BIT_CLEAR_R_WMAC_TXCSI_AID1_8821C(x) \
+ ((x) & (~BITS_R_WMAC_TXCSI_AID1_8821C))
+#define BIT_GET_R_WMAC_TXCSI_AID1_8821C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8821C) & \
+ BIT_MASK_R_WMAC_TXCSI_AID1_8821C)
+#define BIT_SET_R_WMAC_TXCSI_AID1_8821C(x, v) \
+ (BIT_CLEAR_R_WMAC_TXCSI_AID1_8821C(x) | BIT_R_WMAC_TXCSI_AID1_8821C(v))
+
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C 0xffff
+#define BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C(x) \
+ (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C) \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C)
+#define BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C \
+ (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C(x) \
+ ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C) & \
+ BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C(x, v) \
+ (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C(x) | \
+ BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8821C(v))
/* 2 REG_TX_CSI_RPT_PARAM_BW20_8821C (TX CSI REPORT PARAMETER REGISTER) */
#define BIT_SHIFT_R_WMAC_BFINFO_20M_1_8821C 16
#define BIT_MASK_R_WMAC_BFINFO_20M_1_8821C 0xfff
-#define BIT_R_WMAC_BFINFO_20M_1_8821C(x) (((x) & BIT_MASK_R_WMAC_BFINFO_20M_1_8821C) << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8821C)
-#define BIT_GET_R_WMAC_BFINFO_20M_1_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8821C) & BIT_MASK_R_WMAC_BFINFO_20M_1_8821C)
-
+#define BIT_R_WMAC_BFINFO_20M_1_8821C(x) \
+ (((x) & BIT_MASK_R_WMAC_BFINFO_20M_1_8821C) \
+ << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8821C)
+#define BITS_R_WMAC_BFINFO_20M_1_8821C \
+ (BIT_MASK_R_WMAC_BFINFO_20M_1_8821C \
+ << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8821C)
+#define BIT_CLEAR_R_WMAC_BFINFO_20M_1_8821C(x) \
+ ((x) & (~BITS_R_WMAC_BFINFO_20M_1_8821C))
+#define BIT_GET_R_WMAC_BFINFO_20M_1_8821C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8821C) & \
+ BIT_MASK_R_WMAC_BFINFO_20M_1_8821C)
+#define BIT_SET_R_WMAC_BFINFO_20M_1_8821C(x, v) \
+ (BIT_CLEAR_R_WMAC_BFINFO_20M_1_8821C(x) | \
+ BIT_R_WMAC_BFINFO_20M_1_8821C(v))
#define BIT_SHIFT_R_WMAC_BFINFO_20M_0_8821C 0
#define BIT_MASK_R_WMAC_BFINFO_20M_0_8821C 0xfff
-#define BIT_R_WMAC_BFINFO_20M_0_8821C(x) (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8821C) << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8821C)
-#define BIT_GET_R_WMAC_BFINFO_20M_0_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8821C) & BIT_MASK_R_WMAC_BFINFO_20M_0_8821C)
-
+#define BIT_R_WMAC_BFINFO_20M_0_8821C(x) \
+ (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8821C) \
+ << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8821C)
+#define BITS_R_WMAC_BFINFO_20M_0_8821C \
+ (BIT_MASK_R_WMAC_BFINFO_20M_0_8821C \
+ << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8821C)
+#define BIT_CLEAR_R_WMAC_BFINFO_20M_0_8821C(x) \
+ ((x) & (~BITS_R_WMAC_BFINFO_20M_0_8821C))
+#define BIT_GET_R_WMAC_BFINFO_20M_0_8821C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8821C) & \
+ BIT_MASK_R_WMAC_BFINFO_20M_0_8821C)
+#define BIT_SET_R_WMAC_BFINFO_20M_0_8821C(x, v) \
+ (BIT_CLEAR_R_WMAC_BFINFO_20M_0_8821C(x) | \
+ BIT_R_WMAC_BFINFO_20M_0_8821C(v))
/* 2 REG_TX_CSI_RPT_PARAM_BW40_8821C (TX CSI REPORT PARAMETER_BW40 REGISTER) */
#define BIT_SHIFT_WMAC_RESP_ANTCD_8821C 0
#define BIT_MASK_WMAC_RESP_ANTCD_8821C 0xf
-#define BIT_WMAC_RESP_ANTCD_8821C(x) (((x) & BIT_MASK_WMAC_RESP_ANTCD_8821C) << BIT_SHIFT_WMAC_RESP_ANTCD_8821C)
-#define BIT_GET_WMAC_RESP_ANTCD_8821C(x) (((x) >> BIT_SHIFT_WMAC_RESP_ANTCD_8821C) & BIT_MASK_WMAC_RESP_ANTCD_8821C)
-
-
-/* 2 REG_TX_CSI_RPT_PARAM_BW80_8821C (TX CSI REPORT PARAMETER_BW80 REGISTER) */
+#define BIT_WMAC_RESP_ANTCD_8821C(x) \
+ (((x) & BIT_MASK_WMAC_RESP_ANTCD_8821C) \
+ << BIT_SHIFT_WMAC_RESP_ANTCD_8821C)
+#define BITS_WMAC_RESP_ANTCD_8821C \
+ (BIT_MASK_WMAC_RESP_ANTCD_8821C << BIT_SHIFT_WMAC_RESP_ANTCD_8821C)
+#define BIT_CLEAR_WMAC_RESP_ANTCD_8821C(x) ((x) & (~BITS_WMAC_RESP_ANTCD_8821C))
+#define BIT_GET_WMAC_RESP_ANTCD_8821C(x) \
+ (((x) >> BIT_SHIFT_WMAC_RESP_ANTCD_8821C) & \
+ BIT_MASK_WMAC_RESP_ANTCD_8821C)
+#define BIT_SET_WMAC_RESP_ANTCD_8821C(x, v) \
+ (BIT_CLEAR_WMAC_RESP_ANTCD_8821C(x) | BIT_WMAC_RESP_ANTCD_8821C(v))
+
+/* 2 REG_RSVD_8821C */
/* 2 REG_BCN_PSR_RPT2_8821C (BEACON PARSER REPORT REGISTER2) */
#define BIT_SHIFT_DTIM_CNT2_8821C 24
#define BIT_MASK_DTIM_CNT2_8821C 0xff
-#define BIT_DTIM_CNT2_8821C(x) (((x) & BIT_MASK_DTIM_CNT2_8821C) << BIT_SHIFT_DTIM_CNT2_8821C)
-#define BIT_GET_DTIM_CNT2_8821C(x) (((x) >> BIT_SHIFT_DTIM_CNT2_8821C) & BIT_MASK_DTIM_CNT2_8821C)
-
+#define BIT_DTIM_CNT2_8821C(x) \
+ (((x) & BIT_MASK_DTIM_CNT2_8821C) << BIT_SHIFT_DTIM_CNT2_8821C)
+#define BITS_DTIM_CNT2_8821C \
+ (BIT_MASK_DTIM_CNT2_8821C << BIT_SHIFT_DTIM_CNT2_8821C)
+#define BIT_CLEAR_DTIM_CNT2_8821C(x) ((x) & (~BITS_DTIM_CNT2_8821C))
+#define BIT_GET_DTIM_CNT2_8821C(x) \
+ (((x) >> BIT_SHIFT_DTIM_CNT2_8821C) & BIT_MASK_DTIM_CNT2_8821C)
+#define BIT_SET_DTIM_CNT2_8821C(x, v) \
+ (BIT_CLEAR_DTIM_CNT2_8821C(x) | BIT_DTIM_CNT2_8821C(v))
#define BIT_SHIFT_DTIM_PERIOD2_8821C 16
#define BIT_MASK_DTIM_PERIOD2_8821C 0xff
-#define BIT_DTIM_PERIOD2_8821C(x) (((x) & BIT_MASK_DTIM_PERIOD2_8821C) << BIT_SHIFT_DTIM_PERIOD2_8821C)
-#define BIT_GET_DTIM_PERIOD2_8821C(x) (((x) >> BIT_SHIFT_DTIM_PERIOD2_8821C) & BIT_MASK_DTIM_PERIOD2_8821C)
+#define BIT_DTIM_PERIOD2_8821C(x) \
+ (((x) & BIT_MASK_DTIM_PERIOD2_8821C) << BIT_SHIFT_DTIM_PERIOD2_8821C)
+#define BITS_DTIM_PERIOD2_8821C \
+ (BIT_MASK_DTIM_PERIOD2_8821C << BIT_SHIFT_DTIM_PERIOD2_8821C)
+#define BIT_CLEAR_DTIM_PERIOD2_8821C(x) ((x) & (~BITS_DTIM_PERIOD2_8821C))
+#define BIT_GET_DTIM_PERIOD2_8821C(x) \
+ (((x) >> BIT_SHIFT_DTIM_PERIOD2_8821C) & BIT_MASK_DTIM_PERIOD2_8821C)
+#define BIT_SET_DTIM_PERIOD2_8821C(x, v) \
+ (BIT_CLEAR_DTIM_PERIOD2_8821C(x) | BIT_DTIM_PERIOD2_8821C(v))
#define BIT_DTIM2_8821C BIT(15)
#define BIT_TIM2_8821C BIT(14)
#define BIT_SHIFT_PS_AID_2_8821C 0
#define BIT_MASK_PS_AID_2_8821C 0x7ff
-#define BIT_PS_AID_2_8821C(x) (((x) & BIT_MASK_PS_AID_2_8821C) << BIT_SHIFT_PS_AID_2_8821C)
-#define BIT_GET_PS_AID_2_8821C(x) (((x) >> BIT_SHIFT_PS_AID_2_8821C) & BIT_MASK_PS_AID_2_8821C)
-
+#define BIT_PS_AID_2_8821C(x) \
+ (((x) & BIT_MASK_PS_AID_2_8821C) << BIT_SHIFT_PS_AID_2_8821C)
+#define BITS_PS_AID_2_8821C \
+ (BIT_MASK_PS_AID_2_8821C << BIT_SHIFT_PS_AID_2_8821C)
+#define BIT_CLEAR_PS_AID_2_8821C(x) ((x) & (~BITS_PS_AID_2_8821C))
+#define BIT_GET_PS_AID_2_8821C(x) \
+ (((x) >> BIT_SHIFT_PS_AID_2_8821C) & BIT_MASK_PS_AID_2_8821C)
+#define BIT_SET_PS_AID_2_8821C(x, v) \
+ (BIT_CLEAR_PS_AID_2_8821C(x) | BIT_PS_AID_2_8821C(v))
/* 2 REG_BCN_PSR_RPT3_8821C (BEACON PARSER REPORT REGISTER3) */
#define BIT_SHIFT_DTIM_CNT3_8821C 24
#define BIT_MASK_DTIM_CNT3_8821C 0xff
-#define BIT_DTIM_CNT3_8821C(x) (((x) & BIT_MASK_DTIM_CNT3_8821C) << BIT_SHIFT_DTIM_CNT3_8821C)
-#define BIT_GET_DTIM_CNT3_8821C(x) (((x) >> BIT_SHIFT_DTIM_CNT3_8821C) & BIT_MASK_DTIM_CNT3_8821C)
-
+#define BIT_DTIM_CNT3_8821C(x) \
+ (((x) & BIT_MASK_DTIM_CNT3_8821C) << BIT_SHIFT_DTIM_CNT3_8821C)
+#define BITS_DTIM_CNT3_8821C \
+ (BIT_MASK_DTIM_CNT3_8821C << BIT_SHIFT_DTIM_CNT3_8821C)
+#define BIT_CLEAR_DTIM_CNT3_8821C(x) ((x) & (~BITS_DTIM_CNT3_8821C))
+#define BIT_GET_DTIM_CNT3_8821C(x) \
+ (((x) >> BIT_SHIFT_DTIM_CNT3_8821C) & BIT_MASK_DTIM_CNT3_8821C)
+#define BIT_SET_DTIM_CNT3_8821C(x, v) \
+ (BIT_CLEAR_DTIM_CNT3_8821C(x) | BIT_DTIM_CNT3_8821C(v))
#define BIT_SHIFT_DTIM_PERIOD3_8821C 16
#define BIT_MASK_DTIM_PERIOD3_8821C 0xff
-#define BIT_DTIM_PERIOD3_8821C(x) (((x) & BIT_MASK_DTIM_PERIOD3_8821C) << BIT_SHIFT_DTIM_PERIOD3_8821C)
-#define BIT_GET_DTIM_PERIOD3_8821C(x) (((x) >> BIT_SHIFT_DTIM_PERIOD3_8821C) & BIT_MASK_DTIM_PERIOD3_8821C)
+#define BIT_DTIM_PERIOD3_8821C(x) \
+ (((x) & BIT_MASK_DTIM_PERIOD3_8821C) << BIT_SHIFT_DTIM_PERIOD3_8821C)
+#define BITS_DTIM_PERIOD3_8821C \
+ (BIT_MASK_DTIM_PERIOD3_8821C << BIT_SHIFT_DTIM_PERIOD3_8821C)
+#define BIT_CLEAR_DTIM_PERIOD3_8821C(x) ((x) & (~BITS_DTIM_PERIOD3_8821C))
+#define BIT_GET_DTIM_PERIOD3_8821C(x) \
+ (((x) >> BIT_SHIFT_DTIM_PERIOD3_8821C) & BIT_MASK_DTIM_PERIOD3_8821C)
+#define BIT_SET_DTIM_PERIOD3_8821C(x, v) \
+ (BIT_CLEAR_DTIM_PERIOD3_8821C(x) | BIT_DTIM_PERIOD3_8821C(v))
#define BIT_DTIM3_8821C BIT(15)
#define BIT_TIM3_8821C BIT(14)
#define BIT_SHIFT_PS_AID_3_8821C 0
#define BIT_MASK_PS_AID_3_8821C 0x7ff
-#define BIT_PS_AID_3_8821C(x) (((x) & BIT_MASK_PS_AID_3_8821C) << BIT_SHIFT_PS_AID_3_8821C)
-#define BIT_GET_PS_AID_3_8821C(x) (((x) >> BIT_SHIFT_PS_AID_3_8821C) & BIT_MASK_PS_AID_3_8821C)
-
+#define BIT_PS_AID_3_8821C(x) \
+ (((x) & BIT_MASK_PS_AID_3_8821C) << BIT_SHIFT_PS_AID_3_8821C)
+#define BITS_PS_AID_3_8821C \
+ (BIT_MASK_PS_AID_3_8821C << BIT_SHIFT_PS_AID_3_8821C)
+#define BIT_CLEAR_PS_AID_3_8821C(x) ((x) & (~BITS_PS_AID_3_8821C))
+#define BIT_GET_PS_AID_3_8821C(x) \
+ (((x) >> BIT_SHIFT_PS_AID_3_8821C) & BIT_MASK_PS_AID_3_8821C)
+#define BIT_SET_PS_AID_3_8821C(x, v) \
+ (BIT_CLEAR_PS_AID_3_8821C(x) | BIT_PS_AID_3_8821C(v))
/* 2 REG_BCN_PSR_RPT4_8821C (BEACON PARSER REPORT REGISTER4) */
#define BIT_SHIFT_DTIM_CNT4_8821C 24
#define BIT_MASK_DTIM_CNT4_8821C 0xff
-#define BIT_DTIM_CNT4_8821C(x) (((x) & BIT_MASK_DTIM_CNT4_8821C) << BIT_SHIFT_DTIM_CNT4_8821C)
-#define BIT_GET_DTIM_CNT4_8821C(x) (((x) >> BIT_SHIFT_DTIM_CNT4_8821C) & BIT_MASK_DTIM_CNT4_8821C)
-
+#define BIT_DTIM_CNT4_8821C(x) \
+ (((x) & BIT_MASK_DTIM_CNT4_8821C) << BIT_SHIFT_DTIM_CNT4_8821C)
+#define BITS_DTIM_CNT4_8821C \
+ (BIT_MASK_DTIM_CNT4_8821C << BIT_SHIFT_DTIM_CNT4_8821C)
+#define BIT_CLEAR_DTIM_CNT4_8821C(x) ((x) & (~BITS_DTIM_CNT4_8821C))
+#define BIT_GET_DTIM_CNT4_8821C(x) \
+ (((x) >> BIT_SHIFT_DTIM_CNT4_8821C) & BIT_MASK_DTIM_CNT4_8821C)
+#define BIT_SET_DTIM_CNT4_8821C(x, v) \
+ (BIT_CLEAR_DTIM_CNT4_8821C(x) | BIT_DTIM_CNT4_8821C(v))
#define BIT_SHIFT_DTIM_PERIOD4_8821C 16
#define BIT_MASK_DTIM_PERIOD4_8821C 0xff
-#define BIT_DTIM_PERIOD4_8821C(x) (((x) & BIT_MASK_DTIM_PERIOD4_8821C) << BIT_SHIFT_DTIM_PERIOD4_8821C)
-#define BIT_GET_DTIM_PERIOD4_8821C(x) (((x) >> BIT_SHIFT_DTIM_PERIOD4_8821C) & BIT_MASK_DTIM_PERIOD4_8821C)
+#define BIT_DTIM_PERIOD4_8821C(x) \
+ (((x) & BIT_MASK_DTIM_PERIOD4_8821C) << BIT_SHIFT_DTIM_PERIOD4_8821C)
+#define BITS_DTIM_PERIOD4_8821C \
+ (BIT_MASK_DTIM_PERIOD4_8821C << BIT_SHIFT_DTIM_PERIOD4_8821C)
+#define BIT_CLEAR_DTIM_PERIOD4_8821C(x) ((x) & (~BITS_DTIM_PERIOD4_8821C))
+#define BIT_GET_DTIM_PERIOD4_8821C(x) \
+ (((x) >> BIT_SHIFT_DTIM_PERIOD4_8821C) & BIT_MASK_DTIM_PERIOD4_8821C)
+#define BIT_SET_DTIM_PERIOD4_8821C(x, v) \
+ (BIT_CLEAR_DTIM_PERIOD4_8821C(x) | BIT_DTIM_PERIOD4_8821C(v))
#define BIT_DTIM4_8821C BIT(15)
#define BIT_TIM4_8821C BIT(14)
#define BIT_SHIFT_PS_AID_4_8821C 0
#define BIT_MASK_PS_AID_4_8821C 0x7ff
-#define BIT_PS_AID_4_8821C(x) (((x) & BIT_MASK_PS_AID_4_8821C) << BIT_SHIFT_PS_AID_4_8821C)
-#define BIT_GET_PS_AID_4_8821C(x) (((x) >> BIT_SHIFT_PS_AID_4_8821C) & BIT_MASK_PS_AID_4_8821C)
-
+#define BIT_PS_AID_4_8821C(x) \
+ (((x) & BIT_MASK_PS_AID_4_8821C) << BIT_SHIFT_PS_AID_4_8821C)
+#define BITS_PS_AID_4_8821C \
+ (BIT_MASK_PS_AID_4_8821C << BIT_SHIFT_PS_AID_4_8821C)
+#define BIT_CLEAR_PS_AID_4_8821C(x) ((x) & (~BITS_PS_AID_4_8821C))
+#define BIT_GET_PS_AID_4_8821C(x) \
+ (((x) >> BIT_SHIFT_PS_AID_4_8821C) & BIT_MASK_PS_AID_4_8821C)
+#define BIT_SET_PS_AID_4_8821C(x, v) \
+ (BIT_CLEAR_PS_AID_4_8821C(x) | BIT_PS_AID_4_8821C(v))
/* 2 REG_A1_ADDR_MASK_8821C (A1 ADDR MASK REGISTER) */
#define BIT_SHIFT_A1_ADDR_MASK_8821C 0
#define BIT_MASK_A1_ADDR_MASK_8821C 0xffffffffL
-#define BIT_A1_ADDR_MASK_8821C(x) (((x) & BIT_MASK_A1_ADDR_MASK_8821C) << BIT_SHIFT_A1_ADDR_MASK_8821C)
-#define BIT_GET_A1_ADDR_MASK_8821C(x) (((x) >> BIT_SHIFT_A1_ADDR_MASK_8821C) & BIT_MASK_A1_ADDR_MASK_8821C)
+#define BIT_A1_ADDR_MASK_8821C(x) \
+ (((x) & BIT_MASK_A1_ADDR_MASK_8821C) << BIT_SHIFT_A1_ADDR_MASK_8821C)
+#define BITS_A1_ADDR_MASK_8821C \
+ (BIT_MASK_A1_ADDR_MASK_8821C << BIT_SHIFT_A1_ADDR_MASK_8821C)
+#define BIT_CLEAR_A1_ADDR_MASK_8821C(x) ((x) & (~BITS_A1_ADDR_MASK_8821C))
+#define BIT_GET_A1_ADDR_MASK_8821C(x) \
+ (((x) >> BIT_SHIFT_A1_ADDR_MASK_8821C) & BIT_MASK_A1_ADDR_MASK_8821C)
+#define BIT_SET_A1_ADDR_MASK_8821C(x, v) \
+ (BIT_CLEAR_A1_ADDR_MASK_8821C(x) | BIT_A1_ADDR_MASK_8821C(v))
+/* 2 REG_RSVD_8821C */
-/* 2 REG_MACID2_8821C (MAC ID2 REGISTER) */
+/* 2 REG_RSVD_8821C */
-#define BIT_SHIFT_MACID2_8821C 0
-#define BIT_MASK_MACID2_8821C 0xffffffffffffL
-#define BIT_MACID2_8821C(x) (((x) & BIT_MASK_MACID2_8821C) << BIT_SHIFT_MACID2_8821C)
-#define BIT_GET_MACID2_8821C(x) (((x) >> BIT_SHIFT_MACID2_8821C) & BIT_MASK_MACID2_8821C)
+/* 2 REG_RSVD_8821C */
+/* 2 REG_RSVD_8821C */
-/* 2 REG_BSSID2_8821C (BSSID2 REGISTER) */
+/* 2 REG_MACID2_8821C (MAC ID2 REGISTER) */
-#define BIT_SHIFT_BSSID2_8821C 0
-#define BIT_MASK_BSSID2_8821C 0xffffffffffffL
-#define BIT_BSSID2_8821C(x) (((x) & BIT_MASK_BSSID2_8821C) << BIT_SHIFT_BSSID2_8821C)
-#define BIT_GET_BSSID2_8821C(x) (((x) >> BIT_SHIFT_BSSID2_8821C) & BIT_MASK_BSSID2_8821C)
+#define BIT_SHIFT_MACID2_V1_8821C 0
+#define BIT_MASK_MACID2_V1_8821C 0xffffffffL
+#define BIT_MACID2_V1_8821C(x) \
+ (((x) & BIT_MASK_MACID2_V1_8821C) << BIT_SHIFT_MACID2_V1_8821C)
+#define BITS_MACID2_V1_8821C \
+ (BIT_MASK_MACID2_V1_8821C << BIT_SHIFT_MACID2_V1_8821C)
+#define BIT_CLEAR_MACID2_V1_8821C(x) ((x) & (~BITS_MACID2_V1_8821C))
+#define BIT_GET_MACID2_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_MACID2_V1_8821C) & BIT_MASK_MACID2_V1_8821C)
+#define BIT_SET_MACID2_V1_8821C(x, v) \
+ (BIT_CLEAR_MACID2_V1_8821C(x) | BIT_MACID2_V1_8821C(v))
+
+/* 2 REG_MACID2_H_8821C (MAC ID2 REGISTER) */
+
+#define BIT_SHIFT_MACID2_H_V1_8821C 0
+#define BIT_MASK_MACID2_H_V1_8821C 0xffff
+#define BIT_MACID2_H_V1_8821C(x) \
+ (((x) & BIT_MASK_MACID2_H_V1_8821C) << BIT_SHIFT_MACID2_H_V1_8821C)
+#define BITS_MACID2_H_V1_8821C \
+ (BIT_MASK_MACID2_H_V1_8821C << BIT_SHIFT_MACID2_H_V1_8821C)
+#define BIT_CLEAR_MACID2_H_V1_8821C(x) ((x) & (~BITS_MACID2_H_V1_8821C))
+#define BIT_GET_MACID2_H_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_MACID2_H_V1_8821C) & BIT_MASK_MACID2_H_V1_8821C)
+#define BIT_SET_MACID2_H_V1_8821C(x, v) \
+ (BIT_CLEAR_MACID2_H_V1_8821C(x) | BIT_MACID2_H_V1_8821C(v))
+/* 2 REG_BSSID2_8821C (BSSID2 REGISTER) */
-/* 2 REG_MACID3_8821C (MAC ID3 REGISTER) */
+#define BIT_SHIFT_BSSID2_V1_8821C 0
+#define BIT_MASK_BSSID2_V1_8821C 0xffffffffL
+#define BIT_BSSID2_V1_8821C(x) \
+ (((x) & BIT_MASK_BSSID2_V1_8821C) << BIT_SHIFT_BSSID2_V1_8821C)
+#define BITS_BSSID2_V1_8821C \
+ (BIT_MASK_BSSID2_V1_8821C << BIT_SHIFT_BSSID2_V1_8821C)
+#define BIT_CLEAR_BSSID2_V1_8821C(x) ((x) & (~BITS_BSSID2_V1_8821C))
+#define BIT_GET_BSSID2_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_BSSID2_V1_8821C) & BIT_MASK_BSSID2_V1_8821C)
+#define BIT_SET_BSSID2_V1_8821C(x, v) \
+ (BIT_CLEAR_BSSID2_V1_8821C(x) | BIT_BSSID2_V1_8821C(v))
+
+/* 2 REG_BSSID2_H_8821C (BSSID2 REGISTER) */
+
+#define BIT_SHIFT_BSSID2_H_V1_8821C 0
+#define BIT_MASK_BSSID2_H_V1_8821C 0xffff
+#define BIT_BSSID2_H_V1_8821C(x) \
+ (((x) & BIT_MASK_BSSID2_H_V1_8821C) << BIT_SHIFT_BSSID2_H_V1_8821C)
+#define BITS_BSSID2_H_V1_8821C \
+ (BIT_MASK_BSSID2_H_V1_8821C << BIT_SHIFT_BSSID2_H_V1_8821C)
+#define BIT_CLEAR_BSSID2_H_V1_8821C(x) ((x) & (~BITS_BSSID2_H_V1_8821C))
+#define BIT_GET_BSSID2_H_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_BSSID2_H_V1_8821C) & BIT_MASK_BSSID2_H_V1_8821C)
+#define BIT_SET_BSSID2_H_V1_8821C(x, v) \
+ (BIT_CLEAR_BSSID2_H_V1_8821C(x) | BIT_BSSID2_H_V1_8821C(v))
-#define BIT_SHIFT_MACID3_8821C 0
-#define BIT_MASK_MACID3_8821C 0xffffffffffffL
-#define BIT_MACID3_8821C(x) (((x) & BIT_MASK_MACID3_8821C) << BIT_SHIFT_MACID3_8821C)
-#define BIT_GET_MACID3_8821C(x) (((x) >> BIT_SHIFT_MACID3_8821C) & BIT_MASK_MACID3_8821C)
+/* 2 REG_MACID3_8821C (MAC ID3 REGISTER) */
+#define BIT_SHIFT_MACID3_V1_8821C 0
+#define BIT_MASK_MACID3_V1_8821C 0xffffffffL
+#define BIT_MACID3_V1_8821C(x) \
+ (((x) & BIT_MASK_MACID3_V1_8821C) << BIT_SHIFT_MACID3_V1_8821C)
+#define BITS_MACID3_V1_8821C \
+ (BIT_MASK_MACID3_V1_8821C << BIT_SHIFT_MACID3_V1_8821C)
+#define BIT_CLEAR_MACID3_V1_8821C(x) ((x) & (~BITS_MACID3_V1_8821C))
+#define BIT_GET_MACID3_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_MACID3_V1_8821C) & BIT_MASK_MACID3_V1_8821C)
+#define BIT_SET_MACID3_V1_8821C(x, v) \
+ (BIT_CLEAR_MACID3_V1_8821C(x) | BIT_MACID3_V1_8821C(v))
+
+/* 2 REG_MACID3_H_8821C (MAC ID3 REGISTER) */
+
+#define BIT_SHIFT_MACID3_H_V1_8821C 0
+#define BIT_MASK_MACID3_H_V1_8821C 0xffff
+#define BIT_MACID3_H_V1_8821C(x) \
+ (((x) & BIT_MASK_MACID3_H_V1_8821C) << BIT_SHIFT_MACID3_H_V1_8821C)
+#define BITS_MACID3_H_V1_8821C \
+ (BIT_MASK_MACID3_H_V1_8821C << BIT_SHIFT_MACID3_H_V1_8821C)
+#define BIT_CLEAR_MACID3_H_V1_8821C(x) ((x) & (~BITS_MACID3_H_V1_8821C))
+#define BIT_GET_MACID3_H_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_MACID3_H_V1_8821C) & BIT_MASK_MACID3_H_V1_8821C)
+#define BIT_SET_MACID3_H_V1_8821C(x, v) \
+ (BIT_CLEAR_MACID3_H_V1_8821C(x) | BIT_MACID3_H_V1_8821C(v))
/* 2 REG_BSSID3_8821C (BSSID3 REGISTER) */
-#define BIT_SHIFT_BSSID3_8821C 0
-#define BIT_MASK_BSSID3_8821C 0xffffffffffffL
-#define BIT_BSSID3_8821C(x) (((x) & BIT_MASK_BSSID3_8821C) << BIT_SHIFT_BSSID3_8821C)
-#define BIT_GET_BSSID3_8821C(x) (((x) >> BIT_SHIFT_BSSID3_8821C) & BIT_MASK_BSSID3_8821C)
-
+#define BIT_SHIFT_BSSID3_V1_8821C 0
+#define BIT_MASK_BSSID3_V1_8821C 0xffffffffL
+#define BIT_BSSID3_V1_8821C(x) \
+ (((x) & BIT_MASK_BSSID3_V1_8821C) << BIT_SHIFT_BSSID3_V1_8821C)
+#define BITS_BSSID3_V1_8821C \
+ (BIT_MASK_BSSID3_V1_8821C << BIT_SHIFT_BSSID3_V1_8821C)
+#define BIT_CLEAR_BSSID3_V1_8821C(x) ((x) & (~BITS_BSSID3_V1_8821C))
+#define BIT_GET_BSSID3_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_BSSID3_V1_8821C) & BIT_MASK_BSSID3_V1_8821C)
+#define BIT_SET_BSSID3_V1_8821C(x, v) \
+ (BIT_CLEAR_BSSID3_V1_8821C(x) | BIT_BSSID3_V1_8821C(v))
+
+/* 2 REG_BSSID3_H_8821C (BSSID3 REGISTER) */
+
+#define BIT_SHIFT_BSSID3_H_V1_8821C 0
+#define BIT_MASK_BSSID3_H_V1_8821C 0xffff
+#define BIT_BSSID3_H_V1_8821C(x) \
+ (((x) & BIT_MASK_BSSID3_H_V1_8821C) << BIT_SHIFT_BSSID3_H_V1_8821C)
+#define BITS_BSSID3_H_V1_8821C \
+ (BIT_MASK_BSSID3_H_V1_8821C << BIT_SHIFT_BSSID3_H_V1_8821C)
+#define BIT_CLEAR_BSSID3_H_V1_8821C(x) ((x) & (~BITS_BSSID3_H_V1_8821C))
+#define BIT_GET_BSSID3_H_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_BSSID3_H_V1_8821C) & BIT_MASK_BSSID3_H_V1_8821C)
+#define BIT_SET_BSSID3_H_V1_8821C(x, v) \
+ (BIT_CLEAR_BSSID3_H_V1_8821C(x) | BIT_BSSID3_H_V1_8821C(v))
/* 2 REG_MACID4_8821C (MAC ID4 REGISTER) */
-#define BIT_SHIFT_MACID4_8821C 0
-#define BIT_MASK_MACID4_8821C 0xffffffffffffL
-#define BIT_MACID4_8821C(x) (((x) & BIT_MASK_MACID4_8821C) << BIT_SHIFT_MACID4_8821C)
-#define BIT_GET_MACID4_8821C(x) (((x) >> BIT_SHIFT_MACID4_8821C) & BIT_MASK_MACID4_8821C)
-
+#define BIT_SHIFT_MACID4_V1_8821C 0
+#define BIT_MASK_MACID4_V1_8821C 0xffffffffL
+#define BIT_MACID4_V1_8821C(x) \
+ (((x) & BIT_MASK_MACID4_V1_8821C) << BIT_SHIFT_MACID4_V1_8821C)
+#define BITS_MACID4_V1_8821C \
+ (BIT_MASK_MACID4_V1_8821C << BIT_SHIFT_MACID4_V1_8821C)
+#define BIT_CLEAR_MACID4_V1_8821C(x) ((x) & (~BITS_MACID4_V1_8821C))
+#define BIT_GET_MACID4_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_MACID4_V1_8821C) & BIT_MASK_MACID4_V1_8821C)
+#define BIT_SET_MACID4_V1_8821C(x, v) \
+ (BIT_CLEAR_MACID4_V1_8821C(x) | BIT_MACID4_V1_8821C(v))
+
+/* 2 REG_MACID4_H_8821C (MAC ID4 REGISTER) */
+
+#define BIT_SHIFT_MACID4_H_V1_8821C 0
+#define BIT_MASK_MACID4_H_V1_8821C 0xffff
+#define BIT_MACID4_H_V1_8821C(x) \
+ (((x) & BIT_MASK_MACID4_H_V1_8821C) << BIT_SHIFT_MACID4_H_V1_8821C)
+#define BITS_MACID4_H_V1_8821C \
+ (BIT_MASK_MACID4_H_V1_8821C << BIT_SHIFT_MACID4_H_V1_8821C)
+#define BIT_CLEAR_MACID4_H_V1_8821C(x) ((x) & (~BITS_MACID4_H_V1_8821C))
+#define BIT_GET_MACID4_H_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_MACID4_H_V1_8821C) & BIT_MASK_MACID4_H_V1_8821C)
+#define BIT_SET_MACID4_H_V1_8821C(x, v) \
+ (BIT_CLEAR_MACID4_H_V1_8821C(x) | BIT_MACID4_H_V1_8821C(v))
/* 2 REG_BSSID4_8821C (BSSID4 REGISTER) */
-#define BIT_SHIFT_BSSID4_8821C 0
-#define BIT_MASK_BSSID4_8821C 0xffffffffffffL
-#define BIT_BSSID4_8821C(x) (((x) & BIT_MASK_BSSID4_8821C) << BIT_SHIFT_BSSID4_8821C)
-#define BIT_GET_BSSID4_8821C(x) (((x) >> BIT_SHIFT_BSSID4_8821C) & BIT_MASK_BSSID4_8821C)
-
+#define BIT_SHIFT_BSSID4_V1_8821C 0
+#define BIT_MASK_BSSID4_V1_8821C 0xffffffffL
+#define BIT_BSSID4_V1_8821C(x) \
+ (((x) & BIT_MASK_BSSID4_V1_8821C) << BIT_SHIFT_BSSID4_V1_8821C)
+#define BITS_BSSID4_V1_8821C \
+ (BIT_MASK_BSSID4_V1_8821C << BIT_SHIFT_BSSID4_V1_8821C)
+#define BIT_CLEAR_BSSID4_V1_8821C(x) ((x) & (~BITS_BSSID4_V1_8821C))
+#define BIT_GET_BSSID4_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_BSSID4_V1_8821C) & BIT_MASK_BSSID4_V1_8821C)
+#define BIT_SET_BSSID4_V1_8821C(x, v) \
+ (BIT_CLEAR_BSSID4_V1_8821C(x) | BIT_BSSID4_V1_8821C(v))
+
+/* 2 REG_BSSID4_H_8821C (BSSID4 REGISTER) */
+
+#define BIT_SHIFT_BSSID4_H_V1_8821C 0
+#define BIT_MASK_BSSID4_H_V1_8821C 0xffff
+#define BIT_BSSID4_H_V1_8821C(x) \
+ (((x) & BIT_MASK_BSSID4_H_V1_8821C) << BIT_SHIFT_BSSID4_H_V1_8821C)
+#define BITS_BSSID4_H_V1_8821C \
+ (BIT_MASK_BSSID4_H_V1_8821C << BIT_SHIFT_BSSID4_H_V1_8821C)
+#define BIT_CLEAR_BSSID4_H_V1_8821C(x) ((x) & (~BITS_BSSID4_H_V1_8821C))
+#define BIT_GET_BSSID4_H_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_BSSID4_H_V1_8821C) & BIT_MASK_BSSID4_H_V1_8821C)
+#define BIT_SET_BSSID4_H_V1_8821C(x, v) \
+ (BIT_CLEAR_BSSID4_H_V1_8821C(x) | BIT_BSSID4_H_V1_8821C(v))
/* 2 REG_NOA_REPORT_8821C */
+/* 2 REG_NOA_REPORT_1_8821C */
+
+/* 2 REG_NOA_REPORT_2_8821C */
+
+/* 2 REG_NOA_REPORT_3_8821C */
+
/* 2 REG_PWRBIT_SETTING_8821C */
#define BIT_CLI3_PWRBIT_OW_EN_8821C BIT(7)
#define BIT_CLI3_PWR_ST_8821C BIT(6)
@@ -8817,115 +16590,690 @@
#define BIT_CLI0_PWRBIT_OW_EN_8821C BIT(1)
#define BIT_CLI0_PWR_ST_8821C BIT(0)
-/* 2 REG_NOT_VALID_8821C */
-
-/* 2 REG_NOT_VALID_8821C */
-
-/* 2 REG_NOT_VALID_8821C */
-
-/* 2 REG_NOT_VALID_8821C */
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_RSVD_8821C */
+
+/* 2 REG_MU_BF_OPTION_8821C */
+#define BIT_WMAC_RESP_NONSTA1_DIS_8821C BIT(7)
+#define BIT_WMAC_TXMU_ACKPOLICY_EN_8821C BIT(6)
+
+#define BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8821C 4
+#define BIT_MASK_WMAC_TXMU_ACKPOLICY_8821C 0x3
+#define BIT_WMAC_TXMU_ACKPOLICY_8821C(x) \
+ (((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8821C) \
+ << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8821C)
+#define BITS_WMAC_TXMU_ACKPOLICY_8821C \
+ (BIT_MASK_WMAC_TXMU_ACKPOLICY_8821C \
+ << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8821C)
+#define BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8821C(x) \
+ ((x) & (~BITS_WMAC_TXMU_ACKPOLICY_8821C))
+#define BIT_GET_WMAC_TXMU_ACKPOLICY_8821C(x) \
+ (((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8821C) & \
+ BIT_MASK_WMAC_TXMU_ACKPOLICY_8821C)
+#define BIT_SET_WMAC_TXMU_ACKPOLICY_8821C(x, v) \
+ (BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8821C(x) | \
+ BIT_WMAC_TXMU_ACKPOLICY_8821C(v))
+
+#define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8821C 1
+#define BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8821C 0x7
+#define BIT_WMAC_MU_BFEE_PORT_SEL_8821C(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8821C) \
+ << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8821C)
+#define BITS_WMAC_MU_BFEE_PORT_SEL_8821C \
+ (BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8821C \
+ << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8821C)
+#define BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8821C(x) \
+ ((x) & (~BITS_WMAC_MU_BFEE_PORT_SEL_8821C))
+#define BIT_GET_WMAC_MU_BFEE_PORT_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8821C) & \
+ BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8821C)
+#define BIT_SET_WMAC_MU_BFEE_PORT_SEL_8821C(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8821C(x) | \
+ BIT_WMAC_MU_BFEE_PORT_SEL_8821C(v))
+
+#define BIT_WMAC_MU_BFEE_DIS_8821C BIT(0)
+
+/* 2 REG_WMAC_PAUSE_BB_CLR_TH_8821C */
+
+#define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8821C 0
+#define BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8821C 0xff
+#define BIT_WMAC_PAUSE_BB_CLR_TH_8821C(x) \
+ (((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8821C) \
+ << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8821C)
+#define BITS_WMAC_PAUSE_BB_CLR_TH_8821C \
+ (BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8821C \
+ << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8821C)
+#define BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8821C(x) \
+ ((x) & (~BITS_WMAC_PAUSE_BB_CLR_TH_8821C))
+#define BIT_GET_WMAC_PAUSE_BB_CLR_TH_8821C(x) \
+ (((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8821C) & \
+ BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8821C)
+#define BIT_SET_WMAC_PAUSE_BB_CLR_TH_8821C(x, v) \
+ (BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8821C(x) | \
+ BIT_WMAC_PAUSE_BB_CLR_TH_8821C(v))
+
+/* 2 REG_WMAC_MU_ARB_8821C */
+#define BIT_WMAC_ARB_HW_ADAPT_EN_8821C BIT(7)
+#define BIT_WMAC_ARB_SW_EN_8821C BIT(6)
+
+#define BIT_SHIFT_WMAC_ARB_SW_STATE_8821C 0
+#define BIT_MASK_WMAC_ARB_SW_STATE_8821C 0x3f
+#define BIT_WMAC_ARB_SW_STATE_8821C(x) \
+ (((x) & BIT_MASK_WMAC_ARB_SW_STATE_8821C) \
+ << BIT_SHIFT_WMAC_ARB_SW_STATE_8821C)
+#define BITS_WMAC_ARB_SW_STATE_8821C \
+ (BIT_MASK_WMAC_ARB_SW_STATE_8821C << BIT_SHIFT_WMAC_ARB_SW_STATE_8821C)
+#define BIT_CLEAR_WMAC_ARB_SW_STATE_8821C(x) \
+ ((x) & (~BITS_WMAC_ARB_SW_STATE_8821C))
+#define BIT_GET_WMAC_ARB_SW_STATE_8821C(x) \
+ (((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE_8821C) & \
+ BIT_MASK_WMAC_ARB_SW_STATE_8821C)
+#define BIT_SET_WMAC_ARB_SW_STATE_8821C(x, v) \
+ (BIT_CLEAR_WMAC_ARB_SW_STATE_8821C(x) | BIT_WMAC_ARB_SW_STATE_8821C(v))
+
+/* 2 REG_WMAC_MU_OPTION_8821C */
+
+#define BIT_SHIFT_WMAC_MU_DBGSEL_8821C 5
+#define BIT_MASK_WMAC_MU_DBGSEL_8821C 0x3
+#define BIT_WMAC_MU_DBGSEL_8821C(x) \
+ (((x) & BIT_MASK_WMAC_MU_DBGSEL_8821C) \
+ << BIT_SHIFT_WMAC_MU_DBGSEL_8821C)
+#define BITS_WMAC_MU_DBGSEL_8821C \
+ (BIT_MASK_WMAC_MU_DBGSEL_8821C << BIT_SHIFT_WMAC_MU_DBGSEL_8821C)
+#define BIT_CLEAR_WMAC_MU_DBGSEL_8821C(x) ((x) & (~BITS_WMAC_MU_DBGSEL_8821C))
+#define BIT_GET_WMAC_MU_DBGSEL_8821C(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_8821C) & \
+ BIT_MASK_WMAC_MU_DBGSEL_8821C)
+#define BIT_SET_WMAC_MU_DBGSEL_8821C(x, v) \
+ (BIT_CLEAR_WMAC_MU_DBGSEL_8821C(x) | BIT_WMAC_MU_DBGSEL_8821C(v))
+
+#define BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8821C 0
+#define BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8821C 0x1f
+#define BIT_WMAC_MU_CPRD_TIMEOUT_8821C(x) \
+ (((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8821C) \
+ << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8821C)
+#define BITS_WMAC_MU_CPRD_TIMEOUT_8821C \
+ (BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8821C \
+ << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8821C)
+#define BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT_8821C(x) \
+ ((x) & (~BITS_WMAC_MU_CPRD_TIMEOUT_8821C))
+#define BIT_GET_WMAC_MU_CPRD_TIMEOUT_8821C(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8821C) & \
+ BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8821C)
+#define BIT_SET_WMAC_MU_CPRD_TIMEOUT_8821C(x, v) \
+ (BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT_8821C(x) | \
+ BIT_WMAC_MU_CPRD_TIMEOUT_8821C(v))
+
+/* 2 REG_WMAC_MU_BF_CTL_8821C */
+#define BIT_WMAC_INVLD_BFPRT_CHK_8821C BIT(15)
+#define BIT_WMAC_RETXBFRPTSEQ_UPD_8821C BIT(14)
+
+#define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8821C 12
+#define BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8821C 0x3
+#define BIT_WMAC_MU_BFRPTSEG_SEL_8821C(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8821C) \
+ << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8821C)
+#define BITS_WMAC_MU_BFRPTSEG_SEL_8821C \
+ (BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8821C \
+ << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8821C)
+#define BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8821C(x) \
+ ((x) & (~BITS_WMAC_MU_BFRPTSEG_SEL_8821C))
+#define BIT_GET_WMAC_MU_BFRPTSEG_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8821C) & \
+ BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8821C)
+#define BIT_SET_WMAC_MU_BFRPTSEG_SEL_8821C(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8821C(x) | \
+ BIT_WMAC_MU_BFRPTSEG_SEL_8821C(v))
+
+#define BIT_SHIFT_WMAC_MU_BF_MYAID_8821C 0
+#define BIT_MASK_WMAC_MU_BF_MYAID_8821C 0xfff
+#define BIT_WMAC_MU_BF_MYAID_8821C(x) \
+ (((x) & BIT_MASK_WMAC_MU_BF_MYAID_8821C) \
+ << BIT_SHIFT_WMAC_MU_BF_MYAID_8821C)
+#define BITS_WMAC_MU_BF_MYAID_8821C \
+ (BIT_MASK_WMAC_MU_BF_MYAID_8821C << BIT_SHIFT_WMAC_MU_BF_MYAID_8821C)
+#define BIT_CLEAR_WMAC_MU_BF_MYAID_8821C(x) \
+ ((x) & (~BITS_WMAC_MU_BF_MYAID_8821C))
+#define BIT_GET_WMAC_MU_BF_MYAID_8821C(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID_8821C) & \
+ BIT_MASK_WMAC_MU_BF_MYAID_8821C)
+#define BIT_SET_WMAC_MU_BF_MYAID_8821C(x, v) \
+ (BIT_CLEAR_WMAC_MU_BF_MYAID_8821C(x) | BIT_WMAC_MU_BF_MYAID_8821C(v))
+
+/* 2 REG_WMAC_MU_BFRPT_PARA_8821C */
+
+#define BIT_SHIFT_BFRPT_PARA_USERID_SEL_8821C 12
+#define BIT_MASK_BFRPT_PARA_USERID_SEL_8821C 0x7
+#define BIT_BFRPT_PARA_USERID_SEL_8821C(x) \
+ (((x) & BIT_MASK_BFRPT_PARA_USERID_SEL_8821C) \
+ << BIT_SHIFT_BFRPT_PARA_USERID_SEL_8821C)
+#define BITS_BFRPT_PARA_USERID_SEL_8821C \
+ (BIT_MASK_BFRPT_PARA_USERID_SEL_8821C \
+ << BIT_SHIFT_BFRPT_PARA_USERID_SEL_8821C)
+#define BIT_CLEAR_BFRPT_PARA_USERID_SEL_8821C(x) \
+ ((x) & (~BITS_BFRPT_PARA_USERID_SEL_8821C))
+#define BIT_GET_BFRPT_PARA_USERID_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL_8821C) & \
+ BIT_MASK_BFRPT_PARA_USERID_SEL_8821C)
+#define BIT_SET_BFRPT_PARA_USERID_SEL_8821C(x, v) \
+ (BIT_CLEAR_BFRPT_PARA_USERID_SEL_8821C(x) | \
+ BIT_BFRPT_PARA_USERID_SEL_8821C(v))
+
+#define BIT_SHIFT_BFRPT_PARA_8821C 0
+#define BIT_MASK_BFRPT_PARA_8821C 0xfff
+#define BIT_BFRPT_PARA_8821C(x) \
+ (((x) & BIT_MASK_BFRPT_PARA_8821C) << BIT_SHIFT_BFRPT_PARA_8821C)
+#define BITS_BFRPT_PARA_8821C \
+ (BIT_MASK_BFRPT_PARA_8821C << BIT_SHIFT_BFRPT_PARA_8821C)
+#define BIT_CLEAR_BFRPT_PARA_8821C(x) ((x) & (~BITS_BFRPT_PARA_8821C))
+#define BIT_GET_BFRPT_PARA_8821C(x) \
+ (((x) >> BIT_SHIFT_BFRPT_PARA_8821C) & BIT_MASK_BFRPT_PARA_8821C)
+#define BIT_SET_BFRPT_PARA_8821C(x, v) \
+ (BIT_CLEAR_BFRPT_PARA_8821C(x) | BIT_BFRPT_PARA_8821C(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2_8821C */
+#define BIT_STATUS_BFEE2_8821C BIT(10)
+#define BIT_WMAC_MU_BFEE2_EN_8821C BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE2_AID_8821C 0
+#define BIT_MASK_WMAC_MU_BFEE2_AID_8821C 0x1ff
+#define BIT_WMAC_MU_BFEE2_AID_8821C(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE2_AID_8821C) \
+ << BIT_SHIFT_WMAC_MU_BFEE2_AID_8821C)
+#define BITS_WMAC_MU_BFEE2_AID_8821C \
+ (BIT_MASK_WMAC_MU_BFEE2_AID_8821C << BIT_SHIFT_WMAC_MU_BFEE2_AID_8821C)
+#define BIT_CLEAR_WMAC_MU_BFEE2_AID_8821C(x) \
+ ((x) & (~BITS_WMAC_MU_BFEE2_AID_8821C))
+#define BIT_GET_WMAC_MU_BFEE2_AID_8821C(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID_8821C) & \
+ BIT_MASK_WMAC_MU_BFEE2_AID_8821C)
+#define BIT_SET_WMAC_MU_BFEE2_AID_8821C(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE2_AID_8821C(x) | BIT_WMAC_MU_BFEE2_AID_8821C(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3_8821C */
+#define BIT_STATUS_BFEE3_8821C BIT(10)
+#define BIT_WMAC_MU_BFEE3_EN_8821C BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE3_AID_8821C 0
+#define BIT_MASK_WMAC_MU_BFEE3_AID_8821C 0x1ff
+#define BIT_WMAC_MU_BFEE3_AID_8821C(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE3_AID_8821C) \
+ << BIT_SHIFT_WMAC_MU_BFEE3_AID_8821C)
+#define BITS_WMAC_MU_BFEE3_AID_8821C \
+ (BIT_MASK_WMAC_MU_BFEE3_AID_8821C << BIT_SHIFT_WMAC_MU_BFEE3_AID_8821C)
+#define BIT_CLEAR_WMAC_MU_BFEE3_AID_8821C(x) \
+ ((x) & (~BITS_WMAC_MU_BFEE3_AID_8821C))
+#define BIT_GET_WMAC_MU_BFEE3_AID_8821C(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID_8821C) & \
+ BIT_MASK_WMAC_MU_BFEE3_AID_8821C)
+#define BIT_SET_WMAC_MU_BFEE3_AID_8821C(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE3_AID_8821C(x) | BIT_WMAC_MU_BFEE3_AID_8821C(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4_8821C */
+#define BIT_STATUS_BFEE4_8821C BIT(10)
+#define BIT_WMAC_MU_BFEE4_EN_8821C BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE4_AID_8821C 0
+#define BIT_MASK_WMAC_MU_BFEE4_AID_8821C 0x1ff
+#define BIT_WMAC_MU_BFEE4_AID_8821C(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE4_AID_8821C) \
+ << BIT_SHIFT_WMAC_MU_BFEE4_AID_8821C)
+#define BITS_WMAC_MU_BFEE4_AID_8821C \
+ (BIT_MASK_WMAC_MU_BFEE4_AID_8821C << BIT_SHIFT_WMAC_MU_BFEE4_AID_8821C)
+#define BIT_CLEAR_WMAC_MU_BFEE4_AID_8821C(x) \
+ ((x) & (~BITS_WMAC_MU_BFEE4_AID_8821C))
+#define BIT_GET_WMAC_MU_BFEE4_AID_8821C(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID_8821C) & \
+ BIT_MASK_WMAC_MU_BFEE4_AID_8821C)
+#define BIT_SET_WMAC_MU_BFEE4_AID_8821C(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE4_AID_8821C(x) | BIT_WMAC_MU_BFEE4_AID_8821C(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5_8821C */
+#define BIT_BIT_STATUS_BFEE5_8821C BIT(10)
+#define BIT_WMAC_MU_BFEE5_EN_8821C BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE5_AID_8821C 0
+#define BIT_MASK_WMAC_MU_BFEE5_AID_8821C 0x1ff
+#define BIT_WMAC_MU_BFEE5_AID_8821C(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE5_AID_8821C) \
+ << BIT_SHIFT_WMAC_MU_BFEE5_AID_8821C)
+#define BITS_WMAC_MU_BFEE5_AID_8821C \
+ (BIT_MASK_WMAC_MU_BFEE5_AID_8821C << BIT_SHIFT_WMAC_MU_BFEE5_AID_8821C)
+#define BIT_CLEAR_WMAC_MU_BFEE5_AID_8821C(x) \
+ ((x) & (~BITS_WMAC_MU_BFEE5_AID_8821C))
+#define BIT_GET_WMAC_MU_BFEE5_AID_8821C(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID_8821C) & \
+ BIT_MASK_WMAC_MU_BFEE5_AID_8821C)
+#define BIT_SET_WMAC_MU_BFEE5_AID_8821C(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE5_AID_8821C(x) | BIT_WMAC_MU_BFEE5_AID_8821C(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6_8821C */
+#define BIT_STATUS_BFEE6_8821C BIT(10)
+#define BIT_WMAC_MU_BFEE6_EN_8821C BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE6_AID_8821C 0
+#define BIT_MASK_WMAC_MU_BFEE6_AID_8821C 0x1ff
+#define BIT_WMAC_MU_BFEE6_AID_8821C(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE6_AID_8821C) \
+ << BIT_SHIFT_WMAC_MU_BFEE6_AID_8821C)
+#define BITS_WMAC_MU_BFEE6_AID_8821C \
+ (BIT_MASK_WMAC_MU_BFEE6_AID_8821C << BIT_SHIFT_WMAC_MU_BFEE6_AID_8821C)
+#define BIT_CLEAR_WMAC_MU_BFEE6_AID_8821C(x) \
+ ((x) & (~BITS_WMAC_MU_BFEE6_AID_8821C))
+#define BIT_GET_WMAC_MU_BFEE6_AID_8821C(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID_8821C) & \
+ BIT_MASK_WMAC_MU_BFEE6_AID_8821C)
+#define BIT_SET_WMAC_MU_BFEE6_AID_8821C(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE6_AID_8821C(x) | BIT_WMAC_MU_BFEE6_AID_8821C(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7_8821C */
+#define BIT_STATUS_BFEE7_8821C BIT(10)
+#define BIT_WMAC_MU_BFEE7_EN_8821C BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE7_AID_8821C 0
+#define BIT_MASK_WMAC_MU_BFEE7_AID_8821C 0x1ff
+#define BIT_WMAC_MU_BFEE7_AID_8821C(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE7_AID_8821C) \
+ << BIT_SHIFT_WMAC_MU_BFEE7_AID_8821C)
+#define BITS_WMAC_MU_BFEE7_AID_8821C \
+ (BIT_MASK_WMAC_MU_BFEE7_AID_8821C << BIT_SHIFT_WMAC_MU_BFEE7_AID_8821C)
+#define BIT_CLEAR_WMAC_MU_BFEE7_AID_8821C(x) \
+ ((x) & (~BITS_WMAC_MU_BFEE7_AID_8821C))
+#define BIT_GET_WMAC_MU_BFEE7_AID_8821C(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID_8821C) & \
+ BIT_MASK_WMAC_MU_BFEE7_AID_8821C)
+#define BIT_SET_WMAC_MU_BFEE7_AID_8821C(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE7_AID_8821C(x) | BIT_WMAC_MU_BFEE7_AID_8821C(v))
+
+/* 2 REG_WMAC_BB_STOP_RX_COUNTER_8821C */
+#define BIT_RST_ALL_COUNTER_8821C BIT(31)
+
+#define BIT_SHIFT_ABORT_RX_VBON_COUNTER_8821C 16
+#define BIT_MASK_ABORT_RX_VBON_COUNTER_8821C 0xff
+#define BIT_ABORT_RX_VBON_COUNTER_8821C(x) \
+ (((x) & BIT_MASK_ABORT_RX_VBON_COUNTER_8821C) \
+ << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8821C)
+#define BITS_ABORT_RX_VBON_COUNTER_8821C \
+ (BIT_MASK_ABORT_RX_VBON_COUNTER_8821C \
+ << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8821C)
+#define BIT_CLEAR_ABORT_RX_VBON_COUNTER_8821C(x) \
+ ((x) & (~BITS_ABORT_RX_VBON_COUNTER_8821C))
+#define BIT_GET_ABORT_RX_VBON_COUNTER_8821C(x) \
+ (((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER_8821C) & \
+ BIT_MASK_ABORT_RX_VBON_COUNTER_8821C)
+#define BIT_SET_ABORT_RX_VBON_COUNTER_8821C(x, v) \
+ (BIT_CLEAR_ABORT_RX_VBON_COUNTER_8821C(x) | \
+ BIT_ABORT_RX_VBON_COUNTER_8821C(v))
+
+#define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8821C 8
+#define BIT_MASK_ABORT_RX_RDRDY_COUNTER_8821C 0xff
+#define BIT_ABORT_RX_RDRDY_COUNTER_8821C(x) \
+ (((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8821C) \
+ << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8821C)
+#define BITS_ABORT_RX_RDRDY_COUNTER_8821C \
+ (BIT_MASK_ABORT_RX_RDRDY_COUNTER_8821C \
+ << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8821C)
+#define BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8821C(x) \
+ ((x) & (~BITS_ABORT_RX_RDRDY_COUNTER_8821C))
+#define BIT_GET_ABORT_RX_RDRDY_COUNTER_8821C(x) \
+ (((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8821C) & \
+ BIT_MASK_ABORT_RX_RDRDY_COUNTER_8821C)
+#define BIT_SET_ABORT_RX_RDRDY_COUNTER_8821C(x, v) \
+ (BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8821C(x) | \
+ BIT_ABORT_RX_RDRDY_COUNTER_8821C(v))
+
+#define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8821C 0
+#define BIT_MASK_VBON_EARLY_FALLING_COUNTER_8821C 0xff
+#define BIT_VBON_EARLY_FALLING_COUNTER_8821C(x) \
+ (((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8821C) \
+ << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8821C)
+#define BITS_VBON_EARLY_FALLING_COUNTER_8821C \
+ (BIT_MASK_VBON_EARLY_FALLING_COUNTER_8821C \
+ << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8821C)
+#define BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8821C(x) \
+ ((x) & (~BITS_VBON_EARLY_FALLING_COUNTER_8821C))
+#define BIT_GET_VBON_EARLY_FALLING_COUNTER_8821C(x) \
+ (((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8821C) & \
+ BIT_MASK_VBON_EARLY_FALLING_COUNTER_8821C)
+#define BIT_SET_VBON_EARLY_FALLING_COUNTER_8821C(x, v) \
+ (BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8821C(x) | \
+ BIT_VBON_EARLY_FALLING_COUNTER_8821C(v))
+
+/* 2 REG_WMAC_PLCP_MONITOR_8821C */
+#define BIT_WMAC_PLCP_TRX_SEL_8821C BIT(31)
+
+#define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8821C 28
+#define BIT_MASK_WMAC_PLCP_RDSIG_SEL_8821C 0x7
+#define BIT_WMAC_PLCP_RDSIG_SEL_8821C(x) \
+ (((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8821C) \
+ << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8821C)
+#define BITS_WMAC_PLCP_RDSIG_SEL_8821C \
+ (BIT_MASK_WMAC_PLCP_RDSIG_SEL_8821C \
+ << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8821C)
+#define BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8821C(x) \
+ ((x) & (~BITS_WMAC_PLCP_RDSIG_SEL_8821C))
+#define BIT_GET_WMAC_PLCP_RDSIG_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8821C) & \
+ BIT_MASK_WMAC_PLCP_RDSIG_SEL_8821C)
+#define BIT_SET_WMAC_PLCP_RDSIG_SEL_8821C(x, v) \
+ (BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8821C(x) | \
+ BIT_WMAC_PLCP_RDSIG_SEL_8821C(v))
+
+#define BIT_SHIFT_WMAC_RATE_IDX_8821C 24
+#define BIT_MASK_WMAC_RATE_IDX_8821C 0xf
+#define BIT_WMAC_RATE_IDX_8821C(x) \
+ (((x) & BIT_MASK_WMAC_RATE_IDX_8821C) << BIT_SHIFT_WMAC_RATE_IDX_8821C)
+#define BITS_WMAC_RATE_IDX_8821C \
+ (BIT_MASK_WMAC_RATE_IDX_8821C << BIT_SHIFT_WMAC_RATE_IDX_8821C)
+#define BIT_CLEAR_WMAC_RATE_IDX_8821C(x) ((x) & (~BITS_WMAC_RATE_IDX_8821C))
+#define BIT_GET_WMAC_RATE_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_WMAC_RATE_IDX_8821C) & BIT_MASK_WMAC_RATE_IDX_8821C)
+#define BIT_SET_WMAC_RATE_IDX_8821C(x, v) \
+ (BIT_CLEAR_WMAC_RATE_IDX_8821C(x) | BIT_WMAC_RATE_IDX_8821C(v))
+
+#define BIT_SHIFT_WMAC_PLCP_RDSIG_8821C 0
+#define BIT_MASK_WMAC_PLCP_RDSIG_8821C 0xffffff
+#define BIT_WMAC_PLCP_RDSIG_8821C(x) \
+ (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8821C) \
+ << BIT_SHIFT_WMAC_PLCP_RDSIG_8821C)
+#define BITS_WMAC_PLCP_RDSIG_8821C \
+ (BIT_MASK_WMAC_PLCP_RDSIG_8821C << BIT_SHIFT_WMAC_PLCP_RDSIG_8821C)
+#define BIT_CLEAR_WMAC_PLCP_RDSIG_8821C(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8821C))
+#define BIT_GET_WMAC_PLCP_RDSIG_8821C(x) \
+ (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8821C) & \
+ BIT_MASK_WMAC_PLCP_RDSIG_8821C)
+#define BIT_SET_WMAC_PLCP_RDSIG_8821C(x, v) \
+ (BIT_CLEAR_WMAC_PLCP_RDSIG_8821C(x) | BIT_WMAC_PLCP_RDSIG_8821C(v))
+
+/* 2 REG_WMAC_PLCP_MONITOR_MUTX_8821C */
+#define BIT_WMAC_MUTX_IDX_8821C BIT(24)
+
+#define BIT_SHIFT_WMAC_PLCP_RDSIG_8821C 0
+#define BIT_MASK_WMAC_PLCP_RDSIG_8821C 0xffffff
+#define BIT_WMAC_PLCP_RDSIG_8821C(x) \
+ (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8821C) \
+ << BIT_SHIFT_WMAC_PLCP_RDSIG_8821C)
+#define BITS_WMAC_PLCP_RDSIG_8821C \
+ (BIT_MASK_WMAC_PLCP_RDSIG_8821C << BIT_SHIFT_WMAC_PLCP_RDSIG_8821C)
+#define BIT_CLEAR_WMAC_PLCP_RDSIG_8821C(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8821C))
+#define BIT_GET_WMAC_PLCP_RDSIG_8821C(x) \
+ (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8821C) & \
+ BIT_MASK_WMAC_PLCP_RDSIG_8821C)
+#define BIT_SET_WMAC_PLCP_RDSIG_8821C(x, v) \
+ (BIT_CLEAR_WMAC_PLCP_RDSIG_8821C(x) | BIT_WMAC_PLCP_RDSIG_8821C(v))
+
+/* 2 REG_RSVD_8821C */
-/* 2 REG_NOT_VALID_8821C */
+/* 2 REG_TRANSMIT_ADDRSS_0_8821C (TA0 REGISTER) */
-/* 2 REG_NOT_VALID_8821C */
+#define BIT_SHIFT_TA0_V1_8821C 0
+#define BIT_MASK_TA0_V1_8821C 0xffffffffL
+#define BIT_TA0_V1_8821C(x) \
+ (((x) & BIT_MASK_TA0_V1_8821C) << BIT_SHIFT_TA0_V1_8821C)
+#define BITS_TA0_V1_8821C (BIT_MASK_TA0_V1_8821C << BIT_SHIFT_TA0_V1_8821C)
+#define BIT_CLEAR_TA0_V1_8821C(x) ((x) & (~BITS_TA0_V1_8821C))
+#define BIT_GET_TA0_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_TA0_V1_8821C) & BIT_MASK_TA0_V1_8821C)
+#define BIT_SET_TA0_V1_8821C(x, v) \
+ (BIT_CLEAR_TA0_V1_8821C(x) | BIT_TA0_V1_8821C(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_0_H_8821C (TA0 REGISTER) */
+
+#define BIT_SHIFT_TA0_H_V1_8821C 0
+#define BIT_MASK_TA0_H_V1_8821C 0xffff
+#define BIT_TA0_H_V1_8821C(x) \
+ (((x) & BIT_MASK_TA0_H_V1_8821C) << BIT_SHIFT_TA0_H_V1_8821C)
+#define BITS_TA0_H_V1_8821C \
+ (BIT_MASK_TA0_H_V1_8821C << BIT_SHIFT_TA0_H_V1_8821C)
+#define BIT_CLEAR_TA0_H_V1_8821C(x) ((x) & (~BITS_TA0_H_V1_8821C))
+#define BIT_GET_TA0_H_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_TA0_H_V1_8821C) & BIT_MASK_TA0_H_V1_8821C)
+#define BIT_SET_TA0_H_V1_8821C(x, v) \
+ (BIT_CLEAR_TA0_H_V1_8821C(x) | BIT_TA0_H_V1_8821C(v))
-/* 2 REG_NOT_VALID_8821C */
+/* 2 REG_TRANSMIT_ADDRSS_1_8821C (TA1 REGISTER) */
-/* 2 REG_NOT_VALID_8821C */
+#define BIT_SHIFT_TA1_V1_8821C 0
+#define BIT_MASK_TA1_V1_8821C 0xffffffffL
+#define BIT_TA1_V1_8821C(x) \
+ (((x) & BIT_MASK_TA1_V1_8821C) << BIT_SHIFT_TA1_V1_8821C)
+#define BITS_TA1_V1_8821C (BIT_MASK_TA1_V1_8821C << BIT_SHIFT_TA1_V1_8821C)
+#define BIT_CLEAR_TA1_V1_8821C(x) ((x) & (~BITS_TA1_V1_8821C))
+#define BIT_GET_TA1_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_TA1_V1_8821C) & BIT_MASK_TA1_V1_8821C)
+#define BIT_SET_TA1_V1_8821C(x, v) \
+ (BIT_CLEAR_TA1_V1_8821C(x) | BIT_TA1_V1_8821C(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_1_H_8821C (TA1 REGISTER) */
+
+#define BIT_SHIFT_TA1_H_V1_8821C 0
+#define BIT_MASK_TA1_H_V1_8821C 0xffff
+#define BIT_TA1_H_V1_8821C(x) \
+ (((x) & BIT_MASK_TA1_H_V1_8821C) << BIT_SHIFT_TA1_H_V1_8821C)
+#define BITS_TA1_H_V1_8821C \
+ (BIT_MASK_TA1_H_V1_8821C << BIT_SHIFT_TA1_H_V1_8821C)
+#define BIT_CLEAR_TA1_H_V1_8821C(x) ((x) & (~BITS_TA1_H_V1_8821C))
+#define BIT_GET_TA1_H_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_TA1_H_V1_8821C) & BIT_MASK_TA1_H_V1_8821C)
+#define BIT_SET_TA1_H_V1_8821C(x, v) \
+ (BIT_CLEAR_TA1_H_V1_8821C(x) | BIT_TA1_H_V1_8821C(v))
-/* 2 REG_NOT_VALID_8821C */
+/* 2 REG_TRANSMIT_ADDRSS_2_8821C (TA2 REGISTER) */
-/* 2 REG_NOT_VALID_8821C */
+#define BIT_SHIFT_TA2_V1_8821C 0
+#define BIT_MASK_TA2_V1_8821C 0xffffffffL
+#define BIT_TA2_V1_8821C(x) \
+ (((x) & BIT_MASK_TA2_V1_8821C) << BIT_SHIFT_TA2_V1_8821C)
+#define BITS_TA2_V1_8821C (BIT_MASK_TA2_V1_8821C << BIT_SHIFT_TA2_V1_8821C)
+#define BIT_CLEAR_TA2_V1_8821C(x) ((x) & (~BITS_TA2_V1_8821C))
+#define BIT_GET_TA2_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_TA2_V1_8821C) & BIT_MASK_TA2_V1_8821C)
+#define BIT_SET_TA2_V1_8821C(x, v) \
+ (BIT_CLEAR_TA2_V1_8821C(x) | BIT_TA2_V1_8821C(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_2_H_8821C (TA2 REGISTER) */
+
+#define BIT_SHIFT_TA2_H_V1_8821C 0
+#define BIT_MASK_TA2_H_V1_8821C 0xffff
+#define BIT_TA2_H_V1_8821C(x) \
+ (((x) & BIT_MASK_TA2_H_V1_8821C) << BIT_SHIFT_TA2_H_V1_8821C)
+#define BITS_TA2_H_V1_8821C \
+ (BIT_MASK_TA2_H_V1_8821C << BIT_SHIFT_TA2_H_V1_8821C)
+#define BIT_CLEAR_TA2_H_V1_8821C(x) ((x) & (~BITS_TA2_H_V1_8821C))
+#define BIT_GET_TA2_H_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_TA2_H_V1_8821C) & BIT_MASK_TA2_H_V1_8821C)
+#define BIT_SET_TA2_H_V1_8821C(x, v) \
+ (BIT_CLEAR_TA2_H_V1_8821C(x) | BIT_TA2_H_V1_8821C(v))
-/* 2 REG_NOT_VALID_8821C */
+/* 2 REG_TRANSMIT_ADDRSS_3_8821C (TA3 REGISTER) */
-/* 2 REG_NOT_VALID_8821C */
+#define BIT_SHIFT_TA2_V1_8821C 0
+#define BIT_MASK_TA2_V1_8821C 0xffffffffL
+#define BIT_TA2_V1_8821C(x) \
+ (((x) & BIT_MASK_TA2_V1_8821C) << BIT_SHIFT_TA2_V1_8821C)
+#define BITS_TA2_V1_8821C (BIT_MASK_TA2_V1_8821C << BIT_SHIFT_TA2_V1_8821C)
+#define BIT_CLEAR_TA2_V1_8821C(x) ((x) & (~BITS_TA2_V1_8821C))
+#define BIT_GET_TA2_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_TA2_V1_8821C) & BIT_MASK_TA2_V1_8821C)
+#define BIT_SET_TA2_V1_8821C(x, v) \
+ (BIT_CLEAR_TA2_V1_8821C(x) | BIT_TA2_V1_8821C(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_3_H_8821C (TA3 REGISTER) */
+
+#define BIT_SHIFT_TA3_H_V1_8821C 0
+#define BIT_MASK_TA3_H_V1_8821C 0xffff
+#define BIT_TA3_H_V1_8821C(x) \
+ (((x) & BIT_MASK_TA3_H_V1_8821C) << BIT_SHIFT_TA3_H_V1_8821C)
+#define BITS_TA3_H_V1_8821C \
+ (BIT_MASK_TA3_H_V1_8821C << BIT_SHIFT_TA3_H_V1_8821C)
+#define BIT_CLEAR_TA3_H_V1_8821C(x) ((x) & (~BITS_TA3_H_V1_8821C))
+#define BIT_GET_TA3_H_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_TA3_H_V1_8821C) & BIT_MASK_TA3_H_V1_8821C)
+#define BIT_SET_TA3_H_V1_8821C(x, v) \
+ (BIT_CLEAR_TA3_H_V1_8821C(x) | BIT_TA3_H_V1_8821C(v))
-/* 2 REG_NOT_VALID_8821C */
+/* 2 REG_TRANSMIT_ADDRSS_4_8821C (TA4 REGISTER) */
-/* 2 REG_NOT_VALID_8821C */
+#define BIT_SHIFT_TA4_V1_8821C 0
+#define BIT_MASK_TA4_V1_8821C 0xffffffffL
+#define BIT_TA4_V1_8821C(x) \
+ (((x) & BIT_MASK_TA4_V1_8821C) << BIT_SHIFT_TA4_V1_8821C)
+#define BITS_TA4_V1_8821C (BIT_MASK_TA4_V1_8821C << BIT_SHIFT_TA4_V1_8821C)
+#define BIT_CLEAR_TA4_V1_8821C(x) ((x) & (~BITS_TA4_V1_8821C))
+#define BIT_GET_TA4_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_TA4_V1_8821C) & BIT_MASK_TA4_V1_8821C)
+#define BIT_SET_TA4_V1_8821C(x, v) \
+ (BIT_CLEAR_TA4_V1_8821C(x) | BIT_TA4_V1_8821C(v))
-/* 2 REG_NOT_VALID_8821C */
+/* 2 REG_TRANSMIT_ADDRSS_4_H_8821C (TA4 REGISTER) */
-/* 2 REG_TRANSMIT_ADDRSS_0_8821C (TA0 REGISTER) */
+#define BIT_SHIFT_TA4_H_V1_8821C 0
+#define BIT_MASK_TA4_H_V1_8821C 0xffff
+#define BIT_TA4_H_V1_8821C(x) \
+ (((x) & BIT_MASK_TA4_H_V1_8821C) << BIT_SHIFT_TA4_H_V1_8821C)
+#define BITS_TA4_H_V1_8821C \
+ (BIT_MASK_TA4_H_V1_8821C << BIT_SHIFT_TA4_H_V1_8821C)
+#define BIT_CLEAR_TA4_H_V1_8821C(x) ((x) & (~BITS_TA4_H_V1_8821C))
+#define BIT_GET_TA4_H_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_TA4_H_V1_8821C) & BIT_MASK_TA4_H_V1_8821C)
+#define BIT_SET_TA4_H_V1_8821C(x, v) \
+ (BIT_CLEAR_TA4_H_V1_8821C(x) | BIT_TA4_H_V1_8821C(v))
-#define BIT_SHIFT_TA0_8821C 0
-#define BIT_MASK_TA0_8821C 0xffffffffffffL
-#define BIT_TA0_8821C(x) (((x) & BIT_MASK_TA0_8821C) << BIT_SHIFT_TA0_8821C)
-#define BIT_GET_TA0_8821C(x) (((x) >> BIT_SHIFT_TA0_8821C) & BIT_MASK_TA0_8821C)
+/* 2 REG_RSVD_8821C */
+/* 2 REG_RSVD_8821C */
-/* 2 REG_TRANSMIT_ADDRSS_1_8821C (TA1 REGISTER) */
+/* 2 REG_RSVD_8821C */
-#define BIT_SHIFT_TA1_8821C 0
-#define BIT_MASK_TA1_8821C 0xffffffffffffL
-#define BIT_TA1_8821C(x) (((x) & BIT_MASK_TA1_8821C) << BIT_SHIFT_TA1_8821C)
-#define BIT_GET_TA1_8821C(x) (((x) >> BIT_SHIFT_TA1_8821C) & BIT_MASK_TA1_8821C)
+/* 2 REG_RSVD_8821C */
+/* 2 REG_RSVD_8821C */
-/* 2 REG_TRANSMIT_ADDRSS_2_8821C (TA2 REGISTER) */
+/* 2 REG_RSVD_8821C */
-#define BIT_SHIFT_TA2_8821C 0
-#define BIT_MASK_TA2_8821C 0xffffffffffffL
-#define BIT_TA2_8821C(x) (((x) & BIT_MASK_TA2_8821C) << BIT_SHIFT_TA2_8821C)
-#define BIT_GET_TA2_8821C(x) (((x) >> BIT_SHIFT_TA2_8821C) & BIT_MASK_TA2_8821C)
+/* 2 REG_RSVD_8821C */
+/* 2 REG_RSVD_8821C */
-/* 2 REG_TRANSMIT_ADDRSS_3_8821C (TA3 REGISTER) */
+/* 2 REG_RSVD_8821C */
-#define BIT_SHIFT_TA3_8821C 0
-#define BIT_MASK_TA3_8821C 0xffffffffffffL
-#define BIT_TA3_8821C(x) (((x) & BIT_MASK_TA3_8821C) << BIT_SHIFT_TA3_8821C)
-#define BIT_GET_TA3_8821C(x) (((x) >> BIT_SHIFT_TA3_8821C) & BIT_MASK_TA3_8821C)
+/* 2 REG_RSVD_8821C */
+/* 2 REG_RSVD_8821C */
-/* 2 REG_TRANSMIT_ADDRSS_4_8821C (TA4 REGISTER) */
+/* 2 REG_RSVD_8821C */
-#define BIT_SHIFT_TA4_8821C 0
-#define BIT_MASK_TA4_8821C 0xffffffffffffL
-#define BIT_TA4_8821C(x) (((x) & BIT_MASK_TA4_8821C) << BIT_SHIFT_TA4_8821C)
-#define BIT_GET_TA4_8821C(x) (((x) >> BIT_SHIFT_TA4_8821C) & BIT_MASK_TA4_8821C)
+/* 2 REG_RSVD_8821C */
+/* 2 REG_RSVD_8821C */
/* 2 REG_NOT_VALID_8821C */
/* 2 REG_MACID1_8821C */
-#define BIT_SHIFT_MACID1_8821C 0
-#define BIT_MASK_MACID1_8821C 0xffffffffffffL
-#define BIT_MACID1_8821C(x) (((x) & BIT_MASK_MACID1_8821C) << BIT_SHIFT_MACID1_8821C)
-#define BIT_GET_MACID1_8821C(x) (((x) >> BIT_SHIFT_MACID1_8821C) & BIT_MASK_MACID1_8821C)
-
+#define BIT_SHIFT_MACID1_0_8821C 0
+#define BIT_MASK_MACID1_0_8821C 0xffffffffL
+#define BIT_MACID1_0_8821C(x) \
+ (((x) & BIT_MASK_MACID1_0_8821C) << BIT_SHIFT_MACID1_0_8821C)
+#define BITS_MACID1_0_8821C \
+ (BIT_MASK_MACID1_0_8821C << BIT_SHIFT_MACID1_0_8821C)
+#define BIT_CLEAR_MACID1_0_8821C(x) ((x) & (~BITS_MACID1_0_8821C))
+#define BIT_GET_MACID1_0_8821C(x) \
+ (((x) >> BIT_SHIFT_MACID1_0_8821C) & BIT_MASK_MACID1_0_8821C)
+#define BIT_SET_MACID1_0_8821C(x, v) \
+ (BIT_CLEAR_MACID1_0_8821C(x) | BIT_MACID1_0_8821C(v))
+
+/* 2 REG_MACID1_1_8821C */
+
+#define BIT_SHIFT_MACID1_1_8821C 0
+#define BIT_MASK_MACID1_1_8821C 0xffff
+#define BIT_MACID1_1_8821C(x) \
+ (((x) & BIT_MASK_MACID1_1_8821C) << BIT_SHIFT_MACID1_1_8821C)
+#define BITS_MACID1_1_8821C \
+ (BIT_MASK_MACID1_1_8821C << BIT_SHIFT_MACID1_1_8821C)
+#define BIT_CLEAR_MACID1_1_8821C(x) ((x) & (~BITS_MACID1_1_8821C))
+#define BIT_GET_MACID1_1_8821C(x) \
+ (((x) >> BIT_SHIFT_MACID1_1_8821C) & BIT_MASK_MACID1_1_8821C)
+#define BIT_SET_MACID1_1_8821C(x, v) \
+ (BIT_CLEAR_MACID1_1_8821C(x) | BIT_MACID1_1_8821C(v))
/* 2 REG_BSSID1_8821C */
-#define BIT_SHIFT_BSSID1_8821C 0
-#define BIT_MASK_BSSID1_8821C 0xffffffffffffL
-#define BIT_BSSID1_8821C(x) (((x) & BIT_MASK_BSSID1_8821C) << BIT_SHIFT_BSSID1_8821C)
-#define BIT_GET_BSSID1_8821C(x) (((x) >> BIT_SHIFT_BSSID1_8821C) & BIT_MASK_BSSID1_8821C)
-
+#define BIT_SHIFT_BSSID1_0_8821C 0
+#define BIT_MASK_BSSID1_0_8821C 0xffffffffL
+#define BIT_BSSID1_0_8821C(x) \
+ (((x) & BIT_MASK_BSSID1_0_8821C) << BIT_SHIFT_BSSID1_0_8821C)
+#define BITS_BSSID1_0_8821C \
+ (BIT_MASK_BSSID1_0_8821C << BIT_SHIFT_BSSID1_0_8821C)
+#define BIT_CLEAR_BSSID1_0_8821C(x) ((x) & (~BITS_BSSID1_0_8821C))
+#define BIT_GET_BSSID1_0_8821C(x) \
+ (((x) >> BIT_SHIFT_BSSID1_0_8821C) & BIT_MASK_BSSID1_0_8821C)
+#define BIT_SET_BSSID1_0_8821C(x, v) \
+ (BIT_CLEAR_BSSID1_0_8821C(x) | BIT_BSSID1_0_8821C(v))
+
+/* 2 REG_BSSID1_1_8821C */
+
+#define BIT_SHIFT_BSSID1_1_8821C 0
+#define BIT_MASK_BSSID1_1_8821C 0xffff
+#define BIT_BSSID1_1_8821C(x) \
+ (((x) & BIT_MASK_BSSID1_1_8821C) << BIT_SHIFT_BSSID1_1_8821C)
+#define BITS_BSSID1_1_8821C \
+ (BIT_MASK_BSSID1_1_8821C << BIT_SHIFT_BSSID1_1_8821C)
+#define BIT_CLEAR_BSSID1_1_8821C(x) ((x) & (~BITS_BSSID1_1_8821C))
+#define BIT_GET_BSSID1_1_8821C(x) \
+ (((x) >> BIT_SHIFT_BSSID1_1_8821C) & BIT_MASK_BSSID1_1_8821C)
+#define BIT_SET_BSSID1_1_8821C(x, v) \
+ (BIT_CLEAR_BSSID1_1_8821C(x) | BIT_BSSID1_1_8821C(v))
/* 2 REG_BCN_PSR_RPT1_8821C */
#define BIT_SHIFT_DTIM_CNT1_8821C 24
#define BIT_MASK_DTIM_CNT1_8821C 0xff
-#define BIT_DTIM_CNT1_8821C(x) (((x) & BIT_MASK_DTIM_CNT1_8821C) << BIT_SHIFT_DTIM_CNT1_8821C)
-#define BIT_GET_DTIM_CNT1_8821C(x) (((x) >> BIT_SHIFT_DTIM_CNT1_8821C) & BIT_MASK_DTIM_CNT1_8821C)
-
+#define BIT_DTIM_CNT1_8821C(x) \
+ (((x) & BIT_MASK_DTIM_CNT1_8821C) << BIT_SHIFT_DTIM_CNT1_8821C)
+#define BITS_DTIM_CNT1_8821C \
+ (BIT_MASK_DTIM_CNT1_8821C << BIT_SHIFT_DTIM_CNT1_8821C)
+#define BIT_CLEAR_DTIM_CNT1_8821C(x) ((x) & (~BITS_DTIM_CNT1_8821C))
+#define BIT_GET_DTIM_CNT1_8821C(x) \
+ (((x) >> BIT_SHIFT_DTIM_CNT1_8821C) & BIT_MASK_DTIM_CNT1_8821C)
+#define BIT_SET_DTIM_CNT1_8821C(x, v) \
+ (BIT_CLEAR_DTIM_CNT1_8821C(x) | BIT_DTIM_CNT1_8821C(v))
#define BIT_SHIFT_DTIM_PERIOD1_8821C 16
#define BIT_MASK_DTIM_PERIOD1_8821C 0xff
-#define BIT_DTIM_PERIOD1_8821C(x) (((x) & BIT_MASK_DTIM_PERIOD1_8821C) << BIT_SHIFT_DTIM_PERIOD1_8821C)
-#define BIT_GET_DTIM_PERIOD1_8821C(x) (((x) >> BIT_SHIFT_DTIM_PERIOD1_8821C) & BIT_MASK_DTIM_PERIOD1_8821C)
+#define BIT_DTIM_PERIOD1_8821C(x) \
+ (((x) & BIT_MASK_DTIM_PERIOD1_8821C) << BIT_SHIFT_DTIM_PERIOD1_8821C)
+#define BITS_DTIM_PERIOD1_8821C \
+ (BIT_MASK_DTIM_PERIOD1_8821C << BIT_SHIFT_DTIM_PERIOD1_8821C)
+#define BIT_CLEAR_DTIM_PERIOD1_8821C(x) ((x) & (~BITS_DTIM_PERIOD1_8821C))
+#define BIT_GET_DTIM_PERIOD1_8821C(x) \
+ (((x) >> BIT_SHIFT_DTIM_PERIOD1_8821C) & BIT_MASK_DTIM_PERIOD1_8821C)
+#define BIT_SET_DTIM_PERIOD1_8821C(x, v) \
+ (BIT_CLEAR_DTIM_PERIOD1_8821C(x) | BIT_DTIM_PERIOD1_8821C(v))
#define BIT_DTIM1_8821C BIT(15)
#define BIT_TIM1_8821C BIT(14)
#define BIT_SHIFT_PS_AID_1_8821C 0
#define BIT_MASK_PS_AID_1_8821C 0x7ff
-#define BIT_PS_AID_1_8821C(x) (((x) & BIT_MASK_PS_AID_1_8821C) << BIT_SHIFT_PS_AID_1_8821C)
-#define BIT_GET_PS_AID_1_8821C(x) (((x) >> BIT_SHIFT_PS_AID_1_8821C) & BIT_MASK_PS_AID_1_8821C)
-
+#define BIT_PS_AID_1_8821C(x) \
+ (((x) & BIT_MASK_PS_AID_1_8821C) << BIT_SHIFT_PS_AID_1_8821C)
+#define BITS_PS_AID_1_8821C \
+ (BIT_MASK_PS_AID_1_8821C << BIT_SHIFT_PS_AID_1_8821C)
+#define BIT_CLEAR_PS_AID_1_8821C(x) ((x) & (~BITS_PS_AID_1_8821C))
+#define BIT_GET_PS_AID_1_8821C(x) \
+ (((x) >> BIT_SHIFT_PS_AID_1_8821C) & BIT_MASK_PS_AID_1_8821C)
+#define BIT_SET_PS_AID_1_8821C(x, v) \
+ (BIT_CLEAR_PS_AID_1_8821C(x) | BIT_PS_AID_1_8821C(v))
/* 2 REG_ASSOCIATED_BFMEE_SEL_8821C */
#define BIT_TXUSER_ID1_8821C BIT(25)
@@ -8933,34 +17281,73 @@
#define BIT_SHIFT_AID1_8821C 16
#define BIT_MASK_AID1_8821C 0x1ff
#define BIT_AID1_8821C(x) (((x) & BIT_MASK_AID1_8821C) << BIT_SHIFT_AID1_8821C)
-#define BIT_GET_AID1_8821C(x) (((x) >> BIT_SHIFT_AID1_8821C) & BIT_MASK_AID1_8821C)
+#define BITS_AID1_8821C (BIT_MASK_AID1_8821C << BIT_SHIFT_AID1_8821C)
+#define BIT_CLEAR_AID1_8821C(x) ((x) & (~BITS_AID1_8821C))
+#define BIT_GET_AID1_8821C(x) \
+ (((x) >> BIT_SHIFT_AID1_8821C) & BIT_MASK_AID1_8821C)
+#define BIT_SET_AID1_8821C(x, v) (BIT_CLEAR_AID1_8821C(x) | BIT_AID1_8821C(v))
#define BIT_TXUSER_ID0_8821C BIT(9)
#define BIT_SHIFT_AID0_8821C 0
#define BIT_MASK_AID0_8821C 0x1ff
#define BIT_AID0_8821C(x) (((x) & BIT_MASK_AID0_8821C) << BIT_SHIFT_AID0_8821C)
-#define BIT_GET_AID0_8821C(x) (((x) >> BIT_SHIFT_AID0_8821C) & BIT_MASK_AID0_8821C)
-
+#define BITS_AID0_8821C (BIT_MASK_AID0_8821C << BIT_SHIFT_AID0_8821C)
+#define BIT_CLEAR_AID0_8821C(x) ((x) & (~BITS_AID0_8821C))
+#define BIT_GET_AID0_8821C(x) \
+ (((x) >> BIT_SHIFT_AID0_8821C) & BIT_MASK_AID0_8821C)
+#define BIT_SET_AID0_8821C(x, v) (BIT_CLEAR_AID0_8821C(x) | BIT_AID0_8821C(v))
/* 2 REG_SND_PTCL_CTRL_8821C */
#define BIT_SHIFT_NDP_RX_STANDBY_TIMER_8821C 24
#define BIT_MASK_NDP_RX_STANDBY_TIMER_8821C 0xff
-#define BIT_NDP_RX_STANDBY_TIMER_8821C(x) (((x) & BIT_MASK_NDP_RX_STANDBY_TIMER_8821C) << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8821C)
-#define BIT_GET_NDP_RX_STANDBY_TIMER_8821C(x) (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8821C) & BIT_MASK_NDP_RX_STANDBY_TIMER_8821C)
-
+#define BIT_NDP_RX_STANDBY_TIMER_8821C(x) \
+ (((x) & BIT_MASK_NDP_RX_STANDBY_TIMER_8821C) \
+ << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8821C)
+#define BITS_NDP_RX_STANDBY_TIMER_8821C \
+ (BIT_MASK_NDP_RX_STANDBY_TIMER_8821C \
+ << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8821C)
+#define BIT_CLEAR_NDP_RX_STANDBY_TIMER_8821C(x) \
+ ((x) & (~BITS_NDP_RX_STANDBY_TIMER_8821C))
+#define BIT_GET_NDP_RX_STANDBY_TIMER_8821C(x) \
+ (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8821C) & \
+ BIT_MASK_NDP_RX_STANDBY_TIMER_8821C)
+#define BIT_SET_NDP_RX_STANDBY_TIMER_8821C(x, v) \
+ (BIT_CLEAR_NDP_RX_STANDBY_TIMER_8821C(x) | \
+ BIT_NDP_RX_STANDBY_TIMER_8821C(v))
#define BIT_SHIFT_CSI_RPT_OFFSET_HT_8821C 16
#define BIT_MASK_CSI_RPT_OFFSET_HT_8821C 0xff
-#define BIT_CSI_RPT_OFFSET_HT_8821C(x) (((x) & BIT_MASK_CSI_RPT_OFFSET_HT_8821C) << BIT_SHIFT_CSI_RPT_OFFSET_HT_8821C)
-#define BIT_GET_CSI_RPT_OFFSET_HT_8821C(x) (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_8821C) & BIT_MASK_CSI_RPT_OFFSET_HT_8821C)
-
+#define BIT_CSI_RPT_OFFSET_HT_8821C(x) \
+ (((x) & BIT_MASK_CSI_RPT_OFFSET_HT_8821C) \
+ << BIT_SHIFT_CSI_RPT_OFFSET_HT_8821C)
+#define BITS_CSI_RPT_OFFSET_HT_8821C \
+ (BIT_MASK_CSI_RPT_OFFSET_HT_8821C << BIT_SHIFT_CSI_RPT_OFFSET_HT_8821C)
+#define BIT_CLEAR_CSI_RPT_OFFSET_HT_8821C(x) \
+ ((x) & (~BITS_CSI_RPT_OFFSET_HT_8821C))
+#define BIT_GET_CSI_RPT_OFFSET_HT_8821C(x) \
+ (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_8821C) & \
+ BIT_MASK_CSI_RPT_OFFSET_HT_8821C)
+#define BIT_SET_CSI_RPT_OFFSET_HT_8821C(x, v) \
+ (BIT_CLEAR_CSI_RPT_OFFSET_HT_8821C(x) | BIT_CSI_RPT_OFFSET_HT_8821C(v))
#define BIT_SHIFT_R_WMAC_VHT_CATEGORY_8821C 8
#define BIT_MASK_R_WMAC_VHT_CATEGORY_8821C 0xff
-#define BIT_R_WMAC_VHT_CATEGORY_8821C(x) (((x) & BIT_MASK_R_WMAC_VHT_CATEGORY_8821C) << BIT_SHIFT_R_WMAC_VHT_CATEGORY_8821C)
-#define BIT_GET_R_WMAC_VHT_CATEGORY_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY_8821C) & BIT_MASK_R_WMAC_VHT_CATEGORY_8821C)
+#define BIT_R_WMAC_VHT_CATEGORY_8821C(x) \
+ (((x) & BIT_MASK_R_WMAC_VHT_CATEGORY_8821C) \
+ << BIT_SHIFT_R_WMAC_VHT_CATEGORY_8821C)
+#define BITS_R_WMAC_VHT_CATEGORY_8821C \
+ (BIT_MASK_R_WMAC_VHT_CATEGORY_8821C \
+ << BIT_SHIFT_R_WMAC_VHT_CATEGORY_8821C)
+#define BIT_CLEAR_R_WMAC_VHT_CATEGORY_8821C(x) \
+ ((x) & (~BITS_R_WMAC_VHT_CATEGORY_8821C))
+#define BIT_GET_R_WMAC_VHT_CATEGORY_8821C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY_8821C) & \
+ BIT_MASK_R_WMAC_VHT_CATEGORY_8821C)
+#define BIT_SET_R_WMAC_VHT_CATEGORY_8821C(x, v) \
+ (BIT_CLEAR_R_WMAC_VHT_CATEGORY_8821C(x) | \
+ BIT_R_WMAC_VHT_CATEGORY_8821C(v))
#define BIT_R_WMAC_USE_NSTS_8821C BIT(7)
#define BIT_R_DISABLE_CHECK_VHTSIGB_CRC_8821C BIT(6)
@@ -8980,21 +17367,54 @@
#define BIT_SHIFT_R_WMAC_NSARP_MODEN_8821C 6
#define BIT_MASK_R_WMAC_NSARP_MODEN_8821C 0x3
-#define BIT_R_WMAC_NSARP_MODEN_8821C(x) (((x) & BIT_MASK_R_WMAC_NSARP_MODEN_8821C) << BIT_SHIFT_R_WMAC_NSARP_MODEN_8821C)
-#define BIT_GET_R_WMAC_NSARP_MODEN_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8821C) & BIT_MASK_R_WMAC_NSARP_MODEN_8821C)
-
+#define BIT_R_WMAC_NSARP_MODEN_8821C(x) \
+ (((x) & BIT_MASK_R_WMAC_NSARP_MODEN_8821C) \
+ << BIT_SHIFT_R_WMAC_NSARP_MODEN_8821C)
+#define BITS_R_WMAC_NSARP_MODEN_8821C \
+ (BIT_MASK_R_WMAC_NSARP_MODEN_8821C \
+ << BIT_SHIFT_R_WMAC_NSARP_MODEN_8821C)
+#define BIT_CLEAR_R_WMAC_NSARP_MODEN_8821C(x) \
+ ((x) & (~BITS_R_WMAC_NSARP_MODEN_8821C))
+#define BIT_GET_R_WMAC_NSARP_MODEN_8821C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8821C) & \
+ BIT_MASK_R_WMAC_NSARP_MODEN_8821C)
+#define BIT_SET_R_WMAC_NSARP_MODEN_8821C(x, v) \
+ (BIT_CLEAR_R_WMAC_NSARP_MODEN_8821C(x) | \
+ BIT_R_WMAC_NSARP_MODEN_8821C(v))
#define BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8821C 4
#define BIT_MASK_R_WMAC_NSARP_RSPFTP_8821C 0x3
-#define BIT_R_WMAC_NSARP_RSPFTP_8821C(x) (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8821C) << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8821C)
-#define BIT_GET_R_WMAC_NSARP_RSPFTP_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8821C) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8821C)
-
+#define BIT_R_WMAC_NSARP_RSPFTP_8821C(x) \
+ (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8821C) \
+ << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8821C)
+#define BITS_R_WMAC_NSARP_RSPFTP_8821C \
+ (BIT_MASK_R_WMAC_NSARP_RSPFTP_8821C \
+ << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8821C)
+#define BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8821C(x) \
+ ((x) & (~BITS_R_WMAC_NSARP_RSPFTP_8821C))
+#define BIT_GET_R_WMAC_NSARP_RSPFTP_8821C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8821C) & \
+ BIT_MASK_R_WMAC_NSARP_RSPFTP_8821C)
+#define BIT_SET_R_WMAC_NSARP_RSPFTP_8821C(x, v) \
+ (BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8821C(x) | \
+ BIT_R_WMAC_NSARP_RSPFTP_8821C(v))
#define BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8821C 0
#define BIT_MASK_R_WMAC_NSARP_RSPSEC_8821C 0xf
-#define BIT_R_WMAC_NSARP_RSPSEC_8821C(x) (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8821C) << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8821C)
-#define BIT_GET_R_WMAC_NSARP_RSPSEC_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8821C) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8821C)
-
+#define BIT_R_WMAC_NSARP_RSPSEC_8821C(x) \
+ (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8821C) \
+ << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8821C)
+#define BITS_R_WMAC_NSARP_RSPSEC_8821C \
+ (BIT_MASK_R_WMAC_NSARP_RSPSEC_8821C \
+ << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8821C)
+#define BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8821C(x) \
+ ((x) & (~BITS_R_WMAC_NSARP_RSPSEC_8821C))
+#define BIT_GET_R_WMAC_NSARP_RSPSEC_8821C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8821C) & \
+ BIT_MASK_R_WMAC_NSARP_RSPSEC_8821C)
+#define BIT_SET_R_WMAC_NSARP_RSPSEC_8821C(x, v) \
+ (BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8821C(x) | \
+ BIT_R_WMAC_NSARP_RSPSEC_8821C(v))
/* 2 REG_NS_ARP_INFO_8821C */
#define BIT_REQ_IS_MCNS_8821C BIT(23)
@@ -9005,61 +17425,208 @@
#define BIT_SHIFT_EXPRSP_SECTYPE_8821C 16
#define BIT_MASK_EXPRSP_SECTYPE_8821C 0x7
-#define BIT_EXPRSP_SECTYPE_8821C(x) (((x) & BIT_MASK_EXPRSP_SECTYPE_8821C) << BIT_SHIFT_EXPRSP_SECTYPE_8821C)
-#define BIT_GET_EXPRSP_SECTYPE_8821C(x) (((x) >> BIT_SHIFT_EXPRSP_SECTYPE_8821C) & BIT_MASK_EXPRSP_SECTYPE_8821C)
-
+#define BIT_EXPRSP_SECTYPE_8821C(x) \
+ (((x) & BIT_MASK_EXPRSP_SECTYPE_8821C) \
+ << BIT_SHIFT_EXPRSP_SECTYPE_8821C)
+#define BITS_EXPRSP_SECTYPE_8821C \
+ (BIT_MASK_EXPRSP_SECTYPE_8821C << BIT_SHIFT_EXPRSP_SECTYPE_8821C)
+#define BIT_CLEAR_EXPRSP_SECTYPE_8821C(x) ((x) & (~BITS_EXPRSP_SECTYPE_8821C))
+#define BIT_GET_EXPRSP_SECTYPE_8821C(x) \
+ (((x) >> BIT_SHIFT_EXPRSP_SECTYPE_8821C) & \
+ BIT_MASK_EXPRSP_SECTYPE_8821C)
+#define BIT_SET_EXPRSP_SECTYPE_8821C(x, v) \
+ (BIT_CLEAR_EXPRSP_SECTYPE_8821C(x) | BIT_EXPRSP_SECTYPE_8821C(v))
#define BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8821C 8
#define BIT_MASK_EXPRSP_CHKSM_7_TO_0_8821C 0xff
-#define BIT_EXPRSP_CHKSM_7_TO_0_8821C(x) (((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8821C) << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8821C)
-#define BIT_GET_EXPRSP_CHKSM_7_TO_0_8821C(x) (((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8821C) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8821C)
-
+#define BIT_EXPRSP_CHKSM_7_TO_0_8821C(x) \
+ (((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8821C) \
+ << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8821C)
+#define BITS_EXPRSP_CHKSM_7_TO_0_8821C \
+ (BIT_MASK_EXPRSP_CHKSM_7_TO_0_8821C \
+ << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8821C)
+#define BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8821C(x) \
+ ((x) & (~BITS_EXPRSP_CHKSM_7_TO_0_8821C))
+#define BIT_GET_EXPRSP_CHKSM_7_TO_0_8821C(x) \
+ (((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8821C) & \
+ BIT_MASK_EXPRSP_CHKSM_7_TO_0_8821C)
+#define BIT_SET_EXPRSP_CHKSM_7_TO_0_8821C(x, v) \
+ (BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8821C(x) | \
+ BIT_EXPRSP_CHKSM_7_TO_0_8821C(v))
#define BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8821C 0
#define BIT_MASK_EXPRSP_CHKSM_15_TO_8_8821C 0xff
-#define BIT_EXPRSP_CHKSM_15_TO_8_8821C(x) (((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8821C) << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8821C)
-#define BIT_GET_EXPRSP_CHKSM_15_TO_8_8821C(x) (((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8821C) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8821C)
-
+#define BIT_EXPRSP_CHKSM_15_TO_8_8821C(x) \
+ (((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8821C) \
+ << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8821C)
+#define BITS_EXPRSP_CHKSM_15_TO_8_8821C \
+ (BIT_MASK_EXPRSP_CHKSM_15_TO_8_8821C \
+ << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8821C)
+#define BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8821C(x) \
+ ((x) & (~BITS_EXPRSP_CHKSM_15_TO_8_8821C))
+#define BIT_GET_EXPRSP_CHKSM_15_TO_8_8821C(x) \
+ (((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8821C) & \
+ BIT_MASK_EXPRSP_CHKSM_15_TO_8_8821C)
+#define BIT_SET_EXPRSP_CHKSM_15_TO_8_8821C(x, v) \
+ (BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8821C(x) | \
+ BIT_EXPRSP_CHKSM_15_TO_8_8821C(v))
/* 2 REG_BEAMFORMING_INFO_NSARP_V1_8821C */
#define BIT_SHIFT_WMAC_ARPIP_8821C 0
#define BIT_MASK_WMAC_ARPIP_8821C 0xffffffffL
-#define BIT_WMAC_ARPIP_8821C(x) (((x) & BIT_MASK_WMAC_ARPIP_8821C) << BIT_SHIFT_WMAC_ARPIP_8821C)
-#define BIT_GET_WMAC_ARPIP_8821C(x) (((x) >> BIT_SHIFT_WMAC_ARPIP_8821C) & BIT_MASK_WMAC_ARPIP_8821C)
-
+#define BIT_WMAC_ARPIP_8821C(x) \
+ (((x) & BIT_MASK_WMAC_ARPIP_8821C) << BIT_SHIFT_WMAC_ARPIP_8821C)
+#define BITS_WMAC_ARPIP_8821C \
+ (BIT_MASK_WMAC_ARPIP_8821C << BIT_SHIFT_WMAC_ARPIP_8821C)
+#define BIT_CLEAR_WMAC_ARPIP_8821C(x) ((x) & (~BITS_WMAC_ARPIP_8821C))
+#define BIT_GET_WMAC_ARPIP_8821C(x) \
+ (((x) >> BIT_SHIFT_WMAC_ARPIP_8821C) & BIT_MASK_WMAC_ARPIP_8821C)
+#define BIT_SET_WMAC_ARPIP_8821C(x, v) \
+ (BIT_CLEAR_WMAC_ARPIP_8821C(x) | BIT_WMAC_ARPIP_8821C(v))
/* 2 REG_BEAMFORMING_INFO_NSARP_8821C */
#define BIT_SHIFT_BEAMFORMING_INFO_8821C 0
#define BIT_MASK_BEAMFORMING_INFO_8821C 0xffffffffL
-#define BIT_BEAMFORMING_INFO_8821C(x) (((x) & BIT_MASK_BEAMFORMING_INFO_8821C) << BIT_SHIFT_BEAMFORMING_INFO_8821C)
-#define BIT_GET_BEAMFORMING_INFO_8821C(x) (((x) >> BIT_SHIFT_BEAMFORMING_INFO_8821C) & BIT_MASK_BEAMFORMING_INFO_8821C)
-
+#define BIT_BEAMFORMING_INFO_8821C(x) \
+ (((x) & BIT_MASK_BEAMFORMING_INFO_8821C) \
+ << BIT_SHIFT_BEAMFORMING_INFO_8821C)
+#define BITS_BEAMFORMING_INFO_8821C \
+ (BIT_MASK_BEAMFORMING_INFO_8821C << BIT_SHIFT_BEAMFORMING_INFO_8821C)
+#define BIT_CLEAR_BEAMFORMING_INFO_8821C(x) \
+ ((x) & (~BITS_BEAMFORMING_INFO_8821C))
+#define BIT_GET_BEAMFORMING_INFO_8821C(x) \
+ (((x) >> BIT_SHIFT_BEAMFORMING_INFO_8821C) & \
+ BIT_MASK_BEAMFORMING_INFO_8821C)
+#define BIT_SET_BEAMFORMING_INFO_8821C(x, v) \
+ (BIT_CLEAR_BEAMFORMING_INFO_8821C(x) | BIT_BEAMFORMING_INFO_8821C(v))
+
+/* 2 REG_IPV6_8821C */
+
+#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8821C 0
+#define BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8821C 0xffffffffL
+#define BIT_R_WMAC_IPV6_MYIPAD_0_8821C(x) \
+ (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8821C) \
+ << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8821C)
+#define BITS_R_WMAC_IPV6_MYIPAD_0_8821C \
+ (BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8821C \
+ << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8821C)
+#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0_8821C(x) \
+ ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_0_8821C))
+#define BIT_GET_R_WMAC_IPV6_MYIPAD_0_8821C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8821C) & \
+ BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8821C)
+#define BIT_SET_R_WMAC_IPV6_MYIPAD_0_8821C(x, v) \
+ (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0_8821C(x) | \
+ BIT_R_WMAC_IPV6_MYIPAD_0_8821C(v))
+
+/* 2 REG_IPV6_1_8821C */
+
+#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8821C 0
+#define BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8821C 0xffffffffL
+#define BIT_R_WMAC_IPV6_MYIPAD_1_8821C(x) \
+ (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8821C) \
+ << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8821C)
+#define BITS_R_WMAC_IPV6_MYIPAD_1_8821C \
+ (BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8821C \
+ << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8821C)
+#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1_8821C(x) \
+ ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_1_8821C))
+#define BIT_GET_R_WMAC_IPV6_MYIPAD_1_8821C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8821C) & \
+ BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8821C)
+#define BIT_SET_R_WMAC_IPV6_MYIPAD_1_8821C(x, v) \
+ (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1_8821C(x) | \
+ BIT_R_WMAC_IPV6_MYIPAD_1_8821C(v))
+
+/* 2 REG_IPV6_2_8821C */
+
+#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8821C 0
+#define BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8821C 0xffffffffL
+#define BIT_R_WMAC_IPV6_MYIPAD_2_8821C(x) \
+ (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8821C) \
+ << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8821C)
+#define BITS_R_WMAC_IPV6_MYIPAD_2_8821C \
+ (BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8821C \
+ << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8821C)
+#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2_8821C(x) \
+ ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_2_8821C))
+#define BIT_GET_R_WMAC_IPV6_MYIPAD_2_8821C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8821C) & \
+ BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8821C)
+#define BIT_SET_R_WMAC_IPV6_MYIPAD_2_8821C(x, v) \
+ (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2_8821C(x) | \
+ BIT_R_WMAC_IPV6_MYIPAD_2_8821C(v))
+
+/* 2 REG_IPV6_3_8821C */
+
+#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8821C 0
+#define BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8821C 0xffffffffL
+#define BIT_R_WMAC_IPV6_MYIPAD_3_8821C(x) \
+ (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8821C) \
+ << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8821C)
+#define BITS_R_WMAC_IPV6_MYIPAD_3_8821C \
+ (BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8821C \
+ << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8821C)
+#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3_8821C(x) \
+ ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_3_8821C))
+#define BIT_GET_R_WMAC_IPV6_MYIPAD_3_8821C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8821C) & \
+ BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8821C)
+#define BIT_SET_R_WMAC_IPV6_MYIPAD_3_8821C(x, v) \
+ (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3_8821C(x) | \
+ BIT_R_WMAC_IPV6_MYIPAD_3_8821C(v))
/* 2 REG_NOT_VALID_8821C */
-#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_8821C 0
-#define BIT_MASK_R_WMAC_IPV6_MYIPAD_8821C 0xffffffffffffffffffffffffffffffffL
-#define BIT_R_WMAC_IPV6_MYIPAD_8821C(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_8821C) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_8821C)
-#define BIT_GET_R_WMAC_IPV6_MYIPAD_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_8821C) & BIT_MASK_R_WMAC_IPV6_MYIPAD_8821C)
+/* 2 REG_NOT_VALID_8821C */
+/* 2 REG_NOT_VALID_8821C */
-/* 2 REG_RSVD_0X740_8821C */
+/* 2 REG_NOT_VALID_8821C */
/* 2 REG_WMAC_RTX_CTX_SUBTYPE_CFG_8821C */
#define BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8821C 4
#define BIT_MASK_R_WMAC_CTX_SUBTYPE_8821C 0xf
-#define BIT_R_WMAC_CTX_SUBTYPE_8821C(x) (((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8821C) << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8821C)
-#define BIT_GET_R_WMAC_CTX_SUBTYPE_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8821C) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8821C)
-
+#define BIT_R_WMAC_CTX_SUBTYPE_8821C(x) \
+ (((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8821C) \
+ << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8821C)
+#define BITS_R_WMAC_CTX_SUBTYPE_8821C \
+ (BIT_MASK_R_WMAC_CTX_SUBTYPE_8821C \
+ << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8821C)
+#define BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8821C(x) \
+ ((x) & (~BITS_R_WMAC_CTX_SUBTYPE_8821C))
+#define BIT_GET_R_WMAC_CTX_SUBTYPE_8821C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8821C) & \
+ BIT_MASK_R_WMAC_CTX_SUBTYPE_8821C)
+#define BIT_SET_R_WMAC_CTX_SUBTYPE_8821C(x, v) \
+ (BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8821C(x) | \
+ BIT_R_WMAC_CTX_SUBTYPE_8821C(v))
#define BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8821C 0
#define BIT_MASK_R_WMAC_RTX_SUBTYPE_8821C 0xf
-#define BIT_R_WMAC_RTX_SUBTYPE_8821C(x) (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8821C) << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8821C)
-#define BIT_GET_R_WMAC_RTX_SUBTYPE_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8821C) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8821C)
+#define BIT_R_WMAC_RTX_SUBTYPE_8821C(x) \
+ (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8821C) \
+ << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8821C)
+#define BITS_R_WMAC_RTX_SUBTYPE_8821C \
+ (BIT_MASK_R_WMAC_RTX_SUBTYPE_8821C \
+ << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8821C)
+#define BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8821C(x) \
+ ((x) & (~BITS_R_WMAC_RTX_SUBTYPE_8821C))
+#define BIT_GET_R_WMAC_RTX_SUBTYPE_8821C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8821C) & \
+ BIT_MASK_R_WMAC_RTX_SUBTYPE_8821C)
+#define BIT_SET_R_WMAC_RTX_SUBTYPE_8821C(x, v) \
+ (BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8821C(x) | \
+ BIT_R_WMAC_RTX_SUBTYPE_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+/* 2 REG_NOT_VALID_8821C */
/* 2 REG_WMAC_SWAES_CFG_8821C */
@@ -9069,9 +17636,14 @@
#define BIT_SHIFT_TIMER_8821C 0
#define BIT_MASK_TIMER_8821C 0xff
-#define BIT_TIMER_8821C(x) (((x) & BIT_MASK_TIMER_8821C) << BIT_SHIFT_TIMER_8821C)
-#define BIT_GET_TIMER_8821C(x) (((x) >> BIT_SHIFT_TIMER_8821C) & BIT_MASK_TIMER_8821C)
-
+#define BIT_TIMER_8821C(x) \
+ (((x) & BIT_MASK_TIMER_8821C) << BIT_SHIFT_TIMER_8821C)
+#define BITS_TIMER_8821C (BIT_MASK_TIMER_8821C << BIT_SHIFT_TIMER_8821C)
+#define BIT_CLEAR_TIMER_8821C(x) ((x) & (~BITS_TIMER_8821C))
+#define BIT_GET_TIMER_8821C(x) \
+ (((x) >> BIT_SHIFT_TIMER_8821C) & BIT_MASK_TIMER_8821C)
+#define BIT_SET_TIMER_8821C(x, v) \
+ (BIT_CLEAR_TIMER_8821C(x) | BIT_TIMER_8821C(v))
/* 2 REG_BT_COEX_8821C */
#define BIT_R_GNT_BT_RFC_SW_8821C BIT(12)
@@ -9082,49 +17654,98 @@
#define BIT_SHIFT_R_BT_CNT_THR_8821C 0
#define BIT_MASK_R_BT_CNT_THR_8821C 0xff
-#define BIT_R_BT_CNT_THR_8821C(x) (((x) & BIT_MASK_R_BT_CNT_THR_8821C) << BIT_SHIFT_R_BT_CNT_THR_8821C)
-#define BIT_GET_R_BT_CNT_THR_8821C(x) (((x) >> BIT_SHIFT_R_BT_CNT_THR_8821C) & BIT_MASK_R_BT_CNT_THR_8821C)
-
+#define BIT_R_BT_CNT_THR_8821C(x) \
+ (((x) & BIT_MASK_R_BT_CNT_THR_8821C) << BIT_SHIFT_R_BT_CNT_THR_8821C)
+#define BITS_R_BT_CNT_THR_8821C \
+ (BIT_MASK_R_BT_CNT_THR_8821C << BIT_SHIFT_R_BT_CNT_THR_8821C)
+#define BIT_CLEAR_R_BT_CNT_THR_8821C(x) ((x) & (~BITS_R_BT_CNT_THR_8821C))
+#define BIT_GET_R_BT_CNT_THR_8821C(x) \
+ (((x) >> BIT_SHIFT_R_BT_CNT_THR_8821C) & BIT_MASK_R_BT_CNT_THR_8821C)
+#define BIT_SET_R_BT_CNT_THR_8821C(x, v) \
+ (BIT_CLEAR_R_BT_CNT_THR_8821C(x) | BIT_R_BT_CNT_THR_8821C(v))
/* 2 REG_WLAN_ACT_MASK_CTRL_8821C */
-#define BIT_WLRX_TER_BY_CTL_8821C BIT(43)
-#define BIT_WLRX_TER_BY_AD_8821C BIT(42)
-#define BIT_ANT_DIVERSITY_SEL_8821C BIT(41)
-#define BIT_ANTSEL_FOR_BT_CTRL_EN_8821C BIT(40)
-#define BIT_WLACT_LOW_GNTWL_EN_8821C BIT(34)
-#define BIT_WLACT_HIGH_GNTBT_EN_8821C BIT(33)
-#define BIT_NAV_UPPER_V1_8821C BIT(32)
#define BIT_SHIFT_RXMYRTS_NAV_V1_8821C 8
#define BIT_MASK_RXMYRTS_NAV_V1_8821C 0xff
-#define BIT_RXMYRTS_NAV_V1_8821C(x) (((x) & BIT_MASK_RXMYRTS_NAV_V1_8821C) << BIT_SHIFT_RXMYRTS_NAV_V1_8821C)
-#define BIT_GET_RXMYRTS_NAV_V1_8821C(x) (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8821C) & BIT_MASK_RXMYRTS_NAV_V1_8821C)
-
+#define BIT_RXMYRTS_NAV_V1_8821C(x) \
+ (((x) & BIT_MASK_RXMYRTS_NAV_V1_8821C) \
+ << BIT_SHIFT_RXMYRTS_NAV_V1_8821C)
+#define BITS_RXMYRTS_NAV_V1_8821C \
+ (BIT_MASK_RXMYRTS_NAV_V1_8821C << BIT_SHIFT_RXMYRTS_NAV_V1_8821C)
+#define BIT_CLEAR_RXMYRTS_NAV_V1_8821C(x) ((x) & (~BITS_RXMYRTS_NAV_V1_8821C))
+#define BIT_GET_RXMYRTS_NAV_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8821C) & \
+ BIT_MASK_RXMYRTS_NAV_V1_8821C)
+#define BIT_SET_RXMYRTS_NAV_V1_8821C(x, v) \
+ (BIT_CLEAR_RXMYRTS_NAV_V1_8821C(x) | BIT_RXMYRTS_NAV_V1_8821C(v))
#define BIT_SHIFT_RTSRST_V1_8821C 0
#define BIT_MASK_RTSRST_V1_8821C 0xff
-#define BIT_RTSRST_V1_8821C(x) (((x) & BIT_MASK_RTSRST_V1_8821C) << BIT_SHIFT_RTSRST_V1_8821C)
-#define BIT_GET_RTSRST_V1_8821C(x) (((x) >> BIT_SHIFT_RTSRST_V1_8821C) & BIT_MASK_RTSRST_V1_8821C)
-
+#define BIT_RTSRST_V1_8821C(x) \
+ (((x) & BIT_MASK_RTSRST_V1_8821C) << BIT_SHIFT_RTSRST_V1_8821C)
+#define BITS_RTSRST_V1_8821C \
+ (BIT_MASK_RTSRST_V1_8821C << BIT_SHIFT_RTSRST_V1_8821C)
+#define BIT_CLEAR_RTSRST_V1_8821C(x) ((x) & (~BITS_RTSRST_V1_8821C))
+#define BIT_GET_RTSRST_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_RTSRST_V1_8821C) & BIT_MASK_RTSRST_V1_8821C)
+#define BIT_SET_RTSRST_V1_8821C(x, v) \
+ (BIT_CLEAR_RTSRST_V1_8821C(x) | BIT_RTSRST_V1_8821C(v))
+
+/* 2 REG_WLAN_ACT_MASK_CTRL_1_8821C */
+#define BIT_WLRX_TER_BY_CTL_1_8821C BIT(11)
+#define BIT_WLRX_TER_BY_AD_1_8821C BIT(10)
+#define BIT_ANT_DIVERSITY_SEL_1_8821C BIT(9)
+#define BIT_ANTSEL_FOR_BT_CTRL_EN_1_8821C BIT(8)
+#define BIT_WLACT_LOW_GNTWL_EN_1_8821C BIT(2)
+#define BIT_WLACT_HIGH_GNTBT_EN_1_8821C BIT(1)
+#define BIT_NAV_UPPER_1_V1_8821C BIT(0)
/* 2 REG_BT_COEX_ENHANCED_INTR_CTRL_8821C */
#define BIT_SHIFT_BT_STAT_DELAY_8821C 12
#define BIT_MASK_BT_STAT_DELAY_8821C 0xf
-#define BIT_BT_STAT_DELAY_8821C(x) (((x) & BIT_MASK_BT_STAT_DELAY_8821C) << BIT_SHIFT_BT_STAT_DELAY_8821C)
-#define BIT_GET_BT_STAT_DELAY_8821C(x) (((x) >> BIT_SHIFT_BT_STAT_DELAY_8821C) & BIT_MASK_BT_STAT_DELAY_8821C)
-
+#define BIT_BT_STAT_DELAY_8821C(x) \
+ (((x) & BIT_MASK_BT_STAT_DELAY_8821C) << BIT_SHIFT_BT_STAT_DELAY_8821C)
+#define BITS_BT_STAT_DELAY_8821C \
+ (BIT_MASK_BT_STAT_DELAY_8821C << BIT_SHIFT_BT_STAT_DELAY_8821C)
+#define BIT_CLEAR_BT_STAT_DELAY_8821C(x) ((x) & (~BITS_BT_STAT_DELAY_8821C))
+#define BIT_GET_BT_STAT_DELAY_8821C(x) \
+ (((x) >> BIT_SHIFT_BT_STAT_DELAY_8821C) & BIT_MASK_BT_STAT_DELAY_8821C)
+#define BIT_SET_BT_STAT_DELAY_8821C(x, v) \
+ (BIT_CLEAR_BT_STAT_DELAY_8821C(x) | BIT_BT_STAT_DELAY_8821C(v))
#define BIT_SHIFT_BT_TRX_INIT_DETECT_8821C 8
#define BIT_MASK_BT_TRX_INIT_DETECT_8821C 0xf
-#define BIT_BT_TRX_INIT_DETECT_8821C(x) (((x) & BIT_MASK_BT_TRX_INIT_DETECT_8821C) << BIT_SHIFT_BT_TRX_INIT_DETECT_8821C)
-#define BIT_GET_BT_TRX_INIT_DETECT_8821C(x) (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8821C) & BIT_MASK_BT_TRX_INIT_DETECT_8821C)
-
+#define BIT_BT_TRX_INIT_DETECT_8821C(x) \
+ (((x) & BIT_MASK_BT_TRX_INIT_DETECT_8821C) \
+ << BIT_SHIFT_BT_TRX_INIT_DETECT_8821C)
+#define BITS_BT_TRX_INIT_DETECT_8821C \
+ (BIT_MASK_BT_TRX_INIT_DETECT_8821C \
+ << BIT_SHIFT_BT_TRX_INIT_DETECT_8821C)
+#define BIT_CLEAR_BT_TRX_INIT_DETECT_8821C(x) \
+ ((x) & (~BITS_BT_TRX_INIT_DETECT_8821C))
+#define BIT_GET_BT_TRX_INIT_DETECT_8821C(x) \
+ (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8821C) & \
+ BIT_MASK_BT_TRX_INIT_DETECT_8821C)
+#define BIT_SET_BT_TRX_INIT_DETECT_8821C(x, v) \
+ (BIT_CLEAR_BT_TRX_INIT_DETECT_8821C(x) | \
+ BIT_BT_TRX_INIT_DETECT_8821C(v))
#define BIT_SHIFT_BT_PRI_DETECT_TO_8821C 4
#define BIT_MASK_BT_PRI_DETECT_TO_8821C 0xf
-#define BIT_BT_PRI_DETECT_TO_8821C(x) (((x) & BIT_MASK_BT_PRI_DETECT_TO_8821C) << BIT_SHIFT_BT_PRI_DETECT_TO_8821C)
-#define BIT_GET_BT_PRI_DETECT_TO_8821C(x) (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8821C) & BIT_MASK_BT_PRI_DETECT_TO_8821C)
+#define BIT_BT_PRI_DETECT_TO_8821C(x) \
+ (((x) & BIT_MASK_BT_PRI_DETECT_TO_8821C) \
+ << BIT_SHIFT_BT_PRI_DETECT_TO_8821C)
+#define BITS_BT_PRI_DETECT_TO_8821C \
+ (BIT_MASK_BT_PRI_DETECT_TO_8821C << BIT_SHIFT_BT_PRI_DETECT_TO_8821C)
+#define BIT_CLEAR_BT_PRI_DETECT_TO_8821C(x) \
+ ((x) & (~BITS_BT_PRI_DETECT_TO_8821C))
+#define BIT_GET_BT_PRI_DETECT_TO_8821C(x) \
+ (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8821C) & \
+ BIT_MASK_BT_PRI_DETECT_TO_8821C)
+#define BIT_SET_BT_PRI_DETECT_TO_8821C(x, v) \
+ (BIT_CLEAR_BT_PRI_DETECT_TO_8821C(x) | BIT_BT_PRI_DETECT_TO_8821C(v))
#define BIT_R_GRANTALL_WLMASK_8821C BIT(3)
#define BIT_STATIS_BT_EN_8821C BIT(2)
@@ -9133,48 +17754,105 @@
/* 2 REG_BT_ACT_STATISTICS_8821C */
-#define BIT_SHIFT_STATIS_BT_LO_RX_8821C (48 & CPU_OPT_WIDTH)
-#define BIT_MASK_STATIS_BT_LO_RX_8821C 0xffff
-#define BIT_STATIS_BT_LO_RX_8821C(x) (((x) & BIT_MASK_STATIS_BT_LO_RX_8821C) << BIT_SHIFT_STATIS_BT_LO_RX_8821C)
-#define BIT_GET_STATIS_BT_LO_RX_8821C(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_RX_8821C) & BIT_MASK_STATIS_BT_LO_RX_8821C)
-
-
-#define BIT_SHIFT_STATIS_BT_LO_TX_8821C (32 & CPU_OPT_WIDTH)
-#define BIT_MASK_STATIS_BT_LO_TX_8821C 0xffff
-#define BIT_STATIS_BT_LO_TX_8821C(x) (((x) & BIT_MASK_STATIS_BT_LO_TX_8821C) << BIT_SHIFT_STATIS_BT_LO_TX_8821C)
-#define BIT_GET_STATIS_BT_LO_TX_8821C(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_TX_8821C) & BIT_MASK_STATIS_BT_LO_TX_8821C)
-
-
#define BIT_SHIFT_STATIS_BT_HI_RX_8821C 16
#define BIT_MASK_STATIS_BT_HI_RX_8821C 0xffff
-#define BIT_STATIS_BT_HI_RX_8821C(x) (((x) & BIT_MASK_STATIS_BT_HI_RX_8821C) << BIT_SHIFT_STATIS_BT_HI_RX_8821C)
-#define BIT_GET_STATIS_BT_HI_RX_8821C(x) (((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8821C) & BIT_MASK_STATIS_BT_HI_RX_8821C)
-
+#define BIT_STATIS_BT_HI_RX_8821C(x) \
+ (((x) & BIT_MASK_STATIS_BT_HI_RX_8821C) \
+ << BIT_SHIFT_STATIS_BT_HI_RX_8821C)
+#define BITS_STATIS_BT_HI_RX_8821C \
+ (BIT_MASK_STATIS_BT_HI_RX_8821C << BIT_SHIFT_STATIS_BT_HI_RX_8821C)
+#define BIT_CLEAR_STATIS_BT_HI_RX_8821C(x) ((x) & (~BITS_STATIS_BT_HI_RX_8821C))
+#define BIT_GET_STATIS_BT_HI_RX_8821C(x) \
+ (((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8821C) & \
+ BIT_MASK_STATIS_BT_HI_RX_8821C)
+#define BIT_SET_STATIS_BT_HI_RX_8821C(x, v) \
+ (BIT_CLEAR_STATIS_BT_HI_RX_8821C(x) | BIT_STATIS_BT_HI_RX_8821C(v))
#define BIT_SHIFT_STATIS_BT_HI_TX_8821C 0
#define BIT_MASK_STATIS_BT_HI_TX_8821C 0xffff
-#define BIT_STATIS_BT_HI_TX_8821C(x) (((x) & BIT_MASK_STATIS_BT_HI_TX_8821C) << BIT_SHIFT_STATIS_BT_HI_TX_8821C)
-#define BIT_GET_STATIS_BT_HI_TX_8821C(x) (((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8821C) & BIT_MASK_STATIS_BT_HI_TX_8821C)
-
+#define BIT_STATIS_BT_HI_TX_8821C(x) \
+ (((x) & BIT_MASK_STATIS_BT_HI_TX_8821C) \
+ << BIT_SHIFT_STATIS_BT_HI_TX_8821C)
+#define BITS_STATIS_BT_HI_TX_8821C \
+ (BIT_MASK_STATIS_BT_HI_TX_8821C << BIT_SHIFT_STATIS_BT_HI_TX_8821C)
+#define BIT_CLEAR_STATIS_BT_HI_TX_8821C(x) ((x) & (~BITS_STATIS_BT_HI_TX_8821C))
+#define BIT_GET_STATIS_BT_HI_TX_8821C(x) \
+ (((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8821C) & \
+ BIT_MASK_STATIS_BT_HI_TX_8821C)
+#define BIT_SET_STATIS_BT_HI_TX_8821C(x, v) \
+ (BIT_CLEAR_STATIS_BT_HI_TX_8821C(x) | BIT_STATIS_BT_HI_TX_8821C(v))
+
+/* 2 REG_BT_ACT_STATISTICS_1_8821C */
+
+#define BIT_SHIFT_STATIS_BT_LO_RX_1_8821C 16
+#define BIT_MASK_STATIS_BT_LO_RX_1_8821C 0xffff
+#define BIT_STATIS_BT_LO_RX_1_8821C(x) \
+ (((x) & BIT_MASK_STATIS_BT_LO_RX_1_8821C) \
+ << BIT_SHIFT_STATIS_BT_LO_RX_1_8821C)
+#define BITS_STATIS_BT_LO_RX_1_8821C \
+ (BIT_MASK_STATIS_BT_LO_RX_1_8821C << BIT_SHIFT_STATIS_BT_LO_RX_1_8821C)
+#define BIT_CLEAR_STATIS_BT_LO_RX_1_8821C(x) \
+ ((x) & (~BITS_STATIS_BT_LO_RX_1_8821C))
+#define BIT_GET_STATIS_BT_LO_RX_1_8821C(x) \
+ (((x) >> BIT_SHIFT_STATIS_BT_LO_RX_1_8821C) & \
+ BIT_MASK_STATIS_BT_LO_RX_1_8821C)
+#define BIT_SET_STATIS_BT_LO_RX_1_8821C(x, v) \
+ (BIT_CLEAR_STATIS_BT_LO_RX_1_8821C(x) | BIT_STATIS_BT_LO_RX_1_8821C(v))
+
+#define BIT_SHIFT_STATIS_BT_LO_TX_1_8821C 0
+#define BIT_MASK_STATIS_BT_LO_TX_1_8821C 0xffff
+#define BIT_STATIS_BT_LO_TX_1_8821C(x) \
+ (((x) & BIT_MASK_STATIS_BT_LO_TX_1_8821C) \
+ << BIT_SHIFT_STATIS_BT_LO_TX_1_8821C)
+#define BITS_STATIS_BT_LO_TX_1_8821C \
+ (BIT_MASK_STATIS_BT_LO_TX_1_8821C << BIT_SHIFT_STATIS_BT_LO_TX_1_8821C)
+#define BIT_CLEAR_STATIS_BT_LO_TX_1_8821C(x) \
+ ((x) & (~BITS_STATIS_BT_LO_TX_1_8821C))
+#define BIT_GET_STATIS_BT_LO_TX_1_8821C(x) \
+ (((x) >> BIT_SHIFT_STATIS_BT_LO_TX_1_8821C) & \
+ BIT_MASK_STATIS_BT_LO_TX_1_8821C)
+#define BIT_SET_STATIS_BT_LO_TX_1_8821C(x, v) \
+ (BIT_CLEAR_STATIS_BT_LO_TX_1_8821C(x) | BIT_STATIS_BT_LO_TX_1_8821C(v))
/* 2 REG_BT_STATISTICS_CONTROL_REGISTER_8821C */
#define BIT_SHIFT_R_BT_CMD_RPT_8821C 16
#define BIT_MASK_R_BT_CMD_RPT_8821C 0xffff
-#define BIT_R_BT_CMD_RPT_8821C(x) (((x) & BIT_MASK_R_BT_CMD_RPT_8821C) << BIT_SHIFT_R_BT_CMD_RPT_8821C)
-#define BIT_GET_R_BT_CMD_RPT_8821C(x) (((x) >> BIT_SHIFT_R_BT_CMD_RPT_8821C) & BIT_MASK_R_BT_CMD_RPT_8821C)
-
+#define BIT_R_BT_CMD_RPT_8821C(x) \
+ (((x) & BIT_MASK_R_BT_CMD_RPT_8821C) << BIT_SHIFT_R_BT_CMD_RPT_8821C)
+#define BITS_R_BT_CMD_RPT_8821C \
+ (BIT_MASK_R_BT_CMD_RPT_8821C << BIT_SHIFT_R_BT_CMD_RPT_8821C)
+#define BIT_CLEAR_R_BT_CMD_RPT_8821C(x) ((x) & (~BITS_R_BT_CMD_RPT_8821C))
+#define BIT_GET_R_BT_CMD_RPT_8821C(x) \
+ (((x) >> BIT_SHIFT_R_BT_CMD_RPT_8821C) & BIT_MASK_R_BT_CMD_RPT_8821C)
+#define BIT_SET_R_BT_CMD_RPT_8821C(x, v) \
+ (BIT_CLEAR_R_BT_CMD_RPT_8821C(x) | BIT_R_BT_CMD_RPT_8821C(v))
#define BIT_SHIFT_R_RPT_FROM_BT_8821C 8
#define BIT_MASK_R_RPT_FROM_BT_8821C 0xff
-#define BIT_R_RPT_FROM_BT_8821C(x) (((x) & BIT_MASK_R_RPT_FROM_BT_8821C) << BIT_SHIFT_R_RPT_FROM_BT_8821C)
-#define BIT_GET_R_RPT_FROM_BT_8821C(x) (((x) >> BIT_SHIFT_R_RPT_FROM_BT_8821C) & BIT_MASK_R_RPT_FROM_BT_8821C)
-
+#define BIT_R_RPT_FROM_BT_8821C(x) \
+ (((x) & BIT_MASK_R_RPT_FROM_BT_8821C) << BIT_SHIFT_R_RPT_FROM_BT_8821C)
+#define BITS_R_RPT_FROM_BT_8821C \
+ (BIT_MASK_R_RPT_FROM_BT_8821C << BIT_SHIFT_R_RPT_FROM_BT_8821C)
+#define BIT_CLEAR_R_RPT_FROM_BT_8821C(x) ((x) & (~BITS_R_RPT_FROM_BT_8821C))
+#define BIT_GET_R_RPT_FROM_BT_8821C(x) \
+ (((x) >> BIT_SHIFT_R_RPT_FROM_BT_8821C) & BIT_MASK_R_RPT_FROM_BT_8821C)
+#define BIT_SET_R_RPT_FROM_BT_8821C(x, v) \
+ (BIT_CLEAR_R_RPT_FROM_BT_8821C(x) | BIT_R_RPT_FROM_BT_8821C(v))
#define BIT_SHIFT_BT_HID_ISR_SET_8821C 6
#define BIT_MASK_BT_HID_ISR_SET_8821C 0x3
-#define BIT_BT_HID_ISR_SET_8821C(x) (((x) & BIT_MASK_BT_HID_ISR_SET_8821C) << BIT_SHIFT_BT_HID_ISR_SET_8821C)
-#define BIT_GET_BT_HID_ISR_SET_8821C(x) (((x) >> BIT_SHIFT_BT_HID_ISR_SET_8821C) & BIT_MASK_BT_HID_ISR_SET_8821C)
+#define BIT_BT_HID_ISR_SET_8821C(x) \
+ (((x) & BIT_MASK_BT_HID_ISR_SET_8821C) \
+ << BIT_SHIFT_BT_HID_ISR_SET_8821C)
+#define BITS_BT_HID_ISR_SET_8821C \
+ (BIT_MASK_BT_HID_ISR_SET_8821C << BIT_SHIFT_BT_HID_ISR_SET_8821C)
+#define BIT_CLEAR_BT_HID_ISR_SET_8821C(x) ((x) & (~BITS_BT_HID_ISR_SET_8821C))
+#define BIT_GET_BT_HID_ISR_SET_8821C(x) \
+ (((x) >> BIT_SHIFT_BT_HID_ISR_SET_8821C) & \
+ BIT_MASK_BT_HID_ISR_SET_8821C)
+#define BIT_SET_BT_HID_ISR_SET_8821C(x, v) \
+ (BIT_CLEAR_BT_HID_ISR_SET_8821C(x) | BIT_BT_HID_ISR_SET_8821C(v))
#define BIT_TDMA_BT_START_NOTIFY_8821C BIT(5)
#define BIT_ENABLE_TDMA_FW_MODE_8821C BIT(4)
@@ -9187,27 +17865,54 @@
#define BIT_SHIFT_BT_PROFILE_8821C 24
#define BIT_MASK_BT_PROFILE_8821C 0xff
-#define BIT_BT_PROFILE_8821C(x) (((x) & BIT_MASK_BT_PROFILE_8821C) << BIT_SHIFT_BT_PROFILE_8821C)
-#define BIT_GET_BT_PROFILE_8821C(x) (((x) >> BIT_SHIFT_BT_PROFILE_8821C) & BIT_MASK_BT_PROFILE_8821C)
-
+#define BIT_BT_PROFILE_8821C(x) \
+ (((x) & BIT_MASK_BT_PROFILE_8821C) << BIT_SHIFT_BT_PROFILE_8821C)
+#define BITS_BT_PROFILE_8821C \
+ (BIT_MASK_BT_PROFILE_8821C << BIT_SHIFT_BT_PROFILE_8821C)
+#define BIT_CLEAR_BT_PROFILE_8821C(x) ((x) & (~BITS_BT_PROFILE_8821C))
+#define BIT_GET_BT_PROFILE_8821C(x) \
+ (((x) >> BIT_SHIFT_BT_PROFILE_8821C) & BIT_MASK_BT_PROFILE_8821C)
+#define BIT_SET_BT_PROFILE_8821C(x, v) \
+ (BIT_CLEAR_BT_PROFILE_8821C(x) | BIT_BT_PROFILE_8821C(v))
#define BIT_SHIFT_BT_POWER_8821C 16
#define BIT_MASK_BT_POWER_8821C 0xff
-#define BIT_BT_POWER_8821C(x) (((x) & BIT_MASK_BT_POWER_8821C) << BIT_SHIFT_BT_POWER_8821C)
-#define BIT_GET_BT_POWER_8821C(x) (((x) >> BIT_SHIFT_BT_POWER_8821C) & BIT_MASK_BT_POWER_8821C)
-
+#define BIT_BT_POWER_8821C(x) \
+ (((x) & BIT_MASK_BT_POWER_8821C) << BIT_SHIFT_BT_POWER_8821C)
+#define BITS_BT_POWER_8821C \
+ (BIT_MASK_BT_POWER_8821C << BIT_SHIFT_BT_POWER_8821C)
+#define BIT_CLEAR_BT_POWER_8821C(x) ((x) & (~BITS_BT_POWER_8821C))
+#define BIT_GET_BT_POWER_8821C(x) \
+ (((x) >> BIT_SHIFT_BT_POWER_8821C) & BIT_MASK_BT_POWER_8821C)
+#define BIT_SET_BT_POWER_8821C(x, v) \
+ (BIT_CLEAR_BT_POWER_8821C(x) | BIT_BT_POWER_8821C(v))
#define BIT_SHIFT_BT_PREDECT_STATUS_8821C 8
#define BIT_MASK_BT_PREDECT_STATUS_8821C 0xff
-#define BIT_BT_PREDECT_STATUS_8821C(x) (((x) & BIT_MASK_BT_PREDECT_STATUS_8821C) << BIT_SHIFT_BT_PREDECT_STATUS_8821C)
-#define BIT_GET_BT_PREDECT_STATUS_8821C(x) (((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8821C) & BIT_MASK_BT_PREDECT_STATUS_8821C)
-
+#define BIT_BT_PREDECT_STATUS_8821C(x) \
+ (((x) & BIT_MASK_BT_PREDECT_STATUS_8821C) \
+ << BIT_SHIFT_BT_PREDECT_STATUS_8821C)
+#define BITS_BT_PREDECT_STATUS_8821C \
+ (BIT_MASK_BT_PREDECT_STATUS_8821C << BIT_SHIFT_BT_PREDECT_STATUS_8821C)
+#define BIT_CLEAR_BT_PREDECT_STATUS_8821C(x) \
+ ((x) & (~BITS_BT_PREDECT_STATUS_8821C))
+#define BIT_GET_BT_PREDECT_STATUS_8821C(x) \
+ (((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8821C) & \
+ BIT_MASK_BT_PREDECT_STATUS_8821C)
+#define BIT_SET_BT_PREDECT_STATUS_8821C(x, v) \
+ (BIT_CLEAR_BT_PREDECT_STATUS_8821C(x) | BIT_BT_PREDECT_STATUS_8821C(v))
#define BIT_SHIFT_BT_CMD_INFO_8821C 0
#define BIT_MASK_BT_CMD_INFO_8821C 0xff
-#define BIT_BT_CMD_INFO_8821C(x) (((x) & BIT_MASK_BT_CMD_INFO_8821C) << BIT_SHIFT_BT_CMD_INFO_8821C)
-#define BIT_GET_BT_CMD_INFO_8821C(x) (((x) >> BIT_SHIFT_BT_CMD_INFO_8821C) & BIT_MASK_BT_CMD_INFO_8821C)
-
+#define BIT_BT_CMD_INFO_8821C(x) \
+ (((x) & BIT_MASK_BT_CMD_INFO_8821C) << BIT_SHIFT_BT_CMD_INFO_8821C)
+#define BITS_BT_CMD_INFO_8821C \
+ (BIT_MASK_BT_CMD_INFO_8821C << BIT_SHIFT_BT_CMD_INFO_8821C)
+#define BIT_CLEAR_BT_CMD_INFO_8821C(x) ((x) & (~BITS_BT_CMD_INFO_8821C))
+#define BIT_GET_BT_CMD_INFO_8821C(x) \
+ (((x) >> BIT_SHIFT_BT_CMD_INFO_8821C) & BIT_MASK_BT_CMD_INFO_8821C)
+#define BIT_SET_BT_CMD_INFO_8821C(x, v) \
+ (BIT_CLEAR_BT_CMD_INFO_8821C(x) | BIT_BT_CMD_INFO_8821C(v))
/* 2 REG_BT_INTERRUPT_CONTROL_REGISTER_8821C */
#define BIT_EN_MAC_NULL_PKT_NOTIFY_8821C BIT(31)
@@ -9221,39 +17926,102 @@
#define BIT_SHIFT_WLAN_RPT_DATA_8821C 16
#define BIT_MASK_WLAN_RPT_DATA_8821C 0xff
-#define BIT_WLAN_RPT_DATA_8821C(x) (((x) & BIT_MASK_WLAN_RPT_DATA_8821C) << BIT_SHIFT_WLAN_RPT_DATA_8821C)
-#define BIT_GET_WLAN_RPT_DATA_8821C(x) (((x) >> BIT_SHIFT_WLAN_RPT_DATA_8821C) & BIT_MASK_WLAN_RPT_DATA_8821C)
-
+#define BIT_WLAN_RPT_DATA_8821C(x) \
+ (((x) & BIT_MASK_WLAN_RPT_DATA_8821C) << BIT_SHIFT_WLAN_RPT_DATA_8821C)
+#define BITS_WLAN_RPT_DATA_8821C \
+ (BIT_MASK_WLAN_RPT_DATA_8821C << BIT_SHIFT_WLAN_RPT_DATA_8821C)
+#define BIT_CLEAR_WLAN_RPT_DATA_8821C(x) ((x) & (~BITS_WLAN_RPT_DATA_8821C))
+#define BIT_GET_WLAN_RPT_DATA_8821C(x) \
+ (((x) >> BIT_SHIFT_WLAN_RPT_DATA_8821C) & BIT_MASK_WLAN_RPT_DATA_8821C)
+#define BIT_SET_WLAN_RPT_DATA_8821C(x, v) \
+ (BIT_CLEAR_WLAN_RPT_DATA_8821C(x) | BIT_WLAN_RPT_DATA_8821C(v))
#define BIT_SHIFT_CMD_ID_8821C 8
#define BIT_MASK_CMD_ID_8821C 0xff
-#define BIT_CMD_ID_8821C(x) (((x) & BIT_MASK_CMD_ID_8821C) << BIT_SHIFT_CMD_ID_8821C)
-#define BIT_GET_CMD_ID_8821C(x) (((x) >> BIT_SHIFT_CMD_ID_8821C) & BIT_MASK_CMD_ID_8821C)
-
+#define BIT_CMD_ID_8821C(x) \
+ (((x) & BIT_MASK_CMD_ID_8821C) << BIT_SHIFT_CMD_ID_8821C)
+#define BITS_CMD_ID_8821C (BIT_MASK_CMD_ID_8821C << BIT_SHIFT_CMD_ID_8821C)
+#define BIT_CLEAR_CMD_ID_8821C(x) ((x) & (~BITS_CMD_ID_8821C))
+#define BIT_GET_CMD_ID_8821C(x) \
+ (((x) >> BIT_SHIFT_CMD_ID_8821C) & BIT_MASK_CMD_ID_8821C)
+#define BIT_SET_CMD_ID_8821C(x, v) \
+ (BIT_CLEAR_CMD_ID_8821C(x) | BIT_CMD_ID_8821C(v))
#define BIT_SHIFT_BT_DATA_8821C 0
#define BIT_MASK_BT_DATA_8821C 0xff
-#define BIT_BT_DATA_8821C(x) (((x) & BIT_MASK_BT_DATA_8821C) << BIT_SHIFT_BT_DATA_8821C)
-#define BIT_GET_BT_DATA_8821C(x) (((x) >> BIT_SHIFT_BT_DATA_8821C) & BIT_MASK_BT_DATA_8821C)
-
+#define BIT_BT_DATA_8821C(x) \
+ (((x) & BIT_MASK_BT_DATA_8821C) << BIT_SHIFT_BT_DATA_8821C)
+#define BITS_BT_DATA_8821C (BIT_MASK_BT_DATA_8821C << BIT_SHIFT_BT_DATA_8821C)
+#define BIT_CLEAR_BT_DATA_8821C(x) ((x) & (~BITS_BT_DATA_8821C))
+#define BIT_GET_BT_DATA_8821C(x) \
+ (((x) >> BIT_SHIFT_BT_DATA_8821C) & BIT_MASK_BT_DATA_8821C)
+#define BIT_SET_BT_DATA_8821C(x, v) \
+ (BIT_CLEAR_BT_DATA_8821C(x) | BIT_BT_DATA_8821C(v))
/* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8821C */
#define BIT_SHIFT_WLAN_RPT_TO_8821C 0
#define BIT_MASK_WLAN_RPT_TO_8821C 0xff
-#define BIT_WLAN_RPT_TO_8821C(x) (((x) & BIT_MASK_WLAN_RPT_TO_8821C) << BIT_SHIFT_WLAN_RPT_TO_8821C)
-#define BIT_GET_WLAN_RPT_TO_8821C(x) (((x) >> BIT_SHIFT_WLAN_RPT_TO_8821C) & BIT_MASK_WLAN_RPT_TO_8821C)
-
+#define BIT_WLAN_RPT_TO_8821C(x) \
+ (((x) & BIT_MASK_WLAN_RPT_TO_8821C) << BIT_SHIFT_WLAN_RPT_TO_8821C)
+#define BITS_WLAN_RPT_TO_8821C \
+ (BIT_MASK_WLAN_RPT_TO_8821C << BIT_SHIFT_WLAN_RPT_TO_8821C)
+#define BIT_CLEAR_WLAN_RPT_TO_8821C(x) ((x) & (~BITS_WLAN_RPT_TO_8821C))
+#define BIT_GET_WLAN_RPT_TO_8821C(x) \
+ (((x) >> BIT_SHIFT_WLAN_RPT_TO_8821C) & BIT_MASK_WLAN_RPT_TO_8821C)
+#define BIT_SET_WLAN_RPT_TO_8821C(x, v) \
+ (BIT_CLEAR_WLAN_RPT_TO_8821C(x) | BIT_WLAN_RPT_TO_8821C(v))
/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8821C */
-#define BIT_SHIFT_ISOLATION_CHK_8821C 1
-#define BIT_MASK_ISOLATION_CHK_8821C 0x7fffffffffffffffffffL
-#define BIT_ISOLATION_CHK_8821C(x) (((x) & BIT_MASK_ISOLATION_CHK_8821C) << BIT_SHIFT_ISOLATION_CHK_8821C)
-#define BIT_GET_ISOLATION_CHK_8821C(x) (((x) >> BIT_SHIFT_ISOLATION_CHK_8821C) & BIT_MASK_ISOLATION_CHK_8821C)
+#define BIT_SHIFT_ISOLATION_CHK_0_8821C 1
+#define BIT_MASK_ISOLATION_CHK_0_8821C 0x7fffff
+#define BIT_ISOLATION_CHK_0_8821C(x) \
+ (((x) & BIT_MASK_ISOLATION_CHK_0_8821C) \
+ << BIT_SHIFT_ISOLATION_CHK_0_8821C)
+#define BITS_ISOLATION_CHK_0_8821C \
+ (BIT_MASK_ISOLATION_CHK_0_8821C << BIT_SHIFT_ISOLATION_CHK_0_8821C)
+#define BIT_CLEAR_ISOLATION_CHK_0_8821C(x) ((x) & (~BITS_ISOLATION_CHK_0_8821C))
+#define BIT_GET_ISOLATION_CHK_0_8821C(x) \
+ (((x) >> BIT_SHIFT_ISOLATION_CHK_0_8821C) & \
+ BIT_MASK_ISOLATION_CHK_0_8821C)
+#define BIT_SET_ISOLATION_CHK_0_8821C(x, v) \
+ (BIT_CLEAR_ISOLATION_CHK_0_8821C(x) | BIT_ISOLATION_CHK_0_8821C(v))
#define BIT_ISOLATION_EN_8821C BIT(0)
+/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1_8821C */
+
+#define BIT_SHIFT_ISOLATION_CHK_1_8821C 0
+#define BIT_MASK_ISOLATION_CHK_1_8821C 0xffffffffL
+#define BIT_ISOLATION_CHK_1_8821C(x) \
+ (((x) & BIT_MASK_ISOLATION_CHK_1_8821C) \
+ << BIT_SHIFT_ISOLATION_CHK_1_8821C)
+#define BITS_ISOLATION_CHK_1_8821C \
+ (BIT_MASK_ISOLATION_CHK_1_8821C << BIT_SHIFT_ISOLATION_CHK_1_8821C)
+#define BIT_CLEAR_ISOLATION_CHK_1_8821C(x) ((x) & (~BITS_ISOLATION_CHK_1_8821C))
+#define BIT_GET_ISOLATION_CHK_1_8821C(x) \
+ (((x) >> BIT_SHIFT_ISOLATION_CHK_1_8821C) & \
+ BIT_MASK_ISOLATION_CHK_1_8821C)
+#define BIT_SET_ISOLATION_CHK_1_8821C(x, v) \
+ (BIT_CLEAR_ISOLATION_CHK_1_8821C(x) | BIT_ISOLATION_CHK_1_8821C(v))
+
+/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2_8821C */
+
+#define BIT_SHIFT_ISOLATION_CHK_2_8821C 0
+#define BIT_MASK_ISOLATION_CHK_2_8821C 0xffffff
+#define BIT_ISOLATION_CHK_2_8821C(x) \
+ (((x) & BIT_MASK_ISOLATION_CHK_2_8821C) \
+ << BIT_SHIFT_ISOLATION_CHK_2_8821C)
+#define BITS_ISOLATION_CHK_2_8821C \
+ (BIT_MASK_ISOLATION_CHK_2_8821C << BIT_SHIFT_ISOLATION_CHK_2_8821C)
+#define BIT_CLEAR_ISOLATION_CHK_2_8821C(x) ((x) & (~BITS_ISOLATION_CHK_2_8821C))
+#define BIT_GET_ISOLATION_CHK_2_8821C(x) \
+ (((x) >> BIT_SHIFT_ISOLATION_CHK_2_8821C) & \
+ BIT_MASK_ISOLATION_CHK_2_8821C)
+#define BIT_SET_ISOLATION_CHK_2_8821C(x, v) \
+ (BIT_CLEAR_ISOLATION_CHK_2_8821C(x) | BIT_ISOLATION_CHK_2_8821C(v))
+
/* 2 REG_BT_INTERRUPT_STATUS_REGISTER_8821C */
#define BIT_BT_HID_ISR_8821C BIT(7)
#define BIT_BT_QUERY_ISR_8821C BIT(6)
@@ -9268,22 +18036,45 @@
#define BIT_SHIFT_BT_TIME_8821C 6
#define BIT_MASK_BT_TIME_8821C 0x3ffffff
-#define BIT_BT_TIME_8821C(x) (((x) & BIT_MASK_BT_TIME_8821C) << BIT_SHIFT_BT_TIME_8821C)
-#define BIT_GET_BT_TIME_8821C(x) (((x) >> BIT_SHIFT_BT_TIME_8821C) & BIT_MASK_BT_TIME_8821C)
-
+#define BIT_BT_TIME_8821C(x) \
+ (((x) & BIT_MASK_BT_TIME_8821C) << BIT_SHIFT_BT_TIME_8821C)
+#define BITS_BT_TIME_8821C (BIT_MASK_BT_TIME_8821C << BIT_SHIFT_BT_TIME_8821C)
+#define BIT_CLEAR_BT_TIME_8821C(x) ((x) & (~BITS_BT_TIME_8821C))
+#define BIT_GET_BT_TIME_8821C(x) \
+ (((x) >> BIT_SHIFT_BT_TIME_8821C) & BIT_MASK_BT_TIME_8821C)
+#define BIT_SET_BT_TIME_8821C(x, v) \
+ (BIT_CLEAR_BT_TIME_8821C(x) | BIT_BT_TIME_8821C(v))
#define BIT_SHIFT_BT_RPT_SAMPLE_RATE_8821C 0
#define BIT_MASK_BT_RPT_SAMPLE_RATE_8821C 0x3f
-#define BIT_BT_RPT_SAMPLE_RATE_8821C(x) (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8821C) << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8821C)
-#define BIT_GET_BT_RPT_SAMPLE_RATE_8821C(x) (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8821C) & BIT_MASK_BT_RPT_SAMPLE_RATE_8821C)
-
+#define BIT_BT_RPT_SAMPLE_RATE_8821C(x) \
+ (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8821C) \
+ << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8821C)
+#define BITS_BT_RPT_SAMPLE_RATE_8821C \
+ (BIT_MASK_BT_RPT_SAMPLE_RATE_8821C \
+ << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8821C)
+#define BIT_CLEAR_BT_RPT_SAMPLE_RATE_8821C(x) \
+ ((x) & (~BITS_BT_RPT_SAMPLE_RATE_8821C))
+#define BIT_GET_BT_RPT_SAMPLE_RATE_8821C(x) \
+ (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8821C) & \
+ BIT_MASK_BT_RPT_SAMPLE_RATE_8821C)
+#define BIT_SET_BT_RPT_SAMPLE_RATE_8821C(x, v) \
+ (BIT_CLEAR_BT_RPT_SAMPLE_RATE_8821C(x) | \
+ BIT_BT_RPT_SAMPLE_RATE_8821C(v))
/* 2 REG_BT_ACT_REGISTER_8821C */
#define BIT_SHIFT_BT_EISR_EN_8821C 16
#define BIT_MASK_BT_EISR_EN_8821C 0xff
-#define BIT_BT_EISR_EN_8821C(x) (((x) & BIT_MASK_BT_EISR_EN_8821C) << BIT_SHIFT_BT_EISR_EN_8821C)
-#define BIT_GET_BT_EISR_EN_8821C(x) (((x) >> BIT_SHIFT_BT_EISR_EN_8821C) & BIT_MASK_BT_EISR_EN_8821C)
+#define BIT_BT_EISR_EN_8821C(x) \
+ (((x) & BIT_MASK_BT_EISR_EN_8821C) << BIT_SHIFT_BT_EISR_EN_8821C)
+#define BITS_BT_EISR_EN_8821C \
+ (BIT_MASK_BT_EISR_EN_8821C << BIT_SHIFT_BT_EISR_EN_8821C)
+#define BIT_CLEAR_BT_EISR_EN_8821C(x) ((x) & (~BITS_BT_EISR_EN_8821C))
+#define BIT_GET_BT_EISR_EN_8821C(x) \
+ (((x) >> BIT_SHIFT_BT_EISR_EN_8821C) & BIT_MASK_BT_EISR_EN_8821C)
+#define BIT_SET_BT_EISR_EN_8821C(x, v) \
+ (BIT_CLEAR_BT_EISR_EN_8821C(x) | BIT_BT_EISR_EN_8821C(v))
#define BIT_BT_ACT_FALLING_ISR_8821C BIT(10)
#define BIT_BT_ACT_RISING_ISR_8821C BIT(9)
@@ -9291,17 +18082,29 @@
#define BIT_SHIFT_BT_CH_8821C 0
#define BIT_MASK_BT_CH_8821C 0xff
-#define BIT_BT_CH_8821C(x) (((x) & BIT_MASK_BT_CH_8821C) << BIT_SHIFT_BT_CH_8821C)
-#define BIT_GET_BT_CH_8821C(x) (((x) >> BIT_SHIFT_BT_CH_8821C) & BIT_MASK_BT_CH_8821C)
-
+#define BIT_BT_CH_8821C(x) \
+ (((x) & BIT_MASK_BT_CH_8821C) << BIT_SHIFT_BT_CH_8821C)
+#define BITS_BT_CH_8821C (BIT_MASK_BT_CH_8821C << BIT_SHIFT_BT_CH_8821C)
+#define BIT_CLEAR_BT_CH_8821C(x) ((x) & (~BITS_BT_CH_8821C))
+#define BIT_GET_BT_CH_8821C(x) \
+ (((x) >> BIT_SHIFT_BT_CH_8821C) & BIT_MASK_BT_CH_8821C)
+#define BIT_SET_BT_CH_8821C(x, v) \
+ (BIT_CLEAR_BT_CH_8821C(x) | BIT_BT_CH_8821C(v))
/* 2 REG_OBFF_CTRL_BASIC_8821C */
#define BIT_OBFF_EN_V1_8821C BIT(31)
#define BIT_SHIFT_OBFF_STATE_V1_8821C 28
#define BIT_MASK_OBFF_STATE_V1_8821C 0x3
-#define BIT_OBFF_STATE_V1_8821C(x) (((x) & BIT_MASK_OBFF_STATE_V1_8821C) << BIT_SHIFT_OBFF_STATE_V1_8821C)
-#define BIT_GET_OBFF_STATE_V1_8821C(x) (((x) >> BIT_SHIFT_OBFF_STATE_V1_8821C) & BIT_MASK_OBFF_STATE_V1_8821C)
+#define BIT_OBFF_STATE_V1_8821C(x) \
+ (((x) & BIT_MASK_OBFF_STATE_V1_8821C) << BIT_SHIFT_OBFF_STATE_V1_8821C)
+#define BITS_OBFF_STATE_V1_8821C \
+ (BIT_MASK_OBFF_STATE_V1_8821C << BIT_SHIFT_OBFF_STATE_V1_8821C)
+#define BIT_CLEAR_OBFF_STATE_V1_8821C(x) ((x) & (~BITS_OBFF_STATE_V1_8821C))
+#define BIT_GET_OBFF_STATE_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_OBFF_STATE_V1_8821C) & BIT_MASK_OBFF_STATE_V1_8821C)
+#define BIT_SET_OBFF_STATE_V1_8821C(x, v) \
+ (BIT_CLEAR_OBFF_STATE_V1_8821C(x) | BIT_OBFF_STATE_V1_8821C(v))
#define BIT_OBFF_ACT_RXDMA_EN_8821C BIT(27)
#define BIT_OBFF_BLOCK_INT_EN_8821C BIT(26)
@@ -9310,26 +18113,51 @@
#define BIT_SHIFT_WAKE_MAX_PLS_8821C 20
#define BIT_MASK_WAKE_MAX_PLS_8821C 0x7
-#define BIT_WAKE_MAX_PLS_8821C(x) (((x) & BIT_MASK_WAKE_MAX_PLS_8821C) << BIT_SHIFT_WAKE_MAX_PLS_8821C)
-#define BIT_GET_WAKE_MAX_PLS_8821C(x) (((x) >> BIT_SHIFT_WAKE_MAX_PLS_8821C) & BIT_MASK_WAKE_MAX_PLS_8821C)
-
+#define BIT_WAKE_MAX_PLS_8821C(x) \
+ (((x) & BIT_MASK_WAKE_MAX_PLS_8821C) << BIT_SHIFT_WAKE_MAX_PLS_8821C)
+#define BITS_WAKE_MAX_PLS_8821C \
+ (BIT_MASK_WAKE_MAX_PLS_8821C << BIT_SHIFT_WAKE_MAX_PLS_8821C)
+#define BIT_CLEAR_WAKE_MAX_PLS_8821C(x) ((x) & (~BITS_WAKE_MAX_PLS_8821C))
+#define BIT_GET_WAKE_MAX_PLS_8821C(x) \
+ (((x) >> BIT_SHIFT_WAKE_MAX_PLS_8821C) & BIT_MASK_WAKE_MAX_PLS_8821C)
+#define BIT_SET_WAKE_MAX_PLS_8821C(x, v) \
+ (BIT_CLEAR_WAKE_MAX_PLS_8821C(x) | BIT_WAKE_MAX_PLS_8821C(v))
#define BIT_SHIFT_WAKE_MIN_PLS_8821C 16
#define BIT_MASK_WAKE_MIN_PLS_8821C 0x7
-#define BIT_WAKE_MIN_PLS_8821C(x) (((x) & BIT_MASK_WAKE_MIN_PLS_8821C) << BIT_SHIFT_WAKE_MIN_PLS_8821C)
-#define BIT_GET_WAKE_MIN_PLS_8821C(x) (((x) >> BIT_SHIFT_WAKE_MIN_PLS_8821C) & BIT_MASK_WAKE_MIN_PLS_8821C)
-
+#define BIT_WAKE_MIN_PLS_8821C(x) \
+ (((x) & BIT_MASK_WAKE_MIN_PLS_8821C) << BIT_SHIFT_WAKE_MIN_PLS_8821C)
+#define BITS_WAKE_MIN_PLS_8821C \
+ (BIT_MASK_WAKE_MIN_PLS_8821C << BIT_SHIFT_WAKE_MIN_PLS_8821C)
+#define BIT_CLEAR_WAKE_MIN_PLS_8821C(x) ((x) & (~BITS_WAKE_MIN_PLS_8821C))
+#define BIT_GET_WAKE_MIN_PLS_8821C(x) \
+ (((x) >> BIT_SHIFT_WAKE_MIN_PLS_8821C) & BIT_MASK_WAKE_MIN_PLS_8821C)
+#define BIT_SET_WAKE_MIN_PLS_8821C(x, v) \
+ (BIT_CLEAR_WAKE_MIN_PLS_8821C(x) | BIT_WAKE_MIN_PLS_8821C(v))
#define BIT_SHIFT_WAKE_MAX_F2F_8821C 12
#define BIT_MASK_WAKE_MAX_F2F_8821C 0x7
-#define BIT_WAKE_MAX_F2F_8821C(x) (((x) & BIT_MASK_WAKE_MAX_F2F_8821C) << BIT_SHIFT_WAKE_MAX_F2F_8821C)
-#define BIT_GET_WAKE_MAX_F2F_8821C(x) (((x) >> BIT_SHIFT_WAKE_MAX_F2F_8821C) & BIT_MASK_WAKE_MAX_F2F_8821C)
-
+#define BIT_WAKE_MAX_F2F_8821C(x) \
+ (((x) & BIT_MASK_WAKE_MAX_F2F_8821C) << BIT_SHIFT_WAKE_MAX_F2F_8821C)
+#define BITS_WAKE_MAX_F2F_8821C \
+ (BIT_MASK_WAKE_MAX_F2F_8821C << BIT_SHIFT_WAKE_MAX_F2F_8821C)
+#define BIT_CLEAR_WAKE_MAX_F2F_8821C(x) ((x) & (~BITS_WAKE_MAX_F2F_8821C))
+#define BIT_GET_WAKE_MAX_F2F_8821C(x) \
+ (((x) >> BIT_SHIFT_WAKE_MAX_F2F_8821C) & BIT_MASK_WAKE_MAX_F2F_8821C)
+#define BIT_SET_WAKE_MAX_F2F_8821C(x, v) \
+ (BIT_CLEAR_WAKE_MAX_F2F_8821C(x) | BIT_WAKE_MAX_F2F_8821C(v))
#define BIT_SHIFT_WAKE_MIN_F2F_8821C 8
#define BIT_MASK_WAKE_MIN_F2F_8821C 0x7
-#define BIT_WAKE_MIN_F2F_8821C(x) (((x) & BIT_MASK_WAKE_MIN_F2F_8821C) << BIT_SHIFT_WAKE_MIN_F2F_8821C)
-#define BIT_GET_WAKE_MIN_F2F_8821C(x) (((x) >> BIT_SHIFT_WAKE_MIN_F2F_8821C) & BIT_MASK_WAKE_MIN_F2F_8821C)
+#define BIT_WAKE_MIN_F2F_8821C(x) \
+ (((x) & BIT_MASK_WAKE_MIN_F2F_8821C) << BIT_SHIFT_WAKE_MIN_F2F_8821C)
+#define BITS_WAKE_MIN_F2F_8821C \
+ (BIT_MASK_WAKE_MIN_F2F_8821C << BIT_SHIFT_WAKE_MIN_F2F_8821C)
+#define BIT_CLEAR_WAKE_MIN_F2F_8821C(x) ((x) & (~BITS_WAKE_MIN_F2F_8821C))
+#define BIT_GET_WAKE_MIN_F2F_8821C(x) \
+ (((x) >> BIT_SHIFT_WAKE_MIN_F2F_8821C) & BIT_MASK_WAKE_MIN_F2F_8821C)
+#define BIT_SET_WAKE_MIN_F2F_8821C(x, v) \
+ (BIT_CLEAR_WAKE_MIN_F2F_8821C(x) | BIT_WAKE_MIN_F2F_8821C(v))
#define BIT_APP_CPU_ACT_V1_8821C BIT(3)
#define BIT_APP_OBFF_V1_8821C BIT(2)
@@ -9340,27 +18168,65 @@
#define BIT_SHIFT_RX_HIGH_TIMER_IDX_8821C 24
#define BIT_MASK_RX_HIGH_TIMER_IDX_8821C 0x7
-#define BIT_RX_HIGH_TIMER_IDX_8821C(x) (((x) & BIT_MASK_RX_HIGH_TIMER_IDX_8821C) << BIT_SHIFT_RX_HIGH_TIMER_IDX_8821C)
-#define BIT_GET_RX_HIGH_TIMER_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8821C) & BIT_MASK_RX_HIGH_TIMER_IDX_8821C)
-
+#define BIT_RX_HIGH_TIMER_IDX_8821C(x) \
+ (((x) & BIT_MASK_RX_HIGH_TIMER_IDX_8821C) \
+ << BIT_SHIFT_RX_HIGH_TIMER_IDX_8821C)
+#define BITS_RX_HIGH_TIMER_IDX_8821C \
+ (BIT_MASK_RX_HIGH_TIMER_IDX_8821C << BIT_SHIFT_RX_HIGH_TIMER_IDX_8821C)
+#define BIT_CLEAR_RX_HIGH_TIMER_IDX_8821C(x) \
+ ((x) & (~BITS_RX_HIGH_TIMER_IDX_8821C))
+#define BIT_GET_RX_HIGH_TIMER_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8821C) & \
+ BIT_MASK_RX_HIGH_TIMER_IDX_8821C)
+#define BIT_SET_RX_HIGH_TIMER_IDX_8821C(x, v) \
+ (BIT_CLEAR_RX_HIGH_TIMER_IDX_8821C(x) | BIT_RX_HIGH_TIMER_IDX_8821C(v))
#define BIT_SHIFT_RX_MED_TIMER_IDX_8821C 16
#define BIT_MASK_RX_MED_TIMER_IDX_8821C 0x7
-#define BIT_RX_MED_TIMER_IDX_8821C(x) (((x) & BIT_MASK_RX_MED_TIMER_IDX_8821C) << BIT_SHIFT_RX_MED_TIMER_IDX_8821C)
-#define BIT_GET_RX_MED_TIMER_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8821C) & BIT_MASK_RX_MED_TIMER_IDX_8821C)
-
+#define BIT_RX_MED_TIMER_IDX_8821C(x) \
+ (((x) & BIT_MASK_RX_MED_TIMER_IDX_8821C) \
+ << BIT_SHIFT_RX_MED_TIMER_IDX_8821C)
+#define BITS_RX_MED_TIMER_IDX_8821C \
+ (BIT_MASK_RX_MED_TIMER_IDX_8821C << BIT_SHIFT_RX_MED_TIMER_IDX_8821C)
+#define BIT_CLEAR_RX_MED_TIMER_IDX_8821C(x) \
+ ((x) & (~BITS_RX_MED_TIMER_IDX_8821C))
+#define BIT_GET_RX_MED_TIMER_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8821C) & \
+ BIT_MASK_RX_MED_TIMER_IDX_8821C)
+#define BIT_SET_RX_MED_TIMER_IDX_8821C(x, v) \
+ (BIT_CLEAR_RX_MED_TIMER_IDX_8821C(x) | BIT_RX_MED_TIMER_IDX_8821C(v))
#define BIT_SHIFT_RX_LOW_TIMER_IDX_8821C 8
#define BIT_MASK_RX_LOW_TIMER_IDX_8821C 0x7
-#define BIT_RX_LOW_TIMER_IDX_8821C(x) (((x) & BIT_MASK_RX_LOW_TIMER_IDX_8821C) << BIT_SHIFT_RX_LOW_TIMER_IDX_8821C)
-#define BIT_GET_RX_LOW_TIMER_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8821C) & BIT_MASK_RX_LOW_TIMER_IDX_8821C)
-
+#define BIT_RX_LOW_TIMER_IDX_8821C(x) \
+ (((x) & BIT_MASK_RX_LOW_TIMER_IDX_8821C) \
+ << BIT_SHIFT_RX_LOW_TIMER_IDX_8821C)
+#define BITS_RX_LOW_TIMER_IDX_8821C \
+ (BIT_MASK_RX_LOW_TIMER_IDX_8821C << BIT_SHIFT_RX_LOW_TIMER_IDX_8821C)
+#define BIT_CLEAR_RX_LOW_TIMER_IDX_8821C(x) \
+ ((x) & (~BITS_RX_LOW_TIMER_IDX_8821C))
+#define BIT_GET_RX_LOW_TIMER_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8821C) & \
+ BIT_MASK_RX_LOW_TIMER_IDX_8821C)
+#define BIT_SET_RX_LOW_TIMER_IDX_8821C(x, v) \
+ (BIT_CLEAR_RX_LOW_TIMER_IDX_8821C(x) | BIT_RX_LOW_TIMER_IDX_8821C(v))
#define BIT_SHIFT_OBFF_INT_TIMER_IDX_8821C 0
#define BIT_MASK_OBFF_INT_TIMER_IDX_8821C 0x7
-#define BIT_OBFF_INT_TIMER_IDX_8821C(x) (((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8821C) << BIT_SHIFT_OBFF_INT_TIMER_IDX_8821C)
-#define BIT_GET_OBFF_INT_TIMER_IDX_8821C(x) (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8821C) & BIT_MASK_OBFF_INT_TIMER_IDX_8821C)
-
+#define BIT_OBFF_INT_TIMER_IDX_8821C(x) \
+ (((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8821C) \
+ << BIT_SHIFT_OBFF_INT_TIMER_IDX_8821C)
+#define BITS_OBFF_INT_TIMER_IDX_8821C \
+ (BIT_MASK_OBFF_INT_TIMER_IDX_8821C \
+ << BIT_SHIFT_OBFF_INT_TIMER_IDX_8821C)
+#define BIT_CLEAR_OBFF_INT_TIMER_IDX_8821C(x) \
+ ((x) & (~BITS_OBFF_INT_TIMER_IDX_8821C))
+#define BIT_GET_OBFF_INT_TIMER_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8821C) & \
+ BIT_MASK_OBFF_INT_TIMER_IDX_8821C)
+#define BIT_SET_OBFF_INT_TIMER_IDX_8821C(x, v) \
+ (BIT_CLEAR_OBFF_INT_TIMER_IDX_8821C(x) | \
+ BIT_OBFF_INT_TIMER_IDX_8821C(v))
/* 2 REG_LTR_CTRL_BASIC_8821C */
#define BIT_LTR_EN_V1_8821C BIT(31)
@@ -9376,113 +18242,260 @@
#define BIT_SHIFT_HIGH_RATE_TRIG_SEL_8821C 20
#define BIT_MASK_HIGH_RATE_TRIG_SEL_8821C 0x3
-#define BIT_HIGH_RATE_TRIG_SEL_8821C(x) (((x) & BIT_MASK_HIGH_RATE_TRIG_SEL_8821C) << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8821C)
-#define BIT_GET_HIGH_RATE_TRIG_SEL_8821C(x) (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8821C) & BIT_MASK_HIGH_RATE_TRIG_SEL_8821C)
-
+#define BIT_HIGH_RATE_TRIG_SEL_8821C(x) \
+ (((x) & BIT_MASK_HIGH_RATE_TRIG_SEL_8821C) \
+ << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8821C)
+#define BITS_HIGH_RATE_TRIG_SEL_8821C \
+ (BIT_MASK_HIGH_RATE_TRIG_SEL_8821C \
+ << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8821C)
+#define BIT_CLEAR_HIGH_RATE_TRIG_SEL_8821C(x) \
+ ((x) & (~BITS_HIGH_RATE_TRIG_SEL_8821C))
+#define BIT_GET_HIGH_RATE_TRIG_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8821C) & \
+ BIT_MASK_HIGH_RATE_TRIG_SEL_8821C)
+#define BIT_SET_HIGH_RATE_TRIG_SEL_8821C(x, v) \
+ (BIT_CLEAR_HIGH_RATE_TRIG_SEL_8821C(x) | \
+ BIT_HIGH_RATE_TRIG_SEL_8821C(v))
#define BIT_SHIFT_MED_RATE_TRIG_SEL_8821C 18
#define BIT_MASK_MED_RATE_TRIG_SEL_8821C 0x3
-#define BIT_MED_RATE_TRIG_SEL_8821C(x) (((x) & BIT_MASK_MED_RATE_TRIG_SEL_8821C) << BIT_SHIFT_MED_RATE_TRIG_SEL_8821C)
-#define BIT_GET_MED_RATE_TRIG_SEL_8821C(x) (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8821C) & BIT_MASK_MED_RATE_TRIG_SEL_8821C)
-
+#define BIT_MED_RATE_TRIG_SEL_8821C(x) \
+ (((x) & BIT_MASK_MED_RATE_TRIG_SEL_8821C) \
+ << BIT_SHIFT_MED_RATE_TRIG_SEL_8821C)
+#define BITS_MED_RATE_TRIG_SEL_8821C \
+ (BIT_MASK_MED_RATE_TRIG_SEL_8821C << BIT_SHIFT_MED_RATE_TRIG_SEL_8821C)
+#define BIT_CLEAR_MED_RATE_TRIG_SEL_8821C(x) \
+ ((x) & (~BITS_MED_RATE_TRIG_SEL_8821C))
+#define BIT_GET_MED_RATE_TRIG_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8821C) & \
+ BIT_MASK_MED_RATE_TRIG_SEL_8821C)
+#define BIT_SET_MED_RATE_TRIG_SEL_8821C(x, v) \
+ (BIT_CLEAR_MED_RATE_TRIG_SEL_8821C(x) | BIT_MED_RATE_TRIG_SEL_8821C(v))
#define BIT_SHIFT_LOW_RATE_TRIG_SEL_8821C 16
#define BIT_MASK_LOW_RATE_TRIG_SEL_8821C 0x3
-#define BIT_LOW_RATE_TRIG_SEL_8821C(x) (((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8821C) << BIT_SHIFT_LOW_RATE_TRIG_SEL_8821C)
-#define BIT_GET_LOW_RATE_TRIG_SEL_8821C(x) (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8821C) & BIT_MASK_LOW_RATE_TRIG_SEL_8821C)
-
+#define BIT_LOW_RATE_TRIG_SEL_8821C(x) \
+ (((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8821C) \
+ << BIT_SHIFT_LOW_RATE_TRIG_SEL_8821C)
+#define BITS_LOW_RATE_TRIG_SEL_8821C \
+ (BIT_MASK_LOW_RATE_TRIG_SEL_8821C << BIT_SHIFT_LOW_RATE_TRIG_SEL_8821C)
+#define BIT_CLEAR_LOW_RATE_TRIG_SEL_8821C(x) \
+ ((x) & (~BITS_LOW_RATE_TRIG_SEL_8821C))
+#define BIT_GET_LOW_RATE_TRIG_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8821C) & \
+ BIT_MASK_LOW_RATE_TRIG_SEL_8821C)
+#define BIT_SET_LOW_RATE_TRIG_SEL_8821C(x, v) \
+ (BIT_CLEAR_LOW_RATE_TRIG_SEL_8821C(x) | BIT_LOW_RATE_TRIG_SEL_8821C(v))
#define BIT_SHIFT_HIGH_RATE_BD_IDX_8821C 8
#define BIT_MASK_HIGH_RATE_BD_IDX_8821C 0x7f
-#define BIT_HIGH_RATE_BD_IDX_8821C(x) (((x) & BIT_MASK_HIGH_RATE_BD_IDX_8821C) << BIT_SHIFT_HIGH_RATE_BD_IDX_8821C)
-#define BIT_GET_HIGH_RATE_BD_IDX_8821C(x) (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8821C) & BIT_MASK_HIGH_RATE_BD_IDX_8821C)
-
+#define BIT_HIGH_RATE_BD_IDX_8821C(x) \
+ (((x) & BIT_MASK_HIGH_RATE_BD_IDX_8821C) \
+ << BIT_SHIFT_HIGH_RATE_BD_IDX_8821C)
+#define BITS_HIGH_RATE_BD_IDX_8821C \
+ (BIT_MASK_HIGH_RATE_BD_IDX_8821C << BIT_SHIFT_HIGH_RATE_BD_IDX_8821C)
+#define BIT_CLEAR_HIGH_RATE_BD_IDX_8821C(x) \
+ ((x) & (~BITS_HIGH_RATE_BD_IDX_8821C))
+#define BIT_GET_HIGH_RATE_BD_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8821C) & \
+ BIT_MASK_HIGH_RATE_BD_IDX_8821C)
+#define BIT_SET_HIGH_RATE_BD_IDX_8821C(x, v) \
+ (BIT_CLEAR_HIGH_RATE_BD_IDX_8821C(x) | BIT_HIGH_RATE_BD_IDX_8821C(v))
#define BIT_SHIFT_LOW_RATE_BD_IDX_8821C 0
#define BIT_MASK_LOW_RATE_BD_IDX_8821C 0x7f
-#define BIT_LOW_RATE_BD_IDX_8821C(x) (((x) & BIT_MASK_LOW_RATE_BD_IDX_8821C) << BIT_SHIFT_LOW_RATE_BD_IDX_8821C)
-#define BIT_GET_LOW_RATE_BD_IDX_8821C(x) (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8821C) & BIT_MASK_LOW_RATE_BD_IDX_8821C)
-
+#define BIT_LOW_RATE_BD_IDX_8821C(x) \
+ (((x) & BIT_MASK_LOW_RATE_BD_IDX_8821C) \
+ << BIT_SHIFT_LOW_RATE_BD_IDX_8821C)
+#define BITS_LOW_RATE_BD_IDX_8821C \
+ (BIT_MASK_LOW_RATE_BD_IDX_8821C << BIT_SHIFT_LOW_RATE_BD_IDX_8821C)
+#define BIT_CLEAR_LOW_RATE_BD_IDX_8821C(x) ((x) & (~BITS_LOW_RATE_BD_IDX_8821C))
+#define BIT_GET_LOW_RATE_BD_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8821C) & \
+ BIT_MASK_LOW_RATE_BD_IDX_8821C)
+#define BIT_SET_LOW_RATE_BD_IDX_8821C(x, v) \
+ (BIT_CLEAR_LOW_RATE_BD_IDX_8821C(x) | BIT_LOW_RATE_BD_IDX_8821C(v))
/* 2 REG_LTR_CTRL2_TIMER_THRESHOLD_8821C */
#define BIT_SHIFT_RX_EMPTY_TIMER_IDX_8821C 24
#define BIT_MASK_RX_EMPTY_TIMER_IDX_8821C 0x7
-#define BIT_RX_EMPTY_TIMER_IDX_8821C(x) (((x) & BIT_MASK_RX_EMPTY_TIMER_IDX_8821C) << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8821C)
-#define BIT_GET_RX_EMPTY_TIMER_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8821C) & BIT_MASK_RX_EMPTY_TIMER_IDX_8821C)
-
+#define BIT_RX_EMPTY_TIMER_IDX_8821C(x) \
+ (((x) & BIT_MASK_RX_EMPTY_TIMER_IDX_8821C) \
+ << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8821C)
+#define BITS_RX_EMPTY_TIMER_IDX_8821C \
+ (BIT_MASK_RX_EMPTY_TIMER_IDX_8821C \
+ << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8821C)
+#define BIT_CLEAR_RX_EMPTY_TIMER_IDX_8821C(x) \
+ ((x) & (~BITS_RX_EMPTY_TIMER_IDX_8821C))
+#define BIT_GET_RX_EMPTY_TIMER_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8821C) & \
+ BIT_MASK_RX_EMPTY_TIMER_IDX_8821C)
+#define BIT_SET_RX_EMPTY_TIMER_IDX_8821C(x, v) \
+ (BIT_CLEAR_RX_EMPTY_TIMER_IDX_8821C(x) | \
+ BIT_RX_EMPTY_TIMER_IDX_8821C(v))
#define BIT_SHIFT_RX_AFULL_TH_IDX_8821C 20
#define BIT_MASK_RX_AFULL_TH_IDX_8821C 0x7
-#define BIT_RX_AFULL_TH_IDX_8821C(x) (((x) & BIT_MASK_RX_AFULL_TH_IDX_8821C) << BIT_SHIFT_RX_AFULL_TH_IDX_8821C)
-#define BIT_GET_RX_AFULL_TH_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8821C) & BIT_MASK_RX_AFULL_TH_IDX_8821C)
-
+#define BIT_RX_AFULL_TH_IDX_8821C(x) \
+ (((x) & BIT_MASK_RX_AFULL_TH_IDX_8821C) \
+ << BIT_SHIFT_RX_AFULL_TH_IDX_8821C)
+#define BITS_RX_AFULL_TH_IDX_8821C \
+ (BIT_MASK_RX_AFULL_TH_IDX_8821C << BIT_SHIFT_RX_AFULL_TH_IDX_8821C)
+#define BIT_CLEAR_RX_AFULL_TH_IDX_8821C(x) ((x) & (~BITS_RX_AFULL_TH_IDX_8821C))
+#define BIT_GET_RX_AFULL_TH_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8821C) & \
+ BIT_MASK_RX_AFULL_TH_IDX_8821C)
+#define BIT_SET_RX_AFULL_TH_IDX_8821C(x, v) \
+ (BIT_CLEAR_RX_AFULL_TH_IDX_8821C(x) | BIT_RX_AFULL_TH_IDX_8821C(v))
#define BIT_SHIFT_RX_HIGH_TH_IDX_8821C 16
#define BIT_MASK_RX_HIGH_TH_IDX_8821C 0x7
-#define BIT_RX_HIGH_TH_IDX_8821C(x) (((x) & BIT_MASK_RX_HIGH_TH_IDX_8821C) << BIT_SHIFT_RX_HIGH_TH_IDX_8821C)
-#define BIT_GET_RX_HIGH_TH_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8821C) & BIT_MASK_RX_HIGH_TH_IDX_8821C)
-
+#define BIT_RX_HIGH_TH_IDX_8821C(x) \
+ (((x) & BIT_MASK_RX_HIGH_TH_IDX_8821C) \
+ << BIT_SHIFT_RX_HIGH_TH_IDX_8821C)
+#define BITS_RX_HIGH_TH_IDX_8821C \
+ (BIT_MASK_RX_HIGH_TH_IDX_8821C << BIT_SHIFT_RX_HIGH_TH_IDX_8821C)
+#define BIT_CLEAR_RX_HIGH_TH_IDX_8821C(x) ((x) & (~BITS_RX_HIGH_TH_IDX_8821C))
+#define BIT_GET_RX_HIGH_TH_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8821C) & \
+ BIT_MASK_RX_HIGH_TH_IDX_8821C)
+#define BIT_SET_RX_HIGH_TH_IDX_8821C(x, v) \
+ (BIT_CLEAR_RX_HIGH_TH_IDX_8821C(x) | BIT_RX_HIGH_TH_IDX_8821C(v))
#define BIT_SHIFT_RX_MED_TH_IDX_8821C 12
#define BIT_MASK_RX_MED_TH_IDX_8821C 0x7
-#define BIT_RX_MED_TH_IDX_8821C(x) (((x) & BIT_MASK_RX_MED_TH_IDX_8821C) << BIT_SHIFT_RX_MED_TH_IDX_8821C)
-#define BIT_GET_RX_MED_TH_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_MED_TH_IDX_8821C) & BIT_MASK_RX_MED_TH_IDX_8821C)
-
+#define BIT_RX_MED_TH_IDX_8821C(x) \
+ (((x) & BIT_MASK_RX_MED_TH_IDX_8821C) << BIT_SHIFT_RX_MED_TH_IDX_8821C)
+#define BITS_RX_MED_TH_IDX_8821C \
+ (BIT_MASK_RX_MED_TH_IDX_8821C << BIT_SHIFT_RX_MED_TH_IDX_8821C)
+#define BIT_CLEAR_RX_MED_TH_IDX_8821C(x) ((x) & (~BITS_RX_MED_TH_IDX_8821C))
+#define BIT_GET_RX_MED_TH_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_RX_MED_TH_IDX_8821C) & BIT_MASK_RX_MED_TH_IDX_8821C)
+#define BIT_SET_RX_MED_TH_IDX_8821C(x, v) \
+ (BIT_CLEAR_RX_MED_TH_IDX_8821C(x) | BIT_RX_MED_TH_IDX_8821C(v))
#define BIT_SHIFT_RX_LOW_TH_IDX_8821C 8
#define BIT_MASK_RX_LOW_TH_IDX_8821C 0x7
-#define BIT_RX_LOW_TH_IDX_8821C(x) (((x) & BIT_MASK_RX_LOW_TH_IDX_8821C) << BIT_SHIFT_RX_LOW_TH_IDX_8821C)
-#define BIT_GET_RX_LOW_TH_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8821C) & BIT_MASK_RX_LOW_TH_IDX_8821C)
-
+#define BIT_RX_LOW_TH_IDX_8821C(x) \
+ (((x) & BIT_MASK_RX_LOW_TH_IDX_8821C) << BIT_SHIFT_RX_LOW_TH_IDX_8821C)
+#define BITS_RX_LOW_TH_IDX_8821C \
+ (BIT_MASK_RX_LOW_TH_IDX_8821C << BIT_SHIFT_RX_LOW_TH_IDX_8821C)
+#define BIT_CLEAR_RX_LOW_TH_IDX_8821C(x) ((x) & (~BITS_RX_LOW_TH_IDX_8821C))
+#define BIT_GET_RX_LOW_TH_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8821C) & BIT_MASK_RX_LOW_TH_IDX_8821C)
+#define BIT_SET_RX_LOW_TH_IDX_8821C(x, v) \
+ (BIT_CLEAR_RX_LOW_TH_IDX_8821C(x) | BIT_RX_LOW_TH_IDX_8821C(v))
#define BIT_SHIFT_LTR_SPACE_IDX_8821C 4
#define BIT_MASK_LTR_SPACE_IDX_8821C 0x3
-#define BIT_LTR_SPACE_IDX_8821C(x) (((x) & BIT_MASK_LTR_SPACE_IDX_8821C) << BIT_SHIFT_LTR_SPACE_IDX_8821C)
-#define BIT_GET_LTR_SPACE_IDX_8821C(x) (((x) >> BIT_SHIFT_LTR_SPACE_IDX_8821C) & BIT_MASK_LTR_SPACE_IDX_8821C)
-
+#define BIT_LTR_SPACE_IDX_8821C(x) \
+ (((x) & BIT_MASK_LTR_SPACE_IDX_8821C) << BIT_SHIFT_LTR_SPACE_IDX_8821C)
+#define BITS_LTR_SPACE_IDX_8821C \
+ (BIT_MASK_LTR_SPACE_IDX_8821C << BIT_SHIFT_LTR_SPACE_IDX_8821C)
+#define BIT_CLEAR_LTR_SPACE_IDX_8821C(x) ((x) & (~BITS_LTR_SPACE_IDX_8821C))
+#define BIT_GET_LTR_SPACE_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_LTR_SPACE_IDX_8821C) & BIT_MASK_LTR_SPACE_IDX_8821C)
+#define BIT_SET_LTR_SPACE_IDX_8821C(x, v) \
+ (BIT_CLEAR_LTR_SPACE_IDX_8821C(x) | BIT_LTR_SPACE_IDX_8821C(v))
#define BIT_SHIFT_LTR_IDLE_TIMER_IDX_8821C 0
#define BIT_MASK_LTR_IDLE_TIMER_IDX_8821C 0x7
-#define BIT_LTR_IDLE_TIMER_IDX_8821C(x) (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8821C) << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8821C)
-#define BIT_GET_LTR_IDLE_TIMER_IDX_8821C(x) (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8821C) & BIT_MASK_LTR_IDLE_TIMER_IDX_8821C)
-
+#define BIT_LTR_IDLE_TIMER_IDX_8821C(x) \
+ (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8821C) \
+ << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8821C)
+#define BITS_LTR_IDLE_TIMER_IDX_8821C \
+ (BIT_MASK_LTR_IDLE_TIMER_IDX_8821C \
+ << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8821C)
+#define BIT_CLEAR_LTR_IDLE_TIMER_IDX_8821C(x) \
+ ((x) & (~BITS_LTR_IDLE_TIMER_IDX_8821C))
+#define BIT_GET_LTR_IDLE_TIMER_IDX_8821C(x) \
+ (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8821C) & \
+ BIT_MASK_LTR_IDLE_TIMER_IDX_8821C)
+#define BIT_SET_LTR_IDLE_TIMER_IDX_8821C(x, v) \
+ (BIT_CLEAR_LTR_IDLE_TIMER_IDX_8821C(x) | \
+ BIT_LTR_IDLE_TIMER_IDX_8821C(v))
/* 2 REG_LTR_IDLE_LATENCY_V1_8821C */
#define BIT_SHIFT_LTR_IDLE_L_8821C 0
#define BIT_MASK_LTR_IDLE_L_8821C 0xffffffffL
-#define BIT_LTR_IDLE_L_8821C(x) (((x) & BIT_MASK_LTR_IDLE_L_8821C) << BIT_SHIFT_LTR_IDLE_L_8821C)
-#define BIT_GET_LTR_IDLE_L_8821C(x) (((x) >> BIT_SHIFT_LTR_IDLE_L_8821C) & BIT_MASK_LTR_IDLE_L_8821C)
-
+#define BIT_LTR_IDLE_L_8821C(x) \
+ (((x) & BIT_MASK_LTR_IDLE_L_8821C) << BIT_SHIFT_LTR_IDLE_L_8821C)
+#define BITS_LTR_IDLE_L_8821C \
+ (BIT_MASK_LTR_IDLE_L_8821C << BIT_SHIFT_LTR_IDLE_L_8821C)
+#define BIT_CLEAR_LTR_IDLE_L_8821C(x) ((x) & (~BITS_LTR_IDLE_L_8821C))
+#define BIT_GET_LTR_IDLE_L_8821C(x) \
+ (((x) >> BIT_SHIFT_LTR_IDLE_L_8821C) & BIT_MASK_LTR_IDLE_L_8821C)
+#define BIT_SET_LTR_IDLE_L_8821C(x, v) \
+ (BIT_CLEAR_LTR_IDLE_L_8821C(x) | BIT_LTR_IDLE_L_8821C(v))
/* 2 REG_LTR_ACTIVE_LATENCY_V1_8821C */
#define BIT_SHIFT_LTR_ACT_L_8821C 0
#define BIT_MASK_LTR_ACT_L_8821C 0xffffffffL
-#define BIT_LTR_ACT_L_8821C(x) (((x) & BIT_MASK_LTR_ACT_L_8821C) << BIT_SHIFT_LTR_ACT_L_8821C)
-#define BIT_GET_LTR_ACT_L_8821C(x) (((x) >> BIT_SHIFT_LTR_ACT_L_8821C) & BIT_MASK_LTR_ACT_L_8821C)
-
+#define BIT_LTR_ACT_L_8821C(x) \
+ (((x) & BIT_MASK_LTR_ACT_L_8821C) << BIT_SHIFT_LTR_ACT_L_8821C)
+#define BITS_LTR_ACT_L_8821C \
+ (BIT_MASK_LTR_ACT_L_8821C << BIT_SHIFT_LTR_ACT_L_8821C)
+#define BIT_CLEAR_LTR_ACT_L_8821C(x) ((x) & (~BITS_LTR_ACT_L_8821C))
+#define BIT_GET_LTR_ACT_L_8821C(x) \
+ (((x) >> BIT_SHIFT_LTR_ACT_L_8821C) & BIT_MASK_LTR_ACT_L_8821C)
+#define BIT_SET_LTR_ACT_L_8821C(x, v) \
+ (BIT_CLEAR_LTR_ACT_L_8821C(x) | BIT_LTR_ACT_L_8821C(v))
/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_8821C */
-#define BIT_APPEND_MACID_IN_RESP_EN_8821C BIT(50)
-#define BIT_ADDR2_MATCH_EN_8821C BIT(49)
-#define BIT_ANTTRN_EN_8821C BIT(48)
-#define BIT_SHIFT_TRAIN_STA_ADDR_8821C 0
-#define BIT_MASK_TRAIN_STA_ADDR_8821C 0xffffffffffffL
-#define BIT_TRAIN_STA_ADDR_8821C(x) (((x) & BIT_MASK_TRAIN_STA_ADDR_8821C) << BIT_SHIFT_TRAIN_STA_ADDR_8821C)
-#define BIT_GET_TRAIN_STA_ADDR_8821C(x) (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_8821C) & BIT_MASK_TRAIN_STA_ADDR_8821C)
-
-
-/* 2 REG_RSVD_0X7B4_8821C */
+#define BIT_SHIFT_TRAIN_STA_ADDR_0_8821C 0
+#define BIT_MASK_TRAIN_STA_ADDR_0_8821C 0xffffffffL
+#define BIT_TRAIN_STA_ADDR_0_8821C(x) \
+ (((x) & BIT_MASK_TRAIN_STA_ADDR_0_8821C) \
+ << BIT_SHIFT_TRAIN_STA_ADDR_0_8821C)
+#define BITS_TRAIN_STA_ADDR_0_8821C \
+ (BIT_MASK_TRAIN_STA_ADDR_0_8821C << BIT_SHIFT_TRAIN_STA_ADDR_0_8821C)
+#define BIT_CLEAR_TRAIN_STA_ADDR_0_8821C(x) \
+ ((x) & (~BITS_TRAIN_STA_ADDR_0_8821C))
+#define BIT_GET_TRAIN_STA_ADDR_0_8821C(x) \
+ (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_0_8821C) & \
+ BIT_MASK_TRAIN_STA_ADDR_0_8821C)
+#define BIT_SET_TRAIN_STA_ADDR_0_8821C(x, v) \
+ (BIT_CLEAR_TRAIN_STA_ADDR_0_8821C(x) | BIT_TRAIN_STA_ADDR_0_8821C(v))
+
+/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_1_8821C */
+#define BIT_APPEND_MACID_IN_RESP_EN_1_8821C BIT(18)
+#define BIT_ADDR2_MATCH_EN_1_8821C BIT(17)
+#define BIT_ANTTRN_EN_1_8821C BIT(16)
+
+#define BIT_SHIFT_TRAIN_STA_ADDR_1_8821C 0
+#define BIT_MASK_TRAIN_STA_ADDR_1_8821C 0xffff
+#define BIT_TRAIN_STA_ADDR_1_8821C(x) \
+ (((x) & BIT_MASK_TRAIN_STA_ADDR_1_8821C) \
+ << BIT_SHIFT_TRAIN_STA_ADDR_1_8821C)
+#define BITS_TRAIN_STA_ADDR_1_8821C \
+ (BIT_MASK_TRAIN_STA_ADDR_1_8821C << BIT_SHIFT_TRAIN_STA_ADDR_1_8821C)
+#define BIT_CLEAR_TRAIN_STA_ADDR_1_8821C(x) \
+ ((x) & (~BITS_TRAIN_STA_ADDR_1_8821C))
+#define BIT_GET_TRAIN_STA_ADDR_1_8821C(x) \
+ (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_1_8821C) & \
+ BIT_MASK_TRAIN_STA_ADDR_1_8821C)
+#define BIT_SET_TRAIN_STA_ADDR_1_8821C(x, v) \
+ (BIT_CLEAR_TRAIN_STA_ADDR_1_8821C(x) | BIT_TRAIN_STA_ADDR_1_8821C(v))
/* 2 REG_WMAC_PKTCNT_RWD_8821C */
#define BIT_SHIFT_PKTCNT_BSSIDMAP_8821C 4
#define BIT_MASK_PKTCNT_BSSIDMAP_8821C 0xf
-#define BIT_PKTCNT_BSSIDMAP_8821C(x) (((x) & BIT_MASK_PKTCNT_BSSIDMAP_8821C) << BIT_SHIFT_PKTCNT_BSSIDMAP_8821C)
-#define BIT_GET_PKTCNT_BSSIDMAP_8821C(x) (((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP_8821C) & BIT_MASK_PKTCNT_BSSIDMAP_8821C)
+#define BIT_PKTCNT_BSSIDMAP_8821C(x) \
+ (((x) & BIT_MASK_PKTCNT_BSSIDMAP_8821C) \
+ << BIT_SHIFT_PKTCNT_BSSIDMAP_8821C)
+#define BITS_PKTCNT_BSSIDMAP_8821C \
+ (BIT_MASK_PKTCNT_BSSIDMAP_8821C << BIT_SHIFT_PKTCNT_BSSIDMAP_8821C)
+#define BIT_CLEAR_PKTCNT_BSSIDMAP_8821C(x) ((x) & (~BITS_PKTCNT_BSSIDMAP_8821C))
+#define BIT_GET_PKTCNT_BSSIDMAP_8821C(x) \
+ (((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP_8821C) & \
+ BIT_MASK_PKTCNT_BSSIDMAP_8821C)
+#define BIT_SET_PKTCNT_BSSIDMAP_8821C(x, v) \
+ (BIT_CLEAR_PKTCNT_BSSIDMAP_8821C(x) | BIT_PKTCNT_BSSIDMAP_8821C(v))
#define BIT_PKTCNT_CNTRST_8821C BIT(1)
#define BIT_PKTCNT_CNTEN_8821C BIT(0)
@@ -9493,52 +18506,120 @@
#define BIT_SHIFT_WMAC_PKTCNT_CFGAD_8821C 0
#define BIT_MASK_WMAC_PKTCNT_CFGAD_8821C 0xff
-#define BIT_WMAC_PKTCNT_CFGAD_8821C(x) (((x) & BIT_MASK_WMAC_PKTCNT_CFGAD_8821C) << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8821C)
-#define BIT_GET_WMAC_PKTCNT_CFGAD_8821C(x) (((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD_8821C) & BIT_MASK_WMAC_PKTCNT_CFGAD_8821C)
-
+#define BIT_WMAC_PKTCNT_CFGAD_8821C(x) \
+ (((x) & BIT_MASK_WMAC_PKTCNT_CFGAD_8821C) \
+ << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8821C)
+#define BITS_WMAC_PKTCNT_CFGAD_8821C \
+ (BIT_MASK_WMAC_PKTCNT_CFGAD_8821C << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8821C)
+#define BIT_CLEAR_WMAC_PKTCNT_CFGAD_8821C(x) \
+ ((x) & (~BITS_WMAC_PKTCNT_CFGAD_8821C))
+#define BIT_GET_WMAC_PKTCNT_CFGAD_8821C(x) \
+ (((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD_8821C) & \
+ BIT_MASK_WMAC_PKTCNT_CFGAD_8821C)
+#define BIT_SET_WMAC_PKTCNT_CFGAD_8821C(x, v) \
+ (BIT_CLEAR_WMAC_PKTCNT_CFGAD_8821C(x) | BIT_WMAC_PKTCNT_CFGAD_8821C(v))
/* 2 REG_IQ_DUMP_8821C */
-#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8821C (64 & CPU_OPT_WIDTH)
-#define BIT_MASK_R_WMAC_MATCH_REF_MAC_8821C 0xffffffffL
-#define BIT_R_WMAC_MATCH_REF_MAC_8821C(x) (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_8821C) << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8821C)
-#define BIT_GET_R_WMAC_MATCH_REF_MAC_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8821C) & BIT_MASK_R_WMAC_MATCH_REF_MAC_8821C)
-
-
-#define BIT_SHIFT_R_WMAC_MASK_LA_MAC_8821C (32 & CPU_OPT_WIDTH)
-#define BIT_MASK_R_WMAC_MASK_LA_MAC_8821C 0xffffffffL
-#define BIT_R_WMAC_MASK_LA_MAC_8821C(x) (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_8821C) << BIT_SHIFT_R_WMAC_MASK_LA_MAC_8821C)
-#define BIT_GET_R_WMAC_MASK_LA_MAC_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_8821C) & BIT_MASK_R_WMAC_MASK_LA_MAC_8821C)
-
-
-#define BIT_SHIFT_DUMP_OK_ADDR_8821C 15
-#define BIT_MASK_DUMP_OK_ADDR_8821C 0x1ffff
-#define BIT_DUMP_OK_ADDR_8821C(x) (((x) & BIT_MASK_DUMP_OK_ADDR_8821C) << BIT_SHIFT_DUMP_OK_ADDR_8821C)
-#define BIT_GET_DUMP_OK_ADDR_8821C(x) (((x) >> BIT_SHIFT_DUMP_OK_ADDR_8821C) & BIT_MASK_DUMP_OK_ADDR_8821C)
-
+#define BIT_SHIFT_DUMP_OK_ADDR_8821C 16
+#define BIT_MASK_DUMP_OK_ADDR_8821C 0xffff
+#define BIT_DUMP_OK_ADDR_8821C(x) \
+ (((x) & BIT_MASK_DUMP_OK_ADDR_8821C) << BIT_SHIFT_DUMP_OK_ADDR_8821C)
+#define BITS_DUMP_OK_ADDR_8821C \
+ (BIT_MASK_DUMP_OK_ADDR_8821C << BIT_SHIFT_DUMP_OK_ADDR_8821C)
+#define BIT_CLEAR_DUMP_OK_ADDR_8821C(x) ((x) & (~BITS_DUMP_OK_ADDR_8821C))
+#define BIT_GET_DUMP_OK_ADDR_8821C(x) \
+ (((x) >> BIT_SHIFT_DUMP_OK_ADDR_8821C) & BIT_MASK_DUMP_OK_ADDR_8821C)
+#define BIT_SET_DUMP_OK_ADDR_8821C(x, v) \
+ (BIT_CLEAR_DUMP_OK_ADDR_8821C(x) | BIT_DUMP_OK_ADDR_8821C(v))
#define BIT_SHIFT_R_TRIG_TIME_SEL_8821C 8
#define BIT_MASK_R_TRIG_TIME_SEL_8821C 0x7f
-#define BIT_R_TRIG_TIME_SEL_8821C(x) (((x) & BIT_MASK_R_TRIG_TIME_SEL_8821C) << BIT_SHIFT_R_TRIG_TIME_SEL_8821C)
-#define BIT_GET_R_TRIG_TIME_SEL_8821C(x) (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8821C) & BIT_MASK_R_TRIG_TIME_SEL_8821C)
-
+#define BIT_R_TRIG_TIME_SEL_8821C(x) \
+ (((x) & BIT_MASK_R_TRIG_TIME_SEL_8821C) \
+ << BIT_SHIFT_R_TRIG_TIME_SEL_8821C)
+#define BITS_R_TRIG_TIME_SEL_8821C \
+ (BIT_MASK_R_TRIG_TIME_SEL_8821C << BIT_SHIFT_R_TRIG_TIME_SEL_8821C)
+#define BIT_CLEAR_R_TRIG_TIME_SEL_8821C(x) ((x) & (~BITS_R_TRIG_TIME_SEL_8821C))
+#define BIT_GET_R_TRIG_TIME_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8821C) & \
+ BIT_MASK_R_TRIG_TIME_SEL_8821C)
+#define BIT_SET_R_TRIG_TIME_SEL_8821C(x, v) \
+ (BIT_CLEAR_R_TRIG_TIME_SEL_8821C(x) | BIT_R_TRIG_TIME_SEL_8821C(v))
#define BIT_SHIFT_R_MAC_TRIG_SEL_8821C 6
#define BIT_MASK_R_MAC_TRIG_SEL_8821C 0x3
-#define BIT_R_MAC_TRIG_SEL_8821C(x) (((x) & BIT_MASK_R_MAC_TRIG_SEL_8821C) << BIT_SHIFT_R_MAC_TRIG_SEL_8821C)
-#define BIT_GET_R_MAC_TRIG_SEL_8821C(x) (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8821C) & BIT_MASK_R_MAC_TRIG_SEL_8821C)
+#define BIT_R_MAC_TRIG_SEL_8821C(x) \
+ (((x) & BIT_MASK_R_MAC_TRIG_SEL_8821C) \
+ << BIT_SHIFT_R_MAC_TRIG_SEL_8821C)
+#define BITS_R_MAC_TRIG_SEL_8821C \
+ (BIT_MASK_R_MAC_TRIG_SEL_8821C << BIT_SHIFT_R_MAC_TRIG_SEL_8821C)
+#define BIT_CLEAR_R_MAC_TRIG_SEL_8821C(x) ((x) & (~BITS_R_MAC_TRIG_SEL_8821C))
+#define BIT_GET_R_MAC_TRIG_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8821C) & \
+ BIT_MASK_R_MAC_TRIG_SEL_8821C)
+#define BIT_SET_R_MAC_TRIG_SEL_8821C(x, v) \
+ (BIT_CLEAR_R_MAC_TRIG_SEL_8821C(x) | BIT_R_MAC_TRIG_SEL_8821C(v))
#define BIT_MAC_TRIG_REG_8821C BIT(5)
#define BIT_SHIFT_R_LEVEL_PULSE_SEL_8821C 3
#define BIT_MASK_R_LEVEL_PULSE_SEL_8821C 0x3
-#define BIT_R_LEVEL_PULSE_SEL_8821C(x) (((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8821C) << BIT_SHIFT_R_LEVEL_PULSE_SEL_8821C)
-#define BIT_GET_R_LEVEL_PULSE_SEL_8821C(x) (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8821C) & BIT_MASK_R_LEVEL_PULSE_SEL_8821C)
+#define BIT_R_LEVEL_PULSE_SEL_8821C(x) \
+ (((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8821C) \
+ << BIT_SHIFT_R_LEVEL_PULSE_SEL_8821C)
+#define BITS_R_LEVEL_PULSE_SEL_8821C \
+ (BIT_MASK_R_LEVEL_PULSE_SEL_8821C << BIT_SHIFT_R_LEVEL_PULSE_SEL_8821C)
+#define BIT_CLEAR_R_LEVEL_PULSE_SEL_8821C(x) \
+ ((x) & (~BITS_R_LEVEL_PULSE_SEL_8821C))
+#define BIT_GET_R_LEVEL_PULSE_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8821C) & \
+ BIT_MASK_R_LEVEL_PULSE_SEL_8821C)
+#define BIT_SET_R_LEVEL_PULSE_SEL_8821C(x, v) \
+ (BIT_CLEAR_R_LEVEL_PULSE_SEL_8821C(x) | BIT_R_LEVEL_PULSE_SEL_8821C(v))
#define BIT_EN_LA_MAC_8821C BIT(2)
#define BIT_R_EN_IQDUMP_8821C BIT(1)
#define BIT_R_IQDATA_DUMP_8821C BIT(0)
+/* 2 REG_IQ_DUMP_1_8821C */
+
+#define BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8821C 0
+#define BIT_MASK_R_WMAC_MASK_LA_MAC_1_8821C 0xffffffffL
+#define BIT_R_WMAC_MASK_LA_MAC_1_8821C(x) \
+ (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_1_8821C) \
+ << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8821C)
+#define BITS_R_WMAC_MASK_LA_MAC_1_8821C \
+ (BIT_MASK_R_WMAC_MASK_LA_MAC_1_8821C \
+ << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8821C)
+#define BIT_CLEAR_R_WMAC_MASK_LA_MAC_1_8821C(x) \
+ ((x) & (~BITS_R_WMAC_MASK_LA_MAC_1_8821C))
+#define BIT_GET_R_WMAC_MASK_LA_MAC_1_8821C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8821C) & \
+ BIT_MASK_R_WMAC_MASK_LA_MAC_1_8821C)
+#define BIT_SET_R_WMAC_MASK_LA_MAC_1_8821C(x, v) \
+ (BIT_CLEAR_R_WMAC_MASK_LA_MAC_1_8821C(x) | \
+ BIT_R_WMAC_MASK_LA_MAC_1_8821C(v))
+
+/* 2 REG_IQ_DUMP_2_8821C */
+
+#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8821C 0
+#define BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8821C 0xffffffffL
+#define BIT_R_WMAC_MATCH_REF_MAC_2_8821C(x) \
+ (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8821C) \
+ << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8821C)
+#define BITS_R_WMAC_MATCH_REF_MAC_2_8821C \
+ (BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8821C \
+ << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8821C)
+#define BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2_8821C(x) \
+ ((x) & (~BITS_R_WMAC_MATCH_REF_MAC_2_8821C))
+#define BIT_GET_R_WMAC_MATCH_REF_MAC_2_8821C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8821C) & \
+ BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8821C)
+#define BIT_SET_R_WMAC_MATCH_REF_MAC_2_8821C(x, v) \
+ (BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2_8821C(x) | \
+ BIT_R_WMAC_MATCH_REF_MAC_2_8821C(v))
+
/* 2 REG_WMAC_FTM_CTL_8821C */
#define BIT_RXFTM_TXACK_SC_8821C BIT(6)
#define BIT_RXFTM_TXACK_BW_8821C BIT(5)
@@ -9551,53 +18632,92 @@
/* 2 REG_WMAC_OPTION_FUNCTION_8821C */
-#define BIT_SHIFT_R_WMAC_RX_FIL_LEN_8821C (64 & CPU_OPT_WIDTH)
-#define BIT_MASK_R_WMAC_RX_FIL_LEN_8821C 0xffff
-#define BIT_R_WMAC_RX_FIL_LEN_8821C(x) (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_8821C) << BIT_SHIFT_R_WMAC_RX_FIL_LEN_8821C)
-#define BIT_GET_R_WMAC_RX_FIL_LEN_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_8821C) & BIT_MASK_R_WMAC_RX_FIL_LEN_8821C)
-
-
-#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8821C (56 & CPU_OPT_WIDTH)
-#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8821C 0xff
-#define BIT_R_WMAC_RXFIFO_FULL_TH_8821C(x) (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8821C) << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8821C)
-#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8821C) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8821C)
-
-#define BIT_R_WMAC_RX_SYNCFIFO_SYNC_8821C BIT(55)
-#define BIT_R_WMAC_RXRST_DLY_8821C BIT(54)
-#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP_8821C BIT(53)
-#define BIT_R_WMAC_SRCH_TXRPT_UA1_8821C BIT(52)
-#define BIT_R_WMAC_SRCH_TXRPT_TYPE_8821C BIT(51)
-#define BIT_R_WMAC_NDP_RST_8821C BIT(50)
-#define BIT_R_WMAC_POWINT_EN_8821C BIT(49)
-#define BIT_R_WMAC_SRCH_TXRPT_PERPKT_8821C BIT(48)
-#define BIT_R_WMAC_SRCH_TXRPT_MID_8821C BIT(47)
-#define BIT_R_WMAC_PFIN_TOEN_8821C BIT(46)
-#define BIT_R_WMAC_FIL_SECERR_8821C BIT(45)
-#define BIT_R_WMAC_FIL_CTLPKTLEN_8821C BIT(44)
-#define BIT_R_WMAC_FIL_FCTYPE_8821C BIT(43)
-#define BIT_R_WMAC_FIL_FCPROVER_8821C BIT(42)
-#define BIT_R_WMAC_PHYSTS_SNIF_8821C BIT(41)
-#define BIT_R_WMAC_PHYSTS_PLCP_8821C BIT(40)
-#define BIT_R_MAC_TCR_VBONF_RD_8821C BIT(39)
-#define BIT_R_WMAC_TCR_MPAR_NDP_8821C BIT(38)
-#define BIT_R_WMAC_NDP_FILTER_8821C BIT(37)
-#define BIT_R_WMAC_RXLEN_SEL_8821C BIT(36)
-#define BIT_R_WMAC_RXLEN_SEL1_8821C BIT(35)
-#define BIT_R_OFDM_FILTER_8821C BIT(34)
-#define BIT_R_WMAC_CHK_OFDM_LEN_8821C BIT(33)
-#define BIT_R_WMAC_CHK_CCK_LEN_8821C BIT(32)
-
#define BIT_SHIFT_R_OFDM_LEN_8821C 26
#define BIT_MASK_R_OFDM_LEN_8821C 0x3f
-#define BIT_R_OFDM_LEN_8821C(x) (((x) & BIT_MASK_R_OFDM_LEN_8821C) << BIT_SHIFT_R_OFDM_LEN_8821C)
-#define BIT_GET_R_OFDM_LEN_8821C(x) (((x) >> BIT_SHIFT_R_OFDM_LEN_8821C) & BIT_MASK_R_OFDM_LEN_8821C)
-
+#define BIT_R_OFDM_LEN_8821C(x) \
+ (((x) & BIT_MASK_R_OFDM_LEN_8821C) << BIT_SHIFT_R_OFDM_LEN_8821C)
+#define BITS_R_OFDM_LEN_8821C \
+ (BIT_MASK_R_OFDM_LEN_8821C << BIT_SHIFT_R_OFDM_LEN_8821C)
+#define BIT_CLEAR_R_OFDM_LEN_8821C(x) ((x) & (~BITS_R_OFDM_LEN_8821C))
+#define BIT_GET_R_OFDM_LEN_8821C(x) \
+ (((x) >> BIT_SHIFT_R_OFDM_LEN_8821C) & BIT_MASK_R_OFDM_LEN_8821C)
+#define BIT_SET_R_OFDM_LEN_8821C(x, v) \
+ (BIT_CLEAR_R_OFDM_LEN_8821C(x) | BIT_R_OFDM_LEN_8821C(v))
#define BIT_SHIFT_R_CCK_LEN_8821C 0
#define BIT_MASK_R_CCK_LEN_8821C 0xffff
-#define BIT_R_CCK_LEN_8821C(x) (((x) & BIT_MASK_R_CCK_LEN_8821C) << BIT_SHIFT_R_CCK_LEN_8821C)
-#define BIT_GET_R_CCK_LEN_8821C(x) (((x) >> BIT_SHIFT_R_CCK_LEN_8821C) & BIT_MASK_R_CCK_LEN_8821C)
-
+#define BIT_R_CCK_LEN_8821C(x) \
+ (((x) & BIT_MASK_R_CCK_LEN_8821C) << BIT_SHIFT_R_CCK_LEN_8821C)
+#define BITS_R_CCK_LEN_8821C \
+ (BIT_MASK_R_CCK_LEN_8821C << BIT_SHIFT_R_CCK_LEN_8821C)
+#define BIT_CLEAR_R_CCK_LEN_8821C(x) ((x) & (~BITS_R_CCK_LEN_8821C))
+#define BIT_GET_R_CCK_LEN_8821C(x) \
+ (((x) >> BIT_SHIFT_R_CCK_LEN_8821C) & BIT_MASK_R_CCK_LEN_8821C)
+#define BIT_SET_R_CCK_LEN_8821C(x, v) \
+ (BIT_CLEAR_R_CCK_LEN_8821C(x) | BIT_R_CCK_LEN_8821C(v))
+
+/* 2 REG_WMAC_OPTION_FUNCTION_1_8821C */
+
+#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8821C 24
+#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8821C 0xff
+#define BIT_R_WMAC_RXFIFO_FULL_TH_1_8821C(x) \
+ (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8821C) \
+ << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8821C)
+#define BITS_R_WMAC_RXFIFO_FULL_TH_1_8821C \
+ (BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8821C \
+ << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8821C)
+#define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1_8821C(x) \
+ ((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH_1_8821C))
+#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_1_8821C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8821C) & \
+ BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8821C)
+#define BIT_SET_R_WMAC_RXFIFO_FULL_TH_1_8821C(x, v) \
+ (BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1_8821C(x) | \
+ BIT_R_WMAC_RXFIFO_FULL_TH_1_8821C(v))
+
+#define BIT_R_WMAC_RX_SYNCFIFO_SYNC_1_8821C BIT(23)
+#define BIT_R_WMAC_RXRST_DLY_1_8821C BIT(22)
+#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP_1_8821C BIT(21)
+#define BIT_R_WMAC_SRCH_TXRPT_UA1_1_8821C BIT(20)
+#define BIT_R_WMAC_SRCH_TXRPT_TYPE_1_8821C BIT(19)
+#define BIT_R_WMAC_NDP_RST_1_8821C BIT(18)
+#define BIT_R_WMAC_POWINT_EN_1_8821C BIT(17)
+#define BIT_R_WMAC_SRCH_TXRPT_PERPKT_1_8821C BIT(16)
+#define BIT_R_WMAC_SRCH_TXRPT_MID_1_8821C BIT(15)
+#define BIT_R_WMAC_PFIN_TOEN_1_8821C BIT(14)
+#define BIT_R_WMAC_FIL_SECERR_1_8821C BIT(13)
+#define BIT_R_WMAC_FIL_CTLPKTLEN_1_8821C BIT(12)
+#define BIT_R_WMAC_FIL_FCTYPE_1_8821C BIT(11)
+#define BIT_R_WMAC_FIL_FCPROVER_1_8821C BIT(10)
+#define BIT_R_WMAC_PHYSTS_SNIF_1_8821C BIT(9)
+#define BIT_R_WMAC_PHYSTS_PLCP_1_8821C BIT(8)
+#define BIT_R_MAC_TCR_VBONF_RD_1_8821C BIT(7)
+#define BIT_R_WMAC_TCR_MPAR_NDP_1_8821C BIT(6)
+#define BIT_R_WMAC_NDP_FILTER_1_8821C BIT(5)
+#define BIT_R_WMAC_RXLEN_SEL_1_8821C BIT(4)
+#define BIT_R_WMAC_RXLEN_SEL1_1_8821C BIT(3)
+#define BIT_R_OFDM_FILTER_1_8821C BIT(2)
+#define BIT_R_WMAC_CHK_OFDM_LEN_1_8821C BIT(1)
+#define BIT_R_WMAC_CHK_CCK_LEN_1_8821C BIT(0)
+
+/* 2 REG_WMAC_OPTION_FUNCTION_2_8821C */
+
+#define BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8821C 0
+#define BIT_MASK_R_WMAC_RX_FIL_LEN_2_8821C 0xffff
+#define BIT_R_WMAC_RX_FIL_LEN_2_8821C(x) \
+ (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_2_8821C) \
+ << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8821C)
+#define BITS_R_WMAC_RX_FIL_LEN_2_8821C \
+ (BIT_MASK_R_WMAC_RX_FIL_LEN_2_8821C \
+ << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8821C)
+#define BIT_CLEAR_R_WMAC_RX_FIL_LEN_2_8821C(x) \
+ ((x) & (~BITS_R_WMAC_RX_FIL_LEN_2_8821C))
+#define BIT_GET_R_WMAC_RX_FIL_LEN_2_8821C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8821C) & \
+ BIT_MASK_R_WMAC_RX_FIL_LEN_2_8821C)
+#define BIT_SET_R_WMAC_RX_FIL_LEN_2_8821C(x, v) \
+ (BIT_CLEAR_R_WMAC_RX_FIL_LEN_2_8821C(x) | \
+ BIT_R_WMAC_RX_FIL_LEN_2_8821C(v))
/* 2 REG_RX_FILTER_FUNCTION_8821C */
#define BIT_R_WMAC_MHRDDY_LATCH_8821C BIT(14)
@@ -9616,33 +18736,66 @@
#define BIT_R_WMAC_RXFIL_MESH_DEL_8821C BIT(1)
#define BIT_R_WMAC_RXFIL_MASKM_8821C BIT(0)
+/* 2 REG_NOT_VALID_8821C */
+
/* 2 REG_NDP_SIG_8821C */
#define BIT_SHIFT_R_WMAC_TXNDP_SIGB_8821C 0
#define BIT_MASK_R_WMAC_TXNDP_SIGB_8821C 0x1fffff
-#define BIT_R_WMAC_TXNDP_SIGB_8821C(x) (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB_8821C) << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8821C)
-#define BIT_GET_R_WMAC_TXNDP_SIGB_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8821C) & BIT_MASK_R_WMAC_TXNDP_SIGB_8821C)
-
+#define BIT_R_WMAC_TXNDP_SIGB_8821C(x) \
+ (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB_8821C) \
+ << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8821C)
+#define BITS_R_WMAC_TXNDP_SIGB_8821C \
+ (BIT_MASK_R_WMAC_TXNDP_SIGB_8821C << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8821C)
+#define BIT_CLEAR_R_WMAC_TXNDP_SIGB_8821C(x) \
+ ((x) & (~BITS_R_WMAC_TXNDP_SIGB_8821C))
+#define BIT_GET_R_WMAC_TXNDP_SIGB_8821C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8821C) & \
+ BIT_MASK_R_WMAC_TXNDP_SIGB_8821C)
+#define BIT_SET_R_WMAC_TXNDP_SIGB_8821C(x, v) \
+ (BIT_CLEAR_R_WMAC_TXNDP_SIGB_8821C(x) | BIT_R_WMAC_TXNDP_SIGB_8821C(v))
/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_8821C */
-#define BIT_SHIFT_R_MAC_DEBUG_8821C (32 & CPU_OPT_WIDTH)
-#define BIT_MASK_R_MAC_DEBUG_8821C 0xffffffffL
-#define BIT_R_MAC_DEBUG_8821C(x) (((x) & BIT_MASK_R_MAC_DEBUG_8821C) << BIT_SHIFT_R_MAC_DEBUG_8821C)
-#define BIT_GET_R_MAC_DEBUG_8821C(x) (((x) >> BIT_SHIFT_R_MAC_DEBUG_8821C) & BIT_MASK_R_MAC_DEBUG_8821C)
-
-
#define BIT_SHIFT_R_MAC_DBG_SHIFT_8821C 8
#define BIT_MASK_R_MAC_DBG_SHIFT_8821C 0x7
-#define BIT_R_MAC_DBG_SHIFT_8821C(x) (((x) & BIT_MASK_R_MAC_DBG_SHIFT_8821C) << BIT_SHIFT_R_MAC_DBG_SHIFT_8821C)
-#define BIT_GET_R_MAC_DBG_SHIFT_8821C(x) (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8821C) & BIT_MASK_R_MAC_DBG_SHIFT_8821C)
-
+#define BIT_R_MAC_DBG_SHIFT_8821C(x) \
+ (((x) & BIT_MASK_R_MAC_DBG_SHIFT_8821C) \
+ << BIT_SHIFT_R_MAC_DBG_SHIFT_8821C)
+#define BITS_R_MAC_DBG_SHIFT_8821C \
+ (BIT_MASK_R_MAC_DBG_SHIFT_8821C << BIT_SHIFT_R_MAC_DBG_SHIFT_8821C)
+#define BIT_CLEAR_R_MAC_DBG_SHIFT_8821C(x) ((x) & (~BITS_R_MAC_DBG_SHIFT_8821C))
+#define BIT_GET_R_MAC_DBG_SHIFT_8821C(x) \
+ (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8821C) & \
+ BIT_MASK_R_MAC_DBG_SHIFT_8821C)
+#define BIT_SET_R_MAC_DBG_SHIFT_8821C(x, v) \
+ (BIT_CLEAR_R_MAC_DBG_SHIFT_8821C(x) | BIT_R_MAC_DBG_SHIFT_8821C(v))
#define BIT_SHIFT_R_MAC_DBG_SEL_8821C 0
#define BIT_MASK_R_MAC_DBG_SEL_8821C 0x3
-#define BIT_R_MAC_DBG_SEL_8821C(x) (((x) & BIT_MASK_R_MAC_DBG_SEL_8821C) << BIT_SHIFT_R_MAC_DBG_SEL_8821C)
-#define BIT_GET_R_MAC_DBG_SEL_8821C(x) (((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8821C) & BIT_MASK_R_MAC_DBG_SEL_8821C)
-
+#define BIT_R_MAC_DBG_SEL_8821C(x) \
+ (((x) & BIT_MASK_R_MAC_DBG_SEL_8821C) << BIT_SHIFT_R_MAC_DBG_SEL_8821C)
+#define BITS_R_MAC_DBG_SEL_8821C \
+ (BIT_MASK_R_MAC_DBG_SEL_8821C << BIT_SHIFT_R_MAC_DBG_SEL_8821C)
+#define BIT_CLEAR_R_MAC_DBG_SEL_8821C(x) ((x) & (~BITS_R_MAC_DBG_SEL_8821C))
+#define BIT_GET_R_MAC_DBG_SEL_8821C(x) \
+ (((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8821C) & BIT_MASK_R_MAC_DBG_SEL_8821C)
+#define BIT_SET_R_MAC_DBG_SEL_8821C(x, v) \
+ (BIT_CLEAR_R_MAC_DBG_SEL_8821C(x) | BIT_R_MAC_DBG_SEL_8821C(v))
+
+/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_1_8821C */
+
+#define BIT_SHIFT_R_MAC_DEBUG_1_8821C 0
+#define BIT_MASK_R_MAC_DEBUG_1_8821C 0xffffffffL
+#define BIT_R_MAC_DEBUG_1_8821C(x) \
+ (((x) & BIT_MASK_R_MAC_DEBUG_1_8821C) << BIT_SHIFT_R_MAC_DEBUG_1_8821C)
+#define BITS_R_MAC_DEBUG_1_8821C \
+ (BIT_MASK_R_MAC_DEBUG_1_8821C << BIT_SHIFT_R_MAC_DEBUG_1_8821C)
+#define BIT_CLEAR_R_MAC_DEBUG_1_8821C(x) ((x) & (~BITS_R_MAC_DEBUG_1_8821C))
+#define BIT_GET_R_MAC_DEBUG_1_8821C(x) \
+ (((x) >> BIT_SHIFT_R_MAC_DEBUG_1_8821C) & BIT_MASK_R_MAC_DEBUG_1_8821C)
+#define BIT_SET_R_MAC_DEBUG_1_8821C(x, v) \
+ (BIT_CLEAR_R_MAC_DEBUG_1_8821C(x) | BIT_R_MAC_DEBUG_1_8821C(v))
/* 2 REG_WSEC_OPTION_8821C */
#define BIT_RXDEC_BM_MGNT_8821C BIT(22)
@@ -9652,8 +18805,12 @@
/* 2 REG_RTS_ADDRESS_0_8821C */
+/* 2 REG_RTS_ADDRESS_0_1_8821C */
+
/* 2 REG_RTS_ADDRESS_1_8821C */
+/* 2 REG_RTS_ADDRESS_1_1_8821C */
+
/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8821C */
#define BIT_LTECOEX_ACCESS_START_V1_8821C BIT(31)
#define BIT_LTECOEX_WRITE_MODE_V1_8821C BIT(30)
@@ -9661,31 +18818,189 @@
#define BIT_SHIFT_WRITE_BYTE_EN_V1_8821C 16
#define BIT_MASK_WRITE_BYTE_EN_V1_8821C 0xf
-#define BIT_WRITE_BYTE_EN_V1_8821C(x) (((x) & BIT_MASK_WRITE_BYTE_EN_V1_8821C) << BIT_SHIFT_WRITE_BYTE_EN_V1_8821C)
-#define BIT_GET_WRITE_BYTE_EN_V1_8821C(x) (((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1_8821C) & BIT_MASK_WRITE_BYTE_EN_V1_8821C)
-
+#define BIT_WRITE_BYTE_EN_V1_8821C(x) \
+ (((x) & BIT_MASK_WRITE_BYTE_EN_V1_8821C) \
+ << BIT_SHIFT_WRITE_BYTE_EN_V1_8821C)
+#define BITS_WRITE_BYTE_EN_V1_8821C \
+ (BIT_MASK_WRITE_BYTE_EN_V1_8821C << BIT_SHIFT_WRITE_BYTE_EN_V1_8821C)
+#define BIT_CLEAR_WRITE_BYTE_EN_V1_8821C(x) \
+ ((x) & (~BITS_WRITE_BYTE_EN_V1_8821C))
+#define BIT_GET_WRITE_BYTE_EN_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1_8821C) & \
+ BIT_MASK_WRITE_BYTE_EN_V1_8821C)
+#define BIT_SET_WRITE_BYTE_EN_V1_8821C(x, v) \
+ (BIT_CLEAR_WRITE_BYTE_EN_V1_8821C(x) | BIT_WRITE_BYTE_EN_V1_8821C(v))
#define BIT_SHIFT_LTECOEX_REG_ADDR_V1_8821C 0
#define BIT_MASK_LTECOEX_REG_ADDR_V1_8821C 0xffff
-#define BIT_LTECOEX_REG_ADDR_V1_8821C(x) (((x) & BIT_MASK_LTECOEX_REG_ADDR_V1_8821C) << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8821C)
-#define BIT_GET_LTECOEX_REG_ADDR_V1_8821C(x) (((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1_8821C) & BIT_MASK_LTECOEX_REG_ADDR_V1_8821C)
-
+#define BIT_LTECOEX_REG_ADDR_V1_8821C(x) \
+ (((x) & BIT_MASK_LTECOEX_REG_ADDR_V1_8821C) \
+ << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8821C)
+#define BITS_LTECOEX_REG_ADDR_V1_8821C \
+ (BIT_MASK_LTECOEX_REG_ADDR_V1_8821C \
+ << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8821C)
+#define BIT_CLEAR_LTECOEX_REG_ADDR_V1_8821C(x) \
+ ((x) & (~BITS_LTECOEX_REG_ADDR_V1_8821C))
+#define BIT_GET_LTECOEX_REG_ADDR_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1_8821C) & \
+ BIT_MASK_LTECOEX_REG_ADDR_V1_8821C)
+#define BIT_SET_LTECOEX_REG_ADDR_V1_8821C(x, v) \
+ (BIT_CLEAR_LTECOEX_REG_ADDR_V1_8821C(x) | \
+ BIT_LTECOEX_REG_ADDR_V1_8821C(v))
/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8821C */
#define BIT_SHIFT_LTECOEX_W_DATA_V1_8821C 0
#define BIT_MASK_LTECOEX_W_DATA_V1_8821C 0xffffffffL
-#define BIT_LTECOEX_W_DATA_V1_8821C(x) (((x) & BIT_MASK_LTECOEX_W_DATA_V1_8821C) << BIT_SHIFT_LTECOEX_W_DATA_V1_8821C)
-#define BIT_GET_LTECOEX_W_DATA_V1_8821C(x) (((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1_8821C) & BIT_MASK_LTECOEX_W_DATA_V1_8821C)
-
+#define BIT_LTECOEX_W_DATA_V1_8821C(x) \
+ (((x) & BIT_MASK_LTECOEX_W_DATA_V1_8821C) \
+ << BIT_SHIFT_LTECOEX_W_DATA_V1_8821C)
+#define BITS_LTECOEX_W_DATA_V1_8821C \
+ (BIT_MASK_LTECOEX_W_DATA_V1_8821C << BIT_SHIFT_LTECOEX_W_DATA_V1_8821C)
+#define BIT_CLEAR_LTECOEX_W_DATA_V1_8821C(x) \
+ ((x) & (~BITS_LTECOEX_W_DATA_V1_8821C))
+#define BIT_GET_LTECOEX_W_DATA_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1_8821C) & \
+ BIT_MASK_LTECOEX_W_DATA_V1_8821C)
+#define BIT_SET_LTECOEX_W_DATA_V1_8821C(x, v) \
+ (BIT_CLEAR_LTECOEX_W_DATA_V1_8821C(x) | BIT_LTECOEX_W_DATA_V1_8821C(v))
/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8821C */
#define BIT_SHIFT_LTECOEX_R_DATA_V1_8821C 0
#define BIT_MASK_LTECOEX_R_DATA_V1_8821C 0xffffffffL
-#define BIT_LTECOEX_R_DATA_V1_8821C(x) (((x) & BIT_MASK_LTECOEX_R_DATA_V1_8821C) << BIT_SHIFT_LTECOEX_R_DATA_V1_8821C)
-#define BIT_GET_LTECOEX_R_DATA_V1_8821C(x) (((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1_8821C) & BIT_MASK_LTECOEX_R_DATA_V1_8821C)
+#define BIT_LTECOEX_R_DATA_V1_8821C(x) \
+ (((x) & BIT_MASK_LTECOEX_R_DATA_V1_8821C) \
+ << BIT_SHIFT_LTECOEX_R_DATA_V1_8821C)
+#define BITS_LTECOEX_R_DATA_V1_8821C \
+ (BIT_MASK_LTECOEX_R_DATA_V1_8821C << BIT_SHIFT_LTECOEX_R_DATA_V1_8821C)
+#define BIT_CLEAR_LTECOEX_R_DATA_V1_8821C(x) \
+ ((x) & (~BITS_LTECOEX_R_DATA_V1_8821C))
+#define BIT_GET_LTECOEX_R_DATA_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1_8821C) & \
+ BIT_MASK_LTECOEX_R_DATA_V1_8821C)
+#define BIT_SET_LTECOEX_R_DATA_V1_8821C(x, v) \
+ (BIT_CLEAR_LTECOEX_R_DATA_V1_8821C(x) | BIT_LTECOEX_R_DATA_V1_8821C(v))
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+
+/* 2 REG_NOT_VALID_8821C */
+/* 2 REG_NOT_VALID_8821C */
/* 2 REG_NOT_VALID_8821C */
@@ -9693,15 +19008,26 @@
#define BIT_SHIFT_SDIO_INT_TIMEOUT_8821C 16
#define BIT_MASK_SDIO_INT_TIMEOUT_8821C 0xffff
-#define BIT_SDIO_INT_TIMEOUT_8821C(x) (((x) & BIT_MASK_SDIO_INT_TIMEOUT_8821C) << BIT_SHIFT_SDIO_INT_TIMEOUT_8821C)
-#define BIT_GET_SDIO_INT_TIMEOUT_8821C(x) (((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT_8821C) & BIT_MASK_SDIO_INT_TIMEOUT_8821C)
+#define BIT_SDIO_INT_TIMEOUT_8821C(x) \
+ (((x) & BIT_MASK_SDIO_INT_TIMEOUT_8821C) \
+ << BIT_SHIFT_SDIO_INT_TIMEOUT_8821C)
+#define BITS_SDIO_INT_TIMEOUT_8821C \
+ (BIT_MASK_SDIO_INT_TIMEOUT_8821C << BIT_SHIFT_SDIO_INT_TIMEOUT_8821C)
+#define BIT_CLEAR_SDIO_INT_TIMEOUT_8821C(x) \
+ ((x) & (~BITS_SDIO_INT_TIMEOUT_8821C))
+#define BIT_GET_SDIO_INT_TIMEOUT_8821C(x) \
+ (((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT_8821C) & \
+ BIT_MASK_SDIO_INT_TIMEOUT_8821C)
+#define BIT_SET_SDIO_INT_TIMEOUT_8821C(x, v) \
+ (BIT_CLEAR_SDIO_INT_TIMEOUT_8821C(x) | BIT_SDIO_INT_TIMEOUT_8821C(v))
#define BIT_IO_ERR_STATUS_8821C BIT(15)
#define BIT_REPLY_ERRCRC_IN_DATA_8821C BIT(9)
#define BIT_EN_CMD53_OVERLAP_8821C BIT(8)
#define BIT_REPLY_ERR_IN_R5_8821C BIT(7)
#define BIT_R18A_EN_8821C BIT(6)
-#define BIT_INIT_CMD_EN_8821C BIT(5)
+#define BIT_SDIO_CMD_FORCE_VLD_8821C BIT(5)
+#define BIT_INIT_CMD_EN_8821C BIT(4)
#define BIT_EN_RXDMA_MASK_INT_8821C BIT(2)
#define BIT_EN_MASK_TIMER_8821C BIT(1)
#define BIT_CMD_ERR_STOP_INT_EN_8821C BIT(0)
@@ -9762,86 +19088,155 @@
#define BIT_SHIFT_RX_REQ_LEN_V1_8821C 0
#define BIT_MASK_RX_REQ_LEN_V1_8821C 0x3ffff
-#define BIT_RX_REQ_LEN_V1_8821C(x) (((x) & BIT_MASK_RX_REQ_LEN_V1_8821C) << BIT_SHIFT_RX_REQ_LEN_V1_8821C)
-#define BIT_GET_RX_REQ_LEN_V1_8821C(x) (((x) >> BIT_SHIFT_RX_REQ_LEN_V1_8821C) & BIT_MASK_RX_REQ_LEN_V1_8821C)
-
+#define BIT_RX_REQ_LEN_V1_8821C(x) \
+ (((x) & BIT_MASK_RX_REQ_LEN_V1_8821C) << BIT_SHIFT_RX_REQ_LEN_V1_8821C)
+#define BITS_RX_REQ_LEN_V1_8821C \
+ (BIT_MASK_RX_REQ_LEN_V1_8821C << BIT_SHIFT_RX_REQ_LEN_V1_8821C)
+#define BIT_CLEAR_RX_REQ_LEN_V1_8821C(x) ((x) & (~BITS_RX_REQ_LEN_V1_8821C))
+#define BIT_GET_RX_REQ_LEN_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_RX_REQ_LEN_V1_8821C) & BIT_MASK_RX_REQ_LEN_V1_8821C)
+#define BIT_SET_RX_REQ_LEN_V1_8821C(x, v) \
+ (BIT_CLEAR_RX_REQ_LEN_V1_8821C(x) | BIT_RX_REQ_LEN_V1_8821C(v))
/* 2 REG_SDIO_FREE_TXPG_SEQ_V1_8821C */
#define BIT_SHIFT_FREE_TXPG_SEQ_8821C 0
#define BIT_MASK_FREE_TXPG_SEQ_8821C 0xff
-#define BIT_FREE_TXPG_SEQ_8821C(x) (((x) & BIT_MASK_FREE_TXPG_SEQ_8821C) << BIT_SHIFT_FREE_TXPG_SEQ_8821C)
-#define BIT_GET_FREE_TXPG_SEQ_8821C(x) (((x) >> BIT_SHIFT_FREE_TXPG_SEQ_8821C) & BIT_MASK_FREE_TXPG_SEQ_8821C)
-
+#define BIT_FREE_TXPG_SEQ_8821C(x) \
+ (((x) & BIT_MASK_FREE_TXPG_SEQ_8821C) << BIT_SHIFT_FREE_TXPG_SEQ_8821C)
+#define BITS_FREE_TXPG_SEQ_8821C \
+ (BIT_MASK_FREE_TXPG_SEQ_8821C << BIT_SHIFT_FREE_TXPG_SEQ_8821C)
+#define BIT_CLEAR_FREE_TXPG_SEQ_8821C(x) ((x) & (~BITS_FREE_TXPG_SEQ_8821C))
+#define BIT_GET_FREE_TXPG_SEQ_8821C(x) \
+ (((x) >> BIT_SHIFT_FREE_TXPG_SEQ_8821C) & BIT_MASK_FREE_TXPG_SEQ_8821C)
+#define BIT_SET_FREE_TXPG_SEQ_8821C(x, v) \
+ (BIT_CLEAR_FREE_TXPG_SEQ_8821C(x) | BIT_FREE_TXPG_SEQ_8821C(v))
/* 2 REG_SDIO_FREE_TXPG_8821C */
#define BIT_SHIFT_MID_FREEPG_V1_8821C 16
#define BIT_MASK_MID_FREEPG_V1_8821C 0xfff
-#define BIT_MID_FREEPG_V1_8821C(x) (((x) & BIT_MASK_MID_FREEPG_V1_8821C) << BIT_SHIFT_MID_FREEPG_V1_8821C)
-#define BIT_GET_MID_FREEPG_V1_8821C(x) (((x) >> BIT_SHIFT_MID_FREEPG_V1_8821C) & BIT_MASK_MID_FREEPG_V1_8821C)
-
+#define BIT_MID_FREEPG_V1_8821C(x) \
+ (((x) & BIT_MASK_MID_FREEPG_V1_8821C) << BIT_SHIFT_MID_FREEPG_V1_8821C)
+#define BITS_MID_FREEPG_V1_8821C \
+ (BIT_MASK_MID_FREEPG_V1_8821C << BIT_SHIFT_MID_FREEPG_V1_8821C)
+#define BIT_CLEAR_MID_FREEPG_V1_8821C(x) ((x) & (~BITS_MID_FREEPG_V1_8821C))
+#define BIT_GET_MID_FREEPG_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_MID_FREEPG_V1_8821C) & BIT_MASK_MID_FREEPG_V1_8821C)
+#define BIT_SET_MID_FREEPG_V1_8821C(x, v) \
+ (BIT_CLEAR_MID_FREEPG_V1_8821C(x) | BIT_MID_FREEPG_V1_8821C(v))
#define BIT_SHIFT_HIQ_FREEPG_V1_8821C 0
#define BIT_MASK_HIQ_FREEPG_V1_8821C 0xfff
-#define BIT_HIQ_FREEPG_V1_8821C(x) (((x) & BIT_MASK_HIQ_FREEPG_V1_8821C) << BIT_SHIFT_HIQ_FREEPG_V1_8821C)
-#define BIT_GET_HIQ_FREEPG_V1_8821C(x) (((x) >> BIT_SHIFT_HIQ_FREEPG_V1_8821C) & BIT_MASK_HIQ_FREEPG_V1_8821C)
-
+#define BIT_HIQ_FREEPG_V1_8821C(x) \
+ (((x) & BIT_MASK_HIQ_FREEPG_V1_8821C) << BIT_SHIFT_HIQ_FREEPG_V1_8821C)
+#define BITS_HIQ_FREEPG_V1_8821C \
+ (BIT_MASK_HIQ_FREEPG_V1_8821C << BIT_SHIFT_HIQ_FREEPG_V1_8821C)
+#define BIT_CLEAR_HIQ_FREEPG_V1_8821C(x) ((x) & (~BITS_HIQ_FREEPG_V1_8821C))
+#define BIT_GET_HIQ_FREEPG_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_HIQ_FREEPG_V1_8821C) & BIT_MASK_HIQ_FREEPG_V1_8821C)
+#define BIT_SET_HIQ_FREEPG_V1_8821C(x, v) \
+ (BIT_CLEAR_HIQ_FREEPG_V1_8821C(x) | BIT_HIQ_FREEPG_V1_8821C(v))
/* 2 REG_SDIO_FREE_TXPG2_8821C */
#define BIT_SHIFT_PUB_FREEPG_V1_8821C 16
#define BIT_MASK_PUB_FREEPG_V1_8821C 0xfff
-#define BIT_PUB_FREEPG_V1_8821C(x) (((x) & BIT_MASK_PUB_FREEPG_V1_8821C) << BIT_SHIFT_PUB_FREEPG_V1_8821C)
-#define BIT_GET_PUB_FREEPG_V1_8821C(x) (((x) >> BIT_SHIFT_PUB_FREEPG_V1_8821C) & BIT_MASK_PUB_FREEPG_V1_8821C)
-
+#define BIT_PUB_FREEPG_V1_8821C(x) \
+ (((x) & BIT_MASK_PUB_FREEPG_V1_8821C) << BIT_SHIFT_PUB_FREEPG_V1_8821C)
+#define BITS_PUB_FREEPG_V1_8821C \
+ (BIT_MASK_PUB_FREEPG_V1_8821C << BIT_SHIFT_PUB_FREEPG_V1_8821C)
+#define BIT_CLEAR_PUB_FREEPG_V1_8821C(x) ((x) & (~BITS_PUB_FREEPG_V1_8821C))
+#define BIT_GET_PUB_FREEPG_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_PUB_FREEPG_V1_8821C) & BIT_MASK_PUB_FREEPG_V1_8821C)
+#define BIT_SET_PUB_FREEPG_V1_8821C(x, v) \
+ (BIT_CLEAR_PUB_FREEPG_V1_8821C(x) | BIT_PUB_FREEPG_V1_8821C(v))
#define BIT_SHIFT_LOW_FREEPG_V1_8821C 0
#define BIT_MASK_LOW_FREEPG_V1_8821C 0xfff
-#define BIT_LOW_FREEPG_V1_8821C(x) (((x) & BIT_MASK_LOW_FREEPG_V1_8821C) << BIT_SHIFT_LOW_FREEPG_V1_8821C)
-#define BIT_GET_LOW_FREEPG_V1_8821C(x) (((x) >> BIT_SHIFT_LOW_FREEPG_V1_8821C) & BIT_MASK_LOW_FREEPG_V1_8821C)
-
+#define BIT_LOW_FREEPG_V1_8821C(x) \
+ (((x) & BIT_MASK_LOW_FREEPG_V1_8821C) << BIT_SHIFT_LOW_FREEPG_V1_8821C)
+#define BITS_LOW_FREEPG_V1_8821C \
+ (BIT_MASK_LOW_FREEPG_V1_8821C << BIT_SHIFT_LOW_FREEPG_V1_8821C)
+#define BIT_CLEAR_LOW_FREEPG_V1_8821C(x) ((x) & (~BITS_LOW_FREEPG_V1_8821C))
+#define BIT_GET_LOW_FREEPG_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_LOW_FREEPG_V1_8821C) & BIT_MASK_LOW_FREEPG_V1_8821C)
+#define BIT_SET_LOW_FREEPG_V1_8821C(x, v) \
+ (BIT_CLEAR_LOW_FREEPG_V1_8821C(x) | BIT_LOW_FREEPG_V1_8821C(v))
/* 2 REG_SDIO_OQT_FREE_TXPG_V1_8821C */
#define BIT_SHIFT_NOAC_OQT_FREEPG_V1_8821C 24
#define BIT_MASK_NOAC_OQT_FREEPG_V1_8821C 0xff
-#define BIT_NOAC_OQT_FREEPG_V1_8821C(x) (((x) & BIT_MASK_NOAC_OQT_FREEPG_V1_8821C) << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8821C)
-#define BIT_GET_NOAC_OQT_FREEPG_V1_8821C(x) (((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1_8821C) & BIT_MASK_NOAC_OQT_FREEPG_V1_8821C)
-
+#define BIT_NOAC_OQT_FREEPG_V1_8821C(x) \
+ (((x) & BIT_MASK_NOAC_OQT_FREEPG_V1_8821C) \
+ << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8821C)
+#define BITS_NOAC_OQT_FREEPG_V1_8821C \
+ (BIT_MASK_NOAC_OQT_FREEPG_V1_8821C \
+ << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8821C)
+#define BIT_CLEAR_NOAC_OQT_FREEPG_V1_8821C(x) \
+ ((x) & (~BITS_NOAC_OQT_FREEPG_V1_8821C))
+#define BIT_GET_NOAC_OQT_FREEPG_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1_8821C) & \
+ BIT_MASK_NOAC_OQT_FREEPG_V1_8821C)
+#define BIT_SET_NOAC_OQT_FREEPG_V1_8821C(x, v) \
+ (BIT_CLEAR_NOAC_OQT_FREEPG_V1_8821C(x) | \
+ BIT_NOAC_OQT_FREEPG_V1_8821C(v))
#define BIT_SHIFT_AC_OQT_FREEPG_V1_8821C 16
#define BIT_MASK_AC_OQT_FREEPG_V1_8821C 0xff
-#define BIT_AC_OQT_FREEPG_V1_8821C(x) (((x) & BIT_MASK_AC_OQT_FREEPG_V1_8821C) << BIT_SHIFT_AC_OQT_FREEPG_V1_8821C)
-#define BIT_GET_AC_OQT_FREEPG_V1_8821C(x) (((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1_8821C) & BIT_MASK_AC_OQT_FREEPG_V1_8821C)
-
+#define BIT_AC_OQT_FREEPG_V1_8821C(x) \
+ (((x) & BIT_MASK_AC_OQT_FREEPG_V1_8821C) \
+ << BIT_SHIFT_AC_OQT_FREEPG_V1_8821C)
+#define BITS_AC_OQT_FREEPG_V1_8821C \
+ (BIT_MASK_AC_OQT_FREEPG_V1_8821C << BIT_SHIFT_AC_OQT_FREEPG_V1_8821C)
+#define BIT_CLEAR_AC_OQT_FREEPG_V1_8821C(x) \
+ ((x) & (~BITS_AC_OQT_FREEPG_V1_8821C))
+#define BIT_GET_AC_OQT_FREEPG_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1_8821C) & \
+ BIT_MASK_AC_OQT_FREEPG_V1_8821C)
+#define BIT_SET_AC_OQT_FREEPG_V1_8821C(x, v) \
+ (BIT_CLEAR_AC_OQT_FREEPG_V1_8821C(x) | BIT_AC_OQT_FREEPG_V1_8821C(v))
#define BIT_SHIFT_EXQ_FREEPG_V1_8821C 0
#define BIT_MASK_EXQ_FREEPG_V1_8821C 0xfff
-#define BIT_EXQ_FREEPG_V1_8821C(x) (((x) & BIT_MASK_EXQ_FREEPG_V1_8821C) << BIT_SHIFT_EXQ_FREEPG_V1_8821C)
-#define BIT_GET_EXQ_FREEPG_V1_8821C(x) (((x) >> BIT_SHIFT_EXQ_FREEPG_V1_8821C) & BIT_MASK_EXQ_FREEPG_V1_8821C)
-
+#define BIT_EXQ_FREEPG_V1_8821C(x) \
+ (((x) & BIT_MASK_EXQ_FREEPG_V1_8821C) << BIT_SHIFT_EXQ_FREEPG_V1_8821C)
+#define BITS_EXQ_FREEPG_V1_8821C \
+ (BIT_MASK_EXQ_FREEPG_V1_8821C << BIT_SHIFT_EXQ_FREEPG_V1_8821C)
+#define BIT_CLEAR_EXQ_FREEPG_V1_8821C(x) ((x) & (~BITS_EXQ_FREEPG_V1_8821C))
+#define BIT_GET_EXQ_FREEPG_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_EXQ_FREEPG_V1_8821C) & BIT_MASK_EXQ_FREEPG_V1_8821C)
+#define BIT_SET_EXQ_FREEPG_V1_8821C(x, v) \
+ (BIT_CLEAR_EXQ_FREEPG_V1_8821C(x) | BIT_EXQ_FREEPG_V1_8821C(v))
/* 2 REG_SDIO_HTSFR_INFO_8821C */
#define BIT_SHIFT_HTSFR1_8821C 16
#define BIT_MASK_HTSFR1_8821C 0xffff
-#define BIT_HTSFR1_8821C(x) (((x) & BIT_MASK_HTSFR1_8821C) << BIT_SHIFT_HTSFR1_8821C)
-#define BIT_GET_HTSFR1_8821C(x) (((x) >> BIT_SHIFT_HTSFR1_8821C) & BIT_MASK_HTSFR1_8821C)
-
+#define BIT_HTSFR1_8821C(x) \
+ (((x) & BIT_MASK_HTSFR1_8821C) << BIT_SHIFT_HTSFR1_8821C)
+#define BITS_HTSFR1_8821C (BIT_MASK_HTSFR1_8821C << BIT_SHIFT_HTSFR1_8821C)
+#define BIT_CLEAR_HTSFR1_8821C(x) ((x) & (~BITS_HTSFR1_8821C))
+#define BIT_GET_HTSFR1_8821C(x) \
+ (((x) >> BIT_SHIFT_HTSFR1_8821C) & BIT_MASK_HTSFR1_8821C)
+#define BIT_SET_HTSFR1_8821C(x, v) \
+ (BIT_CLEAR_HTSFR1_8821C(x) | BIT_HTSFR1_8821C(v))
#define BIT_SHIFT_HTSFR0_8821C 0
#define BIT_MASK_HTSFR0_8821C 0xffff
-#define BIT_HTSFR0_8821C(x) (((x) & BIT_MASK_HTSFR0_8821C) << BIT_SHIFT_HTSFR0_8821C)
-#define BIT_GET_HTSFR0_8821C(x) (((x) >> BIT_SHIFT_HTSFR0_8821C) & BIT_MASK_HTSFR0_8821C)
-
+#define BIT_HTSFR0_8821C(x) \
+ (((x) & BIT_MASK_HTSFR0_8821C) << BIT_SHIFT_HTSFR0_8821C)
+#define BITS_HTSFR0_8821C (BIT_MASK_HTSFR0_8821C << BIT_SHIFT_HTSFR0_8821C)
+#define BIT_CLEAR_HTSFR0_8821C(x) ((x) & (~BITS_HTSFR0_8821C))
+#define BIT_GET_HTSFR0_8821C(x) \
+ (((x) >> BIT_SHIFT_HTSFR0_8821C) & BIT_MASK_HTSFR0_8821C)
+#define BIT_SET_HTSFR0_8821C(x, v) \
+ (BIT_CLEAR_HTSFR0_8821C(x) | BIT_HTSFR0_8821C(v))
/* 2 REG_SDIO_HCPWM1_V2_8821C */
-#define BIT_TOGGLING_8821C BIT(7)
-#define BIT_WWLAN_8821C BIT(3)
-#define BIT_RPS_ST_8821C BIT(2)
-#define BIT_WLAN_TRX_8821C BIT(1)
-#define BIT_SYS_CLK_8821C BIT(0)
+#define BIT_TOGGLE_8821C BIT(7)
+#define BIT_CUR_PS_8821C BIT(0)
/* 2 REG_SDIO_HCPWM2_V2_8821C */
@@ -9852,46 +19247,83 @@
#define BIT_SHIFT_INDIRECT_REG_SIZE_8821C 16
#define BIT_MASK_INDIRECT_REG_SIZE_8821C 0x3
-#define BIT_INDIRECT_REG_SIZE_8821C(x) (((x) & BIT_MASK_INDIRECT_REG_SIZE_8821C) << BIT_SHIFT_INDIRECT_REG_SIZE_8821C)
-#define BIT_GET_INDIRECT_REG_SIZE_8821C(x) (((x) >> BIT_SHIFT_INDIRECT_REG_SIZE_8821C) & BIT_MASK_INDIRECT_REG_SIZE_8821C)
-
+#define BIT_INDIRECT_REG_SIZE_8821C(x) \
+ (((x) & BIT_MASK_INDIRECT_REG_SIZE_8821C) \
+ << BIT_SHIFT_INDIRECT_REG_SIZE_8821C)
+#define BITS_INDIRECT_REG_SIZE_8821C \
+ (BIT_MASK_INDIRECT_REG_SIZE_8821C << BIT_SHIFT_INDIRECT_REG_SIZE_8821C)
+#define BIT_CLEAR_INDIRECT_REG_SIZE_8821C(x) \
+ ((x) & (~BITS_INDIRECT_REG_SIZE_8821C))
+#define BIT_GET_INDIRECT_REG_SIZE_8821C(x) \
+ (((x) >> BIT_SHIFT_INDIRECT_REG_SIZE_8821C) & \
+ BIT_MASK_INDIRECT_REG_SIZE_8821C)
+#define BIT_SET_INDIRECT_REG_SIZE_8821C(x, v) \
+ (BIT_CLEAR_INDIRECT_REG_SIZE_8821C(x) | BIT_INDIRECT_REG_SIZE_8821C(v))
#define BIT_SHIFT_INDIRECT_REG_ADDR_8821C 0
#define BIT_MASK_INDIRECT_REG_ADDR_8821C 0xffff
-#define BIT_INDIRECT_REG_ADDR_8821C(x) (((x) & BIT_MASK_INDIRECT_REG_ADDR_8821C) << BIT_SHIFT_INDIRECT_REG_ADDR_8821C)
-#define BIT_GET_INDIRECT_REG_ADDR_8821C(x) (((x) >> BIT_SHIFT_INDIRECT_REG_ADDR_8821C) & BIT_MASK_INDIRECT_REG_ADDR_8821C)
-
+#define BIT_INDIRECT_REG_ADDR_8821C(x) \
+ (((x) & BIT_MASK_INDIRECT_REG_ADDR_8821C) \
+ << BIT_SHIFT_INDIRECT_REG_ADDR_8821C)
+#define BITS_INDIRECT_REG_ADDR_8821C \
+ (BIT_MASK_INDIRECT_REG_ADDR_8821C << BIT_SHIFT_INDIRECT_REG_ADDR_8821C)
+#define BIT_CLEAR_INDIRECT_REG_ADDR_8821C(x) \
+ ((x) & (~BITS_INDIRECT_REG_ADDR_8821C))
+#define BIT_GET_INDIRECT_REG_ADDR_8821C(x) \
+ (((x) >> BIT_SHIFT_INDIRECT_REG_ADDR_8821C) & \
+ BIT_MASK_INDIRECT_REG_ADDR_8821C)
+#define BIT_SET_INDIRECT_REG_ADDR_8821C(x, v) \
+ (BIT_CLEAR_INDIRECT_REG_ADDR_8821C(x) | BIT_INDIRECT_REG_ADDR_8821C(v))
/* 2 REG_SDIO_INDIRECT_REG_DATA_8821C */
#define BIT_SHIFT_INDIRECT_REG_DATA_8821C 0
#define BIT_MASK_INDIRECT_REG_DATA_8821C 0xffffffffL
-#define BIT_INDIRECT_REG_DATA_8821C(x) (((x) & BIT_MASK_INDIRECT_REG_DATA_8821C) << BIT_SHIFT_INDIRECT_REG_DATA_8821C)
-#define BIT_GET_INDIRECT_REG_DATA_8821C(x) (((x) >> BIT_SHIFT_INDIRECT_REG_DATA_8821C) & BIT_MASK_INDIRECT_REG_DATA_8821C)
-
+#define BIT_INDIRECT_REG_DATA_8821C(x) \
+ (((x) & BIT_MASK_INDIRECT_REG_DATA_8821C) \
+ << BIT_SHIFT_INDIRECT_REG_DATA_8821C)
+#define BITS_INDIRECT_REG_DATA_8821C \
+ (BIT_MASK_INDIRECT_REG_DATA_8821C << BIT_SHIFT_INDIRECT_REG_DATA_8821C)
+#define BIT_CLEAR_INDIRECT_REG_DATA_8821C(x) \
+ ((x) & (~BITS_INDIRECT_REG_DATA_8821C))
+#define BIT_GET_INDIRECT_REG_DATA_8821C(x) \
+ (((x) >> BIT_SHIFT_INDIRECT_REG_DATA_8821C) & \
+ BIT_MASK_INDIRECT_REG_DATA_8821C)
+#define BIT_SET_INDIRECT_REG_DATA_8821C(x, v) \
+ (BIT_CLEAR_INDIRECT_REG_DATA_8821C(x) | BIT_INDIRECT_REG_DATA_8821C(v))
/* 2 REG_SDIO_H2C_8821C */
#define BIT_SHIFT_SDIO_H2C_MSG_8821C 0
#define BIT_MASK_SDIO_H2C_MSG_8821C 0xffffffffL
-#define BIT_SDIO_H2C_MSG_8821C(x) (((x) & BIT_MASK_SDIO_H2C_MSG_8821C) << BIT_SHIFT_SDIO_H2C_MSG_8821C)
-#define BIT_GET_SDIO_H2C_MSG_8821C(x) (((x) >> BIT_SHIFT_SDIO_H2C_MSG_8821C) & BIT_MASK_SDIO_H2C_MSG_8821C)
-
+#define BIT_SDIO_H2C_MSG_8821C(x) \
+ (((x) & BIT_MASK_SDIO_H2C_MSG_8821C) << BIT_SHIFT_SDIO_H2C_MSG_8821C)
+#define BITS_SDIO_H2C_MSG_8821C \
+ (BIT_MASK_SDIO_H2C_MSG_8821C << BIT_SHIFT_SDIO_H2C_MSG_8821C)
+#define BIT_CLEAR_SDIO_H2C_MSG_8821C(x) ((x) & (~BITS_SDIO_H2C_MSG_8821C))
+#define BIT_GET_SDIO_H2C_MSG_8821C(x) \
+ (((x) >> BIT_SHIFT_SDIO_H2C_MSG_8821C) & BIT_MASK_SDIO_H2C_MSG_8821C)
+#define BIT_SET_SDIO_H2C_MSG_8821C(x, v) \
+ (BIT_CLEAR_SDIO_H2C_MSG_8821C(x) | BIT_SDIO_H2C_MSG_8821C(v))
/* 2 REG_SDIO_C2H_8821C */
#define BIT_SHIFT_SDIO_C2H_MSG_8821C 0
#define BIT_MASK_SDIO_C2H_MSG_8821C 0xffffffffL
-#define BIT_SDIO_C2H_MSG_8821C(x) (((x) & BIT_MASK_SDIO_C2H_MSG_8821C) << BIT_SHIFT_SDIO_C2H_MSG_8821C)
-#define BIT_GET_SDIO_C2H_MSG_8821C(x) (((x) >> BIT_SHIFT_SDIO_C2H_MSG_8821C) & BIT_MASK_SDIO_C2H_MSG_8821C)
-
+#define BIT_SDIO_C2H_MSG_8821C(x) \
+ (((x) & BIT_MASK_SDIO_C2H_MSG_8821C) << BIT_SHIFT_SDIO_C2H_MSG_8821C)
+#define BITS_SDIO_C2H_MSG_8821C \
+ (BIT_MASK_SDIO_C2H_MSG_8821C << BIT_SHIFT_SDIO_C2H_MSG_8821C)
+#define BIT_CLEAR_SDIO_C2H_MSG_8821C(x) ((x) & (~BITS_SDIO_C2H_MSG_8821C))
+#define BIT_GET_SDIO_C2H_MSG_8821C(x) \
+ (((x) >> BIT_SHIFT_SDIO_C2H_MSG_8821C) & BIT_MASK_SDIO_C2H_MSG_8821C)
+#define BIT_SET_SDIO_C2H_MSG_8821C(x, v) \
+ (BIT_CLEAR_SDIO_C2H_MSG_8821C(x) | BIT_SDIO_C2H_MSG_8821C(v))
/* 2 REG_SDIO_HRPWM1_8821C */
-#define BIT_TOGGLING_8821C BIT(7)
-#define BIT_WWLAN_8821C BIT(3)
-#define BIT_RPS_ST_8821C BIT(2)
-#define BIT_WLAN_TRX_8821C BIT(1)
-#define BIT_SYS_CLK_8821C BIT(0)
+#define BIT_TOGGLE_8821C BIT(7)
+#define BIT_ACK_8821C BIT(6)
+#define BIT_REQ_PS_8821C BIT(0)
/* 2 REG_SDIO_HRPWM2_8821C */
@@ -9914,31 +19346,45 @@
#define BIT_SHIFT_CMDIN_2RESP_TIMER_8821C 0
#define BIT_MASK_CMDIN_2RESP_TIMER_8821C 0xffff
-#define BIT_CMDIN_2RESP_TIMER_8821C(x) (((x) & BIT_MASK_CMDIN_2RESP_TIMER_8821C) << BIT_SHIFT_CMDIN_2RESP_TIMER_8821C)
-#define BIT_GET_CMDIN_2RESP_TIMER_8821C(x) (((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER_8821C) & BIT_MASK_CMDIN_2RESP_TIMER_8821C)
-
+#define BIT_CMDIN_2RESP_TIMER_8821C(x) \
+ (((x) & BIT_MASK_CMDIN_2RESP_TIMER_8821C) \
+ << BIT_SHIFT_CMDIN_2RESP_TIMER_8821C)
+#define BITS_CMDIN_2RESP_TIMER_8821C \
+ (BIT_MASK_CMDIN_2RESP_TIMER_8821C << BIT_SHIFT_CMDIN_2RESP_TIMER_8821C)
+#define BIT_CLEAR_CMDIN_2RESP_TIMER_8821C(x) \
+ ((x) & (~BITS_CMDIN_2RESP_TIMER_8821C))
+#define BIT_GET_CMDIN_2RESP_TIMER_8821C(x) \
+ (((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER_8821C) & \
+ BIT_MASK_CMDIN_2RESP_TIMER_8821C)
+#define BIT_SET_CMDIN_2RESP_TIMER_8821C(x, v) \
+ (BIT_CLEAR_CMDIN_2RESP_TIMER_8821C(x) | BIT_CMDIN_2RESP_TIMER_8821C(v))
/* 2 REG_SDIO_CMD_CRC_8821C */
#define BIT_SHIFT_SDIO_CMD_CRC_V1_8821C 0
#define BIT_MASK_SDIO_CMD_CRC_V1_8821C 0xff
-#define BIT_SDIO_CMD_CRC_V1_8821C(x) (((x) & BIT_MASK_SDIO_CMD_CRC_V1_8821C) << BIT_SHIFT_SDIO_CMD_CRC_V1_8821C)
-#define BIT_GET_SDIO_CMD_CRC_V1_8821C(x) (((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1_8821C) & BIT_MASK_SDIO_CMD_CRC_V1_8821C)
-
+#define BIT_SDIO_CMD_CRC_V1_8821C(x) \
+ (((x) & BIT_MASK_SDIO_CMD_CRC_V1_8821C) \
+ << BIT_SHIFT_SDIO_CMD_CRC_V1_8821C)
+#define BITS_SDIO_CMD_CRC_V1_8821C \
+ (BIT_MASK_SDIO_CMD_CRC_V1_8821C << BIT_SHIFT_SDIO_CMD_CRC_V1_8821C)
+#define BIT_CLEAR_SDIO_CMD_CRC_V1_8821C(x) ((x) & (~BITS_SDIO_CMD_CRC_V1_8821C))
+#define BIT_GET_SDIO_CMD_CRC_V1_8821C(x) \
+ (((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1_8821C) & \
+ BIT_MASK_SDIO_CMD_CRC_V1_8821C)
+#define BIT_SET_SDIO_CMD_CRC_V1_8821C(x, v) \
+ (BIT_CLEAR_SDIO_CMD_CRC_V1_8821C(x) | BIT_SDIO_CMD_CRC_V1_8821C(v))
/* 2 REG_SDIO_HSISR_8821C */
#define BIT_DRV_WLAN_INT_CLR_8821C BIT(1)
#define BIT_DRV_WLAN_INT_8821C BIT(0)
-/* 2 REG_SDIO_HSIMR_8821C */
-#define BIT_HISR_MASK_8821C BIT(0)
-
/* 2 REG_SDIO_ERR_RPT_8821C */
#define BIT_HR_FF_OVF_8821C BIT(6)
#define BIT_HR_FF_UDN_8821C BIT(5)
#define BIT_TXDMA_BUSY_ERR_8821C BIT(4)
#define BIT_TXDMA_VLD_ERR_8821C BIT(3)
-#define BIT_QSEL_UNKOWN_ERR_8821C BIT(2)
+#define BIT_QSEL_UNKNOWN_ERR_8821C BIT(2)
#define BIT_QSEL_MIS_ERR_8821C BIT(1)
#define BIT_SDIO_OVERRD_ERR_8821C BIT(0)
@@ -9946,25 +19392,53 @@
#define BIT_SHIFT_CMD_CRC_ERR_CNT_8821C 0
#define BIT_MASK_CMD_CRC_ERR_CNT_8821C 0xff
-#define BIT_CMD_CRC_ERR_CNT_8821C(x) (((x) & BIT_MASK_CMD_CRC_ERR_CNT_8821C) << BIT_SHIFT_CMD_CRC_ERR_CNT_8821C)
-#define BIT_GET_CMD_CRC_ERR_CNT_8821C(x) (((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT_8821C) & BIT_MASK_CMD_CRC_ERR_CNT_8821C)
-
+#define BIT_CMD_CRC_ERR_CNT_8821C(x) \
+ (((x) & BIT_MASK_CMD_CRC_ERR_CNT_8821C) \
+ << BIT_SHIFT_CMD_CRC_ERR_CNT_8821C)
+#define BITS_CMD_CRC_ERR_CNT_8821C \
+ (BIT_MASK_CMD_CRC_ERR_CNT_8821C << BIT_SHIFT_CMD_CRC_ERR_CNT_8821C)
+#define BIT_CLEAR_CMD_CRC_ERR_CNT_8821C(x) ((x) & (~BITS_CMD_CRC_ERR_CNT_8821C))
+#define BIT_GET_CMD_CRC_ERR_CNT_8821C(x) \
+ (((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT_8821C) & \
+ BIT_MASK_CMD_CRC_ERR_CNT_8821C)
+#define BIT_SET_CMD_CRC_ERR_CNT_8821C(x, v) \
+ (BIT_CLEAR_CMD_CRC_ERR_CNT_8821C(x) | BIT_CMD_CRC_ERR_CNT_8821C(v))
/* 2 REG_SDIO_DATA_ERRCNT_8821C */
#define BIT_SHIFT_DATA_CRC_ERR_CNT_8821C 0
#define BIT_MASK_DATA_CRC_ERR_CNT_8821C 0xff
-#define BIT_DATA_CRC_ERR_CNT_8821C(x) (((x) & BIT_MASK_DATA_CRC_ERR_CNT_8821C) << BIT_SHIFT_DATA_CRC_ERR_CNT_8821C)
-#define BIT_GET_DATA_CRC_ERR_CNT_8821C(x) (((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT_8821C) & BIT_MASK_DATA_CRC_ERR_CNT_8821C)
-
+#define BIT_DATA_CRC_ERR_CNT_8821C(x) \
+ (((x) & BIT_MASK_DATA_CRC_ERR_CNT_8821C) \
+ << BIT_SHIFT_DATA_CRC_ERR_CNT_8821C)
+#define BITS_DATA_CRC_ERR_CNT_8821C \
+ (BIT_MASK_DATA_CRC_ERR_CNT_8821C << BIT_SHIFT_DATA_CRC_ERR_CNT_8821C)
+#define BIT_CLEAR_DATA_CRC_ERR_CNT_8821C(x) \
+ ((x) & (~BITS_DATA_CRC_ERR_CNT_8821C))
+#define BIT_GET_DATA_CRC_ERR_CNT_8821C(x) \
+ (((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT_8821C) & \
+ BIT_MASK_DATA_CRC_ERR_CNT_8821C)
+#define BIT_SET_DATA_CRC_ERR_CNT_8821C(x, v) \
+ (BIT_CLEAR_DATA_CRC_ERR_CNT_8821C(x) | BIT_DATA_CRC_ERR_CNT_8821C(v))
/* 2 REG_SDIO_CMD_ERR_CONTENT_8821C */
#define BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8821C 0
#define BIT_MASK_SDIO_CMD_ERR_CONTENT_8821C 0xffffffffffL
-#define BIT_SDIO_CMD_ERR_CONTENT_8821C(x) (((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8821C) << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8821C)
-#define BIT_GET_SDIO_CMD_ERR_CONTENT_8821C(x) (((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8821C) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8821C)
-
+#define BIT_SDIO_CMD_ERR_CONTENT_8821C(x) \
+ (((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8821C) \
+ << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8821C)
+#define BITS_SDIO_CMD_ERR_CONTENT_8821C \
+ (BIT_MASK_SDIO_CMD_ERR_CONTENT_8821C \
+ << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8821C)
+#define BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8821C(x) \
+ ((x) & (~BITS_SDIO_CMD_ERR_CONTENT_8821C))
+#define BIT_GET_SDIO_CMD_ERR_CONTENT_8821C(x) \
+ (((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8821C) & \
+ BIT_MASK_SDIO_CMD_ERR_CONTENT_8821C)
+#define BIT_SET_SDIO_CMD_ERR_CONTENT_8821C(x, v) \
+ (BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8821C(x) | \
+ BIT_SDIO_CMD_ERR_CONTENT_8821C(v))
/* 2 REG_SDIO_CRC_ERR_IDX_8821C */
#define BIT_D3_CRC_ERR_8821C BIT(4)
@@ -9976,17 +19450,34 @@
/* 2 REG_SDIO_DATA_CRC_8821C */
#define BIT_SHIFT_SDIO_DATA_CRC_8821C 0
-#define BIT_MASK_SDIO_DATA_CRC_8821C 0xff
-#define BIT_SDIO_DATA_CRC_8821C(x) (((x) & BIT_MASK_SDIO_DATA_CRC_8821C) << BIT_SHIFT_SDIO_DATA_CRC_8821C)
-#define BIT_GET_SDIO_DATA_CRC_8821C(x) (((x) >> BIT_SHIFT_SDIO_DATA_CRC_8821C) & BIT_MASK_SDIO_DATA_CRC_8821C)
-
+#define BIT_MASK_SDIO_DATA_CRC_8821C 0xffff
+#define BIT_SDIO_DATA_CRC_8821C(x) \
+ (((x) & BIT_MASK_SDIO_DATA_CRC_8821C) << BIT_SHIFT_SDIO_DATA_CRC_8821C)
+#define BITS_SDIO_DATA_CRC_8821C \
+ (BIT_MASK_SDIO_DATA_CRC_8821C << BIT_SHIFT_SDIO_DATA_CRC_8821C)
+#define BIT_CLEAR_SDIO_DATA_CRC_8821C(x) ((x) & (~BITS_SDIO_DATA_CRC_8821C))
+#define BIT_GET_SDIO_DATA_CRC_8821C(x) \
+ (((x) >> BIT_SHIFT_SDIO_DATA_CRC_8821C) & BIT_MASK_SDIO_DATA_CRC_8821C)
+#define BIT_SET_SDIO_DATA_CRC_8821C(x, v) \
+ (BIT_CLEAR_SDIO_DATA_CRC_8821C(x) | BIT_SDIO_DATA_CRC_8821C(v))
/* 2 REG_SDIO_DATA_REPLY_TIME_8821C */
#define BIT_SHIFT_SDIO_DATA_REPLY_TIME_8821C 0
#define BIT_MASK_SDIO_DATA_REPLY_TIME_8821C 0x7
-#define BIT_SDIO_DATA_REPLY_TIME_8821C(x) (((x) & BIT_MASK_SDIO_DATA_REPLY_TIME_8821C) << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8821C)
-#define BIT_GET_SDIO_DATA_REPLY_TIME_8821C(x) (((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME_8821C) & BIT_MASK_SDIO_DATA_REPLY_TIME_8821C)
-
+#define BIT_SDIO_DATA_REPLY_TIME_8821C(x) \
+ (((x) & BIT_MASK_SDIO_DATA_REPLY_TIME_8821C) \
+ << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8821C)
+#define BITS_SDIO_DATA_REPLY_TIME_8821C \
+ (BIT_MASK_SDIO_DATA_REPLY_TIME_8821C \
+ << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8821C)
+#define BIT_CLEAR_SDIO_DATA_REPLY_TIME_8821C(x) \
+ ((x) & (~BITS_SDIO_DATA_REPLY_TIME_8821C))
+#define BIT_GET_SDIO_DATA_REPLY_TIME_8821C(x) \
+ (((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME_8821C) & \
+ BIT_MASK_SDIO_DATA_REPLY_TIME_8821C)
+#define BIT_SET_SDIO_DATA_REPLY_TIME_8821C(x, v) \
+ (BIT_CLEAR_SDIO_DATA_REPLY_TIME_8821C(x) | \
+ BIT_SDIO_DATA_REPLY_TIME_8821C(v))
#endif
diff --git a/hal/halmac/halmac_bit_8822b.h b/hal/halmac/halmac_bit_8822b.h
index 089f8d3..0b29665 100644
--- a/hal/halmac/halmac_bit_8822b.h
+++ b/hal/halmac/halmac_bit_8822b.h
@@ -1,3 +1,18 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
#ifndef __INC_HALMAC_BIT_8822B_H
#define __INC_HALMAC_BIT_8822B_H
@@ -91,14 +106,25 @@
#define BIT_SHIFT_VPDIDX_8822B 8
#define BIT_MASK_VPDIDX_8822B 0xff
-#define BIT_VPDIDX_8822B(x) (((x) & BIT_MASK_VPDIDX_8822B) << BIT_SHIFT_VPDIDX_8822B)
-#define BIT_GET_VPDIDX_8822B(x) (((x) >> BIT_SHIFT_VPDIDX_8822B) & BIT_MASK_VPDIDX_8822B)
-
+#define BIT_VPDIDX_8822B(x) \
+ (((x) & BIT_MASK_VPDIDX_8822B) << BIT_SHIFT_VPDIDX_8822B)
+#define BITS_VPDIDX_8822B (BIT_MASK_VPDIDX_8822B << BIT_SHIFT_VPDIDX_8822B)
+#define BIT_CLEAR_VPDIDX_8822B(x) ((x) & (~BITS_VPDIDX_8822B))
+#define BIT_GET_VPDIDX_8822B(x) \
+ (((x) >> BIT_SHIFT_VPDIDX_8822B) & BIT_MASK_VPDIDX_8822B)
+#define BIT_SET_VPDIDX_8822B(x, v) \
+ (BIT_CLEAR_VPDIDX_8822B(x) | BIT_VPDIDX_8822B(v))
#define BIT_SHIFT_EEM1_0_8822B 6
#define BIT_MASK_EEM1_0_8822B 0x3
-#define BIT_EEM1_0_8822B(x) (((x) & BIT_MASK_EEM1_0_8822B) << BIT_SHIFT_EEM1_0_8822B)
-#define BIT_GET_EEM1_0_8822B(x) (((x) >> BIT_SHIFT_EEM1_0_8822B) & BIT_MASK_EEM1_0_8822B)
+#define BIT_EEM1_0_8822B(x) \
+ (((x) & BIT_MASK_EEM1_0_8822B) << BIT_SHIFT_EEM1_0_8822B)
+#define BITS_EEM1_0_8822B (BIT_MASK_EEM1_0_8822B << BIT_SHIFT_EEM1_0_8822B)
+#define BIT_CLEAR_EEM1_0_8822B(x) ((x) & (~BITS_EEM1_0_8822B))
+#define BIT_GET_EEM1_0_8822B(x) \
+ (((x) >> BIT_SHIFT_EEM1_0_8822B) & BIT_MASK_EEM1_0_8822B)
+#define BIT_SET_EEM1_0_8822B(x, v) \
+ (BIT_CLEAR_EEM1_0_8822B(x) | BIT_EEM1_0_8822B(v))
#define BIT_AUTOLOAD_SUS_8822B BIT(5)
#define BIT_EERPOMSEL_8822B BIT(4)
@@ -111,9 +137,15 @@
#define BIT_SHIFT_VPD_DATA_8822B 0
#define BIT_MASK_VPD_DATA_8822B 0xffffffffL
-#define BIT_VPD_DATA_8822B(x) (((x) & BIT_MASK_VPD_DATA_8822B) << BIT_SHIFT_VPD_DATA_8822B)
-#define BIT_GET_VPD_DATA_8822B(x) (((x) >> BIT_SHIFT_VPD_DATA_8822B) & BIT_MASK_VPD_DATA_8822B)
-
+#define BIT_VPD_DATA_8822B(x) \
+ (((x) & BIT_MASK_VPD_DATA_8822B) << BIT_SHIFT_VPD_DATA_8822B)
+#define BITS_VPD_DATA_8822B \
+ (BIT_MASK_VPD_DATA_8822B << BIT_SHIFT_VPD_DATA_8822B)
+#define BIT_CLEAR_VPD_DATA_8822B(x) ((x) & (~BITS_VPD_DATA_8822B))
+#define BIT_GET_VPD_DATA_8822B(x) \
+ (((x) >> BIT_SHIFT_VPD_DATA_8822B) & BIT_MASK_VPD_DATA_8822B)
+#define BIT_SET_VPD_DATA_8822B(x, v) \
+ (BIT_CLEAR_VPD_DATA_8822B(x) | BIT_VPD_DATA_8822B(v))
/* 2 REG_SYS_SWR_CTRL1_8822B */
#define BIT_C2_L_BIT0_8822B BIT(31)
@@ -121,20 +153,37 @@
#define BIT_SHIFT_C1_L_8822B 29
#define BIT_MASK_C1_L_8822B 0x3
#define BIT_C1_L_8822B(x) (((x) & BIT_MASK_C1_L_8822B) << BIT_SHIFT_C1_L_8822B)
-#define BIT_GET_C1_L_8822B(x) (((x) >> BIT_SHIFT_C1_L_8822B) & BIT_MASK_C1_L_8822B)
-
+#define BITS_C1_L_8822B (BIT_MASK_C1_L_8822B << BIT_SHIFT_C1_L_8822B)
+#define BIT_CLEAR_C1_L_8822B(x) ((x) & (~BITS_C1_L_8822B))
+#define BIT_GET_C1_L_8822B(x) \
+ (((x) >> BIT_SHIFT_C1_L_8822B) & BIT_MASK_C1_L_8822B)
+#define BIT_SET_C1_L_8822B(x, v) (BIT_CLEAR_C1_L_8822B(x) | BIT_C1_L_8822B(v))
#define BIT_SHIFT_REG_FREQ_L_8822B 25
#define BIT_MASK_REG_FREQ_L_8822B 0x7
-#define BIT_REG_FREQ_L_8822B(x) (((x) & BIT_MASK_REG_FREQ_L_8822B) << BIT_SHIFT_REG_FREQ_L_8822B)
-#define BIT_GET_REG_FREQ_L_8822B(x) (((x) >> BIT_SHIFT_REG_FREQ_L_8822B) & BIT_MASK_REG_FREQ_L_8822B)
+#define BIT_REG_FREQ_L_8822B(x) \
+ (((x) & BIT_MASK_REG_FREQ_L_8822B) << BIT_SHIFT_REG_FREQ_L_8822B)
+#define BITS_REG_FREQ_L_8822B \
+ (BIT_MASK_REG_FREQ_L_8822B << BIT_SHIFT_REG_FREQ_L_8822B)
+#define BIT_CLEAR_REG_FREQ_L_8822B(x) ((x) & (~BITS_REG_FREQ_L_8822B))
+#define BIT_GET_REG_FREQ_L_8822B(x) \
+ (((x) >> BIT_SHIFT_REG_FREQ_L_8822B) & BIT_MASK_REG_FREQ_L_8822B)
+#define BIT_SET_REG_FREQ_L_8822B(x, v) \
+ (BIT_CLEAR_REG_FREQ_L_8822B(x) | BIT_REG_FREQ_L_8822B(v))
#define BIT_REG_EN_DUTY_8822B BIT(24)
#define BIT_SHIFT_REG_MODE_8822B 22
#define BIT_MASK_REG_MODE_8822B 0x3
-#define BIT_REG_MODE_8822B(x) (((x) & BIT_MASK_REG_MODE_8822B) << BIT_SHIFT_REG_MODE_8822B)
-#define BIT_GET_REG_MODE_8822B(x) (((x) >> BIT_SHIFT_REG_MODE_8822B) & BIT_MASK_REG_MODE_8822B)
+#define BIT_REG_MODE_8822B(x) \
+ (((x) & BIT_MASK_REG_MODE_8822B) << BIT_SHIFT_REG_MODE_8822B)
+#define BITS_REG_MODE_8822B \
+ (BIT_MASK_REG_MODE_8822B << BIT_SHIFT_REG_MODE_8822B)
+#define BIT_CLEAR_REG_MODE_8822B(x) ((x) & (~BITS_REG_MODE_8822B))
+#define BIT_GET_REG_MODE_8822B(x) \
+ (((x) >> BIT_SHIFT_REG_MODE_8822B) & BIT_MASK_REG_MODE_8822B)
+#define BIT_SET_REG_MODE_8822B(x, v) \
+ (BIT_CLEAR_REG_MODE_8822B(x) | BIT_REG_MODE_8822B(v))
#define BIT_REG_EN_SP_8822B BIT(21)
#define BIT_REG_AUTO_L_8822B BIT(20)
@@ -143,14 +192,23 @@
#define BIT_SHIFT_OCP_L1_8822B 15
#define BIT_MASK_OCP_L1_8822B 0x7
-#define BIT_OCP_L1_8822B(x) (((x) & BIT_MASK_OCP_L1_8822B) << BIT_SHIFT_OCP_L1_8822B)
-#define BIT_GET_OCP_L1_8822B(x) (((x) >> BIT_SHIFT_OCP_L1_8822B) & BIT_MASK_OCP_L1_8822B)
-
+#define BIT_OCP_L1_8822B(x) \
+ (((x) & BIT_MASK_OCP_L1_8822B) << BIT_SHIFT_OCP_L1_8822B)
+#define BITS_OCP_L1_8822B (BIT_MASK_OCP_L1_8822B << BIT_SHIFT_OCP_L1_8822B)
+#define BIT_CLEAR_OCP_L1_8822B(x) ((x) & (~BITS_OCP_L1_8822B))
+#define BIT_GET_OCP_L1_8822B(x) \
+ (((x) >> BIT_SHIFT_OCP_L1_8822B) & BIT_MASK_OCP_L1_8822B)
+#define BIT_SET_OCP_L1_8822B(x, v) \
+ (BIT_CLEAR_OCP_L1_8822B(x) | BIT_OCP_L1_8822B(v))
#define BIT_SHIFT_CF_L_8822B 13
#define BIT_MASK_CF_L_8822B 0x3
#define BIT_CF_L_8822B(x) (((x) & BIT_MASK_CF_L_8822B) << BIT_SHIFT_CF_L_8822B)
-#define BIT_GET_CF_L_8822B(x) (((x) >> BIT_SHIFT_CF_L_8822B) & BIT_MASK_CF_L_8822B)
+#define BITS_CF_L_8822B (BIT_MASK_CF_L_8822B << BIT_SHIFT_CF_L_8822B)
+#define BIT_CLEAR_CF_L_8822B(x) ((x) & (~BITS_CF_L_8822B))
+#define BIT_GET_CF_L_8822B(x) \
+ (((x) >> BIT_SHIFT_CF_L_8822B) & BIT_MASK_CF_L_8822B)
+#define BIT_SET_CF_L_8822B(x, v) (BIT_CLEAR_CF_L_8822B(x) | BIT_CF_L_8822B(v))
#define BIT_SW18_FPWM_8822B BIT(11)
#define BIT_SW18_SWEN_8822B BIT(9)
@@ -164,32 +222,62 @@
#define BIT_SHIFT_REG_DELAY_8822B 28
#define BIT_MASK_REG_DELAY_8822B 0x3
-#define BIT_REG_DELAY_8822B(x) (((x) & BIT_MASK_REG_DELAY_8822B) << BIT_SHIFT_REG_DELAY_8822B)
-#define BIT_GET_REG_DELAY_8822B(x) (((x) >> BIT_SHIFT_REG_DELAY_8822B) & BIT_MASK_REG_DELAY_8822B)
-
+#define BIT_REG_DELAY_8822B(x) \
+ (((x) & BIT_MASK_REG_DELAY_8822B) << BIT_SHIFT_REG_DELAY_8822B)
+#define BITS_REG_DELAY_8822B \
+ (BIT_MASK_REG_DELAY_8822B << BIT_SHIFT_REG_DELAY_8822B)
+#define BIT_CLEAR_REG_DELAY_8822B(x) ((x) & (~BITS_REG_DELAY_8822B))
+#define BIT_GET_REG_DELAY_8822B(x) \
+ (((x) >> BIT_SHIFT_REG_DELAY_8822B) & BIT_MASK_REG_DELAY_8822B)
+#define BIT_SET_REG_DELAY_8822B(x, v) \
+ (BIT_CLEAR_REG_DELAY_8822B(x) | BIT_REG_DELAY_8822B(v))
#define BIT_SHIFT_V15ADJ_L1_V1_8822B 24
#define BIT_MASK_V15ADJ_L1_V1_8822B 0x7
-#define BIT_V15ADJ_L1_V1_8822B(x) (((x) & BIT_MASK_V15ADJ_L1_V1_8822B) << BIT_SHIFT_V15ADJ_L1_V1_8822B)
-#define BIT_GET_V15ADJ_L1_V1_8822B(x) (((x) >> BIT_SHIFT_V15ADJ_L1_V1_8822B) & BIT_MASK_V15ADJ_L1_V1_8822B)
-
+#define BIT_V15ADJ_L1_V1_8822B(x) \
+ (((x) & BIT_MASK_V15ADJ_L1_V1_8822B) << BIT_SHIFT_V15ADJ_L1_V1_8822B)
+#define BITS_V15ADJ_L1_V1_8822B \
+ (BIT_MASK_V15ADJ_L1_V1_8822B << BIT_SHIFT_V15ADJ_L1_V1_8822B)
+#define BIT_CLEAR_V15ADJ_L1_V1_8822B(x) ((x) & (~BITS_V15ADJ_L1_V1_8822B))
+#define BIT_GET_V15ADJ_L1_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_V15ADJ_L1_V1_8822B) & BIT_MASK_V15ADJ_L1_V1_8822B)
+#define BIT_SET_V15ADJ_L1_V1_8822B(x, v) \
+ (BIT_CLEAR_V15ADJ_L1_V1_8822B(x) | BIT_V15ADJ_L1_V1_8822B(v))
#define BIT_SHIFT_VOL_L1_V1_8822B 20
#define BIT_MASK_VOL_L1_V1_8822B 0xf
-#define BIT_VOL_L1_V1_8822B(x) (((x) & BIT_MASK_VOL_L1_V1_8822B) << BIT_SHIFT_VOL_L1_V1_8822B)
-#define BIT_GET_VOL_L1_V1_8822B(x) (((x) >> BIT_SHIFT_VOL_L1_V1_8822B) & BIT_MASK_VOL_L1_V1_8822B)
-
+#define BIT_VOL_L1_V1_8822B(x) \
+ (((x) & BIT_MASK_VOL_L1_V1_8822B) << BIT_SHIFT_VOL_L1_V1_8822B)
+#define BITS_VOL_L1_V1_8822B \
+ (BIT_MASK_VOL_L1_V1_8822B << BIT_SHIFT_VOL_L1_V1_8822B)
+#define BIT_CLEAR_VOL_L1_V1_8822B(x) ((x) & (~BITS_VOL_L1_V1_8822B))
+#define BIT_GET_VOL_L1_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_VOL_L1_V1_8822B) & BIT_MASK_VOL_L1_V1_8822B)
+#define BIT_SET_VOL_L1_V1_8822B(x, v) \
+ (BIT_CLEAR_VOL_L1_V1_8822B(x) | BIT_VOL_L1_V1_8822B(v))
#define BIT_SHIFT_IN_L1_V1_8822B 17
#define BIT_MASK_IN_L1_V1_8822B 0x7
-#define BIT_IN_L1_V1_8822B(x) (((x) & BIT_MASK_IN_L1_V1_8822B) << BIT_SHIFT_IN_L1_V1_8822B)
-#define BIT_GET_IN_L1_V1_8822B(x) (((x) >> BIT_SHIFT_IN_L1_V1_8822B) & BIT_MASK_IN_L1_V1_8822B)
-
+#define BIT_IN_L1_V1_8822B(x) \
+ (((x) & BIT_MASK_IN_L1_V1_8822B) << BIT_SHIFT_IN_L1_V1_8822B)
+#define BITS_IN_L1_V1_8822B \
+ (BIT_MASK_IN_L1_V1_8822B << BIT_SHIFT_IN_L1_V1_8822B)
+#define BIT_CLEAR_IN_L1_V1_8822B(x) ((x) & (~BITS_IN_L1_V1_8822B))
+#define BIT_GET_IN_L1_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_IN_L1_V1_8822B) & BIT_MASK_IN_L1_V1_8822B)
+#define BIT_SET_IN_L1_V1_8822B(x, v) \
+ (BIT_CLEAR_IN_L1_V1_8822B(x) | BIT_IN_L1_V1_8822B(v))
#define BIT_SHIFT_TBOX_L1_8822B 15
#define BIT_MASK_TBOX_L1_8822B 0x3
-#define BIT_TBOX_L1_8822B(x) (((x) & BIT_MASK_TBOX_L1_8822B) << BIT_SHIFT_TBOX_L1_8822B)
-#define BIT_GET_TBOX_L1_8822B(x) (((x) >> BIT_SHIFT_TBOX_L1_8822B) & BIT_MASK_TBOX_L1_8822B)
+#define BIT_TBOX_L1_8822B(x) \
+ (((x) & BIT_MASK_TBOX_L1_8822B) << BIT_SHIFT_TBOX_L1_8822B)
+#define BITS_TBOX_L1_8822B (BIT_MASK_TBOX_L1_8822B << BIT_SHIFT_TBOX_L1_8822B)
+#define BIT_CLEAR_TBOX_L1_8822B(x) ((x) & (~BITS_TBOX_L1_8822B))
+#define BIT_GET_TBOX_L1_8822B(x) \
+ (((x) >> BIT_SHIFT_TBOX_L1_8822B) & BIT_MASK_TBOX_L1_8822B)
+#define BIT_SET_TBOX_L1_8822B(x, v) \
+ (BIT_CLEAR_TBOX_L1_8822B(x) | BIT_TBOX_L1_8822B(v))
#define BIT_SW18_SEL_8822B BIT(13)
@@ -199,25 +287,44 @@
#define BIT_SHIFT_R3_L_8822B 7
#define BIT_MASK_R3_L_8822B 0x3
#define BIT_R3_L_8822B(x) (((x) & BIT_MASK_R3_L_8822B) << BIT_SHIFT_R3_L_8822B)
-#define BIT_GET_R3_L_8822B(x) (((x) >> BIT_SHIFT_R3_L_8822B) & BIT_MASK_R3_L_8822B)
-
+#define BITS_R3_L_8822B (BIT_MASK_R3_L_8822B << BIT_SHIFT_R3_L_8822B)
+#define BIT_CLEAR_R3_L_8822B(x) ((x) & (~BITS_R3_L_8822B))
+#define BIT_GET_R3_L_8822B(x) \
+ (((x) >> BIT_SHIFT_R3_L_8822B) & BIT_MASK_R3_L_8822B)
+#define BIT_SET_R3_L_8822B(x, v) (BIT_CLEAR_R3_L_8822B(x) | BIT_R3_L_8822B(v))
#define BIT_SHIFT_SW18_R2_8822B 5
#define BIT_MASK_SW18_R2_8822B 0x3
-#define BIT_SW18_R2_8822B(x) (((x) & BIT_MASK_SW18_R2_8822B) << BIT_SHIFT_SW18_R2_8822B)
-#define BIT_GET_SW18_R2_8822B(x) (((x) >> BIT_SHIFT_SW18_R2_8822B) & BIT_MASK_SW18_R2_8822B)
-
+#define BIT_SW18_R2_8822B(x) \
+ (((x) & BIT_MASK_SW18_R2_8822B) << BIT_SHIFT_SW18_R2_8822B)
+#define BITS_SW18_R2_8822B (BIT_MASK_SW18_R2_8822B << BIT_SHIFT_SW18_R2_8822B)
+#define BIT_CLEAR_SW18_R2_8822B(x) ((x) & (~BITS_SW18_R2_8822B))
+#define BIT_GET_SW18_R2_8822B(x) \
+ (((x) >> BIT_SHIFT_SW18_R2_8822B) & BIT_MASK_SW18_R2_8822B)
+#define BIT_SET_SW18_R2_8822B(x, v) \
+ (BIT_CLEAR_SW18_R2_8822B(x) | BIT_SW18_R2_8822B(v))
#define BIT_SHIFT_SW18_R1_8822B 3
#define BIT_MASK_SW18_R1_8822B 0x3
-#define BIT_SW18_R1_8822B(x) (((x) & BIT_MASK_SW18_R1_8822B) << BIT_SHIFT_SW18_R1_8822B)
-#define BIT_GET_SW18_R1_8822B(x) (((x) >> BIT_SHIFT_SW18_R1_8822B) & BIT_MASK_SW18_R1_8822B)
-
+#define BIT_SW18_R1_8822B(x) \
+ (((x) & BIT_MASK_SW18_R1_8822B) << BIT_SHIFT_SW18_R1_8822B)
+#define BITS_SW18_R1_8822B (BIT_MASK_SW18_R1_8822B << BIT_SHIFT_SW18_R1_8822B)
+#define BIT_CLEAR_SW18_R1_8822B(x) ((x) & (~BITS_SW18_R1_8822B))
+#define BIT_GET_SW18_R1_8822B(x) \
+ (((x) >> BIT_SHIFT_SW18_R1_8822B) & BIT_MASK_SW18_R1_8822B)
+#define BIT_SET_SW18_R1_8822B(x, v) \
+ (BIT_CLEAR_SW18_R1_8822B(x) | BIT_SW18_R1_8822B(v))
#define BIT_SHIFT_C3_L_C3_8822B 1
#define BIT_MASK_C3_L_C3_8822B 0x3
-#define BIT_C3_L_C3_8822B(x) (((x) & BIT_MASK_C3_L_C3_8822B) << BIT_SHIFT_C3_L_C3_8822B)
-#define BIT_GET_C3_L_C3_8822B(x) (((x) >> BIT_SHIFT_C3_L_C3_8822B) & BIT_MASK_C3_L_C3_8822B)
+#define BIT_C3_L_C3_8822B(x) \
+ (((x) & BIT_MASK_C3_L_C3_8822B) << BIT_SHIFT_C3_L_C3_8822B)
+#define BITS_C3_L_C3_8822B (BIT_MASK_C3_L_C3_8822B << BIT_SHIFT_C3_L_C3_8822B)
+#define BIT_CLEAR_C3_L_C3_8822B(x) ((x) & (~BITS_C3_L_C3_8822B))
+#define BIT_GET_C3_L_C3_8822B(x) \
+ (((x) >> BIT_SHIFT_C3_L_C3_8822B) & BIT_MASK_C3_L_C3_8822B)
+#define BIT_SET_C3_L_C3_8822B(x, v) \
+ (BIT_CLEAR_C3_L_C3_8822B(x) | BIT_C3_L_C3_8822B(v))
#define BIT_C2_L_BIT1_8822B BIT(0)
@@ -226,15 +333,27 @@
#define BIT_SHIFT_SPS18_OCP_TH_8822B 16
#define BIT_MASK_SPS18_OCP_TH_8822B 0x7fff
-#define BIT_SPS18_OCP_TH_8822B(x) (((x) & BIT_MASK_SPS18_OCP_TH_8822B) << BIT_SHIFT_SPS18_OCP_TH_8822B)
-#define BIT_GET_SPS18_OCP_TH_8822B(x) (((x) >> BIT_SHIFT_SPS18_OCP_TH_8822B) & BIT_MASK_SPS18_OCP_TH_8822B)
-
+#define BIT_SPS18_OCP_TH_8822B(x) \
+ (((x) & BIT_MASK_SPS18_OCP_TH_8822B) << BIT_SHIFT_SPS18_OCP_TH_8822B)
+#define BITS_SPS18_OCP_TH_8822B \
+ (BIT_MASK_SPS18_OCP_TH_8822B << BIT_SHIFT_SPS18_OCP_TH_8822B)
+#define BIT_CLEAR_SPS18_OCP_TH_8822B(x) ((x) & (~BITS_SPS18_OCP_TH_8822B))
+#define BIT_GET_SPS18_OCP_TH_8822B(x) \
+ (((x) >> BIT_SHIFT_SPS18_OCP_TH_8822B) & BIT_MASK_SPS18_OCP_TH_8822B)
+#define BIT_SET_SPS18_OCP_TH_8822B(x, v) \
+ (BIT_CLEAR_SPS18_OCP_TH_8822B(x) | BIT_SPS18_OCP_TH_8822B(v))
#define BIT_SHIFT_OCP_WINDOW_8822B 0
#define BIT_MASK_OCP_WINDOW_8822B 0xffff
-#define BIT_OCP_WINDOW_8822B(x) (((x) & BIT_MASK_OCP_WINDOW_8822B) << BIT_SHIFT_OCP_WINDOW_8822B)
-#define BIT_GET_OCP_WINDOW_8822B(x) (((x) >> BIT_SHIFT_OCP_WINDOW_8822B) & BIT_MASK_OCP_WINDOW_8822B)
-
+#define BIT_OCP_WINDOW_8822B(x) \
+ (((x) & BIT_MASK_OCP_WINDOW_8822B) << BIT_SHIFT_OCP_WINDOW_8822B)
+#define BITS_OCP_WINDOW_8822B \
+ (BIT_MASK_OCP_WINDOW_8822B << BIT_SHIFT_OCP_WINDOW_8822B)
+#define BIT_CLEAR_OCP_WINDOW_8822B(x) ((x) & (~BITS_OCP_WINDOW_8822B))
+#define BIT_GET_OCP_WINDOW_8822B(x) \
+ (((x) >> BIT_SHIFT_OCP_WINDOW_8822B) & BIT_MASK_OCP_WINDOW_8822B)
+#define BIT_SET_OCP_WINDOW_8822B(x, v) \
+ (BIT_CLEAR_OCP_WINDOW_8822B(x) | BIT_OCP_WINDOW_8822B(v))
/* 2 REG_RSV_CTRL_8822B */
#define BIT_HREG_DBG_8822B BIT(23)
@@ -257,15 +376,29 @@
#define BIT_SHIFT_LPLDH12_RSV_8822B 29
#define BIT_MASK_LPLDH12_RSV_8822B 0x7
-#define BIT_LPLDH12_RSV_8822B(x) (((x) & BIT_MASK_LPLDH12_RSV_8822B) << BIT_SHIFT_LPLDH12_RSV_8822B)
-#define BIT_GET_LPLDH12_RSV_8822B(x) (((x) >> BIT_SHIFT_LPLDH12_RSV_8822B) & BIT_MASK_LPLDH12_RSV_8822B)
+#define BIT_LPLDH12_RSV_8822B(x) \
+ (((x) & BIT_MASK_LPLDH12_RSV_8822B) << BIT_SHIFT_LPLDH12_RSV_8822B)
+#define BITS_LPLDH12_RSV_8822B \
+ (BIT_MASK_LPLDH12_RSV_8822B << BIT_SHIFT_LPLDH12_RSV_8822B)
+#define BIT_CLEAR_LPLDH12_RSV_8822B(x) ((x) & (~BITS_LPLDH12_RSV_8822B))
+#define BIT_GET_LPLDH12_RSV_8822B(x) \
+ (((x) >> BIT_SHIFT_LPLDH12_RSV_8822B) & BIT_MASK_LPLDH12_RSV_8822B)
+#define BIT_SET_LPLDH12_RSV_8822B(x, v) \
+ (BIT_CLEAR_LPLDH12_RSV_8822B(x) | BIT_LPLDH12_RSV_8822B(v))
#define BIT_LPLDH12_SLP_8822B BIT(28)
#define BIT_SHIFT_LPLDH12_VADJ_8822B 24
#define BIT_MASK_LPLDH12_VADJ_8822B 0xf
-#define BIT_LPLDH12_VADJ_8822B(x) (((x) & BIT_MASK_LPLDH12_VADJ_8822B) << BIT_SHIFT_LPLDH12_VADJ_8822B)
-#define BIT_GET_LPLDH12_VADJ_8822B(x) (((x) >> BIT_SHIFT_LPLDH12_VADJ_8822B) & BIT_MASK_LPLDH12_VADJ_8822B)
+#define BIT_LPLDH12_VADJ_8822B(x) \
+ (((x) & BIT_MASK_LPLDH12_VADJ_8822B) << BIT_SHIFT_LPLDH12_VADJ_8822B)
+#define BITS_LPLDH12_VADJ_8822B \
+ (BIT_MASK_LPLDH12_VADJ_8822B << BIT_SHIFT_LPLDH12_VADJ_8822B)
+#define BIT_CLEAR_LPLDH12_VADJ_8822B(x) ((x) & (~BITS_LPLDH12_VADJ_8822B))
+#define BIT_GET_LPLDH12_VADJ_8822B(x) \
+ (((x) >> BIT_SHIFT_LPLDH12_VADJ_8822B) & BIT_MASK_LPLDH12_VADJ_8822B)
+#define BIT_SET_LPLDH12_VADJ_8822B(x, v) \
+ (BIT_CLEAR_LPLDH12_VADJ_8822B(x) | BIT_LPLDH12_VADJ_8822B(v))
#define BIT_LDH12_EN_8822B BIT(16)
#define BIT_WLBBOFF_BIG_PWC_EN_8822B BIT(14)
@@ -289,40 +422,79 @@
#define BIT_SHIFT_XTAL_CAP_XI_8822B 25
#define BIT_MASK_XTAL_CAP_XI_8822B 0x3f
-#define BIT_XTAL_CAP_XI_8822B(x) (((x) & BIT_MASK_XTAL_CAP_XI_8822B) << BIT_SHIFT_XTAL_CAP_XI_8822B)
-#define BIT_GET_XTAL_CAP_XI_8822B(x) (((x) >> BIT_SHIFT_XTAL_CAP_XI_8822B) & BIT_MASK_XTAL_CAP_XI_8822B)
-
+#define BIT_XTAL_CAP_XI_8822B(x) \
+ (((x) & BIT_MASK_XTAL_CAP_XI_8822B) << BIT_SHIFT_XTAL_CAP_XI_8822B)
+#define BITS_XTAL_CAP_XI_8822B \
+ (BIT_MASK_XTAL_CAP_XI_8822B << BIT_SHIFT_XTAL_CAP_XI_8822B)
+#define BIT_CLEAR_XTAL_CAP_XI_8822B(x) ((x) & (~BITS_XTAL_CAP_XI_8822B))
+#define BIT_GET_XTAL_CAP_XI_8822B(x) \
+ (((x) >> BIT_SHIFT_XTAL_CAP_XI_8822B) & BIT_MASK_XTAL_CAP_XI_8822B)
+#define BIT_SET_XTAL_CAP_XI_8822B(x, v) \
+ (BIT_CLEAR_XTAL_CAP_XI_8822B(x) | BIT_XTAL_CAP_XI_8822B(v))
#define BIT_SHIFT_XTAL_DRV_DIGI_8822B 23
#define BIT_MASK_XTAL_DRV_DIGI_8822B 0x3
-#define BIT_XTAL_DRV_DIGI_8822B(x) (((x) & BIT_MASK_XTAL_DRV_DIGI_8822B) << BIT_SHIFT_XTAL_DRV_DIGI_8822B)
-#define BIT_GET_XTAL_DRV_DIGI_8822B(x) (((x) >> BIT_SHIFT_XTAL_DRV_DIGI_8822B) & BIT_MASK_XTAL_DRV_DIGI_8822B)
+#define BIT_XTAL_DRV_DIGI_8822B(x) \
+ (((x) & BIT_MASK_XTAL_DRV_DIGI_8822B) << BIT_SHIFT_XTAL_DRV_DIGI_8822B)
+#define BITS_XTAL_DRV_DIGI_8822B \
+ (BIT_MASK_XTAL_DRV_DIGI_8822B << BIT_SHIFT_XTAL_DRV_DIGI_8822B)
+#define BIT_CLEAR_XTAL_DRV_DIGI_8822B(x) ((x) & (~BITS_XTAL_DRV_DIGI_8822B))
+#define BIT_GET_XTAL_DRV_DIGI_8822B(x) \
+ (((x) >> BIT_SHIFT_XTAL_DRV_DIGI_8822B) & BIT_MASK_XTAL_DRV_DIGI_8822B)
+#define BIT_SET_XTAL_DRV_DIGI_8822B(x, v) \
+ (BIT_CLEAR_XTAL_DRV_DIGI_8822B(x) | BIT_XTAL_DRV_DIGI_8822B(v))
#define BIT_XTAL_DRV_USB_BIT1_8822B BIT(22)
#define BIT_SHIFT_MAC_CLK_SEL_8822B 20
#define BIT_MASK_MAC_CLK_SEL_8822B 0x3
-#define BIT_MAC_CLK_SEL_8822B(x) (((x) & BIT_MASK_MAC_CLK_SEL_8822B) << BIT_SHIFT_MAC_CLK_SEL_8822B)
-#define BIT_GET_MAC_CLK_SEL_8822B(x) (((x) >> BIT_SHIFT_MAC_CLK_SEL_8822B) & BIT_MASK_MAC_CLK_SEL_8822B)
+#define BIT_MAC_CLK_SEL_8822B(x) \
+ (((x) & BIT_MASK_MAC_CLK_SEL_8822B) << BIT_SHIFT_MAC_CLK_SEL_8822B)
+#define BITS_MAC_CLK_SEL_8822B \
+ (BIT_MASK_MAC_CLK_SEL_8822B << BIT_SHIFT_MAC_CLK_SEL_8822B)
+#define BIT_CLEAR_MAC_CLK_SEL_8822B(x) ((x) & (~BITS_MAC_CLK_SEL_8822B))
+#define BIT_GET_MAC_CLK_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_MAC_CLK_SEL_8822B) & BIT_MASK_MAC_CLK_SEL_8822B)
+#define BIT_SET_MAC_CLK_SEL_8822B(x, v) \
+ (BIT_CLEAR_MAC_CLK_SEL_8822B(x) | BIT_MAC_CLK_SEL_8822B(v))
#define BIT_XTAL_DRV_USB_BIT0_8822B BIT(19)
#define BIT_SHIFT_XTAL_DRV_AFE_8822B 17
#define BIT_MASK_XTAL_DRV_AFE_8822B 0x3
-#define BIT_XTAL_DRV_AFE_8822B(x) (((x) & BIT_MASK_XTAL_DRV_AFE_8822B) << BIT_SHIFT_XTAL_DRV_AFE_8822B)
-#define BIT_GET_XTAL_DRV_AFE_8822B(x) (((x) >> BIT_SHIFT_XTAL_DRV_AFE_8822B) & BIT_MASK_XTAL_DRV_AFE_8822B)
-
+#define BIT_XTAL_DRV_AFE_8822B(x) \
+ (((x) & BIT_MASK_XTAL_DRV_AFE_8822B) << BIT_SHIFT_XTAL_DRV_AFE_8822B)
+#define BITS_XTAL_DRV_AFE_8822B \
+ (BIT_MASK_XTAL_DRV_AFE_8822B << BIT_SHIFT_XTAL_DRV_AFE_8822B)
+#define BIT_CLEAR_XTAL_DRV_AFE_8822B(x) ((x) & (~BITS_XTAL_DRV_AFE_8822B))
+#define BIT_GET_XTAL_DRV_AFE_8822B(x) \
+ (((x) >> BIT_SHIFT_XTAL_DRV_AFE_8822B) & BIT_MASK_XTAL_DRV_AFE_8822B)
+#define BIT_SET_XTAL_DRV_AFE_8822B(x, v) \
+ (BIT_CLEAR_XTAL_DRV_AFE_8822B(x) | BIT_XTAL_DRV_AFE_8822B(v))
#define BIT_SHIFT_XTAL_DRV_RF2_8822B 15
#define BIT_MASK_XTAL_DRV_RF2_8822B 0x3
-#define BIT_XTAL_DRV_RF2_8822B(x) (((x) & BIT_MASK_XTAL_DRV_RF2_8822B) << BIT_SHIFT_XTAL_DRV_RF2_8822B)
-#define BIT_GET_XTAL_DRV_RF2_8822B(x) (((x) >> BIT_SHIFT_XTAL_DRV_RF2_8822B) & BIT_MASK_XTAL_DRV_RF2_8822B)
-
+#define BIT_XTAL_DRV_RF2_8822B(x) \
+ (((x) & BIT_MASK_XTAL_DRV_RF2_8822B) << BIT_SHIFT_XTAL_DRV_RF2_8822B)
+#define BITS_XTAL_DRV_RF2_8822B \
+ (BIT_MASK_XTAL_DRV_RF2_8822B << BIT_SHIFT_XTAL_DRV_RF2_8822B)
+#define BIT_CLEAR_XTAL_DRV_RF2_8822B(x) ((x) & (~BITS_XTAL_DRV_RF2_8822B))
+#define BIT_GET_XTAL_DRV_RF2_8822B(x) \
+ (((x) >> BIT_SHIFT_XTAL_DRV_RF2_8822B) & BIT_MASK_XTAL_DRV_RF2_8822B)
+#define BIT_SET_XTAL_DRV_RF2_8822B(x, v) \
+ (BIT_CLEAR_XTAL_DRV_RF2_8822B(x) | BIT_XTAL_DRV_RF2_8822B(v))
#define BIT_SHIFT_XTAL_DRV_RF1_8822B 13
#define BIT_MASK_XTAL_DRV_RF1_8822B 0x3
-#define BIT_XTAL_DRV_RF1_8822B(x) (((x) & BIT_MASK_XTAL_DRV_RF1_8822B) << BIT_SHIFT_XTAL_DRV_RF1_8822B)
-#define BIT_GET_XTAL_DRV_RF1_8822B(x) (((x) >> BIT_SHIFT_XTAL_DRV_RF1_8822B) & BIT_MASK_XTAL_DRV_RF1_8822B)
+#define BIT_XTAL_DRV_RF1_8822B(x) \
+ (((x) & BIT_MASK_XTAL_DRV_RF1_8822B) << BIT_SHIFT_XTAL_DRV_RF1_8822B)
+#define BITS_XTAL_DRV_RF1_8822B \
+ (BIT_MASK_XTAL_DRV_RF1_8822B << BIT_SHIFT_XTAL_DRV_RF1_8822B)
+#define BIT_CLEAR_XTAL_DRV_RF1_8822B(x) ((x) & (~BITS_XTAL_DRV_RF1_8822B))
+#define BIT_GET_XTAL_DRV_RF1_8822B(x) \
+ (((x) >> BIT_SHIFT_XTAL_DRV_RF1_8822B) & BIT_MASK_XTAL_DRV_RF1_8822B)
+#define BIT_SET_XTAL_DRV_RF1_8822B(x, v) \
+ (BIT_CLEAR_XTAL_DRV_RF1_8822B(x) | BIT_XTAL_DRV_RF1_8822B(v))
#define BIT_XTAL_DELAY_DIGI_8822B BIT(12)
#define BIT_XTAL_DELAY_USB_8822B BIT(11)
@@ -330,22 +502,42 @@
#define BIT_SHIFT_XTAL_LDO_VREF_8822B 7
#define BIT_MASK_XTAL_LDO_VREF_8822B 0x7
-#define BIT_XTAL_LDO_VREF_8822B(x) (((x) & BIT_MASK_XTAL_LDO_VREF_8822B) << BIT_SHIFT_XTAL_LDO_VREF_8822B)
-#define BIT_GET_XTAL_LDO_VREF_8822B(x) (((x) >> BIT_SHIFT_XTAL_LDO_VREF_8822B) & BIT_MASK_XTAL_LDO_VREF_8822B)
+#define BIT_XTAL_LDO_VREF_8822B(x) \
+ (((x) & BIT_MASK_XTAL_LDO_VREF_8822B) << BIT_SHIFT_XTAL_LDO_VREF_8822B)
+#define BITS_XTAL_LDO_VREF_8822B \
+ (BIT_MASK_XTAL_LDO_VREF_8822B << BIT_SHIFT_XTAL_LDO_VREF_8822B)
+#define BIT_CLEAR_XTAL_LDO_VREF_8822B(x) ((x) & (~BITS_XTAL_LDO_VREF_8822B))
+#define BIT_GET_XTAL_LDO_VREF_8822B(x) \
+ (((x) >> BIT_SHIFT_XTAL_LDO_VREF_8822B) & BIT_MASK_XTAL_LDO_VREF_8822B)
+#define BIT_SET_XTAL_LDO_VREF_8822B(x, v) \
+ (BIT_CLEAR_XTAL_LDO_VREF_8822B(x) | BIT_XTAL_LDO_VREF_8822B(v))
#define BIT_XTAL_XQSEL_RF_8822B BIT(6)
#define BIT_XTAL_XQSEL_8822B BIT(5)
#define BIT_SHIFT_XTAL_GMN_V2_8822B 3
#define BIT_MASK_XTAL_GMN_V2_8822B 0x3
-#define BIT_XTAL_GMN_V2_8822B(x) (((x) & BIT_MASK_XTAL_GMN_V2_8822B) << BIT_SHIFT_XTAL_GMN_V2_8822B)
-#define BIT_GET_XTAL_GMN_V2_8822B(x) (((x) >> BIT_SHIFT_XTAL_GMN_V2_8822B) & BIT_MASK_XTAL_GMN_V2_8822B)
-
+#define BIT_XTAL_GMN_V2_8822B(x) \
+ (((x) & BIT_MASK_XTAL_GMN_V2_8822B) << BIT_SHIFT_XTAL_GMN_V2_8822B)
+#define BITS_XTAL_GMN_V2_8822B \
+ (BIT_MASK_XTAL_GMN_V2_8822B << BIT_SHIFT_XTAL_GMN_V2_8822B)
+#define BIT_CLEAR_XTAL_GMN_V2_8822B(x) ((x) & (~BITS_XTAL_GMN_V2_8822B))
+#define BIT_GET_XTAL_GMN_V2_8822B(x) \
+ (((x) >> BIT_SHIFT_XTAL_GMN_V2_8822B) & BIT_MASK_XTAL_GMN_V2_8822B)
+#define BIT_SET_XTAL_GMN_V2_8822B(x, v) \
+ (BIT_CLEAR_XTAL_GMN_V2_8822B(x) | BIT_XTAL_GMN_V2_8822B(v))
#define BIT_SHIFT_XTAL_GMP_V2_8822B 1
#define BIT_MASK_XTAL_GMP_V2_8822B 0x3
-#define BIT_XTAL_GMP_V2_8822B(x) (((x) & BIT_MASK_XTAL_GMP_V2_8822B) << BIT_SHIFT_XTAL_GMP_V2_8822B)
-#define BIT_GET_XTAL_GMP_V2_8822B(x) (((x) >> BIT_SHIFT_XTAL_GMP_V2_8822B) & BIT_MASK_XTAL_GMP_V2_8822B)
+#define BIT_XTAL_GMP_V2_8822B(x) \
+ (((x) & BIT_MASK_XTAL_GMP_V2_8822B) << BIT_SHIFT_XTAL_GMP_V2_8822B)
+#define BITS_XTAL_GMP_V2_8822B \
+ (BIT_MASK_XTAL_GMP_V2_8822B << BIT_SHIFT_XTAL_GMP_V2_8822B)
+#define BIT_CLEAR_XTAL_GMP_V2_8822B(x) ((x) & (~BITS_XTAL_GMP_V2_8822B))
+#define BIT_GET_XTAL_GMP_V2_8822B(x) \
+ (((x) >> BIT_SHIFT_XTAL_GMP_V2_8822B) & BIT_MASK_XTAL_GMP_V2_8822B)
+#define BIT_SET_XTAL_GMP_V2_8822B(x, v) \
+ (BIT_CLEAR_XTAL_GMP_V2_8822B(x) | BIT_XTAL_GMP_V2_8822B(v))
#define BIT_XTAL_EN_8822B BIT(0)
@@ -353,33 +545,63 @@
#define BIT_SHIFT_REG_C3_V4_8822B 30
#define BIT_MASK_REG_C3_V4_8822B 0x3
-#define BIT_REG_C3_V4_8822B(x) (((x) & BIT_MASK_REG_C3_V4_8822B) << BIT_SHIFT_REG_C3_V4_8822B)
-#define BIT_GET_REG_C3_V4_8822B(x) (((x) >> BIT_SHIFT_REG_C3_V4_8822B) & BIT_MASK_REG_C3_V4_8822B)
+#define BIT_REG_C3_V4_8822B(x) \
+ (((x) & BIT_MASK_REG_C3_V4_8822B) << BIT_SHIFT_REG_C3_V4_8822B)
+#define BITS_REG_C3_V4_8822B \
+ (BIT_MASK_REG_C3_V4_8822B << BIT_SHIFT_REG_C3_V4_8822B)
+#define BIT_CLEAR_REG_C3_V4_8822B(x) ((x) & (~BITS_REG_C3_V4_8822B))
+#define BIT_GET_REG_C3_V4_8822B(x) \
+ (((x) >> BIT_SHIFT_REG_C3_V4_8822B) & BIT_MASK_REG_C3_V4_8822B)
+#define BIT_SET_REG_C3_V4_8822B(x, v) \
+ (BIT_CLEAR_REG_C3_V4_8822B(x) | BIT_REG_C3_V4_8822B(v))
#define BIT_REG_CP_BIT1_8822B BIT(29)
#define BIT_SHIFT_REG_RS_V4_8822B 26
#define BIT_MASK_REG_RS_V4_8822B 0x7
-#define BIT_REG_RS_V4_8822B(x) (((x) & BIT_MASK_REG_RS_V4_8822B) << BIT_SHIFT_REG_RS_V4_8822B)
-#define BIT_GET_REG_RS_V4_8822B(x) (((x) >> BIT_SHIFT_REG_RS_V4_8822B) & BIT_MASK_REG_RS_V4_8822B)
-
+#define BIT_REG_RS_V4_8822B(x) \
+ (((x) & BIT_MASK_REG_RS_V4_8822B) << BIT_SHIFT_REG_RS_V4_8822B)
+#define BITS_REG_RS_V4_8822B \
+ (BIT_MASK_REG_RS_V4_8822B << BIT_SHIFT_REG_RS_V4_8822B)
+#define BIT_CLEAR_REG_RS_V4_8822B(x) ((x) & (~BITS_REG_RS_V4_8822B))
+#define BIT_GET_REG_RS_V4_8822B(x) \
+ (((x) >> BIT_SHIFT_REG_RS_V4_8822B) & BIT_MASK_REG_RS_V4_8822B)
+#define BIT_SET_REG_RS_V4_8822B(x, v) \
+ (BIT_CLEAR_REG_RS_V4_8822B(x) | BIT_REG_RS_V4_8822B(v))
#define BIT_SHIFT_REG__CS_8822B 24
#define BIT_MASK_REG__CS_8822B 0x3
-#define BIT_REG__CS_8822B(x) (((x) & BIT_MASK_REG__CS_8822B) << BIT_SHIFT_REG__CS_8822B)
-#define BIT_GET_REG__CS_8822B(x) (((x) >> BIT_SHIFT_REG__CS_8822B) & BIT_MASK_REG__CS_8822B)
-
+#define BIT_REG__CS_8822B(x) \
+ (((x) & BIT_MASK_REG__CS_8822B) << BIT_SHIFT_REG__CS_8822B)
+#define BITS_REG__CS_8822B (BIT_MASK_REG__CS_8822B << BIT_SHIFT_REG__CS_8822B)
+#define BIT_CLEAR_REG__CS_8822B(x) ((x) & (~BITS_REG__CS_8822B))
+#define BIT_GET_REG__CS_8822B(x) \
+ (((x) >> BIT_SHIFT_REG__CS_8822B) & BIT_MASK_REG__CS_8822B)
+#define BIT_SET_REG__CS_8822B(x, v) \
+ (BIT_CLEAR_REG__CS_8822B(x) | BIT_REG__CS_8822B(v))
#define BIT_SHIFT_REG_CP_OFFSET_8822B 21
#define BIT_MASK_REG_CP_OFFSET_8822B 0x7
-#define BIT_REG_CP_OFFSET_8822B(x) (((x) & BIT_MASK_REG_CP_OFFSET_8822B) << BIT_SHIFT_REG_CP_OFFSET_8822B)
-#define BIT_GET_REG_CP_OFFSET_8822B(x) (((x) >> BIT_SHIFT_REG_CP_OFFSET_8822B) & BIT_MASK_REG_CP_OFFSET_8822B)
-
+#define BIT_REG_CP_OFFSET_8822B(x) \
+ (((x) & BIT_MASK_REG_CP_OFFSET_8822B) << BIT_SHIFT_REG_CP_OFFSET_8822B)
+#define BITS_REG_CP_OFFSET_8822B \
+ (BIT_MASK_REG_CP_OFFSET_8822B << BIT_SHIFT_REG_CP_OFFSET_8822B)
+#define BIT_CLEAR_REG_CP_OFFSET_8822B(x) ((x) & (~BITS_REG_CP_OFFSET_8822B))
+#define BIT_GET_REG_CP_OFFSET_8822B(x) \
+ (((x) >> BIT_SHIFT_REG_CP_OFFSET_8822B) & BIT_MASK_REG_CP_OFFSET_8822B)
+#define BIT_SET_REG_CP_OFFSET_8822B(x, v) \
+ (BIT_CLEAR_REG_CP_OFFSET_8822B(x) | BIT_REG_CP_OFFSET_8822B(v))
#define BIT_SHIFT_CP_BIAS_8822B 18
#define BIT_MASK_CP_BIAS_8822B 0x7
-#define BIT_CP_BIAS_8822B(x) (((x) & BIT_MASK_CP_BIAS_8822B) << BIT_SHIFT_CP_BIAS_8822B)
-#define BIT_GET_CP_BIAS_8822B(x) (((x) >> BIT_SHIFT_CP_BIAS_8822B) & BIT_MASK_CP_BIAS_8822B)
+#define BIT_CP_BIAS_8822B(x) \
+ (((x) & BIT_MASK_CP_BIAS_8822B) << BIT_SHIFT_CP_BIAS_8822B)
+#define BITS_CP_BIAS_8822B (BIT_MASK_CP_BIAS_8822B << BIT_SHIFT_CP_BIAS_8822B)
+#define BIT_CLEAR_CP_BIAS_8822B(x) ((x) & (~BITS_CP_BIAS_8822B))
+#define BIT_GET_CP_BIAS_8822B(x) \
+ (((x) >> BIT_SHIFT_CP_BIAS_8822B) & BIT_MASK_CP_BIAS_8822B)
+#define BIT_SET_CP_BIAS_8822B(x, v) \
+ (BIT_CLEAR_CP_BIAS_8822B(x) | BIT_CP_BIAS_8822B(v))
#define BIT_REG_IDOUBLE_V2_8822B BIT(17)
#define BIT_EN_SYN_8822B BIT(16)
@@ -387,27 +609,50 @@
#define BIT_SHIFT_MCCO_8822B 14
#define BIT_MASK_MCCO_8822B 0x3
#define BIT_MCCO_8822B(x) (((x) & BIT_MASK_MCCO_8822B) << BIT_SHIFT_MCCO_8822B)
-#define BIT_GET_MCCO_8822B(x) (((x) >> BIT_SHIFT_MCCO_8822B) & BIT_MASK_MCCO_8822B)
-
+#define BITS_MCCO_8822B (BIT_MASK_MCCO_8822B << BIT_SHIFT_MCCO_8822B)
+#define BIT_CLEAR_MCCO_8822B(x) ((x) & (~BITS_MCCO_8822B))
+#define BIT_GET_MCCO_8822B(x) \
+ (((x) >> BIT_SHIFT_MCCO_8822B) & BIT_MASK_MCCO_8822B)
+#define BIT_SET_MCCO_8822B(x, v) (BIT_CLEAR_MCCO_8822B(x) | BIT_MCCO_8822B(v))
#define BIT_SHIFT_REG_LDO_SEL_8822B 12
#define BIT_MASK_REG_LDO_SEL_8822B 0x3
-#define BIT_REG_LDO_SEL_8822B(x) (((x) & BIT_MASK_REG_LDO_SEL_8822B) << BIT_SHIFT_REG_LDO_SEL_8822B)
-#define BIT_GET_REG_LDO_SEL_8822B(x) (((x) >> BIT_SHIFT_REG_LDO_SEL_8822B) & BIT_MASK_REG_LDO_SEL_8822B)
+#define BIT_REG_LDO_SEL_8822B(x) \
+ (((x) & BIT_MASK_REG_LDO_SEL_8822B) << BIT_SHIFT_REG_LDO_SEL_8822B)
+#define BITS_REG_LDO_SEL_8822B \
+ (BIT_MASK_REG_LDO_SEL_8822B << BIT_SHIFT_REG_LDO_SEL_8822B)
+#define BIT_CLEAR_REG_LDO_SEL_8822B(x) ((x) & (~BITS_REG_LDO_SEL_8822B))
+#define BIT_GET_REG_LDO_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_REG_LDO_SEL_8822B) & BIT_MASK_REG_LDO_SEL_8822B)
+#define BIT_SET_REG_LDO_SEL_8822B(x, v) \
+ (BIT_CLEAR_REG_LDO_SEL_8822B(x) | BIT_REG_LDO_SEL_8822B(v))
#define BIT_REG_KVCO_V2_8822B BIT(10)
#define BIT_AGPIO_GPO_8822B BIT(9)
#define BIT_SHIFT_AGPIO_DRV_8822B 7
#define BIT_MASK_AGPIO_DRV_8822B 0x3
-#define BIT_AGPIO_DRV_8822B(x) (((x) & BIT_MASK_AGPIO_DRV_8822B) << BIT_SHIFT_AGPIO_DRV_8822B)
-#define BIT_GET_AGPIO_DRV_8822B(x) (((x) >> BIT_SHIFT_AGPIO_DRV_8822B) & BIT_MASK_AGPIO_DRV_8822B)
-
+#define BIT_AGPIO_DRV_8822B(x) \
+ (((x) & BIT_MASK_AGPIO_DRV_8822B) << BIT_SHIFT_AGPIO_DRV_8822B)
+#define BITS_AGPIO_DRV_8822B \
+ (BIT_MASK_AGPIO_DRV_8822B << BIT_SHIFT_AGPIO_DRV_8822B)
+#define BIT_CLEAR_AGPIO_DRV_8822B(x) ((x) & (~BITS_AGPIO_DRV_8822B))
+#define BIT_GET_AGPIO_DRV_8822B(x) \
+ (((x) >> BIT_SHIFT_AGPIO_DRV_8822B) & BIT_MASK_AGPIO_DRV_8822B)
+#define BIT_SET_AGPIO_DRV_8822B(x, v) \
+ (BIT_CLEAR_AGPIO_DRV_8822B(x) | BIT_AGPIO_DRV_8822B(v))
#define BIT_SHIFT_XTAL_CAP_XO_8822B 1
#define BIT_MASK_XTAL_CAP_XO_8822B 0x3f
-#define BIT_XTAL_CAP_XO_8822B(x) (((x) & BIT_MASK_XTAL_CAP_XO_8822B) << BIT_SHIFT_XTAL_CAP_XO_8822B)
-#define BIT_GET_XTAL_CAP_XO_8822B(x) (((x) >> BIT_SHIFT_XTAL_CAP_XO_8822B) & BIT_MASK_XTAL_CAP_XO_8822B)
+#define BIT_XTAL_CAP_XO_8822B(x) \
+ (((x) & BIT_MASK_XTAL_CAP_XO_8822B) << BIT_SHIFT_XTAL_CAP_XO_8822B)
+#define BITS_XTAL_CAP_XO_8822B \
+ (BIT_MASK_XTAL_CAP_XO_8822B << BIT_SHIFT_XTAL_CAP_XO_8822B)
+#define BIT_CLEAR_XTAL_CAP_XO_8822B(x) ((x) & (~BITS_XTAL_CAP_XO_8822B))
+#define BIT_GET_XTAL_CAP_XO_8822B(x) \
+ (((x) >> BIT_SHIFT_XTAL_CAP_XO_8822B) & BIT_MASK_XTAL_CAP_XO_8822B)
+#define BIT_SET_XTAL_CAP_XO_8822B(x, v) \
+ (BIT_CLEAR_XTAL_CAP_XO_8822B(x) | BIT_XTAL_CAP_XO_8822B(v))
#define BIT_POW_PLL_8822B BIT(0)
@@ -416,7 +661,10 @@
#define BIT_SHIFT_PS_8822B 7
#define BIT_MASK_PS_8822B 0x7
#define BIT_PS_8822B(x) (((x) & BIT_MASK_PS_8822B) << BIT_SHIFT_PS_8822B)
+#define BITS_PS_8822B (BIT_MASK_PS_8822B << BIT_SHIFT_PS_8822B)
+#define BIT_CLEAR_PS_8822B(x) ((x) & (~BITS_PS_8822B))
#define BIT_GET_PS_8822B(x) (((x) >> BIT_SHIFT_PS_8822B) & BIT_MASK_PS_8822B)
+#define BIT_SET_PS_8822B(x, v) (BIT_CLEAR_PS_8822B(x) | BIT_PS_8822B(v))
#define BIT_PSEN_8822B BIT(6)
#define BIT_DOGENB_8822B BIT(5)
@@ -424,8 +672,15 @@
#define BIT_SHIFT_REG_R3_V4_8822B 1
#define BIT_MASK_REG_R3_V4_8822B 0x7
-#define BIT_REG_R3_V4_8822B(x) (((x) & BIT_MASK_REG_R3_V4_8822B) << BIT_SHIFT_REG_R3_V4_8822B)
-#define BIT_GET_REG_R3_V4_8822B(x) (((x) >> BIT_SHIFT_REG_R3_V4_8822B) & BIT_MASK_REG_R3_V4_8822B)
+#define BIT_REG_R3_V4_8822B(x) \
+ (((x) & BIT_MASK_REG_R3_V4_8822B) << BIT_SHIFT_REG_R3_V4_8822B)
+#define BITS_REG_R3_V4_8822B \
+ (BIT_MASK_REG_R3_V4_8822B << BIT_SHIFT_REG_R3_V4_8822B)
+#define BIT_CLEAR_REG_R3_V4_8822B(x) ((x) & (~BITS_REG_R3_V4_8822B))
+#define BIT_GET_REG_R3_V4_8822B(x) \
+ (((x) >> BIT_SHIFT_REG_R3_V4_8822B) & BIT_MASK_REG_R3_V4_8822B)
+#define BIT_SET_REG_R3_V4_8822B(x, v) \
+ (BIT_CLEAR_REG_R3_V4_8822B(x) | BIT_REG_R3_V4_8822B(v))
#define BIT_REG_CP_BIT0_8822B BIT(0)
@@ -434,90 +689,172 @@
#define BIT_SHIFT_EF_PGPD_8822B 28
#define BIT_MASK_EF_PGPD_8822B 0x7
-#define BIT_EF_PGPD_8822B(x) (((x) & BIT_MASK_EF_PGPD_8822B) << BIT_SHIFT_EF_PGPD_8822B)
-#define BIT_GET_EF_PGPD_8822B(x) (((x) >> BIT_SHIFT_EF_PGPD_8822B) & BIT_MASK_EF_PGPD_8822B)
-
+#define BIT_EF_PGPD_8822B(x) \
+ (((x) & BIT_MASK_EF_PGPD_8822B) << BIT_SHIFT_EF_PGPD_8822B)
+#define BITS_EF_PGPD_8822B (BIT_MASK_EF_PGPD_8822B << BIT_SHIFT_EF_PGPD_8822B)
+#define BIT_CLEAR_EF_PGPD_8822B(x) ((x) & (~BITS_EF_PGPD_8822B))
+#define BIT_GET_EF_PGPD_8822B(x) \
+ (((x) >> BIT_SHIFT_EF_PGPD_8822B) & BIT_MASK_EF_PGPD_8822B)
+#define BIT_SET_EF_PGPD_8822B(x, v) \
+ (BIT_CLEAR_EF_PGPD_8822B(x) | BIT_EF_PGPD_8822B(v))
#define BIT_SHIFT_EF_RDT_8822B 24
#define BIT_MASK_EF_RDT_8822B 0xf
-#define BIT_EF_RDT_8822B(x) (((x) & BIT_MASK_EF_RDT_8822B) << BIT_SHIFT_EF_RDT_8822B)
-#define BIT_GET_EF_RDT_8822B(x) (((x) >> BIT_SHIFT_EF_RDT_8822B) & BIT_MASK_EF_RDT_8822B)
-
+#define BIT_EF_RDT_8822B(x) \
+ (((x) & BIT_MASK_EF_RDT_8822B) << BIT_SHIFT_EF_RDT_8822B)
+#define BITS_EF_RDT_8822B (BIT_MASK_EF_RDT_8822B << BIT_SHIFT_EF_RDT_8822B)
+#define BIT_CLEAR_EF_RDT_8822B(x) ((x) & (~BITS_EF_RDT_8822B))
+#define BIT_GET_EF_RDT_8822B(x) \
+ (((x) >> BIT_SHIFT_EF_RDT_8822B) & BIT_MASK_EF_RDT_8822B)
+#define BIT_SET_EF_RDT_8822B(x, v) \
+ (BIT_CLEAR_EF_RDT_8822B(x) | BIT_EF_RDT_8822B(v))
#define BIT_SHIFT_EF_PGTS_8822B 20
#define BIT_MASK_EF_PGTS_8822B 0xf
-#define BIT_EF_PGTS_8822B(x) (((x) & BIT_MASK_EF_PGTS_8822B) << BIT_SHIFT_EF_PGTS_8822B)
-#define BIT_GET_EF_PGTS_8822B(x) (((x) >> BIT_SHIFT_EF_PGTS_8822B) & BIT_MASK_EF_PGTS_8822B)
+#define BIT_EF_PGTS_8822B(x) \
+ (((x) & BIT_MASK_EF_PGTS_8822B) << BIT_SHIFT_EF_PGTS_8822B)
+#define BITS_EF_PGTS_8822B (BIT_MASK_EF_PGTS_8822B << BIT_SHIFT_EF_PGTS_8822B)
+#define BIT_CLEAR_EF_PGTS_8822B(x) ((x) & (~BITS_EF_PGTS_8822B))
+#define BIT_GET_EF_PGTS_8822B(x) \
+ (((x) >> BIT_SHIFT_EF_PGTS_8822B) & BIT_MASK_EF_PGTS_8822B)
+#define BIT_SET_EF_PGTS_8822B(x, v) \
+ (BIT_CLEAR_EF_PGTS_8822B(x) | BIT_EF_PGTS_8822B(v))
#define BIT_EF_PDWN_8822B BIT(19)
#define BIT_EF_ALDEN_8822B BIT(18)
#define BIT_SHIFT_EF_ADDR_8822B 8
#define BIT_MASK_EF_ADDR_8822B 0x3ff
-#define BIT_EF_ADDR_8822B(x) (((x) & BIT_MASK_EF_ADDR_8822B) << BIT_SHIFT_EF_ADDR_8822B)
-#define BIT_GET_EF_ADDR_8822B(x) (((x) >> BIT_SHIFT_EF_ADDR_8822B) & BIT_MASK_EF_ADDR_8822B)
-
+#define BIT_EF_ADDR_8822B(x) \
+ (((x) & BIT_MASK_EF_ADDR_8822B) << BIT_SHIFT_EF_ADDR_8822B)
+#define BITS_EF_ADDR_8822B (BIT_MASK_EF_ADDR_8822B << BIT_SHIFT_EF_ADDR_8822B)
+#define BIT_CLEAR_EF_ADDR_8822B(x) ((x) & (~BITS_EF_ADDR_8822B))
+#define BIT_GET_EF_ADDR_8822B(x) \
+ (((x) >> BIT_SHIFT_EF_ADDR_8822B) & BIT_MASK_EF_ADDR_8822B)
+#define BIT_SET_EF_ADDR_8822B(x, v) \
+ (BIT_CLEAR_EF_ADDR_8822B(x) | BIT_EF_ADDR_8822B(v))
#define BIT_SHIFT_EF_DATA_8822B 0
#define BIT_MASK_EF_DATA_8822B 0xff
-#define BIT_EF_DATA_8822B(x) (((x) & BIT_MASK_EF_DATA_8822B) << BIT_SHIFT_EF_DATA_8822B)
-#define BIT_GET_EF_DATA_8822B(x) (((x) >> BIT_SHIFT_EF_DATA_8822B) & BIT_MASK_EF_DATA_8822B)
-
+#define BIT_EF_DATA_8822B(x) \
+ (((x) & BIT_MASK_EF_DATA_8822B) << BIT_SHIFT_EF_DATA_8822B)
+#define BITS_EF_DATA_8822B (BIT_MASK_EF_DATA_8822B << BIT_SHIFT_EF_DATA_8822B)
+#define BIT_CLEAR_EF_DATA_8822B(x) ((x) & (~BITS_EF_DATA_8822B))
+#define BIT_GET_EF_DATA_8822B(x) \
+ (((x) >> BIT_SHIFT_EF_DATA_8822B) & BIT_MASK_EF_DATA_8822B)
+#define BIT_SET_EF_DATA_8822B(x, v) \
+ (BIT_CLEAR_EF_DATA_8822B(x) | BIT_EF_DATA_8822B(v))
/* 2 REG_LDO_EFUSE_CTRL_8822B */
#define BIT_LDOE25_EN_8822B BIT(31)
#define BIT_SHIFT_LDOE25_V12ADJ_L_8822B 27
#define BIT_MASK_LDOE25_V12ADJ_L_8822B 0xf
-#define BIT_LDOE25_V12ADJ_L_8822B(x) (((x) & BIT_MASK_LDOE25_V12ADJ_L_8822B) << BIT_SHIFT_LDOE25_V12ADJ_L_8822B)
-#define BIT_GET_LDOE25_V12ADJ_L_8822B(x) (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_8822B) & BIT_MASK_LDOE25_V12ADJ_L_8822B)
+#define BIT_LDOE25_V12ADJ_L_8822B(x) \
+ (((x) & BIT_MASK_LDOE25_V12ADJ_L_8822B) \
+ << BIT_SHIFT_LDOE25_V12ADJ_L_8822B)
+#define BITS_LDOE25_V12ADJ_L_8822B \
+ (BIT_MASK_LDOE25_V12ADJ_L_8822B << BIT_SHIFT_LDOE25_V12ADJ_L_8822B)
+#define BIT_CLEAR_LDOE25_V12ADJ_L_8822B(x) ((x) & (~BITS_LDOE25_V12ADJ_L_8822B))
+#define BIT_GET_LDOE25_V12ADJ_L_8822B(x) \
+ (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_8822B) & \
+ BIT_MASK_LDOE25_V12ADJ_L_8822B)
+#define BIT_SET_LDOE25_V12ADJ_L_8822B(x, v) \
+ (BIT_CLEAR_LDOE25_V12ADJ_L_8822B(x) | BIT_LDOE25_V12ADJ_L_8822B(v))
#define BIT_EF_CRES_SEL_8822B BIT(26)
#define BIT_SHIFT_EF_SCAN_START_V1_8822B 16
#define BIT_MASK_EF_SCAN_START_V1_8822B 0x3ff
-#define BIT_EF_SCAN_START_V1_8822B(x) (((x) & BIT_MASK_EF_SCAN_START_V1_8822B) << BIT_SHIFT_EF_SCAN_START_V1_8822B)
-#define BIT_GET_EF_SCAN_START_V1_8822B(x) (((x) >> BIT_SHIFT_EF_SCAN_START_V1_8822B) & BIT_MASK_EF_SCAN_START_V1_8822B)
-
+#define BIT_EF_SCAN_START_V1_8822B(x) \
+ (((x) & BIT_MASK_EF_SCAN_START_V1_8822B) \
+ << BIT_SHIFT_EF_SCAN_START_V1_8822B)
+#define BITS_EF_SCAN_START_V1_8822B \
+ (BIT_MASK_EF_SCAN_START_V1_8822B << BIT_SHIFT_EF_SCAN_START_V1_8822B)
+#define BIT_CLEAR_EF_SCAN_START_V1_8822B(x) \
+ ((x) & (~BITS_EF_SCAN_START_V1_8822B))
+#define BIT_GET_EF_SCAN_START_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_EF_SCAN_START_V1_8822B) & \
+ BIT_MASK_EF_SCAN_START_V1_8822B)
+#define BIT_SET_EF_SCAN_START_V1_8822B(x, v) \
+ (BIT_CLEAR_EF_SCAN_START_V1_8822B(x) | BIT_EF_SCAN_START_V1_8822B(v))
#define BIT_SHIFT_EF_SCAN_END_8822B 12
#define BIT_MASK_EF_SCAN_END_8822B 0xf
-#define BIT_EF_SCAN_END_8822B(x) (((x) & BIT_MASK_EF_SCAN_END_8822B) << BIT_SHIFT_EF_SCAN_END_8822B)
-#define BIT_GET_EF_SCAN_END_8822B(x) (((x) >> BIT_SHIFT_EF_SCAN_END_8822B) & BIT_MASK_EF_SCAN_END_8822B)
+#define BIT_EF_SCAN_END_8822B(x) \
+ (((x) & BIT_MASK_EF_SCAN_END_8822B) << BIT_SHIFT_EF_SCAN_END_8822B)
+#define BITS_EF_SCAN_END_8822B \
+ (BIT_MASK_EF_SCAN_END_8822B << BIT_SHIFT_EF_SCAN_END_8822B)
+#define BIT_CLEAR_EF_SCAN_END_8822B(x) ((x) & (~BITS_EF_SCAN_END_8822B))
+#define BIT_GET_EF_SCAN_END_8822B(x) \
+ (((x) >> BIT_SHIFT_EF_SCAN_END_8822B) & BIT_MASK_EF_SCAN_END_8822B)
+#define BIT_SET_EF_SCAN_END_8822B(x, v) \
+ (BIT_CLEAR_EF_SCAN_END_8822B(x) | BIT_EF_SCAN_END_8822B(v))
#define BIT_EF_PD_DIS_8822B BIT(11)
#define BIT_SHIFT_EF_CELL_SEL_8822B 8
#define BIT_MASK_EF_CELL_SEL_8822B 0x3
-#define BIT_EF_CELL_SEL_8822B(x) (((x) & BIT_MASK_EF_CELL_SEL_8822B) << BIT_SHIFT_EF_CELL_SEL_8822B)
-#define BIT_GET_EF_CELL_SEL_8822B(x) (((x) >> BIT_SHIFT_EF_CELL_SEL_8822B) & BIT_MASK_EF_CELL_SEL_8822B)
+#define BIT_EF_CELL_SEL_8822B(x) \
+ (((x) & BIT_MASK_EF_CELL_SEL_8822B) << BIT_SHIFT_EF_CELL_SEL_8822B)
+#define BITS_EF_CELL_SEL_8822B \
+ (BIT_MASK_EF_CELL_SEL_8822B << BIT_SHIFT_EF_CELL_SEL_8822B)
+#define BIT_CLEAR_EF_CELL_SEL_8822B(x) ((x) & (~BITS_EF_CELL_SEL_8822B))
+#define BIT_GET_EF_CELL_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_EF_CELL_SEL_8822B) & BIT_MASK_EF_CELL_SEL_8822B)
+#define BIT_SET_EF_CELL_SEL_8822B(x, v) \
+ (BIT_CLEAR_EF_CELL_SEL_8822B(x) | BIT_EF_CELL_SEL_8822B(v))
#define BIT_EF_TRPT_8822B BIT(7)
#define BIT_SHIFT_EF_TTHD_8822B 0
#define BIT_MASK_EF_TTHD_8822B 0x7f
-#define BIT_EF_TTHD_8822B(x) (((x) & BIT_MASK_EF_TTHD_8822B) << BIT_SHIFT_EF_TTHD_8822B)
-#define BIT_GET_EF_TTHD_8822B(x) (((x) >> BIT_SHIFT_EF_TTHD_8822B) & BIT_MASK_EF_TTHD_8822B)
-
+#define BIT_EF_TTHD_8822B(x) \
+ (((x) & BIT_MASK_EF_TTHD_8822B) << BIT_SHIFT_EF_TTHD_8822B)
+#define BITS_EF_TTHD_8822B (BIT_MASK_EF_TTHD_8822B << BIT_SHIFT_EF_TTHD_8822B)
+#define BIT_CLEAR_EF_TTHD_8822B(x) ((x) & (~BITS_EF_TTHD_8822B))
+#define BIT_GET_EF_TTHD_8822B(x) \
+ (((x) >> BIT_SHIFT_EF_TTHD_8822B) & BIT_MASK_EF_TTHD_8822B)
+#define BIT_SET_EF_TTHD_8822B(x, v) \
+ (BIT_CLEAR_EF_TTHD_8822B(x) | BIT_EF_TTHD_8822B(v))
/* 2 REG_PWR_OPTION_CTRL_8822B */
#define BIT_SHIFT_DBG_SEL_V1_8822B 16
#define BIT_MASK_DBG_SEL_V1_8822B 0xff
-#define BIT_DBG_SEL_V1_8822B(x) (((x) & BIT_MASK_DBG_SEL_V1_8822B) << BIT_SHIFT_DBG_SEL_V1_8822B)
-#define BIT_GET_DBG_SEL_V1_8822B(x) (((x) >> BIT_SHIFT_DBG_SEL_V1_8822B) & BIT_MASK_DBG_SEL_V1_8822B)
-
+#define BIT_DBG_SEL_V1_8822B(x) \
+ (((x) & BIT_MASK_DBG_SEL_V1_8822B) << BIT_SHIFT_DBG_SEL_V1_8822B)
+#define BITS_DBG_SEL_V1_8822B \
+ (BIT_MASK_DBG_SEL_V1_8822B << BIT_SHIFT_DBG_SEL_V1_8822B)
+#define BIT_CLEAR_DBG_SEL_V1_8822B(x) ((x) & (~BITS_DBG_SEL_V1_8822B))
+#define BIT_GET_DBG_SEL_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_DBG_SEL_V1_8822B) & BIT_MASK_DBG_SEL_V1_8822B)
+#define BIT_SET_DBG_SEL_V1_8822B(x, v) \
+ (BIT_CLEAR_DBG_SEL_V1_8822B(x) | BIT_DBG_SEL_V1_8822B(v))
#define BIT_SHIFT_DBG_SEL_BYTE_8822B 14
#define BIT_MASK_DBG_SEL_BYTE_8822B 0x3
-#define BIT_DBG_SEL_BYTE_8822B(x) (((x) & BIT_MASK_DBG_SEL_BYTE_8822B) << BIT_SHIFT_DBG_SEL_BYTE_8822B)
-#define BIT_GET_DBG_SEL_BYTE_8822B(x) (((x) >> BIT_SHIFT_DBG_SEL_BYTE_8822B) & BIT_MASK_DBG_SEL_BYTE_8822B)
-
+#define BIT_DBG_SEL_BYTE_8822B(x) \
+ (((x) & BIT_MASK_DBG_SEL_BYTE_8822B) << BIT_SHIFT_DBG_SEL_BYTE_8822B)
+#define BITS_DBG_SEL_BYTE_8822B \
+ (BIT_MASK_DBG_SEL_BYTE_8822B << BIT_SHIFT_DBG_SEL_BYTE_8822B)
+#define BIT_CLEAR_DBG_SEL_BYTE_8822B(x) ((x) & (~BITS_DBG_SEL_BYTE_8822B))
+#define BIT_GET_DBG_SEL_BYTE_8822B(x) \
+ (((x) >> BIT_SHIFT_DBG_SEL_BYTE_8822B) & BIT_MASK_DBG_SEL_BYTE_8822B)
+#define BIT_SET_DBG_SEL_BYTE_8822B(x, v) \
+ (BIT_CLEAR_DBG_SEL_BYTE_8822B(x) | BIT_DBG_SEL_BYTE_8822B(v))
#define BIT_SHIFT_STD_L1_V1_8822B 12
#define BIT_MASK_STD_L1_V1_8822B 0x3
-#define BIT_STD_L1_V1_8822B(x) (((x) & BIT_MASK_STD_L1_V1_8822B) << BIT_SHIFT_STD_L1_V1_8822B)
-#define BIT_GET_STD_L1_V1_8822B(x) (((x) >> BIT_SHIFT_STD_L1_V1_8822B) & BIT_MASK_STD_L1_V1_8822B)
+#define BIT_STD_L1_V1_8822B(x) \
+ (((x) & BIT_MASK_STD_L1_V1_8822B) << BIT_SHIFT_STD_L1_V1_8822B)
+#define BITS_STD_L1_V1_8822B \
+ (BIT_MASK_STD_L1_V1_8822B << BIT_SHIFT_STD_L1_V1_8822B)
+#define BIT_CLEAR_STD_L1_V1_8822B(x) ((x) & (~BITS_STD_L1_V1_8822B))
+#define BIT_GET_STD_L1_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_STD_L1_V1_8822B) & BIT_MASK_STD_L1_V1_8822B)
+#define BIT_SET_STD_L1_V1_8822B(x, v) \
+ (BIT_CLEAR_STD_L1_V1_8822B(x) | BIT_STD_L1_V1_8822B(v))
#define BIT_SYSON_DBG_PAD_E2_8822B BIT(11)
#define BIT_SYSON_LED_PAD_E2_8822B BIT(10)
@@ -527,49 +864,101 @@
#define BIT_SHIFT_SYSON_SPS0WWV_WT_8822B 4
#define BIT_MASK_SYSON_SPS0WWV_WT_8822B 0x3
-#define BIT_SYSON_SPS0WWV_WT_8822B(x) (((x) & BIT_MASK_SYSON_SPS0WWV_WT_8822B) << BIT_SHIFT_SYSON_SPS0WWV_WT_8822B)
-#define BIT_GET_SYSON_SPS0WWV_WT_8822B(x) (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8822B) & BIT_MASK_SYSON_SPS0WWV_WT_8822B)
-
+#define BIT_SYSON_SPS0WWV_WT_8822B(x) \
+ (((x) & BIT_MASK_SYSON_SPS0WWV_WT_8822B) \
+ << BIT_SHIFT_SYSON_SPS0WWV_WT_8822B)
+#define BITS_SYSON_SPS0WWV_WT_8822B \
+ (BIT_MASK_SYSON_SPS0WWV_WT_8822B << BIT_SHIFT_SYSON_SPS0WWV_WT_8822B)
+#define BIT_CLEAR_SYSON_SPS0WWV_WT_8822B(x) \
+ ((x) & (~BITS_SYSON_SPS0WWV_WT_8822B))
+#define BIT_GET_SYSON_SPS0WWV_WT_8822B(x) \
+ (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8822B) & \
+ BIT_MASK_SYSON_SPS0WWV_WT_8822B)
+#define BIT_SET_SYSON_SPS0WWV_WT_8822B(x, v) \
+ (BIT_CLEAR_SYSON_SPS0WWV_WT_8822B(x) | BIT_SYSON_SPS0WWV_WT_8822B(v))
#define BIT_SHIFT_SYSON_SPS0LDO_WT_8822B 2
#define BIT_MASK_SYSON_SPS0LDO_WT_8822B 0x3
-#define BIT_SYSON_SPS0LDO_WT_8822B(x) (((x) & BIT_MASK_SYSON_SPS0LDO_WT_8822B) << BIT_SHIFT_SYSON_SPS0LDO_WT_8822B)
-#define BIT_GET_SYSON_SPS0LDO_WT_8822B(x) (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8822B) & BIT_MASK_SYSON_SPS0LDO_WT_8822B)
-
+#define BIT_SYSON_SPS0LDO_WT_8822B(x) \
+ (((x) & BIT_MASK_SYSON_SPS0LDO_WT_8822B) \
+ << BIT_SHIFT_SYSON_SPS0LDO_WT_8822B)
+#define BITS_SYSON_SPS0LDO_WT_8822B \
+ (BIT_MASK_SYSON_SPS0LDO_WT_8822B << BIT_SHIFT_SYSON_SPS0LDO_WT_8822B)
+#define BIT_CLEAR_SYSON_SPS0LDO_WT_8822B(x) \
+ ((x) & (~BITS_SYSON_SPS0LDO_WT_8822B))
+#define BIT_GET_SYSON_SPS0LDO_WT_8822B(x) \
+ (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8822B) & \
+ BIT_MASK_SYSON_SPS0LDO_WT_8822B)
+#define BIT_SET_SYSON_SPS0LDO_WT_8822B(x, v) \
+ (BIT_CLEAR_SYSON_SPS0LDO_WT_8822B(x) | BIT_SYSON_SPS0LDO_WT_8822B(v))
#define BIT_SHIFT_SYSON_RCLK_SCALE_8822B 0
#define BIT_MASK_SYSON_RCLK_SCALE_8822B 0x3
-#define BIT_SYSON_RCLK_SCALE_8822B(x) (((x) & BIT_MASK_SYSON_RCLK_SCALE_8822B) << BIT_SHIFT_SYSON_RCLK_SCALE_8822B)
-#define BIT_GET_SYSON_RCLK_SCALE_8822B(x) (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8822B) & BIT_MASK_SYSON_RCLK_SCALE_8822B)
-
+#define BIT_SYSON_RCLK_SCALE_8822B(x) \
+ (((x) & BIT_MASK_SYSON_RCLK_SCALE_8822B) \
+ << BIT_SHIFT_SYSON_RCLK_SCALE_8822B)
+#define BITS_SYSON_RCLK_SCALE_8822B \
+ (BIT_MASK_SYSON_RCLK_SCALE_8822B << BIT_SHIFT_SYSON_RCLK_SCALE_8822B)
+#define BIT_CLEAR_SYSON_RCLK_SCALE_8822B(x) \
+ ((x) & (~BITS_SYSON_RCLK_SCALE_8822B))
+#define BIT_GET_SYSON_RCLK_SCALE_8822B(x) \
+ (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8822B) & \
+ BIT_MASK_SYSON_RCLK_SCALE_8822B)
+#define BIT_SET_SYSON_RCLK_SCALE_8822B(x, v) \
+ (BIT_CLEAR_SYSON_RCLK_SCALE_8822B(x) | BIT_SYSON_RCLK_SCALE_8822B(v))
/* 2 REG_CAL_TIMER_8822B */
#define BIT_SHIFT_MATCH_CNT_8822B 8
#define BIT_MASK_MATCH_CNT_8822B 0xff
-#define BIT_MATCH_CNT_8822B(x) (((x) & BIT_MASK_MATCH_CNT_8822B) << BIT_SHIFT_MATCH_CNT_8822B)
-#define BIT_GET_MATCH_CNT_8822B(x) (((x) >> BIT_SHIFT_MATCH_CNT_8822B) & BIT_MASK_MATCH_CNT_8822B)
-
+#define BIT_MATCH_CNT_8822B(x) \
+ (((x) & BIT_MASK_MATCH_CNT_8822B) << BIT_SHIFT_MATCH_CNT_8822B)
+#define BITS_MATCH_CNT_8822B \
+ (BIT_MASK_MATCH_CNT_8822B << BIT_SHIFT_MATCH_CNT_8822B)
+#define BIT_CLEAR_MATCH_CNT_8822B(x) ((x) & (~BITS_MATCH_CNT_8822B))
+#define BIT_GET_MATCH_CNT_8822B(x) \
+ (((x) >> BIT_SHIFT_MATCH_CNT_8822B) & BIT_MASK_MATCH_CNT_8822B)
+#define BIT_SET_MATCH_CNT_8822B(x, v) \
+ (BIT_CLEAR_MATCH_CNT_8822B(x) | BIT_MATCH_CNT_8822B(v))
#define BIT_SHIFT_CAL_SCAL_8822B 0
#define BIT_MASK_CAL_SCAL_8822B 0xff
-#define BIT_CAL_SCAL_8822B(x) (((x) & BIT_MASK_CAL_SCAL_8822B) << BIT_SHIFT_CAL_SCAL_8822B)
-#define BIT_GET_CAL_SCAL_8822B(x) (((x) >> BIT_SHIFT_CAL_SCAL_8822B) & BIT_MASK_CAL_SCAL_8822B)
-
+#define BIT_CAL_SCAL_8822B(x) \
+ (((x) & BIT_MASK_CAL_SCAL_8822B) << BIT_SHIFT_CAL_SCAL_8822B)
+#define BITS_CAL_SCAL_8822B \
+ (BIT_MASK_CAL_SCAL_8822B << BIT_SHIFT_CAL_SCAL_8822B)
+#define BIT_CLEAR_CAL_SCAL_8822B(x) ((x) & (~BITS_CAL_SCAL_8822B))
+#define BIT_GET_CAL_SCAL_8822B(x) \
+ (((x) >> BIT_SHIFT_CAL_SCAL_8822B) & BIT_MASK_CAL_SCAL_8822B)
+#define BIT_SET_CAL_SCAL_8822B(x, v) \
+ (BIT_CLEAR_CAL_SCAL_8822B(x) | BIT_CAL_SCAL_8822B(v))
/* 2 REG_ACLK_MON_8822B */
#define BIT_SHIFT_RCLK_MON_8822B 5
#define BIT_MASK_RCLK_MON_8822B 0x7ff
-#define BIT_RCLK_MON_8822B(x) (((x) & BIT_MASK_RCLK_MON_8822B) << BIT_SHIFT_RCLK_MON_8822B)
-#define BIT_GET_RCLK_MON_8822B(x) (((x) >> BIT_SHIFT_RCLK_MON_8822B) & BIT_MASK_RCLK_MON_8822B)
+#define BIT_RCLK_MON_8822B(x) \
+ (((x) & BIT_MASK_RCLK_MON_8822B) << BIT_SHIFT_RCLK_MON_8822B)
+#define BITS_RCLK_MON_8822B \
+ (BIT_MASK_RCLK_MON_8822B << BIT_SHIFT_RCLK_MON_8822B)
+#define BIT_CLEAR_RCLK_MON_8822B(x) ((x) & (~BITS_RCLK_MON_8822B))
+#define BIT_GET_RCLK_MON_8822B(x) \
+ (((x) >> BIT_SHIFT_RCLK_MON_8822B) & BIT_MASK_RCLK_MON_8822B)
+#define BIT_SET_RCLK_MON_8822B(x, v) \
+ (BIT_CLEAR_RCLK_MON_8822B(x) | BIT_RCLK_MON_8822B(v))
#define BIT_CAL_EN_8822B BIT(4)
#define BIT_SHIFT_DPSTU_8822B 2
#define BIT_MASK_DPSTU_8822B 0x3
-#define BIT_DPSTU_8822B(x) (((x) & BIT_MASK_DPSTU_8822B) << BIT_SHIFT_DPSTU_8822B)
-#define BIT_GET_DPSTU_8822B(x) (((x) >> BIT_SHIFT_DPSTU_8822B) & BIT_MASK_DPSTU_8822B)
+#define BIT_DPSTU_8822B(x) \
+ (((x) & BIT_MASK_DPSTU_8822B) << BIT_SHIFT_DPSTU_8822B)
+#define BITS_DPSTU_8822B (BIT_MASK_DPSTU_8822B << BIT_SHIFT_DPSTU_8822B)
+#define BIT_CLEAR_DPSTU_8822B(x) ((x) & (~BITS_DPSTU_8822B))
+#define BIT_GET_DPSTU_8822B(x) \
+ (((x) >> BIT_SHIFT_DPSTU_8822B) & BIT_MASK_DPSTU_8822B)
+#define BIT_SET_DPSTU_8822B(x, v) \
+ (BIT_CLEAR_DPSTU_8822B(x) | BIT_DPSTU_8822B(v))
#define BIT_SUS_16X_8822B BIT(1)
@@ -587,8 +976,14 @@
#define BIT_SHIFT_BTMODE_8822B 6
#define BIT_MASK_BTMODE_8822B 0x3
-#define BIT_BTMODE_8822B(x) (((x) & BIT_MASK_BTMODE_8822B) << BIT_SHIFT_BTMODE_8822B)
-#define BIT_GET_BTMODE_8822B(x) (((x) >> BIT_SHIFT_BTMODE_8822B) & BIT_MASK_BTMODE_8822B)
+#define BIT_BTMODE_8822B(x) \
+ (((x) & BIT_MASK_BTMODE_8822B) << BIT_SHIFT_BTMODE_8822B)
+#define BITS_BTMODE_8822B (BIT_MASK_BTMODE_8822B << BIT_SHIFT_BTMODE_8822B)
+#define BIT_CLEAR_BTMODE_8822B(x) ((x) & (~BITS_BTMODE_8822B))
+#define BIT_GET_BTMODE_8822B(x) \
+ (((x) >> BIT_SHIFT_BTMODE_8822B) & BIT_MASK_BTMODE_8822B)
+#define BIT_SET_BTMODE_8822B(x, v) \
+ (BIT_CLEAR_BTMODE_8822B(x) | BIT_BTMODE_8822B(v))
#define BIT_ENBT_8822B BIT(5)
#define BIT_EROM_EN_8822B BIT(4)
@@ -597,42 +992,89 @@
#define BIT_SHIFT_GPIOSEL_8822B 0
#define BIT_MASK_GPIOSEL_8822B 0x3
-#define BIT_GPIOSEL_8822B(x) (((x) & BIT_MASK_GPIOSEL_8822B) << BIT_SHIFT_GPIOSEL_8822B)
-#define BIT_GET_GPIOSEL_8822B(x) (((x) >> BIT_SHIFT_GPIOSEL_8822B) & BIT_MASK_GPIOSEL_8822B)
-
+#define BIT_GPIOSEL_8822B(x) \
+ (((x) & BIT_MASK_GPIOSEL_8822B) << BIT_SHIFT_GPIOSEL_8822B)
+#define BITS_GPIOSEL_8822B (BIT_MASK_GPIOSEL_8822B << BIT_SHIFT_GPIOSEL_8822B)
+#define BIT_CLEAR_GPIOSEL_8822B(x) ((x) & (~BITS_GPIOSEL_8822B))
+#define BIT_GET_GPIOSEL_8822B(x) \
+ (((x) >> BIT_SHIFT_GPIOSEL_8822B) & BIT_MASK_GPIOSEL_8822B)
+#define BIT_SET_GPIOSEL_8822B(x, v) \
+ (BIT_CLEAR_GPIOSEL_8822B(x) | BIT_GPIOSEL_8822B(v))
/* 2 REG_GPIO_PIN_CTRL_8822B */
#define BIT_SHIFT_GPIO_MOD_7_TO_0_8822B 24
#define BIT_MASK_GPIO_MOD_7_TO_0_8822B 0xff
-#define BIT_GPIO_MOD_7_TO_0_8822B(x) (((x) & BIT_MASK_GPIO_MOD_7_TO_0_8822B) << BIT_SHIFT_GPIO_MOD_7_TO_0_8822B)
-#define BIT_GET_GPIO_MOD_7_TO_0_8822B(x) (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8822B) & BIT_MASK_GPIO_MOD_7_TO_0_8822B)
-
+#define BIT_GPIO_MOD_7_TO_0_8822B(x) \
+ (((x) & BIT_MASK_GPIO_MOD_7_TO_0_8822B) \
+ << BIT_SHIFT_GPIO_MOD_7_TO_0_8822B)
+#define BITS_GPIO_MOD_7_TO_0_8822B \
+ (BIT_MASK_GPIO_MOD_7_TO_0_8822B << BIT_SHIFT_GPIO_MOD_7_TO_0_8822B)
+#define BIT_CLEAR_GPIO_MOD_7_TO_0_8822B(x) ((x) & (~BITS_GPIO_MOD_7_TO_0_8822B))
+#define BIT_GET_GPIO_MOD_7_TO_0_8822B(x) \
+ (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8822B) & \
+ BIT_MASK_GPIO_MOD_7_TO_0_8822B)
+#define BIT_SET_GPIO_MOD_7_TO_0_8822B(x, v) \
+ (BIT_CLEAR_GPIO_MOD_7_TO_0_8822B(x) | BIT_GPIO_MOD_7_TO_0_8822B(v))
#define BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822B 16
#define BIT_MASK_GPIO_IO_SEL_7_TO_0_8822B 0xff
-#define BIT_GPIO_IO_SEL_7_TO_0_8822B(x) (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8822B) << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822B)
-#define BIT_GET_GPIO_IO_SEL_7_TO_0_8822B(x) (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822B) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8822B)
-
+#define BIT_GPIO_IO_SEL_7_TO_0_8822B(x) \
+ (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8822B) \
+ << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822B)
+#define BITS_GPIO_IO_SEL_7_TO_0_8822B \
+ (BIT_MASK_GPIO_IO_SEL_7_TO_0_8822B \
+ << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822B)
+#define BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8822B(x) \
+ ((x) & (~BITS_GPIO_IO_SEL_7_TO_0_8822B))
+#define BIT_GET_GPIO_IO_SEL_7_TO_0_8822B(x) \
+ (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822B) & \
+ BIT_MASK_GPIO_IO_SEL_7_TO_0_8822B)
+#define BIT_SET_GPIO_IO_SEL_7_TO_0_8822B(x, v) \
+ (BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8822B(x) | \
+ BIT_GPIO_IO_SEL_7_TO_0_8822B(v))
#define BIT_SHIFT_GPIO_OUT_7_TO_0_8822B 8
#define BIT_MASK_GPIO_OUT_7_TO_0_8822B 0xff
-#define BIT_GPIO_OUT_7_TO_0_8822B(x) (((x) & BIT_MASK_GPIO_OUT_7_TO_0_8822B) << BIT_SHIFT_GPIO_OUT_7_TO_0_8822B)
-#define BIT_GET_GPIO_OUT_7_TO_0_8822B(x) (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8822B) & BIT_MASK_GPIO_OUT_7_TO_0_8822B)
-
+#define BIT_GPIO_OUT_7_TO_0_8822B(x) \
+ (((x) & BIT_MASK_GPIO_OUT_7_TO_0_8822B) \
+ << BIT_SHIFT_GPIO_OUT_7_TO_0_8822B)
+#define BITS_GPIO_OUT_7_TO_0_8822B \
+ (BIT_MASK_GPIO_OUT_7_TO_0_8822B << BIT_SHIFT_GPIO_OUT_7_TO_0_8822B)
+#define BIT_CLEAR_GPIO_OUT_7_TO_0_8822B(x) ((x) & (~BITS_GPIO_OUT_7_TO_0_8822B))
+#define BIT_GET_GPIO_OUT_7_TO_0_8822B(x) \
+ (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8822B) & \
+ BIT_MASK_GPIO_OUT_7_TO_0_8822B)
+#define BIT_SET_GPIO_OUT_7_TO_0_8822B(x, v) \
+ (BIT_CLEAR_GPIO_OUT_7_TO_0_8822B(x) | BIT_GPIO_OUT_7_TO_0_8822B(v))
#define BIT_SHIFT_GPIO_IN_7_TO_0_8822B 0
#define BIT_MASK_GPIO_IN_7_TO_0_8822B 0xff
-#define BIT_GPIO_IN_7_TO_0_8822B(x) (((x) & BIT_MASK_GPIO_IN_7_TO_0_8822B) << BIT_SHIFT_GPIO_IN_7_TO_0_8822B)
-#define BIT_GET_GPIO_IN_7_TO_0_8822B(x) (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8822B) & BIT_MASK_GPIO_IN_7_TO_0_8822B)
-
+#define BIT_GPIO_IN_7_TO_0_8822B(x) \
+ (((x) & BIT_MASK_GPIO_IN_7_TO_0_8822B) \
+ << BIT_SHIFT_GPIO_IN_7_TO_0_8822B)
+#define BITS_GPIO_IN_7_TO_0_8822B \
+ (BIT_MASK_GPIO_IN_7_TO_0_8822B << BIT_SHIFT_GPIO_IN_7_TO_0_8822B)
+#define BIT_CLEAR_GPIO_IN_7_TO_0_8822B(x) ((x) & (~BITS_GPIO_IN_7_TO_0_8822B))
+#define BIT_GET_GPIO_IN_7_TO_0_8822B(x) \
+ (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8822B) & \
+ BIT_MASK_GPIO_IN_7_TO_0_8822B)
+#define BIT_SET_GPIO_IN_7_TO_0_8822B(x, v) \
+ (BIT_CLEAR_GPIO_IN_7_TO_0_8822B(x) | BIT_GPIO_IN_7_TO_0_8822B(v))
/* 2 REG_GPIO_INTM_8822B */
#define BIT_SHIFT_MUXDBG_SEL_8822B 30
#define BIT_MASK_MUXDBG_SEL_8822B 0x3
-#define BIT_MUXDBG_SEL_8822B(x) (((x) & BIT_MASK_MUXDBG_SEL_8822B) << BIT_SHIFT_MUXDBG_SEL_8822B)
-#define BIT_GET_MUXDBG_SEL_8822B(x) (((x) >> BIT_SHIFT_MUXDBG_SEL_8822B) & BIT_MASK_MUXDBG_SEL_8822B)
+#define BIT_MUXDBG_SEL_8822B(x) \
+ (((x) & BIT_MASK_MUXDBG_SEL_8822B) << BIT_SHIFT_MUXDBG_SEL_8822B)
+#define BITS_MUXDBG_SEL_8822B \
+ (BIT_MASK_MUXDBG_SEL_8822B << BIT_SHIFT_MUXDBG_SEL_8822B)
+#define BIT_CLEAR_MUXDBG_SEL_8822B(x) ((x) & (~BITS_MUXDBG_SEL_8822B))
+#define BIT_GET_MUXDBG_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_MUXDBG_SEL_8822B) & BIT_MASK_MUXDBG_SEL_8822B)
+#define BIT_SET_MUXDBG_SEL_8822B(x, v) \
+ (BIT_CLEAR_MUXDBG_SEL_8822B(x) | BIT_MUXDBG_SEL_8822B(v))
#define BIT_EXTWOL_SEL_8822B BIT(17)
#define BIT_EXTWOL_EN_8822B BIT(16)
@@ -670,8 +1112,14 @@
#define BIT_SHIFT_LED2CM_8822B 16
#define BIT_MASK_LED2CM_8822B 0x7
-#define BIT_LED2CM_8822B(x) (((x) & BIT_MASK_LED2CM_8822B) << BIT_SHIFT_LED2CM_8822B)
-#define BIT_GET_LED2CM_8822B(x) (((x) >> BIT_SHIFT_LED2CM_8822B) & BIT_MASK_LED2CM_8822B)
+#define BIT_LED2CM_8822B(x) \
+ (((x) & BIT_MASK_LED2CM_8822B) << BIT_SHIFT_LED2CM_8822B)
+#define BITS_LED2CM_8822B (BIT_MASK_LED2CM_8822B << BIT_SHIFT_LED2CM_8822B)
+#define BIT_CLEAR_LED2CM_8822B(x) ((x) & (~BITS_LED2CM_8822B))
+#define BIT_GET_LED2CM_8822B(x) \
+ (((x) >> BIT_SHIFT_LED2CM_8822B) & BIT_MASK_LED2CM_8822B)
+#define BIT_SET_LED2CM_8822B(x, v) \
+ (BIT_CLEAR_LED2CM_8822B(x) | BIT_LED2CM_8822B(v))
#define BIT_LED1DIS_8822B BIT(15)
#define BIT_LED1PL_8822B BIT(12)
@@ -679,24 +1127,45 @@
#define BIT_SHIFT_LED1CM_8822B 8
#define BIT_MASK_LED1CM_8822B 0x7
-#define BIT_LED1CM_8822B(x) (((x) & BIT_MASK_LED1CM_8822B) << BIT_SHIFT_LED1CM_8822B)
-#define BIT_GET_LED1CM_8822B(x) (((x) >> BIT_SHIFT_LED1CM_8822B) & BIT_MASK_LED1CM_8822B)
+#define BIT_LED1CM_8822B(x) \
+ (((x) & BIT_MASK_LED1CM_8822B) << BIT_SHIFT_LED1CM_8822B)
+#define BITS_LED1CM_8822B (BIT_MASK_LED1CM_8822B << BIT_SHIFT_LED1CM_8822B)
+#define BIT_CLEAR_LED1CM_8822B(x) ((x) & (~BITS_LED1CM_8822B))
+#define BIT_GET_LED1CM_8822B(x) \
+ (((x) >> BIT_SHIFT_LED1CM_8822B) & BIT_MASK_LED1CM_8822B)
+#define BIT_SET_LED1CM_8822B(x, v) \
+ (BIT_CLEAR_LED1CM_8822B(x) | BIT_LED1CM_8822B(v))
#define BIT_LED0DIS_8822B BIT(7)
#define BIT_SHIFT_AFE_LDO_SWR_CHECK_8822B 5
#define BIT_MASK_AFE_LDO_SWR_CHECK_8822B 0x3
-#define BIT_AFE_LDO_SWR_CHECK_8822B(x) (((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8822B) << BIT_SHIFT_AFE_LDO_SWR_CHECK_8822B)
-#define BIT_GET_AFE_LDO_SWR_CHECK_8822B(x) (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8822B) & BIT_MASK_AFE_LDO_SWR_CHECK_8822B)
+#define BIT_AFE_LDO_SWR_CHECK_8822B(x) \
+ (((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8822B) \
+ << BIT_SHIFT_AFE_LDO_SWR_CHECK_8822B)
+#define BITS_AFE_LDO_SWR_CHECK_8822B \
+ (BIT_MASK_AFE_LDO_SWR_CHECK_8822B << BIT_SHIFT_AFE_LDO_SWR_CHECK_8822B)
+#define BIT_CLEAR_AFE_LDO_SWR_CHECK_8822B(x) \
+ ((x) & (~BITS_AFE_LDO_SWR_CHECK_8822B))
+#define BIT_GET_AFE_LDO_SWR_CHECK_8822B(x) \
+ (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8822B) & \
+ BIT_MASK_AFE_LDO_SWR_CHECK_8822B)
+#define BIT_SET_AFE_LDO_SWR_CHECK_8822B(x, v) \
+ (BIT_CLEAR_AFE_LDO_SWR_CHECK_8822B(x) | BIT_AFE_LDO_SWR_CHECK_8822B(v))
#define BIT_LED0PL_8822B BIT(4)
#define BIT_LED0SV_8822B BIT(3)
#define BIT_SHIFT_LED0CM_8822B 0
#define BIT_MASK_LED0CM_8822B 0x7
-#define BIT_LED0CM_8822B(x) (((x) & BIT_MASK_LED0CM_8822B) << BIT_SHIFT_LED0CM_8822B)
-#define BIT_GET_LED0CM_8822B(x) (((x) >> BIT_SHIFT_LED0CM_8822B) & BIT_MASK_LED0CM_8822B)
-
+#define BIT_LED0CM_8822B(x) \
+ (((x) & BIT_MASK_LED0CM_8822B) << BIT_SHIFT_LED0CM_8822B)
+#define BITS_LED0CM_8822B (BIT_MASK_LED0CM_8822B << BIT_SHIFT_LED0CM_8822B)
+#define BIT_CLEAR_LED0CM_8822B(x) ((x) & (~BITS_LED0CM_8822B))
+#define BIT_GET_LED0CM_8822B(x) \
+ (((x) >> BIT_SHIFT_LED0CM_8822B) & BIT_MASK_LED0CM_8822B)
+#define BIT_SET_LED0CM_8822B(x, v) \
+ (BIT_CLEAR_LED0CM_8822B(x) | BIT_LED0CM_8822B(v))
/* 2 REG_FSIMR_8822B */
#define BIT_FS_PDNINT_EN_8822B BIT(31)
@@ -776,7 +1245,7 @@
#define BIT_GPIO5_INT_EN_8822B BIT(21)
#define BIT_GPIO4_INT_EN_8822B BIT(20)
#define BIT_GPIO3_INT_EN_8822B BIT(19)
-#define BIT_GPIO2_INT_EN_V1_8822B BIT(16)
+#define BIT_GPIO2_INT_EN_V1_8822B BIT(18)
#define BIT_GPIO1_INT_EN_8822B BIT(17)
#define BIT_GPIO0_INT_EN_8822B BIT(16)
#define BIT_PDNINT_EN_8822B BIT(7)
@@ -798,7 +1267,7 @@
#define BIT_GPIO5_INT_8822B BIT(21)
#define BIT_GPIO4_INT_8822B BIT(20)
#define BIT_GPIO3_INT_8822B BIT(19)
-#define BIT_GPIO2_INT_V1_8822B BIT(16)
+#define BIT_GPIO2_INT_V1_8822B BIT(18)
#define BIT_GPIO1_INT_8822B BIT(17)
#define BIT_GPIO0_INT_8822B BIT(16)
#define BIT_PDNINT_8822B BIT(7)
@@ -810,27 +1279,64 @@
#define BIT_SHIFT_GPIO_MOD_15_TO_8_8822B 24
#define BIT_MASK_GPIO_MOD_15_TO_8_8822B 0xff
-#define BIT_GPIO_MOD_15_TO_8_8822B(x) (((x) & BIT_MASK_GPIO_MOD_15_TO_8_8822B) << BIT_SHIFT_GPIO_MOD_15_TO_8_8822B)
-#define BIT_GET_GPIO_MOD_15_TO_8_8822B(x) (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8822B) & BIT_MASK_GPIO_MOD_15_TO_8_8822B)
-
+#define BIT_GPIO_MOD_15_TO_8_8822B(x) \
+ (((x) & BIT_MASK_GPIO_MOD_15_TO_8_8822B) \
+ << BIT_SHIFT_GPIO_MOD_15_TO_8_8822B)
+#define BITS_GPIO_MOD_15_TO_8_8822B \
+ (BIT_MASK_GPIO_MOD_15_TO_8_8822B << BIT_SHIFT_GPIO_MOD_15_TO_8_8822B)
+#define BIT_CLEAR_GPIO_MOD_15_TO_8_8822B(x) \
+ ((x) & (~BITS_GPIO_MOD_15_TO_8_8822B))
+#define BIT_GET_GPIO_MOD_15_TO_8_8822B(x) \
+ (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8822B) & \
+ BIT_MASK_GPIO_MOD_15_TO_8_8822B)
+#define BIT_SET_GPIO_MOD_15_TO_8_8822B(x, v) \
+ (BIT_CLEAR_GPIO_MOD_15_TO_8_8822B(x) | BIT_GPIO_MOD_15_TO_8_8822B(v))
#define BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822B 16
#define BIT_MASK_GPIO_IO_SEL_15_TO_8_8822B 0xff
-#define BIT_GPIO_IO_SEL_15_TO_8_8822B(x) (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8822B) << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822B)
-#define BIT_GET_GPIO_IO_SEL_15_TO_8_8822B(x) (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822B) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8822B)
-
+#define BIT_GPIO_IO_SEL_15_TO_8_8822B(x) \
+ (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8822B) \
+ << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822B)
+#define BITS_GPIO_IO_SEL_15_TO_8_8822B \
+ (BIT_MASK_GPIO_IO_SEL_15_TO_8_8822B \
+ << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822B)
+#define BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8822B(x) \
+ ((x) & (~BITS_GPIO_IO_SEL_15_TO_8_8822B))
+#define BIT_GET_GPIO_IO_SEL_15_TO_8_8822B(x) \
+ (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822B) & \
+ BIT_MASK_GPIO_IO_SEL_15_TO_8_8822B)
+#define BIT_SET_GPIO_IO_SEL_15_TO_8_8822B(x, v) \
+ (BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8822B(x) | \
+ BIT_GPIO_IO_SEL_15_TO_8_8822B(v))
#define BIT_SHIFT_GPIO_OUT_15_TO_8_8822B 8
#define BIT_MASK_GPIO_OUT_15_TO_8_8822B 0xff
-#define BIT_GPIO_OUT_15_TO_8_8822B(x) (((x) & BIT_MASK_GPIO_OUT_15_TO_8_8822B) << BIT_SHIFT_GPIO_OUT_15_TO_8_8822B)
-#define BIT_GET_GPIO_OUT_15_TO_8_8822B(x) (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8822B) & BIT_MASK_GPIO_OUT_15_TO_8_8822B)
-
+#define BIT_GPIO_OUT_15_TO_8_8822B(x) \
+ (((x) & BIT_MASK_GPIO_OUT_15_TO_8_8822B) \
+ << BIT_SHIFT_GPIO_OUT_15_TO_8_8822B)
+#define BITS_GPIO_OUT_15_TO_8_8822B \
+ (BIT_MASK_GPIO_OUT_15_TO_8_8822B << BIT_SHIFT_GPIO_OUT_15_TO_8_8822B)
+#define BIT_CLEAR_GPIO_OUT_15_TO_8_8822B(x) \
+ ((x) & (~BITS_GPIO_OUT_15_TO_8_8822B))
+#define BIT_GET_GPIO_OUT_15_TO_8_8822B(x) \
+ (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8822B) & \
+ BIT_MASK_GPIO_OUT_15_TO_8_8822B)
+#define BIT_SET_GPIO_OUT_15_TO_8_8822B(x, v) \
+ (BIT_CLEAR_GPIO_OUT_15_TO_8_8822B(x) | BIT_GPIO_OUT_15_TO_8_8822B(v))
#define BIT_SHIFT_GPIO_IN_15_TO_8_8822B 0
#define BIT_MASK_GPIO_IN_15_TO_8_8822B 0xff
-#define BIT_GPIO_IN_15_TO_8_8822B(x) (((x) & BIT_MASK_GPIO_IN_15_TO_8_8822B) << BIT_SHIFT_GPIO_IN_15_TO_8_8822B)
-#define BIT_GET_GPIO_IN_15_TO_8_8822B(x) (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8822B) & BIT_MASK_GPIO_IN_15_TO_8_8822B)
-
+#define BIT_GPIO_IN_15_TO_8_8822B(x) \
+ (((x) & BIT_MASK_GPIO_IN_15_TO_8_8822B) \
+ << BIT_SHIFT_GPIO_IN_15_TO_8_8822B)
+#define BITS_GPIO_IN_15_TO_8_8822B \
+ (BIT_MASK_GPIO_IN_15_TO_8_8822B << BIT_SHIFT_GPIO_IN_15_TO_8_8822B)
+#define BIT_CLEAR_GPIO_IN_15_TO_8_8822B(x) ((x) & (~BITS_GPIO_IN_15_TO_8_8822B))
+#define BIT_GET_GPIO_IN_15_TO_8_8822B(x) \
+ (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8822B) & \
+ BIT_MASK_GPIO_IN_15_TO_8_8822B)
+#define BIT_SET_GPIO_IN_15_TO_8_8822B(x, v) \
+ (BIT_CLEAR_GPIO_IN_15_TO_8_8822B(x) | BIT_GPIO_IN_15_TO_8_8822B(v))
/* 2 REG_PAD_CTRL1_8822B */
#define BIT_PAPE_WLBT_SEL_8822B BIT(29)
@@ -847,8 +1353,15 @@
#define BIT_SHIFT_BTGP_GPIO_SL_8822B 16
#define BIT_MASK_BTGP_GPIO_SL_8822B 0x3
-#define BIT_BTGP_GPIO_SL_8822B(x) (((x) & BIT_MASK_BTGP_GPIO_SL_8822B) << BIT_SHIFT_BTGP_GPIO_SL_8822B)
-#define BIT_GET_BTGP_GPIO_SL_8822B(x) (((x) >> BIT_SHIFT_BTGP_GPIO_SL_8822B) & BIT_MASK_BTGP_GPIO_SL_8822B)
+#define BIT_BTGP_GPIO_SL_8822B(x) \
+ (((x) & BIT_MASK_BTGP_GPIO_SL_8822B) << BIT_SHIFT_BTGP_GPIO_SL_8822B)
+#define BITS_BTGP_GPIO_SL_8822B \
+ (BIT_MASK_BTGP_GPIO_SL_8822B << BIT_SHIFT_BTGP_GPIO_SL_8822B)
+#define BIT_CLEAR_BTGP_GPIO_SL_8822B(x) ((x) & (~BITS_BTGP_GPIO_SL_8822B))
+#define BIT_GET_BTGP_GPIO_SL_8822B(x) \
+ (((x) >> BIT_SHIFT_BTGP_GPIO_SL_8822B) & BIT_MASK_BTGP_GPIO_SL_8822B)
+#define BIT_SET_BTGP_GPIO_SL_8822B(x, v) \
+ (BIT_CLEAR_BTGP_GPIO_SL_8822B(x) | BIT_BTGP_GPIO_SL_8822B(v))
#define BIT_PAD_SDIO_SR_8822B BIT(14)
#define BIT_GPIO14_OUTPUT_PL_8822B BIT(13)
@@ -899,9 +1412,15 @@
#define BIT_SHIFT_WLCLK_PHASE_8822B 0
#define BIT_MASK_WLCLK_PHASE_8822B 0x1f
-#define BIT_WLCLK_PHASE_8822B(x) (((x) & BIT_MASK_WLCLK_PHASE_8822B) << BIT_SHIFT_WLCLK_PHASE_8822B)
-#define BIT_GET_WLCLK_PHASE_8822B(x) (((x) >> BIT_SHIFT_WLCLK_PHASE_8822B) & BIT_MASK_WLCLK_PHASE_8822B)
-
+#define BIT_WLCLK_PHASE_8822B(x) \
+ (((x) & BIT_MASK_WLCLK_PHASE_8822B) << BIT_SHIFT_WLCLK_PHASE_8822B)
+#define BITS_WLCLK_PHASE_8822B \
+ (BIT_MASK_WLCLK_PHASE_8822B << BIT_SHIFT_WLCLK_PHASE_8822B)
+#define BIT_CLEAR_WLCLK_PHASE_8822B(x) ((x) & (~BITS_WLCLK_PHASE_8822B))
+#define BIT_GET_WLCLK_PHASE_8822B(x) \
+ (((x) >> BIT_SHIFT_WLCLK_PHASE_8822B) & BIT_MASK_WLCLK_PHASE_8822B)
+#define BIT_SET_WLCLK_PHASE_8822B(x, v) \
+ (BIT_CLEAR_WLCLK_PHASE_8822B(x) | BIT_WLCLK_PHASE_8822B(v))
/* 2 REG_SYS_SDIO_CTRL_8822B */
#define BIT_DBG_GNT_WL_BT_8822B BIT(27)
@@ -916,12 +1435,34 @@
#define BIT_PCIE_WAIT_TIME_8822B BIT(9)
#define BIT_MPCIE_REFCLK_XTAL_SEL_8822B BIT(8)
+#define BIT_SHIFT_SI_AUTHORIZATION_8822B 0
+#define BIT_MASK_SI_AUTHORIZATION_8822B 0xff
+#define BIT_SI_AUTHORIZATION_8822B(x) \
+ (((x) & BIT_MASK_SI_AUTHORIZATION_8822B) \
+ << BIT_SHIFT_SI_AUTHORIZATION_8822B)
+#define BITS_SI_AUTHORIZATION_8822B \
+ (BIT_MASK_SI_AUTHORIZATION_8822B << BIT_SHIFT_SI_AUTHORIZATION_8822B)
+#define BIT_CLEAR_SI_AUTHORIZATION_8822B(x) \
+ ((x) & (~BITS_SI_AUTHORIZATION_8822B))
+#define BIT_GET_SI_AUTHORIZATION_8822B(x) \
+ (((x) >> BIT_SHIFT_SI_AUTHORIZATION_8822B) & \
+ BIT_MASK_SI_AUTHORIZATION_8822B)
+#define BIT_SET_SI_AUTHORIZATION_8822B(x, v) \
+ (BIT_CLEAR_SI_AUTHORIZATION_8822B(x) | BIT_SI_AUTHORIZATION_8822B(v))
+
/* 2 REG_HCI_OPT_CTRL_8822B */
#define BIT_SHIFT_TSFT_SEL_8822B 29
#define BIT_MASK_TSFT_SEL_8822B 0x7
-#define BIT_TSFT_SEL_8822B(x) (((x) & BIT_MASK_TSFT_SEL_8822B) << BIT_SHIFT_TSFT_SEL_8822B)
-#define BIT_GET_TSFT_SEL_8822B(x) (((x) >> BIT_SHIFT_TSFT_SEL_8822B) & BIT_MASK_TSFT_SEL_8822B)
+#define BIT_TSFT_SEL_8822B(x) \
+ (((x) & BIT_MASK_TSFT_SEL_8822B) << BIT_SHIFT_TSFT_SEL_8822B)
+#define BITS_TSFT_SEL_8822B \
+ (BIT_MASK_TSFT_SEL_8822B << BIT_SHIFT_TSFT_SEL_8822B)
+#define BIT_CLEAR_TSFT_SEL_8822B(x) ((x) & (~BITS_TSFT_SEL_8822B))
+#define BIT_GET_TSFT_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_TSFT_SEL_8822B) & BIT_MASK_TSFT_SEL_8822B)
+#define BIT_SET_TSFT_SEL_8822B(x, v) \
+ (BIT_CLEAR_TSFT_SEL_8822B(x) | BIT_TSFT_SEL_8822B(v))
#define BIT_USB_HOST_PWR_OFF_EN_8822B BIT(12)
#define BIT_SYM_LPS_BLOCK_EN_8822B BIT(11)
@@ -931,8 +1472,15 @@
#define BIT_SHIFT_SDIO_PAD_E_8822B 5
#define BIT_MASK_SDIO_PAD_E_8822B 0x7
-#define BIT_SDIO_PAD_E_8822B(x) (((x) & BIT_MASK_SDIO_PAD_E_8822B) << BIT_SHIFT_SDIO_PAD_E_8822B)
-#define BIT_GET_SDIO_PAD_E_8822B(x) (((x) >> BIT_SHIFT_SDIO_PAD_E_8822B) & BIT_MASK_SDIO_PAD_E_8822B)
+#define BIT_SDIO_PAD_E_8822B(x) \
+ (((x) & BIT_MASK_SDIO_PAD_E_8822B) << BIT_SHIFT_SDIO_PAD_E_8822B)
+#define BITS_SDIO_PAD_E_8822B \
+ (BIT_MASK_SDIO_PAD_E_8822B << BIT_SHIFT_SDIO_PAD_E_8822B)
+#define BIT_CLEAR_SDIO_PAD_E_8822B(x) ((x) & (~BITS_SDIO_PAD_E_8822B))
+#define BIT_GET_SDIO_PAD_E_8822B(x) \
+ (((x) >> BIT_SHIFT_SDIO_PAD_E_8822B) & BIT_MASK_SDIO_PAD_E_8822B)
+#define BIT_SET_SDIO_PAD_E_8822B(x, v) \
+ (BIT_CLEAR_SDIO_PAD_E_8822B(x) | BIT_SDIO_PAD_E_8822B(v))
#define BIT_USB_LPPLL_EN_8822B BIT(4)
#define BIT_ROP_SW15_8822B BIT(2)
@@ -947,38 +1495,93 @@
#define BIT_SHIFT_AUTO_ZCD_IN_CODE_8822B 21
#define BIT_MASK_AUTO_ZCD_IN_CODE_8822B 0x1f
-#define BIT_AUTO_ZCD_IN_CODE_8822B(x) (((x) & BIT_MASK_AUTO_ZCD_IN_CODE_8822B) << BIT_SHIFT_AUTO_ZCD_IN_CODE_8822B)
-#define BIT_GET_AUTO_ZCD_IN_CODE_8822B(x) (((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE_8822B) & BIT_MASK_AUTO_ZCD_IN_CODE_8822B)
-
+#define BIT_AUTO_ZCD_IN_CODE_8822B(x) \
+ (((x) & BIT_MASK_AUTO_ZCD_IN_CODE_8822B) \
+ << BIT_SHIFT_AUTO_ZCD_IN_CODE_8822B)
+#define BITS_AUTO_ZCD_IN_CODE_8822B \
+ (BIT_MASK_AUTO_ZCD_IN_CODE_8822B << BIT_SHIFT_AUTO_ZCD_IN_CODE_8822B)
+#define BIT_CLEAR_AUTO_ZCD_IN_CODE_8822B(x) \
+ ((x) & (~BITS_AUTO_ZCD_IN_CODE_8822B))
+#define BIT_GET_AUTO_ZCD_IN_CODE_8822B(x) \
+ (((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE_8822B) & \
+ BIT_MASK_AUTO_ZCD_IN_CODE_8822B)
+#define BIT_SET_AUTO_ZCD_IN_CODE_8822B(x, v) \
+ (BIT_CLEAR_AUTO_ZCD_IN_CODE_8822B(x) | BIT_AUTO_ZCD_IN_CODE_8822B(v))
#define BIT_SHIFT_ZCD_CODE_IN_L_8822B 16
#define BIT_MASK_ZCD_CODE_IN_L_8822B 0x1f
-#define BIT_ZCD_CODE_IN_L_8822B(x) (((x) & BIT_MASK_ZCD_CODE_IN_L_8822B) << BIT_SHIFT_ZCD_CODE_IN_L_8822B)
-#define BIT_GET_ZCD_CODE_IN_L_8822B(x) (((x) >> BIT_SHIFT_ZCD_CODE_IN_L_8822B) & BIT_MASK_ZCD_CODE_IN_L_8822B)
-
+#define BIT_ZCD_CODE_IN_L_8822B(x) \
+ (((x) & BIT_MASK_ZCD_CODE_IN_L_8822B) << BIT_SHIFT_ZCD_CODE_IN_L_8822B)
+#define BITS_ZCD_CODE_IN_L_8822B \
+ (BIT_MASK_ZCD_CODE_IN_L_8822B << BIT_SHIFT_ZCD_CODE_IN_L_8822B)
+#define BIT_CLEAR_ZCD_CODE_IN_L_8822B(x) ((x) & (~BITS_ZCD_CODE_IN_L_8822B))
+#define BIT_GET_ZCD_CODE_IN_L_8822B(x) \
+ (((x) >> BIT_SHIFT_ZCD_CODE_IN_L_8822B) & BIT_MASK_ZCD_CODE_IN_L_8822B)
+#define BIT_SET_ZCD_CODE_IN_L_8822B(x, v) \
+ (BIT_CLEAR_ZCD_CODE_IN_L_8822B(x) | BIT_ZCD_CODE_IN_L_8822B(v))
#define BIT_SHIFT_LDO_HV5_DUMMY_8822B 14
#define BIT_MASK_LDO_HV5_DUMMY_8822B 0x3
-#define BIT_LDO_HV5_DUMMY_8822B(x) (((x) & BIT_MASK_LDO_HV5_DUMMY_8822B) << BIT_SHIFT_LDO_HV5_DUMMY_8822B)
-#define BIT_GET_LDO_HV5_DUMMY_8822B(x) (((x) >> BIT_SHIFT_LDO_HV5_DUMMY_8822B) & BIT_MASK_LDO_HV5_DUMMY_8822B)
-
+#define BIT_LDO_HV5_DUMMY_8822B(x) \
+ (((x) & BIT_MASK_LDO_HV5_DUMMY_8822B) << BIT_SHIFT_LDO_HV5_DUMMY_8822B)
+#define BITS_LDO_HV5_DUMMY_8822B \
+ (BIT_MASK_LDO_HV5_DUMMY_8822B << BIT_SHIFT_LDO_HV5_DUMMY_8822B)
+#define BIT_CLEAR_LDO_HV5_DUMMY_8822B(x) ((x) & (~BITS_LDO_HV5_DUMMY_8822B))
+#define BIT_GET_LDO_HV5_DUMMY_8822B(x) \
+ (((x) >> BIT_SHIFT_LDO_HV5_DUMMY_8822B) & BIT_MASK_LDO_HV5_DUMMY_8822B)
+#define BIT_SET_LDO_HV5_DUMMY_8822B(x, v) \
+ (BIT_CLEAR_LDO_HV5_DUMMY_8822B(x) | BIT_LDO_HV5_DUMMY_8822B(v))
#define BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8822B 12
#define BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8822B 0x3
-#define BIT_REG_VTUNE33_BIT0_TO_BIT1_8822B(x) (((x) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8822B) << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8822B)
-#define BIT_GET_REG_VTUNE33_BIT0_TO_BIT1_8822B(x) (((x) >> BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8822B) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8822B)
-
+#define BIT_REG_VTUNE33_BIT0_TO_BIT1_8822B(x) \
+ (((x) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8822B) \
+ << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8822B)
+#define BITS_REG_VTUNE33_BIT0_TO_BIT1_8822B \
+ (BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8822B \
+ << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8822B)
+#define BIT_CLEAR_REG_VTUNE33_BIT0_TO_BIT1_8822B(x) \
+ ((x) & (~BITS_REG_VTUNE33_BIT0_TO_BIT1_8822B))
+#define BIT_GET_REG_VTUNE33_BIT0_TO_BIT1_8822B(x) \
+ (((x) >> BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8822B) & \
+ BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8822B)
+#define BIT_SET_REG_VTUNE33_BIT0_TO_BIT1_8822B(x, v) \
+ (BIT_CLEAR_REG_VTUNE33_BIT0_TO_BIT1_8822B(x) | \
+ BIT_REG_VTUNE33_BIT0_TO_BIT1_8822B(v))
#define BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8822B 10
#define BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8822B 0x3
-#define BIT_REG_STANDBY33_BIT0_TO_BIT1_8822B(x) (((x) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8822B) << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8822B)
-#define BIT_GET_REG_STANDBY33_BIT0_TO_BIT1_8822B(x) (((x) >> BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8822B) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8822B)
-
+#define BIT_REG_STANDBY33_BIT0_TO_BIT1_8822B(x) \
+ (((x) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8822B) \
+ << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8822B)
+#define BITS_REG_STANDBY33_BIT0_TO_BIT1_8822B \
+ (BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8822B \
+ << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8822B)
+#define BIT_CLEAR_REG_STANDBY33_BIT0_TO_BIT1_8822B(x) \
+ ((x) & (~BITS_REG_STANDBY33_BIT0_TO_BIT1_8822B))
+#define BIT_GET_REG_STANDBY33_BIT0_TO_BIT1_8822B(x) \
+ (((x) >> BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8822B) & \
+ BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8822B)
+#define BIT_SET_REG_STANDBY33_BIT0_TO_BIT1_8822B(x, v) \
+ (BIT_CLEAR_REG_STANDBY33_BIT0_TO_BIT1_8822B(x) | \
+ BIT_REG_STANDBY33_BIT0_TO_BIT1_8822B(v))
#define BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8822B 8
#define BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8822B 0x3
-#define BIT_REG_LOAD33_BIT0_TO_BIT1_8822B(x) (((x) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8822B) << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8822B)
-#define BIT_GET_REG_LOAD33_BIT0_TO_BIT1_8822B(x) (((x) >> BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8822B) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8822B)
+#define BIT_REG_LOAD33_BIT0_TO_BIT1_8822B(x) \
+ (((x) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8822B) \
+ << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8822B)
+#define BITS_REG_LOAD33_BIT0_TO_BIT1_8822B \
+ (BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8822B \
+ << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8822B)
+#define BIT_CLEAR_REG_LOAD33_BIT0_TO_BIT1_8822B(x) \
+ ((x) & (~BITS_REG_LOAD33_BIT0_TO_BIT1_8822B))
+#define BIT_GET_REG_LOAD33_BIT0_TO_BIT1_8822B(x) \
+ (((x) >> BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8822B) & \
+ BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8822B)
+#define BIT_SET_REG_LOAD33_BIT0_TO_BIT1_8822B(x, v) \
+ (BIT_CLEAR_REG_LOAD33_BIT0_TO_BIT1_8822B(x) | \
+ BIT_REG_LOAD33_BIT0_TO_BIT1_8822B(v))
#define BIT_REG_BYPASS_L_8822B BIT(7)
#define BIT_REG_LDOF_L_8822B BIT(6)
@@ -987,8 +1590,14 @@
#define BIT_SHIFT_CFC_L_8822B 1
#define BIT_MASK_CFC_L_8822B 0x3
-#define BIT_CFC_L_8822B(x) (((x) & BIT_MASK_CFC_L_8822B) << BIT_SHIFT_CFC_L_8822B)
-#define BIT_GET_CFC_L_8822B(x) (((x) >> BIT_SHIFT_CFC_L_8822B) & BIT_MASK_CFC_L_8822B)
+#define BIT_CFC_L_8822B(x) \
+ (((x) & BIT_MASK_CFC_L_8822B) << BIT_SHIFT_CFC_L_8822B)
+#define BITS_CFC_L_8822B (BIT_MASK_CFC_L_8822B << BIT_SHIFT_CFC_L_8822B)
+#define BIT_CLEAR_CFC_L_8822B(x) ((x) & (~BITS_CFC_L_8822B))
+#define BIT_GET_CFC_L_8822B(x) \
+ (((x) >> BIT_SHIFT_CFC_L_8822B) & BIT_MASK_CFC_L_8822B)
+#define BIT_SET_CFC_L_8822B(x, v) \
+ (BIT_CLEAR_CFC_L_8822B(x) | BIT_CFC_L_8822B(v))
#define BIT_REG_OCPS_L_V1_8822B BIT(0)
@@ -997,7 +1606,11 @@
#define BIT_SHIFT_RPWM_8822B 24
#define BIT_MASK_RPWM_8822B 0xff
#define BIT_RPWM_8822B(x) (((x) & BIT_MASK_RPWM_8822B) << BIT_SHIFT_RPWM_8822B)
-#define BIT_GET_RPWM_8822B(x) (((x) >> BIT_SHIFT_RPWM_8822B) & BIT_MASK_RPWM_8822B)
+#define BITS_RPWM_8822B (BIT_MASK_RPWM_8822B << BIT_SHIFT_RPWM_8822B)
+#define BIT_CLEAR_RPWM_8822B(x) ((x) & (~BITS_RPWM_8822B))
+#define BIT_GET_RPWM_8822B(x) \
+ (((x) >> BIT_SHIFT_RPWM_8822B) & BIT_MASK_RPWM_8822B)
+#define BIT_SET_RPWM_8822B(x, v) (BIT_CLEAR_RPWM_8822B(x) | BIT_RPWM_8822B(v))
#define BIT_ANA_PORT_EN_8822B BIT(22)
#define BIT_MAC_PORT_EN_8822B BIT(21)
@@ -1006,16 +1619,29 @@
#define BIT_SHIFT_ROM_PGE_8822B 16
#define BIT_MASK_ROM_PGE_8822B 0x7
-#define BIT_ROM_PGE_8822B(x) (((x) & BIT_MASK_ROM_PGE_8822B) << BIT_SHIFT_ROM_PGE_8822B)
-#define BIT_GET_ROM_PGE_8822B(x) (((x) >> BIT_SHIFT_ROM_PGE_8822B) & BIT_MASK_ROM_PGE_8822B)
+#define BIT_ROM_PGE_8822B(x) \
+ (((x) & BIT_MASK_ROM_PGE_8822B) << BIT_SHIFT_ROM_PGE_8822B)
+#define BITS_ROM_PGE_8822B (BIT_MASK_ROM_PGE_8822B << BIT_SHIFT_ROM_PGE_8822B)
+#define BIT_CLEAR_ROM_PGE_8822B(x) ((x) & (~BITS_ROM_PGE_8822B))
+#define BIT_GET_ROM_PGE_8822B(x) \
+ (((x) >> BIT_SHIFT_ROM_PGE_8822B) & BIT_MASK_ROM_PGE_8822B)
+#define BIT_SET_ROM_PGE_8822B(x, v) \
+ (BIT_CLEAR_ROM_PGE_8822B(x) | BIT_ROM_PGE_8822B(v))
#define BIT_FW_INIT_RDY_8822B BIT(15)
#define BIT_FW_DW_RDY_8822B BIT(14)
#define BIT_SHIFT_CPU_CLK_SEL_8822B 12
#define BIT_MASK_CPU_CLK_SEL_8822B 0x3
-#define BIT_CPU_CLK_SEL_8822B(x) (((x) & BIT_MASK_CPU_CLK_SEL_8822B) << BIT_SHIFT_CPU_CLK_SEL_8822B)
-#define BIT_GET_CPU_CLK_SEL_8822B(x) (((x) >> BIT_SHIFT_CPU_CLK_SEL_8822B) & BIT_MASK_CPU_CLK_SEL_8822B)
+#define BIT_CPU_CLK_SEL_8822B(x) \
+ (((x) & BIT_MASK_CPU_CLK_SEL_8822B) << BIT_SHIFT_CPU_CLK_SEL_8822B)
+#define BITS_CPU_CLK_SEL_8822B \
+ (BIT_MASK_CPU_CLK_SEL_8822B << BIT_SHIFT_CPU_CLK_SEL_8822B)
+#define BIT_CLEAR_CPU_CLK_SEL_8822B(x) ((x) & (~BITS_CPU_CLK_SEL_8822B))
+#define BIT_GET_CPU_CLK_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_CPU_CLK_SEL_8822B) & BIT_MASK_CPU_CLK_SEL_8822B)
+#define BIT_SET_CPU_CLK_SEL_8822B(x, v) \
+ (BIT_CLEAR_CPU_CLK_SEL_8822B(x) | BIT_CPU_CLK_SEL_8822B(v))
#define BIT_CCLK_CHG_MASK_8822B BIT(11)
#define BIT_EMEM__TXBUF_CHKSUM_OK_8822B BIT(10)
@@ -1032,39 +1658,68 @@
/* 2 REG_MCU_TST_CFG_8822B */
-#define BIT_SHIFT_LBKTST_8822B 0
-#define BIT_MASK_LBKTST_8822B 0xffff
-#define BIT_LBKTST_8822B(x) (((x) & BIT_MASK_LBKTST_8822B) << BIT_SHIFT_LBKTST_8822B)
-#define BIT_GET_LBKTST_8822B(x) (((x) >> BIT_SHIFT_LBKTST_8822B) & BIT_MASK_LBKTST_8822B)
-
+#define BIT_SHIFT_C2H_MSG_8822B 0
+#define BIT_MASK_C2H_MSG_8822B 0xffff
+#define BIT_C2H_MSG_8822B(x) \
+ (((x) & BIT_MASK_C2H_MSG_8822B) << BIT_SHIFT_C2H_MSG_8822B)
+#define BITS_C2H_MSG_8822B (BIT_MASK_C2H_MSG_8822B << BIT_SHIFT_C2H_MSG_8822B)
+#define BIT_CLEAR_C2H_MSG_8822B(x) ((x) & (~BITS_C2H_MSG_8822B))
+#define BIT_GET_C2H_MSG_8822B(x) \
+ (((x) >> BIT_SHIFT_C2H_MSG_8822B) & BIT_MASK_C2H_MSG_8822B)
+#define BIT_SET_C2H_MSG_8822B(x, v) \
+ (BIT_CLEAR_C2H_MSG_8822B(x) | BIT_C2H_MSG_8822B(v))
/* 2 REG_HMEBOX_E0_E1_8822B */
#define BIT_SHIFT_HOST_MSG_E1_8822B 16
#define BIT_MASK_HOST_MSG_E1_8822B 0xffff
-#define BIT_HOST_MSG_E1_8822B(x) (((x) & BIT_MASK_HOST_MSG_E1_8822B) << BIT_SHIFT_HOST_MSG_E1_8822B)
-#define BIT_GET_HOST_MSG_E1_8822B(x) (((x) >> BIT_SHIFT_HOST_MSG_E1_8822B) & BIT_MASK_HOST_MSG_E1_8822B)
-
+#define BIT_HOST_MSG_E1_8822B(x) \
+ (((x) & BIT_MASK_HOST_MSG_E1_8822B) << BIT_SHIFT_HOST_MSG_E1_8822B)
+#define BITS_HOST_MSG_E1_8822B \
+ (BIT_MASK_HOST_MSG_E1_8822B << BIT_SHIFT_HOST_MSG_E1_8822B)
+#define BIT_CLEAR_HOST_MSG_E1_8822B(x) ((x) & (~BITS_HOST_MSG_E1_8822B))
+#define BIT_GET_HOST_MSG_E1_8822B(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_E1_8822B) & BIT_MASK_HOST_MSG_E1_8822B)
+#define BIT_SET_HOST_MSG_E1_8822B(x, v) \
+ (BIT_CLEAR_HOST_MSG_E1_8822B(x) | BIT_HOST_MSG_E1_8822B(v))
#define BIT_SHIFT_HOST_MSG_E0_8822B 0
#define BIT_MASK_HOST_MSG_E0_8822B 0xffff
-#define BIT_HOST_MSG_E0_8822B(x) (((x) & BIT_MASK_HOST_MSG_E0_8822B) << BIT_SHIFT_HOST_MSG_E0_8822B)
-#define BIT_GET_HOST_MSG_E0_8822B(x) (((x) >> BIT_SHIFT_HOST_MSG_E0_8822B) & BIT_MASK_HOST_MSG_E0_8822B)
-
+#define BIT_HOST_MSG_E0_8822B(x) \
+ (((x) & BIT_MASK_HOST_MSG_E0_8822B) << BIT_SHIFT_HOST_MSG_E0_8822B)
+#define BITS_HOST_MSG_E0_8822B \
+ (BIT_MASK_HOST_MSG_E0_8822B << BIT_SHIFT_HOST_MSG_E0_8822B)
+#define BIT_CLEAR_HOST_MSG_E0_8822B(x) ((x) & (~BITS_HOST_MSG_E0_8822B))
+#define BIT_GET_HOST_MSG_E0_8822B(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_E0_8822B) & BIT_MASK_HOST_MSG_E0_8822B)
+#define BIT_SET_HOST_MSG_E0_8822B(x, v) \
+ (BIT_CLEAR_HOST_MSG_E0_8822B(x) | BIT_HOST_MSG_E0_8822B(v))
/* 2 REG_HMEBOX_E2_E3_8822B */
#define BIT_SHIFT_HOST_MSG_E3_8822B 16
#define BIT_MASK_HOST_MSG_E3_8822B 0xffff
-#define BIT_HOST_MSG_E3_8822B(x) (((x) & BIT_MASK_HOST_MSG_E3_8822B) << BIT_SHIFT_HOST_MSG_E3_8822B)
-#define BIT_GET_HOST_MSG_E3_8822B(x) (((x) >> BIT_SHIFT_HOST_MSG_E3_8822B) & BIT_MASK_HOST_MSG_E3_8822B)
-
+#define BIT_HOST_MSG_E3_8822B(x) \
+ (((x) & BIT_MASK_HOST_MSG_E3_8822B) << BIT_SHIFT_HOST_MSG_E3_8822B)
+#define BITS_HOST_MSG_E3_8822B \
+ (BIT_MASK_HOST_MSG_E3_8822B << BIT_SHIFT_HOST_MSG_E3_8822B)
+#define BIT_CLEAR_HOST_MSG_E3_8822B(x) ((x) & (~BITS_HOST_MSG_E3_8822B))
+#define BIT_GET_HOST_MSG_E3_8822B(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_E3_8822B) & BIT_MASK_HOST_MSG_E3_8822B)
+#define BIT_SET_HOST_MSG_E3_8822B(x, v) \
+ (BIT_CLEAR_HOST_MSG_E3_8822B(x) | BIT_HOST_MSG_E3_8822B(v))
#define BIT_SHIFT_HOST_MSG_E2_8822B 0
#define BIT_MASK_HOST_MSG_E2_8822B 0xffff
-#define BIT_HOST_MSG_E2_8822B(x) (((x) & BIT_MASK_HOST_MSG_E2_8822B) << BIT_SHIFT_HOST_MSG_E2_8822B)
-#define BIT_GET_HOST_MSG_E2_8822B(x) (((x) >> BIT_SHIFT_HOST_MSG_E2_8822B) & BIT_MASK_HOST_MSG_E2_8822B)
-
+#define BIT_HOST_MSG_E2_8822B(x) \
+ (((x) & BIT_MASK_HOST_MSG_E2_8822B) << BIT_SHIFT_HOST_MSG_E2_8822B)
+#define BITS_HOST_MSG_E2_8822B \
+ (BIT_MASK_HOST_MSG_E2_8822B << BIT_SHIFT_HOST_MSG_E2_8822B)
+#define BIT_CLEAR_HOST_MSG_E2_8822B(x) ((x) & (~BITS_HOST_MSG_E2_8822B))
+#define BIT_GET_HOST_MSG_E2_8822B(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_E2_8822B) & BIT_MASK_HOST_MSG_E2_8822B)
+#define BIT_SET_HOST_MSG_E2_8822B(x, v) \
+ (BIT_CLEAR_HOST_MSG_E2_8822B(x) | BIT_HOST_MSG_E2_8822B(v))
/* 2 REG_WLLPS_CTRL_8822B */
#define BIT_WLLPSOP_EABM_8822B BIT(31)
@@ -1081,14 +1736,35 @@
#define BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822B 12
#define BIT_MASK_LPLDH12_VADJ_STEP_DN_8822B 0xf
-#define BIT_LPLDH12_VADJ_STEP_DN_8822B(x) (((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8822B) << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822B)
-#define BIT_GET_LPLDH12_VADJ_STEP_DN_8822B(x) (((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822B) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8822B)
-
+#define BIT_LPLDH12_VADJ_STEP_DN_8822B(x) \
+ (((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8822B) \
+ << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822B)
+#define BITS_LPLDH12_VADJ_STEP_DN_8822B \
+ (BIT_MASK_LPLDH12_VADJ_STEP_DN_8822B \
+ << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822B)
+#define BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8822B(x) \
+ ((x) & (~BITS_LPLDH12_VADJ_STEP_DN_8822B))
+#define BIT_GET_LPLDH12_VADJ_STEP_DN_8822B(x) \
+ (((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822B) & \
+ BIT_MASK_LPLDH12_VADJ_STEP_DN_8822B)
+#define BIT_SET_LPLDH12_VADJ_STEP_DN_8822B(x, v) \
+ (BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8822B(x) | \
+ BIT_LPLDH12_VADJ_STEP_DN_8822B(v))
#define BIT_SHIFT_V15ADJ_L1_STEP_DN_8822B 8
#define BIT_MASK_V15ADJ_L1_STEP_DN_8822B 0x7
-#define BIT_V15ADJ_L1_STEP_DN_8822B(x) (((x) & BIT_MASK_V15ADJ_L1_STEP_DN_8822B) << BIT_SHIFT_V15ADJ_L1_STEP_DN_8822B)
-#define BIT_GET_V15ADJ_L1_STEP_DN_8822B(x) (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN_8822B) & BIT_MASK_V15ADJ_L1_STEP_DN_8822B)
+#define BIT_V15ADJ_L1_STEP_DN_8822B(x) \
+ (((x) & BIT_MASK_V15ADJ_L1_STEP_DN_8822B) \
+ << BIT_SHIFT_V15ADJ_L1_STEP_DN_8822B)
+#define BITS_V15ADJ_L1_STEP_DN_8822B \
+ (BIT_MASK_V15ADJ_L1_STEP_DN_8822B << BIT_SHIFT_V15ADJ_L1_STEP_DN_8822B)
+#define BIT_CLEAR_V15ADJ_L1_STEP_DN_8822B(x) \
+ ((x) & (~BITS_V15ADJ_L1_STEP_DN_8822B))
+#define BIT_GET_V15ADJ_L1_STEP_DN_8822B(x) \
+ (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN_8822B) & \
+ BIT_MASK_V15ADJ_L1_STEP_DN_8822B)
+#define BIT_SET_V15ADJ_L1_STEP_DN_8822B(x, v) \
+ (BIT_CLEAR_V15ADJ_L1_STEP_DN_8822B(x) | BIT_V15ADJ_L1_STEP_DN_8822B(v))
#define BIT_REGU_32K_CLK_EN_8822B BIT(1)
#define BIT_WL_LPS_EN_8822B BIT(0)
@@ -1100,105 +1776,198 @@
#define BIT_SHIFT_REF_SEL_8822B 25
#define BIT_MASK_REF_SEL_8822B 0xf
-#define BIT_REF_SEL_8822B(x) (((x) & BIT_MASK_REF_SEL_8822B) << BIT_SHIFT_REF_SEL_8822B)
-#define BIT_GET_REF_SEL_8822B(x) (((x) >> BIT_SHIFT_REF_SEL_8822B) & BIT_MASK_REF_SEL_8822B)
-
+#define BIT_REF_SEL_8822B(x) \
+ (((x) & BIT_MASK_REF_SEL_8822B) << BIT_SHIFT_REF_SEL_8822B)
+#define BITS_REF_SEL_8822B (BIT_MASK_REF_SEL_8822B << BIT_SHIFT_REF_SEL_8822B)
+#define BIT_CLEAR_REF_SEL_8822B(x) ((x) & (~BITS_REF_SEL_8822B))
+#define BIT_GET_REF_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_REF_SEL_8822B) & BIT_MASK_REF_SEL_8822B)
+#define BIT_SET_REF_SEL_8822B(x, v) \
+ (BIT_CLEAR_REF_SEL_8822B(x) | BIT_REF_SEL_8822B(v))
#define BIT_SHIFT_F0F_SDM_8822B 12
#define BIT_MASK_F0F_SDM_8822B 0x1fff
-#define BIT_F0F_SDM_8822B(x) (((x) & BIT_MASK_F0F_SDM_8822B) << BIT_SHIFT_F0F_SDM_8822B)
-#define BIT_GET_F0F_SDM_8822B(x) (((x) >> BIT_SHIFT_F0F_SDM_8822B) & BIT_MASK_F0F_SDM_8822B)
-
+#define BIT_F0F_SDM_8822B(x) \
+ (((x) & BIT_MASK_F0F_SDM_8822B) << BIT_SHIFT_F0F_SDM_8822B)
+#define BITS_F0F_SDM_8822B (BIT_MASK_F0F_SDM_8822B << BIT_SHIFT_F0F_SDM_8822B)
+#define BIT_CLEAR_F0F_SDM_8822B(x) ((x) & (~BITS_F0F_SDM_8822B))
+#define BIT_GET_F0F_SDM_8822B(x) \
+ (((x) >> BIT_SHIFT_F0F_SDM_8822B) & BIT_MASK_F0F_SDM_8822B)
+#define BIT_SET_F0F_SDM_8822B(x, v) \
+ (BIT_CLEAR_F0F_SDM_8822B(x) | BIT_F0F_SDM_8822B(v))
#define BIT_SHIFT_F0N_SDM_8822B 9
#define BIT_MASK_F0N_SDM_8822B 0x7
-#define BIT_F0N_SDM_8822B(x) (((x) & BIT_MASK_F0N_SDM_8822B) << BIT_SHIFT_F0N_SDM_8822B)
-#define BIT_GET_F0N_SDM_8822B(x) (((x) >> BIT_SHIFT_F0N_SDM_8822B) & BIT_MASK_F0N_SDM_8822B)
-
+#define BIT_F0N_SDM_8822B(x) \
+ (((x) & BIT_MASK_F0N_SDM_8822B) << BIT_SHIFT_F0N_SDM_8822B)
+#define BITS_F0N_SDM_8822B (BIT_MASK_F0N_SDM_8822B << BIT_SHIFT_F0N_SDM_8822B)
+#define BIT_CLEAR_F0N_SDM_8822B(x) ((x) & (~BITS_F0N_SDM_8822B))
+#define BIT_GET_F0N_SDM_8822B(x) \
+ (((x) >> BIT_SHIFT_F0N_SDM_8822B) & BIT_MASK_F0N_SDM_8822B)
+#define BIT_SET_F0N_SDM_8822B(x, v) \
+ (BIT_CLEAR_F0N_SDM_8822B(x) | BIT_F0N_SDM_8822B(v))
#define BIT_SHIFT_DIVN_SDM_8822B 3
#define BIT_MASK_DIVN_SDM_8822B 0x3f
-#define BIT_DIVN_SDM_8822B(x) (((x) & BIT_MASK_DIVN_SDM_8822B) << BIT_SHIFT_DIVN_SDM_8822B)
-#define BIT_GET_DIVN_SDM_8822B(x) (((x) >> BIT_SHIFT_DIVN_SDM_8822B) & BIT_MASK_DIVN_SDM_8822B)
-
+#define BIT_DIVN_SDM_8822B(x) \
+ (((x) & BIT_MASK_DIVN_SDM_8822B) << BIT_SHIFT_DIVN_SDM_8822B)
+#define BITS_DIVN_SDM_8822B \
+ (BIT_MASK_DIVN_SDM_8822B << BIT_SHIFT_DIVN_SDM_8822B)
+#define BIT_CLEAR_DIVN_SDM_8822B(x) ((x) & (~BITS_DIVN_SDM_8822B))
+#define BIT_GET_DIVN_SDM_8822B(x) \
+ (((x) >> BIT_SHIFT_DIVN_SDM_8822B) & BIT_MASK_DIVN_SDM_8822B)
+#define BIT_SET_DIVN_SDM_8822B(x, v) \
+ (BIT_CLEAR_DIVN_SDM_8822B(x) | BIT_DIVN_SDM_8822B(v))
/* 2 REG_GPIO_DEBOUNCE_CTRL_8822B */
#define BIT_WLGP_DBC1EN_8822B BIT(15)
#define BIT_SHIFT_WLGP_DBC1_8822B 8
#define BIT_MASK_WLGP_DBC1_8822B 0xf
-#define BIT_WLGP_DBC1_8822B(x) (((x) & BIT_MASK_WLGP_DBC1_8822B) << BIT_SHIFT_WLGP_DBC1_8822B)
-#define BIT_GET_WLGP_DBC1_8822B(x) (((x) >> BIT_SHIFT_WLGP_DBC1_8822B) & BIT_MASK_WLGP_DBC1_8822B)
+#define BIT_WLGP_DBC1_8822B(x) \
+ (((x) & BIT_MASK_WLGP_DBC1_8822B) << BIT_SHIFT_WLGP_DBC1_8822B)
+#define BITS_WLGP_DBC1_8822B \
+ (BIT_MASK_WLGP_DBC1_8822B << BIT_SHIFT_WLGP_DBC1_8822B)
+#define BIT_CLEAR_WLGP_DBC1_8822B(x) ((x) & (~BITS_WLGP_DBC1_8822B))
+#define BIT_GET_WLGP_DBC1_8822B(x) \
+ (((x) >> BIT_SHIFT_WLGP_DBC1_8822B) & BIT_MASK_WLGP_DBC1_8822B)
+#define BIT_SET_WLGP_DBC1_8822B(x, v) \
+ (BIT_CLEAR_WLGP_DBC1_8822B(x) | BIT_WLGP_DBC1_8822B(v))
#define BIT_WLGP_DBC0EN_8822B BIT(7)
#define BIT_SHIFT_WLGP_DBC0_8822B 0
#define BIT_MASK_WLGP_DBC0_8822B 0xf
-#define BIT_WLGP_DBC0_8822B(x) (((x) & BIT_MASK_WLGP_DBC0_8822B) << BIT_SHIFT_WLGP_DBC0_8822B)
-#define BIT_GET_WLGP_DBC0_8822B(x) (((x) >> BIT_SHIFT_WLGP_DBC0_8822B) & BIT_MASK_WLGP_DBC0_8822B)
-
+#define BIT_WLGP_DBC0_8822B(x) \
+ (((x) & BIT_MASK_WLGP_DBC0_8822B) << BIT_SHIFT_WLGP_DBC0_8822B)
+#define BITS_WLGP_DBC0_8822B \
+ (BIT_MASK_WLGP_DBC0_8822B << BIT_SHIFT_WLGP_DBC0_8822B)
+#define BIT_CLEAR_WLGP_DBC0_8822B(x) ((x) & (~BITS_WLGP_DBC0_8822B))
+#define BIT_GET_WLGP_DBC0_8822B(x) \
+ (((x) >> BIT_SHIFT_WLGP_DBC0_8822B) & BIT_MASK_WLGP_DBC0_8822B)
+#define BIT_SET_WLGP_DBC0_8822B(x, v) \
+ (BIT_CLEAR_WLGP_DBC0_8822B(x) | BIT_WLGP_DBC0_8822B(v))
/* 2 REG_RPWM2_8822B */
#define BIT_SHIFT_RPWM2_8822B 16
#define BIT_MASK_RPWM2_8822B 0xffff
-#define BIT_RPWM2_8822B(x) (((x) & BIT_MASK_RPWM2_8822B) << BIT_SHIFT_RPWM2_8822B)
-#define BIT_GET_RPWM2_8822B(x) (((x) >> BIT_SHIFT_RPWM2_8822B) & BIT_MASK_RPWM2_8822B)
-
+#define BIT_RPWM2_8822B(x) \
+ (((x) & BIT_MASK_RPWM2_8822B) << BIT_SHIFT_RPWM2_8822B)
+#define BITS_RPWM2_8822B (BIT_MASK_RPWM2_8822B << BIT_SHIFT_RPWM2_8822B)
+#define BIT_CLEAR_RPWM2_8822B(x) ((x) & (~BITS_RPWM2_8822B))
+#define BIT_GET_RPWM2_8822B(x) \
+ (((x) >> BIT_SHIFT_RPWM2_8822B) & BIT_MASK_RPWM2_8822B)
+#define BIT_SET_RPWM2_8822B(x, v) \
+ (BIT_CLEAR_RPWM2_8822B(x) | BIT_RPWM2_8822B(v))
/* 2 REG_SYSON_FSM_MON_8822B */
#define BIT_SHIFT_FSM_MON_SEL_8822B 24
#define BIT_MASK_FSM_MON_SEL_8822B 0x7
-#define BIT_FSM_MON_SEL_8822B(x) (((x) & BIT_MASK_FSM_MON_SEL_8822B) << BIT_SHIFT_FSM_MON_SEL_8822B)
-#define BIT_GET_FSM_MON_SEL_8822B(x) (((x) >> BIT_SHIFT_FSM_MON_SEL_8822B) & BIT_MASK_FSM_MON_SEL_8822B)
+#define BIT_FSM_MON_SEL_8822B(x) \
+ (((x) & BIT_MASK_FSM_MON_SEL_8822B) << BIT_SHIFT_FSM_MON_SEL_8822B)
+#define BITS_FSM_MON_SEL_8822B \
+ (BIT_MASK_FSM_MON_SEL_8822B << BIT_SHIFT_FSM_MON_SEL_8822B)
+#define BIT_CLEAR_FSM_MON_SEL_8822B(x) ((x) & (~BITS_FSM_MON_SEL_8822B))
+#define BIT_GET_FSM_MON_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_FSM_MON_SEL_8822B) & BIT_MASK_FSM_MON_SEL_8822B)
+#define BIT_SET_FSM_MON_SEL_8822B(x, v) \
+ (BIT_CLEAR_FSM_MON_SEL_8822B(x) | BIT_FSM_MON_SEL_8822B(v))
#define BIT_DOP_ELDO_8822B BIT(23)
#define BIT_FSM_MON_UPD_8822B BIT(15)
#define BIT_SHIFT_FSM_PAR_8822B 0
#define BIT_MASK_FSM_PAR_8822B 0x7fff
-#define BIT_FSM_PAR_8822B(x) (((x) & BIT_MASK_FSM_PAR_8822B) << BIT_SHIFT_FSM_PAR_8822B)
-#define BIT_GET_FSM_PAR_8822B(x) (((x) >> BIT_SHIFT_FSM_PAR_8822B) & BIT_MASK_FSM_PAR_8822B)
-
+#define BIT_FSM_PAR_8822B(x) \
+ (((x) & BIT_MASK_FSM_PAR_8822B) << BIT_SHIFT_FSM_PAR_8822B)
+#define BITS_FSM_PAR_8822B (BIT_MASK_FSM_PAR_8822B << BIT_SHIFT_FSM_PAR_8822B)
+#define BIT_CLEAR_FSM_PAR_8822B(x) ((x) & (~BITS_FSM_PAR_8822B))
+#define BIT_GET_FSM_PAR_8822B(x) \
+ (((x) >> BIT_SHIFT_FSM_PAR_8822B) & BIT_MASK_FSM_PAR_8822B)
+#define BIT_SET_FSM_PAR_8822B(x, v) \
+ (BIT_CLEAR_FSM_PAR_8822B(x) | BIT_FSM_PAR_8822B(v))
/* 2 REG_AFE_CTRL6_8822B */
#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B 0
#define BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B 0x7
-#define BIT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B(x) (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B) << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B)
-#define BIT_GET_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B(x) (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B)
-
+#define BIT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B(x) \
+ (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B) \
+ << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B)
+#define BITS_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B \
+ (BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B \
+ << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B)
+#define BIT_CLEAR_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B(x) \
+ ((x) & (~BITS_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B))
+#define BIT_GET_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B(x) \
+ (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B) & \
+ BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B)
+#define BIT_SET_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B(x, v) \
+ (BIT_CLEAR_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B(x) | \
+ BIT_BB_DBG_SEL_AFE_SDM_BIT3_1_8822B(v))
/* 2 REG_PMC_DBG_CTRL1_8822B */
#define BIT_BT_INT_EN_8822B BIT(31)
#define BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822B 16
#define BIT_MASK_RD_WR_WIFI_BT_INFO_8822B 0x7fff
-#define BIT_RD_WR_WIFI_BT_INFO_8822B(x) (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8822B) << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822B)
-#define BIT_GET_RD_WR_WIFI_BT_INFO_8822B(x) (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822B) & BIT_MASK_RD_WR_WIFI_BT_INFO_8822B)
+#define BIT_RD_WR_WIFI_BT_INFO_8822B(x) \
+ (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8822B) \
+ << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822B)
+#define BITS_RD_WR_WIFI_BT_INFO_8822B \
+ (BIT_MASK_RD_WR_WIFI_BT_INFO_8822B \
+ << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822B)
+#define BIT_CLEAR_RD_WR_WIFI_BT_INFO_8822B(x) \
+ ((x) & (~BITS_RD_WR_WIFI_BT_INFO_8822B))
+#define BIT_GET_RD_WR_WIFI_BT_INFO_8822B(x) \
+ (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822B) & \
+ BIT_MASK_RD_WR_WIFI_BT_INFO_8822B)
+#define BIT_SET_RD_WR_WIFI_BT_INFO_8822B(x, v) \
+ (BIT_CLEAR_RD_WR_WIFI_BT_INFO_8822B(x) | \
+ BIT_RD_WR_WIFI_BT_INFO_8822B(v))
#define BIT_PMC_WR_OVF_8822B BIT(8)
#define BIT_SHIFT_WLPMC_ERRINT_8822B 0
#define BIT_MASK_WLPMC_ERRINT_8822B 0xff
-#define BIT_WLPMC_ERRINT_8822B(x) (((x) & BIT_MASK_WLPMC_ERRINT_8822B) << BIT_SHIFT_WLPMC_ERRINT_8822B)
-#define BIT_GET_WLPMC_ERRINT_8822B(x) (((x) >> BIT_SHIFT_WLPMC_ERRINT_8822B) & BIT_MASK_WLPMC_ERRINT_8822B)
-
+#define BIT_WLPMC_ERRINT_8822B(x) \
+ (((x) & BIT_MASK_WLPMC_ERRINT_8822B) << BIT_SHIFT_WLPMC_ERRINT_8822B)
+#define BITS_WLPMC_ERRINT_8822B \
+ (BIT_MASK_WLPMC_ERRINT_8822B << BIT_SHIFT_WLPMC_ERRINT_8822B)
+#define BIT_CLEAR_WLPMC_ERRINT_8822B(x) ((x) & (~BITS_WLPMC_ERRINT_8822B))
+#define BIT_GET_WLPMC_ERRINT_8822B(x) \
+ (((x) >> BIT_SHIFT_WLPMC_ERRINT_8822B) & BIT_MASK_WLPMC_ERRINT_8822B)
+#define BIT_SET_WLPMC_ERRINT_8822B(x, v) \
+ (BIT_CLEAR_WLPMC_ERRINT_8822B(x) | BIT_WLPMC_ERRINT_8822B(v))
/* 2 REG_AFE_CTRL7_8822B */
#define BIT_SHIFT_SEL_V_8822B 30
#define BIT_MASK_SEL_V_8822B 0x3
-#define BIT_SEL_V_8822B(x) (((x) & BIT_MASK_SEL_V_8822B) << BIT_SHIFT_SEL_V_8822B)
-#define BIT_GET_SEL_V_8822B(x) (((x) >> BIT_SHIFT_SEL_V_8822B) & BIT_MASK_SEL_V_8822B)
+#define BIT_SEL_V_8822B(x) \
+ (((x) & BIT_MASK_SEL_V_8822B) << BIT_SHIFT_SEL_V_8822B)
+#define BITS_SEL_V_8822B (BIT_MASK_SEL_V_8822B << BIT_SHIFT_SEL_V_8822B)
+#define BIT_CLEAR_SEL_V_8822B(x) ((x) & (~BITS_SEL_V_8822B))
+#define BIT_GET_SEL_V_8822B(x) \
+ (((x) >> BIT_SHIFT_SEL_V_8822B) & BIT_MASK_SEL_V_8822B)
+#define BIT_SET_SEL_V_8822B(x, v) \
+ (BIT_CLEAR_SEL_V_8822B(x) | BIT_SEL_V_8822B(v))
#define BIT_SEL_LDO_PC_8822B BIT(29)
#define BIT_SHIFT_CK_MON_SEL_8822B 26
#define BIT_MASK_CK_MON_SEL_8822B 0x7
-#define BIT_CK_MON_SEL_8822B(x) (((x) & BIT_MASK_CK_MON_SEL_8822B) << BIT_SHIFT_CK_MON_SEL_8822B)
-#define BIT_GET_CK_MON_SEL_8822B(x) (((x) >> BIT_SHIFT_CK_MON_SEL_8822B) & BIT_MASK_CK_MON_SEL_8822B)
+#define BIT_CK_MON_SEL_8822B(x) \
+ (((x) & BIT_MASK_CK_MON_SEL_8822B) << BIT_SHIFT_CK_MON_SEL_8822B)
+#define BITS_CK_MON_SEL_8822B \
+ (BIT_MASK_CK_MON_SEL_8822B << BIT_SHIFT_CK_MON_SEL_8822B)
+#define BIT_CLEAR_CK_MON_SEL_8822B(x) ((x) & (~BITS_CK_MON_SEL_8822B))
+#define BIT_GET_CK_MON_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_CK_MON_SEL_8822B) & BIT_MASK_CK_MON_SEL_8822B)
+#define BIT_SET_CK_MON_SEL_8822B(x, v) \
+ (BIT_CLEAR_CK_MON_SEL_8822B(x) | BIT_CK_MON_SEL_8822B(v))
#define BIT_CK_MON_EN_8822B BIT(25)
#define BIT_FREF_EDGE_8822B BIT(24)
@@ -1218,8 +1987,8 @@
#define BIT_BCNDMAINT0_MSK_8822B BIT(20)
#define BIT_BCNDERR0_MSK_8822B BIT(16)
#define BIT_HSISR_IND_ON_INT_MSK_8822B BIT(15)
-#define BIT_BCNDMAINT_E_MSK_8822B BIT(14)
-#define BIT_CTWEND_MSK_8822B BIT(12)
+#define BIT_HISR3_IND_INT_MSK_8822B BIT(14)
+#define BIT_HISR2_IND_INT_MSK_8822B BIT(13)
#define BIT_HISR1_IND_MSK_8822B BIT(11)
#define BIT_C2HCMD_MSK_8822B BIT(10)
#define BIT_CPWM2_MSK_8822B BIT(9)
@@ -1234,8 +2003,8 @@
#define BIT_RXOK_MSK_8822B BIT(0)
/* 2 REG_HISR0_8822B */
-#define BIT_TIMEOUT_INTERRUPT2_8822B BIT(31)
-#define BIT_TIMEOUT_INTERRUTP1_8822B BIT(30)
+#define BIT_PSTIMEOUT2_8822B BIT(31)
+#define BIT_PSTIMEOUT1_8822B BIT(30)
#define BIT_PSTIMEOUT_8822B BIT(29)
#define BIT_GTINT4_8822B BIT(28)
#define BIT_GTINT3_8822B BIT(27)
@@ -1245,8 +2014,8 @@
#define BIT_BCNDMAINT0_8822B BIT(20)
#define BIT_BCNDERR0_8822B BIT(16)
#define BIT_HSISR_IND_ON_INT_8822B BIT(15)
-#define BIT_BCNDMAINT_E_8822B BIT(14)
-#define BIT_CTWEND_8822B BIT(12)
+#define BIT_HISR3_IND_INT_8822B BIT(14)
+#define BIT_HISR2_IND_INT_8822B BIT(13)
#define BIT_HISR1_IND_INT_8822B BIT(11)
#define BIT_C2HCMD_8822B BIT(10)
#define BIT_CPWM2_8822B BIT(9)
@@ -1263,7 +2032,6 @@
/* 2 REG_HIMR1_8822B */
#define BIT_TXFIFO_TH_INT_8822B BIT(30)
#define BIT_BTON_STS_UPDATE_MASK_8822B BIT(29)
-#define BIT_MCU_ERR_MASK_8822B BIT(28)
#define BIT_BCNDMAINT7__MSK_8822B BIT(27)
#define BIT_BCNDMAINT6__MSK_8822B BIT(26)
#define BIT_BCNDMAINT5__MSK_8822B BIT(25)
@@ -1278,8 +2046,7 @@
#define BIT_BCNDERR3_MSK_8822B BIT(16)
#define BIT_BCNDERR2_MSK_8822B BIT(15)
#define BIT_BCNDERR1_MSK_8822B BIT(14)
-#define BIT_ATIMEND_E_MSK_8822B BIT(13)
-#define BIT_ATIMEND__MSK_8822B BIT(12)
+#define BIT_ATIMEND_E_V1_MSK_8822B BIT(12)
#define BIT_TXERR_MSK_8822B BIT(11)
#define BIT_RXERR_MSK_8822B BIT(10)
#define BIT_TXFOVW_MSK_8822B BIT(9)
@@ -1293,7 +2060,6 @@
/* 2 REG_HISR1_8822B */
#define BIT_TXFIFO_TH_INT_8822B BIT(30)
#define BIT_BTON_STS_UPDATE_INT_8822B BIT(29)
-#define BIT_MCU_ERR_8822B BIT(28)
#define BIT_BCNDMAINT7_8822B BIT(27)
#define BIT_BCNDMAINT6_8822B BIT(26)
#define BIT_BCNDMAINT5_8822B BIT(25)
@@ -1308,8 +2074,7 @@
#define BIT_BCNDERR3_8822B BIT(16)
#define BIT_BCNDERR2_8822B BIT(15)
#define BIT_BCNDERR1_8822B BIT(14)
-#define BIT_ATIMEND_E_8822B BIT(13)
-#define BIT_ATIMEND_8822B BIT(12)
+#define BIT_ATIMEND_E_V1_INT_8822B BIT(12)
#define BIT_TXERR_INT_8822B BIT(11)
#define BIT_RXERR_INT_8822B BIT(10)
#define BIT_TXFOVW_8822B BIT(9)
@@ -1324,25 +2089,48 @@
#define BIT_SHIFT_DEBUG_ST_8822B 0
#define BIT_MASK_DEBUG_ST_8822B 0xffffffffL
-#define BIT_DEBUG_ST_8822B(x) (((x) & BIT_MASK_DEBUG_ST_8822B) << BIT_SHIFT_DEBUG_ST_8822B)
-#define BIT_GET_DEBUG_ST_8822B(x) (((x) >> BIT_SHIFT_DEBUG_ST_8822B) & BIT_MASK_DEBUG_ST_8822B)
-
+#define BIT_DEBUG_ST_8822B(x) \
+ (((x) & BIT_MASK_DEBUG_ST_8822B) << BIT_SHIFT_DEBUG_ST_8822B)
+#define BITS_DEBUG_ST_8822B \
+ (BIT_MASK_DEBUG_ST_8822B << BIT_SHIFT_DEBUG_ST_8822B)
+#define BIT_CLEAR_DEBUG_ST_8822B(x) ((x) & (~BITS_DEBUG_ST_8822B))
+#define BIT_GET_DEBUG_ST_8822B(x) \
+ (((x) >> BIT_SHIFT_DEBUG_ST_8822B) & BIT_MASK_DEBUG_ST_8822B)
+#define BIT_SET_DEBUG_ST_8822B(x, v) \
+ (BIT_CLEAR_DEBUG_ST_8822B(x) | BIT_DEBUG_ST_8822B(v))
/* 2 REG_PAD_CTRL2_8822B */
#define BIT_USB3_USB2_TRANSITION_8822B BIT(20)
#define BIT_SHIFT_USB23_SW_MODE_V1_8822B 18
#define BIT_MASK_USB23_SW_MODE_V1_8822B 0x3
-#define BIT_USB23_SW_MODE_V1_8822B(x) (((x) & BIT_MASK_USB23_SW_MODE_V1_8822B) << BIT_SHIFT_USB23_SW_MODE_V1_8822B)
-#define BIT_GET_USB23_SW_MODE_V1_8822B(x) (((x) >> BIT_SHIFT_USB23_SW_MODE_V1_8822B) & BIT_MASK_USB23_SW_MODE_V1_8822B)
+#define BIT_USB23_SW_MODE_V1_8822B(x) \
+ (((x) & BIT_MASK_USB23_SW_MODE_V1_8822B) \
+ << BIT_SHIFT_USB23_SW_MODE_V1_8822B)
+#define BITS_USB23_SW_MODE_V1_8822B \
+ (BIT_MASK_USB23_SW_MODE_V1_8822B << BIT_SHIFT_USB23_SW_MODE_V1_8822B)
+#define BIT_CLEAR_USB23_SW_MODE_V1_8822B(x) \
+ ((x) & (~BITS_USB23_SW_MODE_V1_8822B))
+#define BIT_GET_USB23_SW_MODE_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_USB23_SW_MODE_V1_8822B) & \
+ BIT_MASK_USB23_SW_MODE_V1_8822B)
+#define BIT_SET_USB23_SW_MODE_V1_8822B(x, v) \
+ (BIT_CLEAR_USB23_SW_MODE_V1_8822B(x) | BIT_USB23_SW_MODE_V1_8822B(v))
#define BIT_NO_PDN_CHIPOFF_V1_8822B BIT(17)
#define BIT_RSM_EN_V1_8822B BIT(16)
#define BIT_SHIFT_MATCH_CNT_8822B 8
#define BIT_MASK_MATCH_CNT_8822B 0xff
-#define BIT_MATCH_CNT_8822B(x) (((x) & BIT_MASK_MATCH_CNT_8822B) << BIT_SHIFT_MATCH_CNT_8822B)
-#define BIT_GET_MATCH_CNT_8822B(x) (((x) >> BIT_SHIFT_MATCH_CNT_8822B) & BIT_MASK_MATCH_CNT_8822B)
+#define BIT_MATCH_CNT_8822B(x) \
+ (((x) & BIT_MASK_MATCH_CNT_8822B) << BIT_SHIFT_MATCH_CNT_8822B)
+#define BITS_MATCH_CNT_8822B \
+ (BIT_MASK_MATCH_CNT_8822B << BIT_SHIFT_MATCH_CNT_8822B)
+#define BIT_CLEAR_MATCH_CNT_8822B(x) ((x) & (~BITS_MATCH_CNT_8822B))
+#define BIT_GET_MATCH_CNT_8822B(x) \
+ (((x) >> BIT_SHIFT_MATCH_CNT_8822B) & BIT_MASK_MATCH_CNT_8822B)
+#define BIT_SET_MATCH_CNT_8822B(x, v) \
+ (BIT_CLEAR_MATCH_CNT_8822B(x) | BIT_MATCH_CNT_8822B(v))
#define BIT_LD_B12V_EN_8822B BIT(7)
#define BIT_EECS_IOSEL_V1_8822B BIT(6)
@@ -1358,8 +2146,17 @@
#define BIT_SHIFT_EFUSE_BURN_GNT_8822B 24
#define BIT_MASK_EFUSE_BURN_GNT_8822B 0xff
-#define BIT_EFUSE_BURN_GNT_8822B(x) (((x) & BIT_MASK_EFUSE_BURN_GNT_8822B) << BIT_SHIFT_EFUSE_BURN_GNT_8822B)
-#define BIT_GET_EFUSE_BURN_GNT_8822B(x) (((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8822B) & BIT_MASK_EFUSE_BURN_GNT_8822B)
+#define BIT_EFUSE_BURN_GNT_8822B(x) \
+ (((x) & BIT_MASK_EFUSE_BURN_GNT_8822B) \
+ << BIT_SHIFT_EFUSE_BURN_GNT_8822B)
+#define BITS_EFUSE_BURN_GNT_8822B \
+ (BIT_MASK_EFUSE_BURN_GNT_8822B << BIT_SHIFT_EFUSE_BURN_GNT_8822B)
+#define BIT_CLEAR_EFUSE_BURN_GNT_8822B(x) ((x) & (~BITS_EFUSE_BURN_GNT_8822B))
+#define BIT_GET_EFUSE_BURN_GNT_8822B(x) \
+ (((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8822B) & \
+ BIT_MASK_EFUSE_BURN_GNT_8822B)
+#define BIT_SET_EFUSE_BURN_GNT_8822B(x, v) \
+ (BIT_CLEAR_EFUSE_BURN_GNT_8822B(x) | BIT_EFUSE_BURN_GNT_8822B(v))
#define BIT_STOP_WL_PMC_8822B BIT(9)
#define BIT_STOP_SYM_PMC_8822B BIT(8)
@@ -1370,9 +2167,15 @@
#define BIT_SHIFT_SYSON_REG_ARB_8822B 0
#define BIT_MASK_SYSON_REG_ARB_8822B 0x3
-#define BIT_SYSON_REG_ARB_8822B(x) (((x) & BIT_MASK_SYSON_REG_ARB_8822B) << BIT_SHIFT_SYSON_REG_ARB_8822B)
-#define BIT_GET_SYSON_REG_ARB_8822B(x) (((x) >> BIT_SHIFT_SYSON_REG_ARB_8822B) & BIT_MASK_SYSON_REG_ARB_8822B)
-
+#define BIT_SYSON_REG_ARB_8822B(x) \
+ (((x) & BIT_MASK_SYSON_REG_ARB_8822B) << BIT_SHIFT_SYSON_REG_ARB_8822B)
+#define BITS_SYSON_REG_ARB_8822B \
+ (BIT_MASK_SYSON_REG_ARB_8822B << BIT_SHIFT_SYSON_REG_ARB_8822B)
+#define BIT_CLEAR_SYSON_REG_ARB_8822B(x) ((x) & (~BITS_SYSON_REG_ARB_8822B))
+#define BIT_GET_SYSON_REG_ARB_8822B(x) \
+ (((x) >> BIT_SHIFT_SYSON_REG_ARB_8822B) & BIT_MASK_SYSON_REG_ARB_8822B)
+#define BIT_SET_SYSON_REG_ARB_8822B(x, v) \
+ (BIT_CLEAR_SYSON_REG_ARB_8822B(x) | BIT_SYSON_REG_ARB_8822B(v))
/* 2 REG_BIST_CTRL_8822B */
#define BIT_BIST_USB_DIS_8822B BIT(27)
@@ -1382,8 +2185,15 @@
#define BIT_SHIFT_BIST_RPT_SEL_8822B 16
#define BIT_MASK_BIST_RPT_SEL_8822B 0xf
-#define BIT_BIST_RPT_SEL_8822B(x) (((x) & BIT_MASK_BIST_RPT_SEL_8822B) << BIT_SHIFT_BIST_RPT_SEL_8822B)
-#define BIT_GET_BIST_RPT_SEL_8822B(x) (((x) >> BIT_SHIFT_BIST_RPT_SEL_8822B) & BIT_MASK_BIST_RPT_SEL_8822B)
+#define BIT_BIST_RPT_SEL_8822B(x) \
+ (((x) & BIT_MASK_BIST_RPT_SEL_8822B) << BIT_SHIFT_BIST_RPT_SEL_8822B)
+#define BITS_BIST_RPT_SEL_8822B \
+ (BIT_MASK_BIST_RPT_SEL_8822B << BIT_SHIFT_BIST_RPT_SEL_8822B)
+#define BIT_CLEAR_BIST_RPT_SEL_8822B(x) ((x) & (~BITS_BIST_RPT_SEL_8822B))
+#define BIT_GET_BIST_RPT_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_BIST_RPT_SEL_8822B) & BIT_MASK_BIST_RPT_SEL_8822B)
+#define BIT_SET_BIST_RPT_SEL_8822B(x, v) \
+ (BIT_CLEAR_BIST_RPT_SEL_8822B(x) | BIT_BIST_RPT_SEL_8822B(v))
#define BIT_BIST_RESUME_PS_8822B BIT(4)
#define BIT_BIST_RESUME_8822B BIT(3)
@@ -1395,54 +2205,100 @@
#define BIT_SHIFT_MBIST_REPORT_8822B 0
#define BIT_MASK_MBIST_REPORT_8822B 0xffffffffL
-#define BIT_MBIST_REPORT_8822B(x) (((x) & BIT_MASK_MBIST_REPORT_8822B) << BIT_SHIFT_MBIST_REPORT_8822B)
-#define BIT_GET_MBIST_REPORT_8822B(x) (((x) >> BIT_SHIFT_MBIST_REPORT_8822B) & BIT_MASK_MBIST_REPORT_8822B)
-
+#define BIT_MBIST_REPORT_8822B(x) \
+ (((x) & BIT_MASK_MBIST_REPORT_8822B) << BIT_SHIFT_MBIST_REPORT_8822B)
+#define BITS_MBIST_REPORT_8822B \
+ (BIT_MASK_MBIST_REPORT_8822B << BIT_SHIFT_MBIST_REPORT_8822B)
+#define BIT_CLEAR_MBIST_REPORT_8822B(x) ((x) & (~BITS_MBIST_REPORT_8822B))
+#define BIT_GET_MBIST_REPORT_8822B(x) \
+ (((x) >> BIT_SHIFT_MBIST_REPORT_8822B) & BIT_MASK_MBIST_REPORT_8822B)
+#define BIT_SET_MBIST_REPORT_8822B(x, v) \
+ (BIT_CLEAR_MBIST_REPORT_8822B(x) | BIT_MBIST_REPORT_8822B(v))
/* 2 REG_MEM_CTRL_8822B */
#define BIT_UMEM_RME_8822B BIT(31)
#define BIT_SHIFT_BT_SPRAM_8822B 28
#define BIT_MASK_BT_SPRAM_8822B 0x3
-#define BIT_BT_SPRAM_8822B(x) (((x) & BIT_MASK_BT_SPRAM_8822B) << BIT_SHIFT_BT_SPRAM_8822B)
-#define BIT_GET_BT_SPRAM_8822B(x) (((x) >> BIT_SHIFT_BT_SPRAM_8822B) & BIT_MASK_BT_SPRAM_8822B)
-
+#define BIT_BT_SPRAM_8822B(x) \
+ (((x) & BIT_MASK_BT_SPRAM_8822B) << BIT_SHIFT_BT_SPRAM_8822B)
+#define BITS_BT_SPRAM_8822B \
+ (BIT_MASK_BT_SPRAM_8822B << BIT_SHIFT_BT_SPRAM_8822B)
+#define BIT_CLEAR_BT_SPRAM_8822B(x) ((x) & (~BITS_BT_SPRAM_8822B))
+#define BIT_GET_BT_SPRAM_8822B(x) \
+ (((x) >> BIT_SHIFT_BT_SPRAM_8822B) & BIT_MASK_BT_SPRAM_8822B)
+#define BIT_SET_BT_SPRAM_8822B(x, v) \
+ (BIT_CLEAR_BT_SPRAM_8822B(x) | BIT_BT_SPRAM_8822B(v))
#define BIT_SHIFT_BT_ROM_8822B 24
#define BIT_MASK_BT_ROM_8822B 0xf
-#define BIT_BT_ROM_8822B(x) (((x) & BIT_MASK_BT_ROM_8822B) << BIT_SHIFT_BT_ROM_8822B)
-#define BIT_GET_BT_ROM_8822B(x) (((x) >> BIT_SHIFT_BT_ROM_8822B) & BIT_MASK_BT_ROM_8822B)
-
+#define BIT_BT_ROM_8822B(x) \
+ (((x) & BIT_MASK_BT_ROM_8822B) << BIT_SHIFT_BT_ROM_8822B)
+#define BITS_BT_ROM_8822B (BIT_MASK_BT_ROM_8822B << BIT_SHIFT_BT_ROM_8822B)
+#define BIT_CLEAR_BT_ROM_8822B(x) ((x) & (~BITS_BT_ROM_8822B))
+#define BIT_GET_BT_ROM_8822B(x) \
+ (((x) >> BIT_SHIFT_BT_ROM_8822B) & BIT_MASK_BT_ROM_8822B)
+#define BIT_SET_BT_ROM_8822B(x, v) \
+ (BIT_CLEAR_BT_ROM_8822B(x) | BIT_BT_ROM_8822B(v))
#define BIT_SHIFT_PCI_DPRAM_8822B 10
#define BIT_MASK_PCI_DPRAM_8822B 0x3
-#define BIT_PCI_DPRAM_8822B(x) (((x) & BIT_MASK_PCI_DPRAM_8822B) << BIT_SHIFT_PCI_DPRAM_8822B)
-#define BIT_GET_PCI_DPRAM_8822B(x) (((x) >> BIT_SHIFT_PCI_DPRAM_8822B) & BIT_MASK_PCI_DPRAM_8822B)
-
+#define BIT_PCI_DPRAM_8822B(x) \
+ (((x) & BIT_MASK_PCI_DPRAM_8822B) << BIT_SHIFT_PCI_DPRAM_8822B)
+#define BITS_PCI_DPRAM_8822B \
+ (BIT_MASK_PCI_DPRAM_8822B << BIT_SHIFT_PCI_DPRAM_8822B)
+#define BIT_CLEAR_PCI_DPRAM_8822B(x) ((x) & (~BITS_PCI_DPRAM_8822B))
+#define BIT_GET_PCI_DPRAM_8822B(x) \
+ (((x) >> BIT_SHIFT_PCI_DPRAM_8822B) & BIT_MASK_PCI_DPRAM_8822B)
+#define BIT_SET_PCI_DPRAM_8822B(x, v) \
+ (BIT_CLEAR_PCI_DPRAM_8822B(x) | BIT_PCI_DPRAM_8822B(v))
#define BIT_SHIFT_PCI_SPRAM_8822B 8
#define BIT_MASK_PCI_SPRAM_8822B 0x3
-#define BIT_PCI_SPRAM_8822B(x) (((x) & BIT_MASK_PCI_SPRAM_8822B) << BIT_SHIFT_PCI_SPRAM_8822B)
-#define BIT_GET_PCI_SPRAM_8822B(x) (((x) >> BIT_SHIFT_PCI_SPRAM_8822B) & BIT_MASK_PCI_SPRAM_8822B)
-
+#define BIT_PCI_SPRAM_8822B(x) \
+ (((x) & BIT_MASK_PCI_SPRAM_8822B) << BIT_SHIFT_PCI_SPRAM_8822B)
+#define BITS_PCI_SPRAM_8822B \
+ (BIT_MASK_PCI_SPRAM_8822B << BIT_SHIFT_PCI_SPRAM_8822B)
+#define BIT_CLEAR_PCI_SPRAM_8822B(x) ((x) & (~BITS_PCI_SPRAM_8822B))
+#define BIT_GET_PCI_SPRAM_8822B(x) \
+ (((x) >> BIT_SHIFT_PCI_SPRAM_8822B) & BIT_MASK_PCI_SPRAM_8822B)
+#define BIT_SET_PCI_SPRAM_8822B(x, v) \
+ (BIT_CLEAR_PCI_SPRAM_8822B(x) | BIT_PCI_SPRAM_8822B(v))
#define BIT_SHIFT_USB_SPRAM_8822B 6
#define BIT_MASK_USB_SPRAM_8822B 0x3
-#define BIT_USB_SPRAM_8822B(x) (((x) & BIT_MASK_USB_SPRAM_8822B) << BIT_SHIFT_USB_SPRAM_8822B)
-#define BIT_GET_USB_SPRAM_8822B(x) (((x) >> BIT_SHIFT_USB_SPRAM_8822B) & BIT_MASK_USB_SPRAM_8822B)
-
+#define BIT_USB_SPRAM_8822B(x) \
+ (((x) & BIT_MASK_USB_SPRAM_8822B) << BIT_SHIFT_USB_SPRAM_8822B)
+#define BITS_USB_SPRAM_8822B \
+ (BIT_MASK_USB_SPRAM_8822B << BIT_SHIFT_USB_SPRAM_8822B)
+#define BIT_CLEAR_USB_SPRAM_8822B(x) ((x) & (~BITS_USB_SPRAM_8822B))
+#define BIT_GET_USB_SPRAM_8822B(x) \
+ (((x) >> BIT_SHIFT_USB_SPRAM_8822B) & BIT_MASK_USB_SPRAM_8822B)
+#define BIT_SET_USB_SPRAM_8822B(x, v) \
+ (BIT_CLEAR_USB_SPRAM_8822B(x) | BIT_USB_SPRAM_8822B(v))
#define BIT_SHIFT_USB_SPRF_8822B 4
#define BIT_MASK_USB_SPRF_8822B 0x3
-#define BIT_USB_SPRF_8822B(x) (((x) & BIT_MASK_USB_SPRF_8822B) << BIT_SHIFT_USB_SPRF_8822B)
-#define BIT_GET_USB_SPRF_8822B(x) (((x) >> BIT_SHIFT_USB_SPRF_8822B) & BIT_MASK_USB_SPRF_8822B)
-
+#define BIT_USB_SPRF_8822B(x) \
+ (((x) & BIT_MASK_USB_SPRF_8822B) << BIT_SHIFT_USB_SPRF_8822B)
+#define BITS_USB_SPRF_8822B \
+ (BIT_MASK_USB_SPRF_8822B << BIT_SHIFT_USB_SPRF_8822B)
+#define BIT_CLEAR_USB_SPRF_8822B(x) ((x) & (~BITS_USB_SPRF_8822B))
+#define BIT_GET_USB_SPRF_8822B(x) \
+ (((x) >> BIT_SHIFT_USB_SPRF_8822B) & BIT_MASK_USB_SPRF_8822B)
+#define BIT_SET_USB_SPRF_8822B(x, v) \
+ (BIT_CLEAR_USB_SPRF_8822B(x) | BIT_USB_SPRF_8822B(v))
#define BIT_SHIFT_MCU_ROM_8822B 0
#define BIT_MASK_MCU_ROM_8822B 0xf
-#define BIT_MCU_ROM_8822B(x) (((x) & BIT_MASK_MCU_ROM_8822B) << BIT_SHIFT_MCU_ROM_8822B)
-#define BIT_GET_MCU_ROM_8822B(x) (((x) >> BIT_SHIFT_MCU_ROM_8822B) & BIT_MASK_MCU_ROM_8822B)
-
+#define BIT_MCU_ROM_8822B(x) \
+ (((x) & BIT_MASK_MCU_ROM_8822B) << BIT_SHIFT_MCU_ROM_8822B)
+#define BITS_MCU_ROM_8822B (BIT_MASK_MCU_ROM_8822B << BIT_SHIFT_MCU_ROM_8822B)
+#define BIT_CLEAR_MCU_ROM_8822B(x) ((x) & (~BITS_MCU_ROM_8822B))
+#define BIT_GET_MCU_ROM_8822B(x) \
+ (((x) >> BIT_SHIFT_MCU_ROM_8822B) & BIT_MASK_MCU_ROM_8822B)
+#define BIT_SET_MCU_ROM_8822B(x, v) \
+ (BIT_CLEAR_MCU_ROM_8822B(x) | BIT_MCU_ROM_8822B(v))
/* 2 REG_AFE_CTRL8_8822B */
#define BIT_SYN_AGPIO_8822B BIT(20)
@@ -1451,9 +2307,15 @@
#define BIT_SHIFT_XTAL_SEL_TOK_8822B 0
#define BIT_MASK_XTAL_SEL_TOK_8822B 0x7
-#define BIT_XTAL_SEL_TOK_8822B(x) (((x) & BIT_MASK_XTAL_SEL_TOK_8822B) << BIT_SHIFT_XTAL_SEL_TOK_8822B)
-#define BIT_GET_XTAL_SEL_TOK_8822B(x) (((x) >> BIT_SHIFT_XTAL_SEL_TOK_8822B) & BIT_MASK_XTAL_SEL_TOK_8822B)
-
+#define BIT_XTAL_SEL_TOK_8822B(x) \
+ (((x) & BIT_MASK_XTAL_SEL_TOK_8822B) << BIT_SHIFT_XTAL_SEL_TOK_8822B)
+#define BITS_XTAL_SEL_TOK_8822B \
+ (BIT_MASK_XTAL_SEL_TOK_8822B << BIT_SHIFT_XTAL_SEL_TOK_8822B)
+#define BIT_CLEAR_XTAL_SEL_TOK_8822B(x) ((x) & (~BITS_XTAL_SEL_TOK_8822B))
+#define BIT_GET_XTAL_SEL_TOK_8822B(x) \
+ (((x) >> BIT_SHIFT_XTAL_SEL_TOK_8822B) & BIT_MASK_XTAL_SEL_TOK_8822B)
+#define BIT_SET_XTAL_SEL_TOK_8822B(x, v) \
+ (BIT_CLEAR_XTAL_SEL_TOK_8822B(x) | BIT_XTAL_SEL_TOK_8822B(v))
/* 2 REG_USB_SIE_INTF_8822B */
#define BIT_RD_SEL_8822B BIT(31)
@@ -1463,21 +2325,48 @@
#define BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822B 16
#define BIT_MASK_USB_SIE_INTF_ADDR_V1_8822B 0x1ff
-#define BIT_USB_SIE_INTF_ADDR_V1_8822B(x) (((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8822B) << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822B)
-#define BIT_GET_USB_SIE_INTF_ADDR_V1_8822B(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822B) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8822B)
-
+#define BIT_USB_SIE_INTF_ADDR_V1_8822B(x) \
+ (((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8822B) \
+ << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822B)
+#define BITS_USB_SIE_INTF_ADDR_V1_8822B \
+ (BIT_MASK_USB_SIE_INTF_ADDR_V1_8822B \
+ << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822B)
+#define BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8822B(x) \
+ ((x) & (~BITS_USB_SIE_INTF_ADDR_V1_8822B))
+#define BIT_GET_USB_SIE_INTF_ADDR_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822B) & \
+ BIT_MASK_USB_SIE_INTF_ADDR_V1_8822B)
+#define BIT_SET_USB_SIE_INTF_ADDR_V1_8822B(x, v) \
+ (BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8822B(x) | \
+ BIT_USB_SIE_INTF_ADDR_V1_8822B(v))
#define BIT_SHIFT_USB_SIE_INTF_RD_8822B 8
#define BIT_MASK_USB_SIE_INTF_RD_8822B 0xff
-#define BIT_USB_SIE_INTF_RD_8822B(x) (((x) & BIT_MASK_USB_SIE_INTF_RD_8822B) << BIT_SHIFT_USB_SIE_INTF_RD_8822B)
-#define BIT_GET_USB_SIE_INTF_RD_8822B(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_RD_8822B) & BIT_MASK_USB_SIE_INTF_RD_8822B)
-
+#define BIT_USB_SIE_INTF_RD_8822B(x) \
+ (((x) & BIT_MASK_USB_SIE_INTF_RD_8822B) \
+ << BIT_SHIFT_USB_SIE_INTF_RD_8822B)
+#define BITS_USB_SIE_INTF_RD_8822B \
+ (BIT_MASK_USB_SIE_INTF_RD_8822B << BIT_SHIFT_USB_SIE_INTF_RD_8822B)
+#define BIT_CLEAR_USB_SIE_INTF_RD_8822B(x) ((x) & (~BITS_USB_SIE_INTF_RD_8822B))
+#define BIT_GET_USB_SIE_INTF_RD_8822B(x) \
+ (((x) >> BIT_SHIFT_USB_SIE_INTF_RD_8822B) & \
+ BIT_MASK_USB_SIE_INTF_RD_8822B)
+#define BIT_SET_USB_SIE_INTF_RD_8822B(x, v) \
+ (BIT_CLEAR_USB_SIE_INTF_RD_8822B(x) | BIT_USB_SIE_INTF_RD_8822B(v))
#define BIT_SHIFT_USB_SIE_INTF_WD_8822B 0
#define BIT_MASK_USB_SIE_INTF_WD_8822B 0xff
-#define BIT_USB_SIE_INTF_WD_8822B(x) (((x) & BIT_MASK_USB_SIE_INTF_WD_8822B) << BIT_SHIFT_USB_SIE_INTF_WD_8822B)
-#define BIT_GET_USB_SIE_INTF_WD_8822B(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_WD_8822B) & BIT_MASK_USB_SIE_INTF_WD_8822B)
-
+#define BIT_USB_SIE_INTF_WD_8822B(x) \
+ (((x) & BIT_MASK_USB_SIE_INTF_WD_8822B) \
+ << BIT_SHIFT_USB_SIE_INTF_WD_8822B)
+#define BITS_USB_SIE_INTF_WD_8822B \
+ (BIT_MASK_USB_SIE_INTF_WD_8822B << BIT_SHIFT_USB_SIE_INTF_WD_8822B)
+#define BIT_CLEAR_USB_SIE_INTF_WD_8822B(x) ((x) & (~BITS_USB_SIE_INTF_WD_8822B))
+#define BIT_GET_USB_SIE_INTF_WD_8822B(x) \
+ (((x) >> BIT_SHIFT_USB_SIE_INTF_WD_8822B) & \
+ BIT_MASK_USB_SIE_INTF_WD_8822B)
+#define BIT_SET_USB_SIE_INTF_WD_8822B(x, v) \
+ (BIT_CLEAR_USB_SIE_INTF_WD_8822B(x) | BIT_USB_SIE_INTF_WD_8822B(v))
/* 2 REG_PCIE_MIO_INTF_8822B */
#define BIT_PCIE_MIO_BYIOREG_8822B BIT(13)
@@ -1485,38 +2374,69 @@
#define BIT_SHIFT_PCIE_MIO_WE_8822B 8
#define BIT_MASK_PCIE_MIO_WE_8822B 0xf
-#define BIT_PCIE_MIO_WE_8822B(x) (((x) & BIT_MASK_PCIE_MIO_WE_8822B) << BIT_SHIFT_PCIE_MIO_WE_8822B)
-#define BIT_GET_PCIE_MIO_WE_8822B(x) (((x) >> BIT_SHIFT_PCIE_MIO_WE_8822B) & BIT_MASK_PCIE_MIO_WE_8822B)
-
+#define BIT_PCIE_MIO_WE_8822B(x) \
+ (((x) & BIT_MASK_PCIE_MIO_WE_8822B) << BIT_SHIFT_PCIE_MIO_WE_8822B)
+#define BITS_PCIE_MIO_WE_8822B \
+ (BIT_MASK_PCIE_MIO_WE_8822B << BIT_SHIFT_PCIE_MIO_WE_8822B)
+#define BIT_CLEAR_PCIE_MIO_WE_8822B(x) ((x) & (~BITS_PCIE_MIO_WE_8822B))
+#define BIT_GET_PCIE_MIO_WE_8822B(x) \
+ (((x) >> BIT_SHIFT_PCIE_MIO_WE_8822B) & BIT_MASK_PCIE_MIO_WE_8822B)
+#define BIT_SET_PCIE_MIO_WE_8822B(x, v) \
+ (BIT_CLEAR_PCIE_MIO_WE_8822B(x) | BIT_PCIE_MIO_WE_8822B(v))
#define BIT_SHIFT_PCIE_MIO_ADDR_8822B 0
#define BIT_MASK_PCIE_MIO_ADDR_8822B 0xff
-#define BIT_PCIE_MIO_ADDR_8822B(x) (((x) & BIT_MASK_PCIE_MIO_ADDR_8822B) << BIT_SHIFT_PCIE_MIO_ADDR_8822B)
-#define BIT_GET_PCIE_MIO_ADDR_8822B(x) (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8822B) & BIT_MASK_PCIE_MIO_ADDR_8822B)
-
+#define BIT_PCIE_MIO_ADDR_8822B(x) \
+ (((x) & BIT_MASK_PCIE_MIO_ADDR_8822B) << BIT_SHIFT_PCIE_MIO_ADDR_8822B)
+#define BITS_PCIE_MIO_ADDR_8822B \
+ (BIT_MASK_PCIE_MIO_ADDR_8822B << BIT_SHIFT_PCIE_MIO_ADDR_8822B)
+#define BIT_CLEAR_PCIE_MIO_ADDR_8822B(x) ((x) & (~BITS_PCIE_MIO_ADDR_8822B))
+#define BIT_GET_PCIE_MIO_ADDR_8822B(x) \
+ (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8822B) & BIT_MASK_PCIE_MIO_ADDR_8822B)
+#define BIT_SET_PCIE_MIO_ADDR_8822B(x, v) \
+ (BIT_CLEAR_PCIE_MIO_ADDR_8822B(x) | BIT_PCIE_MIO_ADDR_8822B(v))
/* 2 REG_PCIE_MIO_INTD_8822B */
#define BIT_SHIFT_PCIE_MIO_DATA_8822B 0
#define BIT_MASK_PCIE_MIO_DATA_8822B 0xffffffffL
-#define BIT_PCIE_MIO_DATA_8822B(x) (((x) & BIT_MASK_PCIE_MIO_DATA_8822B) << BIT_SHIFT_PCIE_MIO_DATA_8822B)
-#define BIT_GET_PCIE_MIO_DATA_8822B(x) (((x) >> BIT_SHIFT_PCIE_MIO_DATA_8822B) & BIT_MASK_PCIE_MIO_DATA_8822B)
-
+#define BIT_PCIE_MIO_DATA_8822B(x) \
+ (((x) & BIT_MASK_PCIE_MIO_DATA_8822B) << BIT_SHIFT_PCIE_MIO_DATA_8822B)
+#define BITS_PCIE_MIO_DATA_8822B \
+ (BIT_MASK_PCIE_MIO_DATA_8822B << BIT_SHIFT_PCIE_MIO_DATA_8822B)
+#define BIT_CLEAR_PCIE_MIO_DATA_8822B(x) ((x) & (~BITS_PCIE_MIO_DATA_8822B))
+#define BIT_GET_PCIE_MIO_DATA_8822B(x) \
+ (((x) >> BIT_SHIFT_PCIE_MIO_DATA_8822B) & BIT_MASK_PCIE_MIO_DATA_8822B)
+#define BIT_SET_PCIE_MIO_DATA_8822B(x, v) \
+ (BIT_CLEAR_PCIE_MIO_DATA_8822B(x) | BIT_PCIE_MIO_DATA_8822B(v))
/* 2 REG_WLRF1_8822B */
#define BIT_SHIFT_WLRF1_CTRL_8822B 24
#define BIT_MASK_WLRF1_CTRL_8822B 0xff
-#define BIT_WLRF1_CTRL_8822B(x) (((x) & BIT_MASK_WLRF1_CTRL_8822B) << BIT_SHIFT_WLRF1_CTRL_8822B)
-#define BIT_GET_WLRF1_CTRL_8822B(x) (((x) >> BIT_SHIFT_WLRF1_CTRL_8822B) & BIT_MASK_WLRF1_CTRL_8822B)
-
+#define BIT_WLRF1_CTRL_8822B(x) \
+ (((x) & BIT_MASK_WLRF1_CTRL_8822B) << BIT_SHIFT_WLRF1_CTRL_8822B)
+#define BITS_WLRF1_CTRL_8822B \
+ (BIT_MASK_WLRF1_CTRL_8822B << BIT_SHIFT_WLRF1_CTRL_8822B)
+#define BIT_CLEAR_WLRF1_CTRL_8822B(x) ((x) & (~BITS_WLRF1_CTRL_8822B))
+#define BIT_GET_WLRF1_CTRL_8822B(x) \
+ (((x) >> BIT_SHIFT_WLRF1_CTRL_8822B) & BIT_MASK_WLRF1_CTRL_8822B)
+#define BIT_SET_WLRF1_CTRL_8822B(x, v) \
+ (BIT_CLEAR_WLRF1_CTRL_8822B(x) | BIT_WLRF1_CTRL_8822B(v))
/* 2 REG_SYS_CFG1_8822B */
#define BIT_SHIFT_TRP_ICFG_8822B 28
#define BIT_MASK_TRP_ICFG_8822B 0xf
-#define BIT_TRP_ICFG_8822B(x) (((x) & BIT_MASK_TRP_ICFG_8822B) << BIT_SHIFT_TRP_ICFG_8822B)
-#define BIT_GET_TRP_ICFG_8822B(x) (((x) >> BIT_SHIFT_TRP_ICFG_8822B) & BIT_MASK_TRP_ICFG_8822B)
+#define BIT_TRP_ICFG_8822B(x) \
+ (((x) & BIT_MASK_TRP_ICFG_8822B) << BIT_SHIFT_TRP_ICFG_8822B)
+#define BITS_TRP_ICFG_8822B \
+ (BIT_MASK_TRP_ICFG_8822B << BIT_SHIFT_TRP_ICFG_8822B)
+#define BIT_CLEAR_TRP_ICFG_8822B(x) ((x) & (~BITS_TRP_ICFG_8822B))
+#define BIT_GET_TRP_ICFG_8822B(x) \
+ (((x) >> BIT_SHIFT_TRP_ICFG_8822B) & BIT_MASK_TRP_ICFG_8822B)
+#define BIT_SET_TRP_ICFG_8822B(x, v) \
+ (BIT_CLEAR_TRP_ICFG_8822B(x) | BIT_TRP_ICFG_8822B(v))
#define BIT_RF_TYPE_ID_8822B BIT(27)
#define BIT_BD_HCI_SEL_8822B BIT(26)
@@ -1528,14 +2448,27 @@
#define BIT_SHIFT_VENDOR_ID_8822B 16
#define BIT_MASK_VENDOR_ID_8822B 0xf
-#define BIT_VENDOR_ID_8822B(x) (((x) & BIT_MASK_VENDOR_ID_8822B) << BIT_SHIFT_VENDOR_ID_8822B)
-#define BIT_GET_VENDOR_ID_8822B(x) (((x) >> BIT_SHIFT_VENDOR_ID_8822B) & BIT_MASK_VENDOR_ID_8822B)
-
+#define BIT_VENDOR_ID_8822B(x) \
+ (((x) & BIT_MASK_VENDOR_ID_8822B) << BIT_SHIFT_VENDOR_ID_8822B)
+#define BITS_VENDOR_ID_8822B \
+ (BIT_MASK_VENDOR_ID_8822B << BIT_SHIFT_VENDOR_ID_8822B)
+#define BIT_CLEAR_VENDOR_ID_8822B(x) ((x) & (~BITS_VENDOR_ID_8822B))
+#define BIT_GET_VENDOR_ID_8822B(x) \
+ (((x) >> BIT_SHIFT_VENDOR_ID_8822B) & BIT_MASK_VENDOR_ID_8822B)
+#define BIT_SET_VENDOR_ID_8822B(x, v) \
+ (BIT_CLEAR_VENDOR_ID_8822B(x) | BIT_VENDOR_ID_8822B(v))
#define BIT_SHIFT_CHIP_VER_8822B 12
#define BIT_MASK_CHIP_VER_8822B 0xf
-#define BIT_CHIP_VER_8822B(x) (((x) & BIT_MASK_CHIP_VER_8822B) << BIT_SHIFT_CHIP_VER_8822B)
-#define BIT_GET_CHIP_VER_8822B(x) (((x) >> BIT_SHIFT_CHIP_VER_8822B) & BIT_MASK_CHIP_VER_8822B)
+#define BIT_CHIP_VER_8822B(x) \
+ (((x) & BIT_MASK_CHIP_VER_8822B) << BIT_SHIFT_CHIP_VER_8822B)
+#define BITS_CHIP_VER_8822B \
+ (BIT_MASK_CHIP_VER_8822B << BIT_SHIFT_CHIP_VER_8822B)
+#define BIT_CLEAR_CHIP_VER_8822B(x) ((x) & (~BITS_CHIP_VER_8822B))
+#define BIT_GET_CHIP_VER_8822B(x) \
+ (((x) >> BIT_SHIFT_CHIP_VER_8822B) & BIT_MASK_CHIP_VER_8822B)
+#define BIT_SET_CHIP_VER_8822B(x, v) \
+ (BIT_CLEAR_CHIP_VER_8822B(x) | BIT_CHIP_VER_8822B(v))
#define BIT_BD_MAC3_8822B BIT(11)
#define BIT_BD_MAC1_8822B BIT(10)
@@ -1554,21 +2487,41 @@
#define BIT_SHIFT_RF_RL_ID_8822B 28
#define BIT_MASK_RF_RL_ID_8822B 0xf
-#define BIT_RF_RL_ID_8822B(x) (((x) & BIT_MASK_RF_RL_ID_8822B) << BIT_SHIFT_RF_RL_ID_8822B)
-#define BIT_GET_RF_RL_ID_8822B(x) (((x) >> BIT_SHIFT_RF_RL_ID_8822B) & BIT_MASK_RF_RL_ID_8822B)
+#define BIT_RF_RL_ID_8822B(x) \
+ (((x) & BIT_MASK_RF_RL_ID_8822B) << BIT_SHIFT_RF_RL_ID_8822B)
+#define BITS_RF_RL_ID_8822B \
+ (BIT_MASK_RF_RL_ID_8822B << BIT_SHIFT_RF_RL_ID_8822B)
+#define BIT_CLEAR_RF_RL_ID_8822B(x) ((x) & (~BITS_RF_RL_ID_8822B))
+#define BIT_GET_RF_RL_ID_8822B(x) \
+ (((x) >> BIT_SHIFT_RF_RL_ID_8822B) & BIT_MASK_RF_RL_ID_8822B)
+#define BIT_SET_RF_RL_ID_8822B(x, v) \
+ (BIT_CLEAR_RF_RL_ID_8822B(x) | BIT_RF_RL_ID_8822B(v))
#define BIT_HPHY_ICFG_8822B BIT(19)
#define BIT_SHIFT_SEL_0XC0_8822B 16
#define BIT_MASK_SEL_0XC0_8822B 0x3
-#define BIT_SEL_0XC0_8822B(x) (((x) & BIT_MASK_SEL_0XC0_8822B) << BIT_SHIFT_SEL_0XC0_8822B)
-#define BIT_GET_SEL_0XC0_8822B(x) (((x) >> BIT_SHIFT_SEL_0XC0_8822B) & BIT_MASK_SEL_0XC0_8822B)
-
+#define BIT_SEL_0XC0_8822B(x) \
+ (((x) & BIT_MASK_SEL_0XC0_8822B) << BIT_SHIFT_SEL_0XC0_8822B)
+#define BITS_SEL_0XC0_8822B \
+ (BIT_MASK_SEL_0XC0_8822B << BIT_SHIFT_SEL_0XC0_8822B)
+#define BIT_CLEAR_SEL_0XC0_8822B(x) ((x) & (~BITS_SEL_0XC0_8822B))
+#define BIT_GET_SEL_0XC0_8822B(x) \
+ (((x) >> BIT_SHIFT_SEL_0XC0_8822B) & BIT_MASK_SEL_0XC0_8822B)
+#define BIT_SET_SEL_0XC0_8822B(x, v) \
+ (BIT_CLEAR_SEL_0XC0_8822B(x) | BIT_SEL_0XC0_8822B(v))
#define BIT_SHIFT_HCI_SEL_V3_8822B 12
#define BIT_MASK_HCI_SEL_V3_8822B 0x7
-#define BIT_HCI_SEL_V3_8822B(x) (((x) & BIT_MASK_HCI_SEL_V3_8822B) << BIT_SHIFT_HCI_SEL_V3_8822B)
-#define BIT_GET_HCI_SEL_V3_8822B(x) (((x) >> BIT_SHIFT_HCI_SEL_V3_8822B) & BIT_MASK_HCI_SEL_V3_8822B)
+#define BIT_HCI_SEL_V3_8822B(x) \
+ (((x) & BIT_MASK_HCI_SEL_V3_8822B) << BIT_SHIFT_HCI_SEL_V3_8822B)
+#define BITS_HCI_SEL_V3_8822B \
+ (BIT_MASK_HCI_SEL_V3_8822B << BIT_SHIFT_HCI_SEL_V3_8822B)
+#define BIT_CLEAR_HCI_SEL_V3_8822B(x) ((x) & (~BITS_HCI_SEL_V3_8822B))
+#define BIT_GET_HCI_SEL_V3_8822B(x) \
+ (((x) >> BIT_SHIFT_HCI_SEL_V3_8822B) & BIT_MASK_HCI_SEL_V3_8822B)
+#define BIT_SET_HCI_SEL_V3_8822B(x, v) \
+ (BIT_CLEAR_HCI_SEL_V3_8822B(x) | BIT_HCI_SEL_V3_8822B(v))
#define BIT_USB_OPERATION_MODE_8822B BIT(10)
#define BIT_BT_PDN_8822B BIT(9)
@@ -1578,15 +2531,31 @@
#define BIT_SHIFT_PAD_HCI_SEL_V1_8822B 3
#define BIT_MASK_PAD_HCI_SEL_V1_8822B 0x7
-#define BIT_PAD_HCI_SEL_V1_8822B(x) (((x) & BIT_MASK_PAD_HCI_SEL_V1_8822B) << BIT_SHIFT_PAD_HCI_SEL_V1_8822B)
-#define BIT_GET_PAD_HCI_SEL_V1_8822B(x) (((x) >> BIT_SHIFT_PAD_HCI_SEL_V1_8822B) & BIT_MASK_PAD_HCI_SEL_V1_8822B)
-
+#define BIT_PAD_HCI_SEL_V1_8822B(x) \
+ (((x) & BIT_MASK_PAD_HCI_SEL_V1_8822B) \
+ << BIT_SHIFT_PAD_HCI_SEL_V1_8822B)
+#define BITS_PAD_HCI_SEL_V1_8822B \
+ (BIT_MASK_PAD_HCI_SEL_V1_8822B << BIT_SHIFT_PAD_HCI_SEL_V1_8822B)
+#define BIT_CLEAR_PAD_HCI_SEL_V1_8822B(x) ((x) & (~BITS_PAD_HCI_SEL_V1_8822B))
+#define BIT_GET_PAD_HCI_SEL_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_PAD_HCI_SEL_V1_8822B) & \
+ BIT_MASK_PAD_HCI_SEL_V1_8822B)
+#define BIT_SET_PAD_HCI_SEL_V1_8822B(x, v) \
+ (BIT_CLEAR_PAD_HCI_SEL_V1_8822B(x) | BIT_PAD_HCI_SEL_V1_8822B(v))
#define BIT_SHIFT_EFS_HCI_SEL_V1_8822B 0
#define BIT_MASK_EFS_HCI_SEL_V1_8822B 0x7
-#define BIT_EFS_HCI_SEL_V1_8822B(x) (((x) & BIT_MASK_EFS_HCI_SEL_V1_8822B) << BIT_SHIFT_EFS_HCI_SEL_V1_8822B)
-#define BIT_GET_EFS_HCI_SEL_V1_8822B(x) (((x) >> BIT_SHIFT_EFS_HCI_SEL_V1_8822B) & BIT_MASK_EFS_HCI_SEL_V1_8822B)
-
+#define BIT_EFS_HCI_SEL_V1_8822B(x) \
+ (((x) & BIT_MASK_EFS_HCI_SEL_V1_8822B) \
+ << BIT_SHIFT_EFS_HCI_SEL_V1_8822B)
+#define BITS_EFS_HCI_SEL_V1_8822B \
+ (BIT_MASK_EFS_HCI_SEL_V1_8822B << BIT_SHIFT_EFS_HCI_SEL_V1_8822B)
+#define BIT_CLEAR_EFS_HCI_SEL_V1_8822B(x) ((x) & (~BITS_EFS_HCI_SEL_V1_8822B))
+#define BIT_GET_EFS_HCI_SEL_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_EFS_HCI_SEL_V1_8822B) & \
+ BIT_MASK_EFS_HCI_SEL_V1_8822B)
+#define BIT_SET_EFS_HCI_SEL_V1_8822B(x, v) \
+ (BIT_CLEAR_EFS_HCI_SEL_V1_8822B(x) | BIT_EFS_HCI_SEL_V1_8822B(v))
/* 2 REG_SYS_STATUS2_8822B */
#define BIT_SIO_ALDN_8822B BIT(19)
@@ -1596,24 +2565,39 @@
#define BIT_SHIFT_EPVID1_8822B 8
#define BIT_MASK_EPVID1_8822B 0xff
-#define BIT_EPVID1_8822B(x) (((x) & BIT_MASK_EPVID1_8822B) << BIT_SHIFT_EPVID1_8822B)
-#define BIT_GET_EPVID1_8822B(x) (((x) >> BIT_SHIFT_EPVID1_8822B) & BIT_MASK_EPVID1_8822B)
-
+#define BIT_EPVID1_8822B(x) \
+ (((x) & BIT_MASK_EPVID1_8822B) << BIT_SHIFT_EPVID1_8822B)
+#define BITS_EPVID1_8822B (BIT_MASK_EPVID1_8822B << BIT_SHIFT_EPVID1_8822B)
+#define BIT_CLEAR_EPVID1_8822B(x) ((x) & (~BITS_EPVID1_8822B))
+#define BIT_GET_EPVID1_8822B(x) \
+ (((x) >> BIT_SHIFT_EPVID1_8822B) & BIT_MASK_EPVID1_8822B)
+#define BIT_SET_EPVID1_8822B(x, v) \
+ (BIT_CLEAR_EPVID1_8822B(x) | BIT_EPVID1_8822B(v))
#define BIT_SHIFT_EPVID0_8822B 0
#define BIT_MASK_EPVID0_8822B 0xff
-#define BIT_EPVID0_8822B(x) (((x) & BIT_MASK_EPVID0_8822B) << BIT_SHIFT_EPVID0_8822B)
-#define BIT_GET_EPVID0_8822B(x) (((x) >> BIT_SHIFT_EPVID0_8822B) & BIT_MASK_EPVID0_8822B)
-
+#define BIT_EPVID0_8822B(x) \
+ (((x) & BIT_MASK_EPVID0_8822B) << BIT_SHIFT_EPVID0_8822B)
+#define BITS_EPVID0_8822B (BIT_MASK_EPVID0_8822B << BIT_SHIFT_EPVID0_8822B)
+#define BIT_CLEAR_EPVID0_8822B(x) ((x) & (~BITS_EPVID0_8822B))
+#define BIT_GET_EPVID0_8822B(x) \
+ (((x) >> BIT_SHIFT_EPVID0_8822B) & BIT_MASK_EPVID0_8822B)
+#define BIT_SET_EPVID0_8822B(x, v) \
+ (BIT_CLEAR_EPVID0_8822B(x) | BIT_EPVID0_8822B(v))
/* 2 REG_SYS_CFG2_8822B */
-#define BIT_HCI_SEL_EMBEDED_8822B BIT(8)
+#define BIT_HCI_SEL_EMBEDDED_8822B BIT(8)
#define BIT_SHIFT_HW_ID_8822B 0
#define BIT_MASK_HW_ID_8822B 0xff
-#define BIT_HW_ID_8822B(x) (((x) & BIT_MASK_HW_ID_8822B) << BIT_SHIFT_HW_ID_8822B)
-#define BIT_GET_HW_ID_8822B(x) (((x) >> BIT_SHIFT_HW_ID_8822B) & BIT_MASK_HW_ID_8822B)
-
+#define BIT_HW_ID_8822B(x) \
+ (((x) & BIT_MASK_HW_ID_8822B) << BIT_SHIFT_HW_ID_8822B)
+#define BITS_HW_ID_8822B (BIT_MASK_HW_ID_8822B << BIT_SHIFT_HW_ID_8822B)
+#define BIT_CLEAR_HW_ID_8822B(x) ((x) & (~BITS_HW_ID_8822B))
+#define BIT_GET_HW_ID_8822B(x) \
+ (((x) >> BIT_SHIFT_HW_ID_8822B) & BIT_MASK_HW_ID_8822B)
+#define BIT_SET_HW_ID_8822B(x, v) \
+ (BIT_CLEAR_HW_ID_8822B(x) | BIT_HW_ID_8822B(v))
/* 2 REG_SYS_CFG3_8822B */
#define BIT_PWC_MA33V_8822B BIT(15)
@@ -1641,17 +2625,31 @@
#define BIT_SHIFT_CPU_DMEM_CON_8822B 0
#define BIT_MASK_CPU_DMEM_CON_8822B 0xff
-#define BIT_CPU_DMEM_CON_8822B(x) (((x) & BIT_MASK_CPU_DMEM_CON_8822B) << BIT_SHIFT_CPU_DMEM_CON_8822B)
-#define BIT_GET_CPU_DMEM_CON_8822B(x) (((x) >> BIT_SHIFT_CPU_DMEM_CON_8822B) & BIT_MASK_CPU_DMEM_CON_8822B)
-
+#define BIT_CPU_DMEM_CON_8822B(x) \
+ (((x) & BIT_MASK_CPU_DMEM_CON_8822B) << BIT_SHIFT_CPU_DMEM_CON_8822B)
+#define BITS_CPU_DMEM_CON_8822B \
+ (BIT_MASK_CPU_DMEM_CON_8822B << BIT_SHIFT_CPU_DMEM_CON_8822B)
+#define BIT_CLEAR_CPU_DMEM_CON_8822B(x) ((x) & (~BITS_CPU_DMEM_CON_8822B))
+#define BIT_GET_CPU_DMEM_CON_8822B(x) \
+ (((x) >> BIT_SHIFT_CPU_DMEM_CON_8822B) & BIT_MASK_CPU_DMEM_CON_8822B)
+#define BIT_SET_CPU_DMEM_CON_8822B(x, v) \
+ (BIT_CLEAR_CPU_DMEM_CON_8822B(x) | BIT_CPU_DMEM_CON_8822B(v))
/* 2 REG_BOOT_REASON_8822B */
-#define BIT_SHIFT_BOOT_REASON_8822B 0
-#define BIT_MASK_BOOT_REASON_8822B 0x7
-#define BIT_BOOT_REASON_8822B(x) (((x) & BIT_MASK_BOOT_REASON_8822B) << BIT_SHIFT_BOOT_REASON_8822B)
-#define BIT_GET_BOOT_REASON_8822B(x) (((x) >> BIT_SHIFT_BOOT_REASON_8822B) & BIT_MASK_BOOT_REASON_8822B)
-
+#define BIT_SHIFT_BOOT_REASON_V1_8822B 0
+#define BIT_MASK_BOOT_REASON_V1_8822B 0x7
+#define BIT_BOOT_REASON_V1_8822B(x) \
+ (((x) & BIT_MASK_BOOT_REASON_V1_8822B) \
+ << BIT_SHIFT_BOOT_REASON_V1_8822B)
+#define BITS_BOOT_REASON_V1_8822B \
+ (BIT_MASK_BOOT_REASON_V1_8822B << BIT_SHIFT_BOOT_REASON_V1_8822B)
+#define BIT_CLEAR_BOOT_REASON_V1_8822B(x) ((x) & (~BITS_BOOT_REASON_V1_8822B))
+#define BIT_GET_BOOT_REASON_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_BOOT_REASON_V1_8822B) & \
+ BIT_MASK_BOOT_REASON_V1_8822B)
+#define BIT_SET_BOOT_REASON_V1_8822B(x, v) \
+ (BIT_CLEAR_BOOT_REASON_V1_8822B(x) | BIT_BOOT_REASON_V1_8822B(v))
/* 2 REG_NFCPAD_CTRL_8822B */
#define BIT_PAD_SHUTDW_8822B BIT(18)
@@ -1664,21 +2662,39 @@
#define BIT_SHIFT_NFCPAD_IO_SEL_8822B 8
#define BIT_MASK_NFCPAD_IO_SEL_8822B 0xf
-#define BIT_NFCPAD_IO_SEL_8822B(x) (((x) & BIT_MASK_NFCPAD_IO_SEL_8822B) << BIT_SHIFT_NFCPAD_IO_SEL_8822B)
-#define BIT_GET_NFCPAD_IO_SEL_8822B(x) (((x) >> BIT_SHIFT_NFCPAD_IO_SEL_8822B) & BIT_MASK_NFCPAD_IO_SEL_8822B)
-
+#define BIT_NFCPAD_IO_SEL_8822B(x) \
+ (((x) & BIT_MASK_NFCPAD_IO_SEL_8822B) << BIT_SHIFT_NFCPAD_IO_SEL_8822B)
+#define BITS_NFCPAD_IO_SEL_8822B \
+ (BIT_MASK_NFCPAD_IO_SEL_8822B << BIT_SHIFT_NFCPAD_IO_SEL_8822B)
+#define BIT_CLEAR_NFCPAD_IO_SEL_8822B(x) ((x) & (~BITS_NFCPAD_IO_SEL_8822B))
+#define BIT_GET_NFCPAD_IO_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_NFCPAD_IO_SEL_8822B) & BIT_MASK_NFCPAD_IO_SEL_8822B)
+#define BIT_SET_NFCPAD_IO_SEL_8822B(x, v) \
+ (BIT_CLEAR_NFCPAD_IO_SEL_8822B(x) | BIT_NFCPAD_IO_SEL_8822B(v))
#define BIT_SHIFT_NFCPAD_OUT_8822B 4
#define BIT_MASK_NFCPAD_OUT_8822B 0xf
-#define BIT_NFCPAD_OUT_8822B(x) (((x) & BIT_MASK_NFCPAD_OUT_8822B) << BIT_SHIFT_NFCPAD_OUT_8822B)
-#define BIT_GET_NFCPAD_OUT_8822B(x) (((x) >> BIT_SHIFT_NFCPAD_OUT_8822B) & BIT_MASK_NFCPAD_OUT_8822B)
-
+#define BIT_NFCPAD_OUT_8822B(x) \
+ (((x) & BIT_MASK_NFCPAD_OUT_8822B) << BIT_SHIFT_NFCPAD_OUT_8822B)
+#define BITS_NFCPAD_OUT_8822B \
+ (BIT_MASK_NFCPAD_OUT_8822B << BIT_SHIFT_NFCPAD_OUT_8822B)
+#define BIT_CLEAR_NFCPAD_OUT_8822B(x) ((x) & (~BITS_NFCPAD_OUT_8822B))
+#define BIT_GET_NFCPAD_OUT_8822B(x) \
+ (((x) >> BIT_SHIFT_NFCPAD_OUT_8822B) & BIT_MASK_NFCPAD_OUT_8822B)
+#define BIT_SET_NFCPAD_OUT_8822B(x, v) \
+ (BIT_CLEAR_NFCPAD_OUT_8822B(x) | BIT_NFCPAD_OUT_8822B(v))
#define BIT_SHIFT_NFCPAD_IN_8822B 0
#define BIT_MASK_NFCPAD_IN_8822B 0xf
-#define BIT_NFCPAD_IN_8822B(x) (((x) & BIT_MASK_NFCPAD_IN_8822B) << BIT_SHIFT_NFCPAD_IN_8822B)
-#define BIT_GET_NFCPAD_IN_8822B(x) (((x) >> BIT_SHIFT_NFCPAD_IN_8822B) & BIT_MASK_NFCPAD_IN_8822B)
-
+#define BIT_NFCPAD_IN_8822B(x) \
+ (((x) & BIT_MASK_NFCPAD_IN_8822B) << BIT_SHIFT_NFCPAD_IN_8822B)
+#define BITS_NFCPAD_IN_8822B \
+ (BIT_MASK_NFCPAD_IN_8822B << BIT_SHIFT_NFCPAD_IN_8822B)
+#define BIT_CLEAR_NFCPAD_IN_8822B(x) ((x) & (~BITS_NFCPAD_IN_8822B))
+#define BIT_GET_NFCPAD_IN_8822B(x) \
+ (((x) >> BIT_SHIFT_NFCPAD_IN_8822B) & BIT_MASK_NFCPAD_IN_8822B)
+#define BIT_SET_NFCPAD_IN_8822B(x, v) \
+ (BIT_CLEAR_NFCPAD_IN_8822B(x) | BIT_NFCPAD_IN_8822B(v))
/* 2 REG_HIMR2_8822B */
#define BIT_BCNDMAINT_P4_MSK_8822B BIT(31)
@@ -1798,17 +2814,35 @@
#define BIT_SHIFT_H2C_PKT_READADDR_8822B 0
#define BIT_MASK_H2C_PKT_READADDR_8822B 0x3ffff
-#define BIT_H2C_PKT_READADDR_8822B(x) (((x) & BIT_MASK_H2C_PKT_READADDR_8822B) << BIT_SHIFT_H2C_PKT_READADDR_8822B)
-#define BIT_GET_H2C_PKT_READADDR_8822B(x) (((x) >> BIT_SHIFT_H2C_PKT_READADDR_8822B) & BIT_MASK_H2C_PKT_READADDR_8822B)
-
+#define BIT_H2C_PKT_READADDR_8822B(x) \
+ (((x) & BIT_MASK_H2C_PKT_READADDR_8822B) \
+ << BIT_SHIFT_H2C_PKT_READADDR_8822B)
+#define BITS_H2C_PKT_READADDR_8822B \
+ (BIT_MASK_H2C_PKT_READADDR_8822B << BIT_SHIFT_H2C_PKT_READADDR_8822B)
+#define BIT_CLEAR_H2C_PKT_READADDR_8822B(x) \
+ ((x) & (~BITS_H2C_PKT_READADDR_8822B))
+#define BIT_GET_H2C_PKT_READADDR_8822B(x) \
+ (((x) >> BIT_SHIFT_H2C_PKT_READADDR_8822B) & \
+ BIT_MASK_H2C_PKT_READADDR_8822B)
+#define BIT_SET_H2C_PKT_READADDR_8822B(x, v) \
+ (BIT_CLEAR_H2C_PKT_READADDR_8822B(x) | BIT_H2C_PKT_READADDR_8822B(v))
/* 2 REG_H2C_PKT_WRITEADDR_8822B */
#define BIT_SHIFT_H2C_PKT_WRITEADDR_8822B 0
#define BIT_MASK_H2C_PKT_WRITEADDR_8822B 0x3ffff
-#define BIT_H2C_PKT_WRITEADDR_8822B(x) (((x) & BIT_MASK_H2C_PKT_WRITEADDR_8822B) << BIT_SHIFT_H2C_PKT_WRITEADDR_8822B)
-#define BIT_GET_H2C_PKT_WRITEADDR_8822B(x) (((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR_8822B) & BIT_MASK_H2C_PKT_WRITEADDR_8822B)
-
+#define BIT_H2C_PKT_WRITEADDR_8822B(x) \
+ (((x) & BIT_MASK_H2C_PKT_WRITEADDR_8822B) \
+ << BIT_SHIFT_H2C_PKT_WRITEADDR_8822B)
+#define BITS_H2C_PKT_WRITEADDR_8822B \
+ (BIT_MASK_H2C_PKT_WRITEADDR_8822B << BIT_SHIFT_H2C_PKT_WRITEADDR_8822B)
+#define BIT_CLEAR_H2C_PKT_WRITEADDR_8822B(x) \
+ ((x) & (~BITS_H2C_PKT_WRITEADDR_8822B))
+#define BIT_GET_H2C_PKT_WRITEADDR_8822B(x) \
+ (((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR_8822B) & \
+ BIT_MASK_H2C_PKT_WRITEADDR_8822B)
+#define BIT_SET_H2C_PKT_WRITEADDR_8822B(x, v) \
+ (BIT_CLEAR_H2C_PKT_WRITEADDR_8822B(x) | BIT_H2C_PKT_WRITEADDR_8822B(v))
/* 2 REG_MEM_PWR_CRTL_8822B */
#define BIT_MEM_BB_SD_8822B BIT(17)
@@ -1829,65 +2863,105 @@
#define BIT_SHIFT_FW_DBG0_8822B 0
#define BIT_MASK_FW_DBG0_8822B 0xffffffffL
-#define BIT_FW_DBG0_8822B(x) (((x) & BIT_MASK_FW_DBG0_8822B) << BIT_SHIFT_FW_DBG0_8822B)
-#define BIT_GET_FW_DBG0_8822B(x) (((x) >> BIT_SHIFT_FW_DBG0_8822B) & BIT_MASK_FW_DBG0_8822B)
-
+#define BIT_FW_DBG0_8822B(x) \
+ (((x) & BIT_MASK_FW_DBG0_8822B) << BIT_SHIFT_FW_DBG0_8822B)
+#define BITS_FW_DBG0_8822B (BIT_MASK_FW_DBG0_8822B << BIT_SHIFT_FW_DBG0_8822B)
+#define BIT_CLEAR_FW_DBG0_8822B(x) ((x) & (~BITS_FW_DBG0_8822B))
+#define BIT_GET_FW_DBG0_8822B(x) \
+ (((x) >> BIT_SHIFT_FW_DBG0_8822B) & BIT_MASK_FW_DBG0_8822B)
+#define BIT_SET_FW_DBG0_8822B(x, v) \
+ (BIT_CLEAR_FW_DBG0_8822B(x) | BIT_FW_DBG0_8822B(v))
/* 2 REG_FW_DBG1_8822B */
#define BIT_SHIFT_FW_DBG1_8822B 0
#define BIT_MASK_FW_DBG1_8822B 0xffffffffL
-#define BIT_FW_DBG1_8822B(x) (((x) & BIT_MASK_FW_DBG1_8822B) << BIT_SHIFT_FW_DBG1_8822B)
-#define BIT_GET_FW_DBG1_8822B(x) (((x) >> BIT_SHIFT_FW_DBG1_8822B) & BIT_MASK_FW_DBG1_8822B)
-
+#define BIT_FW_DBG1_8822B(x) \
+ (((x) & BIT_MASK_FW_DBG1_8822B) << BIT_SHIFT_FW_DBG1_8822B)
+#define BITS_FW_DBG1_8822B (BIT_MASK_FW_DBG1_8822B << BIT_SHIFT_FW_DBG1_8822B)
+#define BIT_CLEAR_FW_DBG1_8822B(x) ((x) & (~BITS_FW_DBG1_8822B))
+#define BIT_GET_FW_DBG1_8822B(x) \
+ (((x) >> BIT_SHIFT_FW_DBG1_8822B) & BIT_MASK_FW_DBG1_8822B)
+#define BIT_SET_FW_DBG1_8822B(x, v) \
+ (BIT_CLEAR_FW_DBG1_8822B(x) | BIT_FW_DBG1_8822B(v))
/* 2 REG_FW_DBG2_8822B */
#define BIT_SHIFT_FW_DBG2_8822B 0
#define BIT_MASK_FW_DBG2_8822B 0xffffffffL
-#define BIT_FW_DBG2_8822B(x) (((x) & BIT_MASK_FW_DBG2_8822B) << BIT_SHIFT_FW_DBG2_8822B)
-#define BIT_GET_FW_DBG2_8822B(x) (((x) >> BIT_SHIFT_FW_DBG2_8822B) & BIT_MASK_FW_DBG2_8822B)
-
+#define BIT_FW_DBG2_8822B(x) \
+ (((x) & BIT_MASK_FW_DBG2_8822B) << BIT_SHIFT_FW_DBG2_8822B)
+#define BITS_FW_DBG2_8822B (BIT_MASK_FW_DBG2_8822B << BIT_SHIFT_FW_DBG2_8822B)
+#define BIT_CLEAR_FW_DBG2_8822B(x) ((x) & (~BITS_FW_DBG2_8822B))
+#define BIT_GET_FW_DBG2_8822B(x) \
+ (((x) >> BIT_SHIFT_FW_DBG2_8822B) & BIT_MASK_FW_DBG2_8822B)
+#define BIT_SET_FW_DBG2_8822B(x, v) \
+ (BIT_CLEAR_FW_DBG2_8822B(x) | BIT_FW_DBG2_8822B(v))
/* 2 REG_FW_DBG3_8822B */
#define BIT_SHIFT_FW_DBG3_8822B 0
#define BIT_MASK_FW_DBG3_8822B 0xffffffffL
-#define BIT_FW_DBG3_8822B(x) (((x) & BIT_MASK_FW_DBG3_8822B) << BIT_SHIFT_FW_DBG3_8822B)
-#define BIT_GET_FW_DBG3_8822B(x) (((x) >> BIT_SHIFT_FW_DBG3_8822B) & BIT_MASK_FW_DBG3_8822B)
-
+#define BIT_FW_DBG3_8822B(x) \
+ (((x) & BIT_MASK_FW_DBG3_8822B) << BIT_SHIFT_FW_DBG3_8822B)
+#define BITS_FW_DBG3_8822B (BIT_MASK_FW_DBG3_8822B << BIT_SHIFT_FW_DBG3_8822B)
+#define BIT_CLEAR_FW_DBG3_8822B(x) ((x) & (~BITS_FW_DBG3_8822B))
+#define BIT_GET_FW_DBG3_8822B(x) \
+ (((x) >> BIT_SHIFT_FW_DBG3_8822B) & BIT_MASK_FW_DBG3_8822B)
+#define BIT_SET_FW_DBG3_8822B(x, v) \
+ (BIT_CLEAR_FW_DBG3_8822B(x) | BIT_FW_DBG3_8822B(v))
/* 2 REG_FW_DBG4_8822B */
#define BIT_SHIFT_FW_DBG4_8822B 0
#define BIT_MASK_FW_DBG4_8822B 0xffffffffL
-#define BIT_FW_DBG4_8822B(x) (((x) & BIT_MASK_FW_DBG4_8822B) << BIT_SHIFT_FW_DBG4_8822B)
-#define BIT_GET_FW_DBG4_8822B(x) (((x) >> BIT_SHIFT_FW_DBG4_8822B) & BIT_MASK_FW_DBG4_8822B)
-
+#define BIT_FW_DBG4_8822B(x) \
+ (((x) & BIT_MASK_FW_DBG4_8822B) << BIT_SHIFT_FW_DBG4_8822B)
+#define BITS_FW_DBG4_8822B (BIT_MASK_FW_DBG4_8822B << BIT_SHIFT_FW_DBG4_8822B)
+#define BIT_CLEAR_FW_DBG4_8822B(x) ((x) & (~BITS_FW_DBG4_8822B))
+#define BIT_GET_FW_DBG4_8822B(x) \
+ (((x) >> BIT_SHIFT_FW_DBG4_8822B) & BIT_MASK_FW_DBG4_8822B)
+#define BIT_SET_FW_DBG4_8822B(x, v) \
+ (BIT_CLEAR_FW_DBG4_8822B(x) | BIT_FW_DBG4_8822B(v))
/* 2 REG_FW_DBG5_8822B */
#define BIT_SHIFT_FW_DBG5_8822B 0
#define BIT_MASK_FW_DBG5_8822B 0xffffffffL
-#define BIT_FW_DBG5_8822B(x) (((x) & BIT_MASK_FW_DBG5_8822B) << BIT_SHIFT_FW_DBG5_8822B)
-#define BIT_GET_FW_DBG5_8822B(x) (((x) >> BIT_SHIFT_FW_DBG5_8822B) & BIT_MASK_FW_DBG5_8822B)
-
+#define BIT_FW_DBG5_8822B(x) \
+ (((x) & BIT_MASK_FW_DBG5_8822B) << BIT_SHIFT_FW_DBG5_8822B)
+#define BITS_FW_DBG5_8822B (BIT_MASK_FW_DBG5_8822B << BIT_SHIFT_FW_DBG5_8822B)
+#define BIT_CLEAR_FW_DBG5_8822B(x) ((x) & (~BITS_FW_DBG5_8822B))
+#define BIT_GET_FW_DBG5_8822B(x) \
+ (((x) >> BIT_SHIFT_FW_DBG5_8822B) & BIT_MASK_FW_DBG5_8822B)
+#define BIT_SET_FW_DBG5_8822B(x, v) \
+ (BIT_CLEAR_FW_DBG5_8822B(x) | BIT_FW_DBG5_8822B(v))
/* 2 REG_FW_DBG6_8822B */
#define BIT_SHIFT_FW_DBG6_8822B 0
#define BIT_MASK_FW_DBG6_8822B 0xffffffffL
-#define BIT_FW_DBG6_8822B(x) (((x) & BIT_MASK_FW_DBG6_8822B) << BIT_SHIFT_FW_DBG6_8822B)
-#define BIT_GET_FW_DBG6_8822B(x) (((x) >> BIT_SHIFT_FW_DBG6_8822B) & BIT_MASK_FW_DBG6_8822B)
-
+#define BIT_FW_DBG6_8822B(x) \
+ (((x) & BIT_MASK_FW_DBG6_8822B) << BIT_SHIFT_FW_DBG6_8822B)
+#define BITS_FW_DBG6_8822B (BIT_MASK_FW_DBG6_8822B << BIT_SHIFT_FW_DBG6_8822B)
+#define BIT_CLEAR_FW_DBG6_8822B(x) ((x) & (~BITS_FW_DBG6_8822B))
+#define BIT_GET_FW_DBG6_8822B(x) \
+ (((x) >> BIT_SHIFT_FW_DBG6_8822B) & BIT_MASK_FW_DBG6_8822B)
+#define BIT_SET_FW_DBG6_8822B(x, v) \
+ (BIT_CLEAR_FW_DBG6_8822B(x) | BIT_FW_DBG6_8822B(v))
/* 2 REG_FW_DBG7_8822B */
#define BIT_SHIFT_FW_DBG7_8822B 0
#define BIT_MASK_FW_DBG7_8822B 0xffffffffL
-#define BIT_FW_DBG7_8822B(x) (((x) & BIT_MASK_FW_DBG7_8822B) << BIT_SHIFT_FW_DBG7_8822B)
-#define BIT_GET_FW_DBG7_8822B(x) (((x) >> BIT_SHIFT_FW_DBG7_8822B) & BIT_MASK_FW_DBG7_8822B)
-
+#define BIT_FW_DBG7_8822B(x) \
+ (((x) & BIT_MASK_FW_DBG7_8822B) << BIT_SHIFT_FW_DBG7_8822B)
+#define BITS_FW_DBG7_8822B (BIT_MASK_FW_DBG7_8822B << BIT_SHIFT_FW_DBG7_8822B)
+#define BIT_CLEAR_FW_DBG7_8822B(x) ((x) & (~BITS_FW_DBG7_8822B))
+#define BIT_GET_FW_DBG7_8822B(x) \
+ (((x) >> BIT_SHIFT_FW_DBG7_8822B) & BIT_MASK_FW_DBG7_8822B)
+#define BIT_SET_FW_DBG7_8822B(x, v) \
+ (BIT_CLEAR_FW_DBG7_8822B(x) | BIT_FW_DBG7_8822B(v))
/* 2 REG_NOT_VALID_8822B */
@@ -1895,20 +2969,36 @@
#define BIT_SHIFT_LBMODE_8822B 24
#define BIT_MASK_LBMODE_8822B 0x1f
-#define BIT_LBMODE_8822B(x) (((x) & BIT_MASK_LBMODE_8822B) << BIT_SHIFT_LBMODE_8822B)
-#define BIT_GET_LBMODE_8822B(x) (((x) >> BIT_SHIFT_LBMODE_8822B) & BIT_MASK_LBMODE_8822B)
-
+#define BIT_LBMODE_8822B(x) \
+ (((x) & BIT_MASK_LBMODE_8822B) << BIT_SHIFT_LBMODE_8822B)
+#define BITS_LBMODE_8822B (BIT_MASK_LBMODE_8822B << BIT_SHIFT_LBMODE_8822B)
+#define BIT_CLEAR_LBMODE_8822B(x) ((x) & (~BITS_LBMODE_8822B))
+#define BIT_GET_LBMODE_8822B(x) \
+ (((x) >> BIT_SHIFT_LBMODE_8822B) & BIT_MASK_LBMODE_8822B)
+#define BIT_SET_LBMODE_8822B(x, v) \
+ (BIT_CLEAR_LBMODE_8822B(x) | BIT_LBMODE_8822B(v))
#define BIT_SHIFT_NETYPE1_8822B 18
#define BIT_MASK_NETYPE1_8822B 0x3
-#define BIT_NETYPE1_8822B(x) (((x) & BIT_MASK_NETYPE1_8822B) << BIT_SHIFT_NETYPE1_8822B)
-#define BIT_GET_NETYPE1_8822B(x) (((x) >> BIT_SHIFT_NETYPE1_8822B) & BIT_MASK_NETYPE1_8822B)
-
+#define BIT_NETYPE1_8822B(x) \
+ (((x) & BIT_MASK_NETYPE1_8822B) << BIT_SHIFT_NETYPE1_8822B)
+#define BITS_NETYPE1_8822B (BIT_MASK_NETYPE1_8822B << BIT_SHIFT_NETYPE1_8822B)
+#define BIT_CLEAR_NETYPE1_8822B(x) ((x) & (~BITS_NETYPE1_8822B))
+#define BIT_GET_NETYPE1_8822B(x) \
+ (((x) >> BIT_SHIFT_NETYPE1_8822B) & BIT_MASK_NETYPE1_8822B)
+#define BIT_SET_NETYPE1_8822B(x, v) \
+ (BIT_CLEAR_NETYPE1_8822B(x) | BIT_NETYPE1_8822B(v))
#define BIT_SHIFT_NETYPE0_8822B 16
#define BIT_MASK_NETYPE0_8822B 0x3
-#define BIT_NETYPE0_8822B(x) (((x) & BIT_MASK_NETYPE0_8822B) << BIT_SHIFT_NETYPE0_8822B)
-#define BIT_GET_NETYPE0_8822B(x) (((x) >> BIT_SHIFT_NETYPE0_8822B) & BIT_MASK_NETYPE0_8822B)
+#define BIT_NETYPE0_8822B(x) \
+ (((x) & BIT_MASK_NETYPE0_8822B) << BIT_SHIFT_NETYPE0_8822B)
+#define BITS_NETYPE0_8822B (BIT_MASK_NETYPE0_8822B << BIT_SHIFT_NETYPE0_8822B)
+#define BIT_CLEAR_NETYPE0_8822B(x) ((x) & (~BITS_NETYPE0_8822B))
+#define BIT_GET_NETYPE0_8822B(x) \
+ (((x) >> BIT_SHIFT_NETYPE0_8822B) & BIT_MASK_NETYPE0_8822B)
+#define BIT_SET_NETYPE0_8822B(x, v) \
+ (BIT_CLEAR_NETYPE0_8822B(x) | BIT_NETYPE0_8822B(v))
#define BIT_I2C_MAILBOX_EN_8822B BIT(12)
#define BIT_SHCUT_EN_8822B BIT(11)
@@ -1931,38 +3021,75 @@
#define BIT_SHIFT_TXDMA_HIQ_MAP_8822B 14
#define BIT_MASK_TXDMA_HIQ_MAP_8822B 0x3
-#define BIT_TXDMA_HIQ_MAP_8822B(x) (((x) & BIT_MASK_TXDMA_HIQ_MAP_8822B) << BIT_SHIFT_TXDMA_HIQ_MAP_8822B)
-#define BIT_GET_TXDMA_HIQ_MAP_8822B(x) (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8822B) & BIT_MASK_TXDMA_HIQ_MAP_8822B)
-
+#define BIT_TXDMA_HIQ_MAP_8822B(x) \
+ (((x) & BIT_MASK_TXDMA_HIQ_MAP_8822B) << BIT_SHIFT_TXDMA_HIQ_MAP_8822B)
+#define BITS_TXDMA_HIQ_MAP_8822B \
+ (BIT_MASK_TXDMA_HIQ_MAP_8822B << BIT_SHIFT_TXDMA_HIQ_MAP_8822B)
+#define BIT_CLEAR_TXDMA_HIQ_MAP_8822B(x) ((x) & (~BITS_TXDMA_HIQ_MAP_8822B))
+#define BIT_GET_TXDMA_HIQ_MAP_8822B(x) \
+ (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8822B) & BIT_MASK_TXDMA_HIQ_MAP_8822B)
+#define BIT_SET_TXDMA_HIQ_MAP_8822B(x, v) \
+ (BIT_CLEAR_TXDMA_HIQ_MAP_8822B(x) | BIT_TXDMA_HIQ_MAP_8822B(v))
#define BIT_SHIFT_TXDMA_MGQ_MAP_8822B 12
#define BIT_MASK_TXDMA_MGQ_MAP_8822B 0x3
-#define BIT_TXDMA_MGQ_MAP_8822B(x) (((x) & BIT_MASK_TXDMA_MGQ_MAP_8822B) << BIT_SHIFT_TXDMA_MGQ_MAP_8822B)
-#define BIT_GET_TXDMA_MGQ_MAP_8822B(x) (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8822B) & BIT_MASK_TXDMA_MGQ_MAP_8822B)
-
+#define BIT_TXDMA_MGQ_MAP_8822B(x) \
+ (((x) & BIT_MASK_TXDMA_MGQ_MAP_8822B) << BIT_SHIFT_TXDMA_MGQ_MAP_8822B)
+#define BITS_TXDMA_MGQ_MAP_8822B \
+ (BIT_MASK_TXDMA_MGQ_MAP_8822B << BIT_SHIFT_TXDMA_MGQ_MAP_8822B)
+#define BIT_CLEAR_TXDMA_MGQ_MAP_8822B(x) ((x) & (~BITS_TXDMA_MGQ_MAP_8822B))
+#define BIT_GET_TXDMA_MGQ_MAP_8822B(x) \
+ (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8822B) & BIT_MASK_TXDMA_MGQ_MAP_8822B)
+#define BIT_SET_TXDMA_MGQ_MAP_8822B(x, v) \
+ (BIT_CLEAR_TXDMA_MGQ_MAP_8822B(x) | BIT_TXDMA_MGQ_MAP_8822B(v))
#define BIT_SHIFT_TXDMA_BKQ_MAP_8822B 10
#define BIT_MASK_TXDMA_BKQ_MAP_8822B 0x3
-#define BIT_TXDMA_BKQ_MAP_8822B(x) (((x) & BIT_MASK_TXDMA_BKQ_MAP_8822B) << BIT_SHIFT_TXDMA_BKQ_MAP_8822B)
-#define BIT_GET_TXDMA_BKQ_MAP_8822B(x) (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8822B) & BIT_MASK_TXDMA_BKQ_MAP_8822B)
-
+#define BIT_TXDMA_BKQ_MAP_8822B(x) \
+ (((x) & BIT_MASK_TXDMA_BKQ_MAP_8822B) << BIT_SHIFT_TXDMA_BKQ_MAP_8822B)
+#define BITS_TXDMA_BKQ_MAP_8822B \
+ (BIT_MASK_TXDMA_BKQ_MAP_8822B << BIT_SHIFT_TXDMA_BKQ_MAP_8822B)
+#define BIT_CLEAR_TXDMA_BKQ_MAP_8822B(x) ((x) & (~BITS_TXDMA_BKQ_MAP_8822B))
+#define BIT_GET_TXDMA_BKQ_MAP_8822B(x) \
+ (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8822B) & BIT_MASK_TXDMA_BKQ_MAP_8822B)
+#define BIT_SET_TXDMA_BKQ_MAP_8822B(x, v) \
+ (BIT_CLEAR_TXDMA_BKQ_MAP_8822B(x) | BIT_TXDMA_BKQ_MAP_8822B(v))
#define BIT_SHIFT_TXDMA_BEQ_MAP_8822B 8
#define BIT_MASK_TXDMA_BEQ_MAP_8822B 0x3
-#define BIT_TXDMA_BEQ_MAP_8822B(x) (((x) & BIT_MASK_TXDMA_BEQ_MAP_8822B) << BIT_SHIFT_TXDMA_BEQ_MAP_8822B)
-#define BIT_GET_TXDMA_BEQ_MAP_8822B(x) (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8822B) & BIT_MASK_TXDMA_BEQ_MAP_8822B)
-
+#define BIT_TXDMA_BEQ_MAP_8822B(x) \
+ (((x) & BIT_MASK_TXDMA_BEQ_MAP_8822B) << BIT_SHIFT_TXDMA_BEQ_MAP_8822B)
+#define BITS_TXDMA_BEQ_MAP_8822B \
+ (BIT_MASK_TXDMA_BEQ_MAP_8822B << BIT_SHIFT_TXDMA_BEQ_MAP_8822B)
+#define BIT_CLEAR_TXDMA_BEQ_MAP_8822B(x) ((x) & (~BITS_TXDMA_BEQ_MAP_8822B))
+#define BIT_GET_TXDMA_BEQ_MAP_8822B(x) \
+ (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8822B) & BIT_MASK_TXDMA_BEQ_MAP_8822B)
+#define BIT_SET_TXDMA_BEQ_MAP_8822B(x, v) \
+ (BIT_CLEAR_TXDMA_BEQ_MAP_8822B(x) | BIT_TXDMA_BEQ_MAP_8822B(v))
#define BIT_SHIFT_TXDMA_VIQ_MAP_8822B 6
#define BIT_MASK_TXDMA_VIQ_MAP_8822B 0x3
-#define BIT_TXDMA_VIQ_MAP_8822B(x) (((x) & BIT_MASK_TXDMA_VIQ_MAP_8822B) << BIT_SHIFT_TXDMA_VIQ_MAP_8822B)
-#define BIT_GET_TXDMA_VIQ_MAP_8822B(x) (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8822B) & BIT_MASK_TXDMA_VIQ_MAP_8822B)
-
+#define BIT_TXDMA_VIQ_MAP_8822B(x) \
+ (((x) & BIT_MASK_TXDMA_VIQ_MAP_8822B) << BIT_SHIFT_TXDMA_VIQ_MAP_8822B)
+#define BITS_TXDMA_VIQ_MAP_8822B \
+ (BIT_MASK_TXDMA_VIQ_MAP_8822B << BIT_SHIFT_TXDMA_VIQ_MAP_8822B)
+#define BIT_CLEAR_TXDMA_VIQ_MAP_8822B(x) ((x) & (~BITS_TXDMA_VIQ_MAP_8822B))
+#define BIT_GET_TXDMA_VIQ_MAP_8822B(x) \
+ (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8822B) & BIT_MASK_TXDMA_VIQ_MAP_8822B)
+#define BIT_SET_TXDMA_VIQ_MAP_8822B(x, v) \
+ (BIT_CLEAR_TXDMA_VIQ_MAP_8822B(x) | BIT_TXDMA_VIQ_MAP_8822B(v))
#define BIT_SHIFT_TXDMA_VOQ_MAP_8822B 4
#define BIT_MASK_TXDMA_VOQ_MAP_8822B 0x3
-#define BIT_TXDMA_VOQ_MAP_8822B(x) (((x) & BIT_MASK_TXDMA_VOQ_MAP_8822B) << BIT_SHIFT_TXDMA_VOQ_MAP_8822B)
-#define BIT_GET_TXDMA_VOQ_MAP_8822B(x) (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8822B) & BIT_MASK_TXDMA_VOQ_MAP_8822B)
+#define BIT_TXDMA_VOQ_MAP_8822B(x) \
+ (((x) & BIT_MASK_TXDMA_VOQ_MAP_8822B) << BIT_SHIFT_TXDMA_VOQ_MAP_8822B)
+#define BITS_TXDMA_VOQ_MAP_8822B \
+ (BIT_MASK_TXDMA_VOQ_MAP_8822B << BIT_SHIFT_TXDMA_VOQ_MAP_8822B)
+#define BIT_CLEAR_TXDMA_VOQ_MAP_8822B(x) ((x) & (~BITS_TXDMA_VOQ_MAP_8822B))
+#define BIT_GET_TXDMA_VOQ_MAP_8822B(x) \
+ (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8822B) & BIT_MASK_TXDMA_VOQ_MAP_8822B)
+#define BIT_SET_TXDMA_VOQ_MAP_8822B(x, v) \
+ (BIT_CLEAR_TXDMA_VOQ_MAP_8822B(x) | BIT_TXDMA_VOQ_MAP_8822B(v))
#define BIT_RXDMA_AGG_EN_8822B BIT(2)
#define BIT_RXSHFT_EN_8822B BIT(1)
@@ -1972,15 +3099,31 @@
#define BIT_SHIFT_RXFFOVFL_RSV_V2_8822B 8
#define BIT_MASK_RXFFOVFL_RSV_V2_8822B 0xf
-#define BIT_RXFFOVFL_RSV_V2_8822B(x) (((x) & BIT_MASK_RXFFOVFL_RSV_V2_8822B) << BIT_SHIFT_RXFFOVFL_RSV_V2_8822B)
-#define BIT_GET_RXFFOVFL_RSV_V2_8822B(x) (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8822B) & BIT_MASK_RXFFOVFL_RSV_V2_8822B)
-
+#define BIT_RXFFOVFL_RSV_V2_8822B(x) \
+ (((x) & BIT_MASK_RXFFOVFL_RSV_V2_8822B) \
+ << BIT_SHIFT_RXFFOVFL_RSV_V2_8822B)
+#define BITS_RXFFOVFL_RSV_V2_8822B \
+ (BIT_MASK_RXFFOVFL_RSV_V2_8822B << BIT_SHIFT_RXFFOVFL_RSV_V2_8822B)
+#define BIT_CLEAR_RXFFOVFL_RSV_V2_8822B(x) ((x) & (~BITS_RXFFOVFL_RSV_V2_8822B))
+#define BIT_GET_RXFFOVFL_RSV_V2_8822B(x) \
+ (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8822B) & \
+ BIT_MASK_RXFFOVFL_RSV_V2_8822B)
+#define BIT_SET_RXFFOVFL_RSV_V2_8822B(x, v) \
+ (BIT_CLEAR_RXFFOVFL_RSV_V2_8822B(x) | BIT_RXFFOVFL_RSV_V2_8822B(v))
#define BIT_SHIFT_TXPKTBUF_PGBNDY_8822B 0
#define BIT_MASK_TXPKTBUF_PGBNDY_8822B 0xff
-#define BIT_TXPKTBUF_PGBNDY_8822B(x) (((x) & BIT_MASK_TXPKTBUF_PGBNDY_8822B) << BIT_SHIFT_TXPKTBUF_PGBNDY_8822B)
-#define BIT_GET_TXPKTBUF_PGBNDY_8822B(x) (((x) >> BIT_SHIFT_TXPKTBUF_PGBNDY_8822B) & BIT_MASK_TXPKTBUF_PGBNDY_8822B)
-
+#define BIT_TXPKTBUF_PGBNDY_8822B(x) \
+ (((x) & BIT_MASK_TXPKTBUF_PGBNDY_8822B) \
+ << BIT_SHIFT_TXPKTBUF_PGBNDY_8822B)
+#define BITS_TXPKTBUF_PGBNDY_8822B \
+ (BIT_MASK_TXPKTBUF_PGBNDY_8822B << BIT_SHIFT_TXPKTBUF_PGBNDY_8822B)
+#define BIT_CLEAR_TXPKTBUF_PGBNDY_8822B(x) ((x) & (~BITS_TXPKTBUF_PGBNDY_8822B))
+#define BIT_GET_TXPKTBUF_PGBNDY_8822B(x) \
+ (((x) >> BIT_SHIFT_TXPKTBUF_PGBNDY_8822B) & \
+ BIT_MASK_TXPKTBUF_PGBNDY_8822B)
+#define BIT_SET_TXPKTBUF_PGBNDY_8822B(x, v) \
+ (BIT_CLEAR_TXPKTBUF_PGBNDY_8822B(x) | BIT_TXPKTBUF_PGBNDY_8822B(v))
/* 2 REG_PTA_I2C_MBOX_8822B */
@@ -1988,21 +3131,44 @@
#define BIT_SHIFT_I2C_M_STATUS_8822B 8
#define BIT_MASK_I2C_M_STATUS_8822B 0xf
-#define BIT_I2C_M_STATUS_8822B(x) (((x) & BIT_MASK_I2C_M_STATUS_8822B) << BIT_SHIFT_I2C_M_STATUS_8822B)
-#define BIT_GET_I2C_M_STATUS_8822B(x) (((x) >> BIT_SHIFT_I2C_M_STATUS_8822B) & BIT_MASK_I2C_M_STATUS_8822B)
-
+#define BIT_I2C_M_STATUS_8822B(x) \
+ (((x) & BIT_MASK_I2C_M_STATUS_8822B) << BIT_SHIFT_I2C_M_STATUS_8822B)
+#define BITS_I2C_M_STATUS_8822B \
+ (BIT_MASK_I2C_M_STATUS_8822B << BIT_SHIFT_I2C_M_STATUS_8822B)
+#define BIT_CLEAR_I2C_M_STATUS_8822B(x) ((x) & (~BITS_I2C_M_STATUS_8822B))
+#define BIT_GET_I2C_M_STATUS_8822B(x) \
+ (((x) >> BIT_SHIFT_I2C_M_STATUS_8822B) & BIT_MASK_I2C_M_STATUS_8822B)
+#define BIT_SET_I2C_M_STATUS_8822B(x, v) \
+ (BIT_CLEAR_I2C_M_STATUS_8822B(x) | BIT_I2C_M_STATUS_8822B(v))
#define BIT_SHIFT_I2C_M_BUS_GNT_FW_8822B 4
#define BIT_MASK_I2C_M_BUS_GNT_FW_8822B 0x7
-#define BIT_I2C_M_BUS_GNT_FW_8822B(x) (((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8822B) << BIT_SHIFT_I2C_M_BUS_GNT_FW_8822B)
-#define BIT_GET_I2C_M_BUS_GNT_FW_8822B(x) (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8822B) & BIT_MASK_I2C_M_BUS_GNT_FW_8822B)
+#define BIT_I2C_M_BUS_GNT_FW_8822B(x) \
+ (((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8822B) \
+ << BIT_SHIFT_I2C_M_BUS_GNT_FW_8822B)
+#define BITS_I2C_M_BUS_GNT_FW_8822B \
+ (BIT_MASK_I2C_M_BUS_GNT_FW_8822B << BIT_SHIFT_I2C_M_BUS_GNT_FW_8822B)
+#define BIT_CLEAR_I2C_M_BUS_GNT_FW_8822B(x) \
+ ((x) & (~BITS_I2C_M_BUS_GNT_FW_8822B))
+#define BIT_GET_I2C_M_BUS_GNT_FW_8822B(x) \
+ (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8822B) & \
+ BIT_MASK_I2C_M_BUS_GNT_FW_8822B)
+#define BIT_SET_I2C_M_BUS_GNT_FW_8822B(x, v) \
+ (BIT_CLEAR_I2C_M_BUS_GNT_FW_8822B(x) | BIT_I2C_M_BUS_GNT_FW_8822B(v))
#define BIT_I2C_M_GNT_FW_8822B BIT(3)
#define BIT_SHIFT_I2C_M_SPEED_8822B 1
#define BIT_MASK_I2C_M_SPEED_8822B 0x3
-#define BIT_I2C_M_SPEED_8822B(x) (((x) & BIT_MASK_I2C_M_SPEED_8822B) << BIT_SHIFT_I2C_M_SPEED_8822B)
-#define BIT_GET_I2C_M_SPEED_8822B(x) (((x) >> BIT_SHIFT_I2C_M_SPEED_8822B) & BIT_MASK_I2C_M_SPEED_8822B)
+#define BIT_I2C_M_SPEED_8822B(x) \
+ (((x) & BIT_MASK_I2C_M_SPEED_8822B) << BIT_SHIFT_I2C_M_SPEED_8822B)
+#define BITS_I2C_M_SPEED_8822B \
+ (BIT_MASK_I2C_M_SPEED_8822B << BIT_SHIFT_I2C_M_SPEED_8822B)
+#define BIT_CLEAR_I2C_M_SPEED_8822B(x) ((x) & (~BITS_I2C_M_SPEED_8822B))
+#define BIT_GET_I2C_M_SPEED_8822B(x) \
+ (((x) >> BIT_SHIFT_I2C_M_SPEED_8822B) & BIT_MASK_I2C_M_SPEED_8822B)
+#define BIT_SET_I2C_M_SPEED_8822B(x, v) \
+ (BIT_CLEAR_I2C_M_SPEED_8822B(x) | BIT_I2C_M_SPEED_8822B(v))
#define BIT_I2C_M_UNLOCK_8822B BIT(0)
@@ -2012,9 +3178,15 @@
#define BIT_SHIFT_RXFF0_BNDY_V2_8822B 0
#define BIT_MASK_RXFF0_BNDY_V2_8822B 0x3ffff
-#define BIT_RXFF0_BNDY_V2_8822B(x) (((x) & BIT_MASK_RXFF0_BNDY_V2_8822B) << BIT_SHIFT_RXFF0_BNDY_V2_8822B)
-#define BIT_GET_RXFF0_BNDY_V2_8822B(x) (((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8822B) & BIT_MASK_RXFF0_BNDY_V2_8822B)
-
+#define BIT_RXFF0_BNDY_V2_8822B(x) \
+ (((x) & BIT_MASK_RXFF0_BNDY_V2_8822B) << BIT_SHIFT_RXFF0_BNDY_V2_8822B)
+#define BITS_RXFF0_BNDY_V2_8822B \
+ (BIT_MASK_RXFF0_BNDY_V2_8822B << BIT_SHIFT_RXFF0_BNDY_V2_8822B)
+#define BIT_CLEAR_RXFF0_BNDY_V2_8822B(x) ((x) & (~BITS_RXFF0_BNDY_V2_8822B))
+#define BIT_GET_RXFF0_BNDY_V2_8822B(x) \
+ (((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8822B) & BIT_MASK_RXFF0_BNDY_V2_8822B)
+#define BIT_SET_RXFF0_BNDY_V2_8822B(x, v) \
+ (BIT_CLEAR_RXFF0_BNDY_V2_8822B(x) | BIT_RXFF0_BNDY_V2_8822B(v))
/* 2 REG_FE1IMR_8822B */
#define BIT_FS_RXDMA2_DONE_INT_EN_8822B BIT(28)
@@ -2081,9 +3253,15 @@
#define BIT_SHIFT_CPWM_MOD_8822B 24
#define BIT_MASK_CPWM_MOD_8822B 0x7f
-#define BIT_CPWM_MOD_8822B(x) (((x) & BIT_MASK_CPWM_MOD_8822B) << BIT_SHIFT_CPWM_MOD_8822B)
-#define BIT_GET_CPWM_MOD_8822B(x) (((x) >> BIT_SHIFT_CPWM_MOD_8822B) & BIT_MASK_CPWM_MOD_8822B)
-
+#define BIT_CPWM_MOD_8822B(x) \
+ (((x) & BIT_MASK_CPWM_MOD_8822B) << BIT_SHIFT_CPWM_MOD_8822B)
+#define BITS_CPWM_MOD_8822B \
+ (BIT_MASK_CPWM_MOD_8822B << BIT_SHIFT_CPWM_MOD_8822B)
+#define BIT_CLEAR_CPWM_MOD_8822B(x) ((x) & (~BITS_CPWM_MOD_8822B))
+#define BIT_GET_CPWM_MOD_8822B(x) \
+ (((x) >> BIT_SHIFT_CPWM_MOD_8822B) & BIT_MASK_CPWM_MOD_8822B)
+#define BIT_SET_CPWM_MOD_8822B(x, v) \
+ (BIT_CLEAR_CPWM_MOD_8822B(x) | BIT_CPWM_MOD_8822B(v))
/* 2 REG_FWIMR_8822B */
#define BIT_FS_TXBCNOK_MB7_INT_EN_8822B BIT(31)
@@ -2106,8 +3284,7 @@
#define BIT_SIFS_OVERSPEC_INT_EN_8822B BIT(14)
#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_EN_8822B BIT(13)
#define BIT_FS_MGNTQFF_TO_INT_EN_8822B BIT(12)
-#define BIT_FS_DDMA1_LP_INT_EN_8822B BIT(11)
-#define BIT_FS_DDMA1_HP_INT_EN_8822B BIT(10)
+#define BIT_FS_CPUMGQ_ERR_INT_EN_8822B BIT(11)
#define BIT_FS_DDMA0_LP_INT_EN_8822B BIT(9)
#define BIT_FS_DDMA0_HP_INT_EN_8822B BIT(8)
#define BIT_FS_TRXRPT_INT_EN_8822B BIT(7)
@@ -2140,8 +3317,7 @@
#define BIT_SIFS_OVERSPEC_INT_8822B BIT(14)
#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_8822B BIT(13)
#define BIT_FS_MGNTQFF_TO_INT_8822B BIT(12)
-#define BIT_FS_DDMA1_LP_INT_8822B BIT(11)
-#define BIT_FS_DDMA1_HP_INT_8822B BIT(10)
+#define BIT_FS_CPUMGQ_ERR_INT_8822B BIT(11)
#define BIT_FS_DDMA0_LP_INT_8822B BIT(9)
#define BIT_FS_DDMA0_HP_INT_8822B BIT(8)
#define BIT_FS_TRXRPT_INT_8822B BIT(7)
@@ -2201,8 +3377,17 @@
#define BIT_SHIFT_PKTBUF_WRITE_EN_8822B 24
#define BIT_MASK_PKTBUF_WRITE_EN_8822B 0xff
-#define BIT_PKTBUF_WRITE_EN_8822B(x) (((x) & BIT_MASK_PKTBUF_WRITE_EN_8822B) << BIT_SHIFT_PKTBUF_WRITE_EN_8822B)
-#define BIT_GET_PKTBUF_WRITE_EN_8822B(x) (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8822B) & BIT_MASK_PKTBUF_WRITE_EN_8822B)
+#define BIT_PKTBUF_WRITE_EN_8822B(x) \
+ (((x) & BIT_MASK_PKTBUF_WRITE_EN_8822B) \
+ << BIT_SHIFT_PKTBUF_WRITE_EN_8822B)
+#define BITS_PKTBUF_WRITE_EN_8822B \
+ (BIT_MASK_PKTBUF_WRITE_EN_8822B << BIT_SHIFT_PKTBUF_WRITE_EN_8822B)
+#define BIT_CLEAR_PKTBUF_WRITE_EN_8822B(x) ((x) & (~BITS_PKTBUF_WRITE_EN_8822B))
+#define BIT_GET_PKTBUF_WRITE_EN_8822B(x) \
+ (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8822B) & \
+ BIT_MASK_PKTBUF_WRITE_EN_8822B)
+#define BIT_SET_PKTBUF_WRITE_EN_8822B(x, v) \
+ (BIT_CLEAR_PKTBUF_WRITE_EN_8822B(x) | BIT_PKTBUF_WRITE_EN_8822B(v))
#define BIT_TXRPTBUF_DBG_8822B BIT(23)
@@ -2212,40 +3397,81 @@
#define BIT_SHIFT_PKTBUF_DBG_ADDR_8822B 0
#define BIT_MASK_PKTBUF_DBG_ADDR_8822B 0x1fff
-#define BIT_PKTBUF_DBG_ADDR_8822B(x) (((x) & BIT_MASK_PKTBUF_DBG_ADDR_8822B) << BIT_SHIFT_PKTBUF_DBG_ADDR_8822B)
-#define BIT_GET_PKTBUF_DBG_ADDR_8822B(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8822B) & BIT_MASK_PKTBUF_DBG_ADDR_8822B)
-
+#define BIT_PKTBUF_DBG_ADDR_8822B(x) \
+ (((x) & BIT_MASK_PKTBUF_DBG_ADDR_8822B) \
+ << BIT_SHIFT_PKTBUF_DBG_ADDR_8822B)
+#define BITS_PKTBUF_DBG_ADDR_8822B \
+ (BIT_MASK_PKTBUF_DBG_ADDR_8822B << BIT_SHIFT_PKTBUF_DBG_ADDR_8822B)
+#define BIT_CLEAR_PKTBUF_DBG_ADDR_8822B(x) ((x) & (~BITS_PKTBUF_DBG_ADDR_8822B))
+#define BIT_GET_PKTBUF_DBG_ADDR_8822B(x) \
+ (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8822B) & \
+ BIT_MASK_PKTBUF_DBG_ADDR_8822B)
+#define BIT_SET_PKTBUF_DBG_ADDR_8822B(x, v) \
+ (BIT_CLEAR_PKTBUF_DBG_ADDR_8822B(x) | BIT_PKTBUF_DBG_ADDR_8822B(v))
/* 2 REG_PKTBUF_DBG_DATA_L_8822B */
#define BIT_SHIFT_PKTBUF_DBG_DATA_L_8822B 0
#define BIT_MASK_PKTBUF_DBG_DATA_L_8822B 0xffffffffL
-#define BIT_PKTBUF_DBG_DATA_L_8822B(x) (((x) & BIT_MASK_PKTBUF_DBG_DATA_L_8822B) << BIT_SHIFT_PKTBUF_DBG_DATA_L_8822B)
-#define BIT_GET_PKTBUF_DBG_DATA_L_8822B(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8822B) & BIT_MASK_PKTBUF_DBG_DATA_L_8822B)
-
+#define BIT_PKTBUF_DBG_DATA_L_8822B(x) \
+ (((x) & BIT_MASK_PKTBUF_DBG_DATA_L_8822B) \
+ << BIT_SHIFT_PKTBUF_DBG_DATA_L_8822B)
+#define BITS_PKTBUF_DBG_DATA_L_8822B \
+ (BIT_MASK_PKTBUF_DBG_DATA_L_8822B << BIT_SHIFT_PKTBUF_DBG_DATA_L_8822B)
+#define BIT_CLEAR_PKTBUF_DBG_DATA_L_8822B(x) \
+ ((x) & (~BITS_PKTBUF_DBG_DATA_L_8822B))
+#define BIT_GET_PKTBUF_DBG_DATA_L_8822B(x) \
+ (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8822B) & \
+ BIT_MASK_PKTBUF_DBG_DATA_L_8822B)
+#define BIT_SET_PKTBUF_DBG_DATA_L_8822B(x, v) \
+ (BIT_CLEAR_PKTBUF_DBG_DATA_L_8822B(x) | BIT_PKTBUF_DBG_DATA_L_8822B(v))
/* 2 REG_PKTBUF_DBG_DATA_H_8822B */
#define BIT_SHIFT_PKTBUF_DBG_DATA_H_8822B 0
#define BIT_MASK_PKTBUF_DBG_DATA_H_8822B 0xffffffffL
-#define BIT_PKTBUF_DBG_DATA_H_8822B(x) (((x) & BIT_MASK_PKTBUF_DBG_DATA_H_8822B) << BIT_SHIFT_PKTBUF_DBG_DATA_H_8822B)
-#define BIT_GET_PKTBUF_DBG_DATA_H_8822B(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8822B) & BIT_MASK_PKTBUF_DBG_DATA_H_8822B)
-
+#define BIT_PKTBUF_DBG_DATA_H_8822B(x) \
+ (((x) & BIT_MASK_PKTBUF_DBG_DATA_H_8822B) \
+ << BIT_SHIFT_PKTBUF_DBG_DATA_H_8822B)
+#define BITS_PKTBUF_DBG_DATA_H_8822B \
+ (BIT_MASK_PKTBUF_DBG_DATA_H_8822B << BIT_SHIFT_PKTBUF_DBG_DATA_H_8822B)
+#define BIT_CLEAR_PKTBUF_DBG_DATA_H_8822B(x) \
+ ((x) & (~BITS_PKTBUF_DBG_DATA_H_8822B))
+#define BIT_GET_PKTBUF_DBG_DATA_H_8822B(x) \
+ (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8822B) & \
+ BIT_MASK_PKTBUF_DBG_DATA_H_8822B)
+#define BIT_SET_PKTBUF_DBG_DATA_H_8822B(x, v) \
+ (BIT_CLEAR_PKTBUF_DBG_DATA_H_8822B(x) | BIT_PKTBUF_DBG_DATA_H_8822B(v))
/* 2 REG_CPWM2_8822B */
#define BIT_SHIFT_L0S_TO_RCVY_NUM_8822B 16
#define BIT_MASK_L0S_TO_RCVY_NUM_8822B 0xff
-#define BIT_L0S_TO_RCVY_NUM_8822B(x) (((x) & BIT_MASK_L0S_TO_RCVY_NUM_8822B) << BIT_SHIFT_L0S_TO_RCVY_NUM_8822B)
-#define BIT_GET_L0S_TO_RCVY_NUM_8822B(x) (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8822B) & BIT_MASK_L0S_TO_RCVY_NUM_8822B)
+#define BIT_L0S_TO_RCVY_NUM_8822B(x) \
+ (((x) & BIT_MASK_L0S_TO_RCVY_NUM_8822B) \
+ << BIT_SHIFT_L0S_TO_RCVY_NUM_8822B)
+#define BITS_L0S_TO_RCVY_NUM_8822B \
+ (BIT_MASK_L0S_TO_RCVY_NUM_8822B << BIT_SHIFT_L0S_TO_RCVY_NUM_8822B)
+#define BIT_CLEAR_L0S_TO_RCVY_NUM_8822B(x) ((x) & (~BITS_L0S_TO_RCVY_NUM_8822B))
+#define BIT_GET_L0S_TO_RCVY_NUM_8822B(x) \
+ (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8822B) & \
+ BIT_MASK_L0S_TO_RCVY_NUM_8822B)
+#define BIT_SET_L0S_TO_RCVY_NUM_8822B(x, v) \
+ (BIT_CLEAR_L0S_TO_RCVY_NUM_8822B(x) | BIT_L0S_TO_RCVY_NUM_8822B(v))
#define BIT_CPWM2_TOGGLING_8822B BIT(15)
#define BIT_SHIFT_CPWM2_MOD_8822B 0
#define BIT_MASK_CPWM2_MOD_8822B 0x7fff
-#define BIT_CPWM2_MOD_8822B(x) (((x) & BIT_MASK_CPWM2_MOD_8822B) << BIT_SHIFT_CPWM2_MOD_8822B)
-#define BIT_GET_CPWM2_MOD_8822B(x) (((x) >> BIT_SHIFT_CPWM2_MOD_8822B) & BIT_MASK_CPWM2_MOD_8822B)
-
+#define BIT_CPWM2_MOD_8822B(x) \
+ (((x) & BIT_MASK_CPWM2_MOD_8822B) << BIT_SHIFT_CPWM2_MOD_8822B)
+#define BITS_CPWM2_MOD_8822B \
+ (BIT_MASK_CPWM2_MOD_8822B << BIT_SHIFT_CPWM2_MOD_8822B)
+#define BIT_CLEAR_CPWM2_MOD_8822B(x) ((x) & (~BITS_CPWM2_MOD_8822B))
+#define BIT_GET_CPWM2_MOD_8822B(x) \
+ (((x) >> BIT_SHIFT_CPWM2_MOD_8822B) & BIT_MASK_CPWM2_MOD_8822B)
+#define BIT_SET_CPWM2_MOD_8822B(x, v) \
+ (BIT_CLEAR_CPWM2_MOD_8822B(x) | BIT_CPWM2_MOD_8822B(v))
/* 2 REG_NOT_VALID_8822B */
@@ -2256,9 +3482,14 @@
#define BIT_SHIFT_TC0DATA_8822B 0
#define BIT_MASK_TC0DATA_8822B 0xffffff
-#define BIT_TC0DATA_8822B(x) (((x) & BIT_MASK_TC0DATA_8822B) << BIT_SHIFT_TC0DATA_8822B)
-#define BIT_GET_TC0DATA_8822B(x) (((x) >> BIT_SHIFT_TC0DATA_8822B) & BIT_MASK_TC0DATA_8822B)
-
+#define BIT_TC0DATA_8822B(x) \
+ (((x) & BIT_MASK_TC0DATA_8822B) << BIT_SHIFT_TC0DATA_8822B)
+#define BITS_TC0DATA_8822B (BIT_MASK_TC0DATA_8822B << BIT_SHIFT_TC0DATA_8822B)
+#define BIT_CLEAR_TC0DATA_8822B(x) ((x) & (~BITS_TC0DATA_8822B))
+#define BIT_GET_TC0DATA_8822B(x) \
+ (((x) >> BIT_SHIFT_TC0DATA_8822B) & BIT_MASK_TC0DATA_8822B)
+#define BIT_SET_TC0DATA_8822B(x, v) \
+ (BIT_CLEAR_TC0DATA_8822B(x) | BIT_TC0DATA_8822B(v))
/* 2 REG_TC1_CTRL_8822B */
#define BIT_TC1INT_EN_8822B BIT(26)
@@ -2267,9 +3498,14 @@
#define BIT_SHIFT_TC1DATA_8822B 0
#define BIT_MASK_TC1DATA_8822B 0xffffff
-#define BIT_TC1DATA_8822B(x) (((x) & BIT_MASK_TC1DATA_8822B) << BIT_SHIFT_TC1DATA_8822B)
-#define BIT_GET_TC1DATA_8822B(x) (((x) >> BIT_SHIFT_TC1DATA_8822B) & BIT_MASK_TC1DATA_8822B)
-
+#define BIT_TC1DATA_8822B(x) \
+ (((x) & BIT_MASK_TC1DATA_8822B) << BIT_SHIFT_TC1DATA_8822B)
+#define BITS_TC1DATA_8822B (BIT_MASK_TC1DATA_8822B << BIT_SHIFT_TC1DATA_8822B)
+#define BIT_CLEAR_TC1DATA_8822B(x) ((x) & (~BITS_TC1DATA_8822B))
+#define BIT_GET_TC1DATA_8822B(x) \
+ (((x) >> BIT_SHIFT_TC1DATA_8822B) & BIT_MASK_TC1DATA_8822B)
+#define BIT_SET_TC1DATA_8822B(x, v) \
+ (BIT_CLEAR_TC1DATA_8822B(x) | BIT_TC1DATA_8822B(v))
/* 2 REG_TC2_CTRL_8822B */
#define BIT_TC2INT_EN_8822B BIT(26)
@@ -2278,9 +3514,14 @@
#define BIT_SHIFT_TC2DATA_8822B 0
#define BIT_MASK_TC2DATA_8822B 0xffffff
-#define BIT_TC2DATA_8822B(x) (((x) & BIT_MASK_TC2DATA_8822B) << BIT_SHIFT_TC2DATA_8822B)
-#define BIT_GET_TC2DATA_8822B(x) (((x) >> BIT_SHIFT_TC2DATA_8822B) & BIT_MASK_TC2DATA_8822B)
-
+#define BIT_TC2DATA_8822B(x) \
+ (((x) & BIT_MASK_TC2DATA_8822B) << BIT_SHIFT_TC2DATA_8822B)
+#define BITS_TC2DATA_8822B (BIT_MASK_TC2DATA_8822B << BIT_SHIFT_TC2DATA_8822B)
+#define BIT_CLEAR_TC2DATA_8822B(x) ((x) & (~BITS_TC2DATA_8822B))
+#define BIT_GET_TC2DATA_8822B(x) \
+ (((x) >> BIT_SHIFT_TC2DATA_8822B) & BIT_MASK_TC2DATA_8822B)
+#define BIT_SET_TC2DATA_8822B(x, v) \
+ (BIT_CLEAR_TC2DATA_8822B(x) | BIT_TC2DATA_8822B(v))
/* 2 REG_TC3_CTRL_8822B */
#define BIT_TC3INT_EN_8822B BIT(26)
@@ -2289,9 +3530,14 @@
#define BIT_SHIFT_TC3DATA_8822B 0
#define BIT_MASK_TC3DATA_8822B 0xffffff
-#define BIT_TC3DATA_8822B(x) (((x) & BIT_MASK_TC3DATA_8822B) << BIT_SHIFT_TC3DATA_8822B)
-#define BIT_GET_TC3DATA_8822B(x) (((x) >> BIT_SHIFT_TC3DATA_8822B) & BIT_MASK_TC3DATA_8822B)
-
+#define BIT_TC3DATA_8822B(x) \
+ (((x) & BIT_MASK_TC3DATA_8822B) << BIT_SHIFT_TC3DATA_8822B)
+#define BITS_TC3DATA_8822B (BIT_MASK_TC3DATA_8822B << BIT_SHIFT_TC3DATA_8822B)
+#define BIT_CLEAR_TC3DATA_8822B(x) ((x) & (~BITS_TC3DATA_8822B))
+#define BIT_GET_TC3DATA_8822B(x) \
+ (((x) >> BIT_SHIFT_TC3DATA_8822B) & BIT_MASK_TC3DATA_8822B)
+#define BIT_SET_TC3DATA_8822B(x, v) \
+ (BIT_CLEAR_TC3DATA_8822B(x) | BIT_TC3DATA_8822B(v))
/* 2 REG_TC4_CTRL_8822B */
#define BIT_TC4INT_EN_8822B BIT(26)
@@ -2300,17 +3546,28 @@
#define BIT_SHIFT_TC4DATA_8822B 0
#define BIT_MASK_TC4DATA_8822B 0xffffff
-#define BIT_TC4DATA_8822B(x) (((x) & BIT_MASK_TC4DATA_8822B) << BIT_SHIFT_TC4DATA_8822B)
-#define BIT_GET_TC4DATA_8822B(x) (((x) >> BIT_SHIFT_TC4DATA_8822B) & BIT_MASK_TC4DATA_8822B)
-
+#define BIT_TC4DATA_8822B(x) \
+ (((x) & BIT_MASK_TC4DATA_8822B) << BIT_SHIFT_TC4DATA_8822B)
+#define BITS_TC4DATA_8822B (BIT_MASK_TC4DATA_8822B << BIT_SHIFT_TC4DATA_8822B)
+#define BIT_CLEAR_TC4DATA_8822B(x) ((x) & (~BITS_TC4DATA_8822B))
+#define BIT_GET_TC4DATA_8822B(x) \
+ (((x) >> BIT_SHIFT_TC4DATA_8822B) & BIT_MASK_TC4DATA_8822B)
+#define BIT_SET_TC4DATA_8822B(x, v) \
+ (BIT_CLEAR_TC4DATA_8822B(x) | BIT_TC4DATA_8822B(v))
/* 2 REG_TCUNIT_BASE_8822B */
#define BIT_SHIFT_TCUNIT_BASE_8822B 0
#define BIT_MASK_TCUNIT_BASE_8822B 0x3fff
-#define BIT_TCUNIT_BASE_8822B(x) (((x) & BIT_MASK_TCUNIT_BASE_8822B) << BIT_SHIFT_TCUNIT_BASE_8822B)
-#define BIT_GET_TCUNIT_BASE_8822B(x) (((x) >> BIT_SHIFT_TCUNIT_BASE_8822B) & BIT_MASK_TCUNIT_BASE_8822B)
-
+#define BIT_TCUNIT_BASE_8822B(x) \
+ (((x) & BIT_MASK_TCUNIT_BASE_8822B) << BIT_SHIFT_TCUNIT_BASE_8822B)
+#define BITS_TCUNIT_BASE_8822B \
+ (BIT_MASK_TCUNIT_BASE_8822B << BIT_SHIFT_TCUNIT_BASE_8822B)
+#define BIT_CLEAR_TCUNIT_BASE_8822B(x) ((x) & (~BITS_TCUNIT_BASE_8822B))
+#define BIT_GET_TCUNIT_BASE_8822B(x) \
+ (((x) >> BIT_SHIFT_TCUNIT_BASE_8822B) & BIT_MASK_TCUNIT_BASE_8822B)
+#define BIT_SET_TCUNIT_BASE_8822B(x, v) \
+ (BIT_CLEAR_TCUNIT_BASE_8822B(x) | BIT_TCUNIT_BASE_8822B(v))
/* 2 REG_TC5_CTRL_8822B */
#define BIT_TC5INT_EN_8822B BIT(26)
@@ -2319,9 +3576,14 @@
#define BIT_SHIFT_TC5DATA_8822B 0
#define BIT_MASK_TC5DATA_8822B 0xffffff
-#define BIT_TC5DATA_8822B(x) (((x) & BIT_MASK_TC5DATA_8822B) << BIT_SHIFT_TC5DATA_8822B)
-#define BIT_GET_TC5DATA_8822B(x) (((x) >> BIT_SHIFT_TC5DATA_8822B) & BIT_MASK_TC5DATA_8822B)
-
+#define BIT_TC5DATA_8822B(x) \
+ (((x) & BIT_MASK_TC5DATA_8822B) << BIT_SHIFT_TC5DATA_8822B)
+#define BITS_TC5DATA_8822B (BIT_MASK_TC5DATA_8822B << BIT_SHIFT_TC5DATA_8822B)
+#define BIT_CLEAR_TC5DATA_8822B(x) ((x) & (~BITS_TC5DATA_8822B))
+#define BIT_GET_TC5DATA_8822B(x) \
+ (((x) >> BIT_SHIFT_TC5DATA_8822B) & BIT_MASK_TC5DATA_8822B)
+#define BIT_SET_TC5DATA_8822B(x, v) \
+ (BIT_CLEAR_TC5DATA_8822B(x) | BIT_TC5DATA_8822B(v))
/* 2 REG_TC6_CTRL_8822B */
#define BIT_TC6INT_EN_8822B BIT(26)
@@ -2330,111 +3592,244 @@
#define BIT_SHIFT_TC6DATA_8822B 0
#define BIT_MASK_TC6DATA_8822B 0xffffff
-#define BIT_TC6DATA_8822B(x) (((x) & BIT_MASK_TC6DATA_8822B) << BIT_SHIFT_TC6DATA_8822B)
-#define BIT_GET_TC6DATA_8822B(x) (((x) >> BIT_SHIFT_TC6DATA_8822B) & BIT_MASK_TC6DATA_8822B)
-
+#define BIT_TC6DATA_8822B(x) \
+ (((x) & BIT_MASK_TC6DATA_8822B) << BIT_SHIFT_TC6DATA_8822B)
+#define BITS_TC6DATA_8822B (BIT_MASK_TC6DATA_8822B << BIT_SHIFT_TC6DATA_8822B)
+#define BIT_CLEAR_TC6DATA_8822B(x) ((x) & (~BITS_TC6DATA_8822B))
+#define BIT_GET_TC6DATA_8822B(x) \
+ (((x) >> BIT_SHIFT_TC6DATA_8822B) & BIT_MASK_TC6DATA_8822B)
+#define BIT_SET_TC6DATA_8822B(x, v) \
+ (BIT_CLEAR_TC6DATA_8822B(x) | BIT_TC6DATA_8822B(v))
/* 2 REG_MBIST_FAIL_8822B */
#define BIT_SHIFT_8051_MBIST_FAIL_8822B 26
#define BIT_MASK_8051_MBIST_FAIL_8822B 0x7
-#define BIT_8051_MBIST_FAIL_8822B(x) (((x) & BIT_MASK_8051_MBIST_FAIL_8822B) << BIT_SHIFT_8051_MBIST_FAIL_8822B)
-#define BIT_GET_8051_MBIST_FAIL_8822B(x) (((x) >> BIT_SHIFT_8051_MBIST_FAIL_8822B) & BIT_MASK_8051_MBIST_FAIL_8822B)
-
+#define BIT_8051_MBIST_FAIL_8822B(x) \
+ (((x) & BIT_MASK_8051_MBIST_FAIL_8822B) \
+ << BIT_SHIFT_8051_MBIST_FAIL_8822B)
+#define BITS_8051_MBIST_FAIL_8822B \
+ (BIT_MASK_8051_MBIST_FAIL_8822B << BIT_SHIFT_8051_MBIST_FAIL_8822B)
+#define BIT_CLEAR_8051_MBIST_FAIL_8822B(x) ((x) & (~BITS_8051_MBIST_FAIL_8822B))
+#define BIT_GET_8051_MBIST_FAIL_8822B(x) \
+ (((x) >> BIT_SHIFT_8051_MBIST_FAIL_8822B) & \
+ BIT_MASK_8051_MBIST_FAIL_8822B)
+#define BIT_SET_8051_MBIST_FAIL_8822B(x, v) \
+ (BIT_CLEAR_8051_MBIST_FAIL_8822B(x) | BIT_8051_MBIST_FAIL_8822B(v))
#define BIT_SHIFT_USB_MBIST_FAIL_8822B 24
#define BIT_MASK_USB_MBIST_FAIL_8822B 0x3
-#define BIT_USB_MBIST_FAIL_8822B(x) (((x) & BIT_MASK_USB_MBIST_FAIL_8822B) << BIT_SHIFT_USB_MBIST_FAIL_8822B)
-#define BIT_GET_USB_MBIST_FAIL_8822B(x) (((x) >> BIT_SHIFT_USB_MBIST_FAIL_8822B) & BIT_MASK_USB_MBIST_FAIL_8822B)
-
+#define BIT_USB_MBIST_FAIL_8822B(x) \
+ (((x) & BIT_MASK_USB_MBIST_FAIL_8822B) \
+ << BIT_SHIFT_USB_MBIST_FAIL_8822B)
+#define BITS_USB_MBIST_FAIL_8822B \
+ (BIT_MASK_USB_MBIST_FAIL_8822B << BIT_SHIFT_USB_MBIST_FAIL_8822B)
+#define BIT_CLEAR_USB_MBIST_FAIL_8822B(x) ((x) & (~BITS_USB_MBIST_FAIL_8822B))
+#define BIT_GET_USB_MBIST_FAIL_8822B(x) \
+ (((x) >> BIT_SHIFT_USB_MBIST_FAIL_8822B) & \
+ BIT_MASK_USB_MBIST_FAIL_8822B)
+#define BIT_SET_USB_MBIST_FAIL_8822B(x, v) \
+ (BIT_CLEAR_USB_MBIST_FAIL_8822B(x) | BIT_USB_MBIST_FAIL_8822B(v))
#define BIT_SHIFT_PCIE_MBIST_FAIL_8822B 16
#define BIT_MASK_PCIE_MBIST_FAIL_8822B 0x3f
-#define BIT_PCIE_MBIST_FAIL_8822B(x) (((x) & BIT_MASK_PCIE_MBIST_FAIL_8822B) << BIT_SHIFT_PCIE_MBIST_FAIL_8822B)
-#define BIT_GET_PCIE_MBIST_FAIL_8822B(x) (((x) >> BIT_SHIFT_PCIE_MBIST_FAIL_8822B) & BIT_MASK_PCIE_MBIST_FAIL_8822B)
-
+#define BIT_PCIE_MBIST_FAIL_8822B(x) \
+ (((x) & BIT_MASK_PCIE_MBIST_FAIL_8822B) \
+ << BIT_SHIFT_PCIE_MBIST_FAIL_8822B)
+#define BITS_PCIE_MBIST_FAIL_8822B \
+ (BIT_MASK_PCIE_MBIST_FAIL_8822B << BIT_SHIFT_PCIE_MBIST_FAIL_8822B)
+#define BIT_CLEAR_PCIE_MBIST_FAIL_8822B(x) ((x) & (~BITS_PCIE_MBIST_FAIL_8822B))
+#define BIT_GET_PCIE_MBIST_FAIL_8822B(x) \
+ (((x) >> BIT_SHIFT_PCIE_MBIST_FAIL_8822B) & \
+ BIT_MASK_PCIE_MBIST_FAIL_8822B)
+#define BIT_SET_PCIE_MBIST_FAIL_8822B(x, v) \
+ (BIT_CLEAR_PCIE_MBIST_FAIL_8822B(x) | BIT_PCIE_MBIST_FAIL_8822B(v))
#define BIT_SHIFT_MAC_MBIST_FAIL_8822B 0
#define BIT_MASK_MAC_MBIST_FAIL_8822B 0xfff
-#define BIT_MAC_MBIST_FAIL_8822B(x) (((x) & BIT_MASK_MAC_MBIST_FAIL_8822B) << BIT_SHIFT_MAC_MBIST_FAIL_8822B)
-#define BIT_GET_MAC_MBIST_FAIL_8822B(x) (((x) >> BIT_SHIFT_MAC_MBIST_FAIL_8822B) & BIT_MASK_MAC_MBIST_FAIL_8822B)
-
+#define BIT_MAC_MBIST_FAIL_8822B(x) \
+ (((x) & BIT_MASK_MAC_MBIST_FAIL_8822B) \
+ << BIT_SHIFT_MAC_MBIST_FAIL_8822B)
+#define BITS_MAC_MBIST_FAIL_8822B \
+ (BIT_MASK_MAC_MBIST_FAIL_8822B << BIT_SHIFT_MAC_MBIST_FAIL_8822B)
+#define BIT_CLEAR_MAC_MBIST_FAIL_8822B(x) ((x) & (~BITS_MAC_MBIST_FAIL_8822B))
+#define BIT_GET_MAC_MBIST_FAIL_8822B(x) \
+ (((x) >> BIT_SHIFT_MAC_MBIST_FAIL_8822B) & \
+ BIT_MASK_MAC_MBIST_FAIL_8822B)
+#define BIT_SET_MAC_MBIST_FAIL_8822B(x, v) \
+ (BIT_CLEAR_MAC_MBIST_FAIL_8822B(x) | BIT_MAC_MBIST_FAIL_8822B(v))
/* 2 REG_MBIST_START_PAUSE_8822B */
#define BIT_SHIFT_8051_MBIST_START_PAUSE_8822B 26
#define BIT_MASK_8051_MBIST_START_PAUSE_8822B 0x7
-#define BIT_8051_MBIST_START_PAUSE_8822B(x) (((x) & BIT_MASK_8051_MBIST_START_PAUSE_8822B) << BIT_SHIFT_8051_MBIST_START_PAUSE_8822B)
-#define BIT_GET_8051_MBIST_START_PAUSE_8822B(x) (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_8822B) & BIT_MASK_8051_MBIST_START_PAUSE_8822B)
-
+#define BIT_8051_MBIST_START_PAUSE_8822B(x) \
+ (((x) & BIT_MASK_8051_MBIST_START_PAUSE_8822B) \
+ << BIT_SHIFT_8051_MBIST_START_PAUSE_8822B)
+#define BITS_8051_MBIST_START_PAUSE_8822B \
+ (BIT_MASK_8051_MBIST_START_PAUSE_8822B \
+ << BIT_SHIFT_8051_MBIST_START_PAUSE_8822B)
+#define BIT_CLEAR_8051_MBIST_START_PAUSE_8822B(x) \
+ ((x) & (~BITS_8051_MBIST_START_PAUSE_8822B))
+#define BIT_GET_8051_MBIST_START_PAUSE_8822B(x) \
+ (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_8822B) & \
+ BIT_MASK_8051_MBIST_START_PAUSE_8822B)
+#define BIT_SET_8051_MBIST_START_PAUSE_8822B(x, v) \
+ (BIT_CLEAR_8051_MBIST_START_PAUSE_8822B(x) | \
+ BIT_8051_MBIST_START_PAUSE_8822B(v))
#define BIT_SHIFT_USB_MBIST_START_PAUSE_8822B 24
#define BIT_MASK_USB_MBIST_START_PAUSE_8822B 0x3
-#define BIT_USB_MBIST_START_PAUSE_8822B(x) (((x) & BIT_MASK_USB_MBIST_START_PAUSE_8822B) << BIT_SHIFT_USB_MBIST_START_PAUSE_8822B)
-#define BIT_GET_USB_MBIST_START_PAUSE_8822B(x) (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_8822B) & BIT_MASK_USB_MBIST_START_PAUSE_8822B)
-
+#define BIT_USB_MBIST_START_PAUSE_8822B(x) \
+ (((x) & BIT_MASK_USB_MBIST_START_PAUSE_8822B) \
+ << BIT_SHIFT_USB_MBIST_START_PAUSE_8822B)
+#define BITS_USB_MBIST_START_PAUSE_8822B \
+ (BIT_MASK_USB_MBIST_START_PAUSE_8822B \
+ << BIT_SHIFT_USB_MBIST_START_PAUSE_8822B)
+#define BIT_CLEAR_USB_MBIST_START_PAUSE_8822B(x) \
+ ((x) & (~BITS_USB_MBIST_START_PAUSE_8822B))
+#define BIT_GET_USB_MBIST_START_PAUSE_8822B(x) \
+ (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_8822B) & \
+ BIT_MASK_USB_MBIST_START_PAUSE_8822B)
+#define BIT_SET_USB_MBIST_START_PAUSE_8822B(x, v) \
+ (BIT_CLEAR_USB_MBIST_START_PAUSE_8822B(x) | \
+ BIT_USB_MBIST_START_PAUSE_8822B(v))
#define BIT_SHIFT_PCIE_MBIST_START_PAUSE_8822B 16
#define BIT_MASK_PCIE_MBIST_START_PAUSE_8822B 0x3f
-#define BIT_PCIE_MBIST_START_PAUSE_8822B(x) (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_8822B) << BIT_SHIFT_PCIE_MBIST_START_PAUSE_8822B)
-#define BIT_GET_PCIE_MBIST_START_PAUSE_8822B(x) (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_8822B) & BIT_MASK_PCIE_MBIST_START_PAUSE_8822B)
-
+#define BIT_PCIE_MBIST_START_PAUSE_8822B(x) \
+ (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_8822B) \
+ << BIT_SHIFT_PCIE_MBIST_START_PAUSE_8822B)
+#define BITS_PCIE_MBIST_START_PAUSE_8822B \
+ (BIT_MASK_PCIE_MBIST_START_PAUSE_8822B \
+ << BIT_SHIFT_PCIE_MBIST_START_PAUSE_8822B)
+#define BIT_CLEAR_PCIE_MBIST_START_PAUSE_8822B(x) \
+ ((x) & (~BITS_PCIE_MBIST_START_PAUSE_8822B))
+#define BIT_GET_PCIE_MBIST_START_PAUSE_8822B(x) \
+ (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_8822B) & \
+ BIT_MASK_PCIE_MBIST_START_PAUSE_8822B)
+#define BIT_SET_PCIE_MBIST_START_PAUSE_8822B(x, v) \
+ (BIT_CLEAR_PCIE_MBIST_START_PAUSE_8822B(x) | \
+ BIT_PCIE_MBIST_START_PAUSE_8822B(v))
#define BIT_SHIFT_MAC_MBIST_START_PAUSE_8822B 0
#define BIT_MASK_MAC_MBIST_START_PAUSE_8822B 0xfff
-#define BIT_MAC_MBIST_START_PAUSE_8822B(x) (((x) & BIT_MASK_MAC_MBIST_START_PAUSE_8822B) << BIT_SHIFT_MAC_MBIST_START_PAUSE_8822B)
-#define BIT_GET_MAC_MBIST_START_PAUSE_8822B(x) (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_8822B) & BIT_MASK_MAC_MBIST_START_PAUSE_8822B)
-
+#define BIT_MAC_MBIST_START_PAUSE_8822B(x) \
+ (((x) & BIT_MASK_MAC_MBIST_START_PAUSE_8822B) \
+ << BIT_SHIFT_MAC_MBIST_START_PAUSE_8822B)
+#define BITS_MAC_MBIST_START_PAUSE_8822B \
+ (BIT_MASK_MAC_MBIST_START_PAUSE_8822B \
+ << BIT_SHIFT_MAC_MBIST_START_PAUSE_8822B)
+#define BIT_CLEAR_MAC_MBIST_START_PAUSE_8822B(x) \
+ ((x) & (~BITS_MAC_MBIST_START_PAUSE_8822B))
+#define BIT_GET_MAC_MBIST_START_PAUSE_8822B(x) \
+ (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_8822B) & \
+ BIT_MASK_MAC_MBIST_START_PAUSE_8822B)
+#define BIT_SET_MAC_MBIST_START_PAUSE_8822B(x, v) \
+ (BIT_CLEAR_MAC_MBIST_START_PAUSE_8822B(x) | \
+ BIT_MAC_MBIST_START_PAUSE_8822B(v))
/* 2 REG_MBIST_DONE_8822B */
#define BIT_SHIFT_8051_MBIST_DONE_8822B 26
#define BIT_MASK_8051_MBIST_DONE_8822B 0x7
-#define BIT_8051_MBIST_DONE_8822B(x) (((x) & BIT_MASK_8051_MBIST_DONE_8822B) << BIT_SHIFT_8051_MBIST_DONE_8822B)
-#define BIT_GET_8051_MBIST_DONE_8822B(x) (((x) >> BIT_SHIFT_8051_MBIST_DONE_8822B) & BIT_MASK_8051_MBIST_DONE_8822B)
-
+#define BIT_8051_MBIST_DONE_8822B(x) \
+ (((x) & BIT_MASK_8051_MBIST_DONE_8822B) \
+ << BIT_SHIFT_8051_MBIST_DONE_8822B)
+#define BITS_8051_MBIST_DONE_8822B \
+ (BIT_MASK_8051_MBIST_DONE_8822B << BIT_SHIFT_8051_MBIST_DONE_8822B)
+#define BIT_CLEAR_8051_MBIST_DONE_8822B(x) ((x) & (~BITS_8051_MBIST_DONE_8822B))
+#define BIT_GET_8051_MBIST_DONE_8822B(x) \
+ (((x) >> BIT_SHIFT_8051_MBIST_DONE_8822B) & \
+ BIT_MASK_8051_MBIST_DONE_8822B)
+#define BIT_SET_8051_MBIST_DONE_8822B(x, v) \
+ (BIT_CLEAR_8051_MBIST_DONE_8822B(x) | BIT_8051_MBIST_DONE_8822B(v))
#define BIT_SHIFT_USB_MBIST_DONE_8822B 24
#define BIT_MASK_USB_MBIST_DONE_8822B 0x3
-#define BIT_USB_MBIST_DONE_8822B(x) (((x) & BIT_MASK_USB_MBIST_DONE_8822B) << BIT_SHIFT_USB_MBIST_DONE_8822B)
-#define BIT_GET_USB_MBIST_DONE_8822B(x) (((x) >> BIT_SHIFT_USB_MBIST_DONE_8822B) & BIT_MASK_USB_MBIST_DONE_8822B)
-
+#define BIT_USB_MBIST_DONE_8822B(x) \
+ (((x) & BIT_MASK_USB_MBIST_DONE_8822B) \
+ << BIT_SHIFT_USB_MBIST_DONE_8822B)
+#define BITS_USB_MBIST_DONE_8822B \
+ (BIT_MASK_USB_MBIST_DONE_8822B << BIT_SHIFT_USB_MBIST_DONE_8822B)
+#define BIT_CLEAR_USB_MBIST_DONE_8822B(x) ((x) & (~BITS_USB_MBIST_DONE_8822B))
+#define BIT_GET_USB_MBIST_DONE_8822B(x) \
+ (((x) >> BIT_SHIFT_USB_MBIST_DONE_8822B) & \
+ BIT_MASK_USB_MBIST_DONE_8822B)
+#define BIT_SET_USB_MBIST_DONE_8822B(x, v) \
+ (BIT_CLEAR_USB_MBIST_DONE_8822B(x) | BIT_USB_MBIST_DONE_8822B(v))
#define BIT_SHIFT_PCIE_MBIST_DONE_8822B 16
#define BIT_MASK_PCIE_MBIST_DONE_8822B 0x3f
-#define BIT_PCIE_MBIST_DONE_8822B(x) (((x) & BIT_MASK_PCIE_MBIST_DONE_8822B) << BIT_SHIFT_PCIE_MBIST_DONE_8822B)
-#define BIT_GET_PCIE_MBIST_DONE_8822B(x) (((x) >> BIT_SHIFT_PCIE_MBIST_DONE_8822B) & BIT_MASK_PCIE_MBIST_DONE_8822B)
-
+#define BIT_PCIE_MBIST_DONE_8822B(x) \
+ (((x) & BIT_MASK_PCIE_MBIST_DONE_8822B) \
+ << BIT_SHIFT_PCIE_MBIST_DONE_8822B)
+#define BITS_PCIE_MBIST_DONE_8822B \
+ (BIT_MASK_PCIE_MBIST_DONE_8822B << BIT_SHIFT_PCIE_MBIST_DONE_8822B)
+#define BIT_CLEAR_PCIE_MBIST_DONE_8822B(x) ((x) & (~BITS_PCIE_MBIST_DONE_8822B))
+#define BIT_GET_PCIE_MBIST_DONE_8822B(x) \
+ (((x) >> BIT_SHIFT_PCIE_MBIST_DONE_8822B) & \
+ BIT_MASK_PCIE_MBIST_DONE_8822B)
+#define BIT_SET_PCIE_MBIST_DONE_8822B(x, v) \
+ (BIT_CLEAR_PCIE_MBIST_DONE_8822B(x) | BIT_PCIE_MBIST_DONE_8822B(v))
#define BIT_SHIFT_MAC_MBIST_DONE_8822B 0
#define BIT_MASK_MAC_MBIST_DONE_8822B 0xfff
-#define BIT_MAC_MBIST_DONE_8822B(x) (((x) & BIT_MASK_MAC_MBIST_DONE_8822B) << BIT_SHIFT_MAC_MBIST_DONE_8822B)
-#define BIT_GET_MAC_MBIST_DONE_8822B(x) (((x) >> BIT_SHIFT_MAC_MBIST_DONE_8822B) & BIT_MASK_MAC_MBIST_DONE_8822B)
-
+#define BIT_MAC_MBIST_DONE_8822B(x) \
+ (((x) & BIT_MASK_MAC_MBIST_DONE_8822B) \
+ << BIT_SHIFT_MAC_MBIST_DONE_8822B)
+#define BITS_MAC_MBIST_DONE_8822B \
+ (BIT_MASK_MAC_MBIST_DONE_8822B << BIT_SHIFT_MAC_MBIST_DONE_8822B)
+#define BIT_CLEAR_MAC_MBIST_DONE_8822B(x) ((x) & (~BITS_MAC_MBIST_DONE_8822B))
+#define BIT_GET_MAC_MBIST_DONE_8822B(x) \
+ (((x) >> BIT_SHIFT_MAC_MBIST_DONE_8822B) & \
+ BIT_MASK_MAC_MBIST_DONE_8822B)
+#define BIT_SET_MAC_MBIST_DONE_8822B(x, v) \
+ (BIT_CLEAR_MAC_MBIST_DONE_8822B(x) | BIT_MAC_MBIST_DONE_8822B(v))
/* 2 REG_MBIST_FAIL_NRML_8822B */
#define BIT_SHIFT_MBIST_FAIL_NRML_8822B 0
#define BIT_MASK_MBIST_FAIL_NRML_8822B 0xffffffffL
-#define BIT_MBIST_FAIL_NRML_8822B(x) (((x) & BIT_MASK_MBIST_FAIL_NRML_8822B) << BIT_SHIFT_MBIST_FAIL_NRML_8822B)
-#define BIT_GET_MBIST_FAIL_NRML_8822B(x) (((x) >> BIT_SHIFT_MBIST_FAIL_NRML_8822B) & BIT_MASK_MBIST_FAIL_NRML_8822B)
-
+#define BIT_MBIST_FAIL_NRML_8822B(x) \
+ (((x) & BIT_MASK_MBIST_FAIL_NRML_8822B) \
+ << BIT_SHIFT_MBIST_FAIL_NRML_8822B)
+#define BITS_MBIST_FAIL_NRML_8822B \
+ (BIT_MASK_MBIST_FAIL_NRML_8822B << BIT_SHIFT_MBIST_FAIL_NRML_8822B)
+#define BIT_CLEAR_MBIST_FAIL_NRML_8822B(x) ((x) & (~BITS_MBIST_FAIL_NRML_8822B))
+#define BIT_GET_MBIST_FAIL_NRML_8822B(x) \
+ (((x) >> BIT_SHIFT_MBIST_FAIL_NRML_8822B) & \
+ BIT_MASK_MBIST_FAIL_NRML_8822B)
+#define BIT_SET_MBIST_FAIL_NRML_8822B(x, v) \
+ (BIT_CLEAR_MBIST_FAIL_NRML_8822B(x) | BIT_MBIST_FAIL_NRML_8822B(v))
/* 2 REG_AES_DECRPT_DATA_8822B */
#define BIT_SHIFT_IPS_CFG_ADDR_8822B 0
#define BIT_MASK_IPS_CFG_ADDR_8822B 0xff
-#define BIT_IPS_CFG_ADDR_8822B(x) (((x) & BIT_MASK_IPS_CFG_ADDR_8822B) << BIT_SHIFT_IPS_CFG_ADDR_8822B)
-#define BIT_GET_IPS_CFG_ADDR_8822B(x) (((x) >> BIT_SHIFT_IPS_CFG_ADDR_8822B) & BIT_MASK_IPS_CFG_ADDR_8822B)
-
+#define BIT_IPS_CFG_ADDR_8822B(x) \
+ (((x) & BIT_MASK_IPS_CFG_ADDR_8822B) << BIT_SHIFT_IPS_CFG_ADDR_8822B)
+#define BITS_IPS_CFG_ADDR_8822B \
+ (BIT_MASK_IPS_CFG_ADDR_8822B << BIT_SHIFT_IPS_CFG_ADDR_8822B)
+#define BIT_CLEAR_IPS_CFG_ADDR_8822B(x) ((x) & (~BITS_IPS_CFG_ADDR_8822B))
+#define BIT_GET_IPS_CFG_ADDR_8822B(x) \
+ (((x) >> BIT_SHIFT_IPS_CFG_ADDR_8822B) & BIT_MASK_IPS_CFG_ADDR_8822B)
+#define BIT_SET_IPS_CFG_ADDR_8822B(x, v) \
+ (BIT_CLEAR_IPS_CFG_ADDR_8822B(x) | BIT_IPS_CFG_ADDR_8822B(v))
/* 2 REG_AES_DECRPT_CFG_8822B */
#define BIT_SHIFT_IPS_CFG_DATA_8822B 0
#define BIT_MASK_IPS_CFG_DATA_8822B 0xffffffffL
-#define BIT_IPS_CFG_DATA_8822B(x) (((x) & BIT_MASK_IPS_CFG_DATA_8822B) << BIT_SHIFT_IPS_CFG_DATA_8822B)
-#define BIT_GET_IPS_CFG_DATA_8822B(x) (((x) >> BIT_SHIFT_IPS_CFG_DATA_8822B) & BIT_MASK_IPS_CFG_DATA_8822B)
-
+#define BIT_IPS_CFG_DATA_8822B(x) \
+ (((x) & BIT_MASK_IPS_CFG_DATA_8822B) << BIT_SHIFT_IPS_CFG_DATA_8822B)
+#define BITS_IPS_CFG_DATA_8822B \
+ (BIT_MASK_IPS_CFG_DATA_8822B << BIT_SHIFT_IPS_CFG_DATA_8822B)
+#define BIT_CLEAR_IPS_CFG_DATA_8822B(x) ((x) & (~BITS_IPS_CFG_DATA_8822B))
+#define BIT_GET_IPS_CFG_DATA_8822B(x) \
+ (((x) >> BIT_SHIFT_IPS_CFG_DATA_8822B) & BIT_MASK_IPS_CFG_DATA_8822B)
+#define BIT_SET_IPS_CFG_DATA_8822B(x, v) \
+ (BIT_CLEAR_IPS_CFG_DATA_8822B(x) | BIT_IPS_CFG_DATA_8822B(v))
/* 2 REG_NOT_VALID_8822B */
@@ -2445,20 +3840,44 @@
#define BIT_SHIFT_TEMP_VALUE_8822B 24
#define BIT_MASK_TEMP_VALUE_8822B 0x3f
-#define BIT_TEMP_VALUE_8822B(x) (((x) & BIT_MASK_TEMP_VALUE_8822B) << BIT_SHIFT_TEMP_VALUE_8822B)
-#define BIT_GET_TEMP_VALUE_8822B(x) (((x) >> BIT_SHIFT_TEMP_VALUE_8822B) & BIT_MASK_TEMP_VALUE_8822B)
-
+#define BIT_TEMP_VALUE_8822B(x) \
+ (((x) & BIT_MASK_TEMP_VALUE_8822B) << BIT_SHIFT_TEMP_VALUE_8822B)
+#define BITS_TEMP_VALUE_8822B \
+ (BIT_MASK_TEMP_VALUE_8822B << BIT_SHIFT_TEMP_VALUE_8822B)
+#define BIT_CLEAR_TEMP_VALUE_8822B(x) ((x) & (~BITS_TEMP_VALUE_8822B))
+#define BIT_GET_TEMP_VALUE_8822B(x) \
+ (((x) >> BIT_SHIFT_TEMP_VALUE_8822B) & BIT_MASK_TEMP_VALUE_8822B)
+#define BIT_SET_TEMP_VALUE_8822B(x, v) \
+ (BIT_CLEAR_TEMP_VALUE_8822B(x) | BIT_TEMP_VALUE_8822B(v))
#define BIT_SHIFT_REG_TMETER_TIMER_8822B 8
#define BIT_MASK_REG_TMETER_TIMER_8822B 0xfff
-#define BIT_REG_TMETER_TIMER_8822B(x) (((x) & BIT_MASK_REG_TMETER_TIMER_8822B) << BIT_SHIFT_REG_TMETER_TIMER_8822B)
-#define BIT_GET_REG_TMETER_TIMER_8822B(x) (((x) >> BIT_SHIFT_REG_TMETER_TIMER_8822B) & BIT_MASK_REG_TMETER_TIMER_8822B)
-
+#define BIT_REG_TMETER_TIMER_8822B(x) \
+ (((x) & BIT_MASK_REG_TMETER_TIMER_8822B) \
+ << BIT_SHIFT_REG_TMETER_TIMER_8822B)
+#define BITS_REG_TMETER_TIMER_8822B \
+ (BIT_MASK_REG_TMETER_TIMER_8822B << BIT_SHIFT_REG_TMETER_TIMER_8822B)
+#define BIT_CLEAR_REG_TMETER_TIMER_8822B(x) \
+ ((x) & (~BITS_REG_TMETER_TIMER_8822B))
+#define BIT_GET_REG_TMETER_TIMER_8822B(x) \
+ (((x) >> BIT_SHIFT_REG_TMETER_TIMER_8822B) & \
+ BIT_MASK_REG_TMETER_TIMER_8822B)
+#define BIT_SET_REG_TMETER_TIMER_8822B(x, v) \
+ (BIT_CLEAR_REG_TMETER_TIMER_8822B(x) | BIT_REG_TMETER_TIMER_8822B(v))
#define BIT_SHIFT_REG_TEMP_DELTA_8822B 2
#define BIT_MASK_REG_TEMP_DELTA_8822B 0x3f
-#define BIT_REG_TEMP_DELTA_8822B(x) (((x) & BIT_MASK_REG_TEMP_DELTA_8822B) << BIT_SHIFT_REG_TEMP_DELTA_8822B)
-#define BIT_GET_REG_TEMP_DELTA_8822B(x) (((x) >> BIT_SHIFT_REG_TEMP_DELTA_8822B) & BIT_MASK_REG_TEMP_DELTA_8822B)
+#define BIT_REG_TEMP_DELTA_8822B(x) \
+ (((x) & BIT_MASK_REG_TEMP_DELTA_8822B) \
+ << BIT_SHIFT_REG_TEMP_DELTA_8822B)
+#define BITS_REG_TEMP_DELTA_8822B \
+ (BIT_MASK_REG_TEMP_DELTA_8822B << BIT_SHIFT_REG_TEMP_DELTA_8822B)
+#define BIT_CLEAR_REG_TEMP_DELTA_8822B(x) ((x) & (~BITS_REG_TEMP_DELTA_8822B))
+#define BIT_GET_REG_TEMP_DELTA_8822B(x) \
+ (((x) >> BIT_SHIFT_REG_TEMP_DELTA_8822B) & \
+ BIT_MASK_REG_TEMP_DELTA_8822B)
+#define BIT_SET_REG_TEMP_DELTA_8822B(x, v) \
+ (BIT_CLEAR_REG_TEMP_DELTA_8822B(x) | BIT_REG_TEMP_DELTA_8822B(v))
#define BIT_REG_TMETER_EN_8822B BIT(0)
@@ -2466,14 +3885,33 @@
#define BIT_SHIFT_OSC_32K_CLKGEN_0_8822B 16
#define BIT_MASK_OSC_32K_CLKGEN_0_8822B 0xffff
-#define BIT_OSC_32K_CLKGEN_0_8822B(x) (((x) & BIT_MASK_OSC_32K_CLKGEN_0_8822B) << BIT_SHIFT_OSC_32K_CLKGEN_0_8822B)
-#define BIT_GET_OSC_32K_CLKGEN_0_8822B(x) (((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0_8822B) & BIT_MASK_OSC_32K_CLKGEN_0_8822B)
-
+#define BIT_OSC_32K_CLKGEN_0_8822B(x) \
+ (((x) & BIT_MASK_OSC_32K_CLKGEN_0_8822B) \
+ << BIT_SHIFT_OSC_32K_CLKGEN_0_8822B)
+#define BITS_OSC_32K_CLKGEN_0_8822B \
+ (BIT_MASK_OSC_32K_CLKGEN_0_8822B << BIT_SHIFT_OSC_32K_CLKGEN_0_8822B)
+#define BIT_CLEAR_OSC_32K_CLKGEN_0_8822B(x) \
+ ((x) & (~BITS_OSC_32K_CLKGEN_0_8822B))
+#define BIT_GET_OSC_32K_CLKGEN_0_8822B(x) \
+ (((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0_8822B) & \
+ BIT_MASK_OSC_32K_CLKGEN_0_8822B)
+#define BIT_SET_OSC_32K_CLKGEN_0_8822B(x, v) \
+ (BIT_CLEAR_OSC_32K_CLKGEN_0_8822B(x) | BIT_OSC_32K_CLKGEN_0_8822B(v))
#define BIT_SHIFT_OSC_32K_RES_COMP_8822B 4
#define BIT_MASK_OSC_32K_RES_COMP_8822B 0x3
-#define BIT_OSC_32K_RES_COMP_8822B(x) (((x) & BIT_MASK_OSC_32K_RES_COMP_8822B) << BIT_SHIFT_OSC_32K_RES_COMP_8822B)
-#define BIT_GET_OSC_32K_RES_COMP_8822B(x) (((x) >> BIT_SHIFT_OSC_32K_RES_COMP_8822B) & BIT_MASK_OSC_32K_RES_COMP_8822B)
+#define BIT_OSC_32K_RES_COMP_8822B(x) \
+ (((x) & BIT_MASK_OSC_32K_RES_COMP_8822B) \
+ << BIT_SHIFT_OSC_32K_RES_COMP_8822B)
+#define BITS_OSC_32K_RES_COMP_8822B \
+ (BIT_MASK_OSC_32K_RES_COMP_8822B << BIT_SHIFT_OSC_32K_RES_COMP_8822B)
+#define BIT_CLEAR_OSC_32K_RES_COMP_8822B(x) \
+ ((x) & (~BITS_OSC_32K_RES_COMP_8822B))
+#define BIT_GET_OSC_32K_RES_COMP_8822B(x) \
+ (((x) >> BIT_SHIFT_OSC_32K_RES_COMP_8822B) & \
+ BIT_MASK_OSC_32K_RES_COMP_8822B)
+#define BIT_SET_OSC_32K_RES_COMP_8822B(x, v) \
+ (BIT_CLEAR_OSC_32K_RES_COMP_8822B(x) | BIT_OSC_32K_RES_COMP_8822B(v))
#define BIT_OSC_32K_OUT_SEL_8822B BIT(3)
#define BIT_ISO_WL_2_OSC_32K_8822B BIT(1)
@@ -2485,65 +3923,164 @@
#define BIT_SHIFT_CAL_32K_REG_ADDR_8822B 16
#define BIT_MASK_CAL_32K_REG_ADDR_8822B 0x3f
-#define BIT_CAL_32K_REG_ADDR_8822B(x) (((x) & BIT_MASK_CAL_32K_REG_ADDR_8822B) << BIT_SHIFT_CAL_32K_REG_ADDR_8822B)
-#define BIT_GET_CAL_32K_REG_ADDR_8822B(x) (((x) >> BIT_SHIFT_CAL_32K_REG_ADDR_8822B) & BIT_MASK_CAL_32K_REG_ADDR_8822B)
-
+#define BIT_CAL_32K_REG_ADDR_8822B(x) \
+ (((x) & BIT_MASK_CAL_32K_REG_ADDR_8822B) \
+ << BIT_SHIFT_CAL_32K_REG_ADDR_8822B)
+#define BITS_CAL_32K_REG_ADDR_8822B \
+ (BIT_MASK_CAL_32K_REG_ADDR_8822B << BIT_SHIFT_CAL_32K_REG_ADDR_8822B)
+#define BIT_CLEAR_CAL_32K_REG_ADDR_8822B(x) \
+ ((x) & (~BITS_CAL_32K_REG_ADDR_8822B))
+#define BIT_GET_CAL_32K_REG_ADDR_8822B(x) \
+ (((x) >> BIT_SHIFT_CAL_32K_REG_ADDR_8822B) & \
+ BIT_MASK_CAL_32K_REG_ADDR_8822B)
+#define BIT_SET_CAL_32K_REG_ADDR_8822B(x, v) \
+ (BIT_CLEAR_CAL_32K_REG_ADDR_8822B(x) | BIT_CAL_32K_REG_ADDR_8822B(v))
#define BIT_SHIFT_CAL_32K_REG_DATA_8822B 0
#define BIT_MASK_CAL_32K_REG_DATA_8822B 0xffff
-#define BIT_CAL_32K_REG_DATA_8822B(x) (((x) & BIT_MASK_CAL_32K_REG_DATA_8822B) << BIT_SHIFT_CAL_32K_REG_DATA_8822B)
-#define BIT_GET_CAL_32K_REG_DATA_8822B(x) (((x) >> BIT_SHIFT_CAL_32K_REG_DATA_8822B) & BIT_MASK_CAL_32K_REG_DATA_8822B)
-
+#define BIT_CAL_32K_REG_DATA_8822B(x) \
+ (((x) & BIT_MASK_CAL_32K_REG_DATA_8822B) \
+ << BIT_SHIFT_CAL_32K_REG_DATA_8822B)
+#define BITS_CAL_32K_REG_DATA_8822B \
+ (BIT_MASK_CAL_32K_REG_DATA_8822B << BIT_SHIFT_CAL_32K_REG_DATA_8822B)
+#define BIT_CLEAR_CAL_32K_REG_DATA_8822B(x) \
+ ((x) & (~BITS_CAL_32K_REG_DATA_8822B))
+#define BIT_GET_CAL_32K_REG_DATA_8822B(x) \
+ (((x) >> BIT_SHIFT_CAL_32K_REG_DATA_8822B) & \
+ BIT_MASK_CAL_32K_REG_DATA_8822B)
+#define BIT_SET_CAL_32K_REG_DATA_8822B(x, v) \
+ (BIT_CLEAR_CAL_32K_REG_DATA_8822B(x) | BIT_CAL_32K_REG_DATA_8822B(v))
/* 2 REG_NOT_VALID_8822B */
/* 2 REG_C2HEVT_8822B */
-#define BIT_SHIFT_C2HEVT_MSG_8822B 0
-#define BIT_MASK_C2HEVT_MSG_8822B 0xffffffffffffffffffffffffffffffffL
-#define BIT_C2HEVT_MSG_8822B(x) (((x) & BIT_MASK_C2HEVT_MSG_8822B) << BIT_SHIFT_C2HEVT_MSG_8822B)
-#define BIT_GET_C2HEVT_MSG_8822B(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_8822B) & BIT_MASK_C2HEVT_MSG_8822B)
-
+#define BIT_SHIFT_C2HEVT_MSG_V1_8822B 0
+#define BIT_MASK_C2HEVT_MSG_V1_8822B 0xffffffffL
+#define BIT_C2HEVT_MSG_V1_8822B(x) \
+ (((x) & BIT_MASK_C2HEVT_MSG_V1_8822B) << BIT_SHIFT_C2HEVT_MSG_V1_8822B)
+#define BITS_C2HEVT_MSG_V1_8822B \
+ (BIT_MASK_C2HEVT_MSG_V1_8822B << BIT_SHIFT_C2HEVT_MSG_V1_8822B)
+#define BIT_CLEAR_C2HEVT_MSG_V1_8822B(x) ((x) & (~BITS_C2HEVT_MSG_V1_8822B))
+#define BIT_GET_C2HEVT_MSG_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_C2HEVT_MSG_V1_8822B) & BIT_MASK_C2HEVT_MSG_V1_8822B)
+#define BIT_SET_C2HEVT_MSG_V1_8822B(x, v) \
+ (BIT_CLEAR_C2HEVT_MSG_V1_8822B(x) | BIT_C2HEVT_MSG_V1_8822B(v))
+
+/* 2 REG_C2HEVT_1_8822B */
+
+#define BIT_SHIFT_C2HEVT_MSG_1_8822B 0
+#define BIT_MASK_C2HEVT_MSG_1_8822B 0xffffffffL
+#define BIT_C2HEVT_MSG_1_8822B(x) \
+ (((x) & BIT_MASK_C2HEVT_MSG_1_8822B) << BIT_SHIFT_C2HEVT_MSG_1_8822B)
+#define BITS_C2HEVT_MSG_1_8822B \
+ (BIT_MASK_C2HEVT_MSG_1_8822B << BIT_SHIFT_C2HEVT_MSG_1_8822B)
+#define BIT_CLEAR_C2HEVT_MSG_1_8822B(x) ((x) & (~BITS_C2HEVT_MSG_1_8822B))
+#define BIT_GET_C2HEVT_MSG_1_8822B(x) \
+ (((x) >> BIT_SHIFT_C2HEVT_MSG_1_8822B) & BIT_MASK_C2HEVT_MSG_1_8822B)
+#define BIT_SET_C2HEVT_MSG_1_8822B(x, v) \
+ (BIT_CLEAR_C2HEVT_MSG_1_8822B(x) | BIT_C2HEVT_MSG_1_8822B(v))
+
+/* 2 REG_C2HEVT_2_8822B */
+
+#define BIT_SHIFT_C2HEVT_MSG_2_8822B 0
+#define BIT_MASK_C2HEVT_MSG_2_8822B 0xffffffffL
+#define BIT_C2HEVT_MSG_2_8822B(x) \
+ (((x) & BIT_MASK_C2HEVT_MSG_2_8822B) << BIT_SHIFT_C2HEVT_MSG_2_8822B)
+#define BITS_C2HEVT_MSG_2_8822B \
+ (BIT_MASK_C2HEVT_MSG_2_8822B << BIT_SHIFT_C2HEVT_MSG_2_8822B)
+#define BIT_CLEAR_C2HEVT_MSG_2_8822B(x) ((x) & (~BITS_C2HEVT_MSG_2_8822B))
+#define BIT_GET_C2HEVT_MSG_2_8822B(x) \
+ (((x) >> BIT_SHIFT_C2HEVT_MSG_2_8822B) & BIT_MASK_C2HEVT_MSG_2_8822B)
+#define BIT_SET_C2HEVT_MSG_2_8822B(x, v) \
+ (BIT_CLEAR_C2HEVT_MSG_2_8822B(x) | BIT_C2HEVT_MSG_2_8822B(v))
+
+/* 2 REG_C2HEVT_3_8822B */
+
+#define BIT_SHIFT_C2HEVT_MSG_3_8822B 0
+#define BIT_MASK_C2HEVT_MSG_3_8822B 0xffffffffL
+#define BIT_C2HEVT_MSG_3_8822B(x) \
+ (((x) & BIT_MASK_C2HEVT_MSG_3_8822B) << BIT_SHIFT_C2HEVT_MSG_3_8822B)
+#define BITS_C2HEVT_MSG_3_8822B \
+ (BIT_MASK_C2HEVT_MSG_3_8822B << BIT_SHIFT_C2HEVT_MSG_3_8822B)
+#define BIT_CLEAR_C2HEVT_MSG_3_8822B(x) ((x) & (~BITS_C2HEVT_MSG_3_8822B))
+#define BIT_GET_C2HEVT_MSG_3_8822B(x) \
+ (((x) >> BIT_SHIFT_C2HEVT_MSG_3_8822B) & BIT_MASK_C2HEVT_MSG_3_8822B)
+#define BIT_SET_C2HEVT_MSG_3_8822B(x, v) \
+ (BIT_CLEAR_C2HEVT_MSG_3_8822B(x) | BIT_C2HEVT_MSG_3_8822B(v))
/* 2 REG_SW_DEFINED_PAGE1_8822B */
#define BIT_SHIFT_SW_DEFINED_PAGE1_8822B 0
#define BIT_MASK_SW_DEFINED_PAGE1_8822B 0xffffffffffffffffL
-#define BIT_SW_DEFINED_PAGE1_8822B(x) (((x) & BIT_MASK_SW_DEFINED_PAGE1_8822B) << BIT_SHIFT_SW_DEFINED_PAGE1_8822B)
-#define BIT_GET_SW_DEFINED_PAGE1_8822B(x) (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_8822B) & BIT_MASK_SW_DEFINED_PAGE1_8822B)
-
+#define BIT_SW_DEFINED_PAGE1_8822B(x) \
+ (((x) & BIT_MASK_SW_DEFINED_PAGE1_8822B) \
+ << BIT_SHIFT_SW_DEFINED_PAGE1_8822B)
+#define BITS_SW_DEFINED_PAGE1_8822B \
+ (BIT_MASK_SW_DEFINED_PAGE1_8822B << BIT_SHIFT_SW_DEFINED_PAGE1_8822B)
+#define BIT_CLEAR_SW_DEFINED_PAGE1_8822B(x) \
+ ((x) & (~BITS_SW_DEFINED_PAGE1_8822B))
+#define BIT_GET_SW_DEFINED_PAGE1_8822B(x) \
+ (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_8822B) & \
+ BIT_MASK_SW_DEFINED_PAGE1_8822B)
+#define BIT_SET_SW_DEFINED_PAGE1_8822B(x, v) \
+ (BIT_CLEAR_SW_DEFINED_PAGE1_8822B(x) | BIT_SW_DEFINED_PAGE1_8822B(v))
/* 2 REG_MCUTST_I_8822B */
#define BIT_SHIFT_MCUDMSG_I_8822B 0
#define BIT_MASK_MCUDMSG_I_8822B 0xffffffffL
-#define BIT_MCUDMSG_I_8822B(x) (((x) & BIT_MASK_MCUDMSG_I_8822B) << BIT_SHIFT_MCUDMSG_I_8822B)
-#define BIT_GET_MCUDMSG_I_8822B(x) (((x) >> BIT_SHIFT_MCUDMSG_I_8822B) & BIT_MASK_MCUDMSG_I_8822B)
-
+#define BIT_MCUDMSG_I_8822B(x) \
+ (((x) & BIT_MASK_MCUDMSG_I_8822B) << BIT_SHIFT_MCUDMSG_I_8822B)
+#define BITS_MCUDMSG_I_8822B \
+ (BIT_MASK_MCUDMSG_I_8822B << BIT_SHIFT_MCUDMSG_I_8822B)
+#define BIT_CLEAR_MCUDMSG_I_8822B(x) ((x) & (~BITS_MCUDMSG_I_8822B))
+#define BIT_GET_MCUDMSG_I_8822B(x) \
+ (((x) >> BIT_SHIFT_MCUDMSG_I_8822B) & BIT_MASK_MCUDMSG_I_8822B)
+#define BIT_SET_MCUDMSG_I_8822B(x, v) \
+ (BIT_CLEAR_MCUDMSG_I_8822B(x) | BIT_MCUDMSG_I_8822B(v))
/* 2 REG_MCUTST_II_8822B */
#define BIT_SHIFT_MCUDMSG_II_8822B 0
#define BIT_MASK_MCUDMSG_II_8822B 0xffffffffL
-#define BIT_MCUDMSG_II_8822B(x) (((x) & BIT_MASK_MCUDMSG_II_8822B) << BIT_SHIFT_MCUDMSG_II_8822B)
-#define BIT_GET_MCUDMSG_II_8822B(x) (((x) >> BIT_SHIFT_MCUDMSG_II_8822B) & BIT_MASK_MCUDMSG_II_8822B)
-
+#define BIT_MCUDMSG_II_8822B(x) \
+ (((x) & BIT_MASK_MCUDMSG_II_8822B) << BIT_SHIFT_MCUDMSG_II_8822B)
+#define BITS_MCUDMSG_II_8822B \
+ (BIT_MASK_MCUDMSG_II_8822B << BIT_SHIFT_MCUDMSG_II_8822B)
+#define BIT_CLEAR_MCUDMSG_II_8822B(x) ((x) & (~BITS_MCUDMSG_II_8822B))
+#define BIT_GET_MCUDMSG_II_8822B(x) \
+ (((x) >> BIT_SHIFT_MCUDMSG_II_8822B) & BIT_MASK_MCUDMSG_II_8822B)
+#define BIT_SET_MCUDMSG_II_8822B(x, v) \
+ (BIT_CLEAR_MCUDMSG_II_8822B(x) | BIT_MCUDMSG_II_8822B(v))
/* 2 REG_FMETHR_8822B */
#define BIT_FMSG_INT_8822B BIT(31)
#define BIT_SHIFT_FW_MSG_8822B 0
#define BIT_MASK_FW_MSG_8822B 0xffffffffL
-#define BIT_FW_MSG_8822B(x) (((x) & BIT_MASK_FW_MSG_8822B) << BIT_SHIFT_FW_MSG_8822B)
-#define BIT_GET_FW_MSG_8822B(x) (((x) >> BIT_SHIFT_FW_MSG_8822B) & BIT_MASK_FW_MSG_8822B)
-
+#define BIT_FW_MSG_8822B(x) \
+ (((x) & BIT_MASK_FW_MSG_8822B) << BIT_SHIFT_FW_MSG_8822B)
+#define BITS_FW_MSG_8822B (BIT_MASK_FW_MSG_8822B << BIT_SHIFT_FW_MSG_8822B)
+#define BIT_CLEAR_FW_MSG_8822B(x) ((x) & (~BITS_FW_MSG_8822B))
+#define BIT_GET_FW_MSG_8822B(x) \
+ (((x) >> BIT_SHIFT_FW_MSG_8822B) & BIT_MASK_FW_MSG_8822B)
+#define BIT_SET_FW_MSG_8822B(x, v) \
+ (BIT_CLEAR_FW_MSG_8822B(x) | BIT_FW_MSG_8822B(v))
/* 2 REG_HMETFR_8822B */
#define BIT_SHIFT_HRCV_MSG_8822B 24
#define BIT_MASK_HRCV_MSG_8822B 0xff
-#define BIT_HRCV_MSG_8822B(x) (((x) & BIT_MASK_HRCV_MSG_8822B) << BIT_SHIFT_HRCV_MSG_8822B)
-#define BIT_GET_HRCV_MSG_8822B(x) (((x) >> BIT_SHIFT_HRCV_MSG_8822B) & BIT_MASK_HRCV_MSG_8822B)
+#define BIT_HRCV_MSG_8822B(x) \
+ (((x) & BIT_MASK_HRCV_MSG_8822B) << BIT_SHIFT_HRCV_MSG_8822B)
+#define BITS_HRCV_MSG_8822B \
+ (BIT_MASK_HRCV_MSG_8822B << BIT_SHIFT_HRCV_MSG_8822B)
+#define BIT_CLEAR_HRCV_MSG_8822B(x) ((x) & (~BITS_HRCV_MSG_8822B))
+#define BIT_GET_HRCV_MSG_8822B(x) \
+ (((x) >> BIT_SHIFT_HRCV_MSG_8822B) & BIT_MASK_HRCV_MSG_8822B)
+#define BIT_SET_HRCV_MSG_8822B(x, v) \
+ (BIT_CLEAR_HRCV_MSG_8822B(x) | BIT_HRCV_MSG_8822B(v))
#define BIT_INT_BOX3_8822B BIT(3)
#define BIT_INT_BOX2_8822B BIT(2)
@@ -2554,80 +4091,152 @@
#define BIT_SHIFT_HOST_MSG_0_8822B 0
#define BIT_MASK_HOST_MSG_0_8822B 0xffffffffL
-#define BIT_HOST_MSG_0_8822B(x) (((x) & BIT_MASK_HOST_MSG_0_8822B) << BIT_SHIFT_HOST_MSG_0_8822B)
-#define BIT_GET_HOST_MSG_0_8822B(x) (((x) >> BIT_SHIFT_HOST_MSG_0_8822B) & BIT_MASK_HOST_MSG_0_8822B)
-
+#define BIT_HOST_MSG_0_8822B(x) \
+ (((x) & BIT_MASK_HOST_MSG_0_8822B) << BIT_SHIFT_HOST_MSG_0_8822B)
+#define BITS_HOST_MSG_0_8822B \
+ (BIT_MASK_HOST_MSG_0_8822B << BIT_SHIFT_HOST_MSG_0_8822B)
+#define BIT_CLEAR_HOST_MSG_0_8822B(x) ((x) & (~BITS_HOST_MSG_0_8822B))
+#define BIT_GET_HOST_MSG_0_8822B(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_0_8822B) & BIT_MASK_HOST_MSG_0_8822B)
+#define BIT_SET_HOST_MSG_0_8822B(x, v) \
+ (BIT_CLEAR_HOST_MSG_0_8822B(x) | BIT_HOST_MSG_0_8822B(v))
/* 2 REG_HMEBOX1_8822B */
#define BIT_SHIFT_HOST_MSG_1_8822B 0
#define BIT_MASK_HOST_MSG_1_8822B 0xffffffffL
-#define BIT_HOST_MSG_1_8822B(x) (((x) & BIT_MASK_HOST_MSG_1_8822B) << BIT_SHIFT_HOST_MSG_1_8822B)
-#define BIT_GET_HOST_MSG_1_8822B(x) (((x) >> BIT_SHIFT_HOST_MSG_1_8822B) & BIT_MASK_HOST_MSG_1_8822B)
-
+#define BIT_HOST_MSG_1_8822B(x) \
+ (((x) & BIT_MASK_HOST_MSG_1_8822B) << BIT_SHIFT_HOST_MSG_1_8822B)
+#define BITS_HOST_MSG_1_8822B \
+ (BIT_MASK_HOST_MSG_1_8822B << BIT_SHIFT_HOST_MSG_1_8822B)
+#define BIT_CLEAR_HOST_MSG_1_8822B(x) ((x) & (~BITS_HOST_MSG_1_8822B))
+#define BIT_GET_HOST_MSG_1_8822B(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_1_8822B) & BIT_MASK_HOST_MSG_1_8822B)
+#define BIT_SET_HOST_MSG_1_8822B(x, v) \
+ (BIT_CLEAR_HOST_MSG_1_8822B(x) | BIT_HOST_MSG_1_8822B(v))
/* 2 REG_HMEBOX2_8822B */
#define BIT_SHIFT_HOST_MSG_2_8822B 0
#define BIT_MASK_HOST_MSG_2_8822B 0xffffffffL
-#define BIT_HOST_MSG_2_8822B(x) (((x) & BIT_MASK_HOST_MSG_2_8822B) << BIT_SHIFT_HOST_MSG_2_8822B)
-#define BIT_GET_HOST_MSG_2_8822B(x) (((x) >> BIT_SHIFT_HOST_MSG_2_8822B) & BIT_MASK_HOST_MSG_2_8822B)
-
+#define BIT_HOST_MSG_2_8822B(x) \
+ (((x) & BIT_MASK_HOST_MSG_2_8822B) << BIT_SHIFT_HOST_MSG_2_8822B)
+#define BITS_HOST_MSG_2_8822B \
+ (BIT_MASK_HOST_MSG_2_8822B << BIT_SHIFT_HOST_MSG_2_8822B)
+#define BIT_CLEAR_HOST_MSG_2_8822B(x) ((x) & (~BITS_HOST_MSG_2_8822B))
+#define BIT_GET_HOST_MSG_2_8822B(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_2_8822B) & BIT_MASK_HOST_MSG_2_8822B)
+#define BIT_SET_HOST_MSG_2_8822B(x, v) \
+ (BIT_CLEAR_HOST_MSG_2_8822B(x) | BIT_HOST_MSG_2_8822B(v))
/* 2 REG_HMEBOX3_8822B */
#define BIT_SHIFT_HOST_MSG_3_8822B 0
#define BIT_MASK_HOST_MSG_3_8822B 0xffffffffL
-#define BIT_HOST_MSG_3_8822B(x) (((x) & BIT_MASK_HOST_MSG_3_8822B) << BIT_SHIFT_HOST_MSG_3_8822B)
-#define BIT_GET_HOST_MSG_3_8822B(x) (((x) >> BIT_SHIFT_HOST_MSG_3_8822B) & BIT_MASK_HOST_MSG_3_8822B)
-
+#define BIT_HOST_MSG_3_8822B(x) \
+ (((x) & BIT_MASK_HOST_MSG_3_8822B) << BIT_SHIFT_HOST_MSG_3_8822B)
+#define BITS_HOST_MSG_3_8822B \
+ (BIT_MASK_HOST_MSG_3_8822B << BIT_SHIFT_HOST_MSG_3_8822B)
+#define BIT_CLEAR_HOST_MSG_3_8822B(x) ((x) & (~BITS_HOST_MSG_3_8822B))
+#define BIT_GET_HOST_MSG_3_8822B(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_3_8822B) & BIT_MASK_HOST_MSG_3_8822B)
+#define BIT_SET_HOST_MSG_3_8822B(x, v) \
+ (BIT_CLEAR_HOST_MSG_3_8822B(x) | BIT_HOST_MSG_3_8822B(v))
/* 2 REG_LLT_INIT_8822B */
#define BIT_SHIFT_LLTE_RWM_8822B 30
#define BIT_MASK_LLTE_RWM_8822B 0x3
-#define BIT_LLTE_RWM_8822B(x) (((x) & BIT_MASK_LLTE_RWM_8822B) << BIT_SHIFT_LLTE_RWM_8822B)
-#define BIT_GET_LLTE_RWM_8822B(x) (((x) >> BIT_SHIFT_LLTE_RWM_8822B) & BIT_MASK_LLTE_RWM_8822B)
-
+#define BIT_LLTE_RWM_8822B(x) \
+ (((x) & BIT_MASK_LLTE_RWM_8822B) << BIT_SHIFT_LLTE_RWM_8822B)
+#define BITS_LLTE_RWM_8822B \
+ (BIT_MASK_LLTE_RWM_8822B << BIT_SHIFT_LLTE_RWM_8822B)
+#define BIT_CLEAR_LLTE_RWM_8822B(x) ((x) & (~BITS_LLTE_RWM_8822B))
+#define BIT_GET_LLTE_RWM_8822B(x) \
+ (((x) >> BIT_SHIFT_LLTE_RWM_8822B) & BIT_MASK_LLTE_RWM_8822B)
+#define BIT_SET_LLTE_RWM_8822B(x, v) \
+ (BIT_CLEAR_LLTE_RWM_8822B(x) | BIT_LLTE_RWM_8822B(v))
#define BIT_SHIFT_LLTINI_PDATA_V1_8822B 16
#define BIT_MASK_LLTINI_PDATA_V1_8822B 0xfff
-#define BIT_LLTINI_PDATA_V1_8822B(x) (((x) & BIT_MASK_LLTINI_PDATA_V1_8822B) << BIT_SHIFT_LLTINI_PDATA_V1_8822B)
-#define BIT_GET_LLTINI_PDATA_V1_8822B(x) (((x) >> BIT_SHIFT_LLTINI_PDATA_V1_8822B) & BIT_MASK_LLTINI_PDATA_V1_8822B)
-
+#define BIT_LLTINI_PDATA_V1_8822B(x) \
+ (((x) & BIT_MASK_LLTINI_PDATA_V1_8822B) \
+ << BIT_SHIFT_LLTINI_PDATA_V1_8822B)
+#define BITS_LLTINI_PDATA_V1_8822B \
+ (BIT_MASK_LLTINI_PDATA_V1_8822B << BIT_SHIFT_LLTINI_PDATA_V1_8822B)
+#define BIT_CLEAR_LLTINI_PDATA_V1_8822B(x) ((x) & (~BITS_LLTINI_PDATA_V1_8822B))
+#define BIT_GET_LLTINI_PDATA_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_LLTINI_PDATA_V1_8822B) & \
+ BIT_MASK_LLTINI_PDATA_V1_8822B)
+#define BIT_SET_LLTINI_PDATA_V1_8822B(x, v) \
+ (BIT_CLEAR_LLTINI_PDATA_V1_8822B(x) | BIT_LLTINI_PDATA_V1_8822B(v))
#define BIT_SHIFT_LLTINI_HDATA_V1_8822B 0
#define BIT_MASK_LLTINI_HDATA_V1_8822B 0xfff
-#define BIT_LLTINI_HDATA_V1_8822B(x) (((x) & BIT_MASK_LLTINI_HDATA_V1_8822B) << BIT_SHIFT_LLTINI_HDATA_V1_8822B)
-#define BIT_GET_LLTINI_HDATA_V1_8822B(x) (((x) >> BIT_SHIFT_LLTINI_HDATA_V1_8822B) & BIT_MASK_LLTINI_HDATA_V1_8822B)
-
+#define BIT_LLTINI_HDATA_V1_8822B(x) \
+ (((x) & BIT_MASK_LLTINI_HDATA_V1_8822B) \
+ << BIT_SHIFT_LLTINI_HDATA_V1_8822B)
+#define BITS_LLTINI_HDATA_V1_8822B \
+ (BIT_MASK_LLTINI_HDATA_V1_8822B << BIT_SHIFT_LLTINI_HDATA_V1_8822B)
+#define BIT_CLEAR_LLTINI_HDATA_V1_8822B(x) ((x) & (~BITS_LLTINI_HDATA_V1_8822B))
+#define BIT_GET_LLTINI_HDATA_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_LLTINI_HDATA_V1_8822B) & \
+ BIT_MASK_LLTINI_HDATA_V1_8822B)
+#define BIT_SET_LLTINI_HDATA_V1_8822B(x, v) \
+ (BIT_CLEAR_LLTINI_HDATA_V1_8822B(x) | BIT_LLTINI_HDATA_V1_8822B(v))
/* 2 REG_LLT_INIT_ADDR_8822B */
#define BIT_SHIFT_LLTINI_ADDR_V1_8822B 0
#define BIT_MASK_LLTINI_ADDR_V1_8822B 0xfff
-#define BIT_LLTINI_ADDR_V1_8822B(x) (((x) & BIT_MASK_LLTINI_ADDR_V1_8822B) << BIT_SHIFT_LLTINI_ADDR_V1_8822B)
-#define BIT_GET_LLTINI_ADDR_V1_8822B(x) (((x) >> BIT_SHIFT_LLTINI_ADDR_V1_8822B) & BIT_MASK_LLTINI_ADDR_V1_8822B)
-
+#define BIT_LLTINI_ADDR_V1_8822B(x) \
+ (((x) & BIT_MASK_LLTINI_ADDR_V1_8822B) \
+ << BIT_SHIFT_LLTINI_ADDR_V1_8822B)
+#define BITS_LLTINI_ADDR_V1_8822B \
+ (BIT_MASK_LLTINI_ADDR_V1_8822B << BIT_SHIFT_LLTINI_ADDR_V1_8822B)
+#define BIT_CLEAR_LLTINI_ADDR_V1_8822B(x) ((x) & (~BITS_LLTINI_ADDR_V1_8822B))
+#define BIT_GET_LLTINI_ADDR_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_LLTINI_ADDR_V1_8822B) & \
+ BIT_MASK_LLTINI_ADDR_V1_8822B)
+#define BIT_SET_LLTINI_ADDR_V1_8822B(x, v) \
+ (BIT_CLEAR_LLTINI_ADDR_V1_8822B(x) | BIT_LLTINI_ADDR_V1_8822B(v))
/* 2 REG_BB_ACCESS_CTRL_8822B */
#define BIT_SHIFT_BB_WRITE_READ_8822B 30
#define BIT_MASK_BB_WRITE_READ_8822B 0x3
-#define BIT_BB_WRITE_READ_8822B(x) (((x) & BIT_MASK_BB_WRITE_READ_8822B) << BIT_SHIFT_BB_WRITE_READ_8822B)
-#define BIT_GET_BB_WRITE_READ_8822B(x) (((x) >> BIT_SHIFT_BB_WRITE_READ_8822B) & BIT_MASK_BB_WRITE_READ_8822B)
-
+#define BIT_BB_WRITE_READ_8822B(x) \
+ (((x) & BIT_MASK_BB_WRITE_READ_8822B) << BIT_SHIFT_BB_WRITE_READ_8822B)
+#define BITS_BB_WRITE_READ_8822B \
+ (BIT_MASK_BB_WRITE_READ_8822B << BIT_SHIFT_BB_WRITE_READ_8822B)
+#define BIT_CLEAR_BB_WRITE_READ_8822B(x) ((x) & (~BITS_BB_WRITE_READ_8822B))
+#define BIT_GET_BB_WRITE_READ_8822B(x) \
+ (((x) >> BIT_SHIFT_BB_WRITE_READ_8822B) & BIT_MASK_BB_WRITE_READ_8822B)
+#define BIT_SET_BB_WRITE_READ_8822B(x, v) \
+ (BIT_CLEAR_BB_WRITE_READ_8822B(x) | BIT_BB_WRITE_READ_8822B(v))
#define BIT_SHIFT_BB_WRITE_EN_8822B 12
#define BIT_MASK_BB_WRITE_EN_8822B 0xf
-#define BIT_BB_WRITE_EN_8822B(x) (((x) & BIT_MASK_BB_WRITE_EN_8822B) << BIT_SHIFT_BB_WRITE_EN_8822B)
-#define BIT_GET_BB_WRITE_EN_8822B(x) (((x) >> BIT_SHIFT_BB_WRITE_EN_8822B) & BIT_MASK_BB_WRITE_EN_8822B)
-
+#define BIT_BB_WRITE_EN_8822B(x) \
+ (((x) & BIT_MASK_BB_WRITE_EN_8822B) << BIT_SHIFT_BB_WRITE_EN_8822B)
+#define BITS_BB_WRITE_EN_8822B \
+ (BIT_MASK_BB_WRITE_EN_8822B << BIT_SHIFT_BB_WRITE_EN_8822B)
+#define BIT_CLEAR_BB_WRITE_EN_8822B(x) ((x) & (~BITS_BB_WRITE_EN_8822B))
+#define BIT_GET_BB_WRITE_EN_8822B(x) \
+ (((x) >> BIT_SHIFT_BB_WRITE_EN_8822B) & BIT_MASK_BB_WRITE_EN_8822B)
+#define BIT_SET_BB_WRITE_EN_8822B(x, v) \
+ (BIT_CLEAR_BB_WRITE_EN_8822B(x) | BIT_BB_WRITE_EN_8822B(v))
#define BIT_SHIFT_BB_ADDR_8822B 2
#define BIT_MASK_BB_ADDR_8822B 0x1ff
-#define BIT_BB_ADDR_8822B(x) (((x) & BIT_MASK_BB_ADDR_8822B) << BIT_SHIFT_BB_ADDR_8822B)
-#define BIT_GET_BB_ADDR_8822B(x) (((x) >> BIT_SHIFT_BB_ADDR_8822B) & BIT_MASK_BB_ADDR_8822B)
+#define BIT_BB_ADDR_8822B(x) \
+ (((x) & BIT_MASK_BB_ADDR_8822B) << BIT_SHIFT_BB_ADDR_8822B)
+#define BITS_BB_ADDR_8822B (BIT_MASK_BB_ADDR_8822B << BIT_SHIFT_BB_ADDR_8822B)
+#define BIT_CLEAR_BB_ADDR_8822B(x) ((x) & (~BITS_BB_ADDR_8822B))
+#define BIT_GET_BB_ADDR_8822B(x) \
+ (((x) >> BIT_SHIFT_BB_ADDR_8822B) & BIT_MASK_BB_ADDR_8822B)
+#define BIT_SET_BB_ADDR_8822B(x, v) \
+ (BIT_CLEAR_BB_ADDR_8822B(x) | BIT_BB_ADDR_8822B(v))
#define BIT_BB_ERRACC_8822B BIT(0)
@@ -2635,41 +4244,70 @@
#define BIT_SHIFT_BB_DATA_8822B 0
#define BIT_MASK_BB_DATA_8822B 0xffffffffL
-#define BIT_BB_DATA_8822B(x) (((x) & BIT_MASK_BB_DATA_8822B) << BIT_SHIFT_BB_DATA_8822B)
-#define BIT_GET_BB_DATA_8822B(x) (((x) >> BIT_SHIFT_BB_DATA_8822B) & BIT_MASK_BB_DATA_8822B)
-
+#define BIT_BB_DATA_8822B(x) \
+ (((x) & BIT_MASK_BB_DATA_8822B) << BIT_SHIFT_BB_DATA_8822B)
+#define BITS_BB_DATA_8822B (BIT_MASK_BB_DATA_8822B << BIT_SHIFT_BB_DATA_8822B)
+#define BIT_CLEAR_BB_DATA_8822B(x) ((x) & (~BITS_BB_DATA_8822B))
+#define BIT_GET_BB_DATA_8822B(x) \
+ (((x) >> BIT_SHIFT_BB_DATA_8822B) & BIT_MASK_BB_DATA_8822B)
+#define BIT_SET_BB_DATA_8822B(x, v) \
+ (BIT_CLEAR_BB_DATA_8822B(x) | BIT_BB_DATA_8822B(v))
/* 2 REG_HMEBOX_E0_8822B */
#define BIT_SHIFT_HMEBOX_E0_8822B 0
#define BIT_MASK_HMEBOX_E0_8822B 0xffffffffL
-#define BIT_HMEBOX_E0_8822B(x) (((x) & BIT_MASK_HMEBOX_E0_8822B) << BIT_SHIFT_HMEBOX_E0_8822B)
-#define BIT_GET_HMEBOX_E0_8822B(x) (((x) >> BIT_SHIFT_HMEBOX_E0_8822B) & BIT_MASK_HMEBOX_E0_8822B)
-
+#define BIT_HMEBOX_E0_8822B(x) \
+ (((x) & BIT_MASK_HMEBOX_E0_8822B) << BIT_SHIFT_HMEBOX_E0_8822B)
+#define BITS_HMEBOX_E0_8822B \
+ (BIT_MASK_HMEBOX_E0_8822B << BIT_SHIFT_HMEBOX_E0_8822B)
+#define BIT_CLEAR_HMEBOX_E0_8822B(x) ((x) & (~BITS_HMEBOX_E0_8822B))
+#define BIT_GET_HMEBOX_E0_8822B(x) \
+ (((x) >> BIT_SHIFT_HMEBOX_E0_8822B) & BIT_MASK_HMEBOX_E0_8822B)
+#define BIT_SET_HMEBOX_E0_8822B(x, v) \
+ (BIT_CLEAR_HMEBOX_E0_8822B(x) | BIT_HMEBOX_E0_8822B(v))
/* 2 REG_HMEBOX_E1_8822B */
#define BIT_SHIFT_HMEBOX_E1_8822B 0
#define BIT_MASK_HMEBOX_E1_8822B 0xffffffffL
-#define BIT_HMEBOX_E1_8822B(x) (((x) & BIT_MASK_HMEBOX_E1_8822B) << BIT_SHIFT_HMEBOX_E1_8822B)
-#define BIT_GET_HMEBOX_E1_8822B(x) (((x) >> BIT_SHIFT_HMEBOX_E1_8822B) & BIT_MASK_HMEBOX_E1_8822B)
-
+#define BIT_HMEBOX_E1_8822B(x) \
+ (((x) & BIT_MASK_HMEBOX_E1_8822B) << BIT_SHIFT_HMEBOX_E1_8822B)
+#define BITS_HMEBOX_E1_8822B \
+ (BIT_MASK_HMEBOX_E1_8822B << BIT_SHIFT_HMEBOX_E1_8822B)
+#define BIT_CLEAR_HMEBOX_E1_8822B(x) ((x) & (~BITS_HMEBOX_E1_8822B))
+#define BIT_GET_HMEBOX_E1_8822B(x) \
+ (((x) >> BIT_SHIFT_HMEBOX_E1_8822B) & BIT_MASK_HMEBOX_E1_8822B)
+#define BIT_SET_HMEBOX_E1_8822B(x, v) \
+ (BIT_CLEAR_HMEBOX_E1_8822B(x) | BIT_HMEBOX_E1_8822B(v))
/* 2 REG_HMEBOX_E2_8822B */
#define BIT_SHIFT_HMEBOX_E2_8822B 0
#define BIT_MASK_HMEBOX_E2_8822B 0xffffffffL
-#define BIT_HMEBOX_E2_8822B(x) (((x) & BIT_MASK_HMEBOX_E2_8822B) << BIT_SHIFT_HMEBOX_E2_8822B)
-#define BIT_GET_HMEBOX_E2_8822B(x) (((x) >> BIT_SHIFT_HMEBOX_E2_8822B) & BIT_MASK_HMEBOX_E2_8822B)
-
+#define BIT_HMEBOX_E2_8822B(x) \
+ (((x) & BIT_MASK_HMEBOX_E2_8822B) << BIT_SHIFT_HMEBOX_E2_8822B)
+#define BITS_HMEBOX_E2_8822B \
+ (BIT_MASK_HMEBOX_E2_8822B << BIT_SHIFT_HMEBOX_E2_8822B)
+#define BIT_CLEAR_HMEBOX_E2_8822B(x) ((x) & (~BITS_HMEBOX_E2_8822B))
+#define BIT_GET_HMEBOX_E2_8822B(x) \
+ (((x) >> BIT_SHIFT_HMEBOX_E2_8822B) & BIT_MASK_HMEBOX_E2_8822B)
+#define BIT_SET_HMEBOX_E2_8822B(x, v) \
+ (BIT_CLEAR_HMEBOX_E2_8822B(x) | BIT_HMEBOX_E2_8822B(v))
/* 2 REG_HMEBOX_E3_8822B */
#define BIT_SHIFT_HMEBOX_E3_8822B 0
#define BIT_MASK_HMEBOX_E3_8822B 0xffffffffL
-#define BIT_HMEBOX_E3_8822B(x) (((x) & BIT_MASK_HMEBOX_E3_8822B) << BIT_SHIFT_HMEBOX_E3_8822B)
-#define BIT_GET_HMEBOX_E3_8822B(x) (((x) >> BIT_SHIFT_HMEBOX_E3_8822B) & BIT_MASK_HMEBOX_E3_8822B)
-
+#define BIT_HMEBOX_E3_8822B(x) \
+ (((x) & BIT_MASK_HMEBOX_E3_8822B) << BIT_SHIFT_HMEBOX_E3_8822B)
+#define BITS_HMEBOX_E3_8822B \
+ (BIT_MASK_HMEBOX_E3_8822B << BIT_SHIFT_HMEBOX_E3_8822B)
+#define BIT_CLEAR_HMEBOX_E3_8822B(x) ((x) & (~BITS_HMEBOX_E3_8822B))
+#define BIT_GET_HMEBOX_E3_8822B(x) \
+ (((x) >> BIT_SHIFT_HMEBOX_E3_8822B) & BIT_MASK_HMEBOX_E3_8822B)
+#define BIT_SET_HMEBOX_E3_8822B(x, v) \
+ (BIT_CLEAR_HMEBOX_E3_8822B(x) | BIT_HMEBOX_E3_8822B(v))
/* 2 REG_NOT_VALID_8822B */
@@ -2677,48 +4315,88 @@
#define BIT_SHIFT_PHY_REQ_DELAY_8822B 24
#define BIT_MASK_PHY_REQ_DELAY_8822B 0xf
-#define BIT_PHY_REQ_DELAY_8822B(x) (((x) & BIT_MASK_PHY_REQ_DELAY_8822B) << BIT_SHIFT_PHY_REQ_DELAY_8822B)
-#define BIT_GET_PHY_REQ_DELAY_8822B(x) (((x) >> BIT_SHIFT_PHY_REQ_DELAY_8822B) & BIT_MASK_PHY_REQ_DELAY_8822B)
+#define BIT_PHY_REQ_DELAY_8822B(x) \
+ (((x) & BIT_MASK_PHY_REQ_DELAY_8822B) << BIT_SHIFT_PHY_REQ_DELAY_8822B)
+#define BITS_PHY_REQ_DELAY_8822B \
+ (BIT_MASK_PHY_REQ_DELAY_8822B << BIT_SHIFT_PHY_REQ_DELAY_8822B)
+#define BIT_CLEAR_PHY_REQ_DELAY_8822B(x) ((x) & (~BITS_PHY_REQ_DELAY_8822B))
+#define BIT_GET_PHY_REQ_DELAY_8822B(x) \
+ (((x) >> BIT_SHIFT_PHY_REQ_DELAY_8822B) & BIT_MASK_PHY_REQ_DELAY_8822B)
+#define BIT_SET_PHY_REQ_DELAY_8822B(x, v) \
+ (BIT_CLEAR_PHY_REQ_DELAY_8822B(x) | BIT_PHY_REQ_DELAY_8822B(v))
#define BIT_SPD_DOWN_8822B BIT(16)
#define BIT_SHIFT_NETYPE4_8822B 4
#define BIT_MASK_NETYPE4_8822B 0x3
-#define BIT_NETYPE4_8822B(x) (((x) & BIT_MASK_NETYPE4_8822B) << BIT_SHIFT_NETYPE4_8822B)
-#define BIT_GET_NETYPE4_8822B(x) (((x) >> BIT_SHIFT_NETYPE4_8822B) & BIT_MASK_NETYPE4_8822B)
-
+#define BIT_NETYPE4_8822B(x) \
+ (((x) & BIT_MASK_NETYPE4_8822B) << BIT_SHIFT_NETYPE4_8822B)
+#define BITS_NETYPE4_8822B (BIT_MASK_NETYPE4_8822B << BIT_SHIFT_NETYPE4_8822B)
+#define BIT_CLEAR_NETYPE4_8822B(x) ((x) & (~BITS_NETYPE4_8822B))
+#define BIT_GET_NETYPE4_8822B(x) \
+ (((x) >> BIT_SHIFT_NETYPE4_8822B) & BIT_MASK_NETYPE4_8822B)
+#define BIT_SET_NETYPE4_8822B(x, v) \
+ (BIT_CLEAR_NETYPE4_8822B(x) | BIT_NETYPE4_8822B(v))
#define BIT_SHIFT_NETYPE3_8822B 2
#define BIT_MASK_NETYPE3_8822B 0x3
-#define BIT_NETYPE3_8822B(x) (((x) & BIT_MASK_NETYPE3_8822B) << BIT_SHIFT_NETYPE3_8822B)
-#define BIT_GET_NETYPE3_8822B(x) (((x) >> BIT_SHIFT_NETYPE3_8822B) & BIT_MASK_NETYPE3_8822B)
-
+#define BIT_NETYPE3_8822B(x) \
+ (((x) & BIT_MASK_NETYPE3_8822B) << BIT_SHIFT_NETYPE3_8822B)
+#define BITS_NETYPE3_8822B (BIT_MASK_NETYPE3_8822B << BIT_SHIFT_NETYPE3_8822B)
+#define BIT_CLEAR_NETYPE3_8822B(x) ((x) & (~BITS_NETYPE3_8822B))
+#define BIT_GET_NETYPE3_8822B(x) \
+ (((x) >> BIT_SHIFT_NETYPE3_8822B) & BIT_MASK_NETYPE3_8822B)
+#define BIT_SET_NETYPE3_8822B(x, v) \
+ (BIT_CLEAR_NETYPE3_8822B(x) | BIT_NETYPE3_8822B(v))
#define BIT_SHIFT_NETYPE2_8822B 0
#define BIT_MASK_NETYPE2_8822B 0x3
-#define BIT_NETYPE2_8822B(x) (((x) & BIT_MASK_NETYPE2_8822B) << BIT_SHIFT_NETYPE2_8822B)
-#define BIT_GET_NETYPE2_8822B(x) (((x) >> BIT_SHIFT_NETYPE2_8822B) & BIT_MASK_NETYPE2_8822B)
-
+#define BIT_NETYPE2_8822B(x) \
+ (((x) & BIT_MASK_NETYPE2_8822B) << BIT_SHIFT_NETYPE2_8822B)
+#define BITS_NETYPE2_8822B (BIT_MASK_NETYPE2_8822B << BIT_SHIFT_NETYPE2_8822B)
+#define BIT_CLEAR_NETYPE2_8822B(x) ((x) & (~BITS_NETYPE2_8822B))
+#define BIT_GET_NETYPE2_8822B(x) \
+ (((x) >> BIT_SHIFT_NETYPE2_8822B) & BIT_MASK_NETYPE2_8822B)
+#define BIT_SET_NETYPE2_8822B(x, v) \
+ (BIT_CLEAR_NETYPE2_8822B(x) | BIT_NETYPE2_8822B(v))
/* 2 REG_FWFF_8822B */
#define BIT_SHIFT_PKTNUM_TH_V1_8822B 24
#define BIT_MASK_PKTNUM_TH_V1_8822B 0xff
-#define BIT_PKTNUM_TH_V1_8822B(x) (((x) & BIT_MASK_PKTNUM_TH_V1_8822B) << BIT_SHIFT_PKTNUM_TH_V1_8822B)
-#define BIT_GET_PKTNUM_TH_V1_8822B(x) (((x) >> BIT_SHIFT_PKTNUM_TH_V1_8822B) & BIT_MASK_PKTNUM_TH_V1_8822B)
-
+#define BIT_PKTNUM_TH_V1_8822B(x) \
+ (((x) & BIT_MASK_PKTNUM_TH_V1_8822B) << BIT_SHIFT_PKTNUM_TH_V1_8822B)
+#define BITS_PKTNUM_TH_V1_8822B \
+ (BIT_MASK_PKTNUM_TH_V1_8822B << BIT_SHIFT_PKTNUM_TH_V1_8822B)
+#define BIT_CLEAR_PKTNUM_TH_V1_8822B(x) ((x) & (~BITS_PKTNUM_TH_V1_8822B))
+#define BIT_GET_PKTNUM_TH_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_PKTNUM_TH_V1_8822B) & BIT_MASK_PKTNUM_TH_V1_8822B)
+#define BIT_SET_PKTNUM_TH_V1_8822B(x, v) \
+ (BIT_CLEAR_PKTNUM_TH_V1_8822B(x) | BIT_PKTNUM_TH_V1_8822B(v))
#define BIT_SHIFT_TIMER_TH_8822B 16
#define BIT_MASK_TIMER_TH_8822B 0xff
-#define BIT_TIMER_TH_8822B(x) (((x) & BIT_MASK_TIMER_TH_8822B) << BIT_SHIFT_TIMER_TH_8822B)
-#define BIT_GET_TIMER_TH_8822B(x) (((x) >> BIT_SHIFT_TIMER_TH_8822B) & BIT_MASK_TIMER_TH_8822B)
-
+#define BIT_TIMER_TH_8822B(x) \
+ (((x) & BIT_MASK_TIMER_TH_8822B) << BIT_SHIFT_TIMER_TH_8822B)
+#define BITS_TIMER_TH_8822B \
+ (BIT_MASK_TIMER_TH_8822B << BIT_SHIFT_TIMER_TH_8822B)
+#define BIT_CLEAR_TIMER_TH_8822B(x) ((x) & (~BITS_TIMER_TH_8822B))
+#define BIT_GET_TIMER_TH_8822B(x) \
+ (((x) >> BIT_SHIFT_TIMER_TH_8822B) & BIT_MASK_TIMER_TH_8822B)
+#define BIT_SET_TIMER_TH_8822B(x, v) \
+ (BIT_CLEAR_TIMER_TH_8822B(x) | BIT_TIMER_TH_8822B(v))
#define BIT_SHIFT_RXPKT1ENADDR_8822B 0
#define BIT_MASK_RXPKT1ENADDR_8822B 0xffff
-#define BIT_RXPKT1ENADDR_8822B(x) (((x) & BIT_MASK_RXPKT1ENADDR_8822B) << BIT_SHIFT_RXPKT1ENADDR_8822B)
-#define BIT_GET_RXPKT1ENADDR_8822B(x) (((x) >> BIT_SHIFT_RXPKT1ENADDR_8822B) & BIT_MASK_RXPKT1ENADDR_8822B)
-
+#define BIT_RXPKT1ENADDR_8822B(x) \
+ (((x) & BIT_MASK_RXPKT1ENADDR_8822B) << BIT_SHIFT_RXPKT1ENADDR_8822B)
+#define BITS_RXPKT1ENADDR_8822B \
+ (BIT_MASK_RXPKT1ENADDR_8822B << BIT_SHIFT_RXPKT1ENADDR_8822B)
+#define BIT_CLEAR_RXPKT1ENADDR_8822B(x) ((x) & (~BITS_RXPKT1ENADDR_8822B))
+#define BIT_GET_RXPKT1ENADDR_8822B(x) \
+ (((x) >> BIT_SHIFT_RXPKT1ENADDR_8822B) & BIT_MASK_RXPKT1ENADDR_8822B)
+#define BIT_SET_RXPKT1ENADDR_8822B(x, v) \
+ (BIT_CLEAR_RXPKT1ENADDR_8822B(x) | BIT_RXPKT1ENADDR_8822B(v))
/* 2 REG_RXFF_PTR_V1_8822B */
@@ -2726,9 +4404,17 @@
#define BIT_SHIFT_RXFF0_RDPTR_V2_8822B 0
#define BIT_MASK_RXFF0_RDPTR_V2_8822B 0x3ffff
-#define BIT_RXFF0_RDPTR_V2_8822B(x) (((x) & BIT_MASK_RXFF0_RDPTR_V2_8822B) << BIT_SHIFT_RXFF0_RDPTR_V2_8822B)
-#define BIT_GET_RXFF0_RDPTR_V2_8822B(x) (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8822B) & BIT_MASK_RXFF0_RDPTR_V2_8822B)
-
+#define BIT_RXFF0_RDPTR_V2_8822B(x) \
+ (((x) & BIT_MASK_RXFF0_RDPTR_V2_8822B) \
+ << BIT_SHIFT_RXFF0_RDPTR_V2_8822B)
+#define BITS_RXFF0_RDPTR_V2_8822B \
+ (BIT_MASK_RXFF0_RDPTR_V2_8822B << BIT_SHIFT_RXFF0_RDPTR_V2_8822B)
+#define BIT_CLEAR_RXFF0_RDPTR_V2_8822B(x) ((x) & (~BITS_RXFF0_RDPTR_V2_8822B))
+#define BIT_GET_RXFF0_RDPTR_V2_8822B(x) \
+ (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8822B) & \
+ BIT_MASK_RXFF0_RDPTR_V2_8822B)
+#define BIT_SET_RXFF0_RDPTR_V2_8822B(x, v) \
+ (BIT_CLEAR_RXFF0_RDPTR_V2_8822B(x) | BIT_RXFF0_RDPTR_V2_8822B(v))
/* 2 REG_RXFF_WTR_V1_8822B */
@@ -2736,9 +4422,17 @@
#define BIT_SHIFT_RXFF0_WTPTR_V2_8822B 0
#define BIT_MASK_RXFF0_WTPTR_V2_8822B 0x3ffff
-#define BIT_RXFF0_WTPTR_V2_8822B(x) (((x) & BIT_MASK_RXFF0_WTPTR_V2_8822B) << BIT_SHIFT_RXFF0_WTPTR_V2_8822B)
-#define BIT_GET_RXFF0_WTPTR_V2_8822B(x) (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8822B) & BIT_MASK_RXFF0_WTPTR_V2_8822B)
-
+#define BIT_RXFF0_WTPTR_V2_8822B(x) \
+ (((x) & BIT_MASK_RXFF0_WTPTR_V2_8822B) \
+ << BIT_SHIFT_RXFF0_WTPTR_V2_8822B)
+#define BITS_RXFF0_WTPTR_V2_8822B \
+ (BIT_MASK_RXFF0_WTPTR_V2_8822B << BIT_SHIFT_RXFF0_WTPTR_V2_8822B)
+#define BIT_CLEAR_RXFF0_WTPTR_V2_8822B(x) ((x) & (~BITS_RXFF0_WTPTR_V2_8822B))
+#define BIT_GET_RXFF0_WTPTR_V2_8822B(x) \
+ (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8822B) & \
+ BIT_MASK_RXFF0_WTPTR_V2_8822B)
+#define BIT_SET_RXFF0_WTPTR_V2_8822B(x, v) \
+ (BIT_CLEAR_RXFF0_WTPTR_V2_8822B(x) | BIT_RXFF0_WTPTR_V2_8822B(v))
/* 2 REG_FE2IMR_8822B */
#define BIT__FE4ISR__IND_MSK_8822B BIT(29)
@@ -2972,47 +4666,82 @@
#define BIT_SHIFT_MID_31TO0_8822B 0
#define BIT_MASK_MID_31TO0_8822B 0xffffffffL
-#define BIT_MID_31TO0_8822B(x) (((x) & BIT_MASK_MID_31TO0_8822B) << BIT_SHIFT_MID_31TO0_8822B)
-#define BIT_GET_MID_31TO0_8822B(x) (((x) >> BIT_SHIFT_MID_31TO0_8822B) & BIT_MASK_MID_31TO0_8822B)
-
+#define BIT_MID_31TO0_8822B(x) \
+ (((x) & BIT_MASK_MID_31TO0_8822B) << BIT_SHIFT_MID_31TO0_8822B)
+#define BITS_MID_31TO0_8822B \
+ (BIT_MASK_MID_31TO0_8822B << BIT_SHIFT_MID_31TO0_8822B)
+#define BIT_CLEAR_MID_31TO0_8822B(x) ((x) & (~BITS_MID_31TO0_8822B))
+#define BIT_GET_MID_31TO0_8822B(x) \
+ (((x) >> BIT_SHIFT_MID_31TO0_8822B) & BIT_MASK_MID_31TO0_8822B)
+#define BIT_SET_MID_31TO0_8822B(x, v) \
+ (BIT_CLEAR_MID_31TO0_8822B(x) | BIT_MID_31TO0_8822B(v))
/* 2 REG_SPWR1_8822B */
#define BIT_SHIFT_MID_63TO32_8822B 0
#define BIT_MASK_MID_63TO32_8822B 0xffffffffL
-#define BIT_MID_63TO32_8822B(x) (((x) & BIT_MASK_MID_63TO32_8822B) << BIT_SHIFT_MID_63TO32_8822B)
-#define BIT_GET_MID_63TO32_8822B(x) (((x) >> BIT_SHIFT_MID_63TO32_8822B) & BIT_MASK_MID_63TO32_8822B)
-
+#define BIT_MID_63TO32_8822B(x) \
+ (((x) & BIT_MASK_MID_63TO32_8822B) << BIT_SHIFT_MID_63TO32_8822B)
+#define BITS_MID_63TO32_8822B \
+ (BIT_MASK_MID_63TO32_8822B << BIT_SHIFT_MID_63TO32_8822B)
+#define BIT_CLEAR_MID_63TO32_8822B(x) ((x) & (~BITS_MID_63TO32_8822B))
+#define BIT_GET_MID_63TO32_8822B(x) \
+ (((x) >> BIT_SHIFT_MID_63TO32_8822B) & BIT_MASK_MID_63TO32_8822B)
+#define BIT_SET_MID_63TO32_8822B(x, v) \
+ (BIT_CLEAR_MID_63TO32_8822B(x) | BIT_MID_63TO32_8822B(v))
/* 2 REG_SPWR2_8822B */
#define BIT_SHIFT_MID_95O64_8822B 0
#define BIT_MASK_MID_95O64_8822B 0xffffffffL
-#define BIT_MID_95O64_8822B(x) (((x) & BIT_MASK_MID_95O64_8822B) << BIT_SHIFT_MID_95O64_8822B)
-#define BIT_GET_MID_95O64_8822B(x) (((x) >> BIT_SHIFT_MID_95O64_8822B) & BIT_MASK_MID_95O64_8822B)
-
+#define BIT_MID_95O64_8822B(x) \
+ (((x) & BIT_MASK_MID_95O64_8822B) << BIT_SHIFT_MID_95O64_8822B)
+#define BITS_MID_95O64_8822B \
+ (BIT_MASK_MID_95O64_8822B << BIT_SHIFT_MID_95O64_8822B)
+#define BIT_CLEAR_MID_95O64_8822B(x) ((x) & (~BITS_MID_95O64_8822B))
+#define BIT_GET_MID_95O64_8822B(x) \
+ (((x) >> BIT_SHIFT_MID_95O64_8822B) & BIT_MASK_MID_95O64_8822B)
+#define BIT_SET_MID_95O64_8822B(x, v) \
+ (BIT_CLEAR_MID_95O64_8822B(x) | BIT_MID_95O64_8822B(v))
/* 2 REG_SPWR3_8822B */
#define BIT_SHIFT_MID_127TO96_8822B 0
#define BIT_MASK_MID_127TO96_8822B 0xffffffffL
-#define BIT_MID_127TO96_8822B(x) (((x) & BIT_MASK_MID_127TO96_8822B) << BIT_SHIFT_MID_127TO96_8822B)
-#define BIT_GET_MID_127TO96_8822B(x) (((x) >> BIT_SHIFT_MID_127TO96_8822B) & BIT_MASK_MID_127TO96_8822B)
-
+#define BIT_MID_127TO96_8822B(x) \
+ (((x) & BIT_MASK_MID_127TO96_8822B) << BIT_SHIFT_MID_127TO96_8822B)
+#define BITS_MID_127TO96_8822B \
+ (BIT_MASK_MID_127TO96_8822B << BIT_SHIFT_MID_127TO96_8822B)
+#define BIT_CLEAR_MID_127TO96_8822B(x) ((x) & (~BITS_MID_127TO96_8822B))
+#define BIT_GET_MID_127TO96_8822B(x) \
+ (((x) >> BIT_SHIFT_MID_127TO96_8822B) & BIT_MASK_MID_127TO96_8822B)
+#define BIT_SET_MID_127TO96_8822B(x, v) \
+ (BIT_CLEAR_MID_127TO96_8822B(x) | BIT_MID_127TO96_8822B(v))
/* 2 REG_POWSEQ_8822B */
#define BIT_SHIFT_SEQNUM_MID_8822B 16
#define BIT_MASK_SEQNUM_MID_8822B 0xffff
-#define BIT_SEQNUM_MID_8822B(x) (((x) & BIT_MASK_SEQNUM_MID_8822B) << BIT_SHIFT_SEQNUM_MID_8822B)
-#define BIT_GET_SEQNUM_MID_8822B(x) (((x) >> BIT_SHIFT_SEQNUM_MID_8822B) & BIT_MASK_SEQNUM_MID_8822B)
-
+#define BIT_SEQNUM_MID_8822B(x) \
+ (((x) & BIT_MASK_SEQNUM_MID_8822B) << BIT_SHIFT_SEQNUM_MID_8822B)
+#define BITS_SEQNUM_MID_8822B \
+ (BIT_MASK_SEQNUM_MID_8822B << BIT_SHIFT_SEQNUM_MID_8822B)
+#define BIT_CLEAR_SEQNUM_MID_8822B(x) ((x) & (~BITS_SEQNUM_MID_8822B))
+#define BIT_GET_SEQNUM_MID_8822B(x) \
+ (((x) >> BIT_SHIFT_SEQNUM_MID_8822B) & BIT_MASK_SEQNUM_MID_8822B)
+#define BIT_SET_SEQNUM_MID_8822B(x, v) \
+ (BIT_CLEAR_SEQNUM_MID_8822B(x) | BIT_SEQNUM_MID_8822B(v))
#define BIT_SHIFT_REF_MID_8822B 0
#define BIT_MASK_REF_MID_8822B 0x7f
-#define BIT_REF_MID_8822B(x) (((x) & BIT_MASK_REF_MID_8822B) << BIT_SHIFT_REF_MID_8822B)
-#define BIT_GET_REF_MID_8822B(x) (((x) >> BIT_SHIFT_REF_MID_8822B) & BIT_MASK_REF_MID_8822B)
-
+#define BIT_REF_MID_8822B(x) \
+ (((x) & BIT_MASK_REF_MID_8822B) << BIT_SHIFT_REF_MID_8822B)
+#define BITS_REF_MID_8822B (BIT_MASK_REF_MID_8822B << BIT_SHIFT_REF_MID_8822B)
+#define BIT_CLEAR_REF_MID_8822B(x) ((x) & (~BITS_REF_MID_8822B))
+#define BIT_GET_REF_MID_8822B(x) \
+ (((x) >> BIT_SHIFT_REF_MID_8822B) & BIT_MASK_REF_MID_8822B)
+#define BIT_SET_REF_MID_8822B(x, v) \
+ (BIT_CLEAR_REF_MID_8822B(x) | BIT_REF_MID_8822B(v))
/* 2 REG_TC7_CTRL_V1_8822B */
#define BIT_TC7INT_EN_8822B BIT(26)
@@ -3021,9 +4750,14 @@
#define BIT_SHIFT_TC7DATA_8822B 0
#define BIT_MASK_TC7DATA_8822B 0xffffff
-#define BIT_TC7DATA_8822B(x) (((x) & BIT_MASK_TC7DATA_8822B) << BIT_SHIFT_TC7DATA_8822B)
-#define BIT_GET_TC7DATA_8822B(x) (((x) >> BIT_SHIFT_TC7DATA_8822B) & BIT_MASK_TC7DATA_8822B)
-
+#define BIT_TC7DATA_8822B(x) \
+ (((x) & BIT_MASK_TC7DATA_8822B) << BIT_SHIFT_TC7DATA_8822B)
+#define BITS_TC7DATA_8822B (BIT_MASK_TC7DATA_8822B << BIT_SHIFT_TC7DATA_8822B)
+#define BIT_CLEAR_TC7DATA_8822B(x) ((x) & (~BITS_TC7DATA_8822B))
+#define BIT_GET_TC7DATA_8822B(x) \
+ (((x) >> BIT_SHIFT_TC7DATA_8822B) & BIT_MASK_TC7DATA_8822B)
+#define BIT_SET_TC7DATA_8822B(x, v) \
+ (BIT_CLEAR_TC7DATA_8822B(x) | BIT_TC7DATA_8822B(v))
/* 2 REG_TC8_CTRL_V1_8822B */
#define BIT_TC8INT_EN_8822B BIT(26)
@@ -3032,9 +4766,14 @@
#define BIT_SHIFT_TC8DATA_8822B 0
#define BIT_MASK_TC8DATA_8822B 0xffffff
-#define BIT_TC8DATA_8822B(x) (((x) & BIT_MASK_TC8DATA_8822B) << BIT_SHIFT_TC8DATA_8822B)
-#define BIT_GET_TC8DATA_8822B(x) (((x) >> BIT_SHIFT_TC8DATA_8822B) & BIT_MASK_TC8DATA_8822B)
-
+#define BIT_TC8DATA_8822B(x) \
+ (((x) & BIT_MASK_TC8DATA_8822B) << BIT_SHIFT_TC8DATA_8822B)
+#define BITS_TC8DATA_8822B (BIT_MASK_TC8DATA_8822B << BIT_SHIFT_TC8DATA_8822B)
+#define BIT_CLEAR_TC8DATA_8822B(x) ((x) & (~BITS_TC8DATA_8822B))
+#define BIT_GET_TC8DATA_8822B(x) \
+ (((x) >> BIT_SHIFT_TC8DATA_8822B) & BIT_MASK_TC8DATA_8822B)
+#define BIT_SET_TC8DATA_8822B(x, v) \
+ (BIT_CLEAR_TC8DATA_8822B(x) | BIT_TC8DATA_8822B(v))
/* 2 REG_FT2IMR_8822B */
#define BIT_FS_CLI3_RX_UAPSDMD1_EN_8822B BIT(31)
@@ -3096,33 +4835,53 @@
#define BIT_SHIFT_FW_MSG2_8822B 0
#define BIT_MASK_FW_MSG2_8822B 0xffffffffL
-#define BIT_FW_MSG2_8822B(x) (((x) & BIT_MASK_FW_MSG2_8822B) << BIT_SHIFT_FW_MSG2_8822B)
-#define BIT_GET_FW_MSG2_8822B(x) (((x) >> BIT_SHIFT_FW_MSG2_8822B) & BIT_MASK_FW_MSG2_8822B)
-
+#define BIT_FW_MSG2_8822B(x) \
+ (((x) & BIT_MASK_FW_MSG2_8822B) << BIT_SHIFT_FW_MSG2_8822B)
+#define BITS_FW_MSG2_8822B (BIT_MASK_FW_MSG2_8822B << BIT_SHIFT_FW_MSG2_8822B)
+#define BIT_CLEAR_FW_MSG2_8822B(x) ((x) & (~BITS_FW_MSG2_8822B))
+#define BIT_GET_FW_MSG2_8822B(x) \
+ (((x) >> BIT_SHIFT_FW_MSG2_8822B) & BIT_MASK_FW_MSG2_8822B)
+#define BIT_SET_FW_MSG2_8822B(x, v) \
+ (BIT_CLEAR_FW_MSG2_8822B(x) | BIT_FW_MSG2_8822B(v))
/* 2 REG_MSG3_8822B */
#define BIT_SHIFT_FW_MSG3_8822B 0
#define BIT_MASK_FW_MSG3_8822B 0xffffffffL
-#define BIT_FW_MSG3_8822B(x) (((x) & BIT_MASK_FW_MSG3_8822B) << BIT_SHIFT_FW_MSG3_8822B)
-#define BIT_GET_FW_MSG3_8822B(x) (((x) >> BIT_SHIFT_FW_MSG3_8822B) & BIT_MASK_FW_MSG3_8822B)
-
+#define BIT_FW_MSG3_8822B(x) \
+ (((x) & BIT_MASK_FW_MSG3_8822B) << BIT_SHIFT_FW_MSG3_8822B)
+#define BITS_FW_MSG3_8822B (BIT_MASK_FW_MSG3_8822B << BIT_SHIFT_FW_MSG3_8822B)
+#define BIT_CLEAR_FW_MSG3_8822B(x) ((x) & (~BITS_FW_MSG3_8822B))
+#define BIT_GET_FW_MSG3_8822B(x) \
+ (((x) >> BIT_SHIFT_FW_MSG3_8822B) & BIT_MASK_FW_MSG3_8822B)
+#define BIT_SET_FW_MSG3_8822B(x, v) \
+ (BIT_CLEAR_FW_MSG3_8822B(x) | BIT_FW_MSG3_8822B(v))
/* 2 REG_MSG4_8822B */
#define BIT_SHIFT_FW_MSG4_8822B 0
#define BIT_MASK_FW_MSG4_8822B 0xffffffffL
-#define BIT_FW_MSG4_8822B(x) (((x) & BIT_MASK_FW_MSG4_8822B) << BIT_SHIFT_FW_MSG4_8822B)
-#define BIT_GET_FW_MSG4_8822B(x) (((x) >> BIT_SHIFT_FW_MSG4_8822B) & BIT_MASK_FW_MSG4_8822B)
-
+#define BIT_FW_MSG4_8822B(x) \
+ (((x) & BIT_MASK_FW_MSG4_8822B) << BIT_SHIFT_FW_MSG4_8822B)
+#define BITS_FW_MSG4_8822B (BIT_MASK_FW_MSG4_8822B << BIT_SHIFT_FW_MSG4_8822B)
+#define BIT_CLEAR_FW_MSG4_8822B(x) ((x) & (~BITS_FW_MSG4_8822B))
+#define BIT_GET_FW_MSG4_8822B(x) \
+ (((x) >> BIT_SHIFT_FW_MSG4_8822B) & BIT_MASK_FW_MSG4_8822B)
+#define BIT_SET_FW_MSG4_8822B(x, v) \
+ (BIT_CLEAR_FW_MSG4_8822B(x) | BIT_FW_MSG4_8822B(v))
/* 2 REG_MSG5_8822B */
#define BIT_SHIFT_FW_MSG5_8822B 0
#define BIT_MASK_FW_MSG5_8822B 0xffffffffL
-#define BIT_FW_MSG5_8822B(x) (((x) & BIT_MASK_FW_MSG5_8822B) << BIT_SHIFT_FW_MSG5_8822B)
-#define BIT_GET_FW_MSG5_8822B(x) (((x) >> BIT_SHIFT_FW_MSG5_8822B) & BIT_MASK_FW_MSG5_8822B)
-
+#define BIT_FW_MSG5_8822B(x) \
+ (((x) & BIT_MASK_FW_MSG5_8822B) << BIT_SHIFT_FW_MSG5_8822B)
+#define BITS_FW_MSG5_8822B (BIT_MASK_FW_MSG5_8822B << BIT_SHIFT_FW_MSG5_8822B)
+#define BIT_CLEAR_FW_MSG5_8822B(x) ((x) & (~BITS_FW_MSG5_8822B))
+#define BIT_GET_FW_MSG5_8822B(x) \
+ (((x) >> BIT_SHIFT_FW_MSG5_8822B) & BIT_MASK_FW_MSG5_8822B)
+#define BIT_SET_FW_MSG5_8822B(x, v) \
+ (BIT_CLEAR_FW_MSG5_8822B(x) | BIT_FW_MSG5_8822B(v))
/* 2 REG_NOT_VALID_8822B */
@@ -3130,50 +4889,112 @@
#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822B 16
#define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822B 0xff
-#define BIT_TX_OQT_HE_FREE_SPACE_V1_8822B(x) (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822B) << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822B)
-#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1_8822B(x) (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822B) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822B)
-
+#define BIT_TX_OQT_HE_FREE_SPACE_V1_8822B(x) \
+ (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822B) \
+ << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822B)
+#define BITS_TX_OQT_HE_FREE_SPACE_V1_8822B \
+ (BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822B \
+ << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822B)
+#define BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8822B(x) \
+ ((x) & (~BITS_TX_OQT_HE_FREE_SPACE_V1_8822B))
+#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822B) & \
+ BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822B)
+#define BIT_SET_TX_OQT_HE_FREE_SPACE_V1_8822B(x, v) \
+ (BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8822B(x) | \
+ BIT_TX_OQT_HE_FREE_SPACE_V1_8822B(v))
#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822B 0
#define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822B 0xff
-#define BIT_TX_OQT_NL_FREE_SPACE_V1_8822B(x) (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822B) << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822B)
-#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1_8822B(x) (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822B) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822B)
-
+#define BIT_TX_OQT_NL_FREE_SPACE_V1_8822B(x) \
+ (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822B) \
+ << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822B)
+#define BITS_TX_OQT_NL_FREE_SPACE_V1_8822B \
+ (BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822B \
+ << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822B)
+#define BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8822B(x) \
+ ((x) & (~BITS_TX_OQT_NL_FREE_SPACE_V1_8822B))
+#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822B) & \
+ BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822B)
+#define BIT_SET_TX_OQT_NL_FREE_SPACE_V1_8822B(x, v) \
+ (BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8822B(x) | \
+ BIT_TX_OQT_NL_FREE_SPACE_V1_8822B(v))
/* 2 REG_FIFOPAGE_CTRL_2_8822B */
#define BIT_BCN_VALID_1_V1_8822B BIT(31)
#define BIT_SHIFT_BCN_HEAD_1_V1_8822B 16
#define BIT_MASK_BCN_HEAD_1_V1_8822B 0xfff
-#define BIT_BCN_HEAD_1_V1_8822B(x) (((x) & BIT_MASK_BCN_HEAD_1_V1_8822B) << BIT_SHIFT_BCN_HEAD_1_V1_8822B)
-#define BIT_GET_BCN_HEAD_1_V1_8822B(x) (((x) >> BIT_SHIFT_BCN_HEAD_1_V1_8822B) & BIT_MASK_BCN_HEAD_1_V1_8822B)
+#define BIT_BCN_HEAD_1_V1_8822B(x) \
+ (((x) & BIT_MASK_BCN_HEAD_1_V1_8822B) << BIT_SHIFT_BCN_HEAD_1_V1_8822B)
+#define BITS_BCN_HEAD_1_V1_8822B \
+ (BIT_MASK_BCN_HEAD_1_V1_8822B << BIT_SHIFT_BCN_HEAD_1_V1_8822B)
+#define BIT_CLEAR_BCN_HEAD_1_V1_8822B(x) ((x) & (~BITS_BCN_HEAD_1_V1_8822B))
+#define BIT_GET_BCN_HEAD_1_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_BCN_HEAD_1_V1_8822B) & BIT_MASK_BCN_HEAD_1_V1_8822B)
+#define BIT_SET_BCN_HEAD_1_V1_8822B(x, v) \
+ (BIT_CLEAR_BCN_HEAD_1_V1_8822B(x) | BIT_BCN_HEAD_1_V1_8822B(v))
#define BIT_BCN_VALID_V1_8822B BIT(15)
#define BIT_SHIFT_BCN_HEAD_V1_8822B 0
#define BIT_MASK_BCN_HEAD_V1_8822B 0xfff
-#define BIT_BCN_HEAD_V1_8822B(x) (((x) & BIT_MASK_BCN_HEAD_V1_8822B) << BIT_SHIFT_BCN_HEAD_V1_8822B)
-#define BIT_GET_BCN_HEAD_V1_8822B(x) (((x) >> BIT_SHIFT_BCN_HEAD_V1_8822B) & BIT_MASK_BCN_HEAD_V1_8822B)
-
+#define BIT_BCN_HEAD_V1_8822B(x) \
+ (((x) & BIT_MASK_BCN_HEAD_V1_8822B) << BIT_SHIFT_BCN_HEAD_V1_8822B)
+#define BITS_BCN_HEAD_V1_8822B \
+ (BIT_MASK_BCN_HEAD_V1_8822B << BIT_SHIFT_BCN_HEAD_V1_8822B)
+#define BIT_CLEAR_BCN_HEAD_V1_8822B(x) ((x) & (~BITS_BCN_HEAD_V1_8822B))
+#define BIT_GET_BCN_HEAD_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_BCN_HEAD_V1_8822B) & BIT_MASK_BCN_HEAD_V1_8822B)
+#define BIT_SET_BCN_HEAD_V1_8822B(x, v) \
+ (BIT_CLEAR_BCN_HEAD_V1_8822B(x) | BIT_BCN_HEAD_V1_8822B(v))
/* 2 REG_AUTO_LLT_V1_8822B */
#define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B 24
#define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B 0xff
-#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B(x) (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B) << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B)
-#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B(x) (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B)
-
+#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B(x) \
+ (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B) \
+ << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B)
+#define BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B \
+ (BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B \
+ << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B)
+#define BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B(x) \
+ ((x) & (~BITS_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B))
+#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B) & \
+ BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B)
+#define BIT_SET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B(x, v) \
+ (BIT_CLEAR_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B(x) | \
+ BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8822B(v))
#define BIT_SHIFT_LLT_FREE_PAGE_V1_8822B 8
#define BIT_MASK_LLT_FREE_PAGE_V1_8822B 0xffff
-#define BIT_LLT_FREE_PAGE_V1_8822B(x) (((x) & BIT_MASK_LLT_FREE_PAGE_V1_8822B) << BIT_SHIFT_LLT_FREE_PAGE_V1_8822B)
-#define BIT_GET_LLT_FREE_PAGE_V1_8822B(x) (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1_8822B) & BIT_MASK_LLT_FREE_PAGE_V1_8822B)
-
+#define BIT_LLT_FREE_PAGE_V1_8822B(x) \
+ (((x) & BIT_MASK_LLT_FREE_PAGE_V1_8822B) \
+ << BIT_SHIFT_LLT_FREE_PAGE_V1_8822B)
+#define BITS_LLT_FREE_PAGE_V1_8822B \
+ (BIT_MASK_LLT_FREE_PAGE_V1_8822B << BIT_SHIFT_LLT_FREE_PAGE_V1_8822B)
+#define BIT_CLEAR_LLT_FREE_PAGE_V1_8822B(x) \
+ ((x) & (~BITS_LLT_FREE_PAGE_V1_8822B))
+#define BIT_GET_LLT_FREE_PAGE_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1_8822B) & \
+ BIT_MASK_LLT_FREE_PAGE_V1_8822B)
+#define BIT_SET_LLT_FREE_PAGE_V1_8822B(x, v) \
+ (BIT_CLEAR_LLT_FREE_PAGE_V1_8822B(x) | BIT_LLT_FREE_PAGE_V1_8822B(v))
#define BIT_SHIFT_BLK_DESC_NUM_8822B 4
#define BIT_MASK_BLK_DESC_NUM_8822B 0xf
-#define BIT_BLK_DESC_NUM_8822B(x) (((x) & BIT_MASK_BLK_DESC_NUM_8822B) << BIT_SHIFT_BLK_DESC_NUM_8822B)
-#define BIT_GET_BLK_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_BLK_DESC_NUM_8822B) & BIT_MASK_BLK_DESC_NUM_8822B)
+#define BIT_BLK_DESC_NUM_8822B(x) \
+ (((x) & BIT_MASK_BLK_DESC_NUM_8822B) << BIT_SHIFT_BLK_DESC_NUM_8822B)
+#define BITS_BLK_DESC_NUM_8822B \
+ (BIT_MASK_BLK_DESC_NUM_8822B << BIT_SHIFT_BLK_DESC_NUM_8822B)
+#define BIT_CLEAR_BLK_DESC_NUM_8822B(x) ((x) & (~BITS_BLK_DESC_NUM_8822B))
+#define BIT_GET_BLK_DESC_NUM_8822B(x) \
+ (((x) >> BIT_SHIFT_BLK_DESC_NUM_8822B) & BIT_MASK_BLK_DESC_NUM_8822B)
+#define BIT_SET_BLK_DESC_NUM_8822B(x, v) \
+ (BIT_CLEAR_BLK_DESC_NUM_8822B(x) | BIT_BLK_DESC_NUM_8822B(v))
#define BIT_R_BCN_HEAD_SEL_8822B BIT(3)
#define BIT_R_EN_BCN_SW_HEAD_SEL_8822B BIT(2)
@@ -3188,8 +5009,17 @@
#define BIT_SHIFT_PG_UNDER_TH_V1_8822B 16
#define BIT_MASK_PG_UNDER_TH_V1_8822B 0xfff
-#define BIT_PG_UNDER_TH_V1_8822B(x) (((x) & BIT_MASK_PG_UNDER_TH_V1_8822B) << BIT_SHIFT_PG_UNDER_TH_V1_8822B)
-#define BIT_GET_PG_UNDER_TH_V1_8822B(x) (((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8822B) & BIT_MASK_PG_UNDER_TH_V1_8822B)
+#define BIT_PG_UNDER_TH_V1_8822B(x) \
+ (((x) & BIT_MASK_PG_UNDER_TH_V1_8822B) \
+ << BIT_SHIFT_PG_UNDER_TH_V1_8822B)
+#define BITS_PG_UNDER_TH_V1_8822B \
+ (BIT_MASK_PG_UNDER_TH_V1_8822B << BIT_SHIFT_PG_UNDER_TH_V1_8822B)
+#define BIT_CLEAR_PG_UNDER_TH_V1_8822B(x) ((x) & (~BITS_PG_UNDER_TH_V1_8822B))
+#define BIT_GET_PG_UNDER_TH_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8822B) & \
+ BIT_MASK_PG_UNDER_TH_V1_8822B)
+#define BIT_SET_PG_UNDER_TH_V1_8822B(x, v) \
+ (BIT_CLEAR_PG_UNDER_TH_V1_8822B(x) | BIT_PG_UNDER_TH_V1_8822B(v))
#define BIT_RESTORE_H2C_ADDRESS_8822B BIT(15)
#define BIT_SDIO_TXDESC_CHKSUM_EN_8822B BIT(13)
@@ -3201,9 +5031,15 @@
#define BIT_SHIFT_CHECK_OFFSET_8822B 0
#define BIT_MASK_CHECK_OFFSET_8822B 0xff
-#define BIT_CHECK_OFFSET_8822B(x) (((x) & BIT_MASK_CHECK_OFFSET_8822B) << BIT_SHIFT_CHECK_OFFSET_8822B)
-#define BIT_GET_CHECK_OFFSET_8822B(x) (((x) >> BIT_SHIFT_CHECK_OFFSET_8822B) & BIT_MASK_CHECK_OFFSET_8822B)
-
+#define BIT_CHECK_OFFSET_8822B(x) \
+ (((x) & BIT_MASK_CHECK_OFFSET_8822B) << BIT_SHIFT_CHECK_OFFSET_8822B)
+#define BITS_CHECK_OFFSET_8822B \
+ (BIT_MASK_CHECK_OFFSET_8822B << BIT_SHIFT_CHECK_OFFSET_8822B)
+#define BIT_CLEAR_CHECK_OFFSET_8822B(x) ((x) & (~BITS_CHECK_OFFSET_8822B))
+#define BIT_GET_CHECK_OFFSET_8822B(x) \
+ (((x) >> BIT_SHIFT_CHECK_OFFSET_8822B) & BIT_MASK_CHECK_OFFSET_8822B)
+#define BIT_SET_CHECK_OFFSET_8822B(x, v) \
+ (BIT_CLEAR_CHECK_OFFSET_8822B(x) | BIT_CHECK_OFFSET_8822B(v))
/* 2 REG_TXDMA_STATUS_8822B */
#define BIT_HI_OQT_UDN_8822B BIT(17)
@@ -3231,71 +5067,139 @@
#define BIT_SHIFT_HPQ_HIGH_TH_V1_8822B 16
#define BIT_MASK_HPQ_HIGH_TH_V1_8822B 0xfff
-#define BIT_HPQ_HIGH_TH_V1_8822B(x) (((x) & BIT_MASK_HPQ_HIGH_TH_V1_8822B) << BIT_SHIFT_HPQ_HIGH_TH_V1_8822B)
-#define BIT_GET_HPQ_HIGH_TH_V1_8822B(x) (((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1_8822B) & BIT_MASK_HPQ_HIGH_TH_V1_8822B)
-
+#define BIT_HPQ_HIGH_TH_V1_8822B(x) \
+ (((x) & BIT_MASK_HPQ_HIGH_TH_V1_8822B) \
+ << BIT_SHIFT_HPQ_HIGH_TH_V1_8822B)
+#define BITS_HPQ_HIGH_TH_V1_8822B \
+ (BIT_MASK_HPQ_HIGH_TH_V1_8822B << BIT_SHIFT_HPQ_HIGH_TH_V1_8822B)
+#define BIT_CLEAR_HPQ_HIGH_TH_V1_8822B(x) ((x) & (~BITS_HPQ_HIGH_TH_V1_8822B))
+#define BIT_GET_HPQ_HIGH_TH_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1_8822B) & \
+ BIT_MASK_HPQ_HIGH_TH_V1_8822B)
+#define BIT_SET_HPQ_HIGH_TH_V1_8822B(x, v) \
+ (BIT_CLEAR_HPQ_HIGH_TH_V1_8822B(x) | BIT_HPQ_HIGH_TH_V1_8822B(v))
#define BIT_SHIFT_HPQ_LOW_TH_V1_8822B 0
#define BIT_MASK_HPQ_LOW_TH_V1_8822B 0xfff
-#define BIT_HPQ_LOW_TH_V1_8822B(x) (((x) & BIT_MASK_HPQ_LOW_TH_V1_8822B) << BIT_SHIFT_HPQ_LOW_TH_V1_8822B)
-#define BIT_GET_HPQ_LOW_TH_V1_8822B(x) (((x) >> BIT_SHIFT_HPQ_LOW_TH_V1_8822B) & BIT_MASK_HPQ_LOW_TH_V1_8822B)
-
+#define BIT_HPQ_LOW_TH_V1_8822B(x) \
+ (((x) & BIT_MASK_HPQ_LOW_TH_V1_8822B) << BIT_SHIFT_HPQ_LOW_TH_V1_8822B)
+#define BITS_HPQ_LOW_TH_V1_8822B \
+ (BIT_MASK_HPQ_LOW_TH_V1_8822B << BIT_SHIFT_HPQ_LOW_TH_V1_8822B)
+#define BIT_CLEAR_HPQ_LOW_TH_V1_8822B(x) ((x) & (~BITS_HPQ_LOW_TH_V1_8822B))
+#define BIT_GET_HPQ_LOW_TH_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_HPQ_LOW_TH_V1_8822B) & BIT_MASK_HPQ_LOW_TH_V1_8822B)
+#define BIT_SET_HPQ_LOW_TH_V1_8822B(x, v) \
+ (BIT_CLEAR_HPQ_LOW_TH_V1_8822B(x) | BIT_HPQ_LOW_TH_V1_8822B(v))
/* 2 REG_TQPNT2_8822B */
#define BIT_SHIFT_NPQ_HIGH_TH_V1_8822B 16
#define BIT_MASK_NPQ_HIGH_TH_V1_8822B 0xfff
-#define BIT_NPQ_HIGH_TH_V1_8822B(x) (((x) & BIT_MASK_NPQ_HIGH_TH_V1_8822B) << BIT_SHIFT_NPQ_HIGH_TH_V1_8822B)
-#define BIT_GET_NPQ_HIGH_TH_V1_8822B(x) (((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1_8822B) & BIT_MASK_NPQ_HIGH_TH_V1_8822B)
-
+#define BIT_NPQ_HIGH_TH_V1_8822B(x) \
+ (((x) & BIT_MASK_NPQ_HIGH_TH_V1_8822B) \
+ << BIT_SHIFT_NPQ_HIGH_TH_V1_8822B)
+#define BITS_NPQ_HIGH_TH_V1_8822B \
+ (BIT_MASK_NPQ_HIGH_TH_V1_8822B << BIT_SHIFT_NPQ_HIGH_TH_V1_8822B)
+#define BIT_CLEAR_NPQ_HIGH_TH_V1_8822B(x) ((x) & (~BITS_NPQ_HIGH_TH_V1_8822B))
+#define BIT_GET_NPQ_HIGH_TH_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1_8822B) & \
+ BIT_MASK_NPQ_HIGH_TH_V1_8822B)
+#define BIT_SET_NPQ_HIGH_TH_V1_8822B(x, v) \
+ (BIT_CLEAR_NPQ_HIGH_TH_V1_8822B(x) | BIT_NPQ_HIGH_TH_V1_8822B(v))
#define BIT_SHIFT_NPQ_LOW_TH_V1_8822B 0
#define BIT_MASK_NPQ_LOW_TH_V1_8822B 0xfff
-#define BIT_NPQ_LOW_TH_V1_8822B(x) (((x) & BIT_MASK_NPQ_LOW_TH_V1_8822B) << BIT_SHIFT_NPQ_LOW_TH_V1_8822B)
-#define BIT_GET_NPQ_LOW_TH_V1_8822B(x) (((x) >> BIT_SHIFT_NPQ_LOW_TH_V1_8822B) & BIT_MASK_NPQ_LOW_TH_V1_8822B)
-
+#define BIT_NPQ_LOW_TH_V1_8822B(x) \
+ (((x) & BIT_MASK_NPQ_LOW_TH_V1_8822B) << BIT_SHIFT_NPQ_LOW_TH_V1_8822B)
+#define BITS_NPQ_LOW_TH_V1_8822B \
+ (BIT_MASK_NPQ_LOW_TH_V1_8822B << BIT_SHIFT_NPQ_LOW_TH_V1_8822B)
+#define BIT_CLEAR_NPQ_LOW_TH_V1_8822B(x) ((x) & (~BITS_NPQ_LOW_TH_V1_8822B))
+#define BIT_GET_NPQ_LOW_TH_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_NPQ_LOW_TH_V1_8822B) & BIT_MASK_NPQ_LOW_TH_V1_8822B)
+#define BIT_SET_NPQ_LOW_TH_V1_8822B(x, v) \
+ (BIT_CLEAR_NPQ_LOW_TH_V1_8822B(x) | BIT_NPQ_LOW_TH_V1_8822B(v))
/* 2 REG_TQPNT3_8822B */
#define BIT_SHIFT_LPQ_HIGH_TH_V1_8822B 16
#define BIT_MASK_LPQ_HIGH_TH_V1_8822B 0xfff
-#define BIT_LPQ_HIGH_TH_V1_8822B(x) (((x) & BIT_MASK_LPQ_HIGH_TH_V1_8822B) << BIT_SHIFT_LPQ_HIGH_TH_V1_8822B)
-#define BIT_GET_LPQ_HIGH_TH_V1_8822B(x) (((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1_8822B) & BIT_MASK_LPQ_HIGH_TH_V1_8822B)
-
+#define BIT_LPQ_HIGH_TH_V1_8822B(x) \
+ (((x) & BIT_MASK_LPQ_HIGH_TH_V1_8822B) \
+ << BIT_SHIFT_LPQ_HIGH_TH_V1_8822B)
+#define BITS_LPQ_HIGH_TH_V1_8822B \
+ (BIT_MASK_LPQ_HIGH_TH_V1_8822B << BIT_SHIFT_LPQ_HIGH_TH_V1_8822B)
+#define BIT_CLEAR_LPQ_HIGH_TH_V1_8822B(x) ((x) & (~BITS_LPQ_HIGH_TH_V1_8822B))
+#define BIT_GET_LPQ_HIGH_TH_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1_8822B) & \
+ BIT_MASK_LPQ_HIGH_TH_V1_8822B)
+#define BIT_SET_LPQ_HIGH_TH_V1_8822B(x, v) \
+ (BIT_CLEAR_LPQ_HIGH_TH_V1_8822B(x) | BIT_LPQ_HIGH_TH_V1_8822B(v))
#define BIT_SHIFT_LPQ_LOW_TH_V1_8822B 0
#define BIT_MASK_LPQ_LOW_TH_V1_8822B 0xfff
-#define BIT_LPQ_LOW_TH_V1_8822B(x) (((x) & BIT_MASK_LPQ_LOW_TH_V1_8822B) << BIT_SHIFT_LPQ_LOW_TH_V1_8822B)
-#define BIT_GET_LPQ_LOW_TH_V1_8822B(x) (((x) >> BIT_SHIFT_LPQ_LOW_TH_V1_8822B) & BIT_MASK_LPQ_LOW_TH_V1_8822B)
-
+#define BIT_LPQ_LOW_TH_V1_8822B(x) \
+ (((x) & BIT_MASK_LPQ_LOW_TH_V1_8822B) << BIT_SHIFT_LPQ_LOW_TH_V1_8822B)
+#define BITS_LPQ_LOW_TH_V1_8822B \
+ (BIT_MASK_LPQ_LOW_TH_V1_8822B << BIT_SHIFT_LPQ_LOW_TH_V1_8822B)
+#define BIT_CLEAR_LPQ_LOW_TH_V1_8822B(x) ((x) & (~BITS_LPQ_LOW_TH_V1_8822B))
+#define BIT_GET_LPQ_LOW_TH_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_LPQ_LOW_TH_V1_8822B) & BIT_MASK_LPQ_LOW_TH_V1_8822B)
+#define BIT_SET_LPQ_LOW_TH_V1_8822B(x, v) \
+ (BIT_CLEAR_LPQ_LOW_TH_V1_8822B(x) | BIT_LPQ_LOW_TH_V1_8822B(v))
/* 2 REG_TQPNT4_8822B */
#define BIT_SHIFT_EXQ_HIGH_TH_V1_8822B 16
#define BIT_MASK_EXQ_HIGH_TH_V1_8822B 0xfff
-#define BIT_EXQ_HIGH_TH_V1_8822B(x) (((x) & BIT_MASK_EXQ_HIGH_TH_V1_8822B) << BIT_SHIFT_EXQ_HIGH_TH_V1_8822B)
-#define BIT_GET_EXQ_HIGH_TH_V1_8822B(x) (((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1_8822B) & BIT_MASK_EXQ_HIGH_TH_V1_8822B)
-
+#define BIT_EXQ_HIGH_TH_V1_8822B(x) \
+ (((x) & BIT_MASK_EXQ_HIGH_TH_V1_8822B) \
+ << BIT_SHIFT_EXQ_HIGH_TH_V1_8822B)
+#define BITS_EXQ_HIGH_TH_V1_8822B \
+ (BIT_MASK_EXQ_HIGH_TH_V1_8822B << BIT_SHIFT_EXQ_HIGH_TH_V1_8822B)
+#define BIT_CLEAR_EXQ_HIGH_TH_V1_8822B(x) ((x) & (~BITS_EXQ_HIGH_TH_V1_8822B))
+#define BIT_GET_EXQ_HIGH_TH_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1_8822B) & \
+ BIT_MASK_EXQ_HIGH_TH_V1_8822B)
+#define BIT_SET_EXQ_HIGH_TH_V1_8822B(x, v) \
+ (BIT_CLEAR_EXQ_HIGH_TH_V1_8822B(x) | BIT_EXQ_HIGH_TH_V1_8822B(v))
#define BIT_SHIFT_EXQ_LOW_TH_V1_8822B 0
#define BIT_MASK_EXQ_LOW_TH_V1_8822B 0xfff
-#define BIT_EXQ_LOW_TH_V1_8822B(x) (((x) & BIT_MASK_EXQ_LOW_TH_V1_8822B) << BIT_SHIFT_EXQ_LOW_TH_V1_8822B)
-#define BIT_GET_EXQ_LOW_TH_V1_8822B(x) (((x) >> BIT_SHIFT_EXQ_LOW_TH_V1_8822B) & BIT_MASK_EXQ_LOW_TH_V1_8822B)
-
+#define BIT_EXQ_LOW_TH_V1_8822B(x) \
+ (((x) & BIT_MASK_EXQ_LOW_TH_V1_8822B) << BIT_SHIFT_EXQ_LOW_TH_V1_8822B)
+#define BITS_EXQ_LOW_TH_V1_8822B \
+ (BIT_MASK_EXQ_LOW_TH_V1_8822B << BIT_SHIFT_EXQ_LOW_TH_V1_8822B)
+#define BIT_CLEAR_EXQ_LOW_TH_V1_8822B(x) ((x) & (~BITS_EXQ_LOW_TH_V1_8822B))
+#define BIT_GET_EXQ_LOW_TH_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_EXQ_LOW_TH_V1_8822B) & BIT_MASK_EXQ_LOW_TH_V1_8822B)
+#define BIT_SET_EXQ_LOW_TH_V1_8822B(x, v) \
+ (BIT_CLEAR_EXQ_LOW_TH_V1_8822B(x) | BIT_EXQ_LOW_TH_V1_8822B(v))
/* 2 REG_RQPN_CTRL_1_8822B */
#define BIT_SHIFT_TXPKTNUM_H_8822B 16
#define BIT_MASK_TXPKTNUM_H_8822B 0xffff
-#define BIT_TXPKTNUM_H_8822B(x) (((x) & BIT_MASK_TXPKTNUM_H_8822B) << BIT_SHIFT_TXPKTNUM_H_8822B)
-#define BIT_GET_TXPKTNUM_H_8822B(x) (((x) >> BIT_SHIFT_TXPKTNUM_H_8822B) & BIT_MASK_TXPKTNUM_H_8822B)
-
+#define BIT_TXPKTNUM_H_8822B(x) \
+ (((x) & BIT_MASK_TXPKTNUM_H_8822B) << BIT_SHIFT_TXPKTNUM_H_8822B)
+#define BITS_TXPKTNUM_H_8822B \
+ (BIT_MASK_TXPKTNUM_H_8822B << BIT_SHIFT_TXPKTNUM_H_8822B)
+#define BIT_CLEAR_TXPKTNUM_H_8822B(x) ((x) & (~BITS_TXPKTNUM_H_8822B))
+#define BIT_GET_TXPKTNUM_H_8822B(x) \
+ (((x) >> BIT_SHIFT_TXPKTNUM_H_8822B) & BIT_MASK_TXPKTNUM_H_8822B)
+#define BIT_SET_TXPKTNUM_H_8822B(x, v) \
+ (BIT_CLEAR_TXPKTNUM_H_8822B(x) | BIT_TXPKTNUM_H_8822B(v))
#define BIT_SHIFT_TXPKTNUM_V2_8822B 0
#define BIT_MASK_TXPKTNUM_V2_8822B 0xffff
-#define BIT_TXPKTNUM_V2_8822B(x) (((x) & BIT_MASK_TXPKTNUM_V2_8822B) << BIT_SHIFT_TXPKTNUM_V2_8822B)
-#define BIT_GET_TXPKTNUM_V2_8822B(x) (((x) >> BIT_SHIFT_TXPKTNUM_V2_8822B) & BIT_MASK_TXPKTNUM_V2_8822B)
-
+#define BIT_TXPKTNUM_V2_8822B(x) \
+ (((x) & BIT_MASK_TXPKTNUM_V2_8822B) << BIT_SHIFT_TXPKTNUM_V2_8822B)
+#define BITS_TXPKTNUM_V2_8822B \
+ (BIT_MASK_TXPKTNUM_V2_8822B << BIT_SHIFT_TXPKTNUM_V2_8822B)
+#define BIT_CLEAR_TXPKTNUM_V2_8822B(x) ((x) & (~BITS_TXPKTNUM_V2_8822B))
+#define BIT_GET_TXPKTNUM_V2_8822B(x) \
+ (((x) >> BIT_SHIFT_TXPKTNUM_V2_8822B) & BIT_MASK_TXPKTNUM_V2_8822B)
+#define BIT_SET_TXPKTNUM_V2_8822B(x, v) \
+ (BIT_CLEAR_TXPKTNUM_V2_8822B(x) | BIT_TXPKTNUM_V2_8822B(v))
/* 2 REG_RQPN_CTRL_2_8822B */
#define BIT_LD_RQPN_8822B BIT(31)
@@ -3308,103 +5212,192 @@
#define BIT_SHIFT_HPQ_AVAL_PG_V1_8822B 16
#define BIT_MASK_HPQ_AVAL_PG_V1_8822B 0xfff
-#define BIT_HPQ_AVAL_PG_V1_8822B(x) (((x) & BIT_MASK_HPQ_AVAL_PG_V1_8822B) << BIT_SHIFT_HPQ_AVAL_PG_V1_8822B)
-#define BIT_GET_HPQ_AVAL_PG_V1_8822B(x) (((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1_8822B) & BIT_MASK_HPQ_AVAL_PG_V1_8822B)
-
+#define BIT_HPQ_AVAL_PG_V1_8822B(x) \
+ (((x) & BIT_MASK_HPQ_AVAL_PG_V1_8822B) \
+ << BIT_SHIFT_HPQ_AVAL_PG_V1_8822B)
+#define BITS_HPQ_AVAL_PG_V1_8822B \
+ (BIT_MASK_HPQ_AVAL_PG_V1_8822B << BIT_SHIFT_HPQ_AVAL_PG_V1_8822B)
+#define BIT_CLEAR_HPQ_AVAL_PG_V1_8822B(x) ((x) & (~BITS_HPQ_AVAL_PG_V1_8822B))
+#define BIT_GET_HPQ_AVAL_PG_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1_8822B) & \
+ BIT_MASK_HPQ_AVAL_PG_V1_8822B)
+#define BIT_SET_HPQ_AVAL_PG_V1_8822B(x, v) \
+ (BIT_CLEAR_HPQ_AVAL_PG_V1_8822B(x) | BIT_HPQ_AVAL_PG_V1_8822B(v))
#define BIT_SHIFT_HPQ_V1_8822B 0
#define BIT_MASK_HPQ_V1_8822B 0xfff
-#define BIT_HPQ_V1_8822B(x) (((x) & BIT_MASK_HPQ_V1_8822B) << BIT_SHIFT_HPQ_V1_8822B)
-#define BIT_GET_HPQ_V1_8822B(x) (((x) >> BIT_SHIFT_HPQ_V1_8822B) & BIT_MASK_HPQ_V1_8822B)
-
+#define BIT_HPQ_V1_8822B(x) \
+ (((x) & BIT_MASK_HPQ_V1_8822B) << BIT_SHIFT_HPQ_V1_8822B)
+#define BITS_HPQ_V1_8822B (BIT_MASK_HPQ_V1_8822B << BIT_SHIFT_HPQ_V1_8822B)
+#define BIT_CLEAR_HPQ_V1_8822B(x) ((x) & (~BITS_HPQ_V1_8822B))
+#define BIT_GET_HPQ_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_HPQ_V1_8822B) & BIT_MASK_HPQ_V1_8822B)
+#define BIT_SET_HPQ_V1_8822B(x, v) \
+ (BIT_CLEAR_HPQ_V1_8822B(x) | BIT_HPQ_V1_8822B(v))
/* 2 REG_FIFOPAGE_INFO_2_8822B */
#define BIT_SHIFT_LPQ_AVAL_PG_V1_8822B 16
#define BIT_MASK_LPQ_AVAL_PG_V1_8822B 0xfff
-#define BIT_LPQ_AVAL_PG_V1_8822B(x) (((x) & BIT_MASK_LPQ_AVAL_PG_V1_8822B) << BIT_SHIFT_LPQ_AVAL_PG_V1_8822B)
-#define BIT_GET_LPQ_AVAL_PG_V1_8822B(x) (((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1_8822B) & BIT_MASK_LPQ_AVAL_PG_V1_8822B)
-
+#define BIT_LPQ_AVAL_PG_V1_8822B(x) \
+ (((x) & BIT_MASK_LPQ_AVAL_PG_V1_8822B) \
+ << BIT_SHIFT_LPQ_AVAL_PG_V1_8822B)
+#define BITS_LPQ_AVAL_PG_V1_8822B \
+ (BIT_MASK_LPQ_AVAL_PG_V1_8822B << BIT_SHIFT_LPQ_AVAL_PG_V1_8822B)
+#define BIT_CLEAR_LPQ_AVAL_PG_V1_8822B(x) ((x) & (~BITS_LPQ_AVAL_PG_V1_8822B))
+#define BIT_GET_LPQ_AVAL_PG_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1_8822B) & \
+ BIT_MASK_LPQ_AVAL_PG_V1_8822B)
+#define BIT_SET_LPQ_AVAL_PG_V1_8822B(x, v) \
+ (BIT_CLEAR_LPQ_AVAL_PG_V1_8822B(x) | BIT_LPQ_AVAL_PG_V1_8822B(v))
#define BIT_SHIFT_LPQ_V1_8822B 0
#define BIT_MASK_LPQ_V1_8822B 0xfff
-#define BIT_LPQ_V1_8822B(x) (((x) & BIT_MASK_LPQ_V1_8822B) << BIT_SHIFT_LPQ_V1_8822B)
-#define BIT_GET_LPQ_V1_8822B(x) (((x) >> BIT_SHIFT_LPQ_V1_8822B) & BIT_MASK_LPQ_V1_8822B)
-
+#define BIT_LPQ_V1_8822B(x) \
+ (((x) & BIT_MASK_LPQ_V1_8822B) << BIT_SHIFT_LPQ_V1_8822B)
+#define BITS_LPQ_V1_8822B (BIT_MASK_LPQ_V1_8822B << BIT_SHIFT_LPQ_V1_8822B)
+#define BIT_CLEAR_LPQ_V1_8822B(x) ((x) & (~BITS_LPQ_V1_8822B))
+#define BIT_GET_LPQ_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_LPQ_V1_8822B) & BIT_MASK_LPQ_V1_8822B)
+#define BIT_SET_LPQ_V1_8822B(x, v) \
+ (BIT_CLEAR_LPQ_V1_8822B(x) | BIT_LPQ_V1_8822B(v))
/* 2 REG_FIFOPAGE_INFO_3_8822B */
#define BIT_SHIFT_NPQ_AVAL_PG_V1_8822B 16
#define BIT_MASK_NPQ_AVAL_PG_V1_8822B 0xfff
-#define BIT_NPQ_AVAL_PG_V1_8822B(x) (((x) & BIT_MASK_NPQ_AVAL_PG_V1_8822B) << BIT_SHIFT_NPQ_AVAL_PG_V1_8822B)
-#define BIT_GET_NPQ_AVAL_PG_V1_8822B(x) (((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1_8822B) & BIT_MASK_NPQ_AVAL_PG_V1_8822B)
-
+#define BIT_NPQ_AVAL_PG_V1_8822B(x) \
+ (((x) & BIT_MASK_NPQ_AVAL_PG_V1_8822B) \
+ << BIT_SHIFT_NPQ_AVAL_PG_V1_8822B)
+#define BITS_NPQ_AVAL_PG_V1_8822B \
+ (BIT_MASK_NPQ_AVAL_PG_V1_8822B << BIT_SHIFT_NPQ_AVAL_PG_V1_8822B)
+#define BIT_CLEAR_NPQ_AVAL_PG_V1_8822B(x) ((x) & (~BITS_NPQ_AVAL_PG_V1_8822B))
+#define BIT_GET_NPQ_AVAL_PG_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1_8822B) & \
+ BIT_MASK_NPQ_AVAL_PG_V1_8822B)
+#define BIT_SET_NPQ_AVAL_PG_V1_8822B(x, v) \
+ (BIT_CLEAR_NPQ_AVAL_PG_V1_8822B(x) | BIT_NPQ_AVAL_PG_V1_8822B(v))
#define BIT_SHIFT_NPQ_V1_8822B 0
#define BIT_MASK_NPQ_V1_8822B 0xfff
-#define BIT_NPQ_V1_8822B(x) (((x) & BIT_MASK_NPQ_V1_8822B) << BIT_SHIFT_NPQ_V1_8822B)
-#define BIT_GET_NPQ_V1_8822B(x) (((x) >> BIT_SHIFT_NPQ_V1_8822B) & BIT_MASK_NPQ_V1_8822B)
-
+#define BIT_NPQ_V1_8822B(x) \
+ (((x) & BIT_MASK_NPQ_V1_8822B) << BIT_SHIFT_NPQ_V1_8822B)
+#define BITS_NPQ_V1_8822B (BIT_MASK_NPQ_V1_8822B << BIT_SHIFT_NPQ_V1_8822B)
+#define BIT_CLEAR_NPQ_V1_8822B(x) ((x) & (~BITS_NPQ_V1_8822B))
+#define BIT_GET_NPQ_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_NPQ_V1_8822B) & BIT_MASK_NPQ_V1_8822B)
+#define BIT_SET_NPQ_V1_8822B(x, v) \
+ (BIT_CLEAR_NPQ_V1_8822B(x) | BIT_NPQ_V1_8822B(v))
/* 2 REG_FIFOPAGE_INFO_4_8822B */
#define BIT_SHIFT_EXQ_AVAL_PG_V1_8822B 16
#define BIT_MASK_EXQ_AVAL_PG_V1_8822B 0xfff
-#define BIT_EXQ_AVAL_PG_V1_8822B(x) (((x) & BIT_MASK_EXQ_AVAL_PG_V1_8822B) << BIT_SHIFT_EXQ_AVAL_PG_V1_8822B)
-#define BIT_GET_EXQ_AVAL_PG_V1_8822B(x) (((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1_8822B) & BIT_MASK_EXQ_AVAL_PG_V1_8822B)
-
+#define BIT_EXQ_AVAL_PG_V1_8822B(x) \
+ (((x) & BIT_MASK_EXQ_AVAL_PG_V1_8822B) \
+ << BIT_SHIFT_EXQ_AVAL_PG_V1_8822B)
+#define BITS_EXQ_AVAL_PG_V1_8822B \
+ (BIT_MASK_EXQ_AVAL_PG_V1_8822B << BIT_SHIFT_EXQ_AVAL_PG_V1_8822B)
+#define BIT_CLEAR_EXQ_AVAL_PG_V1_8822B(x) ((x) & (~BITS_EXQ_AVAL_PG_V1_8822B))
+#define BIT_GET_EXQ_AVAL_PG_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1_8822B) & \
+ BIT_MASK_EXQ_AVAL_PG_V1_8822B)
+#define BIT_SET_EXQ_AVAL_PG_V1_8822B(x, v) \
+ (BIT_CLEAR_EXQ_AVAL_PG_V1_8822B(x) | BIT_EXQ_AVAL_PG_V1_8822B(v))
#define BIT_SHIFT_EXQ_V1_8822B 0
#define BIT_MASK_EXQ_V1_8822B 0xfff
-#define BIT_EXQ_V1_8822B(x) (((x) & BIT_MASK_EXQ_V1_8822B) << BIT_SHIFT_EXQ_V1_8822B)
-#define BIT_GET_EXQ_V1_8822B(x) (((x) >> BIT_SHIFT_EXQ_V1_8822B) & BIT_MASK_EXQ_V1_8822B)
-
+#define BIT_EXQ_V1_8822B(x) \
+ (((x) & BIT_MASK_EXQ_V1_8822B) << BIT_SHIFT_EXQ_V1_8822B)
+#define BITS_EXQ_V1_8822B (BIT_MASK_EXQ_V1_8822B << BIT_SHIFT_EXQ_V1_8822B)
+#define BIT_CLEAR_EXQ_V1_8822B(x) ((x) & (~BITS_EXQ_V1_8822B))
+#define BIT_GET_EXQ_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_EXQ_V1_8822B) & BIT_MASK_EXQ_V1_8822B)
+#define BIT_SET_EXQ_V1_8822B(x, v) \
+ (BIT_CLEAR_EXQ_V1_8822B(x) | BIT_EXQ_V1_8822B(v))
/* 2 REG_FIFOPAGE_INFO_5_8822B */
#define BIT_SHIFT_PUBQ_AVAL_PG_V1_8822B 16
#define BIT_MASK_PUBQ_AVAL_PG_V1_8822B 0xfff
-#define BIT_PUBQ_AVAL_PG_V1_8822B(x) (((x) & BIT_MASK_PUBQ_AVAL_PG_V1_8822B) << BIT_SHIFT_PUBQ_AVAL_PG_V1_8822B)
-#define BIT_GET_PUBQ_AVAL_PG_V1_8822B(x) (((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1_8822B) & BIT_MASK_PUBQ_AVAL_PG_V1_8822B)
-
+#define BIT_PUBQ_AVAL_PG_V1_8822B(x) \
+ (((x) & BIT_MASK_PUBQ_AVAL_PG_V1_8822B) \
+ << BIT_SHIFT_PUBQ_AVAL_PG_V1_8822B)
+#define BITS_PUBQ_AVAL_PG_V1_8822B \
+ (BIT_MASK_PUBQ_AVAL_PG_V1_8822B << BIT_SHIFT_PUBQ_AVAL_PG_V1_8822B)
+#define BIT_CLEAR_PUBQ_AVAL_PG_V1_8822B(x) ((x) & (~BITS_PUBQ_AVAL_PG_V1_8822B))
+#define BIT_GET_PUBQ_AVAL_PG_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1_8822B) & \
+ BIT_MASK_PUBQ_AVAL_PG_V1_8822B)
+#define BIT_SET_PUBQ_AVAL_PG_V1_8822B(x, v) \
+ (BIT_CLEAR_PUBQ_AVAL_PG_V1_8822B(x) | BIT_PUBQ_AVAL_PG_V1_8822B(v))
#define BIT_SHIFT_PUBQ_V1_8822B 0
#define BIT_MASK_PUBQ_V1_8822B 0xfff
-#define BIT_PUBQ_V1_8822B(x) (((x) & BIT_MASK_PUBQ_V1_8822B) << BIT_SHIFT_PUBQ_V1_8822B)
-#define BIT_GET_PUBQ_V1_8822B(x) (((x) >> BIT_SHIFT_PUBQ_V1_8822B) & BIT_MASK_PUBQ_V1_8822B)
-
+#define BIT_PUBQ_V1_8822B(x) \
+ (((x) & BIT_MASK_PUBQ_V1_8822B) << BIT_SHIFT_PUBQ_V1_8822B)
+#define BITS_PUBQ_V1_8822B (BIT_MASK_PUBQ_V1_8822B << BIT_SHIFT_PUBQ_V1_8822B)
+#define BIT_CLEAR_PUBQ_V1_8822B(x) ((x) & (~BITS_PUBQ_V1_8822B))
+#define BIT_GET_PUBQ_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_PUBQ_V1_8822B) & BIT_MASK_PUBQ_V1_8822B)
+#define BIT_SET_PUBQ_V1_8822B(x, v) \
+ (BIT_CLEAR_PUBQ_V1_8822B(x) | BIT_PUBQ_V1_8822B(v))
/* 2 REG_H2C_HEAD_8822B */
#define BIT_SHIFT_H2C_HEAD_8822B 0
#define BIT_MASK_H2C_HEAD_8822B 0x3ffff
-#define BIT_H2C_HEAD_8822B(x) (((x) & BIT_MASK_H2C_HEAD_8822B) << BIT_SHIFT_H2C_HEAD_8822B)
-#define BIT_GET_H2C_HEAD_8822B(x) (((x) >> BIT_SHIFT_H2C_HEAD_8822B) & BIT_MASK_H2C_HEAD_8822B)
-
+#define BIT_H2C_HEAD_8822B(x) \
+ (((x) & BIT_MASK_H2C_HEAD_8822B) << BIT_SHIFT_H2C_HEAD_8822B)
+#define BITS_H2C_HEAD_8822B \
+ (BIT_MASK_H2C_HEAD_8822B << BIT_SHIFT_H2C_HEAD_8822B)
+#define BIT_CLEAR_H2C_HEAD_8822B(x) ((x) & (~BITS_H2C_HEAD_8822B))
+#define BIT_GET_H2C_HEAD_8822B(x) \
+ (((x) >> BIT_SHIFT_H2C_HEAD_8822B) & BIT_MASK_H2C_HEAD_8822B)
+#define BIT_SET_H2C_HEAD_8822B(x, v) \
+ (BIT_CLEAR_H2C_HEAD_8822B(x) | BIT_H2C_HEAD_8822B(v))
/* 2 REG_H2C_TAIL_8822B */
#define BIT_SHIFT_H2C_TAIL_8822B 0
#define BIT_MASK_H2C_TAIL_8822B 0x3ffff
-#define BIT_H2C_TAIL_8822B(x) (((x) & BIT_MASK_H2C_TAIL_8822B) << BIT_SHIFT_H2C_TAIL_8822B)
-#define BIT_GET_H2C_TAIL_8822B(x) (((x) >> BIT_SHIFT_H2C_TAIL_8822B) & BIT_MASK_H2C_TAIL_8822B)
-
+#define BIT_H2C_TAIL_8822B(x) \
+ (((x) & BIT_MASK_H2C_TAIL_8822B) << BIT_SHIFT_H2C_TAIL_8822B)
+#define BITS_H2C_TAIL_8822B \
+ (BIT_MASK_H2C_TAIL_8822B << BIT_SHIFT_H2C_TAIL_8822B)
+#define BIT_CLEAR_H2C_TAIL_8822B(x) ((x) & (~BITS_H2C_TAIL_8822B))
+#define BIT_GET_H2C_TAIL_8822B(x) \
+ (((x) >> BIT_SHIFT_H2C_TAIL_8822B) & BIT_MASK_H2C_TAIL_8822B)
+#define BIT_SET_H2C_TAIL_8822B(x, v) \
+ (BIT_CLEAR_H2C_TAIL_8822B(x) | BIT_H2C_TAIL_8822B(v))
/* 2 REG_H2C_READ_ADDR_8822B */
#define BIT_SHIFT_H2C_READ_ADDR_8822B 0
#define BIT_MASK_H2C_READ_ADDR_8822B 0x3ffff
-#define BIT_H2C_READ_ADDR_8822B(x) (((x) & BIT_MASK_H2C_READ_ADDR_8822B) << BIT_SHIFT_H2C_READ_ADDR_8822B)
-#define BIT_GET_H2C_READ_ADDR_8822B(x) (((x) >> BIT_SHIFT_H2C_READ_ADDR_8822B) & BIT_MASK_H2C_READ_ADDR_8822B)
-
+#define BIT_H2C_READ_ADDR_8822B(x) \
+ (((x) & BIT_MASK_H2C_READ_ADDR_8822B) << BIT_SHIFT_H2C_READ_ADDR_8822B)
+#define BITS_H2C_READ_ADDR_8822B \
+ (BIT_MASK_H2C_READ_ADDR_8822B << BIT_SHIFT_H2C_READ_ADDR_8822B)
+#define BIT_CLEAR_H2C_READ_ADDR_8822B(x) ((x) & (~BITS_H2C_READ_ADDR_8822B))
+#define BIT_GET_H2C_READ_ADDR_8822B(x) \
+ (((x) >> BIT_SHIFT_H2C_READ_ADDR_8822B) & BIT_MASK_H2C_READ_ADDR_8822B)
+#define BIT_SET_H2C_READ_ADDR_8822B(x, v) \
+ (BIT_CLEAR_H2C_READ_ADDR_8822B(x) | BIT_H2C_READ_ADDR_8822B(v))
/* 2 REG_H2C_WR_ADDR_8822B */
#define BIT_SHIFT_H2C_WR_ADDR_8822B 0
#define BIT_MASK_H2C_WR_ADDR_8822B 0x3ffff
-#define BIT_H2C_WR_ADDR_8822B(x) (((x) & BIT_MASK_H2C_WR_ADDR_8822B) << BIT_SHIFT_H2C_WR_ADDR_8822B)
-#define BIT_GET_H2C_WR_ADDR_8822B(x) (((x) >> BIT_SHIFT_H2C_WR_ADDR_8822B) & BIT_MASK_H2C_WR_ADDR_8822B)
-
+#define BIT_H2C_WR_ADDR_8822B(x) \
+ (((x) & BIT_MASK_H2C_WR_ADDR_8822B) << BIT_SHIFT_H2C_WR_ADDR_8822B)
+#define BITS_H2C_WR_ADDR_8822B \
+ (BIT_MASK_H2C_WR_ADDR_8822B << BIT_SHIFT_H2C_WR_ADDR_8822B)
+#define BIT_CLEAR_H2C_WR_ADDR_8822B(x) ((x) & (~BITS_H2C_WR_ADDR_8822B))
+#define BIT_GET_H2C_WR_ADDR_8822B(x) \
+ (((x) >> BIT_SHIFT_H2C_WR_ADDR_8822B) & BIT_MASK_H2C_WR_ADDR_8822B)
+#define BIT_SET_H2C_WR_ADDR_8822B(x, v) \
+ (BIT_CLEAR_H2C_WR_ADDR_8822B(x) | BIT_H2C_WR_ADDR_8822B(v))
/* 2 REG_H2C_INFO_8822B */
#define BIT_H2C_SPACE_VLD_8822B BIT(3)
@@ -3412,48 +5405,90 @@
#define BIT_SHIFT_H2C_LEN_SEL_8822B 0
#define BIT_MASK_H2C_LEN_SEL_8822B 0x3
-#define BIT_H2C_LEN_SEL_8822B(x) (((x) & BIT_MASK_H2C_LEN_SEL_8822B) << BIT_SHIFT_H2C_LEN_SEL_8822B)
-#define BIT_GET_H2C_LEN_SEL_8822B(x) (((x) >> BIT_SHIFT_H2C_LEN_SEL_8822B) & BIT_MASK_H2C_LEN_SEL_8822B)
-
+#define BIT_H2C_LEN_SEL_8822B(x) \
+ (((x) & BIT_MASK_H2C_LEN_SEL_8822B) << BIT_SHIFT_H2C_LEN_SEL_8822B)
+#define BITS_H2C_LEN_SEL_8822B \
+ (BIT_MASK_H2C_LEN_SEL_8822B << BIT_SHIFT_H2C_LEN_SEL_8822B)
+#define BIT_CLEAR_H2C_LEN_SEL_8822B(x) ((x) & (~BITS_H2C_LEN_SEL_8822B))
+#define BIT_GET_H2C_LEN_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_H2C_LEN_SEL_8822B) & BIT_MASK_H2C_LEN_SEL_8822B)
+#define BIT_SET_H2C_LEN_SEL_8822B(x, v) \
+ (BIT_CLEAR_H2C_LEN_SEL_8822B(x) | BIT_H2C_LEN_SEL_8822B(v))
/* 2 REG_RXDMA_AGG_PG_TH_8822B */
-
-#define BIT_SHIFT_RXDMA_AGG_OLD_MOD_8822B 24
-#define BIT_MASK_RXDMA_AGG_OLD_MOD_8822B 0xff
-#define BIT_RXDMA_AGG_OLD_MOD_8822B(x) (((x) & BIT_MASK_RXDMA_AGG_OLD_MOD_8822B) << BIT_SHIFT_RXDMA_AGG_OLD_MOD_8822B)
-#define BIT_GET_RXDMA_AGG_OLD_MOD_8822B(x) (((x) >> BIT_SHIFT_RXDMA_AGG_OLD_MOD_8822B) & BIT_MASK_RXDMA_AGG_OLD_MOD_8822B)
-
+#define BIT_USB_RXDMA_AGG_EN_8822B BIT(31)
+#define BIT_EN_PRE_CALC_8822B BIT(29)
+#define BIT_RXAGG_SW_EN_8822B BIT(28)
+#define BIT_RXAGG_SW_TRIG_8822B BIT(27)
#define BIT_SHIFT_PKT_NUM_WOL_8822B 16
#define BIT_MASK_PKT_NUM_WOL_8822B 0xff
-#define BIT_PKT_NUM_WOL_8822B(x) (((x) & BIT_MASK_PKT_NUM_WOL_8822B) << BIT_SHIFT_PKT_NUM_WOL_8822B)
-#define BIT_GET_PKT_NUM_WOL_8822B(x) (((x) >> BIT_SHIFT_PKT_NUM_WOL_8822B) & BIT_MASK_PKT_NUM_WOL_8822B)
-
-
-#define BIT_SHIFT_DMA_AGG_TO_8822B 8
-#define BIT_MASK_DMA_AGG_TO_8822B 0xf
-#define BIT_DMA_AGG_TO_8822B(x) (((x) & BIT_MASK_DMA_AGG_TO_8822B) << BIT_SHIFT_DMA_AGG_TO_8822B)
-#define BIT_GET_DMA_AGG_TO_8822B(x) (((x) >> BIT_SHIFT_DMA_AGG_TO_8822B) & BIT_MASK_DMA_AGG_TO_8822B)
-
-
-#define BIT_SHIFT_RXDMA_AGG_PG_TH_V1_8822B 0
-#define BIT_MASK_RXDMA_AGG_PG_TH_V1_8822B 0xf
-#define BIT_RXDMA_AGG_PG_TH_V1_8822B(x) (((x) & BIT_MASK_RXDMA_AGG_PG_TH_V1_8822B) << BIT_SHIFT_RXDMA_AGG_PG_TH_V1_8822B)
-#define BIT_GET_RXDMA_AGG_PG_TH_V1_8822B(x) (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_V1_8822B) & BIT_MASK_RXDMA_AGG_PG_TH_V1_8822B)
-
+#define BIT_PKT_NUM_WOL_8822B(x) \
+ (((x) & BIT_MASK_PKT_NUM_WOL_8822B) << BIT_SHIFT_PKT_NUM_WOL_8822B)
+#define BITS_PKT_NUM_WOL_8822B \
+ (BIT_MASK_PKT_NUM_WOL_8822B << BIT_SHIFT_PKT_NUM_WOL_8822B)
+#define BIT_CLEAR_PKT_NUM_WOL_8822B(x) ((x) & (~BITS_PKT_NUM_WOL_8822B))
+#define BIT_GET_PKT_NUM_WOL_8822B(x) \
+ (((x) >> BIT_SHIFT_PKT_NUM_WOL_8822B) & BIT_MASK_PKT_NUM_WOL_8822B)
+#define BIT_SET_PKT_NUM_WOL_8822B(x, v) \
+ (BIT_CLEAR_PKT_NUM_WOL_8822B(x) | BIT_PKT_NUM_WOL_8822B(v))
+
+#define BIT_SHIFT_DMA_AGG_TO_V1_8822B 8
+#define BIT_MASK_DMA_AGG_TO_V1_8822B 0xff
+#define BIT_DMA_AGG_TO_V1_8822B(x) \
+ (((x) & BIT_MASK_DMA_AGG_TO_V1_8822B) << BIT_SHIFT_DMA_AGG_TO_V1_8822B)
+#define BITS_DMA_AGG_TO_V1_8822B \
+ (BIT_MASK_DMA_AGG_TO_V1_8822B << BIT_SHIFT_DMA_AGG_TO_V1_8822B)
+#define BIT_CLEAR_DMA_AGG_TO_V1_8822B(x) ((x) & (~BITS_DMA_AGG_TO_V1_8822B))
+#define BIT_GET_DMA_AGG_TO_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_DMA_AGG_TO_V1_8822B) & BIT_MASK_DMA_AGG_TO_V1_8822B)
+#define BIT_SET_DMA_AGG_TO_V1_8822B(x, v) \
+ (BIT_CLEAR_DMA_AGG_TO_V1_8822B(x) | BIT_DMA_AGG_TO_V1_8822B(v))
+
+#define BIT_SHIFT_RXDMA_AGG_PG_TH_8822B 0
+#define BIT_MASK_RXDMA_AGG_PG_TH_8822B 0xff
+#define BIT_RXDMA_AGG_PG_TH_8822B(x) \
+ (((x) & BIT_MASK_RXDMA_AGG_PG_TH_8822B) \
+ << BIT_SHIFT_RXDMA_AGG_PG_TH_8822B)
+#define BITS_RXDMA_AGG_PG_TH_8822B \
+ (BIT_MASK_RXDMA_AGG_PG_TH_8822B << BIT_SHIFT_RXDMA_AGG_PG_TH_8822B)
+#define BIT_CLEAR_RXDMA_AGG_PG_TH_8822B(x) ((x) & (~BITS_RXDMA_AGG_PG_TH_8822B))
+#define BIT_GET_RXDMA_AGG_PG_TH_8822B(x) \
+ (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_8822B) & \
+ BIT_MASK_RXDMA_AGG_PG_TH_8822B)
+#define BIT_SET_RXDMA_AGG_PG_TH_8822B(x, v) \
+ (BIT_CLEAR_RXDMA_AGG_PG_TH_8822B(x) | BIT_RXDMA_AGG_PG_TH_8822B(v))
/* 2 REG_RXPKT_NUM_8822B */
#define BIT_SHIFT_RXPKT_NUM_8822B 24
#define BIT_MASK_RXPKT_NUM_8822B 0xff
-#define BIT_RXPKT_NUM_8822B(x) (((x) & BIT_MASK_RXPKT_NUM_8822B) << BIT_SHIFT_RXPKT_NUM_8822B)
-#define BIT_GET_RXPKT_NUM_8822B(x) (((x) >> BIT_SHIFT_RXPKT_NUM_8822B) & BIT_MASK_RXPKT_NUM_8822B)
-
+#define BIT_RXPKT_NUM_8822B(x) \
+ (((x) & BIT_MASK_RXPKT_NUM_8822B) << BIT_SHIFT_RXPKT_NUM_8822B)
+#define BITS_RXPKT_NUM_8822B \
+ (BIT_MASK_RXPKT_NUM_8822B << BIT_SHIFT_RXPKT_NUM_8822B)
+#define BIT_CLEAR_RXPKT_NUM_8822B(x) ((x) & (~BITS_RXPKT_NUM_8822B))
+#define BIT_GET_RXPKT_NUM_8822B(x) \
+ (((x) >> BIT_SHIFT_RXPKT_NUM_8822B) & BIT_MASK_RXPKT_NUM_8822B)
+#define BIT_SET_RXPKT_NUM_8822B(x, v) \
+ (BIT_CLEAR_RXPKT_NUM_8822B(x) | BIT_RXPKT_NUM_8822B(v))
#define BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822B 20
#define BIT_MASK_FW_UPD_RDPTR19_TO_16_8822B 0xf
-#define BIT_FW_UPD_RDPTR19_TO_16_8822B(x) (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8822B) << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822B)
-#define BIT_GET_FW_UPD_RDPTR19_TO_16_8822B(x) (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822B) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8822B)
+#define BIT_FW_UPD_RDPTR19_TO_16_8822B(x) \
+ (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8822B) \
+ << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822B)
+#define BITS_FW_UPD_RDPTR19_TO_16_8822B \
+ (BIT_MASK_FW_UPD_RDPTR19_TO_16_8822B \
+ << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822B)
+#define BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8822B(x) \
+ ((x) & (~BITS_FW_UPD_RDPTR19_TO_16_8822B))
+#define BIT_GET_FW_UPD_RDPTR19_TO_16_8822B(x) \
+ (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822B) & \
+ BIT_MASK_FW_UPD_RDPTR19_TO_16_8822B)
+#define BIT_SET_FW_UPD_RDPTR19_TO_16_8822B(x, v) \
+ (BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8822B(x) | \
+ BIT_FW_UPD_RDPTR19_TO_16_8822B(v))
#define BIT_RXDMA_REQ_8822B BIT(19)
#define BIT_RW_RELEASE_EN_8822B BIT(18)
@@ -3462,9 +5497,15 @@
#define BIT_SHIFT_FW_UPD_RDPTR_8822B 0
#define BIT_MASK_FW_UPD_RDPTR_8822B 0xffff
-#define BIT_FW_UPD_RDPTR_8822B(x) (((x) & BIT_MASK_FW_UPD_RDPTR_8822B) << BIT_SHIFT_FW_UPD_RDPTR_8822B)
-#define BIT_GET_FW_UPD_RDPTR_8822B(x) (((x) >> BIT_SHIFT_FW_UPD_RDPTR_8822B) & BIT_MASK_FW_UPD_RDPTR_8822B)
-
+#define BIT_FW_UPD_RDPTR_8822B(x) \
+ (((x) & BIT_MASK_FW_UPD_RDPTR_8822B) << BIT_SHIFT_FW_UPD_RDPTR_8822B)
+#define BITS_FW_UPD_RDPTR_8822B \
+ (BIT_MASK_FW_UPD_RDPTR_8822B << BIT_SHIFT_FW_UPD_RDPTR_8822B)
+#define BIT_CLEAR_FW_UPD_RDPTR_8822B(x) ((x) & (~BITS_FW_UPD_RDPTR_8822B))
+#define BIT_GET_FW_UPD_RDPTR_8822B(x) \
+ (((x) >> BIT_SHIFT_FW_UPD_RDPTR_8822B) & BIT_MASK_FW_UPD_RDPTR_8822B)
+#define BIT_SET_FW_UPD_RDPTR_8822B(x, v) \
+ (BIT_CLEAR_FW_UPD_RDPTR_8822B(x) | BIT_FW_UPD_RDPTR_8822B(v))
/* 2 REG_RXDMA_STATUS_8822B */
#define BIT_C2H_PKT_OVF_8822B BIT(7)
@@ -3479,24 +5520,43 @@
#define BIT_SHIFT_RDE_DEBUG_8822B 0
#define BIT_MASK_RDE_DEBUG_8822B 0xffffffffL
-#define BIT_RDE_DEBUG_8822B(x) (((x) & BIT_MASK_RDE_DEBUG_8822B) << BIT_SHIFT_RDE_DEBUG_8822B)
-#define BIT_GET_RDE_DEBUG_8822B(x) (((x) >> BIT_SHIFT_RDE_DEBUG_8822B) & BIT_MASK_RDE_DEBUG_8822B)
-
+#define BIT_RDE_DEBUG_8822B(x) \
+ (((x) & BIT_MASK_RDE_DEBUG_8822B) << BIT_SHIFT_RDE_DEBUG_8822B)
+#define BITS_RDE_DEBUG_8822B \
+ (BIT_MASK_RDE_DEBUG_8822B << BIT_SHIFT_RDE_DEBUG_8822B)
+#define BIT_CLEAR_RDE_DEBUG_8822B(x) ((x) & (~BITS_RDE_DEBUG_8822B))
+#define BIT_GET_RDE_DEBUG_8822B(x) \
+ (((x) >> BIT_SHIFT_RDE_DEBUG_8822B) & BIT_MASK_RDE_DEBUG_8822B)
+#define BIT_SET_RDE_DEBUG_8822B(x, v) \
+ (BIT_CLEAR_RDE_DEBUG_8822B(x) | BIT_RDE_DEBUG_8822B(v))
/* 2 REG_RXDMA_MODE_8822B */
#define BIT_SHIFT_PKTNUM_TH_V2_8822B 24
#define BIT_MASK_PKTNUM_TH_V2_8822B 0x1f
-#define BIT_PKTNUM_TH_V2_8822B(x) (((x) & BIT_MASK_PKTNUM_TH_V2_8822B) << BIT_SHIFT_PKTNUM_TH_V2_8822B)
-#define BIT_GET_PKTNUM_TH_V2_8822B(x) (((x) >> BIT_SHIFT_PKTNUM_TH_V2_8822B) & BIT_MASK_PKTNUM_TH_V2_8822B)
+#define BIT_PKTNUM_TH_V2_8822B(x) \
+ (((x) & BIT_MASK_PKTNUM_TH_V2_8822B) << BIT_SHIFT_PKTNUM_TH_V2_8822B)
+#define BITS_PKTNUM_TH_V2_8822B \
+ (BIT_MASK_PKTNUM_TH_V2_8822B << BIT_SHIFT_PKTNUM_TH_V2_8822B)
+#define BIT_CLEAR_PKTNUM_TH_V2_8822B(x) ((x) & (~BITS_PKTNUM_TH_V2_8822B))
+#define BIT_GET_PKTNUM_TH_V2_8822B(x) \
+ (((x) >> BIT_SHIFT_PKTNUM_TH_V2_8822B) & BIT_MASK_PKTNUM_TH_V2_8822B)
+#define BIT_SET_PKTNUM_TH_V2_8822B(x, v) \
+ (BIT_CLEAR_PKTNUM_TH_V2_8822B(x) | BIT_PKTNUM_TH_V2_8822B(v))
#define BIT_TXBA_BREAK_USBAGG_8822B BIT(23)
#define BIT_SHIFT_PKTLEN_PARA_8822B 16
#define BIT_MASK_PKTLEN_PARA_8822B 0x7
-#define BIT_PKTLEN_PARA_8822B(x) (((x) & BIT_MASK_PKTLEN_PARA_8822B) << BIT_SHIFT_PKTLEN_PARA_8822B)
-#define BIT_GET_PKTLEN_PARA_8822B(x) (((x) >> BIT_SHIFT_PKTLEN_PARA_8822B) & BIT_MASK_PKTLEN_PARA_8822B)
-
+#define BIT_PKTLEN_PARA_8822B(x) \
+ (((x) & BIT_MASK_PKTLEN_PARA_8822B) << BIT_SHIFT_PKTLEN_PARA_8822B)
+#define BITS_PKTLEN_PARA_8822B \
+ (BIT_MASK_PKTLEN_PARA_8822B << BIT_SHIFT_PKTLEN_PARA_8822B)
+#define BIT_CLEAR_PKTLEN_PARA_8822B(x) ((x) & (~BITS_PKTLEN_PARA_8822B))
+#define BIT_GET_PKTLEN_PARA_8822B(x) \
+ (((x) >> BIT_SHIFT_PKTLEN_PARA_8822B) & BIT_MASK_PKTLEN_PARA_8822B)
+#define BIT_SET_PKTLEN_PARA_8822B(x, v) \
+ (BIT_CLEAR_PKTLEN_PARA_8822B(x) | BIT_PKTLEN_PARA_8822B(v))
/* 2 REG_NOT_VALID_8822B */
@@ -3506,14 +5566,27 @@
#define BIT_SHIFT_BURST_SIZE_8822B 4
#define BIT_MASK_BURST_SIZE_8822B 0x3
-#define BIT_BURST_SIZE_8822B(x) (((x) & BIT_MASK_BURST_SIZE_8822B) << BIT_SHIFT_BURST_SIZE_8822B)
-#define BIT_GET_BURST_SIZE_8822B(x) (((x) >> BIT_SHIFT_BURST_SIZE_8822B) & BIT_MASK_BURST_SIZE_8822B)
-
+#define BIT_BURST_SIZE_8822B(x) \
+ (((x) & BIT_MASK_BURST_SIZE_8822B) << BIT_SHIFT_BURST_SIZE_8822B)
+#define BITS_BURST_SIZE_8822B \
+ (BIT_MASK_BURST_SIZE_8822B << BIT_SHIFT_BURST_SIZE_8822B)
+#define BIT_CLEAR_BURST_SIZE_8822B(x) ((x) & (~BITS_BURST_SIZE_8822B))
+#define BIT_GET_BURST_SIZE_8822B(x) \
+ (((x) >> BIT_SHIFT_BURST_SIZE_8822B) & BIT_MASK_BURST_SIZE_8822B)
+#define BIT_SET_BURST_SIZE_8822B(x, v) \
+ (BIT_CLEAR_BURST_SIZE_8822B(x) | BIT_BURST_SIZE_8822B(v))
#define BIT_SHIFT_BURST_CNT_8822B 2
#define BIT_MASK_BURST_CNT_8822B 0x3
-#define BIT_BURST_CNT_8822B(x) (((x) & BIT_MASK_BURST_CNT_8822B) << BIT_SHIFT_BURST_CNT_8822B)
-#define BIT_GET_BURST_CNT_8822B(x) (((x) >> BIT_SHIFT_BURST_CNT_8822B) & BIT_MASK_BURST_CNT_8822B)
+#define BIT_BURST_CNT_8822B(x) \
+ (((x) & BIT_MASK_BURST_CNT_8822B) << BIT_SHIFT_BURST_CNT_8822B)
+#define BITS_BURST_CNT_8822B \
+ (BIT_MASK_BURST_CNT_8822B << BIT_SHIFT_BURST_CNT_8822B)
+#define BIT_CLEAR_BURST_CNT_8822B(x) ((x) & (~BITS_BURST_CNT_8822B))
+#define BIT_GET_BURST_CNT_8822B(x) \
+ (((x) >> BIT_SHIFT_BURST_CNT_8822B) & BIT_MASK_BURST_CNT_8822B)
+#define BIT_SET_BURST_CNT_8822B(x, v) \
+ (BIT_CLEAR_BURST_CNT_8822B(x) | BIT_BURST_CNT_8822B(v))
#define BIT_DMA_MODE_8822B BIT(1)
@@ -3521,53 +5594,111 @@
#define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822B 24
#define BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822B 0xf
-#define BIT_R_C2H_STR_ADDR_16_TO_19_8822B(x) (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822B) << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822B)
-#define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8822B(x) (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822B) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822B)
+#define BIT_R_C2H_STR_ADDR_16_TO_19_8822B(x) \
+ (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822B) \
+ << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822B)
+#define BITS_R_C2H_STR_ADDR_16_TO_19_8822B \
+ (BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822B \
+ << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822B)
+#define BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8822B(x) \
+ ((x) & (~BITS_R_C2H_STR_ADDR_16_TO_19_8822B))
+#define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8822B(x) \
+ (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822B) & \
+ BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822B)
+#define BIT_SET_R_C2H_STR_ADDR_16_TO_19_8822B(x, v) \
+ (BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8822B(x) | \
+ BIT_R_C2H_STR_ADDR_16_TO_19_8822B(v))
#define BIT_R_C2H_PKT_REQ_8822B BIT(16)
#define BIT_SHIFT_R_C2H_STR_ADDR_8822B 0
#define BIT_MASK_R_C2H_STR_ADDR_8822B 0xffff
-#define BIT_R_C2H_STR_ADDR_8822B(x) (((x) & BIT_MASK_R_C2H_STR_ADDR_8822B) << BIT_SHIFT_R_C2H_STR_ADDR_8822B)
-#define BIT_GET_R_C2H_STR_ADDR_8822B(x) (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8822B) & BIT_MASK_R_C2H_STR_ADDR_8822B)
-
+#define BIT_R_C2H_STR_ADDR_8822B(x) \
+ (((x) & BIT_MASK_R_C2H_STR_ADDR_8822B) \
+ << BIT_SHIFT_R_C2H_STR_ADDR_8822B)
+#define BITS_R_C2H_STR_ADDR_8822B \
+ (BIT_MASK_R_C2H_STR_ADDR_8822B << BIT_SHIFT_R_C2H_STR_ADDR_8822B)
+#define BIT_CLEAR_R_C2H_STR_ADDR_8822B(x) ((x) & (~BITS_R_C2H_STR_ADDR_8822B))
+#define BIT_GET_R_C2H_STR_ADDR_8822B(x) \
+ (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8822B) & \
+ BIT_MASK_R_C2H_STR_ADDR_8822B)
+#define BIT_SET_R_C2H_STR_ADDR_8822B(x, v) \
+ (BIT_CLEAR_R_C2H_STR_ADDR_8822B(x) | BIT_R_C2H_STR_ADDR_8822B(v))
/* 2 REG_FWFF_C2H_8822B */
#define BIT_SHIFT_C2H_DMA_ADDR_8822B 0
#define BIT_MASK_C2H_DMA_ADDR_8822B 0x3ffff
-#define BIT_C2H_DMA_ADDR_8822B(x) (((x) & BIT_MASK_C2H_DMA_ADDR_8822B) << BIT_SHIFT_C2H_DMA_ADDR_8822B)
-#define BIT_GET_C2H_DMA_ADDR_8822B(x) (((x) >> BIT_SHIFT_C2H_DMA_ADDR_8822B) & BIT_MASK_C2H_DMA_ADDR_8822B)
-
+#define BIT_C2H_DMA_ADDR_8822B(x) \
+ (((x) & BIT_MASK_C2H_DMA_ADDR_8822B) << BIT_SHIFT_C2H_DMA_ADDR_8822B)
+#define BITS_C2H_DMA_ADDR_8822B \
+ (BIT_MASK_C2H_DMA_ADDR_8822B << BIT_SHIFT_C2H_DMA_ADDR_8822B)
+#define BIT_CLEAR_C2H_DMA_ADDR_8822B(x) ((x) & (~BITS_C2H_DMA_ADDR_8822B))
+#define BIT_GET_C2H_DMA_ADDR_8822B(x) \
+ (((x) >> BIT_SHIFT_C2H_DMA_ADDR_8822B) & BIT_MASK_C2H_DMA_ADDR_8822B)
+#define BIT_SET_C2H_DMA_ADDR_8822B(x, v) \
+ (BIT_CLEAR_C2H_DMA_ADDR_8822B(x) | BIT_C2H_DMA_ADDR_8822B(v))
/* 2 REG_FWFF_CTRL_8822B */
#define BIT_FWFF_DMAPKT_REQ_8822B BIT(31)
#define BIT_SHIFT_FWFF_DMA_PKT_NUM_8822B 16
#define BIT_MASK_FWFF_DMA_PKT_NUM_8822B 0xff
-#define BIT_FWFF_DMA_PKT_NUM_8822B(x) (((x) & BIT_MASK_FWFF_DMA_PKT_NUM_8822B) << BIT_SHIFT_FWFF_DMA_PKT_NUM_8822B)
-#define BIT_GET_FWFF_DMA_PKT_NUM_8822B(x) (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_8822B) & BIT_MASK_FWFF_DMA_PKT_NUM_8822B)
-
+#define BIT_FWFF_DMA_PKT_NUM_8822B(x) \
+ (((x) & BIT_MASK_FWFF_DMA_PKT_NUM_8822B) \
+ << BIT_SHIFT_FWFF_DMA_PKT_NUM_8822B)
+#define BITS_FWFF_DMA_PKT_NUM_8822B \
+ (BIT_MASK_FWFF_DMA_PKT_NUM_8822B << BIT_SHIFT_FWFF_DMA_PKT_NUM_8822B)
+#define BIT_CLEAR_FWFF_DMA_PKT_NUM_8822B(x) \
+ ((x) & (~BITS_FWFF_DMA_PKT_NUM_8822B))
+#define BIT_GET_FWFF_DMA_PKT_NUM_8822B(x) \
+ (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_8822B) & \
+ BIT_MASK_FWFF_DMA_PKT_NUM_8822B)
+#define BIT_SET_FWFF_DMA_PKT_NUM_8822B(x, v) \
+ (BIT_CLEAR_FWFF_DMA_PKT_NUM_8822B(x) | BIT_FWFF_DMA_PKT_NUM_8822B(v))
#define BIT_SHIFT_FWFF_STR_ADDR_8822B 0
#define BIT_MASK_FWFF_STR_ADDR_8822B 0xffff
-#define BIT_FWFF_STR_ADDR_8822B(x) (((x) & BIT_MASK_FWFF_STR_ADDR_8822B) << BIT_SHIFT_FWFF_STR_ADDR_8822B)
-#define BIT_GET_FWFF_STR_ADDR_8822B(x) (((x) >> BIT_SHIFT_FWFF_STR_ADDR_8822B) & BIT_MASK_FWFF_STR_ADDR_8822B)
-
+#define BIT_FWFF_STR_ADDR_8822B(x) \
+ (((x) & BIT_MASK_FWFF_STR_ADDR_8822B) << BIT_SHIFT_FWFF_STR_ADDR_8822B)
+#define BITS_FWFF_STR_ADDR_8822B \
+ (BIT_MASK_FWFF_STR_ADDR_8822B << BIT_SHIFT_FWFF_STR_ADDR_8822B)
+#define BIT_CLEAR_FWFF_STR_ADDR_8822B(x) ((x) & (~BITS_FWFF_STR_ADDR_8822B))
+#define BIT_GET_FWFF_STR_ADDR_8822B(x) \
+ (((x) >> BIT_SHIFT_FWFF_STR_ADDR_8822B) & BIT_MASK_FWFF_STR_ADDR_8822B)
+#define BIT_SET_FWFF_STR_ADDR_8822B(x, v) \
+ (BIT_CLEAR_FWFF_STR_ADDR_8822B(x) | BIT_FWFF_STR_ADDR_8822B(v))
/* 2 REG_FWFF_PKT_INFO_8822B */
#define BIT_SHIFT_FWFF_PKT_QUEUED_8822B 16
#define BIT_MASK_FWFF_PKT_QUEUED_8822B 0xff
-#define BIT_FWFF_PKT_QUEUED_8822B(x) (((x) & BIT_MASK_FWFF_PKT_QUEUED_8822B) << BIT_SHIFT_FWFF_PKT_QUEUED_8822B)
-#define BIT_GET_FWFF_PKT_QUEUED_8822B(x) (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_8822B) & BIT_MASK_FWFF_PKT_QUEUED_8822B)
-
+#define BIT_FWFF_PKT_QUEUED_8822B(x) \
+ (((x) & BIT_MASK_FWFF_PKT_QUEUED_8822B) \
+ << BIT_SHIFT_FWFF_PKT_QUEUED_8822B)
+#define BITS_FWFF_PKT_QUEUED_8822B \
+ (BIT_MASK_FWFF_PKT_QUEUED_8822B << BIT_SHIFT_FWFF_PKT_QUEUED_8822B)
+#define BIT_CLEAR_FWFF_PKT_QUEUED_8822B(x) ((x) & (~BITS_FWFF_PKT_QUEUED_8822B))
+#define BIT_GET_FWFF_PKT_QUEUED_8822B(x) \
+ (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_8822B) & \
+ BIT_MASK_FWFF_PKT_QUEUED_8822B)
+#define BIT_SET_FWFF_PKT_QUEUED_8822B(x, v) \
+ (BIT_CLEAR_FWFF_PKT_QUEUED_8822B(x) | BIT_FWFF_PKT_QUEUED_8822B(v))
#define BIT_SHIFT_FWFF_PKT_STR_ADDR_8822B 0
#define BIT_MASK_FWFF_PKT_STR_ADDR_8822B 0xffff
-#define BIT_FWFF_PKT_STR_ADDR_8822B(x) (((x) & BIT_MASK_FWFF_PKT_STR_ADDR_8822B) << BIT_SHIFT_FWFF_PKT_STR_ADDR_8822B)
-#define BIT_GET_FWFF_PKT_STR_ADDR_8822B(x) (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_8822B) & BIT_MASK_FWFF_PKT_STR_ADDR_8822B)
-
+#define BIT_FWFF_PKT_STR_ADDR_8822B(x) \
+ (((x) & BIT_MASK_FWFF_PKT_STR_ADDR_8822B) \
+ << BIT_SHIFT_FWFF_PKT_STR_ADDR_8822B)
+#define BITS_FWFF_PKT_STR_ADDR_8822B \
+ (BIT_MASK_FWFF_PKT_STR_ADDR_8822B << BIT_SHIFT_FWFF_PKT_STR_ADDR_8822B)
+#define BIT_CLEAR_FWFF_PKT_STR_ADDR_8822B(x) \
+ ((x) & (~BITS_FWFF_PKT_STR_ADDR_8822B))
+#define BIT_GET_FWFF_PKT_STR_ADDR_8822B(x) \
+ (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_8822B) & \
+ BIT_MASK_FWFF_PKT_STR_ADDR_8822B)
+#define BIT_SET_FWFF_PKT_STR_ADDR_8822B(x, v) \
+ (BIT_CLEAR_FWFF_PKT_STR_ADDR_8822B(x) | BIT_FWFF_PKT_STR_ADDR_8822B(v))
/* 2 REG_NOT_VALID_8822B */
@@ -3575,20 +5706,33 @@
#define BIT_SHIFT_DDMACH0_SA_8822B 0
#define BIT_MASK_DDMACH0_SA_8822B 0xffffffffL
-#define BIT_DDMACH0_SA_8822B(x) (((x) & BIT_MASK_DDMACH0_SA_8822B) << BIT_SHIFT_DDMACH0_SA_8822B)
-#define BIT_GET_DDMACH0_SA_8822B(x) (((x) >> BIT_SHIFT_DDMACH0_SA_8822B) & BIT_MASK_DDMACH0_SA_8822B)
-
+#define BIT_DDMACH0_SA_8822B(x) \
+ (((x) & BIT_MASK_DDMACH0_SA_8822B) << BIT_SHIFT_DDMACH0_SA_8822B)
+#define BITS_DDMACH0_SA_8822B \
+ (BIT_MASK_DDMACH0_SA_8822B << BIT_SHIFT_DDMACH0_SA_8822B)
+#define BIT_CLEAR_DDMACH0_SA_8822B(x) ((x) & (~BITS_DDMACH0_SA_8822B))
+#define BIT_GET_DDMACH0_SA_8822B(x) \
+ (((x) >> BIT_SHIFT_DDMACH0_SA_8822B) & BIT_MASK_DDMACH0_SA_8822B)
+#define BIT_SET_DDMACH0_SA_8822B(x, v) \
+ (BIT_CLEAR_DDMACH0_SA_8822B(x) | BIT_DDMACH0_SA_8822B(v))
/* 2 REG_DDMA_CH0DA_8822B */
#define BIT_SHIFT_DDMACH0_DA_8822B 0
#define BIT_MASK_DDMACH0_DA_8822B 0xffffffffL
-#define BIT_DDMACH0_DA_8822B(x) (((x) & BIT_MASK_DDMACH0_DA_8822B) << BIT_SHIFT_DDMACH0_DA_8822B)
-#define BIT_GET_DDMACH0_DA_8822B(x) (((x) >> BIT_SHIFT_DDMACH0_DA_8822B) & BIT_MASK_DDMACH0_DA_8822B)
-
+#define BIT_DDMACH0_DA_8822B(x) \
+ (((x) & BIT_MASK_DDMACH0_DA_8822B) << BIT_SHIFT_DDMACH0_DA_8822B)
+#define BITS_DDMACH0_DA_8822B \
+ (BIT_MASK_DDMACH0_DA_8822B << BIT_SHIFT_DDMACH0_DA_8822B)
+#define BIT_CLEAR_DDMACH0_DA_8822B(x) ((x) & (~BITS_DDMACH0_DA_8822B))
+#define BIT_GET_DDMACH0_DA_8822B(x) \
+ (((x) >> BIT_SHIFT_DDMACH0_DA_8822B) & BIT_MASK_DDMACH0_DA_8822B)
+#define BIT_SET_DDMACH0_DA_8822B(x, v) \
+ (BIT_CLEAR_DDMACH0_DA_8822B(x) | BIT_DDMACH0_DA_8822B(v))
/* 2 REG_DDMA_CH0CTRL_8822B */
#define BIT_DDMACH0_OWN_8822B BIT(31)
+#define BIT_DDMACH0_IDMEM_ERR_8822B BIT(30)
#define BIT_DDMACH0_CHKSUM_EN_8822B BIT(29)
#define BIT_DDMACH0_DA_W_DISABLE_8822B BIT(28)
#define BIT_DDMACH0_CHKSUM_STS_8822B BIT(27)
@@ -3598,28 +5742,47 @@
#define BIT_SHIFT_DDMACH0_DLEN_8822B 0
#define BIT_MASK_DDMACH0_DLEN_8822B 0x3ffff
-#define BIT_DDMACH0_DLEN_8822B(x) (((x) & BIT_MASK_DDMACH0_DLEN_8822B) << BIT_SHIFT_DDMACH0_DLEN_8822B)
-#define BIT_GET_DDMACH0_DLEN_8822B(x) (((x) >> BIT_SHIFT_DDMACH0_DLEN_8822B) & BIT_MASK_DDMACH0_DLEN_8822B)
-
+#define BIT_DDMACH0_DLEN_8822B(x) \
+ (((x) & BIT_MASK_DDMACH0_DLEN_8822B) << BIT_SHIFT_DDMACH0_DLEN_8822B)
+#define BITS_DDMACH0_DLEN_8822B \
+ (BIT_MASK_DDMACH0_DLEN_8822B << BIT_SHIFT_DDMACH0_DLEN_8822B)
+#define BIT_CLEAR_DDMACH0_DLEN_8822B(x) ((x) & (~BITS_DDMACH0_DLEN_8822B))
+#define BIT_GET_DDMACH0_DLEN_8822B(x) \
+ (((x) >> BIT_SHIFT_DDMACH0_DLEN_8822B) & BIT_MASK_DDMACH0_DLEN_8822B)
+#define BIT_SET_DDMACH0_DLEN_8822B(x, v) \
+ (BIT_CLEAR_DDMACH0_DLEN_8822B(x) | BIT_DDMACH0_DLEN_8822B(v))
/* 2 REG_DDMA_CH1SA_8822B */
#define BIT_SHIFT_DDMACH1_SA_8822B 0
#define BIT_MASK_DDMACH1_SA_8822B 0xffffffffL
-#define BIT_DDMACH1_SA_8822B(x) (((x) & BIT_MASK_DDMACH1_SA_8822B) << BIT_SHIFT_DDMACH1_SA_8822B)
-#define BIT_GET_DDMACH1_SA_8822B(x) (((x) >> BIT_SHIFT_DDMACH1_SA_8822B) & BIT_MASK_DDMACH1_SA_8822B)
-
+#define BIT_DDMACH1_SA_8822B(x) \
+ (((x) & BIT_MASK_DDMACH1_SA_8822B) << BIT_SHIFT_DDMACH1_SA_8822B)
+#define BITS_DDMACH1_SA_8822B \
+ (BIT_MASK_DDMACH1_SA_8822B << BIT_SHIFT_DDMACH1_SA_8822B)
+#define BIT_CLEAR_DDMACH1_SA_8822B(x) ((x) & (~BITS_DDMACH1_SA_8822B))
+#define BIT_GET_DDMACH1_SA_8822B(x) \
+ (((x) >> BIT_SHIFT_DDMACH1_SA_8822B) & BIT_MASK_DDMACH1_SA_8822B)
+#define BIT_SET_DDMACH1_SA_8822B(x, v) \
+ (BIT_CLEAR_DDMACH1_SA_8822B(x) | BIT_DDMACH1_SA_8822B(v))
/* 2 REG_DDMA_CH1DA_8822B */
#define BIT_SHIFT_DDMACH1_DA_8822B 0
#define BIT_MASK_DDMACH1_DA_8822B 0xffffffffL
-#define BIT_DDMACH1_DA_8822B(x) (((x) & BIT_MASK_DDMACH1_DA_8822B) << BIT_SHIFT_DDMACH1_DA_8822B)
-#define BIT_GET_DDMACH1_DA_8822B(x) (((x) >> BIT_SHIFT_DDMACH1_DA_8822B) & BIT_MASK_DDMACH1_DA_8822B)
-
+#define BIT_DDMACH1_DA_8822B(x) \
+ (((x) & BIT_MASK_DDMACH1_DA_8822B) << BIT_SHIFT_DDMACH1_DA_8822B)
+#define BITS_DDMACH1_DA_8822B \
+ (BIT_MASK_DDMACH1_DA_8822B << BIT_SHIFT_DDMACH1_DA_8822B)
+#define BIT_CLEAR_DDMACH1_DA_8822B(x) ((x) & (~BITS_DDMACH1_DA_8822B))
+#define BIT_GET_DDMACH1_DA_8822B(x) \
+ (((x) >> BIT_SHIFT_DDMACH1_DA_8822B) & BIT_MASK_DDMACH1_DA_8822B)
+#define BIT_SET_DDMACH1_DA_8822B(x, v) \
+ (BIT_CLEAR_DDMACH1_DA_8822B(x) | BIT_DDMACH1_DA_8822B(v))
/* 2 REG_DDMA_CH1CTRL_8822B */
#define BIT_DDMACH1_OWN_8822B BIT(31)
+#define BIT_DDMACH1_IDMEM_ERR_8822B BIT(30)
#define BIT_DDMACH1_CHKSUM_EN_8822B BIT(29)
#define BIT_DDMACH1_DA_W_DISABLE_8822B BIT(28)
#define BIT_DDMACH1_CHKSUM_STS_8822B BIT(27)
@@ -3629,28 +5792,47 @@
#define BIT_SHIFT_DDMACH1_DLEN_8822B 0
#define BIT_MASK_DDMACH1_DLEN_8822B 0x3ffff
-#define BIT_DDMACH1_DLEN_8822B(x) (((x) & BIT_MASK_DDMACH1_DLEN_8822B) << BIT_SHIFT_DDMACH1_DLEN_8822B)
-#define BIT_GET_DDMACH1_DLEN_8822B(x) (((x) >> BIT_SHIFT_DDMACH1_DLEN_8822B) & BIT_MASK_DDMACH1_DLEN_8822B)
-
+#define BIT_DDMACH1_DLEN_8822B(x) \
+ (((x) & BIT_MASK_DDMACH1_DLEN_8822B) << BIT_SHIFT_DDMACH1_DLEN_8822B)
+#define BITS_DDMACH1_DLEN_8822B \
+ (BIT_MASK_DDMACH1_DLEN_8822B << BIT_SHIFT_DDMACH1_DLEN_8822B)
+#define BIT_CLEAR_DDMACH1_DLEN_8822B(x) ((x) & (~BITS_DDMACH1_DLEN_8822B))
+#define BIT_GET_DDMACH1_DLEN_8822B(x) \
+ (((x) >> BIT_SHIFT_DDMACH1_DLEN_8822B) & BIT_MASK_DDMACH1_DLEN_8822B)
+#define BIT_SET_DDMACH1_DLEN_8822B(x, v) \
+ (BIT_CLEAR_DDMACH1_DLEN_8822B(x) | BIT_DDMACH1_DLEN_8822B(v))
/* 2 REG_DDMA_CH2SA_8822B */
#define BIT_SHIFT_DDMACH2_SA_8822B 0
#define BIT_MASK_DDMACH2_SA_8822B 0xffffffffL
-#define BIT_DDMACH2_SA_8822B(x) (((x) & BIT_MASK_DDMACH2_SA_8822B) << BIT_SHIFT_DDMACH2_SA_8822B)
-#define BIT_GET_DDMACH2_SA_8822B(x) (((x) >> BIT_SHIFT_DDMACH2_SA_8822B) & BIT_MASK_DDMACH2_SA_8822B)
-
+#define BIT_DDMACH2_SA_8822B(x) \
+ (((x) & BIT_MASK_DDMACH2_SA_8822B) << BIT_SHIFT_DDMACH2_SA_8822B)
+#define BITS_DDMACH2_SA_8822B \
+ (BIT_MASK_DDMACH2_SA_8822B << BIT_SHIFT_DDMACH2_SA_8822B)
+#define BIT_CLEAR_DDMACH2_SA_8822B(x) ((x) & (~BITS_DDMACH2_SA_8822B))
+#define BIT_GET_DDMACH2_SA_8822B(x) \
+ (((x) >> BIT_SHIFT_DDMACH2_SA_8822B) & BIT_MASK_DDMACH2_SA_8822B)
+#define BIT_SET_DDMACH2_SA_8822B(x, v) \
+ (BIT_CLEAR_DDMACH2_SA_8822B(x) | BIT_DDMACH2_SA_8822B(v))
/* 2 REG_DDMA_CH2DA_8822B */
#define BIT_SHIFT_DDMACH2_DA_8822B 0
#define BIT_MASK_DDMACH2_DA_8822B 0xffffffffL
-#define BIT_DDMACH2_DA_8822B(x) (((x) & BIT_MASK_DDMACH2_DA_8822B) << BIT_SHIFT_DDMACH2_DA_8822B)
-#define BIT_GET_DDMACH2_DA_8822B(x) (((x) >> BIT_SHIFT_DDMACH2_DA_8822B) & BIT_MASK_DDMACH2_DA_8822B)
-
+#define BIT_DDMACH2_DA_8822B(x) \
+ (((x) & BIT_MASK_DDMACH2_DA_8822B) << BIT_SHIFT_DDMACH2_DA_8822B)
+#define BITS_DDMACH2_DA_8822B \
+ (BIT_MASK_DDMACH2_DA_8822B << BIT_SHIFT_DDMACH2_DA_8822B)
+#define BIT_CLEAR_DDMACH2_DA_8822B(x) ((x) & (~BITS_DDMACH2_DA_8822B))
+#define BIT_GET_DDMACH2_DA_8822B(x) \
+ (((x) >> BIT_SHIFT_DDMACH2_DA_8822B) & BIT_MASK_DDMACH2_DA_8822B)
+#define BIT_SET_DDMACH2_DA_8822B(x, v) \
+ (BIT_CLEAR_DDMACH2_DA_8822B(x) | BIT_DDMACH2_DA_8822B(v))
/* 2 REG_DDMA_CH2CTRL_8822B */
#define BIT_DDMACH2_OWN_8822B BIT(31)
+#define BIT_DDMACH2_IDMEM_ERR_8822B BIT(30)
#define BIT_DDMACH2_CHKSUM_EN_8822B BIT(29)
#define BIT_DDMACH2_DA_W_DISABLE_8822B BIT(28)
#define BIT_DDMACH2_CHKSUM_STS_8822B BIT(27)
@@ -3660,28 +5842,47 @@
#define BIT_SHIFT_DDMACH2_DLEN_8822B 0
#define BIT_MASK_DDMACH2_DLEN_8822B 0x3ffff
-#define BIT_DDMACH2_DLEN_8822B(x) (((x) & BIT_MASK_DDMACH2_DLEN_8822B) << BIT_SHIFT_DDMACH2_DLEN_8822B)
-#define BIT_GET_DDMACH2_DLEN_8822B(x) (((x) >> BIT_SHIFT_DDMACH2_DLEN_8822B) & BIT_MASK_DDMACH2_DLEN_8822B)
-
+#define BIT_DDMACH2_DLEN_8822B(x) \
+ (((x) & BIT_MASK_DDMACH2_DLEN_8822B) << BIT_SHIFT_DDMACH2_DLEN_8822B)
+#define BITS_DDMACH2_DLEN_8822B \
+ (BIT_MASK_DDMACH2_DLEN_8822B << BIT_SHIFT_DDMACH2_DLEN_8822B)
+#define BIT_CLEAR_DDMACH2_DLEN_8822B(x) ((x) & (~BITS_DDMACH2_DLEN_8822B))
+#define BIT_GET_DDMACH2_DLEN_8822B(x) \
+ (((x) >> BIT_SHIFT_DDMACH2_DLEN_8822B) & BIT_MASK_DDMACH2_DLEN_8822B)
+#define BIT_SET_DDMACH2_DLEN_8822B(x, v) \
+ (BIT_CLEAR_DDMACH2_DLEN_8822B(x) | BIT_DDMACH2_DLEN_8822B(v))
/* 2 REG_DDMA_CH3SA_8822B */
#define BIT_SHIFT_DDMACH3_SA_8822B 0
#define BIT_MASK_DDMACH3_SA_8822B 0xffffffffL
-#define BIT_DDMACH3_SA_8822B(x) (((x) & BIT_MASK_DDMACH3_SA_8822B) << BIT_SHIFT_DDMACH3_SA_8822B)
-#define BIT_GET_DDMACH3_SA_8822B(x) (((x) >> BIT_SHIFT_DDMACH3_SA_8822B) & BIT_MASK_DDMACH3_SA_8822B)
-
+#define BIT_DDMACH3_SA_8822B(x) \
+ (((x) & BIT_MASK_DDMACH3_SA_8822B) << BIT_SHIFT_DDMACH3_SA_8822B)
+#define BITS_DDMACH3_SA_8822B \
+ (BIT_MASK_DDMACH3_SA_8822B << BIT_SHIFT_DDMACH3_SA_8822B)
+#define BIT_CLEAR_DDMACH3_SA_8822B(x) ((x) & (~BITS_DDMACH3_SA_8822B))
+#define BIT_GET_DDMACH3_SA_8822B(x) \
+ (((x) >> BIT_SHIFT_DDMACH3_SA_8822B) & BIT_MASK_DDMACH3_SA_8822B)
+#define BIT_SET_DDMACH3_SA_8822B(x, v) \
+ (BIT_CLEAR_DDMACH3_SA_8822B(x) | BIT_DDMACH3_SA_8822B(v))
/* 2 REG_DDMA_CH3DA_8822B */
#define BIT_SHIFT_DDMACH3_DA_8822B 0
#define BIT_MASK_DDMACH3_DA_8822B 0xffffffffL
-#define BIT_DDMACH3_DA_8822B(x) (((x) & BIT_MASK_DDMACH3_DA_8822B) << BIT_SHIFT_DDMACH3_DA_8822B)
-#define BIT_GET_DDMACH3_DA_8822B(x) (((x) >> BIT_SHIFT_DDMACH3_DA_8822B) & BIT_MASK_DDMACH3_DA_8822B)
-
+#define BIT_DDMACH3_DA_8822B(x) \
+ (((x) & BIT_MASK_DDMACH3_DA_8822B) << BIT_SHIFT_DDMACH3_DA_8822B)
+#define BITS_DDMACH3_DA_8822B \
+ (BIT_MASK_DDMACH3_DA_8822B << BIT_SHIFT_DDMACH3_DA_8822B)
+#define BIT_CLEAR_DDMACH3_DA_8822B(x) ((x) & (~BITS_DDMACH3_DA_8822B))
+#define BIT_GET_DDMACH3_DA_8822B(x) \
+ (((x) >> BIT_SHIFT_DDMACH3_DA_8822B) & BIT_MASK_DDMACH3_DA_8822B)
+#define BIT_SET_DDMACH3_DA_8822B(x, v) \
+ (BIT_CLEAR_DDMACH3_DA_8822B(x) | BIT_DDMACH3_DA_8822B(v))
/* 2 REG_DDMA_CH3CTRL_8822B */
#define BIT_DDMACH3_OWN_8822B BIT(31)
+#define BIT_DDMACH3_IDMEM_ERR_8822B BIT(30)
#define BIT_DDMACH3_CHKSUM_EN_8822B BIT(29)
#define BIT_DDMACH3_DA_W_DISABLE_8822B BIT(28)
#define BIT_DDMACH3_CHKSUM_STS_8822B BIT(27)
@@ -3691,28 +5892,47 @@
#define BIT_SHIFT_DDMACH3_DLEN_8822B 0
#define BIT_MASK_DDMACH3_DLEN_8822B 0x3ffff
-#define BIT_DDMACH3_DLEN_8822B(x) (((x) & BIT_MASK_DDMACH3_DLEN_8822B) << BIT_SHIFT_DDMACH3_DLEN_8822B)
-#define BIT_GET_DDMACH3_DLEN_8822B(x) (((x) >> BIT_SHIFT_DDMACH3_DLEN_8822B) & BIT_MASK_DDMACH3_DLEN_8822B)
-
+#define BIT_DDMACH3_DLEN_8822B(x) \
+ (((x) & BIT_MASK_DDMACH3_DLEN_8822B) << BIT_SHIFT_DDMACH3_DLEN_8822B)
+#define BITS_DDMACH3_DLEN_8822B \
+ (BIT_MASK_DDMACH3_DLEN_8822B << BIT_SHIFT_DDMACH3_DLEN_8822B)
+#define BIT_CLEAR_DDMACH3_DLEN_8822B(x) ((x) & (~BITS_DDMACH3_DLEN_8822B))
+#define BIT_GET_DDMACH3_DLEN_8822B(x) \
+ (((x) >> BIT_SHIFT_DDMACH3_DLEN_8822B) & BIT_MASK_DDMACH3_DLEN_8822B)
+#define BIT_SET_DDMACH3_DLEN_8822B(x, v) \
+ (BIT_CLEAR_DDMACH3_DLEN_8822B(x) | BIT_DDMACH3_DLEN_8822B(v))
/* 2 REG_DDMA_CH4SA_8822B */
#define BIT_SHIFT_DDMACH4_SA_8822B 0
#define BIT_MASK_DDMACH4_SA_8822B 0xffffffffL
-#define BIT_DDMACH4_SA_8822B(x) (((x) & BIT_MASK_DDMACH4_SA_8822B) << BIT_SHIFT_DDMACH4_SA_8822B)
-#define BIT_GET_DDMACH4_SA_8822B(x) (((x) >> BIT_SHIFT_DDMACH4_SA_8822B) & BIT_MASK_DDMACH4_SA_8822B)
-
+#define BIT_DDMACH4_SA_8822B(x) \
+ (((x) & BIT_MASK_DDMACH4_SA_8822B) << BIT_SHIFT_DDMACH4_SA_8822B)
+#define BITS_DDMACH4_SA_8822B \
+ (BIT_MASK_DDMACH4_SA_8822B << BIT_SHIFT_DDMACH4_SA_8822B)
+#define BIT_CLEAR_DDMACH4_SA_8822B(x) ((x) & (~BITS_DDMACH4_SA_8822B))
+#define BIT_GET_DDMACH4_SA_8822B(x) \
+ (((x) >> BIT_SHIFT_DDMACH4_SA_8822B) & BIT_MASK_DDMACH4_SA_8822B)
+#define BIT_SET_DDMACH4_SA_8822B(x, v) \
+ (BIT_CLEAR_DDMACH4_SA_8822B(x) | BIT_DDMACH4_SA_8822B(v))
/* 2 REG_DDMA_CH4DA_8822B */
#define BIT_SHIFT_DDMACH4_DA_8822B 0
#define BIT_MASK_DDMACH4_DA_8822B 0xffffffffL
-#define BIT_DDMACH4_DA_8822B(x) (((x) & BIT_MASK_DDMACH4_DA_8822B) << BIT_SHIFT_DDMACH4_DA_8822B)
-#define BIT_GET_DDMACH4_DA_8822B(x) (((x) >> BIT_SHIFT_DDMACH4_DA_8822B) & BIT_MASK_DDMACH4_DA_8822B)
-
+#define BIT_DDMACH4_DA_8822B(x) \
+ (((x) & BIT_MASK_DDMACH4_DA_8822B) << BIT_SHIFT_DDMACH4_DA_8822B)
+#define BITS_DDMACH4_DA_8822B \
+ (BIT_MASK_DDMACH4_DA_8822B << BIT_SHIFT_DDMACH4_DA_8822B)
+#define BIT_CLEAR_DDMACH4_DA_8822B(x) ((x) & (~BITS_DDMACH4_DA_8822B))
+#define BIT_GET_DDMACH4_DA_8822B(x) \
+ (((x) >> BIT_SHIFT_DDMACH4_DA_8822B) & BIT_MASK_DDMACH4_DA_8822B)
+#define BIT_SET_DDMACH4_DA_8822B(x, v) \
+ (BIT_CLEAR_DDMACH4_DA_8822B(x) | BIT_DDMACH4_DA_8822B(v))
/* 2 REG_DDMA_CH4CTRL_8822B */
#define BIT_DDMACH4_OWN_8822B BIT(31)
+#define BIT_DDMACH4_IDMEM_ERR_8822B BIT(30)
#define BIT_DDMACH4_CHKSUM_EN_8822B BIT(29)
#define BIT_DDMACH4_DA_W_DISABLE_8822B BIT(28)
#define BIT_DDMACH4_CHKSUM_STS_8822B BIT(27)
@@ -3722,28 +5942,47 @@
#define BIT_SHIFT_DDMACH4_DLEN_8822B 0
#define BIT_MASK_DDMACH4_DLEN_8822B 0x3ffff
-#define BIT_DDMACH4_DLEN_8822B(x) (((x) & BIT_MASK_DDMACH4_DLEN_8822B) << BIT_SHIFT_DDMACH4_DLEN_8822B)
-#define BIT_GET_DDMACH4_DLEN_8822B(x) (((x) >> BIT_SHIFT_DDMACH4_DLEN_8822B) & BIT_MASK_DDMACH4_DLEN_8822B)
-
+#define BIT_DDMACH4_DLEN_8822B(x) \
+ (((x) & BIT_MASK_DDMACH4_DLEN_8822B) << BIT_SHIFT_DDMACH4_DLEN_8822B)
+#define BITS_DDMACH4_DLEN_8822B \
+ (BIT_MASK_DDMACH4_DLEN_8822B << BIT_SHIFT_DDMACH4_DLEN_8822B)
+#define BIT_CLEAR_DDMACH4_DLEN_8822B(x) ((x) & (~BITS_DDMACH4_DLEN_8822B))
+#define BIT_GET_DDMACH4_DLEN_8822B(x) \
+ (((x) >> BIT_SHIFT_DDMACH4_DLEN_8822B) & BIT_MASK_DDMACH4_DLEN_8822B)
+#define BIT_SET_DDMACH4_DLEN_8822B(x, v) \
+ (BIT_CLEAR_DDMACH4_DLEN_8822B(x) | BIT_DDMACH4_DLEN_8822B(v))
/* 2 REG_DDMA_CH5SA_8822B */
#define BIT_SHIFT_DDMACH5_SA_8822B 0
#define BIT_MASK_DDMACH5_SA_8822B 0xffffffffL
-#define BIT_DDMACH5_SA_8822B(x) (((x) & BIT_MASK_DDMACH5_SA_8822B) << BIT_SHIFT_DDMACH5_SA_8822B)
-#define BIT_GET_DDMACH5_SA_8822B(x) (((x) >> BIT_SHIFT_DDMACH5_SA_8822B) & BIT_MASK_DDMACH5_SA_8822B)
-
+#define BIT_DDMACH5_SA_8822B(x) \
+ (((x) & BIT_MASK_DDMACH5_SA_8822B) << BIT_SHIFT_DDMACH5_SA_8822B)
+#define BITS_DDMACH5_SA_8822B \
+ (BIT_MASK_DDMACH5_SA_8822B << BIT_SHIFT_DDMACH5_SA_8822B)
+#define BIT_CLEAR_DDMACH5_SA_8822B(x) ((x) & (~BITS_DDMACH5_SA_8822B))
+#define BIT_GET_DDMACH5_SA_8822B(x) \
+ (((x) >> BIT_SHIFT_DDMACH5_SA_8822B) & BIT_MASK_DDMACH5_SA_8822B)
+#define BIT_SET_DDMACH5_SA_8822B(x, v) \
+ (BIT_CLEAR_DDMACH5_SA_8822B(x) | BIT_DDMACH5_SA_8822B(v))
/* 2 REG_DDMA_CH5DA_8822B */
#define BIT_SHIFT_DDMACH5_DA_8822B 0
#define BIT_MASK_DDMACH5_DA_8822B 0xffffffffL
-#define BIT_DDMACH5_DA_8822B(x) (((x) & BIT_MASK_DDMACH5_DA_8822B) << BIT_SHIFT_DDMACH5_DA_8822B)
-#define BIT_GET_DDMACH5_DA_8822B(x) (((x) >> BIT_SHIFT_DDMACH5_DA_8822B) & BIT_MASK_DDMACH5_DA_8822B)
-
+#define BIT_DDMACH5_DA_8822B(x) \
+ (((x) & BIT_MASK_DDMACH5_DA_8822B) << BIT_SHIFT_DDMACH5_DA_8822B)
+#define BITS_DDMACH5_DA_8822B \
+ (BIT_MASK_DDMACH5_DA_8822B << BIT_SHIFT_DDMACH5_DA_8822B)
+#define BIT_CLEAR_DDMACH5_DA_8822B(x) ((x) & (~BITS_DDMACH5_DA_8822B))
+#define BIT_GET_DDMACH5_DA_8822B(x) \
+ (((x) >> BIT_SHIFT_DDMACH5_DA_8822B) & BIT_MASK_DDMACH5_DA_8822B)
+#define BIT_SET_DDMACH5_DA_8822B(x, v) \
+ (BIT_CLEAR_DDMACH5_DA_8822B(x) | BIT_DDMACH5_DA_8822B(v))
/* 2 REG_REG_DDMA_CH5CTRL_8822B */
#define BIT_DDMACH5_OWN_8822B BIT(31)
+#define BIT_DDMACH5_IDMEM_ERR_8822B BIT(30)
#define BIT_DDMACH5_CHKSUM_EN_8822B BIT(29)
#define BIT_DDMACH5_DA_W_DISABLE_8822B BIT(28)
#define BIT_DDMACH5_CHKSUM_STS_8822B BIT(27)
@@ -3753,9 +5992,15 @@
#define BIT_SHIFT_DDMACH5_DLEN_8822B 0
#define BIT_MASK_DDMACH5_DLEN_8822B 0x3ffff
-#define BIT_DDMACH5_DLEN_8822B(x) (((x) & BIT_MASK_DDMACH5_DLEN_8822B) << BIT_SHIFT_DDMACH5_DLEN_8822B)
-#define BIT_GET_DDMACH5_DLEN_8822B(x) (((x) >> BIT_SHIFT_DDMACH5_DLEN_8822B) & BIT_MASK_DDMACH5_DLEN_8822B)
-
+#define BIT_DDMACH5_DLEN_8822B(x) \
+ (((x) & BIT_MASK_DDMACH5_DLEN_8822B) << BIT_SHIFT_DDMACH5_DLEN_8822B)
+#define BITS_DDMACH5_DLEN_8822B \
+ (BIT_MASK_DDMACH5_DLEN_8822B << BIT_SHIFT_DDMACH5_DLEN_8822B)
+#define BIT_CLEAR_DDMACH5_DLEN_8822B(x) ((x) & (~BITS_DDMACH5_DLEN_8822B))
+#define BIT_GET_DDMACH5_DLEN_8822B(x) \
+ (((x) >> BIT_SHIFT_DDMACH5_DLEN_8822B) & BIT_MASK_DDMACH5_DLEN_8822B)
+#define BIT_SET_DDMACH5_DLEN_8822B(x, v) \
+ (BIT_CLEAR_DDMACH5_DLEN_8822B(x) | BIT_DDMACH5_DLEN_8822B(v))
/* 2 REG_DDMA_INT_MSK_8822B */
#define BIT_DDMACH5_MSK_8822B BIT(5)
@@ -3777,9 +6022,15 @@
#define BIT_SHIFT_IDDMA0_CHKSUM_8822B 0
#define BIT_MASK_IDDMA0_CHKSUM_8822B 0xffff
-#define BIT_IDDMA0_CHKSUM_8822B(x) (((x) & BIT_MASK_IDDMA0_CHKSUM_8822B) << BIT_SHIFT_IDDMA0_CHKSUM_8822B)
-#define BIT_GET_IDDMA0_CHKSUM_8822B(x) (((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8822B) & BIT_MASK_IDDMA0_CHKSUM_8822B)
-
+#define BIT_IDDMA0_CHKSUM_8822B(x) \
+ (((x) & BIT_MASK_IDDMA0_CHKSUM_8822B) << BIT_SHIFT_IDDMA0_CHKSUM_8822B)
+#define BITS_IDDMA0_CHKSUM_8822B \
+ (BIT_MASK_IDDMA0_CHKSUM_8822B << BIT_SHIFT_IDDMA0_CHKSUM_8822B)
+#define BIT_CLEAR_IDDMA0_CHKSUM_8822B(x) ((x) & (~BITS_IDDMA0_CHKSUM_8822B))
+#define BIT_GET_IDDMA0_CHKSUM_8822B(x) \
+ (((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8822B) & BIT_MASK_IDDMA0_CHKSUM_8822B)
+#define BIT_SET_IDDMA0_CHKSUM_8822B(x, v) \
+ (BIT_CLEAR_IDDMA0_CHKSUM_8822B(x) | BIT_IDDMA0_CHKSUM_8822B(v))
/* 2 REG_DDMA_MONITOR_8822B */
#define BIT_IDDMA0_PERMU_UNDERFLOW_8822B BIT(14)
@@ -3799,15 +6050,33 @@
#define BIT_SHIFT_PCIE_MAX_RXDMA_8822B 28
#define BIT_MASK_PCIE_MAX_RXDMA_8822B 0x7
-#define BIT_PCIE_MAX_RXDMA_8822B(x) (((x) & BIT_MASK_PCIE_MAX_RXDMA_8822B) << BIT_SHIFT_PCIE_MAX_RXDMA_8822B)
-#define BIT_GET_PCIE_MAX_RXDMA_8822B(x) (((x) >> BIT_SHIFT_PCIE_MAX_RXDMA_8822B) & BIT_MASK_PCIE_MAX_RXDMA_8822B)
+#define BIT_PCIE_MAX_RXDMA_8822B(x) \
+ (((x) & BIT_MASK_PCIE_MAX_RXDMA_8822B) \
+ << BIT_SHIFT_PCIE_MAX_RXDMA_8822B)
+#define BITS_PCIE_MAX_RXDMA_8822B \
+ (BIT_MASK_PCIE_MAX_RXDMA_8822B << BIT_SHIFT_PCIE_MAX_RXDMA_8822B)
+#define BIT_CLEAR_PCIE_MAX_RXDMA_8822B(x) ((x) & (~BITS_PCIE_MAX_RXDMA_8822B))
+#define BIT_GET_PCIE_MAX_RXDMA_8822B(x) \
+ (((x) >> BIT_SHIFT_PCIE_MAX_RXDMA_8822B) & \
+ BIT_MASK_PCIE_MAX_RXDMA_8822B)
+#define BIT_SET_PCIE_MAX_RXDMA_8822B(x, v) \
+ (BIT_CLEAR_PCIE_MAX_RXDMA_8822B(x) | BIT_PCIE_MAX_RXDMA_8822B(v))
#define BIT_MULRW_8822B BIT(27)
#define BIT_SHIFT_PCIE_MAX_TXDMA_8822B 24
#define BIT_MASK_PCIE_MAX_TXDMA_8822B 0x7
-#define BIT_PCIE_MAX_TXDMA_8822B(x) (((x) & BIT_MASK_PCIE_MAX_TXDMA_8822B) << BIT_SHIFT_PCIE_MAX_TXDMA_8822B)
-#define BIT_GET_PCIE_MAX_TXDMA_8822B(x) (((x) >> BIT_SHIFT_PCIE_MAX_TXDMA_8822B) & BIT_MASK_PCIE_MAX_TXDMA_8822B)
+#define BIT_PCIE_MAX_TXDMA_8822B(x) \
+ (((x) & BIT_MASK_PCIE_MAX_TXDMA_8822B) \
+ << BIT_SHIFT_PCIE_MAX_TXDMA_8822B)
+#define BITS_PCIE_MAX_TXDMA_8822B \
+ (BIT_MASK_PCIE_MAX_TXDMA_8822B << BIT_SHIFT_PCIE_MAX_TXDMA_8822B)
+#define BIT_CLEAR_PCIE_MAX_TXDMA_8822B(x) ((x) & (~BITS_PCIE_MAX_TXDMA_8822B))
+#define BIT_GET_PCIE_MAX_TXDMA_8822B(x) \
+ (((x) >> BIT_SHIFT_PCIE_MAX_TXDMA_8822B) & \
+ BIT_MASK_PCIE_MAX_TXDMA_8822B)
+#define BIT_SET_PCIE_MAX_TXDMA_8822B(x, v) \
+ (BIT_CLEAR_PCIE_MAX_TXDMA_8822B(x) | BIT_PCIE_MAX_TXDMA_8822B(v))
#define BIT_EN_CPL_TIMEOUT_PS_8822B BIT(22)
#define BIT_REG_TXDMA_FAIL_PS_8822B BIT(21)
@@ -3837,378 +6106,729 @@
#define BIT_SHIFT_TXTTIMER_MATCH_NUM_8822B 28
#define BIT_MASK_TXTTIMER_MATCH_NUM_8822B 0xf
-#define BIT_TXTTIMER_MATCH_NUM_8822B(x) (((x) & BIT_MASK_TXTTIMER_MATCH_NUM_8822B) << BIT_SHIFT_TXTTIMER_MATCH_NUM_8822B)
-#define BIT_GET_TXTTIMER_MATCH_NUM_8822B(x) (((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM_8822B) & BIT_MASK_TXTTIMER_MATCH_NUM_8822B)
-
+#define BIT_TXTTIMER_MATCH_NUM_8822B(x) \
+ (((x) & BIT_MASK_TXTTIMER_MATCH_NUM_8822B) \
+ << BIT_SHIFT_TXTTIMER_MATCH_NUM_8822B)
+#define BITS_TXTTIMER_MATCH_NUM_8822B \
+ (BIT_MASK_TXTTIMER_MATCH_NUM_8822B \
+ << BIT_SHIFT_TXTTIMER_MATCH_NUM_8822B)
+#define BIT_CLEAR_TXTTIMER_MATCH_NUM_8822B(x) \
+ ((x) & (~BITS_TXTTIMER_MATCH_NUM_8822B))
+#define BIT_GET_TXTTIMER_MATCH_NUM_8822B(x) \
+ (((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM_8822B) & \
+ BIT_MASK_TXTTIMER_MATCH_NUM_8822B)
+#define BIT_SET_TXTTIMER_MATCH_NUM_8822B(x, v) \
+ (BIT_CLEAR_TXTTIMER_MATCH_NUM_8822B(x) | \
+ BIT_TXTTIMER_MATCH_NUM_8822B(v))
#define BIT_SHIFT_TXPKT_NUM_MATCH_8822B 24
#define BIT_MASK_TXPKT_NUM_MATCH_8822B 0xf
-#define BIT_TXPKT_NUM_MATCH_8822B(x) (((x) & BIT_MASK_TXPKT_NUM_MATCH_8822B) << BIT_SHIFT_TXPKT_NUM_MATCH_8822B)
-#define BIT_GET_TXPKT_NUM_MATCH_8822B(x) (((x) >> BIT_SHIFT_TXPKT_NUM_MATCH_8822B) & BIT_MASK_TXPKT_NUM_MATCH_8822B)
-
+#define BIT_TXPKT_NUM_MATCH_8822B(x) \
+ (((x) & BIT_MASK_TXPKT_NUM_MATCH_8822B) \
+ << BIT_SHIFT_TXPKT_NUM_MATCH_8822B)
+#define BITS_TXPKT_NUM_MATCH_8822B \
+ (BIT_MASK_TXPKT_NUM_MATCH_8822B << BIT_SHIFT_TXPKT_NUM_MATCH_8822B)
+#define BIT_CLEAR_TXPKT_NUM_MATCH_8822B(x) ((x) & (~BITS_TXPKT_NUM_MATCH_8822B))
+#define BIT_GET_TXPKT_NUM_MATCH_8822B(x) \
+ (((x) >> BIT_SHIFT_TXPKT_NUM_MATCH_8822B) & \
+ BIT_MASK_TXPKT_NUM_MATCH_8822B)
+#define BIT_SET_TXPKT_NUM_MATCH_8822B(x, v) \
+ (BIT_CLEAR_TXPKT_NUM_MATCH_8822B(x) | BIT_TXPKT_NUM_MATCH_8822B(v))
#define BIT_SHIFT_RXTTIMER_MATCH_NUM_8822B 20
#define BIT_MASK_RXTTIMER_MATCH_NUM_8822B 0xf
-#define BIT_RXTTIMER_MATCH_NUM_8822B(x) (((x) & BIT_MASK_RXTTIMER_MATCH_NUM_8822B) << BIT_SHIFT_RXTTIMER_MATCH_NUM_8822B)
-#define BIT_GET_RXTTIMER_MATCH_NUM_8822B(x) (((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM_8822B) & BIT_MASK_RXTTIMER_MATCH_NUM_8822B)
-
+#define BIT_RXTTIMER_MATCH_NUM_8822B(x) \
+ (((x) & BIT_MASK_RXTTIMER_MATCH_NUM_8822B) \
+ << BIT_SHIFT_RXTTIMER_MATCH_NUM_8822B)
+#define BITS_RXTTIMER_MATCH_NUM_8822B \
+ (BIT_MASK_RXTTIMER_MATCH_NUM_8822B \
+ << BIT_SHIFT_RXTTIMER_MATCH_NUM_8822B)
+#define BIT_CLEAR_RXTTIMER_MATCH_NUM_8822B(x) \
+ ((x) & (~BITS_RXTTIMER_MATCH_NUM_8822B))
+#define BIT_GET_RXTTIMER_MATCH_NUM_8822B(x) \
+ (((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM_8822B) & \
+ BIT_MASK_RXTTIMER_MATCH_NUM_8822B)
+#define BIT_SET_RXTTIMER_MATCH_NUM_8822B(x, v) \
+ (BIT_CLEAR_RXTTIMER_MATCH_NUM_8822B(x) | \
+ BIT_RXTTIMER_MATCH_NUM_8822B(v))
#define BIT_SHIFT_RXPKT_NUM_MATCH_8822B 16
#define BIT_MASK_RXPKT_NUM_MATCH_8822B 0xf
-#define BIT_RXPKT_NUM_MATCH_8822B(x) (((x) & BIT_MASK_RXPKT_NUM_MATCH_8822B) << BIT_SHIFT_RXPKT_NUM_MATCH_8822B)
-#define BIT_GET_RXPKT_NUM_MATCH_8822B(x) (((x) >> BIT_SHIFT_RXPKT_NUM_MATCH_8822B) & BIT_MASK_RXPKT_NUM_MATCH_8822B)
-
+#define BIT_RXPKT_NUM_MATCH_8822B(x) \
+ (((x) & BIT_MASK_RXPKT_NUM_MATCH_8822B) \
+ << BIT_SHIFT_RXPKT_NUM_MATCH_8822B)
+#define BITS_RXPKT_NUM_MATCH_8822B \
+ (BIT_MASK_RXPKT_NUM_MATCH_8822B << BIT_SHIFT_RXPKT_NUM_MATCH_8822B)
+#define BIT_CLEAR_RXPKT_NUM_MATCH_8822B(x) ((x) & (~BITS_RXPKT_NUM_MATCH_8822B))
+#define BIT_GET_RXPKT_NUM_MATCH_8822B(x) \
+ (((x) >> BIT_SHIFT_RXPKT_NUM_MATCH_8822B) & \
+ BIT_MASK_RXPKT_NUM_MATCH_8822B)
+#define BIT_SET_RXPKT_NUM_MATCH_8822B(x, v) \
+ (BIT_CLEAR_RXPKT_NUM_MATCH_8822B(x) | BIT_RXPKT_NUM_MATCH_8822B(v))
#define BIT_SHIFT_MIGRATE_TIMER_8822B 0
#define BIT_MASK_MIGRATE_TIMER_8822B 0xffff
-#define BIT_MIGRATE_TIMER_8822B(x) (((x) & BIT_MASK_MIGRATE_TIMER_8822B) << BIT_SHIFT_MIGRATE_TIMER_8822B)
-#define BIT_GET_MIGRATE_TIMER_8822B(x) (((x) >> BIT_SHIFT_MIGRATE_TIMER_8822B) & BIT_MASK_MIGRATE_TIMER_8822B)
-
+#define BIT_MIGRATE_TIMER_8822B(x) \
+ (((x) & BIT_MASK_MIGRATE_TIMER_8822B) << BIT_SHIFT_MIGRATE_TIMER_8822B)
+#define BITS_MIGRATE_TIMER_8822B \
+ (BIT_MASK_MIGRATE_TIMER_8822B << BIT_SHIFT_MIGRATE_TIMER_8822B)
+#define BIT_CLEAR_MIGRATE_TIMER_8822B(x) ((x) & (~BITS_MIGRATE_TIMER_8822B))
+#define BIT_GET_MIGRATE_TIMER_8822B(x) \
+ (((x) >> BIT_SHIFT_MIGRATE_TIMER_8822B) & BIT_MASK_MIGRATE_TIMER_8822B)
+#define BIT_SET_MIGRATE_TIMER_8822B(x, v) \
+ (BIT_CLEAR_MIGRATE_TIMER_8822B(x) | BIT_MIGRATE_TIMER_8822B(v))
/* 2 REG_BCNQ_TXBD_DESA_8822B */
#define BIT_SHIFT_BCNQ_TXBD_DESA_8822B 0
#define BIT_MASK_BCNQ_TXBD_DESA_8822B 0xffffffffffffffffL
-#define BIT_BCNQ_TXBD_DESA_8822B(x) (((x) & BIT_MASK_BCNQ_TXBD_DESA_8822B) << BIT_SHIFT_BCNQ_TXBD_DESA_8822B)
-#define BIT_GET_BCNQ_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_BCNQ_TXBD_DESA_8822B) & BIT_MASK_BCNQ_TXBD_DESA_8822B)
-
+#define BIT_BCNQ_TXBD_DESA_8822B(x) \
+ (((x) & BIT_MASK_BCNQ_TXBD_DESA_8822B) \
+ << BIT_SHIFT_BCNQ_TXBD_DESA_8822B)
+#define BITS_BCNQ_TXBD_DESA_8822B \
+ (BIT_MASK_BCNQ_TXBD_DESA_8822B << BIT_SHIFT_BCNQ_TXBD_DESA_8822B)
+#define BIT_CLEAR_BCNQ_TXBD_DESA_8822B(x) ((x) & (~BITS_BCNQ_TXBD_DESA_8822B))
+#define BIT_GET_BCNQ_TXBD_DESA_8822B(x) \
+ (((x) >> BIT_SHIFT_BCNQ_TXBD_DESA_8822B) & \
+ BIT_MASK_BCNQ_TXBD_DESA_8822B)
+#define BIT_SET_BCNQ_TXBD_DESA_8822B(x, v) \
+ (BIT_CLEAR_BCNQ_TXBD_DESA_8822B(x) | BIT_BCNQ_TXBD_DESA_8822B(v))
/* 2 REG_MGQ_TXBD_DESA_8822B */
#define BIT_SHIFT_MGQ_TXBD_DESA_8822B 0
#define BIT_MASK_MGQ_TXBD_DESA_8822B 0xffffffffffffffffL
-#define BIT_MGQ_TXBD_DESA_8822B(x) (((x) & BIT_MASK_MGQ_TXBD_DESA_8822B) << BIT_SHIFT_MGQ_TXBD_DESA_8822B)
-#define BIT_GET_MGQ_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_MGQ_TXBD_DESA_8822B) & BIT_MASK_MGQ_TXBD_DESA_8822B)
-
+#define BIT_MGQ_TXBD_DESA_8822B(x) \
+ (((x) & BIT_MASK_MGQ_TXBD_DESA_8822B) << BIT_SHIFT_MGQ_TXBD_DESA_8822B)
+#define BITS_MGQ_TXBD_DESA_8822B \
+ (BIT_MASK_MGQ_TXBD_DESA_8822B << BIT_SHIFT_MGQ_TXBD_DESA_8822B)
+#define BIT_CLEAR_MGQ_TXBD_DESA_8822B(x) ((x) & (~BITS_MGQ_TXBD_DESA_8822B))
+#define BIT_GET_MGQ_TXBD_DESA_8822B(x) \
+ (((x) >> BIT_SHIFT_MGQ_TXBD_DESA_8822B) & BIT_MASK_MGQ_TXBD_DESA_8822B)
+#define BIT_SET_MGQ_TXBD_DESA_8822B(x, v) \
+ (BIT_CLEAR_MGQ_TXBD_DESA_8822B(x) | BIT_MGQ_TXBD_DESA_8822B(v))
/* 2 REG_VOQ_TXBD_DESA_8822B */
#define BIT_SHIFT_VOQ_TXBD_DESA_8822B 0
#define BIT_MASK_VOQ_TXBD_DESA_8822B 0xffffffffffffffffL
-#define BIT_VOQ_TXBD_DESA_8822B(x) (((x) & BIT_MASK_VOQ_TXBD_DESA_8822B) << BIT_SHIFT_VOQ_TXBD_DESA_8822B)
-#define BIT_GET_VOQ_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_VOQ_TXBD_DESA_8822B) & BIT_MASK_VOQ_TXBD_DESA_8822B)
-
+#define BIT_VOQ_TXBD_DESA_8822B(x) \
+ (((x) & BIT_MASK_VOQ_TXBD_DESA_8822B) << BIT_SHIFT_VOQ_TXBD_DESA_8822B)
+#define BITS_VOQ_TXBD_DESA_8822B \
+ (BIT_MASK_VOQ_TXBD_DESA_8822B << BIT_SHIFT_VOQ_TXBD_DESA_8822B)
+#define BIT_CLEAR_VOQ_TXBD_DESA_8822B(x) ((x) & (~BITS_VOQ_TXBD_DESA_8822B))
+#define BIT_GET_VOQ_TXBD_DESA_8822B(x) \
+ (((x) >> BIT_SHIFT_VOQ_TXBD_DESA_8822B) & BIT_MASK_VOQ_TXBD_DESA_8822B)
+#define BIT_SET_VOQ_TXBD_DESA_8822B(x, v) \
+ (BIT_CLEAR_VOQ_TXBD_DESA_8822B(x) | BIT_VOQ_TXBD_DESA_8822B(v))
/* 2 REG_VIQ_TXBD_DESA_8822B */
#define BIT_SHIFT_VIQ_TXBD_DESA_8822B 0
#define BIT_MASK_VIQ_TXBD_DESA_8822B 0xffffffffffffffffL
-#define BIT_VIQ_TXBD_DESA_8822B(x) (((x) & BIT_MASK_VIQ_TXBD_DESA_8822B) << BIT_SHIFT_VIQ_TXBD_DESA_8822B)
-#define BIT_GET_VIQ_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_VIQ_TXBD_DESA_8822B) & BIT_MASK_VIQ_TXBD_DESA_8822B)
-
+#define BIT_VIQ_TXBD_DESA_8822B(x) \
+ (((x) & BIT_MASK_VIQ_TXBD_DESA_8822B) << BIT_SHIFT_VIQ_TXBD_DESA_8822B)
+#define BITS_VIQ_TXBD_DESA_8822B \
+ (BIT_MASK_VIQ_TXBD_DESA_8822B << BIT_SHIFT_VIQ_TXBD_DESA_8822B)
+#define BIT_CLEAR_VIQ_TXBD_DESA_8822B(x) ((x) & (~BITS_VIQ_TXBD_DESA_8822B))
+#define BIT_GET_VIQ_TXBD_DESA_8822B(x) \
+ (((x) >> BIT_SHIFT_VIQ_TXBD_DESA_8822B) & BIT_MASK_VIQ_TXBD_DESA_8822B)
+#define BIT_SET_VIQ_TXBD_DESA_8822B(x, v) \
+ (BIT_CLEAR_VIQ_TXBD_DESA_8822B(x) | BIT_VIQ_TXBD_DESA_8822B(v))
/* 2 REG_BEQ_TXBD_DESA_8822B */
#define BIT_SHIFT_BEQ_TXBD_DESA_8822B 0
#define BIT_MASK_BEQ_TXBD_DESA_8822B 0xffffffffffffffffL
-#define BIT_BEQ_TXBD_DESA_8822B(x) (((x) & BIT_MASK_BEQ_TXBD_DESA_8822B) << BIT_SHIFT_BEQ_TXBD_DESA_8822B)
-#define BIT_GET_BEQ_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_BEQ_TXBD_DESA_8822B) & BIT_MASK_BEQ_TXBD_DESA_8822B)
-
+#define BIT_BEQ_TXBD_DESA_8822B(x) \
+ (((x) & BIT_MASK_BEQ_TXBD_DESA_8822B) << BIT_SHIFT_BEQ_TXBD_DESA_8822B)
+#define BITS_BEQ_TXBD_DESA_8822B \
+ (BIT_MASK_BEQ_TXBD_DESA_8822B << BIT_SHIFT_BEQ_TXBD_DESA_8822B)
+#define BIT_CLEAR_BEQ_TXBD_DESA_8822B(x) ((x) & (~BITS_BEQ_TXBD_DESA_8822B))
+#define BIT_GET_BEQ_TXBD_DESA_8822B(x) \
+ (((x) >> BIT_SHIFT_BEQ_TXBD_DESA_8822B) & BIT_MASK_BEQ_TXBD_DESA_8822B)
+#define BIT_SET_BEQ_TXBD_DESA_8822B(x, v) \
+ (BIT_CLEAR_BEQ_TXBD_DESA_8822B(x) | BIT_BEQ_TXBD_DESA_8822B(v))
/* 2 REG_BKQ_TXBD_DESA_8822B */
#define BIT_SHIFT_BKQ_TXBD_DESA_8822B 0
#define BIT_MASK_BKQ_TXBD_DESA_8822B 0xffffffffffffffffL
-#define BIT_BKQ_TXBD_DESA_8822B(x) (((x) & BIT_MASK_BKQ_TXBD_DESA_8822B) << BIT_SHIFT_BKQ_TXBD_DESA_8822B)
-#define BIT_GET_BKQ_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_BKQ_TXBD_DESA_8822B) & BIT_MASK_BKQ_TXBD_DESA_8822B)
-
+#define BIT_BKQ_TXBD_DESA_8822B(x) \
+ (((x) & BIT_MASK_BKQ_TXBD_DESA_8822B) << BIT_SHIFT_BKQ_TXBD_DESA_8822B)
+#define BITS_BKQ_TXBD_DESA_8822B \
+ (BIT_MASK_BKQ_TXBD_DESA_8822B << BIT_SHIFT_BKQ_TXBD_DESA_8822B)
+#define BIT_CLEAR_BKQ_TXBD_DESA_8822B(x) ((x) & (~BITS_BKQ_TXBD_DESA_8822B))
+#define BIT_GET_BKQ_TXBD_DESA_8822B(x) \
+ (((x) >> BIT_SHIFT_BKQ_TXBD_DESA_8822B) & BIT_MASK_BKQ_TXBD_DESA_8822B)
+#define BIT_SET_BKQ_TXBD_DESA_8822B(x, v) \
+ (BIT_CLEAR_BKQ_TXBD_DESA_8822B(x) | BIT_BKQ_TXBD_DESA_8822B(v))
/* 2 REG_RXQ_RXBD_DESA_8822B */
#define BIT_SHIFT_RXQ_RXBD_DESA_8822B 0
#define BIT_MASK_RXQ_RXBD_DESA_8822B 0xffffffffffffffffL
-#define BIT_RXQ_RXBD_DESA_8822B(x) (((x) & BIT_MASK_RXQ_RXBD_DESA_8822B) << BIT_SHIFT_RXQ_RXBD_DESA_8822B)
-#define BIT_GET_RXQ_RXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_RXQ_RXBD_DESA_8822B) & BIT_MASK_RXQ_RXBD_DESA_8822B)
-
+#define BIT_RXQ_RXBD_DESA_8822B(x) \
+ (((x) & BIT_MASK_RXQ_RXBD_DESA_8822B) << BIT_SHIFT_RXQ_RXBD_DESA_8822B)
+#define BITS_RXQ_RXBD_DESA_8822B \
+ (BIT_MASK_RXQ_RXBD_DESA_8822B << BIT_SHIFT_RXQ_RXBD_DESA_8822B)
+#define BIT_CLEAR_RXQ_RXBD_DESA_8822B(x) ((x) & (~BITS_RXQ_RXBD_DESA_8822B))
+#define BIT_GET_RXQ_RXBD_DESA_8822B(x) \
+ (((x) >> BIT_SHIFT_RXQ_RXBD_DESA_8822B) & BIT_MASK_RXQ_RXBD_DESA_8822B)
+#define BIT_SET_RXQ_RXBD_DESA_8822B(x, v) \
+ (BIT_CLEAR_RXQ_RXBD_DESA_8822B(x) | BIT_RXQ_RXBD_DESA_8822B(v))
/* 2 REG_HI0Q_TXBD_DESA_8822B */
#define BIT_SHIFT_HI0Q_TXBD_DESA_8822B 0
#define BIT_MASK_HI0Q_TXBD_DESA_8822B 0xffffffffffffffffL
-#define BIT_HI0Q_TXBD_DESA_8822B(x) (((x) & BIT_MASK_HI0Q_TXBD_DESA_8822B) << BIT_SHIFT_HI0Q_TXBD_DESA_8822B)
-#define BIT_GET_HI0Q_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_8822B) & BIT_MASK_HI0Q_TXBD_DESA_8822B)
-
+#define BIT_HI0Q_TXBD_DESA_8822B(x) \
+ (((x) & BIT_MASK_HI0Q_TXBD_DESA_8822B) \
+ << BIT_SHIFT_HI0Q_TXBD_DESA_8822B)
+#define BITS_HI0Q_TXBD_DESA_8822B \
+ (BIT_MASK_HI0Q_TXBD_DESA_8822B << BIT_SHIFT_HI0Q_TXBD_DESA_8822B)
+#define BIT_CLEAR_HI0Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI0Q_TXBD_DESA_8822B))
+#define BIT_GET_HI0Q_TXBD_DESA_8822B(x) \
+ (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_8822B) & \
+ BIT_MASK_HI0Q_TXBD_DESA_8822B)
+#define BIT_SET_HI0Q_TXBD_DESA_8822B(x, v) \
+ (BIT_CLEAR_HI0Q_TXBD_DESA_8822B(x) | BIT_HI0Q_TXBD_DESA_8822B(v))
/* 2 REG_HI1Q_TXBD_DESA_8822B */
#define BIT_SHIFT_HI1Q_TXBD_DESA_8822B 0
#define BIT_MASK_HI1Q_TXBD_DESA_8822B 0xffffffffffffffffL
-#define BIT_HI1Q_TXBD_DESA_8822B(x) (((x) & BIT_MASK_HI1Q_TXBD_DESA_8822B) << BIT_SHIFT_HI1Q_TXBD_DESA_8822B)
-#define BIT_GET_HI1Q_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_8822B) & BIT_MASK_HI1Q_TXBD_DESA_8822B)
-
+#define BIT_HI1Q_TXBD_DESA_8822B(x) \
+ (((x) & BIT_MASK_HI1Q_TXBD_DESA_8822B) \
+ << BIT_SHIFT_HI1Q_TXBD_DESA_8822B)
+#define BITS_HI1Q_TXBD_DESA_8822B \
+ (BIT_MASK_HI1Q_TXBD_DESA_8822B << BIT_SHIFT_HI1Q_TXBD_DESA_8822B)
+#define BIT_CLEAR_HI1Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI1Q_TXBD_DESA_8822B))
+#define BIT_GET_HI1Q_TXBD_DESA_8822B(x) \
+ (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_8822B) & \
+ BIT_MASK_HI1Q_TXBD_DESA_8822B)
+#define BIT_SET_HI1Q_TXBD_DESA_8822B(x, v) \
+ (BIT_CLEAR_HI1Q_TXBD_DESA_8822B(x) | BIT_HI1Q_TXBD_DESA_8822B(v))
/* 2 REG_HI2Q_TXBD_DESA_8822B */
#define BIT_SHIFT_HI2Q_TXBD_DESA_8822B 0
#define BIT_MASK_HI2Q_TXBD_DESA_8822B 0xffffffffffffffffL
-#define BIT_HI2Q_TXBD_DESA_8822B(x) (((x) & BIT_MASK_HI2Q_TXBD_DESA_8822B) << BIT_SHIFT_HI2Q_TXBD_DESA_8822B)
-#define BIT_GET_HI2Q_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_8822B) & BIT_MASK_HI2Q_TXBD_DESA_8822B)
-
+#define BIT_HI2Q_TXBD_DESA_8822B(x) \
+ (((x) & BIT_MASK_HI2Q_TXBD_DESA_8822B) \
+ << BIT_SHIFT_HI2Q_TXBD_DESA_8822B)
+#define BITS_HI2Q_TXBD_DESA_8822B \
+ (BIT_MASK_HI2Q_TXBD_DESA_8822B << BIT_SHIFT_HI2Q_TXBD_DESA_8822B)
+#define BIT_CLEAR_HI2Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI2Q_TXBD_DESA_8822B))
+#define BIT_GET_HI2Q_TXBD_DESA_8822B(x) \
+ (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_8822B) & \
+ BIT_MASK_HI2Q_TXBD_DESA_8822B)
+#define BIT_SET_HI2Q_TXBD_DESA_8822B(x, v) \
+ (BIT_CLEAR_HI2Q_TXBD_DESA_8822B(x) | BIT_HI2Q_TXBD_DESA_8822B(v))
/* 2 REG_HI3Q_TXBD_DESA_8822B */
#define BIT_SHIFT_HI3Q_TXBD_DESA_8822B 0
#define BIT_MASK_HI3Q_TXBD_DESA_8822B 0xffffffffffffffffL
-#define BIT_HI3Q_TXBD_DESA_8822B(x) (((x) & BIT_MASK_HI3Q_TXBD_DESA_8822B) << BIT_SHIFT_HI3Q_TXBD_DESA_8822B)
-#define BIT_GET_HI3Q_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_8822B) & BIT_MASK_HI3Q_TXBD_DESA_8822B)
-
+#define BIT_HI3Q_TXBD_DESA_8822B(x) \
+ (((x) & BIT_MASK_HI3Q_TXBD_DESA_8822B) \
+ << BIT_SHIFT_HI3Q_TXBD_DESA_8822B)
+#define BITS_HI3Q_TXBD_DESA_8822B \
+ (BIT_MASK_HI3Q_TXBD_DESA_8822B << BIT_SHIFT_HI3Q_TXBD_DESA_8822B)
+#define BIT_CLEAR_HI3Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI3Q_TXBD_DESA_8822B))
+#define BIT_GET_HI3Q_TXBD_DESA_8822B(x) \
+ (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_8822B) & \
+ BIT_MASK_HI3Q_TXBD_DESA_8822B)
+#define BIT_SET_HI3Q_TXBD_DESA_8822B(x, v) \
+ (BIT_CLEAR_HI3Q_TXBD_DESA_8822B(x) | BIT_HI3Q_TXBD_DESA_8822B(v))
/* 2 REG_HI4Q_TXBD_DESA_8822B */
#define BIT_SHIFT_HI4Q_TXBD_DESA_8822B 0
#define BIT_MASK_HI4Q_TXBD_DESA_8822B 0xffffffffffffffffL
-#define BIT_HI4Q_TXBD_DESA_8822B(x) (((x) & BIT_MASK_HI4Q_TXBD_DESA_8822B) << BIT_SHIFT_HI4Q_TXBD_DESA_8822B)
-#define BIT_GET_HI4Q_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_8822B) & BIT_MASK_HI4Q_TXBD_DESA_8822B)
-
+#define BIT_HI4Q_TXBD_DESA_8822B(x) \
+ (((x) & BIT_MASK_HI4Q_TXBD_DESA_8822B) \
+ << BIT_SHIFT_HI4Q_TXBD_DESA_8822B)
+#define BITS_HI4Q_TXBD_DESA_8822B \
+ (BIT_MASK_HI4Q_TXBD_DESA_8822B << BIT_SHIFT_HI4Q_TXBD_DESA_8822B)
+#define BIT_CLEAR_HI4Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI4Q_TXBD_DESA_8822B))
+#define BIT_GET_HI4Q_TXBD_DESA_8822B(x) \
+ (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_8822B) & \
+ BIT_MASK_HI4Q_TXBD_DESA_8822B)
+#define BIT_SET_HI4Q_TXBD_DESA_8822B(x, v) \
+ (BIT_CLEAR_HI4Q_TXBD_DESA_8822B(x) | BIT_HI4Q_TXBD_DESA_8822B(v))
/* 2 REG_HI5Q_TXBD_DESA_8822B */
#define BIT_SHIFT_HI5Q_TXBD_DESA_8822B 0
#define BIT_MASK_HI5Q_TXBD_DESA_8822B 0xffffffffffffffffL
-#define BIT_HI5Q_TXBD_DESA_8822B(x) (((x) & BIT_MASK_HI5Q_TXBD_DESA_8822B) << BIT_SHIFT_HI5Q_TXBD_DESA_8822B)
-#define BIT_GET_HI5Q_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_8822B) & BIT_MASK_HI5Q_TXBD_DESA_8822B)
-
+#define BIT_HI5Q_TXBD_DESA_8822B(x) \
+ (((x) & BIT_MASK_HI5Q_TXBD_DESA_8822B) \
+ << BIT_SHIFT_HI5Q_TXBD_DESA_8822B)
+#define BITS_HI5Q_TXBD_DESA_8822B \
+ (BIT_MASK_HI5Q_TXBD_DESA_8822B << BIT_SHIFT_HI5Q_TXBD_DESA_8822B)
+#define BIT_CLEAR_HI5Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI5Q_TXBD_DESA_8822B))
+#define BIT_GET_HI5Q_TXBD_DESA_8822B(x) \
+ (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_8822B) & \
+ BIT_MASK_HI5Q_TXBD_DESA_8822B)
+#define BIT_SET_HI5Q_TXBD_DESA_8822B(x, v) \
+ (BIT_CLEAR_HI5Q_TXBD_DESA_8822B(x) | BIT_HI5Q_TXBD_DESA_8822B(v))
/* 2 REG_HI6Q_TXBD_DESA_8822B */
#define BIT_SHIFT_HI6Q_TXBD_DESA_8822B 0
#define BIT_MASK_HI6Q_TXBD_DESA_8822B 0xffffffffffffffffL
-#define BIT_HI6Q_TXBD_DESA_8822B(x) (((x) & BIT_MASK_HI6Q_TXBD_DESA_8822B) << BIT_SHIFT_HI6Q_TXBD_DESA_8822B)
-#define BIT_GET_HI6Q_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_8822B) & BIT_MASK_HI6Q_TXBD_DESA_8822B)
-
+#define BIT_HI6Q_TXBD_DESA_8822B(x) \
+ (((x) & BIT_MASK_HI6Q_TXBD_DESA_8822B) \
+ << BIT_SHIFT_HI6Q_TXBD_DESA_8822B)
+#define BITS_HI6Q_TXBD_DESA_8822B \
+ (BIT_MASK_HI6Q_TXBD_DESA_8822B << BIT_SHIFT_HI6Q_TXBD_DESA_8822B)
+#define BIT_CLEAR_HI6Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI6Q_TXBD_DESA_8822B))
+#define BIT_GET_HI6Q_TXBD_DESA_8822B(x) \
+ (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_8822B) & \
+ BIT_MASK_HI6Q_TXBD_DESA_8822B)
+#define BIT_SET_HI6Q_TXBD_DESA_8822B(x, v) \
+ (BIT_CLEAR_HI6Q_TXBD_DESA_8822B(x) | BIT_HI6Q_TXBD_DESA_8822B(v))
/* 2 REG_HI7Q_TXBD_DESA_8822B */
#define BIT_SHIFT_HI7Q_TXBD_DESA_8822B 0
#define BIT_MASK_HI7Q_TXBD_DESA_8822B 0xffffffffffffffffL
-#define BIT_HI7Q_TXBD_DESA_8822B(x) (((x) & BIT_MASK_HI7Q_TXBD_DESA_8822B) << BIT_SHIFT_HI7Q_TXBD_DESA_8822B)
-#define BIT_GET_HI7Q_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_8822B) & BIT_MASK_HI7Q_TXBD_DESA_8822B)
-
+#define BIT_HI7Q_TXBD_DESA_8822B(x) \
+ (((x) & BIT_MASK_HI7Q_TXBD_DESA_8822B) \
+ << BIT_SHIFT_HI7Q_TXBD_DESA_8822B)
+#define BITS_HI7Q_TXBD_DESA_8822B \
+ (BIT_MASK_HI7Q_TXBD_DESA_8822B << BIT_SHIFT_HI7Q_TXBD_DESA_8822B)
+#define BIT_CLEAR_HI7Q_TXBD_DESA_8822B(x) ((x) & (~BITS_HI7Q_TXBD_DESA_8822B))
+#define BIT_GET_HI7Q_TXBD_DESA_8822B(x) \
+ (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_8822B) & \
+ BIT_MASK_HI7Q_TXBD_DESA_8822B)
+#define BIT_SET_HI7Q_TXBD_DESA_8822B(x, v) \
+ (BIT_CLEAR_HI7Q_TXBD_DESA_8822B(x) | BIT_HI7Q_TXBD_DESA_8822B(v))
/* 2 REG_MGQ_TXBD_NUM_8822B */
#define BIT_PCIE_MGQ_FLAG_8822B BIT(14)
#define BIT_SHIFT_MGQ_DESC_MODE_8822B 12
#define BIT_MASK_MGQ_DESC_MODE_8822B 0x3
-#define BIT_MGQ_DESC_MODE_8822B(x) (((x) & BIT_MASK_MGQ_DESC_MODE_8822B) << BIT_SHIFT_MGQ_DESC_MODE_8822B)
-#define BIT_GET_MGQ_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_MGQ_DESC_MODE_8822B) & BIT_MASK_MGQ_DESC_MODE_8822B)
-
+#define BIT_MGQ_DESC_MODE_8822B(x) \
+ (((x) & BIT_MASK_MGQ_DESC_MODE_8822B) << BIT_SHIFT_MGQ_DESC_MODE_8822B)
+#define BITS_MGQ_DESC_MODE_8822B \
+ (BIT_MASK_MGQ_DESC_MODE_8822B << BIT_SHIFT_MGQ_DESC_MODE_8822B)
+#define BIT_CLEAR_MGQ_DESC_MODE_8822B(x) ((x) & (~BITS_MGQ_DESC_MODE_8822B))
+#define BIT_GET_MGQ_DESC_MODE_8822B(x) \
+ (((x) >> BIT_SHIFT_MGQ_DESC_MODE_8822B) & BIT_MASK_MGQ_DESC_MODE_8822B)
+#define BIT_SET_MGQ_DESC_MODE_8822B(x, v) \
+ (BIT_CLEAR_MGQ_DESC_MODE_8822B(x) | BIT_MGQ_DESC_MODE_8822B(v))
#define BIT_SHIFT_MGQ_DESC_NUM_8822B 0
#define BIT_MASK_MGQ_DESC_NUM_8822B 0xfff
-#define BIT_MGQ_DESC_NUM_8822B(x) (((x) & BIT_MASK_MGQ_DESC_NUM_8822B) << BIT_SHIFT_MGQ_DESC_NUM_8822B)
-#define BIT_GET_MGQ_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_MGQ_DESC_NUM_8822B) & BIT_MASK_MGQ_DESC_NUM_8822B)
-
+#define BIT_MGQ_DESC_NUM_8822B(x) \
+ (((x) & BIT_MASK_MGQ_DESC_NUM_8822B) << BIT_SHIFT_MGQ_DESC_NUM_8822B)
+#define BITS_MGQ_DESC_NUM_8822B \
+ (BIT_MASK_MGQ_DESC_NUM_8822B << BIT_SHIFT_MGQ_DESC_NUM_8822B)
+#define BIT_CLEAR_MGQ_DESC_NUM_8822B(x) ((x) & (~BITS_MGQ_DESC_NUM_8822B))
+#define BIT_GET_MGQ_DESC_NUM_8822B(x) \
+ (((x) >> BIT_SHIFT_MGQ_DESC_NUM_8822B) & BIT_MASK_MGQ_DESC_NUM_8822B)
+#define BIT_SET_MGQ_DESC_NUM_8822B(x, v) \
+ (BIT_CLEAR_MGQ_DESC_NUM_8822B(x) | BIT_MGQ_DESC_NUM_8822B(v))
/* 2 REG_RX_RXBD_NUM_8822B */
#define BIT_SYS_32_64_8822B BIT(15)
#define BIT_SHIFT_BCNQ_DESC_MODE_8822B 13
#define BIT_MASK_BCNQ_DESC_MODE_8822B 0x3
-#define BIT_BCNQ_DESC_MODE_8822B(x) (((x) & BIT_MASK_BCNQ_DESC_MODE_8822B) << BIT_SHIFT_BCNQ_DESC_MODE_8822B)
-#define BIT_GET_BCNQ_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_BCNQ_DESC_MODE_8822B) & BIT_MASK_BCNQ_DESC_MODE_8822B)
+#define BIT_BCNQ_DESC_MODE_8822B(x) \
+ (((x) & BIT_MASK_BCNQ_DESC_MODE_8822B) \
+ << BIT_SHIFT_BCNQ_DESC_MODE_8822B)
+#define BITS_BCNQ_DESC_MODE_8822B \
+ (BIT_MASK_BCNQ_DESC_MODE_8822B << BIT_SHIFT_BCNQ_DESC_MODE_8822B)
+#define BIT_CLEAR_BCNQ_DESC_MODE_8822B(x) ((x) & (~BITS_BCNQ_DESC_MODE_8822B))
+#define BIT_GET_BCNQ_DESC_MODE_8822B(x) \
+ (((x) >> BIT_SHIFT_BCNQ_DESC_MODE_8822B) & \
+ BIT_MASK_BCNQ_DESC_MODE_8822B)
+#define BIT_SET_BCNQ_DESC_MODE_8822B(x, v) \
+ (BIT_CLEAR_BCNQ_DESC_MODE_8822B(x) | BIT_BCNQ_DESC_MODE_8822B(v))
#define BIT_PCIE_BCNQ_FLAG_8822B BIT(12)
#define BIT_SHIFT_RXQ_DESC_NUM_8822B 0
#define BIT_MASK_RXQ_DESC_NUM_8822B 0xfff
-#define BIT_RXQ_DESC_NUM_8822B(x) (((x) & BIT_MASK_RXQ_DESC_NUM_8822B) << BIT_SHIFT_RXQ_DESC_NUM_8822B)
-#define BIT_GET_RXQ_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_RXQ_DESC_NUM_8822B) & BIT_MASK_RXQ_DESC_NUM_8822B)
-
+#define BIT_RXQ_DESC_NUM_8822B(x) \
+ (((x) & BIT_MASK_RXQ_DESC_NUM_8822B) << BIT_SHIFT_RXQ_DESC_NUM_8822B)
+#define BITS_RXQ_DESC_NUM_8822B \
+ (BIT_MASK_RXQ_DESC_NUM_8822B << BIT_SHIFT_RXQ_DESC_NUM_8822B)
+#define BIT_CLEAR_RXQ_DESC_NUM_8822B(x) ((x) & (~BITS_RXQ_DESC_NUM_8822B))
+#define BIT_GET_RXQ_DESC_NUM_8822B(x) \
+ (((x) >> BIT_SHIFT_RXQ_DESC_NUM_8822B) & BIT_MASK_RXQ_DESC_NUM_8822B)
+#define BIT_SET_RXQ_DESC_NUM_8822B(x, v) \
+ (BIT_CLEAR_RXQ_DESC_NUM_8822B(x) | BIT_RXQ_DESC_NUM_8822B(v))
/* 2 REG_VOQ_TXBD_NUM_8822B */
#define BIT_PCIE_VOQ_FLAG_8822B BIT(14)
#define BIT_SHIFT_VOQ_DESC_MODE_8822B 12
#define BIT_MASK_VOQ_DESC_MODE_8822B 0x3
-#define BIT_VOQ_DESC_MODE_8822B(x) (((x) & BIT_MASK_VOQ_DESC_MODE_8822B) << BIT_SHIFT_VOQ_DESC_MODE_8822B)
-#define BIT_GET_VOQ_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_VOQ_DESC_MODE_8822B) & BIT_MASK_VOQ_DESC_MODE_8822B)
-
+#define BIT_VOQ_DESC_MODE_8822B(x) \
+ (((x) & BIT_MASK_VOQ_DESC_MODE_8822B) << BIT_SHIFT_VOQ_DESC_MODE_8822B)
+#define BITS_VOQ_DESC_MODE_8822B \
+ (BIT_MASK_VOQ_DESC_MODE_8822B << BIT_SHIFT_VOQ_DESC_MODE_8822B)
+#define BIT_CLEAR_VOQ_DESC_MODE_8822B(x) ((x) & (~BITS_VOQ_DESC_MODE_8822B))
+#define BIT_GET_VOQ_DESC_MODE_8822B(x) \
+ (((x) >> BIT_SHIFT_VOQ_DESC_MODE_8822B) & BIT_MASK_VOQ_DESC_MODE_8822B)
+#define BIT_SET_VOQ_DESC_MODE_8822B(x, v) \
+ (BIT_CLEAR_VOQ_DESC_MODE_8822B(x) | BIT_VOQ_DESC_MODE_8822B(v))
#define BIT_SHIFT_VOQ_DESC_NUM_8822B 0
#define BIT_MASK_VOQ_DESC_NUM_8822B 0xfff
-#define BIT_VOQ_DESC_NUM_8822B(x) (((x) & BIT_MASK_VOQ_DESC_NUM_8822B) << BIT_SHIFT_VOQ_DESC_NUM_8822B)
-#define BIT_GET_VOQ_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_VOQ_DESC_NUM_8822B) & BIT_MASK_VOQ_DESC_NUM_8822B)
-
+#define BIT_VOQ_DESC_NUM_8822B(x) \
+ (((x) & BIT_MASK_VOQ_DESC_NUM_8822B) << BIT_SHIFT_VOQ_DESC_NUM_8822B)
+#define BITS_VOQ_DESC_NUM_8822B \
+ (BIT_MASK_VOQ_DESC_NUM_8822B << BIT_SHIFT_VOQ_DESC_NUM_8822B)
+#define BIT_CLEAR_VOQ_DESC_NUM_8822B(x) ((x) & (~BITS_VOQ_DESC_NUM_8822B))
+#define BIT_GET_VOQ_DESC_NUM_8822B(x) \
+ (((x) >> BIT_SHIFT_VOQ_DESC_NUM_8822B) & BIT_MASK_VOQ_DESC_NUM_8822B)
+#define BIT_SET_VOQ_DESC_NUM_8822B(x, v) \
+ (BIT_CLEAR_VOQ_DESC_NUM_8822B(x) | BIT_VOQ_DESC_NUM_8822B(v))
/* 2 REG_VIQ_TXBD_NUM_8822B */
#define BIT_PCIE_VIQ_FLAG_8822B BIT(14)
#define BIT_SHIFT_VIQ_DESC_MODE_8822B 12
#define BIT_MASK_VIQ_DESC_MODE_8822B 0x3
-#define BIT_VIQ_DESC_MODE_8822B(x) (((x) & BIT_MASK_VIQ_DESC_MODE_8822B) << BIT_SHIFT_VIQ_DESC_MODE_8822B)
-#define BIT_GET_VIQ_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_VIQ_DESC_MODE_8822B) & BIT_MASK_VIQ_DESC_MODE_8822B)
-
+#define BIT_VIQ_DESC_MODE_8822B(x) \
+ (((x) & BIT_MASK_VIQ_DESC_MODE_8822B) << BIT_SHIFT_VIQ_DESC_MODE_8822B)
+#define BITS_VIQ_DESC_MODE_8822B \
+ (BIT_MASK_VIQ_DESC_MODE_8822B << BIT_SHIFT_VIQ_DESC_MODE_8822B)
+#define BIT_CLEAR_VIQ_DESC_MODE_8822B(x) ((x) & (~BITS_VIQ_DESC_MODE_8822B))
+#define BIT_GET_VIQ_DESC_MODE_8822B(x) \
+ (((x) >> BIT_SHIFT_VIQ_DESC_MODE_8822B) & BIT_MASK_VIQ_DESC_MODE_8822B)
+#define BIT_SET_VIQ_DESC_MODE_8822B(x, v) \
+ (BIT_CLEAR_VIQ_DESC_MODE_8822B(x) | BIT_VIQ_DESC_MODE_8822B(v))
#define BIT_SHIFT_VIQ_DESC_NUM_8822B 0
#define BIT_MASK_VIQ_DESC_NUM_8822B 0xfff
-#define BIT_VIQ_DESC_NUM_8822B(x) (((x) & BIT_MASK_VIQ_DESC_NUM_8822B) << BIT_SHIFT_VIQ_DESC_NUM_8822B)
-#define BIT_GET_VIQ_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_VIQ_DESC_NUM_8822B) & BIT_MASK_VIQ_DESC_NUM_8822B)
-
+#define BIT_VIQ_DESC_NUM_8822B(x) \
+ (((x) & BIT_MASK_VIQ_DESC_NUM_8822B) << BIT_SHIFT_VIQ_DESC_NUM_8822B)
+#define BITS_VIQ_DESC_NUM_8822B \
+ (BIT_MASK_VIQ_DESC_NUM_8822B << BIT_SHIFT_VIQ_DESC_NUM_8822B)
+#define BIT_CLEAR_VIQ_DESC_NUM_8822B(x) ((x) & (~BITS_VIQ_DESC_NUM_8822B))
+#define BIT_GET_VIQ_DESC_NUM_8822B(x) \
+ (((x) >> BIT_SHIFT_VIQ_DESC_NUM_8822B) & BIT_MASK_VIQ_DESC_NUM_8822B)
+#define BIT_SET_VIQ_DESC_NUM_8822B(x, v) \
+ (BIT_CLEAR_VIQ_DESC_NUM_8822B(x) | BIT_VIQ_DESC_NUM_8822B(v))
/* 2 REG_BEQ_TXBD_NUM_8822B */
#define BIT_PCIE_BEQ_FLAG_8822B BIT(14)
#define BIT_SHIFT_BEQ_DESC_MODE_8822B 12
#define BIT_MASK_BEQ_DESC_MODE_8822B 0x3
-#define BIT_BEQ_DESC_MODE_8822B(x) (((x) & BIT_MASK_BEQ_DESC_MODE_8822B) << BIT_SHIFT_BEQ_DESC_MODE_8822B)
-#define BIT_GET_BEQ_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_BEQ_DESC_MODE_8822B) & BIT_MASK_BEQ_DESC_MODE_8822B)
-
+#define BIT_BEQ_DESC_MODE_8822B(x) \
+ (((x) & BIT_MASK_BEQ_DESC_MODE_8822B) << BIT_SHIFT_BEQ_DESC_MODE_8822B)
+#define BITS_BEQ_DESC_MODE_8822B \
+ (BIT_MASK_BEQ_DESC_MODE_8822B << BIT_SHIFT_BEQ_DESC_MODE_8822B)
+#define BIT_CLEAR_BEQ_DESC_MODE_8822B(x) ((x) & (~BITS_BEQ_DESC_MODE_8822B))
+#define BIT_GET_BEQ_DESC_MODE_8822B(x) \
+ (((x) >> BIT_SHIFT_BEQ_DESC_MODE_8822B) & BIT_MASK_BEQ_DESC_MODE_8822B)
+#define BIT_SET_BEQ_DESC_MODE_8822B(x, v) \
+ (BIT_CLEAR_BEQ_DESC_MODE_8822B(x) | BIT_BEQ_DESC_MODE_8822B(v))
#define BIT_SHIFT_BEQ_DESC_NUM_8822B 0
#define BIT_MASK_BEQ_DESC_NUM_8822B 0xfff
-#define BIT_BEQ_DESC_NUM_8822B(x) (((x) & BIT_MASK_BEQ_DESC_NUM_8822B) << BIT_SHIFT_BEQ_DESC_NUM_8822B)
-#define BIT_GET_BEQ_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_BEQ_DESC_NUM_8822B) & BIT_MASK_BEQ_DESC_NUM_8822B)
-
+#define BIT_BEQ_DESC_NUM_8822B(x) \
+ (((x) & BIT_MASK_BEQ_DESC_NUM_8822B) << BIT_SHIFT_BEQ_DESC_NUM_8822B)
+#define BITS_BEQ_DESC_NUM_8822B \
+ (BIT_MASK_BEQ_DESC_NUM_8822B << BIT_SHIFT_BEQ_DESC_NUM_8822B)
+#define BIT_CLEAR_BEQ_DESC_NUM_8822B(x) ((x) & (~BITS_BEQ_DESC_NUM_8822B))
+#define BIT_GET_BEQ_DESC_NUM_8822B(x) \
+ (((x) >> BIT_SHIFT_BEQ_DESC_NUM_8822B) & BIT_MASK_BEQ_DESC_NUM_8822B)
+#define BIT_SET_BEQ_DESC_NUM_8822B(x, v) \
+ (BIT_CLEAR_BEQ_DESC_NUM_8822B(x) | BIT_BEQ_DESC_NUM_8822B(v))
/* 2 REG_BKQ_TXBD_NUM_8822B */
#define BIT_PCIE_BKQ_FLAG_8822B BIT(14)
#define BIT_SHIFT_BKQ_DESC_MODE_8822B 12
#define BIT_MASK_BKQ_DESC_MODE_8822B 0x3
-#define BIT_BKQ_DESC_MODE_8822B(x) (((x) & BIT_MASK_BKQ_DESC_MODE_8822B) << BIT_SHIFT_BKQ_DESC_MODE_8822B)
-#define BIT_GET_BKQ_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_BKQ_DESC_MODE_8822B) & BIT_MASK_BKQ_DESC_MODE_8822B)
-
+#define BIT_BKQ_DESC_MODE_8822B(x) \
+ (((x) & BIT_MASK_BKQ_DESC_MODE_8822B) << BIT_SHIFT_BKQ_DESC_MODE_8822B)
+#define BITS_BKQ_DESC_MODE_8822B \
+ (BIT_MASK_BKQ_DESC_MODE_8822B << BIT_SHIFT_BKQ_DESC_MODE_8822B)
+#define BIT_CLEAR_BKQ_DESC_MODE_8822B(x) ((x) & (~BITS_BKQ_DESC_MODE_8822B))
+#define BIT_GET_BKQ_DESC_MODE_8822B(x) \
+ (((x) >> BIT_SHIFT_BKQ_DESC_MODE_8822B) & BIT_MASK_BKQ_DESC_MODE_8822B)
+#define BIT_SET_BKQ_DESC_MODE_8822B(x, v) \
+ (BIT_CLEAR_BKQ_DESC_MODE_8822B(x) | BIT_BKQ_DESC_MODE_8822B(v))
#define BIT_SHIFT_BKQ_DESC_NUM_8822B 0
#define BIT_MASK_BKQ_DESC_NUM_8822B 0xfff
-#define BIT_BKQ_DESC_NUM_8822B(x) (((x) & BIT_MASK_BKQ_DESC_NUM_8822B) << BIT_SHIFT_BKQ_DESC_NUM_8822B)
-#define BIT_GET_BKQ_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_BKQ_DESC_NUM_8822B) & BIT_MASK_BKQ_DESC_NUM_8822B)
-
+#define BIT_BKQ_DESC_NUM_8822B(x) \
+ (((x) & BIT_MASK_BKQ_DESC_NUM_8822B) << BIT_SHIFT_BKQ_DESC_NUM_8822B)
+#define BITS_BKQ_DESC_NUM_8822B \
+ (BIT_MASK_BKQ_DESC_NUM_8822B << BIT_SHIFT_BKQ_DESC_NUM_8822B)
+#define BIT_CLEAR_BKQ_DESC_NUM_8822B(x) ((x) & (~BITS_BKQ_DESC_NUM_8822B))
+#define BIT_GET_BKQ_DESC_NUM_8822B(x) \
+ (((x) >> BIT_SHIFT_BKQ_DESC_NUM_8822B) & BIT_MASK_BKQ_DESC_NUM_8822B)
+#define BIT_SET_BKQ_DESC_NUM_8822B(x, v) \
+ (BIT_CLEAR_BKQ_DESC_NUM_8822B(x) | BIT_BKQ_DESC_NUM_8822B(v))
/* 2 REG_HI0Q_TXBD_NUM_8822B */
#define BIT_HI0Q_FLAG_8822B BIT(14)
#define BIT_SHIFT_HI0Q_DESC_MODE_8822B 12
#define BIT_MASK_HI0Q_DESC_MODE_8822B 0x3
-#define BIT_HI0Q_DESC_MODE_8822B(x) (((x) & BIT_MASK_HI0Q_DESC_MODE_8822B) << BIT_SHIFT_HI0Q_DESC_MODE_8822B)
-#define BIT_GET_HI0Q_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_HI0Q_DESC_MODE_8822B) & BIT_MASK_HI0Q_DESC_MODE_8822B)
-
+#define BIT_HI0Q_DESC_MODE_8822B(x) \
+ (((x) & BIT_MASK_HI0Q_DESC_MODE_8822B) \
+ << BIT_SHIFT_HI0Q_DESC_MODE_8822B)
+#define BITS_HI0Q_DESC_MODE_8822B \
+ (BIT_MASK_HI0Q_DESC_MODE_8822B << BIT_SHIFT_HI0Q_DESC_MODE_8822B)
+#define BIT_CLEAR_HI0Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI0Q_DESC_MODE_8822B))
+#define BIT_GET_HI0Q_DESC_MODE_8822B(x) \
+ (((x) >> BIT_SHIFT_HI0Q_DESC_MODE_8822B) & \
+ BIT_MASK_HI0Q_DESC_MODE_8822B)
+#define BIT_SET_HI0Q_DESC_MODE_8822B(x, v) \
+ (BIT_CLEAR_HI0Q_DESC_MODE_8822B(x) | BIT_HI0Q_DESC_MODE_8822B(v))
#define BIT_SHIFT_HI0Q_DESC_NUM_8822B 0
#define BIT_MASK_HI0Q_DESC_NUM_8822B 0xfff
-#define BIT_HI0Q_DESC_NUM_8822B(x) (((x) & BIT_MASK_HI0Q_DESC_NUM_8822B) << BIT_SHIFT_HI0Q_DESC_NUM_8822B)
-#define BIT_GET_HI0Q_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_HI0Q_DESC_NUM_8822B) & BIT_MASK_HI0Q_DESC_NUM_8822B)
-
+#define BIT_HI0Q_DESC_NUM_8822B(x) \
+ (((x) & BIT_MASK_HI0Q_DESC_NUM_8822B) << BIT_SHIFT_HI0Q_DESC_NUM_8822B)
+#define BITS_HI0Q_DESC_NUM_8822B \
+ (BIT_MASK_HI0Q_DESC_NUM_8822B << BIT_SHIFT_HI0Q_DESC_NUM_8822B)
+#define BIT_CLEAR_HI0Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI0Q_DESC_NUM_8822B))
+#define BIT_GET_HI0Q_DESC_NUM_8822B(x) \
+ (((x) >> BIT_SHIFT_HI0Q_DESC_NUM_8822B) & BIT_MASK_HI0Q_DESC_NUM_8822B)
+#define BIT_SET_HI0Q_DESC_NUM_8822B(x, v) \
+ (BIT_CLEAR_HI0Q_DESC_NUM_8822B(x) | BIT_HI0Q_DESC_NUM_8822B(v))
/* 2 REG_HI1Q_TXBD_NUM_8822B */
#define BIT_HI1Q_FLAG_8822B BIT(14)
#define BIT_SHIFT_HI1Q_DESC_MODE_8822B 12
#define BIT_MASK_HI1Q_DESC_MODE_8822B 0x3
-#define BIT_HI1Q_DESC_MODE_8822B(x) (((x) & BIT_MASK_HI1Q_DESC_MODE_8822B) << BIT_SHIFT_HI1Q_DESC_MODE_8822B)
-#define BIT_GET_HI1Q_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_HI1Q_DESC_MODE_8822B) & BIT_MASK_HI1Q_DESC_MODE_8822B)
-
+#define BIT_HI1Q_DESC_MODE_8822B(x) \
+ (((x) & BIT_MASK_HI1Q_DESC_MODE_8822B) \
+ << BIT_SHIFT_HI1Q_DESC_MODE_8822B)
+#define BITS_HI1Q_DESC_MODE_8822B \
+ (BIT_MASK_HI1Q_DESC_MODE_8822B << BIT_SHIFT_HI1Q_DESC_MODE_8822B)
+#define BIT_CLEAR_HI1Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI1Q_DESC_MODE_8822B))
+#define BIT_GET_HI1Q_DESC_MODE_8822B(x) \
+ (((x) >> BIT_SHIFT_HI1Q_DESC_MODE_8822B) & \
+ BIT_MASK_HI1Q_DESC_MODE_8822B)
+#define BIT_SET_HI1Q_DESC_MODE_8822B(x, v) \
+ (BIT_CLEAR_HI1Q_DESC_MODE_8822B(x) | BIT_HI1Q_DESC_MODE_8822B(v))
#define BIT_SHIFT_HI1Q_DESC_NUM_8822B 0
#define BIT_MASK_HI1Q_DESC_NUM_8822B 0xfff
-#define BIT_HI1Q_DESC_NUM_8822B(x) (((x) & BIT_MASK_HI1Q_DESC_NUM_8822B) << BIT_SHIFT_HI1Q_DESC_NUM_8822B)
-#define BIT_GET_HI1Q_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_HI1Q_DESC_NUM_8822B) & BIT_MASK_HI1Q_DESC_NUM_8822B)
-
+#define BIT_HI1Q_DESC_NUM_8822B(x) \
+ (((x) & BIT_MASK_HI1Q_DESC_NUM_8822B) << BIT_SHIFT_HI1Q_DESC_NUM_8822B)
+#define BITS_HI1Q_DESC_NUM_8822B \
+ (BIT_MASK_HI1Q_DESC_NUM_8822B << BIT_SHIFT_HI1Q_DESC_NUM_8822B)
+#define BIT_CLEAR_HI1Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI1Q_DESC_NUM_8822B))
+#define BIT_GET_HI1Q_DESC_NUM_8822B(x) \
+ (((x) >> BIT_SHIFT_HI1Q_DESC_NUM_8822B) & BIT_MASK_HI1Q_DESC_NUM_8822B)
+#define BIT_SET_HI1Q_DESC_NUM_8822B(x, v) \
+ (BIT_CLEAR_HI1Q_DESC_NUM_8822B(x) | BIT_HI1Q_DESC_NUM_8822B(v))
/* 2 REG_HI2Q_TXBD_NUM_8822B */
#define BIT_HI2Q_FLAG_8822B BIT(14)
#define BIT_SHIFT_HI2Q_DESC_MODE_8822B 12
#define BIT_MASK_HI2Q_DESC_MODE_8822B 0x3
-#define BIT_HI2Q_DESC_MODE_8822B(x) (((x) & BIT_MASK_HI2Q_DESC_MODE_8822B) << BIT_SHIFT_HI2Q_DESC_MODE_8822B)
-#define BIT_GET_HI2Q_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_HI2Q_DESC_MODE_8822B) & BIT_MASK_HI2Q_DESC_MODE_8822B)
-
+#define BIT_HI2Q_DESC_MODE_8822B(x) \
+ (((x) & BIT_MASK_HI2Q_DESC_MODE_8822B) \
+ << BIT_SHIFT_HI2Q_DESC_MODE_8822B)
+#define BITS_HI2Q_DESC_MODE_8822B \
+ (BIT_MASK_HI2Q_DESC_MODE_8822B << BIT_SHIFT_HI2Q_DESC_MODE_8822B)
+#define BIT_CLEAR_HI2Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI2Q_DESC_MODE_8822B))
+#define BIT_GET_HI2Q_DESC_MODE_8822B(x) \
+ (((x) >> BIT_SHIFT_HI2Q_DESC_MODE_8822B) & \
+ BIT_MASK_HI2Q_DESC_MODE_8822B)
+#define BIT_SET_HI2Q_DESC_MODE_8822B(x, v) \
+ (BIT_CLEAR_HI2Q_DESC_MODE_8822B(x) | BIT_HI2Q_DESC_MODE_8822B(v))
#define BIT_SHIFT_HI2Q_DESC_NUM_8822B 0
#define BIT_MASK_HI2Q_DESC_NUM_8822B 0xfff
-#define BIT_HI2Q_DESC_NUM_8822B(x) (((x) & BIT_MASK_HI2Q_DESC_NUM_8822B) << BIT_SHIFT_HI2Q_DESC_NUM_8822B)
-#define BIT_GET_HI2Q_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_HI2Q_DESC_NUM_8822B) & BIT_MASK_HI2Q_DESC_NUM_8822B)
-
+#define BIT_HI2Q_DESC_NUM_8822B(x) \
+ (((x) & BIT_MASK_HI2Q_DESC_NUM_8822B) << BIT_SHIFT_HI2Q_DESC_NUM_8822B)
+#define BITS_HI2Q_DESC_NUM_8822B \
+ (BIT_MASK_HI2Q_DESC_NUM_8822B << BIT_SHIFT_HI2Q_DESC_NUM_8822B)
+#define BIT_CLEAR_HI2Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI2Q_DESC_NUM_8822B))
+#define BIT_GET_HI2Q_DESC_NUM_8822B(x) \
+ (((x) >> BIT_SHIFT_HI2Q_DESC_NUM_8822B) & BIT_MASK_HI2Q_DESC_NUM_8822B)
+#define BIT_SET_HI2Q_DESC_NUM_8822B(x, v) \
+ (BIT_CLEAR_HI2Q_DESC_NUM_8822B(x) | BIT_HI2Q_DESC_NUM_8822B(v))
/* 2 REG_HI3Q_TXBD_NUM_8822B */
#define BIT_HI3Q_FLAG_8822B BIT(14)
#define BIT_SHIFT_HI3Q_DESC_MODE_8822B 12
#define BIT_MASK_HI3Q_DESC_MODE_8822B 0x3
-#define BIT_HI3Q_DESC_MODE_8822B(x) (((x) & BIT_MASK_HI3Q_DESC_MODE_8822B) << BIT_SHIFT_HI3Q_DESC_MODE_8822B)
-#define BIT_GET_HI3Q_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_HI3Q_DESC_MODE_8822B) & BIT_MASK_HI3Q_DESC_MODE_8822B)
-
+#define BIT_HI3Q_DESC_MODE_8822B(x) \
+ (((x) & BIT_MASK_HI3Q_DESC_MODE_8822B) \
+ << BIT_SHIFT_HI3Q_DESC_MODE_8822B)
+#define BITS_HI3Q_DESC_MODE_8822B \
+ (BIT_MASK_HI3Q_DESC_MODE_8822B << BIT_SHIFT_HI3Q_DESC_MODE_8822B)
+#define BIT_CLEAR_HI3Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI3Q_DESC_MODE_8822B))
+#define BIT_GET_HI3Q_DESC_MODE_8822B(x) \
+ (((x) >> BIT_SHIFT_HI3Q_DESC_MODE_8822B) & \
+ BIT_MASK_HI3Q_DESC_MODE_8822B)
+#define BIT_SET_HI3Q_DESC_MODE_8822B(x, v) \
+ (BIT_CLEAR_HI3Q_DESC_MODE_8822B(x) | BIT_HI3Q_DESC_MODE_8822B(v))
#define BIT_SHIFT_HI3Q_DESC_NUM_8822B 0
#define BIT_MASK_HI3Q_DESC_NUM_8822B 0xfff
-#define BIT_HI3Q_DESC_NUM_8822B(x) (((x) & BIT_MASK_HI3Q_DESC_NUM_8822B) << BIT_SHIFT_HI3Q_DESC_NUM_8822B)
-#define BIT_GET_HI3Q_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_HI3Q_DESC_NUM_8822B) & BIT_MASK_HI3Q_DESC_NUM_8822B)
-
+#define BIT_HI3Q_DESC_NUM_8822B(x) \
+ (((x) & BIT_MASK_HI3Q_DESC_NUM_8822B) << BIT_SHIFT_HI3Q_DESC_NUM_8822B)
+#define BITS_HI3Q_DESC_NUM_8822B \
+ (BIT_MASK_HI3Q_DESC_NUM_8822B << BIT_SHIFT_HI3Q_DESC_NUM_8822B)
+#define BIT_CLEAR_HI3Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI3Q_DESC_NUM_8822B))
+#define BIT_GET_HI3Q_DESC_NUM_8822B(x) \
+ (((x) >> BIT_SHIFT_HI3Q_DESC_NUM_8822B) & BIT_MASK_HI3Q_DESC_NUM_8822B)
+#define BIT_SET_HI3Q_DESC_NUM_8822B(x, v) \
+ (BIT_CLEAR_HI3Q_DESC_NUM_8822B(x) | BIT_HI3Q_DESC_NUM_8822B(v))
/* 2 REG_HI4Q_TXBD_NUM_8822B */
#define BIT_HI4Q_FLAG_8822B BIT(14)
#define BIT_SHIFT_HI4Q_DESC_MODE_8822B 12
#define BIT_MASK_HI4Q_DESC_MODE_8822B 0x3
-#define BIT_HI4Q_DESC_MODE_8822B(x) (((x) & BIT_MASK_HI4Q_DESC_MODE_8822B) << BIT_SHIFT_HI4Q_DESC_MODE_8822B)
-#define BIT_GET_HI4Q_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_HI4Q_DESC_MODE_8822B) & BIT_MASK_HI4Q_DESC_MODE_8822B)
-
+#define BIT_HI4Q_DESC_MODE_8822B(x) \
+ (((x) & BIT_MASK_HI4Q_DESC_MODE_8822B) \
+ << BIT_SHIFT_HI4Q_DESC_MODE_8822B)
+#define BITS_HI4Q_DESC_MODE_8822B \
+ (BIT_MASK_HI4Q_DESC_MODE_8822B << BIT_SHIFT_HI4Q_DESC_MODE_8822B)
+#define BIT_CLEAR_HI4Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI4Q_DESC_MODE_8822B))
+#define BIT_GET_HI4Q_DESC_MODE_8822B(x) \
+ (((x) >> BIT_SHIFT_HI4Q_DESC_MODE_8822B) & \
+ BIT_MASK_HI4Q_DESC_MODE_8822B)
+#define BIT_SET_HI4Q_DESC_MODE_8822B(x, v) \
+ (BIT_CLEAR_HI4Q_DESC_MODE_8822B(x) | BIT_HI4Q_DESC_MODE_8822B(v))
#define BIT_SHIFT_HI4Q_DESC_NUM_8822B 0
#define BIT_MASK_HI4Q_DESC_NUM_8822B 0xfff
-#define BIT_HI4Q_DESC_NUM_8822B(x) (((x) & BIT_MASK_HI4Q_DESC_NUM_8822B) << BIT_SHIFT_HI4Q_DESC_NUM_8822B)
-#define BIT_GET_HI4Q_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_HI4Q_DESC_NUM_8822B) & BIT_MASK_HI4Q_DESC_NUM_8822B)
-
+#define BIT_HI4Q_DESC_NUM_8822B(x) \
+ (((x) & BIT_MASK_HI4Q_DESC_NUM_8822B) << BIT_SHIFT_HI4Q_DESC_NUM_8822B)
+#define BITS_HI4Q_DESC_NUM_8822B \
+ (BIT_MASK_HI4Q_DESC_NUM_8822B << BIT_SHIFT_HI4Q_DESC_NUM_8822B)
+#define BIT_CLEAR_HI4Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI4Q_DESC_NUM_8822B))
+#define BIT_GET_HI4Q_DESC_NUM_8822B(x) \
+ (((x) >> BIT_SHIFT_HI4Q_DESC_NUM_8822B) & BIT_MASK_HI4Q_DESC_NUM_8822B)
+#define BIT_SET_HI4Q_DESC_NUM_8822B(x, v) \
+ (BIT_CLEAR_HI4Q_DESC_NUM_8822B(x) | BIT_HI4Q_DESC_NUM_8822B(v))
/* 2 REG_HI5Q_TXBD_NUM_8822B */
#define BIT_HI5Q_FLAG_8822B BIT(14)
#define BIT_SHIFT_HI5Q_DESC_MODE_8822B 12
#define BIT_MASK_HI5Q_DESC_MODE_8822B 0x3
-#define BIT_HI5Q_DESC_MODE_8822B(x) (((x) & BIT_MASK_HI5Q_DESC_MODE_8822B) << BIT_SHIFT_HI5Q_DESC_MODE_8822B)
-#define BIT_GET_HI5Q_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_HI5Q_DESC_MODE_8822B) & BIT_MASK_HI5Q_DESC_MODE_8822B)
-
+#define BIT_HI5Q_DESC_MODE_8822B(x) \
+ (((x) & BIT_MASK_HI5Q_DESC_MODE_8822B) \
+ << BIT_SHIFT_HI5Q_DESC_MODE_8822B)
+#define BITS_HI5Q_DESC_MODE_8822B \
+ (BIT_MASK_HI5Q_DESC_MODE_8822B << BIT_SHIFT_HI5Q_DESC_MODE_8822B)
+#define BIT_CLEAR_HI5Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI5Q_DESC_MODE_8822B))
+#define BIT_GET_HI5Q_DESC_MODE_8822B(x) \
+ (((x) >> BIT_SHIFT_HI5Q_DESC_MODE_8822B) & \
+ BIT_MASK_HI5Q_DESC_MODE_8822B)
+#define BIT_SET_HI5Q_DESC_MODE_8822B(x, v) \
+ (BIT_CLEAR_HI5Q_DESC_MODE_8822B(x) | BIT_HI5Q_DESC_MODE_8822B(v))
#define BIT_SHIFT_HI5Q_DESC_NUM_8822B 0
#define BIT_MASK_HI5Q_DESC_NUM_8822B 0xfff
-#define BIT_HI5Q_DESC_NUM_8822B(x) (((x) & BIT_MASK_HI5Q_DESC_NUM_8822B) << BIT_SHIFT_HI5Q_DESC_NUM_8822B)
-#define BIT_GET_HI5Q_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_HI5Q_DESC_NUM_8822B) & BIT_MASK_HI5Q_DESC_NUM_8822B)
-
+#define BIT_HI5Q_DESC_NUM_8822B(x) \
+ (((x) & BIT_MASK_HI5Q_DESC_NUM_8822B) << BIT_SHIFT_HI5Q_DESC_NUM_8822B)
+#define BITS_HI5Q_DESC_NUM_8822B \
+ (BIT_MASK_HI5Q_DESC_NUM_8822B << BIT_SHIFT_HI5Q_DESC_NUM_8822B)
+#define BIT_CLEAR_HI5Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI5Q_DESC_NUM_8822B))
+#define BIT_GET_HI5Q_DESC_NUM_8822B(x) \
+ (((x) >> BIT_SHIFT_HI5Q_DESC_NUM_8822B) & BIT_MASK_HI5Q_DESC_NUM_8822B)
+#define BIT_SET_HI5Q_DESC_NUM_8822B(x, v) \
+ (BIT_CLEAR_HI5Q_DESC_NUM_8822B(x) | BIT_HI5Q_DESC_NUM_8822B(v))
/* 2 REG_HI6Q_TXBD_NUM_8822B */
#define BIT_HI6Q_FLAG_8822B BIT(14)
#define BIT_SHIFT_HI6Q_DESC_MODE_8822B 12
#define BIT_MASK_HI6Q_DESC_MODE_8822B 0x3
-#define BIT_HI6Q_DESC_MODE_8822B(x) (((x) & BIT_MASK_HI6Q_DESC_MODE_8822B) << BIT_SHIFT_HI6Q_DESC_MODE_8822B)
-#define BIT_GET_HI6Q_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_HI6Q_DESC_MODE_8822B) & BIT_MASK_HI6Q_DESC_MODE_8822B)
-
+#define BIT_HI6Q_DESC_MODE_8822B(x) \
+ (((x) & BIT_MASK_HI6Q_DESC_MODE_8822B) \
+ << BIT_SHIFT_HI6Q_DESC_MODE_8822B)
+#define BITS_HI6Q_DESC_MODE_8822B \
+ (BIT_MASK_HI6Q_DESC_MODE_8822B << BIT_SHIFT_HI6Q_DESC_MODE_8822B)
+#define BIT_CLEAR_HI6Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI6Q_DESC_MODE_8822B))
+#define BIT_GET_HI6Q_DESC_MODE_8822B(x) \
+ (((x) >> BIT_SHIFT_HI6Q_DESC_MODE_8822B) & \
+ BIT_MASK_HI6Q_DESC_MODE_8822B)
+#define BIT_SET_HI6Q_DESC_MODE_8822B(x, v) \
+ (BIT_CLEAR_HI6Q_DESC_MODE_8822B(x) | BIT_HI6Q_DESC_MODE_8822B(v))
#define BIT_SHIFT_HI6Q_DESC_NUM_8822B 0
#define BIT_MASK_HI6Q_DESC_NUM_8822B 0xfff
-#define BIT_HI6Q_DESC_NUM_8822B(x) (((x) & BIT_MASK_HI6Q_DESC_NUM_8822B) << BIT_SHIFT_HI6Q_DESC_NUM_8822B)
-#define BIT_GET_HI6Q_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_HI6Q_DESC_NUM_8822B) & BIT_MASK_HI6Q_DESC_NUM_8822B)
-
+#define BIT_HI6Q_DESC_NUM_8822B(x) \
+ (((x) & BIT_MASK_HI6Q_DESC_NUM_8822B) << BIT_SHIFT_HI6Q_DESC_NUM_8822B)
+#define BITS_HI6Q_DESC_NUM_8822B \
+ (BIT_MASK_HI6Q_DESC_NUM_8822B << BIT_SHIFT_HI6Q_DESC_NUM_8822B)
+#define BIT_CLEAR_HI6Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI6Q_DESC_NUM_8822B))
+#define BIT_GET_HI6Q_DESC_NUM_8822B(x) \
+ (((x) >> BIT_SHIFT_HI6Q_DESC_NUM_8822B) & BIT_MASK_HI6Q_DESC_NUM_8822B)
+#define BIT_SET_HI6Q_DESC_NUM_8822B(x, v) \
+ (BIT_CLEAR_HI6Q_DESC_NUM_8822B(x) | BIT_HI6Q_DESC_NUM_8822B(v))
/* 2 REG_HI7Q_TXBD_NUM_8822B */
#define BIT_HI7Q_FLAG_8822B BIT(14)
#define BIT_SHIFT_HI7Q_DESC_MODE_8822B 12
#define BIT_MASK_HI7Q_DESC_MODE_8822B 0x3
-#define BIT_HI7Q_DESC_MODE_8822B(x) (((x) & BIT_MASK_HI7Q_DESC_MODE_8822B) << BIT_SHIFT_HI7Q_DESC_MODE_8822B)
-#define BIT_GET_HI7Q_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_HI7Q_DESC_MODE_8822B) & BIT_MASK_HI7Q_DESC_MODE_8822B)
-
+#define BIT_HI7Q_DESC_MODE_8822B(x) \
+ (((x) & BIT_MASK_HI7Q_DESC_MODE_8822B) \
+ << BIT_SHIFT_HI7Q_DESC_MODE_8822B)
+#define BITS_HI7Q_DESC_MODE_8822B \
+ (BIT_MASK_HI7Q_DESC_MODE_8822B << BIT_SHIFT_HI7Q_DESC_MODE_8822B)
+#define BIT_CLEAR_HI7Q_DESC_MODE_8822B(x) ((x) & (~BITS_HI7Q_DESC_MODE_8822B))
+#define BIT_GET_HI7Q_DESC_MODE_8822B(x) \
+ (((x) >> BIT_SHIFT_HI7Q_DESC_MODE_8822B) & \
+ BIT_MASK_HI7Q_DESC_MODE_8822B)
+#define BIT_SET_HI7Q_DESC_MODE_8822B(x, v) \
+ (BIT_CLEAR_HI7Q_DESC_MODE_8822B(x) | BIT_HI7Q_DESC_MODE_8822B(v))
#define BIT_SHIFT_HI7Q_DESC_NUM_8822B 0
#define BIT_MASK_HI7Q_DESC_NUM_8822B 0xfff
-#define BIT_HI7Q_DESC_NUM_8822B(x) (((x) & BIT_MASK_HI7Q_DESC_NUM_8822B) << BIT_SHIFT_HI7Q_DESC_NUM_8822B)
-#define BIT_GET_HI7Q_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_HI7Q_DESC_NUM_8822B) & BIT_MASK_HI7Q_DESC_NUM_8822B)
-
+#define BIT_HI7Q_DESC_NUM_8822B(x) \
+ (((x) & BIT_MASK_HI7Q_DESC_NUM_8822B) << BIT_SHIFT_HI7Q_DESC_NUM_8822B)
+#define BITS_HI7Q_DESC_NUM_8822B \
+ (BIT_MASK_HI7Q_DESC_NUM_8822B << BIT_SHIFT_HI7Q_DESC_NUM_8822B)
+#define BIT_CLEAR_HI7Q_DESC_NUM_8822B(x) ((x) & (~BITS_HI7Q_DESC_NUM_8822B))
+#define BIT_GET_HI7Q_DESC_NUM_8822B(x) \
+ (((x) >> BIT_SHIFT_HI7Q_DESC_NUM_8822B) & BIT_MASK_HI7Q_DESC_NUM_8822B)
+#define BIT_SET_HI7Q_DESC_NUM_8822B(x, v) \
+ (BIT_CLEAR_HI7Q_DESC_NUM_8822B(x) | BIT_HI7Q_DESC_NUM_8822B(v))
/* 2 REG_TSFTIMER_HCI_8822B */
#define BIT_SHIFT_TSFT2_HCI_8822B 16
#define BIT_MASK_TSFT2_HCI_8822B 0xffff
-#define BIT_TSFT2_HCI_8822B(x) (((x) & BIT_MASK_TSFT2_HCI_8822B) << BIT_SHIFT_TSFT2_HCI_8822B)
-#define BIT_GET_TSFT2_HCI_8822B(x) (((x) >> BIT_SHIFT_TSFT2_HCI_8822B) & BIT_MASK_TSFT2_HCI_8822B)
-
+#define BIT_TSFT2_HCI_8822B(x) \
+ (((x) & BIT_MASK_TSFT2_HCI_8822B) << BIT_SHIFT_TSFT2_HCI_8822B)
+#define BITS_TSFT2_HCI_8822B \
+ (BIT_MASK_TSFT2_HCI_8822B << BIT_SHIFT_TSFT2_HCI_8822B)
+#define BIT_CLEAR_TSFT2_HCI_8822B(x) ((x) & (~BITS_TSFT2_HCI_8822B))
+#define BIT_GET_TSFT2_HCI_8822B(x) \
+ (((x) >> BIT_SHIFT_TSFT2_HCI_8822B) & BIT_MASK_TSFT2_HCI_8822B)
+#define BIT_SET_TSFT2_HCI_8822B(x, v) \
+ (BIT_CLEAR_TSFT2_HCI_8822B(x) | BIT_TSFT2_HCI_8822B(v))
#define BIT_SHIFT_TSFT1_HCI_8822B 0
#define BIT_MASK_TSFT1_HCI_8822B 0xffff
-#define BIT_TSFT1_HCI_8822B(x) (((x) & BIT_MASK_TSFT1_HCI_8822B) << BIT_SHIFT_TSFT1_HCI_8822B)
-#define BIT_GET_TSFT1_HCI_8822B(x) (((x) >> BIT_SHIFT_TSFT1_HCI_8822B) & BIT_MASK_TSFT1_HCI_8822B)
-
+#define BIT_TSFT1_HCI_8822B(x) \
+ (((x) & BIT_MASK_TSFT1_HCI_8822B) << BIT_SHIFT_TSFT1_HCI_8822B)
+#define BITS_TSFT1_HCI_8822B \
+ (BIT_MASK_TSFT1_HCI_8822B << BIT_SHIFT_TSFT1_HCI_8822B)
+#define BIT_CLEAR_TSFT1_HCI_8822B(x) ((x) & (~BITS_TSFT1_HCI_8822B))
+#define BIT_GET_TSFT1_HCI_8822B(x) \
+ (((x) >> BIT_SHIFT_TSFT1_HCI_8822B) & BIT_MASK_TSFT1_HCI_8822B)
+#define BIT_SET_TSFT1_HCI_8822B(x, v) \
+ (BIT_CLEAR_TSFT1_HCI_8822B(x) | BIT_TSFT1_HCI_8822B(v))
/* 2 REG_BD_RWPTR_CLR_8822B */
#define BIT_CLR_HI7Q_HW_IDX_8822B BIT(29)
@@ -4244,221 +6864,406 @@
#define BIT_SHIFT_VOQ_HW_IDX_8822B 16
#define BIT_MASK_VOQ_HW_IDX_8822B 0xfff
-#define BIT_VOQ_HW_IDX_8822B(x) (((x) & BIT_MASK_VOQ_HW_IDX_8822B) << BIT_SHIFT_VOQ_HW_IDX_8822B)
-#define BIT_GET_VOQ_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_VOQ_HW_IDX_8822B) & BIT_MASK_VOQ_HW_IDX_8822B)
-
+#define BIT_VOQ_HW_IDX_8822B(x) \
+ (((x) & BIT_MASK_VOQ_HW_IDX_8822B) << BIT_SHIFT_VOQ_HW_IDX_8822B)
+#define BITS_VOQ_HW_IDX_8822B \
+ (BIT_MASK_VOQ_HW_IDX_8822B << BIT_SHIFT_VOQ_HW_IDX_8822B)
+#define BIT_CLEAR_VOQ_HW_IDX_8822B(x) ((x) & (~BITS_VOQ_HW_IDX_8822B))
+#define BIT_GET_VOQ_HW_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_VOQ_HW_IDX_8822B) & BIT_MASK_VOQ_HW_IDX_8822B)
+#define BIT_SET_VOQ_HW_IDX_8822B(x, v) \
+ (BIT_CLEAR_VOQ_HW_IDX_8822B(x) | BIT_VOQ_HW_IDX_8822B(v))
#define BIT_SHIFT_VOQ_HOST_IDX_8822B 0
#define BIT_MASK_VOQ_HOST_IDX_8822B 0xfff
-#define BIT_VOQ_HOST_IDX_8822B(x) (((x) & BIT_MASK_VOQ_HOST_IDX_8822B) << BIT_SHIFT_VOQ_HOST_IDX_8822B)
-#define BIT_GET_VOQ_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_VOQ_HOST_IDX_8822B) & BIT_MASK_VOQ_HOST_IDX_8822B)
-
+#define BIT_VOQ_HOST_IDX_8822B(x) \
+ (((x) & BIT_MASK_VOQ_HOST_IDX_8822B) << BIT_SHIFT_VOQ_HOST_IDX_8822B)
+#define BITS_VOQ_HOST_IDX_8822B \
+ (BIT_MASK_VOQ_HOST_IDX_8822B << BIT_SHIFT_VOQ_HOST_IDX_8822B)
+#define BIT_CLEAR_VOQ_HOST_IDX_8822B(x) ((x) & (~BITS_VOQ_HOST_IDX_8822B))
+#define BIT_GET_VOQ_HOST_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_VOQ_HOST_IDX_8822B) & BIT_MASK_VOQ_HOST_IDX_8822B)
+#define BIT_SET_VOQ_HOST_IDX_8822B(x, v) \
+ (BIT_CLEAR_VOQ_HOST_IDX_8822B(x) | BIT_VOQ_HOST_IDX_8822B(v))
/* 2 REG_VIQ_TXBD_IDX_8822B */
#define BIT_SHIFT_VIQ_HW_IDX_8822B 16
#define BIT_MASK_VIQ_HW_IDX_8822B 0xfff
-#define BIT_VIQ_HW_IDX_8822B(x) (((x) & BIT_MASK_VIQ_HW_IDX_8822B) << BIT_SHIFT_VIQ_HW_IDX_8822B)
-#define BIT_GET_VIQ_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_VIQ_HW_IDX_8822B) & BIT_MASK_VIQ_HW_IDX_8822B)
-
+#define BIT_VIQ_HW_IDX_8822B(x) \
+ (((x) & BIT_MASK_VIQ_HW_IDX_8822B) << BIT_SHIFT_VIQ_HW_IDX_8822B)
+#define BITS_VIQ_HW_IDX_8822B \
+ (BIT_MASK_VIQ_HW_IDX_8822B << BIT_SHIFT_VIQ_HW_IDX_8822B)
+#define BIT_CLEAR_VIQ_HW_IDX_8822B(x) ((x) & (~BITS_VIQ_HW_IDX_8822B))
+#define BIT_GET_VIQ_HW_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_VIQ_HW_IDX_8822B) & BIT_MASK_VIQ_HW_IDX_8822B)
+#define BIT_SET_VIQ_HW_IDX_8822B(x, v) \
+ (BIT_CLEAR_VIQ_HW_IDX_8822B(x) | BIT_VIQ_HW_IDX_8822B(v))
#define BIT_SHIFT_VIQ_HOST_IDX_8822B 0
#define BIT_MASK_VIQ_HOST_IDX_8822B 0xfff
-#define BIT_VIQ_HOST_IDX_8822B(x) (((x) & BIT_MASK_VIQ_HOST_IDX_8822B) << BIT_SHIFT_VIQ_HOST_IDX_8822B)
-#define BIT_GET_VIQ_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_VIQ_HOST_IDX_8822B) & BIT_MASK_VIQ_HOST_IDX_8822B)
-
+#define BIT_VIQ_HOST_IDX_8822B(x) \
+ (((x) & BIT_MASK_VIQ_HOST_IDX_8822B) << BIT_SHIFT_VIQ_HOST_IDX_8822B)
+#define BITS_VIQ_HOST_IDX_8822B \
+ (BIT_MASK_VIQ_HOST_IDX_8822B << BIT_SHIFT_VIQ_HOST_IDX_8822B)
+#define BIT_CLEAR_VIQ_HOST_IDX_8822B(x) ((x) & (~BITS_VIQ_HOST_IDX_8822B))
+#define BIT_GET_VIQ_HOST_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_VIQ_HOST_IDX_8822B) & BIT_MASK_VIQ_HOST_IDX_8822B)
+#define BIT_SET_VIQ_HOST_IDX_8822B(x, v) \
+ (BIT_CLEAR_VIQ_HOST_IDX_8822B(x) | BIT_VIQ_HOST_IDX_8822B(v))
/* 2 REG_BEQ_TXBD_IDX_8822B */
#define BIT_SHIFT_BEQ_HW_IDX_8822B 16
#define BIT_MASK_BEQ_HW_IDX_8822B 0xfff
-#define BIT_BEQ_HW_IDX_8822B(x) (((x) & BIT_MASK_BEQ_HW_IDX_8822B) << BIT_SHIFT_BEQ_HW_IDX_8822B)
-#define BIT_GET_BEQ_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_BEQ_HW_IDX_8822B) & BIT_MASK_BEQ_HW_IDX_8822B)
-
+#define BIT_BEQ_HW_IDX_8822B(x) \
+ (((x) & BIT_MASK_BEQ_HW_IDX_8822B) << BIT_SHIFT_BEQ_HW_IDX_8822B)
+#define BITS_BEQ_HW_IDX_8822B \
+ (BIT_MASK_BEQ_HW_IDX_8822B << BIT_SHIFT_BEQ_HW_IDX_8822B)
+#define BIT_CLEAR_BEQ_HW_IDX_8822B(x) ((x) & (~BITS_BEQ_HW_IDX_8822B))
+#define BIT_GET_BEQ_HW_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_BEQ_HW_IDX_8822B) & BIT_MASK_BEQ_HW_IDX_8822B)
+#define BIT_SET_BEQ_HW_IDX_8822B(x, v) \
+ (BIT_CLEAR_BEQ_HW_IDX_8822B(x) | BIT_BEQ_HW_IDX_8822B(v))
#define BIT_SHIFT_BEQ_HOST_IDX_8822B 0
#define BIT_MASK_BEQ_HOST_IDX_8822B 0xfff
-#define BIT_BEQ_HOST_IDX_8822B(x) (((x) & BIT_MASK_BEQ_HOST_IDX_8822B) << BIT_SHIFT_BEQ_HOST_IDX_8822B)
-#define BIT_GET_BEQ_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_BEQ_HOST_IDX_8822B) & BIT_MASK_BEQ_HOST_IDX_8822B)
-
+#define BIT_BEQ_HOST_IDX_8822B(x) \
+ (((x) & BIT_MASK_BEQ_HOST_IDX_8822B) << BIT_SHIFT_BEQ_HOST_IDX_8822B)
+#define BITS_BEQ_HOST_IDX_8822B \
+ (BIT_MASK_BEQ_HOST_IDX_8822B << BIT_SHIFT_BEQ_HOST_IDX_8822B)
+#define BIT_CLEAR_BEQ_HOST_IDX_8822B(x) ((x) & (~BITS_BEQ_HOST_IDX_8822B))
+#define BIT_GET_BEQ_HOST_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_BEQ_HOST_IDX_8822B) & BIT_MASK_BEQ_HOST_IDX_8822B)
+#define BIT_SET_BEQ_HOST_IDX_8822B(x, v) \
+ (BIT_CLEAR_BEQ_HOST_IDX_8822B(x) | BIT_BEQ_HOST_IDX_8822B(v))
/* 2 REG_BKQ_TXBD_IDX_8822B */
#define BIT_SHIFT_BKQ_HW_IDX_8822B 16
#define BIT_MASK_BKQ_HW_IDX_8822B 0xfff
-#define BIT_BKQ_HW_IDX_8822B(x) (((x) & BIT_MASK_BKQ_HW_IDX_8822B) << BIT_SHIFT_BKQ_HW_IDX_8822B)
-#define BIT_GET_BKQ_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_BKQ_HW_IDX_8822B) & BIT_MASK_BKQ_HW_IDX_8822B)
-
+#define BIT_BKQ_HW_IDX_8822B(x) \
+ (((x) & BIT_MASK_BKQ_HW_IDX_8822B) << BIT_SHIFT_BKQ_HW_IDX_8822B)
+#define BITS_BKQ_HW_IDX_8822B \
+ (BIT_MASK_BKQ_HW_IDX_8822B << BIT_SHIFT_BKQ_HW_IDX_8822B)
+#define BIT_CLEAR_BKQ_HW_IDX_8822B(x) ((x) & (~BITS_BKQ_HW_IDX_8822B))
+#define BIT_GET_BKQ_HW_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_BKQ_HW_IDX_8822B) & BIT_MASK_BKQ_HW_IDX_8822B)
+#define BIT_SET_BKQ_HW_IDX_8822B(x, v) \
+ (BIT_CLEAR_BKQ_HW_IDX_8822B(x) | BIT_BKQ_HW_IDX_8822B(v))
#define BIT_SHIFT_BKQ_HOST_IDX_8822B 0
#define BIT_MASK_BKQ_HOST_IDX_8822B 0xfff
-#define BIT_BKQ_HOST_IDX_8822B(x) (((x) & BIT_MASK_BKQ_HOST_IDX_8822B) << BIT_SHIFT_BKQ_HOST_IDX_8822B)
-#define BIT_GET_BKQ_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_BKQ_HOST_IDX_8822B) & BIT_MASK_BKQ_HOST_IDX_8822B)
-
+#define BIT_BKQ_HOST_IDX_8822B(x) \
+ (((x) & BIT_MASK_BKQ_HOST_IDX_8822B) << BIT_SHIFT_BKQ_HOST_IDX_8822B)
+#define BITS_BKQ_HOST_IDX_8822B \
+ (BIT_MASK_BKQ_HOST_IDX_8822B << BIT_SHIFT_BKQ_HOST_IDX_8822B)
+#define BIT_CLEAR_BKQ_HOST_IDX_8822B(x) ((x) & (~BITS_BKQ_HOST_IDX_8822B))
+#define BIT_GET_BKQ_HOST_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_BKQ_HOST_IDX_8822B) & BIT_MASK_BKQ_HOST_IDX_8822B)
+#define BIT_SET_BKQ_HOST_IDX_8822B(x, v) \
+ (BIT_CLEAR_BKQ_HOST_IDX_8822B(x) | BIT_BKQ_HOST_IDX_8822B(v))
/* 2 REG_MGQ_TXBD_IDX_8822B */
#define BIT_SHIFT_MGQ_HW_IDX_8822B 16
#define BIT_MASK_MGQ_HW_IDX_8822B 0xfff
-#define BIT_MGQ_HW_IDX_8822B(x) (((x) & BIT_MASK_MGQ_HW_IDX_8822B) << BIT_SHIFT_MGQ_HW_IDX_8822B)
-#define BIT_GET_MGQ_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_MGQ_HW_IDX_8822B) & BIT_MASK_MGQ_HW_IDX_8822B)
-
+#define BIT_MGQ_HW_IDX_8822B(x) \
+ (((x) & BIT_MASK_MGQ_HW_IDX_8822B) << BIT_SHIFT_MGQ_HW_IDX_8822B)
+#define BITS_MGQ_HW_IDX_8822B \
+ (BIT_MASK_MGQ_HW_IDX_8822B << BIT_SHIFT_MGQ_HW_IDX_8822B)
+#define BIT_CLEAR_MGQ_HW_IDX_8822B(x) ((x) & (~BITS_MGQ_HW_IDX_8822B))
+#define BIT_GET_MGQ_HW_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_MGQ_HW_IDX_8822B) & BIT_MASK_MGQ_HW_IDX_8822B)
+#define BIT_SET_MGQ_HW_IDX_8822B(x, v) \
+ (BIT_CLEAR_MGQ_HW_IDX_8822B(x) | BIT_MGQ_HW_IDX_8822B(v))
#define BIT_SHIFT_MGQ_HOST_IDX_8822B 0
#define BIT_MASK_MGQ_HOST_IDX_8822B 0xfff
-#define BIT_MGQ_HOST_IDX_8822B(x) (((x) & BIT_MASK_MGQ_HOST_IDX_8822B) << BIT_SHIFT_MGQ_HOST_IDX_8822B)
-#define BIT_GET_MGQ_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_MGQ_HOST_IDX_8822B) & BIT_MASK_MGQ_HOST_IDX_8822B)
-
+#define BIT_MGQ_HOST_IDX_8822B(x) \
+ (((x) & BIT_MASK_MGQ_HOST_IDX_8822B) << BIT_SHIFT_MGQ_HOST_IDX_8822B)
+#define BITS_MGQ_HOST_IDX_8822B \
+ (BIT_MASK_MGQ_HOST_IDX_8822B << BIT_SHIFT_MGQ_HOST_IDX_8822B)
+#define BIT_CLEAR_MGQ_HOST_IDX_8822B(x) ((x) & (~BITS_MGQ_HOST_IDX_8822B))
+#define BIT_GET_MGQ_HOST_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_MGQ_HOST_IDX_8822B) & BIT_MASK_MGQ_HOST_IDX_8822B)
+#define BIT_SET_MGQ_HOST_IDX_8822B(x, v) \
+ (BIT_CLEAR_MGQ_HOST_IDX_8822B(x) | BIT_MGQ_HOST_IDX_8822B(v))
/* 2 REG_RXQ_RXBD_IDX_8822B */
#define BIT_SHIFT_RXQ_HW_IDX_8822B 16
#define BIT_MASK_RXQ_HW_IDX_8822B 0xfff
-#define BIT_RXQ_HW_IDX_8822B(x) (((x) & BIT_MASK_RXQ_HW_IDX_8822B) << BIT_SHIFT_RXQ_HW_IDX_8822B)
-#define BIT_GET_RXQ_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_RXQ_HW_IDX_8822B) & BIT_MASK_RXQ_HW_IDX_8822B)
-
+#define BIT_RXQ_HW_IDX_8822B(x) \
+ (((x) & BIT_MASK_RXQ_HW_IDX_8822B) << BIT_SHIFT_RXQ_HW_IDX_8822B)
+#define BITS_RXQ_HW_IDX_8822B \
+ (BIT_MASK_RXQ_HW_IDX_8822B << BIT_SHIFT_RXQ_HW_IDX_8822B)
+#define BIT_CLEAR_RXQ_HW_IDX_8822B(x) ((x) & (~BITS_RXQ_HW_IDX_8822B))
+#define BIT_GET_RXQ_HW_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_RXQ_HW_IDX_8822B) & BIT_MASK_RXQ_HW_IDX_8822B)
+#define BIT_SET_RXQ_HW_IDX_8822B(x, v) \
+ (BIT_CLEAR_RXQ_HW_IDX_8822B(x) | BIT_RXQ_HW_IDX_8822B(v))
#define BIT_SHIFT_RXQ_HOST_IDX_8822B 0
#define BIT_MASK_RXQ_HOST_IDX_8822B 0xfff
-#define BIT_RXQ_HOST_IDX_8822B(x) (((x) & BIT_MASK_RXQ_HOST_IDX_8822B) << BIT_SHIFT_RXQ_HOST_IDX_8822B)
-#define BIT_GET_RXQ_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_RXQ_HOST_IDX_8822B) & BIT_MASK_RXQ_HOST_IDX_8822B)
-
+#define BIT_RXQ_HOST_IDX_8822B(x) \
+ (((x) & BIT_MASK_RXQ_HOST_IDX_8822B) << BIT_SHIFT_RXQ_HOST_IDX_8822B)
+#define BITS_RXQ_HOST_IDX_8822B \
+ (BIT_MASK_RXQ_HOST_IDX_8822B << BIT_SHIFT_RXQ_HOST_IDX_8822B)
+#define BIT_CLEAR_RXQ_HOST_IDX_8822B(x) ((x) & (~BITS_RXQ_HOST_IDX_8822B))
+#define BIT_GET_RXQ_HOST_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_RXQ_HOST_IDX_8822B) & BIT_MASK_RXQ_HOST_IDX_8822B)
+#define BIT_SET_RXQ_HOST_IDX_8822B(x, v) \
+ (BIT_CLEAR_RXQ_HOST_IDX_8822B(x) | BIT_RXQ_HOST_IDX_8822B(v))
/* 2 REG_HI0Q_TXBD_IDX_8822B */
#define BIT_SHIFT_HI0Q_HW_IDX_8822B 16
#define BIT_MASK_HI0Q_HW_IDX_8822B 0xfff
-#define BIT_HI0Q_HW_IDX_8822B(x) (((x) & BIT_MASK_HI0Q_HW_IDX_8822B) << BIT_SHIFT_HI0Q_HW_IDX_8822B)
-#define BIT_GET_HI0Q_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_HI0Q_HW_IDX_8822B) & BIT_MASK_HI0Q_HW_IDX_8822B)
-
+#define BIT_HI0Q_HW_IDX_8822B(x) \
+ (((x) & BIT_MASK_HI0Q_HW_IDX_8822B) << BIT_SHIFT_HI0Q_HW_IDX_8822B)
+#define BITS_HI0Q_HW_IDX_8822B \
+ (BIT_MASK_HI0Q_HW_IDX_8822B << BIT_SHIFT_HI0Q_HW_IDX_8822B)
+#define BIT_CLEAR_HI0Q_HW_IDX_8822B(x) ((x) & (~BITS_HI0Q_HW_IDX_8822B))
+#define BIT_GET_HI0Q_HW_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_HI0Q_HW_IDX_8822B) & BIT_MASK_HI0Q_HW_IDX_8822B)
+#define BIT_SET_HI0Q_HW_IDX_8822B(x, v) \
+ (BIT_CLEAR_HI0Q_HW_IDX_8822B(x) | BIT_HI0Q_HW_IDX_8822B(v))
#define BIT_SHIFT_HI0Q_HOST_IDX_8822B 0
#define BIT_MASK_HI0Q_HOST_IDX_8822B 0xfff
-#define BIT_HI0Q_HOST_IDX_8822B(x) (((x) & BIT_MASK_HI0Q_HOST_IDX_8822B) << BIT_SHIFT_HI0Q_HOST_IDX_8822B)
-#define BIT_GET_HI0Q_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_HI0Q_HOST_IDX_8822B) & BIT_MASK_HI0Q_HOST_IDX_8822B)
-
+#define BIT_HI0Q_HOST_IDX_8822B(x) \
+ (((x) & BIT_MASK_HI0Q_HOST_IDX_8822B) << BIT_SHIFT_HI0Q_HOST_IDX_8822B)
+#define BITS_HI0Q_HOST_IDX_8822B \
+ (BIT_MASK_HI0Q_HOST_IDX_8822B << BIT_SHIFT_HI0Q_HOST_IDX_8822B)
+#define BIT_CLEAR_HI0Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI0Q_HOST_IDX_8822B))
+#define BIT_GET_HI0Q_HOST_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_HI0Q_HOST_IDX_8822B) & BIT_MASK_HI0Q_HOST_IDX_8822B)
+#define BIT_SET_HI0Q_HOST_IDX_8822B(x, v) \
+ (BIT_CLEAR_HI0Q_HOST_IDX_8822B(x) | BIT_HI0Q_HOST_IDX_8822B(v))
/* 2 REG_HI1Q_TXBD_IDX_8822B */
#define BIT_SHIFT_HI1Q_HW_IDX_8822B 16
#define BIT_MASK_HI1Q_HW_IDX_8822B 0xfff
-#define BIT_HI1Q_HW_IDX_8822B(x) (((x) & BIT_MASK_HI1Q_HW_IDX_8822B) << BIT_SHIFT_HI1Q_HW_IDX_8822B)
-#define BIT_GET_HI1Q_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_HI1Q_HW_IDX_8822B) & BIT_MASK_HI1Q_HW_IDX_8822B)
-
+#define BIT_HI1Q_HW_IDX_8822B(x) \
+ (((x) & BIT_MASK_HI1Q_HW_IDX_8822B) << BIT_SHIFT_HI1Q_HW_IDX_8822B)
+#define BITS_HI1Q_HW_IDX_8822B \
+ (BIT_MASK_HI1Q_HW_IDX_8822B << BIT_SHIFT_HI1Q_HW_IDX_8822B)
+#define BIT_CLEAR_HI1Q_HW_IDX_8822B(x) ((x) & (~BITS_HI1Q_HW_IDX_8822B))
+#define BIT_GET_HI1Q_HW_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_HI1Q_HW_IDX_8822B) & BIT_MASK_HI1Q_HW_IDX_8822B)
+#define BIT_SET_HI1Q_HW_IDX_8822B(x, v) \
+ (BIT_CLEAR_HI1Q_HW_IDX_8822B(x) | BIT_HI1Q_HW_IDX_8822B(v))
#define BIT_SHIFT_HI1Q_HOST_IDX_8822B 0
#define BIT_MASK_HI1Q_HOST_IDX_8822B 0xfff
-#define BIT_HI1Q_HOST_IDX_8822B(x) (((x) & BIT_MASK_HI1Q_HOST_IDX_8822B) << BIT_SHIFT_HI1Q_HOST_IDX_8822B)
-#define BIT_GET_HI1Q_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_HI1Q_HOST_IDX_8822B) & BIT_MASK_HI1Q_HOST_IDX_8822B)
-
+#define BIT_HI1Q_HOST_IDX_8822B(x) \
+ (((x) & BIT_MASK_HI1Q_HOST_IDX_8822B) << BIT_SHIFT_HI1Q_HOST_IDX_8822B)
+#define BITS_HI1Q_HOST_IDX_8822B \
+ (BIT_MASK_HI1Q_HOST_IDX_8822B << BIT_SHIFT_HI1Q_HOST_IDX_8822B)
+#define BIT_CLEAR_HI1Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI1Q_HOST_IDX_8822B))
+#define BIT_GET_HI1Q_HOST_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_HI1Q_HOST_IDX_8822B) & BIT_MASK_HI1Q_HOST_IDX_8822B)
+#define BIT_SET_HI1Q_HOST_IDX_8822B(x, v) \
+ (BIT_CLEAR_HI1Q_HOST_IDX_8822B(x) | BIT_HI1Q_HOST_IDX_8822B(v))
/* 2 REG_HI2Q_TXBD_IDX_8822B */
#define BIT_SHIFT_HI2Q_HW_IDX_8822B 16
#define BIT_MASK_HI2Q_HW_IDX_8822B 0xfff
-#define BIT_HI2Q_HW_IDX_8822B(x) (((x) & BIT_MASK_HI2Q_HW_IDX_8822B) << BIT_SHIFT_HI2Q_HW_IDX_8822B)
-#define BIT_GET_HI2Q_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_HI2Q_HW_IDX_8822B) & BIT_MASK_HI2Q_HW_IDX_8822B)
-
+#define BIT_HI2Q_HW_IDX_8822B(x) \
+ (((x) & BIT_MASK_HI2Q_HW_IDX_8822B) << BIT_SHIFT_HI2Q_HW_IDX_8822B)
+#define BITS_HI2Q_HW_IDX_8822B \
+ (BIT_MASK_HI2Q_HW_IDX_8822B << BIT_SHIFT_HI2Q_HW_IDX_8822B)
+#define BIT_CLEAR_HI2Q_HW_IDX_8822B(x) ((x) & (~BITS_HI2Q_HW_IDX_8822B))
+#define BIT_GET_HI2Q_HW_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_HI2Q_HW_IDX_8822B) & BIT_MASK_HI2Q_HW_IDX_8822B)
+#define BIT_SET_HI2Q_HW_IDX_8822B(x, v) \
+ (BIT_CLEAR_HI2Q_HW_IDX_8822B(x) | BIT_HI2Q_HW_IDX_8822B(v))
#define BIT_SHIFT_HI2Q_HOST_IDX_8822B 0
#define BIT_MASK_HI2Q_HOST_IDX_8822B 0xfff
-#define BIT_HI2Q_HOST_IDX_8822B(x) (((x) & BIT_MASK_HI2Q_HOST_IDX_8822B) << BIT_SHIFT_HI2Q_HOST_IDX_8822B)
-#define BIT_GET_HI2Q_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_HI2Q_HOST_IDX_8822B) & BIT_MASK_HI2Q_HOST_IDX_8822B)
-
+#define BIT_HI2Q_HOST_IDX_8822B(x) \
+ (((x) & BIT_MASK_HI2Q_HOST_IDX_8822B) << BIT_SHIFT_HI2Q_HOST_IDX_8822B)
+#define BITS_HI2Q_HOST_IDX_8822B \
+ (BIT_MASK_HI2Q_HOST_IDX_8822B << BIT_SHIFT_HI2Q_HOST_IDX_8822B)
+#define BIT_CLEAR_HI2Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI2Q_HOST_IDX_8822B))
+#define BIT_GET_HI2Q_HOST_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_HI2Q_HOST_IDX_8822B) & BIT_MASK_HI2Q_HOST_IDX_8822B)
+#define BIT_SET_HI2Q_HOST_IDX_8822B(x, v) \
+ (BIT_CLEAR_HI2Q_HOST_IDX_8822B(x) | BIT_HI2Q_HOST_IDX_8822B(v))
/* 2 REG_HI3Q_TXBD_IDX_8822B */
#define BIT_SHIFT_HI3Q_HW_IDX_8822B 16
#define BIT_MASK_HI3Q_HW_IDX_8822B 0xfff
-#define BIT_HI3Q_HW_IDX_8822B(x) (((x) & BIT_MASK_HI3Q_HW_IDX_8822B) << BIT_SHIFT_HI3Q_HW_IDX_8822B)
-#define BIT_GET_HI3Q_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_HI3Q_HW_IDX_8822B) & BIT_MASK_HI3Q_HW_IDX_8822B)
-
+#define BIT_HI3Q_HW_IDX_8822B(x) \
+ (((x) & BIT_MASK_HI3Q_HW_IDX_8822B) << BIT_SHIFT_HI3Q_HW_IDX_8822B)
+#define BITS_HI3Q_HW_IDX_8822B \
+ (BIT_MASK_HI3Q_HW_IDX_8822B << BIT_SHIFT_HI3Q_HW_IDX_8822B)
+#define BIT_CLEAR_HI3Q_HW_IDX_8822B(x) ((x) & (~BITS_HI3Q_HW_IDX_8822B))
+#define BIT_GET_HI3Q_HW_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_HI3Q_HW_IDX_8822B) & BIT_MASK_HI3Q_HW_IDX_8822B)
+#define BIT_SET_HI3Q_HW_IDX_8822B(x, v) \
+ (BIT_CLEAR_HI3Q_HW_IDX_8822B(x) | BIT_HI3Q_HW_IDX_8822B(v))
#define BIT_SHIFT_HI3Q_HOST_IDX_8822B 0
#define BIT_MASK_HI3Q_HOST_IDX_8822B 0xfff
-#define BIT_HI3Q_HOST_IDX_8822B(x) (((x) & BIT_MASK_HI3Q_HOST_IDX_8822B) << BIT_SHIFT_HI3Q_HOST_IDX_8822B)
-#define BIT_GET_HI3Q_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_HI3Q_HOST_IDX_8822B) & BIT_MASK_HI3Q_HOST_IDX_8822B)
-
+#define BIT_HI3Q_HOST_IDX_8822B(x) \
+ (((x) & BIT_MASK_HI3Q_HOST_IDX_8822B) << BIT_SHIFT_HI3Q_HOST_IDX_8822B)
+#define BITS_HI3Q_HOST_IDX_8822B \
+ (BIT_MASK_HI3Q_HOST_IDX_8822B << BIT_SHIFT_HI3Q_HOST_IDX_8822B)
+#define BIT_CLEAR_HI3Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI3Q_HOST_IDX_8822B))
+#define BIT_GET_HI3Q_HOST_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_HI3Q_HOST_IDX_8822B) & BIT_MASK_HI3Q_HOST_IDX_8822B)
+#define BIT_SET_HI3Q_HOST_IDX_8822B(x, v) \
+ (BIT_CLEAR_HI3Q_HOST_IDX_8822B(x) | BIT_HI3Q_HOST_IDX_8822B(v))
/* 2 REG_HI4Q_TXBD_IDX_8822B */
#define BIT_SHIFT_HI4Q_HW_IDX_8822B 16
#define BIT_MASK_HI4Q_HW_IDX_8822B 0xfff
-#define BIT_HI4Q_HW_IDX_8822B(x) (((x) & BIT_MASK_HI4Q_HW_IDX_8822B) << BIT_SHIFT_HI4Q_HW_IDX_8822B)
-#define BIT_GET_HI4Q_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_HI4Q_HW_IDX_8822B) & BIT_MASK_HI4Q_HW_IDX_8822B)
-
+#define BIT_HI4Q_HW_IDX_8822B(x) \
+ (((x) & BIT_MASK_HI4Q_HW_IDX_8822B) << BIT_SHIFT_HI4Q_HW_IDX_8822B)
+#define BITS_HI4Q_HW_IDX_8822B \
+ (BIT_MASK_HI4Q_HW_IDX_8822B << BIT_SHIFT_HI4Q_HW_IDX_8822B)
+#define BIT_CLEAR_HI4Q_HW_IDX_8822B(x) ((x) & (~BITS_HI4Q_HW_IDX_8822B))
+#define BIT_GET_HI4Q_HW_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_HI4Q_HW_IDX_8822B) & BIT_MASK_HI4Q_HW_IDX_8822B)
+#define BIT_SET_HI4Q_HW_IDX_8822B(x, v) \
+ (BIT_CLEAR_HI4Q_HW_IDX_8822B(x) | BIT_HI4Q_HW_IDX_8822B(v))
#define BIT_SHIFT_HI4Q_HOST_IDX_8822B 0
#define BIT_MASK_HI4Q_HOST_IDX_8822B 0xfff
-#define BIT_HI4Q_HOST_IDX_8822B(x) (((x) & BIT_MASK_HI4Q_HOST_IDX_8822B) << BIT_SHIFT_HI4Q_HOST_IDX_8822B)
-#define BIT_GET_HI4Q_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_HI4Q_HOST_IDX_8822B) & BIT_MASK_HI4Q_HOST_IDX_8822B)
-
+#define BIT_HI4Q_HOST_IDX_8822B(x) \
+ (((x) & BIT_MASK_HI4Q_HOST_IDX_8822B) << BIT_SHIFT_HI4Q_HOST_IDX_8822B)
+#define BITS_HI4Q_HOST_IDX_8822B \
+ (BIT_MASK_HI4Q_HOST_IDX_8822B << BIT_SHIFT_HI4Q_HOST_IDX_8822B)
+#define BIT_CLEAR_HI4Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI4Q_HOST_IDX_8822B))
+#define BIT_GET_HI4Q_HOST_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_HI4Q_HOST_IDX_8822B) & BIT_MASK_HI4Q_HOST_IDX_8822B)
+#define BIT_SET_HI4Q_HOST_IDX_8822B(x, v) \
+ (BIT_CLEAR_HI4Q_HOST_IDX_8822B(x) | BIT_HI4Q_HOST_IDX_8822B(v))
/* 2 REG_HI5Q_TXBD_IDX_8822B */
#define BIT_SHIFT_HI5Q_HW_IDX_8822B 16
#define BIT_MASK_HI5Q_HW_IDX_8822B 0xfff
-#define BIT_HI5Q_HW_IDX_8822B(x) (((x) & BIT_MASK_HI5Q_HW_IDX_8822B) << BIT_SHIFT_HI5Q_HW_IDX_8822B)
-#define BIT_GET_HI5Q_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_HI5Q_HW_IDX_8822B) & BIT_MASK_HI5Q_HW_IDX_8822B)
-
+#define BIT_HI5Q_HW_IDX_8822B(x) \
+ (((x) & BIT_MASK_HI5Q_HW_IDX_8822B) << BIT_SHIFT_HI5Q_HW_IDX_8822B)
+#define BITS_HI5Q_HW_IDX_8822B \
+ (BIT_MASK_HI5Q_HW_IDX_8822B << BIT_SHIFT_HI5Q_HW_IDX_8822B)
+#define BIT_CLEAR_HI5Q_HW_IDX_8822B(x) ((x) & (~BITS_HI5Q_HW_IDX_8822B))
+#define BIT_GET_HI5Q_HW_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_HI5Q_HW_IDX_8822B) & BIT_MASK_HI5Q_HW_IDX_8822B)
+#define BIT_SET_HI5Q_HW_IDX_8822B(x, v) \
+ (BIT_CLEAR_HI5Q_HW_IDX_8822B(x) | BIT_HI5Q_HW_IDX_8822B(v))
#define BIT_SHIFT_HI5Q_HOST_IDX_8822B 0
#define BIT_MASK_HI5Q_HOST_IDX_8822B 0xfff
-#define BIT_HI5Q_HOST_IDX_8822B(x) (((x) & BIT_MASK_HI5Q_HOST_IDX_8822B) << BIT_SHIFT_HI5Q_HOST_IDX_8822B)
-#define BIT_GET_HI5Q_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_HI5Q_HOST_IDX_8822B) & BIT_MASK_HI5Q_HOST_IDX_8822B)
-
+#define BIT_HI5Q_HOST_IDX_8822B(x) \
+ (((x) & BIT_MASK_HI5Q_HOST_IDX_8822B) << BIT_SHIFT_HI5Q_HOST_IDX_8822B)
+#define BITS_HI5Q_HOST_IDX_8822B \
+ (BIT_MASK_HI5Q_HOST_IDX_8822B << BIT_SHIFT_HI5Q_HOST_IDX_8822B)
+#define BIT_CLEAR_HI5Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI5Q_HOST_IDX_8822B))
+#define BIT_GET_HI5Q_HOST_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_HI5Q_HOST_IDX_8822B) & BIT_MASK_HI5Q_HOST_IDX_8822B)
+#define BIT_SET_HI5Q_HOST_IDX_8822B(x, v) \
+ (BIT_CLEAR_HI5Q_HOST_IDX_8822B(x) | BIT_HI5Q_HOST_IDX_8822B(v))
/* 2 REG_HI6Q_TXBD_IDX_8822B */
#define BIT_SHIFT_HI6Q_HW_IDX_8822B 16
#define BIT_MASK_HI6Q_HW_IDX_8822B 0xfff
-#define BIT_HI6Q_HW_IDX_8822B(x) (((x) & BIT_MASK_HI6Q_HW_IDX_8822B) << BIT_SHIFT_HI6Q_HW_IDX_8822B)
-#define BIT_GET_HI6Q_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_HI6Q_HW_IDX_8822B) & BIT_MASK_HI6Q_HW_IDX_8822B)
-
+#define BIT_HI6Q_HW_IDX_8822B(x) \
+ (((x) & BIT_MASK_HI6Q_HW_IDX_8822B) << BIT_SHIFT_HI6Q_HW_IDX_8822B)
+#define BITS_HI6Q_HW_IDX_8822B \
+ (BIT_MASK_HI6Q_HW_IDX_8822B << BIT_SHIFT_HI6Q_HW_IDX_8822B)
+#define BIT_CLEAR_HI6Q_HW_IDX_8822B(x) ((x) & (~BITS_HI6Q_HW_IDX_8822B))
+#define BIT_GET_HI6Q_HW_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_HI6Q_HW_IDX_8822B) & BIT_MASK_HI6Q_HW_IDX_8822B)
+#define BIT_SET_HI6Q_HW_IDX_8822B(x, v) \
+ (BIT_CLEAR_HI6Q_HW_IDX_8822B(x) | BIT_HI6Q_HW_IDX_8822B(v))
#define BIT_SHIFT_HI6Q_HOST_IDX_8822B 0
#define BIT_MASK_HI6Q_HOST_IDX_8822B 0xfff
-#define BIT_HI6Q_HOST_IDX_8822B(x) (((x) & BIT_MASK_HI6Q_HOST_IDX_8822B) << BIT_SHIFT_HI6Q_HOST_IDX_8822B)
-#define BIT_GET_HI6Q_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_HI6Q_HOST_IDX_8822B) & BIT_MASK_HI6Q_HOST_IDX_8822B)
-
+#define BIT_HI6Q_HOST_IDX_8822B(x) \
+ (((x) & BIT_MASK_HI6Q_HOST_IDX_8822B) << BIT_SHIFT_HI6Q_HOST_IDX_8822B)
+#define BITS_HI6Q_HOST_IDX_8822B \
+ (BIT_MASK_HI6Q_HOST_IDX_8822B << BIT_SHIFT_HI6Q_HOST_IDX_8822B)
+#define BIT_CLEAR_HI6Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI6Q_HOST_IDX_8822B))
+#define BIT_GET_HI6Q_HOST_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_HI6Q_HOST_IDX_8822B) & BIT_MASK_HI6Q_HOST_IDX_8822B)
+#define BIT_SET_HI6Q_HOST_IDX_8822B(x, v) \
+ (BIT_CLEAR_HI6Q_HOST_IDX_8822B(x) | BIT_HI6Q_HOST_IDX_8822B(v))
/* 2 REG_HI7Q_TXBD_IDX_8822B */
#define BIT_SHIFT_HI7Q_HW_IDX_8822B 16
#define BIT_MASK_HI7Q_HW_IDX_8822B 0xfff
-#define BIT_HI7Q_HW_IDX_8822B(x) (((x) & BIT_MASK_HI7Q_HW_IDX_8822B) << BIT_SHIFT_HI7Q_HW_IDX_8822B)
-#define BIT_GET_HI7Q_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_HI7Q_HW_IDX_8822B) & BIT_MASK_HI7Q_HW_IDX_8822B)
-
+#define BIT_HI7Q_HW_IDX_8822B(x) \
+ (((x) & BIT_MASK_HI7Q_HW_IDX_8822B) << BIT_SHIFT_HI7Q_HW_IDX_8822B)
+#define BITS_HI7Q_HW_IDX_8822B \
+ (BIT_MASK_HI7Q_HW_IDX_8822B << BIT_SHIFT_HI7Q_HW_IDX_8822B)
+#define BIT_CLEAR_HI7Q_HW_IDX_8822B(x) ((x) & (~BITS_HI7Q_HW_IDX_8822B))
+#define BIT_GET_HI7Q_HW_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_HI7Q_HW_IDX_8822B) & BIT_MASK_HI7Q_HW_IDX_8822B)
+#define BIT_SET_HI7Q_HW_IDX_8822B(x, v) \
+ (BIT_CLEAR_HI7Q_HW_IDX_8822B(x) | BIT_HI7Q_HW_IDX_8822B(v))
#define BIT_SHIFT_HI7Q_HOST_IDX_8822B 0
#define BIT_MASK_HI7Q_HOST_IDX_8822B 0xfff
-#define BIT_HI7Q_HOST_IDX_8822B(x) (((x) & BIT_MASK_HI7Q_HOST_IDX_8822B) << BIT_SHIFT_HI7Q_HOST_IDX_8822B)
-#define BIT_GET_HI7Q_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_HI7Q_HOST_IDX_8822B) & BIT_MASK_HI7Q_HOST_IDX_8822B)
-
+#define BIT_HI7Q_HOST_IDX_8822B(x) \
+ (((x) & BIT_MASK_HI7Q_HOST_IDX_8822B) << BIT_SHIFT_HI7Q_HOST_IDX_8822B)
+#define BITS_HI7Q_HOST_IDX_8822B \
+ (BIT_MASK_HI7Q_HOST_IDX_8822B << BIT_SHIFT_HI7Q_HOST_IDX_8822B)
+#define BIT_CLEAR_HI7Q_HOST_IDX_8822B(x) ((x) & (~BITS_HI7Q_HOST_IDX_8822B))
+#define BIT_GET_HI7Q_HOST_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_HI7Q_HOST_IDX_8822B) & BIT_MASK_HI7Q_HOST_IDX_8822B)
+#define BIT_SET_HI7Q_HOST_IDX_8822B(x, v) \
+ (BIT_CLEAR_HI7Q_HOST_IDX_8822B(x) | BIT_HI7Q_HOST_IDX_8822B(v))
/* 2 REG_DBG_SEL_V1_8822B */
#define BIT_SHIFT_DBG_SEL_8822B 0
#define BIT_MASK_DBG_SEL_8822B 0xff
-#define BIT_DBG_SEL_8822B(x) (((x) & BIT_MASK_DBG_SEL_8822B) << BIT_SHIFT_DBG_SEL_8822B)
-#define BIT_GET_DBG_SEL_8822B(x) (((x) >> BIT_SHIFT_DBG_SEL_8822B) & BIT_MASK_DBG_SEL_8822B)
-
+#define BIT_DBG_SEL_8822B(x) \
+ (((x) & BIT_MASK_DBG_SEL_8822B) << BIT_SHIFT_DBG_SEL_8822B)
+#define BITS_DBG_SEL_8822B (BIT_MASK_DBG_SEL_8822B << BIT_SHIFT_DBG_SEL_8822B)
+#define BIT_CLEAR_DBG_SEL_8822B(x) ((x) & (~BITS_DBG_SEL_8822B))
+#define BIT_GET_DBG_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_DBG_SEL_8822B) & BIT_MASK_DBG_SEL_8822B)
+#define BIT_SET_DBG_SEL_8822B(x, v) \
+ (BIT_CLEAR_DBG_SEL_8822B(x) | BIT_DBG_SEL_8822B(v))
/* 2 REG_PCIE_HRPWM1_V1_8822B */
#define BIT_SHIFT_PCIE_HRPWM_8822B 0
#define BIT_MASK_PCIE_HRPWM_8822B 0xff
-#define BIT_PCIE_HRPWM_8822B(x) (((x) & BIT_MASK_PCIE_HRPWM_8822B) << BIT_SHIFT_PCIE_HRPWM_8822B)
-#define BIT_GET_PCIE_HRPWM_8822B(x) (((x) >> BIT_SHIFT_PCIE_HRPWM_8822B) & BIT_MASK_PCIE_HRPWM_8822B)
-
+#define BIT_PCIE_HRPWM_8822B(x) \
+ (((x) & BIT_MASK_PCIE_HRPWM_8822B) << BIT_SHIFT_PCIE_HRPWM_8822B)
+#define BITS_PCIE_HRPWM_8822B \
+ (BIT_MASK_PCIE_HRPWM_8822B << BIT_SHIFT_PCIE_HRPWM_8822B)
+#define BIT_CLEAR_PCIE_HRPWM_8822B(x) ((x) & (~BITS_PCIE_HRPWM_8822B))
+#define BIT_GET_PCIE_HRPWM_8822B(x) \
+ (((x) >> BIT_SHIFT_PCIE_HRPWM_8822B) & BIT_MASK_PCIE_HRPWM_8822B)
+#define BIT_SET_PCIE_HRPWM_8822B(x, v) \
+ (BIT_CLEAR_PCIE_HRPWM_8822B(x) | BIT_PCIE_HRPWM_8822B(v))
/* 2 REG_PCIE_HCPWM1_V1_8822B */
#define BIT_SHIFT_PCIE_HCPWM_8822B 0
#define BIT_MASK_PCIE_HCPWM_8822B 0xff
-#define BIT_PCIE_HCPWM_8822B(x) (((x) & BIT_MASK_PCIE_HCPWM_8822B) << BIT_SHIFT_PCIE_HCPWM_8822B)
-#define BIT_GET_PCIE_HCPWM_8822B(x) (((x) >> BIT_SHIFT_PCIE_HCPWM_8822B) & BIT_MASK_PCIE_HCPWM_8822B)
-
+#define BIT_PCIE_HCPWM_8822B(x) \
+ (((x) & BIT_MASK_PCIE_HCPWM_8822B) << BIT_SHIFT_PCIE_HCPWM_8822B)
+#define BITS_PCIE_HCPWM_8822B \
+ (BIT_MASK_PCIE_HCPWM_8822B << BIT_SHIFT_PCIE_HCPWM_8822B)
+#define BIT_CLEAR_PCIE_HCPWM_8822B(x) ((x) & (~BITS_PCIE_HCPWM_8822B))
+#define BIT_GET_PCIE_HCPWM_8822B(x) \
+ (((x) >> BIT_SHIFT_PCIE_HCPWM_8822B) & BIT_MASK_PCIE_HCPWM_8822B)
+#define BIT_SET_PCIE_HCPWM_8822B(x, v) \
+ (BIT_CLEAR_PCIE_HCPWM_8822B(x) | BIT_PCIE_HCPWM_8822B(v))
/* 2 REG_PCIE_CTRL2_8822B */
#define BIT_DIS_TXDMA_PRE_8822B BIT(7)
@@ -4466,8 +7271,15 @@
#define BIT_SHIFT_HPS_CLKR_PCIE_8822B 4
#define BIT_MASK_HPS_CLKR_PCIE_8822B 0x3
-#define BIT_HPS_CLKR_PCIE_8822B(x) (((x) & BIT_MASK_HPS_CLKR_PCIE_8822B) << BIT_SHIFT_HPS_CLKR_PCIE_8822B)
-#define BIT_GET_HPS_CLKR_PCIE_8822B(x) (((x) >> BIT_SHIFT_HPS_CLKR_PCIE_8822B) & BIT_MASK_HPS_CLKR_PCIE_8822B)
+#define BIT_HPS_CLKR_PCIE_8822B(x) \
+ (((x) & BIT_MASK_HPS_CLKR_PCIE_8822B) << BIT_SHIFT_HPS_CLKR_PCIE_8822B)
+#define BITS_HPS_CLKR_PCIE_8822B \
+ (BIT_MASK_HPS_CLKR_PCIE_8822B << BIT_SHIFT_HPS_CLKR_PCIE_8822B)
+#define BIT_CLEAR_HPS_CLKR_PCIE_8822B(x) ((x) & (~BITS_HPS_CLKR_PCIE_8822B))
+#define BIT_GET_HPS_CLKR_PCIE_8822B(x) \
+ (((x) >> BIT_SHIFT_HPS_CLKR_PCIE_8822B) & BIT_MASK_HPS_CLKR_PCIE_8822B)
+#define BIT_SET_HPS_CLKR_PCIE_8822B(x, v) \
+ (BIT_CLEAR_HPS_CLKR_PCIE_8822B(x) | BIT_HPS_CLKR_PCIE_8822B(v))
#define BIT_PCIE_INT_8822B BIT(3)
#define BIT_TXFLAG_EXIT_L1_EN_8822B BIT(2)
@@ -4478,49 +7290,88 @@
#define BIT_SHIFT_PCIE_HRPWM2_8822B 0
#define BIT_MASK_PCIE_HRPWM2_8822B 0xffff
-#define BIT_PCIE_HRPWM2_8822B(x) (((x) & BIT_MASK_PCIE_HRPWM2_8822B) << BIT_SHIFT_PCIE_HRPWM2_8822B)
-#define BIT_GET_PCIE_HRPWM2_8822B(x) (((x) >> BIT_SHIFT_PCIE_HRPWM2_8822B) & BIT_MASK_PCIE_HRPWM2_8822B)
-
+#define BIT_PCIE_HRPWM2_8822B(x) \
+ (((x) & BIT_MASK_PCIE_HRPWM2_8822B) << BIT_SHIFT_PCIE_HRPWM2_8822B)
+#define BITS_PCIE_HRPWM2_8822B \
+ (BIT_MASK_PCIE_HRPWM2_8822B << BIT_SHIFT_PCIE_HRPWM2_8822B)
+#define BIT_CLEAR_PCIE_HRPWM2_8822B(x) ((x) & (~BITS_PCIE_HRPWM2_8822B))
+#define BIT_GET_PCIE_HRPWM2_8822B(x) \
+ (((x) >> BIT_SHIFT_PCIE_HRPWM2_8822B) & BIT_MASK_PCIE_HRPWM2_8822B)
+#define BIT_SET_PCIE_HRPWM2_8822B(x, v) \
+ (BIT_CLEAR_PCIE_HRPWM2_8822B(x) | BIT_PCIE_HRPWM2_8822B(v))
/* 2 REG_PCIE_HCPWM2_V1_8822B */
#define BIT_SHIFT_PCIE_HCPWM2_8822B 0
#define BIT_MASK_PCIE_HCPWM2_8822B 0xffff
-#define BIT_PCIE_HCPWM2_8822B(x) (((x) & BIT_MASK_PCIE_HCPWM2_8822B) << BIT_SHIFT_PCIE_HCPWM2_8822B)
-#define BIT_GET_PCIE_HCPWM2_8822B(x) (((x) >> BIT_SHIFT_PCIE_HCPWM2_8822B) & BIT_MASK_PCIE_HCPWM2_8822B)
-
+#define BIT_PCIE_HCPWM2_8822B(x) \
+ (((x) & BIT_MASK_PCIE_HCPWM2_8822B) << BIT_SHIFT_PCIE_HCPWM2_8822B)
+#define BITS_PCIE_HCPWM2_8822B \
+ (BIT_MASK_PCIE_HCPWM2_8822B << BIT_SHIFT_PCIE_HCPWM2_8822B)
+#define BIT_CLEAR_PCIE_HCPWM2_8822B(x) ((x) & (~BITS_PCIE_HCPWM2_8822B))
+#define BIT_GET_PCIE_HCPWM2_8822B(x) \
+ (((x) >> BIT_SHIFT_PCIE_HCPWM2_8822B) & BIT_MASK_PCIE_HCPWM2_8822B)
+#define BIT_SET_PCIE_HCPWM2_8822B(x, v) \
+ (BIT_CLEAR_PCIE_HCPWM2_8822B(x) | BIT_PCIE_HCPWM2_8822B(v))
/* 2 REG_PCIE_H2C_MSG_V1_8822B */
#define BIT_SHIFT_DRV2FW_INFO_8822B 0
#define BIT_MASK_DRV2FW_INFO_8822B 0xffffffffL
-#define BIT_DRV2FW_INFO_8822B(x) (((x) & BIT_MASK_DRV2FW_INFO_8822B) << BIT_SHIFT_DRV2FW_INFO_8822B)
-#define BIT_GET_DRV2FW_INFO_8822B(x) (((x) >> BIT_SHIFT_DRV2FW_INFO_8822B) & BIT_MASK_DRV2FW_INFO_8822B)
-
+#define BIT_DRV2FW_INFO_8822B(x) \
+ (((x) & BIT_MASK_DRV2FW_INFO_8822B) << BIT_SHIFT_DRV2FW_INFO_8822B)
+#define BITS_DRV2FW_INFO_8822B \
+ (BIT_MASK_DRV2FW_INFO_8822B << BIT_SHIFT_DRV2FW_INFO_8822B)
+#define BIT_CLEAR_DRV2FW_INFO_8822B(x) ((x) & (~BITS_DRV2FW_INFO_8822B))
+#define BIT_GET_DRV2FW_INFO_8822B(x) \
+ (((x) >> BIT_SHIFT_DRV2FW_INFO_8822B) & BIT_MASK_DRV2FW_INFO_8822B)
+#define BIT_SET_DRV2FW_INFO_8822B(x, v) \
+ (BIT_CLEAR_DRV2FW_INFO_8822B(x) | BIT_DRV2FW_INFO_8822B(v))
/* 2 REG_PCIE_C2H_MSG_V1_8822B */
#define BIT_SHIFT_HCI_PCIE_C2H_MSG_8822B 0
#define BIT_MASK_HCI_PCIE_C2H_MSG_8822B 0xffffffffL
-#define BIT_HCI_PCIE_C2H_MSG_8822B(x) (((x) & BIT_MASK_HCI_PCIE_C2H_MSG_8822B) << BIT_SHIFT_HCI_PCIE_C2H_MSG_8822B)
-#define BIT_GET_HCI_PCIE_C2H_MSG_8822B(x) (((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG_8822B) & BIT_MASK_HCI_PCIE_C2H_MSG_8822B)
-
+#define BIT_HCI_PCIE_C2H_MSG_8822B(x) \
+ (((x) & BIT_MASK_HCI_PCIE_C2H_MSG_8822B) \
+ << BIT_SHIFT_HCI_PCIE_C2H_MSG_8822B)
+#define BITS_HCI_PCIE_C2H_MSG_8822B \
+ (BIT_MASK_HCI_PCIE_C2H_MSG_8822B << BIT_SHIFT_HCI_PCIE_C2H_MSG_8822B)
+#define BIT_CLEAR_HCI_PCIE_C2H_MSG_8822B(x) \
+ ((x) & (~BITS_HCI_PCIE_C2H_MSG_8822B))
+#define BIT_GET_HCI_PCIE_C2H_MSG_8822B(x) \
+ (((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG_8822B) & \
+ BIT_MASK_HCI_PCIE_C2H_MSG_8822B)
+#define BIT_SET_HCI_PCIE_C2H_MSG_8822B(x, v) \
+ (BIT_CLEAR_HCI_PCIE_C2H_MSG_8822B(x) | BIT_HCI_PCIE_C2H_MSG_8822B(v))
/* 2 REG_DBI_WDATA_V1_8822B */
#define BIT_SHIFT_DBI_WDATA_8822B 0
#define BIT_MASK_DBI_WDATA_8822B 0xffffffffL
-#define BIT_DBI_WDATA_8822B(x) (((x) & BIT_MASK_DBI_WDATA_8822B) << BIT_SHIFT_DBI_WDATA_8822B)
-#define BIT_GET_DBI_WDATA_8822B(x) (((x) >> BIT_SHIFT_DBI_WDATA_8822B) & BIT_MASK_DBI_WDATA_8822B)
-
+#define BIT_DBI_WDATA_8822B(x) \
+ (((x) & BIT_MASK_DBI_WDATA_8822B) << BIT_SHIFT_DBI_WDATA_8822B)
+#define BITS_DBI_WDATA_8822B \
+ (BIT_MASK_DBI_WDATA_8822B << BIT_SHIFT_DBI_WDATA_8822B)
+#define BIT_CLEAR_DBI_WDATA_8822B(x) ((x) & (~BITS_DBI_WDATA_8822B))
+#define BIT_GET_DBI_WDATA_8822B(x) \
+ (((x) >> BIT_SHIFT_DBI_WDATA_8822B) & BIT_MASK_DBI_WDATA_8822B)
+#define BIT_SET_DBI_WDATA_8822B(x, v) \
+ (BIT_CLEAR_DBI_WDATA_8822B(x) | BIT_DBI_WDATA_8822B(v))
/* 2 REG_DBI_RDATA_V1_8822B */
#define BIT_SHIFT_DBI_RDATA_8822B 0
#define BIT_MASK_DBI_RDATA_8822B 0xffffffffL
-#define BIT_DBI_RDATA_8822B(x) (((x) & BIT_MASK_DBI_RDATA_8822B) << BIT_SHIFT_DBI_RDATA_8822B)
-#define BIT_GET_DBI_RDATA_8822B(x) (((x) >> BIT_SHIFT_DBI_RDATA_8822B) & BIT_MASK_DBI_RDATA_8822B)
-
+#define BIT_DBI_RDATA_8822B(x) \
+ (((x) & BIT_MASK_DBI_RDATA_8822B) << BIT_SHIFT_DBI_RDATA_8822B)
+#define BITS_DBI_RDATA_8822B \
+ (BIT_MASK_DBI_RDATA_8822B << BIT_SHIFT_DBI_RDATA_8822B)
+#define BIT_CLEAR_DBI_RDATA_8822B(x) ((x) & (~BITS_DBI_RDATA_8822B))
+#define BIT_GET_DBI_RDATA_8822B(x) \
+ (((x) >> BIT_SHIFT_DBI_RDATA_8822B) & BIT_MASK_DBI_RDATA_8822B)
+#define BIT_SET_DBI_RDATA_8822B(x, v) \
+ (BIT_CLEAR_DBI_RDATA_8822B(x) | BIT_DBI_RDATA_8822B(v))
/* 2 REG_DBI_FLAG_V1_8822B */
#define BIT_EN_STUCK_DBG_8822B BIT(26)
@@ -4531,42 +7382,84 @@
#define BIT_SHIFT_DBI_WREN_8822B 12
#define BIT_MASK_DBI_WREN_8822B 0xf
-#define BIT_DBI_WREN_8822B(x) (((x) & BIT_MASK_DBI_WREN_8822B) << BIT_SHIFT_DBI_WREN_8822B)
-#define BIT_GET_DBI_WREN_8822B(x) (((x) >> BIT_SHIFT_DBI_WREN_8822B) & BIT_MASK_DBI_WREN_8822B)
-
+#define BIT_DBI_WREN_8822B(x) \
+ (((x) & BIT_MASK_DBI_WREN_8822B) << BIT_SHIFT_DBI_WREN_8822B)
+#define BITS_DBI_WREN_8822B \
+ (BIT_MASK_DBI_WREN_8822B << BIT_SHIFT_DBI_WREN_8822B)
+#define BIT_CLEAR_DBI_WREN_8822B(x) ((x) & (~BITS_DBI_WREN_8822B))
+#define BIT_GET_DBI_WREN_8822B(x) \
+ (((x) >> BIT_SHIFT_DBI_WREN_8822B) & BIT_MASK_DBI_WREN_8822B)
+#define BIT_SET_DBI_WREN_8822B(x, v) \
+ (BIT_CLEAR_DBI_WREN_8822B(x) | BIT_DBI_WREN_8822B(v))
#define BIT_SHIFT_DBI_ADDR_8822B 0
#define BIT_MASK_DBI_ADDR_8822B 0xfff
-#define BIT_DBI_ADDR_8822B(x) (((x) & BIT_MASK_DBI_ADDR_8822B) << BIT_SHIFT_DBI_ADDR_8822B)
-#define BIT_GET_DBI_ADDR_8822B(x) (((x) >> BIT_SHIFT_DBI_ADDR_8822B) & BIT_MASK_DBI_ADDR_8822B)
-
+#define BIT_DBI_ADDR_8822B(x) \
+ (((x) & BIT_MASK_DBI_ADDR_8822B) << BIT_SHIFT_DBI_ADDR_8822B)
+#define BITS_DBI_ADDR_8822B \
+ (BIT_MASK_DBI_ADDR_8822B << BIT_SHIFT_DBI_ADDR_8822B)
+#define BIT_CLEAR_DBI_ADDR_8822B(x) ((x) & (~BITS_DBI_ADDR_8822B))
+#define BIT_GET_DBI_ADDR_8822B(x) \
+ (((x) >> BIT_SHIFT_DBI_ADDR_8822B) & BIT_MASK_DBI_ADDR_8822B)
+#define BIT_SET_DBI_ADDR_8822B(x, v) \
+ (BIT_CLEAR_DBI_ADDR_8822B(x) | BIT_DBI_ADDR_8822B(v))
/* 2 REG_MDIO_V1_8822B */
#define BIT_SHIFT_MDIO_RDATA_8822B 16
#define BIT_MASK_MDIO_RDATA_8822B 0xffff
-#define BIT_MDIO_RDATA_8822B(x) (((x) & BIT_MASK_MDIO_RDATA_8822B) << BIT_SHIFT_MDIO_RDATA_8822B)
-#define BIT_GET_MDIO_RDATA_8822B(x) (((x) >> BIT_SHIFT_MDIO_RDATA_8822B) & BIT_MASK_MDIO_RDATA_8822B)
-
+#define BIT_MDIO_RDATA_8822B(x) \
+ (((x) & BIT_MASK_MDIO_RDATA_8822B) << BIT_SHIFT_MDIO_RDATA_8822B)
+#define BITS_MDIO_RDATA_8822B \
+ (BIT_MASK_MDIO_RDATA_8822B << BIT_SHIFT_MDIO_RDATA_8822B)
+#define BIT_CLEAR_MDIO_RDATA_8822B(x) ((x) & (~BITS_MDIO_RDATA_8822B))
+#define BIT_GET_MDIO_RDATA_8822B(x) \
+ (((x) >> BIT_SHIFT_MDIO_RDATA_8822B) & BIT_MASK_MDIO_RDATA_8822B)
+#define BIT_SET_MDIO_RDATA_8822B(x, v) \
+ (BIT_CLEAR_MDIO_RDATA_8822B(x) | BIT_MDIO_RDATA_8822B(v))
#define BIT_SHIFT_MDIO_WDATA_8822B 0
#define BIT_MASK_MDIO_WDATA_8822B 0xffff
-#define BIT_MDIO_WDATA_8822B(x) (((x) & BIT_MASK_MDIO_WDATA_8822B) << BIT_SHIFT_MDIO_WDATA_8822B)
-#define BIT_GET_MDIO_WDATA_8822B(x) (((x) >> BIT_SHIFT_MDIO_WDATA_8822B) & BIT_MASK_MDIO_WDATA_8822B)
-
+#define BIT_MDIO_WDATA_8822B(x) \
+ (((x) & BIT_MASK_MDIO_WDATA_8822B) << BIT_SHIFT_MDIO_WDATA_8822B)
+#define BITS_MDIO_WDATA_8822B \
+ (BIT_MASK_MDIO_WDATA_8822B << BIT_SHIFT_MDIO_WDATA_8822B)
+#define BIT_CLEAR_MDIO_WDATA_8822B(x) ((x) & (~BITS_MDIO_WDATA_8822B))
+#define BIT_GET_MDIO_WDATA_8822B(x) \
+ (((x) >> BIT_SHIFT_MDIO_WDATA_8822B) & BIT_MASK_MDIO_WDATA_8822B)
+#define BIT_SET_MDIO_WDATA_8822B(x, v) \
+ (BIT_CLEAR_MDIO_WDATA_8822B(x) | BIT_MDIO_WDATA_8822B(v))
/* 2 REG_PCIE_MIX_CFG_8822B */
#define BIT_SHIFT_MDIO_PHY_ADDR_8822B 24
#define BIT_MASK_MDIO_PHY_ADDR_8822B 0x1f
-#define BIT_MDIO_PHY_ADDR_8822B(x) (((x) & BIT_MASK_MDIO_PHY_ADDR_8822B) << BIT_SHIFT_MDIO_PHY_ADDR_8822B)
-#define BIT_GET_MDIO_PHY_ADDR_8822B(x) (((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8822B) & BIT_MASK_MDIO_PHY_ADDR_8822B)
-
+#define BIT_MDIO_PHY_ADDR_8822B(x) \
+ (((x) & BIT_MASK_MDIO_PHY_ADDR_8822B) << BIT_SHIFT_MDIO_PHY_ADDR_8822B)
+#define BITS_MDIO_PHY_ADDR_8822B \
+ (BIT_MASK_MDIO_PHY_ADDR_8822B << BIT_SHIFT_MDIO_PHY_ADDR_8822B)
+#define BIT_CLEAR_MDIO_PHY_ADDR_8822B(x) ((x) & (~BITS_MDIO_PHY_ADDR_8822B))
+#define BIT_GET_MDIO_PHY_ADDR_8822B(x) \
+ (((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8822B) & BIT_MASK_MDIO_PHY_ADDR_8822B)
+#define BIT_SET_MDIO_PHY_ADDR_8822B(x, v) \
+ (BIT_CLEAR_MDIO_PHY_ADDR_8822B(x) | BIT_MDIO_PHY_ADDR_8822B(v))
#define BIT_SHIFT_WATCH_DOG_RECORD_V1_8822B 10
#define BIT_MASK_WATCH_DOG_RECORD_V1_8822B 0x3fff
-#define BIT_WATCH_DOG_RECORD_V1_8822B(x) (((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8822B) << BIT_SHIFT_WATCH_DOG_RECORD_V1_8822B)
-#define BIT_GET_WATCH_DOG_RECORD_V1_8822B(x) (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8822B) & BIT_MASK_WATCH_DOG_RECORD_V1_8822B)
+#define BIT_WATCH_DOG_RECORD_V1_8822B(x) \
+ (((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8822B) \
+ << BIT_SHIFT_WATCH_DOG_RECORD_V1_8822B)
+#define BITS_WATCH_DOG_RECORD_V1_8822B \
+ (BIT_MASK_WATCH_DOG_RECORD_V1_8822B \
+ << BIT_SHIFT_WATCH_DOG_RECORD_V1_8822B)
+#define BIT_CLEAR_WATCH_DOG_RECORD_V1_8822B(x) \
+ ((x) & (~BITS_WATCH_DOG_RECORD_V1_8822B))
+#define BIT_GET_WATCH_DOG_RECORD_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8822B) & \
+ BIT_MASK_WATCH_DOG_RECORD_V1_8822B)
+#define BIT_SET_WATCH_DOG_RECORD_V1_8822B(x, v) \
+ (BIT_CLEAR_WATCH_DOG_RECORD_V1_8822B(x) | \
+ BIT_WATCH_DOG_RECORD_V1_8822B(v))
#define BIT_R_IO_TIMEOUT_FLAG_V1_8822B BIT(9)
#define BIT_EN_WATCH_DOG_8822B BIT(8)
@@ -4576,30 +7469,66 @@
#define BIT_SHIFT_MDIO_REG_ADDR_V1_8822B 0
#define BIT_MASK_MDIO_REG_ADDR_V1_8822B 0x1f
-#define BIT_MDIO_REG_ADDR_V1_8822B(x) (((x) & BIT_MASK_MDIO_REG_ADDR_V1_8822B) << BIT_SHIFT_MDIO_REG_ADDR_V1_8822B)
-#define BIT_GET_MDIO_REG_ADDR_V1_8822B(x) (((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1_8822B) & BIT_MASK_MDIO_REG_ADDR_V1_8822B)
-
+#define BIT_MDIO_REG_ADDR_V1_8822B(x) \
+ (((x) & BIT_MASK_MDIO_REG_ADDR_V1_8822B) \
+ << BIT_SHIFT_MDIO_REG_ADDR_V1_8822B)
+#define BITS_MDIO_REG_ADDR_V1_8822B \
+ (BIT_MASK_MDIO_REG_ADDR_V1_8822B << BIT_SHIFT_MDIO_REG_ADDR_V1_8822B)
+#define BIT_CLEAR_MDIO_REG_ADDR_V1_8822B(x) \
+ ((x) & (~BITS_MDIO_REG_ADDR_V1_8822B))
+#define BIT_GET_MDIO_REG_ADDR_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1_8822B) & \
+ BIT_MASK_MDIO_REG_ADDR_V1_8822B)
+#define BIT_SET_MDIO_REG_ADDR_V1_8822B(x, v) \
+ (BIT_CLEAR_MDIO_REG_ADDR_V1_8822B(x) | BIT_MDIO_REG_ADDR_V1_8822B(v))
/* 2 REG_HCI_MIX_CFG_8822B */
#define BIT_HOST_GEN2_SUPPORT_8822B BIT(20)
#define BIT_SHIFT_TXDMA_ERR_FLAG_8822B 16
#define BIT_MASK_TXDMA_ERR_FLAG_8822B 0xf
-#define BIT_TXDMA_ERR_FLAG_8822B(x) (((x) & BIT_MASK_TXDMA_ERR_FLAG_8822B) << BIT_SHIFT_TXDMA_ERR_FLAG_8822B)
-#define BIT_GET_TXDMA_ERR_FLAG_8822B(x) (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_8822B) & BIT_MASK_TXDMA_ERR_FLAG_8822B)
-
+#define BIT_TXDMA_ERR_FLAG_8822B(x) \
+ (((x) & BIT_MASK_TXDMA_ERR_FLAG_8822B) \
+ << BIT_SHIFT_TXDMA_ERR_FLAG_8822B)
+#define BITS_TXDMA_ERR_FLAG_8822B \
+ (BIT_MASK_TXDMA_ERR_FLAG_8822B << BIT_SHIFT_TXDMA_ERR_FLAG_8822B)
+#define BIT_CLEAR_TXDMA_ERR_FLAG_8822B(x) ((x) & (~BITS_TXDMA_ERR_FLAG_8822B))
+#define BIT_GET_TXDMA_ERR_FLAG_8822B(x) \
+ (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_8822B) & \
+ BIT_MASK_TXDMA_ERR_FLAG_8822B)
+#define BIT_SET_TXDMA_ERR_FLAG_8822B(x, v) \
+ (BIT_CLEAR_TXDMA_ERR_FLAG_8822B(x) | BIT_TXDMA_ERR_FLAG_8822B(v))
#define BIT_SHIFT_EARLY_MODE_SEL_8822B 12
#define BIT_MASK_EARLY_MODE_SEL_8822B 0xf
-#define BIT_EARLY_MODE_SEL_8822B(x) (((x) & BIT_MASK_EARLY_MODE_SEL_8822B) << BIT_SHIFT_EARLY_MODE_SEL_8822B)
-#define BIT_GET_EARLY_MODE_SEL_8822B(x) (((x) >> BIT_SHIFT_EARLY_MODE_SEL_8822B) & BIT_MASK_EARLY_MODE_SEL_8822B)
+#define BIT_EARLY_MODE_SEL_8822B(x) \
+ (((x) & BIT_MASK_EARLY_MODE_SEL_8822B) \
+ << BIT_SHIFT_EARLY_MODE_SEL_8822B)
+#define BITS_EARLY_MODE_SEL_8822B \
+ (BIT_MASK_EARLY_MODE_SEL_8822B << BIT_SHIFT_EARLY_MODE_SEL_8822B)
+#define BIT_CLEAR_EARLY_MODE_SEL_8822B(x) ((x) & (~BITS_EARLY_MODE_SEL_8822B))
+#define BIT_GET_EARLY_MODE_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_EARLY_MODE_SEL_8822B) & \
+ BIT_MASK_EARLY_MODE_SEL_8822B)
+#define BIT_SET_EARLY_MODE_SEL_8822B(x, v) \
+ (BIT_CLEAR_EARLY_MODE_SEL_8822B(x) | BIT_EARLY_MODE_SEL_8822B(v))
#define BIT_EPHY_RX50_EN_8822B BIT(11)
#define BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822B 8
#define BIT_MASK_MSI_TIMEOUT_ID_V1_8822B 0x7
-#define BIT_MSI_TIMEOUT_ID_V1_8822B(x) (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8822B) << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822B)
-#define BIT_GET_MSI_TIMEOUT_ID_V1_8822B(x) (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822B) & BIT_MASK_MSI_TIMEOUT_ID_V1_8822B)
+#define BIT_MSI_TIMEOUT_ID_V1_8822B(x) \
+ (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8822B) \
+ << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822B)
+#define BITS_MSI_TIMEOUT_ID_V1_8822B \
+ (BIT_MASK_MSI_TIMEOUT_ID_V1_8822B << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822B)
+#define BIT_CLEAR_MSI_TIMEOUT_ID_V1_8822B(x) \
+ ((x) & (~BITS_MSI_TIMEOUT_ID_V1_8822B))
+#define BIT_GET_MSI_TIMEOUT_ID_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822B) & \
+ BIT_MASK_MSI_TIMEOUT_ID_V1_8822B)
+#define BIT_SET_MSI_TIMEOUT_ID_V1_8822B(x, v) \
+ (BIT_CLEAR_MSI_TIMEOUT_ID_V1_8822B(x) | BIT_MSI_TIMEOUT_ID_V1_8822B(v))
#define BIT_RADDR_RD_8822B BIT(7)
#define BIT_EN_MUL_TAG_8822B BIT(6)
@@ -4614,36 +7543,77 @@
#define BIT_SHIFT_STC_INT_FLAG_8822B 16
#define BIT_MASK_STC_INT_FLAG_8822B 0xff
-#define BIT_STC_INT_FLAG_8822B(x) (((x) & BIT_MASK_STC_INT_FLAG_8822B) << BIT_SHIFT_STC_INT_FLAG_8822B)
-#define BIT_GET_STC_INT_FLAG_8822B(x) (((x) >> BIT_SHIFT_STC_INT_FLAG_8822B) & BIT_MASK_STC_INT_FLAG_8822B)
-
+#define BIT_STC_INT_FLAG_8822B(x) \
+ (((x) & BIT_MASK_STC_INT_FLAG_8822B) << BIT_SHIFT_STC_INT_FLAG_8822B)
+#define BITS_STC_INT_FLAG_8822B \
+ (BIT_MASK_STC_INT_FLAG_8822B << BIT_SHIFT_STC_INT_FLAG_8822B)
+#define BIT_CLEAR_STC_INT_FLAG_8822B(x) ((x) & (~BITS_STC_INT_FLAG_8822B))
+#define BIT_GET_STC_INT_FLAG_8822B(x) \
+ (((x) >> BIT_SHIFT_STC_INT_FLAG_8822B) & BIT_MASK_STC_INT_FLAG_8822B)
+#define BIT_SET_STC_INT_FLAG_8822B(x, v) \
+ (BIT_CLEAR_STC_INT_FLAG_8822B(x) | BIT_STC_INT_FLAG_8822B(v))
#define BIT_SHIFT_STC_INT_IDX_8822B 8
#define BIT_MASK_STC_INT_IDX_8822B 0x7
-#define BIT_STC_INT_IDX_8822B(x) (((x) & BIT_MASK_STC_INT_IDX_8822B) << BIT_SHIFT_STC_INT_IDX_8822B)
-#define BIT_GET_STC_INT_IDX_8822B(x) (((x) >> BIT_SHIFT_STC_INT_IDX_8822B) & BIT_MASK_STC_INT_IDX_8822B)
-
+#define BIT_STC_INT_IDX_8822B(x) \
+ (((x) & BIT_MASK_STC_INT_IDX_8822B) << BIT_SHIFT_STC_INT_IDX_8822B)
+#define BITS_STC_INT_IDX_8822B \
+ (BIT_MASK_STC_INT_IDX_8822B << BIT_SHIFT_STC_INT_IDX_8822B)
+#define BIT_CLEAR_STC_INT_IDX_8822B(x) ((x) & (~BITS_STC_INT_IDX_8822B))
+#define BIT_GET_STC_INT_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_STC_INT_IDX_8822B) & BIT_MASK_STC_INT_IDX_8822B)
+#define BIT_SET_STC_INT_IDX_8822B(x, v) \
+ (BIT_CLEAR_STC_INT_IDX_8822B(x) | BIT_STC_INT_IDX_8822B(v))
#define BIT_SHIFT_STC_INT_REALTIME_CS_8822B 0
#define BIT_MASK_STC_INT_REALTIME_CS_8822B 0x3f
-#define BIT_STC_INT_REALTIME_CS_8822B(x) (((x) & BIT_MASK_STC_INT_REALTIME_CS_8822B) << BIT_SHIFT_STC_INT_REALTIME_CS_8822B)
-#define BIT_GET_STC_INT_REALTIME_CS_8822B(x) (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8822B) & BIT_MASK_STC_INT_REALTIME_CS_8822B)
-
+#define BIT_STC_INT_REALTIME_CS_8822B(x) \
+ (((x) & BIT_MASK_STC_INT_REALTIME_CS_8822B) \
+ << BIT_SHIFT_STC_INT_REALTIME_CS_8822B)
+#define BITS_STC_INT_REALTIME_CS_8822B \
+ (BIT_MASK_STC_INT_REALTIME_CS_8822B \
+ << BIT_SHIFT_STC_INT_REALTIME_CS_8822B)
+#define BIT_CLEAR_STC_INT_REALTIME_CS_8822B(x) \
+ ((x) & (~BITS_STC_INT_REALTIME_CS_8822B))
+#define BIT_GET_STC_INT_REALTIME_CS_8822B(x) \
+ (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8822B) & \
+ BIT_MASK_STC_INT_REALTIME_CS_8822B)
+#define BIT_SET_STC_INT_REALTIME_CS_8822B(x, v) \
+ (BIT_CLEAR_STC_INT_REALTIME_CS_8822B(x) | \
+ BIT_STC_INT_REALTIME_CS_8822B(v))
/* 2 REG_ST_INT_CFG_8822B(PCIE STATE CHANGE INTERRUPT CONFIGURATION) */
#define BIT_STC_INT_GRP_EN_8822B BIT(31)
#define BIT_SHIFT_STC_INT_EXPECT_LS_8822B 8
#define BIT_MASK_STC_INT_EXPECT_LS_8822B 0x3f
-#define BIT_STC_INT_EXPECT_LS_8822B(x) (((x) & BIT_MASK_STC_INT_EXPECT_LS_8822B) << BIT_SHIFT_STC_INT_EXPECT_LS_8822B)
-#define BIT_GET_STC_INT_EXPECT_LS_8822B(x) (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8822B) & BIT_MASK_STC_INT_EXPECT_LS_8822B)
-
+#define BIT_STC_INT_EXPECT_LS_8822B(x) \
+ (((x) & BIT_MASK_STC_INT_EXPECT_LS_8822B) \
+ << BIT_SHIFT_STC_INT_EXPECT_LS_8822B)
+#define BITS_STC_INT_EXPECT_LS_8822B \
+ (BIT_MASK_STC_INT_EXPECT_LS_8822B << BIT_SHIFT_STC_INT_EXPECT_LS_8822B)
+#define BIT_CLEAR_STC_INT_EXPECT_LS_8822B(x) \
+ ((x) & (~BITS_STC_INT_EXPECT_LS_8822B))
+#define BIT_GET_STC_INT_EXPECT_LS_8822B(x) \
+ (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8822B) & \
+ BIT_MASK_STC_INT_EXPECT_LS_8822B)
+#define BIT_SET_STC_INT_EXPECT_LS_8822B(x, v) \
+ (BIT_CLEAR_STC_INT_EXPECT_LS_8822B(x) | BIT_STC_INT_EXPECT_LS_8822B(v))
#define BIT_SHIFT_STC_INT_EXPECT_CS_8822B 0
#define BIT_MASK_STC_INT_EXPECT_CS_8822B 0x3f
-#define BIT_STC_INT_EXPECT_CS_8822B(x) (((x) & BIT_MASK_STC_INT_EXPECT_CS_8822B) << BIT_SHIFT_STC_INT_EXPECT_CS_8822B)
-#define BIT_GET_STC_INT_EXPECT_CS_8822B(x) (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8822B) & BIT_MASK_STC_INT_EXPECT_CS_8822B)
-
+#define BIT_STC_INT_EXPECT_CS_8822B(x) \
+ (((x) & BIT_MASK_STC_INT_EXPECT_CS_8822B) \
+ << BIT_SHIFT_STC_INT_EXPECT_CS_8822B)
+#define BITS_STC_INT_EXPECT_CS_8822B \
+ (BIT_MASK_STC_INT_EXPECT_CS_8822B << BIT_SHIFT_STC_INT_EXPECT_CS_8822B)
+#define BIT_CLEAR_STC_INT_EXPECT_CS_8822B(x) \
+ ((x) & (~BITS_STC_INT_EXPECT_CS_8822B))
+#define BIT_GET_STC_INT_EXPECT_CS_8822B(x) \
+ (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8822B) & \
+ BIT_MASK_STC_INT_EXPECT_CS_8822B)
+#define BIT_SET_STC_INT_EXPECT_CS_8822B(x, v) \
+ (BIT_CLEAR_STC_INT_EXPECT_CS_8822B(x) | BIT_STC_INT_EXPECT_CS_8822B(v))
/* 2 REG_CMU_DLY_CTRL_8822B(PCIE PHY CLOCK MGT UNIT DELAY CONTROL ) */
#define BIT_CMU_DLY_EN_8822B BIT(31)
@@ -4651,247 +7621,583 @@
#define BIT_SHIFT_CMU_DLY_PRE_DIV_8822B 0
#define BIT_MASK_CMU_DLY_PRE_DIV_8822B 0xff
-#define BIT_CMU_DLY_PRE_DIV_8822B(x) (((x) & BIT_MASK_CMU_DLY_PRE_DIV_8822B) << BIT_SHIFT_CMU_DLY_PRE_DIV_8822B)
-#define BIT_GET_CMU_DLY_PRE_DIV_8822B(x) (((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV_8822B) & BIT_MASK_CMU_DLY_PRE_DIV_8822B)
-
+#define BIT_CMU_DLY_PRE_DIV_8822B(x) \
+ (((x) & BIT_MASK_CMU_DLY_PRE_DIV_8822B) \
+ << BIT_SHIFT_CMU_DLY_PRE_DIV_8822B)
+#define BITS_CMU_DLY_PRE_DIV_8822B \
+ (BIT_MASK_CMU_DLY_PRE_DIV_8822B << BIT_SHIFT_CMU_DLY_PRE_DIV_8822B)
+#define BIT_CLEAR_CMU_DLY_PRE_DIV_8822B(x) ((x) & (~BITS_CMU_DLY_PRE_DIV_8822B))
+#define BIT_GET_CMU_DLY_PRE_DIV_8822B(x) \
+ (((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV_8822B) & \
+ BIT_MASK_CMU_DLY_PRE_DIV_8822B)
+#define BIT_SET_CMU_DLY_PRE_DIV_8822B(x, v) \
+ (BIT_CLEAR_CMU_DLY_PRE_DIV_8822B(x) | BIT_CMU_DLY_PRE_DIV_8822B(v))
/* 2 REG_CMU_DLY_CFG_8822B(PCIE PHY CLOCK MGT UNIT DELAY CONFIGURATION ) */
#define BIT_SHIFT_CMU_DLY_LTR_A2I_8822B 24
#define BIT_MASK_CMU_DLY_LTR_A2I_8822B 0xff
-#define BIT_CMU_DLY_LTR_A2I_8822B(x) (((x) & BIT_MASK_CMU_DLY_LTR_A2I_8822B) << BIT_SHIFT_CMU_DLY_LTR_A2I_8822B)
-#define BIT_GET_CMU_DLY_LTR_A2I_8822B(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I_8822B) & BIT_MASK_CMU_DLY_LTR_A2I_8822B)
-
+#define BIT_CMU_DLY_LTR_A2I_8822B(x) \
+ (((x) & BIT_MASK_CMU_DLY_LTR_A2I_8822B) \
+ << BIT_SHIFT_CMU_DLY_LTR_A2I_8822B)
+#define BITS_CMU_DLY_LTR_A2I_8822B \
+ (BIT_MASK_CMU_DLY_LTR_A2I_8822B << BIT_SHIFT_CMU_DLY_LTR_A2I_8822B)
+#define BIT_CLEAR_CMU_DLY_LTR_A2I_8822B(x) ((x) & (~BITS_CMU_DLY_LTR_A2I_8822B))
+#define BIT_GET_CMU_DLY_LTR_A2I_8822B(x) \
+ (((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I_8822B) & \
+ BIT_MASK_CMU_DLY_LTR_A2I_8822B)
+#define BIT_SET_CMU_DLY_LTR_A2I_8822B(x, v) \
+ (BIT_CLEAR_CMU_DLY_LTR_A2I_8822B(x) | BIT_CMU_DLY_LTR_A2I_8822B(v))
#define BIT_SHIFT_CMU_DLY_LTR_I2A_8822B 16
#define BIT_MASK_CMU_DLY_LTR_I2A_8822B 0xff
-#define BIT_CMU_DLY_LTR_I2A_8822B(x) (((x) & BIT_MASK_CMU_DLY_LTR_I2A_8822B) << BIT_SHIFT_CMU_DLY_LTR_I2A_8822B)
-#define BIT_GET_CMU_DLY_LTR_I2A_8822B(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A_8822B) & BIT_MASK_CMU_DLY_LTR_I2A_8822B)
-
+#define BIT_CMU_DLY_LTR_I2A_8822B(x) \
+ (((x) & BIT_MASK_CMU_DLY_LTR_I2A_8822B) \
+ << BIT_SHIFT_CMU_DLY_LTR_I2A_8822B)
+#define BITS_CMU_DLY_LTR_I2A_8822B \
+ (BIT_MASK_CMU_DLY_LTR_I2A_8822B << BIT_SHIFT_CMU_DLY_LTR_I2A_8822B)
+#define BIT_CLEAR_CMU_DLY_LTR_I2A_8822B(x) ((x) & (~BITS_CMU_DLY_LTR_I2A_8822B))
+#define BIT_GET_CMU_DLY_LTR_I2A_8822B(x) \
+ (((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A_8822B) & \
+ BIT_MASK_CMU_DLY_LTR_I2A_8822B)
+#define BIT_SET_CMU_DLY_LTR_I2A_8822B(x, v) \
+ (BIT_CLEAR_CMU_DLY_LTR_I2A_8822B(x) | BIT_CMU_DLY_LTR_I2A_8822B(v))
#define BIT_SHIFT_CMU_DLY_LTR_IDLE_8822B 8
#define BIT_MASK_CMU_DLY_LTR_IDLE_8822B 0xff
-#define BIT_CMU_DLY_LTR_IDLE_8822B(x) (((x) & BIT_MASK_CMU_DLY_LTR_IDLE_8822B) << BIT_SHIFT_CMU_DLY_LTR_IDLE_8822B)
-#define BIT_GET_CMU_DLY_LTR_IDLE_8822B(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE_8822B) & BIT_MASK_CMU_DLY_LTR_IDLE_8822B)
-
+#define BIT_CMU_DLY_LTR_IDLE_8822B(x) \
+ (((x) & BIT_MASK_CMU_DLY_LTR_IDLE_8822B) \
+ << BIT_SHIFT_CMU_DLY_LTR_IDLE_8822B)
+#define BITS_CMU_DLY_LTR_IDLE_8822B \
+ (BIT_MASK_CMU_DLY_LTR_IDLE_8822B << BIT_SHIFT_CMU_DLY_LTR_IDLE_8822B)
+#define BIT_CLEAR_CMU_DLY_LTR_IDLE_8822B(x) \
+ ((x) & (~BITS_CMU_DLY_LTR_IDLE_8822B))
+#define BIT_GET_CMU_DLY_LTR_IDLE_8822B(x) \
+ (((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE_8822B) & \
+ BIT_MASK_CMU_DLY_LTR_IDLE_8822B)
+#define BIT_SET_CMU_DLY_LTR_IDLE_8822B(x, v) \
+ (BIT_CLEAR_CMU_DLY_LTR_IDLE_8822B(x) | BIT_CMU_DLY_LTR_IDLE_8822B(v))
#define BIT_SHIFT_CMU_DLY_LTR_ACT_8822B 0
#define BIT_MASK_CMU_DLY_LTR_ACT_8822B 0xff
-#define BIT_CMU_DLY_LTR_ACT_8822B(x) (((x) & BIT_MASK_CMU_DLY_LTR_ACT_8822B) << BIT_SHIFT_CMU_DLY_LTR_ACT_8822B)
-#define BIT_GET_CMU_DLY_LTR_ACT_8822B(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT_8822B) & BIT_MASK_CMU_DLY_LTR_ACT_8822B)
-
+#define BIT_CMU_DLY_LTR_ACT_8822B(x) \
+ (((x) & BIT_MASK_CMU_DLY_LTR_ACT_8822B) \
+ << BIT_SHIFT_CMU_DLY_LTR_ACT_8822B)
+#define BITS_CMU_DLY_LTR_ACT_8822B \
+ (BIT_MASK_CMU_DLY_LTR_ACT_8822B << BIT_SHIFT_CMU_DLY_LTR_ACT_8822B)
+#define BIT_CLEAR_CMU_DLY_LTR_ACT_8822B(x) ((x) & (~BITS_CMU_DLY_LTR_ACT_8822B))
+#define BIT_GET_CMU_DLY_LTR_ACT_8822B(x) \
+ (((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT_8822B) & \
+ BIT_MASK_CMU_DLY_LTR_ACT_8822B)
+#define BIT_SET_CMU_DLY_LTR_ACT_8822B(x, v) \
+ (BIT_CLEAR_CMU_DLY_LTR_ACT_8822B(x) | BIT_CMU_DLY_LTR_ACT_8822B(v))
/* 2 REG_H2CQ_TXBD_DESA_8822B */
#define BIT_SHIFT_H2CQ_TXBD_DESA_8822B 0
#define BIT_MASK_H2CQ_TXBD_DESA_8822B 0xffffffffffffffffL
-#define BIT_H2CQ_TXBD_DESA_8822B(x) (((x) & BIT_MASK_H2CQ_TXBD_DESA_8822B) << BIT_SHIFT_H2CQ_TXBD_DESA_8822B)
-#define BIT_GET_H2CQ_TXBD_DESA_8822B(x) (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_8822B) & BIT_MASK_H2CQ_TXBD_DESA_8822B)
-
+#define BIT_H2CQ_TXBD_DESA_8822B(x) \
+ (((x) & BIT_MASK_H2CQ_TXBD_DESA_8822B) \
+ << BIT_SHIFT_H2CQ_TXBD_DESA_8822B)
+#define BITS_H2CQ_TXBD_DESA_8822B \
+ (BIT_MASK_H2CQ_TXBD_DESA_8822B << BIT_SHIFT_H2CQ_TXBD_DESA_8822B)
+#define BIT_CLEAR_H2CQ_TXBD_DESA_8822B(x) ((x) & (~BITS_H2CQ_TXBD_DESA_8822B))
+#define BIT_GET_H2CQ_TXBD_DESA_8822B(x) \
+ (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_8822B) & \
+ BIT_MASK_H2CQ_TXBD_DESA_8822B)
+#define BIT_SET_H2CQ_TXBD_DESA_8822B(x, v) \
+ (BIT_CLEAR_H2CQ_TXBD_DESA_8822B(x) | BIT_H2CQ_TXBD_DESA_8822B(v))
/* 2 REG_H2CQ_TXBD_NUM_8822B */
#define BIT_PCIE_H2CQ_FLAG_8822B BIT(14)
#define BIT_SHIFT_H2CQ_DESC_MODE_8822B 12
#define BIT_MASK_H2CQ_DESC_MODE_8822B 0x3
-#define BIT_H2CQ_DESC_MODE_8822B(x) (((x) & BIT_MASK_H2CQ_DESC_MODE_8822B) << BIT_SHIFT_H2CQ_DESC_MODE_8822B)
-#define BIT_GET_H2CQ_DESC_MODE_8822B(x) (((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8822B) & BIT_MASK_H2CQ_DESC_MODE_8822B)
-
+#define BIT_H2CQ_DESC_MODE_8822B(x) \
+ (((x) & BIT_MASK_H2CQ_DESC_MODE_8822B) \
+ << BIT_SHIFT_H2CQ_DESC_MODE_8822B)
+#define BITS_H2CQ_DESC_MODE_8822B \
+ (BIT_MASK_H2CQ_DESC_MODE_8822B << BIT_SHIFT_H2CQ_DESC_MODE_8822B)
+#define BIT_CLEAR_H2CQ_DESC_MODE_8822B(x) ((x) & (~BITS_H2CQ_DESC_MODE_8822B))
+#define BIT_GET_H2CQ_DESC_MODE_8822B(x) \
+ (((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8822B) & \
+ BIT_MASK_H2CQ_DESC_MODE_8822B)
+#define BIT_SET_H2CQ_DESC_MODE_8822B(x, v) \
+ (BIT_CLEAR_H2CQ_DESC_MODE_8822B(x) | BIT_H2CQ_DESC_MODE_8822B(v))
#define BIT_SHIFT_H2CQ_DESC_NUM_8822B 0
#define BIT_MASK_H2CQ_DESC_NUM_8822B 0xfff
-#define BIT_H2CQ_DESC_NUM_8822B(x) (((x) & BIT_MASK_H2CQ_DESC_NUM_8822B) << BIT_SHIFT_H2CQ_DESC_NUM_8822B)
-#define BIT_GET_H2CQ_DESC_NUM_8822B(x) (((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8822B) & BIT_MASK_H2CQ_DESC_NUM_8822B)
-
+#define BIT_H2CQ_DESC_NUM_8822B(x) \
+ (((x) & BIT_MASK_H2CQ_DESC_NUM_8822B) << BIT_SHIFT_H2CQ_DESC_NUM_8822B)
+#define BITS_H2CQ_DESC_NUM_8822B \
+ (BIT_MASK_H2CQ_DESC_NUM_8822B << BIT_SHIFT_H2CQ_DESC_NUM_8822B)
+#define BIT_CLEAR_H2CQ_DESC_NUM_8822B(x) ((x) & (~BITS_H2CQ_DESC_NUM_8822B))
+#define BIT_GET_H2CQ_DESC_NUM_8822B(x) \
+ (((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8822B) & BIT_MASK_H2CQ_DESC_NUM_8822B)
+#define BIT_SET_H2CQ_DESC_NUM_8822B(x, v) \
+ (BIT_CLEAR_H2CQ_DESC_NUM_8822B(x) | BIT_H2CQ_DESC_NUM_8822B(v))
/* 2 REG_H2CQ_TXBD_IDX_8822B */
#define BIT_SHIFT_H2CQ_HW_IDX_8822B 16
#define BIT_MASK_H2CQ_HW_IDX_8822B 0xfff
-#define BIT_H2CQ_HW_IDX_8822B(x) (((x) & BIT_MASK_H2CQ_HW_IDX_8822B) << BIT_SHIFT_H2CQ_HW_IDX_8822B)
-#define BIT_GET_H2CQ_HW_IDX_8822B(x) (((x) >> BIT_SHIFT_H2CQ_HW_IDX_8822B) & BIT_MASK_H2CQ_HW_IDX_8822B)
-
+#define BIT_H2CQ_HW_IDX_8822B(x) \
+ (((x) & BIT_MASK_H2CQ_HW_IDX_8822B) << BIT_SHIFT_H2CQ_HW_IDX_8822B)
+#define BITS_H2CQ_HW_IDX_8822B \
+ (BIT_MASK_H2CQ_HW_IDX_8822B << BIT_SHIFT_H2CQ_HW_IDX_8822B)
+#define BIT_CLEAR_H2CQ_HW_IDX_8822B(x) ((x) & (~BITS_H2CQ_HW_IDX_8822B))
+#define BIT_GET_H2CQ_HW_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_H2CQ_HW_IDX_8822B) & BIT_MASK_H2CQ_HW_IDX_8822B)
+#define BIT_SET_H2CQ_HW_IDX_8822B(x, v) \
+ (BIT_CLEAR_H2CQ_HW_IDX_8822B(x) | BIT_H2CQ_HW_IDX_8822B(v))
#define BIT_SHIFT_H2CQ_HOST_IDX_8822B 0
#define BIT_MASK_H2CQ_HOST_IDX_8822B 0xfff
-#define BIT_H2CQ_HOST_IDX_8822B(x) (((x) & BIT_MASK_H2CQ_HOST_IDX_8822B) << BIT_SHIFT_H2CQ_HOST_IDX_8822B)
-#define BIT_GET_H2CQ_HOST_IDX_8822B(x) (((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8822B) & BIT_MASK_H2CQ_HOST_IDX_8822B)
-
+#define BIT_H2CQ_HOST_IDX_8822B(x) \
+ (((x) & BIT_MASK_H2CQ_HOST_IDX_8822B) << BIT_SHIFT_H2CQ_HOST_IDX_8822B)
+#define BITS_H2CQ_HOST_IDX_8822B \
+ (BIT_MASK_H2CQ_HOST_IDX_8822B << BIT_SHIFT_H2CQ_HOST_IDX_8822B)
+#define BIT_CLEAR_H2CQ_HOST_IDX_8822B(x) ((x) & (~BITS_H2CQ_HOST_IDX_8822B))
+#define BIT_GET_H2CQ_HOST_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8822B) & BIT_MASK_H2CQ_HOST_IDX_8822B)
+#define BIT_SET_H2CQ_HOST_IDX_8822B(x, v) \
+ (BIT_CLEAR_H2CQ_HOST_IDX_8822B(x) | BIT_H2CQ_HOST_IDX_8822B(v))
/* 2 REG_H2CQ_CSR_8822B[31:0] (H2CQ CONTROL AND STATUS) */
#define BIT_H2CQ_FULL_8822B BIT(31)
#define BIT_CLR_H2CQ_HOST_IDX_8822B BIT(16)
#define BIT_CLR_H2CQ_HW_IDX_8822B BIT(8)
+#define BIT_STOP_H2CQ_8822B BIT(0)
+
+/* 2 REG_CHANGE_PCIE_SPEED_8822B */
+#define BIT_CHANGE_PCIE_SPEED_8822B BIT(18)
+
+#define BIT_SHIFT_GEN1_GEN2_8822B 16
+#define BIT_MASK_GEN1_GEN2_8822B 0x3
+#define BIT_GEN1_GEN2_8822B(x) \
+ (((x) & BIT_MASK_GEN1_GEN2_8822B) << BIT_SHIFT_GEN1_GEN2_8822B)
+#define BITS_GEN1_GEN2_8822B \
+ (BIT_MASK_GEN1_GEN2_8822B << BIT_SHIFT_GEN1_GEN2_8822B)
+#define BIT_CLEAR_GEN1_GEN2_8822B(x) ((x) & (~BITS_GEN1_GEN2_8822B))
+#define BIT_GET_GEN1_GEN2_8822B(x) \
+ (((x) >> BIT_SHIFT_GEN1_GEN2_8822B) & BIT_MASK_GEN1_GEN2_8822B)
+#define BIT_SET_GEN1_GEN2_8822B(x, v) \
+ (BIT_CLEAR_GEN1_GEN2_8822B(x) | BIT_GEN1_GEN2_8822B(v))
+
+#define BIT_SHIFT_RXDMA_ERROR_COUNTER_8822B 8
+#define BIT_MASK_RXDMA_ERROR_COUNTER_8822B 0xff
+#define BIT_RXDMA_ERROR_COUNTER_8822B(x) \
+ (((x) & BIT_MASK_RXDMA_ERROR_COUNTER_8822B) \
+ << BIT_SHIFT_RXDMA_ERROR_COUNTER_8822B)
+#define BITS_RXDMA_ERROR_COUNTER_8822B \
+ (BIT_MASK_RXDMA_ERROR_COUNTER_8822B \
+ << BIT_SHIFT_RXDMA_ERROR_COUNTER_8822B)
+#define BIT_CLEAR_RXDMA_ERROR_COUNTER_8822B(x) \
+ ((x) & (~BITS_RXDMA_ERROR_COUNTER_8822B))
+#define BIT_GET_RXDMA_ERROR_COUNTER_8822B(x) \
+ (((x) >> BIT_SHIFT_RXDMA_ERROR_COUNTER_8822B) & \
+ BIT_MASK_RXDMA_ERROR_COUNTER_8822B)
+#define BIT_SET_RXDMA_ERROR_COUNTER_8822B(x, v) \
+ (BIT_CLEAR_RXDMA_ERROR_COUNTER_8822B(x) | \
+ BIT_RXDMA_ERROR_COUNTER_8822B(v))
+
+#define BIT_TXDMA_ERROR_HANDLE_STATUS_8822B BIT(7)
+#define BIT_TXDMA_ERROR_PULSE_8822B BIT(6)
+#define BIT_TXDMA_STUCK_ERROR_HANDLE_ENABLE_8822B BIT(5)
+#define BIT_TXDMA_RETURN_ERROR_ENABLE_8822B BIT(4)
+#define BIT_RXDMA_ERROR_HANDLE_STATUS_8822B BIT(3)
+
+#define BIT_SHIFT_AUTO_HANG_RELEASE_8822B 0
+#define BIT_MASK_AUTO_HANG_RELEASE_8822B 0x7
+#define BIT_AUTO_HANG_RELEASE_8822B(x) \
+ (((x) & BIT_MASK_AUTO_HANG_RELEASE_8822B) \
+ << BIT_SHIFT_AUTO_HANG_RELEASE_8822B)
+#define BITS_AUTO_HANG_RELEASE_8822B \
+ (BIT_MASK_AUTO_HANG_RELEASE_8822B << BIT_SHIFT_AUTO_HANG_RELEASE_8822B)
+#define BIT_CLEAR_AUTO_HANG_RELEASE_8822B(x) \
+ ((x) & (~BITS_AUTO_HANG_RELEASE_8822B))
+#define BIT_GET_AUTO_HANG_RELEASE_8822B(x) \
+ (((x) >> BIT_SHIFT_AUTO_HANG_RELEASE_8822B) & \
+ BIT_MASK_AUTO_HANG_RELEASE_8822B)
+#define BIT_SET_AUTO_HANG_RELEASE_8822B(x, v) \
+ (BIT_CLEAR_AUTO_HANG_RELEASE_8822B(x) | BIT_AUTO_HANG_RELEASE_8822B(v))
+
+/* 2 REG_OLD_DEHANG_8822B */
+#define BIT_OLD_DEHANG_8822B BIT(1)
/* 2 REG_Q0_INFO_8822B */
#define BIT_SHIFT_QUEUEMACID_Q0_V1_8822B 25
#define BIT_MASK_QUEUEMACID_Q0_V1_8822B 0x7f
-#define BIT_QUEUEMACID_Q0_V1_8822B(x) (((x) & BIT_MASK_QUEUEMACID_Q0_V1_8822B) << BIT_SHIFT_QUEUEMACID_Q0_V1_8822B)
-#define BIT_GET_QUEUEMACID_Q0_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1_8822B) & BIT_MASK_QUEUEMACID_Q0_V1_8822B)
-
+#define BIT_QUEUEMACID_Q0_V1_8822B(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q0_V1_8822B) \
+ << BIT_SHIFT_QUEUEMACID_Q0_V1_8822B)
+#define BITS_QUEUEMACID_Q0_V1_8822B \
+ (BIT_MASK_QUEUEMACID_Q0_V1_8822B << BIT_SHIFT_QUEUEMACID_Q0_V1_8822B)
+#define BIT_CLEAR_QUEUEMACID_Q0_V1_8822B(x) \
+ ((x) & (~BITS_QUEUEMACID_Q0_V1_8822B))
+#define BIT_GET_QUEUEMACID_Q0_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1_8822B) & \
+ BIT_MASK_QUEUEMACID_Q0_V1_8822B)
+#define BIT_SET_QUEUEMACID_Q0_V1_8822B(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q0_V1_8822B(x) | BIT_QUEUEMACID_Q0_V1_8822B(v))
#define BIT_SHIFT_QUEUEAC_Q0_V1_8822B 23
#define BIT_MASK_QUEUEAC_Q0_V1_8822B 0x3
-#define BIT_QUEUEAC_Q0_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_Q0_V1_8822B) << BIT_SHIFT_QUEUEAC_Q0_V1_8822B)
-#define BIT_GET_QUEUEAC_Q0_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q0_V1_8822B) & BIT_MASK_QUEUEAC_Q0_V1_8822B)
+#define BIT_QUEUEAC_Q0_V1_8822B(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q0_V1_8822B) << BIT_SHIFT_QUEUEAC_Q0_V1_8822B)
+#define BITS_QUEUEAC_Q0_V1_8822B \
+ (BIT_MASK_QUEUEAC_Q0_V1_8822B << BIT_SHIFT_QUEUEAC_Q0_V1_8822B)
+#define BIT_CLEAR_QUEUEAC_Q0_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q0_V1_8822B))
+#define BIT_GET_QUEUEAC_Q0_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q0_V1_8822B) & BIT_MASK_QUEUEAC_Q0_V1_8822B)
+#define BIT_SET_QUEUEAC_Q0_V1_8822B(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q0_V1_8822B(x) | BIT_QUEUEAC_Q0_V1_8822B(v))
#define BIT_TIDEMPTY_Q0_V1_8822B BIT(22)
#define BIT_SHIFT_TAIL_PKT_Q0_V2_8822B 11
#define BIT_MASK_TAIL_PKT_Q0_V2_8822B 0x7ff
-#define BIT_TAIL_PKT_Q0_V2_8822B(x) (((x) & BIT_MASK_TAIL_PKT_Q0_V2_8822B) << BIT_SHIFT_TAIL_PKT_Q0_V2_8822B)
-#define BIT_GET_TAIL_PKT_Q0_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2_8822B) & BIT_MASK_TAIL_PKT_Q0_V2_8822B)
-
+#define BIT_TAIL_PKT_Q0_V2_8822B(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q0_V2_8822B) \
+ << BIT_SHIFT_TAIL_PKT_Q0_V2_8822B)
+#define BITS_TAIL_PKT_Q0_V2_8822B \
+ (BIT_MASK_TAIL_PKT_Q0_V2_8822B << BIT_SHIFT_TAIL_PKT_Q0_V2_8822B)
+#define BIT_CLEAR_TAIL_PKT_Q0_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q0_V2_8822B))
+#define BIT_GET_TAIL_PKT_Q0_V2_8822B(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2_8822B) & \
+ BIT_MASK_TAIL_PKT_Q0_V2_8822B)
+#define BIT_SET_TAIL_PKT_Q0_V2_8822B(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q0_V2_8822B(x) | BIT_TAIL_PKT_Q0_V2_8822B(v))
#define BIT_SHIFT_HEAD_PKT_Q0_V1_8822B 0
#define BIT_MASK_HEAD_PKT_Q0_V1_8822B 0x7ff
-#define BIT_HEAD_PKT_Q0_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_Q0_V1_8822B) << BIT_SHIFT_HEAD_PKT_Q0_V1_8822B)
-#define BIT_GET_HEAD_PKT_Q0_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1_8822B) & BIT_MASK_HEAD_PKT_Q0_V1_8822B)
-
+#define BIT_HEAD_PKT_Q0_V1_8822B(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q0_V1_8822B) \
+ << BIT_SHIFT_HEAD_PKT_Q0_V1_8822B)
+#define BITS_HEAD_PKT_Q0_V1_8822B \
+ (BIT_MASK_HEAD_PKT_Q0_V1_8822B << BIT_SHIFT_HEAD_PKT_Q0_V1_8822B)
+#define BIT_CLEAR_HEAD_PKT_Q0_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q0_V1_8822B))
+#define BIT_GET_HEAD_PKT_Q0_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1_8822B) & \
+ BIT_MASK_HEAD_PKT_Q0_V1_8822B)
+#define BIT_SET_HEAD_PKT_Q0_V1_8822B(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q0_V1_8822B(x) | BIT_HEAD_PKT_Q0_V1_8822B(v))
/* 2 REG_Q1_INFO_8822B */
#define BIT_SHIFT_QUEUEMACID_Q1_V1_8822B 25
#define BIT_MASK_QUEUEMACID_Q1_V1_8822B 0x7f
-#define BIT_QUEUEMACID_Q1_V1_8822B(x) (((x) & BIT_MASK_QUEUEMACID_Q1_V1_8822B) << BIT_SHIFT_QUEUEMACID_Q1_V1_8822B)
-#define BIT_GET_QUEUEMACID_Q1_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1_8822B) & BIT_MASK_QUEUEMACID_Q1_V1_8822B)
-
+#define BIT_QUEUEMACID_Q1_V1_8822B(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q1_V1_8822B) \
+ << BIT_SHIFT_QUEUEMACID_Q1_V1_8822B)
+#define BITS_QUEUEMACID_Q1_V1_8822B \
+ (BIT_MASK_QUEUEMACID_Q1_V1_8822B << BIT_SHIFT_QUEUEMACID_Q1_V1_8822B)
+#define BIT_CLEAR_QUEUEMACID_Q1_V1_8822B(x) \
+ ((x) & (~BITS_QUEUEMACID_Q1_V1_8822B))
+#define BIT_GET_QUEUEMACID_Q1_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1_8822B) & \
+ BIT_MASK_QUEUEMACID_Q1_V1_8822B)
+#define BIT_SET_QUEUEMACID_Q1_V1_8822B(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q1_V1_8822B(x) | BIT_QUEUEMACID_Q1_V1_8822B(v))
#define BIT_SHIFT_QUEUEAC_Q1_V1_8822B 23
#define BIT_MASK_QUEUEAC_Q1_V1_8822B 0x3
-#define BIT_QUEUEAC_Q1_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_Q1_V1_8822B) << BIT_SHIFT_QUEUEAC_Q1_V1_8822B)
-#define BIT_GET_QUEUEAC_Q1_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q1_V1_8822B) & BIT_MASK_QUEUEAC_Q1_V1_8822B)
+#define BIT_QUEUEAC_Q1_V1_8822B(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q1_V1_8822B) << BIT_SHIFT_QUEUEAC_Q1_V1_8822B)
+#define BITS_QUEUEAC_Q1_V1_8822B \
+ (BIT_MASK_QUEUEAC_Q1_V1_8822B << BIT_SHIFT_QUEUEAC_Q1_V1_8822B)
+#define BIT_CLEAR_QUEUEAC_Q1_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q1_V1_8822B))
+#define BIT_GET_QUEUEAC_Q1_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q1_V1_8822B) & BIT_MASK_QUEUEAC_Q1_V1_8822B)
+#define BIT_SET_QUEUEAC_Q1_V1_8822B(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q1_V1_8822B(x) | BIT_QUEUEAC_Q1_V1_8822B(v))
#define BIT_TIDEMPTY_Q1_V1_8822B BIT(22)
#define BIT_SHIFT_TAIL_PKT_Q1_V2_8822B 11
#define BIT_MASK_TAIL_PKT_Q1_V2_8822B 0x7ff
-#define BIT_TAIL_PKT_Q1_V2_8822B(x) (((x) & BIT_MASK_TAIL_PKT_Q1_V2_8822B) << BIT_SHIFT_TAIL_PKT_Q1_V2_8822B)
-#define BIT_GET_TAIL_PKT_Q1_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2_8822B) & BIT_MASK_TAIL_PKT_Q1_V2_8822B)
-
+#define BIT_TAIL_PKT_Q1_V2_8822B(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q1_V2_8822B) \
+ << BIT_SHIFT_TAIL_PKT_Q1_V2_8822B)
+#define BITS_TAIL_PKT_Q1_V2_8822B \
+ (BIT_MASK_TAIL_PKT_Q1_V2_8822B << BIT_SHIFT_TAIL_PKT_Q1_V2_8822B)
+#define BIT_CLEAR_TAIL_PKT_Q1_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q1_V2_8822B))
+#define BIT_GET_TAIL_PKT_Q1_V2_8822B(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2_8822B) & \
+ BIT_MASK_TAIL_PKT_Q1_V2_8822B)
+#define BIT_SET_TAIL_PKT_Q1_V2_8822B(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q1_V2_8822B(x) | BIT_TAIL_PKT_Q1_V2_8822B(v))
#define BIT_SHIFT_HEAD_PKT_Q1_V1_8822B 0
#define BIT_MASK_HEAD_PKT_Q1_V1_8822B 0x7ff
-#define BIT_HEAD_PKT_Q1_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_Q1_V1_8822B) << BIT_SHIFT_HEAD_PKT_Q1_V1_8822B)
-#define BIT_GET_HEAD_PKT_Q1_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1_8822B) & BIT_MASK_HEAD_PKT_Q1_V1_8822B)
-
+#define BIT_HEAD_PKT_Q1_V1_8822B(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q1_V1_8822B) \
+ << BIT_SHIFT_HEAD_PKT_Q1_V1_8822B)
+#define BITS_HEAD_PKT_Q1_V1_8822B \
+ (BIT_MASK_HEAD_PKT_Q1_V1_8822B << BIT_SHIFT_HEAD_PKT_Q1_V1_8822B)
+#define BIT_CLEAR_HEAD_PKT_Q1_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q1_V1_8822B))
+#define BIT_GET_HEAD_PKT_Q1_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1_8822B) & \
+ BIT_MASK_HEAD_PKT_Q1_V1_8822B)
+#define BIT_SET_HEAD_PKT_Q1_V1_8822B(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q1_V1_8822B(x) | BIT_HEAD_PKT_Q1_V1_8822B(v))
/* 2 REG_Q2_INFO_8822B */
#define BIT_SHIFT_QUEUEMACID_Q2_V1_8822B 25
#define BIT_MASK_QUEUEMACID_Q2_V1_8822B 0x7f
-#define BIT_QUEUEMACID_Q2_V1_8822B(x) (((x) & BIT_MASK_QUEUEMACID_Q2_V1_8822B) << BIT_SHIFT_QUEUEMACID_Q2_V1_8822B)
-#define BIT_GET_QUEUEMACID_Q2_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1_8822B) & BIT_MASK_QUEUEMACID_Q2_V1_8822B)
-
+#define BIT_QUEUEMACID_Q2_V1_8822B(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q2_V1_8822B) \
+ << BIT_SHIFT_QUEUEMACID_Q2_V1_8822B)
+#define BITS_QUEUEMACID_Q2_V1_8822B \
+ (BIT_MASK_QUEUEMACID_Q2_V1_8822B << BIT_SHIFT_QUEUEMACID_Q2_V1_8822B)
+#define BIT_CLEAR_QUEUEMACID_Q2_V1_8822B(x) \
+ ((x) & (~BITS_QUEUEMACID_Q2_V1_8822B))
+#define BIT_GET_QUEUEMACID_Q2_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1_8822B) & \
+ BIT_MASK_QUEUEMACID_Q2_V1_8822B)
+#define BIT_SET_QUEUEMACID_Q2_V1_8822B(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q2_V1_8822B(x) | BIT_QUEUEMACID_Q2_V1_8822B(v))
#define BIT_SHIFT_QUEUEAC_Q2_V1_8822B 23
#define BIT_MASK_QUEUEAC_Q2_V1_8822B 0x3
-#define BIT_QUEUEAC_Q2_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_Q2_V1_8822B) << BIT_SHIFT_QUEUEAC_Q2_V1_8822B)
-#define BIT_GET_QUEUEAC_Q2_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q2_V1_8822B) & BIT_MASK_QUEUEAC_Q2_V1_8822B)
+#define BIT_QUEUEAC_Q2_V1_8822B(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q2_V1_8822B) << BIT_SHIFT_QUEUEAC_Q2_V1_8822B)
+#define BITS_QUEUEAC_Q2_V1_8822B \
+ (BIT_MASK_QUEUEAC_Q2_V1_8822B << BIT_SHIFT_QUEUEAC_Q2_V1_8822B)
+#define BIT_CLEAR_QUEUEAC_Q2_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q2_V1_8822B))
+#define BIT_GET_QUEUEAC_Q2_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q2_V1_8822B) & BIT_MASK_QUEUEAC_Q2_V1_8822B)
+#define BIT_SET_QUEUEAC_Q2_V1_8822B(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q2_V1_8822B(x) | BIT_QUEUEAC_Q2_V1_8822B(v))
#define BIT_TIDEMPTY_Q2_V1_8822B BIT(22)
#define BIT_SHIFT_TAIL_PKT_Q2_V2_8822B 11
#define BIT_MASK_TAIL_PKT_Q2_V2_8822B 0x7ff
-#define BIT_TAIL_PKT_Q2_V2_8822B(x) (((x) & BIT_MASK_TAIL_PKT_Q2_V2_8822B) << BIT_SHIFT_TAIL_PKT_Q2_V2_8822B)
-#define BIT_GET_TAIL_PKT_Q2_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2_8822B) & BIT_MASK_TAIL_PKT_Q2_V2_8822B)
-
+#define BIT_TAIL_PKT_Q2_V2_8822B(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q2_V2_8822B) \
+ << BIT_SHIFT_TAIL_PKT_Q2_V2_8822B)
+#define BITS_TAIL_PKT_Q2_V2_8822B \
+ (BIT_MASK_TAIL_PKT_Q2_V2_8822B << BIT_SHIFT_TAIL_PKT_Q2_V2_8822B)
+#define BIT_CLEAR_TAIL_PKT_Q2_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q2_V2_8822B))
+#define BIT_GET_TAIL_PKT_Q2_V2_8822B(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2_8822B) & \
+ BIT_MASK_TAIL_PKT_Q2_V2_8822B)
+#define BIT_SET_TAIL_PKT_Q2_V2_8822B(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q2_V2_8822B(x) | BIT_TAIL_PKT_Q2_V2_8822B(v))
#define BIT_SHIFT_HEAD_PKT_Q2_V1_8822B 0
#define BIT_MASK_HEAD_PKT_Q2_V1_8822B 0x7ff
-#define BIT_HEAD_PKT_Q2_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_Q2_V1_8822B) << BIT_SHIFT_HEAD_PKT_Q2_V1_8822B)
-#define BIT_GET_HEAD_PKT_Q2_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1_8822B) & BIT_MASK_HEAD_PKT_Q2_V1_8822B)
-
+#define BIT_HEAD_PKT_Q2_V1_8822B(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q2_V1_8822B) \
+ << BIT_SHIFT_HEAD_PKT_Q2_V1_8822B)
+#define BITS_HEAD_PKT_Q2_V1_8822B \
+ (BIT_MASK_HEAD_PKT_Q2_V1_8822B << BIT_SHIFT_HEAD_PKT_Q2_V1_8822B)
+#define BIT_CLEAR_HEAD_PKT_Q2_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q2_V1_8822B))
+#define BIT_GET_HEAD_PKT_Q2_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1_8822B) & \
+ BIT_MASK_HEAD_PKT_Q2_V1_8822B)
+#define BIT_SET_HEAD_PKT_Q2_V1_8822B(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q2_V1_8822B(x) | BIT_HEAD_PKT_Q2_V1_8822B(v))
/* 2 REG_Q3_INFO_8822B */
#define BIT_SHIFT_QUEUEMACID_Q3_V1_8822B 25
#define BIT_MASK_QUEUEMACID_Q3_V1_8822B 0x7f
-#define BIT_QUEUEMACID_Q3_V1_8822B(x) (((x) & BIT_MASK_QUEUEMACID_Q3_V1_8822B) << BIT_SHIFT_QUEUEMACID_Q3_V1_8822B)
-#define BIT_GET_QUEUEMACID_Q3_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1_8822B) & BIT_MASK_QUEUEMACID_Q3_V1_8822B)
-
+#define BIT_QUEUEMACID_Q3_V1_8822B(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q3_V1_8822B) \
+ << BIT_SHIFT_QUEUEMACID_Q3_V1_8822B)
+#define BITS_QUEUEMACID_Q3_V1_8822B \
+ (BIT_MASK_QUEUEMACID_Q3_V1_8822B << BIT_SHIFT_QUEUEMACID_Q3_V1_8822B)
+#define BIT_CLEAR_QUEUEMACID_Q3_V1_8822B(x) \
+ ((x) & (~BITS_QUEUEMACID_Q3_V1_8822B))
+#define BIT_GET_QUEUEMACID_Q3_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1_8822B) & \
+ BIT_MASK_QUEUEMACID_Q3_V1_8822B)
+#define BIT_SET_QUEUEMACID_Q3_V1_8822B(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q3_V1_8822B(x) | BIT_QUEUEMACID_Q3_V1_8822B(v))
#define BIT_SHIFT_QUEUEAC_Q3_V1_8822B 23
#define BIT_MASK_QUEUEAC_Q3_V1_8822B 0x3
-#define BIT_QUEUEAC_Q3_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_Q3_V1_8822B) << BIT_SHIFT_QUEUEAC_Q3_V1_8822B)
-#define BIT_GET_QUEUEAC_Q3_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q3_V1_8822B) & BIT_MASK_QUEUEAC_Q3_V1_8822B)
+#define BIT_QUEUEAC_Q3_V1_8822B(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q3_V1_8822B) << BIT_SHIFT_QUEUEAC_Q3_V1_8822B)
+#define BITS_QUEUEAC_Q3_V1_8822B \
+ (BIT_MASK_QUEUEAC_Q3_V1_8822B << BIT_SHIFT_QUEUEAC_Q3_V1_8822B)
+#define BIT_CLEAR_QUEUEAC_Q3_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q3_V1_8822B))
+#define BIT_GET_QUEUEAC_Q3_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q3_V1_8822B) & BIT_MASK_QUEUEAC_Q3_V1_8822B)
+#define BIT_SET_QUEUEAC_Q3_V1_8822B(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q3_V1_8822B(x) | BIT_QUEUEAC_Q3_V1_8822B(v))
#define BIT_TIDEMPTY_Q3_V1_8822B BIT(22)
#define BIT_SHIFT_TAIL_PKT_Q3_V2_8822B 11
#define BIT_MASK_TAIL_PKT_Q3_V2_8822B 0x7ff
-#define BIT_TAIL_PKT_Q3_V2_8822B(x) (((x) & BIT_MASK_TAIL_PKT_Q3_V2_8822B) << BIT_SHIFT_TAIL_PKT_Q3_V2_8822B)
-#define BIT_GET_TAIL_PKT_Q3_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2_8822B) & BIT_MASK_TAIL_PKT_Q3_V2_8822B)
-
+#define BIT_TAIL_PKT_Q3_V2_8822B(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q3_V2_8822B) \
+ << BIT_SHIFT_TAIL_PKT_Q3_V2_8822B)
+#define BITS_TAIL_PKT_Q3_V2_8822B \
+ (BIT_MASK_TAIL_PKT_Q3_V2_8822B << BIT_SHIFT_TAIL_PKT_Q3_V2_8822B)
+#define BIT_CLEAR_TAIL_PKT_Q3_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q3_V2_8822B))
+#define BIT_GET_TAIL_PKT_Q3_V2_8822B(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2_8822B) & \
+ BIT_MASK_TAIL_PKT_Q3_V2_8822B)
+#define BIT_SET_TAIL_PKT_Q3_V2_8822B(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q3_V2_8822B(x) | BIT_TAIL_PKT_Q3_V2_8822B(v))
#define BIT_SHIFT_HEAD_PKT_Q3_V1_8822B 0
#define BIT_MASK_HEAD_PKT_Q3_V1_8822B 0x7ff
-#define BIT_HEAD_PKT_Q3_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_Q3_V1_8822B) << BIT_SHIFT_HEAD_PKT_Q3_V1_8822B)
-#define BIT_GET_HEAD_PKT_Q3_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1_8822B) & BIT_MASK_HEAD_PKT_Q3_V1_8822B)
-
+#define BIT_HEAD_PKT_Q3_V1_8822B(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q3_V1_8822B) \
+ << BIT_SHIFT_HEAD_PKT_Q3_V1_8822B)
+#define BITS_HEAD_PKT_Q3_V1_8822B \
+ (BIT_MASK_HEAD_PKT_Q3_V1_8822B << BIT_SHIFT_HEAD_PKT_Q3_V1_8822B)
+#define BIT_CLEAR_HEAD_PKT_Q3_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q3_V1_8822B))
+#define BIT_GET_HEAD_PKT_Q3_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1_8822B) & \
+ BIT_MASK_HEAD_PKT_Q3_V1_8822B)
+#define BIT_SET_HEAD_PKT_Q3_V1_8822B(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q3_V1_8822B(x) | BIT_HEAD_PKT_Q3_V1_8822B(v))
/* 2 REG_MGQ_INFO_8822B */
#define BIT_SHIFT_QUEUEMACID_MGQ_V1_8822B 25
#define BIT_MASK_QUEUEMACID_MGQ_V1_8822B 0x7f
-#define BIT_QUEUEMACID_MGQ_V1_8822B(x) (((x) & BIT_MASK_QUEUEMACID_MGQ_V1_8822B) << BIT_SHIFT_QUEUEMACID_MGQ_V1_8822B)
-#define BIT_GET_QUEUEMACID_MGQ_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1_8822B) & BIT_MASK_QUEUEMACID_MGQ_V1_8822B)
-
+#define BIT_QUEUEMACID_MGQ_V1_8822B(x) \
+ (((x) & BIT_MASK_QUEUEMACID_MGQ_V1_8822B) \
+ << BIT_SHIFT_QUEUEMACID_MGQ_V1_8822B)
+#define BITS_QUEUEMACID_MGQ_V1_8822B \
+ (BIT_MASK_QUEUEMACID_MGQ_V1_8822B << BIT_SHIFT_QUEUEMACID_MGQ_V1_8822B)
+#define BIT_CLEAR_QUEUEMACID_MGQ_V1_8822B(x) \
+ ((x) & (~BITS_QUEUEMACID_MGQ_V1_8822B))
+#define BIT_GET_QUEUEMACID_MGQ_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1_8822B) & \
+ BIT_MASK_QUEUEMACID_MGQ_V1_8822B)
+#define BIT_SET_QUEUEMACID_MGQ_V1_8822B(x, v) \
+ (BIT_CLEAR_QUEUEMACID_MGQ_V1_8822B(x) | BIT_QUEUEMACID_MGQ_V1_8822B(v))
#define BIT_SHIFT_QUEUEAC_MGQ_V1_8822B 23
#define BIT_MASK_QUEUEAC_MGQ_V1_8822B 0x3
-#define BIT_QUEUEAC_MGQ_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_MGQ_V1_8822B) << BIT_SHIFT_QUEUEAC_MGQ_V1_8822B)
-#define BIT_GET_QUEUEAC_MGQ_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1_8822B) & BIT_MASK_QUEUEAC_MGQ_V1_8822B)
+#define BIT_QUEUEAC_MGQ_V1_8822B(x) \
+ (((x) & BIT_MASK_QUEUEAC_MGQ_V1_8822B) \
+ << BIT_SHIFT_QUEUEAC_MGQ_V1_8822B)
+#define BITS_QUEUEAC_MGQ_V1_8822B \
+ (BIT_MASK_QUEUEAC_MGQ_V1_8822B << BIT_SHIFT_QUEUEAC_MGQ_V1_8822B)
+#define BIT_CLEAR_QUEUEAC_MGQ_V1_8822B(x) ((x) & (~BITS_QUEUEAC_MGQ_V1_8822B))
+#define BIT_GET_QUEUEAC_MGQ_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1_8822B) & \
+ BIT_MASK_QUEUEAC_MGQ_V1_8822B)
+#define BIT_SET_QUEUEAC_MGQ_V1_8822B(x, v) \
+ (BIT_CLEAR_QUEUEAC_MGQ_V1_8822B(x) | BIT_QUEUEAC_MGQ_V1_8822B(v))
#define BIT_TIDEMPTY_MGQ_V1_8822B BIT(22)
#define BIT_SHIFT_TAIL_PKT_MGQ_V2_8822B 11
#define BIT_MASK_TAIL_PKT_MGQ_V2_8822B 0x7ff
-#define BIT_TAIL_PKT_MGQ_V2_8822B(x) (((x) & BIT_MASK_TAIL_PKT_MGQ_V2_8822B) << BIT_SHIFT_TAIL_PKT_MGQ_V2_8822B)
-#define BIT_GET_TAIL_PKT_MGQ_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2_8822B) & BIT_MASK_TAIL_PKT_MGQ_V2_8822B)
-
+#define BIT_TAIL_PKT_MGQ_V2_8822B(x) \
+ (((x) & BIT_MASK_TAIL_PKT_MGQ_V2_8822B) \
+ << BIT_SHIFT_TAIL_PKT_MGQ_V2_8822B)
+#define BITS_TAIL_PKT_MGQ_V2_8822B \
+ (BIT_MASK_TAIL_PKT_MGQ_V2_8822B << BIT_SHIFT_TAIL_PKT_MGQ_V2_8822B)
+#define BIT_CLEAR_TAIL_PKT_MGQ_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_MGQ_V2_8822B))
+#define BIT_GET_TAIL_PKT_MGQ_V2_8822B(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2_8822B) & \
+ BIT_MASK_TAIL_PKT_MGQ_V2_8822B)
+#define BIT_SET_TAIL_PKT_MGQ_V2_8822B(x, v) \
+ (BIT_CLEAR_TAIL_PKT_MGQ_V2_8822B(x) | BIT_TAIL_PKT_MGQ_V2_8822B(v))
#define BIT_SHIFT_HEAD_PKT_MGQ_V1_8822B 0
#define BIT_MASK_HEAD_PKT_MGQ_V1_8822B 0x7ff
-#define BIT_HEAD_PKT_MGQ_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_MGQ_V1_8822B) << BIT_SHIFT_HEAD_PKT_MGQ_V1_8822B)
-#define BIT_GET_HEAD_PKT_MGQ_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1_8822B) & BIT_MASK_HEAD_PKT_MGQ_V1_8822B)
-
+#define BIT_HEAD_PKT_MGQ_V1_8822B(x) \
+ (((x) & BIT_MASK_HEAD_PKT_MGQ_V1_8822B) \
+ << BIT_SHIFT_HEAD_PKT_MGQ_V1_8822B)
+#define BITS_HEAD_PKT_MGQ_V1_8822B \
+ (BIT_MASK_HEAD_PKT_MGQ_V1_8822B << BIT_SHIFT_HEAD_PKT_MGQ_V1_8822B)
+#define BIT_CLEAR_HEAD_PKT_MGQ_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_MGQ_V1_8822B))
+#define BIT_GET_HEAD_PKT_MGQ_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1_8822B) & \
+ BIT_MASK_HEAD_PKT_MGQ_V1_8822B)
+#define BIT_SET_HEAD_PKT_MGQ_V1_8822B(x, v) \
+ (BIT_CLEAR_HEAD_PKT_MGQ_V1_8822B(x) | BIT_HEAD_PKT_MGQ_V1_8822B(v))
/* 2 REG_HIQ_INFO_8822B */
#define BIT_SHIFT_QUEUEMACID_HIQ_V1_8822B 25
#define BIT_MASK_QUEUEMACID_HIQ_V1_8822B 0x7f
-#define BIT_QUEUEMACID_HIQ_V1_8822B(x) (((x) & BIT_MASK_QUEUEMACID_HIQ_V1_8822B) << BIT_SHIFT_QUEUEMACID_HIQ_V1_8822B)
-#define BIT_GET_QUEUEMACID_HIQ_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1_8822B) & BIT_MASK_QUEUEMACID_HIQ_V1_8822B)
-
+#define BIT_QUEUEMACID_HIQ_V1_8822B(x) \
+ (((x) & BIT_MASK_QUEUEMACID_HIQ_V1_8822B) \
+ << BIT_SHIFT_QUEUEMACID_HIQ_V1_8822B)
+#define BITS_QUEUEMACID_HIQ_V1_8822B \
+ (BIT_MASK_QUEUEMACID_HIQ_V1_8822B << BIT_SHIFT_QUEUEMACID_HIQ_V1_8822B)
+#define BIT_CLEAR_QUEUEMACID_HIQ_V1_8822B(x) \
+ ((x) & (~BITS_QUEUEMACID_HIQ_V1_8822B))
+#define BIT_GET_QUEUEMACID_HIQ_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1_8822B) & \
+ BIT_MASK_QUEUEMACID_HIQ_V1_8822B)
+#define BIT_SET_QUEUEMACID_HIQ_V1_8822B(x, v) \
+ (BIT_CLEAR_QUEUEMACID_HIQ_V1_8822B(x) | BIT_QUEUEMACID_HIQ_V1_8822B(v))
#define BIT_SHIFT_QUEUEAC_HIQ_V1_8822B 23
#define BIT_MASK_QUEUEAC_HIQ_V1_8822B 0x3
-#define BIT_QUEUEAC_HIQ_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_HIQ_V1_8822B) << BIT_SHIFT_QUEUEAC_HIQ_V1_8822B)
-#define BIT_GET_QUEUEAC_HIQ_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1_8822B) & BIT_MASK_QUEUEAC_HIQ_V1_8822B)
+#define BIT_QUEUEAC_HIQ_V1_8822B(x) \
+ (((x) & BIT_MASK_QUEUEAC_HIQ_V1_8822B) \
+ << BIT_SHIFT_QUEUEAC_HIQ_V1_8822B)
+#define BITS_QUEUEAC_HIQ_V1_8822B \
+ (BIT_MASK_QUEUEAC_HIQ_V1_8822B << BIT_SHIFT_QUEUEAC_HIQ_V1_8822B)
+#define BIT_CLEAR_QUEUEAC_HIQ_V1_8822B(x) ((x) & (~BITS_QUEUEAC_HIQ_V1_8822B))
+#define BIT_GET_QUEUEAC_HIQ_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1_8822B) & \
+ BIT_MASK_QUEUEAC_HIQ_V1_8822B)
+#define BIT_SET_QUEUEAC_HIQ_V1_8822B(x, v) \
+ (BIT_CLEAR_QUEUEAC_HIQ_V1_8822B(x) | BIT_QUEUEAC_HIQ_V1_8822B(v))
#define BIT_TIDEMPTY_HIQ_V1_8822B BIT(22)
#define BIT_SHIFT_TAIL_PKT_HIQ_V2_8822B 11
#define BIT_MASK_TAIL_PKT_HIQ_V2_8822B 0x7ff
-#define BIT_TAIL_PKT_HIQ_V2_8822B(x) (((x) & BIT_MASK_TAIL_PKT_HIQ_V2_8822B) << BIT_SHIFT_TAIL_PKT_HIQ_V2_8822B)
-#define BIT_GET_TAIL_PKT_HIQ_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2_8822B) & BIT_MASK_TAIL_PKT_HIQ_V2_8822B)
-
+#define BIT_TAIL_PKT_HIQ_V2_8822B(x) \
+ (((x) & BIT_MASK_TAIL_PKT_HIQ_V2_8822B) \
+ << BIT_SHIFT_TAIL_PKT_HIQ_V2_8822B)
+#define BITS_TAIL_PKT_HIQ_V2_8822B \
+ (BIT_MASK_TAIL_PKT_HIQ_V2_8822B << BIT_SHIFT_TAIL_PKT_HIQ_V2_8822B)
+#define BIT_CLEAR_TAIL_PKT_HIQ_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_HIQ_V2_8822B))
+#define BIT_GET_TAIL_PKT_HIQ_V2_8822B(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2_8822B) & \
+ BIT_MASK_TAIL_PKT_HIQ_V2_8822B)
+#define BIT_SET_TAIL_PKT_HIQ_V2_8822B(x, v) \
+ (BIT_CLEAR_TAIL_PKT_HIQ_V2_8822B(x) | BIT_TAIL_PKT_HIQ_V2_8822B(v))
#define BIT_SHIFT_HEAD_PKT_HIQ_V1_8822B 0
#define BIT_MASK_HEAD_PKT_HIQ_V1_8822B 0x7ff
-#define BIT_HEAD_PKT_HIQ_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_HIQ_V1_8822B) << BIT_SHIFT_HEAD_PKT_HIQ_V1_8822B)
-#define BIT_GET_HEAD_PKT_HIQ_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1_8822B) & BIT_MASK_HEAD_PKT_HIQ_V1_8822B)
-
+#define BIT_HEAD_PKT_HIQ_V1_8822B(x) \
+ (((x) & BIT_MASK_HEAD_PKT_HIQ_V1_8822B) \
+ << BIT_SHIFT_HEAD_PKT_HIQ_V1_8822B)
+#define BITS_HEAD_PKT_HIQ_V1_8822B \
+ (BIT_MASK_HEAD_PKT_HIQ_V1_8822B << BIT_SHIFT_HEAD_PKT_HIQ_V1_8822B)
+#define BIT_CLEAR_HEAD_PKT_HIQ_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_HIQ_V1_8822B))
+#define BIT_GET_HEAD_PKT_HIQ_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1_8822B) & \
+ BIT_MASK_HEAD_PKT_HIQ_V1_8822B)
+#define BIT_SET_HEAD_PKT_HIQ_V1_8822B(x, v) \
+ (BIT_CLEAR_HEAD_PKT_HIQ_V1_8822B(x) | BIT_HEAD_PKT_HIQ_V1_8822B(v))
/* 2 REG_BCNQ_INFO_8822B */
#define BIT_SHIFT_BCNQ_HEAD_PG_V1_8822B 0
#define BIT_MASK_BCNQ_HEAD_PG_V1_8822B 0xfff
-#define BIT_BCNQ_HEAD_PG_V1_8822B(x) (((x) & BIT_MASK_BCNQ_HEAD_PG_V1_8822B) << BIT_SHIFT_BCNQ_HEAD_PG_V1_8822B)
-#define BIT_GET_BCNQ_HEAD_PG_V1_8822B(x) (((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1_8822B) & BIT_MASK_BCNQ_HEAD_PG_V1_8822B)
-
+#define BIT_BCNQ_HEAD_PG_V1_8822B(x) \
+ (((x) & BIT_MASK_BCNQ_HEAD_PG_V1_8822B) \
+ << BIT_SHIFT_BCNQ_HEAD_PG_V1_8822B)
+#define BITS_BCNQ_HEAD_PG_V1_8822B \
+ (BIT_MASK_BCNQ_HEAD_PG_V1_8822B << BIT_SHIFT_BCNQ_HEAD_PG_V1_8822B)
+#define BIT_CLEAR_BCNQ_HEAD_PG_V1_8822B(x) ((x) & (~BITS_BCNQ_HEAD_PG_V1_8822B))
+#define BIT_GET_BCNQ_HEAD_PG_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1_8822B) & \
+ BIT_MASK_BCNQ_HEAD_PG_V1_8822B)
+#define BIT_SET_BCNQ_HEAD_PG_V1_8822B(x, v) \
+ (BIT_CLEAR_BCNQ_HEAD_PG_V1_8822B(x) | BIT_BCNQ_HEAD_PG_V1_8822B(v))
/* 2 REG_TXPKT_EMPTY_8822B */
#define BIT_BCNQ_EMPTY_8822B BIT(11)
@@ -4915,9 +8221,17 @@
#define BIT_SHIFT_FW_FREE_TAIL_V1_8822B 0
#define BIT_MASK_FW_FREE_TAIL_V1_8822B 0xfff
-#define BIT_FW_FREE_TAIL_V1_8822B(x) (((x) & BIT_MASK_FW_FREE_TAIL_V1_8822B) << BIT_SHIFT_FW_FREE_TAIL_V1_8822B)
-#define BIT_GET_FW_FREE_TAIL_V1_8822B(x) (((x) >> BIT_SHIFT_FW_FREE_TAIL_V1_8822B) & BIT_MASK_FW_FREE_TAIL_V1_8822B)
-
+#define BIT_FW_FREE_TAIL_V1_8822B(x) \
+ (((x) & BIT_MASK_FW_FREE_TAIL_V1_8822B) \
+ << BIT_SHIFT_FW_FREE_TAIL_V1_8822B)
+#define BITS_FW_FREE_TAIL_V1_8822B \
+ (BIT_MASK_FW_FREE_TAIL_V1_8822B << BIT_SHIFT_FW_FREE_TAIL_V1_8822B)
+#define BIT_CLEAR_FW_FREE_TAIL_V1_8822B(x) ((x) & (~BITS_FW_FREE_TAIL_V1_8822B))
+#define BIT_GET_FW_FREE_TAIL_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_FW_FREE_TAIL_V1_8822B) & \
+ BIT_MASK_FW_FREE_TAIL_V1_8822B)
+#define BIT_SET_FW_FREE_TAIL_V1_8822B(x, v) \
+ (BIT_CLEAR_FW_FREE_TAIL_V1_8822B(x) | BIT_FW_FREE_TAIL_V1_8822B(v))
/* 2 REG_FWHW_TXQ_CTRL_8822B */
#define BIT_RTS_LIMIT_IN_OFDM_8822B BIT(23)
@@ -4927,8 +8241,15 @@
#define BIT_SHIFT_EN_QUEUE_RPT_8822B 8
#define BIT_MASK_EN_QUEUE_RPT_8822B 0xff
-#define BIT_EN_QUEUE_RPT_8822B(x) (((x) & BIT_MASK_EN_QUEUE_RPT_8822B) << BIT_SHIFT_EN_QUEUE_RPT_8822B)
-#define BIT_GET_EN_QUEUE_RPT_8822B(x) (((x) >> BIT_SHIFT_EN_QUEUE_RPT_8822B) & BIT_MASK_EN_QUEUE_RPT_8822B)
+#define BIT_EN_QUEUE_RPT_8822B(x) \
+ (((x) & BIT_MASK_EN_QUEUE_RPT_8822B) << BIT_SHIFT_EN_QUEUE_RPT_8822B)
+#define BITS_EN_QUEUE_RPT_8822B \
+ (BIT_MASK_EN_QUEUE_RPT_8822B << BIT_SHIFT_EN_QUEUE_RPT_8822B)
+#define BIT_CLEAR_EN_QUEUE_RPT_8822B(x) ((x) & (~BITS_EN_QUEUE_RPT_8822B))
+#define BIT_GET_EN_QUEUE_RPT_8822B(x) \
+ (((x) >> BIT_SHIFT_EN_QUEUE_RPT_8822B) & BIT_MASK_EN_QUEUE_RPT_8822B)
+#define BIT_SET_EN_QUEUE_RPT_8822B(x, v) \
+ (BIT_CLEAR_EN_QUEUE_RPT_8822B(x) | BIT_EN_QUEUE_RPT_8822B(v))
#define BIT_EN_RTY_BK_8822B BIT(7)
#define BIT_EN_USE_INI_RAT_8822B BIT(6)
@@ -4940,21 +8261,39 @@
#define BIT_EN_FTMRPT_8822B BIT(0)
/* 2 REG_DATAFB_SEL_8822B */
-#define BIT__R_EN_RTY_BK_COD_8822B BIT(2)
#define BIT_SHIFT__R_DATA_FALLBACK_SEL_8822B 0
#define BIT_MASK__R_DATA_FALLBACK_SEL_8822B 0x3
-#define BIT__R_DATA_FALLBACK_SEL_8822B(x) (((x) & BIT_MASK__R_DATA_FALLBACK_SEL_8822B) << BIT_SHIFT__R_DATA_FALLBACK_SEL_8822B)
-#define BIT_GET__R_DATA_FALLBACK_SEL_8822B(x) (((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL_8822B) & BIT_MASK__R_DATA_FALLBACK_SEL_8822B)
-
+#define BIT__R_DATA_FALLBACK_SEL_8822B(x) \
+ (((x) & BIT_MASK__R_DATA_FALLBACK_SEL_8822B) \
+ << BIT_SHIFT__R_DATA_FALLBACK_SEL_8822B)
+#define BITS__R_DATA_FALLBACK_SEL_8822B \
+ (BIT_MASK__R_DATA_FALLBACK_SEL_8822B \
+ << BIT_SHIFT__R_DATA_FALLBACK_SEL_8822B)
+#define BIT_CLEAR__R_DATA_FALLBACK_SEL_8822B(x) \
+ ((x) & (~BITS__R_DATA_FALLBACK_SEL_8822B))
+#define BIT_GET__R_DATA_FALLBACK_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL_8822B) & \
+ BIT_MASK__R_DATA_FALLBACK_SEL_8822B)
+#define BIT_SET__R_DATA_FALLBACK_SEL_8822B(x, v) \
+ (BIT_CLEAR__R_DATA_FALLBACK_SEL_8822B(x) | \
+ BIT__R_DATA_FALLBACK_SEL_8822B(v))
/* 2 REG_BCNQ_BDNY_V1_8822B */
#define BIT_SHIFT_BCNQ_PGBNDY_V1_8822B 0
#define BIT_MASK_BCNQ_PGBNDY_V1_8822B 0xfff
-#define BIT_BCNQ_PGBNDY_V1_8822B(x) (((x) & BIT_MASK_BCNQ_PGBNDY_V1_8822B) << BIT_SHIFT_BCNQ_PGBNDY_V1_8822B)
-#define BIT_GET_BCNQ_PGBNDY_V1_8822B(x) (((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1_8822B) & BIT_MASK_BCNQ_PGBNDY_V1_8822B)
-
+#define BIT_BCNQ_PGBNDY_V1_8822B(x) \
+ (((x) & BIT_MASK_BCNQ_PGBNDY_V1_8822B) \
+ << BIT_SHIFT_BCNQ_PGBNDY_V1_8822B)
+#define BITS_BCNQ_PGBNDY_V1_8822B \
+ (BIT_MASK_BCNQ_PGBNDY_V1_8822B << BIT_SHIFT_BCNQ_PGBNDY_V1_8822B)
+#define BIT_CLEAR_BCNQ_PGBNDY_V1_8822B(x) ((x) & (~BITS_BCNQ_PGBNDY_V1_8822B))
+#define BIT_GET_BCNQ_PGBNDY_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1_8822B) & \
+ BIT_MASK_BCNQ_PGBNDY_V1_8822B)
+#define BIT_SET_BCNQ_PGBNDY_V1_8822B(x, v) \
+ (BIT_CLEAR_BCNQ_PGBNDY_V1_8822B(x) | BIT_BCNQ_PGBNDY_V1_8822B(v))
/* 2 REG_LIFETIME_EN_8822B */
#define BIT_BT_INT_CPU_8822B BIT(7)
@@ -4969,29 +8308,55 @@
#define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822B 8
#define BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822B 0xff
-#define BIT_SPEC_SIFS_OFDM_PTCL_8822B(x) (((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822B) << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822B)
-#define BIT_GET_SPEC_SIFS_OFDM_PTCL_8822B(x) (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822B) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822B)
-
+#define BIT_SPEC_SIFS_OFDM_PTCL_8822B(x) \
+ (((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822B) \
+ << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822B)
+#define BITS_SPEC_SIFS_OFDM_PTCL_8822B \
+ (BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822B \
+ << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822B)
+#define BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8822B(x) \
+ ((x) & (~BITS_SPEC_SIFS_OFDM_PTCL_8822B))
+#define BIT_GET_SPEC_SIFS_OFDM_PTCL_8822B(x) \
+ (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822B) & \
+ BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822B)
+#define BIT_SET_SPEC_SIFS_OFDM_PTCL_8822B(x, v) \
+ (BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8822B(x) | \
+ BIT_SPEC_SIFS_OFDM_PTCL_8822B(v))
#define BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822B 0
#define BIT_MASK_SPEC_SIFS_CCK_PTCL_8822B 0xff
-#define BIT_SPEC_SIFS_CCK_PTCL_8822B(x) (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8822B) << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822B)
-#define BIT_GET_SPEC_SIFS_CCK_PTCL_8822B(x) (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822B) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8822B)
-
+#define BIT_SPEC_SIFS_CCK_PTCL_8822B(x) \
+ (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8822B) \
+ << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822B)
+#define BITS_SPEC_SIFS_CCK_PTCL_8822B \
+ (BIT_MASK_SPEC_SIFS_CCK_PTCL_8822B \
+ << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822B)
+#define BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8822B(x) \
+ ((x) & (~BITS_SPEC_SIFS_CCK_PTCL_8822B))
+#define BIT_GET_SPEC_SIFS_CCK_PTCL_8822B(x) \
+ (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822B) & \
+ BIT_MASK_SPEC_SIFS_CCK_PTCL_8822B)
+#define BIT_SET_SPEC_SIFS_CCK_PTCL_8822B(x, v) \
+ (BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8822B(x) | \
+ BIT_SPEC_SIFS_CCK_PTCL_8822B(v))
/* 2 REG_RETRY_LIMIT_8822B */
#define BIT_SHIFT_SRL_8822B 8
#define BIT_MASK_SRL_8822B 0x3f
#define BIT_SRL_8822B(x) (((x) & BIT_MASK_SRL_8822B) << BIT_SHIFT_SRL_8822B)
+#define BITS_SRL_8822B (BIT_MASK_SRL_8822B << BIT_SHIFT_SRL_8822B)
+#define BIT_CLEAR_SRL_8822B(x) ((x) & (~BITS_SRL_8822B))
#define BIT_GET_SRL_8822B(x) (((x) >> BIT_SHIFT_SRL_8822B) & BIT_MASK_SRL_8822B)
-
+#define BIT_SET_SRL_8822B(x, v) (BIT_CLEAR_SRL_8822B(x) | BIT_SRL_8822B(v))
#define BIT_SHIFT_LRL_8822B 0
#define BIT_MASK_LRL_8822B 0x3f
#define BIT_LRL_8822B(x) (((x) & BIT_MASK_LRL_8822B) << BIT_SHIFT_LRL_8822B)
+#define BITS_LRL_8822B (BIT_MASK_LRL_8822B << BIT_SHIFT_LRL_8822B)
+#define BIT_CLEAR_LRL_8822B(x) ((x) & (~BITS_LRL_8822B))
#define BIT_GET_LRL_8822B(x) (((x) >> BIT_SHIFT_LRL_8822B) & BIT_MASK_LRL_8822B)
-
+#define BIT_SET_LRL_8822B(x, v) (BIT_CLEAR_LRL_8822B(x) | BIT_LRL_8822B(v))
/* 2 REG_TXBF_CTRL_8822B */
#define BIT_R_ENABLE_NDPA_8822B BIT(31)
@@ -5004,8 +8369,15 @@
#define BIT_SHIFT_R_TXBF1_AID_8822B 16
#define BIT_MASK_R_TXBF1_AID_8822B 0x1ff
-#define BIT_R_TXBF1_AID_8822B(x) (((x) & BIT_MASK_R_TXBF1_AID_8822B) << BIT_SHIFT_R_TXBF1_AID_8822B)
-#define BIT_GET_R_TXBF1_AID_8822B(x) (((x) >> BIT_SHIFT_R_TXBF1_AID_8822B) & BIT_MASK_R_TXBF1_AID_8822B)
+#define BIT_R_TXBF1_AID_8822B(x) \
+ (((x) & BIT_MASK_R_TXBF1_AID_8822B) << BIT_SHIFT_R_TXBF1_AID_8822B)
+#define BITS_R_TXBF1_AID_8822B \
+ (BIT_MASK_R_TXBF1_AID_8822B << BIT_SHIFT_R_TXBF1_AID_8822B)
+#define BIT_CLEAR_R_TXBF1_AID_8822B(x) ((x) & (~BITS_R_TXBF1_AID_8822B))
+#define BIT_GET_R_TXBF1_AID_8822B(x) \
+ (((x) >> BIT_SHIFT_R_TXBF1_AID_8822B) & BIT_MASK_R_TXBF1_AID_8822B)
+#define BIT_SET_R_TXBF1_AID_8822B(x, v) \
+ (BIT_CLEAR_R_TXBF1_AID_8822B(x) | BIT_R_TXBF1_AID_8822B(v))
#define BIT_DIS_NDP_BFEN_8822B BIT(15)
#define BIT_R_TXBCN_NOBLOCK_NDP_8822B BIT(14)
@@ -5015,140 +8387,267 @@
#define BIT_SHIFT_R_TXBF0_AID_8822B 0
#define BIT_MASK_R_TXBF0_AID_8822B 0x1ff
-#define BIT_R_TXBF0_AID_8822B(x) (((x) & BIT_MASK_R_TXBF0_AID_8822B) << BIT_SHIFT_R_TXBF0_AID_8822B)
-#define BIT_GET_R_TXBF0_AID_8822B(x) (((x) >> BIT_SHIFT_R_TXBF0_AID_8822B) & BIT_MASK_R_TXBF0_AID_8822B)
-
+#define BIT_R_TXBF0_AID_8822B(x) \
+ (((x) & BIT_MASK_R_TXBF0_AID_8822B) << BIT_SHIFT_R_TXBF0_AID_8822B)
+#define BITS_R_TXBF0_AID_8822B \
+ (BIT_MASK_R_TXBF0_AID_8822B << BIT_SHIFT_R_TXBF0_AID_8822B)
+#define BIT_CLEAR_R_TXBF0_AID_8822B(x) ((x) & (~BITS_R_TXBF0_AID_8822B))
+#define BIT_GET_R_TXBF0_AID_8822B(x) \
+ (((x) >> BIT_SHIFT_R_TXBF0_AID_8822B) & BIT_MASK_R_TXBF0_AID_8822B)
+#define BIT_SET_R_TXBF0_AID_8822B(x, v) \
+ (BIT_CLEAR_R_TXBF0_AID_8822B(x) | BIT_R_TXBF0_AID_8822B(v))
/* 2 REG_DARFRC_8822B */
#define BIT_SHIFT_DARF_RC8_8822B (56 & CPU_OPT_WIDTH)
#define BIT_MASK_DARF_RC8_8822B 0x1f
-#define BIT_DARF_RC8_8822B(x) (((x) & BIT_MASK_DARF_RC8_8822B) << BIT_SHIFT_DARF_RC8_8822B)
-#define BIT_GET_DARF_RC8_8822B(x) (((x) >> BIT_SHIFT_DARF_RC8_8822B) & BIT_MASK_DARF_RC8_8822B)
-
+#define BIT_DARF_RC8_8822B(x) \
+ (((x) & BIT_MASK_DARF_RC8_8822B) << BIT_SHIFT_DARF_RC8_8822B)
+#define BITS_DARF_RC8_8822B \
+ (BIT_MASK_DARF_RC8_8822B << BIT_SHIFT_DARF_RC8_8822B)
+#define BIT_CLEAR_DARF_RC8_8822B(x) ((x) & (~BITS_DARF_RC8_8822B))
+#define BIT_GET_DARF_RC8_8822B(x) \
+ (((x) >> BIT_SHIFT_DARF_RC8_8822B) & BIT_MASK_DARF_RC8_8822B)
+#define BIT_SET_DARF_RC8_8822B(x, v) \
+ (BIT_CLEAR_DARF_RC8_8822B(x) | BIT_DARF_RC8_8822B(v))
#define BIT_SHIFT_DARF_RC7_8822B (48 & CPU_OPT_WIDTH)
#define BIT_MASK_DARF_RC7_8822B 0x1f
-#define BIT_DARF_RC7_8822B(x) (((x) & BIT_MASK_DARF_RC7_8822B) << BIT_SHIFT_DARF_RC7_8822B)
-#define BIT_GET_DARF_RC7_8822B(x) (((x) >> BIT_SHIFT_DARF_RC7_8822B) & BIT_MASK_DARF_RC7_8822B)
-
+#define BIT_DARF_RC7_8822B(x) \
+ (((x) & BIT_MASK_DARF_RC7_8822B) << BIT_SHIFT_DARF_RC7_8822B)
+#define BITS_DARF_RC7_8822B \
+ (BIT_MASK_DARF_RC7_8822B << BIT_SHIFT_DARF_RC7_8822B)
+#define BIT_CLEAR_DARF_RC7_8822B(x) ((x) & (~BITS_DARF_RC7_8822B))
+#define BIT_GET_DARF_RC7_8822B(x) \
+ (((x) >> BIT_SHIFT_DARF_RC7_8822B) & BIT_MASK_DARF_RC7_8822B)
+#define BIT_SET_DARF_RC7_8822B(x, v) \
+ (BIT_CLEAR_DARF_RC7_8822B(x) | BIT_DARF_RC7_8822B(v))
#define BIT_SHIFT_DARF_RC6_8822B (40 & CPU_OPT_WIDTH)
#define BIT_MASK_DARF_RC6_8822B 0x1f
-#define BIT_DARF_RC6_8822B(x) (((x) & BIT_MASK_DARF_RC6_8822B) << BIT_SHIFT_DARF_RC6_8822B)
-#define BIT_GET_DARF_RC6_8822B(x) (((x) >> BIT_SHIFT_DARF_RC6_8822B) & BIT_MASK_DARF_RC6_8822B)
-
+#define BIT_DARF_RC6_8822B(x) \
+ (((x) & BIT_MASK_DARF_RC6_8822B) << BIT_SHIFT_DARF_RC6_8822B)
+#define BITS_DARF_RC6_8822B \
+ (BIT_MASK_DARF_RC6_8822B << BIT_SHIFT_DARF_RC6_8822B)
+#define BIT_CLEAR_DARF_RC6_8822B(x) ((x) & (~BITS_DARF_RC6_8822B))
+#define BIT_GET_DARF_RC6_8822B(x) \
+ (((x) >> BIT_SHIFT_DARF_RC6_8822B) & BIT_MASK_DARF_RC6_8822B)
+#define BIT_SET_DARF_RC6_8822B(x, v) \
+ (BIT_CLEAR_DARF_RC6_8822B(x) | BIT_DARF_RC6_8822B(v))
#define BIT_SHIFT_DARF_RC5_8822B (32 & CPU_OPT_WIDTH)
#define BIT_MASK_DARF_RC5_8822B 0x1f
-#define BIT_DARF_RC5_8822B(x) (((x) & BIT_MASK_DARF_RC5_8822B) << BIT_SHIFT_DARF_RC5_8822B)
-#define BIT_GET_DARF_RC5_8822B(x) (((x) >> BIT_SHIFT_DARF_RC5_8822B) & BIT_MASK_DARF_RC5_8822B)
-
+#define BIT_DARF_RC5_8822B(x) \
+ (((x) & BIT_MASK_DARF_RC5_8822B) << BIT_SHIFT_DARF_RC5_8822B)
+#define BITS_DARF_RC5_8822B \
+ (BIT_MASK_DARF_RC5_8822B << BIT_SHIFT_DARF_RC5_8822B)
+#define BIT_CLEAR_DARF_RC5_8822B(x) ((x) & (~BITS_DARF_RC5_8822B))
+#define BIT_GET_DARF_RC5_8822B(x) \
+ (((x) >> BIT_SHIFT_DARF_RC5_8822B) & BIT_MASK_DARF_RC5_8822B)
+#define BIT_SET_DARF_RC5_8822B(x, v) \
+ (BIT_CLEAR_DARF_RC5_8822B(x) | BIT_DARF_RC5_8822B(v))
#define BIT_SHIFT_DARF_RC4_8822B 24
#define BIT_MASK_DARF_RC4_8822B 0x1f
-#define BIT_DARF_RC4_8822B(x) (((x) & BIT_MASK_DARF_RC4_8822B) << BIT_SHIFT_DARF_RC4_8822B)
-#define BIT_GET_DARF_RC4_8822B(x) (((x) >> BIT_SHIFT_DARF_RC4_8822B) & BIT_MASK_DARF_RC4_8822B)
-
+#define BIT_DARF_RC4_8822B(x) \
+ (((x) & BIT_MASK_DARF_RC4_8822B) << BIT_SHIFT_DARF_RC4_8822B)
+#define BITS_DARF_RC4_8822B \
+ (BIT_MASK_DARF_RC4_8822B << BIT_SHIFT_DARF_RC4_8822B)
+#define BIT_CLEAR_DARF_RC4_8822B(x) ((x) & (~BITS_DARF_RC4_8822B))
+#define BIT_GET_DARF_RC4_8822B(x) \
+ (((x) >> BIT_SHIFT_DARF_RC4_8822B) & BIT_MASK_DARF_RC4_8822B)
+#define BIT_SET_DARF_RC4_8822B(x, v) \
+ (BIT_CLEAR_DARF_RC4_8822B(x) | BIT_DARF_RC4_8822B(v))
#define BIT_SHIFT_DARF_RC3_8822B 16
#define BIT_MASK_DARF_RC3_8822B 0x1f
-#define BIT_DARF_RC3_8822B(x) (((x) & BIT_MASK_DARF_RC3_8822B) << BIT_SHIFT_DARF_RC3_8822B)
-#define BIT_GET_DARF_RC3_8822B(x) (((x) >> BIT_SHIFT_DARF_RC3_8822B) & BIT_MASK_DARF_RC3_8822B)
-
+#define BIT_DARF_RC3_8822B(x) \
+ (((x) & BIT_MASK_DARF_RC3_8822B) << BIT_SHIFT_DARF_RC3_8822B)
+#define BITS_DARF_RC3_8822B \
+ (BIT_MASK_DARF_RC3_8822B << BIT_SHIFT_DARF_RC3_8822B)
+#define BIT_CLEAR_DARF_RC3_8822B(x) ((x) & (~BITS_DARF_RC3_8822B))
+#define BIT_GET_DARF_RC3_8822B(x) \
+ (((x) >> BIT_SHIFT_DARF_RC3_8822B) & BIT_MASK_DARF_RC3_8822B)
+#define BIT_SET_DARF_RC3_8822B(x, v) \
+ (BIT_CLEAR_DARF_RC3_8822B(x) | BIT_DARF_RC3_8822B(v))
#define BIT_SHIFT_DARF_RC2_8822B 8
#define BIT_MASK_DARF_RC2_8822B 0x1f
-#define BIT_DARF_RC2_8822B(x) (((x) & BIT_MASK_DARF_RC2_8822B) << BIT_SHIFT_DARF_RC2_8822B)
-#define BIT_GET_DARF_RC2_8822B(x) (((x) >> BIT_SHIFT_DARF_RC2_8822B) & BIT_MASK_DARF_RC2_8822B)
-
+#define BIT_DARF_RC2_8822B(x) \
+ (((x) & BIT_MASK_DARF_RC2_8822B) << BIT_SHIFT_DARF_RC2_8822B)
+#define BITS_DARF_RC2_8822B \
+ (BIT_MASK_DARF_RC2_8822B << BIT_SHIFT_DARF_RC2_8822B)
+#define BIT_CLEAR_DARF_RC2_8822B(x) ((x) & (~BITS_DARF_RC2_8822B))
+#define BIT_GET_DARF_RC2_8822B(x) \
+ (((x) >> BIT_SHIFT_DARF_RC2_8822B) & BIT_MASK_DARF_RC2_8822B)
+#define BIT_SET_DARF_RC2_8822B(x, v) \
+ (BIT_CLEAR_DARF_RC2_8822B(x) | BIT_DARF_RC2_8822B(v))
#define BIT_SHIFT_DARF_RC1_8822B 0
#define BIT_MASK_DARF_RC1_8822B 0x1f
-#define BIT_DARF_RC1_8822B(x) (((x) & BIT_MASK_DARF_RC1_8822B) << BIT_SHIFT_DARF_RC1_8822B)
-#define BIT_GET_DARF_RC1_8822B(x) (((x) >> BIT_SHIFT_DARF_RC1_8822B) & BIT_MASK_DARF_RC1_8822B)
-
+#define BIT_DARF_RC1_8822B(x) \
+ (((x) & BIT_MASK_DARF_RC1_8822B) << BIT_SHIFT_DARF_RC1_8822B)
+#define BITS_DARF_RC1_8822B \
+ (BIT_MASK_DARF_RC1_8822B << BIT_SHIFT_DARF_RC1_8822B)
+#define BIT_CLEAR_DARF_RC1_8822B(x) ((x) & (~BITS_DARF_RC1_8822B))
+#define BIT_GET_DARF_RC1_8822B(x) \
+ (((x) >> BIT_SHIFT_DARF_RC1_8822B) & BIT_MASK_DARF_RC1_8822B)
+#define BIT_SET_DARF_RC1_8822B(x, v) \
+ (BIT_CLEAR_DARF_RC1_8822B(x) | BIT_DARF_RC1_8822B(v))
/* 2 REG_RARFRC_8822B */
#define BIT_SHIFT_RARF_RC8_8822B (56 & CPU_OPT_WIDTH)
#define BIT_MASK_RARF_RC8_8822B 0x1f
-#define BIT_RARF_RC8_8822B(x) (((x) & BIT_MASK_RARF_RC8_8822B) << BIT_SHIFT_RARF_RC8_8822B)
-#define BIT_GET_RARF_RC8_8822B(x) (((x) >> BIT_SHIFT_RARF_RC8_8822B) & BIT_MASK_RARF_RC8_8822B)
-
+#define BIT_RARF_RC8_8822B(x) \
+ (((x) & BIT_MASK_RARF_RC8_8822B) << BIT_SHIFT_RARF_RC8_8822B)
+#define BITS_RARF_RC8_8822B \
+ (BIT_MASK_RARF_RC8_8822B << BIT_SHIFT_RARF_RC8_8822B)
+#define BIT_CLEAR_RARF_RC8_8822B(x) ((x) & (~BITS_RARF_RC8_8822B))
+#define BIT_GET_RARF_RC8_8822B(x) \
+ (((x) >> BIT_SHIFT_RARF_RC8_8822B) & BIT_MASK_RARF_RC8_8822B)
+#define BIT_SET_RARF_RC8_8822B(x, v) \
+ (BIT_CLEAR_RARF_RC8_8822B(x) | BIT_RARF_RC8_8822B(v))
#define BIT_SHIFT_RARF_RC7_8822B (48 & CPU_OPT_WIDTH)
#define BIT_MASK_RARF_RC7_8822B 0x1f
-#define BIT_RARF_RC7_8822B(x) (((x) & BIT_MASK_RARF_RC7_8822B) << BIT_SHIFT_RARF_RC7_8822B)
-#define BIT_GET_RARF_RC7_8822B(x) (((x) >> BIT_SHIFT_RARF_RC7_8822B) & BIT_MASK_RARF_RC7_8822B)
-
+#define BIT_RARF_RC7_8822B(x) \
+ (((x) & BIT_MASK_RARF_RC7_8822B) << BIT_SHIFT_RARF_RC7_8822B)
+#define BITS_RARF_RC7_8822B \
+ (BIT_MASK_RARF_RC7_8822B << BIT_SHIFT_RARF_RC7_8822B)
+#define BIT_CLEAR_RARF_RC7_8822B(x) ((x) & (~BITS_RARF_RC7_8822B))
+#define BIT_GET_RARF_RC7_8822B(x) \
+ (((x) >> BIT_SHIFT_RARF_RC7_8822B) & BIT_MASK_RARF_RC7_8822B)
+#define BIT_SET_RARF_RC7_8822B(x, v) \
+ (BIT_CLEAR_RARF_RC7_8822B(x) | BIT_RARF_RC7_8822B(v))
#define BIT_SHIFT_RARF_RC6_8822B (40 & CPU_OPT_WIDTH)
#define BIT_MASK_RARF_RC6_8822B 0x1f
-#define BIT_RARF_RC6_8822B(x) (((x) & BIT_MASK_RARF_RC6_8822B) << BIT_SHIFT_RARF_RC6_8822B)
-#define BIT_GET_RARF_RC6_8822B(x) (((x) >> BIT_SHIFT_RARF_RC6_8822B) & BIT_MASK_RARF_RC6_8822B)
-
+#define BIT_RARF_RC6_8822B(x) \
+ (((x) & BIT_MASK_RARF_RC6_8822B) << BIT_SHIFT_RARF_RC6_8822B)
+#define BITS_RARF_RC6_8822B \
+ (BIT_MASK_RARF_RC6_8822B << BIT_SHIFT_RARF_RC6_8822B)
+#define BIT_CLEAR_RARF_RC6_8822B(x) ((x) & (~BITS_RARF_RC6_8822B))
+#define BIT_GET_RARF_RC6_8822B(x) \
+ (((x) >> BIT_SHIFT_RARF_RC6_8822B) & BIT_MASK_RARF_RC6_8822B)
+#define BIT_SET_RARF_RC6_8822B(x, v) \
+ (BIT_CLEAR_RARF_RC6_8822B(x) | BIT_RARF_RC6_8822B(v))
#define BIT_SHIFT_RARF_RC5_8822B (32 & CPU_OPT_WIDTH)
#define BIT_MASK_RARF_RC5_8822B 0x1f
-#define BIT_RARF_RC5_8822B(x) (((x) & BIT_MASK_RARF_RC5_8822B) << BIT_SHIFT_RARF_RC5_8822B)
-#define BIT_GET_RARF_RC5_8822B(x) (((x) >> BIT_SHIFT_RARF_RC5_8822B) & BIT_MASK_RARF_RC5_8822B)
-
+#define BIT_RARF_RC5_8822B(x) \
+ (((x) & BIT_MASK_RARF_RC5_8822B) << BIT_SHIFT_RARF_RC5_8822B)
+#define BITS_RARF_RC5_8822B \
+ (BIT_MASK_RARF_RC5_8822B << BIT_SHIFT_RARF_RC5_8822B)
+#define BIT_CLEAR_RARF_RC5_8822B(x) ((x) & (~BITS_RARF_RC5_8822B))
+#define BIT_GET_RARF_RC5_8822B(x) \
+ (((x) >> BIT_SHIFT_RARF_RC5_8822B) & BIT_MASK_RARF_RC5_8822B)
+#define BIT_SET_RARF_RC5_8822B(x, v) \
+ (BIT_CLEAR_RARF_RC5_8822B(x) | BIT_RARF_RC5_8822B(v))
#define BIT_SHIFT_RARF_RC4_8822B 24
#define BIT_MASK_RARF_RC4_8822B 0x1f
-#define BIT_RARF_RC4_8822B(x) (((x) & BIT_MASK_RARF_RC4_8822B) << BIT_SHIFT_RARF_RC4_8822B)
-#define BIT_GET_RARF_RC4_8822B(x) (((x) >> BIT_SHIFT_RARF_RC4_8822B) & BIT_MASK_RARF_RC4_8822B)
-
+#define BIT_RARF_RC4_8822B(x) \
+ (((x) & BIT_MASK_RARF_RC4_8822B) << BIT_SHIFT_RARF_RC4_8822B)
+#define BITS_RARF_RC4_8822B \
+ (BIT_MASK_RARF_RC4_8822B << BIT_SHIFT_RARF_RC4_8822B)
+#define BIT_CLEAR_RARF_RC4_8822B(x) ((x) & (~BITS_RARF_RC4_8822B))
+#define BIT_GET_RARF_RC4_8822B(x) \
+ (((x) >> BIT_SHIFT_RARF_RC4_8822B) & BIT_MASK_RARF_RC4_8822B)
+#define BIT_SET_RARF_RC4_8822B(x, v) \
+ (BIT_CLEAR_RARF_RC4_8822B(x) | BIT_RARF_RC4_8822B(v))
#define BIT_SHIFT_RARF_RC3_8822B 16
#define BIT_MASK_RARF_RC3_8822B 0x1f
-#define BIT_RARF_RC3_8822B(x) (((x) & BIT_MASK_RARF_RC3_8822B) << BIT_SHIFT_RARF_RC3_8822B)
-#define BIT_GET_RARF_RC3_8822B(x) (((x) >> BIT_SHIFT_RARF_RC3_8822B) & BIT_MASK_RARF_RC3_8822B)
-
+#define BIT_RARF_RC3_8822B(x) \
+ (((x) & BIT_MASK_RARF_RC3_8822B) << BIT_SHIFT_RARF_RC3_8822B)
+#define BITS_RARF_RC3_8822B \
+ (BIT_MASK_RARF_RC3_8822B << BIT_SHIFT_RARF_RC3_8822B)
+#define BIT_CLEAR_RARF_RC3_8822B(x) ((x) & (~BITS_RARF_RC3_8822B))
+#define BIT_GET_RARF_RC3_8822B(x) \
+ (((x) >> BIT_SHIFT_RARF_RC3_8822B) & BIT_MASK_RARF_RC3_8822B)
+#define BIT_SET_RARF_RC3_8822B(x, v) \
+ (BIT_CLEAR_RARF_RC3_8822B(x) | BIT_RARF_RC3_8822B(v))
#define BIT_SHIFT_RARF_RC2_8822B 8
#define BIT_MASK_RARF_RC2_8822B 0x1f
-#define BIT_RARF_RC2_8822B(x) (((x) & BIT_MASK_RARF_RC2_8822B) << BIT_SHIFT_RARF_RC2_8822B)
-#define BIT_GET_RARF_RC2_8822B(x) (((x) >> BIT_SHIFT_RARF_RC2_8822B) & BIT_MASK_RARF_RC2_8822B)
-
+#define BIT_RARF_RC2_8822B(x) \
+ (((x) & BIT_MASK_RARF_RC2_8822B) << BIT_SHIFT_RARF_RC2_8822B)
+#define BITS_RARF_RC2_8822B \
+ (BIT_MASK_RARF_RC2_8822B << BIT_SHIFT_RARF_RC2_8822B)
+#define BIT_CLEAR_RARF_RC2_8822B(x) ((x) & (~BITS_RARF_RC2_8822B))
+#define BIT_GET_RARF_RC2_8822B(x) \
+ (((x) >> BIT_SHIFT_RARF_RC2_8822B) & BIT_MASK_RARF_RC2_8822B)
+#define BIT_SET_RARF_RC2_8822B(x, v) \
+ (BIT_CLEAR_RARF_RC2_8822B(x) | BIT_RARF_RC2_8822B(v))
#define BIT_SHIFT_RARF_RC1_8822B 0
#define BIT_MASK_RARF_RC1_8822B 0x1f
-#define BIT_RARF_RC1_8822B(x) (((x) & BIT_MASK_RARF_RC1_8822B) << BIT_SHIFT_RARF_RC1_8822B)
-#define BIT_GET_RARF_RC1_8822B(x) (((x) >> BIT_SHIFT_RARF_RC1_8822B) & BIT_MASK_RARF_RC1_8822B)
-
+#define BIT_RARF_RC1_8822B(x) \
+ (((x) & BIT_MASK_RARF_RC1_8822B) << BIT_SHIFT_RARF_RC1_8822B)
+#define BITS_RARF_RC1_8822B \
+ (BIT_MASK_RARF_RC1_8822B << BIT_SHIFT_RARF_RC1_8822B)
+#define BIT_CLEAR_RARF_RC1_8822B(x) ((x) & (~BITS_RARF_RC1_8822B))
+#define BIT_GET_RARF_RC1_8822B(x) \
+ (((x) >> BIT_SHIFT_RARF_RC1_8822B) & BIT_MASK_RARF_RC1_8822B)
+#define BIT_SET_RARF_RC1_8822B(x, v) \
+ (BIT_CLEAR_RARF_RC1_8822B(x) | BIT_RARF_RC1_8822B(v))
/* 2 REG_RRSR_8822B */
#define BIT_SHIFT_RRSR_RSC_8822B 21
#define BIT_MASK_RRSR_RSC_8822B 0x3
-#define BIT_RRSR_RSC_8822B(x) (((x) & BIT_MASK_RRSR_RSC_8822B) << BIT_SHIFT_RRSR_RSC_8822B)
-#define BIT_GET_RRSR_RSC_8822B(x) (((x) >> BIT_SHIFT_RRSR_RSC_8822B) & BIT_MASK_RRSR_RSC_8822B)
+#define BIT_RRSR_RSC_8822B(x) \
+ (((x) & BIT_MASK_RRSR_RSC_8822B) << BIT_SHIFT_RRSR_RSC_8822B)
+#define BITS_RRSR_RSC_8822B \
+ (BIT_MASK_RRSR_RSC_8822B << BIT_SHIFT_RRSR_RSC_8822B)
+#define BIT_CLEAR_RRSR_RSC_8822B(x) ((x) & (~BITS_RRSR_RSC_8822B))
+#define BIT_GET_RRSR_RSC_8822B(x) \
+ (((x) >> BIT_SHIFT_RRSR_RSC_8822B) & BIT_MASK_RRSR_RSC_8822B)
+#define BIT_SET_RRSR_RSC_8822B(x, v) \
+ (BIT_CLEAR_RRSR_RSC_8822B(x) | BIT_RRSR_RSC_8822B(v))
#define BIT_RRSR_BW_8822B BIT(20)
#define BIT_SHIFT_RRSC_BITMAP_8822B 0
#define BIT_MASK_RRSC_BITMAP_8822B 0xfffff
-#define BIT_RRSC_BITMAP_8822B(x) (((x) & BIT_MASK_RRSC_BITMAP_8822B) << BIT_SHIFT_RRSC_BITMAP_8822B)
-#define BIT_GET_RRSC_BITMAP_8822B(x) (((x) >> BIT_SHIFT_RRSC_BITMAP_8822B) & BIT_MASK_RRSC_BITMAP_8822B)
-
+#define BIT_RRSC_BITMAP_8822B(x) \
+ (((x) & BIT_MASK_RRSC_BITMAP_8822B) << BIT_SHIFT_RRSC_BITMAP_8822B)
+#define BITS_RRSC_BITMAP_8822B \
+ (BIT_MASK_RRSC_BITMAP_8822B << BIT_SHIFT_RRSC_BITMAP_8822B)
+#define BIT_CLEAR_RRSC_BITMAP_8822B(x) ((x) & (~BITS_RRSC_BITMAP_8822B))
+#define BIT_GET_RRSC_BITMAP_8822B(x) \
+ (((x) >> BIT_SHIFT_RRSC_BITMAP_8822B) & BIT_MASK_RRSC_BITMAP_8822B)
+#define BIT_SET_RRSC_BITMAP_8822B(x, v) \
+ (BIT_CLEAR_RRSC_BITMAP_8822B(x) | BIT_RRSC_BITMAP_8822B(v))
/* 2 REG_ARFR0_8822B */
#define BIT_SHIFT_ARFR0_V1_8822B 0
#define BIT_MASK_ARFR0_V1_8822B 0xffffffffffffffffL
-#define BIT_ARFR0_V1_8822B(x) (((x) & BIT_MASK_ARFR0_V1_8822B) << BIT_SHIFT_ARFR0_V1_8822B)
-#define BIT_GET_ARFR0_V1_8822B(x) (((x) >> BIT_SHIFT_ARFR0_V1_8822B) & BIT_MASK_ARFR0_V1_8822B)
-
+#define BIT_ARFR0_V1_8822B(x) \
+ (((x) & BIT_MASK_ARFR0_V1_8822B) << BIT_SHIFT_ARFR0_V1_8822B)
+#define BITS_ARFR0_V1_8822B \
+ (BIT_MASK_ARFR0_V1_8822B << BIT_SHIFT_ARFR0_V1_8822B)
+#define BIT_CLEAR_ARFR0_V1_8822B(x) ((x) & (~BITS_ARFR0_V1_8822B))
+#define BIT_GET_ARFR0_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_ARFR0_V1_8822B) & BIT_MASK_ARFR0_V1_8822B)
+#define BIT_SET_ARFR0_V1_8822B(x, v) \
+ (BIT_CLEAR_ARFR0_V1_8822B(x) | BIT_ARFR0_V1_8822B(v))
/* 2 REG_ARFR1_V1_8822B */
#define BIT_SHIFT_ARFR1_V1_8822B 0
#define BIT_MASK_ARFR1_V1_8822B 0xffffffffffffffffL
-#define BIT_ARFR1_V1_8822B(x) (((x) & BIT_MASK_ARFR1_V1_8822B) << BIT_SHIFT_ARFR1_V1_8822B)
-#define BIT_GET_ARFR1_V1_8822B(x) (((x) >> BIT_SHIFT_ARFR1_V1_8822B) & BIT_MASK_ARFR1_V1_8822B)
-
+#define BIT_ARFR1_V1_8822B(x) \
+ (((x) & BIT_MASK_ARFR1_V1_8822B) << BIT_SHIFT_ARFR1_V1_8822B)
+#define BITS_ARFR1_V1_8822B \
+ (BIT_MASK_ARFR1_V1_8822B << BIT_SHIFT_ARFR1_V1_8822B)
+#define BIT_CLEAR_ARFR1_V1_8822B(x) ((x) & (~BITS_ARFR1_V1_8822B))
+#define BIT_GET_ARFR1_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_ARFR1_V1_8822B) & BIT_MASK_ARFR1_V1_8822B)
+#define BIT_SET_ARFR1_V1_8822B(x, v) \
+ (BIT_CLEAR_ARFR1_V1_8822B(x) | BIT_ARFR1_V1_8822B(v))
/* 2 REG_CCK_CHECK_8822B */
#define BIT_CHECK_CCK_EN_8822B BIT(7)
@@ -5164,25 +8663,50 @@
#define BIT_SHIFT_AMPDU_MAX_TIME_8822B 0
#define BIT_MASK_AMPDU_MAX_TIME_8822B 0xff
-#define BIT_AMPDU_MAX_TIME_8822B(x) (((x) & BIT_MASK_AMPDU_MAX_TIME_8822B) << BIT_SHIFT_AMPDU_MAX_TIME_8822B)
-#define BIT_GET_AMPDU_MAX_TIME_8822B(x) (((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8822B) & BIT_MASK_AMPDU_MAX_TIME_8822B)
-
+#define BIT_AMPDU_MAX_TIME_8822B(x) \
+ (((x) & BIT_MASK_AMPDU_MAX_TIME_8822B) \
+ << BIT_SHIFT_AMPDU_MAX_TIME_8822B)
+#define BITS_AMPDU_MAX_TIME_8822B \
+ (BIT_MASK_AMPDU_MAX_TIME_8822B << BIT_SHIFT_AMPDU_MAX_TIME_8822B)
+#define BIT_CLEAR_AMPDU_MAX_TIME_8822B(x) ((x) & (~BITS_AMPDU_MAX_TIME_8822B))
+#define BIT_GET_AMPDU_MAX_TIME_8822B(x) \
+ (((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8822B) & \
+ BIT_MASK_AMPDU_MAX_TIME_8822B)
+#define BIT_SET_AMPDU_MAX_TIME_8822B(x, v) \
+ (BIT_CLEAR_AMPDU_MAX_TIME_8822B(x) | BIT_AMPDU_MAX_TIME_8822B(v))
/* 2 REG_BCNQ1_BDNY_V1_8822B */
#define BIT_SHIFT_BCNQ1_PGBNDY_V1_8822B 0
#define BIT_MASK_BCNQ1_PGBNDY_V1_8822B 0xfff
-#define BIT_BCNQ1_PGBNDY_V1_8822B(x) (((x) & BIT_MASK_BCNQ1_PGBNDY_V1_8822B) << BIT_SHIFT_BCNQ1_PGBNDY_V1_8822B)
-#define BIT_GET_BCNQ1_PGBNDY_V1_8822B(x) (((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1_8822B) & BIT_MASK_BCNQ1_PGBNDY_V1_8822B)
-
+#define BIT_BCNQ1_PGBNDY_V1_8822B(x) \
+ (((x) & BIT_MASK_BCNQ1_PGBNDY_V1_8822B) \
+ << BIT_SHIFT_BCNQ1_PGBNDY_V1_8822B)
+#define BITS_BCNQ1_PGBNDY_V1_8822B \
+ (BIT_MASK_BCNQ1_PGBNDY_V1_8822B << BIT_SHIFT_BCNQ1_PGBNDY_V1_8822B)
+#define BIT_CLEAR_BCNQ1_PGBNDY_V1_8822B(x) ((x) & (~BITS_BCNQ1_PGBNDY_V1_8822B))
+#define BIT_GET_BCNQ1_PGBNDY_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1_8822B) & \
+ BIT_MASK_BCNQ1_PGBNDY_V1_8822B)
+#define BIT_SET_BCNQ1_PGBNDY_V1_8822B(x, v) \
+ (BIT_CLEAR_BCNQ1_PGBNDY_V1_8822B(x) | BIT_BCNQ1_PGBNDY_V1_8822B(v))
/* 2 REG_AMPDU_MAX_LENGTH_8822B */
#define BIT_SHIFT_AMPDU_MAX_LENGTH_8822B 0
#define BIT_MASK_AMPDU_MAX_LENGTH_8822B 0xffffffffL
-#define BIT_AMPDU_MAX_LENGTH_8822B(x) (((x) & BIT_MASK_AMPDU_MAX_LENGTH_8822B) << BIT_SHIFT_AMPDU_MAX_LENGTH_8822B)
-#define BIT_GET_AMPDU_MAX_LENGTH_8822B(x) (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_8822B) & BIT_MASK_AMPDU_MAX_LENGTH_8822B)
-
+#define BIT_AMPDU_MAX_LENGTH_8822B(x) \
+ (((x) & BIT_MASK_AMPDU_MAX_LENGTH_8822B) \
+ << BIT_SHIFT_AMPDU_MAX_LENGTH_8822B)
+#define BITS_AMPDU_MAX_LENGTH_8822B \
+ (BIT_MASK_AMPDU_MAX_LENGTH_8822B << BIT_SHIFT_AMPDU_MAX_LENGTH_8822B)
+#define BIT_CLEAR_AMPDU_MAX_LENGTH_8822B(x) \
+ ((x) & (~BITS_AMPDU_MAX_LENGTH_8822B))
+#define BIT_GET_AMPDU_MAX_LENGTH_8822B(x) \
+ (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_8822B) & \
+ BIT_MASK_AMPDU_MAX_LENGTH_8822B)
+#define BIT_SET_AMPDU_MAX_LENGTH_8822B(x, v) \
+ (BIT_CLEAR_AMPDU_MAX_LENGTH_8822B(x) | BIT_AMPDU_MAX_LENGTH_8822B(v))
/* 2 REG_ACQ_STOP_8822B */
#define BIT_AC7Q_STOP_8822B BIT(7)
@@ -5198,9 +8722,17 @@
#define BIT_SHIFT_R_NDPA_RATE_V1_8822B 0
#define BIT_MASK_R_NDPA_RATE_V1_8822B 0xff
-#define BIT_R_NDPA_RATE_V1_8822B(x) (((x) & BIT_MASK_R_NDPA_RATE_V1_8822B) << BIT_SHIFT_R_NDPA_RATE_V1_8822B)
-#define BIT_GET_R_NDPA_RATE_V1_8822B(x) (((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8822B) & BIT_MASK_R_NDPA_RATE_V1_8822B)
-
+#define BIT_R_NDPA_RATE_V1_8822B(x) \
+ (((x) & BIT_MASK_R_NDPA_RATE_V1_8822B) \
+ << BIT_SHIFT_R_NDPA_RATE_V1_8822B)
+#define BITS_R_NDPA_RATE_V1_8822B \
+ (BIT_MASK_R_NDPA_RATE_V1_8822B << BIT_SHIFT_R_NDPA_RATE_V1_8822B)
+#define BIT_CLEAR_R_NDPA_RATE_V1_8822B(x) ((x) & (~BITS_R_NDPA_RATE_V1_8822B))
+#define BIT_GET_R_NDPA_RATE_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8822B) & \
+ BIT_MASK_R_NDPA_RATE_V1_8822B)
+#define BIT_SET_R_NDPA_RATE_V1_8822B(x, v) \
+ (BIT_CLEAR_R_NDPA_RATE_V1_8822B(x) | BIT_R_NDPA_RATE_V1_8822B(v))
/* 2 REG_TX_HANG_CTRL_8822B */
#define BIT_R_EN_GNT_BT_AWAKE_8822B BIT(3)
@@ -5213,201 +8745,437 @@
#define BIT_SHIFT_BW_SIGTA_8822B 3
#define BIT_MASK_BW_SIGTA_8822B 0x3
-#define BIT_BW_SIGTA_8822B(x) (((x) & BIT_MASK_BW_SIGTA_8822B) << BIT_SHIFT_BW_SIGTA_8822B)
-#define BIT_GET_BW_SIGTA_8822B(x) (((x) >> BIT_SHIFT_BW_SIGTA_8822B) & BIT_MASK_BW_SIGTA_8822B)
+#define BIT_BW_SIGTA_8822B(x) \
+ (((x) & BIT_MASK_BW_SIGTA_8822B) << BIT_SHIFT_BW_SIGTA_8822B)
+#define BITS_BW_SIGTA_8822B \
+ (BIT_MASK_BW_SIGTA_8822B << BIT_SHIFT_BW_SIGTA_8822B)
+#define BIT_CLEAR_BW_SIGTA_8822B(x) ((x) & (~BITS_BW_SIGTA_8822B))
+#define BIT_GET_BW_SIGTA_8822B(x) \
+ (((x) >> BIT_SHIFT_BW_SIGTA_8822B) & BIT_MASK_BW_SIGTA_8822B)
+#define BIT_SET_BW_SIGTA_8822B(x, v) \
+ (BIT_CLEAR_BW_SIGTA_8822B(x) | BIT_BW_SIGTA_8822B(v))
#define BIT_EN_BAR_SIGTA_8822B BIT(2)
#define BIT_SHIFT_R_NDPA_BW_8822B 0
#define BIT_MASK_R_NDPA_BW_8822B 0x3
-#define BIT_R_NDPA_BW_8822B(x) (((x) & BIT_MASK_R_NDPA_BW_8822B) << BIT_SHIFT_R_NDPA_BW_8822B)
-#define BIT_GET_R_NDPA_BW_8822B(x) (((x) >> BIT_SHIFT_R_NDPA_BW_8822B) & BIT_MASK_R_NDPA_BW_8822B)
-
+#define BIT_R_NDPA_BW_8822B(x) \
+ (((x) & BIT_MASK_R_NDPA_BW_8822B) << BIT_SHIFT_R_NDPA_BW_8822B)
+#define BITS_R_NDPA_BW_8822B \
+ (BIT_MASK_R_NDPA_BW_8822B << BIT_SHIFT_R_NDPA_BW_8822B)
+#define BIT_CLEAR_R_NDPA_BW_8822B(x) ((x) & (~BITS_R_NDPA_BW_8822B))
+#define BIT_GET_R_NDPA_BW_8822B(x) \
+ (((x) >> BIT_SHIFT_R_NDPA_BW_8822B) & BIT_MASK_R_NDPA_BW_8822B)
+#define BIT_SET_R_NDPA_BW_8822B(x, v) \
+ (BIT_CLEAR_R_NDPA_BW_8822B(x) | BIT_R_NDPA_BW_8822B(v))
/* 2 REG_RD_RESP_PKT_TH_8822B */
#define BIT_SHIFT_RD_RESP_PKT_TH_V1_8822B 0
#define BIT_MASK_RD_RESP_PKT_TH_V1_8822B 0x3f
-#define BIT_RD_RESP_PKT_TH_V1_8822B(x) (((x) & BIT_MASK_RD_RESP_PKT_TH_V1_8822B) << BIT_SHIFT_RD_RESP_PKT_TH_V1_8822B)
-#define BIT_GET_RD_RESP_PKT_TH_V1_8822B(x) (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8822B) & BIT_MASK_RD_RESP_PKT_TH_V1_8822B)
-
+#define BIT_RD_RESP_PKT_TH_V1_8822B(x) \
+ (((x) & BIT_MASK_RD_RESP_PKT_TH_V1_8822B) \
+ << BIT_SHIFT_RD_RESP_PKT_TH_V1_8822B)
+#define BITS_RD_RESP_PKT_TH_V1_8822B \
+ (BIT_MASK_RD_RESP_PKT_TH_V1_8822B << BIT_SHIFT_RD_RESP_PKT_TH_V1_8822B)
+#define BIT_CLEAR_RD_RESP_PKT_TH_V1_8822B(x) \
+ ((x) & (~BITS_RD_RESP_PKT_TH_V1_8822B))
+#define BIT_GET_RD_RESP_PKT_TH_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8822B) & \
+ BIT_MASK_RD_RESP_PKT_TH_V1_8822B)
+#define BIT_SET_RD_RESP_PKT_TH_V1_8822B(x, v) \
+ (BIT_CLEAR_RD_RESP_PKT_TH_V1_8822B(x) | BIT_RD_RESP_PKT_TH_V1_8822B(v))
/* 2 REG_CMDQ_INFO_8822B */
#define BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822B 25
#define BIT_MASK_QUEUEMACID_CMDQ_V1_8822B 0x7f
-#define BIT_QUEUEMACID_CMDQ_V1_8822B(x) (((x) & BIT_MASK_QUEUEMACID_CMDQ_V1_8822B) << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822B)
-#define BIT_GET_QUEUEMACID_CMDQ_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822B) & BIT_MASK_QUEUEMACID_CMDQ_V1_8822B)
-
+#define BIT_QUEUEMACID_CMDQ_V1_8822B(x) \
+ (((x) & BIT_MASK_QUEUEMACID_CMDQ_V1_8822B) \
+ << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822B)
+#define BITS_QUEUEMACID_CMDQ_V1_8822B \
+ (BIT_MASK_QUEUEMACID_CMDQ_V1_8822B \
+ << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822B)
+#define BIT_CLEAR_QUEUEMACID_CMDQ_V1_8822B(x) \
+ ((x) & (~BITS_QUEUEMACID_CMDQ_V1_8822B))
+#define BIT_GET_QUEUEMACID_CMDQ_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822B) & \
+ BIT_MASK_QUEUEMACID_CMDQ_V1_8822B)
+#define BIT_SET_QUEUEMACID_CMDQ_V1_8822B(x, v) \
+ (BIT_CLEAR_QUEUEMACID_CMDQ_V1_8822B(x) | \
+ BIT_QUEUEMACID_CMDQ_V1_8822B(v))
#define BIT_SHIFT_QUEUEAC_CMDQ_V1_8822B 23
#define BIT_MASK_QUEUEAC_CMDQ_V1_8822B 0x3
-#define BIT_QUEUEAC_CMDQ_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_CMDQ_V1_8822B) << BIT_SHIFT_QUEUEAC_CMDQ_V1_8822B)
-#define BIT_GET_QUEUEAC_CMDQ_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1_8822B) & BIT_MASK_QUEUEAC_CMDQ_V1_8822B)
+#define BIT_QUEUEAC_CMDQ_V1_8822B(x) \
+ (((x) & BIT_MASK_QUEUEAC_CMDQ_V1_8822B) \
+ << BIT_SHIFT_QUEUEAC_CMDQ_V1_8822B)
+#define BITS_QUEUEAC_CMDQ_V1_8822B \
+ (BIT_MASK_QUEUEAC_CMDQ_V1_8822B << BIT_SHIFT_QUEUEAC_CMDQ_V1_8822B)
+#define BIT_CLEAR_QUEUEAC_CMDQ_V1_8822B(x) ((x) & (~BITS_QUEUEAC_CMDQ_V1_8822B))
+#define BIT_GET_QUEUEAC_CMDQ_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1_8822B) & \
+ BIT_MASK_QUEUEAC_CMDQ_V1_8822B)
+#define BIT_SET_QUEUEAC_CMDQ_V1_8822B(x, v) \
+ (BIT_CLEAR_QUEUEAC_CMDQ_V1_8822B(x) | BIT_QUEUEAC_CMDQ_V1_8822B(v))
#define BIT_TIDEMPTY_CMDQ_V1_8822B BIT(22)
#define BIT_SHIFT_TAIL_PKT_CMDQ_V2_8822B 11
#define BIT_MASK_TAIL_PKT_CMDQ_V2_8822B 0x7ff
-#define BIT_TAIL_PKT_CMDQ_V2_8822B(x) (((x) & BIT_MASK_TAIL_PKT_CMDQ_V2_8822B) << BIT_SHIFT_TAIL_PKT_CMDQ_V2_8822B)
-#define BIT_GET_TAIL_PKT_CMDQ_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_CMDQ_V2_8822B) & BIT_MASK_TAIL_PKT_CMDQ_V2_8822B)
-
+#define BIT_TAIL_PKT_CMDQ_V2_8822B(x) \
+ (((x) & BIT_MASK_TAIL_PKT_CMDQ_V2_8822B) \
+ << BIT_SHIFT_TAIL_PKT_CMDQ_V2_8822B)
+#define BITS_TAIL_PKT_CMDQ_V2_8822B \
+ (BIT_MASK_TAIL_PKT_CMDQ_V2_8822B << BIT_SHIFT_TAIL_PKT_CMDQ_V2_8822B)
+#define BIT_CLEAR_TAIL_PKT_CMDQ_V2_8822B(x) \
+ ((x) & (~BITS_TAIL_PKT_CMDQ_V2_8822B))
+#define BIT_GET_TAIL_PKT_CMDQ_V2_8822B(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_CMDQ_V2_8822B) & \
+ BIT_MASK_TAIL_PKT_CMDQ_V2_8822B)
+#define BIT_SET_TAIL_PKT_CMDQ_V2_8822B(x, v) \
+ (BIT_CLEAR_TAIL_PKT_CMDQ_V2_8822B(x) | BIT_TAIL_PKT_CMDQ_V2_8822B(v))
#define BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822B 0
#define BIT_MASK_HEAD_PKT_CMDQ_V1_8822B 0x7ff
-#define BIT_HEAD_PKT_CMDQ_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_CMDQ_V1_8822B) << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822B)
-#define BIT_GET_HEAD_PKT_CMDQ_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822B) & BIT_MASK_HEAD_PKT_CMDQ_V1_8822B)
-
+#define BIT_HEAD_PKT_CMDQ_V1_8822B(x) \
+ (((x) & BIT_MASK_HEAD_PKT_CMDQ_V1_8822B) \
+ << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822B)
+#define BITS_HEAD_PKT_CMDQ_V1_8822B \
+ (BIT_MASK_HEAD_PKT_CMDQ_V1_8822B << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822B)
+#define BIT_CLEAR_HEAD_PKT_CMDQ_V1_8822B(x) \
+ ((x) & (~BITS_HEAD_PKT_CMDQ_V1_8822B))
+#define BIT_GET_HEAD_PKT_CMDQ_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822B) & \
+ BIT_MASK_HEAD_PKT_CMDQ_V1_8822B)
+#define BIT_SET_HEAD_PKT_CMDQ_V1_8822B(x, v) \
+ (BIT_CLEAR_HEAD_PKT_CMDQ_V1_8822B(x) | BIT_HEAD_PKT_CMDQ_V1_8822B(v))
/* 2 REG_Q4_INFO_8822B */
#define BIT_SHIFT_QUEUEMACID_Q4_V1_8822B 25
#define BIT_MASK_QUEUEMACID_Q4_V1_8822B 0x7f
-#define BIT_QUEUEMACID_Q4_V1_8822B(x) (((x) & BIT_MASK_QUEUEMACID_Q4_V1_8822B) << BIT_SHIFT_QUEUEMACID_Q4_V1_8822B)
-#define BIT_GET_QUEUEMACID_Q4_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1_8822B) & BIT_MASK_QUEUEMACID_Q4_V1_8822B)
-
+#define BIT_QUEUEMACID_Q4_V1_8822B(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q4_V1_8822B) \
+ << BIT_SHIFT_QUEUEMACID_Q4_V1_8822B)
+#define BITS_QUEUEMACID_Q4_V1_8822B \
+ (BIT_MASK_QUEUEMACID_Q4_V1_8822B << BIT_SHIFT_QUEUEMACID_Q4_V1_8822B)
+#define BIT_CLEAR_QUEUEMACID_Q4_V1_8822B(x) \
+ ((x) & (~BITS_QUEUEMACID_Q4_V1_8822B))
+#define BIT_GET_QUEUEMACID_Q4_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1_8822B) & \
+ BIT_MASK_QUEUEMACID_Q4_V1_8822B)
+#define BIT_SET_QUEUEMACID_Q4_V1_8822B(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q4_V1_8822B(x) | BIT_QUEUEMACID_Q4_V1_8822B(v))
#define BIT_SHIFT_QUEUEAC_Q4_V1_8822B 23
#define BIT_MASK_QUEUEAC_Q4_V1_8822B 0x3
-#define BIT_QUEUEAC_Q4_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_Q4_V1_8822B) << BIT_SHIFT_QUEUEAC_Q4_V1_8822B)
-#define BIT_GET_QUEUEAC_Q4_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q4_V1_8822B) & BIT_MASK_QUEUEAC_Q4_V1_8822B)
+#define BIT_QUEUEAC_Q4_V1_8822B(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q4_V1_8822B) << BIT_SHIFT_QUEUEAC_Q4_V1_8822B)
+#define BITS_QUEUEAC_Q4_V1_8822B \
+ (BIT_MASK_QUEUEAC_Q4_V1_8822B << BIT_SHIFT_QUEUEAC_Q4_V1_8822B)
+#define BIT_CLEAR_QUEUEAC_Q4_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q4_V1_8822B))
+#define BIT_GET_QUEUEAC_Q4_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q4_V1_8822B) & BIT_MASK_QUEUEAC_Q4_V1_8822B)
+#define BIT_SET_QUEUEAC_Q4_V1_8822B(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q4_V1_8822B(x) | BIT_QUEUEAC_Q4_V1_8822B(v))
#define BIT_TIDEMPTY_Q4_V1_8822B BIT(22)
#define BIT_SHIFT_TAIL_PKT_Q4_V2_8822B 11
#define BIT_MASK_TAIL_PKT_Q4_V2_8822B 0x7ff
-#define BIT_TAIL_PKT_Q4_V2_8822B(x) (((x) & BIT_MASK_TAIL_PKT_Q4_V2_8822B) << BIT_SHIFT_TAIL_PKT_Q4_V2_8822B)
-#define BIT_GET_TAIL_PKT_Q4_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8822B) & BIT_MASK_TAIL_PKT_Q4_V2_8822B)
-
+#define BIT_TAIL_PKT_Q4_V2_8822B(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q4_V2_8822B) \
+ << BIT_SHIFT_TAIL_PKT_Q4_V2_8822B)
+#define BITS_TAIL_PKT_Q4_V2_8822B \
+ (BIT_MASK_TAIL_PKT_Q4_V2_8822B << BIT_SHIFT_TAIL_PKT_Q4_V2_8822B)
+#define BIT_CLEAR_TAIL_PKT_Q4_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q4_V2_8822B))
+#define BIT_GET_TAIL_PKT_Q4_V2_8822B(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8822B) & \
+ BIT_MASK_TAIL_PKT_Q4_V2_8822B)
+#define BIT_SET_TAIL_PKT_Q4_V2_8822B(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q4_V2_8822B(x) | BIT_TAIL_PKT_Q4_V2_8822B(v))
#define BIT_SHIFT_HEAD_PKT_Q4_V1_8822B 0
#define BIT_MASK_HEAD_PKT_Q4_V1_8822B 0x7ff
-#define BIT_HEAD_PKT_Q4_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_Q4_V1_8822B) << BIT_SHIFT_HEAD_PKT_Q4_V1_8822B)
-#define BIT_GET_HEAD_PKT_Q4_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1_8822B) & BIT_MASK_HEAD_PKT_Q4_V1_8822B)
-
+#define BIT_HEAD_PKT_Q4_V1_8822B(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q4_V1_8822B) \
+ << BIT_SHIFT_HEAD_PKT_Q4_V1_8822B)
+#define BITS_HEAD_PKT_Q4_V1_8822B \
+ (BIT_MASK_HEAD_PKT_Q4_V1_8822B << BIT_SHIFT_HEAD_PKT_Q4_V1_8822B)
+#define BIT_CLEAR_HEAD_PKT_Q4_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q4_V1_8822B))
+#define BIT_GET_HEAD_PKT_Q4_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1_8822B) & \
+ BIT_MASK_HEAD_PKT_Q4_V1_8822B)
+#define BIT_SET_HEAD_PKT_Q4_V1_8822B(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q4_V1_8822B(x) | BIT_HEAD_PKT_Q4_V1_8822B(v))
/* 2 REG_Q5_INFO_8822B */
#define BIT_SHIFT_QUEUEMACID_Q5_V1_8822B 25
#define BIT_MASK_QUEUEMACID_Q5_V1_8822B 0x7f
-#define BIT_QUEUEMACID_Q5_V1_8822B(x) (((x) & BIT_MASK_QUEUEMACID_Q5_V1_8822B) << BIT_SHIFT_QUEUEMACID_Q5_V1_8822B)
-#define BIT_GET_QUEUEMACID_Q5_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1_8822B) & BIT_MASK_QUEUEMACID_Q5_V1_8822B)
-
+#define BIT_QUEUEMACID_Q5_V1_8822B(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q5_V1_8822B) \
+ << BIT_SHIFT_QUEUEMACID_Q5_V1_8822B)
+#define BITS_QUEUEMACID_Q5_V1_8822B \
+ (BIT_MASK_QUEUEMACID_Q5_V1_8822B << BIT_SHIFT_QUEUEMACID_Q5_V1_8822B)
+#define BIT_CLEAR_QUEUEMACID_Q5_V1_8822B(x) \
+ ((x) & (~BITS_QUEUEMACID_Q5_V1_8822B))
+#define BIT_GET_QUEUEMACID_Q5_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1_8822B) & \
+ BIT_MASK_QUEUEMACID_Q5_V1_8822B)
+#define BIT_SET_QUEUEMACID_Q5_V1_8822B(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q5_V1_8822B(x) | BIT_QUEUEMACID_Q5_V1_8822B(v))
#define BIT_SHIFT_QUEUEAC_Q5_V1_8822B 23
#define BIT_MASK_QUEUEAC_Q5_V1_8822B 0x3
-#define BIT_QUEUEAC_Q5_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_Q5_V1_8822B) << BIT_SHIFT_QUEUEAC_Q5_V1_8822B)
-#define BIT_GET_QUEUEAC_Q5_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q5_V1_8822B) & BIT_MASK_QUEUEAC_Q5_V1_8822B)
+#define BIT_QUEUEAC_Q5_V1_8822B(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q5_V1_8822B) << BIT_SHIFT_QUEUEAC_Q5_V1_8822B)
+#define BITS_QUEUEAC_Q5_V1_8822B \
+ (BIT_MASK_QUEUEAC_Q5_V1_8822B << BIT_SHIFT_QUEUEAC_Q5_V1_8822B)
+#define BIT_CLEAR_QUEUEAC_Q5_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q5_V1_8822B))
+#define BIT_GET_QUEUEAC_Q5_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q5_V1_8822B) & BIT_MASK_QUEUEAC_Q5_V1_8822B)
+#define BIT_SET_QUEUEAC_Q5_V1_8822B(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q5_V1_8822B(x) | BIT_QUEUEAC_Q5_V1_8822B(v))
#define BIT_TIDEMPTY_Q5_V1_8822B BIT(22)
#define BIT_SHIFT_TAIL_PKT_Q5_V2_8822B 11
#define BIT_MASK_TAIL_PKT_Q5_V2_8822B 0x7ff
-#define BIT_TAIL_PKT_Q5_V2_8822B(x) (((x) & BIT_MASK_TAIL_PKT_Q5_V2_8822B) << BIT_SHIFT_TAIL_PKT_Q5_V2_8822B)
-#define BIT_GET_TAIL_PKT_Q5_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2_8822B) & BIT_MASK_TAIL_PKT_Q5_V2_8822B)
-
+#define BIT_TAIL_PKT_Q5_V2_8822B(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q5_V2_8822B) \
+ << BIT_SHIFT_TAIL_PKT_Q5_V2_8822B)
+#define BITS_TAIL_PKT_Q5_V2_8822B \
+ (BIT_MASK_TAIL_PKT_Q5_V2_8822B << BIT_SHIFT_TAIL_PKT_Q5_V2_8822B)
+#define BIT_CLEAR_TAIL_PKT_Q5_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q5_V2_8822B))
+#define BIT_GET_TAIL_PKT_Q5_V2_8822B(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2_8822B) & \
+ BIT_MASK_TAIL_PKT_Q5_V2_8822B)
+#define BIT_SET_TAIL_PKT_Q5_V2_8822B(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q5_V2_8822B(x) | BIT_TAIL_PKT_Q5_V2_8822B(v))
#define BIT_SHIFT_HEAD_PKT_Q5_V1_8822B 0
#define BIT_MASK_HEAD_PKT_Q5_V1_8822B 0x7ff
-#define BIT_HEAD_PKT_Q5_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_Q5_V1_8822B) << BIT_SHIFT_HEAD_PKT_Q5_V1_8822B)
-#define BIT_GET_HEAD_PKT_Q5_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1_8822B) & BIT_MASK_HEAD_PKT_Q5_V1_8822B)
-
+#define BIT_HEAD_PKT_Q5_V1_8822B(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q5_V1_8822B) \
+ << BIT_SHIFT_HEAD_PKT_Q5_V1_8822B)
+#define BITS_HEAD_PKT_Q5_V1_8822B \
+ (BIT_MASK_HEAD_PKT_Q5_V1_8822B << BIT_SHIFT_HEAD_PKT_Q5_V1_8822B)
+#define BIT_CLEAR_HEAD_PKT_Q5_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q5_V1_8822B))
+#define BIT_GET_HEAD_PKT_Q5_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1_8822B) & \
+ BIT_MASK_HEAD_PKT_Q5_V1_8822B)
+#define BIT_SET_HEAD_PKT_Q5_V1_8822B(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q5_V1_8822B(x) | BIT_HEAD_PKT_Q5_V1_8822B(v))
/* 2 REG_Q6_INFO_8822B */
#define BIT_SHIFT_QUEUEMACID_Q6_V1_8822B 25
#define BIT_MASK_QUEUEMACID_Q6_V1_8822B 0x7f
-#define BIT_QUEUEMACID_Q6_V1_8822B(x) (((x) & BIT_MASK_QUEUEMACID_Q6_V1_8822B) << BIT_SHIFT_QUEUEMACID_Q6_V1_8822B)
-#define BIT_GET_QUEUEMACID_Q6_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1_8822B) & BIT_MASK_QUEUEMACID_Q6_V1_8822B)
-
+#define BIT_QUEUEMACID_Q6_V1_8822B(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q6_V1_8822B) \
+ << BIT_SHIFT_QUEUEMACID_Q6_V1_8822B)
+#define BITS_QUEUEMACID_Q6_V1_8822B \
+ (BIT_MASK_QUEUEMACID_Q6_V1_8822B << BIT_SHIFT_QUEUEMACID_Q6_V1_8822B)
+#define BIT_CLEAR_QUEUEMACID_Q6_V1_8822B(x) \
+ ((x) & (~BITS_QUEUEMACID_Q6_V1_8822B))
+#define BIT_GET_QUEUEMACID_Q6_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1_8822B) & \
+ BIT_MASK_QUEUEMACID_Q6_V1_8822B)
+#define BIT_SET_QUEUEMACID_Q6_V1_8822B(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q6_V1_8822B(x) | BIT_QUEUEMACID_Q6_V1_8822B(v))
#define BIT_SHIFT_QUEUEAC_Q6_V1_8822B 23
#define BIT_MASK_QUEUEAC_Q6_V1_8822B 0x3
-#define BIT_QUEUEAC_Q6_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_Q6_V1_8822B) << BIT_SHIFT_QUEUEAC_Q6_V1_8822B)
-#define BIT_GET_QUEUEAC_Q6_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q6_V1_8822B) & BIT_MASK_QUEUEAC_Q6_V1_8822B)
+#define BIT_QUEUEAC_Q6_V1_8822B(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q6_V1_8822B) << BIT_SHIFT_QUEUEAC_Q6_V1_8822B)
+#define BITS_QUEUEAC_Q6_V1_8822B \
+ (BIT_MASK_QUEUEAC_Q6_V1_8822B << BIT_SHIFT_QUEUEAC_Q6_V1_8822B)
+#define BIT_CLEAR_QUEUEAC_Q6_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q6_V1_8822B))
+#define BIT_GET_QUEUEAC_Q6_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q6_V1_8822B) & BIT_MASK_QUEUEAC_Q6_V1_8822B)
+#define BIT_SET_QUEUEAC_Q6_V1_8822B(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q6_V1_8822B(x) | BIT_QUEUEAC_Q6_V1_8822B(v))
#define BIT_TIDEMPTY_Q6_V1_8822B BIT(22)
#define BIT_SHIFT_TAIL_PKT_Q6_V2_8822B 11
#define BIT_MASK_TAIL_PKT_Q6_V2_8822B 0x7ff
-#define BIT_TAIL_PKT_Q6_V2_8822B(x) (((x) & BIT_MASK_TAIL_PKT_Q6_V2_8822B) << BIT_SHIFT_TAIL_PKT_Q6_V2_8822B)
-#define BIT_GET_TAIL_PKT_Q6_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2_8822B) & BIT_MASK_TAIL_PKT_Q6_V2_8822B)
-
+#define BIT_TAIL_PKT_Q6_V2_8822B(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q6_V2_8822B) \
+ << BIT_SHIFT_TAIL_PKT_Q6_V2_8822B)
+#define BITS_TAIL_PKT_Q6_V2_8822B \
+ (BIT_MASK_TAIL_PKT_Q6_V2_8822B << BIT_SHIFT_TAIL_PKT_Q6_V2_8822B)
+#define BIT_CLEAR_TAIL_PKT_Q6_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q6_V2_8822B))
+#define BIT_GET_TAIL_PKT_Q6_V2_8822B(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2_8822B) & \
+ BIT_MASK_TAIL_PKT_Q6_V2_8822B)
+#define BIT_SET_TAIL_PKT_Q6_V2_8822B(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q6_V2_8822B(x) | BIT_TAIL_PKT_Q6_V2_8822B(v))
#define BIT_SHIFT_HEAD_PKT_Q6_V1_8822B 0
#define BIT_MASK_HEAD_PKT_Q6_V1_8822B 0x7ff
-#define BIT_HEAD_PKT_Q6_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_Q6_V1_8822B) << BIT_SHIFT_HEAD_PKT_Q6_V1_8822B)
-#define BIT_GET_HEAD_PKT_Q6_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1_8822B) & BIT_MASK_HEAD_PKT_Q6_V1_8822B)
-
+#define BIT_HEAD_PKT_Q6_V1_8822B(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q6_V1_8822B) \
+ << BIT_SHIFT_HEAD_PKT_Q6_V1_8822B)
+#define BITS_HEAD_PKT_Q6_V1_8822B \
+ (BIT_MASK_HEAD_PKT_Q6_V1_8822B << BIT_SHIFT_HEAD_PKT_Q6_V1_8822B)
+#define BIT_CLEAR_HEAD_PKT_Q6_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q6_V1_8822B))
+#define BIT_GET_HEAD_PKT_Q6_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1_8822B) & \
+ BIT_MASK_HEAD_PKT_Q6_V1_8822B)
+#define BIT_SET_HEAD_PKT_Q6_V1_8822B(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q6_V1_8822B(x) | BIT_HEAD_PKT_Q6_V1_8822B(v))
/* 2 REG_Q7_INFO_8822B */
#define BIT_SHIFT_QUEUEMACID_Q7_V1_8822B 25
#define BIT_MASK_QUEUEMACID_Q7_V1_8822B 0x7f
-#define BIT_QUEUEMACID_Q7_V1_8822B(x) (((x) & BIT_MASK_QUEUEMACID_Q7_V1_8822B) << BIT_SHIFT_QUEUEMACID_Q7_V1_8822B)
-#define BIT_GET_QUEUEMACID_Q7_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1_8822B) & BIT_MASK_QUEUEMACID_Q7_V1_8822B)
-
+#define BIT_QUEUEMACID_Q7_V1_8822B(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q7_V1_8822B) \
+ << BIT_SHIFT_QUEUEMACID_Q7_V1_8822B)
+#define BITS_QUEUEMACID_Q7_V1_8822B \
+ (BIT_MASK_QUEUEMACID_Q7_V1_8822B << BIT_SHIFT_QUEUEMACID_Q7_V1_8822B)
+#define BIT_CLEAR_QUEUEMACID_Q7_V1_8822B(x) \
+ ((x) & (~BITS_QUEUEMACID_Q7_V1_8822B))
+#define BIT_GET_QUEUEMACID_Q7_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1_8822B) & \
+ BIT_MASK_QUEUEMACID_Q7_V1_8822B)
+#define BIT_SET_QUEUEMACID_Q7_V1_8822B(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q7_V1_8822B(x) | BIT_QUEUEMACID_Q7_V1_8822B(v))
#define BIT_SHIFT_QUEUEAC_Q7_V1_8822B 23
#define BIT_MASK_QUEUEAC_Q7_V1_8822B 0x3
-#define BIT_QUEUEAC_Q7_V1_8822B(x) (((x) & BIT_MASK_QUEUEAC_Q7_V1_8822B) << BIT_SHIFT_QUEUEAC_Q7_V1_8822B)
-#define BIT_GET_QUEUEAC_Q7_V1_8822B(x) (((x) >> BIT_SHIFT_QUEUEAC_Q7_V1_8822B) & BIT_MASK_QUEUEAC_Q7_V1_8822B)
+#define BIT_QUEUEAC_Q7_V1_8822B(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q7_V1_8822B) << BIT_SHIFT_QUEUEAC_Q7_V1_8822B)
+#define BITS_QUEUEAC_Q7_V1_8822B \
+ (BIT_MASK_QUEUEAC_Q7_V1_8822B << BIT_SHIFT_QUEUEAC_Q7_V1_8822B)
+#define BIT_CLEAR_QUEUEAC_Q7_V1_8822B(x) ((x) & (~BITS_QUEUEAC_Q7_V1_8822B))
+#define BIT_GET_QUEUEAC_Q7_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q7_V1_8822B) & BIT_MASK_QUEUEAC_Q7_V1_8822B)
+#define BIT_SET_QUEUEAC_Q7_V1_8822B(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q7_V1_8822B(x) | BIT_QUEUEAC_Q7_V1_8822B(v))
#define BIT_TIDEMPTY_Q7_V1_8822B BIT(22)
#define BIT_SHIFT_TAIL_PKT_Q7_V2_8822B 11
#define BIT_MASK_TAIL_PKT_Q7_V2_8822B 0x7ff
-#define BIT_TAIL_PKT_Q7_V2_8822B(x) (((x) & BIT_MASK_TAIL_PKT_Q7_V2_8822B) << BIT_SHIFT_TAIL_PKT_Q7_V2_8822B)
-#define BIT_GET_TAIL_PKT_Q7_V2_8822B(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2_8822B) & BIT_MASK_TAIL_PKT_Q7_V2_8822B)
-
+#define BIT_TAIL_PKT_Q7_V2_8822B(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q7_V2_8822B) \
+ << BIT_SHIFT_TAIL_PKT_Q7_V2_8822B)
+#define BITS_TAIL_PKT_Q7_V2_8822B \
+ (BIT_MASK_TAIL_PKT_Q7_V2_8822B << BIT_SHIFT_TAIL_PKT_Q7_V2_8822B)
+#define BIT_CLEAR_TAIL_PKT_Q7_V2_8822B(x) ((x) & (~BITS_TAIL_PKT_Q7_V2_8822B))
+#define BIT_GET_TAIL_PKT_Q7_V2_8822B(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2_8822B) & \
+ BIT_MASK_TAIL_PKT_Q7_V2_8822B)
+#define BIT_SET_TAIL_PKT_Q7_V2_8822B(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q7_V2_8822B(x) | BIT_TAIL_PKT_Q7_V2_8822B(v))
#define BIT_SHIFT_HEAD_PKT_Q7_V1_8822B 0
#define BIT_MASK_HEAD_PKT_Q7_V1_8822B 0x7ff
-#define BIT_HEAD_PKT_Q7_V1_8822B(x) (((x) & BIT_MASK_HEAD_PKT_Q7_V1_8822B) << BIT_SHIFT_HEAD_PKT_Q7_V1_8822B)
-#define BIT_GET_HEAD_PKT_Q7_V1_8822B(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1_8822B) & BIT_MASK_HEAD_PKT_Q7_V1_8822B)
-
+#define BIT_HEAD_PKT_Q7_V1_8822B(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q7_V1_8822B) \
+ << BIT_SHIFT_HEAD_PKT_Q7_V1_8822B)
+#define BITS_HEAD_PKT_Q7_V1_8822B \
+ (BIT_MASK_HEAD_PKT_Q7_V1_8822B << BIT_SHIFT_HEAD_PKT_Q7_V1_8822B)
+#define BIT_CLEAR_HEAD_PKT_Q7_V1_8822B(x) ((x) & (~BITS_HEAD_PKT_Q7_V1_8822B))
+#define BIT_GET_HEAD_PKT_Q7_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1_8822B) & \
+ BIT_MASK_HEAD_PKT_Q7_V1_8822B)
+#define BIT_SET_HEAD_PKT_Q7_V1_8822B(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q7_V1_8822B(x) | BIT_HEAD_PKT_Q7_V1_8822B(v))
/* 2 REG_WMAC_LBK_BUF_HD_V1_8822B */
#define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822B 0
#define BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822B 0xfff
-#define BIT_WMAC_LBK_BUF_HEAD_V1_8822B(x) (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822B) << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822B)
-#define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8822B(x) (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822B) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822B)
-
+#define BIT_WMAC_LBK_BUF_HEAD_V1_8822B(x) \
+ (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822B) \
+ << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822B)
+#define BITS_WMAC_LBK_BUF_HEAD_V1_8822B \
+ (BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822B \
+ << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822B)
+#define BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8822B(x) \
+ ((x) & (~BITS_WMAC_LBK_BUF_HEAD_V1_8822B))
+#define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822B) & \
+ BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822B)
+#define BIT_SET_WMAC_LBK_BUF_HEAD_V1_8822B(x, v) \
+ (BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8822B(x) | \
+ BIT_WMAC_LBK_BUF_HEAD_V1_8822B(v))
/* 2 REG_MGQ_BDNY_V1_8822B */
#define BIT_SHIFT_MGQ_PGBNDY_V1_8822B 0
#define BIT_MASK_MGQ_PGBNDY_V1_8822B 0xfff
-#define BIT_MGQ_PGBNDY_V1_8822B(x) (((x) & BIT_MASK_MGQ_PGBNDY_V1_8822B) << BIT_SHIFT_MGQ_PGBNDY_V1_8822B)
-#define BIT_GET_MGQ_PGBNDY_V1_8822B(x) (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8822B) & BIT_MASK_MGQ_PGBNDY_V1_8822B)
-
+#define BIT_MGQ_PGBNDY_V1_8822B(x) \
+ (((x) & BIT_MASK_MGQ_PGBNDY_V1_8822B) << BIT_SHIFT_MGQ_PGBNDY_V1_8822B)
+#define BITS_MGQ_PGBNDY_V1_8822B \
+ (BIT_MASK_MGQ_PGBNDY_V1_8822B << BIT_SHIFT_MGQ_PGBNDY_V1_8822B)
+#define BIT_CLEAR_MGQ_PGBNDY_V1_8822B(x) ((x) & (~BITS_MGQ_PGBNDY_V1_8822B))
+#define BIT_GET_MGQ_PGBNDY_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8822B) & BIT_MASK_MGQ_PGBNDY_V1_8822B)
+#define BIT_SET_MGQ_PGBNDY_V1_8822B(x, v) \
+ (BIT_CLEAR_MGQ_PGBNDY_V1_8822B(x) | BIT_MGQ_PGBNDY_V1_8822B(v))
/* 2 REG_TXRPT_CTRL_8822B */
#define BIT_SHIFT_TRXRPT_TIMER_TH_8822B 24
#define BIT_MASK_TRXRPT_TIMER_TH_8822B 0xff
-#define BIT_TRXRPT_TIMER_TH_8822B(x) (((x) & BIT_MASK_TRXRPT_TIMER_TH_8822B) << BIT_SHIFT_TRXRPT_TIMER_TH_8822B)
-#define BIT_GET_TRXRPT_TIMER_TH_8822B(x) (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8822B) & BIT_MASK_TRXRPT_TIMER_TH_8822B)
-
+#define BIT_TRXRPT_TIMER_TH_8822B(x) \
+ (((x) & BIT_MASK_TRXRPT_TIMER_TH_8822B) \
+ << BIT_SHIFT_TRXRPT_TIMER_TH_8822B)
+#define BITS_TRXRPT_TIMER_TH_8822B \
+ (BIT_MASK_TRXRPT_TIMER_TH_8822B << BIT_SHIFT_TRXRPT_TIMER_TH_8822B)
+#define BIT_CLEAR_TRXRPT_TIMER_TH_8822B(x) ((x) & (~BITS_TRXRPT_TIMER_TH_8822B))
+#define BIT_GET_TRXRPT_TIMER_TH_8822B(x) \
+ (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8822B) & \
+ BIT_MASK_TRXRPT_TIMER_TH_8822B)
+#define BIT_SET_TRXRPT_TIMER_TH_8822B(x, v) \
+ (BIT_CLEAR_TRXRPT_TIMER_TH_8822B(x) | BIT_TRXRPT_TIMER_TH_8822B(v))
#define BIT_SHIFT_TRXRPT_LEN_TH_8822B 16
#define BIT_MASK_TRXRPT_LEN_TH_8822B 0xff
-#define BIT_TRXRPT_LEN_TH_8822B(x) (((x) & BIT_MASK_TRXRPT_LEN_TH_8822B) << BIT_SHIFT_TRXRPT_LEN_TH_8822B)
-#define BIT_GET_TRXRPT_LEN_TH_8822B(x) (((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8822B) & BIT_MASK_TRXRPT_LEN_TH_8822B)
-
+#define BIT_TRXRPT_LEN_TH_8822B(x) \
+ (((x) & BIT_MASK_TRXRPT_LEN_TH_8822B) << BIT_SHIFT_TRXRPT_LEN_TH_8822B)
+#define BITS_TRXRPT_LEN_TH_8822B \
+ (BIT_MASK_TRXRPT_LEN_TH_8822B << BIT_SHIFT_TRXRPT_LEN_TH_8822B)
+#define BIT_CLEAR_TRXRPT_LEN_TH_8822B(x) ((x) & (~BITS_TRXRPT_LEN_TH_8822B))
+#define BIT_GET_TRXRPT_LEN_TH_8822B(x) \
+ (((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8822B) & BIT_MASK_TRXRPT_LEN_TH_8822B)
+#define BIT_SET_TRXRPT_LEN_TH_8822B(x, v) \
+ (BIT_CLEAR_TRXRPT_LEN_TH_8822B(x) | BIT_TRXRPT_LEN_TH_8822B(v))
#define BIT_SHIFT_TRXRPT_READ_PTR_8822B 8
#define BIT_MASK_TRXRPT_READ_PTR_8822B 0xff
-#define BIT_TRXRPT_READ_PTR_8822B(x) (((x) & BIT_MASK_TRXRPT_READ_PTR_8822B) << BIT_SHIFT_TRXRPT_READ_PTR_8822B)
-#define BIT_GET_TRXRPT_READ_PTR_8822B(x) (((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8822B) & BIT_MASK_TRXRPT_READ_PTR_8822B)
-
+#define BIT_TRXRPT_READ_PTR_8822B(x) \
+ (((x) & BIT_MASK_TRXRPT_READ_PTR_8822B) \
+ << BIT_SHIFT_TRXRPT_READ_PTR_8822B)
+#define BITS_TRXRPT_READ_PTR_8822B \
+ (BIT_MASK_TRXRPT_READ_PTR_8822B << BIT_SHIFT_TRXRPT_READ_PTR_8822B)
+#define BIT_CLEAR_TRXRPT_READ_PTR_8822B(x) ((x) & (~BITS_TRXRPT_READ_PTR_8822B))
+#define BIT_GET_TRXRPT_READ_PTR_8822B(x) \
+ (((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8822B) & \
+ BIT_MASK_TRXRPT_READ_PTR_8822B)
+#define BIT_SET_TRXRPT_READ_PTR_8822B(x, v) \
+ (BIT_CLEAR_TRXRPT_READ_PTR_8822B(x) | BIT_TRXRPT_READ_PTR_8822B(v))
#define BIT_SHIFT_TRXRPT_WRITE_PTR_8822B 0
#define BIT_MASK_TRXRPT_WRITE_PTR_8822B 0xff
-#define BIT_TRXRPT_WRITE_PTR_8822B(x) (((x) & BIT_MASK_TRXRPT_WRITE_PTR_8822B) << BIT_SHIFT_TRXRPT_WRITE_PTR_8822B)
-#define BIT_GET_TRXRPT_WRITE_PTR_8822B(x) (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8822B) & BIT_MASK_TRXRPT_WRITE_PTR_8822B)
-
+#define BIT_TRXRPT_WRITE_PTR_8822B(x) \
+ (((x) & BIT_MASK_TRXRPT_WRITE_PTR_8822B) \
+ << BIT_SHIFT_TRXRPT_WRITE_PTR_8822B)
+#define BITS_TRXRPT_WRITE_PTR_8822B \
+ (BIT_MASK_TRXRPT_WRITE_PTR_8822B << BIT_SHIFT_TRXRPT_WRITE_PTR_8822B)
+#define BIT_CLEAR_TRXRPT_WRITE_PTR_8822B(x) \
+ ((x) & (~BITS_TRXRPT_WRITE_PTR_8822B))
+#define BIT_GET_TRXRPT_WRITE_PTR_8822B(x) \
+ (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8822B) & \
+ BIT_MASK_TRXRPT_WRITE_PTR_8822B)
+#define BIT_SET_TRXRPT_WRITE_PTR_8822B(x, v) \
+ (BIT_CLEAR_TRXRPT_WRITE_PTR_8822B(x) | BIT_TRXRPT_WRITE_PTR_8822B(v))
/* 2 REG_INIRTS_RATE_SEL_8822B */
#define BIT_LEAG_RTS_BW_DUP_8822B BIT(5)
@@ -5416,100 +9184,205 @@
#define BIT_SHIFT_BASIC_CFEND_RATE_8822B 0
#define BIT_MASK_BASIC_CFEND_RATE_8822B 0x1f
-#define BIT_BASIC_CFEND_RATE_8822B(x) (((x) & BIT_MASK_BASIC_CFEND_RATE_8822B) << BIT_SHIFT_BASIC_CFEND_RATE_8822B)
-#define BIT_GET_BASIC_CFEND_RATE_8822B(x) (((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8822B) & BIT_MASK_BASIC_CFEND_RATE_8822B)
-
+#define BIT_BASIC_CFEND_RATE_8822B(x) \
+ (((x) & BIT_MASK_BASIC_CFEND_RATE_8822B) \
+ << BIT_SHIFT_BASIC_CFEND_RATE_8822B)
+#define BITS_BASIC_CFEND_RATE_8822B \
+ (BIT_MASK_BASIC_CFEND_RATE_8822B << BIT_SHIFT_BASIC_CFEND_RATE_8822B)
+#define BIT_CLEAR_BASIC_CFEND_RATE_8822B(x) \
+ ((x) & (~BITS_BASIC_CFEND_RATE_8822B))
+#define BIT_GET_BASIC_CFEND_RATE_8822B(x) \
+ (((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8822B) & \
+ BIT_MASK_BASIC_CFEND_RATE_8822B)
+#define BIT_SET_BASIC_CFEND_RATE_8822B(x, v) \
+ (BIT_CLEAR_BASIC_CFEND_RATE_8822B(x) | BIT_BASIC_CFEND_RATE_8822B(v))
/* 2 REG_STBC_CFEND_RATE_8822B */
#define BIT_SHIFT_STBC_CFEND_RATE_8822B 0
#define BIT_MASK_STBC_CFEND_RATE_8822B 0x1f
-#define BIT_STBC_CFEND_RATE_8822B(x) (((x) & BIT_MASK_STBC_CFEND_RATE_8822B) << BIT_SHIFT_STBC_CFEND_RATE_8822B)
-#define BIT_GET_STBC_CFEND_RATE_8822B(x) (((x) >> BIT_SHIFT_STBC_CFEND_RATE_8822B) & BIT_MASK_STBC_CFEND_RATE_8822B)
-
+#define BIT_STBC_CFEND_RATE_8822B(x) \
+ (((x) & BIT_MASK_STBC_CFEND_RATE_8822B) \
+ << BIT_SHIFT_STBC_CFEND_RATE_8822B)
+#define BITS_STBC_CFEND_RATE_8822B \
+ (BIT_MASK_STBC_CFEND_RATE_8822B << BIT_SHIFT_STBC_CFEND_RATE_8822B)
+#define BIT_CLEAR_STBC_CFEND_RATE_8822B(x) ((x) & (~BITS_STBC_CFEND_RATE_8822B))
+#define BIT_GET_STBC_CFEND_RATE_8822B(x) \
+ (((x) >> BIT_SHIFT_STBC_CFEND_RATE_8822B) & \
+ BIT_MASK_STBC_CFEND_RATE_8822B)
+#define BIT_SET_STBC_CFEND_RATE_8822B(x, v) \
+ (BIT_CLEAR_STBC_CFEND_RATE_8822B(x) | BIT_STBC_CFEND_RATE_8822B(v))
/* 2 REG_DATA_SC_8822B */
#define BIT_SHIFT_TXSC_40M_8822B 4
#define BIT_MASK_TXSC_40M_8822B 0xf
-#define BIT_TXSC_40M_8822B(x) (((x) & BIT_MASK_TXSC_40M_8822B) << BIT_SHIFT_TXSC_40M_8822B)
-#define BIT_GET_TXSC_40M_8822B(x) (((x) >> BIT_SHIFT_TXSC_40M_8822B) & BIT_MASK_TXSC_40M_8822B)
-
+#define BIT_TXSC_40M_8822B(x) \
+ (((x) & BIT_MASK_TXSC_40M_8822B) << BIT_SHIFT_TXSC_40M_8822B)
+#define BITS_TXSC_40M_8822B \
+ (BIT_MASK_TXSC_40M_8822B << BIT_SHIFT_TXSC_40M_8822B)
+#define BIT_CLEAR_TXSC_40M_8822B(x) ((x) & (~BITS_TXSC_40M_8822B))
+#define BIT_GET_TXSC_40M_8822B(x) \
+ (((x) >> BIT_SHIFT_TXSC_40M_8822B) & BIT_MASK_TXSC_40M_8822B)
+#define BIT_SET_TXSC_40M_8822B(x, v) \
+ (BIT_CLEAR_TXSC_40M_8822B(x) | BIT_TXSC_40M_8822B(v))
#define BIT_SHIFT_TXSC_20M_8822B 0
#define BIT_MASK_TXSC_20M_8822B 0xf
-#define BIT_TXSC_20M_8822B(x) (((x) & BIT_MASK_TXSC_20M_8822B) << BIT_SHIFT_TXSC_20M_8822B)
-#define BIT_GET_TXSC_20M_8822B(x) (((x) >> BIT_SHIFT_TXSC_20M_8822B) & BIT_MASK_TXSC_20M_8822B)
-
+#define BIT_TXSC_20M_8822B(x) \
+ (((x) & BIT_MASK_TXSC_20M_8822B) << BIT_SHIFT_TXSC_20M_8822B)
+#define BITS_TXSC_20M_8822B \
+ (BIT_MASK_TXSC_20M_8822B << BIT_SHIFT_TXSC_20M_8822B)
+#define BIT_CLEAR_TXSC_20M_8822B(x) ((x) & (~BITS_TXSC_20M_8822B))
+#define BIT_GET_TXSC_20M_8822B(x) \
+ (((x) >> BIT_SHIFT_TXSC_20M_8822B) & BIT_MASK_TXSC_20M_8822B)
+#define BIT_SET_TXSC_20M_8822B(x, v) \
+ (BIT_CLEAR_TXSC_20M_8822B(x) | BIT_TXSC_20M_8822B(v))
/* 2 REG_MACID_SLEEP3_8822B */
#define BIT_SHIFT_MACID127_96_PKTSLEEP_8822B 0
#define BIT_MASK_MACID127_96_PKTSLEEP_8822B 0xffffffffL
-#define BIT_MACID127_96_PKTSLEEP_8822B(x) (((x) & BIT_MASK_MACID127_96_PKTSLEEP_8822B) << BIT_SHIFT_MACID127_96_PKTSLEEP_8822B)
-#define BIT_GET_MACID127_96_PKTSLEEP_8822B(x) (((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP_8822B) & BIT_MASK_MACID127_96_PKTSLEEP_8822B)
-
+#define BIT_MACID127_96_PKTSLEEP_8822B(x) \
+ (((x) & BIT_MASK_MACID127_96_PKTSLEEP_8822B) \
+ << BIT_SHIFT_MACID127_96_PKTSLEEP_8822B)
+#define BITS_MACID127_96_PKTSLEEP_8822B \
+ (BIT_MASK_MACID127_96_PKTSLEEP_8822B \
+ << BIT_SHIFT_MACID127_96_PKTSLEEP_8822B)
+#define BIT_CLEAR_MACID127_96_PKTSLEEP_8822B(x) \
+ ((x) & (~BITS_MACID127_96_PKTSLEEP_8822B))
+#define BIT_GET_MACID127_96_PKTSLEEP_8822B(x) \
+ (((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP_8822B) & \
+ BIT_MASK_MACID127_96_PKTSLEEP_8822B)
+#define BIT_SET_MACID127_96_PKTSLEEP_8822B(x, v) \
+ (BIT_CLEAR_MACID127_96_PKTSLEEP_8822B(x) | \
+ BIT_MACID127_96_PKTSLEEP_8822B(v))
/* 2 REG_MACID_SLEEP1_8822B */
#define BIT_SHIFT_MACID63_32_PKTSLEEP_8822B 0
#define BIT_MASK_MACID63_32_PKTSLEEP_8822B 0xffffffffL
-#define BIT_MACID63_32_PKTSLEEP_8822B(x) (((x) & BIT_MASK_MACID63_32_PKTSLEEP_8822B) << BIT_SHIFT_MACID63_32_PKTSLEEP_8822B)
-#define BIT_GET_MACID63_32_PKTSLEEP_8822B(x) (((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP_8822B) & BIT_MASK_MACID63_32_PKTSLEEP_8822B)
-
+#define BIT_MACID63_32_PKTSLEEP_8822B(x) \
+ (((x) & BIT_MASK_MACID63_32_PKTSLEEP_8822B) \
+ << BIT_SHIFT_MACID63_32_PKTSLEEP_8822B)
+#define BITS_MACID63_32_PKTSLEEP_8822B \
+ (BIT_MASK_MACID63_32_PKTSLEEP_8822B \
+ << BIT_SHIFT_MACID63_32_PKTSLEEP_8822B)
+#define BIT_CLEAR_MACID63_32_PKTSLEEP_8822B(x) \
+ ((x) & (~BITS_MACID63_32_PKTSLEEP_8822B))
+#define BIT_GET_MACID63_32_PKTSLEEP_8822B(x) \
+ (((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP_8822B) & \
+ BIT_MASK_MACID63_32_PKTSLEEP_8822B)
+#define BIT_SET_MACID63_32_PKTSLEEP_8822B(x, v) \
+ (BIT_CLEAR_MACID63_32_PKTSLEEP_8822B(x) | \
+ BIT_MACID63_32_PKTSLEEP_8822B(v))
/* 2 REG_ARFR2_V1_8822B */
#define BIT_SHIFT_ARFR2_V1_8822B 0
#define BIT_MASK_ARFR2_V1_8822B 0xffffffffffffffffL
-#define BIT_ARFR2_V1_8822B(x) (((x) & BIT_MASK_ARFR2_V1_8822B) << BIT_SHIFT_ARFR2_V1_8822B)
-#define BIT_GET_ARFR2_V1_8822B(x) (((x) >> BIT_SHIFT_ARFR2_V1_8822B) & BIT_MASK_ARFR2_V1_8822B)
-
+#define BIT_ARFR2_V1_8822B(x) \
+ (((x) & BIT_MASK_ARFR2_V1_8822B) << BIT_SHIFT_ARFR2_V1_8822B)
+#define BITS_ARFR2_V1_8822B \
+ (BIT_MASK_ARFR2_V1_8822B << BIT_SHIFT_ARFR2_V1_8822B)
+#define BIT_CLEAR_ARFR2_V1_8822B(x) ((x) & (~BITS_ARFR2_V1_8822B))
+#define BIT_GET_ARFR2_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_ARFR2_V1_8822B) & BIT_MASK_ARFR2_V1_8822B)
+#define BIT_SET_ARFR2_V1_8822B(x, v) \
+ (BIT_CLEAR_ARFR2_V1_8822B(x) | BIT_ARFR2_V1_8822B(v))
/* 2 REG_ARFR3_V1_8822B */
#define BIT_SHIFT_ARFR3_V1_8822B 0
#define BIT_MASK_ARFR3_V1_8822B 0xffffffffffffffffL
-#define BIT_ARFR3_V1_8822B(x) (((x) & BIT_MASK_ARFR3_V1_8822B) << BIT_SHIFT_ARFR3_V1_8822B)
-#define BIT_GET_ARFR3_V1_8822B(x) (((x) >> BIT_SHIFT_ARFR3_V1_8822B) & BIT_MASK_ARFR3_V1_8822B)
-
+#define BIT_ARFR3_V1_8822B(x) \
+ (((x) & BIT_MASK_ARFR3_V1_8822B) << BIT_SHIFT_ARFR3_V1_8822B)
+#define BITS_ARFR3_V1_8822B \
+ (BIT_MASK_ARFR3_V1_8822B << BIT_SHIFT_ARFR3_V1_8822B)
+#define BIT_CLEAR_ARFR3_V1_8822B(x) ((x) & (~BITS_ARFR3_V1_8822B))
+#define BIT_GET_ARFR3_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_ARFR3_V1_8822B) & BIT_MASK_ARFR3_V1_8822B)
+#define BIT_SET_ARFR3_V1_8822B(x, v) \
+ (BIT_CLEAR_ARFR3_V1_8822B(x) | BIT_ARFR3_V1_8822B(v))
/* 2 REG_ARFR4_8822B */
#define BIT_SHIFT_ARFR4_8822B 0
#define BIT_MASK_ARFR4_8822B 0xffffffffffffffffL
-#define BIT_ARFR4_8822B(x) (((x) & BIT_MASK_ARFR4_8822B) << BIT_SHIFT_ARFR4_8822B)
-#define BIT_GET_ARFR4_8822B(x) (((x) >> BIT_SHIFT_ARFR4_8822B) & BIT_MASK_ARFR4_8822B)
-
+#define BIT_ARFR4_8822B(x) \
+ (((x) & BIT_MASK_ARFR4_8822B) << BIT_SHIFT_ARFR4_8822B)
+#define BITS_ARFR4_8822B (BIT_MASK_ARFR4_8822B << BIT_SHIFT_ARFR4_8822B)
+#define BIT_CLEAR_ARFR4_8822B(x) ((x) & (~BITS_ARFR4_8822B))
+#define BIT_GET_ARFR4_8822B(x) \
+ (((x) >> BIT_SHIFT_ARFR4_8822B) & BIT_MASK_ARFR4_8822B)
+#define BIT_SET_ARFR4_8822B(x, v) \
+ (BIT_CLEAR_ARFR4_8822B(x) | BIT_ARFR4_8822B(v))
/* 2 REG_ARFR5_8822B */
#define BIT_SHIFT_ARFR5_8822B 0
#define BIT_MASK_ARFR5_8822B 0xffffffffffffffffL
-#define BIT_ARFR5_8822B(x) (((x) & BIT_MASK_ARFR5_8822B) << BIT_SHIFT_ARFR5_8822B)
-#define BIT_GET_ARFR5_8822B(x) (((x) >> BIT_SHIFT_ARFR5_8822B) & BIT_MASK_ARFR5_8822B)
-
+#define BIT_ARFR5_8822B(x) \
+ (((x) & BIT_MASK_ARFR5_8822B) << BIT_SHIFT_ARFR5_8822B)
+#define BITS_ARFR5_8822B (BIT_MASK_ARFR5_8822B << BIT_SHIFT_ARFR5_8822B)
+#define BIT_CLEAR_ARFR5_8822B(x) ((x) & (~BITS_ARFR5_8822B))
+#define BIT_GET_ARFR5_8822B(x) \
+ (((x) >> BIT_SHIFT_ARFR5_8822B) & BIT_MASK_ARFR5_8822B)
+#define BIT_SET_ARFR5_8822B(x, v) \
+ (BIT_CLEAR_ARFR5_8822B(x) | BIT_ARFR5_8822B(v))
/* 2 REG_TXRPT_START_OFFSET_8822B */
#define BIT_SHIFT_MACID_MURATE_OFFSET_8822B 24
#define BIT_MASK_MACID_MURATE_OFFSET_8822B 0xff
-#define BIT_MACID_MURATE_OFFSET_8822B(x) (((x) & BIT_MASK_MACID_MURATE_OFFSET_8822B) << BIT_SHIFT_MACID_MURATE_OFFSET_8822B)
-#define BIT_GET_MACID_MURATE_OFFSET_8822B(x) (((x) >> BIT_SHIFT_MACID_MURATE_OFFSET_8822B) & BIT_MASK_MACID_MURATE_OFFSET_8822B)
+#define BIT_MACID_MURATE_OFFSET_8822B(x) \
+ (((x) & BIT_MASK_MACID_MURATE_OFFSET_8822B) \
+ << BIT_SHIFT_MACID_MURATE_OFFSET_8822B)
+#define BITS_MACID_MURATE_OFFSET_8822B \
+ (BIT_MASK_MACID_MURATE_OFFSET_8822B \
+ << BIT_SHIFT_MACID_MURATE_OFFSET_8822B)
+#define BIT_CLEAR_MACID_MURATE_OFFSET_8822B(x) \
+ ((x) & (~BITS_MACID_MURATE_OFFSET_8822B))
+#define BIT_GET_MACID_MURATE_OFFSET_8822B(x) \
+ (((x) >> BIT_SHIFT_MACID_MURATE_OFFSET_8822B) & \
+ BIT_MASK_MACID_MURATE_OFFSET_8822B)
+#define BIT_SET_MACID_MURATE_OFFSET_8822B(x, v) \
+ (BIT_CLEAR_MACID_MURATE_OFFSET_8822B(x) | \
+ BIT_MACID_MURATE_OFFSET_8822B(v))
#define BIT_RPTFIFO_SIZE_OPT_8822B BIT(16)
#define BIT_SHIFT_MACID_CTRL_OFFSET_8822B 8
#define BIT_MASK_MACID_CTRL_OFFSET_8822B 0xff
-#define BIT_MACID_CTRL_OFFSET_8822B(x) (((x) & BIT_MASK_MACID_CTRL_OFFSET_8822B) << BIT_SHIFT_MACID_CTRL_OFFSET_8822B)
-#define BIT_GET_MACID_CTRL_OFFSET_8822B(x) (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_8822B) & BIT_MASK_MACID_CTRL_OFFSET_8822B)
-
+#define BIT_MACID_CTRL_OFFSET_8822B(x) \
+ (((x) & BIT_MASK_MACID_CTRL_OFFSET_8822B) \
+ << BIT_SHIFT_MACID_CTRL_OFFSET_8822B)
+#define BITS_MACID_CTRL_OFFSET_8822B \
+ (BIT_MASK_MACID_CTRL_OFFSET_8822B << BIT_SHIFT_MACID_CTRL_OFFSET_8822B)
+#define BIT_CLEAR_MACID_CTRL_OFFSET_8822B(x) \
+ ((x) & (~BITS_MACID_CTRL_OFFSET_8822B))
+#define BIT_GET_MACID_CTRL_OFFSET_8822B(x) \
+ (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_8822B) & \
+ BIT_MASK_MACID_CTRL_OFFSET_8822B)
+#define BIT_SET_MACID_CTRL_OFFSET_8822B(x, v) \
+ (BIT_CLEAR_MACID_CTRL_OFFSET_8822B(x) | BIT_MACID_CTRL_OFFSET_8822B(v))
#define BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822B 0
#define BIT_MASK_AMPDU_TXRPT_OFFSET_8822B 0xff
-#define BIT_AMPDU_TXRPT_OFFSET_8822B(x) (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_8822B) << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822B)
-#define BIT_GET_AMPDU_TXRPT_OFFSET_8822B(x) (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822B) & BIT_MASK_AMPDU_TXRPT_OFFSET_8822B)
-
+#define BIT_AMPDU_TXRPT_OFFSET_8822B(x) \
+ (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_8822B) \
+ << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822B)
+#define BITS_AMPDU_TXRPT_OFFSET_8822B \
+ (BIT_MASK_AMPDU_TXRPT_OFFSET_8822B \
+ << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822B)
+#define BIT_CLEAR_AMPDU_TXRPT_OFFSET_8822B(x) \
+ ((x) & (~BITS_AMPDU_TXRPT_OFFSET_8822B))
+#define BIT_GET_AMPDU_TXRPT_OFFSET_8822B(x) \
+ (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822B) & \
+ BIT_MASK_AMPDU_TXRPT_OFFSET_8822B)
+#define BIT_SET_AMPDU_TXRPT_OFFSET_8822B(x, v) \
+ (BIT_CLEAR_AMPDU_TXRPT_OFFSET_8822B(x) | \
+ BIT_AMPDU_TXRPT_OFFSET_8822B(v))
/* 2 REG_POWER_STAGE1_8822B */
#define BIT_PTA_WL_PRI_MASK_CPU_MGQ_8822B BIT(31)
@@ -5523,25 +9396,44 @@
#define BIT_SHIFT_POWER_STAGE1_8822B 0
#define BIT_MASK_POWER_STAGE1_8822B 0xffffff
-#define BIT_POWER_STAGE1_8822B(x) (((x) & BIT_MASK_POWER_STAGE1_8822B) << BIT_SHIFT_POWER_STAGE1_8822B)
-#define BIT_GET_POWER_STAGE1_8822B(x) (((x) >> BIT_SHIFT_POWER_STAGE1_8822B) & BIT_MASK_POWER_STAGE1_8822B)
-
+#define BIT_POWER_STAGE1_8822B(x) \
+ (((x) & BIT_MASK_POWER_STAGE1_8822B) << BIT_SHIFT_POWER_STAGE1_8822B)
+#define BITS_POWER_STAGE1_8822B \
+ (BIT_MASK_POWER_STAGE1_8822B << BIT_SHIFT_POWER_STAGE1_8822B)
+#define BIT_CLEAR_POWER_STAGE1_8822B(x) ((x) & (~BITS_POWER_STAGE1_8822B))
+#define BIT_GET_POWER_STAGE1_8822B(x) \
+ (((x) >> BIT_SHIFT_POWER_STAGE1_8822B) & BIT_MASK_POWER_STAGE1_8822B)
+#define BIT_SET_POWER_STAGE1_8822B(x, v) \
+ (BIT_CLEAR_POWER_STAGE1_8822B(x) | BIT_POWER_STAGE1_8822B(v))
/* 2 REG_POWER_STAGE2_8822B */
#define BIT__R_CTRL_PKT_POW_ADJ_8822B BIT(24)
#define BIT_SHIFT_POWER_STAGE2_8822B 0
#define BIT_MASK_POWER_STAGE2_8822B 0xffffff
-#define BIT_POWER_STAGE2_8822B(x) (((x) & BIT_MASK_POWER_STAGE2_8822B) << BIT_SHIFT_POWER_STAGE2_8822B)
-#define BIT_GET_POWER_STAGE2_8822B(x) (((x) >> BIT_SHIFT_POWER_STAGE2_8822B) & BIT_MASK_POWER_STAGE2_8822B)
-
+#define BIT_POWER_STAGE2_8822B(x) \
+ (((x) & BIT_MASK_POWER_STAGE2_8822B) << BIT_SHIFT_POWER_STAGE2_8822B)
+#define BITS_POWER_STAGE2_8822B \
+ (BIT_MASK_POWER_STAGE2_8822B << BIT_SHIFT_POWER_STAGE2_8822B)
+#define BIT_CLEAR_POWER_STAGE2_8822B(x) ((x) & (~BITS_POWER_STAGE2_8822B))
+#define BIT_GET_POWER_STAGE2_8822B(x) \
+ (((x) >> BIT_SHIFT_POWER_STAGE2_8822B) & BIT_MASK_POWER_STAGE2_8822B)
+#define BIT_SET_POWER_STAGE2_8822B(x, v) \
+ (BIT_CLEAR_POWER_STAGE2_8822B(x) | BIT_POWER_STAGE2_8822B(v))
/* 2 REG_SW_AMPDU_BURST_MODE_CTRL_8822B */
#define BIT_SHIFT_PAD_NUM_THRES_8822B 24
#define BIT_MASK_PAD_NUM_THRES_8822B 0x3f
-#define BIT_PAD_NUM_THRES_8822B(x) (((x) & BIT_MASK_PAD_NUM_THRES_8822B) << BIT_SHIFT_PAD_NUM_THRES_8822B)
-#define BIT_GET_PAD_NUM_THRES_8822B(x) (((x) >> BIT_SHIFT_PAD_NUM_THRES_8822B) & BIT_MASK_PAD_NUM_THRES_8822B)
+#define BIT_PAD_NUM_THRES_8822B(x) \
+ (((x) & BIT_MASK_PAD_NUM_THRES_8822B) << BIT_SHIFT_PAD_NUM_THRES_8822B)
+#define BITS_PAD_NUM_THRES_8822B \
+ (BIT_MASK_PAD_NUM_THRES_8822B << BIT_SHIFT_PAD_NUM_THRES_8822B)
+#define BIT_CLEAR_PAD_NUM_THRES_8822B(x) ((x) & (~BITS_PAD_NUM_THRES_8822B))
+#define BIT_GET_PAD_NUM_THRES_8822B(x) \
+ (((x) >> BIT_SHIFT_PAD_NUM_THRES_8822B) & BIT_MASK_PAD_NUM_THRES_8822B)
+#define BIT_SET_PAD_NUM_THRES_8822B(x, v) \
+ (BIT_CLEAR_PAD_NUM_THRES_8822B(x) | BIT_PAD_NUM_THRES_8822B(v))
#define BIT_R_DMA_THIS_QUEUE_BK_8822B BIT(23)
#define BIT_R_DMA_THIS_QUEUE_BE_8822B BIT(22)
@@ -5550,16 +9442,32 @@
#define BIT_SHIFT_R_TOTAL_LEN_TH_8822B 8
#define BIT_MASK_R_TOTAL_LEN_TH_8822B 0xfff
-#define BIT_R_TOTAL_LEN_TH_8822B(x) (((x) & BIT_MASK_R_TOTAL_LEN_TH_8822B) << BIT_SHIFT_R_TOTAL_LEN_TH_8822B)
-#define BIT_GET_R_TOTAL_LEN_TH_8822B(x) (((x) >> BIT_SHIFT_R_TOTAL_LEN_TH_8822B) & BIT_MASK_R_TOTAL_LEN_TH_8822B)
+#define BIT_R_TOTAL_LEN_TH_8822B(x) \
+ (((x) & BIT_MASK_R_TOTAL_LEN_TH_8822B) \
+ << BIT_SHIFT_R_TOTAL_LEN_TH_8822B)
+#define BITS_R_TOTAL_LEN_TH_8822B \
+ (BIT_MASK_R_TOTAL_LEN_TH_8822B << BIT_SHIFT_R_TOTAL_LEN_TH_8822B)
+#define BIT_CLEAR_R_TOTAL_LEN_TH_8822B(x) ((x) & (~BITS_R_TOTAL_LEN_TH_8822B))
+#define BIT_GET_R_TOTAL_LEN_TH_8822B(x) \
+ (((x) >> BIT_SHIFT_R_TOTAL_LEN_TH_8822B) & \
+ BIT_MASK_R_TOTAL_LEN_TH_8822B)
+#define BIT_SET_R_TOTAL_LEN_TH_8822B(x, v) \
+ (BIT_CLEAR_R_TOTAL_LEN_TH_8822B(x) | BIT_R_TOTAL_LEN_TH_8822B(v))
#define BIT_EN_NEW_EARLY_8822B BIT(7)
#define BIT_PRE_TX_CMD_8822B BIT(6)
#define BIT_SHIFT_NUM_SCL_EN_8822B 4
#define BIT_MASK_NUM_SCL_EN_8822B 0x3
-#define BIT_NUM_SCL_EN_8822B(x) (((x) & BIT_MASK_NUM_SCL_EN_8822B) << BIT_SHIFT_NUM_SCL_EN_8822B)
-#define BIT_GET_NUM_SCL_EN_8822B(x) (((x) >> BIT_SHIFT_NUM_SCL_EN_8822B) & BIT_MASK_NUM_SCL_EN_8822B)
+#define BIT_NUM_SCL_EN_8822B(x) \
+ (((x) & BIT_MASK_NUM_SCL_EN_8822B) << BIT_SHIFT_NUM_SCL_EN_8822B)
+#define BITS_NUM_SCL_EN_8822B \
+ (BIT_MASK_NUM_SCL_EN_8822B << BIT_SHIFT_NUM_SCL_EN_8822B)
+#define BIT_CLEAR_NUM_SCL_EN_8822B(x) ((x) & (~BITS_NUM_SCL_EN_8822B))
+#define BIT_GET_NUM_SCL_EN_8822B(x) \
+ (((x) >> BIT_SHIFT_NUM_SCL_EN_8822B) & BIT_MASK_NUM_SCL_EN_8822B)
+#define BIT_SET_NUM_SCL_EN_8822B(x, v) \
+ (BIT_CLEAR_NUM_SCL_EN_8822B(x) | BIT_NUM_SCL_EN_8822B(v))
#define BIT_BK_EN_8822B BIT(3)
#define BIT_BE_EN_8822B BIT(2)
@@ -5570,43 +9478,86 @@
#define BIT_SHIFT_PKT_LIFTIME_BEBK_8822B 16
#define BIT_MASK_PKT_LIFTIME_BEBK_8822B 0xffff
-#define BIT_PKT_LIFTIME_BEBK_8822B(x) (((x) & BIT_MASK_PKT_LIFTIME_BEBK_8822B) << BIT_SHIFT_PKT_LIFTIME_BEBK_8822B)
-#define BIT_GET_PKT_LIFTIME_BEBK_8822B(x) (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8822B) & BIT_MASK_PKT_LIFTIME_BEBK_8822B)
-
+#define BIT_PKT_LIFTIME_BEBK_8822B(x) \
+ (((x) & BIT_MASK_PKT_LIFTIME_BEBK_8822B) \
+ << BIT_SHIFT_PKT_LIFTIME_BEBK_8822B)
+#define BITS_PKT_LIFTIME_BEBK_8822B \
+ (BIT_MASK_PKT_LIFTIME_BEBK_8822B << BIT_SHIFT_PKT_LIFTIME_BEBK_8822B)
+#define BIT_CLEAR_PKT_LIFTIME_BEBK_8822B(x) \
+ ((x) & (~BITS_PKT_LIFTIME_BEBK_8822B))
+#define BIT_GET_PKT_LIFTIME_BEBK_8822B(x) \
+ (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8822B) & \
+ BIT_MASK_PKT_LIFTIME_BEBK_8822B)
+#define BIT_SET_PKT_LIFTIME_BEBK_8822B(x, v) \
+ (BIT_CLEAR_PKT_LIFTIME_BEBK_8822B(x) | BIT_PKT_LIFTIME_BEBK_8822B(v))
#define BIT_SHIFT_PKT_LIFTIME_VOVI_8822B 0
#define BIT_MASK_PKT_LIFTIME_VOVI_8822B 0xffff
-#define BIT_PKT_LIFTIME_VOVI_8822B(x) (((x) & BIT_MASK_PKT_LIFTIME_VOVI_8822B) << BIT_SHIFT_PKT_LIFTIME_VOVI_8822B)
-#define BIT_GET_PKT_LIFTIME_VOVI_8822B(x) (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8822B) & BIT_MASK_PKT_LIFTIME_VOVI_8822B)
-
+#define BIT_PKT_LIFTIME_VOVI_8822B(x) \
+ (((x) & BIT_MASK_PKT_LIFTIME_VOVI_8822B) \
+ << BIT_SHIFT_PKT_LIFTIME_VOVI_8822B)
+#define BITS_PKT_LIFTIME_VOVI_8822B \
+ (BIT_MASK_PKT_LIFTIME_VOVI_8822B << BIT_SHIFT_PKT_LIFTIME_VOVI_8822B)
+#define BIT_CLEAR_PKT_LIFTIME_VOVI_8822B(x) \
+ ((x) & (~BITS_PKT_LIFTIME_VOVI_8822B))
+#define BIT_GET_PKT_LIFTIME_VOVI_8822B(x) \
+ (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8822B) & \
+ BIT_MASK_PKT_LIFTIME_VOVI_8822B)
+#define BIT_SET_PKT_LIFTIME_VOVI_8822B(x, v) \
+ (BIT_CLEAR_PKT_LIFTIME_VOVI_8822B(x) | BIT_PKT_LIFTIME_VOVI_8822B(v))
/* 2 REG_STBC_SETTING_8822B */
#define BIT_SHIFT_CDEND_TXTIME_L_8822B 4
#define BIT_MASK_CDEND_TXTIME_L_8822B 0xf
-#define BIT_CDEND_TXTIME_L_8822B(x) (((x) & BIT_MASK_CDEND_TXTIME_L_8822B) << BIT_SHIFT_CDEND_TXTIME_L_8822B)
-#define BIT_GET_CDEND_TXTIME_L_8822B(x) (((x) >> BIT_SHIFT_CDEND_TXTIME_L_8822B) & BIT_MASK_CDEND_TXTIME_L_8822B)
-
+#define BIT_CDEND_TXTIME_L_8822B(x) \
+ (((x) & BIT_MASK_CDEND_TXTIME_L_8822B) \
+ << BIT_SHIFT_CDEND_TXTIME_L_8822B)
+#define BITS_CDEND_TXTIME_L_8822B \
+ (BIT_MASK_CDEND_TXTIME_L_8822B << BIT_SHIFT_CDEND_TXTIME_L_8822B)
+#define BIT_CLEAR_CDEND_TXTIME_L_8822B(x) ((x) & (~BITS_CDEND_TXTIME_L_8822B))
+#define BIT_GET_CDEND_TXTIME_L_8822B(x) \
+ (((x) >> BIT_SHIFT_CDEND_TXTIME_L_8822B) & \
+ BIT_MASK_CDEND_TXTIME_L_8822B)
+#define BIT_SET_CDEND_TXTIME_L_8822B(x, v) \
+ (BIT_CLEAR_CDEND_TXTIME_L_8822B(x) | BIT_CDEND_TXTIME_L_8822B(v))
#define BIT_SHIFT_NESS_8822B 2
#define BIT_MASK_NESS_8822B 0x3
#define BIT_NESS_8822B(x) (((x) & BIT_MASK_NESS_8822B) << BIT_SHIFT_NESS_8822B)
-#define BIT_GET_NESS_8822B(x) (((x) >> BIT_SHIFT_NESS_8822B) & BIT_MASK_NESS_8822B)
-
+#define BITS_NESS_8822B (BIT_MASK_NESS_8822B << BIT_SHIFT_NESS_8822B)
+#define BIT_CLEAR_NESS_8822B(x) ((x) & (~BITS_NESS_8822B))
+#define BIT_GET_NESS_8822B(x) \
+ (((x) >> BIT_SHIFT_NESS_8822B) & BIT_MASK_NESS_8822B)
+#define BIT_SET_NESS_8822B(x, v) (BIT_CLEAR_NESS_8822B(x) | BIT_NESS_8822B(v))
#define BIT_SHIFT_STBC_CFEND_8822B 0
#define BIT_MASK_STBC_CFEND_8822B 0x3
-#define BIT_STBC_CFEND_8822B(x) (((x) & BIT_MASK_STBC_CFEND_8822B) << BIT_SHIFT_STBC_CFEND_8822B)
-#define BIT_GET_STBC_CFEND_8822B(x) (((x) >> BIT_SHIFT_STBC_CFEND_8822B) & BIT_MASK_STBC_CFEND_8822B)
-
+#define BIT_STBC_CFEND_8822B(x) \
+ (((x) & BIT_MASK_STBC_CFEND_8822B) << BIT_SHIFT_STBC_CFEND_8822B)
+#define BITS_STBC_CFEND_8822B \
+ (BIT_MASK_STBC_CFEND_8822B << BIT_SHIFT_STBC_CFEND_8822B)
+#define BIT_CLEAR_STBC_CFEND_8822B(x) ((x) & (~BITS_STBC_CFEND_8822B))
+#define BIT_GET_STBC_CFEND_8822B(x) \
+ (((x) >> BIT_SHIFT_STBC_CFEND_8822B) & BIT_MASK_STBC_CFEND_8822B)
+#define BIT_SET_STBC_CFEND_8822B(x, v) \
+ (BIT_CLEAR_STBC_CFEND_8822B(x) | BIT_STBC_CFEND_8822B(v))
/* 2 REG_STBC_SETTING2_8822B */
#define BIT_SHIFT_CDEND_TXTIME_H_8822B 0
#define BIT_MASK_CDEND_TXTIME_H_8822B 0x1f
-#define BIT_CDEND_TXTIME_H_8822B(x) (((x) & BIT_MASK_CDEND_TXTIME_H_8822B) << BIT_SHIFT_CDEND_TXTIME_H_8822B)
-#define BIT_GET_CDEND_TXTIME_H_8822B(x) (((x) >> BIT_SHIFT_CDEND_TXTIME_H_8822B) & BIT_MASK_CDEND_TXTIME_H_8822B)
-
+#define BIT_CDEND_TXTIME_H_8822B(x) \
+ (((x) & BIT_MASK_CDEND_TXTIME_H_8822B) \
+ << BIT_SHIFT_CDEND_TXTIME_H_8822B)
+#define BITS_CDEND_TXTIME_H_8822B \
+ (BIT_MASK_CDEND_TXTIME_H_8822B << BIT_SHIFT_CDEND_TXTIME_H_8822B)
+#define BIT_CLEAR_CDEND_TXTIME_H_8822B(x) ((x) & (~BITS_CDEND_TXTIME_H_8822B))
+#define BIT_GET_CDEND_TXTIME_H_8822B(x) \
+ (((x) >> BIT_SHIFT_CDEND_TXTIME_H_8822B) & \
+ BIT_MASK_CDEND_TXTIME_H_8822B)
+#define BIT_SET_CDEND_TXTIME_H_8822B(x, v) \
+ (BIT_CLEAR_CDEND_TXTIME_H_8822B(x) | BIT_CDEND_TXTIME_H_8822B(v))
/* 2 REG_QUEUE_CTRL_8822B */
#define BIT_PTA_EDCCA_EN_8822B BIT(5)
@@ -5623,111 +9574,229 @@
#define BIT_SHIFT_RTS_MAX_AGG_NUM_8822B 24
#define BIT_MASK_RTS_MAX_AGG_NUM_8822B 0x3f
-#define BIT_RTS_MAX_AGG_NUM_8822B(x) (((x) & BIT_MASK_RTS_MAX_AGG_NUM_8822B) << BIT_SHIFT_RTS_MAX_AGG_NUM_8822B)
-#define BIT_GET_RTS_MAX_AGG_NUM_8822B(x) (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8822B) & BIT_MASK_RTS_MAX_AGG_NUM_8822B)
-
+#define BIT_RTS_MAX_AGG_NUM_8822B(x) \
+ (((x) & BIT_MASK_RTS_MAX_AGG_NUM_8822B) \
+ << BIT_SHIFT_RTS_MAX_AGG_NUM_8822B)
+#define BITS_RTS_MAX_AGG_NUM_8822B \
+ (BIT_MASK_RTS_MAX_AGG_NUM_8822B << BIT_SHIFT_RTS_MAX_AGG_NUM_8822B)
+#define BIT_CLEAR_RTS_MAX_AGG_NUM_8822B(x) ((x) & (~BITS_RTS_MAX_AGG_NUM_8822B))
+#define BIT_GET_RTS_MAX_AGG_NUM_8822B(x) \
+ (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8822B) & \
+ BIT_MASK_RTS_MAX_AGG_NUM_8822B)
+#define BIT_SET_RTS_MAX_AGG_NUM_8822B(x, v) \
+ (BIT_CLEAR_RTS_MAX_AGG_NUM_8822B(x) | BIT_RTS_MAX_AGG_NUM_8822B(v))
#define BIT_SHIFT_MAX_AGG_NUM_8822B 16
#define BIT_MASK_MAX_AGG_NUM_8822B 0x3f
-#define BIT_MAX_AGG_NUM_8822B(x) (((x) & BIT_MASK_MAX_AGG_NUM_8822B) << BIT_SHIFT_MAX_AGG_NUM_8822B)
-#define BIT_GET_MAX_AGG_NUM_8822B(x) (((x) >> BIT_SHIFT_MAX_AGG_NUM_8822B) & BIT_MASK_MAX_AGG_NUM_8822B)
-
+#define BIT_MAX_AGG_NUM_8822B(x) \
+ (((x) & BIT_MASK_MAX_AGG_NUM_8822B) << BIT_SHIFT_MAX_AGG_NUM_8822B)
+#define BITS_MAX_AGG_NUM_8822B \
+ (BIT_MASK_MAX_AGG_NUM_8822B << BIT_SHIFT_MAX_AGG_NUM_8822B)
+#define BIT_CLEAR_MAX_AGG_NUM_8822B(x) ((x) & (~BITS_MAX_AGG_NUM_8822B))
+#define BIT_GET_MAX_AGG_NUM_8822B(x) \
+ (((x) >> BIT_SHIFT_MAX_AGG_NUM_8822B) & BIT_MASK_MAX_AGG_NUM_8822B)
+#define BIT_SET_MAX_AGG_NUM_8822B(x, v) \
+ (BIT_CLEAR_MAX_AGG_NUM_8822B(x) | BIT_MAX_AGG_NUM_8822B(v))
#define BIT_SHIFT_RTS_TXTIME_TH_8822B 8
#define BIT_MASK_RTS_TXTIME_TH_8822B 0xff
-#define BIT_RTS_TXTIME_TH_8822B(x) (((x) & BIT_MASK_RTS_TXTIME_TH_8822B) << BIT_SHIFT_RTS_TXTIME_TH_8822B)
-#define BIT_GET_RTS_TXTIME_TH_8822B(x) (((x) >> BIT_SHIFT_RTS_TXTIME_TH_8822B) & BIT_MASK_RTS_TXTIME_TH_8822B)
-
+#define BIT_RTS_TXTIME_TH_8822B(x) \
+ (((x) & BIT_MASK_RTS_TXTIME_TH_8822B) << BIT_SHIFT_RTS_TXTIME_TH_8822B)
+#define BITS_RTS_TXTIME_TH_8822B \
+ (BIT_MASK_RTS_TXTIME_TH_8822B << BIT_SHIFT_RTS_TXTIME_TH_8822B)
+#define BIT_CLEAR_RTS_TXTIME_TH_8822B(x) ((x) & (~BITS_RTS_TXTIME_TH_8822B))
+#define BIT_GET_RTS_TXTIME_TH_8822B(x) \
+ (((x) >> BIT_SHIFT_RTS_TXTIME_TH_8822B) & BIT_MASK_RTS_TXTIME_TH_8822B)
+#define BIT_SET_RTS_TXTIME_TH_8822B(x, v) \
+ (BIT_CLEAR_RTS_TXTIME_TH_8822B(x) | BIT_RTS_TXTIME_TH_8822B(v))
#define BIT_SHIFT_RTS_LEN_TH_8822B 0
#define BIT_MASK_RTS_LEN_TH_8822B 0xff
-#define BIT_RTS_LEN_TH_8822B(x) (((x) & BIT_MASK_RTS_LEN_TH_8822B) << BIT_SHIFT_RTS_LEN_TH_8822B)
-#define BIT_GET_RTS_LEN_TH_8822B(x) (((x) >> BIT_SHIFT_RTS_LEN_TH_8822B) & BIT_MASK_RTS_LEN_TH_8822B)
-
+#define BIT_RTS_LEN_TH_8822B(x) \
+ (((x) & BIT_MASK_RTS_LEN_TH_8822B) << BIT_SHIFT_RTS_LEN_TH_8822B)
+#define BITS_RTS_LEN_TH_8822B \
+ (BIT_MASK_RTS_LEN_TH_8822B << BIT_SHIFT_RTS_LEN_TH_8822B)
+#define BIT_CLEAR_RTS_LEN_TH_8822B(x) ((x) & (~BITS_RTS_LEN_TH_8822B))
+#define BIT_GET_RTS_LEN_TH_8822B(x) \
+ (((x) >> BIT_SHIFT_RTS_LEN_TH_8822B) & BIT_MASK_RTS_LEN_TH_8822B)
+#define BIT_SET_RTS_LEN_TH_8822B(x, v) \
+ (BIT_CLEAR_RTS_LEN_TH_8822B(x) | BIT_RTS_LEN_TH_8822B(v))
/* 2 REG_BAR_MODE_CTRL_8822B */
#define BIT_SHIFT_BAR_RTY_LMT_8822B 16
#define BIT_MASK_BAR_RTY_LMT_8822B 0x3
-#define BIT_BAR_RTY_LMT_8822B(x) (((x) & BIT_MASK_BAR_RTY_LMT_8822B) << BIT_SHIFT_BAR_RTY_LMT_8822B)
-#define BIT_GET_BAR_RTY_LMT_8822B(x) (((x) >> BIT_SHIFT_BAR_RTY_LMT_8822B) & BIT_MASK_BAR_RTY_LMT_8822B)
-
+#define BIT_BAR_RTY_LMT_8822B(x) \
+ (((x) & BIT_MASK_BAR_RTY_LMT_8822B) << BIT_SHIFT_BAR_RTY_LMT_8822B)
+#define BITS_BAR_RTY_LMT_8822B \
+ (BIT_MASK_BAR_RTY_LMT_8822B << BIT_SHIFT_BAR_RTY_LMT_8822B)
+#define BIT_CLEAR_BAR_RTY_LMT_8822B(x) ((x) & (~BITS_BAR_RTY_LMT_8822B))
+#define BIT_GET_BAR_RTY_LMT_8822B(x) \
+ (((x) >> BIT_SHIFT_BAR_RTY_LMT_8822B) & BIT_MASK_BAR_RTY_LMT_8822B)
+#define BIT_SET_BAR_RTY_LMT_8822B(x, v) \
+ (BIT_CLEAR_BAR_RTY_LMT_8822B(x) | BIT_BAR_RTY_LMT_8822B(v))
#define BIT_SHIFT_BAR_PKT_TXTIME_TH_8822B 8
#define BIT_MASK_BAR_PKT_TXTIME_TH_8822B 0xff
-#define BIT_BAR_PKT_TXTIME_TH_8822B(x) (((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8822B) << BIT_SHIFT_BAR_PKT_TXTIME_TH_8822B)
-#define BIT_GET_BAR_PKT_TXTIME_TH_8822B(x) (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8822B) & BIT_MASK_BAR_PKT_TXTIME_TH_8822B)
+#define BIT_BAR_PKT_TXTIME_TH_8822B(x) \
+ (((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8822B) \
+ << BIT_SHIFT_BAR_PKT_TXTIME_TH_8822B)
+#define BITS_BAR_PKT_TXTIME_TH_8822B \
+ (BIT_MASK_BAR_PKT_TXTIME_TH_8822B << BIT_SHIFT_BAR_PKT_TXTIME_TH_8822B)
+#define BIT_CLEAR_BAR_PKT_TXTIME_TH_8822B(x) \
+ ((x) & (~BITS_BAR_PKT_TXTIME_TH_8822B))
+#define BIT_GET_BAR_PKT_TXTIME_TH_8822B(x) \
+ (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8822B) & \
+ BIT_MASK_BAR_PKT_TXTIME_TH_8822B)
+#define BIT_SET_BAR_PKT_TXTIME_TH_8822B(x, v) \
+ (BIT_CLEAR_BAR_PKT_TXTIME_TH_8822B(x) | BIT_BAR_PKT_TXTIME_TH_8822B(v))
#define BIT_BAR_EN_V1_8822B BIT(6)
#define BIT_SHIFT_BAR_PKTNUM_TH_V1_8822B 0
#define BIT_MASK_BAR_PKTNUM_TH_V1_8822B 0x3f
-#define BIT_BAR_PKTNUM_TH_V1_8822B(x) (((x) & BIT_MASK_BAR_PKTNUM_TH_V1_8822B) << BIT_SHIFT_BAR_PKTNUM_TH_V1_8822B)
-#define BIT_GET_BAR_PKTNUM_TH_V1_8822B(x) (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8822B) & BIT_MASK_BAR_PKTNUM_TH_V1_8822B)
-
+#define BIT_BAR_PKTNUM_TH_V1_8822B(x) \
+ (((x) & BIT_MASK_BAR_PKTNUM_TH_V1_8822B) \
+ << BIT_SHIFT_BAR_PKTNUM_TH_V1_8822B)
+#define BITS_BAR_PKTNUM_TH_V1_8822B \
+ (BIT_MASK_BAR_PKTNUM_TH_V1_8822B << BIT_SHIFT_BAR_PKTNUM_TH_V1_8822B)
+#define BIT_CLEAR_BAR_PKTNUM_TH_V1_8822B(x) \
+ ((x) & (~BITS_BAR_PKTNUM_TH_V1_8822B))
+#define BIT_GET_BAR_PKTNUM_TH_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8822B) & \
+ BIT_MASK_BAR_PKTNUM_TH_V1_8822B)
+#define BIT_SET_BAR_PKTNUM_TH_V1_8822B(x, v) \
+ (BIT_CLEAR_BAR_PKTNUM_TH_V1_8822B(x) | BIT_BAR_PKTNUM_TH_V1_8822B(v))
/* 2 REG_RA_TRY_RATE_AGG_LMT_8822B */
#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822B 0
#define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822B 0x3f
-#define BIT_RA_TRY_RATE_AGG_LMT_V1_8822B(x) (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822B) << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822B)
-#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8822B(x) (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822B) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822B)
-
+#define BIT_RA_TRY_RATE_AGG_LMT_V1_8822B(x) \
+ (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822B) \
+ << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822B)
+#define BITS_RA_TRY_RATE_AGG_LMT_V1_8822B \
+ (BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822B \
+ << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822B)
+#define BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8822B(x) \
+ ((x) & (~BITS_RA_TRY_RATE_AGG_LMT_V1_8822B))
+#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822B) & \
+ BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822B)
+#define BIT_SET_RA_TRY_RATE_AGG_LMT_V1_8822B(x, v) \
+ (BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8822B(x) | \
+ BIT_RA_TRY_RATE_AGG_LMT_V1_8822B(v))
/* 2 REG_MACID_SLEEP2_8822B */
#define BIT_SHIFT_MACID95_64PKTSLEEP_8822B 0
#define BIT_MASK_MACID95_64PKTSLEEP_8822B 0xffffffffL
-#define BIT_MACID95_64PKTSLEEP_8822B(x) (((x) & BIT_MASK_MACID95_64PKTSLEEP_8822B) << BIT_SHIFT_MACID95_64PKTSLEEP_8822B)
-#define BIT_GET_MACID95_64PKTSLEEP_8822B(x) (((x) >> BIT_SHIFT_MACID95_64PKTSLEEP_8822B) & BIT_MASK_MACID95_64PKTSLEEP_8822B)
-
+#define BIT_MACID95_64PKTSLEEP_8822B(x) \
+ (((x) & BIT_MASK_MACID95_64PKTSLEEP_8822B) \
+ << BIT_SHIFT_MACID95_64PKTSLEEP_8822B)
+#define BITS_MACID95_64PKTSLEEP_8822B \
+ (BIT_MASK_MACID95_64PKTSLEEP_8822B \
+ << BIT_SHIFT_MACID95_64PKTSLEEP_8822B)
+#define BIT_CLEAR_MACID95_64PKTSLEEP_8822B(x) \
+ ((x) & (~BITS_MACID95_64PKTSLEEP_8822B))
+#define BIT_GET_MACID95_64PKTSLEEP_8822B(x) \
+ (((x) >> BIT_SHIFT_MACID95_64PKTSLEEP_8822B) & \
+ BIT_MASK_MACID95_64PKTSLEEP_8822B)
+#define BIT_SET_MACID95_64PKTSLEEP_8822B(x, v) \
+ (BIT_CLEAR_MACID95_64PKTSLEEP_8822B(x) | \
+ BIT_MACID95_64PKTSLEEP_8822B(v))
/* 2 REG_MACID_SLEEP_8822B */
#define BIT_SHIFT_MACID31_0_PKTSLEEP_8822B 0
#define BIT_MASK_MACID31_0_PKTSLEEP_8822B 0xffffffffL
-#define BIT_MACID31_0_PKTSLEEP_8822B(x) (((x) & BIT_MASK_MACID31_0_PKTSLEEP_8822B) << BIT_SHIFT_MACID31_0_PKTSLEEP_8822B)
-#define BIT_GET_MACID31_0_PKTSLEEP_8822B(x) (((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP_8822B) & BIT_MASK_MACID31_0_PKTSLEEP_8822B)
-
+#define BIT_MACID31_0_PKTSLEEP_8822B(x) \
+ (((x) & BIT_MASK_MACID31_0_PKTSLEEP_8822B) \
+ << BIT_SHIFT_MACID31_0_PKTSLEEP_8822B)
+#define BITS_MACID31_0_PKTSLEEP_8822B \
+ (BIT_MASK_MACID31_0_PKTSLEEP_8822B \
+ << BIT_SHIFT_MACID31_0_PKTSLEEP_8822B)
+#define BIT_CLEAR_MACID31_0_PKTSLEEP_8822B(x) \
+ ((x) & (~BITS_MACID31_0_PKTSLEEP_8822B))
+#define BIT_GET_MACID31_0_PKTSLEEP_8822B(x) \
+ (((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP_8822B) & \
+ BIT_MASK_MACID31_0_PKTSLEEP_8822B)
+#define BIT_SET_MACID31_0_PKTSLEEP_8822B(x, v) \
+ (BIT_CLEAR_MACID31_0_PKTSLEEP_8822B(x) | \
+ BIT_MACID31_0_PKTSLEEP_8822B(v))
/* 2 REG_HW_SEQ0_8822B */
#define BIT_SHIFT_HW_SSN_SEQ0_8822B 0
#define BIT_MASK_HW_SSN_SEQ0_8822B 0xfff
-#define BIT_HW_SSN_SEQ0_8822B(x) (((x) & BIT_MASK_HW_SSN_SEQ0_8822B) << BIT_SHIFT_HW_SSN_SEQ0_8822B)
-#define BIT_GET_HW_SSN_SEQ0_8822B(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ0_8822B) & BIT_MASK_HW_SSN_SEQ0_8822B)
-
+#define BIT_HW_SSN_SEQ0_8822B(x) \
+ (((x) & BIT_MASK_HW_SSN_SEQ0_8822B) << BIT_SHIFT_HW_SSN_SEQ0_8822B)
+#define BITS_HW_SSN_SEQ0_8822B \
+ (BIT_MASK_HW_SSN_SEQ0_8822B << BIT_SHIFT_HW_SSN_SEQ0_8822B)
+#define BIT_CLEAR_HW_SSN_SEQ0_8822B(x) ((x) & (~BITS_HW_SSN_SEQ0_8822B))
+#define BIT_GET_HW_SSN_SEQ0_8822B(x) \
+ (((x) >> BIT_SHIFT_HW_SSN_SEQ0_8822B) & BIT_MASK_HW_SSN_SEQ0_8822B)
+#define BIT_SET_HW_SSN_SEQ0_8822B(x, v) \
+ (BIT_CLEAR_HW_SSN_SEQ0_8822B(x) | BIT_HW_SSN_SEQ0_8822B(v))
/* 2 REG_HW_SEQ1_8822B */
#define BIT_SHIFT_HW_SSN_SEQ1_8822B 0
#define BIT_MASK_HW_SSN_SEQ1_8822B 0xfff
-#define BIT_HW_SSN_SEQ1_8822B(x) (((x) & BIT_MASK_HW_SSN_SEQ1_8822B) << BIT_SHIFT_HW_SSN_SEQ1_8822B)
-#define BIT_GET_HW_SSN_SEQ1_8822B(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ1_8822B) & BIT_MASK_HW_SSN_SEQ1_8822B)
-
+#define BIT_HW_SSN_SEQ1_8822B(x) \
+ (((x) & BIT_MASK_HW_SSN_SEQ1_8822B) << BIT_SHIFT_HW_SSN_SEQ1_8822B)
+#define BITS_HW_SSN_SEQ1_8822B \
+ (BIT_MASK_HW_SSN_SEQ1_8822B << BIT_SHIFT_HW_SSN_SEQ1_8822B)
+#define BIT_CLEAR_HW_SSN_SEQ1_8822B(x) ((x) & (~BITS_HW_SSN_SEQ1_8822B))
+#define BIT_GET_HW_SSN_SEQ1_8822B(x) \
+ (((x) >> BIT_SHIFT_HW_SSN_SEQ1_8822B) & BIT_MASK_HW_SSN_SEQ1_8822B)
+#define BIT_SET_HW_SSN_SEQ1_8822B(x, v) \
+ (BIT_CLEAR_HW_SSN_SEQ1_8822B(x) | BIT_HW_SSN_SEQ1_8822B(v))
/* 2 REG_HW_SEQ2_8822B */
#define BIT_SHIFT_HW_SSN_SEQ2_8822B 0
#define BIT_MASK_HW_SSN_SEQ2_8822B 0xfff
-#define BIT_HW_SSN_SEQ2_8822B(x) (((x) & BIT_MASK_HW_SSN_SEQ2_8822B) << BIT_SHIFT_HW_SSN_SEQ2_8822B)
-#define BIT_GET_HW_SSN_SEQ2_8822B(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ2_8822B) & BIT_MASK_HW_SSN_SEQ2_8822B)
-
+#define BIT_HW_SSN_SEQ2_8822B(x) \
+ (((x) & BIT_MASK_HW_SSN_SEQ2_8822B) << BIT_SHIFT_HW_SSN_SEQ2_8822B)
+#define BITS_HW_SSN_SEQ2_8822B \
+ (BIT_MASK_HW_SSN_SEQ2_8822B << BIT_SHIFT_HW_SSN_SEQ2_8822B)
+#define BIT_CLEAR_HW_SSN_SEQ2_8822B(x) ((x) & (~BITS_HW_SSN_SEQ2_8822B))
+#define BIT_GET_HW_SSN_SEQ2_8822B(x) \
+ (((x) >> BIT_SHIFT_HW_SSN_SEQ2_8822B) & BIT_MASK_HW_SSN_SEQ2_8822B)
+#define BIT_SET_HW_SSN_SEQ2_8822B(x, v) \
+ (BIT_CLEAR_HW_SSN_SEQ2_8822B(x) | BIT_HW_SSN_SEQ2_8822B(v))
/* 2 REG_HW_SEQ3_8822B */
#define BIT_SHIFT_HW_SSN_SEQ3_8822B 0
#define BIT_MASK_HW_SSN_SEQ3_8822B 0xfff
-#define BIT_HW_SSN_SEQ3_8822B(x) (((x) & BIT_MASK_HW_SSN_SEQ3_8822B) << BIT_SHIFT_HW_SSN_SEQ3_8822B)
-#define BIT_GET_HW_SSN_SEQ3_8822B(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ3_8822B) & BIT_MASK_HW_SSN_SEQ3_8822B)
-
+#define BIT_HW_SSN_SEQ3_8822B(x) \
+ (((x) & BIT_MASK_HW_SSN_SEQ3_8822B) << BIT_SHIFT_HW_SSN_SEQ3_8822B)
+#define BITS_HW_SSN_SEQ3_8822B \
+ (BIT_MASK_HW_SSN_SEQ3_8822B << BIT_SHIFT_HW_SSN_SEQ3_8822B)
+#define BIT_CLEAR_HW_SSN_SEQ3_8822B(x) ((x) & (~BITS_HW_SSN_SEQ3_8822B))
+#define BIT_GET_HW_SSN_SEQ3_8822B(x) \
+ (((x) >> BIT_SHIFT_HW_SSN_SEQ3_8822B) & BIT_MASK_HW_SSN_SEQ3_8822B)
+#define BIT_SET_HW_SSN_SEQ3_8822B(x, v) \
+ (BIT_CLEAR_HW_SSN_SEQ3_8822B(x) | BIT_HW_SSN_SEQ3_8822B(v))
/* 2 REG_NULL_PKT_STATUS_V1_8822B */
#define BIT_SHIFT_PTCL_TOTAL_PG_V2_8822B 2
#define BIT_MASK_PTCL_TOTAL_PG_V2_8822B 0x3fff
-#define BIT_PTCL_TOTAL_PG_V2_8822B(x) (((x) & BIT_MASK_PTCL_TOTAL_PG_V2_8822B) << BIT_SHIFT_PTCL_TOTAL_PG_V2_8822B)
-#define BIT_GET_PTCL_TOTAL_PG_V2_8822B(x) (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2_8822B) & BIT_MASK_PTCL_TOTAL_PG_V2_8822B)
+#define BIT_PTCL_TOTAL_PG_V2_8822B(x) \
+ (((x) & BIT_MASK_PTCL_TOTAL_PG_V2_8822B) \
+ << BIT_SHIFT_PTCL_TOTAL_PG_V2_8822B)
+#define BITS_PTCL_TOTAL_PG_V2_8822B \
+ (BIT_MASK_PTCL_TOTAL_PG_V2_8822B << BIT_SHIFT_PTCL_TOTAL_PG_V2_8822B)
+#define BIT_CLEAR_PTCL_TOTAL_PG_V2_8822B(x) \
+ ((x) & (~BITS_PTCL_TOTAL_PG_V2_8822B))
+#define BIT_GET_PTCL_TOTAL_PG_V2_8822B(x) \
+ (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2_8822B) & \
+ BIT_MASK_PTCL_TOTAL_PG_V2_8822B)
+#define BIT_SET_PTCL_TOTAL_PG_V2_8822B(x, v) \
+ (BIT_CLEAR_PTCL_TOTAL_PG_V2_8822B(x) | BIT_PTCL_TOTAL_PG_V2_8822B(v))
#define BIT_TX_NULL_1_8822B BIT(1)
#define BIT_TX_NULL_0_8822B BIT(0)
@@ -5760,9 +9829,20 @@
#define BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822B 0
#define BIT_MASK_BT_POLLUTE_PKT_CNT_8822B 0xffff
-#define BIT_BT_POLLUTE_PKT_CNT_8822B(x) (((x) & BIT_MASK_BT_POLLUTE_PKT_CNT_8822B) << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822B)
-#define BIT_GET_BT_POLLUTE_PKT_CNT_8822B(x) (((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822B) & BIT_MASK_BT_POLLUTE_PKT_CNT_8822B)
-
+#define BIT_BT_POLLUTE_PKT_CNT_8822B(x) \
+ (((x) & BIT_MASK_BT_POLLUTE_PKT_CNT_8822B) \
+ << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822B)
+#define BITS_BT_POLLUTE_PKT_CNT_8822B \
+ (BIT_MASK_BT_POLLUTE_PKT_CNT_8822B \
+ << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822B)
+#define BIT_CLEAR_BT_POLLUTE_PKT_CNT_8822B(x) \
+ ((x) & (~BITS_BT_POLLUTE_PKT_CNT_8822B))
+#define BIT_GET_BT_POLLUTE_PKT_CNT_8822B(x) \
+ (((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822B) & \
+ BIT_MASK_BT_POLLUTE_PKT_CNT_8822B)
+#define BIT_SET_BT_POLLUTE_PKT_CNT_8822B(x, v) \
+ (BIT_CLEAR_BT_POLLUTE_PKT_CNT_8822B(x) | \
+ BIT_BT_POLLUTE_PKT_CNT_8822B(v))
/* 2 REG_NOT_VALID_8822B */
@@ -5770,9 +9850,15 @@
#define BIT_SHIFT_PTCL_DBG_8822B 0
#define BIT_MASK_PTCL_DBG_8822B 0xffffffffL
-#define BIT_PTCL_DBG_8822B(x) (((x) & BIT_MASK_PTCL_DBG_8822B) << BIT_SHIFT_PTCL_DBG_8822B)
-#define BIT_GET_PTCL_DBG_8822B(x) (((x) >> BIT_SHIFT_PTCL_DBG_8822B) & BIT_MASK_PTCL_DBG_8822B)
-
+#define BIT_PTCL_DBG_8822B(x) \
+ (((x) & BIT_MASK_PTCL_DBG_8822B) << BIT_SHIFT_PTCL_DBG_8822B)
+#define BITS_PTCL_DBG_8822B \
+ (BIT_MASK_PTCL_DBG_8822B << BIT_SHIFT_PTCL_DBG_8822B)
+#define BIT_CLEAR_PTCL_DBG_8822B(x) ((x) & (~BITS_PTCL_DBG_8822B))
+#define BIT_GET_PTCL_DBG_8822B(x) \
+ (((x) >> BIT_SHIFT_PTCL_DBG_8822B) & BIT_MASK_PTCL_DBG_8822B)
+#define BIT_SET_PTCL_DBG_8822B(x, v) \
+ (BIT_CLEAR_PTCL_DBG_8822B(x) | BIT_PTCL_DBG_8822B(v))
/* 2 REG_NOT_VALID_8822B */
@@ -5780,16 +9866,28 @@
#define BIT_SHIFT_TRI_HEAD_ADDR_8822B 16
#define BIT_MASK_TRI_HEAD_ADDR_8822B 0xfff
-#define BIT_TRI_HEAD_ADDR_8822B(x) (((x) & BIT_MASK_TRI_HEAD_ADDR_8822B) << BIT_SHIFT_TRI_HEAD_ADDR_8822B)
-#define BIT_GET_TRI_HEAD_ADDR_8822B(x) (((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8822B) & BIT_MASK_TRI_HEAD_ADDR_8822B)
+#define BIT_TRI_HEAD_ADDR_8822B(x) \
+ (((x) & BIT_MASK_TRI_HEAD_ADDR_8822B) << BIT_SHIFT_TRI_HEAD_ADDR_8822B)
+#define BITS_TRI_HEAD_ADDR_8822B \
+ (BIT_MASK_TRI_HEAD_ADDR_8822B << BIT_SHIFT_TRI_HEAD_ADDR_8822B)
+#define BIT_CLEAR_TRI_HEAD_ADDR_8822B(x) ((x) & (~BITS_TRI_HEAD_ADDR_8822B))
+#define BIT_GET_TRI_HEAD_ADDR_8822B(x) \
+ (((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8822B) & BIT_MASK_TRI_HEAD_ADDR_8822B)
+#define BIT_SET_TRI_HEAD_ADDR_8822B(x, v) \
+ (BIT_CLEAR_TRI_HEAD_ADDR_8822B(x) | BIT_TRI_HEAD_ADDR_8822B(v))
#define BIT_DROP_TH_EN_8822B BIT(8)
#define BIT_SHIFT_DROP_TH_8822B 0
#define BIT_MASK_DROP_TH_8822B 0xff
-#define BIT_DROP_TH_8822B(x) (((x) & BIT_MASK_DROP_TH_8822B) << BIT_SHIFT_DROP_TH_8822B)
-#define BIT_GET_DROP_TH_8822B(x) (((x) >> BIT_SHIFT_DROP_TH_8822B) & BIT_MASK_DROP_TH_8822B)
-
+#define BIT_DROP_TH_8822B(x) \
+ (((x) & BIT_MASK_DROP_TH_8822B) << BIT_SHIFT_DROP_TH_8822B)
+#define BITS_DROP_TH_8822B (BIT_MASK_DROP_TH_8822B << BIT_SHIFT_DROP_TH_8822B)
+#define BIT_CLEAR_DROP_TH_8822B(x) ((x) & (~BITS_DROP_TH_8822B))
+#define BIT_GET_DROP_TH_8822B(x) \
+ (((x) >> BIT_SHIFT_DROP_TH_8822B) & BIT_MASK_DROP_TH_8822B)
+#define BIT_SET_DROP_TH_8822B(x, v) \
+ (BIT_CLEAR_DROP_TH_8822B(x) | BIT_DROP_TH_8822B(v))
/* 2 REG_NOT_VALID_8822B */
@@ -5809,154 +9907,287 @@
#define BIT_SHIFT_GTAB_ID_8822B 28
#define BIT_MASK_GTAB_ID_8822B 0x7
-#define BIT_GTAB_ID_8822B(x) (((x) & BIT_MASK_GTAB_ID_8822B) << BIT_SHIFT_GTAB_ID_8822B)
-#define BIT_GET_GTAB_ID_8822B(x) (((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B)
-
+#define BIT_GTAB_ID_8822B(x) \
+ (((x) & BIT_MASK_GTAB_ID_8822B) << BIT_SHIFT_GTAB_ID_8822B)
+#define BITS_GTAB_ID_8822B (BIT_MASK_GTAB_ID_8822B << BIT_SHIFT_GTAB_ID_8822B)
+#define BIT_CLEAR_GTAB_ID_8822B(x) ((x) & (~BITS_GTAB_ID_8822B))
+#define BIT_GET_GTAB_ID_8822B(x) \
+ (((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B)
+#define BIT_SET_GTAB_ID_8822B(x, v) \
+ (BIT_CLEAR_GTAB_ID_8822B(x) | BIT_GTAB_ID_8822B(v))
#define BIT_SHIFT_AC1_PKT_INFO_8822B 16
#define BIT_MASK_AC1_PKT_INFO_8822B 0xfff
-#define BIT_AC1_PKT_INFO_8822B(x) (((x) & BIT_MASK_AC1_PKT_INFO_8822B) << BIT_SHIFT_AC1_PKT_INFO_8822B)
-#define BIT_GET_AC1_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_AC1_PKT_INFO_8822B) & BIT_MASK_AC1_PKT_INFO_8822B)
+#define BIT_AC1_PKT_INFO_8822B(x) \
+ (((x) & BIT_MASK_AC1_PKT_INFO_8822B) << BIT_SHIFT_AC1_PKT_INFO_8822B)
+#define BITS_AC1_PKT_INFO_8822B \
+ (BIT_MASK_AC1_PKT_INFO_8822B << BIT_SHIFT_AC1_PKT_INFO_8822B)
+#define BIT_CLEAR_AC1_PKT_INFO_8822B(x) ((x) & (~BITS_AC1_PKT_INFO_8822B))
+#define BIT_GET_AC1_PKT_INFO_8822B(x) \
+ (((x) >> BIT_SHIFT_AC1_PKT_INFO_8822B) & BIT_MASK_AC1_PKT_INFO_8822B)
+#define BIT_SET_AC1_PKT_INFO_8822B(x, v) \
+ (BIT_CLEAR_AC1_PKT_INFO_8822B(x) | BIT_AC1_PKT_INFO_8822B(v))
#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822B BIT(15)
#define BIT_SHIFT_GTAB_ID_V1_8822B 12
#define BIT_MASK_GTAB_ID_V1_8822B 0x7
-#define BIT_GTAB_ID_V1_8822B(x) (((x) & BIT_MASK_GTAB_ID_V1_8822B) << BIT_SHIFT_GTAB_ID_V1_8822B)
-#define BIT_GET_GTAB_ID_V1_8822B(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B)
-
+#define BIT_GTAB_ID_V1_8822B(x) \
+ (((x) & BIT_MASK_GTAB_ID_V1_8822B) << BIT_SHIFT_GTAB_ID_V1_8822B)
+#define BITS_GTAB_ID_V1_8822B \
+ (BIT_MASK_GTAB_ID_V1_8822B << BIT_SHIFT_GTAB_ID_V1_8822B)
+#define BIT_CLEAR_GTAB_ID_V1_8822B(x) ((x) & (~BITS_GTAB_ID_V1_8822B))
+#define BIT_GET_GTAB_ID_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B)
+#define BIT_SET_GTAB_ID_V1_8822B(x, v) \
+ (BIT_CLEAR_GTAB_ID_V1_8822B(x) | BIT_GTAB_ID_V1_8822B(v))
#define BIT_SHIFT_AC0_PKT_INFO_8822B 0
#define BIT_MASK_AC0_PKT_INFO_8822B 0xfff
-#define BIT_AC0_PKT_INFO_8822B(x) (((x) & BIT_MASK_AC0_PKT_INFO_8822B) << BIT_SHIFT_AC0_PKT_INFO_8822B)
-#define BIT_GET_AC0_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_AC0_PKT_INFO_8822B) & BIT_MASK_AC0_PKT_INFO_8822B)
-
+#define BIT_AC0_PKT_INFO_8822B(x) \
+ (((x) & BIT_MASK_AC0_PKT_INFO_8822B) << BIT_SHIFT_AC0_PKT_INFO_8822B)
+#define BITS_AC0_PKT_INFO_8822B \
+ (BIT_MASK_AC0_PKT_INFO_8822B << BIT_SHIFT_AC0_PKT_INFO_8822B)
+#define BIT_CLEAR_AC0_PKT_INFO_8822B(x) ((x) & (~BITS_AC0_PKT_INFO_8822B))
+#define BIT_GET_AC0_PKT_INFO_8822B(x) \
+ (((x) >> BIT_SHIFT_AC0_PKT_INFO_8822B) & BIT_MASK_AC0_PKT_INFO_8822B)
+#define BIT_SET_AC0_PKT_INFO_8822B(x, v) \
+ (BIT_CLEAR_AC0_PKT_INFO_8822B(x) | BIT_AC0_PKT_INFO_8822B(v))
/* 2 REG_Q2_Q3_INFO_8822B */
#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822B BIT(31)
#define BIT_SHIFT_GTAB_ID_8822B 28
#define BIT_MASK_GTAB_ID_8822B 0x7
-#define BIT_GTAB_ID_8822B(x) (((x) & BIT_MASK_GTAB_ID_8822B) << BIT_SHIFT_GTAB_ID_8822B)
-#define BIT_GET_GTAB_ID_8822B(x) (((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B)
-
+#define BIT_GTAB_ID_8822B(x) \
+ (((x) & BIT_MASK_GTAB_ID_8822B) << BIT_SHIFT_GTAB_ID_8822B)
+#define BITS_GTAB_ID_8822B (BIT_MASK_GTAB_ID_8822B << BIT_SHIFT_GTAB_ID_8822B)
+#define BIT_CLEAR_GTAB_ID_8822B(x) ((x) & (~BITS_GTAB_ID_8822B))
+#define BIT_GET_GTAB_ID_8822B(x) \
+ (((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B)
+#define BIT_SET_GTAB_ID_8822B(x, v) \
+ (BIT_CLEAR_GTAB_ID_8822B(x) | BIT_GTAB_ID_8822B(v))
#define BIT_SHIFT_AC3_PKT_INFO_8822B 16
#define BIT_MASK_AC3_PKT_INFO_8822B 0xfff
-#define BIT_AC3_PKT_INFO_8822B(x) (((x) & BIT_MASK_AC3_PKT_INFO_8822B) << BIT_SHIFT_AC3_PKT_INFO_8822B)
-#define BIT_GET_AC3_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_AC3_PKT_INFO_8822B) & BIT_MASK_AC3_PKT_INFO_8822B)
+#define BIT_AC3_PKT_INFO_8822B(x) \
+ (((x) & BIT_MASK_AC3_PKT_INFO_8822B) << BIT_SHIFT_AC3_PKT_INFO_8822B)
+#define BITS_AC3_PKT_INFO_8822B \
+ (BIT_MASK_AC3_PKT_INFO_8822B << BIT_SHIFT_AC3_PKT_INFO_8822B)
+#define BIT_CLEAR_AC3_PKT_INFO_8822B(x) ((x) & (~BITS_AC3_PKT_INFO_8822B))
+#define BIT_GET_AC3_PKT_INFO_8822B(x) \
+ (((x) >> BIT_SHIFT_AC3_PKT_INFO_8822B) & BIT_MASK_AC3_PKT_INFO_8822B)
+#define BIT_SET_AC3_PKT_INFO_8822B(x, v) \
+ (BIT_CLEAR_AC3_PKT_INFO_8822B(x) | BIT_AC3_PKT_INFO_8822B(v))
#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822B BIT(15)
#define BIT_SHIFT_GTAB_ID_V1_8822B 12
#define BIT_MASK_GTAB_ID_V1_8822B 0x7
-#define BIT_GTAB_ID_V1_8822B(x) (((x) & BIT_MASK_GTAB_ID_V1_8822B) << BIT_SHIFT_GTAB_ID_V1_8822B)
-#define BIT_GET_GTAB_ID_V1_8822B(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B)
-
+#define BIT_GTAB_ID_V1_8822B(x) \
+ (((x) & BIT_MASK_GTAB_ID_V1_8822B) << BIT_SHIFT_GTAB_ID_V1_8822B)
+#define BITS_GTAB_ID_V1_8822B \
+ (BIT_MASK_GTAB_ID_V1_8822B << BIT_SHIFT_GTAB_ID_V1_8822B)
+#define BIT_CLEAR_GTAB_ID_V1_8822B(x) ((x) & (~BITS_GTAB_ID_V1_8822B))
+#define BIT_GET_GTAB_ID_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B)
+#define BIT_SET_GTAB_ID_V1_8822B(x, v) \
+ (BIT_CLEAR_GTAB_ID_V1_8822B(x) | BIT_GTAB_ID_V1_8822B(v))
#define BIT_SHIFT_AC2_PKT_INFO_8822B 0
#define BIT_MASK_AC2_PKT_INFO_8822B 0xfff
-#define BIT_AC2_PKT_INFO_8822B(x) (((x) & BIT_MASK_AC2_PKT_INFO_8822B) << BIT_SHIFT_AC2_PKT_INFO_8822B)
-#define BIT_GET_AC2_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_AC2_PKT_INFO_8822B) & BIT_MASK_AC2_PKT_INFO_8822B)
-
+#define BIT_AC2_PKT_INFO_8822B(x) \
+ (((x) & BIT_MASK_AC2_PKT_INFO_8822B) << BIT_SHIFT_AC2_PKT_INFO_8822B)
+#define BITS_AC2_PKT_INFO_8822B \
+ (BIT_MASK_AC2_PKT_INFO_8822B << BIT_SHIFT_AC2_PKT_INFO_8822B)
+#define BIT_CLEAR_AC2_PKT_INFO_8822B(x) ((x) & (~BITS_AC2_PKT_INFO_8822B))
+#define BIT_GET_AC2_PKT_INFO_8822B(x) \
+ (((x) >> BIT_SHIFT_AC2_PKT_INFO_8822B) & BIT_MASK_AC2_PKT_INFO_8822B)
+#define BIT_SET_AC2_PKT_INFO_8822B(x, v) \
+ (BIT_CLEAR_AC2_PKT_INFO_8822B(x) | BIT_AC2_PKT_INFO_8822B(v))
/* 2 REG_Q4_Q5_INFO_8822B */
#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822B BIT(31)
#define BIT_SHIFT_GTAB_ID_8822B 28
#define BIT_MASK_GTAB_ID_8822B 0x7
-#define BIT_GTAB_ID_8822B(x) (((x) & BIT_MASK_GTAB_ID_8822B) << BIT_SHIFT_GTAB_ID_8822B)
-#define BIT_GET_GTAB_ID_8822B(x) (((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B)
-
+#define BIT_GTAB_ID_8822B(x) \
+ (((x) & BIT_MASK_GTAB_ID_8822B) << BIT_SHIFT_GTAB_ID_8822B)
+#define BITS_GTAB_ID_8822B (BIT_MASK_GTAB_ID_8822B << BIT_SHIFT_GTAB_ID_8822B)
+#define BIT_CLEAR_GTAB_ID_8822B(x) ((x) & (~BITS_GTAB_ID_8822B))
+#define BIT_GET_GTAB_ID_8822B(x) \
+ (((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B)
+#define BIT_SET_GTAB_ID_8822B(x, v) \
+ (BIT_CLEAR_GTAB_ID_8822B(x) | BIT_GTAB_ID_8822B(v))
#define BIT_SHIFT_AC5_PKT_INFO_8822B 16
#define BIT_MASK_AC5_PKT_INFO_8822B 0xfff
-#define BIT_AC5_PKT_INFO_8822B(x) (((x) & BIT_MASK_AC5_PKT_INFO_8822B) << BIT_SHIFT_AC5_PKT_INFO_8822B)
-#define BIT_GET_AC5_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_AC5_PKT_INFO_8822B) & BIT_MASK_AC5_PKT_INFO_8822B)
+#define BIT_AC5_PKT_INFO_8822B(x) \
+ (((x) & BIT_MASK_AC5_PKT_INFO_8822B) << BIT_SHIFT_AC5_PKT_INFO_8822B)
+#define BITS_AC5_PKT_INFO_8822B \
+ (BIT_MASK_AC5_PKT_INFO_8822B << BIT_SHIFT_AC5_PKT_INFO_8822B)
+#define BIT_CLEAR_AC5_PKT_INFO_8822B(x) ((x) & (~BITS_AC5_PKT_INFO_8822B))
+#define BIT_GET_AC5_PKT_INFO_8822B(x) \
+ (((x) >> BIT_SHIFT_AC5_PKT_INFO_8822B) & BIT_MASK_AC5_PKT_INFO_8822B)
+#define BIT_SET_AC5_PKT_INFO_8822B(x, v) \
+ (BIT_CLEAR_AC5_PKT_INFO_8822B(x) | BIT_AC5_PKT_INFO_8822B(v))
#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822B BIT(15)
#define BIT_SHIFT_GTAB_ID_V1_8822B 12
#define BIT_MASK_GTAB_ID_V1_8822B 0x7
-#define BIT_GTAB_ID_V1_8822B(x) (((x) & BIT_MASK_GTAB_ID_V1_8822B) << BIT_SHIFT_GTAB_ID_V1_8822B)
-#define BIT_GET_GTAB_ID_V1_8822B(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B)
-
+#define BIT_GTAB_ID_V1_8822B(x) \
+ (((x) & BIT_MASK_GTAB_ID_V1_8822B) << BIT_SHIFT_GTAB_ID_V1_8822B)
+#define BITS_GTAB_ID_V1_8822B \
+ (BIT_MASK_GTAB_ID_V1_8822B << BIT_SHIFT_GTAB_ID_V1_8822B)
+#define BIT_CLEAR_GTAB_ID_V1_8822B(x) ((x) & (~BITS_GTAB_ID_V1_8822B))
+#define BIT_GET_GTAB_ID_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B)
+#define BIT_SET_GTAB_ID_V1_8822B(x, v) \
+ (BIT_CLEAR_GTAB_ID_V1_8822B(x) | BIT_GTAB_ID_V1_8822B(v))
#define BIT_SHIFT_AC4_PKT_INFO_8822B 0
#define BIT_MASK_AC4_PKT_INFO_8822B 0xfff
-#define BIT_AC4_PKT_INFO_8822B(x) (((x) & BIT_MASK_AC4_PKT_INFO_8822B) << BIT_SHIFT_AC4_PKT_INFO_8822B)
-#define BIT_GET_AC4_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_AC4_PKT_INFO_8822B) & BIT_MASK_AC4_PKT_INFO_8822B)
-
+#define BIT_AC4_PKT_INFO_8822B(x) \
+ (((x) & BIT_MASK_AC4_PKT_INFO_8822B) << BIT_SHIFT_AC4_PKT_INFO_8822B)
+#define BITS_AC4_PKT_INFO_8822B \
+ (BIT_MASK_AC4_PKT_INFO_8822B << BIT_SHIFT_AC4_PKT_INFO_8822B)
+#define BIT_CLEAR_AC4_PKT_INFO_8822B(x) ((x) & (~BITS_AC4_PKT_INFO_8822B))
+#define BIT_GET_AC4_PKT_INFO_8822B(x) \
+ (((x) >> BIT_SHIFT_AC4_PKT_INFO_8822B) & BIT_MASK_AC4_PKT_INFO_8822B)
+#define BIT_SET_AC4_PKT_INFO_8822B(x, v) \
+ (BIT_CLEAR_AC4_PKT_INFO_8822B(x) | BIT_AC4_PKT_INFO_8822B(v))
/* 2 REG_Q6_Q7_INFO_8822B */
#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822B BIT(31)
#define BIT_SHIFT_GTAB_ID_8822B 28
#define BIT_MASK_GTAB_ID_8822B 0x7
-#define BIT_GTAB_ID_8822B(x) (((x) & BIT_MASK_GTAB_ID_8822B) << BIT_SHIFT_GTAB_ID_8822B)
-#define BIT_GET_GTAB_ID_8822B(x) (((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B)
-
+#define BIT_GTAB_ID_8822B(x) \
+ (((x) & BIT_MASK_GTAB_ID_8822B) << BIT_SHIFT_GTAB_ID_8822B)
+#define BITS_GTAB_ID_8822B (BIT_MASK_GTAB_ID_8822B << BIT_SHIFT_GTAB_ID_8822B)
+#define BIT_CLEAR_GTAB_ID_8822B(x) ((x) & (~BITS_GTAB_ID_8822B))
+#define BIT_GET_GTAB_ID_8822B(x) \
+ (((x) >> BIT_SHIFT_GTAB_ID_8822B) & BIT_MASK_GTAB_ID_8822B)
+#define BIT_SET_GTAB_ID_8822B(x, v) \
+ (BIT_CLEAR_GTAB_ID_8822B(x) | BIT_GTAB_ID_8822B(v))
#define BIT_SHIFT_AC7_PKT_INFO_8822B 16
#define BIT_MASK_AC7_PKT_INFO_8822B 0xfff
-#define BIT_AC7_PKT_INFO_8822B(x) (((x) & BIT_MASK_AC7_PKT_INFO_8822B) << BIT_SHIFT_AC7_PKT_INFO_8822B)
-#define BIT_GET_AC7_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_AC7_PKT_INFO_8822B) & BIT_MASK_AC7_PKT_INFO_8822B)
+#define BIT_AC7_PKT_INFO_8822B(x) \
+ (((x) & BIT_MASK_AC7_PKT_INFO_8822B) << BIT_SHIFT_AC7_PKT_INFO_8822B)
+#define BITS_AC7_PKT_INFO_8822B \
+ (BIT_MASK_AC7_PKT_INFO_8822B << BIT_SHIFT_AC7_PKT_INFO_8822B)
+#define BIT_CLEAR_AC7_PKT_INFO_8822B(x) ((x) & (~BITS_AC7_PKT_INFO_8822B))
+#define BIT_GET_AC7_PKT_INFO_8822B(x) \
+ (((x) >> BIT_SHIFT_AC7_PKT_INFO_8822B) & BIT_MASK_AC7_PKT_INFO_8822B)
+#define BIT_SET_AC7_PKT_INFO_8822B(x, v) \
+ (BIT_CLEAR_AC7_PKT_INFO_8822B(x) | BIT_AC7_PKT_INFO_8822B(v))
#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822B BIT(15)
#define BIT_SHIFT_GTAB_ID_V1_8822B 12
#define BIT_MASK_GTAB_ID_V1_8822B 0x7
-#define BIT_GTAB_ID_V1_8822B(x) (((x) & BIT_MASK_GTAB_ID_V1_8822B) << BIT_SHIFT_GTAB_ID_V1_8822B)
-#define BIT_GET_GTAB_ID_V1_8822B(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B)
-
+#define BIT_GTAB_ID_V1_8822B(x) \
+ (((x) & BIT_MASK_GTAB_ID_V1_8822B) << BIT_SHIFT_GTAB_ID_V1_8822B)
+#define BITS_GTAB_ID_V1_8822B \
+ (BIT_MASK_GTAB_ID_V1_8822B << BIT_SHIFT_GTAB_ID_V1_8822B)
+#define BIT_CLEAR_GTAB_ID_V1_8822B(x) ((x) & (~BITS_GTAB_ID_V1_8822B))
+#define BIT_GET_GTAB_ID_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_GTAB_ID_V1_8822B) & BIT_MASK_GTAB_ID_V1_8822B)
+#define BIT_SET_GTAB_ID_V1_8822B(x, v) \
+ (BIT_CLEAR_GTAB_ID_V1_8822B(x) | BIT_GTAB_ID_V1_8822B(v))
#define BIT_SHIFT_AC6_PKT_INFO_8822B 0
#define BIT_MASK_AC6_PKT_INFO_8822B 0xfff
-#define BIT_AC6_PKT_INFO_8822B(x) (((x) & BIT_MASK_AC6_PKT_INFO_8822B) << BIT_SHIFT_AC6_PKT_INFO_8822B)
-#define BIT_GET_AC6_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_AC6_PKT_INFO_8822B) & BIT_MASK_AC6_PKT_INFO_8822B)
-
+#define BIT_AC6_PKT_INFO_8822B(x) \
+ (((x) & BIT_MASK_AC6_PKT_INFO_8822B) << BIT_SHIFT_AC6_PKT_INFO_8822B)
+#define BITS_AC6_PKT_INFO_8822B \
+ (BIT_MASK_AC6_PKT_INFO_8822B << BIT_SHIFT_AC6_PKT_INFO_8822B)
+#define BIT_CLEAR_AC6_PKT_INFO_8822B(x) ((x) & (~BITS_AC6_PKT_INFO_8822B))
+#define BIT_GET_AC6_PKT_INFO_8822B(x) \
+ (((x) >> BIT_SHIFT_AC6_PKT_INFO_8822B) & BIT_MASK_AC6_PKT_INFO_8822B)
+#define BIT_SET_AC6_PKT_INFO_8822B(x, v) \
+ (BIT_CLEAR_AC6_PKT_INFO_8822B(x) | BIT_AC6_PKT_INFO_8822B(v))
/* 2 REG_MGQ_HIQ_INFO_8822B */
#define BIT_SHIFT_HIQ_PKT_INFO_8822B 16
#define BIT_MASK_HIQ_PKT_INFO_8822B 0xfff
-#define BIT_HIQ_PKT_INFO_8822B(x) (((x) & BIT_MASK_HIQ_PKT_INFO_8822B) << BIT_SHIFT_HIQ_PKT_INFO_8822B)
-#define BIT_GET_HIQ_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_HIQ_PKT_INFO_8822B) & BIT_MASK_HIQ_PKT_INFO_8822B)
-
+#define BIT_HIQ_PKT_INFO_8822B(x) \
+ (((x) & BIT_MASK_HIQ_PKT_INFO_8822B) << BIT_SHIFT_HIQ_PKT_INFO_8822B)
+#define BITS_HIQ_PKT_INFO_8822B \
+ (BIT_MASK_HIQ_PKT_INFO_8822B << BIT_SHIFT_HIQ_PKT_INFO_8822B)
+#define BIT_CLEAR_HIQ_PKT_INFO_8822B(x) ((x) & (~BITS_HIQ_PKT_INFO_8822B))
+#define BIT_GET_HIQ_PKT_INFO_8822B(x) \
+ (((x) >> BIT_SHIFT_HIQ_PKT_INFO_8822B) & BIT_MASK_HIQ_PKT_INFO_8822B)
+#define BIT_SET_HIQ_PKT_INFO_8822B(x, v) \
+ (BIT_CLEAR_HIQ_PKT_INFO_8822B(x) | BIT_HIQ_PKT_INFO_8822B(v))
#define BIT_SHIFT_MGQ_PKT_INFO_8822B 0
#define BIT_MASK_MGQ_PKT_INFO_8822B 0xfff
-#define BIT_MGQ_PKT_INFO_8822B(x) (((x) & BIT_MASK_MGQ_PKT_INFO_8822B) << BIT_SHIFT_MGQ_PKT_INFO_8822B)
-#define BIT_GET_MGQ_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_MGQ_PKT_INFO_8822B) & BIT_MASK_MGQ_PKT_INFO_8822B)
-
+#define BIT_MGQ_PKT_INFO_8822B(x) \
+ (((x) & BIT_MASK_MGQ_PKT_INFO_8822B) << BIT_SHIFT_MGQ_PKT_INFO_8822B)
+#define BITS_MGQ_PKT_INFO_8822B \
+ (BIT_MASK_MGQ_PKT_INFO_8822B << BIT_SHIFT_MGQ_PKT_INFO_8822B)
+#define BIT_CLEAR_MGQ_PKT_INFO_8822B(x) ((x) & (~BITS_MGQ_PKT_INFO_8822B))
+#define BIT_GET_MGQ_PKT_INFO_8822B(x) \
+ (((x) >> BIT_SHIFT_MGQ_PKT_INFO_8822B) & BIT_MASK_MGQ_PKT_INFO_8822B)
+#define BIT_SET_MGQ_PKT_INFO_8822B(x, v) \
+ (BIT_CLEAR_MGQ_PKT_INFO_8822B(x) | BIT_MGQ_PKT_INFO_8822B(v))
/* 2 REG_CMDQ_BCNQ_INFO_8822B */
#define BIT_SHIFT_CMDQ_PKT_INFO_8822B 16
#define BIT_MASK_CMDQ_PKT_INFO_8822B 0xfff
-#define BIT_CMDQ_PKT_INFO_8822B(x) (((x) & BIT_MASK_CMDQ_PKT_INFO_8822B) << BIT_SHIFT_CMDQ_PKT_INFO_8822B)
-#define BIT_GET_CMDQ_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_CMDQ_PKT_INFO_8822B) & BIT_MASK_CMDQ_PKT_INFO_8822B)
-
+#define BIT_CMDQ_PKT_INFO_8822B(x) \
+ (((x) & BIT_MASK_CMDQ_PKT_INFO_8822B) << BIT_SHIFT_CMDQ_PKT_INFO_8822B)
+#define BITS_CMDQ_PKT_INFO_8822B \
+ (BIT_MASK_CMDQ_PKT_INFO_8822B << BIT_SHIFT_CMDQ_PKT_INFO_8822B)
+#define BIT_CLEAR_CMDQ_PKT_INFO_8822B(x) ((x) & (~BITS_CMDQ_PKT_INFO_8822B))
+#define BIT_GET_CMDQ_PKT_INFO_8822B(x) \
+ (((x) >> BIT_SHIFT_CMDQ_PKT_INFO_8822B) & BIT_MASK_CMDQ_PKT_INFO_8822B)
+#define BIT_SET_CMDQ_PKT_INFO_8822B(x, v) \
+ (BIT_CLEAR_CMDQ_PKT_INFO_8822B(x) | BIT_CMDQ_PKT_INFO_8822B(v))
#define BIT_SHIFT_BCNQ_PKT_INFO_8822B 0
#define BIT_MASK_BCNQ_PKT_INFO_8822B 0xfff
-#define BIT_BCNQ_PKT_INFO_8822B(x) (((x) & BIT_MASK_BCNQ_PKT_INFO_8822B) << BIT_SHIFT_BCNQ_PKT_INFO_8822B)
-#define BIT_GET_BCNQ_PKT_INFO_8822B(x) (((x) >> BIT_SHIFT_BCNQ_PKT_INFO_8822B) & BIT_MASK_BCNQ_PKT_INFO_8822B)
-
+#define BIT_BCNQ_PKT_INFO_8822B(x) \
+ (((x) & BIT_MASK_BCNQ_PKT_INFO_8822B) << BIT_SHIFT_BCNQ_PKT_INFO_8822B)
+#define BITS_BCNQ_PKT_INFO_8822B \
+ (BIT_MASK_BCNQ_PKT_INFO_8822B << BIT_SHIFT_BCNQ_PKT_INFO_8822B)
+#define BIT_CLEAR_BCNQ_PKT_INFO_8822B(x) ((x) & (~BITS_BCNQ_PKT_INFO_8822B))
+#define BIT_GET_BCNQ_PKT_INFO_8822B(x) \
+ (((x) >> BIT_SHIFT_BCNQ_PKT_INFO_8822B) & BIT_MASK_BCNQ_PKT_INFO_8822B)
+#define BIT_SET_BCNQ_PKT_INFO_8822B(x, v) \
+ (BIT_CLEAR_BCNQ_PKT_INFO_8822B(x) | BIT_BCNQ_PKT_INFO_8822B(v))
/* 2 REG_USEREG_SETTING_8822B */
#define BIT_NDPA_USEREG_8822B BIT(21)
#define BIT_SHIFT_RETRY_USEREG_8822B 19
#define BIT_MASK_RETRY_USEREG_8822B 0x3
-#define BIT_RETRY_USEREG_8822B(x) (((x) & BIT_MASK_RETRY_USEREG_8822B) << BIT_SHIFT_RETRY_USEREG_8822B)
-#define BIT_GET_RETRY_USEREG_8822B(x) (((x) >> BIT_SHIFT_RETRY_USEREG_8822B) & BIT_MASK_RETRY_USEREG_8822B)
-
+#define BIT_RETRY_USEREG_8822B(x) \
+ (((x) & BIT_MASK_RETRY_USEREG_8822B) << BIT_SHIFT_RETRY_USEREG_8822B)
+#define BITS_RETRY_USEREG_8822B \
+ (BIT_MASK_RETRY_USEREG_8822B << BIT_SHIFT_RETRY_USEREG_8822B)
+#define BIT_CLEAR_RETRY_USEREG_8822B(x) ((x) & (~BITS_RETRY_USEREG_8822B))
+#define BIT_GET_RETRY_USEREG_8822B(x) \
+ (((x) >> BIT_SHIFT_RETRY_USEREG_8822B) & BIT_MASK_RETRY_USEREG_8822B)
+#define BIT_SET_RETRY_USEREG_8822B(x, v) \
+ (BIT_CLEAR_RETRY_USEREG_8822B(x) | BIT_RETRY_USEREG_8822B(v))
#define BIT_SHIFT_TRYPKT_USEREG_8822B 17
#define BIT_MASK_TRYPKT_USEREG_8822B 0x3
-#define BIT_TRYPKT_USEREG_8822B(x) (((x) & BIT_MASK_TRYPKT_USEREG_8822B) << BIT_SHIFT_TRYPKT_USEREG_8822B)
-#define BIT_GET_TRYPKT_USEREG_8822B(x) (((x) >> BIT_SHIFT_TRYPKT_USEREG_8822B) & BIT_MASK_TRYPKT_USEREG_8822B)
+#define BIT_TRYPKT_USEREG_8822B(x) \
+ (((x) & BIT_MASK_TRYPKT_USEREG_8822B) << BIT_SHIFT_TRYPKT_USEREG_8822B)
+#define BITS_TRYPKT_USEREG_8822B \
+ (BIT_MASK_TRYPKT_USEREG_8822B << BIT_SHIFT_TRYPKT_USEREG_8822B)
+#define BIT_CLEAR_TRYPKT_USEREG_8822B(x) ((x) & (~BITS_TRYPKT_USEREG_8822B))
+#define BIT_GET_TRYPKT_USEREG_8822B(x) \
+ (((x) >> BIT_SHIFT_TRYPKT_USEREG_8822B) & BIT_MASK_TRYPKT_USEREG_8822B)
+#define BIT_SET_TRYPKT_USEREG_8822B(x, v) \
+ (BIT_CLEAR_TRYPKT_USEREG_8822B(x) | BIT_TRYPKT_USEREG_8822B(v))
#define BIT_CTLPKT_USEREG_8822B BIT(16)
@@ -5964,9 +10195,15 @@
#define BIT_SHIFT_AESIV_OFFSET_8822B 0
#define BIT_MASK_AESIV_OFFSET_8822B 0xfff
-#define BIT_AESIV_OFFSET_8822B(x) (((x) & BIT_MASK_AESIV_OFFSET_8822B) << BIT_SHIFT_AESIV_OFFSET_8822B)
-#define BIT_GET_AESIV_OFFSET_8822B(x) (((x) >> BIT_SHIFT_AESIV_OFFSET_8822B) & BIT_MASK_AESIV_OFFSET_8822B)
-
+#define BIT_AESIV_OFFSET_8822B(x) \
+ (((x) & BIT_MASK_AESIV_OFFSET_8822B) << BIT_SHIFT_AESIV_OFFSET_8822B)
+#define BITS_AESIV_OFFSET_8822B \
+ (BIT_MASK_AESIV_OFFSET_8822B << BIT_SHIFT_AESIV_OFFSET_8822B)
+#define BIT_CLEAR_AESIV_OFFSET_8822B(x) ((x) & (~BITS_AESIV_OFFSET_8822B))
+#define BIT_GET_AESIV_OFFSET_8822B(x) \
+ (((x) >> BIT_SHIFT_AESIV_OFFSET_8822B) & BIT_MASK_AESIV_OFFSET_8822B)
+#define BIT_SET_AESIV_OFFSET_8822B(x, v) \
+ (BIT_CLEAR_AESIV_OFFSET_8822B(x) | BIT_AESIV_OFFSET_8822B(v))
/* 2 REG_BF0_TIME_SETTING_8822B */
#define BIT_BF0_TIMER_SET_8822B BIT(31)
@@ -5976,15 +10213,30 @@
#define BIT_SHIFT_BF0_PRETIME_OVER_8822B 16
#define BIT_MASK_BF0_PRETIME_OVER_8822B 0xfff
-#define BIT_BF0_PRETIME_OVER_8822B(x) (((x) & BIT_MASK_BF0_PRETIME_OVER_8822B) << BIT_SHIFT_BF0_PRETIME_OVER_8822B)
-#define BIT_GET_BF0_PRETIME_OVER_8822B(x) (((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8822B) & BIT_MASK_BF0_PRETIME_OVER_8822B)
-
+#define BIT_BF0_PRETIME_OVER_8822B(x) \
+ (((x) & BIT_MASK_BF0_PRETIME_OVER_8822B) \
+ << BIT_SHIFT_BF0_PRETIME_OVER_8822B)
+#define BITS_BF0_PRETIME_OVER_8822B \
+ (BIT_MASK_BF0_PRETIME_OVER_8822B << BIT_SHIFT_BF0_PRETIME_OVER_8822B)
+#define BIT_CLEAR_BF0_PRETIME_OVER_8822B(x) \
+ ((x) & (~BITS_BF0_PRETIME_OVER_8822B))
+#define BIT_GET_BF0_PRETIME_OVER_8822B(x) \
+ (((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8822B) & \
+ BIT_MASK_BF0_PRETIME_OVER_8822B)
+#define BIT_SET_BF0_PRETIME_OVER_8822B(x, v) \
+ (BIT_CLEAR_BF0_PRETIME_OVER_8822B(x) | BIT_BF0_PRETIME_OVER_8822B(v))
#define BIT_SHIFT_BF0_LIFETIME_8822B 0
#define BIT_MASK_BF0_LIFETIME_8822B 0xffff
-#define BIT_BF0_LIFETIME_8822B(x) (((x) & BIT_MASK_BF0_LIFETIME_8822B) << BIT_SHIFT_BF0_LIFETIME_8822B)
-#define BIT_GET_BF0_LIFETIME_8822B(x) (((x) >> BIT_SHIFT_BF0_LIFETIME_8822B) & BIT_MASK_BF0_LIFETIME_8822B)
-
+#define BIT_BF0_LIFETIME_8822B(x) \
+ (((x) & BIT_MASK_BF0_LIFETIME_8822B) << BIT_SHIFT_BF0_LIFETIME_8822B)
+#define BITS_BF0_LIFETIME_8822B \
+ (BIT_MASK_BF0_LIFETIME_8822B << BIT_SHIFT_BF0_LIFETIME_8822B)
+#define BIT_CLEAR_BF0_LIFETIME_8822B(x) ((x) & (~BITS_BF0_LIFETIME_8822B))
+#define BIT_GET_BF0_LIFETIME_8822B(x) \
+ (((x) >> BIT_SHIFT_BF0_LIFETIME_8822B) & BIT_MASK_BF0_LIFETIME_8822B)
+#define BIT_SET_BF0_LIFETIME_8822B(x, v) \
+ (BIT_CLEAR_BF0_LIFETIME_8822B(x) | BIT_BF0_LIFETIME_8822B(v))
/* 2 REG_BF1_TIME_SETTING_8822B */
#define BIT_BF1_TIMER_SET_8822B BIT(31)
@@ -5994,15 +10246,30 @@
#define BIT_SHIFT_BF1_PRETIME_OVER_8822B 16
#define BIT_MASK_BF1_PRETIME_OVER_8822B 0xfff
-#define BIT_BF1_PRETIME_OVER_8822B(x) (((x) & BIT_MASK_BF1_PRETIME_OVER_8822B) << BIT_SHIFT_BF1_PRETIME_OVER_8822B)
-#define BIT_GET_BF1_PRETIME_OVER_8822B(x) (((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8822B) & BIT_MASK_BF1_PRETIME_OVER_8822B)
-
+#define BIT_BF1_PRETIME_OVER_8822B(x) \
+ (((x) & BIT_MASK_BF1_PRETIME_OVER_8822B) \
+ << BIT_SHIFT_BF1_PRETIME_OVER_8822B)
+#define BITS_BF1_PRETIME_OVER_8822B \
+ (BIT_MASK_BF1_PRETIME_OVER_8822B << BIT_SHIFT_BF1_PRETIME_OVER_8822B)
+#define BIT_CLEAR_BF1_PRETIME_OVER_8822B(x) \
+ ((x) & (~BITS_BF1_PRETIME_OVER_8822B))
+#define BIT_GET_BF1_PRETIME_OVER_8822B(x) \
+ (((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8822B) & \
+ BIT_MASK_BF1_PRETIME_OVER_8822B)
+#define BIT_SET_BF1_PRETIME_OVER_8822B(x, v) \
+ (BIT_CLEAR_BF1_PRETIME_OVER_8822B(x) | BIT_BF1_PRETIME_OVER_8822B(v))
#define BIT_SHIFT_BF1_LIFETIME_8822B 0
#define BIT_MASK_BF1_LIFETIME_8822B 0xffff
-#define BIT_BF1_LIFETIME_8822B(x) (((x) & BIT_MASK_BF1_LIFETIME_8822B) << BIT_SHIFT_BF1_LIFETIME_8822B)
-#define BIT_GET_BF1_LIFETIME_8822B(x) (((x) >> BIT_SHIFT_BF1_LIFETIME_8822B) & BIT_MASK_BF1_LIFETIME_8822B)
-
+#define BIT_BF1_LIFETIME_8822B(x) \
+ (((x) & BIT_MASK_BF1_LIFETIME_8822B) << BIT_SHIFT_BF1_LIFETIME_8822B)
+#define BITS_BF1_LIFETIME_8822B \
+ (BIT_MASK_BF1_LIFETIME_8822B << BIT_SHIFT_BF1_LIFETIME_8822B)
+#define BIT_CLEAR_BF1_LIFETIME_8822B(x) ((x) & (~BITS_BF1_LIFETIME_8822B))
+#define BIT_GET_BF1_LIFETIME_8822B(x) \
+ (((x) >> BIT_SHIFT_BF1_LIFETIME_8822B) & BIT_MASK_BF1_LIFETIME_8822B)
+#define BIT_SET_BF1_LIFETIME_8822B(x, v) \
+ (BIT_CLEAR_BF1_LIFETIME_8822B(x) | BIT_BF1_LIFETIME_8822B(v))
/* 2 REG_BF_TIMEOUT_EN_8822B */
#define BIT_EN_VHT_LDPC_8822B BIT(9)
@@ -6014,189 +10281,434 @@
#define BIT_SHIFT_MACID31_0_RELEASE_8822B 0
#define BIT_MASK_MACID31_0_RELEASE_8822B 0xffffffffL
-#define BIT_MACID31_0_RELEASE_8822B(x) (((x) & BIT_MASK_MACID31_0_RELEASE_8822B) << BIT_SHIFT_MACID31_0_RELEASE_8822B)
-#define BIT_GET_MACID31_0_RELEASE_8822B(x) (((x) >> BIT_SHIFT_MACID31_0_RELEASE_8822B) & BIT_MASK_MACID31_0_RELEASE_8822B)
-
+#define BIT_MACID31_0_RELEASE_8822B(x) \
+ (((x) & BIT_MASK_MACID31_0_RELEASE_8822B) \
+ << BIT_SHIFT_MACID31_0_RELEASE_8822B)
+#define BITS_MACID31_0_RELEASE_8822B \
+ (BIT_MASK_MACID31_0_RELEASE_8822B << BIT_SHIFT_MACID31_0_RELEASE_8822B)
+#define BIT_CLEAR_MACID31_0_RELEASE_8822B(x) \
+ ((x) & (~BITS_MACID31_0_RELEASE_8822B))
+#define BIT_GET_MACID31_0_RELEASE_8822B(x) \
+ (((x) >> BIT_SHIFT_MACID31_0_RELEASE_8822B) & \
+ BIT_MASK_MACID31_0_RELEASE_8822B)
+#define BIT_SET_MACID31_0_RELEASE_8822B(x, v) \
+ (BIT_CLEAR_MACID31_0_RELEASE_8822B(x) | BIT_MACID31_0_RELEASE_8822B(v))
/* 2 REG_MACID_RELEASE1_8822B */
#define BIT_SHIFT_MACID63_32_RELEASE_8822B 0
#define BIT_MASK_MACID63_32_RELEASE_8822B 0xffffffffL
-#define BIT_MACID63_32_RELEASE_8822B(x) (((x) & BIT_MASK_MACID63_32_RELEASE_8822B) << BIT_SHIFT_MACID63_32_RELEASE_8822B)
-#define BIT_GET_MACID63_32_RELEASE_8822B(x) (((x) >> BIT_SHIFT_MACID63_32_RELEASE_8822B) & BIT_MASK_MACID63_32_RELEASE_8822B)
-
+#define BIT_MACID63_32_RELEASE_8822B(x) \
+ (((x) & BIT_MASK_MACID63_32_RELEASE_8822B) \
+ << BIT_SHIFT_MACID63_32_RELEASE_8822B)
+#define BITS_MACID63_32_RELEASE_8822B \
+ (BIT_MASK_MACID63_32_RELEASE_8822B \
+ << BIT_SHIFT_MACID63_32_RELEASE_8822B)
+#define BIT_CLEAR_MACID63_32_RELEASE_8822B(x) \
+ ((x) & (~BITS_MACID63_32_RELEASE_8822B))
+#define BIT_GET_MACID63_32_RELEASE_8822B(x) \
+ (((x) >> BIT_SHIFT_MACID63_32_RELEASE_8822B) & \
+ BIT_MASK_MACID63_32_RELEASE_8822B)
+#define BIT_SET_MACID63_32_RELEASE_8822B(x, v) \
+ (BIT_CLEAR_MACID63_32_RELEASE_8822B(x) | \
+ BIT_MACID63_32_RELEASE_8822B(v))
/* 2 REG_MACID_RELEASE2_8822B */
#define BIT_SHIFT_MACID95_64_RELEASE_8822B 0
#define BIT_MASK_MACID95_64_RELEASE_8822B 0xffffffffL
-#define BIT_MACID95_64_RELEASE_8822B(x) (((x) & BIT_MASK_MACID95_64_RELEASE_8822B) << BIT_SHIFT_MACID95_64_RELEASE_8822B)
-#define BIT_GET_MACID95_64_RELEASE_8822B(x) (((x) >> BIT_SHIFT_MACID95_64_RELEASE_8822B) & BIT_MASK_MACID95_64_RELEASE_8822B)
-
+#define BIT_MACID95_64_RELEASE_8822B(x) \
+ (((x) & BIT_MASK_MACID95_64_RELEASE_8822B) \
+ << BIT_SHIFT_MACID95_64_RELEASE_8822B)
+#define BITS_MACID95_64_RELEASE_8822B \
+ (BIT_MASK_MACID95_64_RELEASE_8822B \
+ << BIT_SHIFT_MACID95_64_RELEASE_8822B)
+#define BIT_CLEAR_MACID95_64_RELEASE_8822B(x) \
+ ((x) & (~BITS_MACID95_64_RELEASE_8822B))
+#define BIT_GET_MACID95_64_RELEASE_8822B(x) \
+ (((x) >> BIT_SHIFT_MACID95_64_RELEASE_8822B) & \
+ BIT_MASK_MACID95_64_RELEASE_8822B)
+#define BIT_SET_MACID95_64_RELEASE_8822B(x, v) \
+ (BIT_CLEAR_MACID95_64_RELEASE_8822B(x) | \
+ BIT_MACID95_64_RELEASE_8822B(v))
/* 2 REG_MACID_RELEASE3_8822B */
#define BIT_SHIFT_MACID127_96_RELEASE_8822B 0
#define BIT_MASK_MACID127_96_RELEASE_8822B 0xffffffffL
-#define BIT_MACID127_96_RELEASE_8822B(x) (((x) & BIT_MASK_MACID127_96_RELEASE_8822B) << BIT_SHIFT_MACID127_96_RELEASE_8822B)
-#define BIT_GET_MACID127_96_RELEASE_8822B(x) (((x) >> BIT_SHIFT_MACID127_96_RELEASE_8822B) & BIT_MASK_MACID127_96_RELEASE_8822B)
-
+#define BIT_MACID127_96_RELEASE_8822B(x) \
+ (((x) & BIT_MASK_MACID127_96_RELEASE_8822B) \
+ << BIT_SHIFT_MACID127_96_RELEASE_8822B)
+#define BITS_MACID127_96_RELEASE_8822B \
+ (BIT_MASK_MACID127_96_RELEASE_8822B \
+ << BIT_SHIFT_MACID127_96_RELEASE_8822B)
+#define BIT_CLEAR_MACID127_96_RELEASE_8822B(x) \
+ ((x) & (~BITS_MACID127_96_RELEASE_8822B))
+#define BIT_GET_MACID127_96_RELEASE_8822B(x) \
+ (((x) >> BIT_SHIFT_MACID127_96_RELEASE_8822B) & \
+ BIT_MASK_MACID127_96_RELEASE_8822B)
+#define BIT_SET_MACID127_96_RELEASE_8822B(x, v) \
+ (BIT_CLEAR_MACID127_96_RELEASE_8822B(x) | \
+ BIT_MACID127_96_RELEASE_8822B(v))
/* 2 REG_MACID_RELEASE_SETTING_8822B */
#define BIT_MACID_VALUE_8822B BIT(7)
#define BIT_SHIFT_MACID_OFFSET_8822B 0
#define BIT_MASK_MACID_OFFSET_8822B 0x7f
-#define BIT_MACID_OFFSET_8822B(x) (((x) & BIT_MASK_MACID_OFFSET_8822B) << BIT_SHIFT_MACID_OFFSET_8822B)
-#define BIT_GET_MACID_OFFSET_8822B(x) (((x) >> BIT_SHIFT_MACID_OFFSET_8822B) & BIT_MASK_MACID_OFFSET_8822B)
-
+#define BIT_MACID_OFFSET_8822B(x) \
+ (((x) & BIT_MASK_MACID_OFFSET_8822B) << BIT_SHIFT_MACID_OFFSET_8822B)
+#define BITS_MACID_OFFSET_8822B \
+ (BIT_MASK_MACID_OFFSET_8822B << BIT_SHIFT_MACID_OFFSET_8822B)
+#define BIT_CLEAR_MACID_OFFSET_8822B(x) ((x) & (~BITS_MACID_OFFSET_8822B))
+#define BIT_GET_MACID_OFFSET_8822B(x) \
+ (((x) >> BIT_SHIFT_MACID_OFFSET_8822B) & BIT_MASK_MACID_OFFSET_8822B)
+#define BIT_SET_MACID_OFFSET_8822B(x, v) \
+ (BIT_CLEAR_MACID_OFFSET_8822B(x) | BIT_MACID_OFFSET_8822B(v))
/* 2 REG_FAST_EDCA_VOVI_SETTING_8822B */
#define BIT_SHIFT_VI_FAST_EDCA_TO_8822B 24
#define BIT_MASK_VI_FAST_EDCA_TO_8822B 0xff
-#define BIT_VI_FAST_EDCA_TO_8822B(x) (((x) & BIT_MASK_VI_FAST_EDCA_TO_8822B) << BIT_SHIFT_VI_FAST_EDCA_TO_8822B)
-#define BIT_GET_VI_FAST_EDCA_TO_8822B(x) (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8822B) & BIT_MASK_VI_FAST_EDCA_TO_8822B)
+#define BIT_VI_FAST_EDCA_TO_8822B(x) \
+ (((x) & BIT_MASK_VI_FAST_EDCA_TO_8822B) \
+ << BIT_SHIFT_VI_FAST_EDCA_TO_8822B)
+#define BITS_VI_FAST_EDCA_TO_8822B \
+ (BIT_MASK_VI_FAST_EDCA_TO_8822B << BIT_SHIFT_VI_FAST_EDCA_TO_8822B)
+#define BIT_CLEAR_VI_FAST_EDCA_TO_8822B(x) ((x) & (~BITS_VI_FAST_EDCA_TO_8822B))
+#define BIT_GET_VI_FAST_EDCA_TO_8822B(x) \
+ (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8822B) & \
+ BIT_MASK_VI_FAST_EDCA_TO_8822B)
+#define BIT_SET_VI_FAST_EDCA_TO_8822B(x, v) \
+ (BIT_CLEAR_VI_FAST_EDCA_TO_8822B(x) | BIT_VI_FAST_EDCA_TO_8822B(v))
#define BIT_VI_THRESHOLD_SEL_8822B BIT(23)
#define BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822B 16
#define BIT_MASK_VI_FAST_EDCA_PKT_TH_8822B 0x7f
-#define BIT_VI_FAST_EDCA_PKT_TH_8822B(x) (((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8822B) << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822B)
-#define BIT_GET_VI_FAST_EDCA_PKT_TH_8822B(x) (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822B) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8822B)
-
+#define BIT_VI_FAST_EDCA_PKT_TH_8822B(x) \
+ (((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8822B) \
+ << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822B)
+#define BITS_VI_FAST_EDCA_PKT_TH_8822B \
+ (BIT_MASK_VI_FAST_EDCA_PKT_TH_8822B \
+ << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822B)
+#define BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8822B(x) \
+ ((x) & (~BITS_VI_FAST_EDCA_PKT_TH_8822B))
+#define BIT_GET_VI_FAST_EDCA_PKT_TH_8822B(x) \
+ (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822B) & \
+ BIT_MASK_VI_FAST_EDCA_PKT_TH_8822B)
+#define BIT_SET_VI_FAST_EDCA_PKT_TH_8822B(x, v) \
+ (BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8822B(x) | \
+ BIT_VI_FAST_EDCA_PKT_TH_8822B(v))
#define BIT_SHIFT_VO_FAST_EDCA_TO_8822B 8
#define BIT_MASK_VO_FAST_EDCA_TO_8822B 0xff
-#define BIT_VO_FAST_EDCA_TO_8822B(x) (((x) & BIT_MASK_VO_FAST_EDCA_TO_8822B) << BIT_SHIFT_VO_FAST_EDCA_TO_8822B)
-#define BIT_GET_VO_FAST_EDCA_TO_8822B(x) (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8822B) & BIT_MASK_VO_FAST_EDCA_TO_8822B)
+#define BIT_VO_FAST_EDCA_TO_8822B(x) \
+ (((x) & BIT_MASK_VO_FAST_EDCA_TO_8822B) \
+ << BIT_SHIFT_VO_FAST_EDCA_TO_8822B)
+#define BITS_VO_FAST_EDCA_TO_8822B \
+ (BIT_MASK_VO_FAST_EDCA_TO_8822B << BIT_SHIFT_VO_FAST_EDCA_TO_8822B)
+#define BIT_CLEAR_VO_FAST_EDCA_TO_8822B(x) ((x) & (~BITS_VO_FAST_EDCA_TO_8822B))
+#define BIT_GET_VO_FAST_EDCA_TO_8822B(x) \
+ (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8822B) & \
+ BIT_MASK_VO_FAST_EDCA_TO_8822B)
+#define BIT_SET_VO_FAST_EDCA_TO_8822B(x, v) \
+ (BIT_CLEAR_VO_FAST_EDCA_TO_8822B(x) | BIT_VO_FAST_EDCA_TO_8822B(v))
#define BIT_VO_THRESHOLD_SEL_8822B BIT(7)
#define BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822B 0
#define BIT_MASK_VO_FAST_EDCA_PKT_TH_8822B 0x7f
-#define BIT_VO_FAST_EDCA_PKT_TH_8822B(x) (((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8822B) << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822B)
-#define BIT_GET_VO_FAST_EDCA_PKT_TH_8822B(x) (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822B) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8822B)
-
+#define BIT_VO_FAST_EDCA_PKT_TH_8822B(x) \
+ (((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8822B) \
+ << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822B)
+#define BITS_VO_FAST_EDCA_PKT_TH_8822B \
+ (BIT_MASK_VO_FAST_EDCA_PKT_TH_8822B \
+ << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822B)
+#define BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8822B(x) \
+ ((x) & (~BITS_VO_FAST_EDCA_PKT_TH_8822B))
+#define BIT_GET_VO_FAST_EDCA_PKT_TH_8822B(x) \
+ (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822B) & \
+ BIT_MASK_VO_FAST_EDCA_PKT_TH_8822B)
+#define BIT_SET_VO_FAST_EDCA_PKT_TH_8822B(x, v) \
+ (BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8822B(x) | \
+ BIT_VO_FAST_EDCA_PKT_TH_8822B(v))
/* 2 REG_FAST_EDCA_BEBK_SETTING_8822B */
#define BIT_SHIFT_BK_FAST_EDCA_TO_8822B 24
#define BIT_MASK_BK_FAST_EDCA_TO_8822B 0xff
-#define BIT_BK_FAST_EDCA_TO_8822B(x) (((x) & BIT_MASK_BK_FAST_EDCA_TO_8822B) << BIT_SHIFT_BK_FAST_EDCA_TO_8822B)
-#define BIT_GET_BK_FAST_EDCA_TO_8822B(x) (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8822B) & BIT_MASK_BK_FAST_EDCA_TO_8822B)
+#define BIT_BK_FAST_EDCA_TO_8822B(x) \
+ (((x) & BIT_MASK_BK_FAST_EDCA_TO_8822B) \
+ << BIT_SHIFT_BK_FAST_EDCA_TO_8822B)
+#define BITS_BK_FAST_EDCA_TO_8822B \
+ (BIT_MASK_BK_FAST_EDCA_TO_8822B << BIT_SHIFT_BK_FAST_EDCA_TO_8822B)
+#define BIT_CLEAR_BK_FAST_EDCA_TO_8822B(x) ((x) & (~BITS_BK_FAST_EDCA_TO_8822B))
+#define BIT_GET_BK_FAST_EDCA_TO_8822B(x) \
+ (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8822B) & \
+ BIT_MASK_BK_FAST_EDCA_TO_8822B)
+#define BIT_SET_BK_FAST_EDCA_TO_8822B(x, v) \
+ (BIT_CLEAR_BK_FAST_EDCA_TO_8822B(x) | BIT_BK_FAST_EDCA_TO_8822B(v))
#define BIT_BK_THRESHOLD_SEL_8822B BIT(23)
#define BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822B 16
#define BIT_MASK_BK_FAST_EDCA_PKT_TH_8822B 0x7f
-#define BIT_BK_FAST_EDCA_PKT_TH_8822B(x) (((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8822B) << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822B)
-#define BIT_GET_BK_FAST_EDCA_PKT_TH_8822B(x) (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822B) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8822B)
-
+#define BIT_BK_FAST_EDCA_PKT_TH_8822B(x) \
+ (((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8822B) \
+ << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822B)
+#define BITS_BK_FAST_EDCA_PKT_TH_8822B \
+ (BIT_MASK_BK_FAST_EDCA_PKT_TH_8822B \
+ << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822B)
+#define BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8822B(x) \
+ ((x) & (~BITS_BK_FAST_EDCA_PKT_TH_8822B))
+#define BIT_GET_BK_FAST_EDCA_PKT_TH_8822B(x) \
+ (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822B) & \
+ BIT_MASK_BK_FAST_EDCA_PKT_TH_8822B)
+#define BIT_SET_BK_FAST_EDCA_PKT_TH_8822B(x, v) \
+ (BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8822B(x) | \
+ BIT_BK_FAST_EDCA_PKT_TH_8822B(v))
#define BIT_SHIFT_BE_FAST_EDCA_TO_8822B 8
#define BIT_MASK_BE_FAST_EDCA_TO_8822B 0xff
-#define BIT_BE_FAST_EDCA_TO_8822B(x) (((x) & BIT_MASK_BE_FAST_EDCA_TO_8822B) << BIT_SHIFT_BE_FAST_EDCA_TO_8822B)
-#define BIT_GET_BE_FAST_EDCA_TO_8822B(x) (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8822B) & BIT_MASK_BE_FAST_EDCA_TO_8822B)
+#define BIT_BE_FAST_EDCA_TO_8822B(x) \
+ (((x) & BIT_MASK_BE_FAST_EDCA_TO_8822B) \
+ << BIT_SHIFT_BE_FAST_EDCA_TO_8822B)
+#define BITS_BE_FAST_EDCA_TO_8822B \
+ (BIT_MASK_BE_FAST_EDCA_TO_8822B << BIT_SHIFT_BE_FAST_EDCA_TO_8822B)
+#define BIT_CLEAR_BE_FAST_EDCA_TO_8822B(x) ((x) & (~BITS_BE_FAST_EDCA_TO_8822B))
+#define BIT_GET_BE_FAST_EDCA_TO_8822B(x) \
+ (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8822B) & \
+ BIT_MASK_BE_FAST_EDCA_TO_8822B)
+#define BIT_SET_BE_FAST_EDCA_TO_8822B(x, v) \
+ (BIT_CLEAR_BE_FAST_EDCA_TO_8822B(x) | BIT_BE_FAST_EDCA_TO_8822B(v))
#define BIT_BE_THRESHOLD_SEL_8822B BIT(7)
#define BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822B 0
#define BIT_MASK_BE_FAST_EDCA_PKT_TH_8822B 0x7f
-#define BIT_BE_FAST_EDCA_PKT_TH_8822B(x) (((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8822B) << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822B)
-#define BIT_GET_BE_FAST_EDCA_PKT_TH_8822B(x) (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822B) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8822B)
-
+#define BIT_BE_FAST_EDCA_PKT_TH_8822B(x) \
+ (((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8822B) \
+ << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822B)
+#define BITS_BE_FAST_EDCA_PKT_TH_8822B \
+ (BIT_MASK_BE_FAST_EDCA_PKT_TH_8822B \
+ << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822B)
+#define BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8822B(x) \
+ ((x) & (~BITS_BE_FAST_EDCA_PKT_TH_8822B))
+#define BIT_GET_BE_FAST_EDCA_PKT_TH_8822B(x) \
+ (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822B) & \
+ BIT_MASK_BE_FAST_EDCA_PKT_TH_8822B)
+#define BIT_SET_BE_FAST_EDCA_PKT_TH_8822B(x, v) \
+ (BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8822B(x) | \
+ BIT_BE_FAST_EDCA_PKT_TH_8822B(v))
/* 2 REG_MACID_DROP0_8822B */
#define BIT_SHIFT_MACID31_0_DROP_8822B 0
#define BIT_MASK_MACID31_0_DROP_8822B 0xffffffffL
-#define BIT_MACID31_0_DROP_8822B(x) (((x) & BIT_MASK_MACID31_0_DROP_8822B) << BIT_SHIFT_MACID31_0_DROP_8822B)
-#define BIT_GET_MACID31_0_DROP_8822B(x) (((x) >> BIT_SHIFT_MACID31_0_DROP_8822B) & BIT_MASK_MACID31_0_DROP_8822B)
-
+#define BIT_MACID31_0_DROP_8822B(x) \
+ (((x) & BIT_MASK_MACID31_0_DROP_8822B) \
+ << BIT_SHIFT_MACID31_0_DROP_8822B)
+#define BITS_MACID31_0_DROP_8822B \
+ (BIT_MASK_MACID31_0_DROP_8822B << BIT_SHIFT_MACID31_0_DROP_8822B)
+#define BIT_CLEAR_MACID31_0_DROP_8822B(x) ((x) & (~BITS_MACID31_0_DROP_8822B))
+#define BIT_GET_MACID31_0_DROP_8822B(x) \
+ (((x) >> BIT_SHIFT_MACID31_0_DROP_8822B) & \
+ BIT_MASK_MACID31_0_DROP_8822B)
+#define BIT_SET_MACID31_0_DROP_8822B(x, v) \
+ (BIT_CLEAR_MACID31_0_DROP_8822B(x) | BIT_MACID31_0_DROP_8822B(v))
/* 2 REG_MACID_DROP1_8822B */
#define BIT_SHIFT_MACID63_32_DROP_8822B 0
#define BIT_MASK_MACID63_32_DROP_8822B 0xffffffffL
-#define BIT_MACID63_32_DROP_8822B(x) (((x) & BIT_MASK_MACID63_32_DROP_8822B) << BIT_SHIFT_MACID63_32_DROP_8822B)
-#define BIT_GET_MACID63_32_DROP_8822B(x) (((x) >> BIT_SHIFT_MACID63_32_DROP_8822B) & BIT_MASK_MACID63_32_DROP_8822B)
-
+#define BIT_MACID63_32_DROP_8822B(x) \
+ (((x) & BIT_MASK_MACID63_32_DROP_8822B) \
+ << BIT_SHIFT_MACID63_32_DROP_8822B)
+#define BITS_MACID63_32_DROP_8822B \
+ (BIT_MASK_MACID63_32_DROP_8822B << BIT_SHIFT_MACID63_32_DROP_8822B)
+#define BIT_CLEAR_MACID63_32_DROP_8822B(x) ((x) & (~BITS_MACID63_32_DROP_8822B))
+#define BIT_GET_MACID63_32_DROP_8822B(x) \
+ (((x) >> BIT_SHIFT_MACID63_32_DROP_8822B) & \
+ BIT_MASK_MACID63_32_DROP_8822B)
+#define BIT_SET_MACID63_32_DROP_8822B(x, v) \
+ (BIT_CLEAR_MACID63_32_DROP_8822B(x) | BIT_MACID63_32_DROP_8822B(v))
/* 2 REG_MACID_DROP2_8822B */
#define BIT_SHIFT_MACID95_64_DROP_8822B 0
#define BIT_MASK_MACID95_64_DROP_8822B 0xffffffffL
-#define BIT_MACID95_64_DROP_8822B(x) (((x) & BIT_MASK_MACID95_64_DROP_8822B) << BIT_SHIFT_MACID95_64_DROP_8822B)
-#define BIT_GET_MACID95_64_DROP_8822B(x) (((x) >> BIT_SHIFT_MACID95_64_DROP_8822B) & BIT_MASK_MACID95_64_DROP_8822B)
-
+#define BIT_MACID95_64_DROP_8822B(x) \
+ (((x) & BIT_MASK_MACID95_64_DROP_8822B) \
+ << BIT_SHIFT_MACID95_64_DROP_8822B)
+#define BITS_MACID95_64_DROP_8822B \
+ (BIT_MASK_MACID95_64_DROP_8822B << BIT_SHIFT_MACID95_64_DROP_8822B)
+#define BIT_CLEAR_MACID95_64_DROP_8822B(x) ((x) & (~BITS_MACID95_64_DROP_8822B))
+#define BIT_GET_MACID95_64_DROP_8822B(x) \
+ (((x) >> BIT_SHIFT_MACID95_64_DROP_8822B) & \
+ BIT_MASK_MACID95_64_DROP_8822B)
+#define BIT_SET_MACID95_64_DROP_8822B(x, v) \
+ (BIT_CLEAR_MACID95_64_DROP_8822B(x) | BIT_MACID95_64_DROP_8822B(v))
/* 2 REG_MACID_DROP3_8822B */
#define BIT_SHIFT_MACID127_96_DROP_8822B 0
#define BIT_MASK_MACID127_96_DROP_8822B 0xffffffffL
-#define BIT_MACID127_96_DROP_8822B(x) (((x) & BIT_MASK_MACID127_96_DROP_8822B) << BIT_SHIFT_MACID127_96_DROP_8822B)
-#define BIT_GET_MACID127_96_DROP_8822B(x) (((x) >> BIT_SHIFT_MACID127_96_DROP_8822B) & BIT_MASK_MACID127_96_DROP_8822B)
-
+#define BIT_MACID127_96_DROP_8822B(x) \
+ (((x) & BIT_MASK_MACID127_96_DROP_8822B) \
+ << BIT_SHIFT_MACID127_96_DROP_8822B)
+#define BITS_MACID127_96_DROP_8822B \
+ (BIT_MASK_MACID127_96_DROP_8822B << BIT_SHIFT_MACID127_96_DROP_8822B)
+#define BIT_CLEAR_MACID127_96_DROP_8822B(x) \
+ ((x) & (~BITS_MACID127_96_DROP_8822B))
+#define BIT_GET_MACID127_96_DROP_8822B(x) \
+ (((x) >> BIT_SHIFT_MACID127_96_DROP_8822B) & \
+ BIT_MASK_MACID127_96_DROP_8822B)
+#define BIT_SET_MACID127_96_DROP_8822B(x, v) \
+ (BIT_CLEAR_MACID127_96_DROP_8822B(x) | BIT_MACID127_96_DROP_8822B(v))
/* 2 REG_R_MACID_RELEASE_SUCCESS_0_8822B */
#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822B 0
#define BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822B 0xffffffffL
-#define BIT_R_MACID_RELEASE_SUCCESS_0_8822B(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822B) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822B)
-#define BIT_GET_R_MACID_RELEASE_SUCCESS_0_8822B(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822B) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822B)
-
+#define BIT_R_MACID_RELEASE_SUCCESS_0_8822B(x) \
+ (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822B) \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822B)
+#define BITS_R_MACID_RELEASE_SUCCESS_0_8822B \
+ (BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822B \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822B)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8822B(x) \
+ ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_0_8822B))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_0_8822B(x) \
+ (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822B) & \
+ BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822B)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_0_8822B(x, v) \
+ (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8822B(x) | \
+ BIT_R_MACID_RELEASE_SUCCESS_0_8822B(v))
/* 2 REG_R_MACID_RELEASE_SUCCESS_1_8822B */
#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822B 0
#define BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822B 0xffffffffL
-#define BIT_R_MACID_RELEASE_SUCCESS_1_8822B(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822B) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822B)
-#define BIT_GET_R_MACID_RELEASE_SUCCESS_1_8822B(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822B) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822B)
-
+#define BIT_R_MACID_RELEASE_SUCCESS_1_8822B(x) \
+ (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822B) \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822B)
+#define BITS_R_MACID_RELEASE_SUCCESS_1_8822B \
+ (BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822B \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822B)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8822B(x) \
+ ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_1_8822B))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_1_8822B(x) \
+ (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822B) & \
+ BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822B)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_1_8822B(x, v) \
+ (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8822B(x) | \
+ BIT_R_MACID_RELEASE_SUCCESS_1_8822B(v))
/* 2 REG_R_MACID_RELEASE_SUCCESS_2_8822B */
#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822B 0
#define BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822B 0xffffffffL
-#define BIT_R_MACID_RELEASE_SUCCESS_2_8822B(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822B) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822B)
-#define BIT_GET_R_MACID_RELEASE_SUCCESS_2_8822B(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822B) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822B)
-
+#define BIT_R_MACID_RELEASE_SUCCESS_2_8822B(x) \
+ (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822B) \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822B)
+#define BITS_R_MACID_RELEASE_SUCCESS_2_8822B \
+ (BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822B \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822B)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8822B(x) \
+ ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_2_8822B))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_2_8822B(x) \
+ (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822B) & \
+ BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822B)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_2_8822B(x, v) \
+ (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8822B(x) | \
+ BIT_R_MACID_RELEASE_SUCCESS_2_8822B(v))
/* 2 REG_R_MACID_RELEASE_SUCCESS_3_8822B */
#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822B 0
#define BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822B 0xffffffffL
-#define BIT_R_MACID_RELEASE_SUCCESS_3_8822B(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822B) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822B)
-#define BIT_GET_R_MACID_RELEASE_SUCCESS_3_8822B(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822B) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822B)
-
+#define BIT_R_MACID_RELEASE_SUCCESS_3_8822B(x) \
+ (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822B) \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822B)
+#define BITS_R_MACID_RELEASE_SUCCESS_3_8822B \
+ (BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822B \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822B)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8822B(x) \
+ ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_3_8822B))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_3_8822B(x) \
+ (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822B) & \
+ BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822B)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_3_8822B(x, v) \
+ (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8822B(x) | \
+ BIT_R_MACID_RELEASE_SUCCESS_3_8822B(v))
/* 2 REG_MGG_FIFO_CRTL_8822B */
#define BIT_R_MGG_FIFO_EN_8822B BIT(31)
#define BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8822B 28
#define BIT_MASK_R_MGG_FIFO_PG_SIZE_8822B 0x7
-#define BIT_R_MGG_FIFO_PG_SIZE_8822B(x) (((x) & BIT_MASK_R_MGG_FIFO_PG_SIZE_8822B) << BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8822B)
-#define BIT_GET_R_MGG_FIFO_PG_SIZE_8822B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8822B) & BIT_MASK_R_MGG_FIFO_PG_SIZE_8822B)
-
+#define BIT_R_MGG_FIFO_PG_SIZE_8822B(x) \
+ (((x) & BIT_MASK_R_MGG_FIFO_PG_SIZE_8822B) \
+ << BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8822B)
+#define BITS_R_MGG_FIFO_PG_SIZE_8822B \
+ (BIT_MASK_R_MGG_FIFO_PG_SIZE_8822B \
+ << BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8822B)
+#define BIT_CLEAR_R_MGG_FIFO_PG_SIZE_8822B(x) \
+ ((x) & (~BITS_R_MGG_FIFO_PG_SIZE_8822B))
+#define BIT_GET_R_MGG_FIFO_PG_SIZE_8822B(x) \
+ (((x) >> BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8822B) & \
+ BIT_MASK_R_MGG_FIFO_PG_SIZE_8822B)
+#define BIT_SET_R_MGG_FIFO_PG_SIZE_8822B(x, v) \
+ (BIT_CLEAR_R_MGG_FIFO_PG_SIZE_8822B(x) | \
+ BIT_R_MGG_FIFO_PG_SIZE_8822B(v))
#define BIT_SHIFT_R_MGG_FIFO_START_PG_8822B 16
#define BIT_MASK_R_MGG_FIFO_START_PG_8822B 0xfff
-#define BIT_R_MGG_FIFO_START_PG_8822B(x) (((x) & BIT_MASK_R_MGG_FIFO_START_PG_8822B) << BIT_SHIFT_R_MGG_FIFO_START_PG_8822B)
-#define BIT_GET_R_MGG_FIFO_START_PG_8822B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_START_PG_8822B) & BIT_MASK_R_MGG_FIFO_START_PG_8822B)
-
+#define BIT_R_MGG_FIFO_START_PG_8822B(x) \
+ (((x) & BIT_MASK_R_MGG_FIFO_START_PG_8822B) \
+ << BIT_SHIFT_R_MGG_FIFO_START_PG_8822B)
+#define BITS_R_MGG_FIFO_START_PG_8822B \
+ (BIT_MASK_R_MGG_FIFO_START_PG_8822B \
+ << BIT_SHIFT_R_MGG_FIFO_START_PG_8822B)
+#define BIT_CLEAR_R_MGG_FIFO_START_PG_8822B(x) \
+ ((x) & (~BITS_R_MGG_FIFO_START_PG_8822B))
+#define BIT_GET_R_MGG_FIFO_START_PG_8822B(x) \
+ (((x) >> BIT_SHIFT_R_MGG_FIFO_START_PG_8822B) & \
+ BIT_MASK_R_MGG_FIFO_START_PG_8822B)
+#define BIT_SET_R_MGG_FIFO_START_PG_8822B(x, v) \
+ (BIT_CLEAR_R_MGG_FIFO_START_PG_8822B(x) | \
+ BIT_R_MGG_FIFO_START_PG_8822B(v))
#define BIT_SHIFT_R_MGG_FIFO_SIZE_8822B 14
#define BIT_MASK_R_MGG_FIFO_SIZE_8822B 0x3
-#define BIT_R_MGG_FIFO_SIZE_8822B(x) (((x) & BIT_MASK_R_MGG_FIFO_SIZE_8822B) << BIT_SHIFT_R_MGG_FIFO_SIZE_8822B)
-#define BIT_GET_R_MGG_FIFO_SIZE_8822B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_SIZE_8822B) & BIT_MASK_R_MGG_FIFO_SIZE_8822B)
+#define BIT_R_MGG_FIFO_SIZE_8822B(x) \
+ (((x) & BIT_MASK_R_MGG_FIFO_SIZE_8822B) \
+ << BIT_SHIFT_R_MGG_FIFO_SIZE_8822B)
+#define BITS_R_MGG_FIFO_SIZE_8822B \
+ (BIT_MASK_R_MGG_FIFO_SIZE_8822B << BIT_SHIFT_R_MGG_FIFO_SIZE_8822B)
+#define BIT_CLEAR_R_MGG_FIFO_SIZE_8822B(x) ((x) & (~BITS_R_MGG_FIFO_SIZE_8822B))
+#define BIT_GET_R_MGG_FIFO_SIZE_8822B(x) \
+ (((x) >> BIT_SHIFT_R_MGG_FIFO_SIZE_8822B) & \
+ BIT_MASK_R_MGG_FIFO_SIZE_8822B)
+#define BIT_SET_R_MGG_FIFO_SIZE_8822B(x, v) \
+ (BIT_CLEAR_R_MGG_FIFO_SIZE_8822B(x) | BIT_R_MGG_FIFO_SIZE_8822B(v))
#define BIT_R_MGG_FIFO_PAUSE_8822B BIT(13)
#define BIT_SHIFT_R_MGG_FIFO_RPTR_8822B 8
#define BIT_MASK_R_MGG_FIFO_RPTR_8822B 0x1f
-#define BIT_R_MGG_FIFO_RPTR_8822B(x) (((x) & BIT_MASK_R_MGG_FIFO_RPTR_8822B) << BIT_SHIFT_R_MGG_FIFO_RPTR_8822B)
-#define BIT_GET_R_MGG_FIFO_RPTR_8822B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_RPTR_8822B) & BIT_MASK_R_MGG_FIFO_RPTR_8822B)
+#define BIT_R_MGG_FIFO_RPTR_8822B(x) \
+ (((x) & BIT_MASK_R_MGG_FIFO_RPTR_8822B) \
+ << BIT_SHIFT_R_MGG_FIFO_RPTR_8822B)
+#define BITS_R_MGG_FIFO_RPTR_8822B \
+ (BIT_MASK_R_MGG_FIFO_RPTR_8822B << BIT_SHIFT_R_MGG_FIFO_RPTR_8822B)
+#define BIT_CLEAR_R_MGG_FIFO_RPTR_8822B(x) ((x) & (~BITS_R_MGG_FIFO_RPTR_8822B))
+#define BIT_GET_R_MGG_FIFO_RPTR_8822B(x) \
+ (((x) >> BIT_SHIFT_R_MGG_FIFO_RPTR_8822B) & \
+ BIT_MASK_R_MGG_FIFO_RPTR_8822B)
+#define BIT_SET_R_MGG_FIFO_RPTR_8822B(x, v) \
+ (BIT_CLEAR_R_MGG_FIFO_RPTR_8822B(x) | BIT_R_MGG_FIFO_RPTR_8822B(v))
#define BIT_R_MGG_FIFO_OV_8822B BIT(7)
#define BIT_R_MGG_FIFO_WPTR_ERROR_8822B BIT(6)
@@ -6204,62 +10716,184 @@
#define BIT_SHIFT_R_MGG_FIFO_WPTR_8822B 0
#define BIT_MASK_R_MGG_FIFO_WPTR_8822B 0x1f
-#define BIT_R_MGG_FIFO_WPTR_8822B(x) (((x) & BIT_MASK_R_MGG_FIFO_WPTR_8822B) << BIT_SHIFT_R_MGG_FIFO_WPTR_8822B)
-#define BIT_GET_R_MGG_FIFO_WPTR_8822B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_WPTR_8822B) & BIT_MASK_R_MGG_FIFO_WPTR_8822B)
-
+#define BIT_R_MGG_FIFO_WPTR_8822B(x) \
+ (((x) & BIT_MASK_R_MGG_FIFO_WPTR_8822B) \
+ << BIT_SHIFT_R_MGG_FIFO_WPTR_8822B)
+#define BITS_R_MGG_FIFO_WPTR_8822B \
+ (BIT_MASK_R_MGG_FIFO_WPTR_8822B << BIT_SHIFT_R_MGG_FIFO_WPTR_8822B)
+#define BIT_CLEAR_R_MGG_FIFO_WPTR_8822B(x) ((x) & (~BITS_R_MGG_FIFO_WPTR_8822B))
+#define BIT_GET_R_MGG_FIFO_WPTR_8822B(x) \
+ (((x) >> BIT_SHIFT_R_MGG_FIFO_WPTR_8822B) & \
+ BIT_MASK_R_MGG_FIFO_WPTR_8822B)
+#define BIT_SET_R_MGG_FIFO_WPTR_8822B(x, v) \
+ (BIT_CLEAR_R_MGG_FIFO_WPTR_8822B(x) | BIT_R_MGG_FIFO_WPTR_8822B(v))
/* 2 REG_MGG_FIFO_INT_8822B */
#define BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8822B 16
#define BIT_MASK_R_MGG_FIFO_INT_FLAG_8822B 0xffff
-#define BIT_R_MGG_FIFO_INT_FLAG_8822B(x) (((x) & BIT_MASK_R_MGG_FIFO_INT_FLAG_8822B) << BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8822B)
-#define BIT_GET_R_MGG_FIFO_INT_FLAG_8822B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8822B) & BIT_MASK_R_MGG_FIFO_INT_FLAG_8822B)
-
+#define BIT_R_MGG_FIFO_INT_FLAG_8822B(x) \
+ (((x) & BIT_MASK_R_MGG_FIFO_INT_FLAG_8822B) \
+ << BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8822B)
+#define BITS_R_MGG_FIFO_INT_FLAG_8822B \
+ (BIT_MASK_R_MGG_FIFO_INT_FLAG_8822B \
+ << BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8822B)
+#define BIT_CLEAR_R_MGG_FIFO_INT_FLAG_8822B(x) \
+ ((x) & (~BITS_R_MGG_FIFO_INT_FLAG_8822B))
+#define BIT_GET_R_MGG_FIFO_INT_FLAG_8822B(x) \
+ (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8822B) & \
+ BIT_MASK_R_MGG_FIFO_INT_FLAG_8822B)
+#define BIT_SET_R_MGG_FIFO_INT_FLAG_8822B(x, v) \
+ (BIT_CLEAR_R_MGG_FIFO_INT_FLAG_8822B(x) | \
+ BIT_R_MGG_FIFO_INT_FLAG_8822B(v))
#define BIT_SHIFT_R_MGG_FIFO_INT_MASK_8822B 0
#define BIT_MASK_R_MGG_FIFO_INT_MASK_8822B 0xffff
-#define BIT_R_MGG_FIFO_INT_MASK_8822B(x) (((x) & BIT_MASK_R_MGG_FIFO_INT_MASK_8822B) << BIT_SHIFT_R_MGG_FIFO_INT_MASK_8822B)
-#define BIT_GET_R_MGG_FIFO_INT_MASK_8822B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_MASK_8822B) & BIT_MASK_R_MGG_FIFO_INT_MASK_8822B)
-
+#define BIT_R_MGG_FIFO_INT_MASK_8822B(x) \
+ (((x) & BIT_MASK_R_MGG_FIFO_INT_MASK_8822B) \
+ << BIT_SHIFT_R_MGG_FIFO_INT_MASK_8822B)
+#define BITS_R_MGG_FIFO_INT_MASK_8822B \
+ (BIT_MASK_R_MGG_FIFO_INT_MASK_8822B \
+ << BIT_SHIFT_R_MGG_FIFO_INT_MASK_8822B)
+#define BIT_CLEAR_R_MGG_FIFO_INT_MASK_8822B(x) \
+ ((x) & (~BITS_R_MGG_FIFO_INT_MASK_8822B))
+#define BIT_GET_R_MGG_FIFO_INT_MASK_8822B(x) \
+ (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_MASK_8822B) & \
+ BIT_MASK_R_MGG_FIFO_INT_MASK_8822B)
+#define BIT_SET_R_MGG_FIFO_INT_MASK_8822B(x, v) \
+ (BIT_CLEAR_R_MGG_FIFO_INT_MASK_8822B(x) | \
+ BIT_R_MGG_FIFO_INT_MASK_8822B(v))
/* 2 REG_MGG_FIFO_LIFETIME_8822B */
#define BIT_SHIFT_R_MGG_FIFO_LIFETIME_8822B 16
#define BIT_MASK_R_MGG_FIFO_LIFETIME_8822B 0xffff
-#define BIT_R_MGG_FIFO_LIFETIME_8822B(x) (((x) & BIT_MASK_R_MGG_FIFO_LIFETIME_8822B) << BIT_SHIFT_R_MGG_FIFO_LIFETIME_8822B)
-#define BIT_GET_R_MGG_FIFO_LIFETIME_8822B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_LIFETIME_8822B) & BIT_MASK_R_MGG_FIFO_LIFETIME_8822B)
-
+#define BIT_R_MGG_FIFO_LIFETIME_8822B(x) \
+ (((x) & BIT_MASK_R_MGG_FIFO_LIFETIME_8822B) \
+ << BIT_SHIFT_R_MGG_FIFO_LIFETIME_8822B)
+#define BITS_R_MGG_FIFO_LIFETIME_8822B \
+ (BIT_MASK_R_MGG_FIFO_LIFETIME_8822B \
+ << BIT_SHIFT_R_MGG_FIFO_LIFETIME_8822B)
+#define BIT_CLEAR_R_MGG_FIFO_LIFETIME_8822B(x) \
+ ((x) & (~BITS_R_MGG_FIFO_LIFETIME_8822B))
+#define BIT_GET_R_MGG_FIFO_LIFETIME_8822B(x) \
+ (((x) >> BIT_SHIFT_R_MGG_FIFO_LIFETIME_8822B) & \
+ BIT_MASK_R_MGG_FIFO_LIFETIME_8822B)
+#define BIT_SET_R_MGG_FIFO_LIFETIME_8822B(x, v) \
+ (BIT_CLEAR_R_MGG_FIFO_LIFETIME_8822B(x) | \
+ BIT_R_MGG_FIFO_LIFETIME_8822B(v))
#define BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8822B 0
#define BIT_MASK_R_MGG_FIFO_VALID_MAP_8822B 0xffff
-#define BIT_R_MGG_FIFO_VALID_MAP_8822B(x) (((x) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8822B) << BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8822B)
-#define BIT_GET_R_MGG_FIFO_VALID_MAP_8822B(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8822B) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8822B)
-
+#define BIT_R_MGG_FIFO_VALID_MAP_8822B(x) \
+ (((x) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8822B) \
+ << BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8822B)
+#define BITS_R_MGG_FIFO_VALID_MAP_8822B \
+ (BIT_MASK_R_MGG_FIFO_VALID_MAP_8822B \
+ << BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8822B)
+#define BIT_CLEAR_R_MGG_FIFO_VALID_MAP_8822B(x) \
+ ((x) & (~BITS_R_MGG_FIFO_VALID_MAP_8822B))
+#define BIT_GET_R_MGG_FIFO_VALID_MAP_8822B(x) \
+ (((x) >> BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8822B) & \
+ BIT_MASK_R_MGG_FIFO_VALID_MAP_8822B)
+#define BIT_SET_R_MGG_FIFO_VALID_MAP_8822B(x, v) \
+ (BIT_CLEAR_R_MGG_FIFO_VALID_MAP_8822B(x) | \
+ BIT_R_MGG_FIFO_VALID_MAP_8822B(v))
/* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B */
#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B 0
#define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B 0x7f
-#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B)
-#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B)
+#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B(x) \
+ (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B) \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B)
+#define BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B \
+ (BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B(x) \
+ ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B(x) \
+ (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B) & \
+ BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B(x, v) \
+ (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B(x) | \
+ BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B(v))
+
+/* 2 REG_SHCUT_SETTING_8822B */
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
-/* 2 REG_MACID_SHCUT_OFFSET_8822B */
+/* 2 REG_NOT_VALID_8822B */
-#define BIT_SHIFT_MACID_SHCUT_OFFSET_V1_8822B 0
-#define BIT_MASK_MACID_SHCUT_OFFSET_V1_8822B 0xff
-#define BIT_MACID_SHCUT_OFFSET_V1_8822B(x) (((x) & BIT_MASK_MACID_SHCUT_OFFSET_V1_8822B) << BIT_SHIFT_MACID_SHCUT_OFFSET_V1_8822B)
-#define BIT_GET_MACID_SHCUT_OFFSET_V1_8822B(x) (((x) >> BIT_SHIFT_MACID_SHCUT_OFFSET_V1_8822B) & BIT_MASK_MACID_SHCUT_OFFSET_V1_8822B)
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_SHCUT_LLC_ETH_TYPE0_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_SHCUT_LLC_ETH_TYPE1_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_SHCUT_LLC_OUI0_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_SHCUT_LLC_OUI1_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_SHCUT_LLC_OUI2_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_SHCUT_LLC_OUI3_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
/* 2 REG_MU_TX_CTL_8822B */
#define BIT_R_EN_REVERS_GTAB_8822B BIT(6)
#define BIT_SHIFT_R_MU_TABLE_VALID_8822B 0
#define BIT_MASK_R_MU_TABLE_VALID_8822B 0x3f
-#define BIT_R_MU_TABLE_VALID_8822B(x) (((x) & BIT_MASK_R_MU_TABLE_VALID_8822B) << BIT_SHIFT_R_MU_TABLE_VALID_8822B)
-#define BIT_GET_R_MU_TABLE_VALID_8822B(x) (((x) >> BIT_SHIFT_R_MU_TABLE_VALID_8822B) & BIT_MASK_R_MU_TABLE_VALID_8822B)
-
+#define BIT_R_MU_TABLE_VALID_8822B(x) \
+ (((x) & BIT_MASK_R_MU_TABLE_VALID_8822B) \
+ << BIT_SHIFT_R_MU_TABLE_VALID_8822B)
+#define BITS_R_MU_TABLE_VALID_8822B \
+ (BIT_MASK_R_MU_TABLE_VALID_8822B << BIT_SHIFT_R_MU_TABLE_VALID_8822B)
+#define BIT_CLEAR_R_MU_TABLE_VALID_8822B(x) \
+ ((x) & (~BITS_R_MU_TABLE_VALID_8822B))
+#define BIT_GET_R_MU_TABLE_VALID_8822B(x) \
+ (((x) >> BIT_SHIFT_R_MU_TABLE_VALID_8822B) & \
+ BIT_MASK_R_MU_TABLE_VALID_8822B)
+#define BIT_SET_R_MU_TABLE_VALID_8822B(x, v) \
+ (BIT_CLEAR_R_MU_TABLE_VALID_8822B(x) | BIT_R_MU_TABLE_VALID_8822B(v))
/* 2 REG_MU_STA_GID_VLD_8822B */
@@ -6267,15 +10901,37 @@
#define BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B 0
#define BIT_MASK_R_MU_STA_GTAB_VALID_8822B 0xffffffffL
-#define BIT_R_MU_STA_GTAB_VALID_8822B(x) (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8822B) << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B)
-#define BIT_GET_R_MU_STA_GTAB_VALID_8822B(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) & BIT_MASK_R_MU_STA_GTAB_VALID_8822B)
-
+#define BIT_R_MU_STA_GTAB_VALID_8822B(x) \
+ (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8822B) \
+ << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B)
+#define BITS_R_MU_STA_GTAB_VALID_8822B \
+ (BIT_MASK_R_MU_STA_GTAB_VALID_8822B \
+ << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B)
+#define BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x) \
+ ((x) & (~BITS_R_MU_STA_GTAB_VALID_8822B))
+#define BIT_GET_R_MU_STA_GTAB_VALID_8822B(x) \
+ (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) & \
+ BIT_MASK_R_MU_STA_GTAB_VALID_8822B)
+#define BIT_SET_R_MU_STA_GTAB_VALID_8822B(x, v) \
+ (BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x) | \
+ BIT_R_MU_STA_GTAB_VALID_8822B(v))
#define BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B 0
#define BIT_MASK_R_MU_STA_GTAB_VALID_8822B 0xffffffffL
-#define BIT_R_MU_STA_GTAB_VALID_8822B(x) (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8822B) << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B)
-#define BIT_GET_R_MU_STA_GTAB_VALID_8822B(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) & BIT_MASK_R_MU_STA_GTAB_VALID_8822B)
-
+#define BIT_R_MU_STA_GTAB_VALID_8822B(x) \
+ (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8822B) \
+ << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B)
+#define BITS_R_MU_STA_GTAB_VALID_8822B \
+ (BIT_MASK_R_MU_STA_GTAB_VALID_8822B \
+ << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B)
+#define BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x) \
+ ((x) & (~BITS_R_MU_STA_GTAB_VALID_8822B))
+#define BIT_GET_R_MU_STA_GTAB_VALID_8822B(x) \
+ (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) & \
+ BIT_MASK_R_MU_STA_GTAB_VALID_8822B)
+#define BIT_SET_R_MU_STA_GTAB_VALID_8822B(x, v) \
+ (BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x) | \
+ BIT_R_MU_STA_GTAB_VALID_8822B(v))
/* 2 REG_MU_STA_USER_POS_INFO_8822B */
@@ -6283,30 +10939,185 @@
#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B 0
#define BIT_MASK_R_MU_STA_GTAB_POSITION_8822B 0xffffffffffffffffL
-#define BIT_R_MU_STA_GTAB_POSITION_8822B(x) (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8822B) << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B)
-#define BIT_GET_R_MU_STA_GTAB_POSITION_8822B(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) & BIT_MASK_R_MU_STA_GTAB_POSITION_8822B)
+#define BIT_R_MU_STA_GTAB_POSITION_8822B(x) \
+ (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8822B) \
+ << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B)
+#define BITS_R_MU_STA_GTAB_POSITION_8822B \
+ (BIT_MASK_R_MU_STA_GTAB_POSITION_8822B \
+ << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B)
+#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x) \
+ ((x) & (~BITS_R_MU_STA_GTAB_POSITION_8822B))
+#define BIT_GET_R_MU_STA_GTAB_POSITION_8822B(x) \
+ (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) & \
+ BIT_MASK_R_MU_STA_GTAB_POSITION_8822B)
+#define BIT_SET_R_MU_STA_GTAB_POSITION_8822B(x, v) \
+ (BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x) | \
+ BIT_R_MU_STA_GTAB_POSITION_8822B(v))
+
+#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B 0
+#define BIT_MASK_R_MU_STA_GTAB_POSITION_8822B 0xffffffffffffffffL
+#define BIT_R_MU_STA_GTAB_POSITION_8822B(x) \
+ (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8822B) \
+ << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B)
+#define BITS_R_MU_STA_GTAB_POSITION_8822B \
+ (BIT_MASK_R_MU_STA_GTAB_POSITION_8822B \
+ << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B)
+#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x) \
+ ((x) & (~BITS_R_MU_STA_GTAB_POSITION_8822B))
+#define BIT_GET_R_MU_STA_GTAB_POSITION_8822B(x) \
+ (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) & \
+ BIT_MASK_R_MU_STA_GTAB_POSITION_8822B)
+#define BIT_SET_R_MU_STA_GTAB_POSITION_8822B(x, v) \
+ (BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x) | \
+ BIT_R_MU_STA_GTAB_POSITION_8822B(v))
+
+/* 2 REG_MU_TRX_DBG_CNT_8822B */
+#define BIT_MU_DNGCNT_RST_8822B BIT(20)
+
+#define BIT_SHIFT_MU_DBGCNT_SEL_8822B 16
+#define BIT_MASK_MU_DBGCNT_SEL_8822B 0xf
+#define BIT_MU_DBGCNT_SEL_8822B(x) \
+ (((x) & BIT_MASK_MU_DBGCNT_SEL_8822B) << BIT_SHIFT_MU_DBGCNT_SEL_8822B)
+#define BITS_MU_DBGCNT_SEL_8822B \
+ (BIT_MASK_MU_DBGCNT_SEL_8822B << BIT_SHIFT_MU_DBGCNT_SEL_8822B)
+#define BIT_CLEAR_MU_DBGCNT_SEL_8822B(x) ((x) & (~BITS_MU_DBGCNT_SEL_8822B))
+#define BIT_GET_MU_DBGCNT_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_MU_DBGCNT_SEL_8822B) & BIT_MASK_MU_DBGCNT_SEL_8822B)
+#define BIT_SET_MU_DBGCNT_SEL_8822B(x, v) \
+ (BIT_CLEAR_MU_DBGCNT_SEL_8822B(x) | BIT_MU_DBGCNT_SEL_8822B(v))
+
+#define BIT_SHIFT_MU_DNGCNT_8822B 0
+#define BIT_MASK_MU_DNGCNT_8822B 0xffff
+#define BIT_MU_DNGCNT_8822B(x) \
+ (((x) & BIT_MASK_MU_DNGCNT_8822B) << BIT_SHIFT_MU_DNGCNT_8822B)
+#define BITS_MU_DNGCNT_8822B \
+ (BIT_MASK_MU_DNGCNT_8822B << BIT_SHIFT_MU_DNGCNT_8822B)
+#define BIT_CLEAR_MU_DNGCNT_8822B(x) ((x) & (~BITS_MU_DNGCNT_8822B))
+#define BIT_GET_MU_DNGCNT_8822B(x) \
+ (((x) >> BIT_SHIFT_MU_DNGCNT_8822B) & BIT_MASK_MU_DNGCNT_8822B)
+#define BIT_SET_MU_DNGCNT_8822B(x, v) \
+ (BIT_CLEAR_MU_DNGCNT_8822B(x) | BIT_MU_DNGCNT_8822B(v))
+
+/* 2 REG_MU_TX_CTL_8822B */
+#define BIT_R_EN_REVERS_GTAB_8822B BIT(6)
+
+#define BIT_SHIFT_R_MU_TABLE_VALID_8822B 0
+#define BIT_MASK_R_MU_TABLE_VALID_8822B 0x3f
+#define BIT_R_MU_TABLE_VALID_8822B(x) \
+ (((x) & BIT_MASK_R_MU_TABLE_VALID_8822B) \
+ << BIT_SHIFT_R_MU_TABLE_VALID_8822B)
+#define BITS_R_MU_TABLE_VALID_8822B \
+ (BIT_MASK_R_MU_TABLE_VALID_8822B << BIT_SHIFT_R_MU_TABLE_VALID_8822B)
+#define BIT_CLEAR_R_MU_TABLE_VALID_8822B(x) \
+ ((x) & (~BITS_R_MU_TABLE_VALID_8822B))
+#define BIT_GET_R_MU_TABLE_VALID_8822B(x) \
+ (((x) >> BIT_SHIFT_R_MU_TABLE_VALID_8822B) & \
+ BIT_MASK_R_MU_TABLE_VALID_8822B)
+#define BIT_SET_R_MU_TABLE_VALID_8822B(x, v) \
+ (BIT_CLEAR_R_MU_TABLE_VALID_8822B(x) | BIT_R_MU_TABLE_VALID_8822B(v))
+
+/* 2 REG_MU_STA_GID_VLD_8822B */
+
+/* 2 REG_NOT_VALID_8822B */
+
+#define BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B 0
+#define BIT_MASK_R_MU_STA_GTAB_VALID_8822B 0xffffffffL
+#define BIT_R_MU_STA_GTAB_VALID_8822B(x) \
+ (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8822B) \
+ << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B)
+#define BITS_R_MU_STA_GTAB_VALID_8822B \
+ (BIT_MASK_R_MU_STA_GTAB_VALID_8822B \
+ << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B)
+#define BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x) \
+ ((x) & (~BITS_R_MU_STA_GTAB_VALID_8822B))
+#define BIT_GET_R_MU_STA_GTAB_VALID_8822B(x) \
+ (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) & \
+ BIT_MASK_R_MU_STA_GTAB_VALID_8822B)
+#define BIT_SET_R_MU_STA_GTAB_VALID_8822B(x, v) \
+ (BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x) | \
+ BIT_R_MU_STA_GTAB_VALID_8822B(v))
+
+#define BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B 0
+#define BIT_MASK_R_MU_STA_GTAB_VALID_8822B 0xffffffffL
+#define BIT_R_MU_STA_GTAB_VALID_8822B(x) \
+ (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8822B) \
+ << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B)
+#define BITS_R_MU_STA_GTAB_VALID_8822B \
+ (BIT_MASK_R_MU_STA_GTAB_VALID_8822B \
+ << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B)
+#define BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x) \
+ ((x) & (~BITS_R_MU_STA_GTAB_VALID_8822B))
+#define BIT_GET_R_MU_STA_GTAB_VALID_8822B(x) \
+ (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8822B) & \
+ BIT_MASK_R_MU_STA_GTAB_VALID_8822B)
+#define BIT_SET_R_MU_STA_GTAB_VALID_8822B(x, v) \
+ (BIT_CLEAR_R_MU_STA_GTAB_VALID_8822B(x) | \
+ BIT_R_MU_STA_GTAB_VALID_8822B(v))
+
+/* 2 REG_MU_STA_USER_POS_INFO_8822B */
+/* 2 REG_NOT_VALID_8822B */
#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B 0
#define BIT_MASK_R_MU_STA_GTAB_POSITION_8822B 0xffffffffffffffffL
-#define BIT_R_MU_STA_GTAB_POSITION_8822B(x) (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8822B) << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B)
-#define BIT_GET_R_MU_STA_GTAB_POSITION_8822B(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) & BIT_MASK_R_MU_STA_GTAB_POSITION_8822B)
+#define BIT_R_MU_STA_GTAB_POSITION_8822B(x) \
+ (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8822B) \
+ << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B)
+#define BITS_R_MU_STA_GTAB_POSITION_8822B \
+ (BIT_MASK_R_MU_STA_GTAB_POSITION_8822B \
+ << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B)
+#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x) \
+ ((x) & (~BITS_R_MU_STA_GTAB_POSITION_8822B))
+#define BIT_GET_R_MU_STA_GTAB_POSITION_8822B(x) \
+ (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) & \
+ BIT_MASK_R_MU_STA_GTAB_POSITION_8822B)
+#define BIT_SET_R_MU_STA_GTAB_POSITION_8822B(x, v) \
+ (BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x) | \
+ BIT_R_MU_STA_GTAB_POSITION_8822B(v))
+#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B 0
+#define BIT_MASK_R_MU_STA_GTAB_POSITION_8822B 0xffffffffffffffffL
+#define BIT_R_MU_STA_GTAB_POSITION_8822B(x) \
+ (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8822B) \
+ << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B)
+#define BITS_R_MU_STA_GTAB_POSITION_8822B \
+ (BIT_MASK_R_MU_STA_GTAB_POSITION_8822B \
+ << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B)
+#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x) \
+ ((x) & (~BITS_R_MU_STA_GTAB_POSITION_8822B))
+#define BIT_GET_R_MU_STA_GTAB_POSITION_8822B(x) \
+ (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8822B) & \
+ BIT_MASK_R_MU_STA_GTAB_POSITION_8822B)
+#define BIT_SET_R_MU_STA_GTAB_POSITION_8822B(x, v) \
+ (BIT_CLEAR_R_MU_STA_GTAB_POSITION_8822B(x) | \
+ BIT_R_MU_STA_GTAB_POSITION_8822B(v))
/* 2 REG_MU_TRX_DBG_CNT_8822B */
#define BIT_MU_DNGCNT_RST_8822B BIT(20)
#define BIT_SHIFT_MU_DBGCNT_SEL_8822B 16
#define BIT_MASK_MU_DBGCNT_SEL_8822B 0xf
-#define BIT_MU_DBGCNT_SEL_8822B(x) (((x) & BIT_MASK_MU_DBGCNT_SEL_8822B) << BIT_SHIFT_MU_DBGCNT_SEL_8822B)
-#define BIT_GET_MU_DBGCNT_SEL_8822B(x) (((x) >> BIT_SHIFT_MU_DBGCNT_SEL_8822B) & BIT_MASK_MU_DBGCNT_SEL_8822B)
-
+#define BIT_MU_DBGCNT_SEL_8822B(x) \
+ (((x) & BIT_MASK_MU_DBGCNT_SEL_8822B) << BIT_SHIFT_MU_DBGCNT_SEL_8822B)
+#define BITS_MU_DBGCNT_SEL_8822B \
+ (BIT_MASK_MU_DBGCNT_SEL_8822B << BIT_SHIFT_MU_DBGCNT_SEL_8822B)
+#define BIT_CLEAR_MU_DBGCNT_SEL_8822B(x) ((x) & (~BITS_MU_DBGCNT_SEL_8822B))
+#define BIT_GET_MU_DBGCNT_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_MU_DBGCNT_SEL_8822B) & BIT_MASK_MU_DBGCNT_SEL_8822B)
+#define BIT_SET_MU_DBGCNT_SEL_8822B(x, v) \
+ (BIT_CLEAR_MU_DBGCNT_SEL_8822B(x) | BIT_MU_DBGCNT_SEL_8822B(v))
#define BIT_SHIFT_MU_DNGCNT_8822B 0
#define BIT_MASK_MU_DNGCNT_8822B 0xffff
-#define BIT_MU_DNGCNT_8822B(x) (((x) & BIT_MASK_MU_DNGCNT_8822B) << BIT_SHIFT_MU_DNGCNT_8822B)
-#define BIT_GET_MU_DNGCNT_8822B(x) (((x) >> BIT_SHIFT_MU_DNGCNT_8822B) & BIT_MASK_MU_DNGCNT_8822B)
-
+#define BIT_MU_DNGCNT_8822B(x) \
+ (((x) & BIT_MASK_MU_DNGCNT_8822B) << BIT_SHIFT_MU_DNGCNT_8822B)
+#define BITS_MU_DNGCNT_8822B \
+ (BIT_MASK_MU_DNGCNT_8822B << BIT_SHIFT_MU_DNGCNT_8822B)
+#define BIT_CLEAR_MU_DNGCNT_8822B(x) ((x) & (~BITS_MU_DNGCNT_8822B))
+#define BIT_GET_MU_DNGCNT_8822B(x) \
+ (((x) >> BIT_SHIFT_MU_DNGCNT_8822B) & BIT_MASK_MU_DNGCNT_8822B)
+#define BIT_SET_MU_DNGCNT_8822B(x, v) \
+ (BIT_CLEAR_MU_DNGCNT_8822B(x) | BIT_MU_DNGCNT_8822B(v))
/* 2 REG_NOT_VALID_8822B */
@@ -6314,21 +11125,32 @@
#define BIT_SHIFT_TXOPLIMIT_8822B 16
#define BIT_MASK_TXOPLIMIT_8822B 0x7ff
-#define BIT_TXOPLIMIT_8822B(x) (((x) & BIT_MASK_TXOPLIMIT_8822B) << BIT_SHIFT_TXOPLIMIT_8822B)
-#define BIT_GET_TXOPLIMIT_8822B(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B)
-
+#define BIT_TXOPLIMIT_8822B(x) \
+ (((x) & BIT_MASK_TXOPLIMIT_8822B) << BIT_SHIFT_TXOPLIMIT_8822B)
+#define BITS_TXOPLIMIT_8822B \
+ (BIT_MASK_TXOPLIMIT_8822B << BIT_SHIFT_TXOPLIMIT_8822B)
+#define BIT_CLEAR_TXOPLIMIT_8822B(x) ((x) & (~BITS_TXOPLIMIT_8822B))
+#define BIT_GET_TXOPLIMIT_8822B(x) \
+ (((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B)
+#define BIT_SET_TXOPLIMIT_8822B(x, v) \
+ (BIT_CLEAR_TXOPLIMIT_8822B(x) | BIT_TXOPLIMIT_8822B(v))
#define BIT_SHIFT_CW_8822B 8
#define BIT_MASK_CW_8822B 0xff
#define BIT_CW_8822B(x) (((x) & BIT_MASK_CW_8822B) << BIT_SHIFT_CW_8822B)
+#define BITS_CW_8822B (BIT_MASK_CW_8822B << BIT_SHIFT_CW_8822B)
+#define BIT_CLEAR_CW_8822B(x) ((x) & (~BITS_CW_8822B))
#define BIT_GET_CW_8822B(x) (((x) >> BIT_SHIFT_CW_8822B) & BIT_MASK_CW_8822B)
-
+#define BIT_SET_CW_8822B(x, v) (BIT_CLEAR_CW_8822B(x) | BIT_CW_8822B(v))
#define BIT_SHIFT_AIFS_8822B 0
#define BIT_MASK_AIFS_8822B 0xff
#define BIT_AIFS_8822B(x) (((x) & BIT_MASK_AIFS_8822B) << BIT_SHIFT_AIFS_8822B)
-#define BIT_GET_AIFS_8822B(x) (((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B)
-
+#define BITS_AIFS_8822B (BIT_MASK_AIFS_8822B << BIT_SHIFT_AIFS_8822B)
+#define BIT_CLEAR_AIFS_8822B(x) ((x) & (~BITS_AIFS_8822B))
+#define BIT_GET_AIFS_8822B(x) \
+ (((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B)
+#define BIT_SET_AIFS_8822B(x, v) (BIT_CLEAR_AIFS_8822B(x) | BIT_AIFS_8822B(v))
/* 2 REG_EDCA_VI_PARAM_8822B */
@@ -6336,21 +11158,32 @@
#define BIT_SHIFT_TXOPLIMIT_8822B 16
#define BIT_MASK_TXOPLIMIT_8822B 0x7ff
-#define BIT_TXOPLIMIT_8822B(x) (((x) & BIT_MASK_TXOPLIMIT_8822B) << BIT_SHIFT_TXOPLIMIT_8822B)
-#define BIT_GET_TXOPLIMIT_8822B(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B)
-
+#define BIT_TXOPLIMIT_8822B(x) \
+ (((x) & BIT_MASK_TXOPLIMIT_8822B) << BIT_SHIFT_TXOPLIMIT_8822B)
+#define BITS_TXOPLIMIT_8822B \
+ (BIT_MASK_TXOPLIMIT_8822B << BIT_SHIFT_TXOPLIMIT_8822B)
+#define BIT_CLEAR_TXOPLIMIT_8822B(x) ((x) & (~BITS_TXOPLIMIT_8822B))
+#define BIT_GET_TXOPLIMIT_8822B(x) \
+ (((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B)
+#define BIT_SET_TXOPLIMIT_8822B(x, v) \
+ (BIT_CLEAR_TXOPLIMIT_8822B(x) | BIT_TXOPLIMIT_8822B(v))
#define BIT_SHIFT_CW_8822B 8
#define BIT_MASK_CW_8822B 0xff
#define BIT_CW_8822B(x) (((x) & BIT_MASK_CW_8822B) << BIT_SHIFT_CW_8822B)
+#define BITS_CW_8822B (BIT_MASK_CW_8822B << BIT_SHIFT_CW_8822B)
+#define BIT_CLEAR_CW_8822B(x) ((x) & (~BITS_CW_8822B))
#define BIT_GET_CW_8822B(x) (((x) >> BIT_SHIFT_CW_8822B) & BIT_MASK_CW_8822B)
-
+#define BIT_SET_CW_8822B(x, v) (BIT_CLEAR_CW_8822B(x) | BIT_CW_8822B(v))
#define BIT_SHIFT_AIFS_8822B 0
#define BIT_MASK_AIFS_8822B 0xff
#define BIT_AIFS_8822B(x) (((x) & BIT_MASK_AIFS_8822B) << BIT_SHIFT_AIFS_8822B)
-#define BIT_GET_AIFS_8822B(x) (((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B)
-
+#define BITS_AIFS_8822B (BIT_MASK_AIFS_8822B << BIT_SHIFT_AIFS_8822B)
+#define BIT_CLEAR_AIFS_8822B(x) ((x) & (~BITS_AIFS_8822B))
+#define BIT_GET_AIFS_8822B(x) \
+ (((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B)
+#define BIT_SET_AIFS_8822B(x, v) (BIT_CLEAR_AIFS_8822B(x) | BIT_AIFS_8822B(v))
/* 2 REG_EDCA_BE_PARAM_8822B */
@@ -6358,21 +11191,32 @@
#define BIT_SHIFT_TXOPLIMIT_8822B 16
#define BIT_MASK_TXOPLIMIT_8822B 0x7ff
-#define BIT_TXOPLIMIT_8822B(x) (((x) & BIT_MASK_TXOPLIMIT_8822B) << BIT_SHIFT_TXOPLIMIT_8822B)
-#define BIT_GET_TXOPLIMIT_8822B(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B)
-
+#define BIT_TXOPLIMIT_8822B(x) \
+ (((x) & BIT_MASK_TXOPLIMIT_8822B) << BIT_SHIFT_TXOPLIMIT_8822B)
+#define BITS_TXOPLIMIT_8822B \
+ (BIT_MASK_TXOPLIMIT_8822B << BIT_SHIFT_TXOPLIMIT_8822B)
+#define BIT_CLEAR_TXOPLIMIT_8822B(x) ((x) & (~BITS_TXOPLIMIT_8822B))
+#define BIT_GET_TXOPLIMIT_8822B(x) \
+ (((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B)
+#define BIT_SET_TXOPLIMIT_8822B(x, v) \
+ (BIT_CLEAR_TXOPLIMIT_8822B(x) | BIT_TXOPLIMIT_8822B(v))
#define BIT_SHIFT_CW_8822B 8
#define BIT_MASK_CW_8822B 0xff
#define BIT_CW_8822B(x) (((x) & BIT_MASK_CW_8822B) << BIT_SHIFT_CW_8822B)
+#define BITS_CW_8822B (BIT_MASK_CW_8822B << BIT_SHIFT_CW_8822B)
+#define BIT_CLEAR_CW_8822B(x) ((x) & (~BITS_CW_8822B))
#define BIT_GET_CW_8822B(x) (((x) >> BIT_SHIFT_CW_8822B) & BIT_MASK_CW_8822B)
-
+#define BIT_SET_CW_8822B(x, v) (BIT_CLEAR_CW_8822B(x) | BIT_CW_8822B(v))
#define BIT_SHIFT_AIFS_8822B 0
#define BIT_MASK_AIFS_8822B 0xff
#define BIT_AIFS_8822B(x) (((x) & BIT_MASK_AIFS_8822B) << BIT_SHIFT_AIFS_8822B)
-#define BIT_GET_AIFS_8822B(x) (((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B)
-
+#define BITS_AIFS_8822B (BIT_MASK_AIFS_8822B << BIT_SHIFT_AIFS_8822B)
+#define BIT_CLEAR_AIFS_8822B(x) ((x) & (~BITS_AIFS_8822B))
+#define BIT_GET_AIFS_8822B(x) \
+ (((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B)
+#define BIT_SET_AIFS_8822B(x, v) (BIT_CLEAR_AIFS_8822B(x) | BIT_AIFS_8822B(v))
/* 2 REG_EDCA_BK_PARAM_8822B */
@@ -6380,107 +11224,186 @@
#define BIT_SHIFT_TXOPLIMIT_8822B 16
#define BIT_MASK_TXOPLIMIT_8822B 0x7ff
-#define BIT_TXOPLIMIT_8822B(x) (((x) & BIT_MASK_TXOPLIMIT_8822B) << BIT_SHIFT_TXOPLIMIT_8822B)
-#define BIT_GET_TXOPLIMIT_8822B(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B)
-
+#define BIT_TXOPLIMIT_8822B(x) \
+ (((x) & BIT_MASK_TXOPLIMIT_8822B) << BIT_SHIFT_TXOPLIMIT_8822B)
+#define BITS_TXOPLIMIT_8822B \
+ (BIT_MASK_TXOPLIMIT_8822B << BIT_SHIFT_TXOPLIMIT_8822B)
+#define BIT_CLEAR_TXOPLIMIT_8822B(x) ((x) & (~BITS_TXOPLIMIT_8822B))
+#define BIT_GET_TXOPLIMIT_8822B(x) \
+ (((x) >> BIT_SHIFT_TXOPLIMIT_8822B) & BIT_MASK_TXOPLIMIT_8822B)
+#define BIT_SET_TXOPLIMIT_8822B(x, v) \
+ (BIT_CLEAR_TXOPLIMIT_8822B(x) | BIT_TXOPLIMIT_8822B(v))
#define BIT_SHIFT_CW_8822B 8
#define BIT_MASK_CW_8822B 0xff
#define BIT_CW_8822B(x) (((x) & BIT_MASK_CW_8822B) << BIT_SHIFT_CW_8822B)
+#define BITS_CW_8822B (BIT_MASK_CW_8822B << BIT_SHIFT_CW_8822B)
+#define BIT_CLEAR_CW_8822B(x) ((x) & (~BITS_CW_8822B))
#define BIT_GET_CW_8822B(x) (((x) >> BIT_SHIFT_CW_8822B) & BIT_MASK_CW_8822B)
-
+#define BIT_SET_CW_8822B(x, v) (BIT_CLEAR_CW_8822B(x) | BIT_CW_8822B(v))
#define BIT_SHIFT_AIFS_8822B 0
#define BIT_MASK_AIFS_8822B 0xff
#define BIT_AIFS_8822B(x) (((x) & BIT_MASK_AIFS_8822B) << BIT_SHIFT_AIFS_8822B)
-#define BIT_GET_AIFS_8822B(x) (((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B)
-
+#define BITS_AIFS_8822B (BIT_MASK_AIFS_8822B << BIT_SHIFT_AIFS_8822B)
+#define BIT_CLEAR_AIFS_8822B(x) ((x) & (~BITS_AIFS_8822B))
+#define BIT_GET_AIFS_8822B(x) \
+ (((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B)
+#define BIT_SET_AIFS_8822B(x, v) (BIT_CLEAR_AIFS_8822B(x) | BIT_AIFS_8822B(v))
/* 2 REG_BCNTCFG_8822B */
#define BIT_SHIFT_BCNCW_MAX_8822B 12
#define BIT_MASK_BCNCW_MAX_8822B 0xf
-#define BIT_BCNCW_MAX_8822B(x) (((x) & BIT_MASK_BCNCW_MAX_8822B) << BIT_SHIFT_BCNCW_MAX_8822B)
-#define BIT_GET_BCNCW_MAX_8822B(x) (((x) >> BIT_SHIFT_BCNCW_MAX_8822B) & BIT_MASK_BCNCW_MAX_8822B)
-
+#define BIT_BCNCW_MAX_8822B(x) \
+ (((x) & BIT_MASK_BCNCW_MAX_8822B) << BIT_SHIFT_BCNCW_MAX_8822B)
+#define BITS_BCNCW_MAX_8822B \
+ (BIT_MASK_BCNCW_MAX_8822B << BIT_SHIFT_BCNCW_MAX_8822B)
+#define BIT_CLEAR_BCNCW_MAX_8822B(x) ((x) & (~BITS_BCNCW_MAX_8822B))
+#define BIT_GET_BCNCW_MAX_8822B(x) \
+ (((x) >> BIT_SHIFT_BCNCW_MAX_8822B) & BIT_MASK_BCNCW_MAX_8822B)
+#define BIT_SET_BCNCW_MAX_8822B(x, v) \
+ (BIT_CLEAR_BCNCW_MAX_8822B(x) | BIT_BCNCW_MAX_8822B(v))
#define BIT_SHIFT_BCNCW_MIN_8822B 8
#define BIT_MASK_BCNCW_MIN_8822B 0xf
-#define BIT_BCNCW_MIN_8822B(x) (((x) & BIT_MASK_BCNCW_MIN_8822B) << BIT_SHIFT_BCNCW_MIN_8822B)
-#define BIT_GET_BCNCW_MIN_8822B(x) (((x) >> BIT_SHIFT_BCNCW_MIN_8822B) & BIT_MASK_BCNCW_MIN_8822B)
-
+#define BIT_BCNCW_MIN_8822B(x) \
+ (((x) & BIT_MASK_BCNCW_MIN_8822B) << BIT_SHIFT_BCNCW_MIN_8822B)
+#define BITS_BCNCW_MIN_8822B \
+ (BIT_MASK_BCNCW_MIN_8822B << BIT_SHIFT_BCNCW_MIN_8822B)
+#define BIT_CLEAR_BCNCW_MIN_8822B(x) ((x) & (~BITS_BCNCW_MIN_8822B))
+#define BIT_GET_BCNCW_MIN_8822B(x) \
+ (((x) >> BIT_SHIFT_BCNCW_MIN_8822B) & BIT_MASK_BCNCW_MIN_8822B)
+#define BIT_SET_BCNCW_MIN_8822B(x, v) \
+ (BIT_CLEAR_BCNCW_MIN_8822B(x) | BIT_BCNCW_MIN_8822B(v))
#define BIT_SHIFT_BCNIFS_8822B 0
#define BIT_MASK_BCNIFS_8822B 0xff
-#define BIT_BCNIFS_8822B(x) (((x) & BIT_MASK_BCNIFS_8822B) << BIT_SHIFT_BCNIFS_8822B)
-#define BIT_GET_BCNIFS_8822B(x) (((x) >> BIT_SHIFT_BCNIFS_8822B) & BIT_MASK_BCNIFS_8822B)
-
+#define BIT_BCNIFS_8822B(x) \
+ (((x) & BIT_MASK_BCNIFS_8822B) << BIT_SHIFT_BCNIFS_8822B)
+#define BITS_BCNIFS_8822B (BIT_MASK_BCNIFS_8822B << BIT_SHIFT_BCNIFS_8822B)
+#define BIT_CLEAR_BCNIFS_8822B(x) ((x) & (~BITS_BCNIFS_8822B))
+#define BIT_GET_BCNIFS_8822B(x) \
+ (((x) >> BIT_SHIFT_BCNIFS_8822B) & BIT_MASK_BCNIFS_8822B)
+#define BIT_SET_BCNIFS_8822B(x, v) \
+ (BIT_CLEAR_BCNIFS_8822B(x) | BIT_BCNIFS_8822B(v))
/* 2 REG_PIFS_8822B */
#define BIT_SHIFT_PIFS_8822B 0
#define BIT_MASK_PIFS_8822B 0xff
#define BIT_PIFS_8822B(x) (((x) & BIT_MASK_PIFS_8822B) << BIT_SHIFT_PIFS_8822B)
-#define BIT_GET_PIFS_8822B(x) (((x) >> BIT_SHIFT_PIFS_8822B) & BIT_MASK_PIFS_8822B)
-
+#define BITS_PIFS_8822B (BIT_MASK_PIFS_8822B << BIT_SHIFT_PIFS_8822B)
+#define BIT_CLEAR_PIFS_8822B(x) ((x) & (~BITS_PIFS_8822B))
+#define BIT_GET_PIFS_8822B(x) \
+ (((x) >> BIT_SHIFT_PIFS_8822B) & BIT_MASK_PIFS_8822B)
+#define BIT_SET_PIFS_8822B(x, v) (BIT_CLEAR_PIFS_8822B(x) | BIT_PIFS_8822B(v))
/* 2 REG_RDG_PIFS_8822B */
#define BIT_SHIFT_RDG_PIFS_8822B 0
#define BIT_MASK_RDG_PIFS_8822B 0xff
-#define BIT_RDG_PIFS_8822B(x) (((x) & BIT_MASK_RDG_PIFS_8822B) << BIT_SHIFT_RDG_PIFS_8822B)
-#define BIT_GET_RDG_PIFS_8822B(x) (((x) >> BIT_SHIFT_RDG_PIFS_8822B) & BIT_MASK_RDG_PIFS_8822B)
-
+#define BIT_RDG_PIFS_8822B(x) \
+ (((x) & BIT_MASK_RDG_PIFS_8822B) << BIT_SHIFT_RDG_PIFS_8822B)
+#define BITS_RDG_PIFS_8822B \
+ (BIT_MASK_RDG_PIFS_8822B << BIT_SHIFT_RDG_PIFS_8822B)
+#define BIT_CLEAR_RDG_PIFS_8822B(x) ((x) & (~BITS_RDG_PIFS_8822B))
+#define BIT_GET_RDG_PIFS_8822B(x) \
+ (((x) >> BIT_SHIFT_RDG_PIFS_8822B) & BIT_MASK_RDG_PIFS_8822B)
+#define BIT_SET_RDG_PIFS_8822B(x, v) \
+ (BIT_CLEAR_RDG_PIFS_8822B(x) | BIT_RDG_PIFS_8822B(v))
/* 2 REG_SIFS_8822B */
#define BIT_SHIFT_SIFS_OFDM_TRX_8822B 24
#define BIT_MASK_SIFS_OFDM_TRX_8822B 0xff
-#define BIT_SIFS_OFDM_TRX_8822B(x) (((x) & BIT_MASK_SIFS_OFDM_TRX_8822B) << BIT_SHIFT_SIFS_OFDM_TRX_8822B)
-#define BIT_GET_SIFS_OFDM_TRX_8822B(x) (((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8822B) & BIT_MASK_SIFS_OFDM_TRX_8822B)
-
+#define BIT_SIFS_OFDM_TRX_8822B(x) \
+ (((x) & BIT_MASK_SIFS_OFDM_TRX_8822B) << BIT_SHIFT_SIFS_OFDM_TRX_8822B)
+#define BITS_SIFS_OFDM_TRX_8822B \
+ (BIT_MASK_SIFS_OFDM_TRX_8822B << BIT_SHIFT_SIFS_OFDM_TRX_8822B)
+#define BIT_CLEAR_SIFS_OFDM_TRX_8822B(x) ((x) & (~BITS_SIFS_OFDM_TRX_8822B))
+#define BIT_GET_SIFS_OFDM_TRX_8822B(x) \
+ (((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8822B) & BIT_MASK_SIFS_OFDM_TRX_8822B)
+#define BIT_SET_SIFS_OFDM_TRX_8822B(x, v) \
+ (BIT_CLEAR_SIFS_OFDM_TRX_8822B(x) | BIT_SIFS_OFDM_TRX_8822B(v))
#define BIT_SHIFT_SIFS_CCK_TRX_8822B 16
#define BIT_MASK_SIFS_CCK_TRX_8822B 0xff
-#define BIT_SIFS_CCK_TRX_8822B(x) (((x) & BIT_MASK_SIFS_CCK_TRX_8822B) << BIT_SHIFT_SIFS_CCK_TRX_8822B)
-#define BIT_GET_SIFS_CCK_TRX_8822B(x) (((x) >> BIT_SHIFT_SIFS_CCK_TRX_8822B) & BIT_MASK_SIFS_CCK_TRX_8822B)
-
+#define BIT_SIFS_CCK_TRX_8822B(x) \
+ (((x) & BIT_MASK_SIFS_CCK_TRX_8822B) << BIT_SHIFT_SIFS_CCK_TRX_8822B)
+#define BITS_SIFS_CCK_TRX_8822B \
+ (BIT_MASK_SIFS_CCK_TRX_8822B << BIT_SHIFT_SIFS_CCK_TRX_8822B)
+#define BIT_CLEAR_SIFS_CCK_TRX_8822B(x) ((x) & (~BITS_SIFS_CCK_TRX_8822B))
+#define BIT_GET_SIFS_CCK_TRX_8822B(x) \
+ (((x) >> BIT_SHIFT_SIFS_CCK_TRX_8822B) & BIT_MASK_SIFS_CCK_TRX_8822B)
+#define BIT_SET_SIFS_CCK_TRX_8822B(x, v) \
+ (BIT_CLEAR_SIFS_CCK_TRX_8822B(x) | BIT_SIFS_CCK_TRX_8822B(v))
#define BIT_SHIFT_SIFS_OFDM_CTX_8822B 8
#define BIT_MASK_SIFS_OFDM_CTX_8822B 0xff
-#define BIT_SIFS_OFDM_CTX_8822B(x) (((x) & BIT_MASK_SIFS_OFDM_CTX_8822B) << BIT_SHIFT_SIFS_OFDM_CTX_8822B)
-#define BIT_GET_SIFS_OFDM_CTX_8822B(x) (((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8822B) & BIT_MASK_SIFS_OFDM_CTX_8822B)
-
+#define BIT_SIFS_OFDM_CTX_8822B(x) \
+ (((x) & BIT_MASK_SIFS_OFDM_CTX_8822B) << BIT_SHIFT_SIFS_OFDM_CTX_8822B)
+#define BITS_SIFS_OFDM_CTX_8822B \
+ (BIT_MASK_SIFS_OFDM_CTX_8822B << BIT_SHIFT_SIFS_OFDM_CTX_8822B)
+#define BIT_CLEAR_SIFS_OFDM_CTX_8822B(x) ((x) & (~BITS_SIFS_OFDM_CTX_8822B))
+#define BIT_GET_SIFS_OFDM_CTX_8822B(x) \
+ (((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8822B) & BIT_MASK_SIFS_OFDM_CTX_8822B)
+#define BIT_SET_SIFS_OFDM_CTX_8822B(x, v) \
+ (BIT_CLEAR_SIFS_OFDM_CTX_8822B(x) | BIT_SIFS_OFDM_CTX_8822B(v))
#define BIT_SHIFT_SIFS_CCK_CTX_8822B 0
#define BIT_MASK_SIFS_CCK_CTX_8822B 0xff
-#define BIT_SIFS_CCK_CTX_8822B(x) (((x) & BIT_MASK_SIFS_CCK_CTX_8822B) << BIT_SHIFT_SIFS_CCK_CTX_8822B)
-#define BIT_GET_SIFS_CCK_CTX_8822B(x) (((x) >> BIT_SHIFT_SIFS_CCK_CTX_8822B) & BIT_MASK_SIFS_CCK_CTX_8822B)
-
+#define BIT_SIFS_CCK_CTX_8822B(x) \
+ (((x) & BIT_MASK_SIFS_CCK_CTX_8822B) << BIT_SHIFT_SIFS_CCK_CTX_8822B)
+#define BITS_SIFS_CCK_CTX_8822B \
+ (BIT_MASK_SIFS_CCK_CTX_8822B << BIT_SHIFT_SIFS_CCK_CTX_8822B)
+#define BIT_CLEAR_SIFS_CCK_CTX_8822B(x) ((x) & (~BITS_SIFS_CCK_CTX_8822B))
+#define BIT_GET_SIFS_CCK_CTX_8822B(x) \
+ (((x) >> BIT_SHIFT_SIFS_CCK_CTX_8822B) & BIT_MASK_SIFS_CCK_CTX_8822B)
+#define BIT_SET_SIFS_CCK_CTX_8822B(x, v) \
+ (BIT_CLEAR_SIFS_CCK_CTX_8822B(x) | BIT_SIFS_CCK_CTX_8822B(v))
/* 2 REG_TSFTR_SYN_OFFSET_8822B */
#define BIT_SHIFT_TSFTR_SNC_OFFSET_8822B 0
#define BIT_MASK_TSFTR_SNC_OFFSET_8822B 0xffff
-#define BIT_TSFTR_SNC_OFFSET_8822B(x) (((x) & BIT_MASK_TSFTR_SNC_OFFSET_8822B) << BIT_SHIFT_TSFTR_SNC_OFFSET_8822B)
-#define BIT_GET_TSFTR_SNC_OFFSET_8822B(x) (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_8822B) & BIT_MASK_TSFTR_SNC_OFFSET_8822B)
-
+#define BIT_TSFTR_SNC_OFFSET_8822B(x) \
+ (((x) & BIT_MASK_TSFTR_SNC_OFFSET_8822B) \
+ << BIT_SHIFT_TSFTR_SNC_OFFSET_8822B)
+#define BITS_TSFTR_SNC_OFFSET_8822B \
+ (BIT_MASK_TSFTR_SNC_OFFSET_8822B << BIT_SHIFT_TSFTR_SNC_OFFSET_8822B)
+#define BIT_CLEAR_TSFTR_SNC_OFFSET_8822B(x) \
+ ((x) & (~BITS_TSFTR_SNC_OFFSET_8822B))
+#define BIT_GET_TSFTR_SNC_OFFSET_8822B(x) \
+ (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_8822B) & \
+ BIT_MASK_TSFTR_SNC_OFFSET_8822B)
+#define BIT_SET_TSFTR_SNC_OFFSET_8822B(x, v) \
+ (BIT_CLEAR_TSFTR_SNC_OFFSET_8822B(x) | BIT_TSFTR_SNC_OFFSET_8822B(v))
/* 2 REG_AGGR_BREAK_TIME_8822B */
#define BIT_SHIFT_AGGR_BK_TIME_8822B 0
#define BIT_MASK_AGGR_BK_TIME_8822B 0xff
-#define BIT_AGGR_BK_TIME_8822B(x) (((x) & BIT_MASK_AGGR_BK_TIME_8822B) << BIT_SHIFT_AGGR_BK_TIME_8822B)
-#define BIT_GET_AGGR_BK_TIME_8822B(x) (((x) >> BIT_SHIFT_AGGR_BK_TIME_8822B) & BIT_MASK_AGGR_BK_TIME_8822B)
-
+#define BIT_AGGR_BK_TIME_8822B(x) \
+ (((x) & BIT_MASK_AGGR_BK_TIME_8822B) << BIT_SHIFT_AGGR_BK_TIME_8822B)
+#define BITS_AGGR_BK_TIME_8822B \
+ (BIT_MASK_AGGR_BK_TIME_8822B << BIT_SHIFT_AGGR_BK_TIME_8822B)
+#define BIT_CLEAR_AGGR_BK_TIME_8822B(x) ((x) & (~BITS_AGGR_BK_TIME_8822B))
+#define BIT_GET_AGGR_BK_TIME_8822B(x) \
+ (((x) >> BIT_SHIFT_AGGR_BK_TIME_8822B) & BIT_MASK_AGGR_BK_TIME_8822B)
+#define BIT_SET_AGGR_BK_TIME_8822B(x, v) \
+ (BIT_CLEAR_AGGR_BK_TIME_8822B(x) | BIT_AGGR_BK_TIME_8822B(v))
/* 2 REG_SLOT_8822B */
#define BIT_SHIFT_SLOT_8822B 0
#define BIT_MASK_SLOT_8822B 0xff
#define BIT_SLOT_8822B(x) (((x) & BIT_MASK_SLOT_8822B) << BIT_SHIFT_SLOT_8822B)
-#define BIT_GET_SLOT_8822B(x) (((x) >> BIT_SHIFT_SLOT_8822B) & BIT_MASK_SLOT_8822B)
-
+#define BITS_SLOT_8822B (BIT_MASK_SLOT_8822B << BIT_SHIFT_SLOT_8822B)
+#define BIT_CLEAR_SLOT_8822B(x) ((x) & (~BITS_SLOT_8822B))
+#define BIT_GET_SLOT_8822B(x) \
+ (((x) >> BIT_SHIFT_SLOT_8822B) & BIT_MASK_SLOT_8822B)
+#define BIT_SET_SLOT_8822B(x, v) (BIT_CLEAR_SLOT_8822B(x) | BIT_SLOT_8822B(v))
/* 2 REG_TX_PTCL_CTRL_8822B */
#define BIT_DIS_EDCCA_8822B BIT(15)
@@ -6490,8 +11413,15 @@
#define BIT_SHIFT_TXQ_NAV_MSK_8822B 8
#define BIT_MASK_TXQ_NAV_MSK_8822B 0xf
-#define BIT_TXQ_NAV_MSK_8822B(x) (((x) & BIT_MASK_TXQ_NAV_MSK_8822B) << BIT_SHIFT_TXQ_NAV_MSK_8822B)
-#define BIT_GET_TXQ_NAV_MSK_8822B(x) (((x) >> BIT_SHIFT_TXQ_NAV_MSK_8822B) & BIT_MASK_TXQ_NAV_MSK_8822B)
+#define BIT_TXQ_NAV_MSK_8822B(x) \
+ (((x) & BIT_MASK_TXQ_NAV_MSK_8822B) << BIT_SHIFT_TXQ_NAV_MSK_8822B)
+#define BITS_TXQ_NAV_MSK_8822B \
+ (BIT_MASK_TXQ_NAV_MSK_8822B << BIT_SHIFT_TXQ_NAV_MSK_8822B)
+#define BIT_CLEAR_TXQ_NAV_MSK_8822B(x) ((x) & (~BITS_TXQ_NAV_MSK_8822B))
+#define BIT_GET_TXQ_NAV_MSK_8822B(x) \
+ (((x) >> BIT_SHIFT_TXQ_NAV_MSK_8822B) & BIT_MASK_TXQ_NAV_MSK_8822B)
+#define BIT_SET_TXQ_NAV_MSK_8822B(x, v) \
+ (BIT_CLEAR_TXQ_NAV_MSK_8822B(x) | BIT_TXQ_NAV_MSK_8822B(v))
#define BIT_DIS_CW_8822B BIT(7)
#define BIT_NAV_END_TXOP_8822B BIT(6)
@@ -6567,15 +11497,29 @@
#define BIT_SHIFT_CCA_FILTER_THRS_8822B 8
#define BIT_MASK_CCA_FILTER_THRS_8822B 0xff
-#define BIT_CCA_FILTER_THRS_8822B(x) (((x) & BIT_MASK_CCA_FILTER_THRS_8822B) << BIT_SHIFT_CCA_FILTER_THRS_8822B)
-#define BIT_GET_CCA_FILTER_THRS_8822B(x) (((x) >> BIT_SHIFT_CCA_FILTER_THRS_8822B) & BIT_MASK_CCA_FILTER_THRS_8822B)
-
+#define BIT_CCA_FILTER_THRS_8822B(x) \
+ (((x) & BIT_MASK_CCA_FILTER_THRS_8822B) \
+ << BIT_SHIFT_CCA_FILTER_THRS_8822B)
+#define BITS_CCA_FILTER_THRS_8822B \
+ (BIT_MASK_CCA_FILTER_THRS_8822B << BIT_SHIFT_CCA_FILTER_THRS_8822B)
+#define BIT_CLEAR_CCA_FILTER_THRS_8822B(x) ((x) & (~BITS_CCA_FILTER_THRS_8822B))
+#define BIT_GET_CCA_FILTER_THRS_8822B(x) \
+ (((x) >> BIT_SHIFT_CCA_FILTER_THRS_8822B) & \
+ BIT_MASK_CCA_FILTER_THRS_8822B)
+#define BIT_SET_CCA_FILTER_THRS_8822B(x, v) \
+ (BIT_CLEAR_CCA_FILTER_THRS_8822B(x) | BIT_CCA_FILTER_THRS_8822B(v))
#define BIT_SHIFT_EDCCA_THRS_8822B 0
#define BIT_MASK_EDCCA_THRS_8822B 0xff
-#define BIT_EDCCA_THRS_8822B(x) (((x) & BIT_MASK_EDCCA_THRS_8822B) << BIT_SHIFT_EDCCA_THRS_8822B)
-#define BIT_GET_EDCCA_THRS_8822B(x) (((x) >> BIT_SHIFT_EDCCA_THRS_8822B) & BIT_MASK_EDCCA_THRS_8822B)
-
+#define BIT_EDCCA_THRS_8822B(x) \
+ (((x) & BIT_MASK_EDCCA_THRS_8822B) << BIT_SHIFT_EDCCA_THRS_8822B)
+#define BITS_EDCCA_THRS_8822B \
+ (BIT_MASK_EDCCA_THRS_8822B << BIT_SHIFT_EDCCA_THRS_8822B)
+#define BIT_CLEAR_EDCCA_THRS_8822B(x) ((x) & (~BITS_EDCCA_THRS_8822B))
+#define BIT_GET_EDCCA_THRS_8822B(x) \
+ (((x) >> BIT_SHIFT_EDCCA_THRS_8822B) & BIT_MASK_EDCCA_THRS_8822B)
+#define BIT_SET_EDCCA_THRS_8822B(x, v) \
+ (BIT_CLEAR_EDCCA_THRS_8822B(x) | BIT_EDCCA_THRS_8822B(v))
/* 2 REG_P2PPS_SPEC_STATE_8822B */
#define BIT_SPEC_POWER_STATE_8822B BIT(7)
@@ -6587,82 +11531,240 @@
#define BIT_SPEC_NOA0_OFF_PERIOD_8822B BIT(1)
#define BIT_SPEC_FORCE_DOZE0_8822B BIT(0)
+/* 2 REG_TXOP_LIMIT_CTRL_8822B */
+
+#define BIT_SHIFT_TXOP_TBTT_CNT_8822B 24
+#define BIT_MASK_TXOP_TBTT_CNT_8822B 0xff
+#define BIT_TXOP_TBTT_CNT_8822B(x) \
+ (((x) & BIT_MASK_TXOP_TBTT_CNT_8822B) << BIT_SHIFT_TXOP_TBTT_CNT_8822B)
+#define BITS_TXOP_TBTT_CNT_8822B \
+ (BIT_MASK_TXOP_TBTT_CNT_8822B << BIT_SHIFT_TXOP_TBTT_CNT_8822B)
+#define BIT_CLEAR_TXOP_TBTT_CNT_8822B(x) ((x) & (~BITS_TXOP_TBTT_CNT_8822B))
+#define BIT_GET_TXOP_TBTT_CNT_8822B(x) \
+ (((x) >> BIT_SHIFT_TXOP_TBTT_CNT_8822B) & BIT_MASK_TXOP_TBTT_CNT_8822B)
+#define BIT_SET_TXOP_TBTT_CNT_8822B(x, v) \
+ (BIT_CLEAR_TXOP_TBTT_CNT_8822B(x) | BIT_TXOP_TBTT_CNT_8822B(v))
+
+#define BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822B 20
+#define BIT_MASK_TXOP_TBTT_CNT_SEL_8822B 0xf
+#define BIT_TXOP_TBTT_CNT_SEL_8822B(x) \
+ (((x) & BIT_MASK_TXOP_TBTT_CNT_SEL_8822B) \
+ << BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822B)
+#define BITS_TXOP_TBTT_CNT_SEL_8822B \
+ (BIT_MASK_TXOP_TBTT_CNT_SEL_8822B << BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822B)
+#define BIT_CLEAR_TXOP_TBTT_CNT_SEL_8822B(x) \
+ ((x) & (~BITS_TXOP_TBTT_CNT_SEL_8822B))
+#define BIT_GET_TXOP_TBTT_CNT_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822B) & \
+ BIT_MASK_TXOP_TBTT_CNT_SEL_8822B)
+#define BIT_SET_TXOP_TBTT_CNT_SEL_8822B(x, v) \
+ (BIT_CLEAR_TXOP_TBTT_CNT_SEL_8822B(x) | BIT_TXOP_TBTT_CNT_SEL_8822B(v))
+
+#define BIT_SHIFT_TXOP_LMT_EN_8822B 16
+#define BIT_MASK_TXOP_LMT_EN_8822B 0xf
+#define BIT_TXOP_LMT_EN_8822B(x) \
+ (((x) & BIT_MASK_TXOP_LMT_EN_8822B) << BIT_SHIFT_TXOP_LMT_EN_8822B)
+#define BITS_TXOP_LMT_EN_8822B \
+ (BIT_MASK_TXOP_LMT_EN_8822B << BIT_SHIFT_TXOP_LMT_EN_8822B)
+#define BIT_CLEAR_TXOP_LMT_EN_8822B(x) ((x) & (~BITS_TXOP_LMT_EN_8822B))
+#define BIT_GET_TXOP_LMT_EN_8822B(x) \
+ (((x) >> BIT_SHIFT_TXOP_LMT_EN_8822B) & BIT_MASK_TXOP_LMT_EN_8822B)
+#define BIT_SET_TXOP_LMT_EN_8822B(x, v) \
+ (BIT_CLEAR_TXOP_LMT_EN_8822B(x) | BIT_TXOP_LMT_EN_8822B(v))
+
+#define BIT_SHIFT_TXOP_LMT_TX_TIME_8822B 8
+#define BIT_MASK_TXOP_LMT_TX_TIME_8822B 0xff
+#define BIT_TXOP_LMT_TX_TIME_8822B(x) \
+ (((x) & BIT_MASK_TXOP_LMT_TX_TIME_8822B) \
+ << BIT_SHIFT_TXOP_LMT_TX_TIME_8822B)
+#define BITS_TXOP_LMT_TX_TIME_8822B \
+ (BIT_MASK_TXOP_LMT_TX_TIME_8822B << BIT_SHIFT_TXOP_LMT_TX_TIME_8822B)
+#define BIT_CLEAR_TXOP_LMT_TX_TIME_8822B(x) \
+ ((x) & (~BITS_TXOP_LMT_TX_TIME_8822B))
+#define BIT_GET_TXOP_LMT_TX_TIME_8822B(x) \
+ (((x) >> BIT_SHIFT_TXOP_LMT_TX_TIME_8822B) & \
+ BIT_MASK_TXOP_LMT_TX_TIME_8822B)
+#define BIT_SET_TXOP_LMT_TX_TIME_8822B(x, v) \
+ (BIT_CLEAR_TXOP_LMT_TX_TIME_8822B(x) | BIT_TXOP_LMT_TX_TIME_8822B(v))
+
+#define BIT_TXOP_CNT_TRIGGER_RESET_8822B BIT(7)
+
+#define BIT_SHIFT_TXOP_LMT_PKT_NUM_8822B 0
+#define BIT_MASK_TXOP_LMT_PKT_NUM_8822B 0x3f
+#define BIT_TXOP_LMT_PKT_NUM_8822B(x) \
+ (((x) & BIT_MASK_TXOP_LMT_PKT_NUM_8822B) \
+ << BIT_SHIFT_TXOP_LMT_PKT_NUM_8822B)
+#define BITS_TXOP_LMT_PKT_NUM_8822B \
+ (BIT_MASK_TXOP_LMT_PKT_NUM_8822B << BIT_SHIFT_TXOP_LMT_PKT_NUM_8822B)
+#define BIT_CLEAR_TXOP_LMT_PKT_NUM_8822B(x) \
+ ((x) & (~BITS_TXOP_LMT_PKT_NUM_8822B))
+#define BIT_GET_TXOP_LMT_PKT_NUM_8822B(x) \
+ (((x) >> BIT_SHIFT_TXOP_LMT_PKT_NUM_8822B) & \
+ BIT_MASK_TXOP_LMT_PKT_NUM_8822B)
+#define BIT_SET_TXOP_LMT_PKT_NUM_8822B(x, v) \
+ (BIT_CLEAR_TXOP_LMT_PKT_NUM_8822B(x) | BIT_TXOP_LMT_PKT_NUM_8822B(v))
+
/* 2 REG_BAR_TX_CTRL_8822B */
-/* 2 REG_NOT_VALID_8822B */
+/* 2 REG_P2PON_DIS_TXTIME_8822B */
#define BIT_SHIFT_P2PON_DIS_TXTIME_8822B 0
#define BIT_MASK_P2PON_DIS_TXTIME_8822B 0xff
-#define BIT_P2PON_DIS_TXTIME_8822B(x) (((x) & BIT_MASK_P2PON_DIS_TXTIME_8822B) << BIT_SHIFT_P2PON_DIS_TXTIME_8822B)
-#define BIT_GET_P2PON_DIS_TXTIME_8822B(x) (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8822B) & BIT_MASK_P2PON_DIS_TXTIME_8822B)
-
+#define BIT_P2PON_DIS_TXTIME_8822B(x) \
+ (((x) & BIT_MASK_P2PON_DIS_TXTIME_8822B) \
+ << BIT_SHIFT_P2PON_DIS_TXTIME_8822B)
+#define BITS_P2PON_DIS_TXTIME_8822B \
+ (BIT_MASK_P2PON_DIS_TXTIME_8822B << BIT_SHIFT_P2PON_DIS_TXTIME_8822B)
+#define BIT_CLEAR_P2PON_DIS_TXTIME_8822B(x) \
+ ((x) & (~BITS_P2PON_DIS_TXTIME_8822B))
+#define BIT_GET_P2PON_DIS_TXTIME_8822B(x) \
+ (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8822B) & \
+ BIT_MASK_P2PON_DIS_TXTIME_8822B)
+#define BIT_SET_P2PON_DIS_TXTIME_8822B(x, v) \
+ (BIT_CLEAR_P2PON_DIS_TXTIME_8822B(x) | BIT_P2PON_DIS_TXTIME_8822B(v))
/* 2 REG_QUEUE_INCOL_THR_8822B */
#define BIT_SHIFT_BK_QUEUE_THR_8822B 24
#define BIT_MASK_BK_QUEUE_THR_8822B 0xff
-#define BIT_BK_QUEUE_THR_8822B(x) (((x) & BIT_MASK_BK_QUEUE_THR_8822B) << BIT_SHIFT_BK_QUEUE_THR_8822B)
-#define BIT_GET_BK_QUEUE_THR_8822B(x) (((x) >> BIT_SHIFT_BK_QUEUE_THR_8822B) & BIT_MASK_BK_QUEUE_THR_8822B)
-
+#define BIT_BK_QUEUE_THR_8822B(x) \
+ (((x) & BIT_MASK_BK_QUEUE_THR_8822B) << BIT_SHIFT_BK_QUEUE_THR_8822B)
+#define BITS_BK_QUEUE_THR_8822B \
+ (BIT_MASK_BK_QUEUE_THR_8822B << BIT_SHIFT_BK_QUEUE_THR_8822B)
+#define BIT_CLEAR_BK_QUEUE_THR_8822B(x) ((x) & (~BITS_BK_QUEUE_THR_8822B))
+#define BIT_GET_BK_QUEUE_THR_8822B(x) \
+ (((x) >> BIT_SHIFT_BK_QUEUE_THR_8822B) & BIT_MASK_BK_QUEUE_THR_8822B)
+#define BIT_SET_BK_QUEUE_THR_8822B(x, v) \
+ (BIT_CLEAR_BK_QUEUE_THR_8822B(x) | BIT_BK_QUEUE_THR_8822B(v))
#define BIT_SHIFT_BE_QUEUE_THR_8822B 16
#define BIT_MASK_BE_QUEUE_THR_8822B 0xff
-#define BIT_BE_QUEUE_THR_8822B(x) (((x) & BIT_MASK_BE_QUEUE_THR_8822B) << BIT_SHIFT_BE_QUEUE_THR_8822B)
-#define BIT_GET_BE_QUEUE_THR_8822B(x) (((x) >> BIT_SHIFT_BE_QUEUE_THR_8822B) & BIT_MASK_BE_QUEUE_THR_8822B)
-
+#define BIT_BE_QUEUE_THR_8822B(x) \
+ (((x) & BIT_MASK_BE_QUEUE_THR_8822B) << BIT_SHIFT_BE_QUEUE_THR_8822B)
+#define BITS_BE_QUEUE_THR_8822B \
+ (BIT_MASK_BE_QUEUE_THR_8822B << BIT_SHIFT_BE_QUEUE_THR_8822B)
+#define BIT_CLEAR_BE_QUEUE_THR_8822B(x) ((x) & (~BITS_BE_QUEUE_THR_8822B))
+#define BIT_GET_BE_QUEUE_THR_8822B(x) \
+ (((x) >> BIT_SHIFT_BE_QUEUE_THR_8822B) & BIT_MASK_BE_QUEUE_THR_8822B)
+#define BIT_SET_BE_QUEUE_THR_8822B(x, v) \
+ (BIT_CLEAR_BE_QUEUE_THR_8822B(x) | BIT_BE_QUEUE_THR_8822B(v))
#define BIT_SHIFT_VI_QUEUE_THR_8822B 8
#define BIT_MASK_VI_QUEUE_THR_8822B 0xff
-#define BIT_VI_QUEUE_THR_8822B(x) (((x) & BIT_MASK_VI_QUEUE_THR_8822B) << BIT_SHIFT_VI_QUEUE_THR_8822B)
-#define BIT_GET_VI_QUEUE_THR_8822B(x) (((x) >> BIT_SHIFT_VI_QUEUE_THR_8822B) & BIT_MASK_VI_QUEUE_THR_8822B)
-
+#define BIT_VI_QUEUE_THR_8822B(x) \
+ (((x) & BIT_MASK_VI_QUEUE_THR_8822B) << BIT_SHIFT_VI_QUEUE_THR_8822B)
+#define BITS_VI_QUEUE_THR_8822B \
+ (BIT_MASK_VI_QUEUE_THR_8822B << BIT_SHIFT_VI_QUEUE_THR_8822B)
+#define BIT_CLEAR_VI_QUEUE_THR_8822B(x) ((x) & (~BITS_VI_QUEUE_THR_8822B))
+#define BIT_GET_VI_QUEUE_THR_8822B(x) \
+ (((x) >> BIT_SHIFT_VI_QUEUE_THR_8822B) & BIT_MASK_VI_QUEUE_THR_8822B)
+#define BIT_SET_VI_QUEUE_THR_8822B(x, v) \
+ (BIT_CLEAR_VI_QUEUE_THR_8822B(x) | BIT_VI_QUEUE_THR_8822B(v))
#define BIT_SHIFT_VO_QUEUE_THR_8822B 0
#define BIT_MASK_VO_QUEUE_THR_8822B 0xff
-#define BIT_VO_QUEUE_THR_8822B(x) (((x) & BIT_MASK_VO_QUEUE_THR_8822B) << BIT_SHIFT_VO_QUEUE_THR_8822B)
-#define BIT_GET_VO_QUEUE_THR_8822B(x) (((x) >> BIT_SHIFT_VO_QUEUE_THR_8822B) & BIT_MASK_VO_QUEUE_THR_8822B)
-
+#define BIT_VO_QUEUE_THR_8822B(x) \
+ (((x) & BIT_MASK_VO_QUEUE_THR_8822B) << BIT_SHIFT_VO_QUEUE_THR_8822B)
+#define BITS_VO_QUEUE_THR_8822B \
+ (BIT_MASK_VO_QUEUE_THR_8822B << BIT_SHIFT_VO_QUEUE_THR_8822B)
+#define BIT_CLEAR_VO_QUEUE_THR_8822B(x) ((x) & (~BITS_VO_QUEUE_THR_8822B))
+#define BIT_GET_VO_QUEUE_THR_8822B(x) \
+ (((x) >> BIT_SHIFT_VO_QUEUE_THR_8822B) & BIT_MASK_VO_QUEUE_THR_8822B)
+#define BIT_SET_VO_QUEUE_THR_8822B(x, v) \
+ (BIT_CLEAR_VO_QUEUE_THR_8822B(x) | BIT_VO_QUEUE_THR_8822B(v))
/* 2 REG_QUEUE_INCOL_EN_8822B */
#define BIT_QUEUE_INCOL_EN_8822B BIT(16)
#define BIT_SHIFT_BE_TRIGGER_NUM_8822B 12
#define BIT_MASK_BE_TRIGGER_NUM_8822B 0xf
-#define BIT_BE_TRIGGER_NUM_8822B(x) (((x) & BIT_MASK_BE_TRIGGER_NUM_8822B) << BIT_SHIFT_BE_TRIGGER_NUM_8822B)
-#define BIT_GET_BE_TRIGGER_NUM_8822B(x) (((x) >> BIT_SHIFT_BE_TRIGGER_NUM_8822B) & BIT_MASK_BE_TRIGGER_NUM_8822B)
-
+#define BIT_BE_TRIGGER_NUM_8822B(x) \
+ (((x) & BIT_MASK_BE_TRIGGER_NUM_8822B) \
+ << BIT_SHIFT_BE_TRIGGER_NUM_8822B)
+#define BITS_BE_TRIGGER_NUM_8822B \
+ (BIT_MASK_BE_TRIGGER_NUM_8822B << BIT_SHIFT_BE_TRIGGER_NUM_8822B)
+#define BIT_CLEAR_BE_TRIGGER_NUM_8822B(x) ((x) & (~BITS_BE_TRIGGER_NUM_8822B))
+#define BIT_GET_BE_TRIGGER_NUM_8822B(x) \
+ (((x) >> BIT_SHIFT_BE_TRIGGER_NUM_8822B) & \
+ BIT_MASK_BE_TRIGGER_NUM_8822B)
+#define BIT_SET_BE_TRIGGER_NUM_8822B(x, v) \
+ (BIT_CLEAR_BE_TRIGGER_NUM_8822B(x) | BIT_BE_TRIGGER_NUM_8822B(v))
#define BIT_SHIFT_BK_TRIGGER_NUM_8822B 8
#define BIT_MASK_BK_TRIGGER_NUM_8822B 0xf
-#define BIT_BK_TRIGGER_NUM_8822B(x) (((x) & BIT_MASK_BK_TRIGGER_NUM_8822B) << BIT_SHIFT_BK_TRIGGER_NUM_8822B)
-#define BIT_GET_BK_TRIGGER_NUM_8822B(x) (((x) >> BIT_SHIFT_BK_TRIGGER_NUM_8822B) & BIT_MASK_BK_TRIGGER_NUM_8822B)
-
+#define BIT_BK_TRIGGER_NUM_8822B(x) \
+ (((x) & BIT_MASK_BK_TRIGGER_NUM_8822B) \
+ << BIT_SHIFT_BK_TRIGGER_NUM_8822B)
+#define BITS_BK_TRIGGER_NUM_8822B \
+ (BIT_MASK_BK_TRIGGER_NUM_8822B << BIT_SHIFT_BK_TRIGGER_NUM_8822B)
+#define BIT_CLEAR_BK_TRIGGER_NUM_8822B(x) ((x) & (~BITS_BK_TRIGGER_NUM_8822B))
+#define BIT_GET_BK_TRIGGER_NUM_8822B(x) \
+ (((x) >> BIT_SHIFT_BK_TRIGGER_NUM_8822B) & \
+ BIT_MASK_BK_TRIGGER_NUM_8822B)
+#define BIT_SET_BK_TRIGGER_NUM_8822B(x, v) \
+ (BIT_CLEAR_BK_TRIGGER_NUM_8822B(x) | BIT_BK_TRIGGER_NUM_8822B(v))
#define BIT_SHIFT_VI_TRIGGER_NUM_8822B 4
#define BIT_MASK_VI_TRIGGER_NUM_8822B 0xf
-#define BIT_VI_TRIGGER_NUM_8822B(x) (((x) & BIT_MASK_VI_TRIGGER_NUM_8822B) << BIT_SHIFT_VI_TRIGGER_NUM_8822B)
-#define BIT_GET_VI_TRIGGER_NUM_8822B(x) (((x) >> BIT_SHIFT_VI_TRIGGER_NUM_8822B) & BIT_MASK_VI_TRIGGER_NUM_8822B)
-
+#define BIT_VI_TRIGGER_NUM_8822B(x) \
+ (((x) & BIT_MASK_VI_TRIGGER_NUM_8822B) \
+ << BIT_SHIFT_VI_TRIGGER_NUM_8822B)
+#define BITS_VI_TRIGGER_NUM_8822B \
+ (BIT_MASK_VI_TRIGGER_NUM_8822B << BIT_SHIFT_VI_TRIGGER_NUM_8822B)
+#define BIT_CLEAR_VI_TRIGGER_NUM_8822B(x) ((x) & (~BITS_VI_TRIGGER_NUM_8822B))
+#define BIT_GET_VI_TRIGGER_NUM_8822B(x) \
+ (((x) >> BIT_SHIFT_VI_TRIGGER_NUM_8822B) & \
+ BIT_MASK_VI_TRIGGER_NUM_8822B)
+#define BIT_SET_VI_TRIGGER_NUM_8822B(x, v) \
+ (BIT_CLEAR_VI_TRIGGER_NUM_8822B(x) | BIT_VI_TRIGGER_NUM_8822B(v))
#define BIT_SHIFT_VO_TRIGGER_NUM_8822B 0
#define BIT_MASK_VO_TRIGGER_NUM_8822B 0xf
-#define BIT_VO_TRIGGER_NUM_8822B(x) (((x) & BIT_MASK_VO_TRIGGER_NUM_8822B) << BIT_SHIFT_VO_TRIGGER_NUM_8822B)
-#define BIT_GET_VO_TRIGGER_NUM_8822B(x) (((x) >> BIT_SHIFT_VO_TRIGGER_NUM_8822B) & BIT_MASK_VO_TRIGGER_NUM_8822B)
-
+#define BIT_VO_TRIGGER_NUM_8822B(x) \
+ (((x) & BIT_MASK_VO_TRIGGER_NUM_8822B) \
+ << BIT_SHIFT_VO_TRIGGER_NUM_8822B)
+#define BITS_VO_TRIGGER_NUM_8822B \
+ (BIT_MASK_VO_TRIGGER_NUM_8822B << BIT_SHIFT_VO_TRIGGER_NUM_8822B)
+#define BIT_CLEAR_VO_TRIGGER_NUM_8822B(x) ((x) & (~BITS_VO_TRIGGER_NUM_8822B))
+#define BIT_GET_VO_TRIGGER_NUM_8822B(x) \
+ (((x) >> BIT_SHIFT_VO_TRIGGER_NUM_8822B) & \
+ BIT_MASK_VO_TRIGGER_NUM_8822B)
+#define BIT_SET_VO_TRIGGER_NUM_8822B(x, v) \
+ (BIT_CLEAR_VO_TRIGGER_NUM_8822B(x) | BIT_VO_TRIGGER_NUM_8822B(v))
/* 2 REG_TBTT_PROHIBIT_8822B */
#define BIT_SHIFT_TBTT_HOLD_TIME_AP_8822B 8
#define BIT_MASK_TBTT_HOLD_TIME_AP_8822B 0xfff
-#define BIT_TBTT_HOLD_TIME_AP_8822B(x) (((x) & BIT_MASK_TBTT_HOLD_TIME_AP_8822B) << BIT_SHIFT_TBTT_HOLD_TIME_AP_8822B)
-#define BIT_GET_TBTT_HOLD_TIME_AP_8822B(x) (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP_8822B) & BIT_MASK_TBTT_HOLD_TIME_AP_8822B)
-
+#define BIT_TBTT_HOLD_TIME_AP_8822B(x) \
+ (((x) & BIT_MASK_TBTT_HOLD_TIME_AP_8822B) \
+ << BIT_SHIFT_TBTT_HOLD_TIME_AP_8822B)
+#define BITS_TBTT_HOLD_TIME_AP_8822B \
+ (BIT_MASK_TBTT_HOLD_TIME_AP_8822B << BIT_SHIFT_TBTT_HOLD_TIME_AP_8822B)
+#define BIT_CLEAR_TBTT_HOLD_TIME_AP_8822B(x) \
+ ((x) & (~BITS_TBTT_HOLD_TIME_AP_8822B))
+#define BIT_GET_TBTT_HOLD_TIME_AP_8822B(x) \
+ (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP_8822B) & \
+ BIT_MASK_TBTT_HOLD_TIME_AP_8822B)
+#define BIT_SET_TBTT_HOLD_TIME_AP_8822B(x, v) \
+ (BIT_CLEAR_TBTT_HOLD_TIME_AP_8822B(x) | BIT_TBTT_HOLD_TIME_AP_8822B(v))
#define BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822B 0
#define BIT_MASK_TBTT_PROHIBIT_SETUP_8822B 0xf
-#define BIT_TBTT_PROHIBIT_SETUP_8822B(x) (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8822B) << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822B)
-#define BIT_GET_TBTT_PROHIBIT_SETUP_8822B(x) (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822B) & BIT_MASK_TBTT_PROHIBIT_SETUP_8822B)
-
+#define BIT_TBTT_PROHIBIT_SETUP_8822B(x) \
+ (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8822B) \
+ << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822B)
+#define BITS_TBTT_PROHIBIT_SETUP_8822B \
+ (BIT_MASK_TBTT_PROHIBIT_SETUP_8822B \
+ << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822B)
+#define BIT_CLEAR_TBTT_PROHIBIT_SETUP_8822B(x) \
+ ((x) & (~BITS_TBTT_PROHIBIT_SETUP_8822B))
+#define BIT_GET_TBTT_PROHIBIT_SETUP_8822B(x) \
+ (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822B) & \
+ BIT_MASK_TBTT_PROHIBIT_SETUP_8822B)
+#define BIT_SET_TBTT_PROHIBIT_SETUP_8822B(x, v) \
+ (BIT_CLEAR_TBTT_PROHIBIT_SETUP_8822B(x) | \
+ BIT_TBTT_PROHIBIT_SETUP_8822B(v))
/* 2 REG_P2PPS_STATE_8822B */
#define BIT_POWER_STATE_8822B BIT(7)
@@ -6678,17 +11780,31 @@
#define BIT_SHIFT_RD_NAV_PROT_NXT_8822B 0
#define BIT_MASK_RD_NAV_PROT_NXT_8822B 0xffff
-#define BIT_RD_NAV_PROT_NXT_8822B(x) (((x) & BIT_MASK_RD_NAV_PROT_NXT_8822B) << BIT_SHIFT_RD_NAV_PROT_NXT_8822B)
-#define BIT_GET_RD_NAV_PROT_NXT_8822B(x) (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8822B) & BIT_MASK_RD_NAV_PROT_NXT_8822B)
-
+#define BIT_RD_NAV_PROT_NXT_8822B(x) \
+ (((x) & BIT_MASK_RD_NAV_PROT_NXT_8822B) \
+ << BIT_SHIFT_RD_NAV_PROT_NXT_8822B)
+#define BITS_RD_NAV_PROT_NXT_8822B \
+ (BIT_MASK_RD_NAV_PROT_NXT_8822B << BIT_SHIFT_RD_NAV_PROT_NXT_8822B)
+#define BIT_CLEAR_RD_NAV_PROT_NXT_8822B(x) ((x) & (~BITS_RD_NAV_PROT_NXT_8822B))
+#define BIT_GET_RD_NAV_PROT_NXT_8822B(x) \
+ (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8822B) & \
+ BIT_MASK_RD_NAV_PROT_NXT_8822B)
+#define BIT_SET_RD_NAV_PROT_NXT_8822B(x, v) \
+ (BIT_CLEAR_RD_NAV_PROT_NXT_8822B(x) | BIT_RD_NAV_PROT_NXT_8822B(v))
/* 2 REG_NAV_PROT_LEN_8822B */
#define BIT_SHIFT_NAV_PROT_LEN_8822B 0
#define BIT_MASK_NAV_PROT_LEN_8822B 0xffff
-#define BIT_NAV_PROT_LEN_8822B(x) (((x) & BIT_MASK_NAV_PROT_LEN_8822B) << BIT_SHIFT_NAV_PROT_LEN_8822B)
-#define BIT_GET_NAV_PROT_LEN_8822B(x) (((x) >> BIT_SHIFT_NAV_PROT_LEN_8822B) & BIT_MASK_NAV_PROT_LEN_8822B)
-
+#define BIT_NAV_PROT_LEN_8822B(x) \
+ (((x) & BIT_MASK_NAV_PROT_LEN_8822B) << BIT_SHIFT_NAV_PROT_LEN_8822B)
+#define BITS_NAV_PROT_LEN_8822B \
+ (BIT_MASK_NAV_PROT_LEN_8822B << BIT_SHIFT_NAV_PROT_LEN_8822B)
+#define BIT_CLEAR_NAV_PROT_LEN_8822B(x) ((x) & (~BITS_NAV_PROT_LEN_8822B))
+#define BIT_GET_NAV_PROT_LEN_8822B(x) \
+ (((x) >> BIT_SHIFT_NAV_PROT_LEN_8822B) & BIT_MASK_NAV_PROT_LEN_8822B)
+#define BIT_SET_NAV_PROT_LEN_8822B(x, v) \
+ (BIT_CLEAR_NAV_PROT_LEN_8822B(x) | BIT_NAV_PROT_LEN_8822B(v))
/* 2 REG_BCN_CTRL_8822B */
#define BIT_DIS_RX_BSSID_FIT_8822B BIT(6)
@@ -6712,9 +11828,15 @@
#define BIT_SHIFT_MBID_BCN_NUM_8822B 0
#define BIT_MASK_MBID_BCN_NUM_8822B 0x7
-#define BIT_MBID_BCN_NUM_8822B(x) (((x) & BIT_MASK_MBID_BCN_NUM_8822B) << BIT_SHIFT_MBID_BCN_NUM_8822B)
-#define BIT_GET_MBID_BCN_NUM_8822B(x) (((x) >> BIT_SHIFT_MBID_BCN_NUM_8822B) & BIT_MASK_MBID_BCN_NUM_8822B)
-
+#define BIT_MBID_BCN_NUM_8822B(x) \
+ (((x) & BIT_MASK_MBID_BCN_NUM_8822B) << BIT_SHIFT_MBID_BCN_NUM_8822B)
+#define BITS_MBID_BCN_NUM_8822B \
+ (BIT_MASK_MBID_BCN_NUM_8822B << BIT_SHIFT_MBID_BCN_NUM_8822B)
+#define BIT_CLEAR_MBID_BCN_NUM_8822B(x) ((x) & (~BITS_MBID_BCN_NUM_8822B))
+#define BIT_GET_MBID_BCN_NUM_8822B(x) \
+ (((x) >> BIT_SHIFT_MBID_BCN_NUM_8822B) & BIT_MASK_MBID_BCN_NUM_8822B)
+#define BIT_SET_MBID_BCN_NUM_8822B(x, v) \
+ (BIT_CLEAR_MBID_BCN_NUM_8822B(x) | BIT_MBID_BCN_NUM_8822B(v))
/* 2 REG_DUAL_TSF_RST_8822B */
#define BIT_FREECNT_RST_8822B BIT(5)
@@ -6728,152 +11850,297 @@
#define BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822B 28
#define BIT_MASK_BCN_TIMER_SEL_FWRD_8822B 0x7
-#define BIT_BCN_TIMER_SEL_FWRD_8822B(x) (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_8822B) << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822B)
-#define BIT_GET_BCN_TIMER_SEL_FWRD_8822B(x) (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822B) & BIT_MASK_BCN_TIMER_SEL_FWRD_8822B)
-
+#define BIT_BCN_TIMER_SEL_FWRD_8822B(x) \
+ (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_8822B) \
+ << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822B)
+#define BITS_BCN_TIMER_SEL_FWRD_8822B \
+ (BIT_MASK_BCN_TIMER_SEL_FWRD_8822B \
+ << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822B)
+#define BIT_CLEAR_BCN_TIMER_SEL_FWRD_8822B(x) \
+ ((x) & (~BITS_BCN_TIMER_SEL_FWRD_8822B))
+#define BIT_GET_BCN_TIMER_SEL_FWRD_8822B(x) \
+ (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822B) & \
+ BIT_MASK_BCN_TIMER_SEL_FWRD_8822B)
+#define BIT_SET_BCN_TIMER_SEL_FWRD_8822B(x, v) \
+ (BIT_CLEAR_BCN_TIMER_SEL_FWRD_8822B(x) | \
+ BIT_BCN_TIMER_SEL_FWRD_8822B(v))
#define BIT_SHIFT_BCN_SPACE_CLINT0_8822B 16
#define BIT_MASK_BCN_SPACE_CLINT0_8822B 0xfff
-#define BIT_BCN_SPACE_CLINT0_8822B(x) (((x) & BIT_MASK_BCN_SPACE_CLINT0_8822B) << BIT_SHIFT_BCN_SPACE_CLINT0_8822B)
-#define BIT_GET_BCN_SPACE_CLINT0_8822B(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT0_8822B) & BIT_MASK_BCN_SPACE_CLINT0_8822B)
-
+#define BIT_BCN_SPACE_CLINT0_8822B(x) \
+ (((x) & BIT_MASK_BCN_SPACE_CLINT0_8822B) \
+ << BIT_SHIFT_BCN_SPACE_CLINT0_8822B)
+#define BITS_BCN_SPACE_CLINT0_8822B \
+ (BIT_MASK_BCN_SPACE_CLINT0_8822B << BIT_SHIFT_BCN_SPACE_CLINT0_8822B)
+#define BIT_CLEAR_BCN_SPACE_CLINT0_8822B(x) \
+ ((x) & (~BITS_BCN_SPACE_CLINT0_8822B))
+#define BIT_GET_BCN_SPACE_CLINT0_8822B(x) \
+ (((x) >> BIT_SHIFT_BCN_SPACE_CLINT0_8822B) & \
+ BIT_MASK_BCN_SPACE_CLINT0_8822B)
+#define BIT_SET_BCN_SPACE_CLINT0_8822B(x, v) \
+ (BIT_CLEAR_BCN_SPACE_CLINT0_8822B(x) | BIT_BCN_SPACE_CLINT0_8822B(v))
#define BIT_SHIFT_BCN_SPACE0_8822B 0
#define BIT_MASK_BCN_SPACE0_8822B 0xffff
-#define BIT_BCN_SPACE0_8822B(x) (((x) & BIT_MASK_BCN_SPACE0_8822B) << BIT_SHIFT_BCN_SPACE0_8822B)
-#define BIT_GET_BCN_SPACE0_8822B(x) (((x) >> BIT_SHIFT_BCN_SPACE0_8822B) & BIT_MASK_BCN_SPACE0_8822B)
-
+#define BIT_BCN_SPACE0_8822B(x) \
+ (((x) & BIT_MASK_BCN_SPACE0_8822B) << BIT_SHIFT_BCN_SPACE0_8822B)
+#define BITS_BCN_SPACE0_8822B \
+ (BIT_MASK_BCN_SPACE0_8822B << BIT_SHIFT_BCN_SPACE0_8822B)
+#define BIT_CLEAR_BCN_SPACE0_8822B(x) ((x) & (~BITS_BCN_SPACE0_8822B))
+#define BIT_GET_BCN_SPACE0_8822B(x) \
+ (((x) >> BIT_SHIFT_BCN_SPACE0_8822B) & BIT_MASK_BCN_SPACE0_8822B)
+#define BIT_SET_BCN_SPACE0_8822B(x, v) \
+ (BIT_CLEAR_BCN_SPACE0_8822B(x) | BIT_BCN_SPACE0_8822B(v))
/* 2 REG_DRVERLYINT_8822B */
#define BIT_SHIFT_DRVERLYITV_8822B 0
#define BIT_MASK_DRVERLYITV_8822B 0xff
-#define BIT_DRVERLYITV_8822B(x) (((x) & BIT_MASK_DRVERLYITV_8822B) << BIT_SHIFT_DRVERLYITV_8822B)
-#define BIT_GET_DRVERLYITV_8822B(x) (((x) >> BIT_SHIFT_DRVERLYITV_8822B) & BIT_MASK_DRVERLYITV_8822B)
-
+#define BIT_DRVERLYITV_8822B(x) \
+ (((x) & BIT_MASK_DRVERLYITV_8822B) << BIT_SHIFT_DRVERLYITV_8822B)
+#define BITS_DRVERLYITV_8822B \
+ (BIT_MASK_DRVERLYITV_8822B << BIT_SHIFT_DRVERLYITV_8822B)
+#define BIT_CLEAR_DRVERLYITV_8822B(x) ((x) & (~BITS_DRVERLYITV_8822B))
+#define BIT_GET_DRVERLYITV_8822B(x) \
+ (((x) >> BIT_SHIFT_DRVERLYITV_8822B) & BIT_MASK_DRVERLYITV_8822B)
+#define BIT_SET_DRVERLYITV_8822B(x, v) \
+ (BIT_CLEAR_DRVERLYITV_8822B(x) | BIT_DRVERLYITV_8822B(v))
/* 2 REG_BCNDMATIM_8822B */
#define BIT_SHIFT_BCNDMATIM_8822B 0
#define BIT_MASK_BCNDMATIM_8822B 0xff
-#define BIT_BCNDMATIM_8822B(x) (((x) & BIT_MASK_BCNDMATIM_8822B) << BIT_SHIFT_BCNDMATIM_8822B)
-#define BIT_GET_BCNDMATIM_8822B(x) (((x) >> BIT_SHIFT_BCNDMATIM_8822B) & BIT_MASK_BCNDMATIM_8822B)
-
+#define BIT_BCNDMATIM_8822B(x) \
+ (((x) & BIT_MASK_BCNDMATIM_8822B) << BIT_SHIFT_BCNDMATIM_8822B)
+#define BITS_BCNDMATIM_8822B \
+ (BIT_MASK_BCNDMATIM_8822B << BIT_SHIFT_BCNDMATIM_8822B)
+#define BIT_CLEAR_BCNDMATIM_8822B(x) ((x) & (~BITS_BCNDMATIM_8822B))
+#define BIT_GET_BCNDMATIM_8822B(x) \
+ (((x) >> BIT_SHIFT_BCNDMATIM_8822B) & BIT_MASK_BCNDMATIM_8822B)
+#define BIT_SET_BCNDMATIM_8822B(x, v) \
+ (BIT_CLEAR_BCNDMATIM_8822B(x) | BIT_BCNDMATIM_8822B(v))
/* 2 REG_ATIMWND_8822B */
#define BIT_SHIFT_ATIMWND0_8822B 0
#define BIT_MASK_ATIMWND0_8822B 0xffff
-#define BIT_ATIMWND0_8822B(x) (((x) & BIT_MASK_ATIMWND0_8822B) << BIT_SHIFT_ATIMWND0_8822B)
-#define BIT_GET_ATIMWND0_8822B(x) (((x) >> BIT_SHIFT_ATIMWND0_8822B) & BIT_MASK_ATIMWND0_8822B)
-
+#define BIT_ATIMWND0_8822B(x) \
+ (((x) & BIT_MASK_ATIMWND0_8822B) << BIT_SHIFT_ATIMWND0_8822B)
+#define BITS_ATIMWND0_8822B \
+ (BIT_MASK_ATIMWND0_8822B << BIT_SHIFT_ATIMWND0_8822B)
+#define BIT_CLEAR_ATIMWND0_8822B(x) ((x) & (~BITS_ATIMWND0_8822B))
+#define BIT_GET_ATIMWND0_8822B(x) \
+ (((x) >> BIT_SHIFT_ATIMWND0_8822B) & BIT_MASK_ATIMWND0_8822B)
+#define BIT_SET_ATIMWND0_8822B(x, v) \
+ (BIT_CLEAR_ATIMWND0_8822B(x) | BIT_ATIMWND0_8822B(v))
/* 2 REG_USTIME_TSF_8822B */
#define BIT_SHIFT_USTIME_TSF_V1_8822B 0
#define BIT_MASK_USTIME_TSF_V1_8822B 0xff
-#define BIT_USTIME_TSF_V1_8822B(x) (((x) & BIT_MASK_USTIME_TSF_V1_8822B) << BIT_SHIFT_USTIME_TSF_V1_8822B)
-#define BIT_GET_USTIME_TSF_V1_8822B(x) (((x) >> BIT_SHIFT_USTIME_TSF_V1_8822B) & BIT_MASK_USTIME_TSF_V1_8822B)
-
+#define BIT_USTIME_TSF_V1_8822B(x) \
+ (((x) & BIT_MASK_USTIME_TSF_V1_8822B) << BIT_SHIFT_USTIME_TSF_V1_8822B)
+#define BITS_USTIME_TSF_V1_8822B \
+ (BIT_MASK_USTIME_TSF_V1_8822B << BIT_SHIFT_USTIME_TSF_V1_8822B)
+#define BIT_CLEAR_USTIME_TSF_V1_8822B(x) ((x) & (~BITS_USTIME_TSF_V1_8822B))
+#define BIT_GET_USTIME_TSF_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_USTIME_TSF_V1_8822B) & BIT_MASK_USTIME_TSF_V1_8822B)
+#define BIT_SET_USTIME_TSF_V1_8822B(x, v) \
+ (BIT_CLEAR_USTIME_TSF_V1_8822B(x) | BIT_USTIME_TSF_V1_8822B(v))
/* 2 REG_BCN_MAX_ERR_8822B */
#define BIT_SHIFT_BCN_MAX_ERR_8822B 0
#define BIT_MASK_BCN_MAX_ERR_8822B 0xff
-#define BIT_BCN_MAX_ERR_8822B(x) (((x) & BIT_MASK_BCN_MAX_ERR_8822B) << BIT_SHIFT_BCN_MAX_ERR_8822B)
-#define BIT_GET_BCN_MAX_ERR_8822B(x) (((x) >> BIT_SHIFT_BCN_MAX_ERR_8822B) & BIT_MASK_BCN_MAX_ERR_8822B)
-
+#define BIT_BCN_MAX_ERR_8822B(x) \
+ (((x) & BIT_MASK_BCN_MAX_ERR_8822B) << BIT_SHIFT_BCN_MAX_ERR_8822B)
+#define BITS_BCN_MAX_ERR_8822B \
+ (BIT_MASK_BCN_MAX_ERR_8822B << BIT_SHIFT_BCN_MAX_ERR_8822B)
+#define BIT_CLEAR_BCN_MAX_ERR_8822B(x) ((x) & (~BITS_BCN_MAX_ERR_8822B))
+#define BIT_GET_BCN_MAX_ERR_8822B(x) \
+ (((x) >> BIT_SHIFT_BCN_MAX_ERR_8822B) & BIT_MASK_BCN_MAX_ERR_8822B)
+#define BIT_SET_BCN_MAX_ERR_8822B(x, v) \
+ (BIT_CLEAR_BCN_MAX_ERR_8822B(x) | BIT_BCN_MAX_ERR_8822B(v))
/* 2 REG_RXTSF_OFFSET_CCK_8822B */
#define BIT_SHIFT_CCK_RXTSF_OFFSET_8822B 0
#define BIT_MASK_CCK_RXTSF_OFFSET_8822B 0xff
-#define BIT_CCK_RXTSF_OFFSET_8822B(x) (((x) & BIT_MASK_CCK_RXTSF_OFFSET_8822B) << BIT_SHIFT_CCK_RXTSF_OFFSET_8822B)
-#define BIT_GET_CCK_RXTSF_OFFSET_8822B(x) (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8822B) & BIT_MASK_CCK_RXTSF_OFFSET_8822B)
-
+#define BIT_CCK_RXTSF_OFFSET_8822B(x) \
+ (((x) & BIT_MASK_CCK_RXTSF_OFFSET_8822B) \
+ << BIT_SHIFT_CCK_RXTSF_OFFSET_8822B)
+#define BITS_CCK_RXTSF_OFFSET_8822B \
+ (BIT_MASK_CCK_RXTSF_OFFSET_8822B << BIT_SHIFT_CCK_RXTSF_OFFSET_8822B)
+#define BIT_CLEAR_CCK_RXTSF_OFFSET_8822B(x) \
+ ((x) & (~BITS_CCK_RXTSF_OFFSET_8822B))
+#define BIT_GET_CCK_RXTSF_OFFSET_8822B(x) \
+ (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8822B) & \
+ BIT_MASK_CCK_RXTSF_OFFSET_8822B)
+#define BIT_SET_CCK_RXTSF_OFFSET_8822B(x, v) \
+ (BIT_CLEAR_CCK_RXTSF_OFFSET_8822B(x) | BIT_CCK_RXTSF_OFFSET_8822B(v))
/* 2 REG_RXTSF_OFFSET_OFDM_8822B */
#define BIT_SHIFT_OFDM_RXTSF_OFFSET_8822B 0
#define BIT_MASK_OFDM_RXTSF_OFFSET_8822B 0xff
-#define BIT_OFDM_RXTSF_OFFSET_8822B(x) (((x) & BIT_MASK_OFDM_RXTSF_OFFSET_8822B) << BIT_SHIFT_OFDM_RXTSF_OFFSET_8822B)
-#define BIT_GET_OFDM_RXTSF_OFFSET_8822B(x) (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8822B) & BIT_MASK_OFDM_RXTSF_OFFSET_8822B)
-
+#define BIT_OFDM_RXTSF_OFFSET_8822B(x) \
+ (((x) & BIT_MASK_OFDM_RXTSF_OFFSET_8822B) \
+ << BIT_SHIFT_OFDM_RXTSF_OFFSET_8822B)
+#define BITS_OFDM_RXTSF_OFFSET_8822B \
+ (BIT_MASK_OFDM_RXTSF_OFFSET_8822B << BIT_SHIFT_OFDM_RXTSF_OFFSET_8822B)
+#define BIT_CLEAR_OFDM_RXTSF_OFFSET_8822B(x) \
+ ((x) & (~BITS_OFDM_RXTSF_OFFSET_8822B))
+#define BIT_GET_OFDM_RXTSF_OFFSET_8822B(x) \
+ (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8822B) & \
+ BIT_MASK_OFDM_RXTSF_OFFSET_8822B)
+#define BIT_SET_OFDM_RXTSF_OFFSET_8822B(x, v) \
+ (BIT_CLEAR_OFDM_RXTSF_OFFSET_8822B(x) | BIT_OFDM_RXTSF_OFFSET_8822B(v))
/* 2 REG_TSFTR_8822B */
#define BIT_SHIFT_TSF_TIMER_8822B 0
#define BIT_MASK_TSF_TIMER_8822B 0xffffffffffffffffL
-#define BIT_TSF_TIMER_8822B(x) (((x) & BIT_MASK_TSF_TIMER_8822B) << BIT_SHIFT_TSF_TIMER_8822B)
-#define BIT_GET_TSF_TIMER_8822B(x) (((x) >> BIT_SHIFT_TSF_TIMER_8822B) & BIT_MASK_TSF_TIMER_8822B)
-
+#define BIT_TSF_TIMER_8822B(x) \
+ (((x) & BIT_MASK_TSF_TIMER_8822B) << BIT_SHIFT_TSF_TIMER_8822B)
+#define BITS_TSF_TIMER_8822B \
+ (BIT_MASK_TSF_TIMER_8822B << BIT_SHIFT_TSF_TIMER_8822B)
+#define BIT_CLEAR_TSF_TIMER_8822B(x) ((x) & (~BITS_TSF_TIMER_8822B))
+#define BIT_GET_TSF_TIMER_8822B(x) \
+ (((x) >> BIT_SHIFT_TSF_TIMER_8822B) & BIT_MASK_TSF_TIMER_8822B)
+#define BIT_SET_TSF_TIMER_8822B(x, v) \
+ (BIT_CLEAR_TSF_TIMER_8822B(x) | BIT_TSF_TIMER_8822B(v))
/* 2 REG_FREERUN_CNT_8822B */
#define BIT_SHIFT_FREERUN_CNT_8822B 0
#define BIT_MASK_FREERUN_CNT_8822B 0xffffffffffffffffL
-#define BIT_FREERUN_CNT_8822B(x) (((x) & BIT_MASK_FREERUN_CNT_8822B) << BIT_SHIFT_FREERUN_CNT_8822B)
-#define BIT_GET_FREERUN_CNT_8822B(x) (((x) >> BIT_SHIFT_FREERUN_CNT_8822B) & BIT_MASK_FREERUN_CNT_8822B)
-
+#define BIT_FREERUN_CNT_8822B(x) \
+ (((x) & BIT_MASK_FREERUN_CNT_8822B) << BIT_SHIFT_FREERUN_CNT_8822B)
+#define BITS_FREERUN_CNT_8822B \
+ (BIT_MASK_FREERUN_CNT_8822B << BIT_SHIFT_FREERUN_CNT_8822B)
+#define BIT_CLEAR_FREERUN_CNT_8822B(x) ((x) & (~BITS_FREERUN_CNT_8822B))
+#define BIT_GET_FREERUN_CNT_8822B(x) \
+ (((x) >> BIT_SHIFT_FREERUN_CNT_8822B) & BIT_MASK_FREERUN_CNT_8822B)
+#define BIT_SET_FREERUN_CNT_8822B(x, v) \
+ (BIT_CLEAR_FREERUN_CNT_8822B(x) | BIT_FREERUN_CNT_8822B(v))
/* 2 REG_ATIMWND1_V1_8822B */
#define BIT_SHIFT_ATIMWND1_V1_8822B 0
#define BIT_MASK_ATIMWND1_V1_8822B 0xff
-#define BIT_ATIMWND1_V1_8822B(x) (((x) & BIT_MASK_ATIMWND1_V1_8822B) << BIT_SHIFT_ATIMWND1_V1_8822B)
-#define BIT_GET_ATIMWND1_V1_8822B(x) (((x) >> BIT_SHIFT_ATIMWND1_V1_8822B) & BIT_MASK_ATIMWND1_V1_8822B)
-
+#define BIT_ATIMWND1_V1_8822B(x) \
+ (((x) & BIT_MASK_ATIMWND1_V1_8822B) << BIT_SHIFT_ATIMWND1_V1_8822B)
+#define BITS_ATIMWND1_V1_8822B \
+ (BIT_MASK_ATIMWND1_V1_8822B << BIT_SHIFT_ATIMWND1_V1_8822B)
+#define BIT_CLEAR_ATIMWND1_V1_8822B(x) ((x) & (~BITS_ATIMWND1_V1_8822B))
+#define BIT_GET_ATIMWND1_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_ATIMWND1_V1_8822B) & BIT_MASK_ATIMWND1_V1_8822B)
+#define BIT_SET_ATIMWND1_V1_8822B(x, v) \
+ (BIT_CLEAR_ATIMWND1_V1_8822B(x) | BIT_ATIMWND1_V1_8822B(v))
/* 2 REG_TBTT_PROHIBIT_INFRA_8822B */
#define BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822B 0
#define BIT_MASK_TBTT_PROHIBIT_INFRA_8822B 0xff
-#define BIT_TBTT_PROHIBIT_INFRA_8822B(x) (((x) & BIT_MASK_TBTT_PROHIBIT_INFRA_8822B) << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822B)
-#define BIT_GET_TBTT_PROHIBIT_INFRA_8822B(x) (((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822B) & BIT_MASK_TBTT_PROHIBIT_INFRA_8822B)
-
+#define BIT_TBTT_PROHIBIT_INFRA_8822B(x) \
+ (((x) & BIT_MASK_TBTT_PROHIBIT_INFRA_8822B) \
+ << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822B)
+#define BITS_TBTT_PROHIBIT_INFRA_8822B \
+ (BIT_MASK_TBTT_PROHIBIT_INFRA_8822B \
+ << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822B)
+#define BIT_CLEAR_TBTT_PROHIBIT_INFRA_8822B(x) \
+ ((x) & (~BITS_TBTT_PROHIBIT_INFRA_8822B))
+#define BIT_GET_TBTT_PROHIBIT_INFRA_8822B(x) \
+ (((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822B) & \
+ BIT_MASK_TBTT_PROHIBIT_INFRA_8822B)
+#define BIT_SET_TBTT_PROHIBIT_INFRA_8822B(x, v) \
+ (BIT_CLEAR_TBTT_PROHIBIT_INFRA_8822B(x) | \
+ BIT_TBTT_PROHIBIT_INFRA_8822B(v))
/* 2 REG_CTWND_8822B */
#define BIT_SHIFT_CTWND_8822B 0
#define BIT_MASK_CTWND_8822B 0xff
-#define BIT_CTWND_8822B(x) (((x) & BIT_MASK_CTWND_8822B) << BIT_SHIFT_CTWND_8822B)
-#define BIT_GET_CTWND_8822B(x) (((x) >> BIT_SHIFT_CTWND_8822B) & BIT_MASK_CTWND_8822B)
-
+#define BIT_CTWND_8822B(x) \
+ (((x) & BIT_MASK_CTWND_8822B) << BIT_SHIFT_CTWND_8822B)
+#define BITS_CTWND_8822B (BIT_MASK_CTWND_8822B << BIT_SHIFT_CTWND_8822B)
+#define BIT_CLEAR_CTWND_8822B(x) ((x) & (~BITS_CTWND_8822B))
+#define BIT_GET_CTWND_8822B(x) \
+ (((x) >> BIT_SHIFT_CTWND_8822B) & BIT_MASK_CTWND_8822B)
+#define BIT_SET_CTWND_8822B(x, v) \
+ (BIT_CLEAR_CTWND_8822B(x) | BIT_CTWND_8822B(v))
/* 2 REG_BCNIVLCUNT_8822B */
#define BIT_SHIFT_BCNIVLCUNT_8822B 0
#define BIT_MASK_BCNIVLCUNT_8822B 0x7f
-#define BIT_BCNIVLCUNT_8822B(x) (((x) & BIT_MASK_BCNIVLCUNT_8822B) << BIT_SHIFT_BCNIVLCUNT_8822B)
-#define BIT_GET_BCNIVLCUNT_8822B(x) (((x) >> BIT_SHIFT_BCNIVLCUNT_8822B) & BIT_MASK_BCNIVLCUNT_8822B)
-
+#define BIT_BCNIVLCUNT_8822B(x) \
+ (((x) & BIT_MASK_BCNIVLCUNT_8822B) << BIT_SHIFT_BCNIVLCUNT_8822B)
+#define BITS_BCNIVLCUNT_8822B \
+ (BIT_MASK_BCNIVLCUNT_8822B << BIT_SHIFT_BCNIVLCUNT_8822B)
+#define BIT_CLEAR_BCNIVLCUNT_8822B(x) ((x) & (~BITS_BCNIVLCUNT_8822B))
+#define BIT_GET_BCNIVLCUNT_8822B(x) \
+ (((x) >> BIT_SHIFT_BCNIVLCUNT_8822B) & BIT_MASK_BCNIVLCUNT_8822B)
+#define BIT_SET_BCNIVLCUNT_8822B(x, v) \
+ (BIT_CLEAR_BCNIVLCUNT_8822B(x) | BIT_BCNIVLCUNT_8822B(v))
/* 2 REG_BCNDROPCTRL_8822B */
#define BIT_BEACON_DROP_EN_8822B BIT(7)
#define BIT_SHIFT_BEACON_DROP_IVL_8822B 0
#define BIT_MASK_BEACON_DROP_IVL_8822B 0x7f
-#define BIT_BEACON_DROP_IVL_8822B(x) (((x) & BIT_MASK_BEACON_DROP_IVL_8822B) << BIT_SHIFT_BEACON_DROP_IVL_8822B)
-#define BIT_GET_BEACON_DROP_IVL_8822B(x) (((x) >> BIT_SHIFT_BEACON_DROP_IVL_8822B) & BIT_MASK_BEACON_DROP_IVL_8822B)
-
+#define BIT_BEACON_DROP_IVL_8822B(x) \
+ (((x) & BIT_MASK_BEACON_DROP_IVL_8822B) \
+ << BIT_SHIFT_BEACON_DROP_IVL_8822B)
+#define BITS_BEACON_DROP_IVL_8822B \
+ (BIT_MASK_BEACON_DROP_IVL_8822B << BIT_SHIFT_BEACON_DROP_IVL_8822B)
+#define BIT_CLEAR_BEACON_DROP_IVL_8822B(x) ((x) & (~BITS_BEACON_DROP_IVL_8822B))
+#define BIT_GET_BEACON_DROP_IVL_8822B(x) \
+ (((x) >> BIT_SHIFT_BEACON_DROP_IVL_8822B) & \
+ BIT_MASK_BEACON_DROP_IVL_8822B)
+#define BIT_SET_BEACON_DROP_IVL_8822B(x, v) \
+ (BIT_CLEAR_BEACON_DROP_IVL_8822B(x) | BIT_BEACON_DROP_IVL_8822B(v))
/* 2 REG_HGQ_TIMEOUT_PERIOD_8822B */
#define BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822B 0
#define BIT_MASK_HGQ_TIMEOUT_PERIOD_8822B 0xff
-#define BIT_HGQ_TIMEOUT_PERIOD_8822B(x) (((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8822B) << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822B)
-#define BIT_GET_HGQ_TIMEOUT_PERIOD_8822B(x) (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822B) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8822B)
-
+#define BIT_HGQ_TIMEOUT_PERIOD_8822B(x) \
+ (((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8822B) \
+ << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822B)
+#define BITS_HGQ_TIMEOUT_PERIOD_8822B \
+ (BIT_MASK_HGQ_TIMEOUT_PERIOD_8822B \
+ << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822B)
+#define BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8822B(x) \
+ ((x) & (~BITS_HGQ_TIMEOUT_PERIOD_8822B))
+#define BIT_GET_HGQ_TIMEOUT_PERIOD_8822B(x) \
+ (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822B) & \
+ BIT_MASK_HGQ_TIMEOUT_PERIOD_8822B)
+#define BIT_SET_HGQ_TIMEOUT_PERIOD_8822B(x, v) \
+ (BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8822B(x) | \
+ BIT_HGQ_TIMEOUT_PERIOD_8822B(v))
/* 2 REG_TXCMD_TIMEOUT_PERIOD_8822B */
#define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822B 0
#define BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822B 0xff
-#define BIT_TXCMD_TIMEOUT_PERIOD_8822B(x) (((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822B) << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822B)
-#define BIT_GET_TXCMD_TIMEOUT_PERIOD_8822B(x) (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822B) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822B)
-
+#define BIT_TXCMD_TIMEOUT_PERIOD_8822B(x) \
+ (((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822B) \
+ << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822B)
+#define BITS_TXCMD_TIMEOUT_PERIOD_8822B \
+ (BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822B \
+ << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822B)
+#define BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8822B(x) \
+ ((x) & (~BITS_TXCMD_TIMEOUT_PERIOD_8822B))
+#define BIT_GET_TXCMD_TIMEOUT_PERIOD_8822B(x) \
+ (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822B) & \
+ BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822B)
+#define BIT_SET_TXCMD_TIMEOUT_PERIOD_8822B(x, v) \
+ (BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8822B(x) | \
+ BIT_TXCMD_TIMEOUT_PERIOD_8822B(v))
/* 2 REG_MISC_CTRL_8822B */
+#define BIT_AUTO_SYNC_BY_TBTT_8822B BIT(6)
#define BIT_DIS_TRX_CAL_BCN_8822B BIT(5)
#define BIT_DIS_TX_CAL_TBTT_8822B BIT(4)
#define BIT_EN_FREECNT_8822B BIT(3)
@@ -6881,9 +12148,18 @@
#define BIT_SHIFT_DIS_SECONDARY_CCA_8822B 0
#define BIT_MASK_DIS_SECONDARY_CCA_8822B 0x3
-#define BIT_DIS_SECONDARY_CCA_8822B(x) (((x) & BIT_MASK_DIS_SECONDARY_CCA_8822B) << BIT_SHIFT_DIS_SECONDARY_CCA_8822B)
-#define BIT_GET_DIS_SECONDARY_CCA_8822B(x) (((x) >> BIT_SHIFT_DIS_SECONDARY_CCA_8822B) & BIT_MASK_DIS_SECONDARY_CCA_8822B)
-
+#define BIT_DIS_SECONDARY_CCA_8822B(x) \
+ (((x) & BIT_MASK_DIS_SECONDARY_CCA_8822B) \
+ << BIT_SHIFT_DIS_SECONDARY_CCA_8822B)
+#define BITS_DIS_SECONDARY_CCA_8822B \
+ (BIT_MASK_DIS_SECONDARY_CCA_8822B << BIT_SHIFT_DIS_SECONDARY_CCA_8822B)
+#define BIT_CLEAR_DIS_SECONDARY_CCA_8822B(x) \
+ ((x) & (~BITS_DIS_SECONDARY_CCA_8822B))
+#define BIT_GET_DIS_SECONDARY_CCA_8822B(x) \
+ (((x) >> BIT_SHIFT_DIS_SECONDARY_CCA_8822B) & \
+ BIT_MASK_DIS_SECONDARY_CCA_8822B)
+#define BIT_SET_DIS_SECONDARY_CCA_8822B(x, v) \
+ (BIT_CLEAR_DIS_SECONDARY_CCA_8822B(x) | BIT_DIS_SECONDARY_CCA_8822B(v))
/* 2 REG_BCN_CTRL_CLINT1_8822B */
#define BIT_CLI1_DIS_RX_BSSID_FIT_8822B BIT(6)
@@ -6915,9 +12191,15 @@
#define BIT_SHIFT_PORT_SEL_8822B 0
#define BIT_MASK_PORT_SEL_8822B 0x7
-#define BIT_PORT_SEL_8822B(x) (((x) & BIT_MASK_PORT_SEL_8822B) << BIT_SHIFT_PORT_SEL_8822B)
-#define BIT_GET_PORT_SEL_8822B(x) (((x) >> BIT_SHIFT_PORT_SEL_8822B) & BIT_MASK_PORT_SEL_8822B)
-
+#define BIT_PORT_SEL_8822B(x) \
+ (((x) & BIT_MASK_PORT_SEL_8822B) << BIT_SHIFT_PORT_SEL_8822B)
+#define BITS_PORT_SEL_8822B \
+ (BIT_MASK_PORT_SEL_8822B << BIT_SHIFT_PORT_SEL_8822B)
+#define BIT_CLEAR_PORT_SEL_8822B(x) ((x) & (~BITS_PORT_SEL_8822B))
+#define BIT_GET_PORT_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_PORT_SEL_8822B) & BIT_MASK_PORT_SEL_8822B)
+#define BIT_SET_PORT_SEL_8822B(x, v) \
+ (BIT_CLEAR_PORT_SEL_8822B(x) | BIT_PORT_SEL_8822B(v))
/* 2 REG_P2PPS1_SPEC_STATE_8822B */
#define BIT_P2P1_SPEC_POWER_STATE_8822B BIT(7)
@@ -6963,57 +12245,99 @@
#define BIT_SHIFT_PSTIMER0_INT_8822B 5
#define BIT_MASK_PSTIMER0_INT_8822B 0x7ffffff
-#define BIT_PSTIMER0_INT_8822B(x) (((x) & BIT_MASK_PSTIMER0_INT_8822B) << BIT_SHIFT_PSTIMER0_INT_8822B)
-#define BIT_GET_PSTIMER0_INT_8822B(x) (((x) >> BIT_SHIFT_PSTIMER0_INT_8822B) & BIT_MASK_PSTIMER0_INT_8822B)
-
+#define BIT_PSTIMER0_INT_8822B(x) \
+ (((x) & BIT_MASK_PSTIMER0_INT_8822B) << BIT_SHIFT_PSTIMER0_INT_8822B)
+#define BITS_PSTIMER0_INT_8822B \
+ (BIT_MASK_PSTIMER0_INT_8822B << BIT_SHIFT_PSTIMER0_INT_8822B)
+#define BIT_CLEAR_PSTIMER0_INT_8822B(x) ((x) & (~BITS_PSTIMER0_INT_8822B))
+#define BIT_GET_PSTIMER0_INT_8822B(x) \
+ (((x) >> BIT_SHIFT_PSTIMER0_INT_8822B) & BIT_MASK_PSTIMER0_INT_8822B)
+#define BIT_SET_PSTIMER0_INT_8822B(x, v) \
+ (BIT_CLEAR_PSTIMER0_INT_8822B(x) | BIT_PSTIMER0_INT_8822B(v))
/* 2 REG_PS_TIMER1_8822B */
#define BIT_SHIFT_PSTIMER1_INT_8822B 5
#define BIT_MASK_PSTIMER1_INT_8822B 0x7ffffff
-#define BIT_PSTIMER1_INT_8822B(x) (((x) & BIT_MASK_PSTIMER1_INT_8822B) << BIT_SHIFT_PSTIMER1_INT_8822B)
-#define BIT_GET_PSTIMER1_INT_8822B(x) (((x) >> BIT_SHIFT_PSTIMER1_INT_8822B) & BIT_MASK_PSTIMER1_INT_8822B)
-
+#define BIT_PSTIMER1_INT_8822B(x) \
+ (((x) & BIT_MASK_PSTIMER1_INT_8822B) << BIT_SHIFT_PSTIMER1_INT_8822B)
+#define BITS_PSTIMER1_INT_8822B \
+ (BIT_MASK_PSTIMER1_INT_8822B << BIT_SHIFT_PSTIMER1_INT_8822B)
+#define BIT_CLEAR_PSTIMER1_INT_8822B(x) ((x) & (~BITS_PSTIMER1_INT_8822B))
+#define BIT_GET_PSTIMER1_INT_8822B(x) \
+ (((x) >> BIT_SHIFT_PSTIMER1_INT_8822B) & BIT_MASK_PSTIMER1_INT_8822B)
+#define BIT_SET_PSTIMER1_INT_8822B(x, v) \
+ (BIT_CLEAR_PSTIMER1_INT_8822B(x) | BIT_PSTIMER1_INT_8822B(v))
/* 2 REG_PS_TIMER2_8822B */
#define BIT_SHIFT_PSTIMER2_INT_8822B 5
#define BIT_MASK_PSTIMER2_INT_8822B 0x7ffffff
-#define BIT_PSTIMER2_INT_8822B(x) (((x) & BIT_MASK_PSTIMER2_INT_8822B) << BIT_SHIFT_PSTIMER2_INT_8822B)
-#define BIT_GET_PSTIMER2_INT_8822B(x) (((x) >> BIT_SHIFT_PSTIMER2_INT_8822B) & BIT_MASK_PSTIMER2_INT_8822B)
-
+#define BIT_PSTIMER2_INT_8822B(x) \
+ (((x) & BIT_MASK_PSTIMER2_INT_8822B) << BIT_SHIFT_PSTIMER2_INT_8822B)
+#define BITS_PSTIMER2_INT_8822B \
+ (BIT_MASK_PSTIMER2_INT_8822B << BIT_SHIFT_PSTIMER2_INT_8822B)
+#define BIT_CLEAR_PSTIMER2_INT_8822B(x) ((x) & (~BITS_PSTIMER2_INT_8822B))
+#define BIT_GET_PSTIMER2_INT_8822B(x) \
+ (((x) >> BIT_SHIFT_PSTIMER2_INT_8822B) & BIT_MASK_PSTIMER2_INT_8822B)
+#define BIT_SET_PSTIMER2_INT_8822B(x, v) \
+ (BIT_CLEAR_PSTIMER2_INT_8822B(x) | BIT_PSTIMER2_INT_8822B(v))
/* 2 REG_TBTT_CTN_AREA_8822B */
#define BIT_SHIFT_TBTT_CTN_AREA_8822B 0
#define BIT_MASK_TBTT_CTN_AREA_8822B 0xff
-#define BIT_TBTT_CTN_AREA_8822B(x) (((x) & BIT_MASK_TBTT_CTN_AREA_8822B) << BIT_SHIFT_TBTT_CTN_AREA_8822B)
-#define BIT_GET_TBTT_CTN_AREA_8822B(x) (((x) >> BIT_SHIFT_TBTT_CTN_AREA_8822B) & BIT_MASK_TBTT_CTN_AREA_8822B)
-
+#define BIT_TBTT_CTN_AREA_8822B(x) \
+ (((x) & BIT_MASK_TBTT_CTN_AREA_8822B) << BIT_SHIFT_TBTT_CTN_AREA_8822B)
+#define BITS_TBTT_CTN_AREA_8822B \
+ (BIT_MASK_TBTT_CTN_AREA_8822B << BIT_SHIFT_TBTT_CTN_AREA_8822B)
+#define BIT_CLEAR_TBTT_CTN_AREA_8822B(x) ((x) & (~BITS_TBTT_CTN_AREA_8822B))
+#define BIT_GET_TBTT_CTN_AREA_8822B(x) \
+ (((x) >> BIT_SHIFT_TBTT_CTN_AREA_8822B) & BIT_MASK_TBTT_CTN_AREA_8822B)
+#define BIT_SET_TBTT_CTN_AREA_8822B(x, v) \
+ (BIT_CLEAR_TBTT_CTN_AREA_8822B(x) | BIT_TBTT_CTN_AREA_8822B(v))
/* 2 REG_FORCE_BCN_IFS_8822B */
#define BIT_SHIFT_FORCE_BCN_IFS_8822B 0
#define BIT_MASK_FORCE_BCN_IFS_8822B 0xff
-#define BIT_FORCE_BCN_IFS_8822B(x) (((x) & BIT_MASK_FORCE_BCN_IFS_8822B) << BIT_SHIFT_FORCE_BCN_IFS_8822B)
-#define BIT_GET_FORCE_BCN_IFS_8822B(x) (((x) >> BIT_SHIFT_FORCE_BCN_IFS_8822B) & BIT_MASK_FORCE_BCN_IFS_8822B)
-
+#define BIT_FORCE_BCN_IFS_8822B(x) \
+ (((x) & BIT_MASK_FORCE_BCN_IFS_8822B) << BIT_SHIFT_FORCE_BCN_IFS_8822B)
+#define BITS_FORCE_BCN_IFS_8822B \
+ (BIT_MASK_FORCE_BCN_IFS_8822B << BIT_SHIFT_FORCE_BCN_IFS_8822B)
+#define BIT_CLEAR_FORCE_BCN_IFS_8822B(x) ((x) & (~BITS_FORCE_BCN_IFS_8822B))
+#define BIT_GET_FORCE_BCN_IFS_8822B(x) \
+ (((x) >> BIT_SHIFT_FORCE_BCN_IFS_8822B) & BIT_MASK_FORCE_BCN_IFS_8822B)
+#define BIT_SET_FORCE_BCN_IFS_8822B(x, v) \
+ (BIT_CLEAR_FORCE_BCN_IFS_8822B(x) | BIT_FORCE_BCN_IFS_8822B(v))
/* 2 REG_TXOP_MIN_8822B */
#define BIT_SHIFT_TXOP_MIN_8822B 0
#define BIT_MASK_TXOP_MIN_8822B 0x3fff
-#define BIT_TXOP_MIN_8822B(x) (((x) & BIT_MASK_TXOP_MIN_8822B) << BIT_SHIFT_TXOP_MIN_8822B)
-#define BIT_GET_TXOP_MIN_8822B(x) (((x) >> BIT_SHIFT_TXOP_MIN_8822B) & BIT_MASK_TXOP_MIN_8822B)
-
+#define BIT_TXOP_MIN_8822B(x) \
+ (((x) & BIT_MASK_TXOP_MIN_8822B) << BIT_SHIFT_TXOP_MIN_8822B)
+#define BITS_TXOP_MIN_8822B \
+ (BIT_MASK_TXOP_MIN_8822B << BIT_SHIFT_TXOP_MIN_8822B)
+#define BIT_CLEAR_TXOP_MIN_8822B(x) ((x) & (~BITS_TXOP_MIN_8822B))
+#define BIT_GET_TXOP_MIN_8822B(x) \
+ (((x) >> BIT_SHIFT_TXOP_MIN_8822B) & BIT_MASK_TXOP_MIN_8822B)
+#define BIT_SET_TXOP_MIN_8822B(x, v) \
+ (BIT_CLEAR_TXOP_MIN_8822B(x) | BIT_TXOP_MIN_8822B(v))
/* 2 REG_PRE_BKF_TIME_8822B */
#define BIT_SHIFT_PRE_BKF_TIME_8822B 0
#define BIT_MASK_PRE_BKF_TIME_8822B 0xff
-#define BIT_PRE_BKF_TIME_8822B(x) (((x) & BIT_MASK_PRE_BKF_TIME_8822B) << BIT_SHIFT_PRE_BKF_TIME_8822B)
-#define BIT_GET_PRE_BKF_TIME_8822B(x) (((x) >> BIT_SHIFT_PRE_BKF_TIME_8822B) & BIT_MASK_PRE_BKF_TIME_8822B)
-
+#define BIT_PRE_BKF_TIME_8822B(x) \
+ (((x) & BIT_MASK_PRE_BKF_TIME_8822B) << BIT_SHIFT_PRE_BKF_TIME_8822B)
+#define BITS_PRE_BKF_TIME_8822B \
+ (BIT_MASK_PRE_BKF_TIME_8822B << BIT_SHIFT_PRE_BKF_TIME_8822B)
+#define BIT_CLEAR_PRE_BKF_TIME_8822B(x) ((x) & (~BITS_PRE_BKF_TIME_8822B))
+#define BIT_GET_PRE_BKF_TIME_8822B(x) \
+ (((x) >> BIT_SHIFT_PRE_BKF_TIME_8822B) & BIT_MASK_PRE_BKF_TIME_8822B)
+#define BIT_SET_PRE_BKF_TIME_8822B(x, v) \
+ (BIT_CLEAR_PRE_BKF_TIME_8822B(x) | BIT_PRE_BKF_TIME_8822B(v))
/* 2 REG_CROSS_TXOP_CTRL_8822B */
#define BIT_DTIM_BYPASS_8822B BIT(2)
@@ -7024,57 +12348,99 @@
#define BIT_SHIFT_ATIMWND2_8822B 0
#define BIT_MASK_ATIMWND2_8822B 0xff
-#define BIT_ATIMWND2_8822B(x) (((x) & BIT_MASK_ATIMWND2_8822B) << BIT_SHIFT_ATIMWND2_8822B)
-#define BIT_GET_ATIMWND2_8822B(x) (((x) >> BIT_SHIFT_ATIMWND2_8822B) & BIT_MASK_ATIMWND2_8822B)
-
+#define BIT_ATIMWND2_8822B(x) \
+ (((x) & BIT_MASK_ATIMWND2_8822B) << BIT_SHIFT_ATIMWND2_8822B)
+#define BITS_ATIMWND2_8822B \
+ (BIT_MASK_ATIMWND2_8822B << BIT_SHIFT_ATIMWND2_8822B)
+#define BIT_CLEAR_ATIMWND2_8822B(x) ((x) & (~BITS_ATIMWND2_8822B))
+#define BIT_GET_ATIMWND2_8822B(x) \
+ (((x) >> BIT_SHIFT_ATIMWND2_8822B) & BIT_MASK_ATIMWND2_8822B)
+#define BIT_SET_ATIMWND2_8822B(x, v) \
+ (BIT_CLEAR_ATIMWND2_8822B(x) | BIT_ATIMWND2_8822B(v))
/* 2 REG_ATIMWND3_8822B */
#define BIT_SHIFT_ATIMWND3_8822B 0
#define BIT_MASK_ATIMWND3_8822B 0xff
-#define BIT_ATIMWND3_8822B(x) (((x) & BIT_MASK_ATIMWND3_8822B) << BIT_SHIFT_ATIMWND3_8822B)
-#define BIT_GET_ATIMWND3_8822B(x) (((x) >> BIT_SHIFT_ATIMWND3_8822B) & BIT_MASK_ATIMWND3_8822B)
-
+#define BIT_ATIMWND3_8822B(x) \
+ (((x) & BIT_MASK_ATIMWND3_8822B) << BIT_SHIFT_ATIMWND3_8822B)
+#define BITS_ATIMWND3_8822B \
+ (BIT_MASK_ATIMWND3_8822B << BIT_SHIFT_ATIMWND3_8822B)
+#define BIT_CLEAR_ATIMWND3_8822B(x) ((x) & (~BITS_ATIMWND3_8822B))
+#define BIT_GET_ATIMWND3_8822B(x) \
+ (((x) >> BIT_SHIFT_ATIMWND3_8822B) & BIT_MASK_ATIMWND3_8822B)
+#define BIT_SET_ATIMWND3_8822B(x, v) \
+ (BIT_CLEAR_ATIMWND3_8822B(x) | BIT_ATIMWND3_8822B(v))
/* 2 REG_ATIMWND4_8822B */
#define BIT_SHIFT_ATIMWND4_8822B 0
#define BIT_MASK_ATIMWND4_8822B 0xff
-#define BIT_ATIMWND4_8822B(x) (((x) & BIT_MASK_ATIMWND4_8822B) << BIT_SHIFT_ATIMWND4_8822B)
-#define BIT_GET_ATIMWND4_8822B(x) (((x) >> BIT_SHIFT_ATIMWND4_8822B) & BIT_MASK_ATIMWND4_8822B)
-
+#define BIT_ATIMWND4_8822B(x) \
+ (((x) & BIT_MASK_ATIMWND4_8822B) << BIT_SHIFT_ATIMWND4_8822B)
+#define BITS_ATIMWND4_8822B \
+ (BIT_MASK_ATIMWND4_8822B << BIT_SHIFT_ATIMWND4_8822B)
+#define BIT_CLEAR_ATIMWND4_8822B(x) ((x) & (~BITS_ATIMWND4_8822B))
+#define BIT_GET_ATIMWND4_8822B(x) \
+ (((x) >> BIT_SHIFT_ATIMWND4_8822B) & BIT_MASK_ATIMWND4_8822B)
+#define BIT_SET_ATIMWND4_8822B(x, v) \
+ (BIT_CLEAR_ATIMWND4_8822B(x) | BIT_ATIMWND4_8822B(v))
/* 2 REG_ATIMWND5_8822B */
#define BIT_SHIFT_ATIMWND5_8822B 0
#define BIT_MASK_ATIMWND5_8822B 0xff
-#define BIT_ATIMWND5_8822B(x) (((x) & BIT_MASK_ATIMWND5_8822B) << BIT_SHIFT_ATIMWND5_8822B)
-#define BIT_GET_ATIMWND5_8822B(x) (((x) >> BIT_SHIFT_ATIMWND5_8822B) & BIT_MASK_ATIMWND5_8822B)
-
+#define BIT_ATIMWND5_8822B(x) \
+ (((x) & BIT_MASK_ATIMWND5_8822B) << BIT_SHIFT_ATIMWND5_8822B)
+#define BITS_ATIMWND5_8822B \
+ (BIT_MASK_ATIMWND5_8822B << BIT_SHIFT_ATIMWND5_8822B)
+#define BIT_CLEAR_ATIMWND5_8822B(x) ((x) & (~BITS_ATIMWND5_8822B))
+#define BIT_GET_ATIMWND5_8822B(x) \
+ (((x) >> BIT_SHIFT_ATIMWND5_8822B) & BIT_MASK_ATIMWND5_8822B)
+#define BIT_SET_ATIMWND5_8822B(x, v) \
+ (BIT_CLEAR_ATIMWND5_8822B(x) | BIT_ATIMWND5_8822B(v))
/* 2 REG_ATIMWND6_8822B */
#define BIT_SHIFT_ATIMWND6_8822B 0
#define BIT_MASK_ATIMWND6_8822B 0xff
-#define BIT_ATIMWND6_8822B(x) (((x) & BIT_MASK_ATIMWND6_8822B) << BIT_SHIFT_ATIMWND6_8822B)
-#define BIT_GET_ATIMWND6_8822B(x) (((x) >> BIT_SHIFT_ATIMWND6_8822B) & BIT_MASK_ATIMWND6_8822B)
-
+#define BIT_ATIMWND6_8822B(x) \
+ (((x) & BIT_MASK_ATIMWND6_8822B) << BIT_SHIFT_ATIMWND6_8822B)
+#define BITS_ATIMWND6_8822B \
+ (BIT_MASK_ATIMWND6_8822B << BIT_SHIFT_ATIMWND6_8822B)
+#define BIT_CLEAR_ATIMWND6_8822B(x) ((x) & (~BITS_ATIMWND6_8822B))
+#define BIT_GET_ATIMWND6_8822B(x) \
+ (((x) >> BIT_SHIFT_ATIMWND6_8822B) & BIT_MASK_ATIMWND6_8822B)
+#define BIT_SET_ATIMWND6_8822B(x, v) \
+ (BIT_CLEAR_ATIMWND6_8822B(x) | BIT_ATIMWND6_8822B(v))
/* 2 REG_ATIMWND7_8822B */
#define BIT_SHIFT_ATIMWND7_8822B 0
#define BIT_MASK_ATIMWND7_8822B 0xff
-#define BIT_ATIMWND7_8822B(x) (((x) & BIT_MASK_ATIMWND7_8822B) << BIT_SHIFT_ATIMWND7_8822B)
-#define BIT_GET_ATIMWND7_8822B(x) (((x) >> BIT_SHIFT_ATIMWND7_8822B) & BIT_MASK_ATIMWND7_8822B)
-
+#define BIT_ATIMWND7_8822B(x) \
+ (((x) & BIT_MASK_ATIMWND7_8822B) << BIT_SHIFT_ATIMWND7_8822B)
+#define BITS_ATIMWND7_8822B \
+ (BIT_MASK_ATIMWND7_8822B << BIT_SHIFT_ATIMWND7_8822B)
+#define BIT_CLEAR_ATIMWND7_8822B(x) ((x) & (~BITS_ATIMWND7_8822B))
+#define BIT_GET_ATIMWND7_8822B(x) \
+ (((x) >> BIT_SHIFT_ATIMWND7_8822B) & BIT_MASK_ATIMWND7_8822B)
+#define BIT_SET_ATIMWND7_8822B(x, v) \
+ (BIT_CLEAR_ATIMWND7_8822B(x) | BIT_ATIMWND7_8822B(v))
/* 2 REG_ATIMUGT_8822B */
#define BIT_SHIFT_ATIM_URGENT_8822B 0
#define BIT_MASK_ATIM_URGENT_8822B 0xff
-#define BIT_ATIM_URGENT_8822B(x) (((x) & BIT_MASK_ATIM_URGENT_8822B) << BIT_SHIFT_ATIM_URGENT_8822B)
-#define BIT_GET_ATIM_URGENT_8822B(x) (((x) >> BIT_SHIFT_ATIM_URGENT_8822B) & BIT_MASK_ATIM_URGENT_8822B)
-
+#define BIT_ATIM_URGENT_8822B(x) \
+ (((x) & BIT_MASK_ATIM_URGENT_8822B) << BIT_SHIFT_ATIM_URGENT_8822B)
+#define BITS_ATIM_URGENT_8822B \
+ (BIT_MASK_ATIM_URGENT_8822B << BIT_SHIFT_ATIM_URGENT_8822B)
+#define BIT_CLEAR_ATIM_URGENT_8822B(x) ((x) & (~BITS_ATIM_URGENT_8822B))
+#define BIT_GET_ATIM_URGENT_8822B(x) \
+ (((x) >> BIT_SHIFT_ATIM_URGENT_8822B) & BIT_MASK_ATIM_URGENT_8822B)
+#define BIT_SET_ATIM_URGENT_8822B(x, v) \
+ (BIT_CLEAR_ATIM_URGENT_8822B(x) | BIT_ATIM_URGENT_8822B(v))
/* 2 REG_HIQ_NO_LMT_EN_8822B */
#define BIT_HIQ_NO_LMT_EN_VAP7_8822B BIT(7)
@@ -7090,65 +12456,129 @@
#define BIT_SHIFT_DTIM_COUNT_ROOT_8822B 0
#define BIT_MASK_DTIM_COUNT_ROOT_8822B 0xff
-#define BIT_DTIM_COUNT_ROOT_8822B(x) (((x) & BIT_MASK_DTIM_COUNT_ROOT_8822B) << BIT_SHIFT_DTIM_COUNT_ROOT_8822B)
-#define BIT_GET_DTIM_COUNT_ROOT_8822B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_ROOT_8822B) & BIT_MASK_DTIM_COUNT_ROOT_8822B)
-
+#define BIT_DTIM_COUNT_ROOT_8822B(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_ROOT_8822B) \
+ << BIT_SHIFT_DTIM_COUNT_ROOT_8822B)
+#define BITS_DTIM_COUNT_ROOT_8822B \
+ (BIT_MASK_DTIM_COUNT_ROOT_8822B << BIT_SHIFT_DTIM_COUNT_ROOT_8822B)
+#define BIT_CLEAR_DTIM_COUNT_ROOT_8822B(x) ((x) & (~BITS_DTIM_COUNT_ROOT_8822B))
+#define BIT_GET_DTIM_COUNT_ROOT_8822B(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_ROOT_8822B) & \
+ BIT_MASK_DTIM_COUNT_ROOT_8822B)
+#define BIT_SET_DTIM_COUNT_ROOT_8822B(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_ROOT_8822B(x) | BIT_DTIM_COUNT_ROOT_8822B(v))
/* 2 REG_DTIM_COUNTER_VAP1_8822B */
#define BIT_SHIFT_DTIM_COUNT_VAP1_8822B 0
#define BIT_MASK_DTIM_COUNT_VAP1_8822B 0xff
-#define BIT_DTIM_COUNT_VAP1_8822B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP1_8822B) << BIT_SHIFT_DTIM_COUNT_VAP1_8822B)
-#define BIT_GET_DTIM_COUNT_VAP1_8822B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP1_8822B) & BIT_MASK_DTIM_COUNT_VAP1_8822B)
-
+#define BIT_DTIM_COUNT_VAP1_8822B(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_VAP1_8822B) \
+ << BIT_SHIFT_DTIM_COUNT_VAP1_8822B)
+#define BITS_DTIM_COUNT_VAP1_8822B \
+ (BIT_MASK_DTIM_COUNT_VAP1_8822B << BIT_SHIFT_DTIM_COUNT_VAP1_8822B)
+#define BIT_CLEAR_DTIM_COUNT_VAP1_8822B(x) ((x) & (~BITS_DTIM_COUNT_VAP1_8822B))
+#define BIT_GET_DTIM_COUNT_VAP1_8822B(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP1_8822B) & \
+ BIT_MASK_DTIM_COUNT_VAP1_8822B)
+#define BIT_SET_DTIM_COUNT_VAP1_8822B(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_VAP1_8822B(x) | BIT_DTIM_COUNT_VAP1_8822B(v))
/* 2 REG_DTIM_COUNTER_VAP2_8822B */
#define BIT_SHIFT_DTIM_COUNT_VAP2_8822B 0
#define BIT_MASK_DTIM_COUNT_VAP2_8822B 0xff
-#define BIT_DTIM_COUNT_VAP2_8822B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP2_8822B) << BIT_SHIFT_DTIM_COUNT_VAP2_8822B)
-#define BIT_GET_DTIM_COUNT_VAP2_8822B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP2_8822B) & BIT_MASK_DTIM_COUNT_VAP2_8822B)
-
+#define BIT_DTIM_COUNT_VAP2_8822B(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_VAP2_8822B) \
+ << BIT_SHIFT_DTIM_COUNT_VAP2_8822B)
+#define BITS_DTIM_COUNT_VAP2_8822B \
+ (BIT_MASK_DTIM_COUNT_VAP2_8822B << BIT_SHIFT_DTIM_COUNT_VAP2_8822B)
+#define BIT_CLEAR_DTIM_COUNT_VAP2_8822B(x) ((x) & (~BITS_DTIM_COUNT_VAP2_8822B))
+#define BIT_GET_DTIM_COUNT_VAP2_8822B(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP2_8822B) & \
+ BIT_MASK_DTIM_COUNT_VAP2_8822B)
+#define BIT_SET_DTIM_COUNT_VAP2_8822B(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_VAP2_8822B(x) | BIT_DTIM_COUNT_VAP2_8822B(v))
/* 2 REG_DTIM_COUNTER_VAP3_8822B */
#define BIT_SHIFT_DTIM_COUNT_VAP3_8822B 0
#define BIT_MASK_DTIM_COUNT_VAP3_8822B 0xff
-#define BIT_DTIM_COUNT_VAP3_8822B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP3_8822B) << BIT_SHIFT_DTIM_COUNT_VAP3_8822B)
-#define BIT_GET_DTIM_COUNT_VAP3_8822B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP3_8822B) & BIT_MASK_DTIM_COUNT_VAP3_8822B)
-
+#define BIT_DTIM_COUNT_VAP3_8822B(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_VAP3_8822B) \
+ << BIT_SHIFT_DTIM_COUNT_VAP3_8822B)
+#define BITS_DTIM_COUNT_VAP3_8822B \
+ (BIT_MASK_DTIM_COUNT_VAP3_8822B << BIT_SHIFT_DTIM_COUNT_VAP3_8822B)
+#define BIT_CLEAR_DTIM_COUNT_VAP3_8822B(x) ((x) & (~BITS_DTIM_COUNT_VAP3_8822B))
+#define BIT_GET_DTIM_COUNT_VAP3_8822B(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP3_8822B) & \
+ BIT_MASK_DTIM_COUNT_VAP3_8822B)
+#define BIT_SET_DTIM_COUNT_VAP3_8822B(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_VAP3_8822B(x) | BIT_DTIM_COUNT_VAP3_8822B(v))
/* 2 REG_DTIM_COUNTER_VAP4_8822B */
#define BIT_SHIFT_DTIM_COUNT_VAP4_8822B 0
#define BIT_MASK_DTIM_COUNT_VAP4_8822B 0xff
-#define BIT_DTIM_COUNT_VAP4_8822B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP4_8822B) << BIT_SHIFT_DTIM_COUNT_VAP4_8822B)
-#define BIT_GET_DTIM_COUNT_VAP4_8822B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP4_8822B) & BIT_MASK_DTIM_COUNT_VAP4_8822B)
-
+#define BIT_DTIM_COUNT_VAP4_8822B(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_VAP4_8822B) \
+ << BIT_SHIFT_DTIM_COUNT_VAP4_8822B)
+#define BITS_DTIM_COUNT_VAP4_8822B \
+ (BIT_MASK_DTIM_COUNT_VAP4_8822B << BIT_SHIFT_DTIM_COUNT_VAP4_8822B)
+#define BIT_CLEAR_DTIM_COUNT_VAP4_8822B(x) ((x) & (~BITS_DTIM_COUNT_VAP4_8822B))
+#define BIT_GET_DTIM_COUNT_VAP4_8822B(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP4_8822B) & \
+ BIT_MASK_DTIM_COUNT_VAP4_8822B)
+#define BIT_SET_DTIM_COUNT_VAP4_8822B(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_VAP4_8822B(x) | BIT_DTIM_COUNT_VAP4_8822B(v))
/* 2 REG_DTIM_COUNTER_VAP5_8822B */
#define BIT_SHIFT_DTIM_COUNT_VAP5_8822B 0
#define BIT_MASK_DTIM_COUNT_VAP5_8822B 0xff
-#define BIT_DTIM_COUNT_VAP5_8822B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP5_8822B) << BIT_SHIFT_DTIM_COUNT_VAP5_8822B)
-#define BIT_GET_DTIM_COUNT_VAP5_8822B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP5_8822B) & BIT_MASK_DTIM_COUNT_VAP5_8822B)
-
+#define BIT_DTIM_COUNT_VAP5_8822B(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_VAP5_8822B) \
+ << BIT_SHIFT_DTIM_COUNT_VAP5_8822B)
+#define BITS_DTIM_COUNT_VAP5_8822B \
+ (BIT_MASK_DTIM_COUNT_VAP5_8822B << BIT_SHIFT_DTIM_COUNT_VAP5_8822B)
+#define BIT_CLEAR_DTIM_COUNT_VAP5_8822B(x) ((x) & (~BITS_DTIM_COUNT_VAP5_8822B))
+#define BIT_GET_DTIM_COUNT_VAP5_8822B(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP5_8822B) & \
+ BIT_MASK_DTIM_COUNT_VAP5_8822B)
+#define BIT_SET_DTIM_COUNT_VAP5_8822B(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_VAP5_8822B(x) | BIT_DTIM_COUNT_VAP5_8822B(v))
/* 2 REG_DTIM_COUNTER_VAP6_8822B */
#define BIT_SHIFT_DTIM_COUNT_VAP6_8822B 0
#define BIT_MASK_DTIM_COUNT_VAP6_8822B 0xff
-#define BIT_DTIM_COUNT_VAP6_8822B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP6_8822B) << BIT_SHIFT_DTIM_COUNT_VAP6_8822B)
-#define BIT_GET_DTIM_COUNT_VAP6_8822B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP6_8822B) & BIT_MASK_DTIM_COUNT_VAP6_8822B)
-
+#define BIT_DTIM_COUNT_VAP6_8822B(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_VAP6_8822B) \
+ << BIT_SHIFT_DTIM_COUNT_VAP6_8822B)
+#define BITS_DTIM_COUNT_VAP6_8822B \
+ (BIT_MASK_DTIM_COUNT_VAP6_8822B << BIT_SHIFT_DTIM_COUNT_VAP6_8822B)
+#define BIT_CLEAR_DTIM_COUNT_VAP6_8822B(x) ((x) & (~BITS_DTIM_COUNT_VAP6_8822B))
+#define BIT_GET_DTIM_COUNT_VAP6_8822B(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP6_8822B) & \
+ BIT_MASK_DTIM_COUNT_VAP6_8822B)
+#define BIT_SET_DTIM_COUNT_VAP6_8822B(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_VAP6_8822B(x) | BIT_DTIM_COUNT_VAP6_8822B(v))
/* 2 REG_DTIM_COUNTER_VAP7_8822B */
#define BIT_SHIFT_DTIM_COUNT_VAP7_8822B 0
#define BIT_MASK_DTIM_COUNT_VAP7_8822B 0xff
-#define BIT_DTIM_COUNT_VAP7_8822B(x) (((x) & BIT_MASK_DTIM_COUNT_VAP7_8822B) << BIT_SHIFT_DTIM_COUNT_VAP7_8822B)
-#define BIT_GET_DTIM_COUNT_VAP7_8822B(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP7_8822B) & BIT_MASK_DTIM_COUNT_VAP7_8822B)
-
+#define BIT_DTIM_COUNT_VAP7_8822B(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_VAP7_8822B) \
+ << BIT_SHIFT_DTIM_COUNT_VAP7_8822B)
+#define BITS_DTIM_COUNT_VAP7_8822B \
+ (BIT_MASK_DTIM_COUNT_VAP7_8822B << BIT_SHIFT_DTIM_COUNT_VAP7_8822B)
+#define BIT_CLEAR_DTIM_COUNT_VAP7_8822B(x) ((x) & (~BITS_DTIM_COUNT_VAP7_8822B))
+#define BIT_GET_DTIM_COUNT_VAP7_8822B(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP7_8822B) & \
+ BIT_MASK_DTIM_COUNT_VAP7_8822B)
+#define BIT_SET_DTIM_COUNT_VAP7_8822B(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_VAP7_8822B(x) | BIT_DTIM_COUNT_VAP7_8822B(v))
/* 2 REG_DIS_ATIM_8822B */
#define BIT_DIS_ATIM_VAP7_8822B BIT(7)
@@ -7164,15 +12594,29 @@
#define BIT_SHIFT_TSFT_SEL_TIMER1_8822B 3
#define BIT_MASK_TSFT_SEL_TIMER1_8822B 0x7
-#define BIT_TSFT_SEL_TIMER1_8822B(x) (((x) & BIT_MASK_TSFT_SEL_TIMER1_8822B) << BIT_SHIFT_TSFT_SEL_TIMER1_8822B)
-#define BIT_GET_TSFT_SEL_TIMER1_8822B(x) (((x) >> BIT_SHIFT_TSFT_SEL_TIMER1_8822B) & BIT_MASK_TSFT_SEL_TIMER1_8822B)
-
+#define BIT_TSFT_SEL_TIMER1_8822B(x) \
+ (((x) & BIT_MASK_TSFT_SEL_TIMER1_8822B) \
+ << BIT_SHIFT_TSFT_SEL_TIMER1_8822B)
+#define BITS_TSFT_SEL_TIMER1_8822B \
+ (BIT_MASK_TSFT_SEL_TIMER1_8822B << BIT_SHIFT_TSFT_SEL_TIMER1_8822B)
+#define BIT_CLEAR_TSFT_SEL_TIMER1_8822B(x) ((x) & (~BITS_TSFT_SEL_TIMER1_8822B))
+#define BIT_GET_TSFT_SEL_TIMER1_8822B(x) \
+ (((x) >> BIT_SHIFT_TSFT_SEL_TIMER1_8822B) & \
+ BIT_MASK_TSFT_SEL_TIMER1_8822B)
+#define BIT_SET_TSFT_SEL_TIMER1_8822B(x, v) \
+ (BIT_CLEAR_TSFT_SEL_TIMER1_8822B(x) | BIT_TSFT_SEL_TIMER1_8822B(v))
#define BIT_SHIFT_EARLY_128US_8822B 0
#define BIT_MASK_EARLY_128US_8822B 0x7
-#define BIT_EARLY_128US_8822B(x) (((x) & BIT_MASK_EARLY_128US_8822B) << BIT_SHIFT_EARLY_128US_8822B)
-#define BIT_GET_EARLY_128US_8822B(x) (((x) >> BIT_SHIFT_EARLY_128US_8822B) & BIT_MASK_EARLY_128US_8822B)
-
+#define BIT_EARLY_128US_8822B(x) \
+ (((x) & BIT_MASK_EARLY_128US_8822B) << BIT_SHIFT_EARLY_128US_8822B)
+#define BITS_EARLY_128US_8822B \
+ (BIT_MASK_EARLY_128US_8822B << BIT_SHIFT_EARLY_128US_8822B)
+#define BIT_CLEAR_EARLY_128US_8822B(x) ((x) & (~BITS_EARLY_128US_8822B))
+#define BIT_GET_EARLY_128US_8822B(x) \
+ (((x) >> BIT_SHIFT_EARLY_128US_8822B) & BIT_MASK_EARLY_128US_8822B)
+#define BIT_SET_EARLY_128US_8822B(x, v) \
+ (BIT_CLEAR_EARLY_128US_8822B(x) | BIT_EARLY_128US_8822B(v))
/* 2 REG_P2PPS1_CTRL_8822B */
#define BIT_P2P1_CTW_ALLSTASLEEP_8822B BIT(7)
@@ -7192,71 +12636,145 @@
#define BIT_SHIFT_SYNC_CLI_SEL_8822B 4
#define BIT_MASK_SYNC_CLI_SEL_8822B 0x7
-#define BIT_SYNC_CLI_SEL_8822B(x) (((x) & BIT_MASK_SYNC_CLI_SEL_8822B) << BIT_SHIFT_SYNC_CLI_SEL_8822B)
-#define BIT_GET_SYNC_CLI_SEL_8822B(x) (((x) >> BIT_SHIFT_SYNC_CLI_SEL_8822B) & BIT_MASK_SYNC_CLI_SEL_8822B)
-
+#define BIT_SYNC_CLI_SEL_8822B(x) \
+ (((x) & BIT_MASK_SYNC_CLI_SEL_8822B) << BIT_SHIFT_SYNC_CLI_SEL_8822B)
+#define BITS_SYNC_CLI_SEL_8822B \
+ (BIT_MASK_SYNC_CLI_SEL_8822B << BIT_SHIFT_SYNC_CLI_SEL_8822B)
+#define BIT_CLEAR_SYNC_CLI_SEL_8822B(x) ((x) & (~BITS_SYNC_CLI_SEL_8822B))
+#define BIT_GET_SYNC_CLI_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_SYNC_CLI_SEL_8822B) & BIT_MASK_SYNC_CLI_SEL_8822B)
+#define BIT_SET_SYNC_CLI_SEL_8822B(x, v) \
+ (BIT_CLEAR_SYNC_CLI_SEL_8822B(x) | BIT_SYNC_CLI_SEL_8822B(v))
#define BIT_SHIFT_TSFT_SEL_TIMER0_8822B 0
#define BIT_MASK_TSFT_SEL_TIMER0_8822B 0x7
-#define BIT_TSFT_SEL_TIMER0_8822B(x) (((x) & BIT_MASK_TSFT_SEL_TIMER0_8822B) << BIT_SHIFT_TSFT_SEL_TIMER0_8822B)
-#define BIT_GET_TSFT_SEL_TIMER0_8822B(x) (((x) >> BIT_SHIFT_TSFT_SEL_TIMER0_8822B) & BIT_MASK_TSFT_SEL_TIMER0_8822B)
-
+#define BIT_TSFT_SEL_TIMER0_8822B(x) \
+ (((x) & BIT_MASK_TSFT_SEL_TIMER0_8822B) \
+ << BIT_SHIFT_TSFT_SEL_TIMER0_8822B)
+#define BITS_TSFT_SEL_TIMER0_8822B \
+ (BIT_MASK_TSFT_SEL_TIMER0_8822B << BIT_SHIFT_TSFT_SEL_TIMER0_8822B)
+#define BIT_CLEAR_TSFT_SEL_TIMER0_8822B(x) ((x) & (~BITS_TSFT_SEL_TIMER0_8822B))
+#define BIT_GET_TSFT_SEL_TIMER0_8822B(x) \
+ (((x) >> BIT_SHIFT_TSFT_SEL_TIMER0_8822B) & \
+ BIT_MASK_TSFT_SEL_TIMER0_8822B)
+#define BIT_SET_TSFT_SEL_TIMER0_8822B(x, v) \
+ (BIT_CLEAR_TSFT_SEL_TIMER0_8822B(x) | BIT_TSFT_SEL_TIMER0_8822B(v))
/* 2 REG_NOA_UNIT_SEL_8822B */
#define BIT_SHIFT_NOA_UNIT2_SEL_8822B 8
#define BIT_MASK_NOA_UNIT2_SEL_8822B 0x7
-#define BIT_NOA_UNIT2_SEL_8822B(x) (((x) & BIT_MASK_NOA_UNIT2_SEL_8822B) << BIT_SHIFT_NOA_UNIT2_SEL_8822B)
-#define BIT_GET_NOA_UNIT2_SEL_8822B(x) (((x) >> BIT_SHIFT_NOA_UNIT2_SEL_8822B) & BIT_MASK_NOA_UNIT2_SEL_8822B)
-
+#define BIT_NOA_UNIT2_SEL_8822B(x) \
+ (((x) & BIT_MASK_NOA_UNIT2_SEL_8822B) << BIT_SHIFT_NOA_UNIT2_SEL_8822B)
+#define BITS_NOA_UNIT2_SEL_8822B \
+ (BIT_MASK_NOA_UNIT2_SEL_8822B << BIT_SHIFT_NOA_UNIT2_SEL_8822B)
+#define BIT_CLEAR_NOA_UNIT2_SEL_8822B(x) ((x) & (~BITS_NOA_UNIT2_SEL_8822B))
+#define BIT_GET_NOA_UNIT2_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_NOA_UNIT2_SEL_8822B) & BIT_MASK_NOA_UNIT2_SEL_8822B)
+#define BIT_SET_NOA_UNIT2_SEL_8822B(x, v) \
+ (BIT_CLEAR_NOA_UNIT2_SEL_8822B(x) | BIT_NOA_UNIT2_SEL_8822B(v))
#define BIT_SHIFT_NOA_UNIT1_SEL_8822B 4
#define BIT_MASK_NOA_UNIT1_SEL_8822B 0x7
-#define BIT_NOA_UNIT1_SEL_8822B(x) (((x) & BIT_MASK_NOA_UNIT1_SEL_8822B) << BIT_SHIFT_NOA_UNIT1_SEL_8822B)
-#define BIT_GET_NOA_UNIT1_SEL_8822B(x) (((x) >> BIT_SHIFT_NOA_UNIT1_SEL_8822B) & BIT_MASK_NOA_UNIT1_SEL_8822B)
-
+#define BIT_NOA_UNIT1_SEL_8822B(x) \
+ (((x) & BIT_MASK_NOA_UNIT1_SEL_8822B) << BIT_SHIFT_NOA_UNIT1_SEL_8822B)
+#define BITS_NOA_UNIT1_SEL_8822B \
+ (BIT_MASK_NOA_UNIT1_SEL_8822B << BIT_SHIFT_NOA_UNIT1_SEL_8822B)
+#define BIT_CLEAR_NOA_UNIT1_SEL_8822B(x) ((x) & (~BITS_NOA_UNIT1_SEL_8822B))
+#define BIT_GET_NOA_UNIT1_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_NOA_UNIT1_SEL_8822B) & BIT_MASK_NOA_UNIT1_SEL_8822B)
+#define BIT_SET_NOA_UNIT1_SEL_8822B(x, v) \
+ (BIT_CLEAR_NOA_UNIT1_SEL_8822B(x) | BIT_NOA_UNIT1_SEL_8822B(v))
#define BIT_SHIFT_NOA_UNIT0_SEL_8822B 0
#define BIT_MASK_NOA_UNIT0_SEL_8822B 0x7
-#define BIT_NOA_UNIT0_SEL_8822B(x) (((x) & BIT_MASK_NOA_UNIT0_SEL_8822B) << BIT_SHIFT_NOA_UNIT0_SEL_8822B)
-#define BIT_GET_NOA_UNIT0_SEL_8822B(x) (((x) >> BIT_SHIFT_NOA_UNIT0_SEL_8822B) & BIT_MASK_NOA_UNIT0_SEL_8822B)
-
+#define BIT_NOA_UNIT0_SEL_8822B(x) \
+ (((x) & BIT_MASK_NOA_UNIT0_SEL_8822B) << BIT_SHIFT_NOA_UNIT0_SEL_8822B)
+#define BITS_NOA_UNIT0_SEL_8822B \
+ (BIT_MASK_NOA_UNIT0_SEL_8822B << BIT_SHIFT_NOA_UNIT0_SEL_8822B)
+#define BIT_CLEAR_NOA_UNIT0_SEL_8822B(x) ((x) & (~BITS_NOA_UNIT0_SEL_8822B))
+#define BIT_GET_NOA_UNIT0_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_NOA_UNIT0_SEL_8822B) & BIT_MASK_NOA_UNIT0_SEL_8822B)
+#define BIT_SET_NOA_UNIT0_SEL_8822B(x, v) \
+ (BIT_CLEAR_NOA_UNIT0_SEL_8822B(x) | BIT_NOA_UNIT0_SEL_8822B(v))
/* 2 REG_P2POFF_DIS_TXTIME_8822B */
#define BIT_SHIFT_P2POFF_DIS_TXTIME_8822B 0
#define BIT_MASK_P2POFF_DIS_TXTIME_8822B 0xff
-#define BIT_P2POFF_DIS_TXTIME_8822B(x) (((x) & BIT_MASK_P2POFF_DIS_TXTIME_8822B) << BIT_SHIFT_P2POFF_DIS_TXTIME_8822B)
-#define BIT_GET_P2POFF_DIS_TXTIME_8822B(x) (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8822B) & BIT_MASK_P2POFF_DIS_TXTIME_8822B)
-
+#define BIT_P2POFF_DIS_TXTIME_8822B(x) \
+ (((x) & BIT_MASK_P2POFF_DIS_TXTIME_8822B) \
+ << BIT_SHIFT_P2POFF_DIS_TXTIME_8822B)
+#define BITS_P2POFF_DIS_TXTIME_8822B \
+ (BIT_MASK_P2POFF_DIS_TXTIME_8822B << BIT_SHIFT_P2POFF_DIS_TXTIME_8822B)
+#define BIT_CLEAR_P2POFF_DIS_TXTIME_8822B(x) \
+ ((x) & (~BITS_P2POFF_DIS_TXTIME_8822B))
+#define BIT_GET_P2POFF_DIS_TXTIME_8822B(x) \
+ (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8822B) & \
+ BIT_MASK_P2POFF_DIS_TXTIME_8822B)
+#define BIT_SET_P2POFF_DIS_TXTIME_8822B(x, v) \
+ (BIT_CLEAR_P2POFF_DIS_TXTIME_8822B(x) | BIT_P2POFF_DIS_TXTIME_8822B(v))
/* 2 REG_MBSSID_BCN_SPACE2_8822B */
#define BIT_SHIFT_BCN_SPACE_CLINT2_8822B 16
#define BIT_MASK_BCN_SPACE_CLINT2_8822B 0xfff
-#define BIT_BCN_SPACE_CLINT2_8822B(x) (((x) & BIT_MASK_BCN_SPACE_CLINT2_8822B) << BIT_SHIFT_BCN_SPACE_CLINT2_8822B)
-#define BIT_GET_BCN_SPACE_CLINT2_8822B(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT2_8822B) & BIT_MASK_BCN_SPACE_CLINT2_8822B)
-
+#define BIT_BCN_SPACE_CLINT2_8822B(x) \
+ (((x) & BIT_MASK_BCN_SPACE_CLINT2_8822B) \
+ << BIT_SHIFT_BCN_SPACE_CLINT2_8822B)
+#define BITS_BCN_SPACE_CLINT2_8822B \
+ (BIT_MASK_BCN_SPACE_CLINT2_8822B << BIT_SHIFT_BCN_SPACE_CLINT2_8822B)
+#define BIT_CLEAR_BCN_SPACE_CLINT2_8822B(x) \
+ ((x) & (~BITS_BCN_SPACE_CLINT2_8822B))
+#define BIT_GET_BCN_SPACE_CLINT2_8822B(x) \
+ (((x) >> BIT_SHIFT_BCN_SPACE_CLINT2_8822B) & \
+ BIT_MASK_BCN_SPACE_CLINT2_8822B)
+#define BIT_SET_BCN_SPACE_CLINT2_8822B(x, v) \
+ (BIT_CLEAR_BCN_SPACE_CLINT2_8822B(x) | BIT_BCN_SPACE_CLINT2_8822B(v))
#define BIT_SHIFT_BCN_SPACE_CLINT1_8822B 0
#define BIT_MASK_BCN_SPACE_CLINT1_8822B 0xfff
-#define BIT_BCN_SPACE_CLINT1_8822B(x) (((x) & BIT_MASK_BCN_SPACE_CLINT1_8822B) << BIT_SHIFT_BCN_SPACE_CLINT1_8822B)
-#define BIT_GET_BCN_SPACE_CLINT1_8822B(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT1_8822B) & BIT_MASK_BCN_SPACE_CLINT1_8822B)
-
+#define BIT_BCN_SPACE_CLINT1_8822B(x) \
+ (((x) & BIT_MASK_BCN_SPACE_CLINT1_8822B) \
+ << BIT_SHIFT_BCN_SPACE_CLINT1_8822B)
+#define BITS_BCN_SPACE_CLINT1_8822B \
+ (BIT_MASK_BCN_SPACE_CLINT1_8822B << BIT_SHIFT_BCN_SPACE_CLINT1_8822B)
+#define BIT_CLEAR_BCN_SPACE_CLINT1_8822B(x) \
+ ((x) & (~BITS_BCN_SPACE_CLINT1_8822B))
+#define BIT_GET_BCN_SPACE_CLINT1_8822B(x) \
+ (((x) >> BIT_SHIFT_BCN_SPACE_CLINT1_8822B) & \
+ BIT_MASK_BCN_SPACE_CLINT1_8822B)
+#define BIT_SET_BCN_SPACE_CLINT1_8822B(x, v) \
+ (BIT_CLEAR_BCN_SPACE_CLINT1_8822B(x) | BIT_BCN_SPACE_CLINT1_8822B(v))
/* 2 REG_MBSSID_BCN_SPACE3_8822B */
#define BIT_SHIFT_SUB_BCN_SPACE_8822B 16
#define BIT_MASK_SUB_BCN_SPACE_8822B 0xff
-#define BIT_SUB_BCN_SPACE_8822B(x) (((x) & BIT_MASK_SUB_BCN_SPACE_8822B) << BIT_SHIFT_SUB_BCN_SPACE_8822B)
-#define BIT_GET_SUB_BCN_SPACE_8822B(x) (((x) >> BIT_SHIFT_SUB_BCN_SPACE_8822B) & BIT_MASK_SUB_BCN_SPACE_8822B)
-
+#define BIT_SUB_BCN_SPACE_8822B(x) \
+ (((x) & BIT_MASK_SUB_BCN_SPACE_8822B) << BIT_SHIFT_SUB_BCN_SPACE_8822B)
+#define BITS_SUB_BCN_SPACE_8822B \
+ (BIT_MASK_SUB_BCN_SPACE_8822B << BIT_SHIFT_SUB_BCN_SPACE_8822B)
+#define BIT_CLEAR_SUB_BCN_SPACE_8822B(x) ((x) & (~BITS_SUB_BCN_SPACE_8822B))
+#define BIT_GET_SUB_BCN_SPACE_8822B(x) \
+ (((x) >> BIT_SHIFT_SUB_BCN_SPACE_8822B) & BIT_MASK_SUB_BCN_SPACE_8822B)
+#define BIT_SET_SUB_BCN_SPACE_8822B(x, v) \
+ (BIT_CLEAR_SUB_BCN_SPACE_8822B(x) | BIT_SUB_BCN_SPACE_8822B(v))
#define BIT_SHIFT_BCN_SPACE_CLINT3_8822B 0
#define BIT_MASK_BCN_SPACE_CLINT3_8822B 0xfff
-#define BIT_BCN_SPACE_CLINT3_8822B(x) (((x) & BIT_MASK_BCN_SPACE_CLINT3_8822B) << BIT_SHIFT_BCN_SPACE_CLINT3_8822B)
-#define BIT_GET_BCN_SPACE_CLINT3_8822B(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT3_8822B) & BIT_MASK_BCN_SPACE_CLINT3_8822B)
-
+#define BIT_BCN_SPACE_CLINT3_8822B(x) \
+ (((x) & BIT_MASK_BCN_SPACE_CLINT3_8822B) \
+ << BIT_SHIFT_BCN_SPACE_CLINT3_8822B)
+#define BITS_BCN_SPACE_CLINT3_8822B \
+ (BIT_MASK_BCN_SPACE_CLINT3_8822B << BIT_SHIFT_BCN_SPACE_CLINT3_8822B)
+#define BIT_CLEAR_BCN_SPACE_CLINT3_8822B(x) \
+ ((x) & (~BITS_BCN_SPACE_CLINT3_8822B))
+#define BIT_GET_BCN_SPACE_CLINT3_8822B(x) \
+ (((x) >> BIT_SHIFT_BCN_SPACE_CLINT3_8822B) & \
+ BIT_MASK_BCN_SPACE_CLINT3_8822B)
+#define BIT_SET_BCN_SPACE_CLINT3_8822B(x, v) \
+ (BIT_CLEAR_BCN_SPACE_CLINT3_8822B(x) | BIT_BCN_SPACE_CLINT3_8822B(v))
/* 2 REG_ACMHWCTRL_8822B */
#define BIT_BEQ_ACM_STATUS_8822B BIT(7)
@@ -7276,81 +12794,158 @@
#define BIT_SHIFT_AVGPERIOD_8822B 0
#define BIT_MASK_AVGPERIOD_8822B 0xffff
-#define BIT_AVGPERIOD_8822B(x) (((x) & BIT_MASK_AVGPERIOD_8822B) << BIT_SHIFT_AVGPERIOD_8822B)
-#define BIT_GET_AVGPERIOD_8822B(x) (((x) >> BIT_SHIFT_AVGPERIOD_8822B) & BIT_MASK_AVGPERIOD_8822B)
-
+#define BIT_AVGPERIOD_8822B(x) \
+ (((x) & BIT_MASK_AVGPERIOD_8822B) << BIT_SHIFT_AVGPERIOD_8822B)
+#define BITS_AVGPERIOD_8822B \
+ (BIT_MASK_AVGPERIOD_8822B << BIT_SHIFT_AVGPERIOD_8822B)
+#define BIT_CLEAR_AVGPERIOD_8822B(x) ((x) & (~BITS_AVGPERIOD_8822B))
+#define BIT_GET_AVGPERIOD_8822B(x) \
+ (((x) >> BIT_SHIFT_AVGPERIOD_8822B) & BIT_MASK_AVGPERIOD_8822B)
+#define BIT_SET_AVGPERIOD_8822B(x, v) \
+ (BIT_CLEAR_AVGPERIOD_8822B(x) | BIT_AVGPERIOD_8822B(v))
/* 2 REG_VO_ADMTIME_8822B */
#define BIT_SHIFT_VO_ADMITTED_TIME_8822B 0
#define BIT_MASK_VO_ADMITTED_TIME_8822B 0xffff
-#define BIT_VO_ADMITTED_TIME_8822B(x) (((x) & BIT_MASK_VO_ADMITTED_TIME_8822B) << BIT_SHIFT_VO_ADMITTED_TIME_8822B)
-#define BIT_GET_VO_ADMITTED_TIME_8822B(x) (((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8822B) & BIT_MASK_VO_ADMITTED_TIME_8822B)
-
+#define BIT_VO_ADMITTED_TIME_8822B(x) \
+ (((x) & BIT_MASK_VO_ADMITTED_TIME_8822B) \
+ << BIT_SHIFT_VO_ADMITTED_TIME_8822B)
+#define BITS_VO_ADMITTED_TIME_8822B \
+ (BIT_MASK_VO_ADMITTED_TIME_8822B << BIT_SHIFT_VO_ADMITTED_TIME_8822B)
+#define BIT_CLEAR_VO_ADMITTED_TIME_8822B(x) \
+ ((x) & (~BITS_VO_ADMITTED_TIME_8822B))
+#define BIT_GET_VO_ADMITTED_TIME_8822B(x) \
+ (((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8822B) & \
+ BIT_MASK_VO_ADMITTED_TIME_8822B)
+#define BIT_SET_VO_ADMITTED_TIME_8822B(x, v) \
+ (BIT_CLEAR_VO_ADMITTED_TIME_8822B(x) | BIT_VO_ADMITTED_TIME_8822B(v))
/* 2 REG_VI_ADMTIME_8822B */
#define BIT_SHIFT_VI_ADMITTED_TIME_8822B 0
#define BIT_MASK_VI_ADMITTED_TIME_8822B 0xffff
-#define BIT_VI_ADMITTED_TIME_8822B(x) (((x) & BIT_MASK_VI_ADMITTED_TIME_8822B) << BIT_SHIFT_VI_ADMITTED_TIME_8822B)
-#define BIT_GET_VI_ADMITTED_TIME_8822B(x) (((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8822B) & BIT_MASK_VI_ADMITTED_TIME_8822B)
-
+#define BIT_VI_ADMITTED_TIME_8822B(x) \
+ (((x) & BIT_MASK_VI_ADMITTED_TIME_8822B) \
+ << BIT_SHIFT_VI_ADMITTED_TIME_8822B)
+#define BITS_VI_ADMITTED_TIME_8822B \
+ (BIT_MASK_VI_ADMITTED_TIME_8822B << BIT_SHIFT_VI_ADMITTED_TIME_8822B)
+#define BIT_CLEAR_VI_ADMITTED_TIME_8822B(x) \
+ ((x) & (~BITS_VI_ADMITTED_TIME_8822B))
+#define BIT_GET_VI_ADMITTED_TIME_8822B(x) \
+ (((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8822B) & \
+ BIT_MASK_VI_ADMITTED_TIME_8822B)
+#define BIT_SET_VI_ADMITTED_TIME_8822B(x, v) \
+ (BIT_CLEAR_VI_ADMITTED_TIME_8822B(x) | BIT_VI_ADMITTED_TIME_8822B(v))
/* 2 REG_BE_ADMTIME_8822B */
#define BIT_SHIFT_BE_ADMITTED_TIME_8822B 0
#define BIT_MASK_BE_ADMITTED_TIME_8822B 0xffff
-#define BIT_BE_ADMITTED_TIME_8822B(x) (((x) & BIT_MASK_BE_ADMITTED_TIME_8822B) << BIT_SHIFT_BE_ADMITTED_TIME_8822B)
-#define BIT_GET_BE_ADMITTED_TIME_8822B(x) (((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8822B) & BIT_MASK_BE_ADMITTED_TIME_8822B)
-
+#define BIT_BE_ADMITTED_TIME_8822B(x) \
+ (((x) & BIT_MASK_BE_ADMITTED_TIME_8822B) \
+ << BIT_SHIFT_BE_ADMITTED_TIME_8822B)
+#define BITS_BE_ADMITTED_TIME_8822B \
+ (BIT_MASK_BE_ADMITTED_TIME_8822B << BIT_SHIFT_BE_ADMITTED_TIME_8822B)
+#define BIT_CLEAR_BE_ADMITTED_TIME_8822B(x) \
+ ((x) & (~BITS_BE_ADMITTED_TIME_8822B))
+#define BIT_GET_BE_ADMITTED_TIME_8822B(x) \
+ (((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8822B) & \
+ BIT_MASK_BE_ADMITTED_TIME_8822B)
+#define BIT_SET_BE_ADMITTED_TIME_8822B(x, v) \
+ (BIT_CLEAR_BE_ADMITTED_TIME_8822B(x) | BIT_BE_ADMITTED_TIME_8822B(v))
/* 2 REG_EDCA_RANDOM_GEN_8822B */
#define BIT_SHIFT_RANDOM_GEN_8822B 0
#define BIT_MASK_RANDOM_GEN_8822B 0xffffff
-#define BIT_RANDOM_GEN_8822B(x) (((x) & BIT_MASK_RANDOM_GEN_8822B) << BIT_SHIFT_RANDOM_GEN_8822B)
-#define BIT_GET_RANDOM_GEN_8822B(x) (((x) >> BIT_SHIFT_RANDOM_GEN_8822B) & BIT_MASK_RANDOM_GEN_8822B)
-
+#define BIT_RANDOM_GEN_8822B(x) \
+ (((x) & BIT_MASK_RANDOM_GEN_8822B) << BIT_SHIFT_RANDOM_GEN_8822B)
+#define BITS_RANDOM_GEN_8822B \
+ (BIT_MASK_RANDOM_GEN_8822B << BIT_SHIFT_RANDOM_GEN_8822B)
+#define BIT_CLEAR_RANDOM_GEN_8822B(x) ((x) & (~BITS_RANDOM_GEN_8822B))
+#define BIT_GET_RANDOM_GEN_8822B(x) \
+ (((x) >> BIT_SHIFT_RANDOM_GEN_8822B) & BIT_MASK_RANDOM_GEN_8822B)
+#define BIT_SET_RANDOM_GEN_8822B(x, v) \
+ (BIT_CLEAR_RANDOM_GEN_8822B(x) | BIT_RANDOM_GEN_8822B(v))
/* 2 REG_TXCMD_NOA_SEL_8822B */
-#define BIT_SHIFT_NOA_SEL_8822B 4
-#define BIT_MASK_NOA_SEL_8822B 0x7
-#define BIT_NOA_SEL_8822B(x) (((x) & BIT_MASK_NOA_SEL_8822B) << BIT_SHIFT_NOA_SEL_8822B)
-#define BIT_GET_NOA_SEL_8822B(x) (((x) >> BIT_SHIFT_NOA_SEL_8822B) & BIT_MASK_NOA_SEL_8822B)
-
+#define BIT_SHIFT_NOA_SEL_V2_8822B 4
+#define BIT_MASK_NOA_SEL_V2_8822B 0x7
+#define BIT_NOA_SEL_V2_8822B(x) \
+ (((x) & BIT_MASK_NOA_SEL_V2_8822B) << BIT_SHIFT_NOA_SEL_V2_8822B)
+#define BITS_NOA_SEL_V2_8822B \
+ (BIT_MASK_NOA_SEL_V2_8822B << BIT_SHIFT_NOA_SEL_V2_8822B)
+#define BIT_CLEAR_NOA_SEL_V2_8822B(x) ((x) & (~BITS_NOA_SEL_V2_8822B))
+#define BIT_GET_NOA_SEL_V2_8822B(x) \
+ (((x) >> BIT_SHIFT_NOA_SEL_V2_8822B) & BIT_MASK_NOA_SEL_V2_8822B)
+#define BIT_SET_NOA_SEL_V2_8822B(x, v) \
+ (BIT_CLEAR_NOA_SEL_V2_8822B(x) | BIT_NOA_SEL_V2_8822B(v))
#define BIT_SHIFT_TXCMD_SEG_SEL_8822B 0
#define BIT_MASK_TXCMD_SEG_SEL_8822B 0xf
-#define BIT_TXCMD_SEG_SEL_8822B(x) (((x) & BIT_MASK_TXCMD_SEG_SEL_8822B) << BIT_SHIFT_TXCMD_SEG_SEL_8822B)
-#define BIT_GET_TXCMD_SEG_SEL_8822B(x) (((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8822B) & BIT_MASK_TXCMD_SEG_SEL_8822B)
-
+#define BIT_TXCMD_SEG_SEL_8822B(x) \
+ (((x) & BIT_MASK_TXCMD_SEG_SEL_8822B) << BIT_SHIFT_TXCMD_SEG_SEL_8822B)
+#define BITS_TXCMD_SEG_SEL_8822B \
+ (BIT_MASK_TXCMD_SEG_SEL_8822B << BIT_SHIFT_TXCMD_SEG_SEL_8822B)
+#define BIT_CLEAR_TXCMD_SEG_SEL_8822B(x) ((x) & (~BITS_TXCMD_SEG_SEL_8822B))
+#define BIT_GET_TXCMD_SEG_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8822B) & BIT_MASK_TXCMD_SEG_SEL_8822B)
+#define BIT_SET_TXCMD_SEG_SEL_8822B(x, v) \
+ (BIT_CLEAR_TXCMD_SEG_SEL_8822B(x) | BIT_TXCMD_SEG_SEL_8822B(v))
/* 2 REG_NOA_PARAM_8822B */
#define BIT_SHIFT_NOA_COUNT_8822B (96 & CPU_OPT_WIDTH)
#define BIT_MASK_NOA_COUNT_8822B 0xff
-#define BIT_NOA_COUNT_8822B(x) (((x) & BIT_MASK_NOA_COUNT_8822B) << BIT_SHIFT_NOA_COUNT_8822B)
-#define BIT_GET_NOA_COUNT_8822B(x) (((x) >> BIT_SHIFT_NOA_COUNT_8822B) & BIT_MASK_NOA_COUNT_8822B)
-
+#define BIT_NOA_COUNT_8822B(x) \
+ (((x) & BIT_MASK_NOA_COUNT_8822B) << BIT_SHIFT_NOA_COUNT_8822B)
+#define BITS_NOA_COUNT_8822B \
+ (BIT_MASK_NOA_COUNT_8822B << BIT_SHIFT_NOA_COUNT_8822B)
+#define BIT_CLEAR_NOA_COUNT_8822B(x) ((x) & (~BITS_NOA_COUNT_8822B))
+#define BIT_GET_NOA_COUNT_8822B(x) \
+ (((x) >> BIT_SHIFT_NOA_COUNT_8822B) & BIT_MASK_NOA_COUNT_8822B)
+#define BIT_SET_NOA_COUNT_8822B(x, v) \
+ (BIT_CLEAR_NOA_COUNT_8822B(x) | BIT_NOA_COUNT_8822B(v))
#define BIT_SHIFT_NOA_START_TIME_8822B (64 & CPU_OPT_WIDTH)
#define BIT_MASK_NOA_START_TIME_8822B 0xffffffffL
-#define BIT_NOA_START_TIME_8822B(x) (((x) & BIT_MASK_NOA_START_TIME_8822B) << BIT_SHIFT_NOA_START_TIME_8822B)
-#define BIT_GET_NOA_START_TIME_8822B(x) (((x) >> BIT_SHIFT_NOA_START_TIME_8822B) & BIT_MASK_NOA_START_TIME_8822B)
-
+#define BIT_NOA_START_TIME_8822B(x) \
+ (((x) & BIT_MASK_NOA_START_TIME_8822B) \
+ << BIT_SHIFT_NOA_START_TIME_8822B)
+#define BITS_NOA_START_TIME_8822B \
+ (BIT_MASK_NOA_START_TIME_8822B << BIT_SHIFT_NOA_START_TIME_8822B)
+#define BIT_CLEAR_NOA_START_TIME_8822B(x) ((x) & (~BITS_NOA_START_TIME_8822B))
+#define BIT_GET_NOA_START_TIME_8822B(x) \
+ (((x) >> BIT_SHIFT_NOA_START_TIME_8822B) & \
+ BIT_MASK_NOA_START_TIME_8822B)
+#define BIT_SET_NOA_START_TIME_8822B(x, v) \
+ (BIT_CLEAR_NOA_START_TIME_8822B(x) | BIT_NOA_START_TIME_8822B(v))
#define BIT_SHIFT_NOA_INTERVAL_8822B (32 & CPU_OPT_WIDTH)
#define BIT_MASK_NOA_INTERVAL_8822B 0xffffffffL
-#define BIT_NOA_INTERVAL_8822B(x) (((x) & BIT_MASK_NOA_INTERVAL_8822B) << BIT_SHIFT_NOA_INTERVAL_8822B)
-#define BIT_GET_NOA_INTERVAL_8822B(x) (((x) >> BIT_SHIFT_NOA_INTERVAL_8822B) & BIT_MASK_NOA_INTERVAL_8822B)
-
+#define BIT_NOA_INTERVAL_8822B(x) \
+ (((x) & BIT_MASK_NOA_INTERVAL_8822B) << BIT_SHIFT_NOA_INTERVAL_8822B)
+#define BITS_NOA_INTERVAL_8822B \
+ (BIT_MASK_NOA_INTERVAL_8822B << BIT_SHIFT_NOA_INTERVAL_8822B)
+#define BIT_CLEAR_NOA_INTERVAL_8822B(x) ((x) & (~BITS_NOA_INTERVAL_8822B))
+#define BIT_GET_NOA_INTERVAL_8822B(x) \
+ (((x) >> BIT_SHIFT_NOA_INTERVAL_8822B) & BIT_MASK_NOA_INTERVAL_8822B)
+#define BIT_SET_NOA_INTERVAL_8822B(x, v) \
+ (BIT_CLEAR_NOA_INTERVAL_8822B(x) | BIT_NOA_INTERVAL_8822B(v))
#define BIT_SHIFT_NOA_DURATION_8822B 0
#define BIT_MASK_NOA_DURATION_8822B 0xffffffffL
-#define BIT_NOA_DURATION_8822B(x) (((x) & BIT_MASK_NOA_DURATION_8822B) << BIT_SHIFT_NOA_DURATION_8822B)
-#define BIT_GET_NOA_DURATION_8822B(x) (((x) >> BIT_SHIFT_NOA_DURATION_8822B) & BIT_MASK_NOA_DURATION_8822B)
-
+#define BIT_NOA_DURATION_8822B(x) \
+ (((x) & BIT_MASK_NOA_DURATION_8822B) << BIT_SHIFT_NOA_DURATION_8822B)
+#define BITS_NOA_DURATION_8822B \
+ (BIT_MASK_NOA_DURATION_8822B << BIT_SHIFT_NOA_DURATION_8822B)
+#define BIT_CLEAR_NOA_DURATION_8822B(x) ((x) & (~BITS_NOA_DURATION_8822B))
+#define BIT_GET_NOA_DURATION_8822B(x) \
+ (((x) >> BIT_SHIFT_NOA_DURATION_8822B) & BIT_MASK_NOA_DURATION_8822B)
+#define BIT_SET_NOA_DURATION_8822B(x, v) \
+ (BIT_CLEAR_NOA_DURATION_8822B(x) | BIT_NOA_DURATION_8822B(v))
/* 2 REG_P2P_RST_8822B */
#define BIT_P2P2_PWR_RST1_8822B BIT(5)
@@ -7361,16 +12956,23 @@
#define BIT_P2P_PWR_RST0_V1_8822B BIT(0)
/* 2 REG_SCHEDULER_RST_8822B */
-#define BIT_SYNC_CLI_8822B BIT(1)
+#define BIT_SYNC_CLI_ONCE_RIGHT_NOW_8822B BIT(2)
+#define BIT_SYNC_CLI_ONCE_BY_TBTT_8822B BIT(1)
#define BIT_SCHEDULER_RST_V1_8822B BIT(0)
/* 2 REG_SCH_TXCMD_8822B */
#define BIT_SHIFT_SCH_TXCMD_8822B 0
#define BIT_MASK_SCH_TXCMD_8822B 0xffffffffL
-#define BIT_SCH_TXCMD_8822B(x) (((x) & BIT_MASK_SCH_TXCMD_8822B) << BIT_SHIFT_SCH_TXCMD_8822B)
-#define BIT_GET_SCH_TXCMD_8822B(x) (((x) >> BIT_SHIFT_SCH_TXCMD_8822B) & BIT_MASK_SCH_TXCMD_8822B)
-
+#define BIT_SCH_TXCMD_8822B(x) \
+ (((x) & BIT_MASK_SCH_TXCMD_8822B) << BIT_SHIFT_SCH_TXCMD_8822B)
+#define BITS_SCH_TXCMD_8822B \
+ (BIT_MASK_SCH_TXCMD_8822B << BIT_SHIFT_SCH_TXCMD_8822B)
+#define BIT_CLEAR_SCH_TXCMD_8822B(x) ((x) & (~BITS_SCH_TXCMD_8822B))
+#define BIT_GET_SCH_TXCMD_8822B(x) \
+ (((x) >> BIT_SHIFT_SCH_TXCMD_8822B) & BIT_MASK_SCH_TXCMD_8822B)
+#define BIT_SET_SCH_TXCMD_8822B(x, v) \
+ (BIT_CLEAR_SCH_TXCMD_8822B(x) | BIT_SCH_TXCMD_8822B(v))
/* 2 REG_PAGE5_DUMMY_8822B */
@@ -7378,33 +12980,62 @@
#define BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822B 0
#define BIT_MASK_CPUMGQ_TX_TIMER_V1_8822B 0xffffffffL
-#define BIT_CPUMGQ_TX_TIMER_V1_8822B(x) (((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8822B) << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822B)
-#define BIT_GET_CPUMGQ_TX_TIMER_V1_8822B(x) (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822B) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8822B)
-
+#define BIT_CPUMGQ_TX_TIMER_V1_8822B(x) \
+ (((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8822B) \
+ << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822B)
+#define BITS_CPUMGQ_TX_TIMER_V1_8822B \
+ (BIT_MASK_CPUMGQ_TX_TIMER_V1_8822B \
+ << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822B)
+#define BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8822B(x) \
+ ((x) & (~BITS_CPUMGQ_TX_TIMER_V1_8822B))
+#define BIT_GET_CPUMGQ_TX_TIMER_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822B) & \
+ BIT_MASK_CPUMGQ_TX_TIMER_V1_8822B)
+#define BIT_SET_CPUMGQ_TX_TIMER_V1_8822B(x, v) \
+ (BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8822B(x) | \
+ BIT_CPUMGQ_TX_TIMER_V1_8822B(v))
/* 2 REG_PS_TIMER_A_8822B */
#define BIT_SHIFT_PS_TIMER_A_V1_8822B 0
#define BIT_MASK_PS_TIMER_A_V1_8822B 0xffffffffL
-#define BIT_PS_TIMER_A_V1_8822B(x) (((x) & BIT_MASK_PS_TIMER_A_V1_8822B) << BIT_SHIFT_PS_TIMER_A_V1_8822B)
-#define BIT_GET_PS_TIMER_A_V1_8822B(x) (((x) >> BIT_SHIFT_PS_TIMER_A_V1_8822B) & BIT_MASK_PS_TIMER_A_V1_8822B)
-
+#define BIT_PS_TIMER_A_V1_8822B(x) \
+ (((x) & BIT_MASK_PS_TIMER_A_V1_8822B) << BIT_SHIFT_PS_TIMER_A_V1_8822B)
+#define BITS_PS_TIMER_A_V1_8822B \
+ (BIT_MASK_PS_TIMER_A_V1_8822B << BIT_SHIFT_PS_TIMER_A_V1_8822B)
+#define BIT_CLEAR_PS_TIMER_A_V1_8822B(x) ((x) & (~BITS_PS_TIMER_A_V1_8822B))
+#define BIT_GET_PS_TIMER_A_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_A_V1_8822B) & BIT_MASK_PS_TIMER_A_V1_8822B)
+#define BIT_SET_PS_TIMER_A_V1_8822B(x, v) \
+ (BIT_CLEAR_PS_TIMER_A_V1_8822B(x) | BIT_PS_TIMER_A_V1_8822B(v))
/* 2 REG_PS_TIMER_B_8822B */
#define BIT_SHIFT_PS_TIMER_B_V1_8822B 0
#define BIT_MASK_PS_TIMER_B_V1_8822B 0xffffffffL
-#define BIT_PS_TIMER_B_V1_8822B(x) (((x) & BIT_MASK_PS_TIMER_B_V1_8822B) << BIT_SHIFT_PS_TIMER_B_V1_8822B)
-#define BIT_GET_PS_TIMER_B_V1_8822B(x) (((x) >> BIT_SHIFT_PS_TIMER_B_V1_8822B) & BIT_MASK_PS_TIMER_B_V1_8822B)
-
+#define BIT_PS_TIMER_B_V1_8822B(x) \
+ (((x) & BIT_MASK_PS_TIMER_B_V1_8822B) << BIT_SHIFT_PS_TIMER_B_V1_8822B)
+#define BITS_PS_TIMER_B_V1_8822B \
+ (BIT_MASK_PS_TIMER_B_V1_8822B << BIT_SHIFT_PS_TIMER_B_V1_8822B)
+#define BIT_CLEAR_PS_TIMER_B_V1_8822B(x) ((x) & (~BITS_PS_TIMER_B_V1_8822B))
+#define BIT_GET_PS_TIMER_B_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_B_V1_8822B) & BIT_MASK_PS_TIMER_B_V1_8822B)
+#define BIT_SET_PS_TIMER_B_V1_8822B(x, v) \
+ (BIT_CLEAR_PS_TIMER_B_V1_8822B(x) | BIT_PS_TIMER_B_V1_8822B(v))
/* 2 REG_PS_TIMER_C_8822B */
#define BIT_SHIFT_PS_TIMER_C_V1_8822B 0
#define BIT_MASK_PS_TIMER_C_V1_8822B 0xffffffffL
-#define BIT_PS_TIMER_C_V1_8822B(x) (((x) & BIT_MASK_PS_TIMER_C_V1_8822B) << BIT_SHIFT_PS_TIMER_C_V1_8822B)
-#define BIT_GET_PS_TIMER_C_V1_8822B(x) (((x) >> BIT_SHIFT_PS_TIMER_C_V1_8822B) & BIT_MASK_PS_TIMER_C_V1_8822B)
-
+#define BIT_PS_TIMER_C_V1_8822B(x) \
+ (((x) & BIT_MASK_PS_TIMER_C_V1_8822B) << BIT_SHIFT_PS_TIMER_C_V1_8822B)
+#define BITS_PS_TIMER_C_V1_8822B \
+ (BIT_MASK_PS_TIMER_C_V1_8822B << BIT_SHIFT_PS_TIMER_C_V1_8822B)
+#define BIT_CLEAR_PS_TIMER_C_V1_8822B(x) ((x) & (~BITS_PS_TIMER_C_V1_8822B))
+#define BIT_GET_PS_TIMER_C_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_C_V1_8822B) & BIT_MASK_PS_TIMER_C_V1_8822B)
+#define BIT_SET_PS_TIMER_C_V1_8822B(x, v) \
+ (BIT_CLEAR_PS_TIMER_C_V1_8822B(x) | BIT_PS_TIMER_C_V1_8822B(v))
/* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8822B */
#define BIT_CPUMGQ_TIMER_EN_8822B BIT(31)
@@ -7412,62 +13043,169 @@
#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822B 24
#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822B 0x7
-#define BIT_CPUMGQ_TIMER_TSF_SEL_8822B(x) (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822B) << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822B)
-#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_8822B(x) (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822B) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822B)
+#define BIT_CPUMGQ_TIMER_TSF_SEL_8822B(x) \
+ (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822B) \
+ << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822B)
+#define BITS_CPUMGQ_TIMER_TSF_SEL_8822B \
+ (BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822B \
+ << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822B)
+#define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8822B(x) \
+ ((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL_8822B))
+#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822B) & \
+ BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822B)
+#define BIT_SET_CPUMGQ_TIMER_TSF_SEL_8822B(x, v) \
+ (BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8822B(x) | \
+ BIT_CPUMGQ_TIMER_TSF_SEL_8822B(v))
#define BIT_PS_TIMER_C_EN_8822B BIT(23)
#define BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822B 16
#define BIT_MASK_PS_TIMER_C_TSF_SEL_8822B 0x7
-#define BIT_PS_TIMER_C_TSF_SEL_8822B(x) (((x) & BIT_MASK_PS_TIMER_C_TSF_SEL_8822B) << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822B)
-#define BIT_GET_PS_TIMER_C_TSF_SEL_8822B(x) (((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822B) & BIT_MASK_PS_TIMER_C_TSF_SEL_8822B)
+#define BIT_PS_TIMER_C_TSF_SEL_8822B(x) \
+ (((x) & BIT_MASK_PS_TIMER_C_TSF_SEL_8822B) \
+ << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822B)
+#define BITS_PS_TIMER_C_TSF_SEL_8822B \
+ (BIT_MASK_PS_TIMER_C_TSF_SEL_8822B \
+ << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822B)
+#define BIT_CLEAR_PS_TIMER_C_TSF_SEL_8822B(x) \
+ ((x) & (~BITS_PS_TIMER_C_TSF_SEL_8822B))
+#define BIT_GET_PS_TIMER_C_TSF_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822B) & \
+ BIT_MASK_PS_TIMER_C_TSF_SEL_8822B)
+#define BIT_SET_PS_TIMER_C_TSF_SEL_8822B(x, v) \
+ (BIT_CLEAR_PS_TIMER_C_TSF_SEL_8822B(x) | \
+ BIT_PS_TIMER_C_TSF_SEL_8822B(v))
#define BIT_PS_TIMER_B_EN_8822B BIT(15)
#define BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822B 8
#define BIT_MASK_PS_TIMER_B_TSF_SEL_8822B 0x7
-#define BIT_PS_TIMER_B_TSF_SEL_8822B(x) (((x) & BIT_MASK_PS_TIMER_B_TSF_SEL_8822B) << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822B)
-#define BIT_GET_PS_TIMER_B_TSF_SEL_8822B(x) (((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822B) & BIT_MASK_PS_TIMER_B_TSF_SEL_8822B)
+#define BIT_PS_TIMER_B_TSF_SEL_8822B(x) \
+ (((x) & BIT_MASK_PS_TIMER_B_TSF_SEL_8822B) \
+ << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822B)
+#define BITS_PS_TIMER_B_TSF_SEL_8822B \
+ (BIT_MASK_PS_TIMER_B_TSF_SEL_8822B \
+ << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822B)
+#define BIT_CLEAR_PS_TIMER_B_TSF_SEL_8822B(x) \
+ ((x) & (~BITS_PS_TIMER_B_TSF_SEL_8822B))
+#define BIT_GET_PS_TIMER_B_TSF_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822B) & \
+ BIT_MASK_PS_TIMER_B_TSF_SEL_8822B)
+#define BIT_SET_PS_TIMER_B_TSF_SEL_8822B(x, v) \
+ (BIT_CLEAR_PS_TIMER_B_TSF_SEL_8822B(x) | \
+ BIT_PS_TIMER_B_TSF_SEL_8822B(v))
#define BIT_PS_TIMER_A_EN_8822B BIT(7)
#define BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822B 0
#define BIT_MASK_PS_TIMER_A_TSF_SEL_8822B 0x7
-#define BIT_PS_TIMER_A_TSF_SEL_8822B(x) (((x) & BIT_MASK_PS_TIMER_A_TSF_SEL_8822B) << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822B)
-#define BIT_GET_PS_TIMER_A_TSF_SEL_8822B(x) (((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822B) & BIT_MASK_PS_TIMER_A_TSF_SEL_8822B)
-
+#define BIT_PS_TIMER_A_TSF_SEL_8822B(x) \
+ (((x) & BIT_MASK_PS_TIMER_A_TSF_SEL_8822B) \
+ << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822B)
+#define BITS_PS_TIMER_A_TSF_SEL_8822B \
+ (BIT_MASK_PS_TIMER_A_TSF_SEL_8822B \
+ << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822B)
+#define BIT_CLEAR_PS_TIMER_A_TSF_SEL_8822B(x) \
+ ((x) & (~BITS_PS_TIMER_A_TSF_SEL_8822B))
+#define BIT_GET_PS_TIMER_A_TSF_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822B) & \
+ BIT_MASK_PS_TIMER_A_TSF_SEL_8822B)
+#define BIT_SET_PS_TIMER_A_TSF_SEL_8822B(x, v) \
+ (BIT_CLEAR_PS_TIMER_A_TSF_SEL_8822B(x) | \
+ BIT_PS_TIMER_A_TSF_SEL_8822B(v))
/* 2 REG_CPUMGQ_TX_TIMER_EARLY_8822B */
#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822B 0
#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822B 0xff
-#define BIT_CPUMGQ_TX_TIMER_EARLY_8822B(x) (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822B) << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822B)
-#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_8822B(x) (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822B) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822B)
-
+#define BIT_CPUMGQ_TX_TIMER_EARLY_8822B(x) \
+ (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822B) \
+ << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822B)
+#define BITS_CPUMGQ_TX_TIMER_EARLY_8822B \
+ (BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822B \
+ << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822B)
+#define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8822B(x) \
+ ((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY_8822B))
+#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_8822B(x) \
+ (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822B) & \
+ BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822B)
+#define BIT_SET_CPUMGQ_TX_TIMER_EARLY_8822B(x, v) \
+ (BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8822B(x) | \
+ BIT_CPUMGQ_TX_TIMER_EARLY_8822B(v))
/* 2 REG_PS_TIMER_A_EARLY_8822B */
#define BIT_SHIFT_PS_TIMER_A_EARLY_8822B 0
#define BIT_MASK_PS_TIMER_A_EARLY_8822B 0xff
-#define BIT_PS_TIMER_A_EARLY_8822B(x) (((x) & BIT_MASK_PS_TIMER_A_EARLY_8822B) << BIT_SHIFT_PS_TIMER_A_EARLY_8822B)
-#define BIT_GET_PS_TIMER_A_EARLY_8822B(x) (((x) >> BIT_SHIFT_PS_TIMER_A_EARLY_8822B) & BIT_MASK_PS_TIMER_A_EARLY_8822B)
-
+#define BIT_PS_TIMER_A_EARLY_8822B(x) \
+ (((x) & BIT_MASK_PS_TIMER_A_EARLY_8822B) \
+ << BIT_SHIFT_PS_TIMER_A_EARLY_8822B)
+#define BITS_PS_TIMER_A_EARLY_8822B \
+ (BIT_MASK_PS_TIMER_A_EARLY_8822B << BIT_SHIFT_PS_TIMER_A_EARLY_8822B)
+#define BIT_CLEAR_PS_TIMER_A_EARLY_8822B(x) \
+ ((x) & (~BITS_PS_TIMER_A_EARLY_8822B))
+#define BIT_GET_PS_TIMER_A_EARLY_8822B(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_A_EARLY_8822B) & \
+ BIT_MASK_PS_TIMER_A_EARLY_8822B)
+#define BIT_SET_PS_TIMER_A_EARLY_8822B(x, v) \
+ (BIT_CLEAR_PS_TIMER_A_EARLY_8822B(x) | BIT_PS_TIMER_A_EARLY_8822B(v))
/* 2 REG_PS_TIMER_B_EARLY_8822B */
#define BIT_SHIFT_PS_TIMER_B_EARLY_8822B 0
#define BIT_MASK_PS_TIMER_B_EARLY_8822B 0xff
-#define BIT_PS_TIMER_B_EARLY_8822B(x) (((x) & BIT_MASK_PS_TIMER_B_EARLY_8822B) << BIT_SHIFT_PS_TIMER_B_EARLY_8822B)
-#define BIT_GET_PS_TIMER_B_EARLY_8822B(x) (((x) >> BIT_SHIFT_PS_TIMER_B_EARLY_8822B) & BIT_MASK_PS_TIMER_B_EARLY_8822B)
-
+#define BIT_PS_TIMER_B_EARLY_8822B(x) \
+ (((x) & BIT_MASK_PS_TIMER_B_EARLY_8822B) \
+ << BIT_SHIFT_PS_TIMER_B_EARLY_8822B)
+#define BITS_PS_TIMER_B_EARLY_8822B \
+ (BIT_MASK_PS_TIMER_B_EARLY_8822B << BIT_SHIFT_PS_TIMER_B_EARLY_8822B)
+#define BIT_CLEAR_PS_TIMER_B_EARLY_8822B(x) \
+ ((x) & (~BITS_PS_TIMER_B_EARLY_8822B))
+#define BIT_GET_PS_TIMER_B_EARLY_8822B(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_B_EARLY_8822B) & \
+ BIT_MASK_PS_TIMER_B_EARLY_8822B)
+#define BIT_SET_PS_TIMER_B_EARLY_8822B(x, v) \
+ (BIT_CLEAR_PS_TIMER_B_EARLY_8822B(x) | BIT_PS_TIMER_B_EARLY_8822B(v))
/* 2 REG_PS_TIMER_C_EARLY_8822B */
#define BIT_SHIFT_PS_TIMER_C_EARLY_8822B 0
#define BIT_MASK_PS_TIMER_C_EARLY_8822B 0xff
-#define BIT_PS_TIMER_C_EARLY_8822B(x) (((x) & BIT_MASK_PS_TIMER_C_EARLY_8822B) << BIT_SHIFT_PS_TIMER_C_EARLY_8822B)
-#define BIT_GET_PS_TIMER_C_EARLY_8822B(x) (((x) >> BIT_SHIFT_PS_TIMER_C_EARLY_8822B) & BIT_MASK_PS_TIMER_C_EARLY_8822B)
+#define BIT_PS_TIMER_C_EARLY_8822B(x) \
+ (((x) & BIT_MASK_PS_TIMER_C_EARLY_8822B) \
+ << BIT_SHIFT_PS_TIMER_C_EARLY_8822B)
+#define BITS_PS_TIMER_C_EARLY_8822B \
+ (BIT_MASK_PS_TIMER_C_EARLY_8822B << BIT_SHIFT_PS_TIMER_C_EARLY_8822B)
+#define BIT_CLEAR_PS_TIMER_C_EARLY_8822B(x) \
+ ((x) & (~BITS_PS_TIMER_C_EARLY_8822B))
+#define BIT_GET_PS_TIMER_C_EARLY_8822B(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_C_EARLY_8822B) & \
+ BIT_MASK_PS_TIMER_C_EARLY_8822B)
+#define BIT_SET_PS_TIMER_C_EARLY_8822B(x, v) \
+ (BIT_CLEAR_PS_TIMER_C_EARLY_8822B(x) | BIT_PS_TIMER_C_EARLY_8822B(v))
+
+/* 2 REG_CPUMGQ_PARAMETER_8822B */
+/* 2 REG_NOT_VALID_8822B */
+#define BIT_MAC_STOP_CPUMGQ_8822B BIT(16)
+
+#define BIT_SHIFT_CW_8822B 8
+#define BIT_MASK_CW_8822B 0xff
+#define BIT_CW_8822B(x) (((x) & BIT_MASK_CW_8822B) << BIT_SHIFT_CW_8822B)
+#define BITS_CW_8822B (BIT_MASK_CW_8822B << BIT_SHIFT_CW_8822B)
+#define BIT_CLEAR_CW_8822B(x) ((x) & (~BITS_CW_8822B))
+#define BIT_GET_CW_8822B(x) (((x) >> BIT_SHIFT_CW_8822B) & BIT_MASK_CW_8822B)
+#define BIT_SET_CW_8822B(x, v) (BIT_CLEAR_CW_8822B(x) | BIT_CW_8822B(v))
+
+#define BIT_SHIFT_AIFS_8822B 0
+#define BIT_MASK_AIFS_8822B 0xff
+#define BIT_AIFS_8822B(x) (((x) & BIT_MASK_AIFS_8822B) << BIT_SHIFT_AIFS_8822B)
+#define BITS_AIFS_8822B (BIT_MASK_AIFS_8822B << BIT_SHIFT_AIFS_8822B)
+#define BIT_CLEAR_AIFS_8822B(x) ((x) & (~BITS_AIFS_8822B))
+#define BIT_GET_AIFS_8822B(x) \
+ (((x) >> BIT_SHIFT_AIFS_8822B) & BIT_MASK_AIFS_8822B)
+#define BIT_SET_AIFS_8822B(x, v) (BIT_CLEAR_AIFS_8822B(x) | BIT_AIFS_8822B(v))
/* 2 REG_NOT_VALID_8822B */
@@ -7481,9 +13219,17 @@
#define BIT_SHIFT_APPEND_MHDR_LEN_8822B 0
#define BIT_MASK_APPEND_MHDR_LEN_8822B 0x7
-#define BIT_APPEND_MHDR_LEN_8822B(x) (((x) & BIT_MASK_APPEND_MHDR_LEN_8822B) << BIT_SHIFT_APPEND_MHDR_LEN_8822B)
-#define BIT_GET_APPEND_MHDR_LEN_8822B(x) (((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8822B) & BIT_MASK_APPEND_MHDR_LEN_8822B)
-
+#define BIT_APPEND_MHDR_LEN_8822B(x) \
+ (((x) & BIT_MASK_APPEND_MHDR_LEN_8822B) \
+ << BIT_SHIFT_APPEND_MHDR_LEN_8822B)
+#define BITS_APPEND_MHDR_LEN_8822B \
+ (BIT_MASK_APPEND_MHDR_LEN_8822B << BIT_SHIFT_APPEND_MHDR_LEN_8822B)
+#define BIT_CLEAR_APPEND_MHDR_LEN_8822B(x) ((x) & (~BITS_APPEND_MHDR_LEN_8822B))
+#define BIT_GET_APPEND_MHDR_LEN_8822B(x) \
+ (((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8822B) & \
+ BIT_MASK_APPEND_MHDR_LEN_8822B)
+#define BIT_SET_APPEND_MHDR_LEN_8822B(x, v) \
+ (BIT_CLEAR_APPEND_MHDR_LEN_8822B(x) | BIT_APPEND_MHDR_LEN_8822B(v))
/* 2 REG_WMAC_CR_8822B (WMAC CR AND APSD CONTROL REGISTER) */
#define BIT_IC_MACPHY_M_8822B BIT(0)
@@ -7556,57 +13302,96 @@
#define BIT_SHIFT_DRVINFO_SZ_V1_8822B 0
#define BIT_MASK_DRVINFO_SZ_V1_8822B 0xf
-#define BIT_DRVINFO_SZ_V1_8822B(x) (((x) & BIT_MASK_DRVINFO_SZ_V1_8822B) << BIT_SHIFT_DRVINFO_SZ_V1_8822B)
-#define BIT_GET_DRVINFO_SZ_V1_8822B(x) (((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8822B) & BIT_MASK_DRVINFO_SZ_V1_8822B)
-
+#define BIT_DRVINFO_SZ_V1_8822B(x) \
+ (((x) & BIT_MASK_DRVINFO_SZ_V1_8822B) << BIT_SHIFT_DRVINFO_SZ_V1_8822B)
+#define BITS_DRVINFO_SZ_V1_8822B \
+ (BIT_MASK_DRVINFO_SZ_V1_8822B << BIT_SHIFT_DRVINFO_SZ_V1_8822B)
+#define BIT_CLEAR_DRVINFO_SZ_V1_8822B(x) ((x) & (~BITS_DRVINFO_SZ_V1_8822B))
+#define BIT_GET_DRVINFO_SZ_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8822B) & BIT_MASK_DRVINFO_SZ_V1_8822B)
+#define BIT_SET_DRVINFO_SZ_V1_8822B(x, v) \
+ (BIT_CLEAR_DRVINFO_SZ_V1_8822B(x) | BIT_DRVINFO_SZ_V1_8822B(v))
/* 2 REG_RX_DLK_TIME_8822B (RX DEADLOCK TIME REGISTER) */
#define BIT_SHIFT_RX_DLK_TIME_8822B 0
#define BIT_MASK_RX_DLK_TIME_8822B 0xff
-#define BIT_RX_DLK_TIME_8822B(x) (((x) & BIT_MASK_RX_DLK_TIME_8822B) << BIT_SHIFT_RX_DLK_TIME_8822B)
-#define BIT_GET_RX_DLK_TIME_8822B(x) (((x) >> BIT_SHIFT_RX_DLK_TIME_8822B) & BIT_MASK_RX_DLK_TIME_8822B)
-
+#define BIT_RX_DLK_TIME_8822B(x) \
+ (((x) & BIT_MASK_RX_DLK_TIME_8822B) << BIT_SHIFT_RX_DLK_TIME_8822B)
+#define BITS_RX_DLK_TIME_8822B \
+ (BIT_MASK_RX_DLK_TIME_8822B << BIT_SHIFT_RX_DLK_TIME_8822B)
+#define BIT_CLEAR_RX_DLK_TIME_8822B(x) ((x) & (~BITS_RX_DLK_TIME_8822B))
+#define BIT_GET_RX_DLK_TIME_8822B(x) \
+ (((x) >> BIT_SHIFT_RX_DLK_TIME_8822B) & BIT_MASK_RX_DLK_TIME_8822B)
+#define BIT_SET_RX_DLK_TIME_8822B(x, v) \
+ (BIT_CLEAR_RX_DLK_TIME_8822B(x) | BIT_RX_DLK_TIME_8822B(v))
/* 2 REG_RX_PKT_LIMIT_8822B (RX PACKET LENGTH LIMIT REGISTER) */
#define BIT_SHIFT_RXPKTLMT_8822B 0
#define BIT_MASK_RXPKTLMT_8822B 0x3f
-#define BIT_RXPKTLMT_8822B(x) (((x) & BIT_MASK_RXPKTLMT_8822B) << BIT_SHIFT_RXPKTLMT_8822B)
-#define BIT_GET_RXPKTLMT_8822B(x) (((x) >> BIT_SHIFT_RXPKTLMT_8822B) & BIT_MASK_RXPKTLMT_8822B)
-
+#define BIT_RXPKTLMT_8822B(x) \
+ (((x) & BIT_MASK_RXPKTLMT_8822B) << BIT_SHIFT_RXPKTLMT_8822B)
+#define BITS_RXPKTLMT_8822B \
+ (BIT_MASK_RXPKTLMT_8822B << BIT_SHIFT_RXPKTLMT_8822B)
+#define BIT_CLEAR_RXPKTLMT_8822B(x) ((x) & (~BITS_RXPKTLMT_8822B))
+#define BIT_GET_RXPKTLMT_8822B(x) \
+ (((x) >> BIT_SHIFT_RXPKTLMT_8822B) & BIT_MASK_RXPKTLMT_8822B)
+#define BIT_SET_RXPKTLMT_8822B(x, v) \
+ (BIT_CLEAR_RXPKTLMT_8822B(x) | BIT_RXPKTLMT_8822B(v))
/* 2 REG_MACID_8822B (MAC ID REGISTER) */
#define BIT_SHIFT_MACID_8822B 0
#define BIT_MASK_MACID_8822B 0xffffffffffffL
-#define BIT_MACID_8822B(x) (((x) & BIT_MASK_MACID_8822B) << BIT_SHIFT_MACID_8822B)
-#define BIT_GET_MACID_8822B(x) (((x) >> BIT_SHIFT_MACID_8822B) & BIT_MASK_MACID_8822B)
-
+#define BIT_MACID_8822B(x) \
+ (((x) & BIT_MASK_MACID_8822B) << BIT_SHIFT_MACID_8822B)
+#define BITS_MACID_8822B (BIT_MASK_MACID_8822B << BIT_SHIFT_MACID_8822B)
+#define BIT_CLEAR_MACID_8822B(x) ((x) & (~BITS_MACID_8822B))
+#define BIT_GET_MACID_8822B(x) \
+ (((x) >> BIT_SHIFT_MACID_8822B) & BIT_MASK_MACID_8822B)
+#define BIT_SET_MACID_8822B(x, v) \
+ (BIT_CLEAR_MACID_8822B(x) | BIT_MACID_8822B(v))
/* 2 REG_BSSID_8822B (BSSID REGISTER) */
#define BIT_SHIFT_BSSID_8822B 0
#define BIT_MASK_BSSID_8822B 0xffffffffffffL
-#define BIT_BSSID_8822B(x) (((x) & BIT_MASK_BSSID_8822B) << BIT_SHIFT_BSSID_8822B)
-#define BIT_GET_BSSID_8822B(x) (((x) >> BIT_SHIFT_BSSID_8822B) & BIT_MASK_BSSID_8822B)
-
+#define BIT_BSSID_8822B(x) \
+ (((x) & BIT_MASK_BSSID_8822B) << BIT_SHIFT_BSSID_8822B)
+#define BITS_BSSID_8822B (BIT_MASK_BSSID_8822B << BIT_SHIFT_BSSID_8822B)
+#define BIT_CLEAR_BSSID_8822B(x) ((x) & (~BITS_BSSID_8822B))
+#define BIT_GET_BSSID_8822B(x) \
+ (((x) >> BIT_SHIFT_BSSID_8822B) & BIT_MASK_BSSID_8822B)
+#define BIT_SET_BSSID_8822B(x, v) \
+ (BIT_CLEAR_BSSID_8822B(x) | BIT_BSSID_8822B(v))
/* 2 REG_MAR_8822B (MULTICAST ADDRESS REGISTER) */
#define BIT_SHIFT_MAR_8822B 0
#define BIT_MASK_MAR_8822B 0xffffffffffffffffL
#define BIT_MAR_8822B(x) (((x) & BIT_MASK_MAR_8822B) << BIT_SHIFT_MAR_8822B)
+#define BITS_MAR_8822B (BIT_MASK_MAR_8822B << BIT_SHIFT_MAR_8822B)
+#define BIT_CLEAR_MAR_8822B(x) ((x) & (~BITS_MAR_8822B))
#define BIT_GET_MAR_8822B(x) (((x) >> BIT_SHIFT_MAR_8822B) & BIT_MASK_MAR_8822B)
-
+#define BIT_SET_MAR_8822B(x, v) (BIT_CLEAR_MAR_8822B(x) | BIT_MAR_8822B(v))
/* 2 REG_MBIDCAMCFG_1_8822B (MBSSID CAM CONFIGURATION REGISTER) */
#define BIT_SHIFT_MBIDCAM_RWDATA_L_8822B 0
#define BIT_MASK_MBIDCAM_RWDATA_L_8822B 0xffffffffL
-#define BIT_MBIDCAM_RWDATA_L_8822B(x) (((x) & BIT_MASK_MBIDCAM_RWDATA_L_8822B) << BIT_SHIFT_MBIDCAM_RWDATA_L_8822B)
-#define BIT_GET_MBIDCAM_RWDATA_L_8822B(x) (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L_8822B) & BIT_MASK_MBIDCAM_RWDATA_L_8822B)
-
+#define BIT_MBIDCAM_RWDATA_L_8822B(x) \
+ (((x) & BIT_MASK_MBIDCAM_RWDATA_L_8822B) \
+ << BIT_SHIFT_MBIDCAM_RWDATA_L_8822B)
+#define BITS_MBIDCAM_RWDATA_L_8822B \
+ (BIT_MASK_MBIDCAM_RWDATA_L_8822B << BIT_SHIFT_MBIDCAM_RWDATA_L_8822B)
+#define BIT_CLEAR_MBIDCAM_RWDATA_L_8822B(x) \
+ ((x) & (~BITS_MBIDCAM_RWDATA_L_8822B))
+#define BIT_GET_MBIDCAM_RWDATA_L_8822B(x) \
+ (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L_8822B) & \
+ BIT_MASK_MBIDCAM_RWDATA_L_8822B)
+#define BIT_SET_MBIDCAM_RWDATA_L_8822B(x, v) \
+ (BIT_CLEAR_MBIDCAM_RWDATA_L_8822B(x) | BIT_MBIDCAM_RWDATA_L_8822B(v))
/* 2 REG_MBIDCAMCFG_2_8822B (MBSSID CAM CONFIGURATION REGISTER) */
#define BIT_MBIDCAM_POLL_8822B BIT(31)
@@ -7614,8 +13399,15 @@
#define BIT_SHIFT_MBIDCAM_ADDR_8822B 24
#define BIT_MASK_MBIDCAM_ADDR_8822B 0x1f
-#define BIT_MBIDCAM_ADDR_8822B(x) (((x) & BIT_MASK_MBIDCAM_ADDR_8822B) << BIT_SHIFT_MBIDCAM_ADDR_8822B)
-#define BIT_GET_MBIDCAM_ADDR_8822B(x) (((x) >> BIT_SHIFT_MBIDCAM_ADDR_8822B) & BIT_MASK_MBIDCAM_ADDR_8822B)
+#define BIT_MBIDCAM_ADDR_8822B(x) \
+ (((x) & BIT_MASK_MBIDCAM_ADDR_8822B) << BIT_SHIFT_MBIDCAM_ADDR_8822B)
+#define BITS_MBIDCAM_ADDR_8822B \
+ (BIT_MASK_MBIDCAM_ADDR_8822B << BIT_SHIFT_MBIDCAM_ADDR_8822B)
+#define BIT_CLEAR_MBIDCAM_ADDR_8822B(x) ((x) & (~BITS_MBIDCAM_ADDR_8822B))
+#define BIT_GET_MBIDCAM_ADDR_8822B(x) \
+ (((x) >> BIT_SHIFT_MBIDCAM_ADDR_8822B) & BIT_MASK_MBIDCAM_ADDR_8822B)
+#define BIT_SET_MBIDCAM_ADDR_8822B(x, v) \
+ (BIT_CLEAR_MBIDCAM_ADDR_8822B(x) | BIT_MBIDCAM_ADDR_8822B(v))
#define BIT_MBIDCAM_VALID_8822B BIT(23)
#define BIT_LSIC_TXOP_EN_8822B BIT(17)
@@ -7623,151 +13415,276 @@
#define BIT_SHIFT_MBIDCAM_RWDATA_H_8822B 0
#define BIT_MASK_MBIDCAM_RWDATA_H_8822B 0xffff
-#define BIT_MBIDCAM_RWDATA_H_8822B(x) (((x) & BIT_MASK_MBIDCAM_RWDATA_H_8822B) << BIT_SHIFT_MBIDCAM_RWDATA_H_8822B)
-#define BIT_GET_MBIDCAM_RWDATA_H_8822B(x) (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H_8822B) & BIT_MASK_MBIDCAM_RWDATA_H_8822B)
-
+#define BIT_MBIDCAM_RWDATA_H_8822B(x) \
+ (((x) & BIT_MASK_MBIDCAM_RWDATA_H_8822B) \
+ << BIT_SHIFT_MBIDCAM_RWDATA_H_8822B)
+#define BITS_MBIDCAM_RWDATA_H_8822B \
+ (BIT_MASK_MBIDCAM_RWDATA_H_8822B << BIT_SHIFT_MBIDCAM_RWDATA_H_8822B)
+#define BIT_CLEAR_MBIDCAM_RWDATA_H_8822B(x) \
+ ((x) & (~BITS_MBIDCAM_RWDATA_H_8822B))
+#define BIT_GET_MBIDCAM_RWDATA_H_8822B(x) \
+ (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H_8822B) & \
+ BIT_MASK_MBIDCAM_RWDATA_H_8822B)
+#define BIT_SET_MBIDCAM_RWDATA_H_8822B(x, v) \
+ (BIT_CLEAR_MBIDCAM_RWDATA_H_8822B(x) | BIT_MBIDCAM_RWDATA_H_8822B(v))
/* 2 REG_ZLD_NUM_8822B */
#define BIT_SHIFT_ZLD_NUM_8822B 0
#define BIT_MASK_ZLD_NUM_8822B 0xff
-#define BIT_ZLD_NUM_8822B(x) (((x) & BIT_MASK_ZLD_NUM_8822B) << BIT_SHIFT_ZLD_NUM_8822B)
-#define BIT_GET_ZLD_NUM_8822B(x) (((x) >> BIT_SHIFT_ZLD_NUM_8822B) & BIT_MASK_ZLD_NUM_8822B)
-
+#define BIT_ZLD_NUM_8822B(x) \
+ (((x) & BIT_MASK_ZLD_NUM_8822B) << BIT_SHIFT_ZLD_NUM_8822B)
+#define BITS_ZLD_NUM_8822B (BIT_MASK_ZLD_NUM_8822B << BIT_SHIFT_ZLD_NUM_8822B)
+#define BIT_CLEAR_ZLD_NUM_8822B(x) ((x) & (~BITS_ZLD_NUM_8822B))
+#define BIT_GET_ZLD_NUM_8822B(x) \
+ (((x) >> BIT_SHIFT_ZLD_NUM_8822B) & BIT_MASK_ZLD_NUM_8822B)
+#define BIT_SET_ZLD_NUM_8822B(x, v) \
+ (BIT_CLEAR_ZLD_NUM_8822B(x) | BIT_ZLD_NUM_8822B(v))
/* 2 REG_UDF_THSD_8822B */
#define BIT_SHIFT_UDF_THSD_8822B 0
#define BIT_MASK_UDF_THSD_8822B 0xff
-#define BIT_UDF_THSD_8822B(x) (((x) & BIT_MASK_UDF_THSD_8822B) << BIT_SHIFT_UDF_THSD_8822B)
-#define BIT_GET_UDF_THSD_8822B(x) (((x) >> BIT_SHIFT_UDF_THSD_8822B) & BIT_MASK_UDF_THSD_8822B)
-
+#define BIT_UDF_THSD_8822B(x) \
+ (((x) & BIT_MASK_UDF_THSD_8822B) << BIT_SHIFT_UDF_THSD_8822B)
+#define BITS_UDF_THSD_8822B \
+ (BIT_MASK_UDF_THSD_8822B << BIT_SHIFT_UDF_THSD_8822B)
+#define BIT_CLEAR_UDF_THSD_8822B(x) ((x) & (~BITS_UDF_THSD_8822B))
+#define BIT_GET_UDF_THSD_8822B(x) \
+ (((x) >> BIT_SHIFT_UDF_THSD_8822B) & BIT_MASK_UDF_THSD_8822B)
+#define BIT_SET_UDF_THSD_8822B(x, v) \
+ (BIT_CLEAR_UDF_THSD_8822B(x) | BIT_UDF_THSD_8822B(v))
/* 2 REG_WMAC_TCR_TSFT_OFS_8822B */
#define BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822B 0
#define BIT_MASK_WMAC_TCR_TSFT_OFS_8822B 0xffff
-#define BIT_WMAC_TCR_TSFT_OFS_8822B(x) (((x) & BIT_MASK_WMAC_TCR_TSFT_OFS_8822B) << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822B)
-#define BIT_GET_WMAC_TCR_TSFT_OFS_8822B(x) (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822B) & BIT_MASK_WMAC_TCR_TSFT_OFS_8822B)
-
+#define BIT_WMAC_TCR_TSFT_OFS_8822B(x) \
+ (((x) & BIT_MASK_WMAC_TCR_TSFT_OFS_8822B) \
+ << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822B)
+#define BITS_WMAC_TCR_TSFT_OFS_8822B \
+ (BIT_MASK_WMAC_TCR_TSFT_OFS_8822B << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822B)
+#define BIT_CLEAR_WMAC_TCR_TSFT_OFS_8822B(x) \
+ ((x) & (~BITS_WMAC_TCR_TSFT_OFS_8822B))
+#define BIT_GET_WMAC_TCR_TSFT_OFS_8822B(x) \
+ (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822B) & \
+ BIT_MASK_WMAC_TCR_TSFT_OFS_8822B)
+#define BIT_SET_WMAC_TCR_TSFT_OFS_8822B(x, v) \
+ (BIT_CLEAR_WMAC_TCR_TSFT_OFS_8822B(x) | BIT_WMAC_TCR_TSFT_OFS_8822B(v))
/* 2 REG_MCU_TEST_2_V1_8822B */
#define BIT_SHIFT_MCU_RSVD_2_V1_8822B 0
#define BIT_MASK_MCU_RSVD_2_V1_8822B 0xffff
-#define BIT_MCU_RSVD_2_V1_8822B(x) (((x) & BIT_MASK_MCU_RSVD_2_V1_8822B) << BIT_SHIFT_MCU_RSVD_2_V1_8822B)
-#define BIT_GET_MCU_RSVD_2_V1_8822B(x) (((x) >> BIT_SHIFT_MCU_RSVD_2_V1_8822B) & BIT_MASK_MCU_RSVD_2_V1_8822B)
-
+#define BIT_MCU_RSVD_2_V1_8822B(x) \
+ (((x) & BIT_MASK_MCU_RSVD_2_V1_8822B) << BIT_SHIFT_MCU_RSVD_2_V1_8822B)
+#define BITS_MCU_RSVD_2_V1_8822B \
+ (BIT_MASK_MCU_RSVD_2_V1_8822B << BIT_SHIFT_MCU_RSVD_2_V1_8822B)
+#define BIT_CLEAR_MCU_RSVD_2_V1_8822B(x) ((x) & (~BITS_MCU_RSVD_2_V1_8822B))
+#define BIT_GET_MCU_RSVD_2_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_MCU_RSVD_2_V1_8822B) & BIT_MASK_MCU_RSVD_2_V1_8822B)
+#define BIT_SET_MCU_RSVD_2_V1_8822B(x, v) \
+ (BIT_CLEAR_MCU_RSVD_2_V1_8822B(x) | BIT_MCU_RSVD_2_V1_8822B(v))
/* 2 REG_WMAC_TXTIMEOUT_8822B */
#define BIT_SHIFT_WMAC_TXTIMEOUT_8822B 0
#define BIT_MASK_WMAC_TXTIMEOUT_8822B 0xff
-#define BIT_WMAC_TXTIMEOUT_8822B(x) (((x) & BIT_MASK_WMAC_TXTIMEOUT_8822B) << BIT_SHIFT_WMAC_TXTIMEOUT_8822B)
-#define BIT_GET_WMAC_TXTIMEOUT_8822B(x) (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8822B) & BIT_MASK_WMAC_TXTIMEOUT_8822B)
-
+#define BIT_WMAC_TXTIMEOUT_8822B(x) \
+ (((x) & BIT_MASK_WMAC_TXTIMEOUT_8822B) \
+ << BIT_SHIFT_WMAC_TXTIMEOUT_8822B)
+#define BITS_WMAC_TXTIMEOUT_8822B \
+ (BIT_MASK_WMAC_TXTIMEOUT_8822B << BIT_SHIFT_WMAC_TXTIMEOUT_8822B)
+#define BIT_CLEAR_WMAC_TXTIMEOUT_8822B(x) ((x) & (~BITS_WMAC_TXTIMEOUT_8822B))
+#define BIT_GET_WMAC_TXTIMEOUT_8822B(x) \
+ (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8822B) & \
+ BIT_MASK_WMAC_TXTIMEOUT_8822B)
+#define BIT_SET_WMAC_TXTIMEOUT_8822B(x, v) \
+ (BIT_CLEAR_WMAC_TXTIMEOUT_8822B(x) | BIT_WMAC_TXTIMEOUT_8822B(v))
/* 2 REG_STMP_THSD_8822B */
#define BIT_SHIFT_STMP_THSD_8822B 0
#define BIT_MASK_STMP_THSD_8822B 0xff
-#define BIT_STMP_THSD_8822B(x) (((x) & BIT_MASK_STMP_THSD_8822B) << BIT_SHIFT_STMP_THSD_8822B)
-#define BIT_GET_STMP_THSD_8822B(x) (((x) >> BIT_SHIFT_STMP_THSD_8822B) & BIT_MASK_STMP_THSD_8822B)
-
+#define BIT_STMP_THSD_8822B(x) \
+ (((x) & BIT_MASK_STMP_THSD_8822B) << BIT_SHIFT_STMP_THSD_8822B)
+#define BITS_STMP_THSD_8822B \
+ (BIT_MASK_STMP_THSD_8822B << BIT_SHIFT_STMP_THSD_8822B)
+#define BIT_CLEAR_STMP_THSD_8822B(x) ((x) & (~BITS_STMP_THSD_8822B))
+#define BIT_GET_STMP_THSD_8822B(x) \
+ (((x) >> BIT_SHIFT_STMP_THSD_8822B) & BIT_MASK_STMP_THSD_8822B)
+#define BIT_SET_STMP_THSD_8822B(x, v) \
+ (BIT_CLEAR_STMP_THSD_8822B(x) | BIT_STMP_THSD_8822B(v))
/* 2 REG_MAC_SPEC_SIFS_8822B (SPECIFICATION SIFS REGISTER) */
#define BIT_SHIFT_SPEC_SIFS_OFDM_8822B 8
#define BIT_MASK_SPEC_SIFS_OFDM_8822B 0xff
-#define BIT_SPEC_SIFS_OFDM_8822B(x) (((x) & BIT_MASK_SPEC_SIFS_OFDM_8822B) << BIT_SHIFT_SPEC_SIFS_OFDM_8822B)
-#define BIT_GET_SPEC_SIFS_OFDM_8822B(x) (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8822B) & BIT_MASK_SPEC_SIFS_OFDM_8822B)
-
+#define BIT_SPEC_SIFS_OFDM_8822B(x) \
+ (((x) & BIT_MASK_SPEC_SIFS_OFDM_8822B) \
+ << BIT_SHIFT_SPEC_SIFS_OFDM_8822B)
+#define BITS_SPEC_SIFS_OFDM_8822B \
+ (BIT_MASK_SPEC_SIFS_OFDM_8822B << BIT_SHIFT_SPEC_SIFS_OFDM_8822B)
+#define BIT_CLEAR_SPEC_SIFS_OFDM_8822B(x) ((x) & (~BITS_SPEC_SIFS_OFDM_8822B))
+#define BIT_GET_SPEC_SIFS_OFDM_8822B(x) \
+ (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8822B) & \
+ BIT_MASK_SPEC_SIFS_OFDM_8822B)
+#define BIT_SET_SPEC_SIFS_OFDM_8822B(x, v) \
+ (BIT_CLEAR_SPEC_SIFS_OFDM_8822B(x) | BIT_SPEC_SIFS_OFDM_8822B(v))
#define BIT_SHIFT_SPEC_SIFS_CCK_8822B 0
#define BIT_MASK_SPEC_SIFS_CCK_8822B 0xff
-#define BIT_SPEC_SIFS_CCK_8822B(x) (((x) & BIT_MASK_SPEC_SIFS_CCK_8822B) << BIT_SHIFT_SPEC_SIFS_CCK_8822B)
-#define BIT_GET_SPEC_SIFS_CCK_8822B(x) (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8822B) & BIT_MASK_SPEC_SIFS_CCK_8822B)
-
+#define BIT_SPEC_SIFS_CCK_8822B(x) \
+ (((x) & BIT_MASK_SPEC_SIFS_CCK_8822B) << BIT_SHIFT_SPEC_SIFS_CCK_8822B)
+#define BITS_SPEC_SIFS_CCK_8822B \
+ (BIT_MASK_SPEC_SIFS_CCK_8822B << BIT_SHIFT_SPEC_SIFS_CCK_8822B)
+#define BIT_CLEAR_SPEC_SIFS_CCK_8822B(x) ((x) & (~BITS_SPEC_SIFS_CCK_8822B))
+#define BIT_GET_SPEC_SIFS_CCK_8822B(x) \
+ (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8822B) & BIT_MASK_SPEC_SIFS_CCK_8822B)
+#define BIT_SET_SPEC_SIFS_CCK_8822B(x, v) \
+ (BIT_CLEAR_SPEC_SIFS_CCK_8822B(x) | BIT_SPEC_SIFS_CCK_8822B(v))
/* 2 REG_USTIME_EDCA_8822B (US TIME TUNING FOR EDCA REGISTER) */
#define BIT_SHIFT_USTIME_EDCA_V1_8822B 0
#define BIT_MASK_USTIME_EDCA_V1_8822B 0x1ff
-#define BIT_USTIME_EDCA_V1_8822B(x) (((x) & BIT_MASK_USTIME_EDCA_V1_8822B) << BIT_SHIFT_USTIME_EDCA_V1_8822B)
-#define BIT_GET_USTIME_EDCA_V1_8822B(x) (((x) >> BIT_SHIFT_USTIME_EDCA_V1_8822B) & BIT_MASK_USTIME_EDCA_V1_8822B)
-
+#define BIT_USTIME_EDCA_V1_8822B(x) \
+ (((x) & BIT_MASK_USTIME_EDCA_V1_8822B) \
+ << BIT_SHIFT_USTIME_EDCA_V1_8822B)
+#define BITS_USTIME_EDCA_V1_8822B \
+ (BIT_MASK_USTIME_EDCA_V1_8822B << BIT_SHIFT_USTIME_EDCA_V1_8822B)
+#define BIT_CLEAR_USTIME_EDCA_V1_8822B(x) ((x) & (~BITS_USTIME_EDCA_V1_8822B))
+#define BIT_GET_USTIME_EDCA_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_USTIME_EDCA_V1_8822B) & \
+ BIT_MASK_USTIME_EDCA_V1_8822B)
+#define BIT_SET_USTIME_EDCA_V1_8822B(x, v) \
+ (BIT_CLEAR_USTIME_EDCA_V1_8822B(x) | BIT_USTIME_EDCA_V1_8822B(v))
/* 2 REG_RESP_SIFS_OFDM_8822B (RESPONSE SIFS FOR OFDM REGISTER) */
#define BIT_SHIFT_SIFS_R2T_OFDM_8822B 8
#define BIT_MASK_SIFS_R2T_OFDM_8822B 0xff
-#define BIT_SIFS_R2T_OFDM_8822B(x) (((x) & BIT_MASK_SIFS_R2T_OFDM_8822B) << BIT_SHIFT_SIFS_R2T_OFDM_8822B)
-#define BIT_GET_SIFS_R2T_OFDM_8822B(x) (((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8822B) & BIT_MASK_SIFS_R2T_OFDM_8822B)
-
+#define BIT_SIFS_R2T_OFDM_8822B(x) \
+ (((x) & BIT_MASK_SIFS_R2T_OFDM_8822B) << BIT_SHIFT_SIFS_R2T_OFDM_8822B)
+#define BITS_SIFS_R2T_OFDM_8822B \
+ (BIT_MASK_SIFS_R2T_OFDM_8822B << BIT_SHIFT_SIFS_R2T_OFDM_8822B)
+#define BIT_CLEAR_SIFS_R2T_OFDM_8822B(x) ((x) & (~BITS_SIFS_R2T_OFDM_8822B))
+#define BIT_GET_SIFS_R2T_OFDM_8822B(x) \
+ (((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8822B) & BIT_MASK_SIFS_R2T_OFDM_8822B)
+#define BIT_SET_SIFS_R2T_OFDM_8822B(x, v) \
+ (BIT_CLEAR_SIFS_R2T_OFDM_8822B(x) | BIT_SIFS_R2T_OFDM_8822B(v))
#define BIT_SHIFT_SIFS_T2T_OFDM_8822B 0
#define BIT_MASK_SIFS_T2T_OFDM_8822B 0xff
-#define BIT_SIFS_T2T_OFDM_8822B(x) (((x) & BIT_MASK_SIFS_T2T_OFDM_8822B) << BIT_SHIFT_SIFS_T2T_OFDM_8822B)
-#define BIT_GET_SIFS_T2T_OFDM_8822B(x) (((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8822B) & BIT_MASK_SIFS_T2T_OFDM_8822B)
-
+#define BIT_SIFS_T2T_OFDM_8822B(x) \
+ (((x) & BIT_MASK_SIFS_T2T_OFDM_8822B) << BIT_SHIFT_SIFS_T2T_OFDM_8822B)
+#define BITS_SIFS_T2T_OFDM_8822B \
+ (BIT_MASK_SIFS_T2T_OFDM_8822B << BIT_SHIFT_SIFS_T2T_OFDM_8822B)
+#define BIT_CLEAR_SIFS_T2T_OFDM_8822B(x) ((x) & (~BITS_SIFS_T2T_OFDM_8822B))
+#define BIT_GET_SIFS_T2T_OFDM_8822B(x) \
+ (((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8822B) & BIT_MASK_SIFS_T2T_OFDM_8822B)
+#define BIT_SET_SIFS_T2T_OFDM_8822B(x, v) \
+ (BIT_CLEAR_SIFS_T2T_OFDM_8822B(x) | BIT_SIFS_T2T_OFDM_8822B(v))
/* 2 REG_RESP_SIFS_CCK_8822B (RESPONSE SIFS FOR CCK REGISTER) */
#define BIT_SHIFT_SIFS_R2T_CCK_8822B 8
#define BIT_MASK_SIFS_R2T_CCK_8822B 0xff
-#define BIT_SIFS_R2T_CCK_8822B(x) (((x) & BIT_MASK_SIFS_R2T_CCK_8822B) << BIT_SHIFT_SIFS_R2T_CCK_8822B)
-#define BIT_GET_SIFS_R2T_CCK_8822B(x) (((x) >> BIT_SHIFT_SIFS_R2T_CCK_8822B) & BIT_MASK_SIFS_R2T_CCK_8822B)
-
+#define BIT_SIFS_R2T_CCK_8822B(x) \
+ (((x) & BIT_MASK_SIFS_R2T_CCK_8822B) << BIT_SHIFT_SIFS_R2T_CCK_8822B)
+#define BITS_SIFS_R2T_CCK_8822B \
+ (BIT_MASK_SIFS_R2T_CCK_8822B << BIT_SHIFT_SIFS_R2T_CCK_8822B)
+#define BIT_CLEAR_SIFS_R2T_CCK_8822B(x) ((x) & (~BITS_SIFS_R2T_CCK_8822B))
+#define BIT_GET_SIFS_R2T_CCK_8822B(x) \
+ (((x) >> BIT_SHIFT_SIFS_R2T_CCK_8822B) & BIT_MASK_SIFS_R2T_CCK_8822B)
+#define BIT_SET_SIFS_R2T_CCK_8822B(x, v) \
+ (BIT_CLEAR_SIFS_R2T_CCK_8822B(x) | BIT_SIFS_R2T_CCK_8822B(v))
#define BIT_SHIFT_SIFS_T2T_CCK_8822B 0
#define BIT_MASK_SIFS_T2T_CCK_8822B 0xff
-#define BIT_SIFS_T2T_CCK_8822B(x) (((x) & BIT_MASK_SIFS_T2T_CCK_8822B) << BIT_SHIFT_SIFS_T2T_CCK_8822B)
-#define BIT_GET_SIFS_T2T_CCK_8822B(x) (((x) >> BIT_SHIFT_SIFS_T2T_CCK_8822B) & BIT_MASK_SIFS_T2T_CCK_8822B)
-
+#define BIT_SIFS_T2T_CCK_8822B(x) \
+ (((x) & BIT_MASK_SIFS_T2T_CCK_8822B) << BIT_SHIFT_SIFS_T2T_CCK_8822B)
+#define BITS_SIFS_T2T_CCK_8822B \
+ (BIT_MASK_SIFS_T2T_CCK_8822B << BIT_SHIFT_SIFS_T2T_CCK_8822B)
+#define BIT_CLEAR_SIFS_T2T_CCK_8822B(x) ((x) & (~BITS_SIFS_T2T_CCK_8822B))
+#define BIT_GET_SIFS_T2T_CCK_8822B(x) \
+ (((x) >> BIT_SHIFT_SIFS_T2T_CCK_8822B) & BIT_MASK_SIFS_T2T_CCK_8822B)
+#define BIT_SET_SIFS_T2T_CCK_8822B(x, v) \
+ (BIT_CLEAR_SIFS_T2T_CCK_8822B(x) | BIT_SIFS_T2T_CCK_8822B(v))
/* 2 REG_EIFS_8822B (EIFS REGISTER) */
#define BIT_SHIFT_EIFS_8822B 0
#define BIT_MASK_EIFS_8822B 0xffff
#define BIT_EIFS_8822B(x) (((x) & BIT_MASK_EIFS_8822B) << BIT_SHIFT_EIFS_8822B)
-#define BIT_GET_EIFS_8822B(x) (((x) >> BIT_SHIFT_EIFS_8822B) & BIT_MASK_EIFS_8822B)
-
+#define BITS_EIFS_8822B (BIT_MASK_EIFS_8822B << BIT_SHIFT_EIFS_8822B)
+#define BIT_CLEAR_EIFS_8822B(x) ((x) & (~BITS_EIFS_8822B))
+#define BIT_GET_EIFS_8822B(x) \
+ (((x) >> BIT_SHIFT_EIFS_8822B) & BIT_MASK_EIFS_8822B)
+#define BIT_SET_EIFS_8822B(x, v) (BIT_CLEAR_EIFS_8822B(x) | BIT_EIFS_8822B(v))
/* 2 REG_CTS2TO_8822B (CTS2 TIMEOUT REGISTER) */
#define BIT_SHIFT_CTS2TO_8822B 0
#define BIT_MASK_CTS2TO_8822B 0xff
-#define BIT_CTS2TO_8822B(x) (((x) & BIT_MASK_CTS2TO_8822B) << BIT_SHIFT_CTS2TO_8822B)
-#define BIT_GET_CTS2TO_8822B(x) (((x) >> BIT_SHIFT_CTS2TO_8822B) & BIT_MASK_CTS2TO_8822B)
-
+#define BIT_CTS2TO_8822B(x) \
+ (((x) & BIT_MASK_CTS2TO_8822B) << BIT_SHIFT_CTS2TO_8822B)
+#define BITS_CTS2TO_8822B (BIT_MASK_CTS2TO_8822B << BIT_SHIFT_CTS2TO_8822B)
+#define BIT_CLEAR_CTS2TO_8822B(x) ((x) & (~BITS_CTS2TO_8822B))
+#define BIT_GET_CTS2TO_8822B(x) \
+ (((x) >> BIT_SHIFT_CTS2TO_8822B) & BIT_MASK_CTS2TO_8822B)
+#define BIT_SET_CTS2TO_8822B(x, v) \
+ (BIT_CLEAR_CTS2TO_8822B(x) | BIT_CTS2TO_8822B(v))
/* 2 REG_ACKTO_8822B (ACK TIMEOUT REGISTER) */
#define BIT_SHIFT_ACKTO_8822B 0
#define BIT_MASK_ACKTO_8822B 0xff
-#define BIT_ACKTO_8822B(x) (((x) & BIT_MASK_ACKTO_8822B) << BIT_SHIFT_ACKTO_8822B)
-#define BIT_GET_ACKTO_8822B(x) (((x) >> BIT_SHIFT_ACKTO_8822B) & BIT_MASK_ACKTO_8822B)
-
+#define BIT_ACKTO_8822B(x) \
+ (((x) & BIT_MASK_ACKTO_8822B) << BIT_SHIFT_ACKTO_8822B)
+#define BITS_ACKTO_8822B (BIT_MASK_ACKTO_8822B << BIT_SHIFT_ACKTO_8822B)
+#define BIT_CLEAR_ACKTO_8822B(x) ((x) & (~BITS_ACKTO_8822B))
+#define BIT_GET_ACKTO_8822B(x) \
+ (((x) >> BIT_SHIFT_ACKTO_8822B) & BIT_MASK_ACKTO_8822B)
+#define BIT_SET_ACKTO_8822B(x, v) \
+ (BIT_CLEAR_ACKTO_8822B(x) | BIT_ACKTO_8822B(v))
/* 2 REG_NAV_CTRL_8822B (NAV CONTROL REGISTER) */
#define BIT_SHIFT_NAV_UPPER_8822B 16
#define BIT_MASK_NAV_UPPER_8822B 0xff
-#define BIT_NAV_UPPER_8822B(x) (((x) & BIT_MASK_NAV_UPPER_8822B) << BIT_SHIFT_NAV_UPPER_8822B)
-#define BIT_GET_NAV_UPPER_8822B(x) (((x) >> BIT_SHIFT_NAV_UPPER_8822B) & BIT_MASK_NAV_UPPER_8822B)
-
+#define BIT_NAV_UPPER_8822B(x) \
+ (((x) & BIT_MASK_NAV_UPPER_8822B) << BIT_SHIFT_NAV_UPPER_8822B)
+#define BITS_NAV_UPPER_8822B \
+ (BIT_MASK_NAV_UPPER_8822B << BIT_SHIFT_NAV_UPPER_8822B)
+#define BIT_CLEAR_NAV_UPPER_8822B(x) ((x) & (~BITS_NAV_UPPER_8822B))
+#define BIT_GET_NAV_UPPER_8822B(x) \
+ (((x) >> BIT_SHIFT_NAV_UPPER_8822B) & BIT_MASK_NAV_UPPER_8822B)
+#define BIT_SET_NAV_UPPER_8822B(x, v) \
+ (BIT_CLEAR_NAV_UPPER_8822B(x) | BIT_NAV_UPPER_8822B(v))
#define BIT_SHIFT_RXMYRTS_NAV_8822B 8
#define BIT_MASK_RXMYRTS_NAV_8822B 0xf
-#define BIT_RXMYRTS_NAV_8822B(x) (((x) & BIT_MASK_RXMYRTS_NAV_8822B) << BIT_SHIFT_RXMYRTS_NAV_8822B)
-#define BIT_GET_RXMYRTS_NAV_8822B(x) (((x) >> BIT_SHIFT_RXMYRTS_NAV_8822B) & BIT_MASK_RXMYRTS_NAV_8822B)
-
+#define BIT_RXMYRTS_NAV_8822B(x) \
+ (((x) & BIT_MASK_RXMYRTS_NAV_8822B) << BIT_SHIFT_RXMYRTS_NAV_8822B)
+#define BITS_RXMYRTS_NAV_8822B \
+ (BIT_MASK_RXMYRTS_NAV_8822B << BIT_SHIFT_RXMYRTS_NAV_8822B)
+#define BIT_CLEAR_RXMYRTS_NAV_8822B(x) ((x) & (~BITS_RXMYRTS_NAV_8822B))
+#define BIT_GET_RXMYRTS_NAV_8822B(x) \
+ (((x) >> BIT_SHIFT_RXMYRTS_NAV_8822B) & BIT_MASK_RXMYRTS_NAV_8822B)
+#define BIT_SET_RXMYRTS_NAV_8822B(x, v) \
+ (BIT_CLEAR_RXMYRTS_NAV_8822B(x) | BIT_RXMYRTS_NAV_8822B(v))
#define BIT_SHIFT_RTSRST_8822B 0
#define BIT_MASK_RTSRST_8822B 0xff
-#define BIT_RTSRST_8822B(x) (((x) & BIT_MASK_RTSRST_8822B) << BIT_SHIFT_RTSRST_8822B)
-#define BIT_GET_RTSRST_8822B(x) (((x) >> BIT_SHIFT_RTSRST_8822B) & BIT_MASK_RTSRST_8822B)
-
+#define BIT_RTSRST_8822B(x) \
+ (((x) & BIT_MASK_RTSRST_8822B) << BIT_SHIFT_RTSRST_8822B)
+#define BITS_RTSRST_8822B (BIT_MASK_RTSRST_8822B << BIT_SHIFT_RTSRST_8822B)
+#define BIT_CLEAR_RTSRST_8822B(x) ((x) & (~BITS_RTSRST_8822B))
+#define BIT_GET_RTSRST_8822B(x) \
+ (((x) >> BIT_SHIFT_RTSRST_8822B) & BIT_MASK_RTSRST_8822B)
+#define BIT_SET_RTSRST_8822B(x, v) \
+ (BIT_CLEAR_RTSRST_8822B(x) | BIT_RTSRST_8822B(v))
/* 2 REG_BACAMCMD_8822B (BLOCK ACK CAM COMMAND REGISTER) */
#define BIT_BACAM_POLL_8822B BIT(31)
@@ -7776,31 +13693,54 @@
#define BIT_SHIFT_TXSBM_8822B 14
#define BIT_MASK_TXSBM_8822B 0x3
-#define BIT_TXSBM_8822B(x) (((x) & BIT_MASK_TXSBM_8822B) << BIT_SHIFT_TXSBM_8822B)
-#define BIT_GET_TXSBM_8822B(x) (((x) >> BIT_SHIFT_TXSBM_8822B) & BIT_MASK_TXSBM_8822B)
-
+#define BIT_TXSBM_8822B(x) \
+ (((x) & BIT_MASK_TXSBM_8822B) << BIT_SHIFT_TXSBM_8822B)
+#define BITS_TXSBM_8822B (BIT_MASK_TXSBM_8822B << BIT_SHIFT_TXSBM_8822B)
+#define BIT_CLEAR_TXSBM_8822B(x) ((x) & (~BITS_TXSBM_8822B))
+#define BIT_GET_TXSBM_8822B(x) \
+ (((x) >> BIT_SHIFT_TXSBM_8822B) & BIT_MASK_TXSBM_8822B)
+#define BIT_SET_TXSBM_8822B(x, v) \
+ (BIT_CLEAR_TXSBM_8822B(x) | BIT_TXSBM_8822B(v))
#define BIT_SHIFT_BACAM_ADDR_8822B 0
#define BIT_MASK_BACAM_ADDR_8822B 0x3f
-#define BIT_BACAM_ADDR_8822B(x) (((x) & BIT_MASK_BACAM_ADDR_8822B) << BIT_SHIFT_BACAM_ADDR_8822B)
-#define BIT_GET_BACAM_ADDR_8822B(x) (((x) >> BIT_SHIFT_BACAM_ADDR_8822B) & BIT_MASK_BACAM_ADDR_8822B)
-
+#define BIT_BACAM_ADDR_8822B(x) \
+ (((x) & BIT_MASK_BACAM_ADDR_8822B) << BIT_SHIFT_BACAM_ADDR_8822B)
+#define BITS_BACAM_ADDR_8822B \
+ (BIT_MASK_BACAM_ADDR_8822B << BIT_SHIFT_BACAM_ADDR_8822B)
+#define BIT_CLEAR_BACAM_ADDR_8822B(x) ((x) & (~BITS_BACAM_ADDR_8822B))
+#define BIT_GET_BACAM_ADDR_8822B(x) \
+ (((x) >> BIT_SHIFT_BACAM_ADDR_8822B) & BIT_MASK_BACAM_ADDR_8822B)
+#define BIT_SET_BACAM_ADDR_8822B(x, v) \
+ (BIT_CLEAR_BACAM_ADDR_8822B(x) | BIT_BACAM_ADDR_8822B(v))
/* 2 REG_BACAMCONTENT_8822B (BLOCK ACK CAM CONTENT REGISTER) */
#define BIT_SHIFT_BA_CONTENT_H_8822B (32 & CPU_OPT_WIDTH)
#define BIT_MASK_BA_CONTENT_H_8822B 0xffffffffL
-#define BIT_BA_CONTENT_H_8822B(x) (((x) & BIT_MASK_BA_CONTENT_H_8822B) << BIT_SHIFT_BA_CONTENT_H_8822B)
-#define BIT_GET_BA_CONTENT_H_8822B(x) (((x) >> BIT_SHIFT_BA_CONTENT_H_8822B) & BIT_MASK_BA_CONTENT_H_8822B)
-
+#define BIT_BA_CONTENT_H_8822B(x) \
+ (((x) & BIT_MASK_BA_CONTENT_H_8822B) << BIT_SHIFT_BA_CONTENT_H_8822B)
+#define BITS_BA_CONTENT_H_8822B \
+ (BIT_MASK_BA_CONTENT_H_8822B << BIT_SHIFT_BA_CONTENT_H_8822B)
+#define BIT_CLEAR_BA_CONTENT_H_8822B(x) ((x) & (~BITS_BA_CONTENT_H_8822B))
+#define BIT_GET_BA_CONTENT_H_8822B(x) \
+ (((x) >> BIT_SHIFT_BA_CONTENT_H_8822B) & BIT_MASK_BA_CONTENT_H_8822B)
+#define BIT_SET_BA_CONTENT_H_8822B(x, v) \
+ (BIT_CLEAR_BA_CONTENT_H_8822B(x) | BIT_BA_CONTENT_H_8822B(v))
#define BIT_SHIFT_BA_CONTENT_L_8822B 0
#define BIT_MASK_BA_CONTENT_L_8822B 0xffffffffL
-#define BIT_BA_CONTENT_L_8822B(x) (((x) & BIT_MASK_BA_CONTENT_L_8822B) << BIT_SHIFT_BA_CONTENT_L_8822B)
-#define BIT_GET_BA_CONTENT_L_8822B(x) (((x) >> BIT_SHIFT_BA_CONTENT_L_8822B) & BIT_MASK_BA_CONTENT_L_8822B)
-
-
-/* 2 REG_NOT_VALID_8822B */
+#define BIT_BA_CONTENT_L_8822B(x) \
+ (((x) & BIT_MASK_BA_CONTENT_L_8822B) << BIT_SHIFT_BA_CONTENT_L_8822B)
+#define BITS_BA_CONTENT_L_8822B \
+ (BIT_MASK_BA_CONTENT_L_8822B << BIT_SHIFT_BA_CONTENT_L_8822B)
+#define BIT_CLEAR_BA_CONTENT_L_8822B(x) ((x) & (~BITS_BA_CONTENT_L_8822B))
+#define BIT_GET_BA_CONTENT_L_8822B(x) \
+ (((x) >> BIT_SHIFT_BA_CONTENT_L_8822B) & BIT_MASK_BA_CONTENT_L_8822B)
+#define BIT_SET_BA_CONTENT_L_8822B(x, v) \
+ (BIT_CLEAR_BA_CONTENT_L_8822B(x) | BIT_BA_CONTENT_L_8822B(v))
+
+/* 2 REG_WMAC_BITMAP_CTL_8822B */
#define BIT_BITMAP_VO_8822B BIT(7)
#define BIT_BITMAP_VI_8822B BIT(6)
#define BIT_BITMAP_BE_8822B BIT(5)
@@ -7808,8 +13748,18 @@
#define BIT_SHIFT_BITMAP_CONDITION_8822B 2
#define BIT_MASK_BITMAP_CONDITION_8822B 0x3
-#define BIT_BITMAP_CONDITION_8822B(x) (((x) & BIT_MASK_BITMAP_CONDITION_8822B) << BIT_SHIFT_BITMAP_CONDITION_8822B)
-#define BIT_GET_BITMAP_CONDITION_8822B(x) (((x) >> BIT_SHIFT_BITMAP_CONDITION_8822B) & BIT_MASK_BITMAP_CONDITION_8822B)
+#define BIT_BITMAP_CONDITION_8822B(x) \
+ (((x) & BIT_MASK_BITMAP_CONDITION_8822B) \
+ << BIT_SHIFT_BITMAP_CONDITION_8822B)
+#define BITS_BITMAP_CONDITION_8822B \
+ (BIT_MASK_BITMAP_CONDITION_8822B << BIT_SHIFT_BITMAP_CONDITION_8822B)
+#define BIT_CLEAR_BITMAP_CONDITION_8822B(x) \
+ ((x) & (~BITS_BITMAP_CONDITION_8822B))
+#define BIT_GET_BITMAP_CONDITION_8822B(x) \
+ (((x) >> BIT_SHIFT_BITMAP_CONDITION_8822B) & \
+ BIT_MASK_BITMAP_CONDITION_8822B)
+#define BIT_SET_BITMAP_CONDITION_8822B(x, v) \
+ (BIT_CLEAR_BITMAP_CONDITION_8822B(x) | BIT_BITMAP_CONDITION_8822B(v))
#define BIT_BITMAP_SSNBK_COUNTER_CLR_8822B BIT(1)
#define BIT_BITMAP_FORCE_8822B BIT(0)
@@ -7818,8 +13768,15 @@
#define BIT_SHIFT_RXPKT_TYPE_8822B 2
#define BIT_MASK_RXPKT_TYPE_8822B 0x3f
-#define BIT_RXPKT_TYPE_8822B(x) (((x) & BIT_MASK_RXPKT_TYPE_8822B) << BIT_SHIFT_RXPKT_TYPE_8822B)
-#define BIT_GET_RXPKT_TYPE_8822B(x) (((x) >> BIT_SHIFT_RXPKT_TYPE_8822B) & BIT_MASK_RXPKT_TYPE_8822B)
+#define BIT_RXPKT_TYPE_8822B(x) \
+ (((x) & BIT_MASK_RXPKT_TYPE_8822B) << BIT_SHIFT_RXPKT_TYPE_8822B)
+#define BITS_RXPKT_TYPE_8822B \
+ (BIT_MASK_RXPKT_TYPE_8822B << BIT_SHIFT_RXPKT_TYPE_8822B)
+#define BIT_CLEAR_RXPKT_TYPE_8822B(x) ((x) & (~BITS_RXPKT_TYPE_8822B))
+#define BIT_GET_RXPKT_TYPE_8822B(x) \
+ (((x) >> BIT_SHIFT_RXPKT_TYPE_8822B) & BIT_MASK_RXPKT_TYPE_8822B)
+#define BIT_SET_RXPKT_TYPE_8822B(x, v) \
+ (BIT_CLEAR_RXPKT_TYPE_8822B(x) | BIT_RXPKT_TYPE_8822B(v))
#define BIT_TXACT_IND_8822B BIT(1)
#define BIT_RXACT_IND_8822B BIT(0)
@@ -7828,8 +13785,20 @@
#define BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822B 2
#define BIT_MASK_BITMAP_SSNBK_COUNTER_8822B 0x3f
-#define BIT_BITMAP_SSNBK_COUNTER_8822B(x) (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8822B) << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822B)
-#define BIT_GET_BITMAP_SSNBK_COUNTER_8822B(x) (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822B) & BIT_MASK_BITMAP_SSNBK_COUNTER_8822B)
+#define BIT_BITMAP_SSNBK_COUNTER_8822B(x) \
+ (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8822B) \
+ << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822B)
+#define BITS_BITMAP_SSNBK_COUNTER_8822B \
+ (BIT_MASK_BITMAP_SSNBK_COUNTER_8822B \
+ << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822B)
+#define BIT_CLEAR_BITMAP_SSNBK_COUNTER_8822B(x) \
+ ((x) & (~BITS_BITMAP_SSNBK_COUNTER_8822B))
+#define BIT_GET_BITMAP_SSNBK_COUNTER_8822B(x) \
+ (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822B) & \
+ BIT_MASK_BITMAP_SSNBK_COUNTER_8822B)
+#define BIT_SET_BITMAP_SSNBK_COUNTER_8822B(x, v) \
+ (BIT_CLEAR_BITMAP_SSNBK_COUNTER_8822B(x) | \
+ BIT_BITMAP_SSNBK_COUNTER_8822B(v))
#define BIT_BITMAP_EN_8822B BIT(1)
#define BIT_WMAC_BACAM_RPMEN_8822B BIT(0)
@@ -7838,16 +13807,33 @@
#define BIT_SHIFT_LBDLY_8822B 0
#define BIT_MASK_LBDLY_8822B 0x1f
-#define BIT_LBDLY_8822B(x) (((x) & BIT_MASK_LBDLY_8822B) << BIT_SHIFT_LBDLY_8822B)
-#define BIT_GET_LBDLY_8822B(x) (((x) >> BIT_SHIFT_LBDLY_8822B) & BIT_MASK_LBDLY_8822B)
-
+#define BIT_LBDLY_8822B(x) \
+ (((x) & BIT_MASK_LBDLY_8822B) << BIT_SHIFT_LBDLY_8822B)
+#define BITS_LBDLY_8822B (BIT_MASK_LBDLY_8822B << BIT_SHIFT_LBDLY_8822B)
+#define BIT_CLEAR_LBDLY_8822B(x) ((x) & (~BITS_LBDLY_8822B))
+#define BIT_GET_LBDLY_8822B(x) \
+ (((x) >> BIT_SHIFT_LBDLY_8822B) & BIT_MASK_LBDLY_8822B)
+#define BIT_SET_LBDLY_8822B(x, v) \
+ (BIT_CLEAR_LBDLY_8822B(x) | BIT_LBDLY_8822B(v))
/* 2 REG_RXERR_RPT_8822B (RX ERROR REPORT REGISTER) */
#define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822B 28
#define BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822B 0xf
-#define BIT_RXERR_RPT_SEL_V1_3_0_8822B(x) (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822B) << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822B)
-#define BIT_GET_RXERR_RPT_SEL_V1_3_0_8822B(x) (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822B) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822B)
+#define BIT_RXERR_RPT_SEL_V1_3_0_8822B(x) \
+ (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822B) \
+ << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822B)
+#define BITS_RXERR_RPT_SEL_V1_3_0_8822B \
+ (BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822B \
+ << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822B)
+#define BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8822B(x) \
+ ((x) & (~BITS_RXERR_RPT_SEL_V1_3_0_8822B))
+#define BIT_GET_RXERR_RPT_SEL_V1_3_0_8822B(x) \
+ (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822B) & \
+ BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822B)
+#define BIT_SET_RXERR_RPT_SEL_V1_3_0_8822B(x, v) \
+ (BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8822B(x) | \
+ BIT_RXERR_RPT_SEL_V1_3_0_8822B(v))
#define BIT_RXERR_RPT_RST_8822B BIT(27)
#define BIT_RXERR_RPT_SEL_V1_4_8822B BIT(26)
@@ -7856,46 +13842,92 @@
#define BIT_SHIFT_UD_SUB_TYPE_8822B 18
#define BIT_MASK_UD_SUB_TYPE_8822B 0xf
-#define BIT_UD_SUB_TYPE_8822B(x) (((x) & BIT_MASK_UD_SUB_TYPE_8822B) << BIT_SHIFT_UD_SUB_TYPE_8822B)
-#define BIT_GET_UD_SUB_TYPE_8822B(x) (((x) >> BIT_SHIFT_UD_SUB_TYPE_8822B) & BIT_MASK_UD_SUB_TYPE_8822B)
-
+#define BIT_UD_SUB_TYPE_8822B(x) \
+ (((x) & BIT_MASK_UD_SUB_TYPE_8822B) << BIT_SHIFT_UD_SUB_TYPE_8822B)
+#define BITS_UD_SUB_TYPE_8822B \
+ (BIT_MASK_UD_SUB_TYPE_8822B << BIT_SHIFT_UD_SUB_TYPE_8822B)
+#define BIT_CLEAR_UD_SUB_TYPE_8822B(x) ((x) & (~BITS_UD_SUB_TYPE_8822B))
+#define BIT_GET_UD_SUB_TYPE_8822B(x) \
+ (((x) >> BIT_SHIFT_UD_SUB_TYPE_8822B) & BIT_MASK_UD_SUB_TYPE_8822B)
+#define BIT_SET_UD_SUB_TYPE_8822B(x, v) \
+ (BIT_CLEAR_UD_SUB_TYPE_8822B(x) | BIT_UD_SUB_TYPE_8822B(v))
#define BIT_SHIFT_UD_TYPE_8822B 16
#define BIT_MASK_UD_TYPE_8822B 0x3
-#define BIT_UD_TYPE_8822B(x) (((x) & BIT_MASK_UD_TYPE_8822B) << BIT_SHIFT_UD_TYPE_8822B)
-#define BIT_GET_UD_TYPE_8822B(x) (((x) >> BIT_SHIFT_UD_TYPE_8822B) & BIT_MASK_UD_TYPE_8822B)
-
+#define BIT_UD_TYPE_8822B(x) \
+ (((x) & BIT_MASK_UD_TYPE_8822B) << BIT_SHIFT_UD_TYPE_8822B)
+#define BITS_UD_TYPE_8822B (BIT_MASK_UD_TYPE_8822B << BIT_SHIFT_UD_TYPE_8822B)
+#define BIT_CLEAR_UD_TYPE_8822B(x) ((x) & (~BITS_UD_TYPE_8822B))
+#define BIT_GET_UD_TYPE_8822B(x) \
+ (((x) >> BIT_SHIFT_UD_TYPE_8822B) & BIT_MASK_UD_TYPE_8822B)
+#define BIT_SET_UD_TYPE_8822B(x, v) \
+ (BIT_CLEAR_UD_TYPE_8822B(x) | BIT_UD_TYPE_8822B(v))
#define BIT_SHIFT_RPT_COUNTER_8822B 0
#define BIT_MASK_RPT_COUNTER_8822B 0xffff
-#define BIT_RPT_COUNTER_8822B(x) (((x) & BIT_MASK_RPT_COUNTER_8822B) << BIT_SHIFT_RPT_COUNTER_8822B)
-#define BIT_GET_RPT_COUNTER_8822B(x) (((x) >> BIT_SHIFT_RPT_COUNTER_8822B) & BIT_MASK_RPT_COUNTER_8822B)
-
+#define BIT_RPT_COUNTER_8822B(x) \
+ (((x) & BIT_MASK_RPT_COUNTER_8822B) << BIT_SHIFT_RPT_COUNTER_8822B)
+#define BITS_RPT_COUNTER_8822B \
+ (BIT_MASK_RPT_COUNTER_8822B << BIT_SHIFT_RPT_COUNTER_8822B)
+#define BIT_CLEAR_RPT_COUNTER_8822B(x) ((x) & (~BITS_RPT_COUNTER_8822B))
+#define BIT_GET_RPT_COUNTER_8822B(x) \
+ (((x) >> BIT_SHIFT_RPT_COUNTER_8822B) & BIT_MASK_RPT_COUNTER_8822B)
+#define BIT_SET_RPT_COUNTER_8822B(x, v) \
+ (BIT_CLEAR_RPT_COUNTER_8822B(x) | BIT_RPT_COUNTER_8822B(v))
/* 2 REG_WMAC_TRXPTCL_CTL_8822B (WMAC TX/RX PROTOCOL CONTROL REGISTER) */
#define BIT_SHIFT_ACKBA_TYPSEL_8822B (60 & CPU_OPT_WIDTH)
#define BIT_MASK_ACKBA_TYPSEL_8822B 0xf
-#define BIT_ACKBA_TYPSEL_8822B(x) (((x) & BIT_MASK_ACKBA_TYPSEL_8822B) << BIT_SHIFT_ACKBA_TYPSEL_8822B)
-#define BIT_GET_ACKBA_TYPSEL_8822B(x) (((x) >> BIT_SHIFT_ACKBA_TYPSEL_8822B) & BIT_MASK_ACKBA_TYPSEL_8822B)
-
+#define BIT_ACKBA_TYPSEL_8822B(x) \
+ (((x) & BIT_MASK_ACKBA_TYPSEL_8822B) << BIT_SHIFT_ACKBA_TYPSEL_8822B)
+#define BITS_ACKBA_TYPSEL_8822B \
+ (BIT_MASK_ACKBA_TYPSEL_8822B << BIT_SHIFT_ACKBA_TYPSEL_8822B)
+#define BIT_CLEAR_ACKBA_TYPSEL_8822B(x) ((x) & (~BITS_ACKBA_TYPSEL_8822B))
+#define BIT_GET_ACKBA_TYPSEL_8822B(x) \
+ (((x) >> BIT_SHIFT_ACKBA_TYPSEL_8822B) & BIT_MASK_ACKBA_TYPSEL_8822B)
+#define BIT_SET_ACKBA_TYPSEL_8822B(x, v) \
+ (BIT_CLEAR_ACKBA_TYPSEL_8822B(x) | BIT_ACKBA_TYPSEL_8822B(v))
#define BIT_SHIFT_ACKBA_ACKPCHK_8822B (56 & CPU_OPT_WIDTH)
#define BIT_MASK_ACKBA_ACKPCHK_8822B 0xf
-#define BIT_ACKBA_ACKPCHK_8822B(x) (((x) & BIT_MASK_ACKBA_ACKPCHK_8822B) << BIT_SHIFT_ACKBA_ACKPCHK_8822B)
-#define BIT_GET_ACKBA_ACKPCHK_8822B(x) (((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8822B) & BIT_MASK_ACKBA_ACKPCHK_8822B)
-
+#define BIT_ACKBA_ACKPCHK_8822B(x) \
+ (((x) & BIT_MASK_ACKBA_ACKPCHK_8822B) << BIT_SHIFT_ACKBA_ACKPCHK_8822B)
+#define BITS_ACKBA_ACKPCHK_8822B \
+ (BIT_MASK_ACKBA_ACKPCHK_8822B << BIT_SHIFT_ACKBA_ACKPCHK_8822B)
+#define BIT_CLEAR_ACKBA_ACKPCHK_8822B(x) ((x) & (~BITS_ACKBA_ACKPCHK_8822B))
+#define BIT_GET_ACKBA_ACKPCHK_8822B(x) \
+ (((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8822B) & BIT_MASK_ACKBA_ACKPCHK_8822B)
+#define BIT_SET_ACKBA_ACKPCHK_8822B(x, v) \
+ (BIT_CLEAR_ACKBA_ACKPCHK_8822B(x) | BIT_ACKBA_ACKPCHK_8822B(v))
#define BIT_SHIFT_ACKBAR_TYPESEL_8822B (48 & CPU_OPT_WIDTH)
#define BIT_MASK_ACKBAR_TYPESEL_8822B 0xff
-#define BIT_ACKBAR_TYPESEL_8822B(x) (((x) & BIT_MASK_ACKBAR_TYPESEL_8822B) << BIT_SHIFT_ACKBAR_TYPESEL_8822B)
-#define BIT_GET_ACKBAR_TYPESEL_8822B(x) (((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8822B) & BIT_MASK_ACKBAR_TYPESEL_8822B)
-
+#define BIT_ACKBAR_TYPESEL_8822B(x) \
+ (((x) & BIT_MASK_ACKBAR_TYPESEL_8822B) \
+ << BIT_SHIFT_ACKBAR_TYPESEL_8822B)
+#define BITS_ACKBAR_TYPESEL_8822B \
+ (BIT_MASK_ACKBAR_TYPESEL_8822B << BIT_SHIFT_ACKBAR_TYPESEL_8822B)
+#define BIT_CLEAR_ACKBAR_TYPESEL_8822B(x) ((x) & (~BITS_ACKBAR_TYPESEL_8822B))
+#define BIT_GET_ACKBAR_TYPESEL_8822B(x) \
+ (((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8822B) & \
+ BIT_MASK_ACKBAR_TYPESEL_8822B)
+#define BIT_SET_ACKBAR_TYPESEL_8822B(x, v) \
+ (BIT_CLEAR_ACKBAR_TYPESEL_8822B(x) | BIT_ACKBAR_TYPESEL_8822B(v))
#define BIT_SHIFT_ACKBAR_ACKPCHK_8822B (44 & CPU_OPT_WIDTH)
#define BIT_MASK_ACKBAR_ACKPCHK_8822B 0xf
-#define BIT_ACKBAR_ACKPCHK_8822B(x) (((x) & BIT_MASK_ACKBAR_ACKPCHK_8822B) << BIT_SHIFT_ACKBAR_ACKPCHK_8822B)
-#define BIT_GET_ACKBAR_ACKPCHK_8822B(x) (((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8822B) & BIT_MASK_ACKBAR_ACKPCHK_8822B)
+#define BIT_ACKBAR_ACKPCHK_8822B(x) \
+ (((x) & BIT_MASK_ACKBAR_ACKPCHK_8822B) \
+ << BIT_SHIFT_ACKBAR_ACKPCHK_8822B)
+#define BITS_ACKBAR_ACKPCHK_8822B \
+ (BIT_MASK_ACKBAR_ACKPCHK_8822B << BIT_SHIFT_ACKBAR_ACKPCHK_8822B)
+#define BIT_CLEAR_ACKBAR_ACKPCHK_8822B(x) ((x) & (~BITS_ACKBAR_ACKPCHK_8822B))
+#define BIT_GET_ACKBAR_ACKPCHK_8822B(x) \
+ (((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8822B) & \
+ BIT_MASK_ACKBAR_ACKPCHK_8822B)
+#define BIT_SET_ACKBAR_ACKPCHK_8822B(x, v) \
+ (BIT_CLEAR_ACKBAR_ACKPCHK_8822B(x) | BIT_ACKBAR_ACKPCHK_8822B(v))
#define BIT_RXBA_IGNOREA2_8822B BIT(42)
#define BIT_EN_SAVE_ALL_TXOPADDR_8822B BIT(41)
@@ -7919,8 +13951,15 @@
#define BIT_SHIFT_RESP_CHNBUSY_8822B 20
#define BIT_MASK_RESP_CHNBUSY_8822B 0x3
-#define BIT_RESP_CHNBUSY_8822B(x) (((x) & BIT_MASK_RESP_CHNBUSY_8822B) << BIT_SHIFT_RESP_CHNBUSY_8822B)
-#define BIT_GET_RESP_CHNBUSY_8822B(x) (((x) >> BIT_SHIFT_RESP_CHNBUSY_8822B) & BIT_MASK_RESP_CHNBUSY_8822B)
+#define BIT_RESP_CHNBUSY_8822B(x) \
+ (((x) & BIT_MASK_RESP_CHNBUSY_8822B) << BIT_SHIFT_RESP_CHNBUSY_8822B)
+#define BITS_RESP_CHNBUSY_8822B \
+ (BIT_MASK_RESP_CHNBUSY_8822B << BIT_SHIFT_RESP_CHNBUSY_8822B)
+#define BIT_CLEAR_RESP_CHNBUSY_8822B(x) ((x) & (~BITS_RESP_CHNBUSY_8822B))
+#define BIT_GET_RESP_CHNBUSY_8822B(x) \
+ (((x) >> BIT_SHIFT_RESP_CHNBUSY_8822B) & BIT_MASK_RESP_CHNBUSY_8822B)
+#define BIT_SET_RESP_CHNBUSY_8822B(x, v) \
+ (BIT_CLEAR_RESP_CHNBUSY_8822B(x) | BIT_RESP_CHNBUSY_8822B(v))
#define BIT_RESP_DCTS_EN_8822B BIT(19)
#define BIT_RESP_DCFE_EN_8822B BIT(18)
@@ -7932,29 +13971,63 @@
#define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822B 10
#define BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822B 0x7
-#define BIT_R_WMAC_SECOND_CCA_TIMER_8822B(x) (((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822B) << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822B)
-#define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822B) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822B)
-
+#define BIT_R_WMAC_SECOND_CCA_TIMER_8822B(x) \
+ (((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822B) \
+ << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822B)
+#define BITS_R_WMAC_SECOND_CCA_TIMER_8822B \
+ (BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822B \
+ << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822B)
+#define BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8822B(x) \
+ ((x) & (~BITS_R_WMAC_SECOND_CCA_TIMER_8822B))
+#define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8822B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822B) & \
+ BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822B)
+#define BIT_SET_R_WMAC_SECOND_CCA_TIMER_8822B(x, v) \
+ (BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8822B(x) | \
+ BIT_R_WMAC_SECOND_CCA_TIMER_8822B(v))
#define BIT_SHIFT_RFMOD_8822B 7
#define BIT_MASK_RFMOD_8822B 0x3
-#define BIT_RFMOD_8822B(x) (((x) & BIT_MASK_RFMOD_8822B) << BIT_SHIFT_RFMOD_8822B)
-#define BIT_GET_RFMOD_8822B(x) (((x) >> BIT_SHIFT_RFMOD_8822B) & BIT_MASK_RFMOD_8822B)
-
+#define BIT_RFMOD_8822B(x) \
+ (((x) & BIT_MASK_RFMOD_8822B) << BIT_SHIFT_RFMOD_8822B)
+#define BITS_RFMOD_8822B (BIT_MASK_RFMOD_8822B << BIT_SHIFT_RFMOD_8822B)
+#define BIT_CLEAR_RFMOD_8822B(x) ((x) & (~BITS_RFMOD_8822B))
+#define BIT_GET_RFMOD_8822B(x) \
+ (((x) >> BIT_SHIFT_RFMOD_8822B) & BIT_MASK_RFMOD_8822B)
+#define BIT_SET_RFMOD_8822B(x, v) \
+ (BIT_CLEAR_RFMOD_8822B(x) | BIT_RFMOD_8822B(v))
#define BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822B 5
#define BIT_MASK_RESP_CTS_DYNBW_SEL_8822B 0x3
-#define BIT_RESP_CTS_DYNBW_SEL_8822B(x) (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8822B) << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822B)
-#define BIT_GET_RESP_CTS_DYNBW_SEL_8822B(x) (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822B) & BIT_MASK_RESP_CTS_DYNBW_SEL_8822B)
+#define BIT_RESP_CTS_DYNBW_SEL_8822B(x) \
+ (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8822B) \
+ << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822B)
+#define BITS_RESP_CTS_DYNBW_SEL_8822B \
+ (BIT_MASK_RESP_CTS_DYNBW_SEL_8822B \
+ << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822B)
+#define BIT_CLEAR_RESP_CTS_DYNBW_SEL_8822B(x) \
+ ((x) & (~BITS_RESP_CTS_DYNBW_SEL_8822B))
+#define BIT_GET_RESP_CTS_DYNBW_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822B) & \
+ BIT_MASK_RESP_CTS_DYNBW_SEL_8822B)
+#define BIT_SET_RESP_CTS_DYNBW_SEL_8822B(x, v) \
+ (BIT_CLEAR_RESP_CTS_DYNBW_SEL_8822B(x) | \
+ BIT_RESP_CTS_DYNBW_SEL_8822B(v))
#define BIT_DLY_TX_WAIT_RXANTSEL_8822B BIT(4)
#define BIT_TXRESP_BY_RXANTSEL_8822B BIT(3)
#define BIT_SHIFT_ORIG_DCTS_CHK_8822B 0
#define BIT_MASK_ORIG_DCTS_CHK_8822B 0x3
-#define BIT_ORIG_DCTS_CHK_8822B(x) (((x) & BIT_MASK_ORIG_DCTS_CHK_8822B) << BIT_SHIFT_ORIG_DCTS_CHK_8822B)
-#define BIT_GET_ORIG_DCTS_CHK_8822B(x) (((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8822B) & BIT_MASK_ORIG_DCTS_CHK_8822B)
-
+#define BIT_ORIG_DCTS_CHK_8822B(x) \
+ (((x) & BIT_MASK_ORIG_DCTS_CHK_8822B) << BIT_SHIFT_ORIG_DCTS_CHK_8822B)
+#define BITS_ORIG_DCTS_CHK_8822B \
+ (BIT_MASK_ORIG_DCTS_CHK_8822B << BIT_SHIFT_ORIG_DCTS_CHK_8822B)
+#define BIT_CLEAR_ORIG_DCTS_CHK_8822B(x) ((x) & (~BITS_ORIG_DCTS_CHK_8822B))
+#define BIT_GET_ORIG_DCTS_CHK_8822B(x) \
+ (((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8822B) & BIT_MASK_ORIG_DCTS_CHK_8822B)
+#define BIT_SET_ORIG_DCTS_CHK_8822B(x, v) \
+ (BIT_CLEAR_ORIG_DCTS_CHK_8822B(x) | BIT_ORIG_DCTS_CHK_8822B(v))
/* 2 REG_CAMCMD_8822B (CAM COMMAND REGISTER) */
#define BIT_SECCAM_POLLING_8822B BIT(31)
@@ -7964,25 +14037,45 @@
#define BIT_SHIFT_SECCAM_ADDR_V2_8822B 0
#define BIT_MASK_SECCAM_ADDR_V2_8822B 0x3ff
-#define BIT_SECCAM_ADDR_V2_8822B(x) (((x) & BIT_MASK_SECCAM_ADDR_V2_8822B) << BIT_SHIFT_SECCAM_ADDR_V2_8822B)
-#define BIT_GET_SECCAM_ADDR_V2_8822B(x) (((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8822B) & BIT_MASK_SECCAM_ADDR_V2_8822B)
-
+#define BIT_SECCAM_ADDR_V2_8822B(x) \
+ (((x) & BIT_MASK_SECCAM_ADDR_V2_8822B) \
+ << BIT_SHIFT_SECCAM_ADDR_V2_8822B)
+#define BITS_SECCAM_ADDR_V2_8822B \
+ (BIT_MASK_SECCAM_ADDR_V2_8822B << BIT_SHIFT_SECCAM_ADDR_V2_8822B)
+#define BIT_CLEAR_SECCAM_ADDR_V2_8822B(x) ((x) & (~BITS_SECCAM_ADDR_V2_8822B))
+#define BIT_GET_SECCAM_ADDR_V2_8822B(x) \
+ (((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8822B) & \
+ BIT_MASK_SECCAM_ADDR_V2_8822B)
+#define BIT_SET_SECCAM_ADDR_V2_8822B(x, v) \
+ (BIT_CLEAR_SECCAM_ADDR_V2_8822B(x) | BIT_SECCAM_ADDR_V2_8822B(v))
/* 2 REG_CAMWRITE_8822B (CAM WRITE REGISTER) */
#define BIT_SHIFT_CAMW_DATA_8822B 0
#define BIT_MASK_CAMW_DATA_8822B 0xffffffffL
-#define BIT_CAMW_DATA_8822B(x) (((x) & BIT_MASK_CAMW_DATA_8822B) << BIT_SHIFT_CAMW_DATA_8822B)
-#define BIT_GET_CAMW_DATA_8822B(x) (((x) >> BIT_SHIFT_CAMW_DATA_8822B) & BIT_MASK_CAMW_DATA_8822B)
-
+#define BIT_CAMW_DATA_8822B(x) \
+ (((x) & BIT_MASK_CAMW_DATA_8822B) << BIT_SHIFT_CAMW_DATA_8822B)
+#define BITS_CAMW_DATA_8822B \
+ (BIT_MASK_CAMW_DATA_8822B << BIT_SHIFT_CAMW_DATA_8822B)
+#define BIT_CLEAR_CAMW_DATA_8822B(x) ((x) & (~BITS_CAMW_DATA_8822B))
+#define BIT_GET_CAMW_DATA_8822B(x) \
+ (((x) >> BIT_SHIFT_CAMW_DATA_8822B) & BIT_MASK_CAMW_DATA_8822B)
+#define BIT_SET_CAMW_DATA_8822B(x, v) \
+ (BIT_CLEAR_CAMW_DATA_8822B(x) | BIT_CAMW_DATA_8822B(v))
/* 2 REG_CAMREAD_8822B (CAM READ REGISTER) */
#define BIT_SHIFT_CAMR_DATA_8822B 0
#define BIT_MASK_CAMR_DATA_8822B 0xffffffffL
-#define BIT_CAMR_DATA_8822B(x) (((x) & BIT_MASK_CAMR_DATA_8822B) << BIT_SHIFT_CAMR_DATA_8822B)
-#define BIT_GET_CAMR_DATA_8822B(x) (((x) >> BIT_SHIFT_CAMR_DATA_8822B) & BIT_MASK_CAMR_DATA_8822B)
-
+#define BIT_CAMR_DATA_8822B(x) \
+ (((x) & BIT_MASK_CAMR_DATA_8822B) << BIT_SHIFT_CAMR_DATA_8822B)
+#define BITS_CAMR_DATA_8822B \
+ (BIT_MASK_CAMR_DATA_8822B << BIT_SHIFT_CAMR_DATA_8822B)
+#define BIT_CLEAR_CAMR_DATA_8822B(x) ((x) & (~BITS_CAMR_DATA_8822B))
+#define BIT_GET_CAMR_DATA_8822B(x) \
+ (((x) >> BIT_SHIFT_CAMR_DATA_8822B) & BIT_MASK_CAMR_DATA_8822B)
+#define BIT_SET_CAMR_DATA_8822B(x, v) \
+ (BIT_CLEAR_CAMR_DATA_8822B(x) | BIT_CAMR_DATA_8822B(v))
/* 2 REG_CAMDBG_8822B (CAM DEBUG REGISTER) */
#define BIT_SECCAM_INFO_8822B BIT(31)
@@ -7990,38 +14083,89 @@
#define BIT_SHIFT_CAMDBG_SEC_TYPE_8822B 12
#define BIT_MASK_CAMDBG_SEC_TYPE_8822B 0x7
-#define BIT_CAMDBG_SEC_TYPE_8822B(x) (((x) & BIT_MASK_CAMDBG_SEC_TYPE_8822B) << BIT_SHIFT_CAMDBG_SEC_TYPE_8822B)
-#define BIT_GET_CAMDBG_SEC_TYPE_8822B(x) (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8822B) & BIT_MASK_CAMDBG_SEC_TYPE_8822B)
+#define BIT_CAMDBG_SEC_TYPE_8822B(x) \
+ (((x) & BIT_MASK_CAMDBG_SEC_TYPE_8822B) \
+ << BIT_SHIFT_CAMDBG_SEC_TYPE_8822B)
+#define BITS_CAMDBG_SEC_TYPE_8822B \
+ (BIT_MASK_CAMDBG_SEC_TYPE_8822B << BIT_SHIFT_CAMDBG_SEC_TYPE_8822B)
+#define BIT_CLEAR_CAMDBG_SEC_TYPE_8822B(x) ((x) & (~BITS_CAMDBG_SEC_TYPE_8822B))
+#define BIT_GET_CAMDBG_SEC_TYPE_8822B(x) \
+ (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8822B) & \
+ BIT_MASK_CAMDBG_SEC_TYPE_8822B)
+#define BIT_SET_CAMDBG_SEC_TYPE_8822B(x, v) \
+ (BIT_CLEAR_CAMDBG_SEC_TYPE_8822B(x) | BIT_CAMDBG_SEC_TYPE_8822B(v))
#define BIT_CAMDBG_EXT_SECTYPE_8822B BIT(11)
#define BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822B 5
#define BIT_MASK_CAMDBG_MIC_KEY_IDX_8822B 0x1f
-#define BIT_CAMDBG_MIC_KEY_IDX_8822B(x) (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8822B) << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822B)
-#define BIT_GET_CAMDBG_MIC_KEY_IDX_8822B(x) (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822B) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8822B)
-
+#define BIT_CAMDBG_MIC_KEY_IDX_8822B(x) \
+ (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8822B) \
+ << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822B)
+#define BITS_CAMDBG_MIC_KEY_IDX_8822B \
+ (BIT_MASK_CAMDBG_MIC_KEY_IDX_8822B \
+ << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822B)
+#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8822B(x) \
+ ((x) & (~BITS_CAMDBG_MIC_KEY_IDX_8822B))
+#define BIT_GET_CAMDBG_MIC_KEY_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822B) & \
+ BIT_MASK_CAMDBG_MIC_KEY_IDX_8822B)
+#define BIT_SET_CAMDBG_MIC_KEY_IDX_8822B(x, v) \
+ (BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8822B(x) | \
+ BIT_CAMDBG_MIC_KEY_IDX_8822B(v))
#define BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822B 0
#define BIT_MASK_CAMDBG_SEC_KEY_IDX_8822B 0x1f
-#define BIT_CAMDBG_SEC_KEY_IDX_8822B(x) (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8822B) << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822B)
-#define BIT_GET_CAMDBG_SEC_KEY_IDX_8822B(x) (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822B) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8822B)
-
+#define BIT_CAMDBG_SEC_KEY_IDX_8822B(x) \
+ (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8822B) \
+ << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822B)
+#define BITS_CAMDBG_SEC_KEY_IDX_8822B \
+ (BIT_MASK_CAMDBG_SEC_KEY_IDX_8822B \
+ << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822B)
+#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8822B(x) \
+ ((x) & (~BITS_CAMDBG_SEC_KEY_IDX_8822B))
+#define BIT_GET_CAMDBG_SEC_KEY_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822B) & \
+ BIT_MASK_CAMDBG_SEC_KEY_IDX_8822B)
+#define BIT_SET_CAMDBG_SEC_KEY_IDX_8822B(x, v) \
+ (BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8822B(x) | \
+ BIT_CAMDBG_SEC_KEY_IDX_8822B(v))
/* 2 REG_RXFILTER_ACTION_1_8822B */
#define BIT_SHIFT_RXFILTER_ACTION_1_8822B 0
#define BIT_MASK_RXFILTER_ACTION_1_8822B 0xff
-#define BIT_RXFILTER_ACTION_1_8822B(x) (((x) & BIT_MASK_RXFILTER_ACTION_1_8822B) << BIT_SHIFT_RXFILTER_ACTION_1_8822B)
-#define BIT_GET_RXFILTER_ACTION_1_8822B(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8822B) & BIT_MASK_RXFILTER_ACTION_1_8822B)
-
+#define BIT_RXFILTER_ACTION_1_8822B(x) \
+ (((x) & BIT_MASK_RXFILTER_ACTION_1_8822B) \
+ << BIT_SHIFT_RXFILTER_ACTION_1_8822B)
+#define BITS_RXFILTER_ACTION_1_8822B \
+ (BIT_MASK_RXFILTER_ACTION_1_8822B << BIT_SHIFT_RXFILTER_ACTION_1_8822B)
+#define BIT_CLEAR_RXFILTER_ACTION_1_8822B(x) \
+ ((x) & (~BITS_RXFILTER_ACTION_1_8822B))
+#define BIT_GET_RXFILTER_ACTION_1_8822B(x) \
+ (((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8822B) & \
+ BIT_MASK_RXFILTER_ACTION_1_8822B)
+#define BIT_SET_RXFILTER_ACTION_1_8822B(x, v) \
+ (BIT_CLEAR_RXFILTER_ACTION_1_8822B(x) | BIT_RXFILTER_ACTION_1_8822B(v))
/* 2 REG_RXFILTER_CATEGORY_1_8822B */
#define BIT_SHIFT_RXFILTER_CATEGORY_1_8822B 0
#define BIT_MASK_RXFILTER_CATEGORY_1_8822B 0xff
-#define BIT_RXFILTER_CATEGORY_1_8822B(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_1_8822B) << BIT_SHIFT_RXFILTER_CATEGORY_1_8822B)
-#define BIT_GET_RXFILTER_CATEGORY_1_8822B(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8822B) & BIT_MASK_RXFILTER_CATEGORY_1_8822B)
-
+#define BIT_RXFILTER_CATEGORY_1_8822B(x) \
+ (((x) & BIT_MASK_RXFILTER_CATEGORY_1_8822B) \
+ << BIT_SHIFT_RXFILTER_CATEGORY_1_8822B)
+#define BITS_RXFILTER_CATEGORY_1_8822B \
+ (BIT_MASK_RXFILTER_CATEGORY_1_8822B \
+ << BIT_SHIFT_RXFILTER_CATEGORY_1_8822B)
+#define BIT_CLEAR_RXFILTER_CATEGORY_1_8822B(x) \
+ ((x) & (~BITS_RXFILTER_CATEGORY_1_8822B))
+#define BIT_GET_RXFILTER_CATEGORY_1_8822B(x) \
+ (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8822B) & \
+ BIT_MASK_RXFILTER_CATEGORY_1_8822B)
+#define BIT_SET_RXFILTER_CATEGORY_1_8822B(x, v) \
+ (BIT_CLEAR_RXFILTER_CATEGORY_1_8822B(x) | \
+ BIT_RXFILTER_CATEGORY_1_8822B(v))
/* 2 REG_SECCFG_8822B (SECURITY CONFIGURATION REGISTER) */
#define BIT_DIS_GCLK_WAPI_8822B BIT(15)
@@ -8044,33 +14188,73 @@
#define BIT_SHIFT_RXFILTER_ACTION_3_8822B 0
#define BIT_MASK_RXFILTER_ACTION_3_8822B 0xff
-#define BIT_RXFILTER_ACTION_3_8822B(x) (((x) & BIT_MASK_RXFILTER_ACTION_3_8822B) << BIT_SHIFT_RXFILTER_ACTION_3_8822B)
-#define BIT_GET_RXFILTER_ACTION_3_8822B(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8822B) & BIT_MASK_RXFILTER_ACTION_3_8822B)
-
+#define BIT_RXFILTER_ACTION_3_8822B(x) \
+ (((x) & BIT_MASK_RXFILTER_ACTION_3_8822B) \
+ << BIT_SHIFT_RXFILTER_ACTION_3_8822B)
+#define BITS_RXFILTER_ACTION_3_8822B \
+ (BIT_MASK_RXFILTER_ACTION_3_8822B << BIT_SHIFT_RXFILTER_ACTION_3_8822B)
+#define BIT_CLEAR_RXFILTER_ACTION_3_8822B(x) \
+ ((x) & (~BITS_RXFILTER_ACTION_3_8822B))
+#define BIT_GET_RXFILTER_ACTION_3_8822B(x) \
+ (((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8822B) & \
+ BIT_MASK_RXFILTER_ACTION_3_8822B)
+#define BIT_SET_RXFILTER_ACTION_3_8822B(x, v) \
+ (BIT_CLEAR_RXFILTER_ACTION_3_8822B(x) | BIT_RXFILTER_ACTION_3_8822B(v))
/* 2 REG_RXFILTER_CATEGORY_3_8822B */
#define BIT_SHIFT_RXFILTER_CATEGORY_3_8822B 0
#define BIT_MASK_RXFILTER_CATEGORY_3_8822B 0xff
-#define BIT_RXFILTER_CATEGORY_3_8822B(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_3_8822B) << BIT_SHIFT_RXFILTER_CATEGORY_3_8822B)
-#define BIT_GET_RXFILTER_CATEGORY_3_8822B(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8822B) & BIT_MASK_RXFILTER_CATEGORY_3_8822B)
-
+#define BIT_RXFILTER_CATEGORY_3_8822B(x) \
+ (((x) & BIT_MASK_RXFILTER_CATEGORY_3_8822B) \
+ << BIT_SHIFT_RXFILTER_CATEGORY_3_8822B)
+#define BITS_RXFILTER_CATEGORY_3_8822B \
+ (BIT_MASK_RXFILTER_CATEGORY_3_8822B \
+ << BIT_SHIFT_RXFILTER_CATEGORY_3_8822B)
+#define BIT_CLEAR_RXFILTER_CATEGORY_3_8822B(x) \
+ ((x) & (~BITS_RXFILTER_CATEGORY_3_8822B))
+#define BIT_GET_RXFILTER_CATEGORY_3_8822B(x) \
+ (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8822B) & \
+ BIT_MASK_RXFILTER_CATEGORY_3_8822B)
+#define BIT_SET_RXFILTER_CATEGORY_3_8822B(x, v) \
+ (BIT_CLEAR_RXFILTER_CATEGORY_3_8822B(x) | \
+ BIT_RXFILTER_CATEGORY_3_8822B(v))
/* 2 REG_RXFILTER_ACTION_2_8822B */
#define BIT_SHIFT_RXFILTER_ACTION_2_8822B 0
#define BIT_MASK_RXFILTER_ACTION_2_8822B 0xff
-#define BIT_RXFILTER_ACTION_2_8822B(x) (((x) & BIT_MASK_RXFILTER_ACTION_2_8822B) << BIT_SHIFT_RXFILTER_ACTION_2_8822B)
-#define BIT_GET_RXFILTER_ACTION_2_8822B(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8822B) & BIT_MASK_RXFILTER_ACTION_2_8822B)
-
+#define BIT_RXFILTER_ACTION_2_8822B(x) \
+ (((x) & BIT_MASK_RXFILTER_ACTION_2_8822B) \
+ << BIT_SHIFT_RXFILTER_ACTION_2_8822B)
+#define BITS_RXFILTER_ACTION_2_8822B \
+ (BIT_MASK_RXFILTER_ACTION_2_8822B << BIT_SHIFT_RXFILTER_ACTION_2_8822B)
+#define BIT_CLEAR_RXFILTER_ACTION_2_8822B(x) \
+ ((x) & (~BITS_RXFILTER_ACTION_2_8822B))
+#define BIT_GET_RXFILTER_ACTION_2_8822B(x) \
+ (((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8822B) & \
+ BIT_MASK_RXFILTER_ACTION_2_8822B)
+#define BIT_SET_RXFILTER_ACTION_2_8822B(x, v) \
+ (BIT_CLEAR_RXFILTER_ACTION_2_8822B(x) | BIT_RXFILTER_ACTION_2_8822B(v))
/* 2 REG_RXFILTER_CATEGORY_2_8822B */
#define BIT_SHIFT_RXFILTER_CATEGORY_2_8822B 0
#define BIT_MASK_RXFILTER_CATEGORY_2_8822B 0xff
-#define BIT_RXFILTER_CATEGORY_2_8822B(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_2_8822B) << BIT_SHIFT_RXFILTER_CATEGORY_2_8822B)
-#define BIT_GET_RXFILTER_CATEGORY_2_8822B(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8822B) & BIT_MASK_RXFILTER_CATEGORY_2_8822B)
-
+#define BIT_RXFILTER_CATEGORY_2_8822B(x) \
+ (((x) & BIT_MASK_RXFILTER_CATEGORY_2_8822B) \
+ << BIT_SHIFT_RXFILTER_CATEGORY_2_8822B)
+#define BITS_RXFILTER_CATEGORY_2_8822B \
+ (BIT_MASK_RXFILTER_CATEGORY_2_8822B \
+ << BIT_SHIFT_RXFILTER_CATEGORY_2_8822B)
+#define BIT_CLEAR_RXFILTER_CATEGORY_2_8822B(x) \
+ ((x) & (~BITS_RXFILTER_CATEGORY_2_8822B))
+#define BIT_GET_RXFILTER_CATEGORY_2_8822B(x) \
+ (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8822B) & \
+ BIT_MASK_RXFILTER_CATEGORY_2_8822B)
+#define BIT_SET_RXFILTER_CATEGORY_2_8822B(x, v) \
+ (BIT_CLEAR_RXFILTER_CATEGORY_2_8822B(x) | \
+ BIT_RXFILTER_CATEGORY_2_8822B(v))
/* 2 REG_RXFLTMAP4_8822B (RX FILTER MAP GROUP 4) */
#define BIT_CTRLFLT15EN_FW_8822B BIT(15)
@@ -8108,7 +14292,7 @@
#define BIT_MGTFLT1EN_FW_8822B BIT(1)
#define BIT_MGTFLT0EN_FW_8822B BIT(0)
-/* 2 REG_RXFLTMAP6_8822B (RX FILTER MAP GROUP 3) */
+/* 2 REG_RXFLTMAP6_8822B (RX FILTER MAP GROUP 6) */
#define BIT_ACTIONFLT15EN_FW_8822B BIT(15)
#define BIT_ACTIONFLT14EN_FW_8822B BIT(14)
#define BIT_ACTIONFLT13EN_FW_8822B BIT(13)
@@ -8126,7 +14310,7 @@
#define BIT_ACTIONFLT1EN_FW_8822B BIT(1)
#define BIT_ACTIONFLT0EN_FW_8822B BIT(0)
-/* 2 REG_RXFLTMAP5_8822B (RX FILTER MAP GROUP 3) */
+/* 2 REG_RXFLTMAP5_8822B (RX FILTER MAP GROUP 5) */
#define BIT_DATAFLT15EN_FW_8822B BIT(15)
#define BIT_DATAFLT14EN_FW_8822B BIT(14)
#define BIT_DATAFLT13EN_FW_8822B BIT(13)
@@ -8158,8 +14342,20 @@
#define BIT_SHIFT_PORTSEL__PS_RX_INFO_8822B 5
#define BIT_MASK_PORTSEL__PS_RX_INFO_8822B 0x7
-#define BIT_PORTSEL__PS_RX_INFO_8822B(x) (((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8822B) << BIT_SHIFT_PORTSEL__PS_RX_INFO_8822B)
-#define BIT_GET_PORTSEL__PS_RX_INFO_8822B(x) (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8822B) & BIT_MASK_PORTSEL__PS_RX_INFO_8822B)
+#define BIT_PORTSEL__PS_RX_INFO_8822B(x) \
+ (((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8822B) \
+ << BIT_SHIFT_PORTSEL__PS_RX_INFO_8822B)
+#define BITS_PORTSEL__PS_RX_INFO_8822B \
+ (BIT_MASK_PORTSEL__PS_RX_INFO_8822B \
+ << BIT_SHIFT_PORTSEL__PS_RX_INFO_8822B)
+#define BIT_CLEAR_PORTSEL__PS_RX_INFO_8822B(x) \
+ ((x) & (~BITS_PORTSEL__PS_RX_INFO_8822B))
+#define BIT_GET_PORTSEL__PS_RX_INFO_8822B(x) \
+ (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8822B) & \
+ BIT_MASK_PORTSEL__PS_RX_INFO_8822B)
+#define BIT_SET_PORTSEL__PS_RX_INFO_8822B(x, v) \
+ (BIT_CLEAR_PORTSEL__PS_RX_INFO_8822B(x) | \
+ BIT_PORTSEL__PS_RX_INFO_8822B(v))
#define BIT_RXCTRLIN0_8822B BIT(4)
#define BIT_RXMGTIN0_8822B BIT(3)
@@ -8176,8 +14372,18 @@
#define BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822B 6
#define BIT_MASK_PSF_BSSIDSEL_B2B1_8822B 0x3
-#define BIT_PSF_BSSIDSEL_B2B1_8822B(x) (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8822B) << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822B)
-#define BIT_GET_PSF_BSSIDSEL_B2B1_8822B(x) (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822B) & BIT_MASK_PSF_BSSIDSEL_B2B1_8822B)
+#define BIT_PSF_BSSIDSEL_B2B1_8822B(x) \
+ (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8822B) \
+ << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822B)
+#define BITS_PSF_BSSIDSEL_B2B1_8822B \
+ (BIT_MASK_PSF_BSSIDSEL_B2B1_8822B << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822B)
+#define BIT_CLEAR_PSF_BSSIDSEL_B2B1_8822B(x) \
+ ((x) & (~BITS_PSF_BSSIDSEL_B2B1_8822B))
+#define BIT_GET_PSF_BSSIDSEL_B2B1_8822B(x) \
+ (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822B) & \
+ BIT_MASK_PSF_BSSIDSEL_B2B1_8822B)
+#define BIT_SET_PSF_BSSIDSEL_B2B1_8822B(x, v) \
+ (BIT_CLEAR_PSF_BSSIDSEL_B2B1_8822B(x) | BIT_PSF_BSSIDSEL_B2B1_8822B(v))
#define BIT_WOWHCI_8822B BIT(5)
#define BIT_PSF_BSSIDSEL_B0_8822B BIT(4)
@@ -8191,40 +14397,75 @@
#define BIT_SHIFT_LPNAV_EARLY_8822B 16
#define BIT_MASK_LPNAV_EARLY_8822B 0x7fff
-#define BIT_LPNAV_EARLY_8822B(x) (((x) & BIT_MASK_LPNAV_EARLY_8822B) << BIT_SHIFT_LPNAV_EARLY_8822B)
-#define BIT_GET_LPNAV_EARLY_8822B(x) (((x) >> BIT_SHIFT_LPNAV_EARLY_8822B) & BIT_MASK_LPNAV_EARLY_8822B)
-
+#define BIT_LPNAV_EARLY_8822B(x) \
+ (((x) & BIT_MASK_LPNAV_EARLY_8822B) << BIT_SHIFT_LPNAV_EARLY_8822B)
+#define BITS_LPNAV_EARLY_8822B \
+ (BIT_MASK_LPNAV_EARLY_8822B << BIT_SHIFT_LPNAV_EARLY_8822B)
+#define BIT_CLEAR_LPNAV_EARLY_8822B(x) ((x) & (~BITS_LPNAV_EARLY_8822B))
+#define BIT_GET_LPNAV_EARLY_8822B(x) \
+ (((x) >> BIT_SHIFT_LPNAV_EARLY_8822B) & BIT_MASK_LPNAV_EARLY_8822B)
+#define BIT_SET_LPNAV_EARLY_8822B(x, v) \
+ (BIT_CLEAR_LPNAV_EARLY_8822B(x) | BIT_LPNAV_EARLY_8822B(v))
#define BIT_SHIFT_LPNAV_TH_8822B 0
#define BIT_MASK_LPNAV_TH_8822B 0xffff
-#define BIT_LPNAV_TH_8822B(x) (((x) & BIT_MASK_LPNAV_TH_8822B) << BIT_SHIFT_LPNAV_TH_8822B)
-#define BIT_GET_LPNAV_TH_8822B(x) (((x) >> BIT_SHIFT_LPNAV_TH_8822B) & BIT_MASK_LPNAV_TH_8822B)
-
+#define BIT_LPNAV_TH_8822B(x) \
+ (((x) & BIT_MASK_LPNAV_TH_8822B) << BIT_SHIFT_LPNAV_TH_8822B)
+#define BITS_LPNAV_TH_8822B \
+ (BIT_MASK_LPNAV_TH_8822B << BIT_SHIFT_LPNAV_TH_8822B)
+#define BIT_CLEAR_LPNAV_TH_8822B(x) ((x) & (~BITS_LPNAV_TH_8822B))
+#define BIT_GET_LPNAV_TH_8822B(x) \
+ (((x) >> BIT_SHIFT_LPNAV_TH_8822B) & BIT_MASK_LPNAV_TH_8822B)
+#define BIT_SET_LPNAV_TH_8822B(x, v) \
+ (BIT_CLEAR_LPNAV_TH_8822B(x) | BIT_LPNAV_TH_8822B(v))
/* 2 REG_WKFMCAM_CMD_8822B (WAKEUP FRAME CAM COMMAND REGISTER) */
#define BIT_WKFCAM_POLLING_V1_8822B BIT(31)
#define BIT_WKFCAM_CLR_V1_8822B BIT(30)
#define BIT_WKFCAM_WE_8822B BIT(16)
-#define BIT_SHIFT_WKFCAM_ADDR_V1_8822B 7
-#define BIT_MASK_WKFCAM_ADDR_V1_8822B 0x1ff
-#define BIT_WKFCAM_ADDR_V1_8822B(x) (((x) & BIT_MASK_WKFCAM_ADDR_V1_8822B) << BIT_SHIFT_WKFCAM_ADDR_V1_8822B)
-#define BIT_GET_WKFCAM_ADDR_V1_8822B(x) (((x) >> BIT_SHIFT_WKFCAM_ADDR_V1_8822B) & BIT_MASK_WKFCAM_ADDR_V1_8822B)
-
+#define BIT_SHIFT_WKFCAM_ADDR_V2_8822B 8
+#define BIT_MASK_WKFCAM_ADDR_V2_8822B 0xff
+#define BIT_WKFCAM_ADDR_V2_8822B(x) \
+ (((x) & BIT_MASK_WKFCAM_ADDR_V2_8822B) \
+ << BIT_SHIFT_WKFCAM_ADDR_V2_8822B)
+#define BITS_WKFCAM_ADDR_V2_8822B \
+ (BIT_MASK_WKFCAM_ADDR_V2_8822B << BIT_SHIFT_WKFCAM_ADDR_V2_8822B)
+#define BIT_CLEAR_WKFCAM_ADDR_V2_8822B(x) ((x) & (~BITS_WKFCAM_ADDR_V2_8822B))
+#define BIT_GET_WKFCAM_ADDR_V2_8822B(x) \
+ (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2_8822B) & \
+ BIT_MASK_WKFCAM_ADDR_V2_8822B)
+#define BIT_SET_WKFCAM_ADDR_V2_8822B(x, v) \
+ (BIT_CLEAR_WKFCAM_ADDR_V2_8822B(x) | BIT_WKFCAM_ADDR_V2_8822B(v))
#define BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822B 0
#define BIT_MASK_WKFCAM_CAM_NUM_V1_8822B 0xff
-#define BIT_WKFCAM_CAM_NUM_V1_8822B(x) (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1_8822B) << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822B)
-#define BIT_GET_WKFCAM_CAM_NUM_V1_8822B(x) (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822B) & BIT_MASK_WKFCAM_CAM_NUM_V1_8822B)
-
+#define BIT_WKFCAM_CAM_NUM_V1_8822B(x) \
+ (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1_8822B) \
+ << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822B)
+#define BITS_WKFCAM_CAM_NUM_V1_8822B \
+ (BIT_MASK_WKFCAM_CAM_NUM_V1_8822B << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822B)
+#define BIT_CLEAR_WKFCAM_CAM_NUM_V1_8822B(x) \
+ ((x) & (~BITS_WKFCAM_CAM_NUM_V1_8822B))
+#define BIT_GET_WKFCAM_CAM_NUM_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822B) & \
+ BIT_MASK_WKFCAM_CAM_NUM_V1_8822B)
+#define BIT_SET_WKFCAM_CAM_NUM_V1_8822B(x, v) \
+ (BIT_CLEAR_WKFCAM_CAM_NUM_V1_8822B(x) | BIT_WKFCAM_CAM_NUM_V1_8822B(v))
/* 2 REG_WKFMCAM_RWD_8822B (WAKEUP FRAME READ/WRITE DATA) */
#define BIT_SHIFT_WKFMCAM_RWD_8822B 0
#define BIT_MASK_WKFMCAM_RWD_8822B 0xffffffffL
-#define BIT_WKFMCAM_RWD_8822B(x) (((x) & BIT_MASK_WKFMCAM_RWD_8822B) << BIT_SHIFT_WKFMCAM_RWD_8822B)
-#define BIT_GET_WKFMCAM_RWD_8822B(x) (((x) >> BIT_SHIFT_WKFMCAM_RWD_8822B) & BIT_MASK_WKFMCAM_RWD_8822B)
-
+#define BIT_WKFMCAM_RWD_8822B(x) \
+ (((x) & BIT_MASK_WKFMCAM_RWD_8822B) << BIT_SHIFT_WKFMCAM_RWD_8822B)
+#define BITS_WKFMCAM_RWD_8822B \
+ (BIT_MASK_WKFMCAM_RWD_8822B << BIT_SHIFT_WKFMCAM_RWD_8822B)
+#define BIT_CLEAR_WKFMCAM_RWD_8822B(x) ((x) & (~BITS_WKFMCAM_RWD_8822B))
+#define BIT_GET_WKFMCAM_RWD_8822B(x) \
+ (((x) >> BIT_SHIFT_WKFMCAM_RWD_8822B) & BIT_MASK_WKFMCAM_RWD_8822B)
+#define BIT_SET_WKFMCAM_RWD_8822B(x, v) \
+ (BIT_CLEAR_WKFMCAM_RWD_8822B(x) | BIT_WKFMCAM_RWD_8822B(v))
/* 2 REG_RXFLTMAP1_8822B (RX FILTER MAP GROUP 1) */
#define BIT_CTRLFLT15EN_8822B BIT(15)
@@ -8264,7 +14505,7 @@
/* 2 REG_NOT_VALID_8822B */
-/* 2 REG_RXFLTMAP_8822B (RX FILTER MAP GROUP 2) */
+/* 2 REG_RXFLTMAP2_8822B (RX FILTER MAP GROUP 2) */
#define BIT_DATAFLT15EN_8822B BIT(15)
#define BIT_DATAFLT14EN_8822B BIT(14)
#define BIT_DATAFLT13EN_8822B BIT(13)
@@ -8286,23 +14527,42 @@
#define BIT_SHIFT_DTIM_CNT_8822B 24
#define BIT_MASK_DTIM_CNT_8822B 0xff
-#define BIT_DTIM_CNT_8822B(x) (((x) & BIT_MASK_DTIM_CNT_8822B) << BIT_SHIFT_DTIM_CNT_8822B)
-#define BIT_GET_DTIM_CNT_8822B(x) (((x) >> BIT_SHIFT_DTIM_CNT_8822B) & BIT_MASK_DTIM_CNT_8822B)
-
+#define BIT_DTIM_CNT_8822B(x) \
+ (((x) & BIT_MASK_DTIM_CNT_8822B) << BIT_SHIFT_DTIM_CNT_8822B)
+#define BITS_DTIM_CNT_8822B \
+ (BIT_MASK_DTIM_CNT_8822B << BIT_SHIFT_DTIM_CNT_8822B)
+#define BIT_CLEAR_DTIM_CNT_8822B(x) ((x) & (~BITS_DTIM_CNT_8822B))
+#define BIT_GET_DTIM_CNT_8822B(x) \
+ (((x) >> BIT_SHIFT_DTIM_CNT_8822B) & BIT_MASK_DTIM_CNT_8822B)
+#define BIT_SET_DTIM_CNT_8822B(x, v) \
+ (BIT_CLEAR_DTIM_CNT_8822B(x) | BIT_DTIM_CNT_8822B(v))
#define BIT_SHIFT_DTIM_PERIOD_8822B 16
#define BIT_MASK_DTIM_PERIOD_8822B 0xff
-#define BIT_DTIM_PERIOD_8822B(x) (((x) & BIT_MASK_DTIM_PERIOD_8822B) << BIT_SHIFT_DTIM_PERIOD_8822B)
-#define BIT_GET_DTIM_PERIOD_8822B(x) (((x) >> BIT_SHIFT_DTIM_PERIOD_8822B) & BIT_MASK_DTIM_PERIOD_8822B)
+#define BIT_DTIM_PERIOD_8822B(x) \
+ (((x) & BIT_MASK_DTIM_PERIOD_8822B) << BIT_SHIFT_DTIM_PERIOD_8822B)
+#define BITS_DTIM_PERIOD_8822B \
+ (BIT_MASK_DTIM_PERIOD_8822B << BIT_SHIFT_DTIM_PERIOD_8822B)
+#define BIT_CLEAR_DTIM_PERIOD_8822B(x) ((x) & (~BITS_DTIM_PERIOD_8822B))
+#define BIT_GET_DTIM_PERIOD_8822B(x) \
+ (((x) >> BIT_SHIFT_DTIM_PERIOD_8822B) & BIT_MASK_DTIM_PERIOD_8822B)
+#define BIT_SET_DTIM_PERIOD_8822B(x, v) \
+ (BIT_CLEAR_DTIM_PERIOD_8822B(x) | BIT_DTIM_PERIOD_8822B(v))
#define BIT_DTIM_8822B BIT(15)
#define BIT_TIM_8822B BIT(14)
#define BIT_SHIFT_PS_AID_0_8822B 0
#define BIT_MASK_PS_AID_0_8822B 0x7ff
-#define BIT_PS_AID_0_8822B(x) (((x) & BIT_MASK_PS_AID_0_8822B) << BIT_SHIFT_PS_AID_0_8822B)
-#define BIT_GET_PS_AID_0_8822B(x) (((x) >> BIT_SHIFT_PS_AID_0_8822B) & BIT_MASK_PS_AID_0_8822B)
-
+#define BIT_PS_AID_0_8822B(x) \
+ (((x) & BIT_MASK_PS_AID_0_8822B) << BIT_SHIFT_PS_AID_0_8822B)
+#define BITS_PS_AID_0_8822B \
+ (BIT_MASK_PS_AID_0_8822B << BIT_SHIFT_PS_AID_0_8822B)
+#define BIT_CLEAR_PS_AID_0_8822B(x) ((x) & (~BITS_PS_AID_0_8822B))
+#define BIT_GET_PS_AID_0_8822B(x) \
+ (((x) >> BIT_SHIFT_PS_AID_0_8822B) & BIT_MASK_PS_AID_0_8822B)
+#define BIT_SET_PS_AID_0_8822B(x, v) \
+ (BIT_CLEAR_PS_AID_0_8822B(x) | BIT_PS_AID_0_8822B(v))
/* 2 REG_FLC_TRPC_8822B (TIMER OF FLC_RPC) */
#define BIT_FLC_RPCT_V1_8822B BIT(7)
@@ -8310,9 +14570,14 @@
#define BIT_SHIFT_TRPCD_8822B 0
#define BIT_MASK_TRPCD_8822B 0x3f
-#define BIT_TRPCD_8822B(x) (((x) & BIT_MASK_TRPCD_8822B) << BIT_SHIFT_TRPCD_8822B)
-#define BIT_GET_TRPCD_8822B(x) (((x) >> BIT_SHIFT_TRPCD_8822B) & BIT_MASK_TRPCD_8822B)
-
+#define BIT_TRPCD_8822B(x) \
+ (((x) & BIT_MASK_TRPCD_8822B) << BIT_SHIFT_TRPCD_8822B)
+#define BITS_TRPCD_8822B (BIT_MASK_TRPCD_8822B << BIT_SHIFT_TRPCD_8822B)
+#define BIT_CLEAR_TRPCD_8822B(x) ((x) & (~BITS_TRPCD_8822B))
+#define BIT_GET_TRPCD_8822B(x) \
+ (((x) >> BIT_SHIFT_TRPCD_8822B) & BIT_MASK_TRPCD_8822B)
+#define BIT_SET_TRPCD_8822B(x, v) \
+ (BIT_CLEAR_TRPCD_8822B(x) | BIT_TRPCD_8822B(v))
/* 2 REG_FLC_PTS_8822B (PKT TYPE SELECTION OF FLC_RPC T) */
#define BIT_CMF_8822B BIT(2)
@@ -8323,42 +14588,78 @@
#define BIT_SHIFT_FLC_RPCT_8822B 0
#define BIT_MASK_FLC_RPCT_8822B 0xff
-#define BIT_FLC_RPCT_8822B(x) (((x) & BIT_MASK_FLC_RPCT_8822B) << BIT_SHIFT_FLC_RPCT_8822B)
-#define BIT_GET_FLC_RPCT_8822B(x) (((x) >> BIT_SHIFT_FLC_RPCT_8822B) & BIT_MASK_FLC_RPCT_8822B)
-
+#define BIT_FLC_RPCT_8822B(x) \
+ (((x) & BIT_MASK_FLC_RPCT_8822B) << BIT_SHIFT_FLC_RPCT_8822B)
+#define BITS_FLC_RPCT_8822B \
+ (BIT_MASK_FLC_RPCT_8822B << BIT_SHIFT_FLC_RPCT_8822B)
+#define BIT_CLEAR_FLC_RPCT_8822B(x) ((x) & (~BITS_FLC_RPCT_8822B))
+#define BIT_GET_FLC_RPCT_8822B(x) \
+ (((x) >> BIT_SHIFT_FLC_RPCT_8822B) & BIT_MASK_FLC_RPCT_8822B)
+#define BIT_SET_FLC_RPCT_8822B(x, v) \
+ (BIT_CLEAR_FLC_RPCT_8822B(x) | BIT_FLC_RPCT_8822B(v))
/* 2 REG_FLC_RPC_8822B (FW LPS CONDITION -- RX PKT COUNTER) */
#define BIT_SHIFT_FLC_RPC_8822B 0
#define BIT_MASK_FLC_RPC_8822B 0xff
-#define BIT_FLC_RPC_8822B(x) (((x) & BIT_MASK_FLC_RPC_8822B) << BIT_SHIFT_FLC_RPC_8822B)
-#define BIT_GET_FLC_RPC_8822B(x) (((x) >> BIT_SHIFT_FLC_RPC_8822B) & BIT_MASK_FLC_RPC_8822B)
-
+#define BIT_FLC_RPC_8822B(x) \
+ (((x) & BIT_MASK_FLC_RPC_8822B) << BIT_SHIFT_FLC_RPC_8822B)
+#define BITS_FLC_RPC_8822B (BIT_MASK_FLC_RPC_8822B << BIT_SHIFT_FLC_RPC_8822B)
+#define BIT_CLEAR_FLC_RPC_8822B(x) ((x) & (~BITS_FLC_RPC_8822B))
+#define BIT_GET_FLC_RPC_8822B(x) \
+ (((x) >> BIT_SHIFT_FLC_RPC_8822B) & BIT_MASK_FLC_RPC_8822B)
+#define BIT_SET_FLC_RPC_8822B(x, v) \
+ (BIT_CLEAR_FLC_RPC_8822B(x) | BIT_FLC_RPC_8822B(v))
/* 2 REG_RXPKTMON_CTRL_8822B */
#define BIT_SHIFT_RXBKQPKT_SEQ_8822B 20
#define BIT_MASK_RXBKQPKT_SEQ_8822B 0xf
-#define BIT_RXBKQPKT_SEQ_8822B(x) (((x) & BIT_MASK_RXBKQPKT_SEQ_8822B) << BIT_SHIFT_RXBKQPKT_SEQ_8822B)
-#define BIT_GET_RXBKQPKT_SEQ_8822B(x) (((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8822B) & BIT_MASK_RXBKQPKT_SEQ_8822B)
-
+#define BIT_RXBKQPKT_SEQ_8822B(x) \
+ (((x) & BIT_MASK_RXBKQPKT_SEQ_8822B) << BIT_SHIFT_RXBKQPKT_SEQ_8822B)
+#define BITS_RXBKQPKT_SEQ_8822B \
+ (BIT_MASK_RXBKQPKT_SEQ_8822B << BIT_SHIFT_RXBKQPKT_SEQ_8822B)
+#define BIT_CLEAR_RXBKQPKT_SEQ_8822B(x) ((x) & (~BITS_RXBKQPKT_SEQ_8822B))
+#define BIT_GET_RXBKQPKT_SEQ_8822B(x) \
+ (((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8822B) & BIT_MASK_RXBKQPKT_SEQ_8822B)
+#define BIT_SET_RXBKQPKT_SEQ_8822B(x, v) \
+ (BIT_CLEAR_RXBKQPKT_SEQ_8822B(x) | BIT_RXBKQPKT_SEQ_8822B(v))
#define BIT_SHIFT_RXBEQPKT_SEQ_8822B 16
#define BIT_MASK_RXBEQPKT_SEQ_8822B 0xf
-#define BIT_RXBEQPKT_SEQ_8822B(x) (((x) & BIT_MASK_RXBEQPKT_SEQ_8822B) << BIT_SHIFT_RXBEQPKT_SEQ_8822B)
-#define BIT_GET_RXBEQPKT_SEQ_8822B(x) (((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8822B) & BIT_MASK_RXBEQPKT_SEQ_8822B)
-
+#define BIT_RXBEQPKT_SEQ_8822B(x) \
+ (((x) & BIT_MASK_RXBEQPKT_SEQ_8822B) << BIT_SHIFT_RXBEQPKT_SEQ_8822B)
+#define BITS_RXBEQPKT_SEQ_8822B \
+ (BIT_MASK_RXBEQPKT_SEQ_8822B << BIT_SHIFT_RXBEQPKT_SEQ_8822B)
+#define BIT_CLEAR_RXBEQPKT_SEQ_8822B(x) ((x) & (~BITS_RXBEQPKT_SEQ_8822B))
+#define BIT_GET_RXBEQPKT_SEQ_8822B(x) \
+ (((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8822B) & BIT_MASK_RXBEQPKT_SEQ_8822B)
+#define BIT_SET_RXBEQPKT_SEQ_8822B(x, v) \
+ (BIT_CLEAR_RXBEQPKT_SEQ_8822B(x) | BIT_RXBEQPKT_SEQ_8822B(v))
#define BIT_SHIFT_RXVIQPKT_SEQ_8822B 12
#define BIT_MASK_RXVIQPKT_SEQ_8822B 0xf
-#define BIT_RXVIQPKT_SEQ_8822B(x) (((x) & BIT_MASK_RXVIQPKT_SEQ_8822B) << BIT_SHIFT_RXVIQPKT_SEQ_8822B)
-#define BIT_GET_RXVIQPKT_SEQ_8822B(x) (((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8822B) & BIT_MASK_RXVIQPKT_SEQ_8822B)
-
+#define BIT_RXVIQPKT_SEQ_8822B(x) \
+ (((x) & BIT_MASK_RXVIQPKT_SEQ_8822B) << BIT_SHIFT_RXVIQPKT_SEQ_8822B)
+#define BITS_RXVIQPKT_SEQ_8822B \
+ (BIT_MASK_RXVIQPKT_SEQ_8822B << BIT_SHIFT_RXVIQPKT_SEQ_8822B)
+#define BIT_CLEAR_RXVIQPKT_SEQ_8822B(x) ((x) & (~BITS_RXVIQPKT_SEQ_8822B))
+#define BIT_GET_RXVIQPKT_SEQ_8822B(x) \
+ (((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8822B) & BIT_MASK_RXVIQPKT_SEQ_8822B)
+#define BIT_SET_RXVIQPKT_SEQ_8822B(x, v) \
+ (BIT_CLEAR_RXVIQPKT_SEQ_8822B(x) | BIT_RXVIQPKT_SEQ_8822B(v))
#define BIT_SHIFT_RXVOQPKT_SEQ_8822B 8
#define BIT_MASK_RXVOQPKT_SEQ_8822B 0xf
-#define BIT_RXVOQPKT_SEQ_8822B(x) (((x) & BIT_MASK_RXVOQPKT_SEQ_8822B) << BIT_SHIFT_RXVOQPKT_SEQ_8822B)
-#define BIT_GET_RXVOQPKT_SEQ_8822B(x) (((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8822B) & BIT_MASK_RXVOQPKT_SEQ_8822B)
+#define BIT_RXVOQPKT_SEQ_8822B(x) \
+ (((x) & BIT_MASK_RXVOQPKT_SEQ_8822B) << BIT_SHIFT_RXVOQPKT_SEQ_8822B)
+#define BITS_RXVOQPKT_SEQ_8822B \
+ (BIT_MASK_RXVOQPKT_SEQ_8822B << BIT_SHIFT_RXVOQPKT_SEQ_8822B)
+#define BIT_CLEAR_RXVOQPKT_SEQ_8822B(x) ((x) & (~BITS_RXVOQPKT_SEQ_8822B))
+#define BIT_GET_RXVOQPKT_SEQ_8822B(x) \
+ (((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8822B) & BIT_MASK_RXVOQPKT_SEQ_8822B)
+#define BIT_SET_RXVOQPKT_SEQ_8822B(x, v) \
+ (BIT_CLEAR_RXVOQPKT_SEQ_8822B(x) | BIT_RXVOQPKT_SEQ_8822B(v))
#define BIT_RXBKQPKT_ERR_8822B BIT(7)
#define BIT_RXBEQPKT_ERR_8822B BIT(6)
@@ -8372,22 +14673,41 @@
#define BIT_SHIFT_STATE_SEL_8822B 24
#define BIT_MASK_STATE_SEL_8822B 0x1f
-#define BIT_STATE_SEL_8822B(x) (((x) & BIT_MASK_STATE_SEL_8822B) << BIT_SHIFT_STATE_SEL_8822B)
-#define BIT_GET_STATE_SEL_8822B(x) (((x) >> BIT_SHIFT_STATE_SEL_8822B) & BIT_MASK_STATE_SEL_8822B)
-
+#define BIT_STATE_SEL_8822B(x) \
+ (((x) & BIT_MASK_STATE_SEL_8822B) << BIT_SHIFT_STATE_SEL_8822B)
+#define BITS_STATE_SEL_8822B \
+ (BIT_MASK_STATE_SEL_8822B << BIT_SHIFT_STATE_SEL_8822B)
+#define BIT_CLEAR_STATE_SEL_8822B(x) ((x) & (~BITS_STATE_SEL_8822B))
+#define BIT_GET_STATE_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_STATE_SEL_8822B) & BIT_MASK_STATE_SEL_8822B)
+#define BIT_SET_STATE_SEL_8822B(x, v) \
+ (BIT_CLEAR_STATE_SEL_8822B(x) | BIT_STATE_SEL_8822B(v))
#define BIT_SHIFT_STATE_INFO_8822B 8
#define BIT_MASK_STATE_INFO_8822B 0xff
-#define BIT_STATE_INFO_8822B(x) (((x) & BIT_MASK_STATE_INFO_8822B) << BIT_SHIFT_STATE_INFO_8822B)
-#define BIT_GET_STATE_INFO_8822B(x) (((x) >> BIT_SHIFT_STATE_INFO_8822B) & BIT_MASK_STATE_INFO_8822B)
+#define BIT_STATE_INFO_8822B(x) \
+ (((x) & BIT_MASK_STATE_INFO_8822B) << BIT_SHIFT_STATE_INFO_8822B)
+#define BITS_STATE_INFO_8822B \
+ (BIT_MASK_STATE_INFO_8822B << BIT_SHIFT_STATE_INFO_8822B)
+#define BIT_CLEAR_STATE_INFO_8822B(x) ((x) & (~BITS_STATE_INFO_8822B))
+#define BIT_GET_STATE_INFO_8822B(x) \
+ (((x) >> BIT_SHIFT_STATE_INFO_8822B) & BIT_MASK_STATE_INFO_8822B)
+#define BIT_SET_STATE_INFO_8822B(x, v) \
+ (BIT_CLEAR_STATE_INFO_8822B(x) | BIT_STATE_INFO_8822B(v))
#define BIT_UPD_NXT_STATE_8822B BIT(7)
#define BIT_SHIFT_CUR_STATE_8822B 0
#define BIT_MASK_CUR_STATE_8822B 0x7f
-#define BIT_CUR_STATE_8822B(x) (((x) & BIT_MASK_CUR_STATE_8822B) << BIT_SHIFT_CUR_STATE_8822B)
-#define BIT_GET_CUR_STATE_8822B(x) (((x) >> BIT_SHIFT_CUR_STATE_8822B) & BIT_MASK_CUR_STATE_8822B)
-
+#define BIT_CUR_STATE_8822B(x) \
+ (((x) & BIT_MASK_CUR_STATE_8822B) << BIT_SHIFT_CUR_STATE_8822B)
+#define BITS_CUR_STATE_8822B \
+ (BIT_MASK_CUR_STATE_8822B << BIT_SHIFT_CUR_STATE_8822B)
+#define BIT_CLEAR_CUR_STATE_8822B(x) ((x) & (~BITS_CUR_STATE_8822B))
+#define BIT_GET_CUR_STATE_8822B(x) \
+ (((x) >> BIT_SHIFT_CUR_STATE_8822B) & BIT_MASK_CUR_STATE_8822B)
+#define BIT_SET_CUR_STATE_8822B(x, v) \
+ (BIT_CLEAR_CUR_STATE_8822B(x) | BIT_CUR_STATE_8822B(v))
/* 2 REG_ERROR_MON_8822B */
#define BIT_MACRX_ERR_1_8822B BIT(17)
@@ -8402,8 +14722,18 @@
#define BIT_SHIFT_INFO_INDEX_OFFSET_8822B 16
#define BIT_MASK_INFO_INDEX_OFFSET_8822B 0x1fff
-#define BIT_INFO_INDEX_OFFSET_8822B(x) (((x) & BIT_MASK_INFO_INDEX_OFFSET_8822B) << BIT_SHIFT_INFO_INDEX_OFFSET_8822B)
-#define BIT_GET_INFO_INDEX_OFFSET_8822B(x) (((x) >> BIT_SHIFT_INFO_INDEX_OFFSET_8822B) & BIT_MASK_INFO_INDEX_OFFSET_8822B)
+#define BIT_INFO_INDEX_OFFSET_8822B(x) \
+ (((x) & BIT_MASK_INFO_INDEX_OFFSET_8822B) \
+ << BIT_SHIFT_INFO_INDEX_OFFSET_8822B)
+#define BITS_INFO_INDEX_OFFSET_8822B \
+ (BIT_MASK_INFO_INDEX_OFFSET_8822B << BIT_SHIFT_INFO_INDEX_OFFSET_8822B)
+#define BIT_CLEAR_INFO_INDEX_OFFSET_8822B(x) \
+ ((x) & (~BITS_INFO_INDEX_OFFSET_8822B))
+#define BIT_GET_INFO_INDEX_OFFSET_8822B(x) \
+ (((x) >> BIT_SHIFT_INFO_INDEX_OFFSET_8822B) & \
+ BIT_MASK_INFO_INDEX_OFFSET_8822B)
+#define BIT_SET_INFO_INDEX_OFFSET_8822B(x, v) \
+ (BIT_CLEAR_INFO_INDEX_OFFSET_8822B(x) | BIT_INFO_INDEX_OFFSET_8822B(v))
#define BIT_WMAC_SRCH_FIFOFULL_8822B BIT(15)
#define BIT_DIS_INFOSRCH_8822B BIT(14)
@@ -8411,9 +14741,18 @@
#define BIT_SHIFT_INFO_ADDR_OFFSET_8822B 0
#define BIT_MASK_INFO_ADDR_OFFSET_8822B 0x1fff
-#define BIT_INFO_ADDR_OFFSET_8822B(x) (((x) & BIT_MASK_INFO_ADDR_OFFSET_8822B) << BIT_SHIFT_INFO_ADDR_OFFSET_8822B)
-#define BIT_GET_INFO_ADDR_OFFSET_8822B(x) (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8822B) & BIT_MASK_INFO_ADDR_OFFSET_8822B)
-
+#define BIT_INFO_ADDR_OFFSET_8822B(x) \
+ (((x) & BIT_MASK_INFO_ADDR_OFFSET_8822B) \
+ << BIT_SHIFT_INFO_ADDR_OFFSET_8822B)
+#define BITS_INFO_ADDR_OFFSET_8822B \
+ (BIT_MASK_INFO_ADDR_OFFSET_8822B << BIT_SHIFT_INFO_ADDR_OFFSET_8822B)
+#define BIT_CLEAR_INFO_ADDR_OFFSET_8822B(x) \
+ ((x) & (~BITS_INFO_ADDR_OFFSET_8822B))
+#define BIT_GET_INFO_ADDR_OFFSET_8822B(x) \
+ (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8822B) & \
+ BIT_MASK_INFO_ADDR_OFFSET_8822B)
+#define BIT_SET_INFO_ADDR_OFFSET_8822B(x, v) \
+ (BIT_CLEAR_INFO_ADDR_OFFSET_8822B(x) | BIT_INFO_ADDR_OFFSET_8822B(v))
/* 2 REG_BT_COEX_TABLE_8822B (BT-COEXISTENCE CONTROL REGISTER) */
#define BIT_PRI_MASK_RX_RESP_8822B BIT(126)
@@ -8422,14 +14761,27 @@
#define BIT_SHIFT_PRI_MASK_TXAC_8822B (117 & CPU_OPT_WIDTH)
#define BIT_MASK_PRI_MASK_TXAC_8822B 0x7f
-#define BIT_PRI_MASK_TXAC_8822B(x) (((x) & BIT_MASK_PRI_MASK_TXAC_8822B) << BIT_SHIFT_PRI_MASK_TXAC_8822B)
-#define BIT_GET_PRI_MASK_TXAC_8822B(x) (((x) >> BIT_SHIFT_PRI_MASK_TXAC_8822B) & BIT_MASK_PRI_MASK_TXAC_8822B)
-
+#define BIT_PRI_MASK_TXAC_8822B(x) \
+ (((x) & BIT_MASK_PRI_MASK_TXAC_8822B) << BIT_SHIFT_PRI_MASK_TXAC_8822B)
+#define BITS_PRI_MASK_TXAC_8822B \
+ (BIT_MASK_PRI_MASK_TXAC_8822B << BIT_SHIFT_PRI_MASK_TXAC_8822B)
+#define BIT_CLEAR_PRI_MASK_TXAC_8822B(x) ((x) & (~BITS_PRI_MASK_TXAC_8822B))
+#define BIT_GET_PRI_MASK_TXAC_8822B(x) \
+ (((x) >> BIT_SHIFT_PRI_MASK_TXAC_8822B) & BIT_MASK_PRI_MASK_TXAC_8822B)
+#define BIT_SET_PRI_MASK_TXAC_8822B(x, v) \
+ (BIT_CLEAR_PRI_MASK_TXAC_8822B(x) | BIT_PRI_MASK_TXAC_8822B(v))
#define BIT_SHIFT_PRI_MASK_NAV_8822B (109 & CPU_OPT_WIDTH)
#define BIT_MASK_PRI_MASK_NAV_8822B 0xff
-#define BIT_PRI_MASK_NAV_8822B(x) (((x) & BIT_MASK_PRI_MASK_NAV_8822B) << BIT_SHIFT_PRI_MASK_NAV_8822B)
-#define BIT_GET_PRI_MASK_NAV_8822B(x) (((x) >> BIT_SHIFT_PRI_MASK_NAV_8822B) & BIT_MASK_PRI_MASK_NAV_8822B)
+#define BIT_PRI_MASK_NAV_8822B(x) \
+ (((x) & BIT_MASK_PRI_MASK_NAV_8822B) << BIT_SHIFT_PRI_MASK_NAV_8822B)
+#define BITS_PRI_MASK_NAV_8822B \
+ (BIT_MASK_PRI_MASK_NAV_8822B << BIT_SHIFT_PRI_MASK_NAV_8822B)
+#define BIT_CLEAR_PRI_MASK_NAV_8822B(x) ((x) & (~BITS_PRI_MASK_NAV_8822B))
+#define BIT_GET_PRI_MASK_NAV_8822B(x) \
+ (((x) >> BIT_SHIFT_PRI_MASK_NAV_8822B) & BIT_MASK_PRI_MASK_NAV_8822B)
+#define BIT_SET_PRI_MASK_NAV_8822B(x, v) \
+ (BIT_CLEAR_PRI_MASK_NAV_8822B(x) | BIT_PRI_MASK_NAV_8822B(v))
#define BIT_PRI_MASK_CCK_8822B BIT(108)
#define BIT_PRI_MASK_OFDM_8822B BIT(107)
@@ -8437,58 +14789,107 @@
#define BIT_SHIFT_PRI_MASK_NUM_8822B (102 & CPU_OPT_WIDTH)
#define BIT_MASK_PRI_MASK_NUM_8822B 0xf
-#define BIT_PRI_MASK_NUM_8822B(x) (((x) & BIT_MASK_PRI_MASK_NUM_8822B) << BIT_SHIFT_PRI_MASK_NUM_8822B)
-#define BIT_GET_PRI_MASK_NUM_8822B(x) (((x) >> BIT_SHIFT_PRI_MASK_NUM_8822B) & BIT_MASK_PRI_MASK_NUM_8822B)
-
+#define BIT_PRI_MASK_NUM_8822B(x) \
+ (((x) & BIT_MASK_PRI_MASK_NUM_8822B) << BIT_SHIFT_PRI_MASK_NUM_8822B)
+#define BITS_PRI_MASK_NUM_8822B \
+ (BIT_MASK_PRI_MASK_NUM_8822B << BIT_SHIFT_PRI_MASK_NUM_8822B)
+#define BIT_CLEAR_PRI_MASK_NUM_8822B(x) ((x) & (~BITS_PRI_MASK_NUM_8822B))
+#define BIT_GET_PRI_MASK_NUM_8822B(x) \
+ (((x) >> BIT_SHIFT_PRI_MASK_NUM_8822B) & BIT_MASK_PRI_MASK_NUM_8822B)
+#define BIT_SET_PRI_MASK_NUM_8822B(x, v) \
+ (BIT_CLEAR_PRI_MASK_NUM_8822B(x) | BIT_PRI_MASK_NUM_8822B(v))
#define BIT_SHIFT_PRI_MASK_TYPE_8822B (98 & CPU_OPT_WIDTH)
#define BIT_MASK_PRI_MASK_TYPE_8822B 0xf
-#define BIT_PRI_MASK_TYPE_8822B(x) (((x) & BIT_MASK_PRI_MASK_TYPE_8822B) << BIT_SHIFT_PRI_MASK_TYPE_8822B)
-#define BIT_GET_PRI_MASK_TYPE_8822B(x) (((x) >> BIT_SHIFT_PRI_MASK_TYPE_8822B) & BIT_MASK_PRI_MASK_TYPE_8822B)
+#define BIT_PRI_MASK_TYPE_8822B(x) \
+ (((x) & BIT_MASK_PRI_MASK_TYPE_8822B) << BIT_SHIFT_PRI_MASK_TYPE_8822B)
+#define BITS_PRI_MASK_TYPE_8822B \
+ (BIT_MASK_PRI_MASK_TYPE_8822B << BIT_SHIFT_PRI_MASK_TYPE_8822B)
+#define BIT_CLEAR_PRI_MASK_TYPE_8822B(x) ((x) & (~BITS_PRI_MASK_TYPE_8822B))
+#define BIT_GET_PRI_MASK_TYPE_8822B(x) \
+ (((x) >> BIT_SHIFT_PRI_MASK_TYPE_8822B) & BIT_MASK_PRI_MASK_TYPE_8822B)
+#define BIT_SET_PRI_MASK_TYPE_8822B(x, v) \
+ (BIT_CLEAR_PRI_MASK_TYPE_8822B(x) | BIT_PRI_MASK_TYPE_8822B(v))
#define BIT_OOB_8822B BIT(97)
#define BIT_ANT_SEL_8822B BIT(96)
#define BIT_SHIFT_BREAK_TABLE_2_8822B (80 & CPU_OPT_WIDTH)
#define BIT_MASK_BREAK_TABLE_2_8822B 0xffff
-#define BIT_BREAK_TABLE_2_8822B(x) (((x) & BIT_MASK_BREAK_TABLE_2_8822B) << BIT_SHIFT_BREAK_TABLE_2_8822B)
-#define BIT_GET_BREAK_TABLE_2_8822B(x) (((x) >> BIT_SHIFT_BREAK_TABLE_2_8822B) & BIT_MASK_BREAK_TABLE_2_8822B)
-
+#define BIT_BREAK_TABLE_2_8822B(x) \
+ (((x) & BIT_MASK_BREAK_TABLE_2_8822B) << BIT_SHIFT_BREAK_TABLE_2_8822B)
+#define BITS_BREAK_TABLE_2_8822B \
+ (BIT_MASK_BREAK_TABLE_2_8822B << BIT_SHIFT_BREAK_TABLE_2_8822B)
+#define BIT_CLEAR_BREAK_TABLE_2_8822B(x) ((x) & (~BITS_BREAK_TABLE_2_8822B))
+#define BIT_GET_BREAK_TABLE_2_8822B(x) \
+ (((x) >> BIT_SHIFT_BREAK_TABLE_2_8822B) & BIT_MASK_BREAK_TABLE_2_8822B)
+#define BIT_SET_BREAK_TABLE_2_8822B(x, v) \
+ (BIT_CLEAR_BREAK_TABLE_2_8822B(x) | BIT_BREAK_TABLE_2_8822B(v))
#define BIT_SHIFT_BREAK_TABLE_1_8822B (64 & CPU_OPT_WIDTH)
#define BIT_MASK_BREAK_TABLE_1_8822B 0xffff
-#define BIT_BREAK_TABLE_1_8822B(x) (((x) & BIT_MASK_BREAK_TABLE_1_8822B) << BIT_SHIFT_BREAK_TABLE_1_8822B)
-#define BIT_GET_BREAK_TABLE_1_8822B(x) (((x) >> BIT_SHIFT_BREAK_TABLE_1_8822B) & BIT_MASK_BREAK_TABLE_1_8822B)
-
+#define BIT_BREAK_TABLE_1_8822B(x) \
+ (((x) & BIT_MASK_BREAK_TABLE_1_8822B) << BIT_SHIFT_BREAK_TABLE_1_8822B)
+#define BITS_BREAK_TABLE_1_8822B \
+ (BIT_MASK_BREAK_TABLE_1_8822B << BIT_SHIFT_BREAK_TABLE_1_8822B)
+#define BIT_CLEAR_BREAK_TABLE_1_8822B(x) ((x) & (~BITS_BREAK_TABLE_1_8822B))
+#define BIT_GET_BREAK_TABLE_1_8822B(x) \
+ (((x) >> BIT_SHIFT_BREAK_TABLE_1_8822B) & BIT_MASK_BREAK_TABLE_1_8822B)
+#define BIT_SET_BREAK_TABLE_1_8822B(x, v) \
+ (BIT_CLEAR_BREAK_TABLE_1_8822B(x) | BIT_BREAK_TABLE_1_8822B(v))
#define BIT_SHIFT_COEX_TABLE_2_8822B (32 & CPU_OPT_WIDTH)
#define BIT_MASK_COEX_TABLE_2_8822B 0xffffffffL
-#define BIT_COEX_TABLE_2_8822B(x) (((x) & BIT_MASK_COEX_TABLE_2_8822B) << BIT_SHIFT_COEX_TABLE_2_8822B)
-#define BIT_GET_COEX_TABLE_2_8822B(x) (((x) >> BIT_SHIFT_COEX_TABLE_2_8822B) & BIT_MASK_COEX_TABLE_2_8822B)
-
+#define BIT_COEX_TABLE_2_8822B(x) \
+ (((x) & BIT_MASK_COEX_TABLE_2_8822B) << BIT_SHIFT_COEX_TABLE_2_8822B)
+#define BITS_COEX_TABLE_2_8822B \
+ (BIT_MASK_COEX_TABLE_2_8822B << BIT_SHIFT_COEX_TABLE_2_8822B)
+#define BIT_CLEAR_COEX_TABLE_2_8822B(x) ((x) & (~BITS_COEX_TABLE_2_8822B))
+#define BIT_GET_COEX_TABLE_2_8822B(x) \
+ (((x) >> BIT_SHIFT_COEX_TABLE_2_8822B) & BIT_MASK_COEX_TABLE_2_8822B)
+#define BIT_SET_COEX_TABLE_2_8822B(x, v) \
+ (BIT_CLEAR_COEX_TABLE_2_8822B(x) | BIT_COEX_TABLE_2_8822B(v))
#define BIT_SHIFT_COEX_TABLE_1_8822B 0
#define BIT_MASK_COEX_TABLE_1_8822B 0xffffffffL
-#define BIT_COEX_TABLE_1_8822B(x) (((x) & BIT_MASK_COEX_TABLE_1_8822B) << BIT_SHIFT_COEX_TABLE_1_8822B)
-#define BIT_GET_COEX_TABLE_1_8822B(x) (((x) >> BIT_SHIFT_COEX_TABLE_1_8822B) & BIT_MASK_COEX_TABLE_1_8822B)
-
+#define BIT_COEX_TABLE_1_8822B(x) \
+ (((x) & BIT_MASK_COEX_TABLE_1_8822B) << BIT_SHIFT_COEX_TABLE_1_8822B)
+#define BITS_COEX_TABLE_1_8822B \
+ (BIT_MASK_COEX_TABLE_1_8822B << BIT_SHIFT_COEX_TABLE_1_8822B)
+#define BIT_CLEAR_COEX_TABLE_1_8822B(x) ((x) & (~BITS_COEX_TABLE_1_8822B))
+#define BIT_GET_COEX_TABLE_1_8822B(x) \
+ (((x) >> BIT_SHIFT_COEX_TABLE_1_8822B) & BIT_MASK_COEX_TABLE_1_8822B)
+#define BIT_SET_COEX_TABLE_1_8822B(x, v) \
+ (BIT_CLEAR_COEX_TABLE_1_8822B(x) | BIT_COEX_TABLE_1_8822B(v))
/* 2 REG_RXCMD_0_8822B */
#define BIT_RXCMD_EN_8822B BIT(31)
#define BIT_SHIFT_RXCMD_INFO_8822B 0
#define BIT_MASK_RXCMD_INFO_8822B 0x7fffffffL
-#define BIT_RXCMD_INFO_8822B(x) (((x) & BIT_MASK_RXCMD_INFO_8822B) << BIT_SHIFT_RXCMD_INFO_8822B)
-#define BIT_GET_RXCMD_INFO_8822B(x) (((x) >> BIT_SHIFT_RXCMD_INFO_8822B) & BIT_MASK_RXCMD_INFO_8822B)
-
+#define BIT_RXCMD_INFO_8822B(x) \
+ (((x) & BIT_MASK_RXCMD_INFO_8822B) << BIT_SHIFT_RXCMD_INFO_8822B)
+#define BITS_RXCMD_INFO_8822B \
+ (BIT_MASK_RXCMD_INFO_8822B << BIT_SHIFT_RXCMD_INFO_8822B)
+#define BIT_CLEAR_RXCMD_INFO_8822B(x) ((x) & (~BITS_RXCMD_INFO_8822B))
+#define BIT_GET_RXCMD_INFO_8822B(x) \
+ (((x) >> BIT_SHIFT_RXCMD_INFO_8822B) & BIT_MASK_RXCMD_INFO_8822B)
+#define BIT_SET_RXCMD_INFO_8822B(x, v) \
+ (BIT_CLEAR_RXCMD_INFO_8822B(x) | BIT_RXCMD_INFO_8822B(v))
/* 2 REG_RXCMD_1_8822B */
#define BIT_SHIFT_RXCMD_PRD_8822B 0
#define BIT_MASK_RXCMD_PRD_8822B 0xffff
-#define BIT_RXCMD_PRD_8822B(x) (((x) & BIT_MASK_RXCMD_PRD_8822B) << BIT_SHIFT_RXCMD_PRD_8822B)
-#define BIT_GET_RXCMD_PRD_8822B(x) (((x) >> BIT_SHIFT_RXCMD_PRD_8822B) & BIT_MASK_RXCMD_PRD_8822B)
-
+#define BIT_RXCMD_PRD_8822B(x) \
+ (((x) & BIT_MASK_RXCMD_PRD_8822B) << BIT_SHIFT_RXCMD_PRD_8822B)
+#define BITS_RXCMD_PRD_8822B \
+ (BIT_MASK_RXCMD_PRD_8822B << BIT_SHIFT_RXCMD_PRD_8822B)
+#define BIT_CLEAR_RXCMD_PRD_8822B(x) ((x) & (~BITS_RXCMD_PRD_8822B))
+#define BIT_GET_RXCMD_PRD_8822B(x) \
+ (((x) >> BIT_SHIFT_RXCMD_PRD_8822B) & BIT_MASK_RXCMD_PRD_8822B)
+#define BIT_SET_RXCMD_PRD_8822B(x, v) \
+ (BIT_CLEAR_RXCMD_PRD_8822B(x) | BIT_RXCMD_PRD_8822B(v))
/* 2 REG_NOT_VALID_8822B */
@@ -8496,33 +14897,74 @@
#define BIT_SHIFT_WMAC_RESP_MFB_8822B 25
#define BIT_MASK_WMAC_RESP_MFB_8822B 0x7f
-#define BIT_WMAC_RESP_MFB_8822B(x) (((x) & BIT_MASK_WMAC_RESP_MFB_8822B) << BIT_SHIFT_WMAC_RESP_MFB_8822B)
-#define BIT_GET_WMAC_RESP_MFB_8822B(x) (((x) >> BIT_SHIFT_WMAC_RESP_MFB_8822B) & BIT_MASK_WMAC_RESP_MFB_8822B)
-
+#define BIT_WMAC_RESP_MFB_8822B(x) \
+ (((x) & BIT_MASK_WMAC_RESP_MFB_8822B) << BIT_SHIFT_WMAC_RESP_MFB_8822B)
+#define BITS_WMAC_RESP_MFB_8822B \
+ (BIT_MASK_WMAC_RESP_MFB_8822B << BIT_SHIFT_WMAC_RESP_MFB_8822B)
+#define BIT_CLEAR_WMAC_RESP_MFB_8822B(x) ((x) & (~BITS_WMAC_RESP_MFB_8822B))
+#define BIT_GET_WMAC_RESP_MFB_8822B(x) \
+ (((x) >> BIT_SHIFT_WMAC_RESP_MFB_8822B) & BIT_MASK_WMAC_RESP_MFB_8822B)
+#define BIT_SET_WMAC_RESP_MFB_8822B(x, v) \
+ (BIT_CLEAR_WMAC_RESP_MFB_8822B(x) | BIT_WMAC_RESP_MFB_8822B(v))
#define BIT_SHIFT_WMAC_ANTINF_SEL_8822B 23
#define BIT_MASK_WMAC_ANTINF_SEL_8822B 0x3
-#define BIT_WMAC_ANTINF_SEL_8822B(x) (((x) & BIT_MASK_WMAC_ANTINF_SEL_8822B) << BIT_SHIFT_WMAC_ANTINF_SEL_8822B)
-#define BIT_GET_WMAC_ANTINF_SEL_8822B(x) (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8822B) & BIT_MASK_WMAC_ANTINF_SEL_8822B)
-
+#define BIT_WMAC_ANTINF_SEL_8822B(x) \
+ (((x) & BIT_MASK_WMAC_ANTINF_SEL_8822B) \
+ << BIT_SHIFT_WMAC_ANTINF_SEL_8822B)
+#define BITS_WMAC_ANTINF_SEL_8822B \
+ (BIT_MASK_WMAC_ANTINF_SEL_8822B << BIT_SHIFT_WMAC_ANTINF_SEL_8822B)
+#define BIT_CLEAR_WMAC_ANTINF_SEL_8822B(x) ((x) & (~BITS_WMAC_ANTINF_SEL_8822B))
+#define BIT_GET_WMAC_ANTINF_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8822B) & \
+ BIT_MASK_WMAC_ANTINF_SEL_8822B)
+#define BIT_SET_WMAC_ANTINF_SEL_8822B(x, v) \
+ (BIT_CLEAR_WMAC_ANTINF_SEL_8822B(x) | BIT_WMAC_ANTINF_SEL_8822B(v))
#define BIT_SHIFT_WMAC_ANTSEL_SEL_8822B 21
#define BIT_MASK_WMAC_ANTSEL_SEL_8822B 0x3
-#define BIT_WMAC_ANTSEL_SEL_8822B(x) (((x) & BIT_MASK_WMAC_ANTSEL_SEL_8822B) << BIT_SHIFT_WMAC_ANTSEL_SEL_8822B)
-#define BIT_GET_WMAC_ANTSEL_SEL_8822B(x) (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8822B) & BIT_MASK_WMAC_ANTSEL_SEL_8822B)
-
+#define BIT_WMAC_ANTSEL_SEL_8822B(x) \
+ (((x) & BIT_MASK_WMAC_ANTSEL_SEL_8822B) \
+ << BIT_SHIFT_WMAC_ANTSEL_SEL_8822B)
+#define BITS_WMAC_ANTSEL_SEL_8822B \
+ (BIT_MASK_WMAC_ANTSEL_SEL_8822B << BIT_SHIFT_WMAC_ANTSEL_SEL_8822B)
+#define BIT_CLEAR_WMAC_ANTSEL_SEL_8822B(x) ((x) & (~BITS_WMAC_ANTSEL_SEL_8822B))
+#define BIT_GET_WMAC_ANTSEL_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8822B) & \
+ BIT_MASK_WMAC_ANTSEL_SEL_8822B)
+#define BIT_SET_WMAC_ANTSEL_SEL_8822B(x, v) \
+ (BIT_CLEAR_WMAC_ANTSEL_SEL_8822B(x) | BIT_WMAC_ANTSEL_SEL_8822B(v))
#define BIT_SHIFT_R_WMAC_RESP_TXPOWER_8822B 18
#define BIT_MASK_R_WMAC_RESP_TXPOWER_8822B 0x7
-#define BIT_R_WMAC_RESP_TXPOWER_8822B(x) (((x) & BIT_MASK_R_WMAC_RESP_TXPOWER_8822B) << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8822B)
-#define BIT_GET_R_WMAC_RESP_TXPOWER_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER_8822B) & BIT_MASK_R_WMAC_RESP_TXPOWER_8822B)
-
+#define BIT_R_WMAC_RESP_TXPOWER_8822B(x) \
+ (((x) & BIT_MASK_R_WMAC_RESP_TXPOWER_8822B) \
+ << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8822B)
+#define BITS_R_WMAC_RESP_TXPOWER_8822B \
+ (BIT_MASK_R_WMAC_RESP_TXPOWER_8822B \
+ << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8822B)
+#define BIT_CLEAR_R_WMAC_RESP_TXPOWER_8822B(x) \
+ ((x) & (~BITS_R_WMAC_RESP_TXPOWER_8822B))
+#define BIT_GET_R_WMAC_RESP_TXPOWER_8822B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER_8822B) & \
+ BIT_MASK_R_WMAC_RESP_TXPOWER_8822B)
+#define BIT_SET_R_WMAC_RESP_TXPOWER_8822B(x, v) \
+ (BIT_CLEAR_R_WMAC_RESP_TXPOWER_8822B(x) | \
+ BIT_R_WMAC_RESP_TXPOWER_8822B(v))
#define BIT_SHIFT_WMAC_RESP_TXANT_8822B 0
#define BIT_MASK_WMAC_RESP_TXANT_8822B 0x3ffff
-#define BIT_WMAC_RESP_TXANT_8822B(x) (((x) & BIT_MASK_WMAC_RESP_TXANT_8822B) << BIT_SHIFT_WMAC_RESP_TXANT_8822B)
-#define BIT_GET_WMAC_RESP_TXANT_8822B(x) (((x) >> BIT_SHIFT_WMAC_RESP_TXANT_8822B) & BIT_MASK_WMAC_RESP_TXANT_8822B)
-
+#define BIT_WMAC_RESP_TXANT_8822B(x) \
+ (((x) & BIT_MASK_WMAC_RESP_TXANT_8822B) \
+ << BIT_SHIFT_WMAC_RESP_TXANT_8822B)
+#define BITS_WMAC_RESP_TXANT_8822B \
+ (BIT_MASK_WMAC_RESP_TXANT_8822B << BIT_SHIFT_WMAC_RESP_TXANT_8822B)
+#define BIT_CLEAR_WMAC_RESP_TXANT_8822B(x) ((x) & (~BITS_WMAC_RESP_TXANT_8822B))
+#define BIT_GET_WMAC_RESP_TXANT_8822B(x) \
+ (((x) >> BIT_SHIFT_WMAC_RESP_TXANT_8822B) & \
+ BIT_MASK_WMAC_RESP_TXANT_8822B)
+#define BIT_SET_WMAC_RESP_TXANT_8822B(x, v) \
+ (BIT_CLEAR_WMAC_RESP_TXANT_8822B(x) | BIT_WMAC_RESP_TXANT_8822B(v))
/* 2 REG_BBPSF_CTRL_8822B */
#define BIT_CTL_IDLE_CLR_CSI_RPT_8822B BIT(31)
@@ -8530,14 +14972,30 @@
#define BIT_SHIFT_WMAC_CSI_RATE_8822B 24
#define BIT_MASK_WMAC_CSI_RATE_8822B 0x3f
-#define BIT_WMAC_CSI_RATE_8822B(x) (((x) & BIT_MASK_WMAC_CSI_RATE_8822B) << BIT_SHIFT_WMAC_CSI_RATE_8822B)
-#define BIT_GET_WMAC_CSI_RATE_8822B(x) (((x) >> BIT_SHIFT_WMAC_CSI_RATE_8822B) & BIT_MASK_WMAC_CSI_RATE_8822B)
-
+#define BIT_WMAC_CSI_RATE_8822B(x) \
+ (((x) & BIT_MASK_WMAC_CSI_RATE_8822B) << BIT_SHIFT_WMAC_CSI_RATE_8822B)
+#define BITS_WMAC_CSI_RATE_8822B \
+ (BIT_MASK_WMAC_CSI_RATE_8822B << BIT_SHIFT_WMAC_CSI_RATE_8822B)
+#define BIT_CLEAR_WMAC_CSI_RATE_8822B(x) ((x) & (~BITS_WMAC_CSI_RATE_8822B))
+#define BIT_GET_WMAC_CSI_RATE_8822B(x) \
+ (((x) >> BIT_SHIFT_WMAC_CSI_RATE_8822B) & BIT_MASK_WMAC_CSI_RATE_8822B)
+#define BIT_SET_WMAC_CSI_RATE_8822B(x, v) \
+ (BIT_CLEAR_WMAC_CSI_RATE_8822B(x) | BIT_WMAC_CSI_RATE_8822B(v))
#define BIT_SHIFT_WMAC_RESP_TXRATE_8822B 16
#define BIT_MASK_WMAC_RESP_TXRATE_8822B 0xff
-#define BIT_WMAC_RESP_TXRATE_8822B(x) (((x) & BIT_MASK_WMAC_RESP_TXRATE_8822B) << BIT_SHIFT_WMAC_RESP_TXRATE_8822B)
-#define BIT_GET_WMAC_RESP_TXRATE_8822B(x) (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8822B) & BIT_MASK_WMAC_RESP_TXRATE_8822B)
+#define BIT_WMAC_RESP_TXRATE_8822B(x) \
+ (((x) & BIT_MASK_WMAC_RESP_TXRATE_8822B) \
+ << BIT_SHIFT_WMAC_RESP_TXRATE_8822B)
+#define BITS_WMAC_RESP_TXRATE_8822B \
+ (BIT_MASK_WMAC_RESP_TXRATE_8822B << BIT_SHIFT_WMAC_RESP_TXRATE_8822B)
+#define BIT_CLEAR_WMAC_RESP_TXRATE_8822B(x) \
+ ((x) & (~BITS_WMAC_RESP_TXRATE_8822B))
+#define BIT_GET_WMAC_RESP_TXRATE_8822B(x) \
+ (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8822B) & \
+ BIT_MASK_WMAC_RESP_TXRATE_8822B)
+#define BIT_SET_WMAC_RESP_TXRATE_8822B(x, v) \
+ (BIT_CLEAR_WMAC_RESP_TXRATE_8822B(x) | BIT_WMAC_RESP_TXRATE_8822B(v))
#define BIT_BBPSF_MPDUCHKEN_8822B BIT(5)
#define BIT_BBPSF_MHCHKEN_8822B BIT(4)
@@ -8545,9 +15003,15 @@
#define BIT_SHIFT_BBPSF_ERRTHR_8822B 0
#define BIT_MASK_BBPSF_ERRTHR_8822B 0x7
-#define BIT_BBPSF_ERRTHR_8822B(x) (((x) & BIT_MASK_BBPSF_ERRTHR_8822B) << BIT_SHIFT_BBPSF_ERRTHR_8822B)
-#define BIT_GET_BBPSF_ERRTHR_8822B(x) (((x) >> BIT_SHIFT_BBPSF_ERRTHR_8822B) & BIT_MASK_BBPSF_ERRTHR_8822B)
-
+#define BIT_BBPSF_ERRTHR_8822B(x) \
+ (((x) & BIT_MASK_BBPSF_ERRTHR_8822B) << BIT_SHIFT_BBPSF_ERRTHR_8822B)
+#define BITS_BBPSF_ERRTHR_8822B \
+ (BIT_MASK_BBPSF_ERRTHR_8822B << BIT_SHIFT_BBPSF_ERRTHR_8822B)
+#define BIT_CLEAR_BBPSF_ERRTHR_8822B(x) ((x) & (~BITS_BBPSF_ERRTHR_8822B))
+#define BIT_GET_BBPSF_ERRTHR_8822B(x) \
+ (((x) >> BIT_SHIFT_BBPSF_ERRTHR_8822B) & BIT_MASK_BBPSF_ERRTHR_8822B)
+#define BIT_SET_BBPSF_ERRTHR_8822B(x, v) \
+ (BIT_CLEAR_BBPSF_ERRTHR_8822B(x) | BIT_BBPSF_ERRTHR_8822B(v))
/* 2 REG_NOT_VALID_8822B */
@@ -8557,59 +15021,135 @@
#define BIT_SHIFT_P2P_OUI_TYPE_8822B 0
#define BIT_MASK_P2P_OUI_TYPE_8822B 0xff
-#define BIT_P2P_OUI_TYPE_8822B(x) (((x) & BIT_MASK_P2P_OUI_TYPE_8822B) << BIT_SHIFT_P2P_OUI_TYPE_8822B)
-#define BIT_GET_P2P_OUI_TYPE_8822B(x) (((x) >> BIT_SHIFT_P2P_OUI_TYPE_8822B) & BIT_MASK_P2P_OUI_TYPE_8822B)
-
+#define BIT_P2P_OUI_TYPE_8822B(x) \
+ (((x) & BIT_MASK_P2P_OUI_TYPE_8822B) << BIT_SHIFT_P2P_OUI_TYPE_8822B)
+#define BITS_P2P_OUI_TYPE_8822B \
+ (BIT_MASK_P2P_OUI_TYPE_8822B << BIT_SHIFT_P2P_OUI_TYPE_8822B)
+#define BIT_CLEAR_P2P_OUI_TYPE_8822B(x) ((x) & (~BITS_P2P_OUI_TYPE_8822B))
+#define BIT_GET_P2P_OUI_TYPE_8822B(x) \
+ (((x) >> BIT_SHIFT_P2P_OUI_TYPE_8822B) & BIT_MASK_P2P_OUI_TYPE_8822B)
+#define BIT_SET_P2P_OUI_TYPE_8822B(x, v) \
+ (BIT_CLEAR_P2P_OUI_TYPE_8822B(x) | BIT_P2P_OUI_TYPE_8822B(v))
/* 2 REG_ASSOCIATED_BFMER0_INFO_8822B (ASSOCIATED BEAMFORMER0 INFO REGISTER) */
#define BIT_SHIFT_R_WMAC_TXCSI_AID0_8822B (48 & CPU_OPT_WIDTH)
#define BIT_MASK_R_WMAC_TXCSI_AID0_8822B 0x1ff
-#define BIT_R_WMAC_TXCSI_AID0_8822B(x) (((x) & BIT_MASK_R_WMAC_TXCSI_AID0_8822B) << BIT_SHIFT_R_WMAC_TXCSI_AID0_8822B)
-#define BIT_GET_R_WMAC_TXCSI_AID0_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8822B) & BIT_MASK_R_WMAC_TXCSI_AID0_8822B)
-
+#define BIT_R_WMAC_TXCSI_AID0_8822B(x) \
+ (((x) & BIT_MASK_R_WMAC_TXCSI_AID0_8822B) \
+ << BIT_SHIFT_R_WMAC_TXCSI_AID0_8822B)
+#define BITS_R_WMAC_TXCSI_AID0_8822B \
+ (BIT_MASK_R_WMAC_TXCSI_AID0_8822B << BIT_SHIFT_R_WMAC_TXCSI_AID0_8822B)
+#define BIT_CLEAR_R_WMAC_TXCSI_AID0_8822B(x) \
+ ((x) & (~BITS_R_WMAC_TXCSI_AID0_8822B))
+#define BIT_GET_R_WMAC_TXCSI_AID0_8822B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8822B) & \
+ BIT_MASK_R_WMAC_TXCSI_AID0_8822B)
+#define BIT_SET_R_WMAC_TXCSI_AID0_8822B(x, v) \
+ (BIT_CLEAR_R_WMAC_TXCSI_AID0_8822B(x) | BIT_R_WMAC_TXCSI_AID0_8822B(v))
#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8822B 0
#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8822B 0xffffffffffffL
-#define BIT_R_WMAC_SOUNDING_RXADD_R0_8822B(x) (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8822B) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8822B)
-#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8822B) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8822B)
-
+#define BIT_R_WMAC_SOUNDING_RXADD_R0_8822B(x) \
+ (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8822B) \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8822B)
+#define BITS_R_WMAC_SOUNDING_RXADD_R0_8822B \
+ (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8822B \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8822B)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_8822B(x) \
+ ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_8822B))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_8822B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8822B) & \
+ BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8822B)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_8822B(x, v) \
+ (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_8822B(x) | \
+ BIT_R_WMAC_SOUNDING_RXADD_R0_8822B(v))
/* 2 REG_ASSOCIATED_BFMER1_INFO_8822B (ASSOCIATED BEAMFORMER1 INFO REGISTER) */
#define BIT_SHIFT_R_WMAC_TXCSI_AID1_8822B (48 & CPU_OPT_WIDTH)
#define BIT_MASK_R_WMAC_TXCSI_AID1_8822B 0x1ff
-#define BIT_R_WMAC_TXCSI_AID1_8822B(x) (((x) & BIT_MASK_R_WMAC_TXCSI_AID1_8822B) << BIT_SHIFT_R_WMAC_TXCSI_AID1_8822B)
-#define BIT_GET_R_WMAC_TXCSI_AID1_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8822B) & BIT_MASK_R_WMAC_TXCSI_AID1_8822B)
-
+#define BIT_R_WMAC_TXCSI_AID1_8822B(x) \
+ (((x) & BIT_MASK_R_WMAC_TXCSI_AID1_8822B) \
+ << BIT_SHIFT_R_WMAC_TXCSI_AID1_8822B)
+#define BITS_R_WMAC_TXCSI_AID1_8822B \
+ (BIT_MASK_R_WMAC_TXCSI_AID1_8822B << BIT_SHIFT_R_WMAC_TXCSI_AID1_8822B)
+#define BIT_CLEAR_R_WMAC_TXCSI_AID1_8822B(x) \
+ ((x) & (~BITS_R_WMAC_TXCSI_AID1_8822B))
+#define BIT_GET_R_WMAC_TXCSI_AID1_8822B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8822B) & \
+ BIT_MASK_R_WMAC_TXCSI_AID1_8822B)
+#define BIT_SET_R_WMAC_TXCSI_AID1_8822B(x, v) \
+ (BIT_CLEAR_R_WMAC_TXCSI_AID1_8822B(x) | BIT_R_WMAC_TXCSI_AID1_8822B(v))
#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8822B 0
#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8822B 0xffffffffffffL
-#define BIT_R_WMAC_SOUNDING_RXADD_R1_8822B(x) (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8822B) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8822B)
-#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8822B) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8822B)
-
+#define BIT_R_WMAC_SOUNDING_RXADD_R1_8822B(x) \
+ (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8822B) \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8822B)
+#define BITS_R_WMAC_SOUNDING_RXADD_R1_8822B \
+ (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8822B \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8822B)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_8822B(x) \
+ ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_8822B))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_8822B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8822B) & \
+ BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8822B)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_8822B(x, v) \
+ (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_8822B(x) | \
+ BIT_R_WMAC_SOUNDING_RXADD_R1_8822B(v))
/* 2 REG_TX_CSI_RPT_PARAM_BW20_8822B (TX CSI REPORT PARAMETER REGISTER) */
#define BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822B 16
#define BIT_MASK_R_WMAC_BFINFO_20M_1_8822B 0xfff
-#define BIT_R_WMAC_BFINFO_20M_1_8822B(x) (((x) & BIT_MASK_R_WMAC_BFINFO_20M_1_8822B) << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822B)
-#define BIT_GET_R_WMAC_BFINFO_20M_1_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822B) & BIT_MASK_R_WMAC_BFINFO_20M_1_8822B)
-
+#define BIT_R_WMAC_BFINFO_20M_1_8822B(x) \
+ (((x) & BIT_MASK_R_WMAC_BFINFO_20M_1_8822B) \
+ << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822B)
+#define BITS_R_WMAC_BFINFO_20M_1_8822B \
+ (BIT_MASK_R_WMAC_BFINFO_20M_1_8822B \
+ << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822B)
+#define BIT_CLEAR_R_WMAC_BFINFO_20M_1_8822B(x) \
+ ((x) & (~BITS_R_WMAC_BFINFO_20M_1_8822B))
+#define BIT_GET_R_WMAC_BFINFO_20M_1_8822B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822B) & \
+ BIT_MASK_R_WMAC_BFINFO_20M_1_8822B)
+#define BIT_SET_R_WMAC_BFINFO_20M_1_8822B(x, v) \
+ (BIT_CLEAR_R_WMAC_BFINFO_20M_1_8822B(x) | \
+ BIT_R_WMAC_BFINFO_20M_1_8822B(v))
#define BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822B 0
#define BIT_MASK_R_WMAC_BFINFO_20M_0_8822B 0xfff
-#define BIT_R_WMAC_BFINFO_20M_0_8822B(x) (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8822B) << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822B)
-#define BIT_GET_R_WMAC_BFINFO_20M_0_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822B) & BIT_MASK_R_WMAC_BFINFO_20M_0_8822B)
-
+#define BIT_R_WMAC_BFINFO_20M_0_8822B(x) \
+ (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8822B) \
+ << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822B)
+#define BITS_R_WMAC_BFINFO_20M_0_8822B \
+ (BIT_MASK_R_WMAC_BFINFO_20M_0_8822B \
+ << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822B)
+#define BIT_CLEAR_R_WMAC_BFINFO_20M_0_8822B(x) \
+ ((x) & (~BITS_R_WMAC_BFINFO_20M_0_8822B))
+#define BIT_GET_R_WMAC_BFINFO_20M_0_8822B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822B) & \
+ BIT_MASK_R_WMAC_BFINFO_20M_0_8822B)
+#define BIT_SET_R_WMAC_BFINFO_20M_0_8822B(x, v) \
+ (BIT_CLEAR_R_WMAC_BFINFO_20M_0_8822B(x) | \
+ BIT_R_WMAC_BFINFO_20M_0_8822B(v))
/* 2 REG_TX_CSI_RPT_PARAM_BW40_8822B (TX CSI REPORT PARAMETER_BW40 REGISTER) */
#define BIT_SHIFT_WMAC_RESP_ANTCD_8822B 0
#define BIT_MASK_WMAC_RESP_ANTCD_8822B 0xf
-#define BIT_WMAC_RESP_ANTCD_8822B(x) (((x) & BIT_MASK_WMAC_RESP_ANTCD_8822B) << BIT_SHIFT_WMAC_RESP_ANTCD_8822B)
-#define BIT_GET_WMAC_RESP_ANTCD_8822B(x) (((x) >> BIT_SHIFT_WMAC_RESP_ANTCD_8822B) & BIT_MASK_WMAC_RESP_ANTCD_8822B)
-
+#define BIT_WMAC_RESP_ANTCD_8822B(x) \
+ (((x) & BIT_MASK_WMAC_RESP_ANTCD_8822B) \
+ << BIT_SHIFT_WMAC_RESP_ANTCD_8822B)
+#define BITS_WMAC_RESP_ANTCD_8822B \
+ (BIT_MASK_WMAC_RESP_ANTCD_8822B << BIT_SHIFT_WMAC_RESP_ANTCD_8822B)
+#define BIT_CLEAR_WMAC_RESP_ANTCD_8822B(x) ((x) & (~BITS_WMAC_RESP_ANTCD_8822B))
+#define BIT_GET_WMAC_RESP_ANTCD_8822B(x) \
+ (((x) >> BIT_SHIFT_WMAC_RESP_ANTCD_8822B) & \
+ BIT_MASK_WMAC_RESP_ANTCD_8822B)
+#define BIT_SET_WMAC_RESP_ANTCD_8822B(x, v) \
+ (BIT_CLEAR_WMAC_RESP_ANTCD_8822B(x) | BIT_WMAC_RESP_ANTCD_8822B(v))
/* 2 REG_TX_CSI_RPT_PARAM_BW80_8822B (TX CSI REPORT PARAMETER_BW80 REGISTER) */
@@ -8617,123 +15157,216 @@
#define BIT_SHIFT_DTIM_CNT2_8822B 24
#define BIT_MASK_DTIM_CNT2_8822B 0xff
-#define BIT_DTIM_CNT2_8822B(x) (((x) & BIT_MASK_DTIM_CNT2_8822B) << BIT_SHIFT_DTIM_CNT2_8822B)
-#define BIT_GET_DTIM_CNT2_8822B(x) (((x) >> BIT_SHIFT_DTIM_CNT2_8822B) & BIT_MASK_DTIM_CNT2_8822B)
-
+#define BIT_DTIM_CNT2_8822B(x) \
+ (((x) & BIT_MASK_DTIM_CNT2_8822B) << BIT_SHIFT_DTIM_CNT2_8822B)
+#define BITS_DTIM_CNT2_8822B \
+ (BIT_MASK_DTIM_CNT2_8822B << BIT_SHIFT_DTIM_CNT2_8822B)
+#define BIT_CLEAR_DTIM_CNT2_8822B(x) ((x) & (~BITS_DTIM_CNT2_8822B))
+#define BIT_GET_DTIM_CNT2_8822B(x) \
+ (((x) >> BIT_SHIFT_DTIM_CNT2_8822B) & BIT_MASK_DTIM_CNT2_8822B)
+#define BIT_SET_DTIM_CNT2_8822B(x, v) \
+ (BIT_CLEAR_DTIM_CNT2_8822B(x) | BIT_DTIM_CNT2_8822B(v))
#define BIT_SHIFT_DTIM_PERIOD2_8822B 16
#define BIT_MASK_DTIM_PERIOD2_8822B 0xff
-#define BIT_DTIM_PERIOD2_8822B(x) (((x) & BIT_MASK_DTIM_PERIOD2_8822B) << BIT_SHIFT_DTIM_PERIOD2_8822B)
-#define BIT_GET_DTIM_PERIOD2_8822B(x) (((x) >> BIT_SHIFT_DTIM_PERIOD2_8822B) & BIT_MASK_DTIM_PERIOD2_8822B)
+#define BIT_DTIM_PERIOD2_8822B(x) \
+ (((x) & BIT_MASK_DTIM_PERIOD2_8822B) << BIT_SHIFT_DTIM_PERIOD2_8822B)
+#define BITS_DTIM_PERIOD2_8822B \
+ (BIT_MASK_DTIM_PERIOD2_8822B << BIT_SHIFT_DTIM_PERIOD2_8822B)
+#define BIT_CLEAR_DTIM_PERIOD2_8822B(x) ((x) & (~BITS_DTIM_PERIOD2_8822B))
+#define BIT_GET_DTIM_PERIOD2_8822B(x) \
+ (((x) >> BIT_SHIFT_DTIM_PERIOD2_8822B) & BIT_MASK_DTIM_PERIOD2_8822B)
+#define BIT_SET_DTIM_PERIOD2_8822B(x, v) \
+ (BIT_CLEAR_DTIM_PERIOD2_8822B(x) | BIT_DTIM_PERIOD2_8822B(v))
#define BIT_DTIM2_8822B BIT(15)
#define BIT_TIM2_8822B BIT(14)
#define BIT_SHIFT_PS_AID_2_8822B 0
#define BIT_MASK_PS_AID_2_8822B 0x7ff
-#define BIT_PS_AID_2_8822B(x) (((x) & BIT_MASK_PS_AID_2_8822B) << BIT_SHIFT_PS_AID_2_8822B)
-#define BIT_GET_PS_AID_2_8822B(x) (((x) >> BIT_SHIFT_PS_AID_2_8822B) & BIT_MASK_PS_AID_2_8822B)
-
+#define BIT_PS_AID_2_8822B(x) \
+ (((x) & BIT_MASK_PS_AID_2_8822B) << BIT_SHIFT_PS_AID_2_8822B)
+#define BITS_PS_AID_2_8822B \
+ (BIT_MASK_PS_AID_2_8822B << BIT_SHIFT_PS_AID_2_8822B)
+#define BIT_CLEAR_PS_AID_2_8822B(x) ((x) & (~BITS_PS_AID_2_8822B))
+#define BIT_GET_PS_AID_2_8822B(x) \
+ (((x) >> BIT_SHIFT_PS_AID_2_8822B) & BIT_MASK_PS_AID_2_8822B)
+#define BIT_SET_PS_AID_2_8822B(x, v) \
+ (BIT_CLEAR_PS_AID_2_8822B(x) | BIT_PS_AID_2_8822B(v))
/* 2 REG_BCN_PSR_RPT3_8822B (BEACON PARSER REPORT REGISTER3) */
#define BIT_SHIFT_DTIM_CNT3_8822B 24
#define BIT_MASK_DTIM_CNT3_8822B 0xff
-#define BIT_DTIM_CNT3_8822B(x) (((x) & BIT_MASK_DTIM_CNT3_8822B) << BIT_SHIFT_DTIM_CNT3_8822B)
-#define BIT_GET_DTIM_CNT3_8822B(x) (((x) >> BIT_SHIFT_DTIM_CNT3_8822B) & BIT_MASK_DTIM_CNT3_8822B)
-
+#define BIT_DTIM_CNT3_8822B(x) \
+ (((x) & BIT_MASK_DTIM_CNT3_8822B) << BIT_SHIFT_DTIM_CNT3_8822B)
+#define BITS_DTIM_CNT3_8822B \
+ (BIT_MASK_DTIM_CNT3_8822B << BIT_SHIFT_DTIM_CNT3_8822B)
+#define BIT_CLEAR_DTIM_CNT3_8822B(x) ((x) & (~BITS_DTIM_CNT3_8822B))
+#define BIT_GET_DTIM_CNT3_8822B(x) \
+ (((x) >> BIT_SHIFT_DTIM_CNT3_8822B) & BIT_MASK_DTIM_CNT3_8822B)
+#define BIT_SET_DTIM_CNT3_8822B(x, v) \
+ (BIT_CLEAR_DTIM_CNT3_8822B(x) | BIT_DTIM_CNT3_8822B(v))
#define BIT_SHIFT_DTIM_PERIOD3_8822B 16
#define BIT_MASK_DTIM_PERIOD3_8822B 0xff
-#define BIT_DTIM_PERIOD3_8822B(x) (((x) & BIT_MASK_DTIM_PERIOD3_8822B) << BIT_SHIFT_DTIM_PERIOD3_8822B)
-#define BIT_GET_DTIM_PERIOD3_8822B(x) (((x) >> BIT_SHIFT_DTIM_PERIOD3_8822B) & BIT_MASK_DTIM_PERIOD3_8822B)
+#define BIT_DTIM_PERIOD3_8822B(x) \
+ (((x) & BIT_MASK_DTIM_PERIOD3_8822B) << BIT_SHIFT_DTIM_PERIOD3_8822B)
+#define BITS_DTIM_PERIOD3_8822B \
+ (BIT_MASK_DTIM_PERIOD3_8822B << BIT_SHIFT_DTIM_PERIOD3_8822B)
+#define BIT_CLEAR_DTIM_PERIOD3_8822B(x) ((x) & (~BITS_DTIM_PERIOD3_8822B))
+#define BIT_GET_DTIM_PERIOD3_8822B(x) \
+ (((x) >> BIT_SHIFT_DTIM_PERIOD3_8822B) & BIT_MASK_DTIM_PERIOD3_8822B)
+#define BIT_SET_DTIM_PERIOD3_8822B(x, v) \
+ (BIT_CLEAR_DTIM_PERIOD3_8822B(x) | BIT_DTIM_PERIOD3_8822B(v))
#define BIT_DTIM3_8822B BIT(15)
#define BIT_TIM3_8822B BIT(14)
#define BIT_SHIFT_PS_AID_3_8822B 0
#define BIT_MASK_PS_AID_3_8822B 0x7ff
-#define BIT_PS_AID_3_8822B(x) (((x) & BIT_MASK_PS_AID_3_8822B) << BIT_SHIFT_PS_AID_3_8822B)
-#define BIT_GET_PS_AID_3_8822B(x) (((x) >> BIT_SHIFT_PS_AID_3_8822B) & BIT_MASK_PS_AID_3_8822B)
-
+#define BIT_PS_AID_3_8822B(x) \
+ (((x) & BIT_MASK_PS_AID_3_8822B) << BIT_SHIFT_PS_AID_3_8822B)
+#define BITS_PS_AID_3_8822B \
+ (BIT_MASK_PS_AID_3_8822B << BIT_SHIFT_PS_AID_3_8822B)
+#define BIT_CLEAR_PS_AID_3_8822B(x) ((x) & (~BITS_PS_AID_3_8822B))
+#define BIT_GET_PS_AID_3_8822B(x) \
+ (((x) >> BIT_SHIFT_PS_AID_3_8822B) & BIT_MASK_PS_AID_3_8822B)
+#define BIT_SET_PS_AID_3_8822B(x, v) \
+ (BIT_CLEAR_PS_AID_3_8822B(x) | BIT_PS_AID_3_8822B(v))
/* 2 REG_BCN_PSR_RPT4_8822B (BEACON PARSER REPORT REGISTER4) */
#define BIT_SHIFT_DTIM_CNT4_8822B 24
#define BIT_MASK_DTIM_CNT4_8822B 0xff
-#define BIT_DTIM_CNT4_8822B(x) (((x) & BIT_MASK_DTIM_CNT4_8822B) << BIT_SHIFT_DTIM_CNT4_8822B)
-#define BIT_GET_DTIM_CNT4_8822B(x) (((x) >> BIT_SHIFT_DTIM_CNT4_8822B) & BIT_MASK_DTIM_CNT4_8822B)
-
+#define BIT_DTIM_CNT4_8822B(x) \
+ (((x) & BIT_MASK_DTIM_CNT4_8822B) << BIT_SHIFT_DTIM_CNT4_8822B)
+#define BITS_DTIM_CNT4_8822B \
+ (BIT_MASK_DTIM_CNT4_8822B << BIT_SHIFT_DTIM_CNT4_8822B)
+#define BIT_CLEAR_DTIM_CNT4_8822B(x) ((x) & (~BITS_DTIM_CNT4_8822B))
+#define BIT_GET_DTIM_CNT4_8822B(x) \
+ (((x) >> BIT_SHIFT_DTIM_CNT4_8822B) & BIT_MASK_DTIM_CNT4_8822B)
+#define BIT_SET_DTIM_CNT4_8822B(x, v) \
+ (BIT_CLEAR_DTIM_CNT4_8822B(x) | BIT_DTIM_CNT4_8822B(v))
#define BIT_SHIFT_DTIM_PERIOD4_8822B 16
#define BIT_MASK_DTIM_PERIOD4_8822B 0xff
-#define BIT_DTIM_PERIOD4_8822B(x) (((x) & BIT_MASK_DTIM_PERIOD4_8822B) << BIT_SHIFT_DTIM_PERIOD4_8822B)
-#define BIT_GET_DTIM_PERIOD4_8822B(x) (((x) >> BIT_SHIFT_DTIM_PERIOD4_8822B) & BIT_MASK_DTIM_PERIOD4_8822B)
+#define BIT_DTIM_PERIOD4_8822B(x) \
+ (((x) & BIT_MASK_DTIM_PERIOD4_8822B) << BIT_SHIFT_DTIM_PERIOD4_8822B)
+#define BITS_DTIM_PERIOD4_8822B \
+ (BIT_MASK_DTIM_PERIOD4_8822B << BIT_SHIFT_DTIM_PERIOD4_8822B)
+#define BIT_CLEAR_DTIM_PERIOD4_8822B(x) ((x) & (~BITS_DTIM_PERIOD4_8822B))
+#define BIT_GET_DTIM_PERIOD4_8822B(x) \
+ (((x) >> BIT_SHIFT_DTIM_PERIOD4_8822B) & BIT_MASK_DTIM_PERIOD4_8822B)
+#define BIT_SET_DTIM_PERIOD4_8822B(x, v) \
+ (BIT_CLEAR_DTIM_PERIOD4_8822B(x) | BIT_DTIM_PERIOD4_8822B(v))
#define BIT_DTIM4_8822B BIT(15)
#define BIT_TIM4_8822B BIT(14)
#define BIT_SHIFT_PS_AID_4_8822B 0
#define BIT_MASK_PS_AID_4_8822B 0x7ff
-#define BIT_PS_AID_4_8822B(x) (((x) & BIT_MASK_PS_AID_4_8822B) << BIT_SHIFT_PS_AID_4_8822B)
-#define BIT_GET_PS_AID_4_8822B(x) (((x) >> BIT_SHIFT_PS_AID_4_8822B) & BIT_MASK_PS_AID_4_8822B)
-
+#define BIT_PS_AID_4_8822B(x) \
+ (((x) & BIT_MASK_PS_AID_4_8822B) << BIT_SHIFT_PS_AID_4_8822B)
+#define BITS_PS_AID_4_8822B \
+ (BIT_MASK_PS_AID_4_8822B << BIT_SHIFT_PS_AID_4_8822B)
+#define BIT_CLEAR_PS_AID_4_8822B(x) ((x) & (~BITS_PS_AID_4_8822B))
+#define BIT_GET_PS_AID_4_8822B(x) \
+ (((x) >> BIT_SHIFT_PS_AID_4_8822B) & BIT_MASK_PS_AID_4_8822B)
+#define BIT_SET_PS_AID_4_8822B(x, v) \
+ (BIT_CLEAR_PS_AID_4_8822B(x) | BIT_PS_AID_4_8822B(v))
/* 2 REG_A1_ADDR_MASK_8822B (A1 ADDR MASK REGISTER) */
#define BIT_SHIFT_A1_ADDR_MASK_8822B 0
#define BIT_MASK_A1_ADDR_MASK_8822B 0xffffffffL
-#define BIT_A1_ADDR_MASK_8822B(x) (((x) & BIT_MASK_A1_ADDR_MASK_8822B) << BIT_SHIFT_A1_ADDR_MASK_8822B)
-#define BIT_GET_A1_ADDR_MASK_8822B(x) (((x) >> BIT_SHIFT_A1_ADDR_MASK_8822B) & BIT_MASK_A1_ADDR_MASK_8822B)
-
+#define BIT_A1_ADDR_MASK_8822B(x) \
+ (((x) & BIT_MASK_A1_ADDR_MASK_8822B) << BIT_SHIFT_A1_ADDR_MASK_8822B)
+#define BITS_A1_ADDR_MASK_8822B \
+ (BIT_MASK_A1_ADDR_MASK_8822B << BIT_SHIFT_A1_ADDR_MASK_8822B)
+#define BIT_CLEAR_A1_ADDR_MASK_8822B(x) ((x) & (~BITS_A1_ADDR_MASK_8822B))
+#define BIT_GET_A1_ADDR_MASK_8822B(x) \
+ (((x) >> BIT_SHIFT_A1_ADDR_MASK_8822B) & BIT_MASK_A1_ADDR_MASK_8822B)
+#define BIT_SET_A1_ADDR_MASK_8822B(x, v) \
+ (BIT_CLEAR_A1_ADDR_MASK_8822B(x) | BIT_A1_ADDR_MASK_8822B(v))
/* 2 REG_MACID2_8822B (MAC ID2 REGISTER) */
#define BIT_SHIFT_MACID2_8822B 0
#define BIT_MASK_MACID2_8822B 0xffffffffffffL
-#define BIT_MACID2_8822B(x) (((x) & BIT_MASK_MACID2_8822B) << BIT_SHIFT_MACID2_8822B)
-#define BIT_GET_MACID2_8822B(x) (((x) >> BIT_SHIFT_MACID2_8822B) & BIT_MASK_MACID2_8822B)
-
+#define BIT_MACID2_8822B(x) \
+ (((x) & BIT_MASK_MACID2_8822B) << BIT_SHIFT_MACID2_8822B)
+#define BITS_MACID2_8822B (BIT_MASK_MACID2_8822B << BIT_SHIFT_MACID2_8822B)
+#define BIT_CLEAR_MACID2_8822B(x) ((x) & (~BITS_MACID2_8822B))
+#define BIT_GET_MACID2_8822B(x) \
+ (((x) >> BIT_SHIFT_MACID2_8822B) & BIT_MASK_MACID2_8822B)
+#define BIT_SET_MACID2_8822B(x, v) \
+ (BIT_CLEAR_MACID2_8822B(x) | BIT_MACID2_8822B(v))
/* 2 REG_BSSID2_8822B (BSSID2 REGISTER) */
#define BIT_SHIFT_BSSID2_8822B 0
#define BIT_MASK_BSSID2_8822B 0xffffffffffffL
-#define BIT_BSSID2_8822B(x) (((x) & BIT_MASK_BSSID2_8822B) << BIT_SHIFT_BSSID2_8822B)
-#define BIT_GET_BSSID2_8822B(x) (((x) >> BIT_SHIFT_BSSID2_8822B) & BIT_MASK_BSSID2_8822B)
-
+#define BIT_BSSID2_8822B(x) \
+ (((x) & BIT_MASK_BSSID2_8822B) << BIT_SHIFT_BSSID2_8822B)
+#define BITS_BSSID2_8822B (BIT_MASK_BSSID2_8822B << BIT_SHIFT_BSSID2_8822B)
+#define BIT_CLEAR_BSSID2_8822B(x) ((x) & (~BITS_BSSID2_8822B))
+#define BIT_GET_BSSID2_8822B(x) \
+ (((x) >> BIT_SHIFT_BSSID2_8822B) & BIT_MASK_BSSID2_8822B)
+#define BIT_SET_BSSID2_8822B(x, v) \
+ (BIT_CLEAR_BSSID2_8822B(x) | BIT_BSSID2_8822B(v))
/* 2 REG_MACID3_8822B (MAC ID3 REGISTER) */
#define BIT_SHIFT_MACID3_8822B 0
#define BIT_MASK_MACID3_8822B 0xffffffffffffL
-#define BIT_MACID3_8822B(x) (((x) & BIT_MASK_MACID3_8822B) << BIT_SHIFT_MACID3_8822B)
-#define BIT_GET_MACID3_8822B(x) (((x) >> BIT_SHIFT_MACID3_8822B) & BIT_MASK_MACID3_8822B)
-
+#define BIT_MACID3_8822B(x) \
+ (((x) & BIT_MASK_MACID3_8822B) << BIT_SHIFT_MACID3_8822B)
+#define BITS_MACID3_8822B (BIT_MASK_MACID3_8822B << BIT_SHIFT_MACID3_8822B)
+#define BIT_CLEAR_MACID3_8822B(x) ((x) & (~BITS_MACID3_8822B))
+#define BIT_GET_MACID3_8822B(x) \
+ (((x) >> BIT_SHIFT_MACID3_8822B) & BIT_MASK_MACID3_8822B)
+#define BIT_SET_MACID3_8822B(x, v) \
+ (BIT_CLEAR_MACID3_8822B(x) | BIT_MACID3_8822B(v))
/* 2 REG_BSSID3_8822B (BSSID3 REGISTER) */
#define BIT_SHIFT_BSSID3_8822B 0
#define BIT_MASK_BSSID3_8822B 0xffffffffffffL
-#define BIT_BSSID3_8822B(x) (((x) & BIT_MASK_BSSID3_8822B) << BIT_SHIFT_BSSID3_8822B)
-#define BIT_GET_BSSID3_8822B(x) (((x) >> BIT_SHIFT_BSSID3_8822B) & BIT_MASK_BSSID3_8822B)
-
+#define BIT_BSSID3_8822B(x) \
+ (((x) & BIT_MASK_BSSID3_8822B) << BIT_SHIFT_BSSID3_8822B)
+#define BITS_BSSID3_8822B (BIT_MASK_BSSID3_8822B << BIT_SHIFT_BSSID3_8822B)
+#define BIT_CLEAR_BSSID3_8822B(x) ((x) & (~BITS_BSSID3_8822B))
+#define BIT_GET_BSSID3_8822B(x) \
+ (((x) >> BIT_SHIFT_BSSID3_8822B) & BIT_MASK_BSSID3_8822B)
+#define BIT_SET_BSSID3_8822B(x, v) \
+ (BIT_CLEAR_BSSID3_8822B(x) | BIT_BSSID3_8822B(v))
/* 2 REG_MACID4_8822B (MAC ID4 REGISTER) */
#define BIT_SHIFT_MACID4_8822B 0
#define BIT_MASK_MACID4_8822B 0xffffffffffffL
-#define BIT_MACID4_8822B(x) (((x) & BIT_MASK_MACID4_8822B) << BIT_SHIFT_MACID4_8822B)
-#define BIT_GET_MACID4_8822B(x) (((x) >> BIT_SHIFT_MACID4_8822B) & BIT_MASK_MACID4_8822B)
-
+#define BIT_MACID4_8822B(x) \
+ (((x) & BIT_MASK_MACID4_8822B) << BIT_SHIFT_MACID4_8822B)
+#define BITS_MACID4_8822B (BIT_MASK_MACID4_8822B << BIT_SHIFT_MACID4_8822B)
+#define BIT_CLEAR_MACID4_8822B(x) ((x) & (~BITS_MACID4_8822B))
+#define BIT_GET_MACID4_8822B(x) \
+ (((x) >> BIT_SHIFT_MACID4_8822B) & BIT_MASK_MACID4_8822B)
+#define BIT_SET_MACID4_8822B(x, v) \
+ (BIT_CLEAR_MACID4_8822B(x) | BIT_MACID4_8822B(v))
/* 2 REG_BSSID4_8822B (BSSID4 REGISTER) */
#define BIT_SHIFT_BSSID4_8822B 0
#define BIT_MASK_BSSID4_8822B 0xffffffffffffL
-#define BIT_BSSID4_8822B(x) (((x) & BIT_MASK_BSSID4_8822B) << BIT_SHIFT_BSSID4_8822B)
-#define BIT_GET_BSSID4_8822B(x) (((x) >> BIT_SHIFT_BSSID4_8822B) & BIT_MASK_BSSID4_8822B)
-
+#define BIT_BSSID4_8822B(x) \
+ (((x) & BIT_MASK_BSSID4_8822B) << BIT_SHIFT_BSSID4_8822B)
+#define BITS_BSSID4_8822B (BIT_MASK_BSSID4_8822B << BIT_SHIFT_BSSID4_8822B)
+#define BIT_CLEAR_BSSID4_8822B(x) ((x) & (~BITS_BSSID4_8822B))
+#define BIT_GET_BSSID4_8822B(x) \
+ (((x) >> BIT_SHIFT_BSSID4_8822B) & BIT_MASK_BSSID4_8822B)
+#define BIT_SET_BSSID4_8822B(x, v) \
+ (BIT_CLEAR_BSSID4_8822B(x) | BIT_BSSID4_8822B(v))
/* 2 REG_NOA_REPORT_8822B */
@@ -8747,75 +15380,464 @@
#define BIT_CLI0_PWRBIT_OW_EN_8822B BIT(1)
#define BIT_CLI0_PWR_ST_8822B BIT(0)
-/* 2 REG_NOT_VALID_8822B */
-
-/* 2 REG_NOT_VALID_8822B */
-
-/* 2 REG_NOT_VALID_8822B */
-
-/* 2 REG_NOT_VALID_8822B */
-
-/* 2 REG_NOT_VALID_8822B */
-
-/* 2 REG_NOT_VALID_8822B */
-
-/* 2 REG_NOT_VALID_8822B */
-
-/* 2 REG_NOT_VALID_8822B */
-
-/* 2 REG_NOT_VALID_8822B */
-
-/* 2 REG_NOT_VALID_8822B */
+/* 2 REG_WMAC_MU_BF_OPTION_8822B */
+#define BIT_WMAC_RESP_NONSTA1_DIS_8822B BIT(7)
+#define BIT_BIT_WMAC_TXMU_ACKPOLICY_EN_8822B BIT(6)
+
+#define BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822B 4
+#define BIT_MASK_WMAC_TXMU_ACKPOLICY_8822B 0x3
+#define BIT_WMAC_TXMU_ACKPOLICY_8822B(x) \
+ (((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8822B) \
+ << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822B)
+#define BITS_WMAC_TXMU_ACKPOLICY_8822B \
+ (BIT_MASK_WMAC_TXMU_ACKPOLICY_8822B \
+ << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822B)
+#define BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8822B(x) \
+ ((x) & (~BITS_WMAC_TXMU_ACKPOLICY_8822B))
+#define BIT_GET_WMAC_TXMU_ACKPOLICY_8822B(x) \
+ (((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822B) & \
+ BIT_MASK_WMAC_TXMU_ACKPOLICY_8822B)
+#define BIT_SET_WMAC_TXMU_ACKPOLICY_8822B(x, v) \
+ (BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8822B(x) | \
+ BIT_WMAC_TXMU_ACKPOLICY_8822B(v))
+
+#define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822B 1
+#define BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822B 0x7
+#define BIT_WMAC_MU_BFEE_PORT_SEL_8822B(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822B) \
+ << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822B)
+#define BITS_WMAC_MU_BFEE_PORT_SEL_8822B \
+ (BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822B \
+ << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822B)
+#define BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8822B(x) \
+ ((x) & (~BITS_WMAC_MU_BFEE_PORT_SEL_8822B))
+#define BIT_GET_WMAC_MU_BFEE_PORT_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822B) & \
+ BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822B)
+#define BIT_SET_WMAC_MU_BFEE_PORT_SEL_8822B(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8822B(x) | \
+ BIT_WMAC_MU_BFEE_PORT_SEL_8822B(v))
+
+#define BIT_WMAC_MU_BFEE_DIS_8822B BIT(0)
/* 2 REG_NOT_VALID_8822B */
-/* 2 REG_NOT_VALID_8822B */
+#define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822B 0
+#define BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822B 0xff
+#define BIT_WMAC_PAUSE_BB_CLR_TH_8822B(x) \
+ (((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822B) \
+ << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822B)
+#define BITS_WMAC_PAUSE_BB_CLR_TH_8822B \
+ (BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822B \
+ << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822B)
+#define BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8822B(x) \
+ ((x) & (~BITS_WMAC_PAUSE_BB_CLR_TH_8822B))
+#define BIT_GET_WMAC_PAUSE_BB_CLR_TH_8822B(x) \
+ (((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822B) & \
+ BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822B)
+#define BIT_SET_WMAC_PAUSE_BB_CLR_TH_8822B(x, v) \
+ (BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8822B(x) | \
+ BIT_WMAC_PAUSE_BB_CLR_TH_8822B(v))
+
+/* 2 REG_WMAC_MU_ARB_8822B */
+#define BIT_WMAC_ARB_HW_ADAPT_EN_8822B BIT(7)
+#define BIT_WMAC_ARB_SW_EN_8822B BIT(6)
+
+#define BIT_SHIFT_WMAC_ARB_SW_STATE_8822B 0
+#define BIT_MASK_WMAC_ARB_SW_STATE_8822B 0x3f
+#define BIT_WMAC_ARB_SW_STATE_8822B(x) \
+ (((x) & BIT_MASK_WMAC_ARB_SW_STATE_8822B) \
+ << BIT_SHIFT_WMAC_ARB_SW_STATE_8822B)
+#define BITS_WMAC_ARB_SW_STATE_8822B \
+ (BIT_MASK_WMAC_ARB_SW_STATE_8822B << BIT_SHIFT_WMAC_ARB_SW_STATE_8822B)
+#define BIT_CLEAR_WMAC_ARB_SW_STATE_8822B(x) \
+ ((x) & (~BITS_WMAC_ARB_SW_STATE_8822B))
+#define BIT_GET_WMAC_ARB_SW_STATE_8822B(x) \
+ (((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE_8822B) & \
+ BIT_MASK_WMAC_ARB_SW_STATE_8822B)
+#define BIT_SET_WMAC_ARB_SW_STATE_8822B(x, v) \
+ (BIT_CLEAR_WMAC_ARB_SW_STATE_8822B(x) | BIT_WMAC_ARB_SW_STATE_8822B(v))
+
+/* 2 REG_WMAC_MU_OPTION_8822B */
+
+#define BIT_SHIFT_WMAC_MU_DBGSEL_8822B 5
+#define BIT_MASK_WMAC_MU_DBGSEL_8822B 0x3
+#define BIT_WMAC_MU_DBGSEL_8822B(x) \
+ (((x) & BIT_MASK_WMAC_MU_DBGSEL_8822B) \
+ << BIT_SHIFT_WMAC_MU_DBGSEL_8822B)
+#define BITS_WMAC_MU_DBGSEL_8822B \
+ (BIT_MASK_WMAC_MU_DBGSEL_8822B << BIT_SHIFT_WMAC_MU_DBGSEL_8822B)
+#define BIT_CLEAR_WMAC_MU_DBGSEL_8822B(x) ((x) & (~BITS_WMAC_MU_DBGSEL_8822B))
+#define BIT_GET_WMAC_MU_DBGSEL_8822B(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_8822B) & \
+ BIT_MASK_WMAC_MU_DBGSEL_8822B)
+#define BIT_SET_WMAC_MU_DBGSEL_8822B(x, v) \
+ (BIT_CLEAR_WMAC_MU_DBGSEL_8822B(x) | BIT_WMAC_MU_DBGSEL_8822B(v))
+
+#define BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8822B 0
+#define BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8822B 0x1f
+#define BIT_WMAC_MU_CPRD_TIMEOUT_8822B(x) \
+ (((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8822B) \
+ << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8822B)
+#define BITS_WMAC_MU_CPRD_TIMEOUT_8822B \
+ (BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8822B \
+ << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8822B)
+#define BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT_8822B(x) \
+ ((x) & (~BITS_WMAC_MU_CPRD_TIMEOUT_8822B))
+#define BIT_GET_WMAC_MU_CPRD_TIMEOUT_8822B(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8822B) & \
+ BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8822B)
+#define BIT_SET_WMAC_MU_CPRD_TIMEOUT_8822B(x, v) \
+ (BIT_CLEAR_WMAC_MU_CPRD_TIMEOUT_8822B(x) | \
+ BIT_WMAC_MU_CPRD_TIMEOUT_8822B(v))
+
+/* 2 REG_WMAC_MU_BF_CTL_8822B */
+#define BIT_WMAC_INVLD_BFPRT_CHK_8822B BIT(15)
+#define BIT_WMAC_RETXBFRPTSEQ_UPD_8822B BIT(14)
+
+#define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822B 12
+#define BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822B 0x3
+#define BIT_WMAC_MU_BFRPTSEG_SEL_8822B(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822B) \
+ << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822B)
+#define BITS_WMAC_MU_BFRPTSEG_SEL_8822B \
+ (BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822B \
+ << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822B)
+#define BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8822B(x) \
+ ((x) & (~BITS_WMAC_MU_BFRPTSEG_SEL_8822B))
+#define BIT_GET_WMAC_MU_BFRPTSEG_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822B) & \
+ BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822B)
+#define BIT_SET_WMAC_MU_BFRPTSEG_SEL_8822B(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8822B(x) | \
+ BIT_WMAC_MU_BFRPTSEG_SEL_8822B(v))
+
+#define BIT_SHIFT_WMAC_MU_BF_MYAID_8822B 0
+#define BIT_MASK_WMAC_MU_BF_MYAID_8822B 0xfff
+#define BIT_WMAC_MU_BF_MYAID_8822B(x) \
+ (((x) & BIT_MASK_WMAC_MU_BF_MYAID_8822B) \
+ << BIT_SHIFT_WMAC_MU_BF_MYAID_8822B)
+#define BITS_WMAC_MU_BF_MYAID_8822B \
+ (BIT_MASK_WMAC_MU_BF_MYAID_8822B << BIT_SHIFT_WMAC_MU_BF_MYAID_8822B)
+#define BIT_CLEAR_WMAC_MU_BF_MYAID_8822B(x) \
+ ((x) & (~BITS_WMAC_MU_BF_MYAID_8822B))
+#define BIT_GET_WMAC_MU_BF_MYAID_8822B(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID_8822B) & \
+ BIT_MASK_WMAC_MU_BF_MYAID_8822B)
+#define BIT_SET_WMAC_MU_BF_MYAID_8822B(x, v) \
+ (BIT_CLEAR_WMAC_MU_BF_MYAID_8822B(x) | BIT_WMAC_MU_BF_MYAID_8822B(v))
+
+/* 2 REG_WMAC_MU_BFRPT_PARA_8822B */
+
+#define BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL_8822B 12
+#define BIT_MASK_BIT_BFRPT_PARA_USERID_SEL_8822B 0x7
+#define BIT_BIT_BFRPT_PARA_USERID_SEL_8822B(x) \
+ (((x) & BIT_MASK_BIT_BFRPT_PARA_USERID_SEL_8822B) \
+ << BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL_8822B)
+#define BITS_BIT_BFRPT_PARA_USERID_SEL_8822B \
+ (BIT_MASK_BIT_BFRPT_PARA_USERID_SEL_8822B \
+ << BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL_8822B)
+#define BIT_CLEAR_BIT_BFRPT_PARA_USERID_SEL_8822B(x) \
+ ((x) & (~BITS_BIT_BFRPT_PARA_USERID_SEL_8822B))
+#define BIT_GET_BIT_BFRPT_PARA_USERID_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL_8822B) & \
+ BIT_MASK_BIT_BFRPT_PARA_USERID_SEL_8822B)
+#define BIT_SET_BIT_BFRPT_PARA_USERID_SEL_8822B(x, v) \
+ (BIT_CLEAR_BIT_BFRPT_PARA_USERID_SEL_8822B(x) | \
+ BIT_BIT_BFRPT_PARA_USERID_SEL_8822B(v))
+
+#define BIT_SHIFT_BFRPT_PARA_8822B 0
+#define BIT_MASK_BFRPT_PARA_8822B 0xfff
+#define BIT_BFRPT_PARA_8822B(x) \
+ (((x) & BIT_MASK_BFRPT_PARA_8822B) << BIT_SHIFT_BFRPT_PARA_8822B)
+#define BITS_BFRPT_PARA_8822B \
+ (BIT_MASK_BFRPT_PARA_8822B << BIT_SHIFT_BFRPT_PARA_8822B)
+#define BIT_CLEAR_BFRPT_PARA_8822B(x) ((x) & (~BITS_BFRPT_PARA_8822B))
+#define BIT_GET_BFRPT_PARA_8822B(x) \
+ (((x) >> BIT_SHIFT_BFRPT_PARA_8822B) & BIT_MASK_BFRPT_PARA_8822B)
+#define BIT_SET_BFRPT_PARA_8822B(x, v) \
+ (BIT_CLEAR_BFRPT_PARA_8822B(x) | BIT_BFRPT_PARA_8822B(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2_8822B */
+#define BIT_STATUS_BFEE2_8822B BIT(10)
+#define BIT_WMAC_MU_BFEE2_EN_8822B BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE2_AID_8822B 0
+#define BIT_MASK_WMAC_MU_BFEE2_AID_8822B 0x1ff
+#define BIT_WMAC_MU_BFEE2_AID_8822B(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE2_AID_8822B) \
+ << BIT_SHIFT_WMAC_MU_BFEE2_AID_8822B)
+#define BITS_WMAC_MU_BFEE2_AID_8822B \
+ (BIT_MASK_WMAC_MU_BFEE2_AID_8822B << BIT_SHIFT_WMAC_MU_BFEE2_AID_8822B)
+#define BIT_CLEAR_WMAC_MU_BFEE2_AID_8822B(x) \
+ ((x) & (~BITS_WMAC_MU_BFEE2_AID_8822B))
+#define BIT_GET_WMAC_MU_BFEE2_AID_8822B(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID_8822B) & \
+ BIT_MASK_WMAC_MU_BFEE2_AID_8822B)
+#define BIT_SET_WMAC_MU_BFEE2_AID_8822B(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE2_AID_8822B(x) | BIT_WMAC_MU_BFEE2_AID_8822B(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3_8822B */
+#define BIT_STATUS_BFEE3_8822B BIT(10)
+#define BIT_WMAC_MU_BFEE3_EN_8822B BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE3_AID_8822B 0
+#define BIT_MASK_WMAC_MU_BFEE3_AID_8822B 0x1ff
+#define BIT_WMAC_MU_BFEE3_AID_8822B(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE3_AID_8822B) \
+ << BIT_SHIFT_WMAC_MU_BFEE3_AID_8822B)
+#define BITS_WMAC_MU_BFEE3_AID_8822B \
+ (BIT_MASK_WMAC_MU_BFEE3_AID_8822B << BIT_SHIFT_WMAC_MU_BFEE3_AID_8822B)
+#define BIT_CLEAR_WMAC_MU_BFEE3_AID_8822B(x) \
+ ((x) & (~BITS_WMAC_MU_BFEE3_AID_8822B))
+#define BIT_GET_WMAC_MU_BFEE3_AID_8822B(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID_8822B) & \
+ BIT_MASK_WMAC_MU_BFEE3_AID_8822B)
+#define BIT_SET_WMAC_MU_BFEE3_AID_8822B(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE3_AID_8822B(x) | BIT_WMAC_MU_BFEE3_AID_8822B(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4_8822B */
+#define BIT_STATUS_BFEE4_8822B BIT(10)
+#define BIT_WMAC_MU_BFEE4_EN_8822B BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE4_AID_8822B 0
+#define BIT_MASK_WMAC_MU_BFEE4_AID_8822B 0x1ff
+#define BIT_WMAC_MU_BFEE4_AID_8822B(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE4_AID_8822B) \
+ << BIT_SHIFT_WMAC_MU_BFEE4_AID_8822B)
+#define BITS_WMAC_MU_BFEE4_AID_8822B \
+ (BIT_MASK_WMAC_MU_BFEE4_AID_8822B << BIT_SHIFT_WMAC_MU_BFEE4_AID_8822B)
+#define BIT_CLEAR_WMAC_MU_BFEE4_AID_8822B(x) \
+ ((x) & (~BITS_WMAC_MU_BFEE4_AID_8822B))
+#define BIT_GET_WMAC_MU_BFEE4_AID_8822B(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID_8822B) & \
+ BIT_MASK_WMAC_MU_BFEE4_AID_8822B)
+#define BIT_SET_WMAC_MU_BFEE4_AID_8822B(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE4_AID_8822B(x) | BIT_WMAC_MU_BFEE4_AID_8822B(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5_8822B */
+#define BIT_STATUS_BFEE5_8822B BIT(10)
+#define BIT_WMAC_MU_BFEE5_EN_8822B BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE5_AID_8822B 0
+#define BIT_MASK_WMAC_MU_BFEE5_AID_8822B 0x1ff
+#define BIT_WMAC_MU_BFEE5_AID_8822B(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE5_AID_8822B) \
+ << BIT_SHIFT_WMAC_MU_BFEE5_AID_8822B)
+#define BITS_WMAC_MU_BFEE5_AID_8822B \
+ (BIT_MASK_WMAC_MU_BFEE5_AID_8822B << BIT_SHIFT_WMAC_MU_BFEE5_AID_8822B)
+#define BIT_CLEAR_WMAC_MU_BFEE5_AID_8822B(x) \
+ ((x) & (~BITS_WMAC_MU_BFEE5_AID_8822B))
+#define BIT_GET_WMAC_MU_BFEE5_AID_8822B(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID_8822B) & \
+ BIT_MASK_WMAC_MU_BFEE5_AID_8822B)
+#define BIT_SET_WMAC_MU_BFEE5_AID_8822B(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE5_AID_8822B(x) | BIT_WMAC_MU_BFEE5_AID_8822B(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6_8822B */
+#define BIT_STATUS_BFEE6_8822B BIT(10)
+#define BIT_WMAC_MU_BFEE6_EN_8822B BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE6_AID_8822B 0
+#define BIT_MASK_WMAC_MU_BFEE6_AID_8822B 0x1ff
+#define BIT_WMAC_MU_BFEE6_AID_8822B(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE6_AID_8822B) \
+ << BIT_SHIFT_WMAC_MU_BFEE6_AID_8822B)
+#define BITS_WMAC_MU_BFEE6_AID_8822B \
+ (BIT_MASK_WMAC_MU_BFEE6_AID_8822B << BIT_SHIFT_WMAC_MU_BFEE6_AID_8822B)
+#define BIT_CLEAR_WMAC_MU_BFEE6_AID_8822B(x) \
+ ((x) & (~BITS_WMAC_MU_BFEE6_AID_8822B))
+#define BIT_GET_WMAC_MU_BFEE6_AID_8822B(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID_8822B) & \
+ BIT_MASK_WMAC_MU_BFEE6_AID_8822B)
+#define BIT_SET_WMAC_MU_BFEE6_AID_8822B(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE6_AID_8822B(x) | BIT_WMAC_MU_BFEE6_AID_8822B(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7_8822B */
+#define BIT_STATUS_BFEE7_8822B BIT(10)
+#define BIT_WMAC_MU_BFEE7_EN_8822B BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE7_AID_8822B 0
+#define BIT_MASK_WMAC_MU_BFEE7_AID_8822B 0x1ff
+#define BIT_WMAC_MU_BFEE7_AID_8822B(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE7_AID_8822B) \
+ << BIT_SHIFT_WMAC_MU_BFEE7_AID_8822B)
+#define BITS_WMAC_MU_BFEE7_AID_8822B \
+ (BIT_MASK_WMAC_MU_BFEE7_AID_8822B << BIT_SHIFT_WMAC_MU_BFEE7_AID_8822B)
+#define BIT_CLEAR_WMAC_MU_BFEE7_AID_8822B(x) \
+ ((x) & (~BITS_WMAC_MU_BFEE7_AID_8822B))
+#define BIT_GET_WMAC_MU_BFEE7_AID_8822B(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID_8822B) & \
+ BIT_MASK_WMAC_MU_BFEE7_AID_8822B)
+#define BIT_SET_WMAC_MU_BFEE7_AID_8822B(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE7_AID_8822B(x) | BIT_WMAC_MU_BFEE7_AID_8822B(v))
/* 2 REG_NOT_VALID_8822B */
+#define BIT_RST_ALL_COUNTER_8822B BIT(31)
+
+#define BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822B 16
+#define BIT_MASK_ABORT_RX_VBON_COUNTER_8822B 0xff
+#define BIT_ABORT_RX_VBON_COUNTER_8822B(x) \
+ (((x) & BIT_MASK_ABORT_RX_VBON_COUNTER_8822B) \
+ << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822B)
+#define BITS_ABORT_RX_VBON_COUNTER_8822B \
+ (BIT_MASK_ABORT_RX_VBON_COUNTER_8822B \
+ << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822B)
+#define BIT_CLEAR_ABORT_RX_VBON_COUNTER_8822B(x) \
+ ((x) & (~BITS_ABORT_RX_VBON_COUNTER_8822B))
+#define BIT_GET_ABORT_RX_VBON_COUNTER_8822B(x) \
+ (((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822B) & \
+ BIT_MASK_ABORT_RX_VBON_COUNTER_8822B)
+#define BIT_SET_ABORT_RX_VBON_COUNTER_8822B(x, v) \
+ (BIT_CLEAR_ABORT_RX_VBON_COUNTER_8822B(x) | \
+ BIT_ABORT_RX_VBON_COUNTER_8822B(v))
+
+#define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822B 8
+#define BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822B 0xff
+#define BIT_ABORT_RX_RDRDY_COUNTER_8822B(x) \
+ (((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822B) \
+ << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822B)
+#define BITS_ABORT_RX_RDRDY_COUNTER_8822B \
+ (BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822B \
+ << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822B)
+#define BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8822B(x) \
+ ((x) & (~BITS_ABORT_RX_RDRDY_COUNTER_8822B))
+#define BIT_GET_ABORT_RX_RDRDY_COUNTER_8822B(x) \
+ (((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822B) & \
+ BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822B)
+#define BIT_SET_ABORT_RX_RDRDY_COUNTER_8822B(x, v) \
+ (BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8822B(x) | \
+ BIT_ABORT_RX_RDRDY_COUNTER_8822B(v))
+
+#define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822B 0
+#define BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822B 0xff
+#define BIT_VBON_EARLY_FALLING_COUNTER_8822B(x) \
+ (((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822B) \
+ << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822B)
+#define BITS_VBON_EARLY_FALLING_COUNTER_8822B \
+ (BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822B \
+ << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822B)
+#define BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8822B(x) \
+ ((x) & (~BITS_VBON_EARLY_FALLING_COUNTER_8822B))
+#define BIT_GET_VBON_EARLY_FALLING_COUNTER_8822B(x) \
+ (((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822B) & \
+ BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822B)
+#define BIT_SET_VBON_EARLY_FALLING_COUNTER_8822B(x, v) \
+ (BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8822B(x) | \
+ BIT_VBON_EARLY_FALLING_COUNTER_8822B(v))
/* 2 REG_NOT_VALID_8822B */
+#define BIT_WMAC_PLCP_TRX_SEL_8822B BIT(31)
+
+#define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822B 28
+#define BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822B 0x7
+#define BIT_WMAC_PLCP_RDSIG_SEL_8822B(x) \
+ (((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822B) \
+ << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822B)
+#define BITS_WMAC_PLCP_RDSIG_SEL_8822B \
+ (BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822B \
+ << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822B)
+#define BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8822B(x) \
+ ((x) & (~BITS_WMAC_PLCP_RDSIG_SEL_8822B))
+#define BIT_GET_WMAC_PLCP_RDSIG_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822B) & \
+ BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822B)
+#define BIT_SET_WMAC_PLCP_RDSIG_SEL_8822B(x, v) \
+ (BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8822B(x) | \
+ BIT_WMAC_PLCP_RDSIG_SEL_8822B(v))
+
+#define BIT_SHIFT_WMAC_RATE_IDX_8822B 24
+#define BIT_MASK_WMAC_RATE_IDX_8822B 0xf
+#define BIT_WMAC_RATE_IDX_8822B(x) \
+ (((x) & BIT_MASK_WMAC_RATE_IDX_8822B) << BIT_SHIFT_WMAC_RATE_IDX_8822B)
+#define BITS_WMAC_RATE_IDX_8822B \
+ (BIT_MASK_WMAC_RATE_IDX_8822B << BIT_SHIFT_WMAC_RATE_IDX_8822B)
+#define BIT_CLEAR_WMAC_RATE_IDX_8822B(x) ((x) & (~BITS_WMAC_RATE_IDX_8822B))
+#define BIT_GET_WMAC_RATE_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_WMAC_RATE_IDX_8822B) & BIT_MASK_WMAC_RATE_IDX_8822B)
+#define BIT_SET_WMAC_RATE_IDX_8822B(x, v) \
+ (BIT_CLEAR_WMAC_RATE_IDX_8822B(x) | BIT_WMAC_RATE_IDX_8822B(v))
+
+#define BIT_SHIFT_WMAC_PLCP_RDSIG_8822B 0
+#define BIT_MASK_WMAC_PLCP_RDSIG_8822B 0xffffff
+#define BIT_WMAC_PLCP_RDSIG_8822B(x) \
+ (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8822B) \
+ << BIT_SHIFT_WMAC_PLCP_RDSIG_8822B)
+#define BITS_WMAC_PLCP_RDSIG_8822B \
+ (BIT_MASK_WMAC_PLCP_RDSIG_8822B << BIT_SHIFT_WMAC_PLCP_RDSIG_8822B)
+#define BIT_CLEAR_WMAC_PLCP_RDSIG_8822B(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8822B))
+#define BIT_GET_WMAC_PLCP_RDSIG_8822B(x) \
+ (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8822B) & \
+ BIT_MASK_WMAC_PLCP_RDSIG_8822B)
+#define BIT_SET_WMAC_PLCP_RDSIG_8822B(x, v) \
+ (BIT_CLEAR_WMAC_PLCP_RDSIG_8822B(x) | BIT_WMAC_PLCP_RDSIG_8822B(v))
/* 2 REG_NOT_VALID_8822B */
+#define BIT_WMAC_MUTX_IDX_8822B BIT(24)
+
+#define BIT_SHIFT_WMAC_PLCP_RDSIG_8822B 0
+#define BIT_MASK_WMAC_PLCP_RDSIG_8822B 0xffffff
+#define BIT_WMAC_PLCP_RDSIG_8822B(x) \
+ (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8822B) \
+ << BIT_SHIFT_WMAC_PLCP_RDSIG_8822B)
+#define BITS_WMAC_PLCP_RDSIG_8822B \
+ (BIT_MASK_WMAC_PLCP_RDSIG_8822B << BIT_SHIFT_WMAC_PLCP_RDSIG_8822B)
+#define BIT_CLEAR_WMAC_PLCP_RDSIG_8822B(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8822B))
+#define BIT_GET_WMAC_PLCP_RDSIG_8822B(x) \
+ (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8822B) & \
+ BIT_MASK_WMAC_PLCP_RDSIG_8822B)
+#define BIT_SET_WMAC_PLCP_RDSIG_8822B(x, v) \
+ (BIT_CLEAR_WMAC_PLCP_RDSIG_8822B(x) | BIT_WMAC_PLCP_RDSIG_8822B(v))
/* 2 REG_TRANSMIT_ADDRSS_0_8822B (TA0 REGISTER) */
#define BIT_SHIFT_TA0_8822B 0
#define BIT_MASK_TA0_8822B 0xffffffffffffL
#define BIT_TA0_8822B(x) (((x) & BIT_MASK_TA0_8822B) << BIT_SHIFT_TA0_8822B)
+#define BITS_TA0_8822B (BIT_MASK_TA0_8822B << BIT_SHIFT_TA0_8822B)
+#define BIT_CLEAR_TA0_8822B(x) ((x) & (~BITS_TA0_8822B))
#define BIT_GET_TA0_8822B(x) (((x) >> BIT_SHIFT_TA0_8822B) & BIT_MASK_TA0_8822B)
-
+#define BIT_SET_TA0_8822B(x, v) (BIT_CLEAR_TA0_8822B(x) | BIT_TA0_8822B(v))
/* 2 REG_TRANSMIT_ADDRSS_1_8822B (TA1 REGISTER) */
#define BIT_SHIFT_TA1_8822B 0
#define BIT_MASK_TA1_8822B 0xffffffffffffL
#define BIT_TA1_8822B(x) (((x) & BIT_MASK_TA1_8822B) << BIT_SHIFT_TA1_8822B)
+#define BITS_TA1_8822B (BIT_MASK_TA1_8822B << BIT_SHIFT_TA1_8822B)
+#define BIT_CLEAR_TA1_8822B(x) ((x) & (~BITS_TA1_8822B))
#define BIT_GET_TA1_8822B(x) (((x) >> BIT_SHIFT_TA1_8822B) & BIT_MASK_TA1_8822B)
-
+#define BIT_SET_TA1_8822B(x, v) (BIT_CLEAR_TA1_8822B(x) | BIT_TA1_8822B(v))
/* 2 REG_TRANSMIT_ADDRSS_2_8822B (TA2 REGISTER) */
#define BIT_SHIFT_TA2_8822B 0
#define BIT_MASK_TA2_8822B 0xffffffffffffL
#define BIT_TA2_8822B(x) (((x) & BIT_MASK_TA2_8822B) << BIT_SHIFT_TA2_8822B)
+#define BITS_TA2_8822B (BIT_MASK_TA2_8822B << BIT_SHIFT_TA2_8822B)
+#define BIT_CLEAR_TA2_8822B(x) ((x) & (~BITS_TA2_8822B))
#define BIT_GET_TA2_8822B(x) (((x) >> BIT_SHIFT_TA2_8822B) & BIT_MASK_TA2_8822B)
-
+#define BIT_SET_TA2_8822B(x, v) (BIT_CLEAR_TA2_8822B(x) | BIT_TA2_8822B(v))
/* 2 REG_TRANSMIT_ADDRSS_3_8822B (TA3 REGISTER) */
#define BIT_SHIFT_TA3_8822B 0
#define BIT_MASK_TA3_8822B 0xffffffffffffL
#define BIT_TA3_8822B(x) (((x) & BIT_MASK_TA3_8822B) << BIT_SHIFT_TA3_8822B)
+#define BITS_TA3_8822B (BIT_MASK_TA3_8822B << BIT_SHIFT_TA3_8822B)
+#define BIT_CLEAR_TA3_8822B(x) ((x) & (~BITS_TA3_8822B))
#define BIT_GET_TA3_8822B(x) (((x) >> BIT_SHIFT_TA3_8822B) & BIT_MASK_TA3_8822B)
-
+#define BIT_SET_TA3_8822B(x, v) (BIT_CLEAR_TA3_8822B(x) | BIT_TA3_8822B(v))
/* 2 REG_TRANSMIT_ADDRSS_4_8822B (TA4 REGISTER) */
#define BIT_SHIFT_TA4_8822B 0
#define BIT_MASK_TA4_8822B 0xffffffffffffL
#define BIT_TA4_8822B(x) (((x) & BIT_MASK_TA4_8822B) << BIT_SHIFT_TA4_8822B)
+#define BITS_TA4_8822B (BIT_MASK_TA4_8822B << BIT_SHIFT_TA4_8822B)
+#define BIT_CLEAR_TA4_8822B(x) ((x) & (~BITS_TA4_8822B))
#define BIT_GET_TA4_8822B(x) (((x) >> BIT_SHIFT_TA4_8822B) & BIT_MASK_TA4_8822B)
-
+#define BIT_SET_TA4_8822B(x, v) (BIT_CLEAR_TA4_8822B(x) | BIT_TA4_8822B(v))
/* 2 REG_NOT_VALID_8822B */
@@ -8823,39 +15845,68 @@
#define BIT_SHIFT_MACID1_8822B 0
#define BIT_MASK_MACID1_8822B 0xffffffffffffL
-#define BIT_MACID1_8822B(x) (((x) & BIT_MASK_MACID1_8822B) << BIT_SHIFT_MACID1_8822B)
-#define BIT_GET_MACID1_8822B(x) (((x) >> BIT_SHIFT_MACID1_8822B) & BIT_MASK_MACID1_8822B)
-
+#define BIT_MACID1_8822B(x) \
+ (((x) & BIT_MASK_MACID1_8822B) << BIT_SHIFT_MACID1_8822B)
+#define BITS_MACID1_8822B (BIT_MASK_MACID1_8822B << BIT_SHIFT_MACID1_8822B)
+#define BIT_CLEAR_MACID1_8822B(x) ((x) & (~BITS_MACID1_8822B))
+#define BIT_GET_MACID1_8822B(x) \
+ (((x) >> BIT_SHIFT_MACID1_8822B) & BIT_MASK_MACID1_8822B)
+#define BIT_SET_MACID1_8822B(x, v) \
+ (BIT_CLEAR_MACID1_8822B(x) | BIT_MACID1_8822B(v))
/* 2 REG_BSSID1_8822B */
#define BIT_SHIFT_BSSID1_8822B 0
#define BIT_MASK_BSSID1_8822B 0xffffffffffffL
-#define BIT_BSSID1_8822B(x) (((x) & BIT_MASK_BSSID1_8822B) << BIT_SHIFT_BSSID1_8822B)
-#define BIT_GET_BSSID1_8822B(x) (((x) >> BIT_SHIFT_BSSID1_8822B) & BIT_MASK_BSSID1_8822B)
-
+#define BIT_BSSID1_8822B(x) \
+ (((x) & BIT_MASK_BSSID1_8822B) << BIT_SHIFT_BSSID1_8822B)
+#define BITS_BSSID1_8822B (BIT_MASK_BSSID1_8822B << BIT_SHIFT_BSSID1_8822B)
+#define BIT_CLEAR_BSSID1_8822B(x) ((x) & (~BITS_BSSID1_8822B))
+#define BIT_GET_BSSID1_8822B(x) \
+ (((x) >> BIT_SHIFT_BSSID1_8822B) & BIT_MASK_BSSID1_8822B)
+#define BIT_SET_BSSID1_8822B(x, v) \
+ (BIT_CLEAR_BSSID1_8822B(x) | BIT_BSSID1_8822B(v))
/* 2 REG_BCN_PSR_RPT1_8822B */
#define BIT_SHIFT_DTIM_CNT1_8822B 24
#define BIT_MASK_DTIM_CNT1_8822B 0xff
-#define BIT_DTIM_CNT1_8822B(x) (((x) & BIT_MASK_DTIM_CNT1_8822B) << BIT_SHIFT_DTIM_CNT1_8822B)
-#define BIT_GET_DTIM_CNT1_8822B(x) (((x) >> BIT_SHIFT_DTIM_CNT1_8822B) & BIT_MASK_DTIM_CNT1_8822B)
-
+#define BIT_DTIM_CNT1_8822B(x) \
+ (((x) & BIT_MASK_DTIM_CNT1_8822B) << BIT_SHIFT_DTIM_CNT1_8822B)
+#define BITS_DTIM_CNT1_8822B \
+ (BIT_MASK_DTIM_CNT1_8822B << BIT_SHIFT_DTIM_CNT1_8822B)
+#define BIT_CLEAR_DTIM_CNT1_8822B(x) ((x) & (~BITS_DTIM_CNT1_8822B))
+#define BIT_GET_DTIM_CNT1_8822B(x) \
+ (((x) >> BIT_SHIFT_DTIM_CNT1_8822B) & BIT_MASK_DTIM_CNT1_8822B)
+#define BIT_SET_DTIM_CNT1_8822B(x, v) \
+ (BIT_CLEAR_DTIM_CNT1_8822B(x) | BIT_DTIM_CNT1_8822B(v))
#define BIT_SHIFT_DTIM_PERIOD1_8822B 16
#define BIT_MASK_DTIM_PERIOD1_8822B 0xff
-#define BIT_DTIM_PERIOD1_8822B(x) (((x) & BIT_MASK_DTIM_PERIOD1_8822B) << BIT_SHIFT_DTIM_PERIOD1_8822B)
-#define BIT_GET_DTIM_PERIOD1_8822B(x) (((x) >> BIT_SHIFT_DTIM_PERIOD1_8822B) & BIT_MASK_DTIM_PERIOD1_8822B)
+#define BIT_DTIM_PERIOD1_8822B(x) \
+ (((x) & BIT_MASK_DTIM_PERIOD1_8822B) << BIT_SHIFT_DTIM_PERIOD1_8822B)
+#define BITS_DTIM_PERIOD1_8822B \
+ (BIT_MASK_DTIM_PERIOD1_8822B << BIT_SHIFT_DTIM_PERIOD1_8822B)
+#define BIT_CLEAR_DTIM_PERIOD1_8822B(x) ((x) & (~BITS_DTIM_PERIOD1_8822B))
+#define BIT_GET_DTIM_PERIOD1_8822B(x) \
+ (((x) >> BIT_SHIFT_DTIM_PERIOD1_8822B) & BIT_MASK_DTIM_PERIOD1_8822B)
+#define BIT_SET_DTIM_PERIOD1_8822B(x, v) \
+ (BIT_CLEAR_DTIM_PERIOD1_8822B(x) | BIT_DTIM_PERIOD1_8822B(v))
#define BIT_DTIM1_8822B BIT(15)
#define BIT_TIM1_8822B BIT(14)
#define BIT_SHIFT_PS_AID_1_8822B 0
#define BIT_MASK_PS_AID_1_8822B 0x7ff
-#define BIT_PS_AID_1_8822B(x) (((x) & BIT_MASK_PS_AID_1_8822B) << BIT_SHIFT_PS_AID_1_8822B)
-#define BIT_GET_PS_AID_1_8822B(x) (((x) >> BIT_SHIFT_PS_AID_1_8822B) & BIT_MASK_PS_AID_1_8822B)
-
+#define BIT_PS_AID_1_8822B(x) \
+ (((x) & BIT_MASK_PS_AID_1_8822B) << BIT_SHIFT_PS_AID_1_8822B)
+#define BITS_PS_AID_1_8822B \
+ (BIT_MASK_PS_AID_1_8822B << BIT_SHIFT_PS_AID_1_8822B)
+#define BIT_CLEAR_PS_AID_1_8822B(x) ((x) & (~BITS_PS_AID_1_8822B))
+#define BIT_GET_PS_AID_1_8822B(x) \
+ (((x) >> BIT_SHIFT_PS_AID_1_8822B) & BIT_MASK_PS_AID_1_8822B)
+#define BIT_SET_PS_AID_1_8822B(x, v) \
+ (BIT_CLEAR_PS_AID_1_8822B(x) | BIT_PS_AID_1_8822B(v))
/* 2 REG_ASSOCIATED_BFMEE_SEL_8822B */
#define BIT_TXUSER_ID1_8822B BIT(25)
@@ -8863,34 +15914,78 @@
#define BIT_SHIFT_AID1_8822B 16
#define BIT_MASK_AID1_8822B 0x1ff
#define BIT_AID1_8822B(x) (((x) & BIT_MASK_AID1_8822B) << BIT_SHIFT_AID1_8822B)
-#define BIT_GET_AID1_8822B(x) (((x) >> BIT_SHIFT_AID1_8822B) & BIT_MASK_AID1_8822B)
+#define BITS_AID1_8822B (BIT_MASK_AID1_8822B << BIT_SHIFT_AID1_8822B)
+#define BIT_CLEAR_AID1_8822B(x) ((x) & (~BITS_AID1_8822B))
+#define BIT_GET_AID1_8822B(x) \
+ (((x) >> BIT_SHIFT_AID1_8822B) & BIT_MASK_AID1_8822B)
+#define BIT_SET_AID1_8822B(x, v) (BIT_CLEAR_AID1_8822B(x) | BIT_AID1_8822B(v))
#define BIT_TXUSER_ID0_8822B BIT(9)
#define BIT_SHIFT_AID0_8822B 0
#define BIT_MASK_AID0_8822B 0x1ff
#define BIT_AID0_8822B(x) (((x) & BIT_MASK_AID0_8822B) << BIT_SHIFT_AID0_8822B)
-#define BIT_GET_AID0_8822B(x) (((x) >> BIT_SHIFT_AID0_8822B) & BIT_MASK_AID0_8822B)
-
+#define BITS_AID0_8822B (BIT_MASK_AID0_8822B << BIT_SHIFT_AID0_8822B)
+#define BIT_CLEAR_AID0_8822B(x) ((x) & (~BITS_AID0_8822B))
+#define BIT_GET_AID0_8822B(x) \
+ (((x) >> BIT_SHIFT_AID0_8822B) & BIT_MASK_AID0_8822B)
+#define BIT_SET_AID0_8822B(x, v) (BIT_CLEAR_AID0_8822B(x) | BIT_AID0_8822B(v))
/* 2 REG_SND_PTCL_CTRL_8822B */
#define BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822B 24
#define BIT_MASK_NDP_RX_STANDBY_TIMER_8822B 0xff
-#define BIT_NDP_RX_STANDBY_TIMER_8822B(x) (((x) & BIT_MASK_NDP_RX_STANDBY_TIMER_8822B) << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822B)
-#define BIT_GET_NDP_RX_STANDBY_TIMER_8822B(x) (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822B) & BIT_MASK_NDP_RX_STANDBY_TIMER_8822B)
-
-
-#define BIT_SHIFT_CSI_RPT_OFFSET_HT_8822B 16
-#define BIT_MASK_CSI_RPT_OFFSET_HT_8822B 0xff
-#define BIT_CSI_RPT_OFFSET_HT_8822B(x) (((x) & BIT_MASK_CSI_RPT_OFFSET_HT_8822B) << BIT_SHIFT_CSI_RPT_OFFSET_HT_8822B)
-#define BIT_GET_CSI_RPT_OFFSET_HT_8822B(x) (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_8822B) & BIT_MASK_CSI_RPT_OFFSET_HT_8822B)
-
-
-#define BIT_SHIFT_R_WMAC_VHT_CATEGORY_8822B 8
-#define BIT_MASK_R_WMAC_VHT_CATEGORY_8822B 0xff
-#define BIT_R_WMAC_VHT_CATEGORY_8822B(x) (((x) & BIT_MASK_R_WMAC_VHT_CATEGORY_8822B) << BIT_SHIFT_R_WMAC_VHT_CATEGORY_8822B)
-#define BIT_GET_R_WMAC_VHT_CATEGORY_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY_8822B) & BIT_MASK_R_WMAC_VHT_CATEGORY_8822B)
+#define BIT_NDP_RX_STANDBY_TIMER_8822B(x) \
+ (((x) & BIT_MASK_NDP_RX_STANDBY_TIMER_8822B) \
+ << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822B)
+#define BITS_NDP_RX_STANDBY_TIMER_8822B \
+ (BIT_MASK_NDP_RX_STANDBY_TIMER_8822B \
+ << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822B)
+#define BIT_CLEAR_NDP_RX_STANDBY_TIMER_8822B(x) \
+ ((x) & (~BITS_NDP_RX_STANDBY_TIMER_8822B))
+#define BIT_GET_NDP_RX_STANDBY_TIMER_8822B(x) \
+ (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822B) & \
+ BIT_MASK_NDP_RX_STANDBY_TIMER_8822B)
+#define BIT_SET_NDP_RX_STANDBY_TIMER_8822B(x, v) \
+ (BIT_CLEAR_NDP_RX_STANDBY_TIMER_8822B(x) | \
+ BIT_NDP_RX_STANDBY_TIMER_8822B(v))
+
+#define BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822B 16
+#define BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822B 0x3f
+#define BIT_CSI_RPT_OFFSET_HT_V1_8822B(x) \
+ (((x) & BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822B) \
+ << BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822B)
+#define BITS_CSI_RPT_OFFSET_HT_V1_8822B \
+ (BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822B \
+ << BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822B)
+#define BIT_CLEAR_CSI_RPT_OFFSET_HT_V1_8822B(x) \
+ ((x) & (~BITS_CSI_RPT_OFFSET_HT_V1_8822B))
+#define BIT_GET_CSI_RPT_OFFSET_HT_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822B) & \
+ BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822B)
+#define BIT_SET_CSI_RPT_OFFSET_HT_V1_8822B(x, v) \
+ (BIT_CLEAR_CSI_RPT_OFFSET_HT_V1_8822B(x) | \
+ BIT_CSI_RPT_OFFSET_HT_V1_8822B(v))
+
+#define BIT_VHTNDP_RPTPOLL_CSI_STR_OFFSET_SEL_8822B BIT(15)
+#define BIT_NDPVLD_POS_RST_FFPTR_DIS_8822B BIT(14)
+
+#define BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8822B 8
+#define BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8822B 0x3f
+#define BIT_R_CSI_RPT_OFFSET_VHT_V1_8822B(x) \
+ (((x) & BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8822B) \
+ << BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8822B)
+#define BITS_R_CSI_RPT_OFFSET_VHT_V1_8822B \
+ (BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8822B \
+ << BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8822B)
+#define BIT_CLEAR_R_CSI_RPT_OFFSET_VHT_V1_8822B(x) \
+ ((x) & (~BITS_R_CSI_RPT_OFFSET_VHT_V1_8822B))
+#define BIT_GET_R_CSI_RPT_OFFSET_VHT_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_R_CSI_RPT_OFFSET_VHT_V1_8822B) & \
+ BIT_MASK_R_CSI_RPT_OFFSET_VHT_V1_8822B)
+#define BIT_SET_R_CSI_RPT_OFFSET_VHT_V1_8822B(x, v) \
+ (BIT_CLEAR_R_CSI_RPT_OFFSET_VHT_V1_8822B(x) | \
+ BIT_R_CSI_RPT_OFFSET_VHT_V1_8822B(v))
#define BIT_R_WMAC_USE_NSTS_8822B BIT(7)
#define BIT_R_DISABLE_CHECK_VHTSIGB_CRC_8822B BIT(6)
@@ -8910,21 +16005,54 @@
#define BIT_SHIFT_R_WMAC_NSARP_MODEN_8822B 6
#define BIT_MASK_R_WMAC_NSARP_MODEN_8822B 0x3
-#define BIT_R_WMAC_NSARP_MODEN_8822B(x) (((x) & BIT_MASK_R_WMAC_NSARP_MODEN_8822B) << BIT_SHIFT_R_WMAC_NSARP_MODEN_8822B)
-#define BIT_GET_R_WMAC_NSARP_MODEN_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8822B) & BIT_MASK_R_WMAC_NSARP_MODEN_8822B)
-
+#define BIT_R_WMAC_NSARP_MODEN_8822B(x) \
+ (((x) & BIT_MASK_R_WMAC_NSARP_MODEN_8822B) \
+ << BIT_SHIFT_R_WMAC_NSARP_MODEN_8822B)
+#define BITS_R_WMAC_NSARP_MODEN_8822B \
+ (BIT_MASK_R_WMAC_NSARP_MODEN_8822B \
+ << BIT_SHIFT_R_WMAC_NSARP_MODEN_8822B)
+#define BIT_CLEAR_R_WMAC_NSARP_MODEN_8822B(x) \
+ ((x) & (~BITS_R_WMAC_NSARP_MODEN_8822B))
+#define BIT_GET_R_WMAC_NSARP_MODEN_8822B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8822B) & \
+ BIT_MASK_R_WMAC_NSARP_MODEN_8822B)
+#define BIT_SET_R_WMAC_NSARP_MODEN_8822B(x, v) \
+ (BIT_CLEAR_R_WMAC_NSARP_MODEN_8822B(x) | \
+ BIT_R_WMAC_NSARP_MODEN_8822B(v))
#define BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822B 4
#define BIT_MASK_R_WMAC_NSARP_RSPFTP_8822B 0x3
-#define BIT_R_WMAC_NSARP_RSPFTP_8822B(x) (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8822B) << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822B)
-#define BIT_GET_R_WMAC_NSARP_RSPFTP_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822B) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8822B)
-
+#define BIT_R_WMAC_NSARP_RSPFTP_8822B(x) \
+ (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8822B) \
+ << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822B)
+#define BITS_R_WMAC_NSARP_RSPFTP_8822B \
+ (BIT_MASK_R_WMAC_NSARP_RSPFTP_8822B \
+ << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822B)
+#define BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8822B(x) \
+ ((x) & (~BITS_R_WMAC_NSARP_RSPFTP_8822B))
+#define BIT_GET_R_WMAC_NSARP_RSPFTP_8822B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822B) & \
+ BIT_MASK_R_WMAC_NSARP_RSPFTP_8822B)
+#define BIT_SET_R_WMAC_NSARP_RSPFTP_8822B(x, v) \
+ (BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8822B(x) | \
+ BIT_R_WMAC_NSARP_RSPFTP_8822B(v))
#define BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822B 0
#define BIT_MASK_R_WMAC_NSARP_RSPSEC_8822B 0xf
-#define BIT_R_WMAC_NSARP_RSPSEC_8822B(x) (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8822B) << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822B)
-#define BIT_GET_R_WMAC_NSARP_RSPSEC_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822B) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8822B)
-
+#define BIT_R_WMAC_NSARP_RSPSEC_8822B(x) \
+ (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8822B) \
+ << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822B)
+#define BITS_R_WMAC_NSARP_RSPSEC_8822B \
+ (BIT_MASK_R_WMAC_NSARP_RSPSEC_8822B \
+ << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822B)
+#define BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8822B(x) \
+ ((x) & (~BITS_R_WMAC_NSARP_RSPSEC_8822B))
+#define BIT_GET_R_WMAC_NSARP_RSPSEC_8822B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822B) & \
+ BIT_MASK_R_WMAC_NSARP_RSPSEC_8822B)
+#define BIT_SET_R_WMAC_NSARP_RSPSEC_8822B(x, v) \
+ (BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8822B(x) | \
+ BIT_R_WMAC_NSARP_RSPSEC_8822B(v))
/* 2 REG_NS_ARP_INFO_8822B */
#define BIT_REQ_IS_MCNS_8822B BIT(23)
@@ -8935,45 +16063,101 @@
#define BIT_SHIFT_EXPRSP_SECTYPE_8822B 16
#define BIT_MASK_EXPRSP_SECTYPE_8822B 0x7
-#define BIT_EXPRSP_SECTYPE_8822B(x) (((x) & BIT_MASK_EXPRSP_SECTYPE_8822B) << BIT_SHIFT_EXPRSP_SECTYPE_8822B)
-#define BIT_GET_EXPRSP_SECTYPE_8822B(x) (((x) >> BIT_SHIFT_EXPRSP_SECTYPE_8822B) & BIT_MASK_EXPRSP_SECTYPE_8822B)
-
+#define BIT_EXPRSP_SECTYPE_8822B(x) \
+ (((x) & BIT_MASK_EXPRSP_SECTYPE_8822B) \
+ << BIT_SHIFT_EXPRSP_SECTYPE_8822B)
+#define BITS_EXPRSP_SECTYPE_8822B \
+ (BIT_MASK_EXPRSP_SECTYPE_8822B << BIT_SHIFT_EXPRSP_SECTYPE_8822B)
+#define BIT_CLEAR_EXPRSP_SECTYPE_8822B(x) ((x) & (~BITS_EXPRSP_SECTYPE_8822B))
+#define BIT_GET_EXPRSP_SECTYPE_8822B(x) \
+ (((x) >> BIT_SHIFT_EXPRSP_SECTYPE_8822B) & \
+ BIT_MASK_EXPRSP_SECTYPE_8822B)
+#define BIT_SET_EXPRSP_SECTYPE_8822B(x, v) \
+ (BIT_CLEAR_EXPRSP_SECTYPE_8822B(x) | BIT_EXPRSP_SECTYPE_8822B(v))
#define BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822B 8
#define BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822B 0xff
-#define BIT_EXPRSP_CHKSM_7_TO_0_8822B(x) (((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822B) << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822B)
-#define BIT_GET_EXPRSP_CHKSM_7_TO_0_8822B(x) (((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822B) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822B)
-
+#define BIT_EXPRSP_CHKSM_7_TO_0_8822B(x) \
+ (((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822B) \
+ << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822B)
+#define BITS_EXPRSP_CHKSM_7_TO_0_8822B \
+ (BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822B \
+ << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822B)
+#define BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8822B(x) \
+ ((x) & (~BITS_EXPRSP_CHKSM_7_TO_0_8822B))
+#define BIT_GET_EXPRSP_CHKSM_7_TO_0_8822B(x) \
+ (((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822B) & \
+ BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822B)
+#define BIT_SET_EXPRSP_CHKSM_7_TO_0_8822B(x, v) \
+ (BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8822B(x) | \
+ BIT_EXPRSP_CHKSM_7_TO_0_8822B(v))
#define BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822B 0
#define BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822B 0xff
-#define BIT_EXPRSP_CHKSM_15_TO_8_8822B(x) (((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822B) << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822B)
-#define BIT_GET_EXPRSP_CHKSM_15_TO_8_8822B(x) (((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822B) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822B)
-
+#define BIT_EXPRSP_CHKSM_15_TO_8_8822B(x) \
+ (((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822B) \
+ << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822B)
+#define BITS_EXPRSP_CHKSM_15_TO_8_8822B \
+ (BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822B \
+ << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822B)
+#define BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8822B(x) \
+ ((x) & (~BITS_EXPRSP_CHKSM_15_TO_8_8822B))
+#define BIT_GET_EXPRSP_CHKSM_15_TO_8_8822B(x) \
+ (((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822B) & \
+ BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822B)
+#define BIT_SET_EXPRSP_CHKSM_15_TO_8_8822B(x, v) \
+ (BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8822B(x) | \
+ BIT_EXPRSP_CHKSM_15_TO_8_8822B(v))
/* 2 REG_BEAMFORMING_INFO_NSARP_V1_8822B */
#define BIT_SHIFT_WMAC_ARPIP_8822B 0
#define BIT_MASK_WMAC_ARPIP_8822B 0xffffffffL
-#define BIT_WMAC_ARPIP_8822B(x) (((x) & BIT_MASK_WMAC_ARPIP_8822B) << BIT_SHIFT_WMAC_ARPIP_8822B)
-#define BIT_GET_WMAC_ARPIP_8822B(x) (((x) >> BIT_SHIFT_WMAC_ARPIP_8822B) & BIT_MASK_WMAC_ARPIP_8822B)
-
+#define BIT_WMAC_ARPIP_8822B(x) \
+ (((x) & BIT_MASK_WMAC_ARPIP_8822B) << BIT_SHIFT_WMAC_ARPIP_8822B)
+#define BITS_WMAC_ARPIP_8822B \
+ (BIT_MASK_WMAC_ARPIP_8822B << BIT_SHIFT_WMAC_ARPIP_8822B)
+#define BIT_CLEAR_WMAC_ARPIP_8822B(x) ((x) & (~BITS_WMAC_ARPIP_8822B))
+#define BIT_GET_WMAC_ARPIP_8822B(x) \
+ (((x) >> BIT_SHIFT_WMAC_ARPIP_8822B) & BIT_MASK_WMAC_ARPIP_8822B)
+#define BIT_SET_WMAC_ARPIP_8822B(x, v) \
+ (BIT_CLEAR_WMAC_ARPIP_8822B(x) | BIT_WMAC_ARPIP_8822B(v))
/* 2 REG_BEAMFORMING_INFO_NSARP_8822B */
#define BIT_SHIFT_BEAMFORMING_INFO_8822B 0
#define BIT_MASK_BEAMFORMING_INFO_8822B 0xffffffffL
-#define BIT_BEAMFORMING_INFO_8822B(x) (((x) & BIT_MASK_BEAMFORMING_INFO_8822B) << BIT_SHIFT_BEAMFORMING_INFO_8822B)
-#define BIT_GET_BEAMFORMING_INFO_8822B(x) (((x) >> BIT_SHIFT_BEAMFORMING_INFO_8822B) & BIT_MASK_BEAMFORMING_INFO_8822B)
-
+#define BIT_BEAMFORMING_INFO_8822B(x) \
+ (((x) & BIT_MASK_BEAMFORMING_INFO_8822B) \
+ << BIT_SHIFT_BEAMFORMING_INFO_8822B)
+#define BITS_BEAMFORMING_INFO_8822B \
+ (BIT_MASK_BEAMFORMING_INFO_8822B << BIT_SHIFT_BEAMFORMING_INFO_8822B)
+#define BIT_CLEAR_BEAMFORMING_INFO_8822B(x) \
+ ((x) & (~BITS_BEAMFORMING_INFO_8822B))
+#define BIT_GET_BEAMFORMING_INFO_8822B(x) \
+ (((x) >> BIT_SHIFT_BEAMFORMING_INFO_8822B) & \
+ BIT_MASK_BEAMFORMING_INFO_8822B)
+#define BIT_SET_BEAMFORMING_INFO_8822B(x, v) \
+ (BIT_CLEAR_BEAMFORMING_INFO_8822B(x) | BIT_BEAMFORMING_INFO_8822B(v))
/* 2 REG_NOT_VALID_8822B */
#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_8822B 0
#define BIT_MASK_R_WMAC_IPV6_MYIPAD_8822B 0xffffffffffffffffffffffffffffffffL
-#define BIT_R_WMAC_IPV6_MYIPAD_8822B(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_8822B) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_8822B)
-#define BIT_GET_R_WMAC_IPV6_MYIPAD_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_8822B) & BIT_MASK_R_WMAC_IPV6_MYIPAD_8822B)
-
+#define BIT_R_WMAC_IPV6_MYIPAD_8822B(x) \
+ (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_8822B) \
+ << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_8822B)
+#define BITS_R_WMAC_IPV6_MYIPAD_8822B \
+ (BIT_MASK_R_WMAC_IPV6_MYIPAD_8822B \
+ << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_8822B)
+#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_8822B(x) \
+ ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_8822B))
+#define BIT_GET_R_WMAC_IPV6_MYIPAD_8822B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_8822B) & \
+ BIT_MASK_R_WMAC_IPV6_MYIPAD_8822B)
+#define BIT_SET_R_WMAC_IPV6_MYIPAD_8822B(x, v) \
+ (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_8822B(x) | \
+ BIT_R_WMAC_IPV6_MYIPAD_8822B(v))
/* 2 REG_RSVD_0X740_8822B */
@@ -8981,15 +16165,37 @@
#define BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822B 4
#define BIT_MASK_R_WMAC_CTX_SUBTYPE_8822B 0xf
-#define BIT_R_WMAC_CTX_SUBTYPE_8822B(x) (((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8822B) << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822B)
-#define BIT_GET_R_WMAC_CTX_SUBTYPE_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822B) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8822B)
-
+#define BIT_R_WMAC_CTX_SUBTYPE_8822B(x) \
+ (((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8822B) \
+ << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822B)
+#define BITS_R_WMAC_CTX_SUBTYPE_8822B \
+ (BIT_MASK_R_WMAC_CTX_SUBTYPE_8822B \
+ << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822B)
+#define BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8822B(x) \
+ ((x) & (~BITS_R_WMAC_CTX_SUBTYPE_8822B))
+#define BIT_GET_R_WMAC_CTX_SUBTYPE_8822B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822B) & \
+ BIT_MASK_R_WMAC_CTX_SUBTYPE_8822B)
+#define BIT_SET_R_WMAC_CTX_SUBTYPE_8822B(x, v) \
+ (BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8822B(x) | \
+ BIT_R_WMAC_CTX_SUBTYPE_8822B(v))
#define BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822B 0
#define BIT_MASK_R_WMAC_RTX_SUBTYPE_8822B 0xf
-#define BIT_R_WMAC_RTX_SUBTYPE_8822B(x) (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8822B) << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822B)
-#define BIT_GET_R_WMAC_RTX_SUBTYPE_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822B) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8822B)
-
+#define BIT_R_WMAC_RTX_SUBTYPE_8822B(x) \
+ (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8822B) \
+ << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822B)
+#define BITS_R_WMAC_RTX_SUBTYPE_8822B \
+ (BIT_MASK_R_WMAC_RTX_SUBTYPE_8822B \
+ << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822B)
+#define BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8822B(x) \
+ ((x) & (~BITS_R_WMAC_RTX_SUBTYPE_8822B))
+#define BIT_GET_R_WMAC_RTX_SUBTYPE_8822B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822B) & \
+ BIT_MASK_R_WMAC_RTX_SUBTYPE_8822B)
+#define BIT_SET_R_WMAC_RTX_SUBTYPE_8822B(x, v) \
+ (BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8822B(x) | \
+ BIT_R_WMAC_RTX_SUBTYPE_8822B(v))
/* 2 REG_WMAC_SWAES_CFG_8822B */
@@ -8999,9 +16205,14 @@
#define BIT_SHIFT_TIMER_8822B 0
#define BIT_MASK_TIMER_8822B 0xff
-#define BIT_TIMER_8822B(x) (((x) & BIT_MASK_TIMER_8822B) << BIT_SHIFT_TIMER_8822B)
-#define BIT_GET_TIMER_8822B(x) (((x) >> BIT_SHIFT_TIMER_8822B) & BIT_MASK_TIMER_8822B)
-
+#define BIT_TIMER_8822B(x) \
+ (((x) & BIT_MASK_TIMER_8822B) << BIT_SHIFT_TIMER_8822B)
+#define BITS_TIMER_8822B (BIT_MASK_TIMER_8822B << BIT_SHIFT_TIMER_8822B)
+#define BIT_CLEAR_TIMER_8822B(x) ((x) & (~BITS_TIMER_8822B))
+#define BIT_GET_TIMER_8822B(x) \
+ (((x) >> BIT_SHIFT_TIMER_8822B) & BIT_MASK_TIMER_8822B)
+#define BIT_SET_TIMER_8822B(x, v) \
+ (BIT_CLEAR_TIMER_8822B(x) | BIT_TIMER_8822B(v))
/* 2 REG_BT_COEX_8822B */
#define BIT_R_GNT_BT_RFC_SW_8822B BIT(12)
@@ -9012,9 +16223,15 @@
#define BIT_SHIFT_R_BT_CNT_THR_8822B 0
#define BIT_MASK_R_BT_CNT_THR_8822B 0xff
-#define BIT_R_BT_CNT_THR_8822B(x) (((x) & BIT_MASK_R_BT_CNT_THR_8822B) << BIT_SHIFT_R_BT_CNT_THR_8822B)
-#define BIT_GET_R_BT_CNT_THR_8822B(x) (((x) >> BIT_SHIFT_R_BT_CNT_THR_8822B) & BIT_MASK_R_BT_CNT_THR_8822B)
-
+#define BIT_R_BT_CNT_THR_8822B(x) \
+ (((x) & BIT_MASK_R_BT_CNT_THR_8822B) << BIT_SHIFT_R_BT_CNT_THR_8822B)
+#define BITS_R_BT_CNT_THR_8822B \
+ (BIT_MASK_R_BT_CNT_THR_8822B << BIT_SHIFT_R_BT_CNT_THR_8822B)
+#define BIT_CLEAR_R_BT_CNT_THR_8822B(x) ((x) & (~BITS_R_BT_CNT_THR_8822B))
+#define BIT_GET_R_BT_CNT_THR_8822B(x) \
+ (((x) >> BIT_SHIFT_R_BT_CNT_THR_8822B) & BIT_MASK_R_BT_CNT_THR_8822B)
+#define BIT_SET_R_BT_CNT_THR_8822B(x, v) \
+ (BIT_CLEAR_R_BT_CNT_THR_8822B(x) | BIT_R_BT_CNT_THR_8822B(v))
/* 2 REG_WLAN_ACT_MASK_CTRL_8822B */
#define BIT_WLRX_TER_BY_CTL_8822B BIT(43)
@@ -9027,34 +16244,75 @@
#define BIT_SHIFT_RXMYRTS_NAV_V1_8822B 8
#define BIT_MASK_RXMYRTS_NAV_V1_8822B 0xff
-#define BIT_RXMYRTS_NAV_V1_8822B(x) (((x) & BIT_MASK_RXMYRTS_NAV_V1_8822B) << BIT_SHIFT_RXMYRTS_NAV_V1_8822B)
-#define BIT_GET_RXMYRTS_NAV_V1_8822B(x) (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8822B) & BIT_MASK_RXMYRTS_NAV_V1_8822B)
-
+#define BIT_RXMYRTS_NAV_V1_8822B(x) \
+ (((x) & BIT_MASK_RXMYRTS_NAV_V1_8822B) \
+ << BIT_SHIFT_RXMYRTS_NAV_V1_8822B)
+#define BITS_RXMYRTS_NAV_V1_8822B \
+ (BIT_MASK_RXMYRTS_NAV_V1_8822B << BIT_SHIFT_RXMYRTS_NAV_V1_8822B)
+#define BIT_CLEAR_RXMYRTS_NAV_V1_8822B(x) ((x) & (~BITS_RXMYRTS_NAV_V1_8822B))
+#define BIT_GET_RXMYRTS_NAV_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8822B) & \
+ BIT_MASK_RXMYRTS_NAV_V1_8822B)
+#define BIT_SET_RXMYRTS_NAV_V1_8822B(x, v) \
+ (BIT_CLEAR_RXMYRTS_NAV_V1_8822B(x) | BIT_RXMYRTS_NAV_V1_8822B(v))
#define BIT_SHIFT_RTSRST_V1_8822B 0
#define BIT_MASK_RTSRST_V1_8822B 0xff
-#define BIT_RTSRST_V1_8822B(x) (((x) & BIT_MASK_RTSRST_V1_8822B) << BIT_SHIFT_RTSRST_V1_8822B)
-#define BIT_GET_RTSRST_V1_8822B(x) (((x) >> BIT_SHIFT_RTSRST_V1_8822B) & BIT_MASK_RTSRST_V1_8822B)
-
+#define BIT_RTSRST_V1_8822B(x) \
+ (((x) & BIT_MASK_RTSRST_V1_8822B) << BIT_SHIFT_RTSRST_V1_8822B)
+#define BITS_RTSRST_V1_8822B \
+ (BIT_MASK_RTSRST_V1_8822B << BIT_SHIFT_RTSRST_V1_8822B)
+#define BIT_CLEAR_RTSRST_V1_8822B(x) ((x) & (~BITS_RTSRST_V1_8822B))
+#define BIT_GET_RTSRST_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_RTSRST_V1_8822B) & BIT_MASK_RTSRST_V1_8822B)
+#define BIT_SET_RTSRST_V1_8822B(x, v) \
+ (BIT_CLEAR_RTSRST_V1_8822B(x) | BIT_RTSRST_V1_8822B(v))
/* 2 REG_BT_COEX_ENHANCED_INTR_CTRL_8822B */
#define BIT_SHIFT_BT_STAT_DELAY_8822B 12
#define BIT_MASK_BT_STAT_DELAY_8822B 0xf
-#define BIT_BT_STAT_DELAY_8822B(x) (((x) & BIT_MASK_BT_STAT_DELAY_8822B) << BIT_SHIFT_BT_STAT_DELAY_8822B)
-#define BIT_GET_BT_STAT_DELAY_8822B(x) (((x) >> BIT_SHIFT_BT_STAT_DELAY_8822B) & BIT_MASK_BT_STAT_DELAY_8822B)
-
+#define BIT_BT_STAT_DELAY_8822B(x) \
+ (((x) & BIT_MASK_BT_STAT_DELAY_8822B) << BIT_SHIFT_BT_STAT_DELAY_8822B)
+#define BITS_BT_STAT_DELAY_8822B \
+ (BIT_MASK_BT_STAT_DELAY_8822B << BIT_SHIFT_BT_STAT_DELAY_8822B)
+#define BIT_CLEAR_BT_STAT_DELAY_8822B(x) ((x) & (~BITS_BT_STAT_DELAY_8822B))
+#define BIT_GET_BT_STAT_DELAY_8822B(x) \
+ (((x) >> BIT_SHIFT_BT_STAT_DELAY_8822B) & BIT_MASK_BT_STAT_DELAY_8822B)
+#define BIT_SET_BT_STAT_DELAY_8822B(x, v) \
+ (BIT_CLEAR_BT_STAT_DELAY_8822B(x) | BIT_BT_STAT_DELAY_8822B(v))
#define BIT_SHIFT_BT_TRX_INIT_DETECT_8822B 8
#define BIT_MASK_BT_TRX_INIT_DETECT_8822B 0xf
-#define BIT_BT_TRX_INIT_DETECT_8822B(x) (((x) & BIT_MASK_BT_TRX_INIT_DETECT_8822B) << BIT_SHIFT_BT_TRX_INIT_DETECT_8822B)
-#define BIT_GET_BT_TRX_INIT_DETECT_8822B(x) (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8822B) & BIT_MASK_BT_TRX_INIT_DETECT_8822B)
-
+#define BIT_BT_TRX_INIT_DETECT_8822B(x) \
+ (((x) & BIT_MASK_BT_TRX_INIT_DETECT_8822B) \
+ << BIT_SHIFT_BT_TRX_INIT_DETECT_8822B)
+#define BITS_BT_TRX_INIT_DETECT_8822B \
+ (BIT_MASK_BT_TRX_INIT_DETECT_8822B \
+ << BIT_SHIFT_BT_TRX_INIT_DETECT_8822B)
+#define BIT_CLEAR_BT_TRX_INIT_DETECT_8822B(x) \
+ ((x) & (~BITS_BT_TRX_INIT_DETECT_8822B))
+#define BIT_GET_BT_TRX_INIT_DETECT_8822B(x) \
+ (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8822B) & \
+ BIT_MASK_BT_TRX_INIT_DETECT_8822B)
+#define BIT_SET_BT_TRX_INIT_DETECT_8822B(x, v) \
+ (BIT_CLEAR_BT_TRX_INIT_DETECT_8822B(x) | \
+ BIT_BT_TRX_INIT_DETECT_8822B(v))
#define BIT_SHIFT_BT_PRI_DETECT_TO_8822B 4
#define BIT_MASK_BT_PRI_DETECT_TO_8822B 0xf
-#define BIT_BT_PRI_DETECT_TO_8822B(x) (((x) & BIT_MASK_BT_PRI_DETECT_TO_8822B) << BIT_SHIFT_BT_PRI_DETECT_TO_8822B)
-#define BIT_GET_BT_PRI_DETECT_TO_8822B(x) (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8822B) & BIT_MASK_BT_PRI_DETECT_TO_8822B)
+#define BIT_BT_PRI_DETECT_TO_8822B(x) \
+ (((x) & BIT_MASK_BT_PRI_DETECT_TO_8822B) \
+ << BIT_SHIFT_BT_PRI_DETECT_TO_8822B)
+#define BITS_BT_PRI_DETECT_TO_8822B \
+ (BIT_MASK_BT_PRI_DETECT_TO_8822B << BIT_SHIFT_BT_PRI_DETECT_TO_8822B)
+#define BIT_CLEAR_BT_PRI_DETECT_TO_8822B(x) \
+ ((x) & (~BITS_BT_PRI_DETECT_TO_8822B))
+#define BIT_GET_BT_PRI_DETECT_TO_8822B(x) \
+ (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8822B) & \
+ BIT_MASK_BT_PRI_DETECT_TO_8822B)
+#define BIT_SET_BT_PRI_DETECT_TO_8822B(x, v) \
+ (BIT_CLEAR_BT_PRI_DETECT_TO_8822B(x) | BIT_BT_PRI_DETECT_TO_8822B(v))
#define BIT_R_GRANTALL_WLMASK_8822B BIT(3)
#define BIT_STATIS_BT_EN_8822B BIT(2)
@@ -9065,46 +16323,99 @@
#define BIT_SHIFT_STATIS_BT_LO_RX_8822B (48 & CPU_OPT_WIDTH)
#define BIT_MASK_STATIS_BT_LO_RX_8822B 0xffff
-#define BIT_STATIS_BT_LO_RX_8822B(x) (((x) & BIT_MASK_STATIS_BT_LO_RX_8822B) << BIT_SHIFT_STATIS_BT_LO_RX_8822B)
-#define BIT_GET_STATIS_BT_LO_RX_8822B(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_RX_8822B) & BIT_MASK_STATIS_BT_LO_RX_8822B)
-
+#define BIT_STATIS_BT_LO_RX_8822B(x) \
+ (((x) & BIT_MASK_STATIS_BT_LO_RX_8822B) \
+ << BIT_SHIFT_STATIS_BT_LO_RX_8822B)
+#define BITS_STATIS_BT_LO_RX_8822B \
+ (BIT_MASK_STATIS_BT_LO_RX_8822B << BIT_SHIFT_STATIS_BT_LO_RX_8822B)
+#define BIT_CLEAR_STATIS_BT_LO_RX_8822B(x) ((x) & (~BITS_STATIS_BT_LO_RX_8822B))
+#define BIT_GET_STATIS_BT_LO_RX_8822B(x) \
+ (((x) >> BIT_SHIFT_STATIS_BT_LO_RX_8822B) & \
+ BIT_MASK_STATIS_BT_LO_RX_8822B)
+#define BIT_SET_STATIS_BT_LO_RX_8822B(x, v) \
+ (BIT_CLEAR_STATIS_BT_LO_RX_8822B(x) | BIT_STATIS_BT_LO_RX_8822B(v))
#define BIT_SHIFT_STATIS_BT_LO_TX_8822B (32 & CPU_OPT_WIDTH)
#define BIT_MASK_STATIS_BT_LO_TX_8822B 0xffff
-#define BIT_STATIS_BT_LO_TX_8822B(x) (((x) & BIT_MASK_STATIS_BT_LO_TX_8822B) << BIT_SHIFT_STATIS_BT_LO_TX_8822B)
-#define BIT_GET_STATIS_BT_LO_TX_8822B(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_TX_8822B) & BIT_MASK_STATIS_BT_LO_TX_8822B)
-
+#define BIT_STATIS_BT_LO_TX_8822B(x) \
+ (((x) & BIT_MASK_STATIS_BT_LO_TX_8822B) \
+ << BIT_SHIFT_STATIS_BT_LO_TX_8822B)
+#define BITS_STATIS_BT_LO_TX_8822B \
+ (BIT_MASK_STATIS_BT_LO_TX_8822B << BIT_SHIFT_STATIS_BT_LO_TX_8822B)
+#define BIT_CLEAR_STATIS_BT_LO_TX_8822B(x) ((x) & (~BITS_STATIS_BT_LO_TX_8822B))
+#define BIT_GET_STATIS_BT_LO_TX_8822B(x) \
+ (((x) >> BIT_SHIFT_STATIS_BT_LO_TX_8822B) & \
+ BIT_MASK_STATIS_BT_LO_TX_8822B)
+#define BIT_SET_STATIS_BT_LO_TX_8822B(x, v) \
+ (BIT_CLEAR_STATIS_BT_LO_TX_8822B(x) | BIT_STATIS_BT_LO_TX_8822B(v))
#define BIT_SHIFT_STATIS_BT_HI_RX_8822B 16
#define BIT_MASK_STATIS_BT_HI_RX_8822B 0xffff
-#define BIT_STATIS_BT_HI_RX_8822B(x) (((x) & BIT_MASK_STATIS_BT_HI_RX_8822B) << BIT_SHIFT_STATIS_BT_HI_RX_8822B)
-#define BIT_GET_STATIS_BT_HI_RX_8822B(x) (((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8822B) & BIT_MASK_STATIS_BT_HI_RX_8822B)
-
+#define BIT_STATIS_BT_HI_RX_8822B(x) \
+ (((x) & BIT_MASK_STATIS_BT_HI_RX_8822B) \
+ << BIT_SHIFT_STATIS_BT_HI_RX_8822B)
+#define BITS_STATIS_BT_HI_RX_8822B \
+ (BIT_MASK_STATIS_BT_HI_RX_8822B << BIT_SHIFT_STATIS_BT_HI_RX_8822B)
+#define BIT_CLEAR_STATIS_BT_HI_RX_8822B(x) ((x) & (~BITS_STATIS_BT_HI_RX_8822B))
+#define BIT_GET_STATIS_BT_HI_RX_8822B(x) \
+ (((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8822B) & \
+ BIT_MASK_STATIS_BT_HI_RX_8822B)
+#define BIT_SET_STATIS_BT_HI_RX_8822B(x, v) \
+ (BIT_CLEAR_STATIS_BT_HI_RX_8822B(x) | BIT_STATIS_BT_HI_RX_8822B(v))
#define BIT_SHIFT_STATIS_BT_HI_TX_8822B 0
#define BIT_MASK_STATIS_BT_HI_TX_8822B 0xffff
-#define BIT_STATIS_BT_HI_TX_8822B(x) (((x) & BIT_MASK_STATIS_BT_HI_TX_8822B) << BIT_SHIFT_STATIS_BT_HI_TX_8822B)
-#define BIT_GET_STATIS_BT_HI_TX_8822B(x) (((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8822B) & BIT_MASK_STATIS_BT_HI_TX_8822B)
-
+#define BIT_STATIS_BT_HI_TX_8822B(x) \
+ (((x) & BIT_MASK_STATIS_BT_HI_TX_8822B) \
+ << BIT_SHIFT_STATIS_BT_HI_TX_8822B)
+#define BITS_STATIS_BT_HI_TX_8822B \
+ (BIT_MASK_STATIS_BT_HI_TX_8822B << BIT_SHIFT_STATIS_BT_HI_TX_8822B)
+#define BIT_CLEAR_STATIS_BT_HI_TX_8822B(x) ((x) & (~BITS_STATIS_BT_HI_TX_8822B))
+#define BIT_GET_STATIS_BT_HI_TX_8822B(x) \
+ (((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8822B) & \
+ BIT_MASK_STATIS_BT_HI_TX_8822B)
+#define BIT_SET_STATIS_BT_HI_TX_8822B(x, v) \
+ (BIT_CLEAR_STATIS_BT_HI_TX_8822B(x) | BIT_STATIS_BT_HI_TX_8822B(v))
/* 2 REG_BT_STATISTICS_CONTROL_REGISTER_8822B */
#define BIT_SHIFT_R_BT_CMD_RPT_8822B 16
#define BIT_MASK_R_BT_CMD_RPT_8822B 0xffff
-#define BIT_R_BT_CMD_RPT_8822B(x) (((x) & BIT_MASK_R_BT_CMD_RPT_8822B) << BIT_SHIFT_R_BT_CMD_RPT_8822B)
-#define BIT_GET_R_BT_CMD_RPT_8822B(x) (((x) >> BIT_SHIFT_R_BT_CMD_RPT_8822B) & BIT_MASK_R_BT_CMD_RPT_8822B)
-
+#define BIT_R_BT_CMD_RPT_8822B(x) \
+ (((x) & BIT_MASK_R_BT_CMD_RPT_8822B) << BIT_SHIFT_R_BT_CMD_RPT_8822B)
+#define BITS_R_BT_CMD_RPT_8822B \
+ (BIT_MASK_R_BT_CMD_RPT_8822B << BIT_SHIFT_R_BT_CMD_RPT_8822B)
+#define BIT_CLEAR_R_BT_CMD_RPT_8822B(x) ((x) & (~BITS_R_BT_CMD_RPT_8822B))
+#define BIT_GET_R_BT_CMD_RPT_8822B(x) \
+ (((x) >> BIT_SHIFT_R_BT_CMD_RPT_8822B) & BIT_MASK_R_BT_CMD_RPT_8822B)
+#define BIT_SET_R_BT_CMD_RPT_8822B(x, v) \
+ (BIT_CLEAR_R_BT_CMD_RPT_8822B(x) | BIT_R_BT_CMD_RPT_8822B(v))
#define BIT_SHIFT_R_RPT_FROM_BT_8822B 8
#define BIT_MASK_R_RPT_FROM_BT_8822B 0xff
-#define BIT_R_RPT_FROM_BT_8822B(x) (((x) & BIT_MASK_R_RPT_FROM_BT_8822B) << BIT_SHIFT_R_RPT_FROM_BT_8822B)
-#define BIT_GET_R_RPT_FROM_BT_8822B(x) (((x) >> BIT_SHIFT_R_RPT_FROM_BT_8822B) & BIT_MASK_R_RPT_FROM_BT_8822B)
-
+#define BIT_R_RPT_FROM_BT_8822B(x) \
+ (((x) & BIT_MASK_R_RPT_FROM_BT_8822B) << BIT_SHIFT_R_RPT_FROM_BT_8822B)
+#define BITS_R_RPT_FROM_BT_8822B \
+ (BIT_MASK_R_RPT_FROM_BT_8822B << BIT_SHIFT_R_RPT_FROM_BT_8822B)
+#define BIT_CLEAR_R_RPT_FROM_BT_8822B(x) ((x) & (~BITS_R_RPT_FROM_BT_8822B))
+#define BIT_GET_R_RPT_FROM_BT_8822B(x) \
+ (((x) >> BIT_SHIFT_R_RPT_FROM_BT_8822B) & BIT_MASK_R_RPT_FROM_BT_8822B)
+#define BIT_SET_R_RPT_FROM_BT_8822B(x, v) \
+ (BIT_CLEAR_R_RPT_FROM_BT_8822B(x) | BIT_R_RPT_FROM_BT_8822B(v))
#define BIT_SHIFT_BT_HID_ISR_SET_8822B 6
#define BIT_MASK_BT_HID_ISR_SET_8822B 0x3
-#define BIT_BT_HID_ISR_SET_8822B(x) (((x) & BIT_MASK_BT_HID_ISR_SET_8822B) << BIT_SHIFT_BT_HID_ISR_SET_8822B)
-#define BIT_GET_BT_HID_ISR_SET_8822B(x) (((x) >> BIT_SHIFT_BT_HID_ISR_SET_8822B) & BIT_MASK_BT_HID_ISR_SET_8822B)
+#define BIT_BT_HID_ISR_SET_8822B(x) \
+ (((x) & BIT_MASK_BT_HID_ISR_SET_8822B) \
+ << BIT_SHIFT_BT_HID_ISR_SET_8822B)
+#define BITS_BT_HID_ISR_SET_8822B \
+ (BIT_MASK_BT_HID_ISR_SET_8822B << BIT_SHIFT_BT_HID_ISR_SET_8822B)
+#define BIT_CLEAR_BT_HID_ISR_SET_8822B(x) ((x) & (~BITS_BT_HID_ISR_SET_8822B))
+#define BIT_GET_BT_HID_ISR_SET_8822B(x) \
+ (((x) >> BIT_SHIFT_BT_HID_ISR_SET_8822B) & \
+ BIT_MASK_BT_HID_ISR_SET_8822B)
+#define BIT_SET_BT_HID_ISR_SET_8822B(x, v) \
+ (BIT_CLEAR_BT_HID_ISR_SET_8822B(x) | BIT_BT_HID_ISR_SET_8822B(v))
#define BIT_TDMA_BT_START_NOTIFY_8822B BIT(5)
#define BIT_ENABLE_TDMA_FW_MODE_8822B BIT(4)
@@ -9117,27 +16428,54 @@
#define BIT_SHIFT_BT_PROFILE_8822B 24
#define BIT_MASK_BT_PROFILE_8822B 0xff
-#define BIT_BT_PROFILE_8822B(x) (((x) & BIT_MASK_BT_PROFILE_8822B) << BIT_SHIFT_BT_PROFILE_8822B)
-#define BIT_GET_BT_PROFILE_8822B(x) (((x) >> BIT_SHIFT_BT_PROFILE_8822B) & BIT_MASK_BT_PROFILE_8822B)
-
+#define BIT_BT_PROFILE_8822B(x) \
+ (((x) & BIT_MASK_BT_PROFILE_8822B) << BIT_SHIFT_BT_PROFILE_8822B)
+#define BITS_BT_PROFILE_8822B \
+ (BIT_MASK_BT_PROFILE_8822B << BIT_SHIFT_BT_PROFILE_8822B)
+#define BIT_CLEAR_BT_PROFILE_8822B(x) ((x) & (~BITS_BT_PROFILE_8822B))
+#define BIT_GET_BT_PROFILE_8822B(x) \
+ (((x) >> BIT_SHIFT_BT_PROFILE_8822B) & BIT_MASK_BT_PROFILE_8822B)
+#define BIT_SET_BT_PROFILE_8822B(x, v) \
+ (BIT_CLEAR_BT_PROFILE_8822B(x) | BIT_BT_PROFILE_8822B(v))
#define BIT_SHIFT_BT_POWER_8822B 16
#define BIT_MASK_BT_POWER_8822B 0xff
-#define BIT_BT_POWER_8822B(x) (((x) & BIT_MASK_BT_POWER_8822B) << BIT_SHIFT_BT_POWER_8822B)
-#define BIT_GET_BT_POWER_8822B(x) (((x) >> BIT_SHIFT_BT_POWER_8822B) & BIT_MASK_BT_POWER_8822B)
-
+#define BIT_BT_POWER_8822B(x) \
+ (((x) & BIT_MASK_BT_POWER_8822B) << BIT_SHIFT_BT_POWER_8822B)
+#define BITS_BT_POWER_8822B \
+ (BIT_MASK_BT_POWER_8822B << BIT_SHIFT_BT_POWER_8822B)
+#define BIT_CLEAR_BT_POWER_8822B(x) ((x) & (~BITS_BT_POWER_8822B))
+#define BIT_GET_BT_POWER_8822B(x) \
+ (((x) >> BIT_SHIFT_BT_POWER_8822B) & BIT_MASK_BT_POWER_8822B)
+#define BIT_SET_BT_POWER_8822B(x, v) \
+ (BIT_CLEAR_BT_POWER_8822B(x) | BIT_BT_POWER_8822B(v))
#define BIT_SHIFT_BT_PREDECT_STATUS_8822B 8
#define BIT_MASK_BT_PREDECT_STATUS_8822B 0xff
-#define BIT_BT_PREDECT_STATUS_8822B(x) (((x) & BIT_MASK_BT_PREDECT_STATUS_8822B) << BIT_SHIFT_BT_PREDECT_STATUS_8822B)
-#define BIT_GET_BT_PREDECT_STATUS_8822B(x) (((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8822B) & BIT_MASK_BT_PREDECT_STATUS_8822B)
-
+#define BIT_BT_PREDECT_STATUS_8822B(x) \
+ (((x) & BIT_MASK_BT_PREDECT_STATUS_8822B) \
+ << BIT_SHIFT_BT_PREDECT_STATUS_8822B)
+#define BITS_BT_PREDECT_STATUS_8822B \
+ (BIT_MASK_BT_PREDECT_STATUS_8822B << BIT_SHIFT_BT_PREDECT_STATUS_8822B)
+#define BIT_CLEAR_BT_PREDECT_STATUS_8822B(x) \
+ ((x) & (~BITS_BT_PREDECT_STATUS_8822B))
+#define BIT_GET_BT_PREDECT_STATUS_8822B(x) \
+ (((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8822B) & \
+ BIT_MASK_BT_PREDECT_STATUS_8822B)
+#define BIT_SET_BT_PREDECT_STATUS_8822B(x, v) \
+ (BIT_CLEAR_BT_PREDECT_STATUS_8822B(x) | BIT_BT_PREDECT_STATUS_8822B(v))
#define BIT_SHIFT_BT_CMD_INFO_8822B 0
#define BIT_MASK_BT_CMD_INFO_8822B 0xff
-#define BIT_BT_CMD_INFO_8822B(x) (((x) & BIT_MASK_BT_CMD_INFO_8822B) << BIT_SHIFT_BT_CMD_INFO_8822B)
-#define BIT_GET_BT_CMD_INFO_8822B(x) (((x) >> BIT_SHIFT_BT_CMD_INFO_8822B) & BIT_MASK_BT_CMD_INFO_8822B)
-
+#define BIT_BT_CMD_INFO_8822B(x) \
+ (((x) & BIT_MASK_BT_CMD_INFO_8822B) << BIT_SHIFT_BT_CMD_INFO_8822B)
+#define BITS_BT_CMD_INFO_8822B \
+ (BIT_MASK_BT_CMD_INFO_8822B << BIT_SHIFT_BT_CMD_INFO_8822B)
+#define BIT_CLEAR_BT_CMD_INFO_8822B(x) ((x) & (~BITS_BT_CMD_INFO_8822B))
+#define BIT_GET_BT_CMD_INFO_8822B(x) \
+ (((x) >> BIT_SHIFT_BT_CMD_INFO_8822B) & BIT_MASK_BT_CMD_INFO_8822B)
+#define BIT_SET_BT_CMD_INFO_8822B(x, v) \
+ (BIT_CLEAR_BT_CMD_INFO_8822B(x) | BIT_BT_CMD_INFO_8822B(v))
/* 2 REG_BT_INTERRUPT_CONTROL_REGISTER_8822B */
#define BIT_EN_MAC_NULL_PKT_NOTIFY_8822B BIT(31)
@@ -9151,36 +16489,65 @@
#define BIT_SHIFT_WLAN_RPT_DATA_8822B 16
#define BIT_MASK_WLAN_RPT_DATA_8822B 0xff
-#define BIT_WLAN_RPT_DATA_8822B(x) (((x) & BIT_MASK_WLAN_RPT_DATA_8822B) << BIT_SHIFT_WLAN_RPT_DATA_8822B)
-#define BIT_GET_WLAN_RPT_DATA_8822B(x) (((x) >> BIT_SHIFT_WLAN_RPT_DATA_8822B) & BIT_MASK_WLAN_RPT_DATA_8822B)
-
+#define BIT_WLAN_RPT_DATA_8822B(x) \
+ (((x) & BIT_MASK_WLAN_RPT_DATA_8822B) << BIT_SHIFT_WLAN_RPT_DATA_8822B)
+#define BITS_WLAN_RPT_DATA_8822B \
+ (BIT_MASK_WLAN_RPT_DATA_8822B << BIT_SHIFT_WLAN_RPT_DATA_8822B)
+#define BIT_CLEAR_WLAN_RPT_DATA_8822B(x) ((x) & (~BITS_WLAN_RPT_DATA_8822B))
+#define BIT_GET_WLAN_RPT_DATA_8822B(x) \
+ (((x) >> BIT_SHIFT_WLAN_RPT_DATA_8822B) & BIT_MASK_WLAN_RPT_DATA_8822B)
+#define BIT_SET_WLAN_RPT_DATA_8822B(x, v) \
+ (BIT_CLEAR_WLAN_RPT_DATA_8822B(x) | BIT_WLAN_RPT_DATA_8822B(v))
#define BIT_SHIFT_CMD_ID_8822B 8
#define BIT_MASK_CMD_ID_8822B 0xff
-#define BIT_CMD_ID_8822B(x) (((x) & BIT_MASK_CMD_ID_8822B) << BIT_SHIFT_CMD_ID_8822B)
-#define BIT_GET_CMD_ID_8822B(x) (((x) >> BIT_SHIFT_CMD_ID_8822B) & BIT_MASK_CMD_ID_8822B)
-
+#define BIT_CMD_ID_8822B(x) \
+ (((x) & BIT_MASK_CMD_ID_8822B) << BIT_SHIFT_CMD_ID_8822B)
+#define BITS_CMD_ID_8822B (BIT_MASK_CMD_ID_8822B << BIT_SHIFT_CMD_ID_8822B)
+#define BIT_CLEAR_CMD_ID_8822B(x) ((x) & (~BITS_CMD_ID_8822B))
+#define BIT_GET_CMD_ID_8822B(x) \
+ (((x) >> BIT_SHIFT_CMD_ID_8822B) & BIT_MASK_CMD_ID_8822B)
+#define BIT_SET_CMD_ID_8822B(x, v) \
+ (BIT_CLEAR_CMD_ID_8822B(x) | BIT_CMD_ID_8822B(v))
#define BIT_SHIFT_BT_DATA_8822B 0
#define BIT_MASK_BT_DATA_8822B 0xff
-#define BIT_BT_DATA_8822B(x) (((x) & BIT_MASK_BT_DATA_8822B) << BIT_SHIFT_BT_DATA_8822B)
-#define BIT_GET_BT_DATA_8822B(x) (((x) >> BIT_SHIFT_BT_DATA_8822B) & BIT_MASK_BT_DATA_8822B)
-
+#define BIT_BT_DATA_8822B(x) \
+ (((x) & BIT_MASK_BT_DATA_8822B) << BIT_SHIFT_BT_DATA_8822B)
+#define BITS_BT_DATA_8822B (BIT_MASK_BT_DATA_8822B << BIT_SHIFT_BT_DATA_8822B)
+#define BIT_CLEAR_BT_DATA_8822B(x) ((x) & (~BITS_BT_DATA_8822B))
+#define BIT_GET_BT_DATA_8822B(x) \
+ (((x) >> BIT_SHIFT_BT_DATA_8822B) & BIT_MASK_BT_DATA_8822B)
+#define BIT_SET_BT_DATA_8822B(x, v) \
+ (BIT_CLEAR_BT_DATA_8822B(x) | BIT_BT_DATA_8822B(v))
/* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8822B */
#define BIT_SHIFT_WLAN_RPT_TO_8822B 0
#define BIT_MASK_WLAN_RPT_TO_8822B 0xff
-#define BIT_WLAN_RPT_TO_8822B(x) (((x) & BIT_MASK_WLAN_RPT_TO_8822B) << BIT_SHIFT_WLAN_RPT_TO_8822B)
-#define BIT_GET_WLAN_RPT_TO_8822B(x) (((x) >> BIT_SHIFT_WLAN_RPT_TO_8822B) & BIT_MASK_WLAN_RPT_TO_8822B)
-
+#define BIT_WLAN_RPT_TO_8822B(x) \
+ (((x) & BIT_MASK_WLAN_RPT_TO_8822B) << BIT_SHIFT_WLAN_RPT_TO_8822B)
+#define BITS_WLAN_RPT_TO_8822B \
+ (BIT_MASK_WLAN_RPT_TO_8822B << BIT_SHIFT_WLAN_RPT_TO_8822B)
+#define BIT_CLEAR_WLAN_RPT_TO_8822B(x) ((x) & (~BITS_WLAN_RPT_TO_8822B))
+#define BIT_GET_WLAN_RPT_TO_8822B(x) \
+ (((x) >> BIT_SHIFT_WLAN_RPT_TO_8822B) & BIT_MASK_WLAN_RPT_TO_8822B)
+#define BIT_SET_WLAN_RPT_TO_8822B(x, v) \
+ (BIT_CLEAR_WLAN_RPT_TO_8822B(x) | BIT_WLAN_RPT_TO_8822B(v))
/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8822B */
#define BIT_SHIFT_ISOLATION_CHK_8822B 1
#define BIT_MASK_ISOLATION_CHK_8822B 0x7fffffffffffffffffffL
-#define BIT_ISOLATION_CHK_8822B(x) (((x) & BIT_MASK_ISOLATION_CHK_8822B) << BIT_SHIFT_ISOLATION_CHK_8822B)
-#define BIT_GET_ISOLATION_CHK_8822B(x) (((x) >> BIT_SHIFT_ISOLATION_CHK_8822B) & BIT_MASK_ISOLATION_CHK_8822B)
+#define BIT_ISOLATION_CHK_8822B(x) \
+ (((x) & BIT_MASK_ISOLATION_CHK_8822B) << BIT_SHIFT_ISOLATION_CHK_8822B)
+#define BITS_ISOLATION_CHK_8822B \
+ (BIT_MASK_ISOLATION_CHK_8822B << BIT_SHIFT_ISOLATION_CHK_8822B)
+#define BIT_CLEAR_ISOLATION_CHK_8822B(x) ((x) & (~BITS_ISOLATION_CHK_8822B))
+#define BIT_GET_ISOLATION_CHK_8822B(x) \
+ (((x) >> BIT_SHIFT_ISOLATION_CHK_8822B) & BIT_MASK_ISOLATION_CHK_8822B)
+#define BIT_SET_ISOLATION_CHK_8822B(x, v) \
+ (BIT_CLEAR_ISOLATION_CHK_8822B(x) | BIT_ISOLATION_CHK_8822B(v))
#define BIT_ISOLATION_EN_8822B BIT(0)
@@ -9198,22 +16565,45 @@
#define BIT_SHIFT_BT_TIME_8822B 6
#define BIT_MASK_BT_TIME_8822B 0x3ffffff
-#define BIT_BT_TIME_8822B(x) (((x) & BIT_MASK_BT_TIME_8822B) << BIT_SHIFT_BT_TIME_8822B)
-#define BIT_GET_BT_TIME_8822B(x) (((x) >> BIT_SHIFT_BT_TIME_8822B) & BIT_MASK_BT_TIME_8822B)
-
+#define BIT_BT_TIME_8822B(x) \
+ (((x) & BIT_MASK_BT_TIME_8822B) << BIT_SHIFT_BT_TIME_8822B)
+#define BITS_BT_TIME_8822B (BIT_MASK_BT_TIME_8822B << BIT_SHIFT_BT_TIME_8822B)
+#define BIT_CLEAR_BT_TIME_8822B(x) ((x) & (~BITS_BT_TIME_8822B))
+#define BIT_GET_BT_TIME_8822B(x) \
+ (((x) >> BIT_SHIFT_BT_TIME_8822B) & BIT_MASK_BT_TIME_8822B)
+#define BIT_SET_BT_TIME_8822B(x, v) \
+ (BIT_CLEAR_BT_TIME_8822B(x) | BIT_BT_TIME_8822B(v))
#define BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822B 0
#define BIT_MASK_BT_RPT_SAMPLE_RATE_8822B 0x3f
-#define BIT_BT_RPT_SAMPLE_RATE_8822B(x) (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8822B) << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822B)
-#define BIT_GET_BT_RPT_SAMPLE_RATE_8822B(x) (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822B) & BIT_MASK_BT_RPT_SAMPLE_RATE_8822B)
-
+#define BIT_BT_RPT_SAMPLE_RATE_8822B(x) \
+ (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8822B) \
+ << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822B)
+#define BITS_BT_RPT_SAMPLE_RATE_8822B \
+ (BIT_MASK_BT_RPT_SAMPLE_RATE_8822B \
+ << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822B)
+#define BIT_CLEAR_BT_RPT_SAMPLE_RATE_8822B(x) \
+ ((x) & (~BITS_BT_RPT_SAMPLE_RATE_8822B))
+#define BIT_GET_BT_RPT_SAMPLE_RATE_8822B(x) \
+ (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822B) & \
+ BIT_MASK_BT_RPT_SAMPLE_RATE_8822B)
+#define BIT_SET_BT_RPT_SAMPLE_RATE_8822B(x, v) \
+ (BIT_CLEAR_BT_RPT_SAMPLE_RATE_8822B(x) | \
+ BIT_BT_RPT_SAMPLE_RATE_8822B(v))
/* 2 REG_BT_ACT_REGISTER_8822B */
#define BIT_SHIFT_BT_EISR_EN_8822B 16
#define BIT_MASK_BT_EISR_EN_8822B 0xff
-#define BIT_BT_EISR_EN_8822B(x) (((x) & BIT_MASK_BT_EISR_EN_8822B) << BIT_SHIFT_BT_EISR_EN_8822B)
-#define BIT_GET_BT_EISR_EN_8822B(x) (((x) >> BIT_SHIFT_BT_EISR_EN_8822B) & BIT_MASK_BT_EISR_EN_8822B)
+#define BIT_BT_EISR_EN_8822B(x) \
+ (((x) & BIT_MASK_BT_EISR_EN_8822B) << BIT_SHIFT_BT_EISR_EN_8822B)
+#define BITS_BT_EISR_EN_8822B \
+ (BIT_MASK_BT_EISR_EN_8822B << BIT_SHIFT_BT_EISR_EN_8822B)
+#define BIT_CLEAR_BT_EISR_EN_8822B(x) ((x) & (~BITS_BT_EISR_EN_8822B))
+#define BIT_GET_BT_EISR_EN_8822B(x) \
+ (((x) >> BIT_SHIFT_BT_EISR_EN_8822B) & BIT_MASK_BT_EISR_EN_8822B)
+#define BIT_SET_BT_EISR_EN_8822B(x, v) \
+ (BIT_CLEAR_BT_EISR_EN_8822B(x) | BIT_BT_EISR_EN_8822B(v))
#define BIT_BT_ACT_FALLING_ISR_8822B BIT(10)
#define BIT_BT_ACT_RISING_ISR_8822B BIT(9)
@@ -9221,17 +16611,29 @@
#define BIT_SHIFT_BT_CH_8822B 0
#define BIT_MASK_BT_CH_8822B 0xff
-#define BIT_BT_CH_8822B(x) (((x) & BIT_MASK_BT_CH_8822B) << BIT_SHIFT_BT_CH_8822B)
-#define BIT_GET_BT_CH_8822B(x) (((x) >> BIT_SHIFT_BT_CH_8822B) & BIT_MASK_BT_CH_8822B)
-
+#define BIT_BT_CH_8822B(x) \
+ (((x) & BIT_MASK_BT_CH_8822B) << BIT_SHIFT_BT_CH_8822B)
+#define BITS_BT_CH_8822B (BIT_MASK_BT_CH_8822B << BIT_SHIFT_BT_CH_8822B)
+#define BIT_CLEAR_BT_CH_8822B(x) ((x) & (~BITS_BT_CH_8822B))
+#define BIT_GET_BT_CH_8822B(x) \
+ (((x) >> BIT_SHIFT_BT_CH_8822B) & BIT_MASK_BT_CH_8822B)
+#define BIT_SET_BT_CH_8822B(x, v) \
+ (BIT_CLEAR_BT_CH_8822B(x) | BIT_BT_CH_8822B(v))
/* 2 REG_OBFF_CTRL_BASIC_8822B */
#define BIT_OBFF_EN_V1_8822B BIT(31)
#define BIT_SHIFT_OBFF_STATE_V1_8822B 28
#define BIT_MASK_OBFF_STATE_V1_8822B 0x3
-#define BIT_OBFF_STATE_V1_8822B(x) (((x) & BIT_MASK_OBFF_STATE_V1_8822B) << BIT_SHIFT_OBFF_STATE_V1_8822B)
-#define BIT_GET_OBFF_STATE_V1_8822B(x) (((x) >> BIT_SHIFT_OBFF_STATE_V1_8822B) & BIT_MASK_OBFF_STATE_V1_8822B)
+#define BIT_OBFF_STATE_V1_8822B(x) \
+ (((x) & BIT_MASK_OBFF_STATE_V1_8822B) << BIT_SHIFT_OBFF_STATE_V1_8822B)
+#define BITS_OBFF_STATE_V1_8822B \
+ (BIT_MASK_OBFF_STATE_V1_8822B << BIT_SHIFT_OBFF_STATE_V1_8822B)
+#define BIT_CLEAR_OBFF_STATE_V1_8822B(x) ((x) & (~BITS_OBFF_STATE_V1_8822B))
+#define BIT_GET_OBFF_STATE_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_OBFF_STATE_V1_8822B) & BIT_MASK_OBFF_STATE_V1_8822B)
+#define BIT_SET_OBFF_STATE_V1_8822B(x, v) \
+ (BIT_CLEAR_OBFF_STATE_V1_8822B(x) | BIT_OBFF_STATE_V1_8822B(v))
#define BIT_OBFF_ACT_RXDMA_EN_8822B BIT(27)
#define BIT_OBFF_BLOCK_INT_EN_8822B BIT(26)
@@ -9240,26 +16642,51 @@
#define BIT_SHIFT_WAKE_MAX_PLS_8822B 20
#define BIT_MASK_WAKE_MAX_PLS_8822B 0x7
-#define BIT_WAKE_MAX_PLS_8822B(x) (((x) & BIT_MASK_WAKE_MAX_PLS_8822B) << BIT_SHIFT_WAKE_MAX_PLS_8822B)
-#define BIT_GET_WAKE_MAX_PLS_8822B(x) (((x) >> BIT_SHIFT_WAKE_MAX_PLS_8822B) & BIT_MASK_WAKE_MAX_PLS_8822B)
-
+#define BIT_WAKE_MAX_PLS_8822B(x) \
+ (((x) & BIT_MASK_WAKE_MAX_PLS_8822B) << BIT_SHIFT_WAKE_MAX_PLS_8822B)
+#define BITS_WAKE_MAX_PLS_8822B \
+ (BIT_MASK_WAKE_MAX_PLS_8822B << BIT_SHIFT_WAKE_MAX_PLS_8822B)
+#define BIT_CLEAR_WAKE_MAX_PLS_8822B(x) ((x) & (~BITS_WAKE_MAX_PLS_8822B))
+#define BIT_GET_WAKE_MAX_PLS_8822B(x) \
+ (((x) >> BIT_SHIFT_WAKE_MAX_PLS_8822B) & BIT_MASK_WAKE_MAX_PLS_8822B)
+#define BIT_SET_WAKE_MAX_PLS_8822B(x, v) \
+ (BIT_CLEAR_WAKE_MAX_PLS_8822B(x) | BIT_WAKE_MAX_PLS_8822B(v))
#define BIT_SHIFT_WAKE_MIN_PLS_8822B 16
#define BIT_MASK_WAKE_MIN_PLS_8822B 0x7
-#define BIT_WAKE_MIN_PLS_8822B(x) (((x) & BIT_MASK_WAKE_MIN_PLS_8822B) << BIT_SHIFT_WAKE_MIN_PLS_8822B)
-#define BIT_GET_WAKE_MIN_PLS_8822B(x) (((x) >> BIT_SHIFT_WAKE_MIN_PLS_8822B) & BIT_MASK_WAKE_MIN_PLS_8822B)
-
+#define BIT_WAKE_MIN_PLS_8822B(x) \
+ (((x) & BIT_MASK_WAKE_MIN_PLS_8822B) << BIT_SHIFT_WAKE_MIN_PLS_8822B)
+#define BITS_WAKE_MIN_PLS_8822B \
+ (BIT_MASK_WAKE_MIN_PLS_8822B << BIT_SHIFT_WAKE_MIN_PLS_8822B)
+#define BIT_CLEAR_WAKE_MIN_PLS_8822B(x) ((x) & (~BITS_WAKE_MIN_PLS_8822B))
+#define BIT_GET_WAKE_MIN_PLS_8822B(x) \
+ (((x) >> BIT_SHIFT_WAKE_MIN_PLS_8822B) & BIT_MASK_WAKE_MIN_PLS_8822B)
+#define BIT_SET_WAKE_MIN_PLS_8822B(x, v) \
+ (BIT_CLEAR_WAKE_MIN_PLS_8822B(x) | BIT_WAKE_MIN_PLS_8822B(v))
#define BIT_SHIFT_WAKE_MAX_F2F_8822B 12
#define BIT_MASK_WAKE_MAX_F2F_8822B 0x7
-#define BIT_WAKE_MAX_F2F_8822B(x) (((x) & BIT_MASK_WAKE_MAX_F2F_8822B) << BIT_SHIFT_WAKE_MAX_F2F_8822B)
-#define BIT_GET_WAKE_MAX_F2F_8822B(x) (((x) >> BIT_SHIFT_WAKE_MAX_F2F_8822B) & BIT_MASK_WAKE_MAX_F2F_8822B)
-
+#define BIT_WAKE_MAX_F2F_8822B(x) \
+ (((x) & BIT_MASK_WAKE_MAX_F2F_8822B) << BIT_SHIFT_WAKE_MAX_F2F_8822B)
+#define BITS_WAKE_MAX_F2F_8822B \
+ (BIT_MASK_WAKE_MAX_F2F_8822B << BIT_SHIFT_WAKE_MAX_F2F_8822B)
+#define BIT_CLEAR_WAKE_MAX_F2F_8822B(x) ((x) & (~BITS_WAKE_MAX_F2F_8822B))
+#define BIT_GET_WAKE_MAX_F2F_8822B(x) \
+ (((x) >> BIT_SHIFT_WAKE_MAX_F2F_8822B) & BIT_MASK_WAKE_MAX_F2F_8822B)
+#define BIT_SET_WAKE_MAX_F2F_8822B(x, v) \
+ (BIT_CLEAR_WAKE_MAX_F2F_8822B(x) | BIT_WAKE_MAX_F2F_8822B(v))
#define BIT_SHIFT_WAKE_MIN_F2F_8822B 8
#define BIT_MASK_WAKE_MIN_F2F_8822B 0x7
-#define BIT_WAKE_MIN_F2F_8822B(x) (((x) & BIT_MASK_WAKE_MIN_F2F_8822B) << BIT_SHIFT_WAKE_MIN_F2F_8822B)
-#define BIT_GET_WAKE_MIN_F2F_8822B(x) (((x) >> BIT_SHIFT_WAKE_MIN_F2F_8822B) & BIT_MASK_WAKE_MIN_F2F_8822B)
+#define BIT_WAKE_MIN_F2F_8822B(x) \
+ (((x) & BIT_MASK_WAKE_MIN_F2F_8822B) << BIT_SHIFT_WAKE_MIN_F2F_8822B)
+#define BITS_WAKE_MIN_F2F_8822B \
+ (BIT_MASK_WAKE_MIN_F2F_8822B << BIT_SHIFT_WAKE_MIN_F2F_8822B)
+#define BIT_CLEAR_WAKE_MIN_F2F_8822B(x) ((x) & (~BITS_WAKE_MIN_F2F_8822B))
+#define BIT_GET_WAKE_MIN_F2F_8822B(x) \
+ (((x) >> BIT_SHIFT_WAKE_MIN_F2F_8822B) & BIT_MASK_WAKE_MIN_F2F_8822B)
+#define BIT_SET_WAKE_MIN_F2F_8822B(x, v) \
+ (BIT_CLEAR_WAKE_MIN_F2F_8822B(x) | BIT_WAKE_MIN_F2F_8822B(v))
#define BIT_APP_CPU_ACT_V1_8822B BIT(3)
#define BIT_APP_OBFF_V1_8822B BIT(2)
@@ -9270,27 +16697,65 @@
#define BIT_SHIFT_RX_HIGH_TIMER_IDX_8822B 24
#define BIT_MASK_RX_HIGH_TIMER_IDX_8822B 0x7
-#define BIT_RX_HIGH_TIMER_IDX_8822B(x) (((x) & BIT_MASK_RX_HIGH_TIMER_IDX_8822B) << BIT_SHIFT_RX_HIGH_TIMER_IDX_8822B)
-#define BIT_GET_RX_HIGH_TIMER_IDX_8822B(x) (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8822B) & BIT_MASK_RX_HIGH_TIMER_IDX_8822B)
-
+#define BIT_RX_HIGH_TIMER_IDX_8822B(x) \
+ (((x) & BIT_MASK_RX_HIGH_TIMER_IDX_8822B) \
+ << BIT_SHIFT_RX_HIGH_TIMER_IDX_8822B)
+#define BITS_RX_HIGH_TIMER_IDX_8822B \
+ (BIT_MASK_RX_HIGH_TIMER_IDX_8822B << BIT_SHIFT_RX_HIGH_TIMER_IDX_8822B)
+#define BIT_CLEAR_RX_HIGH_TIMER_IDX_8822B(x) \
+ ((x) & (~BITS_RX_HIGH_TIMER_IDX_8822B))
+#define BIT_GET_RX_HIGH_TIMER_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8822B) & \
+ BIT_MASK_RX_HIGH_TIMER_IDX_8822B)
+#define BIT_SET_RX_HIGH_TIMER_IDX_8822B(x, v) \
+ (BIT_CLEAR_RX_HIGH_TIMER_IDX_8822B(x) | BIT_RX_HIGH_TIMER_IDX_8822B(v))
#define BIT_SHIFT_RX_MED_TIMER_IDX_8822B 16
#define BIT_MASK_RX_MED_TIMER_IDX_8822B 0x7
-#define BIT_RX_MED_TIMER_IDX_8822B(x) (((x) & BIT_MASK_RX_MED_TIMER_IDX_8822B) << BIT_SHIFT_RX_MED_TIMER_IDX_8822B)
-#define BIT_GET_RX_MED_TIMER_IDX_8822B(x) (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8822B) & BIT_MASK_RX_MED_TIMER_IDX_8822B)
-
+#define BIT_RX_MED_TIMER_IDX_8822B(x) \
+ (((x) & BIT_MASK_RX_MED_TIMER_IDX_8822B) \
+ << BIT_SHIFT_RX_MED_TIMER_IDX_8822B)
+#define BITS_RX_MED_TIMER_IDX_8822B \
+ (BIT_MASK_RX_MED_TIMER_IDX_8822B << BIT_SHIFT_RX_MED_TIMER_IDX_8822B)
+#define BIT_CLEAR_RX_MED_TIMER_IDX_8822B(x) \
+ ((x) & (~BITS_RX_MED_TIMER_IDX_8822B))
+#define BIT_GET_RX_MED_TIMER_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8822B) & \
+ BIT_MASK_RX_MED_TIMER_IDX_8822B)
+#define BIT_SET_RX_MED_TIMER_IDX_8822B(x, v) \
+ (BIT_CLEAR_RX_MED_TIMER_IDX_8822B(x) | BIT_RX_MED_TIMER_IDX_8822B(v))
#define BIT_SHIFT_RX_LOW_TIMER_IDX_8822B 8
#define BIT_MASK_RX_LOW_TIMER_IDX_8822B 0x7
-#define BIT_RX_LOW_TIMER_IDX_8822B(x) (((x) & BIT_MASK_RX_LOW_TIMER_IDX_8822B) << BIT_SHIFT_RX_LOW_TIMER_IDX_8822B)
-#define BIT_GET_RX_LOW_TIMER_IDX_8822B(x) (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8822B) & BIT_MASK_RX_LOW_TIMER_IDX_8822B)
-
+#define BIT_RX_LOW_TIMER_IDX_8822B(x) \
+ (((x) & BIT_MASK_RX_LOW_TIMER_IDX_8822B) \
+ << BIT_SHIFT_RX_LOW_TIMER_IDX_8822B)
+#define BITS_RX_LOW_TIMER_IDX_8822B \
+ (BIT_MASK_RX_LOW_TIMER_IDX_8822B << BIT_SHIFT_RX_LOW_TIMER_IDX_8822B)
+#define BIT_CLEAR_RX_LOW_TIMER_IDX_8822B(x) \
+ ((x) & (~BITS_RX_LOW_TIMER_IDX_8822B))
+#define BIT_GET_RX_LOW_TIMER_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8822B) & \
+ BIT_MASK_RX_LOW_TIMER_IDX_8822B)
+#define BIT_SET_RX_LOW_TIMER_IDX_8822B(x, v) \
+ (BIT_CLEAR_RX_LOW_TIMER_IDX_8822B(x) | BIT_RX_LOW_TIMER_IDX_8822B(v))
#define BIT_SHIFT_OBFF_INT_TIMER_IDX_8822B 0
#define BIT_MASK_OBFF_INT_TIMER_IDX_8822B 0x7
-#define BIT_OBFF_INT_TIMER_IDX_8822B(x) (((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8822B) << BIT_SHIFT_OBFF_INT_TIMER_IDX_8822B)
-#define BIT_GET_OBFF_INT_TIMER_IDX_8822B(x) (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8822B) & BIT_MASK_OBFF_INT_TIMER_IDX_8822B)
-
+#define BIT_OBFF_INT_TIMER_IDX_8822B(x) \
+ (((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8822B) \
+ << BIT_SHIFT_OBFF_INT_TIMER_IDX_8822B)
+#define BITS_OBFF_INT_TIMER_IDX_8822B \
+ (BIT_MASK_OBFF_INT_TIMER_IDX_8822B \
+ << BIT_SHIFT_OBFF_INT_TIMER_IDX_8822B)
+#define BIT_CLEAR_OBFF_INT_TIMER_IDX_8822B(x) \
+ ((x) & (~BITS_OBFF_INT_TIMER_IDX_8822B))
+#define BIT_GET_OBFF_INT_TIMER_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8822B) & \
+ BIT_MASK_OBFF_INT_TIMER_IDX_8822B)
+#define BIT_SET_OBFF_INT_TIMER_IDX_8822B(x, v) \
+ (BIT_CLEAR_OBFF_INT_TIMER_IDX_8822B(x) | \
+ BIT_OBFF_INT_TIMER_IDX_8822B(v))
/* 2 REG_LTR_CTRL_BASIC_8822B */
#define BIT_LTR_EN_V1_8822B BIT(31)
@@ -9306,93 +16771,207 @@
#define BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822B 20
#define BIT_MASK_HIGH_RATE_TRIG_SEL_8822B 0x3
-#define BIT_HIGH_RATE_TRIG_SEL_8822B(x) (((x) & BIT_MASK_HIGH_RATE_TRIG_SEL_8822B) << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822B)
-#define BIT_GET_HIGH_RATE_TRIG_SEL_8822B(x) (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822B) & BIT_MASK_HIGH_RATE_TRIG_SEL_8822B)
-
+#define BIT_HIGH_RATE_TRIG_SEL_8822B(x) \
+ (((x) & BIT_MASK_HIGH_RATE_TRIG_SEL_8822B) \
+ << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822B)
+#define BITS_HIGH_RATE_TRIG_SEL_8822B \
+ (BIT_MASK_HIGH_RATE_TRIG_SEL_8822B \
+ << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822B)
+#define BIT_CLEAR_HIGH_RATE_TRIG_SEL_8822B(x) \
+ ((x) & (~BITS_HIGH_RATE_TRIG_SEL_8822B))
+#define BIT_GET_HIGH_RATE_TRIG_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822B) & \
+ BIT_MASK_HIGH_RATE_TRIG_SEL_8822B)
+#define BIT_SET_HIGH_RATE_TRIG_SEL_8822B(x, v) \
+ (BIT_CLEAR_HIGH_RATE_TRIG_SEL_8822B(x) | \
+ BIT_HIGH_RATE_TRIG_SEL_8822B(v))
#define BIT_SHIFT_MED_RATE_TRIG_SEL_8822B 18
#define BIT_MASK_MED_RATE_TRIG_SEL_8822B 0x3
-#define BIT_MED_RATE_TRIG_SEL_8822B(x) (((x) & BIT_MASK_MED_RATE_TRIG_SEL_8822B) << BIT_SHIFT_MED_RATE_TRIG_SEL_8822B)
-#define BIT_GET_MED_RATE_TRIG_SEL_8822B(x) (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8822B) & BIT_MASK_MED_RATE_TRIG_SEL_8822B)
-
+#define BIT_MED_RATE_TRIG_SEL_8822B(x) \
+ (((x) & BIT_MASK_MED_RATE_TRIG_SEL_8822B) \
+ << BIT_SHIFT_MED_RATE_TRIG_SEL_8822B)
+#define BITS_MED_RATE_TRIG_SEL_8822B \
+ (BIT_MASK_MED_RATE_TRIG_SEL_8822B << BIT_SHIFT_MED_RATE_TRIG_SEL_8822B)
+#define BIT_CLEAR_MED_RATE_TRIG_SEL_8822B(x) \
+ ((x) & (~BITS_MED_RATE_TRIG_SEL_8822B))
+#define BIT_GET_MED_RATE_TRIG_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8822B) & \
+ BIT_MASK_MED_RATE_TRIG_SEL_8822B)
+#define BIT_SET_MED_RATE_TRIG_SEL_8822B(x, v) \
+ (BIT_CLEAR_MED_RATE_TRIG_SEL_8822B(x) | BIT_MED_RATE_TRIG_SEL_8822B(v))
#define BIT_SHIFT_LOW_RATE_TRIG_SEL_8822B 16
#define BIT_MASK_LOW_RATE_TRIG_SEL_8822B 0x3
-#define BIT_LOW_RATE_TRIG_SEL_8822B(x) (((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8822B) << BIT_SHIFT_LOW_RATE_TRIG_SEL_8822B)
-#define BIT_GET_LOW_RATE_TRIG_SEL_8822B(x) (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8822B) & BIT_MASK_LOW_RATE_TRIG_SEL_8822B)
-
+#define BIT_LOW_RATE_TRIG_SEL_8822B(x) \
+ (((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8822B) \
+ << BIT_SHIFT_LOW_RATE_TRIG_SEL_8822B)
+#define BITS_LOW_RATE_TRIG_SEL_8822B \
+ (BIT_MASK_LOW_RATE_TRIG_SEL_8822B << BIT_SHIFT_LOW_RATE_TRIG_SEL_8822B)
+#define BIT_CLEAR_LOW_RATE_TRIG_SEL_8822B(x) \
+ ((x) & (~BITS_LOW_RATE_TRIG_SEL_8822B))
+#define BIT_GET_LOW_RATE_TRIG_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8822B) & \
+ BIT_MASK_LOW_RATE_TRIG_SEL_8822B)
+#define BIT_SET_LOW_RATE_TRIG_SEL_8822B(x, v) \
+ (BIT_CLEAR_LOW_RATE_TRIG_SEL_8822B(x) | BIT_LOW_RATE_TRIG_SEL_8822B(v))
#define BIT_SHIFT_HIGH_RATE_BD_IDX_8822B 8
#define BIT_MASK_HIGH_RATE_BD_IDX_8822B 0x7f
-#define BIT_HIGH_RATE_BD_IDX_8822B(x) (((x) & BIT_MASK_HIGH_RATE_BD_IDX_8822B) << BIT_SHIFT_HIGH_RATE_BD_IDX_8822B)
-#define BIT_GET_HIGH_RATE_BD_IDX_8822B(x) (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8822B) & BIT_MASK_HIGH_RATE_BD_IDX_8822B)
-
+#define BIT_HIGH_RATE_BD_IDX_8822B(x) \
+ (((x) & BIT_MASK_HIGH_RATE_BD_IDX_8822B) \
+ << BIT_SHIFT_HIGH_RATE_BD_IDX_8822B)
+#define BITS_HIGH_RATE_BD_IDX_8822B \
+ (BIT_MASK_HIGH_RATE_BD_IDX_8822B << BIT_SHIFT_HIGH_RATE_BD_IDX_8822B)
+#define BIT_CLEAR_HIGH_RATE_BD_IDX_8822B(x) \
+ ((x) & (~BITS_HIGH_RATE_BD_IDX_8822B))
+#define BIT_GET_HIGH_RATE_BD_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8822B) & \
+ BIT_MASK_HIGH_RATE_BD_IDX_8822B)
+#define BIT_SET_HIGH_RATE_BD_IDX_8822B(x, v) \
+ (BIT_CLEAR_HIGH_RATE_BD_IDX_8822B(x) | BIT_HIGH_RATE_BD_IDX_8822B(v))
#define BIT_SHIFT_LOW_RATE_BD_IDX_8822B 0
#define BIT_MASK_LOW_RATE_BD_IDX_8822B 0x7f
-#define BIT_LOW_RATE_BD_IDX_8822B(x) (((x) & BIT_MASK_LOW_RATE_BD_IDX_8822B) << BIT_SHIFT_LOW_RATE_BD_IDX_8822B)
-#define BIT_GET_LOW_RATE_BD_IDX_8822B(x) (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8822B) & BIT_MASK_LOW_RATE_BD_IDX_8822B)
-
+#define BIT_LOW_RATE_BD_IDX_8822B(x) \
+ (((x) & BIT_MASK_LOW_RATE_BD_IDX_8822B) \
+ << BIT_SHIFT_LOW_RATE_BD_IDX_8822B)
+#define BITS_LOW_RATE_BD_IDX_8822B \
+ (BIT_MASK_LOW_RATE_BD_IDX_8822B << BIT_SHIFT_LOW_RATE_BD_IDX_8822B)
+#define BIT_CLEAR_LOW_RATE_BD_IDX_8822B(x) ((x) & (~BITS_LOW_RATE_BD_IDX_8822B))
+#define BIT_GET_LOW_RATE_BD_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8822B) & \
+ BIT_MASK_LOW_RATE_BD_IDX_8822B)
+#define BIT_SET_LOW_RATE_BD_IDX_8822B(x, v) \
+ (BIT_CLEAR_LOW_RATE_BD_IDX_8822B(x) | BIT_LOW_RATE_BD_IDX_8822B(v))
/* 2 REG_LTR_CTRL2_TIMER_THRESHOLD_8822B */
#define BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822B 24
#define BIT_MASK_RX_EMPTY_TIMER_IDX_8822B 0x7
-#define BIT_RX_EMPTY_TIMER_IDX_8822B(x) (((x) & BIT_MASK_RX_EMPTY_TIMER_IDX_8822B) << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822B)
-#define BIT_GET_RX_EMPTY_TIMER_IDX_8822B(x) (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822B) & BIT_MASK_RX_EMPTY_TIMER_IDX_8822B)
-
+#define BIT_RX_EMPTY_TIMER_IDX_8822B(x) \
+ (((x) & BIT_MASK_RX_EMPTY_TIMER_IDX_8822B) \
+ << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822B)
+#define BITS_RX_EMPTY_TIMER_IDX_8822B \
+ (BIT_MASK_RX_EMPTY_TIMER_IDX_8822B \
+ << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822B)
+#define BIT_CLEAR_RX_EMPTY_TIMER_IDX_8822B(x) \
+ ((x) & (~BITS_RX_EMPTY_TIMER_IDX_8822B))
+#define BIT_GET_RX_EMPTY_TIMER_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822B) & \
+ BIT_MASK_RX_EMPTY_TIMER_IDX_8822B)
+#define BIT_SET_RX_EMPTY_TIMER_IDX_8822B(x, v) \
+ (BIT_CLEAR_RX_EMPTY_TIMER_IDX_8822B(x) | \
+ BIT_RX_EMPTY_TIMER_IDX_8822B(v))
#define BIT_SHIFT_RX_AFULL_TH_IDX_8822B 20
#define BIT_MASK_RX_AFULL_TH_IDX_8822B 0x7
-#define BIT_RX_AFULL_TH_IDX_8822B(x) (((x) & BIT_MASK_RX_AFULL_TH_IDX_8822B) << BIT_SHIFT_RX_AFULL_TH_IDX_8822B)
-#define BIT_GET_RX_AFULL_TH_IDX_8822B(x) (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8822B) & BIT_MASK_RX_AFULL_TH_IDX_8822B)
-
+#define BIT_RX_AFULL_TH_IDX_8822B(x) \
+ (((x) & BIT_MASK_RX_AFULL_TH_IDX_8822B) \
+ << BIT_SHIFT_RX_AFULL_TH_IDX_8822B)
+#define BITS_RX_AFULL_TH_IDX_8822B \
+ (BIT_MASK_RX_AFULL_TH_IDX_8822B << BIT_SHIFT_RX_AFULL_TH_IDX_8822B)
+#define BIT_CLEAR_RX_AFULL_TH_IDX_8822B(x) ((x) & (~BITS_RX_AFULL_TH_IDX_8822B))
+#define BIT_GET_RX_AFULL_TH_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8822B) & \
+ BIT_MASK_RX_AFULL_TH_IDX_8822B)
+#define BIT_SET_RX_AFULL_TH_IDX_8822B(x, v) \
+ (BIT_CLEAR_RX_AFULL_TH_IDX_8822B(x) | BIT_RX_AFULL_TH_IDX_8822B(v))
#define BIT_SHIFT_RX_HIGH_TH_IDX_8822B 16
#define BIT_MASK_RX_HIGH_TH_IDX_8822B 0x7
-#define BIT_RX_HIGH_TH_IDX_8822B(x) (((x) & BIT_MASK_RX_HIGH_TH_IDX_8822B) << BIT_SHIFT_RX_HIGH_TH_IDX_8822B)
-#define BIT_GET_RX_HIGH_TH_IDX_8822B(x) (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8822B) & BIT_MASK_RX_HIGH_TH_IDX_8822B)
-
+#define BIT_RX_HIGH_TH_IDX_8822B(x) \
+ (((x) & BIT_MASK_RX_HIGH_TH_IDX_8822B) \
+ << BIT_SHIFT_RX_HIGH_TH_IDX_8822B)
+#define BITS_RX_HIGH_TH_IDX_8822B \
+ (BIT_MASK_RX_HIGH_TH_IDX_8822B << BIT_SHIFT_RX_HIGH_TH_IDX_8822B)
+#define BIT_CLEAR_RX_HIGH_TH_IDX_8822B(x) ((x) & (~BITS_RX_HIGH_TH_IDX_8822B))
+#define BIT_GET_RX_HIGH_TH_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8822B) & \
+ BIT_MASK_RX_HIGH_TH_IDX_8822B)
+#define BIT_SET_RX_HIGH_TH_IDX_8822B(x, v) \
+ (BIT_CLEAR_RX_HIGH_TH_IDX_8822B(x) | BIT_RX_HIGH_TH_IDX_8822B(v))
#define BIT_SHIFT_RX_MED_TH_IDX_8822B 12
#define BIT_MASK_RX_MED_TH_IDX_8822B 0x7
-#define BIT_RX_MED_TH_IDX_8822B(x) (((x) & BIT_MASK_RX_MED_TH_IDX_8822B) << BIT_SHIFT_RX_MED_TH_IDX_8822B)
-#define BIT_GET_RX_MED_TH_IDX_8822B(x) (((x) >> BIT_SHIFT_RX_MED_TH_IDX_8822B) & BIT_MASK_RX_MED_TH_IDX_8822B)
-
+#define BIT_RX_MED_TH_IDX_8822B(x) \
+ (((x) & BIT_MASK_RX_MED_TH_IDX_8822B) << BIT_SHIFT_RX_MED_TH_IDX_8822B)
+#define BITS_RX_MED_TH_IDX_8822B \
+ (BIT_MASK_RX_MED_TH_IDX_8822B << BIT_SHIFT_RX_MED_TH_IDX_8822B)
+#define BIT_CLEAR_RX_MED_TH_IDX_8822B(x) ((x) & (~BITS_RX_MED_TH_IDX_8822B))
+#define BIT_GET_RX_MED_TH_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_RX_MED_TH_IDX_8822B) & BIT_MASK_RX_MED_TH_IDX_8822B)
+#define BIT_SET_RX_MED_TH_IDX_8822B(x, v) \
+ (BIT_CLEAR_RX_MED_TH_IDX_8822B(x) | BIT_RX_MED_TH_IDX_8822B(v))
#define BIT_SHIFT_RX_LOW_TH_IDX_8822B 8
#define BIT_MASK_RX_LOW_TH_IDX_8822B 0x7
-#define BIT_RX_LOW_TH_IDX_8822B(x) (((x) & BIT_MASK_RX_LOW_TH_IDX_8822B) << BIT_SHIFT_RX_LOW_TH_IDX_8822B)
-#define BIT_GET_RX_LOW_TH_IDX_8822B(x) (((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8822B) & BIT_MASK_RX_LOW_TH_IDX_8822B)
-
+#define BIT_RX_LOW_TH_IDX_8822B(x) \
+ (((x) & BIT_MASK_RX_LOW_TH_IDX_8822B) << BIT_SHIFT_RX_LOW_TH_IDX_8822B)
+#define BITS_RX_LOW_TH_IDX_8822B \
+ (BIT_MASK_RX_LOW_TH_IDX_8822B << BIT_SHIFT_RX_LOW_TH_IDX_8822B)
+#define BIT_CLEAR_RX_LOW_TH_IDX_8822B(x) ((x) & (~BITS_RX_LOW_TH_IDX_8822B))
+#define BIT_GET_RX_LOW_TH_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8822B) & BIT_MASK_RX_LOW_TH_IDX_8822B)
+#define BIT_SET_RX_LOW_TH_IDX_8822B(x, v) \
+ (BIT_CLEAR_RX_LOW_TH_IDX_8822B(x) | BIT_RX_LOW_TH_IDX_8822B(v))
#define BIT_SHIFT_LTR_SPACE_IDX_8822B 4
#define BIT_MASK_LTR_SPACE_IDX_8822B 0x3
-#define BIT_LTR_SPACE_IDX_8822B(x) (((x) & BIT_MASK_LTR_SPACE_IDX_8822B) << BIT_SHIFT_LTR_SPACE_IDX_8822B)
-#define BIT_GET_LTR_SPACE_IDX_8822B(x) (((x) >> BIT_SHIFT_LTR_SPACE_IDX_8822B) & BIT_MASK_LTR_SPACE_IDX_8822B)
-
+#define BIT_LTR_SPACE_IDX_8822B(x) \
+ (((x) & BIT_MASK_LTR_SPACE_IDX_8822B) << BIT_SHIFT_LTR_SPACE_IDX_8822B)
+#define BITS_LTR_SPACE_IDX_8822B \
+ (BIT_MASK_LTR_SPACE_IDX_8822B << BIT_SHIFT_LTR_SPACE_IDX_8822B)
+#define BIT_CLEAR_LTR_SPACE_IDX_8822B(x) ((x) & (~BITS_LTR_SPACE_IDX_8822B))
+#define BIT_GET_LTR_SPACE_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_LTR_SPACE_IDX_8822B) & BIT_MASK_LTR_SPACE_IDX_8822B)
+#define BIT_SET_LTR_SPACE_IDX_8822B(x, v) \
+ (BIT_CLEAR_LTR_SPACE_IDX_8822B(x) | BIT_LTR_SPACE_IDX_8822B(v))
#define BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822B 0
#define BIT_MASK_LTR_IDLE_TIMER_IDX_8822B 0x7
-#define BIT_LTR_IDLE_TIMER_IDX_8822B(x) (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8822B) << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822B)
-#define BIT_GET_LTR_IDLE_TIMER_IDX_8822B(x) (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822B) & BIT_MASK_LTR_IDLE_TIMER_IDX_8822B)
-
+#define BIT_LTR_IDLE_TIMER_IDX_8822B(x) \
+ (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8822B) \
+ << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822B)
+#define BITS_LTR_IDLE_TIMER_IDX_8822B \
+ (BIT_MASK_LTR_IDLE_TIMER_IDX_8822B \
+ << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822B)
+#define BIT_CLEAR_LTR_IDLE_TIMER_IDX_8822B(x) \
+ ((x) & (~BITS_LTR_IDLE_TIMER_IDX_8822B))
+#define BIT_GET_LTR_IDLE_TIMER_IDX_8822B(x) \
+ (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822B) & \
+ BIT_MASK_LTR_IDLE_TIMER_IDX_8822B)
+#define BIT_SET_LTR_IDLE_TIMER_IDX_8822B(x, v) \
+ (BIT_CLEAR_LTR_IDLE_TIMER_IDX_8822B(x) | \
+ BIT_LTR_IDLE_TIMER_IDX_8822B(v))
/* 2 REG_LTR_IDLE_LATENCY_V1_8822B */
#define BIT_SHIFT_LTR_IDLE_L_8822B 0
#define BIT_MASK_LTR_IDLE_L_8822B 0xffffffffL
-#define BIT_LTR_IDLE_L_8822B(x) (((x) & BIT_MASK_LTR_IDLE_L_8822B) << BIT_SHIFT_LTR_IDLE_L_8822B)
-#define BIT_GET_LTR_IDLE_L_8822B(x) (((x) >> BIT_SHIFT_LTR_IDLE_L_8822B) & BIT_MASK_LTR_IDLE_L_8822B)
-
+#define BIT_LTR_IDLE_L_8822B(x) \
+ (((x) & BIT_MASK_LTR_IDLE_L_8822B) << BIT_SHIFT_LTR_IDLE_L_8822B)
+#define BITS_LTR_IDLE_L_8822B \
+ (BIT_MASK_LTR_IDLE_L_8822B << BIT_SHIFT_LTR_IDLE_L_8822B)
+#define BIT_CLEAR_LTR_IDLE_L_8822B(x) ((x) & (~BITS_LTR_IDLE_L_8822B))
+#define BIT_GET_LTR_IDLE_L_8822B(x) \
+ (((x) >> BIT_SHIFT_LTR_IDLE_L_8822B) & BIT_MASK_LTR_IDLE_L_8822B)
+#define BIT_SET_LTR_IDLE_L_8822B(x, v) \
+ (BIT_CLEAR_LTR_IDLE_L_8822B(x) | BIT_LTR_IDLE_L_8822B(v))
/* 2 REG_LTR_ACTIVE_LATENCY_V1_8822B */
#define BIT_SHIFT_LTR_ACT_L_8822B 0
#define BIT_MASK_LTR_ACT_L_8822B 0xffffffffL
-#define BIT_LTR_ACT_L_8822B(x) (((x) & BIT_MASK_LTR_ACT_L_8822B) << BIT_SHIFT_LTR_ACT_L_8822B)
-#define BIT_GET_LTR_ACT_L_8822B(x) (((x) >> BIT_SHIFT_LTR_ACT_L_8822B) & BIT_MASK_LTR_ACT_L_8822B)
-
+#define BIT_LTR_ACT_L_8822B(x) \
+ (((x) & BIT_MASK_LTR_ACT_L_8822B) << BIT_SHIFT_LTR_ACT_L_8822B)
+#define BITS_LTR_ACT_L_8822B \
+ (BIT_MASK_LTR_ACT_L_8822B << BIT_SHIFT_LTR_ACT_L_8822B)
+#define BIT_CLEAR_LTR_ACT_L_8822B(x) ((x) & (~BITS_LTR_ACT_L_8822B))
+#define BIT_GET_LTR_ACT_L_8822B(x) \
+ (((x) >> BIT_SHIFT_LTR_ACT_L_8822B) & BIT_MASK_LTR_ACT_L_8822B)
+#define BIT_SET_LTR_ACT_L_8822B(x, v) \
+ (BIT_CLEAR_LTR_ACT_L_8822B(x) | BIT_LTR_ACT_L_8822B(v))
/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_8822B */
#define BIT_APPEND_MACID_IN_RESP_EN_8822B BIT(50)
@@ -9401,9 +16980,17 @@
#define BIT_SHIFT_TRAIN_STA_ADDR_8822B 0
#define BIT_MASK_TRAIN_STA_ADDR_8822B 0xffffffffffffL
-#define BIT_TRAIN_STA_ADDR_8822B(x) (((x) & BIT_MASK_TRAIN_STA_ADDR_8822B) << BIT_SHIFT_TRAIN_STA_ADDR_8822B)
-#define BIT_GET_TRAIN_STA_ADDR_8822B(x) (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_8822B) & BIT_MASK_TRAIN_STA_ADDR_8822B)
-
+#define BIT_TRAIN_STA_ADDR_8822B(x) \
+ (((x) & BIT_MASK_TRAIN_STA_ADDR_8822B) \
+ << BIT_SHIFT_TRAIN_STA_ADDR_8822B)
+#define BITS_TRAIN_STA_ADDR_8822B \
+ (BIT_MASK_TRAIN_STA_ADDR_8822B << BIT_SHIFT_TRAIN_STA_ADDR_8822B)
+#define BIT_CLEAR_TRAIN_STA_ADDR_8822B(x) ((x) & (~BITS_TRAIN_STA_ADDR_8822B))
+#define BIT_GET_TRAIN_STA_ADDR_8822B(x) \
+ (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_8822B) & \
+ BIT_MASK_TRAIN_STA_ADDR_8822B)
+#define BIT_SET_TRAIN_STA_ADDR_8822B(x, v) \
+ (BIT_CLEAR_TRAIN_STA_ADDR_8822B(x) | BIT_TRAIN_STA_ADDR_8822B(v))
/* 2 REG_RSVD_0X7B4_8822B */
@@ -9411,8 +16998,17 @@
#define BIT_SHIFT_PKTCNT_BSSIDMAP_8822B 4
#define BIT_MASK_PKTCNT_BSSIDMAP_8822B 0xf
-#define BIT_PKTCNT_BSSIDMAP_8822B(x) (((x) & BIT_MASK_PKTCNT_BSSIDMAP_8822B) << BIT_SHIFT_PKTCNT_BSSIDMAP_8822B)
-#define BIT_GET_PKTCNT_BSSIDMAP_8822B(x) (((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP_8822B) & BIT_MASK_PKTCNT_BSSIDMAP_8822B)
+#define BIT_PKTCNT_BSSIDMAP_8822B(x) \
+ (((x) & BIT_MASK_PKTCNT_BSSIDMAP_8822B) \
+ << BIT_SHIFT_PKTCNT_BSSIDMAP_8822B)
+#define BITS_PKTCNT_BSSIDMAP_8822B \
+ (BIT_MASK_PKTCNT_BSSIDMAP_8822B << BIT_SHIFT_PKTCNT_BSSIDMAP_8822B)
+#define BIT_CLEAR_PKTCNT_BSSIDMAP_8822B(x) ((x) & (~BITS_PKTCNT_BSSIDMAP_8822B))
+#define BIT_GET_PKTCNT_BSSIDMAP_8822B(x) \
+ (((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP_8822B) & \
+ BIT_MASK_PKTCNT_BSSIDMAP_8822B)
+#define BIT_SET_PKTCNT_BSSIDMAP_8822B(x, v) \
+ (BIT_CLEAR_PKTCNT_BSSIDMAP_8822B(x) | BIT_PKTCNT_BSSIDMAP_8822B(v))
#define BIT_PKTCNT_CNTRST_8822B BIT(1)
#define BIT_PKTCNT_CNTEN_8822B BIT(0)
@@ -9423,47 +17019,111 @@
#define BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822B 0
#define BIT_MASK_WMAC_PKTCNT_CFGAD_8822B 0xff
-#define BIT_WMAC_PKTCNT_CFGAD_8822B(x) (((x) & BIT_MASK_WMAC_PKTCNT_CFGAD_8822B) << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822B)
-#define BIT_GET_WMAC_PKTCNT_CFGAD_8822B(x) (((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822B) & BIT_MASK_WMAC_PKTCNT_CFGAD_8822B)
-
+#define BIT_WMAC_PKTCNT_CFGAD_8822B(x) \
+ (((x) & BIT_MASK_WMAC_PKTCNT_CFGAD_8822B) \
+ << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822B)
+#define BITS_WMAC_PKTCNT_CFGAD_8822B \
+ (BIT_MASK_WMAC_PKTCNT_CFGAD_8822B << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822B)
+#define BIT_CLEAR_WMAC_PKTCNT_CFGAD_8822B(x) \
+ ((x) & (~BITS_WMAC_PKTCNT_CFGAD_8822B))
+#define BIT_GET_WMAC_PKTCNT_CFGAD_8822B(x) \
+ (((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822B) & \
+ BIT_MASK_WMAC_PKTCNT_CFGAD_8822B)
+#define BIT_SET_WMAC_PKTCNT_CFGAD_8822B(x, v) \
+ (BIT_CLEAR_WMAC_PKTCNT_CFGAD_8822B(x) | BIT_WMAC_PKTCNT_CFGAD_8822B(v))
/* 2 REG_IQ_DUMP_8822B */
#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8822B (64 & CPU_OPT_WIDTH)
#define BIT_MASK_R_WMAC_MATCH_REF_MAC_8822B 0xffffffffL
-#define BIT_R_WMAC_MATCH_REF_MAC_8822B(x) (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_8822B) << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8822B)
-#define BIT_GET_R_WMAC_MATCH_REF_MAC_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8822B) & BIT_MASK_R_WMAC_MATCH_REF_MAC_8822B)
-
+#define BIT_R_WMAC_MATCH_REF_MAC_8822B(x) \
+ (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_8822B) \
+ << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8822B)
+#define BITS_R_WMAC_MATCH_REF_MAC_8822B \
+ (BIT_MASK_R_WMAC_MATCH_REF_MAC_8822B \
+ << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8822B)
+#define BIT_CLEAR_R_WMAC_MATCH_REF_MAC_8822B(x) \
+ ((x) & (~BITS_R_WMAC_MATCH_REF_MAC_8822B))
+#define BIT_GET_R_WMAC_MATCH_REF_MAC_8822B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_8822B) & \
+ BIT_MASK_R_WMAC_MATCH_REF_MAC_8822B)
+#define BIT_SET_R_WMAC_MATCH_REF_MAC_8822B(x, v) \
+ (BIT_CLEAR_R_WMAC_MATCH_REF_MAC_8822B(x) | \
+ BIT_R_WMAC_MATCH_REF_MAC_8822B(v))
#define BIT_SHIFT_R_WMAC_MASK_LA_MAC_8822B (32 & CPU_OPT_WIDTH)
#define BIT_MASK_R_WMAC_MASK_LA_MAC_8822B 0xffffffffL
-#define BIT_R_WMAC_MASK_LA_MAC_8822B(x) (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_8822B) << BIT_SHIFT_R_WMAC_MASK_LA_MAC_8822B)
-#define BIT_GET_R_WMAC_MASK_LA_MAC_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_8822B) & BIT_MASK_R_WMAC_MASK_LA_MAC_8822B)
-
-
-#define BIT_SHIFT_DUMP_OK_ADDR_8822B 15
-#define BIT_MASK_DUMP_OK_ADDR_8822B 0x1ffff
-#define BIT_DUMP_OK_ADDR_8822B(x) (((x) & BIT_MASK_DUMP_OK_ADDR_8822B) << BIT_SHIFT_DUMP_OK_ADDR_8822B)
-#define BIT_GET_DUMP_OK_ADDR_8822B(x) (((x) >> BIT_SHIFT_DUMP_OK_ADDR_8822B) & BIT_MASK_DUMP_OK_ADDR_8822B)
-
+#define BIT_R_WMAC_MASK_LA_MAC_8822B(x) \
+ (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_8822B) \
+ << BIT_SHIFT_R_WMAC_MASK_LA_MAC_8822B)
+#define BITS_R_WMAC_MASK_LA_MAC_8822B \
+ (BIT_MASK_R_WMAC_MASK_LA_MAC_8822B \
+ << BIT_SHIFT_R_WMAC_MASK_LA_MAC_8822B)
+#define BIT_CLEAR_R_WMAC_MASK_LA_MAC_8822B(x) \
+ ((x) & (~BITS_R_WMAC_MASK_LA_MAC_8822B))
+#define BIT_GET_R_WMAC_MASK_LA_MAC_8822B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_8822B) & \
+ BIT_MASK_R_WMAC_MASK_LA_MAC_8822B)
+#define BIT_SET_R_WMAC_MASK_LA_MAC_8822B(x, v) \
+ (BIT_CLEAR_R_WMAC_MASK_LA_MAC_8822B(x) | \
+ BIT_R_WMAC_MASK_LA_MAC_8822B(v))
+
+#define BIT_SHIFT_DUMP_OK_ADDR_8822B 16
+#define BIT_MASK_DUMP_OK_ADDR_8822B 0xffff
+#define BIT_DUMP_OK_ADDR_8822B(x) \
+ (((x) & BIT_MASK_DUMP_OK_ADDR_8822B) << BIT_SHIFT_DUMP_OK_ADDR_8822B)
+#define BITS_DUMP_OK_ADDR_8822B \
+ (BIT_MASK_DUMP_OK_ADDR_8822B << BIT_SHIFT_DUMP_OK_ADDR_8822B)
+#define BIT_CLEAR_DUMP_OK_ADDR_8822B(x) ((x) & (~BITS_DUMP_OK_ADDR_8822B))
+#define BIT_GET_DUMP_OK_ADDR_8822B(x) \
+ (((x) >> BIT_SHIFT_DUMP_OK_ADDR_8822B) & BIT_MASK_DUMP_OK_ADDR_8822B)
+#define BIT_SET_DUMP_OK_ADDR_8822B(x, v) \
+ (BIT_CLEAR_DUMP_OK_ADDR_8822B(x) | BIT_DUMP_OK_ADDR_8822B(v))
#define BIT_SHIFT_R_TRIG_TIME_SEL_8822B 8
#define BIT_MASK_R_TRIG_TIME_SEL_8822B 0x7f
-#define BIT_R_TRIG_TIME_SEL_8822B(x) (((x) & BIT_MASK_R_TRIG_TIME_SEL_8822B) << BIT_SHIFT_R_TRIG_TIME_SEL_8822B)
-#define BIT_GET_R_TRIG_TIME_SEL_8822B(x) (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8822B) & BIT_MASK_R_TRIG_TIME_SEL_8822B)
-
+#define BIT_R_TRIG_TIME_SEL_8822B(x) \
+ (((x) & BIT_MASK_R_TRIG_TIME_SEL_8822B) \
+ << BIT_SHIFT_R_TRIG_TIME_SEL_8822B)
+#define BITS_R_TRIG_TIME_SEL_8822B \
+ (BIT_MASK_R_TRIG_TIME_SEL_8822B << BIT_SHIFT_R_TRIG_TIME_SEL_8822B)
+#define BIT_CLEAR_R_TRIG_TIME_SEL_8822B(x) ((x) & (~BITS_R_TRIG_TIME_SEL_8822B))
+#define BIT_GET_R_TRIG_TIME_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8822B) & \
+ BIT_MASK_R_TRIG_TIME_SEL_8822B)
+#define BIT_SET_R_TRIG_TIME_SEL_8822B(x, v) \
+ (BIT_CLEAR_R_TRIG_TIME_SEL_8822B(x) | BIT_R_TRIG_TIME_SEL_8822B(v))
#define BIT_SHIFT_R_MAC_TRIG_SEL_8822B 6
#define BIT_MASK_R_MAC_TRIG_SEL_8822B 0x3
-#define BIT_R_MAC_TRIG_SEL_8822B(x) (((x) & BIT_MASK_R_MAC_TRIG_SEL_8822B) << BIT_SHIFT_R_MAC_TRIG_SEL_8822B)
-#define BIT_GET_R_MAC_TRIG_SEL_8822B(x) (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8822B) & BIT_MASK_R_MAC_TRIG_SEL_8822B)
+#define BIT_R_MAC_TRIG_SEL_8822B(x) \
+ (((x) & BIT_MASK_R_MAC_TRIG_SEL_8822B) \
+ << BIT_SHIFT_R_MAC_TRIG_SEL_8822B)
+#define BITS_R_MAC_TRIG_SEL_8822B \
+ (BIT_MASK_R_MAC_TRIG_SEL_8822B << BIT_SHIFT_R_MAC_TRIG_SEL_8822B)
+#define BIT_CLEAR_R_MAC_TRIG_SEL_8822B(x) ((x) & (~BITS_R_MAC_TRIG_SEL_8822B))
+#define BIT_GET_R_MAC_TRIG_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8822B) & \
+ BIT_MASK_R_MAC_TRIG_SEL_8822B)
+#define BIT_SET_R_MAC_TRIG_SEL_8822B(x, v) \
+ (BIT_CLEAR_R_MAC_TRIG_SEL_8822B(x) | BIT_R_MAC_TRIG_SEL_8822B(v))
#define BIT_MAC_TRIG_REG_8822B BIT(5)
#define BIT_SHIFT_R_LEVEL_PULSE_SEL_8822B 3
#define BIT_MASK_R_LEVEL_PULSE_SEL_8822B 0x3
-#define BIT_R_LEVEL_PULSE_SEL_8822B(x) (((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8822B) << BIT_SHIFT_R_LEVEL_PULSE_SEL_8822B)
-#define BIT_GET_R_LEVEL_PULSE_SEL_8822B(x) (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8822B) & BIT_MASK_R_LEVEL_PULSE_SEL_8822B)
+#define BIT_R_LEVEL_PULSE_SEL_8822B(x) \
+ (((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8822B) \
+ << BIT_SHIFT_R_LEVEL_PULSE_SEL_8822B)
+#define BITS_R_LEVEL_PULSE_SEL_8822B \
+ (BIT_MASK_R_LEVEL_PULSE_SEL_8822B << BIT_SHIFT_R_LEVEL_PULSE_SEL_8822B)
+#define BIT_CLEAR_R_LEVEL_PULSE_SEL_8822B(x) \
+ ((x) & (~BITS_R_LEVEL_PULSE_SEL_8822B))
+#define BIT_GET_R_LEVEL_PULSE_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8822B) & \
+ BIT_MASK_R_LEVEL_PULSE_SEL_8822B)
+#define BIT_SET_R_LEVEL_PULSE_SEL_8822B(x, v) \
+ (BIT_CLEAR_R_LEVEL_PULSE_SEL_8822B(x) | BIT_R_LEVEL_PULSE_SEL_8822B(v))
#define BIT_EN_LA_MAC_8822B BIT(2)
#define BIT_R_EN_IQDUMP_8822B BIT(1)
@@ -9483,14 +17143,35 @@
#define BIT_SHIFT_R_WMAC_RX_FIL_LEN_8822B (64 & CPU_OPT_WIDTH)
#define BIT_MASK_R_WMAC_RX_FIL_LEN_8822B 0xffff
-#define BIT_R_WMAC_RX_FIL_LEN_8822B(x) (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_8822B) << BIT_SHIFT_R_WMAC_RX_FIL_LEN_8822B)
-#define BIT_GET_R_WMAC_RX_FIL_LEN_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_8822B) & BIT_MASK_R_WMAC_RX_FIL_LEN_8822B)
-
+#define BIT_R_WMAC_RX_FIL_LEN_8822B(x) \
+ (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_8822B) \
+ << BIT_SHIFT_R_WMAC_RX_FIL_LEN_8822B)
+#define BITS_R_WMAC_RX_FIL_LEN_8822B \
+ (BIT_MASK_R_WMAC_RX_FIL_LEN_8822B << BIT_SHIFT_R_WMAC_RX_FIL_LEN_8822B)
+#define BIT_CLEAR_R_WMAC_RX_FIL_LEN_8822B(x) \
+ ((x) & (~BITS_R_WMAC_RX_FIL_LEN_8822B))
+#define BIT_GET_R_WMAC_RX_FIL_LEN_8822B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_8822B) & \
+ BIT_MASK_R_WMAC_RX_FIL_LEN_8822B)
+#define BIT_SET_R_WMAC_RX_FIL_LEN_8822B(x, v) \
+ (BIT_CLEAR_R_WMAC_RX_FIL_LEN_8822B(x) | BIT_R_WMAC_RX_FIL_LEN_8822B(v))
#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8822B (56 & CPU_OPT_WIDTH)
#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8822B 0xff
-#define BIT_R_WMAC_RXFIFO_FULL_TH_8822B(x) (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8822B) << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8822B)
-#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8822B) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8822B)
+#define BIT_R_WMAC_RXFIFO_FULL_TH_8822B(x) \
+ (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8822B) \
+ << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8822B)
+#define BITS_R_WMAC_RXFIFO_FULL_TH_8822B \
+ (BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8822B \
+ << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8822B)
+#define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_8822B(x) \
+ ((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH_8822B))
+#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_8822B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_8822B) & \
+ BIT_MASK_R_WMAC_RXFIFO_FULL_TH_8822B)
+#define BIT_SET_R_WMAC_RXFIFO_FULL_TH_8822B(x, v) \
+ (BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_8822B(x) | \
+ BIT_R_WMAC_RXFIFO_FULL_TH_8822B(v))
#define BIT_R_WMAC_RX_SYNCFIFO_SYNC_8822B BIT(55)
#define BIT_R_WMAC_RXRST_DLY_8822B BIT(54)
@@ -9519,15 +17200,27 @@
#define BIT_SHIFT_R_OFDM_LEN_8822B 26
#define BIT_MASK_R_OFDM_LEN_8822B 0x3f
-#define BIT_R_OFDM_LEN_8822B(x) (((x) & BIT_MASK_R_OFDM_LEN_8822B) << BIT_SHIFT_R_OFDM_LEN_8822B)
-#define BIT_GET_R_OFDM_LEN_8822B(x) (((x) >> BIT_SHIFT_R_OFDM_LEN_8822B) & BIT_MASK_R_OFDM_LEN_8822B)
-
+#define BIT_R_OFDM_LEN_8822B(x) \
+ (((x) & BIT_MASK_R_OFDM_LEN_8822B) << BIT_SHIFT_R_OFDM_LEN_8822B)
+#define BITS_R_OFDM_LEN_8822B \
+ (BIT_MASK_R_OFDM_LEN_8822B << BIT_SHIFT_R_OFDM_LEN_8822B)
+#define BIT_CLEAR_R_OFDM_LEN_8822B(x) ((x) & (~BITS_R_OFDM_LEN_8822B))
+#define BIT_GET_R_OFDM_LEN_8822B(x) \
+ (((x) >> BIT_SHIFT_R_OFDM_LEN_8822B) & BIT_MASK_R_OFDM_LEN_8822B)
+#define BIT_SET_R_OFDM_LEN_8822B(x, v) \
+ (BIT_CLEAR_R_OFDM_LEN_8822B(x) | BIT_R_OFDM_LEN_8822B(v))
#define BIT_SHIFT_R_CCK_LEN_8822B 0
#define BIT_MASK_R_CCK_LEN_8822B 0xffff
-#define BIT_R_CCK_LEN_8822B(x) (((x) & BIT_MASK_R_CCK_LEN_8822B) << BIT_SHIFT_R_CCK_LEN_8822B)
-#define BIT_GET_R_CCK_LEN_8822B(x) (((x) >> BIT_SHIFT_R_CCK_LEN_8822B) & BIT_MASK_R_CCK_LEN_8822B)
-
+#define BIT_R_CCK_LEN_8822B(x) \
+ (((x) & BIT_MASK_R_CCK_LEN_8822B) << BIT_SHIFT_R_CCK_LEN_8822B)
+#define BITS_R_CCK_LEN_8822B \
+ (BIT_MASK_R_CCK_LEN_8822B << BIT_SHIFT_R_CCK_LEN_8822B)
+#define BIT_CLEAR_R_CCK_LEN_8822B(x) ((x) & (~BITS_R_CCK_LEN_8822B))
+#define BIT_GET_R_CCK_LEN_8822B(x) \
+ (((x) >> BIT_SHIFT_R_CCK_LEN_8822B) & BIT_MASK_R_CCK_LEN_8822B)
+#define BIT_SET_R_CCK_LEN_8822B(x, v) \
+ (BIT_CLEAR_R_CCK_LEN_8822B(x) | BIT_R_CCK_LEN_8822B(v))
/* 2 REG_RX_FILTER_FUNCTION_8822B */
#define BIT_R_WMAC_MHRDDY_LATCH_8822B BIT(14)
@@ -9550,35 +17243,64 @@
#define BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822B 0
#define BIT_MASK_R_WMAC_TXNDP_SIGB_8822B 0x1fffff
-#define BIT_R_WMAC_TXNDP_SIGB_8822B(x) (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB_8822B) << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822B)
-#define BIT_GET_R_WMAC_TXNDP_SIGB_8822B(x) (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822B) & BIT_MASK_R_WMAC_TXNDP_SIGB_8822B)
-
+#define BIT_R_WMAC_TXNDP_SIGB_8822B(x) \
+ (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB_8822B) \
+ << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822B)
+#define BITS_R_WMAC_TXNDP_SIGB_8822B \
+ (BIT_MASK_R_WMAC_TXNDP_SIGB_8822B << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822B)
+#define BIT_CLEAR_R_WMAC_TXNDP_SIGB_8822B(x) \
+ ((x) & (~BITS_R_WMAC_TXNDP_SIGB_8822B))
+#define BIT_GET_R_WMAC_TXNDP_SIGB_8822B(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822B) & \
+ BIT_MASK_R_WMAC_TXNDP_SIGB_8822B)
+#define BIT_SET_R_WMAC_TXNDP_SIGB_8822B(x, v) \
+ (BIT_CLEAR_R_WMAC_TXNDP_SIGB_8822B(x) | BIT_R_WMAC_TXNDP_SIGB_8822B(v))
/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_8822B */
#define BIT_SHIFT_R_MAC_DEBUG_8822B (32 & CPU_OPT_WIDTH)
#define BIT_MASK_R_MAC_DEBUG_8822B 0xffffffffL
-#define BIT_R_MAC_DEBUG_8822B(x) (((x) & BIT_MASK_R_MAC_DEBUG_8822B) << BIT_SHIFT_R_MAC_DEBUG_8822B)
-#define BIT_GET_R_MAC_DEBUG_8822B(x) (((x) >> BIT_SHIFT_R_MAC_DEBUG_8822B) & BIT_MASK_R_MAC_DEBUG_8822B)
-
+#define BIT_R_MAC_DEBUG_8822B(x) \
+ (((x) & BIT_MASK_R_MAC_DEBUG_8822B) << BIT_SHIFT_R_MAC_DEBUG_8822B)
+#define BITS_R_MAC_DEBUG_8822B \
+ (BIT_MASK_R_MAC_DEBUG_8822B << BIT_SHIFT_R_MAC_DEBUG_8822B)
+#define BIT_CLEAR_R_MAC_DEBUG_8822B(x) ((x) & (~BITS_R_MAC_DEBUG_8822B))
+#define BIT_GET_R_MAC_DEBUG_8822B(x) \
+ (((x) >> BIT_SHIFT_R_MAC_DEBUG_8822B) & BIT_MASK_R_MAC_DEBUG_8822B)
+#define BIT_SET_R_MAC_DEBUG_8822B(x, v) \
+ (BIT_CLEAR_R_MAC_DEBUG_8822B(x) | BIT_R_MAC_DEBUG_8822B(v))
#define BIT_SHIFT_R_MAC_DBG_SHIFT_8822B 8
#define BIT_MASK_R_MAC_DBG_SHIFT_8822B 0x7
-#define BIT_R_MAC_DBG_SHIFT_8822B(x) (((x) & BIT_MASK_R_MAC_DBG_SHIFT_8822B) << BIT_SHIFT_R_MAC_DBG_SHIFT_8822B)
-#define BIT_GET_R_MAC_DBG_SHIFT_8822B(x) (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8822B) & BIT_MASK_R_MAC_DBG_SHIFT_8822B)
-
+#define BIT_R_MAC_DBG_SHIFT_8822B(x) \
+ (((x) & BIT_MASK_R_MAC_DBG_SHIFT_8822B) \
+ << BIT_SHIFT_R_MAC_DBG_SHIFT_8822B)
+#define BITS_R_MAC_DBG_SHIFT_8822B \
+ (BIT_MASK_R_MAC_DBG_SHIFT_8822B << BIT_SHIFT_R_MAC_DBG_SHIFT_8822B)
+#define BIT_CLEAR_R_MAC_DBG_SHIFT_8822B(x) ((x) & (~BITS_R_MAC_DBG_SHIFT_8822B))
+#define BIT_GET_R_MAC_DBG_SHIFT_8822B(x) \
+ (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8822B) & \
+ BIT_MASK_R_MAC_DBG_SHIFT_8822B)
+#define BIT_SET_R_MAC_DBG_SHIFT_8822B(x, v) \
+ (BIT_CLEAR_R_MAC_DBG_SHIFT_8822B(x) | BIT_R_MAC_DBG_SHIFT_8822B(v))
#define BIT_SHIFT_R_MAC_DBG_SEL_8822B 0
#define BIT_MASK_R_MAC_DBG_SEL_8822B 0x3
-#define BIT_R_MAC_DBG_SEL_8822B(x) (((x) & BIT_MASK_R_MAC_DBG_SEL_8822B) << BIT_SHIFT_R_MAC_DBG_SEL_8822B)
-#define BIT_GET_R_MAC_DBG_SEL_8822B(x) (((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8822B) & BIT_MASK_R_MAC_DBG_SEL_8822B)
-
+#define BIT_R_MAC_DBG_SEL_8822B(x) \
+ (((x) & BIT_MASK_R_MAC_DBG_SEL_8822B) << BIT_SHIFT_R_MAC_DBG_SEL_8822B)
+#define BITS_R_MAC_DBG_SEL_8822B \
+ (BIT_MASK_R_MAC_DBG_SEL_8822B << BIT_SHIFT_R_MAC_DBG_SEL_8822B)
+#define BIT_CLEAR_R_MAC_DBG_SEL_8822B(x) ((x) & (~BITS_R_MAC_DBG_SEL_8822B))
+#define BIT_GET_R_MAC_DBG_SEL_8822B(x) \
+ (((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8822B) & BIT_MASK_R_MAC_DBG_SEL_8822B)
+#define BIT_SET_R_MAC_DBG_SEL_8822B(x, v) \
+ (BIT_CLEAR_R_MAC_DBG_SEL_8822B(x) | BIT_R_MAC_DBG_SEL_8822B(v))
/* 2 REG_RTS_ADDRESS_0_8822B */
/* 2 REG_RTS_ADDRESS_1_8822B */
-/* 2 REG__RPFM_MAP1_8822B (RX PAYLOAD FILTER MAP FRAME TYPE CONTROL REGISTER GROUP 1 */
+/* 2 REG_RPFM_MAP1_8822B */
#define BIT_DATA_RPFM15EN_8822B BIT(15)
#define BIT_DATA_RPFM14EN_8822B BIT(14)
#define BIT_DATA_RPFM13EN_8822B BIT(13)
@@ -9603,31 +17325,69 @@
#define BIT_SHIFT_WRITE_BYTE_EN_V1_8822B 16
#define BIT_MASK_WRITE_BYTE_EN_V1_8822B 0xf
-#define BIT_WRITE_BYTE_EN_V1_8822B(x) (((x) & BIT_MASK_WRITE_BYTE_EN_V1_8822B) << BIT_SHIFT_WRITE_BYTE_EN_V1_8822B)
-#define BIT_GET_WRITE_BYTE_EN_V1_8822B(x) (((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1_8822B) & BIT_MASK_WRITE_BYTE_EN_V1_8822B)
-
+#define BIT_WRITE_BYTE_EN_V1_8822B(x) \
+ (((x) & BIT_MASK_WRITE_BYTE_EN_V1_8822B) \
+ << BIT_SHIFT_WRITE_BYTE_EN_V1_8822B)
+#define BITS_WRITE_BYTE_EN_V1_8822B \
+ (BIT_MASK_WRITE_BYTE_EN_V1_8822B << BIT_SHIFT_WRITE_BYTE_EN_V1_8822B)
+#define BIT_CLEAR_WRITE_BYTE_EN_V1_8822B(x) \
+ ((x) & (~BITS_WRITE_BYTE_EN_V1_8822B))
+#define BIT_GET_WRITE_BYTE_EN_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1_8822B) & \
+ BIT_MASK_WRITE_BYTE_EN_V1_8822B)
+#define BIT_SET_WRITE_BYTE_EN_V1_8822B(x, v) \
+ (BIT_CLEAR_WRITE_BYTE_EN_V1_8822B(x) | BIT_WRITE_BYTE_EN_V1_8822B(v))
#define BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822B 0
#define BIT_MASK_LTECOEX_REG_ADDR_V1_8822B 0xffff
-#define BIT_LTECOEX_REG_ADDR_V1_8822B(x) (((x) & BIT_MASK_LTECOEX_REG_ADDR_V1_8822B) << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822B)
-#define BIT_GET_LTECOEX_REG_ADDR_V1_8822B(x) (((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822B) & BIT_MASK_LTECOEX_REG_ADDR_V1_8822B)
-
+#define BIT_LTECOEX_REG_ADDR_V1_8822B(x) \
+ (((x) & BIT_MASK_LTECOEX_REG_ADDR_V1_8822B) \
+ << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822B)
+#define BITS_LTECOEX_REG_ADDR_V1_8822B \
+ (BIT_MASK_LTECOEX_REG_ADDR_V1_8822B \
+ << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822B)
+#define BIT_CLEAR_LTECOEX_REG_ADDR_V1_8822B(x) \
+ ((x) & (~BITS_LTECOEX_REG_ADDR_V1_8822B))
+#define BIT_GET_LTECOEX_REG_ADDR_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822B) & \
+ BIT_MASK_LTECOEX_REG_ADDR_V1_8822B)
+#define BIT_SET_LTECOEX_REG_ADDR_V1_8822B(x, v) \
+ (BIT_CLEAR_LTECOEX_REG_ADDR_V1_8822B(x) | \
+ BIT_LTECOEX_REG_ADDR_V1_8822B(v))
/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8822B */
#define BIT_SHIFT_LTECOEX_W_DATA_V1_8822B 0
#define BIT_MASK_LTECOEX_W_DATA_V1_8822B 0xffffffffL
-#define BIT_LTECOEX_W_DATA_V1_8822B(x) (((x) & BIT_MASK_LTECOEX_W_DATA_V1_8822B) << BIT_SHIFT_LTECOEX_W_DATA_V1_8822B)
-#define BIT_GET_LTECOEX_W_DATA_V1_8822B(x) (((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1_8822B) & BIT_MASK_LTECOEX_W_DATA_V1_8822B)
-
+#define BIT_LTECOEX_W_DATA_V1_8822B(x) \
+ (((x) & BIT_MASK_LTECOEX_W_DATA_V1_8822B) \
+ << BIT_SHIFT_LTECOEX_W_DATA_V1_8822B)
+#define BITS_LTECOEX_W_DATA_V1_8822B \
+ (BIT_MASK_LTECOEX_W_DATA_V1_8822B << BIT_SHIFT_LTECOEX_W_DATA_V1_8822B)
+#define BIT_CLEAR_LTECOEX_W_DATA_V1_8822B(x) \
+ ((x) & (~BITS_LTECOEX_W_DATA_V1_8822B))
+#define BIT_GET_LTECOEX_W_DATA_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1_8822B) & \
+ BIT_MASK_LTECOEX_W_DATA_V1_8822B)
+#define BIT_SET_LTECOEX_W_DATA_V1_8822B(x, v) \
+ (BIT_CLEAR_LTECOEX_W_DATA_V1_8822B(x) | BIT_LTECOEX_W_DATA_V1_8822B(v))
/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8822B */
#define BIT_SHIFT_LTECOEX_R_DATA_V1_8822B 0
#define BIT_MASK_LTECOEX_R_DATA_V1_8822B 0xffffffffL
-#define BIT_LTECOEX_R_DATA_V1_8822B(x) (((x) & BIT_MASK_LTECOEX_R_DATA_V1_8822B) << BIT_SHIFT_LTECOEX_R_DATA_V1_8822B)
-#define BIT_GET_LTECOEX_R_DATA_V1_8822B(x) (((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1_8822B) & BIT_MASK_LTECOEX_R_DATA_V1_8822B)
-
+#define BIT_LTECOEX_R_DATA_V1_8822B(x) \
+ (((x) & BIT_MASK_LTECOEX_R_DATA_V1_8822B) \
+ << BIT_SHIFT_LTECOEX_R_DATA_V1_8822B)
+#define BITS_LTECOEX_R_DATA_V1_8822B \
+ (BIT_MASK_LTECOEX_R_DATA_V1_8822B << BIT_SHIFT_LTECOEX_R_DATA_V1_8822B)
+#define BIT_CLEAR_LTECOEX_R_DATA_V1_8822B(x) \
+ ((x) & (~BITS_LTECOEX_R_DATA_V1_8822B))
+#define BIT_GET_LTECOEX_R_DATA_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1_8822B) & \
+ BIT_MASK_LTECOEX_R_DATA_V1_8822B)
+#define BIT_SET_LTECOEX_R_DATA_V1_8822B(x, v) \
+ (BIT_CLEAR_LTECOEX_R_DATA_V1_8822B(x) | BIT_LTECOEX_R_DATA_V1_8822B(v))
/* 2 REG_NOT_VALID_8822B */
@@ -9635,15 +17395,26 @@
#define BIT_SHIFT_SDIO_INT_TIMEOUT_8822B 16
#define BIT_MASK_SDIO_INT_TIMEOUT_8822B 0xffff
-#define BIT_SDIO_INT_TIMEOUT_8822B(x) (((x) & BIT_MASK_SDIO_INT_TIMEOUT_8822B) << BIT_SHIFT_SDIO_INT_TIMEOUT_8822B)
-#define BIT_GET_SDIO_INT_TIMEOUT_8822B(x) (((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT_8822B) & BIT_MASK_SDIO_INT_TIMEOUT_8822B)
+#define BIT_SDIO_INT_TIMEOUT_8822B(x) \
+ (((x) & BIT_MASK_SDIO_INT_TIMEOUT_8822B) \
+ << BIT_SHIFT_SDIO_INT_TIMEOUT_8822B)
+#define BITS_SDIO_INT_TIMEOUT_8822B \
+ (BIT_MASK_SDIO_INT_TIMEOUT_8822B << BIT_SHIFT_SDIO_INT_TIMEOUT_8822B)
+#define BIT_CLEAR_SDIO_INT_TIMEOUT_8822B(x) \
+ ((x) & (~BITS_SDIO_INT_TIMEOUT_8822B))
+#define BIT_GET_SDIO_INT_TIMEOUT_8822B(x) \
+ (((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT_8822B) & \
+ BIT_MASK_SDIO_INT_TIMEOUT_8822B)
+#define BIT_SET_SDIO_INT_TIMEOUT_8822B(x, v) \
+ (BIT_CLEAR_SDIO_INT_TIMEOUT_8822B(x) | BIT_SDIO_INT_TIMEOUT_8822B(v))
#define BIT_IO_ERR_STATUS_8822B BIT(15)
#define BIT_REPLY_ERRCRC_IN_DATA_8822B BIT(9)
#define BIT_EN_CMD53_OVERLAP_8822B BIT(8)
#define BIT_REPLY_ERR_IN_R5_8822B BIT(7)
#define BIT_R18A_EN_8822B BIT(6)
-#define BIT_INIT_CMD_EN_8822B BIT(5)
+#define BIT_SDIO_CMD_FORCE_VLD_8822B BIT(5)
+#define BIT_INIT_CMD_EN_8822B BIT(4)
#define BIT_EN_RXDMA_MASK_INT_8822B BIT(2)
#define BIT_EN_MASK_TIMER_8822B BIT(1)
#define BIT_CMD_ERR_STOP_INT_EN_8822B BIT(0)
@@ -9704,86 +17475,155 @@
#define BIT_SHIFT_RX_REQ_LEN_V1_8822B 0
#define BIT_MASK_RX_REQ_LEN_V1_8822B 0x3ffff
-#define BIT_RX_REQ_LEN_V1_8822B(x) (((x) & BIT_MASK_RX_REQ_LEN_V1_8822B) << BIT_SHIFT_RX_REQ_LEN_V1_8822B)
-#define BIT_GET_RX_REQ_LEN_V1_8822B(x) (((x) >> BIT_SHIFT_RX_REQ_LEN_V1_8822B) & BIT_MASK_RX_REQ_LEN_V1_8822B)
-
+#define BIT_RX_REQ_LEN_V1_8822B(x) \
+ (((x) & BIT_MASK_RX_REQ_LEN_V1_8822B) << BIT_SHIFT_RX_REQ_LEN_V1_8822B)
+#define BITS_RX_REQ_LEN_V1_8822B \
+ (BIT_MASK_RX_REQ_LEN_V1_8822B << BIT_SHIFT_RX_REQ_LEN_V1_8822B)
+#define BIT_CLEAR_RX_REQ_LEN_V1_8822B(x) ((x) & (~BITS_RX_REQ_LEN_V1_8822B))
+#define BIT_GET_RX_REQ_LEN_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_RX_REQ_LEN_V1_8822B) & BIT_MASK_RX_REQ_LEN_V1_8822B)
+#define BIT_SET_RX_REQ_LEN_V1_8822B(x, v) \
+ (BIT_CLEAR_RX_REQ_LEN_V1_8822B(x) | BIT_RX_REQ_LEN_V1_8822B(v))
/* 2 REG_SDIO_FREE_TXPG_SEQ_V1_8822B */
#define BIT_SHIFT_FREE_TXPG_SEQ_8822B 0
#define BIT_MASK_FREE_TXPG_SEQ_8822B 0xff
-#define BIT_FREE_TXPG_SEQ_8822B(x) (((x) & BIT_MASK_FREE_TXPG_SEQ_8822B) << BIT_SHIFT_FREE_TXPG_SEQ_8822B)
-#define BIT_GET_FREE_TXPG_SEQ_8822B(x) (((x) >> BIT_SHIFT_FREE_TXPG_SEQ_8822B) & BIT_MASK_FREE_TXPG_SEQ_8822B)
-
+#define BIT_FREE_TXPG_SEQ_8822B(x) \
+ (((x) & BIT_MASK_FREE_TXPG_SEQ_8822B) << BIT_SHIFT_FREE_TXPG_SEQ_8822B)
+#define BITS_FREE_TXPG_SEQ_8822B \
+ (BIT_MASK_FREE_TXPG_SEQ_8822B << BIT_SHIFT_FREE_TXPG_SEQ_8822B)
+#define BIT_CLEAR_FREE_TXPG_SEQ_8822B(x) ((x) & (~BITS_FREE_TXPG_SEQ_8822B))
+#define BIT_GET_FREE_TXPG_SEQ_8822B(x) \
+ (((x) >> BIT_SHIFT_FREE_TXPG_SEQ_8822B) & BIT_MASK_FREE_TXPG_SEQ_8822B)
+#define BIT_SET_FREE_TXPG_SEQ_8822B(x, v) \
+ (BIT_CLEAR_FREE_TXPG_SEQ_8822B(x) | BIT_FREE_TXPG_SEQ_8822B(v))
/* 2 REG_SDIO_FREE_TXPG_8822B */
#define BIT_SHIFT_MID_FREEPG_V1_8822B 16
#define BIT_MASK_MID_FREEPG_V1_8822B 0xfff
-#define BIT_MID_FREEPG_V1_8822B(x) (((x) & BIT_MASK_MID_FREEPG_V1_8822B) << BIT_SHIFT_MID_FREEPG_V1_8822B)
-#define BIT_GET_MID_FREEPG_V1_8822B(x) (((x) >> BIT_SHIFT_MID_FREEPG_V1_8822B) & BIT_MASK_MID_FREEPG_V1_8822B)
-
+#define BIT_MID_FREEPG_V1_8822B(x) \
+ (((x) & BIT_MASK_MID_FREEPG_V1_8822B) << BIT_SHIFT_MID_FREEPG_V1_8822B)
+#define BITS_MID_FREEPG_V1_8822B \
+ (BIT_MASK_MID_FREEPG_V1_8822B << BIT_SHIFT_MID_FREEPG_V1_8822B)
+#define BIT_CLEAR_MID_FREEPG_V1_8822B(x) ((x) & (~BITS_MID_FREEPG_V1_8822B))
+#define BIT_GET_MID_FREEPG_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_MID_FREEPG_V1_8822B) & BIT_MASK_MID_FREEPG_V1_8822B)
+#define BIT_SET_MID_FREEPG_V1_8822B(x, v) \
+ (BIT_CLEAR_MID_FREEPG_V1_8822B(x) | BIT_MID_FREEPG_V1_8822B(v))
#define BIT_SHIFT_HIQ_FREEPG_V1_8822B 0
#define BIT_MASK_HIQ_FREEPG_V1_8822B 0xfff
-#define BIT_HIQ_FREEPG_V1_8822B(x) (((x) & BIT_MASK_HIQ_FREEPG_V1_8822B) << BIT_SHIFT_HIQ_FREEPG_V1_8822B)
-#define BIT_GET_HIQ_FREEPG_V1_8822B(x) (((x) >> BIT_SHIFT_HIQ_FREEPG_V1_8822B) & BIT_MASK_HIQ_FREEPG_V1_8822B)
-
+#define BIT_HIQ_FREEPG_V1_8822B(x) \
+ (((x) & BIT_MASK_HIQ_FREEPG_V1_8822B) << BIT_SHIFT_HIQ_FREEPG_V1_8822B)
+#define BITS_HIQ_FREEPG_V1_8822B \
+ (BIT_MASK_HIQ_FREEPG_V1_8822B << BIT_SHIFT_HIQ_FREEPG_V1_8822B)
+#define BIT_CLEAR_HIQ_FREEPG_V1_8822B(x) ((x) & (~BITS_HIQ_FREEPG_V1_8822B))
+#define BIT_GET_HIQ_FREEPG_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_HIQ_FREEPG_V1_8822B) & BIT_MASK_HIQ_FREEPG_V1_8822B)
+#define BIT_SET_HIQ_FREEPG_V1_8822B(x, v) \
+ (BIT_CLEAR_HIQ_FREEPG_V1_8822B(x) | BIT_HIQ_FREEPG_V1_8822B(v))
/* 2 REG_SDIO_FREE_TXPG2_8822B */
#define BIT_SHIFT_PUB_FREEPG_V1_8822B 16
#define BIT_MASK_PUB_FREEPG_V1_8822B 0xfff
-#define BIT_PUB_FREEPG_V1_8822B(x) (((x) & BIT_MASK_PUB_FREEPG_V1_8822B) << BIT_SHIFT_PUB_FREEPG_V1_8822B)
-#define BIT_GET_PUB_FREEPG_V1_8822B(x) (((x) >> BIT_SHIFT_PUB_FREEPG_V1_8822B) & BIT_MASK_PUB_FREEPG_V1_8822B)
-
+#define BIT_PUB_FREEPG_V1_8822B(x) \
+ (((x) & BIT_MASK_PUB_FREEPG_V1_8822B) << BIT_SHIFT_PUB_FREEPG_V1_8822B)
+#define BITS_PUB_FREEPG_V1_8822B \
+ (BIT_MASK_PUB_FREEPG_V1_8822B << BIT_SHIFT_PUB_FREEPG_V1_8822B)
+#define BIT_CLEAR_PUB_FREEPG_V1_8822B(x) ((x) & (~BITS_PUB_FREEPG_V1_8822B))
+#define BIT_GET_PUB_FREEPG_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_PUB_FREEPG_V1_8822B) & BIT_MASK_PUB_FREEPG_V1_8822B)
+#define BIT_SET_PUB_FREEPG_V1_8822B(x, v) \
+ (BIT_CLEAR_PUB_FREEPG_V1_8822B(x) | BIT_PUB_FREEPG_V1_8822B(v))
#define BIT_SHIFT_LOW_FREEPG_V1_8822B 0
#define BIT_MASK_LOW_FREEPG_V1_8822B 0xfff
-#define BIT_LOW_FREEPG_V1_8822B(x) (((x) & BIT_MASK_LOW_FREEPG_V1_8822B) << BIT_SHIFT_LOW_FREEPG_V1_8822B)
-#define BIT_GET_LOW_FREEPG_V1_8822B(x) (((x) >> BIT_SHIFT_LOW_FREEPG_V1_8822B) & BIT_MASK_LOW_FREEPG_V1_8822B)
-
+#define BIT_LOW_FREEPG_V1_8822B(x) \
+ (((x) & BIT_MASK_LOW_FREEPG_V1_8822B) << BIT_SHIFT_LOW_FREEPG_V1_8822B)
+#define BITS_LOW_FREEPG_V1_8822B \
+ (BIT_MASK_LOW_FREEPG_V1_8822B << BIT_SHIFT_LOW_FREEPG_V1_8822B)
+#define BIT_CLEAR_LOW_FREEPG_V1_8822B(x) ((x) & (~BITS_LOW_FREEPG_V1_8822B))
+#define BIT_GET_LOW_FREEPG_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_LOW_FREEPG_V1_8822B) & BIT_MASK_LOW_FREEPG_V1_8822B)
+#define BIT_SET_LOW_FREEPG_V1_8822B(x, v) \
+ (BIT_CLEAR_LOW_FREEPG_V1_8822B(x) | BIT_LOW_FREEPG_V1_8822B(v))
/* 2 REG_SDIO_OQT_FREE_TXPG_V1_8822B */
#define BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822B 24
#define BIT_MASK_NOAC_OQT_FREEPG_V1_8822B 0xff
-#define BIT_NOAC_OQT_FREEPG_V1_8822B(x) (((x) & BIT_MASK_NOAC_OQT_FREEPG_V1_8822B) << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822B)
-#define BIT_GET_NOAC_OQT_FREEPG_V1_8822B(x) (((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822B) & BIT_MASK_NOAC_OQT_FREEPG_V1_8822B)
-
+#define BIT_NOAC_OQT_FREEPG_V1_8822B(x) \
+ (((x) & BIT_MASK_NOAC_OQT_FREEPG_V1_8822B) \
+ << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822B)
+#define BITS_NOAC_OQT_FREEPG_V1_8822B \
+ (BIT_MASK_NOAC_OQT_FREEPG_V1_8822B \
+ << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822B)
+#define BIT_CLEAR_NOAC_OQT_FREEPG_V1_8822B(x) \
+ ((x) & (~BITS_NOAC_OQT_FREEPG_V1_8822B))
+#define BIT_GET_NOAC_OQT_FREEPG_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822B) & \
+ BIT_MASK_NOAC_OQT_FREEPG_V1_8822B)
+#define BIT_SET_NOAC_OQT_FREEPG_V1_8822B(x, v) \
+ (BIT_CLEAR_NOAC_OQT_FREEPG_V1_8822B(x) | \
+ BIT_NOAC_OQT_FREEPG_V1_8822B(v))
#define BIT_SHIFT_AC_OQT_FREEPG_V1_8822B 16
#define BIT_MASK_AC_OQT_FREEPG_V1_8822B 0xff
-#define BIT_AC_OQT_FREEPG_V1_8822B(x) (((x) & BIT_MASK_AC_OQT_FREEPG_V1_8822B) << BIT_SHIFT_AC_OQT_FREEPG_V1_8822B)
-#define BIT_GET_AC_OQT_FREEPG_V1_8822B(x) (((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1_8822B) & BIT_MASK_AC_OQT_FREEPG_V1_8822B)
-
+#define BIT_AC_OQT_FREEPG_V1_8822B(x) \
+ (((x) & BIT_MASK_AC_OQT_FREEPG_V1_8822B) \
+ << BIT_SHIFT_AC_OQT_FREEPG_V1_8822B)
+#define BITS_AC_OQT_FREEPG_V1_8822B \
+ (BIT_MASK_AC_OQT_FREEPG_V1_8822B << BIT_SHIFT_AC_OQT_FREEPG_V1_8822B)
+#define BIT_CLEAR_AC_OQT_FREEPG_V1_8822B(x) \
+ ((x) & (~BITS_AC_OQT_FREEPG_V1_8822B))
+#define BIT_GET_AC_OQT_FREEPG_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1_8822B) & \
+ BIT_MASK_AC_OQT_FREEPG_V1_8822B)
+#define BIT_SET_AC_OQT_FREEPG_V1_8822B(x, v) \
+ (BIT_CLEAR_AC_OQT_FREEPG_V1_8822B(x) | BIT_AC_OQT_FREEPG_V1_8822B(v))
#define BIT_SHIFT_EXQ_FREEPG_V1_8822B 0
#define BIT_MASK_EXQ_FREEPG_V1_8822B 0xfff
-#define BIT_EXQ_FREEPG_V1_8822B(x) (((x) & BIT_MASK_EXQ_FREEPG_V1_8822B) << BIT_SHIFT_EXQ_FREEPG_V1_8822B)
-#define BIT_GET_EXQ_FREEPG_V1_8822B(x) (((x) >> BIT_SHIFT_EXQ_FREEPG_V1_8822B) & BIT_MASK_EXQ_FREEPG_V1_8822B)
-
+#define BIT_EXQ_FREEPG_V1_8822B(x) \
+ (((x) & BIT_MASK_EXQ_FREEPG_V1_8822B) << BIT_SHIFT_EXQ_FREEPG_V1_8822B)
+#define BITS_EXQ_FREEPG_V1_8822B \
+ (BIT_MASK_EXQ_FREEPG_V1_8822B << BIT_SHIFT_EXQ_FREEPG_V1_8822B)
+#define BIT_CLEAR_EXQ_FREEPG_V1_8822B(x) ((x) & (~BITS_EXQ_FREEPG_V1_8822B))
+#define BIT_GET_EXQ_FREEPG_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_EXQ_FREEPG_V1_8822B) & BIT_MASK_EXQ_FREEPG_V1_8822B)
+#define BIT_SET_EXQ_FREEPG_V1_8822B(x, v) \
+ (BIT_CLEAR_EXQ_FREEPG_V1_8822B(x) | BIT_EXQ_FREEPG_V1_8822B(v))
/* 2 REG_SDIO_HTSFR_INFO_8822B */
#define BIT_SHIFT_HTSFR1_8822B 16
#define BIT_MASK_HTSFR1_8822B 0xffff
-#define BIT_HTSFR1_8822B(x) (((x) & BIT_MASK_HTSFR1_8822B) << BIT_SHIFT_HTSFR1_8822B)
-#define BIT_GET_HTSFR1_8822B(x) (((x) >> BIT_SHIFT_HTSFR1_8822B) & BIT_MASK_HTSFR1_8822B)
-
+#define BIT_HTSFR1_8822B(x) \
+ (((x) & BIT_MASK_HTSFR1_8822B) << BIT_SHIFT_HTSFR1_8822B)
+#define BITS_HTSFR1_8822B (BIT_MASK_HTSFR1_8822B << BIT_SHIFT_HTSFR1_8822B)
+#define BIT_CLEAR_HTSFR1_8822B(x) ((x) & (~BITS_HTSFR1_8822B))
+#define BIT_GET_HTSFR1_8822B(x) \
+ (((x) >> BIT_SHIFT_HTSFR1_8822B) & BIT_MASK_HTSFR1_8822B)
+#define BIT_SET_HTSFR1_8822B(x, v) \
+ (BIT_CLEAR_HTSFR1_8822B(x) | BIT_HTSFR1_8822B(v))
#define BIT_SHIFT_HTSFR0_8822B 0
#define BIT_MASK_HTSFR0_8822B 0xffff
-#define BIT_HTSFR0_8822B(x) (((x) & BIT_MASK_HTSFR0_8822B) << BIT_SHIFT_HTSFR0_8822B)
-#define BIT_GET_HTSFR0_8822B(x) (((x) >> BIT_SHIFT_HTSFR0_8822B) & BIT_MASK_HTSFR0_8822B)
-
+#define BIT_HTSFR0_8822B(x) \
+ (((x) & BIT_MASK_HTSFR0_8822B) << BIT_SHIFT_HTSFR0_8822B)
+#define BITS_HTSFR0_8822B (BIT_MASK_HTSFR0_8822B << BIT_SHIFT_HTSFR0_8822B)
+#define BIT_CLEAR_HTSFR0_8822B(x) ((x) & (~BITS_HTSFR0_8822B))
+#define BIT_GET_HTSFR0_8822B(x) \
+ (((x) >> BIT_SHIFT_HTSFR0_8822B) & BIT_MASK_HTSFR0_8822B)
+#define BIT_SET_HTSFR0_8822B(x, v) \
+ (BIT_CLEAR_HTSFR0_8822B(x) | BIT_HTSFR0_8822B(v))
/* 2 REG_SDIO_HCPWM1_V2_8822B */
-#define BIT_TOGGLING_8822B BIT(7)
-#define BIT_WWLAN_8822B BIT(3)
-#define BIT_RPS_ST_8822B BIT(2)
-#define BIT_WLAN_TRX_8822B BIT(1)
-#define BIT_SYS_CLK_8822B BIT(0)
+#define BIT_TOGGLE_8822B BIT(7)
+#define BIT_CUR_PS_8822B BIT(0)
/* 2 REG_SDIO_HCPWM2_V2_8822B */
@@ -9794,46 +17634,83 @@
#define BIT_SHIFT_INDIRECT_REG_SIZE_8822B 16
#define BIT_MASK_INDIRECT_REG_SIZE_8822B 0x3
-#define BIT_INDIRECT_REG_SIZE_8822B(x) (((x) & BIT_MASK_INDIRECT_REG_SIZE_8822B) << BIT_SHIFT_INDIRECT_REG_SIZE_8822B)
-#define BIT_GET_INDIRECT_REG_SIZE_8822B(x) (((x) >> BIT_SHIFT_INDIRECT_REG_SIZE_8822B) & BIT_MASK_INDIRECT_REG_SIZE_8822B)
-
+#define BIT_INDIRECT_REG_SIZE_8822B(x) \
+ (((x) & BIT_MASK_INDIRECT_REG_SIZE_8822B) \
+ << BIT_SHIFT_INDIRECT_REG_SIZE_8822B)
+#define BITS_INDIRECT_REG_SIZE_8822B \
+ (BIT_MASK_INDIRECT_REG_SIZE_8822B << BIT_SHIFT_INDIRECT_REG_SIZE_8822B)
+#define BIT_CLEAR_INDIRECT_REG_SIZE_8822B(x) \
+ ((x) & (~BITS_INDIRECT_REG_SIZE_8822B))
+#define BIT_GET_INDIRECT_REG_SIZE_8822B(x) \
+ (((x) >> BIT_SHIFT_INDIRECT_REG_SIZE_8822B) & \
+ BIT_MASK_INDIRECT_REG_SIZE_8822B)
+#define BIT_SET_INDIRECT_REG_SIZE_8822B(x, v) \
+ (BIT_CLEAR_INDIRECT_REG_SIZE_8822B(x) | BIT_INDIRECT_REG_SIZE_8822B(v))
#define BIT_SHIFT_INDIRECT_REG_ADDR_8822B 0
#define BIT_MASK_INDIRECT_REG_ADDR_8822B 0xffff
-#define BIT_INDIRECT_REG_ADDR_8822B(x) (((x) & BIT_MASK_INDIRECT_REG_ADDR_8822B) << BIT_SHIFT_INDIRECT_REG_ADDR_8822B)
-#define BIT_GET_INDIRECT_REG_ADDR_8822B(x) (((x) >> BIT_SHIFT_INDIRECT_REG_ADDR_8822B) & BIT_MASK_INDIRECT_REG_ADDR_8822B)
-
+#define BIT_INDIRECT_REG_ADDR_8822B(x) \
+ (((x) & BIT_MASK_INDIRECT_REG_ADDR_8822B) \
+ << BIT_SHIFT_INDIRECT_REG_ADDR_8822B)
+#define BITS_INDIRECT_REG_ADDR_8822B \
+ (BIT_MASK_INDIRECT_REG_ADDR_8822B << BIT_SHIFT_INDIRECT_REG_ADDR_8822B)
+#define BIT_CLEAR_INDIRECT_REG_ADDR_8822B(x) \
+ ((x) & (~BITS_INDIRECT_REG_ADDR_8822B))
+#define BIT_GET_INDIRECT_REG_ADDR_8822B(x) \
+ (((x) >> BIT_SHIFT_INDIRECT_REG_ADDR_8822B) & \
+ BIT_MASK_INDIRECT_REG_ADDR_8822B)
+#define BIT_SET_INDIRECT_REG_ADDR_8822B(x, v) \
+ (BIT_CLEAR_INDIRECT_REG_ADDR_8822B(x) | BIT_INDIRECT_REG_ADDR_8822B(v))
/* 2 REG_SDIO_INDIRECT_REG_DATA_8822B */
#define BIT_SHIFT_INDIRECT_REG_DATA_8822B 0
#define BIT_MASK_INDIRECT_REG_DATA_8822B 0xffffffffL
-#define BIT_INDIRECT_REG_DATA_8822B(x) (((x) & BIT_MASK_INDIRECT_REG_DATA_8822B) << BIT_SHIFT_INDIRECT_REG_DATA_8822B)
-#define BIT_GET_INDIRECT_REG_DATA_8822B(x) (((x) >> BIT_SHIFT_INDIRECT_REG_DATA_8822B) & BIT_MASK_INDIRECT_REG_DATA_8822B)
-
+#define BIT_INDIRECT_REG_DATA_8822B(x) \
+ (((x) & BIT_MASK_INDIRECT_REG_DATA_8822B) \
+ << BIT_SHIFT_INDIRECT_REG_DATA_8822B)
+#define BITS_INDIRECT_REG_DATA_8822B \
+ (BIT_MASK_INDIRECT_REG_DATA_8822B << BIT_SHIFT_INDIRECT_REG_DATA_8822B)
+#define BIT_CLEAR_INDIRECT_REG_DATA_8822B(x) \
+ ((x) & (~BITS_INDIRECT_REG_DATA_8822B))
+#define BIT_GET_INDIRECT_REG_DATA_8822B(x) \
+ (((x) >> BIT_SHIFT_INDIRECT_REG_DATA_8822B) & \
+ BIT_MASK_INDIRECT_REG_DATA_8822B)
+#define BIT_SET_INDIRECT_REG_DATA_8822B(x, v) \
+ (BIT_CLEAR_INDIRECT_REG_DATA_8822B(x) | BIT_INDIRECT_REG_DATA_8822B(v))
/* 2 REG_SDIO_H2C_8822B */
#define BIT_SHIFT_SDIO_H2C_MSG_8822B 0
#define BIT_MASK_SDIO_H2C_MSG_8822B 0xffffffffL
-#define BIT_SDIO_H2C_MSG_8822B(x) (((x) & BIT_MASK_SDIO_H2C_MSG_8822B) << BIT_SHIFT_SDIO_H2C_MSG_8822B)
-#define BIT_GET_SDIO_H2C_MSG_8822B(x) (((x) >> BIT_SHIFT_SDIO_H2C_MSG_8822B) & BIT_MASK_SDIO_H2C_MSG_8822B)
-
+#define BIT_SDIO_H2C_MSG_8822B(x) \
+ (((x) & BIT_MASK_SDIO_H2C_MSG_8822B) << BIT_SHIFT_SDIO_H2C_MSG_8822B)
+#define BITS_SDIO_H2C_MSG_8822B \
+ (BIT_MASK_SDIO_H2C_MSG_8822B << BIT_SHIFT_SDIO_H2C_MSG_8822B)
+#define BIT_CLEAR_SDIO_H2C_MSG_8822B(x) ((x) & (~BITS_SDIO_H2C_MSG_8822B))
+#define BIT_GET_SDIO_H2C_MSG_8822B(x) \
+ (((x) >> BIT_SHIFT_SDIO_H2C_MSG_8822B) & BIT_MASK_SDIO_H2C_MSG_8822B)
+#define BIT_SET_SDIO_H2C_MSG_8822B(x, v) \
+ (BIT_CLEAR_SDIO_H2C_MSG_8822B(x) | BIT_SDIO_H2C_MSG_8822B(v))
/* 2 REG_SDIO_C2H_8822B */
#define BIT_SHIFT_SDIO_C2H_MSG_8822B 0
#define BIT_MASK_SDIO_C2H_MSG_8822B 0xffffffffL
-#define BIT_SDIO_C2H_MSG_8822B(x) (((x) & BIT_MASK_SDIO_C2H_MSG_8822B) << BIT_SHIFT_SDIO_C2H_MSG_8822B)
-#define BIT_GET_SDIO_C2H_MSG_8822B(x) (((x) >> BIT_SHIFT_SDIO_C2H_MSG_8822B) & BIT_MASK_SDIO_C2H_MSG_8822B)
-
+#define BIT_SDIO_C2H_MSG_8822B(x) \
+ (((x) & BIT_MASK_SDIO_C2H_MSG_8822B) << BIT_SHIFT_SDIO_C2H_MSG_8822B)
+#define BITS_SDIO_C2H_MSG_8822B \
+ (BIT_MASK_SDIO_C2H_MSG_8822B << BIT_SHIFT_SDIO_C2H_MSG_8822B)
+#define BIT_CLEAR_SDIO_C2H_MSG_8822B(x) ((x) & (~BITS_SDIO_C2H_MSG_8822B))
+#define BIT_GET_SDIO_C2H_MSG_8822B(x) \
+ (((x) >> BIT_SHIFT_SDIO_C2H_MSG_8822B) & BIT_MASK_SDIO_C2H_MSG_8822B)
+#define BIT_SET_SDIO_C2H_MSG_8822B(x, v) \
+ (BIT_CLEAR_SDIO_C2H_MSG_8822B(x) | BIT_SDIO_C2H_MSG_8822B(v))
/* 2 REG_SDIO_HRPWM1_8822B */
-#define BIT_TOGGLING_8822B BIT(7)
-#define BIT_WWLAN_8822B BIT(3)
-#define BIT_RPS_ST_8822B BIT(2)
-#define BIT_WLAN_TRX_8822B BIT(1)
-#define BIT_SYS_CLK_8822B BIT(0)
+#define BIT_TOGGLE_8822B BIT(7)
+#define BIT_ACK_8822B BIT(6)
+#define BIT_REQ_PS_8822B BIT(0)
/* 2 REG_SDIO_HRPWM2_8822B */
@@ -9856,31 +17733,45 @@
#define BIT_SHIFT_CMDIN_2RESP_TIMER_8822B 0
#define BIT_MASK_CMDIN_2RESP_TIMER_8822B 0xffff
-#define BIT_CMDIN_2RESP_TIMER_8822B(x) (((x) & BIT_MASK_CMDIN_2RESP_TIMER_8822B) << BIT_SHIFT_CMDIN_2RESP_TIMER_8822B)
-#define BIT_GET_CMDIN_2RESP_TIMER_8822B(x) (((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER_8822B) & BIT_MASK_CMDIN_2RESP_TIMER_8822B)
-
+#define BIT_CMDIN_2RESP_TIMER_8822B(x) \
+ (((x) & BIT_MASK_CMDIN_2RESP_TIMER_8822B) \
+ << BIT_SHIFT_CMDIN_2RESP_TIMER_8822B)
+#define BITS_CMDIN_2RESP_TIMER_8822B \
+ (BIT_MASK_CMDIN_2RESP_TIMER_8822B << BIT_SHIFT_CMDIN_2RESP_TIMER_8822B)
+#define BIT_CLEAR_CMDIN_2RESP_TIMER_8822B(x) \
+ ((x) & (~BITS_CMDIN_2RESP_TIMER_8822B))
+#define BIT_GET_CMDIN_2RESP_TIMER_8822B(x) \
+ (((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER_8822B) & \
+ BIT_MASK_CMDIN_2RESP_TIMER_8822B)
+#define BIT_SET_CMDIN_2RESP_TIMER_8822B(x, v) \
+ (BIT_CLEAR_CMDIN_2RESP_TIMER_8822B(x) | BIT_CMDIN_2RESP_TIMER_8822B(v))
/* 2 REG_SDIO_CMD_CRC_8822B */
#define BIT_SHIFT_SDIO_CMD_CRC_V1_8822B 0
#define BIT_MASK_SDIO_CMD_CRC_V1_8822B 0xff
-#define BIT_SDIO_CMD_CRC_V1_8822B(x) (((x) & BIT_MASK_SDIO_CMD_CRC_V1_8822B) << BIT_SHIFT_SDIO_CMD_CRC_V1_8822B)
-#define BIT_GET_SDIO_CMD_CRC_V1_8822B(x) (((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1_8822B) & BIT_MASK_SDIO_CMD_CRC_V1_8822B)
-
+#define BIT_SDIO_CMD_CRC_V1_8822B(x) \
+ (((x) & BIT_MASK_SDIO_CMD_CRC_V1_8822B) \
+ << BIT_SHIFT_SDIO_CMD_CRC_V1_8822B)
+#define BITS_SDIO_CMD_CRC_V1_8822B \
+ (BIT_MASK_SDIO_CMD_CRC_V1_8822B << BIT_SHIFT_SDIO_CMD_CRC_V1_8822B)
+#define BIT_CLEAR_SDIO_CMD_CRC_V1_8822B(x) ((x) & (~BITS_SDIO_CMD_CRC_V1_8822B))
+#define BIT_GET_SDIO_CMD_CRC_V1_8822B(x) \
+ (((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1_8822B) & \
+ BIT_MASK_SDIO_CMD_CRC_V1_8822B)
+#define BIT_SET_SDIO_CMD_CRC_V1_8822B(x, v) \
+ (BIT_CLEAR_SDIO_CMD_CRC_V1_8822B(x) | BIT_SDIO_CMD_CRC_V1_8822B(v))
/* 2 REG_SDIO_HSISR_8822B */
#define BIT_DRV_WLAN_INT_CLR_8822B BIT(1)
#define BIT_DRV_WLAN_INT_8822B BIT(0)
-/* 2 REG_SDIO_HSIMR_8822B */
-#define BIT_HISR_MASK_8822B BIT(0)
-
/* 2 REG_SDIO_ERR_RPT_8822B */
#define BIT_HR_FF_OVF_8822B BIT(6)
#define BIT_HR_FF_UDN_8822B BIT(5)
#define BIT_TXDMA_BUSY_ERR_8822B BIT(4)
#define BIT_TXDMA_VLD_ERR_8822B BIT(3)
-#define BIT_QSEL_UNKOWN_ERR_8822B BIT(2)
+#define BIT_QSEL_UNKNOWN_ERR_8822B BIT(2)
#define BIT_QSEL_MIS_ERR_8822B BIT(1)
#define BIT_SDIO_OVERRD_ERR_8822B BIT(0)
@@ -9888,25 +17779,53 @@
#define BIT_SHIFT_CMD_CRC_ERR_CNT_8822B 0
#define BIT_MASK_CMD_CRC_ERR_CNT_8822B 0xff
-#define BIT_CMD_CRC_ERR_CNT_8822B(x) (((x) & BIT_MASK_CMD_CRC_ERR_CNT_8822B) << BIT_SHIFT_CMD_CRC_ERR_CNT_8822B)
-#define BIT_GET_CMD_CRC_ERR_CNT_8822B(x) (((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT_8822B) & BIT_MASK_CMD_CRC_ERR_CNT_8822B)
-
+#define BIT_CMD_CRC_ERR_CNT_8822B(x) \
+ (((x) & BIT_MASK_CMD_CRC_ERR_CNT_8822B) \
+ << BIT_SHIFT_CMD_CRC_ERR_CNT_8822B)
+#define BITS_CMD_CRC_ERR_CNT_8822B \
+ (BIT_MASK_CMD_CRC_ERR_CNT_8822B << BIT_SHIFT_CMD_CRC_ERR_CNT_8822B)
+#define BIT_CLEAR_CMD_CRC_ERR_CNT_8822B(x) ((x) & (~BITS_CMD_CRC_ERR_CNT_8822B))
+#define BIT_GET_CMD_CRC_ERR_CNT_8822B(x) \
+ (((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT_8822B) & \
+ BIT_MASK_CMD_CRC_ERR_CNT_8822B)
+#define BIT_SET_CMD_CRC_ERR_CNT_8822B(x, v) \
+ (BIT_CLEAR_CMD_CRC_ERR_CNT_8822B(x) | BIT_CMD_CRC_ERR_CNT_8822B(v))
/* 2 REG_SDIO_DATA_ERRCNT_8822B */
#define BIT_SHIFT_DATA_CRC_ERR_CNT_8822B 0
#define BIT_MASK_DATA_CRC_ERR_CNT_8822B 0xff
-#define BIT_DATA_CRC_ERR_CNT_8822B(x) (((x) & BIT_MASK_DATA_CRC_ERR_CNT_8822B) << BIT_SHIFT_DATA_CRC_ERR_CNT_8822B)
-#define BIT_GET_DATA_CRC_ERR_CNT_8822B(x) (((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT_8822B) & BIT_MASK_DATA_CRC_ERR_CNT_8822B)
-
+#define BIT_DATA_CRC_ERR_CNT_8822B(x) \
+ (((x) & BIT_MASK_DATA_CRC_ERR_CNT_8822B) \
+ << BIT_SHIFT_DATA_CRC_ERR_CNT_8822B)
+#define BITS_DATA_CRC_ERR_CNT_8822B \
+ (BIT_MASK_DATA_CRC_ERR_CNT_8822B << BIT_SHIFT_DATA_CRC_ERR_CNT_8822B)
+#define BIT_CLEAR_DATA_CRC_ERR_CNT_8822B(x) \
+ ((x) & (~BITS_DATA_CRC_ERR_CNT_8822B))
+#define BIT_GET_DATA_CRC_ERR_CNT_8822B(x) \
+ (((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT_8822B) & \
+ BIT_MASK_DATA_CRC_ERR_CNT_8822B)
+#define BIT_SET_DATA_CRC_ERR_CNT_8822B(x, v) \
+ (BIT_CLEAR_DATA_CRC_ERR_CNT_8822B(x) | BIT_DATA_CRC_ERR_CNT_8822B(v))
/* 2 REG_SDIO_CMD_ERR_CONTENT_8822B */
#define BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822B 0
#define BIT_MASK_SDIO_CMD_ERR_CONTENT_8822B 0xffffffffffL
-#define BIT_SDIO_CMD_ERR_CONTENT_8822B(x) (((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8822B) << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822B)
-#define BIT_GET_SDIO_CMD_ERR_CONTENT_8822B(x) (((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822B) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8822B)
-
+#define BIT_SDIO_CMD_ERR_CONTENT_8822B(x) \
+ (((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8822B) \
+ << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822B)
+#define BITS_SDIO_CMD_ERR_CONTENT_8822B \
+ (BIT_MASK_SDIO_CMD_ERR_CONTENT_8822B \
+ << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822B)
+#define BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8822B(x) \
+ ((x) & (~BITS_SDIO_CMD_ERR_CONTENT_8822B))
+#define BIT_GET_SDIO_CMD_ERR_CONTENT_8822B(x) \
+ (((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822B) & \
+ BIT_MASK_SDIO_CMD_ERR_CONTENT_8822B)
+#define BIT_SET_SDIO_CMD_ERR_CONTENT_8822B(x, v) \
+ (BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8822B(x) | \
+ BIT_SDIO_CMD_ERR_CONTENT_8822B(v))
/* 2 REG_SDIO_CRC_ERR_IDX_8822B */
#define BIT_D3_CRC_ERR_8822B BIT(4)
@@ -9918,17 +17837,34 @@
/* 2 REG_SDIO_DATA_CRC_8822B */
#define BIT_SHIFT_SDIO_DATA_CRC_8822B 0
-#define BIT_MASK_SDIO_DATA_CRC_8822B 0xff
-#define BIT_SDIO_DATA_CRC_8822B(x) (((x) & BIT_MASK_SDIO_DATA_CRC_8822B) << BIT_SHIFT_SDIO_DATA_CRC_8822B)
-#define BIT_GET_SDIO_DATA_CRC_8822B(x) (((x) >> BIT_SHIFT_SDIO_DATA_CRC_8822B) & BIT_MASK_SDIO_DATA_CRC_8822B)
-
+#define BIT_MASK_SDIO_DATA_CRC_8822B 0xffff
+#define BIT_SDIO_DATA_CRC_8822B(x) \
+ (((x) & BIT_MASK_SDIO_DATA_CRC_8822B) << BIT_SHIFT_SDIO_DATA_CRC_8822B)
+#define BITS_SDIO_DATA_CRC_8822B \
+ (BIT_MASK_SDIO_DATA_CRC_8822B << BIT_SHIFT_SDIO_DATA_CRC_8822B)
+#define BIT_CLEAR_SDIO_DATA_CRC_8822B(x) ((x) & (~BITS_SDIO_DATA_CRC_8822B))
+#define BIT_GET_SDIO_DATA_CRC_8822B(x) \
+ (((x) >> BIT_SHIFT_SDIO_DATA_CRC_8822B) & BIT_MASK_SDIO_DATA_CRC_8822B)
+#define BIT_SET_SDIO_DATA_CRC_8822B(x, v) \
+ (BIT_CLEAR_SDIO_DATA_CRC_8822B(x) | BIT_SDIO_DATA_CRC_8822B(v))
/* 2 REG_SDIO_DATA_REPLY_TIME_8822B */
#define BIT_SHIFT_SDIO_DATA_REPLY_TIME_8822B 0
#define BIT_MASK_SDIO_DATA_REPLY_TIME_8822B 0x7
-#define BIT_SDIO_DATA_REPLY_TIME_8822B(x) (((x) & BIT_MASK_SDIO_DATA_REPLY_TIME_8822B) << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8822B)
-#define BIT_GET_SDIO_DATA_REPLY_TIME_8822B(x) (((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME_8822B) & BIT_MASK_SDIO_DATA_REPLY_TIME_8822B)
-
+#define BIT_SDIO_DATA_REPLY_TIME_8822B(x) \
+ (((x) & BIT_MASK_SDIO_DATA_REPLY_TIME_8822B) \
+ << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8822B)
+#define BITS_SDIO_DATA_REPLY_TIME_8822B \
+ (BIT_MASK_SDIO_DATA_REPLY_TIME_8822B \
+ << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8822B)
+#define BIT_CLEAR_SDIO_DATA_REPLY_TIME_8822B(x) \
+ ((x) & (~BITS_SDIO_DATA_REPLY_TIME_8822B))
+#define BIT_GET_SDIO_DATA_REPLY_TIME_8822B(x) \
+ (((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME_8822B) & \
+ BIT_MASK_SDIO_DATA_REPLY_TIME_8822B)
+#define BIT_SET_SDIO_DATA_REPLY_TIME_8822B(x, v) \
+ (BIT_CLEAR_SDIO_DATA_REPLY_TIME_8822B(x) | \
+ BIT_SDIO_DATA_REPLY_TIME_8822B(v))
#endif
diff --git a/hal/halmac/halmac_bit_8822c.h b/hal/halmac/halmac_bit_8822c.h
new file mode 100644
index 0000000..7666902
--- /dev/null
+++ b/hal/halmac/halmac_bit_8822c.h
@@ -0,0 +1,21816 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef __INC_HALMAC_BIT_8822C_H
+#define __INC_HALMAC_BIT_8822C_H
+
+#define CPU_OPT_WIDTH 0x1F
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_SYS_ISO_CTRL_8822C */
+#define BIT_PWC_EV12V_8822C BIT(15)
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_PA33V_EN_8822C BIT(13)
+#define BIT_PA12V_EN_8822C BIT(12)
+#define BIT_UA33V_EN_8822C BIT(11)
+#define BIT_UA12V_EN_8822C BIT(10)
+#define BIT_ISO_RFDIO_8822C BIT(9)
+#define BIT_ISO_EB2CORE_8822C BIT(8)
+#define BIT_ISO_DIOE_8822C BIT(7)
+#define BIT_ISO_WLPON2PP_8822C BIT(6)
+#define BIT_ISO_IP2MAC_WA2PP_8822C BIT(5)
+#define BIT_ISO_PD2CORE_8822C BIT(4)
+#define BIT_ISO_PA2PCIE_8822C BIT(3)
+#define BIT_ISO_UD2CORE_8822C BIT(2)
+#define BIT_ISO_UA2USB_8822C BIT(1)
+#define BIT_ISO_WD2PP_8822C BIT(0)
+
+/* 2 REG_SYS_FUNC_EN_8822C */
+#define BIT_FEN_MREGEN_8822C BIT(15)
+#define BIT_FEN_HWPDN_8822C BIT(14)
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_FEN_ELDR_8822C BIT(12)
+#define BIT_FEN_DCORE_8822C BIT(11)
+#define BIT_FEN_CPUEN_8822C BIT(10)
+#define BIT_FEN_DIOE_8822C BIT(9)
+#define BIT_FEN_PCIED_8822C BIT(8)
+#define BIT_FEN_PPLL_8822C BIT(7)
+#define BIT_FEN_PCIEA_8822C BIT(6)
+#define BIT_FEN_DIO_PCIE_8822C BIT(5)
+#define BIT_FEN_USBD_8822C BIT(4)
+#define BIT_FEN_UPLL_8822C BIT(3)
+#define BIT_FEN_USBA_8822C BIT(2)
+#define BIT_FEN_BB_GLB_RSTN_8822C BIT(1)
+#define BIT_FEN_BBRSTB_8822C BIT(0)
+
+/* 2 REG_SYS_PW_CTRL_8822C */
+#define BIT_SOP_EABM_8822C BIT(31)
+#define BIT_SOP_ACKF_8822C BIT(30)
+#define BIT_SOP_ERCK_8822C BIT(29)
+#define BIT_SOP_ESWR_8822C BIT(28)
+#define BIT_SOP_PWMM_8822C BIT(27)
+#define BIT_SOP_EECK_8822C BIT(26)
+#define BIT_SOP_ANA_CLK_DIVISION_2_8822C BIT(25)
+#define BIT_SOP_EXTL_8822C BIT(24)
+#define BIT_SYM_OP_RING_12M_8822C BIT(22)
+#define BIT_ROP_SWPR_8822C BIT(21)
+#define BIT_DIS_HW_LPLDM_8822C BIT(20)
+#define BIT_OPT_SWRST_WLMCU_8822C BIT(19)
+#define BIT_RDY_SYSPWR_8822C BIT(17)
+#define BIT_EN_WLON_8822C BIT(16)
+#define BIT_APDM_HPDN_8822C BIT(15)
+#define BIT_AFSM_PCIE_SUS_EN_8822C BIT(12)
+#define BIT_AFSM_WLSUS_EN_8822C BIT(11)
+#define BIT_APFM_SWLPS_8822C BIT(10)
+#define BIT_APFM_OFFMAC_8822C BIT(9)
+#define BIT_APFN_ONMAC_8822C BIT(8)
+#define BIT_CHIP_PDN_EN_8822C BIT(7)
+#define BIT_RDY_MACDIS_8822C BIT(6)
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_PFM_WOWL_8822C BIT(3)
+#define BIT_PFM_LDKP_8822C BIT(2)
+#define BIT_WL_HCI_ALD_8822C BIT(1)
+#define BIT_PFM_LDALL_8822C BIT(0)
+
+/* 2 REG_SYS_CLK_CTRL_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_CPU_CLK_EN_8822C BIT(14)
+#define BIT_SYMREG_CLK_EN_8822C BIT(13)
+#define BIT_HCI_CLK_EN_8822C BIT(12)
+#define BIT_MAC_CLK_EN_8822C BIT(11)
+#define BIT_SEC_CLK_EN_8822C BIT(10)
+#define BIT_PHY_SSC_RSTB_8822C BIT(9)
+#define BIT_EXT_32K_EN_8822C BIT(8)
+#define BIT_WL_CLK_TEST_8822C BIT(7)
+#define BIT_OP_SPS_PWM_EN_8822C BIT(6)
+#define BIT_LOADER_CLK_EN_8822C BIT(5)
+#define BIT_MACSLP_8822C BIT(4)
+#define BIT_WAKEPAD_EN_8822C BIT(3)
+#define BIT_ROMD16V_EN_8822C BIT(2)
+#define BIT_ANA_CLK_DIVISION_2_8822C BIT(1)
+#define BIT_CNTD16V_EN_8822C BIT(0)
+
+/* 2 REG_SYS_EEPROM_CTRL_8822C */
+
+#define BIT_SHIFT_VPDIDX_8822C 8
+#define BIT_MASK_VPDIDX_8822C 0xff
+#define BIT_VPDIDX_8822C(x) \
+ (((x) & BIT_MASK_VPDIDX_8822C) << BIT_SHIFT_VPDIDX_8822C)
+#define BITS_VPDIDX_8822C (BIT_MASK_VPDIDX_8822C << BIT_SHIFT_VPDIDX_8822C)
+#define BIT_CLEAR_VPDIDX_8822C(x) ((x) & (~BITS_VPDIDX_8822C))
+#define BIT_GET_VPDIDX_8822C(x) \
+ (((x) >> BIT_SHIFT_VPDIDX_8822C) & BIT_MASK_VPDIDX_8822C)
+#define BIT_SET_VPDIDX_8822C(x, v) \
+ (BIT_CLEAR_VPDIDX_8822C(x) | BIT_VPDIDX_8822C(v))
+
+#define BIT_SHIFT_EEM1_0_8822C 6
+#define BIT_MASK_EEM1_0_8822C 0x3
+#define BIT_EEM1_0_8822C(x) \
+ (((x) & BIT_MASK_EEM1_0_8822C) << BIT_SHIFT_EEM1_0_8822C)
+#define BITS_EEM1_0_8822C (BIT_MASK_EEM1_0_8822C << BIT_SHIFT_EEM1_0_8822C)
+#define BIT_CLEAR_EEM1_0_8822C(x) ((x) & (~BITS_EEM1_0_8822C))
+#define BIT_GET_EEM1_0_8822C(x) \
+ (((x) >> BIT_SHIFT_EEM1_0_8822C) & BIT_MASK_EEM1_0_8822C)
+#define BIT_SET_EEM1_0_8822C(x, v) \
+ (BIT_CLEAR_EEM1_0_8822C(x) | BIT_EEM1_0_8822C(v))
+
+#define BIT_AUTOLOAD_SUS_8822C BIT(5)
+#define BIT_EERPOMSEL_8822C BIT(4)
+#define BIT_EECS_V1_8822C BIT(3)
+#define BIT_EESK_V1_8822C BIT(2)
+#define BIT_EEDI_V1_8822C BIT(1)
+#define BIT_EEDO_V1_8822C BIT(0)
+
+/* 2 REG_EE_VPD_8822C */
+
+#define BIT_SHIFT_VPD_DATA_8822C 0
+#define BIT_MASK_VPD_DATA_8822C 0xffffffffL
+#define BIT_VPD_DATA_8822C(x) \
+ (((x) & BIT_MASK_VPD_DATA_8822C) << BIT_SHIFT_VPD_DATA_8822C)
+#define BITS_VPD_DATA_8822C \
+ (BIT_MASK_VPD_DATA_8822C << BIT_SHIFT_VPD_DATA_8822C)
+#define BIT_CLEAR_VPD_DATA_8822C(x) ((x) & (~BITS_VPD_DATA_8822C))
+#define BIT_GET_VPD_DATA_8822C(x) \
+ (((x) >> BIT_SHIFT_VPD_DATA_8822C) & BIT_MASK_VPD_DATA_8822C)
+#define BIT_SET_VPD_DATA_8822C(x, v) \
+ (BIT_CLEAR_VPD_DATA_8822C(x) | BIT_VPD_DATA_8822C(v))
+
+/* 2 REG_SYS_SWR_CTRL1_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_HW_AUTO_CTRL_EXT_SWR_8822C BIT(9)
+#define BIT_USE_INTERNAL_SWR_AND_LDO_8822C BIT(8)
+#define BIT_MAC_ID_EN_8822C BIT(7)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_SYS_SWR_CTRL2_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_SW18_SEL_8822C BIT(13)
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_SW18_SD_8822C BIT(10)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_SYS_SWR_CTRL3_8822C */
+#define BIT_SPS18_OCP_DIS_8822C BIT(31)
+
+#define BIT_SHIFT_SPS18_OCP_TH_8822C 16
+#define BIT_MASK_SPS18_OCP_TH_8822C 0x7fff
+#define BIT_SPS18_OCP_TH_8822C(x) \
+ (((x) & BIT_MASK_SPS18_OCP_TH_8822C) << BIT_SHIFT_SPS18_OCP_TH_8822C)
+#define BITS_SPS18_OCP_TH_8822C \
+ (BIT_MASK_SPS18_OCP_TH_8822C << BIT_SHIFT_SPS18_OCP_TH_8822C)
+#define BIT_CLEAR_SPS18_OCP_TH_8822C(x) ((x) & (~BITS_SPS18_OCP_TH_8822C))
+#define BIT_GET_SPS18_OCP_TH_8822C(x) \
+ (((x) >> BIT_SHIFT_SPS18_OCP_TH_8822C) & BIT_MASK_SPS18_OCP_TH_8822C)
+#define BIT_SET_SPS18_OCP_TH_8822C(x, v) \
+ (BIT_CLEAR_SPS18_OCP_TH_8822C(x) | BIT_SPS18_OCP_TH_8822C(v))
+
+#define BIT_SHIFT_OCP_WINDOW_8822C 0
+#define BIT_MASK_OCP_WINDOW_8822C 0xffff
+#define BIT_OCP_WINDOW_8822C(x) \
+ (((x) & BIT_MASK_OCP_WINDOW_8822C) << BIT_SHIFT_OCP_WINDOW_8822C)
+#define BITS_OCP_WINDOW_8822C \
+ (BIT_MASK_OCP_WINDOW_8822C << BIT_SHIFT_OCP_WINDOW_8822C)
+#define BIT_CLEAR_OCP_WINDOW_8822C(x) ((x) & (~BITS_OCP_WINDOW_8822C))
+#define BIT_GET_OCP_WINDOW_8822C(x) \
+ (((x) >> BIT_SHIFT_OCP_WINDOW_8822C) & BIT_MASK_OCP_WINDOW_8822C)
+#define BIT_SET_OCP_WINDOW_8822C(x, v) \
+ (BIT_CLEAR_OCP_WINDOW_8822C(x) | BIT_OCP_WINDOW_8822C(v))
+
+/* 2 REG_RSV_CTRL_8822C */
+#define BIT_HREG_DBG_8822C BIT(23)
+#define BIT_WLMCUIOIF_8822C BIT(8)
+#define BIT_LOCK_ALL_EN_8822C BIT(7)
+#define BIT_R_DIS_PRST_8822C BIT(6)
+#define BIT_WLOCK_1C_B6_8822C BIT(5)
+#define BIT_WLOCK_40_8822C BIT(4)
+#define BIT_WLOCK_08_8822C BIT(3)
+#define BIT_WLOCK_04_8822C BIT(2)
+#define BIT_WLOCK_00_8822C BIT(1)
+#define BIT_WLOCK_ALL_8822C BIT(0)
+
+/* 2 REG_RF_CTRL_8822C */
+#define BIT_RF_SDMRSTB_8822C BIT(2)
+#define BIT_RF_RSTB_8822C BIT(1)
+#define BIT_RF_EN_8822C BIT(0)
+
+/* 2 REG_AFE_LDO_CTRL_8822C */
+#define BIT_R_SYM_WLBBOFF1_P4_EN_8822C BIT(9)
+#define BIT_R_SYM_WLBBOFF1_P3_EN_8822C BIT(8)
+#define BIT_R_SYM_WLBBOFF1_P2_EN_8822C BIT(7)
+#define BIT_R_SYM_WLBBOFF1_P1_EN_8822C BIT(6)
+#define BIT_R_SYM_WLBBOFF_P4_EN_8822C BIT(4)
+#define BIT_R_SYM_WLBBOFF_P3_EN_8822C BIT(3)
+#define BIT_R_SYM_WLBBOFF_P2_EN_8822C BIT(2)
+#define BIT_R_SYM_WLBBOFF_P1_EN_8822C BIT(1)
+#define BIT_R_SYM_WLBBOFF_EN_8822C BIT(0)
+
+/* 2 REG_AFE_CTRL1_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_MAC_CLK_SEL_8822C 20
+#define BIT_MASK_MAC_CLK_SEL_8822C 0x3
+#define BIT_MAC_CLK_SEL_8822C(x) \
+ (((x) & BIT_MASK_MAC_CLK_SEL_8822C) << BIT_SHIFT_MAC_CLK_SEL_8822C)
+#define BITS_MAC_CLK_SEL_8822C \
+ (BIT_MASK_MAC_CLK_SEL_8822C << BIT_SHIFT_MAC_CLK_SEL_8822C)
+#define BIT_CLEAR_MAC_CLK_SEL_8822C(x) ((x) & (~BITS_MAC_CLK_SEL_8822C))
+#define BIT_GET_MAC_CLK_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_MAC_CLK_SEL_8822C) & BIT_MASK_MAC_CLK_SEL_8822C)
+#define BIT_SET_MAC_CLK_SEL_8822C(x, v) \
+ (BIT_CLEAR_MAC_CLK_SEL_8822C(x) | BIT_MAC_CLK_SEL_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_ANAPARSW_POW_MAC_8822C */
+#define BIT_POW_LDO15_8822C BIT(2)
+#define BIT_POW_SW_8822C BIT(1)
+#define BIT_POW_LDO14_8822C BIT(0)
+
+/* 2 REG_ANAPARLDO_POW_MAC_8822C */
+#define BIT_LDOE25_POW_L_8822C BIT(0)
+
+/* 2 REG_ANAPAR_POW_MAC_8822C */
+#define BIT_DUMMY_V4_8822C BIT(7)
+#define BIT_DUMMY_V3_8822C BIT(6)
+#define BIT_DUMMY_V2_8822C BIT(5)
+#define BIT_DUMMY_V1_8822C BIT(4)
+#define BIT_POW_PC_LDO_PORT1_8822C BIT(3)
+#define BIT_POW_PC_LDO_PORT0_8822C BIT(2)
+#define BIT_POW_PLL_V1_8822C BIT(1)
+#define BIT_POW_POWER_CUT_POW_LDO_8822C BIT(0)
+
+/* 2 REG_ANAPAR_POW_XTAL_8822C */
+#define BIT_POW_XTAL_8822C BIT(1)
+#define BIT_POW_BG_8822C BIT(0)
+
+/* 2 REG_ANAPARLDO_MAC_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_REG_STANDBY_L_8822C BIT(19)
+#define BIT_PD_REGU_L_8822C BIT(18)
+#define BIT_EN_PC_BT_L_8822C BIT(17)
+
+#define BIT_SHIFT_REG_LDOADJ_L_8822C 13
+#define BIT_MASK_REG_LDOADJ_L_8822C 0xf
+#define BIT_REG_LDOADJ_L_8822C(x) \
+ (((x) & BIT_MASK_REG_LDOADJ_L_8822C) << BIT_SHIFT_REG_LDOADJ_L_8822C)
+#define BITS_REG_LDOADJ_L_8822C \
+ (BIT_MASK_REG_LDOADJ_L_8822C << BIT_SHIFT_REG_LDOADJ_L_8822C)
+#define BIT_CLEAR_REG_LDOADJ_L_8822C(x) ((x) & (~BITS_REG_LDOADJ_L_8822C))
+#define BIT_GET_REG_LDOADJ_L_8822C(x) \
+ (((x) >> BIT_SHIFT_REG_LDOADJ_L_8822C) & BIT_MASK_REG_LDOADJ_L_8822C)
+#define BIT_SET_REG_LDOADJ_L_8822C(x, v) \
+ (BIT_CLEAR_REG_LDOADJ_L_8822C(x) | BIT_REG_LDOADJ_L_8822C(v))
+
+#define BIT_CK12M_EN_8822C BIT(11)
+#define BIT_CK12M_SEL_8822C BIT(10)
+#define BIT_EN_25_L_8822C BIT(9)
+#define BIT_EN_SLEEP_8822C BIT(8)
+
+#define BIT_SHIFT_LDOH12_V12ADJ_L_8822C 4
+#define BIT_MASK_LDOH12_V12ADJ_L_8822C 0xf
+#define BIT_LDOH12_V12ADJ_L_8822C(x) \
+ (((x) & BIT_MASK_LDOH12_V12ADJ_L_8822C) \
+ << BIT_SHIFT_LDOH12_V12ADJ_L_8822C)
+#define BITS_LDOH12_V12ADJ_L_8822C \
+ (BIT_MASK_LDOH12_V12ADJ_L_8822C << BIT_SHIFT_LDOH12_V12ADJ_L_8822C)
+#define BIT_CLEAR_LDOH12_V12ADJ_L_8822C(x) ((x) & (~BITS_LDOH12_V12ADJ_L_8822C))
+#define BIT_GET_LDOH12_V12ADJ_L_8822C(x) \
+ (((x) >> BIT_SHIFT_LDOH12_V12ADJ_L_8822C) & \
+ BIT_MASK_LDOH12_V12ADJ_L_8822C)
+#define BIT_SET_LDOH12_V12ADJ_L_8822C(x, v) \
+ (BIT_CLEAR_LDOH12_V12ADJ_L_8822C(x) | BIT_LDOH12_V12ADJ_L_8822C(v))
+
+#define BIT_SHIFT_LDOE25_V12ADJ_L_V1_8822C 0
+#define BIT_MASK_LDOE25_V12ADJ_L_V1_8822C 0xf
+#define BIT_LDOE25_V12ADJ_L_V1_8822C(x) \
+ (((x) & BIT_MASK_LDOE25_V12ADJ_L_V1_8822C) \
+ << BIT_SHIFT_LDOE25_V12ADJ_L_V1_8822C)
+#define BITS_LDOE25_V12ADJ_L_V1_8822C \
+ (BIT_MASK_LDOE25_V12ADJ_L_V1_8822C \
+ << BIT_SHIFT_LDOE25_V12ADJ_L_V1_8822C)
+#define BIT_CLEAR_LDOE25_V12ADJ_L_V1_8822C(x) \
+ ((x) & (~BITS_LDOE25_V12ADJ_L_V1_8822C))
+#define BIT_GET_LDOE25_V12ADJ_L_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_V1_8822C) & \
+ BIT_MASK_LDOE25_V12ADJ_L_V1_8822C)
+#define BIT_SET_LDOE25_V12ADJ_L_V1_8822C(x, v) \
+ (BIT_CLEAR_LDOE25_V12ADJ_L_V1_8822C(x) | \
+ BIT_LDOE25_V12ADJ_L_V1_8822C(v))
+
+/* 2 REG_EFUSE_CTRL_8822C */
+#define BIT_EF_FLAG_8822C BIT(31)
+
+#define BIT_SHIFT_EF_PGPD_8822C 28
+#define BIT_MASK_EF_PGPD_8822C 0x7
+#define BIT_EF_PGPD_8822C(x) \
+ (((x) & BIT_MASK_EF_PGPD_8822C) << BIT_SHIFT_EF_PGPD_8822C)
+#define BITS_EF_PGPD_8822C (BIT_MASK_EF_PGPD_8822C << BIT_SHIFT_EF_PGPD_8822C)
+#define BIT_CLEAR_EF_PGPD_8822C(x) ((x) & (~BITS_EF_PGPD_8822C))
+#define BIT_GET_EF_PGPD_8822C(x) \
+ (((x) >> BIT_SHIFT_EF_PGPD_8822C) & BIT_MASK_EF_PGPD_8822C)
+#define BIT_SET_EF_PGPD_8822C(x, v) \
+ (BIT_CLEAR_EF_PGPD_8822C(x) | BIT_EF_PGPD_8822C(v))
+
+#define BIT_SHIFT_EF_RDT_8822C 24
+#define BIT_MASK_EF_RDT_8822C 0xf
+#define BIT_EF_RDT_8822C(x) \
+ (((x) & BIT_MASK_EF_RDT_8822C) << BIT_SHIFT_EF_RDT_8822C)
+#define BITS_EF_RDT_8822C (BIT_MASK_EF_RDT_8822C << BIT_SHIFT_EF_RDT_8822C)
+#define BIT_CLEAR_EF_RDT_8822C(x) ((x) & (~BITS_EF_RDT_8822C))
+#define BIT_GET_EF_RDT_8822C(x) \
+ (((x) >> BIT_SHIFT_EF_RDT_8822C) & BIT_MASK_EF_RDT_8822C)
+#define BIT_SET_EF_RDT_8822C(x, v) \
+ (BIT_CLEAR_EF_RDT_8822C(x) | BIT_EF_RDT_8822C(v))
+
+#define BIT_SHIFT_EF_PGTS_8822C 20
+#define BIT_MASK_EF_PGTS_8822C 0xf
+#define BIT_EF_PGTS_8822C(x) \
+ (((x) & BIT_MASK_EF_PGTS_8822C) << BIT_SHIFT_EF_PGTS_8822C)
+#define BITS_EF_PGTS_8822C (BIT_MASK_EF_PGTS_8822C << BIT_SHIFT_EF_PGTS_8822C)
+#define BIT_CLEAR_EF_PGTS_8822C(x) ((x) & (~BITS_EF_PGTS_8822C))
+#define BIT_GET_EF_PGTS_8822C(x) \
+ (((x) >> BIT_SHIFT_EF_PGTS_8822C) & BIT_MASK_EF_PGTS_8822C)
+#define BIT_SET_EF_PGTS_8822C(x, v) \
+ (BIT_CLEAR_EF_PGTS_8822C(x) | BIT_EF_PGTS_8822C(v))
+
+#define BIT_EF_PDWN_8822C BIT(19)
+#define BIT_EF_ALDEN_8822C BIT(18)
+
+#define BIT_SHIFT_EF_ADDR_8822C 8
+#define BIT_MASK_EF_ADDR_8822C 0x3ff
+#define BIT_EF_ADDR_8822C(x) \
+ (((x) & BIT_MASK_EF_ADDR_8822C) << BIT_SHIFT_EF_ADDR_8822C)
+#define BITS_EF_ADDR_8822C (BIT_MASK_EF_ADDR_8822C << BIT_SHIFT_EF_ADDR_8822C)
+#define BIT_CLEAR_EF_ADDR_8822C(x) ((x) & (~BITS_EF_ADDR_8822C))
+#define BIT_GET_EF_ADDR_8822C(x) \
+ (((x) >> BIT_SHIFT_EF_ADDR_8822C) & BIT_MASK_EF_ADDR_8822C)
+#define BIT_SET_EF_ADDR_8822C(x, v) \
+ (BIT_CLEAR_EF_ADDR_8822C(x) | BIT_EF_ADDR_8822C(v))
+
+#define BIT_SHIFT_EF_DATA_8822C 0
+#define BIT_MASK_EF_DATA_8822C 0xff
+#define BIT_EF_DATA_8822C(x) \
+ (((x) & BIT_MASK_EF_DATA_8822C) << BIT_SHIFT_EF_DATA_8822C)
+#define BITS_EF_DATA_8822C (BIT_MASK_EF_DATA_8822C << BIT_SHIFT_EF_DATA_8822C)
+#define BIT_CLEAR_EF_DATA_8822C(x) ((x) & (~BITS_EF_DATA_8822C))
+#define BIT_GET_EF_DATA_8822C(x) \
+ (((x) >> BIT_SHIFT_EF_DATA_8822C) & BIT_MASK_EF_DATA_8822C)
+#define BIT_SET_EF_DATA_8822C(x, v) \
+ (BIT_CLEAR_EF_DATA_8822C(x) | BIT_EF_DATA_8822C(v))
+
+/* 2 REG_LDO_EFUSE_CTRL_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_EF_CRES_SEL_8822C BIT(26)
+
+#define BIT_SHIFT_EF_SCAN_START_V1_8822C 16
+#define BIT_MASK_EF_SCAN_START_V1_8822C 0x3ff
+#define BIT_EF_SCAN_START_V1_8822C(x) \
+ (((x) & BIT_MASK_EF_SCAN_START_V1_8822C) \
+ << BIT_SHIFT_EF_SCAN_START_V1_8822C)
+#define BITS_EF_SCAN_START_V1_8822C \
+ (BIT_MASK_EF_SCAN_START_V1_8822C << BIT_SHIFT_EF_SCAN_START_V1_8822C)
+#define BIT_CLEAR_EF_SCAN_START_V1_8822C(x) \
+ ((x) & (~BITS_EF_SCAN_START_V1_8822C))
+#define BIT_GET_EF_SCAN_START_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_EF_SCAN_START_V1_8822C) & \
+ BIT_MASK_EF_SCAN_START_V1_8822C)
+#define BIT_SET_EF_SCAN_START_V1_8822C(x, v) \
+ (BIT_CLEAR_EF_SCAN_START_V1_8822C(x) | BIT_EF_SCAN_START_V1_8822C(v))
+
+#define BIT_SHIFT_EF_SCAN_END_8822C 12
+#define BIT_MASK_EF_SCAN_END_8822C 0xf
+#define BIT_EF_SCAN_END_8822C(x) \
+ (((x) & BIT_MASK_EF_SCAN_END_8822C) << BIT_SHIFT_EF_SCAN_END_8822C)
+#define BITS_EF_SCAN_END_8822C \
+ (BIT_MASK_EF_SCAN_END_8822C << BIT_SHIFT_EF_SCAN_END_8822C)
+#define BIT_CLEAR_EF_SCAN_END_8822C(x) ((x) & (~BITS_EF_SCAN_END_8822C))
+#define BIT_GET_EF_SCAN_END_8822C(x) \
+ (((x) >> BIT_SHIFT_EF_SCAN_END_8822C) & BIT_MASK_EF_SCAN_END_8822C)
+#define BIT_SET_EF_SCAN_END_8822C(x, v) \
+ (BIT_CLEAR_EF_SCAN_END_8822C(x) | BIT_EF_SCAN_END_8822C(v))
+
+#define BIT_EF_PD_DIS_8822C BIT(11)
+
+#define BIT_SHIFT_EF_CELL_SEL_8822C 8
+#define BIT_MASK_EF_CELL_SEL_8822C 0x3
+#define BIT_EF_CELL_SEL_8822C(x) \
+ (((x) & BIT_MASK_EF_CELL_SEL_8822C) << BIT_SHIFT_EF_CELL_SEL_8822C)
+#define BITS_EF_CELL_SEL_8822C \
+ (BIT_MASK_EF_CELL_SEL_8822C << BIT_SHIFT_EF_CELL_SEL_8822C)
+#define BIT_CLEAR_EF_CELL_SEL_8822C(x) ((x) & (~BITS_EF_CELL_SEL_8822C))
+#define BIT_GET_EF_CELL_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_EF_CELL_SEL_8822C) & BIT_MASK_EF_CELL_SEL_8822C)
+#define BIT_SET_EF_CELL_SEL_8822C(x, v) \
+ (BIT_CLEAR_EF_CELL_SEL_8822C(x) | BIT_EF_CELL_SEL_8822C(v))
+
+#define BIT_EF_TRPT_8822C BIT(7)
+
+#define BIT_SHIFT_EF_TTHD_8822C 0
+#define BIT_MASK_EF_TTHD_8822C 0x7f
+#define BIT_EF_TTHD_8822C(x) \
+ (((x) & BIT_MASK_EF_TTHD_8822C) << BIT_SHIFT_EF_TTHD_8822C)
+#define BITS_EF_TTHD_8822C (BIT_MASK_EF_TTHD_8822C << BIT_SHIFT_EF_TTHD_8822C)
+#define BIT_CLEAR_EF_TTHD_8822C(x) ((x) & (~BITS_EF_TTHD_8822C))
+#define BIT_GET_EF_TTHD_8822C(x) \
+ (((x) >> BIT_SHIFT_EF_TTHD_8822C) & BIT_MASK_EF_TTHD_8822C)
+#define BIT_SET_EF_TTHD_8822C(x, v) \
+ (BIT_CLEAR_EF_TTHD_8822C(x) | BIT_EF_TTHD_8822C(v))
+
+/* 2 REG_PWR_OPTION_CTRL_8822C */
+
+#define BIT_SHIFT_DBG_SEL_V1_8822C 16
+#define BIT_MASK_DBG_SEL_V1_8822C 0xff
+#define BIT_DBG_SEL_V1_8822C(x) \
+ (((x) & BIT_MASK_DBG_SEL_V1_8822C) << BIT_SHIFT_DBG_SEL_V1_8822C)
+#define BITS_DBG_SEL_V1_8822C \
+ (BIT_MASK_DBG_SEL_V1_8822C << BIT_SHIFT_DBG_SEL_V1_8822C)
+#define BIT_CLEAR_DBG_SEL_V1_8822C(x) ((x) & (~BITS_DBG_SEL_V1_8822C))
+#define BIT_GET_DBG_SEL_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_DBG_SEL_V1_8822C) & BIT_MASK_DBG_SEL_V1_8822C)
+#define BIT_SET_DBG_SEL_V1_8822C(x, v) \
+ (BIT_CLEAR_DBG_SEL_V1_8822C(x) | BIT_DBG_SEL_V1_8822C(v))
+
+#define BIT_SHIFT_DBG_SEL_BYTE_8822C 14
+#define BIT_MASK_DBG_SEL_BYTE_8822C 0x3
+#define BIT_DBG_SEL_BYTE_8822C(x) \
+ (((x) & BIT_MASK_DBG_SEL_BYTE_8822C) << BIT_SHIFT_DBG_SEL_BYTE_8822C)
+#define BITS_DBG_SEL_BYTE_8822C \
+ (BIT_MASK_DBG_SEL_BYTE_8822C << BIT_SHIFT_DBG_SEL_BYTE_8822C)
+#define BIT_CLEAR_DBG_SEL_BYTE_8822C(x) ((x) & (~BITS_DBG_SEL_BYTE_8822C))
+#define BIT_GET_DBG_SEL_BYTE_8822C(x) \
+ (((x) >> BIT_SHIFT_DBG_SEL_BYTE_8822C) & BIT_MASK_DBG_SEL_BYTE_8822C)
+#define BIT_SET_DBG_SEL_BYTE_8822C(x, v) \
+ (BIT_CLEAR_DBG_SEL_BYTE_8822C(x) | BIT_DBG_SEL_BYTE_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_SYSON_DBG_PAD_E2_8822C BIT(11)
+#define BIT_SYSON_LED_PAD_E2_8822C BIT(10)
+#define BIT_SYSON_GPEE_PAD_E2_8822C BIT(9)
+#define BIT_SYSON_PCI_PAD_E2_8822C BIT(8)
+#define BIT_AUTO_SW_LDO_VOL_EN_8822C BIT(7)
+
+#define BIT_SHIFT_SYSON_SPS0WWV_WT_8822C 4
+#define BIT_MASK_SYSON_SPS0WWV_WT_8822C 0x3
+#define BIT_SYSON_SPS0WWV_WT_8822C(x) \
+ (((x) & BIT_MASK_SYSON_SPS0WWV_WT_8822C) \
+ << BIT_SHIFT_SYSON_SPS0WWV_WT_8822C)
+#define BITS_SYSON_SPS0WWV_WT_8822C \
+ (BIT_MASK_SYSON_SPS0WWV_WT_8822C << BIT_SHIFT_SYSON_SPS0WWV_WT_8822C)
+#define BIT_CLEAR_SYSON_SPS0WWV_WT_8822C(x) \
+ ((x) & (~BITS_SYSON_SPS0WWV_WT_8822C))
+#define BIT_GET_SYSON_SPS0WWV_WT_8822C(x) \
+ (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8822C) & \
+ BIT_MASK_SYSON_SPS0WWV_WT_8822C)
+#define BIT_SET_SYSON_SPS0WWV_WT_8822C(x, v) \
+ (BIT_CLEAR_SYSON_SPS0WWV_WT_8822C(x) | BIT_SYSON_SPS0WWV_WT_8822C(v))
+
+#define BIT_SHIFT_SYSON_SPS0LDO_WT_8822C 2
+#define BIT_MASK_SYSON_SPS0LDO_WT_8822C 0x3
+#define BIT_SYSON_SPS0LDO_WT_8822C(x) \
+ (((x) & BIT_MASK_SYSON_SPS0LDO_WT_8822C) \
+ << BIT_SHIFT_SYSON_SPS0LDO_WT_8822C)
+#define BITS_SYSON_SPS0LDO_WT_8822C \
+ (BIT_MASK_SYSON_SPS0LDO_WT_8822C << BIT_SHIFT_SYSON_SPS0LDO_WT_8822C)
+#define BIT_CLEAR_SYSON_SPS0LDO_WT_8822C(x) \
+ ((x) & (~BITS_SYSON_SPS0LDO_WT_8822C))
+#define BIT_GET_SYSON_SPS0LDO_WT_8822C(x) \
+ (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8822C) & \
+ BIT_MASK_SYSON_SPS0LDO_WT_8822C)
+#define BIT_SET_SYSON_SPS0LDO_WT_8822C(x, v) \
+ (BIT_CLEAR_SYSON_SPS0LDO_WT_8822C(x) | BIT_SYSON_SPS0LDO_WT_8822C(v))
+
+#define BIT_SHIFT_SYSON_RCLK_SCALE_8822C 0
+#define BIT_MASK_SYSON_RCLK_SCALE_8822C 0x3
+#define BIT_SYSON_RCLK_SCALE_8822C(x) \
+ (((x) & BIT_MASK_SYSON_RCLK_SCALE_8822C) \
+ << BIT_SHIFT_SYSON_RCLK_SCALE_8822C)
+#define BITS_SYSON_RCLK_SCALE_8822C \
+ (BIT_MASK_SYSON_RCLK_SCALE_8822C << BIT_SHIFT_SYSON_RCLK_SCALE_8822C)
+#define BIT_CLEAR_SYSON_RCLK_SCALE_8822C(x) \
+ ((x) & (~BITS_SYSON_RCLK_SCALE_8822C))
+#define BIT_GET_SYSON_RCLK_SCALE_8822C(x) \
+ (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8822C) & \
+ BIT_MASK_SYSON_RCLK_SCALE_8822C)
+#define BIT_SET_SYSON_RCLK_SCALE_8822C(x, v) \
+ (BIT_CLEAR_SYSON_RCLK_SCALE_8822C(x) | BIT_SYSON_RCLK_SCALE_8822C(v))
+
+/* 2 REG_CAL_TIMER_8822C */
+
+#define BIT_SHIFT_MATCH_CNT_8822C 8
+#define BIT_MASK_MATCH_CNT_8822C 0xff
+#define BIT_MATCH_CNT_8822C(x) \
+ (((x) & BIT_MASK_MATCH_CNT_8822C) << BIT_SHIFT_MATCH_CNT_8822C)
+#define BITS_MATCH_CNT_8822C \
+ (BIT_MASK_MATCH_CNT_8822C << BIT_SHIFT_MATCH_CNT_8822C)
+#define BIT_CLEAR_MATCH_CNT_8822C(x) ((x) & (~BITS_MATCH_CNT_8822C))
+#define BIT_GET_MATCH_CNT_8822C(x) \
+ (((x) >> BIT_SHIFT_MATCH_CNT_8822C) & BIT_MASK_MATCH_CNT_8822C)
+#define BIT_SET_MATCH_CNT_8822C(x, v) \
+ (BIT_CLEAR_MATCH_CNT_8822C(x) | BIT_MATCH_CNT_8822C(v))
+
+#define BIT_SHIFT_CAL_SCAL_8822C 0
+#define BIT_MASK_CAL_SCAL_8822C 0xff
+#define BIT_CAL_SCAL_8822C(x) \
+ (((x) & BIT_MASK_CAL_SCAL_8822C) << BIT_SHIFT_CAL_SCAL_8822C)
+#define BITS_CAL_SCAL_8822C \
+ (BIT_MASK_CAL_SCAL_8822C << BIT_SHIFT_CAL_SCAL_8822C)
+#define BIT_CLEAR_CAL_SCAL_8822C(x) ((x) & (~BITS_CAL_SCAL_8822C))
+#define BIT_GET_CAL_SCAL_8822C(x) \
+ (((x) >> BIT_SHIFT_CAL_SCAL_8822C) & BIT_MASK_CAL_SCAL_8822C)
+#define BIT_SET_CAL_SCAL_8822C(x, v) \
+ (BIT_CLEAR_CAL_SCAL_8822C(x) | BIT_CAL_SCAL_8822C(v))
+
+/* 2 REG_ACLK_MON_8822C */
+
+#define BIT_SHIFT_RCLK_MON_8822C 5
+#define BIT_MASK_RCLK_MON_8822C 0x7ff
+#define BIT_RCLK_MON_8822C(x) \
+ (((x) & BIT_MASK_RCLK_MON_8822C) << BIT_SHIFT_RCLK_MON_8822C)
+#define BITS_RCLK_MON_8822C \
+ (BIT_MASK_RCLK_MON_8822C << BIT_SHIFT_RCLK_MON_8822C)
+#define BIT_CLEAR_RCLK_MON_8822C(x) ((x) & (~BITS_RCLK_MON_8822C))
+#define BIT_GET_RCLK_MON_8822C(x) \
+ (((x) >> BIT_SHIFT_RCLK_MON_8822C) & BIT_MASK_RCLK_MON_8822C)
+#define BIT_SET_RCLK_MON_8822C(x, v) \
+ (BIT_CLEAR_RCLK_MON_8822C(x) | BIT_RCLK_MON_8822C(v))
+
+#define BIT_CAL_EN_8822C BIT(4)
+
+#define BIT_SHIFT_DPSTU_8822C 2
+#define BIT_MASK_DPSTU_8822C 0x3
+#define BIT_DPSTU_8822C(x) \
+ (((x) & BIT_MASK_DPSTU_8822C) << BIT_SHIFT_DPSTU_8822C)
+#define BITS_DPSTU_8822C (BIT_MASK_DPSTU_8822C << BIT_SHIFT_DPSTU_8822C)
+#define BIT_CLEAR_DPSTU_8822C(x) ((x) & (~BITS_DPSTU_8822C))
+#define BIT_GET_DPSTU_8822C(x) \
+ (((x) >> BIT_SHIFT_DPSTU_8822C) & BIT_MASK_DPSTU_8822C)
+#define BIT_SET_DPSTU_8822C(x, v) \
+ (BIT_CLEAR_DPSTU_8822C(x) | BIT_DPSTU_8822C(v))
+
+#define BIT_SUS_16X_8822C BIT(1)
+
+/* 2 REG_GPIO_MUXCFG_2_8822C */
+#define BIT_SOUT_GPIO8_8822C BIT(7)
+#define BIT_SOUT_GPIO5_8822C BIT(6)
+#define BIT_RFE_CTRL_5_GPIO14_V1_8822C BIT(5)
+#define BIT_RFE_CTRL_10_GPIO13_V1_8822C BIT(4)
+#define BIT_RFE_CTRL_11_GPIO4_V1_8822C BIT(3)
+#define BIT_RFE_CTRL_5_GPIO14_8822C BIT(2)
+#define BIT_RFE_CTRL_10_GPIO13_8822C BIT(1)
+#define BIT_RFE_CTRL_11_GPIO4_8822C BIT(0)
+
+/* 2 REG_GPIO_MUXCFG_8822C */
+#define BIT_RFE_CTRL_3_GPIO12_8822C BIT(31)
+#define BIT_BT_RFE_CTRL_5_GPIO12_8822C BIT(30)
+#define BIT_S0_TRSW_GPIO12_8822C BIT(29)
+#define BIT_RFE_CTRL_9_GPIO13_8822C BIT(28)
+#define BIT_RFE_CTRL_9_GPIO12_8822C BIT(27)
+#define BIT_RFE_CTRL_8_GPIO4_8822C BIT(26)
+#define BIT_BT_RFE_CTRL_1_GPIO13_8822C BIT(25)
+#define BIT_BT_RFE_CTRL_1_GPIO12_8822C BIT(24)
+#define BIT_BT_RFE_CTRL_0_GPIO4_8822C BIT(23)
+#define BIT_ANTSW_GPIO13_8822C BIT(22)
+#define BIT_ANTSW_GPIO12_8822C BIT(21)
+#define BIT_ANTSWB_GPIO4_8822C BIT(20)
+#define BIT_FSPI_EN_8822C BIT(19)
+#define BIT_WL_RTS_EXT_32K_SEL_8822C BIT(18)
+#define BIT_WLBT_DPDT_SEL_EN_8822C BIT(17)
+#define BIT_WLBT_LNAON_SEL_EN_8822C BIT(16)
+#define BIT_SIC_LBK_8822C BIT(15)
+#define BIT_ENHTP_8822C BIT(14)
+#define BIT_BT_AOD_GPIO3_8822C BIT(13)
+#define BIT_ENSIC_8822C BIT(12)
+#define BIT_SIC_SWRST_8822C BIT(11)
+#define BIT_PO_WIFI_PTA_PINS_8822C BIT(10)
+#define BIT_PO_BT_PTA_PINS_8822C BIT(9)
+#define BIT_ENUART_8822C BIT(8)
+
+#define BIT_SHIFT_BTMODE_8822C 6
+#define BIT_MASK_BTMODE_8822C 0x3
+#define BIT_BTMODE_8822C(x) \
+ (((x) & BIT_MASK_BTMODE_8822C) << BIT_SHIFT_BTMODE_8822C)
+#define BITS_BTMODE_8822C (BIT_MASK_BTMODE_8822C << BIT_SHIFT_BTMODE_8822C)
+#define BIT_CLEAR_BTMODE_8822C(x) ((x) & (~BITS_BTMODE_8822C))
+#define BIT_GET_BTMODE_8822C(x) \
+ (((x) >> BIT_SHIFT_BTMODE_8822C) & BIT_MASK_BTMODE_8822C)
+#define BIT_SET_BTMODE_8822C(x, v) \
+ (BIT_CLEAR_BTMODE_8822C(x) | BIT_BTMODE_8822C(v))
+
+#define BIT_ENBT_8822C BIT(5)
+#define BIT_EROM_EN_8822C BIT(4)
+#define BIT_WLRFE_6_7_EN_8822C BIT(3)
+#define BIT_WLRFE_4_5_EN_8822C BIT(2)
+
+#define BIT_SHIFT_GPIOSEL_8822C 0
+#define BIT_MASK_GPIOSEL_8822C 0x3
+#define BIT_GPIOSEL_8822C(x) \
+ (((x) & BIT_MASK_GPIOSEL_8822C) << BIT_SHIFT_GPIOSEL_8822C)
+#define BITS_GPIOSEL_8822C (BIT_MASK_GPIOSEL_8822C << BIT_SHIFT_GPIOSEL_8822C)
+#define BIT_CLEAR_GPIOSEL_8822C(x) ((x) & (~BITS_GPIOSEL_8822C))
+#define BIT_GET_GPIOSEL_8822C(x) \
+ (((x) >> BIT_SHIFT_GPIOSEL_8822C) & BIT_MASK_GPIOSEL_8822C)
+#define BIT_SET_GPIOSEL_8822C(x, v) \
+ (BIT_CLEAR_GPIOSEL_8822C(x) | BIT_GPIOSEL_8822C(v))
+
+/* 2 REG_GPIO_PIN_CTRL_8822C */
+
+#define BIT_SHIFT_GPIO_MOD_7_TO_0_8822C 24
+#define BIT_MASK_GPIO_MOD_7_TO_0_8822C 0xff
+#define BIT_GPIO_MOD_7_TO_0_8822C(x) \
+ (((x) & BIT_MASK_GPIO_MOD_7_TO_0_8822C) \
+ << BIT_SHIFT_GPIO_MOD_7_TO_0_8822C)
+#define BITS_GPIO_MOD_7_TO_0_8822C \
+ (BIT_MASK_GPIO_MOD_7_TO_0_8822C << BIT_SHIFT_GPIO_MOD_7_TO_0_8822C)
+#define BIT_CLEAR_GPIO_MOD_7_TO_0_8822C(x) ((x) & (~BITS_GPIO_MOD_7_TO_0_8822C))
+#define BIT_GET_GPIO_MOD_7_TO_0_8822C(x) \
+ (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8822C) & \
+ BIT_MASK_GPIO_MOD_7_TO_0_8822C)
+#define BIT_SET_GPIO_MOD_7_TO_0_8822C(x, v) \
+ (BIT_CLEAR_GPIO_MOD_7_TO_0_8822C(x) | BIT_GPIO_MOD_7_TO_0_8822C(v))
+
+#define BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822C 16
+#define BIT_MASK_GPIO_IO_SEL_7_TO_0_8822C 0xff
+#define BIT_GPIO_IO_SEL_7_TO_0_8822C(x) \
+ (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8822C) \
+ << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822C)
+#define BITS_GPIO_IO_SEL_7_TO_0_8822C \
+ (BIT_MASK_GPIO_IO_SEL_7_TO_0_8822C \
+ << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822C)
+#define BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8822C(x) \
+ ((x) & (~BITS_GPIO_IO_SEL_7_TO_0_8822C))
+#define BIT_GET_GPIO_IO_SEL_7_TO_0_8822C(x) \
+ (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8822C) & \
+ BIT_MASK_GPIO_IO_SEL_7_TO_0_8822C)
+#define BIT_SET_GPIO_IO_SEL_7_TO_0_8822C(x, v) \
+ (BIT_CLEAR_GPIO_IO_SEL_7_TO_0_8822C(x) | \
+ BIT_GPIO_IO_SEL_7_TO_0_8822C(v))
+
+#define BIT_SHIFT_GPIO_OUT_7_TO_0_8822C 8
+#define BIT_MASK_GPIO_OUT_7_TO_0_8822C 0xff
+#define BIT_GPIO_OUT_7_TO_0_8822C(x) \
+ (((x) & BIT_MASK_GPIO_OUT_7_TO_0_8822C) \
+ << BIT_SHIFT_GPIO_OUT_7_TO_0_8822C)
+#define BITS_GPIO_OUT_7_TO_0_8822C \
+ (BIT_MASK_GPIO_OUT_7_TO_0_8822C << BIT_SHIFT_GPIO_OUT_7_TO_0_8822C)
+#define BIT_CLEAR_GPIO_OUT_7_TO_0_8822C(x) ((x) & (~BITS_GPIO_OUT_7_TO_0_8822C))
+#define BIT_GET_GPIO_OUT_7_TO_0_8822C(x) \
+ (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8822C) & \
+ BIT_MASK_GPIO_OUT_7_TO_0_8822C)
+#define BIT_SET_GPIO_OUT_7_TO_0_8822C(x, v) \
+ (BIT_CLEAR_GPIO_OUT_7_TO_0_8822C(x) | BIT_GPIO_OUT_7_TO_0_8822C(v))
+
+#define BIT_SHIFT_GPIO_IN_7_TO_0_8822C 0
+#define BIT_MASK_GPIO_IN_7_TO_0_8822C 0xff
+#define BIT_GPIO_IN_7_TO_0_8822C(x) \
+ (((x) & BIT_MASK_GPIO_IN_7_TO_0_8822C) \
+ << BIT_SHIFT_GPIO_IN_7_TO_0_8822C)
+#define BITS_GPIO_IN_7_TO_0_8822C \
+ (BIT_MASK_GPIO_IN_7_TO_0_8822C << BIT_SHIFT_GPIO_IN_7_TO_0_8822C)
+#define BIT_CLEAR_GPIO_IN_7_TO_0_8822C(x) ((x) & (~BITS_GPIO_IN_7_TO_0_8822C))
+#define BIT_GET_GPIO_IN_7_TO_0_8822C(x) \
+ (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8822C) & \
+ BIT_MASK_GPIO_IN_7_TO_0_8822C)
+#define BIT_SET_GPIO_IN_7_TO_0_8822C(x, v) \
+ (BIT_CLEAR_GPIO_IN_7_TO_0_8822C(x) | BIT_GPIO_IN_7_TO_0_8822C(v))
+
+/* 2 REG_GPIO_INTM_8822C */
+
+#define BIT_SHIFT_MUXDBG_SEL_8822C 30
+#define BIT_MASK_MUXDBG_SEL_8822C 0x3
+#define BIT_MUXDBG_SEL_8822C(x) \
+ (((x) & BIT_MASK_MUXDBG_SEL_8822C) << BIT_SHIFT_MUXDBG_SEL_8822C)
+#define BITS_MUXDBG_SEL_8822C \
+ (BIT_MASK_MUXDBG_SEL_8822C << BIT_SHIFT_MUXDBG_SEL_8822C)
+#define BIT_CLEAR_MUXDBG_SEL_8822C(x) ((x) & (~BITS_MUXDBG_SEL_8822C))
+#define BIT_GET_MUXDBG_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_MUXDBG_SEL_8822C) & BIT_MASK_MUXDBG_SEL_8822C)
+#define BIT_SET_MUXDBG_SEL_8822C(x, v) \
+ (BIT_CLEAR_MUXDBG_SEL_8822C(x) | BIT_MUXDBG_SEL_8822C(v))
+
+#define BIT_EXTWOL_SEL_8822C BIT(17)
+#define BIT_EXTWOL_EN_8822C BIT(16)
+#define BIT_GPIOF_INT_MD_8822C BIT(15)
+#define BIT_GPIOE_INT_MD_8822C BIT(14)
+#define BIT_GPIOD_INT_MD_8822C BIT(13)
+#define BIT_GPIOF_INT_MD_8822C BIT(15)
+#define BIT_GPIOE_INT_MD_8822C BIT(14)
+#define BIT_GPIOD_INT_MD_8822C BIT(13)
+#define BIT_GPIOC_INT_MD_8822C BIT(12)
+#define BIT_GPIOB_INT_MD_8822C BIT(11)
+#define BIT_GPIOA_INT_MD_8822C BIT(10)
+#define BIT_GPIO9_INT_MD_8822C BIT(9)
+#define BIT_GPIO8_INT_MD_8822C BIT(8)
+#define BIT_GPIO7_INT_MD_8822C BIT(7)
+#define BIT_GPIO6_INT_MD_8822C BIT(6)
+#define BIT_GPIO5_INT_MD_8822C BIT(5)
+#define BIT_GPIO4_INT_MD_8822C BIT(4)
+#define BIT_GPIO3_INT_MD_8822C BIT(3)
+#define BIT_GPIO2_INT_MD_8822C BIT(2)
+#define BIT_GPIO1_INT_MD_8822C BIT(1)
+#define BIT_GPIO0_INT_MD_8822C BIT(0)
+
+/* 2 REG_LED_CFG_8822C */
+#define BIT_MAILBOX_1WIRE_GPIO_CFG_8822C BIT(31)
+#define BIT_BT_RF_GPIO_CFG_8822C BIT(30)
+#define BIT_BT_SDIO_INT_GPIO_CFG_8822C BIT(29)
+#define BIT_MAILBOX_3WIRE_GPIO_CFG_8822C BIT(28)
+#define BIT_WLBT_PAPE_SEL_EN_8822C BIT(27)
+#define BIT_LNAON_SEL_EN_8822C BIT(26)
+#define BIT_PAPE_SEL_EN_8822C BIT(25)
+#define BIT_DPDT_WLBT_SEL_8822C BIT(24)
+#define BIT_DPDT_SEL_EN_8822C BIT(23)
+#define BIT_GPIO13_14_WL_CTRL_EN_8822C BIT(22)
+#define BIT_LED2DIS_8822C BIT(21)
+#define BIT_LED2PL_8822C BIT(20)
+#define BIT_LED2SV_8822C BIT(19)
+
+#define BIT_SHIFT_LED2CM_8822C 16
+#define BIT_MASK_LED2CM_8822C 0x7
+#define BIT_LED2CM_8822C(x) \
+ (((x) & BIT_MASK_LED2CM_8822C) << BIT_SHIFT_LED2CM_8822C)
+#define BITS_LED2CM_8822C (BIT_MASK_LED2CM_8822C << BIT_SHIFT_LED2CM_8822C)
+#define BIT_CLEAR_LED2CM_8822C(x) ((x) & (~BITS_LED2CM_8822C))
+#define BIT_GET_LED2CM_8822C(x) \
+ (((x) >> BIT_SHIFT_LED2CM_8822C) & BIT_MASK_LED2CM_8822C)
+#define BIT_SET_LED2CM_8822C(x, v) \
+ (BIT_CLEAR_LED2CM_8822C(x) | BIT_LED2CM_8822C(v))
+
+#define BIT_LED1DIS_8822C BIT(15)
+#define BIT_LED1PL_8822C BIT(12)
+#define BIT_LED1SV_8822C BIT(11)
+
+#define BIT_SHIFT_LED1CM_8822C 8
+#define BIT_MASK_LED1CM_8822C 0x7
+#define BIT_LED1CM_8822C(x) \
+ (((x) & BIT_MASK_LED1CM_8822C) << BIT_SHIFT_LED1CM_8822C)
+#define BITS_LED1CM_8822C (BIT_MASK_LED1CM_8822C << BIT_SHIFT_LED1CM_8822C)
+#define BIT_CLEAR_LED1CM_8822C(x) ((x) & (~BITS_LED1CM_8822C))
+#define BIT_GET_LED1CM_8822C(x) \
+ (((x) >> BIT_SHIFT_LED1CM_8822C) & BIT_MASK_LED1CM_8822C)
+#define BIT_SET_LED1CM_8822C(x, v) \
+ (BIT_CLEAR_LED1CM_8822C(x) | BIT_LED1CM_8822C(v))
+
+#define BIT_LED0DIS_8822C BIT(7)
+
+#define BIT_SHIFT_AFE_LDO_SWR_CHECK_8822C 5
+#define BIT_MASK_AFE_LDO_SWR_CHECK_8822C 0x3
+#define BIT_AFE_LDO_SWR_CHECK_8822C(x) \
+ (((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8822C) \
+ << BIT_SHIFT_AFE_LDO_SWR_CHECK_8822C)
+#define BITS_AFE_LDO_SWR_CHECK_8822C \
+ (BIT_MASK_AFE_LDO_SWR_CHECK_8822C << BIT_SHIFT_AFE_LDO_SWR_CHECK_8822C)
+#define BIT_CLEAR_AFE_LDO_SWR_CHECK_8822C(x) \
+ ((x) & (~BITS_AFE_LDO_SWR_CHECK_8822C))
+#define BIT_GET_AFE_LDO_SWR_CHECK_8822C(x) \
+ (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8822C) & \
+ BIT_MASK_AFE_LDO_SWR_CHECK_8822C)
+#define BIT_SET_AFE_LDO_SWR_CHECK_8822C(x, v) \
+ (BIT_CLEAR_AFE_LDO_SWR_CHECK_8822C(x) | BIT_AFE_LDO_SWR_CHECK_8822C(v))
+
+#define BIT_LED0PL_8822C BIT(4)
+#define BIT_LED0SV_8822C BIT(3)
+
+#define BIT_SHIFT_LED0CM_8822C 0
+#define BIT_MASK_LED0CM_8822C 0x7
+#define BIT_LED0CM_8822C(x) \
+ (((x) & BIT_MASK_LED0CM_8822C) << BIT_SHIFT_LED0CM_8822C)
+#define BITS_LED0CM_8822C (BIT_MASK_LED0CM_8822C << BIT_SHIFT_LED0CM_8822C)
+#define BIT_CLEAR_LED0CM_8822C(x) ((x) & (~BITS_LED0CM_8822C))
+#define BIT_GET_LED0CM_8822C(x) \
+ (((x) >> BIT_SHIFT_LED0CM_8822C) & BIT_MASK_LED0CM_8822C)
+#define BIT_SET_LED0CM_8822C(x, v) \
+ (BIT_CLEAR_LED0CM_8822C(x) | BIT_LED0CM_8822C(v))
+
+/* 2 REG_FSIMR_8822C */
+#define BIT_FS_PDNINT_EN_8822C BIT(31)
+#define BIT_FS_SPS_OCP_INT_EN_8822C BIT(29)
+#define BIT_FS_PWMERR_INT_EN_8822C BIT(28)
+#define BIT_FS_GPIOF_INT_EN_8822C BIT(27)
+#define BIT_FS_GPIOE_INT_EN_8822C BIT(26)
+#define BIT_FS_GPIOD_INT_EN_8822C BIT(25)
+#define BIT_FS_GPIOC_INT_EN_8822C BIT(24)
+#define BIT_FS_GPIOB_INT_EN_8822C BIT(23)
+#define BIT_FS_GPIOA_INT_EN_8822C BIT(22)
+#define BIT_FS_GPIO9_INT_EN_8822C BIT(21)
+#define BIT_FS_GPIO8_INT_EN_8822C BIT(20)
+#define BIT_FS_GPIO7_INT_EN_8822C BIT(19)
+#define BIT_FS_GPIO6_INT_EN_8822C BIT(18)
+#define BIT_FS_GPIO5_INT_EN_8822C BIT(17)
+#define BIT_FS_GPIO4_INT_EN_8822C BIT(16)
+#define BIT_FS_GPIO3_INT_EN_8822C BIT(15)
+#define BIT_FS_GPIO2_INT_EN_8822C BIT(14)
+#define BIT_FS_GPIO1_INT_EN_8822C BIT(13)
+#define BIT_FS_GPIO0_INT_EN_8822C BIT(12)
+#define BIT_FS_HCI_SUS_EN_8822C BIT(11)
+#define BIT_FS_HCI_RES_EN_8822C BIT(10)
+#define BIT_FS_HCI_RESET_EN_8822C BIT(9)
+#define BIT_USB_SCSI_CMD_EN_8822C BIT(8)
+#define BIT_FS_BTON_STS_UPDATE_MSK_EN_8822C BIT(7)
+#define BIT_ACT2RECOVERY_INT_EN_V1_8822C BIT(6)
+#define BIT_GEN1GEN2_SWITCH_8822C BIT(5)
+#define BIT_HCI_TXDMA_REQ_HIMR_8822C BIT(4)
+#define BIT_FS_32K_LEAVE_SETTING_MAK_8822C BIT(3)
+#define BIT_FS_32K_ENTER_SETTING_MAK_8822C BIT(2)
+#define BIT_FS_USB_LPMRSM_MSK_8822C BIT(1)
+#define BIT_FS_USB_LPMINT_MSK_8822C BIT(0)
+
+/* 2 REG_FSISR_8822C */
+#define BIT_FS_PDNINT_8822C BIT(31)
+#define BIT_FS_SPS_OCP_INT_8822C BIT(29)
+#define BIT_FS_PWMERR_INT_8822C BIT(28)
+#define BIT_FS_GPIOF_INT_8822C BIT(27)
+#define BIT_FS_GPIOE_INT_8822C BIT(26)
+#define BIT_FS_GPIOD_INT_8822C BIT(25)
+#define BIT_FS_GPIOC_INT_8822C BIT(24)
+#define BIT_FS_GPIOB_INT_8822C BIT(23)
+#define BIT_FS_GPIOA_INT_8822C BIT(22)
+#define BIT_FS_GPIO9_INT_8822C BIT(21)
+#define BIT_FS_GPIO8_INT_8822C BIT(20)
+#define BIT_FS_GPIO7_INT_8822C BIT(19)
+#define BIT_FS_GPIO6_INT_8822C BIT(18)
+#define BIT_FS_GPIO5_INT_8822C BIT(17)
+#define BIT_FS_GPIO4_INT_8822C BIT(16)
+#define BIT_FS_GPIO3_INT_8822C BIT(15)
+#define BIT_FS_GPIO2_INT_8822C BIT(14)
+#define BIT_FS_GPIO1_INT_8822C BIT(13)
+#define BIT_FS_GPIO0_INT_8822C BIT(12)
+#define BIT_FS_HCI_SUS_INT_8822C BIT(11)
+#define BIT_FS_HCI_RES_INT_8822C BIT(10)
+#define BIT_FS_HCI_RESET_INT_8822C BIT(9)
+#define BIT_USB_SCSI_CMD_INT_8822C BIT(8)
+#define BIT_ACT2RECOVERY_8822C BIT(6)
+#define BIT_GEN1GEN2_SWITCH_8822C BIT(5)
+#define BIT_HCI_TXDMA_REQ_HISR_8822C BIT(4)
+#define BIT_FS_32K_LEAVE_SETTING_INT_8822C BIT(3)
+#define BIT_FS_32K_ENTER_SETTING_INT_8822C BIT(2)
+#define BIT_FS_USB_LPMRSM_INT_8822C BIT(1)
+#define BIT_FS_USB_LPMINT_INT_8822C BIT(0)
+
+/* 2 REG_HSIMR_8822C */
+#define BIT_GPIOF_INT_EN_8822C BIT(31)
+#define BIT_GPIOE_INT_EN_8822C BIT(30)
+#define BIT_GPIOD_INT_EN_8822C BIT(29)
+#define BIT_GPIOC_INT_EN_8822C BIT(28)
+#define BIT_GPIOB_INT_EN_8822C BIT(27)
+#define BIT_GPIOA_INT_EN_8822C BIT(26)
+#define BIT_GPIO9_INT_EN_8822C BIT(25)
+#define BIT_GPIO8_INT_EN_8822C BIT(24)
+#define BIT_GPIO7_INT_EN_8822C BIT(23)
+#define BIT_GPIO6_INT_EN_8822C BIT(22)
+#define BIT_GPIO5_INT_EN_8822C BIT(21)
+#define BIT_GPIO4_INT_EN_8822C BIT(20)
+#define BIT_GPIO3_INT_EN_8822C BIT(19)
+#define BIT_GPIO2_INT_EN_V1_8822C BIT(18)
+#define BIT_GPIO1_INT_EN_8822C BIT(17)
+#define BIT_GPIO0_INT_EN_8822C BIT(16)
+#define BIT_PDNINT_EN_8822C BIT(7)
+#define BIT_RON_INT_EN_8822C BIT(6)
+#define BIT_SPS_OCP_INT_EN_8822C BIT(5)
+#define BIT_GPIO15_0_INT_EN_8822C BIT(0)
+
+/* 2 REG_HSISR_8822C */
+#define BIT_GPIOF_INT_8822C BIT(31)
+#define BIT_GPIOE_INT_8822C BIT(30)
+#define BIT_GPIOD_INT_8822C BIT(29)
+#define BIT_GPIOC_INT_8822C BIT(28)
+#define BIT_GPIOB_INT_8822C BIT(27)
+#define BIT_GPIOA_INT_8822C BIT(26)
+#define BIT_GPIO9_INT_8822C BIT(25)
+#define BIT_GPIO8_INT_8822C BIT(24)
+#define BIT_GPIO7_INT_8822C BIT(23)
+#define BIT_GPIO6_INT_8822C BIT(22)
+#define BIT_GPIO5_INT_8822C BIT(21)
+#define BIT_GPIO4_INT_8822C BIT(20)
+#define BIT_GPIO3_INT_8822C BIT(19)
+#define BIT_GPIO2_INT_V1_8822C BIT(18)
+#define BIT_GPIO1_INT_8822C BIT(17)
+#define BIT_GPIO0_INT_8822C BIT(16)
+#define BIT_PDNINT_8822C BIT(7)
+#define BIT_RON_INT_8822C BIT(6)
+#define BIT_SPS_OCP_INT_8822C BIT(5)
+#define BIT_GPIO15_0_INT_8822C BIT(0)
+
+/* 2 REG_GPIO_EXT_CTRL_8822C */
+
+#define BIT_SHIFT_GPIO_MOD_15_TO_8_8822C 24
+#define BIT_MASK_GPIO_MOD_15_TO_8_8822C 0xff
+#define BIT_GPIO_MOD_15_TO_8_8822C(x) \
+ (((x) & BIT_MASK_GPIO_MOD_15_TO_8_8822C) \
+ << BIT_SHIFT_GPIO_MOD_15_TO_8_8822C)
+#define BITS_GPIO_MOD_15_TO_8_8822C \
+ (BIT_MASK_GPIO_MOD_15_TO_8_8822C << BIT_SHIFT_GPIO_MOD_15_TO_8_8822C)
+#define BIT_CLEAR_GPIO_MOD_15_TO_8_8822C(x) \
+ ((x) & (~BITS_GPIO_MOD_15_TO_8_8822C))
+#define BIT_GET_GPIO_MOD_15_TO_8_8822C(x) \
+ (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8822C) & \
+ BIT_MASK_GPIO_MOD_15_TO_8_8822C)
+#define BIT_SET_GPIO_MOD_15_TO_8_8822C(x, v) \
+ (BIT_CLEAR_GPIO_MOD_15_TO_8_8822C(x) | BIT_GPIO_MOD_15_TO_8_8822C(v))
+
+#define BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822C 16
+#define BIT_MASK_GPIO_IO_SEL_15_TO_8_8822C 0xff
+#define BIT_GPIO_IO_SEL_15_TO_8_8822C(x) \
+ (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8822C) \
+ << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822C)
+#define BITS_GPIO_IO_SEL_15_TO_8_8822C \
+ (BIT_MASK_GPIO_IO_SEL_15_TO_8_8822C \
+ << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822C)
+#define BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8822C(x) \
+ ((x) & (~BITS_GPIO_IO_SEL_15_TO_8_8822C))
+#define BIT_GET_GPIO_IO_SEL_15_TO_8_8822C(x) \
+ (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8822C) & \
+ BIT_MASK_GPIO_IO_SEL_15_TO_8_8822C)
+#define BIT_SET_GPIO_IO_SEL_15_TO_8_8822C(x, v) \
+ (BIT_CLEAR_GPIO_IO_SEL_15_TO_8_8822C(x) | \
+ BIT_GPIO_IO_SEL_15_TO_8_8822C(v))
+
+#define BIT_SHIFT_GPIO_OUT_15_TO_8_8822C 8
+#define BIT_MASK_GPIO_OUT_15_TO_8_8822C 0xff
+#define BIT_GPIO_OUT_15_TO_8_8822C(x) \
+ (((x) & BIT_MASK_GPIO_OUT_15_TO_8_8822C) \
+ << BIT_SHIFT_GPIO_OUT_15_TO_8_8822C)
+#define BITS_GPIO_OUT_15_TO_8_8822C \
+ (BIT_MASK_GPIO_OUT_15_TO_8_8822C << BIT_SHIFT_GPIO_OUT_15_TO_8_8822C)
+#define BIT_CLEAR_GPIO_OUT_15_TO_8_8822C(x) \
+ ((x) & (~BITS_GPIO_OUT_15_TO_8_8822C))
+#define BIT_GET_GPIO_OUT_15_TO_8_8822C(x) \
+ (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8822C) & \
+ BIT_MASK_GPIO_OUT_15_TO_8_8822C)
+#define BIT_SET_GPIO_OUT_15_TO_8_8822C(x, v) \
+ (BIT_CLEAR_GPIO_OUT_15_TO_8_8822C(x) | BIT_GPIO_OUT_15_TO_8_8822C(v))
+
+#define BIT_SHIFT_GPIO_IN_15_TO_8_8822C 0
+#define BIT_MASK_GPIO_IN_15_TO_8_8822C 0xff
+#define BIT_GPIO_IN_15_TO_8_8822C(x) \
+ (((x) & BIT_MASK_GPIO_IN_15_TO_8_8822C) \
+ << BIT_SHIFT_GPIO_IN_15_TO_8_8822C)
+#define BITS_GPIO_IN_15_TO_8_8822C \
+ (BIT_MASK_GPIO_IN_15_TO_8_8822C << BIT_SHIFT_GPIO_IN_15_TO_8_8822C)
+#define BIT_CLEAR_GPIO_IN_15_TO_8_8822C(x) ((x) & (~BITS_GPIO_IN_15_TO_8_8822C))
+#define BIT_GET_GPIO_IN_15_TO_8_8822C(x) \
+ (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8822C) & \
+ BIT_MASK_GPIO_IN_15_TO_8_8822C)
+#define BIT_SET_GPIO_IN_15_TO_8_8822C(x, v) \
+ (BIT_CLEAR_GPIO_IN_15_TO_8_8822C(x) | BIT_GPIO_IN_15_TO_8_8822C(v))
+
+/* 2 REG_PAD_CTRL1_8822C */
+#define BIT_PAPE_WLBT_SEL_8822C BIT(29)
+#define BIT_LNAON_WLBT_SEL_8822C BIT(28)
+#define BIT_BT_BQB_GPIO_SEL_8822C BIT(27)
+#define BIT_BTGP_GPG3_FEN_8822C BIT(26)
+#define BIT_BTGP_GPG2_FEN_8822C BIT(25)
+#define BIT_BTGP_JTAG_EN_8822C BIT(24)
+#define BIT_XTAL_CLK_EXTARNAL_EN_8822C BIT(23)
+#define BIT_BTGP_UART0_EN_8822C BIT(22)
+#define BIT_BTGP_UART1_EN_8822C BIT(21)
+#define BIT_BTGP_SPI_EN_8822C BIT(20)
+#define BIT_BTGP_GPIO_E2_8822C BIT(19)
+#define BIT_BTGP_GPIO_EN_8822C BIT(18)
+
+#define BIT_SHIFT_BTGP_GPIO_SL_8822C 16
+#define BIT_MASK_BTGP_GPIO_SL_8822C 0x3
+#define BIT_BTGP_GPIO_SL_8822C(x) \
+ (((x) & BIT_MASK_BTGP_GPIO_SL_8822C) << BIT_SHIFT_BTGP_GPIO_SL_8822C)
+#define BITS_BTGP_GPIO_SL_8822C \
+ (BIT_MASK_BTGP_GPIO_SL_8822C << BIT_SHIFT_BTGP_GPIO_SL_8822C)
+#define BIT_CLEAR_BTGP_GPIO_SL_8822C(x) ((x) & (~BITS_BTGP_GPIO_SL_8822C))
+#define BIT_GET_BTGP_GPIO_SL_8822C(x) \
+ (((x) >> BIT_SHIFT_BTGP_GPIO_SL_8822C) & BIT_MASK_BTGP_GPIO_SL_8822C)
+#define BIT_SET_BTGP_GPIO_SL_8822C(x, v) \
+ (BIT_CLEAR_BTGP_GPIO_SL_8822C(x) | BIT_BTGP_GPIO_SL_8822C(v))
+
+#define BIT_PAD_SDIO_SR_8822C BIT(14)
+#define BIT_GPIO14_OUTPUT_PL_8822C BIT(13)
+#define BIT_HOST_WAKE_PAD_PULL_EN_8822C BIT(12)
+#define BIT_HOST_WAKE_PAD_SL_8822C BIT(11)
+#define BIT_PAD_LNAON_SR_8822C BIT(10)
+#define BIT_PAD_LNAON_E2_8822C BIT(9)
+#define BIT_SW_LNAON_G_SEL_DATA_8822C BIT(8)
+#define BIT_SW_LNAON_A_SEL_DATA_8822C BIT(7)
+#define BIT_PAD_PAPE_SR_8822C BIT(6)
+#define BIT_PAD_PAPE_E2_8822C BIT(5)
+#define BIT_SW_PAPE_G_SEL_DATA_8822C BIT(4)
+#define BIT_SW_PAPE_A_SEL_DATA_8822C BIT(3)
+#define BIT_PAD_DPDT_SR_8822C BIT(2)
+#define BIT_PAD_DPDT_PAD_E2_8822C BIT(1)
+#define BIT_SW_DPDT_SEL_DATA_8822C BIT(0)
+
+/* 2 REG_WL_BT_PWR_CTRL_8822C */
+#define BIT_ISO_BD2PP_8822C BIT(31)
+#define BIT_LDOV12B_EN_8822C BIT(30)
+#define BIT_CKEN_BTGPS_8822C BIT(29)
+#define BIT_FEN_BTGPS_8822C BIT(28)
+#define BIT_BTCPU_BOOTSEL_8822C BIT(27)
+#define BIT_SPI_SPEEDUP_8822C BIT(26)
+#define BIT_BT_LDO_MODE_8822C BIT(25)
+#define BIT_DEVWAKE_PAD_TYPE_SEL_8822C BIT(24)
+#define BIT_CLKREQ_PAD_TYPE_SEL_8822C BIT(23)
+#define BIT_ISO_BTPON2PP_8822C BIT(22)
+#define BIT_BT_HWROF_EN_8822C BIT(19)
+#define BIT_BT_FUNC_EN_8822C BIT(18)
+#define BIT_BT_HWPDN_SL_8822C BIT(17)
+#define BIT_BT_DISN_EN_8822C BIT(16)
+#define BIT_BT_PDN_PULL_EN_8822C BIT(15)
+#define BIT_WL_PDN_PULL_EN_8822C BIT(14)
+#define BIT_EXTERNAL_REQUEST_PL_8822C BIT(13)
+#define BIT_GPIO0_2_3_PULL_LOW_EN_8822C BIT(12)
+#define BIT_ISO_BA2PP_8822C BIT(11)
+#define BIT_BT_AFE_LDO_EN_8822C BIT(10)
+#define BIT_BT_AFE_PLL_EN_8822C BIT(9)
+#define BIT_BT_DIG_CLK_EN_8822C BIT(8)
+#define BIT_WLAN_32K_SEL_8822C BIT(6)
+#define BIT_WL_DRV_EXIST_IDX_8822C BIT(5)
+#define BIT_DOP_EHPAD_8822C BIT(4)
+#define BIT_WL_HWROF_EN_8822C BIT(3)
+#define BIT_WL_FUNC_EN_8822C BIT(2)
+#define BIT_WL_HWPDN_SL_8822C BIT(1)
+#define BIT_WL_HWPDN_EN_8822C BIT(0)
+
+/* 2 REG_SDM_DEBUG_8822C */
+#define BIT_GPIO_IE_V18_8822C BIT(10)
+#define BIT_PCIE_IE_V18_8822C BIT(9)
+#define BIT_UART_IE_V18_8822C BIT(8)
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_WLCLK_PHASE_8822C 0
+#define BIT_MASK_WLCLK_PHASE_8822C 0x1f
+#define BIT_WLCLK_PHASE_8822C(x) \
+ (((x) & BIT_MASK_WLCLK_PHASE_8822C) << BIT_SHIFT_WLCLK_PHASE_8822C)
+#define BITS_WLCLK_PHASE_8822C \
+ (BIT_MASK_WLCLK_PHASE_8822C << BIT_SHIFT_WLCLK_PHASE_8822C)
+#define BIT_CLEAR_WLCLK_PHASE_8822C(x) ((x) & (~BITS_WLCLK_PHASE_8822C))
+#define BIT_GET_WLCLK_PHASE_8822C(x) \
+ (((x) >> BIT_SHIFT_WLCLK_PHASE_8822C) & BIT_MASK_WLCLK_PHASE_8822C)
+#define BIT_SET_WLCLK_PHASE_8822C(x, v) \
+ (BIT_CLEAR_WLCLK_PHASE_8822C(x) | BIT_WLCLK_PHASE_8822C(v))
+
+/* 2 REG_SYS_SDIO_CTRL_8822C */
+#define BIT_DBG_GNT_WL_BT_8822C BIT(27)
+#define BIT_LTE_MUX_CTRL_PATH_8822C BIT(26)
+#define BIT_LTE_COEX_UART_8822C BIT(25)
+#define BIT_3W_LTE_WL_GPIO_8822C BIT(24)
+#define BIT_SDIO_INT_POLARITY_8822C BIT(19)
+#define BIT_SDIO_INT_8822C BIT(18)
+#define BIT_SDIO_OFF_EN_8822C BIT(17)
+#define BIT_SDIO_ON_EN_8822C BIT(16)
+#define BIT_PCIE_FORCE_PWR_NGAT_8822C BIT(13)
+#define BIT_PCIE_CALIB_EN_V1_8822C BIT(12)
+#define BIT_PAGE3_AUXCLK_GATE_8822C BIT(11)
+#define BIT_PCIE_WAIT_TIMEOUT_EVENT_8822C BIT(10)
+#define BIT_PCIE_WAIT_TIME_8822C BIT(9)
+#define BIT_MPCIE_REFCLK_XTAL_SEL_8822C BIT(8)
+#define BIT_BT_CTRL_USB_PWR_BACKDOOR_8822C BIT(5)
+#define BIT_USB_D_STATE_HOLD_8822C BIT(4)
+#define BIT_REG_FORCE_DP_8822C BIT(3)
+#define BIT_REG_DP_MODE_8822C BIT(2)
+#define BIT_RES_USB_MASS_STORAGE_DESC_8822C BIT(1)
+#define BIT_USB_WAIT_TIME_8822C BIT(0)
+
+/* 2 REG_HCI_OPT_CTRL_8822C */
+
+#define BIT_SHIFT_TSFT_SEL_8822C 29
+#define BIT_MASK_TSFT_SEL_8822C 0x7
+#define BIT_TSFT_SEL_8822C(x) \
+ (((x) & BIT_MASK_TSFT_SEL_8822C) << BIT_SHIFT_TSFT_SEL_8822C)
+#define BITS_TSFT_SEL_8822C \
+ (BIT_MASK_TSFT_SEL_8822C << BIT_SHIFT_TSFT_SEL_8822C)
+#define BIT_CLEAR_TSFT_SEL_8822C(x) ((x) & (~BITS_TSFT_SEL_8822C))
+#define BIT_GET_TSFT_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_TSFT_SEL_8822C) & BIT_MASK_TSFT_SEL_8822C)
+#define BIT_SET_TSFT_SEL_8822C(x, v) \
+ (BIT_CLEAR_TSFT_SEL_8822C(x) | BIT_TSFT_SEL_8822C(v))
+
+#define BIT_SDIO_PAD_E5_8822C BIT(18)
+#define BIT_USB_HOST_PWR_OFF_EN_8822C BIT(12)
+#define BIT_SYM_LPS_BLOCK_EN_8822C BIT(11)
+#define BIT_USB_LPM_ACT_EN_8822C BIT(10)
+#define BIT_USB_LPM_NY_8822C BIT(9)
+#define BIT_USB_SUS_DIS_8822C BIT(8)
+
+#define BIT_SHIFT_SDIO_PAD_E_8822C 5
+#define BIT_MASK_SDIO_PAD_E_8822C 0x7
+#define BIT_SDIO_PAD_E_8822C(x) \
+ (((x) & BIT_MASK_SDIO_PAD_E_8822C) << BIT_SHIFT_SDIO_PAD_E_8822C)
+#define BITS_SDIO_PAD_E_8822C \
+ (BIT_MASK_SDIO_PAD_E_8822C << BIT_SHIFT_SDIO_PAD_E_8822C)
+#define BIT_CLEAR_SDIO_PAD_E_8822C(x) ((x) & (~BITS_SDIO_PAD_E_8822C))
+#define BIT_GET_SDIO_PAD_E_8822C(x) \
+ (((x) >> BIT_SHIFT_SDIO_PAD_E_8822C) & BIT_MASK_SDIO_PAD_E_8822C)
+#define BIT_SET_SDIO_PAD_E_8822C(x, v) \
+ (BIT_CLEAR_SDIO_PAD_E_8822C(x) | BIT_SDIO_PAD_E_8822C(v))
+
+#define BIT_USB_LPPLL_EN_8822C BIT(4)
+#define BIT_USB1_1_USB2_0_DECISION_8822C BIT(3)
+#define BIT_ROP_SW15_8822C BIT(2)
+#define BIT_PCI_CKRDY_OPT_8822C BIT(1)
+#define BIT_PCI_VAUX_EN_8822C BIT(0)
+
+/* 2 REG_HCI_BG_CTRL_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_IBX_EN_VALUE_8822C BIT(9)
+#define BIT_IB_EN_VALUE_8822C BIT(8)
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_FORCED_IB_EN_8822C BIT(4)
+#define BIT_EN_REGBG_8822C BIT(3)
+#define BIT_REG_BG_LPF_8822C BIT(2)
+
+#define BIT_SHIFT_REG_BG_8822C 0
+#define BIT_MASK_REG_BG_8822C 0x3
+#define BIT_REG_BG_8822C(x) \
+ (((x) & BIT_MASK_REG_BG_8822C) << BIT_SHIFT_REG_BG_8822C)
+#define BITS_REG_BG_8822C (BIT_MASK_REG_BG_8822C << BIT_SHIFT_REG_BG_8822C)
+#define BIT_CLEAR_REG_BG_8822C(x) ((x) & (~BITS_REG_BG_8822C))
+#define BIT_GET_REG_BG_8822C(x) \
+ (((x) >> BIT_SHIFT_REG_BG_8822C) & BIT_MASK_REG_BG_8822C)
+#define BIT_SET_REG_BG_8822C(x, v) \
+ (BIT_CLEAR_REG_BG_8822C(x) | BIT_REG_BG_8822C(v))
+
+/* 2 REG_HCI_LDO_CTRL_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_EN_LW_PWR_8822C BIT(6)
+#define BIT_EN_REGU_8822C BIT(5)
+#define BIT_EN_PC_8822C BIT(4)
+
+#define BIT_SHIFT_REG_VADJ_8822C 0
+#define BIT_MASK_REG_VADJ_8822C 0xf
+#define BIT_REG_VADJ_8822C(x) \
+ (((x) & BIT_MASK_REG_VADJ_8822C) << BIT_SHIFT_REG_VADJ_8822C)
+#define BITS_REG_VADJ_8822C \
+ (BIT_MASK_REG_VADJ_8822C << BIT_SHIFT_REG_VADJ_8822C)
+#define BIT_CLEAR_REG_VADJ_8822C(x) ((x) & (~BITS_REG_VADJ_8822C))
+#define BIT_GET_REG_VADJ_8822C(x) \
+ (((x) >> BIT_SHIFT_REG_VADJ_8822C) & BIT_MASK_REG_VADJ_8822C)
+#define BIT_SET_REG_VADJ_8822C(x, v) \
+ (BIT_CLEAR_REG_VADJ_8822C(x) | BIT_REG_VADJ_8822C(v))
+
+/* 2 REG_LDO_SWR_CTRL_8822C */
+#define BIT_EXT_SWR_CTRL_EN_8822C BIT(31)
+#define BIT_ZCD_HW_AUTO_EN_8822C BIT(27)
+#define BIT_ZCD_REGSEL_8822C BIT(26)
+
+#define BIT_SHIFT_AUTO_ZCD_IN_CODE_8822C 21
+#define BIT_MASK_AUTO_ZCD_IN_CODE_8822C 0x1f
+#define BIT_AUTO_ZCD_IN_CODE_8822C(x) \
+ (((x) & BIT_MASK_AUTO_ZCD_IN_CODE_8822C) \
+ << BIT_SHIFT_AUTO_ZCD_IN_CODE_8822C)
+#define BITS_AUTO_ZCD_IN_CODE_8822C \
+ (BIT_MASK_AUTO_ZCD_IN_CODE_8822C << BIT_SHIFT_AUTO_ZCD_IN_CODE_8822C)
+#define BIT_CLEAR_AUTO_ZCD_IN_CODE_8822C(x) \
+ ((x) & (~BITS_AUTO_ZCD_IN_CODE_8822C))
+#define BIT_GET_AUTO_ZCD_IN_CODE_8822C(x) \
+ (((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE_8822C) & \
+ BIT_MASK_AUTO_ZCD_IN_CODE_8822C)
+#define BIT_SET_AUTO_ZCD_IN_CODE_8822C(x, v) \
+ (BIT_CLEAR_AUTO_ZCD_IN_CODE_8822C(x) | BIT_AUTO_ZCD_IN_CODE_8822C(v))
+
+#define BIT_SHIFT_ZCD_CODE_IN_L_8822C 16
+#define BIT_MASK_ZCD_CODE_IN_L_8822C 0x1f
+#define BIT_ZCD_CODE_IN_L_8822C(x) \
+ (((x) & BIT_MASK_ZCD_CODE_IN_L_8822C) << BIT_SHIFT_ZCD_CODE_IN_L_8822C)
+#define BITS_ZCD_CODE_IN_L_8822C \
+ (BIT_MASK_ZCD_CODE_IN_L_8822C << BIT_SHIFT_ZCD_CODE_IN_L_8822C)
+#define BIT_CLEAR_ZCD_CODE_IN_L_8822C(x) ((x) & (~BITS_ZCD_CODE_IN_L_8822C))
+#define BIT_GET_ZCD_CODE_IN_L_8822C(x) \
+ (((x) >> BIT_SHIFT_ZCD_CODE_IN_L_8822C) & BIT_MASK_ZCD_CODE_IN_L_8822C)
+#define BIT_SET_ZCD_CODE_IN_L_8822C(x, v) \
+ (BIT_CLEAR_ZCD_CODE_IN_L_8822C(x) | BIT_ZCD_CODE_IN_L_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_MCUFW_CTRL_8822C */
+
+#define BIT_SHIFT_RPWM_8822C 24
+#define BIT_MASK_RPWM_8822C 0xff
+#define BIT_RPWM_8822C(x) (((x) & BIT_MASK_RPWM_8822C) << BIT_SHIFT_RPWM_8822C)
+#define BITS_RPWM_8822C (BIT_MASK_RPWM_8822C << BIT_SHIFT_RPWM_8822C)
+#define BIT_CLEAR_RPWM_8822C(x) ((x) & (~BITS_RPWM_8822C))
+#define BIT_GET_RPWM_8822C(x) \
+ (((x) >> BIT_SHIFT_RPWM_8822C) & BIT_MASK_RPWM_8822C)
+#define BIT_SET_RPWM_8822C(x, v) (BIT_CLEAR_RPWM_8822C(x) | BIT_RPWM_8822C(v))
+
+#define BIT_ANA_PORT_EN_8822C BIT(22)
+#define BIT_MAC_PORT_EN_8822C BIT(21)
+#define BIT_BOOT_FSPI_EN_8822C BIT(20)
+#define BIT_ROM_DLEN_8822C BIT(19)
+
+#define BIT_SHIFT_ROM_PGE_8822C 16
+#define BIT_MASK_ROM_PGE_8822C 0x7
+#define BIT_ROM_PGE_8822C(x) \
+ (((x) & BIT_MASK_ROM_PGE_8822C) << BIT_SHIFT_ROM_PGE_8822C)
+#define BITS_ROM_PGE_8822C (BIT_MASK_ROM_PGE_8822C << BIT_SHIFT_ROM_PGE_8822C)
+#define BIT_CLEAR_ROM_PGE_8822C(x) ((x) & (~BITS_ROM_PGE_8822C))
+#define BIT_GET_ROM_PGE_8822C(x) \
+ (((x) >> BIT_SHIFT_ROM_PGE_8822C) & BIT_MASK_ROM_PGE_8822C)
+#define BIT_SET_ROM_PGE_8822C(x, v) \
+ (BIT_CLEAR_ROM_PGE_8822C(x) | BIT_ROM_PGE_8822C(v))
+
+#define BIT_FW_INIT_RDY_8822C BIT(15)
+#define BIT_FW_DW_RDY_8822C BIT(14)
+
+#define BIT_SHIFT_CPU_CLK_SEL_8822C 12
+#define BIT_MASK_CPU_CLK_SEL_8822C 0x3
+#define BIT_CPU_CLK_SEL_8822C(x) \
+ (((x) & BIT_MASK_CPU_CLK_SEL_8822C) << BIT_SHIFT_CPU_CLK_SEL_8822C)
+#define BITS_CPU_CLK_SEL_8822C \
+ (BIT_MASK_CPU_CLK_SEL_8822C << BIT_SHIFT_CPU_CLK_SEL_8822C)
+#define BIT_CLEAR_CPU_CLK_SEL_8822C(x) ((x) & (~BITS_CPU_CLK_SEL_8822C))
+#define BIT_GET_CPU_CLK_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_CPU_CLK_SEL_8822C) & BIT_MASK_CPU_CLK_SEL_8822C)
+#define BIT_SET_CPU_CLK_SEL_8822C(x, v) \
+ (BIT_CLEAR_CPU_CLK_SEL_8822C(x) | BIT_CPU_CLK_SEL_8822C(v))
+
+#define BIT_CCLK_CHG_MASK_8822C BIT(11)
+#define BIT_EMEM__TXBUF_CHKSUM_OK_8822C BIT(10)
+#define BIT_EMEM_TXBUF_DW_RDY_8822C BIT(9)
+#define BIT_EMEM_CHKSUM_OK_8822C BIT(8)
+#define BIT_EMEM_DW_OK_8822C BIT(7)
+#define BIT_DMEM_CHKSUM_OK_8822C BIT(6)
+#define BIT_DMEM_DW_OK_8822C BIT(5)
+#define BIT_IMEM_CHKSUM_OK_8822C BIT(4)
+#define BIT_IMEM_DW_OK_8822C BIT(3)
+#define BIT_IMEM_BOOT_LOAD_CHKSUM_OK_8822C BIT(2)
+#define BIT_IMEM_BOOT_LOAD_DW_OK_8822C BIT(1)
+#define BIT_MCUFWDL_EN_8822C BIT(0)
+
+/* 2 REG_MCU_TST_CFG_8822C */
+
+#define BIT_SHIFT_LBKTST_8822C 0
+#define BIT_MASK_LBKTST_8822C 0xffff
+#define BIT_LBKTST_8822C(x) \
+ (((x) & BIT_MASK_LBKTST_8822C) << BIT_SHIFT_LBKTST_8822C)
+#define BITS_LBKTST_8822C (BIT_MASK_LBKTST_8822C << BIT_SHIFT_LBKTST_8822C)
+#define BIT_CLEAR_LBKTST_8822C(x) ((x) & (~BITS_LBKTST_8822C))
+#define BIT_GET_LBKTST_8822C(x) \
+ (((x) >> BIT_SHIFT_LBKTST_8822C) & BIT_MASK_LBKTST_8822C)
+#define BIT_SET_LBKTST_8822C(x, v) \
+ (BIT_CLEAR_LBKTST_8822C(x) | BIT_LBKTST_8822C(v))
+
+/* 2 REG_HMEBOX_E0_E1_8822C */
+
+#define BIT_SHIFT_HOST_MSG_E1_8822C 16
+#define BIT_MASK_HOST_MSG_E1_8822C 0xffff
+#define BIT_HOST_MSG_E1_8822C(x) \
+ (((x) & BIT_MASK_HOST_MSG_E1_8822C) << BIT_SHIFT_HOST_MSG_E1_8822C)
+#define BITS_HOST_MSG_E1_8822C \
+ (BIT_MASK_HOST_MSG_E1_8822C << BIT_SHIFT_HOST_MSG_E1_8822C)
+#define BIT_CLEAR_HOST_MSG_E1_8822C(x) ((x) & (~BITS_HOST_MSG_E1_8822C))
+#define BIT_GET_HOST_MSG_E1_8822C(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_E1_8822C) & BIT_MASK_HOST_MSG_E1_8822C)
+#define BIT_SET_HOST_MSG_E1_8822C(x, v) \
+ (BIT_CLEAR_HOST_MSG_E1_8822C(x) | BIT_HOST_MSG_E1_8822C(v))
+
+#define BIT_SHIFT_HOST_MSG_E0_8822C 0
+#define BIT_MASK_HOST_MSG_E0_8822C 0xffff
+#define BIT_HOST_MSG_E0_8822C(x) \
+ (((x) & BIT_MASK_HOST_MSG_E0_8822C) << BIT_SHIFT_HOST_MSG_E0_8822C)
+#define BITS_HOST_MSG_E0_8822C \
+ (BIT_MASK_HOST_MSG_E0_8822C << BIT_SHIFT_HOST_MSG_E0_8822C)
+#define BIT_CLEAR_HOST_MSG_E0_8822C(x) ((x) & (~BITS_HOST_MSG_E0_8822C))
+#define BIT_GET_HOST_MSG_E0_8822C(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_E0_8822C) & BIT_MASK_HOST_MSG_E0_8822C)
+#define BIT_SET_HOST_MSG_E0_8822C(x, v) \
+ (BIT_CLEAR_HOST_MSG_E0_8822C(x) | BIT_HOST_MSG_E0_8822C(v))
+
+/* 2 REG_HMEBOX_E2_E3_8822C */
+
+#define BIT_SHIFT_HOST_MSG_E3_8822C 16
+#define BIT_MASK_HOST_MSG_E3_8822C 0xffff
+#define BIT_HOST_MSG_E3_8822C(x) \
+ (((x) & BIT_MASK_HOST_MSG_E3_8822C) << BIT_SHIFT_HOST_MSG_E3_8822C)
+#define BITS_HOST_MSG_E3_8822C \
+ (BIT_MASK_HOST_MSG_E3_8822C << BIT_SHIFT_HOST_MSG_E3_8822C)
+#define BIT_CLEAR_HOST_MSG_E3_8822C(x) ((x) & (~BITS_HOST_MSG_E3_8822C))
+#define BIT_GET_HOST_MSG_E3_8822C(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_E3_8822C) & BIT_MASK_HOST_MSG_E3_8822C)
+#define BIT_SET_HOST_MSG_E3_8822C(x, v) \
+ (BIT_CLEAR_HOST_MSG_E3_8822C(x) | BIT_HOST_MSG_E3_8822C(v))
+
+#define BIT_SHIFT_HOST_MSG_E2_8822C 0
+#define BIT_MASK_HOST_MSG_E2_8822C 0xffff
+#define BIT_HOST_MSG_E2_8822C(x) \
+ (((x) & BIT_MASK_HOST_MSG_E2_8822C) << BIT_SHIFT_HOST_MSG_E2_8822C)
+#define BITS_HOST_MSG_E2_8822C \
+ (BIT_MASK_HOST_MSG_E2_8822C << BIT_SHIFT_HOST_MSG_E2_8822C)
+#define BIT_CLEAR_HOST_MSG_E2_8822C(x) ((x) & (~BITS_HOST_MSG_E2_8822C))
+#define BIT_GET_HOST_MSG_E2_8822C(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_E2_8822C) & BIT_MASK_HOST_MSG_E2_8822C)
+#define BIT_SET_HOST_MSG_E2_8822C(x, v) \
+ (BIT_CLEAR_HOST_MSG_E2_8822C(x) | BIT_HOST_MSG_E2_8822C(v))
+
+/* 2 REG_WLLPS_CTRL_8822C */
+#define BIT_WLLPSOP_EABM_8822C BIT(31)
+#define BIT_WLLPSOP_ACKF_8822C BIT(30)
+#define BIT_WLLPSOP_DLDM_8822C BIT(29)
+#define BIT_WLLPSOP_ESWR_8822C BIT(28)
+#define BIT_WLLPSOP_PWMM_8822C BIT(27)
+#define BIT_WLLPSOP_EECK_8822C BIT(26)
+#define BIT_WLLPSOP_WLMACOFF_8822C BIT(25)
+#define BIT_WLLPSOP_EXTAL_8822C BIT(24)
+#define BIT_WL_SYNPON_VOLTSPDN_8822C BIT(23)
+#define BIT_WLLPSOP_WLBBOFF_8822C BIT(22)
+#define BIT_WLLPSOP_WLMEM_DS_8822C BIT(21)
+#define BIT_WLLPSOP_LDO_WAIT_TIME_8822C BIT(20)
+#define BIT_WLLPSOP_ANA_CLK_DIVISION_2_8822C BIT(19)
+#define BIT_AFE_BCN_8822C BIT(18)
+
+#define BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822C 12
+#define BIT_MASK_LPLDH12_VADJ_STEP_DN_8822C 0xf
+#define BIT_LPLDH12_VADJ_STEP_DN_8822C(x) \
+ (((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8822C) \
+ << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822C)
+#define BITS_LPLDH12_VADJ_STEP_DN_8822C \
+ (BIT_MASK_LPLDH12_VADJ_STEP_DN_8822C \
+ << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822C)
+#define BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8822C(x) \
+ ((x) & (~BITS_LPLDH12_VADJ_STEP_DN_8822C))
+#define BIT_GET_LPLDH12_VADJ_STEP_DN_8822C(x) \
+ (((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8822C) & \
+ BIT_MASK_LPLDH12_VADJ_STEP_DN_8822C)
+#define BIT_SET_LPLDH12_VADJ_STEP_DN_8822C(x, v) \
+ (BIT_CLEAR_LPLDH12_VADJ_STEP_DN_8822C(x) | \
+ BIT_LPLDH12_VADJ_STEP_DN_8822C(v))
+
+#define BIT_SHIFT_V15ADJ_L1_STEP_DN_V1_8822C 8
+#define BIT_MASK_V15ADJ_L1_STEP_DN_V1_8822C 0xf
+#define BIT_V15ADJ_L1_STEP_DN_V1_8822C(x) \
+ (((x) & BIT_MASK_V15ADJ_L1_STEP_DN_V1_8822C) \
+ << BIT_SHIFT_V15ADJ_L1_STEP_DN_V1_8822C)
+#define BITS_V15ADJ_L1_STEP_DN_V1_8822C \
+ (BIT_MASK_V15ADJ_L1_STEP_DN_V1_8822C \
+ << BIT_SHIFT_V15ADJ_L1_STEP_DN_V1_8822C)
+#define BIT_CLEAR_V15ADJ_L1_STEP_DN_V1_8822C(x) \
+ ((x) & (~BITS_V15ADJ_L1_STEP_DN_V1_8822C))
+#define BIT_GET_V15ADJ_L1_STEP_DN_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN_V1_8822C) & \
+ BIT_MASK_V15ADJ_L1_STEP_DN_V1_8822C)
+#define BIT_SET_V15ADJ_L1_STEP_DN_V1_8822C(x, v) \
+ (BIT_CLEAR_V15ADJ_L1_STEP_DN_V1_8822C(x) | \
+ BIT_V15ADJ_L1_STEP_DN_V1_8822C(v))
+
+#define BIT_FORCE_LEAVE_LPS_8822C BIT(3)
+#define BIT_SW_AFE_MODE_8822C BIT(2)
+#define BIT_REGU_32K_CLK_EN_8822C BIT(1)
+#define BIT_WL_LPS_EN_8822C BIT(0)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_GPIO_DEBOUNCE_CTRL_8822C */
+#define BIT_WLGP_DBC1EN_8822C BIT(15)
+
+#define BIT_SHIFT_WLGP_DBC1_8822C 8
+#define BIT_MASK_WLGP_DBC1_8822C 0xf
+#define BIT_WLGP_DBC1_8822C(x) \
+ (((x) & BIT_MASK_WLGP_DBC1_8822C) << BIT_SHIFT_WLGP_DBC1_8822C)
+#define BITS_WLGP_DBC1_8822C \
+ (BIT_MASK_WLGP_DBC1_8822C << BIT_SHIFT_WLGP_DBC1_8822C)
+#define BIT_CLEAR_WLGP_DBC1_8822C(x) ((x) & (~BITS_WLGP_DBC1_8822C))
+#define BIT_GET_WLGP_DBC1_8822C(x) \
+ (((x) >> BIT_SHIFT_WLGP_DBC1_8822C) & BIT_MASK_WLGP_DBC1_8822C)
+#define BIT_SET_WLGP_DBC1_8822C(x, v) \
+ (BIT_CLEAR_WLGP_DBC1_8822C(x) | BIT_WLGP_DBC1_8822C(v))
+
+#define BIT_WLGP_DBC0EN_8822C BIT(7)
+
+#define BIT_SHIFT_WLGP_DBC0_8822C 0
+#define BIT_MASK_WLGP_DBC0_8822C 0xf
+#define BIT_WLGP_DBC0_8822C(x) \
+ (((x) & BIT_MASK_WLGP_DBC0_8822C) << BIT_SHIFT_WLGP_DBC0_8822C)
+#define BITS_WLGP_DBC0_8822C \
+ (BIT_MASK_WLGP_DBC0_8822C << BIT_SHIFT_WLGP_DBC0_8822C)
+#define BIT_CLEAR_WLGP_DBC0_8822C(x) ((x) & (~BITS_WLGP_DBC0_8822C))
+#define BIT_GET_WLGP_DBC0_8822C(x) \
+ (((x) >> BIT_SHIFT_WLGP_DBC0_8822C) & BIT_MASK_WLGP_DBC0_8822C)
+#define BIT_SET_WLGP_DBC0_8822C(x, v) \
+ (BIT_CLEAR_WLGP_DBC0_8822C(x) | BIT_WLGP_DBC0_8822C(v))
+
+/* 2 REG_RPWM2_8822C */
+
+#define BIT_SHIFT_RPWM2_8822C 16
+#define BIT_MASK_RPWM2_8822C 0xffff
+#define BIT_RPWM2_8822C(x) \
+ (((x) & BIT_MASK_RPWM2_8822C) << BIT_SHIFT_RPWM2_8822C)
+#define BITS_RPWM2_8822C (BIT_MASK_RPWM2_8822C << BIT_SHIFT_RPWM2_8822C)
+#define BIT_CLEAR_RPWM2_8822C(x) ((x) & (~BITS_RPWM2_8822C))
+#define BIT_GET_RPWM2_8822C(x) \
+ (((x) >> BIT_SHIFT_RPWM2_8822C) & BIT_MASK_RPWM2_8822C)
+#define BIT_SET_RPWM2_8822C(x, v) \
+ (BIT_CLEAR_RPWM2_8822C(x) | BIT_RPWM2_8822C(v))
+
+/* 2 REG_SYSON_FSM_MON_8822C */
+
+#define BIT_SHIFT_FSM_MON_SEL_8822C 24
+#define BIT_MASK_FSM_MON_SEL_8822C 0x7
+#define BIT_FSM_MON_SEL_8822C(x) \
+ (((x) & BIT_MASK_FSM_MON_SEL_8822C) << BIT_SHIFT_FSM_MON_SEL_8822C)
+#define BITS_FSM_MON_SEL_8822C \
+ (BIT_MASK_FSM_MON_SEL_8822C << BIT_SHIFT_FSM_MON_SEL_8822C)
+#define BIT_CLEAR_FSM_MON_SEL_8822C(x) ((x) & (~BITS_FSM_MON_SEL_8822C))
+#define BIT_GET_FSM_MON_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_FSM_MON_SEL_8822C) & BIT_MASK_FSM_MON_SEL_8822C)
+#define BIT_SET_FSM_MON_SEL_8822C(x, v) \
+ (BIT_CLEAR_FSM_MON_SEL_8822C(x) | BIT_FSM_MON_SEL_8822C(v))
+
+#define BIT_DOP_ELDO_8822C BIT(23)
+#define BIT_FSM_MON_UPD_8822C BIT(15)
+
+#define BIT_SHIFT_FSM_PAR_8822C 0
+#define BIT_MASK_FSM_PAR_8822C 0x7fff
+#define BIT_FSM_PAR_8822C(x) \
+ (((x) & BIT_MASK_FSM_PAR_8822C) << BIT_SHIFT_FSM_PAR_8822C)
+#define BITS_FSM_PAR_8822C (BIT_MASK_FSM_PAR_8822C << BIT_SHIFT_FSM_PAR_8822C)
+#define BIT_CLEAR_FSM_PAR_8822C(x) ((x) & (~BITS_FSM_PAR_8822C))
+#define BIT_GET_FSM_PAR_8822C(x) \
+ (((x) >> BIT_SHIFT_FSM_PAR_8822C) & BIT_MASK_FSM_PAR_8822C)
+#define BIT_SET_FSM_PAR_8822C(x, v) \
+ (BIT_CLEAR_FSM_PAR_8822C(x) | BIT_FSM_PAR_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_PMC_DBG_CTRL1_8822C */
+#define BIT_BT_INT_EN_8822C BIT(31)
+
+#define BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822C 16
+#define BIT_MASK_RD_WR_WIFI_BT_INFO_8822C 0x7fff
+#define BIT_RD_WR_WIFI_BT_INFO_8822C(x) \
+ (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8822C) \
+ << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822C)
+#define BITS_RD_WR_WIFI_BT_INFO_8822C \
+ (BIT_MASK_RD_WR_WIFI_BT_INFO_8822C \
+ << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822C)
+#define BIT_CLEAR_RD_WR_WIFI_BT_INFO_8822C(x) \
+ ((x) & (~BITS_RD_WR_WIFI_BT_INFO_8822C))
+#define BIT_GET_RD_WR_WIFI_BT_INFO_8822C(x) \
+ (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8822C) & \
+ BIT_MASK_RD_WR_WIFI_BT_INFO_8822C)
+#define BIT_SET_RD_WR_WIFI_BT_INFO_8822C(x, v) \
+ (BIT_CLEAR_RD_WR_WIFI_BT_INFO_8822C(x) | \
+ BIT_RD_WR_WIFI_BT_INFO_8822C(v))
+
+#define BIT_PMC_WR_OVF_8822C BIT(8)
+
+#define BIT_SHIFT_WLPMC_ERRINT_8822C 0
+#define BIT_MASK_WLPMC_ERRINT_8822C 0xff
+#define BIT_WLPMC_ERRINT_8822C(x) \
+ (((x) & BIT_MASK_WLPMC_ERRINT_8822C) << BIT_SHIFT_WLPMC_ERRINT_8822C)
+#define BITS_WLPMC_ERRINT_8822C \
+ (BIT_MASK_WLPMC_ERRINT_8822C << BIT_SHIFT_WLPMC_ERRINT_8822C)
+#define BIT_CLEAR_WLPMC_ERRINT_8822C(x) ((x) & (~BITS_WLPMC_ERRINT_8822C))
+#define BIT_GET_WLPMC_ERRINT_8822C(x) \
+ (((x) >> BIT_SHIFT_WLPMC_ERRINT_8822C) & BIT_MASK_WLPMC_ERRINT_8822C)
+#define BIT_SET_WLPMC_ERRINT_8822C(x, v) \
+ (BIT_CLEAR_WLPMC_ERRINT_8822C(x) | BIT_WLPMC_ERRINT_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_HIMR0_8822C */
+#define BIT_TIMEOUT_INTERRUPT2_MASK_8822C BIT(31)
+#define BIT_TIMEOUT_INTERRUTP1_MASK_8822C BIT(30)
+#define BIT_PSTIMEOUT_MSK_8822C BIT(29)
+#define BIT_GTINT4_MSK_8822C BIT(28)
+#define BIT_GTINT3_MSK_8822C BIT(27)
+#define BIT_TXBCN0ERR_MSK_8822C BIT(26)
+#define BIT_TXBCN0OK_MSK_8822C BIT(25)
+#define BIT_TSF_BIT32_TOGGLE_MSK_8822C BIT(24)
+#define BIT_BCNDMAINT0_MSK_8822C BIT(20)
+#define BIT_BCNDERR0_MSK_8822C BIT(16)
+#define BIT_HSISR_IND_ON_INT_MSK_8822C BIT(15)
+#define BIT_BCNDMAINT_E_MSK_8822C BIT(14)
+#define BIT_CTWEND_MSK_8822C BIT(12)
+#define BIT_HISR1_IND_MSK_8822C BIT(11)
+#define BIT_C2HCMD_MSK_8822C BIT(10)
+#define BIT_CPWM2_MSK_8822C BIT(9)
+#define BIT_CPWM_MSK_8822C BIT(8)
+#define BIT_HIGHDOK_MSK_8822C BIT(7)
+#define BIT_MGTDOK_MSK_8822C BIT(6)
+#define BIT_BKDOK_MSK_8822C BIT(5)
+#define BIT_BEDOK_MSK_8822C BIT(4)
+#define BIT_VIDOK_MSK_8822C BIT(3)
+#define BIT_VODOK_MSK_8822C BIT(2)
+#define BIT_RDU_MSK_8822C BIT(1)
+#define BIT_RXOK_MSK_8822C BIT(0)
+
+/* 2 REG_HISR0_8822C */
+#define BIT_PSTIMEOUT2_8822C BIT(31)
+#define BIT_PSTIMEOUT1_8822C BIT(30)
+#define BIT_PSTIMEOUT_8822C BIT(29)
+#define BIT_GTINT4_8822C BIT(28)
+#define BIT_GTINT3_8822C BIT(27)
+#define BIT_TXBCN0ERR_8822C BIT(26)
+#define BIT_TXBCN0OK_8822C BIT(25)
+#define BIT_TSF_BIT32_TOGGLE_8822C BIT(24)
+#define BIT_BCNDMAINT0_8822C BIT(20)
+#define BIT_BCNDERR0_8822C BIT(16)
+#define BIT_HSISR_IND_ON_INT_8822C BIT(15)
+#define BIT_BCNDMAINT_E_8822C BIT(14)
+#define BIT_CTWEND_8822C BIT(12)
+#define BIT_HISR1_IND_INT_8822C BIT(11)
+#define BIT_C2HCMD_8822C BIT(10)
+#define BIT_CPWM2_8822C BIT(9)
+#define BIT_CPWM_8822C BIT(8)
+#define BIT_HIGHDOK_8822C BIT(7)
+#define BIT_MGTDOK_8822C BIT(6)
+#define BIT_BKDOK_8822C BIT(5)
+#define BIT_BEDOK_8822C BIT(4)
+#define BIT_VIDOK_8822C BIT(3)
+#define BIT_VODOK_8822C BIT(2)
+#define BIT_RDU_8822C BIT(1)
+#define BIT_RXOK_8822C BIT(0)
+
+/* 2 REG_HIMR1_8822C */
+#define BIT_TXFIFO_TH_INT_8822C BIT(30)
+#define BIT_BTON_STS_UPDATE_MASK_8822C BIT(29)
+#define BIT_MCU_ERR_MASK_8822C BIT(28)
+#define BIT_BCNDMAINT7__MSK_8822C BIT(27)
+#define BIT_BCNDMAINT6__MSK_8822C BIT(26)
+#define BIT_BCNDMAINT5__MSK_8822C BIT(25)
+#define BIT_BCNDMAINT4__MSK_8822C BIT(24)
+#define BIT_BCNDMAINT3_MSK_8822C BIT(23)
+#define BIT_BCNDMAINT2_MSK_8822C BIT(22)
+#define BIT_BCNDMAINT1_MSK_8822C BIT(21)
+#define BIT_BCNDERR7_MSK_8822C BIT(20)
+#define BIT_BCNDERR6_MSK_8822C BIT(19)
+#define BIT_BCNDERR5_MSK_8822C BIT(18)
+#define BIT_BCNDERR4_MSK_8822C BIT(17)
+#define BIT_BCNDERR3_MSK_8822C BIT(16)
+#define BIT_BCNDERR2_MSK_8822C BIT(15)
+#define BIT_BCNDERR1_MSK_8822C BIT(14)
+#define BIT_ATIMEND_E_MSK_8822C BIT(13)
+#define BIT_ATIMEND__MSK_8822C BIT(12)
+#define BIT_TXERR_MSK_8822C BIT(11)
+#define BIT_RXERR_MSK_8822C BIT(10)
+#define BIT_TXFOVW_MSK_8822C BIT(9)
+#define BIT_FOVW_MSK_8822C BIT(8)
+#define BIT_CPU_MGQ_TXDONE_MSK_8822C BIT(5)
+#define BIT_PS_TIMER_C_MSK_8822C BIT(4)
+#define BIT_PS_TIMER_B_MSK_8822C BIT(3)
+#define BIT_PS_TIMER_A_MSK_8822C BIT(2)
+#define BIT_CPUMGQ_TX_TIMER_MSK_8822C BIT(1)
+
+/* 2 REG_HISR1_8822C */
+#define BIT_TXFIFO_TH_INT_8822C BIT(30)
+#define BIT_BTON_STS_UPDATE_INT_8822C BIT(29)
+#define BIT_MCU_ERR_8822C BIT(28)
+#define BIT_BCNDMAINT7_8822C BIT(27)
+#define BIT_BCNDMAINT6_8822C BIT(26)
+#define BIT_BCNDMAINT5_8822C BIT(25)
+#define BIT_BCNDMAINT4_8822C BIT(24)
+#define BIT_BCNDMAINT3_8822C BIT(23)
+#define BIT_BCNDMAINT2_8822C BIT(22)
+#define BIT_BCNDMAINT1_8822C BIT(21)
+#define BIT_BCNDERR7_8822C BIT(20)
+#define BIT_BCNDERR6_8822C BIT(19)
+#define BIT_BCNDERR5_8822C BIT(18)
+#define BIT_BCNDERR4_8822C BIT(17)
+#define BIT_BCNDERR3_8822C BIT(16)
+#define BIT_BCNDERR2_8822C BIT(15)
+#define BIT_BCNDERR1_8822C BIT(14)
+#define BIT_ATIMEND_E_8822C BIT(13)
+#define BIT_ATIMEND_8822C BIT(12)
+#define BIT_TXERR_INT_8822C BIT(11)
+#define BIT_RXERR_INT_8822C BIT(10)
+#define BIT_TXFOVW_8822C BIT(9)
+#define BIT_FOVW_8822C BIT(8)
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_CPU_MGQ_TXDONE_8822C BIT(5)
+#define BIT_PS_TIMER_C_8822C BIT(4)
+#define BIT_PS_TIMER_B_8822C BIT(3)
+#define BIT_PS_TIMER_A_8822C BIT(2)
+#define BIT_CPUMGQ_TX_TIMER_8822C BIT(1)
+
+/* 2 REG_DBG_PORT_SEL_8822C */
+
+#define BIT_SHIFT_DEBUG_ST_8822C 0
+#define BIT_MASK_DEBUG_ST_8822C 0xffffffffL
+#define BIT_DEBUG_ST_8822C(x) \
+ (((x) & BIT_MASK_DEBUG_ST_8822C) << BIT_SHIFT_DEBUG_ST_8822C)
+#define BITS_DEBUG_ST_8822C \
+ (BIT_MASK_DEBUG_ST_8822C << BIT_SHIFT_DEBUG_ST_8822C)
+#define BIT_CLEAR_DEBUG_ST_8822C(x) ((x) & (~BITS_DEBUG_ST_8822C))
+#define BIT_GET_DEBUG_ST_8822C(x) \
+ (((x) >> BIT_SHIFT_DEBUG_ST_8822C) & BIT_MASK_DEBUG_ST_8822C)
+#define BIT_SET_DEBUG_ST_8822C(x, v) \
+ (BIT_CLEAR_DEBUG_ST_8822C(x) | BIT_DEBUG_ST_8822C(v))
+
+/* 2 REG_PAD_CTRL2_8822C */
+#define BIT_USB3_USB2_TRANSITION_8822C BIT(20)
+
+#define BIT_SHIFT_USB23_SW_MODE_V1_8822C 18
+#define BIT_MASK_USB23_SW_MODE_V1_8822C 0x3
+#define BIT_USB23_SW_MODE_V1_8822C(x) \
+ (((x) & BIT_MASK_USB23_SW_MODE_V1_8822C) \
+ << BIT_SHIFT_USB23_SW_MODE_V1_8822C)
+#define BITS_USB23_SW_MODE_V1_8822C \
+ (BIT_MASK_USB23_SW_MODE_V1_8822C << BIT_SHIFT_USB23_SW_MODE_V1_8822C)
+#define BIT_CLEAR_USB23_SW_MODE_V1_8822C(x) \
+ ((x) & (~BITS_USB23_SW_MODE_V1_8822C))
+#define BIT_GET_USB23_SW_MODE_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_USB23_SW_MODE_V1_8822C) & \
+ BIT_MASK_USB23_SW_MODE_V1_8822C)
+#define BIT_SET_USB23_SW_MODE_V1_8822C(x, v) \
+ (BIT_CLEAR_USB23_SW_MODE_V1_8822C(x) | BIT_USB23_SW_MODE_V1_8822C(v))
+
+#define BIT_NO_PDN_CHIPOFF_V1_8822C BIT(17)
+#define BIT_RSM_EN_V1_8822C BIT(16)
+
+#define BIT_SHIFT_MATCH_CNT_8822C 8
+#define BIT_MASK_MATCH_CNT_8822C 0xff
+#define BIT_MATCH_CNT_8822C(x) \
+ (((x) & BIT_MASK_MATCH_CNT_8822C) << BIT_SHIFT_MATCH_CNT_8822C)
+#define BITS_MATCH_CNT_8822C \
+ (BIT_MASK_MATCH_CNT_8822C << BIT_SHIFT_MATCH_CNT_8822C)
+#define BIT_CLEAR_MATCH_CNT_8822C(x) ((x) & (~BITS_MATCH_CNT_8822C))
+#define BIT_GET_MATCH_CNT_8822C(x) \
+ (((x) >> BIT_SHIFT_MATCH_CNT_8822C) & BIT_MASK_MATCH_CNT_8822C)
+#define BIT_SET_MATCH_CNT_8822C(x, v) \
+ (BIT_CLEAR_MATCH_CNT_8822C(x) | BIT_MATCH_CNT_8822C(v))
+
+#define BIT_LD_B12V_EN_8822C BIT(7)
+#define BIT_EECS_IOSEL_V1_8822C BIT(6)
+#define BIT_EECS_DATA_O_V1_8822C BIT(5)
+#define BIT_EECS_DATA_I_V1_8822C BIT(4)
+#define BIT_EESK_IOSEL_V1_8822C BIT(2)
+#define BIT_EESK_DATA_O_V1_8822C BIT(1)
+#define BIT_EESK_DATA_I_V1_8822C BIT(0)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_PMC_DBG_CTRL2_8822C */
+
+#define BIT_SHIFT_EFUSE_BURN_GNT_8822C 24
+#define BIT_MASK_EFUSE_BURN_GNT_8822C 0xff
+#define BIT_EFUSE_BURN_GNT_8822C(x) \
+ (((x) & BIT_MASK_EFUSE_BURN_GNT_8822C) \
+ << BIT_SHIFT_EFUSE_BURN_GNT_8822C)
+#define BITS_EFUSE_BURN_GNT_8822C \
+ (BIT_MASK_EFUSE_BURN_GNT_8822C << BIT_SHIFT_EFUSE_BURN_GNT_8822C)
+#define BIT_CLEAR_EFUSE_BURN_GNT_8822C(x) ((x) & (~BITS_EFUSE_BURN_GNT_8822C))
+#define BIT_GET_EFUSE_BURN_GNT_8822C(x) \
+ (((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8822C) & \
+ BIT_MASK_EFUSE_BURN_GNT_8822C)
+#define BIT_SET_EFUSE_BURN_GNT_8822C(x, v) \
+ (BIT_CLEAR_EFUSE_BURN_GNT_8822C(x) | BIT_EFUSE_BURN_GNT_8822C(v))
+
+#define BIT_STOP_WL_PMC_8822C BIT(9)
+#define BIT_STOP_SYM_PMC_8822C BIT(8)
+#define BIT_BT_ACCESS_WL_PAGE0_8822C BIT(6)
+#define BIT_REG_RST_WLPMC_8822C BIT(5)
+#define BIT_REG_RST_PD12N_8822C BIT(4)
+#define BIT_SYSON_DIS_WLREG_WRMSK_8822C BIT(3)
+#define BIT_SYSON_DIS_PMCREG_WRMSK_8822C BIT(2)
+
+#define BIT_SHIFT_SYSON_REG_ARB_8822C 0
+#define BIT_MASK_SYSON_REG_ARB_8822C 0x3
+#define BIT_SYSON_REG_ARB_8822C(x) \
+ (((x) & BIT_MASK_SYSON_REG_ARB_8822C) << BIT_SHIFT_SYSON_REG_ARB_8822C)
+#define BITS_SYSON_REG_ARB_8822C \
+ (BIT_MASK_SYSON_REG_ARB_8822C << BIT_SHIFT_SYSON_REG_ARB_8822C)
+#define BIT_CLEAR_SYSON_REG_ARB_8822C(x) ((x) & (~BITS_SYSON_REG_ARB_8822C))
+#define BIT_GET_SYSON_REG_ARB_8822C(x) \
+ (((x) >> BIT_SHIFT_SYSON_REG_ARB_8822C) & BIT_MASK_SYSON_REG_ARB_8822C)
+#define BIT_SET_SYSON_REG_ARB_8822C(x, v) \
+ (BIT_CLEAR_SYSON_REG_ARB_8822C(x) | BIT_SYSON_REG_ARB_8822C(v))
+
+/* 2 REG_BIST_CTRL_8822C */
+#define BIT_BIST_USB_DIS_8822C BIT(27)
+#define BIT_BIST_PCI_DIS_8822C BIT(26)
+#define BIT_BIST_BT_DIS_8822C BIT(25)
+#define BIT_BIST_WL_DIS_8822C BIT(24)
+
+#define BIT_SHIFT_BIST_RPT_SEL_8822C 16
+#define BIT_MASK_BIST_RPT_SEL_8822C 0xf
+#define BIT_BIST_RPT_SEL_8822C(x) \
+ (((x) & BIT_MASK_BIST_RPT_SEL_8822C) << BIT_SHIFT_BIST_RPT_SEL_8822C)
+#define BITS_BIST_RPT_SEL_8822C \
+ (BIT_MASK_BIST_RPT_SEL_8822C << BIT_SHIFT_BIST_RPT_SEL_8822C)
+#define BIT_CLEAR_BIST_RPT_SEL_8822C(x) ((x) & (~BITS_BIST_RPT_SEL_8822C))
+#define BIT_GET_BIST_RPT_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_BIST_RPT_SEL_8822C) & BIT_MASK_BIST_RPT_SEL_8822C)
+#define BIT_SET_BIST_RPT_SEL_8822C(x, v) \
+ (BIT_CLEAR_BIST_RPT_SEL_8822C(x) | BIT_BIST_RPT_SEL_8822C(v))
+
+#define BIT_BIST_RESUME_PS_8822C BIT(4)
+#define BIT_BIST_RESUME_8822C BIT(3)
+#define BIT_BIST_NORMAL_8822C BIT(2)
+#define BIT_BIST_RSTN_8822C BIT(1)
+#define BIT_BIST_CLK_EN_8822C BIT(0)
+
+/* 2 REG_BIST_RPT_8822C */
+
+#define BIT_SHIFT_MBIST_REPORT_8822C 0
+#define BIT_MASK_MBIST_REPORT_8822C 0xffffffffL
+#define BIT_MBIST_REPORT_8822C(x) \
+ (((x) & BIT_MASK_MBIST_REPORT_8822C) << BIT_SHIFT_MBIST_REPORT_8822C)
+#define BITS_MBIST_REPORT_8822C \
+ (BIT_MASK_MBIST_REPORT_8822C << BIT_SHIFT_MBIST_REPORT_8822C)
+#define BIT_CLEAR_MBIST_REPORT_8822C(x) ((x) & (~BITS_MBIST_REPORT_8822C))
+#define BIT_GET_MBIST_REPORT_8822C(x) \
+ (((x) >> BIT_SHIFT_MBIST_REPORT_8822C) & BIT_MASK_MBIST_REPORT_8822C)
+#define BIT_SET_MBIST_REPORT_8822C(x, v) \
+ (BIT_CLEAR_MBIST_REPORT_8822C(x) | BIT_MBIST_REPORT_8822C(v))
+
+/* 2 REG_MEM_CTRL_8822C */
+#define BIT_UMEM_RME_8822C BIT(31)
+
+#define BIT_SHIFT_BT_SPRAM_8822C 28
+#define BIT_MASK_BT_SPRAM_8822C 0x3
+#define BIT_BT_SPRAM_8822C(x) \
+ (((x) & BIT_MASK_BT_SPRAM_8822C) << BIT_SHIFT_BT_SPRAM_8822C)
+#define BITS_BT_SPRAM_8822C \
+ (BIT_MASK_BT_SPRAM_8822C << BIT_SHIFT_BT_SPRAM_8822C)
+#define BIT_CLEAR_BT_SPRAM_8822C(x) ((x) & (~BITS_BT_SPRAM_8822C))
+#define BIT_GET_BT_SPRAM_8822C(x) \
+ (((x) >> BIT_SHIFT_BT_SPRAM_8822C) & BIT_MASK_BT_SPRAM_8822C)
+#define BIT_SET_BT_SPRAM_8822C(x, v) \
+ (BIT_CLEAR_BT_SPRAM_8822C(x) | BIT_BT_SPRAM_8822C(v))
+
+#define BIT_SHIFT_BT_ROM_8822C 24
+#define BIT_MASK_BT_ROM_8822C 0xf
+#define BIT_BT_ROM_8822C(x) \
+ (((x) & BIT_MASK_BT_ROM_8822C) << BIT_SHIFT_BT_ROM_8822C)
+#define BITS_BT_ROM_8822C (BIT_MASK_BT_ROM_8822C << BIT_SHIFT_BT_ROM_8822C)
+#define BIT_CLEAR_BT_ROM_8822C(x) ((x) & (~BITS_BT_ROM_8822C))
+#define BIT_GET_BT_ROM_8822C(x) \
+ (((x) >> BIT_SHIFT_BT_ROM_8822C) & BIT_MASK_BT_ROM_8822C)
+#define BIT_SET_BT_ROM_8822C(x, v) \
+ (BIT_CLEAR_BT_ROM_8822C(x) | BIT_BT_ROM_8822C(v))
+
+#define BIT_SHIFT_PCI_DPRAM_8822C 10
+#define BIT_MASK_PCI_DPRAM_8822C 0x3
+#define BIT_PCI_DPRAM_8822C(x) \
+ (((x) & BIT_MASK_PCI_DPRAM_8822C) << BIT_SHIFT_PCI_DPRAM_8822C)
+#define BITS_PCI_DPRAM_8822C \
+ (BIT_MASK_PCI_DPRAM_8822C << BIT_SHIFT_PCI_DPRAM_8822C)
+#define BIT_CLEAR_PCI_DPRAM_8822C(x) ((x) & (~BITS_PCI_DPRAM_8822C))
+#define BIT_GET_PCI_DPRAM_8822C(x) \
+ (((x) >> BIT_SHIFT_PCI_DPRAM_8822C) & BIT_MASK_PCI_DPRAM_8822C)
+#define BIT_SET_PCI_DPRAM_8822C(x, v) \
+ (BIT_CLEAR_PCI_DPRAM_8822C(x) | BIT_PCI_DPRAM_8822C(v))
+
+#define BIT_SHIFT_PCI_SPRAM_8822C 8
+#define BIT_MASK_PCI_SPRAM_8822C 0x3
+#define BIT_PCI_SPRAM_8822C(x) \
+ (((x) & BIT_MASK_PCI_SPRAM_8822C) << BIT_SHIFT_PCI_SPRAM_8822C)
+#define BITS_PCI_SPRAM_8822C \
+ (BIT_MASK_PCI_SPRAM_8822C << BIT_SHIFT_PCI_SPRAM_8822C)
+#define BIT_CLEAR_PCI_SPRAM_8822C(x) ((x) & (~BITS_PCI_SPRAM_8822C))
+#define BIT_GET_PCI_SPRAM_8822C(x) \
+ (((x) >> BIT_SHIFT_PCI_SPRAM_8822C) & BIT_MASK_PCI_SPRAM_8822C)
+#define BIT_SET_PCI_SPRAM_8822C(x, v) \
+ (BIT_CLEAR_PCI_SPRAM_8822C(x) | BIT_PCI_SPRAM_8822C(v))
+
+#define BIT_SHIFT_USB_SPRAM_8822C 6
+#define BIT_MASK_USB_SPRAM_8822C 0x3
+#define BIT_USB_SPRAM_8822C(x) \
+ (((x) & BIT_MASK_USB_SPRAM_8822C) << BIT_SHIFT_USB_SPRAM_8822C)
+#define BITS_USB_SPRAM_8822C \
+ (BIT_MASK_USB_SPRAM_8822C << BIT_SHIFT_USB_SPRAM_8822C)
+#define BIT_CLEAR_USB_SPRAM_8822C(x) ((x) & (~BITS_USB_SPRAM_8822C))
+#define BIT_GET_USB_SPRAM_8822C(x) \
+ (((x) >> BIT_SHIFT_USB_SPRAM_8822C) & BIT_MASK_USB_SPRAM_8822C)
+#define BIT_SET_USB_SPRAM_8822C(x, v) \
+ (BIT_CLEAR_USB_SPRAM_8822C(x) | BIT_USB_SPRAM_8822C(v))
+
+#define BIT_SHIFT_USB_SPRF_8822C 4
+#define BIT_MASK_USB_SPRF_8822C 0x3
+#define BIT_USB_SPRF_8822C(x) \
+ (((x) & BIT_MASK_USB_SPRF_8822C) << BIT_SHIFT_USB_SPRF_8822C)
+#define BITS_USB_SPRF_8822C \
+ (BIT_MASK_USB_SPRF_8822C << BIT_SHIFT_USB_SPRF_8822C)
+#define BIT_CLEAR_USB_SPRF_8822C(x) ((x) & (~BITS_USB_SPRF_8822C))
+#define BIT_GET_USB_SPRF_8822C(x) \
+ (((x) >> BIT_SHIFT_USB_SPRF_8822C) & BIT_MASK_USB_SPRF_8822C)
+#define BIT_SET_USB_SPRF_8822C(x, v) \
+ (BIT_CLEAR_USB_SPRF_8822C(x) | BIT_USB_SPRF_8822C(v))
+
+#define BIT_SHIFT_MCU_ROM_8822C 0
+#define BIT_MASK_MCU_ROM_8822C 0xf
+#define BIT_MCU_ROM_8822C(x) \
+ (((x) & BIT_MASK_MCU_ROM_8822C) << BIT_SHIFT_MCU_ROM_8822C)
+#define BITS_MCU_ROM_8822C (BIT_MASK_MCU_ROM_8822C << BIT_SHIFT_MCU_ROM_8822C)
+#define BIT_CLEAR_MCU_ROM_8822C(x) ((x) & (~BITS_MCU_ROM_8822C))
+#define BIT_GET_MCU_ROM_8822C(x) \
+ (((x) >> BIT_SHIFT_MCU_ROM_8822C) & BIT_MASK_MCU_ROM_8822C)
+#define BIT_SET_MCU_ROM_8822C(x, v) \
+ (BIT_CLEAR_MCU_ROM_8822C(x) | BIT_MCU_ROM_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_USB_SIE_INTF_8822C */
+#define BIT_RD_SEL_8822C BIT(31)
+#define BIT_USB_SIE_INTF_WE_V1_8822C BIT(30)
+#define BIT_USB_SIE_INTF_BYIOREG_V1_8822C BIT(29)
+#define BIT_USB_SIE_SELECT_8822C BIT(28)
+
+#define BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822C 16
+#define BIT_MASK_USB_SIE_INTF_ADDR_V1_8822C 0x1ff
+#define BIT_USB_SIE_INTF_ADDR_V1_8822C(x) \
+ (((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8822C) \
+ << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822C)
+#define BITS_USB_SIE_INTF_ADDR_V1_8822C \
+ (BIT_MASK_USB_SIE_INTF_ADDR_V1_8822C \
+ << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822C)
+#define BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8822C(x) \
+ ((x) & (~BITS_USB_SIE_INTF_ADDR_V1_8822C))
+#define BIT_GET_USB_SIE_INTF_ADDR_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8822C) & \
+ BIT_MASK_USB_SIE_INTF_ADDR_V1_8822C)
+#define BIT_SET_USB_SIE_INTF_ADDR_V1_8822C(x, v) \
+ (BIT_CLEAR_USB_SIE_INTF_ADDR_V1_8822C(x) | \
+ BIT_USB_SIE_INTF_ADDR_V1_8822C(v))
+
+#define BIT_SHIFT_USB_SIE_INTF_RD_8822C 8
+#define BIT_MASK_USB_SIE_INTF_RD_8822C 0xff
+#define BIT_USB_SIE_INTF_RD_8822C(x) \
+ (((x) & BIT_MASK_USB_SIE_INTF_RD_8822C) \
+ << BIT_SHIFT_USB_SIE_INTF_RD_8822C)
+#define BITS_USB_SIE_INTF_RD_8822C \
+ (BIT_MASK_USB_SIE_INTF_RD_8822C << BIT_SHIFT_USB_SIE_INTF_RD_8822C)
+#define BIT_CLEAR_USB_SIE_INTF_RD_8822C(x) ((x) & (~BITS_USB_SIE_INTF_RD_8822C))
+#define BIT_GET_USB_SIE_INTF_RD_8822C(x) \
+ (((x) >> BIT_SHIFT_USB_SIE_INTF_RD_8822C) & \
+ BIT_MASK_USB_SIE_INTF_RD_8822C)
+#define BIT_SET_USB_SIE_INTF_RD_8822C(x, v) \
+ (BIT_CLEAR_USB_SIE_INTF_RD_8822C(x) | BIT_USB_SIE_INTF_RD_8822C(v))
+
+#define BIT_SHIFT_USB_SIE_INTF_WD_8822C 0
+#define BIT_MASK_USB_SIE_INTF_WD_8822C 0xff
+#define BIT_USB_SIE_INTF_WD_8822C(x) \
+ (((x) & BIT_MASK_USB_SIE_INTF_WD_8822C) \
+ << BIT_SHIFT_USB_SIE_INTF_WD_8822C)
+#define BITS_USB_SIE_INTF_WD_8822C \
+ (BIT_MASK_USB_SIE_INTF_WD_8822C << BIT_SHIFT_USB_SIE_INTF_WD_8822C)
+#define BIT_CLEAR_USB_SIE_INTF_WD_8822C(x) ((x) & (~BITS_USB_SIE_INTF_WD_8822C))
+#define BIT_GET_USB_SIE_INTF_WD_8822C(x) \
+ (((x) >> BIT_SHIFT_USB_SIE_INTF_WD_8822C) & \
+ BIT_MASK_USB_SIE_INTF_WD_8822C)
+#define BIT_SET_USB_SIE_INTF_WD_8822C(x, v) \
+ (BIT_CLEAR_USB_SIE_INTF_WD_8822C(x) | BIT_USB_SIE_INTF_WD_8822C(v))
+
+/* 2 REG_PCIE_MIO_INTF_8822C */
+
+#define BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8822C 16
+#define BIT_MASK_PCIE_MIO_ADDR_PAGE_8822C 0x3
+#define BIT_PCIE_MIO_ADDR_PAGE_8822C(x) \
+ (((x) & BIT_MASK_PCIE_MIO_ADDR_PAGE_8822C) \
+ << BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8822C)
+#define BITS_PCIE_MIO_ADDR_PAGE_8822C \
+ (BIT_MASK_PCIE_MIO_ADDR_PAGE_8822C \
+ << BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8822C)
+#define BIT_CLEAR_PCIE_MIO_ADDR_PAGE_8822C(x) \
+ ((x) & (~BITS_PCIE_MIO_ADDR_PAGE_8822C))
+#define BIT_GET_PCIE_MIO_ADDR_PAGE_8822C(x) \
+ (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_PAGE_8822C) & \
+ BIT_MASK_PCIE_MIO_ADDR_PAGE_8822C)
+#define BIT_SET_PCIE_MIO_ADDR_PAGE_8822C(x, v) \
+ (BIT_CLEAR_PCIE_MIO_ADDR_PAGE_8822C(x) | \
+ BIT_PCIE_MIO_ADDR_PAGE_8822C(v))
+
+#define BIT_PCIE_MIO_BYIOREG_8822C BIT(13)
+#define BIT_PCIE_MIO_RE_8822C BIT(12)
+
+#define BIT_SHIFT_PCIE_MIO_WE_8822C 8
+#define BIT_MASK_PCIE_MIO_WE_8822C 0xf
+#define BIT_PCIE_MIO_WE_8822C(x) \
+ (((x) & BIT_MASK_PCIE_MIO_WE_8822C) << BIT_SHIFT_PCIE_MIO_WE_8822C)
+#define BITS_PCIE_MIO_WE_8822C \
+ (BIT_MASK_PCIE_MIO_WE_8822C << BIT_SHIFT_PCIE_MIO_WE_8822C)
+#define BIT_CLEAR_PCIE_MIO_WE_8822C(x) ((x) & (~BITS_PCIE_MIO_WE_8822C))
+#define BIT_GET_PCIE_MIO_WE_8822C(x) \
+ (((x) >> BIT_SHIFT_PCIE_MIO_WE_8822C) & BIT_MASK_PCIE_MIO_WE_8822C)
+#define BIT_SET_PCIE_MIO_WE_8822C(x, v) \
+ (BIT_CLEAR_PCIE_MIO_WE_8822C(x) | BIT_PCIE_MIO_WE_8822C(v))
+
+#define BIT_SHIFT_PCIE_MIO_ADDR_8822C 0
+#define BIT_MASK_PCIE_MIO_ADDR_8822C 0xff
+#define BIT_PCIE_MIO_ADDR_8822C(x) \
+ (((x) & BIT_MASK_PCIE_MIO_ADDR_8822C) << BIT_SHIFT_PCIE_MIO_ADDR_8822C)
+#define BITS_PCIE_MIO_ADDR_8822C \
+ (BIT_MASK_PCIE_MIO_ADDR_8822C << BIT_SHIFT_PCIE_MIO_ADDR_8822C)
+#define BIT_CLEAR_PCIE_MIO_ADDR_8822C(x) ((x) & (~BITS_PCIE_MIO_ADDR_8822C))
+#define BIT_GET_PCIE_MIO_ADDR_8822C(x) \
+ (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8822C) & BIT_MASK_PCIE_MIO_ADDR_8822C)
+#define BIT_SET_PCIE_MIO_ADDR_8822C(x, v) \
+ (BIT_CLEAR_PCIE_MIO_ADDR_8822C(x) | BIT_PCIE_MIO_ADDR_8822C(v))
+
+/* 2 REG_PCIE_MIO_INTD_8822C */
+
+#define BIT_SHIFT_PCIE_MIO_DATA_8822C 0
+#define BIT_MASK_PCIE_MIO_DATA_8822C 0xffffffffL
+#define BIT_PCIE_MIO_DATA_8822C(x) \
+ (((x) & BIT_MASK_PCIE_MIO_DATA_8822C) << BIT_SHIFT_PCIE_MIO_DATA_8822C)
+#define BITS_PCIE_MIO_DATA_8822C \
+ (BIT_MASK_PCIE_MIO_DATA_8822C << BIT_SHIFT_PCIE_MIO_DATA_8822C)
+#define BIT_CLEAR_PCIE_MIO_DATA_8822C(x) ((x) & (~BITS_PCIE_MIO_DATA_8822C))
+#define BIT_GET_PCIE_MIO_DATA_8822C(x) \
+ (((x) >> BIT_SHIFT_PCIE_MIO_DATA_8822C) & BIT_MASK_PCIE_MIO_DATA_8822C)
+#define BIT_SET_PCIE_MIO_DATA_8822C(x, v) \
+ (BIT_CLEAR_PCIE_MIO_DATA_8822C(x) | BIT_PCIE_MIO_DATA_8822C(v))
+
+/* 2 REG_WLRF1_8822C */
+
+#define BIT_SHIFT_WLRF1_CTRL_8822C 24
+#define BIT_MASK_WLRF1_CTRL_8822C 0xff
+#define BIT_WLRF1_CTRL_8822C(x) \
+ (((x) & BIT_MASK_WLRF1_CTRL_8822C) << BIT_SHIFT_WLRF1_CTRL_8822C)
+#define BITS_WLRF1_CTRL_8822C \
+ (BIT_MASK_WLRF1_CTRL_8822C << BIT_SHIFT_WLRF1_CTRL_8822C)
+#define BIT_CLEAR_WLRF1_CTRL_8822C(x) ((x) & (~BITS_WLRF1_CTRL_8822C))
+#define BIT_GET_WLRF1_CTRL_8822C(x) \
+ (((x) >> BIT_SHIFT_WLRF1_CTRL_8822C) & BIT_MASK_WLRF1_CTRL_8822C)
+#define BIT_SET_WLRF1_CTRL_8822C(x, v) \
+ (BIT_CLEAR_WLRF1_CTRL_8822C(x) | BIT_WLRF1_CTRL_8822C(v))
+
+/* 2 REG_SYS_CFG1_8822C */
+
+#define BIT_SHIFT_TRP_ICFG_8822C 28
+#define BIT_MASK_TRP_ICFG_8822C 0xf
+#define BIT_TRP_ICFG_8822C(x) \
+ (((x) & BIT_MASK_TRP_ICFG_8822C) << BIT_SHIFT_TRP_ICFG_8822C)
+#define BITS_TRP_ICFG_8822C \
+ (BIT_MASK_TRP_ICFG_8822C << BIT_SHIFT_TRP_ICFG_8822C)
+#define BIT_CLEAR_TRP_ICFG_8822C(x) ((x) & (~BITS_TRP_ICFG_8822C))
+#define BIT_GET_TRP_ICFG_8822C(x) \
+ (((x) >> BIT_SHIFT_TRP_ICFG_8822C) & BIT_MASK_TRP_ICFG_8822C)
+#define BIT_SET_TRP_ICFG_8822C(x, v) \
+ (BIT_CLEAR_TRP_ICFG_8822C(x) | BIT_TRP_ICFG_8822C(v))
+
+#define BIT_RF_TYPE_ID_8822C BIT(27)
+#define BIT_BD_HCI_SEL_8822C BIT(26)
+#define BIT_BD_PKG_SEL_8822C BIT(25)
+#define BIT_INTERNAL_EXTERNAL_SWR_8822C BIT(24)
+#define BIT_RTL_ID_8822C BIT(23)
+#define BIT_PAD_HWPD_IDN_8822C BIT(22)
+#define BIT_TESTMODE_8822C BIT(20)
+
+#define BIT_SHIFT_VENDOR_ID_8822C 16
+#define BIT_MASK_VENDOR_ID_8822C 0xf
+#define BIT_VENDOR_ID_8822C(x) \
+ (((x) & BIT_MASK_VENDOR_ID_8822C) << BIT_SHIFT_VENDOR_ID_8822C)
+#define BITS_VENDOR_ID_8822C \
+ (BIT_MASK_VENDOR_ID_8822C << BIT_SHIFT_VENDOR_ID_8822C)
+#define BIT_CLEAR_VENDOR_ID_8822C(x) ((x) & (~BITS_VENDOR_ID_8822C))
+#define BIT_GET_VENDOR_ID_8822C(x) \
+ (((x) >> BIT_SHIFT_VENDOR_ID_8822C) & BIT_MASK_VENDOR_ID_8822C)
+#define BIT_SET_VENDOR_ID_8822C(x, v) \
+ (BIT_CLEAR_VENDOR_ID_8822C(x) | BIT_VENDOR_ID_8822C(v))
+
+#define BIT_SHIFT_CHIP_VER_8822C 12
+#define BIT_MASK_CHIP_VER_8822C 0xf
+#define BIT_CHIP_VER_8822C(x) \
+ (((x) & BIT_MASK_CHIP_VER_8822C) << BIT_SHIFT_CHIP_VER_8822C)
+#define BITS_CHIP_VER_8822C \
+ (BIT_MASK_CHIP_VER_8822C << BIT_SHIFT_CHIP_VER_8822C)
+#define BIT_CLEAR_CHIP_VER_8822C(x) ((x) & (~BITS_CHIP_VER_8822C))
+#define BIT_GET_CHIP_VER_8822C(x) \
+ (((x) >> BIT_SHIFT_CHIP_VER_8822C) & BIT_MASK_CHIP_VER_8822C)
+#define BIT_SET_CHIP_VER_8822C(x, v) \
+ (BIT_CLEAR_CHIP_VER_8822C(x) | BIT_CHIP_VER_8822C(v))
+
+#define BIT_BD_MAC3_8822C BIT(11)
+#define BIT_BD_MAC1_8822C BIT(10)
+#define BIT_BD_MAC2_8822C BIT(9)
+#define BIT_SIC_IDLE_8822C BIT(8)
+#define BIT_SW_OFFLOAD_EN_8822C BIT(7)
+#define BIT_OCP_SHUTDN_8822C BIT(6)
+#define BIT_V15_VLD_8822C BIT(5)
+#define BIT_PCIRSTB_8822C BIT(4)
+#define BIT_PCLK_VLD_8822C BIT(3)
+#define BIT_UCLK_VLD_8822C BIT(2)
+#define BIT_ACLK_VLD_8822C BIT(1)
+#define BIT_XCLK_VLD_8822C BIT(0)
+
+/* 2 REG_SYS_STATUS1_8822C */
+
+#define BIT_SHIFT_RF_RL_ID_8822C 28
+#define BIT_MASK_RF_RL_ID_8822C 0xf
+#define BIT_RF_RL_ID_8822C(x) \
+ (((x) & BIT_MASK_RF_RL_ID_8822C) << BIT_SHIFT_RF_RL_ID_8822C)
+#define BITS_RF_RL_ID_8822C \
+ (BIT_MASK_RF_RL_ID_8822C << BIT_SHIFT_RF_RL_ID_8822C)
+#define BIT_CLEAR_RF_RL_ID_8822C(x) ((x) & (~BITS_RF_RL_ID_8822C))
+#define BIT_GET_RF_RL_ID_8822C(x) \
+ (((x) >> BIT_SHIFT_RF_RL_ID_8822C) & BIT_MASK_RF_RL_ID_8822C)
+#define BIT_SET_RF_RL_ID_8822C(x, v) \
+ (BIT_CLEAR_RF_RL_ID_8822C(x) | BIT_RF_RL_ID_8822C(v))
+
+#define BIT_HPHY_ICFG_8822C BIT(19)
+
+#define BIT_SHIFT_SEL_0XC0_8822C 16
+#define BIT_MASK_SEL_0XC0_8822C 0x3
+#define BIT_SEL_0XC0_8822C(x) \
+ (((x) & BIT_MASK_SEL_0XC0_8822C) << BIT_SHIFT_SEL_0XC0_8822C)
+#define BITS_SEL_0XC0_8822C \
+ (BIT_MASK_SEL_0XC0_8822C << BIT_SHIFT_SEL_0XC0_8822C)
+#define BIT_CLEAR_SEL_0XC0_8822C(x) ((x) & (~BITS_SEL_0XC0_8822C))
+#define BIT_GET_SEL_0XC0_8822C(x) \
+ (((x) >> BIT_SHIFT_SEL_0XC0_8822C) & BIT_MASK_SEL_0XC0_8822C)
+#define BIT_SET_SEL_0XC0_8822C(x, v) \
+ (BIT_CLEAR_SEL_0XC0_8822C(x) | BIT_SEL_0XC0_8822C(v))
+
+#define BIT_SHIFT_HCI_SEL_V4_8822C 12
+#define BIT_MASK_HCI_SEL_V4_8822C 0x3
+#define BIT_HCI_SEL_V4_8822C(x) \
+ (((x) & BIT_MASK_HCI_SEL_V4_8822C) << BIT_SHIFT_HCI_SEL_V4_8822C)
+#define BITS_HCI_SEL_V4_8822C \
+ (BIT_MASK_HCI_SEL_V4_8822C << BIT_SHIFT_HCI_SEL_V4_8822C)
+#define BIT_CLEAR_HCI_SEL_V4_8822C(x) ((x) & (~BITS_HCI_SEL_V4_8822C))
+#define BIT_GET_HCI_SEL_V4_8822C(x) \
+ (((x) >> BIT_SHIFT_HCI_SEL_V4_8822C) & BIT_MASK_HCI_SEL_V4_8822C)
+#define BIT_SET_HCI_SEL_V4_8822C(x, v) \
+ (BIT_CLEAR_HCI_SEL_V4_8822C(x) | BIT_HCI_SEL_V4_8822C(v))
+
+#define BIT_USB_OPERATION_MODE_8822C BIT(10)
+#define BIT_BT_PDN_8822C BIT(9)
+#define BIT_AUTO_WLPON_8822C BIT(8)
+#define BIT_WL_MODE_8822C BIT(7)
+#define BIT_PKG_SEL_HCI_8822C BIT(6)
+
+#define BIT_SHIFT_PAD_HCI_SEL_V2_8822C 3
+#define BIT_MASK_PAD_HCI_SEL_V2_8822C 0x3
+#define BIT_PAD_HCI_SEL_V2_8822C(x) \
+ (((x) & BIT_MASK_PAD_HCI_SEL_V2_8822C) \
+ << BIT_SHIFT_PAD_HCI_SEL_V2_8822C)
+#define BITS_PAD_HCI_SEL_V2_8822C \
+ (BIT_MASK_PAD_HCI_SEL_V2_8822C << BIT_SHIFT_PAD_HCI_SEL_V2_8822C)
+#define BIT_CLEAR_PAD_HCI_SEL_V2_8822C(x) ((x) & (~BITS_PAD_HCI_SEL_V2_8822C))
+#define BIT_GET_PAD_HCI_SEL_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_PAD_HCI_SEL_V2_8822C) & \
+ BIT_MASK_PAD_HCI_SEL_V2_8822C)
+#define BIT_SET_PAD_HCI_SEL_V2_8822C(x, v) \
+ (BIT_CLEAR_PAD_HCI_SEL_V2_8822C(x) | BIT_PAD_HCI_SEL_V2_8822C(v))
+
+#define BIT_SHIFT_EFS_HCI_SEL_V1_8822C 0
+#define BIT_MASK_EFS_HCI_SEL_V1_8822C 0x7
+#define BIT_EFS_HCI_SEL_V1_8822C(x) \
+ (((x) & BIT_MASK_EFS_HCI_SEL_V1_8822C) \
+ << BIT_SHIFT_EFS_HCI_SEL_V1_8822C)
+#define BITS_EFS_HCI_SEL_V1_8822C \
+ (BIT_MASK_EFS_HCI_SEL_V1_8822C << BIT_SHIFT_EFS_HCI_SEL_V1_8822C)
+#define BIT_CLEAR_EFS_HCI_SEL_V1_8822C(x) ((x) & (~BITS_EFS_HCI_SEL_V1_8822C))
+#define BIT_GET_EFS_HCI_SEL_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_EFS_HCI_SEL_V1_8822C) & \
+ BIT_MASK_EFS_HCI_SEL_V1_8822C)
+#define BIT_SET_EFS_HCI_SEL_V1_8822C(x, v) \
+ (BIT_CLEAR_EFS_HCI_SEL_V1_8822C(x) | BIT_EFS_HCI_SEL_V1_8822C(v))
+
+/* 2 REG_SYS_STATUS2_8822C */
+#define BIT_HIOE_ON_TIMEOUT_8822C BIT(23)
+#define BIT_SIC_ON_TIMEOUT_8822C BIT(22)
+#define BIT_CPU_ON_TIMEOUT_8822C BIT(21)
+#define BIT_HCI_ON_TIMEOUT_8822C BIT(20)
+#define BIT_SIO_ALDN_8822C BIT(19)
+#define BIT_USB_ALDN_8822C BIT(18)
+#define BIT_PCI_ALDN_8822C BIT(17)
+#define BIT_SYS_ALDN_8822C BIT(16)
+
+#define BIT_SHIFT_EPVID1_8822C 8
+#define BIT_MASK_EPVID1_8822C 0xff
+#define BIT_EPVID1_8822C(x) \
+ (((x) & BIT_MASK_EPVID1_8822C) << BIT_SHIFT_EPVID1_8822C)
+#define BITS_EPVID1_8822C (BIT_MASK_EPVID1_8822C << BIT_SHIFT_EPVID1_8822C)
+#define BIT_CLEAR_EPVID1_8822C(x) ((x) & (~BITS_EPVID1_8822C))
+#define BIT_GET_EPVID1_8822C(x) \
+ (((x) >> BIT_SHIFT_EPVID1_8822C) & BIT_MASK_EPVID1_8822C)
+#define BIT_SET_EPVID1_8822C(x, v) \
+ (BIT_CLEAR_EPVID1_8822C(x) | BIT_EPVID1_8822C(v))
+
+#define BIT_SHIFT_EPVID0_8822C 0
+#define BIT_MASK_EPVID0_8822C 0xff
+#define BIT_EPVID0_8822C(x) \
+ (((x) & BIT_MASK_EPVID0_8822C) << BIT_SHIFT_EPVID0_8822C)
+#define BITS_EPVID0_8822C (BIT_MASK_EPVID0_8822C << BIT_SHIFT_EPVID0_8822C)
+#define BIT_CLEAR_EPVID0_8822C(x) ((x) & (~BITS_EPVID0_8822C))
+#define BIT_GET_EPVID0_8822C(x) \
+ (((x) >> BIT_SHIFT_EPVID0_8822C) & BIT_MASK_EPVID0_8822C)
+#define BIT_SET_EPVID0_8822C(x, v) \
+ (BIT_CLEAR_EPVID0_8822C(x) | BIT_EPVID0_8822C(v))
+
+/* 2 REG_SYS_CFG2_8822C */
+#define BIT_HCI_SEL_EMBEDDED_8822C BIT(8)
+
+#define BIT_SHIFT_HW_ID_8822C 0
+#define BIT_MASK_HW_ID_8822C 0xff
+#define BIT_HW_ID_8822C(x) \
+ (((x) & BIT_MASK_HW_ID_8822C) << BIT_SHIFT_HW_ID_8822C)
+#define BITS_HW_ID_8822C (BIT_MASK_HW_ID_8822C << BIT_SHIFT_HW_ID_8822C)
+#define BIT_CLEAR_HW_ID_8822C(x) ((x) & (~BITS_HW_ID_8822C))
+#define BIT_GET_HW_ID_8822C(x) \
+ (((x) >> BIT_SHIFT_HW_ID_8822C) & BIT_MASK_HW_ID_8822C)
+#define BIT_SET_HW_ID_8822C(x, v) \
+ (BIT_CLEAR_HW_ID_8822C(x) | BIT_HW_ID_8822C(v))
+
+/* 2 REG_SYS_CFG3_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_ANAPARSW_MAC_0_8822C */
+#define BIT_OCP_L_8822C BIT(31)
+#define BIT_POWOCP_L_8822C BIT(30)
+
+#define BIT_SHIFT_CF_L_V2_8822C 28
+#define BIT_MASK_CF_L_V2_8822C 0x3
+#define BIT_CF_L_V2_8822C(x) \
+ (((x) & BIT_MASK_CF_L_V2_8822C) << BIT_SHIFT_CF_L_V2_8822C)
+#define BITS_CF_L_V2_8822C (BIT_MASK_CF_L_V2_8822C << BIT_SHIFT_CF_L_V2_8822C)
+#define BIT_CLEAR_CF_L_V2_8822C(x) ((x) & (~BITS_CF_L_V2_8822C))
+#define BIT_GET_CF_L_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_CF_L_V2_8822C) & BIT_MASK_CF_L_V2_8822C)
+#define BIT_SET_CF_L_V2_8822C(x, v) \
+ (BIT_CLEAR_CF_L_V2_8822C(x) | BIT_CF_L_V2_8822C(v))
+
+#define BIT_SHIFT_CFC_L_V2_8822C 26
+#define BIT_MASK_CFC_L_V2_8822C 0x3
+#define BIT_CFC_L_V2_8822C(x) \
+ (((x) & BIT_MASK_CFC_L_V2_8822C) << BIT_SHIFT_CFC_L_V2_8822C)
+#define BITS_CFC_L_V2_8822C \
+ (BIT_MASK_CFC_L_V2_8822C << BIT_SHIFT_CFC_L_V2_8822C)
+#define BIT_CLEAR_CFC_L_V2_8822C(x) ((x) & (~BITS_CFC_L_V2_8822C))
+#define BIT_GET_CFC_L_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_CFC_L_V2_8822C) & BIT_MASK_CFC_L_V2_8822C)
+#define BIT_SET_CFC_L_V2_8822C(x, v) \
+ (BIT_CLEAR_CFC_L_V2_8822C(x) | BIT_CFC_L_V2_8822C(v))
+
+#define BIT_SHIFT_R3_L_V2_8822C 24
+#define BIT_MASK_R3_L_V2_8822C 0x3
+#define BIT_R3_L_V2_8822C(x) \
+ (((x) & BIT_MASK_R3_L_V2_8822C) << BIT_SHIFT_R3_L_V2_8822C)
+#define BITS_R3_L_V2_8822C (BIT_MASK_R3_L_V2_8822C << BIT_SHIFT_R3_L_V2_8822C)
+#define BIT_CLEAR_R3_L_V2_8822C(x) ((x) & (~BITS_R3_L_V2_8822C))
+#define BIT_GET_R3_L_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_R3_L_V2_8822C) & BIT_MASK_R3_L_V2_8822C)
+#define BIT_SET_R3_L_V2_8822C(x, v) \
+ (BIT_CLEAR_R3_L_V2_8822C(x) | BIT_R3_L_V2_8822C(v))
+
+#define BIT_SHIFT_R2_L_8822C 22
+#define BIT_MASK_R2_L_8822C 0x3
+#define BIT_R2_L_8822C(x) (((x) & BIT_MASK_R2_L_8822C) << BIT_SHIFT_R2_L_8822C)
+#define BITS_R2_L_8822C (BIT_MASK_R2_L_8822C << BIT_SHIFT_R2_L_8822C)
+#define BIT_CLEAR_R2_L_8822C(x) ((x) & (~BITS_R2_L_8822C))
+#define BIT_GET_R2_L_8822C(x) \
+ (((x) >> BIT_SHIFT_R2_L_8822C) & BIT_MASK_R2_L_8822C)
+#define BIT_SET_R2_L_8822C(x, v) (BIT_CLEAR_R2_L_8822C(x) | BIT_R2_L_8822C(v))
+
+#define BIT_SHIFT_R1_L_8822C 20
+#define BIT_MASK_R1_L_8822C 0x3
+#define BIT_R1_L_8822C(x) (((x) & BIT_MASK_R1_L_8822C) << BIT_SHIFT_R1_L_8822C)
+#define BITS_R1_L_8822C (BIT_MASK_R1_L_8822C << BIT_SHIFT_R1_L_8822C)
+#define BIT_CLEAR_R1_L_8822C(x) ((x) & (~BITS_R1_L_8822C))
+#define BIT_GET_R1_L_8822C(x) \
+ (((x) >> BIT_SHIFT_R1_L_8822C) & BIT_MASK_R1_L_8822C)
+#define BIT_SET_R1_L_8822C(x, v) (BIT_CLEAR_R1_L_8822C(x) | BIT_R1_L_8822C(v))
+
+#define BIT_SHIFT_C3_L_8822C 18
+#define BIT_MASK_C3_L_8822C 0x3
+#define BIT_C3_L_8822C(x) (((x) & BIT_MASK_C3_L_8822C) << BIT_SHIFT_C3_L_8822C)
+#define BITS_C3_L_8822C (BIT_MASK_C3_L_8822C << BIT_SHIFT_C3_L_8822C)
+#define BIT_CLEAR_C3_L_8822C(x) ((x) & (~BITS_C3_L_8822C))
+#define BIT_GET_C3_L_8822C(x) \
+ (((x) >> BIT_SHIFT_C3_L_8822C) & BIT_MASK_C3_L_8822C)
+#define BIT_SET_C3_L_8822C(x, v) (BIT_CLEAR_C3_L_8822C(x) | BIT_C3_L_8822C(v))
+
+#define BIT_SHIFT_C2_L_8822C 16
+#define BIT_MASK_C2_L_8822C 0x3
+#define BIT_C2_L_8822C(x) (((x) & BIT_MASK_C2_L_8822C) << BIT_SHIFT_C2_L_8822C)
+#define BITS_C2_L_8822C (BIT_MASK_C2_L_8822C << BIT_SHIFT_C2_L_8822C)
+#define BIT_CLEAR_C2_L_8822C(x) ((x) & (~BITS_C2_L_8822C))
+#define BIT_GET_C2_L_8822C(x) \
+ (((x) >> BIT_SHIFT_C2_L_8822C) & BIT_MASK_C2_L_8822C)
+#define BIT_SET_C2_L_8822C(x, v) (BIT_CLEAR_C2_L_8822C(x) | BIT_C2_L_8822C(v))
+
+#define BIT_SHIFT_C1_L_V2_8822C 14
+#define BIT_MASK_C1_L_V2_8822C 0x3
+#define BIT_C1_L_V2_8822C(x) \
+ (((x) & BIT_MASK_C1_L_V2_8822C) << BIT_SHIFT_C1_L_V2_8822C)
+#define BITS_C1_L_V2_8822C (BIT_MASK_C1_L_V2_8822C << BIT_SHIFT_C1_L_V2_8822C)
+#define BIT_CLEAR_C1_L_V2_8822C(x) ((x) & (~BITS_C1_L_V2_8822C))
+#define BIT_GET_C1_L_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_C1_L_V2_8822C) & BIT_MASK_C1_L_V2_8822C)
+#define BIT_SET_C1_L_V2_8822C(x, v) \
+ (BIT_CLEAR_C1_L_V2_8822C(x) | BIT_C1_L_V2_8822C(v))
+
+#define BIT_REG_OCPS_L_V2_8822C BIT(13)
+#define BIT_REG_PWM_L_8822C BIT(12)
+
+#define BIT_SHIFT_V15ADJ_L_8822C 9
+#define BIT_MASK_V15ADJ_L_8822C 0x7
+#define BIT_V15ADJ_L_8822C(x) \
+ (((x) & BIT_MASK_V15ADJ_L_8822C) << BIT_SHIFT_V15ADJ_L_8822C)
+#define BITS_V15ADJ_L_8822C \
+ (BIT_MASK_V15ADJ_L_8822C << BIT_SHIFT_V15ADJ_L_8822C)
+#define BIT_CLEAR_V15ADJ_L_8822C(x) ((x) & (~BITS_V15ADJ_L_8822C))
+#define BIT_GET_V15ADJ_L_8822C(x) \
+ (((x) >> BIT_SHIFT_V15ADJ_L_8822C) & BIT_MASK_V15ADJ_L_8822C)
+#define BIT_SET_V15ADJ_L_8822C(x, v) \
+ (BIT_CLEAR_V15ADJ_L_8822C(x) | BIT_V15ADJ_L_8822C(v))
+
+#define BIT_SHIFT_IN_L_8822C 6
+#define BIT_MASK_IN_L_8822C 0x7
+#define BIT_IN_L_8822C(x) (((x) & BIT_MASK_IN_L_8822C) << BIT_SHIFT_IN_L_8822C)
+#define BITS_IN_L_8822C (BIT_MASK_IN_L_8822C << BIT_SHIFT_IN_L_8822C)
+#define BIT_CLEAR_IN_L_8822C(x) ((x) & (~BITS_IN_L_8822C))
+#define BIT_GET_IN_L_8822C(x) \
+ (((x) >> BIT_SHIFT_IN_L_8822C) & BIT_MASK_IN_L_8822C)
+#define BIT_SET_IN_L_8822C(x, v) (BIT_CLEAR_IN_L_8822C(x) | BIT_IN_L_8822C(v))
+
+#define BIT_SHIFT_STD_L_8822C 4
+#define BIT_MASK_STD_L_8822C 0x3
+#define BIT_STD_L_8822C(x) \
+ (((x) & BIT_MASK_STD_L_8822C) << BIT_SHIFT_STD_L_8822C)
+#define BITS_STD_L_8822C (BIT_MASK_STD_L_8822C << BIT_SHIFT_STD_L_8822C)
+#define BIT_CLEAR_STD_L_8822C(x) ((x) & (~BITS_STD_L_8822C))
+#define BIT_GET_STD_L_8822C(x) \
+ (((x) >> BIT_SHIFT_STD_L_8822C) & BIT_MASK_STD_L_8822C)
+#define BIT_SET_STD_L_8822C(x, v) \
+ (BIT_CLEAR_STD_L_8822C(x) | BIT_STD_L_8822C(v))
+
+#define BIT_SHIFT_VOL_L_8822C 0
+#define BIT_MASK_VOL_L_8822C 0xf
+#define BIT_VOL_L_8822C(x) \
+ (((x) & BIT_MASK_VOL_L_8822C) << BIT_SHIFT_VOL_L_8822C)
+#define BITS_VOL_L_8822C (BIT_MASK_VOL_L_8822C << BIT_SHIFT_VOL_L_8822C)
+#define BIT_CLEAR_VOL_L_8822C(x) ((x) & (~BITS_VOL_L_8822C))
+#define BIT_GET_VOL_L_8822C(x) \
+ (((x) >> BIT_SHIFT_VOL_L_8822C) & BIT_MASK_VOL_L_8822C)
+#define BIT_SET_VOL_L_8822C(x, v) \
+ (BIT_CLEAR_VOL_L_8822C(x) | BIT_VOL_L_8822C(v))
+
+/* 2 REG_ANAPARSW_MAC_1_8822C */
+
+#define BIT_SHIFT_OCP_L_PFM_8822C 29
+#define BIT_MASK_OCP_L_PFM_8822C 0x7
+#define BIT_OCP_L_PFM_8822C(x) \
+ (((x) & BIT_MASK_OCP_L_PFM_8822C) << BIT_SHIFT_OCP_L_PFM_8822C)
+#define BITS_OCP_L_PFM_8822C \
+ (BIT_MASK_OCP_L_PFM_8822C << BIT_SHIFT_OCP_L_PFM_8822C)
+#define BIT_CLEAR_OCP_L_PFM_8822C(x) ((x) & (~BITS_OCP_L_PFM_8822C))
+#define BIT_GET_OCP_L_PFM_8822C(x) \
+ (((x) >> BIT_SHIFT_OCP_L_PFM_8822C) & BIT_MASK_OCP_L_PFM_8822C)
+#define BIT_SET_OCP_L_PFM_8822C(x, v) \
+ (BIT_CLEAR_OCP_L_PFM_8822C(x) | BIT_OCP_L_PFM_8822C(v))
+
+#define BIT_SHIFT_CFC_L_PFM_8822C 27
+#define BIT_MASK_CFC_L_PFM_8822C 0x3
+#define BIT_CFC_L_PFM_8822C(x) \
+ (((x) & BIT_MASK_CFC_L_PFM_8822C) << BIT_SHIFT_CFC_L_PFM_8822C)
+#define BITS_CFC_L_PFM_8822C \
+ (BIT_MASK_CFC_L_PFM_8822C << BIT_SHIFT_CFC_L_PFM_8822C)
+#define BIT_CLEAR_CFC_L_PFM_8822C(x) ((x) & (~BITS_CFC_L_PFM_8822C))
+#define BIT_GET_CFC_L_PFM_8822C(x) \
+ (((x) >> BIT_SHIFT_CFC_L_PFM_8822C) & BIT_MASK_CFC_L_PFM_8822C)
+#define BIT_SET_CFC_L_PFM_8822C(x, v) \
+ (BIT_CLEAR_CFC_L_PFM_8822C(x) | BIT_CFC_L_PFM_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_REG_FREQ_L_V1_8822C 20
+#define BIT_MASK_REG_FREQ_L_V1_8822C 0x7
+#define BIT_REG_FREQ_L_V1_8822C(x) \
+ (((x) & BIT_MASK_REG_FREQ_L_V1_8822C) << BIT_SHIFT_REG_FREQ_L_V1_8822C)
+#define BITS_REG_FREQ_L_V1_8822C \
+ (BIT_MASK_REG_FREQ_L_V1_8822C << BIT_SHIFT_REG_FREQ_L_V1_8822C)
+#define BIT_CLEAR_REG_FREQ_L_V1_8822C(x) ((x) & (~BITS_REG_FREQ_L_V1_8822C))
+#define BIT_GET_REG_FREQ_L_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_REG_FREQ_L_V1_8822C) & BIT_MASK_REG_FREQ_L_V1_8822C)
+#define BIT_SET_REG_FREQ_L_V1_8822C(x, v) \
+ (BIT_CLEAR_REG_FREQ_L_V1_8822C(x) | BIT_REG_FREQ_L_V1_8822C(v))
+
+#define BIT_EN_DUTY_8822C BIT(19)
+
+#define BIT_SHIFT_REG_MODE_V2_8822C 17
+#define BIT_MASK_REG_MODE_V2_8822C 0x3
+#define BIT_REG_MODE_V2_8822C(x) \
+ (((x) & BIT_MASK_REG_MODE_V2_8822C) << BIT_SHIFT_REG_MODE_V2_8822C)
+#define BITS_REG_MODE_V2_8822C \
+ (BIT_MASK_REG_MODE_V2_8822C << BIT_SHIFT_REG_MODE_V2_8822C)
+#define BIT_CLEAR_REG_MODE_V2_8822C(x) ((x) & (~BITS_REG_MODE_V2_8822C))
+#define BIT_GET_REG_MODE_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_REG_MODE_V2_8822C) & BIT_MASK_REG_MODE_V2_8822C)
+#define BIT_SET_REG_MODE_V2_8822C(x, v) \
+ (BIT_CLEAR_REG_MODE_V2_8822C(x) | BIT_REG_MODE_V2_8822C(v))
+
+#define BIT_EN_SP_8822C BIT(16)
+#define BIT_REG_AUTO_L_V2_8822C BIT(15)
+#define BIT_REG_LDOF_L_V2_8822C BIT(14)
+#define BIT_REG_TYPE_L_V2_8822C BIT(13)
+#define BIT_VO15_V1P05_H_8822C BIT(12)
+#define BIT_ARENB_L_V2_8822C BIT(11)
+
+#define BIT_SHIFT_TBOX_L1_V2_8822C 9
+#define BIT_MASK_TBOX_L1_V2_8822C 0x3
+#define BIT_TBOX_L1_V2_8822C(x) \
+ (((x) & BIT_MASK_TBOX_L1_V2_8822C) << BIT_SHIFT_TBOX_L1_V2_8822C)
+#define BITS_TBOX_L1_V2_8822C \
+ (BIT_MASK_TBOX_L1_V2_8822C << BIT_SHIFT_TBOX_L1_V2_8822C)
+#define BIT_CLEAR_TBOX_L1_V2_8822C(x) ((x) & (~BITS_TBOX_L1_V2_8822C))
+#define BIT_GET_TBOX_L1_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_TBOX_L1_V2_8822C) & BIT_MASK_TBOX_L1_V2_8822C)
+#define BIT_SET_TBOX_L1_V2_8822C(x, v) \
+ (BIT_CLEAR_TBOX_L1_V2_8822C(x) | BIT_TBOX_L1_V2_8822C(v))
+
+#define BIT_SHIFT_REG_DELAY_L_8822C 7
+#define BIT_MASK_REG_DELAY_L_8822C 0x3
+#define BIT_REG_DELAY_L_8822C(x) \
+ (((x) & BIT_MASK_REG_DELAY_L_8822C) << BIT_SHIFT_REG_DELAY_L_8822C)
+#define BITS_REG_DELAY_L_8822C \
+ (BIT_MASK_REG_DELAY_L_8822C << BIT_SHIFT_REG_DELAY_L_8822C)
+#define BIT_CLEAR_REG_DELAY_L_8822C(x) ((x) & (~BITS_REG_DELAY_L_8822C))
+#define BIT_GET_REG_DELAY_L_8822C(x) \
+ (((x) >> BIT_SHIFT_REG_DELAY_L_8822C) & BIT_MASK_REG_DELAY_L_8822C)
+#define BIT_SET_REG_DELAY_L_8822C(x, v) \
+ (BIT_CLEAR_REG_DELAY_L_8822C(x) | BIT_REG_DELAY_L_8822C(v))
+
+#define BIT_REG_CLAMP_D_L_8822C BIT(6)
+#define BIT_REG_BYPASS_L_V2_8822C BIT(5)
+#define BIT_REG_AUTOZCD_L_8822C BIT(4)
+#define BIT_POW_ZCD_L_V2_8822C BIT(3)
+#define BIT_REG_HALF_L_8822C BIT(2)
+
+#define BIT_SHIFT_OCP_L_V2_8822C 0
+#define BIT_MASK_OCP_L_V2_8822C 0x3
+#define BIT_OCP_L_V2_8822C(x) \
+ (((x) & BIT_MASK_OCP_L_V2_8822C) << BIT_SHIFT_OCP_L_V2_8822C)
+#define BITS_OCP_L_V2_8822C \
+ (BIT_MASK_OCP_L_V2_8822C << BIT_SHIFT_OCP_L_V2_8822C)
+#define BIT_CLEAR_OCP_L_V2_8822C(x) ((x) & (~BITS_OCP_L_V2_8822C))
+#define BIT_GET_OCP_L_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_OCP_L_V2_8822C) & BIT_MASK_OCP_L_V2_8822C)
+#define BIT_SET_OCP_L_V2_8822C(x, v) \
+ (BIT_CLEAR_OCP_L_V2_8822C(x) | BIT_OCP_L_V2_8822C(v))
+
+/* 2 REG_ANAPAR_MAC_0_8822C */
+
+#define BIT_SHIFT_REG_LPF_R3_8822C 29
+#define BIT_MASK_REG_LPF_R3_8822C 0x7
+#define BIT_REG_LPF_R3_8822C(x) \
+ (((x) & BIT_MASK_REG_LPF_R3_8822C) << BIT_SHIFT_REG_LPF_R3_8822C)
+#define BITS_REG_LPF_R3_8822C \
+ (BIT_MASK_REG_LPF_R3_8822C << BIT_SHIFT_REG_LPF_R3_8822C)
+#define BIT_CLEAR_REG_LPF_R3_8822C(x) ((x) & (~BITS_REG_LPF_R3_8822C))
+#define BIT_GET_REG_LPF_R3_8822C(x) \
+ (((x) >> BIT_SHIFT_REG_LPF_R3_8822C) & BIT_MASK_REG_LPF_R3_8822C)
+#define BIT_SET_REG_LPF_R3_8822C(x, v) \
+ (BIT_CLEAR_REG_LPF_R3_8822C(x) | BIT_REG_LPF_R3_8822C(v))
+
+#define BIT_SHIFT_REG_LPF_R2_8822C 24
+#define BIT_MASK_REG_LPF_R2_8822C 0x1f
+#define BIT_REG_LPF_R2_8822C(x) \
+ (((x) & BIT_MASK_REG_LPF_R2_8822C) << BIT_SHIFT_REG_LPF_R2_8822C)
+#define BITS_REG_LPF_R2_8822C \
+ (BIT_MASK_REG_LPF_R2_8822C << BIT_SHIFT_REG_LPF_R2_8822C)
+#define BIT_CLEAR_REG_LPF_R2_8822C(x) ((x) & (~BITS_REG_LPF_R2_8822C))
+#define BIT_GET_REG_LPF_R2_8822C(x) \
+ (((x) >> BIT_SHIFT_REG_LPF_R2_8822C) & BIT_MASK_REG_LPF_R2_8822C)
+#define BIT_SET_REG_LPF_R2_8822C(x, v) \
+ (BIT_CLEAR_REG_LPF_R2_8822C(x) | BIT_REG_LPF_R2_8822C(v))
+
+#define BIT_SHIFT_REG_LPF_C3_8822C 21
+#define BIT_MASK_REG_LPF_C3_8822C 0x7
+#define BIT_REG_LPF_C3_8822C(x) \
+ (((x) & BIT_MASK_REG_LPF_C3_8822C) << BIT_SHIFT_REG_LPF_C3_8822C)
+#define BITS_REG_LPF_C3_8822C \
+ (BIT_MASK_REG_LPF_C3_8822C << BIT_SHIFT_REG_LPF_C3_8822C)
+#define BIT_CLEAR_REG_LPF_C3_8822C(x) ((x) & (~BITS_REG_LPF_C3_8822C))
+#define BIT_GET_REG_LPF_C3_8822C(x) \
+ (((x) >> BIT_SHIFT_REG_LPF_C3_8822C) & BIT_MASK_REG_LPF_C3_8822C)
+#define BIT_SET_REG_LPF_C3_8822C(x, v) \
+ (BIT_CLEAR_REG_LPF_C3_8822C(x) | BIT_REG_LPF_C3_8822C(v))
+
+#define BIT_SHIFT_REG_LPF_C2_8822C 18
+#define BIT_MASK_REG_LPF_C2_8822C 0x7
+#define BIT_REG_LPF_C2_8822C(x) \
+ (((x) & BIT_MASK_REG_LPF_C2_8822C) << BIT_SHIFT_REG_LPF_C2_8822C)
+#define BITS_REG_LPF_C2_8822C \
+ (BIT_MASK_REG_LPF_C2_8822C << BIT_SHIFT_REG_LPF_C2_8822C)
+#define BIT_CLEAR_REG_LPF_C2_8822C(x) ((x) & (~BITS_REG_LPF_C2_8822C))
+#define BIT_GET_REG_LPF_C2_8822C(x) \
+ (((x) >> BIT_SHIFT_REG_LPF_C2_8822C) & BIT_MASK_REG_LPF_C2_8822C)
+#define BIT_SET_REG_LPF_C2_8822C(x, v) \
+ (BIT_CLEAR_REG_LPF_C2_8822C(x) | BIT_REG_LPF_C2_8822C(v))
+
+#define BIT_SHIFT_REG_LPF_C1_8822C 15
+#define BIT_MASK_REG_LPF_C1_8822C 0x7
+#define BIT_REG_LPF_C1_8822C(x) \
+ (((x) & BIT_MASK_REG_LPF_C1_8822C) << BIT_SHIFT_REG_LPF_C1_8822C)
+#define BITS_REG_LPF_C1_8822C \
+ (BIT_MASK_REG_LPF_C1_8822C << BIT_SHIFT_REG_LPF_C1_8822C)
+#define BIT_CLEAR_REG_LPF_C1_8822C(x) ((x) & (~BITS_REG_LPF_C1_8822C))
+#define BIT_GET_REG_LPF_C1_8822C(x) \
+ (((x) >> BIT_SHIFT_REG_LPF_C1_8822C) & BIT_MASK_REG_LPF_C1_8822C)
+#define BIT_SET_REG_LPF_C1_8822C(x, v) \
+ (BIT_CLEAR_REG_LPF_C1_8822C(x) | BIT_REG_LPF_C1_8822C(v))
+
+#define BIT_SHIFT_REG_LDO_SEL_V1_8822C 13
+#define BIT_MASK_REG_LDO_SEL_V1_8822C 0x3
+#define BIT_REG_LDO_SEL_V1_8822C(x) \
+ (((x) & BIT_MASK_REG_LDO_SEL_V1_8822C) \
+ << BIT_SHIFT_REG_LDO_SEL_V1_8822C)
+#define BITS_REG_LDO_SEL_V1_8822C \
+ (BIT_MASK_REG_LDO_SEL_V1_8822C << BIT_SHIFT_REG_LDO_SEL_V1_8822C)
+#define BIT_CLEAR_REG_LDO_SEL_V1_8822C(x) ((x) & (~BITS_REG_LDO_SEL_V1_8822C))
+#define BIT_GET_REG_LDO_SEL_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_REG_LDO_SEL_V1_8822C) & \
+ BIT_MASK_REG_LDO_SEL_V1_8822C)
+#define BIT_SET_REG_LDO_SEL_V1_8822C(x, v) \
+ (BIT_CLEAR_REG_LDO_SEL_V1_8822C(x) | BIT_REG_LDO_SEL_V1_8822C(v))
+
+#define BIT_REG_CP_ICPX2_8822C BIT(12)
+
+#define BIT_SHIFT_REG_CP_ICP_SEL_FAST_8822C 9
+#define BIT_MASK_REG_CP_ICP_SEL_FAST_8822C 0x7
+#define BIT_REG_CP_ICP_SEL_FAST_8822C(x) \
+ (((x) & BIT_MASK_REG_CP_ICP_SEL_FAST_8822C) \
+ << BIT_SHIFT_REG_CP_ICP_SEL_FAST_8822C)
+#define BITS_REG_CP_ICP_SEL_FAST_8822C \
+ (BIT_MASK_REG_CP_ICP_SEL_FAST_8822C \
+ << BIT_SHIFT_REG_CP_ICP_SEL_FAST_8822C)
+#define BIT_CLEAR_REG_CP_ICP_SEL_FAST_8822C(x) \
+ ((x) & (~BITS_REG_CP_ICP_SEL_FAST_8822C))
+#define BIT_GET_REG_CP_ICP_SEL_FAST_8822C(x) \
+ (((x) >> BIT_SHIFT_REG_CP_ICP_SEL_FAST_8822C) & \
+ BIT_MASK_REG_CP_ICP_SEL_FAST_8822C)
+#define BIT_SET_REG_CP_ICP_SEL_FAST_8822C(x, v) \
+ (BIT_CLEAR_REG_CP_ICP_SEL_FAST_8822C(x) | \
+ BIT_REG_CP_ICP_SEL_FAST_8822C(v))
+
+#define BIT_SHIFT_REG_CP_ICP_SEL_8822C 6
+#define BIT_MASK_REG_CP_ICP_SEL_8822C 0x7
+#define BIT_REG_CP_ICP_SEL_8822C(x) \
+ (((x) & BIT_MASK_REG_CP_ICP_SEL_8822C) \
+ << BIT_SHIFT_REG_CP_ICP_SEL_8822C)
+#define BITS_REG_CP_ICP_SEL_8822C \
+ (BIT_MASK_REG_CP_ICP_SEL_8822C << BIT_SHIFT_REG_CP_ICP_SEL_8822C)
+#define BIT_CLEAR_REG_CP_ICP_SEL_8822C(x) ((x) & (~BITS_REG_CP_ICP_SEL_8822C))
+#define BIT_GET_REG_CP_ICP_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_REG_CP_ICP_SEL_8822C) & \
+ BIT_MASK_REG_CP_ICP_SEL_8822C)
+#define BIT_SET_REG_CP_ICP_SEL_8822C(x, v) \
+ (BIT_CLEAR_REG_CP_ICP_SEL_8822C(x) | BIT_REG_CP_ICP_SEL_8822C(v))
+
+#define BIT_SHIFT_REG_IB_PI_8822C 4
+#define BIT_MASK_REG_IB_PI_8822C 0x3
+#define BIT_REG_IB_PI_8822C(x) \
+ (((x) & BIT_MASK_REG_IB_PI_8822C) << BIT_SHIFT_REG_IB_PI_8822C)
+#define BITS_REG_IB_PI_8822C \
+ (BIT_MASK_REG_IB_PI_8822C << BIT_SHIFT_REG_IB_PI_8822C)
+#define BIT_CLEAR_REG_IB_PI_8822C(x) ((x) & (~BITS_REG_IB_PI_8822C))
+#define BIT_GET_REG_IB_PI_8822C(x) \
+ (((x) >> BIT_SHIFT_REG_IB_PI_8822C) & BIT_MASK_REG_IB_PI_8822C)
+#define BIT_SET_REG_IB_PI_8822C(x, v) \
+ (BIT_CLEAR_REG_IB_PI_8822C(x) | BIT_REG_IB_PI_8822C(v))
+
+#define BIT_LDO2PWRCUT_8822C BIT(3)
+#define BIT_VPULSE_LDO_8822C BIT(2)
+
+#define BIT_SHIFT_LDO_VSEL_8822C 0
+#define BIT_MASK_LDO_VSEL_8822C 0x3
+#define BIT_LDO_VSEL_8822C(x) \
+ (((x) & BIT_MASK_LDO_VSEL_8822C) << BIT_SHIFT_LDO_VSEL_8822C)
+#define BITS_LDO_VSEL_8822C \
+ (BIT_MASK_LDO_VSEL_8822C << BIT_SHIFT_LDO_VSEL_8822C)
+#define BIT_CLEAR_LDO_VSEL_8822C(x) ((x) & (~BITS_LDO_VSEL_8822C))
+#define BIT_GET_LDO_VSEL_8822C(x) \
+ (((x) >> BIT_SHIFT_LDO_VSEL_8822C) & BIT_MASK_LDO_VSEL_8822C)
+#define BIT_SET_LDO_VSEL_8822C(x, v) \
+ (BIT_CLEAR_LDO_VSEL_8822C(x) | BIT_LDO_VSEL_8822C(v))
+
+/* 2 REG_ANAPAR_MAC_1_8822C */
+
+#define BIT_SHIFT_REG_CK_MON_SEL_8822C 29
+#define BIT_MASK_REG_CK_MON_SEL_8822C 0x7
+#define BIT_REG_CK_MON_SEL_8822C(x) \
+ (((x) & BIT_MASK_REG_CK_MON_SEL_8822C) \
+ << BIT_SHIFT_REG_CK_MON_SEL_8822C)
+#define BITS_REG_CK_MON_SEL_8822C \
+ (BIT_MASK_REG_CK_MON_SEL_8822C << BIT_SHIFT_REG_CK_MON_SEL_8822C)
+#define BIT_CLEAR_REG_CK_MON_SEL_8822C(x) ((x) & (~BITS_REG_CK_MON_SEL_8822C))
+#define BIT_GET_REG_CK_MON_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_REG_CK_MON_SEL_8822C) & \
+ BIT_MASK_REG_CK_MON_SEL_8822C)
+#define BIT_SET_REG_CK_MON_SEL_8822C(x, v) \
+ (BIT_CLEAR_REG_CK_MON_SEL_8822C(x) | BIT_REG_CK_MON_SEL_8822C(v))
+
+#define BIT_REG_CK_MON_EN_8822C BIT(28)
+#define BIT_REG_XTAL_FREQ_SEL_8822C BIT(27)
+#define BIT_REG_XTAL_EDGE_SEL_8822C BIT(26)
+#define BIT_REG_VCO_KVCO_8822C BIT(25)
+#define BIT_REG_SDM_EDGE_SEL_8822C BIT(24)
+#define BIT_REG_SDM_CK_SEL_8822C BIT(23)
+#define BIT_REG_SDM_CK_GATED_8822C BIT(22)
+#define BIT_REG_PFD_RESET_GATED_8822C BIT(21)
+
+#define BIT_SHIFT_REG_LPF_R3_FAST_8822C 16
+#define BIT_MASK_REG_LPF_R3_FAST_8822C 0x1f
+#define BIT_REG_LPF_R3_FAST_8822C(x) \
+ (((x) & BIT_MASK_REG_LPF_R3_FAST_8822C) \
+ << BIT_SHIFT_REG_LPF_R3_FAST_8822C)
+#define BITS_REG_LPF_R3_FAST_8822C \
+ (BIT_MASK_REG_LPF_R3_FAST_8822C << BIT_SHIFT_REG_LPF_R3_FAST_8822C)
+#define BIT_CLEAR_REG_LPF_R3_FAST_8822C(x) ((x) & (~BITS_REG_LPF_R3_FAST_8822C))
+#define BIT_GET_REG_LPF_R3_FAST_8822C(x) \
+ (((x) >> BIT_SHIFT_REG_LPF_R3_FAST_8822C) & \
+ BIT_MASK_REG_LPF_R3_FAST_8822C)
+#define BIT_SET_REG_LPF_R3_FAST_8822C(x, v) \
+ (BIT_CLEAR_REG_LPF_R3_FAST_8822C(x) | BIT_REG_LPF_R3_FAST_8822C(v))
+
+#define BIT_SHIFT_REG_LPF_R2_FAST_8822C 11
+#define BIT_MASK_REG_LPF_R2_FAST_8822C 0x1f
+#define BIT_REG_LPF_R2_FAST_8822C(x) \
+ (((x) & BIT_MASK_REG_LPF_R2_FAST_8822C) \
+ << BIT_SHIFT_REG_LPF_R2_FAST_8822C)
+#define BITS_REG_LPF_R2_FAST_8822C \
+ (BIT_MASK_REG_LPF_R2_FAST_8822C << BIT_SHIFT_REG_LPF_R2_FAST_8822C)
+#define BIT_CLEAR_REG_LPF_R2_FAST_8822C(x) ((x) & (~BITS_REG_LPF_R2_FAST_8822C))
+#define BIT_GET_REG_LPF_R2_FAST_8822C(x) \
+ (((x) >> BIT_SHIFT_REG_LPF_R2_FAST_8822C) & \
+ BIT_MASK_REG_LPF_R2_FAST_8822C)
+#define BIT_SET_REG_LPF_R2_FAST_8822C(x, v) \
+ (BIT_CLEAR_REG_LPF_R2_FAST_8822C(x) | BIT_REG_LPF_R2_FAST_8822C(v))
+
+#define BIT_SHIFT_REG_LPF_C3_FAST_8822C 8
+#define BIT_MASK_REG_LPF_C3_FAST_8822C 0x7
+#define BIT_REG_LPF_C3_FAST_8822C(x) \
+ (((x) & BIT_MASK_REG_LPF_C3_FAST_8822C) \
+ << BIT_SHIFT_REG_LPF_C3_FAST_8822C)
+#define BITS_REG_LPF_C3_FAST_8822C \
+ (BIT_MASK_REG_LPF_C3_FAST_8822C << BIT_SHIFT_REG_LPF_C3_FAST_8822C)
+#define BIT_CLEAR_REG_LPF_C3_FAST_8822C(x) ((x) & (~BITS_REG_LPF_C3_FAST_8822C))
+#define BIT_GET_REG_LPF_C3_FAST_8822C(x) \
+ (((x) >> BIT_SHIFT_REG_LPF_C3_FAST_8822C) & \
+ BIT_MASK_REG_LPF_C3_FAST_8822C)
+#define BIT_SET_REG_LPF_C3_FAST_8822C(x, v) \
+ (BIT_CLEAR_REG_LPF_C3_FAST_8822C(x) | BIT_REG_LPF_C3_FAST_8822C(v))
+
+#define BIT_SHIFT_REG_LPF_C2_FAST_8822C 5
+#define BIT_MASK_REG_LPF_C2_FAST_8822C 0x7
+#define BIT_REG_LPF_C2_FAST_8822C(x) \
+ (((x) & BIT_MASK_REG_LPF_C2_FAST_8822C) \
+ << BIT_SHIFT_REG_LPF_C2_FAST_8822C)
+#define BITS_REG_LPF_C2_FAST_8822C \
+ (BIT_MASK_REG_LPF_C2_FAST_8822C << BIT_SHIFT_REG_LPF_C2_FAST_8822C)
+#define BIT_CLEAR_REG_LPF_C2_FAST_8822C(x) ((x) & (~BITS_REG_LPF_C2_FAST_8822C))
+#define BIT_GET_REG_LPF_C2_FAST_8822C(x) \
+ (((x) >> BIT_SHIFT_REG_LPF_C2_FAST_8822C) & \
+ BIT_MASK_REG_LPF_C2_FAST_8822C)
+#define BIT_SET_REG_LPF_C2_FAST_8822C(x, v) \
+ (BIT_CLEAR_REG_LPF_C2_FAST_8822C(x) | BIT_REG_LPF_C2_FAST_8822C(v))
+
+#define BIT_SHIFT_REG_LPF_C1_FAST_8822C 2
+#define BIT_MASK_REG_LPF_C1_FAST_8822C 0x7
+#define BIT_REG_LPF_C1_FAST_8822C(x) \
+ (((x) & BIT_MASK_REG_LPF_C1_FAST_8822C) \
+ << BIT_SHIFT_REG_LPF_C1_FAST_8822C)
+#define BITS_REG_LPF_C1_FAST_8822C \
+ (BIT_MASK_REG_LPF_C1_FAST_8822C << BIT_SHIFT_REG_LPF_C1_FAST_8822C)
+#define BIT_CLEAR_REG_LPF_C1_FAST_8822C(x) ((x) & (~BITS_REG_LPF_C1_FAST_8822C))
+#define BIT_GET_REG_LPF_C1_FAST_8822C(x) \
+ (((x) >> BIT_SHIFT_REG_LPF_C1_FAST_8822C) & \
+ BIT_MASK_REG_LPF_C1_FAST_8822C)
+#define BIT_SET_REG_LPF_C1_FAST_8822C(x, v) \
+ (BIT_CLEAR_REG_LPF_C1_FAST_8822C(x) | BIT_REG_LPF_C1_FAST_8822C(v))
+
+#define BIT_SHIFT_REG_LPF_R3_V1_8822C 0
+#define BIT_MASK_REG_LPF_R3_V1_8822C 0x3
+#define BIT_REG_LPF_R3_V1_8822C(x) \
+ (((x) & BIT_MASK_REG_LPF_R3_V1_8822C) << BIT_SHIFT_REG_LPF_R3_V1_8822C)
+#define BITS_REG_LPF_R3_V1_8822C \
+ (BIT_MASK_REG_LPF_R3_V1_8822C << BIT_SHIFT_REG_LPF_R3_V1_8822C)
+#define BIT_CLEAR_REG_LPF_R3_V1_8822C(x) ((x) & (~BITS_REG_LPF_R3_V1_8822C))
+#define BIT_GET_REG_LPF_R3_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_REG_LPF_R3_V1_8822C) & BIT_MASK_REG_LPF_R3_V1_8822C)
+#define BIT_SET_REG_LPF_R3_V1_8822C(x, v) \
+ (BIT_CLEAR_REG_LPF_R3_V1_8822C(x) | BIT_REG_LPF_R3_V1_8822C(v))
+
+/* 2 REG_ANAPAR_MAC_2_8822C */
+
+#define BIT_SHIFT_AGPIO_DRV_V1_8822C 30
+#define BIT_MASK_AGPIO_DRV_V1_8822C 0x3
+#define BIT_AGPIO_DRV_V1_8822C(x) \
+ (((x) & BIT_MASK_AGPIO_DRV_V1_8822C) << BIT_SHIFT_AGPIO_DRV_V1_8822C)
+#define BITS_AGPIO_DRV_V1_8822C \
+ (BIT_MASK_AGPIO_DRV_V1_8822C << BIT_SHIFT_AGPIO_DRV_V1_8822C)
+#define BIT_CLEAR_AGPIO_DRV_V1_8822C(x) ((x) & (~BITS_AGPIO_DRV_V1_8822C))
+#define BIT_GET_AGPIO_DRV_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_AGPIO_DRV_V1_8822C) & BIT_MASK_AGPIO_DRV_V1_8822C)
+#define BIT_SET_AGPIO_DRV_V1_8822C(x, v) \
+ (BIT_CLEAR_AGPIO_DRV_V1_8822C(x) | BIT_AGPIO_DRV_V1_8822C(v))
+
+#define BIT_AGPIO_GPO_V1_8822C BIT(29)
+#define BIT_AGPIO_GPE_V1_8822C BIT(28)
+#define BIT_SEL_CLK_8822C BIT(27)
+
+#define BIT_SHIFT_LS_XTAL_SEL_8822C 23
+#define BIT_MASK_LS_XTAL_SEL_8822C 0xf
+#define BIT_LS_XTAL_SEL_8822C(x) \
+ (((x) & BIT_MASK_LS_XTAL_SEL_8822C) << BIT_SHIFT_LS_XTAL_SEL_8822C)
+#define BITS_LS_XTAL_SEL_8822C \
+ (BIT_MASK_LS_XTAL_SEL_8822C << BIT_SHIFT_LS_XTAL_SEL_8822C)
+#define BIT_CLEAR_LS_XTAL_SEL_8822C(x) ((x) & (~BITS_LS_XTAL_SEL_8822C))
+#define BIT_GET_LS_XTAL_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_LS_XTAL_SEL_8822C) & BIT_MASK_LS_XTAL_SEL_8822C)
+#define BIT_SET_LS_XTAL_SEL_8822C(x, v) \
+ (BIT_CLEAR_LS_XTAL_SEL_8822C(x) | BIT_LS_XTAL_SEL_8822C(v))
+
+#define BIT_LS_SDM_ORDER_V1_8822C BIT(22)
+#define BIT_LS_DELAY_PH_8822C BIT(21)
+#define BIT_DIVIDER_SEL_8822C BIT(20)
+
+#define BIT_SHIFT_PCODE_8822C 15
+#define BIT_MASK_PCODE_8822C 0x1f
+#define BIT_PCODE_8822C(x) \
+ (((x) & BIT_MASK_PCODE_8822C) << BIT_SHIFT_PCODE_8822C)
+#define BITS_PCODE_8822C (BIT_MASK_PCODE_8822C << BIT_SHIFT_PCODE_8822C)
+#define BIT_CLEAR_PCODE_8822C(x) ((x) & (~BITS_PCODE_8822C))
+#define BIT_GET_PCODE_8822C(x) \
+ (((x) >> BIT_SHIFT_PCODE_8822C) & BIT_MASK_PCODE_8822C)
+#define BIT_SET_PCODE_8822C(x, v) \
+ (BIT_CLEAR_PCODE_8822C(x) | BIT_PCODE_8822C(v))
+
+#define BIT_SHIFT_NCODE_8822C 7
+#define BIT_MASK_NCODE_8822C 0xff
+#define BIT_NCODE_8822C(x) \
+ (((x) & BIT_MASK_NCODE_8822C) << BIT_SHIFT_NCODE_8822C)
+#define BITS_NCODE_8822C (BIT_MASK_NCODE_8822C << BIT_SHIFT_NCODE_8822C)
+#define BIT_CLEAR_NCODE_8822C(x) ((x) & (~BITS_NCODE_8822C))
+#define BIT_GET_NCODE_8822C(x) \
+ (((x) >> BIT_SHIFT_NCODE_8822C) & BIT_MASK_NCODE_8822C)
+#define BIT_SET_NCODE_8822C(x, v) \
+ (BIT_CLEAR_NCODE_8822C(x) | BIT_NCODE_8822C(v))
+
+#define BIT_REG_BEACON_8822C BIT(6)
+#define BIT_REG_MBIASE_8822C BIT(5)
+
+#define BIT_SHIFT_REG_FAST_SEL_8822C 3
+#define BIT_MASK_REG_FAST_SEL_8822C 0x3
+#define BIT_REG_FAST_SEL_8822C(x) \
+ (((x) & BIT_MASK_REG_FAST_SEL_8822C) << BIT_SHIFT_REG_FAST_SEL_8822C)
+#define BITS_REG_FAST_SEL_8822C \
+ (BIT_MASK_REG_FAST_SEL_8822C << BIT_SHIFT_REG_FAST_SEL_8822C)
+#define BIT_CLEAR_REG_FAST_SEL_8822C(x) ((x) & (~BITS_REG_FAST_SEL_8822C))
+#define BIT_GET_REG_FAST_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_REG_FAST_SEL_8822C) & BIT_MASK_REG_FAST_SEL_8822C)
+#define BIT_SET_REG_FAST_SEL_8822C(x, v) \
+ (BIT_CLEAR_REG_FAST_SEL_8822C(x) | BIT_REG_FAST_SEL_8822C(v))
+
+#define BIT_REG_CK960M_EN_8822C BIT(2)
+#define BIT_REG_CK320M_EN_8822C BIT(1)
+#define BIT_REG_CK_5M_EN_8822C BIT(0)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_ANAPAR_XTAL_0_8822C */
+#define BIT_XTAL_SC_LPS_8822C BIT(31)
+
+#define BIT_SHIFT_XTAL_SC_INIT_8822C 24
+#define BIT_MASK_XTAL_SC_INIT_8822C 0x7f
+#define BIT_XTAL_SC_INIT_8822C(x) \
+ (((x) & BIT_MASK_XTAL_SC_INIT_8822C) << BIT_SHIFT_XTAL_SC_INIT_8822C)
+#define BITS_XTAL_SC_INIT_8822C \
+ (BIT_MASK_XTAL_SC_INIT_8822C << BIT_SHIFT_XTAL_SC_INIT_8822C)
+#define BIT_CLEAR_XTAL_SC_INIT_8822C(x) ((x) & (~BITS_XTAL_SC_INIT_8822C))
+#define BIT_GET_XTAL_SC_INIT_8822C(x) \
+ (((x) >> BIT_SHIFT_XTAL_SC_INIT_8822C) & BIT_MASK_XTAL_SC_INIT_8822C)
+#define BIT_SET_XTAL_SC_INIT_8822C(x, v) \
+ (BIT_CLEAR_XTAL_SC_INIT_8822C(x) | BIT_XTAL_SC_INIT_8822C(v))
+
+#define BIT_SHIFT_XTAL_SC_XO_8822C 17
+#define BIT_MASK_XTAL_SC_XO_8822C 0x7f
+#define BIT_XTAL_SC_XO_8822C(x) \
+ (((x) & BIT_MASK_XTAL_SC_XO_8822C) << BIT_SHIFT_XTAL_SC_XO_8822C)
+#define BITS_XTAL_SC_XO_8822C \
+ (BIT_MASK_XTAL_SC_XO_8822C << BIT_SHIFT_XTAL_SC_XO_8822C)
+#define BIT_CLEAR_XTAL_SC_XO_8822C(x) ((x) & (~BITS_XTAL_SC_XO_8822C))
+#define BIT_GET_XTAL_SC_XO_8822C(x) \
+ (((x) >> BIT_SHIFT_XTAL_SC_XO_8822C) & BIT_MASK_XTAL_SC_XO_8822C)
+#define BIT_SET_XTAL_SC_XO_8822C(x, v) \
+ (BIT_CLEAR_XTAL_SC_XO_8822C(x) | BIT_XTAL_SC_XO_8822C(v))
+
+#define BIT_SHIFT_XTAL_SC_XI_8822C 10
+#define BIT_MASK_XTAL_SC_XI_8822C 0x7f
+#define BIT_XTAL_SC_XI_8822C(x) \
+ (((x) & BIT_MASK_XTAL_SC_XI_8822C) << BIT_SHIFT_XTAL_SC_XI_8822C)
+#define BITS_XTAL_SC_XI_8822C \
+ (BIT_MASK_XTAL_SC_XI_8822C << BIT_SHIFT_XTAL_SC_XI_8822C)
+#define BIT_CLEAR_XTAL_SC_XI_8822C(x) ((x) & (~BITS_XTAL_SC_XI_8822C))
+#define BIT_GET_XTAL_SC_XI_8822C(x) \
+ (((x) >> BIT_SHIFT_XTAL_SC_XI_8822C) & BIT_MASK_XTAL_SC_XI_8822C)
+#define BIT_SET_XTAL_SC_XI_8822C(x, v) \
+ (BIT_CLEAR_XTAL_SC_XI_8822C(x) | BIT_XTAL_SC_XI_8822C(v))
+
+#define BIT_SHIFT_XTAL_GMN_V3_8822C 5
+#define BIT_MASK_XTAL_GMN_V3_8822C 0x1f
+#define BIT_XTAL_GMN_V3_8822C(x) \
+ (((x) & BIT_MASK_XTAL_GMN_V3_8822C) << BIT_SHIFT_XTAL_GMN_V3_8822C)
+#define BITS_XTAL_GMN_V3_8822C \
+ (BIT_MASK_XTAL_GMN_V3_8822C << BIT_SHIFT_XTAL_GMN_V3_8822C)
+#define BIT_CLEAR_XTAL_GMN_V3_8822C(x) ((x) & (~BITS_XTAL_GMN_V3_8822C))
+#define BIT_GET_XTAL_GMN_V3_8822C(x) \
+ (((x) >> BIT_SHIFT_XTAL_GMN_V3_8822C) & BIT_MASK_XTAL_GMN_V3_8822C)
+#define BIT_SET_XTAL_GMN_V3_8822C(x, v) \
+ (BIT_CLEAR_XTAL_GMN_V3_8822C(x) | BIT_XTAL_GMN_V3_8822C(v))
+
+#define BIT_SHIFT_XTAL_GMP_V3_8822C 0
+#define BIT_MASK_XTAL_GMP_V3_8822C 0x1f
+#define BIT_XTAL_GMP_V3_8822C(x) \
+ (((x) & BIT_MASK_XTAL_GMP_V3_8822C) << BIT_SHIFT_XTAL_GMP_V3_8822C)
+#define BITS_XTAL_GMP_V3_8822C \
+ (BIT_MASK_XTAL_GMP_V3_8822C << BIT_SHIFT_XTAL_GMP_V3_8822C)
+#define BIT_CLEAR_XTAL_GMP_V3_8822C(x) ((x) & (~BITS_XTAL_GMP_V3_8822C))
+#define BIT_GET_XTAL_GMP_V3_8822C(x) \
+ (((x) >> BIT_SHIFT_XTAL_GMP_V3_8822C) & BIT_MASK_XTAL_GMP_V3_8822C)
+#define BIT_SET_XTAL_GMP_V3_8822C(x, v) \
+ (BIT_CLEAR_XTAL_GMP_V3_8822C(x) | BIT_XTAL_GMP_V3_8822C(v))
+
+/* 2 REG_ANAPAR_XTAL_1_8822C */
+#define BIT_XTAL_SEL_TOK_V1_8822C BIT(31)
+#define BIT_XTAL_DELAY_DIGI_V2_8822C BIT(30)
+#define BIT_XTAL_DELAY_USB_V2_8822C BIT(29)
+#define BIT_XTAL_DELAY_AFE_V2_8822C BIT(28)
+
+#define BIT_SHIFT_XTAL_DRV_DIGI_V2_8822C 26
+#define BIT_MASK_XTAL_DRV_DIGI_V2_8822C 0x3
+#define BIT_XTAL_DRV_DIGI_V2_8822C(x) \
+ (((x) & BIT_MASK_XTAL_DRV_DIGI_V2_8822C) \
+ << BIT_SHIFT_XTAL_DRV_DIGI_V2_8822C)
+#define BITS_XTAL_DRV_DIGI_V2_8822C \
+ (BIT_MASK_XTAL_DRV_DIGI_V2_8822C << BIT_SHIFT_XTAL_DRV_DIGI_V2_8822C)
+#define BIT_CLEAR_XTAL_DRV_DIGI_V2_8822C(x) \
+ ((x) & (~BITS_XTAL_DRV_DIGI_V2_8822C))
+#define BIT_GET_XTAL_DRV_DIGI_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_XTAL_DRV_DIGI_V2_8822C) & \
+ BIT_MASK_XTAL_DRV_DIGI_V2_8822C)
+#define BIT_SET_XTAL_DRV_DIGI_V2_8822C(x, v) \
+ (BIT_CLEAR_XTAL_DRV_DIGI_V2_8822C(x) | BIT_XTAL_DRV_DIGI_V2_8822C(v))
+
+#define BIT_EN_XTAL_DRV_LPS_8822C BIT(25)
+#define BIT_EN_XTAL_DRV_DIGI_V2_8822C BIT(24)
+
+#define BIT_SHIFT_XTAL_DRV_USB_8822C 22
+#define BIT_MASK_XTAL_DRV_USB_8822C 0x3
+#define BIT_XTAL_DRV_USB_8822C(x) \
+ (((x) & BIT_MASK_XTAL_DRV_USB_8822C) << BIT_SHIFT_XTAL_DRV_USB_8822C)
+#define BITS_XTAL_DRV_USB_8822C \
+ (BIT_MASK_XTAL_DRV_USB_8822C << BIT_SHIFT_XTAL_DRV_USB_8822C)
+#define BIT_CLEAR_XTAL_DRV_USB_8822C(x) ((x) & (~BITS_XTAL_DRV_USB_8822C))
+#define BIT_GET_XTAL_DRV_USB_8822C(x) \
+ (((x) >> BIT_SHIFT_XTAL_DRV_USB_8822C) & BIT_MASK_XTAL_DRV_USB_8822C)
+#define BIT_SET_XTAL_DRV_USB_8822C(x, v) \
+ (BIT_CLEAR_XTAL_DRV_USB_8822C(x) | BIT_XTAL_DRV_USB_8822C(v))
+
+#define BIT_EN_XTAL_DRV_USB_8822C BIT(21)
+
+#define BIT_SHIFT_XTAL_DRV_AFE_V2_8822C 19
+#define BIT_MASK_XTAL_DRV_AFE_V2_8822C 0x3
+#define BIT_XTAL_DRV_AFE_V2_8822C(x) \
+ (((x) & BIT_MASK_XTAL_DRV_AFE_V2_8822C) \
+ << BIT_SHIFT_XTAL_DRV_AFE_V2_8822C)
+#define BITS_XTAL_DRV_AFE_V2_8822C \
+ (BIT_MASK_XTAL_DRV_AFE_V2_8822C << BIT_SHIFT_XTAL_DRV_AFE_V2_8822C)
+#define BIT_CLEAR_XTAL_DRV_AFE_V2_8822C(x) ((x) & (~BITS_XTAL_DRV_AFE_V2_8822C))
+#define BIT_GET_XTAL_DRV_AFE_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_XTAL_DRV_AFE_V2_8822C) & \
+ BIT_MASK_XTAL_DRV_AFE_V2_8822C)
+#define BIT_SET_XTAL_DRV_AFE_V2_8822C(x, v) \
+ (BIT_CLEAR_XTAL_DRV_AFE_V2_8822C(x) | BIT_XTAL_DRV_AFE_V2_8822C(v))
+
+#define BIT_EN_XTAL_DRV_AFE_8822C BIT(18)
+
+#define BIT_SHIFT_XTAL_DRV_RF2_V2_8822C 16
+#define BIT_MASK_XTAL_DRV_RF2_V2_8822C 0x3
+#define BIT_XTAL_DRV_RF2_V2_8822C(x) \
+ (((x) & BIT_MASK_XTAL_DRV_RF2_V2_8822C) \
+ << BIT_SHIFT_XTAL_DRV_RF2_V2_8822C)
+#define BITS_XTAL_DRV_RF2_V2_8822C \
+ (BIT_MASK_XTAL_DRV_RF2_V2_8822C << BIT_SHIFT_XTAL_DRV_RF2_V2_8822C)
+#define BIT_CLEAR_XTAL_DRV_RF2_V2_8822C(x) ((x) & (~BITS_XTAL_DRV_RF2_V2_8822C))
+#define BIT_GET_XTAL_DRV_RF2_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_XTAL_DRV_RF2_V2_8822C) & \
+ BIT_MASK_XTAL_DRV_RF2_V2_8822C)
+#define BIT_SET_XTAL_DRV_RF2_V2_8822C(x, v) \
+ (BIT_CLEAR_XTAL_DRV_RF2_V2_8822C(x) | BIT_XTAL_DRV_RF2_V2_8822C(v))
+
+#define BIT_EN_XTAL_DRV_RF2_8822C BIT(15)
+
+#define BIT_SHIFT_XTAL_DRV_RF1_8822C 13
+#define BIT_MASK_XTAL_DRV_RF1_8822C 0x3
+#define BIT_XTAL_DRV_RF1_8822C(x) \
+ (((x) & BIT_MASK_XTAL_DRV_RF1_8822C) << BIT_SHIFT_XTAL_DRV_RF1_8822C)
+#define BITS_XTAL_DRV_RF1_8822C \
+ (BIT_MASK_XTAL_DRV_RF1_8822C << BIT_SHIFT_XTAL_DRV_RF1_8822C)
+#define BIT_CLEAR_XTAL_DRV_RF1_8822C(x) ((x) & (~BITS_XTAL_DRV_RF1_8822C))
+#define BIT_GET_XTAL_DRV_RF1_8822C(x) \
+ (((x) >> BIT_SHIFT_XTAL_DRV_RF1_8822C) & BIT_MASK_XTAL_DRV_RF1_8822C)
+#define BIT_SET_XTAL_DRV_RF1_8822C(x, v) \
+ (BIT_CLEAR_XTAL_DRV_RF1_8822C(x) | BIT_XTAL_DRV_RF1_8822C(v))
+
+#define BIT_EN_XTAL_DRV_RF1_8822C BIT(12)
+#define BIT_XTAL_DRV_RF_LATCH_V4_8822C BIT(11)
+#define BIT_XTAL_GM_SEP_V3_8822C BIT(10)
+#define BIT_XQSEL_RF_AWAKE_V3_8822C BIT(9)
+#define BIT_XQSEL_RF_INITIAL_V3_8822C BIT(8)
+#define BIT_XQSEL_V2_8822C BIT(7)
+#define BIT_GATED_XTAL_OK0_V2_8822C BIT(6)
+
+#define BIT_SHIFT_XTAL_SC_LPS_V2_8822C 0
+#define BIT_MASK_XTAL_SC_LPS_V2_8822C 0x3f
+#define BIT_XTAL_SC_LPS_V2_8822C(x) \
+ (((x) & BIT_MASK_XTAL_SC_LPS_V2_8822C) \
+ << BIT_SHIFT_XTAL_SC_LPS_V2_8822C)
+#define BITS_XTAL_SC_LPS_V2_8822C \
+ (BIT_MASK_XTAL_SC_LPS_V2_8822C << BIT_SHIFT_XTAL_SC_LPS_V2_8822C)
+#define BIT_CLEAR_XTAL_SC_LPS_V2_8822C(x) ((x) & (~BITS_XTAL_SC_LPS_V2_8822C))
+#define BIT_GET_XTAL_SC_LPS_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_XTAL_SC_LPS_V2_8822C) & \
+ BIT_MASK_XTAL_SC_LPS_V2_8822C)
+#define BIT_SET_XTAL_SC_LPS_V2_8822C(x, v) \
+ (BIT_CLEAR_XTAL_SC_LPS_V2_8822C(x) | BIT_XTAL_SC_LPS_V2_8822C(v))
+
+/* 2 REG_ANAPAR_XTAL_2_8822C */
+#define BIT_XTAL_AAC_CAP_8822C BIT(31)
+
+#define BIT_SHIFT_XTAL_PDSW_8822C 29
+#define BIT_MASK_XTAL_PDSW_8822C 0x3
+#define BIT_XTAL_PDSW_8822C(x) \
+ (((x) & BIT_MASK_XTAL_PDSW_8822C) << BIT_SHIFT_XTAL_PDSW_8822C)
+#define BITS_XTAL_PDSW_8822C \
+ (BIT_MASK_XTAL_PDSW_8822C << BIT_SHIFT_XTAL_PDSW_8822C)
+#define BIT_CLEAR_XTAL_PDSW_8822C(x) ((x) & (~BITS_XTAL_PDSW_8822C))
+#define BIT_GET_XTAL_PDSW_8822C(x) \
+ (((x) >> BIT_SHIFT_XTAL_PDSW_8822C) & BIT_MASK_XTAL_PDSW_8822C)
+#define BIT_SET_XTAL_PDSW_8822C(x, v) \
+ (BIT_CLEAR_XTAL_PDSW_8822C(x) | BIT_XTAL_PDSW_8822C(v))
+
+#define BIT_SHIFT_XTAL_LPS_BUF_VB_8822C 27
+#define BIT_MASK_XTAL_LPS_BUF_VB_8822C 0x3
+#define BIT_XTAL_LPS_BUF_VB_8822C(x) \
+ (((x) & BIT_MASK_XTAL_LPS_BUF_VB_8822C) \
+ << BIT_SHIFT_XTAL_LPS_BUF_VB_8822C)
+#define BITS_XTAL_LPS_BUF_VB_8822C \
+ (BIT_MASK_XTAL_LPS_BUF_VB_8822C << BIT_SHIFT_XTAL_LPS_BUF_VB_8822C)
+#define BIT_CLEAR_XTAL_LPS_BUF_VB_8822C(x) ((x) & (~BITS_XTAL_LPS_BUF_VB_8822C))
+#define BIT_GET_XTAL_LPS_BUF_VB_8822C(x) \
+ (((x) >> BIT_SHIFT_XTAL_LPS_BUF_VB_8822C) & \
+ BIT_MASK_XTAL_LPS_BUF_VB_8822C)
+#define BIT_SET_XTAL_LPS_BUF_VB_8822C(x, v) \
+ (BIT_CLEAR_XTAL_LPS_BUF_VB_8822C(x) | BIT_XTAL_LPS_BUF_VB_8822C(v))
+
+#define BIT_XTAL_PDCK_MANU_8822C BIT(26)
+#define BIT_XTAL_PDCK_OK_MANU_8822C BIT(25)
+
+#define BIT_SHIFT_XTAL_VREF_SEL_8822C 20
+#define BIT_MASK_XTAL_VREF_SEL_8822C 0x1f
+#define BIT_XTAL_VREF_SEL_8822C(x) \
+ (((x) & BIT_MASK_XTAL_VREF_SEL_8822C) << BIT_SHIFT_XTAL_VREF_SEL_8822C)
+#define BITS_XTAL_VREF_SEL_8822C \
+ (BIT_MASK_XTAL_VREF_SEL_8822C << BIT_SHIFT_XTAL_VREF_SEL_8822C)
+#define BIT_CLEAR_XTAL_VREF_SEL_8822C(x) ((x) & (~BITS_XTAL_VREF_SEL_8822C))
+#define BIT_GET_XTAL_VREF_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_XTAL_VREF_SEL_8822C) & BIT_MASK_XTAL_VREF_SEL_8822C)
+#define BIT_SET_XTAL_VREF_SEL_8822C(x, v) \
+ (BIT_CLEAR_XTAL_VREF_SEL_8822C(x) | BIT_XTAL_VREF_SEL_8822C(v))
+
+#define BIT_EN_XTAL_PDCK_VREF_8822C BIT(19)
+#define BIT_XTAL_SEL_PWR_V1_8822C BIT(18)
+#define BIT_XTAL_LPS_DIVISOR_8822C BIT(17)
+#define BIT_XTAL_CKDIGI_SEL_8822C BIT(16)
+#define BIT_EN_XTAL_LPS_CLK_8822C BIT(15)
+#define BIT_EN_XTAL_SCHMITT_8822C BIT(14)
+#define BIT_XTAL_PK_SEL_OFFSET_8822C BIT(13)
+
+#define BIT_SHIFT_XTAL_MANU_PK_SEL_8822C 11
+#define BIT_MASK_XTAL_MANU_PK_SEL_8822C 0x3
+#define BIT_XTAL_MANU_PK_SEL_8822C(x) \
+ (((x) & BIT_MASK_XTAL_MANU_PK_SEL_8822C) \
+ << BIT_SHIFT_XTAL_MANU_PK_SEL_8822C)
+#define BITS_XTAL_MANU_PK_SEL_8822C \
+ (BIT_MASK_XTAL_MANU_PK_SEL_8822C << BIT_SHIFT_XTAL_MANU_PK_SEL_8822C)
+#define BIT_CLEAR_XTAL_MANU_PK_SEL_8822C(x) \
+ ((x) & (~BITS_XTAL_MANU_PK_SEL_8822C))
+#define BIT_GET_XTAL_MANU_PK_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_XTAL_MANU_PK_SEL_8822C) & \
+ BIT_MASK_XTAL_MANU_PK_SEL_8822C)
+#define BIT_SET_XTAL_MANU_PK_SEL_8822C(x, v) \
+ (BIT_CLEAR_XTAL_MANU_PK_SEL_8822C(x) | BIT_XTAL_MANU_PK_SEL_8822C(v))
+
+#define BIT_XTAL_AACK_PK_MANU_8822C BIT(10)
+#define BIT_EN_XTAL_AAC_PKDET_V1_8822C BIT(9)
+#define BIT_EN_XTAL_AAC_GM_V1_8822C BIT(8)
+#define BIT_XTAL_LDO_OPVB_SEL_8822C BIT(7)
+#define BIT_XTAL_LDO_NC_8822C BIT(6)
+
+#define BIT_SHIFT_XTAL_LDO_VREF_V2_8822C 3
+#define BIT_MASK_XTAL_LDO_VREF_V2_8822C 0x7
+#define BIT_XTAL_LDO_VREF_V2_8822C(x) \
+ (((x) & BIT_MASK_XTAL_LDO_VREF_V2_8822C) \
+ << BIT_SHIFT_XTAL_LDO_VREF_V2_8822C)
+#define BITS_XTAL_LDO_VREF_V2_8822C \
+ (BIT_MASK_XTAL_LDO_VREF_V2_8822C << BIT_SHIFT_XTAL_LDO_VREF_V2_8822C)
+#define BIT_CLEAR_XTAL_LDO_VREF_V2_8822C(x) \
+ ((x) & (~BITS_XTAL_LDO_VREF_V2_8822C))
+#define BIT_GET_XTAL_LDO_VREF_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_XTAL_LDO_VREF_V2_8822C) & \
+ BIT_MASK_XTAL_LDO_VREF_V2_8822C)
+#define BIT_SET_XTAL_LDO_VREF_V2_8822C(x, v) \
+ (BIT_CLEAR_XTAL_LDO_VREF_V2_8822C(x) | BIT_XTAL_LDO_VREF_V2_8822C(v))
+
+#define BIT_XTAL_LPMODE_V1_8822C BIT(2)
+
+#define BIT_SHIFT_XTAL_SEL_TOK_V3_8822C 0
+#define BIT_MASK_XTAL_SEL_TOK_V3_8822C 0x3
+#define BIT_XTAL_SEL_TOK_V3_8822C(x) \
+ (((x) & BIT_MASK_XTAL_SEL_TOK_V3_8822C) \
+ << BIT_SHIFT_XTAL_SEL_TOK_V3_8822C)
+#define BITS_XTAL_SEL_TOK_V3_8822C \
+ (BIT_MASK_XTAL_SEL_TOK_V3_8822C << BIT_SHIFT_XTAL_SEL_TOK_V3_8822C)
+#define BIT_CLEAR_XTAL_SEL_TOK_V3_8822C(x) ((x) & (~BITS_XTAL_SEL_TOK_V3_8822C))
+#define BIT_GET_XTAL_SEL_TOK_V3_8822C(x) \
+ (((x) >> BIT_SHIFT_XTAL_SEL_TOK_V3_8822C) & \
+ BIT_MASK_XTAL_SEL_TOK_V3_8822C)
+#define BIT_SET_XTAL_SEL_TOK_V3_8822C(x, v) \
+ (BIT_CLEAR_XTAL_SEL_TOK_V3_8822C(x) | BIT_XTAL_SEL_TOK_V3_8822C(v))
+
+/* 2 REG_ANAPAR_XTAL_3_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_XTAL_DUMMY_V1_8822C 7
+#define BIT_MASK_XTAL_DUMMY_V1_8822C 0x3f
+#define BIT_XTAL_DUMMY_V1_8822C(x) \
+ (((x) & BIT_MASK_XTAL_DUMMY_V1_8822C) << BIT_SHIFT_XTAL_DUMMY_V1_8822C)
+#define BITS_XTAL_DUMMY_V1_8822C \
+ (BIT_MASK_XTAL_DUMMY_V1_8822C << BIT_SHIFT_XTAL_DUMMY_V1_8822C)
+#define BIT_CLEAR_XTAL_DUMMY_V1_8822C(x) ((x) & (~BITS_XTAL_DUMMY_V1_8822C))
+#define BIT_GET_XTAL_DUMMY_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_XTAL_DUMMY_V1_8822C) & BIT_MASK_XTAL_DUMMY_V1_8822C)
+#define BIT_SET_XTAL_DUMMY_V1_8822C(x, v) \
+ (BIT_CLEAR_XTAL_DUMMY_V1_8822C(x) | BIT_XTAL_DUMMY_V1_8822C(v))
+
+#define BIT_XTAL_EN_LNBUF_8822C BIT(6)
+#define BIT_XTAL__AAC_TIE_MID_8822C BIT(5)
+
+#define BIT_SHIFT_XTAL_AAC_OPCUR_8822C 3
+#define BIT_MASK_XTAL_AAC_OPCUR_8822C 0x3
+#define BIT_XTAL_AAC_OPCUR_8822C(x) \
+ (((x) & BIT_MASK_XTAL_AAC_OPCUR_8822C) \
+ << BIT_SHIFT_XTAL_AAC_OPCUR_8822C)
+#define BITS_XTAL_AAC_OPCUR_8822C \
+ (BIT_MASK_XTAL_AAC_OPCUR_8822C << BIT_SHIFT_XTAL_AAC_OPCUR_8822C)
+#define BIT_CLEAR_XTAL_AAC_OPCUR_8822C(x) ((x) & (~BITS_XTAL_AAC_OPCUR_8822C))
+#define BIT_GET_XTAL_AAC_OPCUR_8822C(x) \
+ (((x) >> BIT_SHIFT_XTAL_AAC_OPCUR_8822C) & \
+ BIT_MASK_XTAL_AAC_OPCUR_8822C)
+#define BIT_SET_XTAL_AAC_OPCUR_8822C(x, v) \
+ (BIT_CLEAR_XTAL_AAC_OPCUR_8822C(x) | BIT_XTAL_AAC_OPCUR_8822C(v))
+
+#define BIT_SHIFT_XTAL_AAC_IOFFSET_8822C 1
+#define BIT_MASK_XTAL_AAC_IOFFSET_8822C 0x3
+#define BIT_XTAL_AAC_IOFFSET_8822C(x) \
+ (((x) & BIT_MASK_XTAL_AAC_IOFFSET_8822C) \
+ << BIT_SHIFT_XTAL_AAC_IOFFSET_8822C)
+#define BITS_XTAL_AAC_IOFFSET_8822C \
+ (BIT_MASK_XTAL_AAC_IOFFSET_8822C << BIT_SHIFT_XTAL_AAC_IOFFSET_8822C)
+#define BIT_CLEAR_XTAL_AAC_IOFFSET_8822C(x) \
+ ((x) & (~BITS_XTAL_AAC_IOFFSET_8822C))
+#define BIT_GET_XTAL_AAC_IOFFSET_8822C(x) \
+ (((x) >> BIT_SHIFT_XTAL_AAC_IOFFSET_8822C) & \
+ BIT_MASK_XTAL_AAC_IOFFSET_8822C)
+#define BIT_SET_XTAL_AAC_IOFFSET_8822C(x, v) \
+ (BIT_CLEAR_XTAL_AAC_IOFFSET_8822C(x) | BIT_XTAL_AAC_IOFFSET_8822C(v))
+
+#define BIT_XTAL_AAC_CAP_V1_8822C BIT(0)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_ANAPAR_XTAL_AACK_0_8822C */
+#define BIT_XAAC_LPOW_8822C BIT(31)
+
+#define BIT_SHIFT_AAC_MODE_8822C 29
+#define BIT_MASK_AAC_MODE_8822C 0x3
+#define BIT_AAC_MODE_8822C(x) \
+ (((x) & BIT_MASK_AAC_MODE_8822C) << BIT_SHIFT_AAC_MODE_8822C)
+#define BITS_AAC_MODE_8822C \
+ (BIT_MASK_AAC_MODE_8822C << BIT_SHIFT_AAC_MODE_8822C)
+#define BIT_CLEAR_AAC_MODE_8822C(x) ((x) & (~BITS_AAC_MODE_8822C))
+#define BIT_GET_AAC_MODE_8822C(x) \
+ (((x) >> BIT_SHIFT_AAC_MODE_8822C) & BIT_MASK_AAC_MODE_8822C)
+#define BIT_SET_AAC_MODE_8822C(x, v) \
+ (BIT_CLEAR_AAC_MODE_8822C(x) | BIT_AAC_MODE_8822C(v))
+
+#define BIT_EN_XTAL_AAC_TRIG_8822C BIT(28)
+#define BIT_EN_XTAL_AAC_8822C BIT(27)
+#define BIT_EN_XTAL_AAC_DIGI_8822C BIT(26)
+
+#define BIT_SHIFT_GM_MANUAL_8822C 21
+#define BIT_MASK_GM_MANUAL_8822C 0x1f
+#define BIT_GM_MANUAL_8822C(x) \
+ (((x) & BIT_MASK_GM_MANUAL_8822C) << BIT_SHIFT_GM_MANUAL_8822C)
+#define BITS_GM_MANUAL_8822C \
+ (BIT_MASK_GM_MANUAL_8822C << BIT_SHIFT_GM_MANUAL_8822C)
+#define BIT_CLEAR_GM_MANUAL_8822C(x) ((x) & (~BITS_GM_MANUAL_8822C))
+#define BIT_GET_GM_MANUAL_8822C(x) \
+ (((x) >> BIT_SHIFT_GM_MANUAL_8822C) & BIT_MASK_GM_MANUAL_8822C)
+#define BIT_SET_GM_MANUAL_8822C(x, v) \
+ (BIT_CLEAR_GM_MANUAL_8822C(x) | BIT_GM_MANUAL_8822C(v))
+
+#define BIT_SHIFT_GM_STUP_8822C 16
+#define BIT_MASK_GM_STUP_8822C 0x1f
+#define BIT_GM_STUP_8822C(x) \
+ (((x) & BIT_MASK_GM_STUP_8822C) << BIT_SHIFT_GM_STUP_8822C)
+#define BITS_GM_STUP_8822C (BIT_MASK_GM_STUP_8822C << BIT_SHIFT_GM_STUP_8822C)
+#define BIT_CLEAR_GM_STUP_8822C(x) ((x) & (~BITS_GM_STUP_8822C))
+#define BIT_GET_GM_STUP_8822C(x) \
+ (((x) >> BIT_SHIFT_GM_STUP_8822C) & BIT_MASK_GM_STUP_8822C)
+#define BIT_SET_GM_STUP_8822C(x, v) \
+ (BIT_CLEAR_GM_STUP_8822C(x) | BIT_GM_STUP_8822C(v))
+
+#define BIT_SHIFT_XTAL_CK_SET_8822C 13
+#define BIT_MASK_XTAL_CK_SET_8822C 0x7
+#define BIT_XTAL_CK_SET_8822C(x) \
+ (((x) & BIT_MASK_XTAL_CK_SET_8822C) << BIT_SHIFT_XTAL_CK_SET_8822C)
+#define BITS_XTAL_CK_SET_8822C \
+ (BIT_MASK_XTAL_CK_SET_8822C << BIT_SHIFT_XTAL_CK_SET_8822C)
+#define BIT_CLEAR_XTAL_CK_SET_8822C(x) ((x) & (~BITS_XTAL_CK_SET_8822C))
+#define BIT_GET_XTAL_CK_SET_8822C(x) \
+ (((x) >> BIT_SHIFT_XTAL_CK_SET_8822C) & BIT_MASK_XTAL_CK_SET_8822C)
+#define BIT_SET_XTAL_CK_SET_8822C(x, v) \
+ (BIT_CLEAR_XTAL_CK_SET_8822C(x) | BIT_XTAL_CK_SET_8822C(v))
+
+#define BIT_SHIFT_GM_INIT_8822C 8
+#define BIT_MASK_GM_INIT_8822C 0x1f
+#define BIT_GM_INIT_8822C(x) \
+ (((x) & BIT_MASK_GM_INIT_8822C) << BIT_SHIFT_GM_INIT_8822C)
+#define BITS_GM_INIT_8822C (BIT_MASK_GM_INIT_8822C << BIT_SHIFT_GM_INIT_8822C)
+#define BIT_CLEAR_GM_INIT_8822C(x) ((x) & (~BITS_GM_INIT_8822C))
+#define BIT_GET_GM_INIT_8822C(x) \
+ (((x) >> BIT_SHIFT_GM_INIT_8822C) & BIT_MASK_GM_INIT_8822C)
+#define BIT_SET_GM_INIT_8822C(x, v) \
+ (BIT_CLEAR_GM_INIT_8822C(x) | BIT_GM_INIT_8822C(v))
+
+#define BIT_GM_STEP_8822C BIT(7)
+
+#define BIT_SHIFT_XAAC_GM_OFFSET_8822C 2
+#define BIT_MASK_XAAC_GM_OFFSET_8822C 0x1f
+#define BIT_XAAC_GM_OFFSET_8822C(x) \
+ (((x) & BIT_MASK_XAAC_GM_OFFSET_8822C) \
+ << BIT_SHIFT_XAAC_GM_OFFSET_8822C)
+#define BITS_XAAC_GM_OFFSET_8822C \
+ (BIT_MASK_XAAC_GM_OFFSET_8822C << BIT_SHIFT_XAAC_GM_OFFSET_8822C)
+#define BIT_CLEAR_XAAC_GM_OFFSET_8822C(x) ((x) & (~BITS_XAAC_GM_OFFSET_8822C))
+#define BIT_GET_XAAC_GM_OFFSET_8822C(x) \
+ (((x) >> BIT_SHIFT_XAAC_GM_OFFSET_8822C) & \
+ BIT_MASK_XAAC_GM_OFFSET_8822C)
+#define BIT_SET_XAAC_GM_OFFSET_8822C(x, v) \
+ (BIT_CLEAR_XAAC_GM_OFFSET_8822C(x) | BIT_XAAC_GM_OFFSET_8822C(v))
+
+#define BIT_OFFSET_PLUS_8822C BIT(1)
+#define BIT_RESET_N_8822C BIT(0)
+
+/* 2 REG_ANAPAR_XTAL_AACK_1_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_PK_END_AR_8822C 3
+#define BIT_MASK_PK_END_AR_8822C 0x3
+#define BIT_PK_END_AR_8822C(x) \
+ (((x) & BIT_MASK_PK_END_AR_8822C) << BIT_SHIFT_PK_END_AR_8822C)
+#define BITS_PK_END_AR_8822C \
+ (BIT_MASK_PK_END_AR_8822C << BIT_SHIFT_PK_END_AR_8822C)
+#define BIT_CLEAR_PK_END_AR_8822C(x) ((x) & (~BITS_PK_END_AR_8822C))
+#define BIT_GET_PK_END_AR_8822C(x) \
+ (((x) >> BIT_SHIFT_PK_END_AR_8822C) & BIT_MASK_PK_END_AR_8822C)
+#define BIT_SET_PK_END_AR_8822C(x, v) \
+ (BIT_CLEAR_PK_END_AR_8822C(x) | BIT_PK_END_AR_8822C(v))
+
+#define BIT_SHIFT_PK_START_AR_8822C 1
+#define BIT_MASK_PK_START_AR_8822C 0x3
+#define BIT_PK_START_AR_8822C(x) \
+ (((x) & BIT_MASK_PK_START_AR_8822C) << BIT_SHIFT_PK_START_AR_8822C)
+#define BITS_PK_START_AR_8822C \
+ (BIT_MASK_PK_START_AR_8822C << BIT_SHIFT_PK_START_AR_8822C)
+#define BIT_CLEAR_PK_START_AR_8822C(x) ((x) & (~BITS_PK_START_AR_8822C))
+#define BIT_GET_PK_START_AR_8822C(x) \
+ (((x) >> BIT_SHIFT_PK_START_AR_8822C) & BIT_MASK_PK_START_AR_8822C)
+#define BIT_SET_PK_START_AR_8822C(x, v) \
+ (BIT_CLEAR_PK_START_AR_8822C(x) | BIT_PK_START_AR_8822C(v))
+
+#define BIT_XAAC_LUT_MANUAL_EN_8822C BIT(0)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_ANAPAR_XTAL_MODE_DECODER_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_XTAL_LDO_LPS_8822C 21
+#define BIT_MASK_XTAL_LDO_LPS_8822C 0x7
+#define BIT_XTAL_LDO_LPS_8822C(x) \
+ (((x) & BIT_MASK_XTAL_LDO_LPS_8822C) << BIT_SHIFT_XTAL_LDO_LPS_8822C)
+#define BITS_XTAL_LDO_LPS_8822C \
+ (BIT_MASK_XTAL_LDO_LPS_8822C << BIT_SHIFT_XTAL_LDO_LPS_8822C)
+#define BIT_CLEAR_XTAL_LDO_LPS_8822C(x) ((x) & (~BITS_XTAL_LDO_LPS_8822C))
+#define BIT_GET_XTAL_LDO_LPS_8822C(x) \
+ (((x) >> BIT_SHIFT_XTAL_LDO_LPS_8822C) & BIT_MASK_XTAL_LDO_LPS_8822C)
+#define BIT_SET_XTAL_LDO_LPS_8822C(x, v) \
+ (BIT_CLEAR_XTAL_LDO_LPS_8822C(x) | BIT_XTAL_LDO_LPS_8822C(v))
+
+#define BIT_SHIFT_XTAL_WAIT_CYC_8822C 15
+#define BIT_MASK_XTAL_WAIT_CYC_8822C 0x3f
+#define BIT_XTAL_WAIT_CYC_8822C(x) \
+ (((x) & BIT_MASK_XTAL_WAIT_CYC_8822C) << BIT_SHIFT_XTAL_WAIT_CYC_8822C)
+#define BITS_XTAL_WAIT_CYC_8822C \
+ (BIT_MASK_XTAL_WAIT_CYC_8822C << BIT_SHIFT_XTAL_WAIT_CYC_8822C)
+#define BIT_CLEAR_XTAL_WAIT_CYC_8822C(x) ((x) & (~BITS_XTAL_WAIT_CYC_8822C))
+#define BIT_GET_XTAL_WAIT_CYC_8822C(x) \
+ (((x) >> BIT_SHIFT_XTAL_WAIT_CYC_8822C) & BIT_MASK_XTAL_WAIT_CYC_8822C)
+#define BIT_SET_XTAL_WAIT_CYC_8822C(x, v) \
+ (BIT_CLEAR_XTAL_WAIT_CYC_8822C(x) | BIT_XTAL_WAIT_CYC_8822C(v))
+
+#define BIT_SHIFT_XTAL_LDO_OK_8822C 12
+#define BIT_MASK_XTAL_LDO_OK_8822C 0x7
+#define BIT_XTAL_LDO_OK_8822C(x) \
+ (((x) & BIT_MASK_XTAL_LDO_OK_8822C) << BIT_SHIFT_XTAL_LDO_OK_8822C)
+#define BITS_XTAL_LDO_OK_8822C \
+ (BIT_MASK_XTAL_LDO_OK_8822C << BIT_SHIFT_XTAL_LDO_OK_8822C)
+#define BIT_CLEAR_XTAL_LDO_OK_8822C(x) ((x) & (~BITS_XTAL_LDO_OK_8822C))
+#define BIT_GET_XTAL_LDO_OK_8822C(x) \
+ (((x) >> BIT_SHIFT_XTAL_LDO_OK_8822C) & BIT_MASK_XTAL_LDO_OK_8822C)
+#define BIT_SET_XTAL_LDO_OK_8822C(x, v) \
+ (BIT_CLEAR_XTAL_LDO_OK_8822C(x) | BIT_XTAL_LDO_OK_8822C(v))
+
+#define BIT_XTAL_MD_LPOW_8822C BIT(11)
+
+#define BIT_SHIFT_XTAL_OV_RATIO_8822C 9
+#define BIT_MASK_XTAL_OV_RATIO_8822C 0x3
+#define BIT_XTAL_OV_RATIO_8822C(x) \
+ (((x) & BIT_MASK_XTAL_OV_RATIO_8822C) << BIT_SHIFT_XTAL_OV_RATIO_8822C)
+#define BITS_XTAL_OV_RATIO_8822C \
+ (BIT_MASK_XTAL_OV_RATIO_8822C << BIT_SHIFT_XTAL_OV_RATIO_8822C)
+#define BIT_CLEAR_XTAL_OV_RATIO_8822C(x) ((x) & (~BITS_XTAL_OV_RATIO_8822C))
+#define BIT_GET_XTAL_OV_RATIO_8822C(x) \
+ (((x) >> BIT_SHIFT_XTAL_OV_RATIO_8822C) & BIT_MASK_XTAL_OV_RATIO_8822C)
+#define BIT_SET_XTAL_OV_RATIO_8822C(x, v) \
+ (BIT_CLEAR_XTAL_OV_RATIO_8822C(x) | BIT_XTAL_OV_RATIO_8822C(v))
+
+#define BIT_SHIFT_XTAL_OV_UNIT_8822C 6
+#define BIT_MASK_XTAL_OV_UNIT_8822C 0x7
+#define BIT_XTAL_OV_UNIT_8822C(x) \
+ (((x) & BIT_MASK_XTAL_OV_UNIT_8822C) << BIT_SHIFT_XTAL_OV_UNIT_8822C)
+#define BITS_XTAL_OV_UNIT_8822C \
+ (BIT_MASK_XTAL_OV_UNIT_8822C << BIT_SHIFT_XTAL_OV_UNIT_8822C)
+#define BIT_CLEAR_XTAL_OV_UNIT_8822C(x) ((x) & (~BITS_XTAL_OV_UNIT_8822C))
+#define BIT_GET_XTAL_OV_UNIT_8822C(x) \
+ (((x) >> BIT_SHIFT_XTAL_OV_UNIT_8822C) & BIT_MASK_XTAL_OV_UNIT_8822C)
+#define BIT_SET_XTAL_OV_UNIT_8822C(x, v) \
+ (BIT_CLEAR_XTAL_OV_UNIT_8822C(x) | BIT_XTAL_OV_UNIT_8822C(v))
+
+#define BIT_SHIFT_XTAL_MODE_MANUAL_8822C 4
+#define BIT_MASK_XTAL_MODE_MANUAL_8822C 0x3
+#define BIT_XTAL_MODE_MANUAL_8822C(x) \
+ (((x) & BIT_MASK_XTAL_MODE_MANUAL_8822C) \
+ << BIT_SHIFT_XTAL_MODE_MANUAL_8822C)
+#define BITS_XTAL_MODE_MANUAL_8822C \
+ (BIT_MASK_XTAL_MODE_MANUAL_8822C << BIT_SHIFT_XTAL_MODE_MANUAL_8822C)
+#define BIT_CLEAR_XTAL_MODE_MANUAL_8822C(x) \
+ ((x) & (~BITS_XTAL_MODE_MANUAL_8822C))
+#define BIT_GET_XTAL_MODE_MANUAL_8822C(x) \
+ (((x) >> BIT_SHIFT_XTAL_MODE_MANUAL_8822C) & \
+ BIT_MASK_XTAL_MODE_MANUAL_8822C)
+#define BIT_SET_XTAL_MODE_MANUAL_8822C(x, v) \
+ (BIT_CLEAR_XTAL_MODE_MANUAL_8822C(x) | BIT_XTAL_MODE_MANUAL_8822C(v))
+
+#define BIT_XTAL_MANU_SEL_8822C BIT(3)
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_XTAL_MODE_8822C BIT(1)
+#define BIT_RESET_N_DECODER_8822C BIT(0)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_SYS_CFG5_8822C */
+#define BIT_LPS_STATUS_8822C BIT(3)
+#define BIT_HCI_TXDMA_BUSY_8822C BIT(2)
+#define BIT_HCI_TXDMA_ALLOW_8822C BIT(1)
+#define BIT_FW_CTRL_HCI_TXDMA_EN_8822C BIT(0)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_CPU_DMEM_CON_8822C */
+#define BIT_WDT_AUTO_MODE_8822C BIT(22)
+#define BIT_WDT_PLATFORM_EN_8822C BIT(21)
+#define BIT_WDT_CPU_EN_8822C BIT(20)
+#define BIT_WDT_OPT_IOWRAPPER_8822C BIT(19)
+#define BIT_ANA_PORT_IDLE_8822C BIT(18)
+#define BIT_MAC_PORT_IDLE_8822C BIT(17)
+#define BIT_WL_PLATFORM_RST_8822C BIT(16)
+#define BIT_WL_SECURITY_CLK_8822C BIT(15)
+#define BIT_DDMA_EN_8822C BIT(8)
+
+#define BIT_SHIFT_CPU_DMEM_CON_8822C 0
+#define BIT_MASK_CPU_DMEM_CON_8822C 0xff
+#define BIT_CPU_DMEM_CON_8822C(x) \
+ (((x) & BIT_MASK_CPU_DMEM_CON_8822C) << BIT_SHIFT_CPU_DMEM_CON_8822C)
+#define BITS_CPU_DMEM_CON_8822C \
+ (BIT_MASK_CPU_DMEM_CON_8822C << BIT_SHIFT_CPU_DMEM_CON_8822C)
+#define BIT_CLEAR_CPU_DMEM_CON_8822C(x) ((x) & (~BITS_CPU_DMEM_CON_8822C))
+#define BIT_GET_CPU_DMEM_CON_8822C(x) \
+ (((x) >> BIT_SHIFT_CPU_DMEM_CON_8822C) & BIT_MASK_CPU_DMEM_CON_8822C)
+#define BIT_SET_CPU_DMEM_CON_8822C(x, v) \
+ (BIT_CLEAR_CPU_DMEM_CON_8822C(x) | BIT_CPU_DMEM_CON_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_BOOT_REASON_8822C */
+
+#define BIT_SHIFT_BOOT_REASON_V1_8822C 0
+#define BIT_MASK_BOOT_REASON_V1_8822C 0x7
+#define BIT_BOOT_REASON_V1_8822C(x) \
+ (((x) & BIT_MASK_BOOT_REASON_V1_8822C) \
+ << BIT_SHIFT_BOOT_REASON_V1_8822C)
+#define BITS_BOOT_REASON_V1_8822C \
+ (BIT_MASK_BOOT_REASON_V1_8822C << BIT_SHIFT_BOOT_REASON_V1_8822C)
+#define BIT_CLEAR_BOOT_REASON_V1_8822C(x) ((x) & (~BITS_BOOT_REASON_V1_8822C))
+#define BIT_GET_BOOT_REASON_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_BOOT_REASON_V1_8822C) & \
+ BIT_MASK_BOOT_REASON_V1_8822C)
+#define BIT_SET_BOOT_REASON_V1_8822C(x, v) \
+ (BIT_CLEAR_BOOT_REASON_V1_8822C(x) | BIT_BOOT_REASON_V1_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_HIMR2_8822C */
+#define BIT_BCNDMAINT_P4_MSK_8822C BIT(31)
+#define BIT_BCNDMAINT_P3_MSK_8822C BIT(30)
+#define BIT_BCNDMAINT_P2_MSK_8822C BIT(29)
+#define BIT_BCNDMAINT_P1_MSK_8822C BIT(28)
+#define BIT_ATIMEND7_MSK_8822C BIT(22)
+#define BIT_ATIMEND6_MSK_8822C BIT(21)
+#define BIT_ATIMEND5_MSK_8822C BIT(20)
+#define BIT_ATIMEND4_MSK_8822C BIT(19)
+#define BIT_ATIMEND3_MSK_8822C BIT(18)
+#define BIT_ATIMEND2_MSK_8822C BIT(17)
+#define BIT_ATIMEND1_MSK_8822C BIT(16)
+#define BIT_TXBCN7OK_MSK_8822C BIT(14)
+#define BIT_TXBCN6OK_MSK_8822C BIT(13)
+#define BIT_TXBCN5OK_MSK_8822C BIT(12)
+#define BIT_TXBCN4OK_MSK_8822C BIT(11)
+#define BIT_TXBCN3OK_MSK_8822C BIT(10)
+#define BIT_TXBCN2OK_MSK_8822C BIT(9)
+#define BIT_TXBCN1OK_MSK_V1_8822C BIT(8)
+#define BIT_TXBCN7ERR_MSK_8822C BIT(6)
+#define BIT_TXBCN6ERR_MSK_8822C BIT(5)
+#define BIT_TXBCN5ERR_MSK_8822C BIT(4)
+#define BIT_TXBCN4ERR_MSK_8822C BIT(3)
+#define BIT_TXBCN3ERR_MSK_8822C BIT(2)
+#define BIT_TXBCN2ERR_MSK_8822C BIT(1)
+#define BIT_TXBCN1ERR_MSK_V1_8822C BIT(0)
+
+/* 2 REG_HISR2_8822C */
+#define BIT_BCNDMAINT_P4_8822C BIT(31)
+#define BIT_BCNDMAINT_P3_8822C BIT(30)
+#define BIT_BCNDMAINT_P2_8822C BIT(29)
+#define BIT_BCNDMAINT_P1_8822C BIT(28)
+#define BIT_ATIMEND7_8822C BIT(22)
+#define BIT_ATIMEND6_8822C BIT(21)
+#define BIT_ATIMEND5_8822C BIT(20)
+#define BIT_ATIMEND4_8822C BIT(19)
+#define BIT_ATIMEND3_8822C BIT(18)
+#define BIT_ATIMEND2_8822C BIT(17)
+#define BIT_ATIMEND1_8822C BIT(16)
+#define BIT_TXBCN7OK_8822C BIT(14)
+#define BIT_TXBCN6OK_8822C BIT(13)
+#define BIT_TXBCN5OK_8822C BIT(12)
+#define BIT_TXBCN4OK_8822C BIT(11)
+#define BIT_TXBCN3OK_8822C BIT(10)
+#define BIT_TXBCN2OK_8822C BIT(9)
+#define BIT_TXBCN1OK_8822C BIT(8)
+#define BIT_TXBCN7ERR_8822C BIT(6)
+#define BIT_TXBCN6ERR_8822C BIT(5)
+#define BIT_TXBCN5ERR_8822C BIT(4)
+#define BIT_TXBCN4ERR_8822C BIT(3)
+#define BIT_TXBCN3ERR_8822C BIT(2)
+#define BIT_TXBCN2ERR_8822C BIT(1)
+#define BIT_TXBCN1ERR_8822C BIT(0)
+
+/* 2 REG_HIMR3_8822C */
+#define BIT_WDT_PLATFORM_INT_MSK_8822C BIT(18)
+#define BIT_WDT_CPU_INT_MSK_8822C BIT(17)
+#define BIT_SETH2CDOK_MASK_8822C BIT(16)
+#define BIT_H2C_CMD_FULL_MASK_8822C BIT(15)
+#define BIT_PWR_INT_127_MASK_8822C BIT(14)
+#define BIT_TXSHORTCUT_TXDESUPDATEOK_MASK_8822C BIT(13)
+#define BIT_TXSHORTCUT_BKUPDATEOK_MASK_8822C BIT(12)
+#define BIT_TXSHORTCUT_BEUPDATEOK_MASK_8822C BIT(11)
+#define BIT_TXSHORTCUT_VIUPDATEOK_MAS_8822C BIT(10)
+#define BIT_TXSHORTCUT_VOUPDATEOK_MASK_8822C BIT(9)
+#define BIT_PWR_INT_127_MASK_V1_8822C BIT(8)
+#define BIT_PWR_INT_126TO96_MASK_8822C BIT(7)
+#define BIT_PWR_INT_95TO64_MASK_8822C BIT(6)
+#define BIT_PWR_INT_63TO32_MASK_8822C BIT(5)
+#define BIT_PWR_INT_31TO0_MASK_8822C BIT(4)
+#define BIT_RX_DMA_STUCK_MSK_8822C BIT(3)
+#define BIT_TX_DMA_STUCK_MSK_8822C BIT(2)
+#define BIT_DDMA0_LP_INT_MSK_8822C BIT(1)
+#define BIT_DDMA0_HP_INT_MSK_8822C BIT(0)
+
+/* 2 REG_HISR3_8822C */
+#define BIT_WDT_PLATFORM_INT_8822C BIT(18)
+#define BIT_WDT_CPU_INT_8822C BIT(17)
+#define BIT_SETH2CDOK_8822C BIT(16)
+#define BIT_H2C_CMD_FULL_8822C BIT(15)
+#define BIT_PWR_INT_127_8822C BIT(14)
+#define BIT_TXSHORTCUT_TXDESUPDATEOK_8822C BIT(13)
+#define BIT_TXSHORTCUT_BKUPDATEOK_8822C BIT(12)
+#define BIT_TXSHORTCUT_BEUPDATEOK_8822C BIT(11)
+#define BIT_TXSHORTCUT_VIUPDATEOK_8822C BIT(10)
+#define BIT_TXSHORTCUT_VOUPDATEOK_8822C BIT(9)
+#define BIT_PWR_INT_127_V1_8822C BIT(8)
+#define BIT_PWR_INT_126TO96_8822C BIT(7)
+#define BIT_PWR_INT_95TO64_8822C BIT(6)
+#define BIT_PWR_INT_63TO32_8822C BIT(5)
+#define BIT_PWR_INT_31TO0_8822C BIT(4)
+#define BIT_RX_DMA_STUCK_8822C BIT(3)
+#define BIT_TX_DMA_STUCK_8822C BIT(2)
+#define BIT_DDMA0_LP_INT_8822C BIT(1)
+#define BIT_DDMA0_HP_INT_8822C BIT(0)
+
+/* 2 REG_SW_MDIO_8822C */
+#define BIT_DIS_TIMEOUT_IO_8822C BIT(24)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_H2C_PKT_READADDR_8822C */
+
+#define BIT_SHIFT_H2C_PKT_READADDR_8822C 0
+#define BIT_MASK_H2C_PKT_READADDR_8822C 0x3ffff
+#define BIT_H2C_PKT_READADDR_8822C(x) \
+ (((x) & BIT_MASK_H2C_PKT_READADDR_8822C) \
+ << BIT_SHIFT_H2C_PKT_READADDR_8822C)
+#define BITS_H2C_PKT_READADDR_8822C \
+ (BIT_MASK_H2C_PKT_READADDR_8822C << BIT_SHIFT_H2C_PKT_READADDR_8822C)
+#define BIT_CLEAR_H2C_PKT_READADDR_8822C(x) \
+ ((x) & (~BITS_H2C_PKT_READADDR_8822C))
+#define BIT_GET_H2C_PKT_READADDR_8822C(x) \
+ (((x) >> BIT_SHIFT_H2C_PKT_READADDR_8822C) & \
+ BIT_MASK_H2C_PKT_READADDR_8822C)
+#define BIT_SET_H2C_PKT_READADDR_8822C(x, v) \
+ (BIT_CLEAR_H2C_PKT_READADDR_8822C(x) | BIT_H2C_PKT_READADDR_8822C(v))
+
+/* 2 REG_H2C_PKT_WRITEADDR_8822C */
+
+#define BIT_SHIFT_H2C_PKT_WRITEADDR_8822C 0
+#define BIT_MASK_H2C_PKT_WRITEADDR_8822C 0x3ffff
+#define BIT_H2C_PKT_WRITEADDR_8822C(x) \
+ (((x) & BIT_MASK_H2C_PKT_WRITEADDR_8822C) \
+ << BIT_SHIFT_H2C_PKT_WRITEADDR_8822C)
+#define BITS_H2C_PKT_WRITEADDR_8822C \
+ (BIT_MASK_H2C_PKT_WRITEADDR_8822C << BIT_SHIFT_H2C_PKT_WRITEADDR_8822C)
+#define BIT_CLEAR_H2C_PKT_WRITEADDR_8822C(x) \
+ ((x) & (~BITS_H2C_PKT_WRITEADDR_8822C))
+#define BIT_GET_H2C_PKT_WRITEADDR_8822C(x) \
+ (((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR_8822C) & \
+ BIT_MASK_H2C_PKT_WRITEADDR_8822C)
+#define BIT_SET_H2C_PKT_WRITEADDR_8822C(x, v) \
+ (BIT_CLEAR_H2C_PKT_WRITEADDR_8822C(x) | BIT_H2C_PKT_WRITEADDR_8822C(v))
+
+/* 2 REG_MEM_PWR_CRTL_8822C */
+#define BIT_MEM_BB_SD_8822C BIT(17)
+#define BIT_MEM_BB_DS_8822C BIT(16)
+#define BIT_MEM_BT_DS_8822C BIT(10)
+#define BIT_MEM_SDIO_LS_8822C BIT(9)
+#define BIT_MEM_SDIO_DS_8822C BIT(8)
+#define BIT_MEM_USB_LS_8822C BIT(7)
+#define BIT_MEM_USB_DS_8822C BIT(6)
+#define BIT_MEM_PCI_LS_8822C BIT(5)
+#define BIT_MEM_PCI_DS_8822C BIT(4)
+#define BIT_MEM_WLMAC_LS_8822C BIT(3)
+#define BIT_MEM_WLMAC_DS_8822C BIT(2)
+#define BIT_MEM_WLMCU_LS_8822C BIT(1)
+#define BIT_MEM_WLMCU_DS_8822C BIT(0)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_FW_DBG6_8822C */
+
+#define BIT_SHIFT_FW_DBG6_8822C 0
+#define BIT_MASK_FW_DBG6_8822C 0xffffffffL
+#define BIT_FW_DBG6_8822C(x) \
+ (((x) & BIT_MASK_FW_DBG6_8822C) << BIT_SHIFT_FW_DBG6_8822C)
+#define BITS_FW_DBG6_8822C (BIT_MASK_FW_DBG6_8822C << BIT_SHIFT_FW_DBG6_8822C)
+#define BIT_CLEAR_FW_DBG6_8822C(x) ((x) & (~BITS_FW_DBG6_8822C))
+#define BIT_GET_FW_DBG6_8822C(x) \
+ (((x) >> BIT_SHIFT_FW_DBG6_8822C) & BIT_MASK_FW_DBG6_8822C)
+#define BIT_SET_FW_DBG6_8822C(x, v) \
+ (BIT_CLEAR_FW_DBG6_8822C(x) | BIT_FW_DBG6_8822C(v))
+
+/* 2 REG_FW_DBG7_8822C */
+
+#define BIT_SHIFT_FW_DBG7_8822C 0
+#define BIT_MASK_FW_DBG7_8822C 0xffffffffL
+#define BIT_FW_DBG7_8822C(x) \
+ (((x) & BIT_MASK_FW_DBG7_8822C) << BIT_SHIFT_FW_DBG7_8822C)
+#define BITS_FW_DBG7_8822C (BIT_MASK_FW_DBG7_8822C << BIT_SHIFT_FW_DBG7_8822C)
+#define BIT_CLEAR_FW_DBG7_8822C(x) ((x) & (~BITS_FW_DBG7_8822C))
+#define BIT_GET_FW_DBG7_8822C(x) \
+ (((x) >> BIT_SHIFT_FW_DBG7_8822C) & BIT_MASK_FW_DBG7_8822C)
+#define BIT_SET_FW_DBG7_8822C(x, v) \
+ (BIT_CLEAR_FW_DBG7_8822C(x) | BIT_FW_DBG7_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_CR_8822C */
+
+#define BIT_SHIFT_LBMODE_8822C 24
+#define BIT_MASK_LBMODE_8822C 0x1f
+#define BIT_LBMODE_8822C(x) \
+ (((x) & BIT_MASK_LBMODE_8822C) << BIT_SHIFT_LBMODE_8822C)
+#define BITS_LBMODE_8822C (BIT_MASK_LBMODE_8822C << BIT_SHIFT_LBMODE_8822C)
+#define BIT_CLEAR_LBMODE_8822C(x) ((x) & (~BITS_LBMODE_8822C))
+#define BIT_GET_LBMODE_8822C(x) \
+ (((x) >> BIT_SHIFT_LBMODE_8822C) & BIT_MASK_LBMODE_8822C)
+#define BIT_SET_LBMODE_8822C(x, v) \
+ (BIT_CLEAR_LBMODE_8822C(x) | BIT_LBMODE_8822C(v))
+
+#define BIT_SHIFT_NETYPE1_8822C 18
+#define BIT_MASK_NETYPE1_8822C 0x3
+#define BIT_NETYPE1_8822C(x) \
+ (((x) & BIT_MASK_NETYPE1_8822C) << BIT_SHIFT_NETYPE1_8822C)
+#define BITS_NETYPE1_8822C (BIT_MASK_NETYPE1_8822C << BIT_SHIFT_NETYPE1_8822C)
+#define BIT_CLEAR_NETYPE1_8822C(x) ((x) & (~BITS_NETYPE1_8822C))
+#define BIT_GET_NETYPE1_8822C(x) \
+ (((x) >> BIT_SHIFT_NETYPE1_8822C) & BIT_MASK_NETYPE1_8822C)
+#define BIT_SET_NETYPE1_8822C(x, v) \
+ (BIT_CLEAR_NETYPE1_8822C(x) | BIT_NETYPE1_8822C(v))
+
+#define BIT_SHIFT_NETYPE0_8822C 16
+#define BIT_MASK_NETYPE0_8822C 0x3
+#define BIT_NETYPE0_8822C(x) \
+ (((x) & BIT_MASK_NETYPE0_8822C) << BIT_SHIFT_NETYPE0_8822C)
+#define BITS_NETYPE0_8822C (BIT_MASK_NETYPE0_8822C << BIT_SHIFT_NETYPE0_8822C)
+#define BIT_CLEAR_NETYPE0_8822C(x) ((x) & (~BITS_NETYPE0_8822C))
+#define BIT_GET_NETYPE0_8822C(x) \
+ (((x) >> BIT_SHIFT_NETYPE0_8822C) & BIT_MASK_NETYPE0_8822C)
+#define BIT_SET_NETYPE0_8822C(x, v) \
+ (BIT_CLEAR_NETYPE0_8822C(x) | BIT_NETYPE0_8822C(v))
+
+#define BIT_COUNTER_STS_EN_8822C BIT(13)
+#define BIT_I2C_MAILBOX_EN_8822C BIT(12)
+#define BIT_SHCUT_EN_8822C BIT(11)
+#define BIT_32K_CAL_TMR_EN_8822C BIT(10)
+#define BIT_MAC_SEC_EN_8822C BIT(9)
+#define BIT_ENSWBCN_8822C BIT(8)
+#define BIT_MACRXEN_8822C BIT(7)
+#define BIT_MACTXEN_8822C BIT(6)
+#define BIT_SCHEDULE_EN_8822C BIT(5)
+#define BIT_PROTOCOL_EN_8822C BIT(4)
+#define BIT_RXDMA_EN_8822C BIT(3)
+#define BIT_TXDMA_EN_8822C BIT(2)
+#define BIT_HCI_RXDMA_EN_8822C BIT(1)
+#define BIT_HCI_TXDMA_EN_8822C BIT(0)
+
+/* 2 REG_PG_SIZE_8822C */
+
+#define BIT_SHIFT_DBG_FIFO_SEL_8822C 16
+#define BIT_MASK_DBG_FIFO_SEL_8822C 0xff
+#define BIT_DBG_FIFO_SEL_8822C(x) \
+ (((x) & BIT_MASK_DBG_FIFO_SEL_8822C) << BIT_SHIFT_DBG_FIFO_SEL_8822C)
+#define BITS_DBG_FIFO_SEL_8822C \
+ (BIT_MASK_DBG_FIFO_SEL_8822C << BIT_SHIFT_DBG_FIFO_SEL_8822C)
+#define BIT_CLEAR_DBG_FIFO_SEL_8822C(x) ((x) & (~BITS_DBG_FIFO_SEL_8822C))
+#define BIT_GET_DBG_FIFO_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_DBG_FIFO_SEL_8822C) & BIT_MASK_DBG_FIFO_SEL_8822C)
+#define BIT_SET_DBG_FIFO_SEL_8822C(x, v) \
+ (BIT_CLEAR_DBG_FIFO_SEL_8822C(x) | BIT_DBG_FIFO_SEL_8822C(v))
+
+/* 2 REG_PKT_BUFF_ACCESS_CTRL_8822C */
+
+#define BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8822C 0
+#define BIT_MASK_PKT_BUFF_ACCESS_CTRL_8822C 0xff
+#define BIT_PKT_BUFF_ACCESS_CTRL_8822C(x) \
+ (((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL_8822C) \
+ << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8822C)
+#define BITS_PKT_BUFF_ACCESS_CTRL_8822C \
+ (BIT_MASK_PKT_BUFF_ACCESS_CTRL_8822C \
+ << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8822C)
+#define BIT_CLEAR_PKT_BUFF_ACCESS_CTRL_8822C(x) \
+ ((x) & (~BITS_PKT_BUFF_ACCESS_CTRL_8822C))
+#define BIT_GET_PKT_BUFF_ACCESS_CTRL_8822C(x) \
+ (((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8822C) & \
+ BIT_MASK_PKT_BUFF_ACCESS_CTRL_8822C)
+#define BIT_SET_PKT_BUFF_ACCESS_CTRL_8822C(x, v) \
+ (BIT_CLEAR_PKT_BUFF_ACCESS_CTRL_8822C(x) | \
+ BIT_PKT_BUFF_ACCESS_CTRL_8822C(v))
+
+/* 2 REG_TSF_CLK_STATE_8822C */
+#define BIT_TSF_CLK_STABLE_8822C BIT(15)
+
+/* 2 REG_TXDMA_PQ_MAP_8822C */
+#define BIT_CSI_BW_EN_8822C BIT(31)
+
+#define BIT_SHIFT_TXDMA_H2C_MAP_8822C 16
+#define BIT_MASK_TXDMA_H2C_MAP_8822C 0x3
+#define BIT_TXDMA_H2C_MAP_8822C(x) \
+ (((x) & BIT_MASK_TXDMA_H2C_MAP_8822C) << BIT_SHIFT_TXDMA_H2C_MAP_8822C)
+#define BITS_TXDMA_H2C_MAP_8822C \
+ (BIT_MASK_TXDMA_H2C_MAP_8822C << BIT_SHIFT_TXDMA_H2C_MAP_8822C)
+#define BIT_CLEAR_TXDMA_H2C_MAP_8822C(x) ((x) & (~BITS_TXDMA_H2C_MAP_8822C))
+#define BIT_GET_TXDMA_H2C_MAP_8822C(x) \
+ (((x) >> BIT_SHIFT_TXDMA_H2C_MAP_8822C) & BIT_MASK_TXDMA_H2C_MAP_8822C)
+#define BIT_SET_TXDMA_H2C_MAP_8822C(x, v) \
+ (BIT_CLEAR_TXDMA_H2C_MAP_8822C(x) | BIT_TXDMA_H2C_MAP_8822C(v))
+
+#define BIT_SHIFT_TXDMA_HIQ_MAP_8822C 14
+#define BIT_MASK_TXDMA_HIQ_MAP_8822C 0x3
+#define BIT_TXDMA_HIQ_MAP_8822C(x) \
+ (((x) & BIT_MASK_TXDMA_HIQ_MAP_8822C) << BIT_SHIFT_TXDMA_HIQ_MAP_8822C)
+#define BITS_TXDMA_HIQ_MAP_8822C \
+ (BIT_MASK_TXDMA_HIQ_MAP_8822C << BIT_SHIFT_TXDMA_HIQ_MAP_8822C)
+#define BIT_CLEAR_TXDMA_HIQ_MAP_8822C(x) ((x) & (~BITS_TXDMA_HIQ_MAP_8822C))
+#define BIT_GET_TXDMA_HIQ_MAP_8822C(x) \
+ (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8822C) & BIT_MASK_TXDMA_HIQ_MAP_8822C)
+#define BIT_SET_TXDMA_HIQ_MAP_8822C(x, v) \
+ (BIT_CLEAR_TXDMA_HIQ_MAP_8822C(x) | BIT_TXDMA_HIQ_MAP_8822C(v))
+
+#define BIT_SHIFT_TXDMA_MGQ_MAP_8822C 12
+#define BIT_MASK_TXDMA_MGQ_MAP_8822C 0x3
+#define BIT_TXDMA_MGQ_MAP_8822C(x) \
+ (((x) & BIT_MASK_TXDMA_MGQ_MAP_8822C) << BIT_SHIFT_TXDMA_MGQ_MAP_8822C)
+#define BITS_TXDMA_MGQ_MAP_8822C \
+ (BIT_MASK_TXDMA_MGQ_MAP_8822C << BIT_SHIFT_TXDMA_MGQ_MAP_8822C)
+#define BIT_CLEAR_TXDMA_MGQ_MAP_8822C(x) ((x) & (~BITS_TXDMA_MGQ_MAP_8822C))
+#define BIT_GET_TXDMA_MGQ_MAP_8822C(x) \
+ (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8822C) & BIT_MASK_TXDMA_MGQ_MAP_8822C)
+#define BIT_SET_TXDMA_MGQ_MAP_8822C(x, v) \
+ (BIT_CLEAR_TXDMA_MGQ_MAP_8822C(x) | BIT_TXDMA_MGQ_MAP_8822C(v))
+
+#define BIT_SHIFT_TXDMA_BKQ_MAP_8822C 10
+#define BIT_MASK_TXDMA_BKQ_MAP_8822C 0x3
+#define BIT_TXDMA_BKQ_MAP_8822C(x) \
+ (((x) & BIT_MASK_TXDMA_BKQ_MAP_8822C) << BIT_SHIFT_TXDMA_BKQ_MAP_8822C)
+#define BITS_TXDMA_BKQ_MAP_8822C \
+ (BIT_MASK_TXDMA_BKQ_MAP_8822C << BIT_SHIFT_TXDMA_BKQ_MAP_8822C)
+#define BIT_CLEAR_TXDMA_BKQ_MAP_8822C(x) ((x) & (~BITS_TXDMA_BKQ_MAP_8822C))
+#define BIT_GET_TXDMA_BKQ_MAP_8822C(x) \
+ (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8822C) & BIT_MASK_TXDMA_BKQ_MAP_8822C)
+#define BIT_SET_TXDMA_BKQ_MAP_8822C(x, v) \
+ (BIT_CLEAR_TXDMA_BKQ_MAP_8822C(x) | BIT_TXDMA_BKQ_MAP_8822C(v))
+
+#define BIT_SHIFT_TXDMA_BEQ_MAP_8822C 8
+#define BIT_MASK_TXDMA_BEQ_MAP_8822C 0x3
+#define BIT_TXDMA_BEQ_MAP_8822C(x) \
+ (((x) & BIT_MASK_TXDMA_BEQ_MAP_8822C) << BIT_SHIFT_TXDMA_BEQ_MAP_8822C)
+#define BITS_TXDMA_BEQ_MAP_8822C \
+ (BIT_MASK_TXDMA_BEQ_MAP_8822C << BIT_SHIFT_TXDMA_BEQ_MAP_8822C)
+#define BIT_CLEAR_TXDMA_BEQ_MAP_8822C(x) ((x) & (~BITS_TXDMA_BEQ_MAP_8822C))
+#define BIT_GET_TXDMA_BEQ_MAP_8822C(x) \
+ (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8822C) & BIT_MASK_TXDMA_BEQ_MAP_8822C)
+#define BIT_SET_TXDMA_BEQ_MAP_8822C(x, v) \
+ (BIT_CLEAR_TXDMA_BEQ_MAP_8822C(x) | BIT_TXDMA_BEQ_MAP_8822C(v))
+
+#define BIT_SHIFT_TXDMA_VIQ_MAP_8822C 6
+#define BIT_MASK_TXDMA_VIQ_MAP_8822C 0x3
+#define BIT_TXDMA_VIQ_MAP_8822C(x) \
+ (((x) & BIT_MASK_TXDMA_VIQ_MAP_8822C) << BIT_SHIFT_TXDMA_VIQ_MAP_8822C)
+#define BITS_TXDMA_VIQ_MAP_8822C \
+ (BIT_MASK_TXDMA_VIQ_MAP_8822C << BIT_SHIFT_TXDMA_VIQ_MAP_8822C)
+#define BIT_CLEAR_TXDMA_VIQ_MAP_8822C(x) ((x) & (~BITS_TXDMA_VIQ_MAP_8822C))
+#define BIT_GET_TXDMA_VIQ_MAP_8822C(x) \
+ (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8822C) & BIT_MASK_TXDMA_VIQ_MAP_8822C)
+#define BIT_SET_TXDMA_VIQ_MAP_8822C(x, v) \
+ (BIT_CLEAR_TXDMA_VIQ_MAP_8822C(x) | BIT_TXDMA_VIQ_MAP_8822C(v))
+
+#define BIT_SHIFT_TXDMA_VOQ_MAP_8822C 4
+#define BIT_MASK_TXDMA_VOQ_MAP_8822C 0x3
+#define BIT_TXDMA_VOQ_MAP_8822C(x) \
+ (((x) & BIT_MASK_TXDMA_VOQ_MAP_8822C) << BIT_SHIFT_TXDMA_VOQ_MAP_8822C)
+#define BITS_TXDMA_VOQ_MAP_8822C \
+ (BIT_MASK_TXDMA_VOQ_MAP_8822C << BIT_SHIFT_TXDMA_VOQ_MAP_8822C)
+#define BIT_CLEAR_TXDMA_VOQ_MAP_8822C(x) ((x) & (~BITS_TXDMA_VOQ_MAP_8822C))
+#define BIT_GET_TXDMA_VOQ_MAP_8822C(x) \
+ (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8822C) & BIT_MASK_TXDMA_VOQ_MAP_8822C)
+#define BIT_SET_TXDMA_VOQ_MAP_8822C(x, v) \
+ (BIT_CLEAR_TXDMA_VOQ_MAP_8822C(x) | BIT_TXDMA_VOQ_MAP_8822C(v))
+
+#define BIT_TXDMA_BW_EN_8822C BIT(3)
+#define BIT_RXDMA_AGG_EN_8822C BIT(2)
+#define BIT_RXSHFT_EN_8822C BIT(1)
+#define BIT_RXDMA_ARBBW_EN_8822C BIT(0)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_TRXFF_BNDY_8822C */
+
+#define BIT_SHIFT_FWFFOVFL_RSV_8822C 16
+#define BIT_MASK_FWFFOVFL_RSV_8822C 0xf
+#define BIT_FWFFOVFL_RSV_8822C(x) \
+ (((x) & BIT_MASK_FWFFOVFL_RSV_8822C) << BIT_SHIFT_FWFFOVFL_RSV_8822C)
+#define BITS_FWFFOVFL_RSV_8822C \
+ (BIT_MASK_FWFFOVFL_RSV_8822C << BIT_SHIFT_FWFFOVFL_RSV_8822C)
+#define BIT_CLEAR_FWFFOVFL_RSV_8822C(x) ((x) & (~BITS_FWFFOVFL_RSV_8822C))
+#define BIT_GET_FWFFOVFL_RSV_8822C(x) \
+ (((x) >> BIT_SHIFT_FWFFOVFL_RSV_8822C) & BIT_MASK_FWFFOVFL_RSV_8822C)
+#define BIT_SET_FWFFOVFL_RSV_8822C(x, v) \
+ (BIT_CLEAR_FWFFOVFL_RSV_8822C(x) | BIT_FWFFOVFL_RSV_8822C(v))
+
+#define BIT_SHIFT_RXFFOVFL_RSV_V2_8822C 8
+#define BIT_MASK_RXFFOVFL_RSV_V2_8822C 0xf
+#define BIT_RXFFOVFL_RSV_V2_8822C(x) \
+ (((x) & BIT_MASK_RXFFOVFL_RSV_V2_8822C) \
+ << BIT_SHIFT_RXFFOVFL_RSV_V2_8822C)
+#define BITS_RXFFOVFL_RSV_V2_8822C \
+ (BIT_MASK_RXFFOVFL_RSV_V2_8822C << BIT_SHIFT_RXFFOVFL_RSV_V2_8822C)
+#define BIT_CLEAR_RXFFOVFL_RSV_V2_8822C(x) ((x) & (~BITS_RXFFOVFL_RSV_V2_8822C))
+#define BIT_GET_RXFFOVFL_RSV_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8822C) & \
+ BIT_MASK_RXFFOVFL_RSV_V2_8822C)
+#define BIT_SET_RXFFOVFL_RSV_V2_8822C(x, v) \
+ (BIT_CLEAR_RXFFOVFL_RSV_V2_8822C(x) | BIT_RXFFOVFL_RSV_V2_8822C(v))
+
+/* 2 REG_PTA_I2C_MBOX_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_I2C_M_STATUS_8822C 8
+#define BIT_MASK_I2C_M_STATUS_8822C 0xf
+#define BIT_I2C_M_STATUS_8822C(x) \
+ (((x) & BIT_MASK_I2C_M_STATUS_8822C) << BIT_SHIFT_I2C_M_STATUS_8822C)
+#define BITS_I2C_M_STATUS_8822C \
+ (BIT_MASK_I2C_M_STATUS_8822C << BIT_SHIFT_I2C_M_STATUS_8822C)
+#define BIT_CLEAR_I2C_M_STATUS_8822C(x) ((x) & (~BITS_I2C_M_STATUS_8822C))
+#define BIT_GET_I2C_M_STATUS_8822C(x) \
+ (((x) >> BIT_SHIFT_I2C_M_STATUS_8822C) & BIT_MASK_I2C_M_STATUS_8822C)
+#define BIT_SET_I2C_M_STATUS_8822C(x, v) \
+ (BIT_CLEAR_I2C_M_STATUS_8822C(x) | BIT_I2C_M_STATUS_8822C(v))
+
+#define BIT_SHIFT_I2C_M_BUS_GNT_FW_8822C 4
+#define BIT_MASK_I2C_M_BUS_GNT_FW_8822C 0x7
+#define BIT_I2C_M_BUS_GNT_FW_8822C(x) \
+ (((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8822C) \
+ << BIT_SHIFT_I2C_M_BUS_GNT_FW_8822C)
+#define BITS_I2C_M_BUS_GNT_FW_8822C \
+ (BIT_MASK_I2C_M_BUS_GNT_FW_8822C << BIT_SHIFT_I2C_M_BUS_GNT_FW_8822C)
+#define BIT_CLEAR_I2C_M_BUS_GNT_FW_8822C(x) \
+ ((x) & (~BITS_I2C_M_BUS_GNT_FW_8822C))
+#define BIT_GET_I2C_M_BUS_GNT_FW_8822C(x) \
+ (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8822C) & \
+ BIT_MASK_I2C_M_BUS_GNT_FW_8822C)
+#define BIT_SET_I2C_M_BUS_GNT_FW_8822C(x, v) \
+ (BIT_CLEAR_I2C_M_BUS_GNT_FW_8822C(x) | BIT_I2C_M_BUS_GNT_FW_8822C(v))
+
+#define BIT_I2C_M_GNT_FW_8822C BIT(3)
+
+#define BIT_SHIFT_I2C_M_SPEED_8822C 1
+#define BIT_MASK_I2C_M_SPEED_8822C 0x3
+#define BIT_I2C_M_SPEED_8822C(x) \
+ (((x) & BIT_MASK_I2C_M_SPEED_8822C) << BIT_SHIFT_I2C_M_SPEED_8822C)
+#define BITS_I2C_M_SPEED_8822C \
+ (BIT_MASK_I2C_M_SPEED_8822C << BIT_SHIFT_I2C_M_SPEED_8822C)
+#define BIT_CLEAR_I2C_M_SPEED_8822C(x) ((x) & (~BITS_I2C_M_SPEED_8822C))
+#define BIT_GET_I2C_M_SPEED_8822C(x) \
+ (((x) >> BIT_SHIFT_I2C_M_SPEED_8822C) & BIT_MASK_I2C_M_SPEED_8822C)
+#define BIT_SET_I2C_M_SPEED_8822C(x, v) \
+ (BIT_CLEAR_I2C_M_SPEED_8822C(x) | BIT_I2C_M_SPEED_8822C(v))
+
+#define BIT_I2C_M_UNLOCK_8822C BIT(0)
+
+/* 2 REG_RXFF_BNDY_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_RXFF0_BNDY_V2_8822C 0
+#define BIT_MASK_RXFF0_BNDY_V2_8822C 0x3ffff
+#define BIT_RXFF0_BNDY_V2_8822C(x) \
+ (((x) & BIT_MASK_RXFF0_BNDY_V2_8822C) << BIT_SHIFT_RXFF0_BNDY_V2_8822C)
+#define BITS_RXFF0_BNDY_V2_8822C \
+ (BIT_MASK_RXFF0_BNDY_V2_8822C << BIT_SHIFT_RXFF0_BNDY_V2_8822C)
+#define BIT_CLEAR_RXFF0_BNDY_V2_8822C(x) ((x) & (~BITS_RXFF0_BNDY_V2_8822C))
+#define BIT_GET_RXFF0_BNDY_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8822C) & BIT_MASK_RXFF0_BNDY_V2_8822C)
+#define BIT_SET_RXFF0_BNDY_V2_8822C(x, v) \
+ (BIT_CLEAR_RXFF0_BNDY_V2_8822C(x) | BIT_RXFF0_BNDY_V2_8822C(v))
+
+/* 2 REG_FE1IMR_8822C */
+#define BIT_FS_SW_PLL_LEAVE_32K_INT_EN_8822C BIT(31)
+#define BIT_FS_FWFF_FULL_INT_EN_8822C BIT(30)
+#define BIT_FS_BB_STOP_RX_INT_EN_8822C BIT(29)
+#define BIT_FS_RXDMA2_DONE_INT_EN_8822C BIT(28)
+#define BIT_FS_RXDONE2_INT_EN_8822C BIT(26)
+#define BIT_FS_RX_BCN_P4_INT_EN_8822C BIT(25)
+#define BIT_FS_RX_BCN_P3_INT_EN_8822C BIT(24)
+#define BIT_FS_RX_BCN_P2_INT_EN_8822C BIT(23)
+#define BIT_FS_RX_BCN_P1_INT_EN_8822C BIT(22)
+#define BIT_FS_RX_BCN_P0_INT_EN_8822C BIT(21)
+#define BIT_FS_RX_UMD0_INT_EN_8822C BIT(20)
+#define BIT_FS_RX_UMD1_INT_EN_8822C BIT(19)
+#define BIT_FS_RX_BMD0_INT_EN_8822C BIT(18)
+#define BIT_FS_RX_BMD1_INT_EN_8822C BIT(17)
+#define BIT_FS_RXDONE_INT_EN_8822C BIT(16)
+#define BIT_FS_WWLAN_INT_EN_8822C BIT(15)
+#define BIT_FS_SOUND_DONE_INT_EN_8822C BIT(14)
+#define BIT_FS_BF1_PRETO_INT_EN_8822C BIT(11)
+#define BIT_FS_BF0_PRETO_INT_EN_8822C BIT(10)
+#define BIT_FS_PTCL_RELEASE_MACID_INT_EN_8822C BIT(9)
+#define BIT_FS_PRETX_ERRHLD_INT_EN_8822C BIT(8)
+#define BIT_FS_LTE_COEX_EN_8822C BIT(6)
+#define BIT_FS_WLACTOFF_INT_EN_8822C BIT(5)
+#define BIT_FS_WLACTON_INT_EN_8822C BIT(4)
+#define BIT_FS_BTCMD_INT_EN_8822C BIT(3)
+#define BIT_FS_REG_MAILBOX_TO_I2C_INT_EN_8822C BIT(2)
+#define BIT_FS_TRPC_TO_INT_EN_V1_8822C BIT(1)
+#define BIT_FS_RPC_O_T_INT_EN_V1_8822C BIT(0)
+
+/* 2 REG_FE1ISR_8822C */
+#define BIT_FS_SW_PLL_LEAVE_32K_INT_8822C BIT(31)
+#define BIT_FS_FS_FWFF_FULL_INT_8822C BIT(30)
+#define BIT_FS_BB_STOP_RX_INT_8822C BIT(29)
+#define BIT_FS_RXDMA2_DONE_INT_8822C BIT(28)
+#define BIT_FS_RXDONE2_INT_8822C BIT(26)
+#define BIT_FS_RX_BCN_P4_INT_8822C BIT(25)
+#define BIT_FS_RX_BCN_P3_INT_8822C BIT(24)
+#define BIT_FS_RX_BCN_P2_INT_8822C BIT(23)
+#define BIT_FS_RX_BCN_P1_INT_8822C BIT(22)
+#define BIT_FS_RX_BCN_P0_INT_8822C BIT(21)
+#define BIT_FS_RX_UMD0_INT_8822C BIT(20)
+#define BIT_FS_RX_UMD1_INT_8822C BIT(19)
+#define BIT_FS_RX_BMD0_INT_8822C BIT(18)
+#define BIT_FS_RX_BMD1_INT_8822C BIT(17)
+#define BIT_FS_RXDONE_INT_8822C BIT(16)
+#define BIT_FS_WWLAN_INT_8822C BIT(15)
+#define BIT_FS_SOUND_DONE_INT_8822C BIT(14)
+#define BIT_FS_BF1_PRETO_INT_8822C BIT(11)
+#define BIT_FS_BF0_PRETO_INT_8822C BIT(10)
+#define BIT_FS_PTCL_RELEASE_MACID_INT_8822C BIT(9)
+#define BIT_FS_PRETX_ERRHLD_INT_8822C BIT(8)
+#define BIT_FS_LTE_COEX_INT_8822C BIT(6)
+#define BIT_FS_WLACTOFF_INT_8822C BIT(5)
+#define BIT_FS_WLACTON_INT_8822C BIT(4)
+#define BIT_FS_BCN_RX_INT_INT_8822C BIT(3)
+#define BIT_FS_MAILBOX_TO_I2C_INT_8822C BIT(2)
+#define BIT_FS_TRPC_TO_INT_8822C BIT(1)
+#define BIT_FS_RPC_O_T_INT_8822C BIT(0)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_CPWM_8822C */
+#define BIT_CPWM_TOGGLING_8822C BIT(31)
+
+#define BIT_SHIFT_CPWM_MOD_8822C 24
+#define BIT_MASK_CPWM_MOD_8822C 0x7f
+#define BIT_CPWM_MOD_8822C(x) \
+ (((x) & BIT_MASK_CPWM_MOD_8822C) << BIT_SHIFT_CPWM_MOD_8822C)
+#define BITS_CPWM_MOD_8822C \
+ (BIT_MASK_CPWM_MOD_8822C << BIT_SHIFT_CPWM_MOD_8822C)
+#define BIT_CLEAR_CPWM_MOD_8822C(x) ((x) & (~BITS_CPWM_MOD_8822C))
+#define BIT_GET_CPWM_MOD_8822C(x) \
+ (((x) >> BIT_SHIFT_CPWM_MOD_8822C) & BIT_MASK_CPWM_MOD_8822C)
+#define BIT_SET_CPWM_MOD_8822C(x, v) \
+ (BIT_CLEAR_CPWM_MOD_8822C(x) | BIT_CPWM_MOD_8822C(v))
+
+/* 2 REG_FWIMR_8822C */
+#define BIT_FS_TXBCNOK_MB7_INT_EN_8822C BIT(31)
+#define BIT_FS_TXBCNOK_MB6_INT_EN_8822C BIT(30)
+#define BIT_FS_TXBCNOK_MB5_INT_EN_8822C BIT(29)
+#define BIT_FS_TXBCNOK_MB4_INT_EN_8822C BIT(28)
+#define BIT_FS_TXBCNOK_MB3_INT_EN_8822C BIT(27)
+#define BIT_FS_TXBCNOK_MB2_INT_EN_8822C BIT(26)
+#define BIT_FS_TXBCNOK_MB1_INT_EN_8822C BIT(25)
+#define BIT_FS_TXBCNOK_MB0_INT_EN_8822C BIT(24)
+#define BIT_FS_TXBCNERR_MB7_INT_EN_8822C BIT(23)
+#define BIT_FS_TXBCNERR_MB6_INT_EN_8822C BIT(22)
+#define BIT_FS_TXBCNERR_MB5_INT_EN_8822C BIT(21)
+#define BIT_FS_TXBCNERR_MB4_INT_EN_8822C BIT(20)
+#define BIT_FS_TXBCNERR_MB3_INT_EN_8822C BIT(19)
+#define BIT_FS_TXBCNERR_MB2_INT_EN_8822C BIT(18)
+#define BIT_FS_TXBCNERR_MB1_INT_EN_8822C BIT(17)
+#define BIT_FS_TXBCNERR_MB0_INT_EN_8822C BIT(16)
+#define BIT_CPU_MGQ_TXDONE_INT_EN_8822C BIT(15)
+#define BIT_SIFS_OVERSPEC_INT_EN_8822C BIT(14)
+#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_EN_8822C BIT(13)
+#define BIT_FS_MGNTQFF_TO_INT_EN_8822C BIT(12)
+#define BIT_FS_CPUMGQ_ERR_INT_EN_8822C BIT(11)
+#define BIT_FS_DDMA0_LP_INT_EN_8822C BIT(9)
+#define BIT_FS_DDMA0_HP_INT_EN_8822C BIT(8)
+#define BIT_FS_TRXRPT_INT_EN_8822C BIT(7)
+#define BIT_FS_C2H_W_READY_INT_EN_8822C BIT(6)
+#define BIT_FS_HRCV_INT_EN_8822C BIT(5)
+#define BIT_FS_H2CCMD_INT_EN_8822C BIT(4)
+#define BIT_FS_TXPKTIN_INT_EN_8822C BIT(3)
+#define BIT_FS_ERRORHDL_INT_EN_8822C BIT(2)
+#define BIT_FS_TXCCX_INT_EN_8822C BIT(1)
+#define BIT_FS_TXCLOSE_INT_EN_8822C BIT(0)
+
+/* 2 REG_FWISR_8822C */
+#define BIT_FS_TXBCNOK_MB7_INT_8822C BIT(31)
+#define BIT_FS_TXBCNOK_MB6_INT_8822C BIT(30)
+#define BIT_FS_TXBCNOK_MB5_INT_8822C BIT(29)
+#define BIT_FS_TXBCNOK_MB4_INT_8822C BIT(28)
+#define BIT_FS_TXBCNOK_MB3_INT_8822C BIT(27)
+#define BIT_FS_TXBCNOK_MB2_INT_8822C BIT(26)
+#define BIT_FS_TXBCNOK_MB1_INT_8822C BIT(25)
+#define BIT_FS_TXBCNOK_MB0_INT_8822C BIT(24)
+#define BIT_FS_TXBCNERR_MB7_INT_8822C BIT(23)
+#define BIT_FS_TXBCNERR_MB6_INT_8822C BIT(22)
+#define BIT_FS_TXBCNERR_MB5_INT_8822C BIT(21)
+#define BIT_FS_TXBCNERR_MB4_INT_8822C BIT(20)
+#define BIT_FS_TXBCNERR_MB3_INT_8822C BIT(19)
+#define BIT_FS_TXBCNERR_MB2_INT_8822C BIT(18)
+#define BIT_FS_TXBCNERR_MB1_INT_8822C BIT(17)
+#define BIT_FS_TXBCNERR_MB0_INT_8822C BIT(16)
+#define BIT_CPU_MGQ_TXDONE_INT_8822C BIT(15)
+#define BIT_SIFS_OVERSPEC_INT_8822C BIT(14)
+#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_8822C BIT(13)
+#define BIT_FS_MGNTQFF_TO_INT_8822C BIT(12)
+#define BIT_FS_CPUMGQ_ERR_INT_8822C BIT(11)
+#define BIT_FS_DDMA0_LP_INT_8822C BIT(9)
+#define BIT_FS_DDMA0_HP_INT_8822C BIT(8)
+#define BIT_FS_TRXRPT_INT_8822C BIT(7)
+#define BIT_FS_C2H_W_READY_INT_8822C BIT(6)
+#define BIT_FS_HRCV_INT_8822C BIT(5)
+#define BIT_FS_H2CCMD_INT_8822C BIT(4)
+#define BIT_FS_TXPKTIN_INT_8822C BIT(3)
+#define BIT_FS_ERRORHDL_INT_8822C BIT(2)
+#define BIT_FS_TXCCX_INT_8822C BIT(1)
+#define BIT_FS_TXCLOSE_INT_8822C BIT(0)
+
+/* 2 REG_FTIMR_8822C */
+#define BIT_PS_TIMER_C_EARLY_INT_EN_8822C BIT(23)
+#define BIT_PS_TIMER_B_EARLY_INT_EN_8822C BIT(22)
+#define BIT_PS_TIMER_A_EARLY_INT_EN_8822C BIT(21)
+#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_EN_8822C BIT(20)
+#define BIT_PS_TIMER_C_INT_EN_8822C BIT(19)
+#define BIT_PS_TIMER_B_INT_EN_8822C BIT(18)
+#define BIT_PS_TIMER_A_INT_EN_8822C BIT(17)
+#define BIT_CPUMGQ_TX_TIMER_INT_EN_8822C BIT(16)
+#define BIT_FS_PS_TIMEOUT2_EN_8822C BIT(15)
+#define BIT_FS_PS_TIMEOUT1_EN_8822C BIT(14)
+#define BIT_FS_PS_TIMEOUT0_EN_8822C BIT(13)
+#define BIT_FS_GTINT8_EN_8822C BIT(8)
+#define BIT_FS_GTINT7_EN_8822C BIT(7)
+#define BIT_FS_GTINT6_EN_8822C BIT(6)
+#define BIT_FS_GTINT5_EN_8822C BIT(5)
+#define BIT_FS_GTINT4_EN_8822C BIT(4)
+#define BIT_FS_GTINT3_EN_8822C BIT(3)
+#define BIT_FS_GTINT2_EN_8822C BIT(2)
+#define BIT_FS_GTINT1_EN_8822C BIT(1)
+#define BIT_FS_GTINT0_EN_8822C BIT(0)
+
+/* 2 REG_FTISR_8822C */
+#define BIT_PS_TIMER_C_EARLY__INT_8822C BIT(23)
+#define BIT_PS_TIMER_B_EARLY__INT_8822C BIT(22)
+#define BIT_PS_TIMER_A_EARLY__INT_8822C BIT(21)
+#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_8822C BIT(20)
+#define BIT_PS_TIMER_C_INT_8822C BIT(19)
+#define BIT_PS_TIMER_B_INT_8822C BIT(18)
+#define BIT_PS_TIMER_A_INT_8822C BIT(17)
+#define BIT_CPUMGQ_TX_TIMER_INT_8822C BIT(16)
+#define BIT_FS_PS_TIMEOUT2_INT_8822C BIT(15)
+#define BIT_FS_PS_TIMEOUT1_INT_8822C BIT(14)
+#define BIT_FS_PS_TIMEOUT0_INT_8822C BIT(13)
+#define BIT_FS_GTINT8_INT_8822C BIT(8)
+#define BIT_FS_GTINT7_INT_8822C BIT(7)
+#define BIT_FS_GTINT6_INT_8822C BIT(6)
+#define BIT_FS_GTINT5_INT_8822C BIT(5)
+#define BIT_FS_GTINT4_INT_8822C BIT(4)
+#define BIT_FS_GTINT3_INT_8822C BIT(3)
+#define BIT_FS_GTINT2_INT_8822C BIT(2)
+#define BIT_FS_GTINT1_INT_8822C BIT(1)
+#define BIT_FS_GTINT0_INT_8822C BIT(0)
+
+/* 2 REG_PKTBUF_DBG_CTRL_8822C */
+
+#define BIT_SHIFT_PKTBUF_WRITE_EN_8822C 24
+#define BIT_MASK_PKTBUF_WRITE_EN_8822C 0xff
+#define BIT_PKTBUF_WRITE_EN_8822C(x) \
+ (((x) & BIT_MASK_PKTBUF_WRITE_EN_8822C) \
+ << BIT_SHIFT_PKTBUF_WRITE_EN_8822C)
+#define BITS_PKTBUF_WRITE_EN_8822C \
+ (BIT_MASK_PKTBUF_WRITE_EN_8822C << BIT_SHIFT_PKTBUF_WRITE_EN_8822C)
+#define BIT_CLEAR_PKTBUF_WRITE_EN_8822C(x) ((x) & (~BITS_PKTBUF_WRITE_EN_8822C))
+#define BIT_GET_PKTBUF_WRITE_EN_8822C(x) \
+ (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8822C) & \
+ BIT_MASK_PKTBUF_WRITE_EN_8822C)
+#define BIT_SET_PKTBUF_WRITE_EN_8822C(x, v) \
+ (BIT_CLEAR_PKTBUF_WRITE_EN_8822C(x) | BIT_PKTBUF_WRITE_EN_8822C(v))
+
+#define BIT_TXRPTBUF_DBG_8822C BIT(23)
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_TXPKTBUF_DBG_V2_8822C BIT(20)
+#define BIT_RXPKTBUF_DBG_8822C BIT(16)
+
+#define BIT_SHIFT_PKTBUF_DBG_ADDR_8822C 0
+#define BIT_MASK_PKTBUF_DBG_ADDR_8822C 0x1fff
+#define BIT_PKTBUF_DBG_ADDR_8822C(x) \
+ (((x) & BIT_MASK_PKTBUF_DBG_ADDR_8822C) \
+ << BIT_SHIFT_PKTBUF_DBG_ADDR_8822C)
+#define BITS_PKTBUF_DBG_ADDR_8822C \
+ (BIT_MASK_PKTBUF_DBG_ADDR_8822C << BIT_SHIFT_PKTBUF_DBG_ADDR_8822C)
+#define BIT_CLEAR_PKTBUF_DBG_ADDR_8822C(x) ((x) & (~BITS_PKTBUF_DBG_ADDR_8822C))
+#define BIT_GET_PKTBUF_DBG_ADDR_8822C(x) \
+ (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8822C) & \
+ BIT_MASK_PKTBUF_DBG_ADDR_8822C)
+#define BIT_SET_PKTBUF_DBG_ADDR_8822C(x, v) \
+ (BIT_CLEAR_PKTBUF_DBG_ADDR_8822C(x) | BIT_PKTBUF_DBG_ADDR_8822C(v))
+
+/* 2 REG_PKTBUF_DBG_DATA_L_8822C */
+
+#define BIT_SHIFT_PKTBUF_DBG_DATA_L_8822C 0
+#define BIT_MASK_PKTBUF_DBG_DATA_L_8822C 0xffffffffL
+#define BIT_PKTBUF_DBG_DATA_L_8822C(x) \
+ (((x) & BIT_MASK_PKTBUF_DBG_DATA_L_8822C) \
+ << BIT_SHIFT_PKTBUF_DBG_DATA_L_8822C)
+#define BITS_PKTBUF_DBG_DATA_L_8822C \
+ (BIT_MASK_PKTBUF_DBG_DATA_L_8822C << BIT_SHIFT_PKTBUF_DBG_DATA_L_8822C)
+#define BIT_CLEAR_PKTBUF_DBG_DATA_L_8822C(x) \
+ ((x) & (~BITS_PKTBUF_DBG_DATA_L_8822C))
+#define BIT_GET_PKTBUF_DBG_DATA_L_8822C(x) \
+ (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8822C) & \
+ BIT_MASK_PKTBUF_DBG_DATA_L_8822C)
+#define BIT_SET_PKTBUF_DBG_DATA_L_8822C(x, v) \
+ (BIT_CLEAR_PKTBUF_DBG_DATA_L_8822C(x) | BIT_PKTBUF_DBG_DATA_L_8822C(v))
+
+/* 2 REG_PKTBUF_DBG_DATA_H_8822C */
+
+#define BIT_SHIFT_PKTBUF_DBG_DATA_H_8822C 0
+#define BIT_MASK_PKTBUF_DBG_DATA_H_8822C 0xffffffffL
+#define BIT_PKTBUF_DBG_DATA_H_8822C(x) \
+ (((x) & BIT_MASK_PKTBUF_DBG_DATA_H_8822C) \
+ << BIT_SHIFT_PKTBUF_DBG_DATA_H_8822C)
+#define BITS_PKTBUF_DBG_DATA_H_8822C \
+ (BIT_MASK_PKTBUF_DBG_DATA_H_8822C << BIT_SHIFT_PKTBUF_DBG_DATA_H_8822C)
+#define BIT_CLEAR_PKTBUF_DBG_DATA_H_8822C(x) \
+ ((x) & (~BITS_PKTBUF_DBG_DATA_H_8822C))
+#define BIT_GET_PKTBUF_DBG_DATA_H_8822C(x) \
+ (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8822C) & \
+ BIT_MASK_PKTBUF_DBG_DATA_H_8822C)
+#define BIT_SET_PKTBUF_DBG_DATA_H_8822C(x, v) \
+ (BIT_CLEAR_PKTBUF_DBG_DATA_H_8822C(x) | BIT_PKTBUF_DBG_DATA_H_8822C(v))
+
+/* 2 REG_CPWM2_8822C */
+
+#define BIT_SHIFT_L0S_TO_RCVY_NUM_8822C 16
+#define BIT_MASK_L0S_TO_RCVY_NUM_8822C 0xff
+#define BIT_L0S_TO_RCVY_NUM_8822C(x) \
+ (((x) & BIT_MASK_L0S_TO_RCVY_NUM_8822C) \
+ << BIT_SHIFT_L0S_TO_RCVY_NUM_8822C)
+#define BITS_L0S_TO_RCVY_NUM_8822C \
+ (BIT_MASK_L0S_TO_RCVY_NUM_8822C << BIT_SHIFT_L0S_TO_RCVY_NUM_8822C)
+#define BIT_CLEAR_L0S_TO_RCVY_NUM_8822C(x) ((x) & (~BITS_L0S_TO_RCVY_NUM_8822C))
+#define BIT_GET_L0S_TO_RCVY_NUM_8822C(x) \
+ (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8822C) & \
+ BIT_MASK_L0S_TO_RCVY_NUM_8822C)
+#define BIT_SET_L0S_TO_RCVY_NUM_8822C(x, v) \
+ (BIT_CLEAR_L0S_TO_RCVY_NUM_8822C(x) | BIT_L0S_TO_RCVY_NUM_8822C(v))
+
+#define BIT_CPWM2_TOGGLING_8822C BIT(15)
+
+#define BIT_SHIFT_CPWM2_MOD_8822C 0
+#define BIT_MASK_CPWM2_MOD_8822C 0x7fff
+#define BIT_CPWM2_MOD_8822C(x) \
+ (((x) & BIT_MASK_CPWM2_MOD_8822C) << BIT_SHIFT_CPWM2_MOD_8822C)
+#define BITS_CPWM2_MOD_8822C \
+ (BIT_MASK_CPWM2_MOD_8822C << BIT_SHIFT_CPWM2_MOD_8822C)
+#define BIT_CLEAR_CPWM2_MOD_8822C(x) ((x) & (~BITS_CPWM2_MOD_8822C))
+#define BIT_GET_CPWM2_MOD_8822C(x) \
+ (((x) >> BIT_SHIFT_CPWM2_MOD_8822C) & BIT_MASK_CPWM2_MOD_8822C)
+#define BIT_SET_CPWM2_MOD_8822C(x, v) \
+ (BIT_CLEAR_CPWM2_MOD_8822C(x) | BIT_CPWM2_MOD_8822C(v))
+
+/* 2 REG_TC0_CTRL_8822C */
+#define BIT_TC0INT_EN_8822C BIT(26)
+#define BIT_TC0MODE_8822C BIT(25)
+#define BIT_TC0EN_8822C BIT(24)
+
+#define BIT_SHIFT_TC0DATA_8822C 0
+#define BIT_MASK_TC0DATA_8822C 0xffffff
+#define BIT_TC0DATA_8822C(x) \
+ (((x) & BIT_MASK_TC0DATA_8822C) << BIT_SHIFT_TC0DATA_8822C)
+#define BITS_TC0DATA_8822C (BIT_MASK_TC0DATA_8822C << BIT_SHIFT_TC0DATA_8822C)
+#define BIT_CLEAR_TC0DATA_8822C(x) ((x) & (~BITS_TC0DATA_8822C))
+#define BIT_GET_TC0DATA_8822C(x) \
+ (((x) >> BIT_SHIFT_TC0DATA_8822C) & BIT_MASK_TC0DATA_8822C)
+#define BIT_SET_TC0DATA_8822C(x, v) \
+ (BIT_CLEAR_TC0DATA_8822C(x) | BIT_TC0DATA_8822C(v))
+
+/* 2 REG_TC1_CTRL_8822C */
+#define BIT_TC1INT_EN_8822C BIT(26)
+#define BIT_TC1MODE_8822C BIT(25)
+#define BIT_TC1EN_8822C BIT(24)
+
+#define BIT_SHIFT_TC1DATA_8822C 0
+#define BIT_MASK_TC1DATA_8822C 0xffffff
+#define BIT_TC1DATA_8822C(x) \
+ (((x) & BIT_MASK_TC1DATA_8822C) << BIT_SHIFT_TC1DATA_8822C)
+#define BITS_TC1DATA_8822C (BIT_MASK_TC1DATA_8822C << BIT_SHIFT_TC1DATA_8822C)
+#define BIT_CLEAR_TC1DATA_8822C(x) ((x) & (~BITS_TC1DATA_8822C))
+#define BIT_GET_TC1DATA_8822C(x) \
+ (((x) >> BIT_SHIFT_TC1DATA_8822C) & BIT_MASK_TC1DATA_8822C)
+#define BIT_SET_TC1DATA_8822C(x, v) \
+ (BIT_CLEAR_TC1DATA_8822C(x) | BIT_TC1DATA_8822C(v))
+
+/* 2 REG_TC2_CTRL_8822C */
+#define BIT_TC2INT_EN_8822C BIT(26)
+#define BIT_TC2MODE_8822C BIT(25)
+#define BIT_TC2EN_8822C BIT(24)
+
+#define BIT_SHIFT_TC2DATA_8822C 0
+#define BIT_MASK_TC2DATA_8822C 0xffffff
+#define BIT_TC2DATA_8822C(x) \
+ (((x) & BIT_MASK_TC2DATA_8822C) << BIT_SHIFT_TC2DATA_8822C)
+#define BITS_TC2DATA_8822C (BIT_MASK_TC2DATA_8822C << BIT_SHIFT_TC2DATA_8822C)
+#define BIT_CLEAR_TC2DATA_8822C(x) ((x) & (~BITS_TC2DATA_8822C))
+#define BIT_GET_TC2DATA_8822C(x) \
+ (((x) >> BIT_SHIFT_TC2DATA_8822C) & BIT_MASK_TC2DATA_8822C)
+#define BIT_SET_TC2DATA_8822C(x, v) \
+ (BIT_CLEAR_TC2DATA_8822C(x) | BIT_TC2DATA_8822C(v))
+
+/* 2 REG_TC3_CTRL_8822C */
+#define BIT_TC3INT_EN_8822C BIT(26)
+#define BIT_TC3MODE_8822C BIT(25)
+#define BIT_TC3EN_8822C BIT(24)
+
+#define BIT_SHIFT_TC3DATA_8822C 0
+#define BIT_MASK_TC3DATA_8822C 0xffffff
+#define BIT_TC3DATA_8822C(x) \
+ (((x) & BIT_MASK_TC3DATA_8822C) << BIT_SHIFT_TC3DATA_8822C)
+#define BITS_TC3DATA_8822C (BIT_MASK_TC3DATA_8822C << BIT_SHIFT_TC3DATA_8822C)
+#define BIT_CLEAR_TC3DATA_8822C(x) ((x) & (~BITS_TC3DATA_8822C))
+#define BIT_GET_TC3DATA_8822C(x) \
+ (((x) >> BIT_SHIFT_TC3DATA_8822C) & BIT_MASK_TC3DATA_8822C)
+#define BIT_SET_TC3DATA_8822C(x, v) \
+ (BIT_CLEAR_TC3DATA_8822C(x) | BIT_TC3DATA_8822C(v))
+
+/* 2 REG_TC4_CTRL_8822C */
+#define BIT_TC4INT_EN_8822C BIT(26)
+#define BIT_TC4MODE_8822C BIT(25)
+#define BIT_TC4EN_8822C BIT(24)
+
+#define BIT_SHIFT_TC4DATA_8822C 0
+#define BIT_MASK_TC4DATA_8822C 0xffffff
+#define BIT_TC4DATA_8822C(x) \
+ (((x) & BIT_MASK_TC4DATA_8822C) << BIT_SHIFT_TC4DATA_8822C)
+#define BITS_TC4DATA_8822C (BIT_MASK_TC4DATA_8822C << BIT_SHIFT_TC4DATA_8822C)
+#define BIT_CLEAR_TC4DATA_8822C(x) ((x) & (~BITS_TC4DATA_8822C))
+#define BIT_GET_TC4DATA_8822C(x) \
+ (((x) >> BIT_SHIFT_TC4DATA_8822C) & BIT_MASK_TC4DATA_8822C)
+#define BIT_SET_TC4DATA_8822C(x, v) \
+ (BIT_CLEAR_TC4DATA_8822C(x) | BIT_TC4DATA_8822C(v))
+
+/* 2 REG_TCUNIT_BASE_8822C */
+
+#define BIT_SHIFT_TCUNIT_BASE_8822C 0
+#define BIT_MASK_TCUNIT_BASE_8822C 0x3fff
+#define BIT_TCUNIT_BASE_8822C(x) \
+ (((x) & BIT_MASK_TCUNIT_BASE_8822C) << BIT_SHIFT_TCUNIT_BASE_8822C)
+#define BITS_TCUNIT_BASE_8822C \
+ (BIT_MASK_TCUNIT_BASE_8822C << BIT_SHIFT_TCUNIT_BASE_8822C)
+#define BIT_CLEAR_TCUNIT_BASE_8822C(x) ((x) & (~BITS_TCUNIT_BASE_8822C))
+#define BIT_GET_TCUNIT_BASE_8822C(x) \
+ (((x) >> BIT_SHIFT_TCUNIT_BASE_8822C) & BIT_MASK_TCUNIT_BASE_8822C)
+#define BIT_SET_TCUNIT_BASE_8822C(x, v) \
+ (BIT_CLEAR_TCUNIT_BASE_8822C(x) | BIT_TCUNIT_BASE_8822C(v))
+
+/* 2 REG_TC5_CTRL_8822C */
+#define BIT_TC5INT_EN_8822C BIT(26)
+#define BIT_TC5MODE_8822C BIT(25)
+#define BIT_TC5EN_8822C BIT(24)
+
+#define BIT_SHIFT_TC5DATA_8822C 0
+#define BIT_MASK_TC5DATA_8822C 0xffffff
+#define BIT_TC5DATA_8822C(x) \
+ (((x) & BIT_MASK_TC5DATA_8822C) << BIT_SHIFT_TC5DATA_8822C)
+#define BITS_TC5DATA_8822C (BIT_MASK_TC5DATA_8822C << BIT_SHIFT_TC5DATA_8822C)
+#define BIT_CLEAR_TC5DATA_8822C(x) ((x) & (~BITS_TC5DATA_8822C))
+#define BIT_GET_TC5DATA_8822C(x) \
+ (((x) >> BIT_SHIFT_TC5DATA_8822C) & BIT_MASK_TC5DATA_8822C)
+#define BIT_SET_TC5DATA_8822C(x, v) \
+ (BIT_CLEAR_TC5DATA_8822C(x) | BIT_TC5DATA_8822C(v))
+
+/* 2 REG_TC6_CTRL_8822C */
+#define BIT_TC6INT_EN_8822C BIT(26)
+#define BIT_TC6MODE_8822C BIT(25)
+#define BIT_TC6EN_8822C BIT(24)
+
+#define BIT_SHIFT_TC6DATA_8822C 0
+#define BIT_MASK_TC6DATA_8822C 0xffffff
+#define BIT_TC6DATA_8822C(x) \
+ (((x) & BIT_MASK_TC6DATA_8822C) << BIT_SHIFT_TC6DATA_8822C)
+#define BITS_TC6DATA_8822C (BIT_MASK_TC6DATA_8822C << BIT_SHIFT_TC6DATA_8822C)
+#define BIT_CLEAR_TC6DATA_8822C(x) ((x) & (~BITS_TC6DATA_8822C))
+#define BIT_GET_TC6DATA_8822C(x) \
+ (((x) >> BIT_SHIFT_TC6DATA_8822C) & BIT_MASK_TC6DATA_8822C)
+#define BIT_SET_TC6DATA_8822C(x, v) \
+ (BIT_CLEAR_TC6DATA_8822C(x) | BIT_TC6DATA_8822C(v))
+
+/* 2 REG_MBIST_DRF_FAIL_8822C */
+
+#define BIT_SHIFT_8051_MBIST_DRF_FAIL_8822C 26
+#define BIT_MASK_8051_MBIST_DRF_FAIL_8822C 0x3f
+#define BIT_8051_MBIST_DRF_FAIL_8822C(x) \
+ (((x) & BIT_MASK_8051_MBIST_DRF_FAIL_8822C) \
+ << BIT_SHIFT_8051_MBIST_DRF_FAIL_8822C)
+#define BITS_8051_MBIST_DRF_FAIL_8822C \
+ (BIT_MASK_8051_MBIST_DRF_FAIL_8822C \
+ << BIT_SHIFT_8051_MBIST_DRF_FAIL_8822C)
+#define BIT_CLEAR_8051_MBIST_DRF_FAIL_8822C(x) \
+ ((x) & (~BITS_8051_MBIST_DRF_FAIL_8822C))
+#define BIT_GET_8051_MBIST_DRF_FAIL_8822C(x) \
+ (((x) >> BIT_SHIFT_8051_MBIST_DRF_FAIL_8822C) & \
+ BIT_MASK_8051_MBIST_DRF_FAIL_8822C)
+#define BIT_SET_8051_MBIST_DRF_FAIL_8822C(x, v) \
+ (BIT_CLEAR_8051_MBIST_DRF_FAIL_8822C(x) | \
+ BIT_8051_MBIST_DRF_FAIL_8822C(v))
+
+#define BIT_SHIFT_USB_MBIST_DRF_FAIL_8822C 24
+#define BIT_MASK_USB_MBIST_DRF_FAIL_8822C 0x3
+#define BIT_USB_MBIST_DRF_FAIL_8822C(x) \
+ (((x) & BIT_MASK_USB_MBIST_DRF_FAIL_8822C) \
+ << BIT_SHIFT_USB_MBIST_DRF_FAIL_8822C)
+#define BITS_USB_MBIST_DRF_FAIL_8822C \
+ (BIT_MASK_USB_MBIST_DRF_FAIL_8822C \
+ << BIT_SHIFT_USB_MBIST_DRF_FAIL_8822C)
+#define BIT_CLEAR_USB_MBIST_DRF_FAIL_8822C(x) \
+ ((x) & (~BITS_USB_MBIST_DRF_FAIL_8822C))
+#define BIT_GET_USB_MBIST_DRF_FAIL_8822C(x) \
+ (((x) >> BIT_SHIFT_USB_MBIST_DRF_FAIL_8822C) & \
+ BIT_MASK_USB_MBIST_DRF_FAIL_8822C)
+#define BIT_SET_USB_MBIST_DRF_FAIL_8822C(x, v) \
+ (BIT_CLEAR_USB_MBIST_DRF_FAIL_8822C(x) | \
+ BIT_USB_MBIST_DRF_FAIL_8822C(v))
+
+#define BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8822C 18
+#define BIT_MASK_PCIE_MBIST_DRF_FAIL_8822C 0x3f
+#define BIT_PCIE_MBIST_DRF_FAIL_8822C(x) \
+ (((x) & BIT_MASK_PCIE_MBIST_DRF_FAIL_8822C) \
+ << BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8822C)
+#define BITS_PCIE_MBIST_DRF_FAIL_8822C \
+ (BIT_MASK_PCIE_MBIST_DRF_FAIL_8822C \
+ << BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8822C)
+#define BIT_CLEAR_PCIE_MBIST_DRF_FAIL_8822C(x) \
+ ((x) & (~BITS_PCIE_MBIST_DRF_FAIL_8822C))
+#define BIT_GET_PCIE_MBIST_DRF_FAIL_8822C(x) \
+ (((x) >> BIT_SHIFT_PCIE_MBIST_DRF_FAIL_8822C) & \
+ BIT_MASK_PCIE_MBIST_DRF_FAIL_8822C)
+#define BIT_SET_PCIE_MBIST_DRF_FAIL_8822C(x, v) \
+ (BIT_CLEAR_PCIE_MBIST_DRF_FAIL_8822C(x) | \
+ BIT_PCIE_MBIST_DRF_FAIL_8822C(v))
+
+#define BIT_SHIFT_MAC_MBIST_DRF_FAIL_8822C 0
+#define BIT_MASK_MAC_MBIST_DRF_FAIL_8822C 0x3ffff
+#define BIT_MAC_MBIST_DRF_FAIL_8822C(x) \
+ (((x) & BIT_MASK_MAC_MBIST_DRF_FAIL_8822C) \
+ << BIT_SHIFT_MAC_MBIST_DRF_FAIL_8822C)
+#define BITS_MAC_MBIST_DRF_FAIL_8822C \
+ (BIT_MASK_MAC_MBIST_DRF_FAIL_8822C \
+ << BIT_SHIFT_MAC_MBIST_DRF_FAIL_8822C)
+#define BIT_CLEAR_MAC_MBIST_DRF_FAIL_8822C(x) \
+ ((x) & (~BITS_MAC_MBIST_DRF_FAIL_8822C))
+#define BIT_GET_MAC_MBIST_DRF_FAIL_8822C(x) \
+ (((x) >> BIT_SHIFT_MAC_MBIST_DRF_FAIL_8822C) & \
+ BIT_MASK_MAC_MBIST_DRF_FAIL_8822C)
+#define BIT_SET_MAC_MBIST_DRF_FAIL_8822C(x, v) \
+ (BIT_CLEAR_MAC_MBIST_DRF_FAIL_8822C(x) | \
+ BIT_MAC_MBIST_DRF_FAIL_8822C(v))
+
+/* 2 REG_MBIST_START_PAUSE_8822C */
+
+#define BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8822C 26
+#define BIT_MASK_8051_MBIST_START_PAUSE_V1_8822C 0x3f
+#define BIT_8051_MBIST_START_PAUSE_V1_8822C(x) \
+ (((x) & BIT_MASK_8051_MBIST_START_PAUSE_V1_8822C) \
+ << BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8822C)
+#define BITS_8051_MBIST_START_PAUSE_V1_8822C \
+ (BIT_MASK_8051_MBIST_START_PAUSE_V1_8822C \
+ << BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8822C)
+#define BIT_CLEAR_8051_MBIST_START_PAUSE_V1_8822C(x) \
+ ((x) & (~BITS_8051_MBIST_START_PAUSE_V1_8822C))
+#define BIT_GET_8051_MBIST_START_PAUSE_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_V1_8822C) & \
+ BIT_MASK_8051_MBIST_START_PAUSE_V1_8822C)
+#define BIT_SET_8051_MBIST_START_PAUSE_V1_8822C(x, v) \
+ (BIT_CLEAR_8051_MBIST_START_PAUSE_V1_8822C(x) | \
+ BIT_8051_MBIST_START_PAUSE_V1_8822C(v))
+
+#define BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8822C 24
+#define BIT_MASK_USB_MBIST_START_PAUSE_V1_8822C 0x3
+#define BIT_USB_MBIST_START_PAUSE_V1_8822C(x) \
+ (((x) & BIT_MASK_USB_MBIST_START_PAUSE_V1_8822C) \
+ << BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8822C)
+#define BITS_USB_MBIST_START_PAUSE_V1_8822C \
+ (BIT_MASK_USB_MBIST_START_PAUSE_V1_8822C \
+ << BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8822C)
+#define BIT_CLEAR_USB_MBIST_START_PAUSE_V1_8822C(x) \
+ ((x) & (~BITS_USB_MBIST_START_PAUSE_V1_8822C))
+#define BIT_GET_USB_MBIST_START_PAUSE_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_V1_8822C) & \
+ BIT_MASK_USB_MBIST_START_PAUSE_V1_8822C)
+#define BIT_SET_USB_MBIST_START_PAUSE_V1_8822C(x, v) \
+ (BIT_CLEAR_USB_MBIST_START_PAUSE_V1_8822C(x) | \
+ BIT_USB_MBIST_START_PAUSE_V1_8822C(v))
+
+#define BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8822C 18
+#define BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8822C 0x3f
+#define BIT_PCIE_MBIST_START_PAUSE_V1_8822C(x) \
+ (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8822C) \
+ << BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8822C)
+#define BITS_PCIE_MBIST_START_PAUSE_V1_8822C \
+ (BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8822C \
+ << BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8822C)
+#define BIT_CLEAR_PCIE_MBIST_START_PAUSE_V1_8822C(x) \
+ ((x) & (~BITS_PCIE_MBIST_START_PAUSE_V1_8822C))
+#define BIT_GET_PCIE_MBIST_START_PAUSE_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_V1_8822C) & \
+ BIT_MASK_PCIE_MBIST_START_PAUSE_V1_8822C)
+#define BIT_SET_PCIE_MBIST_START_PAUSE_V1_8822C(x, v) \
+ (BIT_CLEAR_PCIE_MBIST_START_PAUSE_V1_8822C(x) | \
+ BIT_PCIE_MBIST_START_PAUSE_V1_8822C(v))
+
+#define BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8822C 0
+#define BIT_MASK_MAC_MBIST_START_PAUSE_V1_8822C 0x3ffff
+#define BIT_MAC_MBIST_START_PAUSE_V1_8822C(x) \
+ (((x) & BIT_MASK_MAC_MBIST_START_PAUSE_V1_8822C) \
+ << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8822C)
+#define BITS_MAC_MBIST_START_PAUSE_V1_8822C \
+ (BIT_MASK_MAC_MBIST_START_PAUSE_V1_8822C \
+ << BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8822C)
+#define BIT_CLEAR_MAC_MBIST_START_PAUSE_V1_8822C(x) \
+ ((x) & (~BITS_MAC_MBIST_START_PAUSE_V1_8822C))
+#define BIT_GET_MAC_MBIST_START_PAUSE_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_V1_8822C) & \
+ BIT_MASK_MAC_MBIST_START_PAUSE_V1_8822C)
+#define BIT_SET_MAC_MBIST_START_PAUSE_V1_8822C(x, v) \
+ (BIT_CLEAR_MAC_MBIST_START_PAUSE_V1_8822C(x) | \
+ BIT_MAC_MBIST_START_PAUSE_V1_8822C(v))
+
+/* 2 REG_MBIST_DONE_8822C */
+
+#define BIT_SHIFT_8051_MBIST_DONE_V1_8822C 26
+#define BIT_MASK_8051_MBIST_DONE_V1_8822C 0x3f
+#define BIT_8051_MBIST_DONE_V1_8822C(x) \
+ (((x) & BIT_MASK_8051_MBIST_DONE_V1_8822C) \
+ << BIT_SHIFT_8051_MBIST_DONE_V1_8822C)
+#define BITS_8051_MBIST_DONE_V1_8822C \
+ (BIT_MASK_8051_MBIST_DONE_V1_8822C \
+ << BIT_SHIFT_8051_MBIST_DONE_V1_8822C)
+#define BIT_CLEAR_8051_MBIST_DONE_V1_8822C(x) \
+ ((x) & (~BITS_8051_MBIST_DONE_V1_8822C))
+#define BIT_GET_8051_MBIST_DONE_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_8051_MBIST_DONE_V1_8822C) & \
+ BIT_MASK_8051_MBIST_DONE_V1_8822C)
+#define BIT_SET_8051_MBIST_DONE_V1_8822C(x, v) \
+ (BIT_CLEAR_8051_MBIST_DONE_V1_8822C(x) | \
+ BIT_8051_MBIST_DONE_V1_8822C(v))
+
+#define BIT_SHIFT_USB_MBIST_DONE_V1_8822C 24
+#define BIT_MASK_USB_MBIST_DONE_V1_8822C 0x3
+#define BIT_USB_MBIST_DONE_V1_8822C(x) \
+ (((x) & BIT_MASK_USB_MBIST_DONE_V1_8822C) \
+ << BIT_SHIFT_USB_MBIST_DONE_V1_8822C)
+#define BITS_USB_MBIST_DONE_V1_8822C \
+ (BIT_MASK_USB_MBIST_DONE_V1_8822C << BIT_SHIFT_USB_MBIST_DONE_V1_8822C)
+#define BIT_CLEAR_USB_MBIST_DONE_V1_8822C(x) \
+ ((x) & (~BITS_USB_MBIST_DONE_V1_8822C))
+#define BIT_GET_USB_MBIST_DONE_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_USB_MBIST_DONE_V1_8822C) & \
+ BIT_MASK_USB_MBIST_DONE_V1_8822C)
+#define BIT_SET_USB_MBIST_DONE_V1_8822C(x, v) \
+ (BIT_CLEAR_USB_MBIST_DONE_V1_8822C(x) | BIT_USB_MBIST_DONE_V1_8822C(v))
+
+#define BIT_SHIFT_PCIE_MBIST_DONE_V1_8822C 18
+#define BIT_MASK_PCIE_MBIST_DONE_V1_8822C 0x3f
+#define BIT_PCIE_MBIST_DONE_V1_8822C(x) \
+ (((x) & BIT_MASK_PCIE_MBIST_DONE_V1_8822C) \
+ << BIT_SHIFT_PCIE_MBIST_DONE_V1_8822C)
+#define BITS_PCIE_MBIST_DONE_V1_8822C \
+ (BIT_MASK_PCIE_MBIST_DONE_V1_8822C \
+ << BIT_SHIFT_PCIE_MBIST_DONE_V1_8822C)
+#define BIT_CLEAR_PCIE_MBIST_DONE_V1_8822C(x) \
+ ((x) & (~BITS_PCIE_MBIST_DONE_V1_8822C))
+#define BIT_GET_PCIE_MBIST_DONE_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_PCIE_MBIST_DONE_V1_8822C) & \
+ BIT_MASK_PCIE_MBIST_DONE_V1_8822C)
+#define BIT_SET_PCIE_MBIST_DONE_V1_8822C(x, v) \
+ (BIT_CLEAR_PCIE_MBIST_DONE_V1_8822C(x) | \
+ BIT_PCIE_MBIST_DONE_V1_8822C(v))
+
+#define BIT_SHIFT_MAC_MBIST_DONE_V1_8822C 0
+#define BIT_MASK_MAC_MBIST_DONE_V1_8822C 0x3ffff
+#define BIT_MAC_MBIST_DONE_V1_8822C(x) \
+ (((x) & BIT_MASK_MAC_MBIST_DONE_V1_8822C) \
+ << BIT_SHIFT_MAC_MBIST_DONE_V1_8822C)
+#define BITS_MAC_MBIST_DONE_V1_8822C \
+ (BIT_MASK_MAC_MBIST_DONE_V1_8822C << BIT_SHIFT_MAC_MBIST_DONE_V1_8822C)
+#define BIT_CLEAR_MAC_MBIST_DONE_V1_8822C(x) \
+ ((x) & (~BITS_MAC_MBIST_DONE_V1_8822C))
+#define BIT_GET_MAC_MBIST_DONE_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_MAC_MBIST_DONE_V1_8822C) & \
+ BIT_MASK_MAC_MBIST_DONE_V1_8822C)
+#define BIT_SET_MAC_MBIST_DONE_V1_8822C(x, v) \
+ (BIT_CLEAR_MAC_MBIST_DONE_V1_8822C(x) | BIT_MAC_MBIST_DONE_V1_8822C(v))
+
+/* 2 REG_MBIST_READ_BIST_RPT_8822C */
+
+#define BIT_SHIFT_MBIST_READ_BIST_RPT_8822C 0
+#define BIT_MASK_MBIST_READ_BIST_RPT_8822C 0xffffffffL
+#define BIT_MBIST_READ_BIST_RPT_8822C(x) \
+ (((x) & BIT_MASK_MBIST_READ_BIST_RPT_8822C) \
+ << BIT_SHIFT_MBIST_READ_BIST_RPT_8822C)
+#define BITS_MBIST_READ_BIST_RPT_8822C \
+ (BIT_MASK_MBIST_READ_BIST_RPT_8822C \
+ << BIT_SHIFT_MBIST_READ_BIST_RPT_8822C)
+#define BIT_CLEAR_MBIST_READ_BIST_RPT_8822C(x) \
+ ((x) & (~BITS_MBIST_READ_BIST_RPT_8822C))
+#define BIT_GET_MBIST_READ_BIST_RPT_8822C(x) \
+ (((x) >> BIT_SHIFT_MBIST_READ_BIST_RPT_8822C) & \
+ BIT_MASK_MBIST_READ_BIST_RPT_8822C)
+#define BIT_SET_MBIST_READ_BIST_RPT_8822C(x, v) \
+ (BIT_CLEAR_MBIST_READ_BIST_RPT_8822C(x) | \
+ BIT_MBIST_READ_BIST_RPT_8822C(v))
+
+/* 2 REG_AES_DECRPT_DATA_8822C */
+
+#define BIT_SHIFT_IPS_CFG_ADDR_8822C 0
+#define BIT_MASK_IPS_CFG_ADDR_8822C 0xff
+#define BIT_IPS_CFG_ADDR_8822C(x) \
+ (((x) & BIT_MASK_IPS_CFG_ADDR_8822C) << BIT_SHIFT_IPS_CFG_ADDR_8822C)
+#define BITS_IPS_CFG_ADDR_8822C \
+ (BIT_MASK_IPS_CFG_ADDR_8822C << BIT_SHIFT_IPS_CFG_ADDR_8822C)
+#define BIT_CLEAR_IPS_CFG_ADDR_8822C(x) ((x) & (~BITS_IPS_CFG_ADDR_8822C))
+#define BIT_GET_IPS_CFG_ADDR_8822C(x) \
+ (((x) >> BIT_SHIFT_IPS_CFG_ADDR_8822C) & BIT_MASK_IPS_CFG_ADDR_8822C)
+#define BIT_SET_IPS_CFG_ADDR_8822C(x, v) \
+ (BIT_CLEAR_IPS_CFG_ADDR_8822C(x) | BIT_IPS_CFG_ADDR_8822C(v))
+
+/* 2 REG_AES_DECRPT_CFG_8822C */
+
+#define BIT_SHIFT_IPS_CFG_DATA_8822C 0
+#define BIT_MASK_IPS_CFG_DATA_8822C 0xffffffffL
+#define BIT_IPS_CFG_DATA_8822C(x) \
+ (((x) & BIT_MASK_IPS_CFG_DATA_8822C) << BIT_SHIFT_IPS_CFG_DATA_8822C)
+#define BITS_IPS_CFG_DATA_8822C \
+ (BIT_MASK_IPS_CFG_DATA_8822C << BIT_SHIFT_IPS_CFG_DATA_8822C)
+#define BIT_CLEAR_IPS_CFG_DATA_8822C(x) ((x) & (~BITS_IPS_CFG_DATA_8822C))
+#define BIT_GET_IPS_CFG_DATA_8822C(x) \
+ (((x) >> BIT_SHIFT_IPS_CFG_DATA_8822C) & BIT_MASK_IPS_CFG_DATA_8822C)
+#define BIT_SET_IPS_CFG_DATA_8822C(x, v) \
+ (BIT_CLEAR_IPS_CFG_DATA_8822C(x) | BIT_IPS_CFG_DATA_8822C(v))
+
+/* 2 REG_HIOE_CTRL_8822C */
+#define BIT_HIOE_CFG_FILE_LOC_SEL_8822C BIT(31)
+#define BIT_HIOE_WRITE_REQ_8822C BIT(30)
+#define BIT_HIOE_READ_REQ_8822C BIT(29)
+#define BIT_INST_FORMAT_ERR_8822C BIT(25)
+#define BIT_OP_TIMEOUT_ERR_8822C BIT(24)
+
+#define BIT_SHIFT_HIOE_OP_TIMEOUT_8822C 16
+#define BIT_MASK_HIOE_OP_TIMEOUT_8822C 0xff
+#define BIT_HIOE_OP_TIMEOUT_8822C(x) \
+ (((x) & BIT_MASK_HIOE_OP_TIMEOUT_8822C) \
+ << BIT_SHIFT_HIOE_OP_TIMEOUT_8822C)
+#define BITS_HIOE_OP_TIMEOUT_8822C \
+ (BIT_MASK_HIOE_OP_TIMEOUT_8822C << BIT_SHIFT_HIOE_OP_TIMEOUT_8822C)
+#define BIT_CLEAR_HIOE_OP_TIMEOUT_8822C(x) ((x) & (~BITS_HIOE_OP_TIMEOUT_8822C))
+#define BIT_GET_HIOE_OP_TIMEOUT_8822C(x) \
+ (((x) >> BIT_SHIFT_HIOE_OP_TIMEOUT_8822C) & \
+ BIT_MASK_HIOE_OP_TIMEOUT_8822C)
+#define BIT_SET_HIOE_OP_TIMEOUT_8822C(x, v) \
+ (BIT_CLEAR_HIOE_OP_TIMEOUT_8822C(x) | BIT_HIOE_OP_TIMEOUT_8822C(v))
+
+#define BIT_SHIFT_BITDATA_CHECKSUM_8822C 0
+#define BIT_MASK_BITDATA_CHECKSUM_8822C 0xffff
+#define BIT_BITDATA_CHECKSUM_8822C(x) \
+ (((x) & BIT_MASK_BITDATA_CHECKSUM_8822C) \
+ << BIT_SHIFT_BITDATA_CHECKSUM_8822C)
+#define BITS_BITDATA_CHECKSUM_8822C \
+ (BIT_MASK_BITDATA_CHECKSUM_8822C << BIT_SHIFT_BITDATA_CHECKSUM_8822C)
+#define BIT_CLEAR_BITDATA_CHECKSUM_8822C(x) \
+ ((x) & (~BITS_BITDATA_CHECKSUM_8822C))
+#define BIT_GET_BITDATA_CHECKSUM_8822C(x) \
+ (((x) >> BIT_SHIFT_BITDATA_CHECKSUM_8822C) & \
+ BIT_MASK_BITDATA_CHECKSUM_8822C)
+#define BIT_SET_BITDATA_CHECKSUM_8822C(x, v) \
+ (BIT_CLEAR_BITDATA_CHECKSUM_8822C(x) | BIT_BITDATA_CHECKSUM_8822C(v))
+
+/* 2 REG_HIOE_CFG_FILE_8822C */
+
+#define BIT_SHIFT_TXBF_END_ADDR_8822C 16
+#define BIT_MASK_TXBF_END_ADDR_8822C 0xffff
+#define BIT_TXBF_END_ADDR_8822C(x) \
+ (((x) & BIT_MASK_TXBF_END_ADDR_8822C) << BIT_SHIFT_TXBF_END_ADDR_8822C)
+#define BITS_TXBF_END_ADDR_8822C \
+ (BIT_MASK_TXBF_END_ADDR_8822C << BIT_SHIFT_TXBF_END_ADDR_8822C)
+#define BIT_CLEAR_TXBF_END_ADDR_8822C(x) ((x) & (~BITS_TXBF_END_ADDR_8822C))
+#define BIT_GET_TXBF_END_ADDR_8822C(x) \
+ (((x) >> BIT_SHIFT_TXBF_END_ADDR_8822C) & BIT_MASK_TXBF_END_ADDR_8822C)
+#define BIT_SET_TXBF_END_ADDR_8822C(x, v) \
+ (BIT_CLEAR_TXBF_END_ADDR_8822C(x) | BIT_TXBF_END_ADDR_8822C(v))
+
+#define BIT_SHIFT_TXBF_STR_ADDR_8822C 0
+#define BIT_MASK_TXBF_STR_ADDR_8822C 0xffff
+#define BIT_TXBF_STR_ADDR_8822C(x) \
+ (((x) & BIT_MASK_TXBF_STR_ADDR_8822C) << BIT_SHIFT_TXBF_STR_ADDR_8822C)
+#define BITS_TXBF_STR_ADDR_8822C \
+ (BIT_MASK_TXBF_STR_ADDR_8822C << BIT_SHIFT_TXBF_STR_ADDR_8822C)
+#define BIT_CLEAR_TXBF_STR_ADDR_8822C(x) ((x) & (~BITS_TXBF_STR_ADDR_8822C))
+#define BIT_GET_TXBF_STR_ADDR_8822C(x) \
+ (((x) >> BIT_SHIFT_TXBF_STR_ADDR_8822C) & BIT_MASK_TXBF_STR_ADDR_8822C)
+#define BIT_SET_TXBF_STR_ADDR_8822C(x, v) \
+ (BIT_CLEAR_TXBF_STR_ADDR_8822C(x) | BIT_TXBF_STR_ADDR_8822C(v))
+
+/* 2 REG_TMETER_8822C */
+#define BIT_TEMP_VALID_8822C BIT(31)
+
+#define BIT_SHIFT_TEMP_VALUE_8822C 24
+#define BIT_MASK_TEMP_VALUE_8822C 0x3f
+#define BIT_TEMP_VALUE_8822C(x) \
+ (((x) & BIT_MASK_TEMP_VALUE_8822C) << BIT_SHIFT_TEMP_VALUE_8822C)
+#define BITS_TEMP_VALUE_8822C \
+ (BIT_MASK_TEMP_VALUE_8822C << BIT_SHIFT_TEMP_VALUE_8822C)
+#define BIT_CLEAR_TEMP_VALUE_8822C(x) ((x) & (~BITS_TEMP_VALUE_8822C))
+#define BIT_GET_TEMP_VALUE_8822C(x) \
+ (((x) >> BIT_SHIFT_TEMP_VALUE_8822C) & BIT_MASK_TEMP_VALUE_8822C)
+#define BIT_SET_TEMP_VALUE_8822C(x, v) \
+ (BIT_CLEAR_TEMP_VALUE_8822C(x) | BIT_TEMP_VALUE_8822C(v))
+
+#define BIT_SHIFT_REG_TMETER_TIMER_8822C 8
+#define BIT_MASK_REG_TMETER_TIMER_8822C 0xfff
+#define BIT_REG_TMETER_TIMER_8822C(x) \
+ (((x) & BIT_MASK_REG_TMETER_TIMER_8822C) \
+ << BIT_SHIFT_REG_TMETER_TIMER_8822C)
+#define BITS_REG_TMETER_TIMER_8822C \
+ (BIT_MASK_REG_TMETER_TIMER_8822C << BIT_SHIFT_REG_TMETER_TIMER_8822C)
+#define BIT_CLEAR_REG_TMETER_TIMER_8822C(x) \
+ ((x) & (~BITS_REG_TMETER_TIMER_8822C))
+#define BIT_GET_REG_TMETER_TIMER_8822C(x) \
+ (((x) >> BIT_SHIFT_REG_TMETER_TIMER_8822C) & \
+ BIT_MASK_REG_TMETER_TIMER_8822C)
+#define BIT_SET_REG_TMETER_TIMER_8822C(x, v) \
+ (BIT_CLEAR_REG_TMETER_TIMER_8822C(x) | BIT_REG_TMETER_TIMER_8822C(v))
+
+#define BIT_SHIFT_REG_TEMP_DELTA_8822C 2
+#define BIT_MASK_REG_TEMP_DELTA_8822C 0x3f
+#define BIT_REG_TEMP_DELTA_8822C(x) \
+ (((x) & BIT_MASK_REG_TEMP_DELTA_8822C) \
+ << BIT_SHIFT_REG_TEMP_DELTA_8822C)
+#define BITS_REG_TEMP_DELTA_8822C \
+ (BIT_MASK_REG_TEMP_DELTA_8822C << BIT_SHIFT_REG_TEMP_DELTA_8822C)
+#define BIT_CLEAR_REG_TEMP_DELTA_8822C(x) ((x) & (~BITS_REG_TEMP_DELTA_8822C))
+#define BIT_GET_REG_TEMP_DELTA_8822C(x) \
+ (((x) >> BIT_SHIFT_REG_TEMP_DELTA_8822C) & \
+ BIT_MASK_REG_TEMP_DELTA_8822C)
+#define BIT_SET_REG_TEMP_DELTA_8822C(x, v) \
+ (BIT_CLEAR_REG_TEMP_DELTA_8822C(x) | BIT_REG_TEMP_DELTA_8822C(v))
+
+#define BIT_REG_TMETER_EN_8822C BIT(0)
+
+/* 2 REG_OSC_32K_CTRL_8822C */
+
+#define BIT_SHIFT_OSC_32K_CLKGEN_0_8822C 16
+#define BIT_MASK_OSC_32K_CLKGEN_0_8822C 0xffff
+#define BIT_OSC_32K_CLKGEN_0_8822C(x) \
+ (((x) & BIT_MASK_OSC_32K_CLKGEN_0_8822C) \
+ << BIT_SHIFT_OSC_32K_CLKGEN_0_8822C)
+#define BITS_OSC_32K_CLKGEN_0_8822C \
+ (BIT_MASK_OSC_32K_CLKGEN_0_8822C << BIT_SHIFT_OSC_32K_CLKGEN_0_8822C)
+#define BIT_CLEAR_OSC_32K_CLKGEN_0_8822C(x) \
+ ((x) & (~BITS_OSC_32K_CLKGEN_0_8822C))
+#define BIT_GET_OSC_32K_CLKGEN_0_8822C(x) \
+ (((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0_8822C) & \
+ BIT_MASK_OSC_32K_CLKGEN_0_8822C)
+#define BIT_SET_OSC_32K_CLKGEN_0_8822C(x, v) \
+ (BIT_CLEAR_OSC_32K_CLKGEN_0_8822C(x) | BIT_OSC_32K_CLKGEN_0_8822C(v))
+
+#define BIT_SHIFT_OSC_32K_RES_COMP_8822C 4
+#define BIT_MASK_OSC_32K_RES_COMP_8822C 0x3
+#define BIT_OSC_32K_RES_COMP_8822C(x) \
+ (((x) & BIT_MASK_OSC_32K_RES_COMP_8822C) \
+ << BIT_SHIFT_OSC_32K_RES_COMP_8822C)
+#define BITS_OSC_32K_RES_COMP_8822C \
+ (BIT_MASK_OSC_32K_RES_COMP_8822C << BIT_SHIFT_OSC_32K_RES_COMP_8822C)
+#define BIT_CLEAR_OSC_32K_RES_COMP_8822C(x) \
+ ((x) & (~BITS_OSC_32K_RES_COMP_8822C))
+#define BIT_GET_OSC_32K_RES_COMP_8822C(x) \
+ (((x) >> BIT_SHIFT_OSC_32K_RES_COMP_8822C) & \
+ BIT_MASK_OSC_32K_RES_COMP_8822C)
+#define BIT_SET_OSC_32K_RES_COMP_8822C(x, v) \
+ (BIT_CLEAR_OSC_32K_RES_COMP_8822C(x) | BIT_OSC_32K_RES_COMP_8822C(v))
+
+#define BIT_OSC_32K_OUT_SEL_8822C BIT(3)
+#define BIT_ISO_WL_2_OSC_32K_8822C BIT(1)
+#define BIT_POW_CKGEN_8822C BIT(0)
+
+/* 2 REG_32K_CAL_REG1_8822C */
+#define BIT_CAL_32K_REG_WR_8822C BIT(31)
+#define BIT_CAL_32K_DBG_SEL_8822C BIT(22)
+
+#define BIT_SHIFT_CAL_32K_REG_ADDR_8822C 16
+#define BIT_MASK_CAL_32K_REG_ADDR_8822C 0x3f
+#define BIT_CAL_32K_REG_ADDR_8822C(x) \
+ (((x) & BIT_MASK_CAL_32K_REG_ADDR_8822C) \
+ << BIT_SHIFT_CAL_32K_REG_ADDR_8822C)
+#define BITS_CAL_32K_REG_ADDR_8822C \
+ (BIT_MASK_CAL_32K_REG_ADDR_8822C << BIT_SHIFT_CAL_32K_REG_ADDR_8822C)
+#define BIT_CLEAR_CAL_32K_REG_ADDR_8822C(x) \
+ ((x) & (~BITS_CAL_32K_REG_ADDR_8822C))
+#define BIT_GET_CAL_32K_REG_ADDR_8822C(x) \
+ (((x) >> BIT_SHIFT_CAL_32K_REG_ADDR_8822C) & \
+ BIT_MASK_CAL_32K_REG_ADDR_8822C)
+#define BIT_SET_CAL_32K_REG_ADDR_8822C(x, v) \
+ (BIT_CLEAR_CAL_32K_REG_ADDR_8822C(x) | BIT_CAL_32K_REG_ADDR_8822C(v))
+
+#define BIT_SHIFT_CAL_32K_REG_DATA_8822C 0
+#define BIT_MASK_CAL_32K_REG_DATA_8822C 0xffff
+#define BIT_CAL_32K_REG_DATA_8822C(x) \
+ (((x) & BIT_MASK_CAL_32K_REG_DATA_8822C) \
+ << BIT_SHIFT_CAL_32K_REG_DATA_8822C)
+#define BITS_CAL_32K_REG_DATA_8822C \
+ (BIT_MASK_CAL_32K_REG_DATA_8822C << BIT_SHIFT_CAL_32K_REG_DATA_8822C)
+#define BIT_CLEAR_CAL_32K_REG_DATA_8822C(x) \
+ ((x) & (~BITS_CAL_32K_REG_DATA_8822C))
+#define BIT_GET_CAL_32K_REG_DATA_8822C(x) \
+ (((x) >> BIT_SHIFT_CAL_32K_REG_DATA_8822C) & \
+ BIT_MASK_CAL_32K_REG_DATA_8822C)
+#define BIT_SET_CAL_32K_REG_DATA_8822C(x, v) \
+ (BIT_CLEAR_CAL_32K_REG_DATA_8822C(x) | BIT_CAL_32K_REG_DATA_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_C2HEVT_8822C */
+
+#define BIT_SHIFT_C2HEVT_MSG_V1_8822C 0
+#define BIT_MASK_C2HEVT_MSG_V1_8822C 0xffffffffL
+#define BIT_C2HEVT_MSG_V1_8822C(x) \
+ (((x) & BIT_MASK_C2HEVT_MSG_V1_8822C) << BIT_SHIFT_C2HEVT_MSG_V1_8822C)
+#define BITS_C2HEVT_MSG_V1_8822C \
+ (BIT_MASK_C2HEVT_MSG_V1_8822C << BIT_SHIFT_C2HEVT_MSG_V1_8822C)
+#define BIT_CLEAR_C2HEVT_MSG_V1_8822C(x) ((x) & (~BITS_C2HEVT_MSG_V1_8822C))
+#define BIT_GET_C2HEVT_MSG_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_C2HEVT_MSG_V1_8822C) & BIT_MASK_C2HEVT_MSG_V1_8822C)
+#define BIT_SET_C2HEVT_MSG_V1_8822C(x, v) \
+ (BIT_CLEAR_C2HEVT_MSG_V1_8822C(x) | BIT_C2HEVT_MSG_V1_8822C(v))
+
+/* 2 REG_C2HEVT_1_8822C */
+
+#define BIT_SHIFT_C2HEVT_MSG_1_8822C 0
+#define BIT_MASK_C2HEVT_MSG_1_8822C 0xffffffffL
+#define BIT_C2HEVT_MSG_1_8822C(x) \
+ (((x) & BIT_MASK_C2HEVT_MSG_1_8822C) << BIT_SHIFT_C2HEVT_MSG_1_8822C)
+#define BITS_C2HEVT_MSG_1_8822C \
+ (BIT_MASK_C2HEVT_MSG_1_8822C << BIT_SHIFT_C2HEVT_MSG_1_8822C)
+#define BIT_CLEAR_C2HEVT_MSG_1_8822C(x) ((x) & (~BITS_C2HEVT_MSG_1_8822C))
+#define BIT_GET_C2HEVT_MSG_1_8822C(x) \
+ (((x) >> BIT_SHIFT_C2HEVT_MSG_1_8822C) & BIT_MASK_C2HEVT_MSG_1_8822C)
+#define BIT_SET_C2HEVT_MSG_1_8822C(x, v) \
+ (BIT_CLEAR_C2HEVT_MSG_1_8822C(x) | BIT_C2HEVT_MSG_1_8822C(v))
+
+/* 2 REG_C2HEVT_2_8822C */
+
+#define BIT_SHIFT_C2HEVT_MSG_2_8822C 0
+#define BIT_MASK_C2HEVT_MSG_2_8822C 0xffffffffL
+#define BIT_C2HEVT_MSG_2_8822C(x) \
+ (((x) & BIT_MASK_C2HEVT_MSG_2_8822C) << BIT_SHIFT_C2HEVT_MSG_2_8822C)
+#define BITS_C2HEVT_MSG_2_8822C \
+ (BIT_MASK_C2HEVT_MSG_2_8822C << BIT_SHIFT_C2HEVT_MSG_2_8822C)
+#define BIT_CLEAR_C2HEVT_MSG_2_8822C(x) ((x) & (~BITS_C2HEVT_MSG_2_8822C))
+#define BIT_GET_C2HEVT_MSG_2_8822C(x) \
+ (((x) >> BIT_SHIFT_C2HEVT_MSG_2_8822C) & BIT_MASK_C2HEVT_MSG_2_8822C)
+#define BIT_SET_C2HEVT_MSG_2_8822C(x, v) \
+ (BIT_CLEAR_C2HEVT_MSG_2_8822C(x) | BIT_C2HEVT_MSG_2_8822C(v))
+
+/* 2 REG_C2HEVT_3_8822C */
+
+#define BIT_SHIFT_C2HEVT_MSG_3_8822C 0
+#define BIT_MASK_C2HEVT_MSG_3_8822C 0xffffffffL
+#define BIT_C2HEVT_MSG_3_8822C(x) \
+ (((x) & BIT_MASK_C2HEVT_MSG_3_8822C) << BIT_SHIFT_C2HEVT_MSG_3_8822C)
+#define BITS_C2HEVT_MSG_3_8822C \
+ (BIT_MASK_C2HEVT_MSG_3_8822C << BIT_SHIFT_C2HEVT_MSG_3_8822C)
+#define BIT_CLEAR_C2HEVT_MSG_3_8822C(x) ((x) & (~BITS_C2HEVT_MSG_3_8822C))
+#define BIT_GET_C2HEVT_MSG_3_8822C(x) \
+ (((x) >> BIT_SHIFT_C2HEVT_MSG_3_8822C) & BIT_MASK_C2HEVT_MSG_3_8822C)
+#define BIT_SET_C2HEVT_MSG_3_8822C(x, v) \
+ (BIT_CLEAR_C2HEVT_MSG_3_8822C(x) | BIT_C2HEVT_MSG_3_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_SW_DEFINED_PAGE1_8822C */
+
+#define BIT_SHIFT_SW_DEFINED_PAGE1_V1_8822C 0
+#define BIT_MASK_SW_DEFINED_PAGE1_V1_8822C 0xffffffffL
+#define BIT_SW_DEFINED_PAGE1_V1_8822C(x) \
+ (((x) & BIT_MASK_SW_DEFINED_PAGE1_V1_8822C) \
+ << BIT_SHIFT_SW_DEFINED_PAGE1_V1_8822C)
+#define BITS_SW_DEFINED_PAGE1_V1_8822C \
+ (BIT_MASK_SW_DEFINED_PAGE1_V1_8822C \
+ << BIT_SHIFT_SW_DEFINED_PAGE1_V1_8822C)
+#define BIT_CLEAR_SW_DEFINED_PAGE1_V1_8822C(x) \
+ ((x) & (~BITS_SW_DEFINED_PAGE1_V1_8822C))
+#define BIT_GET_SW_DEFINED_PAGE1_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_V1_8822C) & \
+ BIT_MASK_SW_DEFINED_PAGE1_V1_8822C)
+#define BIT_SET_SW_DEFINED_PAGE1_V1_8822C(x, v) \
+ (BIT_CLEAR_SW_DEFINED_PAGE1_V1_8822C(x) | \
+ BIT_SW_DEFINED_PAGE1_V1_8822C(v))
+
+/* 2 REG_SW_DEFINED_PAGE2_8822C */
+
+#define BIT_SHIFT_SW_DEFINED_PAGE2_8822C 0
+#define BIT_MASK_SW_DEFINED_PAGE2_8822C 0xffffffffL
+#define BIT_SW_DEFINED_PAGE2_8822C(x) \
+ (((x) & BIT_MASK_SW_DEFINED_PAGE2_8822C) \
+ << BIT_SHIFT_SW_DEFINED_PAGE2_8822C)
+#define BITS_SW_DEFINED_PAGE2_8822C \
+ (BIT_MASK_SW_DEFINED_PAGE2_8822C << BIT_SHIFT_SW_DEFINED_PAGE2_8822C)
+#define BIT_CLEAR_SW_DEFINED_PAGE2_8822C(x) \
+ ((x) & (~BITS_SW_DEFINED_PAGE2_8822C))
+#define BIT_GET_SW_DEFINED_PAGE2_8822C(x) \
+ (((x) >> BIT_SHIFT_SW_DEFINED_PAGE2_8822C) & \
+ BIT_MASK_SW_DEFINED_PAGE2_8822C)
+#define BIT_SET_SW_DEFINED_PAGE2_8822C(x, v) \
+ (BIT_CLEAR_SW_DEFINED_PAGE2_8822C(x) | BIT_SW_DEFINED_PAGE2_8822C(v))
+
+/* 2 REG_MCUTST_I_8822C */
+
+#define BIT_SHIFT_MCUDMSG_I_8822C 0
+#define BIT_MASK_MCUDMSG_I_8822C 0xffffffffL
+#define BIT_MCUDMSG_I_8822C(x) \
+ (((x) & BIT_MASK_MCUDMSG_I_8822C) << BIT_SHIFT_MCUDMSG_I_8822C)
+#define BITS_MCUDMSG_I_8822C \
+ (BIT_MASK_MCUDMSG_I_8822C << BIT_SHIFT_MCUDMSG_I_8822C)
+#define BIT_CLEAR_MCUDMSG_I_8822C(x) ((x) & (~BITS_MCUDMSG_I_8822C))
+#define BIT_GET_MCUDMSG_I_8822C(x) \
+ (((x) >> BIT_SHIFT_MCUDMSG_I_8822C) & BIT_MASK_MCUDMSG_I_8822C)
+#define BIT_SET_MCUDMSG_I_8822C(x, v) \
+ (BIT_CLEAR_MCUDMSG_I_8822C(x) | BIT_MCUDMSG_I_8822C(v))
+
+/* 2 REG_MCUTST_II_8822C */
+
+#define BIT_SHIFT_MCUDMSG_II_8822C 0
+#define BIT_MASK_MCUDMSG_II_8822C 0xffffffffL
+#define BIT_MCUDMSG_II_8822C(x) \
+ (((x) & BIT_MASK_MCUDMSG_II_8822C) << BIT_SHIFT_MCUDMSG_II_8822C)
+#define BITS_MCUDMSG_II_8822C \
+ (BIT_MASK_MCUDMSG_II_8822C << BIT_SHIFT_MCUDMSG_II_8822C)
+#define BIT_CLEAR_MCUDMSG_II_8822C(x) ((x) & (~BITS_MCUDMSG_II_8822C))
+#define BIT_GET_MCUDMSG_II_8822C(x) \
+ (((x) >> BIT_SHIFT_MCUDMSG_II_8822C) & BIT_MASK_MCUDMSG_II_8822C)
+#define BIT_SET_MCUDMSG_II_8822C(x, v) \
+ (BIT_CLEAR_MCUDMSG_II_8822C(x) | BIT_MCUDMSG_II_8822C(v))
+
+/* 2 REG_FMETHR_8822C */
+#define BIT_FMSG_INT_8822C BIT(31)
+
+#define BIT_SHIFT_FW_MSG_8822C 0
+#define BIT_MASK_FW_MSG_8822C 0xffffffffL
+#define BIT_FW_MSG_8822C(x) \
+ (((x) & BIT_MASK_FW_MSG_8822C) << BIT_SHIFT_FW_MSG_8822C)
+#define BITS_FW_MSG_8822C (BIT_MASK_FW_MSG_8822C << BIT_SHIFT_FW_MSG_8822C)
+#define BIT_CLEAR_FW_MSG_8822C(x) ((x) & (~BITS_FW_MSG_8822C))
+#define BIT_GET_FW_MSG_8822C(x) \
+ (((x) >> BIT_SHIFT_FW_MSG_8822C) & BIT_MASK_FW_MSG_8822C)
+#define BIT_SET_FW_MSG_8822C(x, v) \
+ (BIT_CLEAR_FW_MSG_8822C(x) | BIT_FW_MSG_8822C(v))
+
+/* 2 REG_HMETFR_8822C */
+
+#define BIT_SHIFT_HRCV_MSG_8822C 24
+#define BIT_MASK_HRCV_MSG_8822C 0xff
+#define BIT_HRCV_MSG_8822C(x) \
+ (((x) & BIT_MASK_HRCV_MSG_8822C) << BIT_SHIFT_HRCV_MSG_8822C)
+#define BITS_HRCV_MSG_8822C \
+ (BIT_MASK_HRCV_MSG_8822C << BIT_SHIFT_HRCV_MSG_8822C)
+#define BIT_CLEAR_HRCV_MSG_8822C(x) ((x) & (~BITS_HRCV_MSG_8822C))
+#define BIT_GET_HRCV_MSG_8822C(x) \
+ (((x) >> BIT_SHIFT_HRCV_MSG_8822C) & BIT_MASK_HRCV_MSG_8822C)
+#define BIT_SET_HRCV_MSG_8822C(x, v) \
+ (BIT_CLEAR_HRCV_MSG_8822C(x) | BIT_HRCV_MSG_8822C(v))
+
+#define BIT_INT_BOX3_8822C BIT(3)
+#define BIT_INT_BOX2_8822C BIT(2)
+#define BIT_INT_BOX1_8822C BIT(1)
+#define BIT_INT_BOX0_8822C BIT(0)
+
+/* 2 REG_HMEBOX0_8822C */
+
+#define BIT_SHIFT_HOST_MSG_0_8822C 0
+#define BIT_MASK_HOST_MSG_0_8822C 0xffffffffL
+#define BIT_HOST_MSG_0_8822C(x) \
+ (((x) & BIT_MASK_HOST_MSG_0_8822C) << BIT_SHIFT_HOST_MSG_0_8822C)
+#define BITS_HOST_MSG_0_8822C \
+ (BIT_MASK_HOST_MSG_0_8822C << BIT_SHIFT_HOST_MSG_0_8822C)
+#define BIT_CLEAR_HOST_MSG_0_8822C(x) ((x) & (~BITS_HOST_MSG_0_8822C))
+#define BIT_GET_HOST_MSG_0_8822C(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_0_8822C) & BIT_MASK_HOST_MSG_0_8822C)
+#define BIT_SET_HOST_MSG_0_8822C(x, v) \
+ (BIT_CLEAR_HOST_MSG_0_8822C(x) | BIT_HOST_MSG_0_8822C(v))
+
+/* 2 REG_HMEBOX1_8822C */
+
+#define BIT_SHIFT_HOST_MSG_1_8822C 0
+#define BIT_MASK_HOST_MSG_1_8822C 0xffffffffL
+#define BIT_HOST_MSG_1_8822C(x) \
+ (((x) & BIT_MASK_HOST_MSG_1_8822C) << BIT_SHIFT_HOST_MSG_1_8822C)
+#define BITS_HOST_MSG_1_8822C \
+ (BIT_MASK_HOST_MSG_1_8822C << BIT_SHIFT_HOST_MSG_1_8822C)
+#define BIT_CLEAR_HOST_MSG_1_8822C(x) ((x) & (~BITS_HOST_MSG_1_8822C))
+#define BIT_GET_HOST_MSG_1_8822C(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_1_8822C) & BIT_MASK_HOST_MSG_1_8822C)
+#define BIT_SET_HOST_MSG_1_8822C(x, v) \
+ (BIT_CLEAR_HOST_MSG_1_8822C(x) | BIT_HOST_MSG_1_8822C(v))
+
+/* 2 REG_HMEBOX2_8822C */
+
+#define BIT_SHIFT_HOST_MSG_2_8822C 0
+#define BIT_MASK_HOST_MSG_2_8822C 0xffffffffL
+#define BIT_HOST_MSG_2_8822C(x) \
+ (((x) & BIT_MASK_HOST_MSG_2_8822C) << BIT_SHIFT_HOST_MSG_2_8822C)
+#define BITS_HOST_MSG_2_8822C \
+ (BIT_MASK_HOST_MSG_2_8822C << BIT_SHIFT_HOST_MSG_2_8822C)
+#define BIT_CLEAR_HOST_MSG_2_8822C(x) ((x) & (~BITS_HOST_MSG_2_8822C))
+#define BIT_GET_HOST_MSG_2_8822C(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_2_8822C) & BIT_MASK_HOST_MSG_2_8822C)
+#define BIT_SET_HOST_MSG_2_8822C(x, v) \
+ (BIT_CLEAR_HOST_MSG_2_8822C(x) | BIT_HOST_MSG_2_8822C(v))
+
+/* 2 REG_HMEBOX3_8822C */
+
+#define BIT_SHIFT_HOST_MSG_3_8822C 0
+#define BIT_MASK_HOST_MSG_3_8822C 0xffffffffL
+#define BIT_HOST_MSG_3_8822C(x) \
+ (((x) & BIT_MASK_HOST_MSG_3_8822C) << BIT_SHIFT_HOST_MSG_3_8822C)
+#define BITS_HOST_MSG_3_8822C \
+ (BIT_MASK_HOST_MSG_3_8822C << BIT_SHIFT_HOST_MSG_3_8822C)
+#define BIT_CLEAR_HOST_MSG_3_8822C(x) ((x) & (~BITS_HOST_MSG_3_8822C))
+#define BIT_GET_HOST_MSG_3_8822C(x) \
+ (((x) >> BIT_SHIFT_HOST_MSG_3_8822C) & BIT_MASK_HOST_MSG_3_8822C)
+#define BIT_SET_HOST_MSG_3_8822C(x, v) \
+ (BIT_CLEAR_HOST_MSG_3_8822C(x) | BIT_HOST_MSG_3_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_BB_ACCESS_CTRL_8822C */
+
+#define BIT_SHIFT_BB_WRITE_READ_8822C 30
+#define BIT_MASK_BB_WRITE_READ_8822C 0x3
+#define BIT_BB_WRITE_READ_8822C(x) \
+ (((x) & BIT_MASK_BB_WRITE_READ_8822C) << BIT_SHIFT_BB_WRITE_READ_8822C)
+#define BITS_BB_WRITE_READ_8822C \
+ (BIT_MASK_BB_WRITE_READ_8822C << BIT_SHIFT_BB_WRITE_READ_8822C)
+#define BIT_CLEAR_BB_WRITE_READ_8822C(x) ((x) & (~BITS_BB_WRITE_READ_8822C))
+#define BIT_GET_BB_WRITE_READ_8822C(x) \
+ (((x) >> BIT_SHIFT_BB_WRITE_READ_8822C) & BIT_MASK_BB_WRITE_READ_8822C)
+#define BIT_SET_BB_WRITE_READ_8822C(x, v) \
+ (BIT_CLEAR_BB_WRITE_READ_8822C(x) | BIT_BB_WRITE_READ_8822C(v))
+
+#define BIT_SHIFT_BB_WRITE_EN_8822C 12
+#define BIT_MASK_BB_WRITE_EN_8822C 0xf
+#define BIT_BB_WRITE_EN_8822C(x) \
+ (((x) & BIT_MASK_BB_WRITE_EN_8822C) << BIT_SHIFT_BB_WRITE_EN_8822C)
+#define BITS_BB_WRITE_EN_8822C \
+ (BIT_MASK_BB_WRITE_EN_8822C << BIT_SHIFT_BB_WRITE_EN_8822C)
+#define BIT_CLEAR_BB_WRITE_EN_8822C(x) ((x) & (~BITS_BB_WRITE_EN_8822C))
+#define BIT_GET_BB_WRITE_EN_8822C(x) \
+ (((x) >> BIT_SHIFT_BB_WRITE_EN_8822C) & BIT_MASK_BB_WRITE_EN_8822C)
+#define BIT_SET_BB_WRITE_EN_8822C(x, v) \
+ (BIT_CLEAR_BB_WRITE_EN_8822C(x) | BIT_BB_WRITE_EN_8822C(v))
+
+#define BIT_SHIFT_BB_ADDR_8822C 2
+#define BIT_MASK_BB_ADDR_8822C 0x1ff
+#define BIT_BB_ADDR_8822C(x) \
+ (((x) & BIT_MASK_BB_ADDR_8822C) << BIT_SHIFT_BB_ADDR_8822C)
+#define BITS_BB_ADDR_8822C (BIT_MASK_BB_ADDR_8822C << BIT_SHIFT_BB_ADDR_8822C)
+#define BIT_CLEAR_BB_ADDR_8822C(x) ((x) & (~BITS_BB_ADDR_8822C))
+#define BIT_GET_BB_ADDR_8822C(x) \
+ (((x) >> BIT_SHIFT_BB_ADDR_8822C) & BIT_MASK_BB_ADDR_8822C)
+#define BIT_SET_BB_ADDR_8822C(x, v) \
+ (BIT_CLEAR_BB_ADDR_8822C(x) | BIT_BB_ADDR_8822C(v))
+
+#define BIT_BB_ERRACC_8822C BIT(0)
+
+/* 2 REG_BB_ACCESS_DATA_8822C */
+
+#define BIT_SHIFT_BB_DATA_8822C 0
+#define BIT_MASK_BB_DATA_8822C 0xffffffffL
+#define BIT_BB_DATA_8822C(x) \
+ (((x) & BIT_MASK_BB_DATA_8822C) << BIT_SHIFT_BB_DATA_8822C)
+#define BITS_BB_DATA_8822C (BIT_MASK_BB_DATA_8822C << BIT_SHIFT_BB_DATA_8822C)
+#define BIT_CLEAR_BB_DATA_8822C(x) ((x) & (~BITS_BB_DATA_8822C))
+#define BIT_GET_BB_DATA_8822C(x) \
+ (((x) >> BIT_SHIFT_BB_DATA_8822C) & BIT_MASK_BB_DATA_8822C)
+#define BIT_SET_BB_DATA_8822C(x, v) \
+ (BIT_CLEAR_BB_DATA_8822C(x) | BIT_BB_DATA_8822C(v))
+
+/* 2 REG_HMEBOX_E0_8822C */
+
+#define BIT_SHIFT_HMEBOX_E0_8822C 0
+#define BIT_MASK_HMEBOX_E0_8822C 0xffffffffL
+#define BIT_HMEBOX_E0_8822C(x) \
+ (((x) & BIT_MASK_HMEBOX_E0_8822C) << BIT_SHIFT_HMEBOX_E0_8822C)
+#define BITS_HMEBOX_E0_8822C \
+ (BIT_MASK_HMEBOX_E0_8822C << BIT_SHIFT_HMEBOX_E0_8822C)
+#define BIT_CLEAR_HMEBOX_E0_8822C(x) ((x) & (~BITS_HMEBOX_E0_8822C))
+#define BIT_GET_HMEBOX_E0_8822C(x) \
+ (((x) >> BIT_SHIFT_HMEBOX_E0_8822C) & BIT_MASK_HMEBOX_E0_8822C)
+#define BIT_SET_HMEBOX_E0_8822C(x, v) \
+ (BIT_CLEAR_HMEBOX_E0_8822C(x) | BIT_HMEBOX_E0_8822C(v))
+
+/* 2 REG_HMEBOX_E1_8822C */
+
+#define BIT_SHIFT_HMEBOX_E1_8822C 0
+#define BIT_MASK_HMEBOX_E1_8822C 0xffffffffL
+#define BIT_HMEBOX_E1_8822C(x) \
+ (((x) & BIT_MASK_HMEBOX_E1_8822C) << BIT_SHIFT_HMEBOX_E1_8822C)
+#define BITS_HMEBOX_E1_8822C \
+ (BIT_MASK_HMEBOX_E1_8822C << BIT_SHIFT_HMEBOX_E1_8822C)
+#define BIT_CLEAR_HMEBOX_E1_8822C(x) ((x) & (~BITS_HMEBOX_E1_8822C))
+#define BIT_GET_HMEBOX_E1_8822C(x) \
+ (((x) >> BIT_SHIFT_HMEBOX_E1_8822C) & BIT_MASK_HMEBOX_E1_8822C)
+#define BIT_SET_HMEBOX_E1_8822C(x, v) \
+ (BIT_CLEAR_HMEBOX_E1_8822C(x) | BIT_HMEBOX_E1_8822C(v))
+
+/* 2 REG_HMEBOX_E2_8822C */
+
+#define BIT_SHIFT_HMEBOX_E2_8822C 0
+#define BIT_MASK_HMEBOX_E2_8822C 0xffffffffL
+#define BIT_HMEBOX_E2_8822C(x) \
+ (((x) & BIT_MASK_HMEBOX_E2_8822C) << BIT_SHIFT_HMEBOX_E2_8822C)
+#define BITS_HMEBOX_E2_8822C \
+ (BIT_MASK_HMEBOX_E2_8822C << BIT_SHIFT_HMEBOX_E2_8822C)
+#define BIT_CLEAR_HMEBOX_E2_8822C(x) ((x) & (~BITS_HMEBOX_E2_8822C))
+#define BIT_GET_HMEBOX_E2_8822C(x) \
+ (((x) >> BIT_SHIFT_HMEBOX_E2_8822C) & BIT_MASK_HMEBOX_E2_8822C)
+#define BIT_SET_HMEBOX_E2_8822C(x, v) \
+ (BIT_CLEAR_HMEBOX_E2_8822C(x) | BIT_HMEBOX_E2_8822C(v))
+
+/* 2 REG_HMEBOX_E3_8822C */
+
+#define BIT_SHIFT_HMEBOX_E3_8822C 0
+#define BIT_MASK_HMEBOX_E3_8822C 0xffffffffL
+#define BIT_HMEBOX_E3_8822C(x) \
+ (((x) & BIT_MASK_HMEBOX_E3_8822C) << BIT_SHIFT_HMEBOX_E3_8822C)
+#define BITS_HMEBOX_E3_8822C \
+ (BIT_MASK_HMEBOX_E3_8822C << BIT_SHIFT_HMEBOX_E3_8822C)
+#define BIT_CLEAR_HMEBOX_E3_8822C(x) ((x) & (~BITS_HMEBOX_E3_8822C))
+#define BIT_GET_HMEBOX_E3_8822C(x) \
+ (((x) >> BIT_SHIFT_HMEBOX_E3_8822C) & BIT_MASK_HMEBOX_E3_8822C)
+#define BIT_SET_HMEBOX_E3_8822C(x, v) \
+ (BIT_CLEAR_HMEBOX_E3_8822C(x) | BIT_HMEBOX_E3_8822C(v))
+
+/* 2 REG_CR_EXT_8822C */
+
+#define BIT_SHIFT_PHY_REQ_DELAY_8822C 24
+#define BIT_MASK_PHY_REQ_DELAY_8822C 0xf
+#define BIT_PHY_REQ_DELAY_8822C(x) \
+ (((x) & BIT_MASK_PHY_REQ_DELAY_8822C) << BIT_SHIFT_PHY_REQ_DELAY_8822C)
+#define BITS_PHY_REQ_DELAY_8822C \
+ (BIT_MASK_PHY_REQ_DELAY_8822C << BIT_SHIFT_PHY_REQ_DELAY_8822C)
+#define BIT_CLEAR_PHY_REQ_DELAY_8822C(x) ((x) & (~BITS_PHY_REQ_DELAY_8822C))
+#define BIT_GET_PHY_REQ_DELAY_8822C(x) \
+ (((x) >> BIT_SHIFT_PHY_REQ_DELAY_8822C) & BIT_MASK_PHY_REQ_DELAY_8822C)
+#define BIT_SET_PHY_REQ_DELAY_8822C(x, v) \
+ (BIT_CLEAR_PHY_REQ_DELAY_8822C(x) | BIT_PHY_REQ_DELAY_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_SPD_DOWN_8822C BIT(16)
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_NETYPE4_8822C 4
+#define BIT_MASK_NETYPE4_8822C 0x3
+#define BIT_NETYPE4_8822C(x) \
+ (((x) & BIT_MASK_NETYPE4_8822C) << BIT_SHIFT_NETYPE4_8822C)
+#define BITS_NETYPE4_8822C (BIT_MASK_NETYPE4_8822C << BIT_SHIFT_NETYPE4_8822C)
+#define BIT_CLEAR_NETYPE4_8822C(x) ((x) & (~BITS_NETYPE4_8822C))
+#define BIT_GET_NETYPE4_8822C(x) \
+ (((x) >> BIT_SHIFT_NETYPE4_8822C) & BIT_MASK_NETYPE4_8822C)
+#define BIT_SET_NETYPE4_8822C(x, v) \
+ (BIT_CLEAR_NETYPE4_8822C(x) | BIT_NETYPE4_8822C(v))
+
+#define BIT_SHIFT_NETYPE3_8822C 2
+#define BIT_MASK_NETYPE3_8822C 0x3
+#define BIT_NETYPE3_8822C(x) \
+ (((x) & BIT_MASK_NETYPE3_8822C) << BIT_SHIFT_NETYPE3_8822C)
+#define BITS_NETYPE3_8822C (BIT_MASK_NETYPE3_8822C << BIT_SHIFT_NETYPE3_8822C)
+#define BIT_CLEAR_NETYPE3_8822C(x) ((x) & (~BITS_NETYPE3_8822C))
+#define BIT_GET_NETYPE3_8822C(x) \
+ (((x) >> BIT_SHIFT_NETYPE3_8822C) & BIT_MASK_NETYPE3_8822C)
+#define BIT_SET_NETYPE3_8822C(x, v) \
+ (BIT_CLEAR_NETYPE3_8822C(x) | BIT_NETYPE3_8822C(v))
+
+#define BIT_SHIFT_NETYPE2_8822C 0
+#define BIT_MASK_NETYPE2_8822C 0x3
+#define BIT_NETYPE2_8822C(x) \
+ (((x) & BIT_MASK_NETYPE2_8822C) << BIT_SHIFT_NETYPE2_8822C)
+#define BITS_NETYPE2_8822C (BIT_MASK_NETYPE2_8822C << BIT_SHIFT_NETYPE2_8822C)
+#define BIT_CLEAR_NETYPE2_8822C(x) ((x) & (~BITS_NETYPE2_8822C))
+#define BIT_GET_NETYPE2_8822C(x) \
+ (((x) >> BIT_SHIFT_NETYPE2_8822C) & BIT_MASK_NETYPE2_8822C)
+#define BIT_SET_NETYPE2_8822C(x, v) \
+ (BIT_CLEAR_NETYPE2_8822C(x) | BIT_NETYPE2_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_FWFF_8822C */
+
+#define BIT_SHIFT_PKTNUM_TH_V1_8822C 24
+#define BIT_MASK_PKTNUM_TH_V1_8822C 0xff
+#define BIT_PKTNUM_TH_V1_8822C(x) \
+ (((x) & BIT_MASK_PKTNUM_TH_V1_8822C) << BIT_SHIFT_PKTNUM_TH_V1_8822C)
+#define BITS_PKTNUM_TH_V1_8822C \
+ (BIT_MASK_PKTNUM_TH_V1_8822C << BIT_SHIFT_PKTNUM_TH_V1_8822C)
+#define BIT_CLEAR_PKTNUM_TH_V1_8822C(x) ((x) & (~BITS_PKTNUM_TH_V1_8822C))
+#define BIT_GET_PKTNUM_TH_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_PKTNUM_TH_V1_8822C) & BIT_MASK_PKTNUM_TH_V1_8822C)
+#define BIT_SET_PKTNUM_TH_V1_8822C(x, v) \
+ (BIT_CLEAR_PKTNUM_TH_V1_8822C(x) | BIT_PKTNUM_TH_V1_8822C(v))
+
+#define BIT_SHIFT_TIMER_TH_8822C 16
+#define BIT_MASK_TIMER_TH_8822C 0xff
+#define BIT_TIMER_TH_8822C(x) \
+ (((x) & BIT_MASK_TIMER_TH_8822C) << BIT_SHIFT_TIMER_TH_8822C)
+#define BITS_TIMER_TH_8822C \
+ (BIT_MASK_TIMER_TH_8822C << BIT_SHIFT_TIMER_TH_8822C)
+#define BIT_CLEAR_TIMER_TH_8822C(x) ((x) & (~BITS_TIMER_TH_8822C))
+#define BIT_GET_TIMER_TH_8822C(x) \
+ (((x) >> BIT_SHIFT_TIMER_TH_8822C) & BIT_MASK_TIMER_TH_8822C)
+#define BIT_SET_TIMER_TH_8822C(x, v) \
+ (BIT_CLEAR_TIMER_TH_8822C(x) | BIT_TIMER_TH_8822C(v))
+
+#define BIT_SHIFT_RXPKT1ENADDR_8822C 0
+#define BIT_MASK_RXPKT1ENADDR_8822C 0xffff
+#define BIT_RXPKT1ENADDR_8822C(x) \
+ (((x) & BIT_MASK_RXPKT1ENADDR_8822C) << BIT_SHIFT_RXPKT1ENADDR_8822C)
+#define BITS_RXPKT1ENADDR_8822C \
+ (BIT_MASK_RXPKT1ENADDR_8822C << BIT_SHIFT_RXPKT1ENADDR_8822C)
+#define BIT_CLEAR_RXPKT1ENADDR_8822C(x) ((x) & (~BITS_RXPKT1ENADDR_8822C))
+#define BIT_GET_RXPKT1ENADDR_8822C(x) \
+ (((x) >> BIT_SHIFT_RXPKT1ENADDR_8822C) & BIT_MASK_RXPKT1ENADDR_8822C)
+#define BIT_SET_RXPKT1ENADDR_8822C(x, v) \
+ (BIT_CLEAR_RXPKT1ENADDR_8822C(x) | BIT_RXPKT1ENADDR_8822C(v))
+
+/* 2 REG_RXFF_PTR_V1_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_RXFF0_RDPTR_V2_8822C 0
+#define BIT_MASK_RXFF0_RDPTR_V2_8822C 0x3ffff
+#define BIT_RXFF0_RDPTR_V2_8822C(x) \
+ (((x) & BIT_MASK_RXFF0_RDPTR_V2_8822C) \
+ << BIT_SHIFT_RXFF0_RDPTR_V2_8822C)
+#define BITS_RXFF0_RDPTR_V2_8822C \
+ (BIT_MASK_RXFF0_RDPTR_V2_8822C << BIT_SHIFT_RXFF0_RDPTR_V2_8822C)
+#define BIT_CLEAR_RXFF0_RDPTR_V2_8822C(x) ((x) & (~BITS_RXFF0_RDPTR_V2_8822C))
+#define BIT_GET_RXFF0_RDPTR_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8822C) & \
+ BIT_MASK_RXFF0_RDPTR_V2_8822C)
+#define BIT_SET_RXFF0_RDPTR_V2_8822C(x, v) \
+ (BIT_CLEAR_RXFF0_RDPTR_V2_8822C(x) | BIT_RXFF0_RDPTR_V2_8822C(v))
+
+/* 2 REG_RXFF_WTR_V1_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_RXFF0_WTPTR_V2_8822C 0
+#define BIT_MASK_RXFF0_WTPTR_V2_8822C 0x3ffff
+#define BIT_RXFF0_WTPTR_V2_8822C(x) \
+ (((x) & BIT_MASK_RXFF0_WTPTR_V2_8822C) \
+ << BIT_SHIFT_RXFF0_WTPTR_V2_8822C)
+#define BITS_RXFF0_WTPTR_V2_8822C \
+ (BIT_MASK_RXFF0_WTPTR_V2_8822C << BIT_SHIFT_RXFF0_WTPTR_V2_8822C)
+#define BIT_CLEAR_RXFF0_WTPTR_V2_8822C(x) ((x) & (~BITS_RXFF0_WTPTR_V2_8822C))
+#define BIT_GET_RXFF0_WTPTR_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8822C) & \
+ BIT_MASK_RXFF0_WTPTR_V2_8822C)
+#define BIT_SET_RXFF0_WTPTR_V2_8822C(x, v) \
+ (BIT_CLEAR_RXFF0_WTPTR_V2_8822C(x) | BIT_RXFF0_WTPTR_V2_8822C(v))
+
+/* 2 REG_FE2IMR_8822C */
+#define BIT__FE4ISR__IND_MSK_8822C BIT(29)
+#define BIT_FS_TXSC_DESC_DONE_INT_EN_8822C BIT(28)
+#define BIT_FS_TXSC_BKDONE_INT_EN_8822C BIT(27)
+#define BIT_FS_TXSC_BEDONE_INT_EN_8822C BIT(26)
+#define BIT_FS_TXSC_VIDONE_INT_EN_8822C BIT(25)
+#define BIT_FS_TXSC_VODONE_INT_EN_8822C BIT(24)
+#define BIT_FS_ATIM_MB7_INT_EN_8822C BIT(23)
+#define BIT_FS_ATIM_MB6_INT_EN_8822C BIT(22)
+#define BIT_FS_ATIM_MB5_INT_EN_8822C BIT(21)
+#define BIT_FS_ATIM_MB4_INT_EN_8822C BIT(20)
+#define BIT_FS_ATIM_MB3_INT_EN_8822C BIT(19)
+#define BIT_FS_ATIM_MB2_INT_EN_8822C BIT(18)
+#define BIT_FS_ATIM_MB1_INT_EN_8822C BIT(17)
+#define BIT_FS_ATIM_MB0_INT_EN_8822C BIT(16)
+#define BIT_FS_TBTT4INT_EN_8822C BIT(11)
+#define BIT_FS_TBTT3INT_EN_8822C BIT(10)
+#define BIT_FS_TBTT2INT_EN_8822C BIT(9)
+#define BIT_FS_TBTT1INT_EN_8822C BIT(8)
+#define BIT_FS_TBTT0_MB7INT_EN_8822C BIT(7)
+#define BIT_FS_TBTT0_MB6INT_EN_8822C BIT(6)
+#define BIT_FS_TBTT0_MB5INT_EN_8822C BIT(5)
+#define BIT_FS_TBTT0_MB4INT_EN_8822C BIT(4)
+#define BIT_FS_TBTT0_MB3INT_EN_8822C BIT(3)
+#define BIT_FS_TBTT0_MB2INT_EN_8822C BIT(2)
+#define BIT_FS_TBTT0_MB1INT_EN_8822C BIT(1)
+#define BIT_FS_TBTT0_INT_EN_8822C BIT(0)
+
+/* 2 REG_FE2ISR_8822C */
+#define BIT__FE4ISR__IND_INT_8822C BIT(29)
+#define BIT_FS_TXSC_DESC_DONE_INT_8822C BIT(28)
+#define BIT_FS_TXSC_BKDONE_INT_8822C BIT(27)
+#define BIT_FS_TXSC_BEDONE_INT_8822C BIT(26)
+#define BIT_FS_TXSC_VIDONE_INT_8822C BIT(25)
+#define BIT_FS_TXSC_VODONE_INT_8822C BIT(24)
+#define BIT_FS_ATIM_MB7_INT_8822C BIT(23)
+#define BIT_FS_ATIM_MB6_INT_8822C BIT(22)
+#define BIT_FS_ATIM_MB5_INT_8822C BIT(21)
+#define BIT_FS_ATIM_MB4_INT_8822C BIT(20)
+#define BIT_FS_ATIM_MB3_INT_8822C BIT(19)
+#define BIT_FS_ATIM_MB2_INT_8822C BIT(18)
+#define BIT_FS_ATIM_MB1_INT_8822C BIT(17)
+#define BIT_FS_ATIM_MB0_INT_8822C BIT(16)
+#define BIT_FS_TBTT4INT_8822C BIT(11)
+#define BIT_FS_TBTT3INT_8822C BIT(10)
+#define BIT_FS_TBTT2INT_8822C BIT(9)
+#define BIT_FS_TBTT1INT_8822C BIT(8)
+#define BIT_FS_TBTT0_MB7INT_8822C BIT(7)
+#define BIT_FS_TBTT0_MB6INT_8822C BIT(6)
+#define BIT_FS_TBTT0_MB5INT_8822C BIT(5)
+#define BIT_FS_TBTT0_MB4INT_8822C BIT(4)
+#define BIT_FS_TBTT0_MB3INT_8822C BIT(3)
+#define BIT_FS_TBTT0_MB2INT_8822C BIT(2)
+#define BIT_FS_TBTT0_MB1INT_8822C BIT(1)
+#define BIT_FS_TBTT0_INT_8822C BIT(0)
+
+/* 2 REG_FE3IMR_8822C */
+#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT__EN_8822C BIT(31)
+#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT__EN_8822C BIT(30)
+#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT__EN_8822C BIT(29)
+#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT__EN_8822C BIT(28)
+#define BIT_FS_BCNDMA4_INT_EN_8822C BIT(27)
+#define BIT_FS_BCNDMA3_INT_EN_8822C BIT(26)
+#define BIT_FS_BCNDMA2_INT_EN_8822C BIT(25)
+#define BIT_FS_BCNDMA1_INT_EN_8822C BIT(24)
+#define BIT_FS_BCNDMA0_MB7_INT_EN_8822C BIT(23)
+#define BIT_FS_BCNDMA0_MB6_INT_EN_8822C BIT(22)
+#define BIT_FS_BCNDMA0_MB5_INT_EN_8822C BIT(21)
+#define BIT_FS_BCNDMA0_MB4_INT_EN_8822C BIT(20)
+#define BIT_FS_BCNDMA0_MB3_INT_EN_8822C BIT(19)
+#define BIT_FS_BCNDMA0_MB2_INT_EN_8822C BIT(18)
+#define BIT_FS_BCNDMA0_MB1_INT_EN_8822C BIT(17)
+#define BIT_FS_BCNDMA0_INT_EN_8822C BIT(16)
+#define BIT_FS_MTI_BCNIVLEAR_INT__EN_8822C BIT(15)
+#define BIT_FS_BCNERLY4_INT_EN_8822C BIT(11)
+#define BIT_FS_BCNERLY3_INT_EN_8822C BIT(10)
+#define BIT_FS_BCNERLY2_INT_EN_8822C BIT(9)
+#define BIT_FS_BCNERLY1_INT_EN_8822C BIT(8)
+#define BIT_FS_BCNERLY0_MB7INT_EN_8822C BIT(7)
+#define BIT_FS_BCNERLY0_MB6INT_EN_8822C BIT(6)
+#define BIT_FS_BCNERLY0_MB5INT_EN_8822C BIT(5)
+#define BIT_FS_BCNERLY0_MB4INT_EN_8822C BIT(4)
+#define BIT_FS_BCNERLY0_MB3INT_EN_8822C BIT(3)
+#define BIT_FS_BCNERLY0_MB2INT_EN_8822C BIT(2)
+#define BIT_FS_BCNERLY0_MB1INT_EN_8822C BIT(1)
+#define BIT_FS_BCNERLY0_INT_EN_8822C BIT(0)
+
+/* 2 REG_FE3ISR_8822C */
+#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT_8822C BIT(31)
+#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT_8822C BIT(30)
+#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT_8822C BIT(29)
+#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT_8822C BIT(28)
+#define BIT_FS_BCNDMA4_INT_8822C BIT(27)
+#define BIT_FS_BCNDMA3_INT_8822C BIT(26)
+#define BIT_FS_BCNDMA2_INT_8822C BIT(25)
+#define BIT_FS_BCNDMA1_INT_8822C BIT(24)
+#define BIT_FS_BCNDMA0_MB7_INT_8822C BIT(23)
+#define BIT_FS_BCNDMA0_MB6_INT_8822C BIT(22)
+#define BIT_FS_BCNDMA0_MB5_INT_8822C BIT(21)
+#define BIT_FS_BCNDMA0_MB4_INT_8822C BIT(20)
+#define BIT_FS_BCNDMA0_MB3_INT_8822C BIT(19)
+#define BIT_FS_BCNDMA0_MB2_INT_8822C BIT(18)
+#define BIT_FS_BCNDMA0_MB1_INT_8822C BIT(17)
+#define BIT_FS_BCNDMA0_INT_8822C BIT(16)
+#define BIT_FS_MTI_BCNIVLEAR_INT_8822C BIT(15)
+#define BIT_FS_BCNERLY4_INT_8822C BIT(11)
+#define BIT_FS_BCNERLY3_INT_8822C BIT(10)
+#define BIT_FS_BCNERLY2_INT_8822C BIT(9)
+#define BIT_FS_BCNERLY1_INT_8822C BIT(8)
+#define BIT_FS_BCNERLY0_MB7INT_8822C BIT(7)
+#define BIT_FS_BCNERLY0_MB6INT_8822C BIT(6)
+#define BIT_FS_BCNERLY0_MB5INT_8822C BIT(5)
+#define BIT_FS_BCNERLY0_MB4INT_8822C BIT(4)
+#define BIT_FS_BCNERLY0_MB3INT_8822C BIT(3)
+#define BIT_FS_BCNERLY0_MB2INT_8822C BIT(2)
+#define BIT_FS_BCNERLY0_MB1INT_8822C BIT(1)
+#define BIT_FS_BCNERLY0_INT_8822C BIT(0)
+
+/* 2 REG_FE4IMR_8822C */
+#define BIT_FS_CLI3_TXPKTIN_INT_EN_8822C BIT(19)
+#define BIT_FS_CLI2_TXPKTIN_INT_EN_8822C BIT(18)
+#define BIT_FS_CLI1_TXPKTIN_INT_EN_8822C BIT(17)
+#define BIT_FS_CLI0_TXPKTIN_INT_EN_8822C BIT(16)
+#define BIT_FS_CLI3_RX_UMD0_INT_EN_8822C BIT(15)
+#define BIT_FS_CLI3_RX_UMD1_INT_EN_8822C BIT(14)
+#define BIT_FS_CLI3_RX_BMD0_INT_EN_8822C BIT(13)
+#define BIT_FS_CLI3_RX_BMD1_INT_EN_8822C BIT(12)
+#define BIT_FS_CLI2_RX_UMD0_INT_EN_8822C BIT(11)
+#define BIT_FS_CLI2_RX_UMD1_INT_EN_8822C BIT(10)
+#define BIT_FS_CLI2_RX_BMD0_INT_EN_8822C BIT(9)
+#define BIT_FS_CLI2_RX_BMD1_INT_EN_8822C BIT(8)
+#define BIT_FS_CLI1_RX_UMD0_INT_EN_8822C BIT(7)
+#define BIT_FS_CLI1_RX_UMD1_INT_EN_8822C BIT(6)
+#define BIT_FS_CLI1_RX_BMD0_INT_EN_8822C BIT(5)
+#define BIT_FS_CLI1_RX_BMD1_INT_EN_8822C BIT(4)
+#define BIT_FS_CLI0_RX_UMD0_INT_EN_8822C BIT(3)
+#define BIT_FS_CLI0_RX_UMD1_INT_EN_8822C BIT(2)
+#define BIT_FS_CLI0_RX_BMD0_INT_EN_8822C BIT(1)
+#define BIT_FS_CLI0_RX_BMD1_INT_EN_8822C BIT(0)
+
+/* 2 REG_FE4ISR_8822C */
+#define BIT_FS_CLI3_TXPKTIN_INT_8822C BIT(19)
+#define BIT_FS_CLI2_TXPKTIN_INT_8822C BIT(18)
+#define BIT_FS_CLI1_TXPKTIN_INT_8822C BIT(17)
+#define BIT_FS_CLI0_TXPKTIN_INT_8822C BIT(16)
+#define BIT_FS_CLI3_RX_UMD0_INT_8822C BIT(15)
+#define BIT_FS_CLI3_RX_UMD1_INT_8822C BIT(14)
+#define BIT_FS_CLI3_RX_BMD0_INT_8822C BIT(13)
+#define BIT_FS_CLI3_RX_BMD1_INT_8822C BIT(12)
+#define BIT_FS_CLI2_RX_UMD0_INT_8822C BIT(11)
+#define BIT_FS_CLI2_RX_UMD1_INT_8822C BIT(10)
+#define BIT_FS_CLI2_RX_BMD0_INT_8822C BIT(9)
+#define BIT_FS_CLI2_RX_BMD1_INT_8822C BIT(8)
+#define BIT_FS_CLI1_RX_UMD0_INT_8822C BIT(7)
+#define BIT_FS_CLI1_RX_UMD1_INT_8822C BIT(6)
+#define BIT_FS_CLI1_RX_BMD0_INT_8822C BIT(5)
+#define BIT_FS_CLI1_RX_BMD1_INT_8822C BIT(4)
+#define BIT_FS_CLI0_RX_UMD0_INT_8822C BIT(3)
+#define BIT_FS_CLI0_RX_UMD1_INT_8822C BIT(2)
+#define BIT_FS_CLI0_RX_BMD0_INT_8822C BIT(1)
+#define BIT_FS_CLI0_RX_BMD1_INT_8822C BIT(0)
+
+/* 2 REG_FT1IMR_8822C */
+#define BIT__FT2ISR__IND_MSK_8822C BIT(30)
+#define BIT_FTM_PTT_INT_EN_8822C BIT(29)
+#define BIT_RXFTMREQ_INT_EN_8822C BIT(28)
+#define BIT_RXFTM_INT_EN_8822C BIT(27)
+#define BIT_TXFTM_INT_EN_8822C BIT(26)
+#define BIT_FS_H2C_CMD_OK_INT_EN_8822C BIT(25)
+#define BIT_FS_H2C_CMD_FULL_INT_EN_8822C BIT(24)
+#define BIT_FS_MACID_PWRCHANGE5_INT_EN_8822C BIT(23)
+#define BIT_FS_MACID_PWRCHANGE4_INT_EN_8822C BIT(22)
+#define BIT_FS_MACID_PWRCHANGE3_INT_EN_8822C BIT(21)
+#define BIT_FS_MACID_PWRCHANGE2_INT_EN_8822C BIT(20)
+#define BIT_FS_MACID_PWRCHANGE1_INT_EN_8822C BIT(19)
+#define BIT_FS_MACID_PWRCHANGE0_INT_EN_8822C BIT(18)
+#define BIT_FS_CTWEND2_INT_EN_8822C BIT(17)
+#define BIT_FS_CTWEND1_INT_EN_8822C BIT(16)
+#define BIT_FS_CTWEND0_INT_EN_8822C BIT(15)
+#define BIT_FS_TX_NULL1_INT_EN_8822C BIT(14)
+#define BIT_FS_TX_NULL0_INT_EN_8822C BIT(13)
+#define BIT_FS_TSF_BIT32_TOGGLE_EN_8822C BIT(12)
+#define BIT_FS_P2P_RFON2_INT_EN_8822C BIT(11)
+#define BIT_FS_P2P_RFOFF2_INT_EN_8822C BIT(10)
+#define BIT_FS_P2P_RFON1_INT_EN_8822C BIT(9)
+#define BIT_FS_P2P_RFOFF1_INT_EN_8822C BIT(8)
+#define BIT_FS_P2P_RFON0_INT_EN_8822C BIT(7)
+#define BIT_FS_P2P_RFOFF0_INT_EN_8822C BIT(6)
+#define BIT_FS_RX_UAPSDMD1_EN_8822C BIT(5)
+#define BIT_FS_RX_UAPSDMD0_EN_8822C BIT(4)
+#define BIT_FS_TRIGGER_PKT_EN_8822C BIT(3)
+#define BIT_FS_EOSP_INT_EN_8822C BIT(2)
+#define BIT_FS_RPWM2_INT_EN_8822C BIT(1)
+#define BIT_FS_RPWM_INT_EN_8822C BIT(0)
+
+/* 2 REG_FT1ISR_8822C */
+#define BIT__FT2ISR__IND_INT_8822C BIT(30)
+#define BIT_FTM_PTT_INT_8822C BIT(29)
+#define BIT_RXFTMREQ_INT_8822C BIT(28)
+#define BIT_RXFTM_INT_8822C BIT(27)
+#define BIT_TXFTM_INT_8822C BIT(26)
+#define BIT_FS_H2C_CMD_OK_INT_8822C BIT(25)
+#define BIT_FS_H2C_CMD_FULL_INT_8822C BIT(24)
+#define BIT_FS_MACID_PWRCHANGE5_INT_8822C BIT(23)
+#define BIT_FS_MACID_PWRCHANGE4_INT_8822C BIT(22)
+#define BIT_FS_MACID_PWRCHANGE3_INT_8822C BIT(21)
+#define BIT_FS_MACID_PWRCHANGE2_INT_8822C BIT(20)
+#define BIT_FS_MACID_PWRCHANGE1_INT_8822C BIT(19)
+#define BIT_FS_MACID_PWRCHANGE0_INT_8822C BIT(18)
+#define BIT_FS_CTWEND2_INT_8822C BIT(17)
+#define BIT_FS_CTWEND1_INT_8822C BIT(16)
+#define BIT_FS_CTWEND0_INT_8822C BIT(15)
+#define BIT_FS_TX_NULL1_INT_8822C BIT(14)
+#define BIT_FS_TX_NULL0_INT_8822C BIT(13)
+#define BIT_FS_TSF_BIT32_TOGGLE_INT_8822C BIT(12)
+#define BIT_FS_P2P_RFON2_INT_8822C BIT(11)
+#define BIT_FS_P2P_RFOFF2_INT_8822C BIT(10)
+#define BIT_FS_P2P_RFON1_INT_8822C BIT(9)
+#define BIT_FS_P2P_RFOFF1_INT_8822C BIT(8)
+#define BIT_FS_P2P_RFON0_INT_8822C BIT(7)
+#define BIT_FS_P2P_RFOFF0_INT_8822C BIT(6)
+#define BIT_FS_RX_UAPSDMD1_INT_8822C BIT(5)
+#define BIT_FS_RX_UAPSDMD0_INT_8822C BIT(4)
+#define BIT_FS_TRIGGER_PKT_INT_8822C BIT(3)
+#define BIT_FS_EOSP_INT_8822C BIT(2)
+#define BIT_FS_RPWM2_INT_8822C BIT(1)
+#define BIT_FS_RPWM_INT_8822C BIT(0)
+
+/* 2 REG_SPWR0_8822C */
+
+#define BIT_SHIFT_MID_31TO0_8822C 0
+#define BIT_MASK_MID_31TO0_8822C 0xffffffffL
+#define BIT_MID_31TO0_8822C(x) \
+ (((x) & BIT_MASK_MID_31TO0_8822C) << BIT_SHIFT_MID_31TO0_8822C)
+#define BITS_MID_31TO0_8822C \
+ (BIT_MASK_MID_31TO0_8822C << BIT_SHIFT_MID_31TO0_8822C)
+#define BIT_CLEAR_MID_31TO0_8822C(x) ((x) & (~BITS_MID_31TO0_8822C))
+#define BIT_GET_MID_31TO0_8822C(x) \
+ (((x) >> BIT_SHIFT_MID_31TO0_8822C) & BIT_MASK_MID_31TO0_8822C)
+#define BIT_SET_MID_31TO0_8822C(x, v) \
+ (BIT_CLEAR_MID_31TO0_8822C(x) | BIT_MID_31TO0_8822C(v))
+
+/* 2 REG_SPWR1_8822C */
+
+#define BIT_SHIFT_MID_63TO32_8822C 0
+#define BIT_MASK_MID_63TO32_8822C 0xffffffffL
+#define BIT_MID_63TO32_8822C(x) \
+ (((x) & BIT_MASK_MID_63TO32_8822C) << BIT_SHIFT_MID_63TO32_8822C)
+#define BITS_MID_63TO32_8822C \
+ (BIT_MASK_MID_63TO32_8822C << BIT_SHIFT_MID_63TO32_8822C)
+#define BIT_CLEAR_MID_63TO32_8822C(x) ((x) & (~BITS_MID_63TO32_8822C))
+#define BIT_GET_MID_63TO32_8822C(x) \
+ (((x) >> BIT_SHIFT_MID_63TO32_8822C) & BIT_MASK_MID_63TO32_8822C)
+#define BIT_SET_MID_63TO32_8822C(x, v) \
+ (BIT_CLEAR_MID_63TO32_8822C(x) | BIT_MID_63TO32_8822C(v))
+
+/* 2 REG_SPWR2_8822C */
+
+#define BIT_SHIFT_MID_95O64_8822C 0
+#define BIT_MASK_MID_95O64_8822C 0xffffffffL
+#define BIT_MID_95O64_8822C(x) \
+ (((x) & BIT_MASK_MID_95O64_8822C) << BIT_SHIFT_MID_95O64_8822C)
+#define BITS_MID_95O64_8822C \
+ (BIT_MASK_MID_95O64_8822C << BIT_SHIFT_MID_95O64_8822C)
+#define BIT_CLEAR_MID_95O64_8822C(x) ((x) & (~BITS_MID_95O64_8822C))
+#define BIT_GET_MID_95O64_8822C(x) \
+ (((x) >> BIT_SHIFT_MID_95O64_8822C) & BIT_MASK_MID_95O64_8822C)
+#define BIT_SET_MID_95O64_8822C(x, v) \
+ (BIT_CLEAR_MID_95O64_8822C(x) | BIT_MID_95O64_8822C(v))
+
+/* 2 REG_SPWR3_8822C */
+
+#define BIT_SHIFT_MID_127TO96_8822C 0
+#define BIT_MASK_MID_127TO96_8822C 0xffffffffL
+#define BIT_MID_127TO96_8822C(x) \
+ (((x) & BIT_MASK_MID_127TO96_8822C) << BIT_SHIFT_MID_127TO96_8822C)
+#define BITS_MID_127TO96_8822C \
+ (BIT_MASK_MID_127TO96_8822C << BIT_SHIFT_MID_127TO96_8822C)
+#define BIT_CLEAR_MID_127TO96_8822C(x) ((x) & (~BITS_MID_127TO96_8822C))
+#define BIT_GET_MID_127TO96_8822C(x) \
+ (((x) >> BIT_SHIFT_MID_127TO96_8822C) & BIT_MASK_MID_127TO96_8822C)
+#define BIT_SET_MID_127TO96_8822C(x, v) \
+ (BIT_CLEAR_MID_127TO96_8822C(x) | BIT_MID_127TO96_8822C(v))
+
+/* 2 REG_POWSEQ_8822C */
+
+#define BIT_SHIFT_SEQNUM_MID_8822C 16
+#define BIT_MASK_SEQNUM_MID_8822C 0xffff
+#define BIT_SEQNUM_MID_8822C(x) \
+ (((x) & BIT_MASK_SEQNUM_MID_8822C) << BIT_SHIFT_SEQNUM_MID_8822C)
+#define BITS_SEQNUM_MID_8822C \
+ (BIT_MASK_SEQNUM_MID_8822C << BIT_SHIFT_SEQNUM_MID_8822C)
+#define BIT_CLEAR_SEQNUM_MID_8822C(x) ((x) & (~BITS_SEQNUM_MID_8822C))
+#define BIT_GET_SEQNUM_MID_8822C(x) \
+ (((x) >> BIT_SHIFT_SEQNUM_MID_8822C) & BIT_MASK_SEQNUM_MID_8822C)
+#define BIT_SET_SEQNUM_MID_8822C(x, v) \
+ (BIT_CLEAR_SEQNUM_MID_8822C(x) | BIT_SEQNUM_MID_8822C(v))
+
+#define BIT_SHIFT_REF_MID_8822C 0
+#define BIT_MASK_REF_MID_8822C 0x7f
+#define BIT_REF_MID_8822C(x) \
+ (((x) & BIT_MASK_REF_MID_8822C) << BIT_SHIFT_REF_MID_8822C)
+#define BITS_REF_MID_8822C (BIT_MASK_REF_MID_8822C << BIT_SHIFT_REF_MID_8822C)
+#define BIT_CLEAR_REF_MID_8822C(x) ((x) & (~BITS_REF_MID_8822C))
+#define BIT_GET_REF_MID_8822C(x) \
+ (((x) >> BIT_SHIFT_REF_MID_8822C) & BIT_MASK_REF_MID_8822C)
+#define BIT_SET_REF_MID_8822C(x, v) \
+ (BIT_CLEAR_REF_MID_8822C(x) | BIT_REF_MID_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_TC7_CTRL_V1_8822C */
+#define BIT_TC7INT_EN_8822C BIT(26)
+#define BIT_TC7MODE_8822C BIT(25)
+#define BIT_TC7EN_8822C BIT(24)
+
+#define BIT_SHIFT_TC7DATA_8822C 0
+#define BIT_MASK_TC7DATA_8822C 0xffffff
+#define BIT_TC7DATA_8822C(x) \
+ (((x) & BIT_MASK_TC7DATA_8822C) << BIT_SHIFT_TC7DATA_8822C)
+#define BITS_TC7DATA_8822C (BIT_MASK_TC7DATA_8822C << BIT_SHIFT_TC7DATA_8822C)
+#define BIT_CLEAR_TC7DATA_8822C(x) ((x) & (~BITS_TC7DATA_8822C))
+#define BIT_GET_TC7DATA_8822C(x) \
+ (((x) >> BIT_SHIFT_TC7DATA_8822C) & BIT_MASK_TC7DATA_8822C)
+#define BIT_SET_TC7DATA_8822C(x, v) \
+ (BIT_CLEAR_TC7DATA_8822C(x) | BIT_TC7DATA_8822C(v))
+
+/* 2 REG_TC8_CTRL_V1_8822C */
+#define BIT_TC8INT_EN_8822C BIT(26)
+#define BIT_TC8MODE_8822C BIT(25)
+#define BIT_TC8EN_8822C BIT(24)
+
+#define BIT_SHIFT_TC8DATA_8822C 0
+#define BIT_MASK_TC8DATA_8822C 0xffffff
+#define BIT_TC8DATA_8822C(x) \
+ (((x) & BIT_MASK_TC8DATA_8822C) << BIT_SHIFT_TC8DATA_8822C)
+#define BITS_TC8DATA_8822C (BIT_MASK_TC8DATA_8822C << BIT_SHIFT_TC8DATA_8822C)
+#define BIT_CLEAR_TC8DATA_8822C(x) ((x) & (~BITS_TC8DATA_8822C))
+#define BIT_GET_TC8DATA_8822C(x) \
+ (((x) >> BIT_SHIFT_TC8DATA_8822C) & BIT_MASK_TC8DATA_8822C)
+#define BIT_SET_TC8DATA_8822C(x, v) \
+ (BIT_CLEAR_TC8DATA_8822C(x) | BIT_TC8DATA_8822C(v))
+
+/* 2 REG_RX_BCN_TBTT_ITVL0_8822C */
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8822C 24
+#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8822C 0xff
+#define BIT_RX_BCN_TBTT_ITVL_CLIENT2_8822C(x) \
+ (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8822C) \
+ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8822C)
+#define BITS_RX_BCN_TBTT_ITVL_CLIENT2_8822C \
+ (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8822C \
+ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8822C)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2_8822C(x) \
+ ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT2_8822C))
+#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT2_8822C(x) \
+ (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT2_8822C) & \
+ BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT2_8822C)
+#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT2_8822C(x, v) \
+ (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT2_8822C(x) | \
+ BIT_RX_BCN_TBTT_ITVL_CLIENT2_8822C(v))
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8822C 16
+#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8822C 0xff
+#define BIT_RX_BCN_TBTT_ITVL_CLIENT1_8822C(x) \
+ (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8822C) \
+ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8822C)
+#define BITS_RX_BCN_TBTT_ITVL_CLIENT1_8822C \
+ (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8822C \
+ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8822C)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1_8822C(x) \
+ ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT1_8822C))
+#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT1_8822C(x) \
+ (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT1_8822C) & \
+ BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT1_8822C)
+#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT1_8822C(x, v) \
+ (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT1_8822C(x) | \
+ BIT_RX_BCN_TBTT_ITVL_CLIENT1_8822C(v))
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8822C 8
+#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8822C 0xff
+#define BIT_RX_BCN_TBTT_ITVL_CLIENT0_8822C(x) \
+ (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8822C) \
+ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8822C)
+#define BITS_RX_BCN_TBTT_ITVL_CLIENT0_8822C \
+ (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8822C \
+ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8822C)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0_8822C(x) \
+ ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT0_8822C))
+#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT0_8822C(x) \
+ (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT0_8822C) & \
+ BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT0_8822C)
+#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT0_8822C(x, v) \
+ (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT0_8822C(x) | \
+ BIT_RX_BCN_TBTT_ITVL_CLIENT0_8822C(v))
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8822C 0
+#define BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8822C 0xff
+#define BIT_RX_BCN_TBTT_ITVL_PORT0_8822C(x) \
+ (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8822C) \
+ << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8822C)
+#define BITS_RX_BCN_TBTT_ITVL_PORT0_8822C \
+ (BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8822C \
+ << BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8822C)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0_8822C(x) \
+ ((x) & (~BITS_RX_BCN_TBTT_ITVL_PORT0_8822C))
+#define BIT_GET_RX_BCN_TBTT_ITVL_PORT0_8822C(x) \
+ (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_PORT0_8822C) & \
+ BIT_MASK_RX_BCN_TBTT_ITVL_PORT0_8822C)
+#define BIT_SET_RX_BCN_TBTT_ITVL_PORT0_8822C(x, v) \
+ (BIT_CLEAR_RX_BCN_TBTT_ITVL_PORT0_8822C(x) | \
+ BIT_RX_BCN_TBTT_ITVL_PORT0_8822C(v))
+
+/* 2 REG_RX_BCN_TBTT_ITVL1_8822C */
+
+#define BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8822C 0
+#define BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8822C 0xff
+#define BIT_RX_BCN_TBTT_ITVL_CLIENT3_8822C(x) \
+ (((x) & BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8822C) \
+ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8822C)
+#define BITS_RX_BCN_TBTT_ITVL_CLIENT3_8822C \
+ (BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8822C \
+ << BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8822C)
+#define BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3_8822C(x) \
+ ((x) & (~BITS_RX_BCN_TBTT_ITVL_CLIENT3_8822C))
+#define BIT_GET_RX_BCN_TBTT_ITVL_CLIENT3_8822C(x) \
+ (((x) >> BIT_SHIFT_RX_BCN_TBTT_ITVL_CLIENT3_8822C) & \
+ BIT_MASK_RX_BCN_TBTT_ITVL_CLIENT3_8822C)
+#define BIT_SET_RX_BCN_TBTT_ITVL_CLIENT3_8822C(x, v) \
+ (BIT_CLEAR_RX_BCN_TBTT_ITVL_CLIENT3_8822C(x) | \
+ BIT_RX_BCN_TBTT_ITVL_CLIENT3_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_IO_WRAP_ERR_FLAG_8822C */
+#define BIT_IO_WRAP_ERR_8822C BIT(0)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_SPEED_SENSOR_8822C */
+#define BIT_DSS_1_RST_N_8822C BIT(31)
+#define BIT_DSS_1_SPEED_EN_8822C BIT(30)
+#define BIT_DSS_1_WIRE_SEL_8822C BIT(29)
+#define BIT_DSS_ENCLK_8822C BIT(28)
+
+#define BIT_SHIFT_DSS_1_RO_SEL_8822C 24
+#define BIT_MASK_DSS_1_RO_SEL_8822C 0x7
+#define BIT_DSS_1_RO_SEL_8822C(x) \
+ (((x) & BIT_MASK_DSS_1_RO_SEL_8822C) << BIT_SHIFT_DSS_1_RO_SEL_8822C)
+#define BITS_DSS_1_RO_SEL_8822C \
+ (BIT_MASK_DSS_1_RO_SEL_8822C << BIT_SHIFT_DSS_1_RO_SEL_8822C)
+#define BIT_CLEAR_DSS_1_RO_SEL_8822C(x) ((x) & (~BITS_DSS_1_RO_SEL_8822C))
+#define BIT_GET_DSS_1_RO_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_DSS_1_RO_SEL_8822C) & BIT_MASK_DSS_1_RO_SEL_8822C)
+#define BIT_SET_DSS_1_RO_SEL_8822C(x, v) \
+ (BIT_CLEAR_DSS_1_RO_SEL_8822C(x) | BIT_DSS_1_RO_SEL_8822C(v))
+
+#define BIT_SHIFT_DSS_1_DATA_IN_8822C 0
+#define BIT_MASK_DSS_1_DATA_IN_8822C 0xfffff
+#define BIT_DSS_1_DATA_IN_8822C(x) \
+ (((x) & BIT_MASK_DSS_1_DATA_IN_8822C) << BIT_SHIFT_DSS_1_DATA_IN_8822C)
+#define BITS_DSS_1_DATA_IN_8822C \
+ (BIT_MASK_DSS_1_DATA_IN_8822C << BIT_SHIFT_DSS_1_DATA_IN_8822C)
+#define BIT_CLEAR_DSS_1_DATA_IN_8822C(x) ((x) & (~BITS_DSS_1_DATA_IN_8822C))
+#define BIT_GET_DSS_1_DATA_IN_8822C(x) \
+ (((x) >> BIT_SHIFT_DSS_1_DATA_IN_8822C) & BIT_MASK_DSS_1_DATA_IN_8822C)
+#define BIT_SET_DSS_1_DATA_IN_8822C(x, v) \
+ (BIT_CLEAR_DSS_1_DATA_IN_8822C(x) | BIT_DSS_1_DATA_IN_8822C(v))
+
+/* 2 REG_SPEED_SENSOR1_8822C */
+#define BIT_DSS_1_READY_8822C BIT(31)
+#define BIT_DSS_1_WSORT_GO_8822C BIT(30)
+
+#define BIT_SHIFT_DSS_1_COUNT_OUT_8822C 0
+#define BIT_MASK_DSS_1_COUNT_OUT_8822C 0xfffff
+#define BIT_DSS_1_COUNT_OUT_8822C(x) \
+ (((x) & BIT_MASK_DSS_1_COUNT_OUT_8822C) \
+ << BIT_SHIFT_DSS_1_COUNT_OUT_8822C)
+#define BITS_DSS_1_COUNT_OUT_8822C \
+ (BIT_MASK_DSS_1_COUNT_OUT_8822C << BIT_SHIFT_DSS_1_COUNT_OUT_8822C)
+#define BIT_CLEAR_DSS_1_COUNT_OUT_8822C(x) ((x) & (~BITS_DSS_1_COUNT_OUT_8822C))
+#define BIT_GET_DSS_1_COUNT_OUT_8822C(x) \
+ (((x) >> BIT_SHIFT_DSS_1_COUNT_OUT_8822C) & \
+ BIT_MASK_DSS_1_COUNT_OUT_8822C)
+#define BIT_SET_DSS_1_COUNT_OUT_8822C(x, v) \
+ (BIT_CLEAR_DSS_1_COUNT_OUT_8822C(x) | BIT_DSS_1_COUNT_OUT_8822C(v))
+
+/* 2 REG_SPEED_SENSOR2_8822C */
+#define BIT_DSS_2_RST_N_8822C BIT(31)
+#define BIT_DSS_2_SPEED_EN_8822C BIT(30)
+#define BIT_DSS_2_WIRE_SEL_8822C BIT(29)
+#define BIT_DSS_ENCLK_8822C BIT(28)
+
+#define BIT_SHIFT_DSS_2_RO_SEL_8822C 24
+#define BIT_MASK_DSS_2_RO_SEL_8822C 0x7
+#define BIT_DSS_2_RO_SEL_8822C(x) \
+ (((x) & BIT_MASK_DSS_2_RO_SEL_8822C) << BIT_SHIFT_DSS_2_RO_SEL_8822C)
+#define BITS_DSS_2_RO_SEL_8822C \
+ (BIT_MASK_DSS_2_RO_SEL_8822C << BIT_SHIFT_DSS_2_RO_SEL_8822C)
+#define BIT_CLEAR_DSS_2_RO_SEL_8822C(x) ((x) & (~BITS_DSS_2_RO_SEL_8822C))
+#define BIT_GET_DSS_2_RO_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_DSS_2_RO_SEL_8822C) & BIT_MASK_DSS_2_RO_SEL_8822C)
+#define BIT_SET_DSS_2_RO_SEL_8822C(x, v) \
+ (BIT_CLEAR_DSS_2_RO_SEL_8822C(x) | BIT_DSS_2_RO_SEL_8822C(v))
+
+#define BIT_SHIFT_DSS_2_DATA_IN_8822C 0
+#define BIT_MASK_DSS_2_DATA_IN_8822C 0xfffff
+#define BIT_DSS_2_DATA_IN_8822C(x) \
+ (((x) & BIT_MASK_DSS_2_DATA_IN_8822C) << BIT_SHIFT_DSS_2_DATA_IN_8822C)
+#define BITS_DSS_2_DATA_IN_8822C \
+ (BIT_MASK_DSS_2_DATA_IN_8822C << BIT_SHIFT_DSS_2_DATA_IN_8822C)
+#define BIT_CLEAR_DSS_2_DATA_IN_8822C(x) ((x) & (~BITS_DSS_2_DATA_IN_8822C))
+#define BIT_GET_DSS_2_DATA_IN_8822C(x) \
+ (((x) >> BIT_SHIFT_DSS_2_DATA_IN_8822C) & BIT_MASK_DSS_2_DATA_IN_8822C)
+#define BIT_SET_DSS_2_DATA_IN_8822C(x, v) \
+ (BIT_CLEAR_DSS_2_DATA_IN_8822C(x) | BIT_DSS_2_DATA_IN_8822C(v))
+
+/* 2 REG_SPEED_SENSOR3_8822C */
+#define BIT_DSS_2_READY_8822C BIT(31)
+#define BIT_DSS_2_WSORT_GO_8822C BIT(30)
+
+#define BIT_SHIFT_DSS_2_COUNT_OUT_8822C 0
+#define BIT_MASK_DSS_2_COUNT_OUT_8822C 0xfffff
+#define BIT_DSS_2_COUNT_OUT_8822C(x) \
+ (((x) & BIT_MASK_DSS_2_COUNT_OUT_8822C) \
+ << BIT_SHIFT_DSS_2_COUNT_OUT_8822C)
+#define BITS_DSS_2_COUNT_OUT_8822C \
+ (BIT_MASK_DSS_2_COUNT_OUT_8822C << BIT_SHIFT_DSS_2_COUNT_OUT_8822C)
+#define BIT_CLEAR_DSS_2_COUNT_OUT_8822C(x) ((x) & (~BITS_DSS_2_COUNT_OUT_8822C))
+#define BIT_GET_DSS_2_COUNT_OUT_8822C(x) \
+ (((x) >> BIT_SHIFT_DSS_2_COUNT_OUT_8822C) & \
+ BIT_MASK_DSS_2_COUNT_OUT_8822C)
+#define BIT_SET_DSS_2_COUNT_OUT_8822C(x, v) \
+ (BIT_CLEAR_DSS_2_COUNT_OUT_8822C(x) | BIT_DSS_2_COUNT_OUT_8822C(v))
+
+/* 2 REG_SPEED_SENSOR4_8822C */
+#define BIT_DSS_3_RST_N_8822C BIT(31)
+#define BIT_DSS_3_SPEED_EN_8822C BIT(30)
+#define BIT_DSS_3_WIRE_SEL_8822C BIT(29)
+#define BIT_DSS_ENCLK_8822C BIT(28)
+
+#define BIT_SHIFT_DSS_3_RO_SEL_8822C 24
+#define BIT_MASK_DSS_3_RO_SEL_8822C 0x7
+#define BIT_DSS_3_RO_SEL_8822C(x) \
+ (((x) & BIT_MASK_DSS_3_RO_SEL_8822C) << BIT_SHIFT_DSS_3_RO_SEL_8822C)
+#define BITS_DSS_3_RO_SEL_8822C \
+ (BIT_MASK_DSS_3_RO_SEL_8822C << BIT_SHIFT_DSS_3_RO_SEL_8822C)
+#define BIT_CLEAR_DSS_3_RO_SEL_8822C(x) ((x) & (~BITS_DSS_3_RO_SEL_8822C))
+#define BIT_GET_DSS_3_RO_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_DSS_3_RO_SEL_8822C) & BIT_MASK_DSS_3_RO_SEL_8822C)
+#define BIT_SET_DSS_3_RO_SEL_8822C(x, v) \
+ (BIT_CLEAR_DSS_3_RO_SEL_8822C(x) | BIT_DSS_3_RO_SEL_8822C(v))
+
+#define BIT_SHIFT_DSS_3_DATA_IN_8822C 0
+#define BIT_MASK_DSS_3_DATA_IN_8822C 0xfffff
+#define BIT_DSS_3_DATA_IN_8822C(x) \
+ (((x) & BIT_MASK_DSS_3_DATA_IN_8822C) << BIT_SHIFT_DSS_3_DATA_IN_8822C)
+#define BITS_DSS_3_DATA_IN_8822C \
+ (BIT_MASK_DSS_3_DATA_IN_8822C << BIT_SHIFT_DSS_3_DATA_IN_8822C)
+#define BIT_CLEAR_DSS_3_DATA_IN_8822C(x) ((x) & (~BITS_DSS_3_DATA_IN_8822C))
+#define BIT_GET_DSS_3_DATA_IN_8822C(x) \
+ (((x) >> BIT_SHIFT_DSS_3_DATA_IN_8822C) & BIT_MASK_DSS_3_DATA_IN_8822C)
+#define BIT_SET_DSS_3_DATA_IN_8822C(x, v) \
+ (BIT_CLEAR_DSS_3_DATA_IN_8822C(x) | BIT_DSS_3_DATA_IN_8822C(v))
+
+/* 2 REG_SPEED_SENSOR5_8822C */
+#define BIT_DSS_3_READY_8822C BIT(31)
+#define BIT_DSS_3_WSORT_GO_8822C BIT(30)
+
+#define BIT_SHIFT_DSS_3_COUNT_OUT_8822C 0
+#define BIT_MASK_DSS_3_COUNT_OUT_8822C 0xfffff
+#define BIT_DSS_3_COUNT_OUT_8822C(x) \
+ (((x) & BIT_MASK_DSS_3_COUNT_OUT_8822C) \
+ << BIT_SHIFT_DSS_3_COUNT_OUT_8822C)
+#define BITS_DSS_3_COUNT_OUT_8822C \
+ (BIT_MASK_DSS_3_COUNT_OUT_8822C << BIT_SHIFT_DSS_3_COUNT_OUT_8822C)
+#define BIT_CLEAR_DSS_3_COUNT_OUT_8822C(x) ((x) & (~BITS_DSS_3_COUNT_OUT_8822C))
+#define BIT_GET_DSS_3_COUNT_OUT_8822C(x) \
+ (((x) >> BIT_SHIFT_DSS_3_COUNT_OUT_8822C) & \
+ BIT_MASK_DSS_3_COUNT_OUT_8822C)
+#define BIT_SET_DSS_3_COUNT_OUT_8822C(x, v) \
+ (BIT_CLEAR_DSS_3_COUNT_OUT_8822C(x) | BIT_DSS_3_COUNT_OUT_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_COUNTER_CTRL_8822C */
+
+#define BIT_SHIFT_COUNTER_BASE_8822C 16
+#define BIT_MASK_COUNTER_BASE_8822C 0x1fff
+#define BIT_COUNTER_BASE_8822C(x) \
+ (((x) & BIT_MASK_COUNTER_BASE_8822C) << BIT_SHIFT_COUNTER_BASE_8822C)
+#define BITS_COUNTER_BASE_8822C \
+ (BIT_MASK_COUNTER_BASE_8822C << BIT_SHIFT_COUNTER_BASE_8822C)
+#define BIT_CLEAR_COUNTER_BASE_8822C(x) ((x) & (~BITS_COUNTER_BASE_8822C))
+#define BIT_GET_COUNTER_BASE_8822C(x) \
+ (((x) >> BIT_SHIFT_COUNTER_BASE_8822C) & BIT_MASK_COUNTER_BASE_8822C)
+#define BIT_SET_COUNTER_BASE_8822C(x, v) \
+ (BIT_CLEAR_COUNTER_BASE_8822C(x) | BIT_COUNTER_BASE_8822C(v))
+
+#define BIT_EN_RTS_REQ_8822C BIT(9)
+#define BIT_EN_EDCA_REQ_8822C BIT(8)
+#define BIT_EN_PTCL_REQ_8822C BIT(7)
+#define BIT_EN_SCH_REQ_8822C BIT(6)
+#define BIT_USB_COUNT_EN_8822C BIT(5)
+#define BIT_PCIE_COUNT_EN_8822C BIT(4)
+#define BIT_RQPN_COUNT_EN_8822C BIT(3)
+#define BIT_RDE_COUNT_EN_8822C BIT(2)
+#define BIT_TDE_COUNT_EN_8822C BIT(1)
+#define BIT_DISABLE_COUNTER_8822C BIT(0)
+
+/* 2 REG_COUNTER_THRESHOLD_8822C */
+#define BIT_SEL_ALL_MACID_8822C BIT(31)
+
+#define BIT_SHIFT_COUNTER_MACID_8822C 24
+#define BIT_MASK_COUNTER_MACID_8822C 0x7f
+#define BIT_COUNTER_MACID_8822C(x) \
+ (((x) & BIT_MASK_COUNTER_MACID_8822C) << BIT_SHIFT_COUNTER_MACID_8822C)
+#define BITS_COUNTER_MACID_8822C \
+ (BIT_MASK_COUNTER_MACID_8822C << BIT_SHIFT_COUNTER_MACID_8822C)
+#define BIT_CLEAR_COUNTER_MACID_8822C(x) ((x) & (~BITS_COUNTER_MACID_8822C))
+#define BIT_GET_COUNTER_MACID_8822C(x) \
+ (((x) >> BIT_SHIFT_COUNTER_MACID_8822C) & BIT_MASK_COUNTER_MACID_8822C)
+#define BIT_SET_COUNTER_MACID_8822C(x, v) \
+ (BIT_CLEAR_COUNTER_MACID_8822C(x) | BIT_COUNTER_MACID_8822C(v))
+
+#define BIT_SHIFT_AGG_VALUE2_8822C 16
+#define BIT_MASK_AGG_VALUE2_8822C 0x7f
+#define BIT_AGG_VALUE2_8822C(x) \
+ (((x) & BIT_MASK_AGG_VALUE2_8822C) << BIT_SHIFT_AGG_VALUE2_8822C)
+#define BITS_AGG_VALUE2_8822C \
+ (BIT_MASK_AGG_VALUE2_8822C << BIT_SHIFT_AGG_VALUE2_8822C)
+#define BIT_CLEAR_AGG_VALUE2_8822C(x) ((x) & (~BITS_AGG_VALUE2_8822C))
+#define BIT_GET_AGG_VALUE2_8822C(x) \
+ (((x) >> BIT_SHIFT_AGG_VALUE2_8822C) & BIT_MASK_AGG_VALUE2_8822C)
+#define BIT_SET_AGG_VALUE2_8822C(x, v) \
+ (BIT_CLEAR_AGG_VALUE2_8822C(x) | BIT_AGG_VALUE2_8822C(v))
+
+#define BIT_SHIFT_AGG_VALUE1_8822C 8
+#define BIT_MASK_AGG_VALUE1_8822C 0x7f
+#define BIT_AGG_VALUE1_8822C(x) \
+ (((x) & BIT_MASK_AGG_VALUE1_8822C) << BIT_SHIFT_AGG_VALUE1_8822C)
+#define BITS_AGG_VALUE1_8822C \
+ (BIT_MASK_AGG_VALUE1_8822C << BIT_SHIFT_AGG_VALUE1_8822C)
+#define BIT_CLEAR_AGG_VALUE1_8822C(x) ((x) & (~BITS_AGG_VALUE1_8822C))
+#define BIT_GET_AGG_VALUE1_8822C(x) \
+ (((x) >> BIT_SHIFT_AGG_VALUE1_8822C) & BIT_MASK_AGG_VALUE1_8822C)
+#define BIT_SET_AGG_VALUE1_8822C(x, v) \
+ (BIT_CLEAR_AGG_VALUE1_8822C(x) | BIT_AGG_VALUE1_8822C(v))
+
+#define BIT_SHIFT_AGG_VALUE0_8822C 0
+#define BIT_MASK_AGG_VALUE0_8822C 0x7f
+#define BIT_AGG_VALUE0_8822C(x) \
+ (((x) & BIT_MASK_AGG_VALUE0_8822C) << BIT_SHIFT_AGG_VALUE0_8822C)
+#define BITS_AGG_VALUE0_8822C \
+ (BIT_MASK_AGG_VALUE0_8822C << BIT_SHIFT_AGG_VALUE0_8822C)
+#define BIT_CLEAR_AGG_VALUE0_8822C(x) ((x) & (~BITS_AGG_VALUE0_8822C))
+#define BIT_GET_AGG_VALUE0_8822C(x) \
+ (((x) >> BIT_SHIFT_AGG_VALUE0_8822C) & BIT_MASK_AGG_VALUE0_8822C)
+#define BIT_SET_AGG_VALUE0_8822C(x, v) \
+ (BIT_CLEAR_AGG_VALUE0_8822C(x) | BIT_AGG_VALUE0_8822C(v))
+
+/* 2 REG_COUNTER_SET_8822C */
+
+#define BIT_SHIFT_REQUEST_RESET_8822C 16
+#define BIT_MASK_REQUEST_RESET_8822C 0xffff
+#define BIT_REQUEST_RESET_8822C(x) \
+ (((x) & BIT_MASK_REQUEST_RESET_8822C) << BIT_SHIFT_REQUEST_RESET_8822C)
+#define BITS_REQUEST_RESET_8822C \
+ (BIT_MASK_REQUEST_RESET_8822C << BIT_SHIFT_REQUEST_RESET_8822C)
+#define BIT_CLEAR_REQUEST_RESET_8822C(x) ((x) & (~BITS_REQUEST_RESET_8822C))
+#define BIT_GET_REQUEST_RESET_8822C(x) \
+ (((x) >> BIT_SHIFT_REQUEST_RESET_8822C) & BIT_MASK_REQUEST_RESET_8822C)
+#define BIT_SET_REQUEST_RESET_8822C(x, v) \
+ (BIT_CLEAR_REQUEST_RESET_8822C(x) | BIT_REQUEST_RESET_8822C(v))
+
+#define BIT_SHIFT_REQUEST_START_8822C 0
+#define BIT_MASK_REQUEST_START_8822C 0xffff
+#define BIT_REQUEST_START_8822C(x) \
+ (((x) & BIT_MASK_REQUEST_START_8822C) << BIT_SHIFT_REQUEST_START_8822C)
+#define BITS_REQUEST_START_8822C \
+ (BIT_MASK_REQUEST_START_8822C << BIT_SHIFT_REQUEST_START_8822C)
+#define BIT_CLEAR_REQUEST_START_8822C(x) ((x) & (~BITS_REQUEST_START_8822C))
+#define BIT_GET_REQUEST_START_8822C(x) \
+ (((x) >> BIT_SHIFT_REQUEST_START_8822C) & BIT_MASK_REQUEST_START_8822C)
+#define BIT_SET_REQUEST_START_8822C(x, v) \
+ (BIT_CLEAR_REQUEST_START_8822C(x) | BIT_REQUEST_START_8822C(v))
+
+/* 2 REG_COUNTER_OVERFLOW_8822C */
+
+#define BIT_SHIFT_CNT_OVF_REG_8822C 0
+#define BIT_MASK_CNT_OVF_REG_8822C 0xffff
+#define BIT_CNT_OVF_REG_8822C(x) \
+ (((x) & BIT_MASK_CNT_OVF_REG_8822C) << BIT_SHIFT_CNT_OVF_REG_8822C)
+#define BITS_CNT_OVF_REG_8822C \
+ (BIT_MASK_CNT_OVF_REG_8822C << BIT_SHIFT_CNT_OVF_REG_8822C)
+#define BIT_CLEAR_CNT_OVF_REG_8822C(x) ((x) & (~BITS_CNT_OVF_REG_8822C))
+#define BIT_GET_CNT_OVF_REG_8822C(x) \
+ (((x) >> BIT_SHIFT_CNT_OVF_REG_8822C) & BIT_MASK_CNT_OVF_REG_8822C)
+#define BIT_SET_CNT_OVF_REG_8822C(x, v) \
+ (BIT_CLEAR_CNT_OVF_REG_8822C(x) | BIT_CNT_OVF_REG_8822C(v))
+
+/* 2 REG_TXDMA_LEN_THRESHOLD_8822C */
+
+#define BIT_SHIFT_TDE_LEN_TH1_8822C 16
+#define BIT_MASK_TDE_LEN_TH1_8822C 0xffff
+#define BIT_TDE_LEN_TH1_8822C(x) \
+ (((x) & BIT_MASK_TDE_LEN_TH1_8822C) << BIT_SHIFT_TDE_LEN_TH1_8822C)
+#define BITS_TDE_LEN_TH1_8822C \
+ (BIT_MASK_TDE_LEN_TH1_8822C << BIT_SHIFT_TDE_LEN_TH1_8822C)
+#define BIT_CLEAR_TDE_LEN_TH1_8822C(x) ((x) & (~BITS_TDE_LEN_TH1_8822C))
+#define BIT_GET_TDE_LEN_TH1_8822C(x) \
+ (((x) >> BIT_SHIFT_TDE_LEN_TH1_8822C) & BIT_MASK_TDE_LEN_TH1_8822C)
+#define BIT_SET_TDE_LEN_TH1_8822C(x, v) \
+ (BIT_CLEAR_TDE_LEN_TH1_8822C(x) | BIT_TDE_LEN_TH1_8822C(v))
+
+#define BIT_SHIFT_TDE_LEN_TH0_8822C 0
+#define BIT_MASK_TDE_LEN_TH0_8822C 0xffff
+#define BIT_TDE_LEN_TH0_8822C(x) \
+ (((x) & BIT_MASK_TDE_LEN_TH0_8822C) << BIT_SHIFT_TDE_LEN_TH0_8822C)
+#define BITS_TDE_LEN_TH0_8822C \
+ (BIT_MASK_TDE_LEN_TH0_8822C << BIT_SHIFT_TDE_LEN_TH0_8822C)
+#define BIT_CLEAR_TDE_LEN_TH0_8822C(x) ((x) & (~BITS_TDE_LEN_TH0_8822C))
+#define BIT_GET_TDE_LEN_TH0_8822C(x) \
+ (((x) >> BIT_SHIFT_TDE_LEN_TH0_8822C) & BIT_MASK_TDE_LEN_TH0_8822C)
+#define BIT_SET_TDE_LEN_TH0_8822C(x, v) \
+ (BIT_CLEAR_TDE_LEN_TH0_8822C(x) | BIT_TDE_LEN_TH0_8822C(v))
+
+/* 2 REG_RXDMA_LEN_THRESHOLD_8822C */
+
+#define BIT_SHIFT_RDE_LEN_TH1_8822C 16
+#define BIT_MASK_RDE_LEN_TH1_8822C 0xffff
+#define BIT_RDE_LEN_TH1_8822C(x) \
+ (((x) & BIT_MASK_RDE_LEN_TH1_8822C) << BIT_SHIFT_RDE_LEN_TH1_8822C)
+#define BITS_RDE_LEN_TH1_8822C \
+ (BIT_MASK_RDE_LEN_TH1_8822C << BIT_SHIFT_RDE_LEN_TH1_8822C)
+#define BIT_CLEAR_RDE_LEN_TH1_8822C(x) ((x) & (~BITS_RDE_LEN_TH1_8822C))
+#define BIT_GET_RDE_LEN_TH1_8822C(x) \
+ (((x) >> BIT_SHIFT_RDE_LEN_TH1_8822C) & BIT_MASK_RDE_LEN_TH1_8822C)
+#define BIT_SET_RDE_LEN_TH1_8822C(x, v) \
+ (BIT_CLEAR_RDE_LEN_TH1_8822C(x) | BIT_RDE_LEN_TH1_8822C(v))
+
+#define BIT_SHIFT_RDE_LEN_TH0_8822C 0
+#define BIT_MASK_RDE_LEN_TH0_8822C 0xffff
+#define BIT_RDE_LEN_TH0_8822C(x) \
+ (((x) & BIT_MASK_RDE_LEN_TH0_8822C) << BIT_SHIFT_RDE_LEN_TH0_8822C)
+#define BITS_RDE_LEN_TH0_8822C \
+ (BIT_MASK_RDE_LEN_TH0_8822C << BIT_SHIFT_RDE_LEN_TH0_8822C)
+#define BIT_CLEAR_RDE_LEN_TH0_8822C(x) ((x) & (~BITS_RDE_LEN_TH0_8822C))
+#define BIT_GET_RDE_LEN_TH0_8822C(x) \
+ (((x) >> BIT_SHIFT_RDE_LEN_TH0_8822C) & BIT_MASK_RDE_LEN_TH0_8822C)
+#define BIT_SET_RDE_LEN_TH0_8822C(x, v) \
+ (BIT_CLEAR_RDE_LEN_TH0_8822C(x) | BIT_RDE_LEN_TH0_8822C(v))
+
+/* 2 REG_PCIE_EXEC_TIME_THRESHOLD_8822C */
+
+#define BIT_SHIFT_COUNT_INT_SEL_8822C 16
+#define BIT_MASK_COUNT_INT_SEL_8822C 0x3
+#define BIT_COUNT_INT_SEL_8822C(x) \
+ (((x) & BIT_MASK_COUNT_INT_SEL_8822C) << BIT_SHIFT_COUNT_INT_SEL_8822C)
+#define BITS_COUNT_INT_SEL_8822C \
+ (BIT_MASK_COUNT_INT_SEL_8822C << BIT_SHIFT_COUNT_INT_SEL_8822C)
+#define BIT_CLEAR_COUNT_INT_SEL_8822C(x) ((x) & (~BITS_COUNT_INT_SEL_8822C))
+#define BIT_GET_COUNT_INT_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_COUNT_INT_SEL_8822C) & BIT_MASK_COUNT_INT_SEL_8822C)
+#define BIT_SET_COUNT_INT_SEL_8822C(x, v) \
+ (BIT_CLEAR_COUNT_INT_SEL_8822C(x) | BIT_COUNT_INT_SEL_8822C(v))
+
+#define BIT_SHIFT_EXEC_TIME_TH_8822C 0
+#define BIT_MASK_EXEC_TIME_TH_8822C 0xffff
+#define BIT_EXEC_TIME_TH_8822C(x) \
+ (((x) & BIT_MASK_EXEC_TIME_TH_8822C) << BIT_SHIFT_EXEC_TIME_TH_8822C)
+#define BITS_EXEC_TIME_TH_8822C \
+ (BIT_MASK_EXEC_TIME_TH_8822C << BIT_SHIFT_EXEC_TIME_TH_8822C)
+#define BIT_CLEAR_EXEC_TIME_TH_8822C(x) ((x) & (~BITS_EXEC_TIME_TH_8822C))
+#define BIT_GET_EXEC_TIME_TH_8822C(x) \
+ (((x) >> BIT_SHIFT_EXEC_TIME_TH_8822C) & BIT_MASK_EXEC_TIME_TH_8822C)
+#define BIT_SET_EXEC_TIME_TH_8822C(x, v) \
+ (BIT_CLEAR_EXEC_TIME_TH_8822C(x) | BIT_EXEC_TIME_TH_8822C(v))
+
+/* 2 REG_FT2IMR_8822C */
+#define BIT_FS_CLI3_RX_UAPSDMD1_EN_8822C BIT(31)
+#define BIT_FS_CLI3_RX_UAPSDMD0_EN_8822C BIT(30)
+#define BIT_FS_CLI3_TRIGGER_PKT_EN_8822C BIT(29)
+#define BIT_FS_CLI3_EOSP_INT_EN_8822C BIT(28)
+#define BIT_FS_CLI2_RX_UAPSDMD1_EN_8822C BIT(27)
+#define BIT_FS_CLI2_RX_UAPSDMD0_EN_8822C BIT(26)
+#define BIT_FS_CLI2_TRIGGER_PKT_EN_8822C BIT(25)
+#define BIT_FS_CLI2_EOSP_INT_EN_8822C BIT(24)
+#define BIT_FS_CLI1_RX_UAPSDMD1_EN_8822C BIT(23)
+#define BIT_FS_CLI1_RX_UAPSDMD0_EN_8822C BIT(22)
+#define BIT_FS_CLI1_TRIGGER_PKT_EN_8822C BIT(21)
+#define BIT_FS_CLI1_EOSP_INT_EN_8822C BIT(20)
+#define BIT_FS_CLI0_RX_UAPSDMD1_EN_8822C BIT(19)
+#define BIT_FS_CLI0_RX_UAPSDMD0_EN_8822C BIT(18)
+#define BIT_FS_CLI0_TRIGGER_PKT_EN_8822C BIT(17)
+#define BIT_FS_CLI0_EOSP_INT_EN_8822C BIT(16)
+#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_EN_8822C BIT(9)
+#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_EN_8822C BIT(8)
+#define BIT_FS_CLI3_TX_NULL1_INT_EN_8822C BIT(7)
+#define BIT_FS_CLI3_TX_NULL0_INT_EN_8822C BIT(6)
+#define BIT_FS_CLI2_TX_NULL1_INT_EN_8822C BIT(5)
+#define BIT_FS_CLI2_TX_NULL0_INT_EN_8822C BIT(4)
+#define BIT_FS_CLI1_TX_NULL1_INT_EN_8822C BIT(3)
+#define BIT_FS_CLI1_TX_NULL0_INT_EN_8822C BIT(2)
+#define BIT_FS_CLI0_TX_NULL1_INT_EN_8822C BIT(1)
+#define BIT_FS_CLI0_TX_NULL0_INT_EN_8822C BIT(0)
+
+/* 2 REG_FT2ISR_8822C */
+#define BIT_FS_CLI3_RX_UAPSDMD1_INT_8822C BIT(31)
+#define BIT_FS_CLI3_RX_UAPSDMD0_INT_8822C BIT(30)
+#define BIT_FS_CLI3_TRIGGER_PKT_INT_8822C BIT(29)
+#define BIT_FS_CLI3_EOSP_INT_8822C BIT(28)
+#define BIT_FS_CLI2_RX_UAPSDMD1_INT_8822C BIT(27)
+#define BIT_FS_CLI2_RX_UAPSDMD0_INT_8822C BIT(26)
+#define BIT_FS_CLI2_TRIGGER_PKT_INT_8822C BIT(25)
+#define BIT_FS_CLI2_EOSP_INT_8822C BIT(24)
+#define BIT_FS_CLI1_RX_UAPSDMD1_INT_8822C BIT(23)
+#define BIT_FS_CLI1_RX_UAPSDMD0_INT_8822C BIT(22)
+#define BIT_FS_CLI1_TRIGGER_PKT_INT_8822C BIT(21)
+#define BIT_FS_CLI1_EOSP_INT_8822C BIT(20)
+#define BIT_FS_CLI0_RX_UAPSDMD1_INT_8822C BIT(19)
+#define BIT_FS_CLI0_RX_UAPSDMD0_INT_8822C BIT(18)
+#define BIT_FS_CLI0_TRIGGER_PKT_INT_8822C BIT(17)
+#define BIT_FS_CLI0_EOSP_INT_8822C BIT(16)
+#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_INT_8822C BIT(9)
+#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_INT_8822C BIT(8)
+#define BIT_FS_CLI3_TX_NULL1_INT_8822C BIT(7)
+#define BIT_FS_CLI3_TX_NULL0_INT_8822C BIT(6)
+#define BIT_FS_CLI2_TX_NULL1_INT_8822C BIT(5)
+#define BIT_FS_CLI2_TX_NULL0_INT_8822C BIT(4)
+#define BIT_FS_CLI1_TX_NULL1_INT_8822C BIT(3)
+#define BIT_FS_CLI1_TX_NULL0_INT_8822C BIT(2)
+#define BIT_FS_CLI0_TX_NULL1_INT_8822C BIT(1)
+#define BIT_FS_CLI0_TX_NULL0_INT_8822C BIT(0)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_MSG2_8822C */
+
+#define BIT_SHIFT_FW_MSG2_8822C 0
+#define BIT_MASK_FW_MSG2_8822C 0xffffffffL
+#define BIT_FW_MSG2_8822C(x) \
+ (((x) & BIT_MASK_FW_MSG2_8822C) << BIT_SHIFT_FW_MSG2_8822C)
+#define BITS_FW_MSG2_8822C (BIT_MASK_FW_MSG2_8822C << BIT_SHIFT_FW_MSG2_8822C)
+#define BIT_CLEAR_FW_MSG2_8822C(x) ((x) & (~BITS_FW_MSG2_8822C))
+#define BIT_GET_FW_MSG2_8822C(x) \
+ (((x) >> BIT_SHIFT_FW_MSG2_8822C) & BIT_MASK_FW_MSG2_8822C)
+#define BIT_SET_FW_MSG2_8822C(x, v) \
+ (BIT_CLEAR_FW_MSG2_8822C(x) | BIT_FW_MSG2_8822C(v))
+
+/* 2 REG_MSG3_8822C */
+
+#define BIT_SHIFT_FW_MSG3_8822C 0
+#define BIT_MASK_FW_MSG3_8822C 0xffffffffL
+#define BIT_FW_MSG3_8822C(x) \
+ (((x) & BIT_MASK_FW_MSG3_8822C) << BIT_SHIFT_FW_MSG3_8822C)
+#define BITS_FW_MSG3_8822C (BIT_MASK_FW_MSG3_8822C << BIT_SHIFT_FW_MSG3_8822C)
+#define BIT_CLEAR_FW_MSG3_8822C(x) ((x) & (~BITS_FW_MSG3_8822C))
+#define BIT_GET_FW_MSG3_8822C(x) \
+ (((x) >> BIT_SHIFT_FW_MSG3_8822C) & BIT_MASK_FW_MSG3_8822C)
+#define BIT_SET_FW_MSG3_8822C(x, v) \
+ (BIT_CLEAR_FW_MSG3_8822C(x) | BIT_FW_MSG3_8822C(v))
+
+/* 2 REG_MSG4_8822C */
+
+#define BIT_SHIFT_FW_MSG4_8822C 0
+#define BIT_MASK_FW_MSG4_8822C 0xffffffffL
+#define BIT_FW_MSG4_8822C(x) \
+ (((x) & BIT_MASK_FW_MSG4_8822C) << BIT_SHIFT_FW_MSG4_8822C)
+#define BITS_FW_MSG4_8822C (BIT_MASK_FW_MSG4_8822C << BIT_SHIFT_FW_MSG4_8822C)
+#define BIT_CLEAR_FW_MSG4_8822C(x) ((x) & (~BITS_FW_MSG4_8822C))
+#define BIT_GET_FW_MSG4_8822C(x) \
+ (((x) >> BIT_SHIFT_FW_MSG4_8822C) & BIT_MASK_FW_MSG4_8822C)
+#define BIT_SET_FW_MSG4_8822C(x, v) \
+ (BIT_CLEAR_FW_MSG4_8822C(x) | BIT_FW_MSG4_8822C(v))
+
+/* 2 REG_MSG5_8822C */
+
+#define BIT_SHIFT_FW_MSG5_8822C 0
+#define BIT_MASK_FW_MSG5_8822C 0xffffffffL
+#define BIT_FW_MSG5_8822C(x) \
+ (((x) & BIT_MASK_FW_MSG5_8822C) << BIT_SHIFT_FW_MSG5_8822C)
+#define BITS_FW_MSG5_8822C (BIT_MASK_FW_MSG5_8822C << BIT_SHIFT_FW_MSG5_8822C)
+#define BIT_CLEAR_FW_MSG5_8822C(x) ((x) & (~BITS_FW_MSG5_8822C))
+#define BIT_GET_FW_MSG5_8822C(x) \
+ (((x) >> BIT_SHIFT_FW_MSG5_8822C) & BIT_MASK_FW_MSG5_8822C)
+#define BIT_SET_FW_MSG5_8822C(x, v) \
+ (BIT_CLEAR_FW_MSG5_8822C(x) | BIT_FW_MSG5_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_FIFOPAGE_CTRL_1_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822C 16
+#define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822C 0xff
+#define BIT_TX_OQT_HE_FREE_SPACE_V1_8822C(x) \
+ (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822C) \
+ << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822C)
+#define BITS_TX_OQT_HE_FREE_SPACE_V1_8822C \
+ (BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822C \
+ << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822C)
+#define BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8822C(x) \
+ ((x) & (~BITS_TX_OQT_HE_FREE_SPACE_V1_8822C))
+#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8822C) & \
+ BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8822C)
+#define BIT_SET_TX_OQT_HE_FREE_SPACE_V1_8822C(x, v) \
+ (BIT_CLEAR_TX_OQT_HE_FREE_SPACE_V1_8822C(x) | \
+ BIT_TX_OQT_HE_FREE_SPACE_V1_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822C 0
+#define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822C 0xff
+#define BIT_TX_OQT_NL_FREE_SPACE_V1_8822C(x) \
+ (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822C) \
+ << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822C)
+#define BITS_TX_OQT_NL_FREE_SPACE_V1_8822C \
+ (BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822C \
+ << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822C)
+#define BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8822C(x) \
+ ((x) & (~BITS_TX_OQT_NL_FREE_SPACE_V1_8822C))
+#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8822C) & \
+ BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8822C)
+#define BIT_SET_TX_OQT_NL_FREE_SPACE_V1_8822C(x, v) \
+ (BIT_CLEAR_TX_OQT_NL_FREE_SPACE_V1_8822C(x) | \
+ BIT_TX_OQT_NL_FREE_SPACE_V1_8822C(v))
+
+/* 2 REG_FIFOPAGE_CTRL_2_8822C */
+#define BIT_BCN_VALID_1_V1_8822C BIT(31)
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_BCN_HEAD_1_V1_8822C 16
+#define BIT_MASK_BCN_HEAD_1_V1_8822C 0xfff
+#define BIT_BCN_HEAD_1_V1_8822C(x) \
+ (((x) & BIT_MASK_BCN_HEAD_1_V1_8822C) << BIT_SHIFT_BCN_HEAD_1_V1_8822C)
+#define BITS_BCN_HEAD_1_V1_8822C \
+ (BIT_MASK_BCN_HEAD_1_V1_8822C << BIT_SHIFT_BCN_HEAD_1_V1_8822C)
+#define BIT_CLEAR_BCN_HEAD_1_V1_8822C(x) ((x) & (~BITS_BCN_HEAD_1_V1_8822C))
+#define BIT_GET_BCN_HEAD_1_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_BCN_HEAD_1_V1_8822C) & BIT_MASK_BCN_HEAD_1_V1_8822C)
+#define BIT_SET_BCN_HEAD_1_V1_8822C(x, v) \
+ (BIT_CLEAR_BCN_HEAD_1_V1_8822C(x) | BIT_BCN_HEAD_1_V1_8822C(v))
+
+#define BIT_BCN_VALID_V1_8822C BIT(15)
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_BCN_HEAD_V1_8822C 0
+#define BIT_MASK_BCN_HEAD_V1_8822C 0xfff
+#define BIT_BCN_HEAD_V1_8822C(x) \
+ (((x) & BIT_MASK_BCN_HEAD_V1_8822C) << BIT_SHIFT_BCN_HEAD_V1_8822C)
+#define BITS_BCN_HEAD_V1_8822C \
+ (BIT_MASK_BCN_HEAD_V1_8822C << BIT_SHIFT_BCN_HEAD_V1_8822C)
+#define BIT_CLEAR_BCN_HEAD_V1_8822C(x) ((x) & (~BITS_BCN_HEAD_V1_8822C))
+#define BIT_GET_BCN_HEAD_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_BCN_HEAD_V1_8822C) & BIT_MASK_BCN_HEAD_V1_8822C)
+#define BIT_SET_BCN_HEAD_V1_8822C(x, v) \
+ (BIT_CLEAR_BCN_HEAD_V1_8822C(x) | BIT_BCN_HEAD_V1_8822C(v))
+
+/* 2 REG_AUTO_LLT_V1_8822C */
+
+#define BIT_SHIFT_MAX_TX_PKT_V1_8822C 24
+#define BIT_MASK_MAX_TX_PKT_V1_8822C 0xff
+#define BIT_MAX_TX_PKT_V1_8822C(x) \
+ (((x) & BIT_MASK_MAX_TX_PKT_V1_8822C) << BIT_SHIFT_MAX_TX_PKT_V1_8822C)
+#define BITS_MAX_TX_PKT_V1_8822C \
+ (BIT_MASK_MAX_TX_PKT_V1_8822C << BIT_SHIFT_MAX_TX_PKT_V1_8822C)
+#define BIT_CLEAR_MAX_TX_PKT_V1_8822C(x) ((x) & (~BITS_MAX_TX_PKT_V1_8822C))
+#define BIT_GET_MAX_TX_PKT_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_MAX_TX_PKT_V1_8822C) & BIT_MASK_MAX_TX_PKT_V1_8822C)
+#define BIT_SET_MAX_TX_PKT_V1_8822C(x, v) \
+ (BIT_CLEAR_MAX_TX_PKT_V1_8822C(x) | BIT_MAX_TX_PKT_V1_8822C(v))
+
+#define BIT_TDE_ERROR_STOP_V1_8822C BIT(23)
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_LLT_FREE_PAGE_V2_8822C 8
+#define BIT_MASK_LLT_FREE_PAGE_V2_8822C 0xfff
+#define BIT_LLT_FREE_PAGE_V2_8822C(x) \
+ (((x) & BIT_MASK_LLT_FREE_PAGE_V2_8822C) \
+ << BIT_SHIFT_LLT_FREE_PAGE_V2_8822C)
+#define BITS_LLT_FREE_PAGE_V2_8822C \
+ (BIT_MASK_LLT_FREE_PAGE_V2_8822C << BIT_SHIFT_LLT_FREE_PAGE_V2_8822C)
+#define BIT_CLEAR_LLT_FREE_PAGE_V2_8822C(x) \
+ ((x) & (~BITS_LLT_FREE_PAGE_V2_8822C))
+#define BIT_GET_LLT_FREE_PAGE_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V2_8822C) & \
+ BIT_MASK_LLT_FREE_PAGE_V2_8822C)
+#define BIT_SET_LLT_FREE_PAGE_V2_8822C(x, v) \
+ (BIT_CLEAR_LLT_FREE_PAGE_V2_8822C(x) | BIT_LLT_FREE_PAGE_V2_8822C(v))
+
+#define BIT_SHIFT_BLK_DESC_NUM_8822C 4
+#define BIT_MASK_BLK_DESC_NUM_8822C 0xf
+#define BIT_BLK_DESC_NUM_8822C(x) \
+ (((x) & BIT_MASK_BLK_DESC_NUM_8822C) << BIT_SHIFT_BLK_DESC_NUM_8822C)
+#define BITS_BLK_DESC_NUM_8822C \
+ (BIT_MASK_BLK_DESC_NUM_8822C << BIT_SHIFT_BLK_DESC_NUM_8822C)
+#define BIT_CLEAR_BLK_DESC_NUM_8822C(x) ((x) & (~BITS_BLK_DESC_NUM_8822C))
+#define BIT_GET_BLK_DESC_NUM_8822C(x) \
+ (((x) >> BIT_SHIFT_BLK_DESC_NUM_8822C) & BIT_MASK_BLK_DESC_NUM_8822C)
+#define BIT_SET_BLK_DESC_NUM_8822C(x, v) \
+ (BIT_CLEAR_BLK_DESC_NUM_8822C(x) | BIT_BLK_DESC_NUM_8822C(v))
+
+#define BIT_R_BCN_HEAD_SEL_8822C BIT(3)
+#define BIT_R_EN_BCN_SW_HEAD_SEL_8822C BIT(2)
+#define BIT_LLT_DBG_SEL_8822C BIT(1)
+#define BIT_AUTO_INIT_LLT_V1_8822C BIT(0)
+
+/* 2 REG_TXDMA_OFFSET_CHK_8822C */
+#define BIT_EM_CHKSUM_FIN_8822C BIT(31)
+#define BIT_EMN_PCIE_DMA_MOD_8822C BIT(30)
+#define BIT_EN_TXQUE_CLR_8822C BIT(29)
+#define BIT_EN_PCIE_FIFO_MODE_8822C BIT(28)
+
+#define BIT_SHIFT_PG_UNDER_TH_V1_8822C 16
+#define BIT_MASK_PG_UNDER_TH_V1_8822C 0xfff
+#define BIT_PG_UNDER_TH_V1_8822C(x) \
+ (((x) & BIT_MASK_PG_UNDER_TH_V1_8822C) \
+ << BIT_SHIFT_PG_UNDER_TH_V1_8822C)
+#define BITS_PG_UNDER_TH_V1_8822C \
+ (BIT_MASK_PG_UNDER_TH_V1_8822C << BIT_SHIFT_PG_UNDER_TH_V1_8822C)
+#define BIT_CLEAR_PG_UNDER_TH_V1_8822C(x) ((x) & (~BITS_PG_UNDER_TH_V1_8822C))
+#define BIT_GET_PG_UNDER_TH_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8822C) & \
+ BIT_MASK_PG_UNDER_TH_V1_8822C)
+#define BIT_SET_PG_UNDER_TH_V1_8822C(x, v) \
+ (BIT_CLEAR_PG_UNDER_TH_V1_8822C(x) | BIT_PG_UNDER_TH_V1_8822C(v))
+
+#define BIT_R_EN_RESET_RESTORE_H2C_8822C BIT(15)
+#define BIT_SDIO_TDE_FINISH_8822C BIT(14)
+#define BIT_SDIO_TXDESC_CHKSUM_EN_8822C BIT(13)
+#define BIT_RST_RDPTR_8822C BIT(12)
+#define BIT_RST_WRPTR_8822C BIT(11)
+#define BIT_CHK_PG_TH_EN_8822C BIT(10)
+#define BIT_DROP_DATA_EN_8822C BIT(9)
+#define BIT_CHECK_OFFSET_EN_8822C BIT(8)
+
+#define BIT_SHIFT_CHECK_OFFSET_8822C 0
+#define BIT_MASK_CHECK_OFFSET_8822C 0xff
+#define BIT_CHECK_OFFSET_8822C(x) \
+ (((x) & BIT_MASK_CHECK_OFFSET_8822C) << BIT_SHIFT_CHECK_OFFSET_8822C)
+#define BITS_CHECK_OFFSET_8822C \
+ (BIT_MASK_CHECK_OFFSET_8822C << BIT_SHIFT_CHECK_OFFSET_8822C)
+#define BIT_CLEAR_CHECK_OFFSET_8822C(x) ((x) & (~BITS_CHECK_OFFSET_8822C))
+#define BIT_GET_CHECK_OFFSET_8822C(x) \
+ (((x) >> BIT_SHIFT_CHECK_OFFSET_8822C) & BIT_MASK_CHECK_OFFSET_8822C)
+#define BIT_SET_CHECK_OFFSET_8822C(x, v) \
+ (BIT_CLEAR_CHECK_OFFSET_8822C(x) | BIT_CHECK_OFFSET_8822C(v))
+
+/* 2 REG_TXDMA_STATUS_8822C */
+#define BIT_TXPKTBUF_REQ_ERR_8822C BIT(18)
+#define BIT_HI_OQT_UDN_8822C BIT(17)
+#define BIT_HI_OQT_OVF_8822C BIT(16)
+#define BIT_PAYLOAD_CHKSUM_ERR_8822C BIT(15)
+#define BIT_PAYLOAD_UDN_8822C BIT(14)
+#define BIT_PAYLOAD_OVF_8822C BIT(13)
+#define BIT_DSC_CHKSUM_FAIL_8822C BIT(12)
+#define BIT_UNKNOWN_QSEL_8822C BIT(11)
+#define BIT_EP_QSEL_DIFF_8822C BIT(10)
+#define BIT_TX_OFFS_UNMATCH_8822C BIT(9)
+#define BIT_TXOQT_UDN_8822C BIT(8)
+#define BIT_TXOQT_OVF_8822C BIT(7)
+#define BIT_TXDMA_SFF_UDN_8822C BIT(6)
+#define BIT_TXDMA_SFF_OVF_8822C BIT(5)
+#define BIT_LLT_NULL_PG_8822C BIT(4)
+#define BIT_PAGE_UDN_8822C BIT(3)
+#define BIT_PAGE_OVF_8822C BIT(2)
+#define BIT_TXFF_PG_UDN_8822C BIT(1)
+#define BIT_TXFF_PG_OVF_8822C BIT(0)
+
+/* 2 REG_TX_DMA_DBG_8822C */
+
+/* 2 REG_TQPNT1_8822C */
+#define BIT_HPQ_INT_EN_8822C BIT(31)
+
+#define BIT_SHIFT_HPQ_HIGH_TH_V1_8822C 16
+#define BIT_MASK_HPQ_HIGH_TH_V1_8822C 0xfff
+#define BIT_HPQ_HIGH_TH_V1_8822C(x) \
+ (((x) & BIT_MASK_HPQ_HIGH_TH_V1_8822C) \
+ << BIT_SHIFT_HPQ_HIGH_TH_V1_8822C)
+#define BITS_HPQ_HIGH_TH_V1_8822C \
+ (BIT_MASK_HPQ_HIGH_TH_V1_8822C << BIT_SHIFT_HPQ_HIGH_TH_V1_8822C)
+#define BIT_CLEAR_HPQ_HIGH_TH_V1_8822C(x) ((x) & (~BITS_HPQ_HIGH_TH_V1_8822C))
+#define BIT_GET_HPQ_HIGH_TH_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1_8822C) & \
+ BIT_MASK_HPQ_HIGH_TH_V1_8822C)
+#define BIT_SET_HPQ_HIGH_TH_V1_8822C(x, v) \
+ (BIT_CLEAR_HPQ_HIGH_TH_V1_8822C(x) | BIT_HPQ_HIGH_TH_V1_8822C(v))
+
+#define BIT_SHIFT_HPQ_LOW_TH_V1_8822C 0
+#define BIT_MASK_HPQ_LOW_TH_V1_8822C 0xfff
+#define BIT_HPQ_LOW_TH_V1_8822C(x) \
+ (((x) & BIT_MASK_HPQ_LOW_TH_V1_8822C) << BIT_SHIFT_HPQ_LOW_TH_V1_8822C)
+#define BITS_HPQ_LOW_TH_V1_8822C \
+ (BIT_MASK_HPQ_LOW_TH_V1_8822C << BIT_SHIFT_HPQ_LOW_TH_V1_8822C)
+#define BIT_CLEAR_HPQ_LOW_TH_V1_8822C(x) ((x) & (~BITS_HPQ_LOW_TH_V1_8822C))
+#define BIT_GET_HPQ_LOW_TH_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_HPQ_LOW_TH_V1_8822C) & BIT_MASK_HPQ_LOW_TH_V1_8822C)
+#define BIT_SET_HPQ_LOW_TH_V1_8822C(x, v) \
+ (BIT_CLEAR_HPQ_LOW_TH_V1_8822C(x) | BIT_HPQ_LOW_TH_V1_8822C(v))
+
+/* 2 REG_TQPNT2_8822C */
+#define BIT_NPQ_INT_EN_8822C BIT(31)
+
+#define BIT_SHIFT_NPQ_HIGH_TH_V1_8822C 16
+#define BIT_MASK_NPQ_HIGH_TH_V1_8822C 0xfff
+#define BIT_NPQ_HIGH_TH_V1_8822C(x) \
+ (((x) & BIT_MASK_NPQ_HIGH_TH_V1_8822C) \
+ << BIT_SHIFT_NPQ_HIGH_TH_V1_8822C)
+#define BITS_NPQ_HIGH_TH_V1_8822C \
+ (BIT_MASK_NPQ_HIGH_TH_V1_8822C << BIT_SHIFT_NPQ_HIGH_TH_V1_8822C)
+#define BIT_CLEAR_NPQ_HIGH_TH_V1_8822C(x) ((x) & (~BITS_NPQ_HIGH_TH_V1_8822C))
+#define BIT_GET_NPQ_HIGH_TH_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1_8822C) & \
+ BIT_MASK_NPQ_HIGH_TH_V1_8822C)
+#define BIT_SET_NPQ_HIGH_TH_V1_8822C(x, v) \
+ (BIT_CLEAR_NPQ_HIGH_TH_V1_8822C(x) | BIT_NPQ_HIGH_TH_V1_8822C(v))
+
+#define BIT_SHIFT_NPQ_LOW_TH_V1_8822C 0
+#define BIT_MASK_NPQ_LOW_TH_V1_8822C 0xfff
+#define BIT_NPQ_LOW_TH_V1_8822C(x) \
+ (((x) & BIT_MASK_NPQ_LOW_TH_V1_8822C) << BIT_SHIFT_NPQ_LOW_TH_V1_8822C)
+#define BITS_NPQ_LOW_TH_V1_8822C \
+ (BIT_MASK_NPQ_LOW_TH_V1_8822C << BIT_SHIFT_NPQ_LOW_TH_V1_8822C)
+#define BIT_CLEAR_NPQ_LOW_TH_V1_8822C(x) ((x) & (~BITS_NPQ_LOW_TH_V1_8822C))
+#define BIT_GET_NPQ_LOW_TH_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_NPQ_LOW_TH_V1_8822C) & BIT_MASK_NPQ_LOW_TH_V1_8822C)
+#define BIT_SET_NPQ_LOW_TH_V1_8822C(x, v) \
+ (BIT_CLEAR_NPQ_LOW_TH_V1_8822C(x) | BIT_NPQ_LOW_TH_V1_8822C(v))
+
+/* 2 REG_TQPNT3_8822C */
+#define BIT_LPQ_INT_EN_8822C BIT(31)
+
+#define BIT_SHIFT_LPQ_HIGH_TH_V1_8822C 16
+#define BIT_MASK_LPQ_HIGH_TH_V1_8822C 0xfff
+#define BIT_LPQ_HIGH_TH_V1_8822C(x) \
+ (((x) & BIT_MASK_LPQ_HIGH_TH_V1_8822C) \
+ << BIT_SHIFT_LPQ_HIGH_TH_V1_8822C)
+#define BITS_LPQ_HIGH_TH_V1_8822C \
+ (BIT_MASK_LPQ_HIGH_TH_V1_8822C << BIT_SHIFT_LPQ_HIGH_TH_V1_8822C)
+#define BIT_CLEAR_LPQ_HIGH_TH_V1_8822C(x) ((x) & (~BITS_LPQ_HIGH_TH_V1_8822C))
+#define BIT_GET_LPQ_HIGH_TH_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1_8822C) & \
+ BIT_MASK_LPQ_HIGH_TH_V1_8822C)
+#define BIT_SET_LPQ_HIGH_TH_V1_8822C(x, v) \
+ (BIT_CLEAR_LPQ_HIGH_TH_V1_8822C(x) | BIT_LPQ_HIGH_TH_V1_8822C(v))
+
+#define BIT_SHIFT_LPQ_LOW_TH_V1_8822C 0
+#define BIT_MASK_LPQ_LOW_TH_V1_8822C 0xfff
+#define BIT_LPQ_LOW_TH_V1_8822C(x) \
+ (((x) & BIT_MASK_LPQ_LOW_TH_V1_8822C) << BIT_SHIFT_LPQ_LOW_TH_V1_8822C)
+#define BITS_LPQ_LOW_TH_V1_8822C \
+ (BIT_MASK_LPQ_LOW_TH_V1_8822C << BIT_SHIFT_LPQ_LOW_TH_V1_8822C)
+#define BIT_CLEAR_LPQ_LOW_TH_V1_8822C(x) ((x) & (~BITS_LPQ_LOW_TH_V1_8822C))
+#define BIT_GET_LPQ_LOW_TH_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_LPQ_LOW_TH_V1_8822C) & BIT_MASK_LPQ_LOW_TH_V1_8822C)
+#define BIT_SET_LPQ_LOW_TH_V1_8822C(x, v) \
+ (BIT_CLEAR_LPQ_LOW_TH_V1_8822C(x) | BIT_LPQ_LOW_TH_V1_8822C(v))
+
+/* 2 REG_TQPNT4_8822C */
+#define BIT_EXQ_INT_EN_8822C BIT(31)
+
+#define BIT_SHIFT_EXQ_HIGH_TH_V1_8822C 16
+#define BIT_MASK_EXQ_HIGH_TH_V1_8822C 0xfff
+#define BIT_EXQ_HIGH_TH_V1_8822C(x) \
+ (((x) & BIT_MASK_EXQ_HIGH_TH_V1_8822C) \
+ << BIT_SHIFT_EXQ_HIGH_TH_V1_8822C)
+#define BITS_EXQ_HIGH_TH_V1_8822C \
+ (BIT_MASK_EXQ_HIGH_TH_V1_8822C << BIT_SHIFT_EXQ_HIGH_TH_V1_8822C)
+#define BIT_CLEAR_EXQ_HIGH_TH_V1_8822C(x) ((x) & (~BITS_EXQ_HIGH_TH_V1_8822C))
+#define BIT_GET_EXQ_HIGH_TH_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1_8822C) & \
+ BIT_MASK_EXQ_HIGH_TH_V1_8822C)
+#define BIT_SET_EXQ_HIGH_TH_V1_8822C(x, v) \
+ (BIT_CLEAR_EXQ_HIGH_TH_V1_8822C(x) | BIT_EXQ_HIGH_TH_V1_8822C(v))
+
+#define BIT_SHIFT_EXQ_LOW_TH_V1_8822C 0
+#define BIT_MASK_EXQ_LOW_TH_V1_8822C 0xfff
+#define BIT_EXQ_LOW_TH_V1_8822C(x) \
+ (((x) & BIT_MASK_EXQ_LOW_TH_V1_8822C) << BIT_SHIFT_EXQ_LOW_TH_V1_8822C)
+#define BITS_EXQ_LOW_TH_V1_8822C \
+ (BIT_MASK_EXQ_LOW_TH_V1_8822C << BIT_SHIFT_EXQ_LOW_TH_V1_8822C)
+#define BIT_CLEAR_EXQ_LOW_TH_V1_8822C(x) ((x) & (~BITS_EXQ_LOW_TH_V1_8822C))
+#define BIT_GET_EXQ_LOW_TH_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_EXQ_LOW_TH_V1_8822C) & BIT_MASK_EXQ_LOW_TH_V1_8822C)
+#define BIT_SET_EXQ_LOW_TH_V1_8822C(x, v) \
+ (BIT_CLEAR_EXQ_LOW_TH_V1_8822C(x) | BIT_EXQ_LOW_TH_V1_8822C(v))
+
+/* 2 REG_RQPN_CTRL_1_8822C */
+
+#define BIT_SHIFT_TXPKTNUM_H_V2_8822C 16
+#define BIT_MASK_TXPKTNUM_H_V2_8822C 0xfff
+#define BIT_TXPKTNUM_H_V2_8822C(x) \
+ (((x) & BIT_MASK_TXPKTNUM_H_V2_8822C) << BIT_SHIFT_TXPKTNUM_H_V2_8822C)
+#define BITS_TXPKTNUM_H_V2_8822C \
+ (BIT_MASK_TXPKTNUM_H_V2_8822C << BIT_SHIFT_TXPKTNUM_H_V2_8822C)
+#define BIT_CLEAR_TXPKTNUM_H_V2_8822C(x) ((x) & (~BITS_TXPKTNUM_H_V2_8822C))
+#define BIT_GET_TXPKTNUM_H_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_TXPKTNUM_H_V2_8822C) & BIT_MASK_TXPKTNUM_H_V2_8822C)
+#define BIT_SET_TXPKTNUM_H_V2_8822C(x, v) \
+ (BIT_CLEAR_TXPKTNUM_H_V2_8822C(x) | BIT_TXPKTNUM_H_V2_8822C(v))
+
+#define BIT_SHIFT_TXPKTNUM_V3_8822C 0
+#define BIT_MASK_TXPKTNUM_V3_8822C 0xfff
+#define BIT_TXPKTNUM_V3_8822C(x) \
+ (((x) & BIT_MASK_TXPKTNUM_V3_8822C) << BIT_SHIFT_TXPKTNUM_V3_8822C)
+#define BITS_TXPKTNUM_V3_8822C \
+ (BIT_MASK_TXPKTNUM_V3_8822C << BIT_SHIFT_TXPKTNUM_V3_8822C)
+#define BIT_CLEAR_TXPKTNUM_V3_8822C(x) ((x) & (~BITS_TXPKTNUM_V3_8822C))
+#define BIT_GET_TXPKTNUM_V3_8822C(x) \
+ (((x) >> BIT_SHIFT_TXPKTNUM_V3_8822C) & BIT_MASK_TXPKTNUM_V3_8822C)
+#define BIT_SET_TXPKTNUM_V3_8822C(x, v) \
+ (BIT_CLEAR_TXPKTNUM_V3_8822C(x) | BIT_TXPKTNUM_V3_8822C(v))
+
+/* 2 REG_RQPN_CTRL_2_8822C */
+#define BIT_LD_RQPN_8822C BIT(31)
+#define BIT_EXQ_PUBLIC_DIS_V1_8822C BIT(19)
+#define BIT_NPQ_PUBLIC_DIS_V1_8822C BIT(18)
+#define BIT_LPQ_PUBLIC_DIS_V1_8822C BIT(17)
+#define BIT_HPQ_PUBLIC_DIS_V1_8822C BIT(16)
+#define BIT_SDIO_TXAGG_ALIGN_ADJUST_EN_8822C BIT(15)
+
+#define BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8822C 0
+#define BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8822C 0xfff
+#define BIT_SDIO_TXAGG_ALIGN_SIZE_8822C(x) \
+ (((x) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8822C) \
+ << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8822C)
+#define BITS_SDIO_TXAGG_ALIGN_SIZE_8822C \
+ (BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8822C \
+ << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8822C)
+#define BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_8822C(x) \
+ ((x) & (~BITS_SDIO_TXAGG_ALIGN_SIZE_8822C))
+#define BIT_GET_SDIO_TXAGG_ALIGN_SIZE_8822C(x) \
+ (((x) >> BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8822C) & \
+ BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8822C)
+#define BIT_SET_SDIO_TXAGG_ALIGN_SIZE_8822C(x, v) \
+ (BIT_CLEAR_SDIO_TXAGG_ALIGN_SIZE_8822C(x) | \
+ BIT_SDIO_TXAGG_ALIGN_SIZE_8822C(v))
+
+/* 2 REG_FIFOPAGE_INFO_1_8822C */
+
+#define BIT_SHIFT_HPQ_AVAL_PG_V1_8822C 16
+#define BIT_MASK_HPQ_AVAL_PG_V1_8822C 0xfff
+#define BIT_HPQ_AVAL_PG_V1_8822C(x) \
+ (((x) & BIT_MASK_HPQ_AVAL_PG_V1_8822C) \
+ << BIT_SHIFT_HPQ_AVAL_PG_V1_8822C)
+#define BITS_HPQ_AVAL_PG_V1_8822C \
+ (BIT_MASK_HPQ_AVAL_PG_V1_8822C << BIT_SHIFT_HPQ_AVAL_PG_V1_8822C)
+#define BIT_CLEAR_HPQ_AVAL_PG_V1_8822C(x) ((x) & (~BITS_HPQ_AVAL_PG_V1_8822C))
+#define BIT_GET_HPQ_AVAL_PG_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1_8822C) & \
+ BIT_MASK_HPQ_AVAL_PG_V1_8822C)
+#define BIT_SET_HPQ_AVAL_PG_V1_8822C(x, v) \
+ (BIT_CLEAR_HPQ_AVAL_PG_V1_8822C(x) | BIT_HPQ_AVAL_PG_V1_8822C(v))
+
+#define BIT_SHIFT_HPQ_V1_8822C 0
+#define BIT_MASK_HPQ_V1_8822C 0xfff
+#define BIT_HPQ_V1_8822C(x) \
+ (((x) & BIT_MASK_HPQ_V1_8822C) << BIT_SHIFT_HPQ_V1_8822C)
+#define BITS_HPQ_V1_8822C (BIT_MASK_HPQ_V1_8822C << BIT_SHIFT_HPQ_V1_8822C)
+#define BIT_CLEAR_HPQ_V1_8822C(x) ((x) & (~BITS_HPQ_V1_8822C))
+#define BIT_GET_HPQ_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_HPQ_V1_8822C) & BIT_MASK_HPQ_V1_8822C)
+#define BIT_SET_HPQ_V1_8822C(x, v) \
+ (BIT_CLEAR_HPQ_V1_8822C(x) | BIT_HPQ_V1_8822C(v))
+
+/* 2 REG_FIFOPAGE_INFO_2_8822C */
+
+#define BIT_SHIFT_LPQ_AVAL_PG_V1_8822C 16
+#define BIT_MASK_LPQ_AVAL_PG_V1_8822C 0xfff
+#define BIT_LPQ_AVAL_PG_V1_8822C(x) \
+ (((x) & BIT_MASK_LPQ_AVAL_PG_V1_8822C) \
+ << BIT_SHIFT_LPQ_AVAL_PG_V1_8822C)
+#define BITS_LPQ_AVAL_PG_V1_8822C \
+ (BIT_MASK_LPQ_AVAL_PG_V1_8822C << BIT_SHIFT_LPQ_AVAL_PG_V1_8822C)
+#define BIT_CLEAR_LPQ_AVAL_PG_V1_8822C(x) ((x) & (~BITS_LPQ_AVAL_PG_V1_8822C))
+#define BIT_GET_LPQ_AVAL_PG_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1_8822C) & \
+ BIT_MASK_LPQ_AVAL_PG_V1_8822C)
+#define BIT_SET_LPQ_AVAL_PG_V1_8822C(x, v) \
+ (BIT_CLEAR_LPQ_AVAL_PG_V1_8822C(x) | BIT_LPQ_AVAL_PG_V1_8822C(v))
+
+#define BIT_SHIFT_LPQ_V1_8822C 0
+#define BIT_MASK_LPQ_V1_8822C 0xfff
+#define BIT_LPQ_V1_8822C(x) \
+ (((x) & BIT_MASK_LPQ_V1_8822C) << BIT_SHIFT_LPQ_V1_8822C)
+#define BITS_LPQ_V1_8822C (BIT_MASK_LPQ_V1_8822C << BIT_SHIFT_LPQ_V1_8822C)
+#define BIT_CLEAR_LPQ_V1_8822C(x) ((x) & (~BITS_LPQ_V1_8822C))
+#define BIT_GET_LPQ_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_LPQ_V1_8822C) & BIT_MASK_LPQ_V1_8822C)
+#define BIT_SET_LPQ_V1_8822C(x, v) \
+ (BIT_CLEAR_LPQ_V1_8822C(x) | BIT_LPQ_V1_8822C(v))
+
+/* 2 REG_FIFOPAGE_INFO_3_8822C */
+
+#define BIT_SHIFT_NPQ_AVAL_PG_V1_8822C 16
+#define BIT_MASK_NPQ_AVAL_PG_V1_8822C 0xfff
+#define BIT_NPQ_AVAL_PG_V1_8822C(x) \
+ (((x) & BIT_MASK_NPQ_AVAL_PG_V1_8822C) \
+ << BIT_SHIFT_NPQ_AVAL_PG_V1_8822C)
+#define BITS_NPQ_AVAL_PG_V1_8822C \
+ (BIT_MASK_NPQ_AVAL_PG_V1_8822C << BIT_SHIFT_NPQ_AVAL_PG_V1_8822C)
+#define BIT_CLEAR_NPQ_AVAL_PG_V1_8822C(x) ((x) & (~BITS_NPQ_AVAL_PG_V1_8822C))
+#define BIT_GET_NPQ_AVAL_PG_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1_8822C) & \
+ BIT_MASK_NPQ_AVAL_PG_V1_8822C)
+#define BIT_SET_NPQ_AVAL_PG_V1_8822C(x, v) \
+ (BIT_CLEAR_NPQ_AVAL_PG_V1_8822C(x) | BIT_NPQ_AVAL_PG_V1_8822C(v))
+
+#define BIT_SHIFT_NPQ_V1_8822C 0
+#define BIT_MASK_NPQ_V1_8822C 0xfff
+#define BIT_NPQ_V1_8822C(x) \
+ (((x) & BIT_MASK_NPQ_V1_8822C) << BIT_SHIFT_NPQ_V1_8822C)
+#define BITS_NPQ_V1_8822C (BIT_MASK_NPQ_V1_8822C << BIT_SHIFT_NPQ_V1_8822C)
+#define BIT_CLEAR_NPQ_V1_8822C(x) ((x) & (~BITS_NPQ_V1_8822C))
+#define BIT_GET_NPQ_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_NPQ_V1_8822C) & BIT_MASK_NPQ_V1_8822C)
+#define BIT_SET_NPQ_V1_8822C(x, v) \
+ (BIT_CLEAR_NPQ_V1_8822C(x) | BIT_NPQ_V1_8822C(v))
+
+/* 2 REG_FIFOPAGE_INFO_4_8822C */
+
+#define BIT_SHIFT_EXQ_AVAL_PG_V1_8822C 16
+#define BIT_MASK_EXQ_AVAL_PG_V1_8822C 0xfff
+#define BIT_EXQ_AVAL_PG_V1_8822C(x) \
+ (((x) & BIT_MASK_EXQ_AVAL_PG_V1_8822C) \
+ << BIT_SHIFT_EXQ_AVAL_PG_V1_8822C)
+#define BITS_EXQ_AVAL_PG_V1_8822C \
+ (BIT_MASK_EXQ_AVAL_PG_V1_8822C << BIT_SHIFT_EXQ_AVAL_PG_V1_8822C)
+#define BIT_CLEAR_EXQ_AVAL_PG_V1_8822C(x) ((x) & (~BITS_EXQ_AVAL_PG_V1_8822C))
+#define BIT_GET_EXQ_AVAL_PG_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1_8822C) & \
+ BIT_MASK_EXQ_AVAL_PG_V1_8822C)
+#define BIT_SET_EXQ_AVAL_PG_V1_8822C(x, v) \
+ (BIT_CLEAR_EXQ_AVAL_PG_V1_8822C(x) | BIT_EXQ_AVAL_PG_V1_8822C(v))
+
+#define BIT_SHIFT_EXQ_V1_8822C 0
+#define BIT_MASK_EXQ_V1_8822C 0xfff
+#define BIT_EXQ_V1_8822C(x) \
+ (((x) & BIT_MASK_EXQ_V1_8822C) << BIT_SHIFT_EXQ_V1_8822C)
+#define BITS_EXQ_V1_8822C (BIT_MASK_EXQ_V1_8822C << BIT_SHIFT_EXQ_V1_8822C)
+#define BIT_CLEAR_EXQ_V1_8822C(x) ((x) & (~BITS_EXQ_V1_8822C))
+#define BIT_GET_EXQ_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_EXQ_V1_8822C) & BIT_MASK_EXQ_V1_8822C)
+#define BIT_SET_EXQ_V1_8822C(x, v) \
+ (BIT_CLEAR_EXQ_V1_8822C(x) | BIT_EXQ_V1_8822C(v))
+
+/* 2 REG_FIFOPAGE_INFO_5_8822C */
+
+#define BIT_SHIFT_PUBQ_AVAL_PG_V1_8822C 16
+#define BIT_MASK_PUBQ_AVAL_PG_V1_8822C 0xfff
+#define BIT_PUBQ_AVAL_PG_V1_8822C(x) \
+ (((x) & BIT_MASK_PUBQ_AVAL_PG_V1_8822C) \
+ << BIT_SHIFT_PUBQ_AVAL_PG_V1_8822C)
+#define BITS_PUBQ_AVAL_PG_V1_8822C \
+ (BIT_MASK_PUBQ_AVAL_PG_V1_8822C << BIT_SHIFT_PUBQ_AVAL_PG_V1_8822C)
+#define BIT_CLEAR_PUBQ_AVAL_PG_V1_8822C(x) ((x) & (~BITS_PUBQ_AVAL_PG_V1_8822C))
+#define BIT_GET_PUBQ_AVAL_PG_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1_8822C) & \
+ BIT_MASK_PUBQ_AVAL_PG_V1_8822C)
+#define BIT_SET_PUBQ_AVAL_PG_V1_8822C(x, v) \
+ (BIT_CLEAR_PUBQ_AVAL_PG_V1_8822C(x) | BIT_PUBQ_AVAL_PG_V1_8822C(v))
+
+#define BIT_SHIFT_PUBQ_V1_8822C 0
+#define BIT_MASK_PUBQ_V1_8822C 0xfff
+#define BIT_PUBQ_V1_8822C(x) \
+ (((x) & BIT_MASK_PUBQ_V1_8822C) << BIT_SHIFT_PUBQ_V1_8822C)
+#define BITS_PUBQ_V1_8822C (BIT_MASK_PUBQ_V1_8822C << BIT_SHIFT_PUBQ_V1_8822C)
+#define BIT_CLEAR_PUBQ_V1_8822C(x) ((x) & (~BITS_PUBQ_V1_8822C))
+#define BIT_GET_PUBQ_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_PUBQ_V1_8822C) & BIT_MASK_PUBQ_V1_8822C)
+#define BIT_SET_PUBQ_V1_8822C(x, v) \
+ (BIT_CLEAR_PUBQ_V1_8822C(x) | BIT_PUBQ_V1_8822C(v))
+
+/* 2 REG_H2C_HEAD_8822C */
+
+#define BIT_SHIFT_H2C_HEAD_8822C 0
+#define BIT_MASK_H2C_HEAD_8822C 0x3ffff
+#define BIT_H2C_HEAD_8822C(x) \
+ (((x) & BIT_MASK_H2C_HEAD_8822C) << BIT_SHIFT_H2C_HEAD_8822C)
+#define BITS_H2C_HEAD_8822C \
+ (BIT_MASK_H2C_HEAD_8822C << BIT_SHIFT_H2C_HEAD_8822C)
+#define BIT_CLEAR_H2C_HEAD_8822C(x) ((x) & (~BITS_H2C_HEAD_8822C))
+#define BIT_GET_H2C_HEAD_8822C(x) \
+ (((x) >> BIT_SHIFT_H2C_HEAD_8822C) & BIT_MASK_H2C_HEAD_8822C)
+#define BIT_SET_H2C_HEAD_8822C(x, v) \
+ (BIT_CLEAR_H2C_HEAD_8822C(x) | BIT_H2C_HEAD_8822C(v))
+
+/* 2 REG_H2C_TAIL_8822C */
+
+#define BIT_SHIFT_H2C_TAIL_8822C 0
+#define BIT_MASK_H2C_TAIL_8822C 0x3ffff
+#define BIT_H2C_TAIL_8822C(x) \
+ (((x) & BIT_MASK_H2C_TAIL_8822C) << BIT_SHIFT_H2C_TAIL_8822C)
+#define BITS_H2C_TAIL_8822C \
+ (BIT_MASK_H2C_TAIL_8822C << BIT_SHIFT_H2C_TAIL_8822C)
+#define BIT_CLEAR_H2C_TAIL_8822C(x) ((x) & (~BITS_H2C_TAIL_8822C))
+#define BIT_GET_H2C_TAIL_8822C(x) \
+ (((x) >> BIT_SHIFT_H2C_TAIL_8822C) & BIT_MASK_H2C_TAIL_8822C)
+#define BIT_SET_H2C_TAIL_8822C(x, v) \
+ (BIT_CLEAR_H2C_TAIL_8822C(x) | BIT_H2C_TAIL_8822C(v))
+
+/* 2 REG_H2C_READ_ADDR_8822C */
+
+#define BIT_SHIFT_H2C_READ_ADDR_8822C 0
+#define BIT_MASK_H2C_READ_ADDR_8822C 0x3ffff
+#define BIT_H2C_READ_ADDR_8822C(x) \
+ (((x) & BIT_MASK_H2C_READ_ADDR_8822C) << BIT_SHIFT_H2C_READ_ADDR_8822C)
+#define BITS_H2C_READ_ADDR_8822C \
+ (BIT_MASK_H2C_READ_ADDR_8822C << BIT_SHIFT_H2C_READ_ADDR_8822C)
+#define BIT_CLEAR_H2C_READ_ADDR_8822C(x) ((x) & (~BITS_H2C_READ_ADDR_8822C))
+#define BIT_GET_H2C_READ_ADDR_8822C(x) \
+ (((x) >> BIT_SHIFT_H2C_READ_ADDR_8822C) & BIT_MASK_H2C_READ_ADDR_8822C)
+#define BIT_SET_H2C_READ_ADDR_8822C(x, v) \
+ (BIT_CLEAR_H2C_READ_ADDR_8822C(x) | BIT_H2C_READ_ADDR_8822C(v))
+
+/* 2 REG_H2C_WR_ADDR_8822C */
+
+#define BIT_SHIFT_H2C_WR_ADDR_8822C 0
+#define BIT_MASK_H2C_WR_ADDR_8822C 0x3ffff
+#define BIT_H2C_WR_ADDR_8822C(x) \
+ (((x) & BIT_MASK_H2C_WR_ADDR_8822C) << BIT_SHIFT_H2C_WR_ADDR_8822C)
+#define BITS_H2C_WR_ADDR_8822C \
+ (BIT_MASK_H2C_WR_ADDR_8822C << BIT_SHIFT_H2C_WR_ADDR_8822C)
+#define BIT_CLEAR_H2C_WR_ADDR_8822C(x) ((x) & (~BITS_H2C_WR_ADDR_8822C))
+#define BIT_GET_H2C_WR_ADDR_8822C(x) \
+ (((x) >> BIT_SHIFT_H2C_WR_ADDR_8822C) & BIT_MASK_H2C_WR_ADDR_8822C)
+#define BIT_SET_H2C_WR_ADDR_8822C(x, v) \
+ (BIT_CLEAR_H2C_WR_ADDR_8822C(x) | BIT_H2C_WR_ADDR_8822C(v))
+
+/* 2 REG_H2C_INFO_8822C */
+#define BIT_H2C_SPACE_VLD_8822C BIT(3)
+#define BIT_H2C_WR_ADDR_RST_8822C BIT(2)
+
+#define BIT_SHIFT_H2C_LEN_SEL_8822C 0
+#define BIT_MASK_H2C_LEN_SEL_8822C 0x3
+#define BIT_H2C_LEN_SEL_8822C(x) \
+ (((x) & BIT_MASK_H2C_LEN_SEL_8822C) << BIT_SHIFT_H2C_LEN_SEL_8822C)
+#define BITS_H2C_LEN_SEL_8822C \
+ (BIT_MASK_H2C_LEN_SEL_8822C << BIT_SHIFT_H2C_LEN_SEL_8822C)
+#define BIT_CLEAR_H2C_LEN_SEL_8822C(x) ((x) & (~BITS_H2C_LEN_SEL_8822C))
+#define BIT_GET_H2C_LEN_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_H2C_LEN_SEL_8822C) & BIT_MASK_H2C_LEN_SEL_8822C)
+#define BIT_SET_H2C_LEN_SEL_8822C(x, v) \
+ (BIT_CLEAR_H2C_LEN_SEL_8822C(x) | BIT_H2C_LEN_SEL_8822C(v))
+
+/* 2 REG_PGSUB_CNT_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_RST_PGSUB_CNT_8822C BIT(1)
+#define BIT_PGSUB_CNT_EN_8822C BIT(0)
+
+/* 2 REG_PGSUB_H_8822C */
+
+#define BIT_SHIFT_HPQ_PGSUB_CNT_8822C 0
+#define BIT_MASK_HPQ_PGSUB_CNT_8822C 0xffffffffL
+#define BIT_HPQ_PGSUB_CNT_8822C(x) \
+ (((x) & BIT_MASK_HPQ_PGSUB_CNT_8822C) << BIT_SHIFT_HPQ_PGSUB_CNT_8822C)
+#define BITS_HPQ_PGSUB_CNT_8822C \
+ (BIT_MASK_HPQ_PGSUB_CNT_8822C << BIT_SHIFT_HPQ_PGSUB_CNT_8822C)
+#define BIT_CLEAR_HPQ_PGSUB_CNT_8822C(x) ((x) & (~BITS_HPQ_PGSUB_CNT_8822C))
+#define BIT_GET_HPQ_PGSUB_CNT_8822C(x) \
+ (((x) >> BIT_SHIFT_HPQ_PGSUB_CNT_8822C) & BIT_MASK_HPQ_PGSUB_CNT_8822C)
+#define BIT_SET_HPQ_PGSUB_CNT_8822C(x, v) \
+ (BIT_CLEAR_HPQ_PGSUB_CNT_8822C(x) | BIT_HPQ_PGSUB_CNT_8822C(v))
+
+/* 2 REG_PGSUB_N_8822C */
+
+#define BIT_SHIFT_NPQ_PGSUB_CNT_8822C 0
+#define BIT_MASK_NPQ_PGSUB_CNT_8822C 0xffffffffL
+#define BIT_NPQ_PGSUB_CNT_8822C(x) \
+ (((x) & BIT_MASK_NPQ_PGSUB_CNT_8822C) << BIT_SHIFT_NPQ_PGSUB_CNT_8822C)
+#define BITS_NPQ_PGSUB_CNT_8822C \
+ (BIT_MASK_NPQ_PGSUB_CNT_8822C << BIT_SHIFT_NPQ_PGSUB_CNT_8822C)
+#define BIT_CLEAR_NPQ_PGSUB_CNT_8822C(x) ((x) & (~BITS_NPQ_PGSUB_CNT_8822C))
+#define BIT_GET_NPQ_PGSUB_CNT_8822C(x) \
+ (((x) >> BIT_SHIFT_NPQ_PGSUB_CNT_8822C) & BIT_MASK_NPQ_PGSUB_CNT_8822C)
+#define BIT_SET_NPQ_PGSUB_CNT_8822C(x, v) \
+ (BIT_CLEAR_NPQ_PGSUB_CNT_8822C(x) | BIT_NPQ_PGSUB_CNT_8822C(v))
+
+/* 2 REG_PGSUB_L_8822C */
+
+#define BIT_SHIFT_LPQ_PGSUB_CNT_8822C 0
+#define BIT_MASK_LPQ_PGSUB_CNT_8822C 0xffffffffL
+#define BIT_LPQ_PGSUB_CNT_8822C(x) \
+ (((x) & BIT_MASK_LPQ_PGSUB_CNT_8822C) << BIT_SHIFT_LPQ_PGSUB_CNT_8822C)
+#define BITS_LPQ_PGSUB_CNT_8822C \
+ (BIT_MASK_LPQ_PGSUB_CNT_8822C << BIT_SHIFT_LPQ_PGSUB_CNT_8822C)
+#define BIT_CLEAR_LPQ_PGSUB_CNT_8822C(x) ((x) & (~BITS_LPQ_PGSUB_CNT_8822C))
+#define BIT_GET_LPQ_PGSUB_CNT_8822C(x) \
+ (((x) >> BIT_SHIFT_LPQ_PGSUB_CNT_8822C) & BIT_MASK_LPQ_PGSUB_CNT_8822C)
+#define BIT_SET_LPQ_PGSUB_CNT_8822C(x, v) \
+ (BIT_CLEAR_LPQ_PGSUB_CNT_8822C(x) | BIT_LPQ_PGSUB_CNT_8822C(v))
+
+/* 2 REG_PGSUB_E_8822C */
+
+#define BIT_SHIFT_EPQ_PGSUB_CNT_8822C 0
+#define BIT_MASK_EPQ_PGSUB_CNT_8822C 0xffffffffL
+#define BIT_EPQ_PGSUB_CNT_8822C(x) \
+ (((x) & BIT_MASK_EPQ_PGSUB_CNT_8822C) << BIT_SHIFT_EPQ_PGSUB_CNT_8822C)
+#define BITS_EPQ_PGSUB_CNT_8822C \
+ (BIT_MASK_EPQ_PGSUB_CNT_8822C << BIT_SHIFT_EPQ_PGSUB_CNT_8822C)
+#define BIT_CLEAR_EPQ_PGSUB_CNT_8822C(x) ((x) & (~BITS_EPQ_PGSUB_CNT_8822C))
+#define BIT_GET_EPQ_PGSUB_CNT_8822C(x) \
+ (((x) >> BIT_SHIFT_EPQ_PGSUB_CNT_8822C) & BIT_MASK_EPQ_PGSUB_CNT_8822C)
+#define BIT_SET_EPQ_PGSUB_CNT_8822C(x, v) \
+ (BIT_CLEAR_EPQ_PGSUB_CNT_8822C(x) | BIT_EPQ_PGSUB_CNT_8822C(v))
+
+/* 2 REG_RXDMA_AGG_PG_TH_8822C */
+#define BIT_USB_RXDMA_AGG_EN_8822C BIT(31)
+#define BIT_EN_FW_ADD_8822C BIT(30)
+#define BIT_EN_PRE_CALC_8822C BIT(29)
+#define BIT_RXAGG_SW_EN_8822C BIT(28)
+#define BIT_RXAGG_SW_TRIG_8822C BIT(27)
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_DMA_AGG_TO_V1_8822C 8
+#define BIT_MASK_DMA_AGG_TO_V1_8822C 0xff
+#define BIT_DMA_AGG_TO_V1_8822C(x) \
+ (((x) & BIT_MASK_DMA_AGG_TO_V1_8822C) << BIT_SHIFT_DMA_AGG_TO_V1_8822C)
+#define BITS_DMA_AGG_TO_V1_8822C \
+ (BIT_MASK_DMA_AGG_TO_V1_8822C << BIT_SHIFT_DMA_AGG_TO_V1_8822C)
+#define BIT_CLEAR_DMA_AGG_TO_V1_8822C(x) ((x) & (~BITS_DMA_AGG_TO_V1_8822C))
+#define BIT_GET_DMA_AGG_TO_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_DMA_AGG_TO_V1_8822C) & BIT_MASK_DMA_AGG_TO_V1_8822C)
+#define BIT_SET_DMA_AGG_TO_V1_8822C(x, v) \
+ (BIT_CLEAR_DMA_AGG_TO_V1_8822C(x) | BIT_DMA_AGG_TO_V1_8822C(v))
+
+#define BIT_SHIFT_RXDMA_AGG_PG_TH_8822C 0
+#define BIT_MASK_RXDMA_AGG_PG_TH_8822C 0xff
+#define BIT_RXDMA_AGG_PG_TH_8822C(x) \
+ (((x) & BIT_MASK_RXDMA_AGG_PG_TH_8822C) \
+ << BIT_SHIFT_RXDMA_AGG_PG_TH_8822C)
+#define BITS_RXDMA_AGG_PG_TH_8822C \
+ (BIT_MASK_RXDMA_AGG_PG_TH_8822C << BIT_SHIFT_RXDMA_AGG_PG_TH_8822C)
+#define BIT_CLEAR_RXDMA_AGG_PG_TH_8822C(x) ((x) & (~BITS_RXDMA_AGG_PG_TH_8822C))
+#define BIT_GET_RXDMA_AGG_PG_TH_8822C(x) \
+ (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_8822C) & \
+ BIT_MASK_RXDMA_AGG_PG_TH_8822C)
+#define BIT_SET_RXDMA_AGG_PG_TH_8822C(x, v) \
+ (BIT_CLEAR_RXDMA_AGG_PG_TH_8822C(x) | BIT_RXDMA_AGG_PG_TH_8822C(v))
+
+/* 2 REG_RXPKT_NUM_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822C 20
+#define BIT_MASK_FW_UPD_RDPTR19_TO_16_8822C 0xf
+#define BIT_FW_UPD_RDPTR19_TO_16_8822C(x) \
+ (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8822C) \
+ << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822C)
+#define BITS_FW_UPD_RDPTR19_TO_16_8822C \
+ (BIT_MASK_FW_UPD_RDPTR19_TO_16_8822C \
+ << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822C)
+#define BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8822C(x) \
+ ((x) & (~BITS_FW_UPD_RDPTR19_TO_16_8822C))
+#define BIT_GET_FW_UPD_RDPTR19_TO_16_8822C(x) \
+ (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8822C) & \
+ BIT_MASK_FW_UPD_RDPTR19_TO_16_8822C)
+#define BIT_SET_FW_UPD_RDPTR19_TO_16_8822C(x, v) \
+ (BIT_CLEAR_FW_UPD_RDPTR19_TO_16_8822C(x) | \
+ BIT_FW_UPD_RDPTR19_TO_16_8822C(v))
+
+#define BIT_RXDMA_REQ_8822C BIT(19)
+#define BIT_RW_RELEASE_EN_8822C BIT(18)
+#define BIT_RXDMA_IDLE_8822C BIT(17)
+#define BIT_RXPKT_RELEASE_POLL_8822C BIT(16)
+
+#define BIT_SHIFT_FW_UPD_RDPTR_8822C 0
+#define BIT_MASK_FW_UPD_RDPTR_8822C 0xffff
+#define BIT_FW_UPD_RDPTR_8822C(x) \
+ (((x) & BIT_MASK_FW_UPD_RDPTR_8822C) << BIT_SHIFT_FW_UPD_RDPTR_8822C)
+#define BITS_FW_UPD_RDPTR_8822C \
+ (BIT_MASK_FW_UPD_RDPTR_8822C << BIT_SHIFT_FW_UPD_RDPTR_8822C)
+#define BIT_CLEAR_FW_UPD_RDPTR_8822C(x) ((x) & (~BITS_FW_UPD_RDPTR_8822C))
+#define BIT_GET_FW_UPD_RDPTR_8822C(x) \
+ (((x) >> BIT_SHIFT_FW_UPD_RDPTR_8822C) & BIT_MASK_FW_UPD_RDPTR_8822C)
+#define BIT_SET_FW_UPD_RDPTR_8822C(x, v) \
+ (BIT_CLEAR_FW_UPD_RDPTR_8822C(x) | BIT_FW_UPD_RDPTR_8822C(v))
+
+/* 2 REG_RXDMA_STATUS_8822C */
+#define BIT_C2H_PKT_OVF_8822C BIT(7)
+#define BIT_AGG_CONFGI_ISSUE_8822C BIT(6)
+#define BIT_FW_POLL_ISSUE_8822C BIT(5)
+#define BIT_RX_DATA_UDN_8822C BIT(4)
+#define BIT_RX_SFF_UDN_8822C BIT(3)
+#define BIT_RX_SFF_OVF_8822C BIT(2)
+#define BIT_RXPKT_OVF_8822C BIT(0)
+
+/* 2 REG_RXDMA_DPR_8822C */
+
+#define BIT_SHIFT_RDE_DEBUG_8822C 0
+#define BIT_MASK_RDE_DEBUG_8822C 0xffffffffL
+#define BIT_RDE_DEBUG_8822C(x) \
+ (((x) & BIT_MASK_RDE_DEBUG_8822C) << BIT_SHIFT_RDE_DEBUG_8822C)
+#define BITS_RDE_DEBUG_8822C \
+ (BIT_MASK_RDE_DEBUG_8822C << BIT_SHIFT_RDE_DEBUG_8822C)
+#define BIT_CLEAR_RDE_DEBUG_8822C(x) ((x) & (~BITS_RDE_DEBUG_8822C))
+#define BIT_GET_RDE_DEBUG_8822C(x) \
+ (((x) >> BIT_SHIFT_RDE_DEBUG_8822C) & BIT_MASK_RDE_DEBUG_8822C)
+#define BIT_SET_RDE_DEBUG_8822C(x, v) \
+ (BIT_CLEAR_RDE_DEBUG_8822C(x) | BIT_RDE_DEBUG_8822C(v))
+
+/* 2 REG_RXDMA_MODE_8822C */
+
+#define BIT_SHIFT_PKTNUM_TH_V2_8822C 24
+#define BIT_MASK_PKTNUM_TH_V2_8822C 0x1f
+#define BIT_PKTNUM_TH_V2_8822C(x) \
+ (((x) & BIT_MASK_PKTNUM_TH_V2_8822C) << BIT_SHIFT_PKTNUM_TH_V2_8822C)
+#define BITS_PKTNUM_TH_V2_8822C \
+ (BIT_MASK_PKTNUM_TH_V2_8822C << BIT_SHIFT_PKTNUM_TH_V2_8822C)
+#define BIT_CLEAR_PKTNUM_TH_V2_8822C(x) ((x) & (~BITS_PKTNUM_TH_V2_8822C))
+#define BIT_GET_PKTNUM_TH_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_PKTNUM_TH_V2_8822C) & BIT_MASK_PKTNUM_TH_V2_8822C)
+#define BIT_SET_PKTNUM_TH_V2_8822C(x, v) \
+ (BIT_CLEAR_PKTNUM_TH_V2_8822C(x) | BIT_PKTNUM_TH_V2_8822C(v))
+
+#define BIT_TXBA_BREAK_USBAGG_8822C BIT(23)
+
+#define BIT_SHIFT_PKTLEN_PARA_8822C 16
+#define BIT_MASK_PKTLEN_PARA_8822C 0x7
+#define BIT_PKTLEN_PARA_8822C(x) \
+ (((x) & BIT_MASK_PKTLEN_PARA_8822C) << BIT_SHIFT_PKTLEN_PARA_8822C)
+#define BITS_PKTLEN_PARA_8822C \
+ (BIT_MASK_PKTLEN_PARA_8822C << BIT_SHIFT_PKTLEN_PARA_8822C)
+#define BIT_CLEAR_PKTLEN_PARA_8822C(x) ((x) & (~BITS_PKTLEN_PARA_8822C))
+#define BIT_GET_PKTLEN_PARA_8822C(x) \
+ (((x) >> BIT_SHIFT_PKTLEN_PARA_8822C) & BIT_MASK_PKTLEN_PARA_8822C)
+#define BIT_SET_PKTLEN_PARA_8822C(x, v) \
+ (BIT_CLEAR_PKTLEN_PARA_8822C(x) | BIT_PKTLEN_PARA_8822C(v))
+
+#define BIT_RX_DBG_SEL_8822C BIT(7)
+#define BIT_EN_SPD_8822C BIT(6)
+
+#define BIT_SHIFT_BURST_SIZE_8822C 4
+#define BIT_MASK_BURST_SIZE_8822C 0x3
+#define BIT_BURST_SIZE_8822C(x) \
+ (((x) & BIT_MASK_BURST_SIZE_8822C) << BIT_SHIFT_BURST_SIZE_8822C)
+#define BITS_BURST_SIZE_8822C \
+ (BIT_MASK_BURST_SIZE_8822C << BIT_SHIFT_BURST_SIZE_8822C)
+#define BIT_CLEAR_BURST_SIZE_8822C(x) ((x) & (~BITS_BURST_SIZE_8822C))
+#define BIT_GET_BURST_SIZE_8822C(x) \
+ (((x) >> BIT_SHIFT_BURST_SIZE_8822C) & BIT_MASK_BURST_SIZE_8822C)
+#define BIT_SET_BURST_SIZE_8822C(x, v) \
+ (BIT_CLEAR_BURST_SIZE_8822C(x) | BIT_BURST_SIZE_8822C(v))
+
+#define BIT_SHIFT_BURST_CNT_8822C 2
+#define BIT_MASK_BURST_CNT_8822C 0x3
+#define BIT_BURST_CNT_8822C(x) \
+ (((x) & BIT_MASK_BURST_CNT_8822C) << BIT_SHIFT_BURST_CNT_8822C)
+#define BITS_BURST_CNT_8822C \
+ (BIT_MASK_BURST_CNT_8822C << BIT_SHIFT_BURST_CNT_8822C)
+#define BIT_CLEAR_BURST_CNT_8822C(x) ((x) & (~BITS_BURST_CNT_8822C))
+#define BIT_GET_BURST_CNT_8822C(x) \
+ (((x) >> BIT_SHIFT_BURST_CNT_8822C) & BIT_MASK_BURST_CNT_8822C)
+#define BIT_SET_BURST_CNT_8822C(x, v) \
+ (BIT_CLEAR_BURST_CNT_8822C(x) | BIT_BURST_CNT_8822C(v))
+
+#define BIT_DMA_MODE_8822C BIT(1)
+
+/* 2 REG_C2H_PKT_8822C */
+
+#define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822C 24
+#define BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822C 0xf
+#define BIT_R_C2H_STR_ADDR_16_TO_19_8822C(x) \
+ (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822C) \
+ << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822C)
+#define BITS_R_C2H_STR_ADDR_16_TO_19_8822C \
+ (BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822C \
+ << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822C)
+#define BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8822C(x) \
+ ((x) & (~BITS_R_C2H_STR_ADDR_16_TO_19_8822C))
+#define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8822C(x) \
+ (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8822C) & \
+ BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8822C)
+#define BIT_SET_R_C2H_STR_ADDR_16_TO_19_8822C(x, v) \
+ (BIT_CLEAR_R_C2H_STR_ADDR_16_TO_19_8822C(x) | \
+ BIT_R_C2H_STR_ADDR_16_TO_19_8822C(v))
+
+#define BIT_R_C2H_PKT_REQ_8822C BIT(16)
+
+#define BIT_SHIFT_R_C2H_STR_ADDR_8822C 0
+#define BIT_MASK_R_C2H_STR_ADDR_8822C 0xffff
+#define BIT_R_C2H_STR_ADDR_8822C(x) \
+ (((x) & BIT_MASK_R_C2H_STR_ADDR_8822C) \
+ << BIT_SHIFT_R_C2H_STR_ADDR_8822C)
+#define BITS_R_C2H_STR_ADDR_8822C \
+ (BIT_MASK_R_C2H_STR_ADDR_8822C << BIT_SHIFT_R_C2H_STR_ADDR_8822C)
+#define BIT_CLEAR_R_C2H_STR_ADDR_8822C(x) ((x) & (~BITS_R_C2H_STR_ADDR_8822C))
+#define BIT_GET_R_C2H_STR_ADDR_8822C(x) \
+ (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8822C) & \
+ BIT_MASK_R_C2H_STR_ADDR_8822C)
+#define BIT_SET_R_C2H_STR_ADDR_8822C(x, v) \
+ (BIT_CLEAR_R_C2H_STR_ADDR_8822C(x) | BIT_R_C2H_STR_ADDR_8822C(v))
+
+/* 2 REG_FWFF_C2H_8822C */
+
+#define BIT_SHIFT_C2H_DMA_ADDR_8822C 0
+#define BIT_MASK_C2H_DMA_ADDR_8822C 0x3ffff
+#define BIT_C2H_DMA_ADDR_8822C(x) \
+ (((x) & BIT_MASK_C2H_DMA_ADDR_8822C) << BIT_SHIFT_C2H_DMA_ADDR_8822C)
+#define BITS_C2H_DMA_ADDR_8822C \
+ (BIT_MASK_C2H_DMA_ADDR_8822C << BIT_SHIFT_C2H_DMA_ADDR_8822C)
+#define BIT_CLEAR_C2H_DMA_ADDR_8822C(x) ((x) & (~BITS_C2H_DMA_ADDR_8822C))
+#define BIT_GET_C2H_DMA_ADDR_8822C(x) \
+ (((x) >> BIT_SHIFT_C2H_DMA_ADDR_8822C) & BIT_MASK_C2H_DMA_ADDR_8822C)
+#define BIT_SET_C2H_DMA_ADDR_8822C(x, v) \
+ (BIT_CLEAR_C2H_DMA_ADDR_8822C(x) | BIT_C2H_DMA_ADDR_8822C(v))
+
+/* 2 REG_FWFF_CTRL_8822C */
+#define BIT_FWFF_DMAPKT_REQ_8822C BIT(31)
+
+#define BIT_SHIFT_FWFF_DMA_PKT_NUM_8822C 16
+#define BIT_MASK_FWFF_DMA_PKT_NUM_8822C 0xff
+#define BIT_FWFF_DMA_PKT_NUM_8822C(x) \
+ (((x) & BIT_MASK_FWFF_DMA_PKT_NUM_8822C) \
+ << BIT_SHIFT_FWFF_DMA_PKT_NUM_8822C)
+#define BITS_FWFF_DMA_PKT_NUM_8822C \
+ (BIT_MASK_FWFF_DMA_PKT_NUM_8822C << BIT_SHIFT_FWFF_DMA_PKT_NUM_8822C)
+#define BIT_CLEAR_FWFF_DMA_PKT_NUM_8822C(x) \
+ ((x) & (~BITS_FWFF_DMA_PKT_NUM_8822C))
+#define BIT_GET_FWFF_DMA_PKT_NUM_8822C(x) \
+ (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_8822C) & \
+ BIT_MASK_FWFF_DMA_PKT_NUM_8822C)
+#define BIT_SET_FWFF_DMA_PKT_NUM_8822C(x, v) \
+ (BIT_CLEAR_FWFF_DMA_PKT_NUM_8822C(x) | BIT_FWFF_DMA_PKT_NUM_8822C(v))
+
+#define BIT_SHIFT_FWFF_STR_ADDR_8822C 0
+#define BIT_MASK_FWFF_STR_ADDR_8822C 0xffff
+#define BIT_FWFF_STR_ADDR_8822C(x) \
+ (((x) & BIT_MASK_FWFF_STR_ADDR_8822C) << BIT_SHIFT_FWFF_STR_ADDR_8822C)
+#define BITS_FWFF_STR_ADDR_8822C \
+ (BIT_MASK_FWFF_STR_ADDR_8822C << BIT_SHIFT_FWFF_STR_ADDR_8822C)
+#define BIT_CLEAR_FWFF_STR_ADDR_8822C(x) ((x) & (~BITS_FWFF_STR_ADDR_8822C))
+#define BIT_GET_FWFF_STR_ADDR_8822C(x) \
+ (((x) >> BIT_SHIFT_FWFF_STR_ADDR_8822C) & BIT_MASK_FWFF_STR_ADDR_8822C)
+#define BIT_SET_FWFF_STR_ADDR_8822C(x, v) \
+ (BIT_CLEAR_FWFF_STR_ADDR_8822C(x) | BIT_FWFF_STR_ADDR_8822C(v))
+
+/* 2 REG_FWFF_PKT_INFO_8822C */
+
+#define BIT_SHIFT_FWFF_PKT_QUEUED_8822C 16
+#define BIT_MASK_FWFF_PKT_QUEUED_8822C 0xff
+#define BIT_FWFF_PKT_QUEUED_8822C(x) \
+ (((x) & BIT_MASK_FWFF_PKT_QUEUED_8822C) \
+ << BIT_SHIFT_FWFF_PKT_QUEUED_8822C)
+#define BITS_FWFF_PKT_QUEUED_8822C \
+ (BIT_MASK_FWFF_PKT_QUEUED_8822C << BIT_SHIFT_FWFF_PKT_QUEUED_8822C)
+#define BIT_CLEAR_FWFF_PKT_QUEUED_8822C(x) ((x) & (~BITS_FWFF_PKT_QUEUED_8822C))
+#define BIT_GET_FWFF_PKT_QUEUED_8822C(x) \
+ (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_8822C) & \
+ BIT_MASK_FWFF_PKT_QUEUED_8822C)
+#define BIT_SET_FWFF_PKT_QUEUED_8822C(x, v) \
+ (BIT_CLEAR_FWFF_PKT_QUEUED_8822C(x) | BIT_FWFF_PKT_QUEUED_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_FWFF_PKT_STR_ADDR_V2_8822C 0
+#define BIT_MASK_FWFF_PKT_STR_ADDR_V2_8822C 0x3fff
+#define BIT_FWFF_PKT_STR_ADDR_V2_8822C(x) \
+ (((x) & BIT_MASK_FWFF_PKT_STR_ADDR_V2_8822C) \
+ << BIT_SHIFT_FWFF_PKT_STR_ADDR_V2_8822C)
+#define BITS_FWFF_PKT_STR_ADDR_V2_8822C \
+ (BIT_MASK_FWFF_PKT_STR_ADDR_V2_8822C \
+ << BIT_SHIFT_FWFF_PKT_STR_ADDR_V2_8822C)
+#define BIT_CLEAR_FWFF_PKT_STR_ADDR_V2_8822C(x) \
+ ((x) & (~BITS_FWFF_PKT_STR_ADDR_V2_8822C))
+#define BIT_GET_FWFF_PKT_STR_ADDR_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_V2_8822C) & \
+ BIT_MASK_FWFF_PKT_STR_ADDR_V2_8822C)
+#define BIT_SET_FWFF_PKT_STR_ADDR_V2_8822C(x, v) \
+ (BIT_CLEAR_FWFF_PKT_STR_ADDR_V2_8822C(x) | \
+ BIT_FWFF_PKT_STR_ADDR_V2_8822C(v))
+
+/* 2 REG_RXPKTNUM_8822C */
+
+#define BIT_SHIFT_PKT_NUM_WOL_V1_8822C 16
+#define BIT_MASK_PKT_NUM_WOL_V1_8822C 0xffff
+#define BIT_PKT_NUM_WOL_V1_8822C(x) \
+ (((x) & BIT_MASK_PKT_NUM_WOL_V1_8822C) \
+ << BIT_SHIFT_PKT_NUM_WOL_V1_8822C)
+#define BITS_PKT_NUM_WOL_V1_8822C \
+ (BIT_MASK_PKT_NUM_WOL_V1_8822C << BIT_SHIFT_PKT_NUM_WOL_V1_8822C)
+#define BIT_CLEAR_PKT_NUM_WOL_V1_8822C(x) ((x) & (~BITS_PKT_NUM_WOL_V1_8822C))
+#define BIT_GET_PKT_NUM_WOL_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_PKT_NUM_WOL_V1_8822C) & \
+ BIT_MASK_PKT_NUM_WOL_V1_8822C)
+#define BIT_SET_PKT_NUM_WOL_V1_8822C(x, v) \
+ (BIT_CLEAR_PKT_NUM_WOL_V1_8822C(x) | BIT_PKT_NUM_WOL_V1_8822C(v))
+
+#define BIT_SHIFT_RXPKT_NUM_V1_8822C 0
+#define BIT_MASK_RXPKT_NUM_V1_8822C 0xffff
+#define BIT_RXPKT_NUM_V1_8822C(x) \
+ (((x) & BIT_MASK_RXPKT_NUM_V1_8822C) << BIT_SHIFT_RXPKT_NUM_V1_8822C)
+#define BITS_RXPKT_NUM_V1_8822C \
+ (BIT_MASK_RXPKT_NUM_V1_8822C << BIT_SHIFT_RXPKT_NUM_V1_8822C)
+#define BIT_CLEAR_RXPKT_NUM_V1_8822C(x) ((x) & (~BITS_RXPKT_NUM_V1_8822C))
+#define BIT_GET_RXPKT_NUM_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_RXPKT_NUM_V1_8822C) & BIT_MASK_RXPKT_NUM_V1_8822C)
+#define BIT_SET_RXPKT_NUM_V1_8822C(x, v) \
+ (BIT_CLEAR_RXPKT_NUM_V1_8822C(x) | BIT_RXPKT_NUM_V1_8822C(v))
+
+/* 2 REG_RXPKTNUM_TH_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_RXPKT_NUM_TH_8822C 0
+#define BIT_MASK_RXPKT_NUM_TH_8822C 0xff
+#define BIT_RXPKT_NUM_TH_8822C(x) \
+ (((x) & BIT_MASK_RXPKT_NUM_TH_8822C) << BIT_SHIFT_RXPKT_NUM_TH_8822C)
+#define BITS_RXPKT_NUM_TH_8822C \
+ (BIT_MASK_RXPKT_NUM_TH_8822C << BIT_SHIFT_RXPKT_NUM_TH_8822C)
+#define BIT_CLEAR_RXPKT_NUM_TH_8822C(x) ((x) & (~BITS_RXPKT_NUM_TH_8822C))
+#define BIT_GET_RXPKT_NUM_TH_8822C(x) \
+ (((x) >> BIT_SHIFT_RXPKT_NUM_TH_8822C) & BIT_MASK_RXPKT_NUM_TH_8822C)
+#define BIT_SET_RXPKT_NUM_TH_8822C(x, v) \
+ (BIT_CLEAR_RXPKT_NUM_TH_8822C(x) | BIT_RXPKT_NUM_TH_8822C(v))
+
+/* 2 REG_FW_MSG1_8822C */
+
+#define BIT_SHIFT_FW_MSG_REG1_8822C 0
+#define BIT_MASK_FW_MSG_REG1_8822C 0xffffffffL
+#define BIT_FW_MSG_REG1_8822C(x) \
+ (((x) & BIT_MASK_FW_MSG_REG1_8822C) << BIT_SHIFT_FW_MSG_REG1_8822C)
+#define BITS_FW_MSG_REG1_8822C \
+ (BIT_MASK_FW_MSG_REG1_8822C << BIT_SHIFT_FW_MSG_REG1_8822C)
+#define BIT_CLEAR_FW_MSG_REG1_8822C(x) ((x) & (~BITS_FW_MSG_REG1_8822C))
+#define BIT_GET_FW_MSG_REG1_8822C(x) \
+ (((x) >> BIT_SHIFT_FW_MSG_REG1_8822C) & BIT_MASK_FW_MSG_REG1_8822C)
+#define BIT_SET_FW_MSG_REG1_8822C(x, v) \
+ (BIT_CLEAR_FW_MSG_REG1_8822C(x) | BIT_FW_MSG_REG1_8822C(v))
+
+/* 2 REG_FW_MSG2_8822C */
+
+#define BIT_SHIFT_FW_MSG_REG2_8822C 0
+#define BIT_MASK_FW_MSG_REG2_8822C 0xffffffffL
+#define BIT_FW_MSG_REG2_8822C(x) \
+ (((x) & BIT_MASK_FW_MSG_REG2_8822C) << BIT_SHIFT_FW_MSG_REG2_8822C)
+#define BITS_FW_MSG_REG2_8822C \
+ (BIT_MASK_FW_MSG_REG2_8822C << BIT_SHIFT_FW_MSG_REG2_8822C)
+#define BIT_CLEAR_FW_MSG_REG2_8822C(x) ((x) & (~BITS_FW_MSG_REG2_8822C))
+#define BIT_GET_FW_MSG_REG2_8822C(x) \
+ (((x) >> BIT_SHIFT_FW_MSG_REG2_8822C) & BIT_MASK_FW_MSG_REG2_8822C)
+#define BIT_SET_FW_MSG_REG2_8822C(x, v) \
+ (BIT_CLEAR_FW_MSG_REG2_8822C(x) | BIT_FW_MSG_REG2_8822C(v))
+
+/* 2 REG_FW_MSG3_8822C */
+
+#define BIT_SHIFT_FW_MSG_REG3_8822C 0
+#define BIT_MASK_FW_MSG_REG3_8822C 0xffffffffL
+#define BIT_FW_MSG_REG3_8822C(x) \
+ (((x) & BIT_MASK_FW_MSG_REG3_8822C) << BIT_SHIFT_FW_MSG_REG3_8822C)
+#define BITS_FW_MSG_REG3_8822C \
+ (BIT_MASK_FW_MSG_REG3_8822C << BIT_SHIFT_FW_MSG_REG3_8822C)
+#define BIT_CLEAR_FW_MSG_REG3_8822C(x) ((x) & (~BITS_FW_MSG_REG3_8822C))
+#define BIT_GET_FW_MSG_REG3_8822C(x) \
+ (((x) >> BIT_SHIFT_FW_MSG_REG3_8822C) & BIT_MASK_FW_MSG_REG3_8822C)
+#define BIT_SET_FW_MSG_REG3_8822C(x, v) \
+ (BIT_CLEAR_FW_MSG_REG3_8822C(x) | BIT_FW_MSG_REG3_8822C(v))
+
+/* 2 REG_FW_MSG4_8822C */
+
+#define BIT_SHIFT_FW_MSG_REG4_8822C 0
+#define BIT_MASK_FW_MSG_REG4_8822C 0xffffffffL
+#define BIT_FW_MSG_REG4_8822C(x) \
+ (((x) & BIT_MASK_FW_MSG_REG4_8822C) << BIT_SHIFT_FW_MSG_REG4_8822C)
+#define BITS_FW_MSG_REG4_8822C \
+ (BIT_MASK_FW_MSG_REG4_8822C << BIT_SHIFT_FW_MSG_REG4_8822C)
+#define BIT_CLEAR_FW_MSG_REG4_8822C(x) ((x) & (~BITS_FW_MSG_REG4_8822C))
+#define BIT_GET_FW_MSG_REG4_8822C(x) \
+ (((x) >> BIT_SHIFT_FW_MSG_REG4_8822C) & BIT_MASK_FW_MSG_REG4_8822C)
+#define BIT_SET_FW_MSG_REG4_8822C(x, v) \
+ (BIT_CLEAR_FW_MSG_REG4_8822C(x) | BIT_FW_MSG_REG4_8822C(v))
+
+/* 2 REG_DDMA_CH0SA_8822C */
+
+#define BIT_SHIFT_DDMACH0_SA_8822C 0
+#define BIT_MASK_DDMACH0_SA_8822C 0xffffffffL
+#define BIT_DDMACH0_SA_8822C(x) \
+ (((x) & BIT_MASK_DDMACH0_SA_8822C) << BIT_SHIFT_DDMACH0_SA_8822C)
+#define BITS_DDMACH0_SA_8822C \
+ (BIT_MASK_DDMACH0_SA_8822C << BIT_SHIFT_DDMACH0_SA_8822C)
+#define BIT_CLEAR_DDMACH0_SA_8822C(x) ((x) & (~BITS_DDMACH0_SA_8822C))
+#define BIT_GET_DDMACH0_SA_8822C(x) \
+ (((x) >> BIT_SHIFT_DDMACH0_SA_8822C) & BIT_MASK_DDMACH0_SA_8822C)
+#define BIT_SET_DDMACH0_SA_8822C(x, v) \
+ (BIT_CLEAR_DDMACH0_SA_8822C(x) | BIT_DDMACH0_SA_8822C(v))
+
+/* 2 REG_DDMA_CH0DA_8822C */
+
+#define BIT_SHIFT_DDMACH0_DA_8822C 0
+#define BIT_MASK_DDMACH0_DA_8822C 0xffffffffL
+#define BIT_DDMACH0_DA_8822C(x) \
+ (((x) & BIT_MASK_DDMACH0_DA_8822C) << BIT_SHIFT_DDMACH0_DA_8822C)
+#define BITS_DDMACH0_DA_8822C \
+ (BIT_MASK_DDMACH0_DA_8822C << BIT_SHIFT_DDMACH0_DA_8822C)
+#define BIT_CLEAR_DDMACH0_DA_8822C(x) ((x) & (~BITS_DDMACH0_DA_8822C))
+#define BIT_GET_DDMACH0_DA_8822C(x) \
+ (((x) >> BIT_SHIFT_DDMACH0_DA_8822C) & BIT_MASK_DDMACH0_DA_8822C)
+#define BIT_SET_DDMACH0_DA_8822C(x, v) \
+ (BIT_CLEAR_DDMACH0_DA_8822C(x) | BIT_DDMACH0_DA_8822C(v))
+
+/* 2 REG_DDMA_CH0CTRL_8822C */
+#define BIT_DDMACH0_OWN_8822C BIT(31)
+#define BIT_DDMACH0_IDMEM_ERR_8822C BIT(30)
+#define BIT_DDMACH0_CHKSUM_EN_8822C BIT(29)
+#define BIT_DDMACH0_DA_W_DISABLE_8822C BIT(28)
+#define BIT_DDMACH0_CHKSUM_STS_8822C BIT(27)
+#define BIT_DDMACH0_DDMA_MODE_8822C BIT(26)
+#define BIT_DDMACH0_RESET_CHKSUM_STS_8822C BIT(25)
+#define BIT_DDMACH0_CHKSUM_CONT_8822C BIT(24)
+
+#define BIT_SHIFT_DDMACH0_DLEN_8822C 0
+#define BIT_MASK_DDMACH0_DLEN_8822C 0x3ffff
+#define BIT_DDMACH0_DLEN_8822C(x) \
+ (((x) & BIT_MASK_DDMACH0_DLEN_8822C) << BIT_SHIFT_DDMACH0_DLEN_8822C)
+#define BITS_DDMACH0_DLEN_8822C \
+ (BIT_MASK_DDMACH0_DLEN_8822C << BIT_SHIFT_DDMACH0_DLEN_8822C)
+#define BIT_CLEAR_DDMACH0_DLEN_8822C(x) ((x) & (~BITS_DDMACH0_DLEN_8822C))
+#define BIT_GET_DDMACH0_DLEN_8822C(x) \
+ (((x) >> BIT_SHIFT_DDMACH0_DLEN_8822C) & BIT_MASK_DDMACH0_DLEN_8822C)
+#define BIT_SET_DDMACH0_DLEN_8822C(x, v) \
+ (BIT_CLEAR_DDMACH0_DLEN_8822C(x) | BIT_DDMACH0_DLEN_8822C(v))
+
+/* 2 REG_DDMA_CH1SA_8822C */
+
+#define BIT_SHIFT_DDMACH1_SA_8822C 0
+#define BIT_MASK_DDMACH1_SA_8822C 0xffffffffL
+#define BIT_DDMACH1_SA_8822C(x) \
+ (((x) & BIT_MASK_DDMACH1_SA_8822C) << BIT_SHIFT_DDMACH1_SA_8822C)
+#define BITS_DDMACH1_SA_8822C \
+ (BIT_MASK_DDMACH1_SA_8822C << BIT_SHIFT_DDMACH1_SA_8822C)
+#define BIT_CLEAR_DDMACH1_SA_8822C(x) ((x) & (~BITS_DDMACH1_SA_8822C))
+#define BIT_GET_DDMACH1_SA_8822C(x) \
+ (((x) >> BIT_SHIFT_DDMACH1_SA_8822C) & BIT_MASK_DDMACH1_SA_8822C)
+#define BIT_SET_DDMACH1_SA_8822C(x, v) \
+ (BIT_CLEAR_DDMACH1_SA_8822C(x) | BIT_DDMACH1_SA_8822C(v))
+
+/* 2 REG_DDMA_CH1DA_8822C */
+
+#define BIT_SHIFT_DDMACH1_DA_8822C 0
+#define BIT_MASK_DDMACH1_DA_8822C 0xffffffffL
+#define BIT_DDMACH1_DA_8822C(x) \
+ (((x) & BIT_MASK_DDMACH1_DA_8822C) << BIT_SHIFT_DDMACH1_DA_8822C)
+#define BITS_DDMACH1_DA_8822C \
+ (BIT_MASK_DDMACH1_DA_8822C << BIT_SHIFT_DDMACH1_DA_8822C)
+#define BIT_CLEAR_DDMACH1_DA_8822C(x) ((x) & (~BITS_DDMACH1_DA_8822C))
+#define BIT_GET_DDMACH1_DA_8822C(x) \
+ (((x) >> BIT_SHIFT_DDMACH1_DA_8822C) & BIT_MASK_DDMACH1_DA_8822C)
+#define BIT_SET_DDMACH1_DA_8822C(x, v) \
+ (BIT_CLEAR_DDMACH1_DA_8822C(x) | BIT_DDMACH1_DA_8822C(v))
+
+/* 2 REG_DDMA_CH1CTRL_8822C */
+#define BIT_DDMACH1_OWN_8822C BIT(31)
+#define BIT_DDMACH1_IDMEM_ERR_8822C BIT(30)
+#define BIT_DDMACH1_CHKSUM_EN_8822C BIT(29)
+#define BIT_DDMACH1_DA_W_DISABLE_8822C BIT(28)
+#define BIT_DDMACH1_CHKSUM_STS_8822C BIT(27)
+#define BIT_DDMACH1_DDMA_MODE_8822C BIT(26)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_DDMACH1_DLEN_8822C 0
+#define BIT_MASK_DDMACH1_DLEN_8822C 0x3ffff
+#define BIT_DDMACH1_DLEN_8822C(x) \
+ (((x) & BIT_MASK_DDMACH1_DLEN_8822C) << BIT_SHIFT_DDMACH1_DLEN_8822C)
+#define BITS_DDMACH1_DLEN_8822C \
+ (BIT_MASK_DDMACH1_DLEN_8822C << BIT_SHIFT_DDMACH1_DLEN_8822C)
+#define BIT_CLEAR_DDMACH1_DLEN_8822C(x) ((x) & (~BITS_DDMACH1_DLEN_8822C))
+#define BIT_GET_DDMACH1_DLEN_8822C(x) \
+ (((x) >> BIT_SHIFT_DDMACH1_DLEN_8822C) & BIT_MASK_DDMACH1_DLEN_8822C)
+#define BIT_SET_DDMACH1_DLEN_8822C(x, v) \
+ (BIT_CLEAR_DDMACH1_DLEN_8822C(x) | BIT_DDMACH1_DLEN_8822C(v))
+
+/* 2 REG_DDMA_CH2SA_8822C */
+
+#define BIT_SHIFT_DDMACH2_SA_8822C 0
+#define BIT_MASK_DDMACH2_SA_8822C 0xffffffffL
+#define BIT_DDMACH2_SA_8822C(x) \
+ (((x) & BIT_MASK_DDMACH2_SA_8822C) << BIT_SHIFT_DDMACH2_SA_8822C)
+#define BITS_DDMACH2_SA_8822C \
+ (BIT_MASK_DDMACH2_SA_8822C << BIT_SHIFT_DDMACH2_SA_8822C)
+#define BIT_CLEAR_DDMACH2_SA_8822C(x) ((x) & (~BITS_DDMACH2_SA_8822C))
+#define BIT_GET_DDMACH2_SA_8822C(x) \
+ (((x) >> BIT_SHIFT_DDMACH2_SA_8822C) & BIT_MASK_DDMACH2_SA_8822C)
+#define BIT_SET_DDMACH2_SA_8822C(x, v) \
+ (BIT_CLEAR_DDMACH2_SA_8822C(x) | BIT_DDMACH2_SA_8822C(v))
+
+/* 2 REG_DDMA_CH2DA_8822C */
+
+#define BIT_SHIFT_DDMACH2_DA_8822C 0
+#define BIT_MASK_DDMACH2_DA_8822C 0xffffffffL
+#define BIT_DDMACH2_DA_8822C(x) \
+ (((x) & BIT_MASK_DDMACH2_DA_8822C) << BIT_SHIFT_DDMACH2_DA_8822C)
+#define BITS_DDMACH2_DA_8822C \
+ (BIT_MASK_DDMACH2_DA_8822C << BIT_SHIFT_DDMACH2_DA_8822C)
+#define BIT_CLEAR_DDMACH2_DA_8822C(x) ((x) & (~BITS_DDMACH2_DA_8822C))
+#define BIT_GET_DDMACH2_DA_8822C(x) \
+ (((x) >> BIT_SHIFT_DDMACH2_DA_8822C) & BIT_MASK_DDMACH2_DA_8822C)
+#define BIT_SET_DDMACH2_DA_8822C(x, v) \
+ (BIT_CLEAR_DDMACH2_DA_8822C(x) | BIT_DDMACH2_DA_8822C(v))
+
+/* 2 REG_DDMA_CH2CTRL_8822C */
+#define BIT_DDMACH2_OWN_8822C BIT(31)
+#define BIT_DDMACH2_IDMEM_ERR_8822C BIT(30)
+#define BIT_DDMACH2_CHKSUM_EN_8822C BIT(29)
+#define BIT_DDMACH2_DA_W_DISABLE_8822C BIT(28)
+#define BIT_DDMACH2_CHKSUM_STS_8822C BIT(27)
+#define BIT_DDMACH2_DDMA_MODE_8822C BIT(26)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_DDMACH2_DLEN_8822C 0
+#define BIT_MASK_DDMACH2_DLEN_8822C 0x3ffff
+#define BIT_DDMACH2_DLEN_8822C(x) \
+ (((x) & BIT_MASK_DDMACH2_DLEN_8822C) << BIT_SHIFT_DDMACH2_DLEN_8822C)
+#define BITS_DDMACH2_DLEN_8822C \
+ (BIT_MASK_DDMACH2_DLEN_8822C << BIT_SHIFT_DDMACH2_DLEN_8822C)
+#define BIT_CLEAR_DDMACH2_DLEN_8822C(x) ((x) & (~BITS_DDMACH2_DLEN_8822C))
+#define BIT_GET_DDMACH2_DLEN_8822C(x) \
+ (((x) >> BIT_SHIFT_DDMACH2_DLEN_8822C) & BIT_MASK_DDMACH2_DLEN_8822C)
+#define BIT_SET_DDMACH2_DLEN_8822C(x, v) \
+ (BIT_CLEAR_DDMACH2_DLEN_8822C(x) | BIT_DDMACH2_DLEN_8822C(v))
+
+/* 2 REG_DDMA_CH3SA_8822C */
+
+#define BIT_SHIFT_DDMACH3_SA_8822C 0
+#define BIT_MASK_DDMACH3_SA_8822C 0xffffffffL
+#define BIT_DDMACH3_SA_8822C(x) \
+ (((x) & BIT_MASK_DDMACH3_SA_8822C) << BIT_SHIFT_DDMACH3_SA_8822C)
+#define BITS_DDMACH3_SA_8822C \
+ (BIT_MASK_DDMACH3_SA_8822C << BIT_SHIFT_DDMACH3_SA_8822C)
+#define BIT_CLEAR_DDMACH3_SA_8822C(x) ((x) & (~BITS_DDMACH3_SA_8822C))
+#define BIT_GET_DDMACH3_SA_8822C(x) \
+ (((x) >> BIT_SHIFT_DDMACH3_SA_8822C) & BIT_MASK_DDMACH3_SA_8822C)
+#define BIT_SET_DDMACH3_SA_8822C(x, v) \
+ (BIT_CLEAR_DDMACH3_SA_8822C(x) | BIT_DDMACH3_SA_8822C(v))
+
+/* 2 REG_DDMA_CH3DA_8822C */
+
+#define BIT_SHIFT_DDMACH3_DA_8822C 0
+#define BIT_MASK_DDMACH3_DA_8822C 0xffffffffL
+#define BIT_DDMACH3_DA_8822C(x) \
+ (((x) & BIT_MASK_DDMACH3_DA_8822C) << BIT_SHIFT_DDMACH3_DA_8822C)
+#define BITS_DDMACH3_DA_8822C \
+ (BIT_MASK_DDMACH3_DA_8822C << BIT_SHIFT_DDMACH3_DA_8822C)
+#define BIT_CLEAR_DDMACH3_DA_8822C(x) ((x) & (~BITS_DDMACH3_DA_8822C))
+#define BIT_GET_DDMACH3_DA_8822C(x) \
+ (((x) >> BIT_SHIFT_DDMACH3_DA_8822C) & BIT_MASK_DDMACH3_DA_8822C)
+#define BIT_SET_DDMACH3_DA_8822C(x, v) \
+ (BIT_CLEAR_DDMACH3_DA_8822C(x) | BIT_DDMACH3_DA_8822C(v))
+
+/* 2 REG_DDMA_CH3CTRL_8822C */
+#define BIT_DDMACH3_OWN_8822C BIT(31)
+#define BIT_DDMACH3_IDMEM_ERR_8822C BIT(30)
+#define BIT_DDMACH3_CHKSUM_EN_8822C BIT(29)
+#define BIT_DDMACH3_DA_W_DISABLE_8822C BIT(28)
+#define BIT_DDMACH3_CHKSUM_STS_8822C BIT(27)
+#define BIT_DDMACH3_DDMA_MODE_8822C BIT(26)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_DDMACH3_DLEN_8822C 0
+#define BIT_MASK_DDMACH3_DLEN_8822C 0x3ffff
+#define BIT_DDMACH3_DLEN_8822C(x) \
+ (((x) & BIT_MASK_DDMACH3_DLEN_8822C) << BIT_SHIFT_DDMACH3_DLEN_8822C)
+#define BITS_DDMACH3_DLEN_8822C \
+ (BIT_MASK_DDMACH3_DLEN_8822C << BIT_SHIFT_DDMACH3_DLEN_8822C)
+#define BIT_CLEAR_DDMACH3_DLEN_8822C(x) ((x) & (~BITS_DDMACH3_DLEN_8822C))
+#define BIT_GET_DDMACH3_DLEN_8822C(x) \
+ (((x) >> BIT_SHIFT_DDMACH3_DLEN_8822C) & BIT_MASK_DDMACH3_DLEN_8822C)
+#define BIT_SET_DDMACH3_DLEN_8822C(x, v) \
+ (BIT_CLEAR_DDMACH3_DLEN_8822C(x) | BIT_DDMACH3_DLEN_8822C(v))
+
+/* 2 REG_DDMA_CH4SA_8822C */
+
+#define BIT_SHIFT_DDMACH4_SA_8822C 0
+#define BIT_MASK_DDMACH4_SA_8822C 0xffffffffL
+#define BIT_DDMACH4_SA_8822C(x) \
+ (((x) & BIT_MASK_DDMACH4_SA_8822C) << BIT_SHIFT_DDMACH4_SA_8822C)
+#define BITS_DDMACH4_SA_8822C \
+ (BIT_MASK_DDMACH4_SA_8822C << BIT_SHIFT_DDMACH4_SA_8822C)
+#define BIT_CLEAR_DDMACH4_SA_8822C(x) ((x) & (~BITS_DDMACH4_SA_8822C))
+#define BIT_GET_DDMACH4_SA_8822C(x) \
+ (((x) >> BIT_SHIFT_DDMACH4_SA_8822C) & BIT_MASK_DDMACH4_SA_8822C)
+#define BIT_SET_DDMACH4_SA_8822C(x, v) \
+ (BIT_CLEAR_DDMACH4_SA_8822C(x) | BIT_DDMACH4_SA_8822C(v))
+
+/* 2 REG_DDMA_CH4DA_8822C */
+
+#define BIT_SHIFT_DDMACH4_DA_8822C 0
+#define BIT_MASK_DDMACH4_DA_8822C 0xffffffffL
+#define BIT_DDMACH4_DA_8822C(x) \
+ (((x) & BIT_MASK_DDMACH4_DA_8822C) << BIT_SHIFT_DDMACH4_DA_8822C)
+#define BITS_DDMACH4_DA_8822C \
+ (BIT_MASK_DDMACH4_DA_8822C << BIT_SHIFT_DDMACH4_DA_8822C)
+#define BIT_CLEAR_DDMACH4_DA_8822C(x) ((x) & (~BITS_DDMACH4_DA_8822C))
+#define BIT_GET_DDMACH4_DA_8822C(x) \
+ (((x) >> BIT_SHIFT_DDMACH4_DA_8822C) & BIT_MASK_DDMACH4_DA_8822C)
+#define BIT_SET_DDMACH4_DA_8822C(x, v) \
+ (BIT_CLEAR_DDMACH4_DA_8822C(x) | BIT_DDMACH4_DA_8822C(v))
+
+/* 2 REG_DDMA_CH4CTRL_8822C */
+#define BIT_DDMACH4_OWN_8822C BIT(31)
+#define BIT_DDMACH4_IDMEM_ERR_8822C BIT(30)
+#define BIT_DDMACH4_CHKSUM_EN_8822C BIT(29)
+#define BIT_DDMACH4_DA_W_DISABLE_8822C BIT(28)
+#define BIT_DDMACH4_CHKSUM_STS_8822C BIT(27)
+#define BIT_DDMACH4_DDMA_MODE_8822C BIT(26)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_DDMACH4_DLEN_8822C 0
+#define BIT_MASK_DDMACH4_DLEN_8822C 0x3ffff
+#define BIT_DDMACH4_DLEN_8822C(x) \
+ (((x) & BIT_MASK_DDMACH4_DLEN_8822C) << BIT_SHIFT_DDMACH4_DLEN_8822C)
+#define BITS_DDMACH4_DLEN_8822C \
+ (BIT_MASK_DDMACH4_DLEN_8822C << BIT_SHIFT_DDMACH4_DLEN_8822C)
+#define BIT_CLEAR_DDMACH4_DLEN_8822C(x) ((x) & (~BITS_DDMACH4_DLEN_8822C))
+#define BIT_GET_DDMACH4_DLEN_8822C(x) \
+ (((x) >> BIT_SHIFT_DDMACH4_DLEN_8822C) & BIT_MASK_DDMACH4_DLEN_8822C)
+#define BIT_SET_DDMACH4_DLEN_8822C(x, v) \
+ (BIT_CLEAR_DDMACH4_DLEN_8822C(x) | BIT_DDMACH4_DLEN_8822C(v))
+
+/* 2 REG_DDMA_CH5SA_8822C */
+
+#define BIT_SHIFT_DDMACH5_SA_8822C 0
+#define BIT_MASK_DDMACH5_SA_8822C 0xffffffffL
+#define BIT_DDMACH5_SA_8822C(x) \
+ (((x) & BIT_MASK_DDMACH5_SA_8822C) << BIT_SHIFT_DDMACH5_SA_8822C)
+#define BITS_DDMACH5_SA_8822C \
+ (BIT_MASK_DDMACH5_SA_8822C << BIT_SHIFT_DDMACH5_SA_8822C)
+#define BIT_CLEAR_DDMACH5_SA_8822C(x) ((x) & (~BITS_DDMACH5_SA_8822C))
+#define BIT_GET_DDMACH5_SA_8822C(x) \
+ (((x) >> BIT_SHIFT_DDMACH5_SA_8822C) & BIT_MASK_DDMACH5_SA_8822C)
+#define BIT_SET_DDMACH5_SA_8822C(x, v) \
+ (BIT_CLEAR_DDMACH5_SA_8822C(x) | BIT_DDMACH5_SA_8822C(v))
+
+/* 2 REG_DDMA_CH5DA_8822C */
+
+#define BIT_SHIFT_DDMACH5_DA_8822C 0
+#define BIT_MASK_DDMACH5_DA_8822C 0xffffffffL
+#define BIT_DDMACH5_DA_8822C(x) \
+ (((x) & BIT_MASK_DDMACH5_DA_8822C) << BIT_SHIFT_DDMACH5_DA_8822C)
+#define BITS_DDMACH5_DA_8822C \
+ (BIT_MASK_DDMACH5_DA_8822C << BIT_SHIFT_DDMACH5_DA_8822C)
+#define BIT_CLEAR_DDMACH5_DA_8822C(x) ((x) & (~BITS_DDMACH5_DA_8822C))
+#define BIT_GET_DDMACH5_DA_8822C(x) \
+ (((x) >> BIT_SHIFT_DDMACH5_DA_8822C) & BIT_MASK_DDMACH5_DA_8822C)
+#define BIT_SET_DDMACH5_DA_8822C(x, v) \
+ (BIT_CLEAR_DDMACH5_DA_8822C(x) | BIT_DDMACH5_DA_8822C(v))
+
+/* 2 REG_DDMA_CH5CTRL_8822C */
+#define BIT_DDMACH5_OWN_8822C BIT(31)
+#define BIT_DDMACH5_IDMEM_ERR_8822C BIT(30)
+#define BIT_DDMACH5_CHKSUM_EN_8822C BIT(29)
+#define BIT_DDMACH5_DA_W_DISABLE_8822C BIT(28)
+#define BIT_DDMACH5_CHKSUM_STS_8822C BIT(27)
+#define BIT_DDMACH5_DDMA_MODE_8822C BIT(26)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_DDMACH5_DLEN_8822C 0
+#define BIT_MASK_DDMACH5_DLEN_8822C 0x3ffff
+#define BIT_DDMACH5_DLEN_8822C(x) \
+ (((x) & BIT_MASK_DDMACH5_DLEN_8822C) << BIT_SHIFT_DDMACH5_DLEN_8822C)
+#define BITS_DDMACH5_DLEN_8822C \
+ (BIT_MASK_DDMACH5_DLEN_8822C << BIT_SHIFT_DDMACH5_DLEN_8822C)
+#define BIT_CLEAR_DDMACH5_DLEN_8822C(x) ((x) & (~BITS_DDMACH5_DLEN_8822C))
+#define BIT_GET_DDMACH5_DLEN_8822C(x) \
+ (((x) >> BIT_SHIFT_DDMACH5_DLEN_8822C) & BIT_MASK_DDMACH5_DLEN_8822C)
+#define BIT_SET_DDMACH5_DLEN_8822C(x, v) \
+ (BIT_CLEAR_DDMACH5_DLEN_8822C(x) | BIT_DDMACH5_DLEN_8822C(v))
+
+/* 2 REG_DDMA_INT_MSK_8822C */
+#define BIT_DDMACH5_MSK_8822C BIT(5)
+#define BIT_DDMACH4_MSK_8822C BIT(4)
+#define BIT_DDMACH3_MSK_8822C BIT(3)
+#define BIT_DDMACH2_MSK_8822C BIT(2)
+#define BIT_DDMACH1_MSK_8822C BIT(1)
+#define BIT_DDMACH0_MSK_8822C BIT(0)
+
+/* 2 REG_DDMA_CHSTATUS_8822C */
+#define BIT_DDMACH5_BUSY_8822C BIT(5)
+#define BIT_DDMACH4_BUSY_8822C BIT(4)
+#define BIT_DDMACH3_BUSY_8822C BIT(3)
+#define BIT_DDMACH2_BUSY_8822C BIT(2)
+#define BIT_DDMACH1_BUSY_8822C BIT(1)
+#define BIT_DDMACH0_BUSY_8822C BIT(0)
+
+/* 2 REG_DDMA_CHKSUM_8822C */
+
+#define BIT_SHIFT_IDDMA0_CHKSUM_8822C 0
+#define BIT_MASK_IDDMA0_CHKSUM_8822C 0xffff
+#define BIT_IDDMA0_CHKSUM_8822C(x) \
+ (((x) & BIT_MASK_IDDMA0_CHKSUM_8822C) << BIT_SHIFT_IDDMA0_CHKSUM_8822C)
+#define BITS_IDDMA0_CHKSUM_8822C \
+ (BIT_MASK_IDDMA0_CHKSUM_8822C << BIT_SHIFT_IDDMA0_CHKSUM_8822C)
+#define BIT_CLEAR_IDDMA0_CHKSUM_8822C(x) ((x) & (~BITS_IDDMA0_CHKSUM_8822C))
+#define BIT_GET_IDDMA0_CHKSUM_8822C(x) \
+ (((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8822C) & BIT_MASK_IDDMA0_CHKSUM_8822C)
+#define BIT_SET_IDDMA0_CHKSUM_8822C(x, v) \
+ (BIT_CLEAR_IDDMA0_CHKSUM_8822C(x) | BIT_IDDMA0_CHKSUM_8822C(v))
+
+/* 2 REG_DDMA_MONITOR_8822C */
+#define BIT_IDDMA0_PERMU_UNDERFLOW_8822C BIT(14)
+#define BIT_IDDMA0_FIFO_UNDERFLOW_8822C BIT(13)
+#define BIT_IDDMA0_FIFO_OVERFLOW_8822C BIT(12)
+#define BIT_CH5_ERR_8822C BIT(5)
+#define BIT_CH4_ERR_8822C BIT(4)
+#define BIT_CH3_ERR_8822C BIT(3)
+#define BIT_CH2_ERR_8822C BIT(2)
+#define BIT_CH1_ERR_8822C BIT(1)
+#define BIT_CH0_ERR_8822C BIT(0)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_PCIE_CTRL_8822C */
+#define BIT_PCIEIO_PERSTB_SEL_8822C BIT(31)
+
+#define BIT_SHIFT_PCIE_MAX_RXDMA_8822C 28
+#define BIT_MASK_PCIE_MAX_RXDMA_8822C 0x7
+#define BIT_PCIE_MAX_RXDMA_8822C(x) \
+ (((x) & BIT_MASK_PCIE_MAX_RXDMA_8822C) \
+ << BIT_SHIFT_PCIE_MAX_RXDMA_8822C)
+#define BITS_PCIE_MAX_RXDMA_8822C \
+ (BIT_MASK_PCIE_MAX_RXDMA_8822C << BIT_SHIFT_PCIE_MAX_RXDMA_8822C)
+#define BIT_CLEAR_PCIE_MAX_RXDMA_8822C(x) ((x) & (~BITS_PCIE_MAX_RXDMA_8822C))
+#define BIT_GET_PCIE_MAX_RXDMA_8822C(x) \
+ (((x) >> BIT_SHIFT_PCIE_MAX_RXDMA_8822C) & \
+ BIT_MASK_PCIE_MAX_RXDMA_8822C)
+#define BIT_SET_PCIE_MAX_RXDMA_8822C(x, v) \
+ (BIT_CLEAR_PCIE_MAX_RXDMA_8822C(x) | BIT_PCIE_MAX_RXDMA_8822C(v))
+
+#define BIT_SHIFT_PCIE_MAX_TXDMA_8822C 24
+#define BIT_MASK_PCIE_MAX_TXDMA_8822C 0x7
+#define BIT_PCIE_MAX_TXDMA_8822C(x) \
+ (((x) & BIT_MASK_PCIE_MAX_TXDMA_8822C) \
+ << BIT_SHIFT_PCIE_MAX_TXDMA_8822C)
+#define BITS_PCIE_MAX_TXDMA_8822C \
+ (BIT_MASK_PCIE_MAX_TXDMA_8822C << BIT_SHIFT_PCIE_MAX_TXDMA_8822C)
+#define BIT_CLEAR_PCIE_MAX_TXDMA_8822C(x) ((x) & (~BITS_PCIE_MAX_TXDMA_8822C))
+#define BIT_GET_PCIE_MAX_TXDMA_8822C(x) \
+ (((x) >> BIT_SHIFT_PCIE_MAX_TXDMA_8822C) & \
+ BIT_MASK_PCIE_MAX_TXDMA_8822C)
+#define BIT_SET_PCIE_MAX_TXDMA_8822C(x, v) \
+ (BIT_CLEAR_PCIE_MAX_TXDMA_8822C(x) | BIT_PCIE_MAX_TXDMA_8822C(v))
+
+#define BIT_EN_CPL_TIMEOUT_PS_8822C BIT(22)
+#define BIT_REG_TXDMA_FAIL_PS_8822C BIT(21)
+#define BIT_PCIE_RST_TRXDMA_INTF_8822C BIT(20)
+#define BIT_EN_HWENTR_L1_8822C BIT(19)
+#define BIT_EN_ADV_CLKGATE_8822C BIT(18)
+#define BIT_PCIE_EN_SWENT_L23_8822C BIT(17)
+#define BIT_PCIE_EN_HWEXT_L1_8822C BIT(16)
+#define BIT_RX_CLOSE_EN_8822C BIT(15)
+#define BIT_STOP_BCNQ_8822C BIT(14)
+#define BIT_STOP_MGQ_8822C BIT(13)
+#define BIT_STOP_VOQ_8822C BIT(12)
+#define BIT_STOP_VIQ_8822C BIT(11)
+#define BIT_STOP_BEQ_8822C BIT(10)
+#define BIT_STOP_BKQ_8822C BIT(9)
+#define BIT_STOP_RXQ_8822C BIT(8)
+#define BIT_STOP_HI7Q_8822C BIT(7)
+#define BIT_STOP_HI6Q_8822C BIT(6)
+#define BIT_STOP_HI5Q_8822C BIT(5)
+#define BIT_STOP_HI4Q_8822C BIT(4)
+#define BIT_STOP_HI3Q_8822C BIT(3)
+#define BIT_STOP_HI2Q_8822C BIT(2)
+#define BIT_STOP_HI1Q_8822C BIT(1)
+#define BIT_STOP_HI0Q_8822C BIT(0)
+
+/* 2 REG_INT_MIG_8822C */
+
+#define BIT_SHIFT_TRXCOUNTER_MATCH_8822C 24
+#define BIT_MASK_TRXCOUNTER_MATCH_8822C 0xff
+#define BIT_TRXCOUNTER_MATCH_8822C(x) \
+ (((x) & BIT_MASK_TRXCOUNTER_MATCH_8822C) \
+ << BIT_SHIFT_TRXCOUNTER_MATCH_8822C)
+#define BITS_TRXCOUNTER_MATCH_8822C \
+ (BIT_MASK_TRXCOUNTER_MATCH_8822C << BIT_SHIFT_TRXCOUNTER_MATCH_8822C)
+#define BIT_CLEAR_TRXCOUNTER_MATCH_8822C(x) \
+ ((x) & (~BITS_TRXCOUNTER_MATCH_8822C))
+#define BIT_GET_TRXCOUNTER_MATCH_8822C(x) \
+ (((x) >> BIT_SHIFT_TRXCOUNTER_MATCH_8822C) & \
+ BIT_MASK_TRXCOUNTER_MATCH_8822C)
+#define BIT_SET_TRXCOUNTER_MATCH_8822C(x, v) \
+ (BIT_CLEAR_TRXCOUNTER_MATCH_8822C(x) | BIT_TRXCOUNTER_MATCH_8822C(v))
+
+#define BIT_SHIFT_TRXTIMER_MATCH_8822C 16
+#define BIT_MASK_TRXTIMER_MATCH_8822C 0xff
+#define BIT_TRXTIMER_MATCH_8822C(x) \
+ (((x) & BIT_MASK_TRXTIMER_MATCH_8822C) \
+ << BIT_SHIFT_TRXTIMER_MATCH_8822C)
+#define BITS_TRXTIMER_MATCH_8822C \
+ (BIT_MASK_TRXTIMER_MATCH_8822C << BIT_SHIFT_TRXTIMER_MATCH_8822C)
+#define BIT_CLEAR_TRXTIMER_MATCH_8822C(x) ((x) & (~BITS_TRXTIMER_MATCH_8822C))
+#define BIT_GET_TRXTIMER_MATCH_8822C(x) \
+ (((x) >> BIT_SHIFT_TRXTIMER_MATCH_8822C) & \
+ BIT_MASK_TRXTIMER_MATCH_8822C)
+#define BIT_SET_TRXTIMER_MATCH_8822C(x, v) \
+ (BIT_CLEAR_TRXTIMER_MATCH_8822C(x) | BIT_TRXTIMER_MATCH_8822C(v))
+
+#define BIT_SHIFT_TRXTIMER_UNIT_8822C 0
+#define BIT_MASK_TRXTIMER_UNIT_8822C 0x3
+#define BIT_TRXTIMER_UNIT_8822C(x) \
+ (((x) & BIT_MASK_TRXTIMER_UNIT_8822C) << BIT_SHIFT_TRXTIMER_UNIT_8822C)
+#define BITS_TRXTIMER_UNIT_8822C \
+ (BIT_MASK_TRXTIMER_UNIT_8822C << BIT_SHIFT_TRXTIMER_UNIT_8822C)
+#define BIT_CLEAR_TRXTIMER_UNIT_8822C(x) ((x) & (~BITS_TRXTIMER_UNIT_8822C))
+#define BIT_GET_TRXTIMER_UNIT_8822C(x) \
+ (((x) >> BIT_SHIFT_TRXTIMER_UNIT_8822C) & BIT_MASK_TRXTIMER_UNIT_8822C)
+#define BIT_SET_TRXTIMER_UNIT_8822C(x, v) \
+ (BIT_CLEAR_TRXTIMER_UNIT_8822C(x) | BIT_TRXTIMER_UNIT_8822C(v))
+
+/* 2 REG_BCNQ_TXBD_DESA_8822C */
+
+#define BIT_SHIFT_BCNQ_TXBD_DESA_8822C 0
+#define BIT_MASK_BCNQ_TXBD_DESA_8822C 0xffffffffffffffffL
+#define BIT_BCNQ_TXBD_DESA_8822C(x) \
+ (((x) & BIT_MASK_BCNQ_TXBD_DESA_8822C) \
+ << BIT_SHIFT_BCNQ_TXBD_DESA_8822C)
+#define BITS_BCNQ_TXBD_DESA_8822C \
+ (BIT_MASK_BCNQ_TXBD_DESA_8822C << BIT_SHIFT_BCNQ_TXBD_DESA_8822C)
+#define BIT_CLEAR_BCNQ_TXBD_DESA_8822C(x) ((x) & (~BITS_BCNQ_TXBD_DESA_8822C))
+#define BIT_GET_BCNQ_TXBD_DESA_8822C(x) \
+ (((x) >> BIT_SHIFT_BCNQ_TXBD_DESA_8822C) & \
+ BIT_MASK_BCNQ_TXBD_DESA_8822C)
+#define BIT_SET_BCNQ_TXBD_DESA_8822C(x, v) \
+ (BIT_CLEAR_BCNQ_TXBD_DESA_8822C(x) | BIT_BCNQ_TXBD_DESA_8822C(v))
+
+/* 2 REG_MGQ_TXBD_DESA_8822C */
+
+#define BIT_SHIFT_MGQ_TXBD_DESA_8822C 0
+#define BIT_MASK_MGQ_TXBD_DESA_8822C 0xffffffffffffffffL
+#define BIT_MGQ_TXBD_DESA_8822C(x) \
+ (((x) & BIT_MASK_MGQ_TXBD_DESA_8822C) << BIT_SHIFT_MGQ_TXBD_DESA_8822C)
+#define BITS_MGQ_TXBD_DESA_8822C \
+ (BIT_MASK_MGQ_TXBD_DESA_8822C << BIT_SHIFT_MGQ_TXBD_DESA_8822C)
+#define BIT_CLEAR_MGQ_TXBD_DESA_8822C(x) ((x) & (~BITS_MGQ_TXBD_DESA_8822C))
+#define BIT_GET_MGQ_TXBD_DESA_8822C(x) \
+ (((x) >> BIT_SHIFT_MGQ_TXBD_DESA_8822C) & BIT_MASK_MGQ_TXBD_DESA_8822C)
+#define BIT_SET_MGQ_TXBD_DESA_8822C(x, v) \
+ (BIT_CLEAR_MGQ_TXBD_DESA_8822C(x) | BIT_MGQ_TXBD_DESA_8822C(v))
+
+/* 2 REG_VOQ_TXBD_DESA_8822C */
+
+#define BIT_SHIFT_VOQ_TXBD_DESA_8822C 0
+#define BIT_MASK_VOQ_TXBD_DESA_8822C 0xffffffffffffffffL
+#define BIT_VOQ_TXBD_DESA_8822C(x) \
+ (((x) & BIT_MASK_VOQ_TXBD_DESA_8822C) << BIT_SHIFT_VOQ_TXBD_DESA_8822C)
+#define BITS_VOQ_TXBD_DESA_8822C \
+ (BIT_MASK_VOQ_TXBD_DESA_8822C << BIT_SHIFT_VOQ_TXBD_DESA_8822C)
+#define BIT_CLEAR_VOQ_TXBD_DESA_8822C(x) ((x) & (~BITS_VOQ_TXBD_DESA_8822C))
+#define BIT_GET_VOQ_TXBD_DESA_8822C(x) \
+ (((x) >> BIT_SHIFT_VOQ_TXBD_DESA_8822C) & BIT_MASK_VOQ_TXBD_DESA_8822C)
+#define BIT_SET_VOQ_TXBD_DESA_8822C(x, v) \
+ (BIT_CLEAR_VOQ_TXBD_DESA_8822C(x) | BIT_VOQ_TXBD_DESA_8822C(v))
+
+/* 2 REG_VIQ_TXBD_DESA_8822C */
+
+#define BIT_SHIFT_VIQ_TXBD_DESA_8822C 0
+#define BIT_MASK_VIQ_TXBD_DESA_8822C 0xffffffffffffffffL
+#define BIT_VIQ_TXBD_DESA_8822C(x) \
+ (((x) & BIT_MASK_VIQ_TXBD_DESA_8822C) << BIT_SHIFT_VIQ_TXBD_DESA_8822C)
+#define BITS_VIQ_TXBD_DESA_8822C \
+ (BIT_MASK_VIQ_TXBD_DESA_8822C << BIT_SHIFT_VIQ_TXBD_DESA_8822C)
+#define BIT_CLEAR_VIQ_TXBD_DESA_8822C(x) ((x) & (~BITS_VIQ_TXBD_DESA_8822C))
+#define BIT_GET_VIQ_TXBD_DESA_8822C(x) \
+ (((x) >> BIT_SHIFT_VIQ_TXBD_DESA_8822C) & BIT_MASK_VIQ_TXBD_DESA_8822C)
+#define BIT_SET_VIQ_TXBD_DESA_8822C(x, v) \
+ (BIT_CLEAR_VIQ_TXBD_DESA_8822C(x) | BIT_VIQ_TXBD_DESA_8822C(v))
+
+/* 2 REG_BEQ_TXBD_DESA_8822C */
+
+#define BIT_SHIFT_BEQ_TXBD_DESA_8822C 0
+#define BIT_MASK_BEQ_TXBD_DESA_8822C 0xffffffffffffffffL
+#define BIT_BEQ_TXBD_DESA_8822C(x) \
+ (((x) & BIT_MASK_BEQ_TXBD_DESA_8822C) << BIT_SHIFT_BEQ_TXBD_DESA_8822C)
+#define BITS_BEQ_TXBD_DESA_8822C \
+ (BIT_MASK_BEQ_TXBD_DESA_8822C << BIT_SHIFT_BEQ_TXBD_DESA_8822C)
+#define BIT_CLEAR_BEQ_TXBD_DESA_8822C(x) ((x) & (~BITS_BEQ_TXBD_DESA_8822C))
+#define BIT_GET_BEQ_TXBD_DESA_8822C(x) \
+ (((x) >> BIT_SHIFT_BEQ_TXBD_DESA_8822C) & BIT_MASK_BEQ_TXBD_DESA_8822C)
+#define BIT_SET_BEQ_TXBD_DESA_8822C(x, v) \
+ (BIT_CLEAR_BEQ_TXBD_DESA_8822C(x) | BIT_BEQ_TXBD_DESA_8822C(v))
+
+/* 2 REG_BKQ_TXBD_DESA_8822C */
+
+#define BIT_SHIFT_BKQ_TXBD_DESA_8822C 0
+#define BIT_MASK_BKQ_TXBD_DESA_8822C 0xffffffffffffffffL
+#define BIT_BKQ_TXBD_DESA_8822C(x) \
+ (((x) & BIT_MASK_BKQ_TXBD_DESA_8822C) << BIT_SHIFT_BKQ_TXBD_DESA_8822C)
+#define BITS_BKQ_TXBD_DESA_8822C \
+ (BIT_MASK_BKQ_TXBD_DESA_8822C << BIT_SHIFT_BKQ_TXBD_DESA_8822C)
+#define BIT_CLEAR_BKQ_TXBD_DESA_8822C(x) ((x) & (~BITS_BKQ_TXBD_DESA_8822C))
+#define BIT_GET_BKQ_TXBD_DESA_8822C(x) \
+ (((x) >> BIT_SHIFT_BKQ_TXBD_DESA_8822C) & BIT_MASK_BKQ_TXBD_DESA_8822C)
+#define BIT_SET_BKQ_TXBD_DESA_8822C(x, v) \
+ (BIT_CLEAR_BKQ_TXBD_DESA_8822C(x) | BIT_BKQ_TXBD_DESA_8822C(v))
+
+/* 2 REG_RXQ_RXBD_DESA_8822C */
+
+#define BIT_SHIFT_RXQ_RXBD_DESA_8822C 0
+#define BIT_MASK_RXQ_RXBD_DESA_8822C 0xffffffffffffffffL
+#define BIT_RXQ_RXBD_DESA_8822C(x) \
+ (((x) & BIT_MASK_RXQ_RXBD_DESA_8822C) << BIT_SHIFT_RXQ_RXBD_DESA_8822C)
+#define BITS_RXQ_RXBD_DESA_8822C \
+ (BIT_MASK_RXQ_RXBD_DESA_8822C << BIT_SHIFT_RXQ_RXBD_DESA_8822C)
+#define BIT_CLEAR_RXQ_RXBD_DESA_8822C(x) ((x) & (~BITS_RXQ_RXBD_DESA_8822C))
+#define BIT_GET_RXQ_RXBD_DESA_8822C(x) \
+ (((x) >> BIT_SHIFT_RXQ_RXBD_DESA_8822C) & BIT_MASK_RXQ_RXBD_DESA_8822C)
+#define BIT_SET_RXQ_RXBD_DESA_8822C(x, v) \
+ (BIT_CLEAR_RXQ_RXBD_DESA_8822C(x) | BIT_RXQ_RXBD_DESA_8822C(v))
+
+/* 2 REG_HI0Q_TXBD_DESA_8822C */
+
+#define BIT_SHIFT_HI0Q_TXBD_DESA_8822C 0
+#define BIT_MASK_HI0Q_TXBD_DESA_8822C 0xffffffffffffffffL
+#define BIT_HI0Q_TXBD_DESA_8822C(x) \
+ (((x) & BIT_MASK_HI0Q_TXBD_DESA_8822C) \
+ << BIT_SHIFT_HI0Q_TXBD_DESA_8822C)
+#define BITS_HI0Q_TXBD_DESA_8822C \
+ (BIT_MASK_HI0Q_TXBD_DESA_8822C << BIT_SHIFT_HI0Q_TXBD_DESA_8822C)
+#define BIT_CLEAR_HI0Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI0Q_TXBD_DESA_8822C))
+#define BIT_GET_HI0Q_TXBD_DESA_8822C(x) \
+ (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_8822C) & \
+ BIT_MASK_HI0Q_TXBD_DESA_8822C)
+#define BIT_SET_HI0Q_TXBD_DESA_8822C(x, v) \
+ (BIT_CLEAR_HI0Q_TXBD_DESA_8822C(x) | BIT_HI0Q_TXBD_DESA_8822C(v))
+
+/* 2 REG_HI1Q_TXBD_DESA_8822C */
+
+#define BIT_SHIFT_HI1Q_TXBD_DESA_8822C 0
+#define BIT_MASK_HI1Q_TXBD_DESA_8822C 0xffffffffffffffffL
+#define BIT_HI1Q_TXBD_DESA_8822C(x) \
+ (((x) & BIT_MASK_HI1Q_TXBD_DESA_8822C) \
+ << BIT_SHIFT_HI1Q_TXBD_DESA_8822C)
+#define BITS_HI1Q_TXBD_DESA_8822C \
+ (BIT_MASK_HI1Q_TXBD_DESA_8822C << BIT_SHIFT_HI1Q_TXBD_DESA_8822C)
+#define BIT_CLEAR_HI1Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI1Q_TXBD_DESA_8822C))
+#define BIT_GET_HI1Q_TXBD_DESA_8822C(x) \
+ (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_8822C) & \
+ BIT_MASK_HI1Q_TXBD_DESA_8822C)
+#define BIT_SET_HI1Q_TXBD_DESA_8822C(x, v) \
+ (BIT_CLEAR_HI1Q_TXBD_DESA_8822C(x) | BIT_HI1Q_TXBD_DESA_8822C(v))
+
+/* 2 REG_HI2Q_TXBD_DESA_8822C */
+
+#define BIT_SHIFT_HI2Q_TXBD_DESA_8822C 0
+#define BIT_MASK_HI2Q_TXBD_DESA_8822C 0xffffffffffffffffL
+#define BIT_HI2Q_TXBD_DESA_8822C(x) \
+ (((x) & BIT_MASK_HI2Q_TXBD_DESA_8822C) \
+ << BIT_SHIFT_HI2Q_TXBD_DESA_8822C)
+#define BITS_HI2Q_TXBD_DESA_8822C \
+ (BIT_MASK_HI2Q_TXBD_DESA_8822C << BIT_SHIFT_HI2Q_TXBD_DESA_8822C)
+#define BIT_CLEAR_HI2Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI2Q_TXBD_DESA_8822C))
+#define BIT_GET_HI2Q_TXBD_DESA_8822C(x) \
+ (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_8822C) & \
+ BIT_MASK_HI2Q_TXBD_DESA_8822C)
+#define BIT_SET_HI2Q_TXBD_DESA_8822C(x, v) \
+ (BIT_CLEAR_HI2Q_TXBD_DESA_8822C(x) | BIT_HI2Q_TXBD_DESA_8822C(v))
+
+/* 2 REG_HI3Q_TXBD_DESA_8822C */
+
+#define BIT_SHIFT_HI3Q_TXBD_DESA_8822C 0
+#define BIT_MASK_HI3Q_TXBD_DESA_8822C 0xffffffffffffffffL
+#define BIT_HI3Q_TXBD_DESA_8822C(x) \
+ (((x) & BIT_MASK_HI3Q_TXBD_DESA_8822C) \
+ << BIT_SHIFT_HI3Q_TXBD_DESA_8822C)
+#define BITS_HI3Q_TXBD_DESA_8822C \
+ (BIT_MASK_HI3Q_TXBD_DESA_8822C << BIT_SHIFT_HI3Q_TXBD_DESA_8822C)
+#define BIT_CLEAR_HI3Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI3Q_TXBD_DESA_8822C))
+#define BIT_GET_HI3Q_TXBD_DESA_8822C(x) \
+ (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_8822C) & \
+ BIT_MASK_HI3Q_TXBD_DESA_8822C)
+#define BIT_SET_HI3Q_TXBD_DESA_8822C(x, v) \
+ (BIT_CLEAR_HI3Q_TXBD_DESA_8822C(x) | BIT_HI3Q_TXBD_DESA_8822C(v))
+
+/* 2 REG_HI4Q_TXBD_DESA_8822C */
+
+#define BIT_SHIFT_HI4Q_TXBD_DESA_8822C 0
+#define BIT_MASK_HI4Q_TXBD_DESA_8822C 0xffffffffffffffffL
+#define BIT_HI4Q_TXBD_DESA_8822C(x) \
+ (((x) & BIT_MASK_HI4Q_TXBD_DESA_8822C) \
+ << BIT_SHIFT_HI4Q_TXBD_DESA_8822C)
+#define BITS_HI4Q_TXBD_DESA_8822C \
+ (BIT_MASK_HI4Q_TXBD_DESA_8822C << BIT_SHIFT_HI4Q_TXBD_DESA_8822C)
+#define BIT_CLEAR_HI4Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI4Q_TXBD_DESA_8822C))
+#define BIT_GET_HI4Q_TXBD_DESA_8822C(x) \
+ (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_8822C) & \
+ BIT_MASK_HI4Q_TXBD_DESA_8822C)
+#define BIT_SET_HI4Q_TXBD_DESA_8822C(x, v) \
+ (BIT_CLEAR_HI4Q_TXBD_DESA_8822C(x) | BIT_HI4Q_TXBD_DESA_8822C(v))
+
+/* 2 REG_HI5Q_TXBD_DESA_8822C */
+
+#define BIT_SHIFT_HI5Q_TXBD_DESA_8822C 0
+#define BIT_MASK_HI5Q_TXBD_DESA_8822C 0xffffffffffffffffL
+#define BIT_HI5Q_TXBD_DESA_8822C(x) \
+ (((x) & BIT_MASK_HI5Q_TXBD_DESA_8822C) \
+ << BIT_SHIFT_HI5Q_TXBD_DESA_8822C)
+#define BITS_HI5Q_TXBD_DESA_8822C \
+ (BIT_MASK_HI5Q_TXBD_DESA_8822C << BIT_SHIFT_HI5Q_TXBD_DESA_8822C)
+#define BIT_CLEAR_HI5Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI5Q_TXBD_DESA_8822C))
+#define BIT_GET_HI5Q_TXBD_DESA_8822C(x) \
+ (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_8822C) & \
+ BIT_MASK_HI5Q_TXBD_DESA_8822C)
+#define BIT_SET_HI5Q_TXBD_DESA_8822C(x, v) \
+ (BIT_CLEAR_HI5Q_TXBD_DESA_8822C(x) | BIT_HI5Q_TXBD_DESA_8822C(v))
+
+/* 2 REG_HI6Q_TXBD_DESA_8822C */
+
+#define BIT_SHIFT_HI6Q_TXBD_DESA_8822C 0
+#define BIT_MASK_HI6Q_TXBD_DESA_8822C 0xffffffffffffffffL
+#define BIT_HI6Q_TXBD_DESA_8822C(x) \
+ (((x) & BIT_MASK_HI6Q_TXBD_DESA_8822C) \
+ << BIT_SHIFT_HI6Q_TXBD_DESA_8822C)
+#define BITS_HI6Q_TXBD_DESA_8822C \
+ (BIT_MASK_HI6Q_TXBD_DESA_8822C << BIT_SHIFT_HI6Q_TXBD_DESA_8822C)
+#define BIT_CLEAR_HI6Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI6Q_TXBD_DESA_8822C))
+#define BIT_GET_HI6Q_TXBD_DESA_8822C(x) \
+ (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_8822C) & \
+ BIT_MASK_HI6Q_TXBD_DESA_8822C)
+#define BIT_SET_HI6Q_TXBD_DESA_8822C(x, v) \
+ (BIT_CLEAR_HI6Q_TXBD_DESA_8822C(x) | BIT_HI6Q_TXBD_DESA_8822C(v))
+
+/* 2 REG_HI7Q_TXBD_DESA_8822C */
+
+#define BIT_SHIFT_HI7Q_TXBD_DESA_8822C 0
+#define BIT_MASK_HI7Q_TXBD_DESA_8822C 0xffffffffffffffffL
+#define BIT_HI7Q_TXBD_DESA_8822C(x) \
+ (((x) & BIT_MASK_HI7Q_TXBD_DESA_8822C) \
+ << BIT_SHIFT_HI7Q_TXBD_DESA_8822C)
+#define BITS_HI7Q_TXBD_DESA_8822C \
+ (BIT_MASK_HI7Q_TXBD_DESA_8822C << BIT_SHIFT_HI7Q_TXBD_DESA_8822C)
+#define BIT_CLEAR_HI7Q_TXBD_DESA_8822C(x) ((x) & (~BITS_HI7Q_TXBD_DESA_8822C))
+#define BIT_GET_HI7Q_TXBD_DESA_8822C(x) \
+ (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_8822C) & \
+ BIT_MASK_HI7Q_TXBD_DESA_8822C)
+#define BIT_SET_HI7Q_TXBD_DESA_8822C(x, v) \
+ (BIT_CLEAR_HI7Q_TXBD_DESA_8822C(x) | BIT_HI7Q_TXBD_DESA_8822C(v))
+
+/* 2 REG_MGQ_TXBD_NUM_8822C */
+#define BIT_PCIE_MGQ_FLAG_8822C BIT(14)
+
+#define BIT_SHIFT_MGQ_DESC_MODE_8822C 12
+#define BIT_MASK_MGQ_DESC_MODE_8822C 0x3
+#define BIT_MGQ_DESC_MODE_8822C(x) \
+ (((x) & BIT_MASK_MGQ_DESC_MODE_8822C) << BIT_SHIFT_MGQ_DESC_MODE_8822C)
+#define BITS_MGQ_DESC_MODE_8822C \
+ (BIT_MASK_MGQ_DESC_MODE_8822C << BIT_SHIFT_MGQ_DESC_MODE_8822C)
+#define BIT_CLEAR_MGQ_DESC_MODE_8822C(x) ((x) & (~BITS_MGQ_DESC_MODE_8822C))
+#define BIT_GET_MGQ_DESC_MODE_8822C(x) \
+ (((x) >> BIT_SHIFT_MGQ_DESC_MODE_8822C) & BIT_MASK_MGQ_DESC_MODE_8822C)
+#define BIT_SET_MGQ_DESC_MODE_8822C(x, v) \
+ (BIT_CLEAR_MGQ_DESC_MODE_8822C(x) | BIT_MGQ_DESC_MODE_8822C(v))
+
+#define BIT_SHIFT_MGQ_DESC_NUM_8822C 0
+#define BIT_MASK_MGQ_DESC_NUM_8822C 0xfff
+#define BIT_MGQ_DESC_NUM_8822C(x) \
+ (((x) & BIT_MASK_MGQ_DESC_NUM_8822C) << BIT_SHIFT_MGQ_DESC_NUM_8822C)
+#define BITS_MGQ_DESC_NUM_8822C \
+ (BIT_MASK_MGQ_DESC_NUM_8822C << BIT_SHIFT_MGQ_DESC_NUM_8822C)
+#define BIT_CLEAR_MGQ_DESC_NUM_8822C(x) ((x) & (~BITS_MGQ_DESC_NUM_8822C))
+#define BIT_GET_MGQ_DESC_NUM_8822C(x) \
+ (((x) >> BIT_SHIFT_MGQ_DESC_NUM_8822C) & BIT_MASK_MGQ_DESC_NUM_8822C)
+#define BIT_SET_MGQ_DESC_NUM_8822C(x, v) \
+ (BIT_CLEAR_MGQ_DESC_NUM_8822C(x) | BIT_MGQ_DESC_NUM_8822C(v))
+
+/* 2 REG_RX_RXBD_NUM_8822C */
+#define BIT_SYS_32_64_8822C BIT(15)
+
+#define BIT_SHIFT_BCNQ_DESC_MODE_8822C 13
+#define BIT_MASK_BCNQ_DESC_MODE_8822C 0x3
+#define BIT_BCNQ_DESC_MODE_8822C(x) \
+ (((x) & BIT_MASK_BCNQ_DESC_MODE_8822C) \
+ << BIT_SHIFT_BCNQ_DESC_MODE_8822C)
+#define BITS_BCNQ_DESC_MODE_8822C \
+ (BIT_MASK_BCNQ_DESC_MODE_8822C << BIT_SHIFT_BCNQ_DESC_MODE_8822C)
+#define BIT_CLEAR_BCNQ_DESC_MODE_8822C(x) ((x) & (~BITS_BCNQ_DESC_MODE_8822C))
+#define BIT_GET_BCNQ_DESC_MODE_8822C(x) \
+ (((x) >> BIT_SHIFT_BCNQ_DESC_MODE_8822C) & \
+ BIT_MASK_BCNQ_DESC_MODE_8822C)
+#define BIT_SET_BCNQ_DESC_MODE_8822C(x, v) \
+ (BIT_CLEAR_BCNQ_DESC_MODE_8822C(x) | BIT_BCNQ_DESC_MODE_8822C(v))
+
+#define BIT_PCIE_BCNQ_FLAG_8822C BIT(12)
+
+#define BIT_SHIFT_RXQ_DESC_NUM_8822C 0
+#define BIT_MASK_RXQ_DESC_NUM_8822C 0xfff
+#define BIT_RXQ_DESC_NUM_8822C(x) \
+ (((x) & BIT_MASK_RXQ_DESC_NUM_8822C) << BIT_SHIFT_RXQ_DESC_NUM_8822C)
+#define BITS_RXQ_DESC_NUM_8822C \
+ (BIT_MASK_RXQ_DESC_NUM_8822C << BIT_SHIFT_RXQ_DESC_NUM_8822C)
+#define BIT_CLEAR_RXQ_DESC_NUM_8822C(x) ((x) & (~BITS_RXQ_DESC_NUM_8822C))
+#define BIT_GET_RXQ_DESC_NUM_8822C(x) \
+ (((x) >> BIT_SHIFT_RXQ_DESC_NUM_8822C) & BIT_MASK_RXQ_DESC_NUM_8822C)
+#define BIT_SET_RXQ_DESC_NUM_8822C(x, v) \
+ (BIT_CLEAR_RXQ_DESC_NUM_8822C(x) | BIT_RXQ_DESC_NUM_8822C(v))
+
+/* 2 REG_VOQ_TXBD_NUM_8822C */
+#define BIT_PCIE_VOQ_FLAG_8822C BIT(14)
+
+#define BIT_SHIFT_VOQ_DESC_MODE_8822C 12
+#define BIT_MASK_VOQ_DESC_MODE_8822C 0x3
+#define BIT_VOQ_DESC_MODE_8822C(x) \
+ (((x) & BIT_MASK_VOQ_DESC_MODE_8822C) << BIT_SHIFT_VOQ_DESC_MODE_8822C)
+#define BITS_VOQ_DESC_MODE_8822C \
+ (BIT_MASK_VOQ_DESC_MODE_8822C << BIT_SHIFT_VOQ_DESC_MODE_8822C)
+#define BIT_CLEAR_VOQ_DESC_MODE_8822C(x) ((x) & (~BITS_VOQ_DESC_MODE_8822C))
+#define BIT_GET_VOQ_DESC_MODE_8822C(x) \
+ (((x) >> BIT_SHIFT_VOQ_DESC_MODE_8822C) & BIT_MASK_VOQ_DESC_MODE_8822C)
+#define BIT_SET_VOQ_DESC_MODE_8822C(x, v) \
+ (BIT_CLEAR_VOQ_DESC_MODE_8822C(x) | BIT_VOQ_DESC_MODE_8822C(v))
+
+#define BIT_SHIFT_VOQ_DESC_NUM_8822C 0
+#define BIT_MASK_VOQ_DESC_NUM_8822C 0xfff
+#define BIT_VOQ_DESC_NUM_8822C(x) \
+ (((x) & BIT_MASK_VOQ_DESC_NUM_8822C) << BIT_SHIFT_VOQ_DESC_NUM_8822C)
+#define BITS_VOQ_DESC_NUM_8822C \
+ (BIT_MASK_VOQ_DESC_NUM_8822C << BIT_SHIFT_VOQ_DESC_NUM_8822C)
+#define BIT_CLEAR_VOQ_DESC_NUM_8822C(x) ((x) & (~BITS_VOQ_DESC_NUM_8822C))
+#define BIT_GET_VOQ_DESC_NUM_8822C(x) \
+ (((x) >> BIT_SHIFT_VOQ_DESC_NUM_8822C) & BIT_MASK_VOQ_DESC_NUM_8822C)
+#define BIT_SET_VOQ_DESC_NUM_8822C(x, v) \
+ (BIT_CLEAR_VOQ_DESC_NUM_8822C(x) | BIT_VOQ_DESC_NUM_8822C(v))
+
+/* 2 REG_VIQ_TXBD_NUM_8822C */
+#define BIT_PCIE_VIQ_FLAG_8822C BIT(14)
+
+#define BIT_SHIFT_VIQ_DESC_MODE_8822C 12
+#define BIT_MASK_VIQ_DESC_MODE_8822C 0x3
+#define BIT_VIQ_DESC_MODE_8822C(x) \
+ (((x) & BIT_MASK_VIQ_DESC_MODE_8822C) << BIT_SHIFT_VIQ_DESC_MODE_8822C)
+#define BITS_VIQ_DESC_MODE_8822C \
+ (BIT_MASK_VIQ_DESC_MODE_8822C << BIT_SHIFT_VIQ_DESC_MODE_8822C)
+#define BIT_CLEAR_VIQ_DESC_MODE_8822C(x) ((x) & (~BITS_VIQ_DESC_MODE_8822C))
+#define BIT_GET_VIQ_DESC_MODE_8822C(x) \
+ (((x) >> BIT_SHIFT_VIQ_DESC_MODE_8822C) & BIT_MASK_VIQ_DESC_MODE_8822C)
+#define BIT_SET_VIQ_DESC_MODE_8822C(x, v) \
+ (BIT_CLEAR_VIQ_DESC_MODE_8822C(x) | BIT_VIQ_DESC_MODE_8822C(v))
+
+#define BIT_SHIFT_VIQ_DESC_NUM_8822C 0
+#define BIT_MASK_VIQ_DESC_NUM_8822C 0xfff
+#define BIT_VIQ_DESC_NUM_8822C(x) \
+ (((x) & BIT_MASK_VIQ_DESC_NUM_8822C) << BIT_SHIFT_VIQ_DESC_NUM_8822C)
+#define BITS_VIQ_DESC_NUM_8822C \
+ (BIT_MASK_VIQ_DESC_NUM_8822C << BIT_SHIFT_VIQ_DESC_NUM_8822C)
+#define BIT_CLEAR_VIQ_DESC_NUM_8822C(x) ((x) & (~BITS_VIQ_DESC_NUM_8822C))
+#define BIT_GET_VIQ_DESC_NUM_8822C(x) \
+ (((x) >> BIT_SHIFT_VIQ_DESC_NUM_8822C) & BIT_MASK_VIQ_DESC_NUM_8822C)
+#define BIT_SET_VIQ_DESC_NUM_8822C(x, v) \
+ (BIT_CLEAR_VIQ_DESC_NUM_8822C(x) | BIT_VIQ_DESC_NUM_8822C(v))
+
+/* 2 REG_BEQ_TXBD_NUM_8822C */
+#define BIT_PCIE_BEQ_FLAG_8822C BIT(14)
+
+#define BIT_SHIFT_BEQ_DESC_MODE_8822C 12
+#define BIT_MASK_BEQ_DESC_MODE_8822C 0x3
+#define BIT_BEQ_DESC_MODE_8822C(x) \
+ (((x) & BIT_MASK_BEQ_DESC_MODE_8822C) << BIT_SHIFT_BEQ_DESC_MODE_8822C)
+#define BITS_BEQ_DESC_MODE_8822C \
+ (BIT_MASK_BEQ_DESC_MODE_8822C << BIT_SHIFT_BEQ_DESC_MODE_8822C)
+#define BIT_CLEAR_BEQ_DESC_MODE_8822C(x) ((x) & (~BITS_BEQ_DESC_MODE_8822C))
+#define BIT_GET_BEQ_DESC_MODE_8822C(x) \
+ (((x) >> BIT_SHIFT_BEQ_DESC_MODE_8822C) & BIT_MASK_BEQ_DESC_MODE_8822C)
+#define BIT_SET_BEQ_DESC_MODE_8822C(x, v) \
+ (BIT_CLEAR_BEQ_DESC_MODE_8822C(x) | BIT_BEQ_DESC_MODE_8822C(v))
+
+#define BIT_SHIFT_BEQ_DESC_NUM_8822C 0
+#define BIT_MASK_BEQ_DESC_NUM_8822C 0xfff
+#define BIT_BEQ_DESC_NUM_8822C(x) \
+ (((x) & BIT_MASK_BEQ_DESC_NUM_8822C) << BIT_SHIFT_BEQ_DESC_NUM_8822C)
+#define BITS_BEQ_DESC_NUM_8822C \
+ (BIT_MASK_BEQ_DESC_NUM_8822C << BIT_SHIFT_BEQ_DESC_NUM_8822C)
+#define BIT_CLEAR_BEQ_DESC_NUM_8822C(x) ((x) & (~BITS_BEQ_DESC_NUM_8822C))
+#define BIT_GET_BEQ_DESC_NUM_8822C(x) \
+ (((x) >> BIT_SHIFT_BEQ_DESC_NUM_8822C) & BIT_MASK_BEQ_DESC_NUM_8822C)
+#define BIT_SET_BEQ_DESC_NUM_8822C(x, v) \
+ (BIT_CLEAR_BEQ_DESC_NUM_8822C(x) | BIT_BEQ_DESC_NUM_8822C(v))
+
+/* 2 REG_BKQ_TXBD_NUM_8822C */
+#define BIT_PCIE_BKQ_FLAG_8822C BIT(14)
+
+#define BIT_SHIFT_BKQ_DESC_MODE_8822C 12
+#define BIT_MASK_BKQ_DESC_MODE_8822C 0x3
+#define BIT_BKQ_DESC_MODE_8822C(x) \
+ (((x) & BIT_MASK_BKQ_DESC_MODE_8822C) << BIT_SHIFT_BKQ_DESC_MODE_8822C)
+#define BITS_BKQ_DESC_MODE_8822C \
+ (BIT_MASK_BKQ_DESC_MODE_8822C << BIT_SHIFT_BKQ_DESC_MODE_8822C)
+#define BIT_CLEAR_BKQ_DESC_MODE_8822C(x) ((x) & (~BITS_BKQ_DESC_MODE_8822C))
+#define BIT_GET_BKQ_DESC_MODE_8822C(x) \
+ (((x) >> BIT_SHIFT_BKQ_DESC_MODE_8822C) & BIT_MASK_BKQ_DESC_MODE_8822C)
+#define BIT_SET_BKQ_DESC_MODE_8822C(x, v) \
+ (BIT_CLEAR_BKQ_DESC_MODE_8822C(x) | BIT_BKQ_DESC_MODE_8822C(v))
+
+#define BIT_SHIFT_BKQ_DESC_NUM_8822C 0
+#define BIT_MASK_BKQ_DESC_NUM_8822C 0xfff
+#define BIT_BKQ_DESC_NUM_8822C(x) \
+ (((x) & BIT_MASK_BKQ_DESC_NUM_8822C) << BIT_SHIFT_BKQ_DESC_NUM_8822C)
+#define BITS_BKQ_DESC_NUM_8822C \
+ (BIT_MASK_BKQ_DESC_NUM_8822C << BIT_SHIFT_BKQ_DESC_NUM_8822C)
+#define BIT_CLEAR_BKQ_DESC_NUM_8822C(x) ((x) & (~BITS_BKQ_DESC_NUM_8822C))
+#define BIT_GET_BKQ_DESC_NUM_8822C(x) \
+ (((x) >> BIT_SHIFT_BKQ_DESC_NUM_8822C) & BIT_MASK_BKQ_DESC_NUM_8822C)
+#define BIT_SET_BKQ_DESC_NUM_8822C(x, v) \
+ (BIT_CLEAR_BKQ_DESC_NUM_8822C(x) | BIT_BKQ_DESC_NUM_8822C(v))
+
+/* 2 REG_HI0Q_TXBD_NUM_8822C */
+#define BIT_HI0Q_FLAG_8822C BIT(14)
+
+#define BIT_SHIFT_HI0Q_DESC_MODE_8822C 12
+#define BIT_MASK_HI0Q_DESC_MODE_8822C 0x3
+#define BIT_HI0Q_DESC_MODE_8822C(x) \
+ (((x) & BIT_MASK_HI0Q_DESC_MODE_8822C) \
+ << BIT_SHIFT_HI0Q_DESC_MODE_8822C)
+#define BITS_HI0Q_DESC_MODE_8822C \
+ (BIT_MASK_HI0Q_DESC_MODE_8822C << BIT_SHIFT_HI0Q_DESC_MODE_8822C)
+#define BIT_CLEAR_HI0Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI0Q_DESC_MODE_8822C))
+#define BIT_GET_HI0Q_DESC_MODE_8822C(x) \
+ (((x) >> BIT_SHIFT_HI0Q_DESC_MODE_8822C) & \
+ BIT_MASK_HI0Q_DESC_MODE_8822C)
+#define BIT_SET_HI0Q_DESC_MODE_8822C(x, v) \
+ (BIT_CLEAR_HI0Q_DESC_MODE_8822C(x) | BIT_HI0Q_DESC_MODE_8822C(v))
+
+#define BIT_SHIFT_HI0Q_DESC_NUM_8822C 0
+#define BIT_MASK_HI0Q_DESC_NUM_8822C 0xfff
+#define BIT_HI0Q_DESC_NUM_8822C(x) \
+ (((x) & BIT_MASK_HI0Q_DESC_NUM_8822C) << BIT_SHIFT_HI0Q_DESC_NUM_8822C)
+#define BITS_HI0Q_DESC_NUM_8822C \
+ (BIT_MASK_HI0Q_DESC_NUM_8822C << BIT_SHIFT_HI0Q_DESC_NUM_8822C)
+#define BIT_CLEAR_HI0Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI0Q_DESC_NUM_8822C))
+#define BIT_GET_HI0Q_DESC_NUM_8822C(x) \
+ (((x) >> BIT_SHIFT_HI0Q_DESC_NUM_8822C) & BIT_MASK_HI0Q_DESC_NUM_8822C)
+#define BIT_SET_HI0Q_DESC_NUM_8822C(x, v) \
+ (BIT_CLEAR_HI0Q_DESC_NUM_8822C(x) | BIT_HI0Q_DESC_NUM_8822C(v))
+
+/* 2 REG_HI1Q_TXBD_NUM_8822C */
+#define BIT_HI1Q_FLAG_8822C BIT(14)
+
+#define BIT_SHIFT_HI1Q_DESC_MODE_8822C 12
+#define BIT_MASK_HI1Q_DESC_MODE_8822C 0x3
+#define BIT_HI1Q_DESC_MODE_8822C(x) \
+ (((x) & BIT_MASK_HI1Q_DESC_MODE_8822C) \
+ << BIT_SHIFT_HI1Q_DESC_MODE_8822C)
+#define BITS_HI1Q_DESC_MODE_8822C \
+ (BIT_MASK_HI1Q_DESC_MODE_8822C << BIT_SHIFT_HI1Q_DESC_MODE_8822C)
+#define BIT_CLEAR_HI1Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI1Q_DESC_MODE_8822C))
+#define BIT_GET_HI1Q_DESC_MODE_8822C(x) \
+ (((x) >> BIT_SHIFT_HI1Q_DESC_MODE_8822C) & \
+ BIT_MASK_HI1Q_DESC_MODE_8822C)
+#define BIT_SET_HI1Q_DESC_MODE_8822C(x, v) \
+ (BIT_CLEAR_HI1Q_DESC_MODE_8822C(x) | BIT_HI1Q_DESC_MODE_8822C(v))
+
+#define BIT_SHIFT_HI1Q_DESC_NUM_8822C 0
+#define BIT_MASK_HI1Q_DESC_NUM_8822C 0xfff
+#define BIT_HI1Q_DESC_NUM_8822C(x) \
+ (((x) & BIT_MASK_HI1Q_DESC_NUM_8822C) << BIT_SHIFT_HI1Q_DESC_NUM_8822C)
+#define BITS_HI1Q_DESC_NUM_8822C \
+ (BIT_MASK_HI1Q_DESC_NUM_8822C << BIT_SHIFT_HI1Q_DESC_NUM_8822C)
+#define BIT_CLEAR_HI1Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI1Q_DESC_NUM_8822C))
+#define BIT_GET_HI1Q_DESC_NUM_8822C(x) \
+ (((x) >> BIT_SHIFT_HI1Q_DESC_NUM_8822C) & BIT_MASK_HI1Q_DESC_NUM_8822C)
+#define BIT_SET_HI1Q_DESC_NUM_8822C(x, v) \
+ (BIT_CLEAR_HI1Q_DESC_NUM_8822C(x) | BIT_HI1Q_DESC_NUM_8822C(v))
+
+/* 2 REG_HI2Q_TXBD_NUM_8822C */
+#define BIT_HI2Q_FLAG_8822C BIT(14)
+
+#define BIT_SHIFT_HI2Q_DESC_MODE_8822C 12
+#define BIT_MASK_HI2Q_DESC_MODE_8822C 0x3
+#define BIT_HI2Q_DESC_MODE_8822C(x) \
+ (((x) & BIT_MASK_HI2Q_DESC_MODE_8822C) \
+ << BIT_SHIFT_HI2Q_DESC_MODE_8822C)
+#define BITS_HI2Q_DESC_MODE_8822C \
+ (BIT_MASK_HI2Q_DESC_MODE_8822C << BIT_SHIFT_HI2Q_DESC_MODE_8822C)
+#define BIT_CLEAR_HI2Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI2Q_DESC_MODE_8822C))
+#define BIT_GET_HI2Q_DESC_MODE_8822C(x) \
+ (((x) >> BIT_SHIFT_HI2Q_DESC_MODE_8822C) & \
+ BIT_MASK_HI2Q_DESC_MODE_8822C)
+#define BIT_SET_HI2Q_DESC_MODE_8822C(x, v) \
+ (BIT_CLEAR_HI2Q_DESC_MODE_8822C(x) | BIT_HI2Q_DESC_MODE_8822C(v))
+
+#define BIT_SHIFT_HI2Q_DESC_NUM_8822C 0
+#define BIT_MASK_HI2Q_DESC_NUM_8822C 0xfff
+#define BIT_HI2Q_DESC_NUM_8822C(x) \
+ (((x) & BIT_MASK_HI2Q_DESC_NUM_8822C) << BIT_SHIFT_HI2Q_DESC_NUM_8822C)
+#define BITS_HI2Q_DESC_NUM_8822C \
+ (BIT_MASK_HI2Q_DESC_NUM_8822C << BIT_SHIFT_HI2Q_DESC_NUM_8822C)
+#define BIT_CLEAR_HI2Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI2Q_DESC_NUM_8822C))
+#define BIT_GET_HI2Q_DESC_NUM_8822C(x) \
+ (((x) >> BIT_SHIFT_HI2Q_DESC_NUM_8822C) & BIT_MASK_HI2Q_DESC_NUM_8822C)
+#define BIT_SET_HI2Q_DESC_NUM_8822C(x, v) \
+ (BIT_CLEAR_HI2Q_DESC_NUM_8822C(x) | BIT_HI2Q_DESC_NUM_8822C(v))
+
+/* 2 REG_HI3Q_TXBD_NUM_8822C */
+#define BIT_HI3Q_FLAG_8822C BIT(14)
+
+#define BIT_SHIFT_HI3Q_DESC_MODE_8822C 12
+#define BIT_MASK_HI3Q_DESC_MODE_8822C 0x3
+#define BIT_HI3Q_DESC_MODE_8822C(x) \
+ (((x) & BIT_MASK_HI3Q_DESC_MODE_8822C) \
+ << BIT_SHIFT_HI3Q_DESC_MODE_8822C)
+#define BITS_HI3Q_DESC_MODE_8822C \
+ (BIT_MASK_HI3Q_DESC_MODE_8822C << BIT_SHIFT_HI3Q_DESC_MODE_8822C)
+#define BIT_CLEAR_HI3Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI3Q_DESC_MODE_8822C))
+#define BIT_GET_HI3Q_DESC_MODE_8822C(x) \
+ (((x) >> BIT_SHIFT_HI3Q_DESC_MODE_8822C) & \
+ BIT_MASK_HI3Q_DESC_MODE_8822C)
+#define BIT_SET_HI3Q_DESC_MODE_8822C(x, v) \
+ (BIT_CLEAR_HI3Q_DESC_MODE_8822C(x) | BIT_HI3Q_DESC_MODE_8822C(v))
+
+#define BIT_SHIFT_HI3Q_DESC_NUM_8822C 0
+#define BIT_MASK_HI3Q_DESC_NUM_8822C 0xfff
+#define BIT_HI3Q_DESC_NUM_8822C(x) \
+ (((x) & BIT_MASK_HI3Q_DESC_NUM_8822C) << BIT_SHIFT_HI3Q_DESC_NUM_8822C)
+#define BITS_HI3Q_DESC_NUM_8822C \
+ (BIT_MASK_HI3Q_DESC_NUM_8822C << BIT_SHIFT_HI3Q_DESC_NUM_8822C)
+#define BIT_CLEAR_HI3Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI3Q_DESC_NUM_8822C))
+#define BIT_GET_HI3Q_DESC_NUM_8822C(x) \
+ (((x) >> BIT_SHIFT_HI3Q_DESC_NUM_8822C) & BIT_MASK_HI3Q_DESC_NUM_8822C)
+#define BIT_SET_HI3Q_DESC_NUM_8822C(x, v) \
+ (BIT_CLEAR_HI3Q_DESC_NUM_8822C(x) | BIT_HI3Q_DESC_NUM_8822C(v))
+
+/* 2 REG_HI4Q_TXBD_NUM_8822C */
+#define BIT_HI4Q_FLAG_8822C BIT(14)
+
+#define BIT_SHIFT_HI4Q_DESC_MODE_8822C 12
+#define BIT_MASK_HI4Q_DESC_MODE_8822C 0x3
+#define BIT_HI4Q_DESC_MODE_8822C(x) \
+ (((x) & BIT_MASK_HI4Q_DESC_MODE_8822C) \
+ << BIT_SHIFT_HI4Q_DESC_MODE_8822C)
+#define BITS_HI4Q_DESC_MODE_8822C \
+ (BIT_MASK_HI4Q_DESC_MODE_8822C << BIT_SHIFT_HI4Q_DESC_MODE_8822C)
+#define BIT_CLEAR_HI4Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI4Q_DESC_MODE_8822C))
+#define BIT_GET_HI4Q_DESC_MODE_8822C(x) \
+ (((x) >> BIT_SHIFT_HI4Q_DESC_MODE_8822C) & \
+ BIT_MASK_HI4Q_DESC_MODE_8822C)
+#define BIT_SET_HI4Q_DESC_MODE_8822C(x, v) \
+ (BIT_CLEAR_HI4Q_DESC_MODE_8822C(x) | BIT_HI4Q_DESC_MODE_8822C(v))
+
+#define BIT_SHIFT_HI4Q_DESC_NUM_8822C 0
+#define BIT_MASK_HI4Q_DESC_NUM_8822C 0xfff
+#define BIT_HI4Q_DESC_NUM_8822C(x) \
+ (((x) & BIT_MASK_HI4Q_DESC_NUM_8822C) << BIT_SHIFT_HI4Q_DESC_NUM_8822C)
+#define BITS_HI4Q_DESC_NUM_8822C \
+ (BIT_MASK_HI4Q_DESC_NUM_8822C << BIT_SHIFT_HI4Q_DESC_NUM_8822C)
+#define BIT_CLEAR_HI4Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI4Q_DESC_NUM_8822C))
+#define BIT_GET_HI4Q_DESC_NUM_8822C(x) \
+ (((x) >> BIT_SHIFT_HI4Q_DESC_NUM_8822C) & BIT_MASK_HI4Q_DESC_NUM_8822C)
+#define BIT_SET_HI4Q_DESC_NUM_8822C(x, v) \
+ (BIT_CLEAR_HI4Q_DESC_NUM_8822C(x) | BIT_HI4Q_DESC_NUM_8822C(v))
+
+/* 2 REG_HI5Q_TXBD_NUM_8822C */
+#define BIT_HI5Q_FLAG_8822C BIT(14)
+
+#define BIT_SHIFT_HI5Q_DESC_MODE_8822C 12
+#define BIT_MASK_HI5Q_DESC_MODE_8822C 0x3
+#define BIT_HI5Q_DESC_MODE_8822C(x) \
+ (((x) & BIT_MASK_HI5Q_DESC_MODE_8822C) \
+ << BIT_SHIFT_HI5Q_DESC_MODE_8822C)
+#define BITS_HI5Q_DESC_MODE_8822C \
+ (BIT_MASK_HI5Q_DESC_MODE_8822C << BIT_SHIFT_HI5Q_DESC_MODE_8822C)
+#define BIT_CLEAR_HI5Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI5Q_DESC_MODE_8822C))
+#define BIT_GET_HI5Q_DESC_MODE_8822C(x) \
+ (((x) >> BIT_SHIFT_HI5Q_DESC_MODE_8822C) & \
+ BIT_MASK_HI5Q_DESC_MODE_8822C)
+#define BIT_SET_HI5Q_DESC_MODE_8822C(x, v) \
+ (BIT_CLEAR_HI5Q_DESC_MODE_8822C(x) | BIT_HI5Q_DESC_MODE_8822C(v))
+
+#define BIT_SHIFT_HI5Q_DESC_NUM_8822C 0
+#define BIT_MASK_HI5Q_DESC_NUM_8822C 0xfff
+#define BIT_HI5Q_DESC_NUM_8822C(x) \
+ (((x) & BIT_MASK_HI5Q_DESC_NUM_8822C) << BIT_SHIFT_HI5Q_DESC_NUM_8822C)
+#define BITS_HI5Q_DESC_NUM_8822C \
+ (BIT_MASK_HI5Q_DESC_NUM_8822C << BIT_SHIFT_HI5Q_DESC_NUM_8822C)
+#define BIT_CLEAR_HI5Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI5Q_DESC_NUM_8822C))
+#define BIT_GET_HI5Q_DESC_NUM_8822C(x) \
+ (((x) >> BIT_SHIFT_HI5Q_DESC_NUM_8822C) & BIT_MASK_HI5Q_DESC_NUM_8822C)
+#define BIT_SET_HI5Q_DESC_NUM_8822C(x, v) \
+ (BIT_CLEAR_HI5Q_DESC_NUM_8822C(x) | BIT_HI5Q_DESC_NUM_8822C(v))
+
+/* 2 REG_HI6Q_TXBD_NUM_8822C */
+#define BIT_HI6Q_FLAG_8822C BIT(14)
+
+#define BIT_SHIFT_HI6Q_DESC_MODE_8822C 12
+#define BIT_MASK_HI6Q_DESC_MODE_8822C 0x3
+#define BIT_HI6Q_DESC_MODE_8822C(x) \
+ (((x) & BIT_MASK_HI6Q_DESC_MODE_8822C) \
+ << BIT_SHIFT_HI6Q_DESC_MODE_8822C)
+#define BITS_HI6Q_DESC_MODE_8822C \
+ (BIT_MASK_HI6Q_DESC_MODE_8822C << BIT_SHIFT_HI6Q_DESC_MODE_8822C)
+#define BIT_CLEAR_HI6Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI6Q_DESC_MODE_8822C))
+#define BIT_GET_HI6Q_DESC_MODE_8822C(x) \
+ (((x) >> BIT_SHIFT_HI6Q_DESC_MODE_8822C) & \
+ BIT_MASK_HI6Q_DESC_MODE_8822C)
+#define BIT_SET_HI6Q_DESC_MODE_8822C(x, v) \
+ (BIT_CLEAR_HI6Q_DESC_MODE_8822C(x) | BIT_HI6Q_DESC_MODE_8822C(v))
+
+#define BIT_SHIFT_HI6Q_DESC_NUM_8822C 0
+#define BIT_MASK_HI6Q_DESC_NUM_8822C 0xfff
+#define BIT_HI6Q_DESC_NUM_8822C(x) \
+ (((x) & BIT_MASK_HI6Q_DESC_NUM_8822C) << BIT_SHIFT_HI6Q_DESC_NUM_8822C)
+#define BITS_HI6Q_DESC_NUM_8822C \
+ (BIT_MASK_HI6Q_DESC_NUM_8822C << BIT_SHIFT_HI6Q_DESC_NUM_8822C)
+#define BIT_CLEAR_HI6Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI6Q_DESC_NUM_8822C))
+#define BIT_GET_HI6Q_DESC_NUM_8822C(x) \
+ (((x) >> BIT_SHIFT_HI6Q_DESC_NUM_8822C) & BIT_MASK_HI6Q_DESC_NUM_8822C)
+#define BIT_SET_HI6Q_DESC_NUM_8822C(x, v) \
+ (BIT_CLEAR_HI6Q_DESC_NUM_8822C(x) | BIT_HI6Q_DESC_NUM_8822C(v))
+
+/* 2 REG_HI7Q_TXBD_NUM_8822C */
+#define BIT_HI7Q_FLAG_8822C BIT(14)
+
+#define BIT_SHIFT_HI7Q_DESC_MODE_8822C 12
+#define BIT_MASK_HI7Q_DESC_MODE_8822C 0x3
+#define BIT_HI7Q_DESC_MODE_8822C(x) \
+ (((x) & BIT_MASK_HI7Q_DESC_MODE_8822C) \
+ << BIT_SHIFT_HI7Q_DESC_MODE_8822C)
+#define BITS_HI7Q_DESC_MODE_8822C \
+ (BIT_MASK_HI7Q_DESC_MODE_8822C << BIT_SHIFT_HI7Q_DESC_MODE_8822C)
+#define BIT_CLEAR_HI7Q_DESC_MODE_8822C(x) ((x) & (~BITS_HI7Q_DESC_MODE_8822C))
+#define BIT_GET_HI7Q_DESC_MODE_8822C(x) \
+ (((x) >> BIT_SHIFT_HI7Q_DESC_MODE_8822C) & \
+ BIT_MASK_HI7Q_DESC_MODE_8822C)
+#define BIT_SET_HI7Q_DESC_MODE_8822C(x, v) \
+ (BIT_CLEAR_HI7Q_DESC_MODE_8822C(x) | BIT_HI7Q_DESC_MODE_8822C(v))
+
+#define BIT_SHIFT_HI7Q_DESC_NUM_8822C 0
+#define BIT_MASK_HI7Q_DESC_NUM_8822C 0xfff
+#define BIT_HI7Q_DESC_NUM_8822C(x) \
+ (((x) & BIT_MASK_HI7Q_DESC_NUM_8822C) << BIT_SHIFT_HI7Q_DESC_NUM_8822C)
+#define BITS_HI7Q_DESC_NUM_8822C \
+ (BIT_MASK_HI7Q_DESC_NUM_8822C << BIT_SHIFT_HI7Q_DESC_NUM_8822C)
+#define BIT_CLEAR_HI7Q_DESC_NUM_8822C(x) ((x) & (~BITS_HI7Q_DESC_NUM_8822C))
+#define BIT_GET_HI7Q_DESC_NUM_8822C(x) \
+ (((x) >> BIT_SHIFT_HI7Q_DESC_NUM_8822C) & BIT_MASK_HI7Q_DESC_NUM_8822C)
+#define BIT_SET_HI7Q_DESC_NUM_8822C(x, v) \
+ (BIT_CLEAR_HI7Q_DESC_NUM_8822C(x) | BIT_HI7Q_DESC_NUM_8822C(v))
+
+/* 2 REG_TSFTIMER_HCI_8822C */
+
+#define BIT_SHIFT_TSFT2_HCI_8822C 16
+#define BIT_MASK_TSFT2_HCI_8822C 0xffff
+#define BIT_TSFT2_HCI_8822C(x) \
+ (((x) & BIT_MASK_TSFT2_HCI_8822C) << BIT_SHIFT_TSFT2_HCI_8822C)
+#define BITS_TSFT2_HCI_8822C \
+ (BIT_MASK_TSFT2_HCI_8822C << BIT_SHIFT_TSFT2_HCI_8822C)
+#define BIT_CLEAR_TSFT2_HCI_8822C(x) ((x) & (~BITS_TSFT2_HCI_8822C))
+#define BIT_GET_TSFT2_HCI_8822C(x) \
+ (((x) >> BIT_SHIFT_TSFT2_HCI_8822C) & BIT_MASK_TSFT2_HCI_8822C)
+#define BIT_SET_TSFT2_HCI_8822C(x, v) \
+ (BIT_CLEAR_TSFT2_HCI_8822C(x) | BIT_TSFT2_HCI_8822C(v))
+
+#define BIT_SHIFT_TSFT1_HCI_8822C 0
+#define BIT_MASK_TSFT1_HCI_8822C 0xffff
+#define BIT_TSFT1_HCI_8822C(x) \
+ (((x) & BIT_MASK_TSFT1_HCI_8822C) << BIT_SHIFT_TSFT1_HCI_8822C)
+#define BITS_TSFT1_HCI_8822C \
+ (BIT_MASK_TSFT1_HCI_8822C << BIT_SHIFT_TSFT1_HCI_8822C)
+#define BIT_CLEAR_TSFT1_HCI_8822C(x) ((x) & (~BITS_TSFT1_HCI_8822C))
+#define BIT_GET_TSFT1_HCI_8822C(x) \
+ (((x) >> BIT_SHIFT_TSFT1_HCI_8822C) & BIT_MASK_TSFT1_HCI_8822C)
+#define BIT_SET_TSFT1_HCI_8822C(x, v) \
+ (BIT_CLEAR_TSFT1_HCI_8822C(x) | BIT_TSFT1_HCI_8822C(v))
+
+/* 2 REG_BD_RWPTR_CLR_8822C */
+#define BIT_CLR_HI7Q_HW_IDX_8822C BIT(29)
+#define BIT_CLR_HI6Q_HW_IDX_8822C BIT(28)
+#define BIT_CLR_HI5Q_HW_IDX_8822C BIT(27)
+#define BIT_CLR_HI4Q_HW_IDX_8822C BIT(26)
+#define BIT_CLR_HI3Q_HW_IDX_8822C BIT(25)
+#define BIT_CLR_HI2Q_HW_IDX_8822C BIT(24)
+#define BIT_CLR_HI1Q_HW_IDX_8822C BIT(23)
+#define BIT_CLR_HI0Q_HW_IDX_8822C BIT(22)
+#define BIT_CLR_BKQ_HW_IDX_8822C BIT(21)
+#define BIT_CLR_BEQ_HW_IDX_8822C BIT(20)
+#define BIT_CLR_VIQ_HW_IDX_8822C BIT(19)
+#define BIT_CLR_VOQ_HW_IDX_8822C BIT(18)
+#define BIT_CLR_MGQ_HW_IDX_8822C BIT(17)
+#define BIT_CLR_RXQ_HW_IDX_8822C BIT(16)
+#define BIT_CLR_HI7Q_HOST_IDX_8822C BIT(13)
+#define BIT_CLR_HI6Q_HOST_IDX_8822C BIT(12)
+#define BIT_CLR_HI5Q_HOST_IDX_8822C BIT(11)
+#define BIT_CLR_HI4Q_HOST_IDX_8822C BIT(10)
+#define BIT_CLR_HI3Q_HOST_IDX_8822C BIT(9)
+#define BIT_CLR_HI2Q_HOST_IDX_8822C BIT(8)
+#define BIT_CLR_HI1Q_HOST_IDX_8822C BIT(7)
+#define BIT_CLR_HI0Q_HOST_IDX_8822C BIT(6)
+#define BIT_CLR_BKQ_HOST_IDX_8822C BIT(5)
+#define BIT_CLR_BEQ_HOST_IDX_8822C BIT(4)
+#define BIT_CLR_VIQ_HOST_IDX_8822C BIT(3)
+#define BIT_CLR_VOQ_HOST_IDX_8822C BIT(2)
+#define BIT_CLR_MGQ_HOST_IDX_8822C BIT(1)
+#define BIT_CLR_RXQ_HOST_IDX_8822C BIT(0)
+
+/* 2 REG_VOQ_TXBD_IDX_8822C */
+
+#define BIT_SHIFT_VOQ_HW_IDX_8822C 16
+#define BIT_MASK_VOQ_HW_IDX_8822C 0xfff
+#define BIT_VOQ_HW_IDX_8822C(x) \
+ (((x) & BIT_MASK_VOQ_HW_IDX_8822C) << BIT_SHIFT_VOQ_HW_IDX_8822C)
+#define BITS_VOQ_HW_IDX_8822C \
+ (BIT_MASK_VOQ_HW_IDX_8822C << BIT_SHIFT_VOQ_HW_IDX_8822C)
+#define BIT_CLEAR_VOQ_HW_IDX_8822C(x) ((x) & (~BITS_VOQ_HW_IDX_8822C))
+#define BIT_GET_VOQ_HW_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_VOQ_HW_IDX_8822C) & BIT_MASK_VOQ_HW_IDX_8822C)
+#define BIT_SET_VOQ_HW_IDX_8822C(x, v) \
+ (BIT_CLEAR_VOQ_HW_IDX_8822C(x) | BIT_VOQ_HW_IDX_8822C(v))
+
+#define BIT_SHIFT_VOQ_HOST_IDX_8822C 0
+#define BIT_MASK_VOQ_HOST_IDX_8822C 0xfff
+#define BIT_VOQ_HOST_IDX_8822C(x) \
+ (((x) & BIT_MASK_VOQ_HOST_IDX_8822C) << BIT_SHIFT_VOQ_HOST_IDX_8822C)
+#define BITS_VOQ_HOST_IDX_8822C \
+ (BIT_MASK_VOQ_HOST_IDX_8822C << BIT_SHIFT_VOQ_HOST_IDX_8822C)
+#define BIT_CLEAR_VOQ_HOST_IDX_8822C(x) ((x) & (~BITS_VOQ_HOST_IDX_8822C))
+#define BIT_GET_VOQ_HOST_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_VOQ_HOST_IDX_8822C) & BIT_MASK_VOQ_HOST_IDX_8822C)
+#define BIT_SET_VOQ_HOST_IDX_8822C(x, v) \
+ (BIT_CLEAR_VOQ_HOST_IDX_8822C(x) | BIT_VOQ_HOST_IDX_8822C(v))
+
+/* 2 REG_VIQ_TXBD_IDX_8822C */
+
+#define BIT_SHIFT_VIQ_HW_IDX_8822C 16
+#define BIT_MASK_VIQ_HW_IDX_8822C 0xfff
+#define BIT_VIQ_HW_IDX_8822C(x) \
+ (((x) & BIT_MASK_VIQ_HW_IDX_8822C) << BIT_SHIFT_VIQ_HW_IDX_8822C)
+#define BITS_VIQ_HW_IDX_8822C \
+ (BIT_MASK_VIQ_HW_IDX_8822C << BIT_SHIFT_VIQ_HW_IDX_8822C)
+#define BIT_CLEAR_VIQ_HW_IDX_8822C(x) ((x) & (~BITS_VIQ_HW_IDX_8822C))
+#define BIT_GET_VIQ_HW_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_VIQ_HW_IDX_8822C) & BIT_MASK_VIQ_HW_IDX_8822C)
+#define BIT_SET_VIQ_HW_IDX_8822C(x, v) \
+ (BIT_CLEAR_VIQ_HW_IDX_8822C(x) | BIT_VIQ_HW_IDX_8822C(v))
+
+#define BIT_SHIFT_VIQ_HOST_IDX_8822C 0
+#define BIT_MASK_VIQ_HOST_IDX_8822C 0xfff
+#define BIT_VIQ_HOST_IDX_8822C(x) \
+ (((x) & BIT_MASK_VIQ_HOST_IDX_8822C) << BIT_SHIFT_VIQ_HOST_IDX_8822C)
+#define BITS_VIQ_HOST_IDX_8822C \
+ (BIT_MASK_VIQ_HOST_IDX_8822C << BIT_SHIFT_VIQ_HOST_IDX_8822C)
+#define BIT_CLEAR_VIQ_HOST_IDX_8822C(x) ((x) & (~BITS_VIQ_HOST_IDX_8822C))
+#define BIT_GET_VIQ_HOST_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_VIQ_HOST_IDX_8822C) & BIT_MASK_VIQ_HOST_IDX_8822C)
+#define BIT_SET_VIQ_HOST_IDX_8822C(x, v) \
+ (BIT_CLEAR_VIQ_HOST_IDX_8822C(x) | BIT_VIQ_HOST_IDX_8822C(v))
+
+/* 2 REG_BEQ_TXBD_IDX_8822C */
+
+#define BIT_SHIFT_BEQ_HW_IDX_8822C 16
+#define BIT_MASK_BEQ_HW_IDX_8822C 0xfff
+#define BIT_BEQ_HW_IDX_8822C(x) \
+ (((x) & BIT_MASK_BEQ_HW_IDX_8822C) << BIT_SHIFT_BEQ_HW_IDX_8822C)
+#define BITS_BEQ_HW_IDX_8822C \
+ (BIT_MASK_BEQ_HW_IDX_8822C << BIT_SHIFT_BEQ_HW_IDX_8822C)
+#define BIT_CLEAR_BEQ_HW_IDX_8822C(x) ((x) & (~BITS_BEQ_HW_IDX_8822C))
+#define BIT_GET_BEQ_HW_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_BEQ_HW_IDX_8822C) & BIT_MASK_BEQ_HW_IDX_8822C)
+#define BIT_SET_BEQ_HW_IDX_8822C(x, v) \
+ (BIT_CLEAR_BEQ_HW_IDX_8822C(x) | BIT_BEQ_HW_IDX_8822C(v))
+
+#define BIT_SHIFT_BEQ_HOST_IDX_8822C 0
+#define BIT_MASK_BEQ_HOST_IDX_8822C 0xfff
+#define BIT_BEQ_HOST_IDX_8822C(x) \
+ (((x) & BIT_MASK_BEQ_HOST_IDX_8822C) << BIT_SHIFT_BEQ_HOST_IDX_8822C)
+#define BITS_BEQ_HOST_IDX_8822C \
+ (BIT_MASK_BEQ_HOST_IDX_8822C << BIT_SHIFT_BEQ_HOST_IDX_8822C)
+#define BIT_CLEAR_BEQ_HOST_IDX_8822C(x) ((x) & (~BITS_BEQ_HOST_IDX_8822C))
+#define BIT_GET_BEQ_HOST_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_BEQ_HOST_IDX_8822C) & BIT_MASK_BEQ_HOST_IDX_8822C)
+#define BIT_SET_BEQ_HOST_IDX_8822C(x, v) \
+ (BIT_CLEAR_BEQ_HOST_IDX_8822C(x) | BIT_BEQ_HOST_IDX_8822C(v))
+
+/* 2 REG_BKQ_TXBD_IDX_8822C */
+
+#define BIT_SHIFT_BKQ_HW_IDX_8822C 16
+#define BIT_MASK_BKQ_HW_IDX_8822C 0xfff
+#define BIT_BKQ_HW_IDX_8822C(x) \
+ (((x) & BIT_MASK_BKQ_HW_IDX_8822C) << BIT_SHIFT_BKQ_HW_IDX_8822C)
+#define BITS_BKQ_HW_IDX_8822C \
+ (BIT_MASK_BKQ_HW_IDX_8822C << BIT_SHIFT_BKQ_HW_IDX_8822C)
+#define BIT_CLEAR_BKQ_HW_IDX_8822C(x) ((x) & (~BITS_BKQ_HW_IDX_8822C))
+#define BIT_GET_BKQ_HW_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_BKQ_HW_IDX_8822C) & BIT_MASK_BKQ_HW_IDX_8822C)
+#define BIT_SET_BKQ_HW_IDX_8822C(x, v) \
+ (BIT_CLEAR_BKQ_HW_IDX_8822C(x) | BIT_BKQ_HW_IDX_8822C(v))
+
+#define BIT_SHIFT_BKQ_HOST_IDX_8822C 0
+#define BIT_MASK_BKQ_HOST_IDX_8822C 0xfff
+#define BIT_BKQ_HOST_IDX_8822C(x) \
+ (((x) & BIT_MASK_BKQ_HOST_IDX_8822C) << BIT_SHIFT_BKQ_HOST_IDX_8822C)
+#define BITS_BKQ_HOST_IDX_8822C \
+ (BIT_MASK_BKQ_HOST_IDX_8822C << BIT_SHIFT_BKQ_HOST_IDX_8822C)
+#define BIT_CLEAR_BKQ_HOST_IDX_8822C(x) ((x) & (~BITS_BKQ_HOST_IDX_8822C))
+#define BIT_GET_BKQ_HOST_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_BKQ_HOST_IDX_8822C) & BIT_MASK_BKQ_HOST_IDX_8822C)
+#define BIT_SET_BKQ_HOST_IDX_8822C(x, v) \
+ (BIT_CLEAR_BKQ_HOST_IDX_8822C(x) | BIT_BKQ_HOST_IDX_8822C(v))
+
+/* 2 REG_MGQ_TXBD_IDX_8822C */
+
+#define BIT_SHIFT_MGQ_HW_IDX_8822C 16
+#define BIT_MASK_MGQ_HW_IDX_8822C 0xfff
+#define BIT_MGQ_HW_IDX_8822C(x) \
+ (((x) & BIT_MASK_MGQ_HW_IDX_8822C) << BIT_SHIFT_MGQ_HW_IDX_8822C)
+#define BITS_MGQ_HW_IDX_8822C \
+ (BIT_MASK_MGQ_HW_IDX_8822C << BIT_SHIFT_MGQ_HW_IDX_8822C)
+#define BIT_CLEAR_MGQ_HW_IDX_8822C(x) ((x) & (~BITS_MGQ_HW_IDX_8822C))
+#define BIT_GET_MGQ_HW_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_MGQ_HW_IDX_8822C) & BIT_MASK_MGQ_HW_IDX_8822C)
+#define BIT_SET_MGQ_HW_IDX_8822C(x, v) \
+ (BIT_CLEAR_MGQ_HW_IDX_8822C(x) | BIT_MGQ_HW_IDX_8822C(v))
+
+#define BIT_SHIFT_MGQ_HOST_IDX_8822C 0
+#define BIT_MASK_MGQ_HOST_IDX_8822C 0xfff
+#define BIT_MGQ_HOST_IDX_8822C(x) \
+ (((x) & BIT_MASK_MGQ_HOST_IDX_8822C) << BIT_SHIFT_MGQ_HOST_IDX_8822C)
+#define BITS_MGQ_HOST_IDX_8822C \
+ (BIT_MASK_MGQ_HOST_IDX_8822C << BIT_SHIFT_MGQ_HOST_IDX_8822C)
+#define BIT_CLEAR_MGQ_HOST_IDX_8822C(x) ((x) & (~BITS_MGQ_HOST_IDX_8822C))
+#define BIT_GET_MGQ_HOST_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_MGQ_HOST_IDX_8822C) & BIT_MASK_MGQ_HOST_IDX_8822C)
+#define BIT_SET_MGQ_HOST_IDX_8822C(x, v) \
+ (BIT_CLEAR_MGQ_HOST_IDX_8822C(x) | BIT_MGQ_HOST_IDX_8822C(v))
+
+/* 2 REG_RXQ_RXBD_IDX_8822C */
+
+#define BIT_SHIFT_RXQ_HW_IDX_8822C 16
+#define BIT_MASK_RXQ_HW_IDX_8822C 0xfff
+#define BIT_RXQ_HW_IDX_8822C(x) \
+ (((x) & BIT_MASK_RXQ_HW_IDX_8822C) << BIT_SHIFT_RXQ_HW_IDX_8822C)
+#define BITS_RXQ_HW_IDX_8822C \
+ (BIT_MASK_RXQ_HW_IDX_8822C << BIT_SHIFT_RXQ_HW_IDX_8822C)
+#define BIT_CLEAR_RXQ_HW_IDX_8822C(x) ((x) & (~BITS_RXQ_HW_IDX_8822C))
+#define BIT_GET_RXQ_HW_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_RXQ_HW_IDX_8822C) & BIT_MASK_RXQ_HW_IDX_8822C)
+#define BIT_SET_RXQ_HW_IDX_8822C(x, v) \
+ (BIT_CLEAR_RXQ_HW_IDX_8822C(x) | BIT_RXQ_HW_IDX_8822C(v))
+
+#define BIT_SHIFT_RXQ_HOST_IDX_8822C 0
+#define BIT_MASK_RXQ_HOST_IDX_8822C 0xfff
+#define BIT_RXQ_HOST_IDX_8822C(x) \
+ (((x) & BIT_MASK_RXQ_HOST_IDX_8822C) << BIT_SHIFT_RXQ_HOST_IDX_8822C)
+#define BITS_RXQ_HOST_IDX_8822C \
+ (BIT_MASK_RXQ_HOST_IDX_8822C << BIT_SHIFT_RXQ_HOST_IDX_8822C)
+#define BIT_CLEAR_RXQ_HOST_IDX_8822C(x) ((x) & (~BITS_RXQ_HOST_IDX_8822C))
+#define BIT_GET_RXQ_HOST_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_RXQ_HOST_IDX_8822C) & BIT_MASK_RXQ_HOST_IDX_8822C)
+#define BIT_SET_RXQ_HOST_IDX_8822C(x, v) \
+ (BIT_CLEAR_RXQ_HOST_IDX_8822C(x) | BIT_RXQ_HOST_IDX_8822C(v))
+
+/* 2 REG_HI0Q_TXBD_IDX_8822C */
+
+#define BIT_SHIFT_HI0Q_HW_IDX_8822C 16
+#define BIT_MASK_HI0Q_HW_IDX_8822C 0xfff
+#define BIT_HI0Q_HW_IDX_8822C(x) \
+ (((x) & BIT_MASK_HI0Q_HW_IDX_8822C) << BIT_SHIFT_HI0Q_HW_IDX_8822C)
+#define BITS_HI0Q_HW_IDX_8822C \
+ (BIT_MASK_HI0Q_HW_IDX_8822C << BIT_SHIFT_HI0Q_HW_IDX_8822C)
+#define BIT_CLEAR_HI0Q_HW_IDX_8822C(x) ((x) & (~BITS_HI0Q_HW_IDX_8822C))
+#define BIT_GET_HI0Q_HW_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_HI0Q_HW_IDX_8822C) & BIT_MASK_HI0Q_HW_IDX_8822C)
+#define BIT_SET_HI0Q_HW_IDX_8822C(x, v) \
+ (BIT_CLEAR_HI0Q_HW_IDX_8822C(x) | BIT_HI0Q_HW_IDX_8822C(v))
+
+#define BIT_SHIFT_HI0Q_HOST_IDX_8822C 0
+#define BIT_MASK_HI0Q_HOST_IDX_8822C 0xfff
+#define BIT_HI0Q_HOST_IDX_8822C(x) \
+ (((x) & BIT_MASK_HI0Q_HOST_IDX_8822C) << BIT_SHIFT_HI0Q_HOST_IDX_8822C)
+#define BITS_HI0Q_HOST_IDX_8822C \
+ (BIT_MASK_HI0Q_HOST_IDX_8822C << BIT_SHIFT_HI0Q_HOST_IDX_8822C)
+#define BIT_CLEAR_HI0Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI0Q_HOST_IDX_8822C))
+#define BIT_GET_HI0Q_HOST_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_HI0Q_HOST_IDX_8822C) & BIT_MASK_HI0Q_HOST_IDX_8822C)
+#define BIT_SET_HI0Q_HOST_IDX_8822C(x, v) \
+ (BIT_CLEAR_HI0Q_HOST_IDX_8822C(x) | BIT_HI0Q_HOST_IDX_8822C(v))
+
+/* 2 REG_HI1Q_TXBD_IDX_8822C */
+
+#define BIT_SHIFT_HI1Q_HW_IDX_8822C 16
+#define BIT_MASK_HI1Q_HW_IDX_8822C 0xfff
+#define BIT_HI1Q_HW_IDX_8822C(x) \
+ (((x) & BIT_MASK_HI1Q_HW_IDX_8822C) << BIT_SHIFT_HI1Q_HW_IDX_8822C)
+#define BITS_HI1Q_HW_IDX_8822C \
+ (BIT_MASK_HI1Q_HW_IDX_8822C << BIT_SHIFT_HI1Q_HW_IDX_8822C)
+#define BIT_CLEAR_HI1Q_HW_IDX_8822C(x) ((x) & (~BITS_HI1Q_HW_IDX_8822C))
+#define BIT_GET_HI1Q_HW_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_HI1Q_HW_IDX_8822C) & BIT_MASK_HI1Q_HW_IDX_8822C)
+#define BIT_SET_HI1Q_HW_IDX_8822C(x, v) \
+ (BIT_CLEAR_HI1Q_HW_IDX_8822C(x) | BIT_HI1Q_HW_IDX_8822C(v))
+
+#define BIT_SHIFT_HI1Q_HOST_IDX_8822C 0
+#define BIT_MASK_HI1Q_HOST_IDX_8822C 0xfff
+#define BIT_HI1Q_HOST_IDX_8822C(x) \
+ (((x) & BIT_MASK_HI1Q_HOST_IDX_8822C) << BIT_SHIFT_HI1Q_HOST_IDX_8822C)
+#define BITS_HI1Q_HOST_IDX_8822C \
+ (BIT_MASK_HI1Q_HOST_IDX_8822C << BIT_SHIFT_HI1Q_HOST_IDX_8822C)
+#define BIT_CLEAR_HI1Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI1Q_HOST_IDX_8822C))
+#define BIT_GET_HI1Q_HOST_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_HI1Q_HOST_IDX_8822C) & BIT_MASK_HI1Q_HOST_IDX_8822C)
+#define BIT_SET_HI1Q_HOST_IDX_8822C(x, v) \
+ (BIT_CLEAR_HI1Q_HOST_IDX_8822C(x) | BIT_HI1Q_HOST_IDX_8822C(v))
+
+/* 2 REG_HI2Q_TXBD_IDX_8822C */
+
+#define BIT_SHIFT_HI2Q_HW_IDX_8822C 16
+#define BIT_MASK_HI2Q_HW_IDX_8822C 0xfff
+#define BIT_HI2Q_HW_IDX_8822C(x) \
+ (((x) & BIT_MASK_HI2Q_HW_IDX_8822C) << BIT_SHIFT_HI2Q_HW_IDX_8822C)
+#define BITS_HI2Q_HW_IDX_8822C \
+ (BIT_MASK_HI2Q_HW_IDX_8822C << BIT_SHIFT_HI2Q_HW_IDX_8822C)
+#define BIT_CLEAR_HI2Q_HW_IDX_8822C(x) ((x) & (~BITS_HI2Q_HW_IDX_8822C))
+#define BIT_GET_HI2Q_HW_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_HI2Q_HW_IDX_8822C) & BIT_MASK_HI2Q_HW_IDX_8822C)
+#define BIT_SET_HI2Q_HW_IDX_8822C(x, v) \
+ (BIT_CLEAR_HI2Q_HW_IDX_8822C(x) | BIT_HI2Q_HW_IDX_8822C(v))
+
+#define BIT_SHIFT_HI2Q_HOST_IDX_8822C 0
+#define BIT_MASK_HI2Q_HOST_IDX_8822C 0xfff
+#define BIT_HI2Q_HOST_IDX_8822C(x) \
+ (((x) & BIT_MASK_HI2Q_HOST_IDX_8822C) << BIT_SHIFT_HI2Q_HOST_IDX_8822C)
+#define BITS_HI2Q_HOST_IDX_8822C \
+ (BIT_MASK_HI2Q_HOST_IDX_8822C << BIT_SHIFT_HI2Q_HOST_IDX_8822C)
+#define BIT_CLEAR_HI2Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI2Q_HOST_IDX_8822C))
+#define BIT_GET_HI2Q_HOST_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_HI2Q_HOST_IDX_8822C) & BIT_MASK_HI2Q_HOST_IDX_8822C)
+#define BIT_SET_HI2Q_HOST_IDX_8822C(x, v) \
+ (BIT_CLEAR_HI2Q_HOST_IDX_8822C(x) | BIT_HI2Q_HOST_IDX_8822C(v))
+
+/* 2 REG_HI3Q_TXBD_IDX_8822C */
+
+#define BIT_SHIFT_HI3Q_HW_IDX_8822C 16
+#define BIT_MASK_HI3Q_HW_IDX_8822C 0xfff
+#define BIT_HI3Q_HW_IDX_8822C(x) \
+ (((x) & BIT_MASK_HI3Q_HW_IDX_8822C) << BIT_SHIFT_HI3Q_HW_IDX_8822C)
+#define BITS_HI3Q_HW_IDX_8822C \
+ (BIT_MASK_HI3Q_HW_IDX_8822C << BIT_SHIFT_HI3Q_HW_IDX_8822C)
+#define BIT_CLEAR_HI3Q_HW_IDX_8822C(x) ((x) & (~BITS_HI3Q_HW_IDX_8822C))
+#define BIT_GET_HI3Q_HW_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_HI3Q_HW_IDX_8822C) & BIT_MASK_HI3Q_HW_IDX_8822C)
+#define BIT_SET_HI3Q_HW_IDX_8822C(x, v) \
+ (BIT_CLEAR_HI3Q_HW_IDX_8822C(x) | BIT_HI3Q_HW_IDX_8822C(v))
+
+#define BIT_SHIFT_HI3Q_HOST_IDX_8822C 0
+#define BIT_MASK_HI3Q_HOST_IDX_8822C 0xfff
+#define BIT_HI3Q_HOST_IDX_8822C(x) \
+ (((x) & BIT_MASK_HI3Q_HOST_IDX_8822C) << BIT_SHIFT_HI3Q_HOST_IDX_8822C)
+#define BITS_HI3Q_HOST_IDX_8822C \
+ (BIT_MASK_HI3Q_HOST_IDX_8822C << BIT_SHIFT_HI3Q_HOST_IDX_8822C)
+#define BIT_CLEAR_HI3Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI3Q_HOST_IDX_8822C))
+#define BIT_GET_HI3Q_HOST_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_HI3Q_HOST_IDX_8822C) & BIT_MASK_HI3Q_HOST_IDX_8822C)
+#define BIT_SET_HI3Q_HOST_IDX_8822C(x, v) \
+ (BIT_CLEAR_HI3Q_HOST_IDX_8822C(x) | BIT_HI3Q_HOST_IDX_8822C(v))
+
+/* 2 REG_HI4Q_TXBD_IDX_8822C */
+
+#define BIT_SHIFT_HI4Q_HW_IDX_8822C 16
+#define BIT_MASK_HI4Q_HW_IDX_8822C 0xfff
+#define BIT_HI4Q_HW_IDX_8822C(x) \
+ (((x) & BIT_MASK_HI4Q_HW_IDX_8822C) << BIT_SHIFT_HI4Q_HW_IDX_8822C)
+#define BITS_HI4Q_HW_IDX_8822C \
+ (BIT_MASK_HI4Q_HW_IDX_8822C << BIT_SHIFT_HI4Q_HW_IDX_8822C)
+#define BIT_CLEAR_HI4Q_HW_IDX_8822C(x) ((x) & (~BITS_HI4Q_HW_IDX_8822C))
+#define BIT_GET_HI4Q_HW_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_HI4Q_HW_IDX_8822C) & BIT_MASK_HI4Q_HW_IDX_8822C)
+#define BIT_SET_HI4Q_HW_IDX_8822C(x, v) \
+ (BIT_CLEAR_HI4Q_HW_IDX_8822C(x) | BIT_HI4Q_HW_IDX_8822C(v))
+
+#define BIT_SHIFT_HI4Q_HOST_IDX_8822C 0
+#define BIT_MASK_HI4Q_HOST_IDX_8822C 0xfff
+#define BIT_HI4Q_HOST_IDX_8822C(x) \
+ (((x) & BIT_MASK_HI4Q_HOST_IDX_8822C) << BIT_SHIFT_HI4Q_HOST_IDX_8822C)
+#define BITS_HI4Q_HOST_IDX_8822C \
+ (BIT_MASK_HI4Q_HOST_IDX_8822C << BIT_SHIFT_HI4Q_HOST_IDX_8822C)
+#define BIT_CLEAR_HI4Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI4Q_HOST_IDX_8822C))
+#define BIT_GET_HI4Q_HOST_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_HI4Q_HOST_IDX_8822C) & BIT_MASK_HI4Q_HOST_IDX_8822C)
+#define BIT_SET_HI4Q_HOST_IDX_8822C(x, v) \
+ (BIT_CLEAR_HI4Q_HOST_IDX_8822C(x) | BIT_HI4Q_HOST_IDX_8822C(v))
+
+/* 2 REG_HI5Q_TXBD_IDX_8822C */
+
+#define BIT_SHIFT_HI5Q_HW_IDX_8822C 16
+#define BIT_MASK_HI5Q_HW_IDX_8822C 0xfff
+#define BIT_HI5Q_HW_IDX_8822C(x) \
+ (((x) & BIT_MASK_HI5Q_HW_IDX_8822C) << BIT_SHIFT_HI5Q_HW_IDX_8822C)
+#define BITS_HI5Q_HW_IDX_8822C \
+ (BIT_MASK_HI5Q_HW_IDX_8822C << BIT_SHIFT_HI5Q_HW_IDX_8822C)
+#define BIT_CLEAR_HI5Q_HW_IDX_8822C(x) ((x) & (~BITS_HI5Q_HW_IDX_8822C))
+#define BIT_GET_HI5Q_HW_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_HI5Q_HW_IDX_8822C) & BIT_MASK_HI5Q_HW_IDX_8822C)
+#define BIT_SET_HI5Q_HW_IDX_8822C(x, v) \
+ (BIT_CLEAR_HI5Q_HW_IDX_8822C(x) | BIT_HI5Q_HW_IDX_8822C(v))
+
+#define BIT_SHIFT_HI5Q_HOST_IDX_8822C 0
+#define BIT_MASK_HI5Q_HOST_IDX_8822C 0xfff
+#define BIT_HI5Q_HOST_IDX_8822C(x) \
+ (((x) & BIT_MASK_HI5Q_HOST_IDX_8822C) << BIT_SHIFT_HI5Q_HOST_IDX_8822C)
+#define BITS_HI5Q_HOST_IDX_8822C \
+ (BIT_MASK_HI5Q_HOST_IDX_8822C << BIT_SHIFT_HI5Q_HOST_IDX_8822C)
+#define BIT_CLEAR_HI5Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI5Q_HOST_IDX_8822C))
+#define BIT_GET_HI5Q_HOST_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_HI5Q_HOST_IDX_8822C) & BIT_MASK_HI5Q_HOST_IDX_8822C)
+#define BIT_SET_HI5Q_HOST_IDX_8822C(x, v) \
+ (BIT_CLEAR_HI5Q_HOST_IDX_8822C(x) | BIT_HI5Q_HOST_IDX_8822C(v))
+
+/* 2 REG_HI6Q_TXBD_IDX_8822C */
+
+#define BIT_SHIFT_HI6Q_HW_IDX_8822C 16
+#define BIT_MASK_HI6Q_HW_IDX_8822C 0xfff
+#define BIT_HI6Q_HW_IDX_8822C(x) \
+ (((x) & BIT_MASK_HI6Q_HW_IDX_8822C) << BIT_SHIFT_HI6Q_HW_IDX_8822C)
+#define BITS_HI6Q_HW_IDX_8822C \
+ (BIT_MASK_HI6Q_HW_IDX_8822C << BIT_SHIFT_HI6Q_HW_IDX_8822C)
+#define BIT_CLEAR_HI6Q_HW_IDX_8822C(x) ((x) & (~BITS_HI6Q_HW_IDX_8822C))
+#define BIT_GET_HI6Q_HW_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_HI6Q_HW_IDX_8822C) & BIT_MASK_HI6Q_HW_IDX_8822C)
+#define BIT_SET_HI6Q_HW_IDX_8822C(x, v) \
+ (BIT_CLEAR_HI6Q_HW_IDX_8822C(x) | BIT_HI6Q_HW_IDX_8822C(v))
+
+#define BIT_SHIFT_HI6Q_HOST_IDX_8822C 0
+#define BIT_MASK_HI6Q_HOST_IDX_8822C 0xfff
+#define BIT_HI6Q_HOST_IDX_8822C(x) \
+ (((x) & BIT_MASK_HI6Q_HOST_IDX_8822C) << BIT_SHIFT_HI6Q_HOST_IDX_8822C)
+#define BITS_HI6Q_HOST_IDX_8822C \
+ (BIT_MASK_HI6Q_HOST_IDX_8822C << BIT_SHIFT_HI6Q_HOST_IDX_8822C)
+#define BIT_CLEAR_HI6Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI6Q_HOST_IDX_8822C))
+#define BIT_GET_HI6Q_HOST_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_HI6Q_HOST_IDX_8822C) & BIT_MASK_HI6Q_HOST_IDX_8822C)
+#define BIT_SET_HI6Q_HOST_IDX_8822C(x, v) \
+ (BIT_CLEAR_HI6Q_HOST_IDX_8822C(x) | BIT_HI6Q_HOST_IDX_8822C(v))
+
+/* 2 REG_HI7Q_TXBD_IDX_8822C */
+
+#define BIT_SHIFT_HI7Q_HW_IDX_8822C 16
+#define BIT_MASK_HI7Q_HW_IDX_8822C 0xfff
+#define BIT_HI7Q_HW_IDX_8822C(x) \
+ (((x) & BIT_MASK_HI7Q_HW_IDX_8822C) << BIT_SHIFT_HI7Q_HW_IDX_8822C)
+#define BITS_HI7Q_HW_IDX_8822C \
+ (BIT_MASK_HI7Q_HW_IDX_8822C << BIT_SHIFT_HI7Q_HW_IDX_8822C)
+#define BIT_CLEAR_HI7Q_HW_IDX_8822C(x) ((x) & (~BITS_HI7Q_HW_IDX_8822C))
+#define BIT_GET_HI7Q_HW_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_HI7Q_HW_IDX_8822C) & BIT_MASK_HI7Q_HW_IDX_8822C)
+#define BIT_SET_HI7Q_HW_IDX_8822C(x, v) \
+ (BIT_CLEAR_HI7Q_HW_IDX_8822C(x) | BIT_HI7Q_HW_IDX_8822C(v))
+
+#define BIT_SHIFT_HI7Q_HOST_IDX_8822C 0
+#define BIT_MASK_HI7Q_HOST_IDX_8822C 0xfff
+#define BIT_HI7Q_HOST_IDX_8822C(x) \
+ (((x) & BIT_MASK_HI7Q_HOST_IDX_8822C) << BIT_SHIFT_HI7Q_HOST_IDX_8822C)
+#define BITS_HI7Q_HOST_IDX_8822C \
+ (BIT_MASK_HI7Q_HOST_IDX_8822C << BIT_SHIFT_HI7Q_HOST_IDX_8822C)
+#define BIT_CLEAR_HI7Q_HOST_IDX_8822C(x) ((x) & (~BITS_HI7Q_HOST_IDX_8822C))
+#define BIT_GET_HI7Q_HOST_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_HI7Q_HOST_IDX_8822C) & BIT_MASK_HI7Q_HOST_IDX_8822C)
+#define BIT_SET_HI7Q_HOST_IDX_8822C(x, v) \
+ (BIT_CLEAR_HI7Q_HOST_IDX_8822C(x) | BIT_HI7Q_HOST_IDX_8822C(v))
+
+/* 2 REG_DBG_SEL_V1_8822C */
+
+#define BIT_SHIFT_DBG_SEL_8822C 0
+#define BIT_MASK_DBG_SEL_8822C 0xff
+#define BIT_DBG_SEL_8822C(x) \
+ (((x) & BIT_MASK_DBG_SEL_8822C) << BIT_SHIFT_DBG_SEL_8822C)
+#define BITS_DBG_SEL_8822C (BIT_MASK_DBG_SEL_8822C << BIT_SHIFT_DBG_SEL_8822C)
+#define BIT_CLEAR_DBG_SEL_8822C(x) ((x) & (~BITS_DBG_SEL_8822C))
+#define BIT_GET_DBG_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_DBG_SEL_8822C) & BIT_MASK_DBG_SEL_8822C)
+#define BIT_SET_DBG_SEL_8822C(x, v) \
+ (BIT_CLEAR_DBG_SEL_8822C(x) | BIT_DBG_SEL_8822C(v))
+
+/* 2 REG_PCIE_HRPWM1_V1_8822C */
+
+#define BIT_SHIFT_PCIE_HRPWM_8822C 0
+#define BIT_MASK_PCIE_HRPWM_8822C 0xff
+#define BIT_PCIE_HRPWM_8822C(x) \
+ (((x) & BIT_MASK_PCIE_HRPWM_8822C) << BIT_SHIFT_PCIE_HRPWM_8822C)
+#define BITS_PCIE_HRPWM_8822C \
+ (BIT_MASK_PCIE_HRPWM_8822C << BIT_SHIFT_PCIE_HRPWM_8822C)
+#define BIT_CLEAR_PCIE_HRPWM_8822C(x) ((x) & (~BITS_PCIE_HRPWM_8822C))
+#define BIT_GET_PCIE_HRPWM_8822C(x) \
+ (((x) >> BIT_SHIFT_PCIE_HRPWM_8822C) & BIT_MASK_PCIE_HRPWM_8822C)
+#define BIT_SET_PCIE_HRPWM_8822C(x, v) \
+ (BIT_CLEAR_PCIE_HRPWM_8822C(x) | BIT_PCIE_HRPWM_8822C(v))
+
+/* 2 REG_PCIE_HCPWM1_V1_8822C */
+
+#define BIT_SHIFT_PCIE_HCPWM_8822C 0
+#define BIT_MASK_PCIE_HCPWM_8822C 0xff
+#define BIT_PCIE_HCPWM_8822C(x) \
+ (((x) & BIT_MASK_PCIE_HCPWM_8822C) << BIT_SHIFT_PCIE_HCPWM_8822C)
+#define BITS_PCIE_HCPWM_8822C \
+ (BIT_MASK_PCIE_HCPWM_8822C << BIT_SHIFT_PCIE_HCPWM_8822C)
+#define BIT_CLEAR_PCIE_HCPWM_8822C(x) ((x) & (~BITS_PCIE_HCPWM_8822C))
+#define BIT_GET_PCIE_HCPWM_8822C(x) \
+ (((x) >> BIT_SHIFT_PCIE_HCPWM_8822C) & BIT_MASK_PCIE_HCPWM_8822C)
+#define BIT_SET_PCIE_HCPWM_8822C(x, v) \
+ (BIT_CLEAR_PCIE_HCPWM_8822C(x) | BIT_PCIE_HCPWM_8822C(v))
+
+/* 2 REG_PCIE_CTRL2_8822C */
+#define BIT_DIS_TXDMA_PRE_8822C BIT(7)
+#define BIT_DIS_RXDMA_PRE_8822C BIT(6)
+
+#define BIT_SHIFT_HPS_CLKR_PCIE_8822C 4
+#define BIT_MASK_HPS_CLKR_PCIE_8822C 0x3
+#define BIT_HPS_CLKR_PCIE_8822C(x) \
+ (((x) & BIT_MASK_HPS_CLKR_PCIE_8822C) << BIT_SHIFT_HPS_CLKR_PCIE_8822C)
+#define BITS_HPS_CLKR_PCIE_8822C \
+ (BIT_MASK_HPS_CLKR_PCIE_8822C << BIT_SHIFT_HPS_CLKR_PCIE_8822C)
+#define BIT_CLEAR_HPS_CLKR_PCIE_8822C(x) ((x) & (~BITS_HPS_CLKR_PCIE_8822C))
+#define BIT_GET_HPS_CLKR_PCIE_8822C(x) \
+ (((x) >> BIT_SHIFT_HPS_CLKR_PCIE_8822C) & BIT_MASK_HPS_CLKR_PCIE_8822C)
+#define BIT_SET_HPS_CLKR_PCIE_8822C(x, v) \
+ (BIT_CLEAR_HPS_CLKR_PCIE_8822C(x) | BIT_HPS_CLKR_PCIE_8822C(v))
+
+#define BIT_PCIE_INT_8822C BIT(3)
+#define BIT_TXFLAG_EXIT_L1_EN_8822C BIT(2)
+#define BIT_EN_RXDMA_ALIGN_8822C BIT(1)
+#define BIT_EN_TXDMA_ALIGN_8822C BIT(0)
+
+/* 2 REG_PCIE_HRPWM2_V1_8822C */
+
+#define BIT_SHIFT_PCIE_HRPWM2_8822C 0
+#define BIT_MASK_PCIE_HRPWM2_8822C 0xffff
+#define BIT_PCIE_HRPWM2_8822C(x) \
+ (((x) & BIT_MASK_PCIE_HRPWM2_8822C) << BIT_SHIFT_PCIE_HRPWM2_8822C)
+#define BITS_PCIE_HRPWM2_8822C \
+ (BIT_MASK_PCIE_HRPWM2_8822C << BIT_SHIFT_PCIE_HRPWM2_8822C)
+#define BIT_CLEAR_PCIE_HRPWM2_8822C(x) ((x) & (~BITS_PCIE_HRPWM2_8822C))
+#define BIT_GET_PCIE_HRPWM2_8822C(x) \
+ (((x) >> BIT_SHIFT_PCIE_HRPWM2_8822C) & BIT_MASK_PCIE_HRPWM2_8822C)
+#define BIT_SET_PCIE_HRPWM2_8822C(x, v) \
+ (BIT_CLEAR_PCIE_HRPWM2_8822C(x) | BIT_PCIE_HRPWM2_8822C(v))
+
+/* 2 REG_PCIE_HCPWM2_V1_8822C */
+
+#define BIT_SHIFT_PCIE_HCPWM2_8822C 0
+#define BIT_MASK_PCIE_HCPWM2_8822C 0xffff
+#define BIT_PCIE_HCPWM2_8822C(x) \
+ (((x) & BIT_MASK_PCIE_HCPWM2_8822C) << BIT_SHIFT_PCIE_HCPWM2_8822C)
+#define BITS_PCIE_HCPWM2_8822C \
+ (BIT_MASK_PCIE_HCPWM2_8822C << BIT_SHIFT_PCIE_HCPWM2_8822C)
+#define BIT_CLEAR_PCIE_HCPWM2_8822C(x) ((x) & (~BITS_PCIE_HCPWM2_8822C))
+#define BIT_GET_PCIE_HCPWM2_8822C(x) \
+ (((x) >> BIT_SHIFT_PCIE_HCPWM2_8822C) & BIT_MASK_PCIE_HCPWM2_8822C)
+#define BIT_SET_PCIE_HCPWM2_8822C(x, v) \
+ (BIT_CLEAR_PCIE_HCPWM2_8822C(x) | BIT_PCIE_HCPWM2_8822C(v))
+
+/* 2 REG_PCIE_H2C_MSG_V1_8822C */
+
+#define BIT_SHIFT_DRV2FW_INFO_8822C 0
+#define BIT_MASK_DRV2FW_INFO_8822C 0xffffffffL
+#define BIT_DRV2FW_INFO_8822C(x) \
+ (((x) & BIT_MASK_DRV2FW_INFO_8822C) << BIT_SHIFT_DRV2FW_INFO_8822C)
+#define BITS_DRV2FW_INFO_8822C \
+ (BIT_MASK_DRV2FW_INFO_8822C << BIT_SHIFT_DRV2FW_INFO_8822C)
+#define BIT_CLEAR_DRV2FW_INFO_8822C(x) ((x) & (~BITS_DRV2FW_INFO_8822C))
+#define BIT_GET_DRV2FW_INFO_8822C(x) \
+ (((x) >> BIT_SHIFT_DRV2FW_INFO_8822C) & BIT_MASK_DRV2FW_INFO_8822C)
+#define BIT_SET_DRV2FW_INFO_8822C(x, v) \
+ (BIT_CLEAR_DRV2FW_INFO_8822C(x) | BIT_DRV2FW_INFO_8822C(v))
+
+/* 2 REG_PCIE_C2H_MSG_V1_8822C */
+
+#define BIT_SHIFT_HCI_PCIE_C2H_MSG_8822C 0
+#define BIT_MASK_HCI_PCIE_C2H_MSG_8822C 0xffffffffL
+#define BIT_HCI_PCIE_C2H_MSG_8822C(x) \
+ (((x) & BIT_MASK_HCI_PCIE_C2H_MSG_8822C) \
+ << BIT_SHIFT_HCI_PCIE_C2H_MSG_8822C)
+#define BITS_HCI_PCIE_C2H_MSG_8822C \
+ (BIT_MASK_HCI_PCIE_C2H_MSG_8822C << BIT_SHIFT_HCI_PCIE_C2H_MSG_8822C)
+#define BIT_CLEAR_HCI_PCIE_C2H_MSG_8822C(x) \
+ ((x) & (~BITS_HCI_PCIE_C2H_MSG_8822C))
+#define BIT_GET_HCI_PCIE_C2H_MSG_8822C(x) \
+ (((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG_8822C) & \
+ BIT_MASK_HCI_PCIE_C2H_MSG_8822C)
+#define BIT_SET_HCI_PCIE_C2H_MSG_8822C(x, v) \
+ (BIT_CLEAR_HCI_PCIE_C2H_MSG_8822C(x) | BIT_HCI_PCIE_C2H_MSG_8822C(v))
+
+/* 2 REG_DBI_WDATA_V1_8822C */
+
+#define BIT_SHIFT_DBI_WDATA_8822C 0
+#define BIT_MASK_DBI_WDATA_8822C 0xffffffffL
+#define BIT_DBI_WDATA_8822C(x) \
+ (((x) & BIT_MASK_DBI_WDATA_8822C) << BIT_SHIFT_DBI_WDATA_8822C)
+#define BITS_DBI_WDATA_8822C \
+ (BIT_MASK_DBI_WDATA_8822C << BIT_SHIFT_DBI_WDATA_8822C)
+#define BIT_CLEAR_DBI_WDATA_8822C(x) ((x) & (~BITS_DBI_WDATA_8822C))
+#define BIT_GET_DBI_WDATA_8822C(x) \
+ (((x) >> BIT_SHIFT_DBI_WDATA_8822C) & BIT_MASK_DBI_WDATA_8822C)
+#define BIT_SET_DBI_WDATA_8822C(x, v) \
+ (BIT_CLEAR_DBI_WDATA_8822C(x) | BIT_DBI_WDATA_8822C(v))
+
+/* 2 REG_DBI_RDATA_V1_8822C */
+
+#define BIT_SHIFT_DBI_RDATA_8822C 0
+#define BIT_MASK_DBI_RDATA_8822C 0xffffffffL
+#define BIT_DBI_RDATA_8822C(x) \
+ (((x) & BIT_MASK_DBI_RDATA_8822C) << BIT_SHIFT_DBI_RDATA_8822C)
+#define BITS_DBI_RDATA_8822C \
+ (BIT_MASK_DBI_RDATA_8822C << BIT_SHIFT_DBI_RDATA_8822C)
+#define BIT_CLEAR_DBI_RDATA_8822C(x) ((x) & (~BITS_DBI_RDATA_8822C))
+#define BIT_GET_DBI_RDATA_8822C(x) \
+ (((x) >> BIT_SHIFT_DBI_RDATA_8822C) & BIT_MASK_DBI_RDATA_8822C)
+#define BIT_SET_DBI_RDATA_8822C(x, v) \
+ (BIT_CLEAR_DBI_RDATA_8822C(x) | BIT_DBI_RDATA_8822C(v))
+
+/* 2 REG_DBI_FLAG_V1_8822C */
+#define BIT_EN_STUCK_DBG_8822C BIT(26)
+#define BIT_RX_STUCK_8822C BIT(25)
+#define BIT_TX_STUCK_8822C BIT(24)
+#define BIT_DBI_RFLAG_8822C BIT(17)
+#define BIT_DBI_WFLAG_8822C BIT(16)
+
+#define BIT_SHIFT_DBI_WREN_8822C 12
+#define BIT_MASK_DBI_WREN_8822C 0xf
+#define BIT_DBI_WREN_8822C(x) \
+ (((x) & BIT_MASK_DBI_WREN_8822C) << BIT_SHIFT_DBI_WREN_8822C)
+#define BITS_DBI_WREN_8822C \
+ (BIT_MASK_DBI_WREN_8822C << BIT_SHIFT_DBI_WREN_8822C)
+#define BIT_CLEAR_DBI_WREN_8822C(x) ((x) & (~BITS_DBI_WREN_8822C))
+#define BIT_GET_DBI_WREN_8822C(x) \
+ (((x) >> BIT_SHIFT_DBI_WREN_8822C) & BIT_MASK_DBI_WREN_8822C)
+#define BIT_SET_DBI_WREN_8822C(x, v) \
+ (BIT_CLEAR_DBI_WREN_8822C(x) | BIT_DBI_WREN_8822C(v))
+
+#define BIT_SHIFT_DBI_ADDR_8822C 0
+#define BIT_MASK_DBI_ADDR_8822C 0xfff
+#define BIT_DBI_ADDR_8822C(x) \
+ (((x) & BIT_MASK_DBI_ADDR_8822C) << BIT_SHIFT_DBI_ADDR_8822C)
+#define BITS_DBI_ADDR_8822C \
+ (BIT_MASK_DBI_ADDR_8822C << BIT_SHIFT_DBI_ADDR_8822C)
+#define BIT_CLEAR_DBI_ADDR_8822C(x) ((x) & (~BITS_DBI_ADDR_8822C))
+#define BIT_GET_DBI_ADDR_8822C(x) \
+ (((x) >> BIT_SHIFT_DBI_ADDR_8822C) & BIT_MASK_DBI_ADDR_8822C)
+#define BIT_SET_DBI_ADDR_8822C(x, v) \
+ (BIT_CLEAR_DBI_ADDR_8822C(x) | BIT_DBI_ADDR_8822C(v))
+
+/* 2 REG_MDIO_V1_8822C */
+
+#define BIT_SHIFT_MDIO_RDATA_8822C 16
+#define BIT_MASK_MDIO_RDATA_8822C 0xffff
+#define BIT_MDIO_RDATA_8822C(x) \
+ (((x) & BIT_MASK_MDIO_RDATA_8822C) << BIT_SHIFT_MDIO_RDATA_8822C)
+#define BITS_MDIO_RDATA_8822C \
+ (BIT_MASK_MDIO_RDATA_8822C << BIT_SHIFT_MDIO_RDATA_8822C)
+#define BIT_CLEAR_MDIO_RDATA_8822C(x) ((x) & (~BITS_MDIO_RDATA_8822C))
+#define BIT_GET_MDIO_RDATA_8822C(x) \
+ (((x) >> BIT_SHIFT_MDIO_RDATA_8822C) & BIT_MASK_MDIO_RDATA_8822C)
+#define BIT_SET_MDIO_RDATA_8822C(x, v) \
+ (BIT_CLEAR_MDIO_RDATA_8822C(x) | BIT_MDIO_RDATA_8822C(v))
+
+#define BIT_SHIFT_MDIO_WDATA_8822C 0
+#define BIT_MASK_MDIO_WDATA_8822C 0xffff
+#define BIT_MDIO_WDATA_8822C(x) \
+ (((x) & BIT_MASK_MDIO_WDATA_8822C) << BIT_SHIFT_MDIO_WDATA_8822C)
+#define BITS_MDIO_WDATA_8822C \
+ (BIT_MASK_MDIO_WDATA_8822C << BIT_SHIFT_MDIO_WDATA_8822C)
+#define BIT_CLEAR_MDIO_WDATA_8822C(x) ((x) & (~BITS_MDIO_WDATA_8822C))
+#define BIT_GET_MDIO_WDATA_8822C(x) \
+ (((x) >> BIT_SHIFT_MDIO_WDATA_8822C) & BIT_MASK_MDIO_WDATA_8822C)
+#define BIT_SET_MDIO_WDATA_8822C(x, v) \
+ (BIT_CLEAR_MDIO_WDATA_8822C(x) | BIT_MDIO_WDATA_8822C(v))
+
+/* 2 REG_PCIE_MIX_CFG_8822C */
+
+#define BIT_SHIFT_MDIO_PHY_ADDR_8822C 24
+#define BIT_MASK_MDIO_PHY_ADDR_8822C 0x1f
+#define BIT_MDIO_PHY_ADDR_8822C(x) \
+ (((x) & BIT_MASK_MDIO_PHY_ADDR_8822C) << BIT_SHIFT_MDIO_PHY_ADDR_8822C)
+#define BITS_MDIO_PHY_ADDR_8822C \
+ (BIT_MASK_MDIO_PHY_ADDR_8822C << BIT_SHIFT_MDIO_PHY_ADDR_8822C)
+#define BIT_CLEAR_MDIO_PHY_ADDR_8822C(x) ((x) & (~BITS_MDIO_PHY_ADDR_8822C))
+#define BIT_GET_MDIO_PHY_ADDR_8822C(x) \
+ (((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8822C) & BIT_MASK_MDIO_PHY_ADDR_8822C)
+#define BIT_SET_MDIO_PHY_ADDR_8822C(x, v) \
+ (BIT_CLEAR_MDIO_PHY_ADDR_8822C(x) | BIT_MDIO_PHY_ADDR_8822C(v))
+
+#define BIT_SHIFT_WATCH_DOG_RECORD_V1_8822C 10
+#define BIT_MASK_WATCH_DOG_RECORD_V1_8822C 0x3fff
+#define BIT_WATCH_DOG_RECORD_V1_8822C(x) \
+ (((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8822C) \
+ << BIT_SHIFT_WATCH_DOG_RECORD_V1_8822C)
+#define BITS_WATCH_DOG_RECORD_V1_8822C \
+ (BIT_MASK_WATCH_DOG_RECORD_V1_8822C \
+ << BIT_SHIFT_WATCH_DOG_RECORD_V1_8822C)
+#define BIT_CLEAR_WATCH_DOG_RECORD_V1_8822C(x) \
+ ((x) & (~BITS_WATCH_DOG_RECORD_V1_8822C))
+#define BIT_GET_WATCH_DOG_RECORD_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8822C) & \
+ BIT_MASK_WATCH_DOG_RECORD_V1_8822C)
+#define BIT_SET_WATCH_DOG_RECORD_V1_8822C(x, v) \
+ (BIT_CLEAR_WATCH_DOG_RECORD_V1_8822C(x) | \
+ BIT_WATCH_DOG_RECORD_V1_8822C(v))
+
+#define BIT_R_IO_TIMEOUT_FLAG_V1_8822C BIT(9)
+#define BIT_EN_WATCH_DOG_8822C BIT(8)
+#define BIT_ECRC_EN_V1_8822C BIT(7)
+#define BIT_MDIO_RFLAG_V1_8822C BIT(6)
+#define BIT_MDIO_WFLAG_V1_8822C BIT(5)
+
+#define BIT_SHIFT_MDIO_REG_ADDR_V1_8822C 0
+#define BIT_MASK_MDIO_REG_ADDR_V1_8822C 0x1f
+#define BIT_MDIO_REG_ADDR_V1_8822C(x) \
+ (((x) & BIT_MASK_MDIO_REG_ADDR_V1_8822C) \
+ << BIT_SHIFT_MDIO_REG_ADDR_V1_8822C)
+#define BITS_MDIO_REG_ADDR_V1_8822C \
+ (BIT_MASK_MDIO_REG_ADDR_V1_8822C << BIT_SHIFT_MDIO_REG_ADDR_V1_8822C)
+#define BIT_CLEAR_MDIO_REG_ADDR_V1_8822C(x) \
+ ((x) & (~BITS_MDIO_REG_ADDR_V1_8822C))
+#define BIT_GET_MDIO_REG_ADDR_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1_8822C) & \
+ BIT_MASK_MDIO_REG_ADDR_V1_8822C)
+#define BIT_SET_MDIO_REG_ADDR_V1_8822C(x, v) \
+ (BIT_CLEAR_MDIO_REG_ADDR_V1_8822C(x) | BIT_MDIO_REG_ADDR_V1_8822C(v))
+
+/* 2 REG_HCI_MIX_CFG_8822C */
+
+#define BIT_SHIFT_WATCH_DOG_TIMER_8822C 28
+#define BIT_MASK_WATCH_DOG_TIMER_8822C 0xf
+#define BIT_WATCH_DOG_TIMER_8822C(x) \
+ (((x) & BIT_MASK_WATCH_DOG_TIMER_8822C) \
+ << BIT_SHIFT_WATCH_DOG_TIMER_8822C)
+#define BITS_WATCH_DOG_TIMER_8822C \
+ (BIT_MASK_WATCH_DOG_TIMER_8822C << BIT_SHIFT_WATCH_DOG_TIMER_8822C)
+#define BIT_CLEAR_WATCH_DOG_TIMER_8822C(x) ((x) & (~BITS_WATCH_DOG_TIMER_8822C))
+#define BIT_GET_WATCH_DOG_TIMER_8822C(x) \
+ (((x) >> BIT_SHIFT_WATCH_DOG_TIMER_8822C) & \
+ BIT_MASK_WATCH_DOG_TIMER_8822C)
+#define BIT_SET_WATCH_DOG_TIMER_8822C(x, v) \
+ (BIT_CLEAR_WATCH_DOG_TIMER_8822C(x) | BIT_WATCH_DOG_TIMER_8822C(v))
+
+#define BIT_EN_ALIGN_MTU_8822C BIT(23)
+
+#define BIT_SHIFT_LATENCY_CONTROL_8822C 21
+#define BIT_MASK_LATENCY_CONTROL_8822C 0x3
+#define BIT_LATENCY_CONTROL_8822C(x) \
+ (((x) & BIT_MASK_LATENCY_CONTROL_8822C) \
+ << BIT_SHIFT_LATENCY_CONTROL_8822C)
+#define BITS_LATENCY_CONTROL_8822C \
+ (BIT_MASK_LATENCY_CONTROL_8822C << BIT_SHIFT_LATENCY_CONTROL_8822C)
+#define BIT_CLEAR_LATENCY_CONTROL_8822C(x) ((x) & (~BITS_LATENCY_CONTROL_8822C))
+#define BIT_GET_LATENCY_CONTROL_8822C(x) \
+ (((x) >> BIT_SHIFT_LATENCY_CONTROL_8822C) & \
+ BIT_MASK_LATENCY_CONTROL_8822C)
+#define BIT_SET_LATENCY_CONTROL_8822C(x, v) \
+ (BIT_CLEAR_LATENCY_CONTROL_8822C(x) | BIT_LATENCY_CONTROL_8822C(v))
+
+#define BIT_HOST_GEN2_SUPPORT_8822C BIT(20)
+
+#define BIT_SHIFT_TXDMA_ERR_FLAG_V1_8822C 15
+#define BIT_MASK_TXDMA_ERR_FLAG_V1_8822C 0x1f
+#define BIT_TXDMA_ERR_FLAG_V1_8822C(x) \
+ (((x) & BIT_MASK_TXDMA_ERR_FLAG_V1_8822C) \
+ << BIT_SHIFT_TXDMA_ERR_FLAG_V1_8822C)
+#define BITS_TXDMA_ERR_FLAG_V1_8822C \
+ (BIT_MASK_TXDMA_ERR_FLAG_V1_8822C << BIT_SHIFT_TXDMA_ERR_FLAG_V1_8822C)
+#define BIT_CLEAR_TXDMA_ERR_FLAG_V1_8822C(x) \
+ ((x) & (~BITS_TXDMA_ERR_FLAG_V1_8822C))
+#define BIT_GET_TXDMA_ERR_FLAG_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_V1_8822C) & \
+ BIT_MASK_TXDMA_ERR_FLAG_V1_8822C)
+#define BIT_SET_TXDMA_ERR_FLAG_V1_8822C(x, v) \
+ (BIT_CLEAR_TXDMA_ERR_FLAG_V1_8822C(x) | BIT_TXDMA_ERR_FLAG_V1_8822C(v))
+
+#define BIT_EPHY_RX50_EN_8822C BIT(11)
+
+#define BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822C 8
+#define BIT_MASK_MSI_TIMEOUT_ID_V1_8822C 0x7
+#define BIT_MSI_TIMEOUT_ID_V1_8822C(x) \
+ (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8822C) \
+ << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822C)
+#define BITS_MSI_TIMEOUT_ID_V1_8822C \
+ (BIT_MASK_MSI_TIMEOUT_ID_V1_8822C << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822C)
+#define BIT_CLEAR_MSI_TIMEOUT_ID_V1_8822C(x) \
+ ((x) & (~BITS_MSI_TIMEOUT_ID_V1_8822C))
+#define BIT_GET_MSI_TIMEOUT_ID_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8822C) & \
+ BIT_MASK_MSI_TIMEOUT_ID_V1_8822C)
+#define BIT_SET_MSI_TIMEOUT_ID_V1_8822C(x, v) \
+ (BIT_CLEAR_MSI_TIMEOUT_ID_V1_8822C(x) | BIT_MSI_TIMEOUT_ID_V1_8822C(v))
+
+#define BIT_RADDR_RD_8822C BIT(7)
+#define BIT_L1OFF_PWR_OFF_EN_8822C BIT(6)
+#define BIT_L0S_LINK_OFF_8822C BIT(4)
+#define BIT_ACT_LINK_OFF_8822C BIT(3)
+#define BIT_EN_SLOW_MAC_TX_8822C BIT(2)
+#define BIT_EN_SLOW_MAC_RX_8822C BIT(1)
+#define BIT_EN_SLOW_MAC_HW_8822C BIT(0)
+
+/* 2 REG_STC_INT_CS_8822C(PCIE STATE CHANGE INTERRUPT CONTROL AND STATUS) */
+#define BIT_STC_INT_EN_8822C BIT(31)
+
+#define BIT_SHIFT_STC_INT_FLAG_8822C 16
+#define BIT_MASK_STC_INT_FLAG_8822C 0xff
+#define BIT_STC_INT_FLAG_8822C(x) \
+ (((x) & BIT_MASK_STC_INT_FLAG_8822C) << BIT_SHIFT_STC_INT_FLAG_8822C)
+#define BITS_STC_INT_FLAG_8822C \
+ (BIT_MASK_STC_INT_FLAG_8822C << BIT_SHIFT_STC_INT_FLAG_8822C)
+#define BIT_CLEAR_STC_INT_FLAG_8822C(x) ((x) & (~BITS_STC_INT_FLAG_8822C))
+#define BIT_GET_STC_INT_FLAG_8822C(x) \
+ (((x) >> BIT_SHIFT_STC_INT_FLAG_8822C) & BIT_MASK_STC_INT_FLAG_8822C)
+#define BIT_SET_STC_INT_FLAG_8822C(x, v) \
+ (BIT_CLEAR_STC_INT_FLAG_8822C(x) | BIT_STC_INT_FLAG_8822C(v))
+
+#define BIT_SHIFT_STC_INT_IDX_8822C 8
+#define BIT_MASK_STC_INT_IDX_8822C 0x7
+#define BIT_STC_INT_IDX_8822C(x) \
+ (((x) & BIT_MASK_STC_INT_IDX_8822C) << BIT_SHIFT_STC_INT_IDX_8822C)
+#define BITS_STC_INT_IDX_8822C \
+ (BIT_MASK_STC_INT_IDX_8822C << BIT_SHIFT_STC_INT_IDX_8822C)
+#define BIT_CLEAR_STC_INT_IDX_8822C(x) ((x) & (~BITS_STC_INT_IDX_8822C))
+#define BIT_GET_STC_INT_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_STC_INT_IDX_8822C) & BIT_MASK_STC_INT_IDX_8822C)
+#define BIT_SET_STC_INT_IDX_8822C(x, v) \
+ (BIT_CLEAR_STC_INT_IDX_8822C(x) | BIT_STC_INT_IDX_8822C(v))
+
+#define BIT_SHIFT_STC_INT_REALTIME_CS_8822C 0
+#define BIT_MASK_STC_INT_REALTIME_CS_8822C 0x3f
+#define BIT_STC_INT_REALTIME_CS_8822C(x) \
+ (((x) & BIT_MASK_STC_INT_REALTIME_CS_8822C) \
+ << BIT_SHIFT_STC_INT_REALTIME_CS_8822C)
+#define BITS_STC_INT_REALTIME_CS_8822C \
+ (BIT_MASK_STC_INT_REALTIME_CS_8822C \
+ << BIT_SHIFT_STC_INT_REALTIME_CS_8822C)
+#define BIT_CLEAR_STC_INT_REALTIME_CS_8822C(x) \
+ ((x) & (~BITS_STC_INT_REALTIME_CS_8822C))
+#define BIT_GET_STC_INT_REALTIME_CS_8822C(x) \
+ (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8822C) & \
+ BIT_MASK_STC_INT_REALTIME_CS_8822C)
+#define BIT_SET_STC_INT_REALTIME_CS_8822C(x, v) \
+ (BIT_CLEAR_STC_INT_REALTIME_CS_8822C(x) | \
+ BIT_STC_INT_REALTIME_CS_8822C(v))
+
+#define BIT_STC_INT_GRP_EN_8822C BIT(31)
+
+#define BIT_SHIFT_STC_INT_EXPECT_LS_8822C 8
+#define BIT_MASK_STC_INT_EXPECT_LS_8822C 0x3f
+#define BIT_STC_INT_EXPECT_LS_8822C(x) \
+ (((x) & BIT_MASK_STC_INT_EXPECT_LS_8822C) \
+ << BIT_SHIFT_STC_INT_EXPECT_LS_8822C)
+#define BITS_STC_INT_EXPECT_LS_8822C \
+ (BIT_MASK_STC_INT_EXPECT_LS_8822C << BIT_SHIFT_STC_INT_EXPECT_LS_8822C)
+#define BIT_CLEAR_STC_INT_EXPECT_LS_8822C(x) \
+ ((x) & (~BITS_STC_INT_EXPECT_LS_8822C))
+#define BIT_GET_STC_INT_EXPECT_LS_8822C(x) \
+ (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8822C) & \
+ BIT_MASK_STC_INT_EXPECT_LS_8822C)
+#define BIT_SET_STC_INT_EXPECT_LS_8822C(x, v) \
+ (BIT_CLEAR_STC_INT_EXPECT_LS_8822C(x) | BIT_STC_INT_EXPECT_LS_8822C(v))
+
+#define BIT_SHIFT_STC_INT_EXPECT_CS_8822C 0
+#define BIT_MASK_STC_INT_EXPECT_CS_8822C 0x3f
+#define BIT_STC_INT_EXPECT_CS_8822C(x) \
+ (((x) & BIT_MASK_STC_INT_EXPECT_CS_8822C) \
+ << BIT_SHIFT_STC_INT_EXPECT_CS_8822C)
+#define BITS_STC_INT_EXPECT_CS_8822C \
+ (BIT_MASK_STC_INT_EXPECT_CS_8822C << BIT_SHIFT_STC_INT_EXPECT_CS_8822C)
+#define BIT_CLEAR_STC_INT_EXPECT_CS_8822C(x) \
+ ((x) & (~BITS_STC_INT_EXPECT_CS_8822C))
+#define BIT_GET_STC_INT_EXPECT_CS_8822C(x) \
+ (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8822C) & \
+ BIT_MASK_STC_INT_EXPECT_CS_8822C)
+#define BIT_SET_STC_INT_EXPECT_CS_8822C(x, v) \
+ (BIT_CLEAR_STC_INT_EXPECT_CS_8822C(x) | BIT_STC_INT_EXPECT_CS_8822C(v))
+
+/* 2 REG_H2CQ_TXBD_DESA_8822C */
+
+#define BIT_SHIFT_H2CQ_TXBD_DESA_8822C 0
+#define BIT_MASK_H2CQ_TXBD_DESA_8822C 0xffffffffffffffffL
+#define BIT_H2CQ_TXBD_DESA_8822C(x) \
+ (((x) & BIT_MASK_H2CQ_TXBD_DESA_8822C) \
+ << BIT_SHIFT_H2CQ_TXBD_DESA_8822C)
+#define BITS_H2CQ_TXBD_DESA_8822C \
+ (BIT_MASK_H2CQ_TXBD_DESA_8822C << BIT_SHIFT_H2CQ_TXBD_DESA_8822C)
+#define BIT_CLEAR_H2CQ_TXBD_DESA_8822C(x) ((x) & (~BITS_H2CQ_TXBD_DESA_8822C))
+#define BIT_GET_H2CQ_TXBD_DESA_8822C(x) \
+ (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_8822C) & \
+ BIT_MASK_H2CQ_TXBD_DESA_8822C)
+#define BIT_SET_H2CQ_TXBD_DESA_8822C(x, v) \
+ (BIT_CLEAR_H2CQ_TXBD_DESA_8822C(x) | BIT_H2CQ_TXBD_DESA_8822C(v))
+
+/* 2 REG_H2CQ_TXBD_NUM_8822C */
+#define BIT_PCIE_H2CQ_FLAG_8822C BIT(14)
+
+#define BIT_SHIFT_H2CQ_DESC_MODE_8822C 12
+#define BIT_MASK_H2CQ_DESC_MODE_8822C 0x3
+#define BIT_H2CQ_DESC_MODE_8822C(x) \
+ (((x) & BIT_MASK_H2CQ_DESC_MODE_8822C) \
+ << BIT_SHIFT_H2CQ_DESC_MODE_8822C)
+#define BITS_H2CQ_DESC_MODE_8822C \
+ (BIT_MASK_H2CQ_DESC_MODE_8822C << BIT_SHIFT_H2CQ_DESC_MODE_8822C)
+#define BIT_CLEAR_H2CQ_DESC_MODE_8822C(x) ((x) & (~BITS_H2CQ_DESC_MODE_8822C))
+#define BIT_GET_H2CQ_DESC_MODE_8822C(x) \
+ (((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8822C) & \
+ BIT_MASK_H2CQ_DESC_MODE_8822C)
+#define BIT_SET_H2CQ_DESC_MODE_8822C(x, v) \
+ (BIT_CLEAR_H2CQ_DESC_MODE_8822C(x) | BIT_H2CQ_DESC_MODE_8822C(v))
+
+#define BIT_SHIFT_H2CQ_DESC_NUM_8822C 0
+#define BIT_MASK_H2CQ_DESC_NUM_8822C 0xfff
+#define BIT_H2CQ_DESC_NUM_8822C(x) \
+ (((x) & BIT_MASK_H2CQ_DESC_NUM_8822C) << BIT_SHIFT_H2CQ_DESC_NUM_8822C)
+#define BITS_H2CQ_DESC_NUM_8822C \
+ (BIT_MASK_H2CQ_DESC_NUM_8822C << BIT_SHIFT_H2CQ_DESC_NUM_8822C)
+#define BIT_CLEAR_H2CQ_DESC_NUM_8822C(x) ((x) & (~BITS_H2CQ_DESC_NUM_8822C))
+#define BIT_GET_H2CQ_DESC_NUM_8822C(x) \
+ (((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8822C) & BIT_MASK_H2CQ_DESC_NUM_8822C)
+#define BIT_SET_H2CQ_DESC_NUM_8822C(x, v) \
+ (BIT_CLEAR_H2CQ_DESC_NUM_8822C(x) | BIT_H2CQ_DESC_NUM_8822C(v))
+
+/* 2 REG_H2CQ_TXBD_IDX_8822C */
+
+#define BIT_SHIFT_H2CQ_HW_IDX_8822C 16
+#define BIT_MASK_H2CQ_HW_IDX_8822C 0xfff
+#define BIT_H2CQ_HW_IDX_8822C(x) \
+ (((x) & BIT_MASK_H2CQ_HW_IDX_8822C) << BIT_SHIFT_H2CQ_HW_IDX_8822C)
+#define BITS_H2CQ_HW_IDX_8822C \
+ (BIT_MASK_H2CQ_HW_IDX_8822C << BIT_SHIFT_H2CQ_HW_IDX_8822C)
+#define BIT_CLEAR_H2CQ_HW_IDX_8822C(x) ((x) & (~BITS_H2CQ_HW_IDX_8822C))
+#define BIT_GET_H2CQ_HW_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_H2CQ_HW_IDX_8822C) & BIT_MASK_H2CQ_HW_IDX_8822C)
+#define BIT_SET_H2CQ_HW_IDX_8822C(x, v) \
+ (BIT_CLEAR_H2CQ_HW_IDX_8822C(x) | BIT_H2CQ_HW_IDX_8822C(v))
+
+#define BIT_SHIFT_H2CQ_HOST_IDX_8822C 0
+#define BIT_MASK_H2CQ_HOST_IDX_8822C 0xfff
+#define BIT_H2CQ_HOST_IDX_8822C(x) \
+ (((x) & BIT_MASK_H2CQ_HOST_IDX_8822C) << BIT_SHIFT_H2CQ_HOST_IDX_8822C)
+#define BITS_H2CQ_HOST_IDX_8822C \
+ (BIT_MASK_H2CQ_HOST_IDX_8822C << BIT_SHIFT_H2CQ_HOST_IDX_8822C)
+#define BIT_CLEAR_H2CQ_HOST_IDX_8822C(x) ((x) & (~BITS_H2CQ_HOST_IDX_8822C))
+#define BIT_GET_H2CQ_HOST_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8822C) & BIT_MASK_H2CQ_HOST_IDX_8822C)
+#define BIT_SET_H2CQ_HOST_IDX_8822C(x, v) \
+ (BIT_CLEAR_H2CQ_HOST_IDX_8822C(x) | BIT_H2CQ_HOST_IDX_8822C(v))
+
+/* 2 REG_H2CQ_CSR_8822C[31:0] (H2CQ CONTROL AND STATUS) */
+#define BIT_H2CQ_FULL_8822C BIT(31)
+#define BIT_CLR_H2CQ_HOST_IDX_8822C BIT(16)
+#define BIT_CLR_H2CQ_HW_IDX_8822C BIT(8)
+#define BIT_STOP_H2CQ_8822C BIT(0)
+
+/* 2 REG_CHANGE_PCIE_SPEED_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_RXDMA_ERR_CNT_8822C 8
+#define BIT_MASK_RXDMA_ERR_CNT_8822C 0xff
+#define BIT_RXDMA_ERR_CNT_8822C(x) \
+ (((x) & BIT_MASK_RXDMA_ERR_CNT_8822C) << BIT_SHIFT_RXDMA_ERR_CNT_8822C)
+#define BITS_RXDMA_ERR_CNT_8822C \
+ (BIT_MASK_RXDMA_ERR_CNT_8822C << BIT_SHIFT_RXDMA_ERR_CNT_8822C)
+#define BIT_CLEAR_RXDMA_ERR_CNT_8822C(x) ((x) & (~BITS_RXDMA_ERR_CNT_8822C))
+#define BIT_GET_RXDMA_ERR_CNT_8822C(x) \
+ (((x) >> BIT_SHIFT_RXDMA_ERR_CNT_8822C) & BIT_MASK_RXDMA_ERR_CNT_8822C)
+#define BIT_SET_RXDMA_ERR_CNT_8822C(x, v) \
+ (BIT_CLEAR_RXDMA_ERR_CNT_8822C(x) | BIT_RXDMA_ERR_CNT_8822C(v))
+
+#define BIT_TXDMA_ERR_HANDLE_REQ_8822C BIT(7)
+#define BIT_TXDMA_ERROR_PS_8822C BIT(6)
+#define BIT_EN_TXDMA_STUCK_ERR_HANDLE_8822C BIT(5)
+#define BIT_EN_TXDMA_RTN_ERR_HANDLE_8822C BIT(4)
+#define BIT_RXDMA_ERR_HANDLE_REQ_8822C BIT(3)
+#define BIT_RXDMA_ERROR_PS_8822C BIT(2)
+#define BIT_EN_RXDMA_STUCK_ERR_HANDLE_8822C BIT(1)
+#define BIT_EN_RXDMA_RTN_ERR_HANDLE_8822C BIT(0)
+
+/* 2 REG_DEBUG_STATE1_8822C */
+
+#define BIT_SHIFT_DEBUG_STATE1_8822C 0
+#define BIT_MASK_DEBUG_STATE1_8822C 0xffffffffL
+#define BIT_DEBUG_STATE1_8822C(x) \
+ (((x) & BIT_MASK_DEBUG_STATE1_8822C) << BIT_SHIFT_DEBUG_STATE1_8822C)
+#define BITS_DEBUG_STATE1_8822C \
+ (BIT_MASK_DEBUG_STATE1_8822C << BIT_SHIFT_DEBUG_STATE1_8822C)
+#define BIT_CLEAR_DEBUG_STATE1_8822C(x) ((x) & (~BITS_DEBUG_STATE1_8822C))
+#define BIT_GET_DEBUG_STATE1_8822C(x) \
+ (((x) >> BIT_SHIFT_DEBUG_STATE1_8822C) & BIT_MASK_DEBUG_STATE1_8822C)
+#define BIT_SET_DEBUG_STATE1_8822C(x, v) \
+ (BIT_CLEAR_DEBUG_STATE1_8822C(x) | BIT_DEBUG_STATE1_8822C(v))
+
+/* 2 REG_DEBUG_STATE2_8822C */
+
+#define BIT_SHIFT_DEBUG_STATE2_8822C 0
+#define BIT_MASK_DEBUG_STATE2_8822C 0xffffffffL
+#define BIT_DEBUG_STATE2_8822C(x) \
+ (((x) & BIT_MASK_DEBUG_STATE2_8822C) << BIT_SHIFT_DEBUG_STATE2_8822C)
+#define BITS_DEBUG_STATE2_8822C \
+ (BIT_MASK_DEBUG_STATE2_8822C << BIT_SHIFT_DEBUG_STATE2_8822C)
+#define BIT_CLEAR_DEBUG_STATE2_8822C(x) ((x) & (~BITS_DEBUG_STATE2_8822C))
+#define BIT_GET_DEBUG_STATE2_8822C(x) \
+ (((x) >> BIT_SHIFT_DEBUG_STATE2_8822C) & BIT_MASK_DEBUG_STATE2_8822C)
+#define BIT_SET_DEBUG_STATE2_8822C(x, v) \
+ (BIT_CLEAR_DEBUG_STATE2_8822C(x) | BIT_DEBUG_STATE2_8822C(v))
+
+/* 2 REG_DEBUG_STATE3_8822C */
+
+#define BIT_SHIFT_DEBUG_STATE3_8822C 0
+#define BIT_MASK_DEBUG_STATE3_8822C 0xffffffffL
+#define BIT_DEBUG_STATE3_8822C(x) \
+ (((x) & BIT_MASK_DEBUG_STATE3_8822C) << BIT_SHIFT_DEBUG_STATE3_8822C)
+#define BITS_DEBUG_STATE3_8822C \
+ (BIT_MASK_DEBUG_STATE3_8822C << BIT_SHIFT_DEBUG_STATE3_8822C)
+#define BIT_CLEAR_DEBUG_STATE3_8822C(x) ((x) & (~BITS_DEBUG_STATE3_8822C))
+#define BIT_GET_DEBUG_STATE3_8822C(x) \
+ (((x) >> BIT_SHIFT_DEBUG_STATE3_8822C) & BIT_MASK_DEBUG_STATE3_8822C)
+#define BIT_SET_DEBUG_STATE3_8822C(x, v) \
+ (BIT_CLEAR_DEBUG_STATE3_8822C(x) | BIT_DEBUG_STATE3_8822C(v))
+
+/* 2 REG_CHNL_DMA_CFG_V1_8822C */
+#define BIT_TXHCI_EN_V1_8822C BIT(26)
+#define BIT_TXHCI_IDLE_V1_8822C BIT(25)
+#define BIT_DMA_PRI_EN_V1_8822C BIT(24)
+
+/* 2 REG_PCIE_HISR0_V1_8822C */
+#define BIT_PSTIMER_2_8822C BIT(31)
+#define BIT_PSTIMER_1_8822C BIT(30)
+#define BIT_PSTIMER_0_8822C BIT(29)
+#define BIT_GTINT4_8822C BIT(28)
+#define BIT_GTINT3_8822C BIT(27)
+#define BIT_TXBCN0ERR_8822C BIT(26)
+#define BIT_TXBCN0OK_8822C BIT(25)
+#define BIT_TSF_BIT32_TOGGLE_8822C BIT(24)
+#define BIT_TXDMA_START_INT_8822C BIT(23)
+#define BIT_TXDMA_STOP_INT_8822C BIT(22)
+#define BIT_HISR7_IND_8822C BIT(21)
+#define BIT_BCNDMAINT0_8822C BIT(20)
+#define BIT_HISR6_IND_8822C BIT(19)
+#define BIT_HISR5_IND_8822C BIT(18)
+#define BIT_HISR4_IND_8822C BIT(17)
+#define BIT_BCNDERR0_8822C BIT(16)
+#define BIT_HSISR_IND_ON_INT_8822C BIT(15)
+#define BIT_HISR3_IND_8822C BIT(14)
+#define BIT_HISR2_IND_8822C BIT(13)
+#define BIT_HISR1_IND_8822C BIT(11)
+#define BIT_C2HCMD_8822C BIT(10)
+#define BIT_CPWM2_8822C BIT(9)
+#define BIT_CPWM_8822C BIT(8)
+#define BIT_TXDMAOK_CHANNEL15_8822C BIT(7)
+#define BIT_TXDMAOK_CHANNEL14_8822C BIT(6)
+#define BIT_TXDMAOK_CHANNEL3_8822C BIT(5)
+#define BIT_TXDMAOK_CHANNEL2_8822C BIT(4)
+#define BIT_TXDMAOK_CHANNEL1_8822C BIT(3)
+#define BIT_TXDMAOK_CHANNEL0_8822C BIT(2)
+#define BIT_RDU_8822C BIT(1)
+#define BIT_RXOK_8822C BIT(0)
+
+/* 2 REG_PCIE_HISR1_V1_8822C */
+#define BIT_PRE_TX_ERR_INT_8822C BIT(31)
+#define BIT_TXFIFO_TH_INT_8822C BIT(30)
+#define BIT_BTON_STS_UPDATE_INT_8822C BIT(29)
+#define BIT_BCNDMAINT7_8822C BIT(27)
+#define BIT_BCNDMAINT6_8822C BIT(26)
+#define BIT_BCNDMAINT5_8822C BIT(25)
+#define BIT_BCNDMAINT4_8822C BIT(24)
+#define BIT_BCNDMAINT3_8822C BIT(23)
+#define BIT_BCNDMAINT2_8822C BIT(22)
+#define BIT_BCNDMAINT1_8822C BIT(21)
+#define BIT_BCNDERR7_8822C BIT(20)
+#define BIT_BCNDERR6_8822C BIT(19)
+#define BIT_BCNDERR5_8822C BIT(18)
+#define BIT_BCNDERR4_8822C BIT(17)
+#define BIT_BCNDERR3_8822C BIT(16)
+#define BIT_BCNDERR2_8822C BIT(15)
+#define BIT_BCNDERR1_8822C BIT(14)
+#define BIT_ATIMEND_8822C BIT(12)
+#define BIT_TXERR_INT_8822C BIT(11)
+#define BIT_RXERR_INT_8822C BIT(10)
+#define BIT_TXFOVW_8822C BIT(9)
+#define BIT_FOVW_8822C BIT(8)
+#define BIT_CPU_MGQ_EARLY_INT_8822C BIT(6)
+#define BIT_CPU_MGQ_TXDONE_8822C BIT(5)
+#define BIT_PSTIMER_5_8822C BIT(4)
+#define BIT_PSTIMER_4_8822C BIT(3)
+#define BIT_PSTIMER_3_8822C BIT(2)
+#define BIT_CPUMGQ_TX_TIMER_8822C BIT(1)
+#define BIT_BB_STOPRX_INT_8822C BIT(0)
+
+/* 2 REG_PCIE_HISR2_V1_8822C */
+#define BIT_BCNDMAINT_P4_8822C BIT(31)
+#define BIT_BCNDMAINT_P3_8822C BIT(30)
+#define BIT_BCNDMAINT_P2_8822C BIT(29)
+#define BIT_BCNDMAINT_P1_8822C BIT(28)
+#define BIT_SCH_PHY_TXOP_SIFS_INT_8822C BIT(23)
+#define BIT_ATIMEND7_8822C BIT(22)
+#define BIT_ATIMEND6_8822C BIT(21)
+#define BIT_ATIMEND5_8822C BIT(20)
+#define BIT_ATIMEND4_8822C BIT(19)
+#define BIT_ATIMEND3_8822C BIT(18)
+#define BIT_ATIMEND2_8822C BIT(17)
+#define BIT_ATIMEND1_8822C BIT(16)
+#define BIT_TXBCN7OK_8822C BIT(14)
+#define BIT_TXBCN6OK_8822C BIT(13)
+#define BIT_TXBCN5OK_8822C BIT(12)
+#define BIT_TXBCN4OK_8822C BIT(11)
+#define BIT_TXBCN3OK_8822C BIT(10)
+#define BIT_TXBCN2OK_8822C BIT(9)
+#define BIT_TXBCN1OK_8822C BIT(8)
+#define BIT_TXBCN7ERR_8822C BIT(6)
+#define BIT_TXBCN6ERR_8822C BIT(5)
+#define BIT_TXBCN5ERR_8822C BIT(4)
+#define BIT_TXBCN4ERR_8822C BIT(3)
+#define BIT_TXBCN3ERR_8822C BIT(2)
+#define BIT_TXBCN2ERR_8822C BIT(1)
+#define BIT_TXBCN1ERR_8822C BIT(0)
+
+/* 2 REG_PCIE_HISR3_V1_8822C */
+#define BIT_GTINT12_8822C BIT(24)
+#define BIT_GTINT11_8822C BIT(23)
+#define BIT_GTINT10_8822C BIT(22)
+#define BIT_GTINT9_8822C BIT(21)
+#define BIT_RX_DESC_BUF_FULL_8822C BIT(20)
+#define BIT_CPHY_LDO_OCP_DET_INT_8822C BIT(19)
+#define BIT_WDT_PLATFORM_INT_8822C BIT(18)
+#define BIT_WDT_CPU_INT_8822C BIT(17)
+#define BIT_SETH2CDOK_8822C BIT(16)
+#define BIT_H2C_CMD_FULL_8822C BIT(15)
+#define BIT_PKT_TRANS_ERR_8822C BIT(14)
+#define BIT_TXSHORTCUT_TXDESUPDATEOK_8822C BIT(13)
+#define BIT_TXSHORTCUT_BKUPDATEOK_8822C BIT(12)
+#define BIT_TXSHORTCUT_BEUPDATEOK_8822C BIT(11)
+#define BIT_TXSHORTCUT_VIUPDATEOK_8822C BIT(10)
+#define BIT_TXSHORTCUT_VOUPDATEOK_8822C BIT(9)
+#define BIT_SEARCH_FAIL_8822C BIT(8)
+#define BIT_PWR_INT_127TO96_8822C BIT(7)
+#define BIT_PWR_INT_95TO64_8822C BIT(6)
+#define BIT_PWR_INT_63TO32_8822C BIT(5)
+#define BIT_PWR_INT_31TO0_8822C BIT(4)
+#define BIT_RX_DMA_STUCK_8822C BIT(3)
+#define BIT_TX_DMA_STUCK_8822C BIT(2)
+#define BIT_DDMA0_LP_INT_8822C BIT(1)
+#define BIT_DDMA0_HP_INT_8822C BIT(0)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_Q0_INFO_8822C */
+
+#define BIT_SHIFT_QUEUEMACID_Q0_V1_8822C 25
+#define BIT_MASK_QUEUEMACID_Q0_V1_8822C 0x7f
+#define BIT_QUEUEMACID_Q0_V1_8822C(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q0_V1_8822C) \
+ << BIT_SHIFT_QUEUEMACID_Q0_V1_8822C)
+#define BITS_QUEUEMACID_Q0_V1_8822C \
+ (BIT_MASK_QUEUEMACID_Q0_V1_8822C << BIT_SHIFT_QUEUEMACID_Q0_V1_8822C)
+#define BIT_CLEAR_QUEUEMACID_Q0_V1_8822C(x) \
+ ((x) & (~BITS_QUEUEMACID_Q0_V1_8822C))
+#define BIT_GET_QUEUEMACID_Q0_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1_8822C) & \
+ BIT_MASK_QUEUEMACID_Q0_V1_8822C)
+#define BIT_SET_QUEUEMACID_Q0_V1_8822C(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q0_V1_8822C(x) | BIT_QUEUEMACID_Q0_V1_8822C(v))
+
+#define BIT_SHIFT_QUEUEAC_Q0_V1_8822C 23
+#define BIT_MASK_QUEUEAC_Q0_V1_8822C 0x3
+#define BIT_QUEUEAC_Q0_V1_8822C(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q0_V1_8822C) << BIT_SHIFT_QUEUEAC_Q0_V1_8822C)
+#define BITS_QUEUEAC_Q0_V1_8822C \
+ (BIT_MASK_QUEUEAC_Q0_V1_8822C << BIT_SHIFT_QUEUEAC_Q0_V1_8822C)
+#define BIT_CLEAR_QUEUEAC_Q0_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q0_V1_8822C))
+#define BIT_GET_QUEUEAC_Q0_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q0_V1_8822C) & BIT_MASK_QUEUEAC_Q0_V1_8822C)
+#define BIT_SET_QUEUEAC_Q0_V1_8822C(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q0_V1_8822C(x) | BIT_QUEUEAC_Q0_V1_8822C(v))
+
+#define BIT_TIDEMPTY_Q0_V1_8822C BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q0_V2_8822C 11
+#define BIT_MASK_TAIL_PKT_Q0_V2_8822C 0x7ff
+#define BIT_TAIL_PKT_Q0_V2_8822C(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q0_V2_8822C) \
+ << BIT_SHIFT_TAIL_PKT_Q0_V2_8822C)
+#define BITS_TAIL_PKT_Q0_V2_8822C \
+ (BIT_MASK_TAIL_PKT_Q0_V2_8822C << BIT_SHIFT_TAIL_PKT_Q0_V2_8822C)
+#define BIT_CLEAR_TAIL_PKT_Q0_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q0_V2_8822C))
+#define BIT_GET_TAIL_PKT_Q0_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2_8822C) & \
+ BIT_MASK_TAIL_PKT_Q0_V2_8822C)
+#define BIT_SET_TAIL_PKT_Q0_V2_8822C(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q0_V2_8822C(x) | BIT_TAIL_PKT_Q0_V2_8822C(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q0_V1_8822C 0
+#define BIT_MASK_HEAD_PKT_Q0_V1_8822C 0x7ff
+#define BIT_HEAD_PKT_Q0_V1_8822C(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q0_V1_8822C) \
+ << BIT_SHIFT_HEAD_PKT_Q0_V1_8822C)
+#define BITS_HEAD_PKT_Q0_V1_8822C \
+ (BIT_MASK_HEAD_PKT_Q0_V1_8822C << BIT_SHIFT_HEAD_PKT_Q0_V1_8822C)
+#define BIT_CLEAR_HEAD_PKT_Q0_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q0_V1_8822C))
+#define BIT_GET_HEAD_PKT_Q0_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1_8822C) & \
+ BIT_MASK_HEAD_PKT_Q0_V1_8822C)
+#define BIT_SET_HEAD_PKT_Q0_V1_8822C(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q0_V1_8822C(x) | BIT_HEAD_PKT_Q0_V1_8822C(v))
+
+/* 2 REG_Q1_INFO_8822C */
+
+#define BIT_SHIFT_QUEUEMACID_Q1_V1_8822C 25
+#define BIT_MASK_QUEUEMACID_Q1_V1_8822C 0x7f
+#define BIT_QUEUEMACID_Q1_V1_8822C(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q1_V1_8822C) \
+ << BIT_SHIFT_QUEUEMACID_Q1_V1_8822C)
+#define BITS_QUEUEMACID_Q1_V1_8822C \
+ (BIT_MASK_QUEUEMACID_Q1_V1_8822C << BIT_SHIFT_QUEUEMACID_Q1_V1_8822C)
+#define BIT_CLEAR_QUEUEMACID_Q1_V1_8822C(x) \
+ ((x) & (~BITS_QUEUEMACID_Q1_V1_8822C))
+#define BIT_GET_QUEUEMACID_Q1_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1_8822C) & \
+ BIT_MASK_QUEUEMACID_Q1_V1_8822C)
+#define BIT_SET_QUEUEMACID_Q1_V1_8822C(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q1_V1_8822C(x) | BIT_QUEUEMACID_Q1_V1_8822C(v))
+
+#define BIT_SHIFT_QUEUEAC_Q1_V1_8822C 23
+#define BIT_MASK_QUEUEAC_Q1_V1_8822C 0x3
+#define BIT_QUEUEAC_Q1_V1_8822C(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q1_V1_8822C) << BIT_SHIFT_QUEUEAC_Q1_V1_8822C)
+#define BITS_QUEUEAC_Q1_V1_8822C \
+ (BIT_MASK_QUEUEAC_Q1_V1_8822C << BIT_SHIFT_QUEUEAC_Q1_V1_8822C)
+#define BIT_CLEAR_QUEUEAC_Q1_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q1_V1_8822C))
+#define BIT_GET_QUEUEAC_Q1_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q1_V1_8822C) & BIT_MASK_QUEUEAC_Q1_V1_8822C)
+#define BIT_SET_QUEUEAC_Q1_V1_8822C(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q1_V1_8822C(x) | BIT_QUEUEAC_Q1_V1_8822C(v))
+
+#define BIT_TIDEMPTY_Q1_V1_8822C BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q1_V2_8822C 11
+#define BIT_MASK_TAIL_PKT_Q1_V2_8822C 0x7ff
+#define BIT_TAIL_PKT_Q1_V2_8822C(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q1_V2_8822C) \
+ << BIT_SHIFT_TAIL_PKT_Q1_V2_8822C)
+#define BITS_TAIL_PKT_Q1_V2_8822C \
+ (BIT_MASK_TAIL_PKT_Q1_V2_8822C << BIT_SHIFT_TAIL_PKT_Q1_V2_8822C)
+#define BIT_CLEAR_TAIL_PKT_Q1_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q1_V2_8822C))
+#define BIT_GET_TAIL_PKT_Q1_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2_8822C) & \
+ BIT_MASK_TAIL_PKT_Q1_V2_8822C)
+#define BIT_SET_TAIL_PKT_Q1_V2_8822C(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q1_V2_8822C(x) | BIT_TAIL_PKT_Q1_V2_8822C(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q1_V1_8822C 0
+#define BIT_MASK_HEAD_PKT_Q1_V1_8822C 0x7ff
+#define BIT_HEAD_PKT_Q1_V1_8822C(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q1_V1_8822C) \
+ << BIT_SHIFT_HEAD_PKT_Q1_V1_8822C)
+#define BITS_HEAD_PKT_Q1_V1_8822C \
+ (BIT_MASK_HEAD_PKT_Q1_V1_8822C << BIT_SHIFT_HEAD_PKT_Q1_V1_8822C)
+#define BIT_CLEAR_HEAD_PKT_Q1_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q1_V1_8822C))
+#define BIT_GET_HEAD_PKT_Q1_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1_8822C) & \
+ BIT_MASK_HEAD_PKT_Q1_V1_8822C)
+#define BIT_SET_HEAD_PKT_Q1_V1_8822C(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q1_V1_8822C(x) | BIT_HEAD_PKT_Q1_V1_8822C(v))
+
+/* 2 REG_Q2_INFO_8822C */
+
+#define BIT_SHIFT_QUEUEMACID_Q2_V1_8822C 25
+#define BIT_MASK_QUEUEMACID_Q2_V1_8822C 0x7f
+#define BIT_QUEUEMACID_Q2_V1_8822C(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q2_V1_8822C) \
+ << BIT_SHIFT_QUEUEMACID_Q2_V1_8822C)
+#define BITS_QUEUEMACID_Q2_V1_8822C \
+ (BIT_MASK_QUEUEMACID_Q2_V1_8822C << BIT_SHIFT_QUEUEMACID_Q2_V1_8822C)
+#define BIT_CLEAR_QUEUEMACID_Q2_V1_8822C(x) \
+ ((x) & (~BITS_QUEUEMACID_Q2_V1_8822C))
+#define BIT_GET_QUEUEMACID_Q2_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1_8822C) & \
+ BIT_MASK_QUEUEMACID_Q2_V1_8822C)
+#define BIT_SET_QUEUEMACID_Q2_V1_8822C(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q2_V1_8822C(x) | BIT_QUEUEMACID_Q2_V1_8822C(v))
+
+#define BIT_SHIFT_QUEUEAC_Q2_V1_8822C 23
+#define BIT_MASK_QUEUEAC_Q2_V1_8822C 0x3
+#define BIT_QUEUEAC_Q2_V1_8822C(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q2_V1_8822C) << BIT_SHIFT_QUEUEAC_Q2_V1_8822C)
+#define BITS_QUEUEAC_Q2_V1_8822C \
+ (BIT_MASK_QUEUEAC_Q2_V1_8822C << BIT_SHIFT_QUEUEAC_Q2_V1_8822C)
+#define BIT_CLEAR_QUEUEAC_Q2_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q2_V1_8822C))
+#define BIT_GET_QUEUEAC_Q2_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q2_V1_8822C) & BIT_MASK_QUEUEAC_Q2_V1_8822C)
+#define BIT_SET_QUEUEAC_Q2_V1_8822C(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q2_V1_8822C(x) | BIT_QUEUEAC_Q2_V1_8822C(v))
+
+#define BIT_TIDEMPTY_Q2_V1_8822C BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q2_V2_8822C 11
+#define BIT_MASK_TAIL_PKT_Q2_V2_8822C 0x7ff
+#define BIT_TAIL_PKT_Q2_V2_8822C(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q2_V2_8822C) \
+ << BIT_SHIFT_TAIL_PKT_Q2_V2_8822C)
+#define BITS_TAIL_PKT_Q2_V2_8822C \
+ (BIT_MASK_TAIL_PKT_Q2_V2_8822C << BIT_SHIFT_TAIL_PKT_Q2_V2_8822C)
+#define BIT_CLEAR_TAIL_PKT_Q2_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q2_V2_8822C))
+#define BIT_GET_TAIL_PKT_Q2_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2_8822C) & \
+ BIT_MASK_TAIL_PKT_Q2_V2_8822C)
+#define BIT_SET_TAIL_PKT_Q2_V2_8822C(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q2_V2_8822C(x) | BIT_TAIL_PKT_Q2_V2_8822C(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q2_V1_8822C 0
+#define BIT_MASK_HEAD_PKT_Q2_V1_8822C 0x7ff
+#define BIT_HEAD_PKT_Q2_V1_8822C(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q2_V1_8822C) \
+ << BIT_SHIFT_HEAD_PKT_Q2_V1_8822C)
+#define BITS_HEAD_PKT_Q2_V1_8822C \
+ (BIT_MASK_HEAD_PKT_Q2_V1_8822C << BIT_SHIFT_HEAD_PKT_Q2_V1_8822C)
+#define BIT_CLEAR_HEAD_PKT_Q2_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q2_V1_8822C))
+#define BIT_GET_HEAD_PKT_Q2_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1_8822C) & \
+ BIT_MASK_HEAD_PKT_Q2_V1_8822C)
+#define BIT_SET_HEAD_PKT_Q2_V1_8822C(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q2_V1_8822C(x) | BIT_HEAD_PKT_Q2_V1_8822C(v))
+
+/* 2 REG_Q3_INFO_8822C */
+
+#define BIT_SHIFT_QUEUEMACID_Q3_V1_8822C 25
+#define BIT_MASK_QUEUEMACID_Q3_V1_8822C 0x7f
+#define BIT_QUEUEMACID_Q3_V1_8822C(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q3_V1_8822C) \
+ << BIT_SHIFT_QUEUEMACID_Q3_V1_8822C)
+#define BITS_QUEUEMACID_Q3_V1_8822C \
+ (BIT_MASK_QUEUEMACID_Q3_V1_8822C << BIT_SHIFT_QUEUEMACID_Q3_V1_8822C)
+#define BIT_CLEAR_QUEUEMACID_Q3_V1_8822C(x) \
+ ((x) & (~BITS_QUEUEMACID_Q3_V1_8822C))
+#define BIT_GET_QUEUEMACID_Q3_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1_8822C) & \
+ BIT_MASK_QUEUEMACID_Q3_V1_8822C)
+#define BIT_SET_QUEUEMACID_Q3_V1_8822C(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q3_V1_8822C(x) | BIT_QUEUEMACID_Q3_V1_8822C(v))
+
+#define BIT_SHIFT_QUEUEAC_Q3_V1_8822C 23
+#define BIT_MASK_QUEUEAC_Q3_V1_8822C 0x3
+#define BIT_QUEUEAC_Q3_V1_8822C(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q3_V1_8822C) << BIT_SHIFT_QUEUEAC_Q3_V1_8822C)
+#define BITS_QUEUEAC_Q3_V1_8822C \
+ (BIT_MASK_QUEUEAC_Q3_V1_8822C << BIT_SHIFT_QUEUEAC_Q3_V1_8822C)
+#define BIT_CLEAR_QUEUEAC_Q3_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q3_V1_8822C))
+#define BIT_GET_QUEUEAC_Q3_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q3_V1_8822C) & BIT_MASK_QUEUEAC_Q3_V1_8822C)
+#define BIT_SET_QUEUEAC_Q3_V1_8822C(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q3_V1_8822C(x) | BIT_QUEUEAC_Q3_V1_8822C(v))
+
+#define BIT_TIDEMPTY_Q3_V1_8822C BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q3_V2_8822C 11
+#define BIT_MASK_TAIL_PKT_Q3_V2_8822C 0x7ff
+#define BIT_TAIL_PKT_Q3_V2_8822C(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q3_V2_8822C) \
+ << BIT_SHIFT_TAIL_PKT_Q3_V2_8822C)
+#define BITS_TAIL_PKT_Q3_V2_8822C \
+ (BIT_MASK_TAIL_PKT_Q3_V2_8822C << BIT_SHIFT_TAIL_PKT_Q3_V2_8822C)
+#define BIT_CLEAR_TAIL_PKT_Q3_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q3_V2_8822C))
+#define BIT_GET_TAIL_PKT_Q3_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2_8822C) & \
+ BIT_MASK_TAIL_PKT_Q3_V2_8822C)
+#define BIT_SET_TAIL_PKT_Q3_V2_8822C(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q3_V2_8822C(x) | BIT_TAIL_PKT_Q3_V2_8822C(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q3_V1_8822C 0
+#define BIT_MASK_HEAD_PKT_Q3_V1_8822C 0x7ff
+#define BIT_HEAD_PKT_Q3_V1_8822C(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q3_V1_8822C) \
+ << BIT_SHIFT_HEAD_PKT_Q3_V1_8822C)
+#define BITS_HEAD_PKT_Q3_V1_8822C \
+ (BIT_MASK_HEAD_PKT_Q3_V1_8822C << BIT_SHIFT_HEAD_PKT_Q3_V1_8822C)
+#define BIT_CLEAR_HEAD_PKT_Q3_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q3_V1_8822C))
+#define BIT_GET_HEAD_PKT_Q3_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1_8822C) & \
+ BIT_MASK_HEAD_PKT_Q3_V1_8822C)
+#define BIT_SET_HEAD_PKT_Q3_V1_8822C(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q3_V1_8822C(x) | BIT_HEAD_PKT_Q3_V1_8822C(v))
+
+/* 2 REG_MGQ_INFO_8822C */
+
+#define BIT_SHIFT_QUEUEMACID_MGQ_V1_8822C 25
+#define BIT_MASK_QUEUEMACID_MGQ_V1_8822C 0x7f
+#define BIT_QUEUEMACID_MGQ_V1_8822C(x) \
+ (((x) & BIT_MASK_QUEUEMACID_MGQ_V1_8822C) \
+ << BIT_SHIFT_QUEUEMACID_MGQ_V1_8822C)
+#define BITS_QUEUEMACID_MGQ_V1_8822C \
+ (BIT_MASK_QUEUEMACID_MGQ_V1_8822C << BIT_SHIFT_QUEUEMACID_MGQ_V1_8822C)
+#define BIT_CLEAR_QUEUEMACID_MGQ_V1_8822C(x) \
+ ((x) & (~BITS_QUEUEMACID_MGQ_V1_8822C))
+#define BIT_GET_QUEUEMACID_MGQ_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1_8822C) & \
+ BIT_MASK_QUEUEMACID_MGQ_V1_8822C)
+#define BIT_SET_QUEUEMACID_MGQ_V1_8822C(x, v) \
+ (BIT_CLEAR_QUEUEMACID_MGQ_V1_8822C(x) | BIT_QUEUEMACID_MGQ_V1_8822C(v))
+
+#define BIT_SHIFT_QUEUEAC_MGQ_V1_8822C 23
+#define BIT_MASK_QUEUEAC_MGQ_V1_8822C 0x3
+#define BIT_QUEUEAC_MGQ_V1_8822C(x) \
+ (((x) & BIT_MASK_QUEUEAC_MGQ_V1_8822C) \
+ << BIT_SHIFT_QUEUEAC_MGQ_V1_8822C)
+#define BITS_QUEUEAC_MGQ_V1_8822C \
+ (BIT_MASK_QUEUEAC_MGQ_V1_8822C << BIT_SHIFT_QUEUEAC_MGQ_V1_8822C)
+#define BIT_CLEAR_QUEUEAC_MGQ_V1_8822C(x) ((x) & (~BITS_QUEUEAC_MGQ_V1_8822C))
+#define BIT_GET_QUEUEAC_MGQ_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1_8822C) & \
+ BIT_MASK_QUEUEAC_MGQ_V1_8822C)
+#define BIT_SET_QUEUEAC_MGQ_V1_8822C(x, v) \
+ (BIT_CLEAR_QUEUEAC_MGQ_V1_8822C(x) | BIT_QUEUEAC_MGQ_V1_8822C(v))
+
+#define BIT_TIDEMPTY_MGQ_V1_8822C BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_MGQ_V2_8822C 11
+#define BIT_MASK_TAIL_PKT_MGQ_V2_8822C 0x7ff
+#define BIT_TAIL_PKT_MGQ_V2_8822C(x) \
+ (((x) & BIT_MASK_TAIL_PKT_MGQ_V2_8822C) \
+ << BIT_SHIFT_TAIL_PKT_MGQ_V2_8822C)
+#define BITS_TAIL_PKT_MGQ_V2_8822C \
+ (BIT_MASK_TAIL_PKT_MGQ_V2_8822C << BIT_SHIFT_TAIL_PKT_MGQ_V2_8822C)
+#define BIT_CLEAR_TAIL_PKT_MGQ_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_MGQ_V2_8822C))
+#define BIT_GET_TAIL_PKT_MGQ_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2_8822C) & \
+ BIT_MASK_TAIL_PKT_MGQ_V2_8822C)
+#define BIT_SET_TAIL_PKT_MGQ_V2_8822C(x, v) \
+ (BIT_CLEAR_TAIL_PKT_MGQ_V2_8822C(x) | BIT_TAIL_PKT_MGQ_V2_8822C(v))
+
+#define BIT_SHIFT_HEAD_PKT_MGQ_V1_8822C 0
+#define BIT_MASK_HEAD_PKT_MGQ_V1_8822C 0x7ff
+#define BIT_HEAD_PKT_MGQ_V1_8822C(x) \
+ (((x) & BIT_MASK_HEAD_PKT_MGQ_V1_8822C) \
+ << BIT_SHIFT_HEAD_PKT_MGQ_V1_8822C)
+#define BITS_HEAD_PKT_MGQ_V1_8822C \
+ (BIT_MASK_HEAD_PKT_MGQ_V1_8822C << BIT_SHIFT_HEAD_PKT_MGQ_V1_8822C)
+#define BIT_CLEAR_HEAD_PKT_MGQ_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_MGQ_V1_8822C))
+#define BIT_GET_HEAD_PKT_MGQ_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1_8822C) & \
+ BIT_MASK_HEAD_PKT_MGQ_V1_8822C)
+#define BIT_SET_HEAD_PKT_MGQ_V1_8822C(x, v) \
+ (BIT_CLEAR_HEAD_PKT_MGQ_V1_8822C(x) | BIT_HEAD_PKT_MGQ_V1_8822C(v))
+
+/* 2 REG_HIQ_INFO_8822C */
+
+#define BIT_SHIFT_QUEUEMACID_HIQ_V1_8822C 25
+#define BIT_MASK_QUEUEMACID_HIQ_V1_8822C 0x7f
+#define BIT_QUEUEMACID_HIQ_V1_8822C(x) \
+ (((x) & BIT_MASK_QUEUEMACID_HIQ_V1_8822C) \
+ << BIT_SHIFT_QUEUEMACID_HIQ_V1_8822C)
+#define BITS_QUEUEMACID_HIQ_V1_8822C \
+ (BIT_MASK_QUEUEMACID_HIQ_V1_8822C << BIT_SHIFT_QUEUEMACID_HIQ_V1_8822C)
+#define BIT_CLEAR_QUEUEMACID_HIQ_V1_8822C(x) \
+ ((x) & (~BITS_QUEUEMACID_HIQ_V1_8822C))
+#define BIT_GET_QUEUEMACID_HIQ_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1_8822C) & \
+ BIT_MASK_QUEUEMACID_HIQ_V1_8822C)
+#define BIT_SET_QUEUEMACID_HIQ_V1_8822C(x, v) \
+ (BIT_CLEAR_QUEUEMACID_HIQ_V1_8822C(x) | BIT_QUEUEMACID_HIQ_V1_8822C(v))
+
+#define BIT_SHIFT_QUEUEAC_HIQ_V1_8822C 23
+#define BIT_MASK_QUEUEAC_HIQ_V1_8822C 0x3
+#define BIT_QUEUEAC_HIQ_V1_8822C(x) \
+ (((x) & BIT_MASK_QUEUEAC_HIQ_V1_8822C) \
+ << BIT_SHIFT_QUEUEAC_HIQ_V1_8822C)
+#define BITS_QUEUEAC_HIQ_V1_8822C \
+ (BIT_MASK_QUEUEAC_HIQ_V1_8822C << BIT_SHIFT_QUEUEAC_HIQ_V1_8822C)
+#define BIT_CLEAR_QUEUEAC_HIQ_V1_8822C(x) ((x) & (~BITS_QUEUEAC_HIQ_V1_8822C))
+#define BIT_GET_QUEUEAC_HIQ_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1_8822C) & \
+ BIT_MASK_QUEUEAC_HIQ_V1_8822C)
+#define BIT_SET_QUEUEAC_HIQ_V1_8822C(x, v) \
+ (BIT_CLEAR_QUEUEAC_HIQ_V1_8822C(x) | BIT_QUEUEAC_HIQ_V1_8822C(v))
+
+#define BIT_TIDEMPTY_HIQ_V1_8822C BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_HIQ_V2_8822C 11
+#define BIT_MASK_TAIL_PKT_HIQ_V2_8822C 0x7ff
+#define BIT_TAIL_PKT_HIQ_V2_8822C(x) \
+ (((x) & BIT_MASK_TAIL_PKT_HIQ_V2_8822C) \
+ << BIT_SHIFT_TAIL_PKT_HIQ_V2_8822C)
+#define BITS_TAIL_PKT_HIQ_V2_8822C \
+ (BIT_MASK_TAIL_PKT_HIQ_V2_8822C << BIT_SHIFT_TAIL_PKT_HIQ_V2_8822C)
+#define BIT_CLEAR_TAIL_PKT_HIQ_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_HIQ_V2_8822C))
+#define BIT_GET_TAIL_PKT_HIQ_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2_8822C) & \
+ BIT_MASK_TAIL_PKT_HIQ_V2_8822C)
+#define BIT_SET_TAIL_PKT_HIQ_V2_8822C(x, v) \
+ (BIT_CLEAR_TAIL_PKT_HIQ_V2_8822C(x) | BIT_TAIL_PKT_HIQ_V2_8822C(v))
+
+#define BIT_SHIFT_HEAD_PKT_HIQ_V1_8822C 0
+#define BIT_MASK_HEAD_PKT_HIQ_V1_8822C 0x7ff
+#define BIT_HEAD_PKT_HIQ_V1_8822C(x) \
+ (((x) & BIT_MASK_HEAD_PKT_HIQ_V1_8822C) \
+ << BIT_SHIFT_HEAD_PKT_HIQ_V1_8822C)
+#define BITS_HEAD_PKT_HIQ_V1_8822C \
+ (BIT_MASK_HEAD_PKT_HIQ_V1_8822C << BIT_SHIFT_HEAD_PKT_HIQ_V1_8822C)
+#define BIT_CLEAR_HEAD_PKT_HIQ_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_HIQ_V1_8822C))
+#define BIT_GET_HEAD_PKT_HIQ_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1_8822C) & \
+ BIT_MASK_HEAD_PKT_HIQ_V1_8822C)
+#define BIT_SET_HEAD_PKT_HIQ_V1_8822C(x, v) \
+ (BIT_CLEAR_HEAD_PKT_HIQ_V1_8822C(x) | BIT_HEAD_PKT_HIQ_V1_8822C(v))
+
+/* 2 REG_BCNQ_INFO_8822C */
+
+#define BIT_SHIFT_BCNQ_HEAD_PG_V1_8822C 0
+#define BIT_MASK_BCNQ_HEAD_PG_V1_8822C 0xfff
+#define BIT_BCNQ_HEAD_PG_V1_8822C(x) \
+ (((x) & BIT_MASK_BCNQ_HEAD_PG_V1_8822C) \
+ << BIT_SHIFT_BCNQ_HEAD_PG_V1_8822C)
+#define BITS_BCNQ_HEAD_PG_V1_8822C \
+ (BIT_MASK_BCNQ_HEAD_PG_V1_8822C << BIT_SHIFT_BCNQ_HEAD_PG_V1_8822C)
+#define BIT_CLEAR_BCNQ_HEAD_PG_V1_8822C(x) ((x) & (~BITS_BCNQ_HEAD_PG_V1_8822C))
+#define BIT_GET_BCNQ_HEAD_PG_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1_8822C) & \
+ BIT_MASK_BCNQ_HEAD_PG_V1_8822C)
+#define BIT_SET_BCNQ_HEAD_PG_V1_8822C(x, v) \
+ (BIT_CLEAR_BCNQ_HEAD_PG_V1_8822C(x) | BIT_BCNQ_HEAD_PG_V1_8822C(v))
+
+/* 2 REG_TXPKT_EMPTY_8822C */
+#define BIT_BCNQ_EMPTY_8822C BIT(11)
+#define BIT_HQQ_EMPTY_8822C BIT(10)
+#define BIT_MQQ_EMPTY_8822C BIT(9)
+#define BIT_MGQ_CPU_EMPTY_8822C BIT(8)
+#define BIT_AC7Q_EMPTY_8822C BIT(7)
+#define BIT_AC6Q_EMPTY_8822C BIT(6)
+#define BIT_AC5Q_EMPTY_8822C BIT(5)
+#define BIT_AC4Q_EMPTY_8822C BIT(4)
+#define BIT_AC3Q_EMPTY_8822C BIT(3)
+#define BIT_AC2Q_EMPTY_8822C BIT(2)
+#define BIT_AC1Q_EMPTY_8822C BIT(1)
+#define BIT_AC0Q_EMPTY_8822C BIT(0)
+
+/* 2 REG_CPU_MGQ_INFO_8822C */
+#define BIT_BCN1_POLL_8822C BIT(30)
+#define BIT_CPUMGT_POLL_8822C BIT(29)
+#define BIT_BCN_POLL_8822C BIT(28)
+#define BIT_CPUMGQ_FW_NUM_V1_8822C BIT(12)
+
+#define BIT_SHIFT_FW_FREE_TAIL_V1_8822C 0
+#define BIT_MASK_FW_FREE_TAIL_V1_8822C 0xfff
+#define BIT_FW_FREE_TAIL_V1_8822C(x) \
+ (((x) & BIT_MASK_FW_FREE_TAIL_V1_8822C) \
+ << BIT_SHIFT_FW_FREE_TAIL_V1_8822C)
+#define BITS_FW_FREE_TAIL_V1_8822C \
+ (BIT_MASK_FW_FREE_TAIL_V1_8822C << BIT_SHIFT_FW_FREE_TAIL_V1_8822C)
+#define BIT_CLEAR_FW_FREE_TAIL_V1_8822C(x) ((x) & (~BITS_FW_FREE_TAIL_V1_8822C))
+#define BIT_GET_FW_FREE_TAIL_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_FW_FREE_TAIL_V1_8822C) & \
+ BIT_MASK_FW_FREE_TAIL_V1_8822C)
+#define BIT_SET_FW_FREE_TAIL_V1_8822C(x, v) \
+ (BIT_CLEAR_FW_FREE_TAIL_V1_8822C(x) | BIT_FW_FREE_TAIL_V1_8822C(v))
+
+/* 2 REG_FWHW_TXQ_CTRL_8822C */
+#define BIT_RTS_LIMIT_IN_OFDM_8822C BIT(23)
+#define BIT_EN_BCNQ_DL_8822C BIT(22)
+#define BIT_EN_RD_RESP_NAV_BK_8822C BIT(21)
+#define BIT_EN_WR_FREE_TAIL_8822C BIT(20)
+#define BIT_NOTXRPT_USERATE_EN_8822C BIT(19)
+#define BIT_DIS_TXFAIL_RPT_8822C BIT(18)
+#define BIT_FTM_TIMEOUT_BYPASS_8822C BIT(16)
+
+#define BIT_SHIFT_EN_QUEUE_RPT_8822C 8
+#define BIT_MASK_EN_QUEUE_RPT_8822C 0xff
+#define BIT_EN_QUEUE_RPT_8822C(x) \
+ (((x) & BIT_MASK_EN_QUEUE_RPT_8822C) << BIT_SHIFT_EN_QUEUE_RPT_8822C)
+#define BITS_EN_QUEUE_RPT_8822C \
+ (BIT_MASK_EN_QUEUE_RPT_8822C << BIT_SHIFT_EN_QUEUE_RPT_8822C)
+#define BIT_CLEAR_EN_QUEUE_RPT_8822C(x) ((x) & (~BITS_EN_QUEUE_RPT_8822C))
+#define BIT_GET_EN_QUEUE_RPT_8822C(x) \
+ (((x) >> BIT_SHIFT_EN_QUEUE_RPT_8822C) & BIT_MASK_EN_QUEUE_RPT_8822C)
+#define BIT_SET_EN_QUEUE_RPT_8822C(x, v) \
+ (BIT_CLEAR_EN_QUEUE_RPT_8822C(x) | BIT_EN_QUEUE_RPT_8822C(v))
+
+#define BIT_EN_RTY_BK_8822C BIT(7)
+#define BIT_EN_USE_INI_RAT_8822C BIT(6)
+#define BIT_EN_RTS_NAV_BK_8822C BIT(5)
+#define BIT_DIS_SSN_CHECK_8822C BIT(4)
+#define BIT_MACID_MATCH_RTS_8822C BIT(3)
+#define BIT_EN_BCN_TRXRPT_V1_8822C BIT(2)
+#define BIT_R_EN_FTMRPT_V1_8822C BIT(1)
+#define BIT_R_BMC_NAV_PROTECT_8822C BIT(0)
+
+/* 2 REG_DATAFB_SEL_8822C */
+#define BIT_BROADCAST_RTY_EN_8822C BIT(3)
+#define BIT_EN_RTY_BK_COD_8822C BIT(2)
+
+#define BIT_SHIFT__R_DATA_FALLBACK_SEL_8822C 0
+#define BIT_MASK__R_DATA_FALLBACK_SEL_8822C 0x3
+#define BIT__R_DATA_FALLBACK_SEL_8822C(x) \
+ (((x) & BIT_MASK__R_DATA_FALLBACK_SEL_8822C) \
+ << BIT_SHIFT__R_DATA_FALLBACK_SEL_8822C)
+#define BITS__R_DATA_FALLBACK_SEL_8822C \
+ (BIT_MASK__R_DATA_FALLBACK_SEL_8822C \
+ << BIT_SHIFT__R_DATA_FALLBACK_SEL_8822C)
+#define BIT_CLEAR__R_DATA_FALLBACK_SEL_8822C(x) \
+ ((x) & (~BITS__R_DATA_FALLBACK_SEL_8822C))
+#define BIT_GET__R_DATA_FALLBACK_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL_8822C) & \
+ BIT_MASK__R_DATA_FALLBACK_SEL_8822C)
+#define BIT_SET__R_DATA_FALLBACK_SEL_8822C(x, v) \
+ (BIT_CLEAR__R_DATA_FALLBACK_SEL_8822C(x) | \
+ BIT__R_DATA_FALLBACK_SEL_8822C(v))
+
+/* 2 REG_BCNQ_BDNY_V1_8822C */
+
+#define BIT_SHIFT_BCNQ_PGBNDY_V1_8822C 0
+#define BIT_MASK_BCNQ_PGBNDY_V1_8822C 0xfff
+#define BIT_BCNQ_PGBNDY_V1_8822C(x) \
+ (((x) & BIT_MASK_BCNQ_PGBNDY_V1_8822C) \
+ << BIT_SHIFT_BCNQ_PGBNDY_V1_8822C)
+#define BITS_BCNQ_PGBNDY_V1_8822C \
+ (BIT_MASK_BCNQ_PGBNDY_V1_8822C << BIT_SHIFT_BCNQ_PGBNDY_V1_8822C)
+#define BIT_CLEAR_BCNQ_PGBNDY_V1_8822C(x) ((x) & (~BITS_BCNQ_PGBNDY_V1_8822C))
+#define BIT_GET_BCNQ_PGBNDY_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1_8822C) & \
+ BIT_MASK_BCNQ_PGBNDY_V1_8822C)
+#define BIT_SET_BCNQ_PGBNDY_V1_8822C(x, v) \
+ (BIT_CLEAR_BCNQ_PGBNDY_V1_8822C(x) | BIT_BCNQ_PGBNDY_V1_8822C(v))
+
+/* 2 REG_LIFETIME_EN_8822C */
+#define BIT_BT_INT_CPU_8822C BIT(7)
+#define BIT_BT_INT_PTA_8822C BIT(6)
+#define BIT_EN_CTRL_RTYBIT_8822C BIT(4)
+#define BIT_LIFETIME_BK_EN_8822C BIT(3)
+#define BIT_LIFETIME_BE_EN_8822C BIT(2)
+#define BIT_LIFETIME_VI_EN_8822C BIT(1)
+#define BIT_LIFETIME_VO_EN_8822C BIT(0)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_SPEC_SIFS_8822C */
+
+#define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822C 8
+#define BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822C 0xff
+#define BIT_SPEC_SIFS_OFDM_PTCL_8822C(x) \
+ (((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822C) \
+ << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822C)
+#define BITS_SPEC_SIFS_OFDM_PTCL_8822C \
+ (BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822C \
+ << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822C)
+#define BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8822C(x) \
+ ((x) & (~BITS_SPEC_SIFS_OFDM_PTCL_8822C))
+#define BIT_GET_SPEC_SIFS_OFDM_PTCL_8822C(x) \
+ (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8822C) & \
+ BIT_MASK_SPEC_SIFS_OFDM_PTCL_8822C)
+#define BIT_SET_SPEC_SIFS_OFDM_PTCL_8822C(x, v) \
+ (BIT_CLEAR_SPEC_SIFS_OFDM_PTCL_8822C(x) | \
+ BIT_SPEC_SIFS_OFDM_PTCL_8822C(v))
+
+#define BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822C 0
+#define BIT_MASK_SPEC_SIFS_CCK_PTCL_8822C 0xff
+#define BIT_SPEC_SIFS_CCK_PTCL_8822C(x) \
+ (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8822C) \
+ << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822C)
+#define BITS_SPEC_SIFS_CCK_PTCL_8822C \
+ (BIT_MASK_SPEC_SIFS_CCK_PTCL_8822C \
+ << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822C)
+#define BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8822C(x) \
+ ((x) & (~BITS_SPEC_SIFS_CCK_PTCL_8822C))
+#define BIT_GET_SPEC_SIFS_CCK_PTCL_8822C(x) \
+ (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8822C) & \
+ BIT_MASK_SPEC_SIFS_CCK_PTCL_8822C)
+#define BIT_SET_SPEC_SIFS_CCK_PTCL_8822C(x, v) \
+ (BIT_CLEAR_SPEC_SIFS_CCK_PTCL_8822C(x) | \
+ BIT_SPEC_SIFS_CCK_PTCL_8822C(v))
+
+/* 2 REG_RETRY_LIMIT_8822C */
+
+#define BIT_SHIFT_SRL_8822C 8
+#define BIT_MASK_SRL_8822C 0x3f
+#define BIT_SRL_8822C(x) (((x) & BIT_MASK_SRL_8822C) << BIT_SHIFT_SRL_8822C)
+#define BITS_SRL_8822C (BIT_MASK_SRL_8822C << BIT_SHIFT_SRL_8822C)
+#define BIT_CLEAR_SRL_8822C(x) ((x) & (~BITS_SRL_8822C))
+#define BIT_GET_SRL_8822C(x) (((x) >> BIT_SHIFT_SRL_8822C) & BIT_MASK_SRL_8822C)
+#define BIT_SET_SRL_8822C(x, v) (BIT_CLEAR_SRL_8822C(x) | BIT_SRL_8822C(v))
+
+#define BIT_SHIFT_LRL_8822C 0
+#define BIT_MASK_LRL_8822C 0x3f
+#define BIT_LRL_8822C(x) (((x) & BIT_MASK_LRL_8822C) << BIT_SHIFT_LRL_8822C)
+#define BITS_LRL_8822C (BIT_MASK_LRL_8822C << BIT_SHIFT_LRL_8822C)
+#define BIT_CLEAR_LRL_8822C(x) ((x) & (~BITS_LRL_8822C))
+#define BIT_GET_LRL_8822C(x) (((x) >> BIT_SHIFT_LRL_8822C) & BIT_MASK_LRL_8822C)
+#define BIT_SET_LRL_8822C(x, v) (BIT_CLEAR_LRL_8822C(x) | BIT_LRL_8822C(v))
+
+/* 2 REG_TXBF_CTRL_8822C */
+#define BIT_R_ENABLE_NDPA_8822C BIT(31)
+#define BIT_USE_NDPA_PARAMETER_8822C BIT(30)
+#define BIT_R_PROP_TXBF_8822C BIT(29)
+#define BIT_R_EN_NDPA_INT_8822C BIT(28)
+#define BIT_R_TXBF1_80M_8822C BIT(27)
+#define BIT_R_TXBF1_40M_8822C BIT(26)
+#define BIT_R_TXBF1_20M_8822C BIT(25)
+
+#define BIT_SHIFT_R_TXBF1_AID_8822C 16
+#define BIT_MASK_R_TXBF1_AID_8822C 0x1ff
+#define BIT_R_TXBF1_AID_8822C(x) \
+ (((x) & BIT_MASK_R_TXBF1_AID_8822C) << BIT_SHIFT_R_TXBF1_AID_8822C)
+#define BITS_R_TXBF1_AID_8822C \
+ (BIT_MASK_R_TXBF1_AID_8822C << BIT_SHIFT_R_TXBF1_AID_8822C)
+#define BIT_CLEAR_R_TXBF1_AID_8822C(x) ((x) & (~BITS_R_TXBF1_AID_8822C))
+#define BIT_GET_R_TXBF1_AID_8822C(x) \
+ (((x) >> BIT_SHIFT_R_TXBF1_AID_8822C) & BIT_MASK_R_TXBF1_AID_8822C)
+#define BIT_SET_R_TXBF1_AID_8822C(x, v) \
+ (BIT_CLEAR_R_TXBF1_AID_8822C(x) | BIT_R_TXBF1_AID_8822C(v))
+
+#define BIT_DIS_NDP_BFEN_8822C BIT(15)
+#define BIT_R_TXBCN_NOBLOCK_NDP_8822C BIT(14)
+#define BIT_R_TXBF0_80M_8822C BIT(11)
+#define BIT_R_TXBF0_40M_8822C BIT(10)
+#define BIT_R_TXBF0_20M_8822C BIT(9)
+
+#define BIT_SHIFT_R_TXBF0_AID_8822C 0
+#define BIT_MASK_R_TXBF0_AID_8822C 0x1ff
+#define BIT_R_TXBF0_AID_8822C(x) \
+ (((x) & BIT_MASK_R_TXBF0_AID_8822C) << BIT_SHIFT_R_TXBF0_AID_8822C)
+#define BITS_R_TXBF0_AID_8822C \
+ (BIT_MASK_R_TXBF0_AID_8822C << BIT_SHIFT_R_TXBF0_AID_8822C)
+#define BIT_CLEAR_R_TXBF0_AID_8822C(x) ((x) & (~BITS_R_TXBF0_AID_8822C))
+#define BIT_GET_R_TXBF0_AID_8822C(x) \
+ (((x) >> BIT_SHIFT_R_TXBF0_AID_8822C) & BIT_MASK_R_TXBF0_AID_8822C)
+#define BIT_SET_R_TXBF0_AID_8822C(x, v) \
+ (BIT_CLEAR_R_TXBF0_AID_8822C(x) | BIT_R_TXBF0_AID_8822C(v))
+
+/* 2 REG_DARFRC_8822C */
+
+#define BIT_SHIFT_DARF_RC4_8822C 24
+#define BIT_MASK_DARF_RC4_8822C 0x1f
+#define BIT_DARF_RC4_8822C(x) \
+ (((x) & BIT_MASK_DARF_RC4_8822C) << BIT_SHIFT_DARF_RC4_8822C)
+#define BITS_DARF_RC4_8822C \
+ (BIT_MASK_DARF_RC4_8822C << BIT_SHIFT_DARF_RC4_8822C)
+#define BIT_CLEAR_DARF_RC4_8822C(x) ((x) & (~BITS_DARF_RC4_8822C))
+#define BIT_GET_DARF_RC4_8822C(x) \
+ (((x) >> BIT_SHIFT_DARF_RC4_8822C) & BIT_MASK_DARF_RC4_8822C)
+#define BIT_SET_DARF_RC4_8822C(x, v) \
+ (BIT_CLEAR_DARF_RC4_8822C(x) | BIT_DARF_RC4_8822C(v))
+
+#define BIT_SHIFT_DARF_RC3_8822C 16
+#define BIT_MASK_DARF_RC3_8822C 0x1f
+#define BIT_DARF_RC3_8822C(x) \
+ (((x) & BIT_MASK_DARF_RC3_8822C) << BIT_SHIFT_DARF_RC3_8822C)
+#define BITS_DARF_RC3_8822C \
+ (BIT_MASK_DARF_RC3_8822C << BIT_SHIFT_DARF_RC3_8822C)
+#define BIT_CLEAR_DARF_RC3_8822C(x) ((x) & (~BITS_DARF_RC3_8822C))
+#define BIT_GET_DARF_RC3_8822C(x) \
+ (((x) >> BIT_SHIFT_DARF_RC3_8822C) & BIT_MASK_DARF_RC3_8822C)
+#define BIT_SET_DARF_RC3_8822C(x, v) \
+ (BIT_CLEAR_DARF_RC3_8822C(x) | BIT_DARF_RC3_8822C(v))
+
+#define BIT_SHIFT_DARF_RC2_8822C 8
+#define BIT_MASK_DARF_RC2_8822C 0x1f
+#define BIT_DARF_RC2_8822C(x) \
+ (((x) & BIT_MASK_DARF_RC2_8822C) << BIT_SHIFT_DARF_RC2_8822C)
+#define BITS_DARF_RC2_8822C \
+ (BIT_MASK_DARF_RC2_8822C << BIT_SHIFT_DARF_RC2_8822C)
+#define BIT_CLEAR_DARF_RC2_8822C(x) ((x) & (~BITS_DARF_RC2_8822C))
+#define BIT_GET_DARF_RC2_8822C(x) \
+ (((x) >> BIT_SHIFT_DARF_RC2_8822C) & BIT_MASK_DARF_RC2_8822C)
+#define BIT_SET_DARF_RC2_8822C(x, v) \
+ (BIT_CLEAR_DARF_RC2_8822C(x) | BIT_DARF_RC2_8822C(v))
+
+#define BIT_SHIFT_DARF_RC1_8822C 0
+#define BIT_MASK_DARF_RC1_8822C 0x1f
+#define BIT_DARF_RC1_8822C(x) \
+ (((x) & BIT_MASK_DARF_RC1_8822C) << BIT_SHIFT_DARF_RC1_8822C)
+#define BITS_DARF_RC1_8822C \
+ (BIT_MASK_DARF_RC1_8822C << BIT_SHIFT_DARF_RC1_8822C)
+#define BIT_CLEAR_DARF_RC1_8822C(x) ((x) & (~BITS_DARF_RC1_8822C))
+#define BIT_GET_DARF_RC1_8822C(x) \
+ (((x) >> BIT_SHIFT_DARF_RC1_8822C) & BIT_MASK_DARF_RC1_8822C)
+#define BIT_SET_DARF_RC1_8822C(x, v) \
+ (BIT_CLEAR_DARF_RC1_8822C(x) | BIT_DARF_RC1_8822C(v))
+
+/* 2 REG_DARFRCH_8822C */
+
+#define BIT_SHIFT_DARF_RC8_V1_8822C 24
+#define BIT_MASK_DARF_RC8_V1_8822C 0x1f
+#define BIT_DARF_RC8_V1_8822C(x) \
+ (((x) & BIT_MASK_DARF_RC8_V1_8822C) << BIT_SHIFT_DARF_RC8_V1_8822C)
+#define BITS_DARF_RC8_V1_8822C \
+ (BIT_MASK_DARF_RC8_V1_8822C << BIT_SHIFT_DARF_RC8_V1_8822C)
+#define BIT_CLEAR_DARF_RC8_V1_8822C(x) ((x) & (~BITS_DARF_RC8_V1_8822C))
+#define BIT_GET_DARF_RC8_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_DARF_RC8_V1_8822C) & BIT_MASK_DARF_RC8_V1_8822C)
+#define BIT_SET_DARF_RC8_V1_8822C(x, v) \
+ (BIT_CLEAR_DARF_RC8_V1_8822C(x) | BIT_DARF_RC8_V1_8822C(v))
+
+#define BIT_SHIFT_DARF_RC7_V1_8822C 16
+#define BIT_MASK_DARF_RC7_V1_8822C 0x1f
+#define BIT_DARF_RC7_V1_8822C(x) \
+ (((x) & BIT_MASK_DARF_RC7_V1_8822C) << BIT_SHIFT_DARF_RC7_V1_8822C)
+#define BITS_DARF_RC7_V1_8822C \
+ (BIT_MASK_DARF_RC7_V1_8822C << BIT_SHIFT_DARF_RC7_V1_8822C)
+#define BIT_CLEAR_DARF_RC7_V1_8822C(x) ((x) & (~BITS_DARF_RC7_V1_8822C))
+#define BIT_GET_DARF_RC7_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_DARF_RC7_V1_8822C) & BIT_MASK_DARF_RC7_V1_8822C)
+#define BIT_SET_DARF_RC7_V1_8822C(x, v) \
+ (BIT_CLEAR_DARF_RC7_V1_8822C(x) | BIT_DARF_RC7_V1_8822C(v))
+
+#define BIT_SHIFT_DARF_RC6_V1_8822C 8
+#define BIT_MASK_DARF_RC6_V1_8822C 0x1f
+#define BIT_DARF_RC6_V1_8822C(x) \
+ (((x) & BIT_MASK_DARF_RC6_V1_8822C) << BIT_SHIFT_DARF_RC6_V1_8822C)
+#define BITS_DARF_RC6_V1_8822C \
+ (BIT_MASK_DARF_RC6_V1_8822C << BIT_SHIFT_DARF_RC6_V1_8822C)
+#define BIT_CLEAR_DARF_RC6_V1_8822C(x) ((x) & (~BITS_DARF_RC6_V1_8822C))
+#define BIT_GET_DARF_RC6_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_DARF_RC6_V1_8822C) & BIT_MASK_DARF_RC6_V1_8822C)
+#define BIT_SET_DARF_RC6_V1_8822C(x, v) \
+ (BIT_CLEAR_DARF_RC6_V1_8822C(x) | BIT_DARF_RC6_V1_8822C(v))
+
+#define BIT_SHIFT_DARF_RC5_V1_8822C 0
+#define BIT_MASK_DARF_RC5_V1_8822C 0x1f
+#define BIT_DARF_RC5_V1_8822C(x) \
+ (((x) & BIT_MASK_DARF_RC5_V1_8822C) << BIT_SHIFT_DARF_RC5_V1_8822C)
+#define BITS_DARF_RC5_V1_8822C \
+ (BIT_MASK_DARF_RC5_V1_8822C << BIT_SHIFT_DARF_RC5_V1_8822C)
+#define BIT_CLEAR_DARF_RC5_V1_8822C(x) ((x) & (~BITS_DARF_RC5_V1_8822C))
+#define BIT_GET_DARF_RC5_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_DARF_RC5_V1_8822C) & BIT_MASK_DARF_RC5_V1_8822C)
+#define BIT_SET_DARF_RC5_V1_8822C(x, v) \
+ (BIT_CLEAR_DARF_RC5_V1_8822C(x) | BIT_DARF_RC5_V1_8822C(v))
+
+/* 2 REG_RARFRC_8822C */
+
+#define BIT_SHIFT_RARF_RC4_8822C 24
+#define BIT_MASK_RARF_RC4_8822C 0x1f
+#define BIT_RARF_RC4_8822C(x) \
+ (((x) & BIT_MASK_RARF_RC4_8822C) << BIT_SHIFT_RARF_RC4_8822C)
+#define BITS_RARF_RC4_8822C \
+ (BIT_MASK_RARF_RC4_8822C << BIT_SHIFT_RARF_RC4_8822C)
+#define BIT_CLEAR_RARF_RC4_8822C(x) ((x) & (~BITS_RARF_RC4_8822C))
+#define BIT_GET_RARF_RC4_8822C(x) \
+ (((x) >> BIT_SHIFT_RARF_RC4_8822C) & BIT_MASK_RARF_RC4_8822C)
+#define BIT_SET_RARF_RC4_8822C(x, v) \
+ (BIT_CLEAR_RARF_RC4_8822C(x) | BIT_RARF_RC4_8822C(v))
+
+#define BIT_SHIFT_RARF_RC3_8822C 16
+#define BIT_MASK_RARF_RC3_8822C 0x1f
+#define BIT_RARF_RC3_8822C(x) \
+ (((x) & BIT_MASK_RARF_RC3_8822C) << BIT_SHIFT_RARF_RC3_8822C)
+#define BITS_RARF_RC3_8822C \
+ (BIT_MASK_RARF_RC3_8822C << BIT_SHIFT_RARF_RC3_8822C)
+#define BIT_CLEAR_RARF_RC3_8822C(x) ((x) & (~BITS_RARF_RC3_8822C))
+#define BIT_GET_RARF_RC3_8822C(x) \
+ (((x) >> BIT_SHIFT_RARF_RC3_8822C) & BIT_MASK_RARF_RC3_8822C)
+#define BIT_SET_RARF_RC3_8822C(x, v) \
+ (BIT_CLEAR_RARF_RC3_8822C(x) | BIT_RARF_RC3_8822C(v))
+
+#define BIT_SHIFT_RARF_RC2_8822C 8
+#define BIT_MASK_RARF_RC2_8822C 0x1f
+#define BIT_RARF_RC2_8822C(x) \
+ (((x) & BIT_MASK_RARF_RC2_8822C) << BIT_SHIFT_RARF_RC2_8822C)
+#define BITS_RARF_RC2_8822C \
+ (BIT_MASK_RARF_RC2_8822C << BIT_SHIFT_RARF_RC2_8822C)
+#define BIT_CLEAR_RARF_RC2_8822C(x) ((x) & (~BITS_RARF_RC2_8822C))
+#define BIT_GET_RARF_RC2_8822C(x) \
+ (((x) >> BIT_SHIFT_RARF_RC2_8822C) & BIT_MASK_RARF_RC2_8822C)
+#define BIT_SET_RARF_RC2_8822C(x, v) \
+ (BIT_CLEAR_RARF_RC2_8822C(x) | BIT_RARF_RC2_8822C(v))
+
+#define BIT_SHIFT_RARF_RC1_8822C 0
+#define BIT_MASK_RARF_RC1_8822C 0x1f
+#define BIT_RARF_RC1_8822C(x) \
+ (((x) & BIT_MASK_RARF_RC1_8822C) << BIT_SHIFT_RARF_RC1_8822C)
+#define BITS_RARF_RC1_8822C \
+ (BIT_MASK_RARF_RC1_8822C << BIT_SHIFT_RARF_RC1_8822C)
+#define BIT_CLEAR_RARF_RC1_8822C(x) ((x) & (~BITS_RARF_RC1_8822C))
+#define BIT_GET_RARF_RC1_8822C(x) \
+ (((x) >> BIT_SHIFT_RARF_RC1_8822C) & BIT_MASK_RARF_RC1_8822C)
+#define BIT_SET_RARF_RC1_8822C(x, v) \
+ (BIT_CLEAR_RARF_RC1_8822C(x) | BIT_RARF_RC1_8822C(v))
+
+/* 2 REG_RARFRCH_8822C */
+
+#define BIT_SHIFT_RARF_RC8_V1_8822C 24
+#define BIT_MASK_RARF_RC8_V1_8822C 0x1f
+#define BIT_RARF_RC8_V1_8822C(x) \
+ (((x) & BIT_MASK_RARF_RC8_V1_8822C) << BIT_SHIFT_RARF_RC8_V1_8822C)
+#define BITS_RARF_RC8_V1_8822C \
+ (BIT_MASK_RARF_RC8_V1_8822C << BIT_SHIFT_RARF_RC8_V1_8822C)
+#define BIT_CLEAR_RARF_RC8_V1_8822C(x) ((x) & (~BITS_RARF_RC8_V1_8822C))
+#define BIT_GET_RARF_RC8_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_RARF_RC8_V1_8822C) & BIT_MASK_RARF_RC8_V1_8822C)
+#define BIT_SET_RARF_RC8_V1_8822C(x, v) \
+ (BIT_CLEAR_RARF_RC8_V1_8822C(x) | BIT_RARF_RC8_V1_8822C(v))
+
+#define BIT_SHIFT_RARF_RC7_V1_8822C 16
+#define BIT_MASK_RARF_RC7_V1_8822C 0x1f
+#define BIT_RARF_RC7_V1_8822C(x) \
+ (((x) & BIT_MASK_RARF_RC7_V1_8822C) << BIT_SHIFT_RARF_RC7_V1_8822C)
+#define BITS_RARF_RC7_V1_8822C \
+ (BIT_MASK_RARF_RC7_V1_8822C << BIT_SHIFT_RARF_RC7_V1_8822C)
+#define BIT_CLEAR_RARF_RC7_V1_8822C(x) ((x) & (~BITS_RARF_RC7_V1_8822C))
+#define BIT_GET_RARF_RC7_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_RARF_RC7_V1_8822C) & BIT_MASK_RARF_RC7_V1_8822C)
+#define BIT_SET_RARF_RC7_V1_8822C(x, v) \
+ (BIT_CLEAR_RARF_RC7_V1_8822C(x) | BIT_RARF_RC7_V1_8822C(v))
+
+#define BIT_SHIFT_RARF_RC6_V1_8822C 8
+#define BIT_MASK_RARF_RC6_V1_8822C 0x1f
+#define BIT_RARF_RC6_V1_8822C(x) \
+ (((x) & BIT_MASK_RARF_RC6_V1_8822C) << BIT_SHIFT_RARF_RC6_V1_8822C)
+#define BITS_RARF_RC6_V1_8822C \
+ (BIT_MASK_RARF_RC6_V1_8822C << BIT_SHIFT_RARF_RC6_V1_8822C)
+#define BIT_CLEAR_RARF_RC6_V1_8822C(x) ((x) & (~BITS_RARF_RC6_V1_8822C))
+#define BIT_GET_RARF_RC6_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_RARF_RC6_V1_8822C) & BIT_MASK_RARF_RC6_V1_8822C)
+#define BIT_SET_RARF_RC6_V1_8822C(x, v) \
+ (BIT_CLEAR_RARF_RC6_V1_8822C(x) | BIT_RARF_RC6_V1_8822C(v))
+
+#define BIT_SHIFT_RARF_RC5_V1_8822C 0
+#define BIT_MASK_RARF_RC5_V1_8822C 0x1f
+#define BIT_RARF_RC5_V1_8822C(x) \
+ (((x) & BIT_MASK_RARF_RC5_V1_8822C) << BIT_SHIFT_RARF_RC5_V1_8822C)
+#define BITS_RARF_RC5_V1_8822C \
+ (BIT_MASK_RARF_RC5_V1_8822C << BIT_SHIFT_RARF_RC5_V1_8822C)
+#define BIT_CLEAR_RARF_RC5_V1_8822C(x) ((x) & (~BITS_RARF_RC5_V1_8822C))
+#define BIT_GET_RARF_RC5_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_RARF_RC5_V1_8822C) & BIT_MASK_RARF_RC5_V1_8822C)
+#define BIT_SET_RARF_RC5_V1_8822C(x, v) \
+ (BIT_CLEAR_RARF_RC5_V1_8822C(x) | BIT_RARF_RC5_V1_8822C(v))
+
+/* 2 REG_RRSR_8822C */
+
+#define BIT_SHIFT_RRSR_RSC_8822C 21
+#define BIT_MASK_RRSR_RSC_8822C 0x3
+#define BIT_RRSR_RSC_8822C(x) \
+ (((x) & BIT_MASK_RRSR_RSC_8822C) << BIT_SHIFT_RRSR_RSC_8822C)
+#define BITS_RRSR_RSC_8822C \
+ (BIT_MASK_RRSR_RSC_8822C << BIT_SHIFT_RRSR_RSC_8822C)
+#define BIT_CLEAR_RRSR_RSC_8822C(x) ((x) & (~BITS_RRSR_RSC_8822C))
+#define BIT_GET_RRSR_RSC_8822C(x) \
+ (((x) >> BIT_SHIFT_RRSR_RSC_8822C) & BIT_MASK_RRSR_RSC_8822C)
+#define BIT_SET_RRSR_RSC_8822C(x, v) \
+ (BIT_CLEAR_RRSR_RSC_8822C(x) | BIT_RRSR_RSC_8822C(v))
+
+#define BIT_SHIFT_RRSC_BITMAP_8822C 0
+#define BIT_MASK_RRSC_BITMAP_8822C 0xfffff
+#define BIT_RRSC_BITMAP_8822C(x) \
+ (((x) & BIT_MASK_RRSC_BITMAP_8822C) << BIT_SHIFT_RRSC_BITMAP_8822C)
+#define BITS_RRSC_BITMAP_8822C \
+ (BIT_MASK_RRSC_BITMAP_8822C << BIT_SHIFT_RRSC_BITMAP_8822C)
+#define BIT_CLEAR_RRSC_BITMAP_8822C(x) ((x) & (~BITS_RRSC_BITMAP_8822C))
+#define BIT_GET_RRSC_BITMAP_8822C(x) \
+ (((x) >> BIT_SHIFT_RRSC_BITMAP_8822C) & BIT_MASK_RRSC_BITMAP_8822C)
+#define BIT_SET_RRSC_BITMAP_8822C(x, v) \
+ (BIT_CLEAR_RRSC_BITMAP_8822C(x) | BIT_RRSC_BITMAP_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_ARFR0_8822C */
+
+#define BIT_SHIFT_ARFRL0_8822C 0
+#define BIT_MASK_ARFRL0_8822C 0xffffffffL
+#define BIT_ARFRL0_8822C(x) \
+ (((x) & BIT_MASK_ARFRL0_8822C) << BIT_SHIFT_ARFRL0_8822C)
+#define BITS_ARFRL0_8822C (BIT_MASK_ARFRL0_8822C << BIT_SHIFT_ARFRL0_8822C)
+#define BIT_CLEAR_ARFRL0_8822C(x) ((x) & (~BITS_ARFRL0_8822C))
+#define BIT_GET_ARFRL0_8822C(x) \
+ (((x) >> BIT_SHIFT_ARFRL0_8822C) & BIT_MASK_ARFRL0_8822C)
+#define BIT_SET_ARFRL0_8822C(x, v) \
+ (BIT_CLEAR_ARFRL0_8822C(x) | BIT_ARFRL0_8822C(v))
+
+/* 2 REG_ARFRH0_8822C */
+
+#define BIT_SHIFT_ARFRH0_8822C 0
+#define BIT_MASK_ARFRH0_8822C 0xffffffffL
+#define BIT_ARFRH0_8822C(x) \
+ (((x) & BIT_MASK_ARFRH0_8822C) << BIT_SHIFT_ARFRH0_8822C)
+#define BITS_ARFRH0_8822C (BIT_MASK_ARFRH0_8822C << BIT_SHIFT_ARFRH0_8822C)
+#define BIT_CLEAR_ARFRH0_8822C(x) ((x) & (~BITS_ARFRH0_8822C))
+#define BIT_GET_ARFRH0_8822C(x) \
+ (((x) >> BIT_SHIFT_ARFRH0_8822C) & BIT_MASK_ARFRH0_8822C)
+#define BIT_SET_ARFRH0_8822C(x, v) \
+ (BIT_CLEAR_ARFRH0_8822C(x) | BIT_ARFRH0_8822C(v))
+
+/* 2 REG_ARFR1_V1_8822C */
+
+#define BIT_SHIFT_ARFRL1_8822C 0
+#define BIT_MASK_ARFRL1_8822C 0xffffffffL
+#define BIT_ARFRL1_8822C(x) \
+ (((x) & BIT_MASK_ARFRL1_8822C) << BIT_SHIFT_ARFRL1_8822C)
+#define BITS_ARFRL1_8822C (BIT_MASK_ARFRL1_8822C << BIT_SHIFT_ARFRL1_8822C)
+#define BIT_CLEAR_ARFRL1_8822C(x) ((x) & (~BITS_ARFRL1_8822C))
+#define BIT_GET_ARFRL1_8822C(x) \
+ (((x) >> BIT_SHIFT_ARFRL1_8822C) & BIT_MASK_ARFRL1_8822C)
+#define BIT_SET_ARFRL1_8822C(x, v) \
+ (BIT_CLEAR_ARFRL1_8822C(x) | BIT_ARFRL1_8822C(v))
+
+/* 2 REG_ARFRH1_V1_8822C */
+
+#define BIT_SHIFT_ARFRH1_8822C 0
+#define BIT_MASK_ARFRH1_8822C 0xffffffffL
+#define BIT_ARFRH1_8822C(x) \
+ (((x) & BIT_MASK_ARFRH1_8822C) << BIT_SHIFT_ARFRH1_8822C)
+#define BITS_ARFRH1_8822C (BIT_MASK_ARFRH1_8822C << BIT_SHIFT_ARFRH1_8822C)
+#define BIT_CLEAR_ARFRH1_8822C(x) ((x) & (~BITS_ARFRH1_8822C))
+#define BIT_GET_ARFRH1_8822C(x) \
+ (((x) >> BIT_SHIFT_ARFRH1_8822C) & BIT_MASK_ARFRH1_8822C)
+#define BIT_SET_ARFRH1_8822C(x, v) \
+ (BIT_CLEAR_ARFRH1_8822C(x) | BIT_ARFRH1_8822C(v))
+
+/* 2 REG_CCK_CHECK_8822C */
+#define BIT_CHECK_CCK_EN_8822C BIT(7)
+#define BIT_EN_BCN_PKT_REL_8822C BIT(6)
+#define BIT_BCN_PORT_SEL_8822C BIT(5)
+#define BIT_MOREDATA_BYPASS_8822C BIT(4)
+#define BIT_EN_CLR_CMD_REL_BCN_PKT_8822C BIT(3)
+#define BIT_R_EN_SET_MOREDATA_8822C BIT(2)
+#define BIT__R_DIS_CLEAR_MACID_RELEASE_8822C BIT(1)
+#define BIT__R_MACID_RELEASE_EN_8822C BIT(0)
+
+/* 2 REG_AMPDU_MAX_TIME_V1_8822C */
+
+#define BIT_SHIFT_AMPDU_MAX_TIME_8822C 0
+#define BIT_MASK_AMPDU_MAX_TIME_8822C 0xff
+#define BIT_AMPDU_MAX_TIME_8822C(x) \
+ (((x) & BIT_MASK_AMPDU_MAX_TIME_8822C) \
+ << BIT_SHIFT_AMPDU_MAX_TIME_8822C)
+#define BITS_AMPDU_MAX_TIME_8822C \
+ (BIT_MASK_AMPDU_MAX_TIME_8822C << BIT_SHIFT_AMPDU_MAX_TIME_8822C)
+#define BIT_CLEAR_AMPDU_MAX_TIME_8822C(x) ((x) & (~BITS_AMPDU_MAX_TIME_8822C))
+#define BIT_GET_AMPDU_MAX_TIME_8822C(x) \
+ (((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8822C) & \
+ BIT_MASK_AMPDU_MAX_TIME_8822C)
+#define BIT_SET_AMPDU_MAX_TIME_8822C(x, v) \
+ (BIT_CLEAR_AMPDU_MAX_TIME_8822C(x) | BIT_AMPDU_MAX_TIME_8822C(v))
+
+/* 2 REG_BCNQ1_BDNY_V1_8822C */
+
+#define BIT_SHIFT_BCNQ1_PGBNDY_V1_8822C 0
+#define BIT_MASK_BCNQ1_PGBNDY_V1_8822C 0xfff
+#define BIT_BCNQ1_PGBNDY_V1_8822C(x) \
+ (((x) & BIT_MASK_BCNQ1_PGBNDY_V1_8822C) \
+ << BIT_SHIFT_BCNQ1_PGBNDY_V1_8822C)
+#define BITS_BCNQ1_PGBNDY_V1_8822C \
+ (BIT_MASK_BCNQ1_PGBNDY_V1_8822C << BIT_SHIFT_BCNQ1_PGBNDY_V1_8822C)
+#define BIT_CLEAR_BCNQ1_PGBNDY_V1_8822C(x) ((x) & (~BITS_BCNQ1_PGBNDY_V1_8822C))
+#define BIT_GET_BCNQ1_PGBNDY_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1_8822C) & \
+ BIT_MASK_BCNQ1_PGBNDY_V1_8822C)
+#define BIT_SET_BCNQ1_PGBNDY_V1_8822C(x, v) \
+ (BIT_CLEAR_BCNQ1_PGBNDY_V1_8822C(x) | BIT_BCNQ1_PGBNDY_V1_8822C(v))
+
+/* 2 REG_AMPDU_MAX_LENGTH_HT_8822C */
+
+#define BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8822C 0
+#define BIT_MASK_AMPDU_MAX_LENGTH_HT_8822C 0xffff
+#define BIT_AMPDU_MAX_LENGTH_HT_8822C(x) \
+ (((x) & BIT_MASK_AMPDU_MAX_LENGTH_HT_8822C) \
+ << BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8822C)
+#define BITS_AMPDU_MAX_LENGTH_HT_8822C \
+ (BIT_MASK_AMPDU_MAX_LENGTH_HT_8822C \
+ << BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8822C)
+#define BIT_CLEAR_AMPDU_MAX_LENGTH_HT_8822C(x) \
+ ((x) & (~BITS_AMPDU_MAX_LENGTH_HT_8822C))
+#define BIT_GET_AMPDU_MAX_LENGTH_HT_8822C(x) \
+ (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_HT_8822C) & \
+ BIT_MASK_AMPDU_MAX_LENGTH_HT_8822C)
+#define BIT_SET_AMPDU_MAX_LENGTH_HT_8822C(x, v) \
+ (BIT_CLEAR_AMPDU_MAX_LENGTH_HT_8822C(x) | \
+ BIT_AMPDU_MAX_LENGTH_HT_8822C(v))
+
+/* 2 REG_ACQ_STOP_8822C */
+#define BIT_AC7Q_STOP_8822C BIT(7)
+#define BIT_AC6Q_STOP_8822C BIT(6)
+#define BIT_AC5Q_STOP_8822C BIT(5)
+#define BIT_AC4Q_STOP_8822C BIT(4)
+#define BIT_AC3Q_STOP_8822C BIT(3)
+#define BIT_AC2Q_STOP_8822C BIT(2)
+#define BIT_AC1Q_STOP_8822C BIT(1)
+#define BIT_AC0Q_STOP_8822C BIT(0)
+
+/* 2 REG_NDPA_RATE_8822C */
+
+#define BIT_SHIFT_R_NDPA_RATE_V1_8822C 0
+#define BIT_MASK_R_NDPA_RATE_V1_8822C 0xff
+#define BIT_R_NDPA_RATE_V1_8822C(x) \
+ (((x) & BIT_MASK_R_NDPA_RATE_V1_8822C) \
+ << BIT_SHIFT_R_NDPA_RATE_V1_8822C)
+#define BITS_R_NDPA_RATE_V1_8822C \
+ (BIT_MASK_R_NDPA_RATE_V1_8822C << BIT_SHIFT_R_NDPA_RATE_V1_8822C)
+#define BIT_CLEAR_R_NDPA_RATE_V1_8822C(x) ((x) & (~BITS_R_NDPA_RATE_V1_8822C))
+#define BIT_GET_R_NDPA_RATE_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8822C) & \
+ BIT_MASK_R_NDPA_RATE_V1_8822C)
+#define BIT_SET_R_NDPA_RATE_V1_8822C(x, v) \
+ (BIT_CLEAR_R_NDPA_RATE_V1_8822C(x) | BIT_R_NDPA_RATE_V1_8822C(v))
+
+/* 2 REG_TX_HANG_CTRL_8822C */
+#define BIT_R_EN_GNT_BT_AWAKE_8822C BIT(3)
+#define BIT_EN_EOF_V1_8822C BIT(2)
+#define BIT_DIS_OQT_BLOCK_8822C BIT(1)
+#define BIT_SEARCH_QUEUE_EN_8822C BIT(0)
+
+/* 2 REG_NDPA_OPT_CTRL_8822C */
+#define BIT_R_DIS_MACID_RELEASE_RTY_8822C BIT(5)
+
+#define BIT_SHIFT_BW_SIGTA_8822C 3
+#define BIT_MASK_BW_SIGTA_8822C 0x3
+#define BIT_BW_SIGTA_8822C(x) \
+ (((x) & BIT_MASK_BW_SIGTA_8822C) << BIT_SHIFT_BW_SIGTA_8822C)
+#define BITS_BW_SIGTA_8822C \
+ (BIT_MASK_BW_SIGTA_8822C << BIT_SHIFT_BW_SIGTA_8822C)
+#define BIT_CLEAR_BW_SIGTA_8822C(x) ((x) & (~BITS_BW_SIGTA_8822C))
+#define BIT_GET_BW_SIGTA_8822C(x) \
+ (((x) >> BIT_SHIFT_BW_SIGTA_8822C) & BIT_MASK_BW_SIGTA_8822C)
+#define BIT_SET_BW_SIGTA_8822C(x, v) \
+ (BIT_CLEAR_BW_SIGTA_8822C(x) | BIT_BW_SIGTA_8822C(v))
+
+#define BIT_EN_BAR_SIGTA_8822C BIT(2)
+
+#define BIT_SHIFT_R_NDPA_BW_8822C 0
+#define BIT_MASK_R_NDPA_BW_8822C 0x3
+#define BIT_R_NDPA_BW_8822C(x) \
+ (((x) & BIT_MASK_R_NDPA_BW_8822C) << BIT_SHIFT_R_NDPA_BW_8822C)
+#define BITS_R_NDPA_BW_8822C \
+ (BIT_MASK_R_NDPA_BW_8822C << BIT_SHIFT_R_NDPA_BW_8822C)
+#define BIT_CLEAR_R_NDPA_BW_8822C(x) ((x) & (~BITS_R_NDPA_BW_8822C))
+#define BIT_GET_R_NDPA_BW_8822C(x) \
+ (((x) >> BIT_SHIFT_R_NDPA_BW_8822C) & BIT_MASK_R_NDPA_BW_8822C)
+#define BIT_SET_R_NDPA_BW_8822C(x, v) \
+ (BIT_CLEAR_R_NDPA_BW_8822C(x) | BIT_R_NDPA_BW_8822C(v))
+
+/* 2 REG_AMPDU_MAX_LENGTH_VHT_8822C */
+
+#define BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1_8822C 0
+#define BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1_8822C 0xfffff
+#define BIT_AMPDU_MAX_LENGTH_VHT_V1_8822C(x) \
+ (((x) & BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1_8822C) \
+ << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1_8822C)
+#define BITS_AMPDU_MAX_LENGTH_VHT_V1_8822C \
+ (BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1_8822C \
+ << BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1_8822C)
+#define BIT_CLEAR_AMPDU_MAX_LENGTH_VHT_V1_8822C(x) \
+ ((x) & (~BITS_AMPDU_MAX_LENGTH_VHT_V1_8822C))
+#define BIT_GET_AMPDU_MAX_LENGTH_VHT_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_VHT_V1_8822C) & \
+ BIT_MASK_AMPDU_MAX_LENGTH_VHT_V1_8822C)
+#define BIT_SET_AMPDU_MAX_LENGTH_VHT_V1_8822C(x, v) \
+ (BIT_CLEAR_AMPDU_MAX_LENGTH_VHT_V1_8822C(x) | \
+ BIT_AMPDU_MAX_LENGTH_VHT_V1_8822C(v))
+
+/* 2 REG_RD_RESP_PKT_TH_8822C */
+
+#define BIT_SHIFT_RD_RESP_PKT_TH_V1_8822C 0
+#define BIT_MASK_RD_RESP_PKT_TH_V1_8822C 0x3f
+#define BIT_RD_RESP_PKT_TH_V1_8822C(x) \
+ (((x) & BIT_MASK_RD_RESP_PKT_TH_V1_8822C) \
+ << BIT_SHIFT_RD_RESP_PKT_TH_V1_8822C)
+#define BITS_RD_RESP_PKT_TH_V1_8822C \
+ (BIT_MASK_RD_RESP_PKT_TH_V1_8822C << BIT_SHIFT_RD_RESP_PKT_TH_V1_8822C)
+#define BIT_CLEAR_RD_RESP_PKT_TH_V1_8822C(x) \
+ ((x) & (~BITS_RD_RESP_PKT_TH_V1_8822C))
+#define BIT_GET_RD_RESP_PKT_TH_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8822C) & \
+ BIT_MASK_RD_RESP_PKT_TH_V1_8822C)
+#define BIT_SET_RD_RESP_PKT_TH_V1_8822C(x, v) \
+ (BIT_CLEAR_RD_RESP_PKT_TH_V1_8822C(x) | BIT_RD_RESP_PKT_TH_V1_8822C(v))
+
+/* 2 REG_CMDQ_INFO_8822C */
+
+#define BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822C 25
+#define BIT_MASK_QUEUEMACID_CMDQ_V1_8822C 0x7f
+#define BIT_QUEUEMACID_CMDQ_V1_8822C(x) \
+ (((x) & BIT_MASK_QUEUEMACID_CMDQ_V1_8822C) \
+ << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822C)
+#define BITS_QUEUEMACID_CMDQ_V1_8822C \
+ (BIT_MASK_QUEUEMACID_CMDQ_V1_8822C \
+ << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822C)
+#define BIT_CLEAR_QUEUEMACID_CMDQ_V1_8822C(x) \
+ ((x) & (~BITS_QUEUEMACID_CMDQ_V1_8822C))
+#define BIT_GET_QUEUEMACID_CMDQ_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1_8822C) & \
+ BIT_MASK_QUEUEMACID_CMDQ_V1_8822C)
+#define BIT_SET_QUEUEMACID_CMDQ_V1_8822C(x, v) \
+ (BIT_CLEAR_QUEUEMACID_CMDQ_V1_8822C(x) | \
+ BIT_QUEUEMACID_CMDQ_V1_8822C(v))
+
+#define BIT_SHIFT_QUEUEAC_CMDQ_V1_8822C 23
+#define BIT_MASK_QUEUEAC_CMDQ_V1_8822C 0x3
+#define BIT_QUEUEAC_CMDQ_V1_8822C(x) \
+ (((x) & BIT_MASK_QUEUEAC_CMDQ_V1_8822C) \
+ << BIT_SHIFT_QUEUEAC_CMDQ_V1_8822C)
+#define BITS_QUEUEAC_CMDQ_V1_8822C \
+ (BIT_MASK_QUEUEAC_CMDQ_V1_8822C << BIT_SHIFT_QUEUEAC_CMDQ_V1_8822C)
+#define BIT_CLEAR_QUEUEAC_CMDQ_V1_8822C(x) ((x) & (~BITS_QUEUEAC_CMDQ_V1_8822C))
+#define BIT_GET_QUEUEAC_CMDQ_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1_8822C) & \
+ BIT_MASK_QUEUEAC_CMDQ_V1_8822C)
+#define BIT_SET_QUEUEAC_CMDQ_V1_8822C(x, v) \
+ (BIT_CLEAR_QUEUEAC_CMDQ_V1_8822C(x) | BIT_QUEUEAC_CMDQ_V1_8822C(v))
+
+#define BIT_TIDEMPTY_CMDQ_V1_8822C BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q4_V2_8822C 11
+#define BIT_MASK_TAIL_PKT_Q4_V2_8822C 0x7ff
+#define BIT_TAIL_PKT_Q4_V2_8822C(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q4_V2_8822C) \
+ << BIT_SHIFT_TAIL_PKT_Q4_V2_8822C)
+#define BITS_TAIL_PKT_Q4_V2_8822C \
+ (BIT_MASK_TAIL_PKT_Q4_V2_8822C << BIT_SHIFT_TAIL_PKT_Q4_V2_8822C)
+#define BIT_CLEAR_TAIL_PKT_Q4_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q4_V2_8822C))
+#define BIT_GET_TAIL_PKT_Q4_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8822C) & \
+ BIT_MASK_TAIL_PKT_Q4_V2_8822C)
+#define BIT_SET_TAIL_PKT_Q4_V2_8822C(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q4_V2_8822C(x) | BIT_TAIL_PKT_Q4_V2_8822C(v))
+
+#define BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822C 0
+#define BIT_MASK_HEAD_PKT_CMDQ_V1_8822C 0x7ff
+#define BIT_HEAD_PKT_CMDQ_V1_8822C(x) \
+ (((x) & BIT_MASK_HEAD_PKT_CMDQ_V1_8822C) \
+ << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822C)
+#define BITS_HEAD_PKT_CMDQ_V1_8822C \
+ (BIT_MASK_HEAD_PKT_CMDQ_V1_8822C << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822C)
+#define BIT_CLEAR_HEAD_PKT_CMDQ_V1_8822C(x) \
+ ((x) & (~BITS_HEAD_PKT_CMDQ_V1_8822C))
+#define BIT_GET_HEAD_PKT_CMDQ_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1_8822C) & \
+ BIT_MASK_HEAD_PKT_CMDQ_V1_8822C)
+#define BIT_SET_HEAD_PKT_CMDQ_V1_8822C(x, v) \
+ (BIT_CLEAR_HEAD_PKT_CMDQ_V1_8822C(x) | BIT_HEAD_PKT_CMDQ_V1_8822C(v))
+
+/* 2 REG_Q4_INFO_8822C */
+
+#define BIT_SHIFT_QUEUEMACID_Q4_V1_8822C 25
+#define BIT_MASK_QUEUEMACID_Q4_V1_8822C 0x7f
+#define BIT_QUEUEMACID_Q4_V1_8822C(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q4_V1_8822C) \
+ << BIT_SHIFT_QUEUEMACID_Q4_V1_8822C)
+#define BITS_QUEUEMACID_Q4_V1_8822C \
+ (BIT_MASK_QUEUEMACID_Q4_V1_8822C << BIT_SHIFT_QUEUEMACID_Q4_V1_8822C)
+#define BIT_CLEAR_QUEUEMACID_Q4_V1_8822C(x) \
+ ((x) & (~BITS_QUEUEMACID_Q4_V1_8822C))
+#define BIT_GET_QUEUEMACID_Q4_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1_8822C) & \
+ BIT_MASK_QUEUEMACID_Q4_V1_8822C)
+#define BIT_SET_QUEUEMACID_Q4_V1_8822C(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q4_V1_8822C(x) | BIT_QUEUEMACID_Q4_V1_8822C(v))
+
+#define BIT_SHIFT_QUEUEAC_Q4_V1_8822C 23
+#define BIT_MASK_QUEUEAC_Q4_V1_8822C 0x3
+#define BIT_QUEUEAC_Q4_V1_8822C(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q4_V1_8822C) << BIT_SHIFT_QUEUEAC_Q4_V1_8822C)
+#define BITS_QUEUEAC_Q4_V1_8822C \
+ (BIT_MASK_QUEUEAC_Q4_V1_8822C << BIT_SHIFT_QUEUEAC_Q4_V1_8822C)
+#define BIT_CLEAR_QUEUEAC_Q4_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q4_V1_8822C))
+#define BIT_GET_QUEUEAC_Q4_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q4_V1_8822C) & BIT_MASK_QUEUEAC_Q4_V1_8822C)
+#define BIT_SET_QUEUEAC_Q4_V1_8822C(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q4_V1_8822C(x) | BIT_QUEUEAC_Q4_V1_8822C(v))
+
+#define BIT_TIDEMPTY_Q4_V1_8822C BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q4_V2_8822C 11
+#define BIT_MASK_TAIL_PKT_Q4_V2_8822C 0x7ff
+#define BIT_TAIL_PKT_Q4_V2_8822C(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q4_V2_8822C) \
+ << BIT_SHIFT_TAIL_PKT_Q4_V2_8822C)
+#define BITS_TAIL_PKT_Q4_V2_8822C \
+ (BIT_MASK_TAIL_PKT_Q4_V2_8822C << BIT_SHIFT_TAIL_PKT_Q4_V2_8822C)
+#define BIT_CLEAR_TAIL_PKT_Q4_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q4_V2_8822C))
+#define BIT_GET_TAIL_PKT_Q4_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8822C) & \
+ BIT_MASK_TAIL_PKT_Q4_V2_8822C)
+#define BIT_SET_TAIL_PKT_Q4_V2_8822C(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q4_V2_8822C(x) | BIT_TAIL_PKT_Q4_V2_8822C(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q4_V1_8822C 0
+#define BIT_MASK_HEAD_PKT_Q4_V1_8822C 0x7ff
+#define BIT_HEAD_PKT_Q4_V1_8822C(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q4_V1_8822C) \
+ << BIT_SHIFT_HEAD_PKT_Q4_V1_8822C)
+#define BITS_HEAD_PKT_Q4_V1_8822C \
+ (BIT_MASK_HEAD_PKT_Q4_V1_8822C << BIT_SHIFT_HEAD_PKT_Q4_V1_8822C)
+#define BIT_CLEAR_HEAD_PKT_Q4_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q4_V1_8822C))
+#define BIT_GET_HEAD_PKT_Q4_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1_8822C) & \
+ BIT_MASK_HEAD_PKT_Q4_V1_8822C)
+#define BIT_SET_HEAD_PKT_Q4_V1_8822C(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q4_V1_8822C(x) | BIT_HEAD_PKT_Q4_V1_8822C(v))
+
+/* 2 REG_Q5_INFO_8822C */
+
+#define BIT_SHIFT_QUEUEMACID_Q5_V1_8822C 25
+#define BIT_MASK_QUEUEMACID_Q5_V1_8822C 0x7f
+#define BIT_QUEUEMACID_Q5_V1_8822C(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q5_V1_8822C) \
+ << BIT_SHIFT_QUEUEMACID_Q5_V1_8822C)
+#define BITS_QUEUEMACID_Q5_V1_8822C \
+ (BIT_MASK_QUEUEMACID_Q5_V1_8822C << BIT_SHIFT_QUEUEMACID_Q5_V1_8822C)
+#define BIT_CLEAR_QUEUEMACID_Q5_V1_8822C(x) \
+ ((x) & (~BITS_QUEUEMACID_Q5_V1_8822C))
+#define BIT_GET_QUEUEMACID_Q5_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1_8822C) & \
+ BIT_MASK_QUEUEMACID_Q5_V1_8822C)
+#define BIT_SET_QUEUEMACID_Q5_V1_8822C(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q5_V1_8822C(x) | BIT_QUEUEMACID_Q5_V1_8822C(v))
+
+#define BIT_SHIFT_QUEUEAC_Q5_V1_8822C 23
+#define BIT_MASK_QUEUEAC_Q5_V1_8822C 0x3
+#define BIT_QUEUEAC_Q5_V1_8822C(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q5_V1_8822C) << BIT_SHIFT_QUEUEAC_Q5_V1_8822C)
+#define BITS_QUEUEAC_Q5_V1_8822C \
+ (BIT_MASK_QUEUEAC_Q5_V1_8822C << BIT_SHIFT_QUEUEAC_Q5_V1_8822C)
+#define BIT_CLEAR_QUEUEAC_Q5_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q5_V1_8822C))
+#define BIT_GET_QUEUEAC_Q5_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q5_V1_8822C) & BIT_MASK_QUEUEAC_Q5_V1_8822C)
+#define BIT_SET_QUEUEAC_Q5_V1_8822C(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q5_V1_8822C(x) | BIT_QUEUEAC_Q5_V1_8822C(v))
+
+#define BIT_TIDEMPTY_Q5_V1_8822C BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q5_V2_8822C 11
+#define BIT_MASK_TAIL_PKT_Q5_V2_8822C 0x7ff
+#define BIT_TAIL_PKT_Q5_V2_8822C(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q5_V2_8822C) \
+ << BIT_SHIFT_TAIL_PKT_Q5_V2_8822C)
+#define BITS_TAIL_PKT_Q5_V2_8822C \
+ (BIT_MASK_TAIL_PKT_Q5_V2_8822C << BIT_SHIFT_TAIL_PKT_Q5_V2_8822C)
+#define BIT_CLEAR_TAIL_PKT_Q5_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q5_V2_8822C))
+#define BIT_GET_TAIL_PKT_Q5_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2_8822C) & \
+ BIT_MASK_TAIL_PKT_Q5_V2_8822C)
+#define BIT_SET_TAIL_PKT_Q5_V2_8822C(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q5_V2_8822C(x) | BIT_TAIL_PKT_Q5_V2_8822C(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q5_V1_8822C 0
+#define BIT_MASK_HEAD_PKT_Q5_V1_8822C 0x7ff
+#define BIT_HEAD_PKT_Q5_V1_8822C(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q5_V1_8822C) \
+ << BIT_SHIFT_HEAD_PKT_Q5_V1_8822C)
+#define BITS_HEAD_PKT_Q5_V1_8822C \
+ (BIT_MASK_HEAD_PKT_Q5_V1_8822C << BIT_SHIFT_HEAD_PKT_Q5_V1_8822C)
+#define BIT_CLEAR_HEAD_PKT_Q5_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q5_V1_8822C))
+#define BIT_GET_HEAD_PKT_Q5_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1_8822C) & \
+ BIT_MASK_HEAD_PKT_Q5_V1_8822C)
+#define BIT_SET_HEAD_PKT_Q5_V1_8822C(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q5_V1_8822C(x) | BIT_HEAD_PKT_Q5_V1_8822C(v))
+
+/* 2 REG_Q6_INFO_8822C */
+
+#define BIT_SHIFT_QUEUEMACID_Q6_V1_8822C 25
+#define BIT_MASK_QUEUEMACID_Q6_V1_8822C 0x7f
+#define BIT_QUEUEMACID_Q6_V1_8822C(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q6_V1_8822C) \
+ << BIT_SHIFT_QUEUEMACID_Q6_V1_8822C)
+#define BITS_QUEUEMACID_Q6_V1_8822C \
+ (BIT_MASK_QUEUEMACID_Q6_V1_8822C << BIT_SHIFT_QUEUEMACID_Q6_V1_8822C)
+#define BIT_CLEAR_QUEUEMACID_Q6_V1_8822C(x) \
+ ((x) & (~BITS_QUEUEMACID_Q6_V1_8822C))
+#define BIT_GET_QUEUEMACID_Q6_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1_8822C) & \
+ BIT_MASK_QUEUEMACID_Q6_V1_8822C)
+#define BIT_SET_QUEUEMACID_Q6_V1_8822C(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q6_V1_8822C(x) | BIT_QUEUEMACID_Q6_V1_8822C(v))
+
+#define BIT_SHIFT_QUEUEAC_Q6_V1_8822C 23
+#define BIT_MASK_QUEUEAC_Q6_V1_8822C 0x3
+#define BIT_QUEUEAC_Q6_V1_8822C(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q6_V1_8822C) << BIT_SHIFT_QUEUEAC_Q6_V1_8822C)
+#define BITS_QUEUEAC_Q6_V1_8822C \
+ (BIT_MASK_QUEUEAC_Q6_V1_8822C << BIT_SHIFT_QUEUEAC_Q6_V1_8822C)
+#define BIT_CLEAR_QUEUEAC_Q6_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q6_V1_8822C))
+#define BIT_GET_QUEUEAC_Q6_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q6_V1_8822C) & BIT_MASK_QUEUEAC_Q6_V1_8822C)
+#define BIT_SET_QUEUEAC_Q6_V1_8822C(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q6_V1_8822C(x) | BIT_QUEUEAC_Q6_V1_8822C(v))
+
+#define BIT_TIDEMPTY_Q6_V1_8822C BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q6_V2_8822C 11
+#define BIT_MASK_TAIL_PKT_Q6_V2_8822C 0x7ff
+#define BIT_TAIL_PKT_Q6_V2_8822C(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q6_V2_8822C) \
+ << BIT_SHIFT_TAIL_PKT_Q6_V2_8822C)
+#define BITS_TAIL_PKT_Q6_V2_8822C \
+ (BIT_MASK_TAIL_PKT_Q6_V2_8822C << BIT_SHIFT_TAIL_PKT_Q6_V2_8822C)
+#define BIT_CLEAR_TAIL_PKT_Q6_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q6_V2_8822C))
+#define BIT_GET_TAIL_PKT_Q6_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2_8822C) & \
+ BIT_MASK_TAIL_PKT_Q6_V2_8822C)
+#define BIT_SET_TAIL_PKT_Q6_V2_8822C(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q6_V2_8822C(x) | BIT_TAIL_PKT_Q6_V2_8822C(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q6_V1_8822C 0
+#define BIT_MASK_HEAD_PKT_Q6_V1_8822C 0x7ff
+#define BIT_HEAD_PKT_Q6_V1_8822C(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q6_V1_8822C) \
+ << BIT_SHIFT_HEAD_PKT_Q6_V1_8822C)
+#define BITS_HEAD_PKT_Q6_V1_8822C \
+ (BIT_MASK_HEAD_PKT_Q6_V1_8822C << BIT_SHIFT_HEAD_PKT_Q6_V1_8822C)
+#define BIT_CLEAR_HEAD_PKT_Q6_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q6_V1_8822C))
+#define BIT_GET_HEAD_PKT_Q6_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1_8822C) & \
+ BIT_MASK_HEAD_PKT_Q6_V1_8822C)
+#define BIT_SET_HEAD_PKT_Q6_V1_8822C(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q6_V1_8822C(x) | BIT_HEAD_PKT_Q6_V1_8822C(v))
+
+/* 2 REG_Q7_INFO_8822C */
+
+#define BIT_SHIFT_QUEUEMACID_Q7_V1_8822C 25
+#define BIT_MASK_QUEUEMACID_Q7_V1_8822C 0x7f
+#define BIT_QUEUEMACID_Q7_V1_8822C(x) \
+ (((x) & BIT_MASK_QUEUEMACID_Q7_V1_8822C) \
+ << BIT_SHIFT_QUEUEMACID_Q7_V1_8822C)
+#define BITS_QUEUEMACID_Q7_V1_8822C \
+ (BIT_MASK_QUEUEMACID_Q7_V1_8822C << BIT_SHIFT_QUEUEMACID_Q7_V1_8822C)
+#define BIT_CLEAR_QUEUEMACID_Q7_V1_8822C(x) \
+ ((x) & (~BITS_QUEUEMACID_Q7_V1_8822C))
+#define BIT_GET_QUEUEMACID_Q7_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1_8822C) & \
+ BIT_MASK_QUEUEMACID_Q7_V1_8822C)
+#define BIT_SET_QUEUEMACID_Q7_V1_8822C(x, v) \
+ (BIT_CLEAR_QUEUEMACID_Q7_V1_8822C(x) | BIT_QUEUEMACID_Q7_V1_8822C(v))
+
+#define BIT_SHIFT_QUEUEAC_Q7_V1_8822C 23
+#define BIT_MASK_QUEUEAC_Q7_V1_8822C 0x3
+#define BIT_QUEUEAC_Q7_V1_8822C(x) \
+ (((x) & BIT_MASK_QUEUEAC_Q7_V1_8822C) << BIT_SHIFT_QUEUEAC_Q7_V1_8822C)
+#define BITS_QUEUEAC_Q7_V1_8822C \
+ (BIT_MASK_QUEUEAC_Q7_V1_8822C << BIT_SHIFT_QUEUEAC_Q7_V1_8822C)
+#define BIT_CLEAR_QUEUEAC_Q7_V1_8822C(x) ((x) & (~BITS_QUEUEAC_Q7_V1_8822C))
+#define BIT_GET_QUEUEAC_Q7_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_QUEUEAC_Q7_V1_8822C) & BIT_MASK_QUEUEAC_Q7_V1_8822C)
+#define BIT_SET_QUEUEAC_Q7_V1_8822C(x, v) \
+ (BIT_CLEAR_QUEUEAC_Q7_V1_8822C(x) | BIT_QUEUEAC_Q7_V1_8822C(v))
+
+#define BIT_TIDEMPTY_Q7_V1_8822C BIT(22)
+
+#define BIT_SHIFT_TAIL_PKT_Q7_V2_8822C 11
+#define BIT_MASK_TAIL_PKT_Q7_V2_8822C 0x7ff
+#define BIT_TAIL_PKT_Q7_V2_8822C(x) \
+ (((x) & BIT_MASK_TAIL_PKT_Q7_V2_8822C) \
+ << BIT_SHIFT_TAIL_PKT_Q7_V2_8822C)
+#define BITS_TAIL_PKT_Q7_V2_8822C \
+ (BIT_MASK_TAIL_PKT_Q7_V2_8822C << BIT_SHIFT_TAIL_PKT_Q7_V2_8822C)
+#define BIT_CLEAR_TAIL_PKT_Q7_V2_8822C(x) ((x) & (~BITS_TAIL_PKT_Q7_V2_8822C))
+#define BIT_GET_TAIL_PKT_Q7_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2_8822C) & \
+ BIT_MASK_TAIL_PKT_Q7_V2_8822C)
+#define BIT_SET_TAIL_PKT_Q7_V2_8822C(x, v) \
+ (BIT_CLEAR_TAIL_PKT_Q7_V2_8822C(x) | BIT_TAIL_PKT_Q7_V2_8822C(v))
+
+#define BIT_SHIFT_HEAD_PKT_Q7_V1_8822C 0
+#define BIT_MASK_HEAD_PKT_Q7_V1_8822C 0x7ff
+#define BIT_HEAD_PKT_Q7_V1_8822C(x) \
+ (((x) & BIT_MASK_HEAD_PKT_Q7_V1_8822C) \
+ << BIT_SHIFT_HEAD_PKT_Q7_V1_8822C)
+#define BITS_HEAD_PKT_Q7_V1_8822C \
+ (BIT_MASK_HEAD_PKT_Q7_V1_8822C << BIT_SHIFT_HEAD_PKT_Q7_V1_8822C)
+#define BIT_CLEAR_HEAD_PKT_Q7_V1_8822C(x) ((x) & (~BITS_HEAD_PKT_Q7_V1_8822C))
+#define BIT_GET_HEAD_PKT_Q7_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1_8822C) & \
+ BIT_MASK_HEAD_PKT_Q7_V1_8822C)
+#define BIT_SET_HEAD_PKT_Q7_V1_8822C(x, v) \
+ (BIT_CLEAR_HEAD_PKT_Q7_V1_8822C(x) | BIT_HEAD_PKT_Q7_V1_8822C(v))
+
+/* 2 REG_WMAC_LBK_BUF_HD_V1_8822C */
+
+#define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822C 0
+#define BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822C 0xfff
+#define BIT_WMAC_LBK_BUF_HEAD_V1_8822C(x) \
+ (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822C) \
+ << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822C)
+#define BITS_WMAC_LBK_BUF_HEAD_V1_8822C \
+ (BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822C \
+ << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822C)
+#define BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8822C(x) \
+ ((x) & (~BITS_WMAC_LBK_BUF_HEAD_V1_8822C))
+#define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8822C) & \
+ BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8822C)
+#define BIT_SET_WMAC_LBK_BUF_HEAD_V1_8822C(x, v) \
+ (BIT_CLEAR_WMAC_LBK_BUF_HEAD_V1_8822C(x) | \
+ BIT_WMAC_LBK_BUF_HEAD_V1_8822C(v))
+
+/* 2 REG_MGQ_BDNY_V1_8822C */
+
+#define BIT_SHIFT_MGQ_PGBNDY_V1_8822C 0
+#define BIT_MASK_MGQ_PGBNDY_V1_8822C 0xfff
+#define BIT_MGQ_PGBNDY_V1_8822C(x) \
+ (((x) & BIT_MASK_MGQ_PGBNDY_V1_8822C) << BIT_SHIFT_MGQ_PGBNDY_V1_8822C)
+#define BITS_MGQ_PGBNDY_V1_8822C \
+ (BIT_MASK_MGQ_PGBNDY_V1_8822C << BIT_SHIFT_MGQ_PGBNDY_V1_8822C)
+#define BIT_CLEAR_MGQ_PGBNDY_V1_8822C(x) ((x) & (~BITS_MGQ_PGBNDY_V1_8822C))
+#define BIT_GET_MGQ_PGBNDY_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8822C) & BIT_MASK_MGQ_PGBNDY_V1_8822C)
+#define BIT_SET_MGQ_PGBNDY_V1_8822C(x, v) \
+ (BIT_CLEAR_MGQ_PGBNDY_V1_8822C(x) | BIT_MGQ_PGBNDY_V1_8822C(v))
+
+/* 2 REG_TXRPT_CTRL_8822C */
+
+#define BIT_SHIFT_TRXRPT_TIMER_TH_8822C 24
+#define BIT_MASK_TRXRPT_TIMER_TH_8822C 0xff
+#define BIT_TRXRPT_TIMER_TH_8822C(x) \
+ (((x) & BIT_MASK_TRXRPT_TIMER_TH_8822C) \
+ << BIT_SHIFT_TRXRPT_TIMER_TH_8822C)
+#define BITS_TRXRPT_TIMER_TH_8822C \
+ (BIT_MASK_TRXRPT_TIMER_TH_8822C << BIT_SHIFT_TRXRPT_TIMER_TH_8822C)
+#define BIT_CLEAR_TRXRPT_TIMER_TH_8822C(x) ((x) & (~BITS_TRXRPT_TIMER_TH_8822C))
+#define BIT_GET_TRXRPT_TIMER_TH_8822C(x) \
+ (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8822C) & \
+ BIT_MASK_TRXRPT_TIMER_TH_8822C)
+#define BIT_SET_TRXRPT_TIMER_TH_8822C(x, v) \
+ (BIT_CLEAR_TRXRPT_TIMER_TH_8822C(x) | BIT_TRXRPT_TIMER_TH_8822C(v))
+
+#define BIT_SHIFT_TRXRPT_LEN_TH_8822C 16
+#define BIT_MASK_TRXRPT_LEN_TH_8822C 0xff
+#define BIT_TRXRPT_LEN_TH_8822C(x) \
+ (((x) & BIT_MASK_TRXRPT_LEN_TH_8822C) << BIT_SHIFT_TRXRPT_LEN_TH_8822C)
+#define BITS_TRXRPT_LEN_TH_8822C \
+ (BIT_MASK_TRXRPT_LEN_TH_8822C << BIT_SHIFT_TRXRPT_LEN_TH_8822C)
+#define BIT_CLEAR_TRXRPT_LEN_TH_8822C(x) ((x) & (~BITS_TRXRPT_LEN_TH_8822C))
+#define BIT_GET_TRXRPT_LEN_TH_8822C(x) \
+ (((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8822C) & BIT_MASK_TRXRPT_LEN_TH_8822C)
+#define BIT_SET_TRXRPT_LEN_TH_8822C(x, v) \
+ (BIT_CLEAR_TRXRPT_LEN_TH_8822C(x) | BIT_TRXRPT_LEN_TH_8822C(v))
+
+#define BIT_SHIFT_TRXRPT_READ_PTR_8822C 8
+#define BIT_MASK_TRXRPT_READ_PTR_8822C 0xff
+#define BIT_TRXRPT_READ_PTR_8822C(x) \
+ (((x) & BIT_MASK_TRXRPT_READ_PTR_8822C) \
+ << BIT_SHIFT_TRXRPT_READ_PTR_8822C)
+#define BITS_TRXRPT_READ_PTR_8822C \
+ (BIT_MASK_TRXRPT_READ_PTR_8822C << BIT_SHIFT_TRXRPT_READ_PTR_8822C)
+#define BIT_CLEAR_TRXRPT_READ_PTR_8822C(x) ((x) & (~BITS_TRXRPT_READ_PTR_8822C))
+#define BIT_GET_TRXRPT_READ_PTR_8822C(x) \
+ (((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8822C) & \
+ BIT_MASK_TRXRPT_READ_PTR_8822C)
+#define BIT_SET_TRXRPT_READ_PTR_8822C(x, v) \
+ (BIT_CLEAR_TRXRPT_READ_PTR_8822C(x) | BIT_TRXRPT_READ_PTR_8822C(v))
+
+#define BIT_SHIFT_TRXRPT_WRITE_PTR_8822C 0
+#define BIT_MASK_TRXRPT_WRITE_PTR_8822C 0xff
+#define BIT_TRXRPT_WRITE_PTR_8822C(x) \
+ (((x) & BIT_MASK_TRXRPT_WRITE_PTR_8822C) \
+ << BIT_SHIFT_TRXRPT_WRITE_PTR_8822C)
+#define BITS_TRXRPT_WRITE_PTR_8822C \
+ (BIT_MASK_TRXRPT_WRITE_PTR_8822C << BIT_SHIFT_TRXRPT_WRITE_PTR_8822C)
+#define BIT_CLEAR_TRXRPT_WRITE_PTR_8822C(x) \
+ ((x) & (~BITS_TRXRPT_WRITE_PTR_8822C))
+#define BIT_GET_TRXRPT_WRITE_PTR_8822C(x) \
+ (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8822C) & \
+ BIT_MASK_TRXRPT_WRITE_PTR_8822C)
+#define BIT_SET_TRXRPT_WRITE_PTR_8822C(x, v) \
+ (BIT_CLEAR_TRXRPT_WRITE_PTR_8822C(x) | BIT_TRXRPT_WRITE_PTR_8822C(v))
+
+/* 2 REG_INIRTS_RATE_SEL_8822C */
+#define BIT_LEAG_RTS_BW_DUP_8822C BIT(5)
+
+/* 2 REG_BASIC_CFEND_RATE_8822C */
+
+#define BIT_SHIFT_BASIC_CFEND_RATE_8822C 0
+#define BIT_MASK_BASIC_CFEND_RATE_8822C 0x1f
+#define BIT_BASIC_CFEND_RATE_8822C(x) \
+ (((x) & BIT_MASK_BASIC_CFEND_RATE_8822C) \
+ << BIT_SHIFT_BASIC_CFEND_RATE_8822C)
+#define BITS_BASIC_CFEND_RATE_8822C \
+ (BIT_MASK_BASIC_CFEND_RATE_8822C << BIT_SHIFT_BASIC_CFEND_RATE_8822C)
+#define BIT_CLEAR_BASIC_CFEND_RATE_8822C(x) \
+ ((x) & (~BITS_BASIC_CFEND_RATE_8822C))
+#define BIT_GET_BASIC_CFEND_RATE_8822C(x) \
+ (((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8822C) & \
+ BIT_MASK_BASIC_CFEND_RATE_8822C)
+#define BIT_SET_BASIC_CFEND_RATE_8822C(x, v) \
+ (BIT_CLEAR_BASIC_CFEND_RATE_8822C(x) | BIT_BASIC_CFEND_RATE_8822C(v))
+
+/* 2 REG_STBC_CFEND_RATE_8822C */
+
+#define BIT_SHIFT_STBC_CFEND_RATE_8822C 0
+#define BIT_MASK_STBC_CFEND_RATE_8822C 0x1f
+#define BIT_STBC_CFEND_RATE_8822C(x) \
+ (((x) & BIT_MASK_STBC_CFEND_RATE_8822C) \
+ << BIT_SHIFT_STBC_CFEND_RATE_8822C)
+#define BITS_STBC_CFEND_RATE_8822C \
+ (BIT_MASK_STBC_CFEND_RATE_8822C << BIT_SHIFT_STBC_CFEND_RATE_8822C)
+#define BIT_CLEAR_STBC_CFEND_RATE_8822C(x) ((x) & (~BITS_STBC_CFEND_RATE_8822C))
+#define BIT_GET_STBC_CFEND_RATE_8822C(x) \
+ (((x) >> BIT_SHIFT_STBC_CFEND_RATE_8822C) & \
+ BIT_MASK_STBC_CFEND_RATE_8822C)
+#define BIT_SET_STBC_CFEND_RATE_8822C(x, v) \
+ (BIT_CLEAR_STBC_CFEND_RATE_8822C(x) | BIT_STBC_CFEND_RATE_8822C(v))
+
+/* 2 REG_DATA_SC_8822C */
+
+#define BIT_SHIFT_TXSC_40M_8822C 4
+#define BIT_MASK_TXSC_40M_8822C 0xf
+#define BIT_TXSC_40M_8822C(x) \
+ (((x) & BIT_MASK_TXSC_40M_8822C) << BIT_SHIFT_TXSC_40M_8822C)
+#define BITS_TXSC_40M_8822C \
+ (BIT_MASK_TXSC_40M_8822C << BIT_SHIFT_TXSC_40M_8822C)
+#define BIT_CLEAR_TXSC_40M_8822C(x) ((x) & (~BITS_TXSC_40M_8822C))
+#define BIT_GET_TXSC_40M_8822C(x) \
+ (((x) >> BIT_SHIFT_TXSC_40M_8822C) & BIT_MASK_TXSC_40M_8822C)
+#define BIT_SET_TXSC_40M_8822C(x, v) \
+ (BIT_CLEAR_TXSC_40M_8822C(x) | BIT_TXSC_40M_8822C(v))
+
+#define BIT_SHIFT_TXSC_20M_8822C 0
+#define BIT_MASK_TXSC_20M_8822C 0xf
+#define BIT_TXSC_20M_8822C(x) \
+ (((x) & BIT_MASK_TXSC_20M_8822C) << BIT_SHIFT_TXSC_20M_8822C)
+#define BITS_TXSC_20M_8822C \
+ (BIT_MASK_TXSC_20M_8822C << BIT_SHIFT_TXSC_20M_8822C)
+#define BIT_CLEAR_TXSC_20M_8822C(x) ((x) & (~BITS_TXSC_20M_8822C))
+#define BIT_GET_TXSC_20M_8822C(x) \
+ (((x) >> BIT_SHIFT_TXSC_20M_8822C) & BIT_MASK_TXSC_20M_8822C)
+#define BIT_SET_TXSC_20M_8822C(x, v) \
+ (BIT_CLEAR_TXSC_20M_8822C(x) | BIT_TXSC_20M_8822C(v))
+
+/* 2 REG_MACID_SLEEP3_8822C */
+
+#define BIT_SHIFT_MACID127_96_PKTSLEEP_8822C 0
+#define BIT_MASK_MACID127_96_PKTSLEEP_8822C 0xffffffffL
+#define BIT_MACID127_96_PKTSLEEP_8822C(x) \
+ (((x) & BIT_MASK_MACID127_96_PKTSLEEP_8822C) \
+ << BIT_SHIFT_MACID127_96_PKTSLEEP_8822C)
+#define BITS_MACID127_96_PKTSLEEP_8822C \
+ (BIT_MASK_MACID127_96_PKTSLEEP_8822C \
+ << BIT_SHIFT_MACID127_96_PKTSLEEP_8822C)
+#define BIT_CLEAR_MACID127_96_PKTSLEEP_8822C(x) \
+ ((x) & (~BITS_MACID127_96_PKTSLEEP_8822C))
+#define BIT_GET_MACID127_96_PKTSLEEP_8822C(x) \
+ (((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP_8822C) & \
+ BIT_MASK_MACID127_96_PKTSLEEP_8822C)
+#define BIT_SET_MACID127_96_PKTSLEEP_8822C(x, v) \
+ (BIT_CLEAR_MACID127_96_PKTSLEEP_8822C(x) | \
+ BIT_MACID127_96_PKTSLEEP_8822C(v))
+
+/* 2 REG_MACID_SLEEP1_8822C */
+
+#define BIT_SHIFT_MACID63_32_PKTSLEEP_8822C 0
+#define BIT_MASK_MACID63_32_PKTSLEEP_8822C 0xffffffffL
+#define BIT_MACID63_32_PKTSLEEP_8822C(x) \
+ (((x) & BIT_MASK_MACID63_32_PKTSLEEP_8822C) \
+ << BIT_SHIFT_MACID63_32_PKTSLEEP_8822C)
+#define BITS_MACID63_32_PKTSLEEP_8822C \
+ (BIT_MASK_MACID63_32_PKTSLEEP_8822C \
+ << BIT_SHIFT_MACID63_32_PKTSLEEP_8822C)
+#define BIT_CLEAR_MACID63_32_PKTSLEEP_8822C(x) \
+ ((x) & (~BITS_MACID63_32_PKTSLEEP_8822C))
+#define BIT_GET_MACID63_32_PKTSLEEP_8822C(x) \
+ (((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP_8822C) & \
+ BIT_MASK_MACID63_32_PKTSLEEP_8822C)
+#define BIT_SET_MACID63_32_PKTSLEEP_8822C(x, v) \
+ (BIT_CLEAR_MACID63_32_PKTSLEEP_8822C(x) | \
+ BIT_MACID63_32_PKTSLEEP_8822C(v))
+
+/* 2 REG_ARFR2_V1_8822C */
+
+#define BIT_SHIFT_ARFRL2_8822C 0
+#define BIT_MASK_ARFRL2_8822C 0xffffffffL
+#define BIT_ARFRL2_8822C(x) \
+ (((x) & BIT_MASK_ARFRL2_8822C) << BIT_SHIFT_ARFRL2_8822C)
+#define BITS_ARFRL2_8822C (BIT_MASK_ARFRL2_8822C << BIT_SHIFT_ARFRL2_8822C)
+#define BIT_CLEAR_ARFRL2_8822C(x) ((x) & (~BITS_ARFRL2_8822C))
+#define BIT_GET_ARFRL2_8822C(x) \
+ (((x) >> BIT_SHIFT_ARFRL2_8822C) & BIT_MASK_ARFRL2_8822C)
+#define BIT_SET_ARFRL2_8822C(x, v) \
+ (BIT_CLEAR_ARFRL2_8822C(x) | BIT_ARFRL2_8822C(v))
+
+/* 2 REG_ARFRH2_V1_8822C */
+
+#define BIT_SHIFT_ARFRH2_8822C 0
+#define BIT_MASK_ARFRH2_8822C 0xffffffffL
+#define BIT_ARFRH2_8822C(x) \
+ (((x) & BIT_MASK_ARFRH2_8822C) << BIT_SHIFT_ARFRH2_8822C)
+#define BITS_ARFRH2_8822C (BIT_MASK_ARFRH2_8822C << BIT_SHIFT_ARFRH2_8822C)
+#define BIT_CLEAR_ARFRH2_8822C(x) ((x) & (~BITS_ARFRH2_8822C))
+#define BIT_GET_ARFRH2_8822C(x) \
+ (((x) >> BIT_SHIFT_ARFRH2_8822C) & BIT_MASK_ARFRH2_8822C)
+#define BIT_SET_ARFRH2_8822C(x, v) \
+ (BIT_CLEAR_ARFRH2_8822C(x) | BIT_ARFRH2_8822C(v))
+
+/* 2 REG_ARFR3_V1_8822C */
+
+#define BIT_SHIFT_ARFRL3_8822C 0
+#define BIT_MASK_ARFRL3_8822C 0xffffffffL
+#define BIT_ARFRL3_8822C(x) \
+ (((x) & BIT_MASK_ARFRL3_8822C) << BIT_SHIFT_ARFRL3_8822C)
+#define BITS_ARFRL3_8822C (BIT_MASK_ARFRL3_8822C << BIT_SHIFT_ARFRL3_8822C)
+#define BIT_CLEAR_ARFRL3_8822C(x) ((x) & (~BITS_ARFRL3_8822C))
+#define BIT_GET_ARFRL3_8822C(x) \
+ (((x) >> BIT_SHIFT_ARFRL3_8822C) & BIT_MASK_ARFRL3_8822C)
+#define BIT_SET_ARFRL3_8822C(x, v) \
+ (BIT_CLEAR_ARFRL3_8822C(x) | BIT_ARFRL3_8822C(v))
+
+/* 2 REG_ARFRH3_V1_8822C */
+
+#define BIT_SHIFT_ARFRH3_8822C 0
+#define BIT_MASK_ARFRH3_8822C 0xffffffffL
+#define BIT_ARFRH3_8822C(x) \
+ (((x) & BIT_MASK_ARFRH3_8822C) << BIT_SHIFT_ARFRH3_8822C)
+#define BITS_ARFRH3_8822C (BIT_MASK_ARFRH3_8822C << BIT_SHIFT_ARFRH3_8822C)
+#define BIT_CLEAR_ARFRH3_8822C(x) ((x) & (~BITS_ARFRH3_8822C))
+#define BIT_GET_ARFRH3_8822C(x) \
+ (((x) >> BIT_SHIFT_ARFRH3_8822C) & BIT_MASK_ARFRH3_8822C)
+#define BIT_SET_ARFRH3_8822C(x, v) \
+ (BIT_CLEAR_ARFRH3_8822C(x) | BIT_ARFRH3_8822C(v))
+
+/* 2 REG_ARFR4_8822C */
+
+#define BIT_SHIFT_ARFRL4_8822C 0
+#define BIT_MASK_ARFRL4_8822C 0xffffffffL
+#define BIT_ARFRL4_8822C(x) \
+ (((x) & BIT_MASK_ARFRL4_8822C) << BIT_SHIFT_ARFRL4_8822C)
+#define BITS_ARFRL4_8822C (BIT_MASK_ARFRL4_8822C << BIT_SHIFT_ARFRL4_8822C)
+#define BIT_CLEAR_ARFRL4_8822C(x) ((x) & (~BITS_ARFRL4_8822C))
+#define BIT_GET_ARFRL4_8822C(x) \
+ (((x) >> BIT_SHIFT_ARFRL4_8822C) & BIT_MASK_ARFRL4_8822C)
+#define BIT_SET_ARFRL4_8822C(x, v) \
+ (BIT_CLEAR_ARFRL4_8822C(x) | BIT_ARFRL4_8822C(v))
+
+/* 2 REG_ARFRH4_8822C */
+
+#define BIT_SHIFT_ARFRH4_8822C 0
+#define BIT_MASK_ARFRH4_8822C 0xffffffffL
+#define BIT_ARFRH4_8822C(x) \
+ (((x) & BIT_MASK_ARFRH4_8822C) << BIT_SHIFT_ARFRH4_8822C)
+#define BITS_ARFRH4_8822C (BIT_MASK_ARFRH4_8822C << BIT_SHIFT_ARFRH4_8822C)
+#define BIT_CLEAR_ARFRH4_8822C(x) ((x) & (~BITS_ARFRH4_8822C))
+#define BIT_GET_ARFRH4_8822C(x) \
+ (((x) >> BIT_SHIFT_ARFRH4_8822C) & BIT_MASK_ARFRH4_8822C)
+#define BIT_SET_ARFRH4_8822C(x, v) \
+ (BIT_CLEAR_ARFRH4_8822C(x) | BIT_ARFRH4_8822C(v))
+
+/* 2 REG_ARFR5_8822C */
+
+#define BIT_SHIFT_ARFRL5_8822C 0
+#define BIT_MASK_ARFRL5_8822C 0xffffffffL
+#define BIT_ARFRL5_8822C(x) \
+ (((x) & BIT_MASK_ARFRL5_8822C) << BIT_SHIFT_ARFRL5_8822C)
+#define BITS_ARFRL5_8822C (BIT_MASK_ARFRL5_8822C << BIT_SHIFT_ARFRL5_8822C)
+#define BIT_CLEAR_ARFRL5_8822C(x) ((x) & (~BITS_ARFRL5_8822C))
+#define BIT_GET_ARFRL5_8822C(x) \
+ (((x) >> BIT_SHIFT_ARFRL5_8822C) & BIT_MASK_ARFRL5_8822C)
+#define BIT_SET_ARFRL5_8822C(x, v) \
+ (BIT_CLEAR_ARFRL5_8822C(x) | BIT_ARFRL5_8822C(v))
+
+/* 2 REG_ARFRH5_8822C */
+
+#define BIT_SHIFT_ARFRH5_8822C 0
+#define BIT_MASK_ARFRH5_8822C 0xffffffffL
+#define BIT_ARFRH5_8822C(x) \
+ (((x) & BIT_MASK_ARFRH5_8822C) << BIT_SHIFT_ARFRH5_8822C)
+#define BITS_ARFRH5_8822C (BIT_MASK_ARFRH5_8822C << BIT_SHIFT_ARFRH5_8822C)
+#define BIT_CLEAR_ARFRH5_8822C(x) ((x) & (~BITS_ARFRH5_8822C))
+#define BIT_GET_ARFRH5_8822C(x) \
+ (((x) >> BIT_SHIFT_ARFRH5_8822C) & BIT_MASK_ARFRH5_8822C)
+#define BIT_SET_ARFRH5_8822C(x, v) \
+ (BIT_CLEAR_ARFRH5_8822C(x) | BIT_ARFRH5_8822C(v))
+
+/* 2 REG_TXRPT_START_OFFSET_8822C */
+
+#define BIT_SHIFT_MACID_MURATE_OFFSET_8822C 24
+#define BIT_MASK_MACID_MURATE_OFFSET_8822C 0xff
+#define BIT_MACID_MURATE_OFFSET_8822C(x) \
+ (((x) & BIT_MASK_MACID_MURATE_OFFSET_8822C) \
+ << BIT_SHIFT_MACID_MURATE_OFFSET_8822C)
+#define BITS_MACID_MURATE_OFFSET_8822C \
+ (BIT_MASK_MACID_MURATE_OFFSET_8822C \
+ << BIT_SHIFT_MACID_MURATE_OFFSET_8822C)
+#define BIT_CLEAR_MACID_MURATE_OFFSET_8822C(x) \
+ ((x) & (~BITS_MACID_MURATE_OFFSET_8822C))
+#define BIT_GET_MACID_MURATE_OFFSET_8822C(x) \
+ (((x) >> BIT_SHIFT_MACID_MURATE_OFFSET_8822C) & \
+ BIT_MASK_MACID_MURATE_OFFSET_8822C)
+#define BIT_SET_MACID_MURATE_OFFSET_8822C(x, v) \
+ (BIT_CLEAR_MACID_MURATE_OFFSET_8822C(x) | \
+ BIT_MACID_MURATE_OFFSET_8822C(v))
+
+#define BIT_SHIFT_TXRPT_MISS_COUNT_8822C 17
+#define BIT_MASK_TXRPT_MISS_COUNT_8822C 0x7
+#define BIT_TXRPT_MISS_COUNT_8822C(x) \
+ (((x) & BIT_MASK_TXRPT_MISS_COUNT_8822C) \
+ << BIT_SHIFT_TXRPT_MISS_COUNT_8822C)
+#define BITS_TXRPT_MISS_COUNT_8822C \
+ (BIT_MASK_TXRPT_MISS_COUNT_8822C << BIT_SHIFT_TXRPT_MISS_COUNT_8822C)
+#define BIT_CLEAR_TXRPT_MISS_COUNT_8822C(x) \
+ ((x) & (~BITS_TXRPT_MISS_COUNT_8822C))
+#define BIT_GET_TXRPT_MISS_COUNT_8822C(x) \
+ (((x) >> BIT_SHIFT_TXRPT_MISS_COUNT_8822C) & \
+ BIT_MASK_TXRPT_MISS_COUNT_8822C)
+#define BIT_SET_TXRPT_MISS_COUNT_8822C(x, v) \
+ (BIT_CLEAR_TXRPT_MISS_COUNT_8822C(x) | BIT_TXRPT_MISS_COUNT_8822C(v))
+
+#define BIT_RPTFIFO_SIZE_OPT_8822C BIT(16)
+
+#define BIT_SHIFT_MACID_CTRL_OFFSET_8822C 8
+#define BIT_MASK_MACID_CTRL_OFFSET_8822C 0xff
+#define BIT_MACID_CTRL_OFFSET_8822C(x) \
+ (((x) & BIT_MASK_MACID_CTRL_OFFSET_8822C) \
+ << BIT_SHIFT_MACID_CTRL_OFFSET_8822C)
+#define BITS_MACID_CTRL_OFFSET_8822C \
+ (BIT_MASK_MACID_CTRL_OFFSET_8822C << BIT_SHIFT_MACID_CTRL_OFFSET_8822C)
+#define BIT_CLEAR_MACID_CTRL_OFFSET_8822C(x) \
+ ((x) & (~BITS_MACID_CTRL_OFFSET_8822C))
+#define BIT_GET_MACID_CTRL_OFFSET_8822C(x) \
+ (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_8822C) & \
+ BIT_MASK_MACID_CTRL_OFFSET_8822C)
+#define BIT_SET_MACID_CTRL_OFFSET_8822C(x, v) \
+ (BIT_CLEAR_MACID_CTRL_OFFSET_8822C(x) | BIT_MACID_CTRL_OFFSET_8822C(v))
+
+#define BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822C 0
+#define BIT_MASK_AMPDU_TXRPT_OFFSET_8822C 0xff
+#define BIT_AMPDU_TXRPT_OFFSET_8822C(x) \
+ (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_8822C) \
+ << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822C)
+#define BITS_AMPDU_TXRPT_OFFSET_8822C \
+ (BIT_MASK_AMPDU_TXRPT_OFFSET_8822C \
+ << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822C)
+#define BIT_CLEAR_AMPDU_TXRPT_OFFSET_8822C(x) \
+ ((x) & (~BITS_AMPDU_TXRPT_OFFSET_8822C))
+#define BIT_GET_AMPDU_TXRPT_OFFSET_8822C(x) \
+ (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_8822C) & \
+ BIT_MASK_AMPDU_TXRPT_OFFSET_8822C)
+#define BIT_SET_AMPDU_TXRPT_OFFSET_8822C(x, v) \
+ (BIT_CLEAR_AMPDU_TXRPT_OFFSET_8822C(x) | \
+ BIT_AMPDU_TXRPT_OFFSET_8822C(v))
+
+/* 2 REG_POWER_STAGE1_8822C */
+#define BIT_PTA_WL_PRI_MASK_CPU_MGQ_8822C BIT(31)
+#define BIT_PTA_WL_PRI_MASK_BCNQ_8822C BIT(30)
+#define BIT_PTA_WL_PRI_MASK_HIQ_8822C BIT(29)
+#define BIT_PTA_WL_PRI_MASK_MGQ_8822C BIT(28)
+#define BIT_PTA_WL_PRI_MASK_BK_8822C BIT(27)
+#define BIT_PTA_WL_PRI_MASK_BE_8822C BIT(26)
+#define BIT_PTA_WL_PRI_MASK_VI_8822C BIT(25)
+#define BIT_PTA_WL_PRI_MASK_VO_8822C BIT(24)
+
+#define BIT_SHIFT_POWER_STAGE1_8822C 0
+#define BIT_MASK_POWER_STAGE1_8822C 0xffffff
+#define BIT_POWER_STAGE1_8822C(x) \
+ (((x) & BIT_MASK_POWER_STAGE1_8822C) << BIT_SHIFT_POWER_STAGE1_8822C)
+#define BITS_POWER_STAGE1_8822C \
+ (BIT_MASK_POWER_STAGE1_8822C << BIT_SHIFT_POWER_STAGE1_8822C)
+#define BIT_CLEAR_POWER_STAGE1_8822C(x) ((x) & (~BITS_POWER_STAGE1_8822C))
+#define BIT_GET_POWER_STAGE1_8822C(x) \
+ (((x) >> BIT_SHIFT_POWER_STAGE1_8822C) & BIT_MASK_POWER_STAGE1_8822C)
+#define BIT_SET_POWER_STAGE1_8822C(x, v) \
+ (BIT_CLEAR_POWER_STAGE1_8822C(x) | BIT_POWER_STAGE1_8822C(v))
+
+/* 2 REG_POWER_STAGE2_8822C */
+#define BIT__R_CTRL_PKT_POW_ADJ_8822C BIT(24)
+
+#define BIT_SHIFT_POWER_STAGE2_8822C 0
+#define BIT_MASK_POWER_STAGE2_8822C 0xffffff
+#define BIT_POWER_STAGE2_8822C(x) \
+ (((x) & BIT_MASK_POWER_STAGE2_8822C) << BIT_SHIFT_POWER_STAGE2_8822C)
+#define BITS_POWER_STAGE2_8822C \
+ (BIT_MASK_POWER_STAGE2_8822C << BIT_SHIFT_POWER_STAGE2_8822C)
+#define BIT_CLEAR_POWER_STAGE2_8822C(x) ((x) & (~BITS_POWER_STAGE2_8822C))
+#define BIT_GET_POWER_STAGE2_8822C(x) \
+ (((x) >> BIT_SHIFT_POWER_STAGE2_8822C) & BIT_MASK_POWER_STAGE2_8822C)
+#define BIT_SET_POWER_STAGE2_8822C(x, v) \
+ (BIT_CLEAR_POWER_STAGE2_8822C(x) | BIT_POWER_STAGE2_8822C(v))
+
+/* 2 REG_SW_AMPDU_BURST_MODE_CTRL_8822C */
+
+#define BIT_SHIFT_PAD_NUM_THRES_8822C 24
+#define BIT_MASK_PAD_NUM_THRES_8822C 0x3f
+#define BIT_PAD_NUM_THRES_8822C(x) \
+ (((x) & BIT_MASK_PAD_NUM_THRES_8822C) << BIT_SHIFT_PAD_NUM_THRES_8822C)
+#define BITS_PAD_NUM_THRES_8822C \
+ (BIT_MASK_PAD_NUM_THRES_8822C << BIT_SHIFT_PAD_NUM_THRES_8822C)
+#define BIT_CLEAR_PAD_NUM_THRES_8822C(x) ((x) & (~BITS_PAD_NUM_THRES_8822C))
+#define BIT_GET_PAD_NUM_THRES_8822C(x) \
+ (((x) >> BIT_SHIFT_PAD_NUM_THRES_8822C) & BIT_MASK_PAD_NUM_THRES_8822C)
+#define BIT_SET_PAD_NUM_THRES_8822C(x, v) \
+ (BIT_CLEAR_PAD_NUM_THRES_8822C(x) | BIT_PAD_NUM_THRES_8822C(v))
+
+#define BIT_R_DMA_THIS_QUEUE_BK_8822C BIT(23)
+#define BIT_R_DMA_THIS_QUEUE_BE_8822C BIT(22)
+#define BIT_R_DMA_THIS_QUEUE_VI_8822C BIT(21)
+#define BIT_R_DMA_THIS_QUEUE_VO_8822C BIT(20)
+
+#define BIT_SHIFT_R_TOTAL_LEN_TH_8822C 8
+#define BIT_MASK_R_TOTAL_LEN_TH_8822C 0xfff
+#define BIT_R_TOTAL_LEN_TH_8822C(x) \
+ (((x) & BIT_MASK_R_TOTAL_LEN_TH_8822C) \
+ << BIT_SHIFT_R_TOTAL_LEN_TH_8822C)
+#define BITS_R_TOTAL_LEN_TH_8822C \
+ (BIT_MASK_R_TOTAL_LEN_TH_8822C << BIT_SHIFT_R_TOTAL_LEN_TH_8822C)
+#define BIT_CLEAR_R_TOTAL_LEN_TH_8822C(x) ((x) & (~BITS_R_TOTAL_LEN_TH_8822C))
+#define BIT_GET_R_TOTAL_LEN_TH_8822C(x) \
+ (((x) >> BIT_SHIFT_R_TOTAL_LEN_TH_8822C) & \
+ BIT_MASK_R_TOTAL_LEN_TH_8822C)
+#define BIT_SET_R_TOTAL_LEN_TH_8822C(x, v) \
+ (BIT_CLEAR_R_TOTAL_LEN_TH_8822C(x) | BIT_R_TOTAL_LEN_TH_8822C(v))
+
+#define BIT_EN_NEW_EARLY_8822C BIT(7)
+#define BIT_PRE_TX_CMD_8822C BIT(6)
+
+#define BIT_SHIFT_NUM_SCL_EN_8822C 4
+#define BIT_MASK_NUM_SCL_EN_8822C 0x3
+#define BIT_NUM_SCL_EN_8822C(x) \
+ (((x) & BIT_MASK_NUM_SCL_EN_8822C) << BIT_SHIFT_NUM_SCL_EN_8822C)
+#define BITS_NUM_SCL_EN_8822C \
+ (BIT_MASK_NUM_SCL_EN_8822C << BIT_SHIFT_NUM_SCL_EN_8822C)
+#define BIT_CLEAR_NUM_SCL_EN_8822C(x) ((x) & (~BITS_NUM_SCL_EN_8822C))
+#define BIT_GET_NUM_SCL_EN_8822C(x) \
+ (((x) >> BIT_SHIFT_NUM_SCL_EN_8822C) & BIT_MASK_NUM_SCL_EN_8822C)
+#define BIT_SET_NUM_SCL_EN_8822C(x, v) \
+ (BIT_CLEAR_NUM_SCL_EN_8822C(x) | BIT_NUM_SCL_EN_8822C(v))
+
+#define BIT_BK_EN_8822C BIT(3)
+#define BIT_BE_EN_8822C BIT(2)
+#define BIT_VI_EN_8822C BIT(1)
+#define BIT_VO_EN_8822C BIT(0)
+
+/* 2 REG_PKT_LIFE_TIME_8822C */
+
+#define BIT_SHIFT_PKT_LIFTIME_BEBK_8822C 16
+#define BIT_MASK_PKT_LIFTIME_BEBK_8822C 0xffff
+#define BIT_PKT_LIFTIME_BEBK_8822C(x) \
+ (((x) & BIT_MASK_PKT_LIFTIME_BEBK_8822C) \
+ << BIT_SHIFT_PKT_LIFTIME_BEBK_8822C)
+#define BITS_PKT_LIFTIME_BEBK_8822C \
+ (BIT_MASK_PKT_LIFTIME_BEBK_8822C << BIT_SHIFT_PKT_LIFTIME_BEBK_8822C)
+#define BIT_CLEAR_PKT_LIFTIME_BEBK_8822C(x) \
+ ((x) & (~BITS_PKT_LIFTIME_BEBK_8822C))
+#define BIT_GET_PKT_LIFTIME_BEBK_8822C(x) \
+ (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8822C) & \
+ BIT_MASK_PKT_LIFTIME_BEBK_8822C)
+#define BIT_SET_PKT_LIFTIME_BEBK_8822C(x, v) \
+ (BIT_CLEAR_PKT_LIFTIME_BEBK_8822C(x) | BIT_PKT_LIFTIME_BEBK_8822C(v))
+
+#define BIT_SHIFT_PKT_LIFTIME_VOVI_8822C 0
+#define BIT_MASK_PKT_LIFTIME_VOVI_8822C 0xffff
+#define BIT_PKT_LIFTIME_VOVI_8822C(x) \
+ (((x) & BIT_MASK_PKT_LIFTIME_VOVI_8822C) \
+ << BIT_SHIFT_PKT_LIFTIME_VOVI_8822C)
+#define BITS_PKT_LIFTIME_VOVI_8822C \
+ (BIT_MASK_PKT_LIFTIME_VOVI_8822C << BIT_SHIFT_PKT_LIFTIME_VOVI_8822C)
+#define BIT_CLEAR_PKT_LIFTIME_VOVI_8822C(x) \
+ ((x) & (~BITS_PKT_LIFTIME_VOVI_8822C))
+#define BIT_GET_PKT_LIFTIME_VOVI_8822C(x) \
+ (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8822C) & \
+ BIT_MASK_PKT_LIFTIME_VOVI_8822C)
+#define BIT_SET_PKT_LIFTIME_VOVI_8822C(x, v) \
+ (BIT_CLEAR_PKT_LIFTIME_VOVI_8822C(x) | BIT_PKT_LIFTIME_VOVI_8822C(v))
+
+/* 2 REG_STBC_SETTING_8822C */
+
+#define BIT_SHIFT_CDEND_TXTIME_L_8822C 4
+#define BIT_MASK_CDEND_TXTIME_L_8822C 0xf
+#define BIT_CDEND_TXTIME_L_8822C(x) \
+ (((x) & BIT_MASK_CDEND_TXTIME_L_8822C) \
+ << BIT_SHIFT_CDEND_TXTIME_L_8822C)
+#define BITS_CDEND_TXTIME_L_8822C \
+ (BIT_MASK_CDEND_TXTIME_L_8822C << BIT_SHIFT_CDEND_TXTIME_L_8822C)
+#define BIT_CLEAR_CDEND_TXTIME_L_8822C(x) ((x) & (~BITS_CDEND_TXTIME_L_8822C))
+#define BIT_GET_CDEND_TXTIME_L_8822C(x) \
+ (((x) >> BIT_SHIFT_CDEND_TXTIME_L_8822C) & \
+ BIT_MASK_CDEND_TXTIME_L_8822C)
+#define BIT_SET_CDEND_TXTIME_L_8822C(x, v) \
+ (BIT_CLEAR_CDEND_TXTIME_L_8822C(x) | BIT_CDEND_TXTIME_L_8822C(v))
+
+#define BIT_SHIFT_NESS_8822C 2
+#define BIT_MASK_NESS_8822C 0x3
+#define BIT_NESS_8822C(x) (((x) & BIT_MASK_NESS_8822C) << BIT_SHIFT_NESS_8822C)
+#define BITS_NESS_8822C (BIT_MASK_NESS_8822C << BIT_SHIFT_NESS_8822C)
+#define BIT_CLEAR_NESS_8822C(x) ((x) & (~BITS_NESS_8822C))
+#define BIT_GET_NESS_8822C(x) \
+ (((x) >> BIT_SHIFT_NESS_8822C) & BIT_MASK_NESS_8822C)
+#define BIT_SET_NESS_8822C(x, v) (BIT_CLEAR_NESS_8822C(x) | BIT_NESS_8822C(v))
+
+#define BIT_SHIFT_STBC_CFEND_8822C 0
+#define BIT_MASK_STBC_CFEND_8822C 0x3
+#define BIT_STBC_CFEND_8822C(x) \
+ (((x) & BIT_MASK_STBC_CFEND_8822C) << BIT_SHIFT_STBC_CFEND_8822C)
+#define BITS_STBC_CFEND_8822C \
+ (BIT_MASK_STBC_CFEND_8822C << BIT_SHIFT_STBC_CFEND_8822C)
+#define BIT_CLEAR_STBC_CFEND_8822C(x) ((x) & (~BITS_STBC_CFEND_8822C))
+#define BIT_GET_STBC_CFEND_8822C(x) \
+ (((x) >> BIT_SHIFT_STBC_CFEND_8822C) & BIT_MASK_STBC_CFEND_8822C)
+#define BIT_SET_STBC_CFEND_8822C(x, v) \
+ (BIT_CLEAR_STBC_CFEND_8822C(x) | BIT_STBC_CFEND_8822C(v))
+
+/* 2 REG_STBC_SETTING2_8822C */
+
+#define BIT_SHIFT_CDEND_TXTIME_H_8822C 0
+#define BIT_MASK_CDEND_TXTIME_H_8822C 0x1f
+#define BIT_CDEND_TXTIME_H_8822C(x) \
+ (((x) & BIT_MASK_CDEND_TXTIME_H_8822C) \
+ << BIT_SHIFT_CDEND_TXTIME_H_8822C)
+#define BITS_CDEND_TXTIME_H_8822C \
+ (BIT_MASK_CDEND_TXTIME_H_8822C << BIT_SHIFT_CDEND_TXTIME_H_8822C)
+#define BIT_CLEAR_CDEND_TXTIME_H_8822C(x) ((x) & (~BITS_CDEND_TXTIME_H_8822C))
+#define BIT_GET_CDEND_TXTIME_H_8822C(x) \
+ (((x) >> BIT_SHIFT_CDEND_TXTIME_H_8822C) & \
+ BIT_MASK_CDEND_TXTIME_H_8822C)
+#define BIT_SET_CDEND_TXTIME_H_8822C(x, v) \
+ (BIT_CLEAR_CDEND_TXTIME_H_8822C(x) | BIT_CDEND_TXTIME_H_8822C(v))
+
+/* 2 REG_QUEUE_CTRL_8822C */
+#define BIT_FORCE_RND_PRI_8822C BIT(6)
+#define BIT_PTA_EDCCA_EN_8822C BIT(5)
+#define BIT_PTA_WL_TX_EN_8822C BIT(4)
+#define BIT_R_USE_DATA_BW_8822C BIT(3)
+#define BIT_TRI_PKT_INT_MODE1_8822C BIT(2)
+#define BIT_TRI_PKT_INT_MODE0_8822C BIT(1)
+#define BIT_ACQ_MODE_SEL_8822C BIT(0)
+
+/* 2 REG_SINGLE_AMPDU_CTRL_8822C */
+#define BIT_EN_SINGLE_APMDU_8822C BIT(7)
+
+#define BIT_SHIFT_SNDTX_MAXTIME_8822C 0
+#define BIT_MASK_SNDTX_MAXTIME_8822C 0x7f
+#define BIT_SNDTX_MAXTIME_8822C(x) \
+ (((x) & BIT_MASK_SNDTX_MAXTIME_8822C) << BIT_SHIFT_SNDTX_MAXTIME_8822C)
+#define BITS_SNDTX_MAXTIME_8822C \
+ (BIT_MASK_SNDTX_MAXTIME_8822C << BIT_SHIFT_SNDTX_MAXTIME_8822C)
+#define BIT_CLEAR_SNDTX_MAXTIME_8822C(x) ((x) & (~BITS_SNDTX_MAXTIME_8822C))
+#define BIT_GET_SNDTX_MAXTIME_8822C(x) \
+ (((x) >> BIT_SHIFT_SNDTX_MAXTIME_8822C) & BIT_MASK_SNDTX_MAXTIME_8822C)
+#define BIT_SET_SNDTX_MAXTIME_8822C(x, v) \
+ (BIT_CLEAR_SNDTX_MAXTIME_8822C(x) | BIT_SNDTX_MAXTIME_8822C(v))
+
+/* 2 REG_PROT_MODE_CTRL_8822C */
+#define BIT_SND_SIFS_TXDATA_8822C BIT(31)
+#define BIT_TX_SND_MATCH_MACID_8822C BIT(30)
+
+#define BIT_SHIFT_RTS_MAX_AGG_NUM_8822C 24
+#define BIT_MASK_RTS_MAX_AGG_NUM_8822C 0x3f
+#define BIT_RTS_MAX_AGG_NUM_8822C(x) \
+ (((x) & BIT_MASK_RTS_MAX_AGG_NUM_8822C) \
+ << BIT_SHIFT_RTS_MAX_AGG_NUM_8822C)
+#define BITS_RTS_MAX_AGG_NUM_8822C \
+ (BIT_MASK_RTS_MAX_AGG_NUM_8822C << BIT_SHIFT_RTS_MAX_AGG_NUM_8822C)
+#define BIT_CLEAR_RTS_MAX_AGG_NUM_8822C(x) ((x) & (~BITS_RTS_MAX_AGG_NUM_8822C))
+#define BIT_GET_RTS_MAX_AGG_NUM_8822C(x) \
+ (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8822C) & \
+ BIT_MASK_RTS_MAX_AGG_NUM_8822C)
+#define BIT_SET_RTS_MAX_AGG_NUM_8822C(x, v) \
+ (BIT_CLEAR_RTS_MAX_AGG_NUM_8822C(x) | BIT_RTS_MAX_AGG_NUM_8822C(v))
+
+#define BIT_SHIFT_MAX_AGG_NUM_8822C 16
+#define BIT_MASK_MAX_AGG_NUM_8822C 0x3f
+#define BIT_MAX_AGG_NUM_8822C(x) \
+ (((x) & BIT_MASK_MAX_AGG_NUM_8822C) << BIT_SHIFT_MAX_AGG_NUM_8822C)
+#define BITS_MAX_AGG_NUM_8822C \
+ (BIT_MASK_MAX_AGG_NUM_8822C << BIT_SHIFT_MAX_AGG_NUM_8822C)
+#define BIT_CLEAR_MAX_AGG_NUM_8822C(x) ((x) & (~BITS_MAX_AGG_NUM_8822C))
+#define BIT_GET_MAX_AGG_NUM_8822C(x) \
+ (((x) >> BIT_SHIFT_MAX_AGG_NUM_8822C) & BIT_MASK_MAX_AGG_NUM_8822C)
+#define BIT_SET_MAX_AGG_NUM_8822C(x, v) \
+ (BIT_CLEAR_MAX_AGG_NUM_8822C(x) | BIT_MAX_AGG_NUM_8822C(v))
+
+#define BIT_SHIFT_RTS_TXTIME_TH_8822C 8
+#define BIT_MASK_RTS_TXTIME_TH_8822C 0xff
+#define BIT_RTS_TXTIME_TH_8822C(x) \
+ (((x) & BIT_MASK_RTS_TXTIME_TH_8822C) << BIT_SHIFT_RTS_TXTIME_TH_8822C)
+#define BITS_RTS_TXTIME_TH_8822C \
+ (BIT_MASK_RTS_TXTIME_TH_8822C << BIT_SHIFT_RTS_TXTIME_TH_8822C)
+#define BIT_CLEAR_RTS_TXTIME_TH_8822C(x) ((x) & (~BITS_RTS_TXTIME_TH_8822C))
+#define BIT_GET_RTS_TXTIME_TH_8822C(x) \
+ (((x) >> BIT_SHIFT_RTS_TXTIME_TH_8822C) & BIT_MASK_RTS_TXTIME_TH_8822C)
+#define BIT_SET_RTS_TXTIME_TH_8822C(x, v) \
+ (BIT_CLEAR_RTS_TXTIME_TH_8822C(x) | BIT_RTS_TXTIME_TH_8822C(v))
+
+#define BIT_SHIFT_RTS_LEN_TH_8822C 0
+#define BIT_MASK_RTS_LEN_TH_8822C 0xff
+#define BIT_RTS_LEN_TH_8822C(x) \
+ (((x) & BIT_MASK_RTS_LEN_TH_8822C) << BIT_SHIFT_RTS_LEN_TH_8822C)
+#define BITS_RTS_LEN_TH_8822C \
+ (BIT_MASK_RTS_LEN_TH_8822C << BIT_SHIFT_RTS_LEN_TH_8822C)
+#define BIT_CLEAR_RTS_LEN_TH_8822C(x) ((x) & (~BITS_RTS_LEN_TH_8822C))
+#define BIT_GET_RTS_LEN_TH_8822C(x) \
+ (((x) >> BIT_SHIFT_RTS_LEN_TH_8822C) & BIT_MASK_RTS_LEN_TH_8822C)
+#define BIT_SET_RTS_LEN_TH_8822C(x, v) \
+ (BIT_CLEAR_RTS_LEN_TH_8822C(x) | BIT_RTS_LEN_TH_8822C(v))
+
+/* 2 REG_BAR_MODE_CTRL_8822C */
+
+#define BIT_SHIFT_BAR_RTY_LMT_8822C 16
+#define BIT_MASK_BAR_RTY_LMT_8822C 0x3
+#define BIT_BAR_RTY_LMT_8822C(x) \
+ (((x) & BIT_MASK_BAR_RTY_LMT_8822C) << BIT_SHIFT_BAR_RTY_LMT_8822C)
+#define BITS_BAR_RTY_LMT_8822C \
+ (BIT_MASK_BAR_RTY_LMT_8822C << BIT_SHIFT_BAR_RTY_LMT_8822C)
+#define BIT_CLEAR_BAR_RTY_LMT_8822C(x) ((x) & (~BITS_BAR_RTY_LMT_8822C))
+#define BIT_GET_BAR_RTY_LMT_8822C(x) \
+ (((x) >> BIT_SHIFT_BAR_RTY_LMT_8822C) & BIT_MASK_BAR_RTY_LMT_8822C)
+#define BIT_SET_BAR_RTY_LMT_8822C(x, v) \
+ (BIT_CLEAR_BAR_RTY_LMT_8822C(x) | BIT_BAR_RTY_LMT_8822C(v))
+
+#define BIT_SHIFT_BAR_PKT_TXTIME_TH_8822C 8
+#define BIT_MASK_BAR_PKT_TXTIME_TH_8822C 0xff
+#define BIT_BAR_PKT_TXTIME_TH_8822C(x) \
+ (((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8822C) \
+ << BIT_SHIFT_BAR_PKT_TXTIME_TH_8822C)
+#define BITS_BAR_PKT_TXTIME_TH_8822C \
+ (BIT_MASK_BAR_PKT_TXTIME_TH_8822C << BIT_SHIFT_BAR_PKT_TXTIME_TH_8822C)
+#define BIT_CLEAR_BAR_PKT_TXTIME_TH_8822C(x) \
+ ((x) & (~BITS_BAR_PKT_TXTIME_TH_8822C))
+#define BIT_GET_BAR_PKT_TXTIME_TH_8822C(x) \
+ (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8822C) & \
+ BIT_MASK_BAR_PKT_TXTIME_TH_8822C)
+#define BIT_SET_BAR_PKT_TXTIME_TH_8822C(x, v) \
+ (BIT_CLEAR_BAR_PKT_TXTIME_TH_8822C(x) | BIT_BAR_PKT_TXTIME_TH_8822C(v))
+
+#define BIT_BAR_EN_V1_8822C BIT(6)
+
+#define BIT_SHIFT_BAR_PKTNUM_TH_V1_8822C 0
+#define BIT_MASK_BAR_PKTNUM_TH_V1_8822C 0x3f
+#define BIT_BAR_PKTNUM_TH_V1_8822C(x) \
+ (((x) & BIT_MASK_BAR_PKTNUM_TH_V1_8822C) \
+ << BIT_SHIFT_BAR_PKTNUM_TH_V1_8822C)
+#define BITS_BAR_PKTNUM_TH_V1_8822C \
+ (BIT_MASK_BAR_PKTNUM_TH_V1_8822C << BIT_SHIFT_BAR_PKTNUM_TH_V1_8822C)
+#define BIT_CLEAR_BAR_PKTNUM_TH_V1_8822C(x) \
+ ((x) & (~BITS_BAR_PKTNUM_TH_V1_8822C))
+#define BIT_GET_BAR_PKTNUM_TH_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8822C) & \
+ BIT_MASK_BAR_PKTNUM_TH_V1_8822C)
+#define BIT_SET_BAR_PKTNUM_TH_V1_8822C(x, v) \
+ (BIT_CLEAR_BAR_PKTNUM_TH_V1_8822C(x) | BIT_BAR_PKTNUM_TH_V1_8822C(v))
+
+/* 2 REG_RA_TRY_RATE_AGG_LMT_8822C */
+
+#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822C 0
+#define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822C 0x3f
+#define BIT_RA_TRY_RATE_AGG_LMT_V1_8822C(x) \
+ (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822C) \
+ << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822C)
+#define BITS_RA_TRY_RATE_AGG_LMT_V1_8822C \
+ (BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822C \
+ << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822C)
+#define BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8822C(x) \
+ ((x) & (~BITS_RA_TRY_RATE_AGG_LMT_V1_8822C))
+#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8822C) & \
+ BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8822C)
+#define BIT_SET_RA_TRY_RATE_AGG_LMT_V1_8822C(x, v) \
+ (BIT_CLEAR_RA_TRY_RATE_AGG_LMT_V1_8822C(x) | \
+ BIT_RA_TRY_RATE_AGG_LMT_V1_8822C(v))
+
+/* 2 REG_MACID_SLEEP2_8822C */
+
+#define BIT_SHIFT_MACID95_64PKTSLEEP_8822C 0
+#define BIT_MASK_MACID95_64PKTSLEEP_8822C 0xffffffffL
+#define BIT_MACID95_64PKTSLEEP_8822C(x) \
+ (((x) & BIT_MASK_MACID95_64PKTSLEEP_8822C) \
+ << BIT_SHIFT_MACID95_64PKTSLEEP_8822C)
+#define BITS_MACID95_64PKTSLEEP_8822C \
+ (BIT_MASK_MACID95_64PKTSLEEP_8822C \
+ << BIT_SHIFT_MACID95_64PKTSLEEP_8822C)
+#define BIT_CLEAR_MACID95_64PKTSLEEP_8822C(x) \
+ ((x) & (~BITS_MACID95_64PKTSLEEP_8822C))
+#define BIT_GET_MACID95_64PKTSLEEP_8822C(x) \
+ (((x) >> BIT_SHIFT_MACID95_64PKTSLEEP_8822C) & \
+ BIT_MASK_MACID95_64PKTSLEEP_8822C)
+#define BIT_SET_MACID95_64PKTSLEEP_8822C(x, v) \
+ (BIT_CLEAR_MACID95_64PKTSLEEP_8822C(x) | \
+ BIT_MACID95_64PKTSLEEP_8822C(v))
+
+/* 2 REG_MACID_SLEEP_8822C */
+
+#define BIT_SHIFT_MACID31_0_PKTSLEEP_8822C 0
+#define BIT_MASK_MACID31_0_PKTSLEEP_8822C 0xffffffffL
+#define BIT_MACID31_0_PKTSLEEP_8822C(x) \
+ (((x) & BIT_MASK_MACID31_0_PKTSLEEP_8822C) \
+ << BIT_SHIFT_MACID31_0_PKTSLEEP_8822C)
+#define BITS_MACID31_0_PKTSLEEP_8822C \
+ (BIT_MASK_MACID31_0_PKTSLEEP_8822C \
+ << BIT_SHIFT_MACID31_0_PKTSLEEP_8822C)
+#define BIT_CLEAR_MACID31_0_PKTSLEEP_8822C(x) \
+ ((x) & (~BITS_MACID31_0_PKTSLEEP_8822C))
+#define BIT_GET_MACID31_0_PKTSLEEP_8822C(x) \
+ (((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP_8822C) & \
+ BIT_MASK_MACID31_0_PKTSLEEP_8822C)
+#define BIT_SET_MACID31_0_PKTSLEEP_8822C(x, v) \
+ (BIT_CLEAR_MACID31_0_PKTSLEEP_8822C(x) | \
+ BIT_MACID31_0_PKTSLEEP_8822C(v))
+
+/* 2 REG_HW_SEQ0_8822C */
+
+#define BIT_SHIFT_HW_SSN_SEQ0_8822C 0
+#define BIT_MASK_HW_SSN_SEQ0_8822C 0xfff
+#define BIT_HW_SSN_SEQ0_8822C(x) \
+ (((x) & BIT_MASK_HW_SSN_SEQ0_8822C) << BIT_SHIFT_HW_SSN_SEQ0_8822C)
+#define BITS_HW_SSN_SEQ0_8822C \
+ (BIT_MASK_HW_SSN_SEQ0_8822C << BIT_SHIFT_HW_SSN_SEQ0_8822C)
+#define BIT_CLEAR_HW_SSN_SEQ0_8822C(x) ((x) & (~BITS_HW_SSN_SEQ0_8822C))
+#define BIT_GET_HW_SSN_SEQ0_8822C(x) \
+ (((x) >> BIT_SHIFT_HW_SSN_SEQ0_8822C) & BIT_MASK_HW_SSN_SEQ0_8822C)
+#define BIT_SET_HW_SSN_SEQ0_8822C(x, v) \
+ (BIT_CLEAR_HW_SSN_SEQ0_8822C(x) | BIT_HW_SSN_SEQ0_8822C(v))
+
+/* 2 REG_HW_SEQ1_8822C */
+
+#define BIT_SHIFT_HW_SSN_SEQ1_8822C 0
+#define BIT_MASK_HW_SSN_SEQ1_8822C 0xfff
+#define BIT_HW_SSN_SEQ1_8822C(x) \
+ (((x) & BIT_MASK_HW_SSN_SEQ1_8822C) << BIT_SHIFT_HW_SSN_SEQ1_8822C)
+#define BITS_HW_SSN_SEQ1_8822C \
+ (BIT_MASK_HW_SSN_SEQ1_8822C << BIT_SHIFT_HW_SSN_SEQ1_8822C)
+#define BIT_CLEAR_HW_SSN_SEQ1_8822C(x) ((x) & (~BITS_HW_SSN_SEQ1_8822C))
+#define BIT_GET_HW_SSN_SEQ1_8822C(x) \
+ (((x) >> BIT_SHIFT_HW_SSN_SEQ1_8822C) & BIT_MASK_HW_SSN_SEQ1_8822C)
+#define BIT_SET_HW_SSN_SEQ1_8822C(x, v) \
+ (BIT_CLEAR_HW_SSN_SEQ1_8822C(x) | BIT_HW_SSN_SEQ1_8822C(v))
+
+/* 2 REG_HW_SEQ2_8822C */
+
+#define BIT_SHIFT_HW_SSN_SEQ2_8822C 0
+#define BIT_MASK_HW_SSN_SEQ2_8822C 0xfff
+#define BIT_HW_SSN_SEQ2_8822C(x) \
+ (((x) & BIT_MASK_HW_SSN_SEQ2_8822C) << BIT_SHIFT_HW_SSN_SEQ2_8822C)
+#define BITS_HW_SSN_SEQ2_8822C \
+ (BIT_MASK_HW_SSN_SEQ2_8822C << BIT_SHIFT_HW_SSN_SEQ2_8822C)
+#define BIT_CLEAR_HW_SSN_SEQ2_8822C(x) ((x) & (~BITS_HW_SSN_SEQ2_8822C))
+#define BIT_GET_HW_SSN_SEQ2_8822C(x) \
+ (((x) >> BIT_SHIFT_HW_SSN_SEQ2_8822C) & BIT_MASK_HW_SSN_SEQ2_8822C)
+#define BIT_SET_HW_SSN_SEQ2_8822C(x, v) \
+ (BIT_CLEAR_HW_SSN_SEQ2_8822C(x) | BIT_HW_SSN_SEQ2_8822C(v))
+
+/* 2 REG_HW_SEQ3_8822C */
+
+#define BIT_SHIFT_CSI_HWSEQ_SEL_8822C 12
+#define BIT_MASK_CSI_HWSEQ_SEL_8822C 0x3
+#define BIT_CSI_HWSEQ_SEL_8822C(x) \
+ (((x) & BIT_MASK_CSI_HWSEQ_SEL_8822C) << BIT_SHIFT_CSI_HWSEQ_SEL_8822C)
+#define BITS_CSI_HWSEQ_SEL_8822C \
+ (BIT_MASK_CSI_HWSEQ_SEL_8822C << BIT_SHIFT_CSI_HWSEQ_SEL_8822C)
+#define BIT_CLEAR_CSI_HWSEQ_SEL_8822C(x) ((x) & (~BITS_CSI_HWSEQ_SEL_8822C))
+#define BIT_GET_CSI_HWSEQ_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_CSI_HWSEQ_SEL_8822C) & BIT_MASK_CSI_HWSEQ_SEL_8822C)
+#define BIT_SET_CSI_HWSEQ_SEL_8822C(x, v) \
+ (BIT_CLEAR_CSI_HWSEQ_SEL_8822C(x) | BIT_CSI_HWSEQ_SEL_8822C(v))
+
+#define BIT_SHIFT_HW_SSN_SEQ3_8822C 0
+#define BIT_MASK_HW_SSN_SEQ3_8822C 0xfff
+#define BIT_HW_SSN_SEQ3_8822C(x) \
+ (((x) & BIT_MASK_HW_SSN_SEQ3_8822C) << BIT_SHIFT_HW_SSN_SEQ3_8822C)
+#define BITS_HW_SSN_SEQ3_8822C \
+ (BIT_MASK_HW_SSN_SEQ3_8822C << BIT_SHIFT_HW_SSN_SEQ3_8822C)
+#define BIT_CLEAR_HW_SSN_SEQ3_8822C(x) ((x) & (~BITS_HW_SSN_SEQ3_8822C))
+#define BIT_GET_HW_SSN_SEQ3_8822C(x) \
+ (((x) >> BIT_SHIFT_HW_SSN_SEQ3_8822C) & BIT_MASK_HW_SSN_SEQ3_8822C)
+#define BIT_SET_HW_SSN_SEQ3_8822C(x, v) \
+ (BIT_CLEAR_HW_SSN_SEQ3_8822C(x) | BIT_HW_SSN_SEQ3_8822C(v))
+
+/* 2 REG_NULL_PKT_STATUS_V1_8822C */
+
+#define BIT_SHIFT_PTCL_TOTAL_PG_V2_8822C 2
+#define BIT_MASK_PTCL_TOTAL_PG_V2_8822C 0x3fff
+#define BIT_PTCL_TOTAL_PG_V2_8822C(x) \
+ (((x) & BIT_MASK_PTCL_TOTAL_PG_V2_8822C) \
+ << BIT_SHIFT_PTCL_TOTAL_PG_V2_8822C)
+#define BITS_PTCL_TOTAL_PG_V2_8822C \
+ (BIT_MASK_PTCL_TOTAL_PG_V2_8822C << BIT_SHIFT_PTCL_TOTAL_PG_V2_8822C)
+#define BIT_CLEAR_PTCL_TOTAL_PG_V2_8822C(x) \
+ ((x) & (~BITS_PTCL_TOTAL_PG_V2_8822C))
+#define BIT_GET_PTCL_TOTAL_PG_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2_8822C) & \
+ BIT_MASK_PTCL_TOTAL_PG_V2_8822C)
+#define BIT_SET_PTCL_TOTAL_PG_V2_8822C(x, v) \
+ (BIT_CLEAR_PTCL_TOTAL_PG_V2_8822C(x) | BIT_PTCL_TOTAL_PG_V2_8822C(v))
+
+#define BIT_TX_NULL_1_8822C BIT(1)
+#define BIT_TX_NULL_0_8822C BIT(0)
+
+/* 2 REG_PTCL_ERR_STATUS_8822C */
+#define BIT_PTCL_RATE_TABLE_INVALID_8822C BIT(7)
+#define BIT_FTM_T2R_ERROR_8822C BIT(6)
+#define BIT_PTCL_ERR0_8822C BIT(5)
+#define BIT_PTCL_ERR1_8822C BIT(4)
+#define BIT_PTCL_ERR2_8822C BIT(3)
+#define BIT_PTCL_ERR3_8822C BIT(2)
+#define BIT_PTCL_ERR4_8822C BIT(1)
+#define BIT_PTCL_ERR5_8822C BIT(0)
+
+/* 2 REG_NULL_PKT_STATUS_EXTEND_8822C */
+#define BIT_CLI3_TX_NULL_1_8822C BIT(7)
+#define BIT_CLI3_TX_NULL_0_8822C BIT(6)
+#define BIT_CLI2_TX_NULL_1_8822C BIT(5)
+#define BIT_CLI2_TX_NULL_0_8822C BIT(4)
+#define BIT_CLI1_TX_NULL_1_8822C BIT(3)
+#define BIT_CLI1_TX_NULL_0_8822C BIT(2)
+#define BIT_CLI0_TX_NULL_1_8822C BIT(1)
+#define BIT_CLI0_TX_NULL_0_8822C BIT(0)
+
+/* 2 REG_HQMGQ_DROP_8822C */
+#define BIT_HIQ_DROP_8822C BIT(7)
+#define BIT_MGQ_DROP_8822C BIT(6)
+#define BIT_CLR_HGQ_REQ_BLOCK_8822C BIT(5)
+
+/* 2 REG_PRECNT_CTRL_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_EN_PRECNT_8822C BIT(11)
+
+#define BIT_SHIFT_PRECNT_TH_8822C 0
+#define BIT_MASK_PRECNT_TH_8822C 0x7ff
+#define BIT_PRECNT_TH_8822C(x) \
+ (((x) & BIT_MASK_PRECNT_TH_8822C) << BIT_SHIFT_PRECNT_TH_8822C)
+#define BITS_PRECNT_TH_8822C \
+ (BIT_MASK_PRECNT_TH_8822C << BIT_SHIFT_PRECNT_TH_8822C)
+#define BIT_CLEAR_PRECNT_TH_8822C(x) ((x) & (~BITS_PRECNT_TH_8822C))
+#define BIT_GET_PRECNT_TH_8822C(x) \
+ (((x) >> BIT_SHIFT_PRECNT_TH_8822C) & BIT_MASK_PRECNT_TH_8822C)
+#define BIT_SET_PRECNT_TH_8822C(x, v) \
+ (BIT_CLEAR_PRECNT_TH_8822C(x) | BIT_PRECNT_TH_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_BT_POLLUTE_PKT_CNT_8822C */
+
+#define BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822C 0
+#define BIT_MASK_BT_POLLUTE_PKT_CNT_8822C 0xffff
+#define BIT_BT_POLLUTE_PKT_CNT_8822C(x) \
+ (((x) & BIT_MASK_BT_POLLUTE_PKT_CNT_8822C) \
+ << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822C)
+#define BITS_BT_POLLUTE_PKT_CNT_8822C \
+ (BIT_MASK_BT_POLLUTE_PKT_CNT_8822C \
+ << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822C)
+#define BIT_CLEAR_BT_POLLUTE_PKT_CNT_8822C(x) \
+ ((x) & (~BITS_BT_POLLUTE_PKT_CNT_8822C))
+#define BIT_GET_BT_POLLUTE_PKT_CNT_8822C(x) \
+ (((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT_8822C) & \
+ BIT_MASK_BT_POLLUTE_PKT_CNT_8822C)
+#define BIT_SET_BT_POLLUTE_PKT_CNT_8822C(x, v) \
+ (BIT_CLEAR_BT_POLLUTE_PKT_CNT_8822C(x) | \
+ BIT_BT_POLLUTE_PKT_CNT_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_PTCL_DBG_8822C */
+
+#define BIT_SHIFT_PTCL_DBG_8822C 0
+#define BIT_MASK_PTCL_DBG_8822C 0xffffffffL
+#define BIT_PTCL_DBG_8822C(x) \
+ (((x) & BIT_MASK_PTCL_DBG_8822C) << BIT_SHIFT_PTCL_DBG_8822C)
+#define BITS_PTCL_DBG_8822C \
+ (BIT_MASK_PTCL_DBG_8822C << BIT_SHIFT_PTCL_DBG_8822C)
+#define BIT_CLEAR_PTCL_DBG_8822C(x) ((x) & (~BITS_PTCL_DBG_8822C))
+#define BIT_GET_PTCL_DBG_8822C(x) \
+ (((x) >> BIT_SHIFT_PTCL_DBG_8822C) & BIT_MASK_PTCL_DBG_8822C)
+#define BIT_SET_PTCL_DBG_8822C(x, v) \
+ (BIT_CLEAR_PTCL_DBG_8822C(x) | BIT_PTCL_DBG_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_CPUMGQ_TIMER_CTRL2_8822C */
+
+#define BIT_SHIFT_TRI_HEAD_ADDR_8822C 16
+#define BIT_MASK_TRI_HEAD_ADDR_8822C 0xfff
+#define BIT_TRI_HEAD_ADDR_8822C(x) \
+ (((x) & BIT_MASK_TRI_HEAD_ADDR_8822C) << BIT_SHIFT_TRI_HEAD_ADDR_8822C)
+#define BITS_TRI_HEAD_ADDR_8822C \
+ (BIT_MASK_TRI_HEAD_ADDR_8822C << BIT_SHIFT_TRI_HEAD_ADDR_8822C)
+#define BIT_CLEAR_TRI_HEAD_ADDR_8822C(x) ((x) & (~BITS_TRI_HEAD_ADDR_8822C))
+#define BIT_GET_TRI_HEAD_ADDR_8822C(x) \
+ (((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8822C) & BIT_MASK_TRI_HEAD_ADDR_8822C)
+#define BIT_SET_TRI_HEAD_ADDR_8822C(x, v) \
+ (BIT_CLEAR_TRI_HEAD_ADDR_8822C(x) | BIT_TRI_HEAD_ADDR_8822C(v))
+
+#define BIT_DROP_TH_EN_8822C BIT(8)
+
+#define BIT_SHIFT_DROP_TH_8822C 0
+#define BIT_MASK_DROP_TH_8822C 0xff
+#define BIT_DROP_TH_8822C(x) \
+ (((x) & BIT_MASK_DROP_TH_8822C) << BIT_SHIFT_DROP_TH_8822C)
+#define BITS_DROP_TH_8822C (BIT_MASK_DROP_TH_8822C << BIT_SHIFT_DROP_TH_8822C)
+#define BIT_CLEAR_DROP_TH_8822C(x) ((x) & (~BITS_DROP_TH_8822C))
+#define BIT_GET_DROP_TH_8822C(x) \
+ (((x) >> BIT_SHIFT_DROP_TH_8822C) & BIT_MASK_DROP_TH_8822C)
+#define BIT_SET_DROP_TH_8822C(x, v) \
+ (BIT_CLEAR_DROP_TH_8822C(x) | BIT_DROP_TH_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_DUMMY_PAGE4_V1_8822C */
+
+/* 2 REG_MOREDATA_8822C */
+#define BIT_MOREDATA_CTRL2_EN_V1_8822C BIT(3)
+#define BIT_MOREDATA_CTRL1_EN_V1_8822C BIT(2)
+#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE_V1_8822C BIT(0)
+
+/* 2 REG_Q0_Q1_INFO_8822C */
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822C BIT(31)
+
+#define BIT_SHIFT_GTAB_ID_8822C 28
+#define BIT_MASK_GTAB_ID_8822C 0x7
+#define BIT_GTAB_ID_8822C(x) \
+ (((x) & BIT_MASK_GTAB_ID_8822C) << BIT_SHIFT_GTAB_ID_8822C)
+#define BITS_GTAB_ID_8822C (BIT_MASK_GTAB_ID_8822C << BIT_SHIFT_GTAB_ID_8822C)
+#define BIT_CLEAR_GTAB_ID_8822C(x) ((x) & (~BITS_GTAB_ID_8822C))
+#define BIT_GET_GTAB_ID_8822C(x) \
+ (((x) >> BIT_SHIFT_GTAB_ID_8822C) & BIT_MASK_GTAB_ID_8822C)
+#define BIT_SET_GTAB_ID_8822C(x, v) \
+ (BIT_CLEAR_GTAB_ID_8822C(x) | BIT_GTAB_ID_8822C(v))
+
+#define BIT_SHIFT_AC1_PKT_INFO_8822C 16
+#define BIT_MASK_AC1_PKT_INFO_8822C 0xfff
+#define BIT_AC1_PKT_INFO_8822C(x) \
+ (((x) & BIT_MASK_AC1_PKT_INFO_8822C) << BIT_SHIFT_AC1_PKT_INFO_8822C)
+#define BITS_AC1_PKT_INFO_8822C \
+ (BIT_MASK_AC1_PKT_INFO_8822C << BIT_SHIFT_AC1_PKT_INFO_8822C)
+#define BIT_CLEAR_AC1_PKT_INFO_8822C(x) ((x) & (~BITS_AC1_PKT_INFO_8822C))
+#define BIT_GET_AC1_PKT_INFO_8822C(x) \
+ (((x) >> BIT_SHIFT_AC1_PKT_INFO_8822C) & BIT_MASK_AC1_PKT_INFO_8822C)
+#define BIT_SET_AC1_PKT_INFO_8822C(x, v) \
+ (BIT_CLEAR_AC1_PKT_INFO_8822C(x) | BIT_AC1_PKT_INFO_8822C(v))
+
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822C BIT(15)
+
+#define BIT_SHIFT_GTAB_ID_V1_8822C 12
+#define BIT_MASK_GTAB_ID_V1_8822C 0x7
+#define BIT_GTAB_ID_V1_8822C(x) \
+ (((x) & BIT_MASK_GTAB_ID_V1_8822C) << BIT_SHIFT_GTAB_ID_V1_8822C)
+#define BITS_GTAB_ID_V1_8822C \
+ (BIT_MASK_GTAB_ID_V1_8822C << BIT_SHIFT_GTAB_ID_V1_8822C)
+#define BIT_CLEAR_GTAB_ID_V1_8822C(x) ((x) & (~BITS_GTAB_ID_V1_8822C))
+#define BIT_GET_GTAB_ID_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_GTAB_ID_V1_8822C) & BIT_MASK_GTAB_ID_V1_8822C)
+#define BIT_SET_GTAB_ID_V1_8822C(x, v) \
+ (BIT_CLEAR_GTAB_ID_V1_8822C(x) | BIT_GTAB_ID_V1_8822C(v))
+
+#define BIT_SHIFT_AC0_PKT_INFO_8822C 0
+#define BIT_MASK_AC0_PKT_INFO_8822C 0xfff
+#define BIT_AC0_PKT_INFO_8822C(x) \
+ (((x) & BIT_MASK_AC0_PKT_INFO_8822C) << BIT_SHIFT_AC0_PKT_INFO_8822C)
+#define BITS_AC0_PKT_INFO_8822C \
+ (BIT_MASK_AC0_PKT_INFO_8822C << BIT_SHIFT_AC0_PKT_INFO_8822C)
+#define BIT_CLEAR_AC0_PKT_INFO_8822C(x) ((x) & (~BITS_AC0_PKT_INFO_8822C))
+#define BIT_GET_AC0_PKT_INFO_8822C(x) \
+ (((x) >> BIT_SHIFT_AC0_PKT_INFO_8822C) & BIT_MASK_AC0_PKT_INFO_8822C)
+#define BIT_SET_AC0_PKT_INFO_8822C(x, v) \
+ (BIT_CLEAR_AC0_PKT_INFO_8822C(x) | BIT_AC0_PKT_INFO_8822C(v))
+
+/* 2 REG_Q2_Q3_INFO_8822C */
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822C BIT(31)
+
+#define BIT_SHIFT_GTAB_ID_8822C 28
+#define BIT_MASK_GTAB_ID_8822C 0x7
+#define BIT_GTAB_ID_8822C(x) \
+ (((x) & BIT_MASK_GTAB_ID_8822C) << BIT_SHIFT_GTAB_ID_8822C)
+#define BITS_GTAB_ID_8822C (BIT_MASK_GTAB_ID_8822C << BIT_SHIFT_GTAB_ID_8822C)
+#define BIT_CLEAR_GTAB_ID_8822C(x) ((x) & (~BITS_GTAB_ID_8822C))
+#define BIT_GET_GTAB_ID_8822C(x) \
+ (((x) >> BIT_SHIFT_GTAB_ID_8822C) & BIT_MASK_GTAB_ID_8822C)
+#define BIT_SET_GTAB_ID_8822C(x, v) \
+ (BIT_CLEAR_GTAB_ID_8822C(x) | BIT_GTAB_ID_8822C(v))
+
+#define BIT_SHIFT_AC3_PKT_INFO_8822C 16
+#define BIT_MASK_AC3_PKT_INFO_8822C 0xfff
+#define BIT_AC3_PKT_INFO_8822C(x) \
+ (((x) & BIT_MASK_AC3_PKT_INFO_8822C) << BIT_SHIFT_AC3_PKT_INFO_8822C)
+#define BITS_AC3_PKT_INFO_8822C \
+ (BIT_MASK_AC3_PKT_INFO_8822C << BIT_SHIFT_AC3_PKT_INFO_8822C)
+#define BIT_CLEAR_AC3_PKT_INFO_8822C(x) ((x) & (~BITS_AC3_PKT_INFO_8822C))
+#define BIT_GET_AC3_PKT_INFO_8822C(x) \
+ (((x) >> BIT_SHIFT_AC3_PKT_INFO_8822C) & BIT_MASK_AC3_PKT_INFO_8822C)
+#define BIT_SET_AC3_PKT_INFO_8822C(x, v) \
+ (BIT_CLEAR_AC3_PKT_INFO_8822C(x) | BIT_AC3_PKT_INFO_8822C(v))
+
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822C BIT(15)
+
+#define BIT_SHIFT_GTAB_ID_V1_8822C 12
+#define BIT_MASK_GTAB_ID_V1_8822C 0x7
+#define BIT_GTAB_ID_V1_8822C(x) \
+ (((x) & BIT_MASK_GTAB_ID_V1_8822C) << BIT_SHIFT_GTAB_ID_V1_8822C)
+#define BITS_GTAB_ID_V1_8822C \
+ (BIT_MASK_GTAB_ID_V1_8822C << BIT_SHIFT_GTAB_ID_V1_8822C)
+#define BIT_CLEAR_GTAB_ID_V1_8822C(x) ((x) & (~BITS_GTAB_ID_V1_8822C))
+#define BIT_GET_GTAB_ID_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_GTAB_ID_V1_8822C) & BIT_MASK_GTAB_ID_V1_8822C)
+#define BIT_SET_GTAB_ID_V1_8822C(x, v) \
+ (BIT_CLEAR_GTAB_ID_V1_8822C(x) | BIT_GTAB_ID_V1_8822C(v))
+
+#define BIT_SHIFT_AC2_PKT_INFO_8822C 0
+#define BIT_MASK_AC2_PKT_INFO_8822C 0xfff
+#define BIT_AC2_PKT_INFO_8822C(x) \
+ (((x) & BIT_MASK_AC2_PKT_INFO_8822C) << BIT_SHIFT_AC2_PKT_INFO_8822C)
+#define BITS_AC2_PKT_INFO_8822C \
+ (BIT_MASK_AC2_PKT_INFO_8822C << BIT_SHIFT_AC2_PKT_INFO_8822C)
+#define BIT_CLEAR_AC2_PKT_INFO_8822C(x) ((x) & (~BITS_AC2_PKT_INFO_8822C))
+#define BIT_GET_AC2_PKT_INFO_8822C(x) \
+ (((x) >> BIT_SHIFT_AC2_PKT_INFO_8822C) & BIT_MASK_AC2_PKT_INFO_8822C)
+#define BIT_SET_AC2_PKT_INFO_8822C(x, v) \
+ (BIT_CLEAR_AC2_PKT_INFO_8822C(x) | BIT_AC2_PKT_INFO_8822C(v))
+
+/* 2 REG_Q4_Q5_INFO_8822C */
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822C BIT(31)
+
+#define BIT_SHIFT_GTAB_ID_8822C 28
+#define BIT_MASK_GTAB_ID_8822C 0x7
+#define BIT_GTAB_ID_8822C(x) \
+ (((x) & BIT_MASK_GTAB_ID_8822C) << BIT_SHIFT_GTAB_ID_8822C)
+#define BITS_GTAB_ID_8822C (BIT_MASK_GTAB_ID_8822C << BIT_SHIFT_GTAB_ID_8822C)
+#define BIT_CLEAR_GTAB_ID_8822C(x) ((x) & (~BITS_GTAB_ID_8822C))
+#define BIT_GET_GTAB_ID_8822C(x) \
+ (((x) >> BIT_SHIFT_GTAB_ID_8822C) & BIT_MASK_GTAB_ID_8822C)
+#define BIT_SET_GTAB_ID_8822C(x, v) \
+ (BIT_CLEAR_GTAB_ID_8822C(x) | BIT_GTAB_ID_8822C(v))
+
+#define BIT_SHIFT_AC5_PKT_INFO_8822C 16
+#define BIT_MASK_AC5_PKT_INFO_8822C 0xfff
+#define BIT_AC5_PKT_INFO_8822C(x) \
+ (((x) & BIT_MASK_AC5_PKT_INFO_8822C) << BIT_SHIFT_AC5_PKT_INFO_8822C)
+#define BITS_AC5_PKT_INFO_8822C \
+ (BIT_MASK_AC5_PKT_INFO_8822C << BIT_SHIFT_AC5_PKT_INFO_8822C)
+#define BIT_CLEAR_AC5_PKT_INFO_8822C(x) ((x) & (~BITS_AC5_PKT_INFO_8822C))
+#define BIT_GET_AC5_PKT_INFO_8822C(x) \
+ (((x) >> BIT_SHIFT_AC5_PKT_INFO_8822C) & BIT_MASK_AC5_PKT_INFO_8822C)
+#define BIT_SET_AC5_PKT_INFO_8822C(x, v) \
+ (BIT_CLEAR_AC5_PKT_INFO_8822C(x) | BIT_AC5_PKT_INFO_8822C(v))
+
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822C BIT(15)
+
+#define BIT_SHIFT_GTAB_ID_V1_8822C 12
+#define BIT_MASK_GTAB_ID_V1_8822C 0x7
+#define BIT_GTAB_ID_V1_8822C(x) \
+ (((x) & BIT_MASK_GTAB_ID_V1_8822C) << BIT_SHIFT_GTAB_ID_V1_8822C)
+#define BITS_GTAB_ID_V1_8822C \
+ (BIT_MASK_GTAB_ID_V1_8822C << BIT_SHIFT_GTAB_ID_V1_8822C)
+#define BIT_CLEAR_GTAB_ID_V1_8822C(x) ((x) & (~BITS_GTAB_ID_V1_8822C))
+#define BIT_GET_GTAB_ID_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_GTAB_ID_V1_8822C) & BIT_MASK_GTAB_ID_V1_8822C)
+#define BIT_SET_GTAB_ID_V1_8822C(x, v) \
+ (BIT_CLEAR_GTAB_ID_V1_8822C(x) | BIT_GTAB_ID_V1_8822C(v))
+
+#define BIT_SHIFT_AC4_PKT_INFO_8822C 0
+#define BIT_MASK_AC4_PKT_INFO_8822C 0xfff
+#define BIT_AC4_PKT_INFO_8822C(x) \
+ (((x) & BIT_MASK_AC4_PKT_INFO_8822C) << BIT_SHIFT_AC4_PKT_INFO_8822C)
+#define BITS_AC4_PKT_INFO_8822C \
+ (BIT_MASK_AC4_PKT_INFO_8822C << BIT_SHIFT_AC4_PKT_INFO_8822C)
+#define BIT_CLEAR_AC4_PKT_INFO_8822C(x) ((x) & (~BITS_AC4_PKT_INFO_8822C))
+#define BIT_GET_AC4_PKT_INFO_8822C(x) \
+ (((x) >> BIT_SHIFT_AC4_PKT_INFO_8822C) & BIT_MASK_AC4_PKT_INFO_8822C)
+#define BIT_SET_AC4_PKT_INFO_8822C(x, v) \
+ (BIT_CLEAR_AC4_PKT_INFO_8822C(x) | BIT_AC4_PKT_INFO_8822C(v))
+
+/* 2 REG_Q6_Q7_INFO_8822C */
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8822C BIT(31)
+
+#define BIT_SHIFT_GTAB_ID_8822C 28
+#define BIT_MASK_GTAB_ID_8822C 0x7
+#define BIT_GTAB_ID_8822C(x) \
+ (((x) & BIT_MASK_GTAB_ID_8822C) << BIT_SHIFT_GTAB_ID_8822C)
+#define BITS_GTAB_ID_8822C (BIT_MASK_GTAB_ID_8822C << BIT_SHIFT_GTAB_ID_8822C)
+#define BIT_CLEAR_GTAB_ID_8822C(x) ((x) & (~BITS_GTAB_ID_8822C))
+#define BIT_GET_GTAB_ID_8822C(x) \
+ (((x) >> BIT_SHIFT_GTAB_ID_8822C) & BIT_MASK_GTAB_ID_8822C)
+#define BIT_SET_GTAB_ID_8822C(x, v) \
+ (BIT_CLEAR_GTAB_ID_8822C(x) | BIT_GTAB_ID_8822C(v))
+
+#define BIT_SHIFT_AC7_PKT_INFO_8822C 16
+#define BIT_MASK_AC7_PKT_INFO_8822C 0xfff
+#define BIT_AC7_PKT_INFO_8822C(x) \
+ (((x) & BIT_MASK_AC7_PKT_INFO_8822C) << BIT_SHIFT_AC7_PKT_INFO_8822C)
+#define BITS_AC7_PKT_INFO_8822C \
+ (BIT_MASK_AC7_PKT_INFO_8822C << BIT_SHIFT_AC7_PKT_INFO_8822C)
+#define BIT_CLEAR_AC7_PKT_INFO_8822C(x) ((x) & (~BITS_AC7_PKT_INFO_8822C))
+#define BIT_GET_AC7_PKT_INFO_8822C(x) \
+ (((x) >> BIT_SHIFT_AC7_PKT_INFO_8822C) & BIT_MASK_AC7_PKT_INFO_8822C)
+#define BIT_SET_AC7_PKT_INFO_8822C(x, v) \
+ (BIT_CLEAR_AC7_PKT_INFO_8822C(x) | BIT_AC7_PKT_INFO_8822C(v))
+
+#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8822C BIT(15)
+
+#define BIT_SHIFT_GTAB_ID_V1_8822C 12
+#define BIT_MASK_GTAB_ID_V1_8822C 0x7
+#define BIT_GTAB_ID_V1_8822C(x) \
+ (((x) & BIT_MASK_GTAB_ID_V1_8822C) << BIT_SHIFT_GTAB_ID_V1_8822C)
+#define BITS_GTAB_ID_V1_8822C \
+ (BIT_MASK_GTAB_ID_V1_8822C << BIT_SHIFT_GTAB_ID_V1_8822C)
+#define BIT_CLEAR_GTAB_ID_V1_8822C(x) ((x) & (~BITS_GTAB_ID_V1_8822C))
+#define BIT_GET_GTAB_ID_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_GTAB_ID_V1_8822C) & BIT_MASK_GTAB_ID_V1_8822C)
+#define BIT_SET_GTAB_ID_V1_8822C(x, v) \
+ (BIT_CLEAR_GTAB_ID_V1_8822C(x) | BIT_GTAB_ID_V1_8822C(v))
+
+#define BIT_SHIFT_AC6_PKT_INFO_8822C 0
+#define BIT_MASK_AC6_PKT_INFO_8822C 0xfff
+#define BIT_AC6_PKT_INFO_8822C(x) \
+ (((x) & BIT_MASK_AC6_PKT_INFO_8822C) << BIT_SHIFT_AC6_PKT_INFO_8822C)
+#define BITS_AC6_PKT_INFO_8822C \
+ (BIT_MASK_AC6_PKT_INFO_8822C << BIT_SHIFT_AC6_PKT_INFO_8822C)
+#define BIT_CLEAR_AC6_PKT_INFO_8822C(x) ((x) & (~BITS_AC6_PKT_INFO_8822C))
+#define BIT_GET_AC6_PKT_INFO_8822C(x) \
+ (((x) >> BIT_SHIFT_AC6_PKT_INFO_8822C) & BIT_MASK_AC6_PKT_INFO_8822C)
+#define BIT_SET_AC6_PKT_INFO_8822C(x, v) \
+ (BIT_CLEAR_AC6_PKT_INFO_8822C(x) | BIT_AC6_PKT_INFO_8822C(v))
+
+/* 2 REG_MGQ_HIQ_INFO_8822C */
+
+#define BIT_SHIFT_HIQ_PKT_INFO_8822C 16
+#define BIT_MASK_HIQ_PKT_INFO_8822C 0xfff
+#define BIT_HIQ_PKT_INFO_8822C(x) \
+ (((x) & BIT_MASK_HIQ_PKT_INFO_8822C) << BIT_SHIFT_HIQ_PKT_INFO_8822C)
+#define BITS_HIQ_PKT_INFO_8822C \
+ (BIT_MASK_HIQ_PKT_INFO_8822C << BIT_SHIFT_HIQ_PKT_INFO_8822C)
+#define BIT_CLEAR_HIQ_PKT_INFO_8822C(x) ((x) & (~BITS_HIQ_PKT_INFO_8822C))
+#define BIT_GET_HIQ_PKT_INFO_8822C(x) \
+ (((x) >> BIT_SHIFT_HIQ_PKT_INFO_8822C) & BIT_MASK_HIQ_PKT_INFO_8822C)
+#define BIT_SET_HIQ_PKT_INFO_8822C(x, v) \
+ (BIT_CLEAR_HIQ_PKT_INFO_8822C(x) | BIT_HIQ_PKT_INFO_8822C(v))
+
+#define BIT_SHIFT_MGQ_PKT_INFO_8822C 0
+#define BIT_MASK_MGQ_PKT_INFO_8822C 0xfff
+#define BIT_MGQ_PKT_INFO_8822C(x) \
+ (((x) & BIT_MASK_MGQ_PKT_INFO_8822C) << BIT_SHIFT_MGQ_PKT_INFO_8822C)
+#define BITS_MGQ_PKT_INFO_8822C \
+ (BIT_MASK_MGQ_PKT_INFO_8822C << BIT_SHIFT_MGQ_PKT_INFO_8822C)
+#define BIT_CLEAR_MGQ_PKT_INFO_8822C(x) ((x) & (~BITS_MGQ_PKT_INFO_8822C))
+#define BIT_GET_MGQ_PKT_INFO_8822C(x) \
+ (((x) >> BIT_SHIFT_MGQ_PKT_INFO_8822C) & BIT_MASK_MGQ_PKT_INFO_8822C)
+#define BIT_SET_MGQ_PKT_INFO_8822C(x, v) \
+ (BIT_CLEAR_MGQ_PKT_INFO_8822C(x) | BIT_MGQ_PKT_INFO_8822C(v))
+
+/* 2 REG_CMDQ_BCNQ_INFO_8822C */
+
+#define BIT_SHIFT_CMDQ_PKT_INFO_8822C 16
+#define BIT_MASK_CMDQ_PKT_INFO_8822C 0xfff
+#define BIT_CMDQ_PKT_INFO_8822C(x) \
+ (((x) & BIT_MASK_CMDQ_PKT_INFO_8822C) << BIT_SHIFT_CMDQ_PKT_INFO_8822C)
+#define BITS_CMDQ_PKT_INFO_8822C \
+ (BIT_MASK_CMDQ_PKT_INFO_8822C << BIT_SHIFT_CMDQ_PKT_INFO_8822C)
+#define BIT_CLEAR_CMDQ_PKT_INFO_8822C(x) ((x) & (~BITS_CMDQ_PKT_INFO_8822C))
+#define BIT_GET_CMDQ_PKT_INFO_8822C(x) \
+ (((x) >> BIT_SHIFT_CMDQ_PKT_INFO_8822C) & BIT_MASK_CMDQ_PKT_INFO_8822C)
+#define BIT_SET_CMDQ_PKT_INFO_8822C(x, v) \
+ (BIT_CLEAR_CMDQ_PKT_INFO_8822C(x) | BIT_CMDQ_PKT_INFO_8822C(v))
+
+#define BIT_SHIFT_BCNQ_PKT_INFO_8822C 0
+#define BIT_MASK_BCNQ_PKT_INFO_8822C 0xfff
+#define BIT_BCNQ_PKT_INFO_8822C(x) \
+ (((x) & BIT_MASK_BCNQ_PKT_INFO_8822C) << BIT_SHIFT_BCNQ_PKT_INFO_8822C)
+#define BITS_BCNQ_PKT_INFO_8822C \
+ (BIT_MASK_BCNQ_PKT_INFO_8822C << BIT_SHIFT_BCNQ_PKT_INFO_8822C)
+#define BIT_CLEAR_BCNQ_PKT_INFO_8822C(x) ((x) & (~BITS_BCNQ_PKT_INFO_8822C))
+#define BIT_GET_BCNQ_PKT_INFO_8822C(x) \
+ (((x) >> BIT_SHIFT_BCNQ_PKT_INFO_8822C) & BIT_MASK_BCNQ_PKT_INFO_8822C)
+#define BIT_SET_BCNQ_PKT_INFO_8822C(x, v) \
+ (BIT_CLEAR_BCNQ_PKT_INFO_8822C(x) | BIT_BCNQ_PKT_INFO_8822C(v))
+
+/* 2 REG_USEREG_SETTING_8822C */
+#define BIT_NDPA_USEREG_8822C BIT(21)
+
+#define BIT_SHIFT_RETRY_USEREG_8822C 19
+#define BIT_MASK_RETRY_USEREG_8822C 0x3
+#define BIT_RETRY_USEREG_8822C(x) \
+ (((x) & BIT_MASK_RETRY_USEREG_8822C) << BIT_SHIFT_RETRY_USEREG_8822C)
+#define BITS_RETRY_USEREG_8822C \
+ (BIT_MASK_RETRY_USEREG_8822C << BIT_SHIFT_RETRY_USEREG_8822C)
+#define BIT_CLEAR_RETRY_USEREG_8822C(x) ((x) & (~BITS_RETRY_USEREG_8822C))
+#define BIT_GET_RETRY_USEREG_8822C(x) \
+ (((x) >> BIT_SHIFT_RETRY_USEREG_8822C) & BIT_MASK_RETRY_USEREG_8822C)
+#define BIT_SET_RETRY_USEREG_8822C(x, v) \
+ (BIT_CLEAR_RETRY_USEREG_8822C(x) | BIT_RETRY_USEREG_8822C(v))
+
+#define BIT_SHIFT_TRYPKT_USEREG_8822C 17
+#define BIT_MASK_TRYPKT_USEREG_8822C 0x3
+#define BIT_TRYPKT_USEREG_8822C(x) \
+ (((x) & BIT_MASK_TRYPKT_USEREG_8822C) << BIT_SHIFT_TRYPKT_USEREG_8822C)
+#define BITS_TRYPKT_USEREG_8822C \
+ (BIT_MASK_TRYPKT_USEREG_8822C << BIT_SHIFT_TRYPKT_USEREG_8822C)
+#define BIT_CLEAR_TRYPKT_USEREG_8822C(x) ((x) & (~BITS_TRYPKT_USEREG_8822C))
+#define BIT_GET_TRYPKT_USEREG_8822C(x) \
+ (((x) >> BIT_SHIFT_TRYPKT_USEREG_8822C) & BIT_MASK_TRYPKT_USEREG_8822C)
+#define BIT_SET_TRYPKT_USEREG_8822C(x, v) \
+ (BIT_CLEAR_TRYPKT_USEREG_8822C(x) | BIT_TRYPKT_USEREG_8822C(v))
+
+#define BIT_CTLPKT_USEREG_8822C BIT(16)
+
+/* 2 REG_AESIV_SETTING_8822C */
+
+#define BIT_SHIFT_AESIV_OFFSET_8822C 0
+#define BIT_MASK_AESIV_OFFSET_8822C 0xfff
+#define BIT_AESIV_OFFSET_8822C(x) \
+ (((x) & BIT_MASK_AESIV_OFFSET_8822C) << BIT_SHIFT_AESIV_OFFSET_8822C)
+#define BITS_AESIV_OFFSET_8822C \
+ (BIT_MASK_AESIV_OFFSET_8822C << BIT_SHIFT_AESIV_OFFSET_8822C)
+#define BIT_CLEAR_AESIV_OFFSET_8822C(x) ((x) & (~BITS_AESIV_OFFSET_8822C))
+#define BIT_GET_AESIV_OFFSET_8822C(x) \
+ (((x) >> BIT_SHIFT_AESIV_OFFSET_8822C) & BIT_MASK_AESIV_OFFSET_8822C)
+#define BIT_SET_AESIV_OFFSET_8822C(x, v) \
+ (BIT_CLEAR_AESIV_OFFSET_8822C(x) | BIT_AESIV_OFFSET_8822C(v))
+
+/* 2 REG_BF0_TIME_SETTING_8822C */
+#define BIT_BF0_TIMER_SET_8822C BIT(31)
+#define BIT_BF0_TIMER_CLR_8822C BIT(30)
+#define BIT_BF0_UPDATE_EN_8822C BIT(29)
+#define BIT_BF0_TIMER_EN_8822C BIT(28)
+
+#define BIT_SHIFT_BF0_PRETIME_OVER_8822C 16
+#define BIT_MASK_BF0_PRETIME_OVER_8822C 0xfff
+#define BIT_BF0_PRETIME_OVER_8822C(x) \
+ (((x) & BIT_MASK_BF0_PRETIME_OVER_8822C) \
+ << BIT_SHIFT_BF0_PRETIME_OVER_8822C)
+#define BITS_BF0_PRETIME_OVER_8822C \
+ (BIT_MASK_BF0_PRETIME_OVER_8822C << BIT_SHIFT_BF0_PRETIME_OVER_8822C)
+#define BIT_CLEAR_BF0_PRETIME_OVER_8822C(x) \
+ ((x) & (~BITS_BF0_PRETIME_OVER_8822C))
+#define BIT_GET_BF0_PRETIME_OVER_8822C(x) \
+ (((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8822C) & \
+ BIT_MASK_BF0_PRETIME_OVER_8822C)
+#define BIT_SET_BF0_PRETIME_OVER_8822C(x, v) \
+ (BIT_CLEAR_BF0_PRETIME_OVER_8822C(x) | BIT_BF0_PRETIME_OVER_8822C(v))
+
+#define BIT_SHIFT_BF0_LIFETIME_8822C 0
+#define BIT_MASK_BF0_LIFETIME_8822C 0xffff
+#define BIT_BF0_LIFETIME_8822C(x) \
+ (((x) & BIT_MASK_BF0_LIFETIME_8822C) << BIT_SHIFT_BF0_LIFETIME_8822C)
+#define BITS_BF0_LIFETIME_8822C \
+ (BIT_MASK_BF0_LIFETIME_8822C << BIT_SHIFT_BF0_LIFETIME_8822C)
+#define BIT_CLEAR_BF0_LIFETIME_8822C(x) ((x) & (~BITS_BF0_LIFETIME_8822C))
+#define BIT_GET_BF0_LIFETIME_8822C(x) \
+ (((x) >> BIT_SHIFT_BF0_LIFETIME_8822C) & BIT_MASK_BF0_LIFETIME_8822C)
+#define BIT_SET_BF0_LIFETIME_8822C(x, v) \
+ (BIT_CLEAR_BF0_LIFETIME_8822C(x) | BIT_BF0_LIFETIME_8822C(v))
+
+/* 2 REG_BF1_TIME_SETTING_8822C */
+#define BIT_BF1_TIMER_SET_8822C BIT(31)
+#define BIT_BF1_TIMER_CLR_8822C BIT(30)
+#define BIT_BF1_UPDATE_EN_8822C BIT(29)
+#define BIT_BF1_TIMER_EN_8822C BIT(28)
+
+#define BIT_SHIFT_BF1_PRETIME_OVER_8822C 16
+#define BIT_MASK_BF1_PRETIME_OVER_8822C 0xfff
+#define BIT_BF1_PRETIME_OVER_8822C(x) \
+ (((x) & BIT_MASK_BF1_PRETIME_OVER_8822C) \
+ << BIT_SHIFT_BF1_PRETIME_OVER_8822C)
+#define BITS_BF1_PRETIME_OVER_8822C \
+ (BIT_MASK_BF1_PRETIME_OVER_8822C << BIT_SHIFT_BF1_PRETIME_OVER_8822C)
+#define BIT_CLEAR_BF1_PRETIME_OVER_8822C(x) \
+ ((x) & (~BITS_BF1_PRETIME_OVER_8822C))
+#define BIT_GET_BF1_PRETIME_OVER_8822C(x) \
+ (((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8822C) & \
+ BIT_MASK_BF1_PRETIME_OVER_8822C)
+#define BIT_SET_BF1_PRETIME_OVER_8822C(x, v) \
+ (BIT_CLEAR_BF1_PRETIME_OVER_8822C(x) | BIT_BF1_PRETIME_OVER_8822C(v))
+
+#define BIT_SHIFT_BF1_LIFETIME_8822C 0
+#define BIT_MASK_BF1_LIFETIME_8822C 0xffff
+#define BIT_BF1_LIFETIME_8822C(x) \
+ (((x) & BIT_MASK_BF1_LIFETIME_8822C) << BIT_SHIFT_BF1_LIFETIME_8822C)
+#define BITS_BF1_LIFETIME_8822C \
+ (BIT_MASK_BF1_LIFETIME_8822C << BIT_SHIFT_BF1_LIFETIME_8822C)
+#define BIT_CLEAR_BF1_LIFETIME_8822C(x) ((x) & (~BITS_BF1_LIFETIME_8822C))
+#define BIT_GET_BF1_LIFETIME_8822C(x) \
+ (((x) >> BIT_SHIFT_BF1_LIFETIME_8822C) & BIT_MASK_BF1_LIFETIME_8822C)
+#define BIT_SET_BF1_LIFETIME_8822C(x, v) \
+ (BIT_CLEAR_BF1_LIFETIME_8822C(x) | BIT_BF1_LIFETIME_8822C(v))
+
+/* 2 REG_BF_TIMEOUT_EN_8822C */
+#define BIT_EN_VHT_LDPC_8822C BIT(9)
+#define BIT_EN_HT_LDPC_8822C BIT(8)
+#define BIT_BF1_TIMEOUT_EN_8822C BIT(1)
+#define BIT_BF0_TIMEOUT_EN_8822C BIT(0)
+
+/* 2 REG_MACID_RELEASE0_8822C */
+
+#define BIT_SHIFT_MACID31_0_RELEASE_8822C 0
+#define BIT_MASK_MACID31_0_RELEASE_8822C 0xffffffffL
+#define BIT_MACID31_0_RELEASE_8822C(x) \
+ (((x) & BIT_MASK_MACID31_0_RELEASE_8822C) \
+ << BIT_SHIFT_MACID31_0_RELEASE_8822C)
+#define BITS_MACID31_0_RELEASE_8822C \
+ (BIT_MASK_MACID31_0_RELEASE_8822C << BIT_SHIFT_MACID31_0_RELEASE_8822C)
+#define BIT_CLEAR_MACID31_0_RELEASE_8822C(x) \
+ ((x) & (~BITS_MACID31_0_RELEASE_8822C))
+#define BIT_GET_MACID31_0_RELEASE_8822C(x) \
+ (((x) >> BIT_SHIFT_MACID31_0_RELEASE_8822C) & \
+ BIT_MASK_MACID31_0_RELEASE_8822C)
+#define BIT_SET_MACID31_0_RELEASE_8822C(x, v) \
+ (BIT_CLEAR_MACID31_0_RELEASE_8822C(x) | BIT_MACID31_0_RELEASE_8822C(v))
+
+/* 2 REG_MACID_RELEASE1_8822C */
+
+#define BIT_SHIFT_MACID63_32_RELEASE_8822C 0
+#define BIT_MASK_MACID63_32_RELEASE_8822C 0xffffffffL
+#define BIT_MACID63_32_RELEASE_8822C(x) \
+ (((x) & BIT_MASK_MACID63_32_RELEASE_8822C) \
+ << BIT_SHIFT_MACID63_32_RELEASE_8822C)
+#define BITS_MACID63_32_RELEASE_8822C \
+ (BIT_MASK_MACID63_32_RELEASE_8822C \
+ << BIT_SHIFT_MACID63_32_RELEASE_8822C)
+#define BIT_CLEAR_MACID63_32_RELEASE_8822C(x) \
+ ((x) & (~BITS_MACID63_32_RELEASE_8822C))
+#define BIT_GET_MACID63_32_RELEASE_8822C(x) \
+ (((x) >> BIT_SHIFT_MACID63_32_RELEASE_8822C) & \
+ BIT_MASK_MACID63_32_RELEASE_8822C)
+#define BIT_SET_MACID63_32_RELEASE_8822C(x, v) \
+ (BIT_CLEAR_MACID63_32_RELEASE_8822C(x) | \
+ BIT_MACID63_32_RELEASE_8822C(v))
+
+/* 2 REG_MACID_RELEASE2_8822C */
+
+#define BIT_SHIFT_MACID95_64_RELEASE_8822C 0
+#define BIT_MASK_MACID95_64_RELEASE_8822C 0xffffffffL
+#define BIT_MACID95_64_RELEASE_8822C(x) \
+ (((x) & BIT_MASK_MACID95_64_RELEASE_8822C) \
+ << BIT_SHIFT_MACID95_64_RELEASE_8822C)
+#define BITS_MACID95_64_RELEASE_8822C \
+ (BIT_MASK_MACID95_64_RELEASE_8822C \
+ << BIT_SHIFT_MACID95_64_RELEASE_8822C)
+#define BIT_CLEAR_MACID95_64_RELEASE_8822C(x) \
+ ((x) & (~BITS_MACID95_64_RELEASE_8822C))
+#define BIT_GET_MACID95_64_RELEASE_8822C(x) \
+ (((x) >> BIT_SHIFT_MACID95_64_RELEASE_8822C) & \
+ BIT_MASK_MACID95_64_RELEASE_8822C)
+#define BIT_SET_MACID95_64_RELEASE_8822C(x, v) \
+ (BIT_CLEAR_MACID95_64_RELEASE_8822C(x) | \
+ BIT_MACID95_64_RELEASE_8822C(v))
+
+/* 2 REG_MACID_RELEASE3_8822C */
+
+#define BIT_SHIFT_MACID127_96_RELEASE_8822C 0
+#define BIT_MASK_MACID127_96_RELEASE_8822C 0xffffffffL
+#define BIT_MACID127_96_RELEASE_8822C(x) \
+ (((x) & BIT_MASK_MACID127_96_RELEASE_8822C) \
+ << BIT_SHIFT_MACID127_96_RELEASE_8822C)
+#define BITS_MACID127_96_RELEASE_8822C \
+ (BIT_MASK_MACID127_96_RELEASE_8822C \
+ << BIT_SHIFT_MACID127_96_RELEASE_8822C)
+#define BIT_CLEAR_MACID127_96_RELEASE_8822C(x) \
+ ((x) & (~BITS_MACID127_96_RELEASE_8822C))
+#define BIT_GET_MACID127_96_RELEASE_8822C(x) \
+ (((x) >> BIT_SHIFT_MACID127_96_RELEASE_8822C) & \
+ BIT_MASK_MACID127_96_RELEASE_8822C)
+#define BIT_SET_MACID127_96_RELEASE_8822C(x, v) \
+ (BIT_CLEAR_MACID127_96_RELEASE_8822C(x) | \
+ BIT_MACID127_96_RELEASE_8822C(v))
+
+/* 2 REG_MACID_RELEASE_SETTING_8822C */
+#define BIT_MACID_VALUE_8822C BIT(7)
+
+#define BIT_SHIFT_MACID_OFFSET_8822C 0
+#define BIT_MASK_MACID_OFFSET_8822C 0x7f
+#define BIT_MACID_OFFSET_8822C(x) \
+ (((x) & BIT_MASK_MACID_OFFSET_8822C) << BIT_SHIFT_MACID_OFFSET_8822C)
+#define BITS_MACID_OFFSET_8822C \
+ (BIT_MASK_MACID_OFFSET_8822C << BIT_SHIFT_MACID_OFFSET_8822C)
+#define BIT_CLEAR_MACID_OFFSET_8822C(x) ((x) & (~BITS_MACID_OFFSET_8822C))
+#define BIT_GET_MACID_OFFSET_8822C(x) \
+ (((x) >> BIT_SHIFT_MACID_OFFSET_8822C) & BIT_MASK_MACID_OFFSET_8822C)
+#define BIT_SET_MACID_OFFSET_8822C(x, v) \
+ (BIT_CLEAR_MACID_OFFSET_8822C(x) | BIT_MACID_OFFSET_8822C(v))
+
+/* 2 REG_FAST_EDCA_VOVI_SETTING_8822C */
+
+#define BIT_SHIFT_VI_FAST_EDCA_TO_8822C 24
+#define BIT_MASK_VI_FAST_EDCA_TO_8822C 0xff
+#define BIT_VI_FAST_EDCA_TO_8822C(x) \
+ (((x) & BIT_MASK_VI_FAST_EDCA_TO_8822C) \
+ << BIT_SHIFT_VI_FAST_EDCA_TO_8822C)
+#define BITS_VI_FAST_EDCA_TO_8822C \
+ (BIT_MASK_VI_FAST_EDCA_TO_8822C << BIT_SHIFT_VI_FAST_EDCA_TO_8822C)
+#define BIT_CLEAR_VI_FAST_EDCA_TO_8822C(x) ((x) & (~BITS_VI_FAST_EDCA_TO_8822C))
+#define BIT_GET_VI_FAST_EDCA_TO_8822C(x) \
+ (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8822C) & \
+ BIT_MASK_VI_FAST_EDCA_TO_8822C)
+#define BIT_SET_VI_FAST_EDCA_TO_8822C(x, v) \
+ (BIT_CLEAR_VI_FAST_EDCA_TO_8822C(x) | BIT_VI_FAST_EDCA_TO_8822C(v))
+
+#define BIT_VI_THRESHOLD_SEL_8822C BIT(23)
+
+#define BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822C 16
+#define BIT_MASK_VI_FAST_EDCA_PKT_TH_8822C 0x7f
+#define BIT_VI_FAST_EDCA_PKT_TH_8822C(x) \
+ (((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8822C) \
+ << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822C)
+#define BITS_VI_FAST_EDCA_PKT_TH_8822C \
+ (BIT_MASK_VI_FAST_EDCA_PKT_TH_8822C \
+ << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822C)
+#define BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8822C(x) \
+ ((x) & (~BITS_VI_FAST_EDCA_PKT_TH_8822C))
+#define BIT_GET_VI_FAST_EDCA_PKT_TH_8822C(x) \
+ (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8822C) & \
+ BIT_MASK_VI_FAST_EDCA_PKT_TH_8822C)
+#define BIT_SET_VI_FAST_EDCA_PKT_TH_8822C(x, v) \
+ (BIT_CLEAR_VI_FAST_EDCA_PKT_TH_8822C(x) | \
+ BIT_VI_FAST_EDCA_PKT_TH_8822C(v))
+
+#define BIT_SHIFT_VO_FAST_EDCA_TO_8822C 8
+#define BIT_MASK_VO_FAST_EDCA_TO_8822C 0xff
+#define BIT_VO_FAST_EDCA_TO_8822C(x) \
+ (((x) & BIT_MASK_VO_FAST_EDCA_TO_8822C) \
+ << BIT_SHIFT_VO_FAST_EDCA_TO_8822C)
+#define BITS_VO_FAST_EDCA_TO_8822C \
+ (BIT_MASK_VO_FAST_EDCA_TO_8822C << BIT_SHIFT_VO_FAST_EDCA_TO_8822C)
+#define BIT_CLEAR_VO_FAST_EDCA_TO_8822C(x) ((x) & (~BITS_VO_FAST_EDCA_TO_8822C))
+#define BIT_GET_VO_FAST_EDCA_TO_8822C(x) \
+ (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8822C) & \
+ BIT_MASK_VO_FAST_EDCA_TO_8822C)
+#define BIT_SET_VO_FAST_EDCA_TO_8822C(x, v) \
+ (BIT_CLEAR_VO_FAST_EDCA_TO_8822C(x) | BIT_VO_FAST_EDCA_TO_8822C(v))
+
+#define BIT_VO_THRESHOLD_SEL_8822C BIT(7)
+
+#define BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822C 0
+#define BIT_MASK_VO_FAST_EDCA_PKT_TH_8822C 0x7f
+#define BIT_VO_FAST_EDCA_PKT_TH_8822C(x) \
+ (((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8822C) \
+ << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822C)
+#define BITS_VO_FAST_EDCA_PKT_TH_8822C \
+ (BIT_MASK_VO_FAST_EDCA_PKT_TH_8822C \
+ << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822C)
+#define BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8822C(x) \
+ ((x) & (~BITS_VO_FAST_EDCA_PKT_TH_8822C))
+#define BIT_GET_VO_FAST_EDCA_PKT_TH_8822C(x) \
+ (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8822C) & \
+ BIT_MASK_VO_FAST_EDCA_PKT_TH_8822C)
+#define BIT_SET_VO_FAST_EDCA_PKT_TH_8822C(x, v) \
+ (BIT_CLEAR_VO_FAST_EDCA_PKT_TH_8822C(x) | \
+ BIT_VO_FAST_EDCA_PKT_TH_8822C(v))
+
+/* 2 REG_FAST_EDCA_BEBK_SETTING_8822C */
+
+#define BIT_SHIFT_BK_FAST_EDCA_TO_8822C 24
+#define BIT_MASK_BK_FAST_EDCA_TO_8822C 0xff
+#define BIT_BK_FAST_EDCA_TO_8822C(x) \
+ (((x) & BIT_MASK_BK_FAST_EDCA_TO_8822C) \
+ << BIT_SHIFT_BK_FAST_EDCA_TO_8822C)
+#define BITS_BK_FAST_EDCA_TO_8822C \
+ (BIT_MASK_BK_FAST_EDCA_TO_8822C << BIT_SHIFT_BK_FAST_EDCA_TO_8822C)
+#define BIT_CLEAR_BK_FAST_EDCA_TO_8822C(x) ((x) & (~BITS_BK_FAST_EDCA_TO_8822C))
+#define BIT_GET_BK_FAST_EDCA_TO_8822C(x) \
+ (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8822C) & \
+ BIT_MASK_BK_FAST_EDCA_TO_8822C)
+#define BIT_SET_BK_FAST_EDCA_TO_8822C(x, v) \
+ (BIT_CLEAR_BK_FAST_EDCA_TO_8822C(x) | BIT_BK_FAST_EDCA_TO_8822C(v))
+
+#define BIT_BK_THRESHOLD_SEL_8822C BIT(23)
+
+#define BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822C 16
+#define BIT_MASK_BK_FAST_EDCA_PKT_TH_8822C 0x7f
+#define BIT_BK_FAST_EDCA_PKT_TH_8822C(x) \
+ (((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8822C) \
+ << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822C)
+#define BITS_BK_FAST_EDCA_PKT_TH_8822C \
+ (BIT_MASK_BK_FAST_EDCA_PKT_TH_8822C \
+ << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822C)
+#define BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8822C(x) \
+ ((x) & (~BITS_BK_FAST_EDCA_PKT_TH_8822C))
+#define BIT_GET_BK_FAST_EDCA_PKT_TH_8822C(x) \
+ (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8822C) & \
+ BIT_MASK_BK_FAST_EDCA_PKT_TH_8822C)
+#define BIT_SET_BK_FAST_EDCA_PKT_TH_8822C(x, v) \
+ (BIT_CLEAR_BK_FAST_EDCA_PKT_TH_8822C(x) | \
+ BIT_BK_FAST_EDCA_PKT_TH_8822C(v))
+
+#define BIT_SHIFT_BE_FAST_EDCA_TO_8822C 8
+#define BIT_MASK_BE_FAST_EDCA_TO_8822C 0xff
+#define BIT_BE_FAST_EDCA_TO_8822C(x) \
+ (((x) & BIT_MASK_BE_FAST_EDCA_TO_8822C) \
+ << BIT_SHIFT_BE_FAST_EDCA_TO_8822C)
+#define BITS_BE_FAST_EDCA_TO_8822C \
+ (BIT_MASK_BE_FAST_EDCA_TO_8822C << BIT_SHIFT_BE_FAST_EDCA_TO_8822C)
+#define BIT_CLEAR_BE_FAST_EDCA_TO_8822C(x) ((x) & (~BITS_BE_FAST_EDCA_TO_8822C))
+#define BIT_GET_BE_FAST_EDCA_TO_8822C(x) \
+ (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8822C) & \
+ BIT_MASK_BE_FAST_EDCA_TO_8822C)
+#define BIT_SET_BE_FAST_EDCA_TO_8822C(x, v) \
+ (BIT_CLEAR_BE_FAST_EDCA_TO_8822C(x) | BIT_BE_FAST_EDCA_TO_8822C(v))
+
+#define BIT_BE_THRESHOLD_SEL_8822C BIT(7)
+
+#define BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822C 0
+#define BIT_MASK_BE_FAST_EDCA_PKT_TH_8822C 0x7f
+#define BIT_BE_FAST_EDCA_PKT_TH_8822C(x) \
+ (((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8822C) \
+ << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822C)
+#define BITS_BE_FAST_EDCA_PKT_TH_8822C \
+ (BIT_MASK_BE_FAST_EDCA_PKT_TH_8822C \
+ << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822C)
+#define BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8822C(x) \
+ ((x) & (~BITS_BE_FAST_EDCA_PKT_TH_8822C))
+#define BIT_GET_BE_FAST_EDCA_PKT_TH_8822C(x) \
+ (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8822C) & \
+ BIT_MASK_BE_FAST_EDCA_PKT_TH_8822C)
+#define BIT_SET_BE_FAST_EDCA_PKT_TH_8822C(x, v) \
+ (BIT_CLEAR_BE_FAST_EDCA_PKT_TH_8822C(x) | \
+ BIT_BE_FAST_EDCA_PKT_TH_8822C(v))
+
+/* 2 REG_MACID_DROP0_8822C */
+
+#define BIT_SHIFT_MACID31_0_DROP_8822C 0
+#define BIT_MASK_MACID31_0_DROP_8822C 0xffffffffL
+#define BIT_MACID31_0_DROP_8822C(x) \
+ (((x) & BIT_MASK_MACID31_0_DROP_8822C) \
+ << BIT_SHIFT_MACID31_0_DROP_8822C)
+#define BITS_MACID31_0_DROP_8822C \
+ (BIT_MASK_MACID31_0_DROP_8822C << BIT_SHIFT_MACID31_0_DROP_8822C)
+#define BIT_CLEAR_MACID31_0_DROP_8822C(x) ((x) & (~BITS_MACID31_0_DROP_8822C))
+#define BIT_GET_MACID31_0_DROP_8822C(x) \
+ (((x) >> BIT_SHIFT_MACID31_0_DROP_8822C) & \
+ BIT_MASK_MACID31_0_DROP_8822C)
+#define BIT_SET_MACID31_0_DROP_8822C(x, v) \
+ (BIT_CLEAR_MACID31_0_DROP_8822C(x) | BIT_MACID31_0_DROP_8822C(v))
+
+/* 2 REG_MACID_DROP1_8822C */
+
+#define BIT_SHIFT_MACID63_32_DROP_8822C 0
+#define BIT_MASK_MACID63_32_DROP_8822C 0xffffffffL
+#define BIT_MACID63_32_DROP_8822C(x) \
+ (((x) & BIT_MASK_MACID63_32_DROP_8822C) \
+ << BIT_SHIFT_MACID63_32_DROP_8822C)
+#define BITS_MACID63_32_DROP_8822C \
+ (BIT_MASK_MACID63_32_DROP_8822C << BIT_SHIFT_MACID63_32_DROP_8822C)
+#define BIT_CLEAR_MACID63_32_DROP_8822C(x) ((x) & (~BITS_MACID63_32_DROP_8822C))
+#define BIT_GET_MACID63_32_DROP_8822C(x) \
+ (((x) >> BIT_SHIFT_MACID63_32_DROP_8822C) & \
+ BIT_MASK_MACID63_32_DROP_8822C)
+#define BIT_SET_MACID63_32_DROP_8822C(x, v) \
+ (BIT_CLEAR_MACID63_32_DROP_8822C(x) | BIT_MACID63_32_DROP_8822C(v))
+
+/* 2 REG_MACID_DROP2_8822C */
+
+#define BIT_SHIFT_MACID95_64_DROP_8822C 0
+#define BIT_MASK_MACID95_64_DROP_8822C 0xffffffffL
+#define BIT_MACID95_64_DROP_8822C(x) \
+ (((x) & BIT_MASK_MACID95_64_DROP_8822C) \
+ << BIT_SHIFT_MACID95_64_DROP_8822C)
+#define BITS_MACID95_64_DROP_8822C \
+ (BIT_MASK_MACID95_64_DROP_8822C << BIT_SHIFT_MACID95_64_DROP_8822C)
+#define BIT_CLEAR_MACID95_64_DROP_8822C(x) ((x) & (~BITS_MACID95_64_DROP_8822C))
+#define BIT_GET_MACID95_64_DROP_8822C(x) \
+ (((x) >> BIT_SHIFT_MACID95_64_DROP_8822C) & \
+ BIT_MASK_MACID95_64_DROP_8822C)
+#define BIT_SET_MACID95_64_DROP_8822C(x, v) \
+ (BIT_CLEAR_MACID95_64_DROP_8822C(x) | BIT_MACID95_64_DROP_8822C(v))
+
+/* 2 REG_MACID_DROP3_8822C */
+
+#define BIT_SHIFT_MACID127_96_DROP_8822C 0
+#define BIT_MASK_MACID127_96_DROP_8822C 0xffffffffL
+#define BIT_MACID127_96_DROP_8822C(x) \
+ (((x) & BIT_MASK_MACID127_96_DROP_8822C) \
+ << BIT_SHIFT_MACID127_96_DROP_8822C)
+#define BITS_MACID127_96_DROP_8822C \
+ (BIT_MASK_MACID127_96_DROP_8822C << BIT_SHIFT_MACID127_96_DROP_8822C)
+#define BIT_CLEAR_MACID127_96_DROP_8822C(x) \
+ ((x) & (~BITS_MACID127_96_DROP_8822C))
+#define BIT_GET_MACID127_96_DROP_8822C(x) \
+ (((x) >> BIT_SHIFT_MACID127_96_DROP_8822C) & \
+ BIT_MASK_MACID127_96_DROP_8822C)
+#define BIT_SET_MACID127_96_DROP_8822C(x, v) \
+ (BIT_CLEAR_MACID127_96_DROP_8822C(x) | BIT_MACID127_96_DROP_8822C(v))
+
+/* 2 REG_R_MACID_RELEASE_SUCCESS_0_8822C */
+
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822C 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822C 0xffffffffL
+#define BIT_R_MACID_RELEASE_SUCCESS_0_8822C(x) \
+ (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822C) \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822C)
+#define BITS_R_MACID_RELEASE_SUCCESS_0_8822C \
+ (BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822C \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822C)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8822C(x) \
+ ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_0_8822C))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_0_8822C(x) \
+ (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8822C) & \
+ BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8822C)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_0_8822C(x, v) \
+ (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0_8822C(x) | \
+ BIT_R_MACID_RELEASE_SUCCESS_0_8822C(v))
+
+/* 2 REG_R_MACID_RELEASE_SUCCESS_1_8822C */
+
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822C 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822C 0xffffffffL
+#define BIT_R_MACID_RELEASE_SUCCESS_1_8822C(x) \
+ (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822C) \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822C)
+#define BITS_R_MACID_RELEASE_SUCCESS_1_8822C \
+ (BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822C \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822C)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8822C(x) \
+ ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_1_8822C))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_1_8822C(x) \
+ (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8822C) & \
+ BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8822C)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_1_8822C(x, v) \
+ (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1_8822C(x) | \
+ BIT_R_MACID_RELEASE_SUCCESS_1_8822C(v))
+
+/* 2 REG_R_MACID_RELEASE_SUCCESS_2_8822C */
+
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822C 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822C 0xffffffffL
+#define BIT_R_MACID_RELEASE_SUCCESS_2_8822C(x) \
+ (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822C) \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822C)
+#define BITS_R_MACID_RELEASE_SUCCESS_2_8822C \
+ (BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822C \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822C)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8822C(x) \
+ ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_2_8822C))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_2_8822C(x) \
+ (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8822C) & \
+ BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8822C)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_2_8822C(x, v) \
+ (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2_8822C(x) | \
+ BIT_R_MACID_RELEASE_SUCCESS_2_8822C(v))
+
+/* 2 REG_R_MACID_RELEASE_SUCCESS_3_8822C */
+
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822C 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822C 0xffffffffL
+#define BIT_R_MACID_RELEASE_SUCCESS_3_8822C(x) \
+ (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822C) \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822C)
+#define BITS_R_MACID_RELEASE_SUCCESS_3_8822C \
+ (BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822C \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822C)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8822C(x) \
+ ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_3_8822C))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_3_8822C(x) \
+ (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8822C) & \
+ BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8822C)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_3_8822C(x, v) \
+ (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3_8822C(x) | \
+ BIT_R_MACID_RELEASE_SUCCESS_3_8822C(v))
+
+/* 2 REG_MGQ_FIFO_WRITE_POINTER_8822C */
+#define BIT_MGQ_FIFO_OV_8822C BIT(7)
+#define BIT_MGQ_FIFO_WPTR_ERROR_8822C BIT(6)
+#define BIT_EN_MGQ_FIFO_LIFETIME_8822C BIT(5)
+
+#define BIT_SHIFT_MGQ_FIFO_WPTR_8822C 0
+#define BIT_MASK_MGQ_FIFO_WPTR_8822C 0x1f
+#define BIT_MGQ_FIFO_WPTR_8822C(x) \
+ (((x) & BIT_MASK_MGQ_FIFO_WPTR_8822C) << BIT_SHIFT_MGQ_FIFO_WPTR_8822C)
+#define BITS_MGQ_FIFO_WPTR_8822C \
+ (BIT_MASK_MGQ_FIFO_WPTR_8822C << BIT_SHIFT_MGQ_FIFO_WPTR_8822C)
+#define BIT_CLEAR_MGQ_FIFO_WPTR_8822C(x) ((x) & (~BITS_MGQ_FIFO_WPTR_8822C))
+#define BIT_GET_MGQ_FIFO_WPTR_8822C(x) \
+ (((x) >> BIT_SHIFT_MGQ_FIFO_WPTR_8822C) & BIT_MASK_MGQ_FIFO_WPTR_8822C)
+#define BIT_SET_MGQ_FIFO_WPTR_8822C(x, v) \
+ (BIT_CLEAR_MGQ_FIFO_WPTR_8822C(x) | BIT_MGQ_FIFO_WPTR_8822C(v))
+
+/* 2 REG_MGQ_FIFO_READ_POINTER_8822C */
+
+#define BIT_SHIFT_MGQ_FIFO_SIZE_8822C 14
+#define BIT_MASK_MGQ_FIFO_SIZE_8822C 0x3
+#define BIT_MGQ_FIFO_SIZE_8822C(x) \
+ (((x) & BIT_MASK_MGQ_FIFO_SIZE_8822C) << BIT_SHIFT_MGQ_FIFO_SIZE_8822C)
+#define BITS_MGQ_FIFO_SIZE_8822C \
+ (BIT_MASK_MGQ_FIFO_SIZE_8822C << BIT_SHIFT_MGQ_FIFO_SIZE_8822C)
+#define BIT_CLEAR_MGQ_FIFO_SIZE_8822C(x) ((x) & (~BITS_MGQ_FIFO_SIZE_8822C))
+#define BIT_GET_MGQ_FIFO_SIZE_8822C(x) \
+ (((x) >> BIT_SHIFT_MGQ_FIFO_SIZE_8822C) & BIT_MASK_MGQ_FIFO_SIZE_8822C)
+#define BIT_SET_MGQ_FIFO_SIZE_8822C(x, v) \
+ (BIT_CLEAR_MGQ_FIFO_SIZE_8822C(x) | BIT_MGQ_FIFO_SIZE_8822C(v))
+
+#define BIT_MGQ_FIFO_PAUSE_8822C BIT(13)
+
+#define BIT_SHIFT_MGQ_FIFO_RPTR_8822C 8
+#define BIT_MASK_MGQ_FIFO_RPTR_8822C 0x1f
+#define BIT_MGQ_FIFO_RPTR_8822C(x) \
+ (((x) & BIT_MASK_MGQ_FIFO_RPTR_8822C) << BIT_SHIFT_MGQ_FIFO_RPTR_8822C)
+#define BITS_MGQ_FIFO_RPTR_8822C \
+ (BIT_MASK_MGQ_FIFO_RPTR_8822C << BIT_SHIFT_MGQ_FIFO_RPTR_8822C)
+#define BIT_CLEAR_MGQ_FIFO_RPTR_8822C(x) ((x) & (~BITS_MGQ_FIFO_RPTR_8822C))
+#define BIT_GET_MGQ_FIFO_RPTR_8822C(x) \
+ (((x) >> BIT_SHIFT_MGQ_FIFO_RPTR_8822C) & BIT_MASK_MGQ_FIFO_RPTR_8822C)
+#define BIT_SET_MGQ_FIFO_RPTR_8822C(x, v) \
+ (BIT_CLEAR_MGQ_FIFO_RPTR_8822C(x) | BIT_MGQ_FIFO_RPTR_8822C(v))
+
+/* 2 REG_MGQ_FIFO_ENABLE_8822C */
+#define BIT_MGQ_FIFO_EN_8822C BIT(15)
+
+#define BIT_SHIFT_MGQ_FIFO_PG_SIZE_8822C 12
+#define BIT_MASK_MGQ_FIFO_PG_SIZE_8822C 0x7
+#define BIT_MGQ_FIFO_PG_SIZE_8822C(x) \
+ (((x) & BIT_MASK_MGQ_FIFO_PG_SIZE_8822C) \
+ << BIT_SHIFT_MGQ_FIFO_PG_SIZE_8822C)
+#define BITS_MGQ_FIFO_PG_SIZE_8822C \
+ (BIT_MASK_MGQ_FIFO_PG_SIZE_8822C << BIT_SHIFT_MGQ_FIFO_PG_SIZE_8822C)
+#define BIT_CLEAR_MGQ_FIFO_PG_SIZE_8822C(x) \
+ ((x) & (~BITS_MGQ_FIFO_PG_SIZE_8822C))
+#define BIT_GET_MGQ_FIFO_PG_SIZE_8822C(x) \
+ (((x) >> BIT_SHIFT_MGQ_FIFO_PG_SIZE_8822C) & \
+ BIT_MASK_MGQ_FIFO_PG_SIZE_8822C)
+#define BIT_SET_MGQ_FIFO_PG_SIZE_8822C(x, v) \
+ (BIT_CLEAR_MGQ_FIFO_PG_SIZE_8822C(x) | BIT_MGQ_FIFO_PG_SIZE_8822C(v))
+
+#define BIT_SHIFT_MGQ_FIFO_START_PG_8822C 0
+#define BIT_MASK_MGQ_FIFO_START_PG_8822C 0xfff
+#define BIT_MGQ_FIFO_START_PG_8822C(x) \
+ (((x) & BIT_MASK_MGQ_FIFO_START_PG_8822C) \
+ << BIT_SHIFT_MGQ_FIFO_START_PG_8822C)
+#define BITS_MGQ_FIFO_START_PG_8822C \
+ (BIT_MASK_MGQ_FIFO_START_PG_8822C << BIT_SHIFT_MGQ_FIFO_START_PG_8822C)
+#define BIT_CLEAR_MGQ_FIFO_START_PG_8822C(x) \
+ ((x) & (~BITS_MGQ_FIFO_START_PG_8822C))
+#define BIT_GET_MGQ_FIFO_START_PG_8822C(x) \
+ (((x) >> BIT_SHIFT_MGQ_FIFO_START_PG_8822C) & \
+ BIT_MASK_MGQ_FIFO_START_PG_8822C)
+#define BIT_SET_MGQ_FIFO_START_PG_8822C(x, v) \
+ (BIT_CLEAR_MGQ_FIFO_START_PG_8822C(x) | BIT_MGQ_FIFO_START_PG_8822C(v))
+
+/* 2 REG_MGQ_FIFO_RELEASE_INT_MASK_8822C */
+
+#define BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8822C 0
+#define BIT_MASK_MGQ_FIFO_REL_INT_MASK_8822C 0xffff
+#define BIT_MGQ_FIFO_REL_INT_MASK_8822C(x) \
+ (((x) & BIT_MASK_MGQ_FIFO_REL_INT_MASK_8822C) \
+ << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8822C)
+#define BITS_MGQ_FIFO_REL_INT_MASK_8822C \
+ (BIT_MASK_MGQ_FIFO_REL_INT_MASK_8822C \
+ << BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8822C)
+#define BIT_CLEAR_MGQ_FIFO_REL_INT_MASK_8822C(x) \
+ ((x) & (~BITS_MGQ_FIFO_REL_INT_MASK_8822C))
+#define BIT_GET_MGQ_FIFO_REL_INT_MASK_8822C(x) \
+ (((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_MASK_8822C) & \
+ BIT_MASK_MGQ_FIFO_REL_INT_MASK_8822C)
+#define BIT_SET_MGQ_FIFO_REL_INT_MASK_8822C(x, v) \
+ (BIT_CLEAR_MGQ_FIFO_REL_INT_MASK_8822C(x) | \
+ BIT_MGQ_FIFO_REL_INT_MASK_8822C(v))
+
+/* 2 REG_MGQ_FIFO_RELEASE_INT_FLAG_8822C */
+
+#define BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8822C 0
+#define BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8822C 0xffff
+#define BIT_MGQ_FIFO_REL_INT_FLAG_8822C(x) \
+ (((x) & BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8822C) \
+ << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8822C)
+#define BITS_MGQ_FIFO_REL_INT_FLAG_8822C \
+ (BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8822C \
+ << BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8822C)
+#define BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG_8822C(x) \
+ ((x) & (~BITS_MGQ_FIFO_REL_INT_FLAG_8822C))
+#define BIT_GET_MGQ_FIFO_REL_INT_FLAG_8822C(x) \
+ (((x) >> BIT_SHIFT_MGQ_FIFO_REL_INT_FLAG_8822C) & \
+ BIT_MASK_MGQ_FIFO_REL_INT_FLAG_8822C)
+#define BIT_SET_MGQ_FIFO_REL_INT_FLAG_8822C(x, v) \
+ (BIT_CLEAR_MGQ_FIFO_REL_INT_FLAG_8822C(x) | \
+ BIT_MGQ_FIFO_REL_INT_FLAG_8822C(v))
+
+/* 2 REG_MGQ_FIFO_VALID_MAP_8822C */
+
+#define BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8822C 0
+#define BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8822C 0xffff
+#define BIT_MGQ_FIFO_PKT_VALID_MAP_8822C(x) \
+ (((x) & BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8822C) \
+ << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8822C)
+#define BITS_MGQ_FIFO_PKT_VALID_MAP_8822C \
+ (BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8822C \
+ << BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8822C)
+#define BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP_8822C(x) \
+ ((x) & (~BITS_MGQ_FIFO_PKT_VALID_MAP_8822C))
+#define BIT_GET_MGQ_FIFO_PKT_VALID_MAP_8822C(x) \
+ (((x) >> BIT_SHIFT_MGQ_FIFO_PKT_VALID_MAP_8822C) & \
+ BIT_MASK_MGQ_FIFO_PKT_VALID_MAP_8822C)
+#define BIT_SET_MGQ_FIFO_PKT_VALID_MAP_8822C(x, v) \
+ (BIT_CLEAR_MGQ_FIFO_PKT_VALID_MAP_8822C(x) | \
+ BIT_MGQ_FIFO_PKT_VALID_MAP_8822C(v))
+
+/* 2 REG_MGQ_FIFO_LIFETIME_8822C */
+
+#define BIT_SHIFT_MGQ_FIFO_LIFETIME_8822C 0
+#define BIT_MASK_MGQ_FIFO_LIFETIME_8822C 0xffff
+#define BIT_MGQ_FIFO_LIFETIME_8822C(x) \
+ (((x) & BIT_MASK_MGQ_FIFO_LIFETIME_8822C) \
+ << BIT_SHIFT_MGQ_FIFO_LIFETIME_8822C)
+#define BITS_MGQ_FIFO_LIFETIME_8822C \
+ (BIT_MASK_MGQ_FIFO_LIFETIME_8822C << BIT_SHIFT_MGQ_FIFO_LIFETIME_8822C)
+#define BIT_CLEAR_MGQ_FIFO_LIFETIME_8822C(x) \
+ ((x) & (~BITS_MGQ_FIFO_LIFETIME_8822C))
+#define BIT_GET_MGQ_FIFO_LIFETIME_8822C(x) \
+ (((x) >> BIT_SHIFT_MGQ_FIFO_LIFETIME_8822C) & \
+ BIT_MASK_MGQ_FIFO_LIFETIME_8822C)
+#define BIT_SET_MGQ_FIFO_LIFETIME_8822C(x, v) \
+ (BIT_CLEAR_MGQ_FIFO_LIFETIME_8822C(x) | BIT_MGQ_FIFO_LIFETIME_8822C(v))
+
+/* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C */
+
+#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C 0
+#define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C 0x7f
+#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C(x) \
+ (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C) \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C)
+#define BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C \
+ (BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C \
+ << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C)
+#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C(x) \
+ ((x) & (~BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C))
+#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C(x) \
+ (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C) & \
+ BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C)
+#define BIT_SET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C(x, v) \
+ (BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C(x) | \
+ BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C(v))
+
+/* 2 REG_SHCUT_SETTING_8822C */
+
+/* 2 REG_SHCUT_LLC_ETH_TYPE0_8822C */
+
+/* 2 REG_SHCUT_LLC_ETH_TYPE1_8822C */
+
+/* 2 REG_SHCUT_LLC_OUI0_8822C */
+
+/* 2 REG_SHCUT_LLC_OUI1_8822C */
+
+/* 2 REG_SHCUT_LLC_OUI2_8822C */
+
+/* 2 REG_MU_TX_CTL_8822C */
+#define BIT_R_MU_P1_WAIT_STATE_EN_8822C BIT(16)
+
+#define BIT_SHIFT_R_MU_RL_8822C 12
+#define BIT_MASK_R_MU_RL_8822C 0xf
+#define BIT_R_MU_RL_8822C(x) \
+ (((x) & BIT_MASK_R_MU_RL_8822C) << BIT_SHIFT_R_MU_RL_8822C)
+#define BITS_R_MU_RL_8822C (BIT_MASK_R_MU_RL_8822C << BIT_SHIFT_R_MU_RL_8822C)
+#define BIT_CLEAR_R_MU_RL_8822C(x) ((x) & (~BITS_R_MU_RL_8822C))
+#define BIT_GET_R_MU_RL_8822C(x) \
+ (((x) >> BIT_SHIFT_R_MU_RL_8822C) & BIT_MASK_R_MU_RL_8822C)
+#define BIT_SET_R_MU_RL_8822C(x, v) \
+ (BIT_CLEAR_R_MU_RL_8822C(x) | BIT_R_MU_RL_8822C(v))
+
+#define BIT_R_FORCE_P1_RATEDOWN_8822C BIT(11)
+
+#define BIT_SHIFT_R_MU_TAB_SEL_8822C 8
+#define BIT_MASK_R_MU_TAB_SEL_8822C 0x7
+#define BIT_R_MU_TAB_SEL_8822C(x) \
+ (((x) & BIT_MASK_R_MU_TAB_SEL_8822C) << BIT_SHIFT_R_MU_TAB_SEL_8822C)
+#define BITS_R_MU_TAB_SEL_8822C \
+ (BIT_MASK_R_MU_TAB_SEL_8822C << BIT_SHIFT_R_MU_TAB_SEL_8822C)
+#define BIT_CLEAR_R_MU_TAB_SEL_8822C(x) ((x) & (~BITS_R_MU_TAB_SEL_8822C))
+#define BIT_GET_R_MU_TAB_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_R_MU_TAB_SEL_8822C) & BIT_MASK_R_MU_TAB_SEL_8822C)
+#define BIT_SET_R_MU_TAB_SEL_8822C(x, v) \
+ (BIT_CLEAR_R_MU_TAB_SEL_8822C(x) | BIT_R_MU_TAB_SEL_8822C(v))
+
+#define BIT_R_EN_MU_MIMO_8822C BIT(7)
+#define BIT_R_EN_REVERS_GTAB_8822C BIT(6)
+
+#define BIT_SHIFT_R_MU_TABLE_VALID_8822C 0
+#define BIT_MASK_R_MU_TABLE_VALID_8822C 0x3f
+#define BIT_R_MU_TABLE_VALID_8822C(x) \
+ (((x) & BIT_MASK_R_MU_TABLE_VALID_8822C) \
+ << BIT_SHIFT_R_MU_TABLE_VALID_8822C)
+#define BITS_R_MU_TABLE_VALID_8822C \
+ (BIT_MASK_R_MU_TABLE_VALID_8822C << BIT_SHIFT_R_MU_TABLE_VALID_8822C)
+#define BIT_CLEAR_R_MU_TABLE_VALID_8822C(x) \
+ ((x) & (~BITS_R_MU_TABLE_VALID_8822C))
+#define BIT_GET_R_MU_TABLE_VALID_8822C(x) \
+ (((x) >> BIT_SHIFT_R_MU_TABLE_VALID_8822C) & \
+ BIT_MASK_R_MU_TABLE_VALID_8822C)
+#define BIT_SET_R_MU_TABLE_VALID_8822C(x, v) \
+ (BIT_CLEAR_R_MU_TABLE_VALID_8822C(x) | BIT_R_MU_TABLE_VALID_8822C(v))
+
+/* 2 REG_MU_STA_GID_VLD_8822C */
+
+#define BIT_SHIFT_R_MU_STA_GTAB_VALID_8822C 0
+#define BIT_MASK_R_MU_STA_GTAB_VALID_8822C 0xffffffffL
+#define BIT_R_MU_STA_GTAB_VALID_8822C(x) \
+ (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8822C) \
+ << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822C)
+#define BITS_R_MU_STA_GTAB_VALID_8822C \
+ (BIT_MASK_R_MU_STA_GTAB_VALID_8822C \
+ << BIT_SHIFT_R_MU_STA_GTAB_VALID_8822C)
+#define BIT_CLEAR_R_MU_STA_GTAB_VALID_8822C(x) \
+ ((x) & (~BITS_R_MU_STA_GTAB_VALID_8822C))
+#define BIT_GET_R_MU_STA_GTAB_VALID_8822C(x) \
+ (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8822C) & \
+ BIT_MASK_R_MU_STA_GTAB_VALID_8822C)
+#define BIT_SET_R_MU_STA_GTAB_VALID_8822C(x, v) \
+ (BIT_CLEAR_R_MU_STA_GTAB_VALID_8822C(x) | \
+ BIT_R_MU_STA_GTAB_VALID_8822C(v))
+
+/* 2 REG_MU_STA_USER_POS_INFO_8822C */
+
+#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8822C 0
+#define BIT_MASK_R_MU_STA_GTAB_POSITION_L_8822C 0xffffffffL
+#define BIT_R_MU_STA_GTAB_POSITION_L_8822C(x) \
+ (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_L_8822C) \
+ << BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8822C)
+#define BITS_R_MU_STA_GTAB_POSITION_L_8822C \
+ (BIT_MASK_R_MU_STA_GTAB_POSITION_L_8822C \
+ << BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8822C)
+#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_L_8822C(x) \
+ ((x) & (~BITS_R_MU_STA_GTAB_POSITION_L_8822C))
+#define BIT_GET_R_MU_STA_GTAB_POSITION_L_8822C(x) \
+ (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_L_8822C) & \
+ BIT_MASK_R_MU_STA_GTAB_POSITION_L_8822C)
+#define BIT_SET_R_MU_STA_GTAB_POSITION_L_8822C(x, v) \
+ (BIT_CLEAR_R_MU_STA_GTAB_POSITION_L_8822C(x) | \
+ BIT_R_MU_STA_GTAB_POSITION_L_8822C(v))
+
+/* 2 REG_MU_STA_USER_POS_INFO_H_8822C */
+
+#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8822C 0
+#define BIT_MASK_R_MU_STA_GTAB_POSITION_H_8822C 0xffffffffL
+#define BIT_R_MU_STA_GTAB_POSITION_H_8822C(x) \
+ (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_H_8822C) \
+ << BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8822C)
+#define BITS_R_MU_STA_GTAB_POSITION_H_8822C \
+ (BIT_MASK_R_MU_STA_GTAB_POSITION_H_8822C \
+ << BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8822C)
+#define BIT_CLEAR_R_MU_STA_GTAB_POSITION_H_8822C(x) \
+ ((x) & (~BITS_R_MU_STA_GTAB_POSITION_H_8822C))
+#define BIT_GET_R_MU_STA_GTAB_POSITION_H_8822C(x) \
+ (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_H_8822C) & \
+ BIT_MASK_R_MU_STA_GTAB_POSITION_H_8822C)
+#define BIT_SET_R_MU_STA_GTAB_POSITION_H_8822C(x, v) \
+ (BIT_CLEAR_R_MU_STA_GTAB_POSITION_H_8822C(x) | \
+ BIT_R_MU_STA_GTAB_POSITION_H_8822C(v))
+
+/* 2 REG_CHNL_INFO_CTRL_8822C */
+#define BIT_CHNL_REF_RXNAV_8822C BIT(7)
+#define BIT_CHNL_REF_VBON_8822C BIT(6)
+#define BIT_CHNL_REF_EDCA_8822C BIT(5)
+#define BIT_CHNL_REF_CCA_8822C BIT(4)
+#define BIT_RST_CHNL_BUSY_8822C BIT(3)
+#define BIT_RST_CHNL_IDLE_8822C BIT(2)
+#define BIT_CHNL_INFO_RST_8822C BIT(1)
+#define BIT_ATM_AIRTIME_EN_8822C BIT(0)
+
+/* 2 REG_CHNL_IDLE_TIME_8822C */
+
+#define BIT_SHIFT_CHNL_IDLE_TIME_8822C 0
+#define BIT_MASK_CHNL_IDLE_TIME_8822C 0xffffffffL
+#define BIT_CHNL_IDLE_TIME_8822C(x) \
+ (((x) & BIT_MASK_CHNL_IDLE_TIME_8822C) \
+ << BIT_SHIFT_CHNL_IDLE_TIME_8822C)
+#define BITS_CHNL_IDLE_TIME_8822C \
+ (BIT_MASK_CHNL_IDLE_TIME_8822C << BIT_SHIFT_CHNL_IDLE_TIME_8822C)
+#define BIT_CLEAR_CHNL_IDLE_TIME_8822C(x) ((x) & (~BITS_CHNL_IDLE_TIME_8822C))
+#define BIT_GET_CHNL_IDLE_TIME_8822C(x) \
+ (((x) >> BIT_SHIFT_CHNL_IDLE_TIME_8822C) & \
+ BIT_MASK_CHNL_IDLE_TIME_8822C)
+#define BIT_SET_CHNL_IDLE_TIME_8822C(x, v) \
+ (BIT_CLEAR_CHNL_IDLE_TIME_8822C(x) | BIT_CHNL_IDLE_TIME_8822C(v))
+
+/* 2 REG_CHNL_BUSY_TIME_8822C */
+
+#define BIT_SHIFT_CHNL_BUSY_TIME_8822C 0
+#define BIT_MASK_CHNL_BUSY_TIME_8822C 0xffffffffL
+#define BIT_CHNL_BUSY_TIME_8822C(x) \
+ (((x) & BIT_MASK_CHNL_BUSY_TIME_8822C) \
+ << BIT_SHIFT_CHNL_BUSY_TIME_8822C)
+#define BITS_CHNL_BUSY_TIME_8822C \
+ (BIT_MASK_CHNL_BUSY_TIME_8822C << BIT_SHIFT_CHNL_BUSY_TIME_8822C)
+#define BIT_CLEAR_CHNL_BUSY_TIME_8822C(x) ((x) & (~BITS_CHNL_BUSY_TIME_8822C))
+#define BIT_GET_CHNL_BUSY_TIME_8822C(x) \
+ (((x) >> BIT_SHIFT_CHNL_BUSY_TIME_8822C) & \
+ BIT_MASK_CHNL_BUSY_TIME_8822C)
+#define BIT_SET_CHNL_BUSY_TIME_8822C(x, v) \
+ (BIT_CLEAR_CHNL_BUSY_TIME_8822C(x) | BIT_CHNL_BUSY_TIME_8822C(v))
+
+/* 2 REG_MU_TRX_DBG_CNT_V1_8822C */
+#define BIT_MU_DNGCNT_RST_8822C BIT(20)
+
+#define BIT_SHIFT_MU_DNGCNT_SEL_8822C 16
+#define BIT_MASK_MU_DNGCNT_SEL_8822C 0xf
+#define BIT_MU_DNGCNT_SEL_8822C(x) \
+ (((x) & BIT_MASK_MU_DNGCNT_SEL_8822C) << BIT_SHIFT_MU_DNGCNT_SEL_8822C)
+#define BITS_MU_DNGCNT_SEL_8822C \
+ (BIT_MASK_MU_DNGCNT_SEL_8822C << BIT_SHIFT_MU_DNGCNT_SEL_8822C)
+#define BIT_CLEAR_MU_DNGCNT_SEL_8822C(x) ((x) & (~BITS_MU_DNGCNT_SEL_8822C))
+#define BIT_GET_MU_DNGCNT_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_MU_DNGCNT_SEL_8822C) & BIT_MASK_MU_DNGCNT_SEL_8822C)
+#define BIT_SET_MU_DNGCNT_SEL_8822C(x, v) \
+ (BIT_CLEAR_MU_DNGCNT_SEL_8822C(x) | BIT_MU_DNGCNT_SEL_8822C(v))
+
+#define BIT_SHIFT_MU_DNGCNT_8822C 0
+#define BIT_MASK_MU_DNGCNT_8822C 0xffff
+#define BIT_MU_DNGCNT_8822C(x) \
+ (((x) & BIT_MASK_MU_DNGCNT_8822C) << BIT_SHIFT_MU_DNGCNT_8822C)
+#define BITS_MU_DNGCNT_8822C \
+ (BIT_MASK_MU_DNGCNT_8822C << BIT_SHIFT_MU_DNGCNT_8822C)
+#define BIT_CLEAR_MU_DNGCNT_8822C(x) ((x) & (~BITS_MU_DNGCNT_8822C))
+#define BIT_GET_MU_DNGCNT_8822C(x) \
+ (((x) >> BIT_SHIFT_MU_DNGCNT_8822C) & BIT_MASK_MU_DNGCNT_8822C)
+#define BIT_SET_MU_DNGCNT_8822C(x, v) \
+ (BIT_CLEAR_MU_DNGCNT_8822C(x) | BIT_MU_DNGCNT_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_EDCA_VO_PARAM_8822C */
+
+#define BIT_SHIFT_TXOPLIMIT_8822C 16
+#define BIT_MASK_TXOPLIMIT_8822C 0x7ff
+#define BIT_TXOPLIMIT_8822C(x) \
+ (((x) & BIT_MASK_TXOPLIMIT_8822C) << BIT_SHIFT_TXOPLIMIT_8822C)
+#define BITS_TXOPLIMIT_8822C \
+ (BIT_MASK_TXOPLIMIT_8822C << BIT_SHIFT_TXOPLIMIT_8822C)
+#define BIT_CLEAR_TXOPLIMIT_8822C(x) ((x) & (~BITS_TXOPLIMIT_8822C))
+#define BIT_GET_TXOPLIMIT_8822C(x) \
+ (((x) >> BIT_SHIFT_TXOPLIMIT_8822C) & BIT_MASK_TXOPLIMIT_8822C)
+#define BIT_SET_TXOPLIMIT_8822C(x, v) \
+ (BIT_CLEAR_TXOPLIMIT_8822C(x) | BIT_TXOPLIMIT_8822C(v))
+
+#define BIT_SHIFT_CW_8822C 8
+#define BIT_MASK_CW_8822C 0xff
+#define BIT_CW_8822C(x) (((x) & BIT_MASK_CW_8822C) << BIT_SHIFT_CW_8822C)
+#define BITS_CW_8822C (BIT_MASK_CW_8822C << BIT_SHIFT_CW_8822C)
+#define BIT_CLEAR_CW_8822C(x) ((x) & (~BITS_CW_8822C))
+#define BIT_GET_CW_8822C(x) (((x) >> BIT_SHIFT_CW_8822C) & BIT_MASK_CW_8822C)
+#define BIT_SET_CW_8822C(x, v) (BIT_CLEAR_CW_8822C(x) | BIT_CW_8822C(v))
+
+#define BIT_SHIFT_AIFS_8822C 0
+#define BIT_MASK_AIFS_8822C 0xff
+#define BIT_AIFS_8822C(x) (((x) & BIT_MASK_AIFS_8822C) << BIT_SHIFT_AIFS_8822C)
+#define BITS_AIFS_8822C (BIT_MASK_AIFS_8822C << BIT_SHIFT_AIFS_8822C)
+#define BIT_CLEAR_AIFS_8822C(x) ((x) & (~BITS_AIFS_8822C))
+#define BIT_GET_AIFS_8822C(x) \
+ (((x) >> BIT_SHIFT_AIFS_8822C) & BIT_MASK_AIFS_8822C)
+#define BIT_SET_AIFS_8822C(x, v) (BIT_CLEAR_AIFS_8822C(x) | BIT_AIFS_8822C(v))
+
+/* 2 REG_EDCA_VI_PARAM_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_TXOPLIMIT_8822C 16
+#define BIT_MASK_TXOPLIMIT_8822C 0x7ff
+#define BIT_TXOPLIMIT_8822C(x) \
+ (((x) & BIT_MASK_TXOPLIMIT_8822C) << BIT_SHIFT_TXOPLIMIT_8822C)
+#define BITS_TXOPLIMIT_8822C \
+ (BIT_MASK_TXOPLIMIT_8822C << BIT_SHIFT_TXOPLIMIT_8822C)
+#define BIT_CLEAR_TXOPLIMIT_8822C(x) ((x) & (~BITS_TXOPLIMIT_8822C))
+#define BIT_GET_TXOPLIMIT_8822C(x) \
+ (((x) >> BIT_SHIFT_TXOPLIMIT_8822C) & BIT_MASK_TXOPLIMIT_8822C)
+#define BIT_SET_TXOPLIMIT_8822C(x, v) \
+ (BIT_CLEAR_TXOPLIMIT_8822C(x) | BIT_TXOPLIMIT_8822C(v))
+
+#define BIT_SHIFT_CW_8822C 8
+#define BIT_MASK_CW_8822C 0xff
+#define BIT_CW_8822C(x) (((x) & BIT_MASK_CW_8822C) << BIT_SHIFT_CW_8822C)
+#define BITS_CW_8822C (BIT_MASK_CW_8822C << BIT_SHIFT_CW_8822C)
+#define BIT_CLEAR_CW_8822C(x) ((x) & (~BITS_CW_8822C))
+#define BIT_GET_CW_8822C(x) (((x) >> BIT_SHIFT_CW_8822C) & BIT_MASK_CW_8822C)
+#define BIT_SET_CW_8822C(x, v) (BIT_CLEAR_CW_8822C(x) | BIT_CW_8822C(v))
+
+#define BIT_SHIFT_AIFS_8822C 0
+#define BIT_MASK_AIFS_8822C 0xff
+#define BIT_AIFS_8822C(x) (((x) & BIT_MASK_AIFS_8822C) << BIT_SHIFT_AIFS_8822C)
+#define BITS_AIFS_8822C (BIT_MASK_AIFS_8822C << BIT_SHIFT_AIFS_8822C)
+#define BIT_CLEAR_AIFS_8822C(x) ((x) & (~BITS_AIFS_8822C))
+#define BIT_GET_AIFS_8822C(x) \
+ (((x) >> BIT_SHIFT_AIFS_8822C) & BIT_MASK_AIFS_8822C)
+#define BIT_SET_AIFS_8822C(x, v) (BIT_CLEAR_AIFS_8822C(x) | BIT_AIFS_8822C(v))
+
+/* 2 REG_EDCA_BE_PARAM_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_TXOPLIMIT_8822C 16
+#define BIT_MASK_TXOPLIMIT_8822C 0x7ff
+#define BIT_TXOPLIMIT_8822C(x) \
+ (((x) & BIT_MASK_TXOPLIMIT_8822C) << BIT_SHIFT_TXOPLIMIT_8822C)
+#define BITS_TXOPLIMIT_8822C \
+ (BIT_MASK_TXOPLIMIT_8822C << BIT_SHIFT_TXOPLIMIT_8822C)
+#define BIT_CLEAR_TXOPLIMIT_8822C(x) ((x) & (~BITS_TXOPLIMIT_8822C))
+#define BIT_GET_TXOPLIMIT_8822C(x) \
+ (((x) >> BIT_SHIFT_TXOPLIMIT_8822C) & BIT_MASK_TXOPLIMIT_8822C)
+#define BIT_SET_TXOPLIMIT_8822C(x, v) \
+ (BIT_CLEAR_TXOPLIMIT_8822C(x) | BIT_TXOPLIMIT_8822C(v))
+
+#define BIT_SHIFT_CW_8822C 8
+#define BIT_MASK_CW_8822C 0xff
+#define BIT_CW_8822C(x) (((x) & BIT_MASK_CW_8822C) << BIT_SHIFT_CW_8822C)
+#define BITS_CW_8822C (BIT_MASK_CW_8822C << BIT_SHIFT_CW_8822C)
+#define BIT_CLEAR_CW_8822C(x) ((x) & (~BITS_CW_8822C))
+#define BIT_GET_CW_8822C(x) (((x) >> BIT_SHIFT_CW_8822C) & BIT_MASK_CW_8822C)
+#define BIT_SET_CW_8822C(x, v) (BIT_CLEAR_CW_8822C(x) | BIT_CW_8822C(v))
+
+#define BIT_SHIFT_AIFS_8822C 0
+#define BIT_MASK_AIFS_8822C 0xff
+#define BIT_AIFS_8822C(x) (((x) & BIT_MASK_AIFS_8822C) << BIT_SHIFT_AIFS_8822C)
+#define BITS_AIFS_8822C (BIT_MASK_AIFS_8822C << BIT_SHIFT_AIFS_8822C)
+#define BIT_CLEAR_AIFS_8822C(x) ((x) & (~BITS_AIFS_8822C))
+#define BIT_GET_AIFS_8822C(x) \
+ (((x) >> BIT_SHIFT_AIFS_8822C) & BIT_MASK_AIFS_8822C)
+#define BIT_SET_AIFS_8822C(x, v) (BIT_CLEAR_AIFS_8822C(x) | BIT_AIFS_8822C(v))
+
+/* 2 REG_EDCA_BK_PARAM_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_TXOPLIMIT_8822C 16
+#define BIT_MASK_TXOPLIMIT_8822C 0x7ff
+#define BIT_TXOPLIMIT_8822C(x) \
+ (((x) & BIT_MASK_TXOPLIMIT_8822C) << BIT_SHIFT_TXOPLIMIT_8822C)
+#define BITS_TXOPLIMIT_8822C \
+ (BIT_MASK_TXOPLIMIT_8822C << BIT_SHIFT_TXOPLIMIT_8822C)
+#define BIT_CLEAR_TXOPLIMIT_8822C(x) ((x) & (~BITS_TXOPLIMIT_8822C))
+#define BIT_GET_TXOPLIMIT_8822C(x) \
+ (((x) >> BIT_SHIFT_TXOPLIMIT_8822C) & BIT_MASK_TXOPLIMIT_8822C)
+#define BIT_SET_TXOPLIMIT_8822C(x, v) \
+ (BIT_CLEAR_TXOPLIMIT_8822C(x) | BIT_TXOPLIMIT_8822C(v))
+
+#define BIT_SHIFT_CW_8822C 8
+#define BIT_MASK_CW_8822C 0xff
+#define BIT_CW_8822C(x) (((x) & BIT_MASK_CW_8822C) << BIT_SHIFT_CW_8822C)
+#define BITS_CW_8822C (BIT_MASK_CW_8822C << BIT_SHIFT_CW_8822C)
+#define BIT_CLEAR_CW_8822C(x) ((x) & (~BITS_CW_8822C))
+#define BIT_GET_CW_8822C(x) (((x) >> BIT_SHIFT_CW_8822C) & BIT_MASK_CW_8822C)
+#define BIT_SET_CW_8822C(x, v) (BIT_CLEAR_CW_8822C(x) | BIT_CW_8822C(v))
+
+#define BIT_SHIFT_AIFS_8822C 0
+#define BIT_MASK_AIFS_8822C 0xff
+#define BIT_AIFS_8822C(x) (((x) & BIT_MASK_AIFS_8822C) << BIT_SHIFT_AIFS_8822C)
+#define BITS_AIFS_8822C (BIT_MASK_AIFS_8822C << BIT_SHIFT_AIFS_8822C)
+#define BIT_CLEAR_AIFS_8822C(x) ((x) & (~BITS_AIFS_8822C))
+#define BIT_GET_AIFS_8822C(x) \
+ (((x) >> BIT_SHIFT_AIFS_8822C) & BIT_MASK_AIFS_8822C)
+#define BIT_SET_AIFS_8822C(x, v) (BIT_CLEAR_AIFS_8822C(x) | BIT_AIFS_8822C(v))
+
+/* 2 REG_BCNTCFG_8822C */
+
+#define BIT_SHIFT_BCNCW_MAX_8822C 12
+#define BIT_MASK_BCNCW_MAX_8822C 0xf
+#define BIT_BCNCW_MAX_8822C(x) \
+ (((x) & BIT_MASK_BCNCW_MAX_8822C) << BIT_SHIFT_BCNCW_MAX_8822C)
+#define BITS_BCNCW_MAX_8822C \
+ (BIT_MASK_BCNCW_MAX_8822C << BIT_SHIFT_BCNCW_MAX_8822C)
+#define BIT_CLEAR_BCNCW_MAX_8822C(x) ((x) & (~BITS_BCNCW_MAX_8822C))
+#define BIT_GET_BCNCW_MAX_8822C(x) \
+ (((x) >> BIT_SHIFT_BCNCW_MAX_8822C) & BIT_MASK_BCNCW_MAX_8822C)
+#define BIT_SET_BCNCW_MAX_8822C(x, v) \
+ (BIT_CLEAR_BCNCW_MAX_8822C(x) | BIT_BCNCW_MAX_8822C(v))
+
+#define BIT_SHIFT_BCNCW_MIN_8822C 8
+#define BIT_MASK_BCNCW_MIN_8822C 0xf
+#define BIT_BCNCW_MIN_8822C(x) \
+ (((x) & BIT_MASK_BCNCW_MIN_8822C) << BIT_SHIFT_BCNCW_MIN_8822C)
+#define BITS_BCNCW_MIN_8822C \
+ (BIT_MASK_BCNCW_MIN_8822C << BIT_SHIFT_BCNCW_MIN_8822C)
+#define BIT_CLEAR_BCNCW_MIN_8822C(x) ((x) & (~BITS_BCNCW_MIN_8822C))
+#define BIT_GET_BCNCW_MIN_8822C(x) \
+ (((x) >> BIT_SHIFT_BCNCW_MIN_8822C) & BIT_MASK_BCNCW_MIN_8822C)
+#define BIT_SET_BCNCW_MIN_8822C(x, v) \
+ (BIT_CLEAR_BCNCW_MIN_8822C(x) | BIT_BCNCW_MIN_8822C(v))
+
+#define BIT_SHIFT_BCNIFS_8822C 0
+#define BIT_MASK_BCNIFS_8822C 0xff
+#define BIT_BCNIFS_8822C(x) \
+ (((x) & BIT_MASK_BCNIFS_8822C) << BIT_SHIFT_BCNIFS_8822C)
+#define BITS_BCNIFS_8822C (BIT_MASK_BCNIFS_8822C << BIT_SHIFT_BCNIFS_8822C)
+#define BIT_CLEAR_BCNIFS_8822C(x) ((x) & (~BITS_BCNIFS_8822C))
+#define BIT_GET_BCNIFS_8822C(x) \
+ (((x) >> BIT_SHIFT_BCNIFS_8822C) & BIT_MASK_BCNIFS_8822C)
+#define BIT_SET_BCNIFS_8822C(x, v) \
+ (BIT_CLEAR_BCNIFS_8822C(x) | BIT_BCNIFS_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_PIFS_8822C */
+
+#define BIT_SHIFT_PIFS_8822C 0
+#define BIT_MASK_PIFS_8822C 0xff
+#define BIT_PIFS_8822C(x) (((x) & BIT_MASK_PIFS_8822C) << BIT_SHIFT_PIFS_8822C)
+#define BITS_PIFS_8822C (BIT_MASK_PIFS_8822C << BIT_SHIFT_PIFS_8822C)
+#define BIT_CLEAR_PIFS_8822C(x) ((x) & (~BITS_PIFS_8822C))
+#define BIT_GET_PIFS_8822C(x) \
+ (((x) >> BIT_SHIFT_PIFS_8822C) & BIT_MASK_PIFS_8822C)
+#define BIT_SET_PIFS_8822C(x, v) (BIT_CLEAR_PIFS_8822C(x) | BIT_PIFS_8822C(v))
+
+/* 2 REG_RDG_PIFS_8822C */
+
+#define BIT_SHIFT_RDG_PIFS_8822C 0
+#define BIT_MASK_RDG_PIFS_8822C 0xff
+#define BIT_RDG_PIFS_8822C(x) \
+ (((x) & BIT_MASK_RDG_PIFS_8822C) << BIT_SHIFT_RDG_PIFS_8822C)
+#define BITS_RDG_PIFS_8822C \
+ (BIT_MASK_RDG_PIFS_8822C << BIT_SHIFT_RDG_PIFS_8822C)
+#define BIT_CLEAR_RDG_PIFS_8822C(x) ((x) & (~BITS_RDG_PIFS_8822C))
+#define BIT_GET_RDG_PIFS_8822C(x) \
+ (((x) >> BIT_SHIFT_RDG_PIFS_8822C) & BIT_MASK_RDG_PIFS_8822C)
+#define BIT_SET_RDG_PIFS_8822C(x, v) \
+ (BIT_CLEAR_RDG_PIFS_8822C(x) | BIT_RDG_PIFS_8822C(v))
+
+/* 2 REG_SIFS_8822C */
+
+#define BIT_SHIFT_SIFS_OFDM_TRX_8822C 24
+#define BIT_MASK_SIFS_OFDM_TRX_8822C 0xff
+#define BIT_SIFS_OFDM_TRX_8822C(x) \
+ (((x) & BIT_MASK_SIFS_OFDM_TRX_8822C) << BIT_SHIFT_SIFS_OFDM_TRX_8822C)
+#define BITS_SIFS_OFDM_TRX_8822C \
+ (BIT_MASK_SIFS_OFDM_TRX_8822C << BIT_SHIFT_SIFS_OFDM_TRX_8822C)
+#define BIT_CLEAR_SIFS_OFDM_TRX_8822C(x) ((x) & (~BITS_SIFS_OFDM_TRX_8822C))
+#define BIT_GET_SIFS_OFDM_TRX_8822C(x) \
+ (((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8822C) & BIT_MASK_SIFS_OFDM_TRX_8822C)
+#define BIT_SET_SIFS_OFDM_TRX_8822C(x, v) \
+ (BIT_CLEAR_SIFS_OFDM_TRX_8822C(x) | BIT_SIFS_OFDM_TRX_8822C(v))
+
+#define BIT_SHIFT_SIFS_CCK_TRX_8822C 16
+#define BIT_MASK_SIFS_CCK_TRX_8822C 0xff
+#define BIT_SIFS_CCK_TRX_8822C(x) \
+ (((x) & BIT_MASK_SIFS_CCK_TRX_8822C) << BIT_SHIFT_SIFS_CCK_TRX_8822C)
+#define BITS_SIFS_CCK_TRX_8822C \
+ (BIT_MASK_SIFS_CCK_TRX_8822C << BIT_SHIFT_SIFS_CCK_TRX_8822C)
+#define BIT_CLEAR_SIFS_CCK_TRX_8822C(x) ((x) & (~BITS_SIFS_CCK_TRX_8822C))
+#define BIT_GET_SIFS_CCK_TRX_8822C(x) \
+ (((x) >> BIT_SHIFT_SIFS_CCK_TRX_8822C) & BIT_MASK_SIFS_CCK_TRX_8822C)
+#define BIT_SET_SIFS_CCK_TRX_8822C(x, v) \
+ (BIT_CLEAR_SIFS_CCK_TRX_8822C(x) | BIT_SIFS_CCK_TRX_8822C(v))
+
+#define BIT_SHIFT_SIFS_OFDM_CTX_8822C 8
+#define BIT_MASK_SIFS_OFDM_CTX_8822C 0xff
+#define BIT_SIFS_OFDM_CTX_8822C(x) \
+ (((x) & BIT_MASK_SIFS_OFDM_CTX_8822C) << BIT_SHIFT_SIFS_OFDM_CTX_8822C)
+#define BITS_SIFS_OFDM_CTX_8822C \
+ (BIT_MASK_SIFS_OFDM_CTX_8822C << BIT_SHIFT_SIFS_OFDM_CTX_8822C)
+#define BIT_CLEAR_SIFS_OFDM_CTX_8822C(x) ((x) & (~BITS_SIFS_OFDM_CTX_8822C))
+#define BIT_GET_SIFS_OFDM_CTX_8822C(x) \
+ (((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8822C) & BIT_MASK_SIFS_OFDM_CTX_8822C)
+#define BIT_SET_SIFS_OFDM_CTX_8822C(x, v) \
+ (BIT_CLEAR_SIFS_OFDM_CTX_8822C(x) | BIT_SIFS_OFDM_CTX_8822C(v))
+
+#define BIT_SHIFT_SIFS_CCK_CTX_8822C 0
+#define BIT_MASK_SIFS_CCK_CTX_8822C 0xff
+#define BIT_SIFS_CCK_CTX_8822C(x) \
+ (((x) & BIT_MASK_SIFS_CCK_CTX_8822C) << BIT_SHIFT_SIFS_CCK_CTX_8822C)
+#define BITS_SIFS_CCK_CTX_8822C \
+ (BIT_MASK_SIFS_CCK_CTX_8822C << BIT_SHIFT_SIFS_CCK_CTX_8822C)
+#define BIT_CLEAR_SIFS_CCK_CTX_8822C(x) ((x) & (~BITS_SIFS_CCK_CTX_8822C))
+#define BIT_GET_SIFS_CCK_CTX_8822C(x) \
+ (((x) >> BIT_SHIFT_SIFS_CCK_CTX_8822C) & BIT_MASK_SIFS_CCK_CTX_8822C)
+#define BIT_SET_SIFS_CCK_CTX_8822C(x, v) \
+ (BIT_CLEAR_SIFS_CCK_CTX_8822C(x) | BIT_SIFS_CCK_CTX_8822C(v))
+
+/* 2 REG_TSFTR_SYN_OFFSET_8822C */
+
+#define BIT_SHIFT_TSFTR_SNC_OFFSET_8822C 0
+#define BIT_MASK_TSFTR_SNC_OFFSET_8822C 0xffff
+#define BIT_TSFTR_SNC_OFFSET_8822C(x) \
+ (((x) & BIT_MASK_TSFTR_SNC_OFFSET_8822C) \
+ << BIT_SHIFT_TSFTR_SNC_OFFSET_8822C)
+#define BITS_TSFTR_SNC_OFFSET_8822C \
+ (BIT_MASK_TSFTR_SNC_OFFSET_8822C << BIT_SHIFT_TSFTR_SNC_OFFSET_8822C)
+#define BIT_CLEAR_TSFTR_SNC_OFFSET_8822C(x) \
+ ((x) & (~BITS_TSFTR_SNC_OFFSET_8822C))
+#define BIT_GET_TSFTR_SNC_OFFSET_8822C(x) \
+ (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_8822C) & \
+ BIT_MASK_TSFTR_SNC_OFFSET_8822C)
+#define BIT_SET_TSFTR_SNC_OFFSET_8822C(x, v) \
+ (BIT_CLEAR_TSFTR_SNC_OFFSET_8822C(x) | BIT_TSFTR_SNC_OFFSET_8822C(v))
+
+/* 2 REG_AGGR_BREAK_TIME_8822C */
+
+#define BIT_SHIFT_AGGR_BK_TIME_8822C 0
+#define BIT_MASK_AGGR_BK_TIME_8822C 0xff
+#define BIT_AGGR_BK_TIME_8822C(x) \
+ (((x) & BIT_MASK_AGGR_BK_TIME_8822C) << BIT_SHIFT_AGGR_BK_TIME_8822C)
+#define BITS_AGGR_BK_TIME_8822C \
+ (BIT_MASK_AGGR_BK_TIME_8822C << BIT_SHIFT_AGGR_BK_TIME_8822C)
+#define BIT_CLEAR_AGGR_BK_TIME_8822C(x) ((x) & (~BITS_AGGR_BK_TIME_8822C))
+#define BIT_GET_AGGR_BK_TIME_8822C(x) \
+ (((x) >> BIT_SHIFT_AGGR_BK_TIME_8822C) & BIT_MASK_AGGR_BK_TIME_8822C)
+#define BIT_SET_AGGR_BK_TIME_8822C(x, v) \
+ (BIT_CLEAR_AGGR_BK_TIME_8822C(x) | BIT_AGGR_BK_TIME_8822C(v))
+
+/* 2 REG_SLOT_8822C */
+
+#define BIT_SHIFT_SLOT_8822C 0
+#define BIT_MASK_SLOT_8822C 0xff
+#define BIT_SLOT_8822C(x) (((x) & BIT_MASK_SLOT_8822C) << BIT_SHIFT_SLOT_8822C)
+#define BITS_SLOT_8822C (BIT_MASK_SLOT_8822C << BIT_SHIFT_SLOT_8822C)
+#define BIT_CLEAR_SLOT_8822C(x) ((x) & (~BITS_SLOT_8822C))
+#define BIT_GET_SLOT_8822C(x) \
+ (((x) >> BIT_SHIFT_SLOT_8822C) & BIT_MASK_SLOT_8822C)
+#define BIT_SET_SLOT_8822C(x, v) (BIT_CLEAR_SLOT_8822C(x) | BIT_SLOT_8822C(v))
+
+/* 2 REG_NOA_ON_ERLY_TIME_8822C */
+
+#define BIT_SHIFT__NOA_ON_ERLY_TIME_8822C 0
+#define BIT_MASK__NOA_ON_ERLY_TIME_8822C 0xff
+#define BIT__NOA_ON_ERLY_TIME_8822C(x) \
+ (((x) & BIT_MASK__NOA_ON_ERLY_TIME_8822C) \
+ << BIT_SHIFT__NOA_ON_ERLY_TIME_8822C)
+#define BITS__NOA_ON_ERLY_TIME_8822C \
+ (BIT_MASK__NOA_ON_ERLY_TIME_8822C << BIT_SHIFT__NOA_ON_ERLY_TIME_8822C)
+#define BIT_CLEAR__NOA_ON_ERLY_TIME_8822C(x) \
+ ((x) & (~BITS__NOA_ON_ERLY_TIME_8822C))
+#define BIT_GET__NOA_ON_ERLY_TIME_8822C(x) \
+ (((x) >> BIT_SHIFT__NOA_ON_ERLY_TIME_8822C) & \
+ BIT_MASK__NOA_ON_ERLY_TIME_8822C)
+#define BIT_SET__NOA_ON_ERLY_TIME_8822C(x, v) \
+ (BIT_CLEAR__NOA_ON_ERLY_TIME_8822C(x) | BIT__NOA_ON_ERLY_TIME_8822C(v))
+
+/* 2 REG_NOA_OFF_ERLY_TIME_8822C */
+
+#define BIT_SHIFT__NOA_OFF_ERLY_TIME_8822C 0
+#define BIT_MASK__NOA_OFF_ERLY_TIME_8822C 0xff
+#define BIT__NOA_OFF_ERLY_TIME_8822C(x) \
+ (((x) & BIT_MASK__NOA_OFF_ERLY_TIME_8822C) \
+ << BIT_SHIFT__NOA_OFF_ERLY_TIME_8822C)
+#define BITS__NOA_OFF_ERLY_TIME_8822C \
+ (BIT_MASK__NOA_OFF_ERLY_TIME_8822C \
+ << BIT_SHIFT__NOA_OFF_ERLY_TIME_8822C)
+#define BIT_CLEAR__NOA_OFF_ERLY_TIME_8822C(x) \
+ ((x) & (~BITS__NOA_OFF_ERLY_TIME_8822C))
+#define BIT_GET__NOA_OFF_ERLY_TIME_8822C(x) \
+ (((x) >> BIT_SHIFT__NOA_OFF_ERLY_TIME_8822C) & \
+ BIT_MASK__NOA_OFF_ERLY_TIME_8822C)
+#define BIT_SET__NOA_OFF_ERLY_TIME_8822C(x, v) \
+ (BIT_CLEAR__NOA_OFF_ERLY_TIME_8822C(x) | \
+ BIT__NOA_OFF_ERLY_TIME_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_TX_PTCL_CTRL_8822C */
+#define BIT_DIS_EDCCA_8822C BIT(15)
+#define BIT_DIS_CCA_8822C BIT(14)
+#define BIT_LSIG_TXOP_TXCMD_NAV_8822C BIT(13)
+#define BIT_SIFS_BK_EN_8822C BIT(12)
+
+#define BIT_SHIFT_TXQ_NAV_MSK_8822C 8
+#define BIT_MASK_TXQ_NAV_MSK_8822C 0xf
+#define BIT_TXQ_NAV_MSK_8822C(x) \
+ (((x) & BIT_MASK_TXQ_NAV_MSK_8822C) << BIT_SHIFT_TXQ_NAV_MSK_8822C)
+#define BITS_TXQ_NAV_MSK_8822C \
+ (BIT_MASK_TXQ_NAV_MSK_8822C << BIT_SHIFT_TXQ_NAV_MSK_8822C)
+#define BIT_CLEAR_TXQ_NAV_MSK_8822C(x) ((x) & (~BITS_TXQ_NAV_MSK_8822C))
+#define BIT_GET_TXQ_NAV_MSK_8822C(x) \
+ (((x) >> BIT_SHIFT_TXQ_NAV_MSK_8822C) & BIT_MASK_TXQ_NAV_MSK_8822C)
+#define BIT_SET_TXQ_NAV_MSK_8822C(x, v) \
+ (BIT_CLEAR_TXQ_NAV_MSK_8822C(x) | BIT_TXQ_NAV_MSK_8822C(v))
+
+#define BIT_DIS_CW_8822C BIT(7)
+#define BIT_NAV_END_TXOP_8822C BIT(6)
+#define BIT_RDG_END_TXOP_8822C BIT(5)
+#define BIT_AC_INBCN_HOLD_8822C BIT(4)
+#define BIT_MGTQ_TXOP_EN_8822C BIT(3)
+#define BIT_MGTQ_RTSMF_EN_8822C BIT(2)
+#define BIT_HIQ_RTSMF_EN_8822C BIT(1)
+#define BIT_BCN_RTSMF_EN_8822C BIT(0)
+
+/* 2 REG_TXPAUSE_8822C */
+#define BIT_STOP_BCN_HI_MGT_8822C BIT(7)
+#define BIT_MAC_STOPBCNQ_8822C BIT(6)
+#define BIT_MAC_STOPHIQ_8822C BIT(5)
+#define BIT_MAC_STOPMGQ_8822C BIT(4)
+#define BIT_MAC_STOPBK_8822C BIT(3)
+#define BIT_MAC_STOPBE_8822C BIT(2)
+#define BIT_MAC_STOPVI_8822C BIT(1)
+#define BIT_MAC_STOPVO_8822C BIT(0)
+
+/* 2 REG_DIS_TXREQ_CLR_8822C */
+#define BIT_DIS_BT_CCA_8822C BIT(7)
+#define BIT_DIS_TXREQ_CLR_HI_8822C BIT(5)
+#define BIT_DIS_TXREQ_CLR_MGQ_8822C BIT(4)
+#define BIT_DIS_TXREQ_CLR_VO_8822C BIT(3)
+#define BIT_DIS_TXREQ_CLR_VI_8822C BIT(2)
+#define BIT_DIS_TXREQ_CLR_BE_8822C BIT(1)
+#define BIT_DIS_TXREQ_CLR_BK_8822C BIT(0)
+
+/* 2 REG_RD_CTRL_8822C */
+#define BIT_EN_CLR_TXREQ_INCCA_8822C BIT(15)
+#define BIT_DIS_TX_OVER_BCNQ_8822C BIT(14)
+#define BIT_EN_BCNERR_INCCCA_8822C BIT(13)
+#define BIT_EDCCA_MSK_CNTDOWN_EN_8822C BIT(11)
+#define BIT_DIS_TXOP_CFE_8822C BIT(10)
+#define BIT_DIS_LSIG_CFE_8822C BIT(9)
+#define BIT_DIS_STBC_CFE_8822C BIT(8)
+#define BIT_BKQ_RD_INIT_EN_8822C BIT(7)
+#define BIT_BEQ_RD_INIT_EN_8822C BIT(6)
+#define BIT_VIQ_RD_INIT_EN_8822C BIT(5)
+#define BIT_VOQ_RD_INIT_EN_8822C BIT(4)
+#define BIT_BKQ_RD_RESP_EN_8822C BIT(3)
+#define BIT_BEQ_RD_RESP_EN_8822C BIT(2)
+#define BIT_VIQ_RD_RESP_EN_8822C BIT(1)
+#define BIT_VOQ_RD_RESP_EN_8822C BIT(0)
+
+/* 2 REG_MBSSID_CTRL_8822C */
+#define BIT_MBID_BCNQ7_EN_8822C BIT(7)
+#define BIT_MBID_BCNQ6_EN_8822C BIT(6)
+#define BIT_MBID_BCNQ5_EN_8822C BIT(5)
+#define BIT_MBID_BCNQ4_EN_8822C BIT(4)
+#define BIT_MBID_BCNQ3_EN_8822C BIT(3)
+#define BIT_MBID_BCNQ2_EN_8822C BIT(2)
+#define BIT_MBID_BCNQ1_EN_8822C BIT(1)
+#define BIT_MBID_BCNQ0_EN_8822C BIT(0)
+
+/* 2 REG_P2PPS_CTRL_8822C */
+#define BIT_P2P_CTW_ALLSTASLEEP_8822C BIT(7)
+#define BIT_P2P_OFF_DISTX_EN_8822C BIT(6)
+#define BIT_PWR_MGT_EN_8822C BIT(5)
+#define BIT_P2P_NOA1_EN_8822C BIT(2)
+#define BIT_P2P_NOA0_EN_8822C BIT(1)
+
+/* 2 REG_PKT_LIFETIME_CTRL_8822C */
+#define BIT_EN_P2P_CTWND1_8822C BIT(23)
+#define BIT_EN_BKF_CLR_TXREQ_8822C BIT(22)
+#define BIT_EN_TSFBIT32_RST_P2P_8822C BIT(21)
+#define BIT_EN_BCN_TX_BTCCA_8822C BIT(20)
+#define BIT_DIS_PKT_TX_ATIM_8822C BIT(19)
+#define BIT_DIS_BCN_DIS_CTN_8822C BIT(18)
+#define BIT_EN_NAVEND_RST_TXOP_8822C BIT(17)
+#define BIT_EN_FILTER_CCA_8822C BIT(16)
+
+#define BIT_SHIFT_CCA_FILTER_THRS_8822C 8
+#define BIT_MASK_CCA_FILTER_THRS_8822C 0xff
+#define BIT_CCA_FILTER_THRS_8822C(x) \
+ (((x) & BIT_MASK_CCA_FILTER_THRS_8822C) \
+ << BIT_SHIFT_CCA_FILTER_THRS_8822C)
+#define BITS_CCA_FILTER_THRS_8822C \
+ (BIT_MASK_CCA_FILTER_THRS_8822C << BIT_SHIFT_CCA_FILTER_THRS_8822C)
+#define BIT_CLEAR_CCA_FILTER_THRS_8822C(x) ((x) & (~BITS_CCA_FILTER_THRS_8822C))
+#define BIT_GET_CCA_FILTER_THRS_8822C(x) \
+ (((x) >> BIT_SHIFT_CCA_FILTER_THRS_8822C) & \
+ BIT_MASK_CCA_FILTER_THRS_8822C)
+#define BIT_SET_CCA_FILTER_THRS_8822C(x, v) \
+ (BIT_CLEAR_CCA_FILTER_THRS_8822C(x) | BIT_CCA_FILTER_THRS_8822C(v))
+
+#define BIT_SHIFT_EDCCA_THRS_8822C 0
+#define BIT_MASK_EDCCA_THRS_8822C 0xff
+#define BIT_EDCCA_THRS_8822C(x) \
+ (((x) & BIT_MASK_EDCCA_THRS_8822C) << BIT_SHIFT_EDCCA_THRS_8822C)
+#define BITS_EDCCA_THRS_8822C \
+ (BIT_MASK_EDCCA_THRS_8822C << BIT_SHIFT_EDCCA_THRS_8822C)
+#define BIT_CLEAR_EDCCA_THRS_8822C(x) ((x) & (~BITS_EDCCA_THRS_8822C))
+#define BIT_GET_EDCCA_THRS_8822C(x) \
+ (((x) >> BIT_SHIFT_EDCCA_THRS_8822C) & BIT_MASK_EDCCA_THRS_8822C)
+#define BIT_SET_EDCCA_THRS_8822C(x, v) \
+ (BIT_CLEAR_EDCCA_THRS_8822C(x) | BIT_EDCCA_THRS_8822C(v))
+
+/* 2 REG_P2PPS_SPEC_STATE_8822C */
+#define BIT_SPEC_POWER_STATE_8822C BIT(7)
+#define BIT_SPEC_CTWINDOW_ON_8822C BIT(6)
+#define BIT_SPEC_BEACON_AREA_ON_8822C BIT(5)
+#define BIT_SPEC_CTWIN_EARLY_DISTX_8822C BIT(4)
+#define BIT_SPEC_NOA1_OFF_PERIOD_8822C BIT(3)
+#define BIT_SPEC_FORCE_DOZE1_8822C BIT(2)
+#define BIT_SPEC_NOA0_OFF_PERIOD_8822C BIT(1)
+#define BIT_SPEC_FORCE_DOZE0_8822C BIT(0)
+
+/* 2 REG_TXOP_LIMIT_CTRL_8822C */
+
+#define BIT_SHIFT_TXOP_TBTT_CNT_8822C 24
+#define BIT_MASK_TXOP_TBTT_CNT_8822C 0xff
+#define BIT_TXOP_TBTT_CNT_8822C(x) \
+ (((x) & BIT_MASK_TXOP_TBTT_CNT_8822C) << BIT_SHIFT_TXOP_TBTT_CNT_8822C)
+#define BITS_TXOP_TBTT_CNT_8822C \
+ (BIT_MASK_TXOP_TBTT_CNT_8822C << BIT_SHIFT_TXOP_TBTT_CNT_8822C)
+#define BIT_CLEAR_TXOP_TBTT_CNT_8822C(x) ((x) & (~BITS_TXOP_TBTT_CNT_8822C))
+#define BIT_GET_TXOP_TBTT_CNT_8822C(x) \
+ (((x) >> BIT_SHIFT_TXOP_TBTT_CNT_8822C) & BIT_MASK_TXOP_TBTT_CNT_8822C)
+#define BIT_SET_TXOP_TBTT_CNT_8822C(x, v) \
+ (BIT_CLEAR_TXOP_TBTT_CNT_8822C(x) | BIT_TXOP_TBTT_CNT_8822C(v))
+
+#define BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822C 20
+#define BIT_MASK_TXOP_TBTT_CNT_SEL_8822C 0xf
+#define BIT_TXOP_TBTT_CNT_SEL_8822C(x) \
+ (((x) & BIT_MASK_TXOP_TBTT_CNT_SEL_8822C) \
+ << BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822C)
+#define BITS_TXOP_TBTT_CNT_SEL_8822C \
+ (BIT_MASK_TXOP_TBTT_CNT_SEL_8822C << BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822C)
+#define BIT_CLEAR_TXOP_TBTT_CNT_SEL_8822C(x) \
+ ((x) & (~BITS_TXOP_TBTT_CNT_SEL_8822C))
+#define BIT_GET_TXOP_TBTT_CNT_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_TXOP_TBTT_CNT_SEL_8822C) & \
+ BIT_MASK_TXOP_TBTT_CNT_SEL_8822C)
+#define BIT_SET_TXOP_TBTT_CNT_SEL_8822C(x, v) \
+ (BIT_CLEAR_TXOP_TBTT_CNT_SEL_8822C(x) | BIT_TXOP_TBTT_CNT_SEL_8822C(v))
+
+#define BIT_SHIFT_TXOP_LMT_EN_8822C 16
+#define BIT_MASK_TXOP_LMT_EN_8822C 0xf
+#define BIT_TXOP_LMT_EN_8822C(x) \
+ (((x) & BIT_MASK_TXOP_LMT_EN_8822C) << BIT_SHIFT_TXOP_LMT_EN_8822C)
+#define BITS_TXOP_LMT_EN_8822C \
+ (BIT_MASK_TXOP_LMT_EN_8822C << BIT_SHIFT_TXOP_LMT_EN_8822C)
+#define BIT_CLEAR_TXOP_LMT_EN_8822C(x) ((x) & (~BITS_TXOP_LMT_EN_8822C))
+#define BIT_GET_TXOP_LMT_EN_8822C(x) \
+ (((x) >> BIT_SHIFT_TXOP_LMT_EN_8822C) & BIT_MASK_TXOP_LMT_EN_8822C)
+#define BIT_SET_TXOP_LMT_EN_8822C(x, v) \
+ (BIT_CLEAR_TXOP_LMT_EN_8822C(x) | BIT_TXOP_LMT_EN_8822C(v))
+
+#define BIT_SHIFT_TXOP_LMT_TX_TIME_8822C 8
+#define BIT_MASK_TXOP_LMT_TX_TIME_8822C 0xff
+#define BIT_TXOP_LMT_TX_TIME_8822C(x) \
+ (((x) & BIT_MASK_TXOP_LMT_TX_TIME_8822C) \
+ << BIT_SHIFT_TXOP_LMT_TX_TIME_8822C)
+#define BITS_TXOP_LMT_TX_TIME_8822C \
+ (BIT_MASK_TXOP_LMT_TX_TIME_8822C << BIT_SHIFT_TXOP_LMT_TX_TIME_8822C)
+#define BIT_CLEAR_TXOP_LMT_TX_TIME_8822C(x) \
+ ((x) & (~BITS_TXOP_LMT_TX_TIME_8822C))
+#define BIT_GET_TXOP_LMT_TX_TIME_8822C(x) \
+ (((x) >> BIT_SHIFT_TXOP_LMT_TX_TIME_8822C) & \
+ BIT_MASK_TXOP_LMT_TX_TIME_8822C)
+#define BIT_SET_TXOP_LMT_TX_TIME_8822C(x, v) \
+ (BIT_CLEAR_TXOP_LMT_TX_TIME_8822C(x) | BIT_TXOP_LMT_TX_TIME_8822C(v))
+
+#define BIT_TXOP_CNT_TRIGGER_RESET_8822C BIT(7)
+
+#define BIT_SHIFT_TXOP_LMT_PKT_NUM_8822C 0
+#define BIT_MASK_TXOP_LMT_PKT_NUM_8822C 0x3f
+#define BIT_TXOP_LMT_PKT_NUM_8822C(x) \
+ (((x) & BIT_MASK_TXOP_LMT_PKT_NUM_8822C) \
+ << BIT_SHIFT_TXOP_LMT_PKT_NUM_8822C)
+#define BITS_TXOP_LMT_PKT_NUM_8822C \
+ (BIT_MASK_TXOP_LMT_PKT_NUM_8822C << BIT_SHIFT_TXOP_LMT_PKT_NUM_8822C)
+#define BIT_CLEAR_TXOP_LMT_PKT_NUM_8822C(x) \
+ ((x) & (~BITS_TXOP_LMT_PKT_NUM_8822C))
+#define BIT_GET_TXOP_LMT_PKT_NUM_8822C(x) \
+ (((x) >> BIT_SHIFT_TXOP_LMT_PKT_NUM_8822C) & \
+ BIT_MASK_TXOP_LMT_PKT_NUM_8822C)
+#define BIT_SET_TXOP_LMT_PKT_NUM_8822C(x, v) \
+ (BIT_CLEAR_TXOP_LMT_PKT_NUM_8822C(x) | BIT_TXOP_LMT_PKT_NUM_8822C(v))
+
+/* 2 REG_BAR_TX_CTRL_8822C */
+
+/* 2 REG_P2PON_DIS_TXTIME_8822C */
+
+#define BIT_SHIFT_P2PON_DIS_TXTIME_8822C 0
+#define BIT_MASK_P2PON_DIS_TXTIME_8822C 0xff
+#define BIT_P2PON_DIS_TXTIME_8822C(x) \
+ (((x) & BIT_MASK_P2PON_DIS_TXTIME_8822C) \
+ << BIT_SHIFT_P2PON_DIS_TXTIME_8822C)
+#define BITS_P2PON_DIS_TXTIME_8822C \
+ (BIT_MASK_P2PON_DIS_TXTIME_8822C << BIT_SHIFT_P2PON_DIS_TXTIME_8822C)
+#define BIT_CLEAR_P2PON_DIS_TXTIME_8822C(x) \
+ ((x) & (~BITS_P2PON_DIS_TXTIME_8822C))
+#define BIT_GET_P2PON_DIS_TXTIME_8822C(x) \
+ (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8822C) & \
+ BIT_MASK_P2PON_DIS_TXTIME_8822C)
+#define BIT_SET_P2PON_DIS_TXTIME_8822C(x, v) \
+ (BIT_CLEAR_P2PON_DIS_TXTIME_8822C(x) | BIT_P2PON_DIS_TXTIME_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_CCA_TXEN_CNT_8822C */
+#define BIT_CCA_TXEN_CNT_SWITCH_8822C BIT(17)
+#define BIT_CCA_TXEN_CNT_EN_8822C BIT(16)
+
+#define BIT_SHIFT_CCA_TXEN_BIG_CNT_8822C 8
+#define BIT_MASK_CCA_TXEN_BIG_CNT_8822C 0xff
+#define BIT_CCA_TXEN_BIG_CNT_8822C(x) \
+ (((x) & BIT_MASK_CCA_TXEN_BIG_CNT_8822C) \
+ << BIT_SHIFT_CCA_TXEN_BIG_CNT_8822C)
+#define BITS_CCA_TXEN_BIG_CNT_8822C \
+ (BIT_MASK_CCA_TXEN_BIG_CNT_8822C << BIT_SHIFT_CCA_TXEN_BIG_CNT_8822C)
+#define BIT_CLEAR_CCA_TXEN_BIG_CNT_8822C(x) \
+ ((x) & (~BITS_CCA_TXEN_BIG_CNT_8822C))
+#define BIT_GET_CCA_TXEN_BIG_CNT_8822C(x) \
+ (((x) >> BIT_SHIFT_CCA_TXEN_BIG_CNT_8822C) & \
+ BIT_MASK_CCA_TXEN_BIG_CNT_8822C)
+#define BIT_SET_CCA_TXEN_BIG_CNT_8822C(x, v) \
+ (BIT_CLEAR_CCA_TXEN_BIG_CNT_8822C(x) | BIT_CCA_TXEN_BIG_CNT_8822C(v))
+
+#define BIT_SHIFT_CCA_TXEN_SMALL_CNT_8822C 0
+#define BIT_MASK_CCA_TXEN_SMALL_CNT_8822C 0xff
+#define BIT_CCA_TXEN_SMALL_CNT_8822C(x) \
+ (((x) & BIT_MASK_CCA_TXEN_SMALL_CNT_8822C) \
+ << BIT_SHIFT_CCA_TXEN_SMALL_CNT_8822C)
+#define BITS_CCA_TXEN_SMALL_CNT_8822C \
+ (BIT_MASK_CCA_TXEN_SMALL_CNT_8822C \
+ << BIT_SHIFT_CCA_TXEN_SMALL_CNT_8822C)
+#define BIT_CLEAR_CCA_TXEN_SMALL_CNT_8822C(x) \
+ ((x) & (~BITS_CCA_TXEN_SMALL_CNT_8822C))
+#define BIT_GET_CCA_TXEN_SMALL_CNT_8822C(x) \
+ (((x) >> BIT_SHIFT_CCA_TXEN_SMALL_CNT_8822C) & \
+ BIT_MASK_CCA_TXEN_SMALL_CNT_8822C)
+#define BIT_SET_CCA_TXEN_SMALL_CNT_8822C(x, v) \
+ (BIT_CLEAR_CCA_TXEN_SMALL_CNT_8822C(x) | \
+ BIT_CCA_TXEN_SMALL_CNT_8822C(v))
+
+/* 2 REG_MAX_INTER_COLLISION_8822C */
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_BK_8822C 24
+#define BIT_MASK_MAX_INTER_COLLISION_BK_8822C 0xff
+#define BIT_MAX_INTER_COLLISION_BK_8822C(x) \
+ (((x) & BIT_MASK_MAX_INTER_COLLISION_BK_8822C) \
+ << BIT_SHIFT_MAX_INTER_COLLISION_BK_8822C)
+#define BITS_MAX_INTER_COLLISION_BK_8822C \
+ (BIT_MASK_MAX_INTER_COLLISION_BK_8822C \
+ << BIT_SHIFT_MAX_INTER_COLLISION_BK_8822C)
+#define BIT_CLEAR_MAX_INTER_COLLISION_BK_8822C(x) \
+ ((x) & (~BITS_MAX_INTER_COLLISION_BK_8822C))
+#define BIT_GET_MAX_INTER_COLLISION_BK_8822C(x) \
+ (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_BK_8822C) & \
+ BIT_MASK_MAX_INTER_COLLISION_BK_8822C)
+#define BIT_SET_MAX_INTER_COLLISION_BK_8822C(x, v) \
+ (BIT_CLEAR_MAX_INTER_COLLISION_BK_8822C(x) | \
+ BIT_MAX_INTER_COLLISION_BK_8822C(v))
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_BE_8822C 16
+#define BIT_MASK_MAX_INTER_COLLISION_BE_8822C 0xff
+#define BIT_MAX_INTER_COLLISION_BE_8822C(x) \
+ (((x) & BIT_MASK_MAX_INTER_COLLISION_BE_8822C) \
+ << BIT_SHIFT_MAX_INTER_COLLISION_BE_8822C)
+#define BITS_MAX_INTER_COLLISION_BE_8822C \
+ (BIT_MASK_MAX_INTER_COLLISION_BE_8822C \
+ << BIT_SHIFT_MAX_INTER_COLLISION_BE_8822C)
+#define BIT_CLEAR_MAX_INTER_COLLISION_BE_8822C(x) \
+ ((x) & (~BITS_MAX_INTER_COLLISION_BE_8822C))
+#define BIT_GET_MAX_INTER_COLLISION_BE_8822C(x) \
+ (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_BE_8822C) & \
+ BIT_MASK_MAX_INTER_COLLISION_BE_8822C)
+#define BIT_SET_MAX_INTER_COLLISION_BE_8822C(x, v) \
+ (BIT_CLEAR_MAX_INTER_COLLISION_BE_8822C(x) | \
+ BIT_MAX_INTER_COLLISION_BE_8822C(v))
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_VI_8822C 8
+#define BIT_MASK_MAX_INTER_COLLISION_VI_8822C 0xff
+#define BIT_MAX_INTER_COLLISION_VI_8822C(x) \
+ (((x) & BIT_MASK_MAX_INTER_COLLISION_VI_8822C) \
+ << BIT_SHIFT_MAX_INTER_COLLISION_VI_8822C)
+#define BITS_MAX_INTER_COLLISION_VI_8822C \
+ (BIT_MASK_MAX_INTER_COLLISION_VI_8822C \
+ << BIT_SHIFT_MAX_INTER_COLLISION_VI_8822C)
+#define BIT_CLEAR_MAX_INTER_COLLISION_VI_8822C(x) \
+ ((x) & (~BITS_MAX_INTER_COLLISION_VI_8822C))
+#define BIT_GET_MAX_INTER_COLLISION_VI_8822C(x) \
+ (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_VI_8822C) & \
+ BIT_MASK_MAX_INTER_COLLISION_VI_8822C)
+#define BIT_SET_MAX_INTER_COLLISION_VI_8822C(x, v) \
+ (BIT_CLEAR_MAX_INTER_COLLISION_VI_8822C(x) | \
+ BIT_MAX_INTER_COLLISION_VI_8822C(v))
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_VO_8822C 0
+#define BIT_MASK_MAX_INTER_COLLISION_VO_8822C 0xff
+#define BIT_MAX_INTER_COLLISION_VO_8822C(x) \
+ (((x) & BIT_MASK_MAX_INTER_COLLISION_VO_8822C) \
+ << BIT_SHIFT_MAX_INTER_COLLISION_VO_8822C)
+#define BITS_MAX_INTER_COLLISION_VO_8822C \
+ (BIT_MASK_MAX_INTER_COLLISION_VO_8822C \
+ << BIT_SHIFT_MAX_INTER_COLLISION_VO_8822C)
+#define BIT_CLEAR_MAX_INTER_COLLISION_VO_8822C(x) \
+ ((x) & (~BITS_MAX_INTER_COLLISION_VO_8822C))
+#define BIT_GET_MAX_INTER_COLLISION_VO_8822C(x) \
+ (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_VO_8822C) & \
+ BIT_MASK_MAX_INTER_COLLISION_VO_8822C)
+#define BIT_SET_MAX_INTER_COLLISION_VO_8822C(x, v) \
+ (BIT_CLEAR_MAX_INTER_COLLISION_VO_8822C(x) | \
+ BIT_MAX_INTER_COLLISION_VO_8822C(v))
+
+/* 2 REG_MAX_INTER_COLLISION_CNT_8822C */
+#define BIT_MAX_INTER_COLLISION_EN_8822C BIT(16)
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8822C 12
+#define BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8822C 0xf
+#define BIT_MAX_INTER_COLLISION_CNT_BK_8822C(x) \
+ (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8822C) \
+ << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8822C)
+#define BITS_MAX_INTER_COLLISION_CNT_BK_8822C \
+ (BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8822C \
+ << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8822C)
+#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_BK_8822C(x) \
+ ((x) & (~BITS_MAX_INTER_COLLISION_CNT_BK_8822C))
+#define BIT_GET_MAX_INTER_COLLISION_CNT_BK_8822C(x) \
+ (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_BK_8822C) & \
+ BIT_MASK_MAX_INTER_COLLISION_CNT_BK_8822C)
+#define BIT_SET_MAX_INTER_COLLISION_CNT_BK_8822C(x, v) \
+ (BIT_CLEAR_MAX_INTER_COLLISION_CNT_BK_8822C(x) | \
+ BIT_MAX_INTER_COLLISION_CNT_BK_8822C(v))
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8822C 8
+#define BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8822C 0xf
+#define BIT_MAX_INTER_COLLISION_CNT_BE_8822C(x) \
+ (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8822C) \
+ << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8822C)
+#define BITS_MAX_INTER_COLLISION_CNT_BE_8822C \
+ (BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8822C \
+ << BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8822C)
+#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_BE_8822C(x) \
+ ((x) & (~BITS_MAX_INTER_COLLISION_CNT_BE_8822C))
+#define BIT_GET_MAX_INTER_COLLISION_CNT_BE_8822C(x) \
+ (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_BE_8822C) & \
+ BIT_MASK_MAX_INTER_COLLISION_CNT_BE_8822C)
+#define BIT_SET_MAX_INTER_COLLISION_CNT_BE_8822C(x, v) \
+ (BIT_CLEAR_MAX_INTER_COLLISION_CNT_BE_8822C(x) | \
+ BIT_MAX_INTER_COLLISION_CNT_BE_8822C(v))
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8822C 4
+#define BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8822C 0xf
+#define BIT_MAX_INTER_COLLISION_CNT_VI_8822C(x) \
+ (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8822C) \
+ << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8822C)
+#define BITS_MAX_INTER_COLLISION_CNT_VI_8822C \
+ (BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8822C \
+ << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8822C)
+#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_VI_8822C(x) \
+ ((x) & (~BITS_MAX_INTER_COLLISION_CNT_VI_8822C))
+#define BIT_GET_MAX_INTER_COLLISION_CNT_VI_8822C(x) \
+ (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_VI_8822C) & \
+ BIT_MASK_MAX_INTER_COLLISION_CNT_VI_8822C)
+#define BIT_SET_MAX_INTER_COLLISION_CNT_VI_8822C(x, v) \
+ (BIT_CLEAR_MAX_INTER_COLLISION_CNT_VI_8822C(x) | \
+ BIT_MAX_INTER_COLLISION_CNT_VI_8822C(v))
+
+#define BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8822C 0
+#define BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8822C 0xf
+#define BIT_MAX_INTER_COLLISION_CNT_VO_8822C(x) \
+ (((x) & BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8822C) \
+ << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8822C)
+#define BITS_MAX_INTER_COLLISION_CNT_VO_8822C \
+ (BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8822C \
+ << BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8822C)
+#define BIT_CLEAR_MAX_INTER_COLLISION_CNT_VO_8822C(x) \
+ ((x) & (~BITS_MAX_INTER_COLLISION_CNT_VO_8822C))
+#define BIT_GET_MAX_INTER_COLLISION_CNT_VO_8822C(x) \
+ (((x) >> BIT_SHIFT_MAX_INTER_COLLISION_CNT_VO_8822C) & \
+ BIT_MASK_MAX_INTER_COLLISION_CNT_VO_8822C)
+#define BIT_SET_MAX_INTER_COLLISION_CNT_VO_8822C(x, v) \
+ (BIT_CLEAR_MAX_INTER_COLLISION_CNT_VO_8822C(x) | \
+ BIT_MAX_INTER_COLLISION_CNT_VO_8822C(v))
+
+/* 2 REG_TBTT_PROHIBIT_8822C */
+
+#define BIT_SHIFT_TBTT_HOLD_TIME_AP_8822C 8
+#define BIT_MASK_TBTT_HOLD_TIME_AP_8822C 0xfff
+#define BIT_TBTT_HOLD_TIME_AP_8822C(x) \
+ (((x) & BIT_MASK_TBTT_HOLD_TIME_AP_8822C) \
+ << BIT_SHIFT_TBTT_HOLD_TIME_AP_8822C)
+#define BITS_TBTT_HOLD_TIME_AP_8822C \
+ (BIT_MASK_TBTT_HOLD_TIME_AP_8822C << BIT_SHIFT_TBTT_HOLD_TIME_AP_8822C)
+#define BIT_CLEAR_TBTT_HOLD_TIME_AP_8822C(x) \
+ ((x) & (~BITS_TBTT_HOLD_TIME_AP_8822C))
+#define BIT_GET_TBTT_HOLD_TIME_AP_8822C(x) \
+ (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP_8822C) & \
+ BIT_MASK_TBTT_HOLD_TIME_AP_8822C)
+#define BIT_SET_TBTT_HOLD_TIME_AP_8822C(x, v) \
+ (BIT_CLEAR_TBTT_HOLD_TIME_AP_8822C(x) | BIT_TBTT_HOLD_TIME_AP_8822C(v))
+
+#define BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822C 0
+#define BIT_MASK_TBTT_PROHIBIT_SETUP_8822C 0xf
+#define BIT_TBTT_PROHIBIT_SETUP_8822C(x) \
+ (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8822C) \
+ << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822C)
+#define BITS_TBTT_PROHIBIT_SETUP_8822C \
+ (BIT_MASK_TBTT_PROHIBIT_SETUP_8822C \
+ << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822C)
+#define BIT_CLEAR_TBTT_PROHIBIT_SETUP_8822C(x) \
+ ((x) & (~BITS_TBTT_PROHIBIT_SETUP_8822C))
+#define BIT_GET_TBTT_PROHIBIT_SETUP_8822C(x) \
+ (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8822C) & \
+ BIT_MASK_TBTT_PROHIBIT_SETUP_8822C)
+#define BIT_SET_TBTT_PROHIBIT_SETUP_8822C(x, v) \
+ (BIT_CLEAR_TBTT_PROHIBIT_SETUP_8822C(x) | \
+ BIT_TBTT_PROHIBIT_SETUP_8822C(v))
+
+/* 2 REG_P2PPS_STATE_8822C */
+#define BIT_POWER_STATE_8822C BIT(7)
+#define BIT_CTWINDOW_ON_8822C BIT(6)
+#define BIT_BEACON_AREA_ON_8822C BIT(5)
+#define BIT_CTWIN_EARLY_DISTX_8822C BIT(4)
+#define BIT_NOA1_OFF_PERIOD_8822C BIT(3)
+#define BIT_FORCE_DOZE1_8822C BIT(2)
+#define BIT_NOA0_OFF_PERIOD_8822C BIT(1)
+#define BIT_FORCE_DOZE0_8822C BIT(0)
+
+/* 2 REG_RD_NAV_NXT_8822C */
+
+#define BIT_SHIFT_RD_NAV_PROT_NXT_8822C 0
+#define BIT_MASK_RD_NAV_PROT_NXT_8822C 0xffff
+#define BIT_RD_NAV_PROT_NXT_8822C(x) \
+ (((x) & BIT_MASK_RD_NAV_PROT_NXT_8822C) \
+ << BIT_SHIFT_RD_NAV_PROT_NXT_8822C)
+#define BITS_RD_NAV_PROT_NXT_8822C \
+ (BIT_MASK_RD_NAV_PROT_NXT_8822C << BIT_SHIFT_RD_NAV_PROT_NXT_8822C)
+#define BIT_CLEAR_RD_NAV_PROT_NXT_8822C(x) ((x) & (~BITS_RD_NAV_PROT_NXT_8822C))
+#define BIT_GET_RD_NAV_PROT_NXT_8822C(x) \
+ (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8822C) & \
+ BIT_MASK_RD_NAV_PROT_NXT_8822C)
+#define BIT_SET_RD_NAV_PROT_NXT_8822C(x, v) \
+ (BIT_CLEAR_RD_NAV_PROT_NXT_8822C(x) | BIT_RD_NAV_PROT_NXT_8822C(v))
+
+/* 2 REG_NAV_PROT_LEN_8822C */
+
+#define BIT_SHIFT_NAV_PROT_LEN_8822C 0
+#define BIT_MASK_NAV_PROT_LEN_8822C 0xffff
+#define BIT_NAV_PROT_LEN_8822C(x) \
+ (((x) & BIT_MASK_NAV_PROT_LEN_8822C) << BIT_SHIFT_NAV_PROT_LEN_8822C)
+#define BITS_NAV_PROT_LEN_8822C \
+ (BIT_MASK_NAV_PROT_LEN_8822C << BIT_SHIFT_NAV_PROT_LEN_8822C)
+#define BIT_CLEAR_NAV_PROT_LEN_8822C(x) ((x) & (~BITS_NAV_PROT_LEN_8822C))
+#define BIT_GET_NAV_PROT_LEN_8822C(x) \
+ (((x) >> BIT_SHIFT_NAV_PROT_LEN_8822C) & BIT_MASK_NAV_PROT_LEN_8822C)
+#define BIT_SET_NAV_PROT_LEN_8822C(x, v) \
+ (BIT_CLEAR_NAV_PROT_LEN_8822C(x) | BIT_NAV_PROT_LEN_8822C(v))
+
+/* 2 REG_FTM_PTT_8822C */
+
+#define BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8822C 22
+#define BIT_MASK_FTM_PTT_TSF_R2T_SEL_8822C 0x7
+#define BIT_FTM_PTT_TSF_R2T_SEL_8822C(x) \
+ (((x) & BIT_MASK_FTM_PTT_TSF_R2T_SEL_8822C) \
+ << BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8822C)
+#define BITS_FTM_PTT_TSF_R2T_SEL_8822C \
+ (BIT_MASK_FTM_PTT_TSF_R2T_SEL_8822C \
+ << BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8822C)
+#define BIT_CLEAR_FTM_PTT_TSF_R2T_SEL_8822C(x) \
+ ((x) & (~BITS_FTM_PTT_TSF_R2T_SEL_8822C))
+#define BIT_GET_FTM_PTT_TSF_R2T_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_FTM_PTT_TSF_R2T_SEL_8822C) & \
+ BIT_MASK_FTM_PTT_TSF_R2T_SEL_8822C)
+#define BIT_SET_FTM_PTT_TSF_R2T_SEL_8822C(x, v) \
+ (BIT_CLEAR_FTM_PTT_TSF_R2T_SEL_8822C(x) | \
+ BIT_FTM_PTT_TSF_R2T_SEL_8822C(v))
+
+#define BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8822C 19
+#define BIT_MASK_FTM_PTT_TSF_T2R_SEL_8822C 0x7
+#define BIT_FTM_PTT_TSF_T2R_SEL_8822C(x) \
+ (((x) & BIT_MASK_FTM_PTT_TSF_T2R_SEL_8822C) \
+ << BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8822C)
+#define BITS_FTM_PTT_TSF_T2R_SEL_8822C \
+ (BIT_MASK_FTM_PTT_TSF_T2R_SEL_8822C \
+ << BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8822C)
+#define BIT_CLEAR_FTM_PTT_TSF_T2R_SEL_8822C(x) \
+ ((x) & (~BITS_FTM_PTT_TSF_T2R_SEL_8822C))
+#define BIT_GET_FTM_PTT_TSF_T2R_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_FTM_PTT_TSF_T2R_SEL_8822C) & \
+ BIT_MASK_FTM_PTT_TSF_T2R_SEL_8822C)
+#define BIT_SET_FTM_PTT_TSF_T2R_SEL_8822C(x, v) \
+ (BIT_CLEAR_FTM_PTT_TSF_T2R_SEL_8822C(x) | \
+ BIT_FTM_PTT_TSF_T2R_SEL_8822C(v))
+
+#define BIT_SHIFT_FTM_PTT_TSF_SEL_8822C 16
+#define BIT_MASK_FTM_PTT_TSF_SEL_8822C 0x7
+#define BIT_FTM_PTT_TSF_SEL_8822C(x) \
+ (((x) & BIT_MASK_FTM_PTT_TSF_SEL_8822C) \
+ << BIT_SHIFT_FTM_PTT_TSF_SEL_8822C)
+#define BITS_FTM_PTT_TSF_SEL_8822C \
+ (BIT_MASK_FTM_PTT_TSF_SEL_8822C << BIT_SHIFT_FTM_PTT_TSF_SEL_8822C)
+#define BIT_CLEAR_FTM_PTT_TSF_SEL_8822C(x) ((x) & (~BITS_FTM_PTT_TSF_SEL_8822C))
+#define BIT_GET_FTM_PTT_TSF_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_FTM_PTT_TSF_SEL_8822C) & \
+ BIT_MASK_FTM_PTT_TSF_SEL_8822C)
+#define BIT_SET_FTM_PTT_TSF_SEL_8822C(x, v) \
+ (BIT_CLEAR_FTM_PTT_TSF_SEL_8822C(x) | BIT_FTM_PTT_TSF_SEL_8822C(v))
+
+#define BIT_SHIFT_FTM_PTT_VALUE_8822C 0
+#define BIT_MASK_FTM_PTT_VALUE_8822C 0xffff
+#define BIT_FTM_PTT_VALUE_8822C(x) \
+ (((x) & BIT_MASK_FTM_PTT_VALUE_8822C) << BIT_SHIFT_FTM_PTT_VALUE_8822C)
+#define BITS_FTM_PTT_VALUE_8822C \
+ (BIT_MASK_FTM_PTT_VALUE_8822C << BIT_SHIFT_FTM_PTT_VALUE_8822C)
+#define BIT_CLEAR_FTM_PTT_VALUE_8822C(x) ((x) & (~BITS_FTM_PTT_VALUE_8822C))
+#define BIT_GET_FTM_PTT_VALUE_8822C(x) \
+ (((x) >> BIT_SHIFT_FTM_PTT_VALUE_8822C) & BIT_MASK_FTM_PTT_VALUE_8822C)
+#define BIT_SET_FTM_PTT_VALUE_8822C(x, v) \
+ (BIT_CLEAR_FTM_PTT_VALUE_8822C(x) | BIT_FTM_PTT_VALUE_8822C(v))
+
+/* 2 REG_FTM_TSF_8822C */
+
+#define BIT_SHIFT_FTM_T2_TSF_8822C 16
+#define BIT_MASK_FTM_T2_TSF_8822C 0xffff
+#define BIT_FTM_T2_TSF_8822C(x) \
+ (((x) & BIT_MASK_FTM_T2_TSF_8822C) << BIT_SHIFT_FTM_T2_TSF_8822C)
+#define BITS_FTM_T2_TSF_8822C \
+ (BIT_MASK_FTM_T2_TSF_8822C << BIT_SHIFT_FTM_T2_TSF_8822C)
+#define BIT_CLEAR_FTM_T2_TSF_8822C(x) ((x) & (~BITS_FTM_T2_TSF_8822C))
+#define BIT_GET_FTM_T2_TSF_8822C(x) \
+ (((x) >> BIT_SHIFT_FTM_T2_TSF_8822C) & BIT_MASK_FTM_T2_TSF_8822C)
+#define BIT_SET_FTM_T2_TSF_8822C(x, v) \
+ (BIT_CLEAR_FTM_T2_TSF_8822C(x) | BIT_FTM_T2_TSF_8822C(v))
+
+#define BIT_SHIFT_FTM_T1_TSF_8822C 0
+#define BIT_MASK_FTM_T1_TSF_8822C 0xffff
+#define BIT_FTM_T1_TSF_8822C(x) \
+ (((x) & BIT_MASK_FTM_T1_TSF_8822C) << BIT_SHIFT_FTM_T1_TSF_8822C)
+#define BITS_FTM_T1_TSF_8822C \
+ (BIT_MASK_FTM_T1_TSF_8822C << BIT_SHIFT_FTM_T1_TSF_8822C)
+#define BIT_CLEAR_FTM_T1_TSF_8822C(x) ((x) & (~BITS_FTM_T1_TSF_8822C))
+#define BIT_GET_FTM_T1_TSF_8822C(x) \
+ (((x) >> BIT_SHIFT_FTM_T1_TSF_8822C) & BIT_MASK_FTM_T1_TSF_8822C)
+#define BIT_SET_FTM_T1_TSF_8822C(x, v) \
+ (BIT_CLEAR_FTM_T1_TSF_8822C(x) | BIT_FTM_T1_TSF_8822C(v))
+
+/* 2 REG_BCN_CTRL_8822C */
+#define BIT_DIS_RX_BSSID_FIT_8822C BIT(6)
+#define BIT_P0_EN_TXBCN_RPT_8822C BIT(5)
+#define BIT_DIS_TSF_UDT_8822C BIT(4)
+#define BIT_EN_BCN_FUNCTION_8822C BIT(3)
+#define BIT_P0_EN_RXBCN_RPT_8822C BIT(2)
+#define BIT_EN_P2P_CTWINDOW_8822C BIT(1)
+#define BIT_EN_P2P_BCNQ_AREA_8822C BIT(0)
+
+/* 2 REG_BCN_CTRL_CLINT0_8822C */
+#define BIT_CLI0_DIS_RX_BSSID_FIT_8822C BIT(6)
+#define BIT_CLI0_DIS_TSF_UDT_8822C BIT(4)
+#define BIT_CLI0_EN_BCN_FUNCTION_8822C BIT(3)
+#define BIT_CLI0_EN_RXBCN_RPT_8822C BIT(2)
+#define BIT_CLI0_ENP2P_CTWINDOW_8822C BIT(1)
+#define BIT_CLI0_ENP2P_BCNQ_AREA_8822C BIT(0)
+
+/* 2 REG_MBID_NUM_8822C */
+#define BIT_EN_PRE_DL_BEACON_8822C BIT(3)
+
+#define BIT_SHIFT_MBID_BCN_NUM_8822C 0
+#define BIT_MASK_MBID_BCN_NUM_8822C 0x7
+#define BIT_MBID_BCN_NUM_8822C(x) \
+ (((x) & BIT_MASK_MBID_BCN_NUM_8822C) << BIT_SHIFT_MBID_BCN_NUM_8822C)
+#define BITS_MBID_BCN_NUM_8822C \
+ (BIT_MASK_MBID_BCN_NUM_8822C << BIT_SHIFT_MBID_BCN_NUM_8822C)
+#define BIT_CLEAR_MBID_BCN_NUM_8822C(x) ((x) & (~BITS_MBID_BCN_NUM_8822C))
+#define BIT_GET_MBID_BCN_NUM_8822C(x) \
+ (((x) >> BIT_SHIFT_MBID_BCN_NUM_8822C) & BIT_MASK_MBID_BCN_NUM_8822C)
+#define BIT_SET_MBID_BCN_NUM_8822C(x, v) \
+ (BIT_CLEAR_MBID_BCN_NUM_8822C(x) | BIT_MBID_BCN_NUM_8822C(v))
+
+/* 2 REG_DUAL_TSF_RST_8822C */
+#define BIT_FREECNT_RST_8822C BIT(5)
+#define BIT_TSFTR_CLI3_RST_8822C BIT(4)
+#define BIT_TSFTR_CLI2_RST_8822C BIT(3)
+#define BIT_TSFTR_CLI1_RST_8822C BIT(2)
+#define BIT_TSFTR_CLI0_RST_8822C BIT(1)
+#define BIT_TSFTR_RST_8822C BIT(0)
+
+/* 2 REG_MBSSID_BCN_SPACE_8822C */
+
+#define BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822C 28
+#define BIT_MASK_BCN_TIMER_SEL_FWRD_8822C 0x7
+#define BIT_BCN_TIMER_SEL_FWRD_8822C(x) \
+ (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_8822C) \
+ << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822C)
+#define BITS_BCN_TIMER_SEL_FWRD_8822C \
+ (BIT_MASK_BCN_TIMER_SEL_FWRD_8822C \
+ << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822C)
+#define BIT_CLEAR_BCN_TIMER_SEL_FWRD_8822C(x) \
+ ((x) & (~BITS_BCN_TIMER_SEL_FWRD_8822C))
+#define BIT_GET_BCN_TIMER_SEL_FWRD_8822C(x) \
+ (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_8822C) & \
+ BIT_MASK_BCN_TIMER_SEL_FWRD_8822C)
+#define BIT_SET_BCN_TIMER_SEL_FWRD_8822C(x, v) \
+ (BIT_CLEAR_BCN_TIMER_SEL_FWRD_8822C(x) | \
+ BIT_BCN_TIMER_SEL_FWRD_8822C(v))
+
+#define BIT_SHIFT_BCN_SPACE_CLINT0_8822C 16
+#define BIT_MASK_BCN_SPACE_CLINT0_8822C 0xfff
+#define BIT_BCN_SPACE_CLINT0_8822C(x) \
+ (((x) & BIT_MASK_BCN_SPACE_CLINT0_8822C) \
+ << BIT_SHIFT_BCN_SPACE_CLINT0_8822C)
+#define BITS_BCN_SPACE_CLINT0_8822C \
+ (BIT_MASK_BCN_SPACE_CLINT0_8822C << BIT_SHIFT_BCN_SPACE_CLINT0_8822C)
+#define BIT_CLEAR_BCN_SPACE_CLINT0_8822C(x) \
+ ((x) & (~BITS_BCN_SPACE_CLINT0_8822C))
+#define BIT_GET_BCN_SPACE_CLINT0_8822C(x) \
+ (((x) >> BIT_SHIFT_BCN_SPACE_CLINT0_8822C) & \
+ BIT_MASK_BCN_SPACE_CLINT0_8822C)
+#define BIT_SET_BCN_SPACE_CLINT0_8822C(x, v) \
+ (BIT_CLEAR_BCN_SPACE_CLINT0_8822C(x) | BIT_BCN_SPACE_CLINT0_8822C(v))
+
+#define BIT_SHIFT_BCN_SPACE0_8822C 0
+#define BIT_MASK_BCN_SPACE0_8822C 0xffff
+#define BIT_BCN_SPACE0_8822C(x) \
+ (((x) & BIT_MASK_BCN_SPACE0_8822C) << BIT_SHIFT_BCN_SPACE0_8822C)
+#define BITS_BCN_SPACE0_8822C \
+ (BIT_MASK_BCN_SPACE0_8822C << BIT_SHIFT_BCN_SPACE0_8822C)
+#define BIT_CLEAR_BCN_SPACE0_8822C(x) ((x) & (~BITS_BCN_SPACE0_8822C))
+#define BIT_GET_BCN_SPACE0_8822C(x) \
+ (((x) >> BIT_SHIFT_BCN_SPACE0_8822C) & BIT_MASK_BCN_SPACE0_8822C)
+#define BIT_SET_BCN_SPACE0_8822C(x, v) \
+ (BIT_CLEAR_BCN_SPACE0_8822C(x) | BIT_BCN_SPACE0_8822C(v))
+
+/* 2 REG_DRVERLYINT_8822C */
+
+#define BIT_SHIFT_DRVERLYITV_8822C 0
+#define BIT_MASK_DRVERLYITV_8822C 0xff
+#define BIT_DRVERLYITV_8822C(x) \
+ (((x) & BIT_MASK_DRVERLYITV_8822C) << BIT_SHIFT_DRVERLYITV_8822C)
+#define BITS_DRVERLYITV_8822C \
+ (BIT_MASK_DRVERLYITV_8822C << BIT_SHIFT_DRVERLYITV_8822C)
+#define BIT_CLEAR_DRVERLYITV_8822C(x) ((x) & (~BITS_DRVERLYITV_8822C))
+#define BIT_GET_DRVERLYITV_8822C(x) \
+ (((x) >> BIT_SHIFT_DRVERLYITV_8822C) & BIT_MASK_DRVERLYITV_8822C)
+#define BIT_SET_DRVERLYITV_8822C(x, v) \
+ (BIT_CLEAR_DRVERLYITV_8822C(x) | BIT_DRVERLYITV_8822C(v))
+
+/* 2 REG_BCNDMATIM_8822C */
+
+#define BIT_SHIFT_BCNDMATIM_8822C 0
+#define BIT_MASK_BCNDMATIM_8822C 0xff
+#define BIT_BCNDMATIM_8822C(x) \
+ (((x) & BIT_MASK_BCNDMATIM_8822C) << BIT_SHIFT_BCNDMATIM_8822C)
+#define BITS_BCNDMATIM_8822C \
+ (BIT_MASK_BCNDMATIM_8822C << BIT_SHIFT_BCNDMATIM_8822C)
+#define BIT_CLEAR_BCNDMATIM_8822C(x) ((x) & (~BITS_BCNDMATIM_8822C))
+#define BIT_GET_BCNDMATIM_8822C(x) \
+ (((x) >> BIT_SHIFT_BCNDMATIM_8822C) & BIT_MASK_BCNDMATIM_8822C)
+#define BIT_SET_BCNDMATIM_8822C(x, v) \
+ (BIT_CLEAR_BCNDMATIM_8822C(x) | BIT_BCNDMATIM_8822C(v))
+
+/* 2 REG_ATIMWND_8822C */
+
+#define BIT_SHIFT_ATIMWND0_8822C 0
+#define BIT_MASK_ATIMWND0_8822C 0xffff
+#define BIT_ATIMWND0_8822C(x) \
+ (((x) & BIT_MASK_ATIMWND0_8822C) << BIT_SHIFT_ATIMWND0_8822C)
+#define BITS_ATIMWND0_8822C \
+ (BIT_MASK_ATIMWND0_8822C << BIT_SHIFT_ATIMWND0_8822C)
+#define BIT_CLEAR_ATIMWND0_8822C(x) ((x) & (~BITS_ATIMWND0_8822C))
+#define BIT_GET_ATIMWND0_8822C(x) \
+ (((x) >> BIT_SHIFT_ATIMWND0_8822C) & BIT_MASK_ATIMWND0_8822C)
+#define BIT_SET_ATIMWND0_8822C(x, v) \
+ (BIT_CLEAR_ATIMWND0_8822C(x) | BIT_ATIMWND0_8822C(v))
+
+/* 2 REG_USTIME_TSF_8822C */
+
+#define BIT_SHIFT_USTIME_TSF_V1_8822C 0
+#define BIT_MASK_USTIME_TSF_V1_8822C 0xff
+#define BIT_USTIME_TSF_V1_8822C(x) \
+ (((x) & BIT_MASK_USTIME_TSF_V1_8822C) << BIT_SHIFT_USTIME_TSF_V1_8822C)
+#define BITS_USTIME_TSF_V1_8822C \
+ (BIT_MASK_USTIME_TSF_V1_8822C << BIT_SHIFT_USTIME_TSF_V1_8822C)
+#define BIT_CLEAR_USTIME_TSF_V1_8822C(x) ((x) & (~BITS_USTIME_TSF_V1_8822C))
+#define BIT_GET_USTIME_TSF_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_USTIME_TSF_V1_8822C) & BIT_MASK_USTIME_TSF_V1_8822C)
+#define BIT_SET_USTIME_TSF_V1_8822C(x, v) \
+ (BIT_CLEAR_USTIME_TSF_V1_8822C(x) | BIT_USTIME_TSF_V1_8822C(v))
+
+/* 2 REG_BCN_MAX_ERR_8822C */
+
+#define BIT_SHIFT_BCN_MAX_ERR_8822C 0
+#define BIT_MASK_BCN_MAX_ERR_8822C 0xff
+#define BIT_BCN_MAX_ERR_8822C(x) \
+ (((x) & BIT_MASK_BCN_MAX_ERR_8822C) << BIT_SHIFT_BCN_MAX_ERR_8822C)
+#define BITS_BCN_MAX_ERR_8822C \
+ (BIT_MASK_BCN_MAX_ERR_8822C << BIT_SHIFT_BCN_MAX_ERR_8822C)
+#define BIT_CLEAR_BCN_MAX_ERR_8822C(x) ((x) & (~BITS_BCN_MAX_ERR_8822C))
+#define BIT_GET_BCN_MAX_ERR_8822C(x) \
+ (((x) >> BIT_SHIFT_BCN_MAX_ERR_8822C) & BIT_MASK_BCN_MAX_ERR_8822C)
+#define BIT_SET_BCN_MAX_ERR_8822C(x, v) \
+ (BIT_CLEAR_BCN_MAX_ERR_8822C(x) | BIT_BCN_MAX_ERR_8822C(v))
+
+/* 2 REG_RXTSF_OFFSET_CCK_8822C */
+
+#define BIT_SHIFT_CCK_RXTSF_OFFSET_8822C 0
+#define BIT_MASK_CCK_RXTSF_OFFSET_8822C 0xff
+#define BIT_CCK_RXTSF_OFFSET_8822C(x) \
+ (((x) & BIT_MASK_CCK_RXTSF_OFFSET_8822C) \
+ << BIT_SHIFT_CCK_RXTSF_OFFSET_8822C)
+#define BITS_CCK_RXTSF_OFFSET_8822C \
+ (BIT_MASK_CCK_RXTSF_OFFSET_8822C << BIT_SHIFT_CCK_RXTSF_OFFSET_8822C)
+#define BIT_CLEAR_CCK_RXTSF_OFFSET_8822C(x) \
+ ((x) & (~BITS_CCK_RXTSF_OFFSET_8822C))
+#define BIT_GET_CCK_RXTSF_OFFSET_8822C(x) \
+ (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8822C) & \
+ BIT_MASK_CCK_RXTSF_OFFSET_8822C)
+#define BIT_SET_CCK_RXTSF_OFFSET_8822C(x, v) \
+ (BIT_CLEAR_CCK_RXTSF_OFFSET_8822C(x) | BIT_CCK_RXTSF_OFFSET_8822C(v))
+
+/* 2 REG_RXTSF_OFFSET_OFDM_8822C */
+
+#define BIT_SHIFT_OFDM_RXTSF_OFFSET_8822C 0
+#define BIT_MASK_OFDM_RXTSF_OFFSET_8822C 0xff
+#define BIT_OFDM_RXTSF_OFFSET_8822C(x) \
+ (((x) & BIT_MASK_OFDM_RXTSF_OFFSET_8822C) \
+ << BIT_SHIFT_OFDM_RXTSF_OFFSET_8822C)
+#define BITS_OFDM_RXTSF_OFFSET_8822C \
+ (BIT_MASK_OFDM_RXTSF_OFFSET_8822C << BIT_SHIFT_OFDM_RXTSF_OFFSET_8822C)
+#define BIT_CLEAR_OFDM_RXTSF_OFFSET_8822C(x) \
+ ((x) & (~BITS_OFDM_RXTSF_OFFSET_8822C))
+#define BIT_GET_OFDM_RXTSF_OFFSET_8822C(x) \
+ (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8822C) & \
+ BIT_MASK_OFDM_RXTSF_OFFSET_8822C)
+#define BIT_SET_OFDM_RXTSF_OFFSET_8822C(x, v) \
+ (BIT_CLEAR_OFDM_RXTSF_OFFSET_8822C(x) | BIT_OFDM_RXTSF_OFFSET_8822C(v))
+
+/* 2 REG_TSFTR_8822C */
+
+#define BIT_SHIFT_TSF_TIMER_V1_8822C 0
+#define BIT_MASK_TSF_TIMER_V1_8822C 0xffffffffL
+#define BIT_TSF_TIMER_V1_8822C(x) \
+ (((x) & BIT_MASK_TSF_TIMER_V1_8822C) << BIT_SHIFT_TSF_TIMER_V1_8822C)
+#define BITS_TSF_TIMER_V1_8822C \
+ (BIT_MASK_TSF_TIMER_V1_8822C << BIT_SHIFT_TSF_TIMER_V1_8822C)
+#define BIT_CLEAR_TSF_TIMER_V1_8822C(x) ((x) & (~BITS_TSF_TIMER_V1_8822C))
+#define BIT_GET_TSF_TIMER_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_TSF_TIMER_V1_8822C) & BIT_MASK_TSF_TIMER_V1_8822C)
+#define BIT_SET_TSF_TIMER_V1_8822C(x, v) \
+ (BIT_CLEAR_TSF_TIMER_V1_8822C(x) | BIT_TSF_TIMER_V1_8822C(v))
+
+/* 2 REG_TSFTR_1_8822C */
+
+#define BIT_SHIFT_TSF_TIMER_V2_8822C 0
+#define BIT_MASK_TSF_TIMER_V2_8822C 0xffffffffL
+#define BIT_TSF_TIMER_V2_8822C(x) \
+ (((x) & BIT_MASK_TSF_TIMER_V2_8822C) << BIT_SHIFT_TSF_TIMER_V2_8822C)
+#define BITS_TSF_TIMER_V2_8822C \
+ (BIT_MASK_TSF_TIMER_V2_8822C << BIT_SHIFT_TSF_TIMER_V2_8822C)
+#define BIT_CLEAR_TSF_TIMER_V2_8822C(x) ((x) & (~BITS_TSF_TIMER_V2_8822C))
+#define BIT_GET_TSF_TIMER_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_TSF_TIMER_V2_8822C) & BIT_MASK_TSF_TIMER_V2_8822C)
+#define BIT_SET_TSF_TIMER_V2_8822C(x, v) \
+ (BIT_CLEAR_TSF_TIMER_V2_8822C(x) | BIT_TSF_TIMER_V2_8822C(v))
+
+/* 2 REG_FREERUN_CNT_8822C */
+
+#define BIT_SHIFT_FREERUN_CNT_V1_8822C 0
+#define BIT_MASK_FREERUN_CNT_V1_8822C 0xffffffffL
+#define BIT_FREERUN_CNT_V1_8822C(x) \
+ (((x) & BIT_MASK_FREERUN_CNT_V1_8822C) \
+ << BIT_SHIFT_FREERUN_CNT_V1_8822C)
+#define BITS_FREERUN_CNT_V1_8822C \
+ (BIT_MASK_FREERUN_CNT_V1_8822C << BIT_SHIFT_FREERUN_CNT_V1_8822C)
+#define BIT_CLEAR_FREERUN_CNT_V1_8822C(x) ((x) & (~BITS_FREERUN_CNT_V1_8822C))
+#define BIT_GET_FREERUN_CNT_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_FREERUN_CNT_V1_8822C) & \
+ BIT_MASK_FREERUN_CNT_V1_8822C)
+#define BIT_SET_FREERUN_CNT_V1_8822C(x, v) \
+ (BIT_CLEAR_FREERUN_CNT_V1_8822C(x) | BIT_FREERUN_CNT_V1_8822C(v))
+
+/* 2 REG_FREERUN_CNT_1_8822C */
+
+#define BIT_SHIFT_FREERUN_CNT_V2_8822C 0
+#define BIT_MASK_FREERUN_CNT_V2_8822C 0xffffffffL
+#define BIT_FREERUN_CNT_V2_8822C(x) \
+ (((x) & BIT_MASK_FREERUN_CNT_V2_8822C) \
+ << BIT_SHIFT_FREERUN_CNT_V2_8822C)
+#define BITS_FREERUN_CNT_V2_8822C \
+ (BIT_MASK_FREERUN_CNT_V2_8822C << BIT_SHIFT_FREERUN_CNT_V2_8822C)
+#define BIT_CLEAR_FREERUN_CNT_V2_8822C(x) ((x) & (~BITS_FREERUN_CNT_V2_8822C))
+#define BIT_GET_FREERUN_CNT_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_FREERUN_CNT_V2_8822C) & \
+ BIT_MASK_FREERUN_CNT_V2_8822C)
+#define BIT_SET_FREERUN_CNT_V2_8822C(x, v) \
+ (BIT_CLEAR_FREERUN_CNT_V2_8822C(x) | BIT_FREERUN_CNT_V2_8822C(v))
+
+/* 2 REG_ATIMWND1_V1_8822C */
+
+#define BIT_SHIFT_ATIMWND1_V1_8822C 0
+#define BIT_MASK_ATIMWND1_V1_8822C 0xff
+#define BIT_ATIMWND1_V1_8822C(x) \
+ (((x) & BIT_MASK_ATIMWND1_V1_8822C) << BIT_SHIFT_ATIMWND1_V1_8822C)
+#define BITS_ATIMWND1_V1_8822C \
+ (BIT_MASK_ATIMWND1_V1_8822C << BIT_SHIFT_ATIMWND1_V1_8822C)
+#define BIT_CLEAR_ATIMWND1_V1_8822C(x) ((x) & (~BITS_ATIMWND1_V1_8822C))
+#define BIT_GET_ATIMWND1_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_ATIMWND1_V1_8822C) & BIT_MASK_ATIMWND1_V1_8822C)
+#define BIT_SET_ATIMWND1_V1_8822C(x, v) \
+ (BIT_CLEAR_ATIMWND1_V1_8822C(x) | BIT_ATIMWND1_V1_8822C(v))
+
+/* 2 REG_TBTT_PROHIBIT_INFRA_8822C */
+
+#define BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822C 0
+#define BIT_MASK_TBTT_PROHIBIT_INFRA_8822C 0xff
+#define BIT_TBTT_PROHIBIT_INFRA_8822C(x) \
+ (((x) & BIT_MASK_TBTT_PROHIBIT_INFRA_8822C) \
+ << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822C)
+#define BITS_TBTT_PROHIBIT_INFRA_8822C \
+ (BIT_MASK_TBTT_PROHIBIT_INFRA_8822C \
+ << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822C)
+#define BIT_CLEAR_TBTT_PROHIBIT_INFRA_8822C(x) \
+ ((x) & (~BITS_TBTT_PROHIBIT_INFRA_8822C))
+#define BIT_GET_TBTT_PROHIBIT_INFRA_8822C(x) \
+ (((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA_8822C) & \
+ BIT_MASK_TBTT_PROHIBIT_INFRA_8822C)
+#define BIT_SET_TBTT_PROHIBIT_INFRA_8822C(x, v) \
+ (BIT_CLEAR_TBTT_PROHIBIT_INFRA_8822C(x) | \
+ BIT_TBTT_PROHIBIT_INFRA_8822C(v))
+
+/* 2 REG_CTWND_8822C */
+
+#define BIT_SHIFT_CTWND_8822C 0
+#define BIT_MASK_CTWND_8822C 0xff
+#define BIT_CTWND_8822C(x) \
+ (((x) & BIT_MASK_CTWND_8822C) << BIT_SHIFT_CTWND_8822C)
+#define BITS_CTWND_8822C (BIT_MASK_CTWND_8822C << BIT_SHIFT_CTWND_8822C)
+#define BIT_CLEAR_CTWND_8822C(x) ((x) & (~BITS_CTWND_8822C))
+#define BIT_GET_CTWND_8822C(x) \
+ (((x) >> BIT_SHIFT_CTWND_8822C) & BIT_MASK_CTWND_8822C)
+#define BIT_SET_CTWND_8822C(x, v) \
+ (BIT_CLEAR_CTWND_8822C(x) | BIT_CTWND_8822C(v))
+
+/* 2 REG_BCNIVLCUNT_8822C */
+
+#define BIT_SHIFT_BCNIVLCUNT_8822C 0
+#define BIT_MASK_BCNIVLCUNT_8822C 0x7f
+#define BIT_BCNIVLCUNT_8822C(x) \
+ (((x) & BIT_MASK_BCNIVLCUNT_8822C) << BIT_SHIFT_BCNIVLCUNT_8822C)
+#define BITS_BCNIVLCUNT_8822C \
+ (BIT_MASK_BCNIVLCUNT_8822C << BIT_SHIFT_BCNIVLCUNT_8822C)
+#define BIT_CLEAR_BCNIVLCUNT_8822C(x) ((x) & (~BITS_BCNIVLCUNT_8822C))
+#define BIT_GET_BCNIVLCUNT_8822C(x) \
+ (((x) >> BIT_SHIFT_BCNIVLCUNT_8822C) & BIT_MASK_BCNIVLCUNT_8822C)
+#define BIT_SET_BCNIVLCUNT_8822C(x, v) \
+ (BIT_CLEAR_BCNIVLCUNT_8822C(x) | BIT_BCNIVLCUNT_8822C(v))
+
+/* 2 REG_BCNDROPCTRL_8822C */
+#define BIT_BEACON_DROP_EN_8822C BIT(7)
+
+#define BIT_SHIFT_BEACON_DROP_IVL_8822C 0
+#define BIT_MASK_BEACON_DROP_IVL_8822C 0x7f
+#define BIT_BEACON_DROP_IVL_8822C(x) \
+ (((x) & BIT_MASK_BEACON_DROP_IVL_8822C) \
+ << BIT_SHIFT_BEACON_DROP_IVL_8822C)
+#define BITS_BEACON_DROP_IVL_8822C \
+ (BIT_MASK_BEACON_DROP_IVL_8822C << BIT_SHIFT_BEACON_DROP_IVL_8822C)
+#define BIT_CLEAR_BEACON_DROP_IVL_8822C(x) ((x) & (~BITS_BEACON_DROP_IVL_8822C))
+#define BIT_GET_BEACON_DROP_IVL_8822C(x) \
+ (((x) >> BIT_SHIFT_BEACON_DROP_IVL_8822C) & \
+ BIT_MASK_BEACON_DROP_IVL_8822C)
+#define BIT_SET_BEACON_DROP_IVL_8822C(x, v) \
+ (BIT_CLEAR_BEACON_DROP_IVL_8822C(x) | BIT_BEACON_DROP_IVL_8822C(v))
+
+/* 2 REG_HGQ_TIMEOUT_PERIOD_8822C */
+
+#define BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822C 0
+#define BIT_MASK_HGQ_TIMEOUT_PERIOD_8822C 0xff
+#define BIT_HGQ_TIMEOUT_PERIOD_8822C(x) \
+ (((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8822C) \
+ << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822C)
+#define BITS_HGQ_TIMEOUT_PERIOD_8822C \
+ (BIT_MASK_HGQ_TIMEOUT_PERIOD_8822C \
+ << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822C)
+#define BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8822C(x) \
+ ((x) & (~BITS_HGQ_TIMEOUT_PERIOD_8822C))
+#define BIT_GET_HGQ_TIMEOUT_PERIOD_8822C(x) \
+ (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8822C) & \
+ BIT_MASK_HGQ_TIMEOUT_PERIOD_8822C)
+#define BIT_SET_HGQ_TIMEOUT_PERIOD_8822C(x, v) \
+ (BIT_CLEAR_HGQ_TIMEOUT_PERIOD_8822C(x) | \
+ BIT_HGQ_TIMEOUT_PERIOD_8822C(v))
+
+/* 2 REG_TXCMD_TIMEOUT_PERIOD_8822C */
+
+#define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822C 0
+#define BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822C 0xff
+#define BIT_TXCMD_TIMEOUT_PERIOD_8822C(x) \
+ (((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822C) \
+ << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822C)
+#define BITS_TXCMD_TIMEOUT_PERIOD_8822C \
+ (BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822C \
+ << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822C)
+#define BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8822C(x) \
+ ((x) & (~BITS_TXCMD_TIMEOUT_PERIOD_8822C))
+#define BIT_GET_TXCMD_TIMEOUT_PERIOD_8822C(x) \
+ (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8822C) & \
+ BIT_MASK_TXCMD_TIMEOUT_PERIOD_8822C)
+#define BIT_SET_TXCMD_TIMEOUT_PERIOD_8822C(x, v) \
+ (BIT_CLEAR_TXCMD_TIMEOUT_PERIOD_8822C(x) | \
+ BIT_TXCMD_TIMEOUT_PERIOD_8822C(v))
+
+/* 2 REG_MISC_CTRL_8822C */
+#define BIT_DIS_MARK_TSF_US_V2_8822C BIT(7)
+#define BIT_AUTO_SYNC_BY_TBTT_8822C BIT(6)
+#define BIT_DIS_TRX_CAL_BCN_8822C BIT(5)
+#define BIT_DIS_TX_CAL_TBTT_8822C BIT(4)
+#define BIT_EN_FREECNT_8822C BIT(3)
+#define BIT_BCN_AGGRESSION_8822C BIT(2)
+
+#define BIT_SHIFT_DIS_SECONDARY_CCA_8822C 0
+#define BIT_MASK_DIS_SECONDARY_CCA_8822C 0x3
+#define BIT_DIS_SECONDARY_CCA_8822C(x) \
+ (((x) & BIT_MASK_DIS_SECONDARY_CCA_8822C) \
+ << BIT_SHIFT_DIS_SECONDARY_CCA_8822C)
+#define BITS_DIS_SECONDARY_CCA_8822C \
+ (BIT_MASK_DIS_SECONDARY_CCA_8822C << BIT_SHIFT_DIS_SECONDARY_CCA_8822C)
+#define BIT_CLEAR_DIS_SECONDARY_CCA_8822C(x) \
+ ((x) & (~BITS_DIS_SECONDARY_CCA_8822C))
+#define BIT_GET_DIS_SECONDARY_CCA_8822C(x) \
+ (((x) >> BIT_SHIFT_DIS_SECONDARY_CCA_8822C) & \
+ BIT_MASK_DIS_SECONDARY_CCA_8822C)
+#define BIT_SET_DIS_SECONDARY_CCA_8822C(x, v) \
+ (BIT_CLEAR_DIS_SECONDARY_CCA_8822C(x) | BIT_DIS_SECONDARY_CCA_8822C(v))
+
+/* 2 REG_BCN_CTRL_CLINT1_8822C */
+#define BIT_CLI1_DIS_RX_BSSID_FIT_8822C BIT(6)
+#define BIT_CLI1_DIS_TSF_UDT_8822C BIT(4)
+#define BIT_CLI1_EN_BCN_FUNCTION_8822C BIT(3)
+#define BIT_CLI1_EN_RXBCN_RPT_8822C BIT(2)
+#define BIT_CLI1_ENP2P_CTWINDOW_8822C BIT(1)
+#define BIT_CLI1_ENP2P_BCNQ_AREA_8822C BIT(0)
+
+/* 2 REG_BCN_CTRL_CLINT2_8822C */
+#define BIT_CLI2_DIS_RX_BSSID_FIT_8822C BIT(6)
+#define BIT_CLI2_DIS_TSF_UDT_8822C BIT(4)
+#define BIT_CLI2_EN_BCN_FUNCTION_8822C BIT(3)
+#define BIT_CLI2_EN_RXBCN_RPT_8822C BIT(2)
+#define BIT_CLI2_ENP2P_CTWINDOW_8822C BIT(1)
+#define BIT_CLI2_ENP2P_BCNQ_AREA_8822C BIT(0)
+
+/* 2 REG_BCN_CTRL_CLINT3_8822C */
+#define BIT_CLI3_DIS_RX_BSSID_FIT_8822C BIT(6)
+#define BIT_CLI3_DIS_TSF_UDT_8822C BIT(4)
+#define BIT_CLI3_EN_BCN_FUNCTION_8822C BIT(3)
+#define BIT_CLI3_EN_RXBCN_RPT_8822C BIT(2)
+#define BIT_CLI3_ENP2P_CTWINDOW_8822C BIT(1)
+#define BIT_CLI3_ENP2P_BCNQ_AREA_8822C BIT(0)
+
+/* 2 REG_EXTEND_CTRL_8822C */
+#define BIT_EN_TSFBIT32_RST_P2P2_8822C BIT(5)
+#define BIT_EN_TSFBIT32_RST_P2P1_8822C BIT(4)
+
+#define BIT_SHIFT_PORT_SEL_8822C 0
+#define BIT_MASK_PORT_SEL_8822C 0x7
+#define BIT_PORT_SEL_8822C(x) \
+ (((x) & BIT_MASK_PORT_SEL_8822C) << BIT_SHIFT_PORT_SEL_8822C)
+#define BITS_PORT_SEL_8822C \
+ (BIT_MASK_PORT_SEL_8822C << BIT_SHIFT_PORT_SEL_8822C)
+#define BIT_CLEAR_PORT_SEL_8822C(x) ((x) & (~BITS_PORT_SEL_8822C))
+#define BIT_GET_PORT_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_PORT_SEL_8822C) & BIT_MASK_PORT_SEL_8822C)
+#define BIT_SET_PORT_SEL_8822C(x, v) \
+ (BIT_CLEAR_PORT_SEL_8822C(x) | BIT_PORT_SEL_8822C(v))
+
+/* 2 REG_P2PPS1_SPEC_STATE_8822C */
+#define BIT_P2P1_SPEC_POWER_STATE_8822C BIT(7)
+#define BIT_P2P1_SPEC_CTWINDOW_ON_8822C BIT(6)
+#define BIT_P2P1_SPEC_BCN_AREA_ON_8822C BIT(5)
+#define BIT_P2P1_SPEC_CTWIN_EARLY_DISTX_8822C BIT(4)
+#define BIT_P2P1_SPEC_NOA1_OFF_PERIOD_8822C BIT(3)
+#define BIT_P2P1_SPEC_FORCE_DOZE1_8822C BIT(2)
+#define BIT_P2P1_SPEC_NOA0_OFF_PERIOD_8822C BIT(1)
+#define BIT_P2P1_SPEC_FORCE_DOZE0_8822C BIT(0)
+
+/* 2 REG_P2PPS1_STATE_8822C */
+#define BIT_P2P1_POWER_STATE_8822C BIT(7)
+#define BIT_P2P1_CTWINDOW_ON_8822C BIT(6)
+#define BIT_P2P1_BEACON_AREA_ON_8822C BIT(5)
+#define BIT_P2P1_CTWIN_EARLY_DISTX_8822C BIT(4)
+#define BIT_P2P1_NOA1_OFF_PERIOD_8822C BIT(3)
+#define BIT_P2P1_FORCE_DOZE1_8822C BIT(2)
+#define BIT_P2P1_NOA0_OFF_PERIOD_8822C BIT(1)
+#define BIT_P2P1_FORCE_DOZE0_8822C BIT(0)
+
+/* 2 REG_P2PPS2_SPEC_STATE_8822C */
+#define BIT_P2P2_SPEC_POWER_STATE_8822C BIT(7)
+#define BIT_P2P2_SPEC_CTWINDOW_ON_8822C BIT(6)
+#define BIT_P2P2_SPEC_BCN_AREA_ON_8822C BIT(5)
+#define BIT_P2P2_SPEC_CTWIN_EARLY_DISTX_8822C BIT(4)
+#define BIT_P2P2_SPEC_NOA1_OFF_PERIOD_8822C BIT(3)
+#define BIT_P2P2_SPEC_FORCE_DOZE1_8822C BIT(2)
+#define BIT_P2P2_SPEC_NOA0_OFF_PERIOD_8822C BIT(1)
+#define BIT_P2P2_SPEC_FORCE_DOZE0_8822C BIT(0)
+
+/* 2 REG_P2PPS2_STATE_8822C */
+#define BIT_P2P2_POWER_STATE_8822C BIT(7)
+#define BIT_P2P2_CTWINDOW_ON_8822C BIT(6)
+#define BIT_P2P2_BEACON_AREA_ON_8822C BIT(5)
+#define BIT_P2P2_CTWIN_EARLY_DISTX_8822C BIT(4)
+#define BIT_P2P2_NOA1_OFF_PERIOD_8822C BIT(3)
+#define BIT_P2P2_FORCE_DOZE1_8822C BIT(2)
+#define BIT_P2P2_NOA0_OFF_PERIOD_8822C BIT(1)
+#define BIT_P2P2_FORCE_DOZE0_8822C BIT(0)
+
+/* 2 REG_PS_TIMER0_8822C */
+
+#define BIT_SHIFT_PSTIMER0_INT_8822C 5
+#define BIT_MASK_PSTIMER0_INT_8822C 0x7ffffff
+#define BIT_PSTIMER0_INT_8822C(x) \
+ (((x) & BIT_MASK_PSTIMER0_INT_8822C) << BIT_SHIFT_PSTIMER0_INT_8822C)
+#define BITS_PSTIMER0_INT_8822C \
+ (BIT_MASK_PSTIMER0_INT_8822C << BIT_SHIFT_PSTIMER0_INT_8822C)
+#define BIT_CLEAR_PSTIMER0_INT_8822C(x) ((x) & (~BITS_PSTIMER0_INT_8822C))
+#define BIT_GET_PSTIMER0_INT_8822C(x) \
+ (((x) >> BIT_SHIFT_PSTIMER0_INT_8822C) & BIT_MASK_PSTIMER0_INT_8822C)
+#define BIT_SET_PSTIMER0_INT_8822C(x, v) \
+ (BIT_CLEAR_PSTIMER0_INT_8822C(x) | BIT_PSTIMER0_INT_8822C(v))
+
+/* 2 REG_PS_TIMER1_8822C */
+
+#define BIT_SHIFT_PSTIMER1_INT_8822C 5
+#define BIT_MASK_PSTIMER1_INT_8822C 0x7ffffff
+#define BIT_PSTIMER1_INT_8822C(x) \
+ (((x) & BIT_MASK_PSTIMER1_INT_8822C) << BIT_SHIFT_PSTIMER1_INT_8822C)
+#define BITS_PSTIMER1_INT_8822C \
+ (BIT_MASK_PSTIMER1_INT_8822C << BIT_SHIFT_PSTIMER1_INT_8822C)
+#define BIT_CLEAR_PSTIMER1_INT_8822C(x) ((x) & (~BITS_PSTIMER1_INT_8822C))
+#define BIT_GET_PSTIMER1_INT_8822C(x) \
+ (((x) >> BIT_SHIFT_PSTIMER1_INT_8822C) & BIT_MASK_PSTIMER1_INT_8822C)
+#define BIT_SET_PSTIMER1_INT_8822C(x, v) \
+ (BIT_CLEAR_PSTIMER1_INT_8822C(x) | BIT_PSTIMER1_INT_8822C(v))
+
+/* 2 REG_PS_TIMER2_8822C */
+
+#define BIT_SHIFT_PSTIMER2_INT_8822C 5
+#define BIT_MASK_PSTIMER2_INT_8822C 0x7ffffff
+#define BIT_PSTIMER2_INT_8822C(x) \
+ (((x) & BIT_MASK_PSTIMER2_INT_8822C) << BIT_SHIFT_PSTIMER2_INT_8822C)
+#define BITS_PSTIMER2_INT_8822C \
+ (BIT_MASK_PSTIMER2_INT_8822C << BIT_SHIFT_PSTIMER2_INT_8822C)
+#define BIT_CLEAR_PSTIMER2_INT_8822C(x) ((x) & (~BITS_PSTIMER2_INT_8822C))
+#define BIT_GET_PSTIMER2_INT_8822C(x) \
+ (((x) >> BIT_SHIFT_PSTIMER2_INT_8822C) & BIT_MASK_PSTIMER2_INT_8822C)
+#define BIT_SET_PSTIMER2_INT_8822C(x, v) \
+ (BIT_CLEAR_PSTIMER2_INT_8822C(x) | BIT_PSTIMER2_INT_8822C(v))
+
+/* 2 REG_TBTT_CTN_AREA_8822C */
+
+#define BIT_SHIFT_TBTT_CTN_AREA_8822C 0
+#define BIT_MASK_TBTT_CTN_AREA_8822C 0xff
+#define BIT_TBTT_CTN_AREA_8822C(x) \
+ (((x) & BIT_MASK_TBTT_CTN_AREA_8822C) << BIT_SHIFT_TBTT_CTN_AREA_8822C)
+#define BITS_TBTT_CTN_AREA_8822C \
+ (BIT_MASK_TBTT_CTN_AREA_8822C << BIT_SHIFT_TBTT_CTN_AREA_8822C)
+#define BIT_CLEAR_TBTT_CTN_AREA_8822C(x) ((x) & (~BITS_TBTT_CTN_AREA_8822C))
+#define BIT_GET_TBTT_CTN_AREA_8822C(x) \
+ (((x) >> BIT_SHIFT_TBTT_CTN_AREA_8822C) & BIT_MASK_TBTT_CTN_AREA_8822C)
+#define BIT_SET_TBTT_CTN_AREA_8822C(x, v) \
+ (BIT_CLEAR_TBTT_CTN_AREA_8822C(x) | BIT_TBTT_CTN_AREA_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_FORCE_BCN_IFS_8822C */
+
+#define BIT_SHIFT_FORCE_BCN_IFS_8822C 0
+#define BIT_MASK_FORCE_BCN_IFS_8822C 0xff
+#define BIT_FORCE_BCN_IFS_8822C(x) \
+ (((x) & BIT_MASK_FORCE_BCN_IFS_8822C) << BIT_SHIFT_FORCE_BCN_IFS_8822C)
+#define BITS_FORCE_BCN_IFS_8822C \
+ (BIT_MASK_FORCE_BCN_IFS_8822C << BIT_SHIFT_FORCE_BCN_IFS_8822C)
+#define BIT_CLEAR_FORCE_BCN_IFS_8822C(x) ((x) & (~BITS_FORCE_BCN_IFS_8822C))
+#define BIT_GET_FORCE_BCN_IFS_8822C(x) \
+ (((x) >> BIT_SHIFT_FORCE_BCN_IFS_8822C) & BIT_MASK_FORCE_BCN_IFS_8822C)
+#define BIT_SET_FORCE_BCN_IFS_8822C(x, v) \
+ (BIT_CLEAR_FORCE_BCN_IFS_8822C(x) | BIT_FORCE_BCN_IFS_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_TXOP_MIN_8822C */
+#define BIT_HIQ_NAV_BREAK_EN_8822C BIT(15)
+#define BIT_MGQ_NAV_BREAK_EN_8822C BIT(14)
+
+#define BIT_SHIFT_TXOP_MIN_8822C 0
+#define BIT_MASK_TXOP_MIN_8822C 0x3fff
+#define BIT_TXOP_MIN_8822C(x) \
+ (((x) & BIT_MASK_TXOP_MIN_8822C) << BIT_SHIFT_TXOP_MIN_8822C)
+#define BITS_TXOP_MIN_8822C \
+ (BIT_MASK_TXOP_MIN_8822C << BIT_SHIFT_TXOP_MIN_8822C)
+#define BIT_CLEAR_TXOP_MIN_8822C(x) ((x) & (~BITS_TXOP_MIN_8822C))
+#define BIT_GET_TXOP_MIN_8822C(x) \
+ (((x) >> BIT_SHIFT_TXOP_MIN_8822C) & BIT_MASK_TXOP_MIN_8822C)
+#define BIT_SET_TXOP_MIN_8822C(x, v) \
+ (BIT_CLEAR_TXOP_MIN_8822C(x) | BIT_TXOP_MIN_8822C(v))
+
+/* 2 REG_PRE_BKF_TIME_8822C */
+
+#define BIT_SHIFT_PRE_BKF_TIME_8822C 0
+#define BIT_MASK_PRE_BKF_TIME_8822C 0xff
+#define BIT_PRE_BKF_TIME_8822C(x) \
+ (((x) & BIT_MASK_PRE_BKF_TIME_8822C) << BIT_SHIFT_PRE_BKF_TIME_8822C)
+#define BITS_PRE_BKF_TIME_8822C \
+ (BIT_MASK_PRE_BKF_TIME_8822C << BIT_SHIFT_PRE_BKF_TIME_8822C)
+#define BIT_CLEAR_PRE_BKF_TIME_8822C(x) ((x) & (~BITS_PRE_BKF_TIME_8822C))
+#define BIT_GET_PRE_BKF_TIME_8822C(x) \
+ (((x) >> BIT_SHIFT_PRE_BKF_TIME_8822C) & BIT_MASK_PRE_BKF_TIME_8822C)
+#define BIT_SET_PRE_BKF_TIME_8822C(x, v) \
+ (BIT_CLEAR_PRE_BKF_TIME_8822C(x) | BIT_PRE_BKF_TIME_8822C(v))
+
+/* 2 REG_CROSS_TXOP_CTRL_8822C */
+#define BIT_TXFAIL_BREACK_TXOP_EN_8822C BIT(3)
+#define BIT_DTIM_BYPASS_8822C BIT(2)
+#define BIT_RTS_NAV_TXOP_8822C BIT(1)
+#define BIT_NOT_CROSS_TXOP_8822C BIT(0)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_RX_TBTT_SHIFT_V1_8822C */
+#define BIT_RX_TBTT_SHIFT_RW_FLAG_V1_8822C BIT(31)
+
+#define BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1_8822C 16
+#define BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1_8822C 0xfff
+#define BIT_RX_TBTT_SHIFT_OFFSET_V1_8822C(x) \
+ (((x) & BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1_8822C) \
+ << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1_8822C)
+#define BITS_RX_TBTT_SHIFT_OFFSET_V1_8822C \
+ (BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1_8822C \
+ << BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1_8822C)
+#define BIT_CLEAR_RX_TBTT_SHIFT_OFFSET_V1_8822C(x) \
+ ((x) & (~BITS_RX_TBTT_SHIFT_OFFSET_V1_8822C))
+#define BIT_GET_RX_TBTT_SHIFT_OFFSET_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_RX_TBTT_SHIFT_OFFSET_V1_8822C) & \
+ BIT_MASK_RX_TBTT_SHIFT_OFFSET_V1_8822C)
+#define BIT_SET_RX_TBTT_SHIFT_OFFSET_V1_8822C(x, v) \
+ (BIT_CLEAR_RX_TBTT_SHIFT_OFFSET_V1_8822C(x) | \
+ BIT_RX_TBTT_SHIFT_OFFSET_V1_8822C(v))
+
+#define BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1_8822C 8
+#define BIT_MASK_RX_TBTT_SHIFT_SEL_V1_8822C 0x7
+#define BIT_RX_TBTT_SHIFT_SEL_V1_8822C(x) \
+ (((x) & BIT_MASK_RX_TBTT_SHIFT_SEL_V1_8822C) \
+ << BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1_8822C)
+#define BITS_RX_TBTT_SHIFT_SEL_V1_8822C \
+ (BIT_MASK_RX_TBTT_SHIFT_SEL_V1_8822C \
+ << BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1_8822C)
+#define BIT_CLEAR_RX_TBTT_SHIFT_SEL_V1_8822C(x) \
+ ((x) & (~BITS_RX_TBTT_SHIFT_SEL_V1_8822C))
+#define BIT_GET_RX_TBTT_SHIFT_SEL_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_RX_TBTT_SHIFT_SEL_V1_8822C) & \
+ BIT_MASK_RX_TBTT_SHIFT_SEL_V1_8822C)
+#define BIT_SET_RX_TBTT_SHIFT_SEL_V1_8822C(x, v) \
+ (BIT_CLEAR_RX_TBTT_SHIFT_SEL_V1_8822C(x) | \
+ BIT_RX_TBTT_SHIFT_SEL_V1_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_ATIMWND2_8822C */
+
+#define BIT_SHIFT_ATIMWND2_8822C 0
+#define BIT_MASK_ATIMWND2_8822C 0xff
+#define BIT_ATIMWND2_8822C(x) \
+ (((x) & BIT_MASK_ATIMWND2_8822C) << BIT_SHIFT_ATIMWND2_8822C)
+#define BITS_ATIMWND2_8822C \
+ (BIT_MASK_ATIMWND2_8822C << BIT_SHIFT_ATIMWND2_8822C)
+#define BIT_CLEAR_ATIMWND2_8822C(x) ((x) & (~BITS_ATIMWND2_8822C))
+#define BIT_GET_ATIMWND2_8822C(x) \
+ (((x) >> BIT_SHIFT_ATIMWND2_8822C) & BIT_MASK_ATIMWND2_8822C)
+#define BIT_SET_ATIMWND2_8822C(x, v) \
+ (BIT_CLEAR_ATIMWND2_8822C(x) | BIT_ATIMWND2_8822C(v))
+
+/* 2 REG_ATIMWND3_8822C */
+
+#define BIT_SHIFT_ATIMWND3_8822C 0
+#define BIT_MASK_ATIMWND3_8822C 0xff
+#define BIT_ATIMWND3_8822C(x) \
+ (((x) & BIT_MASK_ATIMWND3_8822C) << BIT_SHIFT_ATIMWND3_8822C)
+#define BITS_ATIMWND3_8822C \
+ (BIT_MASK_ATIMWND3_8822C << BIT_SHIFT_ATIMWND3_8822C)
+#define BIT_CLEAR_ATIMWND3_8822C(x) ((x) & (~BITS_ATIMWND3_8822C))
+#define BIT_GET_ATIMWND3_8822C(x) \
+ (((x) >> BIT_SHIFT_ATIMWND3_8822C) & BIT_MASK_ATIMWND3_8822C)
+#define BIT_SET_ATIMWND3_8822C(x, v) \
+ (BIT_CLEAR_ATIMWND3_8822C(x) | BIT_ATIMWND3_8822C(v))
+
+/* 2 REG_ATIMWND4_8822C */
+
+#define BIT_SHIFT_ATIMWND4_8822C 0
+#define BIT_MASK_ATIMWND4_8822C 0xff
+#define BIT_ATIMWND4_8822C(x) \
+ (((x) & BIT_MASK_ATIMWND4_8822C) << BIT_SHIFT_ATIMWND4_8822C)
+#define BITS_ATIMWND4_8822C \
+ (BIT_MASK_ATIMWND4_8822C << BIT_SHIFT_ATIMWND4_8822C)
+#define BIT_CLEAR_ATIMWND4_8822C(x) ((x) & (~BITS_ATIMWND4_8822C))
+#define BIT_GET_ATIMWND4_8822C(x) \
+ (((x) >> BIT_SHIFT_ATIMWND4_8822C) & BIT_MASK_ATIMWND4_8822C)
+#define BIT_SET_ATIMWND4_8822C(x, v) \
+ (BIT_CLEAR_ATIMWND4_8822C(x) | BIT_ATIMWND4_8822C(v))
+
+/* 2 REG_ATIMWND5_8822C */
+
+#define BIT_SHIFT_ATIMWND5_8822C 0
+#define BIT_MASK_ATIMWND5_8822C 0xff
+#define BIT_ATIMWND5_8822C(x) \
+ (((x) & BIT_MASK_ATIMWND5_8822C) << BIT_SHIFT_ATIMWND5_8822C)
+#define BITS_ATIMWND5_8822C \
+ (BIT_MASK_ATIMWND5_8822C << BIT_SHIFT_ATIMWND5_8822C)
+#define BIT_CLEAR_ATIMWND5_8822C(x) ((x) & (~BITS_ATIMWND5_8822C))
+#define BIT_GET_ATIMWND5_8822C(x) \
+ (((x) >> BIT_SHIFT_ATIMWND5_8822C) & BIT_MASK_ATIMWND5_8822C)
+#define BIT_SET_ATIMWND5_8822C(x, v) \
+ (BIT_CLEAR_ATIMWND5_8822C(x) | BIT_ATIMWND5_8822C(v))
+
+/* 2 REG_ATIMWND6_8822C */
+
+#define BIT_SHIFT_ATIMWND6_8822C 0
+#define BIT_MASK_ATIMWND6_8822C 0xff
+#define BIT_ATIMWND6_8822C(x) \
+ (((x) & BIT_MASK_ATIMWND6_8822C) << BIT_SHIFT_ATIMWND6_8822C)
+#define BITS_ATIMWND6_8822C \
+ (BIT_MASK_ATIMWND6_8822C << BIT_SHIFT_ATIMWND6_8822C)
+#define BIT_CLEAR_ATIMWND6_8822C(x) ((x) & (~BITS_ATIMWND6_8822C))
+#define BIT_GET_ATIMWND6_8822C(x) \
+ (((x) >> BIT_SHIFT_ATIMWND6_8822C) & BIT_MASK_ATIMWND6_8822C)
+#define BIT_SET_ATIMWND6_8822C(x, v) \
+ (BIT_CLEAR_ATIMWND6_8822C(x) | BIT_ATIMWND6_8822C(v))
+
+/* 2 REG_ATIMWND7_8822C */
+
+#define BIT_SHIFT_ATIMWND7_8822C 0
+#define BIT_MASK_ATIMWND7_8822C 0xff
+#define BIT_ATIMWND7_8822C(x) \
+ (((x) & BIT_MASK_ATIMWND7_8822C) << BIT_SHIFT_ATIMWND7_8822C)
+#define BITS_ATIMWND7_8822C \
+ (BIT_MASK_ATIMWND7_8822C << BIT_SHIFT_ATIMWND7_8822C)
+#define BIT_CLEAR_ATIMWND7_8822C(x) ((x) & (~BITS_ATIMWND7_8822C))
+#define BIT_GET_ATIMWND7_8822C(x) \
+ (((x) >> BIT_SHIFT_ATIMWND7_8822C) & BIT_MASK_ATIMWND7_8822C)
+#define BIT_SET_ATIMWND7_8822C(x, v) \
+ (BIT_CLEAR_ATIMWND7_8822C(x) | BIT_ATIMWND7_8822C(v))
+
+/* 2 REG_ATIMUGT_8822C */
+
+#define BIT_SHIFT_ATIM_URGENT_8822C 0
+#define BIT_MASK_ATIM_URGENT_8822C 0xff
+#define BIT_ATIM_URGENT_8822C(x) \
+ (((x) & BIT_MASK_ATIM_URGENT_8822C) << BIT_SHIFT_ATIM_URGENT_8822C)
+#define BITS_ATIM_URGENT_8822C \
+ (BIT_MASK_ATIM_URGENT_8822C << BIT_SHIFT_ATIM_URGENT_8822C)
+#define BIT_CLEAR_ATIM_URGENT_8822C(x) ((x) & (~BITS_ATIM_URGENT_8822C))
+#define BIT_GET_ATIM_URGENT_8822C(x) \
+ (((x) >> BIT_SHIFT_ATIM_URGENT_8822C) & BIT_MASK_ATIM_URGENT_8822C)
+#define BIT_SET_ATIM_URGENT_8822C(x, v) \
+ (BIT_CLEAR_ATIM_URGENT_8822C(x) | BIT_ATIM_URGENT_8822C(v))
+
+/* 2 REG_HIQ_NO_LMT_EN_8822C */
+#define BIT_HIQ_NO_LMT_EN_VAP7_8822C BIT(7)
+#define BIT_HIQ_NO_LMT_EN_VAP6_8822C BIT(6)
+#define BIT_HIQ_NO_LMT_EN_VAP5_8822C BIT(5)
+#define BIT_HIQ_NO_LMT_EN_VAP4_8822C BIT(4)
+#define BIT_HIQ_NO_LMT_EN_VAP3_8822C BIT(3)
+#define BIT_HIQ_NO_LMT_EN_VAP2_8822C BIT(2)
+#define BIT_HIQ_NO_LMT_EN_VAP1_8822C BIT(1)
+#define BIT_HIQ_NO_LMT_EN_ROOT_8822C BIT(0)
+
+/* 2 REG_DTIM_COUNTER_ROOT_8822C */
+
+#define BIT_SHIFT_DTIM_COUNT_ROOT_8822C 0
+#define BIT_MASK_DTIM_COUNT_ROOT_8822C 0xff
+#define BIT_DTIM_COUNT_ROOT_8822C(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_ROOT_8822C) \
+ << BIT_SHIFT_DTIM_COUNT_ROOT_8822C)
+#define BITS_DTIM_COUNT_ROOT_8822C \
+ (BIT_MASK_DTIM_COUNT_ROOT_8822C << BIT_SHIFT_DTIM_COUNT_ROOT_8822C)
+#define BIT_CLEAR_DTIM_COUNT_ROOT_8822C(x) ((x) & (~BITS_DTIM_COUNT_ROOT_8822C))
+#define BIT_GET_DTIM_COUNT_ROOT_8822C(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_ROOT_8822C) & \
+ BIT_MASK_DTIM_COUNT_ROOT_8822C)
+#define BIT_SET_DTIM_COUNT_ROOT_8822C(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_ROOT_8822C(x) | BIT_DTIM_COUNT_ROOT_8822C(v))
+
+/* 2 REG_DTIM_COUNTER_VAP1_8822C */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP1_8822C 0
+#define BIT_MASK_DTIM_COUNT_VAP1_8822C 0xff
+#define BIT_DTIM_COUNT_VAP1_8822C(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_VAP1_8822C) \
+ << BIT_SHIFT_DTIM_COUNT_VAP1_8822C)
+#define BITS_DTIM_COUNT_VAP1_8822C \
+ (BIT_MASK_DTIM_COUNT_VAP1_8822C << BIT_SHIFT_DTIM_COUNT_VAP1_8822C)
+#define BIT_CLEAR_DTIM_COUNT_VAP1_8822C(x) ((x) & (~BITS_DTIM_COUNT_VAP1_8822C))
+#define BIT_GET_DTIM_COUNT_VAP1_8822C(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP1_8822C) & \
+ BIT_MASK_DTIM_COUNT_VAP1_8822C)
+#define BIT_SET_DTIM_COUNT_VAP1_8822C(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_VAP1_8822C(x) | BIT_DTIM_COUNT_VAP1_8822C(v))
+
+/* 2 REG_DTIM_COUNTER_VAP2_8822C */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP2_8822C 0
+#define BIT_MASK_DTIM_COUNT_VAP2_8822C 0xff
+#define BIT_DTIM_COUNT_VAP2_8822C(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_VAP2_8822C) \
+ << BIT_SHIFT_DTIM_COUNT_VAP2_8822C)
+#define BITS_DTIM_COUNT_VAP2_8822C \
+ (BIT_MASK_DTIM_COUNT_VAP2_8822C << BIT_SHIFT_DTIM_COUNT_VAP2_8822C)
+#define BIT_CLEAR_DTIM_COUNT_VAP2_8822C(x) ((x) & (~BITS_DTIM_COUNT_VAP2_8822C))
+#define BIT_GET_DTIM_COUNT_VAP2_8822C(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP2_8822C) & \
+ BIT_MASK_DTIM_COUNT_VAP2_8822C)
+#define BIT_SET_DTIM_COUNT_VAP2_8822C(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_VAP2_8822C(x) | BIT_DTIM_COUNT_VAP2_8822C(v))
+
+/* 2 REG_DTIM_COUNTER_VAP3_8822C */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP3_8822C 0
+#define BIT_MASK_DTIM_COUNT_VAP3_8822C 0xff
+#define BIT_DTIM_COUNT_VAP3_8822C(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_VAP3_8822C) \
+ << BIT_SHIFT_DTIM_COUNT_VAP3_8822C)
+#define BITS_DTIM_COUNT_VAP3_8822C \
+ (BIT_MASK_DTIM_COUNT_VAP3_8822C << BIT_SHIFT_DTIM_COUNT_VAP3_8822C)
+#define BIT_CLEAR_DTIM_COUNT_VAP3_8822C(x) ((x) & (~BITS_DTIM_COUNT_VAP3_8822C))
+#define BIT_GET_DTIM_COUNT_VAP3_8822C(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP3_8822C) & \
+ BIT_MASK_DTIM_COUNT_VAP3_8822C)
+#define BIT_SET_DTIM_COUNT_VAP3_8822C(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_VAP3_8822C(x) | BIT_DTIM_COUNT_VAP3_8822C(v))
+
+/* 2 REG_DTIM_COUNTER_VAP4_8822C */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP4_8822C 0
+#define BIT_MASK_DTIM_COUNT_VAP4_8822C 0xff
+#define BIT_DTIM_COUNT_VAP4_8822C(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_VAP4_8822C) \
+ << BIT_SHIFT_DTIM_COUNT_VAP4_8822C)
+#define BITS_DTIM_COUNT_VAP4_8822C \
+ (BIT_MASK_DTIM_COUNT_VAP4_8822C << BIT_SHIFT_DTIM_COUNT_VAP4_8822C)
+#define BIT_CLEAR_DTIM_COUNT_VAP4_8822C(x) ((x) & (~BITS_DTIM_COUNT_VAP4_8822C))
+#define BIT_GET_DTIM_COUNT_VAP4_8822C(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP4_8822C) & \
+ BIT_MASK_DTIM_COUNT_VAP4_8822C)
+#define BIT_SET_DTIM_COUNT_VAP4_8822C(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_VAP4_8822C(x) | BIT_DTIM_COUNT_VAP4_8822C(v))
+
+/* 2 REG_DTIM_COUNTER_VAP5_8822C */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP5_8822C 0
+#define BIT_MASK_DTIM_COUNT_VAP5_8822C 0xff
+#define BIT_DTIM_COUNT_VAP5_8822C(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_VAP5_8822C) \
+ << BIT_SHIFT_DTIM_COUNT_VAP5_8822C)
+#define BITS_DTIM_COUNT_VAP5_8822C \
+ (BIT_MASK_DTIM_COUNT_VAP5_8822C << BIT_SHIFT_DTIM_COUNT_VAP5_8822C)
+#define BIT_CLEAR_DTIM_COUNT_VAP5_8822C(x) ((x) & (~BITS_DTIM_COUNT_VAP5_8822C))
+#define BIT_GET_DTIM_COUNT_VAP5_8822C(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP5_8822C) & \
+ BIT_MASK_DTIM_COUNT_VAP5_8822C)
+#define BIT_SET_DTIM_COUNT_VAP5_8822C(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_VAP5_8822C(x) | BIT_DTIM_COUNT_VAP5_8822C(v))
+
+/* 2 REG_DTIM_COUNTER_VAP6_8822C */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP6_8822C 0
+#define BIT_MASK_DTIM_COUNT_VAP6_8822C 0xff
+#define BIT_DTIM_COUNT_VAP6_8822C(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_VAP6_8822C) \
+ << BIT_SHIFT_DTIM_COUNT_VAP6_8822C)
+#define BITS_DTIM_COUNT_VAP6_8822C \
+ (BIT_MASK_DTIM_COUNT_VAP6_8822C << BIT_SHIFT_DTIM_COUNT_VAP6_8822C)
+#define BIT_CLEAR_DTIM_COUNT_VAP6_8822C(x) ((x) & (~BITS_DTIM_COUNT_VAP6_8822C))
+#define BIT_GET_DTIM_COUNT_VAP6_8822C(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP6_8822C) & \
+ BIT_MASK_DTIM_COUNT_VAP6_8822C)
+#define BIT_SET_DTIM_COUNT_VAP6_8822C(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_VAP6_8822C(x) | BIT_DTIM_COUNT_VAP6_8822C(v))
+
+/* 2 REG_DTIM_COUNTER_VAP7_8822C */
+
+#define BIT_SHIFT_DTIM_COUNT_VAP7_8822C 0
+#define BIT_MASK_DTIM_COUNT_VAP7_8822C 0xff
+#define BIT_DTIM_COUNT_VAP7_8822C(x) \
+ (((x) & BIT_MASK_DTIM_COUNT_VAP7_8822C) \
+ << BIT_SHIFT_DTIM_COUNT_VAP7_8822C)
+#define BITS_DTIM_COUNT_VAP7_8822C \
+ (BIT_MASK_DTIM_COUNT_VAP7_8822C << BIT_SHIFT_DTIM_COUNT_VAP7_8822C)
+#define BIT_CLEAR_DTIM_COUNT_VAP7_8822C(x) ((x) & (~BITS_DTIM_COUNT_VAP7_8822C))
+#define BIT_GET_DTIM_COUNT_VAP7_8822C(x) \
+ (((x) >> BIT_SHIFT_DTIM_COUNT_VAP7_8822C) & \
+ BIT_MASK_DTIM_COUNT_VAP7_8822C)
+#define BIT_SET_DTIM_COUNT_VAP7_8822C(x, v) \
+ (BIT_CLEAR_DTIM_COUNT_VAP7_8822C(x) | BIT_DTIM_COUNT_VAP7_8822C(v))
+
+/* 2 REG_DIS_ATIM_8822C */
+#define BIT_DIS_ATIM_VAP7_8822C BIT(7)
+#define BIT_DIS_ATIM_VAP6_8822C BIT(6)
+#define BIT_DIS_ATIM_VAP5_8822C BIT(5)
+#define BIT_DIS_ATIM_VAP4_8822C BIT(4)
+#define BIT_DIS_ATIM_VAP3_8822C BIT(3)
+#define BIT_DIS_ATIM_VAP2_8822C BIT(2)
+#define BIT_DIS_ATIM_VAP1_8822C BIT(1)
+#define BIT_DIS_ATIM_ROOT_8822C BIT(0)
+
+/* 2 REG_EARLY_128US_8822C */
+
+#define BIT_SHIFT_TSFT_SEL_TIMER1_8822C 3
+#define BIT_MASK_TSFT_SEL_TIMER1_8822C 0x7
+#define BIT_TSFT_SEL_TIMER1_8822C(x) \
+ (((x) & BIT_MASK_TSFT_SEL_TIMER1_8822C) \
+ << BIT_SHIFT_TSFT_SEL_TIMER1_8822C)
+#define BITS_TSFT_SEL_TIMER1_8822C \
+ (BIT_MASK_TSFT_SEL_TIMER1_8822C << BIT_SHIFT_TSFT_SEL_TIMER1_8822C)
+#define BIT_CLEAR_TSFT_SEL_TIMER1_8822C(x) ((x) & (~BITS_TSFT_SEL_TIMER1_8822C))
+#define BIT_GET_TSFT_SEL_TIMER1_8822C(x) \
+ (((x) >> BIT_SHIFT_TSFT_SEL_TIMER1_8822C) & \
+ BIT_MASK_TSFT_SEL_TIMER1_8822C)
+#define BIT_SET_TSFT_SEL_TIMER1_8822C(x, v) \
+ (BIT_CLEAR_TSFT_SEL_TIMER1_8822C(x) | BIT_TSFT_SEL_TIMER1_8822C(v))
+
+#define BIT_SHIFT_EARLY_128US_8822C 0
+#define BIT_MASK_EARLY_128US_8822C 0x7
+#define BIT_EARLY_128US_8822C(x) \
+ (((x) & BIT_MASK_EARLY_128US_8822C) << BIT_SHIFT_EARLY_128US_8822C)
+#define BITS_EARLY_128US_8822C \
+ (BIT_MASK_EARLY_128US_8822C << BIT_SHIFT_EARLY_128US_8822C)
+#define BIT_CLEAR_EARLY_128US_8822C(x) ((x) & (~BITS_EARLY_128US_8822C))
+#define BIT_GET_EARLY_128US_8822C(x) \
+ (((x) >> BIT_SHIFT_EARLY_128US_8822C) & BIT_MASK_EARLY_128US_8822C)
+#define BIT_SET_EARLY_128US_8822C(x, v) \
+ (BIT_CLEAR_EARLY_128US_8822C(x) | BIT_EARLY_128US_8822C(v))
+
+/* 2 REG_P2PPS1_CTRL_8822C */
+#define BIT_P2P1_CTW_ALLSTASLEEP_8822C BIT(7)
+#define BIT_P2P1_OFF_DISTX_EN_8822C BIT(6)
+#define BIT_P2P1_PWR_MGT_EN_8822C BIT(5)
+#define BIT_P2P1_NOA1_EN_8822C BIT(2)
+#define BIT_P2P1_NOA0_EN_8822C BIT(1)
+
+/* 2 REG_P2PPS2_CTRL_8822C */
+#define BIT_P2P2_CTW_ALLSTASLEEP_8822C BIT(7)
+#define BIT_P2P2_OFF_DISTX_EN_8822C BIT(6)
+#define BIT_P2P2_PWR_MGT_EN_8822C BIT(5)
+#define BIT_P2P2_NOA1_EN_8822C BIT(2)
+#define BIT_P2P2_NOA0_EN_8822C BIT(1)
+
+/* 2 REG_TIMER0_SRC_SEL_8822C */
+
+#define BIT_SHIFT_SYNC_CLI_SEL_8822C 4
+#define BIT_MASK_SYNC_CLI_SEL_8822C 0x7
+#define BIT_SYNC_CLI_SEL_8822C(x) \
+ (((x) & BIT_MASK_SYNC_CLI_SEL_8822C) << BIT_SHIFT_SYNC_CLI_SEL_8822C)
+#define BITS_SYNC_CLI_SEL_8822C \
+ (BIT_MASK_SYNC_CLI_SEL_8822C << BIT_SHIFT_SYNC_CLI_SEL_8822C)
+#define BIT_CLEAR_SYNC_CLI_SEL_8822C(x) ((x) & (~BITS_SYNC_CLI_SEL_8822C))
+#define BIT_GET_SYNC_CLI_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_SYNC_CLI_SEL_8822C) & BIT_MASK_SYNC_CLI_SEL_8822C)
+#define BIT_SET_SYNC_CLI_SEL_8822C(x, v) \
+ (BIT_CLEAR_SYNC_CLI_SEL_8822C(x) | BIT_SYNC_CLI_SEL_8822C(v))
+
+#define BIT_SHIFT_TSFT_SEL_TIMER0_8822C 0
+#define BIT_MASK_TSFT_SEL_TIMER0_8822C 0x7
+#define BIT_TSFT_SEL_TIMER0_8822C(x) \
+ (((x) & BIT_MASK_TSFT_SEL_TIMER0_8822C) \
+ << BIT_SHIFT_TSFT_SEL_TIMER0_8822C)
+#define BITS_TSFT_SEL_TIMER0_8822C \
+ (BIT_MASK_TSFT_SEL_TIMER0_8822C << BIT_SHIFT_TSFT_SEL_TIMER0_8822C)
+#define BIT_CLEAR_TSFT_SEL_TIMER0_8822C(x) ((x) & (~BITS_TSFT_SEL_TIMER0_8822C))
+#define BIT_GET_TSFT_SEL_TIMER0_8822C(x) \
+ (((x) >> BIT_SHIFT_TSFT_SEL_TIMER0_8822C) & \
+ BIT_MASK_TSFT_SEL_TIMER0_8822C)
+#define BIT_SET_TSFT_SEL_TIMER0_8822C(x, v) \
+ (BIT_CLEAR_TSFT_SEL_TIMER0_8822C(x) | BIT_TSFT_SEL_TIMER0_8822C(v))
+
+/* 2 REG_NOA_UNIT_SEL_8822C */
+
+#define BIT_SHIFT_NOA_UNIT2_SEL_8822C 8
+#define BIT_MASK_NOA_UNIT2_SEL_8822C 0x7
+#define BIT_NOA_UNIT2_SEL_8822C(x) \
+ (((x) & BIT_MASK_NOA_UNIT2_SEL_8822C) << BIT_SHIFT_NOA_UNIT2_SEL_8822C)
+#define BITS_NOA_UNIT2_SEL_8822C \
+ (BIT_MASK_NOA_UNIT2_SEL_8822C << BIT_SHIFT_NOA_UNIT2_SEL_8822C)
+#define BIT_CLEAR_NOA_UNIT2_SEL_8822C(x) ((x) & (~BITS_NOA_UNIT2_SEL_8822C))
+#define BIT_GET_NOA_UNIT2_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_NOA_UNIT2_SEL_8822C) & BIT_MASK_NOA_UNIT2_SEL_8822C)
+#define BIT_SET_NOA_UNIT2_SEL_8822C(x, v) \
+ (BIT_CLEAR_NOA_UNIT2_SEL_8822C(x) | BIT_NOA_UNIT2_SEL_8822C(v))
+
+#define BIT_SHIFT_NOA_UNIT1_SEL_8822C 4
+#define BIT_MASK_NOA_UNIT1_SEL_8822C 0x7
+#define BIT_NOA_UNIT1_SEL_8822C(x) \
+ (((x) & BIT_MASK_NOA_UNIT1_SEL_8822C) << BIT_SHIFT_NOA_UNIT1_SEL_8822C)
+#define BITS_NOA_UNIT1_SEL_8822C \
+ (BIT_MASK_NOA_UNIT1_SEL_8822C << BIT_SHIFT_NOA_UNIT1_SEL_8822C)
+#define BIT_CLEAR_NOA_UNIT1_SEL_8822C(x) ((x) & (~BITS_NOA_UNIT1_SEL_8822C))
+#define BIT_GET_NOA_UNIT1_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_NOA_UNIT1_SEL_8822C) & BIT_MASK_NOA_UNIT1_SEL_8822C)
+#define BIT_SET_NOA_UNIT1_SEL_8822C(x, v) \
+ (BIT_CLEAR_NOA_UNIT1_SEL_8822C(x) | BIT_NOA_UNIT1_SEL_8822C(v))
+
+#define BIT_SHIFT_NOA_UNIT0_SEL_8822C 0
+#define BIT_MASK_NOA_UNIT0_SEL_8822C 0x7
+#define BIT_NOA_UNIT0_SEL_8822C(x) \
+ (((x) & BIT_MASK_NOA_UNIT0_SEL_8822C) << BIT_SHIFT_NOA_UNIT0_SEL_8822C)
+#define BITS_NOA_UNIT0_SEL_8822C \
+ (BIT_MASK_NOA_UNIT0_SEL_8822C << BIT_SHIFT_NOA_UNIT0_SEL_8822C)
+#define BIT_CLEAR_NOA_UNIT0_SEL_8822C(x) ((x) & (~BITS_NOA_UNIT0_SEL_8822C))
+#define BIT_GET_NOA_UNIT0_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_NOA_UNIT0_SEL_8822C) & BIT_MASK_NOA_UNIT0_SEL_8822C)
+#define BIT_SET_NOA_UNIT0_SEL_8822C(x, v) \
+ (BIT_CLEAR_NOA_UNIT0_SEL_8822C(x) | BIT_NOA_UNIT0_SEL_8822C(v))
+
+/* 2 REG_P2POFF_DIS_TXTIME_8822C */
+
+#define BIT_SHIFT_P2POFF_DIS_TXTIME_8822C 0
+#define BIT_MASK_P2POFF_DIS_TXTIME_8822C 0xff
+#define BIT_P2POFF_DIS_TXTIME_8822C(x) \
+ (((x) & BIT_MASK_P2POFF_DIS_TXTIME_8822C) \
+ << BIT_SHIFT_P2POFF_DIS_TXTIME_8822C)
+#define BITS_P2POFF_DIS_TXTIME_8822C \
+ (BIT_MASK_P2POFF_DIS_TXTIME_8822C << BIT_SHIFT_P2POFF_DIS_TXTIME_8822C)
+#define BIT_CLEAR_P2POFF_DIS_TXTIME_8822C(x) \
+ ((x) & (~BITS_P2POFF_DIS_TXTIME_8822C))
+#define BIT_GET_P2POFF_DIS_TXTIME_8822C(x) \
+ (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8822C) & \
+ BIT_MASK_P2POFF_DIS_TXTIME_8822C)
+#define BIT_SET_P2POFF_DIS_TXTIME_8822C(x, v) \
+ (BIT_CLEAR_P2POFF_DIS_TXTIME_8822C(x) | BIT_P2POFF_DIS_TXTIME_8822C(v))
+
+/* 2 REG_MBSSID_BCN_SPACE2_8822C */
+
+#define BIT_SHIFT_BCN_SPACE_CLINT2_8822C 16
+#define BIT_MASK_BCN_SPACE_CLINT2_8822C 0xfff
+#define BIT_BCN_SPACE_CLINT2_8822C(x) \
+ (((x) & BIT_MASK_BCN_SPACE_CLINT2_8822C) \
+ << BIT_SHIFT_BCN_SPACE_CLINT2_8822C)
+#define BITS_BCN_SPACE_CLINT2_8822C \
+ (BIT_MASK_BCN_SPACE_CLINT2_8822C << BIT_SHIFT_BCN_SPACE_CLINT2_8822C)
+#define BIT_CLEAR_BCN_SPACE_CLINT2_8822C(x) \
+ ((x) & (~BITS_BCN_SPACE_CLINT2_8822C))
+#define BIT_GET_BCN_SPACE_CLINT2_8822C(x) \
+ (((x) >> BIT_SHIFT_BCN_SPACE_CLINT2_8822C) & \
+ BIT_MASK_BCN_SPACE_CLINT2_8822C)
+#define BIT_SET_BCN_SPACE_CLINT2_8822C(x, v) \
+ (BIT_CLEAR_BCN_SPACE_CLINT2_8822C(x) | BIT_BCN_SPACE_CLINT2_8822C(v))
+
+#define BIT_SHIFT_BCN_SPACE_CLINT1_8822C 0
+#define BIT_MASK_BCN_SPACE_CLINT1_8822C 0xfff
+#define BIT_BCN_SPACE_CLINT1_8822C(x) \
+ (((x) & BIT_MASK_BCN_SPACE_CLINT1_8822C) \
+ << BIT_SHIFT_BCN_SPACE_CLINT1_8822C)
+#define BITS_BCN_SPACE_CLINT1_8822C \
+ (BIT_MASK_BCN_SPACE_CLINT1_8822C << BIT_SHIFT_BCN_SPACE_CLINT1_8822C)
+#define BIT_CLEAR_BCN_SPACE_CLINT1_8822C(x) \
+ ((x) & (~BITS_BCN_SPACE_CLINT1_8822C))
+#define BIT_GET_BCN_SPACE_CLINT1_8822C(x) \
+ (((x) >> BIT_SHIFT_BCN_SPACE_CLINT1_8822C) & \
+ BIT_MASK_BCN_SPACE_CLINT1_8822C)
+#define BIT_SET_BCN_SPACE_CLINT1_8822C(x, v) \
+ (BIT_CLEAR_BCN_SPACE_CLINT1_8822C(x) | BIT_BCN_SPACE_CLINT1_8822C(v))
+
+/* 2 REG_MBSSID_BCN_SPACE3_8822C */
+
+#define BIT_SHIFT_SUB_BCN_SPACE_8822C 16
+#define BIT_MASK_SUB_BCN_SPACE_8822C 0xff
+#define BIT_SUB_BCN_SPACE_8822C(x) \
+ (((x) & BIT_MASK_SUB_BCN_SPACE_8822C) << BIT_SHIFT_SUB_BCN_SPACE_8822C)
+#define BITS_SUB_BCN_SPACE_8822C \
+ (BIT_MASK_SUB_BCN_SPACE_8822C << BIT_SHIFT_SUB_BCN_SPACE_8822C)
+#define BIT_CLEAR_SUB_BCN_SPACE_8822C(x) ((x) & (~BITS_SUB_BCN_SPACE_8822C))
+#define BIT_GET_SUB_BCN_SPACE_8822C(x) \
+ (((x) >> BIT_SHIFT_SUB_BCN_SPACE_8822C) & BIT_MASK_SUB_BCN_SPACE_8822C)
+#define BIT_SET_SUB_BCN_SPACE_8822C(x, v) \
+ (BIT_CLEAR_SUB_BCN_SPACE_8822C(x) | BIT_SUB_BCN_SPACE_8822C(v))
+
+#define BIT_SHIFT_BCN_SPACE_CLINT3_8822C 0
+#define BIT_MASK_BCN_SPACE_CLINT3_8822C 0xfff
+#define BIT_BCN_SPACE_CLINT3_8822C(x) \
+ (((x) & BIT_MASK_BCN_SPACE_CLINT3_8822C) \
+ << BIT_SHIFT_BCN_SPACE_CLINT3_8822C)
+#define BITS_BCN_SPACE_CLINT3_8822C \
+ (BIT_MASK_BCN_SPACE_CLINT3_8822C << BIT_SHIFT_BCN_SPACE_CLINT3_8822C)
+#define BIT_CLEAR_BCN_SPACE_CLINT3_8822C(x) \
+ ((x) & (~BITS_BCN_SPACE_CLINT3_8822C))
+#define BIT_GET_BCN_SPACE_CLINT3_8822C(x) \
+ (((x) >> BIT_SHIFT_BCN_SPACE_CLINT3_8822C) & \
+ BIT_MASK_BCN_SPACE_CLINT3_8822C)
+#define BIT_SET_BCN_SPACE_CLINT3_8822C(x, v) \
+ (BIT_CLEAR_BCN_SPACE_CLINT3_8822C(x) | BIT_BCN_SPACE_CLINT3_8822C(v))
+
+/* 2 REG_ACMHWCTRL_8822C */
+#define BIT_BEQ_ACM_STATUS_8822C BIT(7)
+#define BIT_VIQ_ACM_STATUS_8822C BIT(6)
+#define BIT_VOQ_ACM_STATUS_8822C BIT(5)
+#define BIT_BEQ_ACM_EN_8822C BIT(3)
+#define BIT_VIQ_ACM_EN_8822C BIT(2)
+#define BIT_VOQ_ACM_EN_8822C BIT(1)
+#define BIT_ACMHWEN_8822C BIT(0)
+
+/* 2 REG_ACMRSTCTRL_8822C */
+#define BIT_BE_ACM_RESET_USED_TIME_8822C BIT(2)
+#define BIT_VI_ACM_RESET_USED_TIME_8822C BIT(1)
+#define BIT_VO_ACM_RESET_USED_TIME_8822C BIT(0)
+
+/* 2 REG_ACMAVG_8822C */
+
+#define BIT_SHIFT_AVGPERIOD_8822C 0
+#define BIT_MASK_AVGPERIOD_8822C 0xffff
+#define BIT_AVGPERIOD_8822C(x) \
+ (((x) & BIT_MASK_AVGPERIOD_8822C) << BIT_SHIFT_AVGPERIOD_8822C)
+#define BITS_AVGPERIOD_8822C \
+ (BIT_MASK_AVGPERIOD_8822C << BIT_SHIFT_AVGPERIOD_8822C)
+#define BIT_CLEAR_AVGPERIOD_8822C(x) ((x) & (~BITS_AVGPERIOD_8822C))
+#define BIT_GET_AVGPERIOD_8822C(x) \
+ (((x) >> BIT_SHIFT_AVGPERIOD_8822C) & BIT_MASK_AVGPERIOD_8822C)
+#define BIT_SET_AVGPERIOD_8822C(x, v) \
+ (BIT_CLEAR_AVGPERIOD_8822C(x) | BIT_AVGPERIOD_8822C(v))
+
+/* 2 REG_VO_ADMTIME_8822C */
+
+#define BIT_SHIFT_VO_ADMITTED_TIME_8822C 0
+#define BIT_MASK_VO_ADMITTED_TIME_8822C 0xffff
+#define BIT_VO_ADMITTED_TIME_8822C(x) \
+ (((x) & BIT_MASK_VO_ADMITTED_TIME_8822C) \
+ << BIT_SHIFT_VO_ADMITTED_TIME_8822C)
+#define BITS_VO_ADMITTED_TIME_8822C \
+ (BIT_MASK_VO_ADMITTED_TIME_8822C << BIT_SHIFT_VO_ADMITTED_TIME_8822C)
+#define BIT_CLEAR_VO_ADMITTED_TIME_8822C(x) \
+ ((x) & (~BITS_VO_ADMITTED_TIME_8822C))
+#define BIT_GET_VO_ADMITTED_TIME_8822C(x) \
+ (((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8822C) & \
+ BIT_MASK_VO_ADMITTED_TIME_8822C)
+#define BIT_SET_VO_ADMITTED_TIME_8822C(x, v) \
+ (BIT_CLEAR_VO_ADMITTED_TIME_8822C(x) | BIT_VO_ADMITTED_TIME_8822C(v))
+
+/* 2 REG_VI_ADMTIME_8822C */
+
+#define BIT_SHIFT_VI_ADMITTED_TIME_8822C 0
+#define BIT_MASK_VI_ADMITTED_TIME_8822C 0xffff
+#define BIT_VI_ADMITTED_TIME_8822C(x) \
+ (((x) & BIT_MASK_VI_ADMITTED_TIME_8822C) \
+ << BIT_SHIFT_VI_ADMITTED_TIME_8822C)
+#define BITS_VI_ADMITTED_TIME_8822C \
+ (BIT_MASK_VI_ADMITTED_TIME_8822C << BIT_SHIFT_VI_ADMITTED_TIME_8822C)
+#define BIT_CLEAR_VI_ADMITTED_TIME_8822C(x) \
+ ((x) & (~BITS_VI_ADMITTED_TIME_8822C))
+#define BIT_GET_VI_ADMITTED_TIME_8822C(x) \
+ (((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8822C) & \
+ BIT_MASK_VI_ADMITTED_TIME_8822C)
+#define BIT_SET_VI_ADMITTED_TIME_8822C(x, v) \
+ (BIT_CLEAR_VI_ADMITTED_TIME_8822C(x) | BIT_VI_ADMITTED_TIME_8822C(v))
+
+/* 2 REG_BE_ADMTIME_8822C */
+
+#define BIT_SHIFT_BE_ADMITTED_TIME_8822C 0
+#define BIT_MASK_BE_ADMITTED_TIME_8822C 0xffff
+#define BIT_BE_ADMITTED_TIME_8822C(x) \
+ (((x) & BIT_MASK_BE_ADMITTED_TIME_8822C) \
+ << BIT_SHIFT_BE_ADMITTED_TIME_8822C)
+#define BITS_BE_ADMITTED_TIME_8822C \
+ (BIT_MASK_BE_ADMITTED_TIME_8822C << BIT_SHIFT_BE_ADMITTED_TIME_8822C)
+#define BIT_CLEAR_BE_ADMITTED_TIME_8822C(x) \
+ ((x) & (~BITS_BE_ADMITTED_TIME_8822C))
+#define BIT_GET_BE_ADMITTED_TIME_8822C(x) \
+ (((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8822C) & \
+ BIT_MASK_BE_ADMITTED_TIME_8822C)
+#define BIT_SET_BE_ADMITTED_TIME_8822C(x, v) \
+ (BIT_CLEAR_BE_ADMITTED_TIME_8822C(x) | BIT_BE_ADMITTED_TIME_8822C(v))
+
+/* 2 REG_MAC_HEADER_NAV_OFFSET_8822C */
+
+#define BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8822C 0
+#define BIT_MASK_MAC_HEADER_NAV_OFFSET_8822C 0xff
+#define BIT_MAC_HEADER_NAV_OFFSET_8822C(x) \
+ (((x) & BIT_MASK_MAC_HEADER_NAV_OFFSET_8822C) \
+ << BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8822C)
+#define BITS_MAC_HEADER_NAV_OFFSET_8822C \
+ (BIT_MASK_MAC_HEADER_NAV_OFFSET_8822C \
+ << BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8822C)
+#define BIT_CLEAR_MAC_HEADER_NAV_OFFSET_8822C(x) \
+ ((x) & (~BITS_MAC_HEADER_NAV_OFFSET_8822C))
+#define BIT_GET_MAC_HEADER_NAV_OFFSET_8822C(x) \
+ (((x) >> BIT_SHIFT_MAC_HEADER_NAV_OFFSET_8822C) & \
+ BIT_MASK_MAC_HEADER_NAV_OFFSET_8822C)
+#define BIT_SET_MAC_HEADER_NAV_OFFSET_8822C(x, v) \
+ (BIT_CLEAR_MAC_HEADER_NAV_OFFSET_8822C(x) | \
+ BIT_MAC_HEADER_NAV_OFFSET_8822C(v))
+
+/* 2 REG_DIS_NDPA_NAV_CHECK_8822C */
+#define BIT_CHG_POWER_BCN_AREA_V1_8822C BIT(1)
+#define BIT_DIS_NDPA_NAV_CHECK_8822C BIT(0)
+
+/* 2 REG_EDCA_RANDOM_GEN_8822C */
+
+#define BIT_SHIFT_RANDOM_GEN_8822C 0
+#define BIT_MASK_RANDOM_GEN_8822C 0xffffff
+#define BIT_RANDOM_GEN_8822C(x) \
+ (((x) & BIT_MASK_RANDOM_GEN_8822C) << BIT_SHIFT_RANDOM_GEN_8822C)
+#define BITS_RANDOM_GEN_8822C \
+ (BIT_MASK_RANDOM_GEN_8822C << BIT_SHIFT_RANDOM_GEN_8822C)
+#define BIT_CLEAR_RANDOM_GEN_8822C(x) ((x) & (~BITS_RANDOM_GEN_8822C))
+#define BIT_GET_RANDOM_GEN_8822C(x) \
+ (((x) >> BIT_SHIFT_RANDOM_GEN_8822C) & BIT_MASK_RANDOM_GEN_8822C)
+#define BIT_SET_RANDOM_GEN_8822C(x, v) \
+ (BIT_CLEAR_RANDOM_GEN_8822C(x) | BIT_RANDOM_GEN_8822C(v))
+
+/* 2 REG_TXCMD_NOA_SEL_8822C */
+
+#define BIT_SHIFT_NOA_SEL_V2_8822C 4
+#define BIT_MASK_NOA_SEL_V2_8822C 0x7
+#define BIT_NOA_SEL_V2_8822C(x) \
+ (((x) & BIT_MASK_NOA_SEL_V2_8822C) << BIT_SHIFT_NOA_SEL_V2_8822C)
+#define BITS_NOA_SEL_V2_8822C \
+ (BIT_MASK_NOA_SEL_V2_8822C << BIT_SHIFT_NOA_SEL_V2_8822C)
+#define BIT_CLEAR_NOA_SEL_V2_8822C(x) ((x) & (~BITS_NOA_SEL_V2_8822C))
+#define BIT_GET_NOA_SEL_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_NOA_SEL_V2_8822C) & BIT_MASK_NOA_SEL_V2_8822C)
+#define BIT_SET_NOA_SEL_V2_8822C(x, v) \
+ (BIT_CLEAR_NOA_SEL_V2_8822C(x) | BIT_NOA_SEL_V2_8822C(v))
+
+#define BIT_SHIFT_TXCMD_SEG_SEL_8822C 0
+#define BIT_MASK_TXCMD_SEG_SEL_8822C 0xf
+#define BIT_TXCMD_SEG_SEL_8822C(x) \
+ (((x) & BIT_MASK_TXCMD_SEG_SEL_8822C) << BIT_SHIFT_TXCMD_SEG_SEL_8822C)
+#define BITS_TXCMD_SEG_SEL_8822C \
+ (BIT_MASK_TXCMD_SEG_SEL_8822C << BIT_SHIFT_TXCMD_SEG_SEL_8822C)
+#define BIT_CLEAR_TXCMD_SEG_SEL_8822C(x) ((x) & (~BITS_TXCMD_SEG_SEL_8822C))
+#define BIT_GET_TXCMD_SEG_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8822C) & BIT_MASK_TXCMD_SEG_SEL_8822C)
+#define BIT_SET_TXCMD_SEG_SEL_8822C(x, v) \
+ (BIT_CLEAR_TXCMD_SEG_SEL_8822C(x) | BIT_TXCMD_SEG_SEL_8822C(v))
+
+/* 2 REG_32K_CLK_SEL_8822C */
+#define BIT_R_BCNERR_CNT_EN_8822C BIT(20)
+
+#define BIT_SHIFT_R_BCNERR_PORT_SEL_8822C 16
+#define BIT_MASK_R_BCNERR_PORT_SEL_8822C 0x7
+#define BIT_R_BCNERR_PORT_SEL_8822C(x) \
+ (((x) & BIT_MASK_R_BCNERR_PORT_SEL_8822C) \
+ << BIT_SHIFT_R_BCNERR_PORT_SEL_8822C)
+#define BITS_R_BCNERR_PORT_SEL_8822C \
+ (BIT_MASK_R_BCNERR_PORT_SEL_8822C << BIT_SHIFT_R_BCNERR_PORT_SEL_8822C)
+#define BIT_CLEAR_R_BCNERR_PORT_SEL_8822C(x) \
+ ((x) & (~BITS_R_BCNERR_PORT_SEL_8822C))
+#define BIT_GET_R_BCNERR_PORT_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_R_BCNERR_PORT_SEL_8822C) & \
+ BIT_MASK_R_BCNERR_PORT_SEL_8822C)
+#define BIT_SET_R_BCNERR_PORT_SEL_8822C(x, v) \
+ (BIT_CLEAR_R_BCNERR_PORT_SEL_8822C(x) | BIT_R_BCNERR_PORT_SEL_8822C(v))
+
+#define BIT_SHIFT_R_TXPAUSE1_8822C 8
+#define BIT_MASK_R_TXPAUSE1_8822C 0xff
+#define BIT_R_TXPAUSE1_8822C(x) \
+ (((x) & BIT_MASK_R_TXPAUSE1_8822C) << BIT_SHIFT_R_TXPAUSE1_8822C)
+#define BITS_R_TXPAUSE1_8822C \
+ (BIT_MASK_R_TXPAUSE1_8822C << BIT_SHIFT_R_TXPAUSE1_8822C)
+#define BIT_CLEAR_R_TXPAUSE1_8822C(x) ((x) & (~BITS_R_TXPAUSE1_8822C))
+#define BIT_GET_R_TXPAUSE1_8822C(x) \
+ (((x) >> BIT_SHIFT_R_TXPAUSE1_8822C) & BIT_MASK_R_TXPAUSE1_8822C)
+#define BIT_SET_R_TXPAUSE1_8822C(x, v) \
+ (BIT_CLEAR_R_TXPAUSE1_8822C(x) | BIT_R_TXPAUSE1_8822C(v))
+
+#define BIT_SLEEP_32K_EN_V1_8822C BIT(2)
+
+#define BIT_SHIFT_BW_CFG_8822C 0
+#define BIT_MASK_BW_CFG_8822C 0x3
+#define BIT_BW_CFG_8822C(x) \
+ (((x) & BIT_MASK_BW_CFG_8822C) << BIT_SHIFT_BW_CFG_8822C)
+#define BITS_BW_CFG_8822C (BIT_MASK_BW_CFG_8822C << BIT_SHIFT_BW_CFG_8822C)
+#define BIT_CLEAR_BW_CFG_8822C(x) ((x) & (~BITS_BW_CFG_8822C))
+#define BIT_GET_BW_CFG_8822C(x) \
+ (((x) >> BIT_SHIFT_BW_CFG_8822C) & BIT_MASK_BW_CFG_8822C)
+#define BIT_SET_BW_CFG_8822C(x, v) \
+ (BIT_CLEAR_BW_CFG_8822C(x) | BIT_BW_CFG_8822C(v))
+
+/* 2 REG_EARLYINT_ADJUST_8822C */
+
+#define BIT_SHIFT_RXBCN_TIMER_8822C 16
+#define BIT_MASK_RXBCN_TIMER_8822C 0xffff
+#define BIT_RXBCN_TIMER_8822C(x) \
+ (((x) & BIT_MASK_RXBCN_TIMER_8822C) << BIT_SHIFT_RXBCN_TIMER_8822C)
+#define BITS_RXBCN_TIMER_8822C \
+ (BIT_MASK_RXBCN_TIMER_8822C << BIT_SHIFT_RXBCN_TIMER_8822C)
+#define BIT_CLEAR_RXBCN_TIMER_8822C(x) ((x) & (~BITS_RXBCN_TIMER_8822C))
+#define BIT_GET_RXBCN_TIMER_8822C(x) \
+ (((x) >> BIT_SHIFT_RXBCN_TIMER_8822C) & BIT_MASK_RXBCN_TIMER_8822C)
+#define BIT_SET_RXBCN_TIMER_8822C(x, v) \
+ (BIT_CLEAR_RXBCN_TIMER_8822C(x) | BIT_RXBCN_TIMER_8822C(v))
+
+#define BIT_SHIFT_R_ERLYINTADJ_8822C 0
+#define BIT_MASK_R_ERLYINTADJ_8822C 0xffff
+#define BIT_R_ERLYINTADJ_8822C(x) \
+ (((x) & BIT_MASK_R_ERLYINTADJ_8822C) << BIT_SHIFT_R_ERLYINTADJ_8822C)
+#define BITS_R_ERLYINTADJ_8822C \
+ (BIT_MASK_R_ERLYINTADJ_8822C << BIT_SHIFT_R_ERLYINTADJ_8822C)
+#define BIT_CLEAR_R_ERLYINTADJ_8822C(x) ((x) & (~BITS_R_ERLYINTADJ_8822C))
+#define BIT_GET_R_ERLYINTADJ_8822C(x) \
+ (((x) >> BIT_SHIFT_R_ERLYINTADJ_8822C) & BIT_MASK_R_ERLYINTADJ_8822C)
+#define BIT_SET_R_ERLYINTADJ_8822C(x, v) \
+ (BIT_CLEAR_R_ERLYINTADJ_8822C(x) | BIT_R_ERLYINTADJ_8822C(v))
+
+/* 2 REG_BCNERR_CNT_8822C */
+
+#define BIT_SHIFT_BCNERR_CNT_OTHERS_8822C 24
+#define BIT_MASK_BCNERR_CNT_OTHERS_8822C 0xff
+#define BIT_BCNERR_CNT_OTHERS_8822C(x) \
+ (((x) & BIT_MASK_BCNERR_CNT_OTHERS_8822C) \
+ << BIT_SHIFT_BCNERR_CNT_OTHERS_8822C)
+#define BITS_BCNERR_CNT_OTHERS_8822C \
+ (BIT_MASK_BCNERR_CNT_OTHERS_8822C << BIT_SHIFT_BCNERR_CNT_OTHERS_8822C)
+#define BIT_CLEAR_BCNERR_CNT_OTHERS_8822C(x) \
+ ((x) & (~BITS_BCNERR_CNT_OTHERS_8822C))
+#define BIT_GET_BCNERR_CNT_OTHERS_8822C(x) \
+ (((x) >> BIT_SHIFT_BCNERR_CNT_OTHERS_8822C) & \
+ BIT_MASK_BCNERR_CNT_OTHERS_8822C)
+#define BIT_SET_BCNERR_CNT_OTHERS_8822C(x, v) \
+ (BIT_CLEAR_BCNERR_CNT_OTHERS_8822C(x) | BIT_BCNERR_CNT_OTHERS_8822C(v))
+
+#define BIT_SHIFT_BCNERR_CNT_INVALID_8822C 16
+#define BIT_MASK_BCNERR_CNT_INVALID_8822C 0xff
+#define BIT_BCNERR_CNT_INVALID_8822C(x) \
+ (((x) & BIT_MASK_BCNERR_CNT_INVALID_8822C) \
+ << BIT_SHIFT_BCNERR_CNT_INVALID_8822C)
+#define BITS_BCNERR_CNT_INVALID_8822C \
+ (BIT_MASK_BCNERR_CNT_INVALID_8822C \
+ << BIT_SHIFT_BCNERR_CNT_INVALID_8822C)
+#define BIT_CLEAR_BCNERR_CNT_INVALID_8822C(x) \
+ ((x) & (~BITS_BCNERR_CNT_INVALID_8822C))
+#define BIT_GET_BCNERR_CNT_INVALID_8822C(x) \
+ (((x) >> BIT_SHIFT_BCNERR_CNT_INVALID_8822C) & \
+ BIT_MASK_BCNERR_CNT_INVALID_8822C)
+#define BIT_SET_BCNERR_CNT_INVALID_8822C(x, v) \
+ (BIT_CLEAR_BCNERR_CNT_INVALID_8822C(x) | \
+ BIT_BCNERR_CNT_INVALID_8822C(v))
+
+#define BIT_SHIFT_BCNERR_CNT_MAC_8822C 8
+#define BIT_MASK_BCNERR_CNT_MAC_8822C 0xff
+#define BIT_BCNERR_CNT_MAC_8822C(x) \
+ (((x) & BIT_MASK_BCNERR_CNT_MAC_8822C) \
+ << BIT_SHIFT_BCNERR_CNT_MAC_8822C)
+#define BITS_BCNERR_CNT_MAC_8822C \
+ (BIT_MASK_BCNERR_CNT_MAC_8822C << BIT_SHIFT_BCNERR_CNT_MAC_8822C)
+#define BIT_CLEAR_BCNERR_CNT_MAC_8822C(x) ((x) & (~BITS_BCNERR_CNT_MAC_8822C))
+#define BIT_GET_BCNERR_CNT_MAC_8822C(x) \
+ (((x) >> BIT_SHIFT_BCNERR_CNT_MAC_8822C) & \
+ BIT_MASK_BCNERR_CNT_MAC_8822C)
+#define BIT_SET_BCNERR_CNT_MAC_8822C(x, v) \
+ (BIT_CLEAR_BCNERR_CNT_MAC_8822C(x) | BIT_BCNERR_CNT_MAC_8822C(v))
+
+#define BIT_SHIFT_BCNERR_CNT_CCA_8822C 0
+#define BIT_MASK_BCNERR_CNT_CCA_8822C 0xff
+#define BIT_BCNERR_CNT_CCA_8822C(x) \
+ (((x) & BIT_MASK_BCNERR_CNT_CCA_8822C) \
+ << BIT_SHIFT_BCNERR_CNT_CCA_8822C)
+#define BITS_BCNERR_CNT_CCA_8822C \
+ (BIT_MASK_BCNERR_CNT_CCA_8822C << BIT_SHIFT_BCNERR_CNT_CCA_8822C)
+#define BIT_CLEAR_BCNERR_CNT_CCA_8822C(x) ((x) & (~BITS_BCNERR_CNT_CCA_8822C))
+#define BIT_GET_BCNERR_CNT_CCA_8822C(x) \
+ (((x) >> BIT_SHIFT_BCNERR_CNT_CCA_8822C) & \
+ BIT_MASK_BCNERR_CNT_CCA_8822C)
+#define BIT_SET_BCNERR_CNT_CCA_8822C(x, v) \
+ (BIT_CLEAR_BCNERR_CNT_CCA_8822C(x) | BIT_BCNERR_CNT_CCA_8822C(v))
+
+/* 2 REG_BCNERR_CNT_2_8822C */
+
+#define BIT_SHIFT_BCNERR_CNT_EDCCA_8822C 0
+#define BIT_MASK_BCNERR_CNT_EDCCA_8822C 0xff
+#define BIT_BCNERR_CNT_EDCCA_8822C(x) \
+ (((x) & BIT_MASK_BCNERR_CNT_EDCCA_8822C) \
+ << BIT_SHIFT_BCNERR_CNT_EDCCA_8822C)
+#define BITS_BCNERR_CNT_EDCCA_8822C \
+ (BIT_MASK_BCNERR_CNT_EDCCA_8822C << BIT_SHIFT_BCNERR_CNT_EDCCA_8822C)
+#define BIT_CLEAR_BCNERR_CNT_EDCCA_8822C(x) \
+ ((x) & (~BITS_BCNERR_CNT_EDCCA_8822C))
+#define BIT_GET_BCNERR_CNT_EDCCA_8822C(x) \
+ (((x) >> BIT_SHIFT_BCNERR_CNT_EDCCA_8822C) & \
+ BIT_MASK_BCNERR_CNT_EDCCA_8822C)
+#define BIT_SET_BCNERR_CNT_EDCCA_8822C(x, v) \
+ (BIT_CLEAR_BCNERR_CNT_EDCCA_8822C(x) | BIT_BCNERR_CNT_EDCCA_8822C(v))
+
+/* 2 REG_NOA_PARAM_8822C */
+
+#define BIT_SHIFT_NOA_DURATION_V1_8822C 0
+#define BIT_MASK_NOA_DURATION_V1_8822C 0xffffffffL
+#define BIT_NOA_DURATION_V1_8822C(x) \
+ (((x) & BIT_MASK_NOA_DURATION_V1_8822C) \
+ << BIT_SHIFT_NOA_DURATION_V1_8822C)
+#define BITS_NOA_DURATION_V1_8822C \
+ (BIT_MASK_NOA_DURATION_V1_8822C << BIT_SHIFT_NOA_DURATION_V1_8822C)
+#define BIT_CLEAR_NOA_DURATION_V1_8822C(x) ((x) & (~BITS_NOA_DURATION_V1_8822C))
+#define BIT_GET_NOA_DURATION_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_NOA_DURATION_V1_8822C) & \
+ BIT_MASK_NOA_DURATION_V1_8822C)
+#define BIT_SET_NOA_DURATION_V1_8822C(x, v) \
+ (BIT_CLEAR_NOA_DURATION_V1_8822C(x) | BIT_NOA_DURATION_V1_8822C(v))
+
+/* 2 REG_NOA_PARAM_1_8822C */
+
+#define BIT_SHIFT_NOA_INTERVAL_V1_8822C 0
+#define BIT_MASK_NOA_INTERVAL_V1_8822C 0xffffffffL
+#define BIT_NOA_INTERVAL_V1_8822C(x) \
+ (((x) & BIT_MASK_NOA_INTERVAL_V1_8822C) \
+ << BIT_SHIFT_NOA_INTERVAL_V1_8822C)
+#define BITS_NOA_INTERVAL_V1_8822C \
+ (BIT_MASK_NOA_INTERVAL_V1_8822C << BIT_SHIFT_NOA_INTERVAL_V1_8822C)
+#define BIT_CLEAR_NOA_INTERVAL_V1_8822C(x) ((x) & (~BITS_NOA_INTERVAL_V1_8822C))
+#define BIT_GET_NOA_INTERVAL_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_NOA_INTERVAL_V1_8822C) & \
+ BIT_MASK_NOA_INTERVAL_V1_8822C)
+#define BIT_SET_NOA_INTERVAL_V1_8822C(x, v) \
+ (BIT_CLEAR_NOA_INTERVAL_V1_8822C(x) | BIT_NOA_INTERVAL_V1_8822C(v))
+
+/* 2 REG_NOA_PARAM_2_8822C */
+
+#define BIT_SHIFT_NOA_START_TIME_V1_8822C 0
+#define BIT_MASK_NOA_START_TIME_V1_8822C 0xffffffffL
+#define BIT_NOA_START_TIME_V1_8822C(x) \
+ (((x) & BIT_MASK_NOA_START_TIME_V1_8822C) \
+ << BIT_SHIFT_NOA_START_TIME_V1_8822C)
+#define BITS_NOA_START_TIME_V1_8822C \
+ (BIT_MASK_NOA_START_TIME_V1_8822C << BIT_SHIFT_NOA_START_TIME_V1_8822C)
+#define BIT_CLEAR_NOA_START_TIME_V1_8822C(x) \
+ ((x) & (~BITS_NOA_START_TIME_V1_8822C))
+#define BIT_GET_NOA_START_TIME_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_NOA_START_TIME_V1_8822C) & \
+ BIT_MASK_NOA_START_TIME_V1_8822C)
+#define BIT_SET_NOA_START_TIME_V1_8822C(x, v) \
+ (BIT_CLEAR_NOA_START_TIME_V1_8822C(x) | BIT_NOA_START_TIME_V1_8822C(v))
+
+/* 2 REG_NOA_PARAM_3_8822C */
+
+#define BIT_SHIFT_NOA_COUNT_V1_8822C 0
+#define BIT_MASK_NOA_COUNT_V1_8822C 0xffffffffL
+#define BIT_NOA_COUNT_V1_8822C(x) \
+ (((x) & BIT_MASK_NOA_COUNT_V1_8822C) << BIT_SHIFT_NOA_COUNT_V1_8822C)
+#define BITS_NOA_COUNT_V1_8822C \
+ (BIT_MASK_NOA_COUNT_V1_8822C << BIT_SHIFT_NOA_COUNT_V1_8822C)
+#define BIT_CLEAR_NOA_COUNT_V1_8822C(x) ((x) & (~BITS_NOA_COUNT_V1_8822C))
+#define BIT_GET_NOA_COUNT_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_NOA_COUNT_V1_8822C) & BIT_MASK_NOA_COUNT_V1_8822C)
+#define BIT_SET_NOA_COUNT_V1_8822C(x, v) \
+ (BIT_CLEAR_NOA_COUNT_V1_8822C(x) | BIT_NOA_COUNT_V1_8822C(v))
+
+/* 2 REG_P2P_RST_8822C */
+#define BIT_P2P2_PWR_RST1_8822C BIT(5)
+#define BIT_P2P2_PWR_RST0_8822C BIT(4)
+#define BIT_P2P1_PWR_RST1_8822C BIT(3)
+#define BIT_P2P1_PWR_RST0_8822C BIT(2)
+#define BIT_P2P_PWR_RST1_V1_8822C BIT(1)
+#define BIT_P2P_PWR_RST0_V1_8822C BIT(0)
+
+/* 2 REG_SCHEDULER_RST_8822C */
+#define BIT_SYNC_CLI_ONCE_RIGHT_NOW_8822C BIT(2)
+#define BIT_SYNC_CLI_ONCE_BY_TBTT_8822C BIT(1)
+#define BIT_SCHEDULER_RST_V1_8822C BIT(0)
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_SCH_DBG_VALUE_8822C */
+
+#define BIT_SHIFT_SCH_DBG_VALUE_8822C 0
+#define BIT_MASK_SCH_DBG_VALUE_8822C 0xffffffffL
+#define BIT_SCH_DBG_VALUE_8822C(x) \
+ (((x) & BIT_MASK_SCH_DBG_VALUE_8822C) << BIT_SHIFT_SCH_DBG_VALUE_8822C)
+#define BITS_SCH_DBG_VALUE_8822C \
+ (BIT_MASK_SCH_DBG_VALUE_8822C << BIT_SHIFT_SCH_DBG_VALUE_8822C)
+#define BIT_CLEAR_SCH_DBG_VALUE_8822C(x) ((x) & (~BITS_SCH_DBG_VALUE_8822C))
+#define BIT_GET_SCH_DBG_VALUE_8822C(x) \
+ (((x) >> BIT_SHIFT_SCH_DBG_VALUE_8822C) & BIT_MASK_SCH_DBG_VALUE_8822C)
+#define BIT_SET_SCH_DBG_VALUE_8822C(x, v) \
+ (BIT_CLEAR_SCH_DBG_VALUE_8822C(x) | BIT_SCH_DBG_VALUE_8822C(v))
+
+/* 2 REG_SCH_TXCMD_8822C */
+
+#define BIT_SHIFT_SCH_TXCMD_8822C 0
+#define BIT_MASK_SCH_TXCMD_8822C 0xffffffffL
+#define BIT_SCH_TXCMD_8822C(x) \
+ (((x) & BIT_MASK_SCH_TXCMD_8822C) << BIT_SHIFT_SCH_TXCMD_8822C)
+#define BITS_SCH_TXCMD_8822C \
+ (BIT_MASK_SCH_TXCMD_8822C << BIT_SHIFT_SCH_TXCMD_8822C)
+#define BIT_CLEAR_SCH_TXCMD_8822C(x) ((x) & (~BITS_SCH_TXCMD_8822C))
+#define BIT_GET_SCH_TXCMD_8822C(x) \
+ (((x) >> BIT_SHIFT_SCH_TXCMD_8822C) & BIT_MASK_SCH_TXCMD_8822C)
+#define BIT_SET_SCH_TXCMD_8822C(x, v) \
+ (BIT_CLEAR_SCH_TXCMD_8822C(x) | BIT_SCH_TXCMD_8822C(v))
+
+/* 2 REG_PAGE5_DUMMY_8822C */
+
+/* 2 REG_CPUMGQ_TX_TIMER_8822C */
+
+#define BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822C 0
+#define BIT_MASK_CPUMGQ_TX_TIMER_V1_8822C 0xffffffffL
+#define BIT_CPUMGQ_TX_TIMER_V1_8822C(x) \
+ (((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8822C) \
+ << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822C)
+#define BITS_CPUMGQ_TX_TIMER_V1_8822C \
+ (BIT_MASK_CPUMGQ_TX_TIMER_V1_8822C \
+ << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822C)
+#define BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8822C(x) \
+ ((x) & (~BITS_CPUMGQ_TX_TIMER_V1_8822C))
+#define BIT_GET_CPUMGQ_TX_TIMER_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8822C) & \
+ BIT_MASK_CPUMGQ_TX_TIMER_V1_8822C)
+#define BIT_SET_CPUMGQ_TX_TIMER_V1_8822C(x, v) \
+ (BIT_CLEAR_CPUMGQ_TX_TIMER_V1_8822C(x) | \
+ BIT_CPUMGQ_TX_TIMER_V1_8822C(v))
+
+/* 2 REG_PS_TIMER_A_8822C */
+
+#define BIT_SHIFT_PS_TIMER_A_V1_8822C 0
+#define BIT_MASK_PS_TIMER_A_V1_8822C 0xffffffffL
+#define BIT_PS_TIMER_A_V1_8822C(x) \
+ (((x) & BIT_MASK_PS_TIMER_A_V1_8822C) << BIT_SHIFT_PS_TIMER_A_V1_8822C)
+#define BITS_PS_TIMER_A_V1_8822C \
+ (BIT_MASK_PS_TIMER_A_V1_8822C << BIT_SHIFT_PS_TIMER_A_V1_8822C)
+#define BIT_CLEAR_PS_TIMER_A_V1_8822C(x) ((x) & (~BITS_PS_TIMER_A_V1_8822C))
+#define BIT_GET_PS_TIMER_A_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_A_V1_8822C) & BIT_MASK_PS_TIMER_A_V1_8822C)
+#define BIT_SET_PS_TIMER_A_V1_8822C(x, v) \
+ (BIT_CLEAR_PS_TIMER_A_V1_8822C(x) | BIT_PS_TIMER_A_V1_8822C(v))
+
+/* 2 REG_PS_TIMER_B_8822C */
+
+#define BIT_SHIFT_PS_TIMER_B_V1_8822C 0
+#define BIT_MASK_PS_TIMER_B_V1_8822C 0xffffffffL
+#define BIT_PS_TIMER_B_V1_8822C(x) \
+ (((x) & BIT_MASK_PS_TIMER_B_V1_8822C) << BIT_SHIFT_PS_TIMER_B_V1_8822C)
+#define BITS_PS_TIMER_B_V1_8822C \
+ (BIT_MASK_PS_TIMER_B_V1_8822C << BIT_SHIFT_PS_TIMER_B_V1_8822C)
+#define BIT_CLEAR_PS_TIMER_B_V1_8822C(x) ((x) & (~BITS_PS_TIMER_B_V1_8822C))
+#define BIT_GET_PS_TIMER_B_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_B_V1_8822C) & BIT_MASK_PS_TIMER_B_V1_8822C)
+#define BIT_SET_PS_TIMER_B_V1_8822C(x, v) \
+ (BIT_CLEAR_PS_TIMER_B_V1_8822C(x) | BIT_PS_TIMER_B_V1_8822C(v))
+
+/* 2 REG_PS_TIMER_C_8822C */
+
+#define BIT_SHIFT_PS_TIMER_C_V1_8822C 0
+#define BIT_MASK_PS_TIMER_C_V1_8822C 0xffffffffL
+#define BIT_PS_TIMER_C_V1_8822C(x) \
+ (((x) & BIT_MASK_PS_TIMER_C_V1_8822C) << BIT_SHIFT_PS_TIMER_C_V1_8822C)
+#define BITS_PS_TIMER_C_V1_8822C \
+ (BIT_MASK_PS_TIMER_C_V1_8822C << BIT_SHIFT_PS_TIMER_C_V1_8822C)
+#define BIT_CLEAR_PS_TIMER_C_V1_8822C(x) ((x) & (~BITS_PS_TIMER_C_V1_8822C))
+#define BIT_GET_PS_TIMER_C_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_C_V1_8822C) & BIT_MASK_PS_TIMER_C_V1_8822C)
+#define BIT_SET_PS_TIMER_C_V1_8822C(x, v) \
+ (BIT_CLEAR_PS_TIMER_C_V1_8822C(x) | BIT_PS_TIMER_C_V1_8822C(v))
+
+/* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8822C */
+#define BIT_CPUMGQ_TIMER_EN_8822C BIT(31)
+#define BIT_CPUMGQ_TX_EN_8822C BIT(28)
+
+#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822C 24
+#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822C 0x7
+#define BIT_CPUMGQ_TIMER_TSF_SEL_8822C(x) \
+ (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822C) \
+ << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822C)
+#define BITS_CPUMGQ_TIMER_TSF_SEL_8822C \
+ (BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822C \
+ << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822C)
+#define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8822C(x) \
+ ((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL_8822C))
+#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8822C) & \
+ BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8822C)
+#define BIT_SET_CPUMGQ_TIMER_TSF_SEL_8822C(x, v) \
+ (BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL_8822C(x) | \
+ BIT_CPUMGQ_TIMER_TSF_SEL_8822C(v))
+
+#define BIT_PS_TIMER_C_EN_8822C BIT(23)
+
+#define BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822C 16
+#define BIT_MASK_PS_TIMER_C_TSF_SEL_8822C 0x7
+#define BIT_PS_TIMER_C_TSF_SEL_8822C(x) \
+ (((x) & BIT_MASK_PS_TIMER_C_TSF_SEL_8822C) \
+ << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822C)
+#define BITS_PS_TIMER_C_TSF_SEL_8822C \
+ (BIT_MASK_PS_TIMER_C_TSF_SEL_8822C \
+ << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822C)
+#define BIT_CLEAR_PS_TIMER_C_TSF_SEL_8822C(x) \
+ ((x) & (~BITS_PS_TIMER_C_TSF_SEL_8822C))
+#define BIT_GET_PS_TIMER_C_TSF_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL_8822C) & \
+ BIT_MASK_PS_TIMER_C_TSF_SEL_8822C)
+#define BIT_SET_PS_TIMER_C_TSF_SEL_8822C(x, v) \
+ (BIT_CLEAR_PS_TIMER_C_TSF_SEL_8822C(x) | \
+ BIT_PS_TIMER_C_TSF_SEL_8822C(v))
+
+#define BIT_PS_TIMER_B_EN_8822C BIT(15)
+
+#define BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822C 8
+#define BIT_MASK_PS_TIMER_B_TSF_SEL_8822C 0x7
+#define BIT_PS_TIMER_B_TSF_SEL_8822C(x) \
+ (((x) & BIT_MASK_PS_TIMER_B_TSF_SEL_8822C) \
+ << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822C)
+#define BITS_PS_TIMER_B_TSF_SEL_8822C \
+ (BIT_MASK_PS_TIMER_B_TSF_SEL_8822C \
+ << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822C)
+#define BIT_CLEAR_PS_TIMER_B_TSF_SEL_8822C(x) \
+ ((x) & (~BITS_PS_TIMER_B_TSF_SEL_8822C))
+#define BIT_GET_PS_TIMER_B_TSF_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL_8822C) & \
+ BIT_MASK_PS_TIMER_B_TSF_SEL_8822C)
+#define BIT_SET_PS_TIMER_B_TSF_SEL_8822C(x, v) \
+ (BIT_CLEAR_PS_TIMER_B_TSF_SEL_8822C(x) | \
+ BIT_PS_TIMER_B_TSF_SEL_8822C(v))
+
+#define BIT_PS_TIMER_A_EN_8822C BIT(7)
+
+#define BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822C 0
+#define BIT_MASK_PS_TIMER_A_TSF_SEL_8822C 0x7
+#define BIT_PS_TIMER_A_TSF_SEL_8822C(x) \
+ (((x) & BIT_MASK_PS_TIMER_A_TSF_SEL_8822C) \
+ << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822C)
+#define BITS_PS_TIMER_A_TSF_SEL_8822C \
+ (BIT_MASK_PS_TIMER_A_TSF_SEL_8822C \
+ << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822C)
+#define BIT_CLEAR_PS_TIMER_A_TSF_SEL_8822C(x) \
+ ((x) & (~BITS_PS_TIMER_A_TSF_SEL_8822C))
+#define BIT_GET_PS_TIMER_A_TSF_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL_8822C) & \
+ BIT_MASK_PS_TIMER_A_TSF_SEL_8822C)
+#define BIT_SET_PS_TIMER_A_TSF_SEL_8822C(x, v) \
+ (BIT_CLEAR_PS_TIMER_A_TSF_SEL_8822C(x) | \
+ BIT_PS_TIMER_A_TSF_SEL_8822C(v))
+
+/* 2 REG_CPUMGQ_TX_TIMER_EARLY_8822C */
+
+#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822C 0
+#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822C 0xff
+#define BIT_CPUMGQ_TX_TIMER_EARLY_8822C(x) \
+ (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822C) \
+ << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822C)
+#define BITS_CPUMGQ_TX_TIMER_EARLY_8822C \
+ (BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822C \
+ << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822C)
+#define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8822C(x) \
+ ((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY_8822C))
+#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_8822C(x) \
+ (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8822C) & \
+ BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8822C)
+#define BIT_SET_CPUMGQ_TX_TIMER_EARLY_8822C(x, v) \
+ (BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY_8822C(x) | \
+ BIT_CPUMGQ_TX_TIMER_EARLY_8822C(v))
+
+/* 2 REG_PS_TIMER_A_EARLY_8822C */
+
+#define BIT_SHIFT_PS_TIMER_A_EARLY_8822C 0
+#define BIT_MASK_PS_TIMER_A_EARLY_8822C 0xff
+#define BIT_PS_TIMER_A_EARLY_8822C(x) \
+ (((x) & BIT_MASK_PS_TIMER_A_EARLY_8822C) \
+ << BIT_SHIFT_PS_TIMER_A_EARLY_8822C)
+#define BITS_PS_TIMER_A_EARLY_8822C \
+ (BIT_MASK_PS_TIMER_A_EARLY_8822C << BIT_SHIFT_PS_TIMER_A_EARLY_8822C)
+#define BIT_CLEAR_PS_TIMER_A_EARLY_8822C(x) \
+ ((x) & (~BITS_PS_TIMER_A_EARLY_8822C))
+#define BIT_GET_PS_TIMER_A_EARLY_8822C(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_A_EARLY_8822C) & \
+ BIT_MASK_PS_TIMER_A_EARLY_8822C)
+#define BIT_SET_PS_TIMER_A_EARLY_8822C(x, v) \
+ (BIT_CLEAR_PS_TIMER_A_EARLY_8822C(x) | BIT_PS_TIMER_A_EARLY_8822C(v))
+
+/* 2 REG_PS_TIMER_B_EARLY_8822C */
+
+#define BIT_SHIFT_PS_TIMER_B_EARLY_8822C 0
+#define BIT_MASK_PS_TIMER_B_EARLY_8822C 0xff
+#define BIT_PS_TIMER_B_EARLY_8822C(x) \
+ (((x) & BIT_MASK_PS_TIMER_B_EARLY_8822C) \
+ << BIT_SHIFT_PS_TIMER_B_EARLY_8822C)
+#define BITS_PS_TIMER_B_EARLY_8822C \
+ (BIT_MASK_PS_TIMER_B_EARLY_8822C << BIT_SHIFT_PS_TIMER_B_EARLY_8822C)
+#define BIT_CLEAR_PS_TIMER_B_EARLY_8822C(x) \
+ ((x) & (~BITS_PS_TIMER_B_EARLY_8822C))
+#define BIT_GET_PS_TIMER_B_EARLY_8822C(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_B_EARLY_8822C) & \
+ BIT_MASK_PS_TIMER_B_EARLY_8822C)
+#define BIT_SET_PS_TIMER_B_EARLY_8822C(x, v) \
+ (BIT_CLEAR_PS_TIMER_B_EARLY_8822C(x) | BIT_PS_TIMER_B_EARLY_8822C(v))
+
+/* 2 REG_PS_TIMER_C_EARLY_8822C */
+
+#define BIT_SHIFT_PS_TIMER_C_EARLY_8822C 0
+#define BIT_MASK_PS_TIMER_C_EARLY_8822C 0xff
+#define BIT_PS_TIMER_C_EARLY_8822C(x) \
+ (((x) & BIT_MASK_PS_TIMER_C_EARLY_8822C) \
+ << BIT_SHIFT_PS_TIMER_C_EARLY_8822C)
+#define BITS_PS_TIMER_C_EARLY_8822C \
+ (BIT_MASK_PS_TIMER_C_EARLY_8822C << BIT_SHIFT_PS_TIMER_C_EARLY_8822C)
+#define BIT_CLEAR_PS_TIMER_C_EARLY_8822C(x) \
+ ((x) & (~BITS_PS_TIMER_C_EARLY_8822C))
+#define BIT_GET_PS_TIMER_C_EARLY_8822C(x) \
+ (((x) >> BIT_SHIFT_PS_TIMER_C_EARLY_8822C) & \
+ BIT_MASK_PS_TIMER_C_EARLY_8822C)
+#define BIT_SET_PS_TIMER_C_EARLY_8822C(x, v) \
+ (BIT_CLEAR_PS_TIMER_C_EARLY_8822C(x) | BIT_PS_TIMER_C_EARLY_8822C(v))
+
+/* 2 REG_CPUMGQ_PARAMETER_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+#define BIT_MAC_STOP_CPUMGQ_8822C BIT(16)
+
+#define BIT_SHIFT_CW_8822C 8
+#define BIT_MASK_CW_8822C 0xff
+#define BIT_CW_8822C(x) (((x) & BIT_MASK_CW_8822C) << BIT_SHIFT_CW_8822C)
+#define BITS_CW_8822C (BIT_MASK_CW_8822C << BIT_SHIFT_CW_8822C)
+#define BIT_CLEAR_CW_8822C(x) ((x) & (~BITS_CW_8822C))
+#define BIT_GET_CW_8822C(x) (((x) >> BIT_SHIFT_CW_8822C) & BIT_MASK_CW_8822C)
+#define BIT_SET_CW_8822C(x, v) (BIT_CLEAR_CW_8822C(x) | BIT_CW_8822C(v))
+
+#define BIT_SHIFT_AIFS_8822C 0
+#define BIT_MASK_AIFS_8822C 0xff
+#define BIT_AIFS_8822C(x) (((x) & BIT_MASK_AIFS_8822C) << BIT_SHIFT_AIFS_8822C)
+#define BITS_AIFS_8822C (BIT_MASK_AIFS_8822C << BIT_SHIFT_AIFS_8822C)
+#define BIT_CLEAR_AIFS_8822C(x) ((x) & (~BITS_AIFS_8822C))
+#define BIT_GET_AIFS_8822C(x) \
+ (((x) >> BIT_SHIFT_AIFS_8822C) & BIT_MASK_AIFS_8822C)
+#define BIT_SET_AIFS_8822C(x, v) (BIT_CLEAR_AIFS_8822C(x) | BIT_AIFS_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_TSF_SYNC_ADJ_8822C */
+
+#define BIT_SHIFT_R_P0_TSFT_ADJ_VAL_8822C 16
+#define BIT_MASK_R_P0_TSFT_ADJ_VAL_8822C 0xffff
+#define BIT_R_P0_TSFT_ADJ_VAL_8822C(x) \
+ (((x) & BIT_MASK_R_P0_TSFT_ADJ_VAL_8822C) \
+ << BIT_SHIFT_R_P0_TSFT_ADJ_VAL_8822C)
+#define BITS_R_P0_TSFT_ADJ_VAL_8822C \
+ (BIT_MASK_R_P0_TSFT_ADJ_VAL_8822C << BIT_SHIFT_R_P0_TSFT_ADJ_VAL_8822C)
+#define BIT_CLEAR_R_P0_TSFT_ADJ_VAL_8822C(x) \
+ ((x) & (~BITS_R_P0_TSFT_ADJ_VAL_8822C))
+#define BIT_GET_R_P0_TSFT_ADJ_VAL_8822C(x) \
+ (((x) >> BIT_SHIFT_R_P0_TSFT_ADJ_VAL_8822C) & \
+ BIT_MASK_R_P0_TSFT_ADJ_VAL_8822C)
+#define BIT_SET_R_P0_TSFT_ADJ_VAL_8822C(x, v) \
+ (BIT_CLEAR_R_P0_TSFT_ADJ_VAL_8822C(x) | BIT_R_P0_TSFT_ADJ_VAL_8822C(v))
+
+#define BIT_R_X_COMP_Y_OVER_8822C BIT(8)
+
+#define BIT_SHIFT_R_X_SYNC_SEL_8822C 3
+#define BIT_MASK_R_X_SYNC_SEL_8822C 0x7
+#define BIT_R_X_SYNC_SEL_8822C(x) \
+ (((x) & BIT_MASK_R_X_SYNC_SEL_8822C) << BIT_SHIFT_R_X_SYNC_SEL_8822C)
+#define BITS_R_X_SYNC_SEL_8822C \
+ (BIT_MASK_R_X_SYNC_SEL_8822C << BIT_SHIFT_R_X_SYNC_SEL_8822C)
+#define BIT_CLEAR_R_X_SYNC_SEL_8822C(x) ((x) & (~BITS_R_X_SYNC_SEL_8822C))
+#define BIT_GET_R_X_SYNC_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_R_X_SYNC_SEL_8822C) & BIT_MASK_R_X_SYNC_SEL_8822C)
+#define BIT_SET_R_X_SYNC_SEL_8822C(x, v) \
+ (BIT_CLEAR_R_X_SYNC_SEL_8822C(x) | BIT_R_X_SYNC_SEL_8822C(v))
+
+#define BIT_SHIFT_R_SYNC_Y_SEL_8822C 0
+#define BIT_MASK_R_SYNC_Y_SEL_8822C 0x7
+#define BIT_R_SYNC_Y_SEL_8822C(x) \
+ (((x) & BIT_MASK_R_SYNC_Y_SEL_8822C) << BIT_SHIFT_R_SYNC_Y_SEL_8822C)
+#define BITS_R_SYNC_Y_SEL_8822C \
+ (BIT_MASK_R_SYNC_Y_SEL_8822C << BIT_SHIFT_R_SYNC_Y_SEL_8822C)
+#define BIT_CLEAR_R_SYNC_Y_SEL_8822C(x) ((x) & (~BITS_R_SYNC_Y_SEL_8822C))
+#define BIT_GET_R_SYNC_Y_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_R_SYNC_Y_SEL_8822C) & BIT_MASK_R_SYNC_Y_SEL_8822C)
+#define BIT_SET_R_SYNC_Y_SEL_8822C(x, v) \
+ (BIT_CLEAR_R_SYNC_Y_SEL_8822C(x) | BIT_R_SYNC_Y_SEL_8822C(v))
+
+/* 2 REG_TSF_ADJ_VLAUE_8822C */
+
+#define BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL_8822C 16
+#define BIT_MASK_R_CLI1_TSFT_ADJ_VAL_8822C 0xffff
+#define BIT_R_CLI1_TSFT_ADJ_VAL_8822C(x) \
+ (((x) & BIT_MASK_R_CLI1_TSFT_ADJ_VAL_8822C) \
+ << BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL_8822C)
+#define BITS_R_CLI1_TSFT_ADJ_VAL_8822C \
+ (BIT_MASK_R_CLI1_TSFT_ADJ_VAL_8822C \
+ << BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL_8822C)
+#define BIT_CLEAR_R_CLI1_TSFT_ADJ_VAL_8822C(x) \
+ ((x) & (~BITS_R_CLI1_TSFT_ADJ_VAL_8822C))
+#define BIT_GET_R_CLI1_TSFT_ADJ_VAL_8822C(x) \
+ (((x) >> BIT_SHIFT_R_CLI1_TSFT_ADJ_VAL_8822C) & \
+ BIT_MASK_R_CLI1_TSFT_ADJ_VAL_8822C)
+#define BIT_SET_R_CLI1_TSFT_ADJ_VAL_8822C(x, v) \
+ (BIT_CLEAR_R_CLI1_TSFT_ADJ_VAL_8822C(x) | \
+ BIT_R_CLI1_TSFT_ADJ_VAL_8822C(v))
+
+#define BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL_8822C 0
+#define BIT_MASK_R_CLI0_TSFT_ADJ_VAL_8822C 0xffff
+#define BIT_R_CLI0_TSFT_ADJ_VAL_8822C(x) \
+ (((x) & BIT_MASK_R_CLI0_TSFT_ADJ_VAL_8822C) \
+ << BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL_8822C)
+#define BITS_R_CLI0_TSFT_ADJ_VAL_8822C \
+ (BIT_MASK_R_CLI0_TSFT_ADJ_VAL_8822C \
+ << BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL_8822C)
+#define BIT_CLEAR_R_CLI0_TSFT_ADJ_VAL_8822C(x) \
+ ((x) & (~BITS_R_CLI0_TSFT_ADJ_VAL_8822C))
+#define BIT_GET_R_CLI0_TSFT_ADJ_VAL_8822C(x) \
+ (((x) >> BIT_SHIFT_R_CLI0_TSFT_ADJ_VAL_8822C) & \
+ BIT_MASK_R_CLI0_TSFT_ADJ_VAL_8822C)
+#define BIT_SET_R_CLI0_TSFT_ADJ_VAL_8822C(x, v) \
+ (BIT_CLEAR_R_CLI0_TSFT_ADJ_VAL_8822C(x) | \
+ BIT_R_CLI0_TSFT_ADJ_VAL_8822C(v))
+
+/* 2 REG_TSF_ADJ_VLAUE_2_8822C */
+
+#define BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL_8822C 16
+#define BIT_MASK_R_CLI3_TSFT_ADJ_VAL_8822C 0xffff
+#define BIT_R_CLI3_TSFT_ADJ_VAL_8822C(x) \
+ (((x) & BIT_MASK_R_CLI3_TSFT_ADJ_VAL_8822C) \
+ << BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL_8822C)
+#define BITS_R_CLI3_TSFT_ADJ_VAL_8822C \
+ (BIT_MASK_R_CLI3_TSFT_ADJ_VAL_8822C \
+ << BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL_8822C)
+#define BIT_CLEAR_R_CLI3_TSFT_ADJ_VAL_8822C(x) \
+ ((x) & (~BITS_R_CLI3_TSFT_ADJ_VAL_8822C))
+#define BIT_GET_R_CLI3_TSFT_ADJ_VAL_8822C(x) \
+ (((x) >> BIT_SHIFT_R_CLI3_TSFT_ADJ_VAL_8822C) & \
+ BIT_MASK_R_CLI3_TSFT_ADJ_VAL_8822C)
+#define BIT_SET_R_CLI3_TSFT_ADJ_VAL_8822C(x, v) \
+ (BIT_CLEAR_R_CLI3_TSFT_ADJ_VAL_8822C(x) | \
+ BIT_R_CLI3_TSFT_ADJ_VAL_8822C(v))
+
+#define BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL_8822C 0
+#define BIT_MASK_R_CLI2_TSFT_ADJ_VAL_8822C 0xffff
+#define BIT_R_CLI2_TSFT_ADJ_VAL_8822C(x) \
+ (((x) & BIT_MASK_R_CLI2_TSFT_ADJ_VAL_8822C) \
+ << BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL_8822C)
+#define BITS_R_CLI2_TSFT_ADJ_VAL_8822C \
+ (BIT_MASK_R_CLI2_TSFT_ADJ_VAL_8822C \
+ << BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL_8822C)
+#define BIT_CLEAR_R_CLI2_TSFT_ADJ_VAL_8822C(x) \
+ ((x) & (~BITS_R_CLI2_TSFT_ADJ_VAL_8822C))
+#define BIT_GET_R_CLI2_TSFT_ADJ_VAL_8822C(x) \
+ (((x) >> BIT_SHIFT_R_CLI2_TSFT_ADJ_VAL_8822C) & \
+ BIT_MASK_R_CLI2_TSFT_ADJ_VAL_8822C)
+#define BIT_SET_R_CLI2_TSFT_ADJ_VAL_8822C(x, v) \
+ (BIT_CLEAR_R_CLI2_TSFT_ADJ_VAL_8822C(x) | \
+ BIT_R_CLI2_TSFT_ADJ_VAL_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_P2PPS_HW_AUTO_PAUSE_CTRL_8822C */
+#define BIT_P2PPS_NOA_STOP_TX_HANG_8822C BIT(31)
+#define BIT_P2PPS_MACID_PAUSE_EN_8822C BIT(11)
+#define BIT_P2PPS__MGQ_PAUSE_8822C BIT(10)
+#define BIT_P2PPS__HIQ_PAUSE_8822C BIT(9)
+#define BIT_P2PPS__BCNQ_PAUSE_8822C BIT(8)
+
+#define BIT_SHIFT_P2PPS_MACID_PAUSE_8822C 0
+#define BIT_MASK_P2PPS_MACID_PAUSE_8822C 0xff
+#define BIT_P2PPS_MACID_PAUSE_8822C(x) \
+ (((x) & BIT_MASK_P2PPS_MACID_PAUSE_8822C) \
+ << BIT_SHIFT_P2PPS_MACID_PAUSE_8822C)
+#define BITS_P2PPS_MACID_PAUSE_8822C \
+ (BIT_MASK_P2PPS_MACID_PAUSE_8822C << BIT_SHIFT_P2PPS_MACID_PAUSE_8822C)
+#define BIT_CLEAR_P2PPS_MACID_PAUSE_8822C(x) \
+ ((x) & (~BITS_P2PPS_MACID_PAUSE_8822C))
+#define BIT_GET_P2PPS_MACID_PAUSE_8822C(x) \
+ (((x) >> BIT_SHIFT_P2PPS_MACID_PAUSE_8822C) & \
+ BIT_MASK_P2PPS_MACID_PAUSE_8822C)
+#define BIT_SET_P2PPS_MACID_PAUSE_8822C(x, v) \
+ (BIT_CLEAR_P2PPS_MACID_PAUSE_8822C(x) | BIT_P2PPS_MACID_PAUSE_8822C(v))
+
+/* 2 REG_P2PPS1_HW_AUTO_PAUSE_CTRL_8822C */
+#define BIT_P2PPS1_NOA_STOP_TX_HANG_8822C BIT(31)
+#define BIT_P2PPS1_MACID_PAUSE_EN_8822C BIT(11)
+#define BIT_P2PPS1__MGQ_PAUSE_8822C BIT(10)
+#define BIT_P2PPS1__HIQ_PAUSE_8822C BIT(9)
+#define BIT_P2PPS1__BCNQ_PAUSE_8822C BIT(8)
+
+#define BIT_SHIFT_P2PPS1_MACID_PAUSE_8822C 0
+#define BIT_MASK_P2PPS1_MACID_PAUSE_8822C 0xff
+#define BIT_P2PPS1_MACID_PAUSE_8822C(x) \
+ (((x) & BIT_MASK_P2PPS1_MACID_PAUSE_8822C) \
+ << BIT_SHIFT_P2PPS1_MACID_PAUSE_8822C)
+#define BITS_P2PPS1_MACID_PAUSE_8822C \
+ (BIT_MASK_P2PPS1_MACID_PAUSE_8822C \
+ << BIT_SHIFT_P2PPS1_MACID_PAUSE_8822C)
+#define BIT_CLEAR_P2PPS1_MACID_PAUSE_8822C(x) \
+ ((x) & (~BITS_P2PPS1_MACID_PAUSE_8822C))
+#define BIT_GET_P2PPS1_MACID_PAUSE_8822C(x) \
+ (((x) >> BIT_SHIFT_P2PPS1_MACID_PAUSE_8822C) & \
+ BIT_MASK_P2PPS1_MACID_PAUSE_8822C)
+#define BIT_SET_P2PPS1_MACID_PAUSE_8822C(x, v) \
+ (BIT_CLEAR_P2PPS1_MACID_PAUSE_8822C(x) | \
+ BIT_P2PPS1_MACID_PAUSE_8822C(v))
+
+/* 2 REG_P2PPS2_HW_AUTO_PAUSE_CTRL_8822C */
+#define BIT_P2PPS2_NOA_STOP_TX_HANG_8822C BIT(31)
+#define BIT_P2PPS2_MACID_PAUSE_EN_8822C BIT(11)
+#define BIT_P2PPS2__MGQ_PAUSE_8822C BIT(10)
+#define BIT_P2PPS2__HIQ_PAUSE_8822C BIT(9)
+#define BIT_P2PPS2__BCNQ_PAUSE_8822C BIT(8)
+
+#define BIT_SHIFT_P2PPS2_MACID_PAUSE_8822C 0
+#define BIT_MASK_P2PPS2_MACID_PAUSE_8822C 0xff
+#define BIT_P2PPS2_MACID_PAUSE_8822C(x) \
+ (((x) & BIT_MASK_P2PPS2_MACID_PAUSE_8822C) \
+ << BIT_SHIFT_P2PPS2_MACID_PAUSE_8822C)
+#define BITS_P2PPS2_MACID_PAUSE_8822C \
+ (BIT_MASK_P2PPS2_MACID_PAUSE_8822C \
+ << BIT_SHIFT_P2PPS2_MACID_PAUSE_8822C)
+#define BIT_CLEAR_P2PPS2_MACID_PAUSE_8822C(x) \
+ ((x) & (~BITS_P2PPS2_MACID_PAUSE_8822C))
+#define BIT_GET_P2PPS2_MACID_PAUSE_8822C(x) \
+ (((x) >> BIT_SHIFT_P2PPS2_MACID_PAUSE_8822C) & \
+ BIT_MASK_P2PPS2_MACID_PAUSE_8822C)
+#define BIT_SET_P2PPS2_MACID_PAUSE_8822C(x, v) \
+ (BIT_CLEAR_P2PPS2_MACID_PAUSE_8822C(x) | \
+ BIT_P2PPS2_MACID_PAUSE_8822C(v))
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_WMAC_CR_8822C (WMAC CR AND APSD CONTROL REGISTER) */
+#define BIT_IC_MACPHY_M_8822C BIT(0)
+
+/* 2 REG_WMAC_FWPKT_CR_8822C */
+#define BIT_FWEN_8822C BIT(7)
+#define BIT_PHYSTS_PKT_CTRL_8822C BIT(6)
+#define BIT_APPHDR_MIDSRCH_FAIL_8822C BIT(4)
+#define BIT_FWPARSING_EN_8822C BIT(3)
+
+#define BIT_SHIFT_APPEND_MHDR_LEN_8822C 0
+#define BIT_MASK_APPEND_MHDR_LEN_8822C 0x7
+#define BIT_APPEND_MHDR_LEN_8822C(x) \
+ (((x) & BIT_MASK_APPEND_MHDR_LEN_8822C) \
+ << BIT_SHIFT_APPEND_MHDR_LEN_8822C)
+#define BITS_APPEND_MHDR_LEN_8822C \
+ (BIT_MASK_APPEND_MHDR_LEN_8822C << BIT_SHIFT_APPEND_MHDR_LEN_8822C)
+#define BIT_CLEAR_APPEND_MHDR_LEN_8822C(x) ((x) & (~BITS_APPEND_MHDR_LEN_8822C))
+#define BIT_GET_APPEND_MHDR_LEN_8822C(x) \
+ (((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8822C) & \
+ BIT_MASK_APPEND_MHDR_LEN_8822C)
+#define BIT_SET_APPEND_MHDR_LEN_8822C(x, v) \
+ (BIT_CLEAR_APPEND_MHDR_LEN_8822C(x) | BIT_APPEND_MHDR_LEN_8822C(v))
+
+/* 2 REG_FW_STS_FILTER_8822C */
+#define BIT_DATA_FW_STS_FILTER_8822C BIT(2)
+#define BIT_CTRL_FW_STS_FILTER_8822C BIT(1)
+#define BIT_MGNT_FW_STS_FILTER_8822C BIT(0)
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_TCR_8822C (TRANSMISSION CONFIGURATION REGISTER) */
+#define BIT_WMAC_EN_RTS_ADDR_8822C BIT(31)
+#define BIT_WMAC_DISABLE_CCK_8822C BIT(30)
+#define BIT_WMAC_RAW_LEN_8822C BIT(29)
+#define BIT_WMAC_NOTX_IN_RXNDP_8822C BIT(28)
+#define BIT_WMAC_EN_EOF_8822C BIT(27)
+#define BIT_WMAC_BF_SEL_8822C BIT(26)
+#define BIT_WMAC_ANTMODE_SEL_8822C BIT(25)
+#define BIT_WMAC_TCRPWRMGT_HWCTL_8822C BIT(24)
+#define BIT_WMAC_SMOOTH_VAL_8822C BIT(23)
+#define BIT_WMAC_EN_SCRAM_INC_8822C BIT(22)
+#define BIT_UNDERFLOWEN_CMPLEN_SEL_8822C BIT(21)
+#define BIT_FETCH_MPDU_AFTER_WSEC_RDY_8822C BIT(20)
+#define BIT_WMAC_TCR_EN_20MST_8822C BIT(19)
+#define BIT_WMAC_DIS_SIGTA_8822C BIT(18)
+#define BIT_WMAC_DIS_A2B0_8822C BIT(17)
+#define BIT_WMAC_MSK_SIGBCRC_8822C BIT(16)
+#define BIT_WMAC_TCR_ERRSTEN_3_8822C BIT(15)
+#define BIT_WMAC_TCR_ERRSTEN_2_8822C BIT(14)
+#define BIT_WMAC_TCR_ERRSTEN_1_8822C BIT(13)
+#define BIT_WMAC_TCR_ERRSTEN_0_8822C BIT(12)
+#define BIT_WMAC_TCR_TXSK_PERPKT_8822C BIT(11)
+#define BIT_ICV_8822C BIT(10)
+#define BIT_CFEND_FORMAT_8822C BIT(9)
+#define BIT_CRC_8822C BIT(8)
+#define BIT_WMAC_TCRPWRMGT_HWDATA_EN_8822C BIT(7)
+#define BIT_PWR_ST_8822C BIT(6)
+#define BIT_WMAC_TCR_UPD_TIMIE_8822C BIT(5)
+#define BIT_WMAC_TCR_UPD_HGQMD_8822C BIT(4)
+#define BIT_VHTSIGA1_TXPS_8822C BIT(3)
+#define BIT_PAD_SEL_8822C BIT(2)
+#define BIT_DIS_GCLK_8822C BIT(1)
+#define BIT_WMAC_TCRPWRMGT_HWACT_EN_8822C BIT(0)
+
+/* 2 REG_RCR_8822C (RECEIVE CONFIGURATION REGISTER) */
+#define BIT_APP_FCS_8822C BIT(31)
+#define BIT_APP_MIC_8822C BIT(30)
+#define BIT_APP_ICV_8822C BIT(29)
+#define BIT_APP_PHYSTS_8822C BIT(28)
+#define BIT_APP_BASSN_8822C BIT(27)
+#define BIT_VHT_DACK_8822C BIT(26)
+#define BIT_TCPOFLD_EN_8822C BIT(25)
+#define BIT_ENMBID_8822C BIT(24)
+#define BIT_LSIGEN_8822C BIT(23)
+#define BIT_MFBEN_8822C BIT(22)
+#define BIT_DISCHKPPDLLEN_8822C BIT(21)
+#define BIT_PKTCTL_DLEN_8822C BIT(20)
+#define BIT_DISGCLK_8822C BIT(19)
+#define BIT_TIM_PARSER_EN_8822C BIT(18)
+#define BIT_BC_MD_EN_8822C BIT(17)
+#define BIT_UC_MD_EN_8822C BIT(16)
+#define BIT_RXSK_PERPKT_8822C BIT(15)
+#define BIT_HTC_LOC_CTRL_8822C BIT(14)
+#define BIT_ACK_WITH_CBSSID_DATA_OPTION_8822C BIT(13)
+#define BIT_RPFM_CAM_ENABLE_8822C BIT(12)
+#define BIT_TA_BCN_8822C BIT(11)
+#define BIT_DISDECMYPKT_8822C BIT(10)
+#define BIT_AICV_8822C BIT(9)
+#define BIT_ACRC32_8822C BIT(8)
+#define BIT_CBSSID_BCN_8822C BIT(7)
+#define BIT_CBSSID_DATA_8822C BIT(6)
+#define BIT_APWRMGT_8822C BIT(5)
+#define BIT_ADD3_8822C BIT(4)
+#define BIT_AB_8822C BIT(3)
+#define BIT_AM_8822C BIT(2)
+#define BIT_APM_8822C BIT(1)
+#define BIT_AAP_8822C BIT(0)
+
+/* 2 REG_RX_PKT_LIMIT_8822C (RX PACKET LENGTH LIMIT REGISTER) */
+
+#define BIT_SHIFT_RXPKTLMT_8822C 0
+#define BIT_MASK_RXPKTLMT_8822C 0x3f
+#define BIT_RXPKTLMT_8822C(x) \
+ (((x) & BIT_MASK_RXPKTLMT_8822C) << BIT_SHIFT_RXPKTLMT_8822C)
+#define BITS_RXPKTLMT_8822C \
+ (BIT_MASK_RXPKTLMT_8822C << BIT_SHIFT_RXPKTLMT_8822C)
+#define BIT_CLEAR_RXPKTLMT_8822C(x) ((x) & (~BITS_RXPKTLMT_8822C))
+#define BIT_GET_RXPKTLMT_8822C(x) \
+ (((x) >> BIT_SHIFT_RXPKTLMT_8822C) & BIT_MASK_RXPKTLMT_8822C)
+#define BIT_SET_RXPKTLMT_8822C(x, v) \
+ (BIT_CLEAR_RXPKTLMT_8822C(x) | BIT_RXPKTLMT_8822C(v))
+
+/* 2 REG_RX_DLK_TIME_8822C (RX DEADLOCK TIME REGISTER) */
+
+#define BIT_SHIFT_RX_DLK_TIME_8822C 0
+#define BIT_MASK_RX_DLK_TIME_8822C 0xff
+#define BIT_RX_DLK_TIME_8822C(x) \
+ (((x) & BIT_MASK_RX_DLK_TIME_8822C) << BIT_SHIFT_RX_DLK_TIME_8822C)
+#define BITS_RX_DLK_TIME_8822C \
+ (BIT_MASK_RX_DLK_TIME_8822C << BIT_SHIFT_RX_DLK_TIME_8822C)
+#define BIT_CLEAR_RX_DLK_TIME_8822C(x) ((x) & (~BITS_RX_DLK_TIME_8822C))
+#define BIT_GET_RX_DLK_TIME_8822C(x) \
+ (((x) >> BIT_SHIFT_RX_DLK_TIME_8822C) & BIT_MASK_RX_DLK_TIME_8822C)
+#define BIT_SET_RX_DLK_TIME_8822C(x, v) \
+ (BIT_CLEAR_RX_DLK_TIME_8822C(x) | BIT_RX_DLK_TIME_8822C(v))
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RX_DRVINFO_SZ_8822C (RX DRIVER INFO SIZE REGISTER) */
+#define BIT_PHYSTS_PER_PKT_MODE_8822C BIT(7)
+
+#define BIT_SHIFT_DRVINFO_SZ_V1_8822C 0
+#define BIT_MASK_DRVINFO_SZ_V1_8822C 0xf
+#define BIT_DRVINFO_SZ_V1_8822C(x) \
+ (((x) & BIT_MASK_DRVINFO_SZ_V1_8822C) << BIT_SHIFT_DRVINFO_SZ_V1_8822C)
+#define BITS_DRVINFO_SZ_V1_8822C \
+ (BIT_MASK_DRVINFO_SZ_V1_8822C << BIT_SHIFT_DRVINFO_SZ_V1_8822C)
+#define BIT_CLEAR_DRVINFO_SZ_V1_8822C(x) ((x) & (~BITS_DRVINFO_SZ_V1_8822C))
+#define BIT_GET_DRVINFO_SZ_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8822C) & BIT_MASK_DRVINFO_SZ_V1_8822C)
+#define BIT_SET_DRVINFO_SZ_V1_8822C(x, v) \
+ (BIT_CLEAR_DRVINFO_SZ_V1_8822C(x) | BIT_DRVINFO_SZ_V1_8822C(v))
+
+/* 2 REG_MACID_8822C (MAC ID REGISTER) */
+
+#define BIT_SHIFT_MACID_V1_8822C 0
+#define BIT_MASK_MACID_V1_8822C 0xffffffffL
+#define BIT_MACID_V1_8822C(x) \
+ (((x) & BIT_MASK_MACID_V1_8822C) << BIT_SHIFT_MACID_V1_8822C)
+#define BITS_MACID_V1_8822C \
+ (BIT_MASK_MACID_V1_8822C << BIT_SHIFT_MACID_V1_8822C)
+#define BIT_CLEAR_MACID_V1_8822C(x) ((x) & (~BITS_MACID_V1_8822C))
+#define BIT_GET_MACID_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_MACID_V1_8822C) & BIT_MASK_MACID_V1_8822C)
+#define BIT_SET_MACID_V1_8822C(x, v) \
+ (BIT_CLEAR_MACID_V1_8822C(x) | BIT_MACID_V1_8822C(v))
+
+/* 2 REG_MACID_H_8822C (MAC ID REGISTER) */
+
+#define BIT_SHIFT_MACID_H_V1_8822C 0
+#define BIT_MASK_MACID_H_V1_8822C 0xffff
+#define BIT_MACID_H_V1_8822C(x) \
+ (((x) & BIT_MASK_MACID_H_V1_8822C) << BIT_SHIFT_MACID_H_V1_8822C)
+#define BITS_MACID_H_V1_8822C \
+ (BIT_MASK_MACID_H_V1_8822C << BIT_SHIFT_MACID_H_V1_8822C)
+#define BIT_CLEAR_MACID_H_V1_8822C(x) ((x) & (~BITS_MACID_H_V1_8822C))
+#define BIT_GET_MACID_H_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_MACID_H_V1_8822C) & BIT_MASK_MACID_H_V1_8822C)
+#define BIT_SET_MACID_H_V1_8822C(x, v) \
+ (BIT_CLEAR_MACID_H_V1_8822C(x) | BIT_MACID_H_V1_8822C(v))
+
+/* 2 REG_BSSID_8822C (BSSID REGISTER) */
+
+#define BIT_SHIFT_BSSID_V1_8822C 0
+#define BIT_MASK_BSSID_V1_8822C 0xffffffffL
+#define BIT_BSSID_V1_8822C(x) \
+ (((x) & BIT_MASK_BSSID_V1_8822C) << BIT_SHIFT_BSSID_V1_8822C)
+#define BITS_BSSID_V1_8822C \
+ (BIT_MASK_BSSID_V1_8822C << BIT_SHIFT_BSSID_V1_8822C)
+#define BIT_CLEAR_BSSID_V1_8822C(x) ((x) & (~BITS_BSSID_V1_8822C))
+#define BIT_GET_BSSID_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_BSSID_V1_8822C) & BIT_MASK_BSSID_V1_8822C)
+#define BIT_SET_BSSID_V1_8822C(x, v) \
+ (BIT_CLEAR_BSSID_V1_8822C(x) | BIT_BSSID_V1_8822C(v))
+
+/* 2 REG_BSSID_H_8822C (BSSID REGISTER) */
+
+/* 2 REG_NOT_VALID_8822C */
+
+#define BIT_SHIFT_BSSID_H_V1_8822C 0
+#define BIT_MASK_BSSID_H_V1_8822C 0xffff
+#define BIT_BSSID_H_V1_8822C(x) \
+ (((x) & BIT_MASK_BSSID_H_V1_8822C) << BIT_SHIFT_BSSID_H_V1_8822C)
+#define BITS_BSSID_H_V1_8822C \
+ (BIT_MASK_BSSID_H_V1_8822C << BIT_SHIFT_BSSID_H_V1_8822C)
+#define BIT_CLEAR_BSSID_H_V1_8822C(x) ((x) & (~BITS_BSSID_H_V1_8822C))
+#define BIT_GET_BSSID_H_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_BSSID_H_V1_8822C) & BIT_MASK_BSSID_H_V1_8822C)
+#define BIT_SET_BSSID_H_V1_8822C(x, v) \
+ (BIT_CLEAR_BSSID_H_V1_8822C(x) | BIT_BSSID_H_V1_8822C(v))
+
+/* 2 REG_MAR_8822C (MULTICAST ADDRESS REGISTER) */
+
+#define BIT_SHIFT_MAR_V1_8822C 0
+#define BIT_MASK_MAR_V1_8822C 0xffffffffL
+#define BIT_MAR_V1_8822C(x) \
+ (((x) & BIT_MASK_MAR_V1_8822C) << BIT_SHIFT_MAR_V1_8822C)
+#define BITS_MAR_V1_8822C (BIT_MASK_MAR_V1_8822C << BIT_SHIFT_MAR_V1_8822C)
+#define BIT_CLEAR_MAR_V1_8822C(x) ((x) & (~BITS_MAR_V1_8822C))
+#define BIT_GET_MAR_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_MAR_V1_8822C) & BIT_MASK_MAR_V1_8822C)
+#define BIT_SET_MAR_V1_8822C(x, v) \
+ (BIT_CLEAR_MAR_V1_8822C(x) | BIT_MAR_V1_8822C(v))
+
+/* 2 REG_MAR_H_8822C (MULTICAST ADDRESS REGISTER) */
+
+#define BIT_SHIFT_MAR_H_V1_8822C 0
+#define BIT_MASK_MAR_H_V1_8822C 0xffffffffL
+#define BIT_MAR_H_V1_8822C(x) \
+ (((x) & BIT_MASK_MAR_H_V1_8822C) << BIT_SHIFT_MAR_H_V1_8822C)
+#define BITS_MAR_H_V1_8822C \
+ (BIT_MASK_MAR_H_V1_8822C << BIT_SHIFT_MAR_H_V1_8822C)
+#define BIT_CLEAR_MAR_H_V1_8822C(x) ((x) & (~BITS_MAR_H_V1_8822C))
+#define BIT_GET_MAR_H_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_MAR_H_V1_8822C) & BIT_MASK_MAR_H_V1_8822C)
+#define BIT_SET_MAR_H_V1_8822C(x, v) \
+ (BIT_CLEAR_MAR_H_V1_8822C(x) | BIT_MAR_H_V1_8822C(v))
+
+/* 2 REG_MBIDCAMCFG_1_8822C (MBSSID CAM CONFIGURATION REGISTER) */
+
+#define BIT_SHIFT_MBIDCAM_RWDATA_L_8822C 0
+#define BIT_MASK_MBIDCAM_RWDATA_L_8822C 0xffffffffL
+#define BIT_MBIDCAM_RWDATA_L_8822C(x) \
+ (((x) & BIT_MASK_MBIDCAM_RWDATA_L_8822C) \
+ << BIT_SHIFT_MBIDCAM_RWDATA_L_8822C)
+#define BITS_MBIDCAM_RWDATA_L_8822C \
+ (BIT_MASK_MBIDCAM_RWDATA_L_8822C << BIT_SHIFT_MBIDCAM_RWDATA_L_8822C)
+#define BIT_CLEAR_MBIDCAM_RWDATA_L_8822C(x) \
+ ((x) & (~BITS_MBIDCAM_RWDATA_L_8822C))
+#define BIT_GET_MBIDCAM_RWDATA_L_8822C(x) \
+ (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L_8822C) & \
+ BIT_MASK_MBIDCAM_RWDATA_L_8822C)
+#define BIT_SET_MBIDCAM_RWDATA_L_8822C(x, v) \
+ (BIT_CLEAR_MBIDCAM_RWDATA_L_8822C(x) | BIT_MBIDCAM_RWDATA_L_8822C(v))
+
+/* 2 REG_MBIDCAMCFG_2_8822C (MBSSID CAM CONFIGURATION REGISTER) */
+#define BIT_MBIDCAM_POLL_8822C BIT(31)
+#define BIT_MBIDCAM_WT_EN_8822C BIT(30)
+
+#define BIT_SHIFT_MBIDCAM_ADDR_V1_8822C 24
+#define BIT_MASK_MBIDCAM_ADDR_V1_8822C 0x3f
+#define BIT_MBIDCAM_ADDR_V1_8822C(x) \
+ (((x) & BIT_MASK_MBIDCAM_ADDR_V1_8822C) \
+ << BIT_SHIFT_MBIDCAM_ADDR_V1_8822C)
+#define BITS_MBIDCAM_ADDR_V1_8822C \
+ (BIT_MASK_MBIDCAM_ADDR_V1_8822C << BIT_SHIFT_MBIDCAM_ADDR_V1_8822C)
+#define BIT_CLEAR_MBIDCAM_ADDR_V1_8822C(x) ((x) & (~BITS_MBIDCAM_ADDR_V1_8822C))
+#define BIT_GET_MBIDCAM_ADDR_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_MBIDCAM_ADDR_V1_8822C) & \
+ BIT_MASK_MBIDCAM_ADDR_V1_8822C)
+#define BIT_SET_MBIDCAM_ADDR_V1_8822C(x, v) \
+ (BIT_CLEAR_MBIDCAM_ADDR_V1_8822C(x) | BIT_MBIDCAM_ADDR_V1_8822C(v))
+
+#define BIT_MBIDCAM_VALID_8822C BIT(23)
+#define BIT_LSIC_TXOP_EN_8822C BIT(17)
+#define BIT_CTS_EN_8822C BIT(16)
+
+#define BIT_SHIFT_MBIDCAM_RWDATA_H_8822C 0
+#define BIT_MASK_MBIDCAM_RWDATA_H_8822C 0xffff
+#define BIT_MBIDCAM_RWDATA_H_8822C(x) \
+ (((x) & BIT_MASK_MBIDCAM_RWDATA_H_8822C) \
+ << BIT_SHIFT_MBIDCAM_RWDATA_H_8822C)
+#define BITS_MBIDCAM_RWDATA_H_8822C \
+ (BIT_MASK_MBIDCAM_RWDATA_H_8822C << BIT_SHIFT_MBIDCAM_RWDATA_H_8822C)
+#define BIT_CLEAR_MBIDCAM_RWDATA_H_8822C(x) \
+ ((x) & (~BITS_MBIDCAM_RWDATA_H_8822C))
+#define BIT_GET_MBIDCAM_RWDATA_H_8822C(x) \
+ (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H_8822C) & \
+ BIT_MASK_MBIDCAM_RWDATA_H_8822C)
+#define BIT_SET_MBIDCAM_RWDATA_H_8822C(x, v) \
+ (BIT_CLEAR_MBIDCAM_RWDATA_H_8822C(x) | BIT_MBIDCAM_RWDATA_H_8822C(v))
+
+/* 2 REG_WMAC_TCR_TSFT_OFS_8822C */
+
+#define BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822C 0
+#define BIT_MASK_WMAC_TCR_TSFT_OFS_8822C 0xffff
+#define BIT_WMAC_TCR_TSFT_OFS_8822C(x) \
+ (((x) & BIT_MASK_WMAC_TCR_TSFT_OFS_8822C) \
+ << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822C)
+#define BITS_WMAC_TCR_TSFT_OFS_8822C \
+ (BIT_MASK_WMAC_TCR_TSFT_OFS_8822C << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822C)
+#define BIT_CLEAR_WMAC_TCR_TSFT_OFS_8822C(x) \
+ ((x) & (~BITS_WMAC_TCR_TSFT_OFS_8822C))
+#define BIT_GET_WMAC_TCR_TSFT_OFS_8822C(x) \
+ (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8822C) & \
+ BIT_MASK_WMAC_TCR_TSFT_OFS_8822C)
+#define BIT_SET_WMAC_TCR_TSFT_OFS_8822C(x, v) \
+ (BIT_CLEAR_WMAC_TCR_TSFT_OFS_8822C(x) | BIT_WMAC_TCR_TSFT_OFS_8822C(v))
+
+/* 2 REG_UDF_THSD_8822C */
+#define BIT_UDF_THSD_V1_8822C BIT(7)
+
+#define BIT_SHIFT_UDF_THSD_VALUE_8822C 0
+#define BIT_MASK_UDF_THSD_VALUE_8822C 0x7f
+#define BIT_UDF_THSD_VALUE_8822C(x) \
+ (((x) & BIT_MASK_UDF_THSD_VALUE_8822C) \
+ << BIT_SHIFT_UDF_THSD_VALUE_8822C)
+#define BITS_UDF_THSD_VALUE_8822C \
+ (BIT_MASK_UDF_THSD_VALUE_8822C << BIT_SHIFT_UDF_THSD_VALUE_8822C)
+#define BIT_CLEAR_UDF_THSD_VALUE_8822C(x) ((x) & (~BITS_UDF_THSD_VALUE_8822C))
+#define BIT_GET_UDF_THSD_VALUE_8822C(x) \
+ (((x) >> BIT_SHIFT_UDF_THSD_VALUE_8822C) & \
+ BIT_MASK_UDF_THSD_VALUE_8822C)
+#define BIT_SET_UDF_THSD_VALUE_8822C(x, v) \
+ (BIT_CLEAR_UDF_THSD_VALUE_8822C(x) | BIT_UDF_THSD_VALUE_8822C(v))
+
+/* 2 REG_ZLD_NUM_8822C */
+
+#define BIT_SHIFT_ZLD_NUM_8822C 0
+#define BIT_MASK_ZLD_NUM_8822C 0xff
+#define BIT_ZLD_NUM_8822C(x) \
+ (((x) & BIT_MASK_ZLD_NUM_8822C) << BIT_SHIFT_ZLD_NUM_8822C)
+#define BITS_ZLD_NUM_8822C (BIT_MASK_ZLD_NUM_8822C << BIT_SHIFT_ZLD_NUM_8822C)
+#define BIT_CLEAR_ZLD_NUM_8822C(x) ((x) & (~BITS_ZLD_NUM_8822C))
+#define BIT_GET_ZLD_NUM_8822C(x) \
+ (((x) >> BIT_SHIFT_ZLD_NUM_8822C) & BIT_MASK_ZLD_NUM_8822C)
+#define BIT_SET_ZLD_NUM_8822C(x, v) \
+ (BIT_CLEAR_ZLD_NUM_8822C(x) | BIT_ZLD_NUM_8822C(v))
+
+/* 2 REG_STMP_THSD_8822C */
+
+#define BIT_SHIFT_STMP_THSD_8822C 0
+#define BIT_MASK_STMP_THSD_8822C 0xff
+#define BIT_STMP_THSD_8822C(x) \
+ (((x) & BIT_MASK_STMP_THSD_8822C) << BIT_SHIFT_STMP_THSD_8822C)
+#define BITS_STMP_THSD_8822C \
+ (BIT_MASK_STMP_THSD_8822C << BIT_SHIFT_STMP_THSD_8822C)
+#define BIT_CLEAR_STMP_THSD_8822C(x) ((x) & (~BITS_STMP_THSD_8822C))
+#define BIT_GET_STMP_THSD_8822C(x) \
+ (((x) >> BIT_SHIFT_STMP_THSD_8822C) & BIT_MASK_STMP_THSD_8822C)
+#define BIT_SET_STMP_THSD_8822C(x, v) \
+ (BIT_CLEAR_STMP_THSD_8822C(x) | BIT_STMP_THSD_8822C(v))
+
+/* 2 REG_WMAC_TXTIMEOUT_8822C */
+
+#define BIT_SHIFT_WMAC_TXTIMEOUT_8822C 0
+#define BIT_MASK_WMAC_TXTIMEOUT_8822C 0xff
+#define BIT_WMAC_TXTIMEOUT_8822C(x) \
+ (((x) & BIT_MASK_WMAC_TXTIMEOUT_8822C) \
+ << BIT_SHIFT_WMAC_TXTIMEOUT_8822C)
+#define BITS_WMAC_TXTIMEOUT_8822C \
+ (BIT_MASK_WMAC_TXTIMEOUT_8822C << BIT_SHIFT_WMAC_TXTIMEOUT_8822C)
+#define BIT_CLEAR_WMAC_TXTIMEOUT_8822C(x) ((x) & (~BITS_WMAC_TXTIMEOUT_8822C))
+#define BIT_GET_WMAC_TXTIMEOUT_8822C(x) \
+ (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8822C) & \
+ BIT_MASK_WMAC_TXTIMEOUT_8822C)
+#define BIT_SET_WMAC_TXTIMEOUT_8822C(x, v) \
+ (BIT_CLEAR_WMAC_TXTIMEOUT_8822C(x) | BIT_WMAC_TXTIMEOUT_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_USTIME_EDCA_8822C (US TIME TUNING FOR EDCA REGISTER) */
+
+#define BIT_SHIFT_USTIME_EDCA_8822C 0
+#define BIT_MASK_USTIME_EDCA_8822C 0xff
+#define BIT_USTIME_EDCA_8822C(x) \
+ (((x) & BIT_MASK_USTIME_EDCA_8822C) << BIT_SHIFT_USTIME_EDCA_8822C)
+#define BITS_USTIME_EDCA_8822C \
+ (BIT_MASK_USTIME_EDCA_8822C << BIT_SHIFT_USTIME_EDCA_8822C)
+#define BIT_CLEAR_USTIME_EDCA_8822C(x) ((x) & (~BITS_USTIME_EDCA_8822C))
+#define BIT_GET_USTIME_EDCA_8822C(x) \
+ (((x) >> BIT_SHIFT_USTIME_EDCA_8822C) & BIT_MASK_USTIME_EDCA_8822C)
+#define BIT_SET_USTIME_EDCA_8822C(x, v) \
+ (BIT_CLEAR_USTIME_EDCA_8822C(x) | BIT_USTIME_EDCA_8822C(v))
+
+/* 2 REG_ACKTO_CCK_8822C (ACK TIMEOUT REGISTER FOR CCK RATE) */
+
+#define BIT_SHIFT_ACKTO_CCK_8822C 0
+#define BIT_MASK_ACKTO_CCK_8822C 0xff
+#define BIT_ACKTO_CCK_8822C(x) \
+ (((x) & BIT_MASK_ACKTO_CCK_8822C) << BIT_SHIFT_ACKTO_CCK_8822C)
+#define BITS_ACKTO_CCK_8822C \
+ (BIT_MASK_ACKTO_CCK_8822C << BIT_SHIFT_ACKTO_CCK_8822C)
+#define BIT_CLEAR_ACKTO_CCK_8822C(x) ((x) & (~BITS_ACKTO_CCK_8822C))
+#define BIT_GET_ACKTO_CCK_8822C(x) \
+ (((x) >> BIT_SHIFT_ACKTO_CCK_8822C) & BIT_MASK_ACKTO_CCK_8822C)
+#define BIT_SET_ACKTO_CCK_8822C(x, v) \
+ (BIT_CLEAR_ACKTO_CCK_8822C(x) | BIT_ACKTO_CCK_8822C(v))
+
+/* 2 REG_MAC_SPEC_SIFS_8822C (SPECIFICATION SIFS REGISTER) */
+
+#define BIT_SHIFT_SPEC_SIFS_OFDM_8822C 8
+#define BIT_MASK_SPEC_SIFS_OFDM_8822C 0xff
+#define BIT_SPEC_SIFS_OFDM_8822C(x) \
+ (((x) & BIT_MASK_SPEC_SIFS_OFDM_8822C) \
+ << BIT_SHIFT_SPEC_SIFS_OFDM_8822C)
+#define BITS_SPEC_SIFS_OFDM_8822C \
+ (BIT_MASK_SPEC_SIFS_OFDM_8822C << BIT_SHIFT_SPEC_SIFS_OFDM_8822C)
+#define BIT_CLEAR_SPEC_SIFS_OFDM_8822C(x) ((x) & (~BITS_SPEC_SIFS_OFDM_8822C))
+#define BIT_GET_SPEC_SIFS_OFDM_8822C(x) \
+ (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8822C) & \
+ BIT_MASK_SPEC_SIFS_OFDM_8822C)
+#define BIT_SET_SPEC_SIFS_OFDM_8822C(x, v) \
+ (BIT_CLEAR_SPEC_SIFS_OFDM_8822C(x) | BIT_SPEC_SIFS_OFDM_8822C(v))
+
+#define BIT_SHIFT_SPEC_SIFS_CCK_8822C 0
+#define BIT_MASK_SPEC_SIFS_CCK_8822C 0xff
+#define BIT_SPEC_SIFS_CCK_8822C(x) \
+ (((x) & BIT_MASK_SPEC_SIFS_CCK_8822C) << BIT_SHIFT_SPEC_SIFS_CCK_8822C)
+#define BITS_SPEC_SIFS_CCK_8822C \
+ (BIT_MASK_SPEC_SIFS_CCK_8822C << BIT_SHIFT_SPEC_SIFS_CCK_8822C)
+#define BIT_CLEAR_SPEC_SIFS_CCK_8822C(x) ((x) & (~BITS_SPEC_SIFS_CCK_8822C))
+#define BIT_GET_SPEC_SIFS_CCK_8822C(x) \
+ (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8822C) & BIT_MASK_SPEC_SIFS_CCK_8822C)
+#define BIT_SET_SPEC_SIFS_CCK_8822C(x, v) \
+ (BIT_CLEAR_SPEC_SIFS_CCK_8822C(x) | BIT_SPEC_SIFS_CCK_8822C(v))
+
+/* 2 REG_RESP_SIFS_CCK_8822C (RESPONSE SIFS FOR CCK REGISTER) */
+
+#define BIT_SHIFT_SIFS_R2T_CCK_8822C 8
+#define BIT_MASK_SIFS_R2T_CCK_8822C 0xff
+#define BIT_SIFS_R2T_CCK_8822C(x) \
+ (((x) & BIT_MASK_SIFS_R2T_CCK_8822C) << BIT_SHIFT_SIFS_R2T_CCK_8822C)
+#define BITS_SIFS_R2T_CCK_8822C \
+ (BIT_MASK_SIFS_R2T_CCK_8822C << BIT_SHIFT_SIFS_R2T_CCK_8822C)
+#define BIT_CLEAR_SIFS_R2T_CCK_8822C(x) ((x) & (~BITS_SIFS_R2T_CCK_8822C))
+#define BIT_GET_SIFS_R2T_CCK_8822C(x) \
+ (((x) >> BIT_SHIFT_SIFS_R2T_CCK_8822C) & BIT_MASK_SIFS_R2T_CCK_8822C)
+#define BIT_SET_SIFS_R2T_CCK_8822C(x, v) \
+ (BIT_CLEAR_SIFS_R2T_CCK_8822C(x) | BIT_SIFS_R2T_CCK_8822C(v))
+
+#define BIT_SHIFT_SIFS_T2T_CCK_8822C 0
+#define BIT_MASK_SIFS_T2T_CCK_8822C 0xff
+#define BIT_SIFS_T2T_CCK_8822C(x) \
+ (((x) & BIT_MASK_SIFS_T2T_CCK_8822C) << BIT_SHIFT_SIFS_T2T_CCK_8822C)
+#define BITS_SIFS_T2T_CCK_8822C \
+ (BIT_MASK_SIFS_T2T_CCK_8822C << BIT_SHIFT_SIFS_T2T_CCK_8822C)
+#define BIT_CLEAR_SIFS_T2T_CCK_8822C(x) ((x) & (~BITS_SIFS_T2T_CCK_8822C))
+#define BIT_GET_SIFS_T2T_CCK_8822C(x) \
+ (((x) >> BIT_SHIFT_SIFS_T2T_CCK_8822C) & BIT_MASK_SIFS_T2T_CCK_8822C)
+#define BIT_SET_SIFS_T2T_CCK_8822C(x, v) \
+ (BIT_CLEAR_SIFS_T2T_CCK_8822C(x) | BIT_SIFS_T2T_CCK_8822C(v))
+
+/* 2 REG_RESP_SIFS_OFDM_8822C (RESPONSE SIFS FOR OFDM REGISTER) */
+
+#define BIT_SHIFT_SIFS_R2T_OFDM_8822C 8
+#define BIT_MASK_SIFS_R2T_OFDM_8822C 0xff
+#define BIT_SIFS_R2T_OFDM_8822C(x) \
+ (((x) & BIT_MASK_SIFS_R2T_OFDM_8822C) << BIT_SHIFT_SIFS_R2T_OFDM_8822C)
+#define BITS_SIFS_R2T_OFDM_8822C \
+ (BIT_MASK_SIFS_R2T_OFDM_8822C << BIT_SHIFT_SIFS_R2T_OFDM_8822C)
+#define BIT_CLEAR_SIFS_R2T_OFDM_8822C(x) ((x) & (~BITS_SIFS_R2T_OFDM_8822C))
+#define BIT_GET_SIFS_R2T_OFDM_8822C(x) \
+ (((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8822C) & BIT_MASK_SIFS_R2T_OFDM_8822C)
+#define BIT_SET_SIFS_R2T_OFDM_8822C(x, v) \
+ (BIT_CLEAR_SIFS_R2T_OFDM_8822C(x) | BIT_SIFS_R2T_OFDM_8822C(v))
+
+#define BIT_SHIFT_SIFS_T2T_OFDM_8822C 0
+#define BIT_MASK_SIFS_T2T_OFDM_8822C 0xff
+#define BIT_SIFS_T2T_OFDM_8822C(x) \
+ (((x) & BIT_MASK_SIFS_T2T_OFDM_8822C) << BIT_SHIFT_SIFS_T2T_OFDM_8822C)
+#define BITS_SIFS_T2T_OFDM_8822C \
+ (BIT_MASK_SIFS_T2T_OFDM_8822C << BIT_SHIFT_SIFS_T2T_OFDM_8822C)
+#define BIT_CLEAR_SIFS_T2T_OFDM_8822C(x) ((x) & (~BITS_SIFS_T2T_OFDM_8822C))
+#define BIT_GET_SIFS_T2T_OFDM_8822C(x) \
+ (((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8822C) & BIT_MASK_SIFS_T2T_OFDM_8822C)
+#define BIT_SET_SIFS_T2T_OFDM_8822C(x, v) \
+ (BIT_CLEAR_SIFS_T2T_OFDM_8822C(x) | BIT_SIFS_T2T_OFDM_8822C(v))
+
+/* 2 REG_ACKTO_8822C (ACK TIMEOUT REGISTER) */
+
+#define BIT_SHIFT_ACKTO_8822C 0
+#define BIT_MASK_ACKTO_8822C 0xff
+#define BIT_ACKTO_8822C(x) \
+ (((x) & BIT_MASK_ACKTO_8822C) << BIT_SHIFT_ACKTO_8822C)
+#define BITS_ACKTO_8822C (BIT_MASK_ACKTO_8822C << BIT_SHIFT_ACKTO_8822C)
+#define BIT_CLEAR_ACKTO_8822C(x) ((x) & (~BITS_ACKTO_8822C))
+#define BIT_GET_ACKTO_8822C(x) \
+ (((x) >> BIT_SHIFT_ACKTO_8822C) & BIT_MASK_ACKTO_8822C)
+#define BIT_SET_ACKTO_8822C(x, v) \
+ (BIT_CLEAR_ACKTO_8822C(x) | BIT_ACKTO_8822C(v))
+
+/* 2 REG_CTS2TO_8822C (CTS2 TIMEOUT REGISTER) */
+
+#define BIT_SHIFT_CTS2TO_8822C 0
+#define BIT_MASK_CTS2TO_8822C 0xff
+#define BIT_CTS2TO_8822C(x) \
+ (((x) & BIT_MASK_CTS2TO_8822C) << BIT_SHIFT_CTS2TO_8822C)
+#define BITS_CTS2TO_8822C (BIT_MASK_CTS2TO_8822C << BIT_SHIFT_CTS2TO_8822C)
+#define BIT_CLEAR_CTS2TO_8822C(x) ((x) & (~BITS_CTS2TO_8822C))
+#define BIT_GET_CTS2TO_8822C(x) \
+ (((x) >> BIT_SHIFT_CTS2TO_8822C) & BIT_MASK_CTS2TO_8822C)
+#define BIT_SET_CTS2TO_8822C(x, v) \
+ (BIT_CLEAR_CTS2TO_8822C(x) | BIT_CTS2TO_8822C(v))
+
+/* 2 REG_EIFS_8822C (EIFS REGISTER) */
+
+#define BIT_SHIFT_EIFS_8822C 0
+#define BIT_MASK_EIFS_8822C 0xffff
+#define BIT_EIFS_8822C(x) (((x) & BIT_MASK_EIFS_8822C) << BIT_SHIFT_EIFS_8822C)
+#define BITS_EIFS_8822C (BIT_MASK_EIFS_8822C << BIT_SHIFT_EIFS_8822C)
+#define BIT_CLEAR_EIFS_8822C(x) ((x) & (~BITS_EIFS_8822C))
+#define BIT_GET_EIFS_8822C(x) \
+ (((x) >> BIT_SHIFT_EIFS_8822C) & BIT_MASK_EIFS_8822C)
+#define BIT_SET_EIFS_8822C(x, v) (BIT_CLEAR_EIFS_8822C(x) | BIT_EIFS_8822C(v))
+
+/* 2 REG_RPFM_MAP0_8822C */
+#define BIT_MGT_RPFM15EN_8822C BIT(15)
+#define BIT_MGT_RPFM14EN_8822C BIT(14)
+#define BIT_MGT_RPFM13EN_8822C BIT(13)
+#define BIT_MGT_RPFM12EN_8822C BIT(12)
+#define BIT_MGT_RPFM11EN_8822C BIT(11)
+#define BIT_MGT_RPFM10EN_8822C BIT(10)
+#define BIT_MGT_RPFM9EN_8822C BIT(9)
+#define BIT_MGT_RPFM8EN_8822C BIT(8)
+#define BIT_MGT_RPFM7EN_8822C BIT(7)
+#define BIT_MGT_RPFM6EN_8822C BIT(6)
+#define BIT_MGT_RPFM5EN_8822C BIT(5)
+#define BIT_MGT_RPFM4EN_8822C BIT(4)
+#define BIT_MGT_RPFM3EN_8822C BIT(3)
+#define BIT_MGT_RPFM2EN_8822C BIT(2)
+#define BIT_MGT_RPFM1EN_8822C BIT(1)
+#define BIT_MGT_RPFM0EN_8822C BIT(0)
+
+/* 2 REG_RPFM_MAP1_V1_8822C */
+#define BIT_DATA_RPFM15EN_8822C BIT(15)
+#define BIT_DATA_RPFM14EN_8822C BIT(14)
+#define BIT_DATA_RPFM13EN_8822C BIT(13)
+#define BIT_DATA_RPFM12EN_8822C BIT(12)
+#define BIT_DATA_RPFM11EN_8822C BIT(11)
+#define BIT_DATA_RPFM10EN_8822C BIT(10)
+#define BIT_DATA_RPFM9EN_8822C BIT(9)
+#define BIT_DATA_RPFM8EN_8822C BIT(8)
+#define BIT_DATA_RPFM7EN_8822C BIT(7)
+#define BIT_DATA_RPFM6EN_8822C BIT(6)
+#define BIT_DATA_RPFM5EN_8822C BIT(5)
+#define BIT_DATA_RPFM4EN_8822C BIT(4)
+#define BIT_DATA_RPFM3EN_8822C BIT(3)
+#define BIT_DATA_RPFM2EN_8822C BIT(2)
+#define BIT_DATA_RPFM1EN_8822C BIT(1)
+#define BIT_DATA_RPFM0EN_8822C BIT(0)
+
+/* 2 REG_RPFM_CAM_CMD_8822C (RX PAYLOAD FRAME MASK CAM COMMAND REGISTER) */
+#define BIT_RPFM_CAM_POLLING_8822C BIT(31)
+#define BIT_RPFM_CAM_CLR_8822C BIT(30)
+#define BIT_RPFM_CAM_WE_8822C BIT(16)
+
+#define BIT_SHIFT_RPFM_CAM_ADDR_8822C 0
+#define BIT_MASK_RPFM_CAM_ADDR_8822C 0x7f
+#define BIT_RPFM_CAM_ADDR_8822C(x) \
+ (((x) & BIT_MASK_RPFM_CAM_ADDR_8822C) << BIT_SHIFT_RPFM_CAM_ADDR_8822C)
+#define BITS_RPFM_CAM_ADDR_8822C \
+ (BIT_MASK_RPFM_CAM_ADDR_8822C << BIT_SHIFT_RPFM_CAM_ADDR_8822C)
+#define BIT_CLEAR_RPFM_CAM_ADDR_8822C(x) ((x) & (~BITS_RPFM_CAM_ADDR_8822C))
+#define BIT_GET_RPFM_CAM_ADDR_8822C(x) \
+ (((x) >> BIT_SHIFT_RPFM_CAM_ADDR_8822C) & BIT_MASK_RPFM_CAM_ADDR_8822C)
+#define BIT_SET_RPFM_CAM_ADDR_8822C(x, v) \
+ (BIT_CLEAR_RPFM_CAM_ADDR_8822C(x) | BIT_RPFM_CAM_ADDR_8822C(v))
+
+/* 2 REG_RPFM_CAM_RWD_8822C (ACK TIMEOUT REGISTER) */
+
+#define BIT_SHIFT_RPFM_CAM_RWD_8822C 0
+#define BIT_MASK_RPFM_CAM_RWD_8822C 0xffffffffL
+#define BIT_RPFM_CAM_RWD_8822C(x) \
+ (((x) & BIT_MASK_RPFM_CAM_RWD_8822C) << BIT_SHIFT_RPFM_CAM_RWD_8822C)
+#define BITS_RPFM_CAM_RWD_8822C \
+ (BIT_MASK_RPFM_CAM_RWD_8822C << BIT_SHIFT_RPFM_CAM_RWD_8822C)
+#define BIT_CLEAR_RPFM_CAM_RWD_8822C(x) ((x) & (~BITS_RPFM_CAM_RWD_8822C))
+#define BIT_GET_RPFM_CAM_RWD_8822C(x) \
+ (((x) >> BIT_SHIFT_RPFM_CAM_RWD_8822C) & BIT_MASK_RPFM_CAM_RWD_8822C)
+#define BIT_SET_RPFM_CAM_RWD_8822C(x, v) \
+ (BIT_CLEAR_RPFM_CAM_RWD_8822C(x) | BIT_RPFM_CAM_RWD_8822C(v))
+
+/* 2 REG_NAV_CTRL_8822C (NAV CONTROL REGISTER) */
+
+#define BIT_SHIFT_NAV_UPPER_8822C 16
+#define BIT_MASK_NAV_UPPER_8822C 0xff
+#define BIT_NAV_UPPER_8822C(x) \
+ (((x) & BIT_MASK_NAV_UPPER_8822C) << BIT_SHIFT_NAV_UPPER_8822C)
+#define BITS_NAV_UPPER_8822C \
+ (BIT_MASK_NAV_UPPER_8822C << BIT_SHIFT_NAV_UPPER_8822C)
+#define BIT_CLEAR_NAV_UPPER_8822C(x) ((x) & (~BITS_NAV_UPPER_8822C))
+#define BIT_GET_NAV_UPPER_8822C(x) \
+ (((x) >> BIT_SHIFT_NAV_UPPER_8822C) & BIT_MASK_NAV_UPPER_8822C)
+#define BIT_SET_NAV_UPPER_8822C(x, v) \
+ (BIT_CLEAR_NAV_UPPER_8822C(x) | BIT_NAV_UPPER_8822C(v))
+
+#define BIT_SHIFT_RXMYRTS_NAV_8822C 8
+#define BIT_MASK_RXMYRTS_NAV_8822C 0xf
+#define BIT_RXMYRTS_NAV_8822C(x) \
+ (((x) & BIT_MASK_RXMYRTS_NAV_8822C) << BIT_SHIFT_RXMYRTS_NAV_8822C)
+#define BITS_RXMYRTS_NAV_8822C \
+ (BIT_MASK_RXMYRTS_NAV_8822C << BIT_SHIFT_RXMYRTS_NAV_8822C)
+#define BIT_CLEAR_RXMYRTS_NAV_8822C(x) ((x) & (~BITS_RXMYRTS_NAV_8822C))
+#define BIT_GET_RXMYRTS_NAV_8822C(x) \
+ (((x) >> BIT_SHIFT_RXMYRTS_NAV_8822C) & BIT_MASK_RXMYRTS_NAV_8822C)
+#define BIT_SET_RXMYRTS_NAV_8822C(x, v) \
+ (BIT_CLEAR_RXMYRTS_NAV_8822C(x) | BIT_RXMYRTS_NAV_8822C(v))
+
+#define BIT_SHIFT_RTSRST_8822C 0
+#define BIT_MASK_RTSRST_8822C 0xff
+#define BIT_RTSRST_8822C(x) \
+ (((x) & BIT_MASK_RTSRST_8822C) << BIT_SHIFT_RTSRST_8822C)
+#define BITS_RTSRST_8822C (BIT_MASK_RTSRST_8822C << BIT_SHIFT_RTSRST_8822C)
+#define BIT_CLEAR_RTSRST_8822C(x) ((x) & (~BITS_RTSRST_8822C))
+#define BIT_GET_RTSRST_8822C(x) \
+ (((x) >> BIT_SHIFT_RTSRST_8822C) & BIT_MASK_RTSRST_8822C)
+#define BIT_SET_RTSRST_8822C(x, v) \
+ (BIT_CLEAR_RTSRST_8822C(x) | BIT_RTSRST_8822C(v))
+
+/* 2 REG_BACAMCMD_8822C (BLOCK ACK CAM COMMAND REGISTER) */
+#define BIT_BACAM_POLL_8822C BIT(31)
+#define BIT_BACAM_RST_8822C BIT(17)
+#define BIT_BACAM_RW_8822C BIT(16)
+
+#define BIT_SHIFT_TXSBM_8822C 14
+#define BIT_MASK_TXSBM_8822C 0x3
+#define BIT_TXSBM_8822C(x) \
+ (((x) & BIT_MASK_TXSBM_8822C) << BIT_SHIFT_TXSBM_8822C)
+#define BITS_TXSBM_8822C (BIT_MASK_TXSBM_8822C << BIT_SHIFT_TXSBM_8822C)
+#define BIT_CLEAR_TXSBM_8822C(x) ((x) & (~BITS_TXSBM_8822C))
+#define BIT_GET_TXSBM_8822C(x) \
+ (((x) >> BIT_SHIFT_TXSBM_8822C) & BIT_MASK_TXSBM_8822C)
+#define BIT_SET_TXSBM_8822C(x, v) \
+ (BIT_CLEAR_TXSBM_8822C(x) | BIT_TXSBM_8822C(v))
+
+#define BIT_SHIFT_BACAM_ADDR_8822C 0
+#define BIT_MASK_BACAM_ADDR_8822C 0x3f
+#define BIT_BACAM_ADDR_8822C(x) \
+ (((x) & BIT_MASK_BACAM_ADDR_8822C) << BIT_SHIFT_BACAM_ADDR_8822C)
+#define BITS_BACAM_ADDR_8822C \
+ (BIT_MASK_BACAM_ADDR_8822C << BIT_SHIFT_BACAM_ADDR_8822C)
+#define BIT_CLEAR_BACAM_ADDR_8822C(x) ((x) & (~BITS_BACAM_ADDR_8822C))
+#define BIT_GET_BACAM_ADDR_8822C(x) \
+ (((x) >> BIT_SHIFT_BACAM_ADDR_8822C) & BIT_MASK_BACAM_ADDR_8822C)
+#define BIT_SET_BACAM_ADDR_8822C(x, v) \
+ (BIT_CLEAR_BACAM_ADDR_8822C(x) | BIT_BACAM_ADDR_8822C(v))
+
+/* 2 REG_BACAMCONTENT_8822C (BLOCK ACK CAM CONTENT REGISTER) */
+
+#define BIT_SHIFT_BA_CONTENT_L_8822C 0
+#define BIT_MASK_BA_CONTENT_L_8822C 0xffffffffL
+#define BIT_BA_CONTENT_L_8822C(x) \
+ (((x) & BIT_MASK_BA_CONTENT_L_8822C) << BIT_SHIFT_BA_CONTENT_L_8822C)
+#define BITS_BA_CONTENT_L_8822C \
+ (BIT_MASK_BA_CONTENT_L_8822C << BIT_SHIFT_BA_CONTENT_L_8822C)
+#define BIT_CLEAR_BA_CONTENT_L_8822C(x) ((x) & (~BITS_BA_CONTENT_L_8822C))
+#define BIT_GET_BA_CONTENT_L_8822C(x) \
+ (((x) >> BIT_SHIFT_BA_CONTENT_L_8822C) & BIT_MASK_BA_CONTENT_L_8822C)
+#define BIT_SET_BA_CONTENT_L_8822C(x, v) \
+ (BIT_CLEAR_BA_CONTENT_L_8822C(x) | BIT_BA_CONTENT_L_8822C(v))
+
+/* 2 REG_BACAMCONTENT_H_8822C (BLOCK ACK CAM CONTENT REGISTER) */
+
+#define BIT_SHIFT_BA_CONTENT_H_8822C 0
+#define BIT_MASK_BA_CONTENT_H_8822C 0xffffffffL
+#define BIT_BA_CONTENT_H_8822C(x) \
+ (((x) & BIT_MASK_BA_CONTENT_H_8822C) << BIT_SHIFT_BA_CONTENT_H_8822C)
+#define BITS_BA_CONTENT_H_8822C \
+ (BIT_MASK_BA_CONTENT_H_8822C << BIT_SHIFT_BA_CONTENT_H_8822C)
+#define BIT_CLEAR_BA_CONTENT_H_8822C(x) ((x) & (~BITS_BA_CONTENT_H_8822C))
+#define BIT_GET_BA_CONTENT_H_8822C(x) \
+ (((x) >> BIT_SHIFT_BA_CONTENT_H_8822C) & BIT_MASK_BA_CONTENT_H_8822C)
+#define BIT_SET_BA_CONTENT_H_8822C(x, v) \
+ (BIT_CLEAR_BA_CONTENT_H_8822C(x) | BIT_BA_CONTENT_H_8822C(v))
+
+/* 2 REG_LBDLY_8822C (LOOPBACK DELAY REGISTER) */
+
+#define BIT_SHIFT_LBDLY_8822C 0
+#define BIT_MASK_LBDLY_8822C 0x1f
+#define BIT_LBDLY_8822C(x) \
+ (((x) & BIT_MASK_LBDLY_8822C) << BIT_SHIFT_LBDLY_8822C)
+#define BITS_LBDLY_8822C (BIT_MASK_LBDLY_8822C << BIT_SHIFT_LBDLY_8822C)
+#define BIT_CLEAR_LBDLY_8822C(x) ((x) & (~BITS_LBDLY_8822C))
+#define BIT_GET_LBDLY_8822C(x) \
+ (((x) >> BIT_SHIFT_LBDLY_8822C) & BIT_MASK_LBDLY_8822C)
+#define BIT_SET_LBDLY_8822C(x, v) \
+ (BIT_CLEAR_LBDLY_8822C(x) | BIT_LBDLY_8822C(v))
+
+/* 2 REG_WMAC_BACAM_RPMEN_8822C */
+
+#define BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822C 2
+#define BIT_MASK_BITMAP_SSNBK_COUNTER_8822C 0x3f
+#define BIT_BITMAP_SSNBK_COUNTER_8822C(x) \
+ (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8822C) \
+ << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822C)
+#define BITS_BITMAP_SSNBK_COUNTER_8822C \
+ (BIT_MASK_BITMAP_SSNBK_COUNTER_8822C \
+ << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822C)
+#define BIT_CLEAR_BITMAP_SSNBK_COUNTER_8822C(x) \
+ ((x) & (~BITS_BITMAP_SSNBK_COUNTER_8822C))
+#define BIT_GET_BITMAP_SSNBK_COUNTER_8822C(x) \
+ (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8822C) & \
+ BIT_MASK_BITMAP_SSNBK_COUNTER_8822C)
+#define BIT_SET_BITMAP_SSNBK_COUNTER_8822C(x, v) \
+ (BIT_CLEAR_BITMAP_SSNBK_COUNTER_8822C(x) | \
+ BIT_BITMAP_SSNBK_COUNTER_8822C(v))
+
+#define BIT_BITMAP_EN_8822C BIT(1)
+#define BIT_WMAC_BACAM_RPMEN_8822C BIT(0)
+
+/* 2 REG_TX_RX_8822C STATUS */
+
+#define BIT_SHIFT_RXPKT_TYPE_8822C 2
+#define BIT_MASK_RXPKT_TYPE_8822C 0x3f
+#define BIT_RXPKT_TYPE_8822C(x) \
+ (((x) & BIT_MASK_RXPKT_TYPE_8822C) << BIT_SHIFT_RXPKT_TYPE_8822C)
+#define BITS_RXPKT_TYPE_8822C \
+ (BIT_MASK_RXPKT_TYPE_8822C << BIT_SHIFT_RXPKT_TYPE_8822C)
+#define BIT_CLEAR_RXPKT_TYPE_8822C(x) ((x) & (~BITS_RXPKT_TYPE_8822C))
+#define BIT_GET_RXPKT_TYPE_8822C(x) \
+ (((x) >> BIT_SHIFT_RXPKT_TYPE_8822C) & BIT_MASK_RXPKT_TYPE_8822C)
+#define BIT_SET_RXPKT_TYPE_8822C(x, v) \
+ (BIT_CLEAR_RXPKT_TYPE_8822C(x) | BIT_RXPKT_TYPE_8822C(v))
+
+#define BIT_TXACT_IND_8822C BIT(1)
+#define BIT_RXACT_IND_8822C BIT(0)
+
+/* 2 REG_WMAC_BITMAP_CTL_8822C */
+#define BIT_BITMAP_VO_8822C BIT(7)
+#define BIT_BITMAP_VI_8822C BIT(6)
+#define BIT_BITMAP_BE_8822C BIT(5)
+#define BIT_BITMAP_BK_8822C BIT(4)
+
+#define BIT_SHIFT_BITMAP_CONDITION_8822C 2
+#define BIT_MASK_BITMAP_CONDITION_8822C 0x3
+#define BIT_BITMAP_CONDITION_8822C(x) \
+ (((x) & BIT_MASK_BITMAP_CONDITION_8822C) \
+ << BIT_SHIFT_BITMAP_CONDITION_8822C)
+#define BITS_BITMAP_CONDITION_8822C \
+ (BIT_MASK_BITMAP_CONDITION_8822C << BIT_SHIFT_BITMAP_CONDITION_8822C)
+#define BIT_CLEAR_BITMAP_CONDITION_8822C(x) \
+ ((x) & (~BITS_BITMAP_CONDITION_8822C))
+#define BIT_GET_BITMAP_CONDITION_8822C(x) \
+ (((x) >> BIT_SHIFT_BITMAP_CONDITION_8822C) & \
+ BIT_MASK_BITMAP_CONDITION_8822C)
+#define BIT_SET_BITMAP_CONDITION_8822C(x, v) \
+ (BIT_CLEAR_BITMAP_CONDITION_8822C(x) | BIT_BITMAP_CONDITION_8822C(v))
+
+#define BIT_BITMAP_SSNBK_COUNTER_CLR_8822C BIT(1)
+#define BIT_BITMAP_FORCE_8822C BIT(0)
+
+/* 2 REG_RXERR_RPT_8822C (RX ERROR REPORT REGISTER) */
+
+#define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822C 28
+#define BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822C 0xf
+#define BIT_RXERR_RPT_SEL_V1_3_0_8822C(x) \
+ (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822C) \
+ << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822C)
+#define BITS_RXERR_RPT_SEL_V1_3_0_8822C \
+ (BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822C \
+ << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822C)
+#define BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8822C(x) \
+ ((x) & (~BITS_RXERR_RPT_SEL_V1_3_0_8822C))
+#define BIT_GET_RXERR_RPT_SEL_V1_3_0_8822C(x) \
+ (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8822C) & \
+ BIT_MASK_RXERR_RPT_SEL_V1_3_0_8822C)
+#define BIT_SET_RXERR_RPT_SEL_V1_3_0_8822C(x, v) \
+ (BIT_CLEAR_RXERR_RPT_SEL_V1_3_0_8822C(x) | \
+ BIT_RXERR_RPT_SEL_V1_3_0_8822C(v))
+
+#define BIT_RXERR_RPT_RST_8822C BIT(27)
+#define BIT_RXERR_RPT_SEL_V1_4_8822C BIT(26)
+
+#define BIT_SHIFT_UD_SELECT_BSSID_2_1_8822C 24
+#define BIT_MASK_UD_SELECT_BSSID_2_1_8822C 0x3
+#define BIT_UD_SELECT_BSSID_2_1_8822C(x) \
+ (((x) & BIT_MASK_UD_SELECT_BSSID_2_1_8822C) \
+ << BIT_SHIFT_UD_SELECT_BSSID_2_1_8822C)
+#define BITS_UD_SELECT_BSSID_2_1_8822C \
+ (BIT_MASK_UD_SELECT_BSSID_2_1_8822C \
+ << BIT_SHIFT_UD_SELECT_BSSID_2_1_8822C)
+#define BIT_CLEAR_UD_SELECT_BSSID_2_1_8822C(x) \
+ ((x) & (~BITS_UD_SELECT_BSSID_2_1_8822C))
+#define BIT_GET_UD_SELECT_BSSID_2_1_8822C(x) \
+ (((x) >> BIT_SHIFT_UD_SELECT_BSSID_2_1_8822C) & \
+ BIT_MASK_UD_SELECT_BSSID_2_1_8822C)
+#define BIT_SET_UD_SELECT_BSSID_2_1_8822C(x, v) \
+ (BIT_CLEAR_UD_SELECT_BSSID_2_1_8822C(x) | \
+ BIT_UD_SELECT_BSSID_2_1_8822C(v))
+
+#define BIT_W1S_8822C BIT(23)
+#define BIT_UD_SELECT_BSSID_0_8822C BIT(22)
+
+#define BIT_SHIFT_UD_SUB_TYPE_8822C 18
+#define BIT_MASK_UD_SUB_TYPE_8822C 0xf
+#define BIT_UD_SUB_TYPE_8822C(x) \
+ (((x) & BIT_MASK_UD_SUB_TYPE_8822C) << BIT_SHIFT_UD_SUB_TYPE_8822C)
+#define BITS_UD_SUB_TYPE_8822C \
+ (BIT_MASK_UD_SUB_TYPE_8822C << BIT_SHIFT_UD_SUB_TYPE_8822C)
+#define BIT_CLEAR_UD_SUB_TYPE_8822C(x) ((x) & (~BITS_UD_SUB_TYPE_8822C))
+#define BIT_GET_UD_SUB_TYPE_8822C(x) \
+ (((x) >> BIT_SHIFT_UD_SUB_TYPE_8822C) & BIT_MASK_UD_SUB_TYPE_8822C)
+#define BIT_SET_UD_SUB_TYPE_8822C(x, v) \
+ (BIT_CLEAR_UD_SUB_TYPE_8822C(x) | BIT_UD_SUB_TYPE_8822C(v))
+
+#define BIT_SHIFT_UD_TYPE_8822C 16
+#define BIT_MASK_UD_TYPE_8822C 0x3
+#define BIT_UD_TYPE_8822C(x) \
+ (((x) & BIT_MASK_UD_TYPE_8822C) << BIT_SHIFT_UD_TYPE_8822C)
+#define BITS_UD_TYPE_8822C (BIT_MASK_UD_TYPE_8822C << BIT_SHIFT_UD_TYPE_8822C)
+#define BIT_CLEAR_UD_TYPE_8822C(x) ((x) & (~BITS_UD_TYPE_8822C))
+#define BIT_GET_UD_TYPE_8822C(x) \
+ (((x) >> BIT_SHIFT_UD_TYPE_8822C) & BIT_MASK_UD_TYPE_8822C)
+#define BIT_SET_UD_TYPE_8822C(x, v) \
+ (BIT_CLEAR_UD_TYPE_8822C(x) | BIT_UD_TYPE_8822C(v))
+
+#define BIT_SHIFT_RPT_COUNTER_8822C 0
+#define BIT_MASK_RPT_COUNTER_8822C 0xffff
+#define BIT_RPT_COUNTER_8822C(x) \
+ (((x) & BIT_MASK_RPT_COUNTER_8822C) << BIT_SHIFT_RPT_COUNTER_8822C)
+#define BITS_RPT_COUNTER_8822C \
+ (BIT_MASK_RPT_COUNTER_8822C << BIT_SHIFT_RPT_COUNTER_8822C)
+#define BIT_CLEAR_RPT_COUNTER_8822C(x) ((x) & (~BITS_RPT_COUNTER_8822C))
+#define BIT_GET_RPT_COUNTER_8822C(x) \
+ (((x) >> BIT_SHIFT_RPT_COUNTER_8822C) & BIT_MASK_RPT_COUNTER_8822C)
+#define BIT_SET_RPT_COUNTER_8822C(x, v) \
+ (BIT_CLEAR_RPT_COUNTER_8822C(x) | BIT_RPT_COUNTER_8822C(v))
+
+/* 2 REG_WMAC_TRXPTCL_CTL_8822C (WMAC TX/RX PROTOCOL CONTROL REGISTER) */
+#define BIT_ACKTO_BLOCK_SCH_EN_8822C BIT(27)
+#define BIT_EIFS_BLOCK_SCH_EN_8822C BIT(26)
+#define BIT_PLCPCHK_RST_EIFS_8822C BIT(25)
+#define BIT_CCA_RST_EIFS_8822C BIT(24)
+#define BIT_DIS_UPD_MYRXPKTNAV_8822C BIT(23)
+#define BIT_EARLY_TXBA_8822C BIT(22)
+
+#define BIT_SHIFT_RESP_CHNBUSY_8822C 20
+#define BIT_MASK_RESP_CHNBUSY_8822C 0x3
+#define BIT_RESP_CHNBUSY_8822C(x) \
+ (((x) & BIT_MASK_RESP_CHNBUSY_8822C) << BIT_SHIFT_RESP_CHNBUSY_8822C)
+#define BITS_RESP_CHNBUSY_8822C \
+ (BIT_MASK_RESP_CHNBUSY_8822C << BIT_SHIFT_RESP_CHNBUSY_8822C)
+#define BIT_CLEAR_RESP_CHNBUSY_8822C(x) ((x) & (~BITS_RESP_CHNBUSY_8822C))
+#define BIT_GET_RESP_CHNBUSY_8822C(x) \
+ (((x) >> BIT_SHIFT_RESP_CHNBUSY_8822C) & BIT_MASK_RESP_CHNBUSY_8822C)
+#define BIT_SET_RESP_CHNBUSY_8822C(x, v) \
+ (BIT_CLEAR_RESP_CHNBUSY_8822C(x) | BIT_RESP_CHNBUSY_8822C(v))
+
+#define BIT_RESP_DCTS_EN_8822C BIT(19)
+#define BIT_RESP_DCFE_EN_8822C BIT(18)
+#define BIT_RESP_SPLCPEN_8822C BIT(17)
+#define BIT_RESP_SGIEN_8822C BIT(16)
+#define BIT_RESP_LDPC_EN_8822C BIT(15)
+#define BIT_DIS_RESP_ACKINCCA_8822C BIT(14)
+#define BIT_DIS_RESP_CTSINCCA_8822C BIT(13)
+
+#define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822C 10
+#define BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822C 0x7
+#define BIT_R_WMAC_SECOND_CCA_TIMER_8822C(x) \
+ (((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822C) \
+ << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822C)
+#define BITS_R_WMAC_SECOND_CCA_TIMER_8822C \
+ (BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822C \
+ << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822C)
+#define BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8822C(x) \
+ ((x) & (~BITS_R_WMAC_SECOND_CCA_TIMER_8822C))
+#define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8822C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8822C) & \
+ BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8822C)
+#define BIT_SET_R_WMAC_SECOND_CCA_TIMER_8822C(x, v) \
+ (BIT_CLEAR_R_WMAC_SECOND_CCA_TIMER_8822C(x) | \
+ BIT_R_WMAC_SECOND_CCA_TIMER_8822C(v))
+
+#define BIT_SHIFT_RFMOD_8822C 7
+#define BIT_MASK_RFMOD_8822C 0x3
+#define BIT_RFMOD_8822C(x) \
+ (((x) & BIT_MASK_RFMOD_8822C) << BIT_SHIFT_RFMOD_8822C)
+#define BITS_RFMOD_8822C (BIT_MASK_RFMOD_8822C << BIT_SHIFT_RFMOD_8822C)
+#define BIT_CLEAR_RFMOD_8822C(x) ((x) & (~BITS_RFMOD_8822C))
+#define BIT_GET_RFMOD_8822C(x) \
+ (((x) >> BIT_SHIFT_RFMOD_8822C) & BIT_MASK_RFMOD_8822C)
+#define BIT_SET_RFMOD_8822C(x, v) \
+ (BIT_CLEAR_RFMOD_8822C(x) | BIT_RFMOD_8822C(v))
+
+#define BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822C 5
+#define BIT_MASK_RESP_CTS_DYNBW_SEL_8822C 0x3
+#define BIT_RESP_CTS_DYNBW_SEL_8822C(x) \
+ (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8822C) \
+ << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822C)
+#define BITS_RESP_CTS_DYNBW_SEL_8822C \
+ (BIT_MASK_RESP_CTS_DYNBW_SEL_8822C \
+ << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822C)
+#define BIT_CLEAR_RESP_CTS_DYNBW_SEL_8822C(x) \
+ ((x) & (~BITS_RESP_CTS_DYNBW_SEL_8822C))
+#define BIT_GET_RESP_CTS_DYNBW_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8822C) & \
+ BIT_MASK_RESP_CTS_DYNBW_SEL_8822C)
+#define BIT_SET_RESP_CTS_DYNBW_SEL_8822C(x, v) \
+ (BIT_CLEAR_RESP_CTS_DYNBW_SEL_8822C(x) | \
+ BIT_RESP_CTS_DYNBW_SEL_8822C(v))
+
+#define BIT_DLY_TX_WAIT_RXANTSEL_8822C BIT(4)
+#define BIT_TXRESP_BY_RXANTSEL_8822C BIT(3)
+
+#define BIT_SHIFT_ORIG_DCTS_CHK_8822C 0
+#define BIT_MASK_ORIG_DCTS_CHK_8822C 0x3
+#define BIT_ORIG_DCTS_CHK_8822C(x) \
+ (((x) & BIT_MASK_ORIG_DCTS_CHK_8822C) << BIT_SHIFT_ORIG_DCTS_CHK_8822C)
+#define BITS_ORIG_DCTS_CHK_8822C \
+ (BIT_MASK_ORIG_DCTS_CHK_8822C << BIT_SHIFT_ORIG_DCTS_CHK_8822C)
+#define BIT_CLEAR_ORIG_DCTS_CHK_8822C(x) ((x) & (~BITS_ORIG_DCTS_CHK_8822C))
+#define BIT_GET_ORIG_DCTS_CHK_8822C(x) \
+ (((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8822C) & BIT_MASK_ORIG_DCTS_CHK_8822C)
+#define BIT_SET_ORIG_DCTS_CHK_8822C(x, v) \
+ (BIT_CLEAR_ORIG_DCTS_CHK_8822C(x) | BIT_ORIG_DCTS_CHK_8822C(v))
+
+/* 2 REG_WMAC_TRXPTCL_CTL_H_8822C */
+
+#define BIT_SHIFT_ACKBA_TYPSEL_8822C 28
+#define BIT_MASK_ACKBA_TYPSEL_8822C 0xf
+#define BIT_ACKBA_TYPSEL_8822C(x) \
+ (((x) & BIT_MASK_ACKBA_TYPSEL_8822C) << BIT_SHIFT_ACKBA_TYPSEL_8822C)
+#define BITS_ACKBA_TYPSEL_8822C \
+ (BIT_MASK_ACKBA_TYPSEL_8822C << BIT_SHIFT_ACKBA_TYPSEL_8822C)
+#define BIT_CLEAR_ACKBA_TYPSEL_8822C(x) ((x) & (~BITS_ACKBA_TYPSEL_8822C))
+#define BIT_GET_ACKBA_TYPSEL_8822C(x) \
+ (((x) >> BIT_SHIFT_ACKBA_TYPSEL_8822C) & BIT_MASK_ACKBA_TYPSEL_8822C)
+#define BIT_SET_ACKBA_TYPSEL_8822C(x, v) \
+ (BIT_CLEAR_ACKBA_TYPSEL_8822C(x) | BIT_ACKBA_TYPSEL_8822C(v))
+
+#define BIT_SHIFT_ACKBA_ACKPCHK_8822C 24
+#define BIT_MASK_ACKBA_ACKPCHK_8822C 0xf
+#define BIT_ACKBA_ACKPCHK_8822C(x) \
+ (((x) & BIT_MASK_ACKBA_ACKPCHK_8822C) << BIT_SHIFT_ACKBA_ACKPCHK_8822C)
+#define BITS_ACKBA_ACKPCHK_8822C \
+ (BIT_MASK_ACKBA_ACKPCHK_8822C << BIT_SHIFT_ACKBA_ACKPCHK_8822C)
+#define BIT_CLEAR_ACKBA_ACKPCHK_8822C(x) ((x) & (~BITS_ACKBA_ACKPCHK_8822C))
+#define BIT_GET_ACKBA_ACKPCHK_8822C(x) \
+ (((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8822C) & BIT_MASK_ACKBA_ACKPCHK_8822C)
+#define BIT_SET_ACKBA_ACKPCHK_8822C(x, v) \
+ (BIT_CLEAR_ACKBA_ACKPCHK_8822C(x) | BIT_ACKBA_ACKPCHK_8822C(v))
+
+#define BIT_SHIFT_ACKBAR_TYPESEL_8822C 16
+#define BIT_MASK_ACKBAR_TYPESEL_8822C 0xff
+#define BIT_ACKBAR_TYPESEL_8822C(x) \
+ (((x) & BIT_MASK_ACKBAR_TYPESEL_8822C) \
+ << BIT_SHIFT_ACKBAR_TYPESEL_8822C)
+#define BITS_ACKBAR_TYPESEL_8822C \
+ (BIT_MASK_ACKBAR_TYPESEL_8822C << BIT_SHIFT_ACKBAR_TYPESEL_8822C)
+#define BIT_CLEAR_ACKBAR_TYPESEL_8822C(x) ((x) & (~BITS_ACKBAR_TYPESEL_8822C))
+#define BIT_GET_ACKBAR_TYPESEL_8822C(x) \
+ (((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8822C) & \
+ BIT_MASK_ACKBAR_TYPESEL_8822C)
+#define BIT_SET_ACKBAR_TYPESEL_8822C(x, v) \
+ (BIT_CLEAR_ACKBAR_TYPESEL_8822C(x) | BIT_ACKBAR_TYPESEL_8822C(v))
+
+#define BIT_SHIFT_ACKBAR_ACKPCHK_8822C 12
+#define BIT_MASK_ACKBAR_ACKPCHK_8822C 0xf
+#define BIT_ACKBAR_ACKPCHK_8822C(x) \
+ (((x) & BIT_MASK_ACKBAR_ACKPCHK_8822C) \
+ << BIT_SHIFT_ACKBAR_ACKPCHK_8822C)
+#define BITS_ACKBAR_ACKPCHK_8822C \
+ (BIT_MASK_ACKBAR_ACKPCHK_8822C << BIT_SHIFT_ACKBAR_ACKPCHK_8822C)
+#define BIT_CLEAR_ACKBAR_ACKPCHK_8822C(x) ((x) & (~BITS_ACKBAR_ACKPCHK_8822C))
+#define BIT_GET_ACKBAR_ACKPCHK_8822C(x) \
+ (((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8822C) & \
+ BIT_MASK_ACKBAR_ACKPCHK_8822C)
+#define BIT_SET_ACKBAR_ACKPCHK_8822C(x, v) \
+ (BIT_CLEAR_ACKBAR_ACKPCHK_8822C(x) | BIT_ACKBAR_ACKPCHK_8822C(v))
+
+#define BIT_RXBA_IGNOREA2_V1_8822C BIT(10)
+#define BIT_EN_SAVE_ALL_TXOPADDR_V1_8822C BIT(9)
+#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV_V1_8822C BIT(8)
+#define BIT_DIS_TXBA_AMPDUFCSERR_V1_8822C BIT(7)
+#define BIT_DIS_TXBA_RXBARINFULL_V1_8822C BIT(6)
+#define BIT_DIS_TXCFE_INFULL_V1_8822C BIT(5)
+#define BIT_DIS_TXCTS_INFULL_V1_8822C BIT(4)
+#define BIT_EN_TXACKBA_IN_TX_RDG_V1_8822C BIT(3)
+#define BIT_EN_TXACKBA_IN_TXOP_V1_8822C BIT(2)
+#define BIT_EN_TXCTS_IN_RXNAV_V1_8822C BIT(1)
+#define BIT_EN_TXCTS_INTXOP_V1_8822C BIT(0)
+
+/* 2 REG_CAMCMD_8822C (CAM COMMAND REGISTER) */
+#define BIT_SECCAM_POLLING_8822C BIT(31)
+#define BIT_SECCAM_CLR_8822C BIT(30)
+#define BIT_SECCAM_WE_8822C BIT(16)
+
+#define BIT_SHIFT_SECCAM_ADDR_V2_8822C 0
+#define BIT_MASK_SECCAM_ADDR_V2_8822C 0x3ff
+#define BIT_SECCAM_ADDR_V2_8822C(x) \
+ (((x) & BIT_MASK_SECCAM_ADDR_V2_8822C) \
+ << BIT_SHIFT_SECCAM_ADDR_V2_8822C)
+#define BITS_SECCAM_ADDR_V2_8822C \
+ (BIT_MASK_SECCAM_ADDR_V2_8822C << BIT_SHIFT_SECCAM_ADDR_V2_8822C)
+#define BIT_CLEAR_SECCAM_ADDR_V2_8822C(x) ((x) & (~BITS_SECCAM_ADDR_V2_8822C))
+#define BIT_GET_SECCAM_ADDR_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8822C) & \
+ BIT_MASK_SECCAM_ADDR_V2_8822C)
+#define BIT_SET_SECCAM_ADDR_V2_8822C(x, v) \
+ (BIT_CLEAR_SECCAM_ADDR_V2_8822C(x) | BIT_SECCAM_ADDR_V2_8822C(v))
+
+/* 2 REG_CAMWRITE_8822C (CAM WRITE REGISTER) */
+
+#define BIT_SHIFT_CAMW_DATA_8822C 0
+#define BIT_MASK_CAMW_DATA_8822C 0xffffffffL
+#define BIT_CAMW_DATA_8822C(x) \
+ (((x) & BIT_MASK_CAMW_DATA_8822C) << BIT_SHIFT_CAMW_DATA_8822C)
+#define BITS_CAMW_DATA_8822C \
+ (BIT_MASK_CAMW_DATA_8822C << BIT_SHIFT_CAMW_DATA_8822C)
+#define BIT_CLEAR_CAMW_DATA_8822C(x) ((x) & (~BITS_CAMW_DATA_8822C))
+#define BIT_GET_CAMW_DATA_8822C(x) \
+ (((x) >> BIT_SHIFT_CAMW_DATA_8822C) & BIT_MASK_CAMW_DATA_8822C)
+#define BIT_SET_CAMW_DATA_8822C(x, v) \
+ (BIT_CLEAR_CAMW_DATA_8822C(x) | BIT_CAMW_DATA_8822C(v))
+
+/* 2 REG_CAMREAD_8822C (CAM READ REGISTER) */
+
+#define BIT_SHIFT_CAMR_DATA_8822C 0
+#define BIT_MASK_CAMR_DATA_8822C 0xffffffffL
+#define BIT_CAMR_DATA_8822C(x) \
+ (((x) & BIT_MASK_CAMR_DATA_8822C) << BIT_SHIFT_CAMR_DATA_8822C)
+#define BITS_CAMR_DATA_8822C \
+ (BIT_MASK_CAMR_DATA_8822C << BIT_SHIFT_CAMR_DATA_8822C)
+#define BIT_CLEAR_CAMR_DATA_8822C(x) ((x) & (~BITS_CAMR_DATA_8822C))
+#define BIT_GET_CAMR_DATA_8822C(x) \
+ (((x) >> BIT_SHIFT_CAMR_DATA_8822C) & BIT_MASK_CAMR_DATA_8822C)
+#define BIT_SET_CAMR_DATA_8822C(x, v) \
+ (BIT_CLEAR_CAMR_DATA_8822C(x) | BIT_CAMR_DATA_8822C(v))
+
+/* 2 REG_CAMDBG_8822C (CAM DEBUG REGISTER) */
+#define BIT_SECCAM_INFO_8822C BIT(31)
+#define BIT_SEC_KEYFOUND_8822C BIT(15)
+
+#define BIT_SHIFT_CAMDBG_SEC_TYPE_8822C 12
+#define BIT_MASK_CAMDBG_SEC_TYPE_8822C 0x7
+#define BIT_CAMDBG_SEC_TYPE_8822C(x) \
+ (((x) & BIT_MASK_CAMDBG_SEC_TYPE_8822C) \
+ << BIT_SHIFT_CAMDBG_SEC_TYPE_8822C)
+#define BITS_CAMDBG_SEC_TYPE_8822C \
+ (BIT_MASK_CAMDBG_SEC_TYPE_8822C << BIT_SHIFT_CAMDBG_SEC_TYPE_8822C)
+#define BIT_CLEAR_CAMDBG_SEC_TYPE_8822C(x) ((x) & (~BITS_CAMDBG_SEC_TYPE_8822C))
+#define BIT_GET_CAMDBG_SEC_TYPE_8822C(x) \
+ (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8822C) & \
+ BIT_MASK_CAMDBG_SEC_TYPE_8822C)
+#define BIT_SET_CAMDBG_SEC_TYPE_8822C(x, v) \
+ (BIT_CLEAR_CAMDBG_SEC_TYPE_8822C(x) | BIT_CAMDBG_SEC_TYPE_8822C(v))
+
+#define BIT_CAMDBG_EXT_SECTYPE_8822C BIT(11)
+
+#define BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822C 5
+#define BIT_MASK_CAMDBG_MIC_KEY_IDX_8822C 0x1f
+#define BIT_CAMDBG_MIC_KEY_IDX_8822C(x) \
+ (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8822C) \
+ << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822C)
+#define BITS_CAMDBG_MIC_KEY_IDX_8822C \
+ (BIT_MASK_CAMDBG_MIC_KEY_IDX_8822C \
+ << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822C)
+#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8822C(x) \
+ ((x) & (~BITS_CAMDBG_MIC_KEY_IDX_8822C))
+#define BIT_GET_CAMDBG_MIC_KEY_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8822C) & \
+ BIT_MASK_CAMDBG_MIC_KEY_IDX_8822C)
+#define BIT_SET_CAMDBG_MIC_KEY_IDX_8822C(x, v) \
+ (BIT_CLEAR_CAMDBG_MIC_KEY_IDX_8822C(x) | \
+ BIT_CAMDBG_MIC_KEY_IDX_8822C(v))
+
+#define BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822C 0
+#define BIT_MASK_CAMDBG_SEC_KEY_IDX_8822C 0x1f
+#define BIT_CAMDBG_SEC_KEY_IDX_8822C(x) \
+ (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8822C) \
+ << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822C)
+#define BITS_CAMDBG_SEC_KEY_IDX_8822C \
+ (BIT_MASK_CAMDBG_SEC_KEY_IDX_8822C \
+ << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822C)
+#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8822C(x) \
+ ((x) & (~BITS_CAMDBG_SEC_KEY_IDX_8822C))
+#define BIT_GET_CAMDBG_SEC_KEY_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8822C) & \
+ BIT_MASK_CAMDBG_SEC_KEY_IDX_8822C)
+#define BIT_SET_CAMDBG_SEC_KEY_IDX_8822C(x, v) \
+ (BIT_CLEAR_CAMDBG_SEC_KEY_IDX_8822C(x) | \
+ BIT_CAMDBG_SEC_KEY_IDX_8822C(v))
+
+/* 2 REG_SECCFG_8822C (SECURITY CONFIGURATION REGISTER) */
+#define BIT_DIS_GCLK_WAPI_8822C BIT(15)
+#define BIT_DIS_GCLK_AES_8822C BIT(14)
+#define BIT_DIS_GCLK_TKIP_8822C BIT(13)
+#define BIT_AES_SEL_QC_1_8822C BIT(12)
+#define BIT_AES_SEL_QC_0_8822C BIT(11)
+#define BIT_CHK_BMC_8822C BIT(9)
+#define BIT_CHK_KEYID_8822C BIT(8)
+#define BIT_RXBCUSEDK_8822C BIT(7)
+#define BIT_TXBCUSEDK_8822C BIT(6)
+#define BIT_NOSKMC_8822C BIT(5)
+#define BIT_SKBYA2_8822C BIT(4)
+#define BIT_RXDEC_8822C BIT(3)
+#define BIT_TXENC_8822C BIT(2)
+#define BIT_RXUHUSEDK_8822C BIT(1)
+#define BIT_TXUHUSEDK_8822C BIT(0)
+
+/* 2 REG_RXFILTER_CATEGORY_1_8822C */
+
+#define BIT_SHIFT_RXFILTER_CATEGORY_1_8822C 0
+#define BIT_MASK_RXFILTER_CATEGORY_1_8822C 0xff
+#define BIT_RXFILTER_CATEGORY_1_8822C(x) \
+ (((x) & BIT_MASK_RXFILTER_CATEGORY_1_8822C) \
+ << BIT_SHIFT_RXFILTER_CATEGORY_1_8822C)
+#define BITS_RXFILTER_CATEGORY_1_8822C \
+ (BIT_MASK_RXFILTER_CATEGORY_1_8822C \
+ << BIT_SHIFT_RXFILTER_CATEGORY_1_8822C)
+#define BIT_CLEAR_RXFILTER_CATEGORY_1_8822C(x) \
+ ((x) & (~BITS_RXFILTER_CATEGORY_1_8822C))
+#define BIT_GET_RXFILTER_CATEGORY_1_8822C(x) \
+ (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8822C) & \
+ BIT_MASK_RXFILTER_CATEGORY_1_8822C)
+#define BIT_SET_RXFILTER_CATEGORY_1_8822C(x, v) \
+ (BIT_CLEAR_RXFILTER_CATEGORY_1_8822C(x) | \
+ BIT_RXFILTER_CATEGORY_1_8822C(v))
+
+/* 2 REG_RXFILTER_ACTION_1_8822C */
+
+#define BIT_SHIFT_RXFILTER_ACTION_1_8822C 0
+#define BIT_MASK_RXFILTER_ACTION_1_8822C 0xff
+#define BIT_RXFILTER_ACTION_1_8822C(x) \
+ (((x) & BIT_MASK_RXFILTER_ACTION_1_8822C) \
+ << BIT_SHIFT_RXFILTER_ACTION_1_8822C)
+#define BITS_RXFILTER_ACTION_1_8822C \
+ (BIT_MASK_RXFILTER_ACTION_1_8822C << BIT_SHIFT_RXFILTER_ACTION_1_8822C)
+#define BIT_CLEAR_RXFILTER_ACTION_1_8822C(x) \
+ ((x) & (~BITS_RXFILTER_ACTION_1_8822C))
+#define BIT_GET_RXFILTER_ACTION_1_8822C(x) \
+ (((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8822C) & \
+ BIT_MASK_RXFILTER_ACTION_1_8822C)
+#define BIT_SET_RXFILTER_ACTION_1_8822C(x, v) \
+ (BIT_CLEAR_RXFILTER_ACTION_1_8822C(x) | BIT_RXFILTER_ACTION_1_8822C(v))
+
+/* 2 REG_RXFILTER_CATEGORY_2_8822C */
+
+#define BIT_SHIFT_RXFILTER_CATEGORY_2_8822C 0
+#define BIT_MASK_RXFILTER_CATEGORY_2_8822C 0xff
+#define BIT_RXFILTER_CATEGORY_2_8822C(x) \
+ (((x) & BIT_MASK_RXFILTER_CATEGORY_2_8822C) \
+ << BIT_SHIFT_RXFILTER_CATEGORY_2_8822C)
+#define BITS_RXFILTER_CATEGORY_2_8822C \
+ (BIT_MASK_RXFILTER_CATEGORY_2_8822C \
+ << BIT_SHIFT_RXFILTER_CATEGORY_2_8822C)
+#define BIT_CLEAR_RXFILTER_CATEGORY_2_8822C(x) \
+ ((x) & (~BITS_RXFILTER_CATEGORY_2_8822C))
+#define BIT_GET_RXFILTER_CATEGORY_2_8822C(x) \
+ (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8822C) & \
+ BIT_MASK_RXFILTER_CATEGORY_2_8822C)
+#define BIT_SET_RXFILTER_CATEGORY_2_8822C(x, v) \
+ (BIT_CLEAR_RXFILTER_CATEGORY_2_8822C(x) | \
+ BIT_RXFILTER_CATEGORY_2_8822C(v))
+
+/* 2 REG_RXFILTER_ACTION_2_8822C */
+
+#define BIT_SHIFT_RXFILTER_ACTION_2_8822C 0
+#define BIT_MASK_RXFILTER_ACTION_2_8822C 0xff
+#define BIT_RXFILTER_ACTION_2_8822C(x) \
+ (((x) & BIT_MASK_RXFILTER_ACTION_2_8822C) \
+ << BIT_SHIFT_RXFILTER_ACTION_2_8822C)
+#define BITS_RXFILTER_ACTION_2_8822C \
+ (BIT_MASK_RXFILTER_ACTION_2_8822C << BIT_SHIFT_RXFILTER_ACTION_2_8822C)
+#define BIT_CLEAR_RXFILTER_ACTION_2_8822C(x) \
+ ((x) & (~BITS_RXFILTER_ACTION_2_8822C))
+#define BIT_GET_RXFILTER_ACTION_2_8822C(x) \
+ (((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8822C) & \
+ BIT_MASK_RXFILTER_ACTION_2_8822C)
+#define BIT_SET_RXFILTER_ACTION_2_8822C(x, v) \
+ (BIT_CLEAR_RXFILTER_ACTION_2_8822C(x) | BIT_RXFILTER_ACTION_2_8822C(v))
+
+/* 2 REG_RXFILTER_CATEGORY_3_8822C */
+
+#define BIT_SHIFT_RXFILTER_CATEGORY_3_8822C 0
+#define BIT_MASK_RXFILTER_CATEGORY_3_8822C 0xff
+#define BIT_RXFILTER_CATEGORY_3_8822C(x) \
+ (((x) & BIT_MASK_RXFILTER_CATEGORY_3_8822C) \
+ << BIT_SHIFT_RXFILTER_CATEGORY_3_8822C)
+#define BITS_RXFILTER_CATEGORY_3_8822C \
+ (BIT_MASK_RXFILTER_CATEGORY_3_8822C \
+ << BIT_SHIFT_RXFILTER_CATEGORY_3_8822C)
+#define BIT_CLEAR_RXFILTER_CATEGORY_3_8822C(x) \
+ ((x) & (~BITS_RXFILTER_CATEGORY_3_8822C))
+#define BIT_GET_RXFILTER_CATEGORY_3_8822C(x) \
+ (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8822C) & \
+ BIT_MASK_RXFILTER_CATEGORY_3_8822C)
+#define BIT_SET_RXFILTER_CATEGORY_3_8822C(x, v) \
+ (BIT_CLEAR_RXFILTER_CATEGORY_3_8822C(x) | \
+ BIT_RXFILTER_CATEGORY_3_8822C(v))
+
+/* 2 REG_RXFILTER_ACTION_3_8822C */
+
+#define BIT_SHIFT_RXFILTER_ACTION_3_8822C 0
+#define BIT_MASK_RXFILTER_ACTION_3_8822C 0xff
+#define BIT_RXFILTER_ACTION_3_8822C(x) \
+ (((x) & BIT_MASK_RXFILTER_ACTION_3_8822C) \
+ << BIT_SHIFT_RXFILTER_ACTION_3_8822C)
+#define BITS_RXFILTER_ACTION_3_8822C \
+ (BIT_MASK_RXFILTER_ACTION_3_8822C << BIT_SHIFT_RXFILTER_ACTION_3_8822C)
+#define BIT_CLEAR_RXFILTER_ACTION_3_8822C(x) \
+ ((x) & (~BITS_RXFILTER_ACTION_3_8822C))
+#define BIT_GET_RXFILTER_ACTION_3_8822C(x) \
+ (((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8822C) & \
+ BIT_MASK_RXFILTER_ACTION_3_8822C)
+#define BIT_SET_RXFILTER_ACTION_3_8822C(x, v) \
+ (BIT_CLEAR_RXFILTER_ACTION_3_8822C(x) | BIT_RXFILTER_ACTION_3_8822C(v))
+
+/* 2 REG_RXFLTMAP3_8822C (RX FILTER MAP GROUP 3) */
+#define BIT_MGTFLT15EN_FW_8822C BIT(15)
+#define BIT_MGTFLT14EN_FW_8822C BIT(14)
+#define BIT_MGTFLT13EN_FW_8822C BIT(13)
+#define BIT_MGTFLT12EN_FW_8822C BIT(12)
+#define BIT_MGTFLT11EN_FW_8822C BIT(11)
+#define BIT_MGTFLT10EN_FW_8822C BIT(10)
+#define BIT_MGTFLT9EN_FW_8822C BIT(9)
+#define BIT_MGTFLT8EN_FW_8822C BIT(8)
+#define BIT_MGTFLT7EN_FW_8822C BIT(7)
+#define BIT_MGTFLT6EN_FW_8822C BIT(6)
+#define BIT_MGTFLT5EN_FW_8822C BIT(5)
+#define BIT_MGTFLT4EN_FW_8822C BIT(4)
+#define BIT_MGTFLT3EN_FW_8822C BIT(3)
+#define BIT_MGTFLT2EN_FW_8822C BIT(2)
+#define BIT_MGTFLT1EN_FW_8822C BIT(1)
+#define BIT_MGTFLT0EN_FW_8822C BIT(0)
+
+/* 2 REG_RXFLTMAP4_8822C (RX FILTER MAP GROUP 4) */
+#define BIT_CTRLFLT15EN_FW_8822C BIT(15)
+#define BIT_CTRLFLT14EN_FW_8822C BIT(14)
+#define BIT_CTRLFLT13EN_FW_8822C BIT(13)
+#define BIT_CTRLFLT12EN_FW_8822C BIT(12)
+#define BIT_CTRLFLT11EN_FW_8822C BIT(11)
+#define BIT_CTRLFLT10EN_FW_8822C BIT(10)
+#define BIT_CTRLFLT9EN_FW_8822C BIT(9)
+#define BIT_CTRLFLT8EN_FW_8822C BIT(8)
+#define BIT_CTRLFLT7EN_FW_8822C BIT(7)
+#define BIT_CTRLFLT6EN_FW_8822C BIT(6)
+#define BIT_CTRLFLT5EN_FW_8822C BIT(5)
+#define BIT_CTRLFLT4EN_FW_8822C BIT(4)
+#define BIT_CTRLFLT3EN_FW_8822C BIT(3)
+#define BIT_CTRLFLT2EN_FW_8822C BIT(2)
+#define BIT_CTRLFLT1EN_FW_8822C BIT(1)
+#define BIT_CTRLFLT0EN_FW_8822C BIT(0)
+
+/* 2 REG_RXFLTMAP5_8822C (RX FILTER MAP GROUP 5) */
+#define BIT_DATAFLT15EN_FW_8822C BIT(15)
+#define BIT_DATAFLT14EN_FW_8822C BIT(14)
+#define BIT_DATAFLT13EN_FW_8822C BIT(13)
+#define BIT_DATAFLT12EN_FW_8822C BIT(12)
+#define BIT_DATAFLT11EN_FW_8822C BIT(11)
+#define BIT_DATAFLT10EN_FW_8822C BIT(10)
+#define BIT_DATAFLT9EN_FW_8822C BIT(9)
+#define BIT_DATAFLT8EN_FW_8822C BIT(8)
+#define BIT_DATAFLT7EN_FW_8822C BIT(7)
+#define BIT_DATAFLT6EN_FW_8822C BIT(6)
+#define BIT_DATAFLT5EN_FW_8822C BIT(5)
+#define BIT_DATAFLT4EN_FW_8822C BIT(4)
+#define BIT_DATAFLT3EN_FW_8822C BIT(3)
+#define BIT_DATAFLT2EN_FW_8822C BIT(2)
+#define BIT_DATAFLT1EN_FW_8822C BIT(1)
+#define BIT_DATAFLT0EN_FW_8822C BIT(0)
+
+/* 2 REG_RXFLTMAP6_8822C (RX FILTER MAP GROUP 6) */
+#define BIT_ACTIONFLT15EN_FW_8822C BIT(15)
+#define BIT_ACTIONFLT14EN_FW_8822C BIT(14)
+#define BIT_ACTIONFLT13EN_FW_8822C BIT(13)
+#define BIT_ACTIONFLT12EN_FW_8822C BIT(12)
+#define BIT_ACTIONFLT11EN_FW_8822C BIT(11)
+#define BIT_ACTIONFLT10EN_FW_8822C BIT(10)
+#define BIT_ACTIONFLT9EN_FW_8822C BIT(9)
+#define BIT_ACTIONFLT8EN_FW_8822C BIT(8)
+#define BIT_ACTIONFLT7EN_FW_8822C BIT(7)
+#define BIT_ACTIONFLT6EN_FW_8822C BIT(6)
+#define BIT_ACTIONFLT5EN_FW_8822C BIT(5)
+#define BIT_ACTIONFLT4EN_FW_8822C BIT(4)
+#define BIT_ACTIONFLT3EN_FW_8822C BIT(3)
+#define BIT_ACTIONFLT2EN_FW_8822C BIT(2)
+#define BIT_ACTIONFLT1EN_FW_8822C BIT(1)
+#define BIT_ACTIONFLT0EN_FW_8822C BIT(0)
+
+/* 2 REG_WOW_CTRL_8822C (WAKE ON WLAN CONTROL REGISTER) */
+
+#define BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822C 6
+#define BIT_MASK_PSF_BSSIDSEL_B2B1_8822C 0x3
+#define BIT_PSF_BSSIDSEL_B2B1_8822C(x) \
+ (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8822C) \
+ << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822C)
+#define BITS_PSF_BSSIDSEL_B2B1_8822C \
+ (BIT_MASK_PSF_BSSIDSEL_B2B1_8822C << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822C)
+#define BIT_CLEAR_PSF_BSSIDSEL_B2B1_8822C(x) \
+ ((x) & (~BITS_PSF_BSSIDSEL_B2B1_8822C))
+#define BIT_GET_PSF_BSSIDSEL_B2B1_8822C(x) \
+ (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8822C) & \
+ BIT_MASK_PSF_BSSIDSEL_B2B1_8822C)
+#define BIT_SET_PSF_BSSIDSEL_B2B1_8822C(x, v) \
+ (BIT_CLEAR_PSF_BSSIDSEL_B2B1_8822C(x) | BIT_PSF_BSSIDSEL_B2B1_8822C(v))
+
+#define BIT_WOWHCI_8822C BIT(5)
+#define BIT_PSF_BSSIDSEL_B0_8822C BIT(4)
+#define BIT_UWF_8822C BIT(3)
+#define BIT_MAGIC_8822C BIT(2)
+#define BIT_WOWEN_8822C BIT(1)
+#define BIT_FORCE_WAKEUP_8822C BIT(0)
+
+/* 2 REG_NAN_RX_TSF_FILTER_8822C(NAN_RX_TSF_ADDRESS_FILTER) */
+#define BIT_CHK_TSF_TA_8822C BIT(2)
+#define BIT_CHK_TSF_CBSSID_8822C BIT(1)
+#define BIT_CHK_TSF_EN_8822C BIT(0)
+
+/* 2 REG_PS_RX_INFO_8822C (POWER SAVE RX INFORMATION REGISTER) */
+
+#define BIT_SHIFT_PORTSEL__PS_RX_INFO_8822C 5
+#define BIT_MASK_PORTSEL__PS_RX_INFO_8822C 0x7
+#define BIT_PORTSEL__PS_RX_INFO_8822C(x) \
+ (((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8822C) \
+ << BIT_SHIFT_PORTSEL__PS_RX_INFO_8822C)
+#define BITS_PORTSEL__PS_RX_INFO_8822C \
+ (BIT_MASK_PORTSEL__PS_RX_INFO_8822C \
+ << BIT_SHIFT_PORTSEL__PS_RX_INFO_8822C)
+#define BIT_CLEAR_PORTSEL__PS_RX_INFO_8822C(x) \
+ ((x) & (~BITS_PORTSEL__PS_RX_INFO_8822C))
+#define BIT_GET_PORTSEL__PS_RX_INFO_8822C(x) \
+ (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8822C) & \
+ BIT_MASK_PORTSEL__PS_RX_INFO_8822C)
+#define BIT_SET_PORTSEL__PS_RX_INFO_8822C(x, v) \
+ (BIT_CLEAR_PORTSEL__PS_RX_INFO_8822C(x) | \
+ BIT_PORTSEL__PS_RX_INFO_8822C(v))
+
+#define BIT_RXCTRLIN0_8822C BIT(4)
+#define BIT_RXMGTIN0_8822C BIT(3)
+#define BIT_RXDATAIN2_8822C BIT(2)
+#define BIT_RXDATAIN1_8822C BIT(1)
+#define BIT_RXDATAIN0_8822C BIT(0)
+
+/* 2 REG_WMMPS_UAPSD_TID_8822C (WMM POWER SAVE UAPSD TID REGISTER) */
+#define BIT_WMMPS_UAPSD_TID7_8822C BIT(7)
+#define BIT_WMMPS_UAPSD_TID6_8822C BIT(6)
+#define BIT_WMMPS_UAPSD_TID5_8822C BIT(5)
+#define BIT_WMMPS_UAPSD_TID4_8822C BIT(4)
+#define BIT_WMMPS_UAPSD_TID3_8822C BIT(3)
+#define BIT_WMMPS_UAPSD_TID2_8822C BIT(2)
+#define BIT_WMMPS_UAPSD_TID1_8822C BIT(1)
+#define BIT_WMMPS_UAPSD_TID0_8822C BIT(0)
+
+/* 2 REG_LPNAV_CTRL_8822C (LOW POWER NAV CONTROL REGISTER) */
+
+/* 2 REG_WKFMCAM_CMD_8822C (WAKEUP FRAME CAM COMMAND REGISTER) */
+#define BIT_WKFCAM_POLLING_V1_8822C BIT(31)
+#define BIT_WKFCAM_CLR_V1_8822C BIT(30)
+#define BIT_WKFCAM_WE_8822C BIT(16)
+
+#define BIT_SHIFT_WKFCAM_ADDR_V2_8822C 8
+#define BIT_MASK_WKFCAM_ADDR_V2_8822C 0xff
+#define BIT_WKFCAM_ADDR_V2_8822C(x) \
+ (((x) & BIT_MASK_WKFCAM_ADDR_V2_8822C) \
+ << BIT_SHIFT_WKFCAM_ADDR_V2_8822C)
+#define BITS_WKFCAM_ADDR_V2_8822C \
+ (BIT_MASK_WKFCAM_ADDR_V2_8822C << BIT_SHIFT_WKFCAM_ADDR_V2_8822C)
+#define BIT_CLEAR_WKFCAM_ADDR_V2_8822C(x) ((x) & (~BITS_WKFCAM_ADDR_V2_8822C))
+#define BIT_GET_WKFCAM_ADDR_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2_8822C) & \
+ BIT_MASK_WKFCAM_ADDR_V2_8822C)
+#define BIT_SET_WKFCAM_ADDR_V2_8822C(x, v) \
+ (BIT_CLEAR_WKFCAM_ADDR_V2_8822C(x) | BIT_WKFCAM_ADDR_V2_8822C(v))
+
+#define BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822C 0
+#define BIT_MASK_WKFCAM_CAM_NUM_V1_8822C 0xff
+#define BIT_WKFCAM_CAM_NUM_V1_8822C(x) \
+ (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1_8822C) \
+ << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822C)
+#define BITS_WKFCAM_CAM_NUM_V1_8822C \
+ (BIT_MASK_WKFCAM_CAM_NUM_V1_8822C << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822C)
+#define BIT_CLEAR_WKFCAM_CAM_NUM_V1_8822C(x) \
+ ((x) & (~BITS_WKFCAM_CAM_NUM_V1_8822C))
+#define BIT_GET_WKFCAM_CAM_NUM_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8822C) & \
+ BIT_MASK_WKFCAM_CAM_NUM_V1_8822C)
+#define BIT_SET_WKFCAM_CAM_NUM_V1_8822C(x, v) \
+ (BIT_CLEAR_WKFCAM_CAM_NUM_V1_8822C(x) | BIT_WKFCAM_CAM_NUM_V1_8822C(v))
+
+/* 2 REG_WKFMCAM_RWD_8822C (WAKEUP FRAME READ/WRITE DATA) */
+
+#define BIT_SHIFT_WKFMCAM_RWD_8822C 0
+#define BIT_MASK_WKFMCAM_RWD_8822C 0xffffffffL
+#define BIT_WKFMCAM_RWD_8822C(x) \
+ (((x) & BIT_MASK_WKFMCAM_RWD_8822C) << BIT_SHIFT_WKFMCAM_RWD_8822C)
+#define BITS_WKFMCAM_RWD_8822C \
+ (BIT_MASK_WKFMCAM_RWD_8822C << BIT_SHIFT_WKFMCAM_RWD_8822C)
+#define BIT_CLEAR_WKFMCAM_RWD_8822C(x) ((x) & (~BITS_WKFMCAM_RWD_8822C))
+#define BIT_GET_WKFMCAM_RWD_8822C(x) \
+ (((x) >> BIT_SHIFT_WKFMCAM_RWD_8822C) & BIT_MASK_WKFMCAM_RWD_8822C)
+#define BIT_SET_WKFMCAM_RWD_8822C(x, v) \
+ (BIT_CLEAR_WKFMCAM_RWD_8822C(x) | BIT_WKFMCAM_RWD_8822C(v))
+
+/* 2 REG_RXFLTMAP0_8822C (RX FILTER MAP GROUP 0) */
+#define BIT_MGTFLT15EN_8822C BIT(15)
+#define BIT_MGTFLT14EN_8822C BIT(14)
+#define BIT_MGTFLT13EN_8822C BIT(13)
+#define BIT_MGTFLT12EN_8822C BIT(12)
+#define BIT_MGTFLT11EN_8822C BIT(11)
+#define BIT_MGTFLT10EN_8822C BIT(10)
+#define BIT_MGTFLT9EN_8822C BIT(9)
+#define BIT_MGTFLT8EN_8822C BIT(8)
+#define BIT_MGTFLT7EN_8822C BIT(7)
+#define BIT_MGTFLT6EN_8822C BIT(6)
+#define BIT_MGTFLT5EN_8822C BIT(5)
+#define BIT_MGTFLT4EN_8822C BIT(4)
+#define BIT_MGTFLT3EN_8822C BIT(3)
+#define BIT_MGTFLT2EN_8822C BIT(2)
+#define BIT_MGTFLT1EN_8822C BIT(1)
+#define BIT_MGTFLT0EN_8822C BIT(0)
+
+/* 2 REG_RXFLTMAP1_8822C (RX FILTER MAP GROUP 1) */
+#define BIT_CTRLFLT15EN_8822C BIT(15)
+#define BIT_CTRLFLT14EN_8822C BIT(14)
+#define BIT_CTRLFLT13EN_8822C BIT(13)
+#define BIT_CTRLFLT12EN_8822C BIT(12)
+#define BIT_CTRLFLT11EN_8822C BIT(11)
+#define BIT_CTRLFLT10EN_8822C BIT(10)
+#define BIT_CTRLFLT9EN_8822C BIT(9)
+#define BIT_CTRLFLT8EN_8822C BIT(8)
+#define BIT_CTRLFLT7EN_8822C BIT(7)
+#define BIT_CTRLFLT6EN_8822C BIT(6)
+#define BIT_CTRLFLT5EN_8822C BIT(5)
+#define BIT_CTRLFLT4EN_8822C BIT(4)
+#define BIT_CTRLFLT3EN_8822C BIT(3)
+#define BIT_CTRLFLT2EN_8822C BIT(2)
+#define BIT_CTRLFLT1EN_8822C BIT(1)
+#define BIT_CTRLFLT0EN_8822C BIT(0)
+
+/* 2 REG_RXFLTMAP2_8822C (RX FILTER MAP GROUP 2) */
+#define BIT_DATAFLT15EN_8822C BIT(15)
+#define BIT_DATAFLT14EN_8822C BIT(14)
+#define BIT_DATAFLT13EN_8822C BIT(13)
+#define BIT_DATAFLT12EN_8822C BIT(12)
+#define BIT_DATAFLT11EN_8822C BIT(11)
+#define BIT_DATAFLT10EN_8822C BIT(10)
+#define BIT_DATAFLT9EN_8822C BIT(9)
+#define BIT_DATAFLT8EN_8822C BIT(8)
+#define BIT_DATAFLT7EN_8822C BIT(7)
+#define BIT_DATAFLT6EN_8822C BIT(6)
+#define BIT_DATAFLT5EN_8822C BIT(5)
+#define BIT_DATAFLT4EN_8822C BIT(4)
+#define BIT_DATAFLT3EN_8822C BIT(3)
+#define BIT_DATAFLT2EN_8822C BIT(2)
+#define BIT_DATAFLT1EN_8822C BIT(1)
+#define BIT_DATAFLT0EN_8822C BIT(0)
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_BCN_PSR_RPT_8822C (BEACON PARSER REPORT REGISTER) */
+
+#define BIT_SHIFT_DTIM_CNT_8822C 24
+#define BIT_MASK_DTIM_CNT_8822C 0xff
+#define BIT_DTIM_CNT_8822C(x) \
+ (((x) & BIT_MASK_DTIM_CNT_8822C) << BIT_SHIFT_DTIM_CNT_8822C)
+#define BITS_DTIM_CNT_8822C \
+ (BIT_MASK_DTIM_CNT_8822C << BIT_SHIFT_DTIM_CNT_8822C)
+#define BIT_CLEAR_DTIM_CNT_8822C(x) ((x) & (~BITS_DTIM_CNT_8822C))
+#define BIT_GET_DTIM_CNT_8822C(x) \
+ (((x) >> BIT_SHIFT_DTIM_CNT_8822C) & BIT_MASK_DTIM_CNT_8822C)
+#define BIT_SET_DTIM_CNT_8822C(x, v) \
+ (BIT_CLEAR_DTIM_CNT_8822C(x) | BIT_DTIM_CNT_8822C(v))
+
+#define BIT_SHIFT_DTIM_PERIOD_8822C 16
+#define BIT_MASK_DTIM_PERIOD_8822C 0xff
+#define BIT_DTIM_PERIOD_8822C(x) \
+ (((x) & BIT_MASK_DTIM_PERIOD_8822C) << BIT_SHIFT_DTIM_PERIOD_8822C)
+#define BITS_DTIM_PERIOD_8822C \
+ (BIT_MASK_DTIM_PERIOD_8822C << BIT_SHIFT_DTIM_PERIOD_8822C)
+#define BIT_CLEAR_DTIM_PERIOD_8822C(x) ((x) & (~BITS_DTIM_PERIOD_8822C))
+#define BIT_GET_DTIM_PERIOD_8822C(x) \
+ (((x) >> BIT_SHIFT_DTIM_PERIOD_8822C) & BIT_MASK_DTIM_PERIOD_8822C)
+#define BIT_SET_DTIM_PERIOD_8822C(x, v) \
+ (BIT_CLEAR_DTIM_PERIOD_8822C(x) | BIT_DTIM_PERIOD_8822C(v))
+
+#define BIT_DTIM_8822C BIT(15)
+#define BIT_TIM_8822C BIT(14)
+#define BIT_RPT_VALID_8822C BIT(13)
+
+#define BIT_SHIFT_PS_AID_0_8822C 0
+#define BIT_MASK_PS_AID_0_8822C 0x7ff
+#define BIT_PS_AID_0_8822C(x) \
+ (((x) & BIT_MASK_PS_AID_0_8822C) << BIT_SHIFT_PS_AID_0_8822C)
+#define BITS_PS_AID_0_8822C \
+ (BIT_MASK_PS_AID_0_8822C << BIT_SHIFT_PS_AID_0_8822C)
+#define BIT_CLEAR_PS_AID_0_8822C(x) ((x) & (~BITS_PS_AID_0_8822C))
+#define BIT_GET_PS_AID_0_8822C(x) \
+ (((x) >> BIT_SHIFT_PS_AID_0_8822C) & BIT_MASK_PS_AID_0_8822C)
+#define BIT_SET_PS_AID_0_8822C(x, v) \
+ (BIT_CLEAR_PS_AID_0_8822C(x) | BIT_PS_AID_0_8822C(v))
+
+/* 2 REG_FLC_RPC_8822C (FW LPS CONDITION -- RX PKT COUNTER) */
+
+#define BIT_SHIFT_FLC_RPC_8822C 0
+#define BIT_MASK_FLC_RPC_8822C 0xff
+#define BIT_FLC_RPC_8822C(x) \
+ (((x) & BIT_MASK_FLC_RPC_8822C) << BIT_SHIFT_FLC_RPC_8822C)
+#define BITS_FLC_RPC_8822C (BIT_MASK_FLC_RPC_8822C << BIT_SHIFT_FLC_RPC_8822C)
+#define BIT_CLEAR_FLC_RPC_8822C(x) ((x) & (~BITS_FLC_RPC_8822C))
+#define BIT_GET_FLC_RPC_8822C(x) \
+ (((x) >> BIT_SHIFT_FLC_RPC_8822C) & BIT_MASK_FLC_RPC_8822C)
+#define BIT_SET_FLC_RPC_8822C(x, v) \
+ (BIT_CLEAR_FLC_RPC_8822C(x) | BIT_FLC_RPC_8822C(v))
+
+/* 2 REG_FLC_RPCT_8822C (FLC_RPC THRESHOLD) */
+
+#define BIT_SHIFT_FLC_RPCT_8822C 0
+#define BIT_MASK_FLC_RPCT_8822C 0xff
+#define BIT_FLC_RPCT_8822C(x) \
+ (((x) & BIT_MASK_FLC_RPCT_8822C) << BIT_SHIFT_FLC_RPCT_8822C)
+#define BITS_FLC_RPCT_8822C \
+ (BIT_MASK_FLC_RPCT_8822C << BIT_SHIFT_FLC_RPCT_8822C)
+#define BIT_CLEAR_FLC_RPCT_8822C(x) ((x) & (~BITS_FLC_RPCT_8822C))
+#define BIT_GET_FLC_RPCT_8822C(x) \
+ (((x) >> BIT_SHIFT_FLC_RPCT_8822C) & BIT_MASK_FLC_RPCT_8822C)
+#define BIT_SET_FLC_RPCT_8822C(x, v) \
+ (BIT_CLEAR_FLC_RPCT_8822C(x) | BIT_FLC_RPCT_8822C(v))
+
+/* 2 REG_FLC_PTS_8822C (PKT TYPE SELECTION OF FLC_RPC T) */
+#define BIT_CMF_8822C BIT(2)
+#define BIT_CCF_8822C BIT(1)
+#define BIT_CDF_8822C BIT(0)
+
+/* 2 REG_FLC_TRPC_8822C (TIMER OF FLC_RPC) */
+#define BIT_FLC_RPCT_V1_8822C BIT(7)
+#define BIT_MODE_8822C BIT(6)
+
+#define BIT_SHIFT_TRPCD_8822C 0
+#define BIT_MASK_TRPCD_8822C 0x3f
+#define BIT_TRPCD_8822C(x) \
+ (((x) & BIT_MASK_TRPCD_8822C) << BIT_SHIFT_TRPCD_8822C)
+#define BITS_TRPCD_8822C (BIT_MASK_TRPCD_8822C << BIT_SHIFT_TRPCD_8822C)
+#define BIT_CLEAR_TRPCD_8822C(x) ((x) & (~BITS_TRPCD_8822C))
+#define BIT_GET_TRPCD_8822C(x) \
+ (((x) >> BIT_SHIFT_TRPCD_8822C) & BIT_MASK_TRPCD_8822C)
+#define BIT_SET_TRPCD_8822C(x, v) \
+ (BIT_CLEAR_TRPCD_8822C(x) | BIT_TRPCD_8822C(v))
+
+/* 2 REG_RXPKTMON_CTRL_8822C */
+
+#define BIT_SHIFT_RXBKQPKT_SEQ_8822C 20
+#define BIT_MASK_RXBKQPKT_SEQ_8822C 0xf
+#define BIT_RXBKQPKT_SEQ_8822C(x) \
+ (((x) & BIT_MASK_RXBKQPKT_SEQ_8822C) << BIT_SHIFT_RXBKQPKT_SEQ_8822C)
+#define BITS_RXBKQPKT_SEQ_8822C \
+ (BIT_MASK_RXBKQPKT_SEQ_8822C << BIT_SHIFT_RXBKQPKT_SEQ_8822C)
+#define BIT_CLEAR_RXBKQPKT_SEQ_8822C(x) ((x) & (~BITS_RXBKQPKT_SEQ_8822C))
+#define BIT_GET_RXBKQPKT_SEQ_8822C(x) \
+ (((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8822C) & BIT_MASK_RXBKQPKT_SEQ_8822C)
+#define BIT_SET_RXBKQPKT_SEQ_8822C(x, v) \
+ (BIT_CLEAR_RXBKQPKT_SEQ_8822C(x) | BIT_RXBKQPKT_SEQ_8822C(v))
+
+#define BIT_SHIFT_RXBEQPKT_SEQ_8822C 16
+#define BIT_MASK_RXBEQPKT_SEQ_8822C 0xf
+#define BIT_RXBEQPKT_SEQ_8822C(x) \
+ (((x) & BIT_MASK_RXBEQPKT_SEQ_8822C) << BIT_SHIFT_RXBEQPKT_SEQ_8822C)
+#define BITS_RXBEQPKT_SEQ_8822C \
+ (BIT_MASK_RXBEQPKT_SEQ_8822C << BIT_SHIFT_RXBEQPKT_SEQ_8822C)
+#define BIT_CLEAR_RXBEQPKT_SEQ_8822C(x) ((x) & (~BITS_RXBEQPKT_SEQ_8822C))
+#define BIT_GET_RXBEQPKT_SEQ_8822C(x) \
+ (((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8822C) & BIT_MASK_RXBEQPKT_SEQ_8822C)
+#define BIT_SET_RXBEQPKT_SEQ_8822C(x, v) \
+ (BIT_CLEAR_RXBEQPKT_SEQ_8822C(x) | BIT_RXBEQPKT_SEQ_8822C(v))
+
+#define BIT_SHIFT_RXVIQPKT_SEQ_8822C 12
+#define BIT_MASK_RXVIQPKT_SEQ_8822C 0xf
+#define BIT_RXVIQPKT_SEQ_8822C(x) \
+ (((x) & BIT_MASK_RXVIQPKT_SEQ_8822C) << BIT_SHIFT_RXVIQPKT_SEQ_8822C)
+#define BITS_RXVIQPKT_SEQ_8822C \
+ (BIT_MASK_RXVIQPKT_SEQ_8822C << BIT_SHIFT_RXVIQPKT_SEQ_8822C)
+#define BIT_CLEAR_RXVIQPKT_SEQ_8822C(x) ((x) & (~BITS_RXVIQPKT_SEQ_8822C))
+#define BIT_GET_RXVIQPKT_SEQ_8822C(x) \
+ (((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8822C) & BIT_MASK_RXVIQPKT_SEQ_8822C)
+#define BIT_SET_RXVIQPKT_SEQ_8822C(x, v) \
+ (BIT_CLEAR_RXVIQPKT_SEQ_8822C(x) | BIT_RXVIQPKT_SEQ_8822C(v))
+
+#define BIT_SHIFT_RXVOQPKT_SEQ_8822C 8
+#define BIT_MASK_RXVOQPKT_SEQ_8822C 0xf
+#define BIT_RXVOQPKT_SEQ_8822C(x) \
+ (((x) & BIT_MASK_RXVOQPKT_SEQ_8822C) << BIT_SHIFT_RXVOQPKT_SEQ_8822C)
+#define BITS_RXVOQPKT_SEQ_8822C \
+ (BIT_MASK_RXVOQPKT_SEQ_8822C << BIT_SHIFT_RXVOQPKT_SEQ_8822C)
+#define BIT_CLEAR_RXVOQPKT_SEQ_8822C(x) ((x) & (~BITS_RXVOQPKT_SEQ_8822C))
+#define BIT_GET_RXVOQPKT_SEQ_8822C(x) \
+ (((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8822C) & BIT_MASK_RXVOQPKT_SEQ_8822C)
+#define BIT_SET_RXVOQPKT_SEQ_8822C(x, v) \
+ (BIT_CLEAR_RXVOQPKT_SEQ_8822C(x) | BIT_RXVOQPKT_SEQ_8822C(v))
+
+#define BIT_RXBKQPKT_ERR_8822C BIT(7)
+#define BIT_RXBEQPKT_ERR_8822C BIT(6)
+#define BIT_RXVIQPKT_ERR_8822C BIT(5)
+#define BIT_RXVOQPKT_ERR_8822C BIT(4)
+#define BIT_RXDMA_MON_EN_8822C BIT(2)
+#define BIT_RXPKT_MON_RST_8822C BIT(1)
+#define BIT_RXPKT_MON_EN_8822C BIT(0)
+
+/* 2 REG_STATE_MON_8822C */
+
+#define BIT_SHIFT_STATE_SEL_8822C 24
+#define BIT_MASK_STATE_SEL_8822C 0x1f
+#define BIT_STATE_SEL_8822C(x) \
+ (((x) & BIT_MASK_STATE_SEL_8822C) << BIT_SHIFT_STATE_SEL_8822C)
+#define BITS_STATE_SEL_8822C \
+ (BIT_MASK_STATE_SEL_8822C << BIT_SHIFT_STATE_SEL_8822C)
+#define BIT_CLEAR_STATE_SEL_8822C(x) ((x) & (~BITS_STATE_SEL_8822C))
+#define BIT_GET_STATE_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_STATE_SEL_8822C) & BIT_MASK_STATE_SEL_8822C)
+#define BIT_SET_STATE_SEL_8822C(x, v) \
+ (BIT_CLEAR_STATE_SEL_8822C(x) | BIT_STATE_SEL_8822C(v))
+
+#define BIT_SHIFT_STATE_INFO_8822C 8
+#define BIT_MASK_STATE_INFO_8822C 0xff
+#define BIT_STATE_INFO_8822C(x) \
+ (((x) & BIT_MASK_STATE_INFO_8822C) << BIT_SHIFT_STATE_INFO_8822C)
+#define BITS_STATE_INFO_8822C \
+ (BIT_MASK_STATE_INFO_8822C << BIT_SHIFT_STATE_INFO_8822C)
+#define BIT_CLEAR_STATE_INFO_8822C(x) ((x) & (~BITS_STATE_INFO_8822C))
+#define BIT_GET_STATE_INFO_8822C(x) \
+ (((x) >> BIT_SHIFT_STATE_INFO_8822C) & BIT_MASK_STATE_INFO_8822C)
+#define BIT_SET_STATE_INFO_8822C(x, v) \
+ (BIT_CLEAR_STATE_INFO_8822C(x) | BIT_STATE_INFO_8822C(v))
+
+#define BIT_UPD_NXT_STATE_8822C BIT(7)
+
+#define BIT_SHIFT_CUR_STATE_8822C 0
+#define BIT_MASK_CUR_STATE_8822C 0x7f
+#define BIT_CUR_STATE_8822C(x) \
+ (((x) & BIT_MASK_CUR_STATE_8822C) << BIT_SHIFT_CUR_STATE_8822C)
+#define BITS_CUR_STATE_8822C \
+ (BIT_MASK_CUR_STATE_8822C << BIT_SHIFT_CUR_STATE_8822C)
+#define BIT_CLEAR_CUR_STATE_8822C(x) ((x) & (~BITS_CUR_STATE_8822C))
+#define BIT_GET_CUR_STATE_8822C(x) \
+ (((x) >> BIT_SHIFT_CUR_STATE_8822C) & BIT_MASK_CUR_STATE_8822C)
+#define BIT_SET_CUR_STATE_8822C(x, v) \
+ (BIT_CLEAR_CUR_STATE_8822C(x) | BIT_CUR_STATE_8822C(v))
+
+/* 2 REG_ERROR_MON_8822C */
+#define BIT_CSIRPT_LEN_BB_MORE_THAN_MAC_8822C BIT(23)
+#define BIT_CSI_CHKSUM_ERROR_8822C BIT(22)
+#define BIT_MACRX_ERR_4_8822C BIT(20)
+#define BIT_MACRX_ERR_3_8822C BIT(19)
+#define BIT_MACRX_ERR_2_8822C BIT(18)
+#define BIT_MACRX_ERR_1_8822C BIT(17)
+#define BIT_MACRX_ERR_0_8822C BIT(16)
+#define BIT_WMAC_PRETX_ERRHDL_EN_8822C BIT(15)
+#define BIT_MACTX_ERR_5_8822C BIT(5)
+#define BIT_MACTX_ERR_4_8822C BIT(4)
+#define BIT_MACTX_ERR_3_8822C BIT(3)
+#define BIT_MACTX_ERR_2_8822C BIT(2)
+#define BIT_MACTX_ERR_1_8822C BIT(1)
+#define BIT_MACTX_ERR_0_8822C BIT(0)
+
+/* 2 REG_SEARCH_MACID_8822C */
+#define BIT_EN_TXRPTBUF_CLK_8822C BIT(31)
+
+#define BIT_SHIFT_INFO_INDEX_OFFSET_8822C 16
+#define BIT_MASK_INFO_INDEX_OFFSET_8822C 0x1fff
+#define BIT_INFO_INDEX_OFFSET_8822C(x) \
+ (((x) & BIT_MASK_INFO_INDEX_OFFSET_8822C) \
+ << BIT_SHIFT_INFO_INDEX_OFFSET_8822C)
+#define BITS_INFO_INDEX_OFFSET_8822C \
+ (BIT_MASK_INFO_INDEX_OFFSET_8822C << BIT_SHIFT_INFO_INDEX_OFFSET_8822C)
+#define BIT_CLEAR_INFO_INDEX_OFFSET_8822C(x) \
+ ((x) & (~BITS_INFO_INDEX_OFFSET_8822C))
+#define BIT_GET_INFO_INDEX_OFFSET_8822C(x) \
+ (((x) >> BIT_SHIFT_INFO_INDEX_OFFSET_8822C) & \
+ BIT_MASK_INFO_INDEX_OFFSET_8822C)
+#define BIT_SET_INFO_INDEX_OFFSET_8822C(x, v) \
+ (BIT_CLEAR_INFO_INDEX_OFFSET_8822C(x) | BIT_INFO_INDEX_OFFSET_8822C(v))
+
+#define BIT_WMAC_SRCH_FIFOFULL_8822C BIT(15)
+#define BIT_DIS_INFOSRCH_8822C BIT(14)
+
+#define BIT_SHIFT_INFO_ADDR_OFFSET_8822C 0
+#define BIT_MASK_INFO_ADDR_OFFSET_8822C 0x1fff
+#define BIT_INFO_ADDR_OFFSET_8822C(x) \
+ (((x) & BIT_MASK_INFO_ADDR_OFFSET_8822C) \
+ << BIT_SHIFT_INFO_ADDR_OFFSET_8822C)
+#define BITS_INFO_ADDR_OFFSET_8822C \
+ (BIT_MASK_INFO_ADDR_OFFSET_8822C << BIT_SHIFT_INFO_ADDR_OFFSET_8822C)
+#define BIT_CLEAR_INFO_ADDR_OFFSET_8822C(x) \
+ ((x) & (~BITS_INFO_ADDR_OFFSET_8822C))
+#define BIT_GET_INFO_ADDR_OFFSET_8822C(x) \
+ (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8822C) & \
+ BIT_MASK_INFO_ADDR_OFFSET_8822C)
+#define BIT_SET_INFO_ADDR_OFFSET_8822C(x, v) \
+ (BIT_CLEAR_INFO_ADDR_OFFSET_8822C(x) | BIT_INFO_ADDR_OFFSET_8822C(v))
+
+/* 2 REG_BT_COEX_TABLE_8822C (BT-COEXISTENCE CONTROL REGISTER) */
+
+#define BIT_SHIFT_COEX_TABLE_1_8822C 0
+#define BIT_MASK_COEX_TABLE_1_8822C 0xffffffffL
+#define BIT_COEX_TABLE_1_8822C(x) \
+ (((x) & BIT_MASK_COEX_TABLE_1_8822C) << BIT_SHIFT_COEX_TABLE_1_8822C)
+#define BITS_COEX_TABLE_1_8822C \
+ (BIT_MASK_COEX_TABLE_1_8822C << BIT_SHIFT_COEX_TABLE_1_8822C)
+#define BIT_CLEAR_COEX_TABLE_1_8822C(x) ((x) & (~BITS_COEX_TABLE_1_8822C))
+#define BIT_GET_COEX_TABLE_1_8822C(x) \
+ (((x) >> BIT_SHIFT_COEX_TABLE_1_8822C) & BIT_MASK_COEX_TABLE_1_8822C)
+#define BIT_SET_COEX_TABLE_1_8822C(x, v) \
+ (BIT_CLEAR_COEX_TABLE_1_8822C(x) | BIT_COEX_TABLE_1_8822C(v))
+
+/* 2 REG_BT_COEX_TABLE2_8822C (BT-COEXISTENCE CONTROL REGISTER) */
+
+#define BIT_SHIFT_COEX_TABLE_2_8822C 0
+#define BIT_MASK_COEX_TABLE_2_8822C 0xffffffffL
+#define BIT_COEX_TABLE_2_8822C(x) \
+ (((x) & BIT_MASK_COEX_TABLE_2_8822C) << BIT_SHIFT_COEX_TABLE_2_8822C)
+#define BITS_COEX_TABLE_2_8822C \
+ (BIT_MASK_COEX_TABLE_2_8822C << BIT_SHIFT_COEX_TABLE_2_8822C)
+#define BIT_CLEAR_COEX_TABLE_2_8822C(x) ((x) & (~BITS_COEX_TABLE_2_8822C))
+#define BIT_GET_COEX_TABLE_2_8822C(x) \
+ (((x) >> BIT_SHIFT_COEX_TABLE_2_8822C) & BIT_MASK_COEX_TABLE_2_8822C)
+#define BIT_SET_COEX_TABLE_2_8822C(x, v) \
+ (BIT_CLEAR_COEX_TABLE_2_8822C(x) | BIT_COEX_TABLE_2_8822C(v))
+
+/* 2 REG_BT_COEX_BREAK_TABLE_8822C (BT-COEXISTENCE CONTROL REGISTER) */
+
+#define BIT_SHIFT_BREAK_TABLE_2_8822C 16
+#define BIT_MASK_BREAK_TABLE_2_8822C 0xffff
+#define BIT_BREAK_TABLE_2_8822C(x) \
+ (((x) & BIT_MASK_BREAK_TABLE_2_8822C) << BIT_SHIFT_BREAK_TABLE_2_8822C)
+#define BITS_BREAK_TABLE_2_8822C \
+ (BIT_MASK_BREAK_TABLE_2_8822C << BIT_SHIFT_BREAK_TABLE_2_8822C)
+#define BIT_CLEAR_BREAK_TABLE_2_8822C(x) ((x) & (~BITS_BREAK_TABLE_2_8822C))
+#define BIT_GET_BREAK_TABLE_2_8822C(x) \
+ (((x) >> BIT_SHIFT_BREAK_TABLE_2_8822C) & BIT_MASK_BREAK_TABLE_2_8822C)
+#define BIT_SET_BREAK_TABLE_2_8822C(x, v) \
+ (BIT_CLEAR_BREAK_TABLE_2_8822C(x) | BIT_BREAK_TABLE_2_8822C(v))
+
+#define BIT_SHIFT_BREAK_TABLE_1_8822C 0
+#define BIT_MASK_BREAK_TABLE_1_8822C 0xffff
+#define BIT_BREAK_TABLE_1_8822C(x) \
+ (((x) & BIT_MASK_BREAK_TABLE_1_8822C) << BIT_SHIFT_BREAK_TABLE_1_8822C)
+#define BITS_BREAK_TABLE_1_8822C \
+ (BIT_MASK_BREAK_TABLE_1_8822C << BIT_SHIFT_BREAK_TABLE_1_8822C)
+#define BIT_CLEAR_BREAK_TABLE_1_8822C(x) ((x) & (~BITS_BREAK_TABLE_1_8822C))
+#define BIT_GET_BREAK_TABLE_1_8822C(x) \
+ (((x) >> BIT_SHIFT_BREAK_TABLE_1_8822C) & BIT_MASK_BREAK_TABLE_1_8822C)
+#define BIT_SET_BREAK_TABLE_1_8822C(x, v) \
+ (BIT_CLEAR_BREAK_TABLE_1_8822C(x) | BIT_BREAK_TABLE_1_8822C(v))
+
+/* 2 REG_BT_COEX_TABLE_H_8822C (BT-COEXISTENCE CONTROL REGISTER) */
+#define BIT_PRI_MASK_RX_RESP_V1_8822C BIT(30)
+#define BIT_PRI_MASK_RXOFDM_V1_8822C BIT(29)
+#define BIT_PRI_MASK_RXCCK_V1_8822C BIT(28)
+
+#define BIT_SHIFT_PRI_MASK_TXAC_8822C 21
+#define BIT_MASK_PRI_MASK_TXAC_8822C 0x7f
+#define BIT_PRI_MASK_TXAC_8822C(x) \
+ (((x) & BIT_MASK_PRI_MASK_TXAC_8822C) << BIT_SHIFT_PRI_MASK_TXAC_8822C)
+#define BITS_PRI_MASK_TXAC_8822C \
+ (BIT_MASK_PRI_MASK_TXAC_8822C << BIT_SHIFT_PRI_MASK_TXAC_8822C)
+#define BIT_CLEAR_PRI_MASK_TXAC_8822C(x) ((x) & (~BITS_PRI_MASK_TXAC_8822C))
+#define BIT_GET_PRI_MASK_TXAC_8822C(x) \
+ (((x) >> BIT_SHIFT_PRI_MASK_TXAC_8822C) & BIT_MASK_PRI_MASK_TXAC_8822C)
+#define BIT_SET_PRI_MASK_TXAC_8822C(x, v) \
+ (BIT_CLEAR_PRI_MASK_TXAC_8822C(x) | BIT_PRI_MASK_TXAC_8822C(v))
+
+#define BIT_SHIFT_PRI_MASK_NAV_8822C 13
+#define BIT_MASK_PRI_MASK_NAV_8822C 0xff
+#define BIT_PRI_MASK_NAV_8822C(x) \
+ (((x) & BIT_MASK_PRI_MASK_NAV_8822C) << BIT_SHIFT_PRI_MASK_NAV_8822C)
+#define BITS_PRI_MASK_NAV_8822C \
+ (BIT_MASK_PRI_MASK_NAV_8822C << BIT_SHIFT_PRI_MASK_NAV_8822C)
+#define BIT_CLEAR_PRI_MASK_NAV_8822C(x) ((x) & (~BITS_PRI_MASK_NAV_8822C))
+#define BIT_GET_PRI_MASK_NAV_8822C(x) \
+ (((x) >> BIT_SHIFT_PRI_MASK_NAV_8822C) & BIT_MASK_PRI_MASK_NAV_8822C)
+#define BIT_SET_PRI_MASK_NAV_8822C(x, v) \
+ (BIT_CLEAR_PRI_MASK_NAV_8822C(x) | BIT_PRI_MASK_NAV_8822C(v))
+
+#define BIT_PRI_MASK_CCK_V1_8822C BIT(12)
+#define BIT_PRI_MASK_OFDM_V1_8822C BIT(11)
+#define BIT_PRI_MASK_RTY_V1_8822C BIT(10)
+
+#define BIT_SHIFT_PRI_MASK_NUM_8822C 6
+#define BIT_MASK_PRI_MASK_NUM_8822C 0xf
+#define BIT_PRI_MASK_NUM_8822C(x) \
+ (((x) & BIT_MASK_PRI_MASK_NUM_8822C) << BIT_SHIFT_PRI_MASK_NUM_8822C)
+#define BITS_PRI_MASK_NUM_8822C \
+ (BIT_MASK_PRI_MASK_NUM_8822C << BIT_SHIFT_PRI_MASK_NUM_8822C)
+#define BIT_CLEAR_PRI_MASK_NUM_8822C(x) ((x) & (~BITS_PRI_MASK_NUM_8822C))
+#define BIT_GET_PRI_MASK_NUM_8822C(x) \
+ (((x) >> BIT_SHIFT_PRI_MASK_NUM_8822C) & BIT_MASK_PRI_MASK_NUM_8822C)
+#define BIT_SET_PRI_MASK_NUM_8822C(x, v) \
+ (BIT_CLEAR_PRI_MASK_NUM_8822C(x) | BIT_PRI_MASK_NUM_8822C(v))
+
+#define BIT_SHIFT_PRI_MASK_TYPE_8822C 2
+#define BIT_MASK_PRI_MASK_TYPE_8822C 0xf
+#define BIT_PRI_MASK_TYPE_8822C(x) \
+ (((x) & BIT_MASK_PRI_MASK_TYPE_8822C) << BIT_SHIFT_PRI_MASK_TYPE_8822C)
+#define BITS_PRI_MASK_TYPE_8822C \
+ (BIT_MASK_PRI_MASK_TYPE_8822C << BIT_SHIFT_PRI_MASK_TYPE_8822C)
+#define BIT_CLEAR_PRI_MASK_TYPE_8822C(x) ((x) & (~BITS_PRI_MASK_TYPE_8822C))
+#define BIT_GET_PRI_MASK_TYPE_8822C(x) \
+ (((x) >> BIT_SHIFT_PRI_MASK_TYPE_8822C) & BIT_MASK_PRI_MASK_TYPE_8822C)
+#define BIT_SET_PRI_MASK_TYPE_8822C(x, v) \
+ (BIT_CLEAR_PRI_MASK_TYPE_8822C(x) | BIT_PRI_MASK_TYPE_8822C(v))
+
+#define BIT_OOB_V1_8822C BIT(1)
+#define BIT_ANT_SEL_V1_8822C BIT(0)
+
+/* 2 REG_RXCMD_0_8822C */
+#define BIT_RXCMD_EN_8822C BIT(31)
+
+#define BIT_SHIFT_RXCMD_INFO_8822C 0
+#define BIT_MASK_RXCMD_INFO_8822C 0x7fffffffL
+#define BIT_RXCMD_INFO_8822C(x) \
+ (((x) & BIT_MASK_RXCMD_INFO_8822C) << BIT_SHIFT_RXCMD_INFO_8822C)
+#define BITS_RXCMD_INFO_8822C \
+ (BIT_MASK_RXCMD_INFO_8822C << BIT_SHIFT_RXCMD_INFO_8822C)
+#define BIT_CLEAR_RXCMD_INFO_8822C(x) ((x) & (~BITS_RXCMD_INFO_8822C))
+#define BIT_GET_RXCMD_INFO_8822C(x) \
+ (((x) >> BIT_SHIFT_RXCMD_INFO_8822C) & BIT_MASK_RXCMD_INFO_8822C)
+#define BIT_SET_RXCMD_INFO_8822C(x, v) \
+ (BIT_CLEAR_RXCMD_INFO_8822C(x) | BIT_RXCMD_INFO_8822C(v))
+
+/* 2 REG_RXCMD_1_8822C */
+
+#define BIT_SHIFT_RXCMD_PRD_8822C 0
+#define BIT_MASK_RXCMD_PRD_8822C 0xffff
+#define BIT_RXCMD_PRD_8822C(x) \
+ (((x) & BIT_MASK_RXCMD_PRD_8822C) << BIT_SHIFT_RXCMD_PRD_8822C)
+#define BITS_RXCMD_PRD_8822C \
+ (BIT_MASK_RXCMD_PRD_8822C << BIT_SHIFT_RXCMD_PRD_8822C)
+#define BIT_CLEAR_RXCMD_PRD_8822C(x) ((x) & (~BITS_RXCMD_PRD_8822C))
+#define BIT_GET_RXCMD_PRD_8822C(x) \
+ (((x) >> BIT_SHIFT_RXCMD_PRD_8822C) & BIT_MASK_RXCMD_PRD_8822C)
+#define BIT_SET_RXCMD_PRD_8822C(x, v) \
+ (BIT_CLEAR_RXCMD_PRD_8822C(x) | BIT_RXCMD_PRD_8822C(v))
+
+/* 2 REG_WMAC_RESP_TXINFO_8822C (RESPONSE TXINFO REGISTER) */
+
+#define BIT_SHIFT_WMAC_RESP_MFB_8822C 25
+#define BIT_MASK_WMAC_RESP_MFB_8822C 0x7f
+#define BIT_WMAC_RESP_MFB_8822C(x) \
+ (((x) & BIT_MASK_WMAC_RESP_MFB_8822C) << BIT_SHIFT_WMAC_RESP_MFB_8822C)
+#define BITS_WMAC_RESP_MFB_8822C \
+ (BIT_MASK_WMAC_RESP_MFB_8822C << BIT_SHIFT_WMAC_RESP_MFB_8822C)
+#define BIT_CLEAR_WMAC_RESP_MFB_8822C(x) ((x) & (~BITS_WMAC_RESP_MFB_8822C))
+#define BIT_GET_WMAC_RESP_MFB_8822C(x) \
+ (((x) >> BIT_SHIFT_WMAC_RESP_MFB_8822C) & BIT_MASK_WMAC_RESP_MFB_8822C)
+#define BIT_SET_WMAC_RESP_MFB_8822C(x, v) \
+ (BIT_CLEAR_WMAC_RESP_MFB_8822C(x) | BIT_WMAC_RESP_MFB_8822C(v))
+
+#define BIT_SHIFT_WMAC_ANTINF_SEL_8822C 23
+#define BIT_MASK_WMAC_ANTINF_SEL_8822C 0x3
+#define BIT_WMAC_ANTINF_SEL_8822C(x) \
+ (((x) & BIT_MASK_WMAC_ANTINF_SEL_8822C) \
+ << BIT_SHIFT_WMAC_ANTINF_SEL_8822C)
+#define BITS_WMAC_ANTINF_SEL_8822C \
+ (BIT_MASK_WMAC_ANTINF_SEL_8822C << BIT_SHIFT_WMAC_ANTINF_SEL_8822C)
+#define BIT_CLEAR_WMAC_ANTINF_SEL_8822C(x) ((x) & (~BITS_WMAC_ANTINF_SEL_8822C))
+#define BIT_GET_WMAC_ANTINF_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8822C) & \
+ BIT_MASK_WMAC_ANTINF_SEL_8822C)
+#define BIT_SET_WMAC_ANTINF_SEL_8822C(x, v) \
+ (BIT_CLEAR_WMAC_ANTINF_SEL_8822C(x) | BIT_WMAC_ANTINF_SEL_8822C(v))
+
+#define BIT_SHIFT_WMAC_ANTSEL_SEL_8822C 21
+#define BIT_MASK_WMAC_ANTSEL_SEL_8822C 0x3
+#define BIT_WMAC_ANTSEL_SEL_8822C(x) \
+ (((x) & BIT_MASK_WMAC_ANTSEL_SEL_8822C) \
+ << BIT_SHIFT_WMAC_ANTSEL_SEL_8822C)
+#define BITS_WMAC_ANTSEL_SEL_8822C \
+ (BIT_MASK_WMAC_ANTSEL_SEL_8822C << BIT_SHIFT_WMAC_ANTSEL_SEL_8822C)
+#define BIT_CLEAR_WMAC_ANTSEL_SEL_8822C(x) ((x) & (~BITS_WMAC_ANTSEL_SEL_8822C))
+#define BIT_GET_WMAC_ANTSEL_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8822C) & \
+ BIT_MASK_WMAC_ANTSEL_SEL_8822C)
+#define BIT_SET_WMAC_ANTSEL_SEL_8822C(x, v) \
+ (BIT_CLEAR_WMAC_ANTSEL_SEL_8822C(x) | BIT_WMAC_ANTSEL_SEL_8822C(v))
+
+#define BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C 18
+#define BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C 0x3
+#define BIT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C(x) \
+ (((x) & BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C) \
+ << BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C)
+#define BITS_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C \
+ (BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C \
+ << BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C)
+#define BIT_CLEAR_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C(x) \
+ ((x) & (~BITS_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C))
+#define BIT_GET_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C(x) \
+ (((x) >> BIT_SHIFT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C) & \
+ BIT_MASK_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C)
+#define BIT_SET_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C(x, v) \
+ (BIT_CLEAR_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C(x) | \
+ BIT_WMAC_RESP_TXPOWER_OFFSET_TYPE_8822C(v))
+
+#define BIT_SHIFT_WMAC_RESP_TXANT_V1_8822C 6
+#define BIT_MASK_WMAC_RESP_TXANT_V1_8822C 0xfff
+#define BIT_WMAC_RESP_TXANT_V1_8822C(x) \
+ (((x) & BIT_MASK_WMAC_RESP_TXANT_V1_8822C) \
+ << BIT_SHIFT_WMAC_RESP_TXANT_V1_8822C)
+#define BITS_WMAC_RESP_TXANT_V1_8822C \
+ (BIT_MASK_WMAC_RESP_TXANT_V1_8822C \
+ << BIT_SHIFT_WMAC_RESP_TXANT_V1_8822C)
+#define BIT_CLEAR_WMAC_RESP_TXANT_V1_8822C(x) \
+ ((x) & (~BITS_WMAC_RESP_TXANT_V1_8822C))
+#define BIT_GET_WMAC_RESP_TXANT_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_WMAC_RESP_TXANT_V1_8822C) & \
+ BIT_MASK_WMAC_RESP_TXANT_V1_8822C)
+#define BIT_SET_WMAC_RESP_TXANT_V1_8822C(x, v) \
+ (BIT_CLEAR_WMAC_RESP_TXANT_V1_8822C(x) | \
+ BIT_WMAC_RESP_TXANT_V1_8822C(v))
+
+/* 2 REG_BBPSF_CTRL_8822C */
+#define BIT_CTL_IDLE_CLR_CSI_RPT_8822C BIT(31)
+#define BIT_WMAC_USE_NDPARATE_8822C BIT(30)
+
+#define BIT_SHIFT_WMAC_CSI_RATE_8822C 24
+#define BIT_MASK_WMAC_CSI_RATE_8822C 0x3f
+#define BIT_WMAC_CSI_RATE_8822C(x) \
+ (((x) & BIT_MASK_WMAC_CSI_RATE_8822C) << BIT_SHIFT_WMAC_CSI_RATE_8822C)
+#define BITS_WMAC_CSI_RATE_8822C \
+ (BIT_MASK_WMAC_CSI_RATE_8822C << BIT_SHIFT_WMAC_CSI_RATE_8822C)
+#define BIT_CLEAR_WMAC_CSI_RATE_8822C(x) ((x) & (~BITS_WMAC_CSI_RATE_8822C))
+#define BIT_GET_WMAC_CSI_RATE_8822C(x) \
+ (((x) >> BIT_SHIFT_WMAC_CSI_RATE_8822C) & BIT_MASK_WMAC_CSI_RATE_8822C)
+#define BIT_SET_WMAC_CSI_RATE_8822C(x, v) \
+ (BIT_CLEAR_WMAC_CSI_RATE_8822C(x) | BIT_WMAC_CSI_RATE_8822C(v))
+
+#define BIT_SHIFT_WMAC_RESP_TXRATE_8822C 16
+#define BIT_MASK_WMAC_RESP_TXRATE_8822C 0xff
+#define BIT_WMAC_RESP_TXRATE_8822C(x) \
+ (((x) & BIT_MASK_WMAC_RESP_TXRATE_8822C) \
+ << BIT_SHIFT_WMAC_RESP_TXRATE_8822C)
+#define BITS_WMAC_RESP_TXRATE_8822C \
+ (BIT_MASK_WMAC_RESP_TXRATE_8822C << BIT_SHIFT_WMAC_RESP_TXRATE_8822C)
+#define BIT_CLEAR_WMAC_RESP_TXRATE_8822C(x) \
+ ((x) & (~BITS_WMAC_RESP_TXRATE_8822C))
+#define BIT_GET_WMAC_RESP_TXRATE_8822C(x) \
+ (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8822C) & \
+ BIT_MASK_WMAC_RESP_TXRATE_8822C)
+#define BIT_SET_WMAC_RESP_TXRATE_8822C(x, v) \
+ (BIT_CLEAR_WMAC_RESP_TXRATE_8822C(x) | BIT_WMAC_RESP_TXRATE_8822C(v))
+
+#define BIT_SHIFT_CSI_RSC_8822C 13
+#define BIT_MASK_CSI_RSC_8822C 0x3
+#define BIT_CSI_RSC_8822C(x) \
+ (((x) & BIT_MASK_CSI_RSC_8822C) << BIT_SHIFT_CSI_RSC_8822C)
+#define BITS_CSI_RSC_8822C (BIT_MASK_CSI_RSC_8822C << BIT_SHIFT_CSI_RSC_8822C)
+#define BIT_CLEAR_CSI_RSC_8822C(x) ((x) & (~BITS_CSI_RSC_8822C))
+#define BIT_GET_CSI_RSC_8822C(x) \
+ (((x) >> BIT_SHIFT_CSI_RSC_8822C) & BIT_MASK_CSI_RSC_8822C)
+#define BIT_SET_CSI_RSC_8822C(x, v) \
+ (BIT_CLEAR_CSI_RSC_8822C(x) | BIT_CSI_RSC_8822C(v))
+
+#define BIT_CSI_GID_SEL_8822C BIT(12)
+#define BIT_NDPVLD_PROTECT_RDRDY_DIS_8822C BIT(9)
+#define BIT_RDCSI_EMPTY_APPZERO_8822C BIT(8)
+#define BIT_CSI_RATE_FB_EN_8822C BIT(7)
+#define BIT_RXFIFO_WRPTR_WO_CHKSUM_8822C BIT(6)
+
+/* 2 REG_P2P_RX_BCN_NOA_8822C (P2P RX BEACON NOA REGISTER) */
+#define BIT_NOA_PARSER_EN_8822C BIT(15)
+
+#define BIT_SHIFT_BSSID_SEL_V1_8822C 12
+#define BIT_MASK_BSSID_SEL_V1_8822C 0x7
+#define BIT_BSSID_SEL_V1_8822C(x) \
+ (((x) & BIT_MASK_BSSID_SEL_V1_8822C) << BIT_SHIFT_BSSID_SEL_V1_8822C)
+#define BITS_BSSID_SEL_V1_8822C \
+ (BIT_MASK_BSSID_SEL_V1_8822C << BIT_SHIFT_BSSID_SEL_V1_8822C)
+#define BIT_CLEAR_BSSID_SEL_V1_8822C(x) ((x) & (~BITS_BSSID_SEL_V1_8822C))
+#define BIT_GET_BSSID_SEL_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_BSSID_SEL_V1_8822C) & BIT_MASK_BSSID_SEL_V1_8822C)
+#define BIT_SET_BSSID_SEL_V1_8822C(x, v) \
+ (BIT_CLEAR_BSSID_SEL_V1_8822C(x) | BIT_BSSID_SEL_V1_8822C(v))
+
+#define BIT_SHIFT_P2P_OUI_TYPE_8822C 0
+#define BIT_MASK_P2P_OUI_TYPE_8822C 0xff
+#define BIT_P2P_OUI_TYPE_8822C(x) \
+ (((x) & BIT_MASK_P2P_OUI_TYPE_8822C) << BIT_SHIFT_P2P_OUI_TYPE_8822C)
+#define BITS_P2P_OUI_TYPE_8822C \
+ (BIT_MASK_P2P_OUI_TYPE_8822C << BIT_SHIFT_P2P_OUI_TYPE_8822C)
+#define BIT_CLEAR_P2P_OUI_TYPE_8822C(x) ((x) & (~BITS_P2P_OUI_TYPE_8822C))
+#define BIT_GET_P2P_OUI_TYPE_8822C(x) \
+ (((x) >> BIT_SHIFT_P2P_OUI_TYPE_8822C) & BIT_MASK_P2P_OUI_TYPE_8822C)
+#define BIT_SET_P2P_OUI_TYPE_8822C(x, v) \
+ (BIT_CLEAR_P2P_OUI_TYPE_8822C(x) | BIT_P2P_OUI_TYPE_8822C(v))
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_ASSOCIATED_BFMER0_INFO_8822C (ASSOCIATED BEAMFORMER0 INFO REGISTER) */
+
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8822C 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8822C 0xffffffffL
+#define BIT_R_WMAC_SOUNDING_RXADD_R0_V1_8822C(x) \
+ (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8822C) \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8822C)
+#define BITS_R_WMAC_SOUNDING_RXADD_R0_V1_8822C \
+ (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8822C \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8822C)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1_8822C(x) \
+ ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_V1_8822C))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1_8822C) & \
+ BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1_8822C)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_V1_8822C(x, v) \
+ (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1_8822C(x) | \
+ BIT_R_WMAC_SOUNDING_RXADD_R0_V1_8822C(v))
+
+/* 2 REG_ASSOCIATED_BFMER0_INFO_H_8822C */
+
+#define BIT_SHIFT_R_WMAC_TXCSI_AID0_8822C 16
+#define BIT_MASK_R_WMAC_TXCSI_AID0_8822C 0x1ff
+#define BIT_R_WMAC_TXCSI_AID0_8822C(x) \
+ (((x) & BIT_MASK_R_WMAC_TXCSI_AID0_8822C) \
+ << BIT_SHIFT_R_WMAC_TXCSI_AID0_8822C)
+#define BITS_R_WMAC_TXCSI_AID0_8822C \
+ (BIT_MASK_R_WMAC_TXCSI_AID0_8822C << BIT_SHIFT_R_WMAC_TXCSI_AID0_8822C)
+#define BIT_CLEAR_R_WMAC_TXCSI_AID0_8822C(x) \
+ ((x) & (~BITS_R_WMAC_TXCSI_AID0_8822C))
+#define BIT_GET_R_WMAC_TXCSI_AID0_8822C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8822C) & \
+ BIT_MASK_R_WMAC_TXCSI_AID0_8822C)
+#define BIT_SET_R_WMAC_TXCSI_AID0_8822C(x, v) \
+ (BIT_CLEAR_R_WMAC_TXCSI_AID0_8822C(x) | BIT_R_WMAC_TXCSI_AID0_8822C(v))
+
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C 0xffff
+#define BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C(x) \
+ (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C) \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C)
+#define BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C \
+ (BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C(x) \
+ ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C) & \
+ BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C(x, v) \
+ (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C(x) | \
+ BIT_R_WMAC_SOUNDING_RXADD_R0_H_V1_8822C(v))
+
+/* 2 REG_ASSOCIATED_BFMER1_INFO_8822C (ASSOCIATED BEAMFORMER1 INFO REGISTER) */
+
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8822C 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8822C 0xffffffffL
+#define BIT_R_WMAC_SOUNDING_RXADD_R1_V1_8822C(x) \
+ (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8822C) \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8822C)
+#define BITS_R_WMAC_SOUNDING_RXADD_R1_V1_8822C \
+ (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8822C \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8822C)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1_8822C(x) \
+ ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_V1_8822C))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V1_8822C) & \
+ BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V1_8822C)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_V1_8822C(x, v) \
+ (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V1_8822C(x) | \
+ BIT_R_WMAC_SOUNDING_RXADD_R1_V1_8822C(v))
+
+/* 2 REG_ASSOCIATED_BFMER1_INFO_H_8822C */
+
+#define BIT_SHIFT_R_WMAC_TXCSI_AID1_8822C 16
+#define BIT_MASK_R_WMAC_TXCSI_AID1_8822C 0x1ff
+#define BIT_R_WMAC_TXCSI_AID1_8822C(x) \
+ (((x) & BIT_MASK_R_WMAC_TXCSI_AID1_8822C) \
+ << BIT_SHIFT_R_WMAC_TXCSI_AID1_8822C)
+#define BITS_R_WMAC_TXCSI_AID1_8822C \
+ (BIT_MASK_R_WMAC_TXCSI_AID1_8822C << BIT_SHIFT_R_WMAC_TXCSI_AID1_8822C)
+#define BIT_CLEAR_R_WMAC_TXCSI_AID1_8822C(x) \
+ ((x) & (~BITS_R_WMAC_TXCSI_AID1_8822C))
+#define BIT_GET_R_WMAC_TXCSI_AID1_8822C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8822C) & \
+ BIT_MASK_R_WMAC_TXCSI_AID1_8822C)
+#define BIT_SET_R_WMAC_TXCSI_AID1_8822C(x, v) \
+ (BIT_CLEAR_R_WMAC_TXCSI_AID1_8822C(x) | BIT_R_WMAC_TXCSI_AID1_8822C(v))
+
+#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C 0
+#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C 0xffff
+#define BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C(x) \
+ (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C) \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C)
+#define BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C \
+ (BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C \
+ << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C)
+#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C(x) \
+ ((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C))
+#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C) & \
+ BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C)
+#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C(x, v) \
+ (BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C(x) | \
+ BIT_R_WMAC_SOUNDING_RXADD_R1_H_V1_8822C(v))
+
+/* 2 REG_TX_CSI_RPT_PARAM_BW20_8822C (TX CSI REPORT PARAMETER REGISTER) */
+
+#define BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822C 16
+#define BIT_MASK_R_WMAC_BFINFO_20M_1_8822C 0xfff
+#define BIT_R_WMAC_BFINFO_20M_1_8822C(x) \
+ (((x) & BIT_MASK_R_WMAC_BFINFO_20M_1_8822C) \
+ << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822C)
+#define BITS_R_WMAC_BFINFO_20M_1_8822C \
+ (BIT_MASK_R_WMAC_BFINFO_20M_1_8822C \
+ << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822C)
+#define BIT_CLEAR_R_WMAC_BFINFO_20M_1_8822C(x) \
+ ((x) & (~BITS_R_WMAC_BFINFO_20M_1_8822C))
+#define BIT_GET_R_WMAC_BFINFO_20M_1_8822C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8822C) & \
+ BIT_MASK_R_WMAC_BFINFO_20M_1_8822C)
+#define BIT_SET_R_WMAC_BFINFO_20M_1_8822C(x, v) \
+ (BIT_CLEAR_R_WMAC_BFINFO_20M_1_8822C(x) | \
+ BIT_R_WMAC_BFINFO_20M_1_8822C(v))
+
+#define BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822C 0
+#define BIT_MASK_R_WMAC_BFINFO_20M_0_8822C 0xfff
+#define BIT_R_WMAC_BFINFO_20M_0_8822C(x) \
+ (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8822C) \
+ << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822C)
+#define BITS_R_WMAC_BFINFO_20M_0_8822C \
+ (BIT_MASK_R_WMAC_BFINFO_20M_0_8822C \
+ << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822C)
+#define BIT_CLEAR_R_WMAC_BFINFO_20M_0_8822C(x) \
+ ((x) & (~BITS_R_WMAC_BFINFO_20M_0_8822C))
+#define BIT_GET_R_WMAC_BFINFO_20M_0_8822C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8822C) & \
+ BIT_MASK_R_WMAC_BFINFO_20M_0_8822C)
+#define BIT_SET_R_WMAC_BFINFO_20M_0_8822C(x, v) \
+ (BIT_CLEAR_R_WMAC_BFINFO_20M_0_8822C(x) | \
+ BIT_R_WMAC_BFINFO_20M_0_8822C(v))
+
+/* 2 REG_TX_CSI_RPT_PARAM_BW40_8822C (TX CSI REPORT PARAMETER_BW40 REGISTER) */
+
+#define BIT_SHIFT_WMAC_RESP_ANTD_8822C 12
+#define BIT_MASK_WMAC_RESP_ANTD_8822C 0xf
+#define BIT_WMAC_RESP_ANTD_8822C(x) \
+ (((x) & BIT_MASK_WMAC_RESP_ANTD_8822C) \
+ << BIT_SHIFT_WMAC_RESP_ANTD_8822C)
+#define BITS_WMAC_RESP_ANTD_8822C \
+ (BIT_MASK_WMAC_RESP_ANTD_8822C << BIT_SHIFT_WMAC_RESP_ANTD_8822C)
+#define BIT_CLEAR_WMAC_RESP_ANTD_8822C(x) ((x) & (~BITS_WMAC_RESP_ANTD_8822C))
+#define BIT_GET_WMAC_RESP_ANTD_8822C(x) \
+ (((x) >> BIT_SHIFT_WMAC_RESP_ANTD_8822C) & \
+ BIT_MASK_WMAC_RESP_ANTD_8822C)
+#define BIT_SET_WMAC_RESP_ANTD_8822C(x, v) \
+ (BIT_CLEAR_WMAC_RESP_ANTD_8822C(x) | BIT_WMAC_RESP_ANTD_8822C(v))
+
+#define BIT_SHIFT_WMAC_RESP_ANTC_8822C 8
+#define BIT_MASK_WMAC_RESP_ANTC_8822C 0xf
+#define BIT_WMAC_RESP_ANTC_8822C(x) \
+ (((x) & BIT_MASK_WMAC_RESP_ANTC_8822C) \
+ << BIT_SHIFT_WMAC_RESP_ANTC_8822C)
+#define BITS_WMAC_RESP_ANTC_8822C \
+ (BIT_MASK_WMAC_RESP_ANTC_8822C << BIT_SHIFT_WMAC_RESP_ANTC_8822C)
+#define BIT_CLEAR_WMAC_RESP_ANTC_8822C(x) ((x) & (~BITS_WMAC_RESP_ANTC_8822C))
+#define BIT_GET_WMAC_RESP_ANTC_8822C(x) \
+ (((x) >> BIT_SHIFT_WMAC_RESP_ANTC_8822C) & \
+ BIT_MASK_WMAC_RESP_ANTC_8822C)
+#define BIT_SET_WMAC_RESP_ANTC_8822C(x, v) \
+ (BIT_CLEAR_WMAC_RESP_ANTC_8822C(x) | BIT_WMAC_RESP_ANTC_8822C(v))
+
+#define BIT_SHIFT_WMAC_RESP_ANTB_8822C 4
+#define BIT_MASK_WMAC_RESP_ANTB_8822C 0xf
+#define BIT_WMAC_RESP_ANTB_8822C(x) \
+ (((x) & BIT_MASK_WMAC_RESP_ANTB_8822C) \
+ << BIT_SHIFT_WMAC_RESP_ANTB_8822C)
+#define BITS_WMAC_RESP_ANTB_8822C \
+ (BIT_MASK_WMAC_RESP_ANTB_8822C << BIT_SHIFT_WMAC_RESP_ANTB_8822C)
+#define BIT_CLEAR_WMAC_RESP_ANTB_8822C(x) ((x) & (~BITS_WMAC_RESP_ANTB_8822C))
+#define BIT_GET_WMAC_RESP_ANTB_8822C(x) \
+ (((x) >> BIT_SHIFT_WMAC_RESP_ANTB_8822C) & \
+ BIT_MASK_WMAC_RESP_ANTB_8822C)
+#define BIT_SET_WMAC_RESP_ANTB_8822C(x, v) \
+ (BIT_CLEAR_WMAC_RESP_ANTB_8822C(x) | BIT_WMAC_RESP_ANTB_8822C(v))
+
+#define BIT_SHIFT_WMAC_RESP_ANTA_8822C 0
+#define BIT_MASK_WMAC_RESP_ANTA_8822C 0xf
+#define BIT_WMAC_RESP_ANTA_8822C(x) \
+ (((x) & BIT_MASK_WMAC_RESP_ANTA_8822C) \
+ << BIT_SHIFT_WMAC_RESP_ANTA_8822C)
+#define BITS_WMAC_RESP_ANTA_8822C \
+ (BIT_MASK_WMAC_RESP_ANTA_8822C << BIT_SHIFT_WMAC_RESP_ANTA_8822C)
+#define BIT_CLEAR_WMAC_RESP_ANTA_8822C(x) ((x) & (~BITS_WMAC_RESP_ANTA_8822C))
+#define BIT_GET_WMAC_RESP_ANTA_8822C(x) \
+ (((x) >> BIT_SHIFT_WMAC_RESP_ANTA_8822C) & \
+ BIT_MASK_WMAC_RESP_ANTA_8822C)
+#define BIT_SET_WMAC_RESP_ANTA_8822C(x, v) \
+ (BIT_CLEAR_WMAC_RESP_ANTA_8822C(x) | BIT_WMAC_RESP_ANTA_8822C(v))
+
+/* 2 REG_CSI_PTR_8822C */
+
+#define BIT_SHIFT_CSI_RADDR_LATCH_V2_8822C 16
+#define BIT_MASK_CSI_RADDR_LATCH_V2_8822C 0xffff
+#define BIT_CSI_RADDR_LATCH_V2_8822C(x) \
+ (((x) & BIT_MASK_CSI_RADDR_LATCH_V2_8822C) \
+ << BIT_SHIFT_CSI_RADDR_LATCH_V2_8822C)
+#define BITS_CSI_RADDR_LATCH_V2_8822C \
+ (BIT_MASK_CSI_RADDR_LATCH_V2_8822C \
+ << BIT_SHIFT_CSI_RADDR_LATCH_V2_8822C)
+#define BIT_CLEAR_CSI_RADDR_LATCH_V2_8822C(x) \
+ ((x) & (~BITS_CSI_RADDR_LATCH_V2_8822C))
+#define BIT_GET_CSI_RADDR_LATCH_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_CSI_RADDR_LATCH_V2_8822C) & \
+ BIT_MASK_CSI_RADDR_LATCH_V2_8822C)
+#define BIT_SET_CSI_RADDR_LATCH_V2_8822C(x, v) \
+ (BIT_CLEAR_CSI_RADDR_LATCH_V2_8822C(x) | \
+ BIT_CSI_RADDR_LATCH_V2_8822C(v))
+
+#define BIT_SHIFT_CSI_WADDR_LATCH_V2_8822C 0
+#define BIT_MASK_CSI_WADDR_LATCH_V2_8822C 0xffff
+#define BIT_CSI_WADDR_LATCH_V2_8822C(x) \
+ (((x) & BIT_MASK_CSI_WADDR_LATCH_V2_8822C) \
+ << BIT_SHIFT_CSI_WADDR_LATCH_V2_8822C)
+#define BITS_CSI_WADDR_LATCH_V2_8822C \
+ (BIT_MASK_CSI_WADDR_LATCH_V2_8822C \
+ << BIT_SHIFT_CSI_WADDR_LATCH_V2_8822C)
+#define BIT_CLEAR_CSI_WADDR_LATCH_V2_8822C(x) \
+ ((x) & (~BITS_CSI_WADDR_LATCH_V2_8822C))
+#define BIT_GET_CSI_WADDR_LATCH_V2_8822C(x) \
+ (((x) >> BIT_SHIFT_CSI_WADDR_LATCH_V2_8822C) & \
+ BIT_MASK_CSI_WADDR_LATCH_V2_8822C)
+#define BIT_SET_CSI_WADDR_LATCH_V2_8822C(x, v) \
+ (BIT_CLEAR_CSI_WADDR_LATCH_V2_8822C(x) | \
+ BIT_CSI_WADDR_LATCH_V2_8822C(v))
+
+/* 2 REG_BCN_PSR_RPT2_8822C (BEACON PARSER REPORT REGISTER2) */
+
+#define BIT_SHIFT_DTIM_CNT2_8822C 24
+#define BIT_MASK_DTIM_CNT2_8822C 0xff
+#define BIT_DTIM_CNT2_8822C(x) \
+ (((x) & BIT_MASK_DTIM_CNT2_8822C) << BIT_SHIFT_DTIM_CNT2_8822C)
+#define BITS_DTIM_CNT2_8822C \
+ (BIT_MASK_DTIM_CNT2_8822C << BIT_SHIFT_DTIM_CNT2_8822C)
+#define BIT_CLEAR_DTIM_CNT2_8822C(x) ((x) & (~BITS_DTIM_CNT2_8822C))
+#define BIT_GET_DTIM_CNT2_8822C(x) \
+ (((x) >> BIT_SHIFT_DTIM_CNT2_8822C) & BIT_MASK_DTIM_CNT2_8822C)
+#define BIT_SET_DTIM_CNT2_8822C(x, v) \
+ (BIT_CLEAR_DTIM_CNT2_8822C(x) | BIT_DTIM_CNT2_8822C(v))
+
+#define BIT_SHIFT_DTIM_PERIOD2_8822C 16
+#define BIT_MASK_DTIM_PERIOD2_8822C 0xff
+#define BIT_DTIM_PERIOD2_8822C(x) \
+ (((x) & BIT_MASK_DTIM_PERIOD2_8822C) << BIT_SHIFT_DTIM_PERIOD2_8822C)
+#define BITS_DTIM_PERIOD2_8822C \
+ (BIT_MASK_DTIM_PERIOD2_8822C << BIT_SHIFT_DTIM_PERIOD2_8822C)
+#define BIT_CLEAR_DTIM_PERIOD2_8822C(x) ((x) & (~BITS_DTIM_PERIOD2_8822C))
+#define BIT_GET_DTIM_PERIOD2_8822C(x) \
+ (((x) >> BIT_SHIFT_DTIM_PERIOD2_8822C) & BIT_MASK_DTIM_PERIOD2_8822C)
+#define BIT_SET_DTIM_PERIOD2_8822C(x, v) \
+ (BIT_CLEAR_DTIM_PERIOD2_8822C(x) | BIT_DTIM_PERIOD2_8822C(v))
+
+#define BIT_DTIM2_8822C BIT(15)
+#define BIT_TIM2_8822C BIT(14)
+#define BIT_RPT_VALID_8822C BIT(13)
+
+#define BIT_SHIFT_PS_AID_2_8822C 0
+#define BIT_MASK_PS_AID_2_8822C 0x7ff
+#define BIT_PS_AID_2_8822C(x) \
+ (((x) & BIT_MASK_PS_AID_2_8822C) << BIT_SHIFT_PS_AID_2_8822C)
+#define BITS_PS_AID_2_8822C \
+ (BIT_MASK_PS_AID_2_8822C << BIT_SHIFT_PS_AID_2_8822C)
+#define BIT_CLEAR_PS_AID_2_8822C(x) ((x) & (~BITS_PS_AID_2_8822C))
+#define BIT_GET_PS_AID_2_8822C(x) \
+ (((x) >> BIT_SHIFT_PS_AID_2_8822C) & BIT_MASK_PS_AID_2_8822C)
+#define BIT_SET_PS_AID_2_8822C(x, v) \
+ (BIT_CLEAR_PS_AID_2_8822C(x) | BIT_PS_AID_2_8822C(v))
+
+/* 2 REG_BCN_PSR_RPT3_8822C (BEACON PARSER REPORT REGISTER3) */
+
+#define BIT_SHIFT_DTIM_CNT3_8822C 24
+#define BIT_MASK_DTIM_CNT3_8822C 0xff
+#define BIT_DTIM_CNT3_8822C(x) \
+ (((x) & BIT_MASK_DTIM_CNT3_8822C) << BIT_SHIFT_DTIM_CNT3_8822C)
+#define BITS_DTIM_CNT3_8822C \
+ (BIT_MASK_DTIM_CNT3_8822C << BIT_SHIFT_DTIM_CNT3_8822C)
+#define BIT_CLEAR_DTIM_CNT3_8822C(x) ((x) & (~BITS_DTIM_CNT3_8822C))
+#define BIT_GET_DTIM_CNT3_8822C(x) \
+ (((x) >> BIT_SHIFT_DTIM_CNT3_8822C) & BIT_MASK_DTIM_CNT3_8822C)
+#define BIT_SET_DTIM_CNT3_8822C(x, v) \
+ (BIT_CLEAR_DTIM_CNT3_8822C(x) | BIT_DTIM_CNT3_8822C(v))
+
+#define BIT_SHIFT_DTIM_PERIOD3_8822C 16
+#define BIT_MASK_DTIM_PERIOD3_8822C 0xff
+#define BIT_DTIM_PERIOD3_8822C(x) \
+ (((x) & BIT_MASK_DTIM_PERIOD3_8822C) << BIT_SHIFT_DTIM_PERIOD3_8822C)
+#define BITS_DTIM_PERIOD3_8822C \
+ (BIT_MASK_DTIM_PERIOD3_8822C << BIT_SHIFT_DTIM_PERIOD3_8822C)
+#define BIT_CLEAR_DTIM_PERIOD3_8822C(x) ((x) & (~BITS_DTIM_PERIOD3_8822C))
+#define BIT_GET_DTIM_PERIOD3_8822C(x) \
+ (((x) >> BIT_SHIFT_DTIM_PERIOD3_8822C) & BIT_MASK_DTIM_PERIOD3_8822C)
+#define BIT_SET_DTIM_PERIOD3_8822C(x, v) \
+ (BIT_CLEAR_DTIM_PERIOD3_8822C(x) | BIT_DTIM_PERIOD3_8822C(v))
+
+#define BIT_DTIM3_8822C BIT(15)
+#define BIT_TIM3_8822C BIT(14)
+#define BIT_RPT_VALID_8822C BIT(13)
+
+#define BIT_SHIFT_PS_AID_3_8822C 0
+#define BIT_MASK_PS_AID_3_8822C 0x7ff
+#define BIT_PS_AID_3_8822C(x) \
+ (((x) & BIT_MASK_PS_AID_3_8822C) << BIT_SHIFT_PS_AID_3_8822C)
+#define BITS_PS_AID_3_8822C \
+ (BIT_MASK_PS_AID_3_8822C << BIT_SHIFT_PS_AID_3_8822C)
+#define BIT_CLEAR_PS_AID_3_8822C(x) ((x) & (~BITS_PS_AID_3_8822C))
+#define BIT_GET_PS_AID_3_8822C(x) \
+ (((x) >> BIT_SHIFT_PS_AID_3_8822C) & BIT_MASK_PS_AID_3_8822C)
+#define BIT_SET_PS_AID_3_8822C(x, v) \
+ (BIT_CLEAR_PS_AID_3_8822C(x) | BIT_PS_AID_3_8822C(v))
+
+/* 2 REG_BCN_PSR_RPT4_8822C (BEACON PARSER REPORT REGISTER4) */
+
+#define BIT_SHIFT_DTIM_CNT4_8822C 24
+#define BIT_MASK_DTIM_CNT4_8822C 0xff
+#define BIT_DTIM_CNT4_8822C(x) \
+ (((x) & BIT_MASK_DTIM_CNT4_8822C) << BIT_SHIFT_DTIM_CNT4_8822C)
+#define BITS_DTIM_CNT4_8822C \
+ (BIT_MASK_DTIM_CNT4_8822C << BIT_SHIFT_DTIM_CNT4_8822C)
+#define BIT_CLEAR_DTIM_CNT4_8822C(x) ((x) & (~BITS_DTIM_CNT4_8822C))
+#define BIT_GET_DTIM_CNT4_8822C(x) \
+ (((x) >> BIT_SHIFT_DTIM_CNT4_8822C) & BIT_MASK_DTIM_CNT4_8822C)
+#define BIT_SET_DTIM_CNT4_8822C(x, v) \
+ (BIT_CLEAR_DTIM_CNT4_8822C(x) | BIT_DTIM_CNT4_8822C(v))
+
+#define BIT_SHIFT_DTIM_PERIOD4_8822C 16
+#define BIT_MASK_DTIM_PERIOD4_8822C 0xff
+#define BIT_DTIM_PERIOD4_8822C(x) \
+ (((x) & BIT_MASK_DTIM_PERIOD4_8822C) << BIT_SHIFT_DTIM_PERIOD4_8822C)
+#define BITS_DTIM_PERIOD4_8822C \
+ (BIT_MASK_DTIM_PERIOD4_8822C << BIT_SHIFT_DTIM_PERIOD4_8822C)
+#define BIT_CLEAR_DTIM_PERIOD4_8822C(x) ((x) & (~BITS_DTIM_PERIOD4_8822C))
+#define BIT_GET_DTIM_PERIOD4_8822C(x) \
+ (((x) >> BIT_SHIFT_DTIM_PERIOD4_8822C) & BIT_MASK_DTIM_PERIOD4_8822C)
+#define BIT_SET_DTIM_PERIOD4_8822C(x, v) \
+ (BIT_CLEAR_DTIM_PERIOD4_8822C(x) | BIT_DTIM_PERIOD4_8822C(v))
+
+#define BIT_DTIM4_8822C BIT(15)
+#define BIT_TIM4_8822C BIT(14)
+#define BIT_RPT_VALID_8822C BIT(13)
+
+#define BIT_SHIFT_PS_AID_4_8822C 0
+#define BIT_MASK_PS_AID_4_8822C 0x7ff
+#define BIT_PS_AID_4_8822C(x) \
+ (((x) & BIT_MASK_PS_AID_4_8822C) << BIT_SHIFT_PS_AID_4_8822C)
+#define BITS_PS_AID_4_8822C \
+ (BIT_MASK_PS_AID_4_8822C << BIT_SHIFT_PS_AID_4_8822C)
+#define BIT_CLEAR_PS_AID_4_8822C(x) ((x) & (~BITS_PS_AID_4_8822C))
+#define BIT_GET_PS_AID_4_8822C(x) \
+ (((x) >> BIT_SHIFT_PS_AID_4_8822C) & BIT_MASK_PS_AID_4_8822C)
+#define BIT_SET_PS_AID_4_8822C(x, v) \
+ (BIT_CLEAR_PS_AID_4_8822C(x) | BIT_PS_AID_4_8822C(v))
+
+/* 2 REG_A1_ADDR_MASK_8822C (A1 ADDR MASK REGISTER) */
+
+#define BIT_SHIFT_A1_ADDR_MASK_8822C 0
+#define BIT_MASK_A1_ADDR_MASK_8822C 0xffffffffL
+#define BIT_A1_ADDR_MASK_8822C(x) \
+ (((x) & BIT_MASK_A1_ADDR_MASK_8822C) << BIT_SHIFT_A1_ADDR_MASK_8822C)
+#define BITS_A1_ADDR_MASK_8822C \
+ (BIT_MASK_A1_ADDR_MASK_8822C << BIT_SHIFT_A1_ADDR_MASK_8822C)
+#define BIT_CLEAR_A1_ADDR_MASK_8822C(x) ((x) & (~BITS_A1_ADDR_MASK_8822C))
+#define BIT_GET_A1_ADDR_MASK_8822C(x) \
+ (((x) >> BIT_SHIFT_A1_ADDR_MASK_8822C) & BIT_MASK_A1_ADDR_MASK_8822C)
+#define BIT_SET_A1_ADDR_MASK_8822C(x, v) \
+ (BIT_CLEAR_A1_ADDR_MASK_8822C(x) | BIT_A1_ADDR_MASK_8822C(v))
+
+/* 2 REG_RXPSF_CTRL_8822C */
+#define BIT_RXGCK_FIFOTHR_EN_8822C BIT(28)
+
+#define BIT_SHIFT_RXGCK_VHT_FIFOTHR_8822C 26
+#define BIT_MASK_RXGCK_VHT_FIFOTHR_8822C 0x3
+#define BIT_RXGCK_VHT_FIFOTHR_8822C(x) \
+ (((x) & BIT_MASK_RXGCK_VHT_FIFOTHR_8822C) \
+ << BIT_SHIFT_RXGCK_VHT_FIFOTHR_8822C)
+#define BITS_RXGCK_VHT_FIFOTHR_8822C \
+ (BIT_MASK_RXGCK_VHT_FIFOTHR_8822C << BIT_SHIFT_RXGCK_VHT_FIFOTHR_8822C)
+#define BIT_CLEAR_RXGCK_VHT_FIFOTHR_8822C(x) \
+ ((x) & (~BITS_RXGCK_VHT_FIFOTHR_8822C))
+#define BIT_GET_RXGCK_VHT_FIFOTHR_8822C(x) \
+ (((x) >> BIT_SHIFT_RXGCK_VHT_FIFOTHR_8822C) & \
+ BIT_MASK_RXGCK_VHT_FIFOTHR_8822C)
+#define BIT_SET_RXGCK_VHT_FIFOTHR_8822C(x, v) \
+ (BIT_CLEAR_RXGCK_VHT_FIFOTHR_8822C(x) | BIT_RXGCK_VHT_FIFOTHR_8822C(v))
+
+#define BIT_SHIFT_RXGCK_HT_FIFOTHR_8822C 24
+#define BIT_MASK_RXGCK_HT_FIFOTHR_8822C 0x3
+#define BIT_RXGCK_HT_FIFOTHR_8822C(x) \
+ (((x) & BIT_MASK_RXGCK_HT_FIFOTHR_8822C) \
+ << BIT_SHIFT_RXGCK_HT_FIFOTHR_8822C)
+#define BITS_RXGCK_HT_FIFOTHR_8822C \
+ (BIT_MASK_RXGCK_HT_FIFOTHR_8822C << BIT_SHIFT_RXGCK_HT_FIFOTHR_8822C)
+#define BIT_CLEAR_RXGCK_HT_FIFOTHR_8822C(x) \
+ ((x) & (~BITS_RXGCK_HT_FIFOTHR_8822C))
+#define BIT_GET_RXGCK_HT_FIFOTHR_8822C(x) \
+ (((x) >> BIT_SHIFT_RXGCK_HT_FIFOTHR_8822C) & \
+ BIT_MASK_RXGCK_HT_FIFOTHR_8822C)
+#define BIT_SET_RXGCK_HT_FIFOTHR_8822C(x, v) \
+ (BIT_CLEAR_RXGCK_HT_FIFOTHR_8822C(x) | BIT_RXGCK_HT_FIFOTHR_8822C(v))
+
+#define BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8822C 22
+#define BIT_MASK_RXGCK_OFDM_FIFOTHR_8822C 0x3
+#define BIT_RXGCK_OFDM_FIFOTHR_8822C(x) \
+ (((x) & BIT_MASK_RXGCK_OFDM_FIFOTHR_8822C) \
+ << BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8822C)
+#define BITS_RXGCK_OFDM_FIFOTHR_8822C \
+ (BIT_MASK_RXGCK_OFDM_FIFOTHR_8822C \
+ << BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8822C)
+#define BIT_CLEAR_RXGCK_OFDM_FIFOTHR_8822C(x) \
+ ((x) & (~BITS_RXGCK_OFDM_FIFOTHR_8822C))
+#define BIT_GET_RXGCK_OFDM_FIFOTHR_8822C(x) \
+ (((x) >> BIT_SHIFT_RXGCK_OFDM_FIFOTHR_8822C) & \
+ BIT_MASK_RXGCK_OFDM_FIFOTHR_8822C)
+#define BIT_SET_RXGCK_OFDM_FIFOTHR_8822C(x, v) \
+ (BIT_CLEAR_RXGCK_OFDM_FIFOTHR_8822C(x) | \
+ BIT_RXGCK_OFDM_FIFOTHR_8822C(v))
+
+#define BIT_SHIFT_RXGCK_CCK_FIFOTHR_8822C 20
+#define BIT_MASK_RXGCK_CCK_FIFOTHR_8822C 0x3
+#define BIT_RXGCK_CCK_FIFOTHR_8822C(x) \
+ (((x) & BIT_MASK_RXGCK_CCK_FIFOTHR_8822C) \
+ << BIT_SHIFT_RXGCK_CCK_FIFOTHR_8822C)
+#define BITS_RXGCK_CCK_FIFOTHR_8822C \
+ (BIT_MASK_RXGCK_CCK_FIFOTHR_8822C << BIT_SHIFT_RXGCK_CCK_FIFOTHR_8822C)
+#define BIT_CLEAR_RXGCK_CCK_FIFOTHR_8822C(x) \
+ ((x) & (~BITS_RXGCK_CCK_FIFOTHR_8822C))
+#define BIT_GET_RXGCK_CCK_FIFOTHR_8822C(x) \
+ (((x) >> BIT_SHIFT_RXGCK_CCK_FIFOTHR_8822C) & \
+ BIT_MASK_RXGCK_CCK_FIFOTHR_8822C)
+#define BIT_SET_RXGCK_CCK_FIFOTHR_8822C(x, v) \
+ (BIT_CLEAR_RXGCK_CCK_FIFOTHR_8822C(x) | BIT_RXGCK_CCK_FIFOTHR_8822C(v))
+
+#define BIT_SHIFT_RXGCK_ENTRY_DELAY_8822C 17
+#define BIT_MASK_RXGCK_ENTRY_DELAY_8822C 0x7
+#define BIT_RXGCK_ENTRY_DELAY_8822C(x) \
+ (((x) & BIT_MASK_RXGCK_ENTRY_DELAY_8822C) \
+ << BIT_SHIFT_RXGCK_ENTRY_DELAY_8822C)
+#define BITS_RXGCK_ENTRY_DELAY_8822C \
+ (BIT_MASK_RXGCK_ENTRY_DELAY_8822C << BIT_SHIFT_RXGCK_ENTRY_DELAY_8822C)
+#define BIT_CLEAR_RXGCK_ENTRY_DELAY_8822C(x) \
+ ((x) & (~BITS_RXGCK_ENTRY_DELAY_8822C))
+#define BIT_GET_RXGCK_ENTRY_DELAY_8822C(x) \
+ (((x) >> BIT_SHIFT_RXGCK_ENTRY_DELAY_8822C) & \
+ BIT_MASK_RXGCK_ENTRY_DELAY_8822C)
+#define BIT_SET_RXGCK_ENTRY_DELAY_8822C(x, v) \
+ (BIT_CLEAR_RXGCK_ENTRY_DELAY_8822C(x) | BIT_RXGCK_ENTRY_DELAY_8822C(v))
+
+#define BIT_RXGCK_OFDMCCA_EN_8822C BIT(16)
+
+#define BIT_SHIFT_RXPSF_PKTLENTHR_8822C 13
+#define BIT_MASK_RXPSF_PKTLENTHR_8822C 0x7
+#define BIT_RXPSF_PKTLENTHR_8822C(x) \
+ (((x) & BIT_MASK_RXPSF_PKTLENTHR_8822C) \
+ << BIT_SHIFT_RXPSF_PKTLENTHR_8822C)
+#define BITS_RXPSF_PKTLENTHR_8822C \
+ (BIT_MASK_RXPSF_PKTLENTHR_8822C << BIT_SHIFT_RXPSF_PKTLENTHR_8822C)
+#define BIT_CLEAR_RXPSF_PKTLENTHR_8822C(x) ((x) & (~BITS_RXPSF_PKTLENTHR_8822C))
+#define BIT_GET_RXPSF_PKTLENTHR_8822C(x) \
+ (((x) >> BIT_SHIFT_RXPSF_PKTLENTHR_8822C) & \
+ BIT_MASK_RXPSF_PKTLENTHR_8822C)
+#define BIT_SET_RXPSF_PKTLENTHR_8822C(x, v) \
+ (BIT_CLEAR_RXPSF_PKTLENTHR_8822C(x) | BIT_RXPSF_PKTLENTHR_8822C(v))
+
+#define BIT_RXPSF_CTRLEN_8822C BIT(12)
+#define BIT_RXPSF_VHTCHKEN_8822C BIT(11)
+#define BIT_RXPSF_HTCHKEN_8822C BIT(10)
+#define BIT_RXPSF_OFDMCHKEN_8822C BIT(9)
+#define BIT_RXPSF_CCKCHKEN_8822C BIT(8)
+#define BIT_RXPSF_OFDMRST_8822C BIT(7)
+#define BIT_RXPSF_CCKRST_8822C BIT(6)
+#define BIT_RXPSF_MHCHKEN_8822C BIT(5)
+#define BIT_RXPSF_CONT_ERRCHKEN_8822C BIT(4)
+#define BIT_RXPSF_ALL_ERRCHKEN_8822C BIT(3)
+
+#define BIT_SHIFT_RXPSF_ERRTHR_8822C 0
+#define BIT_MASK_RXPSF_ERRTHR_8822C 0x7
+#define BIT_RXPSF_ERRTHR_8822C(x) \
+ (((x) & BIT_MASK_RXPSF_ERRTHR_8822C) << BIT_SHIFT_RXPSF_ERRTHR_8822C)
+#define BITS_RXPSF_ERRTHR_8822C \
+ (BIT_MASK_RXPSF_ERRTHR_8822C << BIT_SHIFT_RXPSF_ERRTHR_8822C)
+#define BIT_CLEAR_RXPSF_ERRTHR_8822C(x) ((x) & (~BITS_RXPSF_ERRTHR_8822C))
+#define BIT_GET_RXPSF_ERRTHR_8822C(x) \
+ (((x) >> BIT_SHIFT_RXPSF_ERRTHR_8822C) & BIT_MASK_RXPSF_ERRTHR_8822C)
+#define BIT_SET_RXPSF_ERRTHR_8822C(x, v) \
+ (BIT_CLEAR_RXPSF_ERRTHR_8822C(x) | BIT_RXPSF_ERRTHR_8822C(v))
+
+/* 2 REG_RXPSF_TYPE_CTRL_8822C */
+#define BIT_RXPSF_DATA15EN_8822C BIT(31)
+#define BIT_RXPSF_DATA14EN_8822C BIT(30)
+#define BIT_RXPSF_DATA13EN_8822C BIT(29)
+#define BIT_RXPSF_DATA12EN_8822C BIT(28)
+#define BIT_RXPSF_DATA11EN_8822C BIT(27)
+#define BIT_RXPSF_DATA10EN_8822C BIT(26)
+#define BIT_RXPSF_DATA9EN_8822C BIT(25)
+#define BIT_RXPSF_DATA8EN_8822C BIT(24)
+#define BIT_RXPSF_DATA7EN_8822C BIT(23)
+#define BIT_RXPSF_DATA6EN_8822C BIT(22)
+#define BIT_RXPSF_DATA5EN_8822C BIT(21)
+#define BIT_RXPSF_DATA4EN_8822C BIT(20)
+#define BIT_RXPSF_DATA3EN_8822C BIT(19)
+#define BIT_RXPSF_DATA2EN_8822C BIT(18)
+#define BIT_RXPSF_DATA1EN_8822C BIT(17)
+#define BIT_RXPSF_DATA0EN_8822C BIT(16)
+#define BIT_RXPSF_MGT15EN_8822C BIT(15)
+#define BIT_RXPSF_MGT14EN_8822C BIT(14)
+#define BIT_RXPSF_MGT13EN_8822C BIT(13)
+#define BIT_RXPSF_MGT12EN_8822C BIT(12)
+#define BIT_RXPSF_MGT11EN_8822C BIT(11)
+#define BIT_RXPSF_MGT10EN_8822C BIT(10)
+#define BIT_RXPSF_MGT9EN_8822C BIT(9)
+#define BIT_RXPSF_MGT8EN_8822C BIT(8)
+#define BIT_RXPSF_MGT7EN_8822C BIT(7)
+#define BIT_RXPSF_MGT6EN_8822C BIT(6)
+#define BIT_RXPSF_MGT5EN_8822C BIT(5)
+#define BIT_RXPSF_MGT4EN_8822C BIT(4)
+#define BIT_RXPSF_MGT3EN_8822C BIT(3)
+#define BIT_RXPSF_MGT2EN_8822C BIT(2)
+#define BIT_RXPSF_MGT1EN_8822C BIT(1)
+#define BIT_RXPSF_MGT0EN_8822C BIT(0)
+
+/* 2 REG_CAM_ACCESS_CTRL_8822C */
+#define BIT_INDIRECT_ERR_8822C BIT(6)
+#define BIT_DIRECT_ERR_8822C BIT(5)
+#define BIT_DIR_ACCESS_EN_RX_BA_8822C BIT(4)
+#define BIT_DIR_ACCESS_EN_MBSSIDCAM_8822C BIT(3)
+#define BIT_DIR_ACCESS_EN_KEY_8822C BIT(2)
+#define BIT_DIR_ACCESS_EN_WOWLAN_8822C BIT(1)
+#define BIT_DIR_ACCESS_EN_FW_FILTER_8822C BIT(0)
+
+/* 2 REG_HT_SND_REF_RATE_8822C */
+
+#define BIT_SHIFT_WMAC_HT_CSI_RATE_8822C 0
+#define BIT_MASK_WMAC_HT_CSI_RATE_8822C 0x3f
+#define BIT_WMAC_HT_CSI_RATE_8822C(x) \
+ (((x) & BIT_MASK_WMAC_HT_CSI_RATE_8822C) \
+ << BIT_SHIFT_WMAC_HT_CSI_RATE_8822C)
+#define BITS_WMAC_HT_CSI_RATE_8822C \
+ (BIT_MASK_WMAC_HT_CSI_RATE_8822C << BIT_SHIFT_WMAC_HT_CSI_RATE_8822C)
+#define BIT_CLEAR_WMAC_HT_CSI_RATE_8822C(x) \
+ ((x) & (~BITS_WMAC_HT_CSI_RATE_8822C))
+#define BIT_GET_WMAC_HT_CSI_RATE_8822C(x) \
+ (((x) >> BIT_SHIFT_WMAC_HT_CSI_RATE_8822C) & \
+ BIT_MASK_WMAC_HT_CSI_RATE_8822C)
+#define BIT_SET_WMAC_HT_CSI_RATE_8822C(x, v) \
+ (BIT_CLEAR_WMAC_HT_CSI_RATE_8822C(x) | BIT_WMAC_HT_CSI_RATE_8822C(v))
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_MACID2_8822C (MAC ID2 REGISTER) */
+
+#define BIT_SHIFT_MACID2_V1_8822C 0
+#define BIT_MASK_MACID2_V1_8822C 0xffffffffL
+#define BIT_MACID2_V1_8822C(x) \
+ (((x) & BIT_MASK_MACID2_V1_8822C) << BIT_SHIFT_MACID2_V1_8822C)
+#define BITS_MACID2_V1_8822C \
+ (BIT_MASK_MACID2_V1_8822C << BIT_SHIFT_MACID2_V1_8822C)
+#define BIT_CLEAR_MACID2_V1_8822C(x) ((x) & (~BITS_MACID2_V1_8822C))
+#define BIT_GET_MACID2_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_MACID2_V1_8822C) & BIT_MASK_MACID2_V1_8822C)
+#define BIT_SET_MACID2_V1_8822C(x, v) \
+ (BIT_CLEAR_MACID2_V1_8822C(x) | BIT_MACID2_V1_8822C(v))
+
+/* 2 REG_MACID2_H_8822C (MAC ID2 REGISTER) */
+
+#define BIT_SHIFT_MACID2_H_V1_8822C 0
+#define BIT_MASK_MACID2_H_V1_8822C 0xffff
+#define BIT_MACID2_H_V1_8822C(x) \
+ (((x) & BIT_MASK_MACID2_H_V1_8822C) << BIT_SHIFT_MACID2_H_V1_8822C)
+#define BITS_MACID2_H_V1_8822C \
+ (BIT_MASK_MACID2_H_V1_8822C << BIT_SHIFT_MACID2_H_V1_8822C)
+#define BIT_CLEAR_MACID2_H_V1_8822C(x) ((x) & (~BITS_MACID2_H_V1_8822C))
+#define BIT_GET_MACID2_H_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_MACID2_H_V1_8822C) & BIT_MASK_MACID2_H_V1_8822C)
+#define BIT_SET_MACID2_H_V1_8822C(x, v) \
+ (BIT_CLEAR_MACID2_H_V1_8822C(x) | BIT_MACID2_H_V1_8822C(v))
+
+/* 2 REG_BSSID2_8822C (BSSID2 REGISTER) */
+
+#define BIT_SHIFT_BSSID2_V1_8822C 0
+#define BIT_MASK_BSSID2_V1_8822C 0xffffffffL
+#define BIT_BSSID2_V1_8822C(x) \
+ (((x) & BIT_MASK_BSSID2_V1_8822C) << BIT_SHIFT_BSSID2_V1_8822C)
+#define BITS_BSSID2_V1_8822C \
+ (BIT_MASK_BSSID2_V1_8822C << BIT_SHIFT_BSSID2_V1_8822C)
+#define BIT_CLEAR_BSSID2_V1_8822C(x) ((x) & (~BITS_BSSID2_V1_8822C))
+#define BIT_GET_BSSID2_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_BSSID2_V1_8822C) & BIT_MASK_BSSID2_V1_8822C)
+#define BIT_SET_BSSID2_V1_8822C(x, v) \
+ (BIT_CLEAR_BSSID2_V1_8822C(x) | BIT_BSSID2_V1_8822C(v))
+
+/* 2 REG_BSSID2_H_8822C (BSSID2 REGISTER) */
+
+#define BIT_SHIFT_BSSID2_H_V1_8822C 0
+#define BIT_MASK_BSSID2_H_V1_8822C 0xffff
+#define BIT_BSSID2_H_V1_8822C(x) \
+ (((x) & BIT_MASK_BSSID2_H_V1_8822C) << BIT_SHIFT_BSSID2_H_V1_8822C)
+#define BITS_BSSID2_H_V1_8822C \
+ (BIT_MASK_BSSID2_H_V1_8822C << BIT_SHIFT_BSSID2_H_V1_8822C)
+#define BIT_CLEAR_BSSID2_H_V1_8822C(x) ((x) & (~BITS_BSSID2_H_V1_8822C))
+#define BIT_GET_BSSID2_H_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_BSSID2_H_V1_8822C) & BIT_MASK_BSSID2_H_V1_8822C)
+#define BIT_SET_BSSID2_H_V1_8822C(x, v) \
+ (BIT_CLEAR_BSSID2_H_V1_8822C(x) | BIT_BSSID2_H_V1_8822C(v))
+
+/* 2 REG_MACID3_8822C (MAC ID3 REGISTER) */
+
+#define BIT_SHIFT_MACID3_V1_8822C 0
+#define BIT_MASK_MACID3_V1_8822C 0xffffffffL
+#define BIT_MACID3_V1_8822C(x) \
+ (((x) & BIT_MASK_MACID3_V1_8822C) << BIT_SHIFT_MACID3_V1_8822C)
+#define BITS_MACID3_V1_8822C \
+ (BIT_MASK_MACID3_V1_8822C << BIT_SHIFT_MACID3_V1_8822C)
+#define BIT_CLEAR_MACID3_V1_8822C(x) ((x) & (~BITS_MACID3_V1_8822C))
+#define BIT_GET_MACID3_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_MACID3_V1_8822C) & BIT_MASK_MACID3_V1_8822C)
+#define BIT_SET_MACID3_V1_8822C(x, v) \
+ (BIT_CLEAR_MACID3_V1_8822C(x) | BIT_MACID3_V1_8822C(v))
+
+/* 2 REG_MACID3_H_8822C (MAC ID3 REGISTER) */
+
+#define BIT_SHIFT_MACID3_H_V1_8822C 0
+#define BIT_MASK_MACID3_H_V1_8822C 0xffff
+#define BIT_MACID3_H_V1_8822C(x) \
+ (((x) & BIT_MASK_MACID3_H_V1_8822C) << BIT_SHIFT_MACID3_H_V1_8822C)
+#define BITS_MACID3_H_V1_8822C \
+ (BIT_MASK_MACID3_H_V1_8822C << BIT_SHIFT_MACID3_H_V1_8822C)
+#define BIT_CLEAR_MACID3_H_V1_8822C(x) ((x) & (~BITS_MACID3_H_V1_8822C))
+#define BIT_GET_MACID3_H_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_MACID3_H_V1_8822C) & BIT_MASK_MACID3_H_V1_8822C)
+#define BIT_SET_MACID3_H_V1_8822C(x, v) \
+ (BIT_CLEAR_MACID3_H_V1_8822C(x) | BIT_MACID3_H_V1_8822C(v))
+
+/* 2 REG_BSSID3_8822C (BSSID3 REGISTER) */
+
+#define BIT_SHIFT_BSSID3_V1_8822C 0
+#define BIT_MASK_BSSID3_V1_8822C 0xffffffffL
+#define BIT_BSSID3_V1_8822C(x) \
+ (((x) & BIT_MASK_BSSID3_V1_8822C) << BIT_SHIFT_BSSID3_V1_8822C)
+#define BITS_BSSID3_V1_8822C \
+ (BIT_MASK_BSSID3_V1_8822C << BIT_SHIFT_BSSID3_V1_8822C)
+#define BIT_CLEAR_BSSID3_V1_8822C(x) ((x) & (~BITS_BSSID3_V1_8822C))
+#define BIT_GET_BSSID3_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_BSSID3_V1_8822C) & BIT_MASK_BSSID3_V1_8822C)
+#define BIT_SET_BSSID3_V1_8822C(x, v) \
+ (BIT_CLEAR_BSSID3_V1_8822C(x) | BIT_BSSID3_V1_8822C(v))
+
+/* 2 REG_BSSID3_H_8822C (BSSID3 REGISTER) */
+
+#define BIT_SHIFT_BSSID3_H_V1_8822C 0
+#define BIT_MASK_BSSID3_H_V1_8822C 0xffff
+#define BIT_BSSID3_H_V1_8822C(x) \
+ (((x) & BIT_MASK_BSSID3_H_V1_8822C) << BIT_SHIFT_BSSID3_H_V1_8822C)
+#define BITS_BSSID3_H_V1_8822C \
+ (BIT_MASK_BSSID3_H_V1_8822C << BIT_SHIFT_BSSID3_H_V1_8822C)
+#define BIT_CLEAR_BSSID3_H_V1_8822C(x) ((x) & (~BITS_BSSID3_H_V1_8822C))
+#define BIT_GET_BSSID3_H_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_BSSID3_H_V1_8822C) & BIT_MASK_BSSID3_H_V1_8822C)
+#define BIT_SET_BSSID3_H_V1_8822C(x, v) \
+ (BIT_CLEAR_BSSID3_H_V1_8822C(x) | BIT_BSSID3_H_V1_8822C(v))
+
+/* 2 REG_MACID4_8822C (MAC ID4 REGISTER) */
+
+#define BIT_SHIFT_MACID4_V1_8822C 0
+#define BIT_MASK_MACID4_V1_8822C 0xffffffffL
+#define BIT_MACID4_V1_8822C(x) \
+ (((x) & BIT_MASK_MACID4_V1_8822C) << BIT_SHIFT_MACID4_V1_8822C)
+#define BITS_MACID4_V1_8822C \
+ (BIT_MASK_MACID4_V1_8822C << BIT_SHIFT_MACID4_V1_8822C)
+#define BIT_CLEAR_MACID4_V1_8822C(x) ((x) & (~BITS_MACID4_V1_8822C))
+#define BIT_GET_MACID4_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_MACID4_V1_8822C) & BIT_MASK_MACID4_V1_8822C)
+#define BIT_SET_MACID4_V1_8822C(x, v) \
+ (BIT_CLEAR_MACID4_V1_8822C(x) | BIT_MACID4_V1_8822C(v))
+
+/* 2 REG_MACID4_H_8822C (MAC ID4 REGISTER) */
+
+#define BIT_SHIFT_MACID4_H_V1_8822C 0
+#define BIT_MASK_MACID4_H_V1_8822C 0xffff
+#define BIT_MACID4_H_V1_8822C(x) \
+ (((x) & BIT_MASK_MACID4_H_V1_8822C) << BIT_SHIFT_MACID4_H_V1_8822C)
+#define BITS_MACID4_H_V1_8822C \
+ (BIT_MASK_MACID4_H_V1_8822C << BIT_SHIFT_MACID4_H_V1_8822C)
+#define BIT_CLEAR_MACID4_H_V1_8822C(x) ((x) & (~BITS_MACID4_H_V1_8822C))
+#define BIT_GET_MACID4_H_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_MACID4_H_V1_8822C) & BIT_MASK_MACID4_H_V1_8822C)
+#define BIT_SET_MACID4_H_V1_8822C(x, v) \
+ (BIT_CLEAR_MACID4_H_V1_8822C(x) | BIT_MACID4_H_V1_8822C(v))
+
+/* 2 REG_BSSID4_8822C (BSSID4 REGISTER) */
+
+#define BIT_SHIFT_BSSID4_V1_8822C 0
+#define BIT_MASK_BSSID4_V1_8822C 0xffffffffL
+#define BIT_BSSID4_V1_8822C(x) \
+ (((x) & BIT_MASK_BSSID4_V1_8822C) << BIT_SHIFT_BSSID4_V1_8822C)
+#define BITS_BSSID4_V1_8822C \
+ (BIT_MASK_BSSID4_V1_8822C << BIT_SHIFT_BSSID4_V1_8822C)
+#define BIT_CLEAR_BSSID4_V1_8822C(x) ((x) & (~BITS_BSSID4_V1_8822C))
+#define BIT_GET_BSSID4_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_BSSID4_V1_8822C) & BIT_MASK_BSSID4_V1_8822C)
+#define BIT_SET_BSSID4_V1_8822C(x, v) \
+ (BIT_CLEAR_BSSID4_V1_8822C(x) | BIT_BSSID4_V1_8822C(v))
+
+/* 2 REG_BSSID4_H_8822C (BSSID4 REGISTER) */
+
+#define BIT_SHIFT_BSSID4_H_V1_8822C 0
+#define BIT_MASK_BSSID4_H_V1_8822C 0xffff
+#define BIT_BSSID4_H_V1_8822C(x) \
+ (((x) & BIT_MASK_BSSID4_H_V1_8822C) << BIT_SHIFT_BSSID4_H_V1_8822C)
+#define BITS_BSSID4_H_V1_8822C \
+ (BIT_MASK_BSSID4_H_V1_8822C << BIT_SHIFT_BSSID4_H_V1_8822C)
+#define BIT_CLEAR_BSSID4_H_V1_8822C(x) ((x) & (~BITS_BSSID4_H_V1_8822C))
+#define BIT_GET_BSSID4_H_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_BSSID4_H_V1_8822C) & BIT_MASK_BSSID4_H_V1_8822C)
+#define BIT_SET_BSSID4_H_V1_8822C(x, v) \
+ (BIT_CLEAR_BSSID4_H_V1_8822C(x) | BIT_BSSID4_H_V1_8822C(v))
+
+/* 2 REG_NOA_REPORT_8822C */
+
+/* 2 REG_NOA_REPORT_1_8822C */
+
+/* 2 REG_NOA_REPORT_2_8822C */
+
+/* 2 REG_NOA_REPORT_3_8822C */
+
+/* 2 REG_PWRBIT_SETTING_8822C */
+#define BIT_CLI3_WMAC_TCRPWRMGT_HWCTL_EN_8822C BIT(15)
+#define BIT_CLI3_WMAC_TCRPWRMGT_HWDATA_EN_8822C BIT(14)
+#define BIT_CLI3_WMAC_TCRPWRMGT_HWACT_EN_8822C BIT(13)
+#define BIT_CLI3_PWR_ST_V1_8822C BIT(12)
+#define BIT_CLI2_WMAC_TCRPWRMGT_HWCTL_EN_8822C BIT(11)
+#define BIT_CLI2_WMAC_TCRPWRMGT_HWDATA_EN_8822C BIT(10)
+#define BIT_CLI2_WMAC_TCRPWRMGT_HWACT_EN_8822C BIT(9)
+#define BIT_CLI2_PWR_ST_V1_8822C BIT(8)
+#define BIT_CLI1_WMAC_TCRPWRMGT_HWCTL_EN_8822C BIT(7)
+#define BIT_CLI1_WMAC_TCRPWRMGT_HWDATA_EN_8822C BIT(6)
+#define BIT_CLI1_WMAC_TCRPWRMGT_HWACT_EN_8822C BIT(5)
+#define BIT_CLI1_PWR_ST_V1_8822C BIT(4)
+#define BIT_CLI0_WMAC_TCRPWRMGT_HWCTL_EN_8822C BIT(3)
+#define BIT_CLI0_WMAC_TCRPWRMGT_HWDATA_EN_8822C BIT(2)
+#define BIT_CLI0_WMAC_TCRPWRMGT_HWACT_EN_8822C BIT(1)
+#define BIT_CLI0_PWR_ST_V1_8822C BIT(0)
+
+/* 2 REG_GENERAL_OPTION_8822C */
+#define BIT_WMAC_EXT_DBG_SEL_V1_8822C BIT(6)
+#define BIT_WMAC_FIX_FIRST_MPDU_WITH_PHYSTS_8822C BIT(5)
+#define BIT_RX_DMA_BYPASS_CHECK_DATABYPASS_CHECK_DATA_8822C BIT(4)
+#define BIT_RX_DMA_BYPASS_CHECK_MGTBIT_RX_DMA_BYPASS_CHECK_MGT_8822C BIT(3)
+#define BIT_TXSERV_FIELD_SEL_8822C BIT(2)
+#define BIT_RXVHT_LEN_SEL_8822C BIT(1)
+#define BIT_RXMIC_PROTECT_EN_8822C BIT(0)
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_CSI_RRSR_8822C */
+#define BIT_CSI_LDPC_EN_8822C BIT(29)
+#define BIT_CSI_STBC_EN_8822C BIT(28)
+
+#define BIT_SHIFT_CSI_RRSC_BITMAP_8822C 4
+#define BIT_MASK_CSI_RRSC_BITMAP_8822C 0xffffff
+#define BIT_CSI_RRSC_BITMAP_8822C(x) \
+ (((x) & BIT_MASK_CSI_RRSC_BITMAP_8822C) \
+ << BIT_SHIFT_CSI_RRSC_BITMAP_8822C)
+#define BITS_CSI_RRSC_BITMAP_8822C \
+ (BIT_MASK_CSI_RRSC_BITMAP_8822C << BIT_SHIFT_CSI_RRSC_BITMAP_8822C)
+#define BIT_CLEAR_CSI_RRSC_BITMAP_8822C(x) ((x) & (~BITS_CSI_RRSC_BITMAP_8822C))
+#define BIT_GET_CSI_RRSC_BITMAP_8822C(x) \
+ (((x) >> BIT_SHIFT_CSI_RRSC_BITMAP_8822C) & \
+ BIT_MASK_CSI_RRSC_BITMAP_8822C)
+#define BIT_SET_CSI_RRSC_BITMAP_8822C(x, v) \
+ (BIT_CLEAR_CSI_RRSC_BITMAP_8822C(x) | BIT_CSI_RRSC_BITMAP_8822C(v))
+
+#define BIT_SHIFT_OFDM_LEN_TH_8822C 0
+#define BIT_MASK_OFDM_LEN_TH_8822C 0xf
+#define BIT_OFDM_LEN_TH_8822C(x) \
+ (((x) & BIT_MASK_OFDM_LEN_TH_8822C) << BIT_SHIFT_OFDM_LEN_TH_8822C)
+#define BITS_OFDM_LEN_TH_8822C \
+ (BIT_MASK_OFDM_LEN_TH_8822C << BIT_SHIFT_OFDM_LEN_TH_8822C)
+#define BIT_CLEAR_OFDM_LEN_TH_8822C(x) ((x) & (~BITS_OFDM_LEN_TH_8822C))
+#define BIT_GET_OFDM_LEN_TH_8822C(x) \
+ (((x) >> BIT_SHIFT_OFDM_LEN_TH_8822C) & BIT_MASK_OFDM_LEN_TH_8822C)
+#define BIT_SET_OFDM_LEN_TH_8822C(x, v) \
+ (BIT_CLEAR_OFDM_LEN_TH_8822C(x) | BIT_OFDM_LEN_TH_8822C(v))
+
+/* 2 REG_MU_BF_OPTION_8822C */
+#define BIT_WMAC_RESP_NONSTA1_DIS_8822C BIT(7)
+#define BIT_WMAC_TXMU_ACKPOLICY_EN_8822C BIT(6)
+
+#define BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822C 4
+#define BIT_MASK_WMAC_TXMU_ACKPOLICY_8822C 0x3
+#define BIT_WMAC_TXMU_ACKPOLICY_8822C(x) \
+ (((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8822C) \
+ << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822C)
+#define BITS_WMAC_TXMU_ACKPOLICY_8822C \
+ (BIT_MASK_WMAC_TXMU_ACKPOLICY_8822C \
+ << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822C)
+#define BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8822C(x) \
+ ((x) & (~BITS_WMAC_TXMU_ACKPOLICY_8822C))
+#define BIT_GET_WMAC_TXMU_ACKPOLICY_8822C(x) \
+ (((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8822C) & \
+ BIT_MASK_WMAC_TXMU_ACKPOLICY_8822C)
+#define BIT_SET_WMAC_TXMU_ACKPOLICY_8822C(x, v) \
+ (BIT_CLEAR_WMAC_TXMU_ACKPOLICY_8822C(x) | \
+ BIT_WMAC_TXMU_ACKPOLICY_8822C(v))
+
+#define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822C 1
+#define BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822C 0x7
+#define BIT_WMAC_MU_BFEE_PORT_SEL_8822C(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822C) \
+ << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822C)
+#define BITS_WMAC_MU_BFEE_PORT_SEL_8822C \
+ (BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822C \
+ << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822C)
+#define BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8822C(x) \
+ ((x) & (~BITS_WMAC_MU_BFEE_PORT_SEL_8822C))
+#define BIT_GET_WMAC_MU_BFEE_PORT_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8822C) & \
+ BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8822C)
+#define BIT_SET_WMAC_MU_BFEE_PORT_SEL_8822C(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL_8822C(x) | \
+ BIT_WMAC_MU_BFEE_PORT_SEL_8822C(v))
+
+#define BIT_WMAC_MU_BFEE_DIS_8822C BIT(0)
+
+/* 2 REG_WMAC_PAUSE_BB_CLR_TH_8822C */
+
+#define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822C 0
+#define BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822C 0xff
+#define BIT_WMAC_PAUSE_BB_CLR_TH_8822C(x) \
+ (((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822C) \
+ << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822C)
+#define BITS_WMAC_PAUSE_BB_CLR_TH_8822C \
+ (BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822C \
+ << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822C)
+#define BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8822C(x) \
+ ((x) & (~BITS_WMAC_PAUSE_BB_CLR_TH_8822C))
+#define BIT_GET_WMAC_PAUSE_BB_CLR_TH_8822C(x) \
+ (((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8822C) & \
+ BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8822C)
+#define BIT_SET_WMAC_PAUSE_BB_CLR_TH_8822C(x, v) \
+ (BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH_8822C(x) | \
+ BIT_WMAC_PAUSE_BB_CLR_TH_8822C(v))
+
+/* 2 REG__WMAC_MULBK_BUF_8822C */
+
+#define BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8822C 0
+#define BIT_MASK_WMAC_MULBK_PAGE_SIZE_8822C 0xff
+#define BIT_WMAC_MULBK_PAGE_SIZE_8822C(x) \
+ (((x) & BIT_MASK_WMAC_MULBK_PAGE_SIZE_8822C) \
+ << BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8822C)
+#define BITS_WMAC_MULBK_PAGE_SIZE_8822C \
+ (BIT_MASK_WMAC_MULBK_PAGE_SIZE_8822C \
+ << BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8822C)
+#define BIT_CLEAR_WMAC_MULBK_PAGE_SIZE_8822C(x) \
+ ((x) & (~BITS_WMAC_MULBK_PAGE_SIZE_8822C))
+#define BIT_GET_WMAC_MULBK_PAGE_SIZE_8822C(x) \
+ (((x) >> BIT_SHIFT_WMAC_MULBK_PAGE_SIZE_8822C) & \
+ BIT_MASK_WMAC_MULBK_PAGE_SIZE_8822C)
+#define BIT_SET_WMAC_MULBK_PAGE_SIZE_8822C(x, v) \
+ (BIT_CLEAR_WMAC_MULBK_PAGE_SIZE_8822C(x) | \
+ BIT_WMAC_MULBK_PAGE_SIZE_8822C(v))
+
+/* 2 REG_WMAC_MU_OPTION_8822C */
+
+/* 2 REG_WMAC_MU_BF_CTL_8822C */
+#define BIT_WMAC_INVLD_BFPRT_CHK_8822C BIT(15)
+#define BIT_WMAC_RETXBFRPTSEQ_UPD_8822C BIT(14)
+
+#define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822C 12
+#define BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822C 0x3
+#define BIT_WMAC_MU_BFRPTSEG_SEL_8822C(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822C) \
+ << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822C)
+#define BITS_WMAC_MU_BFRPTSEG_SEL_8822C \
+ (BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822C \
+ << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822C)
+#define BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8822C(x) \
+ ((x) & (~BITS_WMAC_MU_BFRPTSEG_SEL_8822C))
+#define BIT_GET_WMAC_MU_BFRPTSEG_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8822C) & \
+ BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8822C)
+#define BIT_SET_WMAC_MU_BFRPTSEG_SEL_8822C(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL_8822C(x) | \
+ BIT_WMAC_MU_BFRPTSEG_SEL_8822C(v))
+
+#define BIT_SHIFT_WMAC_MU_BF_MYAID_8822C 0
+#define BIT_MASK_WMAC_MU_BF_MYAID_8822C 0xfff
+#define BIT_WMAC_MU_BF_MYAID_8822C(x) \
+ (((x) & BIT_MASK_WMAC_MU_BF_MYAID_8822C) \
+ << BIT_SHIFT_WMAC_MU_BF_MYAID_8822C)
+#define BITS_WMAC_MU_BF_MYAID_8822C \
+ (BIT_MASK_WMAC_MU_BF_MYAID_8822C << BIT_SHIFT_WMAC_MU_BF_MYAID_8822C)
+#define BIT_CLEAR_WMAC_MU_BF_MYAID_8822C(x) \
+ ((x) & (~BITS_WMAC_MU_BF_MYAID_8822C))
+#define BIT_GET_WMAC_MU_BF_MYAID_8822C(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID_8822C) & \
+ BIT_MASK_WMAC_MU_BF_MYAID_8822C)
+#define BIT_SET_WMAC_MU_BF_MYAID_8822C(x, v) \
+ (BIT_CLEAR_WMAC_MU_BF_MYAID_8822C(x) | BIT_WMAC_MU_BF_MYAID_8822C(v))
+
+/* 2 REG_WMAC_MU_BFRPT_PARA_8822C */
+
+#define BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8822C 13
+#define BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8822C 0x7
+#define BIT_BFRPT_PARA_USERID_SEL_V1_8822C(x) \
+ (((x) & BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8822C) \
+ << BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8822C)
+#define BITS_BFRPT_PARA_USERID_SEL_V1_8822C \
+ (BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8822C \
+ << BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8822C)
+#define BIT_CLEAR_BFRPT_PARA_USERID_SEL_V1_8822C(x) \
+ ((x) & (~BITS_BFRPT_PARA_USERID_SEL_V1_8822C))
+#define BIT_GET_BFRPT_PARA_USERID_SEL_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1_8822C) & \
+ BIT_MASK_BFRPT_PARA_USERID_SEL_V1_8822C)
+#define BIT_SET_BFRPT_PARA_USERID_SEL_V1_8822C(x, v) \
+ (BIT_CLEAR_BFRPT_PARA_USERID_SEL_V1_8822C(x) | \
+ BIT_BFRPT_PARA_USERID_SEL_V1_8822C(v))
+
+#define BIT_SHIFT_BFRPT_PARA_V1_8822C 0
+#define BIT_MASK_BFRPT_PARA_V1_8822C 0x1fff
+#define BIT_BFRPT_PARA_V1_8822C(x) \
+ (((x) & BIT_MASK_BFRPT_PARA_V1_8822C) << BIT_SHIFT_BFRPT_PARA_V1_8822C)
+#define BITS_BFRPT_PARA_V1_8822C \
+ (BIT_MASK_BFRPT_PARA_V1_8822C << BIT_SHIFT_BFRPT_PARA_V1_8822C)
+#define BIT_CLEAR_BFRPT_PARA_V1_8822C(x) ((x) & (~BITS_BFRPT_PARA_V1_8822C))
+#define BIT_GET_BFRPT_PARA_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_BFRPT_PARA_V1_8822C) & BIT_MASK_BFRPT_PARA_V1_8822C)
+#define BIT_SET_BFRPT_PARA_V1_8822C(x, v) \
+ (BIT_CLEAR_BFRPT_PARA_V1_8822C(x) | BIT_BFRPT_PARA_V1_8822C(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2_8822C */
+#define BIT_STATUS_BFEE2_8822C BIT(10)
+#define BIT_WMAC_MU_BFEE2_EN_8822C BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE2_AID_8822C 0
+#define BIT_MASK_WMAC_MU_BFEE2_AID_8822C 0x1ff
+#define BIT_WMAC_MU_BFEE2_AID_8822C(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE2_AID_8822C) \
+ << BIT_SHIFT_WMAC_MU_BFEE2_AID_8822C)
+#define BITS_WMAC_MU_BFEE2_AID_8822C \
+ (BIT_MASK_WMAC_MU_BFEE2_AID_8822C << BIT_SHIFT_WMAC_MU_BFEE2_AID_8822C)
+#define BIT_CLEAR_WMAC_MU_BFEE2_AID_8822C(x) \
+ ((x) & (~BITS_WMAC_MU_BFEE2_AID_8822C))
+#define BIT_GET_WMAC_MU_BFEE2_AID_8822C(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID_8822C) & \
+ BIT_MASK_WMAC_MU_BFEE2_AID_8822C)
+#define BIT_SET_WMAC_MU_BFEE2_AID_8822C(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE2_AID_8822C(x) | BIT_WMAC_MU_BFEE2_AID_8822C(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3_8822C */
+#define BIT_STATUS_BFEE3_8822C BIT(10)
+#define BIT_WMAC_MU_BFEE3_EN_8822C BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE3_AID_8822C 0
+#define BIT_MASK_WMAC_MU_BFEE3_AID_8822C 0x1ff
+#define BIT_WMAC_MU_BFEE3_AID_8822C(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE3_AID_8822C) \
+ << BIT_SHIFT_WMAC_MU_BFEE3_AID_8822C)
+#define BITS_WMAC_MU_BFEE3_AID_8822C \
+ (BIT_MASK_WMAC_MU_BFEE3_AID_8822C << BIT_SHIFT_WMAC_MU_BFEE3_AID_8822C)
+#define BIT_CLEAR_WMAC_MU_BFEE3_AID_8822C(x) \
+ ((x) & (~BITS_WMAC_MU_BFEE3_AID_8822C))
+#define BIT_GET_WMAC_MU_BFEE3_AID_8822C(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID_8822C) & \
+ BIT_MASK_WMAC_MU_BFEE3_AID_8822C)
+#define BIT_SET_WMAC_MU_BFEE3_AID_8822C(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE3_AID_8822C(x) | BIT_WMAC_MU_BFEE3_AID_8822C(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4_8822C */
+#define BIT_STATUS_BFEE4_8822C BIT(10)
+#define BIT_WMAC_MU_BFEE4_EN_8822C BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE4_AID_8822C 0
+#define BIT_MASK_WMAC_MU_BFEE4_AID_8822C 0x1ff
+#define BIT_WMAC_MU_BFEE4_AID_8822C(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE4_AID_8822C) \
+ << BIT_SHIFT_WMAC_MU_BFEE4_AID_8822C)
+#define BITS_WMAC_MU_BFEE4_AID_8822C \
+ (BIT_MASK_WMAC_MU_BFEE4_AID_8822C << BIT_SHIFT_WMAC_MU_BFEE4_AID_8822C)
+#define BIT_CLEAR_WMAC_MU_BFEE4_AID_8822C(x) \
+ ((x) & (~BITS_WMAC_MU_BFEE4_AID_8822C))
+#define BIT_GET_WMAC_MU_BFEE4_AID_8822C(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID_8822C) & \
+ BIT_MASK_WMAC_MU_BFEE4_AID_8822C)
+#define BIT_SET_WMAC_MU_BFEE4_AID_8822C(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE4_AID_8822C(x) | BIT_WMAC_MU_BFEE4_AID_8822C(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5_8822C */
+#define BIT_BIT_STATUS_BFEE5_8822C BIT(10)
+#define BIT_WMAC_MU_BFEE5_EN_8822C BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE5_AID_8822C 0
+#define BIT_MASK_WMAC_MU_BFEE5_AID_8822C 0x1ff
+#define BIT_WMAC_MU_BFEE5_AID_8822C(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE5_AID_8822C) \
+ << BIT_SHIFT_WMAC_MU_BFEE5_AID_8822C)
+#define BITS_WMAC_MU_BFEE5_AID_8822C \
+ (BIT_MASK_WMAC_MU_BFEE5_AID_8822C << BIT_SHIFT_WMAC_MU_BFEE5_AID_8822C)
+#define BIT_CLEAR_WMAC_MU_BFEE5_AID_8822C(x) \
+ ((x) & (~BITS_WMAC_MU_BFEE5_AID_8822C))
+#define BIT_GET_WMAC_MU_BFEE5_AID_8822C(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID_8822C) & \
+ BIT_MASK_WMAC_MU_BFEE5_AID_8822C)
+#define BIT_SET_WMAC_MU_BFEE5_AID_8822C(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE5_AID_8822C(x) | BIT_WMAC_MU_BFEE5_AID_8822C(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6_8822C */
+#define BIT_STATUS_BFEE6_8822C BIT(10)
+#define BIT_WMAC_MU_BFEE6_EN_8822C BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE6_AID_8822C 0
+#define BIT_MASK_WMAC_MU_BFEE6_AID_8822C 0x1ff
+#define BIT_WMAC_MU_BFEE6_AID_8822C(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE6_AID_8822C) \
+ << BIT_SHIFT_WMAC_MU_BFEE6_AID_8822C)
+#define BITS_WMAC_MU_BFEE6_AID_8822C \
+ (BIT_MASK_WMAC_MU_BFEE6_AID_8822C << BIT_SHIFT_WMAC_MU_BFEE6_AID_8822C)
+#define BIT_CLEAR_WMAC_MU_BFEE6_AID_8822C(x) \
+ ((x) & (~BITS_WMAC_MU_BFEE6_AID_8822C))
+#define BIT_GET_WMAC_MU_BFEE6_AID_8822C(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID_8822C) & \
+ BIT_MASK_WMAC_MU_BFEE6_AID_8822C)
+#define BIT_SET_WMAC_MU_BFEE6_AID_8822C(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE6_AID_8822C(x) | BIT_WMAC_MU_BFEE6_AID_8822C(v))
+
+/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7_8822C */
+#define BIT_STATUS_BFEE7_8822C BIT(10)
+#define BIT_WMAC_MU_BFEE7_EN_8822C BIT(9)
+
+#define BIT_SHIFT_WMAC_MU_BFEE7_AID_8822C 0
+#define BIT_MASK_WMAC_MU_BFEE7_AID_8822C 0x1ff
+#define BIT_WMAC_MU_BFEE7_AID_8822C(x) \
+ (((x) & BIT_MASK_WMAC_MU_BFEE7_AID_8822C) \
+ << BIT_SHIFT_WMAC_MU_BFEE7_AID_8822C)
+#define BITS_WMAC_MU_BFEE7_AID_8822C \
+ (BIT_MASK_WMAC_MU_BFEE7_AID_8822C << BIT_SHIFT_WMAC_MU_BFEE7_AID_8822C)
+#define BIT_CLEAR_WMAC_MU_BFEE7_AID_8822C(x) \
+ ((x) & (~BITS_WMAC_MU_BFEE7_AID_8822C))
+#define BIT_GET_WMAC_MU_BFEE7_AID_8822C(x) \
+ (((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID_8822C) & \
+ BIT_MASK_WMAC_MU_BFEE7_AID_8822C)
+#define BIT_SET_WMAC_MU_BFEE7_AID_8822C(x, v) \
+ (BIT_CLEAR_WMAC_MU_BFEE7_AID_8822C(x) | BIT_WMAC_MU_BFEE7_AID_8822C(v))
+
+/* 2 REG_WMAC_BB_STOP_RX_COUNTER_8822C */
+#define BIT_RST_ALL_COUNTER_8822C BIT(31)
+
+#define BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822C 16
+#define BIT_MASK_ABORT_RX_VBON_COUNTER_8822C 0xff
+#define BIT_ABORT_RX_VBON_COUNTER_8822C(x) \
+ (((x) & BIT_MASK_ABORT_RX_VBON_COUNTER_8822C) \
+ << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822C)
+#define BITS_ABORT_RX_VBON_COUNTER_8822C \
+ (BIT_MASK_ABORT_RX_VBON_COUNTER_8822C \
+ << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822C)
+#define BIT_CLEAR_ABORT_RX_VBON_COUNTER_8822C(x) \
+ ((x) & (~BITS_ABORT_RX_VBON_COUNTER_8822C))
+#define BIT_GET_ABORT_RX_VBON_COUNTER_8822C(x) \
+ (((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER_8822C) & \
+ BIT_MASK_ABORT_RX_VBON_COUNTER_8822C)
+#define BIT_SET_ABORT_RX_VBON_COUNTER_8822C(x, v) \
+ (BIT_CLEAR_ABORT_RX_VBON_COUNTER_8822C(x) | \
+ BIT_ABORT_RX_VBON_COUNTER_8822C(v))
+
+#define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822C 8
+#define BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822C 0xff
+#define BIT_ABORT_RX_RDRDY_COUNTER_8822C(x) \
+ (((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822C) \
+ << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822C)
+#define BITS_ABORT_RX_RDRDY_COUNTER_8822C \
+ (BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822C \
+ << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822C)
+#define BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8822C(x) \
+ ((x) & (~BITS_ABORT_RX_RDRDY_COUNTER_8822C))
+#define BIT_GET_ABORT_RX_RDRDY_COUNTER_8822C(x) \
+ (((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8822C) & \
+ BIT_MASK_ABORT_RX_RDRDY_COUNTER_8822C)
+#define BIT_SET_ABORT_RX_RDRDY_COUNTER_8822C(x, v) \
+ (BIT_CLEAR_ABORT_RX_RDRDY_COUNTER_8822C(x) | \
+ BIT_ABORT_RX_RDRDY_COUNTER_8822C(v))
+
+#define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822C 0
+#define BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822C 0xff
+#define BIT_VBON_EARLY_FALLING_COUNTER_8822C(x) \
+ (((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822C) \
+ << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822C)
+#define BITS_VBON_EARLY_FALLING_COUNTER_8822C \
+ (BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822C \
+ << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822C)
+#define BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8822C(x) \
+ ((x) & (~BITS_VBON_EARLY_FALLING_COUNTER_8822C))
+#define BIT_GET_VBON_EARLY_FALLING_COUNTER_8822C(x) \
+ (((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8822C) & \
+ BIT_MASK_VBON_EARLY_FALLING_COUNTER_8822C)
+#define BIT_SET_VBON_EARLY_FALLING_COUNTER_8822C(x, v) \
+ (BIT_CLEAR_VBON_EARLY_FALLING_COUNTER_8822C(x) | \
+ BIT_VBON_EARLY_FALLING_COUNTER_8822C(v))
+
+/* 2 REG_WMAC_PLCP_MONITOR_8822C */
+#define BIT_WMAC_PLCP_TRX_SEL_8822C BIT(31)
+
+#define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822C 28
+#define BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822C 0x7
+#define BIT_WMAC_PLCP_RDSIG_SEL_8822C(x) \
+ (((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822C) \
+ << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822C)
+#define BITS_WMAC_PLCP_RDSIG_SEL_8822C \
+ (BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822C \
+ << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822C)
+#define BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8822C(x) \
+ ((x) & (~BITS_WMAC_PLCP_RDSIG_SEL_8822C))
+#define BIT_GET_WMAC_PLCP_RDSIG_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8822C) & \
+ BIT_MASK_WMAC_PLCP_RDSIG_SEL_8822C)
+#define BIT_SET_WMAC_PLCP_RDSIG_SEL_8822C(x, v) \
+ (BIT_CLEAR_WMAC_PLCP_RDSIG_SEL_8822C(x) | \
+ BIT_WMAC_PLCP_RDSIG_SEL_8822C(v))
+
+#define BIT_SHIFT_WMAC_RATE_IDX_8822C 24
+#define BIT_MASK_WMAC_RATE_IDX_8822C 0xf
+#define BIT_WMAC_RATE_IDX_8822C(x) \
+ (((x) & BIT_MASK_WMAC_RATE_IDX_8822C) << BIT_SHIFT_WMAC_RATE_IDX_8822C)
+#define BITS_WMAC_RATE_IDX_8822C \
+ (BIT_MASK_WMAC_RATE_IDX_8822C << BIT_SHIFT_WMAC_RATE_IDX_8822C)
+#define BIT_CLEAR_WMAC_RATE_IDX_8822C(x) ((x) & (~BITS_WMAC_RATE_IDX_8822C))
+#define BIT_GET_WMAC_RATE_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_WMAC_RATE_IDX_8822C) & BIT_MASK_WMAC_RATE_IDX_8822C)
+#define BIT_SET_WMAC_RATE_IDX_8822C(x, v) \
+ (BIT_CLEAR_WMAC_RATE_IDX_8822C(x) | BIT_WMAC_RATE_IDX_8822C(v))
+
+#define BIT_SHIFT_WMAC_PLCP_RDSIG_8822C 0
+#define BIT_MASK_WMAC_PLCP_RDSIG_8822C 0xffffff
+#define BIT_WMAC_PLCP_RDSIG_8822C(x) \
+ (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8822C) \
+ << BIT_SHIFT_WMAC_PLCP_RDSIG_8822C)
+#define BITS_WMAC_PLCP_RDSIG_8822C \
+ (BIT_MASK_WMAC_PLCP_RDSIG_8822C << BIT_SHIFT_WMAC_PLCP_RDSIG_8822C)
+#define BIT_CLEAR_WMAC_PLCP_RDSIG_8822C(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8822C))
+#define BIT_GET_WMAC_PLCP_RDSIG_8822C(x) \
+ (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8822C) & \
+ BIT_MASK_WMAC_PLCP_RDSIG_8822C)
+#define BIT_SET_WMAC_PLCP_RDSIG_8822C(x, v) \
+ (BIT_CLEAR_WMAC_PLCP_RDSIG_8822C(x) | BIT_WMAC_PLCP_RDSIG_8822C(v))
+
+/* 2 REG_WMAC_PLCP_MONITOR_MUTX_8822C */
+#define BIT_WMAC_MUTX_IDX_8822C BIT(24)
+
+#define BIT_SHIFT_WMAC_PLCP_RDSIG_8822C 0
+#define BIT_MASK_WMAC_PLCP_RDSIG_8822C 0xffffff
+#define BIT_WMAC_PLCP_RDSIG_8822C(x) \
+ (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8822C) \
+ << BIT_SHIFT_WMAC_PLCP_RDSIG_8822C)
+#define BITS_WMAC_PLCP_RDSIG_8822C \
+ (BIT_MASK_WMAC_PLCP_RDSIG_8822C << BIT_SHIFT_WMAC_PLCP_RDSIG_8822C)
+#define BIT_CLEAR_WMAC_PLCP_RDSIG_8822C(x) ((x) & (~BITS_WMAC_PLCP_RDSIG_8822C))
+#define BIT_GET_WMAC_PLCP_RDSIG_8822C(x) \
+ (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8822C) & \
+ BIT_MASK_WMAC_PLCP_RDSIG_8822C)
+#define BIT_SET_WMAC_PLCP_RDSIG_8822C(x, v) \
+ (BIT_CLEAR_WMAC_PLCP_RDSIG_8822C(x) | BIT_WMAC_PLCP_RDSIG_8822C(v))
+
+/* 2 REG_WMAC_CSIDMA_CFG_8822C */
+
+#define BIT_SHIFT_CSI_SEG_SIZE_8822C 16
+#define BIT_MASK_CSI_SEG_SIZE_8822C 0xfff
+#define BIT_CSI_SEG_SIZE_8822C(x) \
+ (((x) & BIT_MASK_CSI_SEG_SIZE_8822C) << BIT_SHIFT_CSI_SEG_SIZE_8822C)
+#define BITS_CSI_SEG_SIZE_8822C \
+ (BIT_MASK_CSI_SEG_SIZE_8822C << BIT_SHIFT_CSI_SEG_SIZE_8822C)
+#define BIT_CLEAR_CSI_SEG_SIZE_8822C(x) ((x) & (~BITS_CSI_SEG_SIZE_8822C))
+#define BIT_GET_CSI_SEG_SIZE_8822C(x) \
+ (((x) >> BIT_SHIFT_CSI_SEG_SIZE_8822C) & BIT_MASK_CSI_SEG_SIZE_8822C)
+#define BIT_SET_CSI_SEG_SIZE_8822C(x, v) \
+ (BIT_CLEAR_CSI_SEG_SIZE_8822C(x) | BIT_CSI_SEG_SIZE_8822C(v))
+
+#define BIT_SHIFT_CSI_START_PAGE_8822C 0
+#define BIT_MASK_CSI_START_PAGE_8822C 0xfff
+#define BIT_CSI_START_PAGE_8822C(x) \
+ (((x) & BIT_MASK_CSI_START_PAGE_8822C) \
+ << BIT_SHIFT_CSI_START_PAGE_8822C)
+#define BITS_CSI_START_PAGE_8822C \
+ (BIT_MASK_CSI_START_PAGE_8822C << BIT_SHIFT_CSI_START_PAGE_8822C)
+#define BIT_CLEAR_CSI_START_PAGE_8822C(x) ((x) & (~BITS_CSI_START_PAGE_8822C))
+#define BIT_GET_CSI_START_PAGE_8822C(x) \
+ (((x) >> BIT_SHIFT_CSI_START_PAGE_8822C) & \
+ BIT_MASK_CSI_START_PAGE_8822C)
+#define BIT_SET_CSI_START_PAGE_8822C(x, v) \
+ (BIT_CLEAR_CSI_START_PAGE_8822C(x) | BIT_CSI_START_PAGE_8822C(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_0_8822C (TA0 REGISTER) */
+
+#define BIT_SHIFT_TA0_V1_8822C 0
+#define BIT_MASK_TA0_V1_8822C 0xffffffffL
+#define BIT_TA0_V1_8822C(x) \
+ (((x) & BIT_MASK_TA0_V1_8822C) << BIT_SHIFT_TA0_V1_8822C)
+#define BITS_TA0_V1_8822C (BIT_MASK_TA0_V1_8822C << BIT_SHIFT_TA0_V1_8822C)
+#define BIT_CLEAR_TA0_V1_8822C(x) ((x) & (~BITS_TA0_V1_8822C))
+#define BIT_GET_TA0_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_TA0_V1_8822C) & BIT_MASK_TA0_V1_8822C)
+#define BIT_SET_TA0_V1_8822C(x, v) \
+ (BIT_CLEAR_TA0_V1_8822C(x) | BIT_TA0_V1_8822C(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_0_H_8822C (TA0 REGISTER) */
+
+#define BIT_SHIFT_TA0_H_V1_8822C 0
+#define BIT_MASK_TA0_H_V1_8822C 0xffff
+#define BIT_TA0_H_V1_8822C(x) \
+ (((x) & BIT_MASK_TA0_H_V1_8822C) << BIT_SHIFT_TA0_H_V1_8822C)
+#define BITS_TA0_H_V1_8822C \
+ (BIT_MASK_TA0_H_V1_8822C << BIT_SHIFT_TA0_H_V1_8822C)
+#define BIT_CLEAR_TA0_H_V1_8822C(x) ((x) & (~BITS_TA0_H_V1_8822C))
+#define BIT_GET_TA0_H_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_TA0_H_V1_8822C) & BIT_MASK_TA0_H_V1_8822C)
+#define BIT_SET_TA0_H_V1_8822C(x, v) \
+ (BIT_CLEAR_TA0_H_V1_8822C(x) | BIT_TA0_H_V1_8822C(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_1_8822C (TA1 REGISTER) */
+
+#define BIT_SHIFT_TA1_V1_8822C 0
+#define BIT_MASK_TA1_V1_8822C 0xffffffffL
+#define BIT_TA1_V1_8822C(x) \
+ (((x) & BIT_MASK_TA1_V1_8822C) << BIT_SHIFT_TA1_V1_8822C)
+#define BITS_TA1_V1_8822C (BIT_MASK_TA1_V1_8822C << BIT_SHIFT_TA1_V1_8822C)
+#define BIT_CLEAR_TA1_V1_8822C(x) ((x) & (~BITS_TA1_V1_8822C))
+#define BIT_GET_TA1_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_TA1_V1_8822C) & BIT_MASK_TA1_V1_8822C)
+#define BIT_SET_TA1_V1_8822C(x, v) \
+ (BIT_CLEAR_TA1_V1_8822C(x) | BIT_TA1_V1_8822C(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_1_H_8822C (TA1 REGISTER) */
+
+#define BIT_SHIFT_TA1_H_V1_8822C 0
+#define BIT_MASK_TA1_H_V1_8822C 0xffff
+#define BIT_TA1_H_V1_8822C(x) \
+ (((x) & BIT_MASK_TA1_H_V1_8822C) << BIT_SHIFT_TA1_H_V1_8822C)
+#define BITS_TA1_H_V1_8822C \
+ (BIT_MASK_TA1_H_V1_8822C << BIT_SHIFT_TA1_H_V1_8822C)
+#define BIT_CLEAR_TA1_H_V1_8822C(x) ((x) & (~BITS_TA1_H_V1_8822C))
+#define BIT_GET_TA1_H_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_TA1_H_V1_8822C) & BIT_MASK_TA1_H_V1_8822C)
+#define BIT_SET_TA1_H_V1_8822C(x, v) \
+ (BIT_CLEAR_TA1_H_V1_8822C(x) | BIT_TA1_H_V1_8822C(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_2_8822C (TA2 REGISTER) */
+
+#define BIT_SHIFT_TA2_V1_8822C 0
+#define BIT_MASK_TA2_V1_8822C 0xffffffffL
+#define BIT_TA2_V1_8822C(x) \
+ (((x) & BIT_MASK_TA2_V1_8822C) << BIT_SHIFT_TA2_V1_8822C)
+#define BITS_TA2_V1_8822C (BIT_MASK_TA2_V1_8822C << BIT_SHIFT_TA2_V1_8822C)
+#define BIT_CLEAR_TA2_V1_8822C(x) ((x) & (~BITS_TA2_V1_8822C))
+#define BIT_GET_TA2_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_TA2_V1_8822C) & BIT_MASK_TA2_V1_8822C)
+#define BIT_SET_TA2_V1_8822C(x, v) \
+ (BIT_CLEAR_TA2_V1_8822C(x) | BIT_TA2_V1_8822C(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_2_H_8822C (TA2 REGISTER) */
+
+#define BIT_SHIFT_TA2_H_V1_8822C 0
+#define BIT_MASK_TA2_H_V1_8822C 0xffff
+#define BIT_TA2_H_V1_8822C(x) \
+ (((x) & BIT_MASK_TA2_H_V1_8822C) << BIT_SHIFT_TA2_H_V1_8822C)
+#define BITS_TA2_H_V1_8822C \
+ (BIT_MASK_TA2_H_V1_8822C << BIT_SHIFT_TA2_H_V1_8822C)
+#define BIT_CLEAR_TA2_H_V1_8822C(x) ((x) & (~BITS_TA2_H_V1_8822C))
+#define BIT_GET_TA2_H_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_TA2_H_V1_8822C) & BIT_MASK_TA2_H_V1_8822C)
+#define BIT_SET_TA2_H_V1_8822C(x, v) \
+ (BIT_CLEAR_TA2_H_V1_8822C(x) | BIT_TA2_H_V1_8822C(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_3_8822C (TA3 REGISTER) */
+
+#define BIT_SHIFT_TA2_V1_8822C 0
+#define BIT_MASK_TA2_V1_8822C 0xffffffffL
+#define BIT_TA2_V1_8822C(x) \
+ (((x) & BIT_MASK_TA2_V1_8822C) << BIT_SHIFT_TA2_V1_8822C)
+#define BITS_TA2_V1_8822C (BIT_MASK_TA2_V1_8822C << BIT_SHIFT_TA2_V1_8822C)
+#define BIT_CLEAR_TA2_V1_8822C(x) ((x) & (~BITS_TA2_V1_8822C))
+#define BIT_GET_TA2_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_TA2_V1_8822C) & BIT_MASK_TA2_V1_8822C)
+#define BIT_SET_TA2_V1_8822C(x, v) \
+ (BIT_CLEAR_TA2_V1_8822C(x) | BIT_TA2_V1_8822C(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_3_H_8822C (TA3 REGISTER) */
+
+#define BIT_SHIFT_TA3_H_V1_8822C 0
+#define BIT_MASK_TA3_H_V1_8822C 0xffff
+#define BIT_TA3_H_V1_8822C(x) \
+ (((x) & BIT_MASK_TA3_H_V1_8822C) << BIT_SHIFT_TA3_H_V1_8822C)
+#define BITS_TA3_H_V1_8822C \
+ (BIT_MASK_TA3_H_V1_8822C << BIT_SHIFT_TA3_H_V1_8822C)
+#define BIT_CLEAR_TA3_H_V1_8822C(x) ((x) & (~BITS_TA3_H_V1_8822C))
+#define BIT_GET_TA3_H_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_TA3_H_V1_8822C) & BIT_MASK_TA3_H_V1_8822C)
+#define BIT_SET_TA3_H_V1_8822C(x, v) \
+ (BIT_CLEAR_TA3_H_V1_8822C(x) | BIT_TA3_H_V1_8822C(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_4_8822C (TA4 REGISTER) */
+
+#define BIT_SHIFT_TA4_V1_8822C 0
+#define BIT_MASK_TA4_V1_8822C 0xffffffffL
+#define BIT_TA4_V1_8822C(x) \
+ (((x) & BIT_MASK_TA4_V1_8822C) << BIT_SHIFT_TA4_V1_8822C)
+#define BITS_TA4_V1_8822C (BIT_MASK_TA4_V1_8822C << BIT_SHIFT_TA4_V1_8822C)
+#define BIT_CLEAR_TA4_V1_8822C(x) ((x) & (~BITS_TA4_V1_8822C))
+#define BIT_GET_TA4_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_TA4_V1_8822C) & BIT_MASK_TA4_V1_8822C)
+#define BIT_SET_TA4_V1_8822C(x, v) \
+ (BIT_CLEAR_TA4_V1_8822C(x) | BIT_TA4_V1_8822C(v))
+
+/* 2 REG_TRANSMIT_ADDRSS_4_H_8822C (TA4 REGISTER) */
+
+#define BIT_SHIFT_TA4_H_V1_8822C 0
+#define BIT_MASK_TA4_H_V1_8822C 0xffff
+#define BIT_TA4_H_V1_8822C(x) \
+ (((x) & BIT_MASK_TA4_H_V1_8822C) << BIT_SHIFT_TA4_H_V1_8822C)
+#define BITS_TA4_H_V1_8822C \
+ (BIT_MASK_TA4_H_V1_8822C << BIT_SHIFT_TA4_H_V1_8822C)
+#define BIT_CLEAR_TA4_H_V1_8822C(x) ((x) & (~BITS_TA4_H_V1_8822C))
+#define BIT_GET_TA4_H_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_TA4_H_V1_8822C) & BIT_MASK_TA4_H_V1_8822C)
+#define BIT_SET_TA4_H_V1_8822C(x, v) \
+ (BIT_CLEAR_TA4_H_V1_8822C(x) | BIT_TA4_H_V1_8822C(v))
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_RSVD_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_MACID1_8822C */
+
+#define BIT_SHIFT_MACID1_0_8822C 0
+#define BIT_MASK_MACID1_0_8822C 0xffffffffL
+#define BIT_MACID1_0_8822C(x) \
+ (((x) & BIT_MASK_MACID1_0_8822C) << BIT_SHIFT_MACID1_0_8822C)
+#define BITS_MACID1_0_8822C \
+ (BIT_MASK_MACID1_0_8822C << BIT_SHIFT_MACID1_0_8822C)
+#define BIT_CLEAR_MACID1_0_8822C(x) ((x) & (~BITS_MACID1_0_8822C))
+#define BIT_GET_MACID1_0_8822C(x) \
+ (((x) >> BIT_SHIFT_MACID1_0_8822C) & BIT_MASK_MACID1_0_8822C)
+#define BIT_SET_MACID1_0_8822C(x, v) \
+ (BIT_CLEAR_MACID1_0_8822C(x) | BIT_MACID1_0_8822C(v))
+
+/* 2 REG_MACID1_1_8822C */
+
+#define BIT_SHIFT_MACID1_1_8822C 0
+#define BIT_MASK_MACID1_1_8822C 0xffff
+#define BIT_MACID1_1_8822C(x) \
+ (((x) & BIT_MASK_MACID1_1_8822C) << BIT_SHIFT_MACID1_1_8822C)
+#define BITS_MACID1_1_8822C \
+ (BIT_MASK_MACID1_1_8822C << BIT_SHIFT_MACID1_1_8822C)
+#define BIT_CLEAR_MACID1_1_8822C(x) ((x) & (~BITS_MACID1_1_8822C))
+#define BIT_GET_MACID1_1_8822C(x) \
+ (((x) >> BIT_SHIFT_MACID1_1_8822C) & BIT_MASK_MACID1_1_8822C)
+#define BIT_SET_MACID1_1_8822C(x, v) \
+ (BIT_CLEAR_MACID1_1_8822C(x) | BIT_MACID1_1_8822C(v))
+
+/* 2 REG_BSSID1_8822C */
+
+#define BIT_SHIFT_BSSID1_0_8822C 0
+#define BIT_MASK_BSSID1_0_8822C 0xffffffffL
+#define BIT_BSSID1_0_8822C(x) \
+ (((x) & BIT_MASK_BSSID1_0_8822C) << BIT_SHIFT_BSSID1_0_8822C)
+#define BITS_BSSID1_0_8822C \
+ (BIT_MASK_BSSID1_0_8822C << BIT_SHIFT_BSSID1_0_8822C)
+#define BIT_CLEAR_BSSID1_0_8822C(x) ((x) & (~BITS_BSSID1_0_8822C))
+#define BIT_GET_BSSID1_0_8822C(x) \
+ (((x) >> BIT_SHIFT_BSSID1_0_8822C) & BIT_MASK_BSSID1_0_8822C)
+#define BIT_SET_BSSID1_0_8822C(x, v) \
+ (BIT_CLEAR_BSSID1_0_8822C(x) | BIT_BSSID1_0_8822C(v))
+
+/* 2 REG_BSSID1_1_8822C */
+
+#define BIT_SHIFT_BSSID1_1_8822C 0
+#define BIT_MASK_BSSID1_1_8822C 0xffff
+#define BIT_BSSID1_1_8822C(x) \
+ (((x) & BIT_MASK_BSSID1_1_8822C) << BIT_SHIFT_BSSID1_1_8822C)
+#define BITS_BSSID1_1_8822C \
+ (BIT_MASK_BSSID1_1_8822C << BIT_SHIFT_BSSID1_1_8822C)
+#define BIT_CLEAR_BSSID1_1_8822C(x) ((x) & (~BITS_BSSID1_1_8822C))
+#define BIT_GET_BSSID1_1_8822C(x) \
+ (((x) >> BIT_SHIFT_BSSID1_1_8822C) & BIT_MASK_BSSID1_1_8822C)
+#define BIT_SET_BSSID1_1_8822C(x, v) \
+ (BIT_CLEAR_BSSID1_1_8822C(x) | BIT_BSSID1_1_8822C(v))
+
+/* 2 REG_BCN_PSR_RPT1_8822C */
+
+#define BIT_SHIFT_DTIM_CNT1_8822C 24
+#define BIT_MASK_DTIM_CNT1_8822C 0xff
+#define BIT_DTIM_CNT1_8822C(x) \
+ (((x) & BIT_MASK_DTIM_CNT1_8822C) << BIT_SHIFT_DTIM_CNT1_8822C)
+#define BITS_DTIM_CNT1_8822C \
+ (BIT_MASK_DTIM_CNT1_8822C << BIT_SHIFT_DTIM_CNT1_8822C)
+#define BIT_CLEAR_DTIM_CNT1_8822C(x) ((x) & (~BITS_DTIM_CNT1_8822C))
+#define BIT_GET_DTIM_CNT1_8822C(x) \
+ (((x) >> BIT_SHIFT_DTIM_CNT1_8822C) & BIT_MASK_DTIM_CNT1_8822C)
+#define BIT_SET_DTIM_CNT1_8822C(x, v) \
+ (BIT_CLEAR_DTIM_CNT1_8822C(x) | BIT_DTIM_CNT1_8822C(v))
+
+#define BIT_SHIFT_DTIM_PERIOD1_8822C 16
+#define BIT_MASK_DTIM_PERIOD1_8822C 0xff
+#define BIT_DTIM_PERIOD1_8822C(x) \
+ (((x) & BIT_MASK_DTIM_PERIOD1_8822C) << BIT_SHIFT_DTIM_PERIOD1_8822C)
+#define BITS_DTIM_PERIOD1_8822C \
+ (BIT_MASK_DTIM_PERIOD1_8822C << BIT_SHIFT_DTIM_PERIOD1_8822C)
+#define BIT_CLEAR_DTIM_PERIOD1_8822C(x) ((x) & (~BITS_DTIM_PERIOD1_8822C))
+#define BIT_GET_DTIM_PERIOD1_8822C(x) \
+ (((x) >> BIT_SHIFT_DTIM_PERIOD1_8822C) & BIT_MASK_DTIM_PERIOD1_8822C)
+#define BIT_SET_DTIM_PERIOD1_8822C(x, v) \
+ (BIT_CLEAR_DTIM_PERIOD1_8822C(x) | BIT_DTIM_PERIOD1_8822C(v))
+
+#define BIT_DTIM1_8822C BIT(15)
+#define BIT_TIM1_8822C BIT(14)
+#define BIT_BCN_VALID_V2_8822C BIT(13)
+
+#define BIT_SHIFT_PS_AID_1_8822C 0
+#define BIT_MASK_PS_AID_1_8822C 0x7ff
+#define BIT_PS_AID_1_8822C(x) \
+ (((x) & BIT_MASK_PS_AID_1_8822C) << BIT_SHIFT_PS_AID_1_8822C)
+#define BITS_PS_AID_1_8822C \
+ (BIT_MASK_PS_AID_1_8822C << BIT_SHIFT_PS_AID_1_8822C)
+#define BIT_CLEAR_PS_AID_1_8822C(x) ((x) & (~BITS_PS_AID_1_8822C))
+#define BIT_GET_PS_AID_1_8822C(x) \
+ (((x) >> BIT_SHIFT_PS_AID_1_8822C) & BIT_MASK_PS_AID_1_8822C)
+#define BIT_SET_PS_AID_1_8822C(x, v) \
+ (BIT_CLEAR_PS_AID_1_8822C(x) | BIT_PS_AID_1_8822C(v))
+
+/* 2 REG_ASSOCIATED_BFMEE_SEL_8822C */
+#define BIT_TXUSER_ID1_8822C BIT(25)
+
+#define BIT_SHIFT_AID1_8822C 16
+#define BIT_MASK_AID1_8822C 0x1ff
+#define BIT_AID1_8822C(x) (((x) & BIT_MASK_AID1_8822C) << BIT_SHIFT_AID1_8822C)
+#define BITS_AID1_8822C (BIT_MASK_AID1_8822C << BIT_SHIFT_AID1_8822C)
+#define BIT_CLEAR_AID1_8822C(x) ((x) & (~BITS_AID1_8822C))
+#define BIT_GET_AID1_8822C(x) \
+ (((x) >> BIT_SHIFT_AID1_8822C) & BIT_MASK_AID1_8822C)
+#define BIT_SET_AID1_8822C(x, v) (BIT_CLEAR_AID1_8822C(x) | BIT_AID1_8822C(v))
+
+#define BIT_TXUSER_ID0_8822C BIT(9)
+
+#define BIT_SHIFT_AID0_8822C 0
+#define BIT_MASK_AID0_8822C 0x1ff
+#define BIT_AID0_8822C(x) (((x) & BIT_MASK_AID0_8822C) << BIT_SHIFT_AID0_8822C)
+#define BITS_AID0_8822C (BIT_MASK_AID0_8822C << BIT_SHIFT_AID0_8822C)
+#define BIT_CLEAR_AID0_8822C(x) ((x) & (~BITS_AID0_8822C))
+#define BIT_GET_AID0_8822C(x) \
+ (((x) >> BIT_SHIFT_AID0_8822C) & BIT_MASK_AID0_8822C)
+#define BIT_SET_AID0_8822C(x, v) (BIT_CLEAR_AID0_8822C(x) | BIT_AID0_8822C(v))
+
+/* 2 REG_SND_PTCL_CTRL_8822C */
+
+#define BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822C 24
+#define BIT_MASK_NDP_RX_STANDBY_TIMER_8822C 0xff
+#define BIT_NDP_RX_STANDBY_TIMER_8822C(x) \
+ (((x) & BIT_MASK_NDP_RX_STANDBY_TIMER_8822C) \
+ << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822C)
+#define BITS_NDP_RX_STANDBY_TIMER_8822C \
+ (BIT_MASK_NDP_RX_STANDBY_TIMER_8822C \
+ << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822C)
+#define BIT_CLEAR_NDP_RX_STANDBY_TIMER_8822C(x) \
+ ((x) & (~BITS_NDP_RX_STANDBY_TIMER_8822C))
+#define BIT_GET_NDP_RX_STANDBY_TIMER_8822C(x) \
+ (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8822C) & \
+ BIT_MASK_NDP_RX_STANDBY_TIMER_8822C)
+#define BIT_SET_NDP_RX_STANDBY_TIMER_8822C(x, v) \
+ (BIT_CLEAR_NDP_RX_STANDBY_TIMER_8822C(x) | \
+ BIT_NDP_RX_STANDBY_TIMER_8822C(v))
+
+#define BIT_R_WMAC_CHK_RPTPOLL_A2_DIS_8822C BIT(23)
+#define BIT_R_WMAC_CHK_UCNDPA_A2_DIS_8822C BIT(22)
+
+#define BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822C 16
+#define BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822C 0x3f
+#define BIT_CSI_RPT_OFFSET_HT_V1_8822C(x) \
+ (((x) & BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822C) \
+ << BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822C)
+#define BITS_CSI_RPT_OFFSET_HT_V1_8822C \
+ (BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822C \
+ << BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822C)
+#define BIT_CLEAR_CSI_RPT_OFFSET_HT_V1_8822C(x) \
+ ((x) & (~BITS_CSI_RPT_OFFSET_HT_V1_8822C))
+#define BIT_GET_CSI_RPT_OFFSET_HT_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_V1_8822C) & \
+ BIT_MASK_CSI_RPT_OFFSET_HT_V1_8822C)
+#define BIT_SET_CSI_RPT_OFFSET_HT_V1_8822C(x, v) \
+ (BIT_CLEAR_CSI_RPT_OFFSET_HT_V1_8822C(x) | \
+ BIT_CSI_RPT_OFFSET_HT_V1_8822C(v))
+
+#define BIT_R_WMAC_OFFSET_RPTPOLL_EN_8822C BIT(15)
+#define BIT_R_WMAC_CSI_CHKSUM_DIS_8822C BIT(14)
+
+#define BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1_8822C 8
+#define BIT_MASK_R_WMAC_VHT_CATEGORY_V1_8822C 0x3f
+#define BIT_R_WMAC_VHT_CATEGORY_V1_8822C(x) \
+ (((x) & BIT_MASK_R_WMAC_VHT_CATEGORY_V1_8822C) \
+ << BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1_8822C)
+#define BITS_R_WMAC_VHT_CATEGORY_V1_8822C \
+ (BIT_MASK_R_WMAC_VHT_CATEGORY_V1_8822C \
+ << BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1_8822C)
+#define BIT_CLEAR_R_WMAC_VHT_CATEGORY_V1_8822C(x) \
+ ((x) & (~BITS_R_WMAC_VHT_CATEGORY_V1_8822C))
+#define BIT_GET_R_WMAC_VHT_CATEGORY_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1_8822C) & \
+ BIT_MASK_R_WMAC_VHT_CATEGORY_V1_8822C)
+#define BIT_SET_R_WMAC_VHT_CATEGORY_V1_8822C(x, v) \
+ (BIT_CLEAR_R_WMAC_VHT_CATEGORY_V1_8822C(x) | \
+ BIT_R_WMAC_VHT_CATEGORY_V1_8822C(v))
+
+#define BIT_R_WMAC_USE_NSTS_8822C BIT(7)
+#define BIT_R_DISABLE_CHECK_VHTSIGB_CRC_8822C BIT(6)
+#define BIT_R_DISABLE_CHECK_VHTSIGA_CRC_8822C BIT(5)
+#define BIT_R_WMAC_BFPARAM_SEL_8822C BIT(4)
+#define BIT_R_WMAC_CSISEQ_SEL_8822C BIT(3)
+#define BIT_R_WMAC_CSI_WITHHTC_EN_8822C BIT(2)
+#define BIT_R_WMAC_HT_NDPA_EN_8822C BIT(1)
+#define BIT_R_WMAC_VHT_NDPA_EN_8822C BIT(0)
+
+/* 2 REG_RX_CSI_RPT_INFO_8822C */
+#define BIT_WRITE_ENABLE_8822C BIT(31)
+#define BIT_WMAC_CHECK_SOUNDING_SEQ_8822C BIT(30)
+
+#define BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8822C 1
+#define BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8822C 0xffffff
+#define BIT_VHTHT_MIMO_CTRL_FIELD_8822C(x) \
+ (((x) & BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8822C) \
+ << BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8822C)
+#define BITS_VHTHT_MIMO_CTRL_FIELD_8822C \
+ (BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8822C \
+ << BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8822C)
+#define BIT_CLEAR_VHTHT_MIMO_CTRL_FIELD_8822C(x) \
+ ((x) & (~BITS_VHTHT_MIMO_CTRL_FIELD_8822C))
+#define BIT_GET_VHTHT_MIMO_CTRL_FIELD_8822C(x) \
+ (((x) >> BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD_8822C) & \
+ BIT_MASK_VHTHT_MIMO_CTRL_FIELD_8822C)
+#define BIT_SET_VHTHT_MIMO_CTRL_FIELD_8822C(x, v) \
+ (BIT_CLEAR_VHTHT_MIMO_CTRL_FIELD_8822C(x) | \
+ BIT_VHTHT_MIMO_CTRL_FIELD_8822C(v))
+
+#define BIT_CSI_INTERRUPT_STATUS_8822C BIT(0)
+
+/* 2 REG_NS_ARP_CTRL_8822C */
+#define BIT_R_WMAC_NSARP_RSPEN_8822C BIT(15)
+#define BIT_R_WMAC_NSARP_RARP_8822C BIT(9)
+#define BIT_R_WMAC_NSARP_RIPV6_8822C BIT(8)
+
+#define BIT_SHIFT_R_WMAC_NSARP_MODEN_8822C 6
+#define BIT_MASK_R_WMAC_NSARP_MODEN_8822C 0x3
+#define BIT_R_WMAC_NSARP_MODEN_8822C(x) \
+ (((x) & BIT_MASK_R_WMAC_NSARP_MODEN_8822C) \
+ << BIT_SHIFT_R_WMAC_NSARP_MODEN_8822C)
+#define BITS_R_WMAC_NSARP_MODEN_8822C \
+ (BIT_MASK_R_WMAC_NSARP_MODEN_8822C \
+ << BIT_SHIFT_R_WMAC_NSARP_MODEN_8822C)
+#define BIT_CLEAR_R_WMAC_NSARP_MODEN_8822C(x) \
+ ((x) & (~BITS_R_WMAC_NSARP_MODEN_8822C))
+#define BIT_GET_R_WMAC_NSARP_MODEN_8822C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8822C) & \
+ BIT_MASK_R_WMAC_NSARP_MODEN_8822C)
+#define BIT_SET_R_WMAC_NSARP_MODEN_8822C(x, v) \
+ (BIT_CLEAR_R_WMAC_NSARP_MODEN_8822C(x) | \
+ BIT_R_WMAC_NSARP_MODEN_8822C(v))
+
+#define BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822C 4
+#define BIT_MASK_R_WMAC_NSARP_RSPFTP_8822C 0x3
+#define BIT_R_WMAC_NSARP_RSPFTP_8822C(x) \
+ (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8822C) \
+ << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822C)
+#define BITS_R_WMAC_NSARP_RSPFTP_8822C \
+ (BIT_MASK_R_WMAC_NSARP_RSPFTP_8822C \
+ << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822C)
+#define BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8822C(x) \
+ ((x) & (~BITS_R_WMAC_NSARP_RSPFTP_8822C))
+#define BIT_GET_R_WMAC_NSARP_RSPFTP_8822C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8822C) & \
+ BIT_MASK_R_WMAC_NSARP_RSPFTP_8822C)
+#define BIT_SET_R_WMAC_NSARP_RSPFTP_8822C(x, v) \
+ (BIT_CLEAR_R_WMAC_NSARP_RSPFTP_8822C(x) | \
+ BIT_R_WMAC_NSARP_RSPFTP_8822C(v))
+
+#define BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822C 0
+#define BIT_MASK_R_WMAC_NSARP_RSPSEC_8822C 0xf
+#define BIT_R_WMAC_NSARP_RSPSEC_8822C(x) \
+ (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8822C) \
+ << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822C)
+#define BITS_R_WMAC_NSARP_RSPSEC_8822C \
+ (BIT_MASK_R_WMAC_NSARP_RSPSEC_8822C \
+ << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822C)
+#define BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8822C(x) \
+ ((x) & (~BITS_R_WMAC_NSARP_RSPSEC_8822C))
+#define BIT_GET_R_WMAC_NSARP_RSPSEC_8822C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8822C) & \
+ BIT_MASK_R_WMAC_NSARP_RSPSEC_8822C)
+#define BIT_SET_R_WMAC_NSARP_RSPSEC_8822C(x, v) \
+ (BIT_CLEAR_R_WMAC_NSARP_RSPSEC_8822C(x) | \
+ BIT_R_WMAC_NSARP_RSPSEC_8822C(v))
+
+/* 2 REG_NS_ARP_INFO_8822C */
+#define BIT_REQ_IS_MCNS_8822C BIT(23)
+#define BIT_REQ_IS_UCNS_8822C BIT(22)
+#define BIT_REQ_IS_USNS_8822C BIT(21)
+#define BIT_REQ_IS_ARP_8822C BIT(20)
+#define BIT_EXPRSP_MH_WITHQC_8822C BIT(19)
+
+#define BIT_SHIFT_EXPRSP_SECTYPE_8822C 16
+#define BIT_MASK_EXPRSP_SECTYPE_8822C 0x7
+#define BIT_EXPRSP_SECTYPE_8822C(x) \
+ (((x) & BIT_MASK_EXPRSP_SECTYPE_8822C) \
+ << BIT_SHIFT_EXPRSP_SECTYPE_8822C)
+#define BITS_EXPRSP_SECTYPE_8822C \
+ (BIT_MASK_EXPRSP_SECTYPE_8822C << BIT_SHIFT_EXPRSP_SECTYPE_8822C)
+#define BIT_CLEAR_EXPRSP_SECTYPE_8822C(x) ((x) & (~BITS_EXPRSP_SECTYPE_8822C))
+#define BIT_GET_EXPRSP_SECTYPE_8822C(x) \
+ (((x) >> BIT_SHIFT_EXPRSP_SECTYPE_8822C) & \
+ BIT_MASK_EXPRSP_SECTYPE_8822C)
+#define BIT_SET_EXPRSP_SECTYPE_8822C(x, v) \
+ (BIT_CLEAR_EXPRSP_SECTYPE_8822C(x) | BIT_EXPRSP_SECTYPE_8822C(v))
+
+#define BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822C 8
+#define BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822C 0xff
+#define BIT_EXPRSP_CHKSM_7_TO_0_8822C(x) \
+ (((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822C) \
+ << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822C)
+#define BITS_EXPRSP_CHKSM_7_TO_0_8822C \
+ (BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822C \
+ << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822C)
+#define BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8822C(x) \
+ ((x) & (~BITS_EXPRSP_CHKSM_7_TO_0_8822C))
+#define BIT_GET_EXPRSP_CHKSM_7_TO_0_8822C(x) \
+ (((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8822C) & \
+ BIT_MASK_EXPRSP_CHKSM_7_TO_0_8822C)
+#define BIT_SET_EXPRSP_CHKSM_7_TO_0_8822C(x, v) \
+ (BIT_CLEAR_EXPRSP_CHKSM_7_TO_0_8822C(x) | \
+ BIT_EXPRSP_CHKSM_7_TO_0_8822C(v))
+
+#define BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822C 0
+#define BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822C 0xff
+#define BIT_EXPRSP_CHKSM_15_TO_8_8822C(x) \
+ (((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822C) \
+ << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822C)
+#define BITS_EXPRSP_CHKSM_15_TO_8_8822C \
+ (BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822C \
+ << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822C)
+#define BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8822C(x) \
+ ((x) & (~BITS_EXPRSP_CHKSM_15_TO_8_8822C))
+#define BIT_GET_EXPRSP_CHKSM_15_TO_8_8822C(x) \
+ (((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8822C) & \
+ BIT_MASK_EXPRSP_CHKSM_15_TO_8_8822C)
+#define BIT_SET_EXPRSP_CHKSM_15_TO_8_8822C(x, v) \
+ (BIT_CLEAR_EXPRSP_CHKSM_15_TO_8_8822C(x) | \
+ BIT_EXPRSP_CHKSM_15_TO_8_8822C(v))
+
+/* 2 REG_BEAMFORMING_INFO_NSARP_V1_8822C */
+
+#define BIT_SHIFT_WMAC_ARPIP_8822C 0
+#define BIT_MASK_WMAC_ARPIP_8822C 0xffffffffL
+#define BIT_WMAC_ARPIP_8822C(x) \
+ (((x) & BIT_MASK_WMAC_ARPIP_8822C) << BIT_SHIFT_WMAC_ARPIP_8822C)
+#define BITS_WMAC_ARPIP_8822C \
+ (BIT_MASK_WMAC_ARPIP_8822C << BIT_SHIFT_WMAC_ARPIP_8822C)
+#define BIT_CLEAR_WMAC_ARPIP_8822C(x) ((x) & (~BITS_WMAC_ARPIP_8822C))
+#define BIT_GET_WMAC_ARPIP_8822C(x) \
+ (((x) >> BIT_SHIFT_WMAC_ARPIP_8822C) & BIT_MASK_WMAC_ARPIP_8822C)
+#define BIT_SET_WMAC_ARPIP_8822C(x, v) \
+ (BIT_CLEAR_WMAC_ARPIP_8822C(x) | BIT_WMAC_ARPIP_8822C(v))
+
+/* 2 REG_BEAMFORMING_INFO_NSARP_8822C */
+
+#define BIT_SHIFT_UPD_BFMEE_USERID_8822C 13
+#define BIT_MASK_UPD_BFMEE_USERID_8822C 0x7
+#define BIT_UPD_BFMEE_USERID_8822C(x) \
+ (((x) & BIT_MASK_UPD_BFMEE_USERID_8822C) \
+ << BIT_SHIFT_UPD_BFMEE_USERID_8822C)
+#define BITS_UPD_BFMEE_USERID_8822C \
+ (BIT_MASK_UPD_BFMEE_USERID_8822C << BIT_SHIFT_UPD_BFMEE_USERID_8822C)
+#define BIT_CLEAR_UPD_BFMEE_USERID_8822C(x) \
+ ((x) & (~BITS_UPD_BFMEE_USERID_8822C))
+#define BIT_GET_UPD_BFMEE_USERID_8822C(x) \
+ (((x) >> BIT_SHIFT_UPD_BFMEE_USERID_8822C) & \
+ BIT_MASK_UPD_BFMEE_USERID_8822C)
+#define BIT_SET_UPD_BFMEE_USERID_8822C(x, v) \
+ (BIT_CLEAR_UPD_BFMEE_USERID_8822C(x) | BIT_UPD_BFMEE_USERID_8822C(v))
+
+#define BIT_UPD_BFMEE_FBTP_8822C BIT(12)
+
+#define BIT_SHIFT_UPD_BFMEE_BW_8822C 0
+#define BIT_MASK_UPD_BFMEE_BW_8822C 0xfff
+#define BIT_UPD_BFMEE_BW_8822C(x) \
+ (((x) & BIT_MASK_UPD_BFMEE_BW_8822C) << BIT_SHIFT_UPD_BFMEE_BW_8822C)
+#define BITS_UPD_BFMEE_BW_8822C \
+ (BIT_MASK_UPD_BFMEE_BW_8822C << BIT_SHIFT_UPD_BFMEE_BW_8822C)
+#define BIT_CLEAR_UPD_BFMEE_BW_8822C(x) ((x) & (~BITS_UPD_BFMEE_BW_8822C))
+#define BIT_GET_UPD_BFMEE_BW_8822C(x) \
+ (((x) >> BIT_SHIFT_UPD_BFMEE_BW_8822C) & BIT_MASK_UPD_BFMEE_BW_8822C)
+#define BIT_SET_UPD_BFMEE_BW_8822C(x, v) \
+ (BIT_CLEAR_UPD_BFMEE_BW_8822C(x) | BIT_UPD_BFMEE_BW_8822C(v))
+
+#define BIT_SHIFT_UPD_BFMEE_CB_8822C 8
+#define BIT_MASK_UPD_BFMEE_CB_8822C 0x3
+#define BIT_UPD_BFMEE_CB_8822C(x) \
+ (((x) & BIT_MASK_UPD_BFMEE_CB_8822C) << BIT_SHIFT_UPD_BFMEE_CB_8822C)
+#define BITS_UPD_BFMEE_CB_8822C \
+ (BIT_MASK_UPD_BFMEE_CB_8822C << BIT_SHIFT_UPD_BFMEE_CB_8822C)
+#define BIT_CLEAR_UPD_BFMEE_CB_8822C(x) ((x) & (~BITS_UPD_BFMEE_CB_8822C))
+#define BIT_GET_UPD_BFMEE_CB_8822C(x) \
+ (((x) >> BIT_SHIFT_UPD_BFMEE_CB_8822C) & BIT_MASK_UPD_BFMEE_CB_8822C)
+#define BIT_SET_UPD_BFMEE_CB_8822C(x, v) \
+ (BIT_CLEAR_UPD_BFMEE_CB_8822C(x) | BIT_UPD_BFMEE_CB_8822C(v))
+
+#define BIT_SHIFT_UPD_BFMEE_NG_8822C 6
+#define BIT_MASK_UPD_BFMEE_NG_8822C 0x3
+#define BIT_UPD_BFMEE_NG_8822C(x) \
+ (((x) & BIT_MASK_UPD_BFMEE_NG_8822C) << BIT_SHIFT_UPD_BFMEE_NG_8822C)
+#define BITS_UPD_BFMEE_NG_8822C \
+ (BIT_MASK_UPD_BFMEE_NG_8822C << BIT_SHIFT_UPD_BFMEE_NG_8822C)
+#define BIT_CLEAR_UPD_BFMEE_NG_8822C(x) ((x) & (~BITS_UPD_BFMEE_NG_8822C))
+#define BIT_GET_UPD_BFMEE_NG_8822C(x) \
+ (((x) >> BIT_SHIFT_UPD_BFMEE_NG_8822C) & BIT_MASK_UPD_BFMEE_NG_8822C)
+#define BIT_SET_UPD_BFMEE_NG_8822C(x, v) \
+ (BIT_CLEAR_UPD_BFMEE_NG_8822C(x) | BIT_UPD_BFMEE_NG_8822C(v))
+
+#define BIT_SHIFT_UPD_BFMEE_NR_8822C 3
+#define BIT_MASK_UPD_BFMEE_NR_8822C 0x7
+#define BIT_UPD_BFMEE_NR_8822C(x) \
+ (((x) & BIT_MASK_UPD_BFMEE_NR_8822C) << BIT_SHIFT_UPD_BFMEE_NR_8822C)
+#define BITS_UPD_BFMEE_NR_8822C \
+ (BIT_MASK_UPD_BFMEE_NR_8822C << BIT_SHIFT_UPD_BFMEE_NR_8822C)
+#define BIT_CLEAR_UPD_BFMEE_NR_8822C(x) ((x) & (~BITS_UPD_BFMEE_NR_8822C))
+#define BIT_GET_UPD_BFMEE_NR_8822C(x) \
+ (((x) >> BIT_SHIFT_UPD_BFMEE_NR_8822C) & BIT_MASK_UPD_BFMEE_NR_8822C)
+#define BIT_SET_UPD_BFMEE_NR_8822C(x, v) \
+ (BIT_CLEAR_UPD_BFMEE_NR_8822C(x) | BIT_UPD_BFMEE_NR_8822C(v))
+
+#define BIT_SHIFT_UPD_BFMEE_NC_8822C 0
+#define BIT_MASK_UPD_BFMEE_NC_8822C 0x7
+#define BIT_UPD_BFMEE_NC_8822C(x) \
+ (((x) & BIT_MASK_UPD_BFMEE_NC_8822C) << BIT_SHIFT_UPD_BFMEE_NC_8822C)
+#define BITS_UPD_BFMEE_NC_8822C \
+ (BIT_MASK_UPD_BFMEE_NC_8822C << BIT_SHIFT_UPD_BFMEE_NC_8822C)
+#define BIT_CLEAR_UPD_BFMEE_NC_8822C(x) ((x) & (~BITS_UPD_BFMEE_NC_8822C))
+#define BIT_GET_UPD_BFMEE_NC_8822C(x) \
+ (((x) >> BIT_SHIFT_UPD_BFMEE_NC_8822C) & BIT_MASK_UPD_BFMEE_NC_8822C)
+#define BIT_SET_UPD_BFMEE_NC_8822C(x, v) \
+ (BIT_CLEAR_UPD_BFMEE_NC_8822C(x) | BIT_UPD_BFMEE_NC_8822C(v))
+
+/* 2 REG_IPV6_8822C */
+
+#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8822C 0
+#define BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8822C 0xffffffffL
+#define BIT_R_WMAC_IPV6_MYIPAD_0_8822C(x) \
+ (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8822C) \
+ << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8822C)
+#define BITS_R_WMAC_IPV6_MYIPAD_0_8822C \
+ (BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8822C \
+ << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8822C)
+#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0_8822C(x) \
+ ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_0_8822C))
+#define BIT_GET_R_WMAC_IPV6_MYIPAD_0_8822C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8822C) & \
+ BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8822C)
+#define BIT_SET_R_WMAC_IPV6_MYIPAD_0_8822C(x, v) \
+ (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_0_8822C(x) | \
+ BIT_R_WMAC_IPV6_MYIPAD_0_8822C(v))
+
+/* 2 REG_IPV6_1_8822C */
+
+#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8822C 0
+#define BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8822C 0xffffffffL
+#define BIT_R_WMAC_IPV6_MYIPAD_1_8822C(x) \
+ (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8822C) \
+ << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8822C)
+#define BITS_R_WMAC_IPV6_MYIPAD_1_8822C \
+ (BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8822C \
+ << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8822C)
+#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1_8822C(x) \
+ ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_1_8822C))
+#define BIT_GET_R_WMAC_IPV6_MYIPAD_1_8822C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8822C) & \
+ BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8822C)
+#define BIT_SET_R_WMAC_IPV6_MYIPAD_1_8822C(x, v) \
+ (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_1_8822C(x) | \
+ BIT_R_WMAC_IPV6_MYIPAD_1_8822C(v))
+
+/* 2 REG_IPV6_2_8822C */
+
+#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8822C 0
+#define BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8822C 0xffffffffL
+#define BIT_R_WMAC_IPV6_MYIPAD_2_8822C(x) \
+ (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8822C) \
+ << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8822C)
+#define BITS_R_WMAC_IPV6_MYIPAD_2_8822C \
+ (BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8822C \
+ << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8822C)
+#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2_8822C(x) \
+ ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_2_8822C))
+#define BIT_GET_R_WMAC_IPV6_MYIPAD_2_8822C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8822C) & \
+ BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8822C)
+#define BIT_SET_R_WMAC_IPV6_MYIPAD_2_8822C(x, v) \
+ (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_2_8822C(x) | \
+ BIT_R_WMAC_IPV6_MYIPAD_2_8822C(v))
+
+/* 2 REG_IPV6_3_8822C */
+
+#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8822C 0
+#define BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8822C 0xffffffffL
+#define BIT_R_WMAC_IPV6_MYIPAD_3_8822C(x) \
+ (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8822C) \
+ << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8822C)
+#define BITS_R_WMAC_IPV6_MYIPAD_3_8822C \
+ (BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8822C \
+ << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8822C)
+#define BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3_8822C(x) \
+ ((x) & (~BITS_R_WMAC_IPV6_MYIPAD_3_8822C))
+#define BIT_GET_R_WMAC_IPV6_MYIPAD_3_8822C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8822C) & \
+ BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8822C)
+#define BIT_SET_R_WMAC_IPV6_MYIPAD_3_8822C(x, v) \
+ (BIT_CLEAR_R_WMAC_IPV6_MYIPAD_3_8822C(x) | \
+ BIT_R_WMAC_IPV6_MYIPAD_3_8822C(v))
+
+/* 2 REG_WMAC_RTX_CTX_SUBTYPE_CFG_8822C */
+
+#define BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822C 4
+#define BIT_MASK_R_WMAC_CTX_SUBTYPE_8822C 0xf
+#define BIT_R_WMAC_CTX_SUBTYPE_8822C(x) \
+ (((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8822C) \
+ << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822C)
+#define BITS_R_WMAC_CTX_SUBTYPE_8822C \
+ (BIT_MASK_R_WMAC_CTX_SUBTYPE_8822C \
+ << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822C)
+#define BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8822C(x) \
+ ((x) & (~BITS_R_WMAC_CTX_SUBTYPE_8822C))
+#define BIT_GET_R_WMAC_CTX_SUBTYPE_8822C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8822C) & \
+ BIT_MASK_R_WMAC_CTX_SUBTYPE_8822C)
+#define BIT_SET_R_WMAC_CTX_SUBTYPE_8822C(x, v) \
+ (BIT_CLEAR_R_WMAC_CTX_SUBTYPE_8822C(x) | \
+ BIT_R_WMAC_CTX_SUBTYPE_8822C(v))
+
+#define BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822C 0
+#define BIT_MASK_R_WMAC_RTX_SUBTYPE_8822C 0xf
+#define BIT_R_WMAC_RTX_SUBTYPE_8822C(x) \
+ (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8822C) \
+ << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822C)
+#define BITS_R_WMAC_RTX_SUBTYPE_8822C \
+ (BIT_MASK_R_WMAC_RTX_SUBTYPE_8822C \
+ << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822C)
+#define BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8822C(x) \
+ ((x) & (~BITS_R_WMAC_RTX_SUBTYPE_8822C))
+#define BIT_GET_R_WMAC_RTX_SUBTYPE_8822C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8822C) & \
+ BIT_MASK_R_WMAC_RTX_SUBTYPE_8822C)
+#define BIT_SET_R_WMAC_RTX_SUBTYPE_8822C(x, v) \
+ (BIT_CLEAR_R_WMAC_RTX_SUBTYPE_8822C(x) | \
+ BIT_R_WMAC_RTX_SUBTYPE_8822C(v))
+
+/* 2 REG_WMAC_SWAES_DIO_B63_B32_8822C */
+
+#define BIT_SHIFT_WMAC_SWAES_DIO_B63_B32_8822C 0
+#define BIT_MASK_WMAC_SWAES_DIO_B63_B32_8822C 0xffffffffL
+#define BIT_WMAC_SWAES_DIO_B63_B32_8822C(x) \
+ (((x) & BIT_MASK_WMAC_SWAES_DIO_B63_B32_8822C) \
+ << BIT_SHIFT_WMAC_SWAES_DIO_B63_B32_8822C)
+#define BITS_WMAC_SWAES_DIO_B63_B32_8822C \
+ (BIT_MASK_WMAC_SWAES_DIO_B63_B32_8822C \
+ << BIT_SHIFT_WMAC_SWAES_DIO_B63_B32_8822C)
+#define BIT_CLEAR_WMAC_SWAES_DIO_B63_B32_8822C(x) \
+ ((x) & (~BITS_WMAC_SWAES_DIO_B63_B32_8822C))
+#define BIT_GET_WMAC_SWAES_DIO_B63_B32_8822C(x) \
+ (((x) >> BIT_SHIFT_WMAC_SWAES_DIO_B63_B32_8822C) & \
+ BIT_MASK_WMAC_SWAES_DIO_B63_B32_8822C)
+#define BIT_SET_WMAC_SWAES_DIO_B63_B32_8822C(x, v) \
+ (BIT_CLEAR_WMAC_SWAES_DIO_B63_B32_8822C(x) | \
+ BIT_WMAC_SWAES_DIO_B63_B32_8822C(v))
+
+/* 2 REG_WMAC_SWAES_DIO_B95_B64_8822C */
+
+#define BIT_SHIFT_WMAC_SWAES_DIO_B95_B64_8822C 0
+#define BIT_MASK_WMAC_SWAES_DIO_B95_B64_8822C 0xffffffffL
+#define BIT_WMAC_SWAES_DIO_B95_B64_8822C(x) \
+ (((x) & BIT_MASK_WMAC_SWAES_DIO_B95_B64_8822C) \
+ << BIT_SHIFT_WMAC_SWAES_DIO_B95_B64_8822C)
+#define BITS_WMAC_SWAES_DIO_B95_B64_8822C \
+ (BIT_MASK_WMAC_SWAES_DIO_B95_B64_8822C \
+ << BIT_SHIFT_WMAC_SWAES_DIO_B95_B64_8822C)
+#define BIT_CLEAR_WMAC_SWAES_DIO_B95_B64_8822C(x) \
+ ((x) & (~BITS_WMAC_SWAES_DIO_B95_B64_8822C))
+#define BIT_GET_WMAC_SWAES_DIO_B95_B64_8822C(x) \
+ (((x) >> BIT_SHIFT_WMAC_SWAES_DIO_B95_B64_8822C) & \
+ BIT_MASK_WMAC_SWAES_DIO_B95_B64_8822C)
+#define BIT_SET_WMAC_SWAES_DIO_B95_B64_8822C(x, v) \
+ (BIT_CLEAR_WMAC_SWAES_DIO_B95_B64_8822C(x) | \
+ BIT_WMAC_SWAES_DIO_B95_B64_8822C(v))
+
+/* 2 REG_WMAC_SWAES_DIO_B127_B96_8822C */
+
+#define BIT_SHIFT_WMAC_SWAES_DIO_B127_B96_8822C 0
+#define BIT_MASK_WMAC_SWAES_DIO_B127_B96_8822C 0xffffffffL
+#define BIT_WMAC_SWAES_DIO_B127_B96_8822C(x) \
+ (((x) & BIT_MASK_WMAC_SWAES_DIO_B127_B96_8822C) \
+ << BIT_SHIFT_WMAC_SWAES_DIO_B127_B96_8822C)
+#define BITS_WMAC_SWAES_DIO_B127_B96_8822C \
+ (BIT_MASK_WMAC_SWAES_DIO_B127_B96_8822C \
+ << BIT_SHIFT_WMAC_SWAES_DIO_B127_B96_8822C)
+#define BIT_CLEAR_WMAC_SWAES_DIO_B127_B96_8822C(x) \
+ ((x) & (~BITS_WMAC_SWAES_DIO_B127_B96_8822C))
+#define BIT_GET_WMAC_SWAES_DIO_B127_B96_8822C(x) \
+ (((x) >> BIT_SHIFT_WMAC_SWAES_DIO_B127_B96_8822C) & \
+ BIT_MASK_WMAC_SWAES_DIO_B127_B96_8822C)
+#define BIT_SET_WMAC_SWAES_DIO_B127_B96_8822C(x, v) \
+ (BIT_CLEAR_WMAC_SWAES_DIO_B127_B96_8822C(x) | \
+ BIT_WMAC_SWAES_DIO_B127_B96_8822C(v))
+
+/* 2 REG_WMAC_SWAES_CFG_8822C */
+
+/* 2 REG_BT_COEX_V2_8822C */
+#define BIT_GNT_BT_POLARITY_8822C BIT(12)
+#define BIT_GNT_BT_BYPASS_PRIORITY_8822C BIT(8)
+
+#define BIT_SHIFT_TIMER_8822C 0
+#define BIT_MASK_TIMER_8822C 0xff
+#define BIT_TIMER_8822C(x) \
+ (((x) & BIT_MASK_TIMER_8822C) << BIT_SHIFT_TIMER_8822C)
+#define BITS_TIMER_8822C (BIT_MASK_TIMER_8822C << BIT_SHIFT_TIMER_8822C)
+#define BIT_CLEAR_TIMER_8822C(x) ((x) & (~BITS_TIMER_8822C))
+#define BIT_GET_TIMER_8822C(x) \
+ (((x) >> BIT_SHIFT_TIMER_8822C) & BIT_MASK_TIMER_8822C)
+#define BIT_SET_TIMER_8822C(x, v) \
+ (BIT_CLEAR_TIMER_8822C(x) | BIT_TIMER_8822C(v))
+
+/* 2 REG_BT_COEX_8822C */
+#define BIT_R_GNT_BT_RFC_SW_8822C BIT(12)
+#define BIT_R_GNT_BT_RFC_SW_EN_8822C BIT(11)
+#define BIT_R_GNT_BT_BB_SW_8822C BIT(10)
+#define BIT_R_GNT_BT_BB_SW_EN_8822C BIT(9)
+#define BIT_R_BT_CNT_THREN_8822C BIT(8)
+
+#define BIT_SHIFT_R_BT_CNT_THR_8822C 0
+#define BIT_MASK_R_BT_CNT_THR_8822C 0xff
+#define BIT_R_BT_CNT_THR_8822C(x) \
+ (((x) & BIT_MASK_R_BT_CNT_THR_8822C) << BIT_SHIFT_R_BT_CNT_THR_8822C)
+#define BITS_R_BT_CNT_THR_8822C \
+ (BIT_MASK_R_BT_CNT_THR_8822C << BIT_SHIFT_R_BT_CNT_THR_8822C)
+#define BIT_CLEAR_R_BT_CNT_THR_8822C(x) ((x) & (~BITS_R_BT_CNT_THR_8822C))
+#define BIT_GET_R_BT_CNT_THR_8822C(x) \
+ (((x) >> BIT_SHIFT_R_BT_CNT_THR_8822C) & BIT_MASK_R_BT_CNT_THR_8822C)
+#define BIT_SET_R_BT_CNT_THR_8822C(x, v) \
+ (BIT_CLEAR_R_BT_CNT_THR_8822C(x) | BIT_R_BT_CNT_THR_8822C(v))
+
+/* 2 REG_WLAN_ACT_MASK_CTRL_8822C */
+
+#define BIT_SHIFT_RXMYRTS_NAV_V1_8822C 8
+#define BIT_MASK_RXMYRTS_NAV_V1_8822C 0xff
+#define BIT_RXMYRTS_NAV_V1_8822C(x) \
+ (((x) & BIT_MASK_RXMYRTS_NAV_V1_8822C) \
+ << BIT_SHIFT_RXMYRTS_NAV_V1_8822C)
+#define BITS_RXMYRTS_NAV_V1_8822C \
+ (BIT_MASK_RXMYRTS_NAV_V1_8822C << BIT_SHIFT_RXMYRTS_NAV_V1_8822C)
+#define BIT_CLEAR_RXMYRTS_NAV_V1_8822C(x) ((x) & (~BITS_RXMYRTS_NAV_V1_8822C))
+#define BIT_GET_RXMYRTS_NAV_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8822C) & \
+ BIT_MASK_RXMYRTS_NAV_V1_8822C)
+#define BIT_SET_RXMYRTS_NAV_V1_8822C(x, v) \
+ (BIT_CLEAR_RXMYRTS_NAV_V1_8822C(x) | BIT_RXMYRTS_NAV_V1_8822C(v))
+
+#define BIT_SHIFT_RTSRST_V1_8822C 0
+#define BIT_MASK_RTSRST_V1_8822C 0xff
+#define BIT_RTSRST_V1_8822C(x) \
+ (((x) & BIT_MASK_RTSRST_V1_8822C) << BIT_SHIFT_RTSRST_V1_8822C)
+#define BITS_RTSRST_V1_8822C \
+ (BIT_MASK_RTSRST_V1_8822C << BIT_SHIFT_RTSRST_V1_8822C)
+#define BIT_CLEAR_RTSRST_V1_8822C(x) ((x) & (~BITS_RTSRST_V1_8822C))
+#define BIT_GET_RTSRST_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_RTSRST_V1_8822C) & BIT_MASK_RTSRST_V1_8822C)
+#define BIT_SET_RTSRST_V1_8822C(x, v) \
+ (BIT_CLEAR_RTSRST_V1_8822C(x) | BIT_RTSRST_V1_8822C(v))
+
+/* 2 REG_WLAN_ACT_MASK_CTRL_1_8822C */
+#define BIT_WLRX_TER_BY_CTL_1_8822C BIT(11)
+#define BIT_WLRX_TER_BY_AD_1_8822C BIT(10)
+#define BIT_ANT_DIVERSITY_SEL_1_8822C BIT(9)
+#define BIT_ANTSEL_FOR_BT_CTRL_EN_1_8822C BIT(8)
+#define BIT_WLACT_LOW_GNTWL_EN_1_8822C BIT(2)
+#define BIT_WLACT_HIGH_GNTBT_EN_1_8822C BIT(1)
+#define BIT_NAV_UPPER_1_V1_8822C BIT(0)
+
+/* 2 REG_BT_COEX_ENHANCED_INTR_CTRL_8822C */
+
+#define BIT_SHIFT_BT_STAT_DELAY_8822C 12
+#define BIT_MASK_BT_STAT_DELAY_8822C 0xf
+#define BIT_BT_STAT_DELAY_8822C(x) \
+ (((x) & BIT_MASK_BT_STAT_DELAY_8822C) << BIT_SHIFT_BT_STAT_DELAY_8822C)
+#define BITS_BT_STAT_DELAY_8822C \
+ (BIT_MASK_BT_STAT_DELAY_8822C << BIT_SHIFT_BT_STAT_DELAY_8822C)
+#define BIT_CLEAR_BT_STAT_DELAY_8822C(x) ((x) & (~BITS_BT_STAT_DELAY_8822C))
+#define BIT_GET_BT_STAT_DELAY_8822C(x) \
+ (((x) >> BIT_SHIFT_BT_STAT_DELAY_8822C) & BIT_MASK_BT_STAT_DELAY_8822C)
+#define BIT_SET_BT_STAT_DELAY_8822C(x, v) \
+ (BIT_CLEAR_BT_STAT_DELAY_8822C(x) | BIT_BT_STAT_DELAY_8822C(v))
+
+#define BIT_SHIFT_BT_TRX_INIT_DETECT_8822C 8
+#define BIT_MASK_BT_TRX_INIT_DETECT_8822C 0xf
+#define BIT_BT_TRX_INIT_DETECT_8822C(x) \
+ (((x) & BIT_MASK_BT_TRX_INIT_DETECT_8822C) \
+ << BIT_SHIFT_BT_TRX_INIT_DETECT_8822C)
+#define BITS_BT_TRX_INIT_DETECT_8822C \
+ (BIT_MASK_BT_TRX_INIT_DETECT_8822C \
+ << BIT_SHIFT_BT_TRX_INIT_DETECT_8822C)
+#define BIT_CLEAR_BT_TRX_INIT_DETECT_8822C(x) \
+ ((x) & (~BITS_BT_TRX_INIT_DETECT_8822C))
+#define BIT_GET_BT_TRX_INIT_DETECT_8822C(x) \
+ (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8822C) & \
+ BIT_MASK_BT_TRX_INIT_DETECT_8822C)
+#define BIT_SET_BT_TRX_INIT_DETECT_8822C(x, v) \
+ (BIT_CLEAR_BT_TRX_INIT_DETECT_8822C(x) | \
+ BIT_BT_TRX_INIT_DETECT_8822C(v))
+
+#define BIT_SHIFT_BT_PRI_DETECT_TO_8822C 4
+#define BIT_MASK_BT_PRI_DETECT_TO_8822C 0xf
+#define BIT_BT_PRI_DETECT_TO_8822C(x) \
+ (((x) & BIT_MASK_BT_PRI_DETECT_TO_8822C) \
+ << BIT_SHIFT_BT_PRI_DETECT_TO_8822C)
+#define BITS_BT_PRI_DETECT_TO_8822C \
+ (BIT_MASK_BT_PRI_DETECT_TO_8822C << BIT_SHIFT_BT_PRI_DETECT_TO_8822C)
+#define BIT_CLEAR_BT_PRI_DETECT_TO_8822C(x) \
+ ((x) & (~BITS_BT_PRI_DETECT_TO_8822C))
+#define BIT_GET_BT_PRI_DETECT_TO_8822C(x) \
+ (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8822C) & \
+ BIT_MASK_BT_PRI_DETECT_TO_8822C)
+#define BIT_SET_BT_PRI_DETECT_TO_8822C(x, v) \
+ (BIT_CLEAR_BT_PRI_DETECT_TO_8822C(x) | BIT_BT_PRI_DETECT_TO_8822C(v))
+
+#define BIT_R_GRANTALL_WLMASK_8822C BIT(3)
+#define BIT_STATIS_BT_EN_8822C BIT(2)
+#define BIT_WL_ACT_MASK_ENABLE_8822C BIT(1)
+#define BIT_ENHANCED_BT_8822C BIT(0)
+
+/* 2 REG_BT_ACT_STATISTICS_8822C */
+
+#define BIT_SHIFT_STATIS_BT_HI_RX_8822C 16
+#define BIT_MASK_STATIS_BT_HI_RX_8822C 0xffff
+#define BIT_STATIS_BT_HI_RX_8822C(x) \
+ (((x) & BIT_MASK_STATIS_BT_HI_RX_8822C) \
+ << BIT_SHIFT_STATIS_BT_HI_RX_8822C)
+#define BITS_STATIS_BT_HI_RX_8822C \
+ (BIT_MASK_STATIS_BT_HI_RX_8822C << BIT_SHIFT_STATIS_BT_HI_RX_8822C)
+#define BIT_CLEAR_STATIS_BT_HI_RX_8822C(x) ((x) & (~BITS_STATIS_BT_HI_RX_8822C))
+#define BIT_GET_STATIS_BT_HI_RX_8822C(x) \
+ (((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8822C) & \
+ BIT_MASK_STATIS_BT_HI_RX_8822C)
+#define BIT_SET_STATIS_BT_HI_RX_8822C(x, v) \
+ (BIT_CLEAR_STATIS_BT_HI_RX_8822C(x) | BIT_STATIS_BT_HI_RX_8822C(v))
+
+#define BIT_SHIFT_STATIS_BT_HI_TX_8822C 0
+#define BIT_MASK_STATIS_BT_HI_TX_8822C 0xffff
+#define BIT_STATIS_BT_HI_TX_8822C(x) \
+ (((x) & BIT_MASK_STATIS_BT_HI_TX_8822C) \
+ << BIT_SHIFT_STATIS_BT_HI_TX_8822C)
+#define BITS_STATIS_BT_HI_TX_8822C \
+ (BIT_MASK_STATIS_BT_HI_TX_8822C << BIT_SHIFT_STATIS_BT_HI_TX_8822C)
+#define BIT_CLEAR_STATIS_BT_HI_TX_8822C(x) ((x) & (~BITS_STATIS_BT_HI_TX_8822C))
+#define BIT_GET_STATIS_BT_HI_TX_8822C(x) \
+ (((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8822C) & \
+ BIT_MASK_STATIS_BT_HI_TX_8822C)
+#define BIT_SET_STATIS_BT_HI_TX_8822C(x, v) \
+ (BIT_CLEAR_STATIS_BT_HI_TX_8822C(x) | BIT_STATIS_BT_HI_TX_8822C(v))
+
+/* 2 REG_BT_ACT_STATISTICS_1_8822C */
+
+#define BIT_SHIFT_STATIS_BT_LO_RX_1_8822C 16
+#define BIT_MASK_STATIS_BT_LO_RX_1_8822C 0xffff
+#define BIT_STATIS_BT_LO_RX_1_8822C(x) \
+ (((x) & BIT_MASK_STATIS_BT_LO_RX_1_8822C) \
+ << BIT_SHIFT_STATIS_BT_LO_RX_1_8822C)
+#define BITS_STATIS_BT_LO_RX_1_8822C \
+ (BIT_MASK_STATIS_BT_LO_RX_1_8822C << BIT_SHIFT_STATIS_BT_LO_RX_1_8822C)
+#define BIT_CLEAR_STATIS_BT_LO_RX_1_8822C(x) \
+ ((x) & (~BITS_STATIS_BT_LO_RX_1_8822C))
+#define BIT_GET_STATIS_BT_LO_RX_1_8822C(x) \
+ (((x) >> BIT_SHIFT_STATIS_BT_LO_RX_1_8822C) & \
+ BIT_MASK_STATIS_BT_LO_RX_1_8822C)
+#define BIT_SET_STATIS_BT_LO_RX_1_8822C(x, v) \
+ (BIT_CLEAR_STATIS_BT_LO_RX_1_8822C(x) | BIT_STATIS_BT_LO_RX_1_8822C(v))
+
+#define BIT_SHIFT_STATIS_BT_LO_TX_1_8822C 0
+#define BIT_MASK_STATIS_BT_LO_TX_1_8822C 0xffff
+#define BIT_STATIS_BT_LO_TX_1_8822C(x) \
+ (((x) & BIT_MASK_STATIS_BT_LO_TX_1_8822C) \
+ << BIT_SHIFT_STATIS_BT_LO_TX_1_8822C)
+#define BITS_STATIS_BT_LO_TX_1_8822C \
+ (BIT_MASK_STATIS_BT_LO_TX_1_8822C << BIT_SHIFT_STATIS_BT_LO_TX_1_8822C)
+#define BIT_CLEAR_STATIS_BT_LO_TX_1_8822C(x) \
+ ((x) & (~BITS_STATIS_BT_LO_TX_1_8822C))
+#define BIT_GET_STATIS_BT_LO_TX_1_8822C(x) \
+ (((x) >> BIT_SHIFT_STATIS_BT_LO_TX_1_8822C) & \
+ BIT_MASK_STATIS_BT_LO_TX_1_8822C)
+#define BIT_SET_STATIS_BT_LO_TX_1_8822C(x, v) \
+ (BIT_CLEAR_STATIS_BT_LO_TX_1_8822C(x) | BIT_STATIS_BT_LO_TX_1_8822C(v))
+
+/* 2 REG_BT_STATISTICS_CONTROL_REGISTER_8822C */
+
+#define BIT_SHIFT_R_BT_CMD_RPT_8822C 16
+#define BIT_MASK_R_BT_CMD_RPT_8822C 0xffff
+#define BIT_R_BT_CMD_RPT_8822C(x) \
+ (((x) & BIT_MASK_R_BT_CMD_RPT_8822C) << BIT_SHIFT_R_BT_CMD_RPT_8822C)
+#define BITS_R_BT_CMD_RPT_8822C \
+ (BIT_MASK_R_BT_CMD_RPT_8822C << BIT_SHIFT_R_BT_CMD_RPT_8822C)
+#define BIT_CLEAR_R_BT_CMD_RPT_8822C(x) ((x) & (~BITS_R_BT_CMD_RPT_8822C))
+#define BIT_GET_R_BT_CMD_RPT_8822C(x) \
+ (((x) >> BIT_SHIFT_R_BT_CMD_RPT_8822C) & BIT_MASK_R_BT_CMD_RPT_8822C)
+#define BIT_SET_R_BT_CMD_RPT_8822C(x, v) \
+ (BIT_CLEAR_R_BT_CMD_RPT_8822C(x) | BIT_R_BT_CMD_RPT_8822C(v))
+
+#define BIT_SHIFT_R_RPT_FROM_BT_8822C 8
+#define BIT_MASK_R_RPT_FROM_BT_8822C 0xff
+#define BIT_R_RPT_FROM_BT_8822C(x) \
+ (((x) & BIT_MASK_R_RPT_FROM_BT_8822C) << BIT_SHIFT_R_RPT_FROM_BT_8822C)
+#define BITS_R_RPT_FROM_BT_8822C \
+ (BIT_MASK_R_RPT_FROM_BT_8822C << BIT_SHIFT_R_RPT_FROM_BT_8822C)
+#define BIT_CLEAR_R_RPT_FROM_BT_8822C(x) ((x) & (~BITS_R_RPT_FROM_BT_8822C))
+#define BIT_GET_R_RPT_FROM_BT_8822C(x) \
+ (((x) >> BIT_SHIFT_R_RPT_FROM_BT_8822C) & BIT_MASK_R_RPT_FROM_BT_8822C)
+#define BIT_SET_R_RPT_FROM_BT_8822C(x, v) \
+ (BIT_CLEAR_R_RPT_FROM_BT_8822C(x) | BIT_R_RPT_FROM_BT_8822C(v))
+
+#define BIT_SHIFT_BT_HID_ISR_SET_8822C 6
+#define BIT_MASK_BT_HID_ISR_SET_8822C 0x3
+#define BIT_BT_HID_ISR_SET_8822C(x) \
+ (((x) & BIT_MASK_BT_HID_ISR_SET_8822C) \
+ << BIT_SHIFT_BT_HID_ISR_SET_8822C)
+#define BITS_BT_HID_ISR_SET_8822C \
+ (BIT_MASK_BT_HID_ISR_SET_8822C << BIT_SHIFT_BT_HID_ISR_SET_8822C)
+#define BIT_CLEAR_BT_HID_ISR_SET_8822C(x) ((x) & (~BITS_BT_HID_ISR_SET_8822C))
+#define BIT_GET_BT_HID_ISR_SET_8822C(x) \
+ (((x) >> BIT_SHIFT_BT_HID_ISR_SET_8822C) & \
+ BIT_MASK_BT_HID_ISR_SET_8822C)
+#define BIT_SET_BT_HID_ISR_SET_8822C(x, v) \
+ (BIT_CLEAR_BT_HID_ISR_SET_8822C(x) | BIT_BT_HID_ISR_SET_8822C(v))
+
+#define BIT_TDMA_BT_START_NOTIFY_8822C BIT(5)
+#define BIT_ENABLE_TDMA_FW_MODE_8822C BIT(4)
+#define BIT_ENABLE_PTA_TDMA_MODE_8822C BIT(3)
+#define BIT_ENABLE_COEXIST_TAB_IN_TDMA_8822C BIT(2)
+#define BIT_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA_8822C BIT(1)
+#define BIT_RTK_BT_ENABLE_8822C BIT(0)
+
+/* 2 REG_BT_STATUS_REPORT_REGISTER_8822C */
+
+#define BIT_SHIFT_BT_PROFILE_8822C 24
+#define BIT_MASK_BT_PROFILE_8822C 0xff
+#define BIT_BT_PROFILE_8822C(x) \
+ (((x) & BIT_MASK_BT_PROFILE_8822C) << BIT_SHIFT_BT_PROFILE_8822C)
+#define BITS_BT_PROFILE_8822C \
+ (BIT_MASK_BT_PROFILE_8822C << BIT_SHIFT_BT_PROFILE_8822C)
+#define BIT_CLEAR_BT_PROFILE_8822C(x) ((x) & (~BITS_BT_PROFILE_8822C))
+#define BIT_GET_BT_PROFILE_8822C(x) \
+ (((x) >> BIT_SHIFT_BT_PROFILE_8822C) & BIT_MASK_BT_PROFILE_8822C)
+#define BIT_SET_BT_PROFILE_8822C(x, v) \
+ (BIT_CLEAR_BT_PROFILE_8822C(x) | BIT_BT_PROFILE_8822C(v))
+
+#define BIT_SHIFT_BT_POWER_8822C 16
+#define BIT_MASK_BT_POWER_8822C 0xff
+#define BIT_BT_POWER_8822C(x) \
+ (((x) & BIT_MASK_BT_POWER_8822C) << BIT_SHIFT_BT_POWER_8822C)
+#define BITS_BT_POWER_8822C \
+ (BIT_MASK_BT_POWER_8822C << BIT_SHIFT_BT_POWER_8822C)
+#define BIT_CLEAR_BT_POWER_8822C(x) ((x) & (~BITS_BT_POWER_8822C))
+#define BIT_GET_BT_POWER_8822C(x) \
+ (((x) >> BIT_SHIFT_BT_POWER_8822C) & BIT_MASK_BT_POWER_8822C)
+#define BIT_SET_BT_POWER_8822C(x, v) \
+ (BIT_CLEAR_BT_POWER_8822C(x) | BIT_BT_POWER_8822C(v))
+
+#define BIT_SHIFT_BT_PREDECT_STATUS_8822C 8
+#define BIT_MASK_BT_PREDECT_STATUS_8822C 0xff
+#define BIT_BT_PREDECT_STATUS_8822C(x) \
+ (((x) & BIT_MASK_BT_PREDECT_STATUS_8822C) \
+ << BIT_SHIFT_BT_PREDECT_STATUS_8822C)
+#define BITS_BT_PREDECT_STATUS_8822C \
+ (BIT_MASK_BT_PREDECT_STATUS_8822C << BIT_SHIFT_BT_PREDECT_STATUS_8822C)
+#define BIT_CLEAR_BT_PREDECT_STATUS_8822C(x) \
+ ((x) & (~BITS_BT_PREDECT_STATUS_8822C))
+#define BIT_GET_BT_PREDECT_STATUS_8822C(x) \
+ (((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8822C) & \
+ BIT_MASK_BT_PREDECT_STATUS_8822C)
+#define BIT_SET_BT_PREDECT_STATUS_8822C(x, v) \
+ (BIT_CLEAR_BT_PREDECT_STATUS_8822C(x) | BIT_BT_PREDECT_STATUS_8822C(v))
+
+#define BIT_SHIFT_BT_CMD_INFO_8822C 0
+#define BIT_MASK_BT_CMD_INFO_8822C 0xff
+#define BIT_BT_CMD_INFO_8822C(x) \
+ (((x) & BIT_MASK_BT_CMD_INFO_8822C) << BIT_SHIFT_BT_CMD_INFO_8822C)
+#define BITS_BT_CMD_INFO_8822C \
+ (BIT_MASK_BT_CMD_INFO_8822C << BIT_SHIFT_BT_CMD_INFO_8822C)
+#define BIT_CLEAR_BT_CMD_INFO_8822C(x) ((x) & (~BITS_BT_CMD_INFO_8822C))
+#define BIT_GET_BT_CMD_INFO_8822C(x) \
+ (((x) >> BIT_SHIFT_BT_CMD_INFO_8822C) & BIT_MASK_BT_CMD_INFO_8822C)
+#define BIT_SET_BT_CMD_INFO_8822C(x, v) \
+ (BIT_CLEAR_BT_CMD_INFO_8822C(x) | BIT_BT_CMD_INFO_8822C(v))
+
+/* 2 REG_BT_INTERRUPT_CONTROL_REGISTER_8822C */
+#define BIT_EN_MAC_NULL_PKT_NOTIFY_8822C BIT(31)
+#define BIT_EN_WLAN_RPT_AND_BT_QUERY_8822C BIT(30)
+#define BIT_EN_BT_STSTUS_RPT_8822C BIT(29)
+#define BIT_EN_BT_POWER_8822C BIT(28)
+#define BIT_EN_BT_CHANNEL_8822C BIT(27)
+#define BIT_EN_BT_SLOT_CHANGE_8822C BIT(26)
+#define BIT_EN_BT_PROFILE_OR_HID_8822C BIT(25)
+#define BIT_WLAN_RPT_NOTIFY_8822C BIT(24)
+
+#define BIT_SHIFT_WLAN_RPT_DATA_8822C 16
+#define BIT_MASK_WLAN_RPT_DATA_8822C 0xff
+#define BIT_WLAN_RPT_DATA_8822C(x) \
+ (((x) & BIT_MASK_WLAN_RPT_DATA_8822C) << BIT_SHIFT_WLAN_RPT_DATA_8822C)
+#define BITS_WLAN_RPT_DATA_8822C \
+ (BIT_MASK_WLAN_RPT_DATA_8822C << BIT_SHIFT_WLAN_RPT_DATA_8822C)
+#define BIT_CLEAR_WLAN_RPT_DATA_8822C(x) ((x) & (~BITS_WLAN_RPT_DATA_8822C))
+#define BIT_GET_WLAN_RPT_DATA_8822C(x) \
+ (((x) >> BIT_SHIFT_WLAN_RPT_DATA_8822C) & BIT_MASK_WLAN_RPT_DATA_8822C)
+#define BIT_SET_WLAN_RPT_DATA_8822C(x, v) \
+ (BIT_CLEAR_WLAN_RPT_DATA_8822C(x) | BIT_WLAN_RPT_DATA_8822C(v))
+
+#define BIT_SHIFT_CMD_ID_8822C 8
+#define BIT_MASK_CMD_ID_8822C 0xff
+#define BIT_CMD_ID_8822C(x) \
+ (((x) & BIT_MASK_CMD_ID_8822C) << BIT_SHIFT_CMD_ID_8822C)
+#define BITS_CMD_ID_8822C (BIT_MASK_CMD_ID_8822C << BIT_SHIFT_CMD_ID_8822C)
+#define BIT_CLEAR_CMD_ID_8822C(x) ((x) & (~BITS_CMD_ID_8822C))
+#define BIT_GET_CMD_ID_8822C(x) \
+ (((x) >> BIT_SHIFT_CMD_ID_8822C) & BIT_MASK_CMD_ID_8822C)
+#define BIT_SET_CMD_ID_8822C(x, v) \
+ (BIT_CLEAR_CMD_ID_8822C(x) | BIT_CMD_ID_8822C(v))
+
+#define BIT_SHIFT_BT_DATA_8822C 0
+#define BIT_MASK_BT_DATA_8822C 0xff
+#define BIT_BT_DATA_8822C(x) \
+ (((x) & BIT_MASK_BT_DATA_8822C) << BIT_SHIFT_BT_DATA_8822C)
+#define BITS_BT_DATA_8822C (BIT_MASK_BT_DATA_8822C << BIT_SHIFT_BT_DATA_8822C)
+#define BIT_CLEAR_BT_DATA_8822C(x) ((x) & (~BITS_BT_DATA_8822C))
+#define BIT_GET_BT_DATA_8822C(x) \
+ (((x) >> BIT_SHIFT_BT_DATA_8822C) & BIT_MASK_BT_DATA_8822C)
+#define BIT_SET_BT_DATA_8822C(x, v) \
+ (BIT_CLEAR_BT_DATA_8822C(x) | BIT_BT_DATA_8822C(v))
+
+/* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8822C */
+
+#define BIT_SHIFT_WLAN_RPT_TO_8822C 0
+#define BIT_MASK_WLAN_RPT_TO_8822C 0xff
+#define BIT_WLAN_RPT_TO_8822C(x) \
+ (((x) & BIT_MASK_WLAN_RPT_TO_8822C) << BIT_SHIFT_WLAN_RPT_TO_8822C)
+#define BITS_WLAN_RPT_TO_8822C \
+ (BIT_MASK_WLAN_RPT_TO_8822C << BIT_SHIFT_WLAN_RPT_TO_8822C)
+#define BIT_CLEAR_WLAN_RPT_TO_8822C(x) ((x) & (~BITS_WLAN_RPT_TO_8822C))
+#define BIT_GET_WLAN_RPT_TO_8822C(x) \
+ (((x) >> BIT_SHIFT_WLAN_RPT_TO_8822C) & BIT_MASK_WLAN_RPT_TO_8822C)
+#define BIT_SET_WLAN_RPT_TO_8822C(x, v) \
+ (BIT_CLEAR_WLAN_RPT_TO_8822C(x) | BIT_WLAN_RPT_TO_8822C(v))
+
+/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8822C */
+
+#define BIT_SHIFT_ISOLATION_CHK_0_8822C 1
+#define BIT_MASK_ISOLATION_CHK_0_8822C 0x7fffff
+#define BIT_ISOLATION_CHK_0_8822C(x) \
+ (((x) & BIT_MASK_ISOLATION_CHK_0_8822C) \
+ << BIT_SHIFT_ISOLATION_CHK_0_8822C)
+#define BITS_ISOLATION_CHK_0_8822C \
+ (BIT_MASK_ISOLATION_CHK_0_8822C << BIT_SHIFT_ISOLATION_CHK_0_8822C)
+#define BIT_CLEAR_ISOLATION_CHK_0_8822C(x) ((x) & (~BITS_ISOLATION_CHK_0_8822C))
+#define BIT_GET_ISOLATION_CHK_0_8822C(x) \
+ (((x) >> BIT_SHIFT_ISOLATION_CHK_0_8822C) & \
+ BIT_MASK_ISOLATION_CHK_0_8822C)
+#define BIT_SET_ISOLATION_CHK_0_8822C(x, v) \
+ (BIT_CLEAR_ISOLATION_CHK_0_8822C(x) | BIT_ISOLATION_CHK_0_8822C(v))
+
+#define BIT_ISOLATION_EN_8822C BIT(0)
+
+/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1_8822C */
+
+#define BIT_SHIFT_ISOLATION_CHK_1_8822C 0
+#define BIT_MASK_ISOLATION_CHK_1_8822C 0xffffffffL
+#define BIT_ISOLATION_CHK_1_8822C(x) \
+ (((x) & BIT_MASK_ISOLATION_CHK_1_8822C) \
+ << BIT_SHIFT_ISOLATION_CHK_1_8822C)
+#define BITS_ISOLATION_CHK_1_8822C \
+ (BIT_MASK_ISOLATION_CHK_1_8822C << BIT_SHIFT_ISOLATION_CHK_1_8822C)
+#define BIT_CLEAR_ISOLATION_CHK_1_8822C(x) ((x) & (~BITS_ISOLATION_CHK_1_8822C))
+#define BIT_GET_ISOLATION_CHK_1_8822C(x) \
+ (((x) >> BIT_SHIFT_ISOLATION_CHK_1_8822C) & \
+ BIT_MASK_ISOLATION_CHK_1_8822C)
+#define BIT_SET_ISOLATION_CHK_1_8822C(x, v) \
+ (BIT_CLEAR_ISOLATION_CHK_1_8822C(x) | BIT_ISOLATION_CHK_1_8822C(v))
+
+/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2_8822C */
+
+#define BIT_SHIFT_ISOLATION_CHK_2_8822C 0
+#define BIT_MASK_ISOLATION_CHK_2_8822C 0xffffff
+#define BIT_ISOLATION_CHK_2_8822C(x) \
+ (((x) & BIT_MASK_ISOLATION_CHK_2_8822C) \
+ << BIT_SHIFT_ISOLATION_CHK_2_8822C)
+#define BITS_ISOLATION_CHK_2_8822C \
+ (BIT_MASK_ISOLATION_CHK_2_8822C << BIT_SHIFT_ISOLATION_CHK_2_8822C)
+#define BIT_CLEAR_ISOLATION_CHK_2_8822C(x) ((x) & (~BITS_ISOLATION_CHK_2_8822C))
+#define BIT_GET_ISOLATION_CHK_2_8822C(x) \
+ (((x) >> BIT_SHIFT_ISOLATION_CHK_2_8822C) & \
+ BIT_MASK_ISOLATION_CHK_2_8822C)
+#define BIT_SET_ISOLATION_CHK_2_8822C(x, v) \
+ (BIT_CLEAR_ISOLATION_CHK_2_8822C(x) | BIT_ISOLATION_CHK_2_8822C(v))
+
+/* 2 REG_BT_INTERRUPT_STATUS_REGISTER_8822C */
+#define BIT_BT_HID_ISR_8822C BIT(7)
+#define BIT_BT_QUERY_ISR_8822C BIT(6)
+#define BIT_MAC_NULL_PKT_NOTIFY_ISR_8822C BIT(5)
+#define BIT_WLAN_RPT_ISR_8822C BIT(4)
+#define BIT_BT_POWER_ISR_8822C BIT(3)
+#define BIT_BT_CHANNEL_ISR_8822C BIT(2)
+#define BIT_BT_SLOT_CHANGE_ISR_8822C BIT(1)
+#define BIT_BT_PROFILE_ISR_8822C BIT(0)
+
+/* 2 REG_BT_TDMA_TIME_REGISTER_8822C */
+
+#define BIT_SHIFT_BT_TIME_8822C 6
+#define BIT_MASK_BT_TIME_8822C 0x3ffffff
+#define BIT_BT_TIME_8822C(x) \
+ (((x) & BIT_MASK_BT_TIME_8822C) << BIT_SHIFT_BT_TIME_8822C)
+#define BITS_BT_TIME_8822C (BIT_MASK_BT_TIME_8822C << BIT_SHIFT_BT_TIME_8822C)
+#define BIT_CLEAR_BT_TIME_8822C(x) ((x) & (~BITS_BT_TIME_8822C))
+#define BIT_GET_BT_TIME_8822C(x) \
+ (((x) >> BIT_SHIFT_BT_TIME_8822C) & BIT_MASK_BT_TIME_8822C)
+#define BIT_SET_BT_TIME_8822C(x, v) \
+ (BIT_CLEAR_BT_TIME_8822C(x) | BIT_BT_TIME_8822C(v))
+
+#define BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822C 0
+#define BIT_MASK_BT_RPT_SAMPLE_RATE_8822C 0x3f
+#define BIT_BT_RPT_SAMPLE_RATE_8822C(x) \
+ (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8822C) \
+ << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822C)
+#define BITS_BT_RPT_SAMPLE_RATE_8822C \
+ (BIT_MASK_BT_RPT_SAMPLE_RATE_8822C \
+ << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822C)
+#define BIT_CLEAR_BT_RPT_SAMPLE_RATE_8822C(x) \
+ ((x) & (~BITS_BT_RPT_SAMPLE_RATE_8822C))
+#define BIT_GET_BT_RPT_SAMPLE_RATE_8822C(x) \
+ (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8822C) & \
+ BIT_MASK_BT_RPT_SAMPLE_RATE_8822C)
+#define BIT_SET_BT_RPT_SAMPLE_RATE_8822C(x, v) \
+ (BIT_CLEAR_BT_RPT_SAMPLE_RATE_8822C(x) | \
+ BIT_BT_RPT_SAMPLE_RATE_8822C(v))
+
+/* 2 REG_BT_ACT_REGISTER_8822C */
+
+#define BIT_SHIFT_BT_EISR_EN_8822C 16
+#define BIT_MASK_BT_EISR_EN_8822C 0xff
+#define BIT_BT_EISR_EN_8822C(x) \
+ (((x) & BIT_MASK_BT_EISR_EN_8822C) << BIT_SHIFT_BT_EISR_EN_8822C)
+#define BITS_BT_EISR_EN_8822C \
+ (BIT_MASK_BT_EISR_EN_8822C << BIT_SHIFT_BT_EISR_EN_8822C)
+#define BIT_CLEAR_BT_EISR_EN_8822C(x) ((x) & (~BITS_BT_EISR_EN_8822C))
+#define BIT_GET_BT_EISR_EN_8822C(x) \
+ (((x) >> BIT_SHIFT_BT_EISR_EN_8822C) & BIT_MASK_BT_EISR_EN_8822C)
+#define BIT_SET_BT_EISR_EN_8822C(x, v) \
+ (BIT_CLEAR_BT_EISR_EN_8822C(x) | BIT_BT_EISR_EN_8822C(v))
+
+#define BIT_BT_ACT_FALLING_ISR_8822C BIT(10)
+#define BIT_BT_ACT_RISING_ISR_8822C BIT(9)
+#define BIT_TDMA_TO_ISR_8822C BIT(8)
+
+#define BIT_SHIFT_BT_CH_V1_8822C 0
+#define BIT_MASK_BT_CH_V1_8822C 0x7f
+#define BIT_BT_CH_V1_8822C(x) \
+ (((x) & BIT_MASK_BT_CH_V1_8822C) << BIT_SHIFT_BT_CH_V1_8822C)
+#define BITS_BT_CH_V1_8822C \
+ (BIT_MASK_BT_CH_V1_8822C << BIT_SHIFT_BT_CH_V1_8822C)
+#define BIT_CLEAR_BT_CH_V1_8822C(x) ((x) & (~BITS_BT_CH_V1_8822C))
+#define BIT_GET_BT_CH_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_BT_CH_V1_8822C) & BIT_MASK_BT_CH_V1_8822C)
+#define BIT_SET_BT_CH_V1_8822C(x, v) \
+ (BIT_CLEAR_BT_CH_V1_8822C(x) | BIT_BT_CH_V1_8822C(v))
+
+/* 2 REG_OBFF_CTRL_BASIC_8822C */
+#define BIT_OBFF_EN_V1_8822C BIT(31)
+
+#define BIT_SHIFT_OBFF_STATE_V1_8822C 28
+#define BIT_MASK_OBFF_STATE_V1_8822C 0x3
+#define BIT_OBFF_STATE_V1_8822C(x) \
+ (((x) & BIT_MASK_OBFF_STATE_V1_8822C) << BIT_SHIFT_OBFF_STATE_V1_8822C)
+#define BITS_OBFF_STATE_V1_8822C \
+ (BIT_MASK_OBFF_STATE_V1_8822C << BIT_SHIFT_OBFF_STATE_V1_8822C)
+#define BIT_CLEAR_OBFF_STATE_V1_8822C(x) ((x) & (~BITS_OBFF_STATE_V1_8822C))
+#define BIT_GET_OBFF_STATE_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_OBFF_STATE_V1_8822C) & BIT_MASK_OBFF_STATE_V1_8822C)
+#define BIT_SET_OBFF_STATE_V1_8822C(x, v) \
+ (BIT_CLEAR_OBFF_STATE_V1_8822C(x) | BIT_OBFF_STATE_V1_8822C(v))
+
+#define BIT_OBFF_ACT_RXDMA_EN_8822C BIT(27)
+#define BIT_OBFF_BLOCK_INT_EN_8822C BIT(26)
+#define BIT_OBFF_AUTOACT_EN_8822C BIT(25)
+#define BIT_OBFF_AUTOIDLE_EN_8822C BIT(24)
+
+#define BIT_SHIFT_WAKE_MAX_PLS_8822C 20
+#define BIT_MASK_WAKE_MAX_PLS_8822C 0x7
+#define BIT_WAKE_MAX_PLS_8822C(x) \
+ (((x) & BIT_MASK_WAKE_MAX_PLS_8822C) << BIT_SHIFT_WAKE_MAX_PLS_8822C)
+#define BITS_WAKE_MAX_PLS_8822C \
+ (BIT_MASK_WAKE_MAX_PLS_8822C << BIT_SHIFT_WAKE_MAX_PLS_8822C)
+#define BIT_CLEAR_WAKE_MAX_PLS_8822C(x) ((x) & (~BITS_WAKE_MAX_PLS_8822C))
+#define BIT_GET_WAKE_MAX_PLS_8822C(x) \
+ (((x) >> BIT_SHIFT_WAKE_MAX_PLS_8822C) & BIT_MASK_WAKE_MAX_PLS_8822C)
+#define BIT_SET_WAKE_MAX_PLS_8822C(x, v) \
+ (BIT_CLEAR_WAKE_MAX_PLS_8822C(x) | BIT_WAKE_MAX_PLS_8822C(v))
+
+#define BIT_SHIFT_WAKE_MIN_PLS_8822C 16
+#define BIT_MASK_WAKE_MIN_PLS_8822C 0x7
+#define BIT_WAKE_MIN_PLS_8822C(x) \
+ (((x) & BIT_MASK_WAKE_MIN_PLS_8822C) << BIT_SHIFT_WAKE_MIN_PLS_8822C)
+#define BITS_WAKE_MIN_PLS_8822C \
+ (BIT_MASK_WAKE_MIN_PLS_8822C << BIT_SHIFT_WAKE_MIN_PLS_8822C)
+#define BIT_CLEAR_WAKE_MIN_PLS_8822C(x) ((x) & (~BITS_WAKE_MIN_PLS_8822C))
+#define BIT_GET_WAKE_MIN_PLS_8822C(x) \
+ (((x) >> BIT_SHIFT_WAKE_MIN_PLS_8822C) & BIT_MASK_WAKE_MIN_PLS_8822C)
+#define BIT_SET_WAKE_MIN_PLS_8822C(x, v) \
+ (BIT_CLEAR_WAKE_MIN_PLS_8822C(x) | BIT_WAKE_MIN_PLS_8822C(v))
+
+#define BIT_SHIFT_WAKE_MAX_F2F_8822C 12
+#define BIT_MASK_WAKE_MAX_F2F_8822C 0x7
+#define BIT_WAKE_MAX_F2F_8822C(x) \
+ (((x) & BIT_MASK_WAKE_MAX_F2F_8822C) << BIT_SHIFT_WAKE_MAX_F2F_8822C)
+#define BITS_WAKE_MAX_F2F_8822C \
+ (BIT_MASK_WAKE_MAX_F2F_8822C << BIT_SHIFT_WAKE_MAX_F2F_8822C)
+#define BIT_CLEAR_WAKE_MAX_F2F_8822C(x) ((x) & (~BITS_WAKE_MAX_F2F_8822C))
+#define BIT_GET_WAKE_MAX_F2F_8822C(x) \
+ (((x) >> BIT_SHIFT_WAKE_MAX_F2F_8822C) & BIT_MASK_WAKE_MAX_F2F_8822C)
+#define BIT_SET_WAKE_MAX_F2F_8822C(x, v) \
+ (BIT_CLEAR_WAKE_MAX_F2F_8822C(x) | BIT_WAKE_MAX_F2F_8822C(v))
+
+#define BIT_SHIFT_WAKE_MIN_F2F_8822C 8
+#define BIT_MASK_WAKE_MIN_F2F_8822C 0x7
+#define BIT_WAKE_MIN_F2F_8822C(x) \
+ (((x) & BIT_MASK_WAKE_MIN_F2F_8822C) << BIT_SHIFT_WAKE_MIN_F2F_8822C)
+#define BITS_WAKE_MIN_F2F_8822C \
+ (BIT_MASK_WAKE_MIN_F2F_8822C << BIT_SHIFT_WAKE_MIN_F2F_8822C)
+#define BIT_CLEAR_WAKE_MIN_F2F_8822C(x) ((x) & (~BITS_WAKE_MIN_F2F_8822C))
+#define BIT_GET_WAKE_MIN_F2F_8822C(x) \
+ (((x) >> BIT_SHIFT_WAKE_MIN_F2F_8822C) & BIT_MASK_WAKE_MIN_F2F_8822C)
+#define BIT_SET_WAKE_MIN_F2F_8822C(x, v) \
+ (BIT_CLEAR_WAKE_MIN_F2F_8822C(x) | BIT_WAKE_MIN_F2F_8822C(v))
+
+#define BIT_APP_CPU_ACT_V1_8822C BIT(3)
+#define BIT_APP_OBFF_V1_8822C BIT(2)
+#define BIT_APP_IDLE_V1_8822C BIT(1)
+#define BIT_APP_INIT_V1_8822C BIT(0)
+
+/* 2 REG_OBFF_CTRL2_TIMER_8822C */
+
+#define BIT_SHIFT_RX_HIGH_TIMER_IDX_8822C 24
+#define BIT_MASK_RX_HIGH_TIMER_IDX_8822C 0x7
+#define BIT_RX_HIGH_TIMER_IDX_8822C(x) \
+ (((x) & BIT_MASK_RX_HIGH_TIMER_IDX_8822C) \
+ << BIT_SHIFT_RX_HIGH_TIMER_IDX_8822C)
+#define BITS_RX_HIGH_TIMER_IDX_8822C \
+ (BIT_MASK_RX_HIGH_TIMER_IDX_8822C << BIT_SHIFT_RX_HIGH_TIMER_IDX_8822C)
+#define BIT_CLEAR_RX_HIGH_TIMER_IDX_8822C(x) \
+ ((x) & (~BITS_RX_HIGH_TIMER_IDX_8822C))
+#define BIT_GET_RX_HIGH_TIMER_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8822C) & \
+ BIT_MASK_RX_HIGH_TIMER_IDX_8822C)
+#define BIT_SET_RX_HIGH_TIMER_IDX_8822C(x, v) \
+ (BIT_CLEAR_RX_HIGH_TIMER_IDX_8822C(x) | BIT_RX_HIGH_TIMER_IDX_8822C(v))
+
+#define BIT_SHIFT_RX_MED_TIMER_IDX_8822C 16
+#define BIT_MASK_RX_MED_TIMER_IDX_8822C 0x7
+#define BIT_RX_MED_TIMER_IDX_8822C(x) \
+ (((x) & BIT_MASK_RX_MED_TIMER_IDX_8822C) \
+ << BIT_SHIFT_RX_MED_TIMER_IDX_8822C)
+#define BITS_RX_MED_TIMER_IDX_8822C \
+ (BIT_MASK_RX_MED_TIMER_IDX_8822C << BIT_SHIFT_RX_MED_TIMER_IDX_8822C)
+#define BIT_CLEAR_RX_MED_TIMER_IDX_8822C(x) \
+ ((x) & (~BITS_RX_MED_TIMER_IDX_8822C))
+#define BIT_GET_RX_MED_TIMER_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8822C) & \
+ BIT_MASK_RX_MED_TIMER_IDX_8822C)
+#define BIT_SET_RX_MED_TIMER_IDX_8822C(x, v) \
+ (BIT_CLEAR_RX_MED_TIMER_IDX_8822C(x) | BIT_RX_MED_TIMER_IDX_8822C(v))
+
+#define BIT_SHIFT_RX_LOW_TIMER_IDX_8822C 8
+#define BIT_MASK_RX_LOW_TIMER_IDX_8822C 0x7
+#define BIT_RX_LOW_TIMER_IDX_8822C(x) \
+ (((x) & BIT_MASK_RX_LOW_TIMER_IDX_8822C) \
+ << BIT_SHIFT_RX_LOW_TIMER_IDX_8822C)
+#define BITS_RX_LOW_TIMER_IDX_8822C \
+ (BIT_MASK_RX_LOW_TIMER_IDX_8822C << BIT_SHIFT_RX_LOW_TIMER_IDX_8822C)
+#define BIT_CLEAR_RX_LOW_TIMER_IDX_8822C(x) \
+ ((x) & (~BITS_RX_LOW_TIMER_IDX_8822C))
+#define BIT_GET_RX_LOW_TIMER_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8822C) & \
+ BIT_MASK_RX_LOW_TIMER_IDX_8822C)
+#define BIT_SET_RX_LOW_TIMER_IDX_8822C(x, v) \
+ (BIT_CLEAR_RX_LOW_TIMER_IDX_8822C(x) | BIT_RX_LOW_TIMER_IDX_8822C(v))
+
+#define BIT_SHIFT_OBFF_INT_TIMER_IDX_8822C 0
+#define BIT_MASK_OBFF_INT_TIMER_IDX_8822C 0x7
+#define BIT_OBFF_INT_TIMER_IDX_8822C(x) \
+ (((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8822C) \
+ << BIT_SHIFT_OBFF_INT_TIMER_IDX_8822C)
+#define BITS_OBFF_INT_TIMER_IDX_8822C \
+ (BIT_MASK_OBFF_INT_TIMER_IDX_8822C \
+ << BIT_SHIFT_OBFF_INT_TIMER_IDX_8822C)
+#define BIT_CLEAR_OBFF_INT_TIMER_IDX_8822C(x) \
+ ((x) & (~BITS_OBFF_INT_TIMER_IDX_8822C))
+#define BIT_GET_OBFF_INT_TIMER_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8822C) & \
+ BIT_MASK_OBFF_INT_TIMER_IDX_8822C)
+#define BIT_SET_OBFF_INT_TIMER_IDX_8822C(x, v) \
+ (BIT_CLEAR_OBFF_INT_TIMER_IDX_8822C(x) | \
+ BIT_OBFF_INT_TIMER_IDX_8822C(v))
+
+/* 2 REG_LTR_CTRL_BASIC_8822C */
+#define BIT_LTR_EN_V1_8822C BIT(31)
+#define BIT_LTR_HW_EN_V1_8822C BIT(30)
+#define BIT_LRT_ACT_CTS_EN_8822C BIT(29)
+#define BIT_LTR_ACT_RXPKT_EN_8822C BIT(28)
+#define BIT_LTR_ACT_RXDMA_EN_8822C BIT(27)
+#define BIT_LTR_IDLE_NO_SNOOP_8822C BIT(26)
+#define BIT_SPDUP_MGTPKT_8822C BIT(25)
+#define BIT_RX_AGG_EN_8822C BIT(24)
+#define BIT_APP_LTR_ACT_8822C BIT(23)
+#define BIT_APP_LTR_IDLE_8822C BIT(22)
+
+#define BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822C 20
+#define BIT_MASK_HIGH_RATE_TRIG_SEL_8822C 0x3
+#define BIT_HIGH_RATE_TRIG_SEL_8822C(x) \
+ (((x) & BIT_MASK_HIGH_RATE_TRIG_SEL_8822C) \
+ << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822C)
+#define BITS_HIGH_RATE_TRIG_SEL_8822C \
+ (BIT_MASK_HIGH_RATE_TRIG_SEL_8822C \
+ << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822C)
+#define BIT_CLEAR_HIGH_RATE_TRIG_SEL_8822C(x) \
+ ((x) & (~BITS_HIGH_RATE_TRIG_SEL_8822C))
+#define BIT_GET_HIGH_RATE_TRIG_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8822C) & \
+ BIT_MASK_HIGH_RATE_TRIG_SEL_8822C)
+#define BIT_SET_HIGH_RATE_TRIG_SEL_8822C(x, v) \
+ (BIT_CLEAR_HIGH_RATE_TRIG_SEL_8822C(x) | \
+ BIT_HIGH_RATE_TRIG_SEL_8822C(v))
+
+#define BIT_SHIFT_MED_RATE_TRIG_SEL_8822C 18
+#define BIT_MASK_MED_RATE_TRIG_SEL_8822C 0x3
+#define BIT_MED_RATE_TRIG_SEL_8822C(x) \
+ (((x) & BIT_MASK_MED_RATE_TRIG_SEL_8822C) \
+ << BIT_SHIFT_MED_RATE_TRIG_SEL_8822C)
+#define BITS_MED_RATE_TRIG_SEL_8822C \
+ (BIT_MASK_MED_RATE_TRIG_SEL_8822C << BIT_SHIFT_MED_RATE_TRIG_SEL_8822C)
+#define BIT_CLEAR_MED_RATE_TRIG_SEL_8822C(x) \
+ ((x) & (~BITS_MED_RATE_TRIG_SEL_8822C))
+#define BIT_GET_MED_RATE_TRIG_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8822C) & \
+ BIT_MASK_MED_RATE_TRIG_SEL_8822C)
+#define BIT_SET_MED_RATE_TRIG_SEL_8822C(x, v) \
+ (BIT_CLEAR_MED_RATE_TRIG_SEL_8822C(x) | BIT_MED_RATE_TRIG_SEL_8822C(v))
+
+#define BIT_SHIFT_LOW_RATE_TRIG_SEL_8822C 16
+#define BIT_MASK_LOW_RATE_TRIG_SEL_8822C 0x3
+#define BIT_LOW_RATE_TRIG_SEL_8822C(x) \
+ (((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8822C) \
+ << BIT_SHIFT_LOW_RATE_TRIG_SEL_8822C)
+#define BITS_LOW_RATE_TRIG_SEL_8822C \
+ (BIT_MASK_LOW_RATE_TRIG_SEL_8822C << BIT_SHIFT_LOW_RATE_TRIG_SEL_8822C)
+#define BIT_CLEAR_LOW_RATE_TRIG_SEL_8822C(x) \
+ ((x) & (~BITS_LOW_RATE_TRIG_SEL_8822C))
+#define BIT_GET_LOW_RATE_TRIG_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8822C) & \
+ BIT_MASK_LOW_RATE_TRIG_SEL_8822C)
+#define BIT_SET_LOW_RATE_TRIG_SEL_8822C(x, v) \
+ (BIT_CLEAR_LOW_RATE_TRIG_SEL_8822C(x) | BIT_LOW_RATE_TRIG_SEL_8822C(v))
+
+#define BIT_SHIFT_HIGH_RATE_BD_IDX_8822C 8
+#define BIT_MASK_HIGH_RATE_BD_IDX_8822C 0x7f
+#define BIT_HIGH_RATE_BD_IDX_8822C(x) \
+ (((x) & BIT_MASK_HIGH_RATE_BD_IDX_8822C) \
+ << BIT_SHIFT_HIGH_RATE_BD_IDX_8822C)
+#define BITS_HIGH_RATE_BD_IDX_8822C \
+ (BIT_MASK_HIGH_RATE_BD_IDX_8822C << BIT_SHIFT_HIGH_RATE_BD_IDX_8822C)
+#define BIT_CLEAR_HIGH_RATE_BD_IDX_8822C(x) \
+ ((x) & (~BITS_HIGH_RATE_BD_IDX_8822C))
+#define BIT_GET_HIGH_RATE_BD_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8822C) & \
+ BIT_MASK_HIGH_RATE_BD_IDX_8822C)
+#define BIT_SET_HIGH_RATE_BD_IDX_8822C(x, v) \
+ (BIT_CLEAR_HIGH_RATE_BD_IDX_8822C(x) | BIT_HIGH_RATE_BD_IDX_8822C(v))
+
+#define BIT_SHIFT_LOW_RATE_BD_IDX_8822C 0
+#define BIT_MASK_LOW_RATE_BD_IDX_8822C 0x7f
+#define BIT_LOW_RATE_BD_IDX_8822C(x) \
+ (((x) & BIT_MASK_LOW_RATE_BD_IDX_8822C) \
+ << BIT_SHIFT_LOW_RATE_BD_IDX_8822C)
+#define BITS_LOW_RATE_BD_IDX_8822C \
+ (BIT_MASK_LOW_RATE_BD_IDX_8822C << BIT_SHIFT_LOW_RATE_BD_IDX_8822C)
+#define BIT_CLEAR_LOW_RATE_BD_IDX_8822C(x) ((x) & (~BITS_LOW_RATE_BD_IDX_8822C))
+#define BIT_GET_LOW_RATE_BD_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8822C) & \
+ BIT_MASK_LOW_RATE_BD_IDX_8822C)
+#define BIT_SET_LOW_RATE_BD_IDX_8822C(x, v) \
+ (BIT_CLEAR_LOW_RATE_BD_IDX_8822C(x) | BIT_LOW_RATE_BD_IDX_8822C(v))
+
+/* 2 REG_LTR_CTRL2_TIMER_THRESHOLD_8822C */
+
+#define BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822C 24
+#define BIT_MASK_RX_EMPTY_TIMER_IDX_8822C 0x7
+#define BIT_RX_EMPTY_TIMER_IDX_8822C(x) \
+ (((x) & BIT_MASK_RX_EMPTY_TIMER_IDX_8822C) \
+ << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822C)
+#define BITS_RX_EMPTY_TIMER_IDX_8822C \
+ (BIT_MASK_RX_EMPTY_TIMER_IDX_8822C \
+ << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822C)
+#define BIT_CLEAR_RX_EMPTY_TIMER_IDX_8822C(x) \
+ ((x) & (~BITS_RX_EMPTY_TIMER_IDX_8822C))
+#define BIT_GET_RX_EMPTY_TIMER_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8822C) & \
+ BIT_MASK_RX_EMPTY_TIMER_IDX_8822C)
+#define BIT_SET_RX_EMPTY_TIMER_IDX_8822C(x, v) \
+ (BIT_CLEAR_RX_EMPTY_TIMER_IDX_8822C(x) | \
+ BIT_RX_EMPTY_TIMER_IDX_8822C(v))
+
+#define BIT_SHIFT_RX_AFULL_TH_IDX_8822C 20
+#define BIT_MASK_RX_AFULL_TH_IDX_8822C 0x7
+#define BIT_RX_AFULL_TH_IDX_8822C(x) \
+ (((x) & BIT_MASK_RX_AFULL_TH_IDX_8822C) \
+ << BIT_SHIFT_RX_AFULL_TH_IDX_8822C)
+#define BITS_RX_AFULL_TH_IDX_8822C \
+ (BIT_MASK_RX_AFULL_TH_IDX_8822C << BIT_SHIFT_RX_AFULL_TH_IDX_8822C)
+#define BIT_CLEAR_RX_AFULL_TH_IDX_8822C(x) ((x) & (~BITS_RX_AFULL_TH_IDX_8822C))
+#define BIT_GET_RX_AFULL_TH_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8822C) & \
+ BIT_MASK_RX_AFULL_TH_IDX_8822C)
+#define BIT_SET_RX_AFULL_TH_IDX_8822C(x, v) \
+ (BIT_CLEAR_RX_AFULL_TH_IDX_8822C(x) | BIT_RX_AFULL_TH_IDX_8822C(v))
+
+#define BIT_SHIFT_RX_HIGH_TH_IDX_8822C 16
+#define BIT_MASK_RX_HIGH_TH_IDX_8822C 0x7
+#define BIT_RX_HIGH_TH_IDX_8822C(x) \
+ (((x) & BIT_MASK_RX_HIGH_TH_IDX_8822C) \
+ << BIT_SHIFT_RX_HIGH_TH_IDX_8822C)
+#define BITS_RX_HIGH_TH_IDX_8822C \
+ (BIT_MASK_RX_HIGH_TH_IDX_8822C << BIT_SHIFT_RX_HIGH_TH_IDX_8822C)
+#define BIT_CLEAR_RX_HIGH_TH_IDX_8822C(x) ((x) & (~BITS_RX_HIGH_TH_IDX_8822C))
+#define BIT_GET_RX_HIGH_TH_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8822C) & \
+ BIT_MASK_RX_HIGH_TH_IDX_8822C)
+#define BIT_SET_RX_HIGH_TH_IDX_8822C(x, v) \
+ (BIT_CLEAR_RX_HIGH_TH_IDX_8822C(x) | BIT_RX_HIGH_TH_IDX_8822C(v))
+
+#define BIT_SHIFT_RX_MED_TH_IDX_8822C 12
+#define BIT_MASK_RX_MED_TH_IDX_8822C 0x7
+#define BIT_RX_MED_TH_IDX_8822C(x) \
+ (((x) & BIT_MASK_RX_MED_TH_IDX_8822C) << BIT_SHIFT_RX_MED_TH_IDX_8822C)
+#define BITS_RX_MED_TH_IDX_8822C \
+ (BIT_MASK_RX_MED_TH_IDX_8822C << BIT_SHIFT_RX_MED_TH_IDX_8822C)
+#define BIT_CLEAR_RX_MED_TH_IDX_8822C(x) ((x) & (~BITS_RX_MED_TH_IDX_8822C))
+#define BIT_GET_RX_MED_TH_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_RX_MED_TH_IDX_8822C) & BIT_MASK_RX_MED_TH_IDX_8822C)
+#define BIT_SET_RX_MED_TH_IDX_8822C(x, v) \
+ (BIT_CLEAR_RX_MED_TH_IDX_8822C(x) | BIT_RX_MED_TH_IDX_8822C(v))
+
+#define BIT_SHIFT_RX_LOW_TH_IDX_8822C 8
+#define BIT_MASK_RX_LOW_TH_IDX_8822C 0x7
+#define BIT_RX_LOW_TH_IDX_8822C(x) \
+ (((x) & BIT_MASK_RX_LOW_TH_IDX_8822C) << BIT_SHIFT_RX_LOW_TH_IDX_8822C)
+#define BITS_RX_LOW_TH_IDX_8822C \
+ (BIT_MASK_RX_LOW_TH_IDX_8822C << BIT_SHIFT_RX_LOW_TH_IDX_8822C)
+#define BIT_CLEAR_RX_LOW_TH_IDX_8822C(x) ((x) & (~BITS_RX_LOW_TH_IDX_8822C))
+#define BIT_GET_RX_LOW_TH_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8822C) & BIT_MASK_RX_LOW_TH_IDX_8822C)
+#define BIT_SET_RX_LOW_TH_IDX_8822C(x, v) \
+ (BIT_CLEAR_RX_LOW_TH_IDX_8822C(x) | BIT_RX_LOW_TH_IDX_8822C(v))
+
+#define BIT_SHIFT_LTR_SPACE_IDX_8822C 4
+#define BIT_MASK_LTR_SPACE_IDX_8822C 0x3
+#define BIT_LTR_SPACE_IDX_8822C(x) \
+ (((x) & BIT_MASK_LTR_SPACE_IDX_8822C) << BIT_SHIFT_LTR_SPACE_IDX_8822C)
+#define BITS_LTR_SPACE_IDX_8822C \
+ (BIT_MASK_LTR_SPACE_IDX_8822C << BIT_SHIFT_LTR_SPACE_IDX_8822C)
+#define BIT_CLEAR_LTR_SPACE_IDX_8822C(x) ((x) & (~BITS_LTR_SPACE_IDX_8822C))
+#define BIT_GET_LTR_SPACE_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_LTR_SPACE_IDX_8822C) & BIT_MASK_LTR_SPACE_IDX_8822C)
+#define BIT_SET_LTR_SPACE_IDX_8822C(x, v) \
+ (BIT_CLEAR_LTR_SPACE_IDX_8822C(x) | BIT_LTR_SPACE_IDX_8822C(v))
+
+#define BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822C 0
+#define BIT_MASK_LTR_IDLE_TIMER_IDX_8822C 0x7
+#define BIT_LTR_IDLE_TIMER_IDX_8822C(x) \
+ (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8822C) \
+ << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822C)
+#define BITS_LTR_IDLE_TIMER_IDX_8822C \
+ (BIT_MASK_LTR_IDLE_TIMER_IDX_8822C \
+ << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822C)
+#define BIT_CLEAR_LTR_IDLE_TIMER_IDX_8822C(x) \
+ ((x) & (~BITS_LTR_IDLE_TIMER_IDX_8822C))
+#define BIT_GET_LTR_IDLE_TIMER_IDX_8822C(x) \
+ (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8822C) & \
+ BIT_MASK_LTR_IDLE_TIMER_IDX_8822C)
+#define BIT_SET_LTR_IDLE_TIMER_IDX_8822C(x, v) \
+ (BIT_CLEAR_LTR_IDLE_TIMER_IDX_8822C(x) | \
+ BIT_LTR_IDLE_TIMER_IDX_8822C(v))
+
+/* 2 REG_LTR_IDLE_LATENCY_V1_8822C */
+
+#define BIT_SHIFT_LTR_IDLE_L_8822C 0
+#define BIT_MASK_LTR_IDLE_L_8822C 0xffffffffL
+#define BIT_LTR_IDLE_L_8822C(x) \
+ (((x) & BIT_MASK_LTR_IDLE_L_8822C) << BIT_SHIFT_LTR_IDLE_L_8822C)
+#define BITS_LTR_IDLE_L_8822C \
+ (BIT_MASK_LTR_IDLE_L_8822C << BIT_SHIFT_LTR_IDLE_L_8822C)
+#define BIT_CLEAR_LTR_IDLE_L_8822C(x) ((x) & (~BITS_LTR_IDLE_L_8822C))
+#define BIT_GET_LTR_IDLE_L_8822C(x) \
+ (((x) >> BIT_SHIFT_LTR_IDLE_L_8822C) & BIT_MASK_LTR_IDLE_L_8822C)
+#define BIT_SET_LTR_IDLE_L_8822C(x, v) \
+ (BIT_CLEAR_LTR_IDLE_L_8822C(x) | BIT_LTR_IDLE_L_8822C(v))
+
+/* 2 REG_LTR_ACTIVE_LATENCY_V1_8822C */
+
+#define BIT_SHIFT_LTR_ACT_L_8822C 0
+#define BIT_MASK_LTR_ACT_L_8822C 0xffffffffL
+#define BIT_LTR_ACT_L_8822C(x) \
+ (((x) & BIT_MASK_LTR_ACT_L_8822C) << BIT_SHIFT_LTR_ACT_L_8822C)
+#define BITS_LTR_ACT_L_8822C \
+ (BIT_MASK_LTR_ACT_L_8822C << BIT_SHIFT_LTR_ACT_L_8822C)
+#define BIT_CLEAR_LTR_ACT_L_8822C(x) ((x) & (~BITS_LTR_ACT_L_8822C))
+#define BIT_GET_LTR_ACT_L_8822C(x) \
+ (((x) >> BIT_SHIFT_LTR_ACT_L_8822C) & BIT_MASK_LTR_ACT_L_8822C)
+#define BIT_SET_LTR_ACT_L_8822C(x, v) \
+ (BIT_CLEAR_LTR_ACT_L_8822C(x) | BIT_LTR_ACT_L_8822C(v))
+
+/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_8822C */
+
+#define BIT_SHIFT_TRAIN_STA_ADDR_0_8822C 0
+#define BIT_MASK_TRAIN_STA_ADDR_0_8822C 0xffffffffL
+#define BIT_TRAIN_STA_ADDR_0_8822C(x) \
+ (((x) & BIT_MASK_TRAIN_STA_ADDR_0_8822C) \
+ << BIT_SHIFT_TRAIN_STA_ADDR_0_8822C)
+#define BITS_TRAIN_STA_ADDR_0_8822C \
+ (BIT_MASK_TRAIN_STA_ADDR_0_8822C << BIT_SHIFT_TRAIN_STA_ADDR_0_8822C)
+#define BIT_CLEAR_TRAIN_STA_ADDR_0_8822C(x) \
+ ((x) & (~BITS_TRAIN_STA_ADDR_0_8822C))
+#define BIT_GET_TRAIN_STA_ADDR_0_8822C(x) \
+ (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_0_8822C) & \
+ BIT_MASK_TRAIN_STA_ADDR_0_8822C)
+#define BIT_SET_TRAIN_STA_ADDR_0_8822C(x, v) \
+ (BIT_CLEAR_TRAIN_STA_ADDR_0_8822C(x) | BIT_TRAIN_STA_ADDR_0_8822C(v))
+
+/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_1_8822C */
+#define BIT_ANTTRN_SWITCH_8822C BIT(19)
+#define BIT_APPEND_MACID_IN_RESP_EN_1_8822C BIT(18)
+#define BIT_ADDR2_MATCH_EN_1_8822C BIT(17)
+#define BIT_ANTTRN_EN_1_8822C BIT(16)
+
+#define BIT_SHIFT_TRAIN_STA_ADDR_1_8822C 0
+#define BIT_MASK_TRAIN_STA_ADDR_1_8822C 0xffff
+#define BIT_TRAIN_STA_ADDR_1_8822C(x) \
+ (((x) & BIT_MASK_TRAIN_STA_ADDR_1_8822C) \
+ << BIT_SHIFT_TRAIN_STA_ADDR_1_8822C)
+#define BITS_TRAIN_STA_ADDR_1_8822C \
+ (BIT_MASK_TRAIN_STA_ADDR_1_8822C << BIT_SHIFT_TRAIN_STA_ADDR_1_8822C)
+#define BIT_CLEAR_TRAIN_STA_ADDR_1_8822C(x) \
+ ((x) & (~BITS_TRAIN_STA_ADDR_1_8822C))
+#define BIT_GET_TRAIN_STA_ADDR_1_8822C(x) \
+ (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_1_8822C) & \
+ BIT_MASK_TRAIN_STA_ADDR_1_8822C)
+#define BIT_SET_TRAIN_STA_ADDR_1_8822C(x, v) \
+ (BIT_CLEAR_TRAIN_STA_ADDR_1_8822C(x) | BIT_TRAIN_STA_ADDR_1_8822C(v))
+
+/* 2 REG_WMAC_PKTCNT_RWD_8822C */
+
+#define BIT_SHIFT_PKTCNT_BSSIDMAP_8822C 4
+#define BIT_MASK_PKTCNT_BSSIDMAP_8822C 0xf
+#define BIT_PKTCNT_BSSIDMAP_8822C(x) \
+ (((x) & BIT_MASK_PKTCNT_BSSIDMAP_8822C) \
+ << BIT_SHIFT_PKTCNT_BSSIDMAP_8822C)
+#define BITS_PKTCNT_BSSIDMAP_8822C \
+ (BIT_MASK_PKTCNT_BSSIDMAP_8822C << BIT_SHIFT_PKTCNT_BSSIDMAP_8822C)
+#define BIT_CLEAR_PKTCNT_BSSIDMAP_8822C(x) ((x) & (~BITS_PKTCNT_BSSIDMAP_8822C))
+#define BIT_GET_PKTCNT_BSSIDMAP_8822C(x) \
+ (((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP_8822C) & \
+ BIT_MASK_PKTCNT_BSSIDMAP_8822C)
+#define BIT_SET_PKTCNT_BSSIDMAP_8822C(x, v) \
+ (BIT_CLEAR_PKTCNT_BSSIDMAP_8822C(x) | BIT_PKTCNT_BSSIDMAP_8822C(v))
+
+#define BIT_PKTCNT_CNTRST_8822C BIT(1)
+#define BIT_PKTCNT_CNTEN_8822C BIT(0)
+
+/* 2 REG_WMAC_PKTCNT_CTRL_8822C */
+#define BIT_WMAC_PKTCNT_TRST_8822C BIT(9)
+#define BIT_WMAC_PKTCNT_FEN_8822C BIT(8)
+
+#define BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822C 0
+#define BIT_MASK_WMAC_PKTCNT_CFGAD_8822C 0xff
+#define BIT_WMAC_PKTCNT_CFGAD_8822C(x) \
+ (((x) & BIT_MASK_WMAC_PKTCNT_CFGAD_8822C) \
+ << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822C)
+#define BITS_WMAC_PKTCNT_CFGAD_8822C \
+ (BIT_MASK_WMAC_PKTCNT_CFGAD_8822C << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822C)
+#define BIT_CLEAR_WMAC_PKTCNT_CFGAD_8822C(x) \
+ ((x) & (~BITS_WMAC_PKTCNT_CFGAD_8822C))
+#define BIT_GET_WMAC_PKTCNT_CFGAD_8822C(x) \
+ (((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD_8822C) & \
+ BIT_MASK_WMAC_PKTCNT_CFGAD_8822C)
+#define BIT_SET_WMAC_PKTCNT_CFGAD_8822C(x, v) \
+ (BIT_CLEAR_WMAC_PKTCNT_CFGAD_8822C(x) | BIT_WMAC_PKTCNT_CFGAD_8822C(v))
+
+/* 2 REG_IQ_DUMP_8822C */
+
+#define BIT_SHIFT_DUMP_OK_ADDR_8822C 16
+#define BIT_MASK_DUMP_OK_ADDR_8822C 0xffff
+#define BIT_DUMP_OK_ADDR_8822C(x) \
+ (((x) & BIT_MASK_DUMP_OK_ADDR_8822C) << BIT_SHIFT_DUMP_OK_ADDR_8822C)
+#define BITS_DUMP_OK_ADDR_8822C \
+ (BIT_MASK_DUMP_OK_ADDR_8822C << BIT_SHIFT_DUMP_OK_ADDR_8822C)
+#define BIT_CLEAR_DUMP_OK_ADDR_8822C(x) ((x) & (~BITS_DUMP_OK_ADDR_8822C))
+#define BIT_GET_DUMP_OK_ADDR_8822C(x) \
+ (((x) >> BIT_SHIFT_DUMP_OK_ADDR_8822C) & BIT_MASK_DUMP_OK_ADDR_8822C)
+#define BIT_SET_DUMP_OK_ADDR_8822C(x, v) \
+ (BIT_CLEAR_DUMP_OK_ADDR_8822C(x) | BIT_DUMP_OK_ADDR_8822C(v))
+
+#define BIT_MACDBG_TRIG_IQDUMP_8822C BIT(15)
+
+#define BIT_SHIFT_R_TRIG_TIME_SEL_8822C 8
+#define BIT_MASK_R_TRIG_TIME_SEL_8822C 0x7f
+#define BIT_R_TRIG_TIME_SEL_8822C(x) \
+ (((x) & BIT_MASK_R_TRIG_TIME_SEL_8822C) \
+ << BIT_SHIFT_R_TRIG_TIME_SEL_8822C)
+#define BITS_R_TRIG_TIME_SEL_8822C \
+ (BIT_MASK_R_TRIG_TIME_SEL_8822C << BIT_SHIFT_R_TRIG_TIME_SEL_8822C)
+#define BIT_CLEAR_R_TRIG_TIME_SEL_8822C(x) ((x) & (~BITS_R_TRIG_TIME_SEL_8822C))
+#define BIT_GET_R_TRIG_TIME_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8822C) & \
+ BIT_MASK_R_TRIG_TIME_SEL_8822C)
+#define BIT_SET_R_TRIG_TIME_SEL_8822C(x, v) \
+ (BIT_CLEAR_R_TRIG_TIME_SEL_8822C(x) | BIT_R_TRIG_TIME_SEL_8822C(v))
+
+#define BIT_SHIFT_R_MAC_TRIG_SEL_8822C 6
+#define BIT_MASK_R_MAC_TRIG_SEL_8822C 0x3
+#define BIT_R_MAC_TRIG_SEL_8822C(x) \
+ (((x) & BIT_MASK_R_MAC_TRIG_SEL_8822C) \
+ << BIT_SHIFT_R_MAC_TRIG_SEL_8822C)
+#define BITS_R_MAC_TRIG_SEL_8822C \
+ (BIT_MASK_R_MAC_TRIG_SEL_8822C << BIT_SHIFT_R_MAC_TRIG_SEL_8822C)
+#define BIT_CLEAR_R_MAC_TRIG_SEL_8822C(x) ((x) & (~BITS_R_MAC_TRIG_SEL_8822C))
+#define BIT_GET_R_MAC_TRIG_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8822C) & \
+ BIT_MASK_R_MAC_TRIG_SEL_8822C)
+#define BIT_SET_R_MAC_TRIG_SEL_8822C(x, v) \
+ (BIT_CLEAR_R_MAC_TRIG_SEL_8822C(x) | BIT_R_MAC_TRIG_SEL_8822C(v))
+
+#define BIT_MAC_TRIG_REG_8822C BIT(5)
+
+#define BIT_SHIFT_R_LEVEL_PULSE_SEL_8822C 3
+#define BIT_MASK_R_LEVEL_PULSE_SEL_8822C 0x3
+#define BIT_R_LEVEL_PULSE_SEL_8822C(x) \
+ (((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8822C) \
+ << BIT_SHIFT_R_LEVEL_PULSE_SEL_8822C)
+#define BITS_R_LEVEL_PULSE_SEL_8822C \
+ (BIT_MASK_R_LEVEL_PULSE_SEL_8822C << BIT_SHIFT_R_LEVEL_PULSE_SEL_8822C)
+#define BIT_CLEAR_R_LEVEL_PULSE_SEL_8822C(x) \
+ ((x) & (~BITS_R_LEVEL_PULSE_SEL_8822C))
+#define BIT_GET_R_LEVEL_PULSE_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8822C) & \
+ BIT_MASK_R_LEVEL_PULSE_SEL_8822C)
+#define BIT_SET_R_LEVEL_PULSE_SEL_8822C(x, v) \
+ (BIT_CLEAR_R_LEVEL_PULSE_SEL_8822C(x) | BIT_R_LEVEL_PULSE_SEL_8822C(v))
+
+#define BIT_EN_LA_MAC_8822C BIT(2)
+#define BIT_R_EN_IQDUMP_8822C BIT(1)
+#define BIT_R_IQDATA_DUMP_8822C BIT(0)
+
+/* 2 REG_IQ_DUMP_1_8822C */
+
+#define BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8822C 0
+#define BIT_MASK_R_WMAC_MASK_LA_MAC_1_8822C 0xffffffffL
+#define BIT_R_WMAC_MASK_LA_MAC_1_8822C(x) \
+ (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_1_8822C) \
+ << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8822C)
+#define BITS_R_WMAC_MASK_LA_MAC_1_8822C \
+ (BIT_MASK_R_WMAC_MASK_LA_MAC_1_8822C \
+ << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8822C)
+#define BIT_CLEAR_R_WMAC_MASK_LA_MAC_1_8822C(x) \
+ ((x) & (~BITS_R_WMAC_MASK_LA_MAC_1_8822C))
+#define BIT_GET_R_WMAC_MASK_LA_MAC_1_8822C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8822C) & \
+ BIT_MASK_R_WMAC_MASK_LA_MAC_1_8822C)
+#define BIT_SET_R_WMAC_MASK_LA_MAC_1_8822C(x, v) \
+ (BIT_CLEAR_R_WMAC_MASK_LA_MAC_1_8822C(x) | \
+ BIT_R_WMAC_MASK_LA_MAC_1_8822C(v))
+
+/* 2 REG_IQ_DUMP_2_8822C */
+
+#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8822C 0
+#define BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8822C 0xffffffffL
+#define BIT_R_WMAC_MATCH_REF_MAC_2_8822C(x) \
+ (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8822C) \
+ << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8822C)
+#define BITS_R_WMAC_MATCH_REF_MAC_2_8822C \
+ (BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8822C \
+ << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8822C)
+#define BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2_8822C(x) \
+ ((x) & (~BITS_R_WMAC_MATCH_REF_MAC_2_8822C))
+#define BIT_GET_R_WMAC_MATCH_REF_MAC_2_8822C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8822C) & \
+ BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8822C)
+#define BIT_SET_R_WMAC_MATCH_REF_MAC_2_8822C(x, v) \
+ (BIT_CLEAR_R_WMAC_MATCH_REF_MAC_2_8822C(x) | \
+ BIT_R_WMAC_MATCH_REF_MAC_2_8822C(v))
+
+/* 2 REG_WMAC_FTM_CTL_8822C */
+#define BIT_RXFTM_TXACK_SC_8822C BIT(6)
+#define BIT_RXFTM_TXACK_BW_8822C BIT(5)
+#define BIT_RXFTM_EN_8822C BIT(3)
+#define BIT_RXFTMREQ_BYDRV_8822C BIT(2)
+#define BIT_RXFTMREQ_EN_8822C BIT(1)
+#define BIT_FTM_EN_8822C BIT(0)
+
+/* 2 REG_WMAC_IQ_MDPK_FUNC_8822C */
+
+/* 2 REG_WMAC_OPTION_FUNCTION_8822C */
+
+#define BIT_SHIFT_R_OFDM_LEN_V1_8822C 16
+#define BIT_MASK_R_OFDM_LEN_V1_8822C 0xffff
+#define BIT_R_OFDM_LEN_V1_8822C(x) \
+ (((x) & BIT_MASK_R_OFDM_LEN_V1_8822C) << BIT_SHIFT_R_OFDM_LEN_V1_8822C)
+#define BITS_R_OFDM_LEN_V1_8822C \
+ (BIT_MASK_R_OFDM_LEN_V1_8822C << BIT_SHIFT_R_OFDM_LEN_V1_8822C)
+#define BIT_CLEAR_R_OFDM_LEN_V1_8822C(x) ((x) & (~BITS_R_OFDM_LEN_V1_8822C))
+#define BIT_GET_R_OFDM_LEN_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_R_OFDM_LEN_V1_8822C) & BIT_MASK_R_OFDM_LEN_V1_8822C)
+#define BIT_SET_R_OFDM_LEN_V1_8822C(x, v) \
+ (BIT_CLEAR_R_OFDM_LEN_V1_8822C(x) | BIT_R_OFDM_LEN_V1_8822C(v))
+
+#define BIT_SHIFT_R_CCK_LEN_8822C 0
+#define BIT_MASK_R_CCK_LEN_8822C 0xffff
+#define BIT_R_CCK_LEN_8822C(x) \
+ (((x) & BIT_MASK_R_CCK_LEN_8822C) << BIT_SHIFT_R_CCK_LEN_8822C)
+#define BITS_R_CCK_LEN_8822C \
+ (BIT_MASK_R_CCK_LEN_8822C << BIT_SHIFT_R_CCK_LEN_8822C)
+#define BIT_CLEAR_R_CCK_LEN_8822C(x) ((x) & (~BITS_R_CCK_LEN_8822C))
+#define BIT_GET_R_CCK_LEN_8822C(x) \
+ (((x) >> BIT_SHIFT_R_CCK_LEN_8822C) & BIT_MASK_R_CCK_LEN_8822C)
+#define BIT_SET_R_CCK_LEN_8822C(x, v) \
+ (BIT_CLEAR_R_CCK_LEN_8822C(x) | BIT_R_CCK_LEN_8822C(v))
+
+/* 2 REG_WMAC_OPTION_FUNCTION_1_8822C */
+
+#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8822C 24
+#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8822C 0xff
+#define BIT_R_WMAC_RXFIFO_FULL_TH_1_8822C(x) \
+ (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8822C) \
+ << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8822C)
+#define BITS_R_WMAC_RXFIFO_FULL_TH_1_8822C \
+ (BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8822C \
+ << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8822C)
+#define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1_8822C(x) \
+ ((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH_1_8822C))
+#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_1_8822C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8822C) & \
+ BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8822C)
+#define BIT_SET_R_WMAC_RXFIFO_FULL_TH_1_8822C(x, v) \
+ (BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1_8822C(x) | \
+ BIT_R_WMAC_RXFIFO_FULL_TH_1_8822C(v))
+
+#define BIT_R_WMAC_RX_SYNCFIFO_SYNC_1_8822C BIT(23)
+#define BIT_R_WMAC_RXRST_DLY_1_8822C BIT(22)
+#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP_1_8822C BIT(21)
+#define BIT_R_WMAC_SRCH_TXRPT_UA1_1_8822C BIT(20)
+#define BIT_R_WMAC_SRCH_TXRPT_TYPE_1_8822C BIT(19)
+#define BIT_R_WMAC_NDP_RST_1_8822C BIT(18)
+#define BIT_R_WMAC_POWINT_EN_1_8822C BIT(17)
+#define BIT_R_WMAC_SRCH_TXRPT_PERPKT_1_8822C BIT(16)
+#define BIT_R_WMAC_SRCH_TXRPT_MID_1_8822C BIT(15)
+#define BIT_R_WMAC_PFIN_TOEN_1_8822C BIT(14)
+#define BIT_R_WMAC_FIL_SECERR_1_8822C BIT(13)
+#define BIT_R_WMAC_FIL_CTLPKTLEN_1_8822C BIT(12)
+#define BIT_R_WMAC_FIL_FCTYPE_1_8822C BIT(11)
+#define BIT_R_WMAC_FIL_FCPROVER_1_8822C BIT(10)
+#define BIT_R_WMAC_PHYSTS_SNIF_1_8822C BIT(9)
+#define BIT_R_WMAC_PHYSTS_PLCP_1_8822C BIT(8)
+#define BIT_R_MAC_TCR_VBONF_RD_1_8822C BIT(7)
+#define BIT_R_WMAC_TCR_MPAR_NDP_1_8822C BIT(6)
+#define BIT_R_WMAC_NDP_FILTER_1_8822C BIT(5)
+#define BIT_R_WMAC_RXLEN_SEL_1_8822C BIT(4)
+#define BIT_R_WMAC_RXLEN_SEL1_1_8822C BIT(3)
+#define BIT_R_OFDM_FILTER_1_8822C BIT(2)
+#define BIT_R_WMAC_CHK_OFDM_LEN_1_8822C BIT(1)
+#define BIT_R_WMAC_CHK_CCK_LEN_1_8822C BIT(0)
+
+/* 2 REG_WMAC_OPTION_FUNCTION_2_8822C */
+
+#define BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8822C 0
+#define BIT_MASK_R_WMAC_RX_FIL_LEN_2_8822C 0xffff
+#define BIT_R_WMAC_RX_FIL_LEN_2_8822C(x) \
+ (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_2_8822C) \
+ << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8822C)
+#define BITS_R_WMAC_RX_FIL_LEN_2_8822C \
+ (BIT_MASK_R_WMAC_RX_FIL_LEN_2_8822C \
+ << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8822C)
+#define BIT_CLEAR_R_WMAC_RX_FIL_LEN_2_8822C(x) \
+ ((x) & (~BITS_R_WMAC_RX_FIL_LEN_2_8822C))
+#define BIT_GET_R_WMAC_RX_FIL_LEN_2_8822C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8822C) & \
+ BIT_MASK_R_WMAC_RX_FIL_LEN_2_8822C)
+#define BIT_SET_R_WMAC_RX_FIL_LEN_2_8822C(x, v) \
+ (BIT_CLEAR_R_WMAC_RX_FIL_LEN_2_8822C(x) | \
+ BIT_R_WMAC_RX_FIL_LEN_2_8822C(v))
+
+/* 2 REG_RX_FILTER_FUNCTION_8822C */
+#define BIT_RXHANG_EN_8822C BIT(15)
+#define BIT_R_WMAC_MHRDDY_LATCH_8822C BIT(14)
+#define BIT_R_WMAC_MHRDDY_CLR_8822C BIT(13)
+#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY1_8822C BIT(12)
+#define BIT_WMAC_DIS_VHT_PLCP_CHK_MU_8822C BIT(11)
+#define BIT_R_CHK_DELIMIT_LEN_8822C BIT(10)
+#define BIT_R_REAPTER_ADDR_MATCH_8822C BIT(9)
+#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY_8822C BIT(8)
+#define BIT_R_LATCH_MACHRDY_8822C BIT(7)
+#define BIT_R_WMAC_RXFIL_REND_8822C BIT(6)
+#define BIT_R_WMAC_MPDURDY_CLR_8822C BIT(5)
+#define BIT_R_WMAC_CLRRXSEC_8822C BIT(4)
+#define BIT_R_WMAC_RXFIL_RDEL_8822C BIT(3)
+#define BIT_R_WMAC_RXFIL_FCSE_8822C BIT(2)
+#define BIT_R_WMAC_RXFIL_MESH_DEL_8822C BIT(1)
+#define BIT_R_WMAC_RXFIL_MASKM_8822C BIT(0)
+
+/* 2 REG_NDP_SIG_8822C */
+
+#define BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822C 0
+#define BIT_MASK_R_WMAC_TXNDP_SIGB_8822C 0x1fffff
+#define BIT_R_WMAC_TXNDP_SIGB_8822C(x) \
+ (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB_8822C) \
+ << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822C)
+#define BITS_R_WMAC_TXNDP_SIGB_8822C \
+ (BIT_MASK_R_WMAC_TXNDP_SIGB_8822C << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822C)
+#define BIT_CLEAR_R_WMAC_TXNDP_SIGB_8822C(x) \
+ ((x) & (~BITS_R_WMAC_TXNDP_SIGB_8822C))
+#define BIT_GET_R_WMAC_TXNDP_SIGB_8822C(x) \
+ (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8822C) & \
+ BIT_MASK_R_WMAC_TXNDP_SIGB_8822C)
+#define BIT_SET_R_WMAC_TXNDP_SIGB_8822C(x, v) \
+ (BIT_CLEAR_R_WMAC_TXNDP_SIGB_8822C(x) | BIT_R_WMAC_TXNDP_SIGB_8822C(v))
+
+/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_8822C */
+
+#define BIT_SHIFT_R_MAC_DBG_SHIFT_8822C 8
+#define BIT_MASK_R_MAC_DBG_SHIFT_8822C 0x7
+#define BIT_R_MAC_DBG_SHIFT_8822C(x) \
+ (((x) & BIT_MASK_R_MAC_DBG_SHIFT_8822C) \
+ << BIT_SHIFT_R_MAC_DBG_SHIFT_8822C)
+#define BITS_R_MAC_DBG_SHIFT_8822C \
+ (BIT_MASK_R_MAC_DBG_SHIFT_8822C << BIT_SHIFT_R_MAC_DBG_SHIFT_8822C)
+#define BIT_CLEAR_R_MAC_DBG_SHIFT_8822C(x) ((x) & (~BITS_R_MAC_DBG_SHIFT_8822C))
+#define BIT_GET_R_MAC_DBG_SHIFT_8822C(x) \
+ (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8822C) & \
+ BIT_MASK_R_MAC_DBG_SHIFT_8822C)
+#define BIT_SET_R_MAC_DBG_SHIFT_8822C(x, v) \
+ (BIT_CLEAR_R_MAC_DBG_SHIFT_8822C(x) | BIT_R_MAC_DBG_SHIFT_8822C(v))
+
+#define BIT_SHIFT_R_MAC_DBG_SEL_8822C 0
+#define BIT_MASK_R_MAC_DBG_SEL_8822C 0x3
+#define BIT_R_MAC_DBG_SEL_8822C(x) \
+ (((x) & BIT_MASK_R_MAC_DBG_SEL_8822C) << BIT_SHIFT_R_MAC_DBG_SEL_8822C)
+#define BITS_R_MAC_DBG_SEL_8822C \
+ (BIT_MASK_R_MAC_DBG_SEL_8822C << BIT_SHIFT_R_MAC_DBG_SEL_8822C)
+#define BIT_CLEAR_R_MAC_DBG_SEL_8822C(x) ((x) & (~BITS_R_MAC_DBG_SEL_8822C))
+#define BIT_GET_R_MAC_DBG_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8822C) & BIT_MASK_R_MAC_DBG_SEL_8822C)
+#define BIT_SET_R_MAC_DBG_SEL_8822C(x, v) \
+ (BIT_CLEAR_R_MAC_DBG_SEL_8822C(x) | BIT_R_MAC_DBG_SEL_8822C(v))
+
+/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_1_8822C */
+
+#define BIT_SHIFT_R_MAC_DEBUG_1_8822C 0
+#define BIT_MASK_R_MAC_DEBUG_1_8822C 0xffffffffL
+#define BIT_R_MAC_DEBUG_1_8822C(x) \
+ (((x) & BIT_MASK_R_MAC_DEBUG_1_8822C) << BIT_SHIFT_R_MAC_DEBUG_1_8822C)
+#define BITS_R_MAC_DEBUG_1_8822C \
+ (BIT_MASK_R_MAC_DEBUG_1_8822C << BIT_SHIFT_R_MAC_DEBUG_1_8822C)
+#define BIT_CLEAR_R_MAC_DEBUG_1_8822C(x) ((x) & (~BITS_R_MAC_DEBUG_1_8822C))
+#define BIT_GET_R_MAC_DEBUG_1_8822C(x) \
+ (((x) >> BIT_SHIFT_R_MAC_DEBUG_1_8822C) & BIT_MASK_R_MAC_DEBUG_1_8822C)
+#define BIT_SET_R_MAC_DEBUG_1_8822C(x, v) \
+ (BIT_CLEAR_R_MAC_DEBUG_1_8822C(x) | BIT_R_MAC_DEBUG_1_8822C(v))
+
+/* 2 REG_WSEC_OPTION_8822C */
+#define BIT_RXDEC_BM_MGNT_8822C BIT(22)
+#define BIT_TXENC_BM_MGNT_8822C BIT(21)
+#define BIT_RXDEC_UNI_MGNT_8822C BIT(20)
+#define BIT_TXENC_UNI_MGNT_8822C BIT(19)
+#define BIT_WMAC_SEC_MASKIV_8822C BIT(18)
+
+#define BIT_SHIFT_WMAC_SEC_PN_SEL_8822C 16
+#define BIT_MASK_WMAC_SEC_PN_SEL_8822C 0x3
+#define BIT_WMAC_SEC_PN_SEL_8822C(x) \
+ (((x) & BIT_MASK_WMAC_SEC_PN_SEL_8822C) \
+ << BIT_SHIFT_WMAC_SEC_PN_SEL_8822C)
+#define BITS_WMAC_SEC_PN_SEL_8822C \
+ (BIT_MASK_WMAC_SEC_PN_SEL_8822C << BIT_SHIFT_WMAC_SEC_PN_SEL_8822C)
+#define BIT_CLEAR_WMAC_SEC_PN_SEL_8822C(x) ((x) & (~BITS_WMAC_SEC_PN_SEL_8822C))
+#define BIT_GET_WMAC_SEC_PN_SEL_8822C(x) \
+ (((x) >> BIT_SHIFT_WMAC_SEC_PN_SEL_8822C) & \
+ BIT_MASK_WMAC_SEC_PN_SEL_8822C)
+#define BIT_SET_WMAC_SEC_PN_SEL_8822C(x, v) \
+ (BIT_CLEAR_WMAC_SEC_PN_SEL_8822C(x) | BIT_WMAC_SEC_PN_SEL_8822C(v))
+
+#define BIT_SHIFT_BT_TIME_CNT_8822C 0
+#define BIT_MASK_BT_TIME_CNT_8822C 0xff
+#define BIT_BT_TIME_CNT_8822C(x) \
+ (((x) & BIT_MASK_BT_TIME_CNT_8822C) << BIT_SHIFT_BT_TIME_CNT_8822C)
+#define BITS_BT_TIME_CNT_8822C \
+ (BIT_MASK_BT_TIME_CNT_8822C << BIT_SHIFT_BT_TIME_CNT_8822C)
+#define BIT_CLEAR_BT_TIME_CNT_8822C(x) ((x) & (~BITS_BT_TIME_CNT_8822C))
+#define BIT_GET_BT_TIME_CNT_8822C(x) \
+ (((x) >> BIT_SHIFT_BT_TIME_CNT_8822C) & BIT_MASK_BT_TIME_CNT_8822C)
+#define BIT_SET_BT_TIME_CNT_8822C(x, v) \
+ (BIT_CLEAR_BT_TIME_CNT_8822C(x) | BIT_BT_TIME_CNT_8822C(v))
+
+/* 2 REG_RTS_ADDRESS_0_8822C */
+
+/* 2 REG_RTS_ADDRESS_0_1_8822C */
+
+/* 2 REG_RTS_ADDRESS_1_8822C */
+
+/* 2 REG_RTS_ADDRESS_1_1_8822C */
+
+/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8822C */
+#define BIT_LTECOEX_ACCESS_START_V1_8822C BIT(31)
+#define BIT_LTECOEX_WRITE_MODE_V1_8822C BIT(30)
+#define BIT_LTECOEX_READY_BIT_V1_8822C BIT(29)
+
+#define BIT_SHIFT_WRITE_BYTE_EN_V1_8822C 16
+#define BIT_MASK_WRITE_BYTE_EN_V1_8822C 0xf
+#define BIT_WRITE_BYTE_EN_V1_8822C(x) \
+ (((x) & BIT_MASK_WRITE_BYTE_EN_V1_8822C) \
+ << BIT_SHIFT_WRITE_BYTE_EN_V1_8822C)
+#define BITS_WRITE_BYTE_EN_V1_8822C \
+ (BIT_MASK_WRITE_BYTE_EN_V1_8822C << BIT_SHIFT_WRITE_BYTE_EN_V1_8822C)
+#define BIT_CLEAR_WRITE_BYTE_EN_V1_8822C(x) \
+ ((x) & (~BITS_WRITE_BYTE_EN_V1_8822C))
+#define BIT_GET_WRITE_BYTE_EN_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1_8822C) & \
+ BIT_MASK_WRITE_BYTE_EN_V1_8822C)
+#define BIT_SET_WRITE_BYTE_EN_V1_8822C(x, v) \
+ (BIT_CLEAR_WRITE_BYTE_EN_V1_8822C(x) | BIT_WRITE_BYTE_EN_V1_8822C(v))
+
+#define BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822C 0
+#define BIT_MASK_LTECOEX_REG_ADDR_V1_8822C 0xffff
+#define BIT_LTECOEX_REG_ADDR_V1_8822C(x) \
+ (((x) & BIT_MASK_LTECOEX_REG_ADDR_V1_8822C) \
+ << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822C)
+#define BITS_LTECOEX_REG_ADDR_V1_8822C \
+ (BIT_MASK_LTECOEX_REG_ADDR_V1_8822C \
+ << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822C)
+#define BIT_CLEAR_LTECOEX_REG_ADDR_V1_8822C(x) \
+ ((x) & (~BITS_LTECOEX_REG_ADDR_V1_8822C))
+#define BIT_GET_LTECOEX_REG_ADDR_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1_8822C) & \
+ BIT_MASK_LTECOEX_REG_ADDR_V1_8822C)
+#define BIT_SET_LTECOEX_REG_ADDR_V1_8822C(x, v) \
+ (BIT_CLEAR_LTECOEX_REG_ADDR_V1_8822C(x) | \
+ BIT_LTECOEX_REG_ADDR_V1_8822C(v))
+
+/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8822C */
+
+#define BIT_SHIFT_LTECOEX_W_DATA_V1_8822C 0
+#define BIT_MASK_LTECOEX_W_DATA_V1_8822C 0xffffffffL
+#define BIT_LTECOEX_W_DATA_V1_8822C(x) \
+ (((x) & BIT_MASK_LTECOEX_W_DATA_V1_8822C) \
+ << BIT_SHIFT_LTECOEX_W_DATA_V1_8822C)
+#define BITS_LTECOEX_W_DATA_V1_8822C \
+ (BIT_MASK_LTECOEX_W_DATA_V1_8822C << BIT_SHIFT_LTECOEX_W_DATA_V1_8822C)
+#define BIT_CLEAR_LTECOEX_W_DATA_V1_8822C(x) \
+ ((x) & (~BITS_LTECOEX_W_DATA_V1_8822C))
+#define BIT_GET_LTECOEX_W_DATA_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1_8822C) & \
+ BIT_MASK_LTECOEX_W_DATA_V1_8822C)
+#define BIT_SET_LTECOEX_W_DATA_V1_8822C(x, v) \
+ (BIT_CLEAR_LTECOEX_W_DATA_V1_8822C(x) | BIT_LTECOEX_W_DATA_V1_8822C(v))
+
+/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8822C */
+
+#define BIT_SHIFT_LTECOEX_R_DATA_V1_8822C 0
+#define BIT_MASK_LTECOEX_R_DATA_V1_8822C 0xffffffffL
+#define BIT_LTECOEX_R_DATA_V1_8822C(x) \
+ (((x) & BIT_MASK_LTECOEX_R_DATA_V1_8822C) \
+ << BIT_SHIFT_LTECOEX_R_DATA_V1_8822C)
+#define BITS_LTECOEX_R_DATA_V1_8822C \
+ (BIT_MASK_LTECOEX_R_DATA_V1_8822C << BIT_SHIFT_LTECOEX_R_DATA_V1_8822C)
+#define BIT_CLEAR_LTECOEX_R_DATA_V1_8822C(x) \
+ ((x) & (~BITS_LTECOEX_R_DATA_V1_8822C))
+#define BIT_GET_LTECOEX_R_DATA_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1_8822C) & \
+ BIT_MASK_LTECOEX_R_DATA_V1_8822C)
+#define BIT_SET_LTECOEX_R_DATA_V1_8822C(x, v) \
+ (BIT_CLEAR_LTECOEX_R_DATA_V1_8822C(x) | BIT_LTECOEX_R_DATA_V1_8822C(v))
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_NOT_VALID_8822C */
+
+/* 2 REG_SDIO_TX_CTRL_8822C */
+
+#define BIT_SHIFT_SDIO_INT_TIMEOUT_8822C 16
+#define BIT_MASK_SDIO_INT_TIMEOUT_8822C 0xffff
+#define BIT_SDIO_INT_TIMEOUT_8822C(x) \
+ (((x) & BIT_MASK_SDIO_INT_TIMEOUT_8822C) \
+ << BIT_SHIFT_SDIO_INT_TIMEOUT_8822C)
+#define BITS_SDIO_INT_TIMEOUT_8822C \
+ (BIT_MASK_SDIO_INT_TIMEOUT_8822C << BIT_SHIFT_SDIO_INT_TIMEOUT_8822C)
+#define BIT_CLEAR_SDIO_INT_TIMEOUT_8822C(x) \
+ ((x) & (~BITS_SDIO_INT_TIMEOUT_8822C))
+#define BIT_GET_SDIO_INT_TIMEOUT_8822C(x) \
+ (((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT_8822C) & \
+ BIT_MASK_SDIO_INT_TIMEOUT_8822C)
+#define BIT_SET_SDIO_INT_TIMEOUT_8822C(x, v) \
+ (BIT_CLEAR_SDIO_INT_TIMEOUT_8822C(x) | BIT_SDIO_INT_TIMEOUT_8822C(v))
+
+#define BIT_IO_ERR_STATUS_8822C BIT(15)
+#define BIT_CMD53_W_MIX_8822C BIT(14)
+#define BIT_CMD53_TX_FORMAT_8822C BIT(13)
+#define BIT_CMD53_R_TIMEOUT_MASK_8822C BIT(12)
+
+#define BIT_SHIFT_CMD53_R_TIMEOUT_UNIT_8822C 10
+#define BIT_MASK_CMD53_R_TIMEOUT_UNIT_8822C 0x3
+#define BIT_CMD53_R_TIMEOUT_UNIT_8822C(x) \
+ (((x) & BIT_MASK_CMD53_R_TIMEOUT_UNIT_8822C) \
+ << BIT_SHIFT_CMD53_R_TIMEOUT_UNIT_8822C)
+#define BITS_CMD53_R_TIMEOUT_UNIT_8822C \
+ (BIT_MASK_CMD53_R_TIMEOUT_UNIT_8822C \
+ << BIT_SHIFT_CMD53_R_TIMEOUT_UNIT_8822C)
+#define BIT_CLEAR_CMD53_R_TIMEOUT_UNIT_8822C(x) \
+ ((x) & (~BITS_CMD53_R_TIMEOUT_UNIT_8822C))
+#define BIT_GET_CMD53_R_TIMEOUT_UNIT_8822C(x) \
+ (((x) >> BIT_SHIFT_CMD53_R_TIMEOUT_UNIT_8822C) & \
+ BIT_MASK_CMD53_R_TIMEOUT_UNIT_8822C)
+#define BIT_SET_CMD53_R_TIMEOUT_UNIT_8822C(x, v) \
+ (BIT_CLEAR_CMD53_R_TIMEOUT_UNIT_8822C(x) | \
+ BIT_CMD53_R_TIMEOUT_UNIT_8822C(v))
+
+#define BIT_REPLY_ERRCRC_IN_DATA_8822C BIT(9)
+#define BIT_EN_CMD53_OVERLAP_8822C BIT(8)
+#define BIT_REPLY_ERR_IN_R5_8822C BIT(7)
+#define BIT_R18A_EN_8822C BIT(6)
+#define BIT_SDIO_CMD_FORCE_VLD_8822C BIT(5)
+#define BIT_INIT_CMD_EN_8822C BIT(4)
+#define BIT_RXINT_READ_MASK_DIS_8822C BIT(3)
+#define BIT_EN_RXDMA_MASK_INT_8822C BIT(2)
+#define BIT_EN_MASK_TIMER_8822C BIT(1)
+#define BIT_CMD_ERR_STOP_INT_EN_8822C BIT(0)
+
+/* 2 REG_SDIO_CMD11_VOL_SWITCH_8822C */
+
+#define BIT_SHIFT_CMD11_SEQ_END_DELAY_8822C 4
+#define BIT_MASK_CMD11_SEQ_END_DELAY_8822C 0xf
+#define BIT_CMD11_SEQ_END_DELAY_8822C(x) \
+ (((x) & BIT_MASK_CMD11_SEQ_END_DELAY_8822C) \
+ << BIT_SHIFT_CMD11_SEQ_END_DELAY_8822C)
+#define BITS_CMD11_SEQ_END_DELAY_8822C \
+ (BIT_MASK_CMD11_SEQ_END_DELAY_8822C \
+ << BIT_SHIFT_CMD11_SEQ_END_DELAY_8822C)
+#define BIT_CLEAR_CMD11_SEQ_END_DELAY_8822C(x) \
+ ((x) & (~BITS_CMD11_SEQ_END_DELAY_8822C))
+#define BIT_GET_CMD11_SEQ_END_DELAY_8822C(x) \
+ (((x) >> BIT_SHIFT_CMD11_SEQ_END_DELAY_8822C) & \
+ BIT_MASK_CMD11_SEQ_END_DELAY_8822C)
+#define BIT_SET_CMD11_SEQ_END_DELAY_8822C(x, v) \
+ (BIT_CLEAR_CMD11_SEQ_END_DELAY_8822C(x) | \
+ BIT_CMD11_SEQ_END_DELAY_8822C(v))
+
+#define BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL_8822C 1
+#define BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL_8822C 0x7
+#define BIT_CMD11_SEQ_SAMPLE_INTERVAL_8822C(x) \
+ (((x) & BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL_8822C) \
+ << BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL_8822C)
+#define BITS_CMD11_SEQ_SAMPLE_INTERVAL_8822C \
+ (BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL_8822C \
+ << BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL_8822C)
+#define BIT_CLEAR_CMD11_SEQ_SAMPLE_INTERVAL_8822C(x) \
+ ((x) & (~BITS_CMD11_SEQ_SAMPLE_INTERVAL_8822C))
+#define BIT_GET_CMD11_SEQ_SAMPLE_INTERVAL_8822C(x) \
+ (((x) >> BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL_8822C) & \
+ BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL_8822C)
+#define BIT_SET_CMD11_SEQ_SAMPLE_INTERVAL_8822C(x, v) \
+ (BIT_CLEAR_CMD11_SEQ_SAMPLE_INTERVAL_8822C(x) | \
+ BIT_CMD11_SEQ_SAMPLE_INTERVAL_8822C(v))
+
+#define BIT_CMD11_SEQ_EN_8822C BIT(0)
+
+/* 2 REG_SDIO_DRIVING_8822C */
+
+#define BIT_SHIFT_SDIO_DRV_TYPE_D_8822C 12
+#define BIT_MASK_SDIO_DRV_TYPE_D_8822C 0xf
+#define BIT_SDIO_DRV_TYPE_D_8822C(x) \
+ (((x) & BIT_MASK_SDIO_DRV_TYPE_D_8822C) \
+ << BIT_SHIFT_SDIO_DRV_TYPE_D_8822C)
+#define BITS_SDIO_DRV_TYPE_D_8822C \
+ (BIT_MASK_SDIO_DRV_TYPE_D_8822C << BIT_SHIFT_SDIO_DRV_TYPE_D_8822C)
+#define BIT_CLEAR_SDIO_DRV_TYPE_D_8822C(x) ((x) & (~BITS_SDIO_DRV_TYPE_D_8822C))
+#define BIT_GET_SDIO_DRV_TYPE_D_8822C(x) \
+ (((x) >> BIT_SHIFT_SDIO_DRV_TYPE_D_8822C) & \
+ BIT_MASK_SDIO_DRV_TYPE_D_8822C)
+#define BIT_SET_SDIO_DRV_TYPE_D_8822C(x, v) \
+ (BIT_CLEAR_SDIO_DRV_TYPE_D_8822C(x) | BIT_SDIO_DRV_TYPE_D_8822C(v))
+
+#define BIT_SHIFT_SDIO_DRV_TYPE_C_8822C 8
+#define BIT_MASK_SDIO_DRV_TYPE_C_8822C 0xf
+#define BIT_SDIO_DRV_TYPE_C_8822C(x) \
+ (((x) & BIT_MASK_SDIO_DRV_TYPE_C_8822C) \
+ << BIT_SHIFT_SDIO_DRV_TYPE_C_8822C)
+#define BITS_SDIO_DRV_TYPE_C_8822C \
+ (BIT_MASK_SDIO_DRV_TYPE_C_8822C << BIT_SHIFT_SDIO_DRV_TYPE_C_8822C)
+#define BIT_CLEAR_SDIO_DRV_TYPE_C_8822C(x) ((x) & (~BITS_SDIO_DRV_TYPE_C_8822C))
+#define BIT_GET_SDIO_DRV_TYPE_C_8822C(x) \
+ (((x) >> BIT_SHIFT_SDIO_DRV_TYPE_C_8822C) & \
+ BIT_MASK_SDIO_DRV_TYPE_C_8822C)
+#define BIT_SET_SDIO_DRV_TYPE_C_8822C(x, v) \
+ (BIT_CLEAR_SDIO_DRV_TYPE_C_8822C(x) | BIT_SDIO_DRV_TYPE_C_8822C(v))
+
+#define BIT_SHIFT_SDIO_DRV_TYPE_B_8822C 4
+#define BIT_MASK_SDIO_DRV_TYPE_B_8822C 0xf
+#define BIT_SDIO_DRV_TYPE_B_8822C(x) \
+ (((x) & BIT_MASK_SDIO_DRV_TYPE_B_8822C) \
+ << BIT_SHIFT_SDIO_DRV_TYPE_B_8822C)
+#define BITS_SDIO_DRV_TYPE_B_8822C \
+ (BIT_MASK_SDIO_DRV_TYPE_B_8822C << BIT_SHIFT_SDIO_DRV_TYPE_B_8822C)
+#define BIT_CLEAR_SDIO_DRV_TYPE_B_8822C(x) ((x) & (~BITS_SDIO_DRV_TYPE_B_8822C))
+#define BIT_GET_SDIO_DRV_TYPE_B_8822C(x) \
+ (((x) >> BIT_SHIFT_SDIO_DRV_TYPE_B_8822C) & \
+ BIT_MASK_SDIO_DRV_TYPE_B_8822C)
+#define BIT_SET_SDIO_DRV_TYPE_B_8822C(x, v) \
+ (BIT_CLEAR_SDIO_DRV_TYPE_B_8822C(x) | BIT_SDIO_DRV_TYPE_B_8822C(v))
+
+#define BIT_SHIFT_SDIO_DRV_TYPE_A_8822C 0
+#define BIT_MASK_SDIO_DRV_TYPE_A_8822C 0xf
+#define BIT_SDIO_DRV_TYPE_A_8822C(x) \
+ (((x) & BIT_MASK_SDIO_DRV_TYPE_A_8822C) \
+ << BIT_SHIFT_SDIO_DRV_TYPE_A_8822C)
+#define BITS_SDIO_DRV_TYPE_A_8822C \
+ (BIT_MASK_SDIO_DRV_TYPE_A_8822C << BIT_SHIFT_SDIO_DRV_TYPE_A_8822C)
+#define BIT_CLEAR_SDIO_DRV_TYPE_A_8822C(x) ((x) & (~BITS_SDIO_DRV_TYPE_A_8822C))
+#define BIT_GET_SDIO_DRV_TYPE_A_8822C(x) \
+ (((x) >> BIT_SHIFT_SDIO_DRV_TYPE_A_8822C) & \
+ BIT_MASK_SDIO_DRV_TYPE_A_8822C)
+#define BIT_SET_SDIO_DRV_TYPE_A_8822C(x, v) \
+ (BIT_CLEAR_SDIO_DRV_TYPE_A_8822C(x) | BIT_SDIO_DRV_TYPE_A_8822C(v))
+
+/* 2 REG_SDIO_MONITOR_8822C */
+
+#define BIT_SHIFT_SDIO_INT_START_8822C 0
+#define BIT_MASK_SDIO_INT_START_8822C 0xffffffffL
+#define BIT_SDIO_INT_START_8822C(x) \
+ (((x) & BIT_MASK_SDIO_INT_START_8822C) \
+ << BIT_SHIFT_SDIO_INT_START_8822C)
+#define BITS_SDIO_INT_START_8822C \
+ (BIT_MASK_SDIO_INT_START_8822C << BIT_SHIFT_SDIO_INT_START_8822C)
+#define BIT_CLEAR_SDIO_INT_START_8822C(x) ((x) & (~BITS_SDIO_INT_START_8822C))
+#define BIT_GET_SDIO_INT_START_8822C(x) \
+ (((x) >> BIT_SHIFT_SDIO_INT_START_8822C) & \
+ BIT_MASK_SDIO_INT_START_8822C)
+#define BIT_SET_SDIO_INT_START_8822C(x, v) \
+ (BIT_CLEAR_SDIO_INT_START_8822C(x) | BIT_SDIO_INT_START_8822C(v))
+
+/* 2 REG_SDIO_MONITOR_2_8822C */
+#define BIT_CMD53_WT_EN_8822C BIT(23)
+
+#define BIT_SHIFT_SDIO_CLK_MONITOR_8822C 21
+#define BIT_MASK_SDIO_CLK_MONITOR_8822C 0x3
+#define BIT_SDIO_CLK_MONITOR_8822C(x) \
+ (((x) & BIT_MASK_SDIO_CLK_MONITOR_8822C) \
+ << BIT_SHIFT_SDIO_CLK_MONITOR_8822C)
+#define BITS_SDIO_CLK_MONITOR_8822C \
+ (BIT_MASK_SDIO_CLK_MONITOR_8822C << BIT_SHIFT_SDIO_CLK_MONITOR_8822C)
+#define BIT_CLEAR_SDIO_CLK_MONITOR_8822C(x) \
+ ((x) & (~BITS_SDIO_CLK_MONITOR_8822C))
+#define BIT_GET_SDIO_CLK_MONITOR_8822C(x) \
+ (((x) >> BIT_SHIFT_SDIO_CLK_MONITOR_8822C) & \
+ BIT_MASK_SDIO_CLK_MONITOR_8822C)
+#define BIT_SET_SDIO_CLK_MONITOR_8822C(x, v) \
+ (BIT_CLEAR_SDIO_CLK_MONITOR_8822C(x) | BIT_SDIO_CLK_MONITOR_8822C(v))
+
+#define BIT_SHIFT_SDIO_CLK_CNT_8822C 0
+#define BIT_MASK_SDIO_CLK_CNT_8822C 0x1fffff
+#define BIT_SDIO_CLK_CNT_8822C(x) \
+ (((x) & BIT_MASK_SDIO_CLK_CNT_8822C) << BIT_SHIFT_SDIO_CLK_CNT_8822C)
+#define BITS_SDIO_CLK_CNT_8822C \
+ (BIT_MASK_SDIO_CLK_CNT_8822C << BIT_SHIFT_SDIO_CLK_CNT_8822C)
+#define BIT_CLEAR_SDIO_CLK_CNT_8822C(x) ((x) & (~BITS_SDIO_CLK_CNT_8822C))
+#define BIT_GET_SDIO_CLK_CNT_8822C(x) \
+ (((x) >> BIT_SHIFT_SDIO_CLK_CNT_8822C) & BIT_MASK_SDIO_CLK_CNT_8822C)
+#define BIT_SET_SDIO_CLK_CNT_8822C(x, v) \
+ (BIT_CLEAR_SDIO_CLK_CNT_8822C(x) | BIT_SDIO_CLK_CNT_8822C(v))
+
+/* 2 REG_SDIO_HIMR_8822C */
+#define BIT_SDIO_CRCERR_MSK_8822C BIT(31)
+#define BIT_SDIO_HSISR3_IND_MSK_8822C BIT(30)
+#define BIT_SDIO_HSISR2_IND_MSK_8822C BIT(29)
+#define BIT_SDIO_HEISR_IND_MSK_8822C BIT(28)
+#define BIT_SDIO_CTWEND_MSK_8822C BIT(27)
+#define BIT_SDIO_ATIMEND_E_MSK_8822C BIT(26)
+#define BIT_SDIIO_ATIMEND_MSK_8822C BIT(25)
+#define BIT_SDIO_OCPINT_MSK_8822C BIT(24)
+#define BIT_SDIO_PSTIMEOUT_MSK_8822C BIT(23)
+#define BIT_SDIO_GTINT4_MSK_8822C BIT(22)
+#define BIT_SDIO_GTINT3_MSK_8822C BIT(21)
+#define BIT_SDIO_HSISR_IND_MSK_8822C BIT(20)
+#define BIT_SDIO_CPWM2_MSK_8822C BIT(19)
+#define BIT_SDIO_CPWM1_MSK_8822C BIT(18)
+#define BIT_SDIO_C2HCMD_INT_MSK_8822C BIT(17)
+#define BIT_SDIO_BCNERLY_INT_MSK_8822C BIT(16)
+#define BIT_SDIO_TXBCNERR_MSK_8822C BIT(7)
+#define BIT_SDIO_TXBCNOK_MSK_8822C BIT(6)
+#define BIT_SDIO_RXFOVW_MSK_8822C BIT(5)
+#define BIT_SDIO_TXFOVW_MSK_8822C BIT(4)
+#define BIT_SDIO_RXERR_MSK_8822C BIT(3)
+#define BIT_SDIO_TXERR_MSK_8822C BIT(2)
+#define BIT_SDIO_AVAL_MSK_8822C BIT(1)
+#define BIT_RX_REQUEST_MSK_8822C BIT(0)
+
+/* 2 REG_SDIO_HISR_8822C */
+#define BIT_SDIO_CRCERR_8822C BIT(31)
+#define BIT_SDIO_HSISR3_IND_8822C BIT(30)
+#define BIT_SDIO_HSISR2_IND_8822C BIT(29)
+#define BIT_SDIO_HEISR_IND_8822C BIT(28)
+#define BIT_SDIO_CTWEND_8822C BIT(27)
+#define BIT_SDIO_ATIMEND_E_8822C BIT(26)
+#define BIT_SDIO_ATIMEND_8822C BIT(25)
+#define BIT_SDIO_OCPINT_8822C BIT(24)
+#define BIT_SDIO_PSTIMEOUT_8822C BIT(23)
+#define BIT_SDIO_GTINT4_8822C BIT(22)
+#define BIT_SDIO_GTINT3_8822C BIT(21)
+#define BIT_SDIO_HSISR_IND_8822C BIT(20)
+#define BIT_SDIO_CPWM2_8822C BIT(19)
+#define BIT_SDIO_CPWM1_8822C BIT(18)
+#define BIT_SDIO_C2HCMD_INT_8822C BIT(17)
+#define BIT_SDIO_BCNERLY_INT_8822C BIT(16)
+#define BIT_SDIO_TXBCNERR_8822C BIT(7)
+#define BIT_SDIO_TXBCNOK_8822C BIT(6)
+#define BIT_SDIO_RXFOVW_8822C BIT(5)
+#define BIT_SDIO_TXFOVW_8822C BIT(4)
+#define BIT_SDIO_RXERR_8822C BIT(3)
+#define BIT_SDIO_TXERR_8822C BIT(2)
+#define BIT_SDIO_AVAL_8822C BIT(1)
+#define BIT_RX_REQUEST_8822C BIT(0)
+
+/* 2 REG_SDIO_RX_REQ_LEN_8822C */
+
+#define BIT_SHIFT_RX_REQ_LEN_V1_8822C 0
+#define BIT_MASK_RX_REQ_LEN_V1_8822C 0x3ffff
+#define BIT_RX_REQ_LEN_V1_8822C(x) \
+ (((x) & BIT_MASK_RX_REQ_LEN_V1_8822C) << BIT_SHIFT_RX_REQ_LEN_V1_8822C)
+#define BITS_RX_REQ_LEN_V1_8822C \
+ (BIT_MASK_RX_REQ_LEN_V1_8822C << BIT_SHIFT_RX_REQ_LEN_V1_8822C)
+#define BIT_CLEAR_RX_REQ_LEN_V1_8822C(x) ((x) & (~BITS_RX_REQ_LEN_V1_8822C))
+#define BIT_GET_RX_REQ_LEN_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_RX_REQ_LEN_V1_8822C) & BIT_MASK_RX_REQ_LEN_V1_8822C)
+#define BIT_SET_RX_REQ_LEN_V1_8822C(x, v) \
+ (BIT_CLEAR_RX_REQ_LEN_V1_8822C(x) | BIT_RX_REQ_LEN_V1_8822C(v))
+
+/* 2 REG_SDIO_FREE_TXPG_SEQ_V1_8822C */
+
+#define BIT_SHIFT_FREE_TXPG_SEQ_8822C 0
+#define BIT_MASK_FREE_TXPG_SEQ_8822C 0xff
+#define BIT_FREE_TXPG_SEQ_8822C(x) \
+ (((x) & BIT_MASK_FREE_TXPG_SEQ_8822C) << BIT_SHIFT_FREE_TXPG_SEQ_8822C)
+#define BITS_FREE_TXPG_SEQ_8822C \
+ (BIT_MASK_FREE_TXPG_SEQ_8822C << BIT_SHIFT_FREE_TXPG_SEQ_8822C)
+#define BIT_CLEAR_FREE_TXPG_SEQ_8822C(x) ((x) & (~BITS_FREE_TXPG_SEQ_8822C))
+#define BIT_GET_FREE_TXPG_SEQ_8822C(x) \
+ (((x) >> BIT_SHIFT_FREE_TXPG_SEQ_8822C) & BIT_MASK_FREE_TXPG_SEQ_8822C)
+#define BIT_SET_FREE_TXPG_SEQ_8822C(x, v) \
+ (BIT_CLEAR_FREE_TXPG_SEQ_8822C(x) | BIT_FREE_TXPG_SEQ_8822C(v))
+
+/* 2 REG_SDIO_FREE_TXPG_8822C */
+
+#define BIT_SHIFT_MID_FREEPG_V1_8822C 16
+#define BIT_MASK_MID_FREEPG_V1_8822C 0xfff
+#define BIT_MID_FREEPG_V1_8822C(x) \
+ (((x) & BIT_MASK_MID_FREEPG_V1_8822C) << BIT_SHIFT_MID_FREEPG_V1_8822C)
+#define BITS_MID_FREEPG_V1_8822C \
+ (BIT_MASK_MID_FREEPG_V1_8822C << BIT_SHIFT_MID_FREEPG_V1_8822C)
+#define BIT_CLEAR_MID_FREEPG_V1_8822C(x) ((x) & (~BITS_MID_FREEPG_V1_8822C))
+#define BIT_GET_MID_FREEPG_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_MID_FREEPG_V1_8822C) & BIT_MASK_MID_FREEPG_V1_8822C)
+#define BIT_SET_MID_FREEPG_V1_8822C(x, v) \
+ (BIT_CLEAR_MID_FREEPG_V1_8822C(x) | BIT_MID_FREEPG_V1_8822C(v))
+
+#define BIT_SHIFT_HIQ_FREEPG_V1_8822C 0
+#define BIT_MASK_HIQ_FREEPG_V1_8822C 0xfff
+#define BIT_HIQ_FREEPG_V1_8822C(x) \
+ (((x) & BIT_MASK_HIQ_FREEPG_V1_8822C) << BIT_SHIFT_HIQ_FREEPG_V1_8822C)
+#define BITS_HIQ_FREEPG_V1_8822C \
+ (BIT_MASK_HIQ_FREEPG_V1_8822C << BIT_SHIFT_HIQ_FREEPG_V1_8822C)
+#define BIT_CLEAR_HIQ_FREEPG_V1_8822C(x) ((x) & (~BITS_HIQ_FREEPG_V1_8822C))
+#define BIT_GET_HIQ_FREEPG_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_HIQ_FREEPG_V1_8822C) & BIT_MASK_HIQ_FREEPG_V1_8822C)
+#define BIT_SET_HIQ_FREEPG_V1_8822C(x, v) \
+ (BIT_CLEAR_HIQ_FREEPG_V1_8822C(x) | BIT_HIQ_FREEPG_V1_8822C(v))
+
+/* 2 REG_SDIO_FREE_TXPG2_8822C */
+
+#define BIT_SHIFT_PUB_FREEPG_V1_8822C 16
+#define BIT_MASK_PUB_FREEPG_V1_8822C 0xfff
+#define BIT_PUB_FREEPG_V1_8822C(x) \
+ (((x) & BIT_MASK_PUB_FREEPG_V1_8822C) << BIT_SHIFT_PUB_FREEPG_V1_8822C)
+#define BITS_PUB_FREEPG_V1_8822C \
+ (BIT_MASK_PUB_FREEPG_V1_8822C << BIT_SHIFT_PUB_FREEPG_V1_8822C)
+#define BIT_CLEAR_PUB_FREEPG_V1_8822C(x) ((x) & (~BITS_PUB_FREEPG_V1_8822C))
+#define BIT_GET_PUB_FREEPG_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_PUB_FREEPG_V1_8822C) & BIT_MASK_PUB_FREEPG_V1_8822C)
+#define BIT_SET_PUB_FREEPG_V1_8822C(x, v) \
+ (BIT_CLEAR_PUB_FREEPG_V1_8822C(x) | BIT_PUB_FREEPG_V1_8822C(v))
+
+#define BIT_SHIFT_LOW_FREEPG_V1_8822C 0
+#define BIT_MASK_LOW_FREEPG_V1_8822C 0xfff
+#define BIT_LOW_FREEPG_V1_8822C(x) \
+ (((x) & BIT_MASK_LOW_FREEPG_V1_8822C) << BIT_SHIFT_LOW_FREEPG_V1_8822C)
+#define BITS_LOW_FREEPG_V1_8822C \
+ (BIT_MASK_LOW_FREEPG_V1_8822C << BIT_SHIFT_LOW_FREEPG_V1_8822C)
+#define BIT_CLEAR_LOW_FREEPG_V1_8822C(x) ((x) & (~BITS_LOW_FREEPG_V1_8822C))
+#define BIT_GET_LOW_FREEPG_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_LOW_FREEPG_V1_8822C) & BIT_MASK_LOW_FREEPG_V1_8822C)
+#define BIT_SET_LOW_FREEPG_V1_8822C(x, v) \
+ (BIT_CLEAR_LOW_FREEPG_V1_8822C(x) | BIT_LOW_FREEPG_V1_8822C(v))
+
+/* 2 REG_SDIO_OQT_FREE_TXPG_V1_8822C */
+
+#define BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822C 24
+#define BIT_MASK_NOAC_OQT_FREEPG_V1_8822C 0xff
+#define BIT_NOAC_OQT_FREEPG_V1_8822C(x) \
+ (((x) & BIT_MASK_NOAC_OQT_FREEPG_V1_8822C) \
+ << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822C)
+#define BITS_NOAC_OQT_FREEPG_V1_8822C \
+ (BIT_MASK_NOAC_OQT_FREEPG_V1_8822C \
+ << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822C)
+#define BIT_CLEAR_NOAC_OQT_FREEPG_V1_8822C(x) \
+ ((x) & (~BITS_NOAC_OQT_FREEPG_V1_8822C))
+#define BIT_GET_NOAC_OQT_FREEPG_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1_8822C) & \
+ BIT_MASK_NOAC_OQT_FREEPG_V1_8822C)
+#define BIT_SET_NOAC_OQT_FREEPG_V1_8822C(x, v) \
+ (BIT_CLEAR_NOAC_OQT_FREEPG_V1_8822C(x) | \
+ BIT_NOAC_OQT_FREEPG_V1_8822C(v))
+
+#define BIT_SHIFT_AC_OQT_FREEPG_V1_8822C 16
+#define BIT_MASK_AC_OQT_FREEPG_V1_8822C 0xff
+#define BIT_AC_OQT_FREEPG_V1_8822C(x) \
+ (((x) & BIT_MASK_AC_OQT_FREEPG_V1_8822C) \
+ << BIT_SHIFT_AC_OQT_FREEPG_V1_8822C)
+#define BITS_AC_OQT_FREEPG_V1_8822C \
+ (BIT_MASK_AC_OQT_FREEPG_V1_8822C << BIT_SHIFT_AC_OQT_FREEPG_V1_8822C)
+#define BIT_CLEAR_AC_OQT_FREEPG_V1_8822C(x) \
+ ((x) & (~BITS_AC_OQT_FREEPG_V1_8822C))
+#define BIT_GET_AC_OQT_FREEPG_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1_8822C) & \
+ BIT_MASK_AC_OQT_FREEPG_V1_8822C)
+#define BIT_SET_AC_OQT_FREEPG_V1_8822C(x, v) \
+ (BIT_CLEAR_AC_OQT_FREEPG_V1_8822C(x) | BIT_AC_OQT_FREEPG_V1_8822C(v))
+
+#define BIT_SHIFT_EXQ_FREEPG_V1_8822C 0
+#define BIT_MASK_EXQ_FREEPG_V1_8822C 0xfff
+#define BIT_EXQ_FREEPG_V1_8822C(x) \
+ (((x) & BIT_MASK_EXQ_FREEPG_V1_8822C) << BIT_SHIFT_EXQ_FREEPG_V1_8822C)
+#define BITS_EXQ_FREEPG_V1_8822C \
+ (BIT_MASK_EXQ_FREEPG_V1_8822C << BIT_SHIFT_EXQ_FREEPG_V1_8822C)
+#define BIT_CLEAR_EXQ_FREEPG_V1_8822C(x) ((x) & (~BITS_EXQ_FREEPG_V1_8822C))
+#define BIT_GET_EXQ_FREEPG_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_EXQ_FREEPG_V1_8822C) & BIT_MASK_EXQ_FREEPG_V1_8822C)
+#define BIT_SET_EXQ_FREEPG_V1_8822C(x, v) \
+ (BIT_CLEAR_EXQ_FREEPG_V1_8822C(x) | BIT_EXQ_FREEPG_V1_8822C(v))
+
+/* 2 REG_SDIO_TXPKT_EMPTY_8822C */
+#define BIT_SDIO_BCNQ_EMPTY_8822C BIT(11)
+#define BIT_SDIO_HQQ_EMPTY_8822C BIT(10)
+#define BIT_SDIO_MQQ_EMPTY_8822C BIT(9)
+#define BIT_SDIO_MGQ_CPU_EMPTY_8822C BIT(8)
+#define BIT_SDIO_AC7Q_EMPTY_8822C BIT(7)
+#define BIT_SDIO_AC6Q_EMPTY_8822C BIT(6)
+#define BIT_SDIO_AC5Q_EMPTY_8822C BIT(5)
+#define BIT_SDIO_AC4Q_EMPTY_8822C BIT(4)
+#define BIT_SDIO_AC3Q_EMPTY_8822C BIT(3)
+#define BIT_SDIO_AC2Q_EMPTY_8822C BIT(2)
+#define BIT_SDIO_AC1Q_EMPTY_8822C BIT(1)
+#define BIT_SDIO_AC0Q_EMPTY_8822C BIT(0)
+
+/* 2 REG_SDIO_HTSFR_INFO_8822C */
+
+#define BIT_SHIFT_HTSFR1_8822C 16
+#define BIT_MASK_HTSFR1_8822C 0xffff
+#define BIT_HTSFR1_8822C(x) \
+ (((x) & BIT_MASK_HTSFR1_8822C) << BIT_SHIFT_HTSFR1_8822C)
+#define BITS_HTSFR1_8822C (BIT_MASK_HTSFR1_8822C << BIT_SHIFT_HTSFR1_8822C)
+#define BIT_CLEAR_HTSFR1_8822C(x) ((x) & (~BITS_HTSFR1_8822C))
+#define BIT_GET_HTSFR1_8822C(x) \
+ (((x) >> BIT_SHIFT_HTSFR1_8822C) & BIT_MASK_HTSFR1_8822C)
+#define BIT_SET_HTSFR1_8822C(x, v) \
+ (BIT_CLEAR_HTSFR1_8822C(x) | BIT_HTSFR1_8822C(v))
+
+#define BIT_SHIFT_HTSFR0_8822C 0
+#define BIT_MASK_HTSFR0_8822C 0xffff
+#define BIT_HTSFR0_8822C(x) \
+ (((x) & BIT_MASK_HTSFR0_8822C) << BIT_SHIFT_HTSFR0_8822C)
+#define BITS_HTSFR0_8822C (BIT_MASK_HTSFR0_8822C << BIT_SHIFT_HTSFR0_8822C)
+#define BIT_CLEAR_HTSFR0_8822C(x) ((x) & (~BITS_HTSFR0_8822C))
+#define BIT_GET_HTSFR0_8822C(x) \
+ (((x) >> BIT_SHIFT_HTSFR0_8822C) & BIT_MASK_HTSFR0_8822C)
+#define BIT_SET_HTSFR0_8822C(x, v) \
+ (BIT_CLEAR_HTSFR0_8822C(x) | BIT_HTSFR0_8822C(v))
+
+/* 2 REG_SDIO_HCPWM1_V2_8822C */
+#define BIT_TOGGLE_8822C BIT(7)
+#define BIT_CUR_PS_8822C BIT(0)
+
+/* 2 REG_SDIO_HCPWM2_V2_8822C */
+
+/* 2 REG_SDIO_INDIRECT_REG_CFG_8822C */
+#define BIT_INDIRECT_REG_RDY_8822C BIT(20)
+#define BIT_INDIRECT_REG_R_8822C BIT(19)
+#define BIT_INDIRECT_REG_W_8822C BIT(18)
+
+#define BIT_SHIFT_INDIRECT_REG_SIZE_8822C 16
+#define BIT_MASK_INDIRECT_REG_SIZE_8822C 0x3
+#define BIT_INDIRECT_REG_SIZE_8822C(x) \
+ (((x) & BIT_MASK_INDIRECT_REG_SIZE_8822C) \
+ << BIT_SHIFT_INDIRECT_REG_SIZE_8822C)
+#define BITS_INDIRECT_REG_SIZE_8822C \
+ (BIT_MASK_INDIRECT_REG_SIZE_8822C << BIT_SHIFT_INDIRECT_REG_SIZE_8822C)
+#define BIT_CLEAR_INDIRECT_REG_SIZE_8822C(x) \
+ ((x) & (~BITS_INDIRECT_REG_SIZE_8822C))
+#define BIT_GET_INDIRECT_REG_SIZE_8822C(x) \
+ (((x) >> BIT_SHIFT_INDIRECT_REG_SIZE_8822C) & \
+ BIT_MASK_INDIRECT_REG_SIZE_8822C)
+#define BIT_SET_INDIRECT_REG_SIZE_8822C(x, v) \
+ (BIT_CLEAR_INDIRECT_REG_SIZE_8822C(x) | BIT_INDIRECT_REG_SIZE_8822C(v))
+
+#define BIT_SHIFT_INDIRECT_REG_ADDR_8822C 0
+#define BIT_MASK_INDIRECT_REG_ADDR_8822C 0xffff
+#define BIT_INDIRECT_REG_ADDR_8822C(x) \
+ (((x) & BIT_MASK_INDIRECT_REG_ADDR_8822C) \
+ << BIT_SHIFT_INDIRECT_REG_ADDR_8822C)
+#define BITS_INDIRECT_REG_ADDR_8822C \
+ (BIT_MASK_INDIRECT_REG_ADDR_8822C << BIT_SHIFT_INDIRECT_REG_ADDR_8822C)
+#define BIT_CLEAR_INDIRECT_REG_ADDR_8822C(x) \
+ ((x) & (~BITS_INDIRECT_REG_ADDR_8822C))
+#define BIT_GET_INDIRECT_REG_ADDR_8822C(x) \
+ (((x) >> BIT_SHIFT_INDIRECT_REG_ADDR_8822C) & \
+ BIT_MASK_INDIRECT_REG_ADDR_8822C)
+#define BIT_SET_INDIRECT_REG_ADDR_8822C(x, v) \
+ (BIT_CLEAR_INDIRECT_REG_ADDR_8822C(x) | BIT_INDIRECT_REG_ADDR_8822C(v))
+
+/* 2 REG_SDIO_INDIRECT_REG_DATA_8822C */
+
+#define BIT_SHIFT_INDIRECT_REG_DATA_8822C 0
+#define BIT_MASK_INDIRECT_REG_DATA_8822C 0xffffffffL
+#define BIT_INDIRECT_REG_DATA_8822C(x) \
+ (((x) & BIT_MASK_INDIRECT_REG_DATA_8822C) \
+ << BIT_SHIFT_INDIRECT_REG_DATA_8822C)
+#define BITS_INDIRECT_REG_DATA_8822C \
+ (BIT_MASK_INDIRECT_REG_DATA_8822C << BIT_SHIFT_INDIRECT_REG_DATA_8822C)
+#define BIT_CLEAR_INDIRECT_REG_DATA_8822C(x) \
+ ((x) & (~BITS_INDIRECT_REG_DATA_8822C))
+#define BIT_GET_INDIRECT_REG_DATA_8822C(x) \
+ (((x) >> BIT_SHIFT_INDIRECT_REG_DATA_8822C) & \
+ BIT_MASK_INDIRECT_REG_DATA_8822C)
+#define BIT_SET_INDIRECT_REG_DATA_8822C(x, v) \
+ (BIT_CLEAR_INDIRECT_REG_DATA_8822C(x) | BIT_INDIRECT_REG_DATA_8822C(v))
+
+/* 2 REG_SDIO_H2C_8822C */
+
+#define BIT_SHIFT_SDIO_H2C_MSG_8822C 0
+#define BIT_MASK_SDIO_H2C_MSG_8822C 0xffffffffL
+#define BIT_SDIO_H2C_MSG_8822C(x) \
+ (((x) & BIT_MASK_SDIO_H2C_MSG_8822C) << BIT_SHIFT_SDIO_H2C_MSG_8822C)
+#define BITS_SDIO_H2C_MSG_8822C \
+ (BIT_MASK_SDIO_H2C_MSG_8822C << BIT_SHIFT_SDIO_H2C_MSG_8822C)
+#define BIT_CLEAR_SDIO_H2C_MSG_8822C(x) ((x) & (~BITS_SDIO_H2C_MSG_8822C))
+#define BIT_GET_SDIO_H2C_MSG_8822C(x) \
+ (((x) >> BIT_SHIFT_SDIO_H2C_MSG_8822C) & BIT_MASK_SDIO_H2C_MSG_8822C)
+#define BIT_SET_SDIO_H2C_MSG_8822C(x, v) \
+ (BIT_CLEAR_SDIO_H2C_MSG_8822C(x) | BIT_SDIO_H2C_MSG_8822C(v))
+
+/* 2 REG_SDIO_C2H_8822C */
+
+#define BIT_SHIFT_SDIO_C2H_MSG_8822C 0
+#define BIT_MASK_SDIO_C2H_MSG_8822C 0xffffffffL
+#define BIT_SDIO_C2H_MSG_8822C(x) \
+ (((x) & BIT_MASK_SDIO_C2H_MSG_8822C) << BIT_SHIFT_SDIO_C2H_MSG_8822C)
+#define BITS_SDIO_C2H_MSG_8822C \
+ (BIT_MASK_SDIO_C2H_MSG_8822C << BIT_SHIFT_SDIO_C2H_MSG_8822C)
+#define BIT_CLEAR_SDIO_C2H_MSG_8822C(x) ((x) & (~BITS_SDIO_C2H_MSG_8822C))
+#define BIT_GET_SDIO_C2H_MSG_8822C(x) \
+ (((x) >> BIT_SHIFT_SDIO_C2H_MSG_8822C) & BIT_MASK_SDIO_C2H_MSG_8822C)
+#define BIT_SET_SDIO_C2H_MSG_8822C(x, v) \
+ (BIT_CLEAR_SDIO_C2H_MSG_8822C(x) | BIT_SDIO_C2H_MSG_8822C(v))
+
+/* 2 REG_SDIO_HRPWM1_8822C */
+#define BIT_TOGGLE_8822C BIT(7)
+#define BIT_ACK_8822C BIT(6)
+#define BIT_REQ_PS_8822C BIT(0)
+
+/* 2 REG_SDIO_HRPWM2_8822C */
+
+/* 2 REG_SDIO_HPS_CLKR_8822C */
+
+/* 2 REG_SDIO_BUS_CTRL_8822C */
+#define BIT_INT_MASK_DIS_8822C BIT(4)
+#define BIT_PAD_CLK_XHGE_EN_8822C BIT(3)
+#define BIT_INTER_CLK_EN_8822C BIT(2)
+#define BIT_EN_RPT_TXCRC_8822C BIT(1)
+#define BIT_DIS_RXDMA_STS_8822C BIT(0)
+
+/* 2 REG_SDIO_HSUS_CTRL_8822C */
+#define BIT_INTR_CTRL_8822C BIT(4)
+#define BIT_SDIO_VOLTAGE_8822C BIT(3)
+#define BIT_BYPASS_INIT_8822C BIT(2)
+#define BIT_HCI_RESUME_RDY_8822C BIT(1)
+#define BIT_HCI_SUS_REQ_8822C BIT(0)
+
+/* 2 REG_SDIO_RESPONSE_TIMER_8822C */
+
+#define BIT_SHIFT_CMDIN_2RESP_TIMER_8822C 0
+#define BIT_MASK_CMDIN_2RESP_TIMER_8822C 0xffff
+#define BIT_CMDIN_2RESP_TIMER_8822C(x) \
+ (((x) & BIT_MASK_CMDIN_2RESP_TIMER_8822C) \
+ << BIT_SHIFT_CMDIN_2RESP_TIMER_8822C)
+#define BITS_CMDIN_2RESP_TIMER_8822C \
+ (BIT_MASK_CMDIN_2RESP_TIMER_8822C << BIT_SHIFT_CMDIN_2RESP_TIMER_8822C)
+#define BIT_CLEAR_CMDIN_2RESP_TIMER_8822C(x) \
+ ((x) & (~BITS_CMDIN_2RESP_TIMER_8822C))
+#define BIT_GET_CMDIN_2RESP_TIMER_8822C(x) \
+ (((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER_8822C) & \
+ BIT_MASK_CMDIN_2RESP_TIMER_8822C)
+#define BIT_SET_CMDIN_2RESP_TIMER_8822C(x, v) \
+ (BIT_CLEAR_CMDIN_2RESP_TIMER_8822C(x) | BIT_CMDIN_2RESP_TIMER_8822C(v))
+
+/* 2 REG_SDIO_CMD_CRC_8822C */
+
+#define BIT_SHIFT_SDIO_CMD_CRC_V1_8822C 0
+#define BIT_MASK_SDIO_CMD_CRC_V1_8822C 0xff
+#define BIT_SDIO_CMD_CRC_V1_8822C(x) \
+ (((x) & BIT_MASK_SDIO_CMD_CRC_V1_8822C) \
+ << BIT_SHIFT_SDIO_CMD_CRC_V1_8822C)
+#define BITS_SDIO_CMD_CRC_V1_8822C \
+ (BIT_MASK_SDIO_CMD_CRC_V1_8822C << BIT_SHIFT_SDIO_CMD_CRC_V1_8822C)
+#define BIT_CLEAR_SDIO_CMD_CRC_V1_8822C(x) ((x) & (~BITS_SDIO_CMD_CRC_V1_8822C))
+#define BIT_GET_SDIO_CMD_CRC_V1_8822C(x) \
+ (((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1_8822C) & \
+ BIT_MASK_SDIO_CMD_CRC_V1_8822C)
+#define BIT_SET_SDIO_CMD_CRC_V1_8822C(x, v) \
+ (BIT_CLEAR_SDIO_CMD_CRC_V1_8822C(x) | BIT_SDIO_CMD_CRC_V1_8822C(v))
+
+/* 2 REG_SDIO_HSISR_8822C */
+#define BIT_DRV_WLAN_INT_CLR_8822C BIT(1)
+#define BIT_DRV_WLAN_INT_8822C BIT(0)
+
+/* 2 REG_SDIO_HSIMR_8822C */
+#define BIT_HISR_MASK_8822C BIT(0)
+
+/* 2 REG_SDIO_DIOERR_RPT_8822C */
+#define BIT_SDIO_PAGE_ERR_8822C BIT(0)
+
+/* 2 REG_SDIO_CMD_ERRCNT_8822C */
+
+#define BIT_SHIFT_CMD_CRC_ERR_CNT_8822C 0
+#define BIT_MASK_CMD_CRC_ERR_CNT_8822C 0xff
+#define BIT_CMD_CRC_ERR_CNT_8822C(x) \
+ (((x) & BIT_MASK_CMD_CRC_ERR_CNT_8822C) \
+ << BIT_SHIFT_CMD_CRC_ERR_CNT_8822C)
+#define BITS_CMD_CRC_ERR_CNT_8822C \
+ (BIT_MASK_CMD_CRC_ERR_CNT_8822C << BIT_SHIFT_CMD_CRC_ERR_CNT_8822C)
+#define BIT_CLEAR_CMD_CRC_ERR_CNT_8822C(x) ((x) & (~BITS_CMD_CRC_ERR_CNT_8822C))
+#define BIT_GET_CMD_CRC_ERR_CNT_8822C(x) \
+ (((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT_8822C) & \
+ BIT_MASK_CMD_CRC_ERR_CNT_8822C)
+#define BIT_SET_CMD_CRC_ERR_CNT_8822C(x, v) \
+ (BIT_CLEAR_CMD_CRC_ERR_CNT_8822C(x) | BIT_CMD_CRC_ERR_CNT_8822C(v))
+
+/* 2 REG_SDIO_DATA_ERRCNT_8822C */
+
+#define BIT_SHIFT_DATA_CRC_ERR_CNT_8822C 0
+#define BIT_MASK_DATA_CRC_ERR_CNT_8822C 0xff
+#define BIT_DATA_CRC_ERR_CNT_8822C(x) \
+ (((x) & BIT_MASK_DATA_CRC_ERR_CNT_8822C) \
+ << BIT_SHIFT_DATA_CRC_ERR_CNT_8822C)
+#define BITS_DATA_CRC_ERR_CNT_8822C \
+ (BIT_MASK_DATA_CRC_ERR_CNT_8822C << BIT_SHIFT_DATA_CRC_ERR_CNT_8822C)
+#define BIT_CLEAR_DATA_CRC_ERR_CNT_8822C(x) \
+ ((x) & (~BITS_DATA_CRC_ERR_CNT_8822C))
+#define BIT_GET_DATA_CRC_ERR_CNT_8822C(x) \
+ (((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT_8822C) & \
+ BIT_MASK_DATA_CRC_ERR_CNT_8822C)
+#define BIT_SET_DATA_CRC_ERR_CNT_8822C(x, v) \
+ (BIT_CLEAR_DATA_CRC_ERR_CNT_8822C(x) | BIT_DATA_CRC_ERR_CNT_8822C(v))
+
+/* 2 REG_SDIO_CMD_ERR_CONTENT_8822C */
+
+#define BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822C 0
+#define BIT_MASK_SDIO_CMD_ERR_CONTENT_8822C 0xffffffffffL
+#define BIT_SDIO_CMD_ERR_CONTENT_8822C(x) \
+ (((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8822C) \
+ << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822C)
+#define BITS_SDIO_CMD_ERR_CONTENT_8822C \
+ (BIT_MASK_SDIO_CMD_ERR_CONTENT_8822C \
+ << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822C)
+#define BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8822C(x) \
+ ((x) & (~BITS_SDIO_CMD_ERR_CONTENT_8822C))
+#define BIT_GET_SDIO_CMD_ERR_CONTENT_8822C(x) \
+ (((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8822C) & \
+ BIT_MASK_SDIO_CMD_ERR_CONTENT_8822C)
+#define BIT_SET_SDIO_CMD_ERR_CONTENT_8822C(x, v) \
+ (BIT_CLEAR_SDIO_CMD_ERR_CONTENT_8822C(x) | \
+ BIT_SDIO_CMD_ERR_CONTENT_8822C(v))
+
+/* 2 REG_SDIO_CRC_ERR_IDX_8822C */
+#define BIT_D3_CRC_ERR_8822C BIT(4)
+#define BIT_D2_CRC_ERR_8822C BIT(3)
+#define BIT_D1_CRC_ERR_8822C BIT(2)
+#define BIT_D0_CRC_ERR_8822C BIT(1)
+#define BIT_CMD_CRC_ERR_8822C BIT(0)
+
+/* 2 REG_SDIO_DATA_CRC_8822C */
+
+#define BIT_SHIFT_SDIO_DATA_CRC_8822C 0
+#define BIT_MASK_SDIO_DATA_CRC_8822C 0xffff
+#define BIT_SDIO_DATA_CRC_8822C(x) \
+ (((x) & BIT_MASK_SDIO_DATA_CRC_8822C) << BIT_SHIFT_SDIO_DATA_CRC_8822C)
+#define BITS_SDIO_DATA_CRC_8822C \
+ (BIT_MASK_SDIO_DATA_CRC_8822C << BIT_SHIFT_SDIO_DATA_CRC_8822C)
+#define BIT_CLEAR_SDIO_DATA_CRC_8822C(x) ((x) & (~BITS_SDIO_DATA_CRC_8822C))
+#define BIT_GET_SDIO_DATA_CRC_8822C(x) \
+ (((x) >> BIT_SHIFT_SDIO_DATA_CRC_8822C) & BIT_MASK_SDIO_DATA_CRC_8822C)
+#define BIT_SET_SDIO_DATA_CRC_8822C(x, v) \
+ (BIT_CLEAR_SDIO_DATA_CRC_8822C(x) | BIT_SDIO_DATA_CRC_8822C(v))
+
+/* 2 REG_SDIO_TRANS_FIFO_STATUS_8822C */
+#define BIT_TRANS_FIFO_UNDERFLOW_8822C BIT(1)
+#define BIT_TRANS_FIFO_OVERFLOW_8822C BIT(0)
+
+#endif
diff --git a/hal/halmac/halmac_fw_info.h b/hal/halmac/halmac_fw_info.h
index 4b821db..1da64fb 100644
--- a/hal/halmac/halmac_fw_info.h
+++ b/hal/halmac/halmac_fw_info.h
@@ -1,22 +1,56 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
#ifndef _HALMAC_FW_INFO_H_
#define _HALMAC_FW_INFO_H_
-#define H2C_FORMAT_VERSION 4
-
-#define H2C_ACK_HDR_CONTENT_LENGTH 8
-#define CFG_PARAMETER_ACK_CONTENT_LENGTH 16
-#define SCAN_STATUS_RPT_CONTENT_LENGTH 4
-#define C2H_DBG_HEADER_LENGTH 4
-#define C2H_DBG_CONTENT_MAX_LENGTH 228
-
-#define C2H_DBG_CONTENT_SEQ_OFFSET 1
+#define H2C_FORMAT_VERSION 11
+
+/* FW bin information */
+#define WLAN_FW_HDR_SIZE 64
+#define WLAN_FW_HDR_CHKSUM_SIZE 8
+
+#define WLAN_FW_HDR_VERSION 4
+#define WLAN_FW_HDR_SUBVERSION 6
+#define WLAN_FW_HDR_SUBINDEX 7
+#define WLAN_FW_HDR_MONTH 16
+#define WLAN_FW_HDR_DATE 17
+#define WLAN_FW_HDR_HOUR 18
+#define WLAN_FW_HDR_MIN 19
+#define WLAN_FW_HDR_YEAR 20
+#define WLAN_FW_HDR_MEM_USAGE 24
+#define WLAN_FW_HDR_H2C_FMT_VER 28
+#define WLAN_FW_HDR_DMEM_ADDR 32
+#define WLAN_FW_HDR_DMEM_SIZE 36
+#define WLAN_FW_HDR_IMEM_SIZE 48
+#define WLAN_FW_HDR_EMEM_SIZE 52
+#define WLAN_FW_HDR_EMEM_ADDR 56
+#define WLAN_FW_HDR_IMEM_ADDR 60
+
+#define H2C_ACK_HDR_CONTENT_LENGTH 8
+#define CFG_PARAMETER_ACK_CONTENT_LENGTH 16
+#define SCAN_STATUS_RPT_CONTENT_LENGTH 4
+#define C2H_DBG_HDR_LEN 4
+#define C2H_DBG_CONTENT_MAX_LENGTH 228
+#define C2H_DBG_CONTENT_SEQ_OFFSET 1
/* Rename from FW SysHalCom_Debug_RAM.h */
-#define FW_REG_H2CPKT_DONE_SEQ 0x1C8
-#define FW_REG_WoW_REASON 0x1C7
+#define FW_REG_H2CPKT_DONE_SEQ 0x1C8
+#define FW_REG_WOW_REASON 0x1C7
-
-typedef enum _HALMAC_DATA_TYPE {
+enum halmac_data_type {
HALMAC_DATA_TYPE_MAC_REG = 0x00,
HALMAC_DATA_TYPE_BB_REG = 0x01,
HALMAC_DATA_TYPE_RADIO_A = 0x02,
@@ -29,73 +63,57 @@ typedef enum _HALMAC_DATA_TYPE {
HALMAC_DATA_TYPE_DRV_DEFINE_2 = 0x82,
HALMAC_DATA_TYPE_DRV_DEFINE_3 = 0x83,
HALMAC_DATA_TYPE_UNDEFINE = 0x7FFFFFFF,
-} HALMAC_DATA_TYPE;
+};
-typedef enum _HALMAC_PACKET_ID {
+enum halmac_packet_id {
HALMAC_PACKET_PROBE_REQ = 0x00,
HALMAC_PACKET_SYNC_BCN = 0x01,
HALMAC_PACKET_DISCOVERY_BCN = 0x02,
-
HALMAC_PACKET_UNDEFINE = 0x7FFFFFFF,
-} HALMAC_PACKET_ID;
+};
-/* Channel Switch Action ID */
-typedef enum _HALMAC_CS_ACTION_ID {
+enum halmac_cs_action_id {
HALMAC_CS_ACTION_NONE = 0x00,
HALMAC_CS_ACTIVE_SCAN = 0x01,
HALMAC_CS_NAN_NONMASTER_DW = 0x02,
HALMAC_CS_NAN_NONMASTER_NONDW = 0x03,
HALMAC_CS_NAN_MASTER_NONDW = 0x04,
HALMAC_CS_NAN_MASTER_DW = 0x05,
-
HALMAC_CS_ACTION_UNDEFINE = 0x7FFFFFFF,
-} HALMAC_CS_ACTION_ID;
+};
-/* Channel Switch Extra Action ID */
-typedef enum _HALMAC_CS_EXTRA_ACTION_ID {
+enum halmac_cs_extra_action_id {
HALMAC_CS_EXTRA_ACTION_NONE = 0x00,
HALMAC_CS_EXTRA_UPDATE_PROBE = 0x01,
HALMAC_CS_EXTRA_UPDATE_BEACON = 0x02,
-
-
HALMAC_CS_EXTRA_ACTION_UNDEFINE = 0x7FFFFFFF,
-} HALMAC_CS_EXTRA_ACTION_ID;
+};
-typedef enum _HALMAC_H2C_RETURN_CODE {
+enum halmac_h2c_return_code {
HALMAC_H2C_RETURN_SUCCESS = 0x00,
HALMAC_H2C_RETURN_CFG_ERR_LEN = 0x01,
HALMAC_H2C_RETURN_CFG_ERR_CMD = 0x02,
-
HALMAC_H2C_RETURN_EFUSE_ERR_DUMP = 0x03,
-
- HALMAC_H2C_RETURN_DATAPACK_ERR_FULL = 0x04, /* DMEM buffer full */
- HALMAC_H2C_RETURN_DATAPACK_ERR_ID = 0x05, /* Invalid pack id */
-
- HALMAC_H2C_RETURN_RUN_ERR_EMPTY = 0x06, /* No data in dedicated buffer */
+ HALMAC_H2C_RETURN_DATAPACK_ERR_FULL = 0x04,
+ HALMAC_H2C_RETURN_DATAPACK_ERR_ID = 0x05,
+ HALMAC_H2C_RETURN_RUN_ERR_EMPTY = 0x06,
HALMAC_H2C_RETURN_RUN_ERR_LEN = 0x07,
HALMAC_H2C_RETURN_RUN_ERR_CMD = 0x08,
- HALMAC_H2C_RETURN_RUN_ERR_ID = 0x09, /* Invalid pack id */
-
- HALMAC_H2C_RETURN_PACKET_ERR_FULL = 0x0A, /* DMEM buffer full */
- HALMAC_H2C_RETURN_PACKET_ERR_ID = 0x0B, /* Invalid packet id */
-
- HALMAC_H2C_RETURN_SCAN_ERR_FULL = 0x0C, /* DMEM buffer full */
- HALMAC_H2C_RETURN_SCAN_ERR_PHYDM = 0x0D, /* PHYDM API return fail */
-
- HALMAC_H2C_RETURN_ORIG_ERR_ID = 0x0E, /* Invalid original H2C cmd id */
-
+ HALMAC_H2C_RETURN_RUN_ERR_ID = 0x09,
+ HALMAC_H2C_RETURN_PACKET_ERR_FULL = 0x0A,
+ HALMAC_H2C_RETURN_PACKET_ERR_ID = 0x0B,
+ HALMAC_H2C_RETURN_SCAN_ERR_FULL = 0x0C,
+ HALMAC_H2C_RETURN_SCAN_ERR_PHYDM = 0x0D,
+ HALMAC_H2C_RETURN_ORIG_ERR_ID = 0x0E,
HALMAC_H2C_RETURN_UNDEFINE = 0x7FFFFFFF,
-} HALMAC_H2C_RETURN_CODE;
-
-typedef enum _HALMAC_SCAN_REPORT_CODE {
- HALMAC_SCAN_REPORT_DONE = 0x00,
- HALMAC_SCAN_REPORT_ERR_PHYDM = 0x01, /* PHYDM API return fail */
- HALMAC_SCAN_REPORT_ERR_ID = 0x02, /* Invalid ActionID */
- HALMAC_SCAN_REPORT_ERR_TX = 0x03, /* Tx RsvdPage fail */
+};
+enum halmac_scan_report_code {
+ HALMAC_SCAN_REPORT_DONE = 0x00,
+ HALMAC_SCAN_REPORT_ERR_PHYDM = 0x01,
+ HALMAC_SCAN_REPORT_ERR_ID = 0x02,
+ HALMAC_SCAN_REPORT_ERR_TX = 0x03,
HALMAC_SCAN_REPORT_UNDEFINE = 0x7FFFFFFF,
-} HALMAC_SCAN_REPORT_CODE;
-
-
+};
#endif
diff --git a/hal/halmac/halmac_fw_offload_c2h_ap.h b/hal/halmac/halmac_fw_offload_c2h_ap.h
index b2f9ecb..635443e 100644
--- a/hal/halmac/halmac_fw_offload_c2h_ap.h
+++ b/hal/halmac/halmac_fw_offload_c2h_ap.h
@@ -1,120 +1,506 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
#ifndef _HAL_FWOFFLOADC2HFORMAT_H2C_C2H_AP_H_
#define _HAL_FWOFFLOADC2HFORMAT_H2C_C2H_AP_H_
-#define C2H_SUB_CMD_ID_C2H_DBG 0X00
-#define C2H_SUB_CMD_ID_BT_COEX_INFO 0X02
-#define C2H_SUB_CMD_ID_SCAN_STATUS_RPT 0X03
-#define C2H_SUB_CMD_ID_H2C_ACK_HDR 0X01
-#define C2H_SUB_CMD_ID_CFG_PARAMETER_ACK 0X01
-#define C2H_SUB_CMD_ID_BT_COEX_ACK 0X01
-#define C2H_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0X01
-#define C2H_SUB_CMD_ID_UPDATE_PACKET_ACK 0X01
-#define C2H_SUB_CMD_ID_UPDATE_DATAPACK_ACK 0X01
-#define C2H_SUB_CMD_ID_RUN_DATAPACK_ACK 0X01
-#define C2H_SUB_CMD_ID_CHANNEL_SWITCH_ACK 0X01
-#define C2H_SUB_CMD_ID_IQK_ACK 0X01
-#define C2H_SUB_CMD_ID_POWER_TRACKING_ACK 0X01
-#define C2H_SUB_CMD_ID_PSD_ACK 0X01
-#define C2H_SUB_CMD_ID_PSD_DATA 0X04
-#define C2H_SUB_CMD_ID_EFUSE_DATA 0X05
-#define H2C_SUB_CMD_ID_CFG_PARAMETER_ACK SUB_CMD_ID_CFG_PARAMETER
+#define C2H_SUB_CMD_ID_C2H_DBG 0X00
+#define C2H_SUB_CMD_ID_BT_COEX_INFO 0X02
+#define C2H_SUB_CMD_ID_SCAN_STATUS_RPT 0X03
+#define C2H_SUB_CMD_ID_H2C_ACK_HDR 0X01
+#define C2H_SUB_CMD_ID_CFG_PARAM_ACK 0X01
+#define C2H_SUB_CMD_ID_BT_COEX_ACK 0X01
+#define C2H_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0X01
+#define C2H_SUB_CMD_ID_UPDATE_PKT_ACK 0X01
+#define C2H_SUB_CMD_ID_UPDATE_DATAPACK_ACK 0X01
+#define C2H_SUB_CMD_ID_RUN_DATAPACK_ACK 0X01
+#define C2H_SUB_CMD_ID_CH_SWITCH_ACK 0X01
+#define C2H_SUB_CMD_ID_IQK_ACK 0X01
+#define C2H_SUB_CMD_ID_PWR_TRK_ACK 0X01
+#define C2H_SUB_CMD_ID_PSD_ACK 0X01
+#define C2H_SUB_CMD_ID_PSD_DATA 0X04
+#define C2H_SUB_CMD_ID_EFUSE_DATA 0X05
+#define C2H_SUB_CMD_ID_IQK_DATA 0X06
+#define C2H_SUB_CMD_ID_C2H_PKT_FTM_DBG 0X07
+#define C2H_SUB_CMD_ID_C2H_PKT_FTM_2_DBG 0X08
+#define C2H_SUB_CMD_ID_C2H_PKT_FTM_3_DBG 0X09
+#define C2H_SUB_CMD_ID_C2H_PKT_FTM_4_DBG 0X0A
+#define C2H_SUB_CMD_ID_FTMACKRPT_HDL_DBG 0X0B
+#define C2H_SUB_CMD_ID_FTMC2H_RPT 0X0C
+#define C2H_SUB_CMD_ID_DRVFTMC2H_RPT 0X0D
+#define C2H_SUB_CMD_ID_C2H_PKT_FTM_5_DBG 0X0E
+#define C2H_SUB_CMD_ID_CCX_RPT 0X0F
+#define C2H_SUB_CMD_ID_C2H_PKT_NAN_RPT 0X10
+#define C2H_SUB_CMD_ID_C2H_PKT_ATM_RPT 0X11
+#define C2H_SUB_CMD_ID_C2H_PKT_FTMSESSION_END 0X1C
+#define C2H_SUB_CMD_ID_C2H_PKT_DETECT_THERMAL 0X1D
+#define C2H_SUB_CMD_ID_FW_DBG_MSG 0XFF
+#define C2H_SUB_CMD_ID_FW_SNDING_ACK 0X01
+#define C2H_SUB_CMD_ID_FW_FWCTRL_RPT 0X1F
+#define C2H_SUB_CMD_ID_H2C_LOOPBACK_ACK 0X20
+#define C2H_SUB_CMD_ID_FWCMD_LOOPBACK_ACK 0X21
+#define H2C_SUB_CMD_ID_CFG_PARAM_ACK SUB_CMD_ID_CFG_PARAM
#define H2C_SUB_CMD_ID_BT_COEX_ACK SUB_CMD_ID_BT_COEX
#define H2C_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK SUB_CMD_ID_DUMP_PHYSICAL_EFUSE
-#define H2C_SUB_CMD_ID_UPDATE_PACKET_ACK SUB_CMD_ID_UPDATE_PACKET
+#define H2C_SUB_CMD_ID_UPDATE_PKT_ACK SUB_CMD_ID_UPDATE_PKT
#define H2C_SUB_CMD_ID_UPDATE_DATAPACK_ACK SUB_CMD_ID_UPDATE_DATAPACK
#define H2C_SUB_CMD_ID_RUN_DATAPACK_ACK SUB_CMD_ID_RUN_DATAPACK
-#define H2C_SUB_CMD_ID_CHANNEL_SWITCH_ACK SUB_CMD_ID_CHANNEL_SWITCH
+#define H2C_SUB_CMD_ID_CH_SWITCH_ACK SUB_CMD_ID_CH_SWITCH
#define H2C_SUB_CMD_ID_IQK_ACK SUB_CMD_ID_IQK
-#define H2C_SUB_CMD_ID_POWER_TRACKING_ACK SUB_CMD_ID_POWER_TRACKING
+#define H2C_SUB_CMD_ID_PWR_TRK_ACK SUB_CMD_ID_PWR_TRK
#define H2C_SUB_CMD_ID_PSD_ACK SUB_CMD_ID_PSD
-#define H2C_CMD_ID_CFG_PARAMETER_ACK 0XFF
-#define H2C_CMD_ID_BT_COEX_ACK 0XFF
-#define H2C_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0XFF
-#define H2C_CMD_ID_UPDATE_PACKET_ACK 0XFF
-#define H2C_CMD_ID_UPDATE_DATAPACK_ACK 0XFF
-#define H2C_CMD_ID_RUN_DATAPACK_ACK 0XFF
-#define H2C_CMD_ID_CHANNEL_SWITCH_ACK 0XFF
-#define H2C_CMD_ID_IQK_ACK 0XFF
-#define H2C_CMD_ID_POWER_TRACKING_ACK 0XFF
-#define H2C_CMD_ID_PSD_ACK 0XFF
-#define C2H_HDR_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8)
-#define C2H_HDR_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value)
-#define C2H_HDR_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value)
-#define C2H_HDR_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8)
-#define C2H_HDR_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value)
-#define C2H_HDR_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value)
-#define C2H_HDR_GET_C2H_SUB_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 8)
-#define C2H_HDR_SET_C2H_SUB_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 8, __Value)
-#define C2H_HDR_SET_C2H_SUB_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 8, __Value)
-#define C2H_HDR_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 24, 8)
-#define C2H_HDR_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 24, 8, __Value)
-#define C2H_HDR_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 24, 8, __Value)
-#define C2H_DBG_GET_DBG_MSG(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 8)
-#define C2H_DBG_SET_DBG_MSG(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 8, __Value)
-#define C2H_DBG_SET_DBG_MSG_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 8, __Value)
-#define BT_COEX_INFO_GET_DATA_START(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 8)
-#define BT_COEX_INFO_SET_DATA_START(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 8, __Value)
-#define BT_COEX_INFO_SET_DATA_START_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 8, __Value)
-#define SCAN_STATUS_RPT_GET_H2C_RETURN_CODE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 8)
-#define SCAN_STATUS_RPT_SET_H2C_RETURN_CODE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 8, __Value)
-#define SCAN_STATUS_RPT_SET_H2C_RETURN_CODE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 8, __Value)
-#define SCAN_STATUS_RPT_GET_H2C_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 16)
-#define SCAN_STATUS_RPT_SET_H2C_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 16, __Value)
-#define SCAN_STATUS_RPT_SET_H2C_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 16, __Value)
-#define H2C_ACK_HDR_GET_H2C_RETURN_CODE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 8)
-#define H2C_ACK_HDR_SET_H2C_RETURN_CODE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 8, __Value)
-#define H2C_ACK_HDR_SET_H2C_RETURN_CODE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 8, __Value)
-#define H2C_ACK_HDR_GET_H2C_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8)
-#define H2C_ACK_HDR_SET_H2C_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value)
-#define H2C_ACK_HDR_SET_H2C_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value)
-#define H2C_ACK_HDR_GET_H2C_SUB_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 16)
-#define H2C_ACK_HDR_SET_H2C_SUB_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 16, __Value)
-#define H2C_ACK_HDR_SET_H2C_SUB_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 16, __Value)
-#define H2C_ACK_HDR_GET_H2C_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 0, 16)
-#define H2C_ACK_HDR_SET_H2C_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 0, 16, __Value)
-#define H2C_ACK_HDR_SET_H2C_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 0, 16, __Value)
-#define CFG_PARAMETER_ACK_GET_OFFSET_ACCUMULATION(__pC2H) GET_C2H_FIELD(__pC2H + 0XC, 0, 32)
-#define CFG_PARAMETER_ACK_SET_OFFSET_ACCUMULATION(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0XC, 0, 32, __Value)
-#define CFG_PARAMETER_ACK_SET_OFFSET_ACCUMULATION_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0XC, 0, 32, __Value)
-#define CFG_PARAMETER_ACK_GET_VALUE_ACCUMULATION(__pC2H) GET_C2H_FIELD(__pC2H + 0X10, 0, 32)
-#define CFG_PARAMETER_ACK_SET_VALUE_ACCUMULATION(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X10, 0, 32, __Value)
-#define CFG_PARAMETER_ACK_SET_VALUE_ACCUMULATION_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X10, 0, 32, __Value)
-#define BT_COEX_ACK_GET_DATA_START(__pC2H) GET_C2H_FIELD(__pC2H + 0XC, 0, 8)
-#define BT_COEX_ACK_SET_DATA_START(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0XC, 0, 8, __Value)
-#define BT_COEX_ACK_SET_DATA_START_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0XC, 0, 8, __Value)
-#define PSD_DATA_GET_SEGMENT_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 7)
-#define PSD_DATA_SET_SEGMENT_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 7, __Value)
-#define PSD_DATA_SET_SEGMENT_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 7, __Value)
-#define PSD_DATA_GET_END_SEGMENT(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 7, 1)
-#define PSD_DATA_SET_END_SEGMENT(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 7, 1, __Value)
-#define PSD_DATA_SET_END_SEGMENT_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 7, 1, __Value)
-#define PSD_DATA_GET_SEGMENT_SIZE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8)
-#define PSD_DATA_SET_SEGMENT_SIZE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value)
-#define PSD_DATA_SET_SEGMENT_SIZE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value)
-#define PSD_DATA_GET_TOTAL_SIZE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 16)
-#define PSD_DATA_SET_TOTAL_SIZE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 16, __Value)
-#define PSD_DATA_SET_TOTAL_SIZE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 16, __Value)
-#define PSD_DATA_GET_H2C_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X8, 0, 16)
-#define PSD_DATA_SET_H2C_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X8, 0, 16, __Value)
-#define PSD_DATA_SET_H2C_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X8, 0, 16, __Value)
-#define PSD_DATA_GET_DATA_START(__pC2H) GET_C2H_FIELD(__pC2H + 0X8, 16, 8)
-#define PSD_DATA_SET_DATA_START(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X8, 16, 8, __Value)
-#define PSD_DATA_SET_DATA_START_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X8, 16, 8, __Value)
-#define EFUSE_DATA_GET_SEGMENT_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 7)
-#define EFUSE_DATA_SET_SEGMENT_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 7, __Value)
-#define EFUSE_DATA_SET_SEGMENT_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 7, __Value)
-#define EFUSE_DATA_GET_END_SEGMENT(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 7, 1)
-#define EFUSE_DATA_SET_END_SEGMENT(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 7, 1, __Value)
-#define EFUSE_DATA_SET_END_SEGMENT_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 7, 1, __Value)
-#define EFUSE_DATA_GET_SEGMENT_SIZE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8)
-#define EFUSE_DATA_SET_SEGMENT_SIZE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value)
-#define EFUSE_DATA_SET_SEGMENT_SIZE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value)
-#define EFUSE_DATA_GET_TOTAL_SIZE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 16)
-#define EFUSE_DATA_SET_TOTAL_SIZE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 16, __Value)
-#define EFUSE_DATA_SET_TOTAL_SIZE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 16, __Value)
-#define EFUSE_DATA_GET_H2C_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X8, 0, 16)
-#define EFUSE_DATA_SET_H2C_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X8, 0, 16, __Value)
-#define EFUSE_DATA_SET_H2C_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X8, 0, 16, __Value)
-#define EFUSE_DATA_GET_DATA_START(__pC2H) GET_C2H_FIELD(__pC2H + 0X8, 16, 8)
-#define EFUSE_DATA_SET_DATA_START(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X8, 16, 8, __Value)
-#define EFUSE_DATA_SET_DATA_START_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X8, 16, 8, __Value)
+#define H2C_SUB_CMD_ID_CCX_RPT SUB_CMD_ID_CCX_RPT
+#define H2C_SUB_CMD_ID_FW_DBG_MSG SUB_CMD_ID_FW_DBG_MSG
+#define H2C_SUB_CMD_ID_FW_SNDING_ACK SUB_CMD_ID_FW_SNDING
+#define H2C_SUB_CMD_ID_FW_FWCTRL_RPT SUB_CMD_ID_FW_FWCTRL_RPT
+#define H2C_SUB_CMD_ID_H2C_LOOPBACK_ACK SUB_CMD_ID_H2C_LOOPBACK
+#define H2C_SUB_CMD_ID_FWCMD_LOOPBACK_ACK SUB_CMD_ID_FWCMD_LOOPBACK
+#define H2C_CMD_ID_CFG_PARAM_ACK 0XFF
+#define H2C_CMD_ID_BT_COEX_ACK 0XFF
+#define H2C_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0XFF
+#define H2C_CMD_ID_UPDATE_PKT_ACK 0XFF
+#define H2C_CMD_ID_UPDATE_DATAPACK_ACK 0XFF
+#define H2C_CMD_ID_RUN_DATAPACK_ACK 0XFF
+#define H2C_CMD_ID_CH_SWITCH_ACK 0XFF
+#define H2C_CMD_ID_IQK_ACK 0XFF
+#define H2C_CMD_ID_PWR_TRK_ACK 0XFF
+#define H2C_CMD_ID_PSD_ACK 0XFF
+#define H2C_CMD_ID_CCX_RPT 0XFF
+#define H2C_CMD_ID_FW_DBG_MSG 0XFF
+#define H2C_CMD_ID_FW_SNDING_ACK 0XFF
+#define H2C_CMD_ID_FW_FWCTRL_RPT 0XFF
+#define H2C_CMD_ID_H2C_LOOPBACK_ACK 0XFF
+#define H2C_CMD_ID_FWCMD_LOOPBACK_ACK 0XFF
+#define C2H_HDR_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define C2H_HDR_SET_CMD_ID(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_HDR_SET_CMD_ID_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_HDR_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define C2H_HDR_SET_SEQ(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_HDR_SET_SEQ_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_HDR_GET_C2H_SUB_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8)
+#define C2H_HDR_SET_C2H_SUB_CMD_ID(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_HDR_SET_C2H_SUB_CMD_ID_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_HDR_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8)
+#define C2H_HDR_SET_LEN(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_HDR_SET_LEN_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_DBG_GET_DBG_MSG(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
+#define C2H_DBG_SET_DBG_MSG(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define C2H_DBG_SET_DBG_MSG_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define BT_COEX_INFO_GET_DATA_START(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
+#define BT_COEX_INFO_SET_DATA_START(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define BT_COEX_INFO_SET_DATA_START_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define SCAN_STATUS_RPT_GET_H2C_RETURN_CODE(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
+#define SCAN_STATUS_RPT_SET_H2C_RETURN_CODE(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define SCAN_STATUS_RPT_SET_H2C_RETURN_CODE_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define SCAN_STATUS_RPT_GET_H2C_SEQ(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X04, 16, 16)
+#define SCAN_STATUS_RPT_SET_H2C_SEQ(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 16, value)
+#define SCAN_STATUS_RPT_SET_H2C_SEQ_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 16, value)
+#define H2C_ACK_HDR_GET_H2C_RETURN_CODE(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
+#define H2C_ACK_HDR_SET_H2C_RETURN_CODE(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define H2C_ACK_HDR_SET_H2C_RETURN_CODE_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define H2C_ACK_HDR_GET_H2C_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
+#define H2C_ACK_HDR_SET_H2C_CMD_ID(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define H2C_ACK_HDR_SET_H2C_CMD_ID_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define H2C_ACK_HDR_GET_H2C_SUB_CMD_ID(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X04, 16, 16)
+#define H2C_ACK_HDR_SET_H2C_SUB_CMD_ID(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 16, value)
+#define H2C_ACK_HDR_SET_H2C_SUB_CMD_ID_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 16, value)
+#define H2C_ACK_HDR_GET_H2C_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 0, 16)
+#define H2C_ACK_HDR_SET_H2C_SEQ(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 16, value)
+#define H2C_ACK_HDR_SET_H2C_SEQ_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 16, value)
+#define CFG_PARAM_ACK_GET_OFFSET_ACCUMULATION(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0XC, 0, 32)
+#define CFG_PARAM_ACK_SET_OFFSET_ACCUMULATION(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 0, 32, value)
+#define CFG_PARAM_ACK_SET_OFFSET_ACCUMULATION_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 0, 32, value)
+#define CFG_PARAM_ACK_GET_VALUE_ACCUMULATION(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X10, 0, 32)
+#define CFG_PARAM_ACK_SET_VALUE_ACCUMULATION(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X10, 0, 32, value)
+#define CFG_PARAM_ACK_SET_VALUE_ACCUMULATION_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X10, 0, 32, value)
+#define BT_COEX_ACK_GET_DATA_START(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 0, 8)
+#define BT_COEX_ACK_SET_DATA_START(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 0, 8, value)
+#define BT_COEX_ACK_SET_DATA_START_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 0, 8, value)
+#define PSD_DATA_GET_SEGMENT_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 7)
+#define PSD_DATA_SET_SEGMENT_ID(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 7, value)
+#define PSD_DATA_SET_SEGMENT_ID_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 7, value)
+#define PSD_DATA_GET_END_SEGMENT(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 7, 1)
+#define PSD_DATA_SET_END_SEGMENT(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 7, 1, value)
+#define PSD_DATA_SET_END_SEGMENT_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 7, 1, value)
+#define PSD_DATA_GET_SEGMENT_SIZE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
+#define PSD_DATA_SET_SEGMENT_SIZE(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define PSD_DATA_SET_SEGMENT_SIZE_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define PSD_DATA_GET_TOTAL_SIZE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 16)
+#define PSD_DATA_SET_TOTAL_SIZE(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 16, value)
+#define PSD_DATA_SET_TOTAL_SIZE_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 16, value)
+#define PSD_DATA_GET_H2C_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 0, 16)
+#define PSD_DATA_SET_H2C_SEQ(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 0, 16, value)
+#define PSD_DATA_SET_H2C_SEQ_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 0, 16, value)
+#define PSD_DATA_GET_DATA_START(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 16, 8)
+#define PSD_DATA_SET_DATA_START(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 16, 8, value)
+#define PSD_DATA_SET_DATA_START_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 16, 8, value)
+#define EFUSE_DATA_GET_SEGMENT_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 7)
+#define EFUSE_DATA_SET_SEGMENT_ID(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 7, value)
+#define EFUSE_DATA_SET_SEGMENT_ID_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 7, value)
+#define EFUSE_DATA_GET_END_SEGMENT(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 7, 1)
+#define EFUSE_DATA_SET_END_SEGMENT(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 7, 1, value)
+#define EFUSE_DATA_SET_END_SEGMENT_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 7, 1, value)
+#define EFUSE_DATA_GET_SEGMENT_SIZE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
+#define EFUSE_DATA_SET_SEGMENT_SIZE(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define EFUSE_DATA_SET_SEGMENT_SIZE_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define EFUSE_DATA_GET_TOTAL_SIZE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 16)
+#define EFUSE_DATA_SET_TOTAL_SIZE(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 16, value)
+#define EFUSE_DATA_SET_TOTAL_SIZE_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 16, value)
+#define EFUSE_DATA_GET_H2C_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 0, 16)
+#define EFUSE_DATA_SET_H2C_SEQ(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 0, 16, value)
+#define EFUSE_DATA_SET_H2C_SEQ_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 0, 16, value)
+#define EFUSE_DATA_GET_DATA_START(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 16, 8)
+#define EFUSE_DATA_SET_DATA_START(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 16, 8, value)
+#define EFUSE_DATA_SET_DATA_START_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 16, 8, value)
+#define IQK_DATA_GET_SEGMENT_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 7)
+#define IQK_DATA_SET_SEGMENT_ID(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 7, value)
+#define IQK_DATA_SET_SEGMENT_ID_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 7, value)
+#define IQK_DATA_GET_END_SEGMENT(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 7, 1)
+#define IQK_DATA_SET_END_SEGMENT(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 7, 1, value)
+#define IQK_DATA_SET_END_SEGMENT_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 7, 1, value)
+#define IQK_DATA_GET_SEGMENT_SIZE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
+#define IQK_DATA_SET_SEGMENT_SIZE(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define IQK_DATA_SET_SEGMENT_SIZE_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define IQK_DATA_GET_TOTAL_SIZE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 16)
+#define IQK_DATA_SET_TOTAL_SIZE(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 16, value)
+#define IQK_DATA_SET_TOTAL_SIZE_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 16, value)
+#define IQK_DATA_GET_H2C_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 0, 16)
+#define IQK_DATA_SET_H2C_SEQ(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 0, 16, value)
+#define IQK_DATA_SET_H2C_SEQ_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 0, 16, value)
+#define IQK_DATA_GET_DATA_START(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 16, 8)
+#define IQK_DATA_SET_DATA_START(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 16, 8, value)
+#define IQK_DATA_SET_DATA_START_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 16, 8, value)
+#define CCX_RPT_GET_POLLUTED(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X4, 0, 1)
+#define CCX_RPT_SET_POLLUTED(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X4, 0, 1, value)
+#define CCX_RPT_SET_POLLUTED_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 0, 1, value)
+#define CCX_RPT_GET_RPT_SEL(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X4, 5, 3)
+#define CCX_RPT_SET_RPT_SEL(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X4, 5, 3, value)
+#define CCX_RPT_SET_RPT_SEL_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 5, 3, value)
+#define CCX_RPT_GET_QSEL(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X4, 8, 5)
+#define CCX_RPT_SET_QSEL(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X4, 8, 5, value)
+#define CCX_RPT_SET_QSEL_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 8, 5, value)
+#define CCX_RPT_GET_MISSED_RPT_NUM(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X4, 13, 3)
+#define CCX_RPT_SET_MISSED_RPT_NUM(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X4, 13, 3, value)
+#define CCX_RPT_SET_MISSED_RPT_NUM_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 13, 3, value)
+#define CCX_RPT_GET_MACID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X4, 16, 7)
+#define CCX_RPT_SET_MACID(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X4, 16, 7, value)
+#define CCX_RPT_SET_MACID_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 16, 7, value)
+#define CCX_RPT_GET_INITIAL_DATA_RATE(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X4, 24, 7)
+#define CCX_RPT_SET_INITIAL_DATA_RATE(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X4, 24, 7, value)
+#define CCX_RPT_SET_INITIAL_DATA_RATE_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 24, 7, value)
+#define CCX_RPT_GET_INITIAL_SGI(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X4, 31, 1)
+#define CCX_RPT_SET_INITIAL_SGI(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X4, 31, 1, value)
+#define CCX_RPT_SET_INITIAL_SGI_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X4, 31, 1, value)
+#define CCX_RPT_GET_QUEUE_TIME(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 0, 16)
+#define CCX_RPT_SET_QUEUE_TIME(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 0, 16, value)
+#define CCX_RPT_SET_QUEUE_TIME_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 0, 16, value)
+#define CCX_RPT_GET_SW_DEFINE_BYTE0(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 16, 8)
+#define CCX_RPT_SET_SW_DEFINE_BYTE0(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 16, 8, value)
+#define CCX_RPT_SET_SW_DEFINE_BYTE0_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 16, 8, value)
+#define CCX_RPT_GET_RTS_RETRY_COUNT(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 24, 4)
+#define CCX_RPT_SET_RTS_RETRY_COUNT(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 24, 4, value)
+#define CCX_RPT_SET_RTS_RETRY_COUNT_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 24, 4, value)
+#define CCX_RPT_GET_BMC(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 29, 1)
+#define CCX_RPT_SET_BMC(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 29, 1, value)
+#define CCX_RPT_SET_BMC_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 29, 1, value)
+#define CCX_RPT_GET_TX_STATE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X8, 30, 2)
+#define CCX_RPT_SET_TX_STATE(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 30, 2, value)
+#define CCX_RPT_SET_TX_STATE_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 30, 2, value)
+#define CCX_RPT_GET_DATA_RETRY_COUNT(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 0, 6)
+#define CCX_RPT_SET_DATA_RETRY_COUNT(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 0, 6, value)
+#define CCX_RPT_SET_DATA_RETRY_COUNT_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 0, 6, value)
+#define CCX_RPT_GET_FINAL_DATA_RATE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 8, 7)
+#define CCX_RPT_SET_FINAL_DATA_RATE(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 8, 7, value)
+#define CCX_RPT_SET_FINAL_DATA_RATE_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 8, 7, value)
+#define CCX_RPT_GET_FINAL_SGI(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 15, 1)
+#define CCX_RPT_SET_FINAL_SGI(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 15, 1, value)
+#define CCX_RPT_SET_FINAL_SGI_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 15, 1, value)
+#define CCX_RPT_GET_RF_CH_NUM(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 16, 10)
+#define CCX_RPT_SET_RF_CH_NUM(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 16, 10, value)
+#define CCX_RPT_SET_RF_CH_NUM_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 16, 10, value)
+#define CCX_RPT_GET_SC(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 26, 4)
+#define CCX_RPT_SET_SC(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 26, 4, value)
+#define CCX_RPT_SET_SC_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 26, 4, value)
+#define CCX_RPT_GET_BW(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0XC, 30, 2)
+#define CCX_RPT_SET_BW(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0XC, 30, 2, value)
+#define CCX_RPT_SET_BW_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0XC, 30, 2, value)
+#define FW_DBG_MSG_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define FW_DBG_MSG_SET_CMD_ID(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define FW_DBG_MSG_SET_CMD_ID_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define FW_DBG_MSG_GET_C2H_SUB_CMD_ID(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8)
+#define FW_DBG_MSG_SET_C2H_SUB_CMD_ID(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define FW_DBG_MSG_SET_C2H_SUB_CMD_ID_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define FW_DBG_MSG_GET_FULL(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 24, 1)
+#define FW_DBG_MSG_SET_FULL(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 1, value)
+#define FW_DBG_MSG_SET_FULL_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 1, value)
+#define FW_DBG_MSG_GET_OWN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 31, 1)
+#define FW_DBG_MSG_SET_OWN(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 31, 1, value)
+#define FW_DBG_MSG_SET_OWN_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 31, 1, value)
+#define FW_FWCTRL_RPT_GET_EVT_TYPE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define FW_FWCTRL_RPT_SET_EVT_TYPE(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define FW_FWCTRL_RPT_SET_EVT_TYPE_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define FW_FWCTRL_RPT_GET_LENGTH(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define FW_FWCTRL_RPT_SET_LENGTH(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define FW_FWCTRL_RPT_SET_LENGTH_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define FW_FWCTRL_RPT_GET_SEQ_NUM(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8)
+#define FW_FWCTRL_RPT_SET_SEQ_NUM(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define FW_FWCTRL_RPT_SET_SEQ_NUM_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define FW_FWCTRL_RPT_GET_IS_ACK(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 24, 1)
+#define FW_FWCTRL_RPT_SET_IS_ACK(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 1, value)
+#define FW_FWCTRL_RPT_SET_IS_ACK_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 1, value)
+#define FW_FWCTRL_RPT_GET_MORE_CONTENT(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X00, 25, 1)
+#define FW_FWCTRL_RPT_SET_MORE_CONTENT(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 25, 1, value)
+#define FW_FWCTRL_RPT_SET_MORE_CONTENT_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 25, 1, value)
+#define FW_FWCTRL_RPT_GET_CONTENT_IDX(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X00, 26, 6)
+#define FW_FWCTRL_RPT_SET_CONTENT_IDX(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 26, 6, value)
+#define FW_FWCTRL_RPT_SET_CONTENT_IDX_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 26, 6, value)
+#define FW_FWCTRL_RPT_GET_CLASS_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
+#define FW_FWCTRL_RPT_SET_CLASS_ID(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define FW_FWCTRL_RPT_SET_CLASS_ID_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define FW_FWCTRL_RPT_GET_CONTENT(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 16)
+#define FW_FWCTRL_RPT_SET_CONTENT(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 16, value)
+#define FW_FWCTRL_RPT_SET_CONTENT_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 16, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_0(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_0(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_0_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_1(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_1(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_1_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_2(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_2(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_2_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_3(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X04, 24, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_3(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_3_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_4(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X8, 0, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_4(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 0, 8, value)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_4_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 0, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_5(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X8, 8, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_5(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 8, 8, value)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_5_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 8, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_6(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X8, 16, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_6(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 16, 8, value)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_6_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 16, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_7(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X8, 24, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_7(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 24, 8, value)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_7_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 24, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_0(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_0(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_0_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_1(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_1(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_1_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_2(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_2(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_2_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_3(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X04, 24, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_3(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_3_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_4(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X8, 0, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_4(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 0, 8, value)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_4_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 0, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_5(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X8, 8, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_5(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 8, 8, value)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_5_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 8, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_6(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X8, 16, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_6(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 16, 8, value)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_6_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 16, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_7(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X8, 24, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_7(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X8, 24, 8, value)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_7_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X8, 24, 8, value)
#endif
diff --git a/hal/halmac/halmac_fw_offload_c2h_nic.h b/hal/halmac/halmac_fw_offload_c2h_nic.h
index ff73963..b87e341 100644
--- a/hal/halmac/halmac_fw_offload_c2h_nic.h
+++ b/hal/halmac/halmac_fw_offload_c2h_nic.h
@@ -1,93 +1,371 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
#ifndef _HAL_FWOFFLOADC2HFORMAT_H2C_C2H_NIC_H_
#define _HAL_FWOFFLOADC2HFORMAT_H2C_C2H_NIC_H_
-#define C2H_SUB_CMD_ID_C2H_DBG 0X00
-#define C2H_SUB_CMD_ID_BT_COEX_INFO 0X02
-#define C2H_SUB_CMD_ID_SCAN_STATUS_RPT 0X03
-#define C2H_SUB_CMD_ID_H2C_ACK_HDR 0X01
-#define C2H_SUB_CMD_ID_CFG_PARAMETER_ACK 0X01
-#define C2H_SUB_CMD_ID_BT_COEX_ACK 0X01
-#define C2H_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0X01
-#define C2H_SUB_CMD_ID_UPDATE_PACKET_ACK 0X01
-#define C2H_SUB_CMD_ID_UPDATE_DATAPACK_ACK 0X01
-#define C2H_SUB_CMD_ID_RUN_DATAPACK_ACK 0X01
-#define C2H_SUB_CMD_ID_CHANNEL_SWITCH_ACK 0X01
-#define C2H_SUB_CMD_ID_IQK_ACK 0X01
-#define C2H_SUB_CMD_ID_POWER_TRACKING_ACK 0X01
-#define C2H_SUB_CMD_ID_PSD_ACK 0X01
-#define C2H_SUB_CMD_ID_PSD_DATA 0X04
-#define C2H_SUB_CMD_ID_EFUSE_DATA 0X05
-#define H2C_SUB_CMD_ID_CFG_PARAMETER_ACK SUB_CMD_ID_CFG_PARAMETER
+#define C2H_SUB_CMD_ID_C2H_DBG 0X00
+#define C2H_SUB_CMD_ID_BT_COEX_INFO 0X02
+#define C2H_SUB_CMD_ID_SCAN_STATUS_RPT 0X03
+#define C2H_SUB_CMD_ID_H2C_ACK_HDR 0X01
+#define C2H_SUB_CMD_ID_CFG_PARAM_ACK 0X01
+#define C2H_SUB_CMD_ID_BT_COEX_ACK 0X01
+#define C2H_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0X01
+#define C2H_SUB_CMD_ID_UPDATE_PKT_ACK 0X01
+#define C2H_SUB_CMD_ID_UPDATE_DATAPACK_ACK 0X01
+#define C2H_SUB_CMD_ID_RUN_DATAPACK_ACK 0X01
+#define C2H_SUB_CMD_ID_CH_SWITCH_ACK 0X01
+#define C2H_SUB_CMD_ID_IQK_ACK 0X01
+#define C2H_SUB_CMD_ID_PWR_TRK_ACK 0X01
+#define C2H_SUB_CMD_ID_PSD_ACK 0X01
+#define C2H_SUB_CMD_ID_PSD_DATA 0X04
+#define C2H_SUB_CMD_ID_EFUSE_DATA 0X05
+#define C2H_SUB_CMD_ID_IQK_DATA 0X06
+#define C2H_SUB_CMD_ID_C2H_PKT_FTM_DBG 0X07
+#define C2H_SUB_CMD_ID_C2H_PKT_FTM_2_DBG 0X08
+#define C2H_SUB_CMD_ID_C2H_PKT_FTM_3_DBG 0X09
+#define C2H_SUB_CMD_ID_C2H_PKT_FTM_4_DBG 0X0A
+#define C2H_SUB_CMD_ID_FTMACKRPT_HDL_DBG 0X0B
+#define C2H_SUB_CMD_ID_FTMC2H_RPT 0X0C
+#define C2H_SUB_CMD_ID_DRVFTMC2H_RPT 0X0D
+#define C2H_SUB_CMD_ID_C2H_PKT_FTM_5_DBG 0X0E
+#define C2H_SUB_CMD_ID_CCX_RPT 0X0F
+#define C2H_SUB_CMD_ID_C2H_PKT_NAN_RPT 0X10
+#define C2H_SUB_CMD_ID_C2H_PKT_ATM_RPT 0X11
+#define C2H_SUB_CMD_ID_C2H_PKT_FTMSESSION_END 0X1C
+#define C2H_SUB_CMD_ID_C2H_PKT_DETECT_THERMAL 0X1D
+#define C2H_SUB_CMD_ID_FW_DBG_MSG 0XFF
+#define C2H_SUB_CMD_ID_FW_SNDING_ACK 0X01
+#define C2H_SUB_CMD_ID_FW_FWCTRL_RPT 0X1F
+#define C2H_SUB_CMD_ID_H2C_LOOPBACK_ACK 0X20
+#define C2H_SUB_CMD_ID_FWCMD_LOOPBACK_ACK 0X21
+#define H2C_SUB_CMD_ID_CFG_PARAM_ACK SUB_CMD_ID_CFG_PARAM
#define H2C_SUB_CMD_ID_BT_COEX_ACK SUB_CMD_ID_BT_COEX
#define H2C_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK SUB_CMD_ID_DUMP_PHYSICAL_EFUSE
-#define H2C_SUB_CMD_ID_UPDATE_PACKET_ACK SUB_CMD_ID_UPDATE_PACKET
+#define H2C_SUB_CMD_ID_UPDATE_PKT_ACK SUB_CMD_ID_UPDATE_PKT
#define H2C_SUB_CMD_ID_UPDATE_DATAPACK_ACK SUB_CMD_ID_UPDATE_DATAPACK
#define H2C_SUB_CMD_ID_RUN_DATAPACK_ACK SUB_CMD_ID_RUN_DATAPACK
-#define H2C_SUB_CMD_ID_CHANNEL_SWITCH_ACK SUB_CMD_ID_CHANNEL_SWITCH
+#define H2C_SUB_CMD_ID_CH_SWITCH_ACK SUB_CMD_ID_CH_SWITCH
#define H2C_SUB_CMD_ID_IQK_ACK SUB_CMD_ID_IQK
-#define H2C_SUB_CMD_ID_POWER_TRACKING_ACK SUB_CMD_ID_POWER_TRACKING
+#define H2C_SUB_CMD_ID_PWR_TRK_ACK SUB_CMD_ID_PWR_TRK
#define H2C_SUB_CMD_ID_PSD_ACK SUB_CMD_ID_PSD
-#define H2C_CMD_ID_CFG_PARAMETER_ACK 0XFF
-#define H2C_CMD_ID_BT_COEX_ACK 0XFF
-#define H2C_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0XFF
-#define H2C_CMD_ID_UPDATE_PACKET_ACK 0XFF
-#define H2C_CMD_ID_UPDATE_DATAPACK_ACK 0XFF
-#define H2C_CMD_ID_RUN_DATAPACK_ACK 0XFF
-#define H2C_CMD_ID_CHANNEL_SWITCH_ACK 0XFF
-#define H2C_CMD_ID_IQK_ACK 0XFF
-#define H2C_CMD_ID_POWER_TRACKING_ACK 0XFF
-#define H2C_CMD_ID_PSD_ACK 0XFF
-#define C2H_HDR_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8)
-#define C2H_HDR_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value)
-#define C2H_HDR_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8)
-#define C2H_HDR_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value)
-#define C2H_HDR_GET_C2H_SUB_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 8)
-#define C2H_HDR_SET_C2H_SUB_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 8, __Value)
-#define C2H_HDR_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 24, 8)
-#define C2H_HDR_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 24, 8, __Value)
-#define C2H_DBG_GET_DBG_MSG(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 8)
-#define C2H_DBG_SET_DBG_MSG(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 8, __Value)
-#define BT_COEX_INFO_GET_DATA_START(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 8)
-#define BT_COEX_INFO_SET_DATA_START(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 8, __Value)
-#define SCAN_STATUS_RPT_GET_H2C_RETURN_CODE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 8)
-#define SCAN_STATUS_RPT_SET_H2C_RETURN_CODE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 8, __Value)
-#define SCAN_STATUS_RPT_GET_H2C_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 16)
-#define SCAN_STATUS_RPT_SET_H2C_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 16, __Value)
-#define H2C_ACK_HDR_GET_H2C_RETURN_CODE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 8)
-#define H2C_ACK_HDR_SET_H2C_RETURN_CODE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 8, __Value)
-#define H2C_ACK_HDR_GET_H2C_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8)
-#define H2C_ACK_HDR_SET_H2C_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value)
-#define H2C_ACK_HDR_GET_H2C_SUB_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 16)
-#define H2C_ACK_HDR_SET_H2C_SUB_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 16, __Value)
-#define H2C_ACK_HDR_GET_H2C_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 0, 16)
-#define H2C_ACK_HDR_SET_H2C_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 0, 16, __Value)
-#define CFG_PARAMETER_ACK_GET_OFFSET_ACCUMULATION(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0XC, 0, 32)
-#define CFG_PARAMETER_ACK_SET_OFFSET_ACCUMULATION(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0XC, 0, 32, __Value)
-#define CFG_PARAMETER_ACK_GET_VALUE_ACCUMULATION(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X10, 0, 32)
-#define CFG_PARAMETER_ACK_SET_VALUE_ACCUMULATION(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X10, 0, 32, __Value)
-#define BT_COEX_ACK_GET_DATA_START(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0XC, 0, 8)
-#define BT_COEX_ACK_SET_DATA_START(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0XC, 0, 8, __Value)
-#define PSD_DATA_GET_SEGMENT_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 7)
-#define PSD_DATA_SET_SEGMENT_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 7, __Value)
-#define PSD_DATA_GET_END_SEGMENT(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 7, 1)
-#define PSD_DATA_SET_END_SEGMENT(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 7, 1, __Value)
-#define PSD_DATA_GET_SEGMENT_SIZE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8)
-#define PSD_DATA_SET_SEGMENT_SIZE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value)
-#define PSD_DATA_GET_TOTAL_SIZE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 16)
-#define PSD_DATA_SET_TOTAL_SIZE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 16, __Value)
-#define PSD_DATA_GET_H2C_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X8, 0, 16)
-#define PSD_DATA_SET_H2C_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X8, 0, 16, __Value)
-#define PSD_DATA_GET_DATA_START(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X8, 16, 8)
-#define PSD_DATA_SET_DATA_START(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X8, 16, 8, __Value)
-#define EFUSE_DATA_GET_SEGMENT_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 7)
-#define EFUSE_DATA_SET_SEGMENT_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 7, __Value)
-#define EFUSE_DATA_GET_END_SEGMENT(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 7, 1)
-#define EFUSE_DATA_SET_END_SEGMENT(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 7, 1, __Value)
-#define EFUSE_DATA_GET_SEGMENT_SIZE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8)
-#define EFUSE_DATA_SET_SEGMENT_SIZE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value)
-#define EFUSE_DATA_GET_TOTAL_SIZE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 16)
-#define EFUSE_DATA_SET_TOTAL_SIZE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 16, __Value)
-#define EFUSE_DATA_GET_H2C_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X8, 0, 16)
-#define EFUSE_DATA_SET_H2C_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X8, 0, 16, __Value)
-#define EFUSE_DATA_GET_DATA_START(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X8, 16, 8)
-#define EFUSE_DATA_SET_DATA_START(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X8, 16, 8, __Value)
+#define H2C_SUB_CMD_ID_CCX_RPT SUB_CMD_ID_CCX_RPT
+#define H2C_SUB_CMD_ID_FW_DBG_MSG SUB_CMD_ID_FW_DBG_MSG
+#define H2C_SUB_CMD_ID_FW_SNDING_ACK SUB_CMD_ID_FW_SNDING
+#define H2C_SUB_CMD_ID_FW_FWCTRL_RPT SUB_CMD_ID_FW_FWCTRL_RPT
+#define H2C_SUB_CMD_ID_H2C_LOOPBACK_ACK SUB_CMD_ID_H2C_LOOPBACK
+#define H2C_SUB_CMD_ID_FWCMD_LOOPBACK_ACK SUB_CMD_ID_FWCMD_LOOPBACK
+#define H2C_CMD_ID_CFG_PARAM_ACK 0XFF
+#define H2C_CMD_ID_BT_COEX_ACK 0XFF
+#define H2C_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0XFF
+#define H2C_CMD_ID_UPDATE_PKT_ACK 0XFF
+#define H2C_CMD_ID_UPDATE_DATAPACK_ACK 0XFF
+#define H2C_CMD_ID_RUN_DATAPACK_ACK 0XFF
+#define H2C_CMD_ID_CH_SWITCH_ACK 0XFF
+#define H2C_CMD_ID_IQK_ACK 0XFF
+#define H2C_CMD_ID_PWR_TRK_ACK 0XFF
+#define H2C_CMD_ID_PSD_ACK 0XFF
+#define H2C_CMD_ID_CCX_RPT 0XFF
+#define H2C_CMD_ID_FW_DBG_MSG 0XFF
+#define H2C_CMD_ID_FW_SNDING_ACK 0XFF
+#define H2C_CMD_ID_FW_FWCTRL_RPT 0XFF
+#define H2C_CMD_ID_H2C_LOOPBACK_ACK 0XFF
+#define H2C_CMD_ID_FWCMD_LOOPBACK_ACK 0XFF
+#define C2H_HDR_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define C2H_HDR_SET_CMD_ID(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_HDR_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define C2H_HDR_SET_SEQ(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_HDR_GET_C2H_SUB_CMD_ID(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8)
+#define C2H_HDR_SET_C2H_SUB_CMD_ID(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_HDR_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8)
+#define C2H_HDR_SET_LEN(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_DBG_GET_DBG_MSG(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
+#define C2H_DBG_SET_DBG_MSG(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
+#define BT_COEX_INFO_GET_DATA_START(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
+#define BT_COEX_INFO_SET_DATA_START(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
+#define SCAN_STATUS_RPT_GET_H2C_RETURN_CODE(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
+#define SCAN_STATUS_RPT_SET_H2C_RETURN_CODE(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
+#define SCAN_STATUS_RPT_GET_H2C_SEQ(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 16)
+#define SCAN_STATUS_RPT_SET_H2C_SEQ(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 16, value)
+#define H2C_ACK_HDR_GET_H2C_RETURN_CODE(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
+#define H2C_ACK_HDR_SET_H2C_RETURN_CODE(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
+#define H2C_ACK_HDR_GET_H2C_CMD_ID(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
+#define H2C_ACK_HDR_SET_H2C_CMD_ID(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
+#define H2C_ACK_HDR_GET_H2C_SUB_CMD_ID(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 16)
+#define H2C_ACK_HDR_SET_H2C_SUB_CMD_ID(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 16, value)
+#define H2C_ACK_HDR_GET_H2C_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 16)
+#define H2C_ACK_HDR_SET_H2C_SEQ(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 16, value)
+#define CFG_PARAM_ACK_GET_OFFSET_ACCUMULATION(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 0, 32)
+#define CFG_PARAM_ACK_SET_OFFSET_ACCUMULATION(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 0, 32, value)
+#define CFG_PARAM_ACK_GET_VALUE_ACCUMULATION(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X10, 0, 32)
+#define CFG_PARAM_ACK_SET_VALUE_ACCUMULATION(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X10, 0, 32, value)
+#define BT_COEX_ACK_GET_DATA_START(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 0, 8)
+#define BT_COEX_ACK_SET_DATA_START(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 0, 8, value)
+#define PSD_DATA_GET_SEGMENT_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 7)
+#define PSD_DATA_SET_SEGMENT_ID(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 7, value)
+#define PSD_DATA_GET_END_SEGMENT(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 7, 1)
+#define PSD_DATA_SET_END_SEGMENT(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 7, 1, value)
+#define PSD_DATA_GET_SEGMENT_SIZE(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
+#define PSD_DATA_SET_SEGMENT_SIZE(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
+#define PSD_DATA_GET_TOTAL_SIZE(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 16)
+#define PSD_DATA_SET_TOTAL_SIZE(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 16, value)
+#define PSD_DATA_GET_H2C_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 0, 16)
+#define PSD_DATA_SET_H2C_SEQ(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 0, 16, value)
+#define PSD_DATA_GET_DATA_START(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 16, 8)
+#define PSD_DATA_SET_DATA_START(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 16, 8, value)
+#define EFUSE_DATA_GET_SEGMENT_ID(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 7)
+#define EFUSE_DATA_SET_SEGMENT_ID(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 7, value)
+#define EFUSE_DATA_GET_END_SEGMENT(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 7, 1)
+#define EFUSE_DATA_SET_END_SEGMENT(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 7, 1, value)
+#define EFUSE_DATA_GET_SEGMENT_SIZE(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
+#define EFUSE_DATA_SET_SEGMENT_SIZE(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
+#define EFUSE_DATA_GET_TOTAL_SIZE(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 16)
+#define EFUSE_DATA_SET_TOTAL_SIZE(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 16, value)
+#define EFUSE_DATA_GET_H2C_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 0, 16)
+#define EFUSE_DATA_SET_H2C_SEQ(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 0, 16, value)
+#define EFUSE_DATA_GET_DATA_START(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 16, 8)
+#define EFUSE_DATA_SET_DATA_START(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 16, 8, value)
+#define IQK_DATA_GET_SEGMENT_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 7)
+#define IQK_DATA_SET_SEGMENT_ID(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 7, value)
+#define IQK_DATA_GET_END_SEGMENT(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 7, 1)
+#define IQK_DATA_SET_END_SEGMENT(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 7, 1, value)
+#define IQK_DATA_GET_SEGMENT_SIZE(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
+#define IQK_DATA_SET_SEGMENT_SIZE(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
+#define IQK_DATA_GET_TOTAL_SIZE(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 16)
+#define IQK_DATA_SET_TOTAL_SIZE(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 16, value)
+#define IQK_DATA_GET_H2C_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 0, 16)
+#define IQK_DATA_SET_H2C_SEQ(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 0, 16, value)
+#define IQK_DATA_GET_DATA_START(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 16, 8)
+#define IQK_DATA_SET_DATA_START(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 16, 8, value)
+#define CCX_RPT_GET_POLLUTED(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 0, 1)
+#define CCX_RPT_SET_POLLUTED(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 0, 1, value)
+#define CCX_RPT_GET_RPT_SEL(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 5, 3)
+#define CCX_RPT_SET_RPT_SEL(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 5, 3, value)
+#define CCX_RPT_GET_QSEL(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 8, 5)
+#define CCX_RPT_SET_QSEL(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 8, 5, value)
+#define CCX_RPT_GET_MISSED_RPT_NUM(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 13, 3)
+#define CCX_RPT_SET_MISSED_RPT_NUM(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 13, 3, value)
+#define CCX_RPT_GET_MACID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 16, 7)
+#define CCX_RPT_SET_MACID(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 16, 7, value)
+#define CCX_RPT_GET_INITIAL_DATA_RATE(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 24, 7)
+#define CCX_RPT_SET_INITIAL_DATA_RATE(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 24, 7, value)
+#define CCX_RPT_GET_INITIAL_SGI(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X4, 31, 1)
+#define CCX_RPT_SET_INITIAL_SGI(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X4, 31, 1, value)
+#define CCX_RPT_GET_QUEUE_TIME(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 0, 16)
+#define CCX_RPT_SET_QUEUE_TIME(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 0, 16, value)
+#define CCX_RPT_GET_SW_DEFINE_BYTE0(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 16, 8)
+#define CCX_RPT_SET_SW_DEFINE_BYTE0(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 16, 8, value)
+#define CCX_RPT_GET_RTS_RETRY_COUNT(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 24, 4)
+#define CCX_RPT_SET_RTS_RETRY_COUNT(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 24, 4, value)
+#define CCX_RPT_GET_BMC(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 29, 1)
+#define CCX_RPT_SET_BMC(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 29, 1, value)
+#define CCX_RPT_GET_TX_STATE(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 30, 2)
+#define CCX_RPT_SET_TX_STATE(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 30, 2, value)
+#define CCX_RPT_GET_DATA_RETRY_COUNT(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 0, 6)
+#define CCX_RPT_SET_DATA_RETRY_COUNT(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 0, 6, value)
+#define CCX_RPT_GET_FINAL_DATA_RATE(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 8, 7)
+#define CCX_RPT_SET_FINAL_DATA_RATE(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 8, 7, value)
+#define CCX_RPT_GET_FINAL_SGI(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 15, 1)
+#define CCX_RPT_SET_FINAL_SGI(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 15, 1, value)
+#define CCX_RPT_GET_RF_CH_NUM(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 16, 10)
+#define CCX_RPT_SET_RF_CH_NUM(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 16, 10, value)
+#define CCX_RPT_GET_SC(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 26, 4)
+#define CCX_RPT_SET_SC(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 26, 4, value)
+#define CCX_RPT_GET_BW(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0XC, 30, 2)
+#define CCX_RPT_SET_BW(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0XC, 30, 2, value)
+#define FW_DBG_MSG_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define FW_DBG_MSG_SET_CMD_ID(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define FW_DBG_MSG_GET_C2H_SUB_CMD_ID(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8)
+#define FW_DBG_MSG_SET_C2H_SUB_CMD_ID(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value)
+#define FW_DBG_MSG_GET_FULL(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 1)
+#define FW_DBG_MSG_SET_FULL(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 1, value)
+#define FW_DBG_MSG_GET_OWN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 31, 1)
+#define FW_DBG_MSG_SET_OWN(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 31, 1, value)
+#define FW_FWCTRL_RPT_GET_EVT_TYPE(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define FW_FWCTRL_RPT_SET_EVT_TYPE(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define FW_FWCTRL_RPT_GET_LENGTH(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define FW_FWCTRL_RPT_SET_LENGTH(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define FW_FWCTRL_RPT_GET_SEQ_NUM(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8)
+#define FW_FWCTRL_RPT_SET_SEQ_NUM(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value)
+#define FW_FWCTRL_RPT_GET_IS_ACK(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 1)
+#define FW_FWCTRL_RPT_SET_IS_ACK(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 1, value)
+#define FW_FWCTRL_RPT_GET_MORE_CONTENT(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 25, 1)
+#define FW_FWCTRL_RPT_SET_MORE_CONTENT(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 25, 1, value)
+#define FW_FWCTRL_RPT_GET_CONTENT_IDX(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 26, 6)
+#define FW_FWCTRL_RPT_SET_CONTENT_IDX(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 26, 6, value)
+#define FW_FWCTRL_RPT_GET_CLASS_ID(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
+#define FW_FWCTRL_RPT_SET_CLASS_ID(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
+#define FW_FWCTRL_RPT_GET_CONTENT(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 16)
+#define FW_FWCTRL_RPT_SET_CONTENT(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 16, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_0(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_0(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_1(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_1(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_2(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_2(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_3(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_3(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_4(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 0, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_4(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 0, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_5(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 8, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_5(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 8, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_6(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 16, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_6(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 16, 8, value)
+#define H2C_LOOPBACK_ACK_GET_H2C_BYTE_7(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 24, 8)
+#define H2C_LOOPBACK_ACK_SET_H2C_BYTE_7(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 24, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_0(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_0(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_1(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_1(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_2(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_2(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_3(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_3(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_4(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 0, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_4(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 0, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_5(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 8, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_5(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 8, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_6(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 16, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_6(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 16, 8, value)
+#define FWCMD_LOOPBACK_ACK_GET_H2C_BYTE_7(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X8, 24, 8)
+#define FWCMD_LOOPBACK_ACK_SET_H2C_BYTE_7(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X8, 24, 8, value)
#endif
diff --git a/hal/halmac/halmac_fw_offload_h2c_ap.h b/hal/halmac/halmac_fw_offload_h2c_ap.h
index 8e5e6a1..9ef85ce 100644
--- a/hal/halmac/halmac_fw_offload_h2c_ap.h
+++ b/hal/halmac/halmac_fw_offload_h2c_ap.h
@@ -1,273 +1,989 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
#ifndef _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_AP_H_
#define _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_AP_H_
-#define CMD_ID_FW_OFFLOAD_H2C 0XFF
-#define CMD_ID_CHANNEL_SWITCH 0XFF
-#define CMD_ID_DUMP_PHYSICAL_EFUSE 0XFF
-#define CMD_ID_UPDATE_BEACON_PARSING_INFO 0XFF
-#define CMD_ID_CFG_PARAMETER 0XFF
-#define CMD_ID_UPDATE_DATAPACK 0XFF
-#define CMD_ID_RUN_DATAPACK 0XFF
-#define CMD_ID_DOWNLOAD_FLASH 0XFF
-#define CMD_ID_UPDATE_PACKET 0XFF
-#define CMD_ID_GENERAL_INFO 0XFF
-#define CMD_ID_IQK 0XFF
-#define CMD_ID_POWER_TRACKING 0XFF
-#define CMD_ID_PSD 0XFF
-#define CMD_ID_BT_COEX 0XFF
-#define CATEGORY_H2C_CMD_HEADER 0X00
-#define CATEGORY_FW_OFFLOAD_H2C 0X01
-#define CATEGORY_CHANNEL_SWITCH 0X01
-#define CATEGORY_DUMP_PHYSICAL_EFUSE 0X01
-#define CATEGORY_UPDATE_BEACON_PARSING_INFO 0X01
-#define CATEGORY_CFG_PARAMETER 0X01
-#define CATEGORY_UPDATE_DATAPACK 0X01
-#define CATEGORY_RUN_DATAPACK 0X01
-#define CATEGORY_DOWNLOAD_FLASH 0X01
-#define CATEGORY_UPDATE_PACKET 0X01
-#define CATEGORY_GENERAL_INFO 0X01
-#define CATEGORY_IQK 0X01
-#define CATEGORY_POWER_TRACKING 0X01
-#define CATEGORY_PSD 0X01
-#define CATEGORY_BT_COEX 0X01
-#define SUB_CMD_ID_CHANNEL_SWITCH 0X02
-#define SUB_CMD_ID_DUMP_PHYSICAL_EFUSE 0X03
-#define SUB_CMD_ID_UPDATE_BEACON_PARSING_INFO 0X05
-#define SUB_CMD_ID_CFG_PARAMETER 0X08
-#define SUB_CMD_ID_UPDATE_DATAPACK 0X09
-#define SUB_CMD_ID_RUN_DATAPACK 0X0A
-#define SUB_CMD_ID_DOWNLOAD_FLASH 0X0B
-#define SUB_CMD_ID_UPDATE_PACKET 0X0C
-#define SUB_CMD_ID_GENERAL_INFO 0X0D
-#define SUB_CMD_ID_IQK 0X0E
-#define SUB_CMD_ID_POWER_TRACKING 0X0F
-#define SUB_CMD_ID_PSD 0X10
-#define SUB_CMD_ID_BT_COEX 0X60
-#define H2C_CMD_HEADER_GET_CATEGORY(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 7)
-#define H2C_CMD_HEADER_SET_CATEGORY(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 7, __Value)
-#define H2C_CMD_HEADER_SET_CATEGORY_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 7, __Value)
-#define H2C_CMD_HEADER_GET_ACK(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 7, 1)
-#define H2C_CMD_HEADER_SET_ACK(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 7, 1, __Value)
-#define H2C_CMD_HEADER_SET_ACK_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 7, 1, __Value)
-#define H2C_CMD_HEADER_GET_TOTAL_LEN(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 16)
-#define H2C_CMD_HEADER_SET_TOTAL_LEN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 16, __Value)
-#define H2C_CMD_HEADER_SET_TOTAL_LEN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 16, __Value)
-#define H2C_CMD_HEADER_GET_SEQ_NUM(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 16)
-#define H2C_CMD_HEADER_SET_SEQ_NUM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 16, __Value)
-#define H2C_CMD_HEADER_SET_SEQ_NUM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 16, __Value)
-#define FW_OFFLOAD_H2C_GET_CATEGORY(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 7)
-#define FW_OFFLOAD_H2C_SET_CATEGORY(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 7, __Value)
-#define FW_OFFLOAD_H2C_SET_CATEGORY_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 7, __Value)
-#define FW_OFFLOAD_H2C_GET_ACK(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 7, 1)
-#define FW_OFFLOAD_H2C_SET_ACK(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 7, 1, __Value)
-#define FW_OFFLOAD_H2C_SET_ACK_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 7, 1, __Value)
-#define FW_OFFLOAD_H2C_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8)
-#define FW_OFFLOAD_H2C_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value)
-#define FW_OFFLOAD_H2C_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value)
-#define FW_OFFLOAD_H2C_GET_SUB_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 16)
-#define FW_OFFLOAD_H2C_SET_SUB_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 16, __Value)
-#define FW_OFFLOAD_H2C_SET_SUB_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 16, __Value)
-#define FW_OFFLOAD_H2C_GET_TOTAL_LEN(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 16)
-#define FW_OFFLOAD_H2C_SET_TOTAL_LEN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 16, __Value)
-#define FW_OFFLOAD_H2C_SET_TOTAL_LEN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 16, __Value)
-#define FW_OFFLOAD_H2C_GET_SEQ_NUM(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 16)
-#define FW_OFFLOAD_H2C_SET_SEQ_NUM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 16, __Value)
-#define FW_OFFLOAD_H2C_SET_SEQ_NUM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 16, __Value)
-#define CHANNEL_SWITCH_GET_SWITCH_START(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 1)
-#define CHANNEL_SWITCH_SET_SWITCH_START(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 1, __Value)
-#define CHANNEL_SWITCH_SET_SWITCH_START_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 1, __Value)
-#define CHANNEL_SWITCH_GET_DEST_CH_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 1, 1)
-#define CHANNEL_SWITCH_SET_DEST_CH_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 1, 1, __Value)
-#define CHANNEL_SWITCH_SET_DEST_CH_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 1, 1, __Value)
-#define CHANNEL_SWITCH_GET_ABSOLUTE_TIME(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 2, 1)
-#define CHANNEL_SWITCH_SET_ABSOLUTE_TIME(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 2, 1, __Value)
-#define CHANNEL_SWITCH_SET_ABSOLUTE_TIME_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 2, 1, __Value)
-#define CHANNEL_SWITCH_GET_PERIODIC_OPTION(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 3, 2)
-#define CHANNEL_SWITCH_SET_PERIODIC_OPTION(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 3, 2, __Value)
-#define CHANNEL_SWITCH_SET_PERIODIC_OPTION_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 3, 2, __Value)
-#define CHANNEL_SWITCH_GET_CHANNEL_INFO_LOC(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 8, 8)
-#define CHANNEL_SWITCH_SET_CHANNEL_INFO_LOC(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 8, 8, __Value)
-#define CHANNEL_SWITCH_SET_CHANNEL_INFO_LOC_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 8, 8, __Value)
-#define CHANNEL_SWITCH_GET_CHANNEL_NUM(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 16, 8)
-#define CHANNEL_SWITCH_SET_CHANNEL_NUM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 16, 8, __Value)
-#define CHANNEL_SWITCH_SET_CHANNEL_NUM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 16, 8, __Value)
-#define CHANNEL_SWITCH_GET_PRI_CH_IDX(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 24, 4)
-#define CHANNEL_SWITCH_SET_PRI_CH_IDX(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 24, 4, __Value)
-#define CHANNEL_SWITCH_SET_PRI_CH_IDX_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 24, 4, __Value)
-#define CHANNEL_SWITCH_GET_DEST_BW(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 28, 4)
-#define CHANNEL_SWITCH_SET_DEST_BW(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 28, 4, __Value)
-#define CHANNEL_SWITCH_SET_DEST_BW_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 28, 4, __Value)
-#define CHANNEL_SWITCH_GET_DEST_CH(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 0, 8)
-#define CHANNEL_SWITCH_SET_DEST_CH(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 0, 8, __Value)
-#define CHANNEL_SWITCH_SET_DEST_CH_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 0, 8, __Value)
-#define CHANNEL_SWITCH_GET_NORMAL_PERIOD(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 8, 8)
-#define CHANNEL_SWITCH_SET_NORMAL_PERIOD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 8, 8, __Value)
-#define CHANNEL_SWITCH_SET_NORMAL_PERIOD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 8, 8, __Value)
-#define CHANNEL_SWITCH_GET_SLOW_PERIOD(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 16, 8)
-#define CHANNEL_SWITCH_SET_SLOW_PERIOD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 16, 8, __Value)
-#define CHANNEL_SWITCH_SET_SLOW_PERIOD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 16, 8, __Value)
-#define CHANNEL_SWITCH_GET_NORMAL_CYCLE(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 24, 8)
-#define CHANNEL_SWITCH_SET_NORMAL_CYCLE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 24, 8, __Value)
-#define CHANNEL_SWITCH_SET_NORMAL_CYCLE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 24, 8, __Value)
-#define CHANNEL_SWITCH_GET_TSF_HIGH(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 0, 32)
-#define CHANNEL_SWITCH_SET_TSF_HIGH(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 0, 32, __Value)
-#define CHANNEL_SWITCH_SET_TSF_HIGH_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 0, 32, __Value)
-#define CHANNEL_SWITCH_GET_TSF_LOW(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 0, 32)
-#define CHANNEL_SWITCH_SET_TSF_LOW(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 0, 32, __Value)
-#define CHANNEL_SWITCH_SET_TSF_LOW_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 0, 32, __Value)
-#define CHANNEL_SWITCH_GET_CHANNEL_INFO_SIZE(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 0, 16)
-#define CHANNEL_SWITCH_SET_CHANNEL_INFO_SIZE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 0, 16, __Value)
-#define CHANNEL_SWITCH_SET_CHANNEL_INFO_SIZE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 0, 16, __Value)
-#define UPDATE_BEACON_PARSING_INFO_GET_FUNC_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 1)
-#define UPDATE_BEACON_PARSING_INFO_SET_FUNC_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 1, __Value)
-#define UPDATE_BEACON_PARSING_INFO_SET_FUNC_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 1, __Value)
-#define UPDATE_BEACON_PARSING_INFO_GET_SIZE_TH(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 8, 4)
-#define UPDATE_BEACON_PARSING_INFO_SET_SIZE_TH(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 8, 4, __Value)
-#define UPDATE_BEACON_PARSING_INFO_SET_SIZE_TH_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 8, 4, __Value)
-#define UPDATE_BEACON_PARSING_INFO_GET_TIMEOUT(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 12, 4)
-#define UPDATE_BEACON_PARSING_INFO_SET_TIMEOUT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 12, 4, __Value)
-#define UPDATE_BEACON_PARSING_INFO_SET_TIMEOUT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 12, 4, __Value)
-#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_0(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 0, 32)
-#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_0(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 0, 32, __Value)
-#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_0_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 0, 32, __Value)
-#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_1(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 0, 32)
-#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 0, 32, __Value)
-#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 0, 32, __Value)
-#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_2(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 0, 32)
-#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 0, 32, __Value)
-#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 0, 32, __Value)
-#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_3(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 0, 32)
-#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_3(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 0, 32, __Value)
-#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_3_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 0, 32, __Value)
-#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_4(__pH2C) GET_H2C_FIELD(__pH2C + 0X1C, 0, 32)
-#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_4(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X1C, 0, 32, __Value)
-#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_4_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X1C, 0, 32, __Value)
-#define CFG_PARAMETER_GET_NUM(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 16)
-#define CFG_PARAMETER_SET_NUM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 16, __Value)
-#define CFG_PARAMETER_SET_NUM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 16, __Value)
-#define CFG_PARAMETER_GET_INIT_CASE(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 16, 1)
-#define CFG_PARAMETER_SET_INIT_CASE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 16, 1, __Value)
-#define CFG_PARAMETER_SET_INIT_CASE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 16, 1, __Value)
-#define CFG_PARAMETER_GET_PHY_PARAMETER_LOC(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 24, 8)
-#define CFG_PARAMETER_SET_PHY_PARAMETER_LOC(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 24, 8, __Value)
-#define CFG_PARAMETER_SET_PHY_PARAMETER_LOC_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 24, 8, __Value)
-#define UPDATE_DATAPACK_GET_SIZE(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 16)
-#define UPDATE_DATAPACK_SET_SIZE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 16, __Value)
-#define UPDATE_DATAPACK_SET_SIZE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 16, __Value)
-#define UPDATE_DATAPACK_GET_DATAPACK_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 16, 8)
-#define UPDATE_DATAPACK_SET_DATAPACK_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 16, 8, __Value)
-#define UPDATE_DATAPACK_SET_DATAPACK_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 16, 8, __Value)
-#define UPDATE_DATAPACK_GET_DATAPACK_LOC(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 24, 8)
-#define UPDATE_DATAPACK_SET_DATAPACK_LOC(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 24, 8, __Value)
-#define UPDATE_DATAPACK_SET_DATAPACK_LOC_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 24, 8, __Value)
-#define UPDATE_DATAPACK_GET_DATAPACK_SEGMENT(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 0, 8)
-#define UPDATE_DATAPACK_SET_DATAPACK_SEGMENT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 0, 8, __Value)
-#define UPDATE_DATAPACK_SET_DATAPACK_SEGMENT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 0, 8, __Value)
-#define UPDATE_DATAPACK_GET_END_SEGMENT(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 8, 1)
-#define UPDATE_DATAPACK_SET_END_SEGMENT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 8, 1, __Value)
-#define UPDATE_DATAPACK_SET_END_SEGMENT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 8, 1, __Value)
-#define RUN_DATAPACK_GET_DATAPACK_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 8)
-#define RUN_DATAPACK_SET_DATAPACK_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 8, __Value)
-#define RUN_DATAPACK_SET_DATAPACK_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 8, __Value)
-#define DOWNLOAD_FLASH_GET_SPI_CMD(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 8)
-#define DOWNLOAD_FLASH_SET_SPI_CMD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 8, __Value)
-#define DOWNLOAD_FLASH_SET_SPI_CMD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 8, __Value)
-#define DOWNLOAD_FLASH_GET_LOCATION(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 8, 16)
-#define DOWNLOAD_FLASH_SET_LOCATION(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 8, 16, __Value)
-#define DOWNLOAD_FLASH_SET_LOCATION_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 8, 16, __Value)
-#define DOWNLOAD_FLASH_GET_START_ADDR(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 0, 32)
-#define DOWNLOAD_FLASH_SET_START_ADDR(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 0, 32, __Value)
-#define DOWNLOAD_FLASH_SET_START_ADDR_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 0, 32, __Value)
-#define DOWNLOAD_FLASH_GET_SIZE(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 0, 16)
-#define DOWNLOAD_FLASH_SET_SIZE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 0, 16, __Value)
-#define DOWNLOAD_FLASH_SET_SIZE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 0, 16, __Value)
-#define DOWNLOAD_FLASH_GET_SEGMENT_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 16, 7)
-#define DOWNLOAD_FLASH_SET_SEGMENT_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 16, 7, __Value)
-#define DOWNLOAD_FLASH_SET_SEGMENT_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 16, 7, __Value)
-#define DOWNLOAD_FLASH_GET_END_SEGMENT(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 23, 1)
-#define DOWNLOAD_FLASH_SET_END_SEGMENT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 23, 1, __Value)
-#define DOWNLOAD_FLASH_SET_END_SEGMENT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 23, 1, __Value)
-#define UPDATE_PACKET_GET_SIZE(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 16)
-#define UPDATE_PACKET_SET_SIZE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 16, __Value)
-#define UPDATE_PACKET_SET_SIZE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 16, __Value)
-#define UPDATE_PACKET_GET_PACKET_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 16, 8)
-#define UPDATE_PACKET_SET_PACKET_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 16, 8, __Value)
-#define UPDATE_PACKET_SET_PACKET_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 16, 8, __Value)
-#define UPDATE_PACKET_GET_PACKET_LOC(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 24, 8)
-#define UPDATE_PACKET_SET_PACKET_LOC(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 24, 8, __Value)
-#define UPDATE_PACKET_SET_PACKET_LOC_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 24, 8, __Value)
-#define GENERAL_INFO_GET_REF_TYPE(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 8)
-#define GENERAL_INFO_SET_REF_TYPE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 8, __Value)
-#define GENERAL_INFO_SET_REF_TYPE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 8, __Value)
-#define GENERAL_INFO_GET_RF_TYPE(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 8, 9)
-#define GENERAL_INFO_SET_RF_TYPE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 8, 9, __Value)
-#define GENERAL_INFO_SET_RF_TYPE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 8, 9, __Value)
-#define GENERAL_INFO_GET_FW_TX_BOUNDARY(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 16, 8)
-#define GENERAL_INFO_SET_FW_TX_BOUNDARY(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 16, 8, __Value)
-#define GENERAL_INFO_SET_FW_TX_BOUNDARY_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 16, 8, __Value)
-#define IQK_GET_CLEAR(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 1)
-#define IQK_SET_CLEAR(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 1, __Value)
-#define IQK_SET_CLEAR_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 1, __Value)
-#define POWER_TRACKING_GET_ENABLE_A(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 1)
-#define POWER_TRACKING_SET_ENABLE_A(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 1, __Value)
-#define POWER_TRACKING_SET_ENABLE_A_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 1, __Value)
-#define POWER_TRACKING_GET_ENABLE_B(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 1, 1)
-#define POWER_TRACKING_SET_ENABLE_B(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 1, 1, __Value)
-#define POWER_TRACKING_SET_ENABLE_B_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 1, 1, __Value)
-#define POWER_TRACKING_GET_ENABLE_C(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 2, 1)
-#define POWER_TRACKING_SET_ENABLE_C(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 2, 1, __Value)
-#define POWER_TRACKING_SET_ENABLE_C_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 2, 1, __Value)
-#define POWER_TRACKING_GET_ENABLE_D(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 3, 1)
-#define POWER_TRACKING_SET_ENABLE_D(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 3, 1, __Value)
-#define POWER_TRACKING_SET_ENABLE_D_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 3, 1, __Value)
-#define POWER_TRACKING_GET_TYPE(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 4, 3)
-#define POWER_TRACKING_SET_TYPE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 4, 3, __Value)
-#define POWER_TRACKING_SET_TYPE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 4, 3, __Value)
-#define POWER_TRACKING_GET_BBSWING_INDEX(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 8, 8)
-#define POWER_TRACKING_SET_BBSWING_INDEX(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 8, 8, __Value)
-#define POWER_TRACKING_SET_BBSWING_INDEX_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 8, 8, __Value)
-#define POWER_TRACKING_GET_TX_PWR_INDEX_A(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 0, 8)
-#define POWER_TRACKING_SET_TX_PWR_INDEX_A(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 0, 8, __Value)
-#define POWER_TRACKING_SET_TX_PWR_INDEX_A_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 0, 8, __Value)
-#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_A(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 8, 8)
-#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_A(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 8, 8, __Value)
-#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_A_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 8, 8, __Value)
-#define POWER_TRACKING_GET_TSSI_VALUE_A(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 16, 8)
-#define POWER_TRACKING_SET_TSSI_VALUE_A(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 16, 8, __Value)
-#define POWER_TRACKING_SET_TSSI_VALUE_A_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 16, 8, __Value)
-#define POWER_TRACKING_GET_TX_PWR_INDEX_B(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 0, 8)
-#define POWER_TRACKING_SET_TX_PWR_INDEX_B(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 0, 8, __Value)
-#define POWER_TRACKING_SET_TX_PWR_INDEX_B_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 0, 8, __Value)
-#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_B(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 8, 8)
-#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_B(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 8, 8, __Value)
-#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_B_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 8, 8, __Value)
-#define POWER_TRACKING_GET_TSSI_VALUE_B(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 16, 8)
-#define POWER_TRACKING_SET_TSSI_VALUE_B(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 16, 8, __Value)
-#define POWER_TRACKING_SET_TSSI_VALUE_B_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 16, 8, __Value)
-#define POWER_TRACKING_GET_TX_PWR_INDEX_C(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 0, 8)
-#define POWER_TRACKING_SET_TX_PWR_INDEX_C(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 0, 8, __Value)
-#define POWER_TRACKING_SET_TX_PWR_INDEX_C_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 0, 8, __Value)
-#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_C(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 8, 8)
-#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_C(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 8, 8, __Value)
-#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_C_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 8, 8, __Value)
-#define POWER_TRACKING_GET_TSSI_VALUE_C(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 16, 8)
-#define POWER_TRACKING_SET_TSSI_VALUE_C(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 16, 8, __Value)
-#define POWER_TRACKING_SET_TSSI_VALUE_C_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 16, 8, __Value)
-#define POWER_TRACKING_GET_TX_PWR_INDEX_D(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 0, 8)
-#define POWER_TRACKING_SET_TX_PWR_INDEX_D(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 0, 8, __Value)
-#define POWER_TRACKING_SET_TX_PWR_INDEX_D_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 0, 8, __Value)
-#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_D(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 8, 8)
-#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_D(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 8, 8, __Value)
-#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_D_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 8, 8, __Value)
-#define POWER_TRACKING_GET_TSSI_VALUE_D(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 16, 8)
-#define POWER_TRACKING_SET_TSSI_VALUE_D(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 16, 8, __Value)
-#define POWER_TRACKING_SET_TSSI_VALUE_D_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 16, 8, __Value)
-#define PSD_GET_START_PSD(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 16)
-#define PSD_SET_START_PSD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 16, __Value)
-#define PSD_SET_START_PSD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 16, __Value)
-#define PSD_GET_END_PSD(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 16, 16)
-#define PSD_SET_END_PSD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 16, 16, __Value)
-#define PSD_SET_END_PSD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 16, 16, __Value)
-#define BT_COEX_GET_DATA_START(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 8)
-#define BT_COEX_SET_DATA_START(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 8, __Value)
-#define BT_COEX_SET_DATA_START_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 8, __Value)
+#define CMD_ID_FW_OFFLOAD_H2C 0XFF
+#define CMD_ID_CH_SWITCH 0XFF
+#define CMD_ID_DUMP_PHYSICAL_EFUSE 0XFF
+#define CMD_ID_UPDATE_BEACON_PARSING_INFO 0XFF
+#define CMD_ID_CFG_PARAM 0XFF
+#define CMD_ID_UPDATE_DATAPACK 0XFF
+#define CMD_ID_RUN_DATAPACK 0XFF
+#define CMD_ID_DOWNLOAD_FLASH 0XFF
+#define CMD_ID_UPDATE_PKT 0XFF
+#define CMD_ID_GENERAL_INFO 0XFF
+#define CMD_ID_IQK 0XFF
+#define CMD_ID_PWR_TRK 0XFF
+#define CMD_ID_PSD 0XFF
+#define CMD_ID_P2PPS 0XFF
+#define CMD_ID_BT_COEX 0XFF
+#define CMD_ID_NAN_CTRL 0XFF
+#define CMD_ID_NAN_CHANNEL_PLAN_0 0XFF
+#define CMD_ID_NAN_CHANNEL_PLAN_1 0XFF
+#define CMD_ID_FW_ACCESS_TEST 0XFF
+#define CMD_ID_PHYDM_INFO 0XFF
+#define CMD_ID_FW_SNDING 0XFF
+#define CMD_ID_H2C_LOOPBACK 0XFF
+#define CMD_ID_FWCMD_LOOPBACK 0XFF
+#define CMD_ID_FW_FWCTRL 0XFF
+#define CATEGORY_H2C_CMD_HEADER 0X00
+#define CATEGORY_FW_OFFLOAD_H2C 0X01
+#define CATEGORY_CH_SWITCH 0X01
+#define CATEGORY_DUMP_PHYSICAL_EFUSE 0X01
+#define CATEGORY_UPDATE_BEACON_PARSING_INFO 0X01
+#define CATEGORY_CFG_PARAM 0X01
+#define CATEGORY_UPDATE_DATAPACK 0X01
+#define CATEGORY_RUN_DATAPACK 0X01
+#define CATEGORY_DOWNLOAD_FLASH 0X01
+#define CATEGORY_UPDATE_PKT 0X01
+#define CATEGORY_GENERAL_INFO 0X01
+#define CATEGORY_IQK 0X01
+#define CATEGORY_PWR_TRK 0X01
+#define CATEGORY_PSD 0X01
+#define CATEGORY_P2PPS 0X01
+#define CATEGORY_BT_COEX 0X01
+#define CATEGORY_NAN_CTRL 0X01
+#define CATEGORY_NAN_CHANNEL_PLAN_0 0X01
+#define CATEGORY_NAN_CHANNEL_PLAN_1 0X01
+#define CATEGORY_FW_ACCESS_TEST 0X01
+#define CATEGORY_PHYDM_INFO 0X01
+#define CATEGORY_FW_SNDING 0X01
+#define CATEGORY_H2C_LOOPBACK 0X01
+#define CATEGORY_FWCMD_LOOPBACK 0X01
+#define CATEGORY_FW_FWCTRL 0X01
+#define SUB_CMD_ID_CH_SWITCH 0X02
+#define SUB_CMD_ID_DUMP_PHYSICAL_EFUSE 0X03
+#define SUB_CMD_ID_UPDATE_BEACON_PARSING_INFO 0X05
+#define SUB_CMD_ID_CFG_PARAM 0X08
+#define SUB_CMD_ID_UPDATE_DATAPACK 0X09
+#define SUB_CMD_ID_RUN_DATAPACK 0X0A
+#define SUB_CMD_ID_DOWNLOAD_FLASH 0X0B
+#define SUB_CMD_ID_UPDATE_PKT 0X0C
+#define SUB_CMD_ID_GENERAL_INFO 0X0D
+#define SUB_CMD_ID_IQK 0X0E
+#define SUB_CMD_ID_PWR_TRK 0X0F
+#define SUB_CMD_ID_PSD 0X10
+#define SUB_CMD_ID_P2PPS 0X24
+#define SUB_CMD_ID_BT_COEX 0X60
+#define SUB_CMD_ID_NAN_CTRL 0XB2
+#define SUB_CMD_ID_NAN_CHANNEL_PLAN_0 0XB4
+#define SUB_CMD_ID_NAN_CHANNEL_PLAN_1 0XB5
+#define SUB_CMD_ID_FW_ACCESS_TEST 0X00
+#define SUB_CMD_ID_PHYDM_INFO 0X11
+#define SUB_CMD_ID_FW_SNDING 0X12
+#define SUB_CMD_ID_H2C_LOOPBACK 0X14
+#define SUB_CMD_ID_FWCMD_LOOPBACK 0X15
+#define SUB_CMD_ID_FW_FWCTRL 0X13
+#define H2C_CMD_HEADER_GET_CATEGORY(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 7)
+#define H2C_CMD_HEADER_SET_CATEGORY(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 7, value)
+#define H2C_CMD_HEADER_SET_CATEGORY_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 7, value)
+#define H2C_CMD_HEADER_GET_ACK(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 7, 1)
+#define H2C_CMD_HEADER_SET_ACK(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 7, 1, value)
+#define H2C_CMD_HEADER_SET_ACK_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 7, 1, value)
+#define H2C_CMD_HEADER_GET_TOTAL_LEN(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 0, 16)
+#define H2C_CMD_HEADER_SET_TOTAL_LEN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 16, value)
+#define H2C_CMD_HEADER_SET_TOTAL_LEN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 16, value)
+#define H2C_CMD_HEADER_GET_SEQ_NUM(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 16, 16)
+#define H2C_CMD_HEADER_SET_SEQ_NUM(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 16, value)
+#define H2C_CMD_HEADER_SET_SEQ_NUM_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 16, value)
+#define FW_OFFLOAD_H2C_GET_CATEGORY(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 7)
+#define FW_OFFLOAD_H2C_SET_CATEGORY(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 7, value)
+#define FW_OFFLOAD_H2C_SET_CATEGORY_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 7, value)
+#define FW_OFFLOAD_H2C_GET_ACK(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 7, 1)
+#define FW_OFFLOAD_H2C_SET_ACK(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 7, 1, value)
+#define FW_OFFLOAD_H2C_SET_ACK_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 7, 1, value)
+#define FW_OFFLOAD_H2C_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define FW_OFFLOAD_H2C_SET_CMD_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define FW_OFFLOAD_H2C_SET_CMD_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define FW_OFFLOAD_H2C_GET_SUB_CMD_ID(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 16, 16)
+#define FW_OFFLOAD_H2C_SET_SUB_CMD_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 16, value)
+#define FW_OFFLOAD_H2C_SET_SUB_CMD_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 16, value)
+#define FW_OFFLOAD_H2C_GET_TOTAL_LEN(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 0, 16)
+#define FW_OFFLOAD_H2C_SET_TOTAL_LEN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 16, value)
+#define FW_OFFLOAD_H2C_SET_TOTAL_LEN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 16, value)
+#define FW_OFFLOAD_H2C_GET_SEQ_NUM(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 16, 16)
+#define FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 16, value)
+#define FW_OFFLOAD_H2C_SET_SEQ_NUM_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 16, value)
+#define CH_SWITCH_GET_START(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)
+#define CH_SWITCH_SET_START(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define CH_SWITCH_SET_START_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define CH_SWITCH_GET_DEST_CH_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1)
+#define CH_SWITCH_SET_DEST_CH_EN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value)
+#define CH_SWITCH_SET_DEST_CH_EN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value)
+#define CH_SWITCH_GET_ABSOLUTE_TIME(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1)
+#define CH_SWITCH_SET_ABSOLUTE_TIME(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value)
+#define CH_SWITCH_SET_ABSOLUTE_TIME_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value)
+#define CH_SWITCH_GET_PERIODIC_OPT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 3, 2)
+#define CH_SWITCH_SET_PERIODIC_OPT(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 3, 2, value)
+#define CH_SWITCH_SET_PERIODIC_OPT_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 3, 2, value)
+#define CH_SWITCH_GET_INFO_LOC(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)
+#define CH_SWITCH_SET_INFO_LOC(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define CH_SWITCH_SET_INFO_LOC_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define CH_SWITCH_GET_CH_NUM(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
+#define CH_SWITCH_SET_CH_NUM(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define CH_SWITCH_SET_CH_NUM_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define CH_SWITCH_GET_PRI_CH_IDX(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 4)
+#define CH_SWITCH_SET_PRI_CH_IDX(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 4, value)
+#define CH_SWITCH_SET_PRI_CH_IDX_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 4, value)
+#define CH_SWITCH_GET_DEST_BW(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 28, 4)
+#define CH_SWITCH_SET_DEST_BW(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 28, 4, value)
+#define CH_SWITCH_SET_DEST_BW_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 28, 4, value)
+#define CH_SWITCH_GET_DEST_CH(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 8)
+#define CH_SWITCH_SET_DEST_CH(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 8, value)
+#define CH_SWITCH_SET_DEST_CH_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 8, value)
+#define CH_SWITCH_GET_NORMAL_PERIOD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 8, 6)
+#define CH_SWITCH_SET_NORMAL_PERIOD(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 8, 6, value)
+#define CH_SWITCH_SET_NORMAL_PERIOD_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 8, 6, value)
+#define CH_SWITCH_GET_NORMAL_PERIOD_SEL(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X0C, 14, 2)
+#define CH_SWITCH_SET_NORMAL_PERIOD_SEL(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 14, 2, value)
+#define CH_SWITCH_SET_NORMAL_PERIOD_SEL_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 14, 2, value)
+#define CH_SWITCH_GET_SLOW_PERIOD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 16, 6)
+#define CH_SWITCH_SET_SLOW_PERIOD(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 16, 6, value)
+#define CH_SWITCH_SET_SLOW_PERIOD_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 16, 6, value)
+#define CH_SWITCH_GET_SLOW_PERIOD_SEL(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X0C, 22, 2)
+#define CH_SWITCH_SET_SLOW_PERIOD_SEL(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 22, 2, value)
+#define CH_SWITCH_SET_SLOW_PERIOD_SEL_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 22, 2, value)
+#define CH_SWITCH_GET_NORMAL_CYCLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 24, 8)
+#define CH_SWITCH_SET_NORMAL_CYCLE(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 24, 8, value)
+#define CH_SWITCH_SET_NORMAL_CYCLE_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 24, 8, value)
+#define CH_SWITCH_GET_TSF_HIGH(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X10, 0, 32)
+#define CH_SWITCH_SET_TSF_HIGH(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 32, value)
+#define CH_SWITCH_SET_TSF_HIGH_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 32, value)
+#define CH_SWITCH_GET_TSF_LOW(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X14, 0, 32)
+#define CH_SWITCH_SET_TSF_LOW(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 0, 32, value)
+#define CH_SWITCH_SET_TSF_LOW_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 0, 32, value)
+#define CH_SWITCH_GET_INFO_SIZE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X18, 0, 16)
+#define CH_SWITCH_SET_INFO_SIZE(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 0, 16, value)
+#define CH_SWITCH_SET_INFO_SIZE_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 0, 16, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_FUNC_EN(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)
+#define UPDATE_BEACON_PARSING_INFO_SET_FUNC_EN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define UPDATE_BEACON_PARSING_INFO_SET_FUNC_EN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_SIZE_TH(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X08, 8, 4)
+#define UPDATE_BEACON_PARSING_INFO_SET_SIZE_TH(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 4, value)
+#define UPDATE_BEACON_PARSING_INFO_SET_SIZE_TH_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 4, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_TIMEOUT(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X08, 12, 4)
+#define UPDATE_BEACON_PARSING_INFO_SET_TIMEOUT(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 12, 4, value)
+#define UPDATE_BEACON_PARSING_INFO_SET_TIMEOUT_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 12, 4, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_0(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 32)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_0(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 32, value)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_0_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 32, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_1(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X10, 0, 32)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_1(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 32, value)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_1_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 32, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_2(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X14, 0, 32)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_2(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 0, 32, value)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_2_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 0, 32, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_3(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X18, 0, 32)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_3(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 0, 32, value)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_3_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 0, 32, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_4(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X1C, 0, 32)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_4(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X1C, 0, 32, value)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_4_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X1C, 0, 32, value)
+#define CFG_PARAM_GET_NUM(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 16)
+#define CFG_PARAM_SET_NUM(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 16, value)
+#define CFG_PARAM_SET_NUM_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 16, value)
+#define CFG_PARAM_GET_INIT_CASE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 1)
+#define CFG_PARAM_SET_INIT_CASE(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 1, value)
+#define CFG_PARAM_SET_INIT_CASE_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 1, value)
+#define CFG_PARAM_GET_LOC(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)
+#define CFG_PARAM_SET_LOC(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define CFG_PARAM_SET_LOC_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define UPDATE_DATAPACK_GET_SIZE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 16)
+#define UPDATE_DATAPACK_SET_SIZE(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 16, value)
+#define UPDATE_DATAPACK_SET_SIZE_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 16, value)
+#define UPDATE_DATAPACK_GET_DATAPACK_ID(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
+#define UPDATE_DATAPACK_SET_DATAPACK_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define UPDATE_DATAPACK_SET_DATAPACK_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define UPDATE_DATAPACK_GET_DATAPACK_LOC(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)
+#define UPDATE_DATAPACK_SET_DATAPACK_LOC(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define UPDATE_DATAPACK_SET_DATAPACK_LOC_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define UPDATE_DATAPACK_GET_DATAPACK_SEGMENT(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 8)
+#define UPDATE_DATAPACK_SET_DATAPACK_SEGMENT(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 8, value)
+#define UPDATE_DATAPACK_SET_DATAPACK_SEGMENT_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 8, value)
+#define UPDATE_DATAPACK_GET_END_SEGMENT(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X0C, 8, 1)
+#define UPDATE_DATAPACK_SET_END_SEGMENT(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 8, 1, value)
+#define UPDATE_DATAPACK_SET_END_SEGMENT_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 8, 1, value)
+#define RUN_DATAPACK_GET_DATAPACK_ID(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8)
+#define RUN_DATAPACK_SET_DATAPACK_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define RUN_DATAPACK_SET_DATAPACK_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define DOWNLOAD_FLASH_GET_SPI_CMD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8)
+#define DOWNLOAD_FLASH_SET_SPI_CMD(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define DOWNLOAD_FLASH_SET_SPI_CMD_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define DOWNLOAD_FLASH_GET_LOCATION(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X08, 8, 16)
+#define DOWNLOAD_FLASH_SET_LOCATION(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 16, value)
+#define DOWNLOAD_FLASH_SET_LOCATION_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 16, value)
+#define DOWNLOAD_FLASH_GET_SIZE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 32)
+#define DOWNLOAD_FLASH_SET_SIZE(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 32, value)
+#define DOWNLOAD_FLASH_SET_SIZE_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 32, value)
+#define DOWNLOAD_FLASH_GET_START_ADDR(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X10, 0, 32)
+#define DOWNLOAD_FLASH_SET_START_ADDR(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 32, value)
+#define DOWNLOAD_FLASH_SET_START_ADDR_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 32, value)
+#define UPDATE_PKT_GET_SIZE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 16)
+#define UPDATE_PKT_SET_SIZE(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 16, value)
+#define UPDATE_PKT_SET_SIZE_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 16, value)
+#define UPDATE_PKT_GET_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
+#define UPDATE_PKT_SET_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define UPDATE_PKT_SET_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define UPDATE_PKT_GET_LOC(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)
+#define UPDATE_PKT_SET_LOC(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define UPDATE_PKT_SET_LOC_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define GENERAL_INFO_GET_FW_TX_BOUNDARY(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
+#define GENERAL_INFO_SET_FW_TX_BOUNDARY(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define GENERAL_INFO_SET_FW_TX_BOUNDARY_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define IQK_GET_CLEAR(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)
+#define IQK_SET_CLEAR(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define IQK_SET_CLEAR_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define IQK_GET_SEGMENT_IQK(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1)
+#define IQK_SET_SEGMENT_IQK(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value)
+#define IQK_SET_SEGMENT_IQK_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value)
+#define PWR_TRK_GET_ENABLE_A(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)
+#define PWR_TRK_SET_ENABLE_A(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define PWR_TRK_SET_ENABLE_A_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define PWR_TRK_GET_ENABLE_B(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1)
+#define PWR_TRK_SET_ENABLE_B(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value)
+#define PWR_TRK_SET_ENABLE_B_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value)
+#define PWR_TRK_GET_ENABLE_C(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1)
+#define PWR_TRK_SET_ENABLE_C(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value)
+#define PWR_TRK_SET_ENABLE_C_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value)
+#define PWR_TRK_GET_ENABLE_D(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 3, 1)
+#define PWR_TRK_SET_ENABLE_D(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 3, 1, value)
+#define PWR_TRK_SET_ENABLE_D_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 3, 1, value)
+#define PWR_TRK_GET_TYPE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 4, 3)
+#define PWR_TRK_SET_TYPE(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 4, 3, value)
+#define PWR_TRK_SET_TYPE_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 4, 3, value)
+#define PWR_TRK_GET_BBSWING_INDEX(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)
+#define PWR_TRK_SET_BBSWING_INDEX(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define PWR_TRK_SET_BBSWING_INDEX_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define PWR_TRK_GET_TX_PWR_INDEX_A(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 8)
+#define PWR_TRK_SET_TX_PWR_INDEX_A(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 8, value)
+#define PWR_TRK_SET_TX_PWR_INDEX_A_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 8, value)
+#define PWR_TRK_GET_OFFSET_VALUE_A(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 8, 8)
+#define PWR_TRK_SET_OFFSET_VALUE_A(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 8, 8, value)
+#define PWR_TRK_SET_OFFSET_VALUE_A_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 8, 8, value)
+#define PWR_TRK_GET_TSSI_VALUE_A(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 16, 8)
+#define PWR_TRK_SET_TSSI_VALUE_A(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 16, 8, value)
+#define PWR_TRK_SET_TSSI_VALUE_A_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 16, 8, value)
+#define PWR_TRK_GET_TX_PWR_INDEX_B(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X10, 0, 8)
+#define PWR_TRK_SET_TX_PWR_INDEX_B(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 8, value)
+#define PWR_TRK_SET_TX_PWR_INDEX_B_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 8, value)
+#define PWR_TRK_GET_OFFSET_VALUE_B(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X10, 8, 8)
+#define PWR_TRK_SET_OFFSET_VALUE_B(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 8, 8, value)
+#define PWR_TRK_SET_OFFSET_VALUE_B_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 8, 8, value)
+#define PWR_TRK_GET_TSSI_VALUE_B(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X10, 16, 8)
+#define PWR_TRK_SET_TSSI_VALUE_B(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 16, 8, value)
+#define PWR_TRK_SET_TSSI_VALUE_B_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 16, 8, value)
+#define PWR_TRK_GET_TX_PWR_INDEX_C(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X14, 0, 8)
+#define PWR_TRK_SET_TX_PWR_INDEX_C(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 0, 8, value)
+#define PWR_TRK_SET_TX_PWR_INDEX_C_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 0, 8, value)
+#define PWR_TRK_GET_OFFSET_VALUE_C(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X14, 8, 8)
+#define PWR_TRK_SET_OFFSET_VALUE_C(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 8, 8, value)
+#define PWR_TRK_SET_OFFSET_VALUE_C_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 8, 8, value)
+#define PWR_TRK_GET_TSSI_VALUE_C(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X14, 16, 8)
+#define PWR_TRK_SET_TSSI_VALUE_C(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 16, 8, value)
+#define PWR_TRK_SET_TSSI_VALUE_C_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 16, 8, value)
+#define PWR_TRK_GET_TX_PWR_INDEX_D(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X18, 0, 8)
+#define PWR_TRK_SET_TX_PWR_INDEX_D(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 0, 8, value)
+#define PWR_TRK_SET_TX_PWR_INDEX_D_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 0, 8, value)
+#define PWR_TRK_GET_OFFSET_VALUE_D(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X18, 8, 8)
+#define PWR_TRK_SET_OFFSET_VALUE_D(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 8, 8, value)
+#define PWR_TRK_SET_OFFSET_VALUE_D_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 8, 8, value)
+#define PWR_TRK_GET_TSSI_VALUE_D(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X18, 16, 8)
+#define PWR_TRK_SET_TSSI_VALUE_D(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 16, 8, value)
+#define PWR_TRK_SET_TSSI_VALUE_D_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 16, 8, value)
+#define PSD_GET_START_PSD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 16)
+#define PSD_SET_START_PSD(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 16, value)
+#define PSD_SET_START_PSD_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 16, value)
+#define PSD_GET_END_PSD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 16)
+#define PSD_SET_END_PSD(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 16, value)
+#define PSD_SET_END_PSD_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 16, value)
+#define P2PPS_GET_OFFLOAD_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)
+#define P2PPS_SET_OFFLOAD_EN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define P2PPS_SET_OFFLOAD_EN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define P2PPS_GET_ROLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1)
+#define P2PPS_SET_ROLE(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value)
+#define P2PPS_SET_ROLE_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value)
+#define P2PPS_GET_CTWINDOW_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1)
+#define P2PPS_SET_CTWINDOW_EN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value)
+#define P2PPS_SET_CTWINDOW_EN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value)
+#define P2PPS_GET_NOA_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 3, 1)
+#define P2PPS_SET_NOA_EN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 3, 1, value)
+#define P2PPS_SET_NOA_EN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 3, 1, value)
+#define P2PPS_GET_NOA_SEL(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 4, 1)
+#define P2PPS_SET_NOA_SEL(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 4, 1, value)
+#define P2PPS_SET_NOA_SEL_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 4, 1, value)
+#define P2PPS_GET_ALLSTASLEEP(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 5, 1)
+#define P2PPS_SET_ALLSTASLEEP(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 5, 1, value)
+#define P2PPS_SET_ALLSTASLEEP_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 5, 1, value)
+#define P2PPS_GET_DISCOVERY(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 6, 1)
+#define P2PPS_SET_DISCOVERY(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 6, 1, value)
+#define P2PPS_SET_DISCOVERY_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 6, 1, value)
+#define P2PPS_GET_DISABLE_CLOSERF(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 7, 1)
+#define P2PPS_SET_DISABLE_CLOSERF(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 7, 1, value)
+#define P2PPS_SET_DISABLE_CLOSERF_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 7, 1, value)
+#define P2PPS_GET_P2P_PORT_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)
+#define P2PPS_SET_P2P_PORT_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define P2PPS_SET_P2P_PORT_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define P2PPS_GET_P2P_GROUP(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
+#define P2PPS_SET_P2P_GROUP(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define P2PPS_SET_P2P_GROUP_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define P2PPS_GET_P2P_MACID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)
+#define P2PPS_SET_P2P_MACID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define P2PPS_SET_P2P_MACID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define P2PPS_GET_CTWINDOW_LENGTH(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 8)
+#define P2PPS_SET_CTWINDOW_LENGTH(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 8, value)
+#define P2PPS_SET_CTWINDOW_LENGTH_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 8, value)
+#define P2PPS_GET_NOA_DURATION_PARA(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X10, 0, 32)
+#define P2PPS_SET_NOA_DURATION_PARA(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 32, value)
+#define P2PPS_SET_NOA_DURATION_PARA_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 32, value)
+#define P2PPS_GET_NOA_INTERVAL_PARA(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X14, 0, 32)
+#define P2PPS_SET_NOA_INTERVAL_PARA(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 0, 32, value)
+#define P2PPS_SET_NOA_INTERVAL_PARA_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 0, 32, value)
+#define P2PPS_GET_NOA_START_TIME_PARA(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X18, 0, 32)
+#define P2PPS_SET_NOA_START_TIME_PARA(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 0, 32, value)
+#define P2PPS_SET_NOA_START_TIME_PARA_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 0, 32, value)
+#define P2PPS_GET_NOA_COUNT_PARA(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X1C, 0, 32)
+#define P2PPS_SET_NOA_COUNT_PARA(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X1C, 0, 32, value)
+#define P2PPS_SET_NOA_COUNT_PARA_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X1C, 0, 32, value)
+#define BT_COEX_GET_DATA_START(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8)
+#define BT_COEX_SET_DATA_START(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define BT_COEX_SET_DATA_START_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define NAN_CTRL_GET_NAN_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 2)
+#define NAN_CTRL_SET_NAN_EN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 2, value)
+#define NAN_CTRL_SET_NAN_EN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 2, value)
+#define NAN_CTRL_GET_WARMUP_TIMER_FLAG(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1)
+#define NAN_CTRL_SET_WARMUP_TIMER_FLAG(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value)
+#define NAN_CTRL_SET_WARMUP_TIMER_FLAG_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value)
+#define NAN_CTRL_GET_SUPPORT_BAND(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 2)
+#define NAN_CTRL_SET_SUPPORT_BAND(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 2, value)
+#define NAN_CTRL_SET_SUPPORT_BAND_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 2, value)
+#define NAN_CTRL_GET_DISABLE_2G_DISC_BCN(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X08, 10, 1)
+#define NAN_CTRL_SET_DISABLE_2G_DISC_BCN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 10, 1, value)
+#define NAN_CTRL_SET_DISABLE_2G_DISC_BCN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 10, 1, value)
+#define NAN_CTRL_GET_DISABLE_5G_DISC_BCN(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X08, 11, 1)
+#define NAN_CTRL_SET_DISABLE_5G_DISC_BCN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 11, 1, value)
+#define NAN_CTRL_SET_DISABLE_5G_DISC_BCN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 11, 1, value)
+#define NAN_CTRL_GET_BCN_RSVD_PAGE_OFFSET(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
+#define NAN_CTRL_SET_BCN_RSVD_PAGE_OFFSET(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define NAN_CTRL_SET_BCN_RSVD_PAGE_OFFSET_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define NAN_CTRL_GET_CHANNEL_2G(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)
+#define NAN_CTRL_SET_CHANNEL_2G(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define NAN_CTRL_SET_CHANNEL_2G_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define NAN_CTRL_GET_CHANNEL_5G(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 8)
+#define NAN_CTRL_SET_CHANNEL_5G(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 8, value)
+#define NAN_CTRL_SET_CHANNEL_5G_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 8, value)
+#define NAN_CTRL_GET_MASTERPREFERENCE_VALUE(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X0C, 8, 8)
+#define NAN_CTRL_SET_MASTERPREFERENCE_VALUE(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 8, 8, value)
+#define NAN_CTRL_SET_MASTERPREFERENCE_VALUE_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 8, 8, value)
+#define NAN_CTRL_GET_RANDOMFACTOR_VALUE(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X0C, 16, 8)
+#define NAN_CTRL_SET_RANDOMFACTOR_VALUE(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 16, 8, value)
+#define NAN_CTRL_SET_RANDOMFACTOR_VALUE_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 16, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_0(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8)
+#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_0(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_0_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_0(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)
+#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_0(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_0_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_0(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 16)
+#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_0(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 16, value)
+#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_0_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 16, value)
+#define NAN_CHANNEL_PLAN_0_GET_DURATION_0(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X0C, 16, 16)
+#define NAN_CHANNEL_PLAN_0_SET_DURATION_0(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 16, 16, value)
+#define NAN_CHANNEL_PLAN_0_SET_DURATION_0_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 16, 16, value)
+#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_1(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X10, 0, 8)
+#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_1(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 8, value)
+#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_1_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_1(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X10, 8, 8)
+#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_1(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 8, 8, value)
+#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_1_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 8, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_1(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X14, 0, 16)
+#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_1(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 0, 16, value)
+#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_1_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 0, 16, value)
+#define NAN_CHANNEL_PLAN_0_GET_DURATION_1(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X14, 16, 16)
+#define NAN_CHANNEL_PLAN_0_SET_DURATION_1(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 16, 16, value)
+#define NAN_CHANNEL_PLAN_0_SET_DURATION_1_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 16, 16, value)
+#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_2(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X18, 0, 8)
+#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_2(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 0, 8, value)
+#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_2_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 0, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_2(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X18, 8, 8)
+#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_2(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 8, 8, value)
+#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_2_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 8, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_2(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X1C, 0, 16)
+#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_2(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X1C, 0, 16, value)
+#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_2_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X1C, 0, 16, value)
+#define NAN_CHANNEL_PLAN_0_GET_DURATION_2(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X1C, 16, 16)
+#define NAN_CHANNEL_PLAN_0_SET_DURATION_2(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X1C, 16, 16, value)
+#define NAN_CHANNEL_PLAN_0_SET_DURATION_2_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X1C, 16, 16, value)
+#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_3(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8)
+#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_3(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_3_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_3(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)
+#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_3(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_3_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_3(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 16)
+#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_3(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 16, value)
+#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_3_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 16, value)
+#define NAN_CHANNEL_PLAN_1_GET_DURATION_3(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X0C, 16, 16)
+#define NAN_CHANNEL_PLAN_1_SET_DURATION_3(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 16, 16, value)
+#define NAN_CHANNEL_PLAN_1_SET_DURATION_3_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 16, 16, value)
+#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_4(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X10, 0, 8)
+#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_4(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 0, 8, value)
+#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_4_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 0, 8, value)
+#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_4(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X10, 8, 8)
+#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_4(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X10, 8, 8, value)
+#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_4_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X10, 8, 8, value)
+#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_4(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X14, 0, 16)
+#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_4(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 0, 16, value)
+#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_4_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 0, 16, value)
+#define NAN_CHANNEL_PLAN_1_GET_DURATION_4(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X14, 16, 16)
+#define NAN_CHANNEL_PLAN_1_SET_DURATION_4(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X14, 16, 16, value)
+#define NAN_CHANNEL_PLAN_1_SET_DURATION_4_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X14, 16, 16, value)
+#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_5(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X18, 0, 8)
+#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_5(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 0, 8, value)
+#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_5_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 0, 8, value)
+#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_5(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X18, 8, 8)
+#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_5(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X18, 8, 8, value)
+#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_5_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X18, 8, 8, value)
+#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_5(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X1C, 0, 16)
+#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_5(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X1C, 0, 16, value)
+#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_5_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X1C, 0, 16, value)
+#define NAN_CHANNEL_PLAN_1_GET_DURATION_5(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X1C, 16, 16)
+#define NAN_CHANNEL_PLAN_1_SET_DURATION_5(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X1C, 16, 16, value)
+#define NAN_CHANNEL_PLAN_1_SET_DURATION_5_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X1C, 16, 16, value)
+#define FW_ACCESS_TEST_GET_ACCESS_TXFF(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_TXFF(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_TXFF_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_RXFF(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_RXFF(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_RXFF_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_FWFF(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_FWFF(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_FWFF_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PHYFF(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X08, 3, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PHYFF(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 3, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_PHYFF_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 3, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_RPT_BUF(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X08, 4, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_RPT_BUF(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 4, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_RPT_BUF_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 4, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_CAM(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X08, 5, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_CAM(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 5, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_CAM_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 5, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_WOW_CAM(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X08, 6, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_WOW_CAM(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 6, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_WOW_CAM_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 6, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_RX_CAM(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X08, 7, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_RX_CAM(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 7, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_RX_CAM_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 7, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_BA_CAM(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X08, 8, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_BA_CAM(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_BA_CAM_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_MBSSID_CAM(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X08, 9, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_MBSSID_CAM(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 9, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_MBSSID_CAM_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 9, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE0(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X08, 16, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE0(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE0_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE1(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X08, 17, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE1(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 17, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE1_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 17, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE2(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X08, 18, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE2(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 18, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE2_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 18, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE3(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X08, 19, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE3(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 19, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE3_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 19, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE4(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X08, 20, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE4(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 20, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE4_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 20, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE5(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X08, 21, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE5(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 21, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE5_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 21, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE6(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X08, 22, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE6(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 22, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE6_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 22, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE7(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X08, 23, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE7(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 23, 1, value)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE7_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 23, 1, value)
+#define PHYDM_INFO_GET_REF_TYPE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8)
+#define PHYDM_INFO_SET_REF_TYPE(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define PHYDM_INFO_SET_REF_TYPE_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define PHYDM_INFO_GET_RF_TYPE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)
+#define PHYDM_INFO_SET_RF_TYPE(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define PHYDM_INFO_SET_RF_TYPE_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define PHYDM_INFO_GET_CUT_VER(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
+#define PHYDM_INFO_SET_CUT_VER(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define PHYDM_INFO_SET_CUT_VER_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define PHYDM_INFO_GET_RX_ANT_STATUS(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X08, 24, 4)
+#define PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 4, value)
+#define PHYDM_INFO_SET_RX_ANT_STATUS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 4, value)
+#define PHYDM_INFO_GET_TX_ANT_STATUS(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X08, 28, 4)
+#define PHYDM_INFO_SET_TX_ANT_STATUS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 28, 4, value)
+#define PHYDM_INFO_SET_TX_ANT_STATUS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 28, 4, value)
+#define FW_SNDING_GET_SU0(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 1)
+#define FW_SNDING_SET_SU0(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define FW_SNDING_SET_SU0_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 1, value)
+#define FW_SNDING_GET_SU1(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 1, 1)
+#define FW_SNDING_SET_SU1(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 1, 1, value)
+#define FW_SNDING_SET_SU1_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 1, 1, value)
+#define FW_SNDING_GET_MU(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 2, 1)
+#define FW_SNDING_SET_MU(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 2, 1, value)
+#define FW_SNDING_SET_MU_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 2, 1, value)
+#define FW_SNDING_GET_PERIOD(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 8)
+#define FW_SNDING_SET_PERIOD(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define FW_SNDING_SET_PERIOD_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 8, value)
+#define FW_SNDING_GET_NDPA0_HEAD_PG(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
+#define FW_SNDING_SET_NDPA0_HEAD_PG(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define FW_SNDING_SET_NDPA0_HEAD_PG_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define FW_SNDING_GET_NDPA1_HEAD_PG(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)
+#define FW_SNDING_SET_NDPA1_HEAD_PG(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define FW_SNDING_SET_NDPA1_HEAD_PG_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define FW_SNDING_GET_MU_NDPA_HEAD_PG(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0XC, 0, 8)
+#define FW_SNDING_SET_MU_NDPA_HEAD_PG(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 0, 8, value)
+#define FW_SNDING_SET_MU_NDPA_HEAD_PG_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 0, 8, value)
+#define FW_SNDING_GET_RPT0_HEAD_PG(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0XC, 8, 8)
+#define FW_SNDING_SET_RPT0_HEAD_PG(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 8, 8, value)
+#define FW_SNDING_SET_RPT0_HEAD_PG_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 8, 8, value)
+#define FW_SNDING_GET_RPT1_HEAD_PG(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0XC, 16, 8)
+#define FW_SNDING_SET_RPT1_HEAD_PG(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 16, 8, value)
+#define FW_SNDING_SET_RPT1_HEAD_PG_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 16, 8, value)
+#define FW_SNDING_GET_RPT2_HEAD_PG(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0XC, 24, 8)
+#define FW_SNDING_SET_RPT2_HEAD_PG(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0XC, 24, 8, value)
+#define FW_SNDING_SET_RPT2_HEAD_PG_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0XC, 24, 8, value)
+#define FW_FWCTRL_GET_SEQ_NUM(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 0, 8)
+#define FW_FWCTRL_SET_SEQ_NUM(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define FW_FWCTRL_SET_SEQ_NUM_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 0, 8, value)
+#define FW_FWCTRL_GET_MORE_CONTENT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 8, 1)
+#define FW_FWCTRL_SET_MORE_CONTENT(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 8, 1, value)
+#define FW_FWCTRL_SET_MORE_CONTENT_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 8, 1, value)
+#define FW_FWCTRL_GET_CONTENT_IDX(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 9, 7)
+#define FW_FWCTRL_SET_CONTENT_IDX(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 9, 7, value)
+#define FW_FWCTRL_SET_CONTENT_IDX_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 9, 7, value)
+#define FW_FWCTRL_GET_CLASS_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 16, 8)
+#define FW_FWCTRL_SET_CLASS_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define FW_FWCTRL_SET_CLASS_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 16, 8, value)
+#define FW_FWCTRL_GET_LENGTH(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X08, 24, 8)
+#define FW_FWCTRL_SET_LENGTH(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define FW_FWCTRL_SET_LENGTH_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X08, 24, 8, value)
+#define FW_FWCTRL_GET_CONTENT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X0C, 0, 32)
+#define FW_FWCTRL_SET_CONTENT(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X0C, 0, 32, value)
+#define FW_FWCTRL_SET_CONTENT_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X0C, 0, 32, value)
#endif
diff --git a/hal/halmac/halmac_fw_offload_h2c_nic.h b/hal/halmac/halmac_fw_offload_h2c_nic.h
index 83f5740..525be7e 100644
--- a/hal/halmac/halmac_fw_offload_h2c_nic.h
+++ b/hal/halmac/halmac_fw_offload_h2c_nic.h
@@ -1,193 +1,694 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
#ifndef _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_NIC_H_
#define _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_NIC_H_
-#define CMD_ID_FW_OFFLOAD_H2C 0XFF
-#define CMD_ID_CHANNEL_SWITCH 0XFF
-#define CMD_ID_DUMP_PHYSICAL_EFUSE 0XFF
-#define CMD_ID_UPDATE_BEACON_PARSING_INFO 0XFF
-#define CMD_ID_CFG_PARAMETER 0XFF
-#define CMD_ID_UPDATE_DATAPACK 0XFF
-#define CMD_ID_RUN_DATAPACK 0XFF
-#define CMD_ID_DOWNLOAD_FLASH 0XFF
-#define CMD_ID_UPDATE_PACKET 0XFF
-#define CMD_ID_GENERAL_INFO 0XFF
-#define CMD_ID_IQK 0XFF
-#define CMD_ID_POWER_TRACKING 0XFF
-#define CMD_ID_PSD 0XFF
-#define CMD_ID_BT_COEX 0XFF
-#define CATEGORY_H2C_CMD_HEADER 0X00
-#define CATEGORY_FW_OFFLOAD_H2C 0X01
-#define CATEGORY_CHANNEL_SWITCH 0X01
-#define CATEGORY_DUMP_PHYSICAL_EFUSE 0X01
-#define CATEGORY_UPDATE_BEACON_PARSING_INFO 0X01
-#define CATEGORY_CFG_PARAMETER 0X01
-#define CATEGORY_UPDATE_DATAPACK 0X01
-#define CATEGORY_RUN_DATAPACK 0X01
-#define CATEGORY_DOWNLOAD_FLASH 0X01
-#define CATEGORY_UPDATE_PACKET 0X01
-#define CATEGORY_GENERAL_INFO 0X01
-#define CATEGORY_IQK 0X01
-#define CATEGORY_POWER_TRACKING 0X01
-#define CATEGORY_PSD 0X01
-#define CATEGORY_BT_COEX 0X01
-#define SUB_CMD_ID_CHANNEL_SWITCH 0X02
-#define SUB_CMD_ID_DUMP_PHYSICAL_EFUSE 0X03
-#define SUB_CMD_ID_UPDATE_BEACON_PARSING_INFO 0X05
-#define SUB_CMD_ID_CFG_PARAMETER 0X08
-#define SUB_CMD_ID_UPDATE_DATAPACK 0X09
-#define SUB_CMD_ID_RUN_DATAPACK 0X0A
-#define SUB_CMD_ID_DOWNLOAD_FLASH 0X0B
-#define SUB_CMD_ID_UPDATE_PACKET 0X0C
-#define SUB_CMD_ID_GENERAL_INFO 0X0D
-#define SUB_CMD_ID_IQK 0X0E
-#define SUB_CMD_ID_POWER_TRACKING 0X0F
-#define SUB_CMD_ID_PSD 0X10
-#define SUB_CMD_ID_BT_COEX 0X60
-#define H2C_CMD_HEADER_GET_CATEGORY(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 7)
-#define H2C_CMD_HEADER_SET_CATEGORY(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 7, __Value)
-#define H2C_CMD_HEADER_GET_ACK(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 7, 1)
-#define H2C_CMD_HEADER_SET_ACK(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 7, 1, __Value)
-#define H2C_CMD_HEADER_GET_TOTAL_LEN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 16)
-#define H2C_CMD_HEADER_SET_TOTAL_LEN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 16, __Value)
-#define H2C_CMD_HEADER_GET_SEQ_NUM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 16)
-#define H2C_CMD_HEADER_SET_SEQ_NUM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 16, __Value)
-#define FW_OFFLOAD_H2C_GET_CATEGORY(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 7)
-#define FW_OFFLOAD_H2C_SET_CATEGORY(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 7, __Value)
-#define FW_OFFLOAD_H2C_GET_ACK(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 7, 1)
-#define FW_OFFLOAD_H2C_SET_ACK(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 7, 1, __Value)
-#define FW_OFFLOAD_H2C_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8)
-#define FW_OFFLOAD_H2C_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value)
-#define FW_OFFLOAD_H2C_GET_SUB_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 16)
-#define FW_OFFLOAD_H2C_SET_SUB_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 16, __Value)
-#define FW_OFFLOAD_H2C_GET_TOTAL_LEN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 16)
-#define FW_OFFLOAD_H2C_SET_TOTAL_LEN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 16, __Value)
-#define FW_OFFLOAD_H2C_GET_SEQ_NUM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 16)
-#define FW_OFFLOAD_H2C_SET_SEQ_NUM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 16, __Value)
-#define CHANNEL_SWITCH_GET_SWITCH_START(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 1)
-#define CHANNEL_SWITCH_SET_SWITCH_START(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 1, __Value)
-#define CHANNEL_SWITCH_GET_DEST_CH_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 1, 1)
-#define CHANNEL_SWITCH_SET_DEST_CH_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 1, 1, __Value)
-#define CHANNEL_SWITCH_GET_ABSOLUTE_TIME(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 2, 1)
-#define CHANNEL_SWITCH_SET_ABSOLUTE_TIME(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 2, 1, __Value)
-#define CHANNEL_SWITCH_GET_PERIODIC_OPTION(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 3, 2)
-#define CHANNEL_SWITCH_SET_PERIODIC_OPTION(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 3, 2, __Value)
-#define CHANNEL_SWITCH_GET_CHANNEL_INFO_LOC(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 8, 8)
-#define CHANNEL_SWITCH_SET_CHANNEL_INFO_LOC(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 8, 8, __Value)
-#define CHANNEL_SWITCH_GET_CHANNEL_NUM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 16, 8)
-#define CHANNEL_SWITCH_SET_CHANNEL_NUM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 16, 8, __Value)
-#define CHANNEL_SWITCH_GET_PRI_CH_IDX(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 24, 4)
-#define CHANNEL_SWITCH_SET_PRI_CH_IDX(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 24, 4, __Value)
-#define CHANNEL_SWITCH_GET_DEST_BW(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 28, 4)
-#define CHANNEL_SWITCH_SET_DEST_BW(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 28, 4, __Value)
-#define CHANNEL_SWITCH_GET_DEST_CH(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 0, 8)
-#define CHANNEL_SWITCH_SET_DEST_CH(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 0, 8, __Value)
-#define CHANNEL_SWITCH_GET_NORMAL_PERIOD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 8, 8)
-#define CHANNEL_SWITCH_SET_NORMAL_PERIOD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 8, 8, __Value)
-#define CHANNEL_SWITCH_GET_SLOW_PERIOD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 16, 8)
-#define CHANNEL_SWITCH_SET_SLOW_PERIOD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 16, 8, __Value)
-#define CHANNEL_SWITCH_GET_NORMAL_CYCLE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 24, 8)
-#define CHANNEL_SWITCH_SET_NORMAL_CYCLE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 24, 8, __Value)
-#define CHANNEL_SWITCH_GET_TSF_HIGH(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 0, 32)
-#define CHANNEL_SWITCH_SET_TSF_HIGH(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 0, 32, __Value)
-#define CHANNEL_SWITCH_GET_TSF_LOW(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 0, 32)
-#define CHANNEL_SWITCH_SET_TSF_LOW(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 0, 32, __Value)
-#define CHANNEL_SWITCH_GET_CHANNEL_INFO_SIZE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 0, 16)
-#define CHANNEL_SWITCH_SET_CHANNEL_INFO_SIZE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 0, 16, __Value)
-#define UPDATE_BEACON_PARSING_INFO_GET_FUNC_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 1)
-#define UPDATE_BEACON_PARSING_INFO_SET_FUNC_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 1, __Value)
-#define UPDATE_BEACON_PARSING_INFO_GET_SIZE_TH(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 8, 4)
-#define UPDATE_BEACON_PARSING_INFO_SET_SIZE_TH(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 8, 4, __Value)
-#define UPDATE_BEACON_PARSING_INFO_GET_TIMEOUT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 12, 4)
-#define UPDATE_BEACON_PARSING_INFO_SET_TIMEOUT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 12, 4, __Value)
-#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_0(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 0, 32)
-#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_0(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 0, 32, __Value)
-#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 0, 32)
-#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 0, 32, __Value)
-#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 0, 32)
-#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 0, 32, __Value)
-#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_3(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 0, 32)
-#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_3(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 0, 32, __Value)
-#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_4(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X1C, 0, 32)
-#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_4(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X1C, 0, 32, __Value)
-#define CFG_PARAMETER_GET_NUM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 16)
-#define CFG_PARAMETER_SET_NUM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 16, __Value)
-#define CFG_PARAMETER_GET_INIT_CASE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 16, 1)
-#define CFG_PARAMETER_SET_INIT_CASE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 16, 1, __Value)
-#define CFG_PARAMETER_GET_PHY_PARAMETER_LOC(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 24, 8)
-#define CFG_PARAMETER_SET_PHY_PARAMETER_LOC(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 24, 8, __Value)
-#define UPDATE_DATAPACK_GET_SIZE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 16)
-#define UPDATE_DATAPACK_SET_SIZE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 16, __Value)
-#define UPDATE_DATAPACK_GET_DATAPACK_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 16, 8)
-#define UPDATE_DATAPACK_SET_DATAPACK_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 16, 8, __Value)
-#define UPDATE_DATAPACK_GET_DATAPACK_LOC(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 24, 8)
-#define UPDATE_DATAPACK_SET_DATAPACK_LOC(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 24, 8, __Value)
-#define UPDATE_DATAPACK_GET_DATAPACK_SEGMENT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 0, 8)
-#define UPDATE_DATAPACK_SET_DATAPACK_SEGMENT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 0, 8, __Value)
-#define UPDATE_DATAPACK_GET_END_SEGMENT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 8, 1)
-#define UPDATE_DATAPACK_SET_END_SEGMENT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 8, 1, __Value)
-#define RUN_DATAPACK_GET_DATAPACK_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 8)
-#define RUN_DATAPACK_SET_DATAPACK_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 8, __Value)
-#define DOWNLOAD_FLASH_GET_SPI_CMD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 8)
-#define DOWNLOAD_FLASH_SET_SPI_CMD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 8, __Value)
-#define DOWNLOAD_FLASH_GET_LOCATION(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 8, 16)
-#define DOWNLOAD_FLASH_SET_LOCATION(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 8, 16, __Value)
-#define DOWNLOAD_FLASH_GET_SIZE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 0, 32)
-#define DOWNLOAD_FLASH_SET_SIZE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 0, 32, __Value)
-#define DOWNLOAD_FLASH_GET_START_ADDR(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 0, 32)
-#define DOWNLOAD_FLASH_SET_START_ADDR(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 0, 32, __Value)
-#define UPDATE_PACKET_GET_SIZE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 16)
-#define UPDATE_PACKET_SET_SIZE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 16, __Value)
-#define UPDATE_PACKET_GET_PACKET_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 16, 8)
-#define UPDATE_PACKET_SET_PACKET_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 16, 8, __Value)
-#define UPDATE_PACKET_GET_PACKET_LOC(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 24, 8)
-#define UPDATE_PACKET_SET_PACKET_LOC(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 24, 8, __Value)
-#define GENERAL_INFO_GET_REF_TYPE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 8)
-#define GENERAL_INFO_SET_REF_TYPE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 8, __Value)
-#define GENERAL_INFO_GET_RF_TYPE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 8, 9)
-#define GENERAL_INFO_SET_RF_TYPE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 8, 9, __Value)
-#define GENERAL_INFO_GET_FW_TX_BOUNDARY(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 16, 8)
-#define GENERAL_INFO_SET_FW_TX_BOUNDARY(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 16, 8, __Value)
-#define IQK_GET_CLEAR(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 1)
-#define IQK_SET_CLEAR(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 1, __Value)
-#define POWER_TRACKING_GET_ENABLE_A(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 1)
-#define POWER_TRACKING_SET_ENABLE_A(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 1, __Value)
-#define POWER_TRACKING_GET_ENABLE_B(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 1, 1)
-#define POWER_TRACKING_SET_ENABLE_B(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 1, 1, __Value)
-#define POWER_TRACKING_GET_ENABLE_C(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 2, 1)
-#define POWER_TRACKING_SET_ENABLE_C(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 2, 1, __Value)
-#define POWER_TRACKING_GET_ENABLE_D(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 3, 1)
-#define POWER_TRACKING_SET_ENABLE_D(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 3, 1, __Value)
-#define POWER_TRACKING_GET_TYPE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 4, 3)
-#define POWER_TRACKING_SET_TYPE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 4, 3, __Value)
-#define POWER_TRACKING_GET_BBSWING_INDEX(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 8, 8)
-#define POWER_TRACKING_SET_BBSWING_INDEX(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 8, 8, __Value)
-#define POWER_TRACKING_GET_TX_PWR_INDEX_A(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 0, 8)
-#define POWER_TRACKING_SET_TX_PWR_INDEX_A(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 0, 8, __Value)
-#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_A(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 8, 8)
-#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_A(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 8, 8, __Value)
-#define POWER_TRACKING_GET_TSSI_VALUE_A(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 16, 8)
-#define POWER_TRACKING_SET_TSSI_VALUE_A(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 16, 8, __Value)
-#define POWER_TRACKING_GET_TX_PWR_INDEX_B(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 0, 8)
-#define POWER_TRACKING_SET_TX_PWR_INDEX_B(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 0, 8, __Value)
-#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_B(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 8, 8)
-#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_B(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 8, 8, __Value)
-#define POWER_TRACKING_GET_TSSI_VALUE_B(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 16, 8)
-#define POWER_TRACKING_SET_TSSI_VALUE_B(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 16, 8, __Value)
-#define POWER_TRACKING_GET_TX_PWR_INDEX_C(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 0, 8)
-#define POWER_TRACKING_SET_TX_PWR_INDEX_C(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 0, 8, __Value)
-#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_C(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 8, 8)
-#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_C(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 8, 8, __Value)
-#define POWER_TRACKING_GET_TSSI_VALUE_C(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 16, 8)
-#define POWER_TRACKING_SET_TSSI_VALUE_C(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 16, 8, __Value)
-#define POWER_TRACKING_GET_TX_PWR_INDEX_D(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 0, 8)
-#define POWER_TRACKING_SET_TX_PWR_INDEX_D(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 0, 8, __Value)
-#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_D(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 8, 8)
-#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_D(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 8, 8, __Value)
-#define POWER_TRACKING_GET_TSSI_VALUE_D(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 16, 8)
-#define POWER_TRACKING_SET_TSSI_VALUE_D(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 16, 8, __Value)
-#define PSD_GET_START_PSD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 16)
-#define PSD_SET_START_PSD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 16, __Value)
-#define PSD_GET_END_PSD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 16, 16)
-#define PSD_SET_END_PSD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 16, 16, __Value)
-#define BT_COEX_GET_DATA_START(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 8)
-#define BT_COEX_SET_DATA_START(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 8, __Value)
+#define CMD_ID_FW_OFFLOAD_H2C 0XFF
+#define CMD_ID_CH_SWITCH 0XFF
+#define CMD_ID_DUMP_PHYSICAL_EFUSE 0XFF
+#define CMD_ID_UPDATE_BEACON_PARSING_INFO 0XFF
+#define CMD_ID_CFG_PARAM 0XFF
+#define CMD_ID_UPDATE_DATAPACK 0XFF
+#define CMD_ID_RUN_DATAPACK 0XFF
+#define CMD_ID_DOWNLOAD_FLASH 0XFF
+#define CMD_ID_UPDATE_PKT 0XFF
+#define CMD_ID_GENERAL_INFO 0XFF
+#define CMD_ID_IQK 0XFF
+#define CMD_ID_PWR_TRK 0XFF
+#define CMD_ID_PSD 0XFF
+#define CMD_ID_P2PPS 0XFF
+#define CMD_ID_BT_COEX 0XFF
+#define CMD_ID_NAN_CTRL 0XFF
+#define CMD_ID_NAN_CHANNEL_PLAN_0 0XFF
+#define CMD_ID_NAN_CHANNEL_PLAN_1 0XFF
+#define CMD_ID_FW_ACCESS_TEST 0XFF
+#define CMD_ID_PHYDM_INFO 0XFF
+#define CMD_ID_FW_SNDING 0XFF
+#define CMD_ID_H2C_LOOPBACK 0XFF
+#define CMD_ID_FWCMD_LOOPBACK 0XFF
+#define CMD_ID_FW_FWCTRL 0XFF
+#define CATEGORY_H2C_CMD_HEADER 0X00
+#define CATEGORY_FW_OFFLOAD_H2C 0X01
+#define CATEGORY_CH_SWITCH 0X01
+#define CATEGORY_DUMP_PHYSICAL_EFUSE 0X01
+#define CATEGORY_UPDATE_BEACON_PARSING_INFO 0X01
+#define CATEGORY_CFG_PARAM 0X01
+#define CATEGORY_UPDATE_DATAPACK 0X01
+#define CATEGORY_RUN_DATAPACK 0X01
+#define CATEGORY_DOWNLOAD_FLASH 0X01
+#define CATEGORY_UPDATE_PKT 0X01
+#define CATEGORY_GENERAL_INFO 0X01
+#define CATEGORY_IQK 0X01
+#define CATEGORY_PWR_TRK 0X01
+#define CATEGORY_PSD 0X01
+#define CATEGORY_P2PPS 0X01
+#define CATEGORY_BT_COEX 0X01
+#define CATEGORY_NAN_CTRL 0X01
+#define CATEGORY_NAN_CHANNEL_PLAN_0 0X01
+#define CATEGORY_NAN_CHANNEL_PLAN_1 0X01
+#define CATEGORY_FW_ACCESS_TEST 0X01
+#define CATEGORY_PHYDM_INFO 0X01
+#define CATEGORY_FW_SNDING 0X01
+#define CATEGORY_H2C_LOOPBACK 0X01
+#define CATEGORY_FWCMD_LOOPBACK 0X01
+#define CATEGORY_FW_FWCTRL 0X01
+#define SUB_CMD_ID_CH_SWITCH 0X02
+#define SUB_CMD_ID_DUMP_PHYSICAL_EFUSE 0X03
+#define SUB_CMD_ID_UPDATE_BEACON_PARSING_INFO 0X05
+#define SUB_CMD_ID_CFG_PARAM 0X08
+#define SUB_CMD_ID_UPDATE_DATAPACK 0X09
+#define SUB_CMD_ID_RUN_DATAPACK 0X0A
+#define SUB_CMD_ID_DOWNLOAD_FLASH 0X0B
+#define SUB_CMD_ID_UPDATE_PKT 0X0C
+#define SUB_CMD_ID_GENERAL_INFO 0X0D
+#define SUB_CMD_ID_IQK 0X0E
+#define SUB_CMD_ID_PWR_TRK 0X0F
+#define SUB_CMD_ID_PSD 0X10
+#define SUB_CMD_ID_P2PPS 0X24
+#define SUB_CMD_ID_BT_COEX 0X60
+#define SUB_CMD_ID_NAN_CTRL 0XB2
+#define SUB_CMD_ID_NAN_CHANNEL_PLAN_0 0XB4
+#define SUB_CMD_ID_NAN_CHANNEL_PLAN_1 0XB5
+#define SUB_CMD_ID_FW_ACCESS_TEST 0X00
+#define SUB_CMD_ID_PHYDM_INFO 0X11
+#define SUB_CMD_ID_FW_SNDING 0X12
+#define SUB_CMD_ID_FW_FWCTRL 0X13
+#define SUB_CMD_ID_H2C_LOOPBACK 0X14
+#define SUB_CMD_ID_FWCMD_LOOPBACK 0X15
+#define H2C_CMD_HEADER_GET_CATEGORY(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 7)
+#define H2C_CMD_HEADER_SET_CATEGORY(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 7, value)
+#define H2C_CMD_HEADER_GET_ACK(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 7, 1)
+#define H2C_CMD_HEADER_SET_ACK(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 7, 1, value)
+#define H2C_CMD_HEADER_GET_TOTAL_LEN(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 16)
+#define H2C_CMD_HEADER_SET_TOTAL_LEN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 16, value)
+#define H2C_CMD_HEADER_GET_SEQ_NUM(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 16)
+#define H2C_CMD_HEADER_SET_SEQ_NUM(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 16, value)
+#define FW_OFFLOAD_H2C_GET_CATEGORY(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 7)
+#define FW_OFFLOAD_H2C_SET_CATEGORY(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 7, value)
+#define FW_OFFLOAD_H2C_GET_ACK(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 7, 1)
+#define FW_OFFLOAD_H2C_SET_ACK(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 7, 1, value)
+#define FW_OFFLOAD_H2C_GET_CMD_ID(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define FW_OFFLOAD_H2C_SET_CMD_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define FW_OFFLOAD_H2C_GET_SUB_CMD_ID(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 16)
+#define FW_OFFLOAD_H2C_SET_SUB_CMD_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 16, value)
+#define FW_OFFLOAD_H2C_GET_TOTAL_LEN(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 16)
+#define FW_OFFLOAD_H2C_SET_TOTAL_LEN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 16, value)
+#define FW_OFFLOAD_H2C_GET_SEQ_NUM(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 16)
+#define FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 16, value)
+#define CH_SWITCH_GET_START(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)
+#define CH_SWITCH_SET_START(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)
+#define CH_SWITCH_GET_DEST_CH_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1)
+#define CH_SWITCH_SET_DEST_CH_EN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value)
+#define CH_SWITCH_GET_ABSOLUTE_TIME(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1)
+#define CH_SWITCH_SET_ABSOLUTE_TIME(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value)
+#define CH_SWITCH_GET_PERIODIC_OPT(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 3, 2)
+#define CH_SWITCH_SET_PERIODIC_OPT(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 3, 2, value)
+#define CH_SWITCH_GET_INFO_LOC(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)
+#define CH_SWITCH_SET_INFO_LOC(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)
+#define CH_SWITCH_GET_CH_NUM(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
+#define CH_SWITCH_SET_CH_NUM(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
+#define CH_SWITCH_GET_PRI_CH_IDX(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 4)
+#define CH_SWITCH_SET_PRI_CH_IDX(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 4, value)
+#define CH_SWITCH_GET_DEST_BW(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 28, 4)
+#define CH_SWITCH_SET_DEST_BW(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 28, 4, value)
+#define CH_SWITCH_GET_DEST_CH(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 8)
+#define CH_SWITCH_SET_DEST_CH(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 8, value)
+#define CH_SWITCH_GET_NORMAL_PERIOD(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 8, 6)
+#define CH_SWITCH_SET_NORMAL_PERIOD(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 8, 6, value)
+#define CH_SWITCH_GET_NORMAL_PERIOD_SEL(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 14, 2)
+#define CH_SWITCH_SET_NORMAL_PERIOD_SEL(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 14, 2, value)
+#define CH_SWITCH_GET_SLOW_PERIOD(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 16, 6)
+#define CH_SWITCH_SET_SLOW_PERIOD(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 16, 6, value)
+#define CH_SWITCH_GET_SLOW_PERIOD_SEL(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 22, 2)
+#define CH_SWITCH_SET_SLOW_PERIOD_SEL(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 22, 2, value)
+#define CH_SWITCH_GET_NORMAL_CYCLE(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 24, 8)
+#define CH_SWITCH_SET_NORMAL_CYCLE(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 24, 8, value)
+#define CH_SWITCH_GET_TSF_HIGH(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 32)
+#define CH_SWITCH_SET_TSF_HIGH(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 32, value)
+#define CH_SWITCH_GET_TSF_LOW(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 0, 32)
+#define CH_SWITCH_SET_TSF_LOW(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 0, 32, value)
+#define CH_SWITCH_GET_INFO_SIZE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 0, 16)
+#define CH_SWITCH_SET_INFO_SIZE(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 0, 16, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_FUNC_EN(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)
+#define UPDATE_BEACON_PARSING_INFO_SET_FUNC_EN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_SIZE_TH(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 4)
+#define UPDATE_BEACON_PARSING_INFO_SET_SIZE_TH(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 4, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_TIMEOUT(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 12, 4)
+#define UPDATE_BEACON_PARSING_INFO_SET_TIMEOUT(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 12, 4, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_0(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 32)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_0(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 32, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_1(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 32)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_1(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 32, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_2(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 0, 32)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_2(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 0, 32, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_3(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 0, 32)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_3(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 0, 32, value)
+#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_4(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X1C, 0, 32)
+#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_4(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X1C, 0, 32, value)
+#define CFG_PARAM_GET_NUM(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 16)
+#define CFG_PARAM_SET_NUM(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 16, value)
+#define CFG_PARAM_GET_INIT_CASE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 1)
+#define CFG_PARAM_SET_INIT_CASE(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 1, value)
+#define CFG_PARAM_GET_LOC(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)
+#define CFG_PARAM_SET_LOC(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)
+#define UPDATE_DATAPACK_GET_SIZE(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 16)
+#define UPDATE_DATAPACK_SET_SIZE(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 16, value)
+#define UPDATE_DATAPACK_GET_DATAPACK_ID(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
+#define UPDATE_DATAPACK_SET_DATAPACK_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
+#define UPDATE_DATAPACK_GET_DATAPACK_LOC(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)
+#define UPDATE_DATAPACK_SET_DATAPACK_LOC(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)
+#define UPDATE_DATAPACK_GET_DATAPACK_SEGMENT(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 8)
+#define UPDATE_DATAPACK_SET_DATAPACK_SEGMENT(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 8, value)
+#define UPDATE_DATAPACK_GET_END_SEGMENT(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 8, 1)
+#define UPDATE_DATAPACK_SET_END_SEGMENT(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 8, 1, value)
+#define RUN_DATAPACK_GET_DATAPACK_ID(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8)
+#define RUN_DATAPACK_SET_DATAPACK_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value)
+#define DOWNLOAD_FLASH_GET_SPI_CMD(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8)
+#define DOWNLOAD_FLASH_SET_SPI_CMD(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value)
+#define DOWNLOAD_FLASH_GET_LOCATION(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 16)
+#define DOWNLOAD_FLASH_SET_LOCATION(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 16, value)
+#define DOWNLOAD_FLASH_GET_SIZE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 32)
+#define DOWNLOAD_FLASH_SET_SIZE(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 32, value)
+#define DOWNLOAD_FLASH_GET_START_ADDR(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 32)
+#define DOWNLOAD_FLASH_SET_START_ADDR(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 32, value)
+#define UPDATE_PKT_GET_SIZE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 16)
+#define UPDATE_PKT_SET_SIZE(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 16, value)
+#define UPDATE_PKT_GET_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
+#define UPDATE_PKT_SET_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
+#define UPDATE_PKT_GET_LOC(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)
+#define UPDATE_PKT_SET_LOC(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)
+#define GENERAL_INFO_GET_FW_TX_BOUNDARY(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
+#define GENERAL_INFO_SET_FW_TX_BOUNDARY(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
+#define IQK_GET_CLEAR(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)
+#define IQK_SET_CLEAR(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)
+#define IQK_GET_SEGMENT_IQK(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1)
+#define IQK_SET_SEGMENT_IQK(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value)
+#define PWR_TRK_GET_ENABLE_A(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)
+#define PWR_TRK_SET_ENABLE_A(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)
+#define PWR_TRK_GET_ENABLE_B(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1)
+#define PWR_TRK_SET_ENABLE_B(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value)
+#define PWR_TRK_GET_ENABLE_C(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1)
+#define PWR_TRK_SET_ENABLE_C(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value)
+#define PWR_TRK_GET_ENABLE_D(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 3, 1)
+#define PWR_TRK_SET_ENABLE_D(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 3, 1, value)
+#define PWR_TRK_GET_TYPE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 4, 3)
+#define PWR_TRK_SET_TYPE(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 4, 3, value)
+#define PWR_TRK_GET_BBSWING_INDEX(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)
+#define PWR_TRK_SET_BBSWING_INDEX(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)
+#define PWR_TRK_GET_TX_PWR_INDEX_A(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 8)
+#define PWR_TRK_SET_TX_PWR_INDEX_A(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 8, value)
+#define PWR_TRK_GET_OFFSET_VALUE_A(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 8, 8)
+#define PWR_TRK_SET_OFFSET_VALUE_A(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 8, 8, value)
+#define PWR_TRK_GET_TSSI_VALUE_A(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 16, 8)
+#define PWR_TRK_SET_TSSI_VALUE_A(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 16, 8, value)
+#define PWR_TRK_GET_TX_PWR_INDEX_B(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 8)
+#define PWR_TRK_SET_TX_PWR_INDEX_B(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 8, value)
+#define PWR_TRK_GET_OFFSET_VALUE_B(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 8, 8)
+#define PWR_TRK_SET_OFFSET_VALUE_B(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 8, 8, value)
+#define PWR_TRK_GET_TSSI_VALUE_B(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 16, 8)
+#define PWR_TRK_SET_TSSI_VALUE_B(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 16, 8, value)
+#define PWR_TRK_GET_TX_PWR_INDEX_C(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 0, 8)
+#define PWR_TRK_SET_TX_PWR_INDEX_C(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 0, 8, value)
+#define PWR_TRK_GET_OFFSET_VALUE_C(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 8, 8)
+#define PWR_TRK_SET_OFFSET_VALUE_C(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 8, 8, value)
+#define PWR_TRK_GET_TSSI_VALUE_C(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 16, 8)
+#define PWR_TRK_SET_TSSI_VALUE_C(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 16, 8, value)
+#define PWR_TRK_GET_TX_PWR_INDEX_D(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 0, 8)
+#define PWR_TRK_SET_TX_PWR_INDEX_D(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 0, 8, value)
+#define PWR_TRK_GET_OFFSET_VALUE_D(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 8, 8)
+#define PWR_TRK_SET_OFFSET_VALUE_D(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 8, 8, value)
+#define PWR_TRK_GET_TSSI_VALUE_D(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 16, 8)
+#define PWR_TRK_SET_TSSI_VALUE_D(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 16, 8, value)
+#define PSD_GET_START_PSD(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 16)
+#define PSD_SET_START_PSD(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 16, value)
+#define PSD_GET_END_PSD(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 16)
+#define PSD_SET_END_PSD(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 16, value)
+#define P2PPS_GET_OFFLOAD_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)
+#define P2PPS_SET_OFFLOAD_EN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)
+#define P2PPS_GET_ROLE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1)
+#define P2PPS_SET_ROLE(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value)
+#define P2PPS_GET_CTWINDOW_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1)
+#define P2PPS_SET_CTWINDOW_EN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value)
+#define P2PPS_GET_NOA_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 3, 1)
+#define P2PPS_SET_NOA_EN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 3, 1, value)
+#define P2PPS_GET_NOA_SEL(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 4, 1)
+#define P2PPS_SET_NOA_SEL(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 4, 1, value)
+#define P2PPS_GET_ALLSTASLEEP(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 5, 1)
+#define P2PPS_SET_ALLSTASLEEP(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 5, 1, value)
+#define P2PPS_GET_DISCOVERY(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 6, 1)
+#define P2PPS_SET_DISCOVERY(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 6, 1, value)
+#define P2PPS_GET_DISABLE_CLOSERF(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 7, 1)
+#define P2PPS_SET_DISABLE_CLOSERF(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 7, 1, value)
+#define P2PPS_GET_P2P_PORT_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)
+#define P2PPS_SET_P2P_PORT_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)
+#define P2PPS_GET_P2P_GROUP(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
+#define P2PPS_SET_P2P_GROUP(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
+#define P2PPS_GET_P2P_MACID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)
+#define P2PPS_SET_P2P_MACID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)
+#define P2PPS_GET_CTWINDOW_LENGTH(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 8)
+#define P2PPS_SET_CTWINDOW_LENGTH(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 8, value)
+#define P2PPS_GET_NOA_DURATION_PARA(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 32)
+#define P2PPS_SET_NOA_DURATION_PARA(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 32, value)
+#define P2PPS_GET_NOA_INTERVAL_PARA(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 0, 32)
+#define P2PPS_SET_NOA_INTERVAL_PARA(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 0, 32, value)
+#define P2PPS_GET_NOA_START_TIME_PARA(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 0, 32)
+#define P2PPS_SET_NOA_START_TIME_PARA(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 0, 32, value)
+#define P2PPS_GET_NOA_COUNT_PARA(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X1C, 0, 32)
+#define P2PPS_SET_NOA_COUNT_PARA(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X1C, 0, 32, value)
+#define BT_COEX_GET_DATA_START(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8)
+#define BT_COEX_SET_DATA_START(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value)
+#define NAN_CTRL_GET_NAN_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 2)
+#define NAN_CTRL_SET_NAN_EN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 2, value)
+#define NAN_CTRL_GET_WARMUP_TIMER_FLAG(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1)
+#define NAN_CTRL_SET_WARMUP_TIMER_FLAG(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value)
+#define NAN_CTRL_GET_SUPPORT_BAND(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 2)
+#define NAN_CTRL_SET_SUPPORT_BAND(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 2, value)
+#define NAN_CTRL_GET_DISABLE_2G_DISC_BCN(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 10, 1)
+#define NAN_CTRL_SET_DISABLE_2G_DISC_BCN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 10, 1, value)
+#define NAN_CTRL_GET_DISABLE_5G_DISC_BCN(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 11, 1)
+#define NAN_CTRL_SET_DISABLE_5G_DISC_BCN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 11, 1, value)
+#define NAN_CTRL_GET_BCN_RSVD_PAGE_OFFSET(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
+#define NAN_CTRL_SET_BCN_RSVD_PAGE_OFFSET(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
+#define NAN_CTRL_GET_CHANNEL_2G(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)
+#define NAN_CTRL_SET_CHANNEL_2G(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)
+#define NAN_CTRL_GET_CHANNEL_5G(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 8)
+#define NAN_CTRL_SET_CHANNEL_5G(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 8, value)
+#define NAN_CTRL_GET_MASTERPREFERENCE_VALUE(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 8, 8)
+#define NAN_CTRL_SET_MASTERPREFERENCE_VALUE(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 8, 8, value)
+#define NAN_CTRL_GET_RANDOMFACTOR_VALUE(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 16, 8)
+#define NAN_CTRL_SET_RANDOMFACTOR_VALUE(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 16, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_0(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8)
+#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_0(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_0(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)
+#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_0(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_0(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 16)
+#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_0(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 16, value)
+#define NAN_CHANNEL_PLAN_0_GET_DURATION_0(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 16, 16)
+#define NAN_CHANNEL_PLAN_0_SET_DURATION_0(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 16, 16, value)
+#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_1(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 8)
+#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_1(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_1(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 8, 8)
+#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_1(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 8, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_1(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 0, 16)
+#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_1(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 0, 16, value)
+#define NAN_CHANNEL_PLAN_0_GET_DURATION_1(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 16, 16)
+#define NAN_CHANNEL_PLAN_0_SET_DURATION_1(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 16, 16, value)
+#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_2(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 0, 8)
+#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_2(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 0, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_2(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 8, 8)
+#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_2(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 8, 8, value)
+#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_2(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X1C, 0, 16)
+#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_2(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X1C, 0, 16, value)
+#define NAN_CHANNEL_PLAN_0_GET_DURATION_2(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X1C, 16, 16)
+#define NAN_CHANNEL_PLAN_0_SET_DURATION_2(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X1C, 16, 16, value)
+#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_3(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8)
+#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_3(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value)
+#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_3(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)
+#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_3(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)
+#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_3(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 16)
+#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_3(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 16, value)
+#define NAN_CHANNEL_PLAN_1_GET_DURATION_3(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 16, 16)
+#define NAN_CHANNEL_PLAN_1_SET_DURATION_3(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 16, 16, value)
+#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_4(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 0, 8)
+#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_4(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 0, 8, value)
+#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_4(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X10, 8, 8)
+#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_4(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X10, 8, 8, value)
+#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_4(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 0, 16)
+#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_4(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 0, 16, value)
+#define NAN_CHANNEL_PLAN_1_GET_DURATION_4(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X14, 16, 16)
+#define NAN_CHANNEL_PLAN_1_SET_DURATION_4(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X14, 16, 16, value)
+#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_5(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 0, 8)
+#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_5(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 0, 8, value)
+#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_5(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X18, 8, 8)
+#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_5(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X18, 8, 8, value)
+#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_5(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X1C, 0, 16)
+#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_5(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X1C, 0, 16, value)
+#define NAN_CHANNEL_PLAN_1_GET_DURATION_5(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X1C, 16, 16)
+#define NAN_CHANNEL_PLAN_1_SET_DURATION_5(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X1C, 16, 16, value)
+#define FW_ACCESS_TEST_GET_ACCESS_TXFF(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_TXFF(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_RXFF(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_RXFF(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_FWFF(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_FWFF(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PHYFF(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 3, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PHYFF(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 3, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_RPT_BUF(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 4, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_RPT_BUF(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 4, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_CAM(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 5, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_CAM(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 5, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_WOW_CAM(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 6, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_WOW_CAM(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 6, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_RX_CAM(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 7, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_RX_CAM(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 7, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_BA_CAM(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_BA_CAM(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_MBSSID_CAM(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 9, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_MBSSID_CAM(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 9, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE0(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE0(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE1(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 17, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE1(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 17, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE2(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 18, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE2(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 18, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE3(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 19, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE3(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 19, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE4(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 20, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE4(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 20, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE5(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 21, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE5(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 21, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE6(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 22, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE6(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 22, 1, value)
+#define FW_ACCESS_TEST_GET_ACCESS_PAGE7(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 23, 1)
+#define FW_ACCESS_TEST_SET_ACCESS_PAGE7(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 23, 1, value)
+#define PHYDM_INFO_GET_REF_TYPE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8)
+#define PHYDM_INFO_SET_REF_TYPE(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value)
+#define PHYDM_INFO_GET_RF_TYPE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)
+#define PHYDM_INFO_SET_RF_TYPE(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)
+#define PHYDM_INFO_GET_CUT_VER(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
+#define PHYDM_INFO_SET_CUT_VER(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
+#define PHYDM_INFO_GET_RX_ANT_STATUS(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 4)
+#define PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 4, value)
+#define PHYDM_INFO_GET_TX_ANT_STATUS(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 28, 4)
+#define PHYDM_INFO_SET_TX_ANT_STATUS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 28, 4, value)
+#define FW_SNDING_GET_SU0(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 1)
+#define FW_SNDING_SET_SU0(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 1, value)
+#define FW_SNDING_GET_SU1(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 1, 1)
+#define FW_SNDING_SET_SU1(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 1, 1, value)
+#define FW_SNDING_GET_MU(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 2, 1)
+#define FW_SNDING_SET_MU(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 2, 1, value)
+#define FW_SNDING_GET_PERIOD(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 8)
+#define FW_SNDING_SET_PERIOD(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 8, value)
+#define FW_SNDING_GET_NDPA0_HEAD_PG(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
+#define FW_SNDING_SET_NDPA0_HEAD_PG(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
+#define FW_SNDING_GET_NDPA1_HEAD_PG(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)
+#define FW_SNDING_SET_NDPA1_HEAD_PG(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)
+#define FW_SNDING_GET_MU_NDPA_HEAD_PG(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 0, 8)
+#define FW_SNDING_SET_MU_NDPA_HEAD_PG(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 0, 8, value)
+#define FW_SNDING_GET_RPT0_HEAD_PG(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 8, 8)
+#define FW_SNDING_SET_RPT0_HEAD_PG(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 8, 8, value)
+#define FW_SNDING_GET_RPT1_HEAD_PG(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 16, 8)
+#define FW_SNDING_SET_RPT1_HEAD_PG(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 16, 8, value)
+#define FW_SNDING_GET_RPT2_HEAD_PG(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0XC, 24, 8)
+#define FW_SNDING_SET_RPT2_HEAD_PG(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0XC, 24, 8, value)
+#define FW_FWCTRL_GET_SEQ_NUM(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 0, 8)
+#define FW_FWCTRL_SET_SEQ_NUM(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 0, 8, value)
+#define FW_FWCTRL_GET_MORE_CONTENT(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 8, 1)
+#define FW_FWCTRL_SET_MORE_CONTENT(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 8, 1, value)
+#define FW_FWCTRL_GET_CONTENT_IDX(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 9, 7)
+#define FW_FWCTRL_SET_CONTENT_IDX(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 9, 7, value)
+#define FW_FWCTRL_GET_CLASS_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 16, 8)
+#define FW_FWCTRL_SET_CLASS_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 16, 8, value)
+#define FW_FWCTRL_GET_LENGTH(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X08, 24, 8)
+#define FW_FWCTRL_SET_LENGTH(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X08, 24, 8, value)
+#define FW_FWCTRL_GET_CONTENT(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X0C, 0, 32)
+#define FW_FWCTRL_SET_CONTENT(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X0C, 0, 32, value)
#endif
diff --git a/hal/halmac/halmac_gpio_cmd.h b/hal/halmac/halmac_gpio_cmd.h
new file mode 100644
index 0000000..803458f
--- /dev/null
+++ b/hal/halmac/halmac_gpio_cmd.h
@@ -0,0 +1,84 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef HALMAC_GPIO_CMD
+#define HALMAC_GPIO_CMD
+
+#include "halmac_2_platform.h"
+
+/* GPIO ID */
+#define HALMAC_GPIO0 0
+#define HALMAC_GPIO1 1
+#define HALMAC_GPIO2 2
+#define HALMAC_GPIO3 3
+#define HALMAC_GPIO4 4
+#define HALMAC_GPIO5 5
+#define HALMAC_GPIO6 6
+#define HALMAC_GPIO7 7
+#define HALMAC_GPIO8 8
+#define HALMAC_GPIO9 9
+#define HALMAC_GPIO10 10
+#define HALMAC_GPIO11 11
+#define HALMAC_GPIO12 12
+#define HALMAC_GPIO13 13
+#define HALMAC_GPIO14 14
+#define HALMAC_GPIO15 15
+#define HALMAC_GPIO_NUM 16
+
+/* GPIO type */
+#define HALMAC_GPIO_IN 0
+#define HALMAC_GPIO_OUT 1
+#define HALMAC_GPIO_IN_OUT 2
+
+/* Function name */
+#define HALMAC_WL_HWPDN 0
+#define HALMAC_BT_HWPDN 1
+#define HALMAC_BT_GPIO 2
+#define HALMAC_WL_HW_EXTWOL 3
+#define HALMAC_BT_HW_EXTWOL 4
+#define HALMAC_BT_SFLASH 5
+#define HALMAC_WL_SFLASH 6
+#define HALMAC_WL_LED 7
+#define HALMAC_SDIO_INT 8
+#define HALMAC_UART0 9
+#define HALMAC_EEPROM 10
+#define HALMAC_JTAG 11
+#define HALMAC_LTE_COEX_UART 12
+#define HALMAC_3W_LTE_WL_GPIO 13
+#define HALMAC_GPIO2_3_WL_CTRL_EN 14
+#define HALMAC_GPIO13_14_WL_CTRL_EN 15
+#define HALMAC_DBG_GNT_WL_BT 16
+#define HALMAC_BT_3DDLS_A 17
+#define HALMAC_BT_3DDLS_B 18
+#define HALMAC_BT_PTA 19
+#define HALMAC_WL_PTA 20
+#define HALMAC_WL_UART 21
+#define HALMAC_WLMAC_DBG 22
+#define HALMAC_WLPHY_DBG 23
+#define HALMAC_BT_DBG 24
+#define HALMAC_WLPHY_RFE_CTRL2GPIO 25
+#define HALMAC_EXT_XTAL 26
+#define HALMAC_SW_IO 27
+
+struct halmac_gpio_pimux_list {
+ u16 func;
+ u8 id;
+ u8 type;
+ u16 offset;
+ u8 msk;
+ u8 value;
+};
+
+#endif
diff --git a/hal/halmac/halmac_h2c_extra_info_ap.h b/hal/halmac/halmac_h2c_extra_info_ap.h
index f19324a..8362987 100644
--- a/hal/halmac/halmac_h2c_extra_info_ap.h
+++ b/hal/halmac/halmac_h2c_extra_info_ap.h
@@ -1,69 +1,220 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
#ifndef _HAL_H2CEXTRAINFO_H2C_C2H_AP_H_
#define _HAL_H2CEXTRAINFO_H2C_C2H_AP_H_
-#define PHY_PARAMETER_INFO_GET_LENGTH(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 0, 8)
-#define PHY_PARAMETER_INFO_SET_LENGTH(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 0, 8, __Value)
-#define PHY_PARAMETER_INFO_SET_LENGTH_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 0, 8, __Value)
-#define PHY_PARAMETER_INFO_GET_IO_CMD(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 8, 7)
-#define PHY_PARAMETER_INFO_SET_IO_CMD(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 8, 7, __Value)
-#define PHY_PARAMETER_INFO_SET_IO_CMD_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 8, 7, __Value)
-#define PHY_PARAMETER_INFO_GET_MSK_EN(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 15, 1)
-#define PHY_PARAMETER_INFO_SET_MSK_EN(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 15, 1, __Value)
-#define PHY_PARAMETER_INFO_SET_MSK_EN_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 15, 1, __Value)
-#define PHY_PARAMETER_INFO_GET_LLT_PG_BNDY(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 16, 8)
-#define PHY_PARAMETER_INFO_SET_LLT_PG_BNDY(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 16, 8, __Value)
-#define PHY_PARAMETER_INFO_SET_LLT_PG_BNDY_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 16, 8, __Value)
-#define PHY_PARAMETER_INFO_GET_EFUSE_RSVDPAGE_LOC(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 16, 8)
-#define PHY_PARAMETER_INFO_SET_EFUSE_RSVDPAGE_LOC(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 16, 8, __Value)
-#define PHY_PARAMETER_INFO_SET_EFUSE_RSVDPAGE_LOC_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 16, 8, __Value)
-#define PHY_PARAMETER_INFO_GET_EFUSE_PATCH_EN(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 16, 8)
-#define PHY_PARAMETER_INFO_SET_EFUSE_PATCH_EN(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 16, 8, __Value)
-#define PHY_PARAMETER_INFO_SET_EFUSE_PATCH_EN_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 16, 8, __Value)
-#define PHY_PARAMETER_INFO_GET_RF_ADDR(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 16, 8)
-#define PHY_PARAMETER_INFO_SET_RF_ADDR(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 16, 8, __Value)
-#define PHY_PARAMETER_INFO_SET_RF_ADDR_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 16, 8, __Value)
-#define PHY_PARAMETER_INFO_GET_IO_ADDR(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 16, 16)
-#define PHY_PARAMETER_INFO_SET_IO_ADDR(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 16, 16, __Value)
-#define PHY_PARAMETER_INFO_SET_IO_ADDR_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 16, 16, __Value)
-#define PHY_PARAMETER_INFO_GET_DELAY_VALUE(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 16, 16)
-#define PHY_PARAMETER_INFO_SET_DELAY_VALUE(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 16, 16, __Value)
-#define PHY_PARAMETER_INFO_SET_DELAY_VALUE_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 16, 16, __Value)
-#define PHY_PARAMETER_INFO_GET_RF_PATH(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 24, 8)
-#define PHY_PARAMETER_INFO_SET_RF_PATH(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 24, 8, __Value)
-#define PHY_PARAMETER_INFO_SET_RF_PATH_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 24, 8, __Value)
-#define PHY_PARAMETER_INFO_GET_DATA(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X04, 0, 32)
-#define PHY_PARAMETER_INFO_SET_DATA(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X04, 0, 32, __Value)
-#define PHY_PARAMETER_INFO_SET_DATA_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X04, 0, 32, __Value)
-#define PHY_PARAMETER_INFO_GET_MASK(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X08, 0, 32)
-#define PHY_PARAMETER_INFO_SET_MASK(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X08, 0, 32, __Value)
-#define PHY_PARAMETER_INFO_SET_MASK_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X08, 0, 32, __Value)
-#define CHANNEL_INFO_GET_CHANNEL(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 0, 8)
-#define CHANNEL_INFO_SET_CHANNEL(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 0, 8, __Value)
-#define CHANNEL_INFO_SET_CHANNEL_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 0, 8, __Value)
-#define CHANNEL_INFO_GET_PRI_CH_IDX(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 8, 4)
-#define CHANNEL_INFO_SET_PRI_CH_IDX(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 8, 4, __Value)
-#define CHANNEL_INFO_SET_PRI_CH_IDX_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 8, 4, __Value)
-#define CHANNEL_INFO_GET_BANDWIDTH(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 12, 4)
-#define CHANNEL_INFO_SET_BANDWIDTH(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 12, 4, __Value)
-#define CHANNEL_INFO_SET_BANDWIDTH_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 12, 4, __Value)
-#define CHANNEL_INFO_GET_TIMEOUT(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 16, 8)
-#define CHANNEL_INFO_SET_TIMEOUT(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 16, 8, __Value)
-#define CHANNEL_INFO_SET_TIMEOUT_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 16, 8, __Value)
-#define CHANNEL_INFO_GET_ACTION_ID(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 24, 7)
-#define CHANNEL_INFO_SET_ACTION_ID(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 24, 7, __Value)
-#define CHANNEL_INFO_SET_ACTION_ID_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 24, 7, __Value)
-#define CHANNEL_INFO_GET_CH_EXTRA_INFO(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 31, 1)
-#define CHANNEL_INFO_SET_CH_EXTRA_INFO(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 31, 1, __Value)
-#define CHANNEL_INFO_SET_CH_EXTRA_INFO_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 31, 1, __Value)
-#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO_ID(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 0, 7)
-#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_ID(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 0, 7, __Value)
-#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_ID_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 0, 7, __Value)
-#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 7, 1)
-#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 7, 1, __Value)
-#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 7, 1, __Value)
-#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO_SIZE(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 8, 8)
-#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_SIZE(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 8, 8, __Value)
-#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_SIZE_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 8, 8, __Value)
-#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO_DATA(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 16, 1)
-#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_DATA(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 16, 1, __Value)
-#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_DATA_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 16, 1, __Value)
+#define PARAM_INFO_GET_LEN(extra_info) GET_C2H_FIELD(extra_info + 0X00, 0, 8)
+#define PARAM_INFO_SET_LEN(extra_info, value) \
+ SET_C2H_FIELD_CLR(extra_info + 0X00, 0, 8, value)
+#define PARAM_INFO_SET_LEN_NO_CLR(extra_info, value) \
+ SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 0, 8, value)
+#define PARAM_INFO_GET_IO_CMD(extra_info) GET_C2H_FIELD(extra_info + 0X00, 8, 7)
+#define PARAM_INFO_SET_IO_CMD(extra_info, value) \
+ SET_C2H_FIELD_CLR(extra_info + 0X00, 8, 7, value)
+#define PARAM_INFO_SET_IO_CMD_NO_CLR(extra_info, value) \
+ SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 8, 7, value)
+#define PARAM_INFO_GET_MSK_EN(extra_info) \
+ GET_C2H_FIELD(extra_info + 0X00, 15, 1)
+#define PARAM_INFO_SET_MSK_EN(extra_info, value) \
+ SET_C2H_FIELD_CLR(extra_info + 0X00, 15, 1, value)
+#define PARAM_INFO_SET_MSK_EN_NO_CLR(extra_info, value) \
+ SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 15, 1, value)
+#define PARAM_INFO_GET_LLT_PG_BNDY(extra_info) \
+ GET_C2H_FIELD(extra_info + 0X00, 16, 8)
+#define PARAM_INFO_SET_LLT_PG_BNDY(extra_info, value) \
+ SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 8, value)
+#define PARAM_INFO_SET_LLT_PG_BNDY_NO_CLR(extra_info, value) \
+ SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 8, value)
+#define PARAM_INFO_GET_EFUSE_RSVDPAGE_LOC(extra_info) \
+ GET_C2H_FIELD(extra_info + 0X00, 16, 8)
+#define PARAM_INFO_SET_EFUSE_RSVDPAGE_LOC(extra_info, value) \
+ SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 8, value)
+#define PARAM_INFO_SET_EFUSE_RSVDPAGE_LOC_NO_CLR(extra_info, value) \
+ SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 8, value)
+#define PARAM_INFO_GET_EFUSE_PATCH_EN(extra_info) \
+ GET_C2H_FIELD(extra_info + 0X00, 16, 8)
+#define PARAM_INFO_SET_EFUSE_PATCH_EN(extra_info, value) \
+ SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 8, value)
+#define PARAM_INFO_SET_EFUSE_PATCH_EN_NO_CLR(extra_info, value) \
+ SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 8, value)
+#define PARAM_INFO_GET_RF_ADDR(extra_info) \
+ GET_C2H_FIELD(extra_info + 0X00, 16, 8)
+#define PARAM_INFO_SET_RF_ADDR(extra_info, value) \
+ SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 8, value)
+#define PARAM_INFO_SET_RF_ADDR_NO_CLR(extra_info, value) \
+ SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 8, value)
+#define PARAM_INFO_GET_IO_ADDR(extra_info) \
+ GET_C2H_FIELD(extra_info + 0X00, 16, 16)
+#define PARAM_INFO_SET_IO_ADDR(extra_info, value) \
+ SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 16, value)
+#define PARAM_INFO_SET_IO_ADDR_NO_CLR(extra_info, value) \
+ SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 16, value)
+#define PARAM_INFO_GET_DELAY_VAL(extra_info) \
+ GET_C2H_FIELD(extra_info + 0X00, 16, 16)
+#define PARAM_INFO_SET_DELAY_VAL(extra_info, value) \
+ SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 16, value)
+#define PARAM_INFO_SET_DELAY_VAL_NO_CLR(extra_info, value) \
+ SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 16, value)
+#define PARAM_INFO_GET_RF_PATH(extra_info) \
+ GET_C2H_FIELD(extra_info + 0X00, 24, 8)
+#define PARAM_INFO_SET_RF_PATH(extra_info, value) \
+ SET_C2H_FIELD_CLR(extra_info + 0X00, 24, 8, value)
+#define PARAM_INFO_SET_RF_PATH_NO_CLR(extra_info, value) \
+ SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 24, 8, value)
+#define PARAM_INFO_GET_DATA(extra_info) GET_C2H_FIELD(extra_info + 0X04, 0, 32)
+#define PARAM_INFO_SET_DATA(extra_info, value) \
+ SET_C2H_FIELD_CLR(extra_info + 0X04, 0, 32, value)
+#define PARAM_INFO_SET_DATA_NO_CLR(extra_info, value) \
+ SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 0, 32, value)
+#define PARAM_INFO_GET_MASK(extra_info) GET_C2H_FIELD(extra_info + 0X08, 0, 32)
+#define PARAM_INFO_SET_MASK(extra_info, value) \
+ SET_C2H_FIELD_CLR(extra_info + 0X08, 0, 32, value)
+#define PARAM_INFO_SET_MASK_NO_CLR(extra_info, value) \
+ SET_C2H_FIELD_NO_CLR(extra_info + 0X08, 0, 32, value)
+#define CH_INFO_GET_CH(extra_info) GET_C2H_FIELD(extra_info + 0X00, 0, 8)
+#define CH_INFO_SET_CH(extra_info, value) \
+ SET_C2H_FIELD_CLR(extra_info + 0X00, 0, 8, value)
+#define CH_INFO_SET_CH_NO_CLR(extra_info, value) \
+ SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 0, 8, value)
+#define CH_INFO_GET_PRI_CH_IDX(extra_info) \
+ GET_C2H_FIELD(extra_info + 0X00, 8, 4)
+#define CH_INFO_SET_PRI_CH_IDX(extra_info, value) \
+ SET_C2H_FIELD_CLR(extra_info + 0X00, 8, 4, value)
+#define CH_INFO_SET_PRI_CH_IDX_NO_CLR(extra_info, value) \
+ SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 8, 4, value)
+#define CH_INFO_GET_BW(extra_info) GET_C2H_FIELD(extra_info + 0X00, 12, 4)
+#define CH_INFO_SET_BW(extra_info, value) \
+ SET_C2H_FIELD_CLR(extra_info + 0X00, 12, 4, value)
+#define CH_INFO_SET_BW_NO_CLR(extra_info, value) \
+ SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 12, 4, value)
+#define CH_INFO_GET_TIMEOUT(extra_info) GET_C2H_FIELD(extra_info + 0X00, 16, 8)
+#define CH_INFO_SET_TIMEOUT(extra_info, value) \
+ SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 8, value)
+#define CH_INFO_SET_TIMEOUT_NO_CLR(extra_info, value) \
+ SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 8, value)
+#define CH_INFO_GET_ACTION_ID(extra_info) \
+ GET_C2H_FIELD(extra_info + 0X00, 24, 7)
+#define CH_INFO_SET_ACTION_ID(extra_info, value) \
+ SET_C2H_FIELD_CLR(extra_info + 0X00, 24, 7, value)
+#define CH_INFO_SET_ACTION_ID_NO_CLR(extra_info, value) \
+ SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 24, 7, value)
+#define CH_INFO_GET_EXTRA_INFO(extra_info) \
+ GET_C2H_FIELD(extra_info + 0X00, 31, 1)
+#define CH_INFO_SET_EXTRA_INFO(extra_info, value) \
+ SET_C2H_FIELD_CLR(extra_info + 0X00, 31, 1, value)
+#define CH_INFO_SET_EXTRA_INFO_NO_CLR(extra_info, value) \
+ SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 31, 1, value)
+#define CH_EXTRA_INFO_GET_ID(extra_info) GET_C2H_FIELD(extra_info + 0X00, 0, 7)
+#define CH_EXTRA_INFO_SET_ID(extra_info, value) \
+ SET_C2H_FIELD_CLR(extra_info + 0X00, 0, 7, value)
+#define CH_EXTRA_INFO_SET_ID_NO_CLR(extra_info, value) \
+ SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 0, 7, value)
+#define CH_EXTRA_INFO_GET_INFO(extra_info) \
+ GET_C2H_FIELD(extra_info + 0X00, 7, 1)
+#define CH_EXTRA_INFO_SET_INFO(extra_info, value) \
+ SET_C2H_FIELD_CLR(extra_info + 0X00, 7, 1, value)
+#define CH_EXTRA_INFO_SET_INFO_NO_CLR(extra_info, value) \
+ SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 7, 1, value)
+#define CH_EXTRA_INFO_GET_SIZE(extra_info) \
+ GET_C2H_FIELD(extra_info + 0X00, 8, 8)
+#define CH_EXTRA_INFO_SET_SIZE(extra_info, value) \
+ SET_C2H_FIELD_CLR(extra_info + 0X00, 8, 8, value)
+#define CH_EXTRA_INFO_SET_SIZE_NO_CLR(extra_info, value) \
+ SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 8, 8, value)
+#define CH_EXTRA_INFO_GET_DATA(extra_info) \
+ GET_C2H_FIELD(extra_info + 0X00, 16, 1)
+#define CH_EXTRA_INFO_SET_DATA(extra_info, value) \
+ SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 1, value)
+#define CH_EXTRA_INFO_SET_DATA_NO_CLR(extra_info, value) \
+ SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 1, value)
+#define HIOE_INSTRUCTION_INFO_GET_BYTEDATA_L(extra_info) \
+ GET_C2H_FIELD(extra_info + 0X00, 0, 16)
+#define HIOE_INSTRUCTION_INFO_SET_BYTEDATA_L(extra_info, value) \
+ SET_C2H_FIELD_CLR(extra_info + 0X00, 0, 16, value)
+#define HIOE_INSTRUCTION_INFO_SET_BYTEDATA_L_NO_CLR(extra_info, value) \
+ SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 0, 16, value)
+#define HIOE_INSTRUCTION_INFO_GET_BITDATA(extra_info) \
+ GET_C2H_FIELD(extra_info + 0X00, 0, 16)
+#define HIOE_INSTRUCTION_INFO_SET_BITDATA(extra_info, value) \
+ SET_C2H_FIELD_CLR(extra_info + 0X00, 0, 16, value)
+#define HIOE_INSTRUCTION_INFO_SET_BITDATA_NO_CLR(extra_info, value) \
+ SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 0, 16, value)
+#define HIOE_INSTRUCTION_INFO_GET_BYTEDATA_H(extra_info) \
+ GET_C2H_FIELD(extra_info + 0X00, 16, 16)
+#define HIOE_INSTRUCTION_INFO_SET_BYTEDATA_H(extra_info, value) \
+ SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 16, value)
+#define HIOE_INSTRUCTION_INFO_SET_BYTEDATA_H_NO_CLR(extra_info, value) \
+ SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 16, value)
+#define HIOE_INSTRUCTION_INFO_GET_BITMASK(extra_info) \
+ GET_C2H_FIELD(extra_info + 0X00, 16, 16)
+#define HIOE_INSTRUCTION_INFO_SET_BITMASK(extra_info, value) \
+ SET_C2H_FIELD_CLR(extra_info + 0X00, 16, 16, value)
+#define HIOE_INSTRUCTION_INFO_SET_BITMASK_NO_CLR(extra_info, value) \
+ SET_C2H_FIELD_NO_CLR(extra_info + 0X00, 16, 16, value)
+#define HIOE_INSTRUCTION_INFO_GET_REG_ADDR(extra_info) \
+ GET_C2H_FIELD(extra_info + 0X04, 0, 22)
+#define HIOE_INSTRUCTION_INFO_SET_REG_ADDR(extra_info, value) \
+ SET_C2H_FIELD_CLR(extra_info + 0X04, 0, 22, value)
+#define HIOE_INSTRUCTION_INFO_SET_REG_ADDR_NO_CLR(extra_info, value) \
+ SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 0, 22, value)
+#define HIOE_INSTRUCTION_INFO_GET_DELAY_VALUE(extra_info) \
+ GET_C2H_FIELD(extra_info + 0X04, 0, 22)
+#define HIOE_INSTRUCTION_INFO_SET_DELAY_VALUE(extra_info, value) \
+ SET_C2H_FIELD_CLR(extra_info + 0X04, 0, 22, value)
+#define HIOE_INSTRUCTION_INFO_SET_DELAY_VALUE_NO_CLR(extra_info, value) \
+ SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 0, 22, value)
+#define HIOE_INSTRUCTION_INFO_GET_MODE_SELECT(extra_info) \
+ GET_C2H_FIELD(extra_info + 0X04, 22, 1)
+#define HIOE_INSTRUCTION_INFO_SET_MODE_SELECT(extra_info, value) \
+ SET_C2H_FIELD_CLR(extra_info + 0X04, 22, 1, value)
+#define HIOE_INSTRUCTION_INFO_SET_MODE_SELECT_NO_CLR(extra_info, value) \
+ SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 22, 1, value)
+#define HIOE_INSTRUCTION_INFO_GET_IO_DELAY(extra_info) \
+ GET_C2H_FIELD(extra_info + 0X04, 23, 1)
+#define HIOE_INSTRUCTION_INFO_SET_IO_DELAY(extra_info, value) \
+ SET_C2H_FIELD_CLR(extra_info + 0X04, 23, 1, value)
+#define HIOE_INSTRUCTION_INFO_SET_IO_DELAY_NO_CLR(extra_info, value) \
+ SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 23, 1, value)
+#define HIOE_INSTRUCTION_INFO_GET_BYTEMASK(extra_info) \
+ GET_C2H_FIELD(extra_info + 0X04, 24, 4)
+#define HIOE_INSTRUCTION_INFO_SET_BYTEMASK(extra_info, value) \
+ SET_C2H_FIELD_CLR(extra_info + 0X04, 24, 4, value)
+#define HIOE_INSTRUCTION_INFO_SET_BYTEMASK_NO_CLR(extra_info, value) \
+ SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 24, 4, value)
+#define HIOE_INSTRUCTION_INFO_GET_RD_EN(extra_info) \
+ GET_C2H_FIELD(extra_info + 0X04, 28, 1)
+#define HIOE_INSTRUCTION_INFO_SET_RD_EN(extra_info, value) \
+ SET_C2H_FIELD_CLR(extra_info + 0X04, 28, 1, value)
+#define HIOE_INSTRUCTION_INFO_SET_RD_EN_NO_CLR(extra_info, value) \
+ SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 28, 1, value)
+#define HIOE_INSTRUCTION_INFO_GET_WR_EN(extra_info) \
+ GET_C2H_FIELD(extra_info + 0X04, 29, 1)
+#define HIOE_INSTRUCTION_INFO_SET_WR_EN(extra_info, value) \
+ SET_C2H_FIELD_CLR(extra_info + 0X04, 29, 1, value)
+#define HIOE_INSTRUCTION_INFO_SET_WR_EN_NO_CLR(extra_info, value) \
+ SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 29, 1, value)
+#define HIOE_INSTRUCTION_INFO_GET_RAW_R(extra_info) \
+ GET_C2H_FIELD(extra_info + 0X04, 30, 1)
+#define HIOE_INSTRUCTION_INFO_SET_RAW_R(extra_info, value) \
+ SET_C2H_FIELD_CLR(extra_info + 0X04, 30, 1, value)
+#define HIOE_INSTRUCTION_INFO_SET_RAW_R_NO_CLR(extra_info, value) \
+ SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 30, 1, value)
+#define HIOE_INSTRUCTION_INFO_GET_RAW(extra_info) \
+ GET_C2H_FIELD(extra_info + 0X04, 31, 1)
+#define HIOE_INSTRUCTION_INFO_SET_RAW(extra_info, value) \
+ SET_C2H_FIELD_CLR(extra_info + 0X04, 31, 1, value)
+#define HIOE_INSTRUCTION_INFO_SET_RAW_NO_CLR(extra_info, value) \
+ SET_C2H_FIELD_NO_CLR(extra_info + 0X04, 31, 1, value)
#endif
diff --git a/hal/halmac/halmac_h2c_extra_info_nic.h b/hal/halmac/halmac_h2c_extra_info_nic.h
index 20bfb5a..d48a683 100644
--- a/hal/halmac/halmac_h2c_extra_info_nic.h
+++ b/hal/halmac/halmac_h2c_extra_info_nic.h
@@ -1,47 +1,171 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
#ifndef _HAL_H2CEXTRAINFO_H2C_C2H_NIC_H_
#define _HAL_H2CEXTRAINFO_H2C_C2H_NIC_H_
-#define PHY_PARAMETER_INFO_GET_LENGTH(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 0, 8)
-#define PHY_PARAMETER_INFO_SET_LENGTH(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 0, 8, __Value)
-#define PHY_PARAMETER_INFO_GET_IO_CMD(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 8, 7)
-#define PHY_PARAMETER_INFO_SET_IO_CMD(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 8, 7, __Value)
-#define PHY_PARAMETER_INFO_GET_MSK_EN(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 15, 1)
-#define PHY_PARAMETER_INFO_SET_MSK_EN(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 15, 1, __Value)
-#define PHY_PARAMETER_INFO_GET_LLT_PG_BNDY(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 16, 8)
-#define PHY_PARAMETER_INFO_SET_LLT_PG_BNDY(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 16, 8, __Value)
-#define PHY_PARAMETER_INFO_GET_EFUSE_RSVDPAGE_LOC(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 16, 8)
-#define PHY_PARAMETER_INFO_SET_EFUSE_RSVDPAGE_LOC(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 16, 8, __Value)
-#define PHY_PARAMETER_INFO_GET_EFUSE_PATCH_EN(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 16, 8)
-#define PHY_PARAMETER_INFO_SET_EFUSE_PATCH_EN(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 16, 8, __Value)
-#define PHY_PARAMETER_INFO_GET_RF_ADDR(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 16, 8)
-#define PHY_PARAMETER_INFO_SET_RF_ADDR(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 16, 8, __Value)
-#define PHY_PARAMETER_INFO_GET_IO_ADDR(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 16, 16)
-#define PHY_PARAMETER_INFO_SET_IO_ADDR(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 16, 16, __Value)
-#define PHY_PARAMETER_INFO_GET_DELAY_VALUE(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 16, 16)
-#define PHY_PARAMETER_INFO_SET_DELAY_VALUE(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 16, 16, __Value)
-#define PHY_PARAMETER_INFO_GET_RF_PATH(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 24, 8)
-#define PHY_PARAMETER_INFO_SET_RF_PATH(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 24, 8, __Value)
-#define PHY_PARAMETER_INFO_GET_DATA(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X04, 0, 32)
-#define PHY_PARAMETER_INFO_SET_DATA(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X04, 0, 32, __Value)
-#define PHY_PARAMETER_INFO_GET_MASK(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X08, 0, 32)
-#define PHY_PARAMETER_INFO_SET_MASK(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X08, 0, 32, __Value)
-#define CHANNEL_INFO_GET_CHANNEL(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 0, 8)
-#define CHANNEL_INFO_SET_CHANNEL(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 0, 8, __Value)
-#define CHANNEL_INFO_GET_PRI_CH_IDX(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 8, 4)
-#define CHANNEL_INFO_SET_PRI_CH_IDX(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 8, 4, __Value)
-#define CHANNEL_INFO_GET_BANDWIDTH(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 12, 4)
-#define CHANNEL_INFO_SET_BANDWIDTH(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 12, 4, __Value)
-#define CHANNEL_INFO_GET_TIMEOUT(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 16, 8)
-#define CHANNEL_INFO_SET_TIMEOUT(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 16, 8, __Value)
-#define CHANNEL_INFO_GET_ACTION_ID(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 24, 7)
-#define CHANNEL_INFO_SET_ACTION_ID(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 24, 7, __Value)
-#define CHANNEL_INFO_GET_CH_EXTRA_INFO(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 31, 1)
-#define CHANNEL_INFO_SET_CH_EXTRA_INFO(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 31, 1, __Value)
-#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO_ID(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 0, 7)
-#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_ID(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 0, 7, __Value)
-#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 7, 1)
-#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 7, 1, __Value)
-#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO_SIZE(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 8, 8)
-#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_SIZE(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 8, 8, __Value)
-#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO_DATA(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 16, 1)
-#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_DATA(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 16, 1, __Value)
+
+/* H2C extra info (rsvd page) usage, unit : page (128byte)*/
+/* dlfw : not include txdesc size*/
+/* update pkt : not include txdesc size*/
+/* cfg param : not include txdesc size*/
+/* scan info : not include txdesc size*/
+/* dl flash : not include txdesc size*/
+#define DLFW_RSVDPG_SIZE 2048
+#define UPDATE_PKT_RSVDPG_SIZE 2048
+#define CFG_PARAM_RSVDPG_SIZE 2048
+#define SCAN_INFO_RSVDPG_SIZE 256
+#define DL_FLASH_RSVDPG_SIZE 2048
+/* su0 snding pkt : include txdesc size */
+#define SU0_SNDING_PKT_OFFSET 0
+#define SU0_SNDING_PKT_RSVDPG_SIZE 128
+
+#define PARAM_INFO_GET_LEN(extra_info) LE_BITS_TO_4BYTE(extra_info + 0X00, 0, 8)
+#define PARAM_INFO_SET_LEN(extra_info, value) \
+ SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 0, 8, value)
+#define PARAM_INFO_GET_IO_CMD(extra_info) \
+ LE_BITS_TO_4BYTE(extra_info + 0X00, 8, 7)
+#define PARAM_INFO_SET_IO_CMD(extra_info, value) \
+ SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 8, 7, value)
+#define PARAM_INFO_GET_MSK_EN(extra_info) \
+ LE_BITS_TO_4BYTE(extra_info + 0X00, 15, 1)
+#define PARAM_INFO_SET_MSK_EN(extra_info, value) \
+ SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 15, 1, value)
+#define PARAM_INFO_GET_LLT_PG_BNDY(extra_info) \
+ LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 8)
+#define PARAM_INFO_SET_LLT_PG_BNDY(extra_info, value) \
+ SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 8, value)
+#define PARAM_INFO_GET_EFUSE_RSVDPAGE_LOC(extra_info) \
+ LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 8)
+#define PARAM_INFO_SET_EFUSE_RSVDPAGE_LOC(extra_info, value) \
+ SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 8, value)
+#define PARAM_INFO_GET_EFUSE_PATCH_EN(extra_info) \
+ LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 8)
+#define PARAM_INFO_SET_EFUSE_PATCH_EN(extra_info, value) \
+ SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 8, value)
+#define PARAM_INFO_GET_RF_ADDR(extra_info) \
+ LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 8)
+#define PARAM_INFO_SET_RF_ADDR(extra_info, value) \
+ SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 8, value)
+#define PARAM_INFO_GET_IO_ADDR(extra_info) \
+ LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 16)
+#define PARAM_INFO_SET_IO_ADDR(extra_info, value) \
+ SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 16, value)
+#define PARAM_INFO_GET_DELAY_VAL(extra_info) \
+ LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 16)
+#define PARAM_INFO_SET_DELAY_VAL(extra_info, value) \
+ SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 16, value)
+#define PARAM_INFO_GET_RF_PATH(extra_info) \
+ LE_BITS_TO_4BYTE(extra_info + 0X00, 24, 8)
+#define PARAM_INFO_SET_RF_PATH(extra_info, value) \
+ SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 24, 8, value)
+#define PARAM_INFO_GET_DATA(extra_info) \
+ LE_BITS_TO_4BYTE(extra_info + 0X04, 0, 32)
+#define PARAM_INFO_SET_DATA(extra_info, value) \
+ SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 0, 32, value)
+#define PARAM_INFO_GET_MASK(extra_info) \
+ LE_BITS_TO_4BYTE(extra_info + 0X08, 0, 32)
+#define PARAM_INFO_SET_MASK(extra_info, value) \
+ SET_BITS_TO_LE_4BYTE(extra_info + 0X08, 0, 32, value)
+#define CH_INFO_GET_CH(extra_info) LE_BITS_TO_4BYTE(extra_info + 0X00, 0, 8)
+#define CH_INFO_SET_CH(extra_info, value) \
+ SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 0, 8, value)
+#define CH_INFO_GET_PRI_CH_IDX(extra_info) \
+ LE_BITS_TO_4BYTE(extra_info + 0X00, 8, 4)
+#define CH_INFO_SET_PRI_CH_IDX(extra_info, value) \
+ SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 8, 4, value)
+#define CH_INFO_GET_BW(extra_info) LE_BITS_TO_4BYTE(extra_info + 0X00, 12, 4)
+#define CH_INFO_SET_BW(extra_info, value) \
+ SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 12, 4, value)
+#define CH_INFO_GET_TIMEOUT(extra_info) \
+ LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 8)
+#define CH_INFO_SET_TIMEOUT(extra_info, value) \
+ SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 8, value)
+#define CH_INFO_GET_ACTION_ID(extra_info) \
+ LE_BITS_TO_4BYTE(extra_info + 0X00, 24, 7)
+#define CH_INFO_SET_ACTION_ID(extra_info, value) \
+ SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 24, 7, value)
+#define CH_INFO_GET_EXTRA_INFO(extra_info) \
+ LE_BITS_TO_4BYTE(extra_info + 0X00, 31, 1)
+#define CH_INFO_SET_EXTRA_INFO(extra_info, value) \
+ SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 31, 1, value)
+#define CH_EXTRA_INFO_GET_ID(extra_info) \
+ LE_BITS_TO_4BYTE(extra_info + 0X00, 0, 7)
+#define CH_EXTRA_INFO_SET_ID(extra_info, value) \
+ SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 0, 7, value)
+#define CH_EXTRA_INFO_GET_INFO(extra_info) \
+ LE_BITS_TO_4BYTE(extra_info + 0X00, 7, 1)
+#define CH_EXTRA_INFO_SET_INFO(extra_info, value) \
+ SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 7, 1, value)
+#define CH_EXTRA_INFO_GET_SIZE(extra_info) \
+ LE_BITS_TO_4BYTE(extra_info + 0X00, 8, 8)
+#define CH_EXTRA_INFO_SET_SIZE(extra_info, value) \
+ SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 8, 8, value)
+#define CH_EXTRA_INFO_GET_DATA(extra_info) \
+ LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 1)
+#define CH_EXTRA_INFO_SET_DATA(extra_info, value) \
+ SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 1, value)
+#define HIOE_INSTRUCTION_INFO_GET_BYTEDATA_L(extra_info) \
+ LE_BITS_TO_4BYTE(extra_info + 0X00, 0, 16)
+#define HIOE_INSTRUCTION_INFO_SET_BYTEDATA_L(extra_info, value) \
+ SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 0, 16, value)
+#define HIOE_INSTRUCTION_INFO_GET_BITDATA(extra_info) \
+ LE_BITS_TO_4BYTE(extra_info + 0X00, 0, 16)
+#define HIOE_INSTRUCTION_INFO_SET_BITDATA(extra_info, value) \
+ SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 0, 16, value)
+#define HIOE_INSTRUCTION_INFO_GET_BYTEDATA_H(extra_info) \
+ LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 16)
+#define HIOE_INSTRUCTION_INFO_SET_BYTEDATA_H(extra_info, value) \
+ SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 16, value)
+#define HIOE_INSTRUCTION_INFO_GET_BITMASK(extra_info) \
+ LE_BITS_TO_4BYTE(extra_info + 0X00, 16, 16)
+#define HIOE_INSTRUCTION_INFO_SET_BITMASK(extra_info, value) \
+ SET_BITS_TO_LE_4BYTE(extra_info + 0X00, 16, 16, value)
+#define HIOE_INSTRUCTION_INFO_GET_REG_ADDR(extra_info) \
+ LE_BITS_TO_4BYTE(extra_info + 0X04, 0, 22)
+#define HIOE_INSTRUCTION_INFO_SET_REG_ADDR(extra_info, value) \
+ SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 0, 22, value)
+#define HIOE_INSTRUCTION_INFO_GET_DELAY_VALUE(extra_info) \
+ LE_BITS_TO_4BYTE(extra_info + 0X04, 0, 22)
+#define HIOE_INSTRUCTION_INFO_SET_DELAY_VALUE(extra_info, value) \
+ SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 0, 22, value)
+#define HIOE_INSTRUCTION_INFO_GET_MODE_SELECT(extra_info) \
+ LE_BITS_TO_4BYTE(extra_info + 0X04, 22, 1)
+#define HIOE_INSTRUCTION_INFO_SET_MODE_SELECT(extra_info, value) \
+ SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 22, 1, value)
+#define HIOE_INSTRUCTION_INFO_GET_IO_DELAY(extra_info) \
+ LE_BITS_TO_4BYTE(extra_info + 0X04, 23, 1)
+#define HIOE_INSTRUCTION_INFO_SET_IO_DELAY(extra_info, value) \
+ SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 23, 1, value)
+#define HIOE_INSTRUCTION_INFO_GET_BYTEMASK(extra_info) \
+ LE_BITS_TO_4BYTE(extra_info + 0X04, 24, 4)
+#define HIOE_INSTRUCTION_INFO_SET_BYTEMASK(extra_info, value) \
+ SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 24, 4, value)
+#define HIOE_INSTRUCTION_INFO_GET_RD_EN(extra_info) \
+ LE_BITS_TO_4BYTE(extra_info + 0X04, 28, 1)
+#define HIOE_INSTRUCTION_INFO_SET_RD_EN(extra_info, value) \
+ SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 28, 1, value)
+#define HIOE_INSTRUCTION_INFO_GET_WR_EN(extra_info) \
+ LE_BITS_TO_4BYTE(extra_info + 0X04, 29, 1)
+#define HIOE_INSTRUCTION_INFO_SET_WR_EN(extra_info, value) \
+ SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 29, 1, value)
+#define HIOE_INSTRUCTION_INFO_GET_RAW_R(extra_info) \
+ LE_BITS_TO_4BYTE(extra_info + 0X04, 30, 1)
+#define HIOE_INSTRUCTION_INFO_SET_RAW_R(extra_info, value) \
+ SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 30, 1, value)
+#define HIOE_INSTRUCTION_INFO_GET_RAW(extra_info) \
+ LE_BITS_TO_4BYTE(extra_info + 0X04, 31, 1)
+#define HIOE_INSTRUCTION_INFO_SET_RAW(extra_info, value) \
+ SET_BITS_TO_LE_4BYTE(extra_info + 0X04, 31, 1, value)
#endif
diff --git a/hal/halmac/halmac_hw_cfg.h b/hal/halmac/halmac_hw_cfg.h
index 60a346a..8d64a83 100644
--- a/hal/halmac/halmac_hw_cfg.h
+++ b/hal/halmac/halmac_hw_cfg.h
@@ -1,35 +1,170 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
#ifndef __HALMAC__HW_CFG_H__
#define __HALMAC__HW_CFG_H__
-#ifndef BIT
- #define BIT(x) (1 << (x))
-#endif
+#include /* CONFIG_[IC] */
+#ifdef CONFIG_RTL8723A
+#define HALMAC_8723A_SUPPORT 1
+#else
#define HALMAC_8723A_SUPPORT 0
+#endif
+
+#ifdef CONFIG_RTL8188E
+#define HALMAC_8188E_SUPPORT 1
+#else
#define HALMAC_8188E_SUPPORT 0
-#define HALMAC_8821A_SUPPORT 0
-#define HALMAC_8723B_SUPPORT 0
-#define HALMAC_8812A_SUPPORT 0
-#define HALMAC_8192E_SUPPORT 0
-#define HALMAC_8881A_SUPPORT 0
-#define HALMAC_8821B_SUPPORT 0
-#define HALMAC_8814A_SUPPORT 0
-#define HALMAC_8814B_SUPPORT 0
-#define HALMAC_8881A_SUPPORT 0
-#define HALMAC_8703B_SUPPORT 0
-#define HALMAC_8723D_SUPPORT 0
-#define HALMAC_8188F_SUPPORT 0
-#define HALMAC_8821BMP_SUPPORT 0
-#define HALMAC_8814AMP_SUPPORT 0
-#define HALMAC_8195A_SUPPORT 0
+#endif
+
+#ifdef CONFIG_RTL8821A
+#define HALMAC_8821A_SUPPORT 1
+#else
+#define HALMAC_8821A_SUPPORT 0
+#endif
+
+#ifdef CONFIG_RTL8723B
+#define HALMAC_8723B_SUPPORT 1
+#else
+#define HALMAC_8723B_SUPPORT 0
+#endif
+
+#ifdef CONFIG_RTL8812A
+#define HALMAC_8812A_SUPPORT 1
+#else
+#define HALMAC_8812A_SUPPORT 0
+#endif
+
+#ifdef CONFIG_RTL8192E
+#define HALMAC_8192E_SUPPORT 1
+#else
+#define HALMAC_8192E_SUPPORT 0
+#endif
+
+#ifdef CONFIG_RTL8881A
+#define HALMAC_8881A_SUPPORT 1
+#else
+#define HALMAC_8881A_SUPPORT 0
+#endif
+
+#ifdef CONFIG_RTL8821B
+#define HALMAC_8821B_SUPPORT 1
+#else
#define HALMAC_8821B_SUPPORT 0
-#define HALMAC_8196F_SUPPORT 0
-#define HALMAC_8197F_SUPPORT 0
+#endif
+
+#ifdef CONFIG_RTL8814A
+#define HALMAC_8814A_SUPPORT 1
+#else
+#define HALMAC_8814A_SUPPORT 0
+#endif
+
+#ifdef CONFIG_RTL8881A
+#define HALMAC_8881A_SUPPORT 1
+#else
+#define HALMAC_8881A_SUPPORT 0
+#endif
+
+#ifdef CONFIG_RTL8703B
+#define HALMAC_8703B_SUPPORT 1
+#else
+#define HALMAC_8703B_SUPPORT 0
+#endif
+
+#ifdef CONFIG_RTL8723D
+#define HALMAC_8723D_SUPPORT 1
+#else
+#define HALMAC_8723D_SUPPORT 0
+#endif
+#ifdef CONFIG_RTL8188F
+#define HALMAC_8188F_SUPPORT 1
+#else
+#define HALMAC_8188F_SUPPORT 0
+#endif
+
+#ifdef CONFIG_RTL8821BMP
+#define HALMAC_8821BMP_SUPPORT 1
+#else
+#define HALMAC_8821BMP_SUPPORT 0
+#endif
+
+#ifdef CONFIG_RTL8814AMP
+#define HALMAC_8814AMP_SUPPORT 1
+#else
+#define HALMAC_8814AMP_SUPPORT 0
+#endif
+
+#ifdef CONFIG_RTL8195A
+#define HALMAC_8195A_SUPPORT 1
+#else
+#define HALMAC_8195A_SUPPORT 0
+#endif
+
+#ifdef CONFIG_RTL8821B
+#define HALMAC_8821B_SUPPORT 1
+#else
+#define HALMAC_8821B_SUPPORT 0
+#endif
+
+#ifdef CONFIG_RTL8196F
+#define HALMAC_8196F_SUPPORT 1
+#else
+#define HALMAC_8196F_SUPPORT 0
+#endif
+
+#ifdef CONFIG_RTL8197F
+#define HALMAC_8197F_SUPPORT 1
+#else
+#define HALMAC_8197F_SUPPORT 0
+#endif
+
+#ifdef CONFIG_RTL8198F
+#define HALMAC_8198F_SUPPORT 1
+#else
+#define HALMAC_8198F_SUPPORT 0
+#endif
+
+
+/* Halmac support IC version */
+
+#ifdef CONFIG_RTL8814B
+#define HALMAC_8814B_SUPPORT 1
+#else
+#define HALMAC_8814B_SUPPORT 0
+#endif
+
+#ifdef CONFIG_RTL8821C
+#define HALMAC_8821C_SUPPORT 1
+#else
#define HALMAC_8821C_SUPPORT 0
+#endif
+
+#ifdef CONFIG_RTL8822B
#define HALMAC_8822B_SUPPORT 1
+#else
+#define HALMAC_8822B_SUPPORT 0
+#endif
+#ifdef CONFIG_RTL8822C
+#define HALMAC_8822C_SUPPORT 1
+#else
+#define HALMAC_8822C_SUPPORT 0
#endif
+#endif /* __HALMAC__HW_CFG_H__ */
diff --git a/hal/halmac/halmac_intf_phy_cmd.h b/hal/halmac/halmac_intf_phy_cmd.h
new file mode 100644
index 0000000..f44bfa1
--- /dev/null
+++ b/hal/halmac/halmac_intf_phy_cmd.h
@@ -0,0 +1,45 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef HALMAC_INTF_PHY_CMD
+#define HALMAC_INTF_PHY_CMD
+
+/* Cut mask */
+enum halmac_intf_phy_cut {
+ HALMAC_INTF_PHY_CUT_TESTCHIP = BIT(0),
+ HALMAC_INTF_PHY_CUT_A = BIT(1),
+ HALMAC_INTF_PHY_CUT_B = BIT(2),
+ HALMAC_INTF_PHY_CUT_C = BIT(3),
+ HALMAC_INTF_PHY_CUT_D = BIT(4),
+ HALMAC_INTF_PHY_CUT_E = BIT(5),
+ HALMAC_INTF_PHY_CUT_F = BIT(6),
+ HALMAC_INTF_PHY_CUT_G = BIT(7),
+ HALMAC_INTF_PHY_CUT_ALL = 0x7FFF,
+};
+
+/* IP selection */
+enum halmac_ip_sel {
+ HALMAC_IP_INTF_PHY = 0,
+ HALMAC_IP_SEL_MAC = 1,
+ HALMAC_IP_PCIE_DBI = 2,
+ HALMAC_IP_SEL_UNDEFINE = 0x7FFF,
+};
+
+/* Platform mask */
+enum halmac_intf_phy_platform {
+ HALMAC_INTF_PHY_PLATFORM_ALL = 0x7FFF,
+};
+
+#endif
diff --git a/hal/halmac/halmac_original_c2h_ap.h b/hal/halmac/halmac_original_c2h_ap.h
index 433da10..bb4bda1 100644
--- a/hal/halmac/halmac_original_c2h_ap.h
+++ b/hal/halmac/halmac_original_c2h_ap.h
@@ -1,336 +1,612 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
#ifndef _HAL_ORIGINALC2HFORMAT_H2C_C2H_AP_H_
#define _HAL_ORIGINALC2HFORMAT_H2C_C2H_AP_H_
-#define CMD_ID_C2H 0X00
-#define CMD_ID_DBG 0X00
-#define CMD_ID_C2H_LB 0X01
-#define CMD_ID_C2H_SND_TXBF 0X02
-#define CMD_ID_C2H_CCX_RPT 0X03
-#define CMD_ID_C2H_AP_REQ_TXRPT 0X04
-#define CMD_ID_C2H_INITIAL_RATE_COLLECTION 0X05
-#define CMD_ID_C2H_RA_RPT 0X0C
-#define CMD_ID_C2H_SPECIAL_STATISTICS 0X0D
-#define CMD_ID_C2H_RA_PARA_RPT 0X0E
-#define CMD_ID_C2H_CUR_CHANNEL 0X10
-#define CMD_ID_C2H_GPIO_WAKEUP 0X14
-#define C2H_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8)
-#define C2H_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value)
-#define C2H_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value)
-#define C2H_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8)
-#define C2H_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value)
-#define C2H_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value)
-#define DBG_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8)
-#define DBG_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value)
-#define DBG_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value)
-#define DBG_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8)
-#define DBG_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value)
-#define DBG_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value)
-#define DBG_GET_DBG_STR1(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 8)
-#define DBG_SET_DBG_STR1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 8, __Value)
-#define DBG_SET_DBG_STR1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 8, __Value)
-#define DBG_GET_DBG_STR2(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 24, 8)
-#define DBG_SET_DBG_STR2(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 24, 8, __Value)
-#define DBG_SET_DBG_STR2_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 24, 8, __Value)
-#define DBG_GET_DBG_STR3(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 8)
-#define DBG_SET_DBG_STR3(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 8, __Value)
-#define DBG_SET_DBG_STR3_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 8, __Value)
-#define DBG_GET_DBG_STR4(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8)
-#define DBG_SET_DBG_STR4(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value)
-#define DBG_SET_DBG_STR4_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value)
-#define DBG_GET_DBG_STR5(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 8)
-#define DBG_SET_DBG_STR5(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 8, __Value)
-#define DBG_SET_DBG_STR5_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 8, __Value)
-#define DBG_GET_DBG_STR6(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 24, 8)
-#define DBG_SET_DBG_STR6(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 24, 8, __Value)
-#define DBG_SET_DBG_STR6_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 24, 8, __Value)
-#define DBG_GET_DBG_STR7(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 0, 8)
-#define DBG_SET_DBG_STR7(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 0, 8, __Value)
-#define DBG_SET_DBG_STR7_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 0, 8, __Value)
-#define DBG_GET_DBG_STR8(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 8, 8)
-#define DBG_SET_DBG_STR8(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 8, 8, __Value)
-#define DBG_SET_DBG_STR8_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 8, 8, __Value)
-#define DBG_GET_DBG_STR9(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 16, 8)
-#define DBG_SET_DBG_STR9(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 16, 8, __Value)
-#define DBG_SET_DBG_STR9_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 16, 8, __Value)
-#define DBG_GET_DBG_STR10(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 24, 8)
-#define DBG_SET_DBG_STR10(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 24, 8, __Value)
-#define DBG_SET_DBG_STR10_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 24, 8, __Value)
-#define DBG_GET_DBG_STR11(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 0, 8)
-#define DBG_SET_DBG_STR11(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 0, 8, __Value)
-#define DBG_SET_DBG_STR11_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 0, 8, __Value)
-#define DBG_GET_DBG_STR12(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 8, 8)
-#define DBG_SET_DBG_STR12(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 8, 8, __Value)
-#define DBG_SET_DBG_STR12_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 8, 8, __Value)
-#define DBG_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8)
-#define DBG_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value)
-#define DBG_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value)
-#define DBG_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8)
-#define DBG_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value)
-#define DBG_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value)
-#define C2H_LB_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8)
-#define C2H_LB_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value)
-#define C2H_LB_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value)
-#define C2H_LB_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8)
-#define C2H_LB_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value)
-#define C2H_LB_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value)
-#define C2H_LB_GET_PAYLOAD1(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 16)
-#define C2H_LB_SET_PAYLOAD1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 16, __Value)
-#define C2H_LB_SET_PAYLOAD1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 16, __Value)
-#define C2H_LB_GET_PAYLOAD2(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 32)
-#define C2H_LB_SET_PAYLOAD2(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 32, __Value)
-#define C2H_LB_SET_PAYLOAD2_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 32, __Value)
-#define C2H_LB_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8)
-#define C2H_LB_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value)
-#define C2H_LB_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value)
-#define C2H_LB_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8)
-#define C2H_LB_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value)
-#define C2H_LB_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value)
-#define C2H_SND_TXBF_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8)
-#define C2H_SND_TXBF_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value)
-#define C2H_SND_TXBF_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value)
-#define C2H_SND_TXBF_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8)
-#define C2H_SND_TXBF_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value)
-#define C2H_SND_TXBF_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value)
-#define C2H_SND_TXBF_GET_SND_RESULT(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 1)
-#define C2H_SND_TXBF_SET_SND_RESULT(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 1, __Value)
-#define C2H_SND_TXBF_SET_SND_RESULT_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 1, __Value)
-#define C2H_SND_TXBF_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8)
-#define C2H_SND_TXBF_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value)
-#define C2H_SND_TXBF_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value)
-#define C2H_SND_TXBF_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8)
-#define C2H_SND_TXBF_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value)
-#define C2H_SND_TXBF_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value)
-#define C2H_CCX_RPT_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8)
-#define C2H_CCX_RPT_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value)
-#define C2H_CCX_RPT_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value)
-#define C2H_CCX_RPT_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8)
-#define C2H_CCX_RPT_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value)
-#define C2H_CCX_RPT_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value)
-#define C2H_CCX_RPT_GET_QSEL(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 5)
-#define C2H_CCX_RPT_SET_QSEL(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 5, __Value)
-#define C2H_CCX_RPT_SET_QSEL_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 5, __Value)
-#define C2H_CCX_RPT_GET_BMC(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 21, 1)
-#define C2H_CCX_RPT_SET_BMC(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 21, 1, __Value)
-#define C2H_CCX_RPT_SET_BMC_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 21, 1, __Value)
-#define C2H_CCX_RPT_GET_LIFE_TIME_OVER(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 22, 1)
-#define C2H_CCX_RPT_SET_LIFE_TIME_OVER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 22, 1, __Value)
-#define C2H_CCX_RPT_SET_LIFE_TIME_OVER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 22, 1, __Value)
-#define C2H_CCX_RPT_GET_RETRY_OVER(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 23, 1)
-#define C2H_CCX_RPT_SET_RETRY_OVER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 23, 1, __Value)
-#define C2H_CCX_RPT_SET_RETRY_OVER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 23, 1, __Value)
-#define C2H_CCX_RPT_GET_MACID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 24, 8)
-#define C2H_CCX_RPT_SET_MACID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 24, 8, __Value)
-#define C2H_CCX_RPT_SET_MACID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 24, 8, __Value)
-#define C2H_CCX_RPT_GET_DATA_RETRY_CNT(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 6)
-#define C2H_CCX_RPT_SET_DATA_RETRY_CNT(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 6, __Value)
-#define C2H_CCX_RPT_SET_DATA_RETRY_CNT_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 6, __Value)
-#define C2H_CCX_RPT_GET_QUEUE7_0(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8)
-#define C2H_CCX_RPT_SET_QUEUE7_0(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value)
-#define C2H_CCX_RPT_SET_QUEUE7_0_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value)
-#define C2H_CCX_RPT_GET_QUEUE15_8(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 8)
-#define C2H_CCX_RPT_SET_QUEUE15_8(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 8, __Value)
-#define C2H_CCX_RPT_SET_QUEUE15_8_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 8, __Value)
-#define C2H_CCX_RPT_GET_FINAL_DATA_RATE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 24, 8)
-#define C2H_CCX_RPT_SET_FINAL_DATA_RATE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 24, 8, __Value)
-#define C2H_CCX_RPT_SET_FINAL_DATA_RATE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 24, 8, __Value)
-#define C2H_CCX_RPT_GET_SW_DEFINE_0(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 0, 8)
-#define C2H_CCX_RPT_SET_SW_DEFINE_0(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 0, 8, __Value)
-#define C2H_CCX_RPT_SET_SW_DEFINE_0_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 0, 8, __Value)
-#define C2H_CCX_RPT_GET_SW_DEFINE_1(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 8, 4)
-#define C2H_CCX_RPT_SET_SW_DEFINE_1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 8, 4, __Value)
-#define C2H_CCX_RPT_SET_SW_DEFINE_1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 8, 4, __Value)
-#define C2H_CCX_RPT_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8)
-#define C2H_CCX_RPT_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value)
-#define C2H_CCX_RPT_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value)
-#define C2H_CCX_RPT_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8)
-#define C2H_CCX_RPT_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value)
-#define C2H_CCX_RPT_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value)
-#define C2H_AP_REQ_TXRPT_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8)
-#define C2H_AP_REQ_TXRPT_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value)
-#define C2H_AP_REQ_TXRPT_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value)
-#define C2H_AP_REQ_TXRPT_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8)
-#define C2H_AP_REQ_TXRPT_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value)
-#define C2H_AP_REQ_TXRPT_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value)
-#define C2H_AP_REQ_TXRPT_GET_STA1_MACID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 8)
-#define C2H_AP_REQ_TXRPT_SET_STA1_MACID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 8, __Value)
-#define C2H_AP_REQ_TXRPT_SET_STA1_MACID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 8, __Value)
-#define C2H_AP_REQ_TXRPT_GET_TX_OK1_0(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 24, 8)
-#define C2H_AP_REQ_TXRPT_SET_TX_OK1_0(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 24, 8, __Value)
-#define C2H_AP_REQ_TXRPT_SET_TX_OK1_0_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 24, 8, __Value)
-#define C2H_AP_REQ_TXRPT_GET_TX_OK1_1(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 8)
-#define C2H_AP_REQ_TXRPT_SET_TX_OK1_1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 8, __Value)
-#define C2H_AP_REQ_TXRPT_SET_TX_OK1_1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 8, __Value)
-#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_0(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8)
-#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_0(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value)
-#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_0_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value)
-#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_1(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 8)
-#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 8, __Value)
-#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 8, __Value)
-#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE1(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 24, 8)
-#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 24, 8, __Value)
-#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 24, 8, __Value)
-#define C2H_AP_REQ_TXRPT_GET_STA2_MACID(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 0, 8)
-#define C2H_AP_REQ_TXRPT_SET_STA2_MACID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 0, 8, __Value)
-#define C2H_AP_REQ_TXRPT_SET_STA2_MACID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 0, 8, __Value)
-#define C2H_AP_REQ_TXRPT_GET_TX_OK2_0(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 8, 8)
-#define C2H_AP_REQ_TXRPT_SET_TX_OK2_0(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 8, 8, __Value)
-#define C2H_AP_REQ_TXRPT_SET_TX_OK2_0_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 8, 8, __Value)
-#define C2H_AP_REQ_TXRPT_GET_TX_OK2_1(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 16, 8)
-#define C2H_AP_REQ_TXRPT_SET_TX_OK2_1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 16, 8, __Value)
-#define C2H_AP_REQ_TXRPT_SET_TX_OK2_1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 16, 8, __Value)
-#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_0(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 24, 8)
-#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_0(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 24, 8, __Value)
-#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_0_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 24, 8, __Value)
-#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_1(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 0, 8)
-#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 0, 8, __Value)
-#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 0, 8, __Value)
-#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE2(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 8, 8)
-#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE2(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 8, 8, __Value)
-#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE2_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 8, 8, __Value)
-#define C2H_AP_REQ_TXRPT_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8)
-#define C2H_AP_REQ_TXRPT_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value)
-#define C2H_AP_REQ_TXRPT_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value)
-#define C2H_AP_REQ_TXRPT_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8)
-#define C2H_AP_REQ_TXRPT_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value)
-#define C2H_AP_REQ_TXRPT_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value)
-#define C2H_INITIAL_RATE_COLLECTION_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8)
-#define C2H_INITIAL_RATE_COLLECTION_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value)
-#define C2H_INITIAL_RATE_COLLECTION_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value)
-#define C2H_INITIAL_RATE_COLLECTION_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8)
-#define C2H_INITIAL_RATE_COLLECTION_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value)
-#define C2H_INITIAL_RATE_COLLECTION_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value)
-#define C2H_INITIAL_RATE_COLLECTION_GET_TRYING_BITMAP(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 7)
-#define C2H_INITIAL_RATE_COLLECTION_SET_TRYING_BITMAP(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 7, __Value)
-#define C2H_INITIAL_RATE_COLLECTION_SET_TRYING_BITMAP_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 7, __Value)
-#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE1(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 24, 8)
-#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 24, 8, __Value)
-#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 24, 8, __Value)
-#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE2(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 8)
-#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE2(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 8, __Value)
-#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE2_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 8, __Value)
-#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE3(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8)
-#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE3(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value)
-#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE3_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value)
-#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE4(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 8)
-#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE4(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 8, __Value)
-#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE4_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 8, __Value)
-#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE5(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 24, 8)
-#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE5(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 24, 8, __Value)
-#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE5_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 24, 8, __Value)
-#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE6(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 0, 8)
-#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE6(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 0, 8, __Value)
-#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE6_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 0, 8, __Value)
-#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE7(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 8, 8)
-#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE7(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 8, 8, __Value)
-#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE7_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 8, 8, __Value)
-#define C2H_INITIAL_RATE_COLLECTION_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8)
-#define C2H_INITIAL_RATE_COLLECTION_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value)
-#define C2H_INITIAL_RATE_COLLECTION_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value)
-#define C2H_INITIAL_RATE_COLLECTION_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8)
-#define C2H_INITIAL_RATE_COLLECTION_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value)
-#define C2H_INITIAL_RATE_COLLECTION_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value)
-#define C2H_RA_RPT_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8)
-#define C2H_RA_RPT_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value)
-#define C2H_RA_RPT_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value)
-#define C2H_RA_RPT_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8)
-#define C2H_RA_RPT_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value)
-#define C2H_RA_RPT_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value)
-#define C2H_RA_RPT_GET_RATE(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 8)
-#define C2H_RA_RPT_SET_RATE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 8, __Value)
-#define C2H_RA_RPT_SET_RATE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 8, __Value)
-#define C2H_RA_RPT_GET_MACID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 24, 8)
-#define C2H_RA_RPT_SET_MACID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 24, 8, __Value)
-#define C2H_RA_RPT_SET_MACID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 24, 8, __Value)
-#define C2H_RA_RPT_GET_USE_LDPC(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 1)
-#define C2H_RA_RPT_SET_USE_LDPC(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 1, __Value)
-#define C2H_RA_RPT_SET_USE_LDPC_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 1, __Value)
-#define C2H_RA_RPT_GET_USE_TXBF(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 1, 1)
-#define C2H_RA_RPT_SET_USE_TXBF(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 1, 1, __Value)
-#define C2H_RA_RPT_SET_USE_TXBF_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 1, 1, __Value)
-#define C2H_RA_RPT_GET_COLLISION_STATE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8)
-#define C2H_RA_RPT_SET_COLLISION_STATE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value)
-#define C2H_RA_RPT_SET_COLLISION_STATE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value)
-#define C2H_RA_RPT_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8)
-#define C2H_RA_RPT_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value)
-#define C2H_RA_RPT_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value)
-#define C2H_RA_RPT_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8)
-#define C2H_RA_RPT_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value)
-#define C2H_RA_RPT_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value)
-#define C2H_SPECIAL_STATISTICS_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8)
-#define C2H_SPECIAL_STATISTICS_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value)
-#define C2H_SPECIAL_STATISTICS_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value)
-#define C2H_SPECIAL_STATISTICS_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8)
-#define C2H_SPECIAL_STATISTICS_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value)
-#define C2H_SPECIAL_STATISTICS_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value)
-#define C2H_SPECIAL_STATISTICS_GET_STATISTICS_IDX(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 8)
-#define C2H_SPECIAL_STATISTICS_SET_STATISTICS_IDX(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 8, __Value)
-#define C2H_SPECIAL_STATISTICS_SET_STATISTICS_IDX_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 8, __Value)
-#define C2H_SPECIAL_STATISTICS_GET_DATA0(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 24, 8)
-#define C2H_SPECIAL_STATISTICS_SET_DATA0(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 24, 8, __Value)
-#define C2H_SPECIAL_STATISTICS_SET_DATA0_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 24, 8, __Value)
-#define C2H_SPECIAL_STATISTICS_GET_DATA1(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 8)
-#define C2H_SPECIAL_STATISTICS_SET_DATA1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 8, __Value)
-#define C2H_SPECIAL_STATISTICS_SET_DATA1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 8, __Value)
-#define C2H_SPECIAL_STATISTICS_GET_DATA2(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8)
-#define C2H_SPECIAL_STATISTICS_SET_DATA2(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value)
-#define C2H_SPECIAL_STATISTICS_SET_DATA2_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value)
-#define C2H_SPECIAL_STATISTICS_GET_DATA3(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 8)
-#define C2H_SPECIAL_STATISTICS_SET_DATA3(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 8, __Value)
-#define C2H_SPECIAL_STATISTICS_SET_DATA3_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 8, __Value)
-#define C2H_SPECIAL_STATISTICS_GET_DATA4(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 24, 8)
-#define C2H_SPECIAL_STATISTICS_SET_DATA4(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 24, 8, __Value)
-#define C2H_SPECIAL_STATISTICS_SET_DATA4_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 24, 8, __Value)
-#define C2H_SPECIAL_STATISTICS_GET_DATA5(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 0, 8)
-#define C2H_SPECIAL_STATISTICS_SET_DATA5(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 0, 8, __Value)
-#define C2H_SPECIAL_STATISTICS_SET_DATA5_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 0, 8, __Value)
-#define C2H_SPECIAL_STATISTICS_GET_DATA6(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 8, 8)
-#define C2H_SPECIAL_STATISTICS_SET_DATA6(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 8, 8, __Value)
-#define C2H_SPECIAL_STATISTICS_SET_DATA6_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 8, 8, __Value)
-#define C2H_SPECIAL_STATISTICS_GET_DATA7(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 16, 8)
-#define C2H_SPECIAL_STATISTICS_SET_DATA7(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 16, 8, __Value)
-#define C2H_SPECIAL_STATISTICS_SET_DATA7_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 16, 8, __Value)
-#define C2H_SPECIAL_STATISTICS_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8)
-#define C2H_SPECIAL_STATISTICS_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value)
-#define C2H_SPECIAL_STATISTICS_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value)
-#define C2H_SPECIAL_STATISTICS_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8)
-#define C2H_SPECIAL_STATISTICS_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value)
-#define C2H_SPECIAL_STATISTICS_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value)
-#define C2H_RA_PARA_RPT_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8)
-#define C2H_RA_PARA_RPT_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value)
-#define C2H_RA_PARA_RPT_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value)
-#define C2H_RA_PARA_RPT_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8)
-#define C2H_RA_PARA_RPT_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value)
-#define C2H_RA_PARA_RPT_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value)
-#define C2H_RA_PARA_RPT_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8)
-#define C2H_RA_PARA_RPT_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value)
-#define C2H_RA_PARA_RPT_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value)
-#define C2H_RA_PARA_RPT_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8)
-#define C2H_RA_PARA_RPT_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value)
-#define C2H_RA_PARA_RPT_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value)
-#define C2H_CUR_CHANNEL_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8)
-#define C2H_CUR_CHANNEL_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value)
-#define C2H_CUR_CHANNEL_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value)
-#define C2H_CUR_CHANNEL_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8)
-#define C2H_CUR_CHANNEL_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value)
-#define C2H_CUR_CHANNEL_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value)
-#define C2H_CUR_CHANNEL_GET_CHANNEL_NUM(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 8)
-#define C2H_CUR_CHANNEL_SET_CHANNEL_NUM(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 8, __Value)
-#define C2H_CUR_CHANNEL_SET_CHANNEL_NUM_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 8, __Value)
-#define C2H_CUR_CHANNEL_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8)
-#define C2H_CUR_CHANNEL_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value)
-#define C2H_CUR_CHANNEL_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value)
-#define C2H_CUR_CHANNEL_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8)
-#define C2H_CUR_CHANNEL_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value)
-#define C2H_CUR_CHANNEL_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value)
-#define C2H_GPIO_WAKEUP_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8)
-#define C2H_GPIO_WAKEUP_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value)
-#define C2H_GPIO_WAKEUP_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value)
-#define C2H_GPIO_WAKEUP_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8)
-#define C2H_GPIO_WAKEUP_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value)
-#define C2H_GPIO_WAKEUP_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value)
-#define C2H_GPIO_WAKEUP_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8)
-#define C2H_GPIO_WAKEUP_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value)
-#define C2H_GPIO_WAKEUP_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value)
-#define C2H_GPIO_WAKEUP_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8)
-#define C2H_GPIO_WAKEUP_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value)
-#define C2H_GPIO_WAKEUP_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value)
+#define CMD_ID_C2H 0X00
+#define CMD_ID_DBG 0X00
+#define CMD_ID_C2H_LB 0X01
+#define CMD_ID_C2H_SND_TXBF 0X02
+#define CMD_ID_C2H_CCX_RPT 0X03
+#define CMD_ID_C2H_AP_REQ_TXRPT 0X04
+#define CMD_ID_C2H_INITIAL_RATE_COLLECTION 0X05
+#define CMD_ID_C2H_RA_RPT 0X0C
+#define CMD_ID_C2H_SPECIAL_STATISTICS 0X0D
+#define CMD_ID_C2H_RA_PARA_RPT 0X0E
+#define CMD_ID_C2H_CUR_CHANNEL 0X10
+#define CMD_ID_C2H_GPIO_WAKEUP 0X14
+#define C2H_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define C2H_SET_CMD_ID(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_SET_CMD_ID_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define C2H_SET_SEQ(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_SET_SEQ_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define DBG_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define DBG_SET_CMD_ID(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define DBG_SET_CMD_ID_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define DBG_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define DBG_SET_SEQ(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define DBG_SET_SEQ_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define DBG_GET_DBG_STR1(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8)
+#define DBG_SET_DBG_STR1(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define DBG_SET_DBG_STR1_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define DBG_GET_DBG_STR2(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8)
+#define DBG_SET_DBG_STR2(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define DBG_SET_DBG_STR2_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define DBG_GET_DBG_STR3(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
+#define DBG_SET_DBG_STR3(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define DBG_SET_DBG_STR3_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define DBG_GET_DBG_STR4(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
+#define DBG_SET_DBG_STR4(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define DBG_SET_DBG_STR4_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define DBG_GET_DBG_STR5(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8)
+#define DBG_SET_DBG_STR5(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define DBG_SET_DBG_STR5_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define DBG_GET_DBG_STR6(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 24, 8)
+#define DBG_SET_DBG_STR6(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define DBG_SET_DBG_STR6_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define DBG_GET_DBG_STR7(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 0, 8)
+#define DBG_SET_DBG_STR7(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 8, value)
+#define DBG_SET_DBG_STR7_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 8, value)
+#define DBG_GET_DBG_STR8(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 8, 8)
+#define DBG_SET_DBG_STR8(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 8, 8, value)
+#define DBG_SET_DBG_STR8_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 8, 8, value)
+#define DBG_GET_DBG_STR9(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 16, 8)
+#define DBG_SET_DBG_STR9(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 16, 8, value)
+#define DBG_SET_DBG_STR9_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 16, 8, value)
+#define DBG_GET_DBG_STR10(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 24, 8)
+#define DBG_SET_DBG_STR10(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 24, 8, value)
+#define DBG_SET_DBG_STR10_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 24, 8, value)
+#define DBG_GET_DBG_STR11(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 0, 8)
+#define DBG_SET_DBG_STR11(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 0, 8, value)
+#define DBG_SET_DBG_STR11_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 0, 8, value)
+#define DBG_GET_DBG_STR12(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 8, 8)
+#define DBG_SET_DBG_STR12(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 8, 8, value)
+#define DBG_SET_DBG_STR12_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 8, 8, value)
+#define DBG_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
+#define DBG_SET_LEN(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define DBG_SET_LEN_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define DBG_GET_TRIGGER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
+#define DBG_SET_TRIGGER(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define DBG_SET_TRIGGER_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_LB_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define C2H_LB_SET_CMD_ID(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_LB_SET_CMD_ID_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_LB_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define C2H_LB_SET_SEQ(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_LB_SET_SEQ_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_LB_GET_PAYLOAD1(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 16, 16)
+#define C2H_LB_SET_PAYLOAD1(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 16, value)
+#define C2H_LB_SET_PAYLOAD1_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 16, value)
+#define C2H_LB_GET_PAYLOAD2(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 32)
+#define C2H_LB_SET_PAYLOAD2(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 32, value)
+#define C2H_LB_SET_PAYLOAD2_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 32, value)
+#define C2H_LB_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
+#define C2H_LB_SET_LEN(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_LB_SET_LEN_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_LB_GET_TRIGGER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
+#define C2H_LB_SET_TRIGGER(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_LB_SET_TRIGGER_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_SND_TXBF_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define C2H_SND_TXBF_SET_CMD_ID(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_SND_TXBF_SET_CMD_ID_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_SND_TXBF_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define C2H_SND_TXBF_SET_SEQ(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_SND_TXBF_SET_SEQ_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_SND_TXBF_GET_SND_RESULT(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X00, 16, 1)
+#define C2H_SND_TXBF_SET_SND_RESULT(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 1, value)
+#define C2H_SND_TXBF_SET_SND_RESULT_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 1, value)
+#define C2H_SND_TXBF_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
+#define C2H_SND_TXBF_SET_LEN(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_SND_TXBF_SET_LEN_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_SND_TXBF_GET_TRIGGER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
+#define C2H_SND_TXBF_SET_TRIGGER(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_SND_TXBF_SET_TRIGGER_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_CCX_RPT_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define C2H_CCX_RPT_SET_CMD_ID(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_CCX_RPT_SET_CMD_ID_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_CCX_RPT_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define C2H_CCX_RPT_SET_SEQ(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_CCX_RPT_SET_SEQ_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_CCX_RPT_GET_QSEL(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 16, 5)
+#define C2H_CCX_RPT_SET_QSEL(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 5, value)
+#define C2H_CCX_RPT_SET_QSEL_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 5, value)
+#define C2H_CCX_RPT_GET_BMC(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 21, 1)
+#define C2H_CCX_RPT_SET_BMC(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 21, 1, value)
+#define C2H_CCX_RPT_SET_BMC_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 21, 1, value)
+#define C2H_CCX_RPT_GET_LIFE_TIME_OVER(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X00, 22, 1)
+#define C2H_CCX_RPT_SET_LIFE_TIME_OVER(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 22, 1, value)
+#define C2H_CCX_RPT_SET_LIFE_TIME_OVER_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 22, 1, value)
+#define C2H_CCX_RPT_GET_RETRY_OVER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 23, 1)
+#define C2H_CCX_RPT_SET_RETRY_OVER(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 23, 1, value)
+#define C2H_CCX_RPT_SET_RETRY_OVER_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 23, 1, value)
+#define C2H_CCX_RPT_GET_MACID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8)
+#define C2H_CCX_RPT_SET_MACID(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_CCX_RPT_SET_MACID_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_CCX_RPT_GET_DATA_RETRY_CNT(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X04, 0, 6)
+#define C2H_CCX_RPT_SET_DATA_RETRY_CNT(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 6, value)
+#define C2H_CCX_RPT_SET_DATA_RETRY_CNT_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 6, value)
+#define C2H_CCX_RPT_GET_QUEUE7_0(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
+#define C2H_CCX_RPT_SET_QUEUE7_0(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_CCX_RPT_SET_QUEUE7_0_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_CCX_RPT_GET_QUEUE15_8(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8)
+#define C2H_CCX_RPT_SET_QUEUE15_8(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define C2H_CCX_RPT_SET_QUEUE15_8_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define C2H_CCX_RPT_GET_FINAL_DATA_RATE(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X04, 24, 8)
+#define C2H_CCX_RPT_SET_FINAL_DATA_RATE(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define C2H_CCX_RPT_SET_FINAL_DATA_RATE_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define C2H_CCX_RPT_GET_SW_DEFINE_0(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 0, 8)
+#define C2H_CCX_RPT_SET_SW_DEFINE_0(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 8, value)
+#define C2H_CCX_RPT_SET_SW_DEFINE_0_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 8, value)
+#define C2H_CCX_RPT_GET_SW_DEFINE_1(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X08, 8, 4)
+#define C2H_CCX_RPT_SET_SW_DEFINE_1(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 8, 4, value)
+#define C2H_CCX_RPT_SET_SW_DEFINE_1_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 8, 4, value)
+#define C2H_CCX_RPT_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
+#define C2H_CCX_RPT_SET_LEN(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_CCX_RPT_SET_LEN_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_CCX_RPT_GET_TRIGGER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
+#define C2H_CCX_RPT_SET_TRIGGER(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_CCX_RPT_SET_TRIGGER_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define C2H_AP_REQ_TXRPT_SET_CMD_ID(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_CMD_ID_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define C2H_AP_REQ_TXRPT_SET_SEQ(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_SEQ_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_STA1_MACID(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8)
+#define C2H_AP_REQ_TXRPT_SET_STA1_MACID(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_STA1_MACID_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_OK1_0(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_OK1_0(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_TX_OK1_0_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_OK1_1(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_OK1_1(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_TX_OK1_1_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_0(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_0(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_0_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_1(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_1(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_1_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE1(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X04, 24, 8)
+#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE1(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE1_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_STA2_MACID(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X08, 0, 8)
+#define C2H_AP_REQ_TXRPT_SET_STA2_MACID(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_STA2_MACID_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_OK2_0(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X08, 8, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_OK2_0(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 8, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_TX_OK2_0_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 8, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_OK2_1(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X08, 16, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_OK2_1(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 16, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_TX_OK2_1_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 16, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_0(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X08, 24, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_0(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 24, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_0_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 24, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_1(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X0C, 0, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_1(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 0, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_1_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 0, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE2(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X0C, 8, 8)
+#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE2(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 8, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE2_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 8, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
+#define C2H_AP_REQ_TXRPT_SET_LEN(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_LEN_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TRIGGER(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
+#define C2H_AP_REQ_TXRPT_SET_TRIGGER(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_AP_REQ_TXRPT_SET_TRIGGER_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_CMD_ID(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_CMD_ID(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_SET_CMD_ID_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_SEQ(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_SEQ(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_SET_SEQ_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_TRYING_BITMAP(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X00, 16, 7)
+#define C2H_INITIAL_RATE_COLLECTION_SET_TRYING_BITMAP(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 7, value)
+#define C2H_INITIAL_RATE_COLLECTION_SET_TRYING_BITMAP_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 7, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE1(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE1(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE1_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE2(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE2(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE2_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE3(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE3(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE3_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE4(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE4(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE4_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE5(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X04, 24, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE5(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE5_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE6(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X08, 0, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE6(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE6_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE7(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X08, 8, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE7(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 8, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE7_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 8, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_LEN(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_LEN(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_SET_LEN_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_TRIGGER(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_TRIGGER(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_SET_TRIGGER_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_RA_RPT_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define C2H_RA_RPT_SET_CMD_ID(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_RA_RPT_SET_CMD_ID_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_RA_RPT_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define C2H_RA_RPT_SET_SEQ(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_RA_RPT_SET_SEQ_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_RA_RPT_GET_RATE(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8)
+#define C2H_RA_RPT_SET_RATE(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_RA_RPT_SET_RATE_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_RA_RPT_GET_MACID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8)
+#define C2H_RA_RPT_SET_MACID(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_RA_RPT_SET_MACID_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_RA_RPT_GET_USE_LDPC(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 0, 1)
+#define C2H_RA_RPT_SET_USE_LDPC(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 1, value)
+#define C2H_RA_RPT_SET_USE_LDPC_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 1, value)
+#define C2H_RA_RPT_GET_USE_TXBF(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X04, 1, 1)
+#define C2H_RA_RPT_SET_USE_TXBF(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 1, 1, value)
+#define C2H_RA_RPT_SET_USE_TXBF_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 1, 1, value)
+#define C2H_RA_RPT_GET_COLLISION_STATE(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
+#define C2H_RA_RPT_SET_COLLISION_STATE(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_RA_RPT_SET_COLLISION_STATE_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_RA_RPT_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
+#define C2H_RA_RPT_SET_LEN(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_RA_RPT_SET_LEN_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_RA_RPT_GET_TRIGGER(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
+#define C2H_RA_RPT_SET_TRIGGER(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_RA_RPT_SET_TRIGGER_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_CMD_ID(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define C2H_SPECIAL_STATISTICS_SET_CMD_ID(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_SPECIAL_STATISTICS_SET_CMD_ID_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_SEQ(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define C2H_SPECIAL_STATISTICS_SET_SEQ(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_SPECIAL_STATISTICS_SET_SEQ_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_STATISTICS_IDX(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8)
+#define C2H_SPECIAL_STATISTICS_SET_STATISTICS_IDX(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_SPECIAL_STATISTICS_SET_STATISTICS_IDX_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA0(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X00, 24, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA0(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_SPECIAL_STATISTICS_SET_DATA0_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA1(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X04, 0, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA1(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define C2H_SPECIAL_STATISTICS_SET_DATA1_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 0, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA2(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X04, 8, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA2(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_SPECIAL_STATISTICS_SET_DATA2_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA3(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X04, 16, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA3(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define C2H_SPECIAL_STATISTICS_SET_DATA3_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 16, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA4(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X04, 24, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA4(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define C2H_SPECIAL_STATISTICS_SET_DATA4_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X04, 24, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA5(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X08, 0, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA5(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 0, 8, value)
+#define C2H_SPECIAL_STATISTICS_SET_DATA5_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 0, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA6(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X08, 8, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA6(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 8, 8, value)
+#define C2H_SPECIAL_STATISTICS_SET_DATA6_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 8, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA7(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X08, 16, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA7(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X08, 16, 8, value)
+#define C2H_SPECIAL_STATISTICS_SET_DATA7_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X08, 16, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_LEN(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
+#define C2H_SPECIAL_STATISTICS_SET_LEN(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_SPECIAL_STATISTICS_SET_LEN_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_TRIGGER(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
+#define C2H_SPECIAL_STATISTICS_SET_TRIGGER(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_SPECIAL_STATISTICS_SET_TRIGGER_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_RA_PARA_RPT_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define C2H_RA_PARA_RPT_SET_CMD_ID(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_RA_PARA_RPT_SET_CMD_ID_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_RA_PARA_RPT_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define C2H_RA_PARA_RPT_SET_SEQ(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_RA_PARA_RPT_SET_SEQ_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_RA_PARA_RPT_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
+#define C2H_RA_PARA_RPT_SET_LEN(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_RA_PARA_RPT_SET_LEN_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_RA_PARA_RPT_GET_TRIGGER(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
+#define C2H_RA_PARA_RPT_SET_TRIGGER(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_RA_PARA_RPT_SET_TRIGGER_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_CUR_CHANNEL_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define C2H_CUR_CHANNEL_SET_CMD_ID(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_CUR_CHANNEL_SET_CMD_ID_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_CUR_CHANNEL_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define C2H_CUR_CHANNEL_SET_SEQ(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_CUR_CHANNEL_SET_SEQ_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_CUR_CHANNEL_GET_CHANNEL_NUM(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X00, 16, 8)
+#define C2H_CUR_CHANNEL_SET_CHANNEL_NUM(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_CUR_CHANNEL_SET_CHANNEL_NUM_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_CUR_CHANNEL_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
+#define C2H_CUR_CHANNEL_SET_LEN(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_CUR_CHANNEL_SET_LEN_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_CUR_CHANNEL_GET_TRIGGER(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
+#define C2H_CUR_CHANNEL_SET_TRIGGER(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_CUR_CHANNEL_SET_TRIGGER_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_GPIO_WAKEUP_GET_CMD_ID(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 0, 8)
+#define C2H_GPIO_WAKEUP_SET_CMD_ID(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_GPIO_WAKEUP_SET_CMD_ID_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_GPIO_WAKEUP_GET_SEQ(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X00, 8, 8)
+#define C2H_GPIO_WAKEUP_SET_SEQ(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_GPIO_WAKEUP_SET_SEQ_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_GPIO_WAKEUP_GET_LEN(c2h_pkt) GET_C2H_FIELD(c2h_pkt + 0X0C, 16, 8)
+#define C2H_GPIO_WAKEUP_SET_LEN(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_GPIO_WAKEUP_SET_LEN_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_GPIO_WAKEUP_GET_TRIGGER(c2h_pkt) \
+ GET_C2H_FIELD(c2h_pkt + 0X0C, 24, 8)
+#define C2H_GPIO_WAKEUP_SET_TRIGGER(c2h_pkt, value) \
+ SET_C2H_FIELD_CLR(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_GPIO_WAKEUP_SET_TRIGGER_NO_CLR(c2h_pkt, value) \
+ SET_C2H_FIELD_NO_CLR(c2h_pkt + 0X0C, 24, 8, value)
#endif
diff --git a/hal/halmac/halmac_original_c2h_nic.h b/hal/halmac/halmac_original_c2h_nic.h
index b72c1ce..18cc2c7 100644
--- a/hal/halmac/halmac_original_c2h_nic.h
+++ b/hal/halmac/halmac_original_c2h_nic.h
@@ -1,229 +1,408 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
#ifndef _HAL_ORIGINALC2HFORMAT_H2C_C2H_NIC_H_
#define _HAL_ORIGINALC2HFORMAT_H2C_C2H_NIC_H_
-#define CMD_ID_C2H 0X00
-#define CMD_ID_DBG 0X00
-#define CMD_ID_C2H_LB 0X01
-#define CMD_ID_C2H_SND_TXBF 0X02
-#define CMD_ID_C2H_CCX_RPT 0X03
-#define CMD_ID_C2H_AP_REQ_TXRPT 0X04
-#define CMD_ID_C2H_INITIAL_RATE_COLLECTION 0X05
-#define CMD_ID_C2H_RA_RPT 0X0C
-#define CMD_ID_C2H_SPECIAL_STATISTICS 0X0D
-#define CMD_ID_C2H_RA_PARA_RPT 0X0E
-#define CMD_ID_C2H_CUR_CHANNEL 0X10
-#define CMD_ID_C2H_GPIO_WAKEUP 0X14
-#define C2H_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8)
-#define C2H_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value)
-#define C2H_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8)
-#define C2H_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value)
-#define DBG_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8)
-#define DBG_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value)
-#define DBG_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8)
-#define DBG_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value)
-#define DBG_GET_DBG_STR1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 8)
-#define DBG_SET_DBG_STR1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 8, __Value)
-#define DBG_GET_DBG_STR2(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 24, 8)
-#define DBG_SET_DBG_STR2(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 24, 8, __Value)
-#define DBG_GET_DBG_STR3(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 8)
-#define DBG_SET_DBG_STR3(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 8, __Value)
-#define DBG_GET_DBG_STR4(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8)
-#define DBG_SET_DBG_STR4(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value)
-#define DBG_GET_DBG_STR5(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 8)
-#define DBG_SET_DBG_STR5(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 8, __Value)
-#define DBG_GET_DBG_STR6(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 24, 8)
-#define DBG_SET_DBG_STR6(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 24, 8, __Value)
-#define DBG_GET_DBG_STR7(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 0, 8)
-#define DBG_SET_DBG_STR7(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 0, 8, __Value)
-#define DBG_GET_DBG_STR8(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 8, 8)
-#define DBG_SET_DBG_STR8(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 8, 8, __Value)
-#define DBG_GET_DBG_STR9(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 16, 8)
-#define DBG_SET_DBG_STR9(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 16, 8, __Value)
-#define DBG_GET_DBG_STR10(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 24, 8)
-#define DBG_SET_DBG_STR10(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 24, 8, __Value)
-#define DBG_GET_DBG_STR11(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 0, 8)
-#define DBG_SET_DBG_STR11(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 0, 8, __Value)
-#define DBG_GET_DBG_STR12(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 8, 8)
-#define DBG_SET_DBG_STR12(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 8, 8, __Value)
-#define DBG_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8)
-#define DBG_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value)
-#define DBG_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8)
-#define DBG_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value)
-#define C2H_LB_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8)
-#define C2H_LB_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value)
-#define C2H_LB_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8)
-#define C2H_LB_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value)
-#define C2H_LB_GET_PAYLOAD1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 16)
-#define C2H_LB_SET_PAYLOAD1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 16, __Value)
-#define C2H_LB_GET_PAYLOAD2(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 32)
-#define C2H_LB_SET_PAYLOAD2(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 32, __Value)
-#define C2H_LB_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8)
-#define C2H_LB_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value)
-#define C2H_LB_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8)
-#define C2H_LB_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value)
-#define C2H_SND_TXBF_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8)
-#define C2H_SND_TXBF_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value)
-#define C2H_SND_TXBF_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8)
-#define C2H_SND_TXBF_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value)
-#define C2H_SND_TXBF_GET_SND_RESULT(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 1)
-#define C2H_SND_TXBF_SET_SND_RESULT(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 1, __Value)
-#define C2H_SND_TXBF_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8)
-#define C2H_SND_TXBF_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value)
-#define C2H_SND_TXBF_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8)
-#define C2H_SND_TXBF_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value)
-#define C2H_CCX_RPT_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8)
-#define C2H_CCX_RPT_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value)
-#define C2H_CCX_RPT_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8)
-#define C2H_CCX_RPT_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value)
-#define C2H_CCX_RPT_GET_QSEL(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 5)
-#define C2H_CCX_RPT_SET_QSEL(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 5, __Value)
-#define C2H_CCX_RPT_GET_BMC(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 21, 1)
-#define C2H_CCX_RPT_SET_BMC(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 21, 1, __Value)
-#define C2H_CCX_RPT_GET_LIFE_TIME_OVER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 22, 1)
-#define C2H_CCX_RPT_SET_LIFE_TIME_OVER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 22, 1, __Value)
-#define C2H_CCX_RPT_GET_RETRY_OVER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 23, 1)
-#define C2H_CCX_RPT_SET_RETRY_OVER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 23, 1, __Value)
-#define C2H_CCX_RPT_GET_MACID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 24, 8)
-#define C2H_CCX_RPT_SET_MACID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 24, 8, __Value)
-#define C2H_CCX_RPT_GET_DATA_RETRY_CNT(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 6)
-#define C2H_CCX_RPT_SET_DATA_RETRY_CNT(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 6, __Value)
-#define C2H_CCX_RPT_GET_QUEUE7_0(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8)
-#define C2H_CCX_RPT_SET_QUEUE7_0(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value)
-#define C2H_CCX_RPT_GET_QUEUE15_8(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 8)
-#define C2H_CCX_RPT_SET_QUEUE15_8(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 8, __Value)
-#define C2H_CCX_RPT_GET_FINAL_DATA_RATE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 24, 8)
-#define C2H_CCX_RPT_SET_FINAL_DATA_RATE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 24, 8, __Value)
-#define C2H_CCX_RPT_GET_SW_DEFINE_0(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 0, 8)
-#define C2H_CCX_RPT_SET_SW_DEFINE_0(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 0, 8, __Value)
-#define C2H_CCX_RPT_GET_SW_DEFINE_1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 8, 4)
-#define C2H_CCX_RPT_SET_SW_DEFINE_1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 8, 4, __Value)
-#define C2H_CCX_RPT_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8)
-#define C2H_CCX_RPT_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value)
-#define C2H_CCX_RPT_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8)
-#define C2H_CCX_RPT_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value)
-#define C2H_AP_REQ_TXRPT_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8)
-#define C2H_AP_REQ_TXRPT_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value)
-#define C2H_AP_REQ_TXRPT_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8)
-#define C2H_AP_REQ_TXRPT_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value)
-#define C2H_AP_REQ_TXRPT_GET_STA1_MACID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 8)
-#define C2H_AP_REQ_TXRPT_SET_STA1_MACID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 8, __Value)
-#define C2H_AP_REQ_TXRPT_GET_TX_OK1_0(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 24, 8)
-#define C2H_AP_REQ_TXRPT_SET_TX_OK1_0(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 24, 8, __Value)
-#define C2H_AP_REQ_TXRPT_GET_TX_OK1_1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 8)
-#define C2H_AP_REQ_TXRPT_SET_TX_OK1_1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 8, __Value)
-#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_0(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8)
-#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_0(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value)
-#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 8)
-#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 8, __Value)
-#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 24, 8)
-#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 24, 8, __Value)
-#define C2H_AP_REQ_TXRPT_GET_STA2_MACID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 0, 8)
-#define C2H_AP_REQ_TXRPT_SET_STA2_MACID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 0, 8, __Value)
-#define C2H_AP_REQ_TXRPT_GET_TX_OK2_0(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 8, 8)
-#define C2H_AP_REQ_TXRPT_SET_TX_OK2_0(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 8, 8, __Value)
-#define C2H_AP_REQ_TXRPT_GET_TX_OK2_1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 16, 8)
-#define C2H_AP_REQ_TXRPT_SET_TX_OK2_1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 16, 8, __Value)
-#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_0(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 24, 8)
-#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_0(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 24, 8, __Value)
-#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 0, 8)
-#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 0, 8, __Value)
-#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE2(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 8, 8)
-#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE2(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 8, 8, __Value)
-#define C2H_AP_REQ_TXRPT_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8)
-#define C2H_AP_REQ_TXRPT_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value)
-#define C2H_AP_REQ_TXRPT_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8)
-#define C2H_AP_REQ_TXRPT_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value)
-#define C2H_INITIAL_RATE_COLLECTION_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8)
-#define C2H_INITIAL_RATE_COLLECTION_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value)
-#define C2H_INITIAL_RATE_COLLECTION_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8)
-#define C2H_INITIAL_RATE_COLLECTION_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value)
-#define C2H_INITIAL_RATE_COLLECTION_GET_TRYING_BITMAP(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 7)
-#define C2H_INITIAL_RATE_COLLECTION_SET_TRYING_BITMAP(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 7, __Value)
-#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 24, 8)
-#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 24, 8, __Value)
-#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE2(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 8)
-#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE2(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 8, __Value)
-#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE3(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8)
-#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE3(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value)
-#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE4(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 8)
-#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE4(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 8, __Value)
-#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE5(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 24, 8)
-#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE5(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 24, 8, __Value)
-#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE6(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 0, 8)
-#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE6(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 0, 8, __Value)
-#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE7(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 8, 8)
-#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE7(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 8, 8, __Value)
-#define C2H_INITIAL_RATE_COLLECTION_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8)
-#define C2H_INITIAL_RATE_COLLECTION_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value)
-#define C2H_INITIAL_RATE_COLLECTION_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8)
-#define C2H_INITIAL_RATE_COLLECTION_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value)
-#define C2H_RA_RPT_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8)
-#define C2H_RA_RPT_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value)
-#define C2H_RA_RPT_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8)
-#define C2H_RA_RPT_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value)
-#define C2H_RA_RPT_GET_RATE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 8)
-#define C2H_RA_RPT_SET_RATE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 8, __Value)
-#define C2H_RA_RPT_GET_MACID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 24, 8)
-#define C2H_RA_RPT_SET_MACID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 24, 8, __Value)
-#define C2H_RA_RPT_GET_USE_LDPC(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 1)
-#define C2H_RA_RPT_SET_USE_LDPC(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 1, __Value)
-#define C2H_RA_RPT_GET_USE_TXBF(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 1, 1)
-#define C2H_RA_RPT_SET_USE_TXBF(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 1, 1, __Value)
-#define C2H_RA_RPT_GET_COLLISION_STATE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8)
-#define C2H_RA_RPT_SET_COLLISION_STATE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value)
-#define C2H_RA_RPT_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8)
-#define C2H_RA_RPT_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value)
-#define C2H_RA_RPT_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8)
-#define C2H_RA_RPT_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value)
-#define C2H_SPECIAL_STATISTICS_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8)
-#define C2H_SPECIAL_STATISTICS_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value)
-#define C2H_SPECIAL_STATISTICS_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8)
-#define C2H_SPECIAL_STATISTICS_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value)
-#define C2H_SPECIAL_STATISTICS_GET_STATISTICS_IDX(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 8)
-#define C2H_SPECIAL_STATISTICS_SET_STATISTICS_IDX(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 8, __Value)
-#define C2H_SPECIAL_STATISTICS_GET_DATA0(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 24, 8)
-#define C2H_SPECIAL_STATISTICS_SET_DATA0(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 24, 8, __Value)
-#define C2H_SPECIAL_STATISTICS_GET_DATA1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 8)
-#define C2H_SPECIAL_STATISTICS_SET_DATA1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 8, __Value)
-#define C2H_SPECIAL_STATISTICS_GET_DATA2(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8)
-#define C2H_SPECIAL_STATISTICS_SET_DATA2(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value)
-#define C2H_SPECIAL_STATISTICS_GET_DATA3(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 8)
-#define C2H_SPECIAL_STATISTICS_SET_DATA3(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 8, __Value)
-#define C2H_SPECIAL_STATISTICS_GET_DATA4(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 24, 8)
-#define C2H_SPECIAL_STATISTICS_SET_DATA4(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 24, 8, __Value)
-#define C2H_SPECIAL_STATISTICS_GET_DATA5(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 0, 8)
-#define C2H_SPECIAL_STATISTICS_SET_DATA5(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 0, 8, __Value)
-#define C2H_SPECIAL_STATISTICS_GET_DATA6(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 8, 8)
-#define C2H_SPECIAL_STATISTICS_SET_DATA6(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 8, 8, __Value)
-#define C2H_SPECIAL_STATISTICS_GET_DATA7(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 16, 8)
-#define C2H_SPECIAL_STATISTICS_SET_DATA7(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 16, 8, __Value)
-#define C2H_SPECIAL_STATISTICS_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8)
-#define C2H_SPECIAL_STATISTICS_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value)
-#define C2H_SPECIAL_STATISTICS_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8)
-#define C2H_SPECIAL_STATISTICS_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value)
-#define C2H_RA_PARA_RPT_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8)
-#define C2H_RA_PARA_RPT_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value)
-#define C2H_RA_PARA_RPT_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8)
-#define C2H_RA_PARA_RPT_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value)
-#define C2H_RA_PARA_RPT_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8)
-#define C2H_RA_PARA_RPT_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value)
-#define C2H_RA_PARA_RPT_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8)
-#define C2H_RA_PARA_RPT_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value)
-#define C2H_CUR_CHANNEL_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8)
-#define C2H_CUR_CHANNEL_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value)
-#define C2H_CUR_CHANNEL_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8)
-#define C2H_CUR_CHANNEL_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value)
-#define C2H_CUR_CHANNEL_GET_CHANNEL_NUM(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 8)
-#define C2H_CUR_CHANNEL_SET_CHANNEL_NUM(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 8, __Value)
-#define C2H_CUR_CHANNEL_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8)
-#define C2H_CUR_CHANNEL_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value)
-#define C2H_CUR_CHANNEL_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8)
-#define C2H_CUR_CHANNEL_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value)
-#define C2H_GPIO_WAKEUP_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8)
-#define C2H_GPIO_WAKEUP_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value)
-#define C2H_GPIO_WAKEUP_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8)
-#define C2H_GPIO_WAKEUP_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value)
-#define C2H_GPIO_WAKEUP_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8)
-#define C2H_GPIO_WAKEUP_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value)
-#define C2H_GPIO_WAKEUP_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8)
-#define C2H_GPIO_WAKEUP_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value)
+#define CMD_ID_C2H 0X00
+#define CMD_ID_DBG 0X00
+#define CMD_ID_C2H_LB 0X01
+#define CMD_ID_C2H_SND_TXBF 0X02
+#define CMD_ID_C2H_CCX_RPT 0X03
+#define CMD_ID_C2H_AP_REQ_TXRPT 0X04
+#define CMD_ID_C2H_INITIAL_RATE_COLLECTION 0X05
+#define CMD_ID_C2H_RA_RPT 0X0C
+#define CMD_ID_C2H_SPECIAL_STATISTICS 0X0D
+#define CMD_ID_C2H_RA_PARA_RPT 0X0E
+#define CMD_ID_C2H_CUR_CHANNEL 0X10
+#define CMD_ID_C2H_GPIO_WAKEUP 0X14
+#define C2H_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define C2H_SET_CMD_ID(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define C2H_SET_SEQ(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define DBG_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define DBG_SET_CMD_ID(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define DBG_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define DBG_SET_SEQ(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define DBG_GET_DBG_STR1(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8)
+#define DBG_SET_DBG_STR1(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value)
+#define DBG_GET_DBG_STR2(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8)
+#define DBG_SET_DBG_STR2(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value)
+#define DBG_GET_DBG_STR3(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
+#define DBG_SET_DBG_STR3(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
+#define DBG_GET_DBG_STR4(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
+#define DBG_SET_DBG_STR4(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
+#define DBG_GET_DBG_STR5(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8)
+#define DBG_SET_DBG_STR5(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value)
+#define DBG_GET_DBG_STR6(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8)
+#define DBG_SET_DBG_STR6(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value)
+#define DBG_GET_DBG_STR7(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 8)
+#define DBG_SET_DBG_STR7(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 8, value)
+#define DBG_GET_DBG_STR8(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 8, 8)
+#define DBG_SET_DBG_STR8(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 8, 8, value)
+#define DBG_GET_DBG_STR9(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 16, 8)
+#define DBG_SET_DBG_STR9(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 16, 8, value)
+#define DBG_GET_DBG_STR10(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 24, 8)
+#define DBG_SET_DBG_STR10(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 24, 8, value)
+#define DBG_GET_DBG_STR11(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 0, 8)
+#define DBG_SET_DBG_STR11(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 0, 8, value)
+#define DBG_GET_DBG_STR12(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 8, 8)
+#define DBG_SET_DBG_STR12(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 8, 8, value)
+#define DBG_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
+#define DBG_SET_LEN(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
+#define DBG_GET_TRIGGER(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
+#define DBG_SET_TRIGGER(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_LB_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define C2H_LB_SET_CMD_ID(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_LB_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define C2H_LB_SET_SEQ(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_LB_GET_PAYLOAD1(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 16)
+#define C2H_LB_SET_PAYLOAD1(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 16, value)
+#define C2H_LB_GET_PAYLOAD2(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 32)
+#define C2H_LB_SET_PAYLOAD2(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 32, value)
+#define C2H_LB_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
+#define C2H_LB_SET_LEN(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_LB_GET_TRIGGER(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
+#define C2H_LB_SET_TRIGGER(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_SND_TXBF_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define C2H_SND_TXBF_SET_CMD_ID(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_SND_TXBF_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define C2H_SND_TXBF_SET_SEQ(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_SND_TXBF_GET_SND_RESULT(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 1)
+#define C2H_SND_TXBF_SET_SND_RESULT(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 1, value)
+#define C2H_SND_TXBF_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
+#define C2H_SND_TXBF_SET_LEN(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_SND_TXBF_GET_TRIGGER(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
+#define C2H_SND_TXBF_SET_TRIGGER(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_CCX_RPT_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define C2H_CCX_RPT_SET_CMD_ID(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_CCX_RPT_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define C2H_CCX_RPT_SET_SEQ(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_CCX_RPT_GET_QSEL(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 5)
+#define C2H_CCX_RPT_SET_QSEL(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 5, value)
+#define C2H_CCX_RPT_GET_BMC(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 21, 1)
+#define C2H_CCX_RPT_SET_BMC(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 21, 1, value)
+#define C2H_CCX_RPT_GET_LIFE_TIME_OVER(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 22, 1)
+#define C2H_CCX_RPT_SET_LIFE_TIME_OVER(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 22, 1, value)
+#define C2H_CCX_RPT_GET_RETRY_OVER(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 23, 1)
+#define C2H_CCX_RPT_SET_RETRY_OVER(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 23, 1, value)
+#define C2H_CCX_RPT_GET_MACID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8)
+#define C2H_CCX_RPT_SET_MACID(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_CCX_RPT_GET_DATA_RETRY_CNT(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 6)
+#define C2H_CCX_RPT_SET_DATA_RETRY_CNT(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 6, value)
+#define C2H_CCX_RPT_GET_QUEUE7_0(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
+#define C2H_CCX_RPT_SET_QUEUE7_0(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_CCX_RPT_GET_QUEUE15_8(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8)
+#define C2H_CCX_RPT_SET_QUEUE15_8(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value)
+#define C2H_CCX_RPT_GET_FINAL_DATA_RATE(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8)
+#define C2H_CCX_RPT_SET_FINAL_DATA_RATE(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value)
+#define C2H_CCX_RPT_GET_SW_DEFINE_0(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 8)
+#define C2H_CCX_RPT_SET_SW_DEFINE_0(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 8, value)
+#define C2H_CCX_RPT_GET_SW_DEFINE_1(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 8, 4)
+#define C2H_CCX_RPT_SET_SW_DEFINE_1(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 8, 4, value)
+#define C2H_CCX_RPT_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
+#define C2H_CCX_RPT_SET_LEN(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_CCX_RPT_GET_TRIGGER(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
+#define C2H_CCX_RPT_SET_TRIGGER(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_CMD_ID(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define C2H_AP_REQ_TXRPT_SET_CMD_ID(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define C2H_AP_REQ_TXRPT_SET_SEQ(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_STA1_MACID(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8)
+#define C2H_AP_REQ_TXRPT_SET_STA1_MACID(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_OK1_0(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_OK1_0(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_OK1_1(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_OK1_1(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_0(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_0(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_1(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_1(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE1(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8)
+#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE1(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_STA2_MACID(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 8)
+#define C2H_AP_REQ_TXRPT_SET_STA2_MACID(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_OK2_0(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 8, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_OK2_0(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 8, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_OK2_1(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 16, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_OK2_1(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 16, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_0(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 24, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_0(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 24, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_1(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 0, 8)
+#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_1(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 0, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE2(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 8, 8)
+#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE2(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 8, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_LEN(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
+#define C2H_AP_REQ_TXRPT_SET_LEN(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_AP_REQ_TXRPT_GET_TRIGGER(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
+#define C2H_AP_REQ_TXRPT_SET_TRIGGER(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_CMD_ID(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_CMD_ID(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_SEQ(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_SEQ(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_TRYING_BITMAP(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 7)
+#define C2H_INITIAL_RATE_COLLECTION_SET_TRYING_BITMAP(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 7, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE1(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE1(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE2(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE2(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE3(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE3(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE4(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE4(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE5(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE5(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE6(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE6(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE7(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 8, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE7(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 8, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_LEN(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_LEN(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_INITIAL_RATE_COLLECTION_GET_TRIGGER(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
+#define C2H_INITIAL_RATE_COLLECTION_SET_TRIGGER(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_RA_RPT_GET_CMD_ID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define C2H_RA_RPT_SET_CMD_ID(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_RA_RPT_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define C2H_RA_RPT_SET_SEQ(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_RA_RPT_GET_RATE(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8)
+#define C2H_RA_RPT_SET_RATE(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_RA_RPT_GET_MACID(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8)
+#define C2H_RA_RPT_SET_MACID(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_RA_RPT_GET_USE_LDPC(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 1)
+#define C2H_RA_RPT_SET_USE_LDPC(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 1, value)
+#define C2H_RA_RPT_GET_USE_TXBF(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 1, 1)
+#define C2H_RA_RPT_SET_USE_TXBF(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 1, 1, value)
+#define C2H_RA_RPT_GET_COLLISION_STATE(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
+#define C2H_RA_RPT_SET_COLLISION_STATE(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_RA_RPT_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
+#define C2H_RA_RPT_SET_LEN(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_RA_RPT_GET_TRIGGER(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
+#define C2H_RA_RPT_SET_TRIGGER(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_CMD_ID(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define C2H_SPECIAL_STATISTICS_SET_CMD_ID(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_SEQ(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define C2H_SPECIAL_STATISTICS_SET_SEQ(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_STATISTICS_IDX(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8)
+#define C2H_SPECIAL_STATISTICS_SET_STATISTICS_IDX(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA0(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 24, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA0(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 24, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA1(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 0, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA1(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 0, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA2(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 8, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA2(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 8, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA3(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 16, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA3(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 16, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA4(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X04, 24, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA4(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X04, 24, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA5(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 0, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA5(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 0, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA6(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 8, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA6(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 8, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_DATA7(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X08, 16, 8)
+#define C2H_SPECIAL_STATISTICS_SET_DATA7(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X08, 16, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_LEN(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
+#define C2H_SPECIAL_STATISTICS_SET_LEN(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_SPECIAL_STATISTICS_GET_TRIGGER(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
+#define C2H_SPECIAL_STATISTICS_SET_TRIGGER(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_RA_PARA_RPT_GET_CMD_ID(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define C2H_RA_PARA_RPT_SET_CMD_ID(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_RA_PARA_RPT_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define C2H_RA_PARA_RPT_SET_SEQ(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_RA_PARA_RPT_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
+#define C2H_RA_PARA_RPT_SET_LEN(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_RA_PARA_RPT_GET_TRIGGER(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
+#define C2H_RA_PARA_RPT_SET_TRIGGER(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_CUR_CHANNEL_GET_CMD_ID(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define C2H_CUR_CHANNEL_SET_CMD_ID(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_CUR_CHANNEL_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define C2H_CUR_CHANNEL_SET_SEQ(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_CUR_CHANNEL_GET_CHANNEL_NUM(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 16, 8)
+#define C2H_CUR_CHANNEL_SET_CHANNEL_NUM(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 16, 8, value)
+#define C2H_CUR_CHANNEL_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
+#define C2H_CUR_CHANNEL_SET_LEN(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_CUR_CHANNEL_GET_TRIGGER(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
+#define C2H_CUR_CHANNEL_SET_TRIGGER(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
+#define C2H_GPIO_WAKEUP_GET_CMD_ID(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 0, 8)
+#define C2H_GPIO_WAKEUP_SET_CMD_ID(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 0, 8, value)
+#define C2H_GPIO_WAKEUP_GET_SEQ(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X00, 8, 8)
+#define C2H_GPIO_WAKEUP_SET_SEQ(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X00, 8, 8, value)
+#define C2H_GPIO_WAKEUP_GET_LEN(c2h_pkt) LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 16, 8)
+#define C2H_GPIO_WAKEUP_SET_LEN(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 16, 8, value)
+#define C2H_GPIO_WAKEUP_GET_TRIGGER(c2h_pkt) \
+ LE_BITS_TO_4BYTE(c2h_pkt + 0X0C, 24, 8)
+#define C2H_GPIO_WAKEUP_SET_TRIGGER(c2h_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(c2h_pkt + 0X0C, 24, 8, value)
#endif
diff --git a/hal/halmac/halmac_original_h2c_ap.h b/hal/halmac/halmac_original_h2c_ap.h
index 248ffad..b28c995 100644
--- a/hal/halmac/halmac_original_h2c_ap.h
+++ b/hal/halmac/halmac_original_h2c_ap.h
@@ -1,38 +1,57 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
#ifndef _HAL_ORIGINALH2CFORMAT_H2C_C2H_AP_H_
#define _HAL_ORIGINALH2CFORMAT_H2C_C2H_AP_H_
-#define CMD_ID_ORIGINAL_H2C 0X00
-#define CMD_ID_H2C2H_LB 0X0
-#define CMD_ID_D0_SCAN_OFFLOAD_CTRL 0X06
-#define CMD_ID_RSVD_PAGE 0X0
-#define CMD_ID_MEDIA_STATUS_RPT 0X01
-#define CMD_ID_KEEP_ALIVE 0X03
-#define CMD_ID_DISCONNECT_DECISION 0X04
-#define CMD_ID_AP_OFFLOAD 0X08
-#define CMD_ID_BCN_RSVDPAGE 0X09
-#define CMD_ID_PROBE_RSP_RSVDPAGE 0X0A
-#define CMD_ID_SET_PWR_MODE 0X00
-#define CMD_ID_PS_TUNING_PARA 0X01
-#define CMD_ID_PS_TUNING_PARA_II 0X02
-#define CMD_ID_PS_LPS_PARA 0X03
-#define CMD_ID_P2P_PS_OFFLOAD 0X04
-#define CMD_ID_PS_SCAN_EN 0X05
-#define CMD_ID_SAP_PS 0X06
-#define CMD_ID_INACTIVE_PS 0X07
-#define CMD_ID_MACID_CFG 0X00
-#define CMD_ID_TXBF 0X01
-#define CMD_ID_RSSI_SETTING 0X02
-#define CMD_ID_AP_REQ_TXRPT 0X03
-#define CMD_ID_INIT_RATE_COLLECTION 0X04
-#define CMD_ID_IQK_OFFLOAD 0X05
-#define CMD_ID_RA_PARA_ADJUST 0X06
-#define CMD_ID_WWLAN 0X00
-#define CMD_ID_REMOTE_WAKE_CTRL 0X01
-#define CMD_ID_AOAC_BLOBAL_INFO 0X02
-#define CMD_ID_AOAC_RSVD_PAGE 0X03
-#define CMD_ID_AOAC_RSVD_PAGE2 0X04
-#define CMD_ID_D0_SCAN_OFFLOAD_INFO 0X05
-#define CMD_ID_CHANNEL_SWITCH_OFFLOAD 0X07
-#define CMD_ID_AOAC_RSVD_PAGE3 0X08
+#define CMD_ID_ORIGINAL_H2C 0X00
+#define CMD_ID_H2C2H_LB 0X0
+#define CMD_ID_D0_SCAN_OFFLOAD_CTRL 0X06
+#define CMD_ID_RSVD_PAGE 0X0
+#define CMD_ID_MEDIA_STATUS_RPT 0X01
+#define CMD_ID_KEEP_ALIVE 0X03
+#define CMD_ID_DISCONNECT_DECISION 0X04
+#define CMD_ID_AP_OFFLOAD 0X08
+#define CMD_ID_BCN_RSVDPAGE 0X09
+#define CMD_ID_PROBE_RSP_RSVDPAGE 0X0A
+#define CMD_ID_SINGLE_CHANNELSWITCH 0X1C
+#define CMD_ID_SINGLE_CHANNELSWITCH_V2 0X1D
+#define CMD_ID_SET_PWR_MODE 0X00
+#define CMD_ID_PS_TUNING_PARA 0X01
+#define CMD_ID_PS_TUNING_PARA_II 0X02
+#define CMD_ID_PS_LPS_PARA 0X03
+#define CMD_ID_P2P_PS_OFFLOAD 0X04
+#define CMD_ID_PS_SCAN_EN 0X05
+#define CMD_ID_SAP_PS 0X06
+#define CMD_ID_INACTIVE_PS 0X07
+#define CMD_ID_MACID_CFG 0X00
+#define CMD_ID_TXBF 0X01
+#define CMD_ID_RSSI_SETTING 0X02
+#define CMD_ID_AP_REQ_TXRPT 0X03
+#define CMD_ID_INIT_RATE_COLLECTION 0X04
+#define CMD_ID_IQK_OFFLOAD 0X05
+#define CMD_ID_MACID_CFG_3SS 0X06
+#define CMD_ID_RA_PARA_ADJUST 0X07
+#define CMD_ID_WWLAN 0X00
+#define CMD_ID_REMOTE_WAKE_CTRL 0X01
+#define CMD_ID_AOAC_GLOBAL_INFO 0X02
+#define CMD_ID_AOAC_RSVD_PAGE 0X03
+#define CMD_ID_AOAC_RSVD_PAGE2 0X04
+#define CMD_ID_D0_SCAN_OFFLOAD_INFO 0X05
+#define CMD_ID_CHANNEL_SWITCH_OFFLOAD 0X07
+#define CMD_ID_AOAC_RSVD_PAGE3 0X08
+#define CMD_ID_DBG_MSG_CTRL 0X1E
#define CLASS_ORIGINAL_H2C 0X00
#define CLASS_H2C2H_LB 0X07
#define CLASS_D0_SCAN_OFFLOAD_CTRL 0X04
@@ -43,810 +62,1600 @@
#define CLASS_AP_OFFLOAD 0X0
#define CLASS_BCN_RSVDPAGE 0X0
#define CLASS_PROBE_RSP_RSVDPAGE 0X0
+#define CLASS_SINGLE_CHANNELSWITCH 0X0
+#define CLASS_SINGLE_CHANNELSWITCH_V2 0X0
#define CLASS_SET_PWR_MODE 0X01
#define CLASS_PS_TUNING_PARA 0X01
#define CLASS_PS_TUNING_PARA_II 0X01
#define CLASS_PS_LPS_PARA 0X01
#define CLASS_P2P_PS_OFFLOAD 0X01
-#define CLASS_PS_SCAN_EN 0X0
-#define CLASS_SAP_PS 0X0
-#define CLASS_INACTIVE_PS 0X0
+#define CLASS_PS_SCAN_EN 0X1
+#define CLASS_SAP_PS 0X1
+#define CLASS_INACTIVE_PS 0X1
#define CLASS_MACID_CFG 0X2
#define CLASS_TXBF 0X2
#define CLASS_RSSI_SETTING 0X2
#define CLASS_AP_REQ_TXRPT 0X2
#define CLASS_INIT_RATE_COLLECTION 0X2
#define CLASS_IQK_OFFLOAD 0X2
+#define CLASS_MACID_CFG_3SS 0X2
#define CLASS_RA_PARA_ADJUST 0X02
#define CLASS_WWLAN 0X4
#define CLASS_REMOTE_WAKE_CTRL 0X4
-#define CLASS_AOAC_BLOBAL_INFO 0X04
+#define CLASS_AOAC_GLOBAL_INFO 0X04
#define CLASS_AOAC_RSVD_PAGE 0X04
#define CLASS_AOAC_RSVD_PAGE2 0X04
#define CLASS_D0_SCAN_OFFLOAD_INFO 0X04
#define CLASS_CHANNEL_SWITCH_OFFLOAD 0X04
#define CLASS_AOAC_RSVD_PAGE3 0X04
-#define ORIGINAL_H2C_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4)
-#define ORIGINAL_H2C_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define ORIGINAL_H2C_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define ORIGINAL_H2C_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3)
-#define ORIGINAL_H2C_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define ORIGINAL_H2C_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define H2C2H_LB_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4)
-#define H2C2H_LB_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define H2C2H_LB_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define H2C2H_LB_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3)
-#define H2C2H_LB_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define H2C2H_LB_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define H2C2H_LB_GET_SEQ(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8)
-#define H2C2H_LB_SET_SEQ(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value)
-#define H2C2H_LB_SET_SEQ_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value)
-#define H2C2H_LB_GET_PAYLOAD1(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 16)
-#define H2C2H_LB_SET_PAYLOAD1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 16, __Value)
-#define H2C2H_LB_SET_PAYLOAD1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 16, __Value)
-#define H2C2H_LB_GET_PAYLOAD2(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 32)
-#define H2C2H_LB_SET_PAYLOAD2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 32, __Value)
-#define H2C2H_LB_SET_PAYLOAD2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 32, __Value)
-#define D0_SCAN_OFFLOAD_CTRL_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4)
-#define D0_SCAN_OFFLOAD_CTRL_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define D0_SCAN_OFFLOAD_CTRL_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define D0_SCAN_OFFLOAD_CTRL_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3)
-#define D0_SCAN_OFFLOAD_CTRL_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define D0_SCAN_OFFLOAD_CTRL_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define D0_SCAN_OFFLOAD_CTRL_GET_D0_SCAN_FUN_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1)
-#define D0_SCAN_OFFLOAD_CTRL_SET_D0_SCAN_FUN_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value)
-#define D0_SCAN_OFFLOAD_CTRL_SET_D0_SCAN_FUN_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value)
-#define D0_SCAN_OFFLOAD_CTRL_GET_RTD3FUN_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1)
-#define D0_SCAN_OFFLOAD_CTRL_SET_RTD3FUN_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value)
-#define D0_SCAN_OFFLOAD_CTRL_SET_RTD3FUN_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value)
-#define D0_SCAN_OFFLOAD_CTRL_GET_U3_SCAN_FUN_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 10, 1)
-#define D0_SCAN_OFFLOAD_CTRL_SET_U3_SCAN_FUN_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 10, 1, __Value)
-#define D0_SCAN_OFFLOAD_CTRL_SET_U3_SCAN_FUN_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 10, 1, __Value)
-#define D0_SCAN_OFFLOAD_CTRL_GET_NLO_FUN_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 11, 1)
-#define D0_SCAN_OFFLOAD_CTRL_SET_NLO_FUN_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 11, 1, __Value)
-#define D0_SCAN_OFFLOAD_CTRL_SET_NLO_FUN_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 11, 1, __Value)
-#define D0_SCAN_OFFLOAD_CTRL_GET_IPS_DEPENDENT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 12, 1)
-#define D0_SCAN_OFFLOAD_CTRL_SET_IPS_DEPENDENT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 12, 1, __Value)
-#define D0_SCAN_OFFLOAD_CTRL_SET_IPS_DEPENDENT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 12, 1, __Value)
-#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_PROBE_PACKET(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 17)
-#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_PROBE_PACKET(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 17, __Value)
-#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_PROBE_PACKET_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 17, __Value)
-#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SCAN_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8)
-#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SCAN_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value)
-#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SCAN_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value)
-#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SSID_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8)
-#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SSID_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value)
-#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SSID_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value)
-#define RSVD_PAGE_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4)
-#define RSVD_PAGE_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define RSVD_PAGE_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define RSVD_PAGE_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3)
-#define RSVD_PAGE_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define RSVD_PAGE_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define RSVD_PAGE_GET_LOC_PROBE_RSP(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8)
-#define RSVD_PAGE_SET_LOC_PROBE_RSP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value)
-#define RSVD_PAGE_SET_LOC_PROBE_RSP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value)
-#define RSVD_PAGE_GET_LOC_PS_POLL(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8)
-#define RSVD_PAGE_SET_LOC_PS_POLL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value)
-#define RSVD_PAGE_SET_LOC_PS_POLL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value)
-#define RSVD_PAGE_GET_LOC_NULL_DATA(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8)
-#define RSVD_PAGE_SET_LOC_NULL_DATA(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value)
-#define RSVD_PAGE_SET_LOC_NULL_DATA_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value)
-#define RSVD_PAGE_GET_LOC_QOS_NULL(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8)
-#define RSVD_PAGE_SET_LOC_QOS_NULL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value)
-#define RSVD_PAGE_SET_LOC_QOS_NULL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value)
-#define RSVD_PAGE_GET_LOC_BT_QOS_NULL(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8)
-#define RSVD_PAGE_SET_LOC_BT_QOS_NULL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value)
-#define RSVD_PAGE_SET_LOC_BT_QOS_NULL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value)
-#define RSVD_PAGE_GET_LOC_CTS2SELF(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 8)
-#define RSVD_PAGE_SET_LOC_CTS2SELF(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 8, __Value)
-#define RSVD_PAGE_SET_LOC_CTS2SELF_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 8, __Value)
-#define RSVD_PAGE_GET_LOC_LTECOEX_QOSNULL(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 24, 8)
-#define RSVD_PAGE_SET_LOC_LTECOEX_QOSNULL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 24, 8, __Value)
-#define RSVD_PAGE_SET_LOC_LTECOEX_QOSNULL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 24, 8, __Value)
-#define MEDIA_STATUS_RPT_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4)
-#define MEDIA_STATUS_RPT_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define MEDIA_STATUS_RPT_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define MEDIA_STATUS_RPT_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3)
-#define MEDIA_STATUS_RPT_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define MEDIA_STATUS_RPT_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define MEDIA_STATUS_RPT_GET_OP_MODE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1)
-#define MEDIA_STATUS_RPT_SET_OP_MODE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value)
-#define MEDIA_STATUS_RPT_SET_OP_MODE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value)
-#define MEDIA_STATUS_RPT_GET_MACID_IN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1)
-#define MEDIA_STATUS_RPT_SET_MACID_IN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value)
-#define MEDIA_STATUS_RPT_SET_MACID_IN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value)
-#define MEDIA_STATUS_RPT_GET_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8)
-#define MEDIA_STATUS_RPT_SET_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value)
-#define MEDIA_STATUS_RPT_SET_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value)
-#define MEDIA_STATUS_RPT_GET_MACID_END(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8)
-#define MEDIA_STATUS_RPT_SET_MACID_END(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value)
-#define MEDIA_STATUS_RPT_SET_MACID_END_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value)
-#define KEEP_ALIVE_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4)
-#define KEEP_ALIVE_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define KEEP_ALIVE_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define KEEP_ALIVE_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3)
-#define KEEP_ALIVE_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define KEEP_ALIVE_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define KEEP_ALIVE_GET_ENABLE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1)
-#define KEEP_ALIVE_SET_ENABLE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value)
-#define KEEP_ALIVE_SET_ENABLE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value)
-#define KEEP_ALIVE_GET_ADOPT_USER_SETTING(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1)
-#define KEEP_ALIVE_SET_ADOPT_USER_SETTING(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value)
-#define KEEP_ALIVE_SET_ADOPT_USER_SETTING_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value)
-#define KEEP_ALIVE_GET_PKT_TYPE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 10, 1)
-#define KEEP_ALIVE_SET_PKT_TYPE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 10, 1, __Value)
-#define KEEP_ALIVE_SET_PKT_TYPE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 10, 1, __Value)
-#define KEEP_ALIVE_GET_KEEP_ALIVE_CHECK_PERIOD(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8)
-#define KEEP_ALIVE_SET_KEEP_ALIVE_CHECK_PERIOD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value)
-#define KEEP_ALIVE_SET_KEEP_ALIVE_CHECK_PERIOD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value)
-#define DISCONNECT_DECISION_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4)
-#define DISCONNECT_DECISION_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define DISCONNECT_DECISION_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define DISCONNECT_DECISION_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3)
-#define DISCONNECT_DECISION_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define DISCONNECT_DECISION_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define DISCONNECT_DECISION_GET_ENABLE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1)
-#define DISCONNECT_DECISION_SET_ENABLE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value)
-#define DISCONNECT_DECISION_SET_ENABLE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value)
-#define DISCONNECT_DECISION_GET_ADOPT_USER_SETTING(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1)
-#define DISCONNECT_DECISION_SET_ADOPT_USER_SETTING(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value)
-#define DISCONNECT_DECISION_SET_ADOPT_USER_SETTING_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value)
-#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 10, 1)
-#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 10, 1, __Value)
-#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 10, 1, __Value)
-#define DISCONNECT_DECISION_GET_DISCONNECT_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 11, 1)
-#define DISCONNECT_DECISION_SET_DISCONNECT_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 11, 1, __Value)
-#define DISCONNECT_DECISION_SET_DISCONNECT_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 11, 1, __Value)
-#define DISCONNECT_DECISION_GET_DISCON_DECISION_CHECK_PERIOD(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8)
-#define DISCONNECT_DECISION_SET_DISCON_DECISION_CHECK_PERIOD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value)
-#define DISCONNECT_DECISION_SET_DISCON_DECISION_CHECK_PERIOD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value)
-#define DISCONNECT_DECISION_GET_TRY_PKT_NUM(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8)
-#define DISCONNECT_DECISION_SET_TRY_PKT_NUM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value)
-#define DISCONNECT_DECISION_SET_TRY_PKT_NUM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value)
-#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_LIMIT(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8)
-#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_LIMIT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value)
-#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_LIMIT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value)
-#define AP_OFFLOAD_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4)
-#define AP_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define AP_OFFLOAD_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define AP_OFFLOAD_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3)
-#define AP_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define AP_OFFLOAD_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define AP_OFFLOAD_GET_ON(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1)
-#define AP_OFFLOAD_SET_ON(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value)
-#define AP_OFFLOAD_SET_ON_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value)
-#define AP_OFFLOAD_GET_CFG_MIFI_PLATFORM(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1)
-#define AP_OFFLOAD_SET_CFG_MIFI_PLATFORM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value)
-#define AP_OFFLOAD_SET_CFG_MIFI_PLATFORM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value)
-#define AP_OFFLOAD_GET_LINKED(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 10, 1)
-#define AP_OFFLOAD_SET_LINKED(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 10, 1, __Value)
-#define AP_OFFLOAD_SET_LINKED_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 10, 1, __Value)
-#define AP_OFFLOAD_GET_EN_AUTO_WAKE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 11, 1)
-#define AP_OFFLOAD_SET_EN_AUTO_WAKE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 11, 1, __Value)
-#define AP_OFFLOAD_SET_EN_AUTO_WAKE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 11, 1, __Value)
-#define AP_OFFLOAD_GET_WAKE_FLAG(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 12, 1)
-#define AP_OFFLOAD_SET_WAKE_FLAG(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 12, 1, __Value)
-#define AP_OFFLOAD_SET_WAKE_FLAG_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 12, 1, __Value)
-#define AP_OFFLOAD_GET_HIDDEN_ROOT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 1)
-#define AP_OFFLOAD_SET_HIDDEN_ROOT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 1, __Value)
-#define AP_OFFLOAD_SET_HIDDEN_ROOT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 1, __Value)
-#define AP_OFFLOAD_GET_HIDDEN_VAP1(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 17, 1)
-#define AP_OFFLOAD_SET_HIDDEN_VAP1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 17, 1, __Value)
-#define AP_OFFLOAD_SET_HIDDEN_VAP1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 17, 1, __Value)
-#define AP_OFFLOAD_GET_HIDDEN_VAP2(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 18, 1)
-#define AP_OFFLOAD_SET_HIDDEN_VAP2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 18, 1, __Value)
-#define AP_OFFLOAD_SET_HIDDEN_VAP2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 18, 1, __Value)
-#define AP_OFFLOAD_GET_HIDDEN_VAP3(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 19, 1)
-#define AP_OFFLOAD_SET_HIDDEN_VAP3(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 19, 1, __Value)
-#define AP_OFFLOAD_SET_HIDDEN_VAP3_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 19, 1, __Value)
-#define AP_OFFLOAD_GET_HIDDEN_VAP4(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 20, 1)
-#define AP_OFFLOAD_SET_HIDDEN_VAP4(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 20, 1, __Value)
-#define AP_OFFLOAD_SET_HIDDEN_VAP4_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 20, 1, __Value)
-#define AP_OFFLOAD_GET_DENYANY_ROOT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 1)
-#define AP_OFFLOAD_SET_DENYANY_ROOT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 1, __Value)
-#define AP_OFFLOAD_SET_DENYANY_ROOT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 1, __Value)
-#define AP_OFFLOAD_GET_DENYANY_VAP1(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 25, 1)
-#define AP_OFFLOAD_SET_DENYANY_VAP1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 25, 1, __Value)
-#define AP_OFFLOAD_SET_DENYANY_VAP1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 25, 1, __Value)
-#define AP_OFFLOAD_GET_DENYANY_VAP2(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 26, 1)
-#define AP_OFFLOAD_SET_DENYANY_VAP2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 26, 1, __Value)
-#define AP_OFFLOAD_SET_DENYANY_VAP2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 26, 1, __Value)
-#define AP_OFFLOAD_GET_DENYANY_VAP3(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 27, 1)
-#define AP_OFFLOAD_SET_DENYANY_VAP3(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 27, 1, __Value)
-#define AP_OFFLOAD_SET_DENYANY_VAP3_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 27, 1, __Value)
-#define AP_OFFLOAD_GET_DENYANY_VAP4(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 28, 1)
-#define AP_OFFLOAD_SET_DENYANY_VAP4(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 28, 1, __Value)
-#define AP_OFFLOAD_SET_DENYANY_VAP4_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 28, 1, __Value)
-#define AP_OFFLOAD_GET_WAIT_TBTT_CNT(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8)
-#define AP_OFFLOAD_SET_WAIT_TBTT_CNT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value)
-#define AP_OFFLOAD_SET_WAIT_TBTT_CNT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value)
-#define AP_OFFLOAD_GET_WAKE_TIMEOUT(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8)
-#define AP_OFFLOAD_SET_WAKE_TIMEOUT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value)
-#define AP_OFFLOAD_SET_WAKE_TIMEOUT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value)
-#define AP_OFFLOAD_GET_LEN_IV_PAIR(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 8)
-#define AP_OFFLOAD_SET_LEN_IV_PAIR(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 8, __Value)
-#define AP_OFFLOAD_SET_LEN_IV_PAIR_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 8, __Value)
-#define AP_OFFLOAD_GET_LEN_IV_GRP(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 24, 8)
-#define AP_OFFLOAD_SET_LEN_IV_GRP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 24, 8, __Value)
-#define AP_OFFLOAD_SET_LEN_IV_GRP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 24, 8, __Value)
-#define BCN_RSVDPAGE_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4)
-#define BCN_RSVDPAGE_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define BCN_RSVDPAGE_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define BCN_RSVDPAGE_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3)
-#define BCN_RSVDPAGE_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define BCN_RSVDPAGE_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define BCN_RSVDPAGE_GET_LOC_ROOT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8)
-#define BCN_RSVDPAGE_SET_LOC_ROOT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value)
-#define BCN_RSVDPAGE_SET_LOC_ROOT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value)
-#define BCN_RSVDPAGE_GET_LOC_VAP1(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8)
-#define BCN_RSVDPAGE_SET_LOC_VAP1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value)
-#define BCN_RSVDPAGE_SET_LOC_VAP1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value)
-#define BCN_RSVDPAGE_GET_LOC_VAP2(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8)
-#define BCN_RSVDPAGE_SET_LOC_VAP2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value)
-#define BCN_RSVDPAGE_SET_LOC_VAP2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value)
-#define BCN_RSVDPAGE_GET_LOC_VAP3(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8)
-#define BCN_RSVDPAGE_SET_LOC_VAP3(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value)
-#define BCN_RSVDPAGE_SET_LOC_VAP3_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value)
-#define BCN_RSVDPAGE_GET_LOC_VAP4(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8)
-#define BCN_RSVDPAGE_SET_LOC_VAP4(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value)
-#define BCN_RSVDPAGE_SET_LOC_VAP4_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value)
-#define PROBE_RSP_RSVDPAGE_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4)
-#define PROBE_RSP_RSVDPAGE_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define PROBE_RSP_RSVDPAGE_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define PROBE_RSP_RSVDPAGE_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3)
-#define PROBE_RSP_RSVDPAGE_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define PROBE_RSP_RSVDPAGE_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define PROBE_RSP_RSVDPAGE_GET_LOC_ROOT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8)
-#define PROBE_RSP_RSVDPAGE_SET_LOC_ROOT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value)
-#define PROBE_RSP_RSVDPAGE_SET_LOC_ROOT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value)
-#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP1(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8)
-#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value)
-#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value)
-#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP2(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8)
-#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value)
-#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value)
-#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP3(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8)
-#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP3(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value)
-#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP3_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value)
-#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP4(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8)
-#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP4(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value)
-#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP4_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value)
-#define SET_PWR_MODE_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4)
-#define SET_PWR_MODE_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define SET_PWR_MODE_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define SET_PWR_MODE_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3)
-#define SET_PWR_MODE_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define SET_PWR_MODE_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define SET_PWR_MODE_GET_MODE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 7)
-#define SET_PWR_MODE_SET_MODE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 7, __Value)
-#define SET_PWR_MODE_SET_MODE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 7, __Value)
-#define SET_PWR_MODE_GET_CLK_REQUEST(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 15, 1)
-#define SET_PWR_MODE_SET_CLK_REQUEST(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 15, 1, __Value)
-#define SET_PWR_MODE_SET_CLK_REQUEST_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 15, 1, __Value)
-#define SET_PWR_MODE_GET_RLBM(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 4)
-#define SET_PWR_MODE_SET_RLBM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 4, __Value)
-#define SET_PWR_MODE_SET_RLBM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 4, __Value)
-#define SET_PWR_MODE_GET_SMART_PS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 20, 4)
-#define SET_PWR_MODE_SET_SMART_PS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 20, 4, __Value)
-#define SET_PWR_MODE_SET_SMART_PS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 20, 4, __Value)
-#define SET_PWR_MODE_GET_AWAKE_INTERVAL(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8)
-#define SET_PWR_MODE_SET_AWAKE_INTERVAL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value)
-#define SET_PWR_MODE_SET_AWAKE_INTERVAL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value)
-#define SET_PWR_MODE_GET_B_ALL_QUEUE_UAPSD(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 1)
-#define SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 1, __Value)
-#define SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 1, __Value)
-#define SET_PWR_MODE_GET_PWR_STATE(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8)
-#define SET_PWR_MODE_SET_PWR_STATE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value)
-#define SET_PWR_MODE_SET_PWR_STATE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value)
-#define SET_PWR_MODE_GET_LOW_POWER_RX_BCN(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 1)
-#define SET_PWR_MODE_SET_LOW_POWER_RX_BCN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 1, __Value)
-#define SET_PWR_MODE_SET_LOW_POWER_RX_BCN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 1, __Value)
-#define SET_PWR_MODE_GET_ANT_AUTO_SWITCH(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 17, 1)
-#define SET_PWR_MODE_SET_ANT_AUTO_SWITCH(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 17, 1, __Value)
-#define SET_PWR_MODE_SET_ANT_AUTO_SWITCH_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 17, 1, __Value)
-#define SET_PWR_MODE_GET_PS_ALLOW_BT_HIGH_PRIORITY(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 18, 1)
-#define SET_PWR_MODE_SET_PS_ALLOW_BT_HIGH_PRIORITY(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 18, 1, __Value)
-#define SET_PWR_MODE_SET_PS_ALLOW_BT_HIGH_PRIORITY_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 18, 1, __Value)
-#define SET_PWR_MODE_GET_PROTECT_BCN(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 19, 1)
-#define SET_PWR_MODE_SET_PROTECT_BCN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 19, 1, __Value)
-#define SET_PWR_MODE_SET_PROTECT_BCN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 19, 1, __Value)
-#define SET_PWR_MODE_GET_SILENCE_PERIOD(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 20, 1)
-#define SET_PWR_MODE_SET_SILENCE_PERIOD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 20, 1, __Value)
-#define SET_PWR_MODE_SET_SILENCE_PERIOD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 20, 1, __Value)
-#define SET_PWR_MODE_GET_FAST_BT_CONNECT(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 21, 1)
-#define SET_PWR_MODE_SET_FAST_BT_CONNECT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 21, 1, __Value)
-#define SET_PWR_MODE_SET_FAST_BT_CONNECT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 21, 1, __Value)
-#define SET_PWR_MODE_GET_TWO_ANTENNA_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 22, 1)
-#define SET_PWR_MODE_SET_TWO_ANTENNA_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 22, 1, __Value)
-#define SET_PWR_MODE_SET_TWO_ANTENNA_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 22, 1, __Value)
-#define SET_PWR_MODE_GET_ADOPT_USER_SETTING(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 24, 1)
-#define SET_PWR_MODE_SET_ADOPT_USER_SETTING(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 24, 1, __Value)
-#define SET_PWR_MODE_SET_ADOPT_USER_SETTING_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 24, 1, __Value)
-#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 25, 3)
-#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 25, 3, __Value)
-#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 25, 3, __Value)
-#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT2(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 28, 4)
-#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 28, 4, __Value)
-#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 28, 4, __Value)
-#define PS_TUNING_PARA_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4)
-#define PS_TUNING_PARA_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define PS_TUNING_PARA_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define PS_TUNING_PARA_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3)
-#define PS_TUNING_PARA_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define PS_TUNING_PARA_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define PS_TUNING_PARA_GET_BCN_TO_LIMIT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 7)
-#define PS_TUNING_PARA_SET_BCN_TO_LIMIT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 7, __Value)
-#define PS_TUNING_PARA_SET_BCN_TO_LIMIT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 7, __Value)
-#define PS_TUNING_PARA_GET_DTIM_TIME_OUT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 15, 1)
-#define PS_TUNING_PARA_SET_DTIM_TIME_OUT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 15, 1, __Value)
-#define PS_TUNING_PARA_SET_DTIM_TIME_OUT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 15, 1, __Value)
-#define PS_TUNING_PARA_GET_PS_TIME_OUT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 4)
-#define PS_TUNING_PARA_SET_PS_TIME_OUT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 4, __Value)
-#define PS_TUNING_PARA_SET_PS_TIME_OUT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 4, __Value)
-#define PS_TUNING_PARA_GET_ADOPT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8)
-#define PS_TUNING_PARA_SET_ADOPT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value)
-#define PS_TUNING_PARA_SET_ADOPT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value)
-#define PS_TUNING_PARA_II_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4)
-#define PS_TUNING_PARA_II_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define PS_TUNING_PARA_II_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define PS_TUNING_PARA_II_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3)
-#define PS_TUNING_PARA_II_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define PS_TUNING_PARA_II_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define PS_TUNING_PARA_II_GET_BCN_TO_PERIOD(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 7)
-#define PS_TUNING_PARA_II_SET_BCN_TO_PERIOD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 7, __Value)
-#define PS_TUNING_PARA_II_SET_BCN_TO_PERIOD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 7, __Value)
-#define PS_TUNING_PARA_II_GET_ADOPT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 15, 1)
-#define PS_TUNING_PARA_II_SET_ADOPT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 15, 1, __Value)
-#define PS_TUNING_PARA_II_SET_ADOPT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 15, 1, __Value)
-#define PS_TUNING_PARA_II_GET_DRV_EARLY_IVL(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8)
-#define PS_TUNING_PARA_II_SET_DRV_EARLY_IVL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value)
-#define PS_TUNING_PARA_II_SET_DRV_EARLY_IVL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value)
-#define PS_LPS_PARA_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4)
-#define PS_LPS_PARA_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define PS_LPS_PARA_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define PS_LPS_PARA_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3)
-#define PS_LPS_PARA_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define PS_LPS_PARA_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define PS_LPS_PARA_GET_LPS_CONTROL(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8)
-#define PS_LPS_PARA_SET_LPS_CONTROL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value)
-#define PS_LPS_PARA_SET_LPS_CONTROL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value)
-#define P2P_PS_OFFLOAD_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4)
-#define P2P_PS_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define P2P_PS_OFFLOAD_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define P2P_PS_OFFLOAD_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3)
-#define P2P_PS_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define P2P_PS_OFFLOAD_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define P2P_PS_OFFLOAD_GET_OFFLOAD_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1)
-#define P2P_PS_OFFLOAD_SET_OFFLOAD_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value)
-#define P2P_PS_OFFLOAD_SET_OFFLOAD_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value)
-#define P2P_PS_OFFLOAD_GET_ROLE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1)
-#define P2P_PS_OFFLOAD_SET_ROLE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value)
-#define P2P_PS_OFFLOAD_SET_ROLE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value)
-#define P2P_PS_OFFLOAD_GET_CTWINDOW_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 10, 1)
-#define P2P_PS_OFFLOAD_SET_CTWINDOW_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 10, 1, __Value)
-#define P2P_PS_OFFLOAD_SET_CTWINDOW_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 10, 1, __Value)
-#define P2P_PS_OFFLOAD_GET_NOA0_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 11, 1)
-#define P2P_PS_OFFLOAD_SET_NOA0_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 11, 1, __Value)
-#define P2P_PS_OFFLOAD_SET_NOA0_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 11, 1, __Value)
-#define P2P_PS_OFFLOAD_GET_NOA1_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 12, 1)
-#define P2P_PS_OFFLOAD_SET_NOA1_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 12, 1, __Value)
-#define P2P_PS_OFFLOAD_SET_NOA1_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 12, 1, __Value)
-#define P2P_PS_OFFLOAD_GET_ALL_STA_SLEEP(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 13, 1)
-#define P2P_PS_OFFLOAD_SET_ALL_STA_SLEEP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 13, 1, __Value)
-#define P2P_PS_OFFLOAD_SET_ALL_STA_SLEEP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 13, 1, __Value)
-#define P2P_PS_OFFLOAD_GET_DISCOVERY(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 14, 1)
-#define P2P_PS_OFFLOAD_SET_DISCOVERY(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 14, 1, __Value)
-#define P2P_PS_OFFLOAD_SET_DISCOVERY_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 14, 1, __Value)
-#define PS_SCAN_EN_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4)
-#define PS_SCAN_EN_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define PS_SCAN_EN_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define PS_SCAN_EN_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3)
-#define PS_SCAN_EN_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define PS_SCAN_EN_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define PS_SCAN_EN_GET_ENABLE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1)
-#define PS_SCAN_EN_SET_ENABLE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value)
-#define PS_SCAN_EN_SET_ENABLE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value)
-#define SAP_PS_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4)
-#define SAP_PS_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define SAP_PS_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define SAP_PS_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3)
-#define SAP_PS_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define SAP_PS_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define SAP_PS_GET_ENABLE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1)
-#define SAP_PS_SET_ENABLE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value)
-#define SAP_PS_SET_ENABLE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value)
-#define SAP_PS_GET_EN_PS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1)
-#define SAP_PS_SET_EN_PS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value)
-#define SAP_PS_SET_EN_PS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value)
-#define SAP_PS_GET_EN_LP_RX(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 10, 1)
-#define SAP_PS_SET_EN_LP_RX(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 10, 1, __Value)
-#define SAP_PS_SET_EN_LP_RX_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 10, 1, __Value)
-#define SAP_PS_GET_MANUAL_32K(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 11, 1)
-#define SAP_PS_SET_MANUAL_32K(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 11, 1, __Value)
-#define SAP_PS_SET_MANUAL_32K_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 11, 1, __Value)
-#define SAP_PS_GET_DURATION(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8)
-#define SAP_PS_SET_DURATION(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value)
-#define SAP_PS_SET_DURATION_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value)
-#define INACTIVE_PS_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4)
-#define INACTIVE_PS_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define INACTIVE_PS_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define INACTIVE_PS_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3)
-#define INACTIVE_PS_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define INACTIVE_PS_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define INACTIVE_PS_GET_ENABLE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1)
-#define INACTIVE_PS_SET_ENABLE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value)
-#define INACTIVE_PS_SET_ENABLE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value)
-#define INACTIVE_PS_GET_IGNORE_PS_CONDITION(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1)
-#define INACTIVE_PS_SET_IGNORE_PS_CONDITION(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value)
-#define INACTIVE_PS_SET_IGNORE_PS_CONDITION_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value)
-#define INACTIVE_PS_GET_FREQUENCY(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8)
-#define INACTIVE_PS_SET_FREQUENCY(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value)
-#define INACTIVE_PS_SET_FREQUENCY_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value)
-#define INACTIVE_PS_GET_DURATION(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8)
-#define INACTIVE_PS_SET_DURATION(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value)
-#define INACTIVE_PS_SET_DURATION_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value)
-#define MACID_CFG_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4)
-#define MACID_CFG_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define MACID_CFG_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define MACID_CFG_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3)
-#define MACID_CFG_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define MACID_CFG_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define MACID_CFG_GET_MAC_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8)
-#define MACID_CFG_SET_MAC_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value)
-#define MACID_CFG_SET_MAC_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value)
-#define MACID_CFG_GET_RATE_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 5)
-#define MACID_CFG_SET_RATE_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 5, __Value)
-#define MACID_CFG_SET_RATE_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 5, __Value)
-#define MACID_CFG_GET_SGI(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 23, 1)
-#define MACID_CFG_SET_SGI(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 23, 1, __Value)
-#define MACID_CFG_SET_SGI_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 23, 1, __Value)
-#define MACID_CFG_GET_BW(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 2)
-#define MACID_CFG_SET_BW(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 2, __Value)
-#define MACID_CFG_SET_BW_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 2, __Value)
-#define MACID_CFG_GET_LDPC_CAP(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 26, 1)
-#define MACID_CFG_SET_LDPC_CAP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 26, 1, __Value)
-#define MACID_CFG_SET_LDPC_CAP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 26, 1, __Value)
-#define MACID_CFG_GET_NO_UPDATE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 27, 1)
-#define MACID_CFG_SET_NO_UPDATE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 27, 1, __Value)
-#define MACID_CFG_SET_NO_UPDATE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 27, 1, __Value)
-#define MACID_CFG_GET_WHT_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 28, 2)
-#define MACID_CFG_SET_WHT_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 28, 2, __Value)
-#define MACID_CFG_SET_WHT_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 28, 2, __Value)
-#define MACID_CFG_GET_DISPT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 30, 1)
-#define MACID_CFG_SET_DISPT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 30, 1, __Value)
-#define MACID_CFG_SET_DISPT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 30, 1, __Value)
-#define MACID_CFG_GET_DISRA(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 31, 1)
-#define MACID_CFG_SET_DISRA(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 31, 1, __Value)
-#define MACID_CFG_SET_DISRA_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 31, 1, __Value)
-#define MACID_CFG_GET_RATE_MASK7_0(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8)
-#define MACID_CFG_SET_RATE_MASK7_0(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value)
-#define MACID_CFG_SET_RATE_MASK7_0_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value)
-#define MACID_CFG_GET_RATE_MASK15_8(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8)
-#define MACID_CFG_SET_RATE_MASK15_8(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value)
-#define MACID_CFG_SET_RATE_MASK15_8_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value)
-#define MACID_CFG_GET_RATE_MASK23_16(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 8)
-#define MACID_CFG_SET_RATE_MASK23_16(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 8, __Value)
-#define MACID_CFG_SET_RATE_MASK23_16_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 8, __Value)
-#define MACID_CFG_GET_RATE_MASK31_24(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 24, 8)
-#define MACID_CFG_SET_RATE_MASK31_24(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 24, 8, __Value)
-#define MACID_CFG_SET_RATE_MASK31_24_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 24, 8, __Value)
-#define TXBF_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4)
-#define TXBF_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define TXBF_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define TXBF_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3)
-#define TXBF_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define TXBF_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define TXBF_GET_NDPA0_HEAD_PAGE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8)
-#define TXBF_SET_NDPA0_HEAD_PAGE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value)
-#define TXBF_SET_NDPA0_HEAD_PAGE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value)
-#define TXBF_GET_NDPA1_HEAD_PAGE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8)
-#define TXBF_SET_NDPA1_HEAD_PAGE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value)
-#define TXBF_SET_NDPA1_HEAD_PAGE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value)
-#define TXBF_GET_PERIOD_0(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8)
-#define TXBF_SET_PERIOD_0(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value)
-#define TXBF_SET_PERIOD_0_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value)
-#define RSSI_SETTING_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4)
-#define RSSI_SETTING_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define RSSI_SETTING_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define RSSI_SETTING_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3)
-#define RSSI_SETTING_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define RSSI_SETTING_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define RSSI_SETTING_GET_MAC_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8)
-#define RSSI_SETTING_SET_MAC_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value)
-#define RSSI_SETTING_SET_MAC_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value)
-#define RSSI_SETTING_GET_RSSI(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 7)
-#define RSSI_SETTING_SET_RSSI(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 7, __Value)
-#define RSSI_SETTING_SET_RSSI_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 7, __Value)
-#define RSSI_SETTING_GET_RA_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8)
-#define RSSI_SETTING_SET_RA_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value)
-#define RSSI_SETTING_SET_RA_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value)
-#define AP_REQ_TXRPT_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4)
-#define AP_REQ_TXRPT_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define AP_REQ_TXRPT_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define AP_REQ_TXRPT_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3)
-#define AP_REQ_TXRPT_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define AP_REQ_TXRPT_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define AP_REQ_TXRPT_GET_STA1_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8)
-#define AP_REQ_TXRPT_SET_STA1_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value)
-#define AP_REQ_TXRPT_SET_STA1_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value)
-#define AP_REQ_TXRPT_GET_STA2_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8)
-#define AP_REQ_TXRPT_SET_STA2_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value)
-#define AP_REQ_TXRPT_SET_STA2_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value)
-#define AP_REQ_TXRPT_GET_RTY_OK_TOTAL(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 1)
-#define AP_REQ_TXRPT_SET_RTY_OK_TOTAL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 1, __Value)
-#define AP_REQ_TXRPT_SET_RTY_OK_TOTAL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 1, __Value)
-#define AP_REQ_TXRPT_GET_RTY_CNT_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 25, 1)
-#define AP_REQ_TXRPT_SET_RTY_CNT_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 25, 1, __Value)
-#define AP_REQ_TXRPT_SET_RTY_CNT_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 25, 1, __Value)
-#define INIT_RATE_COLLECTION_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4)
-#define INIT_RATE_COLLECTION_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define INIT_RATE_COLLECTION_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define INIT_RATE_COLLECTION_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3)
-#define INIT_RATE_COLLECTION_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define INIT_RATE_COLLECTION_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define INIT_RATE_COLLECTION_GET_STA1_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8)
-#define INIT_RATE_COLLECTION_SET_STA1_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value)
-#define INIT_RATE_COLLECTION_SET_STA1_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value)
-#define INIT_RATE_COLLECTION_GET_STA2_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8)
-#define INIT_RATE_COLLECTION_SET_STA2_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value)
-#define INIT_RATE_COLLECTION_SET_STA2_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value)
-#define INIT_RATE_COLLECTION_GET_STA3_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8)
-#define INIT_RATE_COLLECTION_SET_STA3_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value)
-#define INIT_RATE_COLLECTION_SET_STA3_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value)
-#define INIT_RATE_COLLECTION_GET_STA4_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8)
-#define INIT_RATE_COLLECTION_SET_STA4_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value)
-#define INIT_RATE_COLLECTION_SET_STA4_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value)
-#define INIT_RATE_COLLECTION_GET_STA5_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8)
-#define INIT_RATE_COLLECTION_SET_STA5_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value)
-#define INIT_RATE_COLLECTION_SET_STA5_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value)
-#define INIT_RATE_COLLECTION_GET_STA6_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 8)
-#define INIT_RATE_COLLECTION_SET_STA6_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 8, __Value)
-#define INIT_RATE_COLLECTION_SET_STA6_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 8, __Value)
-#define INIT_RATE_COLLECTION_GET_STA7_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 24, 8)
-#define INIT_RATE_COLLECTION_SET_STA7_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 24, 8, __Value)
-#define INIT_RATE_COLLECTION_SET_STA7_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 24, 8, __Value)
-#define IQK_OFFLOAD_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4)
-#define IQK_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define IQK_OFFLOAD_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define IQK_OFFLOAD_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3)
-#define IQK_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define IQK_OFFLOAD_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define IQK_OFFLOAD_GET_CHANNEL(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8)
-#define IQK_OFFLOAD_SET_CHANNEL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value)
-#define IQK_OFFLOAD_SET_CHANNEL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value)
-#define IQK_OFFLOAD_GET_BWBAND(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8)
-#define IQK_OFFLOAD_SET_BWBAND(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value)
-#define IQK_OFFLOAD_SET_BWBAND_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value)
-#define IQK_OFFLOAD_GET_EXTPALNA(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8)
-#define IQK_OFFLOAD_SET_EXTPALNA(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value)
-#define IQK_OFFLOAD_SET_EXTPALNA_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value)
-#define RA_PARA_ADJUST_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4)
-#define RA_PARA_ADJUST_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define RA_PARA_ADJUST_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define RA_PARA_ADJUST_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3)
-#define RA_PARA_ADJUST_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define RA_PARA_ADJUST_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define RA_PARA_ADJUST_GET_MAC_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8)
-#define RA_PARA_ADJUST_SET_MAC_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value)
-#define RA_PARA_ADJUST_SET_MAC_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value)
-#define RA_PARA_ADJUST_GET_PARAMETER_INDEX(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8)
-#define RA_PARA_ADJUST_SET_PARAMETER_INDEX(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value)
-#define RA_PARA_ADJUST_SET_PARAMETER_INDEX_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value)
-#define RA_PARA_ADJUST_GET_RATE_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8)
-#define RA_PARA_ADJUST_SET_RATE_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value)
-#define RA_PARA_ADJUST_SET_RATE_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value)
-#define RA_PARA_ADJUST_GET_VALUE_BYTE0(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8)
-#define RA_PARA_ADJUST_SET_VALUE_BYTE0(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value)
-#define RA_PARA_ADJUST_SET_VALUE_BYTE0_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value)
-#define RA_PARA_ADJUST_GET_VALUE_BYTE1(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8)
-#define RA_PARA_ADJUST_SET_VALUE_BYTE1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value)
-#define RA_PARA_ADJUST_SET_VALUE_BYTE1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value)
-#define RA_PARA_ADJUST_GET_ASK_FW_FOR_FW_PARA(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 8)
-#define RA_PARA_ADJUST_SET_ASK_FW_FOR_FW_PARA(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 8, __Value)
-#define RA_PARA_ADJUST_SET_ASK_FW_FOR_FW_PARA_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 8, __Value)
-#define WWLAN_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4)
-#define WWLAN_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define WWLAN_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define WWLAN_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3)
-#define WWLAN_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define WWLAN_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define WWLAN_GET_FUNC_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1)
-#define WWLAN_SET_FUNC_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value)
-#define WWLAN_SET_FUNC_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value)
-#define WWLAN_GET_PATTERM_MAT_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1)
-#define WWLAN_SET_PATTERM_MAT_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value)
-#define WWLAN_SET_PATTERM_MAT_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value)
-#define WWLAN_GET_MAGIC_PKT_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 10, 1)
-#define WWLAN_SET_MAGIC_PKT_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 10, 1, __Value)
-#define WWLAN_SET_MAGIC_PKT_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 10, 1, __Value)
-#define WWLAN_GET_UNICAST_WAKEUP_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 11, 1)
-#define WWLAN_SET_UNICAST_WAKEUP_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 11, 1, __Value)
-#define WWLAN_SET_UNICAST_WAKEUP_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 11, 1, __Value)
-#define WWLAN_GET_ALL_PKT_DROP(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 12, 1)
-#define WWLAN_SET_ALL_PKT_DROP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 12, 1, __Value)
-#define WWLAN_SET_ALL_PKT_DROP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 12, 1, __Value)
-#define WWLAN_GET_GPIO_ACTIVE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 13, 1)
-#define WWLAN_SET_GPIO_ACTIVE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 13, 1, __Value)
-#define WWLAN_SET_GPIO_ACTIVE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 13, 1, __Value)
-#define WWLAN_GET_REKEY_WAKEUP_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 14, 1)
-#define WWLAN_SET_REKEY_WAKEUP_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 14, 1, __Value)
-#define WWLAN_SET_REKEY_WAKEUP_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 14, 1, __Value)
-#define WWLAN_GET_DEAUTH_WAKEUP_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 15, 1)
-#define WWLAN_SET_DEAUTH_WAKEUP_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 15, 1, __Value)
-#define WWLAN_SET_DEAUTH_WAKEUP_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 15, 1, __Value)
-#define WWLAN_GET_GPIO_NUM(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 7)
-#define WWLAN_SET_GPIO_NUM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 7, __Value)
-#define WWLAN_SET_GPIO_NUM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 7, __Value)
-#define WWLAN_GET_DATAPIN_WAKEUP_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 23, 1)
-#define WWLAN_SET_DATAPIN_WAKEUP_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 23, 1, __Value)
-#define WWLAN_SET_DATAPIN_WAKEUP_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 23, 1, __Value)
-#define WWLAN_GET_GPIO_DURATION(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8)
-#define WWLAN_SET_GPIO_DURATION(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value)
-#define WWLAN_SET_GPIO_DURATION_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value)
-#define WWLAN_GET_GPIO_PLUS_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 1)
-#define WWLAN_SET_GPIO_PLUS_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 1, __Value)
-#define WWLAN_SET_GPIO_PLUS_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 1, __Value)
-#define WWLAN_GET_GPIO_PULSE_COUNT(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 1, 7)
-#define WWLAN_SET_GPIO_PULSE_COUNT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 1, 7, __Value)
-#define WWLAN_SET_GPIO_PULSE_COUNT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 1, 7, __Value)
-#define WWLAN_GET_DISABLE_UPHY(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 1)
-#define WWLAN_SET_DISABLE_UPHY(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 1, __Value)
-#define WWLAN_SET_DISABLE_UPHY_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 1, __Value)
-#define WWLAN_GET_HST2DEV_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 9, 1)
-#define WWLAN_SET_HST2DEV_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 9, 1, __Value)
-#define WWLAN_SET_HST2DEV_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 9, 1, __Value)
-#define WWLAN_GET_GPIO_DURATION_MS(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 10, 1)
-#define WWLAN_SET_GPIO_DURATION_MS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 10, 1, __Value)
-#define WWLAN_SET_GPIO_DURATION_MS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 10, 1, __Value)
-#define REMOTE_WAKE_CTRL_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4)
-#define REMOTE_WAKE_CTRL_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define REMOTE_WAKE_CTRL_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define REMOTE_WAKE_CTRL_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3)
-#define REMOTE_WAKE_CTRL_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define REMOTE_WAKE_CTRL_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define REMOTE_WAKE_CTRL_GET_REMOTE_WAKE_CTRL_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1)
-#define REMOTE_WAKE_CTRL_SET_REMOTE_WAKE_CTRL_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value)
-#define REMOTE_WAKE_CTRL_SET_REMOTE_WAKE_CTRL_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value)
-#define REMOTE_WAKE_CTRL_GET_ARP_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1)
-#define REMOTE_WAKE_CTRL_SET_ARP_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value)
-#define REMOTE_WAKE_CTRL_SET_ARP_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value)
-#define REMOTE_WAKE_CTRL_GET_NDP_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 10, 1)
-#define REMOTE_WAKE_CTRL_SET_NDP_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 10, 1, __Value)
-#define REMOTE_WAKE_CTRL_SET_NDP_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 10, 1, __Value)
-#define REMOTE_WAKE_CTRL_GET_GTK_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 11, 1)
-#define REMOTE_WAKE_CTRL_SET_GTK_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 11, 1, __Value)
-#define REMOTE_WAKE_CTRL_SET_GTK_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 11, 1, __Value)
-#define REMOTE_WAKE_CTRL_GET_NLO_OFFLOAD_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 12, 1)
-#define REMOTE_WAKE_CTRL_SET_NLO_OFFLOAD_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 12, 1, __Value)
-#define REMOTE_WAKE_CTRL_SET_NLO_OFFLOAD_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 12, 1, __Value)
-#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V1_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 13, 1)
-#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V1_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 13, 1, __Value)
-#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V1_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 13, 1, __Value)
-#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V2_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 14, 1)
-#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V2_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 14, 1, __Value)
-#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V2_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 14, 1, __Value)
-#define REMOTE_WAKE_CTRL_GET_FW_UNICAST(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 15, 1)
-#define REMOTE_WAKE_CTRL_SET_FW_UNICAST(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 15, 1, __Value)
-#define REMOTE_WAKE_CTRL_SET_FW_UNICAST_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 15, 1, __Value)
-#define REMOTE_WAKE_CTRL_GET_P2P_OFFLOAD_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 1)
-#define REMOTE_WAKE_CTRL_SET_P2P_OFFLOAD_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 1, __Value)
-#define REMOTE_WAKE_CTRL_SET_P2P_OFFLOAD_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 1, __Value)
-#define REMOTE_WAKE_CTRL_GET_RUNTIME_PM_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 17, 1)
-#define REMOTE_WAKE_CTRL_SET_RUNTIME_PM_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 17, 1, __Value)
-#define REMOTE_WAKE_CTRL_SET_RUNTIME_PM_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 17, 1, __Value)
-#define REMOTE_WAKE_CTRL_GET_NET_BIOS_DROP_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 18, 1)
-#define REMOTE_WAKE_CTRL_SET_NET_BIOS_DROP_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 18, 1, __Value)
-#define REMOTE_WAKE_CTRL_SET_NET_BIOS_DROP_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 18, 1, __Value)
-#define REMOTE_WAKE_CTRL_GET_ARP_ACTION(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 1)
-#define REMOTE_WAKE_CTRL_SET_ARP_ACTION(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 1, __Value)
-#define REMOTE_WAKE_CTRL_SET_ARP_ACTION_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 1, __Value)
-#define REMOTE_WAKE_CTRL_GET_FW_PARSING_UNTIL_WAKEUP(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 28, 1)
-#define REMOTE_WAKE_CTRL_SET_FW_PARSING_UNTIL_WAKEUP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 28, 1, __Value)
-#define REMOTE_WAKE_CTRL_SET_FW_PARSING_UNTIL_WAKEUP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 28, 1, __Value)
-#define REMOTE_WAKE_CTRL_GET_FW_PARSING_AFTER_WAKEUP(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 29, 1)
-#define REMOTE_WAKE_CTRL_SET_FW_PARSING_AFTER_WAKEUP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 29, 1, __Value)
-#define REMOTE_WAKE_CTRL_SET_FW_PARSING_AFTER_WAKEUP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 29, 1, __Value)
-#define AOAC_BLOBAL_INFO_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4)
-#define AOAC_BLOBAL_INFO_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define AOAC_BLOBAL_INFO_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define AOAC_BLOBAL_INFO_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3)
-#define AOAC_BLOBAL_INFO_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define AOAC_BLOBAL_INFO_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define AOAC_BLOBAL_INFO_GET_PAIR_WISE_ENC_ALG(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8)
-#define AOAC_BLOBAL_INFO_SET_PAIR_WISE_ENC_ALG(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value)
-#define AOAC_BLOBAL_INFO_SET_PAIR_WISE_ENC_ALG_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value)
-#define AOAC_BLOBAL_INFO_GET_GROUP_ENC_ALG(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8)
-#define AOAC_BLOBAL_INFO_SET_GROUP_ENC_ALG(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value)
-#define AOAC_BLOBAL_INFO_SET_GROUP_ENC_ALG_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value)
-#define AOAC_RSVD_PAGE_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4)
-#define AOAC_RSVD_PAGE_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define AOAC_RSVD_PAGE_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define AOAC_RSVD_PAGE_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3)
-#define AOAC_RSVD_PAGE_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define AOAC_RSVD_PAGE_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define AOAC_RSVD_PAGE_GET_LOC_REMOTE_CTRL_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8)
-#define AOAC_RSVD_PAGE_SET_LOC_REMOTE_CTRL_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value)
-#define AOAC_RSVD_PAGE_SET_LOC_REMOTE_CTRL_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value)
-#define AOAC_RSVD_PAGE_GET_LOC_ARP_RESPONSE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8)
-#define AOAC_RSVD_PAGE_SET_LOC_ARP_RESPONSE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value)
-#define AOAC_RSVD_PAGE_SET_LOC_ARP_RESPONSE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value)
-#define AOAC_RSVD_PAGE_GET_LOC_NEIGHBOR_ADVERTISEMENT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8)
-#define AOAC_RSVD_PAGE_SET_LOC_NEIGHBOR_ADVERTISEMENT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value)
-#define AOAC_RSVD_PAGE_SET_LOC_NEIGHBOR_ADVERTISEMENT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value)
-#define AOAC_RSVD_PAGE_GET_LOC_GTK_RSP(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8)
-#define AOAC_RSVD_PAGE_SET_LOC_GTK_RSP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value)
-#define AOAC_RSVD_PAGE_SET_LOC_GTK_RSP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value)
-#define AOAC_RSVD_PAGE_GET_LOC_GTK_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8)
-#define AOAC_RSVD_PAGE_SET_LOC_GTK_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value)
-#define AOAC_RSVD_PAGE_SET_LOC_GTK_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value)
-#define AOAC_RSVD_PAGE_GET_LOC_GTK_EXT_MEM(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 8)
-#define AOAC_RSVD_PAGE_SET_LOC_GTK_EXT_MEM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 8, __Value)
-#define AOAC_RSVD_PAGE_SET_LOC_GTK_EXT_MEM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 8, __Value)
-#define AOAC_RSVD_PAGE_GET_LOC_NDP_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 24, 8)
-#define AOAC_RSVD_PAGE_SET_LOC_NDP_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 24, 8, __Value)
-#define AOAC_RSVD_PAGE_SET_LOC_NDP_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 24, 8, __Value)
-#define AOAC_RSVD_PAGE2_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4)
-#define AOAC_RSVD_PAGE2_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define AOAC_RSVD_PAGE2_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define AOAC_RSVD_PAGE2_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3)
-#define AOAC_RSVD_PAGE2_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define AOAC_RSVD_PAGE2_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define AOAC_RSVD_PAGE2_GET_LOC_ROUTER_SOLICATION(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8)
-#define AOAC_RSVD_PAGE2_SET_LOC_ROUTER_SOLICATION(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value)
-#define AOAC_RSVD_PAGE2_SET_LOC_ROUTER_SOLICATION_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value)
-#define AOAC_RSVD_PAGE2_GET_LOC_BUBBLE_PACKET(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8)
-#define AOAC_RSVD_PAGE2_SET_LOC_BUBBLE_PACKET(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value)
-#define AOAC_RSVD_PAGE2_SET_LOC_BUBBLE_PACKET_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value)
-#define AOAC_RSVD_PAGE2_GET_LOC_TEREDO_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8)
-#define AOAC_RSVD_PAGE2_SET_LOC_TEREDO_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value)
-#define AOAC_RSVD_PAGE2_SET_LOC_TEREDO_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value)
-#define AOAC_RSVD_PAGE2_GET_LOC_REALWOW_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8)
-#define AOAC_RSVD_PAGE2_SET_LOC_REALWOW_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value)
-#define AOAC_RSVD_PAGE2_SET_LOC_REALWOW_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value)
-#define AOAC_RSVD_PAGE2_GET_LOC_KEEP_ALIVE_PKT(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8)
-#define AOAC_RSVD_PAGE2_SET_LOC_KEEP_ALIVE_PKT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value)
-#define AOAC_RSVD_PAGE2_SET_LOC_KEEP_ALIVE_PKT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value)
-#define AOAC_RSVD_PAGE2_GET_LOC_ACK_PATTERN(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 8)
-#define AOAC_RSVD_PAGE2_SET_LOC_ACK_PATTERN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 8, __Value)
-#define AOAC_RSVD_PAGE2_SET_LOC_ACK_PATTERN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 8, __Value)
-#define AOAC_RSVD_PAGE2_GET_LOC_WAKEUP_PATTERN(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 24, 8)
-#define AOAC_RSVD_PAGE2_SET_LOC_WAKEUP_PATTERN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 24, 8, __Value)
-#define AOAC_RSVD_PAGE2_SET_LOC_WAKEUP_PATTERN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 24, 8, __Value)
-#define D0_SCAN_OFFLOAD_INFO_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4)
-#define D0_SCAN_OFFLOAD_INFO_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define D0_SCAN_OFFLOAD_INFO_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define D0_SCAN_OFFLOAD_INFO_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3)
-#define D0_SCAN_OFFLOAD_INFO_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define D0_SCAN_OFFLOAD_INFO_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define D0_SCAN_OFFLOAD_INFO_GET_LOC_CHANNEL_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8)
-#define D0_SCAN_OFFLOAD_INFO_SET_LOC_CHANNEL_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value)
-#define D0_SCAN_OFFLOAD_INFO_SET_LOC_CHANNEL_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value)
-#define CHANNEL_SWITCH_OFFLOAD_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4)
-#define CHANNEL_SWITCH_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define CHANNEL_SWITCH_OFFLOAD_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define CHANNEL_SWITCH_OFFLOAD_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3)
-#define CHANNEL_SWITCH_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define CHANNEL_SWITCH_OFFLOAD_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define CHANNEL_SWITCH_OFFLOAD_GET_CHANNEL_NUM(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8)
-#define CHANNEL_SWITCH_OFFLOAD_SET_CHANNEL_NUM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value)
-#define CHANNEL_SWITCH_OFFLOAD_SET_CHANNEL_NUM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value)
-#define CHANNEL_SWITCH_OFFLOAD_GET_EN_RFE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8)
-#define CHANNEL_SWITCH_OFFLOAD_SET_EN_RFE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value)
-#define CHANNEL_SWITCH_OFFLOAD_SET_EN_RFE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value)
-#define CHANNEL_SWITCH_OFFLOAD_GET_RFE_TYPE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8)
-#define CHANNEL_SWITCH_OFFLOAD_SET_RFE_TYPE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value)
-#define CHANNEL_SWITCH_OFFLOAD_SET_RFE_TYPE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value)
-#define AOAC_RSVD_PAGE3_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 4)
-#define AOAC_RSVD_PAGE3_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define AOAC_RSVD_PAGE3_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 4, __Value)
-#define AOAC_RSVD_PAGE3_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3)
-#define AOAC_RSVD_PAGE3_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define AOAC_RSVD_PAGE3_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value)
-#define AOAC_RSVD_PAGE3_GET_LOC_NLO_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8)
-#define AOAC_RSVD_PAGE3_SET_LOC_NLO_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value)
-#define AOAC_RSVD_PAGE3_SET_LOC_NLO_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value)
-#define AOAC_RSVD_PAGE3_GET_LOC_AOAC_REPORT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8)
-#define AOAC_RSVD_PAGE3_SET_LOC_AOAC_REPORT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value)
-#define AOAC_RSVD_PAGE3_SET_LOC_AOAC_REPORT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value)
+#define CLASS_DBG_MSG_CTRL 0X07
+#define ORIGINAL_H2C_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define ORIGINAL_H2C_SET_CMD_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define ORIGINAL_H2C_SET_CMD_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define ORIGINAL_H2C_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define ORIGINAL_H2C_SET_CLASS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define ORIGINAL_H2C_SET_CLASS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define H2C2H_LB_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define H2C2H_LB_SET_CMD_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define H2C2H_LB_SET_CMD_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define H2C2H_LB_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define H2C2H_LB_SET_CLASS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define H2C2H_LB_SET_CLASS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define H2C2H_LB_GET_SEQ(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define H2C2H_LB_SET_SEQ(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define H2C2H_LB_SET_SEQ_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define H2C2H_LB_GET_PAYLOAD1(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 16)
+#define H2C2H_LB_SET_PAYLOAD1(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 16, value)
+#define H2C2H_LB_SET_PAYLOAD1_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 16, value)
+#define H2C2H_LB_GET_PAYLOAD2(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 0, 32)
+#define H2C2H_LB_SET_PAYLOAD2(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 32, value)
+#define H2C2H_LB_SET_PAYLOAD2_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 32, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_CMD_ID(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define D0_SCAN_OFFLOAD_CTRL_SET_CMD_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define D0_SCAN_OFFLOAD_CTRL_SET_CMD_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_CLASS(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define D0_SCAN_OFFLOAD_CTRL_SET_CLASS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define D0_SCAN_OFFLOAD_CTRL_SET_CLASS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_D0_SCAN_FUN_EN(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1)
+#define D0_SCAN_OFFLOAD_CTRL_SET_D0_SCAN_FUN_EN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define D0_SCAN_OFFLOAD_CTRL_SET_D0_SCAN_FUN_EN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_RTD3FUN_EN(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1)
+#define D0_SCAN_OFFLOAD_CTRL_SET_RTD3FUN_EN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define D0_SCAN_OFFLOAD_CTRL_SET_RTD3FUN_EN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_U3_SCAN_FUN_EN(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 10, 1)
+#define D0_SCAN_OFFLOAD_CTRL_SET_U3_SCAN_FUN_EN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value)
+#define D0_SCAN_OFFLOAD_CTRL_SET_U3_SCAN_FUN_EN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_NLO_FUN_EN(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 11, 1)
+#define D0_SCAN_OFFLOAD_CTRL_SET_NLO_FUN_EN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 11, 1, value)
+#define D0_SCAN_OFFLOAD_CTRL_SET_NLO_FUN_EN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 11, 1, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_IPS_DEPENDENT(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 12, 1)
+#define D0_SCAN_OFFLOAD_CTRL_SET_IPS_DEPENDENT(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 12, 1, value)
+#define D0_SCAN_OFFLOAD_CTRL_SET_IPS_DEPENDENT_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 12, 1, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_PROBE_PACKET(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 16, 17)
+#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_PROBE_PACKET(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 17, value)
+#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_PROBE_PACKET_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 17, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SCAN_INFO(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)
+#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SCAN_INFO(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SCAN_INFO_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SSID_INFO(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8)
+#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SSID_INFO(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SSID_INFO_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define RSVD_PAGE_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define RSVD_PAGE_SET_CMD_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define RSVD_PAGE_SET_CMD_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define RSVD_PAGE_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define RSVD_PAGE_SET_CLASS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define RSVD_PAGE_SET_CLASS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define RSVD_PAGE_GET_LOC_PROBE_RSP(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define RSVD_PAGE_SET_LOC_PROBE_RSP(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define RSVD_PAGE_SET_LOC_PROBE_RSP_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define RSVD_PAGE_GET_LOC_PS_POLL(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)
+#define RSVD_PAGE_SET_LOC_PS_POLL(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define RSVD_PAGE_SET_LOC_PS_POLL_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define RSVD_PAGE_GET_LOC_NULL_DATA(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)
+#define RSVD_PAGE_SET_LOC_NULL_DATA(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define RSVD_PAGE_SET_LOC_NULL_DATA_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define RSVD_PAGE_GET_LOC_QOS_NULL(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8)
+#define RSVD_PAGE_SET_LOC_QOS_NULL(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define RSVD_PAGE_SET_LOC_QOS_NULL_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define RSVD_PAGE_GET_LOC_BT_QOS_NULL(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8)
+#define RSVD_PAGE_SET_LOC_BT_QOS_NULL(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define RSVD_PAGE_SET_LOC_BT_QOS_NULL_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define RSVD_PAGE_GET_LOC_CTS2SELF(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 16, 8)
+#define RSVD_PAGE_SET_LOC_CTS2SELF(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 8, value)
+#define RSVD_PAGE_SET_LOC_CTS2SELF_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 8, value)
+#define RSVD_PAGE_GET_LOC_LTECOEX_QOSNULL(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 24, 8)
+#define RSVD_PAGE_SET_LOC_LTECOEX_QOSNULL(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 24, 8, value)
+#define RSVD_PAGE_SET_LOC_LTECOEX_QOSNULL_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 24, 8, value)
+#define MEDIA_STATUS_RPT_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define MEDIA_STATUS_RPT_SET_CMD_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define MEDIA_STATUS_RPT_SET_CMD_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define MEDIA_STATUS_RPT_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define MEDIA_STATUS_RPT_SET_CLASS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define MEDIA_STATUS_RPT_SET_CLASS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define MEDIA_STATUS_RPT_GET_OP_MODE(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1)
+#define MEDIA_STATUS_RPT_SET_OP_MODE(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define MEDIA_STATUS_RPT_SET_OP_MODE_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define MEDIA_STATUS_RPT_GET_MACID_IN(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1)
+#define MEDIA_STATUS_RPT_SET_MACID_IN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define MEDIA_STATUS_RPT_SET_MACID_IN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define MEDIA_STATUS_RPT_GET_MACID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)
+#define MEDIA_STATUS_RPT_SET_MACID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define MEDIA_STATUS_RPT_SET_MACID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define MEDIA_STATUS_RPT_GET_MACID_END(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)
+#define MEDIA_STATUS_RPT_SET_MACID_END(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define MEDIA_STATUS_RPT_SET_MACID_END_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define KEEP_ALIVE_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define KEEP_ALIVE_SET_CMD_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define KEEP_ALIVE_SET_CMD_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define KEEP_ALIVE_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define KEEP_ALIVE_SET_CLASS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define KEEP_ALIVE_SET_CLASS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define KEEP_ALIVE_GET_ENABLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1)
+#define KEEP_ALIVE_SET_ENABLE(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define KEEP_ALIVE_SET_ENABLE_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define KEEP_ALIVE_GET_ADOPT_USER_SETTING(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1)
+#define KEEP_ALIVE_SET_ADOPT_USER_SETTING(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define KEEP_ALIVE_SET_ADOPT_USER_SETTING_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define KEEP_ALIVE_GET_PKT_TYPE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 10, 1)
+#define KEEP_ALIVE_SET_PKT_TYPE(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value)
+#define KEEP_ALIVE_SET_PKT_TYPE_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value)
+#define KEEP_ALIVE_GET_KEEP_ALIVE_CHECK_PERIOD(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)
+#define KEEP_ALIVE_SET_KEEP_ALIVE_CHECK_PERIOD(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define KEEP_ALIVE_SET_KEEP_ALIVE_CHECK_PERIOD_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define DISCONNECT_DECISION_GET_CMD_ID(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define DISCONNECT_DECISION_SET_CMD_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define DISCONNECT_DECISION_SET_CMD_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define DISCONNECT_DECISION_GET_CLASS(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define DISCONNECT_DECISION_SET_CLASS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define DISCONNECT_DECISION_SET_CLASS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define DISCONNECT_DECISION_GET_ENABLE(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1)
+#define DISCONNECT_DECISION_SET_ENABLE(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define DISCONNECT_DECISION_SET_ENABLE_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define DISCONNECT_DECISION_GET_ADOPT_USER_SETTING(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1)
+#define DISCONNECT_DECISION_SET_ADOPT_USER_SETTING(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define DISCONNECT_DECISION_SET_ADOPT_USER_SETTING_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_EN(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 10, 1)
+#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_EN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value)
+#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_EN_NO_CLR(h2c_pkt, \
+ value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value)
+#define DISCONNECT_DECISION_GET_DISCONNECT_EN(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 11, 1)
+#define DISCONNECT_DECISION_SET_DISCONNECT_EN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 11, 1, value)
+#define DISCONNECT_DECISION_SET_DISCONNECT_EN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 11, 1, value)
+#define DISCONNECT_DECISION_GET_DISCON_DECISION_CHECK_PERIOD(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)
+#define DISCONNECT_DECISION_SET_DISCON_DECISION_CHECK_PERIOD(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define DISCONNECT_DECISION_SET_DISCON_DECISION_CHECK_PERIOD_NO_CLR(h2c_pkt, \
+ value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define DISCONNECT_DECISION_GET_TRY_PKT_NUM(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)
+#define DISCONNECT_DECISION_SET_TRY_PKT_NUM(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define DISCONNECT_DECISION_SET_TRY_PKT_NUM_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_LIMIT(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8)
+#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_LIMIT(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_LIMIT_NO_CLR(h2c_pkt, \
+ value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define AP_OFFLOAD_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define AP_OFFLOAD_SET_CMD_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define AP_OFFLOAD_SET_CMD_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define AP_OFFLOAD_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define AP_OFFLOAD_SET_CLASS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define AP_OFFLOAD_SET_CLASS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define AP_OFFLOAD_GET_ON(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1)
+#define AP_OFFLOAD_SET_ON(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define AP_OFFLOAD_SET_ON_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define AP_OFFLOAD_GET_CFG_MIFI_PLATFORM(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1)
+#define AP_OFFLOAD_SET_CFG_MIFI_PLATFORM(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define AP_OFFLOAD_SET_CFG_MIFI_PLATFORM_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define AP_OFFLOAD_GET_LINKED(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 10, 1)
+#define AP_OFFLOAD_SET_LINKED(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value)
+#define AP_OFFLOAD_SET_LINKED_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value)
+#define AP_OFFLOAD_GET_EN_AUTO_WAKE(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 11, 1)
+#define AP_OFFLOAD_SET_EN_AUTO_WAKE(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 11, 1, value)
+#define AP_OFFLOAD_SET_EN_AUTO_WAKE_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 11, 1, value)
+#define AP_OFFLOAD_GET_WAKE_FLAG(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 12, 1)
+#define AP_OFFLOAD_SET_WAKE_FLAG(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 12, 1, value)
+#define AP_OFFLOAD_SET_WAKE_FLAG_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 12, 1, value)
+#define AP_OFFLOAD_GET_HIDDEN_ROOT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 1)
+#define AP_OFFLOAD_SET_HIDDEN_ROOT(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 1, value)
+#define AP_OFFLOAD_SET_HIDDEN_ROOT_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 1, value)
+#define AP_OFFLOAD_GET_HIDDEN_VAP1(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 17, 1)
+#define AP_OFFLOAD_SET_HIDDEN_VAP1(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 17, 1, value)
+#define AP_OFFLOAD_SET_HIDDEN_VAP1_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 17, 1, value)
+#define AP_OFFLOAD_GET_HIDDEN_VAP2(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 18, 1)
+#define AP_OFFLOAD_SET_HIDDEN_VAP2(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 18, 1, value)
+#define AP_OFFLOAD_SET_HIDDEN_VAP2_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 18, 1, value)
+#define AP_OFFLOAD_GET_HIDDEN_VAP3(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 19, 1)
+#define AP_OFFLOAD_SET_HIDDEN_VAP3(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 19, 1, value)
+#define AP_OFFLOAD_SET_HIDDEN_VAP3_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 19, 1, value)
+#define AP_OFFLOAD_GET_HIDDEN_VAP4(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 20, 1)
+#define AP_OFFLOAD_SET_HIDDEN_VAP4(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 20, 1, value)
+#define AP_OFFLOAD_SET_HIDDEN_VAP4_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 20, 1, value)
+#define AP_OFFLOAD_GET_DENYANY_ROOT(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 24, 1)
+#define AP_OFFLOAD_SET_DENYANY_ROOT(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 1, value)
+#define AP_OFFLOAD_SET_DENYANY_ROOT_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 1, value)
+#define AP_OFFLOAD_GET_DENYANY_VAP1(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 25, 1)
+#define AP_OFFLOAD_SET_DENYANY_VAP1(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 25, 1, value)
+#define AP_OFFLOAD_SET_DENYANY_VAP1_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 25, 1, value)
+#define AP_OFFLOAD_GET_DENYANY_VAP2(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 26, 1)
+#define AP_OFFLOAD_SET_DENYANY_VAP2(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 26, 1, value)
+#define AP_OFFLOAD_SET_DENYANY_VAP2_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 26, 1, value)
+#define AP_OFFLOAD_GET_DENYANY_VAP3(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 27, 1)
+#define AP_OFFLOAD_SET_DENYANY_VAP3(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 27, 1, value)
+#define AP_OFFLOAD_SET_DENYANY_VAP3_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 27, 1, value)
+#define AP_OFFLOAD_GET_DENYANY_VAP4(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 28, 1)
+#define AP_OFFLOAD_SET_DENYANY_VAP4(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 28, 1, value)
+#define AP_OFFLOAD_SET_DENYANY_VAP4_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 28, 1, value)
+#define AP_OFFLOAD_GET_WAIT_TBTT_CNT(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8)
+#define AP_OFFLOAD_SET_WAIT_TBTT_CNT(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define AP_OFFLOAD_SET_WAIT_TBTT_CNT_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define AP_OFFLOAD_GET_WAKE_TIMEOUT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8)
+#define AP_OFFLOAD_SET_WAKE_TIMEOUT(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define AP_OFFLOAD_SET_WAKE_TIMEOUT_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define AP_OFFLOAD_GET_LEN_IV_PAIR(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 16, 8)
+#define AP_OFFLOAD_SET_LEN_IV_PAIR(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 8, value)
+#define AP_OFFLOAD_SET_LEN_IV_PAIR_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 8, value)
+#define AP_OFFLOAD_GET_LEN_IV_GRP(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 24, 8)
+#define AP_OFFLOAD_SET_LEN_IV_GRP(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 24, 8, value)
+#define AP_OFFLOAD_SET_LEN_IV_GRP_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 24, 8, value)
+#define BCN_RSVDPAGE_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define BCN_RSVDPAGE_SET_CMD_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define BCN_RSVDPAGE_SET_CMD_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define BCN_RSVDPAGE_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define BCN_RSVDPAGE_SET_CLASS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define BCN_RSVDPAGE_SET_CLASS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define BCN_RSVDPAGE_GET_LOC_ROOT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define BCN_RSVDPAGE_SET_LOC_ROOT(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define BCN_RSVDPAGE_SET_LOC_ROOT_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define BCN_RSVDPAGE_GET_LOC_VAP1(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)
+#define BCN_RSVDPAGE_SET_LOC_VAP1(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define BCN_RSVDPAGE_SET_LOC_VAP1_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define BCN_RSVDPAGE_GET_LOC_VAP2(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)
+#define BCN_RSVDPAGE_SET_LOC_VAP2(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define BCN_RSVDPAGE_SET_LOC_VAP2_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define BCN_RSVDPAGE_GET_LOC_VAP3(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8)
+#define BCN_RSVDPAGE_SET_LOC_VAP3(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define BCN_RSVDPAGE_SET_LOC_VAP3_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define BCN_RSVDPAGE_GET_LOC_VAP4(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8)
+#define BCN_RSVDPAGE_SET_LOC_VAP4(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define BCN_RSVDPAGE_SET_LOC_VAP4_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define PROBE_RSP_RSVDPAGE_GET_CMD_ID(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define PROBE_RSP_RSVDPAGE_SET_CMD_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define PROBE_RSP_RSVDPAGE_SET_CMD_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define PROBE_RSP_RSVDPAGE_GET_CLASS(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define PROBE_RSP_RSVDPAGE_SET_CLASS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define PROBE_RSP_RSVDPAGE_SET_CLASS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define PROBE_RSP_RSVDPAGE_GET_LOC_ROOT(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define PROBE_RSP_RSVDPAGE_SET_LOC_ROOT(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define PROBE_RSP_RSVDPAGE_SET_LOC_ROOT_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP1(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)
+#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP1(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP1_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP2(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)
+#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP2(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP2_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP3(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8)
+#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP3(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP3_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP4(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8)
+#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP4(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP4_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define SINGLE_CHANNELSWITCH_GET_CMD_ID(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define SINGLE_CHANNELSWITCH_SET_CMD_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define SINGLE_CHANNELSWITCH_SET_CMD_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define SINGLE_CHANNELSWITCH_GET_CLASS(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define SINGLE_CHANNELSWITCH_SET_CLASS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define SINGLE_CHANNELSWITCH_SET_CLASS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define SINGLE_CHANNELSWITCH_GET_CHANNEL_NUM(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define SINGLE_CHANNELSWITCH_SET_CHANNEL_NUM(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define SINGLE_CHANNELSWITCH_SET_CHANNEL_NUM_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define SINGLE_CHANNELSWITCH_GET_BW(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 16, 2)
+#define SINGLE_CHANNELSWITCH_SET_BW(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 2, value)
+#define SINGLE_CHANNELSWITCH_SET_BW_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 2, value)
+#define SINGLE_CHANNELSWITCH_GET_BW40SC(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 18, 3)
+#define SINGLE_CHANNELSWITCH_SET_BW40SC(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 18, 3, value)
+#define SINGLE_CHANNELSWITCH_SET_BW40SC_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 18, 3, value)
+#define SINGLE_CHANNELSWITCH_GET_BW80SC(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 21, 3)
+#define SINGLE_CHANNELSWITCH_SET_BW80SC(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 21, 3, value)
+#define SINGLE_CHANNELSWITCH_SET_BW80SC_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 21, 3, value)
+#define SINGLE_CHANNELSWITCH_GET_RFE_TYPE(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 24, 4)
+#define SINGLE_CHANNELSWITCH_SET_RFE_TYPE(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 4, value)
+#define SINGLE_CHANNELSWITCH_SET_RFE_TYPE_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 4, value)
+#define SINGLE_CHANNELSWITCH_V2_GET_CMD_ID(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define SINGLE_CHANNELSWITCH_V2_SET_CMD_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define SINGLE_CHANNELSWITCH_V2_SET_CMD_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define SINGLE_CHANNELSWITCH_V2_GET_CLASS(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define SINGLE_CHANNELSWITCH_V2_SET_CLASS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define SINGLE_CHANNELSWITCH_V2_SET_CLASS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define SINGLE_CHANNELSWITCH_V2_GET_CENTRAL_CH(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define SINGLE_CHANNELSWITCH_V2_SET_CENTRAL_CH(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define SINGLE_CHANNELSWITCH_V2_SET_CENTRAL_CH_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define SINGLE_CHANNELSWITCH_V2_GET_PRIMARY_CH_IDX(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 16, 4)
+#define SINGLE_CHANNELSWITCH_V2_SET_PRIMARY_CH_IDX(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 4, value)
+#define SINGLE_CHANNELSWITCH_V2_SET_PRIMARY_CH_IDX_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 4, value)
+#define SINGLE_CHANNELSWITCH_V2_GET_BW(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 20, 4)
+#define SINGLE_CHANNELSWITCH_V2_SET_BW(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 20, 4, value)
+#define SINGLE_CHANNELSWITCH_V2_SET_BW_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 20, 4, value)
+#define SET_PWR_MODE_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define SET_PWR_MODE_SET_CMD_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define SET_PWR_MODE_SET_CMD_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define SET_PWR_MODE_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define SET_PWR_MODE_SET_CLASS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define SET_PWR_MODE_SET_CLASS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define SET_PWR_MODE_GET_MODE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 7)
+#define SET_PWR_MODE_SET_MODE(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 7, value)
+#define SET_PWR_MODE_SET_MODE_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 7, value)
+#define SET_PWR_MODE_GET_CLK_REQUEST(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 15, 1)
+#define SET_PWR_MODE_SET_CLK_REQUEST(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 15, 1, value)
+#define SET_PWR_MODE_SET_CLK_REQUEST_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 15, 1, value)
+#define SET_PWR_MODE_GET_RLBM(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 4)
+#define SET_PWR_MODE_SET_RLBM(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 4, value)
+#define SET_PWR_MODE_SET_RLBM_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 4, value)
+#define SET_PWR_MODE_GET_SMART_PS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 20, 4)
+#define SET_PWR_MODE_SET_SMART_PS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 20, 4, value)
+#define SET_PWR_MODE_SET_SMART_PS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 20, 4, value)
+#define SET_PWR_MODE_GET_AWAKE_INTERVAL(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)
+#define SET_PWR_MODE_SET_AWAKE_INTERVAL(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define SET_PWR_MODE_SET_AWAKE_INTERVAL_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define SET_PWR_MODE_GET_B_ALL_QUEUE_UAPSD(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 0, 1)
+#define SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 1, value)
+#define SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 1, value)
+#define SET_PWR_MODE_GET_BCN_EARLY_RPT(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 2, 1)
+#define SET_PWR_MODE_SET_BCN_EARLY_RPT(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 2, 1, value)
+#define SET_PWR_MODE_SET_BCN_EARLY_RPT_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 2, 1, value)
+#define SET_PWR_MODE_GET_PORT_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 5, 3)
+#define SET_PWR_MODE_SET_PORT_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 5, 3, value)
+#define SET_PWR_MODE_SET_PORT_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 5, 3, value)
+#define SET_PWR_MODE_GET_PWR_STATE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8)
+#define SET_PWR_MODE_SET_PWR_STATE(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define SET_PWR_MODE_SET_PWR_STATE_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define SET_PWR_MODE_GET_LOW_POWER_RX_BCN(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 16, 1)
+#define SET_PWR_MODE_SET_LOW_POWER_RX_BCN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 1, value)
+#define SET_PWR_MODE_SET_LOW_POWER_RX_BCN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 1, value)
+#define SET_PWR_MODE_GET_ANT_AUTO_SWITCH(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 17, 1)
+#define SET_PWR_MODE_SET_ANT_AUTO_SWITCH(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 17, 1, value)
+#define SET_PWR_MODE_SET_ANT_AUTO_SWITCH_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 17, 1, value)
+#define SET_PWR_MODE_GET_PS_ALLOW_BT_HIGH_PRIORITY(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 18, 1)
+#define SET_PWR_MODE_SET_PS_ALLOW_BT_HIGH_PRIORITY(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 18, 1, value)
+#define SET_PWR_MODE_SET_PS_ALLOW_BT_HIGH_PRIORITY_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 18, 1, value)
+#define SET_PWR_MODE_GET_PROTECT_BCN(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 19, 1)
+#define SET_PWR_MODE_SET_PROTECT_BCN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 19, 1, value)
+#define SET_PWR_MODE_SET_PROTECT_BCN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 19, 1, value)
+#define SET_PWR_MODE_GET_SILENCE_PERIOD(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 20, 1)
+#define SET_PWR_MODE_SET_SILENCE_PERIOD(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 20, 1, value)
+#define SET_PWR_MODE_SET_SILENCE_PERIOD_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 20, 1, value)
+#define SET_PWR_MODE_GET_FAST_BT_CONNECT(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 21, 1)
+#define SET_PWR_MODE_SET_FAST_BT_CONNECT(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 21, 1, value)
+#define SET_PWR_MODE_SET_FAST_BT_CONNECT_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 21, 1, value)
+#define SET_PWR_MODE_GET_TWO_ANTENNA_EN(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 22, 1)
+#define SET_PWR_MODE_SET_TWO_ANTENNA_EN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 22, 1, value)
+#define SET_PWR_MODE_SET_TWO_ANTENNA_EN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 22, 1, value)
+#define SET_PWR_MODE_GET_ADOPT_USER_SETTING(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 24, 1)
+#define SET_PWR_MODE_SET_ADOPT_USER_SETTING(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 24, 1, value)
+#define SET_PWR_MODE_SET_ADOPT_USER_SETTING_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 24, 1, value)
+#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 25, 3)
+#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 25, 3, value)
+#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 25, 3, value)
+#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT2(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 28, 4)
+#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT2(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 28, 4, value)
+#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT2_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 28, 4, value)
+#define PS_TUNING_PARA_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define PS_TUNING_PARA_SET_CMD_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define PS_TUNING_PARA_SET_CMD_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define PS_TUNING_PARA_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define PS_TUNING_PARA_SET_CLASS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define PS_TUNING_PARA_SET_CLASS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define PS_TUNING_PARA_GET_BCN_TO_LIMIT(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 8, 7)
+#define PS_TUNING_PARA_SET_BCN_TO_LIMIT(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 7, value)
+#define PS_TUNING_PARA_SET_BCN_TO_LIMIT_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 7, value)
+#define PS_TUNING_PARA_GET_DTIM_TIME_OUT(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 15, 1)
+#define PS_TUNING_PARA_SET_DTIM_TIME_OUT(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 15, 1, value)
+#define PS_TUNING_PARA_SET_DTIM_TIME_OUT_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 15, 1, value)
+#define PS_TUNING_PARA_GET_PS_TIME_OUT(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 16, 4)
+#define PS_TUNING_PARA_SET_PS_TIME_OUT(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 4, value)
+#define PS_TUNING_PARA_SET_PS_TIME_OUT_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 4, value)
+#define PS_TUNING_PARA_GET_ADOPT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)
+#define PS_TUNING_PARA_SET_ADOPT(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define PS_TUNING_PARA_SET_ADOPT_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define PS_TUNING_PARA_II_GET_CMD_ID(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define PS_TUNING_PARA_II_SET_CMD_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define PS_TUNING_PARA_II_SET_CMD_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define PS_TUNING_PARA_II_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define PS_TUNING_PARA_II_SET_CLASS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define PS_TUNING_PARA_II_SET_CLASS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define PS_TUNING_PARA_II_GET_BCN_TO_PERIOD(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 8, 7)
+#define PS_TUNING_PARA_II_SET_BCN_TO_PERIOD(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 7, value)
+#define PS_TUNING_PARA_II_SET_BCN_TO_PERIOD_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 7, value)
+#define PS_TUNING_PARA_II_GET_ADOPT(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 15, 1)
+#define PS_TUNING_PARA_II_SET_ADOPT(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 15, 1, value)
+#define PS_TUNING_PARA_II_SET_ADOPT_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 15, 1, value)
+#define PS_TUNING_PARA_II_GET_DRV_EARLY_IVL(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)
+#define PS_TUNING_PARA_II_SET_DRV_EARLY_IVL(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define PS_TUNING_PARA_II_SET_DRV_EARLY_IVL_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define PS_LPS_PARA_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define PS_LPS_PARA_SET_CMD_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define PS_LPS_PARA_SET_CMD_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define PS_LPS_PARA_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define PS_LPS_PARA_SET_CLASS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define PS_LPS_PARA_SET_CLASS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define PS_LPS_PARA_GET_LPS_CONTROL(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define PS_LPS_PARA_SET_LPS_CONTROL(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define PS_LPS_PARA_SET_LPS_CONTROL_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define P2P_PS_OFFLOAD_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define P2P_PS_OFFLOAD_SET_CMD_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define P2P_PS_OFFLOAD_SET_CMD_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define P2P_PS_OFFLOAD_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define P2P_PS_OFFLOAD_SET_CLASS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define P2P_PS_OFFLOAD_SET_CLASS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define P2P_PS_OFFLOAD_GET_OFFLOAD_EN(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1)
+#define P2P_PS_OFFLOAD_SET_OFFLOAD_EN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define P2P_PS_OFFLOAD_SET_OFFLOAD_EN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define P2P_PS_OFFLOAD_GET_ROLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1)
+#define P2P_PS_OFFLOAD_SET_ROLE(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define P2P_PS_OFFLOAD_SET_ROLE_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define P2P_PS_OFFLOAD_GET_CTWINDOW_EN(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 10, 1)
+#define P2P_PS_OFFLOAD_SET_CTWINDOW_EN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value)
+#define P2P_PS_OFFLOAD_SET_CTWINDOW_EN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value)
+#define P2P_PS_OFFLOAD_GET_NOA0_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 11, 1)
+#define P2P_PS_OFFLOAD_SET_NOA0_EN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 11, 1, value)
+#define P2P_PS_OFFLOAD_SET_NOA0_EN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 11, 1, value)
+#define P2P_PS_OFFLOAD_GET_NOA1_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 12, 1)
+#define P2P_PS_OFFLOAD_SET_NOA1_EN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 12, 1, value)
+#define P2P_PS_OFFLOAD_SET_NOA1_EN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 12, 1, value)
+#define P2P_PS_OFFLOAD_GET_ALL_STA_SLEEP(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 13, 1)
+#define P2P_PS_OFFLOAD_SET_ALL_STA_SLEEP(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 13, 1, value)
+#define P2P_PS_OFFLOAD_SET_ALL_STA_SLEEP_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 13, 1, value)
+#define P2P_PS_OFFLOAD_GET_DISCOVERY(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 14, 1)
+#define P2P_PS_OFFLOAD_SET_DISCOVERY(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 14, 1, value)
+#define P2P_PS_OFFLOAD_SET_DISCOVERY_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 14, 1, value)
+#define PS_SCAN_EN_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define PS_SCAN_EN_SET_CMD_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define PS_SCAN_EN_SET_CMD_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define PS_SCAN_EN_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define PS_SCAN_EN_SET_CLASS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define PS_SCAN_EN_SET_CLASS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define PS_SCAN_EN_GET_ENABLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1)
+#define PS_SCAN_EN_SET_ENABLE(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define PS_SCAN_EN_SET_ENABLE_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define SAP_PS_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define SAP_PS_SET_CMD_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define SAP_PS_SET_CMD_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define SAP_PS_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define SAP_PS_SET_CLASS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define SAP_PS_SET_CLASS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define SAP_PS_GET_ENABLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1)
+#define SAP_PS_SET_ENABLE(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define SAP_PS_SET_ENABLE_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define SAP_PS_GET_EN_PS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1)
+#define SAP_PS_SET_EN_PS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define SAP_PS_SET_EN_PS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define SAP_PS_GET_EN_LP_RX(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 10, 1)
+#define SAP_PS_SET_EN_LP_RX(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value)
+#define SAP_PS_SET_EN_LP_RX_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value)
+#define SAP_PS_GET_MANUAL_32K(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 11, 1)
+#define SAP_PS_SET_MANUAL_32K(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 11, 1, value)
+#define SAP_PS_SET_MANUAL_32K_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 11, 1, value)
+#define SAP_PS_GET_DURATION(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)
+#define SAP_PS_SET_DURATION(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define SAP_PS_SET_DURATION_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define INACTIVE_PS_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define INACTIVE_PS_SET_CMD_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define INACTIVE_PS_SET_CMD_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define INACTIVE_PS_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define INACTIVE_PS_SET_CLASS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define INACTIVE_PS_SET_CLASS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define INACTIVE_PS_GET_ENABLE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1)
+#define INACTIVE_PS_SET_ENABLE(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define INACTIVE_PS_SET_ENABLE_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define INACTIVE_PS_GET_IGNORE_PS_CONDITION(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1)
+#define INACTIVE_PS_SET_IGNORE_PS_CONDITION(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define INACTIVE_PS_SET_IGNORE_PS_CONDITION_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define INACTIVE_PS_GET_FREQUENCY(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)
+#define INACTIVE_PS_SET_FREQUENCY(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define INACTIVE_PS_SET_FREQUENCY_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define INACTIVE_PS_GET_DURATION(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)
+#define INACTIVE_PS_SET_DURATION(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define INACTIVE_PS_SET_DURATION_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define MACID_CFG_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define MACID_CFG_SET_CMD_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define MACID_CFG_SET_CMD_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define MACID_CFG_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define MACID_CFG_SET_CLASS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define MACID_CFG_SET_CLASS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define MACID_CFG_GET_MAC_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define MACID_CFG_SET_MAC_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define MACID_CFG_SET_MAC_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define MACID_CFG_GET_RATE_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 5)
+#define MACID_CFG_SET_RATE_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 5, value)
+#define MACID_CFG_SET_RATE_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 5, value)
+#define MACID_CFG_GET_INIT_RATE_LV(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 21, 2)
+#define MACID_CFG_SET_INIT_RATE_LV(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 21, 2, value)
+#define MACID_CFG_SET_INIT_RATE_LV_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 21, 2, value)
+#define MACID_CFG_GET_SGI(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 23, 1)
+#define MACID_CFG_SET_SGI(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 23, 1, value)
+#define MACID_CFG_SET_SGI_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 23, 1, value)
+#define MACID_CFG_GET_BW(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 2)
+#define MACID_CFG_SET_BW(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 2, value)
+#define MACID_CFG_SET_BW_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 2, value)
+#define MACID_CFG_GET_LDPC_CAP(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 26, 1)
+#define MACID_CFG_SET_LDPC_CAP(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 26, 1, value)
+#define MACID_CFG_SET_LDPC_CAP_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 26, 1, value)
+#define MACID_CFG_GET_NO_UPDATE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 27, 1)
+#define MACID_CFG_SET_NO_UPDATE(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 27, 1, value)
+#define MACID_CFG_SET_NO_UPDATE_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 27, 1, value)
+#define MACID_CFG_GET_WHT_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 28, 2)
+#define MACID_CFG_SET_WHT_EN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 28, 2, value)
+#define MACID_CFG_SET_WHT_EN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 28, 2, value)
+#define MACID_CFG_GET_DISPT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 30, 1)
+#define MACID_CFG_SET_DISPT(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 30, 1, value)
+#define MACID_CFG_SET_DISPT_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 30, 1, value)
+#define MACID_CFG_GET_DISRA(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 31, 1)
+#define MACID_CFG_SET_DISRA(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 31, 1, value)
+#define MACID_CFG_SET_DISRA_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 31, 1, value)
+#define MACID_CFG_GET_RATE_MASK7_0(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8)
+#define MACID_CFG_SET_RATE_MASK7_0(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define MACID_CFG_SET_RATE_MASK7_0_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define MACID_CFG_GET_RATE_MASK15_8(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8)
+#define MACID_CFG_SET_RATE_MASK15_8(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define MACID_CFG_SET_RATE_MASK15_8_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define MACID_CFG_GET_RATE_MASK23_16(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 16, 8)
+#define MACID_CFG_SET_RATE_MASK23_16(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 8, value)
+#define MACID_CFG_SET_RATE_MASK23_16_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 8, value)
+#define MACID_CFG_GET_RATE_MASK31_24(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 24, 8)
+#define MACID_CFG_SET_RATE_MASK31_24(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 24, 8, value)
+#define MACID_CFG_SET_RATE_MASK31_24_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 24, 8, value)
+#define TXBF_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define TXBF_SET_CMD_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define TXBF_SET_CMD_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define TXBF_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define TXBF_SET_CLASS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define TXBF_SET_CLASS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define TXBF_GET_NDPA0_HEAD_PAGE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define TXBF_SET_NDPA0_HEAD_PAGE(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define TXBF_SET_NDPA0_HEAD_PAGE_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define TXBF_GET_NDPA1_HEAD_PAGE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)
+#define TXBF_SET_NDPA1_HEAD_PAGE(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define TXBF_SET_NDPA1_HEAD_PAGE_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define TXBF_GET_PERIOD_0(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)
+#define TXBF_SET_PERIOD_0(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define TXBF_SET_PERIOD_0_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define RSSI_SETTING_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define RSSI_SETTING_SET_CMD_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define RSSI_SETTING_SET_CMD_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define RSSI_SETTING_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define RSSI_SETTING_SET_CLASS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define RSSI_SETTING_SET_CLASS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define RSSI_SETTING_GET_MAC_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define RSSI_SETTING_SET_MAC_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define RSSI_SETTING_SET_MAC_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define RSSI_SETTING_GET_RSSI(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 7)
+#define RSSI_SETTING_SET_RSSI(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 7, value)
+#define RSSI_SETTING_SET_RSSI_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 7, value)
+#define RSSI_SETTING_GET_RA_INFO(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8)
+#define RSSI_SETTING_SET_RA_INFO(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define RSSI_SETTING_SET_RA_INFO_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define AP_REQ_TXRPT_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define AP_REQ_TXRPT_SET_CMD_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define AP_REQ_TXRPT_SET_CMD_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define AP_REQ_TXRPT_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define AP_REQ_TXRPT_SET_CLASS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define AP_REQ_TXRPT_SET_CLASS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define AP_REQ_TXRPT_GET_STA1_MACID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define AP_REQ_TXRPT_SET_STA1_MACID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define AP_REQ_TXRPT_SET_STA1_MACID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define AP_REQ_TXRPT_GET_STA2_MACID(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)
+#define AP_REQ_TXRPT_SET_STA2_MACID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define AP_REQ_TXRPT_SET_STA2_MACID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define AP_REQ_TXRPT_GET_RTY_OK_TOTAL(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 24, 1)
+#define AP_REQ_TXRPT_SET_RTY_OK_TOTAL(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 1, value)
+#define AP_REQ_TXRPT_SET_RTY_OK_TOTAL_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 1, value)
+#define AP_REQ_TXRPT_GET_RTY_CNT_MACID(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 25, 1)
+#define AP_REQ_TXRPT_SET_RTY_CNT_MACID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 25, 1, value)
+#define AP_REQ_TXRPT_SET_RTY_CNT_MACID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 25, 1, value)
+#define INIT_RATE_COLLECTION_GET_CMD_ID(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define INIT_RATE_COLLECTION_SET_CMD_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define INIT_RATE_COLLECTION_SET_CMD_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define INIT_RATE_COLLECTION_GET_CLASS(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define INIT_RATE_COLLECTION_SET_CLASS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define INIT_RATE_COLLECTION_SET_CLASS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define INIT_RATE_COLLECTION_GET_STA1_MACID(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define INIT_RATE_COLLECTION_SET_STA1_MACID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define INIT_RATE_COLLECTION_SET_STA1_MACID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define INIT_RATE_COLLECTION_GET_STA2_MACID(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)
+#define INIT_RATE_COLLECTION_SET_STA2_MACID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define INIT_RATE_COLLECTION_SET_STA2_MACID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define INIT_RATE_COLLECTION_GET_STA3_MACID(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)
+#define INIT_RATE_COLLECTION_SET_STA3_MACID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define INIT_RATE_COLLECTION_SET_STA3_MACID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define INIT_RATE_COLLECTION_GET_STA4_MACID(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8)
+#define INIT_RATE_COLLECTION_SET_STA4_MACID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define INIT_RATE_COLLECTION_SET_STA4_MACID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define INIT_RATE_COLLECTION_GET_STA5_MACID(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8)
+#define INIT_RATE_COLLECTION_SET_STA5_MACID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define INIT_RATE_COLLECTION_SET_STA5_MACID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define INIT_RATE_COLLECTION_GET_STA6_MACID(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 16, 8)
+#define INIT_RATE_COLLECTION_SET_STA6_MACID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 8, value)
+#define INIT_RATE_COLLECTION_SET_STA6_MACID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 8, value)
+#define INIT_RATE_COLLECTION_GET_STA7_MACID(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 24, 8)
+#define INIT_RATE_COLLECTION_SET_STA7_MACID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 24, 8, value)
+#define INIT_RATE_COLLECTION_SET_STA7_MACID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 24, 8, value)
+#define IQK_OFFLOAD_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define IQK_OFFLOAD_SET_CMD_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define IQK_OFFLOAD_SET_CMD_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define IQK_OFFLOAD_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define IQK_OFFLOAD_SET_CLASS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define IQK_OFFLOAD_SET_CLASS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define IQK_OFFLOAD_GET_CHANNEL(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define IQK_OFFLOAD_SET_CHANNEL(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define IQK_OFFLOAD_SET_CHANNEL_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define IQK_OFFLOAD_GET_BWBAND(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)
+#define IQK_OFFLOAD_SET_BWBAND(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define IQK_OFFLOAD_SET_BWBAND_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define IQK_OFFLOAD_GET_EXTPALNA(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)
+#define IQK_OFFLOAD_SET_EXTPALNA(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define IQK_OFFLOAD_SET_EXTPALNA_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define MACID_CFG_3SS_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define MACID_CFG_3SS_SET_CMD_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define MACID_CFG_3SS_SET_CMD_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define MACID_CFG_3SS_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define MACID_CFG_3SS_SET_CLASS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define MACID_CFG_3SS_SET_CLASS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define MACID_CFG_3SS_GET_MACID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define MACID_CFG_3SS_SET_MACID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define MACID_CFG_3SS_SET_MACID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define MACID_CFG_3SS_GET_RATE_MASK_39_32(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8)
+#define MACID_CFG_3SS_SET_RATE_MASK_39_32(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define MACID_CFG_3SS_SET_RATE_MASK_39_32_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define MACID_CFG_3SS_GET_RATE_MASK_47_40(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8)
+#define MACID_CFG_3SS_SET_RATE_MASK_47_40(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define MACID_CFG_3SS_SET_RATE_MASK_47_40_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define RA_PARA_ADJUST_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define RA_PARA_ADJUST_SET_CMD_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define RA_PARA_ADJUST_SET_CMD_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define RA_PARA_ADJUST_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define RA_PARA_ADJUST_SET_CLASS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define RA_PARA_ADJUST_SET_CLASS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define RA_PARA_ADJUST_GET_MAC_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define RA_PARA_ADJUST_SET_MAC_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define RA_PARA_ADJUST_SET_MAC_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define RA_PARA_ADJUST_GET_PARAMETER_INDEX(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)
+#define RA_PARA_ADJUST_SET_PARAMETER_INDEX(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define RA_PARA_ADJUST_SET_PARAMETER_INDEX_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define RA_PARA_ADJUST_GET_RATE_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)
+#define RA_PARA_ADJUST_SET_RATE_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define RA_PARA_ADJUST_SET_RATE_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define RA_PARA_ADJUST_GET_VALUE_BYTE0(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8)
+#define RA_PARA_ADJUST_SET_VALUE_BYTE0(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define RA_PARA_ADJUST_SET_VALUE_BYTE0_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define RA_PARA_ADJUST_GET_VALUE_BYTE1(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8)
+#define RA_PARA_ADJUST_SET_VALUE_BYTE1(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define RA_PARA_ADJUST_SET_VALUE_BYTE1_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define RA_PARA_ADJUST_GET_ASK_FW_FOR_FW_PARA(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 16, 8)
+#define RA_PARA_ADJUST_SET_ASK_FW_FOR_FW_PARA(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 8, value)
+#define RA_PARA_ADJUST_SET_ASK_FW_FOR_FW_PARA_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 8, value)
+#define WWLAN_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define WWLAN_SET_CMD_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define WWLAN_SET_CMD_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define WWLAN_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define WWLAN_SET_CLASS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define WWLAN_SET_CLASS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define WWLAN_GET_FUNC_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1)
+#define WWLAN_SET_FUNC_EN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define WWLAN_SET_FUNC_EN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define WWLAN_GET_PATTERM_MAT_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1)
+#define WWLAN_SET_PATTERM_MAT_EN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define WWLAN_SET_PATTERM_MAT_EN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define WWLAN_GET_MAGIC_PKT_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 10, 1)
+#define WWLAN_SET_MAGIC_PKT_EN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value)
+#define WWLAN_SET_MAGIC_PKT_EN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value)
+#define WWLAN_GET_UNICAST_WAKEUP_EN(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 11, 1)
+#define WWLAN_SET_UNICAST_WAKEUP_EN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 11, 1, value)
+#define WWLAN_SET_UNICAST_WAKEUP_EN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 11, 1, value)
+#define WWLAN_GET_ALL_PKT_DROP(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 12, 1)
+#define WWLAN_SET_ALL_PKT_DROP(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 12, 1, value)
+#define WWLAN_SET_ALL_PKT_DROP_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 12, 1, value)
+#define WWLAN_GET_GPIO_ACTIVE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 13, 1)
+#define WWLAN_SET_GPIO_ACTIVE(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 13, 1, value)
+#define WWLAN_SET_GPIO_ACTIVE_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 13, 1, value)
+#define WWLAN_GET_REKEY_WAKEUP_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 14, 1)
+#define WWLAN_SET_REKEY_WAKEUP_EN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 14, 1, value)
+#define WWLAN_SET_REKEY_WAKEUP_EN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 14, 1, value)
+#define WWLAN_GET_DEAUTH_WAKEUP_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 15, 1)
+#define WWLAN_SET_DEAUTH_WAKEUP_EN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 15, 1, value)
+#define WWLAN_SET_DEAUTH_WAKEUP_EN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 15, 1, value)
+#define WWLAN_GET_GPIO_NUM(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 16, 7)
+#define WWLAN_SET_GPIO_NUM(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 7, value)
+#define WWLAN_SET_GPIO_NUM_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 7, value)
+#define WWLAN_GET_DATAPIN_WAKEUP_EN(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 23, 1)
+#define WWLAN_SET_DATAPIN_WAKEUP_EN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 23, 1, value)
+#define WWLAN_SET_DATAPIN_WAKEUP_EN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 23, 1, value)
+#define WWLAN_GET_GPIO_DURATION(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)
+#define WWLAN_SET_GPIO_DURATION(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define WWLAN_SET_GPIO_DURATION_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define WWLAN_GET_GPIO_PLUS_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 0, 1)
+#define WWLAN_SET_GPIO_PLUS_EN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 1, value)
+#define WWLAN_SET_GPIO_PLUS_EN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 1, value)
+#define WWLAN_GET_GPIO_PULSE_COUNT(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 1, 7)
+#define WWLAN_SET_GPIO_PULSE_COUNT(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 1, 7, value)
+#define WWLAN_SET_GPIO_PULSE_COUNT_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 1, 7, value)
+#define WWLAN_GET_DISABLE_UPHY(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 8, 1)
+#define WWLAN_SET_DISABLE_UPHY(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 1, value)
+#define WWLAN_SET_DISABLE_UPHY_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 1, value)
+#define WWLAN_GET_HST2DEV_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 9, 1)
+#define WWLAN_SET_HST2DEV_EN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 9, 1, value)
+#define WWLAN_SET_HST2DEV_EN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 9, 1, value)
+#define WWLAN_GET_GPIO_DURATION_MS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X04, 10, 1)
+#define WWLAN_SET_GPIO_DURATION_MS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 10, 1, value)
+#define WWLAN_SET_GPIO_DURATION_MS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 10, 1, value)
+#define REMOTE_WAKE_CTRL_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define REMOTE_WAKE_CTRL_SET_CMD_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define REMOTE_WAKE_CTRL_SET_CMD_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define REMOTE_WAKE_CTRL_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define REMOTE_WAKE_CTRL_SET_CLASS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define REMOTE_WAKE_CTRL_SET_CLASS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define REMOTE_WAKE_CTRL_GET_REMOTE_WAKE_CTRL_EN(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1)
+#define REMOTE_WAKE_CTRL_SET_REMOTE_WAKE_CTRL_EN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define REMOTE_WAKE_CTRL_SET_REMOTE_WAKE_CTRL_EN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define REMOTE_WAKE_CTRL_GET_ARP_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 9, 1)
+#define REMOTE_WAKE_CTRL_SET_ARP_EN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define REMOTE_WAKE_CTRL_SET_ARP_EN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 9, 1, value)
+#define REMOTE_WAKE_CTRL_GET_NDP_EN(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 10, 1)
+#define REMOTE_WAKE_CTRL_SET_NDP_EN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 10, 1, value)
+#define REMOTE_WAKE_CTRL_SET_NDP_EN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 10, 1, value)
+#define REMOTE_WAKE_CTRL_GET_GTK_EN(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 11, 1)
+#define REMOTE_WAKE_CTRL_SET_GTK_EN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 11, 1, value)
+#define REMOTE_WAKE_CTRL_SET_GTK_EN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 11, 1, value)
+#define REMOTE_WAKE_CTRL_GET_NLO_OFFLOAD_EN(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 12, 1)
+#define REMOTE_WAKE_CTRL_SET_NLO_OFFLOAD_EN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 12, 1, value)
+#define REMOTE_WAKE_CTRL_SET_NLO_OFFLOAD_EN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 12, 1, value)
+#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V1_EN(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 13, 1)
+#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V1_EN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 13, 1, value)
+#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V1_EN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 13, 1, value)
+#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V2_EN(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 14, 1)
+#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V2_EN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 14, 1, value)
+#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V2_EN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 14, 1, value)
+#define REMOTE_WAKE_CTRL_GET_FW_UNICAST(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 15, 1)
+#define REMOTE_WAKE_CTRL_SET_FW_UNICAST(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 15, 1, value)
+#define REMOTE_WAKE_CTRL_SET_FW_UNICAST_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 15, 1, value)
+#define REMOTE_WAKE_CTRL_GET_P2P_OFFLOAD_EN(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 16, 1)
+#define REMOTE_WAKE_CTRL_SET_P2P_OFFLOAD_EN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 1, value)
+#define REMOTE_WAKE_CTRL_SET_P2P_OFFLOAD_EN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 1, value)
+#define REMOTE_WAKE_CTRL_GET_RUNTIME_PM_EN(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 17, 1)
+#define REMOTE_WAKE_CTRL_SET_RUNTIME_PM_EN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 17, 1, value)
+#define REMOTE_WAKE_CTRL_SET_RUNTIME_PM_EN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 17, 1, value)
+#define REMOTE_WAKE_CTRL_GET_NET_BIOS_DROP_EN(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 18, 1)
+#define REMOTE_WAKE_CTRL_SET_NET_BIOS_DROP_EN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 18, 1, value)
+#define REMOTE_WAKE_CTRL_SET_NET_BIOS_DROP_EN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 18, 1, value)
+#define REMOTE_WAKE_CTRL_GET_ARP_ACTION(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 24, 1)
+#define REMOTE_WAKE_CTRL_SET_ARP_ACTION(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 1, value)
+#define REMOTE_WAKE_CTRL_SET_ARP_ACTION_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 1, value)
+#define REMOTE_WAKE_CTRL_GET_FW_PARSING_UNTIL_WAKEUP(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 28, 1)
+#define REMOTE_WAKE_CTRL_SET_FW_PARSING_UNTIL_WAKEUP(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 28, 1, value)
+#define REMOTE_WAKE_CTRL_SET_FW_PARSING_UNTIL_WAKEUP_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 28, 1, value)
+#define REMOTE_WAKE_CTRL_GET_FW_PARSING_AFTER_WAKEUP(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 29, 1)
+#define REMOTE_WAKE_CTRL_SET_FW_PARSING_AFTER_WAKEUP(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 29, 1, value)
+#define REMOTE_WAKE_CTRL_SET_FW_PARSING_AFTER_WAKEUP_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 29, 1, value)
+#define AOAC_GLOBAL_INFO_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define AOAC_GLOBAL_INFO_SET_CMD_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define AOAC_GLOBAL_INFO_SET_CMD_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define AOAC_GLOBAL_INFO_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define AOAC_GLOBAL_INFO_SET_CLASS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define AOAC_GLOBAL_INFO_SET_CLASS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define AOAC_GLOBAL_INFO_GET_PAIR_WISE_ENC_ALG(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define AOAC_GLOBAL_INFO_SET_PAIR_WISE_ENC_ALG(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define AOAC_GLOBAL_INFO_SET_PAIR_WISE_ENC_ALG_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define AOAC_GLOBAL_INFO_GET_GROUP_ENC_ALG(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)
+#define AOAC_GLOBAL_INFO_SET_GROUP_ENC_ALG(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define AOAC_GLOBAL_INFO_SET_GROUP_ENC_ALG_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define AOAC_RSVD_PAGE_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define AOAC_RSVD_PAGE_SET_CMD_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define AOAC_RSVD_PAGE_SET_CMD_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define AOAC_RSVD_PAGE_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define AOAC_RSVD_PAGE_SET_CLASS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define AOAC_RSVD_PAGE_SET_CLASS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define AOAC_RSVD_PAGE_GET_LOC_REMOTE_CTRL_INFO(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define AOAC_RSVD_PAGE_SET_LOC_REMOTE_CTRL_INFO(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define AOAC_RSVD_PAGE_SET_LOC_REMOTE_CTRL_INFO_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define AOAC_RSVD_PAGE_GET_LOC_ARP_RESPONSE(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)
+#define AOAC_RSVD_PAGE_SET_LOC_ARP_RESPONSE(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define AOAC_RSVD_PAGE_SET_LOC_ARP_RESPONSE_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define AOAC_RSVD_PAGE_GET_LOC_NEIGHBOR_ADVERTISEMENT(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)
+#define AOAC_RSVD_PAGE_SET_LOC_NEIGHBOR_ADVERTISEMENT(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define AOAC_RSVD_PAGE_SET_LOC_NEIGHBOR_ADVERTISEMENT_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define AOAC_RSVD_PAGE_GET_LOC_GTK_RSP(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8)
+#define AOAC_RSVD_PAGE_SET_LOC_GTK_RSP(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define AOAC_RSVD_PAGE_SET_LOC_GTK_RSP_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define AOAC_RSVD_PAGE_GET_LOC_GTK_INFO(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8)
+#define AOAC_RSVD_PAGE_SET_LOC_GTK_INFO(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define AOAC_RSVD_PAGE_SET_LOC_GTK_INFO_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define AOAC_RSVD_PAGE_GET_LOC_GTK_EXT_MEM(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 16, 8)
+#define AOAC_RSVD_PAGE_SET_LOC_GTK_EXT_MEM(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 8, value)
+#define AOAC_RSVD_PAGE_SET_LOC_GTK_EXT_MEM_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 8, value)
+#define AOAC_RSVD_PAGE_GET_LOC_NDP_INFO(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 24, 8)
+#define AOAC_RSVD_PAGE_SET_LOC_NDP_INFO(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 24, 8, value)
+#define AOAC_RSVD_PAGE_SET_LOC_NDP_INFO_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 24, 8, value)
+#define AOAC_RSVD_PAGE2_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define AOAC_RSVD_PAGE2_SET_CMD_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define AOAC_RSVD_PAGE2_SET_CMD_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define AOAC_RSVD_PAGE2_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define AOAC_RSVD_PAGE2_SET_CLASS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define AOAC_RSVD_PAGE2_SET_CLASS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define AOAC_RSVD_PAGE2_GET_LOC_ROUTER_SOLICATION(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define AOAC_RSVD_PAGE2_SET_LOC_ROUTER_SOLICATION(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define AOAC_RSVD_PAGE2_SET_LOC_ROUTER_SOLICATION_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define AOAC_RSVD_PAGE2_GET_LOC_BUBBLE_PACKET(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)
+#define AOAC_RSVD_PAGE2_SET_LOC_BUBBLE_PACKET(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define AOAC_RSVD_PAGE2_SET_LOC_BUBBLE_PACKET_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define AOAC_RSVD_PAGE2_GET_LOC_TEREDO_INFO(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)
+#define AOAC_RSVD_PAGE2_SET_LOC_TEREDO_INFO(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define AOAC_RSVD_PAGE2_SET_LOC_TEREDO_INFO_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define AOAC_RSVD_PAGE2_GET_LOC_REALWOW_INFO(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 0, 8)
+#define AOAC_RSVD_PAGE2_SET_LOC_REALWOW_INFO(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define AOAC_RSVD_PAGE2_SET_LOC_REALWOW_INFO_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 0, 8, value)
+#define AOAC_RSVD_PAGE2_GET_LOC_KEEP_ALIVE_PKT(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 8, 8)
+#define AOAC_RSVD_PAGE2_SET_LOC_KEEP_ALIVE_PKT(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define AOAC_RSVD_PAGE2_SET_LOC_KEEP_ALIVE_PKT_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 8, 8, value)
+#define AOAC_RSVD_PAGE2_GET_LOC_ACK_PATTERN(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 16, 8)
+#define AOAC_RSVD_PAGE2_SET_LOC_ACK_PATTERN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 16, 8, value)
+#define AOAC_RSVD_PAGE2_SET_LOC_ACK_PATTERN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 16, 8, value)
+#define AOAC_RSVD_PAGE2_GET_LOC_WAKEUP_PATTERN(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X04, 24, 8)
+#define AOAC_RSVD_PAGE2_SET_LOC_WAKEUP_PATTERN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X04, 24, 8, value)
+#define AOAC_RSVD_PAGE2_SET_LOC_WAKEUP_PATTERN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X04, 24, 8, value)
+#define D0_SCAN_OFFLOAD_INFO_GET_CMD_ID(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define D0_SCAN_OFFLOAD_INFO_SET_CMD_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define D0_SCAN_OFFLOAD_INFO_SET_CMD_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define D0_SCAN_OFFLOAD_INFO_GET_CLASS(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define D0_SCAN_OFFLOAD_INFO_SET_CLASS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define D0_SCAN_OFFLOAD_INFO_SET_CLASS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define D0_SCAN_OFFLOAD_INFO_GET_LOC_CHANNEL_INFO(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define D0_SCAN_OFFLOAD_INFO_SET_LOC_CHANNEL_INFO(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define D0_SCAN_OFFLOAD_INFO_SET_LOC_CHANNEL_INFO_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define CHANNEL_SWITCH_OFFLOAD_GET_CMD_ID(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define CHANNEL_SWITCH_OFFLOAD_SET_CMD_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define CHANNEL_SWITCH_OFFLOAD_SET_CMD_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define CHANNEL_SWITCH_OFFLOAD_GET_CLASS(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define CHANNEL_SWITCH_OFFLOAD_SET_CLASS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define CHANNEL_SWITCH_OFFLOAD_SET_CLASS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define CHANNEL_SWITCH_OFFLOAD_GET_CHANNEL_NUM(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define CHANNEL_SWITCH_OFFLOAD_SET_CHANNEL_NUM(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define CHANNEL_SWITCH_OFFLOAD_SET_CHANNEL_NUM_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define CHANNEL_SWITCH_OFFLOAD_GET_EN_RFE(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)
+#define CHANNEL_SWITCH_OFFLOAD_SET_EN_RFE(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define CHANNEL_SWITCH_OFFLOAD_SET_EN_RFE_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define CHANNEL_SWITCH_OFFLOAD_GET_RFE_TYPE(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 24, 8)
+#define CHANNEL_SWITCH_OFFLOAD_SET_RFE_TYPE(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define CHANNEL_SWITCH_OFFLOAD_SET_RFE_TYPE_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 24, 8, value)
+#define AOAC_RSVD_PAGE3_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define AOAC_RSVD_PAGE3_SET_CMD_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define AOAC_RSVD_PAGE3_SET_CMD_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define AOAC_RSVD_PAGE3_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define AOAC_RSVD_PAGE3_SET_CLASS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define AOAC_RSVD_PAGE3_SET_CLASS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define AOAC_RSVD_PAGE3_GET_LOC_NLO_INFO(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 8, 8)
+#define AOAC_RSVD_PAGE3_SET_LOC_NLO_INFO(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define AOAC_RSVD_PAGE3_SET_LOC_NLO_INFO_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 8, value)
+#define AOAC_RSVD_PAGE3_GET_LOC_AOAC_REPORT(h2c_pkt) \
+ GET_H2C_FIELD(h2c_pkt + 0X00, 16, 8)
+#define AOAC_RSVD_PAGE3_SET_LOC_AOAC_REPORT(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define AOAC_RSVD_PAGE3_SET_LOC_AOAC_REPORT_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 16, 8, value)
+#define DBG_MSG_CTRL_GET_CMD_ID(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 0, 5)
+#define DBG_MSG_CTRL_SET_CMD_ID(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define DBG_MSG_CTRL_SET_CMD_ID_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 0, 5, value)
+#define DBG_MSG_CTRL_GET_CLASS(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 5, 3)
+#define DBG_MSG_CTRL_SET_CLASS(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define DBG_MSG_CTRL_SET_CLASS_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 5, 3, value)
+#define DBG_MSG_CTRL_GET_FUN_EN(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 8, 1)
+#define DBG_MSG_CTRL_SET_FUN_EN(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define DBG_MSG_CTRL_SET_FUN_EN_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 8, 1, value)
+#define DBG_MSG_CTRL_GET_MODE(h2c_pkt) GET_H2C_FIELD(h2c_pkt + 0X00, 12, 4)
+#define DBG_MSG_CTRL_SET_MODE(h2c_pkt, value) \
+ SET_H2C_FIELD_CLR(h2c_pkt + 0X00, 12, 4, value)
+#define DBG_MSG_CTRL_SET_MODE_NO_CLR(h2c_pkt, value) \
+ SET_H2C_FIELD_NO_CLR(h2c_pkt + 0X00, 12, 4, value)
#endif
diff --git a/hal/halmac/halmac_original_h2c_nic.h b/hal/halmac/halmac_original_h2c_nic.h
index a42022d..3870ff4 100644
--- a/hal/halmac/halmac_original_h2c_nic.h
+++ b/hal/halmac/halmac_original_h2c_nic.h
@@ -1,38 +1,57 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
#ifndef _HAL_ORIGINALH2CFORMAT_H2C_C2H_NIC_H_
#define _HAL_ORIGINALH2CFORMAT_H2C_C2H_NIC_H_
-#define CMD_ID_ORIGINAL_H2C 0X00
-#define CMD_ID_H2C2H_LB 0X0
-#define CMD_ID_D0_SCAN_OFFLOAD_CTRL 0X06
-#define CMD_ID_RSVD_PAGE 0X0
-#define CMD_ID_MEDIA_STATUS_RPT 0X01
-#define CMD_ID_KEEP_ALIVE 0X03
-#define CMD_ID_DISCONNECT_DECISION 0X04
-#define CMD_ID_AP_OFFLOAD 0X08
-#define CMD_ID_BCN_RSVDPAGE 0X09
-#define CMD_ID_PROBE_RSP_RSVDPAGE 0X0A
-#define CMD_ID_SET_PWR_MODE 0X00
-#define CMD_ID_PS_TUNING_PARA 0X01
-#define CMD_ID_PS_TUNING_PARA_II 0X02
-#define CMD_ID_PS_LPS_PARA 0X03
-#define CMD_ID_P2P_PS_OFFLOAD 0X04
-#define CMD_ID_PS_SCAN_EN 0X05
-#define CMD_ID_SAP_PS 0X06
-#define CMD_ID_INACTIVE_PS 0X07
-#define CMD_ID_MACID_CFG 0X00
-#define CMD_ID_TXBF 0X01
-#define CMD_ID_RSSI_SETTING 0X02
-#define CMD_ID_AP_REQ_TXRPT 0X03
-#define CMD_ID_INIT_RATE_COLLECTION 0X04
-#define CMD_ID_IQK_OFFLOAD 0X05
-#define CMD_ID_RA_PARA_ADJUST 0X06
-#define CMD_ID_WWLAN 0X00
-#define CMD_ID_REMOTE_WAKE_CTRL 0X01
-#define CMD_ID_AOAC_BLOBAL_INFO 0X02
-#define CMD_ID_AOAC_RSVD_PAGE 0X03
-#define CMD_ID_AOAC_RSVD_PAGE2 0X04
-#define CMD_ID_D0_SCAN_OFFLOAD_INFO 0X05
-#define CMD_ID_CHANNEL_SWITCH_OFFLOAD 0X07
-#define CMD_ID_AOAC_RSVD_PAGE3 0X08
+#define CMD_ID_ORIGINAL_H2C 0X00
+#define CMD_ID_H2C2H_LB 0X0
+#define CMD_ID_D0_SCAN_OFFLOAD_CTRL 0X06
+#define CMD_ID_RSVD_PAGE 0X0
+#define CMD_ID_MEDIA_STATUS_RPT 0X01
+#define CMD_ID_KEEP_ALIVE 0X03
+#define CMD_ID_DISCONNECT_DECISION 0X04
+#define CMD_ID_AP_OFFLOAD 0X08
+#define CMD_ID_BCN_RSVDPAGE 0X09
+#define CMD_ID_PROBE_RSP_RSVDPAGE 0X0A
+#define CMD_ID_SINGLE_CHANNELSWITCH 0X1C
+#define CMD_ID_SINGLE_CHANNELSWITCH_V2 0X1D
+#define CMD_ID_SET_PWR_MODE 0X00
+#define CMD_ID_PS_TUNING_PARA 0X01
+#define CMD_ID_PS_TUNING_PARA_II 0X02
+#define CMD_ID_PS_LPS_PARA 0X03
+#define CMD_ID_P2P_PS_OFFLOAD 0X04
+#define CMD_ID_PS_SCAN_EN 0X05
+#define CMD_ID_SAP_PS 0X06
+#define CMD_ID_INACTIVE_PS 0X07
+#define CMD_ID_MACID_CFG 0X00
+#define CMD_ID_TXBF 0X01
+#define CMD_ID_RSSI_SETTING 0X02
+#define CMD_ID_AP_REQ_TXRPT 0X03
+#define CMD_ID_INIT_RATE_COLLECTION 0X04
+#define CMD_ID_IQK_OFFLOAD 0X05
+#define CMD_ID_MACID_CFG_3SS 0X06
+#define CMD_ID_RA_PARA_ADJUST 0X07
+#define CMD_ID_WWLAN 0X00
+#define CMD_ID_REMOTE_WAKE_CTRL 0X01
+#define CMD_ID_AOAC_GLOBAL_INFO 0X02
+#define CMD_ID_AOAC_RSVD_PAGE 0X03
+#define CMD_ID_AOAC_RSVD_PAGE2 0X04
+#define CMD_ID_D0_SCAN_OFFLOAD_INFO 0X05
+#define CMD_ID_CHANNEL_SWITCH_OFFLOAD 0X07
+#define CMD_ID_AOAC_RSVD_PAGE3 0X08
+#define CMD_ID_DBG_MSG_CTRL 0X1E
#define CLASS_ORIGINAL_H2C 0X00
#define CLASS_H2C2H_LB 0X07
#define CLASS_D0_SCAN_OFFLOAD_CTRL 0X04
@@ -43,553 +62,1082 @@
#define CLASS_AP_OFFLOAD 0X0
#define CLASS_BCN_RSVDPAGE 0X0
#define CLASS_PROBE_RSP_RSVDPAGE 0X0
+#define CLASS_SINGLE_CHANNELSWITCH 0X0
+#define CLASS_SINGLE_CHANNELSWITCH_V2 0X0
#define CLASS_SET_PWR_MODE 0X01
#define CLASS_PS_TUNING_PARA 0X01
#define CLASS_PS_TUNING_PARA_II 0X01
#define CLASS_PS_LPS_PARA 0X01
#define CLASS_P2P_PS_OFFLOAD 0X01
-#define CLASS_PS_SCAN_EN 0X0
-#define CLASS_SAP_PS 0X0
-#define CLASS_INACTIVE_PS 0X0
+#define CLASS_PS_SCAN_EN 0X1
+#define CLASS_SAP_PS 0X1
+#define CLASS_INACTIVE_PS 0X1
#define CLASS_MACID_CFG 0X2
#define CLASS_TXBF 0X2
#define CLASS_RSSI_SETTING 0X2
#define CLASS_AP_REQ_TXRPT 0X2
#define CLASS_INIT_RATE_COLLECTION 0X2
#define CLASS_IQK_OFFLOAD 0X2
+#define CLASS_MACID_CFG_3SS 0X2
#define CLASS_RA_PARA_ADJUST 0X02
#define CLASS_WWLAN 0X4
#define CLASS_REMOTE_WAKE_CTRL 0X4
-#define CLASS_AOAC_BLOBAL_INFO 0X04
+#define CLASS_AOAC_GLOBAL_INFO 0X04
#define CLASS_AOAC_RSVD_PAGE 0X04
#define CLASS_AOAC_RSVD_PAGE2 0X04
#define CLASS_D0_SCAN_OFFLOAD_INFO 0X04
#define CLASS_CHANNEL_SWITCH_OFFLOAD 0X04
#define CLASS_AOAC_RSVD_PAGE3 0X04
-#define ORIGINAL_H2C_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4)
-#define ORIGINAL_H2C_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value)
-#define ORIGINAL_H2C_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3)
-#define ORIGINAL_H2C_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value)
-#define H2C2H_LB_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4)
-#define H2C2H_LB_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value)
-#define H2C2H_LB_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3)
-#define H2C2H_LB_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value)
-#define H2C2H_LB_GET_SEQ(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8)
-#define H2C2H_LB_SET_SEQ(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value)
-#define H2C2H_LB_GET_PAYLOAD1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 16)
-#define H2C2H_LB_SET_PAYLOAD1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 16, __Value)
-#define H2C2H_LB_GET_PAYLOAD2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 32)
-#define H2C2H_LB_SET_PAYLOAD2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 32, __Value)
-#define D0_SCAN_OFFLOAD_CTRL_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4)
-#define D0_SCAN_OFFLOAD_CTRL_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value)
-#define D0_SCAN_OFFLOAD_CTRL_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3)
-#define D0_SCAN_OFFLOAD_CTRL_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value)
-#define D0_SCAN_OFFLOAD_CTRL_GET_D0_SCAN_FUN_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1)
-#define D0_SCAN_OFFLOAD_CTRL_SET_D0_SCAN_FUN_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value)
-#define D0_SCAN_OFFLOAD_CTRL_GET_RTD3FUN_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1)
-#define D0_SCAN_OFFLOAD_CTRL_SET_RTD3FUN_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value)
-#define D0_SCAN_OFFLOAD_CTRL_GET_U3_SCAN_FUN_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 10, 1)
-#define D0_SCAN_OFFLOAD_CTRL_SET_U3_SCAN_FUN_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 10, 1, __Value)
-#define D0_SCAN_OFFLOAD_CTRL_GET_NLO_FUN_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 11, 1)
-#define D0_SCAN_OFFLOAD_CTRL_SET_NLO_FUN_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 11, 1, __Value)
-#define D0_SCAN_OFFLOAD_CTRL_GET_IPS_DEPENDENT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 12, 1)
-#define D0_SCAN_OFFLOAD_CTRL_SET_IPS_DEPENDENT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 12, 1, __Value)
-#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_PROBE_PACKET(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 17)
-#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_PROBE_PACKET(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 17, __Value)
-#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SCAN_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8)
-#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SCAN_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value)
-#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SSID_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8)
-#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SSID_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value)
-#define RSVD_PAGE_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4)
-#define RSVD_PAGE_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value)
-#define RSVD_PAGE_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3)
-#define RSVD_PAGE_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value)
-#define RSVD_PAGE_GET_LOC_PROBE_RSP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8)
-#define RSVD_PAGE_SET_LOC_PROBE_RSP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value)
-#define RSVD_PAGE_GET_LOC_PS_POLL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8)
-#define RSVD_PAGE_SET_LOC_PS_POLL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value)
-#define RSVD_PAGE_GET_LOC_NULL_DATA(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8)
-#define RSVD_PAGE_SET_LOC_NULL_DATA(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value)
-#define RSVD_PAGE_GET_LOC_QOS_NULL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8)
-#define RSVD_PAGE_SET_LOC_QOS_NULL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value)
-#define RSVD_PAGE_GET_LOC_BT_QOS_NULL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8)
-#define RSVD_PAGE_SET_LOC_BT_QOS_NULL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value)
-#define RSVD_PAGE_GET_LOC_CTS2SELF(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 8)
-#define RSVD_PAGE_SET_LOC_CTS2SELF(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 8, __Value)
-#define RSVD_PAGE_GET_LOC_LTECOEX_QOSNULL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 24, 8)
-#define RSVD_PAGE_SET_LOC_LTECOEX_QOSNULL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 24, 8, __Value)
-#define MEDIA_STATUS_RPT_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4)
-#define MEDIA_STATUS_RPT_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value)
-#define MEDIA_STATUS_RPT_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3)
-#define MEDIA_STATUS_RPT_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value)
-#define MEDIA_STATUS_RPT_GET_OP_MODE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1)
-#define MEDIA_STATUS_RPT_SET_OP_MODE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value)
-#define MEDIA_STATUS_RPT_GET_MACID_IN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1)
-#define MEDIA_STATUS_RPT_SET_MACID_IN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value)
-#define MEDIA_STATUS_RPT_GET_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8)
-#define MEDIA_STATUS_RPT_SET_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value)
-#define MEDIA_STATUS_RPT_GET_MACID_END(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8)
-#define MEDIA_STATUS_RPT_SET_MACID_END(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value)
-#define KEEP_ALIVE_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4)
-#define KEEP_ALIVE_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value)
-#define KEEP_ALIVE_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3)
-#define KEEP_ALIVE_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value)
-#define KEEP_ALIVE_GET_ENABLE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1)
-#define KEEP_ALIVE_SET_ENABLE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value)
-#define KEEP_ALIVE_GET_ADOPT_USER_SETTING(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1)
-#define KEEP_ALIVE_SET_ADOPT_USER_SETTING(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value)
-#define KEEP_ALIVE_GET_PKT_TYPE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 10, 1)
-#define KEEP_ALIVE_SET_PKT_TYPE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 10, 1, __Value)
-#define KEEP_ALIVE_GET_KEEP_ALIVE_CHECK_PERIOD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8)
-#define KEEP_ALIVE_SET_KEEP_ALIVE_CHECK_PERIOD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value)
-#define DISCONNECT_DECISION_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4)
-#define DISCONNECT_DECISION_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value)
-#define DISCONNECT_DECISION_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3)
-#define DISCONNECT_DECISION_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value)
-#define DISCONNECT_DECISION_GET_ENABLE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1)
-#define DISCONNECT_DECISION_SET_ENABLE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value)
-#define DISCONNECT_DECISION_GET_ADOPT_USER_SETTING(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1)
-#define DISCONNECT_DECISION_SET_ADOPT_USER_SETTING(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value)
-#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 10, 1)
-#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 10, 1, __Value)
-#define DISCONNECT_DECISION_GET_DISCONNECT_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 11, 1)
-#define DISCONNECT_DECISION_SET_DISCONNECT_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 11, 1, __Value)
-#define DISCONNECT_DECISION_GET_DISCON_DECISION_CHECK_PERIOD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8)
-#define DISCONNECT_DECISION_SET_DISCON_DECISION_CHECK_PERIOD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value)
-#define DISCONNECT_DECISION_GET_TRY_PKT_NUM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8)
-#define DISCONNECT_DECISION_SET_TRY_PKT_NUM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value)
-#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_LIMIT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8)
-#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_LIMIT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value)
-#define AP_OFFLOAD_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4)
-#define AP_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value)
-#define AP_OFFLOAD_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3)
-#define AP_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value)
-#define AP_OFFLOAD_GET_ON(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1)
-#define AP_OFFLOAD_SET_ON(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value)
-#define AP_OFFLOAD_GET_CFG_MIFI_PLATFORM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1)
-#define AP_OFFLOAD_SET_CFG_MIFI_PLATFORM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value)
-#define AP_OFFLOAD_GET_LINKED(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 10, 1)
-#define AP_OFFLOAD_SET_LINKED(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 10, 1, __Value)
-#define AP_OFFLOAD_GET_EN_AUTO_WAKE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 11, 1)
-#define AP_OFFLOAD_SET_EN_AUTO_WAKE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 11, 1, __Value)
-#define AP_OFFLOAD_GET_WAKE_FLAG(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 12, 1)
-#define AP_OFFLOAD_SET_WAKE_FLAG(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 12, 1, __Value)
-#define AP_OFFLOAD_GET_HIDDEN_ROOT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 1)
-#define AP_OFFLOAD_SET_HIDDEN_ROOT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 1, __Value)
-#define AP_OFFLOAD_GET_HIDDEN_VAP1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 17, 1)
-#define AP_OFFLOAD_SET_HIDDEN_VAP1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 17, 1, __Value)
-#define AP_OFFLOAD_GET_HIDDEN_VAP2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 18, 1)
-#define AP_OFFLOAD_SET_HIDDEN_VAP2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 18, 1, __Value)
-#define AP_OFFLOAD_GET_HIDDEN_VAP3(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 19, 1)
-#define AP_OFFLOAD_SET_HIDDEN_VAP3(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 19, 1, __Value)
-#define AP_OFFLOAD_GET_HIDDEN_VAP4(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 20, 1)
-#define AP_OFFLOAD_SET_HIDDEN_VAP4(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 20, 1, __Value)
-#define AP_OFFLOAD_GET_DENYANY_ROOT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 1)
-#define AP_OFFLOAD_SET_DENYANY_ROOT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 1, __Value)
-#define AP_OFFLOAD_GET_DENYANY_VAP1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 25, 1)
-#define AP_OFFLOAD_SET_DENYANY_VAP1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 25, 1, __Value)
-#define AP_OFFLOAD_GET_DENYANY_VAP2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 26, 1)
-#define AP_OFFLOAD_SET_DENYANY_VAP2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 26, 1, __Value)
-#define AP_OFFLOAD_GET_DENYANY_VAP3(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 27, 1)
-#define AP_OFFLOAD_SET_DENYANY_VAP3(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 27, 1, __Value)
-#define AP_OFFLOAD_GET_DENYANY_VAP4(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 28, 1)
-#define AP_OFFLOAD_SET_DENYANY_VAP4(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 28, 1, __Value)
-#define AP_OFFLOAD_GET_WAIT_TBTT_CNT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8)
-#define AP_OFFLOAD_SET_WAIT_TBTT_CNT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value)
-#define AP_OFFLOAD_GET_WAKE_TIMEOUT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8)
-#define AP_OFFLOAD_SET_WAKE_TIMEOUT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value)
-#define AP_OFFLOAD_GET_LEN_IV_PAIR(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 8)
-#define AP_OFFLOAD_SET_LEN_IV_PAIR(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 8, __Value)
-#define AP_OFFLOAD_GET_LEN_IV_GRP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 24, 8)
-#define AP_OFFLOAD_SET_LEN_IV_GRP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 24, 8, __Value)
-#define BCN_RSVDPAGE_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4)
-#define BCN_RSVDPAGE_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value)
-#define BCN_RSVDPAGE_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3)
-#define BCN_RSVDPAGE_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value)
-#define BCN_RSVDPAGE_GET_LOC_ROOT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8)
-#define BCN_RSVDPAGE_SET_LOC_ROOT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value)
-#define BCN_RSVDPAGE_GET_LOC_VAP1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8)
-#define BCN_RSVDPAGE_SET_LOC_VAP1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value)
-#define BCN_RSVDPAGE_GET_LOC_VAP2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8)
-#define BCN_RSVDPAGE_SET_LOC_VAP2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value)
-#define BCN_RSVDPAGE_GET_LOC_VAP3(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8)
-#define BCN_RSVDPAGE_SET_LOC_VAP3(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value)
-#define BCN_RSVDPAGE_GET_LOC_VAP4(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8)
-#define BCN_RSVDPAGE_SET_LOC_VAP4(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value)
-#define PROBE_RSP_RSVDPAGE_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4)
-#define PROBE_RSP_RSVDPAGE_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value)
-#define PROBE_RSP_RSVDPAGE_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3)
-#define PROBE_RSP_RSVDPAGE_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value)
-#define PROBE_RSP_RSVDPAGE_GET_LOC_ROOT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8)
-#define PROBE_RSP_RSVDPAGE_SET_LOC_ROOT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value)
-#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8)
-#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value)
-#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8)
-#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value)
-#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP3(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8)
-#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP3(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value)
-#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP4(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8)
-#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP4(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value)
-#define SET_PWR_MODE_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4)
-#define SET_PWR_MODE_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value)
-#define SET_PWR_MODE_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3)
-#define SET_PWR_MODE_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value)
-#define SET_PWR_MODE_GET_MODE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 7)
-#define SET_PWR_MODE_SET_MODE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 7, __Value)
-#define SET_PWR_MODE_GET_CLK_REQUEST(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 15, 1)
-#define SET_PWR_MODE_SET_CLK_REQUEST(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 15, 1, __Value)
-#define SET_PWR_MODE_GET_RLBM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 4)
-#define SET_PWR_MODE_SET_RLBM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 4, __Value)
-#define SET_PWR_MODE_GET_SMART_PS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 20, 4)
-#define SET_PWR_MODE_SET_SMART_PS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 20, 4, __Value)
-#define SET_PWR_MODE_GET_AWAKE_INTERVAL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8)
-#define SET_PWR_MODE_SET_AWAKE_INTERVAL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value)
-#define SET_PWR_MODE_GET_B_ALL_QUEUE_UAPSD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 1)
-#define SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 1, __Value)
-#define SET_PWR_MODE_GET_BCN_EARLY_RPT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 2, 1)
-#define SET_PWR_MODE_SET_BCN_EARLY_RPT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 2, 1, __Value)
-#define SET_PWR_MODE_GET_PORT_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 5, 3)
-#define SET_PWR_MODE_SET_PORT_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 5, 3, __Value)
-#define SET_PWR_MODE_GET_PWR_STATE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8)
-#define SET_PWR_MODE_SET_PWR_STATE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value)
-#define SET_PWR_MODE_GET_LOW_POWER_RX_BCN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 1)
-#define SET_PWR_MODE_SET_LOW_POWER_RX_BCN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 1, __Value)
-#define SET_PWR_MODE_GET_ANT_AUTO_SWITCH(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 17, 1)
-#define SET_PWR_MODE_SET_ANT_AUTO_SWITCH(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 17, 1, __Value)
-#define SET_PWR_MODE_GET_PS_ALLOW_BT_HIGH_PRIORITY(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 18, 1)
-#define SET_PWR_MODE_SET_PS_ALLOW_BT_HIGH_PRIORITY(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 18, 1, __Value)
-#define SET_PWR_MODE_GET_PROTECT_BCN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 19, 1)
-#define SET_PWR_MODE_SET_PROTECT_BCN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 19, 1, __Value)
-#define SET_PWR_MODE_GET_SILENCE_PERIOD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 20, 1)
-#define SET_PWR_MODE_SET_SILENCE_PERIOD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 20, 1, __Value)
-#define SET_PWR_MODE_GET_FAST_BT_CONNECT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 21, 1)
-#define SET_PWR_MODE_SET_FAST_BT_CONNECT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 21, 1, __Value)
-#define SET_PWR_MODE_GET_TWO_ANTENNA_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 22, 1)
-#define SET_PWR_MODE_SET_TWO_ANTENNA_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 22, 1, __Value)
-#define SET_PWR_MODE_GET_ADOPT_USER_SETTING(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 24, 1)
-#define SET_PWR_MODE_SET_ADOPT_USER_SETTING(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 24, 1, __Value)
-#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 25, 3)
-#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 25, 3, __Value)
-#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 28, 4)
-#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 28, 4, __Value)
-#define PS_TUNING_PARA_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4)
-#define PS_TUNING_PARA_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value)
-#define PS_TUNING_PARA_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3)
-#define PS_TUNING_PARA_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value)
-#define PS_TUNING_PARA_GET_BCN_TO_LIMIT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 7)
-#define PS_TUNING_PARA_SET_BCN_TO_LIMIT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 7, __Value)
-#define PS_TUNING_PARA_GET_DTIM_TIME_OUT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 15, 1)
-#define PS_TUNING_PARA_SET_DTIM_TIME_OUT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 15, 1, __Value)
-#define PS_TUNING_PARA_GET_PS_TIME_OUT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 4)
-#define PS_TUNING_PARA_SET_PS_TIME_OUT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 4, __Value)
-#define PS_TUNING_PARA_GET_ADOPT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8)
-#define PS_TUNING_PARA_SET_ADOPT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value)
-#define PS_TUNING_PARA_II_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4)
-#define PS_TUNING_PARA_II_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value)
-#define PS_TUNING_PARA_II_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3)
-#define PS_TUNING_PARA_II_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value)
-#define PS_TUNING_PARA_II_GET_BCN_TO_PERIOD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 7)
-#define PS_TUNING_PARA_II_SET_BCN_TO_PERIOD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 7, __Value)
-#define PS_TUNING_PARA_II_GET_ADOPT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 15, 1)
-#define PS_TUNING_PARA_II_SET_ADOPT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 15, 1, __Value)
-#define PS_TUNING_PARA_II_GET_DRV_EARLY_IVL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8)
-#define PS_TUNING_PARA_II_SET_DRV_EARLY_IVL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value)
-#define PS_LPS_PARA_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4)
-#define PS_LPS_PARA_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value)
-#define PS_LPS_PARA_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3)
-#define PS_LPS_PARA_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value)
-#define PS_LPS_PARA_GET_LPS_CONTROL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8)
-#define PS_LPS_PARA_SET_LPS_CONTROL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value)
-#define P2P_PS_OFFLOAD_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4)
-#define P2P_PS_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value)
-#define P2P_PS_OFFLOAD_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3)
-#define P2P_PS_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value)
-#define P2P_PS_OFFLOAD_GET_OFFLOAD_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1)
-#define P2P_PS_OFFLOAD_SET_OFFLOAD_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value)
-#define P2P_PS_OFFLOAD_GET_ROLE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1)
-#define P2P_PS_OFFLOAD_SET_ROLE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value)
-#define P2P_PS_OFFLOAD_GET_CTWINDOW_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 10, 1)
-#define P2P_PS_OFFLOAD_SET_CTWINDOW_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 10, 1, __Value)
-#define P2P_PS_OFFLOAD_GET_NOA0_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 11, 1)
-#define P2P_PS_OFFLOAD_SET_NOA0_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 11, 1, __Value)
-#define P2P_PS_OFFLOAD_GET_NOA1_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 12, 1)
-#define P2P_PS_OFFLOAD_SET_NOA1_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 12, 1, __Value)
-#define P2P_PS_OFFLOAD_GET_ALL_STA_SLEEP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 13, 1)
-#define P2P_PS_OFFLOAD_SET_ALL_STA_SLEEP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 13, 1, __Value)
-#define P2P_PS_OFFLOAD_GET_DISCOVERY(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 14, 1)
-#define P2P_PS_OFFLOAD_SET_DISCOVERY(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 14, 1, __Value)
-#define PS_SCAN_EN_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4)
-#define PS_SCAN_EN_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value)
-#define PS_SCAN_EN_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3)
-#define PS_SCAN_EN_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value)
-#define PS_SCAN_EN_GET_ENABLE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1)
-#define PS_SCAN_EN_SET_ENABLE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value)
-#define SAP_PS_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4)
-#define SAP_PS_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value)
-#define SAP_PS_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3)
-#define SAP_PS_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value)
-#define SAP_PS_GET_ENABLE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1)
-#define SAP_PS_SET_ENABLE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value)
-#define SAP_PS_GET_EN_PS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1)
-#define SAP_PS_SET_EN_PS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value)
-#define SAP_PS_GET_EN_LP_RX(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 10, 1)
-#define SAP_PS_SET_EN_LP_RX(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 10, 1, __Value)
-#define SAP_PS_GET_MANUAL_32K(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 11, 1)
-#define SAP_PS_SET_MANUAL_32K(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 11, 1, __Value)
-#define SAP_PS_GET_DURATION(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8)
-#define SAP_PS_SET_DURATION(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value)
-#define INACTIVE_PS_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4)
-#define INACTIVE_PS_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value)
-#define INACTIVE_PS_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3)
-#define INACTIVE_PS_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value)
-#define INACTIVE_PS_GET_ENABLE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1)
-#define INACTIVE_PS_SET_ENABLE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value)
-#define INACTIVE_PS_GET_IGNORE_PS_CONDITION(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1)
-#define INACTIVE_PS_SET_IGNORE_PS_CONDITION(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value)
-#define INACTIVE_PS_GET_FREQUENCY(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8)
-#define INACTIVE_PS_SET_FREQUENCY(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value)
-#define INACTIVE_PS_GET_DURATION(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8)
-#define INACTIVE_PS_SET_DURATION(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value)
-#define MACID_CFG_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4)
-#define MACID_CFG_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value)
-#define MACID_CFG_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3)
-#define MACID_CFG_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value)
-#define MACID_CFG_GET_MAC_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8)
-#define MACID_CFG_SET_MAC_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value)
-#define MACID_CFG_GET_RATE_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 5)
-#define MACID_CFG_SET_RATE_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 5, __Value)
-#define MACID_CFG_GET_SGI(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 23, 1)
-#define MACID_CFG_SET_SGI(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 23, 1, __Value)
-#define MACID_CFG_GET_BW(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 2)
-#define MACID_CFG_SET_BW(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 2, __Value)
-#define MACID_CFG_GET_LDPC_CAP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 26, 1)
-#define MACID_CFG_SET_LDPC_CAP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 26, 1, __Value)
-#define MACID_CFG_GET_NO_UPDATE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 27, 1)
-#define MACID_CFG_SET_NO_UPDATE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 27, 1, __Value)
-#define MACID_CFG_GET_WHT_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 28, 2)
-#define MACID_CFG_SET_WHT_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 28, 2, __Value)
-#define MACID_CFG_GET_DISPT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 30, 1)
-#define MACID_CFG_SET_DISPT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 30, 1, __Value)
-#define MACID_CFG_GET_DISRA(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 31, 1)
-#define MACID_CFG_SET_DISRA(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 31, 1, __Value)
-#define MACID_CFG_GET_RATE_MASK7_0(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8)
-#define MACID_CFG_SET_RATE_MASK7_0(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value)
-#define MACID_CFG_GET_RATE_MASK15_8(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8)
-#define MACID_CFG_SET_RATE_MASK15_8(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value)
-#define MACID_CFG_GET_RATE_MASK23_16(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 8)
-#define MACID_CFG_SET_RATE_MASK23_16(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 8, __Value)
-#define MACID_CFG_GET_RATE_MASK31_24(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 24, 8)
-#define MACID_CFG_SET_RATE_MASK31_24(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 24, 8, __Value)
-#define TXBF_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4)
-#define TXBF_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value)
-#define TXBF_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3)
-#define TXBF_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value)
-#define TXBF_GET_NDPA0_HEAD_PAGE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8)
-#define TXBF_SET_NDPA0_HEAD_PAGE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value)
-#define TXBF_GET_NDPA1_HEAD_PAGE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8)
-#define TXBF_SET_NDPA1_HEAD_PAGE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value)
-#define TXBF_GET_PERIOD_0(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8)
-#define TXBF_SET_PERIOD_0(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value)
-#define RSSI_SETTING_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4)
-#define RSSI_SETTING_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value)
-#define RSSI_SETTING_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3)
-#define RSSI_SETTING_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value)
-#define RSSI_SETTING_GET_MAC_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8)
-#define RSSI_SETTING_SET_MAC_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value)
-#define RSSI_SETTING_GET_RSSI(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 7)
-#define RSSI_SETTING_SET_RSSI(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 7, __Value)
-#define RSSI_SETTING_GET_RA_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8)
-#define RSSI_SETTING_SET_RA_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value)
-#define AP_REQ_TXRPT_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4)
-#define AP_REQ_TXRPT_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value)
-#define AP_REQ_TXRPT_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3)
-#define AP_REQ_TXRPT_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value)
-#define AP_REQ_TXRPT_GET_STA1_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8)
-#define AP_REQ_TXRPT_SET_STA1_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value)
-#define AP_REQ_TXRPT_GET_STA2_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8)
-#define AP_REQ_TXRPT_SET_STA2_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value)
-#define AP_REQ_TXRPT_GET_RTY_OK_TOTAL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 1)
-#define AP_REQ_TXRPT_SET_RTY_OK_TOTAL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 1, __Value)
-#define AP_REQ_TXRPT_GET_RTY_CNT_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 25, 1)
-#define AP_REQ_TXRPT_SET_RTY_CNT_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 25, 1, __Value)
-#define INIT_RATE_COLLECTION_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4)
-#define INIT_RATE_COLLECTION_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value)
-#define INIT_RATE_COLLECTION_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3)
-#define INIT_RATE_COLLECTION_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value)
-#define INIT_RATE_COLLECTION_GET_STA1_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8)
-#define INIT_RATE_COLLECTION_SET_STA1_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value)
-#define INIT_RATE_COLLECTION_GET_STA2_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8)
-#define INIT_RATE_COLLECTION_SET_STA2_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value)
-#define INIT_RATE_COLLECTION_GET_STA3_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8)
-#define INIT_RATE_COLLECTION_SET_STA3_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value)
-#define INIT_RATE_COLLECTION_GET_STA4_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8)
-#define INIT_RATE_COLLECTION_SET_STA4_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value)
-#define INIT_RATE_COLLECTION_GET_STA5_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8)
-#define INIT_RATE_COLLECTION_SET_STA5_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value)
-#define INIT_RATE_COLLECTION_GET_STA6_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 8)
-#define INIT_RATE_COLLECTION_SET_STA6_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 8, __Value)
-#define INIT_RATE_COLLECTION_GET_STA7_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 24, 8)
-#define INIT_RATE_COLLECTION_SET_STA7_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 24, 8, __Value)
-#define IQK_OFFLOAD_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4)
-#define IQK_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value)
-#define IQK_OFFLOAD_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3)
-#define IQK_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value)
-#define IQK_OFFLOAD_GET_CHANNEL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8)
-#define IQK_OFFLOAD_SET_CHANNEL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value)
-#define IQK_OFFLOAD_GET_BWBAND(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8)
-#define IQK_OFFLOAD_SET_BWBAND(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value)
-#define IQK_OFFLOAD_GET_EXTPALNA(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8)
-#define IQK_OFFLOAD_SET_EXTPALNA(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value)
-#define RA_PARA_ADJUST_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4)
-#define RA_PARA_ADJUST_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value)
-#define RA_PARA_ADJUST_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3)
-#define RA_PARA_ADJUST_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value)
-#define RA_PARA_ADJUST_GET_MAC_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8)
-#define RA_PARA_ADJUST_SET_MAC_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value)
-#define RA_PARA_ADJUST_GET_PARAMETER_INDEX(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8)
-#define RA_PARA_ADJUST_SET_PARAMETER_INDEX(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value)
-#define RA_PARA_ADJUST_GET_RATE_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8)
-#define RA_PARA_ADJUST_SET_RATE_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value)
-#define RA_PARA_ADJUST_GET_VALUE_BYTE0(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8)
-#define RA_PARA_ADJUST_SET_VALUE_BYTE0(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value)
-#define RA_PARA_ADJUST_GET_VALUE_BYTE1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8)
-#define RA_PARA_ADJUST_SET_VALUE_BYTE1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value)
-#define RA_PARA_ADJUST_GET_ASK_FW_FOR_FW_PARA(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 8)
-#define RA_PARA_ADJUST_SET_ASK_FW_FOR_FW_PARA(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 8, __Value)
-#define WWLAN_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4)
-#define WWLAN_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value)
-#define WWLAN_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3)
-#define WWLAN_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value)
-#define WWLAN_GET_FUNC_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1)
-#define WWLAN_SET_FUNC_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value)
-#define WWLAN_GET_PATTERM_MAT_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1)
-#define WWLAN_SET_PATTERM_MAT_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value)
-#define WWLAN_GET_MAGIC_PKT_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 10, 1)
-#define WWLAN_SET_MAGIC_PKT_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 10, 1, __Value)
-#define WWLAN_GET_UNICAST_WAKEUP_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 11, 1)
-#define WWLAN_SET_UNICAST_WAKEUP_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 11, 1, __Value)
-#define WWLAN_GET_ALL_PKT_DROP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 12, 1)
-#define WWLAN_SET_ALL_PKT_DROP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 12, 1, __Value)
-#define WWLAN_GET_GPIO_ACTIVE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 13, 1)
-#define WWLAN_SET_GPIO_ACTIVE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 13, 1, __Value)
-#define WWLAN_GET_REKEY_WAKEUP_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 14, 1)
-#define WWLAN_SET_REKEY_WAKEUP_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 14, 1, __Value)
-#define WWLAN_GET_DEAUTH_WAKEUP_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 15, 1)
-#define WWLAN_SET_DEAUTH_WAKEUP_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 15, 1, __Value)
-#define WWLAN_GET_GPIO_NUM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 7)
-#define WWLAN_SET_GPIO_NUM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 7, __Value)
-#define WWLAN_GET_DATAPIN_WAKEUP_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 23, 1)
-#define WWLAN_SET_DATAPIN_WAKEUP_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 23, 1, __Value)
-#define WWLAN_GET_GPIO_DURATION(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8)
-#define WWLAN_SET_GPIO_DURATION(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value)
-#define WWLAN_GET_GPIO_PLUS_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 1)
-#define WWLAN_SET_GPIO_PLUS_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 1, __Value)
-#define WWLAN_GET_GPIO_PULSE_COUNT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 1, 7)
-#define WWLAN_SET_GPIO_PULSE_COUNT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 1, 7, __Value)
-#define WWLAN_GET_DISABLE_UPHY(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 1)
-#define WWLAN_SET_DISABLE_UPHY(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 1, __Value)
-#define WWLAN_GET_HST2DEV_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 9, 1)
-#define WWLAN_SET_HST2DEV_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 9, 1, __Value)
-#define WWLAN_GET_GPIO_DURATION_MS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 10, 1)
-#define WWLAN_SET_GPIO_DURATION_MS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 10, 1, __Value)
-#define REMOTE_WAKE_CTRL_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4)
-#define REMOTE_WAKE_CTRL_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value)
-#define REMOTE_WAKE_CTRL_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3)
-#define REMOTE_WAKE_CTRL_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value)
-#define REMOTE_WAKE_CTRL_GET_REMOTE_WAKE_CTRL_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1)
-#define REMOTE_WAKE_CTRL_SET_REMOTE_WAKE_CTRL_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value)
-#define REMOTE_WAKE_CTRL_GET_ARP_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1)
-#define REMOTE_WAKE_CTRL_SET_ARP_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value)
-#define REMOTE_WAKE_CTRL_GET_NDP_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 10, 1)
-#define REMOTE_WAKE_CTRL_SET_NDP_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 10, 1, __Value)
-#define REMOTE_WAKE_CTRL_GET_GTK_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 11, 1)
-#define REMOTE_WAKE_CTRL_SET_GTK_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 11, 1, __Value)
-#define REMOTE_WAKE_CTRL_GET_NLO_OFFLOAD_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 12, 1)
-#define REMOTE_WAKE_CTRL_SET_NLO_OFFLOAD_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 12, 1, __Value)
-#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V1_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 13, 1)
-#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V1_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 13, 1, __Value)
-#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V2_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 14, 1)
-#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V2_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 14, 1, __Value)
-#define REMOTE_WAKE_CTRL_GET_FW_UNICAST(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 15, 1)
-#define REMOTE_WAKE_CTRL_SET_FW_UNICAST(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 15, 1, __Value)
-#define REMOTE_WAKE_CTRL_GET_P2P_OFFLOAD_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 1)
-#define REMOTE_WAKE_CTRL_SET_P2P_OFFLOAD_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 1, __Value)
-#define REMOTE_WAKE_CTRL_GET_RUNTIME_PM_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 17, 1)
-#define REMOTE_WAKE_CTRL_SET_RUNTIME_PM_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 17, 1, __Value)
-#define REMOTE_WAKE_CTRL_GET_NET_BIOS_DROP_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 18, 1)
-#define REMOTE_WAKE_CTRL_SET_NET_BIOS_DROP_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 18, 1, __Value)
-#define REMOTE_WAKE_CTRL_GET_ARP_ACTION(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 1)
-#define REMOTE_WAKE_CTRL_SET_ARP_ACTION(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 1, __Value)
-#define REMOTE_WAKE_CTRL_GET_FW_PARSING_UNTIL_WAKEUP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 28, 1)
-#define REMOTE_WAKE_CTRL_SET_FW_PARSING_UNTIL_WAKEUP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 28, 1, __Value)
-#define REMOTE_WAKE_CTRL_GET_FW_PARSING_AFTER_WAKEUP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 29, 1)
-#define REMOTE_WAKE_CTRL_SET_FW_PARSING_AFTER_WAKEUP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 29, 1, __Value)
-#define AOAC_BLOBAL_INFO_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4)
-#define AOAC_BLOBAL_INFO_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value)
-#define AOAC_BLOBAL_INFO_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3)
-#define AOAC_BLOBAL_INFO_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value)
-#define AOAC_BLOBAL_INFO_GET_PAIR_WISE_ENC_ALG(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8)
-#define AOAC_BLOBAL_INFO_SET_PAIR_WISE_ENC_ALG(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value)
-#define AOAC_BLOBAL_INFO_GET_GROUP_ENC_ALG(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8)
-#define AOAC_BLOBAL_INFO_SET_GROUP_ENC_ALG(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value)
-#define AOAC_RSVD_PAGE_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4)
-#define AOAC_RSVD_PAGE_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value)
-#define AOAC_RSVD_PAGE_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3)
-#define AOAC_RSVD_PAGE_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value)
-#define AOAC_RSVD_PAGE_GET_LOC_REMOTE_CTRL_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8)
-#define AOAC_RSVD_PAGE_SET_LOC_REMOTE_CTRL_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value)
-#define AOAC_RSVD_PAGE_GET_LOC_ARP_RESPONSE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8)
-#define AOAC_RSVD_PAGE_SET_LOC_ARP_RESPONSE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value)
-#define AOAC_RSVD_PAGE_GET_LOC_NEIGHBOR_ADVERTISEMENT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8)
-#define AOAC_RSVD_PAGE_SET_LOC_NEIGHBOR_ADVERTISEMENT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value)
-#define AOAC_RSVD_PAGE_GET_LOC_GTK_RSP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8)
-#define AOAC_RSVD_PAGE_SET_LOC_GTK_RSP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value)
-#define AOAC_RSVD_PAGE_GET_LOC_GTK_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8)
-#define AOAC_RSVD_PAGE_SET_LOC_GTK_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value)
-#define AOAC_RSVD_PAGE_GET_LOC_GTK_EXT_MEM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 8)
-#define AOAC_RSVD_PAGE_SET_LOC_GTK_EXT_MEM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 8, __Value)
-#define AOAC_RSVD_PAGE_GET_LOC_NDP_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 24, 8)
-#define AOAC_RSVD_PAGE_SET_LOC_NDP_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 24, 8, __Value)
-#define AOAC_RSVD_PAGE2_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4)
-#define AOAC_RSVD_PAGE2_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value)
-#define AOAC_RSVD_PAGE2_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3)
-#define AOAC_RSVD_PAGE2_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value)
-#define AOAC_RSVD_PAGE2_GET_LOC_ROUTER_SOLICATION(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8)
-#define AOAC_RSVD_PAGE2_SET_LOC_ROUTER_SOLICATION(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value)
-#define AOAC_RSVD_PAGE2_GET_LOC_BUBBLE_PACKET(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8)
-#define AOAC_RSVD_PAGE2_SET_LOC_BUBBLE_PACKET(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value)
-#define AOAC_RSVD_PAGE2_GET_LOC_TEREDO_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8)
-#define AOAC_RSVD_PAGE2_SET_LOC_TEREDO_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value)
-#define AOAC_RSVD_PAGE2_GET_LOC_REALWOW_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8)
-#define AOAC_RSVD_PAGE2_SET_LOC_REALWOW_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value)
-#define AOAC_RSVD_PAGE2_GET_LOC_KEEP_ALIVE_PKT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8)
-#define AOAC_RSVD_PAGE2_SET_LOC_KEEP_ALIVE_PKT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value)
-#define AOAC_RSVD_PAGE2_GET_LOC_ACK_PATTERN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 8)
-#define AOAC_RSVD_PAGE2_SET_LOC_ACK_PATTERN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 8, __Value)
-#define AOAC_RSVD_PAGE2_GET_LOC_WAKEUP_PATTERN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 24, 8)
-#define AOAC_RSVD_PAGE2_SET_LOC_WAKEUP_PATTERN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 24, 8, __Value)
-#define D0_SCAN_OFFLOAD_INFO_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4)
-#define D0_SCAN_OFFLOAD_INFO_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value)
-#define D0_SCAN_OFFLOAD_INFO_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3)
-#define D0_SCAN_OFFLOAD_INFO_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value)
-#define D0_SCAN_OFFLOAD_INFO_GET_LOC_CHANNEL_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8)
-#define D0_SCAN_OFFLOAD_INFO_SET_LOC_CHANNEL_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value)
-#define CHANNEL_SWITCH_OFFLOAD_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4)
-#define CHANNEL_SWITCH_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value)
-#define CHANNEL_SWITCH_OFFLOAD_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3)
-#define CHANNEL_SWITCH_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value)
-#define CHANNEL_SWITCH_OFFLOAD_GET_CHANNEL_NUM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8)
-#define CHANNEL_SWITCH_OFFLOAD_SET_CHANNEL_NUM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value)
-#define CHANNEL_SWITCH_OFFLOAD_GET_EN_RFE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8)
-#define CHANNEL_SWITCH_OFFLOAD_SET_EN_RFE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value)
-#define CHANNEL_SWITCH_OFFLOAD_GET_RFE_TYPE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8)
-#define CHANNEL_SWITCH_OFFLOAD_SET_RFE_TYPE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value)
-#define AOAC_RSVD_PAGE3_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 4)
-#define AOAC_RSVD_PAGE3_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 4, __Value)
-#define AOAC_RSVD_PAGE3_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3)
-#define AOAC_RSVD_PAGE3_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value)
-#define AOAC_RSVD_PAGE3_GET_LOC_NLO_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8)
-#define AOAC_RSVD_PAGE3_SET_LOC_NLO_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value)
-#define AOAC_RSVD_PAGE3_GET_LOC_AOAC_REPORT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8)
-#define AOAC_RSVD_PAGE3_SET_LOC_AOAC_REPORT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value)
+#define CLASS_DBG_MSG_CTRL 0X07
+#define ORIGINAL_H2C_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define ORIGINAL_H2C_SET_CMD_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define ORIGINAL_H2C_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define ORIGINAL_H2C_SET_CLASS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define H2C2H_LB_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define H2C2H_LB_SET_CMD_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define H2C2H_LB_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define H2C2H_LB_SET_CLASS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define H2C2H_LB_GET_SEQ(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define H2C2H_LB_SET_SEQ(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define H2C2H_LB_GET_PAYLOAD1(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 16)
+#define H2C2H_LB_SET_PAYLOAD1(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 16, value)
+#define H2C2H_LB_GET_PAYLOAD2(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 32)
+#define H2C2H_LB_SET_PAYLOAD2(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 32, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_CMD_ID(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define D0_SCAN_OFFLOAD_CTRL_SET_CMD_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_CLASS(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define D0_SCAN_OFFLOAD_CTRL_SET_CLASS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_D0_SCAN_FUN_EN(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1)
+#define D0_SCAN_OFFLOAD_CTRL_SET_D0_SCAN_FUN_EN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_RTD3FUN_EN(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1)
+#define D0_SCAN_OFFLOAD_CTRL_SET_RTD3FUN_EN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_U3_SCAN_FUN_EN(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1)
+#define D0_SCAN_OFFLOAD_CTRL_SET_U3_SCAN_FUN_EN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_NLO_FUN_EN(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 11, 1)
+#define D0_SCAN_OFFLOAD_CTRL_SET_NLO_FUN_EN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 11, 1, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_IPS_DEPENDENT(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 12, 1)
+#define D0_SCAN_OFFLOAD_CTRL_SET_IPS_DEPENDENT(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 12, 1, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_PROBE_PACKET(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 17)
+#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_PROBE_PACKET(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 17, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SCAN_INFO(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)
+#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SCAN_INFO(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)
+#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SSID_INFO(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8)
+#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SSID_INFO(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value)
+#define RSVD_PAGE_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define RSVD_PAGE_SET_CMD_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define RSVD_PAGE_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define RSVD_PAGE_SET_CLASS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define RSVD_PAGE_GET_LOC_PROBE_RSP(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define RSVD_PAGE_SET_LOC_PROBE_RSP(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define RSVD_PAGE_GET_LOC_PS_POLL(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)
+#define RSVD_PAGE_SET_LOC_PS_POLL(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)
+#define RSVD_PAGE_GET_LOC_NULL_DATA(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)
+#define RSVD_PAGE_SET_LOC_NULL_DATA(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)
+#define RSVD_PAGE_GET_LOC_QOS_NULL(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8)
+#define RSVD_PAGE_SET_LOC_QOS_NULL(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value)
+#define RSVD_PAGE_GET_LOC_BT_QOS_NULL(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8)
+#define RSVD_PAGE_SET_LOC_BT_QOS_NULL(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value)
+#define RSVD_PAGE_GET_LOC_CTS2SELF(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 8)
+#define RSVD_PAGE_SET_LOC_CTS2SELF(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 8, value)
+#define RSVD_PAGE_GET_LOC_LTECOEX_QOSNULL(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 24, 8)
+#define RSVD_PAGE_SET_LOC_LTECOEX_QOSNULL(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 8, value)
+#define MEDIA_STATUS_RPT_GET_CMD_ID(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define MEDIA_STATUS_RPT_SET_CMD_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define MEDIA_STATUS_RPT_GET_CLASS(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define MEDIA_STATUS_RPT_SET_CLASS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define MEDIA_STATUS_RPT_GET_OP_MODE(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1)
+#define MEDIA_STATUS_RPT_SET_OP_MODE(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value)
+#define MEDIA_STATUS_RPT_GET_MACID_IN(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1)
+#define MEDIA_STATUS_RPT_SET_MACID_IN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value)
+#define MEDIA_STATUS_RPT_GET_MACID(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)
+#define MEDIA_STATUS_RPT_SET_MACID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)
+#define MEDIA_STATUS_RPT_GET_MACID_END(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)
+#define MEDIA_STATUS_RPT_SET_MACID_END(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)
+#define KEEP_ALIVE_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define KEEP_ALIVE_SET_CMD_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define KEEP_ALIVE_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define KEEP_ALIVE_SET_CLASS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define KEEP_ALIVE_GET_ENABLE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1)
+#define KEEP_ALIVE_SET_ENABLE(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value)
+#define KEEP_ALIVE_GET_ADOPT_USER_SETTING(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1)
+#define KEEP_ALIVE_SET_ADOPT_USER_SETTING(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value)
+#define KEEP_ALIVE_GET_PKT_TYPE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1)
+#define KEEP_ALIVE_SET_PKT_TYPE(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value)
+#define KEEP_ALIVE_GET_KEEP_ALIVE_CHECK_PERIOD(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)
+#define KEEP_ALIVE_SET_KEEP_ALIVE_CHECK_PERIOD(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)
+#define DISCONNECT_DECISION_GET_CMD_ID(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define DISCONNECT_DECISION_SET_CMD_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define DISCONNECT_DECISION_GET_CLASS(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define DISCONNECT_DECISION_SET_CLASS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define DISCONNECT_DECISION_GET_ENABLE(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1)
+#define DISCONNECT_DECISION_SET_ENABLE(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value)
+#define DISCONNECT_DECISION_GET_ADOPT_USER_SETTING(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1)
+#define DISCONNECT_DECISION_SET_ADOPT_USER_SETTING(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value)
+#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_EN(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1)
+#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_EN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value)
+#define DISCONNECT_DECISION_GET_DISCONNECT_EN(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 11, 1)
+#define DISCONNECT_DECISION_SET_DISCONNECT_EN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 11, 1, value)
+#define DISCONNECT_DECISION_GET_DISCON_DECISION_CHECK_PERIOD(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)
+#define DISCONNECT_DECISION_SET_DISCON_DECISION_CHECK_PERIOD(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)
+#define DISCONNECT_DECISION_GET_TRY_PKT_NUM(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)
+#define DISCONNECT_DECISION_SET_TRY_PKT_NUM(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)
+#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_LIMIT(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8)
+#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_LIMIT(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value)
+#define AP_OFFLOAD_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define AP_OFFLOAD_SET_CMD_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define AP_OFFLOAD_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define AP_OFFLOAD_SET_CLASS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define AP_OFFLOAD_GET_ON(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1)
+#define AP_OFFLOAD_SET_ON(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value)
+#define AP_OFFLOAD_GET_CFG_MIFI_PLATFORM(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1)
+#define AP_OFFLOAD_SET_CFG_MIFI_PLATFORM(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value)
+#define AP_OFFLOAD_GET_LINKED(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1)
+#define AP_OFFLOAD_SET_LINKED(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value)
+#define AP_OFFLOAD_GET_EN_AUTO_WAKE(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 11, 1)
+#define AP_OFFLOAD_SET_EN_AUTO_WAKE(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 11, 1, value)
+#define AP_OFFLOAD_GET_WAKE_FLAG(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 12, 1)
+#define AP_OFFLOAD_SET_WAKE_FLAG(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 12, 1, value)
+#define AP_OFFLOAD_GET_HIDDEN_ROOT(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 1)
+#define AP_OFFLOAD_SET_HIDDEN_ROOT(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 1, value)
+#define AP_OFFLOAD_GET_HIDDEN_VAP1(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 17, 1)
+#define AP_OFFLOAD_SET_HIDDEN_VAP1(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 17, 1, value)
+#define AP_OFFLOAD_GET_HIDDEN_VAP2(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 18, 1)
+#define AP_OFFLOAD_SET_HIDDEN_VAP2(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 18, 1, value)
+#define AP_OFFLOAD_GET_HIDDEN_VAP3(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 19, 1)
+#define AP_OFFLOAD_SET_HIDDEN_VAP3(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 19, 1, value)
+#define AP_OFFLOAD_GET_HIDDEN_VAP4(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 20, 1)
+#define AP_OFFLOAD_SET_HIDDEN_VAP4(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 20, 1, value)
+#define AP_OFFLOAD_GET_DENYANY_ROOT(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 1)
+#define AP_OFFLOAD_SET_DENYANY_ROOT(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 1, value)
+#define AP_OFFLOAD_GET_DENYANY_VAP1(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 25, 1)
+#define AP_OFFLOAD_SET_DENYANY_VAP1(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 25, 1, value)
+#define AP_OFFLOAD_GET_DENYANY_VAP2(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 26, 1)
+#define AP_OFFLOAD_SET_DENYANY_VAP2(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 26, 1, value)
+#define AP_OFFLOAD_GET_DENYANY_VAP3(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 27, 1)
+#define AP_OFFLOAD_SET_DENYANY_VAP3(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 27, 1, value)
+#define AP_OFFLOAD_GET_DENYANY_VAP4(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 28, 1)
+#define AP_OFFLOAD_SET_DENYANY_VAP4(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 28, 1, value)
+#define AP_OFFLOAD_GET_WAIT_TBTT_CNT(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8)
+#define AP_OFFLOAD_SET_WAIT_TBTT_CNT(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value)
+#define AP_OFFLOAD_GET_WAKE_TIMEOUT(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8)
+#define AP_OFFLOAD_SET_WAKE_TIMEOUT(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value)
+#define AP_OFFLOAD_GET_LEN_IV_PAIR(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 8)
+#define AP_OFFLOAD_SET_LEN_IV_PAIR(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 8, value)
+#define AP_OFFLOAD_GET_LEN_IV_GRP(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 24, 8)
+#define AP_OFFLOAD_SET_LEN_IV_GRP(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 8, value)
+#define BCN_RSVDPAGE_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define BCN_RSVDPAGE_SET_CMD_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define BCN_RSVDPAGE_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define BCN_RSVDPAGE_SET_CLASS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define BCN_RSVDPAGE_GET_LOC_ROOT(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define BCN_RSVDPAGE_SET_LOC_ROOT(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define BCN_RSVDPAGE_GET_LOC_VAP1(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)
+#define BCN_RSVDPAGE_SET_LOC_VAP1(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)
+#define BCN_RSVDPAGE_GET_LOC_VAP2(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)
+#define BCN_RSVDPAGE_SET_LOC_VAP2(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)
+#define BCN_RSVDPAGE_GET_LOC_VAP3(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8)
+#define BCN_RSVDPAGE_SET_LOC_VAP3(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value)
+#define BCN_RSVDPAGE_GET_LOC_VAP4(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8)
+#define BCN_RSVDPAGE_SET_LOC_VAP4(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value)
+#define PROBE_RSP_RSVDPAGE_GET_CMD_ID(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define PROBE_RSP_RSVDPAGE_SET_CMD_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define PROBE_RSP_RSVDPAGE_GET_CLASS(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define PROBE_RSP_RSVDPAGE_SET_CLASS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define PROBE_RSP_RSVDPAGE_GET_LOC_ROOT(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define PROBE_RSP_RSVDPAGE_SET_LOC_ROOT(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP1(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)
+#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP1(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)
+#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP2(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)
+#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP2(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)
+#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP3(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8)
+#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP3(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value)
+#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP4(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8)
+#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP4(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value)
+#define SINGLE_CHANNELSWITCH_GET_CMD_ID(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define SINGLE_CHANNELSWITCH_SET_CMD_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define SINGLE_CHANNELSWITCH_GET_CLASS(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define SINGLE_CHANNELSWITCH_SET_CLASS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define SINGLE_CHANNELSWITCH_GET_CHANNEL_NUM(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define SINGLE_CHANNELSWITCH_SET_CHANNEL_NUM(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define SINGLE_CHANNELSWITCH_GET_BW(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 2)
+#define SINGLE_CHANNELSWITCH_SET_BW(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 2, value)
+#define SINGLE_CHANNELSWITCH_GET_BW40SC(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 18, 3)
+#define SINGLE_CHANNELSWITCH_SET_BW40SC(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 18, 3, value)
+#define SINGLE_CHANNELSWITCH_GET_BW80SC(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 21, 3)
+#define SINGLE_CHANNELSWITCH_SET_BW80SC(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 21, 3, value)
+#define SINGLE_CHANNELSWITCH_GET_RFE_TYPE(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 4)
+#define SINGLE_CHANNELSWITCH_SET_RFE_TYPE(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 4, value)
+#define SINGLE_CHANNELSWITCH_V2_GET_CMD_ID(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define SINGLE_CHANNELSWITCH_V2_SET_CMD_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define SINGLE_CHANNELSWITCH_V2_GET_CLASS(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define SINGLE_CHANNELSWITCH_V2_SET_CLASS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define SINGLE_CHANNELSWITCH_V2_GET_CENTRAL_CH(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define SINGLE_CHANNELSWITCH_V2_SET_CENTRAL_CH(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define SINGLE_CHANNELSWITCH_V2_GET_PRIMARY_CH_IDX(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 4)
+#define SINGLE_CHANNELSWITCH_V2_SET_PRIMARY_CH_IDX(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 4, value)
+#define SINGLE_CHANNELSWITCH_V2_GET_BW(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 20, 4)
+#define SINGLE_CHANNELSWITCH_V2_SET_BW(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 20, 4, value)
+#define SET_PWR_MODE_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define SET_PWR_MODE_SET_CMD_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define SET_PWR_MODE_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define SET_PWR_MODE_SET_CLASS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define SET_PWR_MODE_GET_MODE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 7)
+#define SET_PWR_MODE_SET_MODE(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 7, value)
+#define SET_PWR_MODE_GET_CLK_REQUEST(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 15, 1)
+#define SET_PWR_MODE_SET_CLK_REQUEST(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 15, 1, value)
+#define SET_PWR_MODE_GET_RLBM(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 4)
+#define SET_PWR_MODE_SET_RLBM(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 4, value)
+#define SET_PWR_MODE_GET_SMART_PS(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 20, 4)
+#define SET_PWR_MODE_SET_SMART_PS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 20, 4, value)
+#define SET_PWR_MODE_GET_AWAKE_INTERVAL(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)
+#define SET_PWR_MODE_SET_AWAKE_INTERVAL(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)
+#define SET_PWR_MODE_GET_B_ALL_QUEUE_UAPSD(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 1)
+#define SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 1, value)
+#define SET_PWR_MODE_GET_BCN_EARLY_RPT(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 2, 1)
+#define SET_PWR_MODE_SET_BCN_EARLY_RPT(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 2, 1, value)
+#define SET_PWR_MODE_GET_PORT_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 5, 3)
+#define SET_PWR_MODE_SET_PORT_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 5, 3, value)
+#define SET_PWR_MODE_GET_PWR_STATE(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8)
+#define SET_PWR_MODE_SET_PWR_STATE(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value)
+#define SET_PWR_MODE_GET_LOW_POWER_RX_BCN(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 1)
+#define SET_PWR_MODE_SET_LOW_POWER_RX_BCN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 1, value)
+#define SET_PWR_MODE_GET_ANT_AUTO_SWITCH(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 17, 1)
+#define SET_PWR_MODE_SET_ANT_AUTO_SWITCH(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 17, 1, value)
+#define SET_PWR_MODE_GET_PS_ALLOW_BT_HIGH_PRIORITY(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 18, 1)
+#define SET_PWR_MODE_SET_PS_ALLOW_BT_HIGH_PRIORITY(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 18, 1, value)
+#define SET_PWR_MODE_GET_PROTECT_BCN(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 19, 1)
+#define SET_PWR_MODE_SET_PROTECT_BCN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 19, 1, value)
+#define SET_PWR_MODE_GET_SILENCE_PERIOD(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 20, 1)
+#define SET_PWR_MODE_SET_SILENCE_PERIOD(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 20, 1, value)
+#define SET_PWR_MODE_GET_FAST_BT_CONNECT(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 21, 1)
+#define SET_PWR_MODE_SET_FAST_BT_CONNECT(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 21, 1, value)
+#define SET_PWR_MODE_GET_TWO_ANTENNA_EN(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 22, 1)
+#define SET_PWR_MODE_SET_TWO_ANTENNA_EN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 22, 1, value)
+#define SET_PWR_MODE_GET_ADOPT_USER_SETTING(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 24, 1)
+#define SET_PWR_MODE_SET_ADOPT_USER_SETTING(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 1, value)
+#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 25, 3)
+#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 25, 3, value)
+#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT2(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 28, 4)
+#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT2(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 28, 4, value)
+#define PS_TUNING_PARA_GET_CMD_ID(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define PS_TUNING_PARA_SET_CMD_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define PS_TUNING_PARA_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define PS_TUNING_PARA_SET_CLASS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define PS_TUNING_PARA_GET_BCN_TO_LIMIT(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 7)
+#define PS_TUNING_PARA_SET_BCN_TO_LIMIT(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 7, value)
+#define PS_TUNING_PARA_GET_DTIM_TIME_OUT(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 15, 1)
+#define PS_TUNING_PARA_SET_DTIM_TIME_OUT(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 15, 1, value)
+#define PS_TUNING_PARA_GET_PS_TIME_OUT(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 4)
+#define PS_TUNING_PARA_SET_PS_TIME_OUT(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 4, value)
+#define PS_TUNING_PARA_GET_ADOPT(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)
+#define PS_TUNING_PARA_SET_ADOPT(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)
+#define PS_TUNING_PARA_II_GET_CMD_ID(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define PS_TUNING_PARA_II_SET_CMD_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define PS_TUNING_PARA_II_GET_CLASS(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define PS_TUNING_PARA_II_SET_CLASS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define PS_TUNING_PARA_II_GET_BCN_TO_PERIOD(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 7)
+#define PS_TUNING_PARA_II_SET_BCN_TO_PERIOD(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 7, value)
+#define PS_TUNING_PARA_II_GET_ADOPT(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 15, 1)
+#define PS_TUNING_PARA_II_SET_ADOPT(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 15, 1, value)
+#define PS_TUNING_PARA_II_GET_DRV_EARLY_IVL(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)
+#define PS_TUNING_PARA_II_SET_DRV_EARLY_IVL(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)
+#define PS_LPS_PARA_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define PS_LPS_PARA_SET_CMD_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define PS_LPS_PARA_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define PS_LPS_PARA_SET_CLASS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define PS_LPS_PARA_GET_LPS_CONTROL(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define PS_LPS_PARA_SET_LPS_CONTROL(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define P2P_PS_OFFLOAD_GET_CMD_ID(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define P2P_PS_OFFLOAD_SET_CMD_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define P2P_PS_OFFLOAD_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define P2P_PS_OFFLOAD_SET_CLASS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define P2P_PS_OFFLOAD_GET_OFFLOAD_EN(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1)
+#define P2P_PS_OFFLOAD_SET_OFFLOAD_EN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value)
+#define P2P_PS_OFFLOAD_GET_ROLE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1)
+#define P2P_PS_OFFLOAD_SET_ROLE(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value)
+#define P2P_PS_OFFLOAD_GET_CTWINDOW_EN(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1)
+#define P2P_PS_OFFLOAD_SET_CTWINDOW_EN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value)
+#define P2P_PS_OFFLOAD_GET_NOA0_EN(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 11, 1)
+#define P2P_PS_OFFLOAD_SET_NOA0_EN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 11, 1, value)
+#define P2P_PS_OFFLOAD_GET_NOA1_EN(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 12, 1)
+#define P2P_PS_OFFLOAD_SET_NOA1_EN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 12, 1, value)
+#define P2P_PS_OFFLOAD_GET_ALL_STA_SLEEP(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 13, 1)
+#define P2P_PS_OFFLOAD_SET_ALL_STA_SLEEP(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 13, 1, value)
+#define P2P_PS_OFFLOAD_GET_DISCOVERY(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 14, 1)
+#define P2P_PS_OFFLOAD_SET_DISCOVERY(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 14, 1, value)
+#define PS_SCAN_EN_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define PS_SCAN_EN_SET_CMD_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define PS_SCAN_EN_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define PS_SCAN_EN_SET_CLASS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define PS_SCAN_EN_GET_ENABLE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1)
+#define PS_SCAN_EN_SET_ENABLE(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value)
+#define SAP_PS_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define SAP_PS_SET_CMD_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define SAP_PS_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define SAP_PS_SET_CLASS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define SAP_PS_GET_ENABLE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1)
+#define SAP_PS_SET_ENABLE(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value)
+#define SAP_PS_GET_EN_PS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1)
+#define SAP_PS_SET_EN_PS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value)
+#define SAP_PS_GET_EN_LP_RX(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1)
+#define SAP_PS_SET_EN_LP_RX(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value)
+#define SAP_PS_GET_MANUAL_32K(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 11, 1)
+#define SAP_PS_SET_MANUAL_32K(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 11, 1, value)
+#define SAP_PS_GET_DURATION(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)
+#define SAP_PS_SET_DURATION(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)
+#define INACTIVE_PS_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define INACTIVE_PS_SET_CMD_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define INACTIVE_PS_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define INACTIVE_PS_SET_CLASS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define INACTIVE_PS_GET_ENABLE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1)
+#define INACTIVE_PS_SET_ENABLE(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value)
+#define INACTIVE_PS_GET_IGNORE_PS_CONDITION(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1)
+#define INACTIVE_PS_SET_IGNORE_PS_CONDITION(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value)
+#define INACTIVE_PS_GET_FREQUENCY(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)
+#define INACTIVE_PS_SET_FREQUENCY(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)
+#define INACTIVE_PS_GET_DURATION(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)
+#define INACTIVE_PS_SET_DURATION(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)
+#define MACID_CFG_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define MACID_CFG_SET_CMD_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define MACID_CFG_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define MACID_CFG_SET_CLASS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define MACID_CFG_GET_MAC_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define MACID_CFG_SET_MAC_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define MACID_CFG_GET_RATE_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 5)
+#define MACID_CFG_SET_RATE_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 5, value)
+#define MACID_CFG_GET_INIT_RATE_LV(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 21, 2)
+#define MACID_CFG_SET_INIT_RATE_LV(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 21, 2, value)
+#define MACID_CFG_GET_SGI(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 23, 1)
+#define MACID_CFG_SET_SGI(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 23, 1, value)
+#define MACID_CFG_GET_BW(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 2)
+#define MACID_CFG_SET_BW(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 2, value)
+#define MACID_CFG_GET_LDPC_CAP(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 26, 1)
+#define MACID_CFG_SET_LDPC_CAP(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 26, 1, value)
+#define MACID_CFG_GET_NO_UPDATE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 27, 1)
+#define MACID_CFG_SET_NO_UPDATE(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 27, 1, value)
+#define MACID_CFG_GET_WHT_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 28, 2)
+#define MACID_CFG_SET_WHT_EN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 28, 2, value)
+#define MACID_CFG_GET_DISPT(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 30, 1)
+#define MACID_CFG_SET_DISPT(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 30, 1, value)
+#define MACID_CFG_GET_DISRA(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 31, 1)
+#define MACID_CFG_SET_DISRA(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 31, 1, value)
+#define MACID_CFG_GET_RATE_MASK7_0(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8)
+#define MACID_CFG_SET_RATE_MASK7_0(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value)
+#define MACID_CFG_GET_RATE_MASK15_8(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8)
+#define MACID_CFG_SET_RATE_MASK15_8(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value)
+#define MACID_CFG_GET_RATE_MASK23_16(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 8)
+#define MACID_CFG_SET_RATE_MASK23_16(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 8, value)
+#define MACID_CFG_GET_RATE_MASK31_24(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 24, 8)
+#define MACID_CFG_SET_RATE_MASK31_24(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 8, value)
+#define TXBF_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define TXBF_SET_CMD_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define TXBF_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define TXBF_SET_CLASS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define TXBF_GET_NDPA0_HEAD_PAGE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define TXBF_SET_NDPA0_HEAD_PAGE(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define TXBF_GET_NDPA1_HEAD_PAGE(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)
+#define TXBF_SET_NDPA1_HEAD_PAGE(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)
+#define TXBF_GET_PERIOD_0(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)
+#define TXBF_SET_PERIOD_0(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)
+#define RSSI_SETTING_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define RSSI_SETTING_SET_CMD_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define RSSI_SETTING_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define RSSI_SETTING_SET_CLASS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define RSSI_SETTING_GET_MAC_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define RSSI_SETTING_SET_MAC_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define RSSI_SETTING_GET_RSSI(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 7)
+#define RSSI_SETTING_SET_RSSI(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 7, value)
+#define RSSI_SETTING_GET_RA_INFO(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8)
+#define RSSI_SETTING_SET_RA_INFO(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value)
+#define AP_REQ_TXRPT_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define AP_REQ_TXRPT_SET_CMD_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define AP_REQ_TXRPT_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define AP_REQ_TXRPT_SET_CLASS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define AP_REQ_TXRPT_GET_STA1_MACID(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define AP_REQ_TXRPT_SET_STA1_MACID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define AP_REQ_TXRPT_GET_STA2_MACID(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)
+#define AP_REQ_TXRPT_SET_STA2_MACID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)
+#define AP_REQ_TXRPT_GET_RTY_OK_TOTAL(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 1)
+#define AP_REQ_TXRPT_SET_RTY_OK_TOTAL(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 1, value)
+#define AP_REQ_TXRPT_GET_RTY_CNT_MACID(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 25, 1)
+#define AP_REQ_TXRPT_SET_RTY_CNT_MACID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 25, 1, value)
+#define INIT_RATE_COLLECTION_GET_CMD_ID(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define INIT_RATE_COLLECTION_SET_CMD_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define INIT_RATE_COLLECTION_GET_CLASS(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define INIT_RATE_COLLECTION_SET_CLASS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define INIT_RATE_COLLECTION_GET_STA1_MACID(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define INIT_RATE_COLLECTION_SET_STA1_MACID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define INIT_RATE_COLLECTION_GET_STA2_MACID(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)
+#define INIT_RATE_COLLECTION_SET_STA2_MACID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)
+#define INIT_RATE_COLLECTION_GET_STA3_MACID(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)
+#define INIT_RATE_COLLECTION_SET_STA3_MACID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)
+#define INIT_RATE_COLLECTION_GET_STA4_MACID(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8)
+#define INIT_RATE_COLLECTION_SET_STA4_MACID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value)
+#define INIT_RATE_COLLECTION_GET_STA5_MACID(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8)
+#define INIT_RATE_COLLECTION_SET_STA5_MACID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value)
+#define INIT_RATE_COLLECTION_GET_STA6_MACID(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 8)
+#define INIT_RATE_COLLECTION_SET_STA6_MACID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 8, value)
+#define INIT_RATE_COLLECTION_GET_STA7_MACID(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 24, 8)
+#define INIT_RATE_COLLECTION_SET_STA7_MACID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 8, value)
+#define IQK_OFFLOAD_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define IQK_OFFLOAD_SET_CMD_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define IQK_OFFLOAD_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define IQK_OFFLOAD_SET_CLASS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define IQK_OFFLOAD_GET_CHANNEL(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define IQK_OFFLOAD_SET_CHANNEL(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define IQK_OFFLOAD_GET_BWBAND(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)
+#define IQK_OFFLOAD_SET_BWBAND(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)
+#define IQK_OFFLOAD_GET_EXTPALNA(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)
+#define IQK_OFFLOAD_SET_EXTPALNA(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)
+#define MACID_CFG_3SS_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define MACID_CFG_3SS_SET_CMD_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define MACID_CFG_3SS_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define MACID_CFG_3SS_SET_CLASS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define MACID_CFG_3SS_GET_MACID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define MACID_CFG_3SS_SET_MACID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define MACID_CFG_3SS_GET_RATE_MASK_39_32(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8)
+#define MACID_CFG_3SS_SET_RATE_MASK_39_32(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value)
+#define MACID_CFG_3SS_GET_RATE_MASK_47_40(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8)
+#define MACID_CFG_3SS_SET_RATE_MASK_47_40(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value)
+#define RA_PARA_ADJUST_GET_CMD_ID(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define RA_PARA_ADJUST_SET_CMD_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define RA_PARA_ADJUST_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define RA_PARA_ADJUST_SET_CLASS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define RA_PARA_ADJUST_GET_MAC_ID(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define RA_PARA_ADJUST_SET_MAC_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define RA_PARA_ADJUST_GET_PARAMETER_INDEX(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)
+#define RA_PARA_ADJUST_SET_PARAMETER_INDEX(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)
+#define RA_PARA_ADJUST_GET_RATE_ID(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)
+#define RA_PARA_ADJUST_SET_RATE_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)
+#define RA_PARA_ADJUST_GET_VALUE_BYTE0(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8)
+#define RA_PARA_ADJUST_SET_VALUE_BYTE0(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value)
+#define RA_PARA_ADJUST_GET_VALUE_BYTE1(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8)
+#define RA_PARA_ADJUST_SET_VALUE_BYTE1(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value)
+#define RA_PARA_ADJUST_GET_ASK_FW_FOR_FW_PARA(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 8)
+#define RA_PARA_ADJUST_SET_ASK_FW_FOR_FW_PARA(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 8, value)
+#define WWLAN_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define WWLAN_SET_CMD_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define WWLAN_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define WWLAN_SET_CLASS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define WWLAN_GET_FUNC_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1)
+#define WWLAN_SET_FUNC_EN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value)
+#define WWLAN_GET_PATTERM_MAT_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1)
+#define WWLAN_SET_PATTERM_MAT_EN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value)
+#define WWLAN_GET_MAGIC_PKT_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1)
+#define WWLAN_SET_MAGIC_PKT_EN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value)
+#define WWLAN_GET_UNICAST_WAKEUP_EN(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 11, 1)
+#define WWLAN_SET_UNICAST_WAKEUP_EN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 11, 1, value)
+#define WWLAN_GET_ALL_PKT_DROP(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 12, 1)
+#define WWLAN_SET_ALL_PKT_DROP(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 12, 1, value)
+#define WWLAN_GET_GPIO_ACTIVE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 13, 1)
+#define WWLAN_SET_GPIO_ACTIVE(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 13, 1, value)
+#define WWLAN_GET_REKEY_WAKEUP_EN(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 14, 1)
+#define WWLAN_SET_REKEY_WAKEUP_EN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 14, 1, value)
+#define WWLAN_GET_DEAUTH_WAKEUP_EN(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 15, 1)
+#define WWLAN_SET_DEAUTH_WAKEUP_EN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 15, 1, value)
+#define WWLAN_GET_GPIO_NUM(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 7)
+#define WWLAN_SET_GPIO_NUM(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 7, value)
+#define WWLAN_GET_DATAPIN_WAKEUP_EN(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 23, 1)
+#define WWLAN_SET_DATAPIN_WAKEUP_EN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 23, 1, value)
+#define WWLAN_GET_GPIO_DURATION(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)
+#define WWLAN_SET_GPIO_DURATION(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)
+#define WWLAN_GET_GPIO_PLUS_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 1)
+#define WWLAN_SET_GPIO_PLUS_EN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 1, value)
+#define WWLAN_GET_GPIO_PULSE_COUNT(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 1, 7)
+#define WWLAN_SET_GPIO_PULSE_COUNT(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 1, 7, value)
+#define WWLAN_GET_DISABLE_UPHY(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 1)
+#define WWLAN_SET_DISABLE_UPHY(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 1, value)
+#define WWLAN_GET_HST2DEV_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 9, 1)
+#define WWLAN_SET_HST2DEV_EN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 9, 1, value)
+#define WWLAN_GET_GPIO_DURATION_MS(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 10, 1)
+#define WWLAN_SET_GPIO_DURATION_MS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 10, 1, value)
+#define REMOTE_WAKE_CTRL_GET_CMD_ID(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define REMOTE_WAKE_CTRL_SET_CMD_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define REMOTE_WAKE_CTRL_GET_CLASS(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define REMOTE_WAKE_CTRL_SET_CLASS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define REMOTE_WAKE_CTRL_GET_REMOTE_WAKE_CTRL_EN(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1)
+#define REMOTE_WAKE_CTRL_SET_REMOTE_WAKE_CTRL_EN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value)
+#define REMOTE_WAKE_CTRL_GET_ARP_EN(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 9, 1)
+#define REMOTE_WAKE_CTRL_SET_ARP_EN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 9, 1, value)
+#define REMOTE_WAKE_CTRL_GET_NDP_EN(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 10, 1)
+#define REMOTE_WAKE_CTRL_SET_NDP_EN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 10, 1, value)
+#define REMOTE_WAKE_CTRL_GET_GTK_EN(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 11, 1)
+#define REMOTE_WAKE_CTRL_SET_GTK_EN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 11, 1, value)
+#define REMOTE_WAKE_CTRL_GET_NLO_OFFLOAD_EN(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 12, 1)
+#define REMOTE_WAKE_CTRL_SET_NLO_OFFLOAD_EN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 12, 1, value)
+#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V1_EN(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 13, 1)
+#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V1_EN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 13, 1, value)
+#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V2_EN(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 14, 1)
+#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V2_EN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 14, 1, value)
+#define REMOTE_WAKE_CTRL_GET_FW_UNICAST(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 15, 1)
+#define REMOTE_WAKE_CTRL_SET_FW_UNICAST(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 15, 1, value)
+#define REMOTE_WAKE_CTRL_GET_P2P_OFFLOAD_EN(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 1)
+#define REMOTE_WAKE_CTRL_SET_P2P_OFFLOAD_EN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 1, value)
+#define REMOTE_WAKE_CTRL_GET_RUNTIME_PM_EN(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 17, 1)
+#define REMOTE_WAKE_CTRL_SET_RUNTIME_PM_EN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 17, 1, value)
+#define REMOTE_WAKE_CTRL_GET_NET_BIOS_DROP_EN(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 18, 1)
+#define REMOTE_WAKE_CTRL_SET_NET_BIOS_DROP_EN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 18, 1, value)
+#define REMOTE_WAKE_CTRL_GET_ARP_ACTION(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 1)
+#define REMOTE_WAKE_CTRL_SET_ARP_ACTION(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 1, value)
+#define REMOTE_WAKE_CTRL_GET_FW_PARSING_UNTIL_WAKEUP(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 28, 1)
+#define REMOTE_WAKE_CTRL_SET_FW_PARSING_UNTIL_WAKEUP(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 28, 1, value)
+#define REMOTE_WAKE_CTRL_GET_FW_PARSING_AFTER_WAKEUP(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 29, 1)
+#define REMOTE_WAKE_CTRL_SET_FW_PARSING_AFTER_WAKEUP(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 29, 1, value)
+#define AOAC_GLOBAL_INFO_GET_CMD_ID(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define AOAC_GLOBAL_INFO_SET_CMD_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define AOAC_GLOBAL_INFO_GET_CLASS(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define AOAC_GLOBAL_INFO_SET_CLASS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define AOAC_GLOBAL_INFO_GET_PAIR_WISE_ENC_ALG(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define AOAC_GLOBAL_INFO_SET_PAIR_WISE_ENC_ALG(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define AOAC_GLOBAL_INFO_GET_GROUP_ENC_ALG(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)
+#define AOAC_GLOBAL_INFO_SET_GROUP_ENC_ALG(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)
+#define AOAC_RSVD_PAGE_GET_CMD_ID(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define AOAC_RSVD_PAGE_SET_CMD_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define AOAC_RSVD_PAGE_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define AOAC_RSVD_PAGE_SET_CLASS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define AOAC_RSVD_PAGE_GET_LOC_REMOTE_CTRL_INFO(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define AOAC_RSVD_PAGE_SET_LOC_REMOTE_CTRL_INFO(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define AOAC_RSVD_PAGE_GET_LOC_ARP_RESPONSE(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)
+#define AOAC_RSVD_PAGE_SET_LOC_ARP_RESPONSE(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)
+#define AOAC_RSVD_PAGE_GET_LOC_NEIGHBOR_ADVERTISEMENT(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)
+#define AOAC_RSVD_PAGE_SET_LOC_NEIGHBOR_ADVERTISEMENT(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)
+#define AOAC_RSVD_PAGE_GET_LOC_GTK_RSP(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8)
+#define AOAC_RSVD_PAGE_SET_LOC_GTK_RSP(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value)
+#define AOAC_RSVD_PAGE_GET_LOC_GTK_INFO(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8)
+#define AOAC_RSVD_PAGE_SET_LOC_GTK_INFO(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value)
+#define AOAC_RSVD_PAGE_GET_LOC_GTK_EXT_MEM(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 8)
+#define AOAC_RSVD_PAGE_SET_LOC_GTK_EXT_MEM(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 8, value)
+#define AOAC_RSVD_PAGE_GET_LOC_NDP_INFO(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 24, 8)
+#define AOAC_RSVD_PAGE_SET_LOC_NDP_INFO(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 8, value)
+#define AOAC_RSVD_PAGE2_GET_CMD_ID(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define AOAC_RSVD_PAGE2_SET_CMD_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define AOAC_RSVD_PAGE2_GET_CLASS(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define AOAC_RSVD_PAGE2_SET_CLASS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define AOAC_RSVD_PAGE2_GET_LOC_ROUTER_SOLICATION(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define AOAC_RSVD_PAGE2_SET_LOC_ROUTER_SOLICATION(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define AOAC_RSVD_PAGE2_GET_LOC_BUBBLE_PACKET(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)
+#define AOAC_RSVD_PAGE2_SET_LOC_BUBBLE_PACKET(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)
+#define AOAC_RSVD_PAGE2_GET_LOC_TEREDO_INFO(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)
+#define AOAC_RSVD_PAGE2_SET_LOC_TEREDO_INFO(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)
+#define AOAC_RSVD_PAGE2_GET_LOC_REALWOW_INFO(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 0, 8)
+#define AOAC_RSVD_PAGE2_SET_LOC_REALWOW_INFO(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 0, 8, value)
+#define AOAC_RSVD_PAGE2_GET_LOC_KEEP_ALIVE_PKT(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 8, 8)
+#define AOAC_RSVD_PAGE2_SET_LOC_KEEP_ALIVE_PKT(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 8, 8, value)
+#define AOAC_RSVD_PAGE2_GET_LOC_ACK_PATTERN(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 16, 8)
+#define AOAC_RSVD_PAGE2_SET_LOC_ACK_PATTERN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 16, 8, value)
+#define AOAC_RSVD_PAGE2_GET_LOC_WAKEUP_PATTERN(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X04, 24, 8)
+#define AOAC_RSVD_PAGE2_SET_LOC_WAKEUP_PATTERN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X04, 24, 8, value)
+#define D0_SCAN_OFFLOAD_INFO_GET_CMD_ID(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define D0_SCAN_OFFLOAD_INFO_SET_CMD_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define D0_SCAN_OFFLOAD_INFO_GET_CLASS(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define D0_SCAN_OFFLOAD_INFO_SET_CLASS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define D0_SCAN_OFFLOAD_INFO_GET_LOC_CHANNEL_INFO(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define D0_SCAN_OFFLOAD_INFO_SET_LOC_CHANNEL_INFO(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define CHANNEL_SWITCH_OFFLOAD_GET_CMD_ID(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define CHANNEL_SWITCH_OFFLOAD_SET_CMD_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define CHANNEL_SWITCH_OFFLOAD_GET_CLASS(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define CHANNEL_SWITCH_OFFLOAD_SET_CLASS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define CHANNEL_SWITCH_OFFLOAD_GET_CHANNEL_NUM(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define CHANNEL_SWITCH_OFFLOAD_SET_CHANNEL_NUM(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define CHANNEL_SWITCH_OFFLOAD_GET_EN_RFE(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)
+#define CHANNEL_SWITCH_OFFLOAD_SET_EN_RFE(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)
+#define CHANNEL_SWITCH_OFFLOAD_GET_RFE_TYPE(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 24, 8)
+#define CHANNEL_SWITCH_OFFLOAD_SET_RFE_TYPE(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 24, 8, value)
+#define AOAC_RSVD_PAGE3_GET_CMD_ID(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define AOAC_RSVD_PAGE3_SET_CMD_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define AOAC_RSVD_PAGE3_GET_CLASS(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define AOAC_RSVD_PAGE3_SET_CLASS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define AOAC_RSVD_PAGE3_GET_LOC_NLO_INFO(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 8)
+#define AOAC_RSVD_PAGE3_SET_LOC_NLO_INFO(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 8, value)
+#define AOAC_RSVD_PAGE3_GET_LOC_AOAC_REPORT(h2c_pkt) \
+ LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 16, 8)
+#define AOAC_RSVD_PAGE3_SET_LOC_AOAC_REPORT(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 16, 8, value)
+#define DBG_MSG_CTRL_GET_CMD_ID(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 0, 5)
+#define DBG_MSG_CTRL_SET_CMD_ID(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 0, 5, value)
+#define DBG_MSG_CTRL_GET_CLASS(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 5, 3)
+#define DBG_MSG_CTRL_SET_CLASS(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 5, 3, value)
+#define DBG_MSG_CTRL_GET_FUN_EN(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 8, 1)
+#define DBG_MSG_CTRL_SET_FUN_EN(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 8, 1, value)
+#define DBG_MSG_CTRL_GET_MODE(h2c_pkt) LE_BITS_TO_4BYTE(h2c_pkt + 0X00, 12, 4)
+#define DBG_MSG_CTRL_SET_MODE(h2c_pkt, value) \
+ SET_BITS_TO_LE_4BYTE(h2c_pkt + 0X00, 12, 4, value)
#endif
diff --git a/hal/halmac/halmac_pcie_reg.h b/hal/halmac/halmac_pcie_reg.h
index 8808e7b..a2406be 100644
--- a/hal/halmac/halmac_pcie_reg.h
+++ b/hal/halmac/halmac_pcie_reg.h
@@ -1,8 +1,36 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
#ifndef __HALMAC_PCIE_REG_H__
#define __HALMAC_PCIE_REG_H__
+/* PCIE PHY register */
+#define RAC_CTRL_PPR 0x00
+#define RAC_SET_PPR 0x20
+#define RAC_TRG_PPR 0x21
+/* PCIE CFG register */
+#define PCIE_L1_BACKDOOR 0x719
+#define PCIE_ASPM_CTRL 0x70F
+/* PCIE MAC register */
+#define LINK_CTRL2_REG_OFFSET 0xA0
+#define GEN2_CTRL_OFFSET 0x80C
+#define LINK_STATUS_REG_OFFSET 0x82
+#define PCIE_GEN1_SPEED 0x01
+#define PCIE_GEN2_SPEED 0x02
#endif/* __HALMAC_PCIE_REG_H__ */
diff --git a/hal/halmac/halmac_pwr_seq_cmd.h b/hal/halmac/halmac_pwr_seq_cmd.h
index 0367fe3..23d5dbe 100644
--- a/hal/halmac/halmac_pwr_seq_cmd.h
+++ b/hal/halmac/halmac_pwr_seq_cmd.h
@@ -1,81 +1,88 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
#ifndef HALMAC_POWER_SEQUENCE_CMD
#define HALMAC_POWER_SEQUENCE_CMD
#include "halmac_2_platform.h"
-#include "halmac_type.h"
-#define HALMAC_POLLING_READY_TIMEOUT_COUNT 10000
+#define HALMAC_PWR_POLLING_CNT 20000
/*
-* The value of cmd : 4 bits
-*/
+ * The value of cmd : 4 bits
+ */
/*
-* offset : the read register offset
-* msk : the mask of the read value
-* value : N/A, left by 0
-* Note : dirver shall implement this function by read & msk
-*/
+ * offset : the read register offset
+ * msk : the mask of the read value
+ * value : N/A, left by 0
+ * Note : dirver shall implement this function by read & msk
+ */
#define HALMAC_PWR_CMD_READ 0x00
/*
-* offset: the read register offset
-* msk: the mask of the write bits
-* value: write value
-* Note: driver shall implement this cmd by read & msk after write
-*/
+ * offset: the read register offset
+ * msk: the mask of the write bits
+ * value: write value
+ * Note: driver shall implement this cmd by read & msk after write
+ */
#define HALMAC_PWR_CMD_WRITE 0x01
/*
-* offset: the read register offset
-* msk: the mask of the polled value
-* value: the value to be polled, masked by the msd field.
-* Note: driver shall implement this cmd by
-* do{
-* if( (Read(offset) & msk) == (value & msk) )
-* break;
-* } while(not timeout);
-*/
+ * offset: the read register offset
+ * msk: the mask of the polled value
+ * value: the value to be polled, masked by the msd field.
+ * Note: driver shall implement this cmd by
+ * do{
+ * if( (Read(offset) & msk) == (value & msk) )
+ * break;
+ * } while(not timeout);
+ */
#define HALMAC_PWR_CMD_POLLING 0x02
/*
-* offset: the value to delay
-* msk: N/A
-* value: the unit of delay, 0: us, 1: ms
-*/
+ * offset: the value to delay
+ * msk: N/A
+ * value: the unit of delay, 0: us, 1: ms
+ */
#define HALMAC_PWR_CMD_DELAY 0x03
/*
-* offset: N/A
-* msk: N/A
-* value: N/A
-*/
-#define HALMAC_PWR_CMD_END 0x04
+ * offset: N/A
+ * msk: N/A
+ * value: N/A
+ */
+#define HALMAC_PWR_CMD_END 0x04
/*
-* The value of base : 4 bits
-*/
+ * The value of base : 4 bits
+ */
/* define the base address of each block */
-#define HALMAC_PWR_BASEADDR_MAC 0x00
-#define HALMAC_PWR_BASEADDR_USB 0x01
-#define HALMAC_PWR_BASEADDR_PCIE 0x02
-#define HALMAC_PWR_BASEADDR_SDIO 0x03
+#define HALMAC_PWR_ADDR_MAC 0x00
+#define HALMAC_PWR_ADDR_USB 0x01
+#define HALMAC_PWR_ADDR_PCIE 0x02
+#define HALMAC_PWR_ADDR_SDIO 0x03
/*
-* The value of interface_msk : 4 bits
-*/
+ * The value of interface_msk : 4 bits
+ */
#define HALMAC_PWR_INTF_SDIO_MSK BIT(0)
#define HALMAC_PWR_INTF_USB_MSK BIT(1)
#define HALMAC_PWR_INTF_PCI_MSK BIT(2)
-#define HALMAC_PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
-
-/*
-* The value of fab_msk : 4 bits
-*/
-#define HALMAC_PWR_FAB_TSMC_MSK BIT(0)
-#define HALMAC_PWR_FAB_UMC_MSK BIT(1)
-#define HALMAC_PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
+#define HALMAC_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
/*
-* The value of cut_msk : 8 bits
-*/
+ * The value of cut_msk : 8 bits
+ */
#define HALMAC_PWR_CUT_TESTCHIP_MSK BIT(0)
#define HALMAC_PWR_CUT_A_MSK BIT(1)
#define HALMAC_PWR_CUT_B_MSK BIT(2)
@@ -86,21 +93,19 @@
#define HALMAC_PWR_CUT_G_MSK BIT(7)
#define HALMAC_PWR_CUT_ALL_MSK 0xFF
-typedef enum _HALMAC_PWRSEQ_CMD_DELAY_UNIT_ {
- HALMAC_PWRSEQ_DELAY_US,
- HALMAC_PWRSEQ_DELAY_MS,
-} HALMAC_PWRSEQ_DELAY_UNIT;
+enum halmac_pwrseq_cmd_delay_unit {
+ HALMAC_PWR_DELAY_US,
+ HALMAC_PWR_DELAY_MS,
+};
-/* Don't care endian issue, because element of pwer seq vector is fixed address */
-typedef struct _HALMAC_WL_PWR_CFG_ {
+struct halmac_wlan_pwr_cfg {
u16 offset;
- u8 cut_msk;
- u8 fab_msk:4;
- u8 interface_msk:4;
- u8 base:4;
- u8 cmd:4;
- u8 msk;
- u8 value;
-} HALMAC_WLAN_PWR_CFG, *PHALMAC_WLAN_PWR_CFG;
+ u8 cut_msk;
+ u8 interface_msk;
+ u8 base:4;
+ u8 cmd:4;
+ u8 msk;
+ u8 value;
+};
#endif
diff --git a/hal/halmac/halmac_reg2.h b/hal/halmac/halmac_reg2.h
index 9f0c31c..f20eaa4 100644
--- a/hal/halmac/halmac_reg2.h
+++ b/hal/halmac/halmac_reg2.h
@@ -1,2913 +1,6882 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
#ifndef __HALMAC_COM_REG_H__
#define __HALMAC_COM_REG_H__
-/*-------------------------Modification Log-----------------------------------
- For Page0, it is based on Combo_And_WL_Only_Page0_Reg.xls SVN524
- The supported IC are 8723A, 8881A, 8723B, 8192E, 8881A
- 8812A and 8188E is not included in page0 register
-
- For other pages, it is based on MAC_Register.doc SVN502
- Most IC is the same with 8812A
--------------------------Modification Log-----------------------------------*/
-/*--------------------------Include File--------------------------------------*/
#include "halmac_hw_cfg.h"
-/*--------------------------Include File--------------------------------------*/
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+#define REG_SYS_ISO_CTRL 0x0000
+#endif
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define REG_SYS_ISO_CTRL 0x0000
+#define REG_SDIO_TX_CTRL 0x10250000
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_SDIO_TX_CTRL 0x10250000
+#define REG_SYS_FUNC_EN 0x0002
+#define REG_SYS_PW_CTRL 0x0004
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_SYS_FUNC_EN 0x0002
-#define REG_SYS_PW_CTRL 0x0004
-#define REG_SYS_CLK_CTRL 0x0008
-#define REG_SYS_EEPROM_CTRL 0x000A
-#define REG_EE_VPD 0x000C
-#define REG_SYS_SWR_CTRL1 0x0010
-#define REG_SYS_SWR_CTRL2 0x0014
+#define REG_SDIO_CMD11_VOL_SWITCH 0x10250004
+#define REG_SDIO_DRIVING 0x10250006
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_SDIO_HIMR 0x10250014
+#define REG_SYS_CLK_CTRL 0x0008
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_SYS_SWR_CTRL3 0x0018
+#define REG_SDIO_MONITOR 0x10250008
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_SDIO_HISR 0x10250018
+#define REG_SYS_EEPROM_CTRL 0x000A
+#define REG_EE_VPD 0x000C
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_RSV_CTRL 0x001C
+#define REG_SDIO_MONITOR_2 0x1025000C
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_SDIO_RX_REQ_LEN 0x1025001C
+#define REG_SYS_SWR_CTRL1 0x0010
+#define REG_SYS_SWR_CTRL2 0x0014
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_RF_CTRL 0x001F
+#define REG_SDIO_HIMR 0x10250014
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
-#define REG_RF0_CTRL 0x001F
+#define REG_SYS_SWR_CTRL3 0x0018
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_SDIO_FREE_TXPG_SEQ_V1 0x1025001F
+#define REG_SDIO_HISR 0x10250018
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_AFE_LDO_CTRL 0x0020
+#define REG_RSV_CTRL 0x001C
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_SDIO_FREE_TXPG 0x10250020
+#define REG_SDIO_RX_REQ_LEN 0x1025001C
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_AFE_CTRL1 0x0024
+#define REG_RF_CTRL 0x001F
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_SDIO_FREE_TXPG2 0x10250024
+#define REG_RF0_CTRL 0x001F
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_AFE_CTRL2 0x0028
+#define REG_SDIO_FREE_TXPG_SEQ_V1 0x1025001F
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_SDIO_OQT_FREE_TXPG_V1 0x10250028
+#define REG_AFE_LDO_CTRL 0x0020
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_AFE_CTRL3 0x002C
-#define REG_EFUSE_CTRL 0x0030
+#define REG_SDIO_FREE_TXPG 0x10250020
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_SDIO_HTSFR_INFO 0x10250030
+#define REG_AFE_CTRL1 0x0024
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_LDO_EFUSE_CTRL 0x0034
-#define REG_PWR_OPTION_CTRL 0x0038
+#define REG_SDIO_FREE_TXPG2 0x10250024
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_SDIO_HCPWM1_V2 0x10250038
-#define REG_SDIO_HCPWM2_V2 0x1025003A
+#define REG_AFE_CTRL2 0x0028
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_OQT_FREE_TXPG_V1 0x10250028
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define REG_CAL_TIMER 0x003C
-#define REG_ACLK_MON 0x003E
-#define REG_GPIO_MUXCFG 0x0040
+#define REG_ANAPARSW_POW_MAC 0x0028
+#define REG_ANAPARLDO_POW_MAC 0x0029
+#define REG_ANAPAR_POW_MAC 0x002A
+#define REG_ANAPAR_POW_XTAL 0x002B
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_AFE_CTRL3 0x002C
+
+#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define REG_SDIO_INDIRECT_REG_CFG 0x10250040
+#define REG_ANAPARLDO_MAC 0x002C
#endif
+#if (HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_TXPKT_EMPTY 0x1025002C
+
+#endif
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define REG_GPIO_PIN_CTRL 0x0044
+#define REG_EFUSE_CTRL 0x0030
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#define REG_SDIO_HTSFR_INFO 0x10250030
-#define REG_SDIO_INDIRECT_REG_DATA 0x10250044
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_LDO_EFUSE_CTRL 0x0034
+#define REG_PWR_OPTION_CTRL 0x0038
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_HCPWM1_V2 0x10250038
+#define REG_SDIO_HCPWM2_V2 0x1025003A
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define REG_GPIO_INTM 0x0048
-#define REG_LED_CFG 0x004C
-#define REG_FSIMR 0x0050
-#define REG_FSISR 0x0054
-#define REG_HSIMR 0x0058
-#define REG_HSISR 0x005C
-#define REG_GPIO_EXT_CTRL 0x0060
+#define REG_CAL_TIMER 0x003C
+#define REG_ACLK_MON 0x003E
#endif
+#if (HALMAC_8822C_SUPPORT)
+
+#define REG_GPIO_MUXCFG_2 0x003F
+
+#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define REG_SDIO_H2C 0x10250060
+#define REG_GPIO_MUXCFG 0x0040
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_INDIRECT_REG_CFG 0x10250040
+
+#endif
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define REG_PAD_CTRL1 0x0064
+#define REG_GPIO_PIN_CTRL 0x0044
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#define REG_SDIO_INDIRECT_REG_DATA 0x10250044
-#define REG_SDIO_C2H 0x10250064
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_GPIO_INTM 0x0048
+#define REG_LED_CFG 0x004C
+#define REG_FSIMR 0x0050
+#define REG_FSISR 0x0054
+#define REG_HSIMR 0x0058
+#define REG_HSISR 0x005C
+#define REG_GPIO_EXT_CTRL 0x0060
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_H2C 0x10250060
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define REG_WL_BT_PWR_CTRL 0x0068
+#define REG_PAD_CTRL1 0x0064
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_C2H 0x10250064
+
+#endif
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define REG_SDM_DEBUG 0x006C
+#define REG_WL_BT_PWR_CTRL 0x0068
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_SDM_DEBUG 0x006C
+
+#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define REG_GSSR 0x006C
+#define REG_GSSR 0x006C
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_SYS_SDIO_CTRL 0x0070
+#define REG_SYS_SDIO_CTRL 0x0070
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define REG_SYS_CLKR 0x0070
+#define REG_SYS_CLKR 0x0070
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_HCI_OPT_CTRL 0x0074
+#define REG_HCI_OPT_CTRL 0x0074
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_AFE_CTRL4 0x0078
+#define REG_AFE_CTRL4 0x0078
#endif
-
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define REG_AFE_XTAL_CTRL_EXT 0x0078
+#define REG_AFE_XTAL_CTRL_EXT 0x0078
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_LDO_SWR_CTRL 0x007C
+#define REG_HCI_BG_CTRL 0x0078
+#define REG_HCI_LDO_CTRL 0x007A
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_LDO_SWR_CTRL 0x007C
+
+#endif
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define REG_8051FW_CTRL 0x0080
+#define REG_8051FW_CTRL 0x0080
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_MCUFW_CTRL 0x0080
+#define REG_MCUFW_CTRL 0x0080
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_SDIO_HRPWM1 0x10250080
-#define REG_SDIO_HRPWM2 0x10250082
+#define REG_SDIO_HRPWM1 0x10250080
+#define REG_SDIO_HRPWM2 0x10250082
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_MCU_TST_CFG 0x0084
+#define REG_MCU_TST_CFG 0x0084
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_SDIO_HPS_CLKR 0x10250084
-#define REG_SDIO_BUS_CTRL 0x10250085
+#define REG_SDIO_HPS_CLKR 0x10250084
+#define REG_SDIO_BUS_CTRL 0x10250085
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_SDIO_HSUS_CTRL 0x10250086
+#define REG_SDIO_HSUS_CTRL 0x10250086
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_HMEBOX_E0_E1 0x0088
+#define REG_HMEBOX_E0_E1 0x0088
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_SDIO_RESPONSE_TIMER 0x10250088
+#define REG_SDIO_RESPONSE_TIMER 0x10250088
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_SDIO_CMD_CRC 0x1025008A
+#define REG_SDIO_CMD_CRC 0x1025008A
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_HMEBOX_E2_E3 0x008C
-#define REG_WLLPS_CTRL 0x0090
+#define REG_HMEBOX_E2_E3 0x008C
+#define REG_WLLPS_CTRL 0x0090
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_SDIO_HSISR 0x10250090
-#define REG_SDIO_HSIMR 0x10250091
+#define REG_SDIO_HSISR 0x10250090
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_AFE_CTRL5 0x0094
+#define REG_SDIO_HSIMR 0x10250091
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_GPIO_DEBOUNCE_CTRL 0x0098
-#define REG_RPWM2 0x009C
-#define REG_SYSON_FSM_MON 0x00A0
+#define REG_AFE_CTRL5 0x0094
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_AFE_CTRL6 0x00A4
+#define REG_GPIO_DEBOUNCE_CTRL 0x0098
+#define REG_RPWM2 0x009C
+#define REG_SYSON_FSM_MON 0x00A0
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_PMC_DBG_CTRL1 0x00A8
+#define REG_AFE_CTRL6 0x00A4
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_AFE_CTRL7 0x00AC
+#define REG_PMC_DBG_CTRL1 0x00A8
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_HIMR0 0x00B0
-#define REG_HISR0 0x00B4
-#define REG_HIMR1 0x00B8
-#define REG_HISR1 0x00BC
-#define REG_DBG_PORT_SEL 0x00C0
+#define REG_AFE_CTRL7 0x00AC
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_SDIO_ERR_RPT 0x102500C0
-#define REG_SDIO_CMD_ERRCNT 0x102500C1
-#define REG_SDIO_DATA_ERRCNT 0x102500C2
+#define REG_HIMR0 0x00B0
+#define REG_HISR0 0x00B4
+#define REG_HIMR1 0x00B8
+#define REG_HISR1 0x00BC
+#define REG_DBG_PORT_SEL 0x00C0
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+#define REG_SDIO_ERR_RPT 0x102500C0
+
+#endif
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#if (HALMAC_8822C_SUPPORT)
-#define REG_PAD_CTRL2 0x00C4
+#define REG_SDIO_DIOERR_RPT 0x102500C0
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#define REG_SDIO_CMD_ERRCNT 0x102500C2
+#define REG_SDIO_DATA_ERRCNT 0x102500C3
-#define REG_SDIO_CMD_ERR_CONTENT 0x102500C4
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_PAD_CTRL2 0x00C4
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_CMD_ERR_CONTENT 0x102500C4
+
+#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define REG_MEM_RMC 0x00C8
+#define REG_MEM_RMC 0x00C8
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_CRC_ERR_IDX 0x102500C9
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define REG_SDIO_DATA_CRC 0x102500CA
+
+#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-#define REG_SDIO_CRC_ERR_IDX 0x102500C9
-#define REG_SDIO_DATA_CRC 0x102500CA
-#define REG_SDIO_DATA_REPLY_TIME 0x102500CB
+#define REG_SDIO_DATA_REPLY_TIME 0x102500CB
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_PMC_DBG_CTRL2 0x00CC
+
+#endif
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#if (HALMAC_8822C_SUPPORT)
-#define REG_PMC_DBG_CTRL2 0x00CC
-#define REG_BIST_CTRL 0x00D0
-#define REG_BIST_RPT 0x00D4
-#define REG_MEM_CTRL 0x00D8
+#define REG_SDIO_TRANS_FIFO_STATUS 0x102500CC
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#define REG_BIST_CTRL 0x00D0
+#define REG_BIST_RPT 0x00D4
-#define REG_AFE_CTRL8 0x00DC
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_MEM_CTRL 0x00D8
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
+
+#define REG_AFE_CTRL8 0x00DC
+
+#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define REG_WLAN_DBG 0x00DC
+#define REG_WLAN_DBG 0x00DC
#endif
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_SYN_RFC_CTRL 0x00DC
+
+#endif
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define REG_USB_SIE_INTF 0x00E0
-#define REG_PCIE_MIO_INTF 0x00E4
-#define REG_PCIE_MIO_INTD 0x00E8
+#define REG_USB_SIE_INTF 0x00E0
#endif
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_SYS_PINMUX 0x00E0
+
+#endif
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define REG_WLRF1 0x00EC
+#define REG_PCIE_MIO_INTF 0x00E4
+#define REG_PCIE_MIO_INTD 0x00E8
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_WLRF1 0x00EC
+
+#endif
#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#define REG_HPON_FSM 0x00EC
+#define REG_HPON_FSM 0x00EC
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_SYS_CFG1 0x00F0
-#define REG_SYS_STATUS1 0x00F4
-#define REG_SYS_STATUS2 0x00F8
-#define REG_SYS_CFG2 0x00FC
-#define REG_CR 0x0100
+#define REG_SYS_CFG1 0x00F0
+#define REG_SYS_STATUS1 0x00F4
+#define REG_SYS_STATUS2 0x00F8
+#define REG_SYS_CFG2 0x00FC
+#define REG_CR 0x0100
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_PKT_BUFF_ACCESS_CTRL 0x0106
+#define REG_PG_SIZE 0x0104
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_TSF_CLK_STATE 0x0108
-#define REG_TXDMA_PQ_MAP 0x010C
-#define REG_TRXFF_BNDY 0x0114
+#define REG_PKT_BUFF_ACCESS_CTRL 0x0106
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_PTA_I2C_MBOX 0x0118
+#define REG_TSF_CLK_STATE 0x0108
+#define REG_TXDMA_PQ_MAP 0x010C
+#define REG_TRXFF_BNDY 0x0114
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_PTA_I2C_MBOX 0x0118
+
+#endif
#if (HALMAC_8814A_SUPPORT)
-#define REG_FF_STATUS 0x0118
+#define REG_FF_STATUS 0x0118
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8881A_SUPPORT)
-#define REG_RXFF_PTR 0x011C
+#define REG_RXFF_PTR 0x011C
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_RXFF_BNDY 0x011C
+#define REG_RXFF_BNDY 0x011C
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define REG_FEIMR 0x0120
+#define REG_FEIMR 0x0120
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_FE1IMR 0x0120
+#define REG_FE1IMR 0x0120
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define REG_FEISR 0x0124
+#define REG_FEISR 0x0124
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_FE1ISR 0x0124
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define REG_FE1ISR 0x0124
+#define REG_CPWM 0x012C
+#define REG_FWIMR 0x0130
+#define REG_FWISR 0x0134
+#define REG_FTIMR 0x0138
+#define REG_FTISR 0x013C
+#define REG_PKTBUF_DBG_CTRL 0x0140
+#define REG_PKTBUF_DBG_DATA_L 0x0144
+#define REG_PKTBUF_DBG_DATA_H 0x0148
+#define REG_CPWM2 0x014C
+#define REG_TC0_CTRL 0x0150
+#define REG_TC1_CTRL 0x0154
+#define REG_TC2_CTRL 0x0158
+#define REG_TC3_CTRL 0x015C
+#define REG_TC4_CTRL 0x0160
+#define REG_TCUNIT_BASE 0x0164
+#define REG_TC5_CTRL 0x0168
+#define REG_TC6_CTRL 0x016C
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_MBIST_FAIL 0x0170
+
+#endif
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define REG_CPWM 0x012C
-#define REG_FWIMR 0x0130
-#define REG_FWISR 0x0134
-#define REG_FTIMR 0x0138
-#define REG_FTISR 0x013C
-#define REG_PKTBUF_DBG_CTRL 0x0140
-#define REG_PKTBUF_DBG_DATA_L 0x0144
-#define REG_PKTBUF_DBG_DATA_H 0x0148
-#define REG_CPWM2 0x014C
-#define REG_TC0_CTRL 0x0150
-#define REG_TC1_CTRL 0x0154
-#define REG_TC2_CTRL 0x0158
-#define REG_TC3_CTRL 0x015C
-#define REG_TC4_CTRL 0x0160
-#define REG_TCUNIT_BASE 0x0164
-#define REG_TC5_CTRL 0x0168
-#define REG_TC6_CTRL 0x016C
-#define REG_MBIST_FAIL 0x0170
-#define REG_MBIST_START_PAUSE 0x0174
-#define REG_MBIST_DONE 0x0178
+#define REG_MBIST_DRF_FAIL 0x0170
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_MBIST_START_PAUSE 0x0174
+#define REG_MBIST_DONE 0x0178
+
+#endif
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define REG_MBIST_ROM_CRC_DATA 0x017C
+#define REG_MBIST_ROM_CRC_DATA 0x017C
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_MBIST_FAIL_NRML 0x017C
+#define REG_MBIST_FAIL_NRML 0x017C
#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_MBIST_READ_BIST_RPT 0x017C
+
+#endif
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define REG_AES_DECRPT_DATA 0x0180
-#define REG_AES_DECRPT_CFG 0x0184
+#define REG_AES_DECRPT_DATA 0x0180
+#define REG_AES_DECRPT_CFG 0x0184
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
+#define REG_HIOE_CTRL 0x0188
-#define REG_MACCLKFRQ 0x018C
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_MACCLKFRQ 0x018C
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_HIOE_CFG_FILE 0x018C
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define REG_TMETER 0x0190
-#define REG_OSC_32K_CTRL 0x0194
-#define REG_32K_CAL_REG1 0x0198
-#define REG_C2HEVT 0x01A0
+#define REG_TMETER 0x0190
+#define REG_OSC_32K_CTRL 0x0194
+#define REG_32K_CAL_REG1 0x0198
+#define REG_C2HEVT 0x01A0
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define REG_C2HEVT_1 0x01A4
+#define REG_C2HEVT_2 0x01A8
+#define REG_C2HEVT_3 0x01AC
+
+#endif
#if (HALMAC_8814A_SUPPORT)
-#define REG_TC7_CTRL 0x01B0
-#define REG_TC8_CTRL 0x01B4
+#define REG_TC7_CTRL 0x01B0
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_SW_DEFINED_PAGE1 0x01B8
-#define REG_MCUTST_I 0x01C0
-#define REG_MCUTST_II 0x01C4
-#define REG_FMETHR 0x01C8
-#define REG_HMETFR 0x01CC
-#define REG_HMEBOX0 0x01D0
-#define REG_HMEBOX1 0x01D4
-#define REG_HMEBOX2 0x01D8
-#define REG_HMEBOX3 0x01DC
-#define REG_LLT_INIT 0x01E0
+#define REG_RXDESC_BUFF_RPTR 0x01B0
#endif
+#if (HALMAC_8814A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+#define REG_TC8_CTRL 0x01B4
-#define REG_GENTST 0x01E4
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_RXDESC_BUFF_WPTR 0x01B4
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_SW_DEFINED_PAGE1 0x01B8
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define REG_LLT_INIT_ADDR 0x01E4
+#define REG_SW_DEFINED_PAGE2 0x01BC
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_MCUTST_I 0x01C0
+#define REG_MCUTST_II 0x01C4
+#define REG_FMETHR 0x01C8
+#define REG_HMETFR 0x01CC
+#define REG_HMEBOX0 0x01D0
+#define REG_HMEBOX1 0x01D4
+#define REG_HMEBOX2 0x01D8
+#define REG_HMEBOX3 0x01DC
+
+#endif
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#define REG_BB_ACCESS_CTRL 0x01E8
-#define REG_BB_ACCESS_DATA 0x01EC
-#define REG_HMEBOX_E0 0x01F0
-#define REG_HMEBOX_E1 0x01F4
-#define REG_HMEBOX_E2 0x01F8
-#define REG_HMEBOX_E3 0x01FC
+#define REG_LLT_INIT 0x01E0
#endif
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_RXDESC_BUFF_BNDY 0x01E0
+
+#endif
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define REG_RQPN_CTRL_HLPQ 0x0200
+#define REG_GENTST 0x01E4
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_FIFOPAGE_CTRL_1 0x0200
+#define REG_LLT_INIT_ADDR 0x01E4
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_BB_ACCESS_CTRL 0x01E8
+#define REG_BB_ACCESS_DATA 0x01EC
+#define REG_HMEBOX_E0 0x01F0
+#define REG_HMEBOX_E1 0x01F4
+#define REG_HMEBOX_E2 0x01F8
+#define REG_HMEBOX_E3 0x01FC
+
+#endif
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define REG_FIFOPAGE_INFO 0x0204
+#define REG_RQPN_CTRL_HLPQ 0x0200
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_FIFOPAGE_CTRL_2 0x0204
+#define REG_FIFOPAGE_CTRL_1 0x0200
#endif
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_BCN_CTRL_0 0x0200
+
+#endif
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define REG_DWBCN0_CTRL 0x0208
+#define REG_FIFOPAGE_INFO 0x0204
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#define REG_FIFOPAGE_CTRL_2 0x0204
-#define REG_AUTO_LLT_V1 0x0208
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_BCN_CTRL_1 0x0204
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_DWBCN0_CTRL 0x0208
+
+#endif
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#define REG_TXDMA_OFFSET_CHK 0x020C
-#define REG_TXDMA_STATUS 0x0210
+#define REG_AUTO_LLT_V1 0x0208
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_TXDMA_OFFSET_CHK 0x020C
+#define REG_TXDMA_STATUS 0x0210
+
+#endif
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define REG_RQPN_NPQ 0x0214
+#define REG_RQPN_NPQ 0x0214
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_TX_DMA_DBG 0x0214
+
+#endif
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define REG_TX_DMA_DBG 0x0214
+#define REG_TQPNT1 0x0218
#endif
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_DMA_RQPN_INFO_PUB 0x0218
+
+#endif
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#define REG_TQPNT1 0x0218
-#define REG_TQPNT2 0x021C
+#define REG_TQPNT2 0x021C
#endif
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_RQPN_CTRL_2_V1 0x021C
+
+#endif
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define REG_TDE_DEBUG 0x0220
+#define REG_TDE_DEBUG 0x0220
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_TQPNT3 0x0220
+#define REG_TQPNT3 0x0220
#endif
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_BCN_CTRL_2 0x0220
+
+#endif
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define REG_AUTO_LLT 0x0224
+#define REG_AUTO_LLT 0x0224
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_TQPNT4 0x0224
+#define REG_TQPNT4 0x0224
#endif
-
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define REG_DWBCN1_CTRL 0x0228
+#define REG_DWBCN1_CTRL 0x0228
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_RQPN_CTRL_1 0x0228
-#define REG_RQPN_CTRL_2 0x022C
-#define REG_FIFOPAGE_INFO_1 0x0230
-#define REG_FIFOPAGE_INFO_2 0x0234
-#define REG_FIFOPAGE_INFO_3 0x0238
-#define REG_FIFOPAGE_INFO_4 0x023C
-#define REG_FIFOPAGE_INFO_5 0x0240
+#define REG_RQPN_CTRL_1 0x0228
+#define REG_RQPN_CTRL_2 0x022C
+#define REG_FIFOPAGE_INFO_1 0x0230
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_H2C_HEAD 0x0244
-#define REG_H2C_TAIL 0x0248
-#define REG_H2C_READ_ADDR 0x024C
-#define REG_H2C_WR_ADDR 0x0250
-#define REG_H2C_INFO 0x0254
+#define REG_TXPKTNUM_0 0x0230
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_RXDMA_AGG_PG_TH 0x0280
-#define REG_RXPKT_NUM 0x0284
-#define REG_RXDMA_STATUS 0x0288
-#define REG_RXDMA_DPR 0x028C
-#define REG_RXDMA_MODE 0x0290
-#define REG_C2H_PKT 0x0294
+#define REG_FIFOPAGE_INFO_2 0x0234
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_FWFF_C2H 0x0298
-#define REG_FWFF_CTRL 0x029C
-#define REG_FWFF_PKT_INFO 0x02A0
+#define REG_TXPKTNUM_1 0x0234
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
-#define REG_FC2H_INFO 0x02A6
+#define REG_FIFOPAGE_INFO_3 0x0238
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_PCIE_CTRL 0x0300
+#define REG_TXPKTNUM_2 0x0238
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
-#define REG_HCI_CTRL 0x0300
+#define REG_FIFOPAGE_INFO_4 0x023C
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8881A_SUPPORT)
-
-#define REG_LX_CTRL1 0x0300
+#define REG_TXPKTNUM_3 0x023C
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_INT_MIG 0x0304
-#define REG_BCNQ_TXBD_DESA 0x0308
-#define REG_MGQ_TXBD_DESA 0x0310
-#define REG_VOQ_TXBD_DESA 0x0318
-#define REG_VIQ_TXBD_DESA 0x0320
-#define REG_BEQ_TXBD_DESA 0x0328
-#define REG_BKQ_TXBD_DESA 0x0330
-#define REG_RXQ_RXBD_DESA 0x0338
-#define REG_HI0Q_TXBD_DESA 0x0340
-#define REG_HI1Q_TXBD_DESA 0x0348
-#define REG_HI2Q_TXBD_DESA 0x0350
-#define REG_HI3Q_TXBD_DESA 0x0358
-#define REG_HI4Q_TXBD_DESA 0x0360
-#define REG_HI5Q_TXBD_DESA 0x0368
-#define REG_HI6Q_TXBD_DESA 0x0370
-#define REG_HI7Q_TXBD_DESA 0x0378
-#define REG_MGQ_TXBD_NUM 0x0380
-#define REG_RX_RXBD_NUM 0x0382
-#define REG_VOQ_TXBD_NUM 0x0384
-#define REG_VIQ_TXBD_NUM 0x0386
-#define REG_BEQ_TXBD_NUM 0x0388
-#define REG_BKQ_TXBD_NUM 0x038A
-#define REG_HI0Q_TXBD_NUM 0x038C
-#define REG_HI1Q_TXBD_NUM 0x038E
-#define REG_HI2Q_TXBD_NUM 0x0390
-#define REG_HI3Q_TXBD_NUM 0x0392
-#define REG_HI4Q_TXBD_NUM 0x0394
-#define REG_HI5Q_TXBD_NUM 0x0396
-#define REG_HI6Q_TXBD_NUM 0x0398
-#define REG_HI7Q_TXBD_NUM 0x039A
-#define REG_TSFTIMER_HCI 0x039C
-#define REG_BD_RWPTR_CLR 0x039C
-#define REG_VOQ_TXBD_IDX 0x03A0
-#define REG_VIQ_TXBD_IDX 0x03A4
-#define REG_BEQ_TXBD_IDX 0x03A8
-#define REG_BKQ_TXBD_IDX 0x03AC
-#define REG_MGQ_TXBD_IDX 0x03B0
-#define REG_RXQ_RXBD_IDX 0x03B4
-#define REG_HI0Q_TXBD_IDX 0x03B8
-#define REG_HI1Q_TXBD_IDX 0x03BC
-#define REG_HI2Q_TXBD_IDX 0x03C0
-#define REG_HI3Q_TXBD_IDX 0x03C4
-#define REG_HI4Q_TXBD_IDX 0x03C8
-#define REG_HI5Q_TXBD_IDX 0x03CC
-#define REG_HI6Q_TXBD_IDX 0x03D0
-#define REG_HI7Q_TXBD_IDX 0x03D4
+#define REG_FIFOPAGE_INFO_5 0x0240
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_DBG_SEL_V1 0x03D8
+#define REG_TX_AGG_ALIGN 0x0240
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_PCIE_HRPWM1_V1 0x03D9
+#define REG_H2C_HEAD 0x0244
+#define REG_H2C_TAIL 0x0248
+#define REG_H2C_READ_ADDR 0x024C
+#define REG_H2C_WR_ADDR 0x0250
+#define REG_H2C_INFO 0x0254
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
-#define REG_HCI_HRPWM1_V1 0x03D9
+#define REG_TQPNT5 0x0260
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_PCIE_HCPWM1_V1 0x03DA
+#define REG_DMA_OQT_0 0x0260
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
-#define REG_HCI_HCPWM1_V1 0x03DA
+#define REG_TQPNT6 0x0264
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_PCIE_CTRL2 0x03DB
+#define REG_DMA_OQT_1 0x0264
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
-#define REG_HCI_CTRL2 0x03DB
+#define REG_FIFOPAGE_INFO_6 0x0268
+#define REG_FIFOPAGE_INFO_7 0x026C
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8881A_SUPPORT)
-
-#define REG_LX_CTRL2 0x03DB
+#define REG_PGSUB_CNT 0x026C
+#define REG_PGSUB_H 0x0270
+#define REG_PGSUB_N 0x0274
+#define REG_PGSUB_L 0x0278
+#define REG_PGSUB_E 0x027C
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_PCIE_HRPWM2_V1 0x03DC
+#define REG_RXDMA_AGG_PG_TH 0x0280
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
-#define REG_HCI_HRPWM2_V1 0x03DC
+#define REG_RXPKT_NUM 0x0284
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_PCIE_HCPWM2_V1 0x03DE
+#define REG_RXDMA_CTRL 0x0284
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
-#define REG_HCI_HCPWM2_V1 0x03DE
+#define REG_RXDMA_STATUS 0x0288
+#define REG_RXDMA_DPR 0x028C
+#define REG_RXDMA_MODE 0x0290
+#define REG_C2H_PKT 0x0294
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_PCIE_H2C_MSG_V1 0x03E0
+#define REG_FWFF_C2H 0x0298
+#define REG_FWFF_CTRL 0x029C
+#define REG_FWFF_PKT_INFO 0x02A0
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
-#define REG_HCI_H2C_MSG_V1 0x03E0
+#define REG_FC2H_INFO 0x02A4
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_PCIE_C2H_MSG_V1 0x03E4
+#define REG_FWFF_PKT_INFO2 0x02A4
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
-#define REG_HCI_C2H_MSG_V1 0x03E4
+#define REG_RXPKTNUM 0x02B0
+#define REG_RXPKTNUM_TH 0x02B4
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_DBI_WDATA_V1 0x03E8
+#define REG_FW_UPD_RXDES_RDPTR 0x02B8
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8881A_SUPPORT)
-
-#define REG_LX_DMA_ISR 0x03E8
+#define REG_FW_MSG1 0x02E0
+#define REG_FW_MSG2 0x02E4
+#define REG_FW_MSG3 0x02E8
+#define REG_FW_MSG4 0x02EC
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_DBI_RDATA_V1 0x03EC
+#define REG_PCIE_CTRL 0x0300
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_HCI_CTRL 0x0300
+
+#endif
#if (HALMAC_8881A_SUPPORT)
-#define REG_LX_DMA_IMR 0x03EC
+#define REG_LX_CTRL1 0x0300
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_DBI_FLAG_V1 0x03F0
+#define REG_INT_MIG 0x0304
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
-#define REG_STUCK_FLAG_V1 0x03F0
+#define REG_ACH_CTRL 0x0304
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8881A_SUPPORT)
-
-#define REG_LX_DMA_DBG 0x03F0
+#define REG_BCNQ_TXBD_DESA 0x0308
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_MDIO_V1 0x03F4
+#define REG_HIQ_CTRL 0x0308
+#define REG_INT_MIG_V1 0x030C
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
-#define REG_WDT_CFG 0x03F8
+#define REG_MGQ_TXBD_DESA 0x0310
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_PCIE_MIX_CFG 0x03F8
+#define REG_P0MGQ_TXBD_DESA_L 0x0310
+#define REG_P0MGQ_TXBD_DESA_H 0x0314
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8881A_SUPPORT)
+#define REG_VOQ_TXBD_DESA 0x0318
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
-#define REG_BUS_MIX_CFG 0x03F8
+#define REG_ACH0_TXBD_DESA_L 0x0318
+#define REG_ACH0_TXBD_DESA_H 0x031C
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_VIQ_TXBD_DESA 0x0320
+
+#endif
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+#if (HALMAC_8814B_SUPPORT)
-#define REG_HCI_MIX_CFG 0x03FC
+#define REG_ACH1_TXBD_DESA_L 0x0320
+#define REG_ACH1_TXBD_DESA_H 0x0324
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
-#if (HALMAC_8881A_SUPPORT)
+#define REG_BEQ_TXBD_DESA 0x0328
+
+#endif
-#define REG_BUS_MIX_CFG1 0x03FC
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ACH2_TXBD_DESA_L 0x0328
+#define REG_ACH2_TXBD_DESA_H 0x032C
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BKQ_TXBD_DESA 0x0330
+
+#endif
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+#if (HALMAC_8814B_SUPPORT)
-#define REG_Q0_INFO 0x0400
-#define REG_Q1_INFO 0x0404
-#define REG_Q2_INFO 0x0408
-#define REG_Q3_INFO 0x040C
-#define REG_MGQ_INFO 0x0410
-#define REG_HIQ_INFO 0x0414
-#define REG_BCNQ_INFO 0x0418
-#define REG_TXPKT_EMPTY 0x041A
-#define REG_CPU_MGQ_INFO 0x041C
-#define REG_FWHW_TXQ_CTRL 0x0420
+#define REG_ACH3_TXBD_DESA_L 0x0330
+#define REG_ACH3_TXBD_DESA_H 0x0334
#endif
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_RXQ_RXBD_DESA 0x0338
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0RXQ_RXBD_DESA_L 0x0338
+#define REG_P0RXQ_RXBD_DESA_H 0x033C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HI0Q_TXBD_DESA 0x0340
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0BCNQ_TXBD_DESA_L 0x0340
+#define REG_P0BCNQ_TXBD_DESA_H 0x0344
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HI1Q_TXBD_DESA 0x0348
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_FWCMDQ_TXBD_DESA_L 0x0348
+#define REG_FWCMDQ_TXBD_DESA_H 0x034C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HI2Q_TXBD_DESA 0x0350
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_PCIE_HRPWM1_HCPWM1_DCPU 0x0354
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HI3Q_TXBD_DESA 0x0358
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0_MPRT_BCNQ_TXBD_DESA_L 0x0358
+#define REG_P0_MPRT_BCNQ_TXBD_DESA_H 0x035C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HI4Q_TXBD_DESA 0x0360
+#define REG_HI5Q_TXBD_DESA 0x0368
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0_MPRT_BCNQ_TXRXBD_NUM 0x036C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HI6Q_TXBD_DESA 0x0370
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_BD_RWPTR_CLR2 0x0370
+#define REG_BD_RWPTR_CLR3 0x0374
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HI7Q_TXBD_DESA 0x0378
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0MGQ_RXQ_TXRXBD_NUM 0x0378
+#define REG_CHNL_DMA_CFG 0x037C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_MGQ_TXBD_NUM 0x0380
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_FWCMDQ_TXBD_NUM 0x0380
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_RX_RXBD_NUM 0x0382
+#define REG_VOQ_TXBD_NUM 0x0384
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ACH0_ACH1_TXBD_NUM 0x0384
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_VIQ_TXBD_NUM 0x0386
+#define REG_BEQ_TXBD_NUM 0x0388
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ACH2_ACH3_TXBD_NUM 0x0388
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BKQ_TXBD_NUM 0x038A
+#define REG_HI0Q_TXBD_NUM 0x038C
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0HI0Q_HI1Q_TXBD_NUM 0x038C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HI1Q_TXBD_NUM 0x038E
+#define REG_HI2Q_TXBD_NUM 0x0390
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0HI2Q_HI3Q_TXBD_NUM 0x0390
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HI3Q_TXBD_NUM 0x0392
+#define REG_HI4Q_TXBD_NUM 0x0394
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0HI4Q_HI5Q_TXBD_NUM 0x0394
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HI5Q_TXBD_NUM 0x0396
+#define REG_HI6Q_TXBD_NUM 0x0398
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0HI6Q_HI7Q_TXBD_NUM 0x0398
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HI7Q_TXBD_NUM 0x039A
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_TSFTIMER_HCI 0x039C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BD_RWPTR_CLR 0x039C
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_BD_RWPTR_CLR1 0x039C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_VOQ_TXBD_IDX 0x03A0
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ACH0_TXBD_IDX 0x03A0
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_VIQ_TXBD_IDX 0x03A4
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ACH1_TXBD_IDX 0x03A4
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BEQ_TXBD_IDX 0x03A8
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ACH2_TXBD_IDX 0x03A8
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BKQ_TXBD_IDX 0x03AC
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ACH3_TXBD_IDX 0x03AC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_MGQ_TXBD_IDX 0x03B0
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0MGQ_TXBD_IDX 0x03B0
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_RXQ_RXBD_IDX 0x03B4
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0RXQ_RXBD_IDX 0x03B4
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HI0Q_TXBD_IDX 0x03B8
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0HI0Q_TXBD_IDX 0x03B8
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HI1Q_TXBD_IDX 0x03BC
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0HI1Q_TXBD_IDX 0x03BC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HI2Q_TXBD_IDX 0x03C0
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0HI2Q_TXBD_IDX 0x03C0
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HI3Q_TXBD_IDX 0x03C4
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0HI3Q_TXBD_IDX 0x03C4
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HI4Q_TXBD_IDX 0x03C8
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0HI4Q_TXBD_IDX 0x03C8
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HI5Q_TXBD_IDX 0x03CC
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0HI5Q_TXBD_IDX 0x03CC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HI6Q_TXBD_IDX 0x03D0
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0HI6Q_TXBD_IDX 0x03D0
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HI7Q_TXBD_IDX 0x03D4
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0HI7Q_TXBD_IDX 0x03D4
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_DBG_SEL_V1 0x03D8
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_DBGSEL_PCIE_HRPWM1_HCPWM1_V1 0x03D8
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_PCIE_HRPWM1_V1 0x03D9
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_HCI_HRPWM1_V1 0x03D9
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_PCIE_HCPWM1_V1 0x03DA
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_HCI_HCPWM1_V1 0x03DA
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_PCIE_CTRL2 0x03DB
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_HCI_CTRL2 0x03DB
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+#define REG_LX_CTRL2 0x03DB
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_PCIE_HRPWM2_V1 0x03DC
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_HCI_HRPWM2_V1 0x03DC
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_PCIE_HRPWM2_HCPWM2_V1 0x03DC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_PCIE_HCPWM2_V1 0x03DE
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_HCI_HCPWM2_V1 0x03DE
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_PCIE_H2C_MSG_V1 0x03E0
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_HCI_H2C_MSG_V1 0x03E0
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_PCIE_C2H_MSG_V1 0x03E4
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_HCI_C2H_MSG_V1 0x03E4
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_DBI_WDATA_V1 0x03E8
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+#define REG_LX_DMA_ISR 0x03E8
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_DBI_RDATA_V1 0x03EC
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+#define REG_LX_DMA_IMR 0x03EC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define REG_DBI_FLAG_V1 0x03F0
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_STUCK_FLAG_V1 0x03F0
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+#define REG_LX_DMA_DBG 0x03F0
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_MDIO_V1 0x03F4
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT)
+
+#define REG_MDIO2_V1 0x03F8
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_WDT_CFG 0x03F8
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_PCIE_MIX_CFG 0x03F8
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+#define REG_BUS_MIX_CFG 0x03F8
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_HCI_MIX_CFG 0x03FC
+
+#endif
+
+#if (HALMAC_8881A_SUPPORT)
+
+#define REG_BUS_MIX_CFG1 0x03FC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_Q0_INFO 0x0400
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_QUEUE_INFO1 0x0400
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_QUEUELIST_INFO0 0x0400
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_Q1_INFO 0x0404
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_QUEUE_INFO2 0x0404
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_QUEUELIST_INFO1 0x0404
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_Q2_INFO 0x0408
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_QUEUE_INFO3 0x0408
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_QUEUELIST_INFO2 0x0408
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_Q3_INFO 0x040C
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_QINFO_INDEX 0x040C
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_QUEUELIST_INFO3 0x040C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_MGQ_INFO 0x0410
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_QUEUE_EMPTY 0x0410
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_QUEUELIST_INFO_EMPTY 0x0410
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HIQ_INFO 0x0414
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_ACQ_STOP_V1 0x0414
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_QUEUELIST_ACQ_EN 0x0414
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BCNQ_INFO 0x0418
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_BCNQ_BDNY_V2 0x0418
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_TXPKT_EMPTY 0x041A
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_CPU_MGQ_INFO 0x041C
+#define REG_FWHW_TXQ_CTRL 0x0420
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HWSEQ_CTRL 0x0423
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_DATAFB_SEL 0x0423
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BCNQ_BDNY 0x0424
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define REG_BCNQ_BDNY_V1 0x0424
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_TXBDNY 0x0424
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_MGQ_BDNY 0x0425
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_LIFETIME_EN 0x0426
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_FW_FREE_TAIL 0x0427
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_SPEC_SIFS 0x0428
+#define REG_RETRY_LIMIT 0x042A
+#define REG_TXBF_CTRL 0x042C
+#define REG_DARFRC 0x0430
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_DARFRCH 0x0434
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_RARFRC 0x0438
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_RARFRCH 0x043C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_RRSR 0x0440
+#define REG_ARFR0 0x0444
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_ARFRH0 0x0448
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_ARFR1_V1 0x044C
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_REG_ARFR_WT0 0x044C
+#define REG_REG_ARFR_WT1 0x0450
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_ARFRH1_V1 0x0450
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_CCK_CHECK 0x0454
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_AMPDU_BURST_CTRL 0x0455
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_AMPDU_MAX_TIME_V1 0x0455
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_AMPDU_MAX_TIME 0x0456
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define REG_BCNQ1_BDNY_V1 0x0456
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_TAB_SEL 0x0456
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BCNQ1_BDNY 0x0457
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_BCN_INVALID_CTRL 0x0457
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_AMPDU_MAX_LENGTH 0x0458
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_AMPDU_MAX_LENGTH_HT 0x0458
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_ACQ_STOP 0x045C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_WMAC_LBK_BUF_HD 0x045D
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_NDPA_RATE 0x045D
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_TX_HANG_CTRL 0x045E
+#define REG_NDPA_OPT_CTRL 0x045F
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_FAST_EDCA_CTRL 0x0460
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_AMPDU_MAX_LENGTH_VHT 0x0460
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_RD_RESP_PKT_TH 0x0463
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_CMDQ_INFO 0x0464
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_NEW_EDCA_CTRL_V1 0x0464
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_Q4_INFO 0x0468
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ACQ_STOP_V2 0x0468
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_Q5_INFO 0x046C
+#define REG_Q6_INFO 0x0470
+#define REG_Q7_INFO 0x0474
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_WMAC_LBK_BUF_HD_V1 0x0478
+#define REG_MGQ_BDNY_V1 0x047A
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_TXRPT_CTRL 0x047C
+#define REG_INIRTS_RATE_SEL 0x0480
+#define REG_BASIC_CFEND_RATE 0x0481
+#define REG_STBC_CFEND_RATE 0x0482
+#define REG_DATA_SC 0x0483
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_MACID_SLEEP3 0x0484
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_MOREDATA_V1 0x0484
+#define REG_DATA_SC1 0x0487
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_MACID_SLEEP1 0x0488
+#define REG_ARFR2_V1 0x048C
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_ARFRH2_V1 0x0490
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_ARFR3_V1 0x0494
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_ARFRH3_V1 0x0498
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_ARFR4 0x049C
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_ARFRH4 0x04A0
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_ARFR5 0x04A4
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_ARFRH5 0x04A8
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_TXRPT_START_OFFSET 0x04AC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_TRYING_CNT_TH 0x04B0
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_POWER_STAGE1 0x04B4
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_POWER_STAGE2 0x04B8
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_SW_AMPDU_BURST_MODE_CTRL 0x04BC
+#define REG_PKT_LIFE_TIME 0x04C0
+#define REG_STBC_SETTING 0x04C4
+#define REG_STBC_SETTING2 0x04C5
+#define REG_QUEUE_CTRL 0x04C6
+#define REG_SINGLE_AMPDU_CTRL 0x04C7
+#define REG_PROT_MODE_CTRL 0x04C8
+#define REG_BAR_MODE_CTRL 0x04CC
+#define REG_RA_TRY_RATE_AGG_LMT 0x04CF
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_MACID_SLEEP2 0x04D0
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_MACID_SLEEP_CTRL 0x04D0
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_MACID_SLEEP 0x04D4
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_MACID_SLEEP_INFO 0x04D4
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HW_SEQ0 0x04D8
+#define REG_HW_SEQ1 0x04DA
+#define REG_HW_SEQ2 0x04DC
+#define REG_HW_SEQ3 0x04DE
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+#define REG_CSI_SEQ 0x04DE
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_NULL_PKT_STATUS 0x04E0
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define REG_NULL_PKT_STATUS_V1 0x04E0
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_PTCL_ERR_STATUS 0x04E2
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_PTCL_ERR_STATUS_V1 0x04E2
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_PTCL_PKT_NUM 0x04E3
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_NULL_PKT_STATUS_EXTEND 0x04E3
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+#define REG_TRXRPT_MISS_CNT 0x04E3
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+#define REG_VIDEO_ENHANCEMENT_FUN 0x04E4
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_NULL_PKT_STATUS_V2 0x04E4
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+#define REG_HQMGQ_DROP 0x04E4
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define REG_PRECNT_CTRL 0x04E5
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_NULL_PKT_STATUS_EXTEND_V1 0x04E7
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BT_POLLUTE_PKT_CNT 0x04E8
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define REG_PTCL_DBG 0x04EC
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_DROP_NUM 0x04EC
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_PTCL_DBG_V1 0x04EC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_PTCL_TX_RPT 0x04F0
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_TXOP_EXTRA_CTRL 0x04F0
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_BT_POLLUTE_PKTCNT 0x04F0
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_CPUMGQ_TIMER_CTRL2 0x04F4
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_PTCL_DBG_OUT 0x04F8
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_DUMMY_PAGE4 0x04FC
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_DUMMY_PAGE4_V1 0x04FC
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_MOREDATA 0x04FE
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_DUMMY_PAGE4_1 0x04FE
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_EDCA_VO_PARAM 0x0500
+#define REG_EDCA_VI_PARAM 0x0504
+#define REG_EDCA_BE_PARAM 0x0508
+#define REG_EDCA_BK_PARAM 0x050C
+#define REG_BCNTCFG 0x0510
+#define REG_PIFS 0x0512
+#define REG_RDG_PIFS 0x0513
+#define REG_SIFS 0x0514
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_TSFTR_SYN_OFFSET 0x0518
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_FORCE_BCN_IFS_V1 0x0518
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_AGGR_BREAK_TIME 0x051A
+#define REG_SLOT 0x051B
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_EDCA_CPUMGQ_PARAM 0x051C
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_NOA_ON_ERLY_TIME 0x051C
+#define REG_NOA_OFF_ERLY_TIME 0x051D
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_CPUMGQ_PAUSE 0x051E
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_TX_PTCL_CTRL 0x0520
+#define REG_TXPAUSE 0x0522
+#define REG_DIS_TXREQ_CLR 0x0523
+#define REG_RD_CTRL 0x0524
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_MBSSID_CTRL 0x0526
+#define REG_P2PPS_CTRL 0x0527
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_PKT_LIFETIME_CTRL 0x0528
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_P2PPS_SPEC_STATE 0x052B
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_P2PPS0_SPEC_STATE 0x052B
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_TXOP_LIMIT_CTRL 0x052C
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BAR_TX_CTRL 0x0530
+#define REG_P2PON_DIS_TXTIME 0x0531
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_CCA_TXEN_CNT 0x0534
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
+
+#define REG_QUEUE_INCOL_THR 0x0538
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_MAX_INTER_COLLISION 0x0538
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
+
+#define REG_QUEUE_INCOL_EN 0x053C
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_MAX_INTER_COLLISION_CNT 0x053C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_TBTT_PROHIBIT 0x0540
+#define REG_P2PPS_STATE 0x0543
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_RD_NAV_NXT 0x0544
+#define REG_NAV_PROT_LEN 0x0546
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_FTM_CTRL 0x0548
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_FTM_PTT 0x0548
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_FTM_TSF_CNT 0x054C
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_FTM_TSF 0x054C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BCN_CTRL 0x0550
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BCN_CTRL1 0x0551
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define REG_BCN_CTRL_CLINT0 0x0551
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_MBID_NUM 0x0552
+#define REG_DUAL_TSF_RST 0x0553
+#define REG_MBSSID_BCN_SPACE 0x0554
+#define REG_DRVERLYINT 0x0558
+#define REG_BCNDMATIM 0x0559
+#define REG_ATIMWND 0x055A
+#define REG_USTIME_TSF 0x055C
+#define REG_BCN_MAX_ERR 0x055D
+#define REG_RXTSF_OFFSET_CCK 0x055E
+#define REG_RXTSF_OFFSET_OFDM 0x055F
+#define REG_TSFTR 0x0560
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_TSFTR_1 0x0564
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_TSFTR1 0x0568
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define REG_FREERUN_CNT 0x0568
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_FREERUN_CNT_1 0x056C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_ATIMWND1 0x0570
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_ATIMWND1_V1 0x0570
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define REG_TBTT_PROHIBIT_INFRA 0x0571
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_CTWND 0x0572
+#define REG_BCNIVLCUNT 0x0573
+#define REG_BCNDROPCTRL 0x0574
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_HGQ_TIMEOUT_PERIOD 0x0575
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_TXCMD_TIMEOUT_PERIOD 0x0576
+#define REG_MISC_CTRL 0x0577
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define REG_BCN_CTRL_CLINT1 0x0578
+#define REG_BCN_CTRL_CLINT2 0x0579
+#define REG_BCN_CTRL_CLINT3 0x057A
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_EXTEND_CTRL 0x057B
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define REG_P2PPS1_SPEC_STATE 0x057C
+#define REG_P2PPS1_STATE 0x057D
+#define REG_P2PPS2_SPEC_STATE 0x057E
+#define REG_P2PPS2_STATE 0x057F
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_PS_TIMER 0x0580
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define REG_PS_TIMER0 0x0580
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_TIMER0 0x0584
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define REG_PS_TIMER1 0x0584
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_TIMER1 0x0588
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define REG_PS_TIMER2 0x0588
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_TBTT_CTN_AREA 0x058C
+#define REG_FORCE_BCN_IFS 0x058E
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_TXOP_MIN 0x0590
+#define REG_PRE_BKF_TIME 0x0592
+#define REG_CROSS_TXOP_CTRL 0x0593
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_TBTT_INT_SHIFT_CLI0 0x0594
+#define REG_TBTT_INT_SHIFT_CLI1 0x0595
+#define REG_TBTT_INT_SHIFT_CLI2 0x0596
+#define REG_TBTT_INT_SHIFT_CLI3 0x0597
+#define REG_TBTT_INT_SHIFT_ENABLE 0x0598
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+#define REG_RX_TBTT_SHIFT_V1 0x0598
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_ATIMWND2 0x05A0
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_ATIMWND_GROUP1 0x05A0
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_ATIMWND3 0x05A1
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_ATIMWND_GROUP2 0x05A1
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_ATIMWND4 0x05A2
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_ATIMWND_GROUP3 0x05A2
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_ATIMWND5 0x05A3
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_ATIMWND_GROUP4 0x05A3
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_ATIMWND6 0x05A4
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_DTIM_COUNT_GROUP1 0x05A4
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_ATIMWND7 0x05A5
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_DTIM_COUNT_GROUP2 0x05A5
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_ATIMUGT 0x05A6
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_DTIM_COUNT_GROUP3 0x05A6
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_HIQ_NO_LMT_EN 0x05A7
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_DTIM_COUNT_GROUP4 0x05A7
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_DTIM_COUNTER_ROOT 0x05A8
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_HIQ_NO_LMT_EN_V2 0x05A8
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_DTIM_COUNTER_VAP1 0x05A9
+#define REG_DTIM_COUNTER_VAP2 0x05AA
+#define REG_DTIM_COUNTER_VAP3 0x05AB
+#define REG_DTIM_COUNTER_VAP4 0x05AC
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_MBID_BCNQ_EN 0x05AC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_DTIM_COUNTER_VAP5 0x05AD
+#define REG_DTIM_COUNTER_VAP6 0x05AE
+#define REG_DTIM_COUNTER_VAP7 0x05AF
+#define REG_DIS_ATIM 0x05B0
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define REG_EARLY_128US 0x05B1
+#define REG_P2PPS1_CTRL 0x05B2
+#define REG_P2PPS2_CTRL 0x05B3
+#define REG_TIMER0_SRC_SEL 0x05B4
+#define REG_NOA_UNIT_SEL 0x05B5
+#define REG_P2POFF_DIS_TXTIME 0x05B7
+#define REG_MBSSID_BCN_SPACE2 0x05B8
+#define REG_MBSSID_BCN_SPACE3 0x05BC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_ACMHWCTRL 0x05C0
+#define REG_ACMRSTCTRL 0x05C1
+#define REG_ACMAVG 0x05C2
+#define REG_VO_ADMTIME 0x05C4
+#define REG_VI_ADMTIME 0x05C6
+#define REG_BE_ADMTIME 0x05C8
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_MAC_HEADER_NAV_OFFSET 0x05CA
+#define REG_DIS_NDPA_NAV_CHECK 0x05CB
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_EDCA_RANDOM_GEN 0x05CC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_TXCMD_NOA_SEL 0x05CF
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_TXCMD_SEL 0x05CF
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+#define REG_32K_CLK_SEL 0x05D0
+#define REG_EARLYINT_ADJUST 0x05D4
+#define REG_BCNERR_CNT 0x05D8
+#define REG_BCNERR_CNT_2 0x05DC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_NOA_PARAM 0x05E0
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_NOA_PARAM_1 0x05E4
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_MU_DBG_INFO 0x05E8
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_NOA_PARAM_2 0x05E8
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_MU_DBG_INFO_1 0x05EC
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_NOA_PARAM_3 0x05EC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_NOA_SUBIE 0x05ED
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define REG_P2P_RST 0x05F0
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_SCH_DBG_SEL 0x05F0
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_SCHEDULER_RST 0x05F1
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_MU_DBG_ERR_FLAG 0x05F2
+#define REG_TX_ERR_RECOVERY_RST 0x05F3
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_SCH_DBG_VALUE 0x05F4
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_SCH_TXCMD 0x05F8
+#define REG_PAGE5_DUMMY 0x05FC
+#define REG_WMAC_CR 0x0600
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_WMAC_FWPKT_CR 0x0601
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_FW_STS_FILTER 0x0602
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
+
+#define REG_BWOPMODE 0x0603
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_TCR 0x0604
+#define REG_RCR 0x0608
+#define REG_RX_PKT_LIMIT 0x060C
+#define REG_RX_DLK_TIME 0x060D
+#define REG_RX_DRVINFO_SZ 0x060F
+#define REG_MACID 0x0610
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_MACID_H 0x0614
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_BSSID 0x0618
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BSSID_H 0x061C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_MAR 0x0620
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_MAR_H 0x0624
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_MBIDCAMCFG_1 0x0628
+#define REG_MBIDCAMCFG_2 0x062C
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_WMAC_DEBUG_SEL 0x062C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_MCU_TEST_1 0x0630
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_WMAC_TCR_TSFT_OFS 0x0630
+#define REG_UDF_THSD 0x0632
+#define REG_ZLD_NUM 0x0633
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_MCU_TEST_2 0x0634
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_STMP_THSD 0x0634
+#define REG_WMAC_TXTIMEOUT 0x0635
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
+
+#define REG_MCU_TEST_2_V1 0x0636
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_USTIME_EDCA 0x0638
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define REG_ACKTO_CCK 0x0639
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_MAC_SPEC_SIFS 0x063A
+#define REG_RESP_SIFS_CCK 0x063C
+#define REG_RESP_SIFS_OFDM 0x063E
+#define REG_ACKTO 0x0640
+#define REG_CTS2TO 0x0641
+#define REG_EIFS 0x0642
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define REG_RPFM_MAP0 0x0644
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_RPFM_MAP1 0x0646
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_RPFM_MAP1_V1 0x0646
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define REG_RPFM_CAM_CMD 0x0648
+#define REG_RPFM_CAM_RWD 0x064C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_NAV_CTRL 0x0650
+#define REG_BACAMCMD 0x0654
+#define REG_BACAMCONTENT 0x0658
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BACAMCONTENT_H 0x065C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_LBDLY 0x0660
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_WMAC_BACAM_RPMEN 0x0661
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define REG_TX_RX 0x0662
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_WMAC_BITMAP_CTL 0x0663
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_RXERR_RPT 0x0664
+#define REG_WMAC_TRXPTCL_CTL 0x0668
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_WMAC_TRXPTCL_CTL_H 0x066C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_CAMCMD 0x0670
+#define REG_CAMWRITE 0x0674
+#define REG_CAMREAD 0x0678
+#define REG_CAMDBG 0x067C
+#define REG_SECCFG 0x0680
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_RXFILTER_CATEGORY_1 0x0682
+#define REG_RXFILTER_ACTION_1 0x0683
+#define REG_RXFILTER_CATEGORY_2 0x0684
+#define REG_RXFILTER_ACTION_2 0x0685
+#define REG_RXFILTER_CATEGORY_3 0x0686
+#define REG_RXFILTER_ACTION_3 0x0687
+#define REG_RXFLTMAP3 0x0688
+#define REG_RXFLTMAP4 0x068A
+#define REG_RXFLTMAP5 0x068C
+#define REG_RXFLTMAP6 0x068E
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_WOW_CTRL 0x0690
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define REG_NAN_RX_TSF_FILTER 0x0691
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_PS_RX_INFO 0x0692
+#define REG_WMMPS_UAPSD_TID 0x0693
+#define REG_LPNAV_CTRL 0x0694
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_WKFMCAM_NUM 0x0698
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_WKFMCAM_CMD 0x0698
+#define REG_WKFMCAM_RWD 0x069C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_RXFLTMAP0 0x06A0
+#define REG_RXFLTMAP1 0x06A2
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_RXFLTMAP 0x06A4
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define REG_RXFLTMAP2 0x06A4
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_BCN_PSR_RPT 0x06A8
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_FLC_RPC 0x06AC
+#define REG_FLC_RPCT 0x06AD
+#define REG_FLC_PTS 0x06AE
+#define REG_FLC_TRPC 0x06AF
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_RXPKTMON_CTRL 0x06B0
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_STATE_MON 0x06B4
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_ERROR_MON 0x06B8
+#define REG_SEARCH_MACID 0x06BC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_BT_COEX_TABLE 0x06C0
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BT_COEX_TABLE2 0x06C4
+#define REG_BT_COEX_BREAK_TABLE 0x06C8
+#define REG_BT_COEX_TABLE_H 0x06CC
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_RXCMD_0 0x06D0
+#define REG_RXCMD_1 0x06D4
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_WMAC_RESP_TXINFO 0x06D8
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BBPSF_CTRL 0x06DC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_P2P_RX_BCN_NOA 0x06E0
+#define REG_ASSOCIATED_BFMER0_INFO 0x06E4
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_ASSOCIATED_BFMER0_INFO_H 0x06E8
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_ASSOCIATED_BFMER1_INFO 0x06EC
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_ASSOCIATED_BFMER1_INFO_H 0x06F0
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_TX_CSI_RPT_PARAM_BW20 0x06F4
+#define REG_TX_CSI_RPT_PARAM_BW40 0x06F8
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_TX_CSI_RPT_PARAM_BW80 0x06FC
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_CSI_RRSR_V1 0x06FC
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+#define REG_CSI_PTR 0x06FC
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_MACID1 0x0700
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_MACID1_1 0x0704
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BSSID1 0x0708
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_PCIE_CFG_FORCE_LINK_L 0x0709
+#define REG_PCIE_CFG_FORCE_LINK_H 0x070A
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BSSID1_1 0x070C
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_PCIE_CFG_DEFAULT_ACK_FREQUENCY 0x070C
+#define REG_PCIE_CFG_CX_NFTS 0x070D
+#define REG_PCIE_CFG_DEFAULT_ENTR_LATENCY 0x070F
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_BCN_PSR_RPT1 0x0710
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_PCIE_CFG_L1_MISC_SEL 0x0711
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_ASSOCIATED_BFMEE_SEL 0x0714
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_ASSOCIATED_BFMEE_SEL_1 0x0714
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_SND_PTCL_CTRL 0x0718
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_PCIE_CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF 0x0718
+#define REG_PCIE_CFG_FORCE_CLKREQ_N_PAD 0x0719
+#define REG_PCIE_CFG_TIMER_MODIFIER_FOR_ACK_NAK_LATENCY 0x071A
+#define REG_PCIE_CFG_TIMER_MODIFIER_FOR_FLOW_CONTROL_WATCHDOG 0x071B
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_RX_CSI_RPT_INFO 0x071C
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_PCIE_CFG_SKP_INTERVAL_VALUE_L 0x071C
+#define REG_PCIE_CFG_SKP_INTERVAL_VALUE_H 0x071D
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_NS_ARP_CTRL 0x0720
+#define REG_NS_ARP_INFO 0x0724
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_PCIE_CFG_L1_UNIT_SEL 0x0724
+#define REG_PCIE_CFG_MIN_CLKREQ_SEL 0x0725
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_NS_ARP_IPADDR 0x0728
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BEAMFORMING_INFO_NSARP_V1 0x0728
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_WRITE_RX_CSI_RPT_INFO 0x072C
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BEAMFORMING_INFO_NSARP 0x072C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_NS_ARP_IPV6_MYADDR 0x0730
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_IPV6 0x0730
+#define REG_IPV6_1 0x0734
+#define REG_IPV6_2 0x0738
+#define REG_IPV6_3 0x073C
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_WMAC_RTX_CTX_SUBTYPE_CFG 0x0750
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+#define REG_WMAC_SWAES_DIO_B63_B32 0x0754
+#define REG_WMAC_SWAES_DIO_B95_B64 0x0758
+#define REG_WMAC_SWAES_DIO_B127_B96 0x075C
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_WMAC_SWAES_CFG 0x0760
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BT_COEX_V2 0x0762
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_BT_COEX 0x0764
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_WLAN_ACT_MSK_CTRL 0x0768
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_WLAN_ACT_MASK_CTRL 0x0768
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_WLAN_ACT_MASK_CTRL_1 0x076C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BT_STATISTICS_CTRL 0x076E
+#define REG_BT_COEX_ENH_INTF_CTRL 0x076E
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BT_COEX_ENHANCED_INTR_CTRL 0x076E
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || \
+ HALMAC_8881A_SUPPORT)
+
+#define REG_BT_ACT_STATISTICS 0x0770
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BT_ACT_STATISTICS_1 0x0774
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BT_STATISTICS_OTH_CTRL 0x0778
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BT_STATISTICS_CONTROL_REGISTER 0x0778
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BT_CMD_ID 0x077C
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BT_STATUS_REPORT_REGISTER 0x077C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BT__STATUS_RPT 0x077D
+#define REG_BT_DATA 0x0780
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BT_INTERRUPT_CONTROL_REGISTER 0x0780
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_WLAN_RPT_ 0x0781
+#define REG_BT_ISR_CTRL 0x0783
+#define REG_WLAN_RPT_TO_CTR 0x0784
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER 0x0784
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BT_ISOLATION_TABLE 0x0785
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER 0x0785
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1 0x0788
+#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2 0x078C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BT_ISR_STA 0x078F
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BT_INTERRUPT_STATUS_REGISTER 0x078F
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_TDMA_TIME_AND_RPT_SAM_SET 0x0790
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BT_TDMA_TIME_REGISTER 0x0790
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BT_CH_INFO 0x0794
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_BT_ACT_REGISTER 0x0794
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_BT_STATIC_INFO_EXT 0x0795
+#define REG_LTR_IDLE_LATENCY 0x0798
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_OBFF_CTRL_BASIC 0x0798
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_LTR_ACTIVE_LATENCY 0x079C
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_OBFF_CTRL2_TIMER 0x079C
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_OBFF_CTRL 0x07A0
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_LTR_CTRL_BASIC 0x07A0
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_LTR_CTRL 0x07A4
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_LTR_CTRL2_TIMER_THRESHOLD 0x07A4
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_LTR_CTRL2 0x07A8
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_LTR_IDLE_LATENCY_V1 0x07A8
+#define REG_LTR_ACTIVE_LATENCY_V1 0x07AC
+
+#endif
#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-#define REG_HWSEQ_CTRL 0x0423
+#define REG_ANTTRN_CTRL 0x07B0
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define REG_ANTENNA_TRAINING_CONTROL_REGISTER 0x07B0
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_SMART_ANT_CONDITION 0x07B0
+#define REG_SMART_ANT_CTRL 0x07B4
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_1 0x07B4
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_WMAC_PKTCNT_RWD 0x07B8
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_CONTROL_FRAME_REPORT 0x07B8
+
+#endif
+
+#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT || HALMAC_8881A_SUPPORT)
+
+#define REG_WMAC_PKTCNT_CTRL 0x07BC
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_CONTROL_FRAME_CNT_CTRL 0x07BC
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_IQ_DUMP 0x07C0
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_IQ_DUMP_1 0x07C4
+#define REG_IQ_DUMP_2 0x07C8
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_WMAC_FTM_CTL 0x07CC
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define REG_WMAC_IQ_MDPK_FUNC 0x07CE
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_IQ_DUMP_EXT 0x07CF
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT)
+
+#define REG_OFDM_CCK_LEN_MASK 0x07D0
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define REG_WMAC_OPTION_FUNCTION 0x07D0
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_WMAC_OPTION_FUNCTION_1 0x07D4
+#define REG_WMAC_OPTION_FUNCTION_2 0x07D8
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_RX_FILTER_FUNCTION 0x07DA
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_NDP_SIG 0x07E0
+#define REG_TXCMD_INFO_FOR_RSP_PKT 0x07E4
+
+#endif
+
+#if (HALMAC_8814AMP_SUPPORT)
+
+#define REG_SEC_OPT 0x07E8
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_TXCMD_INFO_FOR_RSP_PKT_1 0x07E8
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_SEC_OPT_V2 0x07EC
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_WSEC_OPTION 0x07EC
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_RTS_ADDRESS_0 0x07F0
+
+#endif
+
+#if (HALMAC_8814AMP_SUPPORT)
+
+#define REG_RTS_ADDR0 0x07F0
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_RTS_ADDRESS_0_1 0x07F4
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_RTS_ADDRESS_1 0x07F8
+
+#endif
+
+#if (HALMAC_8814AMP_SUPPORT)
+
+#define REG_RTS_ADDR1 0x07F8
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_RTS_ADDRESS_1_1 0x07FC
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT)
+
+#define REG__RPFM_MAP1 0x07FE
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define REG_SYS_CFG3 0x1000
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_ANAPARSW_MAC_0 0x1010
+#define REG_ANAPARSW_MAC_1 0x1014
+#define REG_ANAPAR_MAC_0 0x1018
+#define REG_ANAPAR_MAC_1 0x101C
+#define REG_ANAPAR_MAC_2 0x1020
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ANAPAR_MAC_3 0x1024
+#define REG_ANAPAR_MAC_4 0x1028
+#define REG_ANAPAR_MAC_5 0x102C
+#define REG_ANAPAR_MAC_6 0x1030
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
+
+#define REG_SYS_CFG4 0x1034
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ANAPAR_MAC_7 0x1034
+#define REG_ANAPAR_MAC_8 0x1038
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_ANAPAR_XTAL_0 0x1040
+#define REG_ANAPAR_XTAL_1 0x1044
+#define REG_ANAPAR_XTAL_2 0x1048
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ANAPAR_XTAL_AAC 0x104C
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+#define REG_ANAPAR_XTAL_3 0x104C
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_ANAPAR_XTAL_R_ONLY 0x1050
+#define REG_CPHY_LDO 0x1054
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+#define REG_ANAPAR_XTAL_AACK_0 0x1054
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_CPHY_BG 0x1058
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+#define REG_ANAPAR_XTAL_AACK_1 0x1058
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_HIMR_4 0x1060
+#define REG_HISR_4 0x1064
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+#define REG_ANAPAR_XTAL_MODE_DECODER 0x1064
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_HIMR_5 0x1068
+#define REG_HISR_5 0x106C
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define REG_SYS_CFG5 0x1070
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_HIMR_6 0x1078
+#define REG_HISR_6 0x107C
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_CPU_DMEM_CON 0x1080
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define REG_BOOT_REASON 0x1088
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_HIMR4 0x1090
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_DATA_CPU_CTL0 0x1090
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_HISR4 0x1094
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_DATA_CPU_CTL1 0x1094
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_HIMR5 0x1098
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_TXDMA_STOP_HIMR 0x1098
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_HISR5 0x109C
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_TXDMA_STOP_HISR 0x109C
+#define REG_TXDMA_START_HIMR 0x10A0
+#define REG_TXDMA_START_HISR 0x10A4
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
+
+#define REG_NFCPAD_CTRL 0x10A8
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_HIMR2 0x10B0
+#define REG_HISR2 0x10B4
+#define REG_HIMR3 0x10B8
+#define REG_HISR3 0x10BC
+#define REG_SW_MDIO 0x10C0
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
+
+#define REG_SW_FLUSH 0x10C4
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_DBG_GPIO_BMUX 0x10C8
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_HIMR_7 0x10C8
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_FPGA_TAG 0x10CC
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_HISR_7 0x10CC
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_WL_DSS_CTRL0 0x10D0
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define REG_H2C_PKT_READADDR 0x10D0
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define REG_WL_DSS_STATUS0 0x10D4
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define REG_H2C_PKT_WRITEADDR 0x10D4
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_WL_DSS_CTRL1 0x10D8
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define REG_MEM_PWR_CRTL 0x10D8
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_WL_DSS_STATUS1 0x10DC
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_FW_DRV_HANDSHAKE 0x10DC
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT)
+
+#define REG_FW_DBG0 0x10E0
+#define REG_FW_DBG1 0x10E4
+#define REG_FW_DBG2 0x10E8
+#define REG_FW_DBG3 0x10EC
+#define REG_FW_DBG4 0x10F0
+#define REG_FW_DBG5 0x10F4
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_FW_DBG6 0x10F8
+#define REG_FW_DBG7 0x10FC
+#define REG_CR_EXT 0x1100
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_TC9_CTRL 0x1104
+#define REG_TC10_CTRL 0x1108
+#define REG_TC11_CTRL 0x110C
+#define REG_TC12_CTRL 0x1110
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_FWFF 0x1114
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define REG_RXFF_PTR_V1 0x1118
+#define REG_RXFF_WTR_V1 0x111C
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_FE2IMR 0x1120
+#define REG_FE2ISR 0x1124
+#define REG_FE3IMR 0x1128
+#define REG_FE3ISR 0x112C
+#define REG_FE4IMR 0x1130
+#define REG_FE4ISR 0x1134
+#define REG_FT1IMR 0x1138
+#define REG_FT1ISR 0x113C
+#define REG_SPWR0 0x1140
+#define REG_SPWR1 0x1144
+#define REG_SPWR2 0x1148
+#define REG_SPWR3 0x114C
+#define REG_POWSEQ 0x1150
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define REG_TC7_CTRL_V1 0x1158
+#define REG_TC8_CTRL_V1 0x115C
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_RXBCN_TBTT_INTERVAL_PORT0TO3 0x1160
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_RX_BCN_TBTT_ITVL0 0x1160
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define REG_RXBCN_TBTT_INTERVAL_PORT4 0x1164
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_RX_BCN_TBTT_ITVL1 0x1164
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+#define REG_FWIMR1 0x1168
+#define REG_FWISR1 0x116C
+#define REG_FWIMR2 0x1170
+
+#endif
+
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_IO_WRAP_ERR_FLAG 0x1170
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
+
+#define REG_FWISR2 0x1174
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_FWIMR3 0x1178
+#define REG_FWISR3 0x117C
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define REG_SPEED_SENSOR 0x1180
+#define REG_SPEED_SENSOR1 0x1184
+#define REG_SPEED_SENSOR2 0x1188
+#define REG_SPEED_SENSOR3 0x118C
+#define REG_SPEED_SENSOR4 0x1190
+#define REG_SPEED_SENSOR5 0x1194
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_RXPKTBUF_1_MAX_ADDR 0x1198
+#define REG_RXFWBUF_1_MAX_ADDR 0x119C
+#define REG_IO_WRAP_ERR_FLAG_V1 0x11A0
+#define REG_RXPKTBUF_1_READ 0x11A4
+#define REG_RXPKTBUF_1_WRITE 0x11A8
+#define REG_BUFF_DBGUG 0x11AC
+#define REG_RFE_CTRL_PAD_E2 0x11B0
+#define REG_RFE_CTRL_PAD_SR 0x11B4
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
+
+#define REG_EXT_QUEUE_REG 0x11C0
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_DATAFB_SEL 0x0423
+#define REG_H2C_PRIORITY_SEL 0x11C0
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_BCNQ_BDNY 0x0424
+#define REG_COUNTER_CONTROL 0x11C4
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_BCNQ_BDNY_V1 0x0424
+#define REG_COUNTER_CTRL 0x11C4
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_MGQ_BDNY 0x0425
+#define REG_COUNTER_TH 0x11C8
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_LIFETIME_EN 0x0426
+#define REG_COUNTER_THRESHOLD 0x11C8
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_FW_FREE_TAIL 0x0427
+#define REG_COUNTER_SET 0x11CC
+#define REG_COUNTER_OVERFLOW 0x11D0
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_SPEC_SIFS 0x0428
-#define REG_RETRY_LIMIT 0x042A
-#define REG_TXBF_CTRL 0x042C
-#define REG_DARFRC 0x0430
-#define REG_RARFRC 0x0438
-#define REG_RRSR 0x0440
-#define REG_ARFR0 0x0444
-#define REG_ARFR1_V1 0x044C
-#define REG_CCK_CHECK 0x0454
+#define REG_TDE_LEN_TH 0x11D4
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_AMPDU_BURST_CTRL 0x0455
+#define REG_TXDMA_LEN_THRESHOLD 0x11D4
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_AMPDU_MAX_TIME_V1 0x0455
+#define REG_RDE_LEN_TH 0x11D8
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_AMPDU_MAX_TIME 0x0456
+#define REG_RXDMA_LEN_THRESHOLD 0x11D8
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_BCNQ1_BDNY_V1 0x0456
+#define REG_PCIE_EXEC_TIME 0x11DC
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_BCNQ1_BDNY 0x0457
+#define REG_PCIE_EXEC_TIME_THRESHOLD 0x11DC
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_AMPDU_MAX_LENGTH 0x0458
-#define REG_ACQ_STOP 0x045C
+#define REG_FT2IMR 0x11E0
+#define REG_FT2ISR 0x11E4
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_WMAC_LBK_BUF_HD 0x045D
+#define REG_MSG2 0x11F0
+#define REG_MSG3 0x11F4
+#define REG_MSG4 0x11F8
+#define REG_MSG5 0x11FC
+#define REG_DDMA_CH0SA 0x1200
+#define REG_DDMA_CH0DA 0x1204
+#define REG_DDMA_CH0CTRL 0x1208
+#define REG_DDMA_CH1SA 0x1210
+#define REG_DDMA_CH1DA 0x1214
+#define REG_DDMA_CH1CTRL 0x1218
+#define REG_DDMA_CH2SA 0x1220
+#define REG_DDMA_CH2DA 0x1224
+#define REG_DDMA_CH2CTRL 0x1228
+#define REG_DDMA_CH3SA 0x1230
+#define REG_DDMA_CH3DA 0x1234
+#define REG_DDMA_CH3CTRL 0x1238
+#define REG_DDMA_CH4SA 0x1240
+#define REG_DDMA_CH4DA 0x1244
+#define REG_DDMA_CH4CTRL 0x1248
+#define REG_DDMA_CH5SA 0x1250
+#define REG_DDMA_CH5DA 0x1254
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8822B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_NDPA_RATE 0x045D
+#define REG_REG_DDMA_CH5CTRL 0x1258
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_TX_HANG_CTRL 0x045E
-#define REG_NDPA_OPT_CTRL 0x045F
+#define REG_DDMA_CH5CTRL 0x1258
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_FAST_EDCA_CTRL 0x0460
+#define REG_DDMA_INT_MSK 0x12E0
+#define REG_DDMA_CHSTATUS 0x12E8
+#define REG_DDMA_CHKSUM 0x12F0
+#define REG_DDMA_MONITOR 0x12FC
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_RD_RESP_PKT_TH 0x0463
-#define REG_CMDQ_INFO 0x0464
-#define REG_Q4_INFO 0x0468
-#define REG_Q5_INFO 0x046C
-#define REG_Q6_INFO 0x0470
-#define REG_Q7_INFO 0x0474
+#define REG_STC_INT_CS 0x1300
+#define REG_ST_INT_CFG 0x1304
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_WMAC_LBK_BUF_HD_V1 0x0478
-#define REG_MGQ_BDNY_V1 0x047A
+#define REG_ACH4_ACH5_TXBD_NUM 0x130C
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_TXRPT_CTRL 0x047C
-#define REG_INIRTS_RATE_SEL 0x0480
-#define REG_BASIC_CFEND_RATE 0x0481
-#define REG_STBC_CFEND_RATE 0x0482
-#define REG_DATA_SC 0x0483
-#define REG_MACID_SLEEP3 0x0484
-#define REG_MACID_SLEEP1 0x0488
-#define REG_ARFR2_V1 0x048C
-#define REG_ARFR3_V1 0x0494
-#define REG_ARFR4 0x049C
-#define REG_ARFR5 0x04A4
-#define REG_TXRPT_START_OFFSET 0x04AC
+#define REG_CMU_DLY_CTRL 0x1310
+#define REG_CMU_DLY_CFG 0x1314
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_TRYING_CNT_TH 0x04B0
+#define REG_FWCMDQ_TXBD_IDX 0x1318
+#define REG_P0HI8Q_TXBD_IDX 0x131C
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_POWER_STAGE1 0x04B4
+#define REG_H2CQ_TXBD_DESA 0x1320
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_POWER_STAGE2 0x04B8
+#define REG_H2CQ_TXBD_DESA_L 0x1320
+#define REG_H2CQ_TXBD_DESA_H 0x1324
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_SW_AMPDU_BURST_MODE_CTRL 0x04BC
-#define REG_PKT_LIFE_TIME 0x04C0
-#define REG_STBC_SETTING 0x04C4
-#define REG_STBC_SETTING2 0x04C5
-#define REG_QUEUE_CTRL 0x04C6
-#define REG_SINGLE_AMPDU_CTRL 0x04C7
-#define REG_PROT_MODE_CTRL 0x04C8
-#define REG_BAR_MODE_CTRL 0x04CC
-#define REG_RA_TRY_RATE_AGG_LMT 0x04CF
-#define REG_MACID_SLEEP2 0x04D0
-#define REG_MACID_SLEEP 0x04D4
+#define REG_H2CQ_TXBD_NUM 0x1328
+#define REG_H2CQ_TXBD_IDX 0x132C
+#define REG_H2CQ_CSR 0x1330
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_HW_SEQ0 0x04D8
-#define REG_HW_SEQ1 0x04DA
-#define REG_HW_SEQ2 0x04DC
-#define REG_HW_SEQ3 0x04DE
+#define REG_P0HI9Q_TXBD_IDX 0x1334
+#define REG_P0HI10Q_TXBD_IDX 0x1338
+#define REG_P0HI11Q_TXBD_IDX 0x133C
+#define REG_P0HI12Q_TXBD_IDX 0x1340
+#define REG_P0HI13Q_TXBD_IDX 0x1344
+#define REG_P0HI14Q_TXBD_IDX 0x1348
+#define REG_P0HI15Q_TXBD_IDX 0x134C
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
-#define REG_CSI_SEQ 0x04DE
+#define REG_AXI_EXCEPT_CS 0x1350
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_NULL_PKT_STATUS 0x04E0
+#define REG_CHANGE_PCIE_SPEED 0x1350
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_NULL_PKT_STATUS_V1 0x04E0
+#define REG_AXI_EXCEPT_TIME 0x1354
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_PTCL_ERR_STATUS 0x04E2
+#define REG_DEBUG_STATE1 0x1354
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_PTCL_PKT_NUM 0x04E3
+#define REG_HI8Q_TXBD_IDX 0x1358
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_NULL_PKT_STATUS_EXTEND 0x04E3
+#define REG_DEBUG_STATE2 0x1358
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
-#define REG_TRXRPT_MISS_CNT 0x04E3
+#define REG_HI9Q_TXBD_IDX 0x135C
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_VIDEO_ENHANCEMENT_FUN 0x04E4
+#define REG_DEBUG_STATE3 0x135C
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_BT_POLLUTE_PKT_CNT 0x04E8
-#define REG_PTCL_DBG 0x04EC
+#define REG_HI10Q_TXBD_IDX 0x1360
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_PTCL_TX_RPT 0x04F0
+#define REG_ACH5_TXBD_DESA_L 0x1360
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
-#define REG_TXOP_EXTRA_CTRL 0x04F0
+#define REG_HI11Q_TXBD_IDX 0x1364
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_CPUMGQ_TIMER_CTRL2 0x04F4
+#define REG_ACH5_TXBD_DESA_H 0x1364
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_DUMMY_PAGE4 0x04FC
+#define REG_HI12Q_TXBD_IDX 0x1368
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_DUMMY_PAGE4_V1 0x04FC
-#define REG_MOREDATA 0x04FE
+#define REG_ACH6_TXBD_DESA_L 0x1368
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_EDCA_VO_PARAM 0x0500
-#define REG_EDCA_VI_PARAM 0x0504
-#define REG_EDCA_BE_PARAM 0x0508
-#define REG_EDCA_BK_PARAM 0x050C
-#define REG_BCNTCFG 0x0510
-#define REG_PIFS 0x0512
-#define REG_RDG_PIFS 0x0513
-#define REG_SIFS 0x0514
-#define REG_TSFTR_SYN_OFFSET 0x0518
-#define REG_AGGR_BREAK_TIME 0x051A
-#define REG_SLOT 0x051B
-#define REG_TX_PTCL_CTRL 0x0520
-#define REG_TXPAUSE 0x0522
-#define REG_DIS_TXREQ_CLR 0x0523
-#define REG_RD_CTRL 0x0524
-#define REG_MBSSID_CTRL 0x0526
-#define REG_P2PPS_CTRL 0x0527
-#define REG_PKT_LIFETIME_CTRL 0x0528
-#define REG_P2PPS_SPEC_STATE 0x052B
+#define REG_HI13Q_TXBD_IDX 0x136C
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_BAR_TX_CTRL 0x0530
+#define REG_ACH6_TXBD_DESA_H 0x136C
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_QUEUE_INCOL_THR 0x0538
-#define REG_QUEUE_INCOL_EN 0x053C
+#define REG_HI14Q_TXBD_IDX 0x1370
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_TBTT_PROHIBIT 0x0540
-#define REG_P2PPS_STATE 0x0543
-#define REG_RD_NAV_NXT 0x0544
-#define REG_NAV_PROT_LEN 0x0546
+#define REG_ACH7_TXBD_DESA_L 0x1370
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
-#define REG_FTM_CTRL 0x0548
-#define REG_FTM_TSF_CNT 0x054C
+#define REG_HI15Q_TXBD_IDX 0x1374
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_BCN_CTRL 0x0550
+#define REG_ACH7_TXBD_DESA_H 0x1374
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_BCN_CTRL1 0x0551
+#define REG_HI8Q_TXBD_DESA 0x1378
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_BCN_CTRL_CLINT0 0x0551
+#define REG_ACH8_TXBD_DESA_L 0x1378
+#define REG_ACH8_TXBD_DESA_H 0x137C
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_MBID_NUM 0x0552
-#define REG_DUAL_TSF_RST 0x0553
-#define REG_MBSSID_BCN_SPACE 0x0554
-#define REG_DRVERLYINT 0x0558
-#define REG_BCNDMATIM 0x0559
-#define REG_ATIMWND 0x055A
-#define REG_USTIME_TSF 0x055C
-#define REG_BCN_MAX_ERR 0x055D
-#define REG_RXTSF_OFFSET_CCK 0x055E
-#define REG_RXTSF_OFFSET_OFDM 0x055F
-#define REG_TSFTR 0x0560
+#define REG_CHNL_DMA_CFG_V1 0x137C
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_TSFTR1 0x0568
+#define REG_HI9Q_TXBD_DESA 0x1380
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_FREERUN_CNT 0x0568
+#define REG_ACH9_TXBD_DESA_L 0x1380
+#define REG_ACH9_TXBD_DESA_H 0x1384
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_ATIMWND1 0x0570
+#define REG_HI10Q_TXBD_DESA 0x1388
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_ATIMWND1_V1 0x0570
+#define REG_ACH10_TXBD_DESA_L 0x1388
+#define REG_ACH10_TXBD_DESA_H 0x138C
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_TBTT_PROHIBIT_INFRA 0x0571
+#define REG_HI11Q_TXBD_DESA 0x1390
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_CTWND 0x0572
-#define REG_BCNIVLCUNT 0x0573
-#define REG_BCNDROPCTRL 0x0574
-#define REG_HGQ_TIMEOUT_PERIOD 0x0575
+#define REG_ACH11_TXBD_DESA_L 0x1390
+#define REG_ACH11_TXBD_DESA_H 0x1394
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_TXCMD_TIMEOUT_PERIOD 0x0576
-#define REG_MISC_CTRL 0x0577
-#define REG_BCN_CTRL_CLINT1 0x0578
-#define REG_BCN_CTRL_CLINT2 0x0579
-#define REG_BCN_CTRL_CLINT3 0x057A
+#define REG_HI12Q_TXBD_DESA 0x1398
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_EXTEND_CTRL 0x057B
+#define REG_ACH12_TXBD_DESA_L 0x1398
+#define REG_ACH12_TXBD_DESA_H 0x139C
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_P2PPS1_SPEC_STATE 0x057C
-#define REG_P2PPS1_STATE 0x057D
-#define REG_P2PPS2_SPEC_STATE 0x057E
-#define REG_P2PPS2_STATE 0x057F
+#define REG_HI13Q_TXBD_DESA 0x13A0
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_PS_TIMER 0x0580
+#define REG_ACH13_TXBD_DESA_L 0x13A0
+#define REG_ACH13_TXBD_DESA_H 0x13A4
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_PS_TIMER0 0x0580
+#define REG_HI14Q_TXBD_DESA 0x13A8
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_TIMER0 0x0584
+#define REG_HI0Q_TXBD_DESA_L 0x13A8
+#define REG_HI0Q_TXBD_DESA_H 0x13AC
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_PS_TIMER1 0x0584
+#define REG_HI15Q_TXBD_DESA 0x13B0
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_TIMER1 0x0588
+#define REG_HI1Q_TXBD_DESA_L 0x13B0
+#define REG_HI1Q_TXBD_DESA_H 0x13B4
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_PS_TIMER2 0x0588
+#define REG_PCIE_HISR0_V1 0x13B4
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_TBTT_CTN_AREA 0x058C
-#define REG_FORCE_BCN_IFS 0x058E
-#define REG_TXOP_MIN 0x0590
-#define REG_PRE_BKF_TIME 0x0592
-#define REG_CROSS_TXOP_CTRL 0x0593
+#define REG_HI8Q_TXBD_NUM 0x13B8
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
-#define REG_TBTT_INT_SHIFT_CLI0 0x0594
-#define REG_TBTT_INT_SHIFT_CLI1 0x0595
-#define REG_TBTT_INT_SHIFT_CLI2 0x0596
-#define REG_TBTT_INT_SHIFT_CLI3 0x0597
-#define REG_TBTT_INT_SHIFT_ENABLE 0x0598
+#define REG_HI2Q_TXBD_DESA_L 0x13B8
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_ATIMWND2 0x05A0
-#define REG_ATIMWND3 0x05A1
-#define REG_ATIMWND4 0x05A2
-#define REG_ATIMWND5 0x05A3
-#define REG_ATIMWND6 0x05A4
-#define REG_ATIMWND7 0x05A5
-#define REG_ATIMUGT 0x05A6
-#define REG_HIQ_NO_LMT_EN 0x05A7
-#define REG_DTIM_COUNTER_ROOT 0x05A8
-#define REG_DTIM_COUNTER_VAP1 0x05A9
-#define REG_DTIM_COUNTER_VAP2 0x05AA
-#define REG_DTIM_COUNTER_VAP3 0x05AB
-#define REG_DTIM_COUNTER_VAP4 0x05AC
-#define REG_DTIM_COUNTER_VAP5 0x05AD
-#define REG_DTIM_COUNTER_VAP6 0x05AE
-#define REG_DTIM_COUNTER_VAP7 0x05AF
-#define REG_DIS_ATIM 0x05B0
+#define REG_HI9Q_TXBD_NUM 0x13BA
+#define REG_HI10Q_TXBD_NUM 0x13BC
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_EARLY_128US 0x05B1
-#define REG_P2PPS1_CTRL 0x05B2
-#define REG_P2PPS2_CTRL 0x05B3
-#define REG_TIMER0_SRC_SEL 0x05B4
-#define REG_NOA_UNIT_SEL 0x05B5
-#define REG_P2POFF_DIS_TXTIME 0x05B7
-#define REG_MBSSID_BCN_SPACE2 0x05B8
-#define REG_MBSSID_BCN_SPACE3 0x05BC
+#define REG_HI2Q_TXBD_DESA_H 0x13BC
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_ACMHWCTRL 0x05C0
-#define REG_ACMRSTCTRL 0x05C1
-#define REG_ACMAVG 0x05C2
-#define REG_VO_ADMTIME 0x05C4
-#define REG_VI_ADMTIME 0x05C6
-#define REG_BE_ADMTIME 0x05C8
-#define REG_EDCA_RANDOM_GEN 0x05CC
-#define REG_TXCMD_NOA_SEL 0x05CF
-#define REG_NOA_PARAM 0x05E0
+#define REG_PCIE_HISR1_V1 0x13BC
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_NOA_SUBIE 0x05ED
+#define REG_HI11Q_TXBD_NUM 0x13BE
+#define REG_HI12Q_TXBD_NUM 0x13C0
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_P2P_RST 0x05F0
-#define REG_SCHEDULER_RST 0x05F1
+#define REG_HI3Q_TXBD_DESA_L 0x13C0
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_SCH_TXCMD 0x05F8
-#define REG_PAGE5_DUMMY 0x05FC
-#define REG_WMAC_CR 0x0600
+#define REG_HI13Q_TXBD_NUM 0x13C2
+#define REG_HI14Q_TXBD_NUM 0x13C4
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_WMAC_FWPKT_CR 0x0601
+#define REG_HI3Q_TXBD_DESA_H 0x13C4
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8821C_SUPPORT)
-
-#define REG_FW_STS_FILTER 0x0602
+#define REG_HI15Q_TXBD_NUM 0x13C6
+#define REG_HIQ_DMA_STOP 0x13C8
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_BWOPMODE 0x0603
+#define REG_HI4Q_TXBD_DESA_L 0x13C8
+#define REG_HI4Q_TXBD_DESA_H 0x13CC
+#define REG_HI5Q_TXBD_DESA_L 0x13D0
+#define REG_HI5Q_TXBD_DESA_H 0x13D4
+#define REG_HI6Q_TXBD_DESA_L 0x13D8
+#define REG_HI6Q_TXBD_DESA_H 0x13DC
+#define REG_HI7Q_TXBD_DESA_L 0x13E0
+#define REG_HI7Q_TXBD_DESA_H 0x13E4
+#define REG_ACH8_ACH9_TXBD_NUM 0x13E8
+#define REG_ACH10_ACH11_TXBD_NUM 0x13EC
+#define REG_ACH12_ACH13_TXBD_NUM 0x13F0
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_TCR 0x0604
-#define REG_RCR 0x0608
-#define REG_RX_PKT_LIMIT 0x060C
-#define REG_RX_DLK_TIME 0x060D
-#define REG_RX_DRVINFO_SZ 0x060F
-#define REG_MACID 0x0610
-#define REG_BSSID 0x0618
-#define REG_MAR 0x0620
-#define REG_MBIDCAMCFG_1 0x0628
-#define REG_MBIDCAMCFG_2 0x062C
+#define REG_OLD_DEHANG 0x13F4
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_MCU_TEST_1 0x0630
+#define REG_ACH4_TXBD_DESA_L 0x13F8
+#define REG_ACH4_TXBD_DESA_H 0x13FC
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_WMAC_TCR_TSFT_OFS 0x0630
-#define REG_UDF_THSD 0x0632
-#define REG_ZLD_NUM 0x0633
+#define REG_Q0_Q1_INFO 0x1400
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_MCU_TEST_2 0x0634
+#define REG_ARFR6 0x1400
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_STMP_THSD 0x0634
-#define REG_WMAC_TXTIMEOUT 0x0635
-#define REG_MCU_TEST_2_V1 0x0636
+#define REG_MU_OFFSET 0x1400
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_USTIME_EDCA 0x0638
+#define REG_Q2_Q3_INFO 0x1404
+#define REG_Q4_Q5_INFO 0x1408
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8821C_SUPPORT)
-
-#define REG_ACKTO_CCK 0x0639
+#define REG_ARFR7 0x1408
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_MAC_SPEC_SIFS 0x063A
-#define REG_RESP_SIFS_CCK 0x063C
-#define REG_RESP_SIFS_OFDM 0x063E
-#define REG_ACKTO 0x0640
-#define REG_CTS2TO 0x0641
-#define REG_EIFS 0x0642
+#define REG_Q6_Q7_INFO 0x140C
+#define REG_MGQ_HIQ_INFO 0x1410
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8821C_SUPPORT)
-
-#define REG_RPFM_MAP0 0x0644
-#define REG_RPFM_MAP1 0x0646
-#define REG_RPFM_CAM_CMD 0x0648
-#define REG_RPFM_CAM_RWD 0x064C
+#define REG_ARFR8 0x1410
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_NAV_CTRL 0x0650
-#define REG_BACAMCMD 0x0654
-#define REG_BACAMCONTENT 0x0658
-#define REG_LBDLY 0x0660
+#define REG_CMDQ_BCNQ_INFO 0x1414
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_WMAC_BACAM_RPMEN 0x0661
+#define REG_USEREG_SETTING 0x1420
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_TX_RX 0x0662
+#define REG_AESIV_SETTING 0x1424
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_RXERR_RPT 0x0664
-#define REG_WMAC_TRXPTCL_CTL 0x0668
-#define REG_CAMCMD 0x0670
-#define REG_CAMWRITE 0x0674
-#define REG_CAMREAD 0x0678
-#define REG_CAMDBG 0x067C
-#define REG_SECCFG 0x0680
+#define REG_BF0_TIME_SETTING 0x1428
+#define REG_BF1_TIME_SETTING 0x142C
+#define REG_BF_TIMEOUT_EN 0x1430
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_RXFILTER_CATEGORY_1 0x0682
-#define REG_RXFILTER_ACTION_1 0x0683
-#define REG_RXFILTER_CATEGORY_2 0x0684
-#define REG_RXFILTER_ACTION_2 0x0685
-#define REG_RXFILTER_CATEGORY_3 0x0686
-#define REG_RXFILTER_ACTION_3 0x0687
-#define REG_RXFLTMAP3 0x0688
-#define REG_RXFLTMAP4 0x068A
-#define REG_RXFLTMAP5 0x068C
-#define REG_RXFLTMAP6 0x068E
+#define REG_MACID_RELEASE0 0x1434
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_WOW_CTRL 0x0690
+#define REG_MACID_RELEASE_INFO 0x1434
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_NAN_RX_TSF_FILTER 0x0691
+#define REG_MACID_RELEASE1 0x1438
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_PS_RX_INFO 0x0692
-#define REG_WMMPS_UAPSD_TID 0x0693
-#define REG_LPNAV_CTRL 0x0694
+#define REG_MACID_RELEASE_SUCCESS_INFO 0x1438
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_WKFMCAM_NUM 0x0698
+#define REG_MACID_RELEASE2 0x143C
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_WKFMCAM_CMD 0x0698
-#define REG_WKFMCAM_RWD 0x069C
+#define REG_MACID_RELEASE_CTRL 0x143C
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_RXFLTMAP0 0x06A0
-#define REG_RXFLTMAP1 0x06A2
-#define REG_RXFLTMAP 0x06A4
-#define REG_BCN_PSR_RPT 0x06A8
+#define REG_MACID_RELEASE3 0x1440
+#define REG_MACID_RELEASE_SETTING 0x1444
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_FLC_RPC 0x06AC
-#define REG_FLC_RPCT 0x06AD
-#define REG_FLC_PTS 0x06AE
-#define REG_FLC_TRPC 0x06AF
+#define REG_FAST_EDCA_VOVI_SETTING 0x1448
+#define REG_FAST_EDCA_BEBK_SETTING 0x144C
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_RXPKTMON_CTRL 0x06B0
+#define REG_MACID_DROP0 0x1450
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_STATE_MON 0x06B4
+#define REG_MACID_DROP_INFO 0x1450
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_ERROR_MON 0x06B8
-#define REG_SEARCH_MACID 0x06BC
+#define REG_MACID_DROP1 0x1454
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_BT_COEX_TABLE 0x06C0
+#define REG_MACID_DROP_CTRL 0x1454
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_RXCMD_0 0x06D0
-#define REG_RXCMD_1 0x06D4
+#define REG_MACID_DROP2 0x1458
+#define REG_MACID_DROP3 0x145C
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_WMAC_RESP_TXINFO 0x06D8
+#define REG_R_MACID_RELEASE_SUCCESS_0 0x1460
+#define REG_R_MACID_RELEASE_SUCCESS_1 0x1464
+#define REG_R_MACID_RELEASE_SUCCESS_2 0x1468
+#define REG_R_MACID_RELEASE_SUCCESS_3 0x146C
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_BBPSF_CTRL 0x06DC
+#define REG_MGG_FIFO_CRTL 0x1470
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_P2P_RX_BCN_NOA 0x06E0
-#define REG_ASSOCIATED_BFMER0_INFO 0x06E4
-#define REG_ASSOCIATED_BFMER1_INFO 0x06EC
-#define REG_TX_CSI_RPT_PARAM_BW20 0x06F4
-#define REG_TX_CSI_RPT_PARAM_BW40 0x06F8
-#define REG_TX_CSI_RPT_PARAM_BW80 0x06FC
-#define REG_MACID1 0x0700
+#define REG_MGQ_FIFO_WRITE_POINTER 0x1470
+#define REG_MGQ_FIFO_READ_POINTER 0x1472
+#define REG_MGQ_FIFO_ENABLE 0x1472
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_BSSID1 0x0708
+#define REG_MGG_FIFO_INT 0x1474
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_BCN_PSR_RPT1 0x0710
-#define REG_ASSOCIATED_BFMEE_SEL 0x0714
-#define REG_SND_PTCL_CTRL 0x0718
-#define REG_RX_CSI_RPT_INFO 0x071C
-#define REG_NS_ARP_CTRL 0x0720
-#define REG_NS_ARP_INFO 0x0724
+#define REG_MGQ_FIFO_RELEASE_INT_MASK 0x1474
+#define REG_MGQ_FIFO_RELEASE_INT_FLAG 0x1476
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_NS_ARP_IPADDR 0x0728
+#define REG_MGG_FIFO_LIFETIME 0x1478
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_BEAMFORMING_INFO_NSARP_V1 0x0728
+#define REG_MGQ_FIFO_VALID_MAP 0x1478
+#define REG_MGQ_FIFO_LIFETIME 0x147A
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_WRITE_RX_CSI_RPT_INFO 0x072C
+#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET 0x147C
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_BEAMFORMING_INFO_NSARP 0x072C
+#define REG_SHCUT_SETTING 0x1480
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_NS_ARP_IPV6_MYADDR 0x0730
+#define REG_PKT_TRANS 0x1480
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_WMAC_RTX_CTX_SUBTYPE_CFG 0x0750
+#define REG_SHCUT_LLC_ETH_TYPE0 0x1484
+#define REG_SHCUT_LLC_ETH_TYPE1 0x1488
+#define REG_SHCUT_LLC_OUI0 0x148C
+#define REG_SHCUT_LLC_OUI1 0x1490
+#define REG_SHCUT_LLC_OUI2 0x1494
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814AMP_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_WMAC_SWAES_CFG 0x0760
+#define REG_SHCUT_LLC_OUI3 0x1498
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_BT_COEX_V2 0x0762
+#define REG_FWCMDQ_CTRL 0x14A0
+#define REG_FWCMDQ_PAGE 0x14A4
+#define REG_FWCMDQ_INFO 0x14A8
+#define REG_FWCMDQ_HOLD_PKTNUM 0x14AC
+#define REG_MU_TX_CTRL 0x14C0
#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_BT_COEX 0x0764
+#define REG_MU_TX_CTL 0x14C0
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_WLAN_ACT_MSK_CTRL 0x0768
+#define REG_MU_STA_GID_VLD 0x14C4
+#define REG_MU_STA_USER_POS_INFO 0x14C8
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_WLAN_ACT_MASK_CTRL 0x0768
+#define REG_MU_STA_USER_POS_INFO_H 0x14CC
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_BT_STATISTICS_CTRL 0x076E
-#define REG_BT_COEX_ENH_INTF_CTRL 0x076E
+#define REG_CHNL_INFO_CTRL 0x14D0
#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_BT_COEX_ENHANCED_INTR_CTRL 0x076E
+#define REG_MU_TRX_DBG_CNT 0x14D0
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_BT_ACT_STATISTICS 0x0770
+#define REG_CHNL_IDLE_TIME 0x14D4
+#define REG_CHNL_BUSY_TIME 0x14D8
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_BT_STATISTICS_OTH_CTRL 0x0778
+#define REG_MU_TRX_DBG_CNT_V1 0x14DC
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_BT_STATISTICS_CONTROL_REGISTER 0x0778
+#define REG_NEW_EDCA_CTRL 0x14F0
#endif
+#if (HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_BT_CMD_ID 0x077C
+#define REG_SWPS_CTRL 0x14F4
+#define REG_SWPS_PKT_TH 0x14F6
+#define REG_SWPS_TIME_TH 0x14F8
+#define REG_MACID_SWPS_EN 0x14FC
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_BT_STATUS_REPORT_REGISTER 0x077C
+#define REG_CPUMGQ_TX_TIMER 0x1500
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_BT__STATUS_RPT 0x077D
-#define REG_BT_DATA 0x0780
+#define REG_PORT_CTRL_SEL 0x1500
+#define REG_PORT_CTRL_CFG 0x1501
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_BT_INTERRUPT_CONTROL_REGISTER 0x0780
+#define REG_PS_TIMER_A 0x1504
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_WLAN_RPT_ 0x0781
-#define REG_BT_ISR_CTRL 0x0783
-#define REG_WLAN_RPT_TO_CTR 0x0784
+#define REG_TBTT_PROHIBIT_CFG 0x1504
+#define REG_DRVERLYINT_CFG 0x1507
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER 0x0784
+#define REG_PS_TIMER_B 0x1508
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_BT_ISOLATION_TABLE 0x0785
+#define REG_BCNDMATIM_CFG 0x1508
+#define REG_CTWND_CFG 0x1509
+#define REG_BCNIVLCUNT_CFG 0x150A
+#define REG_EARLY_128US_CFG 0x150B
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER 0x0785
+#define REG_PS_TIMER_C 0x150C
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_BT_ISR_STA 0x078F
+#define REG_TSFTR_SYNC_OFFSET_CFG 0x150C
+#define REG_TSFTR_SYNC_CTRL_CFG 0x150F
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_BT_INTERRUPT_STATUS_REGISTER 0x078F
+#define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL 0x1510
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_TDMA_TIME_AND_RPT_SAM_SET 0x0790
+#define REG_BCN_SPACE_CFG 0x1510
+#define REG_EARLY_INT_ADJUST_CFG 0x1512
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_BT_TDMA_TIME_REGISTER 0x0790
+#define REG_CPUMGQ_TX_TIMER_EARLY 0x1514
+#define REG_PS_TIMER_A_EARLY 0x1515
+#define REG_PS_TIMER_B_EARLY 0x1516
+#define REG_PS_TIMER_C_EARLY 0x1517
#endif
+#if (HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_BT_CH_INFO 0x0794
+#define REG_CPUMGQ_PARAMETER 0x1518
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_BT_ACT_REGISTER 0x0794
+#define REG_SW_TBTT_TSF_INFO 0x151C
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_BT_STATIC_INFO_EXT 0x0795
-#define REG_LTR_IDLE_LATENCY 0x0798
+#define REG_TSF_SYN_CTRL0 0x1520
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_OBFF_CTRL_BASIC 0x0798
+#define REG_TSFTR_LOW 0x1520
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_LTR_ACTIVE_LATENCY 0x079C
+#define REG_TSF_SYNC_ADJ 0x1520
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_OBFF_CTRL2_TIMER 0x079C
+#define REG_TSF_SYN_CTRL1 0x1521
+#define REG_TSF_SYN_OFFSET0 0x1522
+#define REG_TSF_SYN_OFFSET1 0x1524
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_OBFF_CTRL 0x07A0
+#define REG_TSFTR_HIGH 0x1524
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_LTR_CTRL_BASIC 0x07A0
+#define REG_TSF_ADJ_VLAUE 0x1524
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_LTR_CTRL 0x07A4
+#define REG_TSF_SYN_OFFSET2 0x1528
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_LTR_CTRL2_TIMER_THRESHOLD 0x07A4
+#define REG_BCN_ERR_CNT_MAC 0x1528
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_LTR_CTRL2 0x07A8
+#define REG_TSF_ADJ_VLAUE_2 0x1528
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_LTR_IDLE_LATENCY_V1 0x07A8
-#define REG_LTR_ACTIVE_LATENCY_V1 0x07AC
+#define REG_BCN_ERR_CNT_EDCCA 0x1529
+#define REG_BCN_ERR_CNT_CCA 0x152A
+#define REG_BCN_ERR_CNT_INVALID 0x152B
+#define REG_BCN_ERR_CNT_OTHERS 0x152C
+#define REG_RX_BCN_TIMER 0x152D
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_ANTTRN_CTRL 0x07B0
+#define REG_TSF_SYN_COMPARE_VALUE 0x1530
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_ANTENNA_TRAINING_CONTROL_REGISTER 0x07B0
+#define REG_TBTT_CTN_AREA_V1 0x1530
+#define REG_BCN_MAX_ERR_V1 0x1531
+#define REG_RXTSF_OFFSET_CCK_V1 0x1532
+#define REG_RXTSF_OFFSET_OFDM_V1 0x1533
+#define REG_SUB_BCN_SPACE 0x1534
+#define REG_MBID_NUM_V1 0x1535
+#define REG_MBSSID_CTRL_V1 0x1536
+#define REG_USTIME_TSF_V1 0x1538
+#define REG_BW_CFG 0x1539
+#define REG_ATIMWND_CFG 0x153A
+#define REG_DTIM_COUNTER_CFG 0x153B
+#define REG_ATIM_DTIM_CTRL_SEL 0x153C
+#define REG_ATIMUGT_V1 0x153D
+#define REG_BCNDROPCTRL_V1 0x153E
+#define REG_DIS_ATIM_V1 0x1540
+#define REG_HIQ_NO_LMT_EN_V1 0x1544
+#define REG_P2PPS_CTRL_V1 0x1548
+#define REG_P2PPS_SPEC_STATE_V1 0x154A
+#define REG_P2PPS_STATE_V1 0x154B
+#define REG_P2PPS1_CTRL_V1 0x154C
+#define REG_P2PPS1_SPEC_STATE_V1 0x154E
+#define REG_P2PPS1_STATE_V1 0x154F
+#define REG_P2PPS2_CTRL_V1 0x1550
+#define REG_P2PPS2_SPEC_STATE_V1 0x1552
+#define REG_P2PPS2_STATE_V1 0x1553
+#define REG_P2PON_DIS_TXTIME_V1 0x1554
+#define REG_P2POFF_DIS_TXTIME_V1 0x1555
+#define REG_CHG_POWER_BCN_AREA 0x1556
+#define REG_NOA_SEL 0x1557
+#define REG_NOA_PARAM_V1 0x1558
+#define REG_NOA_PARAM_1_V1 0x155C
+#define REG_NOA_PARAM_2_V1 0x1560
+#define REG_NOA_PARAM_3_V1 0x1564
+#define REG_NOA_ON_ERLY_TIME_V1 0x1568
+#define REG_NOA_OFF_ERLY_TIME_V1 0x1569
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8192E_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8881A_SUPPORT)
-
-#define REG_WMAC_PKTCNT_RWD 0x07B8
-#define REG_WMAC_PKTCNT_CTRL 0x07BC
+#define REG_P2PPS_HW_AUTO_PAUSE_CTRL 0x156C
+#define REG_P2PPS1_HW_AUTO_PAUSE_CTRL 0x1570
+#define REG_P2PPS2_HW_AUTO_PAUSE_CTRL 0x1574
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_IQ_DUMP 0x07C0
+#define REG_RX_TBTT_SHIFT 0x1578
+#define REG_FREERUN_CNT_LOW 0x1580
+#define REG_FREERUN_CNT_HIGH 0x1584
+#define REG_CPUMGQ_TX_TIMER_V1 0x1588
+#define REG_PS_TIMER_0 0x158C
+#define REG_PS_TIMER_1 0x1590
+#define REG_PS_TIMER_2 0x1594
+#define REG_PS_TIMER_3 0x1598
+#define REG_PS_TIMER_4 0x159C
+#define REG_PS_TIMER_5 0x15A0
+#define REG_PS_TIMER_01_CTRL 0x15A4
+#define REG_PS_TIMER_23_CTRL 0x15A8
+#define REG_PS_TIMER_45_CTRL 0x15AC
+#define REG_CPUMGQ_FREERUN_TIMER_CTRL 0x15B0
+#define REG_CPUMGQ_PROHIBIT 0x15B4
+#define REG_TIMER_COMPARE 0x15C0
+#define REG_TIMER_COMPARE_VALUE_LOW 0x15C4
+#define REG_TIMER_COMPARE_VALUE_HIGH 0x15C8
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_WMAC_FTM_CTL 0x07CC
+#define REG_BCN_PSR_RPT2 0x1600
+#define REG_BCN_PSR_RPT3 0x1604
+#define REG_BCN_PSR_RPT4 0x1608
+#define REG_A1_ADDR_MASK 0x160C
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_WMAC_IQ_MDPK_FUNC 0x07CE
+#define REG_RXPSF_CTRL 0x1610
+#define REG_RXPSF_TYPE_CTRL 0x1614
+#define REG_CAM_ACCESS_CTRL 0x1618
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
-#define REG_IQ_DUMP_EXT 0x07CF
+#define REG_CUT_AMSDU_CTRL 0x161C
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
-#define REG_OFDM_CCK_LEN_MASK 0x07D0
+#define REG_HT_SND_REF_RATE 0x161C
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_WMAC_OPTION_FUNCTION 0x07D0
+#define REG_MACID2 0x1620
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_RX_FILTER_FUNCTION 0x07DA
+#define REG_MACID2_H 0x1624
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_NDP_SIG 0x07E0
-#define REG_TXCMD_INFO_FOR_RSP_PKT 0x07E4
+#define REG_BSSID2 0x1628
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814AMP_SUPPORT)
-
-#define REG_SEC_OPT 0x07E8
+#define REG_BSSID2_H 0x162C
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
-#define REG_SEC_OPT_V2 0x07EC
+#define REG_MACID3 0x1630
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT)
-
-#define REG_WSEC_OPTION 0x07EC
+#define REG_MACID3_H 0x1634
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_RTS_ADDRESS_0 0x07F0
+#define REG_BSSID3 0x1638
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814AMP_SUPPORT)
-
-#define REG_RTS_ADDR0 0x07F0
+#define REG_BSSID3_H 0x163C
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_RTS_ADDRESS_1 0x07F8
+#define REG_MACID4 0x1640
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8814AMP_SUPPORT)
-
-#define REG_RTS_ADDR1 0x07F8
+#define REG_MACID4_H 0x1644
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814A_SUPPORT || \
+ HALMAC_8814AMP_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8822B_SUPPORT)
-
-#define REG__RPFM_MAP1 0x07FE
+#define REG_BSSID4 0x1648
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_SYS_CFG3 0x1000
-#define REG_SYS_CFG4 0x1034
+#define REG_BSSID4_H 0x164C
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_SYS_CFG5 0x1070
+#define REG_NOA_REPORT 0x1650
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_CPU_DMEM_CON 0x1080
+#define REG_NOA_REPORT_1 0x1654
+#define REG_NOA_REPORT_2 0x1658
+#define REG_NOA_REPORT_3 0x165C
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_BOOT_REASON 0x1088
-#define REG_NFCPAD_CTRL 0x10A8
+#define REG_PWRBIT_SETTING 0x1660
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_HIMR2 0x10B0
-#define REG_HISR2 0x10B4
-#define REG_HIMR3 0x10B8
-#define REG_HISR3 0x10BC
-#define REG_SW_MDIO 0x10C0
-#define REG_SW_FLUSH 0x10C4
+#define REG_GENERAL_OPTION 0x1664
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
-#define REG_DBG_GPIO_BMUX 0x10C8
-#define REG_FPGA_TAG 0x10CC
-#define REG_WL_DSS_CTRL0 0x10D0
+#define REG_FWPHYFF_RCR 0x1668
+#define REG_ADDRCAM_WRITE_CONTENT 0x166C
+#define REG_ADDRCAM_READ_CONTENT 0x1670
+#define REG_ADDRCAM_CFG 0x1674
#endif
+#if (HALMAC_8198F_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_H2C_PKT_READADDR 0x10D0
-#define REG_H2C_PKT_WRITEADDR 0x10D4
+#define REG_WMAC_CSI_FRAME_RRSR_SETTING 0x1678
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
-#define REG_WL_DSS_CTRL1 0x10D8
+#define REG_CSI_RRSR 0x1678
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822B_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_MEM_PWR_CRTL 0x10D8
+#define REG_WMAC_MU_BF_OPTION 0x167C
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
-#define REG_WL_DSS_STATUS1 0x10DC
+#define REG_MU_BF_OPTION 0x167C
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_FW_DBG0 0x10E0
-#define REG_FW_DBG1 0x10E4
-#define REG_FW_DBG2 0x10E8
-#define REG_FW_DBG3 0x10EC
-#define REG_FW_DBG4 0x10F0
-#define REG_FW_DBG5 0x10F4
-#define REG_FW_DBG6 0x10F8
-#define REG_FW_DBG7 0x10FC
-#define REG_CR_EXT 0x1100
-#define REG_FWFF 0x1114
+#define REG_WMAC_PAUSE_BB_CLR_TH 0x167D
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_RXFF_PTR_V1 0x1118
-#define REG_RXFF_WTR_V1 0x111C
+#define REG_WMAC_MU_ARB 0x167E
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_FE2IMR 0x1120
-#define REG_FE2ISR 0x1124
-#define REG_FE3IMR 0x1128
-#define REG_FE3ISR 0x112C
-#define REG_FE4IMR 0x1130
-#define REG_FE4ISR 0x1134
-#define REG_FT1IMR 0x1138
-#define REG_FT1ISR 0x113C
-#define REG_SPWR0 0x1140
-#define REG_SPWR1 0x1144
-#define REG_SPWR2 0x1148
-#define REG_SPWR3 0x114C
-#define REG_POWSEQ 0x1150
+#define REG_WMAC_MULBK_BUF 0x167E
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_TC7_CTRL_V1 0x1158
-#define REG_TC8_CTRL_V1 0x115C
+#define REG__WMAC_MULBK_BUF 0x167E
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
-#define REG_RXBCN_TBTT_INTERVAL_PORT0TO3 0x1160
-#define REG_RXBCN_TBTT_INTERVAL_PORT4 0x1164
+#define REG_WMAC_MU_OPTION 0x167F
+#define REG_WMAC_MU_BF_CTL 0x1680
+#define REG_WMAC_MU_BFRPT_PARA 0x1682
+#define REG_WMAC_ASSOCIATED_MU_BFMEE2 0x1684
+#define REG_WMAC_ASSOCIATED_MU_BFMEE3 0x1686
+#define REG_WMAC_ASSOCIATED_MU_BFMEE4 0x1688
+#define REG_WMAC_ASSOCIATED_MU_BFMEE5 0x168A
+#define REG_WMAC_ASSOCIATED_MU_BFMEE6 0x168C
+#define REG_WMAC_ASSOCIATED_MU_BFMEE7 0x168E
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
-#define REG_EXT_QUEUE_REG 0x11C0
-#define REG_COUNTER_CONTROL 0x11C4
-#define REG_COUNTER_TH 0x11C8
-#define REG_COUNTER_SET 0x11CC
-#define REG_COUNTER_OVERFLOW 0x11D0
-#define REG_TDE_LEN_TH 0x11D4
-#define REG_RDE_LEN_TH 0x11D8
-#define REG_PCIE_EXEC_TIME 0x11DC
+#define REG_WMAC_BB_STOP_RX_COUNTER 0x1690
+#define REG_WMAC_PLCP_MONITOR 0x1694
#endif
+#if (HALMAC_8814B_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_FT2IMR 0x11E0
-#define REG_FT2ISR 0x11E4
+#define REG_WMAC_DEBUG_PORT 0x1698
#endif
+#if (HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_MSG2 0x11F0
-#define REG_MSG3 0x11F4
-#define REG_MSG4 0x11F8
-#define REG_MSG5 0x11FC
-#define REG_DDMA_CH0SA 0x1200
-#define REG_DDMA_CH0DA 0x1204
-#define REG_DDMA_CH0CTRL 0x1208
-#define REG_DDMA_CH1SA 0x1210
-#define REG_DDMA_CH1DA 0x1214
-#define REG_DDMA_CH1CTRL 0x1218
-#define REG_DDMA_CH2SA 0x1220
-#define REG_DDMA_CH2DA 0x1224
-#define REG_DDMA_CH2CTRL 0x1228
-#define REG_DDMA_CH3SA 0x1230
-#define REG_DDMA_CH3DA 0x1234
-#define REG_DDMA_CH3CTRL 0x1238
-#define REG_DDMA_CH4SA 0x1240
-#define REG_DDMA_CH4DA 0x1244
-#define REG_DDMA_CH4CTRL 0x1248
-#define REG_DDMA_CH5SA 0x1250
-#define REG_DDMA_CH5DA 0x1254
-#define REG_REG_DDMA_CH5CTRL 0x1258
-#define REG_DDMA_INT_MSK 0x12E0
-#define REG_DDMA_CHSTATUS 0x12E8
-#define REG_DDMA_CHKSUM 0x12F0
-#define REG_DDMA_MONITOR 0x12FC
+#define REG_WMAC_PLCP_MONITOR_MUTX 0x1698
#endif
+#if (HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_STC_INT_CS 0x1300
-#define REG_ST_INT_CFG 0x1304
-#define REG_CMU_DLY_CTRL 0x1310
-#define REG_CMU_DLY_CFG 0x1314
-#define REG_H2CQ_TXBD_DESA 0x1320
-#define REG_H2CQ_TXBD_NUM 0x1328
-#define REG_H2CQ_TXBD_IDX 0x132C
-#define REG_H2CQ_CSR 0x1330
+#define REG_WMAC_CSIDMA_CFG 0x169C
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT)
-
-#define REG_AXI_EXCEPT_CS 0x1350
-#define REG_AXI_EXCEPT_TIME 0x1354
+#define REG_TRANSMIT_ADDRSS_0 0x16A0
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_Q0_Q1_INFO 0x1400
-#define REG_Q2_Q3_INFO 0x1404
-#define REG_Q4_Q5_INFO 0x1408
-#define REG_Q6_Q7_INFO 0x140C
-#define REG_MGQ_HIQ_INFO 0x1410
-#define REG_CMDQ_BCNQ_INFO 0x1414
-#define REG_USEREG_SETTING 0x1420
-#define REG_AESIV_SETTING 0x1424
-#define REG_BF0_TIME_SETTING 0x1428
-#define REG_BF1_TIME_SETTING 0x142C
-#define REG_BF_TIMEOUT_EN 0x1430
-#define REG_MACID_RELEASE0 0x1434
-#define REG_MACID_RELEASE1 0x1438
-#define REG_MACID_RELEASE2 0x143C
-#define REG_MACID_RELEASE3 0x1440
-#define REG_MACID_RELEASE_SETTING 0x1444
-#define REG_FAST_EDCA_VOVI_SETTING 0x1448
-#define REG_FAST_EDCA_BEBK_SETTING 0x144C
-#define REG_MACID_DROP0 0x1450
-#define REG_MACID_DROP1 0x1454
-#define REG_MACID_DROP2 0x1458
-#define REG_MACID_DROP3 0x145C
+#define REG_TRANSMIT_ADDRSS_0_H 0x16A4
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_R_MACID_RELEASE_SUCCESS_0 0x1460
-#define REG_R_MACID_RELEASE_SUCCESS_1 0x1464
-#define REG_R_MACID_RELEASE_SUCCESS_2 0x1468
-#define REG_R_MACID_RELEASE_SUCCESS_3 0x146C
-#define REG_MGG_FIFO_CRTL 0x1470
-#define REG_MGG_FIFO_INT 0x1474
-#define REG_MGG_FIFO_LIFETIME 0x1478
-#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET 0x147C
+#define REG_TRANSMIT_ADDRSS_1 0x16A8
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
-#define REG_SHCUT_SETTING 0x1480
+#define REG_TRANSMIT_ADDRSS_1_H 0x16AC
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8822B_SUPPORT)
-
-#define REG_MACID_SHCUT_OFFSET 0x1480
+#define REG_TRANSMIT_ADDRSS_2 0x16B0
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814AMP_SUPPORT)
-
-#define REG_SHCUT_LLC_ETH_TYPE0 0x1484
-#define REG_SHCUT_LLC_ETH_TYPE1 0x1488
-#define REG_SHCUT_LLC_OUI0 0x148C
-#define REG_SHCUT_LLC_OUI1 0x1490
-#define REG_SHCUT_LLC_OUI2 0x1494
-#define REG_SHCUT_LLC_OUI3 0x1498
+#define REG_TRANSMIT_ADDRSS_2_H 0x16B4
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_MU_TX_CTL 0x14C0
-#define REG_MU_STA_GID_VLD 0x14C4
-#define REG_MU_STA_USER_POS_INFO 0x14C8
-#define REG_MU_TRX_DBG_CNT 0x14D0
+#define REG_TRANSMIT_ADDRSS_3 0x16B8
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_CPUMGQ_TX_TIMER 0x1500
-#define REG_PS_TIMER_A 0x1504
-#define REG_PS_TIMER_B 0x1508
-#define REG_PS_TIMER_C 0x150C
-#define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL 0x1510
-#define REG_CPUMGQ_TX_TIMER_EARLY 0x1514
-#define REG_PS_TIMER_A_EARLY 0x1515
-#define REG_PS_TIMER_B_EARLY 0x1516
-#define REG_PS_TIMER_C_EARLY 0x1517
+#define REG_TRANSMIT_ADDRSS_3_H 0x16BC
#endif
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8814A_SUPPORT || HALMAC_8814AMP_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_BCN_PSR_RPT2 0x1600
-#define REG_BCN_PSR_RPT3 0x1604
-#define REG_BCN_PSR_RPT4 0x1608
-#define REG_A1_ADDR_MASK 0x160C
-#define REG_MACID2 0x1620
-#define REG_BSSID2 0x1628
-#define REG_MACID3 0x1630
-#define REG_BSSID3 0x1638
-#define REG_MACID4 0x1640
-#define REG_BSSID4 0x1648
+#define REG_TRANSMIT_ADDRSS_4 0x16C0
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#if (HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_NOA_REPORT 0x1650
-#define REG_PWRBIT_SETTING 0x1660
-#define REG_TRANSMIT_ADDRSS_0 0x16A0
-#define REG_TRANSMIT_ADDRSS_1 0x16A8
-#define REG_TRANSMIT_ADDRSS_2 0x16B0
-#define REG_TRANSMIT_ADDRSS_3 0x16B8
-#define REG_TRANSMIT_ADDRSS_4 0x16C0
+#define REG_TRANSMIT_ADDRSS_4_H 0x16C4
#endif
+#if (HALMAC_8814B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#if (HALMAC_8821C_SUPPORT || HALMAC_8822B_SUPPORT)
-
-#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 0x1700
-#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 0x1704
-#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 0x1708
+#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 0x1700
+#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 0x1704
+#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 0x1708
#endif
+#if (HALMAC_8814B_SUPPORT)
+#define REG_BIST_RSTN0 0x2100
+#define REG_BIST_RSTN2 0x2108
+#define REG_BIST_MODE_NRML0 0x2110
+#define REG_BIST_MODE_NRML1 0x2114
+#define REG_BIST_MODE_NRML2 0x2118
+#define REG_BIST_MODE_NRML3 0x211C
+#define REG_BIST_DONE_NRML_MAC 0x2150
+#define REG_BIST_DONE_NRML1 0x2158
+#define REG_BIST_DONE_DRF_MAC 0x2160
+#define REG_BIST_DONE_DRF 0x2164
+#define REG_BIST_DONE_DRF1 0x2168
+#define REG_BIST_FAIL_NRML_MAC 0x2170
+#define REG_BIST_FAIL_NRML 0x2174
+#define REG_BIST_FAIL_NRML1 0x2178
+#define REG_BIST_FAIL_NRML_MAC_V1 0x2180
+#define REG_BIST_FAIL_NRML_V1 0x2184
+#define REG_BIST_FAIL_NRML1_V1 0x2188
+#define REG_BIST_MISR_DATAOUT 0x2190
+#define REG_BIST_MISR_DATAOUT1 0x2194
+#define REG_BIST_MISR_DATAOUT_CPU 0x2198
+#define REG_BIST_MISR_DATAOUT_CPU1 0x219C
+#define REG_BIST_MISR_DATAOUT_CPU2 0x21A0
+#define REG_BIST_MISR_DATOUT_CPU3 0x21A4
+#define REG_DMA_RQPN_INFO_0 0x2200
+#define REG_DMA_RQPN_INFO_1 0x2204
+#define REG_DMA_RQPN_INFO_2 0x2208
+#define REG_DMA_RQPN_INFO_3 0x220C
+#define REG_DMA_RQPN_INFO_4 0x2210
+#define REG_DMA_RQPN_INFO_5 0x2214
+#define REG_DMA_RQPN_INFO_6 0x2218
+#define REG_DMA_RQPN_INFO_7 0x221C
+#define REG_DMA_RQPN_INFO_8 0x2220
+#define REG_DMA_RQPN_INFO_9 0x2224
+#define REG_DMA_RQPN_INFO_10 0x2228
+#define REG_DMA_RQPN_INFO_11 0x222C
+#define REG_DMA_RQPN_INFO_12 0x2230
+#define REG_DMA_RQPN_INFO_13 0x2234
+#define REG_DMA_RQPN_INFO_14 0x2238
+#define REG_DMA_RQPN_INFO_15 0x223C
+#define REG_DMA_RQPN_INFO_16 0x2240
+#define REG_HWAMSDU_CTL1 0x2250
+#define REG_HWAMSDU_CTL2 0x2254
+#define REG_HI8Q_TXBD_DESA_L 0x2300
+#define REG_HI8Q_TXBD_DESA_H 0x2304
+#define REG_HI9Q_TXBD_DESA_L 0x2308
+#define REG_HI9Q_TXBD_DESA_H 0x230C
+#define REG_HI10Q_TXBD_DESA_L 0x2310
+#define REG_HI10Q_TXBD_DESA_H 0x2314
+#define REG_HI11Q_TXBD_DESA_L 0x2318
+#define REG_HI11Q_TXBD_DESA_H 0x231C
+#define REG_HI12Q_TXBD_DESA_L 0x2320
+#define REG_HI12Q_TXBD_DESA_H 0x2324
+#define REG_HI13Q_TXBD_DESA_L 0x2328
+#define REG_HI13Q_TXBD_DESA_H 0x232C
+#define REG_HI14Q_TXBD_DESA_L 0x2330
+#define REG_HI14Q_TXBD_DESA_H 0x2334
+#define REG_HI15Q_TXBD_DESA_L 0x2338
+#define REG_HI15Q_TXBD_DESA_H 0x233C
+#define REG_HI16Q_TXBD_DESA_L 0x2340
+#define REG_HI16Q_TXBD_DESA_H 0x2344
+#define REG_HI17Q_TXBD_DESA_L 0x2348
+#define REG_HI17Q_TXBD_DESA_H 0x234C
+#define REG_HI18Q_TXBD_DESA_L 0x2350
+#define REG_HI18Q_TXBD_DESA_H 0x2354
+#define REG_HI19Q_TXBD_DESA_L 0x2358
+#define REG_HI19Q_TXBD_DESA_H 0x235C
+#define REG_BD_RWPTR_CLR6 0x2364
+#define REG_P0HI16Q_TXBD_IDX 0x2370
+#define REG_P0HI17Q_TXBD_IDX 0x2374
+#define REG_P0HI18Q_TXBD_IDX 0x2378
+#define REG_P0HI19Q_TXBD_IDX 0x237C
+#define REG_P0HI16Q_HI17Q_TXBD_NUM 0x2380
+#define REG_P0HI18Q_HI19Q_TXBD_NUM 0x2384
+#define REG_PCIE_HISR0 0x23B4
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+#define REG_PCIE_HISR2_V1 0x23B4
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_PCIE_HISR1 0x23BC
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+#define REG_PCIE_HISR3_V1 0x23BC
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define REG_P0HI8Q_HI9Q_TXBD_NUM 0x23C0
+#define REG_P0HI10Q_HI11Q_TXBD_NUM 0x23C4
+#define REG_P0HI12Q_HI13Q_TXBD_NUM 0x23C8
+#define REG_P0HI14Q_HI15Q_TXBD_NUM 0x23CC
+#define REG_ACH6_ACH7_TXBD_NUM 0x23F0
+#define REG_TXPAGE_INT_CTRL_0 0x3200
+#define REG_TXPAGE_INT_CTRL_1 0x3204
+#define REG_TXPAGE_INT_CTRL_2 0x3208
+#define REG_TXPAGE_INT_CTRL_3 0x320C
+#define REG_TXPAGE_INT_CTRL_4 0x3210
+#define REG_TXPAGE_INT_CTRL_5 0x3214
+#define REG_TXPAGE_INT_CTRL_6 0x3218
+#define REG_TXPAGE_INT_CTRL_7 0x321C
+#define REG_TXPAGE_INT_CTRL_8 0x3220
+#define REG_TXPAGE_INT_CTRL_9 0x3224
+#define REG_TXPAGE_INT_CTRL_10 0x3228
+#define REG_TXPAGE_INT_CTRL_11 0x322C
+#define REG_TXPAGE_INT_CTRL_12 0x3230
+#define REG_TXPAGE_INT_CTRL_13 0x3234
+#define REG_TXPAGE_INT_CTRL_14 0x3238
+#define REG_TXPAGE_INT_CTRL_15 0x323C
+#define REG_TXPAGE_INT_CTRL_16 0x3240
+#define REG_ACH4_TXBD_IDX 0x3340
+#define REG_ACH5_TXBD_IDX 0x3344
+#define REG_ACH6_TXBD_IDX 0x3348
+#define REG_ACH7_TXBD_IDX 0x334C
+#define REG_ACH8_TXBD_IDX 0x3350
+#define REG_ACH9_TXBD_IDX 0x3354
+#define REG_ACH10_TXBD_IDX 0x3358
+#define REG_ACH11_TXBD_IDX 0x335C
+#define REG_ACH12_TXBD_IDX 0x3360
+#define REG_ACH13_TXBD_IDX 0x3364
+#define REG_AC_CHANNEL0_WEIGHT 0x3368
+#define REG_AC_CHANNEL1_WEIGHT 0x3369
+#define REG_AC_CHANNEL2_WEIGHT 0x336A
+#define REG_AC_CHANNEL3_WEIGHT 0x336B
+#define REG_AC_CHANNEL4_WEIGHT 0x336C
+#define REG_AC_CHANNEL5_WEIGHT 0x336D
+#define REG_AC_CHANNEL6_WEIGHT 0x336E
+#define REG_AC_CHANNEL7_WEIGHT 0x336F
+#define REG_AC_CHANNEL8_WEIGHT 0x3370
+#define REG_AC_CHANNEL9_WEIGHT 0x3371
+#define REG_AC_CHANNEL10_WEIGHT 0x3372
+#define REG_AC_CHANNEL11_WEIGHT 0x3373
+#define REG_AC_CHANNEL12_WEIGHT 0x3374
+#define REG_AC_CHANNEL13_WEIGHT 0x3375
+#define REG_PCIE_HISR2 0x33B4
+#define REG_PCIE_HISR3 0x33BC
+
+#endif
/* ----------------------------------------------------- */
/* */
/* 0xFB00h ~ 0xFCFFh TX/RX packet buffer affress */
/* */
/* ----------------------------------------------------- */
-#define REG_RXPKTBUF_STARTADDR 0xFB00
-#define REG_TXPKTBUF_STARTADDR 0xFC00
+#define REG_RXPKTBUF_STARTADDR 0xFB00
+#define REG_TXPKTBUF_STARTADDR 0xFC00
/* ----------------------------------------------------- */
/* */
/* 0xFD00h ~ 0xFDFFh 8051 CPU Local REG */
/* */
/* ----------------------------------------------------- */
-#define REG_SYS_CTRL 0xFD00
-#define REG_PONSTS_RPT1 0xFD01
-#define REG_PONSTS_RPT2 0xFD02
-#define REG_PONSTS_RPT3 0xFD03
-#define REG_PONSTS_RPT4 0xFD04 /* 0x84 */
-#define REG_PONSTS_RPT5 0xFD05 /* 0x85 */
-#define REG_8051ERRFLAG 0xFD08
-#define REG_8051ERRFLAG_MASK 0xFD09
-#define REG_TXADDRH 0xFD10 /* Tx Packet High Address */
-#define REG_RXADDRH 0xFD11 /* Rx Packet High Address */
-#define REG_TXADDRH_EXT 0xFD12 /* 0xFD12[0] : for 8051 access txpktbuf high64k as external register */
-
-#define REG_U3_STATE 0xFD48 /* (Read only) [7:4] : usb3 changed last state. [3:0] usb3 state */
+#define REG_SYS_CTRL 0xFD00
+#define REG_PONSTS_RPT1 0xFD01
+#define REG_PONSTS_RPT2 0xFD02
+#define REG_PONSTS_RPT3 0xFD03
+#define REG_PONSTS_RPT4 0xFD04 /* 0x84 */
+#define REG_PONSTS_RPT5 0xFD05 /* 0x85 */
+#define REG_8051ERRFLAG 0xFD08
+#define REG_8051ERRFLAG_MASK 0xFD09
+#define REG_TXADDRH 0xFD10 /* Tx Packet High Address */
+#define REG_RXADDRH 0xFD11 /* Rx Packet High Address */
+#define REG_TXADDRH_EXT 0xFD12
+
+#define REG_U3_STATE 0xFD48
/* for MAILBOX */
-#define REG_OUTDATA0 0xFD50
-#define REG_OUTDATA1 0xFD54
-#define REG_OUTRDY 0xFD58 /* bit[0] : OutReady, bit[1] : OutEmptyIntEn */
+#define REG_OUTDATA0 0xFD50
+#define REG_OUTDATA1 0xFD54
+#define REG_OUTRDY 0xFD58 /* bit[0] : OutReady, bit[1] : OutEmptyIntEn */
-#define REG_INDATA0 0xFD60
-#define REG_INDATA1 0xFD64
-#define REG_INRDY 0xFD68 /* bit[0] : InReady, bit[1] : InRdyIntEn */
+#define REG_INDATA0 0xFD60
+#define REG_INDATA1 0xFD64
+#define REG_INRDY 0xFD68 /* bit[0] : InReady, bit[1] : InRdyIntEn */
/* MCU ERROR debug REG */
-#define REG_MCUERR_PCLSB 0xFD90 /* PC[7:0] */
-#define REG_MCUERR_PCMSB 0xFD91 /* PC[15:8] */
-#define REG_MCUERR_ACC 0xFD92
-#define REG_MCUERR_B 0xFD93
-#define REG_MCUERR_DPTRLSB 0xFD94 /* DPTR[7:0] */
-#define REG_MCUERR_DPTRMSB 0xFD95 /* DPTR[15:8] */
-#define REG_MCUERR_SP 0xFD96 /* SP[7:0] */
-#define REG_MCUERR_IE 0xFD97 /* IE[7:0] */
-#define REG_MCUERR_EIE 0xFD98 /* EIE[7:0] */
-#define REG_VERA_SIM 0xFD9F
+#define REG_MCUERR_PCLSB 0xFD90 /* PC[7:0] */
+#define REG_MCUERR_PCMSB 0xFD91 /* PC[15:8] */
+#define REG_MCUERR_ACC 0xFD92
+#define REG_MCUERR_B 0xFD93
+#define REG_MCUERR_DPTRLSB 0xFD94 /* DPTR[7:0] */
+#define REG_MCUERR_DPTRMSB 0xFD95 /* DPTR[15:8] */
+#define REG_MCUERR_SP 0xFD96 /* SP[7:0] */
+#define REG_MCUERR_IE 0xFD97 /* IE[7:0] */
+#define REG_MCUERR_EIE 0xFD98 /* EIE[7:0] */
+#define REG_VERA_SIM 0xFD9F
/* 0xFD99~0xFD9F are reserved.. */
/* ----------------------------------------------------- */
@@ -2917,70 +6886,69 @@
/* ----------------------------------------------------- */
/* RTS5101 USB Register Definition */
-#define REG_USB_SETUP_DEC_INT 0xFE00
-#define REG_USB_DMACTL 0xFE01
-#define REG_USB_IRQSTAT0 0xFE02
-#define REG_USB_IRQSTAT1 0xFE03
-#define REG_USB_IRQEN0 0xFE04
-#define REG_USB_IRQEN1 0xFE05
-#define REG_USB_AUTOPTRL 0xFE06
-#define REG_USB_AUTOPTRH 0xFE07
-#define REG_USB_AUTODAT 0xFE08
-
-#define REG_USB_SCRATCH0 0xFE09
-#define REG_USB_SCRATCH1 0xFE0A
-#define REG_USB_SEEPROM 0xFE0B
-#define REG_USB_GPIO0 0xFE0C
-#define REG_USB_GPIO0DIR 0xFE0D
-#define REG_USB_CLKSEL 0xFE0E
-#define REG_USB_BOOTCTL 0xFE0F
-
-#define REG_USB_USBCTL 0xFE10
-#define REG_USB_USBSTAT 0xFE11
-#define REG_USB_DEVADDR 0xFE12
-#define REG_USB_USBTEST 0xFE13
-#define REG_USB_FNUM0 0xFE14
-#define REG_USB_FNUM1 0xFE15
-
-#define REG_USB_EP_IDX 0xFE20
-#define REG_USB_EP_CFG 0xFE21
-#define REG_USB_EP_CTL 0xFE22
-#define REG_USB_EP_STAT 0xFE23
-#define REG_USB_EP_IRQ 0xFE24
-#define REG_USB_EP_IRQEN 0xFE25
-#define REG_USB_EP_MAXPKT0 0xFE26
-#define REG_USB_EP_MAXPKT1 0xFE27
-#define REG_USB_EP_DAT 0xFE28
-#define REG_USB_EP_BC0 0xFE29
-#define REG_USB_EP_BC1 0xFE2A
-#define REG_USB_EP_TC0 0xFE2B
-#define REG_USB_EP_TC1 0xFE2C
-#define REG_USB_EP_TC2 0xFE2D
-#define REG_USB_EP_CTL2 0xFE2E
-
-#define REG_USB_INFO 0xFE17
-#define REG_USB_SPECIAL_OPTION 0xFE55
-#define REG_USB_DMA_AGG_TO 0xFE5B
-#define REG_USB_AGG_TO 0xFE5C
-#define REG_USB_AGG_TH 0xFE5D
-
-#define REG_USB_VID 0xFE60
-#define REG_USB_PID 0xFE62
-#define REG_USB_OPT 0xFE64
-#define REG_USB_CONFIG 0xFE65 /* RX EP setting. 0xFE65 Bit[3:0] : RXQ, Bit[7:4] : INTQ */
- /* TX EP setting. 0xFE66 Bit[3:0] : TXQ0, Bit[7:4] : TXQ1, 0xFE67 Bit[3:0] : TXQ2 */
-#define REG_USB_PHY_PARA1 0xFE68 /* Bit[7:4]: XCVR_SEN (USB PHY 0xE2[7:4]), Bit[3:0]: XCVR_SH (USB PHY 0xE2[3:0]) */
-#define REG_USB_PHY_PARA2 0xFE69 /* Bit[7:5]: XCVR_BG (USB PHY 0xE3[5:3]), Bit[4:2]: XCVR_DR (USB PHY 0xE3[2:0]), Bit[1]: SE0_LVL (USB PHY 0xE5[7]), Bit[0]: FORCE_XTL_ON (USB PHY 0xE5[1]) */
-#define REG_USB_PHY_PARA3 0xFE6A /* Bit[7:5]: XCVR_SRC (USB PHY 0xE5[4:2]), Bit[4]: LATE_DLLEN (USB PHY 0xF0[4]), Bit[3]: HS_LP_MODE (USB PHY 0xF0[3]), Bit[2]: UTMI_POS_OUT (USB PHY 0xF1 [7]), Bit[1:0]: TX_DELAY (USB PHY 0xF1 [2:1]) */
-#define REG_USB_PHY_PARA4 0xFE6B /* (USB PHY 0xE7[7:0]) */
-#define REG_USB_OPT2 0xFE6C
-#define REG_USB_MAC_ADDR 0xFE70 /* 0xFE70~0xFE75 */
-#define REG_USB_MANUFACTURE_SETTING 0xFE80 /* 0xFE80~0xFE90 Max : 32 bytes */
-#define REG_USB_PRODUCT_STRING 0xFEA0 /* 0xFEA0~0xFECF Max : 48 bytes */
-#define REG_USB_SERIAL_NUMBER_STRING 0xFED0 /* 0xFED0~0xFEDF Max : 12 bytes */
-
-#define REG_USB_ALTERNATE_SETTING 0xFE4F
-#define REG_USB_INT_BINTERVAL 0xFE6E
-#define REG_USB_GPS_EP_CONFIG 0xFE6D
-
-#endif /* __HALMAC_COM_REG_H__ */
+#define REG_USB_SETUP_DEC_INT 0xFE00
+#define REG_USB_DMACTL 0xFE01
+#define REG_USB_IRQSTAT0 0xFE02
+#define REG_USB_IRQSTAT1 0xFE03
+#define REG_USB_IRQEN0 0xFE04
+#define REG_USB_IRQEN1 0xFE05
+#define REG_USB_AUTOPTRL 0xFE06
+#define REG_USB_AUTOPTRH 0xFE07
+#define REG_USB_AUTODAT 0xFE08
+
+#define REG_USB_SCRATCH0 0xFE09
+#define REG_USB_SCRATCH1 0xFE0A
+#define REG_USB_SEEPROM 0xFE0B
+#define REG_USB_GPIO0 0xFE0C
+#define REG_USB_GPIO0DIR 0xFE0D
+#define REG_USB_CLKSEL 0xFE0E
+#define REG_USB_BOOTCTL 0xFE0F
+
+#define REG_USB_USBCTL 0xFE10
+#define REG_USB_USBSTAT 0xFE11
+#define REG_USB_DEVADDR 0xFE12
+#define REG_USB_USBTEST 0xFE13
+#define REG_USB_FNUM0 0xFE14
+#define REG_USB_FNUM1 0xFE15
+
+#define REG_USB_EP_IDX 0xFE20
+#define REG_USB_EP_CFG 0xFE21
+#define REG_USB_EP_CTL 0xFE22
+#define REG_USB_EP_STAT 0xFE23
+#define REG_USB_EP_IRQ 0xFE24
+#define REG_USB_EP_IRQEN 0xFE25
+#define REG_USB_EP_MAXPKT0 0xFE26
+#define REG_USB_EP_MAXPKT1 0xFE27
+#define REG_USB_EP_DAT 0xFE28
+#define REG_USB_EP_BC0 0xFE29
+#define REG_USB_EP_BC1 0xFE2A
+#define REG_USB_EP_TC0 0xFE2B
+#define REG_USB_EP_TC1 0xFE2C
+#define REG_USB_EP_TC2 0xFE2D
+#define REG_USB_EP_CTL2 0xFE2E
+
+#define REG_USB_INFO 0xFE17
+#define REG_USB_SPECIAL_OPTION 0xFE55
+#define REG_USB_DMA_AGG_TO 0xFE5B
+#define REG_USB_AGG_TO 0xFE5C
+#define REG_USB_AGG_TH 0xFE5D
+
+#define REG_USB_VID 0xFE60
+#define REG_USB_PID 0xFE62
+#define REG_USB_OPT 0xFE64
+#define REG_USB_CONFIG 0xFE65
+
+#define REG_USB_PHY_PARA1 0xFE68
+#define REG_USB_PHY_PARA2 0xFE69
+#define REG_USB_PHY_PARA3 0xFE6A
+#define REG_USB_OPT2 0xFE6C
+#define REG_USB_MAC_ADDR 0xFE70
+#define REG_USB_MANUFACTURE_SETTING 0xFE80
+#define REG_USB_PRODUCT_STRING 0xFEA0
+#define REG_USB_SERIAL_NUMBER_STRING 0xFED0
+
+#define REG_USB_ALTERNATE_SETTING 0xFE4F
+#define REG_USB_INT_BINTERVAL 0xFE6E
+#define REG_USB_GPS_EP_CONFIG 0xFE6D
+
+#endif /* __HALMAC_COM_REG_H__ */
diff --git a/hal/halmac/halmac_reg_8197f.h b/hal/halmac/halmac_reg_8197f.h
new file mode 100644
index 0000000..6be0b3f
--- /dev/null
+++ b/hal/halmac/halmac_reg_8197f.h
@@ -0,0 +1,700 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef __INC_HALMAC_REG_8197F_H
+#define __INC_HALMAC_REG_8197F_H
+
+#define REG_SYS_ISO_CTRL_8197F 0x0000
+#define REG_SYS_FUNC_EN_8197F 0x0002
+#define REG_SYS_PW_CTRL_8197F 0x0004
+#define REG_SYS_CLK_CTRL_8197F 0x0008
+#define REG_SYS_EEPROM_CTRL_8197F 0x000A
+#define REG_EE_VPD_8197F 0x000C
+#define REG_SYS_SWR_CTRL1_8197F 0x0010
+#define REG_SYS_SWR_CTRL2_8197F 0x0014
+#define REG_SYS_SWR_CTRL3_8197F 0x0018
+#define REG_RSV_CTRL_8197F 0x001C
+#define REG_RF0_CTRL_8197F 0x001F
+#define REG_AFE_LDO_CTRL_8197F 0x0020
+#define REG_AFE_CTRL1_8197F 0x0024
+#define REG_AFE_CTRL2_8197F 0x0028
+#define REG_AFE_CTRL3_8197F 0x002C
+#define REG_EFUSE_CTRL_8197F 0x0030
+#define REG_LDO_EFUSE_CTRL_8197F 0x0034
+#define REG_PWR_OPTION_CTRL_8197F 0x0038
+#define REG_CAL_TIMER_8197F 0x003C
+#define REG_ACLK_MON_8197F 0x003E
+#define REG_GPIO_MUXCFG_8197F 0x0040
+#define REG_GPIO_PIN_CTRL_8197F 0x0044
+#define REG_GPIO_INTM_8197F 0x0048
+#define REG_LED_CFG_8197F 0x004C
+#define REG_FSIMR_8197F 0x0050
+#define REG_FSISR_8197F 0x0054
+#define REG_HSIMR_8197F 0x0058
+#define REG_HSISR_8197F 0x005C
+#define REG_GPIO_EXT_CTRL_8197F 0x0060
+#define REG_PAD_CTRL1_8197F 0x0064
+#define REG_WL_BT_PWR_CTRL_8197F 0x0068
+#define REG_SDM_DEBUG_8197F 0x006C
+#define REG_SYS_SDIO_CTRL_8197F 0x0070
+#define REG_HCI_OPT_CTRL_8197F 0x0074
+#define REG_AFE_CTRL4_8197F 0x0078
+#define REG_LDO_SWR_CTRL_8197F 0x007C
+#define REG_MCUFW_CTRL_8197F 0x0080
+#define REG_MCU_TST_CFG_8197F 0x0084
+#define REG_HMEBOX_E0_E1_8197F 0x0088
+#define REG_HMEBOX_E2_E3_8197F 0x008C
+#define REG_WLLPS_CTRL_8197F 0x0090
+#define REG_AFE_CTRL5_8197F 0x0094
+#define REG_GPIO_DEBOUNCE_CTRL_8197F 0x0098
+#define REG_RPWM2_8197F 0x009C
+#define REG_SYSON_FSM_MON_8197F 0x00A0
+#define REG_AFE_CTRL6_8197F 0x00A4
+#define REG_PMC_DBG_CTRL1_8197F 0x00A8
+#define REG_AFE_CTRL7_8197F 0x00AC
+#define REG_HIMR0_8197F 0x00B0
+#define REG_HISR0_8197F 0x00B4
+#define REG_HIMR1_8197F 0x00B8
+#define REG_HISR1_8197F 0x00BC
+#define REG_DBG_PORT_SEL_8197F 0x00C0
+#define REG_PAD_CTRL2_8197F 0x00C4
+#define REG_PMC_DBG_CTRL2_8197F 0x00CC
+#define REG_BIST_CTRL_8197F 0x00D0
+#define REG_BIST_RPT_8197F 0x00D4
+#define REG_MEM_CTRL_8197F 0x00D8
+#define REG_AFE_CTRL8_8197F 0x00DC
+#define REG_USB_SIE_INTF_8197F 0x00E0
+#define REG_PCIE_MIO_INTF_8197F 0x00E4
+#define REG_PCIE_MIO_INTD_8197F 0x00E8
+#define REG_WLRF1_8197F 0x00EC
+#define REG_SYS_CFG1_8197F 0x00F0
+#define REG_SYS_STATUS1_8197F 0x00F4
+#define REG_SYS_STATUS2_8197F 0x00F8
+#define REG_SYS_CFG2_8197F 0x00FC
+#define REG_SYS_CFG3_8197F 0x1000
+#define REG_SYS_CFG4_8197F 0x1034
+#define REG_CPU_DMEM_CON_8197F 0x1080
+#define REG_HIMR2_8197F 0x10B0
+#define REG_HISR2_8197F 0x10B4
+#define REG_HIMR3_8197F 0x10B8
+#define REG_HISR3_8197F 0x10BC
+#define REG_SW_MDIO_8197F 0x10C0
+#define REG_SW_FLUSH_8197F 0x10C4
+#define REG_DBG_GPIO_BMUX_8197F 0x10C8
+#define REG_FPGA_TAG_8197F 0x10CC
+#define REG_WL_DSS_CTRL0_8197F 0x10D0
+#define REG_WL_DSS_CTRL1_8197F 0x10D8
+#define REG_WL_DSS_STATUS1_8197F 0x10DC
+#define REG_FW_DBG0_8197F 0x10E0
+#define REG_FW_DBG1_8197F 0x10E4
+#define REG_FW_DBG2_8197F 0x10E8
+#define REG_FW_DBG3_8197F 0x10EC
+#define REG_FW_DBG4_8197F 0x10F0
+#define REG_FW_DBG5_8197F 0x10F4
+#define REG_FW_DBG6_8197F 0x10F8
+#define REG_FW_DBG7_8197F 0x10FC
+#define REG_CR_8197F 0x0100
+#define REG_TSF_CLK_STATE_8197F 0x0108
+#define REG_TXDMA_PQ_MAP_8197F 0x010C
+#define REG_TRXFF_BNDY_8197F 0x0114
+#define REG_PTA_I2C_MBOX_8197F 0x0118
+#define REG_RXFF_BNDY_8197F 0x011C
+#define REG_FE1IMR_8197F 0x0120
+#define REG_FE1ISR_8197F 0x0124
+#define REG_CPWM_8197F 0x012C
+#define REG_FWIMR_8197F 0x0130
+#define REG_FWISR_8197F 0x0134
+#define REG_FTIMR_8197F 0x0138
+#define REG_FTISR_8197F 0x013C
+#define REG_PKTBUF_DBG_CTRL_8197F 0x0140
+#define REG_PKTBUF_DBG_DATA_L_8197F 0x0144
+#define REG_PKTBUF_DBG_DATA_H_8197F 0x0148
+#define REG_CPWM2_8197F 0x014C
+#define REG_TC0_CTRL_8197F 0x0150
+#define REG_TC1_CTRL_8197F 0x0154
+#define REG_TC2_CTRL_8197F 0x0158
+#define REG_TC3_CTRL_8197F 0x015C
+#define REG_TC4_CTRL_8197F 0x0160
+#define REG_TCUNIT_BASE_8197F 0x0164
+#define REG_TC5_CTRL_8197F 0x0168
+#define REG_TC6_CTRL_8197F 0x016C
+#define REG_MBIST_FAIL_8197F 0x0170
+#define REG_MBIST_START_PAUSE_8197F 0x0174
+#define REG_MBIST_DONE_8197F 0x0178
+#define REG_MBIST_FAIL_NRML_8197F 0x017C
+#define REG_AES_DECRPT_DATA_8197F 0x0180
+#define REG_AES_DECRPT_CFG_8197F 0x0184
+#define REG_MACCLKFRQ_8197F 0x018C
+#define REG_TMETER_8197F 0x0190
+#define REG_OSC_32K_CTRL_8197F 0x0194
+#define REG_32K_CAL_REG1_8197F 0x0198
+#define REG_C2HEVT_8197F 0x01A0
+#define REG_SW_DEFINED_PAGE1_8197F 0x01B8
+#define REG_MCUTST_I_8197F 0x01C0
+#define REG_MCUTST_II_8197F 0x01C4
+#define REG_FMETHR_8197F 0x01C8
+#define REG_HMETFR_8197F 0x01CC
+#define REG_HMEBOX0_8197F 0x01D0
+#define REG_HMEBOX1_8197F 0x01D4
+#define REG_HMEBOX2_8197F 0x01D8
+#define REG_HMEBOX3_8197F 0x01DC
+#define REG_LLT_INIT_8197F 0x01E0
+#define REG_LLT_INIT_ADDR_8197F 0x01E4
+#define REG_BB_ACCESS_CTRL_8197F 0x01E8
+#define REG_BB_ACCESS_DATA_8197F 0x01EC
+#define REG_HMEBOX_E0_8197F 0x01F0
+#define REG_HMEBOX_E1_8197F 0x01F4
+#define REG_HMEBOX_E2_8197F 0x01F8
+#define REG_HMEBOX_E3_8197F 0x01FC
+#define REG_CR_EXT_8197F 0x1100
+#define REG_FWFF_8197F 0x1114
+#define REG_RXFF_PTR_V1_8197F 0x1118
+#define REG_RXFF_WTR_V1_8197F 0x111C
+#define REG_FE2IMR_8197F 0x1120
+#define REG_FE2ISR_8197F 0x1124
+#define REG_FE3IMR_8197F 0x1128
+#define REG_FE3ISR_8197F 0x112C
+#define REG_FE4IMR_8197F 0x1130
+#define REG_FE4ISR_8197F 0x1134
+#define REG_FT1IMR_8197F 0x1138
+#define REG_FT1ISR_8197F 0x113C
+#define REG_SPWR0_8197F 0x1140
+#define REG_SPWR1_8197F 0x1144
+#define REG_SPWR2_8197F 0x1148
+#define REG_SPWR3_8197F 0x114C
+#define REG_POWSEQ_8197F 0x1150
+#define REG_TC7_CTRL_V1_8197F 0x1158
+#define REG_TC8_CTRL_V1_8197F 0x115C
+#define REG_RXBCN_TBTT_INTERVAL_PORT0TO3_8197F 0x1160
+#define REG_RXBCN_TBTT_INTERVAL_PORT4_8197F 0x1164
+#define REG_EXT_QUEUE_REG_8197F 0x11C0
+#define REG_COUNTER_CONTROL_8197F 0x11C4
+#define REG_COUNTER_TH_8197F 0x11C8
+#define REG_COUNTER_SET_8197F 0x11CC
+#define REG_COUNTER_OVERFLOW_8197F 0x11D0
+#define REG_TDE_LEN_TH_8197F 0x11D4
+#define REG_RDE_LEN_TH_8197F 0x11D8
+#define REG_PCIE_EXEC_TIME_8197F 0x11DC
+#define REG_FT2IMR_8197F 0x11E0
+#define REG_FT2ISR_8197F 0x11E4
+#define REG_MSG2_8197F 0x11F0
+#define REG_MSG3_8197F 0x11F4
+#define REG_MSG4_8197F 0x11F8
+#define REG_MSG5_8197F 0x11FC
+#define REG_FIFOPAGE_CTRL_1_8197F 0x0200
+#define REG_FIFOPAGE_CTRL_2_8197F 0x0204
+#define REG_AUTO_LLT_V1_8197F 0x0208
+#define REG_TXDMA_OFFSET_CHK_8197F 0x020C
+#define REG_TXDMA_STATUS_8197F 0x0210
+#define REG_TX_DMA_DBG_8197F 0x0214
+#define REG_TQPNT1_8197F 0x0218
+#define REG_TQPNT2_8197F 0x021C
+#define REG_TQPNT3_8197F 0x0220
+#define REG_TQPNT4_8197F 0x0224
+#define REG_RQPN_CTRL_1_8197F 0x0228
+#define REG_RQPN_CTRL_2_8197F 0x022C
+#define REG_FIFOPAGE_INFO_1_8197F 0x0230
+#define REG_FIFOPAGE_INFO_2_8197F 0x0234
+#define REG_FIFOPAGE_INFO_3_8197F 0x0238
+#define REG_FIFOPAGE_INFO_4_8197F 0x023C
+#define REG_FIFOPAGE_INFO_5_8197F 0x0240
+#define REG_H2C_HEAD_8197F 0x0244
+#define REG_H2C_TAIL_8197F 0x0248
+#define REG_H2C_READ_ADDR_8197F 0x024C
+#define REG_H2C_WR_ADDR_8197F 0x0250
+#define REG_H2C_INFO_8197F 0x0254
+#define REG_RXDMA_AGG_PG_TH_8197F 0x0280
+#define REG_RXPKT_NUM_8197F 0x0284
+#define REG_RXDMA_STATUS_8197F 0x0288
+#define REG_RXDMA_DPR_8197F 0x028C
+#define REG_RXDMA_MODE_8197F 0x0290
+#define REG_C2H_PKT_8197F 0x0294
+#define REG_FWFF_C2H_8197F 0x0298
+#define REG_FWFF_CTRL_8197F 0x029C
+#define REG_FWFF_PKT_INFO_8197F 0x02A0
+#define REG_FC2H_INFO_8197F 0x02A4
+#define REG_DDMA_CH0SA_8197F 0x1200
+#define REG_DDMA_CH0DA_8197F 0x1204
+#define REG_DDMA_CH0CTRL_8197F 0x1208
+#define REG_DDMA_CH1SA_8197F 0x1210
+#define REG_DDMA_CH1DA_8197F 0x1214
+#define REG_DDMA_CH1CTRL_8197F 0x1218
+#define REG_DDMA_CH2SA_8197F 0x1220
+#define REG_DDMA_CH2DA_8197F 0x1224
+#define REG_DDMA_CH2CTRL_8197F 0x1228
+#define REG_DDMA_CH3SA_8197F 0x1230
+#define REG_DDMA_CH3DA_8197F 0x1234
+#define REG_DDMA_CH3CTRL_8197F 0x1238
+#define REG_DDMA_CH4SA_8197F 0x1240
+#define REG_DDMA_CH4DA_8197F 0x1244
+#define REG_DDMA_CH4CTRL_8197F 0x1248
+#define REG_DDMA_CH5SA_8197F 0x1250
+#define REG_DDMA_CH5DA_8197F 0x1254
+#define REG_REG_DDMA_CH5CTRL_8197F 0x1258
+#define REG_DDMA_INT_MSK_8197F 0x12E0
+#define REG_DDMA_CHSTATUS_8197F 0x12E8
+#define REG_DDMA_CHKSUM_8197F 0x12F0
+#define REG_DDMA_MONITOR_8197F 0x12FC
+#define REG_HCI_CTRL_8197F 0x0300
+#define REG_INT_MIG_8197F 0x0304
+#define REG_BCNQ_TXBD_DESA_8197F 0x0308
+#define REG_MGQ_TXBD_DESA_8197F 0x0310
+#define REG_VOQ_TXBD_DESA_8197F 0x0318
+#define REG_VIQ_TXBD_DESA_8197F 0x0320
+#define REG_BEQ_TXBD_DESA_8197F 0x0328
+#define REG_BKQ_TXBD_DESA_8197F 0x0330
+#define REG_RXQ_RXBD_DESA_8197F 0x0338
+#define REG_HI0Q_TXBD_DESA_8197F 0x0340
+#define REG_HI1Q_TXBD_DESA_8197F 0x0348
+#define REG_HI2Q_TXBD_DESA_8197F 0x0350
+#define REG_HI3Q_TXBD_DESA_8197F 0x0358
+#define REG_HI4Q_TXBD_DESA_8197F 0x0360
+#define REG_HI5Q_TXBD_DESA_8197F 0x0368
+#define REG_HI6Q_TXBD_DESA_8197F 0x0370
+#define REG_HI7Q_TXBD_DESA_8197F 0x0378
+#define REG_MGQ_TXBD_NUM_8197F 0x0380
+#define REG_RX_RXBD_NUM_8197F 0x0382
+#define REG_VOQ_TXBD_NUM_8197F 0x0384
+#define REG_VIQ_TXBD_NUM_8197F 0x0386
+#define REG_BEQ_TXBD_NUM_8197F 0x0388
+#define REG_BKQ_TXBD_NUM_8197F 0x038A
+#define REG_HI0Q_TXBD_NUM_8197F 0x038C
+#define REG_HI1Q_TXBD_NUM_8197F 0x038E
+#define REG_HI2Q_TXBD_NUM_8197F 0x0390
+#define REG_HI3Q_TXBD_NUM_8197F 0x0392
+#define REG_HI4Q_TXBD_NUM_8197F 0x0394
+#define REG_HI5Q_TXBD_NUM_8197F 0x0396
+#define REG_HI6Q_TXBD_NUM_8197F 0x0398
+#define REG_HI7Q_TXBD_NUM_8197F 0x039A
+#define REG_TSFTIMER_HCI_8197F 0x039C
+#define REG_BD_RWPTR_CLR_8197F 0x039C
+#define REG_VOQ_TXBD_IDX_8197F 0x03A0
+#define REG_VIQ_TXBD_IDX_8197F 0x03A4
+#define REG_BEQ_TXBD_IDX_8197F 0x03A8
+#define REG_BKQ_TXBD_IDX_8197F 0x03AC
+#define REG_MGQ_TXBD_IDX_8197F 0x03B0
+#define REG_RXQ_RXBD_IDX_8197F 0x03B4
+#define REG_HI0Q_TXBD_IDX_8197F 0x03B8
+#define REG_HI1Q_TXBD_IDX_8197F 0x03BC
+#define REG_HI2Q_TXBD_IDX_8197F 0x03C0
+#define REG_HI3Q_TXBD_IDX_8197F 0x03C4
+#define REG_HI4Q_TXBD_IDX_8197F 0x03C8
+#define REG_HI5Q_TXBD_IDX_8197F 0x03CC
+#define REG_HI6Q_TXBD_IDX_8197F 0x03D0
+#define REG_HI7Q_TXBD_IDX_8197F 0x03D4
+#define REG_DBG_SEL_V1_8197F 0x03D8
+#define REG_HCI_HRPWM1_V1_8197F 0x03D9
+#define REG_HCI_HCPWM1_V1_8197F 0x03DA
+#define REG_HCI_CTRL2_8197F 0x03DB
+#define REG_HCI_HRPWM2_V1_8197F 0x03DC
+#define REG_HCI_HCPWM2_V1_8197F 0x03DE
+#define REG_HCI_H2C_MSG_V1_8197F 0x03E0
+#define REG_HCI_C2H_MSG_V1_8197F 0x03E4
+#define REG_DBI_WDATA_V1_8197F 0x03E8
+#define REG_DBI_RDATA_V1_8197F 0x03EC
+#define REG_STUCK_FLAG_V1_8197F 0x03F0
+#define REG_MDIO_V1_8197F 0x03F4
+#define REG_WDT_CFG_8197F 0x03F8
+#define REG_HCI_MIX_CFG_8197F 0x03FC
+#define REG_STC_INT_CS_8197F 0x1300
+#define REG_ST_INT_CFG_8197F 0x1304
+#define REG_CMU_DLY_CTRL_8197F 0x1310
+#define REG_CMU_DLY_CFG_8197F 0x1314
+#define REG_H2CQ_TXBD_DESA_8197F 0x1320
+#define REG_H2CQ_TXBD_NUM_8197F 0x1328
+#define REG_H2CQ_TXBD_IDX_8197F 0x132C
+#define REG_H2CQ_CSR_8197F 0x1330
+#define REG_AXI_EXCEPT_CS_8197F 0x1350
+#define REG_AXI_EXCEPT_TIME_8197F 0x1354
+#define REG_Q0_INFO_8197F 0x0400
+#define REG_Q1_INFO_8197F 0x0404
+#define REG_Q2_INFO_8197F 0x0408
+#define REG_Q3_INFO_8197F 0x040C
+#define REG_MGQ_INFO_8197F 0x0410
+#define REG_HIQ_INFO_8197F 0x0414
+#define REG_BCNQ_INFO_8197F 0x0418
+#define REG_TXPKT_EMPTY_8197F 0x041A
+#define REG_CPU_MGQ_INFO_8197F 0x041C
+#define REG_FWHW_TXQ_CTRL_8197F 0x0420
+#define REG_BCNQ_BDNY_V1_8197F 0x0424
+#define REG_LIFETIME_EN_8197F 0x0426
+#define REG_SPEC_SIFS_8197F 0x0428
+#define REG_RETRY_LIMIT_8197F 0x042A
+#define REG_TXBF_CTRL_8197F 0x042C
+#define REG_DARFRC_8197F 0x0430
+#define REG_RARFRC_8197F 0x0438
+#define REG_RRSR_8197F 0x0440
+#define REG_ARFR0_8197F 0x0444
+#define REG_ARFR1_V1_8197F 0x044C
+#define REG_CCK_CHECK_8197F 0x0454
+#define REG_AMPDU_MAX_TIME_V1_8197F 0x0455
+#define REG_BCNQ1_BDNY_V1_8197F 0x0456
+#define REG_AMPDU_MAX_LENGTH_8197F 0x0458
+#define REG_ACQ_STOP_8197F 0x045C
+#define REG_NDPA_RATE_8197F 0x045D
+#define REG_TX_HANG_CTRL_8197F 0x045E
+#define REG_NDPA_OPT_CTRL_8197F 0x045F
+#define REG_RD_RESP_PKT_TH_8197F 0x0463
+#define REG_CMDQ_INFO_8197F 0x0464
+#define REG_Q4_INFO_8197F 0x0468
+#define REG_Q5_INFO_8197F 0x046C
+#define REG_Q6_INFO_8197F 0x0470
+#define REG_Q7_INFO_8197F 0x0474
+#define REG_WMAC_LBK_BUF_HD_V1_8197F 0x0478
+#define REG_MGQ_BDNY_V1_8197F 0x047A
+#define REG_TXRPT_CTRL_8197F 0x047C
+#define REG_INIRTS_RATE_SEL_8197F 0x0480
+#define REG_BASIC_CFEND_RATE_8197F 0x0481
+#define REG_STBC_CFEND_RATE_8197F 0x0482
+#define REG_DATA_SC_8197F 0x0483
+#define REG_MACID_SLEEP3_8197F 0x0484
+#define REG_MACID_SLEEP1_8197F 0x0488
+#define REG_ARFR2_V1_8197F 0x048C
+#define REG_ARFR3_V1_8197F 0x0494
+#define REG_ARFR4_8197F 0x049C
+#define REG_ARFR5_8197F 0x04A4
+#define REG_TXRPT_START_OFFSET_8197F 0x04AC
+#define REG_POWER_STAGE1_8197F 0x04B4
+#define REG_POWER_STAGE2_8197F 0x04B8
+#define REG_SW_AMPDU_BURST_MODE_CTRL_8197F 0x04BC
+#define REG_PKT_LIFE_TIME_8197F 0x04C0
+#define REG_STBC_SETTING_8197F 0x04C4
+#define REG_STBC_SETTING2_8197F 0x04C5
+#define REG_QUEUE_CTRL_8197F 0x04C6
+#define REG_SINGLE_AMPDU_CTRL_8197F 0x04C7
+#define REG_PROT_MODE_CTRL_8197F 0x04C8
+#define REG_BAR_MODE_CTRL_8197F 0x04CC
+#define REG_RA_TRY_RATE_AGG_LMT_8197F 0x04CF
+#define REG_MACID_SLEEP2_8197F 0x04D0
+#define REG_MACID_SLEEP_8197F 0x04D4
+#define REG_HW_SEQ0_8197F 0x04D8
+#define REG_HW_SEQ1_8197F 0x04DA
+#define REG_HW_SEQ2_8197F 0x04DC
+#define REG_HW_SEQ3_8197F 0x04DE
+#define REG_NULL_PKT_STATUS_V1_8197F 0x04E0
+#define REG_PTCL_ERR_STATUS_8197F 0x04E2
+#define REG_NULL_PKT_STATUS_EXTEND_8197F 0x04E3
+#define REG_VIDEO_ENHANCEMENT_FUN_8197F 0x04E4
+#define REG_BT_POLLUTE_PKT_CNT_8197F 0x04E8
+#define REG_PTCL_DBG_8197F 0x04EC
+#define REG_TXOP_EXTRA_CTRL_8197F 0x04F0
+#define REG_CPUMGQ_TIMER_CTRL2_8197F 0x04F4
+#define REG_DUMMY_PAGE4_8197F 0x04FC
+#define REG_Q0_Q1_INFO_8197F 0x1400
+#define REG_Q2_Q3_INFO_8197F 0x1404
+#define REG_Q4_Q5_INFO_8197F 0x1408
+#define REG_Q6_Q7_INFO_8197F 0x140C
+#define REG_MGQ_HIQ_INFO_8197F 0x1410
+#define REG_CMDQ_BCNQ_INFO_8197F 0x1414
+#define REG_USEREG_SETTING_8197F 0x1420
+#define REG_AESIV_SETTING_8197F 0x1424
+#define REG_BF0_TIME_SETTING_8197F 0x1428
+#define REG_BF1_TIME_SETTING_8197F 0x142C
+#define REG_BF_TIMEOUT_EN_8197F 0x1430
+#define REG_MACID_RELEASE0_8197F 0x1434
+#define REG_MACID_RELEASE1_8197F 0x1438
+#define REG_MACID_RELEASE2_8197F 0x143C
+#define REG_MACID_RELEASE3_8197F 0x1440
+#define REG_MACID_RELEASE_SETTING_8197F 0x1444
+#define REG_FAST_EDCA_VOVI_SETTING_8197F 0x1448
+#define REG_FAST_EDCA_BEBK_SETTING_8197F 0x144C
+#define REG_MACID_DROP0_8197F 0x1450
+#define REG_MACID_DROP1_8197F 0x1454
+#define REG_MACID_DROP2_8197F 0x1458
+#define REG_MACID_DROP3_8197F 0x145C
+#define REG_R_MACID_RELEASE_SUCCESS_0_8197F 0x1460
+#define REG_R_MACID_RELEASE_SUCCESS_1_8197F 0x1464
+#define REG_R_MACID_RELEASE_SUCCESS_2_8197F 0x1468
+#define REG_R_MACID_RELEASE_SUCCESS_3_8197F 0x146C
+#define REG_MGG_FIFO_CRTL_8197F 0x1470
+#define REG_MGG_FIFO_INT_8197F 0x1474
+#define REG_MGG_FIFO_LIFETIME_8197F 0x1478
+#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F 0x147C
+#define REG_SHCUT_SETTING_8197F 0x1480
+#define REG_SHCUT_LLC_ETH_TYPE0_8197F 0x1484
+#define REG_SHCUT_LLC_ETH_TYPE1_8197F 0x1488
+#define REG_SHCUT_LLC_OUI0_8197F 0x148C
+#define REG_SHCUT_LLC_OUI1_8197F 0x1490
+#define REG_SHCUT_LLC_OUI2_8197F 0x1494
+#define REG_SHCUT_LLC_OUI3_8197F 0x1498
+#define REG_CHNL_INFO_CTRL_8197F 0x14D0
+#define REG_CHNL_IDLE_TIME_8197F 0x14D4
+#define REG_CHNL_BUSY_TIME_8197F 0x14D8
+#define REG_EDCA_VO_PARAM_8197F 0x0500
+#define REG_EDCA_VI_PARAM_8197F 0x0504
+#define REG_EDCA_BE_PARAM_8197F 0x0508
+#define REG_EDCA_BK_PARAM_8197F 0x050C
+#define REG_BCNTCFG_8197F 0x0510
+#define REG_PIFS_8197F 0x0512
+#define REG_RDG_PIFS_8197F 0x0513
+#define REG_SIFS_8197F 0x0514
+#define REG_TSFTR_SYN_OFFSET_8197F 0x0518
+#define REG_AGGR_BREAK_TIME_8197F 0x051A
+#define REG_SLOT_8197F 0x051B
+#define REG_TX_PTCL_CTRL_8197F 0x0520
+#define REG_TXPAUSE_8197F 0x0522
+#define REG_DIS_TXREQ_CLR_8197F 0x0523
+#define REG_RD_CTRL_8197F 0x0524
+#define REG_MBSSID_CTRL_8197F 0x0526
+#define REG_P2PPS_CTRL_8197F 0x0527
+#define REG_PKT_LIFETIME_CTRL_8197F 0x0528
+#define REG_P2PPS_SPEC_STATE_8197F 0x052B
+#define REG_QUEUE_INCOL_THR_8197F 0x0538
+#define REG_QUEUE_INCOL_EN_8197F 0x053C
+#define REG_TBTT_PROHIBIT_8197F 0x0540
+#define REG_P2PPS_STATE_8197F 0x0543
+#define REG_RD_NAV_NXT_8197F 0x0544
+#define REG_NAV_PROT_LEN_8197F 0x0546
+#define REG_FTM_CTRL_8197F 0x0548
+#define REG_FTM_TSF_CNT_8197F 0x054C
+#define REG_BCN_CTRL_8197F 0x0550
+#define REG_BCN_CTRL_CLINT0_8197F 0x0551
+#define REG_MBID_NUM_8197F 0x0552
+#define REG_DUAL_TSF_RST_8197F 0x0553
+#define REG_MBSSID_BCN_SPACE_8197F 0x0554
+#define REG_DRVERLYINT_8197F 0x0558
+#define REG_BCNDMATIM_8197F 0x0559
+#define REG_ATIMWND_8197F 0x055A
+#define REG_USTIME_TSF_8197F 0x055C
+#define REG_BCN_MAX_ERR_8197F 0x055D
+#define REG_RXTSF_OFFSET_CCK_8197F 0x055E
+#define REG_RXTSF_OFFSET_OFDM_8197F 0x055F
+#define REG_TSFTR_8197F 0x0560
+#define REG_FREERUN_CNT_8197F 0x0568
+#define REG_ATIMWND1_8197F 0x0570
+#define REG_TBTT_PROHIBIT_INFRA_8197F 0x0571
+#define REG_CTWND_8197F 0x0572
+#define REG_BCNIVLCUNT_8197F 0x0573
+#define REG_BCNDROPCTRL_8197F 0x0574
+#define REG_HGQ_TIMEOUT_PERIOD_8197F 0x0575
+#define REG_TXCMD_TIMEOUT_PERIOD_8197F 0x0576
+#define REG_MISC_CTRL_8197F 0x0577
+#define REG_BCN_CTRL_CLINT1_8197F 0x0578
+#define REG_BCN_CTRL_CLINT2_8197F 0x0579
+#define REG_BCN_CTRL_CLINT3_8197F 0x057A
+#define REG_EXTEND_CTRL_8197F 0x057B
+#define REG_P2PPS1_SPEC_STATE_8197F 0x057C
+#define REG_P2PPS1_STATE_8197F 0x057D
+#define REG_P2PPS2_SPEC_STATE_8197F 0x057E
+#define REG_P2PPS2_STATE_8197F 0x057F
+#define REG_PS_TIMER0_8197F 0x0580
+#define REG_PS_TIMER1_8197F 0x0584
+#define REG_PS_TIMER2_8197F 0x0588
+#define REG_TBTT_CTN_AREA_8197F 0x058C
+#define REG_FORCE_BCN_IFS_8197F 0x058E
+#define REG_TXOP_MIN_8197F 0x0590
+#define REG_PRE_BKF_TIME_8197F 0x0592
+#define REG_CROSS_TXOP_CTRL_8197F 0x0593
+#define REG_TBTT_INT_SHIFT_CLI0_8197F 0x0594
+#define REG_TBTT_INT_SHIFT_CLI1_8197F 0x0595
+#define REG_TBTT_INT_SHIFT_CLI2_8197F 0x0596
+#define REG_TBTT_INT_SHIFT_CLI3_8197F 0x0597
+#define REG_TBTT_INT_SHIFT_ENABLE_8197F 0x0598
+#define REG_ATIMWND2_8197F 0x05A0
+#define REG_ATIMWND3_8197F 0x05A1
+#define REG_ATIMWND4_8197F 0x05A2
+#define REG_ATIMWND5_8197F 0x05A3
+#define REG_ATIMWND6_8197F 0x05A4
+#define REG_ATIMWND7_8197F 0x05A5
+#define REG_ATIMUGT_8197F 0x05A6
+#define REG_HIQ_NO_LMT_EN_8197F 0x05A7
+#define REG_DTIM_COUNTER_ROOT_8197F 0x05A8
+#define REG_DTIM_COUNTER_VAP1_8197F 0x05A9
+#define REG_DTIM_COUNTER_VAP2_8197F 0x05AA
+#define REG_DTIM_COUNTER_VAP3_8197F 0x05AB
+#define REG_DTIM_COUNTER_VAP4_8197F 0x05AC
+#define REG_DTIM_COUNTER_VAP5_8197F 0x05AD
+#define REG_DTIM_COUNTER_VAP6_8197F 0x05AE
+#define REG_DTIM_COUNTER_VAP7_8197F 0x05AF
+#define REG_DIS_ATIM_8197F 0x05B0
+#define REG_EARLY_128US_8197F 0x05B1
+#define REG_P2PPS1_CTRL_8197F 0x05B2
+#define REG_P2PPS2_CTRL_8197F 0x05B3
+#define REG_TIMER0_SRC_SEL_8197F 0x05B4
+#define REG_NOA_UNIT_SEL_8197F 0x05B5
+#define REG_P2POFF_DIS_TXTIME_8197F 0x05B7
+#define REG_MBSSID_BCN_SPACE2_8197F 0x05B8
+#define REG_MBSSID_BCN_SPACE3_8197F 0x05BC
+#define REG_ACMHWCTRL_8197F 0x05C0
+#define REG_ACMRSTCTRL_8197F 0x05C1
+#define REG_ACMAVG_8197F 0x05C2
+#define REG_VO_ADMTIME_8197F 0x05C4
+#define REG_VI_ADMTIME_8197F 0x05C6
+#define REG_BE_ADMTIME_8197F 0x05C8
+#define REG_EDCA_RANDOM_GEN_8197F 0x05CC
+#define REG_TXCMD_NOA_SEL_8197F 0x05CF
+#define REG_NOA_PARAM_8197F 0x05E0
+#define REG_P2P_RST_8197F 0x05F0
+#define REG_SCHEDULER_RST_8197F 0x05F1
+#define REG_SCH_TXCMD_8197F 0x05F8
+#define REG_PAGE5_DUMMY_8197F 0x05FC
+#define REG_CPUMGQ_TX_TIMER_8197F 0x1500
+#define REG_PS_TIMER_A_8197F 0x1504
+#define REG_PS_TIMER_B_8197F 0x1508
+#define REG_PS_TIMER_C_8197F 0x150C
+#define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8197F 0x1510
+#define REG_CPUMGQ_TX_TIMER_EARLY_8197F 0x1514
+#define REG_PS_TIMER_A_EARLY_8197F 0x1515
+#define REG_PS_TIMER_B_EARLY_8197F 0x1516
+#define REG_PS_TIMER_C_EARLY_8197F 0x1517
+#define REG_WMAC_CR_8197F 0x0600
+#define REG_WMAC_FWPKT_CR_8197F 0x0601
+#define REG_BWOPMODE_8197F 0x0603
+#define REG_TCR_8197F 0x0604
+#define REG_RCR_8197F 0x0608
+#define REG_RX_PKT_LIMIT_8197F 0x060C
+#define REG_RX_DLK_TIME_8197F 0x060D
+#define REG_RX_DRVINFO_SZ_8197F 0x060F
+#define REG_MACID_8197F 0x0610
+#define REG_BSSID_8197F 0x0618
+#define REG_MAR_8197F 0x0620
+#define REG_MBIDCAMCFG_1_8197F 0x0628
+#define REG_MBIDCAMCFG_2_8197F 0x062C
+#define REG_WMAC_TCR_TSFT_OFS_8197F 0x0630
+#define REG_UDF_THSD_8197F 0x0632
+#define REG_ZLD_NUM_8197F 0x0633
+#define REG_STMP_THSD_8197F 0x0634
+#define REG_WMAC_TXTIMEOUT_8197F 0x0635
+#define REG_MCU_TEST_2_V1_8197F 0x0636
+#define REG_USTIME_EDCA_8197F 0x0638
+#define REG_MAC_SPEC_SIFS_8197F 0x063A
+#define REG_RESP_SIFS_CCK_8197F 0x063C
+#define REG_RESP_SIFS_OFDM_8197F 0x063E
+#define REG_ACKTO_8197F 0x0640
+#define REG_CTS2TO_8197F 0x0641
+#define REG_EIFS_8197F 0x0642
+#define REG_NAV_CTRL_8197F 0x0650
+#define REG_BACAMCMD_8197F 0x0654
+#define REG_BACAMCONTENT_8197F 0x0658
+#define REG_LBDLY_8197F 0x0660
+#define REG_WMAC_BACAM_RPMEN_8197F 0x0661
+#define REG_WMAC_BITMAP_CTL_8197F 0x0663
+#define REG_RXERR_RPT_8197F 0x0664
+#define REG_WMAC_TRXPTCL_CTL_8197F 0x0668
+#define REG_CAMCMD_8197F 0x0670
+#define REG_CAMWRITE_8197F 0x0674
+#define REG_CAMREAD_8197F 0x0678
+#define REG_CAMDBG_8197F 0x067C
+#define REG_SECCFG_8197F 0x0680
+#define REG_RXFILTER_CATEGORY_1_8197F 0x0682
+#define REG_RXFILTER_ACTION_1_8197F 0x0683
+#define REG_RXFILTER_CATEGORY_2_8197F 0x0684
+#define REG_RXFILTER_ACTION_2_8197F 0x0685
+#define REG_RXFILTER_CATEGORY_3_8197F 0x0686
+#define REG_RXFILTER_ACTION_3_8197F 0x0687
+#define REG_RXFLTMAP3_8197F 0x0688
+#define REG_RXFLTMAP4_8197F 0x068A
+#define REG_RXFLTMAP5_8197F 0x068C
+#define REG_RXFLTMAP6_8197F 0x068E
+#define REG_WOW_CTRL_8197F 0x0690
+#define REG_PS_RX_INFO_8197F 0x0692
+#define REG_WMMPS_UAPSD_TID_8197F 0x0693
+#define REG_LPNAV_CTRL_8197F 0x0694
+#define REG_WKFMCAM_CMD_8197F 0x0698
+#define REG_WKFMCAM_RWD_8197F 0x069C
+#define REG_RXFLTMAP0_8197F 0x06A0
+#define REG_RXFLTMAP1_8197F 0x06A2
+#define REG_RXFLTMAP_8197F 0x06A4
+#define REG_BCN_PSR_RPT_8197F 0x06A8
+#define REG_RXPKTMON_CTRL_8197F 0x06B0
+#define REG_STATE_MON_8197F 0x06B4
+#define REG_ERROR_MON_8197F 0x06B8
+#define REG_SEARCH_MACID_8197F 0x06BC
+#define REG_BT_COEX_TABLE_8197F 0x06C0
+#define REG_RXCMD_0_8197F 0x06D0
+#define REG_RXCMD_1_8197F 0x06D4
+#define REG_WMAC_RESP_TXINFO_8197F 0x06D8
+#define REG_BBPSF_CTRL_8197F 0x06DC
+#define REG_P2P_RX_BCN_NOA_8197F 0x06E0
+#define REG_ASSOCIATED_BFMER0_INFO_8197F 0x06E4
+#define REG_ASSOCIATED_BFMER1_INFO_8197F 0x06EC
+#define REG_TX_CSI_RPT_PARAM_BW20_8197F 0x06F4
+#define REG_TX_CSI_RPT_PARAM_BW40_8197F 0x06F8
+#define REG_TX_CSI_RPT_PARAM_BW80_8197F 0x06FC
+#define REG_BCN_PSR_RPT2_8197F 0x1600
+#define REG_BCN_PSR_RPT3_8197F 0x1604
+#define REG_BCN_PSR_RPT4_8197F 0x1608
+#define REG_A1_ADDR_MASK_8197F 0x160C
+#define REG_MACID2_8197F 0x1620
+#define REG_BSSID2_8197F 0x1628
+#define REG_MACID3_8197F 0x1630
+#define REG_BSSID3_8197F 0x1638
+#define REG_MACID4_8197F 0x1640
+#define REG_BSSID4_8197F 0x1648
+#define REG_NOA_REPORT_8197F 0x1650
+#define REG_PWRBIT_SETTING_8197F 0x1660
+#define REG_WMAC_MU_BF_OPTION_8197F 0x167C
+#define REG_WMAC_PAUSE_BB_CLR_TH_8197F 0x167D
+#define REG_WMAC_MU_ARB_8197F 0x167E
+#define REG_WMAC_MU_OPTION_8197F 0x167F
+#define REG_WMAC_MU_BF_CTL_8197F 0x1680
+#define REG_WMAC_MU_BFRPT_PARA_8197F 0x1682
+#define REG_WMAC_ASSOCIATED_MU_BFMEE2_8197F 0x1684
+#define REG_WMAC_ASSOCIATED_MU_BFMEE3_8197F 0x1686
+#define REG_WMAC_ASSOCIATED_MU_BFMEE4_8197F 0x1688
+#define REG_WMAC_ASSOCIATED_MU_BFMEE5_8197F 0x168A
+#define REG_WMAC_ASSOCIATED_MU_BFMEE6_8197F 0x168C
+#define REG_WMAC_ASSOCIATED_MU_BFMEE7_8197F 0x168E
+#define REG_TRANSMIT_ADDRSS_0_8197F 0x16A0
+#define REG_TRANSMIT_ADDRSS_1_8197F 0x16A8
+#define REG_TRANSMIT_ADDRSS_2_8197F 0x16B0
+#define REG_TRANSMIT_ADDRSS_3_8197F 0x16B8
+#define REG_TRANSMIT_ADDRSS_4_8197F 0x16C0
+#define REG_MACID1_8197F 0x0700
+#define REG_BSSID1_8197F 0x0708
+#define REG_BCN_PSR_RPT1_8197F 0x0710
+#define REG_ASSOCIATED_BFMEE_SEL_8197F 0x0714
+#define REG_SND_PTCL_CTRL_8197F 0x0718
+#define REG_RX_CSI_RPT_INFO_8197F 0x071C
+#define REG_NS_ARP_CTRL_8197F 0x0720
+#define REG_NS_ARP_INFO_8197F 0x0724
+#define REG_BEAMFORMING_INFO_NSARP_V1_8197F 0x0728
+#define REG_BEAMFORMING_INFO_NSARP_8197F 0x072C
+#define REG_WMAC_RTX_CTX_SUBTYPE_CFG_8197F 0x0750
+#define REG_WMAC_SWAES_CFG_8197F 0x0760
+#define REG_BT_COEX_V2_8197F 0x0762
+#define REG_BT_COEX_8197F 0x0764
+#define REG_WLAN_ACT_MASK_CTRL_8197F 0x0768
+#define REG_BT_COEX_ENHANCED_INTR_CTRL_8197F 0x076E
+#define REG_BT_ACT_STATISTICS_8197F 0x0770
+#define REG_BT_STATISTICS_CONTROL_REGISTER_8197F 0x0778
+#define REG_BT_STATUS_REPORT_REGISTER_8197F 0x077C
+#define REG_BT_INTERRUPT_CONTROL_REGISTER_8197F 0x0780
+#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8197F 0x0784
+#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8197F 0x0785
+#define REG_BT_INTERRUPT_STATUS_REGISTER_8197F 0x078F
+#define REG_BT_TDMA_TIME_REGISTER_8197F 0x0790
+#define REG_BT_ACT_REGISTER_8197F 0x0794
+#define REG_OBFF_CTRL_BASIC_8197F 0x0798
+#define REG_OBFF_CTRL2_TIMER_8197F 0x079C
+#define REG_LTR_CTRL_BASIC_8197F 0x07A0
+#define REG_LTR_CTRL2_TIMER_THRESHOLD_8197F 0x07A4
+#define REG_LTR_IDLE_LATENCY_V1_8197F 0x07A8
+#define REG_LTR_ACTIVE_LATENCY_V1_8197F 0x07AC
+#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_8197F 0x07B0
+#define REG_WMAC_PKTCNT_RWD_8197F 0x07B8
+#define REG_WMAC_PKTCNT_CTRL_8197F 0x07BC
+#define REG_IQ_DUMP_8197F 0x07C0
+#define REG_WMAC_FTM_CTL_8197F 0x07CC
+#define REG_IQ_DUMP_EXT_8197F 0x07CF
+#define REG_OFDM_CCK_LEN_MASK_8197F 0x07D0
+#define REG_RX_FILTER_FUNCTION_8197F 0x07DA
+#define REG_NDP_SIG_8197F 0x07E0
+#define REG_TXCMD_INFO_FOR_RSP_PKT_8197F 0x07E4
+#define REG_SEC_OPT_V2_8197F 0x07EC
+#define REG_RTS_ADDRESS_0_8197F 0x07F0
+#define REG_RTS_ADDRESS_1_8197F 0x07F8
+
+#endif
diff --git a/hal/halmac/halmac_reg_8814b.h b/hal/halmac/halmac_reg_8814b.h
new file mode 100644
index 0000000..9fb8ff5
--- /dev/null
+++ b/hal/halmac/halmac_reg_8814b.h
@@ -0,0 +1,1058 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef __INC_HALMAC_REG_8814B_H
+#define __INC_HALMAC_REG_8814B_H
+
+#define REG_SYS_ISO_CTRL_8814B 0x0000
+#define REG_SYS_FUNC_EN_8814B 0x0002
+#define REG_SYS_PW_CTRL_8814B 0x0004
+#define REG_SYS_CLK_CTRL_8814B 0x0008
+#define REG_SYS_EEPROM_CTRL_8814B 0x000A
+#define REG_EE_VPD_8814B 0x000C
+#define REG_SYS_SWR_CTRL1_8814B 0x0010
+#define REG_SYS_SWR_CTRL2_8814B 0x0014
+#define REG_SYS_SWR_CTRL3_8814B 0x0018
+#define REG_RSV_CTRL_8814B 0x001C
+#define REG_RF_CTRL_8814B 0x001F
+#define REG_AFE_LDO_CTRL_8814B 0x0020
+#define REG_AFE_CTRL1_8814B 0x0024
+#define REG_ANAPARSW_POW_MAC_8814B 0x0028
+#define REG_ANAPARLDO_POW_MAC_8814B 0x0029
+#define REG_ANAPAR_POW_MAC_8814B 0x002A
+#define REG_ANAPAR_POW_XTAL_8814B 0x002B
+#define REG_ANAPARLDO_MAC_8814B 0x002C
+#define REG_EFUSE_CTRL_8814B 0x0030
+#define REG_LDO_EFUSE_CTRL_8814B 0x0034
+#define REG_PWR_OPTION_CTRL_8814B 0x0038
+#define REG_CAL_TIMER_8814B 0x003C
+#define REG_ACLK_MON_8814B 0x003E
+#define REG_GPIO_MUXCFG_8814B 0x0040
+#define REG_GPIO_PIN_CTRL_8814B 0x0044
+#define REG_GPIO_INTM_8814B 0x0048
+#define REG_LED_CFG_8814B 0x004C
+#define REG_FSIMR_8814B 0x0050
+#define REG_FSISR_8814B 0x0054
+#define REG_HSIMR_8814B 0x0058
+#define REG_HSISR_8814B 0x005C
+#define REG_GPIO_EXT_CTRL_8814B 0x0060
+#define REG_PAD_CTRL1_8814B 0x0064
+#define REG_WL_BT_PWR_CTRL_8814B 0x0068
+#define REG_SDM_DEBUG_8814B 0x006C
+#define REG_SYS_SDIO_CTRL_8814B 0x0070
+#define REG_HCI_OPT_CTRL_8814B 0x0074
+#define REG_AFE_CTRL4_8814B 0x0078
+#define REG_LDO_SWR_CTRL_8814B 0x007C
+#define REG_MCUFW_CTRL_8814B 0x0080
+#define REG_MCU_TST_CFG_8814B 0x0084
+#define REG_HMEBOX_E0_E1_8814B 0x0088
+#define REG_HMEBOX_E2_E3_8814B 0x008C
+#define REG_WLLPS_CTRL_8814B 0x0090
+#define REG_AFE_CTRL5_8814B 0x0094
+#define REG_GPIO_DEBOUNCE_CTRL_8814B 0x0098
+#define REG_RPWM2_8814B 0x009C
+#define REG_SYSON_FSM_MON_8814B 0x00A0
+#define REG_AFE_CTRL6_8814B 0x00A4
+#define REG_PMC_DBG_CTRL1_8814B 0x00A8
+#define REG_AFE_CTRL7_8814B 0x00AC
+#define REG_HIMR0_8814B 0x00B0
+#define REG_HISR0_8814B 0x00B4
+#define REG_HIMR1_8814B 0x00B8
+#define REG_HISR1_8814B 0x00BC
+#define REG_DBG_PORT_SEL_8814B 0x00C0
+#define REG_PAD_CTRL2_8814B 0x00C4
+#define REG_PMC_DBG_CTRL2_8814B 0x00CC
+#define REG_MEM_CTRL_8814B 0x00D8
+#define REG_SYN_RFC_CTRL_8814B 0x00DC
+#define REG_USB_SIE_INTF_8814B 0x00E0
+#define REG_PCIE_MIO_INTF_8814B 0x00E4
+#define REG_PCIE_MIO_INTD_8814B 0x00E8
+#define REG_WLRF1_8814B 0x00EC
+#define REG_SYS_CFG1_8814B 0x00F0
+#define REG_SYS_STATUS1_8814B 0x00F4
+#define REG_SYS_STATUS2_8814B 0x00F8
+#define REG_SYS_CFG2_8814B 0x00FC
+#define REG_ANAPARSW_MAC_0_8814B 0x1010
+#define REG_ANAPARSW_MAC_1_8814B 0x1014
+#define REG_ANAPAR_MAC_0_8814B 0x1018
+#define REG_ANAPAR_MAC_1_8814B 0x101C
+#define REG_ANAPAR_MAC_2_8814B 0x1020
+#define REG_ANAPAR_MAC_3_8814B 0x1024
+#define REG_ANAPAR_MAC_4_8814B 0x1028
+#define REG_ANAPAR_MAC_5_8814B 0x102C
+#define REG_ANAPAR_MAC_6_8814B 0x1030
+#define REG_ANAPAR_MAC_7_8814B 0x1034
+#define REG_ANAPAR_MAC_8_8814B 0x1038
+#define REG_ANAPAR_XTAL_0_8814B 0x1040
+#define REG_ANAPAR_XTAL_1_8814B 0x1044
+#define REG_ANAPAR_XTAL_2_8814B 0x1048
+#define REG_ANAPAR_XTAL_AAC_8814B 0x104C
+#define REG_ANAPAR_XTAL_R_ONLY_8814B 0x1050
+#define REG_CPHY_LDO_8814B 0x1054
+#define REG_CPHY_BG_8814B 0x1058
+#define REG_HIMR_4_8814B 0x1060
+#define REG_HISR_4_8814B 0x1064
+#define REG_HIMR_5_8814B 0x1068
+#define REG_HISR_5_8814B 0x106C
+#define REG_SYS_CFG5_8814B 0x1070
+#define REG_HIMR_6_8814B 0x1078
+#define REG_HISR_6_8814B 0x107C
+#define REG_CPU_DMEM_CON_8814B 0x1080
+#define REG_BOOT_REASON_8814B 0x1088
+#define REG_DATA_CPU_CTL0_8814B 0x1090
+#define REG_DATA_CPU_CTL1_8814B 0x1094
+#define REG_TXDMA_STOP_HIMR_8814B 0x1098
+#define REG_TXDMA_STOP_HISR_8814B 0x109C
+#define REG_TXDMA_START_HIMR_8814B 0x10A0
+#define REG_TXDMA_START_HISR_8814B 0x10A4
+#define REG_NFCPAD_CTRL_8814B 0x10A8
+#define REG_HIMR2_8814B 0x10B0
+#define REG_HISR2_8814B 0x10B4
+#define REG_HIMR3_8814B 0x10B8
+#define REG_HISR3_8814B 0x10BC
+#define REG_SW_MDIO_8814B 0x10C0
+#define REG_HIMR_7_8814B 0x10C8
+#define REG_HISR_7_8814B 0x10CC
+#define REG_H2C_PKT_READADDR_8814B 0x10D0
+#define REG_H2C_PKT_WRITEADDR_8814B 0x10D4
+#define REG_MEM_PWR_CRTL_8814B 0x10D8
+#define REG_FW_DRV_HANDSHAKE_8814B 0x10DC
+#define REG_FW_DBG0_8814B 0x10E0
+#define REG_FW_DBG1_8814B 0x10E4
+#define REG_FW_DBG2_8814B 0x10E8
+#define REG_FW_DBG3_8814B 0x10EC
+#define REG_FW_DBG4_8814B 0x10F0
+#define REG_FW_DBG5_8814B 0x10F4
+#define REG_FW_DBG6_8814B 0x10F8
+#define REG_FW_DBG7_8814B 0x10FC
+#define REG_CR_8814B 0x0100
+#define REG_PG_SIZE_8814B 0x0104
+#define REG_PKT_BUFF_ACCESS_CTRL_8814B 0x0106
+#define REG_TSF_CLK_STATE_8814B 0x0108
+#define REG_TXDMA_PQ_MAP_8814B 0x010C
+#define REG_TRXFF_BNDY_8814B 0x0114
+#define REG_PTA_I2C_MBOX_8814B 0x0118
+#define REG_RXFF_BNDY_8814B 0x011C
+#define REG_FE1IMR_8814B 0x0120
+#define REG_FE1ISR_8814B 0x0124
+#define REG_CPWM_8814B 0x012C
+#define REG_FWIMR_8814B 0x0130
+#define REG_FWISR_8814B 0x0134
+#define REG_FTIMR_8814B 0x0138
+#define REG_FTISR_8814B 0x013C
+#define REG_PKTBUF_DBG_CTRL_8814B 0x0140
+#define REG_PKTBUF_DBG_DATA_L_8814B 0x0144
+#define REG_PKTBUF_DBG_DATA_H_8814B 0x0148
+#define REG_CPWM2_8814B 0x014C
+#define REG_TC0_CTRL_8814B 0x0150
+#define REG_TC1_CTRL_8814B 0x0154
+#define REG_TC2_CTRL_8814B 0x0158
+#define REG_TC3_CTRL_8814B 0x015C
+#define REG_TC4_CTRL_8814B 0x0160
+#define REG_TCUNIT_BASE_8814B 0x0164
+#define REG_TC5_CTRL_8814B 0x0168
+#define REG_TC6_CTRL_8814B 0x016C
+#define REG_AES_DECRPT_DATA_8814B 0x0180
+#define REG_AES_DECRPT_CFG_8814B 0x0184
+#define REG_HIOE_CTRL_8814B 0x0188
+#define REG_HIOE_CFG_FILE_8814B 0x018C
+#define REG_TMETER_8814B 0x0190
+#define REG_OSC_32K_CTRL_8814B 0x0194
+#define REG_32K_CAL_REG1_8814B 0x0198
+#define REG_C2HEVT_8814B 0x01A0
+#define REG_C2HEVT_1_8814B 0x01A4
+#define REG_C2HEVT_2_8814B 0x01A8
+#define REG_C2HEVT_3_8814B 0x01AC
+#define REG_RXDESC_BUFF_RPTR_8814B 0x01B0
+#define REG_RXDESC_BUFF_WPTR_8814B 0x01B4
+#define REG_SW_DEFINED_PAGE1_8814B 0x01B8
+#define REG_SW_DEFINED_PAGE2_8814B 0x01BC
+#define REG_MCUTST_I_8814B 0x01C0
+#define REG_MCUTST_II_8814B 0x01C4
+#define REG_FMETHR_8814B 0x01C8
+#define REG_HMETFR_8814B 0x01CC
+#define REG_HMEBOX0_8814B 0x01D0
+#define REG_HMEBOX1_8814B 0x01D4
+#define REG_HMEBOX2_8814B 0x01D8
+#define REG_HMEBOX3_8814B 0x01DC
+#define REG_RXDESC_BUFF_BNDY_8814B 0x01E0
+#define REG_BB_ACCESS_CTRL_8814B 0x01E8
+#define REG_BB_ACCESS_DATA_8814B 0x01EC
+#define REG_HMEBOX_E0_8814B 0x01F0
+#define REG_HMEBOX_E1_8814B 0x01F4
+#define REG_HMEBOX_E2_8814B 0x01F8
+#define REG_HMEBOX_E3_8814B 0x01FC
+#define REG_CR_EXT_8814B 0x1100
+#define REG_TC9_CTRL_8814B 0x1104
+#define REG_TC10_CTRL_8814B 0x1108
+#define REG_TC11_CTRL_8814B 0x110C
+#define REG_TC12_CTRL_8814B 0x1110
+#define REG_FWFF_8814B 0x1114
+#define REG_RXFF_PTR_V1_8814B 0x1118
+#define REG_RXFF_WTR_V1_8814B 0x111C
+#define REG_FE2IMR_8814B 0x1120
+#define REG_FE2ISR_8814B 0x1124
+#define REG_FE3IMR_8814B 0x1128
+#define REG_FE3ISR_8814B 0x112C
+#define REG_FE4IMR_8814B 0x1130
+#define REG_FE4ISR_8814B 0x1134
+#define REG_FT1IMR_8814B 0x1138
+#define REG_FT1ISR_8814B 0x113C
+#define REG_SPWR0_8814B 0x1140
+#define REG_SPWR1_8814B 0x1144
+#define REG_SPWR2_8814B 0x1148
+#define REG_SPWR3_8814B 0x114C
+#define REG_POWSEQ_8814B 0x1150
+#define REG_TC7_CTRL_V1_8814B 0x1158
+#define REG_TC8_CTRL_V1_8814B 0x115C
+#define REG_RX_BCN_TBTT_ITVL0_8814B 0x1160
+#define REG_RX_BCN_TBTT_ITVL1_8814B 0x1164
+#define REG_FWIMR1_8814B 0x1168
+#define REG_FWISR1_8814B 0x116C
+#define REG_FWIMR2_8814B 0x1170
+#define REG_FWISR2_8814B 0x1174
+#define REG_FWIMR3_8814B 0x1178
+#define REG_FWISR3_8814B 0x117C
+#define REG_SPEED_SENSOR_8814B 0x1180
+#define REG_SPEED_SENSOR1_8814B 0x1184
+#define REG_SPEED_SENSOR2_8814B 0x1188
+#define REG_SPEED_SENSOR3_8814B 0x118C
+#define REG_SPEED_SENSOR4_8814B 0x1190
+#define REG_SPEED_SENSOR5_8814B 0x1194
+#define REG_RXPKTBUF_1_MAX_ADDR_8814B 0x1198
+#define REG_RXFWBUF_1_MAX_ADDR_8814B 0x119C
+#define REG_IO_WRAP_ERR_FLAG_V1_8814B 0x11A0
+#define REG_RXPKTBUF_1_READ_8814B 0x11A4
+#define REG_RXPKTBUF_1_WRITE_8814B 0x11A8
+#define REG_BUFF_DBGUG_8814B 0x11AC
+#define REG_RFE_CTRL_PAD_E2_8814B 0x11B0
+#define REG_RFE_CTRL_PAD_SR_8814B 0x11B4
+#define REG_H2C_PRIORITY_SEL_8814B 0x11C0
+#define REG_COUNTER_CTRL_8814B 0x11C4
+#define REG_COUNTER_THRESHOLD_8814B 0x11C8
+#define REG_COUNTER_SET_8814B 0x11CC
+#define REG_COUNTER_OVERFLOW_8814B 0x11D0
+#define REG_TXDMA_LEN_THRESHOLD_8814B 0x11D4
+#define REG_RXDMA_LEN_THRESHOLD_8814B 0x11D8
+#define REG_PCIE_EXEC_TIME_THRESHOLD_8814B 0x11DC
+#define REG_FT2IMR_8814B 0x11E0
+#define REG_FT2ISR_8814B 0x11E4
+#define REG_MSG2_8814B 0x11F0
+#define REG_MSG3_8814B 0x11F4
+#define REG_MSG4_8814B 0x11F8
+#define REG_MSG5_8814B 0x11FC
+#define REG_BIST_RSTN0_8814B 0x2100
+#define REG_BIST_RSTN2_8814B 0x2108
+#define REG_BIST_MODE_NRML0_8814B 0x2110
+#define REG_BIST_MODE_NRML1_8814B 0x2114
+#define REG_BIST_MODE_NRML2_8814B 0x2118
+#define REG_BIST_MODE_NRML3_8814B 0x211C
+#define REG_BIST_DONE_NRML_MAC_8814B 0x2150
+#define REG_BIST_DONE_NRML1_8814B 0x2158
+#define REG_BIST_DONE_DRF_MAC_8814B 0x2160
+#define REG_BIST_DONE_DRF_8814B 0x2164
+#define REG_BIST_DONE_DRF1_8814B 0x2168
+#define REG_BIST_FAIL_NRML_MAC_8814B 0x2170
+#define REG_BIST_FAIL_NRML_8814B 0x2174
+#define REG_BIST_FAIL_NRML1_8814B 0x2178
+#define REG_BIST_FAIL_NRML_MAC_V1_8814B 0x2180
+#define REG_BIST_FAIL_NRML_V1_8814B 0x2184
+#define REG_BIST_FAIL_NRML1_V1_8814B 0x2188
+#define REG_BIST_MISR_DATAOUT_8814B 0x2190
+#define REG_BIST_MISR_DATAOUT1_8814B 0x2194
+#define REG_BIST_MISR_DATAOUT_CPU_8814B 0x2198
+#define REG_BIST_MISR_DATAOUT_CPU1_8814B 0x219C
+#define REG_BIST_MISR_DATAOUT_CPU2_8814B 0x21A0
+#define REG_BIST_MISR_DATOUT_CPU3_8814B 0x21A4
+#define REG_BCN_CTRL_0_8814B 0x0200
+#define REG_BCN_CTRL_1_8814B 0x0204
+#define REG_AUTO_LLT_V1_8814B 0x0208
+#define REG_TXDMA_OFFSET_CHK_8814B 0x020C
+#define REG_TXDMA_STATUS_8814B 0x0210
+#define REG_TX_DMA_DBG_8814B 0x0214
+#define REG_DMA_RQPN_INFO_PUB_8814B 0x0218
+#define REG_RQPN_CTRL_2_V1_8814B 0x021C
+#define REG_BCN_CTRL_2_8814B 0x0220
+#define REG_TXPKTNUM_0_8814B 0x0230
+#define REG_TXPKTNUM_1_8814B 0x0234
+#define REG_TXPKTNUM_2_8814B 0x0238
+#define REG_TXPKTNUM_3_8814B 0x023C
+#define REG_TX_AGG_ALIGN_8814B 0x0240
+#define REG_H2C_HEAD_8814B 0x0244
+#define REG_H2C_TAIL_8814B 0x0248
+#define REG_H2C_READ_ADDR_8814B 0x024C
+#define REG_H2C_WR_ADDR_8814B 0x0250
+#define REG_H2C_INFO_8814B 0x0254
+#define REG_DMA_OQT_0_8814B 0x0260
+#define REG_DMA_OQT_1_8814B 0x0264
+#define REG_RXDMA_AGG_PG_TH_8814B 0x0280
+#define REG_RXDMA_CTRL_8814B 0x0284
+#define REG_RXDMA_STATUS_8814B 0x0288
+#define REG_RXDMA_DPR_8814B 0x028C
+#define REG_RXDMA_MODE_8814B 0x0290
+#define REG_C2H_PKT_8814B 0x0294
+#define REG_FWFF_C2H_8814B 0x0298
+#define REG_FWFF_CTRL_8814B 0x029C
+#define REG_FWFF_PKT_INFO_8814B 0x02A0
+#define REG_FWFF_PKT_INFO2_8814B 0x02A4
+#define REG_RXPKTNUM_8814B 0x02B0
+#define REG_RXPKTNUM_TH_8814B 0x02B4
+#define REG_FW_UPD_RXDES_RDPTR_8814B 0x02B8
+#define REG_DDMA_CH0SA_8814B 0x1200
+#define REG_DDMA_CH0DA_8814B 0x1204
+#define REG_DDMA_CH0CTRL_8814B 0x1208
+#define REG_DDMA_CH1SA_8814B 0x1210
+#define REG_DDMA_CH1DA_8814B 0x1214
+#define REG_DDMA_CH1CTRL_8814B 0x1218
+#define REG_DDMA_CH2SA_8814B 0x1220
+#define REG_DDMA_CH2DA_8814B 0x1224
+#define REG_DDMA_CH2CTRL_8814B 0x1228
+#define REG_DDMA_CH3SA_8814B 0x1230
+#define REG_DDMA_CH3DA_8814B 0x1234
+#define REG_DDMA_CH3CTRL_8814B 0x1238
+#define REG_DDMA_CH4SA_8814B 0x1240
+#define REG_DDMA_CH4DA_8814B 0x1244
+#define REG_DDMA_CH4CTRL_8814B 0x1248
+#define REG_DDMA_CH5SA_8814B 0x1250
+#define REG_DDMA_CH5DA_8814B 0x1254
+#define REG_DDMA_CH5CTRL_8814B 0x1258
+#define REG_DDMA_INT_MSK_8814B 0x12E0
+#define REG_DDMA_CHSTATUS_8814B 0x12E8
+#define REG_DDMA_CHKSUM_8814B 0x12F0
+#define REG_DDMA_MONITOR_8814B 0x12FC
+#define REG_DMA_RQPN_INFO_0_8814B 0x2200
+#define REG_DMA_RQPN_INFO_1_8814B 0x2204
+#define REG_DMA_RQPN_INFO_2_8814B 0x2208
+#define REG_DMA_RQPN_INFO_3_8814B 0x220C
+#define REG_DMA_RQPN_INFO_4_8814B 0x2210
+#define REG_DMA_RQPN_INFO_5_8814B 0x2214
+#define REG_DMA_RQPN_INFO_6_8814B 0x2218
+#define REG_DMA_RQPN_INFO_7_8814B 0x221C
+#define REG_DMA_RQPN_INFO_8_8814B 0x2220
+#define REG_DMA_RQPN_INFO_9_8814B 0x2224
+#define REG_DMA_RQPN_INFO_10_8814B 0x2228
+#define REG_DMA_RQPN_INFO_11_8814B 0x222C
+#define REG_DMA_RQPN_INFO_12_8814B 0x2230
+#define REG_DMA_RQPN_INFO_13_8814B 0x2234
+#define REG_DMA_RQPN_INFO_14_8814B 0x2238
+#define REG_DMA_RQPN_INFO_15_8814B 0x223C
+#define REG_DMA_RQPN_INFO_16_8814B 0x2240
+#define REG_HWAMSDU_CTL1_8814B 0x2250
+#define REG_HWAMSDU_CTL2_8814B 0x2254
+#define REG_TXPAGE_INT_CTRL_0_8814B 0x3200
+#define REG_TXPAGE_INT_CTRL_1_8814B 0x3204
+#define REG_TXPAGE_INT_CTRL_2_8814B 0x3208
+#define REG_TXPAGE_INT_CTRL_3_8814B 0x320C
+#define REG_TXPAGE_INT_CTRL_4_8814B 0x3210
+#define REG_TXPAGE_INT_CTRL_5_8814B 0x3214
+#define REG_TXPAGE_INT_CTRL_6_8814B 0x3218
+#define REG_TXPAGE_INT_CTRL_7_8814B 0x321C
+#define REG_TXPAGE_INT_CTRL_8_8814B 0x3220
+#define REG_TXPAGE_INT_CTRL_9_8814B 0x3224
+#define REG_TXPAGE_INT_CTRL_10_8814B 0x3228
+#define REG_TXPAGE_INT_CTRL_11_8814B 0x322C
+#define REG_TXPAGE_INT_CTRL_12_8814B 0x3230
+#define REG_TXPAGE_INT_CTRL_13_8814B 0x3234
+#define REG_TXPAGE_INT_CTRL_14_8814B 0x3238
+#define REG_TXPAGE_INT_CTRL_15_8814B 0x323C
+#define REG_TXPAGE_INT_CTRL_16_8814B 0x3240
+#define REG_PCIE_CTRL_8814B 0x0300
+#define REG_ACH_CTRL_8814B 0x0304
+#define REG_HIQ_CTRL_8814B 0x0308
+#define REG_INT_MIG_V1_8814B 0x030C
+#define REG_P0MGQ_TXBD_DESA_L_8814B 0x0310
+#define REG_P0MGQ_TXBD_DESA_H_8814B 0x0314
+#define REG_ACH0_TXBD_DESA_L_8814B 0x0318
+#define REG_ACH0_TXBD_DESA_H_8814B 0x031C
+#define REG_ACH1_TXBD_DESA_L_8814B 0x0320
+#define REG_ACH1_TXBD_DESA_H_8814B 0x0324
+#define REG_ACH2_TXBD_DESA_L_8814B 0x0328
+#define REG_ACH2_TXBD_DESA_H_8814B 0x032C
+#define REG_ACH3_TXBD_DESA_L_8814B 0x0330
+#define REG_ACH3_TXBD_DESA_H_8814B 0x0334
+#define REG_P0RXQ_RXBD_DESA_L_8814B 0x0338
+#define REG_P0RXQ_RXBD_DESA_H_8814B 0x033C
+#define REG_P0BCNQ_TXBD_DESA_L_8814B 0x0340
+#define REG_P0BCNQ_TXBD_DESA_H_8814B 0x0344
+#define REG_FWCMDQ_TXBD_DESA_L_8814B 0x0348
+#define REG_FWCMDQ_TXBD_DESA_H_8814B 0x034C
+#define REG_PCIE_HRPWM1_HCPWM1_DCPU_8814B 0x0354
+#define REG_P0_MPRT_BCNQ_TXBD_DESA_L_8814B 0x0358
+#define REG_P0_MPRT_BCNQ_TXBD_DESA_H_8814B 0x035C
+#define REG_P0_MPRT_BCNQ_TXRXBD_NUM_8814B 0x036C
+#define REG_BD_RWPTR_CLR2_8814B 0x0370
+#define REG_BD_RWPTR_CLR3_8814B 0x0374
+#define REG_P0MGQ_RXQ_TXRXBD_NUM_8814B 0x0378
+#define REG_CHNL_DMA_CFG_8814B 0x037C
+#define REG_FWCMDQ_TXBD_NUM_8814B 0x0380
+#define REG_ACH0_ACH1_TXBD_NUM_8814B 0x0384
+#define REG_ACH2_ACH3_TXBD_NUM_8814B 0x0388
+#define REG_P0HI0Q_HI1Q_TXBD_NUM_8814B 0x038C
+#define REG_P0HI2Q_HI3Q_TXBD_NUM_8814B 0x0390
+#define REG_P0HI4Q_HI5Q_TXBD_NUM_8814B 0x0394
+#define REG_P0HI6Q_HI7Q_TXBD_NUM_8814B 0x0398
+#define REG_BD_RWPTR_CLR1_8814B 0x039C
+#define REG_TSFTIMER_HCI_8814B 0x039C
+#define REG_ACH0_TXBD_IDX_8814B 0x03A0
+#define REG_ACH1_TXBD_IDX_8814B 0x03A4
+#define REG_ACH2_TXBD_IDX_8814B 0x03A8
+#define REG_ACH3_TXBD_IDX_8814B 0x03AC
+#define REG_P0MGQ_TXBD_IDX_8814B 0x03B0
+#define REG_P0RXQ_RXBD_IDX_8814B 0x03B4
+#define REG_P0HI0Q_TXBD_IDX_8814B 0x03B8
+#define REG_P0HI1Q_TXBD_IDX_8814B 0x03BC
+#define REG_P0HI2Q_TXBD_IDX_8814B 0x03C0
+#define REG_P0HI3Q_TXBD_IDX_8814B 0x03C4
+#define REG_P0HI4Q_TXBD_IDX_8814B 0x03C8
+#define REG_P0HI5Q_TXBD_IDX_8814B 0x03CC
+#define REG_P0HI6Q_TXBD_IDX_8814B 0x03D0
+#define REG_P0HI7Q_TXBD_IDX_8814B 0x03D4
+#define REG_DBGSEL_PCIE_HRPWM1_HCPWM1_V1_8814B 0x03D8
+#define REG_PCIE_HRPWM2_HCPWM2_V1_8814B 0x03DC
+#define REG_PCIE_H2C_MSG_V1_8814B 0x03E0
+#define REG_PCIE_C2H_MSG_V1_8814B 0x03E4
+#define REG_DBI_WDATA_V1_8814B 0x03E8
+#define REG_DBI_RDATA_V1_8814B 0x03EC
+#define REG_DBI_FLAG_V1_8814B 0x03F0
+#define REG_MDIO_V1_8814B 0x03F4
+#define REG_PCIE_MIX_CFG_8814B 0x03F8
+#define REG_HCI_MIX_CFG_8814B 0x03FC
+#define REG_STC_INT_CS_8814B 0x1300
+#define REG_ST_INT_CFG_8814B 0x1304
+#define REG_ACH4_ACH5_TXBD_NUM_8814B 0x130C
+#define REG_FWCMDQ_TXBD_IDX_8814B 0x1318
+#define REG_P0HI8Q_TXBD_IDX_8814B 0x131C
+#define REG_H2CQ_TXBD_DESA_L_8814B 0x1320
+#define REG_H2CQ_TXBD_DESA_H_8814B 0x1324
+#define REG_H2CQ_TXBD_NUM_8814B 0x1328
+#define REG_H2CQ_TXBD_IDX_8814B 0x132C
+#define REG_H2CQ_CSR_8814B 0x1330
+#define REG_P0HI9Q_TXBD_IDX_8814B 0x1334
+#define REG_P0HI10Q_TXBD_IDX_8814B 0x1338
+#define REG_P0HI11Q_TXBD_IDX_8814B 0x133C
+#define REG_P0HI12Q_TXBD_IDX_8814B 0x1340
+#define REG_P0HI13Q_TXBD_IDX_8814B 0x1344
+#define REG_P0HI14Q_TXBD_IDX_8814B 0x1348
+#define REG_P0HI15Q_TXBD_IDX_8814B 0x134C
+#define REG_CHANGE_PCIE_SPEED_8814B 0x1350
+#define REG_DEBUG_STATE1_8814B 0x1354
+#define REG_DEBUG_STATE2_8814B 0x1358
+#define REG_DEBUG_STATE3_8814B 0x135C
+#define REG_ACH5_TXBD_DESA_L_8814B 0x1360
+#define REG_ACH5_TXBD_DESA_H_8814B 0x1364
+#define REG_ACH6_TXBD_DESA_L_8814B 0x1368
+#define REG_ACH6_TXBD_DESA_H_8814B 0x136C
+#define REG_ACH7_TXBD_DESA_L_8814B 0x1370
+#define REG_ACH7_TXBD_DESA_H_8814B 0x1374
+#define REG_ACH8_TXBD_DESA_L_8814B 0x1378
+#define REG_ACH8_TXBD_DESA_H_8814B 0x137C
+#define REG_ACH9_TXBD_DESA_L_8814B 0x1380
+#define REG_ACH9_TXBD_DESA_H_8814B 0x1384
+#define REG_ACH10_TXBD_DESA_L_8814B 0x1388
+#define REG_ACH10_TXBD_DESA_H_8814B 0x138C
+#define REG_ACH11_TXBD_DESA_L_8814B 0x1390
+#define REG_ACH11_TXBD_DESA_H_8814B 0x1394
+#define REG_ACH12_TXBD_DESA_L_8814B 0x1398
+#define REG_ACH12_TXBD_DESA_H_8814B 0x139C
+#define REG_ACH13_TXBD_DESA_L_8814B 0x13A0
+#define REG_ACH13_TXBD_DESA_H_8814B 0x13A4
+#define REG_HI0Q_TXBD_DESA_L_8814B 0x13A8
+#define REG_HI0Q_TXBD_DESA_H_8814B 0x13AC
+#define REG_HI1Q_TXBD_DESA_L_8814B 0x13B0
+#define REG_HI1Q_TXBD_DESA_H_8814B 0x13B4
+#define REG_HI2Q_TXBD_DESA_L_8814B 0x13B8
+#define REG_HI2Q_TXBD_DESA_H_8814B 0x13BC
+#define REG_HI3Q_TXBD_DESA_L_8814B 0x13C0
+#define REG_HI3Q_TXBD_DESA_H_8814B 0x13C4
+#define REG_HI4Q_TXBD_DESA_L_8814B 0x13C8
+#define REG_HI4Q_TXBD_DESA_H_8814B 0x13CC
+#define REG_HI5Q_TXBD_DESA_L_8814B 0x13D0
+#define REG_HI5Q_TXBD_DESA_H_8814B 0x13D4
+#define REG_HI6Q_TXBD_DESA_L_8814B 0x13D8
+#define REG_HI6Q_TXBD_DESA_H_8814B 0x13DC
+#define REG_HI7Q_TXBD_DESA_L_8814B 0x13E0
+#define REG_HI7Q_TXBD_DESA_H_8814B 0x13E4
+#define REG_ACH8_ACH9_TXBD_NUM_8814B 0x13E8
+#define REG_ACH10_ACH11_TXBD_NUM_8814B 0x13EC
+#define REG_ACH12_ACH13_TXBD_NUM_8814B 0x13F0
+#define REG_OLD_DEHANG_8814B 0x13F4
+#define REG_ACH4_TXBD_DESA_L_8814B 0x13F8
+#define REG_ACH4_TXBD_DESA_H_8814B 0x13FC
+#define REG_HI8Q_TXBD_DESA_L_8814B 0x2300
+#define REG_HI8Q_TXBD_DESA_H_8814B 0x2304
+#define REG_HI9Q_TXBD_DESA_L_8814B 0x2308
+#define REG_HI9Q_TXBD_DESA_H_8814B 0x230C
+#define REG_HI10Q_TXBD_DESA_L_8814B 0x2310
+#define REG_HI10Q_TXBD_DESA_H_8814B 0x2314
+#define REG_HI11Q_TXBD_DESA_L_8814B 0x2318
+#define REG_HI11Q_TXBD_DESA_H_8814B 0x231C
+#define REG_HI12Q_TXBD_DESA_L_8814B 0x2320
+#define REG_HI12Q_TXBD_DESA_H_8814B 0x2324
+#define REG_HI13Q_TXBD_DESA_L_8814B 0x2328
+#define REG_HI13Q_TXBD_DESA_H_8814B 0x232C
+#define REG_HI14Q_TXBD_DESA_L_8814B 0x2330
+#define REG_HI14Q_TXBD_DESA_H_8814B 0x2334
+#define REG_HI15Q_TXBD_DESA_L_8814B 0x2338
+#define REG_HI15Q_TXBD_DESA_H_8814B 0x233C
+#define REG_HI16Q_TXBD_DESA_L_8814B 0x2340
+#define REG_HI16Q_TXBD_DESA_H_8814B 0x2344
+#define REG_HI17Q_TXBD_DESA_L_8814B 0x2348
+#define REG_HI17Q_TXBD_DESA_H_8814B 0x234C
+#define REG_HI18Q_TXBD_DESA_L_8814B 0x2350
+#define REG_HI18Q_TXBD_DESA_H_8814B 0x2354
+#define REG_HI19Q_TXBD_DESA_L_8814B 0x2358
+#define REG_HI19Q_TXBD_DESA_H_8814B 0x235C
+#define REG_BD_RWPTR_CLR6_8814B 0x2364
+#define REG_P0HI16Q_TXBD_IDX_8814B 0x2370
+#define REG_P0HI17Q_TXBD_IDX_8814B 0x2374
+#define REG_P0HI18Q_TXBD_IDX_8814B 0x2378
+#define REG_P0HI19Q_TXBD_IDX_8814B 0x237C
+#define REG_P0HI16Q_HI17Q_TXBD_NUM_8814B 0x2380
+#define REG_P0HI18Q_HI19Q_TXBD_NUM_8814B 0x2384
+#define REG_PCIE_HISR0_8814B 0x23B4
+#define REG_PCIE_HISR1_8814B 0x23BC
+#define REG_P0HI8Q_HI9Q_TXBD_NUM_8814B 0x23C0
+#define REG_P0HI10Q_HI11Q_TXBD_NUM_8814B 0x23C4
+#define REG_P0HI12Q_HI13Q_TXBD_NUM_8814B 0x23C8
+#define REG_P0HI14Q_HI15Q_TXBD_NUM_8814B 0x23CC
+#define REG_ACH6_ACH7_TXBD_NUM_8814B 0x23F0
+#define REG_ACH4_TXBD_IDX_8814B 0x3340
+#define REG_ACH5_TXBD_IDX_8814B 0x3344
+#define REG_ACH6_TXBD_IDX_8814B 0x3348
+#define REG_ACH7_TXBD_IDX_8814B 0x334C
+#define REG_ACH8_TXBD_IDX_8814B 0x3350
+#define REG_ACH9_TXBD_IDX_8814B 0x3354
+#define REG_ACH10_TXBD_IDX_8814B 0x3358
+#define REG_ACH11_TXBD_IDX_8814B 0x335C
+#define REG_ACH12_TXBD_IDX_8814B 0x3360
+#define REG_ACH13_TXBD_IDX_8814B 0x3364
+#define REG_AC_CHANNEL0_WEIGHT_8814B 0x3368
+#define REG_AC_CHANNEL1_WEIGHT_8814B 0x3369
+#define REG_AC_CHANNEL2_WEIGHT_8814B 0x336A
+#define REG_AC_CHANNEL3_WEIGHT_8814B 0x336B
+#define REG_AC_CHANNEL4_WEIGHT_8814B 0x336C
+#define REG_AC_CHANNEL5_WEIGHT_8814B 0x336D
+#define REG_AC_CHANNEL6_WEIGHT_8814B 0x336E
+#define REG_AC_CHANNEL7_WEIGHT_8814B 0x336F
+#define REG_AC_CHANNEL8_WEIGHT_8814B 0x3370
+#define REG_AC_CHANNEL9_WEIGHT_8814B 0x3371
+#define REG_AC_CHANNEL10_WEIGHT_8814B 0x3372
+#define REG_AC_CHANNEL11_WEIGHT_8814B 0x3373
+#define REG_AC_CHANNEL12_WEIGHT_8814B 0x3374
+#define REG_AC_CHANNEL13_WEIGHT_8814B 0x3375
+#define REG_PCIE_HISR2_8814B 0x33B4
+#define REG_PCIE_HISR3_8814B 0x33BC
+#define REG_QUEUELIST_INFO0_8814B 0x0400
+#define REG_QUEUELIST_INFO1_8814B 0x0404
+#define REG_QUEUELIST_INFO2_8814B 0x0408
+#define REG_QUEUELIST_INFO3_8814B 0x040C
+#define REG_QUEUELIST_INFO_EMPTY_8814B 0x0410
+#define REG_QUEUELIST_ACQ_EN_8814B 0x0414
+#define REG_BCNQ_BDNY_V2_8814B 0x0418
+#define REG_CPU_MGQ_INFO_8814B 0x041C
+#define REG_FWHW_TXQ_CTRL_8814B 0x0420
+#define REG_DATAFB_SEL_8814B 0x0423
+#define REG_TXBDNY_8814B 0x0424
+#define REG_LIFETIME_EN_8814B 0x0426
+#define REG_SPEC_SIFS_8814B 0x0428
+#define REG_RETRY_LIMIT_8814B 0x042A
+#define REG_TXBF_CTRL_8814B 0x042C
+#define REG_DARFRC_8814B 0x0430
+#define REG_DARFRCH_8814B 0x0434
+#define REG_RARFRC_8814B 0x0438
+#define REG_RARFRCH_8814B 0x043C
+#define REG_RRSR_8814B 0x0440
+#define REG_ARFR0_8814B 0x0444
+#define REG_ARFRH0_8814B 0x0448
+#define REG_REG_ARFR_WT0_8814B 0x044C
+#define REG_REG_ARFR_WT1_8814B 0x0450
+#define REG_CCK_CHECK_8814B 0x0454
+#define REG_AMPDU_MAX_TIME_V1_8814B 0x0455
+#define REG_TAB_SEL_8814B 0x0456
+#define REG_BCN_INVALID_CTRL_8814B 0x0457
+#define REG_AMPDU_MAX_LENGTH_HT_8814B 0x0458
+#define REG_NDPA_RATE_8814B 0x045D
+#define REG_TX_HANG_CTRL_8814B 0x045E
+#define REG_NDPA_OPT_CTRL_8814B 0x045F
+#define REG_AMPDU_MAX_LENGTH_VHT_8814B 0x0460
+#define REG_RD_RESP_PKT_TH_8814B 0x0463
+#define REG_NEW_EDCA_CTRL_V1_8814B 0x0464
+#define REG_ACQ_STOP_V2_8814B 0x0468
+#define REG_WMAC_LBK_BUF_HD_V1_8814B 0x0478
+#define REG_MGQ_BDNY_V1_8814B 0x047A
+#define REG_TXRPT_CTRL_8814B 0x047C
+#define REG_INIRTS_RATE_SEL_8814B 0x0480
+#define REG_BASIC_CFEND_RATE_8814B 0x0481
+#define REG_STBC_CFEND_RATE_8814B 0x0482
+#define REG_DATA_SC_8814B 0x0483
+#define REG_MOREDATA_V1_8814B 0x0484
+#define REG_DATA_SC1_8814B 0x0487
+#define REG_TXRPT_START_OFFSET_8814B 0x04AC
+#define REG_POWER_STAGE1_8814B 0x04B4
+#define REG_POWER_STAGE2_8814B 0x04B8
+#define REG_SW_AMPDU_BURST_MODE_CTRL_8814B 0x04BC
+#define REG_PKT_LIFE_TIME_8814B 0x04C0
+#define REG_STBC_SETTING_8814B 0x04C4
+#define REG_STBC_SETTING2_8814B 0x04C5
+#define REG_QUEUE_CTRL_8814B 0x04C6
+#define REG_SINGLE_AMPDU_CTRL_8814B 0x04C7
+#define REG_PROT_MODE_CTRL_8814B 0x04C8
+#define REG_BAR_MODE_CTRL_8814B 0x04CC
+#define REG_RA_TRY_RATE_AGG_LMT_8814B 0x04CF
+#define REG_MACID_SLEEP_CTRL_8814B 0x04D0
+#define REG_MACID_SLEEP_INFO_8814B 0x04D4
+#define REG_HW_SEQ0_8814B 0x04D8
+#define REG_HW_SEQ1_8814B 0x04DA
+#define REG_HW_SEQ2_8814B 0x04DC
+#define REG_HW_SEQ3_8814B 0x04DE
+#define REG_PTCL_ERR_STATUS_V1_8814B 0x04E2
+#define REG_NULL_PKT_STATUS_V2_8814B 0x04E4
+#define REG_PRECNT_CTRL_8814B 0x04E5
+#define REG_NULL_PKT_STATUS_EXTEND_V1_8814B 0x04E7
+#define REG_PTCL_DBG_V1_8814B 0x04EC
+#define REG_BT_POLLUTE_PKTCNT_8814B 0x04F0
+#define REG_CPUMGQ_TIMER_CTRL2_8814B 0x04F4
+#define REG_PTCL_DBG_OUT_8814B 0x04F8
+#define REG_DUMMY_PAGE4_V1_8814B 0x04FC
+#define REG_DUMMY_PAGE4_1_8814B 0x04FE
+#define REG_MU_OFFSET_8814B 0x1400
+#define REG_USEREG_SETTING_8814B 0x1420
+#define REG_BF0_TIME_SETTING_8814B 0x1428
+#define REG_BF1_TIME_SETTING_8814B 0x142C
+#define REG_BF_TIMEOUT_EN_8814B 0x1430
+#define REG_MACID_RELEASE_INFO_8814B 0x1434
+#define REG_MACID_RELEASE_SUCCESS_INFO_8814B 0x1438
+#define REG_MACID_RELEASE_CTRL_8814B 0x143C
+#define REG_FAST_EDCA_VOVI_SETTING_8814B 0x1448
+#define REG_FAST_EDCA_BEBK_SETTING_8814B 0x144C
+#define REG_MACID_DROP_INFO_8814B 0x1450
+#define REG_MACID_DROP_CTRL_8814B 0x1454
+#define REG_MGQ_FIFO_WRITE_POINTER_8814B 0x1470
+#define REG_MGQ_FIFO_READ_POINTER_8814B 0x1472
+#define REG_MGQ_FIFO_ENABLE_8814B 0x1472
+#define REG_MGQ_FIFO_RELEASE_INT_MASK_8814B 0x1474
+#define REG_MGQ_FIFO_RELEASE_INT_FLAG_8814B 0x1476
+#define REG_MGQ_FIFO_VALID_MAP_8814B 0x1478
+#define REG_MGQ_FIFO_LIFETIME_8814B 0x147A
+#define REG_PKT_TRANS_8814B 0x1480
+#define REG_SHCUT_LLC_ETH_TYPE0_8814B 0x1484
+#define REG_SHCUT_LLC_ETH_TYPE1_8814B 0x1488
+#define REG_SHCUT_LLC_OUI0_8814B 0x148C
+#define REG_SHCUT_LLC_OUI1_8814B 0x1490
+#define REG_SHCUT_LLC_OUI2_8814B 0x1494
+#define REG_FWCMDQ_CTRL_8814B 0x14A0
+#define REG_FWCMDQ_PAGE_8814B 0x14A4
+#define REG_FWCMDQ_INFO_8814B 0x14A8
+#define REG_FWCMDQ_HOLD_PKTNUM_8814B 0x14AC
+#define REG_MU_TX_CTRL_8814B 0x14C0
+#define REG_MU_STA_GID_VLD_8814B 0x14C4
+#define REG_MU_STA_USER_POS_INFO_8814B 0x14C8
+#define REG_MU_STA_USER_POS_INFO_H_8814B 0x14CC
+#define REG_CHNL_INFO_CTRL_8814B 0x14D0
+#define REG_CHNL_IDLE_TIME_8814B 0x14D4
+#define REG_CHNL_BUSY_TIME_8814B 0x14D8
+#define REG_MU_TRX_DBG_CNT_V1_8814B 0x14DC
+#define REG_SWPS_CTRL_8814B 0x14F4
+#define REG_SWPS_PKT_TH_8814B 0x14F6
+#define REG_SWPS_TIME_TH_8814B 0x14F8
+#define REG_MACID_SWPS_EN_8814B 0x14FC
+#define REG_EDCA_VO_PARAM_8814B 0x0500
+#define REG_EDCA_VI_PARAM_8814B 0x0504
+#define REG_EDCA_BE_PARAM_8814B 0x0508
+#define REG_EDCA_BK_PARAM_8814B 0x050C
+#define REG_BCNTCFG_8814B 0x0510
+#define REG_PIFS_8814B 0x0512
+#define REG_RDG_PIFS_8814B 0x0513
+#define REG_SIFS_8814B 0x0514
+#define REG_FORCE_BCN_IFS_V1_8814B 0x0518
+#define REG_AGGR_BREAK_TIME_8814B 0x051A
+#define REG_SLOT_8814B 0x051B
+#define REG_EDCA_CPUMGQ_PARAM_8814B 0x051C
+#define REG_CPUMGQ_PAUSE_8814B 0x051E
+#define REG_TX_PTCL_CTRL_8814B 0x0520
+#define REG_TXPAUSE_8814B 0x0522
+#define REG_DIS_TXREQ_CLR_8814B 0x0523
+#define REG_RD_CTRL_8814B 0x0524
+#define REG_PKT_LIFETIME_CTRL_8814B 0x0528
+#define REG_TXOP_LIMIT_CTRL_8814B 0x052C
+#define REG_CCA_TXEN_CNT_8814B 0x0534
+#define REG_MAX_INTER_COLLISION_8814B 0x0538
+#define REG_MAX_INTER_COLLISION_CNT_8814B 0x053C
+#define REG_RD_NAV_NXT_8814B 0x0544
+#define REG_NAV_PROT_LEN_8814B 0x0546
+#define REG_FTM_PTT_8814B 0x0548
+#define REG_FTM_TSF_8814B 0x054C
+#define REG_HGQ_TIMEOUT_PERIOD_8814B 0x0575
+#define REG_TXCMD_TIMEOUT_PERIOD_8814B 0x0576
+#define REG_MISC_CTRL_8814B 0x0577
+#define REG_TXOP_MIN_8814B 0x0590
+#define REG_PRE_BKF_TIME_8814B 0x0592
+#define REG_CROSS_TXOP_CTRL_8814B 0x0593
+#define REG_ACMHWCTRL_8814B 0x05C0
+#define REG_ACMRSTCTRL_8814B 0x05C1
+#define REG_ACMAVG_8814B 0x05C2
+#define REG_VO_ADMTIME_8814B 0x05C4
+#define REG_VI_ADMTIME_8814B 0x05C6
+#define REG_BE_ADMTIME_8814B 0x05C8
+#define REG_MAC_HEADER_NAV_OFFSET_8814B 0x05CA
+#define REG_DIS_NDPA_NAV_CHECK_8814B 0x05CB
+#define REG_EDCA_RANDOM_GEN_8814B 0x05CC
+#define REG_TXCMD_SEL_8814B 0x05CF
+#define REG_MU_DBG_INFO_8814B 0x05E8
+#define REG_MU_DBG_INFO_1_8814B 0x05EC
+#define REG_SCH_DBG_SEL_8814B 0x05F0
+#define REG_SCHEDULER_RST_8814B 0x05F1
+#define REG_MU_DBG_ERR_FLAG_8814B 0x05F2
+#define REG_TX_ERR_RECOVERY_RST_8814B 0x05F3
+#define REG_SCH_DBG_VALUE_8814B 0x05F4
+#define REG_SCH_TXCMD_8814B 0x05F8
+#define REG_PAGE5_DUMMY_8814B 0x05FC
+#define REG_PORT_CTRL_SEL_8814B 0x1500
+#define REG_PORT_CTRL_CFG_8814B 0x1501
+#define REG_TBTT_PROHIBIT_CFG_8814B 0x1504
+#define REG_DRVERLYINT_CFG_8814B 0x1507
+#define REG_BCNDMATIM_CFG_8814B 0x1508
+#define REG_CTWND_CFG_8814B 0x1509
+#define REG_BCNIVLCUNT_CFG_8814B 0x150A
+#define REG_EARLY_128US_CFG_8814B 0x150B
+#define REG_TSFTR_SYNC_OFFSET_CFG_8814B 0x150C
+#define REG_TSFTR_SYNC_CTRL_CFG_8814B 0x150F
+#define REG_BCN_SPACE_CFG_8814B 0x1510
+#define REG_EARLY_INT_ADJUST_CFG_8814B 0x1512
+#define REG_SW_TBTT_TSF_INFO_8814B 0x151C
+#define REG_TSFTR_LOW_8814B 0x1520
+#define REG_TSFTR_HIGH_8814B 0x1524
+#define REG_BCN_ERR_CNT_MAC_8814B 0x1528
+#define REG_BCN_ERR_CNT_EDCCA_8814B 0x1529
+#define REG_BCN_ERR_CNT_CCA_8814B 0x152A
+#define REG_BCN_ERR_CNT_INVALID_8814B 0x152B
+#define REG_BCN_ERR_CNT_OTHERS_8814B 0x152C
+#define REG_RX_BCN_TIMER_8814B 0x152D
+#define REG_TBTT_CTN_AREA_V1_8814B 0x1530
+#define REG_BCN_MAX_ERR_V1_8814B 0x1531
+#define REG_RXTSF_OFFSET_CCK_V1_8814B 0x1532
+#define REG_RXTSF_OFFSET_OFDM_V1_8814B 0x1533
+#define REG_SUB_BCN_SPACE_8814B 0x1534
+#define REG_MBID_NUM_V1_8814B 0x1535
+#define REG_MBSSID_CTRL_V1_8814B 0x1536
+#define REG_USTIME_TSF_V1_8814B 0x1538
+#define REG_BW_CFG_8814B 0x1539
+#define REG_ATIMWND_CFG_8814B 0x153A
+#define REG_DTIM_COUNTER_CFG_8814B 0x153B
+#define REG_ATIM_DTIM_CTRL_SEL_8814B 0x153C
+#define REG_ATIMUGT_V1_8814B 0x153D
+#define REG_BCNDROPCTRL_V1_8814B 0x153E
+#define REG_DIS_ATIM_V1_8814B 0x1540
+#define REG_HIQ_NO_LMT_EN_V1_8814B 0x1544
+#define REG_P2PPS_CTRL_V1_8814B 0x1548
+#define REG_P2PPS_SPEC_STATE_V1_8814B 0x154A
+#define REG_P2PPS_STATE_V1_8814B 0x154B
+#define REG_P2PPS1_CTRL_V1_8814B 0x154C
+#define REG_P2PPS1_SPEC_STATE_V1_8814B 0x154E
+#define REG_P2PPS1_STATE_V1_8814B 0x154F
+#define REG_P2PPS2_CTRL_V1_8814B 0x1550
+#define REG_P2PPS2_SPEC_STATE_V1_8814B 0x1552
+#define REG_P2PPS2_STATE_V1_8814B 0x1553
+#define REG_P2PON_DIS_TXTIME_V1_8814B 0x1554
+#define REG_P2POFF_DIS_TXTIME_V1_8814B 0x1555
+#define REG_CHG_POWER_BCN_AREA_8814B 0x1556
+#define REG_NOA_SEL_8814B 0x1557
+#define REG_NOA_PARAM_V1_8814B 0x1558
+#define REG_NOA_PARAM_1_V1_8814B 0x155C
+#define REG_NOA_PARAM_2_V1_8814B 0x1560
+#define REG_NOA_PARAM_3_V1_8814B 0x1564
+#define REG_NOA_ON_ERLY_TIME_V1_8814B 0x1568
+#define REG_NOA_OFF_ERLY_TIME_V1_8814B 0x1569
+#define REG_P2PPS_HW_AUTO_PAUSE_CTRL_8814B 0x156C
+#define REG_P2PPS1_HW_AUTO_PAUSE_CTRL_8814B 0x1570
+#define REG_P2PPS2_HW_AUTO_PAUSE_CTRL_8814B 0x1574
+#define REG_RX_TBTT_SHIFT_8814B 0x1578
+#define REG_FREERUN_CNT_LOW_8814B 0x1580
+#define REG_FREERUN_CNT_HIGH_8814B 0x1584
+#define REG_CPUMGQ_TX_TIMER_V1_8814B 0x1588
+#define REG_PS_TIMER_0_8814B 0x158C
+#define REG_PS_TIMER_1_8814B 0x1590
+#define REG_PS_TIMER_2_8814B 0x1594
+#define REG_PS_TIMER_3_8814B 0x1598
+#define REG_PS_TIMER_4_8814B 0x159C
+#define REG_PS_TIMER_5_8814B 0x15A0
+#define REG_PS_TIMER_01_CTRL_8814B 0x15A4
+#define REG_PS_TIMER_23_CTRL_8814B 0x15A8
+#define REG_PS_TIMER_45_CTRL_8814B 0x15AC
+#define REG_CPUMGQ_FREERUN_TIMER_CTRL_8814B 0x15B0
+#define REG_CPUMGQ_PROHIBIT_8814B 0x15B4
+#define REG_TIMER_COMPARE_8814B 0x15C0
+#define REG_TIMER_COMPARE_VALUE_LOW_8814B 0x15C4
+#define REG_TIMER_COMPARE_VALUE_HIGH_8814B 0x15C8
+#define REG_WMAC_CR_8814B 0x0600
+#define REG_WMAC_FWPKT_CR_8814B 0x0601
+#define REG_FW_STS_FILTER_8814B 0x0602
+#define REG_TCR_8814B 0x0604
+#define REG_RCR_8814B 0x0608
+#define REG_RX_PKT_LIMIT_8814B 0x060C
+#define REG_RX_DLK_TIME_8814B 0x060D
+#define REG_RX_DRVINFO_SZ_8814B 0x060F
+#define REG_MACID_8814B 0x0610
+#define REG_MACID_H_8814B 0x0614
+#define REG_BSSID_8814B 0x0618
+#define REG_BSSID_H_8814B 0x061C
+#define REG_MAR_8814B 0x0620
+#define REG_MAR_H_8814B 0x0624
+#define REG_WMAC_DEBUG_SEL_8814B 0x062C
+#define REG_WMAC_TCR_TSFT_OFS_8814B 0x0630
+#define REG_UDF_THSD_8814B 0x0632
+#define REG_ZLD_NUM_8814B 0x0633
+#define REG_STMP_THSD_8814B 0x0634
+#define REG_WMAC_TXTIMEOUT_8814B 0x0635
+#define REG_MCU_TEST_2_V1_8814B 0x0636
+#define REG_USTIME_EDCA_8814B 0x0638
+#define REG_ACKTO_CCK_8814B 0x0639
+#define REG_MAC_SPEC_SIFS_8814B 0x063A
+#define REG_RESP_SIFS_CCK_8814B 0x063C
+#define REG_RESP_SIFS_OFDM_8814B 0x063E
+#define REG_ACKTO_8814B 0x0640
+#define REG_CTS2TO_8814B 0x0641
+#define REG_EIFS_8814B 0x0642
+#define REG_RPFM_MAP0_8814B 0x0644
+#define REG_RPFM_MAP1_V1_8814B 0x0646
+#define REG_RPFM_CAM_CMD_8814B 0x0648
+#define REG_RPFM_CAM_RWD_8814B 0x064C
+#define REG_NAV_CTRL_8814B 0x0650
+#define REG_BACAMCMD_8814B 0x0654
+#define REG_BACAMCONTENT_8814B 0x0658
+#define REG_BACAMCONTENT_H_8814B 0x065C
+#define REG_LBDLY_8814B 0x0660
+#define REG_WMAC_BACAM_RPMEN_8814B 0x0661
+#define REG_TX_RX_8814B 0x0662
+#define REG_WMAC_BITMAP_CTL_8814B 0x0663
+#define REG_RXERR_RPT_8814B 0x0664
+#define REG_WMAC_TRXPTCL_CTL_8814B 0x0668
+#define REG_WMAC_TRXPTCL_CTL_H_8814B 0x066C
+#define REG_CAMCMD_8814B 0x0670
+#define REG_CAMWRITE_8814B 0x0674
+#define REG_CAMREAD_8814B 0x0678
+#define REG_CAMDBG_8814B 0x067C
+#define REG_SECCFG_8814B 0x0680
+#define REG_RXFILTER_CATEGORY_1_8814B 0x0682
+#define REG_RXFILTER_ACTION_1_8814B 0x0683
+#define REG_RXFILTER_CATEGORY_2_8814B 0x0684
+#define REG_RXFILTER_ACTION_2_8814B 0x0685
+#define REG_RXFILTER_CATEGORY_3_8814B 0x0686
+#define REG_RXFILTER_ACTION_3_8814B 0x0687
+#define REG_RXFLTMAP3_8814B 0x0688
+#define REG_RXFLTMAP4_8814B 0x068A
+#define REG_RXFLTMAP5_8814B 0x068C
+#define REG_RXFLTMAP6_8814B 0x068E
+#define REG_WOW_CTRL_8814B 0x0690
+#define REG_NAN_RX_TSF_FILTER_8814B 0x0691
+#define REG_PS_RX_INFO_8814B 0x0692
+#define REG_WMMPS_UAPSD_TID_8814B 0x0693
+#define REG_LPNAV_CTRL_8814B 0x0694
+#define REG_WKFMCAM_CMD_8814B 0x0698
+#define REG_WKFMCAM_RWD_8814B 0x069C
+#define REG_RXFLTMAP0_8814B 0x06A0
+#define REG_RXFLTMAP1_8814B 0x06A2
+#define REG_RXFLTMAP2_8814B 0x06A4
+#define REG_BCN_PSR_RPT_8814B 0x06A8
+#define REG_FLC_RPC_8814B 0x06AC
+#define REG_FLC_RPCT_8814B 0x06AD
+#define REG_FLC_PTS_8814B 0x06AE
+#define REG_FLC_TRPC_8814B 0x06AF
+#define REG_RXPKTMON_CTRL_8814B 0x06B0
+#define REG_STATE_MON_8814B 0x06B4
+#define REG_ERROR_MON_8814B 0x06B8
+#define REG_SEARCH_MACID_8814B 0x06BC
+#define REG_BT_COEX_TABLE_8814B 0x06C0
+#define REG_BT_COEX_TABLE2_8814B 0x06C4
+#define REG_BT_COEX_BREAK_TABLE_8814B 0x06C8
+#define REG_BT_COEX_TABLE_H_8814B 0x06CC
+#define REG_RXCMD_0_8814B 0x06D0
+#define REG_RXCMD_1_8814B 0x06D4
+#define REG_WMAC_RESP_TXINFO_8814B 0x06D8
+#define REG_BBPSF_CTRL_8814B 0x06DC
+#define REG_P2P_RX_BCN_NOA_8814B 0x06E0
+#define REG_ASSOCIATED_BFMER0_INFO_8814B 0x06E4
+#define REG_ASSOCIATED_BFMER0_INFO_H_8814B 0x06E8
+#define REG_ASSOCIATED_BFMER1_INFO_8814B 0x06EC
+#define REG_ASSOCIATED_BFMER1_INFO_H_8814B 0x06F0
+#define REG_TX_CSI_RPT_PARAM_BW20_8814B 0x06F4
+#define REG_TX_CSI_RPT_PARAM_BW40_8814B 0x06F8
+#define REG_BCN_PSR_RPT2_8814B 0x1600
+#define REG_BCN_PSR_RPT3_8814B 0x1604
+#define REG_BCN_PSR_RPT4_8814B 0x1608
+#define REG_A1_ADDR_MASK_8814B 0x160C
+#define REG_RXPSF_CTRL_8814B 0x1610
+#define REG_RXPSF_TYPE_CTRL_8814B 0x1614
+#define REG_CAM_ACCESS_CTRL_8814B 0x1618
+#define REG_CUT_AMSDU_CTRL_8814B 0x161C
+#define REG_MACID2_8814B 0x1620
+#define REG_MACID2_H_8814B 0x1624
+#define REG_BSSID2_8814B 0x1628
+#define REG_BSSID2_H_8814B 0x162C
+#define REG_MACID3_8814B 0x1630
+#define REG_MACID3_H_8814B 0x1634
+#define REG_BSSID3_8814B 0x1638
+#define REG_BSSID3_H_8814B 0x163C
+#define REG_MACID4_8814B 0x1640
+#define REG_MACID4_H_8814B 0x1644
+#define REG_BSSID4_8814B 0x1648
+#define REG_BSSID4_H_8814B 0x164C
+#define REG_NOA_REPORT_8814B 0x1650
+#define REG_NOA_REPORT_1_8814B 0x1654
+#define REG_NOA_REPORT_2_8814B 0x1658
+#define REG_NOA_REPORT_3_8814B 0x165C
+#define REG_PWRBIT_SETTING_8814B 0x1660
+#define REG_GENERAL_OPTION_8814B 0x1664
+#define REG_FWPHYFF_RCR_8814B 0x1668
+#define REG_ADDRCAM_WRITE_CONTENT_8814B 0x166C
+#define REG_ADDRCAM_READ_CONTENT_8814B 0x1670
+#define REG_ADDRCAM_CFG_8814B 0x1674
+#define REG_CSI_RRSR_8814B 0x1678
+#define REG_MU_BF_OPTION_8814B 0x167C
+#define REG_WMAC_PAUSE_BB_CLR_TH_8814B 0x167D
+#define REG_WMAC_MULBK_BUF_8814B 0x167E
+#define REG_WMAC_MU_OPTION_8814B 0x167F
+#define REG_WMAC_MU_BF_CTL_8814B 0x1680
+#define REG_WMAC_MU_BFRPT_PARA_8814B 0x1682
+#define REG_WMAC_ASSOCIATED_MU_BFMEE2_8814B 0x1684
+#define REG_WMAC_ASSOCIATED_MU_BFMEE3_8814B 0x1686
+#define REG_WMAC_ASSOCIATED_MU_BFMEE4_8814B 0x1688
+#define REG_WMAC_ASSOCIATED_MU_BFMEE5_8814B 0x168A
+#define REG_WMAC_ASSOCIATED_MU_BFMEE6_8814B 0x168C
+#define REG_WMAC_ASSOCIATED_MU_BFMEE7_8814B 0x168E
+#define REG_WMAC_BB_STOP_RX_COUNTER_8814B 0x1690
+#define REG_WMAC_PLCP_MONITOR_8814B 0x1694
+#define REG_WMAC_DEBUG_PORT_8814B 0x1698
+#define REG_TRANSMIT_ADDRSS_0_8814B 0x16A0
+#define REG_TRANSMIT_ADDRSS_0_H_8814B 0x16A4
+#define REG_TRANSMIT_ADDRSS_1_8814B 0x16A8
+#define REG_TRANSMIT_ADDRSS_1_H_8814B 0x16AC
+#define REG_TRANSMIT_ADDRSS_2_8814B 0x16B0
+#define REG_TRANSMIT_ADDRSS_2_H_8814B 0x16B4
+#define REG_TRANSMIT_ADDRSS_3_8814B 0x16B8
+#define REG_TRANSMIT_ADDRSS_3_H_8814B 0x16BC
+#define REG_TRANSMIT_ADDRSS_4_8814B 0x16C0
+#define REG_TRANSMIT_ADDRSS_4_H_8814B 0x16C4
+#define REG_MACID1_8814B 0x0700
+#define REG_MACID1_1_8814B 0x0704
+#define REG_BSSID1_8814B 0x0708
+#define REG_BSSID1_1_8814B 0x070C
+#define REG_BCN_PSR_RPT1_8814B 0x0710
+#define REG_ASSOCIATED_BFMEE_SEL_8814B 0x0714
+#define REG_SND_PTCL_CTRL_8814B 0x0718
+#define REG_RX_CSI_RPT_INFO_8814B 0x071C
+#define REG_NS_ARP_CTRL_8814B 0x0720
+#define REG_NS_ARP_INFO_8814B 0x0724
+#define REG_BEAMFORMING_INFO_NSARP_V1_8814B 0x0728
+#define REG_BEAMFORMING_INFO_NSARP_8814B 0x072C
+#define REG_IPV6_8814B 0x0730
+#define REG_IPV6_1_8814B 0x0734
+#define REG_IPV6_2_8814B 0x0738
+#define REG_IPV6_3_8814B 0x073C
+#define REG_WMAC_RTX_CTX_SUBTYPE_CFG_8814B 0x0750
+#define REG_WMAC_SWAES_CFG_8814B 0x0760
+#define REG_BT_COEX_V2_8814B 0x0762
+#define REG_BT_COEX_8814B 0x0764
+#define REG_WLAN_ACT_MASK_CTRL_8814B 0x0768
+#define REG_WLAN_ACT_MASK_CTRL_1_8814B 0x076C
+#define REG_BT_COEX_ENHANCED_INTR_CTRL_8814B 0x076E
+#define REG_BT_ACT_STATISTICS_8814B 0x0770
+#define REG_BT_ACT_STATISTICS_1_8814B 0x0774
+#define REG_BT_STATISTICS_CONTROL_REGISTER_8814B 0x0778
+#define REG_BT_STATUS_REPORT_REGISTER_8814B 0x077C
+#define REG_BT_INTERRUPT_CONTROL_REGISTER_8814B 0x0780
+#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8814B 0x0784
+#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8814B 0x0785
+#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1_8814B 0x0788
+#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2_8814B 0x078C
+#define REG_BT_INTERRUPT_STATUS_REGISTER_8814B 0x078F
+#define REG_BT_TDMA_TIME_REGISTER_8814B 0x0790
+#define REG_BT_ACT_REGISTER_8814B 0x0794
+#define REG_OBFF_CTRL_BASIC_8814B 0x0798
+#define REG_OBFF_CTRL2_TIMER_8814B 0x079C
+#define REG_LTR_CTRL_BASIC_8814B 0x07A0
+#define REG_LTR_CTRL2_TIMER_THRESHOLD_8814B 0x07A4
+#define REG_LTR_IDLE_LATENCY_V1_8814B 0x07A8
+#define REG_LTR_ACTIVE_LATENCY_V1_8814B 0x07AC
+#define REG_SMART_ANT_CONDITION_8814B 0x07B0
+#define REG_SMART_ANT_CTRL_8814B 0x07B4
+#define REG_CONTROL_FRAME_REPORT_8814B 0x07B8
+#define REG_CONTROL_FRAME_CNT_CTRL_8814B 0x07BC
+#define REG_IQ_DUMP_8814B 0x07C0
+#define REG_IQ_DUMP_1_8814B 0x07C4
+#define REG_IQ_DUMP_2_8814B 0x07C8
+#define REG_WMAC_FTM_CTL_8814B 0x07CC
+#define REG_WMAC_IQ_MDPK_FUNC_8814B 0x07CE
+#define REG_WMAC_OPTION_FUNCTION_8814B 0x07D0
+#define REG_WMAC_OPTION_FUNCTION_1_8814B 0x07D4
+#define REG_WMAC_OPTION_FUNCTION_2_8814B 0x07D8
+#define REG_RX_FILTER_FUNCTION_8814B 0x07DA
+#define REG_NDP_SIG_8814B 0x07E0
+#define REG_TXCMD_INFO_FOR_RSP_PKT_8814B 0x07E4
+#define REG_TXCMD_INFO_FOR_RSP_PKT_1_8814B 0x07E8
+#define REG_WSEC_OPTION_8814B 0x07EC
+#define REG_RTS_ADDRESS_0_8814B 0x07F0
+#define REG_RTS_ADDRESS_0_1_8814B 0x07F4
+#define REG_RTS_ADDRESS_1_8814B 0x07F8
+#define REG_RTS_ADDRESS_1_1_8814B 0x07FC
+#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8814B 0x1700
+#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8814B 0x1704
+#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8814B 0x1708
+#define REG_PCIE_CFG_FORCE_LINK_L_8814B 0x0709
+#define REG_PCIE_CFG_FORCE_LINK_H_8814B 0x070A
+#define REG_PCIE_CFG_DEFAULT_ACK_FREQUENCY_8814B 0x070C
+#define REG_PCIE_CFG_CX_NFTS_8814B 0x070D
+#define REG_PCIE_CFG_DEFAULT_ENTR_LATENCY_8814B 0x070F
+#define REG_PCIE_CFG_L1_MISC_SEL_8814B 0x0711
+#define REG_PCIE_CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF_8814B 0x0718
+#define REG_PCIE_CFG_FORCE_CLKREQ_N_PAD_8814B 0x0719
+#define REG_PCIE_CFG_TIMER_MODIFIER_FOR_ACK_NAK_LATENCY_8814B 0x071A
+#define REG_PCIE_CFG_TIMER_MODIFIER_FOR_FLOW_CONTROL_WATCHDOG_8814B 0x071B
+#define REG_PCIE_CFG_SKP_INTERVAL_VALUE_L_8814B 0x071C
+#define REG_PCIE_CFG_SKP_INTERVAL_VALUE_H_8814B 0x071D
+#define REG_PCIE_CFG_L1_UNIT_SEL_8814B 0x0724
+#define REG_PCIE_CFG_MIN_CLKREQ_SEL_8814B 0x0725
+#define REG_SDIO_TX_CTRL_8814B 0x10250000
+#define REG_SDIO_HIMR_8814B 0x10250014
+#define REG_SDIO_HISR_8814B 0x10250018
+#define REG_SDIO_RX_REQ_LEN_8814B 0x1025001C
+#define REG_SDIO_FREE_TXPG_SEQ_V1_8814B 0x1025001F
+#define REG_SDIO_FREE_TXPG_8814B 0x10250020
+#define REG_SDIO_FREE_TXPG2_8814B 0x10250024
+#define REG_SDIO_OQT_FREE_TXPG_V1_8814B 0x10250028
+#define REG_SDIO_HTSFR_INFO_8814B 0x10250030
+#define REG_SDIO_HCPWM1_V2_8814B 0x10250038
+#define REG_SDIO_HCPWM2_V2_8814B 0x1025003A
+#define REG_SDIO_INDIRECT_REG_CFG_8814B 0x10250040
+#define REG_SDIO_INDIRECT_REG_DATA_8814B 0x10250044
+#define REG_SDIO_H2C_8814B 0x10250060
+#define REG_SDIO_C2H_8814B 0x10250064
+#define REG_SDIO_HRPWM1_8814B 0x10250080
+#define REG_SDIO_HRPWM2_8814B 0x10250082
+#define REG_SDIO_HPS_CLKR_8814B 0x10250084
+#define REG_SDIO_BUS_CTRL_8814B 0x10250085
+#define REG_SDIO_HSUS_CTRL_8814B 0x10250086
+#define REG_SDIO_RESPONSE_TIMER_8814B 0x10250088
+#define REG_SDIO_CMD_CRC_8814B 0x1025008A
+#define REG_SDIO_HSISR_8814B 0x10250090
+#define REG_SDIO_ERR_RPT_8814B 0x102500C0
+#define REG_SDIO_CMD_ERRCNT_8814B 0x102500C2
+#define REG_SDIO_DATA_ERRCNT_8814B 0x102500C3
+#define REG_SDIO_CMD_ERR_CONTENT_8814B 0x102500C4
+#define REG_SDIO_CRC_ERR_IDX_8814B 0x102500C9
+#define REG_SDIO_DATA_CRC_8814B 0x102500CA
+#define REG_SDIO_DATA_REPLY_TIME_8814B 0x102500CB
+
+#endif
diff --git a/hal/halmac/halmac_reg_8821c.h b/hal/halmac/halmac_reg_8821c.h
index e49ef56..dd93baf 100644
--- a/hal/halmac/halmac_reg_8821c.h
+++ b/hal/halmac/halmac_reg_8821c.h
@@ -1,3 +1,18 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
#ifndef __INC_HALMAC_REG_8821C_H
#define __INC_HALMAC_REG_8821C_H
@@ -69,7 +84,6 @@
#define REG_SYS_STATUS2_8821C 0x00F8
#define REG_SYS_CFG2_8821C 0x00FC
#define REG_SYS_CFG3_8821C 0x1000
-#define REG_SYS_CFG4_8821C 0x1034
#define REG_SYS_CFG5_8821C 0x1070
#define REG_CPU_DMEM_CON_8821C 0x1080
#define REG_BOOT_REASON_8821C 0x1088
@@ -79,19 +93,13 @@
#define REG_HIMR3_8821C 0x10B8
#define REG_HISR3_8821C 0x10BC
#define REG_SW_MDIO_8821C 0x10C0
-#define REG_SW_FLUSH_8821C 0x10C4
#define REG_H2C_PKT_READADDR_8821C 0x10D0
#define REG_H2C_PKT_WRITEADDR_8821C 0x10D4
#define REG_MEM_PWR_CRTL_8821C 0x10D8
-#define REG_FW_DBG0_8821C 0x10E0
-#define REG_FW_DBG1_8821C 0x10E4
-#define REG_FW_DBG2_8821C 0x10E8
-#define REG_FW_DBG3_8821C 0x10EC
-#define REG_FW_DBG4_8821C 0x10F0
-#define REG_FW_DBG5_8821C 0x10F4
#define REG_FW_DBG6_8821C 0x10F8
#define REG_FW_DBG7_8821C 0x10FC
#define REG_CR_8821C 0x0100
+#define REG_PG_SIZE_8821C 0x0104
#define REG_PKT_BUFF_ACCESS_CTRL_8821C 0x0106
#define REG_TSF_CLK_STATE_8821C 0x0108
#define REG_TXDMA_PQ_MAP_8821C 0x010C
@@ -117,17 +125,21 @@
#define REG_TCUNIT_BASE_8821C 0x0164
#define REG_TC5_CTRL_8821C 0x0168
#define REG_TC6_CTRL_8821C 0x016C
-#define REG_MBIST_FAIL_8821C 0x0170
+#define REG_MBIST_DRF_FAIL_8821C 0x0170
#define REG_MBIST_START_PAUSE_8821C 0x0174
#define REG_MBIST_DONE_8821C 0x0178
-#define REG_MBIST_FAIL_NRML_8821C 0x017C
+#define REG_MBIST_READ_BIST_RPT_8821C 0x017C
#define REG_AES_DECRPT_DATA_8821C 0x0180
#define REG_AES_DECRPT_CFG_8821C 0x0184
#define REG_TMETER_8821C 0x0190
#define REG_OSC_32K_CTRL_8821C 0x0194
#define REG_32K_CAL_REG1_8821C 0x0198
#define REG_C2HEVT_8821C 0x01A0
+#define REG_C2HEVT_1_8821C 0x01A4
+#define REG_C2HEVT_2_8821C 0x01A8
+#define REG_C2HEVT_3_8821C 0x01AC
#define REG_SW_DEFINED_PAGE1_8821C 0x01B8
+#define REG_SW_DEFINED_PAGE2_8821C 0x01BC
#define REG_MCUTST_I_8821C 0x01C0
#define REG_MCUTST_II_8821C 0x01C4
#define REG_FMETHR_8821C 0x01C8
@@ -136,8 +148,6 @@
#define REG_HMEBOX1_8821C 0x01D4
#define REG_HMEBOX2_8821C 0x01D8
#define REG_HMEBOX3_8821C 0x01DC
-#define REG_LLT_INIT_8821C 0x01E0
-#define REG_LLT_INIT_ADDR_8821C 0x01E4
#define REG_BB_ACCESS_CTRL_8821C 0x01E8
#define REG_BB_ACCESS_DATA_8821C 0x01EC
#define REG_HMEBOX_E0_8821C 0x01F0
@@ -163,6 +173,22 @@
#define REG_POWSEQ_8821C 0x1150
#define REG_TC7_CTRL_V1_8821C 0x1158
#define REG_TC8_CTRL_V1_8821C 0x115C
+#define REG_RX_BCN_TBTT_ITVL0_8821C 0x1160
+#define REG_RX_BCN_TBTT_ITVL1_8821C 0x1164
+#define REG_IO_WRAP_ERR_FLAG_8821C 0x1170
+#define REG_SPEED_SENSOR_8821C 0x1180
+#define REG_SPEED_SENSOR1_8821C 0x1184
+#define REG_SPEED_SENSOR2_8821C 0x1188
+#define REG_SPEED_SENSOR3_8821C 0x118C
+#define REG_SPEED_SENSOR4_8821C 0x1190
+#define REG_SPEED_SENSOR5_8821C 0x1194
+#define REG_COUNTER_CTRL_8821C 0x11C4
+#define REG_COUNTER_THRESHOLD_8821C 0x11C8
+#define REG_COUNTER_SET_8821C 0x11CC
+#define REG_COUNTER_OVERFLOW_8821C 0x11D0
+#define REG_TXDMA_LEN_THRESHOLD_8821C 0x11D4
+#define REG_RXDMA_LEN_THRESHOLD_8821C 0x11D8
+#define REG_PCIE_EXEC_TIME_THRESHOLD_8821C 0x11DC
#define REG_FT2IMR_8821C 0x11E0
#define REG_FT2ISR_8821C 0x11E4
#define REG_MSG2_8821C 0x11F0
@@ -217,7 +243,7 @@
#define REG_DDMA_CH4CTRL_8821C 0x1248
#define REG_DDMA_CH5SA_8821C 0x1250
#define REG_DDMA_CH5DA_8821C 0x1254
-#define REG_REG_DDMA_CH5CTRL_8821C 0x1258
+#define REG_DDMA_CH5CTRL_8821C 0x1258
#define REG_DDMA_INT_MSK_8821C 0x12E0
#define REG_DDMA_CHSTATUS_8821C 0x12E8
#define REG_DDMA_CHKSUM_8821C 0x12F0
@@ -308,10 +334,14 @@
#define REG_RETRY_LIMIT_8821C 0x042A
#define REG_TXBF_CTRL_8821C 0x042C
#define REG_DARFRC_8821C 0x0430
+#define REG_DARFRCH_8821C 0x0434
#define REG_RARFRC_8821C 0x0438
+#define REG_RARFRCH_8821C 0x043C
#define REG_RRSR_8821C 0x0440
#define REG_ARFR0_8821C 0x0444
+#define REG_ARFRH0_8821C 0x0448
#define REG_ARFR1_V1_8821C 0x044C
+#define REG_ARFRH1_V1_8821C 0x0450
#define REG_CCK_CHECK_8821C 0x0454
#define REG_AMPDU_MAX_TIME_V1_8821C 0x0455
#define REG_BCNQ1_BDNY_V1_8821C 0x0456
@@ -336,9 +366,13 @@
#define REG_MACID_SLEEP3_8821C 0x0484
#define REG_MACID_SLEEP1_8821C 0x0488
#define REG_ARFR2_V1_8821C 0x048C
+#define REG_ARFRH2_V1_8821C 0x0490
#define REG_ARFR3_V1_8821C 0x0494
+#define REG_ARFRH3_V1_8821C 0x0498
#define REG_ARFR4_8821C 0x049C
+#define REG_ARFRH4_8821C 0x04A0
#define REG_ARFR5_8821C 0x04A4
+#define REG_ARFRH5_8821C 0x04A8
#define REG_TXRPT_START_OFFSET_8821C 0x04AC
#define REG_POWER_STAGE1_8821C 0x04B4
#define REG_POWER_STAGE2_8821C 0x04B8
@@ -361,6 +395,7 @@
#define REG_PTCL_ERR_STATUS_8821C 0x04E2
#define REG_NULL_PKT_STATUS_EXTEND_8821C 0x04E3
#define REG_VIDEO_ENHANCEMENT_FUN_8821C 0x04E4
+#define REG_PRECNT_CTRL_8821C 0x04E5
#define REG_BT_POLLUTE_PKT_CNT_8821C 0x04E8
#define REG_PTCL_DBG_8821C 0x04EC
#define REG_CPUMGQ_TIMER_CTRL2_8821C 0x04F4
@@ -392,13 +427,24 @@
#define REG_R_MACID_RELEASE_SUCCESS_1_8821C 0x1464
#define REG_R_MACID_RELEASE_SUCCESS_2_8821C 0x1468
#define REG_R_MACID_RELEASE_SUCCESS_3_8821C 0x146C
-#define REG_MGG_FIFO_CRTL_8821C 0x1470
-#define REG_MGG_FIFO_INT_8821C 0x1474
-#define REG_MGG_FIFO_LIFETIME_8821C 0x1478
+#define REG_MGQ_FIFO_WRITE_POINTER_8821C 0x1470
+#define REG_MGQ_FIFO_READ_POINTER_8821C 0x1472
+#define REG_MGQ_FIFO_ENABLE_8821C 0x1472
+#define REG_MGQ_FIFO_RELEASE_INT_MASK_8821C 0x1474
+#define REG_MGQ_FIFO_RELEASE_INT_FLAG_8821C 0x1476
+#define REG_MGQ_FIFO_VALID_MAP_8821C 0x1478
+#define REG_MGQ_FIFO_LIFETIME_8821C 0x147A
#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C 0x147C
+#define REG_SHCUT_SETTING_8821C 0x1480
+#define REG_SHCUT_LLC_ETH_TYPE0_8821C 0x1484
+#define REG_SHCUT_LLC_ETH_TYPE1_8821C 0x1488
+#define REG_SHCUT_LLC_OUI0_8821C 0x148C
+#define REG_SHCUT_LLC_OUI1_8821C 0x1490
+#define REG_SHCUT_LLC_OUI2_8821C 0x1494
#define REG_MU_TX_CTL_8821C 0x14C0
#define REG_MU_STA_GID_VLD_8821C 0x14C4
#define REG_MU_STA_USER_POS_INFO_8821C 0x14C8
+#define REG_MU_STA_USER_POS_INFO_H_8821C 0x14CC
#define REG_MU_TRX_DBG_CNT_8821C 0x14D0
#define REG_EDCA_VO_PARAM_8821C 0x0500
#define REG_EDCA_VI_PARAM_8821C 0x0504
@@ -411,6 +457,8 @@
#define REG_TSFTR_SYN_OFFSET_8821C 0x0518
#define REG_AGGR_BREAK_TIME_8821C 0x051A
#define REG_SLOT_8821C 0x051B
+#define REG_NOA_ON_ERLY_TIME_8821C 0x051C
+#define REG_NOA_OFF_ERLY_TIME_8821C 0x051D
#define REG_TX_PTCL_CTRL_8821C 0x0520
#define REG_TXPAUSE_8821C 0x0522
#define REG_DIS_TXREQ_CLR_8821C 0x0523
@@ -420,6 +468,7 @@
#define REG_PKT_LIFETIME_CTRL_8821C 0x0528
#define REG_P2PPS_SPEC_STATE_8821C 0x052B
#define REG_BAR_TX_CTRL_8821C 0x0530
+#define REG_P2PON_DIS_TXTIME_8821C 0x0531
#define REG_TBTT_PROHIBIT_8821C 0x0540
#define REG_P2PPS_STATE_8821C 0x0543
#define REG_RD_NAV_NXT_8821C 0x0544
@@ -437,7 +486,9 @@
#define REG_RXTSF_OFFSET_CCK_8821C 0x055E
#define REG_RXTSF_OFFSET_OFDM_8821C 0x055F
#define REG_TSFTR_8821C 0x0560
+#define REG_TSFTR_1_8821C 0x0564
#define REG_FREERUN_CNT_8821C 0x0568
+#define REG_FREERUN_CNT_1_8821C 0x056C
#define REG_ATIMWND1_V1_8821C 0x0570
#define REG_TBTT_PROHIBIT_INFRA_8821C 0x0571
#define REG_CTWND_8821C 0x0572
@@ -496,6 +547,9 @@
#define REG_EDCA_RANDOM_GEN_8821C 0x05CC
#define REG_TXCMD_NOA_SEL_8821C 0x05CF
#define REG_NOA_PARAM_8821C 0x05E0
+#define REG_NOA_PARAM_1_8821C 0x05E4
+#define REG_NOA_PARAM_2_8821C 0x05E8
+#define REG_NOA_PARAM_3_8821C 0x05EC
#define REG_P2P_RST_8821C 0x05F0
#define REG_SCHEDULER_RST_8821C 0x05F1
#define REG_SCH_TXCMD_8821C 0x05F8
@@ -509,18 +563,21 @@
#define REG_PS_TIMER_A_EARLY_8821C 0x1515
#define REG_PS_TIMER_B_EARLY_8821C 0x1516
#define REG_PS_TIMER_C_EARLY_8821C 0x1517
+#define REG_CPUMGQ_PARAMETER_8821C 0x1518
#define REG_WMAC_CR_8821C 0x0600
#define REG_WMAC_FWPKT_CR_8821C 0x0601
#define REG_FW_STS_FILTER_8821C 0x0602
-#define REG_BWOPMODE_8821C 0x0603
#define REG_TCR_8821C 0x0604
#define REG_RCR_8821C 0x0608
#define REG_RX_PKT_LIMIT_8821C 0x060C
#define REG_RX_DLK_TIME_8821C 0x060D
#define REG_RX_DRVINFO_SZ_8821C 0x060F
#define REG_MACID_8821C 0x0610
+#define REG_MACID_H_8821C 0x0614
#define REG_BSSID_8821C 0x0618
+#define REG_BSSID_H_8821C 0x061C
#define REG_MAR_8821C 0x0620
+#define REG_MAR_H_8821C 0x0624
#define REG_MBIDCAMCFG_1_8821C 0x0628
#define REG_MBIDCAMCFG_2_8821C 0x062C
#define REG_WMAC_TCR_TSFT_OFS_8821C 0x0630
@@ -538,17 +595,20 @@
#define REG_CTS2TO_8821C 0x0641
#define REG_EIFS_8821C 0x0642
#define REG_RPFM_MAP0_8821C 0x0644
-#define REG_RPFM_MAP1_8821C 0x0646
+#define REG_RPFM_MAP1_V1_8821C 0x0646
#define REG_RPFM_CAM_CMD_8821C 0x0648
#define REG_RPFM_CAM_RWD_8821C 0x064C
#define REG_NAV_CTRL_8821C 0x0650
#define REG_BACAMCMD_8821C 0x0654
#define REG_BACAMCONTENT_8821C 0x0658
+#define REG_BACAMCONTENT_H_8821C 0x065C
#define REG_LBDLY_8821C 0x0660
#define REG_WMAC_BACAM_RPMEN_8821C 0x0661
#define REG_TX_RX_8821C 0x0662
+#define REG_WMAC_BITMAP_CTL_8821C 0x0663
#define REG_RXERR_RPT_8821C 0x0664
#define REG_WMAC_TRXPTCL_CTL_8821C 0x0668
+#define REG_WMAC_TRXPTCL_CTL_H_8821C 0x066C
#define REG_CAMCMD_8821C 0x0670
#define REG_CAMWRITE_8821C 0x0674
#define REG_CAMREAD_8821C 0x0678
@@ -573,7 +633,7 @@
#define REG_WKFMCAM_RWD_8821C 0x069C
#define REG_RXFLTMAP0_8821C 0x06A0
#define REG_RXFLTMAP1_8821C 0x06A2
-#define REG_RXFLTMAP_8821C 0x06A4
+#define REG_RXFLTMAP2_8821C 0x06A4
#define REG_BCN_PSR_RPT_8821C 0x06A8
#define REG_FLC_RPC_8821C 0x06AC
#define REG_FLC_RPCT_8821C 0x06AD
@@ -584,35 +644,70 @@
#define REG_ERROR_MON_8821C 0x06B8
#define REG_SEARCH_MACID_8821C 0x06BC
#define REG_BT_COEX_TABLE_8821C 0x06C0
+#define REG_BT_COEX_TABLE2_8821C 0x06C4
+#define REG_BT_COEX_BREAK_TABLE_8821C 0x06C8
+#define REG_BT_COEX_TABLE_H_8821C 0x06CC
#define REG_RXCMD_0_8821C 0x06D0
#define REG_RXCMD_1_8821C 0x06D4
#define REG_WMAC_RESP_TXINFO_8821C 0x06D8
#define REG_BBPSF_CTRL_8821C 0x06DC
#define REG_P2P_RX_BCN_NOA_8821C 0x06E0
#define REG_ASSOCIATED_BFMER0_INFO_8821C 0x06E4
+#define REG_ASSOCIATED_BFMER0_INFO_H_8821C 0x06E8
#define REG_ASSOCIATED_BFMER1_INFO_8821C 0x06EC
+#define REG_ASSOCIATED_BFMER1_INFO_H_8821C 0x06F0
#define REG_TX_CSI_RPT_PARAM_BW20_8821C 0x06F4
#define REG_TX_CSI_RPT_PARAM_BW40_8821C 0x06F8
-#define REG_TX_CSI_RPT_PARAM_BW80_8821C 0x06FC
#define REG_BCN_PSR_RPT2_8821C 0x1600
#define REG_BCN_PSR_RPT3_8821C 0x1604
#define REG_BCN_PSR_RPT4_8821C 0x1608
#define REG_A1_ADDR_MASK_8821C 0x160C
#define REG_MACID2_8821C 0x1620
+#define REG_MACID2_H_8821C 0x1624
#define REG_BSSID2_8821C 0x1628
+#define REG_BSSID2_H_8821C 0x162C
#define REG_MACID3_8821C 0x1630
+#define REG_MACID3_H_8821C 0x1634
#define REG_BSSID3_8821C 0x1638
+#define REG_BSSID3_H_8821C 0x163C
#define REG_MACID4_8821C 0x1640
+#define REG_MACID4_H_8821C 0x1644
#define REG_BSSID4_8821C 0x1648
+#define REG_BSSID4_H_8821C 0x164C
#define REG_NOA_REPORT_8821C 0x1650
+#define REG_NOA_REPORT_1_8821C 0x1654
+#define REG_NOA_REPORT_2_8821C 0x1658
+#define REG_NOA_REPORT_3_8821C 0x165C
#define REG_PWRBIT_SETTING_8821C 0x1660
+#define REG_MU_BF_OPTION_8821C 0x167C
+#define REG_WMAC_PAUSE_BB_CLR_TH_8821C 0x167D
+#define REG_WMAC_MU_ARB_8821C 0x167E
+#define REG_WMAC_MU_OPTION_8821C 0x167F
+#define REG_WMAC_MU_BF_CTL_8821C 0x1680
+#define REG_WMAC_MU_BFRPT_PARA_8821C 0x1682
+#define REG_WMAC_ASSOCIATED_MU_BFMEE2_8821C 0x1684
+#define REG_WMAC_ASSOCIATED_MU_BFMEE3_8821C 0x1686
+#define REG_WMAC_ASSOCIATED_MU_BFMEE4_8821C 0x1688
+#define REG_WMAC_ASSOCIATED_MU_BFMEE5_8821C 0x168A
+#define REG_WMAC_ASSOCIATED_MU_BFMEE6_8821C 0x168C
+#define REG_WMAC_ASSOCIATED_MU_BFMEE7_8821C 0x168E
+#define REG_WMAC_BB_STOP_RX_COUNTER_8821C 0x1690
+#define REG_WMAC_PLCP_MONITOR_8821C 0x1694
+#define REG_WMAC_PLCP_MONITOR_MUTX_8821C 0x1698
#define REG_TRANSMIT_ADDRSS_0_8821C 0x16A0
+#define REG_TRANSMIT_ADDRSS_0_H_8821C 0x16A4
#define REG_TRANSMIT_ADDRSS_1_8821C 0x16A8
+#define REG_TRANSMIT_ADDRSS_1_H_8821C 0x16AC
#define REG_TRANSMIT_ADDRSS_2_8821C 0x16B0
+#define REG_TRANSMIT_ADDRSS_2_H_8821C 0x16B4
#define REG_TRANSMIT_ADDRSS_3_8821C 0x16B8
+#define REG_TRANSMIT_ADDRSS_3_H_8821C 0x16BC
#define REG_TRANSMIT_ADDRSS_4_8821C 0x16C0
+#define REG_TRANSMIT_ADDRSS_4_H_8821C 0x16C4
#define REG_MACID1_8821C 0x0700
+#define REG_MACID1_1_8821C 0x0704
#define REG_BSSID1_8821C 0x0708
+#define REG_BSSID1_1_8821C 0x070C
#define REG_BCN_PSR_RPT1_8821C 0x0710
#define REG_ASSOCIATED_BFMEE_SEL_8821C 0x0714
#define REG_SND_PTCL_CTRL_8821C 0x0718
@@ -621,18 +716,26 @@
#define REG_NS_ARP_INFO_8821C 0x0724
#define REG_BEAMFORMING_INFO_NSARP_V1_8821C 0x0728
#define REG_BEAMFORMING_INFO_NSARP_8821C 0x072C
+#define REG_IPV6_8821C 0x0730
+#define REG_IPV6_1_8821C 0x0734
+#define REG_IPV6_2_8821C 0x0738
+#define REG_IPV6_3_8821C 0x073C
#define REG_WMAC_RTX_CTX_SUBTYPE_CFG_8821C 0x0750
#define REG_WMAC_SWAES_CFG_8821C 0x0760
#define REG_BT_COEX_V2_8821C 0x0762
#define REG_BT_COEX_8821C 0x0764
#define REG_WLAN_ACT_MASK_CTRL_8821C 0x0768
+#define REG_WLAN_ACT_MASK_CTRL_1_8821C 0x076C
#define REG_BT_COEX_ENHANCED_INTR_CTRL_8821C 0x076E
#define REG_BT_ACT_STATISTICS_8821C 0x0770
+#define REG_BT_ACT_STATISTICS_1_8821C 0x0774
#define REG_BT_STATISTICS_CONTROL_REGISTER_8821C 0x0778
#define REG_BT_STATUS_REPORT_REGISTER_8821C 0x077C
#define REG_BT_INTERRUPT_CONTROL_REGISTER_8821C 0x0780
#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8821C 0x0784
#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8821C 0x0785
+#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1_8821C 0x0788
+#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2_8821C 0x078C
#define REG_BT_INTERRUPT_STATUS_REGISTER_8821C 0x078F
#define REG_BT_TDMA_TIME_REGISTER_8821C 0x0790
#define REG_BT_ACT_REGISTER_8821C 0x0794
@@ -643,18 +746,26 @@
#define REG_LTR_IDLE_LATENCY_V1_8821C 0x07A8
#define REG_LTR_ACTIVE_LATENCY_V1_8821C 0x07AC
#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_8821C 0x07B0
+#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_1_8821C 0x07B4
#define REG_WMAC_PKTCNT_RWD_8821C 0x07B8
#define REG_WMAC_PKTCNT_CTRL_8821C 0x07BC
#define REG_IQ_DUMP_8821C 0x07C0
+#define REG_IQ_DUMP_1_8821C 0x07C4
+#define REG_IQ_DUMP_2_8821C 0x07C8
#define REG_WMAC_FTM_CTL_8821C 0x07CC
#define REG_WMAC_IQ_MDPK_FUNC_8821C 0x07CE
#define REG_WMAC_OPTION_FUNCTION_8821C 0x07D0
+#define REG_WMAC_OPTION_FUNCTION_1_8821C 0x07D4
+#define REG_WMAC_OPTION_FUNCTION_2_8821C 0x07D8
#define REG_RX_FILTER_FUNCTION_8821C 0x07DA
#define REG_NDP_SIG_8821C 0x07E0
#define REG_TXCMD_INFO_FOR_RSP_PKT_8821C 0x07E4
+#define REG_TXCMD_INFO_FOR_RSP_PKT_1_8821C 0x07E8
#define REG_WSEC_OPTION_8821C 0x07EC
#define REG_RTS_ADDRESS_0_8821C 0x07F0
+#define REG_RTS_ADDRESS_0_1_8821C 0x07F4
#define REG_RTS_ADDRESS_1_8821C 0x07F8
+#define REG_RTS_ADDRESS_1_1_8821C 0x07FC
#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8821C 0x1700
#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8821C 0x1704
#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8821C 0x1708
@@ -681,10 +792,9 @@
#define REG_SDIO_RESPONSE_TIMER_8821C 0x10250088
#define REG_SDIO_CMD_CRC_8821C 0x1025008A
#define REG_SDIO_HSISR_8821C 0x10250090
-#define REG_SDIO_HSIMR_8821C 0x10250091
#define REG_SDIO_ERR_RPT_8821C 0x102500C0
-#define REG_SDIO_CMD_ERRCNT_8821C 0x102500C1
-#define REG_SDIO_DATA_ERRCNT_8821C 0x102500C2
+#define REG_SDIO_CMD_ERRCNT_8821C 0x102500C2
+#define REG_SDIO_DATA_ERRCNT_8821C 0x102500C3
#define REG_SDIO_CMD_ERR_CONTENT_8821C 0x102500C4
#define REG_SDIO_CRC_ERR_IDX_8821C 0x102500C9
#define REG_SDIO_DATA_CRC_8821C 0x102500CA
diff --git a/hal/halmac/halmac_reg_8822b.h b/hal/halmac/halmac_reg_8822b.h
index 0f9f929..e06f67e 100644
--- a/hal/halmac/halmac_reg_8822b.h
+++ b/hal/halmac/halmac_reg_8822b.h
@@ -1,3 +1,18 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
#ifndef __INC_HALMAC_REG_8822B_H
#define __INC_HALMAC_REG_8822B_H
@@ -126,6 +141,9 @@
#define REG_OSC_32K_CTRL_8822B 0x0194
#define REG_32K_CAL_REG1_8822B 0x0198
#define REG_C2HEVT_8822B 0x01A0
+#define REG_C2HEVT_1_8822B 0x01A4
+#define REG_C2HEVT_2_8822B 0x01A8
+#define REG_C2HEVT_3_8822B 0x01AC
#define REG_SW_DEFINED_PAGE1_8822B 0x01B8
#define REG_MCUTST_I_8822B 0x01C0
#define REG_MCUTST_II_8822B 0x01C4
@@ -290,6 +308,8 @@
#define REG_H2CQ_TXBD_NUM_8822B 0x1328
#define REG_H2CQ_TXBD_IDX_8822B 0x132C
#define REG_H2CQ_CSR_8822B 0x1330
+#define REG_CHANGE_PCIE_SPEED_8822B 0x1350
+#define REG_OLD_DEHANG_8822B 0x13F4
#define REG_Q0_INFO_8822B 0x0400
#define REG_Q1_INFO_8822B 0x0404
#define REG_Q2_INFO_8822B 0x0408
@@ -395,10 +415,20 @@
#define REG_MGG_FIFO_INT_8822B 0x1474
#define REG_MGG_FIFO_LIFETIME_8822B 0x1478
#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822B 0x147C
-#define REG_MACID_SHCUT_OFFSET_8822B 0x1480
+#define REG_SHCUT_SETTING_8822B 0x1480
+#define REG_SHCUT_LLC_ETH_TYPE0_8822B 0x1484
+#define REG_SHCUT_LLC_ETH_TYPE1_8822B 0x1488
+#define REG_SHCUT_LLC_OUI0_8822B 0x148C
+#define REG_SHCUT_LLC_OUI1_8822B 0x1490
+#define REG_SHCUT_LLC_OUI2_8822B 0x1494
+#define REG_SHCUT_LLC_OUI3_8822B 0x1498
+#define REG_MU_TX_CTL_8822B 0x14C0
#define REG_MU_TX_CTL_8822B 0x14C0
#define REG_MU_STA_GID_VLD_8822B 0x14C4
+#define REG_MU_STA_GID_VLD_8822B 0x14C4
#define REG_MU_STA_USER_POS_INFO_8822B 0x14C8
+#define REG_MU_STA_USER_POS_INFO_8822B 0x14C8
+#define REG_MU_TRX_DBG_CNT_8822B 0x14D0
#define REG_MU_TRX_DBG_CNT_8822B 0x14D0
#define REG_EDCA_VO_PARAM_8822B 0x0500
#define REG_EDCA_VI_PARAM_8822B 0x0504
@@ -419,7 +449,9 @@
#define REG_P2PPS_CTRL_8822B 0x0527
#define REG_PKT_LIFETIME_CTRL_8822B 0x0528
#define REG_P2PPS_SPEC_STATE_8822B 0x052B
+#define REG_TXOP_LIMIT_CTRL_8822B 0x052C
#define REG_BAR_TX_CTRL_8822B 0x0530
+#define REG_P2PON_DIS_TXTIME_8822B 0x0531
#define REG_QUEUE_INCOL_THR_8822B 0x0538
#define REG_QUEUE_INCOL_EN_8822B 0x053C
#define REG_TBTT_PROHIBIT_8822B 0x0540
@@ -511,6 +543,7 @@
#define REG_PS_TIMER_A_EARLY_8822B 0x1515
#define REG_PS_TIMER_B_EARLY_8822B 0x1516
#define REG_PS_TIMER_C_EARLY_8822B 0x1517
+#define REG_CPUMGQ_PARAMETER_8822B 0x1518
#define REG_WMAC_CR_8822B 0x0600
#define REG_WMAC_FWPKT_CR_8822B 0x0601
#define REG_BWOPMODE_8822B 0x0603
@@ -543,6 +576,7 @@
#define REG_LBDLY_8822B 0x0660
#define REG_WMAC_BACAM_RPMEN_8822B 0x0661
#define REG_TX_RX_8822B 0x0662
+#define REG_WMAC_BITMAP_CTL_8822B 0x0663
#define REG_RXERR_RPT_8822B 0x0664
#define REG_WMAC_TRXPTCL_CTL_8822B 0x0668
#define REG_CAMCMD_8822B 0x0670
@@ -569,7 +603,7 @@
#define REG_WKFMCAM_RWD_8822B 0x069C
#define REG_RXFLTMAP0_8822B 0x06A0
#define REG_RXFLTMAP1_8822B 0x06A2
-#define REG_RXFLTMAP_8822B 0x06A4
+#define REG_RXFLTMAP2_8822B 0x06A4
#define REG_BCN_PSR_RPT_8822B 0x06A8
#define REG_FLC_RPC_8822B 0x06AC
#define REG_FLC_RPCT_8822B 0x06AD
@@ -602,6 +636,17 @@
#define REG_BSSID4_8822B 0x1648
#define REG_NOA_REPORT_8822B 0x1650
#define REG_PWRBIT_SETTING_8822B 0x1660
+#define REG_WMAC_MU_BF_OPTION_8822B 0x167C
+#define REG_WMAC_MU_ARB_8822B 0x167E
+#define REG_WMAC_MU_OPTION_8822B 0x167F
+#define REG_WMAC_MU_BF_CTL_8822B 0x1680
+#define REG_WMAC_MU_BFRPT_PARA_8822B 0x1682
+#define REG_WMAC_ASSOCIATED_MU_BFMEE2_8822B 0x1684
+#define REG_WMAC_ASSOCIATED_MU_BFMEE3_8822B 0x1686
+#define REG_WMAC_ASSOCIATED_MU_BFMEE4_8822B 0x1688
+#define REG_WMAC_ASSOCIATED_MU_BFMEE5_8822B 0x168A
+#define REG_WMAC_ASSOCIATED_MU_BFMEE6_8822B 0x168C
+#define REG_WMAC_ASSOCIATED_MU_BFMEE7_8822B 0x168E
#define REG_TRANSMIT_ADDRSS_0_8822B 0x16A0
#define REG_TRANSMIT_ADDRSS_1_8822B 0x16A8
#define REG_TRANSMIT_ADDRSS_2_8822B 0x16B0
@@ -677,10 +722,9 @@
#define REG_SDIO_RESPONSE_TIMER_8822B 0x10250088
#define REG_SDIO_CMD_CRC_8822B 0x1025008A
#define REG_SDIO_HSISR_8822B 0x10250090
-#define REG_SDIO_HSIMR_8822B 0x10250091
#define REG_SDIO_ERR_RPT_8822B 0x102500C0
-#define REG_SDIO_CMD_ERRCNT_8822B 0x102500C1
-#define REG_SDIO_DATA_ERRCNT_8822B 0x102500C2
+#define REG_SDIO_CMD_ERRCNT_8822B 0x102500C2
+#define REG_SDIO_DATA_ERRCNT_8822B 0x102500C3
#define REG_SDIO_CMD_ERR_CONTENT_8822B 0x102500C4
#define REG_SDIO_CRC_ERR_IDX_8822B 0x102500C9
#define REG_SDIO_DATA_CRC_8822B 0x102500CA
diff --git a/hal/halmac/halmac_reg_8822c.h b/hal/halmac/halmac_reg_8822c.h
new file mode 100644
index 0000000..b71418f
--- /dev/null
+++ b/hal/halmac/halmac_reg_8822c.h
@@ -0,0 +1,875 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef __INC_HALMAC_REG_8822C_H
+#define __INC_HALMAC_REG_8822C_H
+
+#define REG_SYS_ISO_CTRL_8822C 0x0000
+#define REG_SYS_FUNC_EN_8822C 0x0002
+#define REG_SYS_PW_CTRL_8822C 0x0004
+#define REG_SYS_CLK_CTRL_8822C 0x0008
+#define REG_SYS_EEPROM_CTRL_8822C 0x000A
+#define REG_EE_VPD_8822C 0x000C
+#define REG_SYS_SWR_CTRL1_8822C 0x0010
+#define REG_SYS_SWR_CTRL2_8822C 0x0014
+#define REG_SYS_SWR_CTRL3_8822C 0x0018
+#define REG_RSV_CTRL_8822C 0x001C
+#define REG_RF_CTRL_8822C 0x001F
+#define REG_AFE_LDO_CTRL_8822C 0x0020
+#define REG_AFE_CTRL1_8822C 0x0024
+#define REG_ANAPARSW_POW_MAC_8822C 0x0028
+#define REG_ANAPARLDO_POW_MAC_8822C 0x0029
+#define REG_ANAPAR_POW_MAC_8822C 0x002A
+#define REG_ANAPAR_POW_XTAL_8822C 0x002B
+#define REG_ANAPARLDO_MAC_8822C 0x002C
+#define REG_EFUSE_CTRL_8822C 0x0030
+#define REG_LDO_EFUSE_CTRL_8822C 0x0034
+#define REG_PWR_OPTION_CTRL_8822C 0x0038
+#define REG_CAL_TIMER_8822C 0x003C
+#define REG_ACLK_MON_8822C 0x003E
+#define REG_GPIO_MUXCFG_2_8822C 0x003F
+#define REG_GPIO_MUXCFG_8822C 0x0040
+#define REG_GPIO_PIN_CTRL_8822C 0x0044
+#define REG_GPIO_INTM_8822C 0x0048
+#define REG_LED_CFG_8822C 0x004C
+#define REG_FSIMR_8822C 0x0050
+#define REG_FSISR_8822C 0x0054
+#define REG_HSIMR_8822C 0x0058
+#define REG_HSISR_8822C 0x005C
+#define REG_GPIO_EXT_CTRL_8822C 0x0060
+#define REG_PAD_CTRL1_8822C 0x0064
+#define REG_WL_BT_PWR_CTRL_8822C 0x0068
+#define REG_SDM_DEBUG_8822C 0x006C
+#define REG_SYS_SDIO_CTRL_8822C 0x0070
+#define REG_HCI_OPT_CTRL_8822C 0x0074
+#define REG_HCI_BG_CTRL_8822C 0x0078
+#define REG_HCI_LDO_CTRL_8822C 0x007A
+#define REG_LDO_SWR_CTRL_8822C 0x007C
+#define REG_MCUFW_CTRL_8822C 0x0080
+#define REG_MCU_TST_CFG_8822C 0x0084
+#define REG_HMEBOX_E0_E1_8822C 0x0088
+#define REG_HMEBOX_E2_E3_8822C 0x008C
+#define REG_WLLPS_CTRL_8822C 0x0090
+#define REG_GPIO_DEBOUNCE_CTRL_8822C 0x0098
+#define REG_RPWM2_8822C 0x009C
+#define REG_SYSON_FSM_MON_8822C 0x00A0
+#define REG_PMC_DBG_CTRL1_8822C 0x00A8
+#define REG_HIMR0_8822C 0x00B0
+#define REG_HISR0_8822C 0x00B4
+#define REG_HIMR1_8822C 0x00B8
+#define REG_HISR1_8822C 0x00BC
+#define REG_DBG_PORT_SEL_8822C 0x00C0
+#define REG_PAD_CTRL2_8822C 0x00C4
+#define REG_PMC_DBG_CTRL2_8822C 0x00CC
+#define REG_BIST_CTRL_8822C 0x00D0
+#define REG_BIST_RPT_8822C 0x00D4
+#define REG_MEM_CTRL_8822C 0x00D8
+#define REG_USB_SIE_INTF_8822C 0x00E0
+#define REG_PCIE_MIO_INTF_8822C 0x00E4
+#define REG_PCIE_MIO_INTD_8822C 0x00E8
+#define REG_WLRF1_8822C 0x00EC
+#define REG_SYS_CFG1_8822C 0x00F0
+#define REG_SYS_STATUS1_8822C 0x00F4
+#define REG_SYS_STATUS2_8822C 0x00F8
+#define REG_SYS_CFG2_8822C 0x00FC
+#define REG_SYS_CFG3_8822C 0x1000
+#define REG_ANAPARSW_MAC_0_8822C 0x1010
+#define REG_ANAPARSW_MAC_1_8822C 0x1014
+#define REG_ANAPAR_MAC_0_8822C 0x1018
+#define REG_ANAPAR_MAC_1_8822C 0x101C
+#define REG_ANAPAR_MAC_2_8822C 0x1020
+#define REG_ANAPAR_XTAL_0_8822C 0x1040
+#define REG_ANAPAR_XTAL_1_8822C 0x1044
+#define REG_ANAPAR_XTAL_2_8822C 0x1048
+#define REG_ANAPAR_XTAL_3_8822C 0x104C
+#define REG_ANAPAR_XTAL_AACK_0_8822C 0x1054
+#define REG_ANAPAR_XTAL_AACK_1_8822C 0x1058
+#define REG_ANAPAR_XTAL_MODE_DECODER_8822C 0x1064
+#define REG_SYS_CFG5_8822C 0x1070
+#define REG_CPU_DMEM_CON_8822C 0x1080
+#define REG_BOOT_REASON_8822C 0x1088
+#define REG_HIMR2_8822C 0x10B0
+#define REG_HISR2_8822C 0x10B4
+#define REG_HIMR3_8822C 0x10B8
+#define REG_HISR3_8822C 0x10BC
+#define REG_SW_MDIO_8822C 0x10C0
+#define REG_H2C_PKT_READADDR_8822C 0x10D0
+#define REG_H2C_PKT_WRITEADDR_8822C 0x10D4
+#define REG_MEM_PWR_CRTL_8822C 0x10D8
+#define REG_FW_DBG6_8822C 0x10F8
+#define REG_FW_DBG7_8822C 0x10FC
+#define REG_CR_8822C 0x0100
+#define REG_PG_SIZE_8822C 0x0104
+#define REG_PKT_BUFF_ACCESS_CTRL_8822C 0x0106
+#define REG_TSF_CLK_STATE_8822C 0x0108
+#define REG_TXDMA_PQ_MAP_8822C 0x010C
+#define REG_TRXFF_BNDY_8822C 0x0114
+#define REG_PTA_I2C_MBOX_8822C 0x0118
+#define REG_RXFF_BNDY_8822C 0x011C
+#define REG_FE1IMR_8822C 0x0120
+#define REG_FE1ISR_8822C 0x0124
+#define REG_CPWM_8822C 0x012C
+#define REG_FWIMR_8822C 0x0130
+#define REG_FWISR_8822C 0x0134
+#define REG_FTIMR_8822C 0x0138
+#define REG_FTISR_8822C 0x013C
+#define REG_PKTBUF_DBG_CTRL_8822C 0x0140
+#define REG_PKTBUF_DBG_DATA_L_8822C 0x0144
+#define REG_PKTBUF_DBG_DATA_H_8822C 0x0148
+#define REG_CPWM2_8822C 0x014C
+#define REG_TC0_CTRL_8822C 0x0150
+#define REG_TC1_CTRL_8822C 0x0154
+#define REG_TC2_CTRL_8822C 0x0158
+#define REG_TC3_CTRL_8822C 0x015C
+#define REG_TC4_CTRL_8822C 0x0160
+#define REG_TCUNIT_BASE_8822C 0x0164
+#define REG_TC5_CTRL_8822C 0x0168
+#define REG_TC6_CTRL_8822C 0x016C
+#define REG_MBIST_DRF_FAIL_8822C 0x0170
+#define REG_MBIST_START_PAUSE_8822C 0x0174
+#define REG_MBIST_DONE_8822C 0x0178
+#define REG_MBIST_READ_BIST_RPT_8822C 0x017C
+#define REG_AES_DECRPT_DATA_8822C 0x0180
+#define REG_AES_DECRPT_CFG_8822C 0x0184
+#define REG_HIOE_CTRL_8822C 0x0188
+#define REG_HIOE_CFG_FILE_8822C 0x018C
+#define REG_TMETER_8822C 0x0190
+#define REG_OSC_32K_CTRL_8822C 0x0194
+#define REG_32K_CAL_REG1_8822C 0x0198
+#define REG_C2HEVT_8822C 0x01A0
+#define REG_C2HEVT_1_8822C 0x01A4
+#define REG_C2HEVT_2_8822C 0x01A8
+#define REG_C2HEVT_3_8822C 0x01AC
+#define REG_SW_DEFINED_PAGE1_8822C 0x01B8
+#define REG_SW_DEFINED_PAGE2_8822C 0x01BC
+#define REG_MCUTST_I_8822C 0x01C0
+#define REG_MCUTST_II_8822C 0x01C4
+#define REG_FMETHR_8822C 0x01C8
+#define REG_HMETFR_8822C 0x01CC
+#define REG_HMEBOX0_8822C 0x01D0
+#define REG_HMEBOX1_8822C 0x01D4
+#define REG_HMEBOX2_8822C 0x01D8
+#define REG_HMEBOX3_8822C 0x01DC
+#define REG_BB_ACCESS_CTRL_8822C 0x01E8
+#define REG_BB_ACCESS_DATA_8822C 0x01EC
+#define REG_HMEBOX_E0_8822C 0x01F0
+#define REG_HMEBOX_E1_8822C 0x01F4
+#define REG_HMEBOX_E2_8822C 0x01F8
+#define REG_HMEBOX_E3_8822C 0x01FC
+#define REG_CR_EXT_8822C 0x1100
+#define REG_FWFF_8822C 0x1114
+#define REG_RXFF_PTR_V1_8822C 0x1118
+#define REG_RXFF_WTR_V1_8822C 0x111C
+#define REG_FE2IMR_8822C 0x1120
+#define REG_FE2ISR_8822C 0x1124
+#define REG_FE3IMR_8822C 0x1128
+#define REG_FE3ISR_8822C 0x112C
+#define REG_FE4IMR_8822C 0x1130
+#define REG_FE4ISR_8822C 0x1134
+#define REG_FT1IMR_8822C 0x1138
+#define REG_FT1ISR_8822C 0x113C
+#define REG_SPWR0_8822C 0x1140
+#define REG_SPWR1_8822C 0x1144
+#define REG_SPWR2_8822C 0x1148
+#define REG_SPWR3_8822C 0x114C
+#define REG_POWSEQ_8822C 0x1150
+#define REG_TC7_CTRL_V1_8822C 0x1158
+#define REG_TC8_CTRL_V1_8822C 0x115C
+#define REG_RX_BCN_TBTT_ITVL0_8822C 0x1160
+#define REG_RX_BCN_TBTT_ITVL1_8822C 0x1164
+#define REG_IO_WRAP_ERR_FLAG_8822C 0x1170
+#define REG_SPEED_SENSOR_8822C 0x1180
+#define REG_SPEED_SENSOR1_8822C 0x1184
+#define REG_SPEED_SENSOR2_8822C 0x1188
+#define REG_SPEED_SENSOR3_8822C 0x118C
+#define REG_SPEED_SENSOR4_8822C 0x1190
+#define REG_SPEED_SENSOR5_8822C 0x1194
+#define REG_COUNTER_CTRL_8822C 0x11C4
+#define REG_COUNTER_THRESHOLD_8822C 0x11C8
+#define REG_COUNTER_SET_8822C 0x11CC
+#define REG_COUNTER_OVERFLOW_8822C 0x11D0
+#define REG_TXDMA_LEN_THRESHOLD_8822C 0x11D4
+#define REG_RXDMA_LEN_THRESHOLD_8822C 0x11D8
+#define REG_PCIE_EXEC_TIME_THRESHOLD_8822C 0x11DC
+#define REG_FT2IMR_8822C 0x11E0
+#define REG_FT2ISR_8822C 0x11E4
+#define REG_MSG2_8822C 0x11F0
+#define REG_MSG3_8822C 0x11F4
+#define REG_MSG4_8822C 0x11F8
+#define REG_MSG5_8822C 0x11FC
+#define REG_FIFOPAGE_CTRL_1_8822C 0x0200
+#define REG_FIFOPAGE_CTRL_2_8822C 0x0204
+#define REG_AUTO_LLT_V1_8822C 0x0208
+#define REG_TXDMA_OFFSET_CHK_8822C 0x020C
+#define REG_TXDMA_STATUS_8822C 0x0210
+#define REG_TX_DMA_DBG_8822C 0x0214
+#define REG_TQPNT1_8822C 0x0218
+#define REG_TQPNT2_8822C 0x021C
+#define REG_TQPNT3_8822C 0x0220
+#define REG_TQPNT4_8822C 0x0224
+#define REG_RQPN_CTRL_1_8822C 0x0228
+#define REG_RQPN_CTRL_2_8822C 0x022C
+#define REG_FIFOPAGE_INFO_1_8822C 0x0230
+#define REG_FIFOPAGE_INFO_2_8822C 0x0234
+#define REG_FIFOPAGE_INFO_3_8822C 0x0238
+#define REG_FIFOPAGE_INFO_4_8822C 0x023C
+#define REG_FIFOPAGE_INFO_5_8822C 0x0240
+#define REG_H2C_HEAD_8822C 0x0244
+#define REG_H2C_TAIL_8822C 0x0248
+#define REG_H2C_READ_ADDR_8822C 0x024C
+#define REG_H2C_WR_ADDR_8822C 0x0250
+#define REG_H2C_INFO_8822C 0x0254
+#define REG_PGSUB_CNT_8822C 0x026C
+#define REG_PGSUB_H_8822C 0x0270
+#define REG_PGSUB_N_8822C 0x0274
+#define REG_PGSUB_L_8822C 0x0278
+#define REG_PGSUB_E_8822C 0x027C
+#define REG_RXDMA_AGG_PG_TH_8822C 0x0280
+#define REG_RXPKT_NUM_8822C 0x0284
+#define REG_RXDMA_STATUS_8822C 0x0288
+#define REG_RXDMA_DPR_8822C 0x028C
+#define REG_RXDMA_MODE_8822C 0x0290
+#define REG_C2H_PKT_8822C 0x0294
+#define REG_FWFF_C2H_8822C 0x0298
+#define REG_FWFF_CTRL_8822C 0x029C
+#define REG_FWFF_PKT_INFO_8822C 0x02A0
+#define REG_RXPKTNUM_8822C 0x02B0
+#define REG_RXPKTNUM_TH_8822C 0x02B4
+#define REG_FW_MSG1_8822C 0x02E0
+#define REG_FW_MSG2_8822C 0x02E4
+#define REG_FW_MSG3_8822C 0x02E8
+#define REG_FW_MSG4_8822C 0x02EC
+#define REG_DDMA_CH0SA_8822C 0x1200
+#define REG_DDMA_CH0DA_8822C 0x1204
+#define REG_DDMA_CH0CTRL_8822C 0x1208
+#define REG_DDMA_CH1SA_8822C 0x1210
+#define REG_DDMA_CH1DA_8822C 0x1214
+#define REG_DDMA_CH1CTRL_8822C 0x1218
+#define REG_DDMA_CH2SA_8822C 0x1220
+#define REG_DDMA_CH2DA_8822C 0x1224
+#define REG_DDMA_CH2CTRL_8822C 0x1228
+#define REG_DDMA_CH3SA_8822C 0x1230
+#define REG_DDMA_CH3DA_8822C 0x1234
+#define REG_DDMA_CH3CTRL_8822C 0x1238
+#define REG_DDMA_CH4SA_8822C 0x1240
+#define REG_DDMA_CH4DA_8822C 0x1244
+#define REG_DDMA_CH4CTRL_8822C 0x1248
+#define REG_DDMA_CH5SA_8822C 0x1250
+#define REG_DDMA_CH5DA_8822C 0x1254
+#define REG_DDMA_CH5CTRL_8822C 0x1258
+#define REG_DDMA_INT_MSK_8822C 0x12E0
+#define REG_DDMA_CHSTATUS_8822C 0x12E8
+#define REG_DDMA_CHKSUM_8822C 0x12F0
+#define REG_DDMA_MONITOR_8822C 0x12FC
+#define REG_PCIE_CTRL_8822C 0x0300
+#define REG_INT_MIG_8822C 0x0304
+#define REG_BCNQ_TXBD_DESA_8822C 0x0308
+#define REG_MGQ_TXBD_DESA_8822C 0x0310
+#define REG_VOQ_TXBD_DESA_8822C 0x0318
+#define REG_VIQ_TXBD_DESA_8822C 0x0320
+#define REG_BEQ_TXBD_DESA_8822C 0x0328
+#define REG_BKQ_TXBD_DESA_8822C 0x0330
+#define REG_RXQ_RXBD_DESA_8822C 0x0338
+#define REG_HI0Q_TXBD_DESA_8822C 0x0340
+#define REG_HI1Q_TXBD_DESA_8822C 0x0348
+#define REG_HI2Q_TXBD_DESA_8822C 0x0350
+#define REG_HI3Q_TXBD_DESA_8822C 0x0358
+#define REG_HI4Q_TXBD_DESA_8822C 0x0360
+#define REG_HI5Q_TXBD_DESA_8822C 0x0368
+#define REG_HI6Q_TXBD_DESA_8822C 0x0370
+#define REG_HI7Q_TXBD_DESA_8822C 0x0378
+#define REG_MGQ_TXBD_NUM_8822C 0x0380
+#define REG_RX_RXBD_NUM_8822C 0x0382
+#define REG_VOQ_TXBD_NUM_8822C 0x0384
+#define REG_VIQ_TXBD_NUM_8822C 0x0386
+#define REG_BEQ_TXBD_NUM_8822C 0x0388
+#define REG_BKQ_TXBD_NUM_8822C 0x038A
+#define REG_HI0Q_TXBD_NUM_8822C 0x038C
+#define REG_HI1Q_TXBD_NUM_8822C 0x038E
+#define REG_HI2Q_TXBD_NUM_8822C 0x0390
+#define REG_HI3Q_TXBD_NUM_8822C 0x0392
+#define REG_HI4Q_TXBD_NUM_8822C 0x0394
+#define REG_HI5Q_TXBD_NUM_8822C 0x0396
+#define REG_HI6Q_TXBD_NUM_8822C 0x0398
+#define REG_HI7Q_TXBD_NUM_8822C 0x039A
+#define REG_TSFTIMER_HCI_8822C 0x039C
+#define REG_BD_RWPTR_CLR_8822C 0x039C
+#define REG_VOQ_TXBD_IDX_8822C 0x03A0
+#define REG_VIQ_TXBD_IDX_8822C 0x03A4
+#define REG_BEQ_TXBD_IDX_8822C 0x03A8
+#define REG_BKQ_TXBD_IDX_8822C 0x03AC
+#define REG_MGQ_TXBD_IDX_8822C 0x03B0
+#define REG_RXQ_RXBD_IDX_8822C 0x03B4
+#define REG_HI0Q_TXBD_IDX_8822C 0x03B8
+#define REG_HI1Q_TXBD_IDX_8822C 0x03BC
+#define REG_HI2Q_TXBD_IDX_8822C 0x03C0
+#define REG_HI3Q_TXBD_IDX_8822C 0x03C4
+#define REG_HI4Q_TXBD_IDX_8822C 0x03C8
+#define REG_HI5Q_TXBD_IDX_8822C 0x03CC
+#define REG_HI6Q_TXBD_IDX_8822C 0x03D0
+#define REG_HI7Q_TXBD_IDX_8822C 0x03D4
+#define REG_DBG_SEL_V1_8822C 0x03D8
+#define REG_PCIE_HRPWM1_V1_8822C 0x03D9
+#define REG_PCIE_HCPWM1_V1_8822C 0x03DA
+#define REG_PCIE_CTRL2_8822C 0x03DB
+#define REG_PCIE_HRPWM2_V1_8822C 0x03DC
+#define REG_PCIE_HCPWM2_V1_8822C 0x03DE
+#define REG_PCIE_H2C_MSG_V1_8822C 0x03E0
+#define REG_PCIE_C2H_MSG_V1_8822C 0x03E4
+#define REG_DBI_WDATA_V1_8822C 0x03E8
+#define REG_DBI_RDATA_V1_8822C 0x03EC
+#define REG_DBI_FLAG_V1_8822C 0x03F0
+#define REG_MDIO_V1_8822C 0x03F4
+#define REG_PCIE_MIX_CFG_8822C 0x03F8
+#define REG_HCI_MIX_CFG_8822C 0x03FC
+#define REG_STC_INT_CS_8822C 0x1300
+#define REG_ST_INT_CFG_8822C 0x1304
+#define REG_H2CQ_TXBD_DESA_8822C 0x1320
+#define REG_H2CQ_TXBD_NUM_8822C 0x1328
+#define REG_H2CQ_TXBD_IDX_8822C 0x132C
+#define REG_H2CQ_CSR_8822C 0x1330
+#define REG_CHANGE_PCIE_SPEED_8822C 0x1350
+#define REG_DEBUG_STATE1_8822C 0x1354
+#define REG_DEBUG_STATE2_8822C 0x1358
+#define REG_DEBUG_STATE3_8822C 0x135C
+#define REG_CHNL_DMA_CFG_V1_8822C 0x137C
+#define REG_PCIE_HISR0_V1_8822C 0x13B4
+#define REG_PCIE_HISR1_V1_8822C 0x13BC
+#define REG_PCIE_HISR2_V1_8822C 0x23B4
+#define REG_PCIE_HISR3_V1_8822C 0x23BC
+#define REG_Q0_INFO_8822C 0x0400
+#define REG_Q1_INFO_8822C 0x0404
+#define REG_Q2_INFO_8822C 0x0408
+#define REG_Q3_INFO_8822C 0x040C
+#define REG_MGQ_INFO_8822C 0x0410
+#define REG_HIQ_INFO_8822C 0x0414
+#define REG_BCNQ_INFO_8822C 0x0418
+#define REG_TXPKT_EMPTY_8822C 0x041A
+#define REG_CPU_MGQ_INFO_8822C 0x041C
+#define REG_FWHW_TXQ_CTRL_8822C 0x0420
+#define REG_DATAFB_SEL_8822C 0x0423
+#define REG_BCNQ_BDNY_V1_8822C 0x0424
+#define REG_LIFETIME_EN_8822C 0x0426
+#define REG_SPEC_SIFS_8822C 0x0428
+#define REG_RETRY_LIMIT_8822C 0x042A
+#define REG_TXBF_CTRL_8822C 0x042C
+#define REG_DARFRC_8822C 0x0430
+#define REG_DARFRCH_8822C 0x0434
+#define REG_RARFRC_8822C 0x0438
+#define REG_RARFRCH_8822C 0x043C
+#define REG_RRSR_8822C 0x0440
+#define REG_ARFR0_8822C 0x0444
+#define REG_ARFRH0_8822C 0x0448
+#define REG_ARFR1_V1_8822C 0x044C
+#define REG_ARFRH1_V1_8822C 0x0450
+#define REG_CCK_CHECK_8822C 0x0454
+#define REG_AMPDU_MAX_TIME_V1_8822C 0x0455
+#define REG_BCNQ1_BDNY_V1_8822C 0x0456
+#define REG_AMPDU_MAX_LENGTH_HT_8822C 0x0458
+#define REG_ACQ_STOP_8822C 0x045C
+#define REG_NDPA_RATE_8822C 0x045D
+#define REG_TX_HANG_CTRL_8822C 0x045E
+#define REG_NDPA_OPT_CTRL_8822C 0x045F
+#define REG_AMPDU_MAX_LENGTH_VHT_8822C 0x0460
+#define REG_RD_RESP_PKT_TH_8822C 0x0463
+#define REG_CMDQ_INFO_8822C 0x0464
+#define REG_Q4_INFO_8822C 0x0468
+#define REG_Q5_INFO_8822C 0x046C
+#define REG_Q6_INFO_8822C 0x0470
+#define REG_Q7_INFO_8822C 0x0474
+#define REG_WMAC_LBK_BUF_HD_V1_8822C 0x0478
+#define REG_MGQ_BDNY_V1_8822C 0x047A
+#define REG_TXRPT_CTRL_8822C 0x047C
+#define REG_INIRTS_RATE_SEL_8822C 0x0480
+#define REG_BASIC_CFEND_RATE_8822C 0x0481
+#define REG_STBC_CFEND_RATE_8822C 0x0482
+#define REG_DATA_SC_8822C 0x0483
+#define REG_MACID_SLEEP3_8822C 0x0484
+#define REG_MACID_SLEEP1_8822C 0x0488
+#define REG_ARFR2_V1_8822C 0x048C
+#define REG_ARFRH2_V1_8822C 0x0490
+#define REG_ARFR3_V1_8822C 0x0494
+#define REG_ARFRH3_V1_8822C 0x0498
+#define REG_ARFR4_8822C 0x049C
+#define REG_ARFRH4_8822C 0x04A0
+#define REG_ARFR5_8822C 0x04A4
+#define REG_ARFRH5_8822C 0x04A8
+#define REG_TXRPT_START_OFFSET_8822C 0x04AC
+#define REG_POWER_STAGE1_8822C 0x04B4
+#define REG_POWER_STAGE2_8822C 0x04B8
+#define REG_SW_AMPDU_BURST_MODE_CTRL_8822C 0x04BC
+#define REG_PKT_LIFE_TIME_8822C 0x04C0
+#define REG_STBC_SETTING_8822C 0x04C4
+#define REG_STBC_SETTING2_8822C 0x04C5
+#define REG_QUEUE_CTRL_8822C 0x04C6
+#define REG_SINGLE_AMPDU_CTRL_8822C 0x04C7
+#define REG_PROT_MODE_CTRL_8822C 0x04C8
+#define REG_BAR_MODE_CTRL_8822C 0x04CC
+#define REG_RA_TRY_RATE_AGG_LMT_8822C 0x04CF
+#define REG_MACID_SLEEP2_8822C 0x04D0
+#define REG_MACID_SLEEP_8822C 0x04D4
+#define REG_HW_SEQ0_8822C 0x04D8
+#define REG_HW_SEQ1_8822C 0x04DA
+#define REG_HW_SEQ2_8822C 0x04DC
+#define REG_HW_SEQ3_8822C 0x04DE
+#define REG_NULL_PKT_STATUS_V1_8822C 0x04E0
+#define REG_PTCL_ERR_STATUS_8822C 0x04E2
+#define REG_NULL_PKT_STATUS_EXTEND_8822C 0x04E3
+#define REG_HQMGQ_DROP_8822C 0x04E4
+#define REG_PRECNT_CTRL_8822C 0x04E5
+#define REG_BT_POLLUTE_PKT_CNT_8822C 0x04E8
+#define REG_PTCL_DBG_8822C 0x04EC
+#define REG_CPUMGQ_TIMER_CTRL2_8822C 0x04F4
+#define REG_DUMMY_PAGE4_V1_8822C 0x04FC
+#define REG_MOREDATA_8822C 0x04FE
+#define REG_Q0_Q1_INFO_8822C 0x1400
+#define REG_Q2_Q3_INFO_8822C 0x1404
+#define REG_Q4_Q5_INFO_8822C 0x1408
+#define REG_Q6_Q7_INFO_8822C 0x140C
+#define REG_MGQ_HIQ_INFO_8822C 0x1410
+#define REG_CMDQ_BCNQ_INFO_8822C 0x1414
+#define REG_USEREG_SETTING_8822C 0x1420
+#define REG_AESIV_SETTING_8822C 0x1424
+#define REG_BF0_TIME_SETTING_8822C 0x1428
+#define REG_BF1_TIME_SETTING_8822C 0x142C
+#define REG_BF_TIMEOUT_EN_8822C 0x1430
+#define REG_MACID_RELEASE0_8822C 0x1434
+#define REG_MACID_RELEASE1_8822C 0x1438
+#define REG_MACID_RELEASE2_8822C 0x143C
+#define REG_MACID_RELEASE3_8822C 0x1440
+#define REG_MACID_RELEASE_SETTING_8822C 0x1444
+#define REG_FAST_EDCA_VOVI_SETTING_8822C 0x1448
+#define REG_FAST_EDCA_BEBK_SETTING_8822C 0x144C
+#define REG_MACID_DROP0_8822C 0x1450
+#define REG_MACID_DROP1_8822C 0x1454
+#define REG_MACID_DROP2_8822C 0x1458
+#define REG_MACID_DROP3_8822C 0x145C
+#define REG_R_MACID_RELEASE_SUCCESS_0_8822C 0x1460
+#define REG_R_MACID_RELEASE_SUCCESS_1_8822C 0x1464
+#define REG_R_MACID_RELEASE_SUCCESS_2_8822C 0x1468
+#define REG_R_MACID_RELEASE_SUCCESS_3_8822C 0x146C
+#define REG_MGQ_FIFO_WRITE_POINTER_8822C 0x1470
+#define REG_MGQ_FIFO_READ_POINTER_8822C 0x1472
+#define REG_MGQ_FIFO_ENABLE_8822C 0x1472
+#define REG_MGQ_FIFO_RELEASE_INT_MASK_8822C 0x1474
+#define REG_MGQ_FIFO_RELEASE_INT_FLAG_8822C 0x1476
+#define REG_MGQ_FIFO_VALID_MAP_8822C 0x1478
+#define REG_MGQ_FIFO_LIFETIME_8822C 0x147A
+#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8822C 0x147C
+#define REG_SHCUT_SETTING_8822C 0x1480
+#define REG_SHCUT_LLC_ETH_TYPE0_8822C 0x1484
+#define REG_SHCUT_LLC_ETH_TYPE1_8822C 0x1488
+#define REG_SHCUT_LLC_OUI0_8822C 0x148C
+#define REG_SHCUT_LLC_OUI1_8822C 0x1490
+#define REG_SHCUT_LLC_OUI2_8822C 0x1494
+#define REG_MU_TX_CTL_8822C 0x14C0
+#define REG_MU_STA_GID_VLD_8822C 0x14C4
+#define REG_MU_STA_USER_POS_INFO_8822C 0x14C8
+#define REG_MU_STA_USER_POS_INFO_H_8822C 0x14CC
+#define REG_CHNL_INFO_CTRL_8822C 0x14D0
+#define REG_CHNL_IDLE_TIME_8822C 0x14D4
+#define REG_CHNL_BUSY_TIME_8822C 0x14D8
+#define REG_MU_TRX_DBG_CNT_V1_8822C 0x14DC
+#define REG_EDCA_VO_PARAM_8822C 0x0500
+#define REG_EDCA_VI_PARAM_8822C 0x0504
+#define REG_EDCA_BE_PARAM_8822C 0x0508
+#define REG_EDCA_BK_PARAM_8822C 0x050C
+#define REG_BCNTCFG_8822C 0x0510
+#define REG_PIFS_8822C 0x0512
+#define REG_RDG_PIFS_8822C 0x0513
+#define REG_SIFS_8822C 0x0514
+#define REG_TSFTR_SYN_OFFSET_8822C 0x0518
+#define REG_AGGR_BREAK_TIME_8822C 0x051A
+#define REG_SLOT_8822C 0x051B
+#define REG_NOA_ON_ERLY_TIME_8822C 0x051C
+#define REG_NOA_OFF_ERLY_TIME_8822C 0x051D
+#define REG_TX_PTCL_CTRL_8822C 0x0520
+#define REG_TXPAUSE_8822C 0x0522
+#define REG_DIS_TXREQ_CLR_8822C 0x0523
+#define REG_RD_CTRL_8822C 0x0524
+#define REG_MBSSID_CTRL_8822C 0x0526
+#define REG_P2PPS_CTRL_8822C 0x0527
+#define REG_PKT_LIFETIME_CTRL_8822C 0x0528
+#define REG_P2PPS_SPEC_STATE_8822C 0x052B
+#define REG_TXOP_LIMIT_CTRL_8822C 0x052C
+#define REG_BAR_TX_CTRL_8822C 0x0530
+#define REG_P2PON_DIS_TXTIME_8822C 0x0531
+#define REG_CCA_TXEN_CNT_8822C 0x0534
+#define REG_MAX_INTER_COLLISION_8822C 0x0538
+#define REG_MAX_INTER_COLLISION_CNT_8822C 0x053C
+#define REG_TBTT_PROHIBIT_8822C 0x0540
+#define REG_P2PPS_STATE_8822C 0x0543
+#define REG_RD_NAV_NXT_8822C 0x0544
+#define REG_NAV_PROT_LEN_8822C 0x0546
+#define REG_FTM_PTT_8822C 0x0548
+#define REG_FTM_TSF_8822C 0x054C
+#define REG_BCN_CTRL_8822C 0x0550
+#define REG_BCN_CTRL_CLINT0_8822C 0x0551
+#define REG_MBID_NUM_8822C 0x0552
+#define REG_DUAL_TSF_RST_8822C 0x0553
+#define REG_MBSSID_BCN_SPACE_8822C 0x0554
+#define REG_DRVERLYINT_8822C 0x0558
+#define REG_BCNDMATIM_8822C 0x0559
+#define REG_ATIMWND_8822C 0x055A
+#define REG_USTIME_TSF_8822C 0x055C
+#define REG_BCN_MAX_ERR_8822C 0x055D
+#define REG_RXTSF_OFFSET_CCK_8822C 0x055E
+#define REG_RXTSF_OFFSET_OFDM_8822C 0x055F
+#define REG_TSFTR_8822C 0x0560
+#define REG_TSFTR_1_8822C 0x0564
+#define REG_FREERUN_CNT_8822C 0x0568
+#define REG_FREERUN_CNT_1_8822C 0x056C
+#define REG_ATIMWND1_V1_8822C 0x0570
+#define REG_TBTT_PROHIBIT_INFRA_8822C 0x0571
+#define REG_CTWND_8822C 0x0572
+#define REG_BCNIVLCUNT_8822C 0x0573
+#define REG_BCNDROPCTRL_8822C 0x0574
+#define REG_HGQ_TIMEOUT_PERIOD_8822C 0x0575
+#define REG_TXCMD_TIMEOUT_PERIOD_8822C 0x0576
+#define REG_MISC_CTRL_8822C 0x0577
+#define REG_BCN_CTRL_CLINT1_8822C 0x0578
+#define REG_BCN_CTRL_CLINT2_8822C 0x0579
+#define REG_BCN_CTRL_CLINT3_8822C 0x057A
+#define REG_EXTEND_CTRL_8822C 0x057B
+#define REG_P2PPS1_SPEC_STATE_8822C 0x057C
+#define REG_P2PPS1_STATE_8822C 0x057D
+#define REG_P2PPS2_SPEC_STATE_8822C 0x057E
+#define REG_P2PPS2_STATE_8822C 0x057F
+#define REG_PS_TIMER0_8822C 0x0580
+#define REG_PS_TIMER1_8822C 0x0584
+#define REG_PS_TIMER2_8822C 0x0588
+#define REG_TBTT_CTN_AREA_8822C 0x058C
+#define REG_FORCE_BCN_IFS_8822C 0x058E
+#define REG_TXOP_MIN_8822C 0x0590
+#define REG_PRE_BKF_TIME_8822C 0x0592
+#define REG_CROSS_TXOP_CTRL_8822C 0x0593
+#define REG_RX_TBTT_SHIFT_V1_8822C 0x0598
+#define REG_ATIMWND2_8822C 0x05A0
+#define REG_ATIMWND3_8822C 0x05A1
+#define REG_ATIMWND4_8822C 0x05A2
+#define REG_ATIMWND5_8822C 0x05A3
+#define REG_ATIMWND6_8822C 0x05A4
+#define REG_ATIMWND7_8822C 0x05A5
+#define REG_ATIMUGT_8822C 0x05A6
+#define REG_HIQ_NO_LMT_EN_8822C 0x05A7
+#define REG_DTIM_COUNTER_ROOT_8822C 0x05A8
+#define REG_DTIM_COUNTER_VAP1_8822C 0x05A9
+#define REG_DTIM_COUNTER_VAP2_8822C 0x05AA
+#define REG_DTIM_COUNTER_VAP3_8822C 0x05AB
+#define REG_DTIM_COUNTER_VAP4_8822C 0x05AC
+#define REG_DTIM_COUNTER_VAP5_8822C 0x05AD
+#define REG_DTIM_COUNTER_VAP6_8822C 0x05AE
+#define REG_DTIM_COUNTER_VAP7_8822C 0x05AF
+#define REG_DIS_ATIM_8822C 0x05B0
+#define REG_EARLY_128US_8822C 0x05B1
+#define REG_P2PPS1_CTRL_8822C 0x05B2
+#define REG_P2PPS2_CTRL_8822C 0x05B3
+#define REG_TIMER0_SRC_SEL_8822C 0x05B4
+#define REG_NOA_UNIT_SEL_8822C 0x05B5
+#define REG_P2POFF_DIS_TXTIME_8822C 0x05B7
+#define REG_MBSSID_BCN_SPACE2_8822C 0x05B8
+#define REG_MBSSID_BCN_SPACE3_8822C 0x05BC
+#define REG_ACMHWCTRL_8822C 0x05C0
+#define REG_ACMRSTCTRL_8822C 0x05C1
+#define REG_ACMAVG_8822C 0x05C2
+#define REG_VO_ADMTIME_8822C 0x05C4
+#define REG_VI_ADMTIME_8822C 0x05C6
+#define REG_BE_ADMTIME_8822C 0x05C8
+#define REG_MAC_HEADER_NAV_OFFSET_8822C 0x05CA
+#define REG_DIS_NDPA_NAV_CHECK_8822C 0x05CB
+#define REG_EDCA_RANDOM_GEN_8822C 0x05CC
+#define REG_TXCMD_NOA_SEL_8822C 0x05CF
+#define REG_32K_CLK_SEL_8822C 0x05D0
+#define REG_EARLYINT_ADJUST_8822C 0x05D4
+#define REG_BCNERR_CNT_8822C 0x05D8
+#define REG_BCNERR_CNT_2_8822C 0x05DC
+#define REG_NOA_PARAM_8822C 0x05E0
+#define REG_NOA_PARAM_1_8822C 0x05E4
+#define REG_NOA_PARAM_2_8822C 0x05E8
+#define REG_NOA_PARAM_3_8822C 0x05EC
+#define REG_P2P_RST_8822C 0x05F0
+#define REG_SCHEDULER_RST_8822C 0x05F1
+#define REG_SCH_DBG_VALUE_8822C 0x05F4
+#define REG_SCH_TXCMD_8822C 0x05F8
+#define REG_PAGE5_DUMMY_8822C 0x05FC
+#define REG_CPUMGQ_TX_TIMER_8822C 0x1500
+#define REG_PS_TIMER_A_8822C 0x1504
+#define REG_PS_TIMER_B_8822C 0x1508
+#define REG_PS_TIMER_C_8822C 0x150C
+#define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8822C 0x1510
+#define REG_CPUMGQ_TX_TIMER_EARLY_8822C 0x1514
+#define REG_PS_TIMER_A_EARLY_8822C 0x1515
+#define REG_PS_TIMER_B_EARLY_8822C 0x1516
+#define REG_PS_TIMER_C_EARLY_8822C 0x1517
+#define REG_CPUMGQ_PARAMETER_8822C 0x1518
+#define REG_TSF_SYNC_ADJ_8822C 0x1520
+#define REG_TSF_ADJ_VLAUE_8822C 0x1524
+#define REG_TSF_ADJ_VLAUE_2_8822C 0x1528
+#define REG_P2PPS_HW_AUTO_PAUSE_CTRL_8822C 0x156C
+#define REG_P2PPS1_HW_AUTO_PAUSE_CTRL_8822C 0x1570
+#define REG_P2PPS2_HW_AUTO_PAUSE_CTRL_8822C 0x1574
+#define REG_WMAC_CR_8822C 0x0600
+#define REG_WMAC_FWPKT_CR_8822C 0x0601
+#define REG_FW_STS_FILTER_8822C 0x0602
+#define REG_TCR_8822C 0x0604
+#define REG_RCR_8822C 0x0608
+#define REG_RX_PKT_LIMIT_8822C 0x060C
+#define REG_RX_DLK_TIME_8822C 0x060D
+#define REG_RX_DRVINFO_SZ_8822C 0x060F
+#define REG_MACID_8822C 0x0610
+#define REG_MACID_H_8822C 0x0614
+#define REG_BSSID_8822C 0x0618
+#define REG_BSSID_H_8822C 0x061C
+#define REG_MAR_8822C 0x0620
+#define REG_MAR_H_8822C 0x0624
+#define REG_MBIDCAMCFG_1_8822C 0x0628
+#define REG_MBIDCAMCFG_2_8822C 0x062C
+#define REG_WMAC_TCR_TSFT_OFS_8822C 0x0630
+#define REG_UDF_THSD_8822C 0x0632
+#define REG_ZLD_NUM_8822C 0x0633
+#define REG_STMP_THSD_8822C 0x0634
+#define REG_WMAC_TXTIMEOUT_8822C 0x0635
+#define REG_USTIME_EDCA_8822C 0x0638
+#define REG_ACKTO_CCK_8822C 0x0639
+#define REG_MAC_SPEC_SIFS_8822C 0x063A
+#define REG_RESP_SIFS_CCK_8822C 0x063C
+#define REG_RESP_SIFS_OFDM_8822C 0x063E
+#define REG_ACKTO_8822C 0x0640
+#define REG_CTS2TO_8822C 0x0641
+#define REG_EIFS_8822C 0x0642
+#define REG_RPFM_MAP0_8822C 0x0644
+#define REG_RPFM_MAP1_V1_8822C 0x0646
+#define REG_RPFM_CAM_CMD_8822C 0x0648
+#define REG_RPFM_CAM_RWD_8822C 0x064C
+#define REG_NAV_CTRL_8822C 0x0650
+#define REG_BACAMCMD_8822C 0x0654
+#define REG_BACAMCONTENT_8822C 0x0658
+#define REG_BACAMCONTENT_H_8822C 0x065C
+#define REG_LBDLY_8822C 0x0660
+#define REG_WMAC_BACAM_RPMEN_8822C 0x0661
+#define REG_TX_RX_8822C 0x0662
+#define REG_WMAC_BITMAP_CTL_8822C 0x0663
+#define REG_RXERR_RPT_8822C 0x0664
+#define REG_WMAC_TRXPTCL_CTL_8822C 0x0668
+#define REG_WMAC_TRXPTCL_CTL_H_8822C 0x066C
+#define REG_CAMCMD_8822C 0x0670
+#define REG_CAMWRITE_8822C 0x0674
+#define REG_CAMREAD_8822C 0x0678
+#define REG_CAMDBG_8822C 0x067C
+#define REG_SECCFG_8822C 0x0680
+#define REG_RXFILTER_CATEGORY_1_8822C 0x0682
+#define REG_RXFILTER_ACTION_1_8822C 0x0683
+#define REG_RXFILTER_CATEGORY_2_8822C 0x0684
+#define REG_RXFILTER_ACTION_2_8822C 0x0685
+#define REG_RXFILTER_CATEGORY_3_8822C 0x0686
+#define REG_RXFILTER_ACTION_3_8822C 0x0687
+#define REG_RXFLTMAP3_8822C 0x0688
+#define REG_RXFLTMAP4_8822C 0x068A
+#define REG_RXFLTMAP5_8822C 0x068C
+#define REG_RXFLTMAP6_8822C 0x068E
+#define REG_WOW_CTRL_8822C 0x0690
+#define REG_NAN_RX_TSF_FILTER_8822C 0x0691
+#define REG_PS_RX_INFO_8822C 0x0692
+#define REG_WMMPS_UAPSD_TID_8822C 0x0693
+#define REG_LPNAV_CTRL_8822C 0x0694
+#define REG_WKFMCAM_CMD_8822C 0x0698
+#define REG_WKFMCAM_RWD_8822C 0x069C
+#define REG_RXFLTMAP0_8822C 0x06A0
+#define REG_RXFLTMAP1_8822C 0x06A2
+#define REG_RXFLTMAP2_8822C 0x06A4
+#define REG_BCN_PSR_RPT_8822C 0x06A8
+#define REG_FLC_RPC_8822C 0x06AC
+#define REG_FLC_RPCT_8822C 0x06AD
+#define REG_FLC_PTS_8822C 0x06AE
+#define REG_FLC_TRPC_8822C 0x06AF
+#define REG_RXPKTMON_CTRL_8822C 0x06B0
+#define REG_STATE_MON_8822C 0x06B4
+#define REG_ERROR_MON_8822C 0x06B8
+#define REG_SEARCH_MACID_8822C 0x06BC
+#define REG_BT_COEX_TABLE_8822C 0x06C0
+#define REG_BT_COEX_TABLE2_8822C 0x06C4
+#define REG_BT_COEX_BREAK_TABLE_8822C 0x06C8
+#define REG_BT_COEX_TABLE_H_8822C 0x06CC
+#define REG_RXCMD_0_8822C 0x06D0
+#define REG_RXCMD_1_8822C 0x06D4
+#define REG_WMAC_RESP_TXINFO_8822C 0x06D8
+#define REG_BBPSF_CTRL_8822C 0x06DC
+#define REG_P2P_RX_BCN_NOA_8822C 0x06E0
+#define REG_ASSOCIATED_BFMER0_INFO_8822C 0x06E4
+#define REG_ASSOCIATED_BFMER0_INFO_H_8822C 0x06E8
+#define REG_ASSOCIATED_BFMER1_INFO_8822C 0x06EC
+#define REG_ASSOCIATED_BFMER1_INFO_H_8822C 0x06F0
+#define REG_TX_CSI_RPT_PARAM_BW20_8822C 0x06F4
+#define REG_TX_CSI_RPT_PARAM_BW40_8822C 0x06F8
+#define REG_CSI_PTR_8822C 0x06FC
+#define REG_BCN_PSR_RPT2_8822C 0x1600
+#define REG_BCN_PSR_RPT3_8822C 0x1604
+#define REG_BCN_PSR_RPT4_8822C 0x1608
+#define REG_A1_ADDR_MASK_8822C 0x160C
+#define REG_RXPSF_CTRL_8822C 0x1610
+#define REG_RXPSF_TYPE_CTRL_8822C 0x1614
+#define REG_CAM_ACCESS_CTRL_8822C 0x1618
+#define REG_HT_SND_REF_RATE_8822C 0x161C
+#define REG_MACID2_8822C 0x1620
+#define REG_MACID2_H_8822C 0x1624
+#define REG_BSSID2_8822C 0x1628
+#define REG_BSSID2_H_8822C 0x162C
+#define REG_MACID3_8822C 0x1630
+#define REG_MACID3_H_8822C 0x1634
+#define REG_BSSID3_8822C 0x1638
+#define REG_BSSID3_H_8822C 0x163C
+#define REG_MACID4_8822C 0x1640
+#define REG_MACID4_H_8822C 0x1644
+#define REG_BSSID4_8822C 0x1648
+#define REG_BSSID4_H_8822C 0x164C
+#define REG_NOA_REPORT_8822C 0x1650
+#define REG_NOA_REPORT_1_8822C 0x1654
+#define REG_NOA_REPORT_2_8822C 0x1658
+#define REG_NOA_REPORT_3_8822C 0x165C
+#define REG_PWRBIT_SETTING_8822C 0x1660
+#define REG_GENERAL_OPTION_8822C 0x1664
+#define REG_CSI_RRSR_8822C 0x1678
+#define REG_MU_BF_OPTION_8822C 0x167C
+#define REG_WMAC_PAUSE_BB_CLR_TH_8822C 0x167D
+#define REG__WMAC_MULBK_BUF_8822C 0x167E
+#define REG_WMAC_MU_OPTION_8822C 0x167F
+#define REG_WMAC_MU_BF_CTL_8822C 0x1680
+#define REG_WMAC_MU_BFRPT_PARA_8822C 0x1682
+#define REG_WMAC_ASSOCIATED_MU_BFMEE2_8822C 0x1684
+#define REG_WMAC_ASSOCIATED_MU_BFMEE3_8822C 0x1686
+#define REG_WMAC_ASSOCIATED_MU_BFMEE4_8822C 0x1688
+#define REG_WMAC_ASSOCIATED_MU_BFMEE5_8822C 0x168A
+#define REG_WMAC_ASSOCIATED_MU_BFMEE6_8822C 0x168C
+#define REG_WMAC_ASSOCIATED_MU_BFMEE7_8822C 0x168E
+#define REG_WMAC_BB_STOP_RX_COUNTER_8822C 0x1690
+#define REG_WMAC_PLCP_MONITOR_8822C 0x1694
+#define REG_WMAC_PLCP_MONITOR_MUTX_8822C 0x1698
+#define REG_WMAC_CSIDMA_CFG_8822C 0x169C
+#define REG_TRANSMIT_ADDRSS_0_8822C 0x16A0
+#define REG_TRANSMIT_ADDRSS_0_H_8822C 0x16A4
+#define REG_TRANSMIT_ADDRSS_1_8822C 0x16A8
+#define REG_TRANSMIT_ADDRSS_1_H_8822C 0x16AC
+#define REG_TRANSMIT_ADDRSS_2_8822C 0x16B0
+#define REG_TRANSMIT_ADDRSS_2_H_8822C 0x16B4
+#define REG_TRANSMIT_ADDRSS_3_8822C 0x16B8
+#define REG_TRANSMIT_ADDRSS_3_H_8822C 0x16BC
+#define REG_TRANSMIT_ADDRSS_4_8822C 0x16C0
+#define REG_TRANSMIT_ADDRSS_4_H_8822C 0x16C4
+#define REG_MACID1_8822C 0x0700
+#define REG_MACID1_1_8822C 0x0704
+#define REG_BSSID1_8822C 0x0708
+#define REG_BSSID1_1_8822C 0x070C
+#define REG_BCN_PSR_RPT1_8822C 0x0710
+#define REG_ASSOCIATED_BFMEE_SEL_8822C 0x0714
+#define REG_SND_PTCL_CTRL_8822C 0x0718
+#define REG_RX_CSI_RPT_INFO_8822C 0x071C
+#define REG_NS_ARP_CTRL_8822C 0x0720
+#define REG_NS_ARP_INFO_8822C 0x0724
+#define REG_BEAMFORMING_INFO_NSARP_V1_8822C 0x0728
+#define REG_BEAMFORMING_INFO_NSARP_8822C 0x072C
+#define REG_IPV6_8822C 0x0730
+#define REG_IPV6_1_8822C 0x0734
+#define REG_IPV6_2_8822C 0x0738
+#define REG_IPV6_3_8822C 0x073C
+#define REG_WMAC_RTX_CTX_SUBTYPE_CFG_8822C 0x0750
+#define REG_WMAC_SWAES_DIO_B63_B32_8822C 0x0754
+#define REG_WMAC_SWAES_DIO_B95_B64_8822C 0x0758
+#define REG_WMAC_SWAES_DIO_B127_B96_8822C 0x075C
+#define REG_WMAC_SWAES_CFG_8822C 0x0760
+#define REG_BT_COEX_V2_8822C 0x0762
+#define REG_BT_COEX_8822C 0x0764
+#define REG_WLAN_ACT_MASK_CTRL_8822C 0x0768
+#define REG_WLAN_ACT_MASK_CTRL_1_8822C 0x076C
+#define REG_BT_COEX_ENHANCED_INTR_CTRL_8822C 0x076E
+#define REG_BT_ACT_STATISTICS_8822C 0x0770
+#define REG_BT_ACT_STATISTICS_1_8822C 0x0774
+#define REG_BT_STATISTICS_CONTROL_REGISTER_8822C 0x0778
+#define REG_BT_STATUS_REPORT_REGISTER_8822C 0x077C
+#define REG_BT_INTERRUPT_CONTROL_REGISTER_8822C 0x0780
+#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8822C 0x0784
+#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8822C 0x0785
+#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1_8822C 0x0788
+#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2_8822C 0x078C
+#define REG_BT_INTERRUPT_STATUS_REGISTER_8822C 0x078F
+#define REG_BT_TDMA_TIME_REGISTER_8822C 0x0790
+#define REG_BT_ACT_REGISTER_8822C 0x0794
+#define REG_OBFF_CTRL_BASIC_8822C 0x0798
+#define REG_OBFF_CTRL2_TIMER_8822C 0x079C
+#define REG_LTR_CTRL_BASIC_8822C 0x07A0
+#define REG_LTR_CTRL2_TIMER_THRESHOLD_8822C 0x07A4
+#define REG_LTR_IDLE_LATENCY_V1_8822C 0x07A8
+#define REG_LTR_ACTIVE_LATENCY_V1_8822C 0x07AC
+#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_8822C 0x07B0
+#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_1_8822C 0x07B4
+#define REG_WMAC_PKTCNT_RWD_8822C 0x07B8
+#define REG_WMAC_PKTCNT_CTRL_8822C 0x07BC
+#define REG_IQ_DUMP_8822C 0x07C0
+#define REG_IQ_DUMP_1_8822C 0x07C4
+#define REG_IQ_DUMP_2_8822C 0x07C8
+#define REG_WMAC_FTM_CTL_8822C 0x07CC
+#define REG_WMAC_IQ_MDPK_FUNC_8822C 0x07CE
+#define REG_WMAC_OPTION_FUNCTION_8822C 0x07D0
+#define REG_WMAC_OPTION_FUNCTION_1_8822C 0x07D4
+#define REG_WMAC_OPTION_FUNCTION_2_8822C 0x07D8
+#define REG_RX_FILTER_FUNCTION_8822C 0x07DA
+#define REG_NDP_SIG_8822C 0x07E0
+#define REG_TXCMD_INFO_FOR_RSP_PKT_8822C 0x07E4
+#define REG_TXCMD_INFO_FOR_RSP_PKT_1_8822C 0x07E8
+#define REG_WSEC_OPTION_8822C 0x07EC
+#define REG_RTS_ADDRESS_0_8822C 0x07F0
+#define REG_RTS_ADDRESS_0_1_8822C 0x07F4
+#define REG_RTS_ADDRESS_1_8822C 0x07F8
+#define REG_RTS_ADDRESS_1_1_8822C 0x07FC
+#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8822C 0x1700
+#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8822C 0x1704
+#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8822C 0x1708
+#define REG_SDIO_TX_CTRL_8822C 0x10250000
+#define REG_SDIO_CMD11_VOL_SWITCH_8822C 0x10250004
+#define REG_SDIO_DRIVING_8822C 0x10250006
+#define REG_SDIO_MONITOR_8822C 0x10250008
+#define REG_SDIO_MONITOR_2_8822C 0x1025000C
+#define REG_SDIO_HIMR_8822C 0x10250014
+#define REG_SDIO_HISR_8822C 0x10250018
+#define REG_SDIO_RX_REQ_LEN_8822C 0x1025001C
+#define REG_SDIO_FREE_TXPG_SEQ_V1_8822C 0x1025001F
+#define REG_SDIO_FREE_TXPG_8822C 0x10250020
+#define REG_SDIO_FREE_TXPG2_8822C 0x10250024
+#define REG_SDIO_OQT_FREE_TXPG_V1_8822C 0x10250028
+#define REG_SDIO_TXPKT_EMPTY_8822C 0x1025002C
+#define REG_SDIO_HTSFR_INFO_8822C 0x10250030
+#define REG_SDIO_HCPWM1_V2_8822C 0x10250038
+#define REG_SDIO_HCPWM2_V2_8822C 0x1025003A
+#define REG_SDIO_INDIRECT_REG_CFG_8822C 0x10250040
+#define REG_SDIO_INDIRECT_REG_DATA_8822C 0x10250044
+#define REG_SDIO_H2C_8822C 0x10250060
+#define REG_SDIO_C2H_8822C 0x10250064
+#define REG_SDIO_HRPWM1_8822C 0x10250080
+#define REG_SDIO_HRPWM2_8822C 0x10250082
+#define REG_SDIO_HPS_CLKR_8822C 0x10250084
+#define REG_SDIO_BUS_CTRL_8822C 0x10250085
+#define REG_SDIO_HSUS_CTRL_8822C 0x10250086
+#define REG_SDIO_RESPONSE_TIMER_8822C 0x10250088
+#define REG_SDIO_CMD_CRC_8822C 0x1025008A
+#define REG_SDIO_HSISR_8822C 0x10250090
+#define REG_SDIO_HSIMR_8822C 0x10250091
+#define REG_SDIO_DIOERR_RPT_8822C 0x102500C0
+#define REG_SDIO_CMD_ERRCNT_8822C 0x102500C2
+#define REG_SDIO_DATA_ERRCNT_8822C 0x102500C3
+#define REG_SDIO_CMD_ERR_CONTENT_8822C 0x102500C4
+#define REG_SDIO_CRC_ERR_IDX_8822C 0x102500C9
+#define REG_SDIO_DATA_CRC_8822C 0x102500CA
+#define REG_SDIO_TRANS_FIFO_STATUS_8822C 0x102500CC
+
+#endif
diff --git a/hal/halmac/halmac_rx_bd_ap.h b/hal/halmac/halmac_rx_bd_ap.h
deleted file mode 100644
index 5bb01c0..0000000
--- a/hal/halmac/halmac_rx_bd_ap.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifndef _HALMAC_RX_BD_AP_H_
-#define _HALMAC_RX_BD_AP_H_
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
-
-/*TXBD_DW0*/
-
-#define GET_RX_BD_RXFAIL(__pRxBd) HALMAC_GET_BD_FIELD(((PHALMAC_RX_BD)__pRxBd)->Dword0, 0x1, 31)
-#define GET_RX_BD_TOTALRXPKTSIZE(__pRxBd) HALMAC_GET_BD_FIELD(((PHALMAC_RX_BD)__pRxBd)->Dword0, 0x1fff, 16)
-#define GET_RX_BD_RXTAG(__pRxBd) HALMAC_GET_BD_FIELD(((PHALMAC_RX_BD)__pRxBd)->Dword0, 0x1fff, 16)
-#define GET_RX_BD_FS(__pRxBd) HALMAC_GET_BD_FIELD(((PHALMAC_RX_BD)__pRxBd)->Dword0, 0x1, 15)
-#define GET_RX_BD_LS(__pRxBd) HALMAC_GET_BD_FIELD(((PHALMAC_RX_BD)__pRxBd)->Dword0, 0x1, 14)
-#define GET_RX_BD_RXBUFFSIZE(__pRxBd) HALMAC_GET_BD_FIELD(((PHALMAC_RX_BD)__pRxBd)->Dword0, 0x3fff, 0)
-
-/*TXBD_DW1*/
-
-#define GET_RX_BD_PHYSICAL_ADDR_LOW(__pRxBd) HALMAC_GET_BD_FIELD(((PHALMAC_RX_BD)__pRxBd)->Dword1, 0xffffffff, 0)
-
-/*TXBD_DW2*/
-
-#define GET_RX_BD_PHYSICAL_ADDR_HIGH(__pRxBd) HALMAC_GET_BD_FIELD(((PHALMAC_RX_BD)__pRxBd)->Dword2, 0xffffffff, 0)
-
-#endif
-
-
-#endif
diff --git a/hal/halmac/halmac_rx_bd_chip.h b/hal/halmac/halmac_rx_bd_chip.h
deleted file mode 100644
index 601f11c..0000000
--- a/hal/halmac/halmac_rx_bd_chip.h
+++ /dev/null
@@ -1,109 +0,0 @@
-#ifndef _HALMAC_RX_BD_CHIP_H_
-#define _HALMAC_RX_BD_CHIP_H_
-#if (HALMAC_8814A_SUPPORT)
-
-/*TXBD_DW0*/
-
-#define GET_RX_BD_RXFAIL_8814A(__pRxBd) GET_RX_BD_RXFAIL(__pRxBd)
-#define GET_RX_BD_TOTALRXPKTSIZE_8814A(__pRxBd) GET_RX_BD_TOTALRXPKTSIZE(__pRxBd)
-#define GET_RX_BD_RXTAG_8814A(__pRxBd) GET_RX_BD_RXTAG(__pRxBd)
-#define GET_RX_BD_FS_8814A(__pRxBd) GET_RX_BD_FS(__pRxBd)
-#define GET_RX_BD_LS_8814A(__pRxBd) GET_RX_BD_LS(__pRxBd)
-#define GET_RX_BD_RXBUFFSIZE_8814A(__pRxBd) GET_RX_BD_RXBUFFSIZE(__pRxBd)
-
-/*TXBD_DW1*/
-
-#define GET_RX_BD_PHYSICAL_ADDR_LOW_8814A(__pRxBd) GET_RX_BD_PHYSICAL_ADDR_LOW(__pRxBd)
-
-/*TXBD_DW2*/
-
-#define GET_RX_BD_PHYSICAL_ADDR_HIGH_8814A(__pRxBd) GET_RX_BD_PHYSICAL_ADDR_HIGH(__pRxBd)
-
-#endif
-
-#if (HALMAC_8822B_SUPPORT)
-
-/*TXBD_DW0*/
-
-#define GET_RX_BD_RXFAIL_8822B(__pRxBd) GET_RX_BD_RXFAIL(__pRxBd)
-#define GET_RX_BD_TOTALRXPKTSIZE_8822B(__pRxBd) GET_RX_BD_TOTALRXPKTSIZE(__pRxBd)
-#define GET_RX_BD_RXTAG_8822B(__pRxBd) GET_RX_BD_RXTAG(__pRxBd)
-#define GET_RX_BD_FS_8822B(__pRxBd) GET_RX_BD_FS(__pRxBd)
-#define GET_RX_BD_LS_8822B(__pRxBd) GET_RX_BD_LS(__pRxBd)
-#define GET_RX_BD_RXBUFFSIZE_8822B(__pRxBd) GET_RX_BD_RXBUFFSIZE(__pRxBd)
-
-/*TXBD_DW1*/
-
-#define GET_RX_BD_PHYSICAL_ADDR_LOW_8822B(__pRxBd) GET_RX_BD_PHYSICAL_ADDR_LOW(__pRxBd)
-
-/*TXBD_DW2*/
-
-#define GET_RX_BD_PHYSICAL_ADDR_HIGH_8822B(__pRxBd) GET_RX_BD_PHYSICAL_ADDR_HIGH(__pRxBd)
-
-#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
-/*TXBD_DW0*/
-
-#define GET_RX_BD_RXFAIL_8197F(__pRxBd) GET_RX_BD_RXFAIL(__pRxBd)
-#define GET_RX_BD_TOTALRXPKTSIZE_8197F(__pRxBd) GET_RX_BD_TOTALRXPKTSIZE(__pRxBd)
-#define GET_RX_BD_RXTAG_8197F(__pRxBd) GET_RX_BD_RXTAG(__pRxBd)
-#define GET_RX_BD_FS_8197F(__pRxBd) GET_RX_BD_FS(__pRxBd)
-#define GET_RX_BD_LS_8197F(__pRxBd) GET_RX_BD_LS(__pRxBd)
-#define GET_RX_BD_RXBUFFSIZE_8197F(__pRxBd) GET_RX_BD_RXBUFFSIZE(__pRxBd)
-
-/*TXBD_DW1*/
-
-#define GET_RX_BD_PHYSICAL_ADDR_LOW_8197F(__pRxBd) GET_RX_BD_PHYSICAL_ADDR_LOW(__pRxBd)
-
-/*TXBD_DW2*/
-
-#define GET_RX_BD_PHYSICAL_ADDR_HIGH_8197F(__pRxBd) GET_RX_BD_PHYSICAL_ADDR_HIGH(__pRxBd)
-
-#endif
-
-#if (HALMAC_8821C_SUPPORT)
-
-/*TXBD_DW0*/
-
-#define GET_RX_BD_RXFAIL_8821C(__pRxBd) GET_RX_BD_RXFAIL(__pRxBd)
-#define GET_RX_BD_TOTALRXPKTSIZE_8821C(__pRxBd) GET_RX_BD_TOTALRXPKTSIZE(__pRxBd)
-#define GET_RX_BD_RXTAG_8821C(__pRxBd) GET_RX_BD_RXTAG(__pRxBd)
-#define GET_RX_BD_FS_8821C(__pRxBd) GET_RX_BD_FS(__pRxBd)
-#define GET_RX_BD_LS_8821C(__pRxBd) GET_RX_BD_LS(__pRxBd)
-#define GET_RX_BD_RXBUFFSIZE_8821C(__pRxBd) GET_RX_BD_RXBUFFSIZE(__pRxBd)
-
-/*TXBD_DW1*/
-
-#define GET_RX_BD_PHYSICAL_ADDR_LOW_8821C(__pRxBd) GET_RX_BD_PHYSICAL_ADDR_LOW(__pRxBd)
-
-/*TXBD_DW2*/
-
-#define GET_RX_BD_PHYSICAL_ADDR_HIGH_8821C(__pRxBd) GET_RX_BD_PHYSICAL_ADDR_HIGH(__pRxBd)
-
-#endif
-
-#if (HALMAC_8188F_SUPPORT)
-
-/*TXBD_DW0*/
-
-#define GET_RX_BD_RXFAIL_8188F(__pRxBd) GET_RX_BD_RXFAIL(__pRxBd)
-#define GET_RX_BD_TOTALRXPKTSIZE_8188F(__pRxBd) GET_RX_BD_TOTALRXPKTSIZE(__pRxBd)
-#define GET_RX_BD_RXTAG_8188F(__pRxBd) GET_RX_BD_RXTAG(__pRxBd)
-#define GET_RX_BD_FS_8188F(__pRxBd) GET_RX_BD_FS(__pRxBd)
-#define GET_RX_BD_LS_8188F(__pRxBd) GET_RX_BD_LS(__pRxBd)
-#define GET_RX_BD_RXBUFFSIZE_8188F(__pRxBd) GET_RX_BD_RXBUFFSIZE(__pRxBd)
-
-/*TXBD_DW1*/
-
-#define GET_RX_BD_PHYSICAL_ADDR_LOW_8188F(__pRxBd) GET_RX_BD_PHYSICAL_ADDR_LOW(__pRxBd)
-
-/*TXBD_DW2*/
-
-#define GET_RX_BD_PHYSICAL_ADDR_HIGH_8188F(__pRxBd) GET_RX_BD_PHYSICAL_ADDR_HIGH(__pRxBd)
-
-#endif
-
-
-#endif
diff --git a/hal/halmac/halmac_rx_bd_nic.h b/hal/halmac/halmac_rx_bd_nic.h
index dc7d5cd..dae936a 100644
--- a/hal/halmac/halmac_rx_bd_nic.h
+++ b/hal/halmac/halmac_rx_bd_nic.h
@@ -1,25 +1,40 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
#ifndef _HALMAC_RX_BD_NIC_H_
#define _HALMAC_RX_BD_NIC_H_
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
/*TXBD_DW0*/
-#define GET_RX_BD_RXFAIL(__pRxBd) LE_BITS_TO_4BYTE(__pRxBd + 0x00, 31, 1)
-#define GET_RX_BD_TOTALRXPKTSIZE(__pRxBd) LE_BITS_TO_4BYTE(__pRxBd + 0x00, 16, 13)
-#define GET_RX_BD_RXTAG(__pRxBd) LE_BITS_TO_4BYTE(__pRxBd + 0x00, 16, 13)
-#define GET_RX_BD_FS(__pRxBd) LE_BITS_TO_4BYTE(__pRxBd + 0x00, 15, 1)
-#define GET_RX_BD_LS(__pRxBd) LE_BITS_TO_4BYTE(__pRxBd + 0x00, 14, 1)
-#define GET_RX_BD_RXBUFFSIZE(__pRxBd) LE_BITS_TO_4BYTE(__pRxBd + 0x00, 0, 14)
+#define GET_RX_BD_RXFAIL(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 31, 1)
+#define GET_RX_BD_TOTALRXPKTSIZE(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 16, 13)
+#define GET_RX_BD_RXTAG(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 16, 13)
+#define GET_RX_BD_FS(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 15, 1)
+#define GET_RX_BD_LS(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 14, 1)
+#define GET_RX_BD_RXBUFFSIZE(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x00, 0, 14)
/*TXBD_DW1*/
-#define GET_RX_BD_PHYSICAL_ADDR_LOW(__pRxBd) LE_BITS_TO_4BYTE(__pRxBd + 0x04, 0, 32)
+#define GET_RX_BD_PHYSICAL_ADDR_LOW(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x04, 0, 32)
/*TXBD_DW2*/
-#define GET_RX_BD_PHYSICAL_ADDR_HIGH(__pRxBd) LE_BITS_TO_4BYTE(__pRxBd + 0x08, 0, 32)
+#define GET_RX_BD_PHYSICAL_ADDR_HIGH(rxbd) LE_BITS_TO_4BYTE(rxbd + 0x08, 0, 32)
#endif
-
#endif
diff --git a/hal/halmac/halmac_rx_desc_ap.h b/hal/halmac/halmac_rx_desc_ap.h
index 386e418..1ba6b92 100644
--- a/hal/halmac/halmac_rx_desc_ap.h
+++ b/hal/halmac/halmac_rx_desc_ap.h
@@ -1,108 +1,614 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
#ifndef _HALMAC_RX_DESC_AP_H_
#define _HALMAC_RX_DESC_AP_H_
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
/*RXDESC_WORD0*/
-#define GET_RX_DESC_EOR(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x1, 30)
-#define GET_RX_DESC_PHYPKTIDC(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x1, 28)
-#define GET_RX_DESC_SWDEC(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x1, 27)
-#define GET_RX_DESC_PHYST(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x1, 26)
-#define GET_RX_DESC_SHIFT(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x3, 24)
-#define GET_RX_DESC_QOS(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x1, 23)
-#define GET_RX_DESC_SECURITY(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x7, 20)
-#define GET_RX_DESC_DRV_INFO_SIZE(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0xf, 16)
-#define GET_RX_DESC_ICV_ERR(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x1, 15)
-#define GET_RX_DESC_CRC32(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x1, 14)
-#define GET_RX_DESC_PKT_LEN(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x3fff, 0)
+#define GET_RX_DESC_EOR(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1, \
+ 30)
+#define GET_RX_DESC_PHYPKTIDC(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1, \
+ 28)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_EVT_PKT(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1, \
+ 28)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_SWDEC(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1, \
+ 27)
+#define GET_RX_DESC_PHYST(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1, \
+ 26)
+#define GET_RX_DESC_SHIFT(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x3, \
+ 24)
+#define GET_RX_DESC_QOS(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1, \
+ 23)
+#define GET_RX_DESC_SECURITY(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x7, \
+ 20)
+#define GET_RX_DESC_DRV_INFO_SIZE(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0xf, \
+ 16)
+#define GET_RX_DESC_ICV_ERR(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1, \
+ 15)
+#define GET_RX_DESC_CRC32(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, 0x1, \
+ 14)
+#define GET_RX_DESC_PKT_LEN(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword0, \
+ 0x3fff, 0)
/*RXDESC_WORD1*/
-#define GET_RX_DESC_BC(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 31)
-#define GET_RX_DESC_MC(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 30)
-#define GET_RX_DESC_TY_PE(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x3, 28)
-#define GET_RX_DESC_MF(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 27)
-#define GET_RX_DESC_MD(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 26)
-#define GET_RX_DESC_PWR(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 25)
-#define GET_RX_DESC_PAM(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 24)
-#define GET_RX_DESC_CHK_VLD(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 23)
-#define GET_RX_DESC_RX_IS_TCP_UDP(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 22)
-#define GET_RX_DESC_RX_IPV(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 21)
-#define GET_RX_DESC_CHKERR(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 20)
-#define GET_RX_DESC_PAGGR(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 15)
-#define GET_RX_DESC_RXID_MATCH(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 14)
-#define GET_RX_DESC_AMSDU(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 13)
-#define GET_RX_DESC_MACID_VLD(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 12)
-#define GET_RX_DESC_TID(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0xf, 8)
+#define GET_RX_DESC_BC(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
+ 31)
+#define GET_RX_DESC_MC(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
+ 30)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_TY_PE(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x3, \
+ 28)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_TYPE(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x3, \
+ 28)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_MF(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
+ 27)
+#define GET_RX_DESC_MD(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
+ 26)
+#define GET_RX_DESC_PWR(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
+ 25)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_PAM(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
+ 24)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_A1_MATCH(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
+ 24)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_CHK_VLD(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
+ 23)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_TCP_CHKSUM_VLD(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
+ 23)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_RX_IS_TCP_UDP(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
+ 22)
+#define GET_RX_DESC_RX_IPV(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
+ 21)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_CHKERR(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
+ 20)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_TCP_CHKSUM_ERR(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
+ 20)
+#define GET_RX_DESC_PHY_PKT_IDC(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
+ 17)
+#define GET_RX_DESC_FW_FIFO_FULL(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
+ 16)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_PAGGR(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
+ 15)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8814B_SUPPORT)
-#define GET_RX_DESC_EXT_SECTYPE(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 7)
+#define GET_RX_DESC_AMPDU(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
+ 15)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
-#define GET_RX_DESC_MACID(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x7f, 0)
+#define GET_RX_DESC_RXID_MATCH(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
+ 14)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_RXCMD_IDC(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
+ 14)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_AMSDU(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
+ 13)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_MACID_VLD(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x1, \
+ 12)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_TID(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0xf, 8)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_MACID(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword1, 0x7f, \
+ 0)
/*RXDESC_WORD2*/
-#define GET_RX_DESC_FCS_OK(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword2, 0x1, 31)
-#define GET_RX_DESC_C2H(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword2, 0x1, 28)
-#define GET_RX_DESC_HWRSVD(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword2, 0xf, 24)
-#define GET_RX_DESC_WLANHD_IV_LEN(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword2, 0x3f, 18)
-#define GET_RX_DESC_RX_IS_QOS(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword2, 0x1, 16)
-#define GET_RX_DESC_FRAG(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword2, 0xf, 12)
-#define GET_RX_DESC_SEQ(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword2, 0xfff, 0)
+#define GET_RX_DESC_FCS_OK(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1, \
+ 31)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_AMSDU_CUT(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1, \
+ 31)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_PPDU_CNT(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x3, \
+ 29)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_C2H(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1, \
+ 28)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_HWRSVD_V1(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x7, \
+ 25)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_HWRSVD(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0xf, \
+ 24)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_RXMAGPKT(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1, \
+ 24)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_WLANHD_IV_LEN(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x3f, \
+ 18)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_LAST_MSDU(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1, \
+ 17)
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_RX_STATISTICS(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1, \
+ 17)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_RX_IS_QOS(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1, \
+ 16)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_EXT_SEC_TYPE(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0x1, \
+ 16)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_FRAG(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, 0xf, \
+ 12)
+#define GET_RX_DESC_SEQ(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword2, \
+ 0xfff, 0)
/*RXDESC_WORD3*/
-#define GET_RX_DESC_MAGIC_WAKE(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x1, 31)
-#define GET_RX_DESC_UNICAST_WAKE(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x1, 30)
-#define GET_RX_DESC_PATTERN_MATCH(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x1, 29)
-#define GET_RX_DESC_DMA_AGG_NUM(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0xff, 16)
-#define GET_RX_DESC_BSSID_FIT_1_0(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x3, 12)
-#define GET_RX_DESC_EOSP(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x1, 11)
-#define GET_RX_DESC_HTC(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x1, 10)
+#define GET_RX_DESC_MAGIC_WAKE(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, \
+ 31)
+#define GET_RX_DESC_UNICAST_WAKE(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, \
+ 30)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_PATTERN_MATCH(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, \
+ 29)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_PATTERN_WAKE(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, \
+ 29)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, \
+ 28)
+#define GET_RX_DESC_RXPAYLOAD_ID(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0xf, \
+ 24)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_DMA_AGG_NUM(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0xff, \
+ 16)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_BSSID_FIT_1_0(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x3, \
+ 12)
+#define GET_RX_DESC_EOSP(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, \
+ 11)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_BSSID_FIT(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1f, \
+ 11)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_HTC(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, \
+ 10)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_AMPDU_END_PKT(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, 9)
+#define GET_RX_DESC_ADDRESS_CAM_VLD(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, 8)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_BSSID_FIT_4_2(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x7, 7)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8814B_SUPPORT)
-#define GET_RX_DESC_BSSID_FIT_4_2(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x7, 7)
+#define GET_RX_DESC_EOSP_V1(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x1, 7)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define GET_RX_DESC_RX_RATE(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x7f, 0)
+#define GET_RX_DESC_RX_RATE(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword3, 0x7f, \
+ 0)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
/*RXDESC_WORD4*/
-#define GET_RX_DESC_A1_FIT(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword4, 0x1f, 24)
+#define GET_RX_DESC_A1_FIT(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1f, \
+ 24)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_ADDRESS_CAM(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0xff, \
+ 24)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_A1_FIT_A1(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x7f, \
+ 24)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8814B_SUPPORT)
-#define GET_RX_DESC_MACID_RPT_BUFF(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword4, 0x7f, 17)
-#define GET_RX_DESC_RX_PRE_NDP_VLD(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword4, 0x1, 16)
-#define GET_RX_DESC_RX_SCRAMBLER(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword4, 0x7f, 9)
-#define GET_RX_DESC_RX_EOF(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword4, 0x1, 8)
+#define GET_RX_DESC_MACID_VLD_V1(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, \
+ 23)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
-#define GET_RX_DESC_PATTERN_IDX(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword4, 0xff, 0)
+#define GET_RX_DESC_MACID_RPT_BUFF(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x7f, \
+ 17)
+#define GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, \
+ 16)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_MACID_V1(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0xff, \
+ 15)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_RX_SCRAMBLER(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x7f, \
+ 9)
+#define GET_RX_DESC_RX_EOF(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, 8)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_FC_POWER(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, 7)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_TXRPTMID_CTL_MASK(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, 6)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_SWPS_RPT(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1, 5)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_PATTERN_IDX(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0xff, \
+ 0)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_PATTERN_IDX_V1(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1f, \
+ 0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_PATTERN_IDX_V2(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword4, 0x1f, \
+ 0)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
/*RXDESC_WORD5*/
-#define GET_RX_DESC_TSFL(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword5, 0xffffffff, 0)
+#define GET_RX_DESC_TSFL(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword5, \
+ 0xffffffff, 0)
#endif
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_FREERUN_CNT(rxdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_rx_desc *)rxdesc)->dword5, \
+ 0xffffffff, 0)
+
+#endif
#endif
diff --git a/hal/halmac/halmac_rx_desc_chip.h b/hal/halmac/halmac_rx_desc_chip.h
index 43d8057..ac36d0a 100644
--- a/hal/halmac/halmac_rx_desc_chip.h
+++ b/hal/halmac/halmac_rx_desc_chip.h
@@ -1,76 +1,98 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
#ifndef _HALMAC_RX_DESC_CHIP_H_
#define _HALMAC_RX_DESC_CHIP_H_
#if (HALMAC_8814A_SUPPORT)
/*RXDESC_WORD0*/
-#define GET_RX_DESC_EOR_8814A(__pRxDesc) GET_RX_DESC_EOR(__pRxDesc)
-#define GET_RX_DESC_PHYPKTIDC_8814A(__pRxDesc) GET_RX_DESC_PHYPKTIDC(__pRxDesc)
-#define GET_RX_DESC_SWDEC_8814A(__pRxDesc) GET_RX_DESC_SWDEC(__pRxDesc)
-#define GET_RX_DESC_PHYST_8814A(__pRxDesc) GET_RX_DESC_PHYST(__pRxDesc)
-#define GET_RX_DESC_SHIFT_8814A(__pRxDesc) GET_RX_DESC_SHIFT(__pRxDesc)
-#define GET_RX_DESC_QOS_8814A(__pRxDesc) GET_RX_DESC_QOS(__pRxDesc)
-#define GET_RX_DESC_SECURITY_8814A(__pRxDesc) GET_RX_DESC_SECURITY(__pRxDesc)
-#define GET_RX_DESC_DRV_INFO_SIZE_8814A(__pRxDesc) GET_RX_DESC_DRV_INFO_SIZE(__pRxDesc)
-#define GET_RX_DESC_ICV_ERR_8814A(__pRxDesc) GET_RX_DESC_ICV_ERR(__pRxDesc)
-#define GET_RX_DESC_CRC32_8814A(__pRxDesc) GET_RX_DESC_CRC32(__pRxDesc)
-#define GET_RX_DESC_PKT_LEN_8814A(__pRxDesc) GET_RX_DESC_PKT_LEN(__pRxDesc)
+#define GET_RX_DESC_EOR_8814A(rxdesc) GET_RX_DESC_EOR(rxdesc)
+#define GET_RX_DESC_PHYPKTIDC_8814A(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc)
+#define GET_RX_DESC_SWDEC_8814A(rxdesc) GET_RX_DESC_SWDEC(rxdesc)
+#define GET_RX_DESC_PHYST_8814A(rxdesc) GET_RX_DESC_PHYST(rxdesc)
+#define GET_RX_DESC_SHIFT_8814A(rxdesc) GET_RX_DESC_SHIFT(rxdesc)
+#define GET_RX_DESC_QOS_8814A(rxdesc) GET_RX_DESC_QOS(rxdesc)
+#define GET_RX_DESC_SECURITY_8814A(rxdesc) GET_RX_DESC_SECURITY(rxdesc)
+#define GET_RX_DESC_DRV_INFO_SIZE_8814A(rxdesc) \
+ GET_RX_DESC_DRV_INFO_SIZE(rxdesc)
+#define GET_RX_DESC_ICV_ERR_8814A(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc)
+#define GET_RX_DESC_CRC32_8814A(rxdesc) GET_RX_DESC_CRC32(rxdesc)
+#define GET_RX_DESC_PKT_LEN_8814A(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc)
/*RXDESC_WORD1*/
-#define GET_RX_DESC_BC_8814A(__pRxDesc) GET_RX_DESC_BC(__pRxDesc)
-#define GET_RX_DESC_MC_8814A(__pRxDesc) GET_RX_DESC_MC(__pRxDesc)
-#define GET_RX_DESC_TY_PE_8814A(__pRxDesc) GET_RX_DESC_TY_PE(__pRxDesc)
-#define GET_RX_DESC_MF_8814A(__pRxDesc) GET_RX_DESC_MF(__pRxDesc)
-#define GET_RX_DESC_MD_8814A(__pRxDesc) GET_RX_DESC_MD(__pRxDesc)
-#define GET_RX_DESC_PWR_8814A(__pRxDesc) GET_RX_DESC_PWR(__pRxDesc)
-#define GET_RX_DESC_PAM_8814A(__pRxDesc) GET_RX_DESC_PAM(__pRxDesc)
-#define GET_RX_DESC_CHK_VLD_8814A(__pRxDesc) GET_RX_DESC_CHK_VLD(__pRxDesc)
-#define GET_RX_DESC_RX_IS_TCP_UDP_8814A(__pRxDesc) GET_RX_DESC_RX_IS_TCP_UDP(__pRxDesc)
-#define GET_RX_DESC_RX_IPV_8814A(__pRxDesc) GET_RX_DESC_RX_IPV(__pRxDesc)
-#define GET_RX_DESC_CHKERR_8814A(__pRxDesc) GET_RX_DESC_CHKERR(__pRxDesc)
-#define GET_RX_DESC_PAGGR_8814A(__pRxDesc) GET_RX_DESC_PAGGR(__pRxDesc)
-#define GET_RX_DESC_RXID_MATCH_8814A(__pRxDesc) GET_RX_DESC_RXID_MATCH(__pRxDesc)
-#define GET_RX_DESC_AMSDU_8814A(__pRxDesc) GET_RX_DESC_AMSDU(__pRxDesc)
-#define GET_RX_DESC_MACID_VLD_8814A(__pRxDesc) GET_RX_DESC_MACID_VLD(__pRxDesc)
-#define GET_RX_DESC_TID_8814A(__pRxDesc) GET_RX_DESC_TID(__pRxDesc)
-#define GET_RX_DESC_EXT_SECTYPE_8814A(__pRxDesc) GET_RX_DESC_EXT_SECTYPE(__pRxDesc)
-#define GET_RX_DESC_MACID_8814A(__pRxDesc) GET_RX_DESC_MACID(__pRxDesc)
+#define GET_RX_DESC_BC_8814A(rxdesc) GET_RX_DESC_BC(rxdesc)
+#define GET_RX_DESC_MC_8814A(rxdesc) GET_RX_DESC_MC(rxdesc)
+#define GET_RX_DESC_TY_PE_8814A(rxdesc) GET_RX_DESC_TY_PE(rxdesc)
+#define GET_RX_DESC_MF_8814A(rxdesc) GET_RX_DESC_MF(rxdesc)
+#define GET_RX_DESC_MD_8814A(rxdesc) GET_RX_DESC_MD(rxdesc)
+#define GET_RX_DESC_PWR_8814A(rxdesc) GET_RX_DESC_PWR(rxdesc)
+#define GET_RX_DESC_PAM_8814A(rxdesc) GET_RX_DESC_PAM(rxdesc)
+#define GET_RX_DESC_CHK_VLD_8814A(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc)
+#define GET_RX_DESC_RX_IS_TCP_UDP_8814A(rxdesc) \
+ GET_RX_DESC_RX_IS_TCP_UDP(rxdesc)
+#define GET_RX_DESC_RX_IPV_8814A(rxdesc) GET_RX_DESC_RX_IPV(rxdesc)
+#define GET_RX_DESC_CHKERR_8814A(rxdesc) GET_RX_DESC_CHKERR(rxdesc)
+#define GET_RX_DESC_PAGGR_8814A(rxdesc) GET_RX_DESC_PAGGR(rxdesc)
+#define GET_RX_DESC_RXID_MATCH_8814A(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc)
+#define GET_RX_DESC_AMSDU_8814A(rxdesc) GET_RX_DESC_AMSDU(rxdesc)
+#define GET_RX_DESC_MACID_VLD_8814A(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc)
+#define GET_RX_DESC_TID_8814A(rxdesc) GET_RX_DESC_TID(rxdesc)
+#define GET_RX_DESC_MACID_8814A(rxdesc) GET_RX_DESC_MACID(rxdesc)
/*RXDESC_WORD2*/
-#define GET_RX_DESC_FCS_OK_8814A(__pRxDesc) GET_RX_DESC_FCS_OK(__pRxDesc)
-#define GET_RX_DESC_C2H_8814A(__pRxDesc) GET_RX_DESC_C2H(__pRxDesc)
-#define GET_RX_DESC_HWRSVD_8814A(__pRxDesc) GET_RX_DESC_HWRSVD(__pRxDesc)
-#define GET_RX_DESC_WLANHD_IV_LEN_8814A(__pRxDesc) GET_RX_DESC_WLANHD_IV_LEN(__pRxDesc)
-#define GET_RX_DESC_RX_IS_QOS_8814A(__pRxDesc) GET_RX_DESC_RX_IS_QOS(__pRxDesc)
-#define GET_RX_DESC_FRAG_8814A(__pRxDesc) GET_RX_DESC_FRAG(__pRxDesc)
-#define GET_RX_DESC_SEQ_8814A(__pRxDesc) GET_RX_DESC_SEQ(__pRxDesc)
+#define GET_RX_DESC_FCS_OK_8814A(rxdesc) GET_RX_DESC_FCS_OK(rxdesc)
+#define GET_RX_DESC_C2H_8814A(rxdesc) GET_RX_DESC_C2H(rxdesc)
+#define GET_RX_DESC_HWRSVD_8814A(rxdesc) GET_RX_DESC_HWRSVD(rxdesc)
+#define GET_RX_DESC_WLANHD_IV_LEN_8814A(rxdesc) \
+ GET_RX_DESC_WLANHD_IV_LEN(rxdesc)
+#define GET_RX_DESC_RX_IS_QOS_8814A(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc)
+#define GET_RX_DESC_FRAG_8814A(rxdesc) GET_RX_DESC_FRAG(rxdesc)
+#define GET_RX_DESC_SEQ_8814A(rxdesc) GET_RX_DESC_SEQ(rxdesc)
/*RXDESC_WORD3*/
-#define GET_RX_DESC_MAGIC_WAKE_8814A(__pRxDesc) GET_RX_DESC_MAGIC_WAKE(__pRxDesc)
-#define GET_RX_DESC_UNICAST_WAKE_8814A(__pRxDesc) GET_RX_DESC_UNICAST_WAKE(__pRxDesc)
-#define GET_RX_DESC_PATTERN_MATCH_8814A(__pRxDesc) GET_RX_DESC_PATTERN_MATCH(__pRxDesc)
-#define GET_RX_DESC_DMA_AGG_NUM_8814A(__pRxDesc) GET_RX_DESC_DMA_AGG_NUM(__pRxDesc)
-#define GET_RX_DESC_BSSID_FIT_1_0_8814A(__pRxDesc) GET_RX_DESC_BSSID_FIT_1_0(__pRxDesc)
-#define GET_RX_DESC_EOSP_8814A(__pRxDesc) GET_RX_DESC_EOSP(__pRxDesc)
-#define GET_RX_DESC_HTC_8814A(__pRxDesc) GET_RX_DESC_HTC(__pRxDesc)
-#define GET_RX_DESC_BSSID_FIT_4_2_8814A(__pRxDesc) GET_RX_DESC_BSSID_FIT_4_2(__pRxDesc)
-#define GET_RX_DESC_RX_RATE_8814A(__pRxDesc) GET_RX_DESC_RX_RATE(__pRxDesc)
+#define GET_RX_DESC_MAGIC_WAKE_8814A(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc)
+#define GET_RX_DESC_UNICAST_WAKE_8814A(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc)
+#define GET_RX_DESC_PATTERN_MATCH_8814A(rxdesc) \
+ GET_RX_DESC_PATTERN_MATCH(rxdesc)
+#define GET_RX_DESC_DMA_AGG_NUM_8814A(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_1_0_8814A(rxdesc) \
+ GET_RX_DESC_BSSID_FIT_1_0(rxdesc)
+#define GET_RX_DESC_EOSP_8814A(rxdesc) GET_RX_DESC_EOSP(rxdesc)
+#define GET_RX_DESC_HTC_8814A(rxdesc) GET_RX_DESC_HTC(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_4_2_8814A(rxdesc) \
+ GET_RX_DESC_BSSID_FIT_4_2(rxdesc)
+#define GET_RX_DESC_RX_RATE_8814A(rxdesc) GET_RX_DESC_RX_RATE(rxdesc)
/*RXDESC_WORD4*/
-#define GET_RX_DESC_A1_FIT_8814A(__pRxDesc) GET_RX_DESC_A1_FIT(__pRxDesc)
-#define GET_RX_DESC_MACID_RPT_BUFF_8814A(__pRxDesc) GET_RX_DESC_MACID_RPT_BUFF(__pRxDesc)
-#define GET_RX_DESC_RX_PRE_NDP_VLD_8814A(__pRxDesc) GET_RX_DESC_RX_PRE_NDP_VLD(__pRxDesc)
-#define GET_RX_DESC_RX_SCRAMBLER_8814A(__pRxDesc) GET_RX_DESC_RX_SCRAMBLER(__pRxDesc)
-#define GET_RX_DESC_RX_EOF_8814A(__pRxDesc) GET_RX_DESC_RX_EOF(__pRxDesc)
-#define GET_RX_DESC_PATTERN_IDX_8814A(__pRxDesc) GET_RX_DESC_PATTERN_IDX(__pRxDesc)
+#define GET_RX_DESC_A1_FIT_8814A(rxdesc) GET_RX_DESC_A1_FIT(rxdesc)
+#define GET_RX_DESC_MACID_RPT_BUFF_8814A(rxdesc) \
+ GET_RX_DESC_MACID_RPT_BUFF(rxdesc)
+#define GET_RX_DESC_RX_PRE_NDP_VLD_8814A(rxdesc) \
+ GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc)
+#define GET_RX_DESC_RX_SCRAMBLER_8814A(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc)
+#define GET_RX_DESC_RX_EOF_8814A(rxdesc) GET_RX_DESC_RX_EOF(rxdesc)
+#define GET_RX_DESC_PATTERN_IDX_8814A(rxdesc) GET_RX_DESC_PATTERN_IDX(rxdesc)
/*RXDESC_WORD5*/
-#define GET_RX_DESC_TSFL_8814A(__pRxDesc) GET_RX_DESC_TSFL(__pRxDesc)
+#define GET_RX_DESC_TSFL_8814A(rxdesc) GET_RX_DESC_TSFL(rxdesc)
#endif
@@ -78,73 +100,84 @@
/*RXDESC_WORD0*/
-#define GET_RX_DESC_EOR_8822B(__pRxDesc) GET_RX_DESC_EOR(__pRxDesc)
-#define GET_RX_DESC_PHYPKTIDC_8822B(__pRxDesc) GET_RX_DESC_PHYPKTIDC(__pRxDesc)
-#define GET_RX_DESC_SWDEC_8822B(__pRxDesc) GET_RX_DESC_SWDEC(__pRxDesc)
-#define GET_RX_DESC_PHYST_8822B(__pRxDesc) GET_RX_DESC_PHYST(__pRxDesc)
-#define GET_RX_DESC_SHIFT_8822B(__pRxDesc) GET_RX_DESC_SHIFT(__pRxDesc)
-#define GET_RX_DESC_QOS_8822B(__pRxDesc) GET_RX_DESC_QOS(__pRxDesc)
-#define GET_RX_DESC_SECURITY_8822B(__pRxDesc) GET_RX_DESC_SECURITY(__pRxDesc)
-#define GET_RX_DESC_DRV_INFO_SIZE_8822B(__pRxDesc) GET_RX_DESC_DRV_INFO_SIZE(__pRxDesc)
-#define GET_RX_DESC_ICV_ERR_8822B(__pRxDesc) GET_RX_DESC_ICV_ERR(__pRxDesc)
-#define GET_RX_DESC_CRC32_8822B(__pRxDesc) GET_RX_DESC_CRC32(__pRxDesc)
-#define GET_RX_DESC_PKT_LEN_8822B(__pRxDesc) GET_RX_DESC_PKT_LEN(__pRxDesc)
+#define GET_RX_DESC_EOR_8822B(rxdesc) GET_RX_DESC_EOR(rxdesc)
+#define GET_RX_DESC_PHYPKTIDC_8822B(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc)
+#define GET_RX_DESC_SWDEC_8822B(rxdesc) GET_RX_DESC_SWDEC(rxdesc)
+#define GET_RX_DESC_PHYST_8822B(rxdesc) GET_RX_DESC_PHYST(rxdesc)
+#define GET_RX_DESC_SHIFT_8822B(rxdesc) GET_RX_DESC_SHIFT(rxdesc)
+#define GET_RX_DESC_QOS_8822B(rxdesc) GET_RX_DESC_QOS(rxdesc)
+#define GET_RX_DESC_SECURITY_8822B(rxdesc) GET_RX_DESC_SECURITY(rxdesc)
+#define GET_RX_DESC_DRV_INFO_SIZE_8822B(rxdesc) \
+ GET_RX_DESC_DRV_INFO_SIZE(rxdesc)
+#define GET_RX_DESC_ICV_ERR_8822B(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc)
+#define GET_RX_DESC_CRC32_8822B(rxdesc) GET_RX_DESC_CRC32(rxdesc)
+#define GET_RX_DESC_PKT_LEN_8822B(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc)
/*RXDESC_WORD1*/
-#define GET_RX_DESC_BC_8822B(__pRxDesc) GET_RX_DESC_BC(__pRxDesc)
-#define GET_RX_DESC_MC_8822B(__pRxDesc) GET_RX_DESC_MC(__pRxDesc)
-#define GET_RX_DESC_TY_PE_8822B(__pRxDesc) GET_RX_DESC_TY_PE(__pRxDesc)
-#define GET_RX_DESC_MF_8822B(__pRxDesc) GET_RX_DESC_MF(__pRxDesc)
-#define GET_RX_DESC_MD_8822B(__pRxDesc) GET_RX_DESC_MD(__pRxDesc)
-#define GET_RX_DESC_PWR_8822B(__pRxDesc) GET_RX_DESC_PWR(__pRxDesc)
-#define GET_RX_DESC_PAM_8822B(__pRxDesc) GET_RX_DESC_PAM(__pRxDesc)
-#define GET_RX_DESC_CHK_VLD_8822B(__pRxDesc) GET_RX_DESC_CHK_VLD(__pRxDesc)
-#define GET_RX_DESC_RX_IS_TCP_UDP_8822B(__pRxDesc) GET_RX_DESC_RX_IS_TCP_UDP(__pRxDesc)
-#define GET_RX_DESC_RX_IPV_8822B(__pRxDesc) GET_RX_DESC_RX_IPV(__pRxDesc)
-#define GET_RX_DESC_CHKERR_8822B(__pRxDesc) GET_RX_DESC_CHKERR(__pRxDesc)
-#define GET_RX_DESC_PAGGR_8822B(__pRxDesc) GET_RX_DESC_PAGGR(__pRxDesc)
-#define GET_RX_DESC_RXID_MATCH_8822B(__pRxDesc) GET_RX_DESC_RXID_MATCH(__pRxDesc)
-#define GET_RX_DESC_AMSDU_8822B(__pRxDesc) GET_RX_DESC_AMSDU(__pRxDesc)
-#define GET_RX_DESC_MACID_VLD_8822B(__pRxDesc) GET_RX_DESC_MACID_VLD(__pRxDesc)
-#define GET_RX_DESC_TID_8822B(__pRxDesc) GET_RX_DESC_TID(__pRxDesc)
-#define GET_RX_DESC_EXT_SECTYPE_8822B(__pRxDesc) GET_RX_DESC_EXT_SECTYPE(__pRxDesc)
-#define GET_RX_DESC_MACID_8822B(__pRxDesc) GET_RX_DESC_MACID(__pRxDesc)
+#define GET_RX_DESC_BC_8822B(rxdesc) GET_RX_DESC_BC(rxdesc)
+#define GET_RX_DESC_MC_8822B(rxdesc) GET_RX_DESC_MC(rxdesc)
+#define GET_RX_DESC_TY_PE_8822B(rxdesc) GET_RX_DESC_TY_PE(rxdesc)
+#define GET_RX_DESC_MF_8822B(rxdesc) GET_RX_DESC_MF(rxdesc)
+#define GET_RX_DESC_MD_8822B(rxdesc) GET_RX_DESC_MD(rxdesc)
+#define GET_RX_DESC_PWR_8822B(rxdesc) GET_RX_DESC_PWR(rxdesc)
+#define GET_RX_DESC_PAM_8822B(rxdesc) GET_RX_DESC_PAM(rxdesc)
+#define GET_RX_DESC_CHK_VLD_8822B(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc)
+#define GET_RX_DESC_RX_IS_TCP_UDP_8822B(rxdesc) \
+ GET_RX_DESC_RX_IS_TCP_UDP(rxdesc)
+#define GET_RX_DESC_RX_IPV_8822B(rxdesc) GET_RX_DESC_RX_IPV(rxdesc)
+#define GET_RX_DESC_CHKERR_8822B(rxdesc) GET_RX_DESC_CHKERR(rxdesc)
+#define GET_RX_DESC_PAGGR_8822B(rxdesc) GET_RX_DESC_PAGGR(rxdesc)
+#define GET_RX_DESC_RXID_MATCH_8822B(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc)
+#define GET_RX_DESC_AMSDU_8822B(rxdesc) GET_RX_DESC_AMSDU(rxdesc)
+#define GET_RX_DESC_MACID_VLD_8822B(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc)
+#define GET_RX_DESC_TID_8822B(rxdesc) GET_RX_DESC_TID(rxdesc)
+#define GET_RX_DESC_MACID_8822B(rxdesc) GET_RX_DESC_MACID(rxdesc)
/*RXDESC_WORD2*/
-#define GET_RX_DESC_FCS_OK_8822B(__pRxDesc) GET_RX_DESC_FCS_OK(__pRxDesc)
-#define GET_RX_DESC_C2H_8822B(__pRxDesc) GET_RX_DESC_C2H(__pRxDesc)
-#define GET_RX_DESC_HWRSVD_8822B(__pRxDesc) GET_RX_DESC_HWRSVD(__pRxDesc)
-#define GET_RX_DESC_WLANHD_IV_LEN_8822B(__pRxDesc) GET_RX_DESC_WLANHD_IV_LEN(__pRxDesc)
-#define GET_RX_DESC_RX_IS_QOS_8822B(__pRxDesc) GET_RX_DESC_RX_IS_QOS(__pRxDesc)
-#define GET_RX_DESC_FRAG_8822B(__pRxDesc) GET_RX_DESC_FRAG(__pRxDesc)
-#define GET_RX_DESC_SEQ_8822B(__pRxDesc) GET_RX_DESC_SEQ(__pRxDesc)
+#define GET_RX_DESC_FCS_OK_8822B(rxdesc) GET_RX_DESC_FCS_OK(rxdesc)
+#define GET_RX_DESC_PPDU_CNT_8822B(rxdesc) GET_RX_DESC_PPDU_CNT(rxdesc)
+#define GET_RX_DESC_C2H_8822B(rxdesc) GET_RX_DESC_C2H(rxdesc)
+#define GET_RX_DESC_HWRSVD_8822B(rxdesc) GET_RX_DESC_HWRSVD(rxdesc)
+#define GET_RX_DESC_WLANHD_IV_LEN_8822B(rxdesc) \
+ GET_RX_DESC_WLANHD_IV_LEN(rxdesc)
+#define GET_RX_DESC_RX_IS_QOS_8822B(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc)
+#define GET_RX_DESC_FRAG_8822B(rxdesc) GET_RX_DESC_FRAG(rxdesc)
+#define GET_RX_DESC_SEQ_8822B(rxdesc) GET_RX_DESC_SEQ(rxdesc)
/*RXDESC_WORD3*/
-#define GET_RX_DESC_MAGIC_WAKE_8822B(__pRxDesc) GET_RX_DESC_MAGIC_WAKE(__pRxDesc)
-#define GET_RX_DESC_UNICAST_WAKE_8822B(__pRxDesc) GET_RX_DESC_UNICAST_WAKE(__pRxDesc)
-#define GET_RX_DESC_PATTERN_MATCH_8822B(__pRxDesc) GET_RX_DESC_PATTERN_MATCH(__pRxDesc)
-#define GET_RX_DESC_DMA_AGG_NUM_8822B(__pRxDesc) GET_RX_DESC_DMA_AGG_NUM(__pRxDesc)
-#define GET_RX_DESC_BSSID_FIT_1_0_8822B(__pRxDesc) GET_RX_DESC_BSSID_FIT_1_0(__pRxDesc)
-#define GET_RX_DESC_EOSP_8822B(__pRxDesc) GET_RX_DESC_EOSP(__pRxDesc)
-#define GET_RX_DESC_HTC_8822B(__pRxDesc) GET_RX_DESC_HTC(__pRxDesc)
-#define GET_RX_DESC_BSSID_FIT_4_2_8822B(__pRxDesc) GET_RX_DESC_BSSID_FIT_4_2(__pRxDesc)
-#define GET_RX_DESC_RX_RATE_8822B(__pRxDesc) GET_RX_DESC_RX_RATE(__pRxDesc)
+#define GET_RX_DESC_MAGIC_WAKE_8822B(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc)
+#define GET_RX_DESC_UNICAST_WAKE_8822B(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc)
+#define GET_RX_DESC_PATTERN_MATCH_8822B(rxdesc) \
+ GET_RX_DESC_PATTERN_MATCH(rxdesc)
+#define GET_RX_DESC_RXPAYLOAD_MATCH_8822B(rxdesc) \
+ GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc)
+#define GET_RX_DESC_RXPAYLOAD_ID_8822B(rxdesc) GET_RX_DESC_RXPAYLOAD_ID(rxdesc)
+#define GET_RX_DESC_DMA_AGG_NUM_8822B(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_1_0_8822B(rxdesc) \
+ GET_RX_DESC_BSSID_FIT_1_0(rxdesc)
+#define GET_RX_DESC_EOSP_8822B(rxdesc) GET_RX_DESC_EOSP(rxdesc)
+#define GET_RX_DESC_HTC_8822B(rxdesc) GET_RX_DESC_HTC(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_4_2_8822B(rxdesc) \
+ GET_RX_DESC_BSSID_FIT_4_2(rxdesc)
+#define GET_RX_DESC_RX_RATE_8822B(rxdesc) GET_RX_DESC_RX_RATE(rxdesc)
/*RXDESC_WORD4*/
-#define GET_RX_DESC_A1_FIT_8822B(__pRxDesc) GET_RX_DESC_A1_FIT(__pRxDesc)
-#define GET_RX_DESC_MACID_RPT_BUFF_8822B(__pRxDesc) GET_RX_DESC_MACID_RPT_BUFF(__pRxDesc)
-#define GET_RX_DESC_RX_PRE_NDP_VLD_8822B(__pRxDesc) GET_RX_DESC_RX_PRE_NDP_VLD(__pRxDesc)
-#define GET_RX_DESC_RX_SCRAMBLER_8822B(__pRxDesc) GET_RX_DESC_RX_SCRAMBLER(__pRxDesc)
-#define GET_RX_DESC_RX_EOF_8822B(__pRxDesc) GET_RX_DESC_RX_EOF(__pRxDesc)
-#define GET_RX_DESC_PATTERN_IDX_8822B(__pRxDesc) GET_RX_DESC_PATTERN_IDX(__pRxDesc)
+#define GET_RX_DESC_A1_FIT_8822B(rxdesc) GET_RX_DESC_A1_FIT(rxdesc)
+#define GET_RX_DESC_MACID_RPT_BUFF_8822B(rxdesc) \
+ GET_RX_DESC_MACID_RPT_BUFF(rxdesc)
+#define GET_RX_DESC_RX_PRE_NDP_VLD_8822B(rxdesc) \
+ GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc)
+#define GET_RX_DESC_RX_SCRAMBLER_8822B(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc)
+#define GET_RX_DESC_RX_EOF_8822B(rxdesc) GET_RX_DESC_RX_EOF(rxdesc)
+#define GET_RX_DESC_PATTERN_IDX_8822B(rxdesc) GET_RX_DESC_PATTERN_IDX(rxdesc)
/*RXDESC_WORD5*/
-#define GET_RX_DESC_TSFL_8822B(__pRxDesc) GET_RX_DESC_TSFL(__pRxDesc)
+#define GET_RX_DESC_TSFL_8822B(rxdesc) GET_RX_DESC_TSFL(rxdesc)
#endif
@@ -152,73 +185,81 @@
/*RXDESC_WORD0*/
-#define GET_RX_DESC_EOR_8197F(__pRxDesc) GET_RX_DESC_EOR(__pRxDesc)
-#define GET_RX_DESC_PHYPKTIDC_8197F(__pRxDesc) GET_RX_DESC_PHYPKTIDC(__pRxDesc)
-#define GET_RX_DESC_SWDEC_8197F(__pRxDesc) GET_RX_DESC_SWDEC(__pRxDesc)
-#define GET_RX_DESC_PHYST_8197F(__pRxDesc) GET_RX_DESC_PHYST(__pRxDesc)
-#define GET_RX_DESC_SHIFT_8197F(__pRxDesc) GET_RX_DESC_SHIFT(__pRxDesc)
-#define GET_RX_DESC_QOS_8197F(__pRxDesc) GET_RX_DESC_QOS(__pRxDesc)
-#define GET_RX_DESC_SECURITY_8197F(__pRxDesc) GET_RX_DESC_SECURITY(__pRxDesc)
-#define GET_RX_DESC_DRV_INFO_SIZE_8197F(__pRxDesc) GET_RX_DESC_DRV_INFO_SIZE(__pRxDesc)
-#define GET_RX_DESC_ICV_ERR_8197F(__pRxDesc) GET_RX_DESC_ICV_ERR(__pRxDesc)
-#define GET_RX_DESC_CRC32_8197F(__pRxDesc) GET_RX_DESC_CRC32(__pRxDesc)
-#define GET_RX_DESC_PKT_LEN_8197F(__pRxDesc) GET_RX_DESC_PKT_LEN(__pRxDesc)
+#define GET_RX_DESC_EOR_8197F(rxdesc) GET_RX_DESC_EOR(rxdesc)
+#define GET_RX_DESC_PHYPKTIDC_8197F(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc)
+#define GET_RX_DESC_SWDEC_8197F(rxdesc) GET_RX_DESC_SWDEC(rxdesc)
+#define GET_RX_DESC_PHYST_8197F(rxdesc) GET_RX_DESC_PHYST(rxdesc)
+#define GET_RX_DESC_SHIFT_8197F(rxdesc) GET_RX_DESC_SHIFT(rxdesc)
+#define GET_RX_DESC_QOS_8197F(rxdesc) GET_RX_DESC_QOS(rxdesc)
+#define GET_RX_DESC_SECURITY_8197F(rxdesc) GET_RX_DESC_SECURITY(rxdesc)
+#define GET_RX_DESC_DRV_INFO_SIZE_8197F(rxdesc) \
+ GET_RX_DESC_DRV_INFO_SIZE(rxdesc)
+#define GET_RX_DESC_ICV_ERR_8197F(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc)
+#define GET_RX_DESC_CRC32_8197F(rxdesc) GET_RX_DESC_CRC32(rxdesc)
+#define GET_RX_DESC_PKT_LEN_8197F(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc)
/*RXDESC_WORD1*/
-#define GET_RX_DESC_BC_8197F(__pRxDesc) GET_RX_DESC_BC(__pRxDesc)
-#define GET_RX_DESC_MC_8197F(__pRxDesc) GET_RX_DESC_MC(__pRxDesc)
-#define GET_RX_DESC_TY_PE_8197F(__pRxDesc) GET_RX_DESC_TY_PE(__pRxDesc)
-#define GET_RX_DESC_MF_8197F(__pRxDesc) GET_RX_DESC_MF(__pRxDesc)
-#define GET_RX_DESC_MD_8197F(__pRxDesc) GET_RX_DESC_MD(__pRxDesc)
-#define GET_RX_DESC_PWR_8197F(__pRxDesc) GET_RX_DESC_PWR(__pRxDesc)
-#define GET_RX_DESC_PAM_8197F(__pRxDesc) GET_RX_DESC_PAM(__pRxDesc)
-#define GET_RX_DESC_CHK_VLD_8197F(__pRxDesc) GET_RX_DESC_CHK_VLD(__pRxDesc)
-#define GET_RX_DESC_RX_IS_TCP_UDP_8197F(__pRxDesc) GET_RX_DESC_RX_IS_TCP_UDP(__pRxDesc)
-#define GET_RX_DESC_RX_IPV_8197F(__pRxDesc) GET_RX_DESC_RX_IPV(__pRxDesc)
-#define GET_RX_DESC_CHKERR_8197F(__pRxDesc) GET_RX_DESC_CHKERR(__pRxDesc)
-#define GET_RX_DESC_PAGGR_8197F(__pRxDesc) GET_RX_DESC_PAGGR(__pRxDesc)
-#define GET_RX_DESC_RXID_MATCH_8197F(__pRxDesc) GET_RX_DESC_RXID_MATCH(__pRxDesc)
-#define GET_RX_DESC_AMSDU_8197F(__pRxDesc) GET_RX_DESC_AMSDU(__pRxDesc)
-#define GET_RX_DESC_MACID_VLD_8197F(__pRxDesc) GET_RX_DESC_MACID_VLD(__pRxDesc)
-#define GET_RX_DESC_TID_8197F(__pRxDesc) GET_RX_DESC_TID(__pRxDesc)
-#define GET_RX_DESC_EXT_SECTYPE_8197F(__pRxDesc) GET_RX_DESC_EXT_SECTYPE(__pRxDesc)
-#define GET_RX_DESC_MACID_8197F(__pRxDesc) GET_RX_DESC_MACID(__pRxDesc)
+#define GET_RX_DESC_BC_8197F(rxdesc) GET_RX_DESC_BC(rxdesc)
+#define GET_RX_DESC_MC_8197F(rxdesc) GET_RX_DESC_MC(rxdesc)
+#define GET_RX_DESC_TY_PE_8197F(rxdesc) GET_RX_DESC_TY_PE(rxdesc)
+#define GET_RX_DESC_MF_8197F(rxdesc) GET_RX_DESC_MF(rxdesc)
+#define GET_RX_DESC_MD_8197F(rxdesc) GET_RX_DESC_MD(rxdesc)
+#define GET_RX_DESC_PWR_8197F(rxdesc) GET_RX_DESC_PWR(rxdesc)
+#define GET_RX_DESC_PAM_8197F(rxdesc) GET_RX_DESC_PAM(rxdesc)
+#define GET_RX_DESC_CHK_VLD_8197F(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc)
+#define GET_RX_DESC_RX_IS_TCP_UDP_8197F(rxdesc) \
+ GET_RX_DESC_RX_IS_TCP_UDP(rxdesc)
+#define GET_RX_DESC_RX_IPV_8197F(rxdesc) GET_RX_DESC_RX_IPV(rxdesc)
+#define GET_RX_DESC_CHKERR_8197F(rxdesc) GET_RX_DESC_CHKERR(rxdesc)
+#define GET_RX_DESC_PAGGR_8197F(rxdesc) GET_RX_DESC_PAGGR(rxdesc)
+#define GET_RX_DESC_RXID_MATCH_8197F(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc)
+#define GET_RX_DESC_AMSDU_8197F(rxdesc) GET_RX_DESC_AMSDU(rxdesc)
+#define GET_RX_DESC_MACID_VLD_8197F(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc)
+#define GET_RX_DESC_TID_8197F(rxdesc) GET_RX_DESC_TID(rxdesc)
+#define GET_RX_DESC_MACID_8197F(rxdesc) GET_RX_DESC_MACID(rxdesc)
/*RXDESC_WORD2*/
-#define GET_RX_DESC_FCS_OK_8197F(__pRxDesc) GET_RX_DESC_FCS_OK(__pRxDesc)
-#define GET_RX_DESC_C2H_8197F(__pRxDesc) GET_RX_DESC_C2H(__pRxDesc)
-#define GET_RX_DESC_HWRSVD_8197F(__pRxDesc) GET_RX_DESC_HWRSVD(__pRxDesc)
-#define GET_RX_DESC_WLANHD_IV_LEN_8197F(__pRxDesc) GET_RX_DESC_WLANHD_IV_LEN(__pRxDesc)
-#define GET_RX_DESC_RX_IS_QOS_8197F(__pRxDesc) GET_RX_DESC_RX_IS_QOS(__pRxDesc)
-#define GET_RX_DESC_FRAG_8197F(__pRxDesc) GET_RX_DESC_FRAG(__pRxDesc)
-#define GET_RX_DESC_SEQ_8197F(__pRxDesc) GET_RX_DESC_SEQ(__pRxDesc)
+#define GET_RX_DESC_FCS_OK_8197F(rxdesc) GET_RX_DESC_FCS_OK(rxdesc)
+#define GET_RX_DESC_C2H_8197F(rxdesc) GET_RX_DESC_C2H(rxdesc)
+#define GET_RX_DESC_HWRSVD_8197F(rxdesc) GET_RX_DESC_HWRSVD(rxdesc)
+#define GET_RX_DESC_WLANHD_IV_LEN_8197F(rxdesc) \
+ GET_RX_DESC_WLANHD_IV_LEN(rxdesc)
+#define GET_RX_DESC_RX_IS_QOS_8197F(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc)
+#define GET_RX_DESC_FRAG_8197F(rxdesc) GET_RX_DESC_FRAG(rxdesc)
+#define GET_RX_DESC_SEQ_8197F(rxdesc) GET_RX_DESC_SEQ(rxdesc)
/*RXDESC_WORD3*/
-#define GET_RX_DESC_MAGIC_WAKE_8197F(__pRxDesc) GET_RX_DESC_MAGIC_WAKE(__pRxDesc)
-#define GET_RX_DESC_UNICAST_WAKE_8197F(__pRxDesc) GET_RX_DESC_UNICAST_WAKE(__pRxDesc)
-#define GET_RX_DESC_PATTERN_MATCH_8197F(__pRxDesc) GET_RX_DESC_PATTERN_MATCH(__pRxDesc)
-#define GET_RX_DESC_DMA_AGG_NUM_8197F(__pRxDesc) GET_RX_DESC_DMA_AGG_NUM(__pRxDesc)
-#define GET_RX_DESC_BSSID_FIT_1_0_8197F(__pRxDesc) GET_RX_DESC_BSSID_FIT_1_0(__pRxDesc)
-#define GET_RX_DESC_EOSP_8197F(__pRxDesc) GET_RX_DESC_EOSP(__pRxDesc)
-#define GET_RX_DESC_HTC_8197F(__pRxDesc) GET_RX_DESC_HTC(__pRxDesc)
-#define GET_RX_DESC_BSSID_FIT_4_2_8197F(__pRxDesc) GET_RX_DESC_BSSID_FIT_4_2(__pRxDesc)
-#define GET_RX_DESC_RX_RATE_8197F(__pRxDesc) GET_RX_DESC_RX_RATE(__pRxDesc)
+#define GET_RX_DESC_MAGIC_WAKE_8197F(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc)
+#define GET_RX_DESC_UNICAST_WAKE_8197F(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc)
+#define GET_RX_DESC_PATTERN_MATCH_8197F(rxdesc) \
+ GET_RX_DESC_PATTERN_MATCH(rxdesc)
+#define GET_RX_DESC_DMA_AGG_NUM_8197F(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_1_0_8197F(rxdesc) \
+ GET_RX_DESC_BSSID_FIT_1_0(rxdesc)
+#define GET_RX_DESC_EOSP_8197F(rxdesc) GET_RX_DESC_EOSP(rxdesc)
+#define GET_RX_DESC_HTC_8197F(rxdesc) GET_RX_DESC_HTC(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_4_2_8197F(rxdesc) \
+ GET_RX_DESC_BSSID_FIT_4_2(rxdesc)
+#define GET_RX_DESC_RX_RATE_8197F(rxdesc) GET_RX_DESC_RX_RATE(rxdesc)
/*RXDESC_WORD4*/
-#define GET_RX_DESC_A1_FIT_8197F(__pRxDesc) GET_RX_DESC_A1_FIT(__pRxDesc)
-#define GET_RX_DESC_MACID_RPT_BUFF_8197F(__pRxDesc) GET_RX_DESC_MACID_RPT_BUFF(__pRxDesc)
-#define GET_RX_DESC_RX_PRE_NDP_VLD_8197F(__pRxDesc) GET_RX_DESC_RX_PRE_NDP_VLD(__pRxDesc)
-#define GET_RX_DESC_RX_SCRAMBLER_8197F(__pRxDesc) GET_RX_DESC_RX_SCRAMBLER(__pRxDesc)
-#define GET_RX_DESC_RX_EOF_8197F(__pRxDesc) GET_RX_DESC_RX_EOF(__pRxDesc)
-#define GET_RX_DESC_PATTERN_IDX_8197F(__pRxDesc) GET_RX_DESC_PATTERN_IDX(__pRxDesc)
+#define GET_RX_DESC_A1_FIT_8197F(rxdesc) GET_RX_DESC_A1_FIT(rxdesc)
+#define GET_RX_DESC_MACID_RPT_BUFF_8197F(rxdesc) \
+ GET_RX_DESC_MACID_RPT_BUFF(rxdesc)
+#define GET_RX_DESC_RX_PRE_NDP_VLD_8197F(rxdesc) \
+ GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc)
+#define GET_RX_DESC_RX_SCRAMBLER_8197F(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc)
+#define GET_RX_DESC_RX_EOF_8197F(rxdesc) GET_RX_DESC_RX_EOF(rxdesc)
+#define GET_RX_DESC_FC_POWER_8197F(rxdesc) GET_RX_DESC_FC_POWER(rxdesc)
+#define GET_RX_DESC_PATTERN_IDX_8197F(rxdesc) GET_RX_DESC_PATTERN_IDX_V1(rxdesc)
/*RXDESC_WORD5*/
-#define GET_RX_DESC_TSFL_8197F(__pRxDesc) GET_RX_DESC_TSFL(__pRxDesc)
+#define GET_RX_DESC_TSFL_8197F(rxdesc) GET_RX_DESC_TSFL(rxdesc)
#endif
@@ -226,143 +267,345 @@
/*RXDESC_WORD0*/
-#define GET_RX_DESC_EOR_8821C(__pRxDesc) GET_RX_DESC_EOR(__pRxDesc)
-#define GET_RX_DESC_PHYPKTIDC_8821C(__pRxDesc) GET_RX_DESC_PHYPKTIDC(__pRxDesc)
-#define GET_RX_DESC_SWDEC_8821C(__pRxDesc) GET_RX_DESC_SWDEC(__pRxDesc)
-#define GET_RX_DESC_PHYST_8821C(__pRxDesc) GET_RX_DESC_PHYST(__pRxDesc)
-#define GET_RX_DESC_SHIFT_8821C(__pRxDesc) GET_RX_DESC_SHIFT(__pRxDesc)
-#define GET_RX_DESC_QOS_8821C(__pRxDesc) GET_RX_DESC_QOS(__pRxDesc)
-#define GET_RX_DESC_SECURITY_8821C(__pRxDesc) GET_RX_DESC_SECURITY(__pRxDesc)
-#define GET_RX_DESC_DRV_INFO_SIZE_8821C(__pRxDesc) GET_RX_DESC_DRV_INFO_SIZE(__pRxDesc)
-#define GET_RX_DESC_ICV_ERR_8821C(__pRxDesc) GET_RX_DESC_ICV_ERR(__pRxDesc)
-#define GET_RX_DESC_CRC32_8821C(__pRxDesc) GET_RX_DESC_CRC32(__pRxDesc)
-#define GET_RX_DESC_PKT_LEN_8821C(__pRxDesc) GET_RX_DESC_PKT_LEN(__pRxDesc)
+#define GET_RX_DESC_EOR_8821C(rxdesc) GET_RX_DESC_EOR(rxdesc)
+#define GET_RX_DESC_PHYPKTIDC_8821C(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc)
+#define GET_RX_DESC_SWDEC_8821C(rxdesc) GET_RX_DESC_SWDEC(rxdesc)
+#define GET_RX_DESC_PHYST_8821C(rxdesc) GET_RX_DESC_PHYST(rxdesc)
+#define GET_RX_DESC_SHIFT_8821C(rxdesc) GET_RX_DESC_SHIFT(rxdesc)
+#define GET_RX_DESC_QOS_8821C(rxdesc) GET_RX_DESC_QOS(rxdesc)
+#define GET_RX_DESC_SECURITY_8821C(rxdesc) GET_RX_DESC_SECURITY(rxdesc)
+#define GET_RX_DESC_DRV_INFO_SIZE_8821C(rxdesc) \
+ GET_RX_DESC_DRV_INFO_SIZE(rxdesc)
+#define GET_RX_DESC_ICV_ERR_8821C(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc)
+#define GET_RX_DESC_CRC32_8821C(rxdesc) GET_RX_DESC_CRC32(rxdesc)
+#define GET_RX_DESC_PKT_LEN_8821C(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc)
+
+/*RXDESC_WORD1*/
+
+#define GET_RX_DESC_BC_8821C(rxdesc) GET_RX_DESC_BC(rxdesc)
+#define GET_RX_DESC_MC_8821C(rxdesc) GET_RX_DESC_MC(rxdesc)
+#define GET_RX_DESC_TY_PE_8821C(rxdesc) GET_RX_DESC_TY_PE(rxdesc)
+#define GET_RX_DESC_MF_8821C(rxdesc) GET_RX_DESC_MF(rxdesc)
+#define GET_RX_DESC_MD_8821C(rxdesc) GET_RX_DESC_MD(rxdesc)
+#define GET_RX_DESC_PWR_8821C(rxdesc) GET_RX_DESC_PWR(rxdesc)
+#define GET_RX_DESC_PAM_8821C(rxdesc) GET_RX_DESC_PAM(rxdesc)
+#define GET_RX_DESC_CHK_VLD_8821C(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc)
+#define GET_RX_DESC_RX_IS_TCP_UDP_8821C(rxdesc) \
+ GET_RX_DESC_RX_IS_TCP_UDP(rxdesc)
+#define GET_RX_DESC_RX_IPV_8821C(rxdesc) GET_RX_DESC_RX_IPV(rxdesc)
+#define GET_RX_DESC_CHKERR_8821C(rxdesc) GET_RX_DESC_CHKERR(rxdesc)
+#define GET_RX_DESC_PAGGR_8821C(rxdesc) GET_RX_DESC_PAGGR(rxdesc)
+#define GET_RX_DESC_RXID_MATCH_8821C(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc)
+#define GET_RX_DESC_AMSDU_8821C(rxdesc) GET_RX_DESC_AMSDU(rxdesc)
+#define GET_RX_DESC_MACID_VLD_8821C(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc)
+#define GET_RX_DESC_TID_8821C(rxdesc) GET_RX_DESC_TID(rxdesc)
+#define GET_RX_DESC_MACID_8821C(rxdesc) GET_RX_DESC_MACID(rxdesc)
+
+/*RXDESC_WORD2*/
+
+#define GET_RX_DESC_FCS_OK_8821C(rxdesc) GET_RX_DESC_FCS_OK(rxdesc)
+#define GET_RX_DESC_PPDU_CNT_8821C(rxdesc) GET_RX_DESC_PPDU_CNT(rxdesc)
+#define GET_RX_DESC_C2H_8821C(rxdesc) GET_RX_DESC_C2H(rxdesc)
+#define GET_RX_DESC_HWRSVD_8821C(rxdesc) GET_RX_DESC_HWRSVD(rxdesc)
+#define GET_RX_DESC_WLANHD_IV_LEN_8821C(rxdesc) \
+ GET_RX_DESC_WLANHD_IV_LEN(rxdesc)
+#define GET_RX_DESC_RX_IS_QOS_8821C(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc)
+#define GET_RX_DESC_FRAG_8821C(rxdesc) GET_RX_DESC_FRAG(rxdesc)
+#define GET_RX_DESC_SEQ_8821C(rxdesc) GET_RX_DESC_SEQ(rxdesc)
+
+/*RXDESC_WORD3*/
+
+#define GET_RX_DESC_MAGIC_WAKE_8821C(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc)
+#define GET_RX_DESC_UNICAST_WAKE_8821C(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc)
+#define GET_RX_DESC_PATTERN_MATCH_8821C(rxdesc) \
+ GET_RX_DESC_PATTERN_MATCH(rxdesc)
+#define GET_RX_DESC_RXPAYLOAD_MATCH_8821C(rxdesc) \
+ GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc)
+#define GET_RX_DESC_RXPAYLOAD_ID_8821C(rxdesc) GET_RX_DESC_RXPAYLOAD_ID(rxdesc)
+#define GET_RX_DESC_DMA_AGG_NUM_8821C(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_1_0_8821C(rxdesc) \
+ GET_RX_DESC_BSSID_FIT_1_0(rxdesc)
+#define GET_RX_DESC_EOSP_8821C(rxdesc) GET_RX_DESC_EOSP(rxdesc)
+#define GET_RX_DESC_HTC_8821C(rxdesc) GET_RX_DESC_HTC(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_4_2_8821C(rxdesc) \
+ GET_RX_DESC_BSSID_FIT_4_2(rxdesc)
+#define GET_RX_DESC_RX_RATE_8821C(rxdesc) GET_RX_DESC_RX_RATE(rxdesc)
+
+/*RXDESC_WORD4*/
+
+#define GET_RX_DESC_A1_FIT_8821C(rxdesc) GET_RX_DESC_A1_FIT(rxdesc)
+#define GET_RX_DESC_MACID_RPT_BUFF_8821C(rxdesc) \
+ GET_RX_DESC_MACID_RPT_BUFF(rxdesc)
+#define GET_RX_DESC_RX_PRE_NDP_VLD_8821C(rxdesc) \
+ GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc)
+#define GET_RX_DESC_RX_SCRAMBLER_8821C(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc)
+#define GET_RX_DESC_RX_EOF_8821C(rxdesc) GET_RX_DESC_RX_EOF(rxdesc)
+#define GET_RX_DESC_PATTERN_IDX_8821C(rxdesc) GET_RX_DESC_PATTERN_IDX(rxdesc)
+
+/*RXDESC_WORD5*/
+
+#define GET_RX_DESC_TSFL_8821C(rxdesc) GET_RX_DESC_TSFL(rxdesc)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+/*RXDESC_WORD0*/
+
+#define GET_RX_DESC_EVT_PKT_8814B(rxdesc) GET_RX_DESC_EVT_PKT(rxdesc)
+#define GET_RX_DESC_SWDEC_8814B(rxdesc) GET_RX_DESC_SWDEC(rxdesc)
+#define GET_RX_DESC_PHYST_8814B(rxdesc) GET_RX_DESC_PHYST(rxdesc)
+#define GET_RX_DESC_SHIFT_8814B(rxdesc) GET_RX_DESC_SHIFT(rxdesc)
+#define GET_RX_DESC_QOS_8814B(rxdesc) GET_RX_DESC_QOS(rxdesc)
+#define GET_RX_DESC_SECURITY_8814B(rxdesc) GET_RX_DESC_SECURITY(rxdesc)
+#define GET_RX_DESC_DRV_INFO_SIZE_8814B(rxdesc) \
+ GET_RX_DESC_DRV_INFO_SIZE(rxdesc)
+#define GET_RX_DESC_ICV_ERR_8814B(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc)
+#define GET_RX_DESC_CRC32_8814B(rxdesc) GET_RX_DESC_CRC32(rxdesc)
+#define GET_RX_DESC_PKT_LEN_8814B(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc)
/*RXDESC_WORD1*/
-#define GET_RX_DESC_BC_8821C(__pRxDesc) GET_RX_DESC_BC(__pRxDesc)
-#define GET_RX_DESC_MC_8821C(__pRxDesc) GET_RX_DESC_MC(__pRxDesc)
-#define GET_RX_DESC_TY_PE_8821C(__pRxDesc) GET_RX_DESC_TY_PE(__pRxDesc)
-#define GET_RX_DESC_MF_8821C(__pRxDesc) GET_RX_DESC_MF(__pRxDesc)
-#define GET_RX_DESC_MD_8821C(__pRxDesc) GET_RX_DESC_MD(__pRxDesc)
-#define GET_RX_DESC_PWR_8821C(__pRxDesc) GET_RX_DESC_PWR(__pRxDesc)
-#define GET_RX_DESC_PAM_8821C(__pRxDesc) GET_RX_DESC_PAM(__pRxDesc)
-#define GET_RX_DESC_CHK_VLD_8821C(__pRxDesc) GET_RX_DESC_CHK_VLD(__pRxDesc)
-#define GET_RX_DESC_RX_IS_TCP_UDP_8821C(__pRxDesc) GET_RX_DESC_RX_IS_TCP_UDP(__pRxDesc)
-#define GET_RX_DESC_RX_IPV_8821C(__pRxDesc) GET_RX_DESC_RX_IPV(__pRxDesc)
-#define GET_RX_DESC_CHKERR_8821C(__pRxDesc) GET_RX_DESC_CHKERR(__pRxDesc)
-#define GET_RX_DESC_PAGGR_8821C(__pRxDesc) GET_RX_DESC_PAGGR(__pRxDesc)
-#define GET_RX_DESC_RXID_MATCH_8821C(__pRxDesc) GET_RX_DESC_RXID_MATCH(__pRxDesc)
-#define GET_RX_DESC_AMSDU_8821C(__pRxDesc) GET_RX_DESC_AMSDU(__pRxDesc)
-#define GET_RX_DESC_MACID_VLD_8821C(__pRxDesc) GET_RX_DESC_MACID_VLD(__pRxDesc)
-#define GET_RX_DESC_TID_8821C(__pRxDesc) GET_RX_DESC_TID(__pRxDesc)
-#define GET_RX_DESC_EXT_SECTYPE_8821C(__pRxDesc) GET_RX_DESC_EXT_SECTYPE(__pRxDesc)
-#define GET_RX_DESC_MACID_8821C(__pRxDesc) GET_RX_DESC_MACID(__pRxDesc)
+#define GET_RX_DESC_BC_8814B(rxdesc) GET_RX_DESC_BC(rxdesc)
+#define GET_RX_DESC_MC_8814B(rxdesc) GET_RX_DESC_MC(rxdesc)
+#define GET_RX_DESC_TYPE_8814B(rxdesc) GET_RX_DESC_TYPE(rxdesc)
+#define GET_RX_DESC_MF_8814B(rxdesc) GET_RX_DESC_MF(rxdesc)
+#define GET_RX_DESC_MD_8814B(rxdesc) GET_RX_DESC_MD(rxdesc)
+#define GET_RX_DESC_PWR_8814B(rxdesc) GET_RX_DESC_PWR(rxdesc)
+#define GET_RX_DESC_A1_MATCH_8814B(rxdesc) GET_RX_DESC_A1_MATCH(rxdesc)
+#define GET_RX_DESC_TCP_CHKSUM_VLD_8814B(rxdesc) \
+ GET_RX_DESC_TCP_CHKSUM_VLD(rxdesc)
+#define GET_RX_DESC_RX_IS_TCP_UDP_8814B(rxdesc) \
+ GET_RX_DESC_RX_IS_TCP_UDP(rxdesc)
+#define GET_RX_DESC_RX_IPV_8814B(rxdesc) GET_RX_DESC_RX_IPV(rxdesc)
+#define GET_RX_DESC_TCP_CHKSUM_ERR_8814B(rxdesc) \
+ GET_RX_DESC_TCP_CHKSUM_ERR(rxdesc)
+#define GET_RX_DESC_PHY_PKT_IDC_8814B(rxdesc) GET_RX_DESC_PHY_PKT_IDC(rxdesc)
+#define GET_RX_DESC_FW_FIFO_FULL_8814B(rxdesc) GET_RX_DESC_FW_FIFO_FULL(rxdesc)
+#define GET_RX_DESC_AMPDU_8814B(rxdesc) GET_RX_DESC_AMPDU(rxdesc)
+#define GET_RX_DESC_RXCMD_IDC_8814B(rxdesc) GET_RX_DESC_RXCMD_IDC(rxdesc)
+#define GET_RX_DESC_AMSDU_8814B(rxdesc) GET_RX_DESC_AMSDU(rxdesc)
+#define GET_RX_DESC_TID_8814B(rxdesc) GET_RX_DESC_TID(rxdesc)
/*RXDESC_WORD2*/
-#define GET_RX_DESC_FCS_OK_8821C(__pRxDesc) GET_RX_DESC_FCS_OK(__pRxDesc)
-#define GET_RX_DESC_C2H_8821C(__pRxDesc) GET_RX_DESC_C2H(__pRxDesc)
-#define GET_RX_DESC_HWRSVD_8821C(__pRxDesc) GET_RX_DESC_HWRSVD(__pRxDesc)
-#define GET_RX_DESC_WLANHD_IV_LEN_8821C(__pRxDesc) GET_RX_DESC_WLANHD_IV_LEN(__pRxDesc)
-#define GET_RX_DESC_RX_IS_QOS_8821C(__pRxDesc) GET_RX_DESC_RX_IS_QOS(__pRxDesc)
-#define GET_RX_DESC_FRAG_8821C(__pRxDesc) GET_RX_DESC_FRAG(__pRxDesc)
-#define GET_RX_DESC_SEQ_8821C(__pRxDesc) GET_RX_DESC_SEQ(__pRxDesc)
+#define GET_RX_DESC_AMSDU_CUT_8814B(rxdesc) GET_RX_DESC_AMSDU_CUT(rxdesc)
+#define GET_RX_DESC_PPDU_CNT_8814B(rxdesc) GET_RX_DESC_PPDU_CNT(rxdesc)
+#define GET_RX_DESC_C2H_8814B(rxdesc) GET_RX_DESC_C2H(rxdesc)
+#define GET_RX_DESC_WLANHD_IV_LEN_8814B(rxdesc) \
+ GET_RX_DESC_WLANHD_IV_LEN(rxdesc)
+#define GET_RX_DESC_LAST_MSDU_8814B(rxdesc) GET_RX_DESC_LAST_MSDU(rxdesc)
+#define GET_RX_DESC_EXT_SEC_TYPE_8814B(rxdesc) GET_RX_DESC_EXT_SEC_TYPE(rxdesc)
+#define GET_RX_DESC_FRAG_8814B(rxdesc) GET_RX_DESC_FRAG(rxdesc)
+#define GET_RX_DESC_SEQ_8814B(rxdesc) GET_RX_DESC_SEQ(rxdesc)
/*RXDESC_WORD3*/
-#define GET_RX_DESC_MAGIC_WAKE_8821C(__pRxDesc) GET_RX_DESC_MAGIC_WAKE(__pRxDesc)
-#define GET_RX_DESC_UNICAST_WAKE_8821C(__pRxDesc) GET_RX_DESC_UNICAST_WAKE(__pRxDesc)
-#define GET_RX_DESC_PATTERN_MATCH_8821C(__pRxDesc) GET_RX_DESC_PATTERN_MATCH(__pRxDesc)
-#define GET_RX_DESC_DMA_AGG_NUM_8821C(__pRxDesc) GET_RX_DESC_DMA_AGG_NUM(__pRxDesc)
-#define GET_RX_DESC_BSSID_FIT_1_0_8821C(__pRxDesc) GET_RX_DESC_BSSID_FIT_1_0(__pRxDesc)
-#define GET_RX_DESC_EOSP_8821C(__pRxDesc) GET_RX_DESC_EOSP(__pRxDesc)
-#define GET_RX_DESC_HTC_8821C(__pRxDesc) GET_RX_DESC_HTC(__pRxDesc)
-#define GET_RX_DESC_BSSID_FIT_4_2_8821C(__pRxDesc) GET_RX_DESC_BSSID_FIT_4_2(__pRxDesc)
-#define GET_RX_DESC_RX_RATE_8821C(__pRxDesc) GET_RX_DESC_RX_RATE(__pRxDesc)
+#define GET_RX_DESC_MAGIC_WAKE_8814B(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc)
+#define GET_RX_DESC_UNICAST_WAKE_8814B(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc)
+#define GET_RX_DESC_PATTERN_WAKE_8814B(rxdesc) GET_RX_DESC_PATTERN_WAKE(rxdesc)
+#define GET_RX_DESC_RXPAYLOAD_MATCH_8814B(rxdesc) \
+ GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc)
+#define GET_RX_DESC_RXPAYLOAD_ID_8814B(rxdesc) GET_RX_DESC_RXPAYLOAD_ID(rxdesc)
+#define GET_RX_DESC_DMA_AGG_NUM_8814B(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_8814B(rxdesc) GET_RX_DESC_BSSID_FIT(rxdesc)
+#define GET_RX_DESC_HTC_8814B(rxdesc) GET_RX_DESC_HTC(rxdesc)
+#define GET_RX_DESC_AMPDU_END_PKT_8814B(rxdesc) \
+ GET_RX_DESC_AMPDU_END_PKT(rxdesc)
+#define GET_RX_DESC_ADDRESS_CAM_VLD_8814B(rxdesc) \
+ GET_RX_DESC_ADDRESS_CAM_VLD(rxdesc)
+#define GET_RX_DESC_EOSP_8814B(rxdesc) GET_RX_DESC_EOSP_V1(rxdesc)
+#define GET_RX_DESC_RX_RATE_8814B(rxdesc) GET_RX_DESC_RX_RATE(rxdesc)
/*RXDESC_WORD4*/
-#define GET_RX_DESC_A1_FIT_8821C(__pRxDesc) GET_RX_DESC_A1_FIT(__pRxDesc)
-#define GET_RX_DESC_MACID_RPT_BUFF_8821C(__pRxDesc) GET_RX_DESC_MACID_RPT_BUFF(__pRxDesc)
-#define GET_RX_DESC_RX_PRE_NDP_VLD_8821C(__pRxDesc) GET_RX_DESC_RX_PRE_NDP_VLD(__pRxDesc)
-#define GET_RX_DESC_RX_SCRAMBLER_8821C(__pRxDesc) GET_RX_DESC_RX_SCRAMBLER(__pRxDesc)
-#define GET_RX_DESC_RX_EOF_8821C(__pRxDesc) GET_RX_DESC_RX_EOF(__pRxDesc)
-#define GET_RX_DESC_PATTERN_IDX_8821C(__pRxDesc) GET_RX_DESC_PATTERN_IDX(__pRxDesc)
+#define GET_RX_DESC_ADDRESS_CAM_8814B(rxdesc) GET_RX_DESC_ADDRESS_CAM(rxdesc)
+#define GET_RX_DESC_MACID_VLD_8814B(rxdesc) GET_RX_DESC_MACID_VLD_V1(rxdesc)
+#define GET_RX_DESC_MACID_8814B(rxdesc) GET_RX_DESC_MACID_V1(rxdesc)
+#define GET_RX_DESC_SWPS_RPT_8814B(rxdesc) GET_RX_DESC_SWPS_RPT(rxdesc)
+#define GET_RX_DESC_PATTERN_IDX_8814B(rxdesc) GET_RX_DESC_PATTERN_IDX_V2(rxdesc)
/*RXDESC_WORD5*/
-#define GET_RX_DESC_TSFL_8821C(__pRxDesc) GET_RX_DESC_TSFL(__pRxDesc)
+#define GET_RX_DESC_FREERUN_CNT_8814B(rxdesc) GET_RX_DESC_FREERUN_CNT(rxdesc)
#endif
-#if (HALMAC_8188F_SUPPORT)
+#if (HALMAC_8198F_SUPPORT)
/*RXDESC_WORD0*/
-#define GET_RX_DESC_EOR_8188F(__pRxDesc) GET_RX_DESC_EOR(__pRxDesc)
-#define GET_RX_DESC_PHYPKTIDC_8188F(__pRxDesc) GET_RX_DESC_PHYPKTIDC(__pRxDesc)
-#define GET_RX_DESC_SWDEC_8188F(__pRxDesc) GET_RX_DESC_SWDEC(__pRxDesc)
-#define GET_RX_DESC_PHYST_8188F(__pRxDesc) GET_RX_DESC_PHYST(__pRxDesc)
-#define GET_RX_DESC_SHIFT_8188F(__pRxDesc) GET_RX_DESC_SHIFT(__pRxDesc)
-#define GET_RX_DESC_QOS_8188F(__pRxDesc) GET_RX_DESC_QOS(__pRxDesc)
-#define GET_RX_DESC_SECURITY_8188F(__pRxDesc) GET_RX_DESC_SECURITY(__pRxDesc)
-#define GET_RX_DESC_DRV_INFO_SIZE_8188F(__pRxDesc) GET_RX_DESC_DRV_INFO_SIZE(__pRxDesc)
-#define GET_RX_DESC_ICV_ERR_8188F(__pRxDesc) GET_RX_DESC_ICV_ERR(__pRxDesc)
-#define GET_RX_DESC_CRC32_8188F(__pRxDesc) GET_RX_DESC_CRC32(__pRxDesc)
-#define GET_RX_DESC_PKT_LEN_8188F(__pRxDesc) GET_RX_DESC_PKT_LEN(__pRxDesc)
+#define GET_RX_DESC_EOR_8198F(rxdesc) GET_RX_DESC_EOR(rxdesc)
+#define GET_RX_DESC_PHYPKTIDC_8198F(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc)
+#define GET_RX_DESC_SWDEC_8198F(rxdesc) GET_RX_DESC_SWDEC(rxdesc)
+#define GET_RX_DESC_PHYST_8198F(rxdesc) GET_RX_DESC_PHYST(rxdesc)
+#define GET_RX_DESC_SHIFT_8198F(rxdesc) GET_RX_DESC_SHIFT(rxdesc)
+#define GET_RX_DESC_QOS_8198F(rxdesc) GET_RX_DESC_QOS(rxdesc)
+#define GET_RX_DESC_SECURITY_8198F(rxdesc) GET_RX_DESC_SECURITY(rxdesc)
+#define GET_RX_DESC_DRV_INFO_SIZE_8198F(rxdesc) \
+ GET_RX_DESC_DRV_INFO_SIZE(rxdesc)
+#define GET_RX_DESC_ICV_ERR_8198F(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc)
+#define GET_RX_DESC_CRC32_8198F(rxdesc) GET_RX_DESC_CRC32(rxdesc)
+#define GET_RX_DESC_PKT_LEN_8198F(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc)
/*RXDESC_WORD1*/
-#define GET_RX_DESC_BC_8188F(__pRxDesc) GET_RX_DESC_BC(__pRxDesc)
-#define GET_RX_DESC_MC_8188F(__pRxDesc) GET_RX_DESC_MC(__pRxDesc)
-#define GET_RX_DESC_TY_PE_8188F(__pRxDesc) GET_RX_DESC_TY_PE(__pRxDesc)
-#define GET_RX_DESC_MF_8188F(__pRxDesc) GET_RX_DESC_MF(__pRxDesc)
-#define GET_RX_DESC_MD_8188F(__pRxDesc) GET_RX_DESC_MD(__pRxDesc)
-#define GET_RX_DESC_PWR_8188F(__pRxDesc) GET_RX_DESC_PWR(__pRxDesc)
-#define GET_RX_DESC_PAM_8188F(__pRxDesc) GET_RX_DESC_PAM(__pRxDesc)
-#define GET_RX_DESC_CHK_VLD_8188F(__pRxDesc) GET_RX_DESC_CHK_VLD(__pRxDesc)
-#define GET_RX_DESC_RX_IS_TCP_UDP_8188F(__pRxDesc) GET_RX_DESC_RX_IS_TCP_UDP(__pRxDesc)
-#define GET_RX_DESC_RX_IPV_8188F(__pRxDesc) GET_RX_DESC_RX_IPV(__pRxDesc)
-#define GET_RX_DESC_CHKERR_8188F(__pRxDesc) GET_RX_DESC_CHKERR(__pRxDesc)
-#define GET_RX_DESC_PAGGR_8188F(__pRxDesc) GET_RX_DESC_PAGGR(__pRxDesc)
-#define GET_RX_DESC_RXID_MATCH_8188F(__pRxDesc) GET_RX_DESC_RXID_MATCH(__pRxDesc)
-#define GET_RX_DESC_AMSDU_8188F(__pRxDesc) GET_RX_DESC_AMSDU(__pRxDesc)
-#define GET_RX_DESC_MACID_VLD_8188F(__pRxDesc) GET_RX_DESC_MACID_VLD(__pRxDesc)
-#define GET_RX_DESC_TID_8188F(__pRxDesc) GET_RX_DESC_TID(__pRxDesc)
-#define GET_RX_DESC_MACID_8188F(__pRxDesc) GET_RX_DESC_MACID(__pRxDesc)
+#define GET_RX_DESC_BC_8198F(rxdesc) GET_RX_DESC_BC(rxdesc)
+#define GET_RX_DESC_MC_8198F(rxdesc) GET_RX_DESC_MC(rxdesc)
+#define GET_RX_DESC_TY_PE_8198F(rxdesc) GET_RX_DESC_TY_PE(rxdesc)
+#define GET_RX_DESC_MF_8198F(rxdesc) GET_RX_DESC_MF(rxdesc)
+#define GET_RX_DESC_MD_8198F(rxdesc) GET_RX_DESC_MD(rxdesc)
+#define GET_RX_DESC_PWR_8198F(rxdesc) GET_RX_DESC_PWR(rxdesc)
+#define GET_RX_DESC_PAM_8198F(rxdesc) GET_RX_DESC_PAM(rxdesc)
+#define GET_RX_DESC_CHK_VLD_8198F(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc)
+#define GET_RX_DESC_RX_IS_TCP_UDP_8198F(rxdesc) \
+ GET_RX_DESC_RX_IS_TCP_UDP(rxdesc)
+#define GET_RX_DESC_RX_IPV_8198F(rxdesc) GET_RX_DESC_RX_IPV(rxdesc)
+#define GET_RX_DESC_CHKERR_8198F(rxdesc) GET_RX_DESC_CHKERR(rxdesc)
+#define GET_RX_DESC_PAGGR_8198F(rxdesc) GET_RX_DESC_PAGGR(rxdesc)
+#define GET_RX_DESC_RXID_MATCH_8198F(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc)
+#define GET_RX_DESC_AMSDU_8198F(rxdesc) GET_RX_DESC_AMSDU(rxdesc)
+#define GET_RX_DESC_MACID_VLD_8198F(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc)
+#define GET_RX_DESC_TID_8198F(rxdesc) GET_RX_DESC_TID(rxdesc)
+#define GET_RX_DESC_MACID_8198F(rxdesc) GET_RX_DESC_MACID(rxdesc)
/*RXDESC_WORD2*/
-#define GET_RX_DESC_FCS_OK_8188F(__pRxDesc) GET_RX_DESC_FCS_OK(__pRxDesc)
-#define GET_RX_DESC_C2H_8188F(__pRxDesc) GET_RX_DESC_C2H(__pRxDesc)
-#define GET_RX_DESC_HWRSVD_8188F(__pRxDesc) GET_RX_DESC_HWRSVD(__pRxDesc)
-#define GET_RX_DESC_WLANHD_IV_LEN_8188F(__pRxDesc) GET_RX_DESC_WLANHD_IV_LEN(__pRxDesc)
-#define GET_RX_DESC_RX_IS_QOS_8188F(__pRxDesc) GET_RX_DESC_RX_IS_QOS(__pRxDesc)
-#define GET_RX_DESC_FRAG_8188F(__pRxDesc) GET_RX_DESC_FRAG(__pRxDesc)
-#define GET_RX_DESC_SEQ_8188F(__pRxDesc) GET_RX_DESC_SEQ(__pRxDesc)
+#define GET_RX_DESC_FCS_OK_8198F(rxdesc) GET_RX_DESC_FCS_OK(rxdesc)
+#define GET_RX_DESC_PPDU_CNT_8198F(rxdesc) GET_RX_DESC_PPDU_CNT(rxdesc)
+#define GET_RX_DESC_C2H_8198F(rxdesc) GET_RX_DESC_C2H(rxdesc)
+#define GET_RX_DESC_HWRSVD_8198F(rxdesc) GET_RX_DESC_HWRSVD_V1(rxdesc)
+#define GET_RX_DESC_RXMAGPKT_8198F(rxdesc) GET_RX_DESC_RXMAGPKT(rxdesc)
+#define GET_RX_DESC_WLANHD_IV_LEN_8198F(rxdesc) \
+ GET_RX_DESC_WLANHD_IV_LEN(rxdesc)
+#define GET_RX_DESC_RX_IS_QOS_8198F(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc)
+#define GET_RX_DESC_FRAG_8198F(rxdesc) GET_RX_DESC_FRAG(rxdesc)
+#define GET_RX_DESC_SEQ_8198F(rxdesc) GET_RX_DESC_SEQ(rxdesc)
/*RXDESC_WORD3*/
-#define GET_RX_DESC_MAGIC_WAKE_8188F(__pRxDesc) GET_RX_DESC_MAGIC_WAKE(__pRxDesc)
-#define GET_RX_DESC_UNICAST_WAKE_8188F(__pRxDesc) GET_RX_DESC_UNICAST_WAKE(__pRxDesc)
-#define GET_RX_DESC_PATTERN_MATCH_8188F(__pRxDesc) GET_RX_DESC_PATTERN_MATCH(__pRxDesc)
-#define GET_RX_DESC_DMA_AGG_NUM_8188F(__pRxDesc) GET_RX_DESC_DMA_AGG_NUM(__pRxDesc)
-#define GET_RX_DESC_BSSID_FIT_1_0_8188F(__pRxDesc) GET_RX_DESC_BSSID_FIT_1_0(__pRxDesc)
-#define GET_RX_DESC_EOSP_8188F(__pRxDesc) GET_RX_DESC_EOSP(__pRxDesc)
-#define GET_RX_DESC_HTC_8188F(__pRxDesc) GET_RX_DESC_HTC(__pRxDesc)
-#define GET_RX_DESC_RX_RATE_8188F(__pRxDesc) GET_RX_DESC_RX_RATE(__pRxDesc)
+#define GET_RX_DESC_MAGIC_WAKE_8198F(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc)
+#define GET_RX_DESC_UNICAST_WAKE_8198F(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc)
+#define GET_RX_DESC_PATTERN_MATCH_8198F(rxdesc) \
+ GET_RX_DESC_PATTERN_MATCH(rxdesc)
+#define GET_RX_DESC_RXPAYLOAD_MATCH_8198F(rxdesc) \
+ GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc)
+#define GET_RX_DESC_RXPAYLOAD_ID_8198F(rxdesc) GET_RX_DESC_RXPAYLOAD_ID(rxdesc)
+#define GET_RX_DESC_DMA_AGG_NUM_8198F(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_1_0_8198F(rxdesc) \
+ GET_RX_DESC_BSSID_FIT_1_0(rxdesc)
+#define GET_RX_DESC_EOSP_8198F(rxdesc) GET_RX_DESC_EOSP(rxdesc)
+#define GET_RX_DESC_HTC_8198F(rxdesc) GET_RX_DESC_HTC(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_4_2_8198F(rxdesc) \
+ GET_RX_DESC_BSSID_FIT_4_2(rxdesc)
+#define GET_RX_DESC_RX_RATE_8198F(rxdesc) GET_RX_DESC_RX_RATE(rxdesc)
/*RXDESC_WORD4*/
-#define GET_RX_DESC_A1_FIT_8188F(__pRxDesc) GET_RX_DESC_A1_FIT(__pRxDesc)
-#define GET_RX_DESC_PATTERN_IDX_8188F(__pRxDesc) GET_RX_DESC_PATTERN_IDX(__pRxDesc)
+#define GET_RX_DESC_A1_FIT_A1_8198F(rxdesc) GET_RX_DESC_A1_FIT_A1(rxdesc)
+#define GET_RX_DESC_MACID_RPT_BUFF_8198F(rxdesc) \
+ GET_RX_DESC_MACID_RPT_BUFF(rxdesc)
+#define GET_RX_DESC_RX_PRE_NDP_VLD_8198F(rxdesc) \
+ GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc)
+#define GET_RX_DESC_RX_SCRAMBLER_8198F(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc)
+#define GET_RX_DESC_RX_EOF_8198F(rxdesc) GET_RX_DESC_RX_EOF(rxdesc)
+#define GET_RX_DESC_FC_POWER_8198F(rxdesc) GET_RX_DESC_FC_POWER(rxdesc)
+#define GET_RX_DESC_TXRPTMID_CTL_MASK_8198F(rxdesc) \
+ GET_RX_DESC_TXRPTMID_CTL_MASK(rxdesc)
+#define GET_RX_DESC_SWPS_RPT_8198F(rxdesc) GET_RX_DESC_SWPS_RPT(rxdesc)
+#define GET_RX_DESC_PATTERN_IDX_8198F(rxdesc) GET_RX_DESC_PATTERN_IDX_V1(rxdesc)
/*RXDESC_WORD5*/
-#define GET_RX_DESC_TSFL_8188F(__pRxDesc) GET_RX_DESC_TSFL(__pRxDesc)
+#define GET_RX_DESC_TSFL_8198F(rxdesc) GET_RX_DESC_TSFL(rxdesc)
#endif
+#if (HALMAC_8822C_SUPPORT)
+
+/*RXDESC_WORD0*/
+
+#define GET_RX_DESC_EOR_8822C(rxdesc) GET_RX_DESC_EOR(rxdesc)
+#define GET_RX_DESC_PHYPKTIDC_8822C(rxdesc) GET_RX_DESC_PHYPKTIDC(rxdesc)
+#define GET_RX_DESC_SWDEC_8822C(rxdesc) GET_RX_DESC_SWDEC(rxdesc)
+#define GET_RX_DESC_PHYST_8822C(rxdesc) GET_RX_DESC_PHYST(rxdesc)
+#define GET_RX_DESC_SHIFT_8822C(rxdesc) GET_RX_DESC_SHIFT(rxdesc)
+#define GET_RX_DESC_QOS_8822C(rxdesc) GET_RX_DESC_QOS(rxdesc)
+#define GET_RX_DESC_SECURITY_8822C(rxdesc) GET_RX_DESC_SECURITY(rxdesc)
+#define GET_RX_DESC_DRV_INFO_SIZE_8822C(rxdesc) \
+ GET_RX_DESC_DRV_INFO_SIZE(rxdesc)
+#define GET_RX_DESC_ICV_ERR_8822C(rxdesc) GET_RX_DESC_ICV_ERR(rxdesc)
+#define GET_RX_DESC_CRC32_8822C(rxdesc) GET_RX_DESC_CRC32(rxdesc)
+#define GET_RX_DESC_PKT_LEN_8822C(rxdesc) GET_RX_DESC_PKT_LEN(rxdesc)
+
+/*RXDESC_WORD1*/
+
+#define GET_RX_DESC_BC_8822C(rxdesc) GET_RX_DESC_BC(rxdesc)
+#define GET_RX_DESC_MC_8822C(rxdesc) GET_RX_DESC_MC(rxdesc)
+#define GET_RX_DESC_TY_PE_8822C(rxdesc) GET_RX_DESC_TY_PE(rxdesc)
+#define GET_RX_DESC_MF_8822C(rxdesc) GET_RX_DESC_MF(rxdesc)
+#define GET_RX_DESC_MD_8822C(rxdesc) GET_RX_DESC_MD(rxdesc)
+#define GET_RX_DESC_PWR_8822C(rxdesc) GET_RX_DESC_PWR(rxdesc)
+#define GET_RX_DESC_PAM_8822C(rxdesc) GET_RX_DESC_PAM(rxdesc)
+#define GET_RX_DESC_CHK_VLD_8822C(rxdesc) GET_RX_DESC_CHK_VLD(rxdesc)
+#define GET_RX_DESC_RX_IS_TCP_UDP_8822C(rxdesc) \
+ GET_RX_DESC_RX_IS_TCP_UDP(rxdesc)
+#define GET_RX_DESC_RX_IPV_8822C(rxdesc) GET_RX_DESC_RX_IPV(rxdesc)
+#define GET_RX_DESC_CHKERR_8822C(rxdesc) GET_RX_DESC_CHKERR(rxdesc)
+#define GET_RX_DESC_PAGGR_8822C(rxdesc) GET_RX_DESC_PAGGR(rxdesc)
+#define GET_RX_DESC_RXID_MATCH_8822C(rxdesc) GET_RX_DESC_RXID_MATCH(rxdesc)
+#define GET_RX_DESC_AMSDU_8822C(rxdesc) GET_RX_DESC_AMSDU(rxdesc)
+#define GET_RX_DESC_MACID_VLD_8822C(rxdesc) GET_RX_DESC_MACID_VLD(rxdesc)
+#define GET_RX_DESC_TID_8822C(rxdesc) GET_RX_DESC_TID(rxdesc)
+#define GET_RX_DESC_MACID_8822C(rxdesc) GET_RX_DESC_MACID(rxdesc)
+
+/*RXDESC_WORD2*/
+
+#define GET_RX_DESC_FCS_OK_8822C(rxdesc) GET_RX_DESC_FCS_OK(rxdesc)
+#define GET_RX_DESC_PPDU_CNT_8822C(rxdesc) GET_RX_DESC_PPDU_CNT(rxdesc)
+#define GET_RX_DESC_C2H_8822C(rxdesc) GET_RX_DESC_C2H(rxdesc)
+#define GET_RX_DESC_HWRSVD_8822C(rxdesc) GET_RX_DESC_HWRSVD(rxdesc)
+#define GET_RX_DESC_WLANHD_IV_LEN_8822C(rxdesc) \
+ GET_RX_DESC_WLANHD_IV_LEN(rxdesc)
+#define GET_RX_DESC_RX_STATISTICS_8822C(rxdesc) \
+ GET_RX_DESC_RX_STATISTICS(rxdesc)
+#define GET_RX_DESC_RX_IS_QOS_8822C(rxdesc) GET_RX_DESC_RX_IS_QOS(rxdesc)
+#define GET_RX_DESC_FRAG_8822C(rxdesc) GET_RX_DESC_FRAG(rxdesc)
+#define GET_RX_DESC_SEQ_8822C(rxdesc) GET_RX_DESC_SEQ(rxdesc)
+
+/*RXDESC_WORD3*/
+
+#define GET_RX_DESC_MAGIC_WAKE_8822C(rxdesc) GET_RX_DESC_MAGIC_WAKE(rxdesc)
+#define GET_RX_DESC_UNICAST_WAKE_8822C(rxdesc) GET_RX_DESC_UNICAST_WAKE(rxdesc)
+#define GET_RX_DESC_PATTERN_MATCH_8822C(rxdesc) \
+ GET_RX_DESC_PATTERN_MATCH(rxdesc)
+#define GET_RX_DESC_RXPAYLOAD_MATCH_8822C(rxdesc) \
+ GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc)
+#define GET_RX_DESC_RXPAYLOAD_ID_8822C(rxdesc) GET_RX_DESC_RXPAYLOAD_ID(rxdesc)
+#define GET_RX_DESC_DMA_AGG_NUM_8822C(rxdesc) GET_RX_DESC_DMA_AGG_NUM(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_1_0_8822C(rxdesc) \
+ GET_RX_DESC_BSSID_FIT_1_0(rxdesc)
+#define GET_RX_DESC_EOSP_8822C(rxdesc) GET_RX_DESC_EOSP(rxdesc)
+#define GET_RX_DESC_HTC_8822C(rxdesc) GET_RX_DESC_HTC(rxdesc)
+#define GET_RX_DESC_BSSID_FIT_4_2_8822C(rxdesc) \
+ GET_RX_DESC_BSSID_FIT_4_2(rxdesc)
+#define GET_RX_DESC_RX_RATE_8822C(rxdesc) GET_RX_DESC_RX_RATE(rxdesc)
+
+/*RXDESC_WORD4*/
+
+#define GET_RX_DESC_A1_FIT_8822C(rxdesc) GET_RX_DESC_A1_FIT(rxdesc)
+#define GET_RX_DESC_MACID_RPT_BUFF_8822C(rxdesc) \
+ GET_RX_DESC_MACID_RPT_BUFF(rxdesc)
+#define GET_RX_DESC_RX_PRE_NDP_VLD_8822C(rxdesc) \
+ GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc)
+#define GET_RX_DESC_RX_SCRAMBLER_8822C(rxdesc) GET_RX_DESC_RX_SCRAMBLER(rxdesc)
+#define GET_RX_DESC_RX_EOF_8822C(rxdesc) GET_RX_DESC_RX_EOF(rxdesc)
+#define GET_RX_DESC_PATTERN_IDX_8822C(rxdesc) GET_RX_DESC_PATTERN_IDX(rxdesc)
+
+/*RXDESC_WORD5*/
+
+#define GET_RX_DESC_TSFL_8822C(rxdesc) GET_RX_DESC_TSFL(rxdesc)
+
+#endif
#endif
diff --git a/hal/halmac/halmac_rx_desc_nic.h b/hal/halmac/halmac_rx_desc_nic.h
index 7722df1..a3baf98 100644
--- a/hal/halmac/halmac_rx_desc_nic.h
+++ b/hal/halmac/halmac_rx_desc_nic.h
@@ -1,108 +1,462 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
#ifndef _HALMAC_RX_DESC_NIC_H_
#define _HALMAC_RX_DESC_NIC_H_
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
/*RXDESC_WORD0*/
-#define GET_RX_DESC_EOR(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 30, 1)
-#define GET_RX_DESC_PHYPKTIDC(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 28, 1)
-#define GET_RX_DESC_SWDEC(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 27, 1)
-#define GET_RX_DESC_PHYST(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 26, 1)
-#define GET_RX_DESC_SHIFT(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 24, 2)
-#define GET_RX_DESC_QOS(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 23, 1)
-#define GET_RX_DESC_SECURITY(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 20, 3)
-#define GET_RX_DESC_DRV_INFO_SIZE(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 16, 4)
-#define GET_RX_DESC_ICV_ERR(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 15, 1)
-#define GET_RX_DESC_CRC32(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 14, 1)
-#define GET_RX_DESC_PKT_LEN(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 0, 14)
+#define GET_RX_DESC_EOR(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 30, 1)
+#define GET_RX_DESC_PHYPKTIDC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 28, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_EVT_PKT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 28, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_SWDEC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 27, 1)
+#define GET_RX_DESC_PHYST(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 26, 1)
+#define GET_RX_DESC_SHIFT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 24, 2)
+#define GET_RX_DESC_QOS(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 23, 1)
+#define GET_RX_DESC_SECURITY(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 20, 3)
+#define GET_RX_DESC_DRV_INFO_SIZE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 16, 4)
+#define GET_RX_DESC_ICV_ERR(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 15, 1)
+#define GET_RX_DESC_CRC32(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 14, 1)
+#define GET_RX_DESC_PKT_LEN(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x00, 0, 14)
/*RXDESC_WORD1*/
-#define GET_RX_DESC_BC(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 31, 1)
-#define GET_RX_DESC_MC(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 30, 1)
-#define GET_RX_DESC_TY_PE(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 28, 2)
-#define GET_RX_DESC_MF(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 27, 1)
-#define GET_RX_DESC_MD(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 26, 1)
-#define GET_RX_DESC_PWR(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 25, 1)
-#define GET_RX_DESC_PAM(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 24, 1)
-#define GET_RX_DESC_CHK_VLD(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 23, 1)
-#define GET_RX_DESC_RX_IS_TCP_UDP(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 22, 1)
-#define GET_RX_DESC_RX_IPV(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 21, 1)
-#define GET_RX_DESC_CHKERR(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 20, 1)
-#define GET_RX_DESC_PAGGR(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 15, 1)
-#define GET_RX_DESC_RXID_MATCH(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 14, 1)
-#define GET_RX_DESC_AMSDU(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 13, 1)
-#define GET_RX_DESC_MACID_VLD(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 12, 1)
-#define GET_RX_DESC_TID(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 8, 4)
+#define GET_RX_DESC_BC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 31, 1)
+#define GET_RX_DESC_MC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 30, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_TY_PE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 28, 2)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_TYPE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 28, 2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_MF(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 27, 1)
+#define GET_RX_DESC_MD(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 26, 1)
+#define GET_RX_DESC_PWR(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 25, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_PAM(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 24, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_A1_MATCH(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 24, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_CHK_VLD(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 23, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_TCP_CHKSUM_VLD(rxdesc) \
+ LE_BITS_TO_4BYTE(rxdesc + 0x04, 23, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_RX_IS_TCP_UDP(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 22, 1)
+#define GET_RX_DESC_RX_IPV(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 21, 1)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
-#define GET_RX_DESC_EXT_SECTYPE(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 7, 1)
+#define GET_RX_DESC_CHKERR(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 20, 1)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_TCP_CHKSUM_ERR(rxdesc) \
+ LE_BITS_TO_4BYTE(rxdesc + 0x04, 20, 1)
+#define GET_RX_DESC_PHY_PKT_IDC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 17, 1)
+#define GET_RX_DESC_FW_FIFO_FULL(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 16, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_PAGGR(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 15, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_AMPDU(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 15, 1)
+
+#endif
-#define GET_RX_DESC_MACID(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 0, 7)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_RXID_MATCH(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 14, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_RXCMD_IDC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 14, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_AMSDU(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 13, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_MACID_VLD(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 12, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_TID(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 8, 4)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_MACID(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x04, 0, 7)
/*RXDESC_WORD2*/
-#define GET_RX_DESC_FCS_OK(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x08, 31, 1)
-#define GET_RX_DESC_C2H(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x08, 28, 1)
-#define GET_RX_DESC_HWRSVD(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x08, 24, 4)
-#define GET_RX_DESC_WLANHD_IV_LEN(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x08, 18, 6)
-#define GET_RX_DESC_RX_IS_QOS(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x08, 16, 1)
-#define GET_RX_DESC_FRAG(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x08, 12, 4)
-#define GET_RX_DESC_SEQ(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x08, 0, 12)
+#define GET_RX_DESC_FCS_OK(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 31, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_AMSDU_CUT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 31, 1)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_PPDU_CNT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 29, 2)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_C2H(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 28, 1)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_HWRSVD_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 25, 3)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_HWRSVD(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 24, 4)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_RXMAGPKT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 24, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_WLANHD_IV_LEN(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 18, 6)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_LAST_MSDU(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 17, 1)
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_RX_STATISTICS(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 17, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_RX_IS_QOS(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 16, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_EXT_SEC_TYPE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 16, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_FRAG(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 12, 4)
+#define GET_RX_DESC_SEQ(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x08, 0, 12)
/*RXDESC_WORD3*/
-#define GET_RX_DESC_MAGIC_WAKE(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 31, 1)
-#define GET_RX_DESC_UNICAST_WAKE(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 30, 1)
-#define GET_RX_DESC_PATTERN_MATCH(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 29, 1)
-#define GET_RX_DESC_DMA_AGG_NUM(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 16, 8)
-#define GET_RX_DESC_BSSID_FIT_1_0(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 12, 2)
-#define GET_RX_DESC_EOSP(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 11, 1)
-#define GET_RX_DESC_HTC(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 10, 1)
+#define GET_RX_DESC_MAGIC_WAKE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 31, 1)
+#define GET_RX_DESC_UNICAST_WAKE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 30, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_PATTERN_MATCH(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 29, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_PATTERN_WAKE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 29, 1)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || \
+ HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
-#define GET_RX_DESC_BSSID_FIT_4_2(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 7, 3)
+#define GET_RX_DESC_RXPAYLOAD_MATCH(rxdesc) \
+ LE_BITS_TO_4BYTE(rxdesc + 0x0C, 28, 1)
+#define GET_RX_DESC_RXPAYLOAD_ID(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 24, 4)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define GET_RX_DESC_RX_RATE(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 0, 7)
+#define GET_RX_DESC_DMA_AGG_NUM(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 16, 8)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_BSSID_FIT_1_0(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 12, 2)
+#define GET_RX_DESC_EOSP(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 11, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_BSSID_FIT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 11, 5)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_HTC(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 10, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_AMPDU_END_PKT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 9, 1)
+#define GET_RX_DESC_ADDRESS_CAM_VLD(rxdesc) \
+ LE_BITS_TO_4BYTE(rxdesc + 0x0C, 8, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_BSSID_FIT_4_2(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 7, 3)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_EOSP_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 7, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_RX_RATE(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x0C, 0, 7)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
/*RXDESC_WORD4*/
-#define GET_RX_DESC_A1_FIT(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x10, 24, 5)
+#define GET_RX_DESC_A1_FIT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 24, 5)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_ADDRESS_CAM(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 24, 8)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_A1_FIT_A1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 24, 7)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8814B_SUPPORT)
-#define GET_RX_DESC_MACID_RPT_BUFF(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x10, 17, 7)
-#define GET_RX_DESC_RX_PRE_NDP_VLD(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x10, 16, 1)
-#define GET_RX_DESC_RX_SCRAMBLER(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x10, 9, 7)
-#define GET_RX_DESC_RX_EOF(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x10, 8, 1)
+#define GET_RX_DESC_MACID_VLD_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 23, 1)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
-#define GET_RX_DESC_PATTERN_IDX(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x10, 0, 8)
+#define GET_RX_DESC_MACID_RPT_BUFF(rxdesc) \
+ LE_BITS_TO_4BYTE(rxdesc + 0x10, 17, 7)
+#define GET_RX_DESC_RX_PRE_NDP_VLD(rxdesc) \
+ LE_BITS_TO_4BYTE(rxdesc + 0x10, 16, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_MACID_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 15, 8)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_RX_SCRAMBLER(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 9, 7)
+#define GET_RX_DESC_RX_EOF(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 8, 1)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_FC_POWER(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 7, 1)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_TXRPTMID_CTL_MASK(rxdesc) \
+ LE_BITS_TO_4BYTE(rxdesc + 0x10, 6, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_SWPS_RPT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 5, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define GET_RX_DESC_PATTERN_IDX(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 0, 8)
+
+#endif
+
+#if (HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
+
+#define GET_RX_DESC_PATTERN_IDX_V1(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 0, 5)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_PATTERN_IDX_V2(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x10, 0, 5)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
/*RXDESC_WORD5*/
-#define GET_RX_DESC_TSFL(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x14, 0, 32)
+#define GET_RX_DESC_TSFL(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x14, 0, 32)
#endif
+#if (HALMAC_8814B_SUPPORT)
+
+#define GET_RX_DESC_FREERUN_CNT(rxdesc) LE_BITS_TO_4BYTE(rxdesc + 0x14, 0, 32)
+
+#endif
#endif
diff --git a/hal/halmac/halmac_sdio_reg.h b/hal/halmac/halmac_sdio_reg.h
index 18dfbe5..71f3de6 100644
--- a/hal/halmac/halmac_sdio_reg.h
+++ b/hal/halmac/halmac_sdio_reg.h
@@ -1,3 +1,18 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
#ifndef __HALMAC_SDIO_REG_H__
#define __HALMAC_SDIO_REG_H__
@@ -5,10 +20,11 @@
#define HALMAC_SDIO_4BYTE_LEN_MASK 0x1FFF
#define HALMAC_SDIO_LOCAL_MSK 0x0FFF
-#define HALMAC_WLAN_IOREG_MSK 0xFFFF
+#define HALMAC_WLAN_MAC_REG_MSK 0xFFFF
+#define HALMAC_WLAN_IOREG_MSK 0xFFFF
/* Sdio Address for SDIO Local Reg, TRX FIFO, MAC Reg */
-typedef enum {
+enum halmac_sdio_cmd_addr {
HALMAC_SDIO_CMD_ADDR_SDIO_REG = 0,
HALMAC_SDIO_CMD_ADDR_MAC_REG = 8,
HALMAC_SDIO_CMD_ADDR_TXFF_HIGH = 4,
@@ -16,27 +32,24 @@ typedef enum {
HALMAC_SDIO_CMD_ADDR_TXFF_NORMAL = 5,
HALMAC_SDIO_CMD_ADDR_TXFF_EXTRA = 7,
HALMAC_SDIO_CMD_ADDR_RXFF = 7,
-} HALMAC_SDIO_CMD_ADDR;
-
-
-#if 1
-#define SDIO_LOCAL_DEVICE_ID 0 /* 0b[16], 000b[15:13] */
-#define WLAN_TX_HIQ_DEVICE_ID 4 /* 0b[16], 100b[15:13] */
-#define WLAN_TX_MIQ_DEVICE_ID 5 /* 0b[16], 101b[15:13] */
-#define WLAN_TX_LOQ_DEVICE_ID 6 /* 0b[16], 110b[15:13] */
-#define WLAN_TX_EPQ_DEVICE_ID 3 /* 0b[16], 110b[15:13] */
-#define WLAN_RX0FF_DEVICE_ID 7 /* 0b[16], 111b[15:13] */
-#define WLAN_IOREG_DEVICE_ID 8 /* 1b[16] */
+};
/* IO Bus domain address mapping */
-#define SDIO_LOCAL_OFFSET 0x10250000
-#define WLAN_IOREG_OFFSET 0x10260000
-#define FW_FIFO_OFFSET 0x10270000
-#define TX_HIQ_OFFSET 0x10310000
-#define TX_MIQ_OFFSET 0x10320000
-#define TX_LOQ_OFFSET 0x10330000
-#define TX_EXQ_OFFSET 0x10350000
-#define RX_RXOFF_OFFSET 0x10340000
+#define SDIO_LOCAL_OFFSET 0x10250000
+#define WLAN_IOREG_OFFSET 0x10260000
+#define FW_FIFO_OFFSET 0x10270000
+#define TX_HIQ_OFFSET 0x10310000
+#define TX_MIQ_OFFSET 0x10320000
+#define TX_LOQ_OFFSET 0x10330000
+#define TX_EXQ_OFFSET 0x10350000
+#define RX_RXOFF_OFFSET 0x10340000
+
+/* Get TX WLAN FIFO information in CMD53 addr */
+#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT)
+#define GET_WLAN_TXFF_DEVICE_ID(cmd53_addr) \
+ LE_BITS_TO_4BYTE((u32 *)cmd53_addr, 13, 4)
+#define GET_WLAN_TXFF_PKT_SIZE(cmd53_addr) \
+ (LE_BITS_TO_4BYTE((u32 *)cmd53_addr, 0, 13) << 2)
#endif
#endif/* __HALMAC_SDIO_REG_H__ */
diff --git a/hal/halmac/halmac_state_machine.h b/hal/halmac/halmac_state_machine.h
new file mode 100644
index 0000000..d6cce79
--- /dev/null
+++ b/hal/halmac/halmac_state_machine.h
@@ -0,0 +1,157 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2017 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_STATE_MACHINE_H_
+#define _HALMAC_STATE_MACHINE_H_
+
+enum halmac_dlfw_state {
+ HALMAC_DLFW_NONE = 0,
+ HALMAC_DLFW_DONE = 1,
+ HALMAC_GEN_INFO_SENT = 2,
+
+ /* Data CPU firmware download framework */
+ HALMAC_DLFW_INIT = 0x11,
+ HALMAC_DLFW_START = 0x12,
+ HALMAC_DLFW_CONF_READY = 0x13,
+ HALMAC_DLFW_CPU_READY = 0x14,
+ HALMAC_DLFW_MEM_READY = 0x15,
+ HALMAC_DLFW_SW_READY = 0x16,
+ HALMAC_DLFW_OFLD_READY = 0x17,
+
+ HALMAC_DLFW_UNDEFINED = 0x7F,
+};
+
+enum halmac_gpio_cfg_state {
+ HALMAC_GPIO_CFG_STATE_IDLE = 0,
+ HALMAC_GPIO_CFG_STATE_BUSY = 1,
+ HALMAC_GPIO_CFG_STATE_UNDEFINED = 0x7F,
+};
+
+enum halmac_rsvd_pg_state {
+ HALMAC_RSVD_PG_STATE_IDLE = 0,
+ HALMAC_RSVD_PG_STATE_BUSY = 1,
+ HALMAC_RSVD_PG_STATE_UNDEFINED = 0x7F,
+};
+
+enum halmac_api_state {
+ HALMAC_API_STATE_INIT = 0,
+ HALMAC_API_STATE_HALT = 1,
+ HALMAC_API_STATE_UNDEFINED = 0x7F,
+};
+
+enum halmac_cmd_construct_state {
+ HALMAC_CMD_CNSTR_IDLE = 0,
+ HALMAC_CMD_CNSTR_BUSY = 1,
+ HALMAC_CMD_CNSTR_H2C_SENT = 2,
+ HALMAC_CMD_CNSTR_CNSTR = 3,
+ HALMAC_CMD_CNSTR_BUF_CLR = 4,
+ HALMAC_CMD_CNSTR_UNDEFINED = 0x7F,
+};
+
+enum halmac_cmd_process_status {
+ HALMAC_CMD_PROCESS_IDLE = 0x01, /* Init status */
+ HALMAC_CMD_PROCESS_SENDING = 0x02, /* Wait ack */
+ HALMAC_CMD_PROCESS_RCVD = 0x03, /* Rcvd ack */
+ HALMAC_CMD_PROCESS_DONE = 0x04, /* Event done */
+ HALMAC_CMD_PROCESS_ERROR = 0x05, /* Return code error */
+ HALMAC_CMD_PROCESS_UNDEFINE = 0x7F,
+};
+
+enum halmac_mac_power {
+ HALMAC_MAC_POWER_OFF = 0x0,
+ HALMAC_MAC_POWER_ON = 0x1,
+ HALMAC_MAC_POWER_UNDEFINE = 0x7F,
+};
+
+enum halmac_wlcpu_mode {
+ HALMAC_WLCPU_ACTIVE = 0x0,
+ HALMAC_WLCPU_ENTER_SLEEP = 0x1,
+ HALMAC_WLCPU_SLEEP = 0x2,
+ HALMAC_WLCPU_UNDEFINE = 0x7F,
+};
+
+struct halmac_efuse_state {
+ enum halmac_cmd_construct_state cmd_cnstr_state;
+ enum halmac_cmd_process_status proc_status;
+ u8 fw_rc;
+ u16 seq_num;
+};
+
+struct halmac_cfg_param_state {
+ enum halmac_cmd_construct_state cmd_cnstr_state;
+ enum halmac_cmd_process_status proc_status;
+ u8 fw_rc;
+ u16 seq_num;
+};
+
+struct halmac_scan_state {
+ enum halmac_cmd_construct_state cmd_cnstr_state;
+ enum halmac_cmd_process_status proc_status;
+ u8 fw_rc;
+ u16 seq_num;
+};
+
+struct halmac_update_pkt_state {
+ enum halmac_cmd_process_status proc_status;
+ u8 fw_rc;
+ u16 seq_num;
+};
+
+struct halmac_iqk_state {
+ enum halmac_cmd_process_status proc_status;
+ u8 fw_rc;
+ u16 seq_num;
+};
+
+struct halmac_pwr_tracking_state {
+ enum halmac_cmd_process_status proc_status;
+ u8 fw_rc;
+ u16 seq_num;
+};
+
+struct halmac_psd_state {
+ enum halmac_cmd_process_status proc_status;
+ u16 data_size;
+ u16 seg_size;
+ u8 *data;
+ u8 fw_rc;
+ u16 seq_num;
+};
+
+struct halmac_fw_snding_state {
+ enum halmac_cmd_construct_state cmd_cnstr_state;
+ enum halmac_cmd_process_status proc_status;
+ u8 fw_rc;
+ u16 seq_num;
+};
+
+struct halmac_state {
+ struct halmac_efuse_state efuse_state;
+ struct halmac_cfg_param_state cfg_param_state;
+ struct halmac_scan_state scan_state;
+ struct halmac_update_pkt_state update_pkt_state;
+ struct halmac_iqk_state iqk_state;
+ struct halmac_pwr_tracking_state pwr_trk_state;
+ struct halmac_psd_state psd_state;
+ struct halmac_fw_snding_state fw_snding_state;
+ enum halmac_api_state api_state;
+ enum halmac_mac_power mac_pwr;
+ enum halmac_dlfw_state dlfw_state;
+ enum halmac_wlcpu_mode wlcpu_mode;
+ enum halmac_gpio_cfg_state gpio_cfg_state;
+ enum halmac_rsvd_pg_state rsvd_pg_state;
+};
+
+#endif
diff --git a/hal/halmac/halmac_tx_bd_ap.h b/hal/halmac/halmac_tx_bd_ap.h
deleted file mode 100644
index 1cff6b1..0000000
--- a/hal/halmac/halmac_tx_bd_ap.h
+++ /dev/null
@@ -1,95 +0,0 @@
-#ifndef _HALMAC_TX_BD_AP_H_
-#define _HALMAC_TX_BD_AP_H_
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
-
-/*TXBD_DW0*/
-
-#define SET_TX_BD_OWN(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword0, __Value, 0x1, 31)
-#define SET_TX_BD_OWN_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword0, __Value, 0x1, 31)
-#define GET_TX_BD_OWN(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword0, 0x1, 31)
-#define SET_TX_BD_PSB(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword0, __Value, 0xff, 16)
-#define SET_TX_BD_PSB_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword0, __Value, 0xff, 16)
-#define GET_TX_BD_PSB(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword0, 0xff, 16)
-#define SET_TX_BD_TX_BUFF_SIZE0(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword0, __Value, 0xffff, 0)
-#define SET_TX_BD_TX_BUFF_SIZE0_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword0, __Value, 0xffff, 0)
-#define GET_TX_BD_TX_BUFF_SIZE0(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword0, 0xffff, 0)
-
-/*TXBD_DW1*/
-
-#define SET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword1, __Value, 0xffffffff, 0)
-#define SET_TX_BD_PHYSICAL_ADDR0_LOW_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword1, __Value, 0xffffffff, 0)
-#define GET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword1, 0xffffffff, 0)
-
-/*TXBD_DW2*/
-
-#define SET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword2, __Value, 0xffffffff, 0)
-#define SET_TX_BD_PHYSICAL_ADDR0_HIGH_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword2, __Value, 0xffffffff, 0)
-#define GET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword2, 0xffffffff, 0)
-
-/*TXBD_DW4*/
-
-#define SET_TX_BD_A1(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword4, __Value, 0x1, 31)
-#define SET_TX_BD_A1_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword4, __Value, 0x1, 31)
-#define GET_TX_BD_A1(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword4, 0x1, 31)
-#define SET_TX_BD_TX_BUFF_SIZE1(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword4, __Value, 0xffff, 0)
-#define SET_TX_BD_TX_BUFF_SIZE1_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword4, __Value, 0xffff, 0)
-#define GET_TX_BD_TX_BUFF_SIZE1(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword4, 0xffff, 0)
-
-/*TXBD_DW5*/
-
-#define SET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword5, __Value, 0xffffffff, 0)
-#define SET_TX_BD_PHYSICAL_ADDR1_LOW_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword5, __Value, 0xffffffff, 0)
-#define GET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword5, 0xffffffff, 0)
-
-/*TXBD_DW6*/
-
-#define SET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword6, __Value, 0xffffffff, 0)
-#define SET_TX_BD_PHYSICAL_ADDR1_HIGH_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword6, __Value, 0xffffffff, 0)
-#define GET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword6, 0xffffffff, 0)
-
-/*TXBD_DW8*/
-
-#define SET_TX_BD_A2(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword8, __Value, 0x1, 31)
-#define SET_TX_BD_A2_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword8, __Value, 0x1, 31)
-#define GET_TX_BD_A2(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword8, 0x1, 31)
-#define SET_TX_BD_TX_BUFF_SIZE2(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword8, __Value, 0xffff, 0)
-#define SET_TX_BD_TX_BUFF_SIZE2_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword8, __Value, 0xffff, 0)
-#define GET_TX_BD_TX_BUFF_SIZE2(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword8, 0xffff, 0)
-
-/*TXBD_DW9*/
-
-#define SET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword9, __Value, 0xffffffff, 0)
-#define SET_TX_BD_PHYSICAL_ADDR2_LOW_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword9, __Value, 0xffffffff, 0)
-#define GET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword9, 0xffffffff, 0)
-
-/*TXBD_DW10*/
-
-#define SET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword10, __Value, 0xffffffff, 0)
-#define SET_TX_BD_PHYSICAL_ADDR2_HIGH_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword10, __Value, 0xffffffff, 0)
-#define GET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword10, 0xffffffff, 0)
-
-/*TXBD_DW12*/
-
-#define SET_TX_BD_A3(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword12, __Value, 0x1, 31)
-#define SET_TX_BD_A3_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword12, __Value, 0x1, 31)
-#define GET_TX_BD_A3(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword12, 0x1, 31)
-#define SET_TX_BD_TX_BUFF_SIZE3(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword12, __Value, 0xffff, 0)
-#define SET_TX_BD_TX_BUFF_SIZE3_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword12, __Value, 0xffff, 0)
-#define GET_TX_BD_TX_BUFF_SIZE3(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword12, 0xffff, 0)
-
-/*TXBD_DW13*/
-
-#define SET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword13, __Value, 0xffffffff, 0)
-#define SET_TX_BD_PHYSICAL_ADDR3_LOW_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword13, __Value, 0xffffffff, 0)
-#define GET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword13, 0xffffffff, 0)
-
-/*TXBD_DW14*/
-
-#define SET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword14, __Value, 0xffffffff, 0)
-#define SET_TX_BD_PHYSICAL_ADDR3_HIGH_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword14, __Value, 0xffffffff, 0)
-#define GET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword14, 0xffffffff, 0)
-
-#endif
-
-
-#endif
diff --git a/hal/halmac/halmac_tx_bd_chip.h b/hal/halmac/halmac_tx_bd_chip.h
deleted file mode 100644
index 17004bc..0000000
--- a/hal/halmac/halmac_tx_bd_chip.h
+++ /dev/null
@@ -1,374 +0,0 @@
-#ifndef _HALMAC_TX_BD_CHIP_H_
-#define _HALMAC_TX_BD_CHIP_H_
-#if (HALMAC_8814A_SUPPORT)
-
-/*TXBD_DW0*/
-
-#define SET_TX_BD_OWN_8814A(__pTxBd, __Value) SET_TX_BD_OWN(__pTxBd, __Value)
-#define GET_TX_BD_OWN_8814A(__pTxBd) GET_TX_BD_OWN(__pTxBd)
-#define SET_TX_BD_PSB_8814A(__pTxBd, __Value) SET_TX_BD_PSB(__pTxBd, __Value)
-#define GET_TX_BD_PSB_8814A(__pTxBd) GET_TX_BD_PSB(__pTxBd)
-#define SET_TX_BD_TX_BUFF_SIZE0_8814A(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE0(__pTxBd, __Value)
-#define GET_TX_BD_TX_BUFF_SIZE0_8814A(__pTxBd) GET_TX_BD_TX_BUFF_SIZE0(__pTxBd)
-
-/*TXBD_DW1*/
-
-#define SET_TX_BD_PHYSICAL_ADDR0_LOW_8814A(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR0_LOW_8814A(__pTxBd) GET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd)
-
-/*TXBD_DW2*/
-
-#define SET_TX_BD_PHYSICAL_ADDR0_HIGH_8814A(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR0_HIGH_8814A(__pTxBd) GET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd)
-
-/*TXBD_DW4*/
-
-#define SET_TX_BD_A1_8814A(__pTxBd, __Value) SET_TX_BD_A1(__pTxBd, __Value)
-#define GET_TX_BD_A1_8814A(__pTxBd) GET_TX_BD_A1(__pTxBd)
-#define SET_TX_BD_TX_BUFF_SIZE1_8814A(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE1(__pTxBd, __Value)
-#define GET_TX_BD_TX_BUFF_SIZE1_8814A(__pTxBd) GET_TX_BD_TX_BUFF_SIZE1(__pTxBd)
-
-/*TXBD_DW5*/
-
-#define SET_TX_BD_PHYSICAL_ADDR1_LOW_8814A(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR1_LOW_8814A(__pTxBd) GET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd)
-
-/*TXBD_DW6*/
-
-#define SET_TX_BD_PHYSICAL_ADDR1_HIGH_8814A(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR1_HIGH_8814A(__pTxBd) GET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd)
-
-/*TXBD_DW8*/
-
-#define SET_TX_BD_A2_8814A(__pTxBd, __Value) SET_TX_BD_A2(__pTxBd, __Value)
-#define GET_TX_BD_A2_8814A(__pTxBd) GET_TX_BD_A2(__pTxBd)
-#define SET_TX_BD_TX_BUFF_SIZE2_8814A(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE2(__pTxBd, __Value)
-#define GET_TX_BD_TX_BUFF_SIZE2_8814A(__pTxBd) GET_TX_BD_TX_BUFF_SIZE2(__pTxBd)
-
-/*TXBD_DW9*/
-
-#define SET_TX_BD_PHYSICAL_ADDR2_LOW_8814A(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR2_LOW_8814A(__pTxBd) GET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd)
-
-/*TXBD_DW10*/
-
-#define SET_TX_BD_PHYSICAL_ADDR2_HIGH_8814A(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR2_HIGH_8814A(__pTxBd) GET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd)
-
-/*TXBD_DW12*/
-
-#define SET_TX_BD_A3_8814A(__pTxBd, __Value) SET_TX_BD_A3(__pTxBd, __Value)
-#define GET_TX_BD_A3_8814A(__pTxBd) GET_TX_BD_A3(__pTxBd)
-#define SET_TX_BD_TX_BUFF_SIZE3_8814A(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE3(__pTxBd, __Value)
-#define GET_TX_BD_TX_BUFF_SIZE3_8814A(__pTxBd) GET_TX_BD_TX_BUFF_SIZE3(__pTxBd)
-
-/*TXBD_DW13*/
-
-#define SET_TX_BD_PHYSICAL_ADDR3_LOW_8814A(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR3_LOW_8814A(__pTxBd) GET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd)
-
-/*TXBD_DW14*/
-
-#define SET_TX_BD_PHYSICAL_ADDR3_HIGH_8814A(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR3_HIGH_8814A(__pTxBd) GET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd)
-
-#endif
-
-#if (HALMAC_8822B_SUPPORT)
-
-/*TXBD_DW0*/
-
-#define SET_TX_BD_OWN_8822B(__pTxBd, __Value) SET_TX_BD_OWN(__pTxBd, __Value)
-#define GET_TX_BD_OWN_8822B(__pTxBd) GET_TX_BD_OWN(__pTxBd)
-#define SET_TX_BD_PSB_8822B(__pTxBd, __Value) SET_TX_BD_PSB(__pTxBd, __Value)
-#define GET_TX_BD_PSB_8822B(__pTxBd) GET_TX_BD_PSB(__pTxBd)
-#define SET_TX_BD_TX_BUFF_SIZE0_8822B(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE0(__pTxBd, __Value)
-#define GET_TX_BD_TX_BUFF_SIZE0_8822B(__pTxBd) GET_TX_BD_TX_BUFF_SIZE0(__pTxBd)
-
-/*TXBD_DW1*/
-
-#define SET_TX_BD_PHYSICAL_ADDR0_LOW_8822B(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR0_LOW_8822B(__pTxBd) GET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd)
-
-/*TXBD_DW2*/
-
-#define SET_TX_BD_PHYSICAL_ADDR0_HIGH_8822B(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR0_HIGH_8822B(__pTxBd) GET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd)
-
-/*TXBD_DW4*/
-
-#define SET_TX_BD_A1_8822B(__pTxBd, __Value) SET_TX_BD_A1(__pTxBd, __Value)
-#define GET_TX_BD_A1_8822B(__pTxBd) GET_TX_BD_A1(__pTxBd)
-#define SET_TX_BD_TX_BUFF_SIZE1_8822B(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE1(__pTxBd, __Value)
-#define GET_TX_BD_TX_BUFF_SIZE1_8822B(__pTxBd) GET_TX_BD_TX_BUFF_SIZE1(__pTxBd)
-
-/*TXBD_DW5*/
-
-#define SET_TX_BD_PHYSICAL_ADDR1_LOW_8822B(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR1_LOW_8822B(__pTxBd) GET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd)
-
-/*TXBD_DW6*/
-
-#define SET_TX_BD_PHYSICAL_ADDR1_HIGH_8822B(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR1_HIGH_8822B(__pTxBd) GET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd)
-
-/*TXBD_DW8*/
-
-#define SET_TX_BD_A2_8822B(__pTxBd, __Value) SET_TX_BD_A2(__pTxBd, __Value)
-#define GET_TX_BD_A2_8822B(__pTxBd) GET_TX_BD_A2(__pTxBd)
-#define SET_TX_BD_TX_BUFF_SIZE2_8822B(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE2(__pTxBd, __Value)
-#define GET_TX_BD_TX_BUFF_SIZE2_8822B(__pTxBd) GET_TX_BD_TX_BUFF_SIZE2(__pTxBd)
-
-/*TXBD_DW9*/
-
-#define SET_TX_BD_PHYSICAL_ADDR2_LOW_8822B(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR2_LOW_8822B(__pTxBd) GET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd)
-
-/*TXBD_DW10*/
-
-#define SET_TX_BD_PHYSICAL_ADDR2_HIGH_8822B(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR2_HIGH_8822B(__pTxBd) GET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd)
-
-/*TXBD_DW12*/
-
-#define SET_TX_BD_A3_8822B(__pTxBd, __Value) SET_TX_BD_A3(__pTxBd, __Value)
-#define GET_TX_BD_A3_8822B(__pTxBd) GET_TX_BD_A3(__pTxBd)
-#define SET_TX_BD_TX_BUFF_SIZE3_8822B(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE3(__pTxBd, __Value)
-#define GET_TX_BD_TX_BUFF_SIZE3_8822B(__pTxBd) GET_TX_BD_TX_BUFF_SIZE3(__pTxBd)
-
-/*TXBD_DW13*/
-
-#define SET_TX_BD_PHYSICAL_ADDR3_LOW_8822B(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR3_LOW_8822B(__pTxBd) GET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd)
-
-/*TXBD_DW14*/
-
-#define SET_TX_BD_PHYSICAL_ADDR3_HIGH_8822B(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR3_HIGH_8822B(__pTxBd) GET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd)
-
-#endif
-
-#if (HALMAC_8197F_SUPPORT)
-
-/*TXBD_DW0*/
-
-#define SET_TX_BD_OWN_8197F(__pTxBd, __Value) SET_TX_BD_OWN(__pTxBd, __Value)
-#define GET_TX_BD_OWN_8197F(__pTxBd) GET_TX_BD_OWN(__pTxBd)
-#define SET_TX_BD_PSB_8197F(__pTxBd, __Value) SET_TX_BD_PSB(__pTxBd, __Value)
-#define GET_TX_BD_PSB_8197F(__pTxBd) GET_TX_BD_PSB(__pTxBd)
-#define SET_TX_BD_TX_BUFF_SIZE0_8197F(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE0(__pTxBd, __Value)
-#define GET_TX_BD_TX_BUFF_SIZE0_8197F(__pTxBd) GET_TX_BD_TX_BUFF_SIZE0(__pTxBd)
-
-/*TXBD_DW1*/
-
-#define SET_TX_BD_PHYSICAL_ADDR0_LOW_8197F(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR0_LOW_8197F(__pTxBd) GET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd)
-
-/*TXBD_DW2*/
-
-#define SET_TX_BD_PHYSICAL_ADDR0_HIGH_8197F(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR0_HIGH_8197F(__pTxBd) GET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd)
-
-/*TXBD_DW4*/
-
-#define SET_TX_BD_A1_8197F(__pTxBd, __Value) SET_TX_BD_A1(__pTxBd, __Value)
-#define GET_TX_BD_A1_8197F(__pTxBd) GET_TX_BD_A1(__pTxBd)
-#define SET_TX_BD_TX_BUFF_SIZE1_8197F(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE1(__pTxBd, __Value)
-#define GET_TX_BD_TX_BUFF_SIZE1_8197F(__pTxBd) GET_TX_BD_TX_BUFF_SIZE1(__pTxBd)
-
-/*TXBD_DW5*/
-
-#define SET_TX_BD_PHYSICAL_ADDR1_LOW_8197F(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR1_LOW_8197F(__pTxBd) GET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd)
-
-/*TXBD_DW6*/
-
-#define SET_TX_BD_PHYSICAL_ADDR1_HIGH_8197F(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR1_HIGH_8197F(__pTxBd) GET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd)
-
-/*TXBD_DW8*/
-
-#define SET_TX_BD_A2_8197F(__pTxBd, __Value) SET_TX_BD_A2(__pTxBd, __Value)
-#define GET_TX_BD_A2_8197F(__pTxBd) GET_TX_BD_A2(__pTxBd)
-#define SET_TX_BD_TX_BUFF_SIZE2_8197F(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE2(__pTxBd, __Value)
-#define GET_TX_BD_TX_BUFF_SIZE2_8197F(__pTxBd) GET_TX_BD_TX_BUFF_SIZE2(__pTxBd)
-
-/*TXBD_DW9*/
-
-#define SET_TX_BD_PHYSICAL_ADDR2_LOW_8197F(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR2_LOW_8197F(__pTxBd) GET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd)
-
-/*TXBD_DW10*/
-
-#define SET_TX_BD_PHYSICAL_ADDR2_HIGH_8197F(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR2_HIGH_8197F(__pTxBd) GET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd)
-
-/*TXBD_DW12*/
-
-#define SET_TX_BD_A3_8197F(__pTxBd, __Value) SET_TX_BD_A3(__pTxBd, __Value)
-#define GET_TX_BD_A3_8197F(__pTxBd) GET_TX_BD_A3(__pTxBd)
-#define SET_TX_BD_TX_BUFF_SIZE3_8197F(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE3(__pTxBd, __Value)
-#define GET_TX_BD_TX_BUFF_SIZE3_8197F(__pTxBd) GET_TX_BD_TX_BUFF_SIZE3(__pTxBd)
-
-/*TXBD_DW13*/
-
-#define SET_TX_BD_PHYSICAL_ADDR3_LOW_8197F(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR3_LOW_8197F(__pTxBd) GET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd)
-
-/*TXBD_DW14*/
-
-#define SET_TX_BD_PHYSICAL_ADDR3_HIGH_8197F(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR3_HIGH_8197F(__pTxBd) GET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd)
-
-#endif
-
-#if (HALMAC_8821C_SUPPORT)
-
-/*TXBD_DW0*/
-
-#define SET_TX_BD_OWN_8821C(__pTxBd, __Value) SET_TX_BD_OWN(__pTxBd, __Value)
-#define GET_TX_BD_OWN_8821C(__pTxBd) GET_TX_BD_OWN(__pTxBd)
-#define SET_TX_BD_PSB_8821C(__pTxBd, __Value) SET_TX_BD_PSB(__pTxBd, __Value)
-#define GET_TX_BD_PSB_8821C(__pTxBd) GET_TX_BD_PSB(__pTxBd)
-#define SET_TX_BD_TX_BUFF_SIZE0_8821C(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE0(__pTxBd, __Value)
-#define GET_TX_BD_TX_BUFF_SIZE0_8821C(__pTxBd) GET_TX_BD_TX_BUFF_SIZE0(__pTxBd)
-
-/*TXBD_DW1*/
-
-#define SET_TX_BD_PHYSICAL_ADDR0_LOW_8821C(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR0_LOW_8821C(__pTxBd) GET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd)
-
-/*TXBD_DW2*/
-
-#define SET_TX_BD_PHYSICAL_ADDR0_HIGH_8821C(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR0_HIGH_8821C(__pTxBd) GET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd)
-
-/*TXBD_DW4*/
-
-#define SET_TX_BD_A1_8821C(__pTxBd, __Value) SET_TX_BD_A1(__pTxBd, __Value)
-#define GET_TX_BD_A1_8821C(__pTxBd) GET_TX_BD_A1(__pTxBd)
-#define SET_TX_BD_TX_BUFF_SIZE1_8821C(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE1(__pTxBd, __Value)
-#define GET_TX_BD_TX_BUFF_SIZE1_8821C(__pTxBd) GET_TX_BD_TX_BUFF_SIZE1(__pTxBd)
-
-/*TXBD_DW5*/
-
-#define SET_TX_BD_PHYSICAL_ADDR1_LOW_8821C(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR1_LOW_8821C(__pTxBd) GET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd)
-
-/*TXBD_DW6*/
-
-#define SET_TX_BD_PHYSICAL_ADDR1_HIGH_8821C(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR1_HIGH_8821C(__pTxBd) GET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd)
-
-/*TXBD_DW8*/
-
-#define SET_TX_BD_A2_8821C(__pTxBd, __Value) SET_TX_BD_A2(__pTxBd, __Value)
-#define GET_TX_BD_A2_8821C(__pTxBd) GET_TX_BD_A2(__pTxBd)
-#define SET_TX_BD_TX_BUFF_SIZE2_8821C(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE2(__pTxBd, __Value)
-#define GET_TX_BD_TX_BUFF_SIZE2_8821C(__pTxBd) GET_TX_BD_TX_BUFF_SIZE2(__pTxBd)
-
-/*TXBD_DW9*/
-
-#define SET_TX_BD_PHYSICAL_ADDR2_LOW_8821C(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR2_LOW_8821C(__pTxBd) GET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd)
-
-/*TXBD_DW10*/
-
-#define SET_TX_BD_PHYSICAL_ADDR2_HIGH_8821C(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR2_HIGH_8821C(__pTxBd) GET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd)
-
-/*TXBD_DW12*/
-
-#define SET_TX_BD_A3_8821C(__pTxBd, __Value) SET_TX_BD_A3(__pTxBd, __Value)
-#define GET_TX_BD_A3_8821C(__pTxBd) GET_TX_BD_A3(__pTxBd)
-#define SET_TX_BD_TX_BUFF_SIZE3_8821C(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE3(__pTxBd, __Value)
-#define GET_TX_BD_TX_BUFF_SIZE3_8821C(__pTxBd) GET_TX_BD_TX_BUFF_SIZE3(__pTxBd)
-
-/*TXBD_DW13*/
-
-#define SET_TX_BD_PHYSICAL_ADDR3_LOW_8821C(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR3_LOW_8821C(__pTxBd) GET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd)
-
-/*TXBD_DW14*/
-
-#define SET_TX_BD_PHYSICAL_ADDR3_HIGH_8821C(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR3_HIGH_8821C(__pTxBd) GET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd)
-
-#endif
-
-#if (HALMAC_8188F_SUPPORT)
-
-/*TXBD_DW0*/
-
-#define SET_TX_BD_OWN_8188F(__pTxBd, __Value) SET_TX_BD_OWN(__pTxBd, __Value)
-#define GET_TX_BD_OWN_8188F(__pTxBd) GET_TX_BD_OWN(__pTxBd)
-#define SET_TX_BD_PSB_8188F(__pTxBd, __Value) SET_TX_BD_PSB(__pTxBd, __Value)
-#define GET_TX_BD_PSB_8188F(__pTxBd) GET_TX_BD_PSB(__pTxBd)
-#define SET_TX_BD_TX_BUFF_SIZE0_8188F(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE0(__pTxBd, __Value)
-#define GET_TX_BD_TX_BUFF_SIZE0_8188F(__pTxBd) GET_TX_BD_TX_BUFF_SIZE0(__pTxBd)
-
-/*TXBD_DW1*/
-
-#define SET_TX_BD_PHYSICAL_ADDR0_LOW_8188F(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR0_LOW_8188F(__pTxBd) GET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd)
-
-/*TXBD_DW2*/
-
-#define SET_TX_BD_PHYSICAL_ADDR0_HIGH_8188F(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR0_HIGH_8188F(__pTxBd) GET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd)
-
-/*TXBD_DW4*/
-
-#define SET_TX_BD_A1_8188F(__pTxBd, __Value) SET_TX_BD_A1(__pTxBd, __Value)
-#define GET_TX_BD_A1_8188F(__pTxBd) GET_TX_BD_A1(__pTxBd)
-#define SET_TX_BD_TX_BUFF_SIZE1_8188F(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE1(__pTxBd, __Value)
-#define GET_TX_BD_TX_BUFF_SIZE1_8188F(__pTxBd) GET_TX_BD_TX_BUFF_SIZE1(__pTxBd)
-
-/*TXBD_DW5*/
-
-#define SET_TX_BD_PHYSICAL_ADDR1_LOW_8188F(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR1_LOW_8188F(__pTxBd) GET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd)
-
-/*TXBD_DW6*/
-
-#define SET_TX_BD_PHYSICAL_ADDR1_HIGH_8188F(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR1_HIGH_8188F(__pTxBd) GET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd)
-
-/*TXBD_DW8*/
-
-#define SET_TX_BD_A2_8188F(__pTxBd, __Value) SET_TX_BD_A2(__pTxBd, __Value)
-#define GET_TX_BD_A2_8188F(__pTxBd) GET_TX_BD_A2(__pTxBd)
-#define SET_TX_BD_TX_BUFF_SIZE2_8188F(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE2(__pTxBd, __Value)
-#define GET_TX_BD_TX_BUFF_SIZE2_8188F(__pTxBd) GET_TX_BD_TX_BUFF_SIZE2(__pTxBd)
-
-/*TXBD_DW9*/
-
-#define SET_TX_BD_PHYSICAL_ADDR2_LOW_8188F(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR2_LOW_8188F(__pTxBd) GET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd)
-
-/*TXBD_DW10*/
-
-#define SET_TX_BD_PHYSICAL_ADDR2_HIGH_8188F(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR2_HIGH_8188F(__pTxBd) GET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd)
-
-/*TXBD_DW12*/
-
-#define SET_TX_BD_A3_8188F(__pTxBd, __Value) SET_TX_BD_A3(__pTxBd, __Value)
-#define GET_TX_BD_A3_8188F(__pTxBd) GET_TX_BD_A3(__pTxBd)
-#define SET_TX_BD_TX_BUFF_SIZE3_8188F(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE3(__pTxBd, __Value)
-#define GET_TX_BD_TX_BUFF_SIZE3_8188F(__pTxBd) GET_TX_BD_TX_BUFF_SIZE3(__pTxBd)
-
-/*TXBD_DW13*/
-
-#define SET_TX_BD_PHYSICAL_ADDR3_LOW_8188F(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR3_LOW_8188F(__pTxBd) GET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd)
-
-/*TXBD_DW14*/
-
-#define SET_TX_BD_PHYSICAL_ADDR3_HIGH_8188F(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR3_HIGH_8188F(__pTxBd) GET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd)
-
-#endif
-
-
-#endif
diff --git a/hal/halmac/halmac_tx_bd_nic.h b/hal/halmac/halmac_tx_bd_nic.h
index 1d53acc..5f312cf 100644
--- a/hal/halmac/halmac_tx_bd_nic.h
+++ b/hal/halmac/halmac_tx_bd_nic.h
@@ -1,78 +1,110 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
#ifndef _HALMAC_TX_BD_NIC_H_
#define _HALMAC_TX_BD_NIC_H_
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
/*TXBD_DW0*/
-#define SET_TX_BD_OWN(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x00, 31, 1, __Value)
-#define GET_TX_BD_OWN(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x00, 31, 1)
-#define SET_TX_BD_PSB(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x00, 16, 8, __Value)
-#define GET_TX_BD_PSB(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x00, 16, 8)
-#define SET_TX_BD_TX_BUFF_SIZE0(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x00, 0, 16, __Value)
-#define GET_TX_BD_TX_BUFF_SIZE0(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x00, 0, 16)
+#define SET_TX_BD_OWN(txbd, value) \
+ SET_BITS_TO_LE_4BYTE(txbd + 0x00, 31, 1, value)
+#define GET_TX_BD_OWN(txbd) LE_BITS_TO_4BYTE(txbd + 0x00, 31, 1)
+#define SET_TX_BD_PSB(txbd, value) \
+ SET_BITS_TO_LE_4BYTE(txbd + 0x00, 16, 8, value)
+#define GET_TX_BD_PSB(txbd) LE_BITS_TO_4BYTE(txbd + 0x00, 16, 8)
+#define SET_TX_BD_TX_BUFF_SIZE0(txbd, value) \
+ SET_BITS_TO_LE_4BYTE(txbd + 0x00, 0, 16, value)
+#define GET_TX_BD_TX_BUFF_SIZE0(txbd) LE_BITS_TO_4BYTE(txbd + 0x00, 0, 16)
/*TXBD_DW1*/
-#define SET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x04, 0, 32, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x04, 0, 32)
+#define SET_TX_BD_PHYSICAL_ADDR0_LOW(txbd, value) \
+ SET_BITS_TO_LE_4BYTE(txbd + 0x04, 0, 32, value)
+#define GET_TX_BD_PHYSICAL_ADDR0_LOW(txbd) LE_BITS_TO_4BYTE(txbd + 0x04, 0, 32)
/*TXBD_DW2*/
-#define SET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x08, 0, 32, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x08, 0, 32)
+#define SET_TX_BD_PHYSICAL_ADDR0_HIGH(txbd, value) \
+ SET_BITS_TO_LE_4BYTE(txbd + 0x08, 0, 32, value)
+#define GET_TX_BD_PHYSICAL_ADDR0_HIGH(txbd) LE_BITS_TO_4BYTE(txbd + 0x08, 0, 32)
/*TXBD_DW4*/
-#define SET_TX_BD_A1(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x10, 31, 1, __Value)
-#define GET_TX_BD_A1(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x10, 31, 1)
-#define SET_TX_BD_TX_BUFF_SIZE1(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x10, 0, 16, __Value)
-#define GET_TX_BD_TX_BUFF_SIZE1(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x10, 0, 16)
+#define SET_TX_BD_A1(txbd, value) \
+ SET_BITS_TO_LE_4BYTE(txbd + 0x10, 31, 1, value)
+#define GET_TX_BD_A1(txbd) LE_BITS_TO_4BYTE(txbd + 0x10, 31, 1)
+#define SET_TX_BD_TX_BUFF_SIZE1(txbd, value) \
+ SET_BITS_TO_LE_4BYTE(txbd + 0x10, 0, 16, value)
+#define GET_TX_BD_TX_BUFF_SIZE1(txbd) LE_BITS_TO_4BYTE(txbd + 0x10, 0, 16)
/*TXBD_DW5*/
-#define SET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x14, 0, 32, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x14, 0, 32)
+#define SET_TX_BD_PHYSICAL_ADDR1_LOW(txbd, value) \
+ SET_BITS_TO_LE_4BYTE(txbd + 0x14, 0, 32, value)
+#define GET_TX_BD_PHYSICAL_ADDR1_LOW(txbd) LE_BITS_TO_4BYTE(txbd + 0x14, 0, 32)
/*TXBD_DW6*/
-#define SET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x18, 0, 32, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x18, 0, 32)
+#define SET_TX_BD_PHYSICAL_ADDR1_HIGH(txbd, value) \
+ SET_BITS_TO_LE_4BYTE(txbd + 0x18, 0, 32, value)
+#define GET_TX_BD_PHYSICAL_ADDR1_HIGH(txbd) LE_BITS_TO_4BYTE(txbd + 0x18, 0, 32)
/*TXBD_DW8*/
-#define SET_TX_BD_A2(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x20, 31, 1, __Value)
-#define GET_TX_BD_A2(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x20, 31, 1)
-#define SET_TX_BD_TX_BUFF_SIZE2(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x20, 0, 16, __Value)
-#define GET_TX_BD_TX_BUFF_SIZE2(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x20, 0, 16)
+#define SET_TX_BD_A2(txbd, value) \
+ SET_BITS_TO_LE_4BYTE(txbd + 0x20, 31, 1, value)
+#define GET_TX_BD_A2(txbd) LE_BITS_TO_4BYTE(txbd + 0x20, 31, 1)
+#define SET_TX_BD_TX_BUFF_SIZE2(txbd, value) \
+ SET_BITS_TO_LE_4BYTE(txbd + 0x20, 0, 16, value)
+#define GET_TX_BD_TX_BUFF_SIZE2(txbd) LE_BITS_TO_4BYTE(txbd + 0x20, 0, 16)
/*TXBD_DW9*/
-#define SET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x24, 0, 32, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x24, 0, 32)
+#define SET_TX_BD_PHYSICAL_ADDR2_LOW(txbd, value) \
+ SET_BITS_TO_LE_4BYTE(txbd + 0x24, 0, 32, value)
+#define GET_TX_BD_PHYSICAL_ADDR2_LOW(txbd) LE_BITS_TO_4BYTE(txbd + 0x24, 0, 32)
/*TXBD_DW10*/
-#define SET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x28, 0, 32, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x28, 0, 32)
+#define SET_TX_BD_PHYSICAL_ADDR2_HIGH(txbd, value) \
+ SET_BITS_TO_LE_4BYTE(txbd + 0x28, 0, 32, value)
+#define GET_TX_BD_PHYSICAL_ADDR2_HIGH(txbd) LE_BITS_TO_4BYTE(txbd + 0x28, 0, 32)
/*TXBD_DW12*/
-#define SET_TX_BD_A3(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x30, 31, 1, __Value)
-#define GET_TX_BD_A3(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x30, 31, 1)
-#define SET_TX_BD_TX_BUFF_SIZE3(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x30, 0, 16, __Value)
-#define GET_TX_BD_TX_BUFF_SIZE3(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x30, 0, 16)
+#define SET_TX_BD_A3(txbd, value) \
+ SET_BITS_TO_LE_4BYTE(txbd + 0x30, 31, 1, value)
+#define GET_TX_BD_A3(txbd) LE_BITS_TO_4BYTE(txbd + 0x30, 31, 1)
+#define SET_TX_BD_TX_BUFF_SIZE3(txbd, value) \
+ SET_BITS_TO_LE_4BYTE(txbd + 0x30, 0, 16, value)
+#define GET_TX_BD_TX_BUFF_SIZE3(txbd) LE_BITS_TO_4BYTE(txbd + 0x30, 0, 16)
/*TXBD_DW13*/
-#define SET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x34, 0, 32, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x34, 0, 32)
+#define SET_TX_BD_PHYSICAL_ADDR3_LOW(txbd, value) \
+ SET_BITS_TO_LE_4BYTE(txbd + 0x34, 0, 32, value)
+#define GET_TX_BD_PHYSICAL_ADDR3_LOW(txbd) LE_BITS_TO_4BYTE(txbd + 0x34, 0, 32)
/*TXBD_DW14*/
-#define SET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x38, 0, 32, __Value)
-#define GET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x38, 0, 32)
+#define SET_TX_BD_PHYSICAL_ADDR3_HIGH(txbd, value) \
+ SET_BITS_TO_LE_4BYTE(txbd + 0x38, 0, 32, value)
+#define GET_TX_BD_PHYSICAL_ADDR3_HIGH(txbd) LE_BITS_TO_4BYTE(txbd + 0x38, 0, 32)
#endif
-
#endif
diff --git a/hal/halmac/halmac_tx_desc_ap.h b/hal/halmac/halmac_tx_desc_ap.h
index e9c1e59..c806492 100644
--- a/hal/halmac/halmac_tx_desc_ap.h
+++ b/hal/halmac/halmac_tx_desc_ap.h
@@ -1,566 +1,1838 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
#ifndef _HALMAC_TX_DESC_AP_H_
#define _HALMAC_TX_DESC_AP_H_
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
/*TXDESC_WORD0*/
-#define SET_TX_DESC_DISQSELSEQ(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 31)
-#define SET_TX_DESC_DISQSELSEQ_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 31)
-#define GET_TX_DESC_DISQSELSEQ(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0x1, 31)
+#define SET_TX_DESC_DISQSELSEQ(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \
+ value, 0x1, 31)
+#define SET_TX_DESC_DISQSELSEQ_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 31)
+#define GET_TX_DESC_DISQSELSEQ(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \
+ 31)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_IE_END_BODY(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \
+ value, 0x1, 31)
+#define SET_TX_DESC_IE_END_BODY_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 31)
+#define GET_TX_DESC_IE_END_BODY(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \
+ 31)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_GF(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \
+ value, 0x1, 30)
+#define SET_TX_DESC_GF_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 30)
+#define GET_TX_DESC_GF(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \
+ 30)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_AGG_EN_V1(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \
+ value, 0x1, 30)
+#define SET_TX_DESC_AGG_EN_V1_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 30)
+#define GET_TX_DESC_AGG_EN_V1(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \
+ 30)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_NO_ACM(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \
+ value, 0x1, 29)
+#define SET_TX_DESC_NO_ACM_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 29)
+#define GET_TX_DESC_NO_ACM(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \
+ 29)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_BK_V1(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \
+ value, 0x1, 29)
+#define SET_TX_DESC_BK_V1_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 29)
+#define GET_TX_DESC_BK_V1(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \
+ 29)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \
+ value, 0x1, 28)
+#define SET_TX_DESC_BCNPKT_TSF_CTRL_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 28)
+#define GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \
+ 28)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_AMSDU_PAD_EN(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \
+ value, 0x1, 27)
+#define SET_TX_DESC_AMSDU_PAD_EN_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 27)
+#define GET_TX_DESC_AMSDU_PAD_EN(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \
+ 27)
+#define SET_TX_DESC_LS(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \
+ value, 0x1, 26)
+#define SET_TX_DESC_LS_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 26)
+#define GET_TX_DESC_LS(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \
+ 26)
+#define SET_TX_DESC_HTC(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \
+ value, 0x1, 25)
+#define SET_TX_DESC_HTC_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 25)
+#define GET_TX_DESC_HTC(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \
+ 25)
+#define SET_TX_DESC_BMC(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \
+ value, 0x1, 24)
+#define SET_TX_DESC_BMC_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 24)
+#define GET_TX_DESC_BMC(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \
+ 24)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_PKT_OFFSET_V1(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \
+ value, 0x1f, 24)
+#define SET_TX_DESC_PKT_OFFSET_V1_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1f, 24)
+#define GET_TX_DESC_PKT_OFFSET_V1(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1f, \
+ 24)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_OFFSET(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \
+ value, 0xff, 16)
+#define SET_TX_DESC_OFFSET_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword0, value, 0xff, 16)
+#define GET_TX_DESC_OFFSET(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0xff, \
+ 16)
+#define SET_TX_DESC_TXPKTSIZE(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \
+ value, 0xffff, 0)
+#define SET_TX_DESC_TXPKTSIZE_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword0, value, 0xffff, 0)
+#define GET_TX_DESC_TXPKTSIZE(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, \
+ 0xffff, 0)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/*WORD1*/
+
+#define SET_TX_DESC_HW_AES_IV_V2(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
+ value, 0x1, 31)
+#define SET_TX_DESC_HW_AES_IV_V2_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 31)
+#define GET_TX_DESC_HW_AES_IV_V2(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \
+ 31)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8814B_SUPPORT)
-#define SET_TX_DESC_GF(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 30)
-#define SET_TX_DESC_GF_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 30)
-#define GET_TX_DESC_GF(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0x1, 30)
-#define SET_TX_DESC_NO_ACM(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 29)
-#define SET_TX_DESC_NO_ACM_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 29)
-#define GET_TX_DESC_NO_ACM(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0x1, 29)
+#define SET_TX_DESC_AMSDU(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
+ value, 0x1, 30)
+#define SET_TX_DESC_AMSDU_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 30)
+#define GET_TX_DESC_AMSDU(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \
+ 30)
#endif
-#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8198F_SUPPORT)
-#define SET_TX_DESC_BCNPKT_TSF_CTRL(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 28)
-#define SET_TX_DESC_BCNPKT_TSF_CTRL_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 28)
-#define GET_TX_DESC_BCNPKT_TSF_CTRL(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0x1, 28)
+#define SET_TX_DESC_FTM_EN_V1(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
+ value, 0x1, 30)
+#define SET_TX_DESC_FTM_EN_V1_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 30)
+#define GET_TX_DESC_FTM_EN_V1(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \
+ 30)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
-#define SET_TX_DESC_AMSDU_PAD_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 27)
-#define SET_TX_DESC_AMSDU_PAD_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 27)
-#define GET_TX_DESC_AMSDU_PAD_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0x1, 27)
+#define SET_TX_DESC_MOREDATA(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
+ value, 0x1, 29)
+#define SET_TX_DESC_MOREDATA_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 29)
+#define GET_TX_DESC_MOREDATA(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \
+ 29)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_HW_AES_IV_V1(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
+ value, 0x1, 29)
+#define SET_TX_DESC_HW_AES_IV_V1_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 29)
+#define GET_TX_DESC_HW_AES_IV_V1(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \
+ 29)
+#define SET_TX_DESC_MHR_CP(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
+ value, 0x1, 25)
+#define SET_TX_DESC_MHR_CP_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 25)
+#define GET_TX_DESC_MHR_CP(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \
+ 25)
-#define SET_TX_DESC_LS(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 26)
-#define SET_TX_DESC_LS_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 26)
-#define GET_TX_DESC_LS(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0x1, 26)
-#define SET_TX_DESC_HTC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 25)
-#define SET_TX_DESC_HTC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 25)
-#define GET_TX_DESC_HTC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0x1, 25)
-#define SET_TX_DESC_BMC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 24)
-#define SET_TX_DESC_BMC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 24)
-#define GET_TX_DESC_BMC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0x1, 24)
-#define SET_TX_DESC_OFFSET(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0xff, 16)
-#define SET_TX_DESC_OFFSET_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0xff, 16)
-#define GET_TX_DESC_OFFSET(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0xff, 16)
-#define SET_TX_DESC_TXPKTSIZE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0xffff, 0)
-#define SET_TX_DESC_TXPKTSIZE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0xffff, 0)
-#define GET_TX_DESC_TXPKTSIZE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0xffff, 0)
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_PKT_OFFSET(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
+ value, 0x1f, 24)
+#define SET_TX_DESC_PKT_OFFSET_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1f, 24)
+#define GET_TX_DESC_PKT_OFFSET(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1f, \
+ 24)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_SMH_EN_V1(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
+ value, 0x1, 24)
+#define SET_TX_DESC_SMH_EN_V1_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 24)
+#define GET_TX_DESC_SMH_EN_V1(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \
+ 24)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_SEC_TYPE(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
+ value, 0x3, 22)
+#define SET_TX_DESC_SEC_TYPE_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x3, 22)
+#define GET_TX_DESC_SEC_TYPE(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x3, \
+ 22)
+#define SET_TX_DESC_EN_DESC_ID(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
+ value, 0x1, 21)
+#define SET_TX_DESC_EN_DESC_ID_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 21)
+#define GET_TX_DESC_EN_DESC_ID(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \
+ 21)
+#define SET_TX_DESC_RATE_ID(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
+ value, 0x1f, 16)
+#define SET_TX_DESC_RATE_ID_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1f, 16)
+#define GET_TX_DESC_RATE_ID(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1f, \
+ 16)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_SMH_CAM(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
+ value, 0xff, 16)
+#define SET_TX_DESC_SMH_CAM_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword1, value, 0xff, 16)
+#define GET_TX_DESC_SMH_CAM(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0xff, \
+ 16)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_PIFS(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
+ value, 0x1, 15)
+#define SET_TX_DESC_PIFS_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 15)
+#define GET_TX_DESC_PIFS(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \
+ 15)
+#define SET_TX_DESC_LSIG_TXOP_EN(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
+ value, 0x1, 14)
+#define SET_TX_DESC_LSIG_TXOP_EN_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 14)
+#define GET_TX_DESC_LSIG_TXOP_EN(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \
+ 14)
+#define SET_TX_DESC_RD_NAV_EXT(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
+ value, 0x1, 13)
+#define SET_TX_DESC_RD_NAV_EXT_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 13)
+#define GET_TX_DESC_RD_NAV_EXT(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \
+ 13)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
-/*TXDESC_WORD1*/
+#define SET_TX_DESC_EXT_EDCA(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
+ value, 0x1, 13)
+#define SET_TX_DESC_EXT_EDCA_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 13)
+#define GET_TX_DESC_EXT_EDCA(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \
+ 13)
-#define SET_TX_DESC_MOREDATA(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 29)
-#define SET_TX_DESC_MOREDATA_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 29)
-#define GET_TX_DESC_MOREDATA(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x1, 29)
-#define SET_TX_DESC_PKT_OFFSET(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1f, 24)
-#define SET_TX_DESC_PKT_OFFSET_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1f, 24)
-#define GET_TX_DESC_PKT_OFFSET(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x1f, 24)
-#define SET_TX_DESC_SEC_TYPE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x3, 22)
-#define SET_TX_DESC_SEC_TYPE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x3, 22)
-#define GET_TX_DESC_SEC_TYPE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x3, 22)
-#define SET_TX_DESC_EN_DESC_ID(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 21)
-#define SET_TX_DESC_EN_DESC_ID_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 21)
-#define GET_TX_DESC_EN_DESC_ID(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x1, 21)
-#define SET_TX_DESC_RATE_ID(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1f, 16)
-#define SET_TX_DESC_RATE_ID_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1f, 16)
-#define GET_TX_DESC_RATE_ID(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x1f, 16)
-#define SET_TX_DESC_PIFS(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 15)
-#define SET_TX_DESC_PIFS_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 15)
-#define GET_TX_DESC_PIFS(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x1, 15)
-#define SET_TX_DESC_LSIG_TXOP_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 14)
-#define SET_TX_DESC_LSIG_TXOP_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 14)
-#define GET_TX_DESC_LSIG_TXOP_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x1, 14)
-#define SET_TX_DESC_RD_NAV_EXT(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 13)
-#define SET_TX_DESC_RD_NAV_EXT_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 13)
-#define GET_TX_DESC_RD_NAV_EXT(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x1, 13)
-#define SET_TX_DESC_QSEL(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1f, 8)
-#define SET_TX_DESC_QSEL_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1f, 8)
-#define GET_TX_DESC_QSEL(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x1f, 8)
-#define SET_TX_DESC_MACID(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x7f, 0)
-#define SET_TX_DESC_MACID_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x7f, 0)
-#define GET_TX_DESC_MACID(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x7f, 0)
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_QSEL(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
+ value, 0x1f, 8)
+#define SET_TX_DESC_QSEL_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1f, 8)
+#define GET_TX_DESC_QSEL(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1f, \
+ 8)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_SPECIAL_CW(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
+ value, 0x1, 7)
+#define SET_TX_DESC_SPECIAL_CW_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 7)
+#define GET_TX_DESC_SPECIAL_CW(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, 7)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_MACID(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
+ value, 0x7f, 0)
+#define SET_TX_DESC_MACID_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x7f, 0)
+#define GET_TX_DESC_MACID(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x7f, \
+ 0)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_MACID_V1(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
+ value, 0x7f, 0)
+#define SET_TX_DESC_MACID_V1_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x7f, 0)
+#define GET_TX_DESC_MACID_V1(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x7f, \
+ 0)
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
/*TXDESC_WORD2*/
-#define SET_TX_DESC_HW_AES_IV(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 31)
-#define SET_TX_DESC_HW_AES_IV_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 31)
-#define GET_TX_DESC_HW_AES_IV(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 31)
+#define SET_TX_DESC_HW_AES_IV(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
+ value, 0x1, 31)
+#define SET_TX_DESC_HW_AES_IV_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 31)
+#define GET_TX_DESC_HW_AES_IV(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \
+ 31)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_CHK_EN_V1(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
+ value, 0x1, 31)
+#define SET_TX_DESC_CHK_EN_V1_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 31)
+#define GET_TX_DESC_CHK_EN_V1(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \
+ 31)
#endif
-#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
-#define SET_TX_DESC_FTM_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 30)
-#define SET_TX_DESC_FTM_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 30)
-#define GET_TX_DESC_FTM_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 30)
+#define SET_TX_DESC_FTM_EN(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
+ value, 0x1, 30)
+#define SET_TX_DESC_FTM_EN_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 30)
+#define GET_TX_DESC_FTM_EN(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \
+ 30)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8198F_SUPPORT)
-#define SET_TX_DESC_G_ID(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x3f, 24)
-#define SET_TX_DESC_G_ID_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x3f, 24)
-#define GET_TX_DESC_G_ID(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x3f, 24)
-#define SET_TX_DESC_BT_NULL(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 23)
-#define SET_TX_DESC_BT_NULL_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 23)
-#define GET_TX_DESC_BT_NULL(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 23)
-#define SET_TX_DESC_AMPDU_DENSITY(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x7, 20)
-#define SET_TX_DESC_AMPDU_DENSITY_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x7, 20)
-#define GET_TX_DESC_AMPDU_DENSITY(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x7, 20)
-#define SET_TX_DESC_SPE_RPT(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 19)
-#define SET_TX_DESC_SPE_RPT_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 19)
-#define GET_TX_DESC_SPE_RPT(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 19)
-#define SET_TX_DESC_RAW(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 18)
-#define SET_TX_DESC_RAW_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 18)
-#define GET_TX_DESC_RAW(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 18)
-#define SET_TX_DESC_MOREFRAG(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 17)
-#define SET_TX_DESC_MOREFRAG_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 17)
-#define GET_TX_DESC_MOREFRAG(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 17)
-#define SET_TX_DESC_BK(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 16)
-#define SET_TX_DESC_BK_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 16)
-#define GET_TX_DESC_BK(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 16)
-#define SET_TX_DESC_NULL_1(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 15)
-#define SET_TX_DESC_NULL_1_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 15)
-#define GET_TX_DESC_NULL_1(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 15)
-#define SET_TX_DESC_NULL_0(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 14)
-#define SET_TX_DESC_NULL_0_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 14)
-#define GET_TX_DESC_NULL_0(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 14)
-#define SET_TX_DESC_RDG_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 13)
-#define SET_TX_DESC_RDG_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 13)
-#define GET_TX_DESC_RDG_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 13)
-#define SET_TX_DESC_AGG_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 12)
-#define SET_TX_DESC_AGG_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 12)
-#define GET_TX_DESC_AGG_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 12)
-#define SET_TX_DESC_CCA_RTS(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x3, 10)
-#define SET_TX_DESC_CCA_RTS_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x3, 10)
-#define GET_TX_DESC_CCA_RTS(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x3, 10)
+#define SET_TX_DESC_ANTCEL_D_V1(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
+ value, 0xf, 28)
+#define SET_TX_DESC_ANTCEL_D_V1_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword2, value, 0xf, 28)
+#define GET_TX_DESC_ANTCEL_D_V1(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0xf, \
+ 28)
#endif
-#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8814B_SUPPORT)
-#define SET_TX_DESC_TRI_FRAME(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 9)
-#define SET_TX_DESC_TRI_FRAME_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 9)
-#define GET_TX_DESC_TRI_FRAME(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 9)
+#define SET_TX_DESC_DMA_PRI(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
+ value, 0x1, 27)
+#define SET_TX_DESC_DMA_PRI_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 27)
+#define GET_TX_DESC_DMA_PRI(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \
+ 27)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define SET_TX_DESC_P_AID(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1ff, 0)
-#define SET_TX_DESC_P_AID_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1ff, 0)
-#define GET_TX_DESC_P_AID(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1ff, 0)
+#define SET_TX_DESC_G_ID(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
+ value, 0x3f, 24)
+#define SET_TX_DESC_G_ID_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x3f, 24)
+#define GET_TX_DESC_G_ID(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x3f, \
+ 24)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_MAX_AMSDU_MODE(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
+ value, 0x7, 24)
+#define SET_TX_DESC_MAX_AMSDU_MODE_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x7, 24)
+#define GET_TX_DESC_MAX_AMSDU_MODE(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x7, \
+ 24)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_ANTSEL_C_V1(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
+ value, 0xf, 24)
+#define SET_TX_DESC_ANTSEL_C_V1_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword2, value, 0xf, 24)
+#define GET_TX_DESC_ANTSEL_C_V1(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0xf, \
+ 24)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_BT_NULL(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
+ value, 0x1, 23)
+#define SET_TX_DESC_BT_NULL_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 23)
+#define GET_TX_DESC_BT_NULL(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \
+ 23)
+#define SET_TX_DESC_AMPDU_DENSITY(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
+ value, 0x7, 20)
+#define SET_TX_DESC_AMPDU_DENSITY_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x7, 20)
+#define GET_TX_DESC_AMPDU_DENSITY(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x7, \
+ 20)
+#define SET_TX_DESC_SPE_RPT(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
+ value, 0x1, 19)
+#define SET_TX_DESC_SPE_RPT_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 19)
+#define GET_TX_DESC_SPE_RPT(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \
+ 19)
+#define SET_TX_DESC_RAW(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
+ value, 0x1, 18)
+#define SET_TX_DESC_RAW_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 18)
+#define GET_TX_DESC_RAW(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \
+ 18)
+#define SET_TX_DESC_MOREFRAG(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
+ value, 0x1, 17)
+#define SET_TX_DESC_MOREFRAG_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 17)
+#define GET_TX_DESC_MOREFRAG(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \
+ 17)
+#define SET_TX_DESC_BK(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
+ value, 0x1, 16)
+#define SET_TX_DESC_BK_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 16)
+#define GET_TX_DESC_BK(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \
+ 16)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_DMA_TXAGG_NUM_V1(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
+ value, 0xff, 16)
+#define SET_TX_DESC_DMA_TXAGG_NUM_V1_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword2, value, 0xff, 16)
+#define GET_TX_DESC_DMA_TXAGG_NUM_V1(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0xff, \
+ 16)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_NULL_1(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
+ value, 0x1, 15)
+#define SET_TX_DESC_NULL_1_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 15)
+#define GET_TX_DESC_NULL_1(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \
+ 15)
+#define SET_TX_DESC_NULL_0(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
+ value, 0x1, 14)
+#define SET_TX_DESC_NULL_0_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 14)
+#define GET_TX_DESC_NULL_0(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \
+ 14)
+#define SET_TX_DESC_RDG_EN(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
+ value, 0x1, 13)
+#define SET_TX_DESC_RDG_EN_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 13)
+#define GET_TX_DESC_RDG_EN(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \
+ 13)
+#define SET_TX_DESC_AGG_EN(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
+ value, 0x1, 12)
+#define SET_TX_DESC_AGG_EN_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 12)
+#define GET_TX_DESC_AGG_EN(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \
+ 12)
+#define SET_TX_DESC_CCA_RTS(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
+ value, 0x3, 10)
+#define SET_TX_DESC_CCA_RTS_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x3, 10)
+#define GET_TX_DESC_CCA_RTS(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x3, \
+ 10)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_TRI_FRAME(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
+ value, 0x1, 9)
+#define SET_TX_DESC_TRI_FRAME_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 9)
+#define GET_TX_DESC_TRI_FRAME(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, 9)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_P_AID(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
+ value, 0x1ff, 0)
+#define SET_TX_DESC_P_AID_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1ff, 0)
+#define GET_TX_DESC_P_AID(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, \
+ 0x1ff, 0)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_TXDESC_CHECKSUM_V1(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
+ value, 0xffff, 0)
+#define SET_TX_DESC_TXDESC_CHECKSUM_V1_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword2, value, 0xffff, 0)
+#define GET_TX_DESC_TXDESC_CHECKSUM_V1(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, \
+ 0xffff, 0)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
/*TXDESC_WORD3*/
-#define SET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0xff, 24)
-#define SET_TX_DESC_AMPDU_MAX_TIME_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0xff, 24)
-#define GET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0xff, 24)
-#define SET_TX_DESC_NDPA(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x3, 22)
-#define SET_TX_DESC_NDPA_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x3, 22)
-#define GET_TX_DESC_NDPA(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x3, 22)
-#define SET_TX_DESC_MAX_AGG_NUM(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1f, 17)
-#define SET_TX_DESC_MAX_AGG_NUM_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1f, 17)
-#define GET_TX_DESC_MAX_AGG_NUM(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1f, 17)
-#define SET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 16)
-#define SET_TX_DESC_USE_MAX_TIME_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 16)
-#define GET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1, 16)
-#define SET_TX_DESC_NAVUSEHDR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 15)
-#define SET_TX_DESC_NAVUSEHDR_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 15)
-#define GET_TX_DESC_NAVUSEHDR(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1, 15)
+#define SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \
+ value, 0xff, 24)
+#define SET_TX_DESC_AMPDU_MAX_TIME_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword3, value, 0xff, 24)
+#define GET_TX_DESC_AMPDU_MAX_TIME(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0xff, \
+ 24)
+#define SET_TX_DESC_NDPA(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \
+ value, 0x3, 22)
+#define SET_TX_DESC_NDPA_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x3, 22)
+#define GET_TX_DESC_NDPA(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x3, \
+ 22)
+#define SET_TX_DESC_MAX_AGG_NUM(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \
+ value, 0x1f, 17)
+#define SET_TX_DESC_MAX_AGG_NUM_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1f, 17)
+#define GET_TX_DESC_MAX_AGG_NUM(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1f, \
+ 17)
+#define SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \
+ value, 0x1, 16)
+#define SET_TX_DESC_USE_MAX_TIME_EN_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 16)
+#define GET_TX_DESC_USE_MAX_TIME_EN(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, \
+ 16)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8814B_SUPPORT)
-#define SET_TX_DESC_CHK_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 14)
-#define SET_TX_DESC_CHK_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 14)
-#define GET_TX_DESC_CHK_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1, 14)
+#define SET_TX_DESC_OFFLOAD_SIZE(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \
+ value, 0x7fff, 16)
+#define SET_TX_DESC_OFFLOAD_SIZE_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x7fff, 16)
+#define GET_TX_DESC_OFFLOAD_SIZE(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, \
+ 0x7fff, 16)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_NAVUSEHDR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \
+ value, 0x1, 15)
+#define SET_TX_DESC_NAVUSEHDR_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 15)
+#define GET_TX_DESC_NAVUSEHDR(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, \
+ 15)
+#define SET_TX_DESC_CHK_EN(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \
+ value, 0x1, 14)
+#define SET_TX_DESC_CHK_EN_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 14)
+#define GET_TX_DESC_CHK_EN(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, \
+ 14)
+#define SET_TX_DESC_HW_RTS_EN(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \
+ value, 0x1, 13)
+#define SET_TX_DESC_HW_RTS_EN_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 13)
+#define GET_TX_DESC_HW_RTS_EN(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, \
+ 13)
+#define SET_TX_DESC_RTSEN(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \
+ value, 0x1, 12)
+#define SET_TX_DESC_RTSEN_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 12)
+#define GET_TX_DESC_RTSEN(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, \
+ 12)
+#define SET_TX_DESC_CTS2SELF(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \
+ value, 0x1, 11)
+#define SET_TX_DESC_CTS2SELF_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 11)
+#define GET_TX_DESC_CTS2SELF(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, \
+ 11)
+
+#endif
-#define SET_TX_DESC_HW_RTS_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 13)
-#define SET_TX_DESC_HW_RTS_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 13)
-#define GET_TX_DESC_HW_RTS_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1, 13)
-#define SET_TX_DESC_RTSEN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 12)
-#define SET_TX_DESC_RTSEN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 12)
-#define GET_TX_DESC_RTSEN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1, 12)
-#define SET_TX_DESC_CTS2SELF(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 11)
-#define SET_TX_DESC_CTS2SELF_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 11)
-#define GET_TX_DESC_CTS2SELF(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1, 11)
-#define SET_TX_DESC_DISDATAFB(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 10)
-#define SET_TX_DESC_DISDATAFB_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 10)
-#define GET_TX_DESC_DISDATAFB(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1, 10)
-#define SET_TX_DESC_DISRTSFB(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 9)
-#define SET_TX_DESC_DISRTSFB_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 9)
-#define GET_TX_DESC_DISRTSFB(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1, 9)
-#define SET_TX_DESC_USE_RATE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 8)
-#define SET_TX_DESC_USE_RATE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 8)
-#define GET_TX_DESC_USE_RATE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1, 8)
-#define SET_TX_DESC_HW_SSN_SEL(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x3, 6)
-#define SET_TX_DESC_HW_SSN_SEL_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x3, 6)
-#define GET_TX_DESC_HW_SSN_SEL(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x3, 6)
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_CHANNEL_DMA(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \
+ value, 0x1f, 11)
+#define SET_TX_DESC_CHANNEL_DMA_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1f, 11)
+#define GET_TX_DESC_CHANNEL_DMA(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1f, \
+ 11)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_DISDATAFB(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \
+ value, 0x1, 10)
+#define SET_TX_DESC_DISDATAFB_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 10)
+#define GET_TX_DESC_DISDATAFB(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, \
+ 10)
+#define SET_TX_DESC_DISRTSFB(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \
+ value, 0x1, 9)
+#define SET_TX_DESC_DISRTSFB_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 9)
+#define GET_TX_DESC_DISRTSFB(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, 9)
+#define SET_TX_DESC_USE_RATE(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \
+ value, 0x1, 8)
+#define SET_TX_DESC_USE_RATE_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 8)
+#define GET_TX_DESC_USE_RATE(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, 8)
+#define SET_TX_DESC_HW_SSN_SEL(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \
+ value, 0x3, 6)
+#define SET_TX_DESC_HW_SSN_SEL_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x3, 6)
+#define GET_TX_DESC_HW_SSN_SEL(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x3, 6)
+
+#endif
-#define SET_TX_DESC_WHEADER_LEN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1f, 0)
-#define SET_TX_DESC_WHEADER_LEN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1f, 0)
-#define GET_TX_DESC_WHEADER_LEN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1f, 0)
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_IE_CNT(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \
+ value, 0x7, 6)
+#define SET_TX_DESC_IE_CNT_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x7, 6)
+#define GET_TX_DESC_IE_CNT(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x7, 6)
+#define SET_TX_DESC_IE_CNT_EN(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \
+ value, 0x1, 5)
+#define SET_TX_DESC_IE_CNT_EN_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 5)
+#define GET_TX_DESC_IE_CNT_EN(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, 5)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+#define SET_TX_DESC_WHEADER_LEN(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \
+ value, 0x1f, 0)
+#define SET_TX_DESC_WHEADER_LEN_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1f, 0)
+#define GET_TX_DESC_WHEADER_LEN(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1f, \
+ 0)
-/*TXDESC_WORD4*/
+#endif
-#define SET_TX_DESC_PCTS_MASK_IDX(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x3, 30)
-#define SET_TX_DESC_PCTS_MASK_IDX_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x3, 30)
-#define GET_TX_DESC_PCTS_MASK_IDX(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, 0x3, 30)
-#define SET_TX_DESC_PCTS_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1, 29)
-#define SET_TX_DESC_PCTS_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1, 29)
-#define GET_TX_DESC_PCTS_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, 0x1, 29)
-#define SET_TX_DESC_RTSRATE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1f, 24)
-#define SET_TX_DESC_RTSRATE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1f, 24)
-#define GET_TX_DESC_RTSRATE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, 0x1f, 24)
-#define SET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x3f, 18)
-#define SET_TX_DESC_RTS_DATA_RTY_LMT_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x3f, 18)
-#define GET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, 0x3f, 18)
-#define SET_TX_DESC_RTY_LMT_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1, 17)
-#define SET_TX_DESC_RTY_LMT_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1, 17)
-#define GET_TX_DESC_RTY_LMT_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, 0x1, 17)
-#define SET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0xf, 13)
-#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0xf, 13)
-#define GET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, 0xf, 13)
-#define SET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1f, 8)
-#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1f, 8)
-#define GET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, 0x1f, 8)
-#define SET_TX_DESC_TRY_RATE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1, 7)
-#define SET_TX_DESC_TRY_RATE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1, 7)
-#define GET_TX_DESC_TRY_RATE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, 0x1, 7)
-#define SET_TX_DESC_DATARATE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x7f, 0)
-#define SET_TX_DESC_DATARATE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x7f, 0)
-#define GET_TX_DESC_DATARATE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, 0x7f, 0)
-
-#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8814B_SUPPORT)
+#define SET_TX_DESC_WHEADER_LEN_V1(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \
+ value, 0x1f, 0)
+#define SET_TX_DESC_WHEADER_LEN_V1_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1f, 0)
+#define GET_TX_DESC_WHEADER_LEN_V1(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1f, \
+ 0)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/*TXDESC_WORD4*/
+
+#define SET_TX_DESC_PCTS_MASK_IDX(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \
+ value, 0x3, 30)
+#define SET_TX_DESC_PCTS_MASK_IDX_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x3, 30)
+#define GET_TX_DESC_PCTS_MASK_IDX(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x3, \
+ 30)
+#define SET_TX_DESC_PCTS_EN(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \
+ value, 0x1, 29)
+#define SET_TX_DESC_PCTS_EN_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1, 29)
+#define GET_TX_DESC_PCTS_EN(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1, \
+ 29)
+#define SET_TX_DESC_RTSRATE(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \
+ value, 0x1f, 24)
+#define SET_TX_DESC_RTSRATE_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1f, 24)
+#define GET_TX_DESC_RTSRATE(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1f, \
+ 24)
+#define SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \
+ value, 0x3f, 18)
+#define SET_TX_DESC_RTS_DATA_RTY_LMT_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x3f, 18)
+#define GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x3f, \
+ 18)
+#define SET_TX_DESC_RTY_LMT_EN(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \
+ value, 0x1, 17)
+#define SET_TX_DESC_RTY_LMT_EN_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1, 17)
+#define GET_TX_DESC_RTY_LMT_EN(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1, \
+ 17)
+#define SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \
+ value, 0xf, 13)
+#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword4, value, 0xf, 13)
+#define GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0xf, \
+ 13)
+#define SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \
+ value, 0x1f, 8)
+#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1f, 8)
+#define GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1f, \
+ 8)
+#define SET_TX_DESC_TRY_RATE(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \
+ value, 0x1, 7)
+#define SET_TX_DESC_TRY_RATE_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1, 7)
+#define GET_TX_DESC_TRY_RATE(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1, 7)
+#define SET_TX_DESC_DATARATE(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \
+ value, 0x7f, 0)
+#define SET_TX_DESC_DATARATE_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x7f, 0)
+#define GET_TX_DESC_DATARATE(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x7f, \
+ 0)
/*TXDESC_WORD5*/
-#define SET_TX_DESC_POLLUTED(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 31)
-#define SET_TX_DESC_POLLUTED_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 31)
-#define GET_TX_DESC_POLLUTED(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x1, 31)
+#define SET_TX_DESC_POLLUTED(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
+ value, 0x1, 31)
+#define SET_TX_DESC_POLLUTED_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 31)
+#define GET_TX_DESC_POLLUTED(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, \
+ 31)
+
+#endif
+
+#if (HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_ANTSEL_EN_V1(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
+ value, 0x1, 30)
+#define SET_TX_DESC_ANTSEL_EN_V1_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 30)
+#define GET_TX_DESC_ANTSEL_EN_V1(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, \
+ 30)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT)
-#define SET_TX_DESC_TXPWR_OFSET(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x7, 28)
-#define SET_TX_DESC_TXPWR_OFSET_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x7, 28)
-#define GET_TX_DESC_TXPWR_OFSET(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x7, 28)
-#define SET_TX_DESC_TX_ANT(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0xf, 24)
-#define SET_TX_DESC_TX_ANT_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0xf, 24)
-#define GET_TX_DESC_TX_ANT(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0xf, 24)
-#define SET_TX_DESC_PORT_ID(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x7, 21)
-#define SET_TX_DESC_PORT_ID_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x7, 21)
-#define GET_TX_DESC_PORT_ID(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x7, 21)
+#define SET_TX_DESC_TXPWR_OFSET(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
+ value, 0x7, 28)
+#define SET_TX_DESC_TXPWR_OFSET_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x7, 28)
+#define GET_TX_DESC_TXPWR_OFSET(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x7, \
+ 28)
#endif
-#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8822C_SUPPORT)
-#define SET_TX_DESC_MULTIPLE_PORT(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x7, 18)
-#define SET_TX_DESC_MULTIPLE_PORT_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x7, 18)
-#define GET_TX_DESC_MULTIPLE_PORT(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x7, 18)
+#define SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
+ value, 0x3, 28)
+#define SET_TX_DESC_TXPWR_OFSET_TYPE_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x3, 28)
+#define GET_TX_DESC_TXPWR_OFSET_TYPE(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x3, \
+ 28)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define SET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 17)
-#define SET_TX_DESC_SIGNALING_TAPKT_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 17)
-#define GET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x1, 17)
+#define SET_TX_DESC_TX_ANT(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
+ value, 0xf, 24)
+#define SET_TX_DESC_TX_ANT_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword5, value, 0xf, 24)
+#define GET_TX_DESC_TX_ANT(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0xf, \
+ 24)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8198F_SUPPORT)
-#define SET_TX_DESC_RTS_SC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0xf, 13)
-#define SET_TX_DESC_RTS_SC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0xf, 13)
-#define GET_TX_DESC_RTS_SC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0xf, 13)
-#define SET_TX_DESC_RTS_SHORT(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 12)
-#define SET_TX_DESC_RTS_SHORT_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 12)
-#define GET_TX_DESC_RTS_SHORT(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x1, 12)
+#define SET_TX_DESC_DROP_ID(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
+ value, 0x3, 24)
+#define SET_TX_DESC_DROP_ID_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x3, 24)
+#define GET_TX_DESC_DROP_ID(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x3, \
+ 24)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
-#define SET_TX_DESC_VCS_STBC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x3, 10)
-#define SET_TX_DESC_VCS_STBC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x3, 10)
-#define GET_TX_DESC_VCS_STBC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x3, 10)
+#define SET_TX_DESC_PORT_ID(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
+ value, 0x7, 21)
+#define SET_TX_DESC_PORT_ID_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x7, 21)
+#define GET_TX_DESC_PORT_ID(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x7, \
+ 21)
#endif
-#if (HALMAC_8188F_SUPPORT)
+#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
-#define SET_TX_DESC_RTS_STBC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x3, 10)
-#define SET_TX_DESC_RTS_STBC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x3, 10)
-#define GET_TX_DESC_RTS_STBC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x3, 10)
+#define SET_TX_DESC_MULTIPLE_PORT(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
+ value, 0x7, 18)
+#define SET_TX_DESC_MULTIPLE_PORT_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x7, 18)
+#define GET_TX_DESC_MULTIPLE_PORT(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x7, \
+ 18)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
-#define SET_TX_DESC_DATA_STBC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x3, 8)
-#define SET_TX_DESC_DATA_STBC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x3, 8)
-#define GET_TX_DESC_DATA_STBC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x3, 8)
+#define SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
+ value, 0x1, 17)
+#define SET_TX_DESC_SIGNALING_TAPKT_EN_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 17)
+#define GET_TX_DESC_SIGNALING_TAPKT_EN(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, \
+ 17)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#define SET_TX_DESC_DATA_LDPC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 7)
-#define SET_TX_DESC_DATA_LDPC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 7)
-#define GET_TX_DESC_DATA_LDPC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x1, 7)
+#define SET_TX_DESC_RTS_SC(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
+ value, 0xf, 13)
+#define SET_TX_DESC_RTS_SC_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword5, value, 0xf, 13)
+#define GET_TX_DESC_RTS_SC(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0xf, \
+ 13)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define SET_TX_DESC_DATA_BW(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x3, 5)
-#define SET_TX_DESC_DATA_BW_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x3, 5)
-#define GET_TX_DESC_DATA_BW(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x3, 5)
-#define SET_TX_DESC_DATA_SHORT(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 4)
-#define SET_TX_DESC_DATA_SHORT_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 4)
-#define GET_TX_DESC_DATA_SHORT(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x1, 4)
-#define SET_TX_DESC_DATA_SC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0xf, 0)
-#define SET_TX_DESC_DATA_SC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0xf, 0)
-#define GET_TX_DESC_DATA_SC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0xf, 0)
+#define SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
+ value, 0xf, 13)
+#define SET_TX_DESC_SIGNALING_TA_PKT_SC_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword5, value, 0xf, 13)
+#define GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0xf, \
+ 13)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_RTS_SHORT(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
+ value, 0x1, 12)
+#define SET_TX_DESC_RTS_SHORT_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 12)
+#define GET_TX_DESC_RTS_SHORT(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, \
+ 12)
+#define SET_TX_DESC_VCS_STBC(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
+ value, 0x3, 10)
+#define SET_TX_DESC_VCS_STBC_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x3, 10)
+#define GET_TX_DESC_VCS_STBC(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x3, \
+ 10)
+#define SET_TX_DESC_DATA_STBC(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
+ value, 0x3, 8)
+#define SET_TX_DESC_DATA_STBC_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x3, 8)
+#define GET_TX_DESC_DATA_STBC(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x3, 8)
+#define SET_TX_DESC_DATA_LDPC(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
+ value, 0x1, 7)
+#define SET_TX_DESC_DATA_LDPC_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 7)
+#define GET_TX_DESC_DATA_LDPC(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, 7)
+#define SET_TX_DESC_DATA_BW(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
+ value, 0x3, 5)
+#define SET_TX_DESC_DATA_BW_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x3, 5)
+#define GET_TX_DESC_DATA_BW(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x3, 5)
+#define SET_TX_DESC_DATA_SHORT(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
+ value, 0x1, 4)
+#define SET_TX_DESC_DATA_SHORT_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 4)
+#define GET_TX_DESC_DATA_SHORT(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, 4)
+#define SET_TX_DESC_DATA_SC(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
+ value, 0xf, 0)
+#define SET_TX_DESC_DATA_SC_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword5, value, 0xf, 0)
+#define GET_TX_DESC_DATA_SC(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0xf, 0)
+
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
/*TXDESC_WORD6*/
-#define SET_TX_DESC_ANTSEL_D(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 30)
-#define SET_TX_DESC_ANTSEL_D_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 30)
-#define GET_TX_DESC_ANTSEL_D(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0x3, 30)
-#define SET_TX_DESC_ANT_MAPD(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 28)
-#define SET_TX_DESC_ANT_MAPD_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 28)
-#define GET_TX_DESC_ANT_MAPD(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0x3, 28)
-#define SET_TX_DESC_ANT_MAPC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 26)
-#define SET_TX_DESC_ANT_MAPC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 26)
-#define GET_TX_DESC_ANT_MAPC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0x3, 26)
-#define SET_TX_DESC_ANT_MAPB(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 24)
-#define SET_TX_DESC_ANT_MAPB_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 24)
-#define GET_TX_DESC_ANT_MAPB(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0x3, 24)
-#define SET_TX_DESC_ANT_MAPA(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 22)
-#define SET_TX_DESC_ANT_MAPA_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 22)
-#define GET_TX_DESC_ANT_MAPA(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0x3, 22)
-#define SET_TX_DESC_ANTSEL_C(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 20)
-#define SET_TX_DESC_ANTSEL_C_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 20)
-#define GET_TX_DESC_ANTSEL_C(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0x3, 20)
-#define SET_TX_DESC_ANTSEL_B(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 18)
-#define SET_TX_DESC_ANTSEL_B_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 18)
-#define GET_TX_DESC_ANTSEL_B(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0x3, 18)
-
-#endif
-
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
-
-#define SET_TX_DESC_ANTSEL_A(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 16)
-#define SET_TX_DESC_ANTSEL_A_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 16)
-#define GET_TX_DESC_ANTSEL_A(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0x3, 16)
-#define SET_TX_DESC_MBSSID(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0xf, 12)
-#define SET_TX_DESC_MBSSID_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0xf, 12)
-#define GET_TX_DESC_MBSSID(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0xf, 12)
-#define SET_TX_DESC_SW_DEFINE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0xfff, 0)
-#define SET_TX_DESC_SW_DEFINE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0xfff, 0)
-#define GET_TX_DESC_SW_DEFINE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0xfff, 0)
+#define SET_TX_DESC_ANTSEL_D(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
+ value, 0x3, 30)
+#define SET_TX_DESC_ANTSEL_D_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 30)
+#define GET_TX_DESC_ANTSEL_D(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \
+ 30)
-/*TXDESC_WORD7*/
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
-#define SET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xff, 24)
-#define SET_TX_DESC_DMA_TXAGG_NUM_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xff, 24)
-#define GET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, 0xff, 24)
+#define SET_TX_DESC_ANT_MAPD_V1(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
+ value, 0x3, 30)
+#define SET_TX_DESC_ANT_MAPD_V1_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 30)
+#define GET_TX_DESC_ANT_MAPD_V1(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \
+ 30)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define SET_TX_DESC_FINAL_DATA_RATE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xff, 24)
-#define SET_TX_DESC_FINAL_DATA_RATE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xff, 24)
-#define GET_TX_DESC_FINAL_DATA_RATE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, 0xff, 24)
-#define SET_TX_DESC_NTX_MAP(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xf, 20)
-#define SET_TX_DESC_NTX_MAP_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xf, 20)
-#define GET_TX_DESC_NTX_MAP(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, 0xf, 20)
+#define SET_TX_DESC_ANT_MAPD(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
+ value, 0x3, 28)
+#define SET_TX_DESC_ANT_MAPD_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 28)
+#define GET_TX_DESC_ANT_MAPD(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \
+ 28)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8198F_SUPPORT)
-#define SET_TX_DESC_TX_BUFF_SIZE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xffff, 0)
-#define SET_TX_DESC_TX_BUFF_SIZE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xffff, 0)
-#define GET_TX_DESC_TX_BUFF_SIZE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, 0xffff, 0)
-#define SET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xffff, 0)
-#define SET_TX_DESC_TXDESC_CHECKSUM_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xffff, 0)
-#define GET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, 0xffff, 0)
-#define SET_TX_DESC_TIMESTAMP(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xffff, 0)
-#define SET_TX_DESC_TIMESTAMP_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xffff, 0)
-#define GET_TX_DESC_TIMESTAMP(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, 0xffff, 0)
+#define SET_TX_DESC_ANT_MAPC_V1(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
+ value, 0x3, 28)
+#define SET_TX_DESC_ANT_MAPC_V1_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 28)
+#define GET_TX_DESC_ANT_MAPC_V1(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \
+ 28)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+#define SET_TX_DESC_ANT_MAPC(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
+ value, 0x3, 26)
+#define SET_TX_DESC_ANT_MAPC_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 26)
+#define GET_TX_DESC_ANT_MAPC(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \
+ 26)
-/*TXDESC_WORD8*/
+#endif
-#define SET_TX_DESC_TXWIFI_CP(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 31)
-#define SET_TX_DESC_TXWIFI_CP_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 31)
-#define GET_TX_DESC_TXWIFI_CP(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 31)
-#define SET_TX_DESC_MAC_CP(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 30)
-#define SET_TX_DESC_MAC_CP_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 30)
-#define GET_TX_DESC_MAC_CP(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 30)
-#define SET_TX_DESC_STW_PKTRE_DIS(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 29)
-#define SET_TX_DESC_STW_PKTRE_DIS_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 29)
-#define GET_TX_DESC_STW_PKTRE_DIS(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 29)
-#define SET_TX_DESC_STW_RB_DIS(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 28)
-#define SET_TX_DESC_STW_RB_DIS_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 28)
-#define GET_TX_DESC_STW_RB_DIS(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 28)
-#define SET_TX_DESC_STW_RATE_DIS(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 27)
-#define SET_TX_DESC_STW_RATE_DIS_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 27)
-#define GET_TX_DESC_STW_RATE_DIS(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 27)
-#define SET_TX_DESC_STW_ANT_DIS(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 26)
-#define SET_TX_DESC_STW_ANT_DIS_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 26)
-#define GET_TX_DESC_STW_ANT_DIS(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 26)
-#define SET_TX_DESC_STW_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 25)
-#define SET_TX_DESC_STW_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 25)
-#define GET_TX_DESC_STW_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 25)
-#define SET_TX_DESC_SMH_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 24)
-#define SET_TX_DESC_SMH_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 24)
-#define GET_TX_DESC_SMH_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 24)
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_ANT_MAPB_V1(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
+ value, 0x3, 26)
+#define SET_TX_DESC_ANT_MAPB_V1_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 26)
+#define GET_TX_DESC_ANT_MAPB_V1(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \
+ 26)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define SET_TX_DESC_TAILPAGE_L(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0xff, 24)
-#define SET_TX_DESC_TAILPAGE_L_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0xff, 24)
-#define GET_TX_DESC_TAILPAGE_L(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0xff, 24)
+#define SET_TX_DESC_ANT_MAPB(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
+ value, 0x3, 24)
+#define SET_TX_DESC_ANT_MAPB_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 24)
+#define GET_TX_DESC_ANT_MAPB(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \
+ 24)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8198F_SUPPORT)
-#define SET_TX_DESC_SDIO_DMASEQ(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0xff, 16)
-#define SET_TX_DESC_SDIO_DMASEQ_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0xff, 16)
-#define GET_TX_DESC_SDIO_DMASEQ(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0xff, 16)
+#define SET_TX_DESC_ANT_MAPA_V1(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
+ value, 0x3, 24)
+#define SET_TX_DESC_ANT_MAPA_V1_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 24)
+#define GET_TX_DESC_ANT_MAPA_V1(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \
+ 24)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_ANT_MAPA(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
+ value, 0x3, 22)
+#define SET_TX_DESC_ANT_MAPA_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 22)
+#define GET_TX_DESC_ANT_MAPA(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \
+ 22)
+#define SET_TX_DESC_ANTSEL_C(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
+ value, 0x3, 20)
+#define SET_TX_DESC_ANTSEL_C_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 20)
+#define GET_TX_DESC_ANTSEL_C(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \
+ 20)
+
+#endif
-#define SET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0xff, 16)
-#define SET_TX_DESC_NEXTHEADPAGE_L_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0xff, 16)
-#define GET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0xff, 16)
-#define SET_TX_DESC_EN_HWSEQ(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 15)
-#define SET_TX_DESC_EN_HWSEQ_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 15)
-#define GET_TX_DESC_EN_HWSEQ(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 15)
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_ANTSEL_B_V1(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
+ value, 0xf, 20)
+#define SET_TX_DESC_ANTSEL_B_V1_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword6, value, 0xf, 20)
+#define GET_TX_DESC_ANTSEL_B_V1(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0xf, \
+ 20)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_ANTSEL_B(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
+ value, 0x3, 18)
+#define SET_TX_DESC_ANTSEL_B_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 18)
+#define GET_TX_DESC_ANTSEL_B(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \
+ 18)
+#define SET_TX_DESC_ANTSEL_A(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
+ value, 0x3, 16)
+#define SET_TX_DESC_ANTSEL_A_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 16)
+#define GET_TX_DESC_ANTSEL_A(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \
+ 16)
-#define SET_TX_DESC_EN_HWEXSEQ(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 14)
-#define SET_TX_DESC_EN_HWEXSEQ_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 14)
-#define GET_TX_DESC_EN_HWEXSEQ(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 14)
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_ANTSEL_A_V1(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
+ value, 0xf, 16)
+#define SET_TX_DESC_ANTSEL_A_V1_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword6, value, 0xf, 16)
+#define GET_TX_DESC_ANTSEL_A_V1(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0xf, \
+ 16)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
-#define SET_TX_DESC_DATA_RC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x3f, 8)
-#define SET_TX_DESC_DATA_RC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x3f, 8)
-#define GET_TX_DESC_DATA_RC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x3f, 8)
-#define SET_TX_DESC_BAR_RTY_TH(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x3, 6)
-#define SET_TX_DESC_BAR_RTY_TH_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x3, 6)
-#define GET_TX_DESC_BAR_RTY_TH(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x3, 6)
-#define SET_TX_DESC_RTS_RC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x3f, 0)
-#define SET_TX_DESC_RTS_RC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x3f, 0)
-#define GET_TX_DESC_RTS_RC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x3f, 0)
+#define SET_TX_DESC_MBSSID(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
+ value, 0xf, 12)
+#define SET_TX_DESC_MBSSID_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword6, value, 0xf, 12)
+#define GET_TX_DESC_MBSSID(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0xf, \
+ 12)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+#define SET_TX_DESC_SW_DEFINE(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
+ value, 0xfff, 0)
+#define SET_TX_DESC_SW_DEFINE_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword6, value, 0xfff, 0)
+#define GET_TX_DESC_SW_DEFINE(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, \
+ 0xfff, 0)
-/*TXDESC_WORD9*/
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
-#define SET_TX_DESC_TAILPAGE_H(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0xf, 28)
-#define SET_TX_DESC_TAILPAGE_H_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0xf, 28)
-#define GET_TX_DESC_TAILPAGE_H(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, 0xf, 28)
-#define SET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0xf, 24)
-#define SET_TX_DESC_NEXTHEADPAGE_H_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0xf, 24)
-#define GET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, 0xf, 24)
+#define SET_TX_DESC_SWPS_SEQ(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
+ value, 0xfff, 0)
+#define SET_TX_DESC_SWPS_SEQ_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword6, value, 0xfff, 0)
+#define GET_TX_DESC_SWPS_SEQ(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, \
+ 0xfff, 0)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
-#define SET_TX_DESC_SW_SEQ(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0xfff, 12)
-#define SET_TX_DESC_SW_SEQ_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0xfff, 12)
-#define GET_TX_DESC_SW_SEQ(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, 0xfff, 12)
-#define SET_TX_DESC_TXBF_PATH(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0x1, 11)
-#define SET_TX_DESC_TXBF_PATH_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0x1, 11)
-#define GET_TX_DESC_TXBF_PATH(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, 0x1, 11)
-#define SET_TX_DESC_PADDING_LEN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0x7ff, 0)
-#define SET_TX_DESC_PADDING_LEN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0x7ff, 0)
-#define GET_TX_DESC_PADDING_LEN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, 0x7ff, 0)
-#define SET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0xff, 0)
-#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0xff, 0)
-#define GET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, 0xff, 0)
+/*TXDESC_WORD7*/
+
+#define SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \
+ value, 0xff, 24)
+#define SET_TX_DESC_DMA_TXAGG_NUM_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword7, value, 0xff, 24)
+#define GET_TX_DESC_DMA_TXAGG_NUM(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0xff, \
+ 24)
+#define SET_TX_DESC_FINAL_DATA_RATE(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \
+ value, 0xff, 24)
+#define SET_TX_DESC_FINAL_DATA_RATE_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword7, value, 0xff, 24)
+#define GET_TX_DESC_FINAL_DATA_RATE(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0xff, \
+ 24)
+#define SET_TX_DESC_NTX_MAP(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \
+ value, 0xf, 20)
+#define SET_TX_DESC_NTX_MAP_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword7, value, 0xf, 20)
+#define GET_TX_DESC_NTX_MAP(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0xf, \
+ 20)
#endif
-#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_ANTSEL_EN(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \
+ value, 0x1, 19)
+#define SET_TX_DESC_ANTSEL_EN_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword7, value, 0x1, 19)
+#define GET_TX_DESC_ANTSEL_EN(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0x1, \
+ 19)
+#define SET_TX_DESC_MBSSID_EX(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \
+ value, 0x7, 16)
+#define SET_TX_DESC_MBSSID_EX_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword7, value, 0x7, 16)
+#define GET_TX_DESC_MBSSID_EX(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0x7, \
+ 16)
+#endif
-/*WORD10*/
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_TX_BUFF_SIZE(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \
+ value, 0xffff, 0)
+#define SET_TX_DESC_TX_BUFF_SIZE_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword7, value, 0xffff, 0)
+#define GET_TX_DESC_TX_BUFF_SIZE(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, \
+ 0xffff, 0)
+#define SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \
+ value, 0xffff, 0)
+#define SET_TX_DESC_TXDESC_CHECKSUM_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword7, value, 0xffff, 0)
+#define GET_TX_DESC_TXDESC_CHECKSUM(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, \
+ 0xffff, 0)
+#define SET_TX_DESC_TIMESTAMP(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \
+ value, 0xffff, 0)
+#define SET_TX_DESC_TIMESTAMP_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword7, value, 0xffff, 0)
+#define GET_TX_DESC_TIMESTAMP(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, \
+ 0xffff, 0)
-#define SET_TX_DESC_MU_DATARATE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword10, __Value, 0xff, 8)
-#define SET_TX_DESC_MU_DATARATE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword10, __Value, 0xff, 8)
-#define GET_TX_DESC_MU_DATARATE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword10, 0xff, 8)
-#define SET_TX_DESC_MU_RC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword10, __Value, 0xf, 4)
-#define SET_TX_DESC_MU_RC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword10, __Value, 0xf, 4)
-#define GET_TX_DESC_MU_RC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword10, 0xf, 4)
-#define SET_TX_DESC_SND_PKT_SEL(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword10, __Value, 0x3, 0)
-#define SET_TX_DESC_SND_PKT_SEL_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword10, __Value, 0x3, 0)
-#define GET_TX_DESC_SND_PKT_SEL(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword10, 0x3, 0)
+/*TXDESC_WORD8*/
+
+#define SET_TX_DESC_TXWIFI_CP(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \
+ value, 0x1, 31)
+#define SET_TX_DESC_TXWIFI_CP_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 31)
+#define GET_TX_DESC_TXWIFI_CP(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, \
+ 31)
+#define SET_TX_DESC_MAC_CP(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \
+ value, 0x1, 30)
+#define SET_TX_DESC_MAC_CP_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 30)
+#define GET_TX_DESC_MAC_CP(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, \
+ 30)
+#define SET_TX_DESC_STW_PKTRE_DIS(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \
+ value, 0x1, 29)
+#define SET_TX_DESC_STW_PKTRE_DIS_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 29)
+#define GET_TX_DESC_STW_PKTRE_DIS(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, \
+ 29)
+#define SET_TX_DESC_STW_RB_DIS(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \
+ value, 0x1, 28)
+#define SET_TX_DESC_STW_RB_DIS_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 28)
+#define GET_TX_DESC_STW_RB_DIS(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, \
+ 28)
+#define SET_TX_DESC_STW_RATE_DIS(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \
+ value, 0x1, 27)
+#define SET_TX_DESC_STW_RATE_DIS_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 27)
+#define GET_TX_DESC_STW_RATE_DIS(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, \
+ 27)
+#define SET_TX_DESC_STW_ANT_DIS(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \
+ value, 0x1, 26)
+#define SET_TX_DESC_STW_ANT_DIS_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 26)
+#define GET_TX_DESC_STW_ANT_DIS(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, \
+ 26)
+#define SET_TX_DESC_STW_EN(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \
+ value, 0x1, 25)
+#define SET_TX_DESC_STW_EN_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 25)
+#define GET_TX_DESC_STW_EN(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, \
+ 25)
+#define SET_TX_DESC_SMH_EN(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \
+ value, 0x1, 24)
+#define SET_TX_DESC_SMH_EN_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 24)
+#define GET_TX_DESC_SMH_EN(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, \
+ 24)
+#define SET_TX_DESC_TAILPAGE_L(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \
+ value, 0xff, 24)
+#define SET_TX_DESC_TAILPAGE_L_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword8, value, 0xff, 24)
+#define GET_TX_DESC_TAILPAGE_L(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xff, \
+ 24)
+#define SET_TX_DESC_SDIO_DMASEQ(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \
+ value, 0xff, 16)
+#define SET_TX_DESC_SDIO_DMASEQ_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword8, value, 0xff, 16)
+#define GET_TX_DESC_SDIO_DMASEQ(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xff, \
+ 16)
+#define SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \
+ value, 0xff, 16)
+#define SET_TX_DESC_NEXTHEADPAGE_L_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword8, value, 0xff, 16)
+#define GET_TX_DESC_NEXTHEADPAGE_L(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xff, \
+ 16)
+#define SET_TX_DESC_EN_HWSEQ(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \
+ value, 0x1, 15)
+#define SET_TX_DESC_EN_HWSEQ_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 15)
+#define GET_TX_DESC_EN_HWSEQ(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, \
+ 15)
+#define SET_TX_DESC_EN_HWEXSEQ(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \
+ value, 0x1, 14)
+#define SET_TX_DESC_EN_HWEXSEQ_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 14)
+#define GET_TX_DESC_EN_HWEXSEQ(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, \
+ 14)
+#define SET_TX_DESC_DATA_RC(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \
+ value, 0x3f, 8)
+#define SET_TX_DESC_DATA_RC_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3f, 8)
+#define GET_TX_DESC_DATA_RC(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3f, \
+ 8)
+#define SET_TX_DESC_BAR_RTY_TH(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \
+ value, 0x3, 6)
+#define SET_TX_DESC_BAR_RTY_TH_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3, 6)
+#define GET_TX_DESC_BAR_RTY_TH(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3, 6)
+#define SET_TX_DESC_RTS_RC(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \
+ value, 0x3f, 0)
+#define SET_TX_DESC_RTS_RC_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3f, 0)
+#define GET_TX_DESC_RTS_RC(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3f, \
+ 0)
+
+/*TXDESC_WORD9*/
+
+#define SET_TX_DESC_TAILPAGE_H(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \
+ value, 0xf, 28)
+#define SET_TX_DESC_TAILPAGE_H_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword9, value, 0xf, 28)
+#define GET_TX_DESC_TAILPAGE_H(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0xf, \
+ 28)
+#define SET_TX_DESC_NEXTHEADPAGE_H(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \
+ value, 0xf, 24)
+#define SET_TX_DESC_NEXTHEADPAGE_H_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword9, value, 0xf, 24)
+#define GET_TX_DESC_NEXTHEADPAGE_H(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0xf, \
+ 24)
+#define SET_TX_DESC_SW_SEQ(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \
+ value, 0xfff, 12)
+#define SET_TX_DESC_SW_SEQ_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword9, value, 0xfff, 12)
+#define GET_TX_DESC_SW_SEQ(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, \
+ 0xfff, 12)
+#define SET_TX_DESC_TXBF_PATH(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \
+ value, 0x1, 11)
+#define SET_TX_DESC_TXBF_PATH_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 11)
+#define GET_TX_DESC_TXBF_PATH(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, \
+ 11)
+#define SET_TX_DESC_PADDING_LEN(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \
+ value, 0x7ff, 0)
+#define SET_TX_DESC_PADDING_LEN_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x7ff, 0)
+#define GET_TX_DESC_PADDING_LEN(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, \
+ 0x7ff, 0)
+#define SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \
+ value, 0xff, 0)
+#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword9, value, 0xff, 0)
+#define GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0xff, \
+ 0)
#endif
+#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/*WORD10*/
+
+#define SET_TX_DESC_MU_DATARATE(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \
+ value, 0xff, 8)
+#define SET_TX_DESC_MU_DATARATE_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword10, value, 0xff, 8)
+#define GET_TX_DESC_MU_DATARATE(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, \
+ 0xff, 8)
+#define SET_TX_DESC_MU_RC(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \
+ value, 0xf, 4)
+#define SET_TX_DESC_MU_RC_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword10, value, 0xf, 4)
+#define GET_TX_DESC_MU_RC(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0xf, \
+ 4)
+#define SET_TX_DESC_SND_PKT_SEL(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \
+ value, 0x3, 0)
+#define SET_TX_DESC_SND_PKT_SEL_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x3, 0)
+#define GET_TX_DESC_SND_PKT_SEL(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x3, \
+ 0)
+
+#endif
#endif
diff --git a/hal/halmac/halmac_tx_desc_buffer_ap.h b/hal/halmac/halmac_tx_desc_buffer_ap.h
new file mode 100644
index 0000000..353571a
--- /dev/null
+++ b/hal/halmac/halmac_tx_desc_buffer_ap.h
@@ -0,0 +1,1078 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_TX_DESC_BUFFER_AP_H_
+#define _HALMAC_TX_DESC_BUFFER_AP_H_
+#if (HALMAC_8814B_SUPPORT)
+
+/*TXDESC_WORD0*/
+
+#define SET_TX_DESC_BUFFER_RDG_EN(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \
+ value, 0x1, 31)
+#define SET_TX_DESC_BUFFER_RDG_EN_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 31)
+#define GET_TX_DESC_BUFFER_RDG_EN(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \
+ 31)
+#define SET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \
+ value, 0x1, 30)
+#define SET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 30)
+#define GET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \
+ 30)
+#define SET_TX_DESC_BUFFER_AGG_EN(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \
+ value, 0x1, 29)
+#define SET_TX_DESC_BUFFER_AGG_EN_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1, 29)
+#define GET_TX_DESC_BUFFER_AGG_EN(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1, \
+ 29)
+#define SET_TX_DESC_BUFFER_PKT_OFFSET(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \
+ value, 0x1f, 24)
+#define SET_TX_DESC_BUFFER_PKT_OFFSET_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword0, value, 0x1f, 24)
+#define GET_TX_DESC_BUFFER_PKT_OFFSET(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0x1f, \
+ 24)
+#define SET_TX_DESC_BUFFER_OFFSET(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \
+ value, 0xff, 16)
+#define SET_TX_DESC_BUFFER_OFFSET_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword0, value, 0xff, 16)
+#define GET_TX_DESC_BUFFER_OFFSET(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, 0xff, \
+ 16)
+#define SET_TX_DESC_BUFFER_TXPKTSIZE(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword0, \
+ value, 0xffff, 0)
+#define SET_TX_DESC_BUFFER_TXPKTSIZE_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword0, value, 0xffff, 0)
+#define GET_TX_DESC_BUFFER_TXPKTSIZE(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword0, \
+ 0xffff, 0)
+
+/*TXDESC_WORD1*/
+
+#define SET_TX_DESC_BUFFER_USERATE(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
+ value, 0x1, 31)
+#define SET_TX_DESC_BUFFER_USERATE_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 31)
+#define GET_TX_DESC_BUFFER_USERATE(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \
+ 31)
+#define SET_TX_DESC_BUFFER_AMSDU(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
+ value, 0x1, 30)
+#define SET_TX_DESC_BUFFER_AMSDU_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 30)
+#define GET_TX_DESC_BUFFER_AMSDU(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \
+ 30)
+#define SET_TX_DESC_BUFFER_EN_HWSEQ(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
+ value, 0x1, 29)
+#define SET_TX_DESC_BUFFER_EN_HWSEQ_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 29)
+#define GET_TX_DESC_BUFFER_EN_HWSEQ(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \
+ 29)
+#define SET_TX_DESC_BUFFER_EN_HWEXSEQ(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
+ value, 0x1, 28)
+#define SET_TX_DESC_BUFFER_EN_HWEXSEQ_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 28)
+#define GET_TX_DESC_BUFFER_EN_HWEXSEQ(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \
+ 28)
+#define SET_TX_DESC_BUFFER_SW_SEQ(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
+ value, 0xfff, 16)
+#define SET_TX_DESC_BUFFER_SW_SEQ_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword1, value, 0xfff, 16)
+#define GET_TX_DESC_BUFFER_SW_SEQ(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, \
+ 0xfff, 16)
+#define SET_TX_DESC_BUFFER_DROP_ID(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
+ value, 0x3, 14)
+#define SET_TX_DESC_BUFFER_DROP_ID_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x3, 14)
+#define GET_TX_DESC_BUFFER_DROP_ID(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x3, \
+ 14)
+#define SET_TX_DESC_BUFFER_MOREDATA(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
+ value, 0x1, 13)
+#define SET_TX_DESC_BUFFER_MOREDATA_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1, 13)
+#define GET_TX_DESC_BUFFER_MOREDATA(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1, \
+ 13)
+#define SET_TX_DESC_BUFFER_QSEL(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
+ value, 0x1f, 8)
+#define SET_TX_DESC_BUFFER_QSEL_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword1, value, 0x1f, 8)
+#define GET_TX_DESC_BUFFER_QSEL(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0x1f, \
+ 8)
+#define SET_TX_DESC_BUFFER_MACID(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword1, \
+ value, 0xff, 0)
+#define SET_TX_DESC_BUFFER_MACID_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword1, value, 0xff, 0)
+#define GET_TX_DESC_BUFFER_MACID(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword1, 0xff, \
+ 0)
+
+/*TXDESC_WORD2*/
+
+#define SET_TX_DESC_BUFFER_CHK_EN(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
+ value, 0x1, 31)
+#define SET_TX_DESC_BUFFER_CHK_EN_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 31)
+#define GET_TX_DESC_BUFFER_CHK_EN(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \
+ 31)
+#define SET_TX_DESC_BUFFER_DISQSELSEQ(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
+ value, 0x1, 30)
+#define SET_TX_DESC_BUFFER_DISQSELSEQ_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 30)
+#define GET_TX_DESC_BUFFER_DISQSELSEQ(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \
+ 30)
+#define SET_TX_DESC_BUFFER_SND_PKT_SEL(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
+ value, 0x3, 28)
+#define SET_TX_DESC_BUFFER_SND_PKT_SEL_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x3, 28)
+#define GET_TX_DESC_BUFFER_SND_PKT_SEL(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x3, \
+ 28)
+#define SET_TX_DESC_BUFFER_DMA_PRI(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
+ value, 0x1, 27)
+#define SET_TX_DESC_BUFFER_DMA_PRI_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x1, 27)
+#define GET_TX_DESC_BUFFER_DMA_PRI(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x1, \
+ 27)
+#define SET_TX_DESC_BUFFER_MAX_AMSDU_MODE(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
+ value, 0x7, 24)
+#define SET_TX_DESC_BUFFER_MAX_AMSDU_MODE_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword2, value, 0x7, 24)
+#define GET_TX_DESC_BUFFER_MAX_AMSDU_MODE(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0x7, \
+ 24)
+#define SET_TX_DESC_BUFFER_DMA_TXAGG_NUM(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
+ value, 0xff, 16)
+#define SET_TX_DESC_BUFFER_DMA_TXAGG_NUM_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword2, value, 0xff, 16)
+#define GET_TX_DESC_BUFFER_DMA_TXAGG_NUM(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, 0xff, \
+ 16)
+#define SET_TX_DESC_BUFFER_TXDESC_CHECKSUM(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword2, \
+ value, 0xffff, 0)
+#define SET_TX_DESC_BUFFER_TXDESC_CHECKSUM_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword2, value, 0xffff, 0)
+#define GET_TX_DESC_BUFFER_TXDESC_CHECKSUM(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword2, \
+ 0xffff, 0)
+
+/*TXDESC_WORD3*/
+
+#define SET_TX_DESC_BUFFER_OFFLOAD_SIZE(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \
+ value, 0x7fff, 16)
+#define SET_TX_DESC_BUFFER_OFFLOAD_SIZE_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x7fff, 16)
+#define GET_TX_DESC_BUFFER_OFFLOAD_SIZE(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, \
+ 0x7fff, 16)
+#define SET_TX_DESC_BUFFER_CHANNEL_DMA(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \
+ value, 0x1f, 11)
+#define SET_TX_DESC_BUFFER_CHANNEL_DMA_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1f, 11)
+#define GET_TX_DESC_BUFFER_CHANNEL_DMA(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1f, \
+ 11)
+#define SET_TX_DESC_BUFFER_MBSSID(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \
+ value, 0xf, 7)
+#define SET_TX_DESC_BUFFER_MBSSID_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword3, value, 0xf, 7)
+#define GET_TX_DESC_BUFFER_MBSSID(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0xf, 7)
+#define SET_TX_DESC_BUFFER_BK(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \
+ value, 0x1, 6)
+#define SET_TX_DESC_BUFFER_BK_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1, 6)
+#define GET_TX_DESC_BUFFER_BK(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1, 6)
+#define SET_TX_DESC_BUFFER_WHEADER_LEN(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword3, \
+ value, 0x1f, 0)
+#define SET_TX_DESC_BUFFER_WHEADER_LEN_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword3, value, 0x1f, 0)
+#define GET_TX_DESC_BUFFER_WHEADER_LEN(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword3, 0x1f, \
+ 0)
+
+/*TXDESC_WORD4*/
+
+#define SET_TX_DESC_BUFFER_TRY_RATE(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \
+ value, 0x1, 26)
+#define SET_TX_DESC_BUFFER_TRY_RATE_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1, 26)
+#define GET_TX_DESC_BUFFER_TRY_RATE(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1, \
+ 26)
+#define SET_TX_DESC_BUFFER_DATA_BW(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \
+ value, 0x3, 24)
+#define SET_TX_DESC_BUFFER_DATA_BW_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x3, 24)
+#define GET_TX_DESC_BUFFER_DATA_BW(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x3, \
+ 24)
+#define SET_TX_DESC_BUFFER_DATA_SHORT(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \
+ value, 0x1, 23)
+#define SET_TX_DESC_BUFFER_DATA_SHORT_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1, 23)
+#define GET_TX_DESC_BUFFER_DATA_SHORT(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1, \
+ 23)
+#define SET_TX_DESC_BUFFER_DATARATE(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \
+ value, 0x7f, 16)
+#define SET_TX_DESC_BUFFER_DATARATE_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x7f, 16)
+#define GET_TX_DESC_BUFFER_DATARATE(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x7f, \
+ 16)
+#define SET_TX_DESC_BUFFER_TXBF_PATH(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \
+ value, 0x1, 11)
+#define SET_TX_DESC_BUFFER_TXBF_PATH_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x1, 11)
+#define GET_TX_DESC_BUFFER_TXBF_PATH(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, 0x1, \
+ 11)
+#define SET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword4, \
+ value, 0x7ff, 0)
+#define SET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword4, value, 0x7ff, 0)
+#define GET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword4, \
+ 0x7ff, 0)
+
+/*TXDESC_WORD5*/
+
+#define SET_TX_DESC_BUFFER_RTY_LMT_EN(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
+ value, 0x1, 31)
+#define SET_TX_DESC_BUFFER_RTY_LMT_EN_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 31)
+#define GET_TX_DESC_BUFFER_RTY_LMT_EN(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, \
+ 31)
+#define SET_TX_DESC_BUFFER_HW_RTS_EN(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
+ value, 0x1, 30)
+#define SET_TX_DESC_BUFFER_HW_RTS_EN_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 30)
+#define GET_TX_DESC_BUFFER_HW_RTS_EN(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, \
+ 30)
+#define SET_TX_DESC_BUFFER_RTS_EN(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
+ value, 0x1, 29)
+#define SET_TX_DESC_BUFFER_RTS_EN_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 29)
+#define GET_TX_DESC_BUFFER_RTS_EN(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, \
+ 29)
+#define SET_TX_DESC_BUFFER_CTS2SELF(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
+ value, 0x1, 28)
+#define SET_TX_DESC_BUFFER_CTS2SELF_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 28)
+#define GET_TX_DESC_BUFFER_CTS2SELF(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, \
+ 28)
+#define SET_TX_DESC_BUFFER_TAILPAGE_H(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
+ value, 0xf, 24)
+#define SET_TX_DESC_BUFFER_TAILPAGE_H_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword5, value, 0xf, 24)
+#define GET_TX_DESC_BUFFER_TAILPAGE_H(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0xf, \
+ 24)
+#define SET_TX_DESC_BUFFER_TAILPAGE_L(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
+ value, 0xff, 16)
+#define SET_TX_DESC_BUFFER_TAILPAGE_L_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword5, value, 0xff, 16)
+#define GET_TX_DESC_BUFFER_TAILPAGE_L(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0xff, \
+ 16)
+#define SET_TX_DESC_BUFFER_NAVUSEHDR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
+ value, 0x1, 15)
+#define SET_TX_DESC_BUFFER_NAVUSEHDR_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 15)
+#define GET_TX_DESC_BUFFER_NAVUSEHDR(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, \
+ 15)
+#define SET_TX_DESC_BUFFER_BMC(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
+ value, 0x1, 14)
+#define SET_TX_DESC_BUFFER_BMC_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 14)
+#define GET_TX_DESC_BUFFER_BMC(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, \
+ 14)
+#define SET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
+ value, 0x3f, 8)
+#define SET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x3f, 8)
+#define GET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x3f, \
+ 8)
+#define SET_TX_DESC_BUFFER_HW_AES_IV(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
+ value, 0x1, 7)
+#define SET_TX_DESC_BUFFER_HW_AES_IV_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 7)
+#define GET_TX_DESC_BUFFER_HW_AES_IV(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, 7)
+#define SET_TX_DESC_BUFFER_BT_NULL(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
+ value, 0x1, 3)
+#define SET_TX_DESC_BUFFER_BT_NULL_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 3)
+#define GET_TX_DESC_BUFFER_BT_NULL(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, 3)
+#define SET_TX_DESC_BUFFER_EN_DESC_ID(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
+ value, 0x1, 2)
+#define SET_TX_DESC_BUFFER_EN_DESC_ID_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x1, 2)
+#define GET_TX_DESC_BUFFER_EN_DESC_ID(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x1, 2)
+#define SET_TX_DESC_BUFFER_SECTYPE(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword5, \
+ value, 0x3, 0)
+#define SET_TX_DESC_BUFFER_SECTYPE_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword5, value, 0x3, 0)
+#define GET_TX_DESC_BUFFER_SECTYPE(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword5, 0x3, 0)
+
+/*TXDESC_WORD6*/
+
+#define SET_TX_DESC_BUFFER_MULTIPLE_PORT(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
+ value, 0x7, 29)
+#define SET_TX_DESC_BUFFER_MULTIPLE_PORT_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x7, 29)
+#define GET_TX_DESC_BUFFER_MULTIPLE_PORT(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x7, \
+ 29)
+#define SET_TX_DESC_BUFFER_POLLUTED(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
+ value, 0x1, 28)
+#define SET_TX_DESC_BUFFER_POLLUTED_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x1, 28)
+#define GET_TX_DESC_BUFFER_POLLUTED(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x1, \
+ 28)
+#define SET_TX_DESC_BUFFER_NULL_1(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
+ value, 0x1, 27)
+#define SET_TX_DESC_BUFFER_NULL_1_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x1, 27)
+#define GET_TX_DESC_BUFFER_NULL_1(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x1, \
+ 27)
+#define SET_TX_DESC_BUFFER_NULL_0(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
+ value, 0x1, 26)
+#define SET_TX_DESC_BUFFER_NULL_0_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x1, 26)
+#define GET_TX_DESC_BUFFER_NULL_0(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x1, \
+ 26)
+#define SET_TX_DESC_BUFFER_TRI_FRAME(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
+ value, 0x1, 25)
+#define SET_TX_DESC_BUFFER_TRI_FRAME_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x1, 25)
+#define GET_TX_DESC_BUFFER_TRI_FRAME(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x1, \
+ 25)
+#define SET_TX_DESC_BUFFER_SPE_RPT(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
+ value, 0x1, 24)
+#define SET_TX_DESC_BUFFER_SPE_RPT_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x1, 24)
+#define GET_TX_DESC_BUFFER_SPE_RPT(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x1, \
+ 24)
+#define SET_TX_DESC_BUFFER_FTM_EN(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
+ value, 0x1, 23)
+#define SET_TX_DESC_BUFFER_FTM_EN_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x1, 23)
+#define GET_TX_DESC_BUFFER_FTM_EN(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x1, \
+ 23)
+#define SET_TX_DESC_BUFFER_MU_DATARATE(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
+ value, 0x7f, 16)
+#define SET_TX_DESC_BUFFER_MU_DATARATE_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x7f, 16)
+#define GET_TX_DESC_BUFFER_MU_DATARATE(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x7f, \
+ 16)
+#define SET_TX_DESC_BUFFER_CCA_RTS(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
+ value, 0x3, 14)
+#define SET_TX_DESC_BUFFER_CCA_RTS_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 14)
+#define GET_TX_DESC_BUFFER_CCA_RTS(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \
+ 14)
+#define SET_TX_DESC_BUFFER_NDPA(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
+ value, 0x3, 12)
+#define SET_TX_DESC_BUFFER_NDPA_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 12)
+#define GET_TX_DESC_BUFFER_NDPA(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, \
+ 12)
+#define SET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
+ value, 0x3, 9)
+#define SET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x3, 9)
+#define GET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, 0x3, 9)
+#define SET_TX_DESC_BUFFER_P_AID(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword6, \
+ value, 0x1ff, 0)
+#define SET_TX_DESC_BUFFER_P_AID_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword6, value, 0x1ff, 0)
+#define GET_TX_DESC_BUFFER_P_AID(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword6, \
+ 0x1ff, 0)
+
+/*TXDESC_WORD7*/
+
+#define SET_TX_DESC_BUFFER_SW_DEFINE(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \
+ value, 0xfff, 16)
+#define SET_TX_DESC_BUFFER_SW_DEFINE_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword7, value, 0xfff, 16)
+#define GET_TX_DESC_BUFFER_SW_DEFINE(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, \
+ 0xfff, 16)
+#define SET_TX_DESC_BUFFER_CTRL_CNT_VALID(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \
+ value, 0x1, 9)
+#define SET_TX_DESC_BUFFER_CTRL_CNT_VALID_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword7, value, 0x1, 9)
+#define GET_TX_DESC_BUFFER_CTRL_CNT_VALID(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0x1, 9)
+#define SET_TX_DESC_BUFFER_CTRL_CNT(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \
+ value, 0xf, 5)
+#define SET_TX_DESC_BUFFER_CTRL_CNT_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword7, value, 0xf, 5)
+#define GET_TX_DESC_BUFFER_CTRL_CNT(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0xf, 5)
+#define SET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword7, \
+ value, 0x1f, 0)
+#define SET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword7, value, 0x1f, 0)
+#define GET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword7, 0x1f, \
+ 0)
+
+/*TXDESC_WORD8*/
+
+#define SET_TX_DESC_BUFFER_PATH_MAPA(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \
+ value, 0x3, 30)
+#define SET_TX_DESC_BUFFER_PATH_MAPA_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3, 30)
+#define GET_TX_DESC_BUFFER_PATH_MAPA(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3, \
+ 30)
+#define SET_TX_DESC_BUFFER_PATH_MAPB(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \
+ value, 0x3, 28)
+#define SET_TX_DESC_BUFFER_PATH_MAPB_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3, 28)
+#define GET_TX_DESC_BUFFER_PATH_MAPB(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3, \
+ 28)
+#define SET_TX_DESC_BUFFER_PATH_MAPC(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \
+ value, 0x3, 26)
+#define SET_TX_DESC_BUFFER_PATH_MAPC_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3, 26)
+#define GET_TX_DESC_BUFFER_PATH_MAPC(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3, \
+ 26)
+#define SET_TX_DESC_BUFFER_PATH_MAPD(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \
+ value, 0x3, 24)
+#define SET_TX_DESC_BUFFER_PATH_MAPD_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x3, 24)
+#define GET_TX_DESC_BUFFER_PATH_MAPD(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x3, \
+ 24)
+#define SET_TX_DESC_BUFFER_ANTSEL_A(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \
+ value, 0xf, 20)
+#define SET_TX_DESC_BUFFER_ANTSEL_A_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword8, value, 0xf, 20)
+#define GET_TX_DESC_BUFFER_ANTSEL_A(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xf, \
+ 20)
+#define SET_TX_DESC_BUFFER_ANTSEL_B(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \
+ value, 0xf, 16)
+#define SET_TX_DESC_BUFFER_ANTSEL_B_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword8, value, 0xf, 16)
+#define GET_TX_DESC_BUFFER_ANTSEL_B(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xf, \
+ 16)
+#define SET_TX_DESC_BUFFER_ANTSEL_C(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \
+ value, 0xf, 12)
+#define SET_TX_DESC_BUFFER_ANTSEL_C_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword8, value, 0xf, 12)
+#define GET_TX_DESC_BUFFER_ANTSEL_C(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xf, \
+ 12)
+#define SET_TX_DESC_BUFFER_ANTSEL_D(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \
+ value, 0xf, 8)
+#define SET_TX_DESC_BUFFER_ANTSEL_D_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword8, value, 0xf, 8)
+#define GET_TX_DESC_BUFFER_ANTSEL_D(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xf, 8)
+#define SET_TX_DESC_BUFFER_NTX_PATH_EN(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \
+ value, 0xf, 4)
+#define SET_TX_DESC_BUFFER_NTX_PATH_EN_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword8, value, 0xf, 4)
+#define GET_TX_DESC_BUFFER_NTX_PATH_EN(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0xf, 4)
+#define SET_TX_DESC_BUFFER_ANTLSEL_EN(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \
+ value, 0x1, 3)
+#define SET_TX_DESC_BUFFER_ANTLSEL_EN_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x1, 3)
+#define GET_TX_DESC_BUFFER_ANTLSEL_EN(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x1, 3)
+#define SET_TX_DESC_BUFFER_AMPDU_DENSITY(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword8, \
+ value, 0x7, 0)
+#define SET_TX_DESC_BUFFER_AMPDU_DENSITY_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword8, value, 0x7, 0)
+#define GET_TX_DESC_BUFFER_AMPDU_DENSITY(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword8, 0x7, 0)
+
+/*TXDESC_WORD9*/
+
+#define SET_TX_DESC_BUFFER_VCS_STBC(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \
+ value, 0x3, 30)
+#define SET_TX_DESC_BUFFER_VCS_STBC_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x3, 30)
+#define GET_TX_DESC_BUFFER_VCS_STBC(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x3, \
+ 30)
+#define SET_TX_DESC_BUFFER_DATA_STBC(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \
+ value, 0x3, 28)
+#define SET_TX_DESC_BUFFER_DATA_STBC_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x3, 28)
+#define GET_TX_DESC_BUFFER_DATA_STBC(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x3, \
+ 28)
+#define SET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \
+ value, 0xf, 24)
+#define SET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword9, value, 0xf, 24)
+#define GET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0xf, \
+ 24)
+#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \
+ value, 0x1, 23)
+#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 23)
+#define GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, \
+ 23)
+#define SET_TX_DESC_BUFFER_MHR_CP(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \
+ value, 0x1, 22)
+#define SET_TX_DESC_BUFFER_MHR_CP_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 22)
+#define GET_TX_DESC_BUFFER_MHR_CP(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, \
+ 22)
+#define SET_TX_DESC_BUFFER_SMH_EN(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \
+ value, 0x1, 21)
+#define SET_TX_DESC_BUFFER_SMH_EN_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 21)
+#define GET_TX_DESC_BUFFER_SMH_EN(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, \
+ 21)
+#define SET_TX_DESC_BUFFER_RTSRATE(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \
+ value, 0x1f, 16)
+#define SET_TX_DESC_BUFFER_RTSRATE_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1f, 16)
+#define GET_TX_DESC_BUFFER_RTSRATE(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1f, \
+ 16)
+#define SET_TX_DESC_BUFFER_SMH_CAM(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \
+ value, 0xff, 8)
+#define SET_TX_DESC_BUFFER_SMH_CAM_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword9, value, 0xff, 8)
+#define GET_TX_DESC_BUFFER_SMH_CAM(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0xff, \
+ 8)
+#define SET_TX_DESC_BUFFER_ARFR_TABLE_SEL(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \
+ value, 0x1, 7)
+#define SET_TX_DESC_BUFFER_ARFR_TABLE_SEL_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 7)
+#define GET_TX_DESC_BUFFER_ARFR_TABLE_SEL(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 7)
+#define SET_TX_DESC_BUFFER_ARFR_HT_EN(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \
+ value, 0x1, 6)
+#define SET_TX_DESC_BUFFER_ARFR_HT_EN_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 6)
+#define GET_TX_DESC_BUFFER_ARFR_HT_EN(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 6)
+#define SET_TX_DESC_BUFFER_ARFR_OFDM_EN(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \
+ value, 0x1, 5)
+#define SET_TX_DESC_BUFFER_ARFR_OFDM_EN_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 5)
+#define GET_TX_DESC_BUFFER_ARFR_OFDM_EN(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 5)
+#define SET_TX_DESC_BUFFER_ARFR_CCK_EN(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \
+ value, 0x1, 4)
+#define SET_TX_DESC_BUFFER_ARFR_CCK_EN_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 4)
+#define GET_TX_DESC_BUFFER_ARFR_CCK_EN(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 4)
+#define SET_TX_DESC_BUFFER_RTS_SHORT(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \
+ value, 0x1, 3)
+#define SET_TX_DESC_BUFFER_RTS_SHORT_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 3)
+#define GET_TX_DESC_BUFFER_RTS_SHORT(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 3)
+#define SET_TX_DESC_BUFFER_DISDATAFB(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \
+ value, 0x1, 2)
+#define SET_TX_DESC_BUFFER_DISDATAFB_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 2)
+#define GET_TX_DESC_BUFFER_DISDATAFB(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 2)
+#define SET_TX_DESC_BUFFER_DISRTSFB(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \
+ value, 0x1, 1)
+#define SET_TX_DESC_BUFFER_DISRTSFB_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 1)
+#define GET_TX_DESC_BUFFER_DISRTSFB(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 1)
+#define SET_TX_DESC_BUFFER_EXT_EDCA(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword9, \
+ value, 0x1, 0)
+#define SET_TX_DESC_BUFFER_EXT_EDCA_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword9, value, 0x1, 0)
+#define GET_TX_DESC_BUFFER_EXT_EDCA(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword9, 0x1, 0)
+
+/*TXDESC_WORD10*/
+
+#define SET_TX_DESC_BUFFER_AMPDU_MAX_TIME(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \
+ value, 0xff, 24)
+#define SET_TX_DESC_BUFFER_AMPDU_MAX_TIME_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword10, value, 0xff, 24)
+#define GET_TX_DESC_BUFFER_AMPDU_MAX_TIME(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, \
+ 0xff, 24)
+#define SET_TX_DESC_BUFFER_SPECIAL_CW(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \
+ value, 0x1, 23)
+#define SET_TX_DESC_BUFFER_SPECIAL_CW_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 23)
+#define GET_TX_DESC_BUFFER_SPECIAL_CW(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \
+ 23)
+#define SET_TX_DESC_BUFFER_RDG_NAV_EXT(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \
+ value, 0x1, 22)
+#define SET_TX_DESC_BUFFER_RDG_NAV_EXT_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 22)
+#define GET_TX_DESC_BUFFER_RDG_NAV_EXT(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \
+ 22)
+#define SET_TX_DESC_BUFFER_RAW(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \
+ value, 0x1, 21)
+#define SET_TX_DESC_BUFFER_RAW_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 21)
+#define GET_TX_DESC_BUFFER_RAW(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \
+ 21)
+#define SET_TX_DESC_BUFFER_MAX_AGG_NUM(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \
+ value, 0x1f, 16)
+#define SET_TX_DESC_BUFFER_MAX_AGG_NUM_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1f, 16)
+#define GET_TX_DESC_BUFFER_MAX_AGG_NUM(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, \
+ 0x1f, 16)
+#define SET_TX_DESC_BUFFER_FINAL_DATA_RATE(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \
+ value, 0xff, 8)
+#define SET_TX_DESC_BUFFER_FINAL_DATA_RATE_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword10, value, 0xff, 8)
+#define GET_TX_DESC_BUFFER_FINAL_DATA_RATE(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, \
+ 0xff, 8)
+#define SET_TX_DESC_BUFFER_GF(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \
+ value, 0x1, 7)
+#define SET_TX_DESC_BUFFER_GF_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 7)
+#define GET_TX_DESC_BUFFER_GF(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \
+ 7)
+#define SET_TX_DESC_BUFFER_MOREFRAG(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \
+ value, 0x1, 6)
+#define SET_TX_DESC_BUFFER_MOREFRAG_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 6)
+#define GET_TX_DESC_BUFFER_MOREFRAG(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \
+ 6)
+#define SET_TX_DESC_BUFFER_NOACM(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \
+ value, 0x1, 5)
+#define SET_TX_DESC_BUFFER_NOACM_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 5)
+#define GET_TX_DESC_BUFFER_NOACM(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \
+ 5)
+#define SET_TX_DESC_BUFFER_HTC(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \
+ value, 0x1, 4)
+#define SET_TX_DESC_BUFFER_HTC_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 4)
+#define GET_TX_DESC_BUFFER_HTC(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \
+ 4)
+#define SET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \
+ value, 0x1, 3)
+#define SET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 3)
+#define GET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \
+ 3)
+#define SET_TX_DESC_BUFFER_USE_MAX_TIME_EN(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \
+ value, 0x1, 2)
+#define SET_TX_DESC_BUFFER_USE_MAX_TIME_EN_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x1, 2)
+#define GET_TX_DESC_BUFFER_USE_MAX_TIME_EN(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x1, \
+ 2)
+#define SET_TX_DESC_BUFFER_HW_SSN_SEL(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword10, \
+ value, 0x3, 0)
+#define SET_TX_DESC_BUFFER_HW_SSN_SEL_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword10, value, 0x3, 0)
+#define GET_TX_DESC_BUFFER_HW_SSN_SEL(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword10, 0x3, \
+ 0)
+
+/*TXDESC_WORD11*/
+
+#define SET_TX_DESC_BUFFER_ADDR_CAM(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword11, \
+ value, 0xff, 24)
+#define SET_TX_DESC_BUFFER_ADDR_CAM_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword11, value, 0xff, 24)
+#define GET_TX_DESC_BUFFER_ADDR_CAM(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword11, \
+ 0xff, 24)
+#define SET_TX_DESC_BUFFER_SND_TARGET(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword11, \
+ value, 0xff, 16)
+#define SET_TX_DESC_BUFFER_SND_TARGET_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword11, value, 0xff, 16)
+#define GET_TX_DESC_BUFFER_SND_TARGET(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword11, \
+ 0xff, 16)
+#define SET_TX_DESC_BUFFER_DATA_LDPC(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword11, \
+ value, 0x1, 15)
+#define SET_TX_DESC_BUFFER_DATA_LDPC_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword11, value, 0x1, 15)
+#define GET_TX_DESC_BUFFER_DATA_LDPC(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword11, 0x1, \
+ 15)
+#define SET_TX_DESC_BUFFER_LSIG_TXOP_EN(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword11, \
+ value, 0x1, 14)
+#define SET_TX_DESC_BUFFER_LSIG_TXOP_EN_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword11, value, 0x1, 14)
+#define GET_TX_DESC_BUFFER_LSIG_TXOP_EN(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword11, 0x1, \
+ 14)
+#define SET_TX_DESC_BUFFER_G_ID(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword11, \
+ value, 0x3f, 8)
+#define SET_TX_DESC_BUFFER_G_ID_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword11, value, 0x3f, 8)
+#define GET_TX_DESC_BUFFER_G_ID(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword11, \
+ 0x3f, 8)
+#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword11, \
+ value, 0xf, 4)
+#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword11, value, 0xf, 4)
+#define GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword11, 0xf, \
+ 4)
+#define SET_TX_DESC_BUFFER_DATA_SC(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword11, \
+ value, 0xf, 0)
+#define SET_TX_DESC_BUFFER_DATA_SC_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword11, value, 0xf, 0)
+#define GET_TX_DESC_BUFFER_DATA_SC(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword11, 0xf, \
+ 0)
+
+/*TXDESC_WORD12*/
+
+#define SET_TX_DESC_BUFFER_LEN1_L(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword12, \
+ value, 0x7f, 17)
+#define SET_TX_DESC_BUFFER_LEN1_L_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword12, value, 0x7f, 17)
+#define GET_TX_DESC_BUFFER_LEN1_L(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword12, \
+ 0x7f, 17)
+#define SET_TX_DESC_BUFFER_LEN0(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword12, \
+ value, 0x1fff, 4)
+#define SET_TX_DESC_BUFFER_LEN0_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword12, value, 0x1fff, 4)
+#define GET_TX_DESC_BUFFER_LEN0(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword12, \
+ 0x1fff, 4)
+#define SET_TX_DESC_BUFFER_PKT_NUM(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword12, \
+ value, 0xf, 0)
+#define SET_TX_DESC_BUFFER_PKT_NUM_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword12, value, 0xf, 0)
+#define GET_TX_DESC_BUFFER_PKT_NUM(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword12, 0xf, \
+ 0)
+
+/*TXDESC_WORD13*/
+
+#define SET_TX_DESC_BUFFER_LEN3(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword13, \
+ value, 0x1fff, 19)
+#define SET_TX_DESC_BUFFER_LEN3_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword13, value, 0x1fff, 19)
+#define GET_TX_DESC_BUFFER_LEN3(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword13, \
+ 0x1fff, 19)
+#define SET_TX_DESC_BUFFER_LEN2(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword13, \
+ value, 0x1fff, 6)
+#define SET_TX_DESC_BUFFER_LEN2_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword13, value, 0x1fff, 6)
+#define GET_TX_DESC_BUFFER_LEN2(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword13, \
+ 0x1fff, 6)
+#define SET_TX_DESC_BUFFER_LEN1_H(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_CLR(((struct halmac_tx_desc *)txdesc)->dword13, \
+ value, 0x3f, 0)
+#define SET_TX_DESC_BUFFER_LEN1_H_NO_CLR(txdesc, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc)->dword13, value, 0x3f, 0)
+#define GET_TX_DESC_BUFFER_LEN1_H(txdesc) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc)->dword13, \
+ 0x3f, 0)
+
+#endif
+
+#endif
diff --git a/hal/halmac/halmac_tx_desc_buffer_chip.h b/hal/halmac/halmac_tx_desc_buffer_chip.h
new file mode 100644
index 0000000..a3e80ca
--- /dev/null
+++ b/hal/halmac/halmac_tx_desc_buffer_chip.h
@@ -0,0 +1,509 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_TX_DESC_BUFFER_CHIP_H_
+#define _HALMAC_TX_DESC_BUFFER_CHIP_H_
+#if (HALMAC_8814B_SUPPORT)
+
+/*TXDESC_WORD0*/
+
+#define SET_TX_DESC_BUFFER_RDG_EN_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_RDG_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_RDG_EN_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_RDG_EN(txdesc)
+#define SET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL(txdesc, value)
+#define GET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL(txdesc)
+#define SET_TX_DESC_BUFFER_AGG_EN_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_AGG_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_AGG_EN_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_AGG_EN(txdesc)
+#define SET_TX_DESC_BUFFER_PKT_OFFSET_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_PKT_OFFSET(txdesc, value)
+#define GET_TX_DESC_BUFFER_PKT_OFFSET_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_PKT_OFFSET(txdesc)
+#define SET_TX_DESC_BUFFER_OFFSET_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_OFFSET(txdesc, value)
+#define GET_TX_DESC_BUFFER_OFFSET_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_OFFSET(txdesc)
+#define SET_TX_DESC_BUFFER_TXPKTSIZE_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_TXPKTSIZE(txdesc, value)
+#define GET_TX_DESC_BUFFER_TXPKTSIZE_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_TXPKTSIZE(txdesc)
+
+/*TXDESC_WORD1*/
+
+#define SET_TX_DESC_BUFFER_USERATE_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_USERATE(txdesc, value)
+#define GET_TX_DESC_BUFFER_USERATE_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_USERATE(txdesc)
+#define SET_TX_DESC_BUFFER_AMSDU_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_AMSDU(txdesc, value)
+#define GET_TX_DESC_BUFFER_AMSDU_8814B(txdesc) GET_TX_DESC_BUFFER_AMSDU(txdesc)
+#define SET_TX_DESC_BUFFER_EN_HWSEQ_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_EN_HWSEQ(txdesc, value)
+#define GET_TX_DESC_BUFFER_EN_HWSEQ_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_EN_HWSEQ(txdesc)
+#define SET_TX_DESC_BUFFER_EN_HWEXSEQ_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_EN_HWEXSEQ(txdesc, value)
+#define GET_TX_DESC_BUFFER_EN_HWEXSEQ_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_EN_HWEXSEQ(txdesc)
+#define SET_TX_DESC_BUFFER_SW_SEQ_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_SW_SEQ(txdesc, value)
+#define GET_TX_DESC_BUFFER_SW_SEQ_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_SW_SEQ(txdesc)
+#define SET_TX_DESC_BUFFER_DROP_ID_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_DROP_ID(txdesc, value)
+#define GET_TX_DESC_BUFFER_DROP_ID_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_DROP_ID(txdesc)
+#define SET_TX_DESC_BUFFER_MOREDATA_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_MOREDATA(txdesc, value)
+#define GET_TX_DESC_BUFFER_MOREDATA_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_MOREDATA(txdesc)
+#define SET_TX_DESC_BUFFER_QSEL_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_QSEL(txdesc, value)
+#define GET_TX_DESC_BUFFER_QSEL_8814B(txdesc) GET_TX_DESC_BUFFER_QSEL(txdesc)
+#define SET_TX_DESC_BUFFER_MACID_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_MACID(txdesc, value)
+#define GET_TX_DESC_BUFFER_MACID_8814B(txdesc) GET_TX_DESC_BUFFER_MACID(txdesc)
+
+/*TXDESC_WORD2*/
+
+#define SET_TX_DESC_BUFFER_CHK_EN_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_CHK_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_CHK_EN_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_CHK_EN(txdesc)
+#define SET_TX_DESC_BUFFER_DISQSELSEQ_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_DISQSELSEQ(txdesc, value)
+#define GET_TX_DESC_BUFFER_DISQSELSEQ_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_DISQSELSEQ(txdesc)
+#define SET_TX_DESC_BUFFER_SND_PKT_SEL_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_SND_PKT_SEL(txdesc, value)
+#define GET_TX_DESC_BUFFER_SND_PKT_SEL_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_SND_PKT_SEL(txdesc)
+#define SET_TX_DESC_BUFFER_DMA_PRI_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_DMA_PRI(txdesc, value)
+#define GET_TX_DESC_BUFFER_DMA_PRI_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_DMA_PRI(txdesc)
+#define SET_TX_DESC_BUFFER_MAX_AMSDU_MODE_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_MAX_AMSDU_MODE(txdesc, value)
+#define GET_TX_DESC_BUFFER_MAX_AMSDU_MODE_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_MAX_AMSDU_MODE(txdesc)
+#define SET_TX_DESC_BUFFER_DMA_TXAGG_NUM_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_DMA_TXAGG_NUM(txdesc, value)
+#define GET_TX_DESC_BUFFER_DMA_TXAGG_NUM_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_DMA_TXAGG_NUM(txdesc)
+#define SET_TX_DESC_BUFFER_TXDESC_CHECKSUM_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_TXDESC_CHECKSUM(txdesc, value)
+#define GET_TX_DESC_BUFFER_TXDESC_CHECKSUM_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_TXDESC_CHECKSUM(txdesc)
+
+/*TXDESC_WORD3*/
+
+#define SET_TX_DESC_BUFFER_OFFLOAD_SIZE_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_OFFLOAD_SIZE(txdesc, value)
+#define GET_TX_DESC_BUFFER_OFFLOAD_SIZE_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_OFFLOAD_SIZE(txdesc)
+#define SET_TX_DESC_BUFFER_CHANNEL_DMA_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_CHANNEL_DMA(txdesc, value)
+#define GET_TX_DESC_BUFFER_CHANNEL_DMA_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_CHANNEL_DMA(txdesc)
+#define SET_TX_DESC_BUFFER_MBSSID_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_MBSSID(txdesc, value)
+#define GET_TX_DESC_BUFFER_MBSSID_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_MBSSID(txdesc)
+#define SET_TX_DESC_BUFFER_BK_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_BK(txdesc, value)
+#define GET_TX_DESC_BUFFER_BK_8814B(txdesc) GET_TX_DESC_BUFFER_BK(txdesc)
+#define SET_TX_DESC_BUFFER_WHEADER_LEN_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_WHEADER_LEN(txdesc, value)
+#define GET_TX_DESC_BUFFER_WHEADER_LEN_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_WHEADER_LEN(txdesc)
+
+/*TXDESC_WORD4*/
+
+#define SET_TX_DESC_BUFFER_TRY_RATE_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_TRY_RATE(txdesc, value)
+#define GET_TX_DESC_BUFFER_TRY_RATE_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_TRY_RATE(txdesc)
+#define SET_TX_DESC_BUFFER_DATA_BW_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_DATA_BW(txdesc, value)
+#define GET_TX_DESC_BUFFER_DATA_BW_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_DATA_BW(txdesc)
+#define SET_TX_DESC_BUFFER_DATA_SHORT_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_DATA_SHORT(txdesc, value)
+#define GET_TX_DESC_BUFFER_DATA_SHORT_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_DATA_SHORT(txdesc)
+#define SET_TX_DESC_BUFFER_DATARATE_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_DATARATE(txdesc, value)
+#define GET_TX_DESC_BUFFER_DATARATE_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_DATARATE(txdesc)
+#define SET_TX_DESC_BUFFER_TXBF_PATH_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_TXBF_PATH(txdesc, value)
+#define GET_TX_DESC_BUFFER_TXBF_PATH_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_TXBF_PATH(txdesc)
+#define SET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET(txdesc, value)
+#define GET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET(txdesc)
+
+/*TXDESC_WORD5*/
+
+#define SET_TX_DESC_BUFFER_RTY_LMT_EN_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_RTY_LMT_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_RTY_LMT_EN_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_RTY_LMT_EN(txdesc)
+#define SET_TX_DESC_BUFFER_HW_RTS_EN_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_HW_RTS_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_HW_RTS_EN_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_HW_RTS_EN(txdesc)
+#define SET_TX_DESC_BUFFER_RTS_EN_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_RTS_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_RTS_EN_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_RTS_EN(txdesc)
+#define SET_TX_DESC_BUFFER_CTS2SELF_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_CTS2SELF(txdesc, value)
+#define GET_TX_DESC_BUFFER_CTS2SELF_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_CTS2SELF(txdesc)
+#define SET_TX_DESC_BUFFER_TAILPAGE_H_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_TAILPAGE_H(txdesc, value)
+#define GET_TX_DESC_BUFFER_TAILPAGE_H_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_TAILPAGE_H(txdesc)
+#define SET_TX_DESC_BUFFER_TAILPAGE_L_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_TAILPAGE_L(txdesc, value)
+#define GET_TX_DESC_BUFFER_TAILPAGE_L_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_TAILPAGE_L(txdesc)
+#define SET_TX_DESC_BUFFER_NAVUSEHDR_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_NAVUSEHDR(txdesc, value)
+#define GET_TX_DESC_BUFFER_NAVUSEHDR_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_NAVUSEHDR(txdesc)
+#define SET_TX_DESC_BUFFER_BMC_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_BMC(txdesc, value)
+#define GET_TX_DESC_BUFFER_BMC_8814B(txdesc) GET_TX_DESC_BUFFER_BMC(txdesc)
+#define SET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT(txdesc, value)
+#define GET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT(txdesc)
+#define SET_TX_DESC_BUFFER_HW_AES_IV_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_HW_AES_IV(txdesc, value)
+#define GET_TX_DESC_BUFFER_HW_AES_IV_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_HW_AES_IV(txdesc)
+#define SET_TX_DESC_BUFFER_BT_NULL_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_BT_NULL(txdesc, value)
+#define GET_TX_DESC_BUFFER_BT_NULL_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_BT_NULL(txdesc)
+#define SET_TX_DESC_BUFFER_EN_DESC_ID_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_EN_DESC_ID(txdesc, value)
+#define GET_TX_DESC_BUFFER_EN_DESC_ID_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_EN_DESC_ID(txdesc)
+#define SET_TX_DESC_BUFFER_SECTYPE_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_SECTYPE(txdesc, value)
+#define GET_TX_DESC_BUFFER_SECTYPE_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_SECTYPE(txdesc)
+
+/*TXDESC_WORD6*/
+
+#define SET_TX_DESC_BUFFER_MULTIPLE_PORT_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_MULTIPLE_PORT(txdesc, value)
+#define GET_TX_DESC_BUFFER_MULTIPLE_PORT_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_MULTIPLE_PORT(txdesc)
+#define SET_TX_DESC_BUFFER_POLLUTED_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_POLLUTED(txdesc, value)
+#define GET_TX_DESC_BUFFER_POLLUTED_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_POLLUTED(txdesc)
+#define SET_TX_DESC_BUFFER_NULL_1_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_NULL_1(txdesc, value)
+#define GET_TX_DESC_BUFFER_NULL_1_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_NULL_1(txdesc)
+#define SET_TX_DESC_BUFFER_NULL_0_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_NULL_0(txdesc, value)
+#define GET_TX_DESC_BUFFER_NULL_0_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_NULL_0(txdesc)
+#define SET_TX_DESC_BUFFER_TRI_FRAME_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_TRI_FRAME(txdesc, value)
+#define GET_TX_DESC_BUFFER_TRI_FRAME_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_TRI_FRAME(txdesc)
+#define SET_TX_DESC_BUFFER_SPE_RPT_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_SPE_RPT(txdesc, value)
+#define GET_TX_DESC_BUFFER_SPE_RPT_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_SPE_RPT(txdesc)
+#define SET_TX_DESC_BUFFER_FTM_EN_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_FTM_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_FTM_EN_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_FTM_EN(txdesc)
+#define SET_TX_DESC_BUFFER_MU_DATARATE_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_MU_DATARATE(txdesc, value)
+#define GET_TX_DESC_BUFFER_MU_DATARATE_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_MU_DATARATE(txdesc)
+#define SET_TX_DESC_BUFFER_CCA_RTS_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_CCA_RTS(txdesc, value)
+#define GET_TX_DESC_BUFFER_CCA_RTS_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_CCA_RTS(txdesc)
+#define SET_TX_DESC_BUFFER_NDPA_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_NDPA(txdesc, value)
+#define GET_TX_DESC_BUFFER_NDPA_8814B(txdesc) GET_TX_DESC_BUFFER_NDPA(txdesc)
+#define SET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE(txdesc, value)
+#define GET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE(txdesc)
+#define SET_TX_DESC_BUFFER_P_AID_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_P_AID(txdesc, value)
+#define GET_TX_DESC_BUFFER_P_AID_8814B(txdesc) GET_TX_DESC_BUFFER_P_AID(txdesc)
+
+/*TXDESC_WORD7*/
+
+#define SET_TX_DESC_BUFFER_SW_DEFINE_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_SW_DEFINE(txdesc, value)
+#define GET_TX_DESC_BUFFER_SW_DEFINE_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_SW_DEFINE(txdesc)
+#define SET_TX_DESC_BUFFER_CTRL_CNT_VALID_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_CTRL_CNT_VALID(txdesc, value)
+#define GET_TX_DESC_BUFFER_CTRL_CNT_VALID_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_CTRL_CNT_VALID(txdesc)
+#define SET_TX_DESC_BUFFER_CTRL_CNT_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_CTRL_CNT(txdesc, value)
+#define GET_TX_DESC_BUFFER_CTRL_CNT_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_CTRL_CNT(txdesc)
+#define SET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE(txdesc, value)
+#define GET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE(txdesc)
+
+/*TXDESC_WORD8*/
+
+#define SET_TX_DESC_BUFFER_PATH_MAPA_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_PATH_MAPA(txdesc, value)
+#define GET_TX_DESC_BUFFER_PATH_MAPA_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_PATH_MAPA(txdesc)
+#define SET_TX_DESC_BUFFER_PATH_MAPB_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_PATH_MAPB(txdesc, value)
+#define GET_TX_DESC_BUFFER_PATH_MAPB_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_PATH_MAPB(txdesc)
+#define SET_TX_DESC_BUFFER_PATH_MAPC_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_PATH_MAPC(txdesc, value)
+#define GET_TX_DESC_BUFFER_PATH_MAPC_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_PATH_MAPC(txdesc)
+#define SET_TX_DESC_BUFFER_PATH_MAPD_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_PATH_MAPD(txdesc, value)
+#define GET_TX_DESC_BUFFER_PATH_MAPD_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_PATH_MAPD(txdesc)
+#define SET_TX_DESC_BUFFER_ANTSEL_A_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_ANTSEL_A(txdesc, value)
+#define GET_TX_DESC_BUFFER_ANTSEL_A_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_ANTSEL_A(txdesc)
+#define SET_TX_DESC_BUFFER_ANTSEL_B_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_ANTSEL_B(txdesc, value)
+#define GET_TX_DESC_BUFFER_ANTSEL_B_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_ANTSEL_B(txdesc)
+#define SET_TX_DESC_BUFFER_ANTSEL_C_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_ANTSEL_C(txdesc, value)
+#define GET_TX_DESC_BUFFER_ANTSEL_C_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_ANTSEL_C(txdesc)
+#define SET_TX_DESC_BUFFER_ANTSEL_D_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_ANTSEL_D(txdesc, value)
+#define GET_TX_DESC_BUFFER_ANTSEL_D_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_ANTSEL_D(txdesc)
+#define SET_TX_DESC_BUFFER_NTX_PATH_EN_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_NTX_PATH_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_NTX_PATH_EN_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_NTX_PATH_EN(txdesc)
+#define SET_TX_DESC_BUFFER_ANTLSEL_EN_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_ANTLSEL_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_ANTLSEL_EN_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_ANTLSEL_EN(txdesc)
+#define SET_TX_DESC_BUFFER_AMPDU_DENSITY_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_AMPDU_DENSITY(txdesc, value)
+#define GET_TX_DESC_BUFFER_AMPDU_DENSITY_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_AMPDU_DENSITY(txdesc)
+
+/*TXDESC_WORD9*/
+
+#define SET_TX_DESC_BUFFER_VCS_STBC_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_VCS_STBC(txdesc, value)
+#define GET_TX_DESC_BUFFER_VCS_STBC_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_VCS_STBC(txdesc)
+#define SET_TX_DESC_BUFFER_DATA_STBC_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_DATA_STBC(txdesc, value)
+#define GET_TX_DESC_BUFFER_DATA_STBC_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_DATA_STBC(txdesc)
+#define SET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE(txdesc, value)
+#define GET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE(txdesc)
+#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN(txdesc)
+#define SET_TX_DESC_BUFFER_MHR_CP_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_MHR_CP(txdesc, value)
+#define GET_TX_DESC_BUFFER_MHR_CP_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_MHR_CP(txdesc)
+#define SET_TX_DESC_BUFFER_SMH_EN_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_SMH_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_SMH_EN_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_SMH_EN(txdesc)
+#define SET_TX_DESC_BUFFER_RTSRATE_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_RTSRATE(txdesc, value)
+#define GET_TX_DESC_BUFFER_RTSRATE_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_RTSRATE(txdesc)
+#define SET_TX_DESC_BUFFER_SMH_CAM_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_SMH_CAM(txdesc, value)
+#define GET_TX_DESC_BUFFER_SMH_CAM_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_SMH_CAM(txdesc)
+#define SET_TX_DESC_BUFFER_ARFR_TABLE_SEL_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_ARFR_TABLE_SEL(txdesc, value)
+#define GET_TX_DESC_BUFFER_ARFR_TABLE_SEL_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_ARFR_TABLE_SEL(txdesc)
+#define SET_TX_DESC_BUFFER_ARFR_HT_EN_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_ARFR_HT_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_ARFR_HT_EN_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_ARFR_HT_EN(txdesc)
+#define SET_TX_DESC_BUFFER_ARFR_OFDM_EN_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_ARFR_OFDM_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_ARFR_OFDM_EN_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_ARFR_OFDM_EN(txdesc)
+#define SET_TX_DESC_BUFFER_ARFR_CCK_EN_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_ARFR_CCK_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_ARFR_CCK_EN_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_ARFR_CCK_EN(txdesc)
+#define SET_TX_DESC_BUFFER_RTS_SHORT_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_RTS_SHORT(txdesc, value)
+#define GET_TX_DESC_BUFFER_RTS_SHORT_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_RTS_SHORT(txdesc)
+#define SET_TX_DESC_BUFFER_DISDATAFB_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_DISDATAFB(txdesc, value)
+#define GET_TX_DESC_BUFFER_DISDATAFB_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_DISDATAFB(txdesc)
+#define SET_TX_DESC_BUFFER_DISRTSFB_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_DISRTSFB(txdesc, value)
+#define GET_TX_DESC_BUFFER_DISRTSFB_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_DISRTSFB(txdesc)
+#define SET_TX_DESC_BUFFER_EXT_EDCA_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_EXT_EDCA(txdesc, value)
+#define GET_TX_DESC_BUFFER_EXT_EDCA_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_EXT_EDCA(txdesc)
+
+/*TXDESC_WORD10*/
+
+#define SET_TX_DESC_BUFFER_AMPDU_MAX_TIME_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_AMPDU_MAX_TIME(txdesc, value)
+#define GET_TX_DESC_BUFFER_AMPDU_MAX_TIME_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_AMPDU_MAX_TIME(txdesc)
+#define SET_TX_DESC_BUFFER_SPECIAL_CW_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_SPECIAL_CW(txdesc, value)
+#define GET_TX_DESC_BUFFER_SPECIAL_CW_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_SPECIAL_CW(txdesc)
+#define SET_TX_DESC_BUFFER_RDG_NAV_EXT_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_RDG_NAV_EXT(txdesc, value)
+#define GET_TX_DESC_BUFFER_RDG_NAV_EXT_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_RDG_NAV_EXT(txdesc)
+#define SET_TX_DESC_BUFFER_RAW_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_RAW(txdesc, value)
+#define GET_TX_DESC_BUFFER_RAW_8814B(txdesc) GET_TX_DESC_BUFFER_RAW(txdesc)
+#define SET_TX_DESC_BUFFER_MAX_AGG_NUM_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_MAX_AGG_NUM(txdesc, value)
+#define GET_TX_DESC_BUFFER_MAX_AGG_NUM_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_MAX_AGG_NUM(txdesc)
+#define SET_TX_DESC_BUFFER_FINAL_DATA_RATE_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_FINAL_DATA_RATE(txdesc, value)
+#define GET_TX_DESC_BUFFER_FINAL_DATA_RATE_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_FINAL_DATA_RATE(txdesc)
+#define SET_TX_DESC_BUFFER_GF_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_GF(txdesc, value)
+#define GET_TX_DESC_BUFFER_GF_8814B(txdesc) GET_TX_DESC_BUFFER_GF(txdesc)
+#define SET_TX_DESC_BUFFER_MOREFRAG_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_MOREFRAG(txdesc, value)
+#define GET_TX_DESC_BUFFER_MOREFRAG_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_MOREFRAG(txdesc)
+#define SET_TX_DESC_BUFFER_NOACM_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_NOACM(txdesc, value)
+#define GET_TX_DESC_BUFFER_NOACM_8814B(txdesc) GET_TX_DESC_BUFFER_NOACM(txdesc)
+#define SET_TX_DESC_BUFFER_HTC_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_HTC(txdesc, value)
+#define GET_TX_DESC_BUFFER_HTC_8814B(txdesc) GET_TX_DESC_BUFFER_HTC(txdesc)
+#define SET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS(txdesc, value)
+#define GET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS(txdesc)
+#define SET_TX_DESC_BUFFER_USE_MAX_TIME_EN_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_USE_MAX_TIME_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_USE_MAX_TIME_EN_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_USE_MAX_TIME_EN(txdesc)
+#define SET_TX_DESC_BUFFER_HW_SSN_SEL_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_HW_SSN_SEL(txdesc, value)
+#define GET_TX_DESC_BUFFER_HW_SSN_SEL_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_HW_SSN_SEL(txdesc)
+
+/*TXDESC_WORD11*/
+
+#define SET_TX_DESC_BUFFER_ADDR_CAM_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_ADDR_CAM(txdesc, value)
+#define GET_TX_DESC_BUFFER_ADDR_CAM_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_ADDR_CAM(txdesc)
+#define SET_TX_DESC_BUFFER_SND_TARGET_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_SND_TARGET(txdesc, value)
+#define GET_TX_DESC_BUFFER_SND_TARGET_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_SND_TARGET(txdesc)
+#define SET_TX_DESC_BUFFER_DATA_LDPC_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_DATA_LDPC(txdesc, value)
+#define GET_TX_DESC_BUFFER_DATA_LDPC_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_DATA_LDPC(txdesc)
+#define SET_TX_DESC_BUFFER_LSIG_TXOP_EN_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_LSIG_TXOP_EN(txdesc, value)
+#define GET_TX_DESC_BUFFER_LSIG_TXOP_EN_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_LSIG_TXOP_EN(txdesc)
+#define SET_TX_DESC_BUFFER_G_ID_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_G_ID(txdesc, value)
+#define GET_TX_DESC_BUFFER_G_ID_8814B(txdesc) GET_TX_DESC_BUFFER_G_ID(txdesc)
+#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC(txdesc, value)
+#define GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC(txdesc)
+#define SET_TX_DESC_BUFFER_DATA_SC_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_DATA_SC(txdesc, value)
+#define GET_TX_DESC_BUFFER_DATA_SC_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_DATA_SC(txdesc)
+
+/*TXDESC_WORD12*/
+
+#define SET_TX_DESC_BUFFER_LEN1_L_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_LEN1_L(txdesc, value)
+#define GET_TX_DESC_BUFFER_LEN1_L_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_LEN1_L(txdesc)
+#define SET_TX_DESC_BUFFER_LEN0_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_LEN0(txdesc, value)
+#define GET_TX_DESC_BUFFER_LEN0_8814B(txdesc) GET_TX_DESC_BUFFER_LEN0(txdesc)
+#define SET_TX_DESC_BUFFER_PKT_NUM_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_PKT_NUM(txdesc, value)
+#define GET_TX_DESC_BUFFER_PKT_NUM_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_PKT_NUM(txdesc)
+
+/*TXDESC_WORD13*/
+
+#define SET_TX_DESC_BUFFER_LEN3_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_LEN3(txdesc, value)
+#define GET_TX_DESC_BUFFER_LEN3_8814B(txdesc) GET_TX_DESC_BUFFER_LEN3(txdesc)
+#define SET_TX_DESC_BUFFER_LEN2_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_LEN2(txdesc, value)
+#define GET_TX_DESC_BUFFER_LEN2_8814B(txdesc) GET_TX_DESC_BUFFER_LEN2(txdesc)
+#define SET_TX_DESC_BUFFER_LEN1_H_8814B(txdesc, value) \
+ SET_TX_DESC_BUFFER_LEN1_H(txdesc, value)
+#define GET_TX_DESC_BUFFER_LEN1_H_8814B(txdesc) \
+ GET_TX_DESC_BUFFER_LEN1_H(txdesc)
+
+#endif
+
+#endif
diff --git a/hal/halmac/halmac_tx_desc_buffer_nic.h b/hal/halmac/halmac_tx_desc_buffer_nic.h
new file mode 100644
index 0000000..6274102
--- /dev/null
+++ b/hal/halmac/halmac_tx_desc_buffer_nic.h
@@ -0,0 +1,491 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_TX_DESC_BUFFER_NIC_H_
+#define _HALMAC_TX_DESC_BUFFER_NIC_H_
+#if (HALMAC_8814B_SUPPORT)
+
+/*TXDESC_WORD0*/
+
+#define SET_TX_DESC_BUFFER_RDG_EN(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 31, 1, value)
+#define GET_TX_DESC_BUFFER_RDG_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 31, 1)
+#define SET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 30, 1, value)
+#define GET_TX_DESC_BUFFER_BCNPKT_TSF_CTRL(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x00, 30, 1)
+#define SET_TX_DESC_BUFFER_AGG_EN(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 29, 1, value)
+#define GET_TX_DESC_BUFFER_AGG_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 29, 1)
+#define SET_TX_DESC_BUFFER_PKT_OFFSET(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 24, 5, value)
+#define GET_TX_DESC_BUFFER_PKT_OFFSET(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x00, 24, 5)
+#define SET_TX_DESC_BUFFER_OFFSET(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 16, 8, value)
+#define GET_TX_DESC_BUFFER_OFFSET(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 16, 8)
+#define SET_TX_DESC_BUFFER_TXPKTSIZE(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 0, 16, value)
+#define GET_TX_DESC_BUFFER_TXPKTSIZE(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x00, 0, 16)
+
+/*TXDESC_WORD1*/
+
+#define SET_TX_DESC_BUFFER_USERATE(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 31, 1, value)
+#define GET_TX_DESC_BUFFER_USERATE(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x04, 31, 1)
+#define SET_TX_DESC_BUFFER_AMSDU(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 30, 1, value)
+#define GET_TX_DESC_BUFFER_AMSDU(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 30, 1)
+#define SET_TX_DESC_BUFFER_EN_HWSEQ(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 29, 1, value)
+#define GET_TX_DESC_BUFFER_EN_HWSEQ(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x04, 29, 1)
+#define SET_TX_DESC_BUFFER_EN_HWEXSEQ(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 28, 1, value)
+#define GET_TX_DESC_BUFFER_EN_HWEXSEQ(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x04, 28, 1)
+#define SET_TX_DESC_BUFFER_SW_SEQ(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 16, 12, value)
+#define GET_TX_DESC_BUFFER_SW_SEQ(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x04, 16, 12)
+#define SET_TX_DESC_BUFFER_DROP_ID(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 14, 2, value)
+#define GET_TX_DESC_BUFFER_DROP_ID(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x04, 14, 2)
+#define SET_TX_DESC_BUFFER_MOREDATA(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 13, 1, value)
+#define GET_TX_DESC_BUFFER_MOREDATA(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x04, 13, 1)
+#define SET_TX_DESC_BUFFER_QSEL(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 8, 5, value)
+#define GET_TX_DESC_BUFFER_QSEL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 8, 5)
+#define SET_TX_DESC_BUFFER_MACID(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 0, 8, value)
+#define GET_TX_DESC_BUFFER_MACID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 0, 8)
+
+/*TXDESC_WORD2*/
+
+#define SET_TX_DESC_BUFFER_CHK_EN(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 31, 1, value)
+#define GET_TX_DESC_BUFFER_CHK_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 31, 1)
+#define SET_TX_DESC_BUFFER_DISQSELSEQ(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 30, 1, value)
+#define GET_TX_DESC_BUFFER_DISQSELSEQ(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x08, 30, 1)
+#define SET_TX_DESC_BUFFER_SND_PKT_SEL(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 28, 2, value)
+#define GET_TX_DESC_BUFFER_SND_PKT_SEL(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x08, 28, 2)
+#define SET_TX_DESC_BUFFER_DMA_PRI(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 27, 1, value)
+#define GET_TX_DESC_BUFFER_DMA_PRI(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x08, 27, 1)
+#define SET_TX_DESC_BUFFER_MAX_AMSDU_MODE(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 24, 3, value)
+#define GET_TX_DESC_BUFFER_MAX_AMSDU_MODE(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x08, 24, 3)
+#define SET_TX_DESC_BUFFER_DMA_TXAGG_NUM(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 16, 8, value)
+#define GET_TX_DESC_BUFFER_DMA_TXAGG_NUM(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x08, 16, 8)
+#define SET_TX_DESC_BUFFER_TXDESC_CHECKSUM(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 0, 16, value)
+#define GET_TX_DESC_BUFFER_TXDESC_CHECKSUM(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x08, 0, 16)
+
+/*TXDESC_WORD3*/
+
+#define SET_TX_DESC_BUFFER_OFFLOAD_SIZE(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 16, 15, value)
+#define GET_TX_DESC_BUFFER_OFFLOAD_SIZE(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x0C, 16, 15)
+#define SET_TX_DESC_BUFFER_CHANNEL_DMA(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 11, 5, value)
+#define GET_TX_DESC_BUFFER_CHANNEL_DMA(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x0C, 11, 5)
+#define SET_TX_DESC_BUFFER_MBSSID(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 7, 4, value)
+#define GET_TX_DESC_BUFFER_MBSSID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 7, 4)
+#define SET_TX_DESC_BUFFER_BK(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 6, 1, value)
+#define GET_TX_DESC_BUFFER_BK(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 6, 1)
+#define SET_TX_DESC_BUFFER_WHEADER_LEN(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 0, 5, value)
+#define GET_TX_DESC_BUFFER_WHEADER_LEN(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x0C, 0, 5)
+
+/*TXDESC_WORD4*/
+
+#define SET_TX_DESC_BUFFER_TRY_RATE(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 26, 1, value)
+#define GET_TX_DESC_BUFFER_TRY_RATE(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x10, 26, 1)
+#define SET_TX_DESC_BUFFER_DATA_BW(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 24, 2, value)
+#define GET_TX_DESC_BUFFER_DATA_BW(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x10, 24, 2)
+#define SET_TX_DESC_BUFFER_DATA_SHORT(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 23, 1, value)
+#define GET_TX_DESC_BUFFER_DATA_SHORT(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x10, 23, 1)
+#define SET_TX_DESC_BUFFER_DATARATE(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 16, 7, value)
+#define GET_TX_DESC_BUFFER_DATARATE(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x10, 16, 7)
+#define SET_TX_DESC_BUFFER_TXBF_PATH(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 11, 1, value)
+#define GET_TX_DESC_BUFFER_TXBF_PATH(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x10, 11, 1)
+#define SET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 0, 11, value)
+#define GET_TX_DESC_BUFFER_GROUP_BIT_IE_OFFSET(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x10, 0, 11)
+
+/*TXDESC_WORD5*/
+
+#define SET_TX_DESC_BUFFER_RTY_LMT_EN(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 31, 1, value)
+#define GET_TX_DESC_BUFFER_RTY_LMT_EN(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x14, 31, 1)
+#define SET_TX_DESC_BUFFER_HW_RTS_EN(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 30, 1, value)
+#define GET_TX_DESC_BUFFER_HW_RTS_EN(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x14, 30, 1)
+#define SET_TX_DESC_BUFFER_RTS_EN(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 29, 1, value)
+#define GET_TX_DESC_BUFFER_RTS_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 29, 1)
+#define SET_TX_DESC_BUFFER_CTS2SELF(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 28, 1, value)
+#define GET_TX_DESC_BUFFER_CTS2SELF(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x14, 28, 1)
+#define SET_TX_DESC_BUFFER_TAILPAGE_H(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 24, 4, value)
+#define GET_TX_DESC_BUFFER_TAILPAGE_H(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x14, 24, 4)
+#define SET_TX_DESC_BUFFER_TAILPAGE_L(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 16, 8, value)
+#define GET_TX_DESC_BUFFER_TAILPAGE_L(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x14, 16, 8)
+#define SET_TX_DESC_BUFFER_NAVUSEHDR(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 15, 1, value)
+#define GET_TX_DESC_BUFFER_NAVUSEHDR(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x14, 15, 1)
+#define SET_TX_DESC_BUFFER_BMC(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 14, 1, value)
+#define GET_TX_DESC_BUFFER_BMC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 14, 1)
+#define SET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 8, 6, value)
+#define GET_TX_DESC_BUFFER_RTS_DATA_RTY_LMT(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x14, 8, 6)
+#define SET_TX_DESC_BUFFER_HW_AES_IV(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 7, 1, value)
+#define GET_TX_DESC_BUFFER_HW_AES_IV(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x14, 7, 1)
+#define SET_TX_DESC_BUFFER_BT_NULL(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 3, 1, value)
+#define GET_TX_DESC_BUFFER_BT_NULL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 3, 1)
+#define SET_TX_DESC_BUFFER_EN_DESC_ID(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 2, 1, value)
+#define GET_TX_DESC_BUFFER_EN_DESC_ID(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x14, 2, 1)
+#define SET_TX_DESC_BUFFER_SECTYPE(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 0, 2, value)
+#define GET_TX_DESC_BUFFER_SECTYPE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 0, 2)
+
+/*TXDESC_WORD6*/
+
+#define SET_TX_DESC_BUFFER_MULTIPLE_PORT(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 29, 3, value)
+#define GET_TX_DESC_BUFFER_MULTIPLE_PORT(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x18, 29, 3)
+#define SET_TX_DESC_BUFFER_POLLUTED(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 28, 1, value)
+#define GET_TX_DESC_BUFFER_POLLUTED(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x18, 28, 1)
+#define SET_TX_DESC_BUFFER_NULL_1(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 27, 1, value)
+#define GET_TX_DESC_BUFFER_NULL_1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 27, 1)
+#define SET_TX_DESC_BUFFER_NULL_0(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 26, 1, value)
+#define GET_TX_DESC_BUFFER_NULL_0(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 26, 1)
+#define SET_TX_DESC_BUFFER_TRI_FRAME(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 25, 1, value)
+#define GET_TX_DESC_BUFFER_TRI_FRAME(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x18, 25, 1)
+#define SET_TX_DESC_BUFFER_SPE_RPT(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 24, 1, value)
+#define GET_TX_DESC_BUFFER_SPE_RPT(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x18, 24, 1)
+#define SET_TX_DESC_BUFFER_FTM_EN(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 23, 1, value)
+#define GET_TX_DESC_BUFFER_FTM_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 23, 1)
+#define SET_TX_DESC_BUFFER_MU_DATARATE(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 16, 7, value)
+#define GET_TX_DESC_BUFFER_MU_DATARATE(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x18, 16, 7)
+#define SET_TX_DESC_BUFFER_CCA_RTS(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 14, 2, value)
+#define GET_TX_DESC_BUFFER_CCA_RTS(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x18, 14, 2)
+#define SET_TX_DESC_BUFFER_NDPA(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 12, 2, value)
+#define GET_TX_DESC_BUFFER_NDPA(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 12, 2)
+#define SET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 9, 2, value)
+#define GET_TX_DESC_BUFFER_TXPWR_OFSET_TYPE(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x18, 9, 2)
+#define SET_TX_DESC_BUFFER_P_AID(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 0, 9, value)
+#define GET_TX_DESC_BUFFER_P_AID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 0, 9)
+
+/*TXDESC_WORD7*/
+
+#define SET_TX_DESC_BUFFER_SW_DEFINE(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 16, 12, value)
+#define GET_TX_DESC_BUFFER_SW_DEFINE(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x1C, 16, 12)
+#define SET_TX_DESC_BUFFER_CTRL_CNT_VALID(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 9, 1, value)
+#define GET_TX_DESC_BUFFER_CTRL_CNT_VALID(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x1C, 9, 1)
+#define SET_TX_DESC_BUFFER_CTRL_CNT(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 5, 4, value)
+#define GET_TX_DESC_BUFFER_CTRL_CNT(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x1C, 5, 4)
+#define SET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 0, 5, value)
+#define GET_TX_DESC_BUFFER_DATA_RTY_LOWEST_RATE(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x1C, 0, 5)
+
+/*TXDESC_WORD8*/
+
+#define SET_TX_DESC_BUFFER_PATH_MAPA(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 30, 2, value)
+#define GET_TX_DESC_BUFFER_PATH_MAPA(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x20, 30, 2)
+#define SET_TX_DESC_BUFFER_PATH_MAPB(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 28, 2, value)
+#define GET_TX_DESC_BUFFER_PATH_MAPB(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x20, 28, 2)
+#define SET_TX_DESC_BUFFER_PATH_MAPC(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 26, 2, value)
+#define GET_TX_DESC_BUFFER_PATH_MAPC(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x20, 26, 2)
+#define SET_TX_DESC_BUFFER_PATH_MAPD(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 24, 2, value)
+#define GET_TX_DESC_BUFFER_PATH_MAPD(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x20, 24, 2)
+#define SET_TX_DESC_BUFFER_ANTSEL_A(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 20, 4, value)
+#define GET_TX_DESC_BUFFER_ANTSEL_A(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x20, 20, 4)
+#define SET_TX_DESC_BUFFER_ANTSEL_B(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 16, 4, value)
+#define GET_TX_DESC_BUFFER_ANTSEL_B(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x20, 16, 4)
+#define SET_TX_DESC_BUFFER_ANTSEL_C(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 12, 4, value)
+#define GET_TX_DESC_BUFFER_ANTSEL_C(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x20, 12, 4)
+#define SET_TX_DESC_BUFFER_ANTSEL_D(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 8, 4, value)
+#define GET_TX_DESC_BUFFER_ANTSEL_D(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x20, 8, 4)
+#define SET_TX_DESC_BUFFER_NTX_PATH_EN(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 4, 4, value)
+#define GET_TX_DESC_BUFFER_NTX_PATH_EN(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x20, 4, 4)
+#define SET_TX_DESC_BUFFER_ANTLSEL_EN(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 3, 1, value)
+#define GET_TX_DESC_BUFFER_ANTLSEL_EN(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x20, 3, 1)
+#define SET_TX_DESC_BUFFER_AMPDU_DENSITY(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 0, 3, value)
+#define GET_TX_DESC_BUFFER_AMPDU_DENSITY(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x20, 0, 3)
+
+/*TXDESC_WORD9*/
+
+#define SET_TX_DESC_BUFFER_VCS_STBC(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 30, 2, value)
+#define GET_TX_DESC_BUFFER_VCS_STBC(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x24, 30, 2)
+#define SET_TX_DESC_BUFFER_DATA_STBC(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 28, 2, value)
+#define GET_TX_DESC_BUFFER_DATA_STBC(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x24, 28, 2)
+#define SET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 24, 4, value)
+#define GET_TX_DESC_BUFFER_RTS_RTY_LOWEST_RATE(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x24, 24, 4)
+#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 23, 1, value)
+#define GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_EN(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x24, 23, 1)
+#define SET_TX_DESC_BUFFER_MHR_CP(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 22, 1, value)
+#define GET_TX_DESC_BUFFER_MHR_CP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 22, 1)
+#define SET_TX_DESC_BUFFER_SMH_EN(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 21, 1, value)
+#define GET_TX_DESC_BUFFER_SMH_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 21, 1)
+#define SET_TX_DESC_BUFFER_RTSRATE(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 16, 5, value)
+#define GET_TX_DESC_BUFFER_RTSRATE(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x24, 16, 5)
+#define SET_TX_DESC_BUFFER_SMH_CAM(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 8, 8, value)
+#define GET_TX_DESC_BUFFER_SMH_CAM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 8, 8)
+#define SET_TX_DESC_BUFFER_ARFR_TABLE_SEL(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 7, 1, value)
+#define GET_TX_DESC_BUFFER_ARFR_TABLE_SEL(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x24, 7, 1)
+#define SET_TX_DESC_BUFFER_ARFR_HT_EN(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 6, 1, value)
+#define GET_TX_DESC_BUFFER_ARFR_HT_EN(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x24, 6, 1)
+#define SET_TX_DESC_BUFFER_ARFR_OFDM_EN(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 5, 1, value)
+#define GET_TX_DESC_BUFFER_ARFR_OFDM_EN(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x24, 5, 1)
+#define SET_TX_DESC_BUFFER_ARFR_CCK_EN(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 4, 1, value)
+#define GET_TX_DESC_BUFFER_ARFR_CCK_EN(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x24, 4, 1)
+#define SET_TX_DESC_BUFFER_RTS_SHORT(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 3, 1, value)
+#define GET_TX_DESC_BUFFER_RTS_SHORT(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x24, 3, 1)
+#define SET_TX_DESC_BUFFER_DISDATAFB(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 2, 1, value)
+#define GET_TX_DESC_BUFFER_DISDATAFB(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x24, 2, 1)
+#define SET_TX_DESC_BUFFER_DISRTSFB(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 1, 1, value)
+#define GET_TX_DESC_BUFFER_DISRTSFB(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x24, 1, 1)
+#define SET_TX_DESC_BUFFER_EXT_EDCA(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 0, 1, value)
+#define GET_TX_DESC_BUFFER_EXT_EDCA(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x24, 0, 1)
+
+/*TXDESC_WORD10*/
+
+#define SET_TX_DESC_BUFFER_AMPDU_MAX_TIME(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 24, 8, value)
+#define GET_TX_DESC_BUFFER_AMPDU_MAX_TIME(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x28, 24, 8)
+#define SET_TX_DESC_BUFFER_SPECIAL_CW(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 23, 1, value)
+#define GET_TX_DESC_BUFFER_SPECIAL_CW(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x28, 23, 1)
+#define SET_TX_DESC_BUFFER_RDG_NAV_EXT(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 22, 1, value)
+#define GET_TX_DESC_BUFFER_RDG_NAV_EXT(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x28, 22, 1)
+#define SET_TX_DESC_BUFFER_RAW(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 21, 1, value)
+#define GET_TX_DESC_BUFFER_RAW(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 21, 1)
+#define SET_TX_DESC_BUFFER_MAX_AGG_NUM(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 16, 5, value)
+#define GET_TX_DESC_BUFFER_MAX_AGG_NUM(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x28, 16, 5)
+#define SET_TX_DESC_BUFFER_FINAL_DATA_RATE(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 8, 8, value)
+#define GET_TX_DESC_BUFFER_FINAL_DATA_RATE(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x28, 8, 8)
+#define SET_TX_DESC_BUFFER_GF(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 7, 1, value)
+#define GET_TX_DESC_BUFFER_GF(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 7, 1)
+#define SET_TX_DESC_BUFFER_MOREFRAG(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 6, 1, value)
+#define GET_TX_DESC_BUFFER_MOREFRAG(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x28, 6, 1)
+#define SET_TX_DESC_BUFFER_NOACM(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 5, 1, value)
+#define GET_TX_DESC_BUFFER_NOACM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 5, 1)
+#define SET_TX_DESC_BUFFER_HTC(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 4, 1, value)
+#define GET_TX_DESC_BUFFER_HTC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 4, 1)
+#define SET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 3, 1, value)
+#define GET_TX_DESC_BUFFER_TX_PKT_AFTER_PIFS(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x28, 3, 1)
+#define SET_TX_DESC_BUFFER_USE_MAX_TIME_EN(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 2, 1, value)
+#define GET_TX_DESC_BUFFER_USE_MAX_TIME_EN(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x28, 2, 1)
+#define SET_TX_DESC_BUFFER_HW_SSN_SEL(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 0, 2, value)
+#define GET_TX_DESC_BUFFER_HW_SSN_SEL(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x28, 0, 2)
+
+/*TXDESC_WORD11*/
+
+#define SET_TX_DESC_BUFFER_ADDR_CAM(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 24, 8, value)
+#define GET_TX_DESC_BUFFER_ADDR_CAM(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x2C, 24, 8)
+#define SET_TX_DESC_BUFFER_SND_TARGET(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 16, 8, value)
+#define GET_TX_DESC_BUFFER_SND_TARGET(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x2C, 16, 8)
+#define SET_TX_DESC_BUFFER_DATA_LDPC(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 15, 1, value)
+#define GET_TX_DESC_BUFFER_DATA_LDPC(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x2C, 15, 1)
+#define SET_TX_DESC_BUFFER_LSIG_TXOP_EN(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 14, 1, value)
+#define GET_TX_DESC_BUFFER_LSIG_TXOP_EN(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x2C, 14, 1)
+#define SET_TX_DESC_BUFFER_G_ID(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 8, 6, value)
+#define GET_TX_DESC_BUFFER_G_ID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x2C, 8, 6)
+#define SET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 4, 4, value)
+#define GET_TX_DESC_BUFFER_SIGNALING_TA_PKT_SC(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x2C, 4, 4)
+#define SET_TX_DESC_BUFFER_DATA_SC(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x2C, 0, 4, value)
+#define GET_TX_DESC_BUFFER_DATA_SC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x2C, 0, 4)
+
+/*TXDESC_WORD12*/
+
+#define SET_TX_DESC_BUFFER_LEN1_L(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x30, 17, 7, value)
+#define GET_TX_DESC_BUFFER_LEN1_L(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x30, 17, 7)
+#define SET_TX_DESC_BUFFER_LEN0(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x30, 4, 13, value)
+#define GET_TX_DESC_BUFFER_LEN0(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x30, 4, 13)
+#define SET_TX_DESC_BUFFER_PKT_NUM(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x30, 0, 4, value)
+#define GET_TX_DESC_BUFFER_PKT_NUM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x30, 0, 4)
+
+/*TXDESC_WORD13*/
+
+#define SET_TX_DESC_BUFFER_LEN3(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x34, 19, 13, value)
+#define GET_TX_DESC_BUFFER_LEN3(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x34, 19, 13)
+#define SET_TX_DESC_BUFFER_LEN2(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x34, 6, 13, value)
+#define GET_TX_DESC_BUFFER_LEN2(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x34, 6, 13)
+#define SET_TX_DESC_BUFFER_LEN1_H(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x34, 0, 6, value)
+#define GET_TX_DESC_BUFFER_LEN1_H(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x34, 0, 6)
+
+#endif
+
+#endif
diff --git a/hal/halmac/halmac_tx_desc_chip.h b/hal/halmac/halmac_tx_desc_chip.h
index d15b6cf..514b187 100644
--- a/hal/halmac/halmac_tx_desc_chip.h
+++ b/hal/halmac/halmac_tx_desc_chip.h
@@ -1,518 +1,759 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
#ifndef _HALMAC_TX_DESC_CHIP_H_
#define _HALMAC_TX_DESC_CHIP_H_
#if (HALMAC_8814A_SUPPORT)
/*TXDESC_WORD0*/
-#define SET_TX_DESC_DISQSELSEQ_8814A(__pTxDesc, __Value) SET_TX_DESC_DISQSELSEQ(__pTxDesc, __Value)
-#define GET_TX_DESC_DISQSELSEQ_8814A(__pTxDesc) GET_TX_DESC_DISQSELSEQ(__pTxDesc)
-#define SET_TX_DESC_GF_8814A(__pTxDesc, __Value) SET_TX_DESC_GF(__pTxDesc, __Value)
-#define GET_TX_DESC_GF_8814A(__pTxDesc) GET_TX_DESC_GF(__pTxDesc)
-#define SET_TX_DESC_NO_ACM_8814A(__pTxDesc, __Value) SET_TX_DESC_NO_ACM(__pTxDesc, __Value)
-#define GET_TX_DESC_NO_ACM_8814A(__pTxDesc) GET_TX_DESC_NO_ACM(__pTxDesc)
-#define SET_TX_DESC_AMSDU_PAD_EN_8814A(__pTxDesc, __Value) SET_TX_DESC_AMSDU_PAD_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_AMSDU_PAD_EN_8814A(__pTxDesc) GET_TX_DESC_AMSDU_PAD_EN(__pTxDesc)
-#define SET_TX_DESC_LS_8814A(__pTxDesc, __Value) SET_TX_DESC_LS(__pTxDesc, __Value)
-#define GET_TX_DESC_LS_8814A(__pTxDesc) GET_TX_DESC_LS(__pTxDesc)
-#define SET_TX_DESC_HTC_8814A(__pTxDesc, __Value) SET_TX_DESC_HTC(__pTxDesc, __Value)
-#define GET_TX_DESC_HTC_8814A(__pTxDesc) GET_TX_DESC_HTC(__pTxDesc)
-#define SET_TX_DESC_BMC_8814A(__pTxDesc, __Value) SET_TX_DESC_BMC(__pTxDesc, __Value)
-#define GET_TX_DESC_BMC_8814A(__pTxDesc) GET_TX_DESC_BMC(__pTxDesc)
-#define SET_TX_DESC_OFFSET_8814A(__pTxDesc, __Value) SET_TX_DESC_OFFSET(__pTxDesc, __Value)
-#define GET_TX_DESC_OFFSET_8814A(__pTxDesc) GET_TX_DESC_OFFSET(__pTxDesc)
-#define SET_TX_DESC_TXPKTSIZE_8814A(__pTxDesc, __Value) SET_TX_DESC_TXPKTSIZE(__pTxDesc, __Value)
-#define GET_TX_DESC_TXPKTSIZE_8814A(__pTxDesc) GET_TX_DESC_TXPKTSIZE(__pTxDesc)
-
-/*TXDESC_WORD1*/
-
-#define SET_TX_DESC_MOREDATA_8814A(__pTxDesc, __Value) SET_TX_DESC_MOREDATA(__pTxDesc, __Value)
-#define GET_TX_DESC_MOREDATA_8814A(__pTxDesc) GET_TX_DESC_MOREDATA(__pTxDesc)
-#define SET_TX_DESC_PKT_OFFSET_8814A(__pTxDesc, __Value) SET_TX_DESC_PKT_OFFSET(__pTxDesc, __Value)
-#define GET_TX_DESC_PKT_OFFSET_8814A(__pTxDesc) GET_TX_DESC_PKT_OFFSET(__pTxDesc)
-#define SET_TX_DESC_SEC_TYPE_8814A(__pTxDesc, __Value) SET_TX_DESC_SEC_TYPE(__pTxDesc, __Value)
-#define GET_TX_DESC_SEC_TYPE_8814A(__pTxDesc) GET_TX_DESC_SEC_TYPE(__pTxDesc)
-#define SET_TX_DESC_EN_DESC_ID_8814A(__pTxDesc, __Value) SET_TX_DESC_EN_DESC_ID(__pTxDesc, __Value)
-#define GET_TX_DESC_EN_DESC_ID_8814A(__pTxDesc) GET_TX_DESC_EN_DESC_ID(__pTxDesc)
-#define SET_TX_DESC_RATE_ID_8814A(__pTxDesc, __Value) SET_TX_DESC_RATE_ID(__pTxDesc, __Value)
-#define GET_TX_DESC_RATE_ID_8814A(__pTxDesc) GET_TX_DESC_RATE_ID(__pTxDesc)
-#define SET_TX_DESC_PIFS_8814A(__pTxDesc, __Value) SET_TX_DESC_PIFS(__pTxDesc, __Value)
-#define GET_TX_DESC_PIFS_8814A(__pTxDesc) GET_TX_DESC_PIFS(__pTxDesc)
-#define SET_TX_DESC_LSIG_TXOP_EN_8814A(__pTxDesc, __Value) SET_TX_DESC_LSIG_TXOP_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_LSIG_TXOP_EN_8814A(__pTxDesc) GET_TX_DESC_LSIG_TXOP_EN(__pTxDesc)
-#define SET_TX_DESC_RD_NAV_EXT_8814A(__pTxDesc, __Value) SET_TX_DESC_RD_NAV_EXT(__pTxDesc, __Value)
-#define GET_TX_DESC_RD_NAV_EXT_8814A(__pTxDesc) GET_TX_DESC_RD_NAV_EXT(__pTxDesc)
-#define SET_TX_DESC_QSEL_8814A(__pTxDesc, __Value) SET_TX_DESC_QSEL(__pTxDesc, __Value)
-#define GET_TX_DESC_QSEL_8814A(__pTxDesc) GET_TX_DESC_QSEL(__pTxDesc)
-#define SET_TX_DESC_MACID_8814A(__pTxDesc, __Value) SET_TX_DESC_MACID(__pTxDesc, __Value)
-#define GET_TX_DESC_MACID_8814A(__pTxDesc) GET_TX_DESC_MACID(__pTxDesc)
+#define SET_TX_DESC_DISQSELSEQ_8814A(txdesc, value) \
+ SET_TX_DESC_DISQSELSEQ(txdesc, value)
+#define GET_TX_DESC_DISQSELSEQ_8814A(txdesc) GET_TX_DESC_DISQSELSEQ(txdesc)
+#define SET_TX_DESC_GF_8814A(txdesc, value) SET_TX_DESC_GF(txdesc, value)
+#define GET_TX_DESC_GF_8814A(txdesc) GET_TX_DESC_GF(txdesc)
+#define SET_TX_DESC_NO_ACM_8814A(txdesc, value) \
+ SET_TX_DESC_NO_ACM(txdesc, value)
+#define GET_TX_DESC_NO_ACM_8814A(txdesc) GET_TX_DESC_NO_ACM(txdesc)
+#define SET_TX_DESC_AMSDU_PAD_EN_8814A(txdesc, value) \
+ SET_TX_DESC_AMSDU_PAD_EN(txdesc, value)
+#define GET_TX_DESC_AMSDU_PAD_EN_8814A(txdesc) GET_TX_DESC_AMSDU_PAD_EN(txdesc)
+#define SET_TX_DESC_LS_8814A(txdesc, value) SET_TX_DESC_LS(txdesc, value)
+#define GET_TX_DESC_LS_8814A(txdesc) GET_TX_DESC_LS(txdesc)
+#define SET_TX_DESC_HTC_8814A(txdesc, value) SET_TX_DESC_HTC(txdesc, value)
+#define GET_TX_DESC_HTC_8814A(txdesc) GET_TX_DESC_HTC(txdesc)
+#define SET_TX_DESC_BMC_8814A(txdesc, value) SET_TX_DESC_BMC(txdesc, value)
+#define GET_TX_DESC_BMC_8814A(txdesc) GET_TX_DESC_BMC(txdesc)
+#define SET_TX_DESC_OFFSET_8814A(txdesc, value) \
+ SET_TX_DESC_OFFSET(txdesc, value)
+#define GET_TX_DESC_OFFSET_8814A(txdesc) GET_TX_DESC_OFFSET(txdesc)
+#define SET_TX_DESC_TXPKTSIZE_8814A(txdesc, value) \
+ SET_TX_DESC_TXPKTSIZE(txdesc, value)
+#define GET_TX_DESC_TXPKTSIZE_8814A(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc)
+
+/*WORD1*/
+
+#define SET_TX_DESC_MOREDATA_8814A(txdesc, value) \
+ SET_TX_DESC_MOREDATA(txdesc, value)
+#define GET_TX_DESC_MOREDATA_8814A(txdesc) GET_TX_DESC_MOREDATA(txdesc)
+#define SET_TX_DESC_PKT_OFFSET_8814A(txdesc, value) \
+ SET_TX_DESC_PKT_OFFSET(txdesc, value)
+#define GET_TX_DESC_PKT_OFFSET_8814A(txdesc) GET_TX_DESC_PKT_OFFSET(txdesc)
+#define SET_TX_DESC_SEC_TYPE_8814A(txdesc, value) \
+ SET_TX_DESC_SEC_TYPE(txdesc, value)
+#define GET_TX_DESC_SEC_TYPE_8814A(txdesc) GET_TX_DESC_SEC_TYPE(txdesc)
+#define SET_TX_DESC_EN_DESC_ID_8814A(txdesc, value) \
+ SET_TX_DESC_EN_DESC_ID(txdesc, value)
+#define GET_TX_DESC_EN_DESC_ID_8814A(txdesc) GET_TX_DESC_EN_DESC_ID(txdesc)
+#define SET_TX_DESC_RATE_ID_8814A(txdesc, value) \
+ SET_TX_DESC_RATE_ID(txdesc, value)
+#define GET_TX_DESC_RATE_ID_8814A(txdesc) GET_TX_DESC_RATE_ID(txdesc)
+#define SET_TX_DESC_PIFS_8814A(txdesc, value) SET_TX_DESC_PIFS(txdesc, value)
+#define GET_TX_DESC_PIFS_8814A(txdesc) GET_TX_DESC_PIFS(txdesc)
+#define SET_TX_DESC_LSIG_TXOP_EN_8814A(txdesc, value) \
+ SET_TX_DESC_LSIG_TXOP_EN(txdesc, value)
+#define GET_TX_DESC_LSIG_TXOP_EN_8814A(txdesc) GET_TX_DESC_LSIG_TXOP_EN(txdesc)
+#define SET_TX_DESC_RD_NAV_EXT_8814A(txdesc, value) \
+ SET_TX_DESC_RD_NAV_EXT(txdesc, value)
+#define GET_TX_DESC_RD_NAV_EXT_8814A(txdesc) GET_TX_DESC_RD_NAV_EXT(txdesc)
+#define SET_TX_DESC_QSEL_8814A(txdesc, value) SET_TX_DESC_QSEL(txdesc, value)
+#define GET_TX_DESC_QSEL_8814A(txdesc) GET_TX_DESC_QSEL(txdesc)
+#define SET_TX_DESC_MACID_8814A(txdesc, value) SET_TX_DESC_MACID(txdesc, value)
+#define GET_TX_DESC_MACID_8814A(txdesc) GET_TX_DESC_MACID(txdesc)
/*TXDESC_WORD2*/
-#define SET_TX_DESC_HW_AES_IV_8814A(__pTxDesc, __Value) SET_TX_DESC_HW_AES_IV(__pTxDesc, __Value)
-#define GET_TX_DESC_HW_AES_IV_8814A(__pTxDesc) GET_TX_DESC_HW_AES_IV(__pTxDesc)
-#define SET_TX_DESC_G_ID_8814A(__pTxDesc, __Value) SET_TX_DESC_G_ID(__pTxDesc, __Value)
-#define GET_TX_DESC_G_ID_8814A(__pTxDesc) GET_TX_DESC_G_ID(__pTxDesc)
-#define SET_TX_DESC_BT_NULL_8814A(__pTxDesc, __Value) SET_TX_DESC_BT_NULL(__pTxDesc, __Value)
-#define GET_TX_DESC_BT_NULL_8814A(__pTxDesc) GET_TX_DESC_BT_NULL(__pTxDesc)
-#define SET_TX_DESC_AMPDU_DENSITY_8814A(__pTxDesc, __Value) SET_TX_DESC_AMPDU_DENSITY(__pTxDesc, __Value)
-#define GET_TX_DESC_AMPDU_DENSITY_8814A(__pTxDesc) GET_TX_DESC_AMPDU_DENSITY(__pTxDesc)
-#define SET_TX_DESC_SPE_RPT_8814A(__pTxDesc, __Value) SET_TX_DESC_SPE_RPT(__pTxDesc, __Value)
-#define GET_TX_DESC_SPE_RPT_8814A(__pTxDesc) GET_TX_DESC_SPE_RPT(__pTxDesc)
-#define SET_TX_DESC_RAW_8814A(__pTxDesc, __Value) SET_TX_DESC_RAW(__pTxDesc, __Value)
-#define GET_TX_DESC_RAW_8814A(__pTxDesc) GET_TX_DESC_RAW(__pTxDesc)
-#define SET_TX_DESC_MOREFRAG_8814A(__pTxDesc, __Value) SET_TX_DESC_MOREFRAG(__pTxDesc, __Value)
-#define GET_TX_DESC_MOREFRAG_8814A(__pTxDesc) GET_TX_DESC_MOREFRAG(__pTxDesc)
-#define SET_TX_DESC_BK_8814A(__pTxDesc, __Value) SET_TX_DESC_BK(__pTxDesc, __Value)
-#define GET_TX_DESC_BK_8814A(__pTxDesc) GET_TX_DESC_BK(__pTxDesc)
-#define SET_TX_DESC_NULL_1_8814A(__pTxDesc, __Value) SET_TX_DESC_NULL_1(__pTxDesc, __Value)
-#define GET_TX_DESC_NULL_1_8814A(__pTxDesc) GET_TX_DESC_NULL_1(__pTxDesc)
-#define SET_TX_DESC_NULL_0_8814A(__pTxDesc, __Value) SET_TX_DESC_NULL_0(__pTxDesc, __Value)
-#define GET_TX_DESC_NULL_0_8814A(__pTxDesc) GET_TX_DESC_NULL_0(__pTxDesc)
-#define SET_TX_DESC_RDG_EN_8814A(__pTxDesc, __Value) SET_TX_DESC_RDG_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_RDG_EN_8814A(__pTxDesc) GET_TX_DESC_RDG_EN(__pTxDesc)
-#define SET_TX_DESC_AGG_EN_8814A(__pTxDesc, __Value) SET_TX_DESC_AGG_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_AGG_EN_8814A(__pTxDesc) GET_TX_DESC_AGG_EN(__pTxDesc)
-#define SET_TX_DESC_CCA_RTS_8814A(__pTxDesc, __Value) SET_TX_DESC_CCA_RTS(__pTxDesc, __Value)
-#define GET_TX_DESC_CCA_RTS_8814A(__pTxDesc) GET_TX_DESC_CCA_RTS(__pTxDesc)
-#define SET_TX_DESC_P_AID_8814A(__pTxDesc, __Value) SET_TX_DESC_P_AID(__pTxDesc, __Value)
-#define GET_TX_DESC_P_AID_8814A(__pTxDesc) GET_TX_DESC_P_AID(__pTxDesc)
+#define SET_TX_DESC_HW_AES_IV_8814A(txdesc, value) \
+ SET_TX_DESC_HW_AES_IV(txdesc, value)
+#define GET_TX_DESC_HW_AES_IV_8814A(txdesc) GET_TX_DESC_HW_AES_IV(txdesc)
+#define SET_TX_DESC_G_ID_8814A(txdesc, value) SET_TX_DESC_G_ID(txdesc, value)
+#define GET_TX_DESC_G_ID_8814A(txdesc) GET_TX_DESC_G_ID(txdesc)
+#define SET_TX_DESC_BT_NULL_8814A(txdesc, value) \
+ SET_TX_DESC_BT_NULL(txdesc, value)
+#define GET_TX_DESC_BT_NULL_8814A(txdesc) GET_TX_DESC_BT_NULL(txdesc)
+#define SET_TX_DESC_AMPDU_DENSITY_8814A(txdesc, value) \
+ SET_TX_DESC_AMPDU_DENSITY(txdesc, value)
+#define GET_TX_DESC_AMPDU_DENSITY_8814A(txdesc) \
+ GET_TX_DESC_AMPDU_DENSITY(txdesc)
+#define SET_TX_DESC_SPE_RPT_8814A(txdesc, value) \
+ SET_TX_DESC_SPE_RPT(txdesc, value)
+#define GET_TX_DESC_SPE_RPT_8814A(txdesc) GET_TX_DESC_SPE_RPT(txdesc)
+#define SET_TX_DESC_RAW_8814A(txdesc, value) SET_TX_DESC_RAW(txdesc, value)
+#define GET_TX_DESC_RAW_8814A(txdesc) GET_TX_DESC_RAW(txdesc)
+#define SET_TX_DESC_MOREFRAG_8814A(txdesc, value) \
+ SET_TX_DESC_MOREFRAG(txdesc, value)
+#define GET_TX_DESC_MOREFRAG_8814A(txdesc) GET_TX_DESC_MOREFRAG(txdesc)
+#define SET_TX_DESC_BK_8814A(txdesc, value) SET_TX_DESC_BK(txdesc, value)
+#define GET_TX_DESC_BK_8814A(txdesc) GET_TX_DESC_BK(txdesc)
+#define SET_TX_DESC_NULL_1_8814A(txdesc, value) \
+ SET_TX_DESC_NULL_1(txdesc, value)
+#define GET_TX_DESC_NULL_1_8814A(txdesc) GET_TX_DESC_NULL_1(txdesc)
+#define SET_TX_DESC_NULL_0_8814A(txdesc, value) \
+ SET_TX_DESC_NULL_0(txdesc, value)
+#define GET_TX_DESC_NULL_0_8814A(txdesc) GET_TX_DESC_NULL_0(txdesc)
+#define SET_TX_DESC_RDG_EN_8814A(txdesc, value) \
+ SET_TX_DESC_RDG_EN(txdesc, value)
+#define GET_TX_DESC_RDG_EN_8814A(txdesc) GET_TX_DESC_RDG_EN(txdesc)
+#define SET_TX_DESC_AGG_EN_8814A(txdesc, value) \
+ SET_TX_DESC_AGG_EN(txdesc, value)
+#define GET_TX_DESC_AGG_EN_8814A(txdesc) GET_TX_DESC_AGG_EN(txdesc)
+#define SET_TX_DESC_CCA_RTS_8814A(txdesc, value) \
+ SET_TX_DESC_CCA_RTS(txdesc, value)
+#define GET_TX_DESC_CCA_RTS_8814A(txdesc) GET_TX_DESC_CCA_RTS(txdesc)
+#define SET_TX_DESC_P_AID_8814A(txdesc, value) SET_TX_DESC_P_AID(txdesc, value)
+#define GET_TX_DESC_P_AID_8814A(txdesc) GET_TX_DESC_P_AID(txdesc)
/*TXDESC_WORD3*/
-#define SET_TX_DESC_AMPDU_MAX_TIME_8814A(__pTxDesc, __Value) SET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc, __Value)
-#define GET_TX_DESC_AMPDU_MAX_TIME_8814A(__pTxDesc) GET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc)
-#define SET_TX_DESC_NDPA_8814A(__pTxDesc, __Value) SET_TX_DESC_NDPA(__pTxDesc, __Value)
-#define GET_TX_DESC_NDPA_8814A(__pTxDesc) GET_TX_DESC_NDPA(__pTxDesc)
-#define SET_TX_DESC_MAX_AGG_NUM_8814A(__pTxDesc, __Value) SET_TX_DESC_MAX_AGG_NUM(__pTxDesc, __Value)
-#define GET_TX_DESC_MAX_AGG_NUM_8814A(__pTxDesc) GET_TX_DESC_MAX_AGG_NUM(__pTxDesc)
-#define SET_TX_DESC_USE_MAX_TIME_EN_8814A(__pTxDesc, __Value) SET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_USE_MAX_TIME_EN_8814A(__pTxDesc) GET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc)
-#define SET_TX_DESC_NAVUSEHDR_8814A(__pTxDesc, __Value) SET_TX_DESC_NAVUSEHDR(__pTxDesc, __Value)
-#define GET_TX_DESC_NAVUSEHDR_8814A(__pTxDesc) GET_TX_DESC_NAVUSEHDR(__pTxDesc)
-#define SET_TX_DESC_CHK_EN_8814A(__pTxDesc, __Value) SET_TX_DESC_CHK_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_CHK_EN_8814A(__pTxDesc) GET_TX_DESC_CHK_EN(__pTxDesc)
-#define SET_TX_DESC_HW_RTS_EN_8814A(__pTxDesc, __Value) SET_TX_DESC_HW_RTS_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_HW_RTS_EN_8814A(__pTxDesc) GET_TX_DESC_HW_RTS_EN(__pTxDesc)
-#define SET_TX_DESC_RTSEN_8814A(__pTxDesc, __Value) SET_TX_DESC_RTSEN(__pTxDesc, __Value)
-#define GET_TX_DESC_RTSEN_8814A(__pTxDesc) GET_TX_DESC_RTSEN(__pTxDesc)
-#define SET_TX_DESC_CTS2SELF_8814A(__pTxDesc, __Value) SET_TX_DESC_CTS2SELF(__pTxDesc, __Value)
-#define GET_TX_DESC_CTS2SELF_8814A(__pTxDesc) GET_TX_DESC_CTS2SELF(__pTxDesc)
-#define SET_TX_DESC_DISDATAFB_8814A(__pTxDesc, __Value) SET_TX_DESC_DISDATAFB(__pTxDesc, __Value)
-#define GET_TX_DESC_DISDATAFB_8814A(__pTxDesc) GET_TX_DESC_DISDATAFB(__pTxDesc)
-#define SET_TX_DESC_DISRTSFB_8814A(__pTxDesc, __Value) SET_TX_DESC_DISRTSFB(__pTxDesc, __Value)
-#define GET_TX_DESC_DISRTSFB_8814A(__pTxDesc) GET_TX_DESC_DISRTSFB(__pTxDesc)
-#define SET_TX_DESC_USE_RATE_8814A(__pTxDesc, __Value) SET_TX_DESC_USE_RATE(__pTxDesc, __Value)
-#define GET_TX_DESC_USE_RATE_8814A(__pTxDesc) GET_TX_DESC_USE_RATE(__pTxDesc)
-#define SET_TX_DESC_HW_SSN_SEL_8814A(__pTxDesc, __Value) SET_TX_DESC_HW_SSN_SEL(__pTxDesc, __Value)
-#define GET_TX_DESC_HW_SSN_SEL_8814A(__pTxDesc) GET_TX_DESC_HW_SSN_SEL(__pTxDesc)
-#define SET_TX_DESC_WHEADER_LEN_8814A(__pTxDesc, __Value) SET_TX_DESC_WHEADER_LEN(__pTxDesc, __Value)
-#define GET_TX_DESC_WHEADER_LEN_8814A(__pTxDesc) GET_TX_DESC_WHEADER_LEN(__pTxDesc)
+#define SET_TX_DESC_AMPDU_MAX_TIME_8814A(txdesc, value) \
+ SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value)
+#define GET_TX_DESC_AMPDU_MAX_TIME_8814A(txdesc) \
+ GET_TX_DESC_AMPDU_MAX_TIME(txdesc)
+#define SET_TX_DESC_NDPA_8814A(txdesc, value) SET_TX_DESC_NDPA(txdesc, value)
+#define GET_TX_DESC_NDPA_8814A(txdesc) GET_TX_DESC_NDPA(txdesc)
+#define SET_TX_DESC_MAX_AGG_NUM_8814A(txdesc, value) \
+ SET_TX_DESC_MAX_AGG_NUM(txdesc, value)
+#define GET_TX_DESC_MAX_AGG_NUM_8814A(txdesc) GET_TX_DESC_MAX_AGG_NUM(txdesc)
+#define SET_TX_DESC_USE_MAX_TIME_EN_8814A(txdesc, value) \
+ SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value)
+#define GET_TX_DESC_USE_MAX_TIME_EN_8814A(txdesc) \
+ GET_TX_DESC_USE_MAX_TIME_EN(txdesc)
+#define SET_TX_DESC_NAVUSEHDR_8814A(txdesc, value) \
+ SET_TX_DESC_NAVUSEHDR(txdesc, value)
+#define GET_TX_DESC_NAVUSEHDR_8814A(txdesc) GET_TX_DESC_NAVUSEHDR(txdesc)
+#define SET_TX_DESC_CHK_EN_8814A(txdesc, value) \
+ SET_TX_DESC_CHK_EN(txdesc, value)
+#define GET_TX_DESC_CHK_EN_8814A(txdesc) GET_TX_DESC_CHK_EN(txdesc)
+#define SET_TX_DESC_HW_RTS_EN_8814A(txdesc, value) \
+ SET_TX_DESC_HW_RTS_EN(txdesc, value)
+#define GET_TX_DESC_HW_RTS_EN_8814A(txdesc) GET_TX_DESC_HW_RTS_EN(txdesc)
+#define SET_TX_DESC_RTSEN_8814A(txdesc, value) SET_TX_DESC_RTSEN(txdesc, value)
+#define GET_TX_DESC_RTSEN_8814A(txdesc) GET_TX_DESC_RTSEN(txdesc)
+#define SET_TX_DESC_CTS2SELF_8814A(txdesc, value) \
+ SET_TX_DESC_CTS2SELF(txdesc, value)
+#define GET_TX_DESC_CTS2SELF_8814A(txdesc) GET_TX_DESC_CTS2SELF(txdesc)
+#define SET_TX_DESC_DISDATAFB_8814A(txdesc, value) \
+ SET_TX_DESC_DISDATAFB(txdesc, value)
+#define GET_TX_DESC_DISDATAFB_8814A(txdesc) GET_TX_DESC_DISDATAFB(txdesc)
+#define SET_TX_DESC_DISRTSFB_8814A(txdesc, value) \
+ SET_TX_DESC_DISRTSFB(txdesc, value)
+#define GET_TX_DESC_DISRTSFB_8814A(txdesc) GET_TX_DESC_DISRTSFB(txdesc)
+#define SET_TX_DESC_USE_RATE_8814A(txdesc, value) \
+ SET_TX_DESC_USE_RATE(txdesc, value)
+#define GET_TX_DESC_USE_RATE_8814A(txdesc) GET_TX_DESC_USE_RATE(txdesc)
+#define SET_TX_DESC_HW_SSN_SEL_8814A(txdesc, value) \
+ SET_TX_DESC_HW_SSN_SEL(txdesc, value)
+#define GET_TX_DESC_HW_SSN_SEL_8814A(txdesc) GET_TX_DESC_HW_SSN_SEL(txdesc)
+#define SET_TX_DESC_WHEADER_LEN_8814A(txdesc, value) \
+ SET_TX_DESC_WHEADER_LEN(txdesc, value)
+#define GET_TX_DESC_WHEADER_LEN_8814A(txdesc) GET_TX_DESC_WHEADER_LEN(txdesc)
/*TXDESC_WORD4*/
-#define SET_TX_DESC_PCTS_MASK_IDX_8814A(__pTxDesc, __Value) SET_TX_DESC_PCTS_MASK_IDX(__pTxDesc, __Value)
-#define GET_TX_DESC_PCTS_MASK_IDX_8814A(__pTxDesc) GET_TX_DESC_PCTS_MASK_IDX(__pTxDesc)
-#define SET_TX_DESC_PCTS_EN_8814A(__pTxDesc, __Value) SET_TX_DESC_PCTS_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_PCTS_EN_8814A(__pTxDesc) GET_TX_DESC_PCTS_EN(__pTxDesc)
-#define SET_TX_DESC_RTSRATE_8814A(__pTxDesc, __Value) SET_TX_DESC_RTSRATE(__pTxDesc, __Value)
-#define GET_TX_DESC_RTSRATE_8814A(__pTxDesc) GET_TX_DESC_RTSRATE(__pTxDesc)
-#define SET_TX_DESC_RTS_DATA_RTY_LMT_8814A(__pTxDesc, __Value) SET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc, __Value)
-#define GET_TX_DESC_RTS_DATA_RTY_LMT_8814A(__pTxDesc) GET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc)
-#define SET_TX_DESC_RTY_LMT_EN_8814A(__pTxDesc, __Value) SET_TX_DESC_RTY_LMT_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_RTY_LMT_EN_8814A(__pTxDesc) GET_TX_DESC_RTY_LMT_EN(__pTxDesc)
-#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8814A(__pTxDesc, __Value) SET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc, __Value)
-#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8814A(__pTxDesc) GET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc)
-#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8814A(__pTxDesc, __Value) SET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc, __Value)
-#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8814A(__pTxDesc) GET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc)
-#define SET_TX_DESC_TRY_RATE_8814A(__pTxDesc, __Value) SET_TX_DESC_TRY_RATE(__pTxDesc, __Value)
-#define GET_TX_DESC_TRY_RATE_8814A(__pTxDesc) GET_TX_DESC_TRY_RATE(__pTxDesc)
-#define SET_TX_DESC_DATARATE_8814A(__pTxDesc, __Value) SET_TX_DESC_DATARATE(__pTxDesc, __Value)
-#define GET_TX_DESC_DATARATE_8814A(__pTxDesc) GET_TX_DESC_DATARATE(__pTxDesc)
+#define SET_TX_DESC_PCTS_MASK_IDX_8814A(txdesc, value) \
+ SET_TX_DESC_PCTS_MASK_IDX(txdesc, value)
+#define GET_TX_DESC_PCTS_MASK_IDX_8814A(txdesc) \
+ GET_TX_DESC_PCTS_MASK_IDX(txdesc)
+#define SET_TX_DESC_PCTS_EN_8814A(txdesc, value) \
+ SET_TX_DESC_PCTS_EN(txdesc, value)
+#define GET_TX_DESC_PCTS_EN_8814A(txdesc) GET_TX_DESC_PCTS_EN(txdesc)
+#define SET_TX_DESC_RTSRATE_8814A(txdesc, value) \
+ SET_TX_DESC_RTSRATE(txdesc, value)
+#define GET_TX_DESC_RTSRATE_8814A(txdesc) GET_TX_DESC_RTSRATE(txdesc)
+#define SET_TX_DESC_RTS_DATA_RTY_LMT_8814A(txdesc, value) \
+ SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value)
+#define GET_TX_DESC_RTS_DATA_RTY_LMT_8814A(txdesc) \
+ GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc)
+#define SET_TX_DESC_RTY_LMT_EN_8814A(txdesc, value) \
+ SET_TX_DESC_RTY_LMT_EN(txdesc, value)
+#define GET_TX_DESC_RTY_LMT_EN_8814A(txdesc) GET_TX_DESC_RTY_LMT_EN(txdesc)
+#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8814A(txdesc, value) \
+ SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value)
+#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8814A(txdesc) \
+ GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc)
+#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8814A(txdesc, value) \
+ SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value)
+#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8814A(txdesc) \
+ GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc)
+#define SET_TX_DESC_TRY_RATE_8814A(txdesc, value) \
+ SET_TX_DESC_TRY_RATE(txdesc, value)
+#define GET_TX_DESC_TRY_RATE_8814A(txdesc) GET_TX_DESC_TRY_RATE(txdesc)
+#define SET_TX_DESC_DATARATE_8814A(txdesc, value) \
+ SET_TX_DESC_DATARATE(txdesc, value)
+#define GET_TX_DESC_DATARATE_8814A(txdesc) GET_TX_DESC_DATARATE(txdesc)
/*TXDESC_WORD5*/
-#define SET_TX_DESC_POLLUTED_8814A(__pTxDesc, __Value) SET_TX_DESC_POLLUTED(__pTxDesc, __Value)
-#define GET_TX_DESC_POLLUTED_8814A(__pTxDesc) GET_TX_DESC_POLLUTED(__pTxDesc)
-#define SET_TX_DESC_TXPWR_OFSET_8814A(__pTxDesc, __Value) SET_TX_DESC_TXPWR_OFSET(__pTxDesc, __Value)
-#define GET_TX_DESC_TXPWR_OFSET_8814A(__pTxDesc) GET_TX_DESC_TXPWR_OFSET(__pTxDesc)
-#define SET_TX_DESC_TX_ANT_8814A(__pTxDesc, __Value) SET_TX_DESC_TX_ANT(__pTxDesc, __Value)
-#define GET_TX_DESC_TX_ANT_8814A(__pTxDesc) GET_TX_DESC_TX_ANT(__pTxDesc)
-#define SET_TX_DESC_PORT_ID_8814A(__pTxDesc, __Value) SET_TX_DESC_PORT_ID(__pTxDesc, __Value)
-#define GET_TX_DESC_PORT_ID_8814A(__pTxDesc) GET_TX_DESC_PORT_ID(__pTxDesc)
-#define SET_TX_DESC_SIGNALING_TAPKT_EN_8814A(__pTxDesc, __Value) SET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_SIGNALING_TAPKT_EN_8814A(__pTxDesc) GET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc)
-#define SET_TX_DESC_RTS_SC_8814A(__pTxDesc, __Value) SET_TX_DESC_RTS_SC(__pTxDesc, __Value)
-#define GET_TX_DESC_RTS_SC_8814A(__pTxDesc) GET_TX_DESC_RTS_SC(__pTxDesc)
-#define SET_TX_DESC_RTS_SHORT_8814A(__pTxDesc, __Value) SET_TX_DESC_RTS_SHORT(__pTxDesc, __Value)
-#define GET_TX_DESC_RTS_SHORT_8814A(__pTxDesc) GET_TX_DESC_RTS_SHORT(__pTxDesc)
-#define SET_TX_DESC_VCS_STBC_8814A(__pTxDesc, __Value) SET_TX_DESC_VCS_STBC(__pTxDesc, __Value)
-#define GET_TX_DESC_VCS_STBC_8814A(__pTxDesc) GET_TX_DESC_VCS_STBC(__pTxDesc)
-#define SET_TX_DESC_DATA_STBC_8814A(__pTxDesc, __Value) SET_TX_DESC_DATA_STBC(__pTxDesc, __Value)
-#define GET_TX_DESC_DATA_STBC_8814A(__pTxDesc) GET_TX_DESC_DATA_STBC(__pTxDesc)
-#define SET_TX_DESC_DATA_LDPC_8814A(__pTxDesc, __Value) SET_TX_DESC_DATA_LDPC(__pTxDesc, __Value)
-#define GET_TX_DESC_DATA_LDPC_8814A(__pTxDesc) GET_TX_DESC_DATA_LDPC(__pTxDesc)
-#define SET_TX_DESC_DATA_BW_8814A(__pTxDesc, __Value) SET_TX_DESC_DATA_BW(__pTxDesc, __Value)
-#define GET_TX_DESC_DATA_BW_8814A(__pTxDesc) GET_TX_DESC_DATA_BW(__pTxDesc)
-#define SET_TX_DESC_DATA_SHORT_8814A(__pTxDesc, __Value) SET_TX_DESC_DATA_SHORT(__pTxDesc, __Value)
-#define GET_TX_DESC_DATA_SHORT_8814A(__pTxDesc) GET_TX_DESC_DATA_SHORT(__pTxDesc)
-#define SET_TX_DESC_DATA_SC_8814A(__pTxDesc, __Value) SET_TX_DESC_DATA_SC(__pTxDesc, __Value)
-#define GET_TX_DESC_DATA_SC_8814A(__pTxDesc) GET_TX_DESC_DATA_SC(__pTxDesc)
+#define SET_TX_DESC_POLLUTED_8814A(txdesc, value) \
+ SET_TX_DESC_POLLUTED(txdesc, value)
+#define GET_TX_DESC_POLLUTED_8814A(txdesc) GET_TX_DESC_POLLUTED(txdesc)
+#define SET_TX_DESC_TXPWR_OFSET_8814A(txdesc, value) \
+ SET_TX_DESC_TXPWR_OFSET(txdesc, value)
+#define GET_TX_DESC_TXPWR_OFSET_8814A(txdesc) GET_TX_DESC_TXPWR_OFSET(txdesc)
+#define SET_TX_DESC_TX_ANT_8814A(txdesc, value) \
+ SET_TX_DESC_TX_ANT(txdesc, value)
+#define GET_TX_DESC_TX_ANT_8814A(txdesc) GET_TX_DESC_TX_ANT(txdesc)
+#define SET_TX_DESC_PORT_ID_8814A(txdesc, value) \
+ SET_TX_DESC_PORT_ID(txdesc, value)
+#define GET_TX_DESC_PORT_ID_8814A(txdesc) GET_TX_DESC_PORT_ID(txdesc)
+#define SET_TX_DESC_SIGNALING_TAPKT_EN_8814A(txdesc, value) \
+ SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value)
+#define GET_TX_DESC_SIGNALING_TAPKT_EN_8814A(txdesc) \
+ GET_TX_DESC_SIGNALING_TAPKT_EN(txdesc)
+#define SET_TX_DESC_RTS_SC_8814A(txdesc, value) \
+ SET_TX_DESC_RTS_SC(txdesc, value)
+#define GET_TX_DESC_RTS_SC_8814A(txdesc) GET_TX_DESC_RTS_SC(txdesc)
+#define SET_TX_DESC_RTS_SHORT_8814A(txdesc, value) \
+ SET_TX_DESC_RTS_SHORT(txdesc, value)
+#define GET_TX_DESC_RTS_SHORT_8814A(txdesc) GET_TX_DESC_RTS_SHORT(txdesc)
+#define SET_TX_DESC_VCS_STBC_8814A(txdesc, value) \
+ SET_TX_DESC_VCS_STBC(txdesc, value)
+#define GET_TX_DESC_VCS_STBC_8814A(txdesc) GET_TX_DESC_VCS_STBC(txdesc)
+#define SET_TX_DESC_DATA_STBC_8814A(txdesc, value) \
+ SET_TX_DESC_DATA_STBC(txdesc, value)
+#define GET_TX_DESC_DATA_STBC_8814A(txdesc) GET_TX_DESC_DATA_STBC(txdesc)
+#define SET_TX_DESC_DATA_LDPC_8814A(txdesc, value) \
+ SET_TX_DESC_DATA_LDPC(txdesc, value)
+#define GET_TX_DESC_DATA_LDPC_8814A(txdesc) GET_TX_DESC_DATA_LDPC(txdesc)
+#define SET_TX_DESC_DATA_BW_8814A(txdesc, value) \
+ SET_TX_DESC_DATA_BW(txdesc, value)
+#define GET_TX_DESC_DATA_BW_8814A(txdesc) GET_TX_DESC_DATA_BW(txdesc)
+#define SET_TX_DESC_DATA_SHORT_8814A(txdesc, value) \
+ SET_TX_DESC_DATA_SHORT(txdesc, value)
+#define GET_TX_DESC_DATA_SHORT_8814A(txdesc) GET_TX_DESC_DATA_SHORT(txdesc)
+#define SET_TX_DESC_DATA_SC_8814A(txdesc, value) \
+ SET_TX_DESC_DATA_SC(txdesc, value)
+#define GET_TX_DESC_DATA_SC_8814A(txdesc) GET_TX_DESC_DATA_SC(txdesc)
/*TXDESC_WORD6*/
-#define SET_TX_DESC_ANTSEL_D_8814A(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_D(__pTxDesc, __Value)
-#define GET_TX_DESC_ANTSEL_D_8814A(__pTxDesc) GET_TX_DESC_ANTSEL_D(__pTxDesc)
-#define SET_TX_DESC_ANT_MAPD_8814A(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPD(__pTxDesc, __Value)
-#define GET_TX_DESC_ANT_MAPD_8814A(__pTxDesc) GET_TX_DESC_ANT_MAPD(__pTxDesc)
-#define SET_TX_DESC_ANT_MAPC_8814A(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPC(__pTxDesc, __Value)
-#define GET_TX_DESC_ANT_MAPC_8814A(__pTxDesc) GET_TX_DESC_ANT_MAPC(__pTxDesc)
-#define SET_TX_DESC_ANT_MAPB_8814A(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPB(__pTxDesc, __Value)
-#define GET_TX_DESC_ANT_MAPB_8814A(__pTxDesc) GET_TX_DESC_ANT_MAPB(__pTxDesc)
-#define SET_TX_DESC_ANT_MAPA_8814A(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPA(__pTxDesc, __Value)
-#define GET_TX_DESC_ANT_MAPA_8814A(__pTxDesc) GET_TX_DESC_ANT_MAPA(__pTxDesc)
-#define SET_TX_DESC_ANTSEL_C_8814A(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_C(__pTxDesc, __Value)
-#define GET_TX_DESC_ANTSEL_C_8814A(__pTxDesc) GET_TX_DESC_ANTSEL_C(__pTxDesc)
-#define SET_TX_DESC_ANTSEL_B_8814A(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_B(__pTxDesc, __Value)
-#define GET_TX_DESC_ANTSEL_B_8814A(__pTxDesc) GET_TX_DESC_ANTSEL_B(__pTxDesc)
-#define SET_TX_DESC_ANTSEL_A_8814A(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_A(__pTxDesc, __Value)
-#define GET_TX_DESC_ANTSEL_A_8814A(__pTxDesc) GET_TX_DESC_ANTSEL_A(__pTxDesc)
-#define SET_TX_DESC_MBSSID_8814A(__pTxDesc, __Value) SET_TX_DESC_MBSSID(__pTxDesc, __Value)
-#define GET_TX_DESC_MBSSID_8814A(__pTxDesc) GET_TX_DESC_MBSSID(__pTxDesc)
-#define SET_TX_DESC_SW_DEFINE_8814A(__pTxDesc, __Value) SET_TX_DESC_SW_DEFINE(__pTxDesc, __Value)
-#define GET_TX_DESC_SW_DEFINE_8814A(__pTxDesc) GET_TX_DESC_SW_DEFINE(__pTxDesc)
+#define SET_TX_DESC_ANTSEL_D_8814A(txdesc, value) \
+ SET_TX_DESC_ANTSEL_D(txdesc, value)
+#define GET_TX_DESC_ANTSEL_D_8814A(txdesc) GET_TX_DESC_ANTSEL_D(txdesc)
+#define SET_TX_DESC_ANT_MAPD_8814A(txdesc, value) \
+ SET_TX_DESC_ANT_MAPD(txdesc, value)
+#define GET_TX_DESC_ANT_MAPD_8814A(txdesc) GET_TX_DESC_ANT_MAPD(txdesc)
+#define SET_TX_DESC_ANT_MAPC_8814A(txdesc, value) \
+ SET_TX_DESC_ANT_MAPC(txdesc, value)
+#define GET_TX_DESC_ANT_MAPC_8814A(txdesc) GET_TX_DESC_ANT_MAPC(txdesc)
+#define SET_TX_DESC_ANT_MAPB_8814A(txdesc, value) \
+ SET_TX_DESC_ANT_MAPB(txdesc, value)
+#define GET_TX_DESC_ANT_MAPB_8814A(txdesc) GET_TX_DESC_ANT_MAPB(txdesc)
+#define SET_TX_DESC_ANT_MAPA_8814A(txdesc, value) \
+ SET_TX_DESC_ANT_MAPA(txdesc, value)
+#define GET_TX_DESC_ANT_MAPA_8814A(txdesc) GET_TX_DESC_ANT_MAPA(txdesc)
+#define SET_TX_DESC_ANTSEL_C_8814A(txdesc, value) \
+ SET_TX_DESC_ANTSEL_C(txdesc, value)
+#define GET_TX_DESC_ANTSEL_C_8814A(txdesc) GET_TX_DESC_ANTSEL_C(txdesc)
+#define SET_TX_DESC_ANTSEL_B_8814A(txdesc, value) \
+ SET_TX_DESC_ANTSEL_B(txdesc, value)
+#define GET_TX_DESC_ANTSEL_B_8814A(txdesc) GET_TX_DESC_ANTSEL_B(txdesc)
+#define SET_TX_DESC_ANTSEL_A_8814A(txdesc, value) \
+ SET_TX_DESC_ANTSEL_A(txdesc, value)
+#define GET_TX_DESC_ANTSEL_A_8814A(txdesc) GET_TX_DESC_ANTSEL_A(txdesc)
+#define SET_TX_DESC_MBSSID_8814A(txdesc, value) \
+ SET_TX_DESC_MBSSID(txdesc, value)
+#define GET_TX_DESC_MBSSID_8814A(txdesc) GET_TX_DESC_MBSSID(txdesc)
+#define SET_TX_DESC_SW_DEFINE_8814A(txdesc, value) \
+ SET_TX_DESC_SW_DEFINE(txdesc, value)
+#define GET_TX_DESC_SW_DEFINE_8814A(txdesc) GET_TX_DESC_SW_DEFINE(txdesc)
/*TXDESC_WORD7*/
-#define SET_TX_DESC_DMA_TXAGG_NUM_8814A(__pTxDesc, __Value) SET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc, __Value)
-#define GET_TX_DESC_DMA_TXAGG_NUM_8814A(__pTxDesc) GET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc)
-#define SET_TX_DESC_FINAL_DATA_RATE_8814A(__pTxDesc, __Value) SET_TX_DESC_FINAL_DATA_RATE(__pTxDesc, __Value)
-#define GET_TX_DESC_FINAL_DATA_RATE_8814A(__pTxDesc) GET_TX_DESC_FINAL_DATA_RATE(__pTxDesc)
-#define SET_TX_DESC_NTX_MAP_8814A(__pTxDesc, __Value) SET_TX_DESC_NTX_MAP(__pTxDesc, __Value)
-#define GET_TX_DESC_NTX_MAP_8814A(__pTxDesc) GET_TX_DESC_NTX_MAP(__pTxDesc)
-#define SET_TX_DESC_TX_BUFF_SIZE_8814A(__pTxDesc, __Value) SET_TX_DESC_TX_BUFF_SIZE(__pTxDesc, __Value)
-#define GET_TX_DESC_TX_BUFF_SIZE_8814A(__pTxDesc) GET_TX_DESC_TX_BUFF_SIZE(__pTxDesc)
-#define SET_TX_DESC_TXDESC_CHECKSUM_8814A(__pTxDesc, __Value) SET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc, __Value)
-#define GET_TX_DESC_TXDESC_CHECKSUM_8814A(__pTxDesc) GET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc)
-#define SET_TX_DESC_TIMESTAMP_8814A(__pTxDesc, __Value) SET_TX_DESC_TIMESTAMP(__pTxDesc, __Value)
-#define GET_TX_DESC_TIMESTAMP_8814A(__pTxDesc) GET_TX_DESC_TIMESTAMP(__pTxDesc)
+#define SET_TX_DESC_DMA_TXAGG_NUM_8814A(txdesc, value) \
+ SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value)
+#define GET_TX_DESC_DMA_TXAGG_NUM_8814A(txdesc) \
+ GET_TX_DESC_DMA_TXAGG_NUM(txdesc)
+#define SET_TX_DESC_FINAL_DATA_RATE_8814A(txdesc, value) \
+ SET_TX_DESC_FINAL_DATA_RATE(txdesc, value)
+#define GET_TX_DESC_FINAL_DATA_RATE_8814A(txdesc) \
+ GET_TX_DESC_FINAL_DATA_RATE(txdesc)
+#define SET_TX_DESC_NTX_MAP_8814A(txdesc, value) \
+ SET_TX_DESC_NTX_MAP(txdesc, value)
+#define GET_TX_DESC_NTX_MAP_8814A(txdesc) GET_TX_DESC_NTX_MAP(txdesc)
+#define SET_TX_DESC_TX_BUFF_SIZE_8814A(txdesc, value) \
+ SET_TX_DESC_TX_BUFF_SIZE(txdesc, value)
+#define GET_TX_DESC_TX_BUFF_SIZE_8814A(txdesc) GET_TX_DESC_TX_BUFF_SIZE(txdesc)
+#define SET_TX_DESC_TXDESC_CHECKSUM_8814A(txdesc, value) \
+ SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value)
+#define GET_TX_DESC_TXDESC_CHECKSUM_8814A(txdesc) \
+ GET_TX_DESC_TXDESC_CHECKSUM(txdesc)
+#define SET_TX_DESC_TIMESTAMP_8814A(txdesc, value) \
+ SET_TX_DESC_TIMESTAMP(txdesc, value)
+#define GET_TX_DESC_TIMESTAMP_8814A(txdesc) GET_TX_DESC_TIMESTAMP(txdesc)
/*TXDESC_WORD8*/
-#define SET_TX_DESC_TXWIFI_CP_8814A(__pTxDesc, __Value) SET_TX_DESC_TXWIFI_CP(__pTxDesc, __Value)
-#define GET_TX_DESC_TXWIFI_CP_8814A(__pTxDesc) GET_TX_DESC_TXWIFI_CP(__pTxDesc)
-#define SET_TX_DESC_MAC_CP_8814A(__pTxDesc, __Value) SET_TX_DESC_MAC_CP(__pTxDesc, __Value)
-#define GET_TX_DESC_MAC_CP_8814A(__pTxDesc) GET_TX_DESC_MAC_CP(__pTxDesc)
-#define SET_TX_DESC_STW_PKTRE_DIS_8814A(__pTxDesc, __Value) SET_TX_DESC_STW_PKTRE_DIS(__pTxDesc, __Value)
-#define GET_TX_DESC_STW_PKTRE_DIS_8814A(__pTxDesc) GET_TX_DESC_STW_PKTRE_DIS(__pTxDesc)
-#define SET_TX_DESC_STW_RB_DIS_8814A(__pTxDesc, __Value) SET_TX_DESC_STW_RB_DIS(__pTxDesc, __Value)
-#define GET_TX_DESC_STW_RB_DIS_8814A(__pTxDesc) GET_TX_DESC_STW_RB_DIS(__pTxDesc)
-#define SET_TX_DESC_STW_RATE_DIS_8814A(__pTxDesc, __Value) SET_TX_DESC_STW_RATE_DIS(__pTxDesc, __Value)
-#define GET_TX_DESC_STW_RATE_DIS_8814A(__pTxDesc) GET_TX_DESC_STW_RATE_DIS(__pTxDesc)
-#define SET_TX_DESC_STW_ANT_DIS_8814A(__pTxDesc, __Value) SET_TX_DESC_STW_ANT_DIS(__pTxDesc, __Value)
-#define GET_TX_DESC_STW_ANT_DIS_8814A(__pTxDesc) GET_TX_DESC_STW_ANT_DIS(__pTxDesc)
-#define SET_TX_DESC_STW_EN_8814A(__pTxDesc, __Value) SET_TX_DESC_STW_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_STW_EN_8814A(__pTxDesc) GET_TX_DESC_STW_EN(__pTxDesc)
-#define SET_TX_DESC_SMH_EN_8814A(__pTxDesc, __Value) SET_TX_DESC_SMH_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_SMH_EN_8814A(__pTxDesc) GET_TX_DESC_SMH_EN(__pTxDesc)
-#define SET_TX_DESC_TAILPAGE_L_8814A(__pTxDesc, __Value) SET_TX_DESC_TAILPAGE_L(__pTxDesc, __Value)
-#define GET_TX_DESC_TAILPAGE_L_8814A(__pTxDesc) GET_TX_DESC_TAILPAGE_L(__pTxDesc)
-#define SET_TX_DESC_SDIO_DMASEQ_8814A(__pTxDesc, __Value) SET_TX_DESC_SDIO_DMASEQ(__pTxDesc, __Value)
-#define GET_TX_DESC_SDIO_DMASEQ_8814A(__pTxDesc) GET_TX_DESC_SDIO_DMASEQ(__pTxDesc)
-#define SET_TX_DESC_NEXTHEADPAGE_L_8814A(__pTxDesc, __Value) SET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc, __Value)
-#define GET_TX_DESC_NEXTHEADPAGE_L_8814A(__pTxDesc) GET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc)
-#define SET_TX_DESC_EN_HWSEQ_8814A(__pTxDesc, __Value) SET_TX_DESC_EN_HWSEQ(__pTxDesc, __Value)
-#define GET_TX_DESC_EN_HWSEQ_8814A(__pTxDesc) GET_TX_DESC_EN_HWSEQ(__pTxDesc)
-#define SET_TX_DESC_EN_HWEXSEQ_8814A(__pTxDesc, __Value) SET_TX_DESC_EN_HWEXSEQ(__pTxDesc, __Value)
-#define GET_TX_DESC_EN_HWEXSEQ_8814A(__pTxDesc) GET_TX_DESC_EN_HWEXSEQ(__pTxDesc)
-#define SET_TX_DESC_DATA_RC_8814A(__pTxDesc, __Value) SET_TX_DESC_DATA_RC(__pTxDesc, __Value)
-#define GET_TX_DESC_DATA_RC_8814A(__pTxDesc) GET_TX_DESC_DATA_RC(__pTxDesc)
-#define SET_TX_DESC_BAR_RTY_TH_8814A(__pTxDesc, __Value) SET_TX_DESC_BAR_RTY_TH(__pTxDesc, __Value)
-#define GET_TX_DESC_BAR_RTY_TH_8814A(__pTxDesc) GET_TX_DESC_BAR_RTY_TH(__pTxDesc)
-#define SET_TX_DESC_RTS_RC_8814A(__pTxDesc, __Value) SET_TX_DESC_RTS_RC(__pTxDesc, __Value)
-#define GET_TX_DESC_RTS_RC_8814A(__pTxDesc) GET_TX_DESC_RTS_RC(__pTxDesc)
+#define SET_TX_DESC_TXWIFI_CP_8814A(txdesc, value) \
+ SET_TX_DESC_TXWIFI_CP(txdesc, value)
+#define GET_TX_DESC_TXWIFI_CP_8814A(txdesc) GET_TX_DESC_TXWIFI_CP(txdesc)
+#define SET_TX_DESC_MAC_CP_8814A(txdesc, value) \
+ SET_TX_DESC_MAC_CP(txdesc, value)
+#define GET_TX_DESC_MAC_CP_8814A(txdesc) GET_TX_DESC_MAC_CP(txdesc)
+#define SET_TX_DESC_STW_PKTRE_DIS_8814A(txdesc, value) \
+ SET_TX_DESC_STW_PKTRE_DIS(txdesc, value)
+#define GET_TX_DESC_STW_PKTRE_DIS_8814A(txdesc) \
+ GET_TX_DESC_STW_PKTRE_DIS(txdesc)
+#define SET_TX_DESC_STW_RB_DIS_8814A(txdesc, value) \
+ SET_TX_DESC_STW_RB_DIS(txdesc, value)
+#define GET_TX_DESC_STW_RB_DIS_8814A(txdesc) GET_TX_DESC_STW_RB_DIS(txdesc)
+#define SET_TX_DESC_STW_RATE_DIS_8814A(txdesc, value) \
+ SET_TX_DESC_STW_RATE_DIS(txdesc, value)
+#define GET_TX_DESC_STW_RATE_DIS_8814A(txdesc) GET_TX_DESC_STW_RATE_DIS(txdesc)
+#define SET_TX_DESC_STW_ANT_DIS_8814A(txdesc, value) \
+ SET_TX_DESC_STW_ANT_DIS(txdesc, value)
+#define GET_TX_DESC_STW_ANT_DIS_8814A(txdesc) GET_TX_DESC_STW_ANT_DIS(txdesc)
+#define SET_TX_DESC_STW_EN_8814A(txdesc, value) \
+ SET_TX_DESC_STW_EN(txdesc, value)
+#define GET_TX_DESC_STW_EN_8814A(txdesc) GET_TX_DESC_STW_EN(txdesc)
+#define SET_TX_DESC_SMH_EN_8814A(txdesc, value) \
+ SET_TX_DESC_SMH_EN(txdesc, value)
+#define GET_TX_DESC_SMH_EN_8814A(txdesc) GET_TX_DESC_SMH_EN(txdesc)
+#define SET_TX_DESC_TAILPAGE_L_8814A(txdesc, value) \
+ SET_TX_DESC_TAILPAGE_L(txdesc, value)
+#define GET_TX_DESC_TAILPAGE_L_8814A(txdesc) GET_TX_DESC_TAILPAGE_L(txdesc)
+#define SET_TX_DESC_SDIO_DMASEQ_8814A(txdesc, value) \
+ SET_TX_DESC_SDIO_DMASEQ(txdesc, value)
+#define GET_TX_DESC_SDIO_DMASEQ_8814A(txdesc) GET_TX_DESC_SDIO_DMASEQ(txdesc)
+#define SET_TX_DESC_NEXTHEADPAGE_L_8814A(txdesc, value) \
+ SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value)
+#define GET_TX_DESC_NEXTHEADPAGE_L_8814A(txdesc) \
+ GET_TX_DESC_NEXTHEADPAGE_L(txdesc)
+#define SET_TX_DESC_EN_HWSEQ_8814A(txdesc, value) \
+ SET_TX_DESC_EN_HWSEQ(txdesc, value)
+#define GET_TX_DESC_EN_HWSEQ_8814A(txdesc) GET_TX_DESC_EN_HWSEQ(txdesc)
+#define SET_TX_DESC_EN_HWEXSEQ_8814A(txdesc, value) \
+ SET_TX_DESC_EN_HWEXSEQ(txdesc, value)
+#define GET_TX_DESC_EN_HWEXSEQ_8814A(txdesc) GET_TX_DESC_EN_HWEXSEQ(txdesc)
+#define SET_TX_DESC_DATA_RC_8814A(txdesc, value) \
+ SET_TX_DESC_DATA_RC(txdesc, value)
+#define GET_TX_DESC_DATA_RC_8814A(txdesc) GET_TX_DESC_DATA_RC(txdesc)
+#define SET_TX_DESC_BAR_RTY_TH_8814A(txdesc, value) \
+ SET_TX_DESC_BAR_RTY_TH(txdesc, value)
+#define GET_TX_DESC_BAR_RTY_TH_8814A(txdesc) GET_TX_DESC_BAR_RTY_TH(txdesc)
+#define SET_TX_DESC_RTS_RC_8814A(txdesc, value) \
+ SET_TX_DESC_RTS_RC(txdesc, value)
+#define GET_TX_DESC_RTS_RC_8814A(txdesc) GET_TX_DESC_RTS_RC(txdesc)
/*TXDESC_WORD9*/
-#define SET_TX_DESC_TAILPAGE_H_8814A(__pTxDesc, __Value) SET_TX_DESC_TAILPAGE_H(__pTxDesc, __Value)
-#define GET_TX_DESC_TAILPAGE_H_8814A(__pTxDesc) GET_TX_DESC_TAILPAGE_H(__pTxDesc)
-#define SET_TX_DESC_NEXTHEADPAGE_H_8814A(__pTxDesc, __Value) SET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc, __Value)
-#define GET_TX_DESC_NEXTHEADPAGE_H_8814A(__pTxDesc) GET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc)
-#define SET_TX_DESC_SW_SEQ_8814A(__pTxDesc, __Value) SET_TX_DESC_SW_SEQ(__pTxDesc, __Value)
-#define GET_TX_DESC_SW_SEQ_8814A(__pTxDesc) GET_TX_DESC_SW_SEQ(__pTxDesc)
-#define SET_TX_DESC_TXBF_PATH_8814A(__pTxDesc, __Value) SET_TX_DESC_TXBF_PATH(__pTxDesc, __Value)
-#define GET_TX_DESC_TXBF_PATH_8814A(__pTxDesc) GET_TX_DESC_TXBF_PATH(__pTxDesc)
-#define SET_TX_DESC_PADDING_LEN_8814A(__pTxDesc, __Value) SET_TX_DESC_PADDING_LEN(__pTxDesc, __Value)
-#define GET_TX_DESC_PADDING_LEN_8814A(__pTxDesc) GET_TX_DESC_PADDING_LEN(__pTxDesc)
-#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8814A(__pTxDesc, __Value) SET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc, __Value)
-#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8814A(__pTxDesc) GET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc)
+#define SET_TX_DESC_TAILPAGE_H_8814A(txdesc, value) \
+ SET_TX_DESC_TAILPAGE_H(txdesc, value)
+#define GET_TX_DESC_TAILPAGE_H_8814A(txdesc) GET_TX_DESC_TAILPAGE_H(txdesc)
+#define SET_TX_DESC_NEXTHEADPAGE_H_8814A(txdesc, value) \
+ SET_TX_DESC_NEXTHEADPAGE_H(txdesc, value)
+#define GET_TX_DESC_NEXTHEADPAGE_H_8814A(txdesc) \
+ GET_TX_DESC_NEXTHEADPAGE_H(txdesc)
+#define SET_TX_DESC_SW_SEQ_8814A(txdesc, value) \
+ SET_TX_DESC_SW_SEQ(txdesc, value)
+#define GET_TX_DESC_SW_SEQ_8814A(txdesc) GET_TX_DESC_SW_SEQ(txdesc)
+#define SET_TX_DESC_TXBF_PATH_8814A(txdesc, value) \
+ SET_TX_DESC_TXBF_PATH(txdesc, value)
+#define GET_TX_DESC_TXBF_PATH_8814A(txdesc) GET_TX_DESC_TXBF_PATH(txdesc)
+#define SET_TX_DESC_PADDING_LEN_8814A(txdesc, value) \
+ SET_TX_DESC_PADDING_LEN(txdesc, value)
+#define GET_TX_DESC_PADDING_LEN_8814A(txdesc) GET_TX_DESC_PADDING_LEN(txdesc)
+#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8814A(txdesc, value) \
+ SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value)
+#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8814A(txdesc) \
+ GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc)
/*WORD10*/
-
#endif
#if (HALMAC_8822B_SUPPORT)
/*TXDESC_WORD0*/
-#define SET_TX_DESC_DISQSELSEQ_8822B(__pTxDesc, __Value) SET_TX_DESC_DISQSELSEQ(__pTxDesc, __Value)
-#define GET_TX_DESC_DISQSELSEQ_8822B(__pTxDesc) GET_TX_DESC_DISQSELSEQ(__pTxDesc)
-#define SET_TX_DESC_GF_8822B(__pTxDesc, __Value) SET_TX_DESC_GF(__pTxDesc, __Value)
-#define GET_TX_DESC_GF_8822B(__pTxDesc) GET_TX_DESC_GF(__pTxDesc)
-#define SET_TX_DESC_NO_ACM_8822B(__pTxDesc, __Value) SET_TX_DESC_NO_ACM(__pTxDesc, __Value)
-#define GET_TX_DESC_NO_ACM_8822B(__pTxDesc) GET_TX_DESC_NO_ACM(__pTxDesc)
-#define SET_TX_DESC_BCNPKT_TSF_CTRL_8822B(__pTxDesc, __Value) SET_TX_DESC_BCNPKT_TSF_CTRL(__pTxDesc, __Value)
-#define GET_TX_DESC_BCNPKT_TSF_CTRL_8822B(__pTxDesc) GET_TX_DESC_BCNPKT_TSF_CTRL(__pTxDesc)
-#define SET_TX_DESC_AMSDU_PAD_EN_8822B(__pTxDesc, __Value) SET_TX_DESC_AMSDU_PAD_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_AMSDU_PAD_EN_8822B(__pTxDesc) GET_TX_DESC_AMSDU_PAD_EN(__pTxDesc)
-#define SET_TX_DESC_LS_8822B(__pTxDesc, __Value) SET_TX_DESC_LS(__pTxDesc, __Value)
-#define GET_TX_DESC_LS_8822B(__pTxDesc) GET_TX_DESC_LS(__pTxDesc)
-#define SET_TX_DESC_HTC_8822B(__pTxDesc, __Value) SET_TX_DESC_HTC(__pTxDesc, __Value)
-#define GET_TX_DESC_HTC_8822B(__pTxDesc) GET_TX_DESC_HTC(__pTxDesc)
-#define SET_TX_DESC_BMC_8822B(__pTxDesc, __Value) SET_TX_DESC_BMC(__pTxDesc, __Value)
-#define GET_TX_DESC_BMC_8822B(__pTxDesc) GET_TX_DESC_BMC(__pTxDesc)
-#define SET_TX_DESC_OFFSET_8822B(__pTxDesc, __Value) SET_TX_DESC_OFFSET(__pTxDesc, __Value)
-#define GET_TX_DESC_OFFSET_8822B(__pTxDesc) GET_TX_DESC_OFFSET(__pTxDesc)
-#define SET_TX_DESC_TXPKTSIZE_8822B(__pTxDesc, __Value) SET_TX_DESC_TXPKTSIZE(__pTxDesc, __Value)
-#define GET_TX_DESC_TXPKTSIZE_8822B(__pTxDesc) GET_TX_DESC_TXPKTSIZE(__pTxDesc)
-
-/*TXDESC_WORD1*/
-
-#define SET_TX_DESC_MOREDATA_8822B(__pTxDesc, __Value) SET_TX_DESC_MOREDATA(__pTxDesc, __Value)
-#define GET_TX_DESC_MOREDATA_8822B(__pTxDesc) GET_TX_DESC_MOREDATA(__pTxDesc)
-#define SET_TX_DESC_PKT_OFFSET_8822B(__pTxDesc, __Value) SET_TX_DESC_PKT_OFFSET(__pTxDesc, __Value)
-#define GET_TX_DESC_PKT_OFFSET_8822B(__pTxDesc) GET_TX_DESC_PKT_OFFSET(__pTxDesc)
-#define SET_TX_DESC_SEC_TYPE_8822B(__pTxDesc, __Value) SET_TX_DESC_SEC_TYPE(__pTxDesc, __Value)
-#define GET_TX_DESC_SEC_TYPE_8822B(__pTxDesc) GET_TX_DESC_SEC_TYPE(__pTxDesc)
-#define SET_TX_DESC_EN_DESC_ID_8822B(__pTxDesc, __Value) SET_TX_DESC_EN_DESC_ID(__pTxDesc, __Value)
-#define GET_TX_DESC_EN_DESC_ID_8822B(__pTxDesc) GET_TX_DESC_EN_DESC_ID(__pTxDesc)
-#define SET_TX_DESC_RATE_ID_8822B(__pTxDesc, __Value) SET_TX_DESC_RATE_ID(__pTxDesc, __Value)
-#define GET_TX_DESC_RATE_ID_8822B(__pTxDesc) GET_TX_DESC_RATE_ID(__pTxDesc)
-#define SET_TX_DESC_PIFS_8822B(__pTxDesc, __Value) SET_TX_DESC_PIFS(__pTxDesc, __Value)
-#define GET_TX_DESC_PIFS_8822B(__pTxDesc) GET_TX_DESC_PIFS(__pTxDesc)
-#define SET_TX_DESC_LSIG_TXOP_EN_8822B(__pTxDesc, __Value) SET_TX_DESC_LSIG_TXOP_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_LSIG_TXOP_EN_8822B(__pTxDesc) GET_TX_DESC_LSIG_TXOP_EN(__pTxDesc)
-#define SET_TX_DESC_RD_NAV_EXT_8822B(__pTxDesc, __Value) SET_TX_DESC_RD_NAV_EXT(__pTxDesc, __Value)
-#define GET_TX_DESC_RD_NAV_EXT_8822B(__pTxDesc) GET_TX_DESC_RD_NAV_EXT(__pTxDesc)
-#define SET_TX_DESC_QSEL_8822B(__pTxDesc, __Value) SET_TX_DESC_QSEL(__pTxDesc, __Value)
-#define GET_TX_DESC_QSEL_8822B(__pTxDesc) GET_TX_DESC_QSEL(__pTxDesc)
-#define SET_TX_DESC_MACID_8822B(__pTxDesc, __Value) SET_TX_DESC_MACID(__pTxDesc, __Value)
-#define GET_TX_DESC_MACID_8822B(__pTxDesc) GET_TX_DESC_MACID(__pTxDesc)
+#define SET_TX_DESC_DISQSELSEQ_8822B(txdesc, value) \
+ SET_TX_DESC_DISQSELSEQ(txdesc, value)
+#define GET_TX_DESC_DISQSELSEQ_8822B(txdesc) GET_TX_DESC_DISQSELSEQ(txdesc)
+#define SET_TX_DESC_GF_8822B(txdesc, value) SET_TX_DESC_GF(txdesc, value)
+#define GET_TX_DESC_GF_8822B(txdesc) GET_TX_DESC_GF(txdesc)
+#define SET_TX_DESC_NO_ACM_8822B(txdesc, value) \
+ SET_TX_DESC_NO_ACM(txdesc, value)
+#define GET_TX_DESC_NO_ACM_8822B(txdesc) GET_TX_DESC_NO_ACM(txdesc)
+#define SET_TX_DESC_BCNPKT_TSF_CTRL_8822B(txdesc, value) \
+ SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value)
+#define GET_TX_DESC_BCNPKT_TSF_CTRL_8822B(txdesc) \
+ GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc)
+#define SET_TX_DESC_AMSDU_PAD_EN_8822B(txdesc, value) \
+ SET_TX_DESC_AMSDU_PAD_EN(txdesc, value)
+#define GET_TX_DESC_AMSDU_PAD_EN_8822B(txdesc) GET_TX_DESC_AMSDU_PAD_EN(txdesc)
+#define SET_TX_DESC_LS_8822B(txdesc, value) SET_TX_DESC_LS(txdesc, value)
+#define GET_TX_DESC_LS_8822B(txdesc) GET_TX_DESC_LS(txdesc)
+#define SET_TX_DESC_HTC_8822B(txdesc, value) SET_TX_DESC_HTC(txdesc, value)
+#define GET_TX_DESC_HTC_8822B(txdesc) GET_TX_DESC_HTC(txdesc)
+#define SET_TX_DESC_BMC_8822B(txdesc, value) SET_TX_DESC_BMC(txdesc, value)
+#define GET_TX_DESC_BMC_8822B(txdesc) GET_TX_DESC_BMC(txdesc)
+#define SET_TX_DESC_OFFSET_8822B(txdesc, value) \
+ SET_TX_DESC_OFFSET(txdesc, value)
+#define GET_TX_DESC_OFFSET_8822B(txdesc) GET_TX_DESC_OFFSET(txdesc)
+#define SET_TX_DESC_TXPKTSIZE_8822B(txdesc, value) \
+ SET_TX_DESC_TXPKTSIZE(txdesc, value)
+#define GET_TX_DESC_TXPKTSIZE_8822B(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc)
+
+/*WORD1*/
+
+#define SET_TX_DESC_MOREDATA_8822B(txdesc, value) \
+ SET_TX_DESC_MOREDATA(txdesc, value)
+#define GET_TX_DESC_MOREDATA_8822B(txdesc) GET_TX_DESC_MOREDATA(txdesc)
+#define SET_TX_DESC_PKT_OFFSET_8822B(txdesc, value) \
+ SET_TX_DESC_PKT_OFFSET(txdesc, value)
+#define GET_TX_DESC_PKT_OFFSET_8822B(txdesc) GET_TX_DESC_PKT_OFFSET(txdesc)
+#define SET_TX_DESC_SEC_TYPE_8822B(txdesc, value) \
+ SET_TX_DESC_SEC_TYPE(txdesc, value)
+#define GET_TX_DESC_SEC_TYPE_8822B(txdesc) GET_TX_DESC_SEC_TYPE(txdesc)
+#define SET_TX_DESC_EN_DESC_ID_8822B(txdesc, value) \
+ SET_TX_DESC_EN_DESC_ID(txdesc, value)
+#define GET_TX_DESC_EN_DESC_ID_8822B(txdesc) GET_TX_DESC_EN_DESC_ID(txdesc)
+#define SET_TX_DESC_RATE_ID_8822B(txdesc, value) \
+ SET_TX_DESC_RATE_ID(txdesc, value)
+#define GET_TX_DESC_RATE_ID_8822B(txdesc) GET_TX_DESC_RATE_ID(txdesc)
+#define SET_TX_DESC_PIFS_8822B(txdesc, value) SET_TX_DESC_PIFS(txdesc, value)
+#define GET_TX_DESC_PIFS_8822B(txdesc) GET_TX_DESC_PIFS(txdesc)
+#define SET_TX_DESC_LSIG_TXOP_EN_8822B(txdesc, value) \
+ SET_TX_DESC_LSIG_TXOP_EN(txdesc, value)
+#define GET_TX_DESC_LSIG_TXOP_EN_8822B(txdesc) GET_TX_DESC_LSIG_TXOP_EN(txdesc)
+#define SET_TX_DESC_RD_NAV_EXT_8822B(txdesc, value) \
+ SET_TX_DESC_RD_NAV_EXT(txdesc, value)
+#define GET_TX_DESC_RD_NAV_EXT_8822B(txdesc) GET_TX_DESC_RD_NAV_EXT(txdesc)
+#define SET_TX_DESC_QSEL_8822B(txdesc, value) SET_TX_DESC_QSEL(txdesc, value)
+#define GET_TX_DESC_QSEL_8822B(txdesc) GET_TX_DESC_QSEL(txdesc)
+#define SET_TX_DESC_MACID_8822B(txdesc, value) SET_TX_DESC_MACID(txdesc, value)
+#define GET_TX_DESC_MACID_8822B(txdesc) GET_TX_DESC_MACID(txdesc)
/*TXDESC_WORD2*/
-#define SET_TX_DESC_HW_AES_IV_8822B(__pTxDesc, __Value) SET_TX_DESC_HW_AES_IV(__pTxDesc, __Value)
-#define GET_TX_DESC_HW_AES_IV_8822B(__pTxDesc) GET_TX_DESC_HW_AES_IV(__pTxDesc)
-#define SET_TX_DESC_FTM_EN_8822B(__pTxDesc, __Value) SET_TX_DESC_FTM_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_FTM_EN_8822B(__pTxDesc) GET_TX_DESC_FTM_EN(__pTxDesc)
-#define SET_TX_DESC_G_ID_8822B(__pTxDesc, __Value) SET_TX_DESC_G_ID(__pTxDesc, __Value)
-#define GET_TX_DESC_G_ID_8822B(__pTxDesc) GET_TX_DESC_G_ID(__pTxDesc)
-#define SET_TX_DESC_BT_NULL_8822B(__pTxDesc, __Value) SET_TX_DESC_BT_NULL(__pTxDesc, __Value)
-#define GET_TX_DESC_BT_NULL_8822B(__pTxDesc) GET_TX_DESC_BT_NULL(__pTxDesc)
-#define SET_TX_DESC_AMPDU_DENSITY_8822B(__pTxDesc, __Value) SET_TX_DESC_AMPDU_DENSITY(__pTxDesc, __Value)
-#define GET_TX_DESC_AMPDU_DENSITY_8822B(__pTxDesc) GET_TX_DESC_AMPDU_DENSITY(__pTxDesc)
-#define SET_TX_DESC_SPE_RPT_8822B(__pTxDesc, __Value) SET_TX_DESC_SPE_RPT(__pTxDesc, __Value)
-#define GET_TX_DESC_SPE_RPT_8822B(__pTxDesc) GET_TX_DESC_SPE_RPT(__pTxDesc)
-#define SET_TX_DESC_RAW_8822B(__pTxDesc, __Value) SET_TX_DESC_RAW(__pTxDesc, __Value)
-#define GET_TX_DESC_RAW_8822B(__pTxDesc) GET_TX_DESC_RAW(__pTxDesc)
-#define SET_TX_DESC_MOREFRAG_8822B(__pTxDesc, __Value) SET_TX_DESC_MOREFRAG(__pTxDesc, __Value)
-#define GET_TX_DESC_MOREFRAG_8822B(__pTxDesc) GET_TX_DESC_MOREFRAG(__pTxDesc)
-#define SET_TX_DESC_BK_8822B(__pTxDesc, __Value) SET_TX_DESC_BK(__pTxDesc, __Value)
-#define GET_TX_DESC_BK_8822B(__pTxDesc) GET_TX_DESC_BK(__pTxDesc)
-#define SET_TX_DESC_NULL_1_8822B(__pTxDesc, __Value) SET_TX_DESC_NULL_1(__pTxDesc, __Value)
-#define GET_TX_DESC_NULL_1_8822B(__pTxDesc) GET_TX_DESC_NULL_1(__pTxDesc)
-#define SET_TX_DESC_NULL_0_8822B(__pTxDesc, __Value) SET_TX_DESC_NULL_0(__pTxDesc, __Value)
-#define GET_TX_DESC_NULL_0_8822B(__pTxDesc) GET_TX_DESC_NULL_0(__pTxDesc)
-#define SET_TX_DESC_RDG_EN_8822B(__pTxDesc, __Value) SET_TX_DESC_RDG_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_RDG_EN_8822B(__pTxDesc) GET_TX_DESC_RDG_EN(__pTxDesc)
-#define SET_TX_DESC_AGG_EN_8822B(__pTxDesc, __Value) SET_TX_DESC_AGG_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_AGG_EN_8822B(__pTxDesc) GET_TX_DESC_AGG_EN(__pTxDesc)
-#define SET_TX_DESC_CCA_RTS_8822B(__pTxDesc, __Value) SET_TX_DESC_CCA_RTS(__pTxDesc, __Value)
-#define GET_TX_DESC_CCA_RTS_8822B(__pTxDesc) GET_TX_DESC_CCA_RTS(__pTxDesc)
-#define SET_TX_DESC_TRI_FRAME_8822B(__pTxDesc, __Value) SET_TX_DESC_TRI_FRAME(__pTxDesc, __Value)
-#define GET_TX_DESC_TRI_FRAME_8822B(__pTxDesc) GET_TX_DESC_TRI_FRAME(__pTxDesc)
-#define SET_TX_DESC_P_AID_8822B(__pTxDesc, __Value) SET_TX_DESC_P_AID(__pTxDesc, __Value)
-#define GET_TX_DESC_P_AID_8822B(__pTxDesc) GET_TX_DESC_P_AID(__pTxDesc)
+#define SET_TX_DESC_HW_AES_IV_8822B(txdesc, value) \
+ SET_TX_DESC_HW_AES_IV(txdesc, value)
+#define GET_TX_DESC_HW_AES_IV_8822B(txdesc) GET_TX_DESC_HW_AES_IV(txdesc)
+#define SET_TX_DESC_FTM_EN_8822B(txdesc, value) \
+ SET_TX_DESC_FTM_EN(txdesc, value)
+#define GET_TX_DESC_FTM_EN_8822B(txdesc) GET_TX_DESC_FTM_EN(txdesc)
+#define SET_TX_DESC_G_ID_8822B(txdesc, value) SET_TX_DESC_G_ID(txdesc, value)
+#define GET_TX_DESC_G_ID_8822B(txdesc) GET_TX_DESC_G_ID(txdesc)
+#define SET_TX_DESC_BT_NULL_8822B(txdesc, value) \
+ SET_TX_DESC_BT_NULL(txdesc, value)
+#define GET_TX_DESC_BT_NULL_8822B(txdesc) GET_TX_DESC_BT_NULL(txdesc)
+#define SET_TX_DESC_AMPDU_DENSITY_8822B(txdesc, value) \
+ SET_TX_DESC_AMPDU_DENSITY(txdesc, value)
+#define GET_TX_DESC_AMPDU_DENSITY_8822B(txdesc) \
+ GET_TX_DESC_AMPDU_DENSITY(txdesc)
+#define SET_TX_DESC_SPE_RPT_8822B(txdesc, value) \
+ SET_TX_DESC_SPE_RPT(txdesc, value)
+#define GET_TX_DESC_SPE_RPT_8822B(txdesc) GET_TX_DESC_SPE_RPT(txdesc)
+#define SET_TX_DESC_RAW_8822B(txdesc, value) SET_TX_DESC_RAW(txdesc, value)
+#define GET_TX_DESC_RAW_8822B(txdesc) GET_TX_DESC_RAW(txdesc)
+#define SET_TX_DESC_MOREFRAG_8822B(txdesc, value) \
+ SET_TX_DESC_MOREFRAG(txdesc, value)
+#define GET_TX_DESC_MOREFRAG_8822B(txdesc) GET_TX_DESC_MOREFRAG(txdesc)
+#define SET_TX_DESC_BK_8822B(txdesc, value) SET_TX_DESC_BK(txdesc, value)
+#define GET_TX_DESC_BK_8822B(txdesc) GET_TX_DESC_BK(txdesc)
+#define SET_TX_DESC_NULL_1_8822B(txdesc, value) \
+ SET_TX_DESC_NULL_1(txdesc, value)
+#define GET_TX_DESC_NULL_1_8822B(txdesc) GET_TX_DESC_NULL_1(txdesc)
+#define SET_TX_DESC_NULL_0_8822B(txdesc, value) \
+ SET_TX_DESC_NULL_0(txdesc, value)
+#define GET_TX_DESC_NULL_0_8822B(txdesc) GET_TX_DESC_NULL_0(txdesc)
+#define SET_TX_DESC_RDG_EN_8822B(txdesc, value) \
+ SET_TX_DESC_RDG_EN(txdesc, value)
+#define GET_TX_DESC_RDG_EN_8822B(txdesc) GET_TX_DESC_RDG_EN(txdesc)
+#define SET_TX_DESC_AGG_EN_8822B(txdesc, value) \
+ SET_TX_DESC_AGG_EN(txdesc, value)
+#define GET_TX_DESC_AGG_EN_8822B(txdesc) GET_TX_DESC_AGG_EN(txdesc)
+#define SET_TX_DESC_CCA_RTS_8822B(txdesc, value) \
+ SET_TX_DESC_CCA_RTS(txdesc, value)
+#define GET_TX_DESC_CCA_RTS_8822B(txdesc) GET_TX_DESC_CCA_RTS(txdesc)
+#define SET_TX_DESC_TRI_FRAME_8822B(txdesc, value) \
+ SET_TX_DESC_TRI_FRAME(txdesc, value)
+#define GET_TX_DESC_TRI_FRAME_8822B(txdesc) GET_TX_DESC_TRI_FRAME(txdesc)
+#define SET_TX_DESC_P_AID_8822B(txdesc, value) SET_TX_DESC_P_AID(txdesc, value)
+#define GET_TX_DESC_P_AID_8822B(txdesc) GET_TX_DESC_P_AID(txdesc)
/*TXDESC_WORD3*/
-#define SET_TX_DESC_AMPDU_MAX_TIME_8822B(__pTxDesc, __Value) SET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc, __Value)
-#define GET_TX_DESC_AMPDU_MAX_TIME_8822B(__pTxDesc) GET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc)
-#define SET_TX_DESC_NDPA_8822B(__pTxDesc, __Value) SET_TX_DESC_NDPA(__pTxDesc, __Value)
-#define GET_TX_DESC_NDPA_8822B(__pTxDesc) GET_TX_DESC_NDPA(__pTxDesc)
-#define SET_TX_DESC_MAX_AGG_NUM_8822B(__pTxDesc, __Value) SET_TX_DESC_MAX_AGG_NUM(__pTxDesc, __Value)
-#define GET_TX_DESC_MAX_AGG_NUM_8822B(__pTxDesc) GET_TX_DESC_MAX_AGG_NUM(__pTxDesc)
-#define SET_TX_DESC_USE_MAX_TIME_EN_8822B(__pTxDesc, __Value) SET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_USE_MAX_TIME_EN_8822B(__pTxDesc) GET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc)
-#define SET_TX_DESC_NAVUSEHDR_8822B(__pTxDesc, __Value) SET_TX_DESC_NAVUSEHDR(__pTxDesc, __Value)
-#define GET_TX_DESC_NAVUSEHDR_8822B(__pTxDesc) GET_TX_DESC_NAVUSEHDR(__pTxDesc)
-#define SET_TX_DESC_CHK_EN_8822B(__pTxDesc, __Value) SET_TX_DESC_CHK_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_CHK_EN_8822B(__pTxDesc) GET_TX_DESC_CHK_EN(__pTxDesc)
-#define SET_TX_DESC_HW_RTS_EN_8822B(__pTxDesc, __Value) SET_TX_DESC_HW_RTS_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_HW_RTS_EN_8822B(__pTxDesc) GET_TX_DESC_HW_RTS_EN(__pTxDesc)
-#define SET_TX_DESC_RTSEN_8822B(__pTxDesc, __Value) SET_TX_DESC_RTSEN(__pTxDesc, __Value)
-#define GET_TX_DESC_RTSEN_8822B(__pTxDesc) GET_TX_DESC_RTSEN(__pTxDesc)
-#define SET_TX_DESC_CTS2SELF_8822B(__pTxDesc, __Value) SET_TX_DESC_CTS2SELF(__pTxDesc, __Value)
-#define GET_TX_DESC_CTS2SELF_8822B(__pTxDesc) GET_TX_DESC_CTS2SELF(__pTxDesc)
-#define SET_TX_DESC_DISDATAFB_8822B(__pTxDesc, __Value) SET_TX_DESC_DISDATAFB(__pTxDesc, __Value)
-#define GET_TX_DESC_DISDATAFB_8822B(__pTxDesc) GET_TX_DESC_DISDATAFB(__pTxDesc)
-#define SET_TX_DESC_DISRTSFB_8822B(__pTxDesc, __Value) SET_TX_DESC_DISRTSFB(__pTxDesc, __Value)
-#define GET_TX_DESC_DISRTSFB_8822B(__pTxDesc) GET_TX_DESC_DISRTSFB(__pTxDesc)
-#define SET_TX_DESC_USE_RATE_8822B(__pTxDesc, __Value) SET_TX_DESC_USE_RATE(__pTxDesc, __Value)
-#define GET_TX_DESC_USE_RATE_8822B(__pTxDesc) GET_TX_DESC_USE_RATE(__pTxDesc)
-#define SET_TX_DESC_HW_SSN_SEL_8822B(__pTxDesc, __Value) SET_TX_DESC_HW_SSN_SEL(__pTxDesc, __Value)
-#define GET_TX_DESC_HW_SSN_SEL_8822B(__pTxDesc) GET_TX_DESC_HW_SSN_SEL(__pTxDesc)
-#define SET_TX_DESC_WHEADER_LEN_8822B(__pTxDesc, __Value) SET_TX_DESC_WHEADER_LEN(__pTxDesc, __Value)
-#define GET_TX_DESC_WHEADER_LEN_8822B(__pTxDesc) GET_TX_DESC_WHEADER_LEN(__pTxDesc)
+#define SET_TX_DESC_AMPDU_MAX_TIME_8822B(txdesc, value) \
+ SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value)
+#define GET_TX_DESC_AMPDU_MAX_TIME_8822B(txdesc) \
+ GET_TX_DESC_AMPDU_MAX_TIME(txdesc)
+#define SET_TX_DESC_NDPA_8822B(txdesc, value) SET_TX_DESC_NDPA(txdesc, value)
+#define GET_TX_DESC_NDPA_8822B(txdesc) GET_TX_DESC_NDPA(txdesc)
+#define SET_TX_DESC_MAX_AGG_NUM_8822B(txdesc, value) \
+ SET_TX_DESC_MAX_AGG_NUM(txdesc, value)
+#define GET_TX_DESC_MAX_AGG_NUM_8822B(txdesc) GET_TX_DESC_MAX_AGG_NUM(txdesc)
+#define SET_TX_DESC_USE_MAX_TIME_EN_8822B(txdesc, value) \
+ SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value)
+#define GET_TX_DESC_USE_MAX_TIME_EN_8822B(txdesc) \
+ GET_TX_DESC_USE_MAX_TIME_EN(txdesc)
+#define SET_TX_DESC_NAVUSEHDR_8822B(txdesc, value) \
+ SET_TX_DESC_NAVUSEHDR(txdesc, value)
+#define GET_TX_DESC_NAVUSEHDR_8822B(txdesc) GET_TX_DESC_NAVUSEHDR(txdesc)
+#define SET_TX_DESC_CHK_EN_8822B(txdesc, value) \
+ SET_TX_DESC_CHK_EN(txdesc, value)
+#define GET_TX_DESC_CHK_EN_8822B(txdesc) GET_TX_DESC_CHK_EN(txdesc)
+#define SET_TX_DESC_HW_RTS_EN_8822B(txdesc, value) \
+ SET_TX_DESC_HW_RTS_EN(txdesc, value)
+#define GET_TX_DESC_HW_RTS_EN_8822B(txdesc) GET_TX_DESC_HW_RTS_EN(txdesc)
+#define SET_TX_DESC_RTSEN_8822B(txdesc, value) SET_TX_DESC_RTSEN(txdesc, value)
+#define GET_TX_DESC_RTSEN_8822B(txdesc) GET_TX_DESC_RTSEN(txdesc)
+#define SET_TX_DESC_CTS2SELF_8822B(txdesc, value) \
+ SET_TX_DESC_CTS2SELF(txdesc, value)
+#define GET_TX_DESC_CTS2SELF_8822B(txdesc) GET_TX_DESC_CTS2SELF(txdesc)
+#define SET_TX_DESC_DISDATAFB_8822B(txdesc, value) \
+ SET_TX_DESC_DISDATAFB(txdesc, value)
+#define GET_TX_DESC_DISDATAFB_8822B(txdesc) GET_TX_DESC_DISDATAFB(txdesc)
+#define SET_TX_DESC_DISRTSFB_8822B(txdesc, value) \
+ SET_TX_DESC_DISRTSFB(txdesc, value)
+#define GET_TX_DESC_DISRTSFB_8822B(txdesc) GET_TX_DESC_DISRTSFB(txdesc)
+#define SET_TX_DESC_USE_RATE_8822B(txdesc, value) \
+ SET_TX_DESC_USE_RATE(txdesc, value)
+#define GET_TX_DESC_USE_RATE_8822B(txdesc) GET_TX_DESC_USE_RATE(txdesc)
+#define SET_TX_DESC_HW_SSN_SEL_8822B(txdesc, value) \
+ SET_TX_DESC_HW_SSN_SEL(txdesc, value)
+#define GET_TX_DESC_HW_SSN_SEL_8822B(txdesc) GET_TX_DESC_HW_SSN_SEL(txdesc)
+#define SET_TX_DESC_WHEADER_LEN_8822B(txdesc, value) \
+ SET_TX_DESC_WHEADER_LEN(txdesc, value)
+#define GET_TX_DESC_WHEADER_LEN_8822B(txdesc) GET_TX_DESC_WHEADER_LEN(txdesc)
/*TXDESC_WORD4*/
-#define SET_TX_DESC_PCTS_MASK_IDX_8822B(__pTxDesc, __Value) SET_TX_DESC_PCTS_MASK_IDX(__pTxDesc, __Value)
-#define GET_TX_DESC_PCTS_MASK_IDX_8822B(__pTxDesc) GET_TX_DESC_PCTS_MASK_IDX(__pTxDesc)
-#define SET_TX_DESC_PCTS_EN_8822B(__pTxDesc, __Value) SET_TX_DESC_PCTS_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_PCTS_EN_8822B(__pTxDesc) GET_TX_DESC_PCTS_EN(__pTxDesc)
-#define SET_TX_DESC_RTSRATE_8822B(__pTxDesc, __Value) SET_TX_DESC_RTSRATE(__pTxDesc, __Value)
-#define GET_TX_DESC_RTSRATE_8822B(__pTxDesc) GET_TX_DESC_RTSRATE(__pTxDesc)
-#define SET_TX_DESC_RTS_DATA_RTY_LMT_8822B(__pTxDesc, __Value) SET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc, __Value)
-#define GET_TX_DESC_RTS_DATA_RTY_LMT_8822B(__pTxDesc) GET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc)
-#define SET_TX_DESC_RTY_LMT_EN_8822B(__pTxDesc, __Value) SET_TX_DESC_RTY_LMT_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_RTY_LMT_EN_8822B(__pTxDesc) GET_TX_DESC_RTY_LMT_EN(__pTxDesc)
-#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8822B(__pTxDesc, __Value) SET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc, __Value)
-#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8822B(__pTxDesc) GET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc)
-#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8822B(__pTxDesc, __Value) SET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc, __Value)
-#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8822B(__pTxDesc) GET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc)
-#define SET_TX_DESC_TRY_RATE_8822B(__pTxDesc, __Value) SET_TX_DESC_TRY_RATE(__pTxDesc, __Value)
-#define GET_TX_DESC_TRY_RATE_8822B(__pTxDesc) GET_TX_DESC_TRY_RATE(__pTxDesc)
-#define SET_TX_DESC_DATARATE_8822B(__pTxDesc, __Value) SET_TX_DESC_DATARATE(__pTxDesc, __Value)
-#define GET_TX_DESC_DATARATE_8822B(__pTxDesc) GET_TX_DESC_DATARATE(__pTxDesc)
+#define SET_TX_DESC_PCTS_MASK_IDX_8822B(txdesc, value) \
+ SET_TX_DESC_PCTS_MASK_IDX(txdesc, value)
+#define GET_TX_DESC_PCTS_MASK_IDX_8822B(txdesc) \
+ GET_TX_DESC_PCTS_MASK_IDX(txdesc)
+#define SET_TX_DESC_PCTS_EN_8822B(txdesc, value) \
+ SET_TX_DESC_PCTS_EN(txdesc, value)
+#define GET_TX_DESC_PCTS_EN_8822B(txdesc) GET_TX_DESC_PCTS_EN(txdesc)
+#define SET_TX_DESC_RTSRATE_8822B(txdesc, value) \
+ SET_TX_DESC_RTSRATE(txdesc, value)
+#define GET_TX_DESC_RTSRATE_8822B(txdesc) GET_TX_DESC_RTSRATE(txdesc)
+#define SET_TX_DESC_RTS_DATA_RTY_LMT_8822B(txdesc, value) \
+ SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value)
+#define GET_TX_DESC_RTS_DATA_RTY_LMT_8822B(txdesc) \
+ GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc)
+#define SET_TX_DESC_RTY_LMT_EN_8822B(txdesc, value) \
+ SET_TX_DESC_RTY_LMT_EN(txdesc, value)
+#define GET_TX_DESC_RTY_LMT_EN_8822B(txdesc) GET_TX_DESC_RTY_LMT_EN(txdesc)
+#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8822B(txdesc, value) \
+ SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value)
+#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8822B(txdesc) \
+ GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc)
+#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8822B(txdesc, value) \
+ SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value)
+#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8822B(txdesc) \
+ GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc)
+#define SET_TX_DESC_TRY_RATE_8822B(txdesc, value) \
+ SET_TX_DESC_TRY_RATE(txdesc, value)
+#define GET_TX_DESC_TRY_RATE_8822B(txdesc) GET_TX_DESC_TRY_RATE(txdesc)
+#define SET_TX_DESC_DATARATE_8822B(txdesc, value) \
+ SET_TX_DESC_DATARATE(txdesc, value)
+#define GET_TX_DESC_DATARATE_8822B(txdesc) GET_TX_DESC_DATARATE(txdesc)
/*TXDESC_WORD5*/
-#define SET_TX_DESC_POLLUTED_8822B(__pTxDesc, __Value) SET_TX_DESC_POLLUTED(__pTxDesc, __Value)
-#define GET_TX_DESC_POLLUTED_8822B(__pTxDesc) GET_TX_DESC_POLLUTED(__pTxDesc)
-#define SET_TX_DESC_TXPWR_OFSET_8822B(__pTxDesc, __Value) SET_TX_DESC_TXPWR_OFSET(__pTxDesc, __Value)
-#define GET_TX_DESC_TXPWR_OFSET_8822B(__pTxDesc) GET_TX_DESC_TXPWR_OFSET(__pTxDesc)
-#define SET_TX_DESC_TX_ANT_8822B(__pTxDesc, __Value) SET_TX_DESC_TX_ANT(__pTxDesc, __Value)
-#define GET_TX_DESC_TX_ANT_8822B(__pTxDesc) GET_TX_DESC_TX_ANT(__pTxDesc)
-#define SET_TX_DESC_PORT_ID_8822B(__pTxDesc, __Value) SET_TX_DESC_PORT_ID(__pTxDesc, __Value)
-#define GET_TX_DESC_PORT_ID_8822B(__pTxDesc) GET_TX_DESC_PORT_ID(__pTxDesc)
-#define SET_TX_DESC_MULTIPLE_PORT_8822B(__pTxDesc, __Value) SET_TX_DESC_MULTIPLE_PORT(__pTxDesc, __Value)
-#define GET_TX_DESC_MULTIPLE_PORT_8822B(__pTxDesc) GET_TX_DESC_MULTIPLE_PORT(__pTxDesc)
-#define SET_TX_DESC_SIGNALING_TAPKT_EN_8822B(__pTxDesc, __Value) SET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_SIGNALING_TAPKT_EN_8822B(__pTxDesc) GET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc)
-#define SET_TX_DESC_RTS_SC_8822B(__pTxDesc, __Value) SET_TX_DESC_RTS_SC(__pTxDesc, __Value)
-#define GET_TX_DESC_RTS_SC_8822B(__pTxDesc) GET_TX_DESC_RTS_SC(__pTxDesc)
-#define SET_TX_DESC_RTS_SHORT_8822B(__pTxDesc, __Value) SET_TX_DESC_RTS_SHORT(__pTxDesc, __Value)
-#define GET_TX_DESC_RTS_SHORT_8822B(__pTxDesc) GET_TX_DESC_RTS_SHORT(__pTxDesc)
-#define SET_TX_DESC_VCS_STBC_8822B(__pTxDesc, __Value) SET_TX_DESC_VCS_STBC(__pTxDesc, __Value)
-#define GET_TX_DESC_VCS_STBC_8822B(__pTxDesc) GET_TX_DESC_VCS_STBC(__pTxDesc)
-#define SET_TX_DESC_DATA_STBC_8822B(__pTxDesc, __Value) SET_TX_DESC_DATA_STBC(__pTxDesc, __Value)
-#define GET_TX_DESC_DATA_STBC_8822B(__pTxDesc) GET_TX_DESC_DATA_STBC(__pTxDesc)
-#define SET_TX_DESC_DATA_LDPC_8822B(__pTxDesc, __Value) SET_TX_DESC_DATA_LDPC(__pTxDesc, __Value)
-#define GET_TX_DESC_DATA_LDPC_8822B(__pTxDesc) GET_TX_DESC_DATA_LDPC(__pTxDesc)
-#define SET_TX_DESC_DATA_BW_8822B(__pTxDesc, __Value) SET_TX_DESC_DATA_BW(__pTxDesc, __Value)
-#define GET_TX_DESC_DATA_BW_8822B(__pTxDesc) GET_TX_DESC_DATA_BW(__pTxDesc)
-#define SET_TX_DESC_DATA_SHORT_8822B(__pTxDesc, __Value) SET_TX_DESC_DATA_SHORT(__pTxDesc, __Value)
-#define GET_TX_DESC_DATA_SHORT_8822B(__pTxDesc) GET_TX_DESC_DATA_SHORT(__pTxDesc)
-#define SET_TX_DESC_DATA_SC_8822B(__pTxDesc, __Value) SET_TX_DESC_DATA_SC(__pTxDesc, __Value)
-#define GET_TX_DESC_DATA_SC_8822B(__pTxDesc) GET_TX_DESC_DATA_SC(__pTxDesc)
+#define SET_TX_DESC_POLLUTED_8822B(txdesc, value) \
+ SET_TX_DESC_POLLUTED(txdesc, value)
+#define GET_TX_DESC_POLLUTED_8822B(txdesc) GET_TX_DESC_POLLUTED(txdesc)
+#define SET_TX_DESC_TXPWR_OFSET_8822B(txdesc, value) \
+ SET_TX_DESC_TXPWR_OFSET(txdesc, value)
+#define GET_TX_DESC_TXPWR_OFSET_8822B(txdesc) GET_TX_DESC_TXPWR_OFSET(txdesc)
+#define SET_TX_DESC_TX_ANT_8822B(txdesc, value) \
+ SET_TX_DESC_TX_ANT(txdesc, value)
+#define GET_TX_DESC_TX_ANT_8822B(txdesc) GET_TX_DESC_TX_ANT(txdesc)
+#define SET_TX_DESC_PORT_ID_8822B(txdesc, value) \
+ SET_TX_DESC_PORT_ID(txdesc, value)
+#define GET_TX_DESC_PORT_ID_8822B(txdesc) GET_TX_DESC_PORT_ID(txdesc)
+#define SET_TX_DESC_MULTIPLE_PORT_8822B(txdesc, value) \
+ SET_TX_DESC_MULTIPLE_PORT(txdesc, value)
+#define GET_TX_DESC_MULTIPLE_PORT_8822B(txdesc) \
+ GET_TX_DESC_MULTIPLE_PORT(txdesc)
+#define SET_TX_DESC_SIGNALING_TAPKT_EN_8822B(txdesc, value) \
+ SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value)
+#define GET_TX_DESC_SIGNALING_TAPKT_EN_8822B(txdesc) \
+ GET_TX_DESC_SIGNALING_TAPKT_EN(txdesc)
+#define SET_TX_DESC_SIGNALING_TA_PKT_SC_8822B(txdesc, value) \
+ SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc, value)
+#define GET_TX_DESC_SIGNALING_TA_PKT_SC_8822B(txdesc) \
+ GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc)
+#define SET_TX_DESC_RTS_SHORT_8822B(txdesc, value) \
+ SET_TX_DESC_RTS_SHORT(txdesc, value)
+#define GET_TX_DESC_RTS_SHORT_8822B(txdesc) GET_TX_DESC_RTS_SHORT(txdesc)
+#define SET_TX_DESC_VCS_STBC_8822B(txdesc, value) \
+ SET_TX_DESC_VCS_STBC(txdesc, value)
+#define GET_TX_DESC_VCS_STBC_8822B(txdesc) GET_TX_DESC_VCS_STBC(txdesc)
+#define SET_TX_DESC_DATA_STBC_8822B(txdesc, value) \
+ SET_TX_DESC_DATA_STBC(txdesc, value)
+#define GET_TX_DESC_DATA_STBC_8822B(txdesc) GET_TX_DESC_DATA_STBC(txdesc)
+#define SET_TX_DESC_DATA_LDPC_8822B(txdesc, value) \
+ SET_TX_DESC_DATA_LDPC(txdesc, value)
+#define GET_TX_DESC_DATA_LDPC_8822B(txdesc) GET_TX_DESC_DATA_LDPC(txdesc)
+#define SET_TX_DESC_DATA_BW_8822B(txdesc, value) \
+ SET_TX_DESC_DATA_BW(txdesc, value)
+#define GET_TX_DESC_DATA_BW_8822B(txdesc) GET_TX_DESC_DATA_BW(txdesc)
+#define SET_TX_DESC_DATA_SHORT_8822B(txdesc, value) \
+ SET_TX_DESC_DATA_SHORT(txdesc, value)
+#define GET_TX_DESC_DATA_SHORT_8822B(txdesc) GET_TX_DESC_DATA_SHORT(txdesc)
+#define SET_TX_DESC_DATA_SC_8822B(txdesc, value) \
+ SET_TX_DESC_DATA_SC(txdesc, value)
+#define GET_TX_DESC_DATA_SC_8822B(txdesc) GET_TX_DESC_DATA_SC(txdesc)
/*TXDESC_WORD6*/
-#define SET_TX_DESC_ANTSEL_D_8822B(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_D(__pTxDesc, __Value)
-#define GET_TX_DESC_ANTSEL_D_8822B(__pTxDesc) GET_TX_DESC_ANTSEL_D(__pTxDesc)
-#define SET_TX_DESC_ANT_MAPD_8822B(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPD(__pTxDesc, __Value)
-#define GET_TX_DESC_ANT_MAPD_8822B(__pTxDesc) GET_TX_DESC_ANT_MAPD(__pTxDesc)
-#define SET_TX_DESC_ANT_MAPC_8822B(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPC(__pTxDesc, __Value)
-#define GET_TX_DESC_ANT_MAPC_8822B(__pTxDesc) GET_TX_DESC_ANT_MAPC(__pTxDesc)
-#define SET_TX_DESC_ANT_MAPB_8822B(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPB(__pTxDesc, __Value)
-#define GET_TX_DESC_ANT_MAPB_8822B(__pTxDesc) GET_TX_DESC_ANT_MAPB(__pTxDesc)
-#define SET_TX_DESC_ANT_MAPA_8822B(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPA(__pTxDesc, __Value)
-#define GET_TX_DESC_ANT_MAPA_8822B(__pTxDesc) GET_TX_DESC_ANT_MAPA(__pTxDesc)
-#define SET_TX_DESC_ANTSEL_C_8822B(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_C(__pTxDesc, __Value)
-#define GET_TX_DESC_ANTSEL_C_8822B(__pTxDesc) GET_TX_DESC_ANTSEL_C(__pTxDesc)
-#define SET_TX_DESC_ANTSEL_B_8822B(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_B(__pTxDesc, __Value)
-#define GET_TX_DESC_ANTSEL_B_8822B(__pTxDesc) GET_TX_DESC_ANTSEL_B(__pTxDesc)
-#define SET_TX_DESC_ANTSEL_A_8822B(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_A(__pTxDesc, __Value)
-#define GET_TX_DESC_ANTSEL_A_8822B(__pTxDesc) GET_TX_DESC_ANTSEL_A(__pTxDesc)
-#define SET_TX_DESC_MBSSID_8822B(__pTxDesc, __Value) SET_TX_DESC_MBSSID(__pTxDesc, __Value)
-#define GET_TX_DESC_MBSSID_8822B(__pTxDesc) GET_TX_DESC_MBSSID(__pTxDesc)
-#define SET_TX_DESC_SW_DEFINE_8822B(__pTxDesc, __Value) SET_TX_DESC_SW_DEFINE(__pTxDesc, __Value)
-#define GET_TX_DESC_SW_DEFINE_8822B(__pTxDesc) GET_TX_DESC_SW_DEFINE(__pTxDesc)
+#define SET_TX_DESC_ANTSEL_D_8822B(txdesc, value) \
+ SET_TX_DESC_ANTSEL_D(txdesc, value)
+#define GET_TX_DESC_ANTSEL_D_8822B(txdesc) GET_TX_DESC_ANTSEL_D(txdesc)
+#define SET_TX_DESC_ANT_MAPD_8822B(txdesc, value) \
+ SET_TX_DESC_ANT_MAPD(txdesc, value)
+#define GET_TX_DESC_ANT_MAPD_8822B(txdesc) GET_TX_DESC_ANT_MAPD(txdesc)
+#define SET_TX_DESC_ANT_MAPC_8822B(txdesc, value) \
+ SET_TX_DESC_ANT_MAPC(txdesc, value)
+#define GET_TX_DESC_ANT_MAPC_8822B(txdesc) GET_TX_DESC_ANT_MAPC(txdesc)
+#define SET_TX_DESC_ANT_MAPB_8822B(txdesc, value) \
+ SET_TX_DESC_ANT_MAPB(txdesc, value)
+#define GET_TX_DESC_ANT_MAPB_8822B(txdesc) GET_TX_DESC_ANT_MAPB(txdesc)
+#define SET_TX_DESC_ANT_MAPA_8822B(txdesc, value) \
+ SET_TX_DESC_ANT_MAPA(txdesc, value)
+#define GET_TX_DESC_ANT_MAPA_8822B(txdesc) GET_TX_DESC_ANT_MAPA(txdesc)
+#define SET_TX_DESC_ANTSEL_C_8822B(txdesc, value) \
+ SET_TX_DESC_ANTSEL_C(txdesc, value)
+#define GET_TX_DESC_ANTSEL_C_8822B(txdesc) GET_TX_DESC_ANTSEL_C(txdesc)
+#define SET_TX_DESC_ANTSEL_B_8822B(txdesc, value) \
+ SET_TX_DESC_ANTSEL_B(txdesc, value)
+#define GET_TX_DESC_ANTSEL_B_8822B(txdesc) GET_TX_DESC_ANTSEL_B(txdesc)
+#define SET_TX_DESC_ANTSEL_A_8822B(txdesc, value) \
+ SET_TX_DESC_ANTSEL_A(txdesc, value)
+#define GET_TX_DESC_ANTSEL_A_8822B(txdesc) GET_TX_DESC_ANTSEL_A(txdesc)
+#define SET_TX_DESC_MBSSID_8822B(txdesc, value) \
+ SET_TX_DESC_MBSSID(txdesc, value)
+#define GET_TX_DESC_MBSSID_8822B(txdesc) GET_TX_DESC_MBSSID(txdesc)
+#define SET_TX_DESC_SW_DEFINE_8822B(txdesc, value) \
+ SET_TX_DESC_SW_DEFINE(txdesc, value)
+#define GET_TX_DESC_SW_DEFINE_8822B(txdesc) GET_TX_DESC_SW_DEFINE(txdesc)
/*TXDESC_WORD7*/
-#define SET_TX_DESC_DMA_TXAGG_NUM_8822B(__pTxDesc, __Value) SET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc, __Value)
-#define GET_TX_DESC_DMA_TXAGG_NUM_8822B(__pTxDesc) GET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc)
-#define SET_TX_DESC_FINAL_DATA_RATE_8822B(__pTxDesc, __Value) SET_TX_DESC_FINAL_DATA_RATE(__pTxDesc, __Value)
-#define GET_TX_DESC_FINAL_DATA_RATE_8822B(__pTxDesc) GET_TX_DESC_FINAL_DATA_RATE(__pTxDesc)
-#define SET_TX_DESC_NTX_MAP_8822B(__pTxDesc, __Value) SET_TX_DESC_NTX_MAP(__pTxDesc, __Value)
-#define GET_TX_DESC_NTX_MAP_8822B(__pTxDesc) GET_TX_DESC_NTX_MAP(__pTxDesc)
-#define SET_TX_DESC_TX_BUFF_SIZE_8822B(__pTxDesc, __Value) SET_TX_DESC_TX_BUFF_SIZE(__pTxDesc, __Value)
-#define GET_TX_DESC_TX_BUFF_SIZE_8822B(__pTxDesc) GET_TX_DESC_TX_BUFF_SIZE(__pTxDesc)
-#define SET_TX_DESC_TXDESC_CHECKSUM_8822B(__pTxDesc, __Value) SET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc, __Value)
-#define GET_TX_DESC_TXDESC_CHECKSUM_8822B(__pTxDesc) GET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc)
-#define SET_TX_DESC_TIMESTAMP_8822B(__pTxDesc, __Value) SET_TX_DESC_TIMESTAMP(__pTxDesc, __Value)
-#define GET_TX_DESC_TIMESTAMP_8822B(__pTxDesc) GET_TX_DESC_TIMESTAMP(__pTxDesc)
+#define SET_TX_DESC_DMA_TXAGG_NUM_8822B(txdesc, value) \
+ SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value)
+#define GET_TX_DESC_DMA_TXAGG_NUM_8822B(txdesc) \
+ GET_TX_DESC_DMA_TXAGG_NUM(txdesc)
+#define SET_TX_DESC_FINAL_DATA_RATE_8822B(txdesc, value) \
+ SET_TX_DESC_FINAL_DATA_RATE(txdesc, value)
+#define GET_TX_DESC_FINAL_DATA_RATE_8822B(txdesc) \
+ GET_TX_DESC_FINAL_DATA_RATE(txdesc)
+#define SET_TX_DESC_NTX_MAP_8822B(txdesc, value) \
+ SET_TX_DESC_NTX_MAP(txdesc, value)
+#define GET_TX_DESC_NTX_MAP_8822B(txdesc) GET_TX_DESC_NTX_MAP(txdesc)
+#define SET_TX_DESC_TX_BUFF_SIZE_8822B(txdesc, value) \
+ SET_TX_DESC_TX_BUFF_SIZE(txdesc, value)
+#define GET_TX_DESC_TX_BUFF_SIZE_8822B(txdesc) GET_TX_DESC_TX_BUFF_SIZE(txdesc)
+#define SET_TX_DESC_TXDESC_CHECKSUM_8822B(txdesc, value) \
+ SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value)
+#define GET_TX_DESC_TXDESC_CHECKSUM_8822B(txdesc) \
+ GET_TX_DESC_TXDESC_CHECKSUM(txdesc)
+#define SET_TX_DESC_TIMESTAMP_8822B(txdesc, value) \
+ SET_TX_DESC_TIMESTAMP(txdesc, value)
+#define GET_TX_DESC_TIMESTAMP_8822B(txdesc) GET_TX_DESC_TIMESTAMP(txdesc)
/*TXDESC_WORD8*/
-#define SET_TX_DESC_TXWIFI_CP_8822B(__pTxDesc, __Value) SET_TX_DESC_TXWIFI_CP(__pTxDesc, __Value)
-#define GET_TX_DESC_TXWIFI_CP_8822B(__pTxDesc) GET_TX_DESC_TXWIFI_CP(__pTxDesc)
-#define SET_TX_DESC_MAC_CP_8822B(__pTxDesc, __Value) SET_TX_DESC_MAC_CP(__pTxDesc, __Value)
-#define GET_TX_DESC_MAC_CP_8822B(__pTxDesc) GET_TX_DESC_MAC_CP(__pTxDesc)
-#define SET_TX_DESC_STW_PKTRE_DIS_8822B(__pTxDesc, __Value) SET_TX_DESC_STW_PKTRE_DIS(__pTxDesc, __Value)
-#define GET_TX_DESC_STW_PKTRE_DIS_8822B(__pTxDesc) GET_TX_DESC_STW_PKTRE_DIS(__pTxDesc)
-#define SET_TX_DESC_STW_RB_DIS_8822B(__pTxDesc, __Value) SET_TX_DESC_STW_RB_DIS(__pTxDesc, __Value)
-#define GET_TX_DESC_STW_RB_DIS_8822B(__pTxDesc) GET_TX_DESC_STW_RB_DIS(__pTxDesc)
-#define SET_TX_DESC_STW_RATE_DIS_8822B(__pTxDesc, __Value) SET_TX_DESC_STW_RATE_DIS(__pTxDesc, __Value)
-#define GET_TX_DESC_STW_RATE_DIS_8822B(__pTxDesc) GET_TX_DESC_STW_RATE_DIS(__pTxDesc)
-#define SET_TX_DESC_STW_ANT_DIS_8822B(__pTxDesc, __Value) SET_TX_DESC_STW_ANT_DIS(__pTxDesc, __Value)
-#define GET_TX_DESC_STW_ANT_DIS_8822B(__pTxDesc) GET_TX_DESC_STW_ANT_DIS(__pTxDesc)
-#define SET_TX_DESC_STW_EN_8822B(__pTxDesc, __Value) SET_TX_DESC_STW_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_STW_EN_8822B(__pTxDesc) GET_TX_DESC_STW_EN(__pTxDesc)
-#define SET_TX_DESC_SMH_EN_8822B(__pTxDesc, __Value) SET_TX_DESC_SMH_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_SMH_EN_8822B(__pTxDesc) GET_TX_DESC_SMH_EN(__pTxDesc)
-#define SET_TX_DESC_TAILPAGE_L_8822B(__pTxDesc, __Value) SET_TX_DESC_TAILPAGE_L(__pTxDesc, __Value)
-#define GET_TX_DESC_TAILPAGE_L_8822B(__pTxDesc) GET_TX_DESC_TAILPAGE_L(__pTxDesc)
-#define SET_TX_DESC_SDIO_DMASEQ_8822B(__pTxDesc, __Value) SET_TX_DESC_SDIO_DMASEQ(__pTxDesc, __Value)
-#define GET_TX_DESC_SDIO_DMASEQ_8822B(__pTxDesc) GET_TX_DESC_SDIO_DMASEQ(__pTxDesc)
-#define SET_TX_DESC_NEXTHEADPAGE_L_8822B(__pTxDesc, __Value) SET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc, __Value)
-#define GET_TX_DESC_NEXTHEADPAGE_L_8822B(__pTxDesc) GET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc)
-#define SET_TX_DESC_EN_HWSEQ_8822B(__pTxDesc, __Value) SET_TX_DESC_EN_HWSEQ(__pTxDesc, __Value)
-#define GET_TX_DESC_EN_HWSEQ_8822B(__pTxDesc) GET_TX_DESC_EN_HWSEQ(__pTxDesc)
-#define SET_TX_DESC_EN_HWEXSEQ_8822B(__pTxDesc, __Value) SET_TX_DESC_EN_HWEXSEQ(__pTxDesc, __Value)
-#define GET_TX_DESC_EN_HWEXSEQ_8822B(__pTxDesc) GET_TX_DESC_EN_HWEXSEQ(__pTxDesc)
-#define SET_TX_DESC_DATA_RC_8822B(__pTxDesc, __Value) SET_TX_DESC_DATA_RC(__pTxDesc, __Value)
-#define GET_TX_DESC_DATA_RC_8822B(__pTxDesc) GET_TX_DESC_DATA_RC(__pTxDesc)
-#define SET_TX_DESC_BAR_RTY_TH_8822B(__pTxDesc, __Value) SET_TX_DESC_BAR_RTY_TH(__pTxDesc, __Value)
-#define GET_TX_DESC_BAR_RTY_TH_8822B(__pTxDesc) GET_TX_DESC_BAR_RTY_TH(__pTxDesc)
-#define SET_TX_DESC_RTS_RC_8822B(__pTxDesc, __Value) SET_TX_DESC_RTS_RC(__pTxDesc, __Value)
-#define GET_TX_DESC_RTS_RC_8822B(__pTxDesc) GET_TX_DESC_RTS_RC(__pTxDesc)
+#define SET_TX_DESC_TXWIFI_CP_8822B(txdesc, value) \
+ SET_TX_DESC_TXWIFI_CP(txdesc, value)
+#define GET_TX_DESC_TXWIFI_CP_8822B(txdesc) GET_TX_DESC_TXWIFI_CP(txdesc)
+#define SET_TX_DESC_MAC_CP_8822B(txdesc, value) \
+ SET_TX_DESC_MAC_CP(txdesc, value)
+#define GET_TX_DESC_MAC_CP_8822B(txdesc) GET_TX_DESC_MAC_CP(txdesc)
+#define SET_TX_DESC_STW_PKTRE_DIS_8822B(txdesc, value) \
+ SET_TX_DESC_STW_PKTRE_DIS(txdesc, value)
+#define GET_TX_DESC_STW_PKTRE_DIS_8822B(txdesc) \
+ GET_TX_DESC_STW_PKTRE_DIS(txdesc)
+#define SET_TX_DESC_STW_RB_DIS_8822B(txdesc, value) \
+ SET_TX_DESC_STW_RB_DIS(txdesc, value)
+#define GET_TX_DESC_STW_RB_DIS_8822B(txdesc) GET_TX_DESC_STW_RB_DIS(txdesc)
+#define SET_TX_DESC_STW_RATE_DIS_8822B(txdesc, value) \
+ SET_TX_DESC_STW_RATE_DIS(txdesc, value)
+#define GET_TX_DESC_STW_RATE_DIS_8822B(txdesc) GET_TX_DESC_STW_RATE_DIS(txdesc)
+#define SET_TX_DESC_STW_ANT_DIS_8822B(txdesc, value) \
+ SET_TX_DESC_STW_ANT_DIS(txdesc, value)
+#define GET_TX_DESC_STW_ANT_DIS_8822B(txdesc) GET_TX_DESC_STW_ANT_DIS(txdesc)
+#define SET_TX_DESC_STW_EN_8822B(txdesc, value) \
+ SET_TX_DESC_STW_EN(txdesc, value)
+#define GET_TX_DESC_STW_EN_8822B(txdesc) GET_TX_DESC_STW_EN(txdesc)
+#define SET_TX_DESC_SMH_EN_8822B(txdesc, value) \
+ SET_TX_DESC_SMH_EN(txdesc, value)
+#define GET_TX_DESC_SMH_EN_8822B(txdesc) GET_TX_DESC_SMH_EN(txdesc)
+#define SET_TX_DESC_TAILPAGE_L_8822B(txdesc, value) \
+ SET_TX_DESC_TAILPAGE_L(txdesc, value)
+#define GET_TX_DESC_TAILPAGE_L_8822B(txdesc) GET_TX_DESC_TAILPAGE_L(txdesc)
+#define SET_TX_DESC_SDIO_DMASEQ_8822B(txdesc, value) \
+ SET_TX_DESC_SDIO_DMASEQ(txdesc, value)
+#define GET_TX_DESC_SDIO_DMASEQ_8822B(txdesc) GET_TX_DESC_SDIO_DMASEQ(txdesc)
+#define SET_TX_DESC_NEXTHEADPAGE_L_8822B(txdesc, value) \
+ SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value)
+#define GET_TX_DESC_NEXTHEADPAGE_L_8822B(txdesc) \
+ GET_TX_DESC_NEXTHEADPAGE_L(txdesc)
+#define SET_TX_DESC_EN_HWSEQ_8822B(txdesc, value) \
+ SET_TX_DESC_EN_HWSEQ(txdesc, value)
+#define GET_TX_DESC_EN_HWSEQ_8822B(txdesc) GET_TX_DESC_EN_HWSEQ(txdesc)
+#define SET_TX_DESC_EN_HWEXSEQ_8822B(txdesc, value) \
+ SET_TX_DESC_EN_HWEXSEQ(txdesc, value)
+#define GET_TX_DESC_EN_HWEXSEQ_8822B(txdesc) GET_TX_DESC_EN_HWEXSEQ(txdesc)
+#define SET_TX_DESC_DATA_RC_8822B(txdesc, value) \
+ SET_TX_DESC_DATA_RC(txdesc, value)
+#define GET_TX_DESC_DATA_RC_8822B(txdesc) GET_TX_DESC_DATA_RC(txdesc)
+#define SET_TX_DESC_BAR_RTY_TH_8822B(txdesc, value) \
+ SET_TX_DESC_BAR_RTY_TH(txdesc, value)
+#define GET_TX_DESC_BAR_RTY_TH_8822B(txdesc) GET_TX_DESC_BAR_RTY_TH(txdesc)
+#define SET_TX_DESC_RTS_RC_8822B(txdesc, value) \
+ SET_TX_DESC_RTS_RC(txdesc, value)
+#define GET_TX_DESC_RTS_RC_8822B(txdesc) GET_TX_DESC_RTS_RC(txdesc)
/*TXDESC_WORD9*/
-#define SET_TX_DESC_TAILPAGE_H_8822B(__pTxDesc, __Value) SET_TX_DESC_TAILPAGE_H(__pTxDesc, __Value)
-#define GET_TX_DESC_TAILPAGE_H_8822B(__pTxDesc) GET_TX_DESC_TAILPAGE_H(__pTxDesc)
-#define SET_TX_DESC_NEXTHEADPAGE_H_8822B(__pTxDesc, __Value) SET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc, __Value)
-#define GET_TX_DESC_NEXTHEADPAGE_H_8822B(__pTxDesc) GET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc)
-#define SET_TX_DESC_SW_SEQ_8822B(__pTxDesc, __Value) SET_TX_DESC_SW_SEQ(__pTxDesc, __Value)
-#define GET_TX_DESC_SW_SEQ_8822B(__pTxDesc) GET_TX_DESC_SW_SEQ(__pTxDesc)
-#define SET_TX_DESC_TXBF_PATH_8822B(__pTxDesc, __Value) SET_TX_DESC_TXBF_PATH(__pTxDesc, __Value)
-#define GET_TX_DESC_TXBF_PATH_8822B(__pTxDesc) GET_TX_DESC_TXBF_PATH(__pTxDesc)
-#define SET_TX_DESC_PADDING_LEN_8822B(__pTxDesc, __Value) SET_TX_DESC_PADDING_LEN(__pTxDesc, __Value)
-#define GET_TX_DESC_PADDING_LEN_8822B(__pTxDesc) GET_TX_DESC_PADDING_LEN(__pTxDesc)
-#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8822B(__pTxDesc, __Value) SET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc, __Value)
-#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8822B(__pTxDesc) GET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc)
+#define SET_TX_DESC_TAILPAGE_H_8822B(txdesc, value) \
+ SET_TX_DESC_TAILPAGE_H(txdesc, value)
+#define GET_TX_DESC_TAILPAGE_H_8822B(txdesc) GET_TX_DESC_TAILPAGE_H(txdesc)
+#define SET_TX_DESC_NEXTHEADPAGE_H_8822B(txdesc, value) \
+ SET_TX_DESC_NEXTHEADPAGE_H(txdesc, value)
+#define GET_TX_DESC_NEXTHEADPAGE_H_8822B(txdesc) \
+ GET_TX_DESC_NEXTHEADPAGE_H(txdesc)
+#define SET_TX_DESC_SW_SEQ_8822B(txdesc, value) \
+ SET_TX_DESC_SW_SEQ(txdesc, value)
+#define GET_TX_DESC_SW_SEQ_8822B(txdesc) GET_TX_DESC_SW_SEQ(txdesc)
+#define SET_TX_DESC_TXBF_PATH_8822B(txdesc, value) \
+ SET_TX_DESC_TXBF_PATH(txdesc, value)
+#define GET_TX_DESC_TXBF_PATH_8822B(txdesc) GET_TX_DESC_TXBF_PATH(txdesc)
+#define SET_TX_DESC_PADDING_LEN_8822B(txdesc, value) \
+ SET_TX_DESC_PADDING_LEN(txdesc, value)
+#define GET_TX_DESC_PADDING_LEN_8822B(txdesc) GET_TX_DESC_PADDING_LEN(txdesc)
+#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8822B(txdesc, value) \
+ SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value)
+#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8822B(txdesc) \
+ GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc)
/*WORD10*/
-#define SET_TX_DESC_MU_DATARATE_8822B(__pTxDesc, __Value) SET_TX_DESC_MU_DATARATE(__pTxDesc, __Value)
-#define GET_TX_DESC_MU_DATARATE_8822B(__pTxDesc) GET_TX_DESC_MU_DATARATE(__pTxDesc)
-#define SET_TX_DESC_MU_RC_8822B(__pTxDesc, __Value) SET_TX_DESC_MU_RC(__pTxDesc, __Value)
-#define GET_TX_DESC_MU_RC_8822B(__pTxDesc) GET_TX_DESC_MU_RC(__pTxDesc)
-#define SET_TX_DESC_SND_PKT_SEL_8822B(__pTxDesc, __Value) SET_TX_DESC_SND_PKT_SEL(__pTxDesc, __Value)
-#define GET_TX_DESC_SND_PKT_SEL_8822B(__pTxDesc) GET_TX_DESC_SND_PKT_SEL(__pTxDesc)
+#define SET_TX_DESC_MU_DATARATE_8822B(txdesc, value) \
+ SET_TX_DESC_MU_DATARATE(txdesc, value)
+#define GET_TX_DESC_MU_DATARATE_8822B(txdesc) GET_TX_DESC_MU_DATARATE(txdesc)
+#define SET_TX_DESC_MU_RC_8822B(txdesc, value) SET_TX_DESC_MU_RC(txdesc, value)
+#define GET_TX_DESC_MU_RC_8822B(txdesc) GET_TX_DESC_MU_RC(txdesc)
+#define SET_TX_DESC_SND_PKT_SEL_8822B(txdesc, value) \
+ SET_TX_DESC_SND_PKT_SEL(txdesc, value)
+#define GET_TX_DESC_SND_PKT_SEL_8822B(txdesc) GET_TX_DESC_SND_PKT_SEL(txdesc)
#endif
@@ -520,728 +761,1625 @@
/*TXDESC_WORD0*/
-#define SET_TX_DESC_DISQSELSEQ_8197F(__pTxDesc, __Value) SET_TX_DESC_DISQSELSEQ(__pTxDesc, __Value)
-#define GET_TX_DESC_DISQSELSEQ_8197F(__pTxDesc) GET_TX_DESC_DISQSELSEQ(__pTxDesc)
-#define SET_TX_DESC_GF_8197F(__pTxDesc, __Value) SET_TX_DESC_GF(__pTxDesc, __Value)
-#define GET_TX_DESC_GF_8197F(__pTxDesc) GET_TX_DESC_GF(__pTxDesc)
-#define SET_TX_DESC_NO_ACM_8197F(__pTxDesc, __Value) SET_TX_DESC_NO_ACM(__pTxDesc, __Value)
-#define GET_TX_DESC_NO_ACM_8197F(__pTxDesc) GET_TX_DESC_NO_ACM(__pTxDesc)
-#define SET_TX_DESC_BCNPKT_TSF_CTRL_8197F(__pTxDesc, __Value) SET_TX_DESC_BCNPKT_TSF_CTRL(__pTxDesc, __Value)
-#define GET_TX_DESC_BCNPKT_TSF_CTRL_8197F(__pTxDesc) GET_TX_DESC_BCNPKT_TSF_CTRL(__pTxDesc)
-#define SET_TX_DESC_AMSDU_PAD_EN_8197F(__pTxDesc, __Value) SET_TX_DESC_AMSDU_PAD_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_AMSDU_PAD_EN_8197F(__pTxDesc) GET_TX_DESC_AMSDU_PAD_EN(__pTxDesc)
-#define SET_TX_DESC_LS_8197F(__pTxDesc, __Value) SET_TX_DESC_LS(__pTxDesc, __Value)
-#define GET_TX_DESC_LS_8197F(__pTxDesc) GET_TX_DESC_LS(__pTxDesc)
-#define SET_TX_DESC_HTC_8197F(__pTxDesc, __Value) SET_TX_DESC_HTC(__pTxDesc, __Value)
-#define GET_TX_DESC_HTC_8197F(__pTxDesc) GET_TX_DESC_HTC(__pTxDesc)
-#define SET_TX_DESC_BMC_8197F(__pTxDesc, __Value) SET_TX_DESC_BMC(__pTxDesc, __Value)
-#define GET_TX_DESC_BMC_8197F(__pTxDesc) GET_TX_DESC_BMC(__pTxDesc)
-#define SET_TX_DESC_OFFSET_8197F(__pTxDesc, __Value) SET_TX_DESC_OFFSET(__pTxDesc, __Value)
-#define GET_TX_DESC_OFFSET_8197F(__pTxDesc) GET_TX_DESC_OFFSET(__pTxDesc)
-#define SET_TX_DESC_TXPKTSIZE_8197F(__pTxDesc, __Value) SET_TX_DESC_TXPKTSIZE(__pTxDesc, __Value)
-#define GET_TX_DESC_TXPKTSIZE_8197F(__pTxDesc) GET_TX_DESC_TXPKTSIZE(__pTxDesc)
-
-/*TXDESC_WORD1*/
-
-#define SET_TX_DESC_MOREDATA_8197F(__pTxDesc, __Value) SET_TX_DESC_MOREDATA(__pTxDesc, __Value)
-#define GET_TX_DESC_MOREDATA_8197F(__pTxDesc) GET_TX_DESC_MOREDATA(__pTxDesc)
-#define SET_TX_DESC_PKT_OFFSET_8197F(__pTxDesc, __Value) SET_TX_DESC_PKT_OFFSET(__pTxDesc, __Value)
-#define GET_TX_DESC_PKT_OFFSET_8197F(__pTxDesc) GET_TX_DESC_PKT_OFFSET(__pTxDesc)
-#define SET_TX_DESC_SEC_TYPE_8197F(__pTxDesc, __Value) SET_TX_DESC_SEC_TYPE(__pTxDesc, __Value)
-#define GET_TX_DESC_SEC_TYPE_8197F(__pTxDesc) GET_TX_DESC_SEC_TYPE(__pTxDesc)
-#define SET_TX_DESC_EN_DESC_ID_8197F(__pTxDesc, __Value) SET_TX_DESC_EN_DESC_ID(__pTxDesc, __Value)
-#define GET_TX_DESC_EN_DESC_ID_8197F(__pTxDesc) GET_TX_DESC_EN_DESC_ID(__pTxDesc)
-#define SET_TX_DESC_RATE_ID_8197F(__pTxDesc, __Value) SET_TX_DESC_RATE_ID(__pTxDesc, __Value)
-#define GET_TX_DESC_RATE_ID_8197F(__pTxDesc) GET_TX_DESC_RATE_ID(__pTxDesc)
-#define SET_TX_DESC_PIFS_8197F(__pTxDesc, __Value) SET_TX_DESC_PIFS(__pTxDesc, __Value)
-#define GET_TX_DESC_PIFS_8197F(__pTxDesc) GET_TX_DESC_PIFS(__pTxDesc)
-#define SET_TX_DESC_LSIG_TXOP_EN_8197F(__pTxDesc, __Value) SET_TX_DESC_LSIG_TXOP_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_LSIG_TXOP_EN_8197F(__pTxDesc) GET_TX_DESC_LSIG_TXOP_EN(__pTxDesc)
-#define SET_TX_DESC_RD_NAV_EXT_8197F(__pTxDesc, __Value) SET_TX_DESC_RD_NAV_EXT(__pTxDesc, __Value)
-#define GET_TX_DESC_RD_NAV_EXT_8197F(__pTxDesc) GET_TX_DESC_RD_NAV_EXT(__pTxDesc)
-#define SET_TX_DESC_QSEL_8197F(__pTxDesc, __Value) SET_TX_DESC_QSEL(__pTxDesc, __Value)
-#define GET_TX_DESC_QSEL_8197F(__pTxDesc) GET_TX_DESC_QSEL(__pTxDesc)
-#define SET_TX_DESC_MACID_8197F(__pTxDesc, __Value) SET_TX_DESC_MACID(__pTxDesc, __Value)
-#define GET_TX_DESC_MACID_8197F(__pTxDesc) GET_TX_DESC_MACID(__pTxDesc)
+#define SET_TX_DESC_DISQSELSEQ_8197F(txdesc, value) \
+ SET_TX_DESC_DISQSELSEQ(txdesc, value)
+#define GET_TX_DESC_DISQSELSEQ_8197F(txdesc) GET_TX_DESC_DISQSELSEQ(txdesc)
+#define SET_TX_DESC_GF_8197F(txdesc, value) SET_TX_DESC_GF(txdesc, value)
+#define GET_TX_DESC_GF_8197F(txdesc) GET_TX_DESC_GF(txdesc)
+#define SET_TX_DESC_NO_ACM_8197F(txdesc, value) \
+ SET_TX_DESC_NO_ACM(txdesc, value)
+#define GET_TX_DESC_NO_ACM_8197F(txdesc) GET_TX_DESC_NO_ACM(txdesc)
+#define SET_TX_DESC_BCNPKT_TSF_CTRL_8197F(txdesc, value) \
+ SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value)
+#define GET_TX_DESC_BCNPKT_TSF_CTRL_8197F(txdesc) \
+ GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc)
+#define SET_TX_DESC_AMSDU_PAD_EN_8197F(txdesc, value) \
+ SET_TX_DESC_AMSDU_PAD_EN(txdesc, value)
+#define GET_TX_DESC_AMSDU_PAD_EN_8197F(txdesc) GET_TX_DESC_AMSDU_PAD_EN(txdesc)
+#define SET_TX_DESC_LS_8197F(txdesc, value) SET_TX_DESC_LS(txdesc, value)
+#define GET_TX_DESC_LS_8197F(txdesc) GET_TX_DESC_LS(txdesc)
+#define SET_TX_DESC_HTC_8197F(txdesc, value) SET_TX_DESC_HTC(txdesc, value)
+#define GET_TX_DESC_HTC_8197F(txdesc) GET_TX_DESC_HTC(txdesc)
+#define SET_TX_DESC_BMC_8197F(txdesc, value) SET_TX_DESC_BMC(txdesc, value)
+#define GET_TX_DESC_BMC_8197F(txdesc) GET_TX_DESC_BMC(txdesc)
+#define SET_TX_DESC_OFFSET_8197F(txdesc, value) \
+ SET_TX_DESC_OFFSET(txdesc, value)
+#define GET_TX_DESC_OFFSET_8197F(txdesc) GET_TX_DESC_OFFSET(txdesc)
+#define SET_TX_DESC_TXPKTSIZE_8197F(txdesc, value) \
+ SET_TX_DESC_TXPKTSIZE(txdesc, value)
+#define GET_TX_DESC_TXPKTSIZE_8197F(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc)
+
+/*WORD1*/
+
+#define SET_TX_DESC_MOREDATA_8197F(txdesc, value) \
+ SET_TX_DESC_MOREDATA(txdesc, value)
+#define GET_TX_DESC_MOREDATA_8197F(txdesc) GET_TX_DESC_MOREDATA(txdesc)
+#define SET_TX_DESC_PKT_OFFSET_8197F(txdesc, value) \
+ SET_TX_DESC_PKT_OFFSET(txdesc, value)
+#define GET_TX_DESC_PKT_OFFSET_8197F(txdesc) GET_TX_DESC_PKT_OFFSET(txdesc)
+#define SET_TX_DESC_SEC_TYPE_8197F(txdesc, value) \
+ SET_TX_DESC_SEC_TYPE(txdesc, value)
+#define GET_TX_DESC_SEC_TYPE_8197F(txdesc) GET_TX_DESC_SEC_TYPE(txdesc)
+#define SET_TX_DESC_EN_DESC_ID_8197F(txdesc, value) \
+ SET_TX_DESC_EN_DESC_ID(txdesc, value)
+#define GET_TX_DESC_EN_DESC_ID_8197F(txdesc) GET_TX_DESC_EN_DESC_ID(txdesc)
+#define SET_TX_DESC_RATE_ID_8197F(txdesc, value) \
+ SET_TX_DESC_RATE_ID(txdesc, value)
+#define GET_TX_DESC_RATE_ID_8197F(txdesc) GET_TX_DESC_RATE_ID(txdesc)
+#define SET_TX_DESC_PIFS_8197F(txdesc, value) SET_TX_DESC_PIFS(txdesc, value)
+#define GET_TX_DESC_PIFS_8197F(txdesc) GET_TX_DESC_PIFS(txdesc)
+#define SET_TX_DESC_LSIG_TXOP_EN_8197F(txdesc, value) \
+ SET_TX_DESC_LSIG_TXOP_EN(txdesc, value)
+#define GET_TX_DESC_LSIG_TXOP_EN_8197F(txdesc) GET_TX_DESC_LSIG_TXOP_EN(txdesc)
+#define SET_TX_DESC_RD_NAV_EXT_8197F(txdesc, value) \
+ SET_TX_DESC_RD_NAV_EXT(txdesc, value)
+#define GET_TX_DESC_RD_NAV_EXT_8197F(txdesc) GET_TX_DESC_RD_NAV_EXT(txdesc)
+#define SET_TX_DESC_QSEL_8197F(txdesc, value) SET_TX_DESC_QSEL(txdesc, value)
+#define GET_TX_DESC_QSEL_8197F(txdesc) GET_TX_DESC_QSEL(txdesc)
+#define SET_TX_DESC_MACID_8197F(txdesc, value) SET_TX_DESC_MACID(txdesc, value)
+#define GET_TX_DESC_MACID_8197F(txdesc) GET_TX_DESC_MACID(txdesc)
/*TXDESC_WORD2*/
-#define SET_TX_DESC_HW_AES_IV_8197F(__pTxDesc, __Value) SET_TX_DESC_HW_AES_IV(__pTxDesc, __Value)
-#define GET_TX_DESC_HW_AES_IV_8197F(__pTxDesc) GET_TX_DESC_HW_AES_IV(__pTxDesc)
-#define SET_TX_DESC_FTM_EN_8197F(__pTxDesc, __Value) SET_TX_DESC_FTM_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_FTM_EN_8197F(__pTxDesc) GET_TX_DESC_FTM_EN(__pTxDesc)
-#define SET_TX_DESC_G_ID_8197F(__pTxDesc, __Value) SET_TX_DESC_G_ID(__pTxDesc, __Value)
-#define GET_TX_DESC_G_ID_8197F(__pTxDesc) GET_TX_DESC_G_ID(__pTxDesc)
-#define SET_TX_DESC_BT_NULL_8197F(__pTxDesc, __Value) SET_TX_DESC_BT_NULL(__pTxDesc, __Value)
-#define GET_TX_DESC_BT_NULL_8197F(__pTxDesc) GET_TX_DESC_BT_NULL(__pTxDesc)
-#define SET_TX_DESC_AMPDU_DENSITY_8197F(__pTxDesc, __Value) SET_TX_DESC_AMPDU_DENSITY(__pTxDesc, __Value)
-#define GET_TX_DESC_AMPDU_DENSITY_8197F(__pTxDesc) GET_TX_DESC_AMPDU_DENSITY(__pTxDesc)
-#define SET_TX_DESC_SPE_RPT_8197F(__pTxDesc, __Value) SET_TX_DESC_SPE_RPT(__pTxDesc, __Value)
-#define GET_TX_DESC_SPE_RPT_8197F(__pTxDesc) GET_TX_DESC_SPE_RPT(__pTxDesc)
-#define SET_TX_DESC_RAW_8197F(__pTxDesc, __Value) SET_TX_DESC_RAW(__pTxDesc, __Value)
-#define GET_TX_DESC_RAW_8197F(__pTxDesc) GET_TX_DESC_RAW(__pTxDesc)
-#define SET_TX_DESC_MOREFRAG_8197F(__pTxDesc, __Value) SET_TX_DESC_MOREFRAG(__pTxDesc, __Value)
-#define GET_TX_DESC_MOREFRAG_8197F(__pTxDesc) GET_TX_DESC_MOREFRAG(__pTxDesc)
-#define SET_TX_DESC_BK_8197F(__pTxDesc, __Value) SET_TX_DESC_BK(__pTxDesc, __Value)
-#define GET_TX_DESC_BK_8197F(__pTxDesc) GET_TX_DESC_BK(__pTxDesc)
-#define SET_TX_DESC_NULL_1_8197F(__pTxDesc, __Value) SET_TX_DESC_NULL_1(__pTxDesc, __Value)
-#define GET_TX_DESC_NULL_1_8197F(__pTxDesc) GET_TX_DESC_NULL_1(__pTxDesc)
-#define SET_TX_DESC_NULL_0_8197F(__pTxDesc, __Value) SET_TX_DESC_NULL_0(__pTxDesc, __Value)
-#define GET_TX_DESC_NULL_0_8197F(__pTxDesc) GET_TX_DESC_NULL_0(__pTxDesc)
-#define SET_TX_DESC_RDG_EN_8197F(__pTxDesc, __Value) SET_TX_DESC_RDG_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_RDG_EN_8197F(__pTxDesc) GET_TX_DESC_RDG_EN(__pTxDesc)
-#define SET_TX_DESC_AGG_EN_8197F(__pTxDesc, __Value) SET_TX_DESC_AGG_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_AGG_EN_8197F(__pTxDesc) GET_TX_DESC_AGG_EN(__pTxDesc)
-#define SET_TX_DESC_CCA_RTS_8197F(__pTxDesc, __Value) SET_TX_DESC_CCA_RTS(__pTxDesc, __Value)
-#define GET_TX_DESC_CCA_RTS_8197F(__pTxDesc) GET_TX_DESC_CCA_RTS(__pTxDesc)
-#define SET_TX_DESC_TRI_FRAME_8197F(__pTxDesc, __Value) SET_TX_DESC_TRI_FRAME(__pTxDesc, __Value)
-#define GET_TX_DESC_TRI_FRAME_8197F(__pTxDesc) GET_TX_DESC_TRI_FRAME(__pTxDesc)
-#define SET_TX_DESC_P_AID_8197F(__pTxDesc, __Value) SET_TX_DESC_P_AID(__pTxDesc, __Value)
-#define GET_TX_DESC_P_AID_8197F(__pTxDesc) GET_TX_DESC_P_AID(__pTxDesc)
+#define SET_TX_DESC_HW_AES_IV_8197F(txdesc, value) \
+ SET_TX_DESC_HW_AES_IV(txdesc, value)
+#define GET_TX_DESC_HW_AES_IV_8197F(txdesc) GET_TX_DESC_HW_AES_IV(txdesc)
+#define SET_TX_DESC_FTM_EN_8197F(txdesc, value) \
+ SET_TX_DESC_FTM_EN(txdesc, value)
+#define GET_TX_DESC_FTM_EN_8197F(txdesc) GET_TX_DESC_FTM_EN(txdesc)
+#define SET_TX_DESC_G_ID_8197F(txdesc, value) SET_TX_DESC_G_ID(txdesc, value)
+#define GET_TX_DESC_G_ID_8197F(txdesc) GET_TX_DESC_G_ID(txdesc)
+#define SET_TX_DESC_BT_NULL_8197F(txdesc, value) \
+ SET_TX_DESC_BT_NULL(txdesc, value)
+#define GET_TX_DESC_BT_NULL_8197F(txdesc) GET_TX_DESC_BT_NULL(txdesc)
+#define SET_TX_DESC_AMPDU_DENSITY_8197F(txdesc, value) \
+ SET_TX_DESC_AMPDU_DENSITY(txdesc, value)
+#define GET_TX_DESC_AMPDU_DENSITY_8197F(txdesc) \
+ GET_TX_DESC_AMPDU_DENSITY(txdesc)
+#define SET_TX_DESC_SPE_RPT_8197F(txdesc, value) \
+ SET_TX_DESC_SPE_RPT(txdesc, value)
+#define GET_TX_DESC_SPE_RPT_8197F(txdesc) GET_TX_DESC_SPE_RPT(txdesc)
+#define SET_TX_DESC_RAW_8197F(txdesc, value) SET_TX_DESC_RAW(txdesc, value)
+#define GET_TX_DESC_RAW_8197F(txdesc) GET_TX_DESC_RAW(txdesc)
+#define SET_TX_DESC_MOREFRAG_8197F(txdesc, value) \
+ SET_TX_DESC_MOREFRAG(txdesc, value)
+#define GET_TX_DESC_MOREFRAG_8197F(txdesc) GET_TX_DESC_MOREFRAG(txdesc)
+#define SET_TX_DESC_BK_8197F(txdesc, value) SET_TX_DESC_BK(txdesc, value)
+#define GET_TX_DESC_BK_8197F(txdesc) GET_TX_DESC_BK(txdesc)
+#define SET_TX_DESC_NULL_1_8197F(txdesc, value) \
+ SET_TX_DESC_NULL_1(txdesc, value)
+#define GET_TX_DESC_NULL_1_8197F(txdesc) GET_TX_DESC_NULL_1(txdesc)
+#define SET_TX_DESC_NULL_0_8197F(txdesc, value) \
+ SET_TX_DESC_NULL_0(txdesc, value)
+#define GET_TX_DESC_NULL_0_8197F(txdesc) GET_TX_DESC_NULL_0(txdesc)
+#define SET_TX_DESC_RDG_EN_8197F(txdesc, value) \
+ SET_TX_DESC_RDG_EN(txdesc, value)
+#define GET_TX_DESC_RDG_EN_8197F(txdesc) GET_TX_DESC_RDG_EN(txdesc)
+#define SET_TX_DESC_AGG_EN_8197F(txdesc, value) \
+ SET_TX_DESC_AGG_EN(txdesc, value)
+#define GET_TX_DESC_AGG_EN_8197F(txdesc) GET_TX_DESC_AGG_EN(txdesc)
+#define SET_TX_DESC_CCA_RTS_8197F(txdesc, value) \
+ SET_TX_DESC_CCA_RTS(txdesc, value)
+#define GET_TX_DESC_CCA_RTS_8197F(txdesc) GET_TX_DESC_CCA_RTS(txdesc)
+#define SET_TX_DESC_TRI_FRAME_8197F(txdesc, value) \
+ SET_TX_DESC_TRI_FRAME(txdesc, value)
+#define GET_TX_DESC_TRI_FRAME_8197F(txdesc) GET_TX_DESC_TRI_FRAME(txdesc)
+#define SET_TX_DESC_P_AID_8197F(txdesc, value) SET_TX_DESC_P_AID(txdesc, value)
+#define GET_TX_DESC_P_AID_8197F(txdesc) GET_TX_DESC_P_AID(txdesc)
/*TXDESC_WORD3*/
-#define SET_TX_DESC_AMPDU_MAX_TIME_8197F(__pTxDesc, __Value) SET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc, __Value)
-#define GET_TX_DESC_AMPDU_MAX_TIME_8197F(__pTxDesc) GET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc)
-#define SET_TX_DESC_NDPA_8197F(__pTxDesc, __Value) SET_TX_DESC_NDPA(__pTxDesc, __Value)
-#define GET_TX_DESC_NDPA_8197F(__pTxDesc) GET_TX_DESC_NDPA(__pTxDesc)
-#define SET_TX_DESC_MAX_AGG_NUM_8197F(__pTxDesc, __Value) SET_TX_DESC_MAX_AGG_NUM(__pTxDesc, __Value)
-#define GET_TX_DESC_MAX_AGG_NUM_8197F(__pTxDesc) GET_TX_DESC_MAX_AGG_NUM(__pTxDesc)
-#define SET_TX_DESC_USE_MAX_TIME_EN_8197F(__pTxDesc, __Value) SET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_USE_MAX_TIME_EN_8197F(__pTxDesc) GET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc)
-#define SET_TX_DESC_NAVUSEHDR_8197F(__pTxDesc, __Value) SET_TX_DESC_NAVUSEHDR(__pTxDesc, __Value)
-#define GET_TX_DESC_NAVUSEHDR_8197F(__pTxDesc) GET_TX_DESC_NAVUSEHDR(__pTxDesc)
-#define SET_TX_DESC_CHK_EN_8197F(__pTxDesc, __Value) SET_TX_DESC_CHK_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_CHK_EN_8197F(__pTxDesc) GET_TX_DESC_CHK_EN(__pTxDesc)
-#define SET_TX_DESC_HW_RTS_EN_8197F(__pTxDesc, __Value) SET_TX_DESC_HW_RTS_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_HW_RTS_EN_8197F(__pTxDesc) GET_TX_DESC_HW_RTS_EN(__pTxDesc)
-#define SET_TX_DESC_RTSEN_8197F(__pTxDesc, __Value) SET_TX_DESC_RTSEN(__pTxDesc, __Value)
-#define GET_TX_DESC_RTSEN_8197F(__pTxDesc) GET_TX_DESC_RTSEN(__pTxDesc)
-#define SET_TX_DESC_CTS2SELF_8197F(__pTxDesc, __Value) SET_TX_DESC_CTS2SELF(__pTxDesc, __Value)
-#define GET_TX_DESC_CTS2SELF_8197F(__pTxDesc) GET_TX_DESC_CTS2SELF(__pTxDesc)
-#define SET_TX_DESC_DISDATAFB_8197F(__pTxDesc, __Value) SET_TX_DESC_DISDATAFB(__pTxDesc, __Value)
-#define GET_TX_DESC_DISDATAFB_8197F(__pTxDesc) GET_TX_DESC_DISDATAFB(__pTxDesc)
-#define SET_TX_DESC_DISRTSFB_8197F(__pTxDesc, __Value) SET_TX_DESC_DISRTSFB(__pTxDesc, __Value)
-#define GET_TX_DESC_DISRTSFB_8197F(__pTxDesc) GET_TX_DESC_DISRTSFB(__pTxDesc)
-#define SET_TX_DESC_USE_RATE_8197F(__pTxDesc, __Value) SET_TX_DESC_USE_RATE(__pTxDesc, __Value)
-#define GET_TX_DESC_USE_RATE_8197F(__pTxDesc) GET_TX_DESC_USE_RATE(__pTxDesc)
-#define SET_TX_DESC_HW_SSN_SEL_8197F(__pTxDesc, __Value) SET_TX_DESC_HW_SSN_SEL(__pTxDesc, __Value)
-#define GET_TX_DESC_HW_SSN_SEL_8197F(__pTxDesc) GET_TX_DESC_HW_SSN_SEL(__pTxDesc)
-#define SET_TX_DESC_WHEADER_LEN_8197F(__pTxDesc, __Value) SET_TX_DESC_WHEADER_LEN(__pTxDesc, __Value)
-#define GET_TX_DESC_WHEADER_LEN_8197F(__pTxDesc) GET_TX_DESC_WHEADER_LEN(__pTxDesc)
+#define SET_TX_DESC_AMPDU_MAX_TIME_8197F(txdesc, value) \
+ SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value)
+#define GET_TX_DESC_AMPDU_MAX_TIME_8197F(txdesc) \
+ GET_TX_DESC_AMPDU_MAX_TIME(txdesc)
+#define SET_TX_DESC_NDPA_8197F(txdesc, value) SET_TX_DESC_NDPA(txdesc, value)
+#define GET_TX_DESC_NDPA_8197F(txdesc) GET_TX_DESC_NDPA(txdesc)
+#define SET_TX_DESC_MAX_AGG_NUM_8197F(txdesc, value) \
+ SET_TX_DESC_MAX_AGG_NUM(txdesc, value)
+#define GET_TX_DESC_MAX_AGG_NUM_8197F(txdesc) GET_TX_DESC_MAX_AGG_NUM(txdesc)
+#define SET_TX_DESC_USE_MAX_TIME_EN_8197F(txdesc, value) \
+ SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value)
+#define GET_TX_DESC_USE_MAX_TIME_EN_8197F(txdesc) \
+ GET_TX_DESC_USE_MAX_TIME_EN(txdesc)
+#define SET_TX_DESC_NAVUSEHDR_8197F(txdesc, value) \
+ SET_TX_DESC_NAVUSEHDR(txdesc, value)
+#define GET_TX_DESC_NAVUSEHDR_8197F(txdesc) GET_TX_DESC_NAVUSEHDR(txdesc)
+#define SET_TX_DESC_CHK_EN_8197F(txdesc, value) \
+ SET_TX_DESC_CHK_EN(txdesc, value)
+#define GET_TX_DESC_CHK_EN_8197F(txdesc) GET_TX_DESC_CHK_EN(txdesc)
+#define SET_TX_DESC_HW_RTS_EN_8197F(txdesc, value) \
+ SET_TX_DESC_HW_RTS_EN(txdesc, value)
+#define GET_TX_DESC_HW_RTS_EN_8197F(txdesc) GET_TX_DESC_HW_RTS_EN(txdesc)
+#define SET_TX_DESC_RTSEN_8197F(txdesc, value) SET_TX_DESC_RTSEN(txdesc, value)
+#define GET_TX_DESC_RTSEN_8197F(txdesc) GET_TX_DESC_RTSEN(txdesc)
+#define SET_TX_DESC_CTS2SELF_8197F(txdesc, value) \
+ SET_TX_DESC_CTS2SELF(txdesc, value)
+#define GET_TX_DESC_CTS2SELF_8197F(txdesc) GET_TX_DESC_CTS2SELF(txdesc)
+#define SET_TX_DESC_DISDATAFB_8197F(txdesc, value) \
+ SET_TX_DESC_DISDATAFB(txdesc, value)
+#define GET_TX_DESC_DISDATAFB_8197F(txdesc) GET_TX_DESC_DISDATAFB(txdesc)
+#define SET_TX_DESC_DISRTSFB_8197F(txdesc, value) \
+ SET_TX_DESC_DISRTSFB(txdesc, value)
+#define GET_TX_DESC_DISRTSFB_8197F(txdesc) GET_TX_DESC_DISRTSFB(txdesc)
+#define SET_TX_DESC_USE_RATE_8197F(txdesc, value) \
+ SET_TX_DESC_USE_RATE(txdesc, value)
+#define GET_TX_DESC_USE_RATE_8197F(txdesc) GET_TX_DESC_USE_RATE(txdesc)
+#define SET_TX_DESC_HW_SSN_SEL_8197F(txdesc, value) \
+ SET_TX_DESC_HW_SSN_SEL(txdesc, value)
+#define GET_TX_DESC_HW_SSN_SEL_8197F(txdesc) GET_TX_DESC_HW_SSN_SEL(txdesc)
+#define SET_TX_DESC_WHEADER_LEN_8197F(txdesc, value) \
+ SET_TX_DESC_WHEADER_LEN(txdesc, value)
+#define GET_TX_DESC_WHEADER_LEN_8197F(txdesc) GET_TX_DESC_WHEADER_LEN(txdesc)
/*TXDESC_WORD4*/
-#define SET_TX_DESC_PCTS_MASK_IDX_8197F(__pTxDesc, __Value) SET_TX_DESC_PCTS_MASK_IDX(__pTxDesc, __Value)
-#define GET_TX_DESC_PCTS_MASK_IDX_8197F(__pTxDesc) GET_TX_DESC_PCTS_MASK_IDX(__pTxDesc)
-#define SET_TX_DESC_PCTS_EN_8197F(__pTxDesc, __Value) SET_TX_DESC_PCTS_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_PCTS_EN_8197F(__pTxDesc) GET_TX_DESC_PCTS_EN(__pTxDesc)
-#define SET_TX_DESC_RTSRATE_8197F(__pTxDesc, __Value) SET_TX_DESC_RTSRATE(__pTxDesc, __Value)
-#define GET_TX_DESC_RTSRATE_8197F(__pTxDesc) GET_TX_DESC_RTSRATE(__pTxDesc)
-#define SET_TX_DESC_RTS_DATA_RTY_LMT_8197F(__pTxDesc, __Value) SET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc, __Value)
-#define GET_TX_DESC_RTS_DATA_RTY_LMT_8197F(__pTxDesc) GET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc)
-#define SET_TX_DESC_RTY_LMT_EN_8197F(__pTxDesc, __Value) SET_TX_DESC_RTY_LMT_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_RTY_LMT_EN_8197F(__pTxDesc) GET_TX_DESC_RTY_LMT_EN(__pTxDesc)
-#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8197F(__pTxDesc, __Value) SET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc, __Value)
-#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8197F(__pTxDesc) GET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc)
-#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8197F(__pTxDesc, __Value) SET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc, __Value)
-#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8197F(__pTxDesc) GET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc)
-#define SET_TX_DESC_TRY_RATE_8197F(__pTxDesc, __Value) SET_TX_DESC_TRY_RATE(__pTxDesc, __Value)
-#define GET_TX_DESC_TRY_RATE_8197F(__pTxDesc) GET_TX_DESC_TRY_RATE(__pTxDesc)
-#define SET_TX_DESC_DATARATE_8197F(__pTxDesc, __Value) SET_TX_DESC_DATARATE(__pTxDesc, __Value)
-#define GET_TX_DESC_DATARATE_8197F(__pTxDesc) GET_TX_DESC_DATARATE(__pTxDesc)
+#define SET_TX_DESC_PCTS_MASK_IDX_8197F(txdesc, value) \
+ SET_TX_DESC_PCTS_MASK_IDX(txdesc, value)
+#define GET_TX_DESC_PCTS_MASK_IDX_8197F(txdesc) \
+ GET_TX_DESC_PCTS_MASK_IDX(txdesc)
+#define SET_TX_DESC_PCTS_EN_8197F(txdesc, value) \
+ SET_TX_DESC_PCTS_EN(txdesc, value)
+#define GET_TX_DESC_PCTS_EN_8197F(txdesc) GET_TX_DESC_PCTS_EN(txdesc)
+#define SET_TX_DESC_RTSRATE_8197F(txdesc, value) \
+ SET_TX_DESC_RTSRATE(txdesc, value)
+#define GET_TX_DESC_RTSRATE_8197F(txdesc) GET_TX_DESC_RTSRATE(txdesc)
+#define SET_TX_DESC_RTS_DATA_RTY_LMT_8197F(txdesc, value) \
+ SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value)
+#define GET_TX_DESC_RTS_DATA_RTY_LMT_8197F(txdesc) \
+ GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc)
+#define SET_TX_DESC_RTY_LMT_EN_8197F(txdesc, value) \
+ SET_TX_DESC_RTY_LMT_EN(txdesc, value)
+#define GET_TX_DESC_RTY_LMT_EN_8197F(txdesc) GET_TX_DESC_RTY_LMT_EN(txdesc)
+#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8197F(txdesc, value) \
+ SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value)
+#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8197F(txdesc) \
+ GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc)
+#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8197F(txdesc, value) \
+ SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value)
+#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8197F(txdesc) \
+ GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc)
+#define SET_TX_DESC_TRY_RATE_8197F(txdesc, value) \
+ SET_TX_DESC_TRY_RATE(txdesc, value)
+#define GET_TX_DESC_TRY_RATE_8197F(txdesc) GET_TX_DESC_TRY_RATE(txdesc)
+#define SET_TX_DESC_DATARATE_8197F(txdesc, value) \
+ SET_TX_DESC_DATARATE(txdesc, value)
+#define GET_TX_DESC_DATARATE_8197F(txdesc) GET_TX_DESC_DATARATE(txdesc)
/*TXDESC_WORD5*/
-#define SET_TX_DESC_POLLUTED_8197F(__pTxDesc, __Value) SET_TX_DESC_POLLUTED(__pTxDesc, __Value)
-#define GET_TX_DESC_POLLUTED_8197F(__pTxDesc) GET_TX_DESC_POLLUTED(__pTxDesc)
-#define SET_TX_DESC_TXPWR_OFSET_8197F(__pTxDesc, __Value) SET_TX_DESC_TXPWR_OFSET(__pTxDesc, __Value)
-#define GET_TX_DESC_TXPWR_OFSET_8197F(__pTxDesc) GET_TX_DESC_TXPWR_OFSET(__pTxDesc)
-#define SET_TX_DESC_TX_ANT_8197F(__pTxDesc, __Value) SET_TX_DESC_TX_ANT(__pTxDesc, __Value)
-#define GET_TX_DESC_TX_ANT_8197F(__pTxDesc) GET_TX_DESC_TX_ANT(__pTxDesc)
-#define SET_TX_DESC_PORT_ID_8197F(__pTxDesc, __Value) SET_TX_DESC_PORT_ID(__pTxDesc, __Value)
-#define GET_TX_DESC_PORT_ID_8197F(__pTxDesc) GET_TX_DESC_PORT_ID(__pTxDesc)
-#define SET_TX_DESC_MULTIPLE_PORT_8197F(__pTxDesc, __Value) SET_TX_DESC_MULTIPLE_PORT(__pTxDesc, __Value)
-#define GET_TX_DESC_MULTIPLE_PORT_8197F(__pTxDesc) GET_TX_DESC_MULTIPLE_PORT(__pTxDesc)
-#define SET_TX_DESC_SIGNALING_TAPKT_EN_8197F(__pTxDesc, __Value) SET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_SIGNALING_TAPKT_EN_8197F(__pTxDesc) GET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc)
-#define SET_TX_DESC_RTS_SC_8197F(__pTxDesc, __Value) SET_TX_DESC_RTS_SC(__pTxDesc, __Value)
-#define GET_TX_DESC_RTS_SC_8197F(__pTxDesc) GET_TX_DESC_RTS_SC(__pTxDesc)
-#define SET_TX_DESC_RTS_SHORT_8197F(__pTxDesc, __Value) SET_TX_DESC_RTS_SHORT(__pTxDesc, __Value)
-#define GET_TX_DESC_RTS_SHORT_8197F(__pTxDesc) GET_TX_DESC_RTS_SHORT(__pTxDesc)
-#define SET_TX_DESC_VCS_STBC_8197F(__pTxDesc, __Value) SET_TX_DESC_VCS_STBC(__pTxDesc, __Value)
-#define GET_TX_DESC_VCS_STBC_8197F(__pTxDesc) GET_TX_DESC_VCS_STBC(__pTxDesc)
-#define SET_TX_DESC_DATA_STBC_8197F(__pTxDesc, __Value) SET_TX_DESC_DATA_STBC(__pTxDesc, __Value)
-#define GET_TX_DESC_DATA_STBC_8197F(__pTxDesc) GET_TX_DESC_DATA_STBC(__pTxDesc)
-#define SET_TX_DESC_DATA_LDPC_8197F(__pTxDesc, __Value) SET_TX_DESC_DATA_LDPC(__pTxDesc, __Value)
-#define GET_TX_DESC_DATA_LDPC_8197F(__pTxDesc) GET_TX_DESC_DATA_LDPC(__pTxDesc)
-#define SET_TX_DESC_DATA_BW_8197F(__pTxDesc, __Value) SET_TX_DESC_DATA_BW(__pTxDesc, __Value)
-#define GET_TX_DESC_DATA_BW_8197F(__pTxDesc) GET_TX_DESC_DATA_BW(__pTxDesc)
-#define SET_TX_DESC_DATA_SHORT_8197F(__pTxDesc, __Value) SET_TX_DESC_DATA_SHORT(__pTxDesc, __Value)
-#define GET_TX_DESC_DATA_SHORT_8197F(__pTxDesc) GET_TX_DESC_DATA_SHORT(__pTxDesc)
-#define SET_TX_DESC_DATA_SC_8197F(__pTxDesc, __Value) SET_TX_DESC_DATA_SC(__pTxDesc, __Value)
-#define GET_TX_DESC_DATA_SC_8197F(__pTxDesc) GET_TX_DESC_DATA_SC(__pTxDesc)
+#define SET_TX_DESC_POLLUTED_8197F(txdesc, value) \
+ SET_TX_DESC_POLLUTED(txdesc, value)
+#define GET_TX_DESC_POLLUTED_8197F(txdesc) GET_TX_DESC_POLLUTED(txdesc)
+#define SET_TX_DESC_TXPWR_OFSET_8197F(txdesc, value) \
+ SET_TX_DESC_TXPWR_OFSET(txdesc, value)
+#define GET_TX_DESC_TXPWR_OFSET_8197F(txdesc) GET_TX_DESC_TXPWR_OFSET(txdesc)
+#define SET_TX_DESC_TX_ANT_8197F(txdesc, value) \
+ SET_TX_DESC_TX_ANT(txdesc, value)
+#define GET_TX_DESC_TX_ANT_8197F(txdesc) GET_TX_DESC_TX_ANT(txdesc)
+#define SET_TX_DESC_PORT_ID_8197F(txdesc, value) \
+ SET_TX_DESC_PORT_ID(txdesc, value)
+#define GET_TX_DESC_PORT_ID_8197F(txdesc) GET_TX_DESC_PORT_ID(txdesc)
+#define SET_TX_DESC_MULTIPLE_PORT_8197F(txdesc, value) \
+ SET_TX_DESC_MULTIPLE_PORT(txdesc, value)
+#define GET_TX_DESC_MULTIPLE_PORT_8197F(txdesc) \
+ GET_TX_DESC_MULTIPLE_PORT(txdesc)
+#define SET_TX_DESC_SIGNALING_TAPKT_EN_8197F(txdesc, value) \
+ SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value)
+#define GET_TX_DESC_SIGNALING_TAPKT_EN_8197F(txdesc) \
+ GET_TX_DESC_SIGNALING_TAPKT_EN(txdesc)
+#define SET_TX_DESC_RTS_SC_8197F(txdesc, value) \
+ SET_TX_DESC_RTS_SC(txdesc, value)
+#define GET_TX_DESC_RTS_SC_8197F(txdesc) GET_TX_DESC_RTS_SC(txdesc)
+#define SET_TX_DESC_RTS_SHORT_8197F(txdesc, value) \
+ SET_TX_DESC_RTS_SHORT(txdesc, value)
+#define GET_TX_DESC_RTS_SHORT_8197F(txdesc) GET_TX_DESC_RTS_SHORT(txdesc)
+#define SET_TX_DESC_VCS_STBC_8197F(txdesc, value) \
+ SET_TX_DESC_VCS_STBC(txdesc, value)
+#define GET_TX_DESC_VCS_STBC_8197F(txdesc) GET_TX_DESC_VCS_STBC(txdesc)
+#define SET_TX_DESC_DATA_STBC_8197F(txdesc, value) \
+ SET_TX_DESC_DATA_STBC(txdesc, value)
+#define GET_TX_DESC_DATA_STBC_8197F(txdesc) GET_TX_DESC_DATA_STBC(txdesc)
+#define SET_TX_DESC_DATA_LDPC_8197F(txdesc, value) \
+ SET_TX_DESC_DATA_LDPC(txdesc, value)
+#define GET_TX_DESC_DATA_LDPC_8197F(txdesc) GET_TX_DESC_DATA_LDPC(txdesc)
+#define SET_TX_DESC_DATA_BW_8197F(txdesc, value) \
+ SET_TX_DESC_DATA_BW(txdesc, value)
+#define GET_TX_DESC_DATA_BW_8197F(txdesc) GET_TX_DESC_DATA_BW(txdesc)
+#define SET_TX_DESC_DATA_SHORT_8197F(txdesc, value) \
+ SET_TX_DESC_DATA_SHORT(txdesc, value)
+#define GET_TX_DESC_DATA_SHORT_8197F(txdesc) GET_TX_DESC_DATA_SHORT(txdesc)
+#define SET_TX_DESC_DATA_SC_8197F(txdesc, value) \
+ SET_TX_DESC_DATA_SC(txdesc, value)
+#define GET_TX_DESC_DATA_SC_8197F(txdesc) GET_TX_DESC_DATA_SC(txdesc)
/*TXDESC_WORD6*/
-#define SET_TX_DESC_ANTSEL_D_8197F(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_D(__pTxDesc, __Value)
-#define GET_TX_DESC_ANTSEL_D_8197F(__pTxDesc) GET_TX_DESC_ANTSEL_D(__pTxDesc)
-#define SET_TX_DESC_ANT_MAPD_8197F(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPD(__pTxDesc, __Value)
-#define GET_TX_DESC_ANT_MAPD_8197F(__pTxDesc) GET_TX_DESC_ANT_MAPD(__pTxDesc)
-#define SET_TX_DESC_ANT_MAPC_8197F(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPC(__pTxDesc, __Value)
-#define GET_TX_DESC_ANT_MAPC_8197F(__pTxDesc) GET_TX_DESC_ANT_MAPC(__pTxDesc)
-#define SET_TX_DESC_ANT_MAPB_8197F(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPB(__pTxDesc, __Value)
-#define GET_TX_DESC_ANT_MAPB_8197F(__pTxDesc) GET_TX_DESC_ANT_MAPB(__pTxDesc)
-#define SET_TX_DESC_ANT_MAPA_8197F(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPA(__pTxDesc, __Value)
-#define GET_TX_DESC_ANT_MAPA_8197F(__pTxDesc) GET_TX_DESC_ANT_MAPA(__pTxDesc)
-#define SET_TX_DESC_ANTSEL_C_8197F(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_C(__pTxDesc, __Value)
-#define GET_TX_DESC_ANTSEL_C_8197F(__pTxDesc) GET_TX_DESC_ANTSEL_C(__pTxDesc)
-#define SET_TX_DESC_ANTSEL_B_8197F(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_B(__pTxDesc, __Value)
-#define GET_TX_DESC_ANTSEL_B_8197F(__pTxDesc) GET_TX_DESC_ANTSEL_B(__pTxDesc)
-#define SET_TX_DESC_ANTSEL_A_8197F(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_A(__pTxDesc, __Value)
-#define GET_TX_DESC_ANTSEL_A_8197F(__pTxDesc) GET_TX_DESC_ANTSEL_A(__pTxDesc)
-#define SET_TX_DESC_MBSSID_8197F(__pTxDesc, __Value) SET_TX_DESC_MBSSID(__pTxDesc, __Value)
-#define GET_TX_DESC_MBSSID_8197F(__pTxDesc) GET_TX_DESC_MBSSID(__pTxDesc)
-#define SET_TX_DESC_SW_DEFINE_8197F(__pTxDesc, __Value) SET_TX_DESC_SW_DEFINE(__pTxDesc, __Value)
-#define GET_TX_DESC_SW_DEFINE_8197F(__pTxDesc) GET_TX_DESC_SW_DEFINE(__pTxDesc)
+#define SET_TX_DESC_ANTSEL_D_8197F(txdesc, value) \
+ SET_TX_DESC_ANTSEL_D(txdesc, value)
+#define GET_TX_DESC_ANTSEL_D_8197F(txdesc) GET_TX_DESC_ANTSEL_D(txdesc)
+#define SET_TX_DESC_ANT_MAPD_8197F(txdesc, value) \
+ SET_TX_DESC_ANT_MAPD(txdesc, value)
+#define GET_TX_DESC_ANT_MAPD_8197F(txdesc) GET_TX_DESC_ANT_MAPD(txdesc)
+#define SET_TX_DESC_ANT_MAPC_8197F(txdesc, value) \
+ SET_TX_DESC_ANT_MAPC(txdesc, value)
+#define GET_TX_DESC_ANT_MAPC_8197F(txdesc) GET_TX_DESC_ANT_MAPC(txdesc)
+#define SET_TX_DESC_ANT_MAPB_8197F(txdesc, value) \
+ SET_TX_DESC_ANT_MAPB(txdesc, value)
+#define GET_TX_DESC_ANT_MAPB_8197F(txdesc) GET_TX_DESC_ANT_MAPB(txdesc)
+#define SET_TX_DESC_ANT_MAPA_8197F(txdesc, value) \
+ SET_TX_DESC_ANT_MAPA(txdesc, value)
+#define GET_TX_DESC_ANT_MAPA_8197F(txdesc) GET_TX_DESC_ANT_MAPA(txdesc)
+#define SET_TX_DESC_ANTSEL_C_8197F(txdesc, value) \
+ SET_TX_DESC_ANTSEL_C(txdesc, value)
+#define GET_TX_DESC_ANTSEL_C_8197F(txdesc) GET_TX_DESC_ANTSEL_C(txdesc)
+#define SET_TX_DESC_ANTSEL_B_8197F(txdesc, value) \
+ SET_TX_DESC_ANTSEL_B(txdesc, value)
+#define GET_TX_DESC_ANTSEL_B_8197F(txdesc) GET_TX_DESC_ANTSEL_B(txdesc)
+#define SET_TX_DESC_ANTSEL_A_8197F(txdesc, value) \
+ SET_TX_DESC_ANTSEL_A(txdesc, value)
+#define GET_TX_DESC_ANTSEL_A_8197F(txdesc) GET_TX_DESC_ANTSEL_A(txdesc)
+#define SET_TX_DESC_MBSSID_8197F(txdesc, value) \
+ SET_TX_DESC_MBSSID(txdesc, value)
+#define GET_TX_DESC_MBSSID_8197F(txdesc) GET_TX_DESC_MBSSID(txdesc)
+#define SET_TX_DESC_SW_DEFINE_8197F(txdesc, value) \
+ SET_TX_DESC_SW_DEFINE(txdesc, value)
+#define GET_TX_DESC_SW_DEFINE_8197F(txdesc) GET_TX_DESC_SW_DEFINE(txdesc)
/*TXDESC_WORD7*/
-#define SET_TX_DESC_DMA_TXAGG_NUM_8197F(__pTxDesc, __Value) SET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc, __Value)
-#define GET_TX_DESC_DMA_TXAGG_NUM_8197F(__pTxDesc) GET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc)
-#define SET_TX_DESC_FINAL_DATA_RATE_8197F(__pTxDesc, __Value) SET_TX_DESC_FINAL_DATA_RATE(__pTxDesc, __Value)
-#define GET_TX_DESC_FINAL_DATA_RATE_8197F(__pTxDesc) GET_TX_DESC_FINAL_DATA_RATE(__pTxDesc)
-#define SET_TX_DESC_NTX_MAP_8197F(__pTxDesc, __Value) SET_TX_DESC_NTX_MAP(__pTxDesc, __Value)
-#define GET_TX_DESC_NTX_MAP_8197F(__pTxDesc) GET_TX_DESC_NTX_MAP(__pTxDesc)
-#define SET_TX_DESC_TX_BUFF_SIZE_8197F(__pTxDesc, __Value) SET_TX_DESC_TX_BUFF_SIZE(__pTxDesc, __Value)
-#define GET_TX_DESC_TX_BUFF_SIZE_8197F(__pTxDesc) GET_TX_DESC_TX_BUFF_SIZE(__pTxDesc)
-#define SET_TX_DESC_TXDESC_CHECKSUM_8197F(__pTxDesc, __Value) SET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc, __Value)
-#define GET_TX_DESC_TXDESC_CHECKSUM_8197F(__pTxDesc) GET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc)
-#define SET_TX_DESC_TIMESTAMP_8197F(__pTxDesc, __Value) SET_TX_DESC_TIMESTAMP(__pTxDesc, __Value)
-#define GET_TX_DESC_TIMESTAMP_8197F(__pTxDesc) GET_TX_DESC_TIMESTAMP(__pTxDesc)
+#define SET_TX_DESC_DMA_TXAGG_NUM_8197F(txdesc, value) \
+ SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value)
+#define GET_TX_DESC_DMA_TXAGG_NUM_8197F(txdesc) \
+ GET_TX_DESC_DMA_TXAGG_NUM(txdesc)
+#define SET_TX_DESC_FINAL_DATA_RATE_8197F(txdesc, value) \
+ SET_TX_DESC_FINAL_DATA_RATE(txdesc, value)
+#define GET_TX_DESC_FINAL_DATA_RATE_8197F(txdesc) \
+ GET_TX_DESC_FINAL_DATA_RATE(txdesc)
+#define SET_TX_DESC_NTX_MAP_8197F(txdesc, value) \
+ SET_TX_DESC_NTX_MAP(txdesc, value)
+#define GET_TX_DESC_NTX_MAP_8197F(txdesc) GET_TX_DESC_NTX_MAP(txdesc)
+#define SET_TX_DESC_TX_BUFF_SIZE_8197F(txdesc, value) \
+ SET_TX_DESC_TX_BUFF_SIZE(txdesc, value)
+#define GET_TX_DESC_TX_BUFF_SIZE_8197F(txdesc) GET_TX_DESC_TX_BUFF_SIZE(txdesc)
+#define SET_TX_DESC_TXDESC_CHECKSUM_8197F(txdesc, value) \
+ SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value)
+#define GET_TX_DESC_TXDESC_CHECKSUM_8197F(txdesc) \
+ GET_TX_DESC_TXDESC_CHECKSUM(txdesc)
+#define SET_TX_DESC_TIMESTAMP_8197F(txdesc, value) \
+ SET_TX_DESC_TIMESTAMP(txdesc, value)
+#define GET_TX_DESC_TIMESTAMP_8197F(txdesc) GET_TX_DESC_TIMESTAMP(txdesc)
/*TXDESC_WORD8*/
-#define SET_TX_DESC_TXWIFI_CP_8197F(__pTxDesc, __Value) SET_TX_DESC_TXWIFI_CP(__pTxDesc, __Value)
-#define GET_TX_DESC_TXWIFI_CP_8197F(__pTxDesc) GET_TX_DESC_TXWIFI_CP(__pTxDesc)
-#define SET_TX_DESC_MAC_CP_8197F(__pTxDesc, __Value) SET_TX_DESC_MAC_CP(__pTxDesc, __Value)
-#define GET_TX_DESC_MAC_CP_8197F(__pTxDesc) GET_TX_DESC_MAC_CP(__pTxDesc)
-#define SET_TX_DESC_STW_PKTRE_DIS_8197F(__pTxDesc, __Value) SET_TX_DESC_STW_PKTRE_DIS(__pTxDesc, __Value)
-#define GET_TX_DESC_STW_PKTRE_DIS_8197F(__pTxDesc) GET_TX_DESC_STW_PKTRE_DIS(__pTxDesc)
-#define SET_TX_DESC_STW_RB_DIS_8197F(__pTxDesc, __Value) SET_TX_DESC_STW_RB_DIS(__pTxDesc, __Value)
-#define GET_TX_DESC_STW_RB_DIS_8197F(__pTxDesc) GET_TX_DESC_STW_RB_DIS(__pTxDesc)
-#define SET_TX_DESC_STW_RATE_DIS_8197F(__pTxDesc, __Value) SET_TX_DESC_STW_RATE_DIS(__pTxDesc, __Value)
-#define GET_TX_DESC_STW_RATE_DIS_8197F(__pTxDesc) GET_TX_DESC_STW_RATE_DIS(__pTxDesc)
-#define SET_TX_DESC_STW_ANT_DIS_8197F(__pTxDesc, __Value) SET_TX_DESC_STW_ANT_DIS(__pTxDesc, __Value)
-#define GET_TX_DESC_STW_ANT_DIS_8197F(__pTxDesc) GET_TX_DESC_STW_ANT_DIS(__pTxDesc)
-#define SET_TX_DESC_STW_EN_8197F(__pTxDesc, __Value) SET_TX_DESC_STW_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_STW_EN_8197F(__pTxDesc) GET_TX_DESC_STW_EN(__pTxDesc)
-#define SET_TX_DESC_SMH_EN_8197F(__pTxDesc, __Value) SET_TX_DESC_SMH_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_SMH_EN_8197F(__pTxDesc) GET_TX_DESC_SMH_EN(__pTxDesc)
-#define SET_TX_DESC_TAILPAGE_L_8197F(__pTxDesc, __Value) SET_TX_DESC_TAILPAGE_L(__pTxDesc, __Value)
-#define GET_TX_DESC_TAILPAGE_L_8197F(__pTxDesc) GET_TX_DESC_TAILPAGE_L(__pTxDesc)
-#define SET_TX_DESC_SDIO_DMASEQ_8197F(__pTxDesc, __Value) SET_TX_DESC_SDIO_DMASEQ(__pTxDesc, __Value)
-#define GET_TX_DESC_SDIO_DMASEQ_8197F(__pTxDesc) GET_TX_DESC_SDIO_DMASEQ(__pTxDesc)
-#define SET_TX_DESC_NEXTHEADPAGE_L_8197F(__pTxDesc, __Value) SET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc, __Value)
-#define GET_TX_DESC_NEXTHEADPAGE_L_8197F(__pTxDesc) GET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc)
-#define SET_TX_DESC_EN_HWSEQ_8197F(__pTxDesc, __Value) SET_TX_DESC_EN_HWSEQ(__pTxDesc, __Value)
-#define GET_TX_DESC_EN_HWSEQ_8197F(__pTxDesc) GET_TX_DESC_EN_HWSEQ(__pTxDesc)
-#define SET_TX_DESC_EN_HWEXSEQ_8197F(__pTxDesc, __Value) SET_TX_DESC_EN_HWEXSEQ(__pTxDesc, __Value)
-#define GET_TX_DESC_EN_HWEXSEQ_8197F(__pTxDesc) GET_TX_DESC_EN_HWEXSEQ(__pTxDesc)
-#define SET_TX_DESC_DATA_RC_8197F(__pTxDesc, __Value) SET_TX_DESC_DATA_RC(__pTxDesc, __Value)
-#define GET_TX_DESC_DATA_RC_8197F(__pTxDesc) GET_TX_DESC_DATA_RC(__pTxDesc)
-#define SET_TX_DESC_BAR_RTY_TH_8197F(__pTxDesc, __Value) SET_TX_DESC_BAR_RTY_TH(__pTxDesc, __Value)
-#define GET_TX_DESC_BAR_RTY_TH_8197F(__pTxDesc) GET_TX_DESC_BAR_RTY_TH(__pTxDesc)
-#define SET_TX_DESC_RTS_RC_8197F(__pTxDesc, __Value) SET_TX_DESC_RTS_RC(__pTxDesc, __Value)
-#define GET_TX_DESC_RTS_RC_8197F(__pTxDesc) GET_TX_DESC_RTS_RC(__pTxDesc)
+#define SET_TX_DESC_TXWIFI_CP_8197F(txdesc, value) \
+ SET_TX_DESC_TXWIFI_CP(txdesc, value)
+#define GET_TX_DESC_TXWIFI_CP_8197F(txdesc) GET_TX_DESC_TXWIFI_CP(txdesc)
+#define SET_TX_DESC_MAC_CP_8197F(txdesc, value) \
+ SET_TX_DESC_MAC_CP(txdesc, value)
+#define GET_TX_DESC_MAC_CP_8197F(txdesc) GET_TX_DESC_MAC_CP(txdesc)
+#define SET_TX_DESC_STW_PKTRE_DIS_8197F(txdesc, value) \
+ SET_TX_DESC_STW_PKTRE_DIS(txdesc, value)
+#define GET_TX_DESC_STW_PKTRE_DIS_8197F(txdesc) \
+ GET_TX_DESC_STW_PKTRE_DIS(txdesc)
+#define SET_TX_DESC_STW_RB_DIS_8197F(txdesc, value) \
+ SET_TX_DESC_STW_RB_DIS(txdesc, value)
+#define GET_TX_DESC_STW_RB_DIS_8197F(txdesc) GET_TX_DESC_STW_RB_DIS(txdesc)
+#define SET_TX_DESC_STW_RATE_DIS_8197F(txdesc, value) \
+ SET_TX_DESC_STW_RATE_DIS(txdesc, value)
+#define GET_TX_DESC_STW_RATE_DIS_8197F(txdesc) GET_TX_DESC_STW_RATE_DIS(txdesc)
+#define SET_TX_DESC_STW_ANT_DIS_8197F(txdesc, value) \
+ SET_TX_DESC_STW_ANT_DIS(txdesc, value)
+#define GET_TX_DESC_STW_ANT_DIS_8197F(txdesc) GET_TX_DESC_STW_ANT_DIS(txdesc)
+#define SET_TX_DESC_STW_EN_8197F(txdesc, value) \
+ SET_TX_DESC_STW_EN(txdesc, value)
+#define GET_TX_DESC_STW_EN_8197F(txdesc) GET_TX_DESC_STW_EN(txdesc)
+#define SET_TX_DESC_SMH_EN_8197F(txdesc, value) \
+ SET_TX_DESC_SMH_EN(txdesc, value)
+#define GET_TX_DESC_SMH_EN_8197F(txdesc) GET_TX_DESC_SMH_EN(txdesc)
+#define SET_TX_DESC_TAILPAGE_L_8197F(txdesc, value) \
+ SET_TX_DESC_TAILPAGE_L(txdesc, value)
+#define GET_TX_DESC_TAILPAGE_L_8197F(txdesc) GET_TX_DESC_TAILPAGE_L(txdesc)
+#define SET_TX_DESC_SDIO_DMASEQ_8197F(txdesc, value) \
+ SET_TX_DESC_SDIO_DMASEQ(txdesc, value)
+#define GET_TX_DESC_SDIO_DMASEQ_8197F(txdesc) GET_TX_DESC_SDIO_DMASEQ(txdesc)
+#define SET_TX_DESC_NEXTHEADPAGE_L_8197F(txdesc, value) \
+ SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value)
+#define GET_TX_DESC_NEXTHEADPAGE_L_8197F(txdesc) \
+ GET_TX_DESC_NEXTHEADPAGE_L(txdesc)
+#define SET_TX_DESC_EN_HWSEQ_8197F(txdesc, value) \
+ SET_TX_DESC_EN_HWSEQ(txdesc, value)
+#define GET_TX_DESC_EN_HWSEQ_8197F(txdesc) GET_TX_DESC_EN_HWSEQ(txdesc)
+#define SET_TX_DESC_EN_HWEXSEQ_8197F(txdesc, value) \
+ SET_TX_DESC_EN_HWEXSEQ(txdesc, value)
+#define GET_TX_DESC_EN_HWEXSEQ_8197F(txdesc) GET_TX_DESC_EN_HWEXSEQ(txdesc)
+#define SET_TX_DESC_DATA_RC_8197F(txdesc, value) \
+ SET_TX_DESC_DATA_RC(txdesc, value)
+#define GET_TX_DESC_DATA_RC_8197F(txdesc) GET_TX_DESC_DATA_RC(txdesc)
+#define SET_TX_DESC_BAR_RTY_TH_8197F(txdesc, value) \
+ SET_TX_DESC_BAR_RTY_TH(txdesc, value)
+#define GET_TX_DESC_BAR_RTY_TH_8197F(txdesc) GET_TX_DESC_BAR_RTY_TH(txdesc)
+#define SET_TX_DESC_RTS_RC_8197F(txdesc, value) \
+ SET_TX_DESC_RTS_RC(txdesc, value)
+#define GET_TX_DESC_RTS_RC_8197F(txdesc) GET_TX_DESC_RTS_RC(txdesc)
/*TXDESC_WORD9*/
-#define SET_TX_DESC_TAILPAGE_H_8197F(__pTxDesc, __Value) SET_TX_DESC_TAILPAGE_H(__pTxDesc, __Value)
-#define GET_TX_DESC_TAILPAGE_H_8197F(__pTxDesc) GET_TX_DESC_TAILPAGE_H(__pTxDesc)
-#define SET_TX_DESC_NEXTHEADPAGE_H_8197F(__pTxDesc, __Value) SET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc, __Value)
-#define GET_TX_DESC_NEXTHEADPAGE_H_8197F(__pTxDesc) GET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc)
-#define SET_TX_DESC_SW_SEQ_8197F(__pTxDesc, __Value) SET_TX_DESC_SW_SEQ(__pTxDesc, __Value)
-#define GET_TX_DESC_SW_SEQ_8197F(__pTxDesc) GET_TX_DESC_SW_SEQ(__pTxDesc)
-#define SET_TX_DESC_TXBF_PATH_8197F(__pTxDesc, __Value) SET_TX_DESC_TXBF_PATH(__pTxDesc, __Value)
-#define GET_TX_DESC_TXBF_PATH_8197F(__pTxDesc) GET_TX_DESC_TXBF_PATH(__pTxDesc)
-#define SET_TX_DESC_PADDING_LEN_8197F(__pTxDesc, __Value) SET_TX_DESC_PADDING_LEN(__pTxDesc, __Value)
-#define GET_TX_DESC_PADDING_LEN_8197F(__pTxDesc) GET_TX_DESC_PADDING_LEN(__pTxDesc)
-#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8197F(__pTxDesc, __Value) SET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc, __Value)
-#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8197F(__pTxDesc) GET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc)
+#define SET_TX_DESC_TAILPAGE_H_8197F(txdesc, value) \
+ SET_TX_DESC_TAILPAGE_H(txdesc, value)
+#define GET_TX_DESC_TAILPAGE_H_8197F(txdesc) GET_TX_DESC_TAILPAGE_H(txdesc)
+#define SET_TX_DESC_NEXTHEADPAGE_H_8197F(txdesc, value) \
+ SET_TX_DESC_NEXTHEADPAGE_H(txdesc, value)
+#define GET_TX_DESC_NEXTHEADPAGE_H_8197F(txdesc) \
+ GET_TX_DESC_NEXTHEADPAGE_H(txdesc)
+#define SET_TX_DESC_SW_SEQ_8197F(txdesc, value) \
+ SET_TX_DESC_SW_SEQ(txdesc, value)
+#define GET_TX_DESC_SW_SEQ_8197F(txdesc) GET_TX_DESC_SW_SEQ(txdesc)
+#define SET_TX_DESC_TXBF_PATH_8197F(txdesc, value) \
+ SET_TX_DESC_TXBF_PATH(txdesc, value)
+#define GET_TX_DESC_TXBF_PATH_8197F(txdesc) GET_TX_DESC_TXBF_PATH(txdesc)
+#define SET_TX_DESC_PADDING_LEN_8197F(txdesc, value) \
+ SET_TX_DESC_PADDING_LEN(txdesc, value)
+#define GET_TX_DESC_PADDING_LEN_8197F(txdesc) GET_TX_DESC_PADDING_LEN(txdesc)
+#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8197F(txdesc, value) \
+ SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value)
+#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8197F(txdesc) \
+ GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc)
/*WORD10*/
-#define SET_TX_DESC_MU_DATARATE_8197F(__pTxDesc, __Value) SET_TX_DESC_MU_DATARATE(__pTxDesc, __Value)
-#define GET_TX_DESC_MU_DATARATE_8197F(__pTxDesc) GET_TX_DESC_MU_DATARATE(__pTxDesc)
-#define SET_TX_DESC_MU_RC_8197F(__pTxDesc, __Value) SET_TX_DESC_MU_RC(__pTxDesc, __Value)
-#define GET_TX_DESC_MU_RC_8197F(__pTxDesc) GET_TX_DESC_MU_RC(__pTxDesc)
-#define SET_TX_DESC_SND_PKT_SEL_8197F(__pTxDesc, __Value) SET_TX_DESC_SND_PKT_SEL(__pTxDesc, __Value)
-#define GET_TX_DESC_SND_PKT_SEL_8197F(__pTxDesc) GET_TX_DESC_SND_PKT_SEL(__pTxDesc)
-
#endif
#if (HALMAC_8821C_SUPPORT)
/*TXDESC_WORD0*/
-#define SET_TX_DESC_DISQSELSEQ_8821C(__pTxDesc, __Value) SET_TX_DESC_DISQSELSEQ(__pTxDesc, __Value)
-#define GET_TX_DESC_DISQSELSEQ_8821C(__pTxDesc) GET_TX_DESC_DISQSELSEQ(__pTxDesc)
-#define SET_TX_DESC_GF_8821C(__pTxDesc, __Value) SET_TX_DESC_GF(__pTxDesc, __Value)
-#define GET_TX_DESC_GF_8821C(__pTxDesc) GET_TX_DESC_GF(__pTxDesc)
-#define SET_TX_DESC_NO_ACM_8821C(__pTxDesc, __Value) SET_TX_DESC_NO_ACM(__pTxDesc, __Value)
-#define GET_TX_DESC_NO_ACM_8821C(__pTxDesc) GET_TX_DESC_NO_ACM(__pTxDesc)
-#define SET_TX_DESC_BCNPKT_TSF_CTRL_8821C(__pTxDesc, __Value) SET_TX_DESC_BCNPKT_TSF_CTRL(__pTxDesc, __Value)
-#define GET_TX_DESC_BCNPKT_TSF_CTRL_8821C(__pTxDesc) GET_TX_DESC_BCNPKT_TSF_CTRL(__pTxDesc)
-#define SET_TX_DESC_AMSDU_PAD_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_AMSDU_PAD_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_AMSDU_PAD_EN_8821C(__pTxDesc) GET_TX_DESC_AMSDU_PAD_EN(__pTxDesc)
-#define SET_TX_DESC_LS_8821C(__pTxDesc, __Value) SET_TX_DESC_LS(__pTxDesc, __Value)
-#define GET_TX_DESC_LS_8821C(__pTxDesc) GET_TX_DESC_LS(__pTxDesc)
-#define SET_TX_DESC_HTC_8821C(__pTxDesc, __Value) SET_TX_DESC_HTC(__pTxDesc, __Value)
-#define GET_TX_DESC_HTC_8821C(__pTxDesc) GET_TX_DESC_HTC(__pTxDesc)
-#define SET_TX_DESC_BMC_8821C(__pTxDesc, __Value) SET_TX_DESC_BMC(__pTxDesc, __Value)
-#define GET_TX_DESC_BMC_8821C(__pTxDesc) GET_TX_DESC_BMC(__pTxDesc)
-#define SET_TX_DESC_OFFSET_8821C(__pTxDesc, __Value) SET_TX_DESC_OFFSET(__pTxDesc, __Value)
-#define GET_TX_DESC_OFFSET_8821C(__pTxDesc) GET_TX_DESC_OFFSET(__pTxDesc)
-#define SET_TX_DESC_TXPKTSIZE_8821C(__pTxDesc, __Value) SET_TX_DESC_TXPKTSIZE(__pTxDesc, __Value)
-#define GET_TX_DESC_TXPKTSIZE_8821C(__pTxDesc) GET_TX_DESC_TXPKTSIZE(__pTxDesc)
-
-/*TXDESC_WORD1*/
-
-#define SET_TX_DESC_MOREDATA_8821C(__pTxDesc, __Value) SET_TX_DESC_MOREDATA(__pTxDesc, __Value)
-#define GET_TX_DESC_MOREDATA_8821C(__pTxDesc) GET_TX_DESC_MOREDATA(__pTxDesc)
-#define SET_TX_DESC_PKT_OFFSET_8821C(__pTxDesc, __Value) SET_TX_DESC_PKT_OFFSET(__pTxDesc, __Value)
-#define GET_TX_DESC_PKT_OFFSET_8821C(__pTxDesc) GET_TX_DESC_PKT_OFFSET(__pTxDesc)
-#define SET_TX_DESC_SEC_TYPE_8821C(__pTxDesc, __Value) SET_TX_DESC_SEC_TYPE(__pTxDesc, __Value)
-#define GET_TX_DESC_SEC_TYPE_8821C(__pTxDesc) GET_TX_DESC_SEC_TYPE(__pTxDesc)
-#define SET_TX_DESC_EN_DESC_ID_8821C(__pTxDesc, __Value) SET_TX_DESC_EN_DESC_ID(__pTxDesc, __Value)
-#define GET_TX_DESC_EN_DESC_ID_8821C(__pTxDesc) GET_TX_DESC_EN_DESC_ID(__pTxDesc)
-#define SET_TX_DESC_RATE_ID_8821C(__pTxDesc, __Value) SET_TX_DESC_RATE_ID(__pTxDesc, __Value)
-#define GET_TX_DESC_RATE_ID_8821C(__pTxDesc) GET_TX_DESC_RATE_ID(__pTxDesc)
-#define SET_TX_DESC_PIFS_8821C(__pTxDesc, __Value) SET_TX_DESC_PIFS(__pTxDesc, __Value)
-#define GET_TX_DESC_PIFS_8821C(__pTxDesc) GET_TX_DESC_PIFS(__pTxDesc)
-#define SET_TX_DESC_LSIG_TXOP_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_LSIG_TXOP_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_LSIG_TXOP_EN_8821C(__pTxDesc) GET_TX_DESC_LSIG_TXOP_EN(__pTxDesc)
-#define SET_TX_DESC_RD_NAV_EXT_8821C(__pTxDesc, __Value) SET_TX_DESC_RD_NAV_EXT(__pTxDesc, __Value)
-#define GET_TX_DESC_RD_NAV_EXT_8821C(__pTxDesc) GET_TX_DESC_RD_NAV_EXT(__pTxDesc)
-#define SET_TX_DESC_QSEL_8821C(__pTxDesc, __Value) SET_TX_DESC_QSEL(__pTxDesc, __Value)
-#define GET_TX_DESC_QSEL_8821C(__pTxDesc) GET_TX_DESC_QSEL(__pTxDesc)
-#define SET_TX_DESC_MACID_8821C(__pTxDesc, __Value) SET_TX_DESC_MACID(__pTxDesc, __Value)
-#define GET_TX_DESC_MACID_8821C(__pTxDesc) GET_TX_DESC_MACID(__pTxDesc)
+#define SET_TX_DESC_DISQSELSEQ_8821C(txdesc, value) \
+ SET_TX_DESC_DISQSELSEQ(txdesc, value)
+#define GET_TX_DESC_DISQSELSEQ_8821C(txdesc) GET_TX_DESC_DISQSELSEQ(txdesc)
+#define SET_TX_DESC_GF_8821C(txdesc, value) SET_TX_DESC_GF(txdesc, value)
+#define GET_TX_DESC_GF_8821C(txdesc) GET_TX_DESC_GF(txdesc)
+#define SET_TX_DESC_NO_ACM_8821C(txdesc, value) \
+ SET_TX_DESC_NO_ACM(txdesc, value)
+#define GET_TX_DESC_NO_ACM_8821C(txdesc) GET_TX_DESC_NO_ACM(txdesc)
+#define SET_TX_DESC_BCNPKT_TSF_CTRL_8821C(txdesc, value) \
+ SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value)
+#define GET_TX_DESC_BCNPKT_TSF_CTRL_8821C(txdesc) \
+ GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc)
+#define SET_TX_DESC_AMSDU_PAD_EN_8821C(txdesc, value) \
+ SET_TX_DESC_AMSDU_PAD_EN(txdesc, value)
+#define GET_TX_DESC_AMSDU_PAD_EN_8821C(txdesc) GET_TX_DESC_AMSDU_PAD_EN(txdesc)
+#define SET_TX_DESC_LS_8821C(txdesc, value) SET_TX_DESC_LS(txdesc, value)
+#define GET_TX_DESC_LS_8821C(txdesc) GET_TX_DESC_LS(txdesc)
+#define SET_TX_DESC_HTC_8821C(txdesc, value) SET_TX_DESC_HTC(txdesc, value)
+#define GET_TX_DESC_HTC_8821C(txdesc) GET_TX_DESC_HTC(txdesc)
+#define SET_TX_DESC_BMC_8821C(txdesc, value) SET_TX_DESC_BMC(txdesc, value)
+#define GET_TX_DESC_BMC_8821C(txdesc) GET_TX_DESC_BMC(txdesc)
+#define SET_TX_DESC_OFFSET_8821C(txdesc, value) \
+ SET_TX_DESC_OFFSET(txdesc, value)
+#define GET_TX_DESC_OFFSET_8821C(txdesc) GET_TX_DESC_OFFSET(txdesc)
+#define SET_TX_DESC_TXPKTSIZE_8821C(txdesc, value) \
+ SET_TX_DESC_TXPKTSIZE(txdesc, value)
+#define GET_TX_DESC_TXPKTSIZE_8821C(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc)
+
+/*WORD1*/
+
+#define SET_TX_DESC_MOREDATA_8821C(txdesc, value) \
+ SET_TX_DESC_MOREDATA(txdesc, value)
+#define GET_TX_DESC_MOREDATA_8821C(txdesc) GET_TX_DESC_MOREDATA(txdesc)
+#define SET_TX_DESC_PKT_OFFSET_8821C(txdesc, value) \
+ SET_TX_DESC_PKT_OFFSET(txdesc, value)
+#define GET_TX_DESC_PKT_OFFSET_8821C(txdesc) GET_TX_DESC_PKT_OFFSET(txdesc)
+#define SET_TX_DESC_SEC_TYPE_8821C(txdesc, value) \
+ SET_TX_DESC_SEC_TYPE(txdesc, value)
+#define GET_TX_DESC_SEC_TYPE_8821C(txdesc) GET_TX_DESC_SEC_TYPE(txdesc)
+#define SET_TX_DESC_EN_DESC_ID_8821C(txdesc, value) \
+ SET_TX_DESC_EN_DESC_ID(txdesc, value)
+#define GET_TX_DESC_EN_DESC_ID_8821C(txdesc) GET_TX_DESC_EN_DESC_ID(txdesc)
+#define SET_TX_DESC_RATE_ID_8821C(txdesc, value) \
+ SET_TX_DESC_RATE_ID(txdesc, value)
+#define GET_TX_DESC_RATE_ID_8821C(txdesc) GET_TX_DESC_RATE_ID(txdesc)
+#define SET_TX_DESC_PIFS_8821C(txdesc, value) SET_TX_DESC_PIFS(txdesc, value)
+#define GET_TX_DESC_PIFS_8821C(txdesc) GET_TX_DESC_PIFS(txdesc)
+#define SET_TX_DESC_LSIG_TXOP_EN_8821C(txdesc, value) \
+ SET_TX_DESC_LSIG_TXOP_EN(txdesc, value)
+#define GET_TX_DESC_LSIG_TXOP_EN_8821C(txdesc) GET_TX_DESC_LSIG_TXOP_EN(txdesc)
+#define SET_TX_DESC_RD_NAV_EXT_8821C(txdesc, value) \
+ SET_TX_DESC_RD_NAV_EXT(txdesc, value)
+#define GET_TX_DESC_RD_NAV_EXT_8821C(txdesc) GET_TX_DESC_RD_NAV_EXT(txdesc)
+#define SET_TX_DESC_QSEL_8821C(txdesc, value) SET_TX_DESC_QSEL(txdesc, value)
+#define GET_TX_DESC_QSEL_8821C(txdesc) GET_TX_DESC_QSEL(txdesc)
+#define SET_TX_DESC_MACID_8821C(txdesc, value) SET_TX_DESC_MACID(txdesc, value)
+#define GET_TX_DESC_MACID_8821C(txdesc) GET_TX_DESC_MACID(txdesc)
/*TXDESC_WORD2*/
-#define SET_TX_DESC_HW_AES_IV_8821C(__pTxDesc, __Value) SET_TX_DESC_HW_AES_IV(__pTxDesc, __Value)
-#define GET_TX_DESC_HW_AES_IV_8821C(__pTxDesc) GET_TX_DESC_HW_AES_IV(__pTxDesc)
-#define SET_TX_DESC_FTM_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_FTM_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_FTM_EN_8821C(__pTxDesc) GET_TX_DESC_FTM_EN(__pTxDesc)
-#define SET_TX_DESC_G_ID_8821C(__pTxDesc, __Value) SET_TX_DESC_G_ID(__pTxDesc, __Value)
-#define GET_TX_DESC_G_ID_8821C(__pTxDesc) GET_TX_DESC_G_ID(__pTxDesc)
-#define SET_TX_DESC_BT_NULL_8821C(__pTxDesc, __Value) SET_TX_DESC_BT_NULL(__pTxDesc, __Value)
-#define GET_TX_DESC_BT_NULL_8821C(__pTxDesc) GET_TX_DESC_BT_NULL(__pTxDesc)
-#define SET_TX_DESC_AMPDU_DENSITY_8821C(__pTxDesc, __Value) SET_TX_DESC_AMPDU_DENSITY(__pTxDesc, __Value)
-#define GET_TX_DESC_AMPDU_DENSITY_8821C(__pTxDesc) GET_TX_DESC_AMPDU_DENSITY(__pTxDesc)
-#define SET_TX_DESC_SPE_RPT_8821C(__pTxDesc, __Value) SET_TX_DESC_SPE_RPT(__pTxDesc, __Value)
-#define GET_TX_DESC_SPE_RPT_8821C(__pTxDesc) GET_TX_DESC_SPE_RPT(__pTxDesc)
-#define SET_TX_DESC_RAW_8821C(__pTxDesc, __Value) SET_TX_DESC_RAW(__pTxDesc, __Value)
-#define GET_TX_DESC_RAW_8821C(__pTxDesc) GET_TX_DESC_RAW(__pTxDesc)
-#define SET_TX_DESC_MOREFRAG_8821C(__pTxDesc, __Value) SET_TX_DESC_MOREFRAG(__pTxDesc, __Value)
-#define GET_TX_DESC_MOREFRAG_8821C(__pTxDesc) GET_TX_DESC_MOREFRAG(__pTxDesc)
-#define SET_TX_DESC_BK_8821C(__pTxDesc, __Value) SET_TX_DESC_BK(__pTxDesc, __Value)
-#define GET_TX_DESC_BK_8821C(__pTxDesc) GET_TX_DESC_BK(__pTxDesc)
-#define SET_TX_DESC_NULL_1_8821C(__pTxDesc, __Value) SET_TX_DESC_NULL_1(__pTxDesc, __Value)
-#define GET_TX_DESC_NULL_1_8821C(__pTxDesc) GET_TX_DESC_NULL_1(__pTxDesc)
-#define SET_TX_DESC_NULL_0_8821C(__pTxDesc, __Value) SET_TX_DESC_NULL_0(__pTxDesc, __Value)
-#define GET_TX_DESC_NULL_0_8821C(__pTxDesc) GET_TX_DESC_NULL_0(__pTxDesc)
-#define SET_TX_DESC_RDG_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_RDG_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_RDG_EN_8821C(__pTxDesc) GET_TX_DESC_RDG_EN(__pTxDesc)
-#define SET_TX_DESC_AGG_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_AGG_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_AGG_EN_8821C(__pTxDesc) GET_TX_DESC_AGG_EN(__pTxDesc)
-#define SET_TX_DESC_CCA_RTS_8821C(__pTxDesc, __Value) SET_TX_DESC_CCA_RTS(__pTxDesc, __Value)
-#define GET_TX_DESC_CCA_RTS_8821C(__pTxDesc) GET_TX_DESC_CCA_RTS(__pTxDesc)
-#define SET_TX_DESC_TRI_FRAME_8821C(__pTxDesc, __Value) SET_TX_DESC_TRI_FRAME(__pTxDesc, __Value)
-#define GET_TX_DESC_TRI_FRAME_8821C(__pTxDesc) GET_TX_DESC_TRI_FRAME(__pTxDesc)
-#define SET_TX_DESC_P_AID_8821C(__pTxDesc, __Value) SET_TX_DESC_P_AID(__pTxDesc, __Value)
-#define GET_TX_DESC_P_AID_8821C(__pTxDesc) GET_TX_DESC_P_AID(__pTxDesc)
+#define SET_TX_DESC_HW_AES_IV_8821C(txdesc, value) \
+ SET_TX_DESC_HW_AES_IV(txdesc, value)
+#define GET_TX_DESC_HW_AES_IV_8821C(txdesc) GET_TX_DESC_HW_AES_IV(txdesc)
+#define SET_TX_DESC_FTM_EN_8821C(txdesc, value) \
+ SET_TX_DESC_FTM_EN(txdesc, value)
+#define GET_TX_DESC_FTM_EN_8821C(txdesc) GET_TX_DESC_FTM_EN(txdesc)
+#define SET_TX_DESC_G_ID_8821C(txdesc, value) SET_TX_DESC_G_ID(txdesc, value)
+#define GET_TX_DESC_G_ID_8821C(txdesc) GET_TX_DESC_G_ID(txdesc)
+#define SET_TX_DESC_BT_NULL_8821C(txdesc, value) \
+ SET_TX_DESC_BT_NULL(txdesc, value)
+#define GET_TX_DESC_BT_NULL_8821C(txdesc) GET_TX_DESC_BT_NULL(txdesc)
+#define SET_TX_DESC_AMPDU_DENSITY_8821C(txdesc, value) \
+ SET_TX_DESC_AMPDU_DENSITY(txdesc, value)
+#define GET_TX_DESC_AMPDU_DENSITY_8821C(txdesc) \
+ GET_TX_DESC_AMPDU_DENSITY(txdesc)
+#define SET_TX_DESC_SPE_RPT_8821C(txdesc, value) \
+ SET_TX_DESC_SPE_RPT(txdesc, value)
+#define GET_TX_DESC_SPE_RPT_8821C(txdesc) GET_TX_DESC_SPE_RPT(txdesc)
+#define SET_TX_DESC_RAW_8821C(txdesc, value) SET_TX_DESC_RAW(txdesc, value)
+#define GET_TX_DESC_RAW_8821C(txdesc) GET_TX_DESC_RAW(txdesc)
+#define SET_TX_DESC_MOREFRAG_8821C(txdesc, value) \
+ SET_TX_DESC_MOREFRAG(txdesc, value)
+#define GET_TX_DESC_MOREFRAG_8821C(txdesc) GET_TX_DESC_MOREFRAG(txdesc)
+#define SET_TX_DESC_BK_8821C(txdesc, value) SET_TX_DESC_BK(txdesc, value)
+#define GET_TX_DESC_BK_8821C(txdesc) GET_TX_DESC_BK(txdesc)
+#define SET_TX_DESC_NULL_1_8821C(txdesc, value) \
+ SET_TX_DESC_NULL_1(txdesc, value)
+#define GET_TX_DESC_NULL_1_8821C(txdesc) GET_TX_DESC_NULL_1(txdesc)
+#define SET_TX_DESC_NULL_0_8821C(txdesc, value) \
+ SET_TX_DESC_NULL_0(txdesc, value)
+#define GET_TX_DESC_NULL_0_8821C(txdesc) GET_TX_DESC_NULL_0(txdesc)
+#define SET_TX_DESC_RDG_EN_8821C(txdesc, value) \
+ SET_TX_DESC_RDG_EN(txdesc, value)
+#define GET_TX_DESC_RDG_EN_8821C(txdesc) GET_TX_DESC_RDG_EN(txdesc)
+#define SET_TX_DESC_AGG_EN_8821C(txdesc, value) \
+ SET_TX_DESC_AGG_EN(txdesc, value)
+#define GET_TX_DESC_AGG_EN_8821C(txdesc) GET_TX_DESC_AGG_EN(txdesc)
+#define SET_TX_DESC_CCA_RTS_8821C(txdesc, value) \
+ SET_TX_DESC_CCA_RTS(txdesc, value)
+#define GET_TX_DESC_CCA_RTS_8821C(txdesc) GET_TX_DESC_CCA_RTS(txdesc)
+#define SET_TX_DESC_TRI_FRAME_8821C(txdesc, value) \
+ SET_TX_DESC_TRI_FRAME(txdesc, value)
+#define GET_TX_DESC_TRI_FRAME_8821C(txdesc) GET_TX_DESC_TRI_FRAME(txdesc)
+#define SET_TX_DESC_P_AID_8821C(txdesc, value) SET_TX_DESC_P_AID(txdesc, value)
+#define GET_TX_DESC_P_AID_8821C(txdesc) GET_TX_DESC_P_AID(txdesc)
/*TXDESC_WORD3*/
-#define SET_TX_DESC_AMPDU_MAX_TIME_8821C(__pTxDesc, __Value) SET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc, __Value)
-#define GET_TX_DESC_AMPDU_MAX_TIME_8821C(__pTxDesc) GET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc)
-#define SET_TX_DESC_NDPA_8821C(__pTxDesc, __Value) SET_TX_DESC_NDPA(__pTxDesc, __Value)
-#define GET_TX_DESC_NDPA_8821C(__pTxDesc) GET_TX_DESC_NDPA(__pTxDesc)
-#define SET_TX_DESC_MAX_AGG_NUM_8821C(__pTxDesc, __Value) SET_TX_DESC_MAX_AGG_NUM(__pTxDesc, __Value)
-#define GET_TX_DESC_MAX_AGG_NUM_8821C(__pTxDesc) GET_TX_DESC_MAX_AGG_NUM(__pTxDesc)
-#define SET_TX_DESC_USE_MAX_TIME_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_USE_MAX_TIME_EN_8821C(__pTxDesc) GET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc)
-#define SET_TX_DESC_NAVUSEHDR_8821C(__pTxDesc, __Value) SET_TX_DESC_NAVUSEHDR(__pTxDesc, __Value)
-#define GET_TX_DESC_NAVUSEHDR_8821C(__pTxDesc) GET_TX_DESC_NAVUSEHDR(__pTxDesc)
-#define SET_TX_DESC_CHK_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_CHK_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_CHK_EN_8821C(__pTxDesc) GET_TX_DESC_CHK_EN(__pTxDesc)
-#define SET_TX_DESC_HW_RTS_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_HW_RTS_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_HW_RTS_EN_8821C(__pTxDesc) GET_TX_DESC_HW_RTS_EN(__pTxDesc)
-#define SET_TX_DESC_RTSEN_8821C(__pTxDesc, __Value) SET_TX_DESC_RTSEN(__pTxDesc, __Value)
-#define GET_TX_DESC_RTSEN_8821C(__pTxDesc) GET_TX_DESC_RTSEN(__pTxDesc)
-#define SET_TX_DESC_CTS2SELF_8821C(__pTxDesc, __Value) SET_TX_DESC_CTS2SELF(__pTxDesc, __Value)
-#define GET_TX_DESC_CTS2SELF_8821C(__pTxDesc) GET_TX_DESC_CTS2SELF(__pTxDesc)
-#define SET_TX_DESC_DISDATAFB_8821C(__pTxDesc, __Value) SET_TX_DESC_DISDATAFB(__pTxDesc, __Value)
-#define GET_TX_DESC_DISDATAFB_8821C(__pTxDesc) GET_TX_DESC_DISDATAFB(__pTxDesc)
-#define SET_TX_DESC_DISRTSFB_8821C(__pTxDesc, __Value) SET_TX_DESC_DISRTSFB(__pTxDesc, __Value)
-#define GET_TX_DESC_DISRTSFB_8821C(__pTxDesc) GET_TX_DESC_DISRTSFB(__pTxDesc)
-#define SET_TX_DESC_USE_RATE_8821C(__pTxDesc, __Value) SET_TX_DESC_USE_RATE(__pTxDesc, __Value)
-#define GET_TX_DESC_USE_RATE_8821C(__pTxDesc) GET_TX_DESC_USE_RATE(__pTxDesc)
-#define SET_TX_DESC_HW_SSN_SEL_8821C(__pTxDesc, __Value) SET_TX_DESC_HW_SSN_SEL(__pTxDesc, __Value)
-#define GET_TX_DESC_HW_SSN_SEL_8821C(__pTxDesc) GET_TX_DESC_HW_SSN_SEL(__pTxDesc)
-#define SET_TX_DESC_WHEADER_LEN_8821C(__pTxDesc, __Value) SET_TX_DESC_WHEADER_LEN(__pTxDesc, __Value)
-#define GET_TX_DESC_WHEADER_LEN_8821C(__pTxDesc) GET_TX_DESC_WHEADER_LEN(__pTxDesc)
+#define SET_TX_DESC_AMPDU_MAX_TIME_8821C(txdesc, value) \
+ SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value)
+#define GET_TX_DESC_AMPDU_MAX_TIME_8821C(txdesc) \
+ GET_TX_DESC_AMPDU_MAX_TIME(txdesc)
+#define SET_TX_DESC_NDPA_8821C(txdesc, value) SET_TX_DESC_NDPA(txdesc, value)
+#define GET_TX_DESC_NDPA_8821C(txdesc) GET_TX_DESC_NDPA(txdesc)
+#define SET_TX_DESC_MAX_AGG_NUM_8821C(txdesc, value) \
+ SET_TX_DESC_MAX_AGG_NUM(txdesc, value)
+#define GET_TX_DESC_MAX_AGG_NUM_8821C(txdesc) GET_TX_DESC_MAX_AGG_NUM(txdesc)
+#define SET_TX_DESC_USE_MAX_TIME_EN_8821C(txdesc, value) \
+ SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value)
+#define GET_TX_DESC_USE_MAX_TIME_EN_8821C(txdesc) \
+ GET_TX_DESC_USE_MAX_TIME_EN(txdesc)
+#define SET_TX_DESC_NAVUSEHDR_8821C(txdesc, value) \
+ SET_TX_DESC_NAVUSEHDR(txdesc, value)
+#define GET_TX_DESC_NAVUSEHDR_8821C(txdesc) GET_TX_DESC_NAVUSEHDR(txdesc)
+#define SET_TX_DESC_CHK_EN_8821C(txdesc, value) \
+ SET_TX_DESC_CHK_EN(txdesc, value)
+#define GET_TX_DESC_CHK_EN_8821C(txdesc) GET_TX_DESC_CHK_EN(txdesc)
+#define SET_TX_DESC_HW_RTS_EN_8821C(txdesc, value) \
+ SET_TX_DESC_HW_RTS_EN(txdesc, value)
+#define GET_TX_DESC_HW_RTS_EN_8821C(txdesc) GET_TX_DESC_HW_RTS_EN(txdesc)
+#define SET_TX_DESC_RTSEN_8821C(txdesc, value) SET_TX_DESC_RTSEN(txdesc, value)
+#define GET_TX_DESC_RTSEN_8821C(txdesc) GET_TX_DESC_RTSEN(txdesc)
+#define SET_TX_DESC_CTS2SELF_8821C(txdesc, value) \
+ SET_TX_DESC_CTS2SELF(txdesc, value)
+#define GET_TX_DESC_CTS2SELF_8821C(txdesc) GET_TX_DESC_CTS2SELF(txdesc)
+#define SET_TX_DESC_DISDATAFB_8821C(txdesc, value) \
+ SET_TX_DESC_DISDATAFB(txdesc, value)
+#define GET_TX_DESC_DISDATAFB_8821C(txdesc) GET_TX_DESC_DISDATAFB(txdesc)
+#define SET_TX_DESC_DISRTSFB_8821C(txdesc, value) \
+ SET_TX_DESC_DISRTSFB(txdesc, value)
+#define GET_TX_DESC_DISRTSFB_8821C(txdesc) GET_TX_DESC_DISRTSFB(txdesc)
+#define SET_TX_DESC_USE_RATE_8821C(txdesc, value) \
+ SET_TX_DESC_USE_RATE(txdesc, value)
+#define GET_TX_DESC_USE_RATE_8821C(txdesc) GET_TX_DESC_USE_RATE(txdesc)
+#define SET_TX_DESC_HW_SSN_SEL_8821C(txdesc, value) \
+ SET_TX_DESC_HW_SSN_SEL(txdesc, value)
+#define GET_TX_DESC_HW_SSN_SEL_8821C(txdesc) GET_TX_DESC_HW_SSN_SEL(txdesc)
+#define SET_TX_DESC_WHEADER_LEN_8821C(txdesc, value) \
+ SET_TX_DESC_WHEADER_LEN(txdesc, value)
+#define GET_TX_DESC_WHEADER_LEN_8821C(txdesc) GET_TX_DESC_WHEADER_LEN(txdesc)
/*TXDESC_WORD4*/
-#define SET_TX_DESC_PCTS_MASK_IDX_8821C(__pTxDesc, __Value) SET_TX_DESC_PCTS_MASK_IDX(__pTxDesc, __Value)
-#define GET_TX_DESC_PCTS_MASK_IDX_8821C(__pTxDesc) GET_TX_DESC_PCTS_MASK_IDX(__pTxDesc)
-#define SET_TX_DESC_PCTS_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_PCTS_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_PCTS_EN_8821C(__pTxDesc) GET_TX_DESC_PCTS_EN(__pTxDesc)
-#define SET_TX_DESC_RTSRATE_8821C(__pTxDesc, __Value) SET_TX_DESC_RTSRATE(__pTxDesc, __Value)
-#define GET_TX_DESC_RTSRATE_8821C(__pTxDesc) GET_TX_DESC_RTSRATE(__pTxDesc)
-#define SET_TX_DESC_RTS_DATA_RTY_LMT_8821C(__pTxDesc, __Value) SET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc, __Value)
-#define GET_TX_DESC_RTS_DATA_RTY_LMT_8821C(__pTxDesc) GET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc)
-#define SET_TX_DESC_RTY_LMT_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_RTY_LMT_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_RTY_LMT_EN_8821C(__pTxDesc) GET_TX_DESC_RTY_LMT_EN(__pTxDesc)
-#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8821C(__pTxDesc, __Value) SET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc, __Value)
-#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8821C(__pTxDesc) GET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc)
-#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8821C(__pTxDesc, __Value) SET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc, __Value)
-#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8821C(__pTxDesc) GET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc)
-#define SET_TX_DESC_TRY_RATE_8821C(__pTxDesc, __Value) SET_TX_DESC_TRY_RATE(__pTxDesc, __Value)
-#define GET_TX_DESC_TRY_RATE_8821C(__pTxDesc) GET_TX_DESC_TRY_RATE(__pTxDesc)
-#define SET_TX_DESC_DATARATE_8821C(__pTxDesc, __Value) SET_TX_DESC_DATARATE(__pTxDesc, __Value)
-#define GET_TX_DESC_DATARATE_8821C(__pTxDesc) GET_TX_DESC_DATARATE(__pTxDesc)
+#define SET_TX_DESC_PCTS_MASK_IDX_8821C(txdesc, value) \
+ SET_TX_DESC_PCTS_MASK_IDX(txdesc, value)
+#define GET_TX_DESC_PCTS_MASK_IDX_8821C(txdesc) \
+ GET_TX_DESC_PCTS_MASK_IDX(txdesc)
+#define SET_TX_DESC_PCTS_EN_8821C(txdesc, value) \
+ SET_TX_DESC_PCTS_EN(txdesc, value)
+#define GET_TX_DESC_PCTS_EN_8821C(txdesc) GET_TX_DESC_PCTS_EN(txdesc)
+#define SET_TX_DESC_RTSRATE_8821C(txdesc, value) \
+ SET_TX_DESC_RTSRATE(txdesc, value)
+#define GET_TX_DESC_RTSRATE_8821C(txdesc) GET_TX_DESC_RTSRATE(txdesc)
+#define SET_TX_DESC_RTS_DATA_RTY_LMT_8821C(txdesc, value) \
+ SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value)
+#define GET_TX_DESC_RTS_DATA_RTY_LMT_8821C(txdesc) \
+ GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc)
+#define SET_TX_DESC_RTY_LMT_EN_8821C(txdesc, value) \
+ SET_TX_DESC_RTY_LMT_EN(txdesc, value)
+#define GET_TX_DESC_RTY_LMT_EN_8821C(txdesc) GET_TX_DESC_RTY_LMT_EN(txdesc)
+#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8821C(txdesc, value) \
+ SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value)
+#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8821C(txdesc) \
+ GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc)
+#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8821C(txdesc, value) \
+ SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value)
+#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8821C(txdesc) \
+ GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc)
+#define SET_TX_DESC_TRY_RATE_8821C(txdesc, value) \
+ SET_TX_DESC_TRY_RATE(txdesc, value)
+#define GET_TX_DESC_TRY_RATE_8821C(txdesc) GET_TX_DESC_TRY_RATE(txdesc)
+#define SET_TX_DESC_DATARATE_8821C(txdesc, value) \
+ SET_TX_DESC_DATARATE(txdesc, value)
+#define GET_TX_DESC_DATARATE_8821C(txdesc) GET_TX_DESC_DATARATE(txdesc)
/*TXDESC_WORD5*/
-#define SET_TX_DESC_POLLUTED_8821C(__pTxDesc, __Value) SET_TX_DESC_POLLUTED(__pTxDesc, __Value)
-#define GET_TX_DESC_POLLUTED_8821C(__pTxDesc) GET_TX_DESC_POLLUTED(__pTxDesc)
-#define SET_TX_DESC_TXPWR_OFSET_8821C(__pTxDesc, __Value) SET_TX_DESC_TXPWR_OFSET(__pTxDesc, __Value)
-#define GET_TX_DESC_TXPWR_OFSET_8821C(__pTxDesc) GET_TX_DESC_TXPWR_OFSET(__pTxDesc)
-#define SET_TX_DESC_TX_ANT_8821C(__pTxDesc, __Value) SET_TX_DESC_TX_ANT(__pTxDesc, __Value)
-#define GET_TX_DESC_TX_ANT_8821C(__pTxDesc) GET_TX_DESC_TX_ANT(__pTxDesc)
-#define SET_TX_DESC_PORT_ID_8821C(__pTxDesc, __Value) SET_TX_DESC_PORT_ID(__pTxDesc, __Value)
-#define GET_TX_DESC_PORT_ID_8821C(__pTxDesc) GET_TX_DESC_PORT_ID(__pTxDesc)
-#define SET_TX_DESC_MULTIPLE_PORT_8821C(__pTxDesc, __Value) SET_TX_DESC_MULTIPLE_PORT(__pTxDesc, __Value)
-#define GET_TX_DESC_MULTIPLE_PORT_8821C(__pTxDesc) GET_TX_DESC_MULTIPLE_PORT(__pTxDesc)
-#define SET_TX_DESC_SIGNALING_TAPKT_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_SIGNALING_TAPKT_EN_8821C(__pTxDesc) GET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc)
-#define SET_TX_DESC_RTS_SC_8821C(__pTxDesc, __Value) SET_TX_DESC_RTS_SC(__pTxDesc, __Value)
-#define GET_TX_DESC_RTS_SC_8821C(__pTxDesc) GET_TX_DESC_RTS_SC(__pTxDesc)
-#define SET_TX_DESC_RTS_SHORT_8821C(__pTxDesc, __Value) SET_TX_DESC_RTS_SHORT(__pTxDesc, __Value)
-#define GET_TX_DESC_RTS_SHORT_8821C(__pTxDesc) GET_TX_DESC_RTS_SHORT(__pTxDesc)
-#define SET_TX_DESC_VCS_STBC_8821C(__pTxDesc, __Value) SET_TX_DESC_VCS_STBC(__pTxDesc, __Value)
-#define GET_TX_DESC_VCS_STBC_8821C(__pTxDesc) GET_TX_DESC_VCS_STBC(__pTxDesc)
-#define SET_TX_DESC_DATA_STBC_8821C(__pTxDesc, __Value) SET_TX_DESC_DATA_STBC(__pTxDesc, __Value)
-#define GET_TX_DESC_DATA_STBC_8821C(__pTxDesc) GET_TX_DESC_DATA_STBC(__pTxDesc)
-#define SET_TX_DESC_DATA_LDPC_8821C(__pTxDesc, __Value) SET_TX_DESC_DATA_LDPC(__pTxDesc, __Value)
-#define GET_TX_DESC_DATA_LDPC_8821C(__pTxDesc) GET_TX_DESC_DATA_LDPC(__pTxDesc)
-#define SET_TX_DESC_DATA_BW_8821C(__pTxDesc, __Value) SET_TX_DESC_DATA_BW(__pTxDesc, __Value)
-#define GET_TX_DESC_DATA_BW_8821C(__pTxDesc) GET_TX_DESC_DATA_BW(__pTxDesc)
-#define SET_TX_DESC_DATA_SHORT_8821C(__pTxDesc, __Value) SET_TX_DESC_DATA_SHORT(__pTxDesc, __Value)
-#define GET_TX_DESC_DATA_SHORT_8821C(__pTxDesc) GET_TX_DESC_DATA_SHORT(__pTxDesc)
-#define SET_TX_DESC_DATA_SC_8821C(__pTxDesc, __Value) SET_TX_DESC_DATA_SC(__pTxDesc, __Value)
-#define GET_TX_DESC_DATA_SC_8821C(__pTxDesc) GET_TX_DESC_DATA_SC(__pTxDesc)
+#define SET_TX_DESC_POLLUTED_8821C(txdesc, value) \
+ SET_TX_DESC_POLLUTED(txdesc, value)
+#define GET_TX_DESC_POLLUTED_8821C(txdesc) GET_TX_DESC_POLLUTED(txdesc)
+#define SET_TX_DESC_TXPWR_OFSET_8821C(txdesc, value) \
+ SET_TX_DESC_TXPWR_OFSET(txdesc, value)
+#define GET_TX_DESC_TXPWR_OFSET_8821C(txdesc) GET_TX_DESC_TXPWR_OFSET(txdesc)
+#define SET_TX_DESC_TX_ANT_8821C(txdesc, value) \
+ SET_TX_DESC_TX_ANT(txdesc, value)
+#define GET_TX_DESC_TX_ANT_8821C(txdesc) GET_TX_DESC_TX_ANT(txdesc)
+#define SET_TX_DESC_PORT_ID_8821C(txdesc, value) \
+ SET_TX_DESC_PORT_ID(txdesc, value)
+#define GET_TX_DESC_PORT_ID_8821C(txdesc) GET_TX_DESC_PORT_ID(txdesc)
+#define SET_TX_DESC_MULTIPLE_PORT_8821C(txdesc, value) \
+ SET_TX_DESC_MULTIPLE_PORT(txdesc, value)
+#define GET_TX_DESC_MULTIPLE_PORT_8821C(txdesc) \
+ GET_TX_DESC_MULTIPLE_PORT(txdesc)
+#define SET_TX_DESC_SIGNALING_TAPKT_EN_8821C(txdesc, value) \
+ SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value)
+#define GET_TX_DESC_SIGNALING_TAPKT_EN_8821C(txdesc) \
+ GET_TX_DESC_SIGNALING_TAPKT_EN(txdesc)
+#define SET_TX_DESC_SIGNALING_TA_PKT_SC_8821C(txdesc, value) \
+ SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc, value)
+#define GET_TX_DESC_SIGNALING_TA_PKT_SC_8821C(txdesc) \
+ GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc)
+#define SET_TX_DESC_RTS_SHORT_8821C(txdesc, value) \
+ SET_TX_DESC_RTS_SHORT(txdesc, value)
+#define GET_TX_DESC_RTS_SHORT_8821C(txdesc) GET_TX_DESC_RTS_SHORT(txdesc)
+#define SET_TX_DESC_VCS_STBC_8821C(txdesc, value) \
+ SET_TX_DESC_VCS_STBC(txdesc, value)
+#define GET_TX_DESC_VCS_STBC_8821C(txdesc) GET_TX_DESC_VCS_STBC(txdesc)
+#define SET_TX_DESC_DATA_STBC_8821C(txdesc, value) \
+ SET_TX_DESC_DATA_STBC(txdesc, value)
+#define GET_TX_DESC_DATA_STBC_8821C(txdesc) GET_TX_DESC_DATA_STBC(txdesc)
+#define SET_TX_DESC_DATA_LDPC_8821C(txdesc, value) \
+ SET_TX_DESC_DATA_LDPC(txdesc, value)
+#define GET_TX_DESC_DATA_LDPC_8821C(txdesc) GET_TX_DESC_DATA_LDPC(txdesc)
+#define SET_TX_DESC_DATA_BW_8821C(txdesc, value) \
+ SET_TX_DESC_DATA_BW(txdesc, value)
+#define GET_TX_DESC_DATA_BW_8821C(txdesc) GET_TX_DESC_DATA_BW(txdesc)
+#define SET_TX_DESC_DATA_SHORT_8821C(txdesc, value) \
+ SET_TX_DESC_DATA_SHORT(txdesc, value)
+#define GET_TX_DESC_DATA_SHORT_8821C(txdesc) GET_TX_DESC_DATA_SHORT(txdesc)
+#define SET_TX_DESC_DATA_SC_8821C(txdesc, value) \
+ SET_TX_DESC_DATA_SC(txdesc, value)
+#define GET_TX_DESC_DATA_SC_8821C(txdesc) GET_TX_DESC_DATA_SC(txdesc)
/*TXDESC_WORD6*/
-#define SET_TX_DESC_ANTSEL_D_8821C(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_D(__pTxDesc, __Value)
-#define GET_TX_DESC_ANTSEL_D_8821C(__pTxDesc) GET_TX_DESC_ANTSEL_D(__pTxDesc)
-#define SET_TX_DESC_ANT_MAPD_8821C(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPD(__pTxDesc, __Value)
-#define GET_TX_DESC_ANT_MAPD_8821C(__pTxDesc) GET_TX_DESC_ANT_MAPD(__pTxDesc)
-#define SET_TX_DESC_ANT_MAPC_8821C(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPC(__pTxDesc, __Value)
-#define GET_TX_DESC_ANT_MAPC_8821C(__pTxDesc) GET_TX_DESC_ANT_MAPC(__pTxDesc)
-#define SET_TX_DESC_ANT_MAPB_8821C(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPB(__pTxDesc, __Value)
-#define GET_TX_DESC_ANT_MAPB_8821C(__pTxDesc) GET_TX_DESC_ANT_MAPB(__pTxDesc)
-#define SET_TX_DESC_ANT_MAPA_8821C(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPA(__pTxDesc, __Value)
-#define GET_TX_DESC_ANT_MAPA_8821C(__pTxDesc) GET_TX_DESC_ANT_MAPA(__pTxDesc)
-#define SET_TX_DESC_ANTSEL_C_8821C(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_C(__pTxDesc, __Value)
-#define GET_TX_DESC_ANTSEL_C_8821C(__pTxDesc) GET_TX_DESC_ANTSEL_C(__pTxDesc)
-#define SET_TX_DESC_ANTSEL_B_8821C(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_B(__pTxDesc, __Value)
-#define GET_TX_DESC_ANTSEL_B_8821C(__pTxDesc) GET_TX_DESC_ANTSEL_B(__pTxDesc)
-#define SET_TX_DESC_ANTSEL_A_8821C(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_A(__pTxDesc, __Value)
-#define GET_TX_DESC_ANTSEL_A_8821C(__pTxDesc) GET_TX_DESC_ANTSEL_A(__pTxDesc)
-#define SET_TX_DESC_MBSSID_8821C(__pTxDesc, __Value) SET_TX_DESC_MBSSID(__pTxDesc, __Value)
-#define GET_TX_DESC_MBSSID_8821C(__pTxDesc) GET_TX_DESC_MBSSID(__pTxDesc)
-#define SET_TX_DESC_SW_DEFINE_8821C(__pTxDesc, __Value) SET_TX_DESC_SW_DEFINE(__pTxDesc, __Value)
-#define GET_TX_DESC_SW_DEFINE_8821C(__pTxDesc) GET_TX_DESC_SW_DEFINE(__pTxDesc)
+#define SET_TX_DESC_ANTSEL_D_8821C(txdesc, value) \
+ SET_TX_DESC_ANTSEL_D(txdesc, value)
+#define GET_TX_DESC_ANTSEL_D_8821C(txdesc) GET_TX_DESC_ANTSEL_D(txdesc)
+#define SET_TX_DESC_ANT_MAPD_8821C(txdesc, value) \
+ SET_TX_DESC_ANT_MAPD(txdesc, value)
+#define GET_TX_DESC_ANT_MAPD_8821C(txdesc) GET_TX_DESC_ANT_MAPD(txdesc)
+#define SET_TX_DESC_ANT_MAPC_8821C(txdesc, value) \
+ SET_TX_DESC_ANT_MAPC(txdesc, value)
+#define GET_TX_DESC_ANT_MAPC_8821C(txdesc) GET_TX_DESC_ANT_MAPC(txdesc)
+#define SET_TX_DESC_ANT_MAPB_8821C(txdesc, value) \
+ SET_TX_DESC_ANT_MAPB(txdesc, value)
+#define GET_TX_DESC_ANT_MAPB_8821C(txdesc) GET_TX_DESC_ANT_MAPB(txdesc)
+#define SET_TX_DESC_ANT_MAPA_8821C(txdesc, value) \
+ SET_TX_DESC_ANT_MAPA(txdesc, value)
+#define GET_TX_DESC_ANT_MAPA_8821C(txdesc) GET_TX_DESC_ANT_MAPA(txdesc)
+#define SET_TX_DESC_ANTSEL_C_8821C(txdesc, value) \
+ SET_TX_DESC_ANTSEL_C(txdesc, value)
+#define GET_TX_DESC_ANTSEL_C_8821C(txdesc) GET_TX_DESC_ANTSEL_C(txdesc)
+#define SET_TX_DESC_ANTSEL_B_8821C(txdesc, value) \
+ SET_TX_DESC_ANTSEL_B(txdesc, value)
+#define GET_TX_DESC_ANTSEL_B_8821C(txdesc) GET_TX_DESC_ANTSEL_B(txdesc)
+#define SET_TX_DESC_ANTSEL_A_8821C(txdesc, value) \
+ SET_TX_DESC_ANTSEL_A(txdesc, value)
+#define GET_TX_DESC_ANTSEL_A_8821C(txdesc) GET_TX_DESC_ANTSEL_A(txdesc)
+#define SET_TX_DESC_MBSSID_8821C(txdesc, value) \
+ SET_TX_DESC_MBSSID(txdesc, value)
+#define GET_TX_DESC_MBSSID_8821C(txdesc) GET_TX_DESC_MBSSID(txdesc)
+#define SET_TX_DESC_SW_DEFINE_8821C(txdesc, value) \
+ SET_TX_DESC_SW_DEFINE(txdesc, value)
+#define GET_TX_DESC_SW_DEFINE_8821C(txdesc) GET_TX_DESC_SW_DEFINE(txdesc)
/*TXDESC_WORD7*/
-#define SET_TX_DESC_DMA_TXAGG_NUM_8821C(__pTxDesc, __Value) SET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc, __Value)
-#define GET_TX_DESC_DMA_TXAGG_NUM_8821C(__pTxDesc) GET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc)
-#define SET_TX_DESC_FINAL_DATA_RATE_8821C(__pTxDesc, __Value) SET_TX_DESC_FINAL_DATA_RATE(__pTxDesc, __Value)
-#define GET_TX_DESC_FINAL_DATA_RATE_8821C(__pTxDesc) GET_TX_DESC_FINAL_DATA_RATE(__pTxDesc)
-#define SET_TX_DESC_NTX_MAP_8821C(__pTxDesc, __Value) SET_TX_DESC_NTX_MAP(__pTxDesc, __Value)
-#define GET_TX_DESC_NTX_MAP_8821C(__pTxDesc) GET_TX_DESC_NTX_MAP(__pTxDesc)
-#define SET_TX_DESC_TX_BUFF_SIZE_8821C(__pTxDesc, __Value) SET_TX_DESC_TX_BUFF_SIZE(__pTxDesc, __Value)
-#define GET_TX_DESC_TX_BUFF_SIZE_8821C(__pTxDesc) GET_TX_DESC_TX_BUFF_SIZE(__pTxDesc)
-#define SET_TX_DESC_TXDESC_CHECKSUM_8821C(__pTxDesc, __Value) SET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc, __Value)
-#define GET_TX_DESC_TXDESC_CHECKSUM_8821C(__pTxDesc) GET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc)
-#define SET_TX_DESC_TIMESTAMP_8821C(__pTxDesc, __Value) SET_TX_DESC_TIMESTAMP(__pTxDesc, __Value)
-#define GET_TX_DESC_TIMESTAMP_8821C(__pTxDesc) GET_TX_DESC_TIMESTAMP(__pTxDesc)
+#define SET_TX_DESC_DMA_TXAGG_NUM_8821C(txdesc, value) \
+ SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value)
+#define GET_TX_DESC_DMA_TXAGG_NUM_8821C(txdesc) \
+ GET_TX_DESC_DMA_TXAGG_NUM(txdesc)
+#define SET_TX_DESC_FINAL_DATA_RATE_8821C(txdesc, value) \
+ SET_TX_DESC_FINAL_DATA_RATE(txdesc, value)
+#define GET_TX_DESC_FINAL_DATA_RATE_8821C(txdesc) \
+ GET_TX_DESC_FINAL_DATA_RATE(txdesc)
+#define SET_TX_DESC_NTX_MAP_8821C(txdesc, value) \
+ SET_TX_DESC_NTX_MAP(txdesc, value)
+#define GET_TX_DESC_NTX_MAP_8821C(txdesc) GET_TX_DESC_NTX_MAP(txdesc)
+#define SET_TX_DESC_TX_BUFF_SIZE_8821C(txdesc, value) \
+ SET_TX_DESC_TX_BUFF_SIZE(txdesc, value)
+#define GET_TX_DESC_TX_BUFF_SIZE_8821C(txdesc) GET_TX_DESC_TX_BUFF_SIZE(txdesc)
+#define SET_TX_DESC_TXDESC_CHECKSUM_8821C(txdesc, value) \
+ SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value)
+#define GET_TX_DESC_TXDESC_CHECKSUM_8821C(txdesc) \
+ GET_TX_DESC_TXDESC_CHECKSUM(txdesc)
+#define SET_TX_DESC_TIMESTAMP_8821C(txdesc, value) \
+ SET_TX_DESC_TIMESTAMP(txdesc, value)
+#define GET_TX_DESC_TIMESTAMP_8821C(txdesc) GET_TX_DESC_TIMESTAMP(txdesc)
/*TXDESC_WORD8*/
-#define SET_TX_DESC_TXWIFI_CP_8821C(__pTxDesc, __Value) SET_TX_DESC_TXWIFI_CP(__pTxDesc, __Value)
-#define GET_TX_DESC_TXWIFI_CP_8821C(__pTxDesc) GET_TX_DESC_TXWIFI_CP(__pTxDesc)
-#define SET_TX_DESC_MAC_CP_8821C(__pTxDesc, __Value) SET_TX_DESC_MAC_CP(__pTxDesc, __Value)
-#define GET_TX_DESC_MAC_CP_8821C(__pTxDesc) GET_TX_DESC_MAC_CP(__pTxDesc)
-#define SET_TX_DESC_STW_PKTRE_DIS_8821C(__pTxDesc, __Value) SET_TX_DESC_STW_PKTRE_DIS(__pTxDesc, __Value)
-#define GET_TX_DESC_STW_PKTRE_DIS_8821C(__pTxDesc) GET_TX_DESC_STW_PKTRE_DIS(__pTxDesc)
-#define SET_TX_DESC_STW_RB_DIS_8821C(__pTxDesc, __Value) SET_TX_DESC_STW_RB_DIS(__pTxDesc, __Value)
-#define GET_TX_DESC_STW_RB_DIS_8821C(__pTxDesc) GET_TX_DESC_STW_RB_DIS(__pTxDesc)
-#define SET_TX_DESC_STW_RATE_DIS_8821C(__pTxDesc, __Value) SET_TX_DESC_STW_RATE_DIS(__pTxDesc, __Value)
-#define GET_TX_DESC_STW_RATE_DIS_8821C(__pTxDesc) GET_TX_DESC_STW_RATE_DIS(__pTxDesc)
-#define SET_TX_DESC_STW_ANT_DIS_8821C(__pTxDesc, __Value) SET_TX_DESC_STW_ANT_DIS(__pTxDesc, __Value)
-#define GET_TX_DESC_STW_ANT_DIS_8821C(__pTxDesc) GET_TX_DESC_STW_ANT_DIS(__pTxDesc)
-#define SET_TX_DESC_STW_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_STW_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_STW_EN_8821C(__pTxDesc) GET_TX_DESC_STW_EN(__pTxDesc)
-#define SET_TX_DESC_SMH_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_SMH_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_SMH_EN_8821C(__pTxDesc) GET_TX_DESC_SMH_EN(__pTxDesc)
-#define SET_TX_DESC_TAILPAGE_L_8821C(__pTxDesc, __Value) SET_TX_DESC_TAILPAGE_L(__pTxDesc, __Value)
-#define GET_TX_DESC_TAILPAGE_L_8821C(__pTxDesc) GET_TX_DESC_TAILPAGE_L(__pTxDesc)
-#define SET_TX_DESC_SDIO_DMASEQ_8821C(__pTxDesc, __Value) SET_TX_DESC_SDIO_DMASEQ(__pTxDesc, __Value)
-#define GET_TX_DESC_SDIO_DMASEQ_8821C(__pTxDesc) GET_TX_DESC_SDIO_DMASEQ(__pTxDesc)
-#define SET_TX_DESC_NEXTHEADPAGE_L_8821C(__pTxDesc, __Value) SET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc, __Value)
-#define GET_TX_DESC_NEXTHEADPAGE_L_8821C(__pTxDesc) GET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc)
-#define SET_TX_DESC_EN_HWSEQ_8821C(__pTxDesc, __Value) SET_TX_DESC_EN_HWSEQ(__pTxDesc, __Value)
-#define GET_TX_DESC_EN_HWSEQ_8821C(__pTxDesc) GET_TX_DESC_EN_HWSEQ(__pTxDesc)
-#define SET_TX_DESC_EN_HWEXSEQ_8821C(__pTxDesc, __Value) SET_TX_DESC_EN_HWEXSEQ(__pTxDesc, __Value)
-#define GET_TX_DESC_EN_HWEXSEQ_8821C(__pTxDesc) GET_TX_DESC_EN_HWEXSEQ(__pTxDesc)
-#define SET_TX_DESC_DATA_RC_8821C(__pTxDesc, __Value) SET_TX_DESC_DATA_RC(__pTxDesc, __Value)
-#define GET_TX_DESC_DATA_RC_8821C(__pTxDesc) GET_TX_DESC_DATA_RC(__pTxDesc)
-#define SET_TX_DESC_BAR_RTY_TH_8821C(__pTxDesc, __Value) SET_TX_DESC_BAR_RTY_TH(__pTxDesc, __Value)
-#define GET_TX_DESC_BAR_RTY_TH_8821C(__pTxDesc) GET_TX_DESC_BAR_RTY_TH(__pTxDesc)
-#define SET_TX_DESC_RTS_RC_8821C(__pTxDesc, __Value) SET_TX_DESC_RTS_RC(__pTxDesc, __Value)
-#define GET_TX_DESC_RTS_RC_8821C(__pTxDesc) GET_TX_DESC_RTS_RC(__pTxDesc)
+#define SET_TX_DESC_TXWIFI_CP_8821C(txdesc, value) \
+ SET_TX_DESC_TXWIFI_CP(txdesc, value)
+#define GET_TX_DESC_TXWIFI_CP_8821C(txdesc) GET_TX_DESC_TXWIFI_CP(txdesc)
+#define SET_TX_DESC_MAC_CP_8821C(txdesc, value) \
+ SET_TX_DESC_MAC_CP(txdesc, value)
+#define GET_TX_DESC_MAC_CP_8821C(txdesc) GET_TX_DESC_MAC_CP(txdesc)
+#define SET_TX_DESC_STW_PKTRE_DIS_8821C(txdesc, value) \
+ SET_TX_DESC_STW_PKTRE_DIS(txdesc, value)
+#define GET_TX_DESC_STW_PKTRE_DIS_8821C(txdesc) \
+ GET_TX_DESC_STW_PKTRE_DIS(txdesc)
+#define SET_TX_DESC_STW_RB_DIS_8821C(txdesc, value) \
+ SET_TX_DESC_STW_RB_DIS(txdesc, value)
+#define GET_TX_DESC_STW_RB_DIS_8821C(txdesc) GET_TX_DESC_STW_RB_DIS(txdesc)
+#define SET_TX_DESC_STW_RATE_DIS_8821C(txdesc, value) \
+ SET_TX_DESC_STW_RATE_DIS(txdesc, value)
+#define GET_TX_DESC_STW_RATE_DIS_8821C(txdesc) GET_TX_DESC_STW_RATE_DIS(txdesc)
+#define SET_TX_DESC_STW_ANT_DIS_8821C(txdesc, value) \
+ SET_TX_DESC_STW_ANT_DIS(txdesc, value)
+#define GET_TX_DESC_STW_ANT_DIS_8821C(txdesc) GET_TX_DESC_STW_ANT_DIS(txdesc)
+#define SET_TX_DESC_STW_EN_8821C(txdesc, value) \
+ SET_TX_DESC_STW_EN(txdesc, value)
+#define GET_TX_DESC_STW_EN_8821C(txdesc) GET_TX_DESC_STW_EN(txdesc)
+#define SET_TX_DESC_SMH_EN_8821C(txdesc, value) \
+ SET_TX_DESC_SMH_EN(txdesc, value)
+#define GET_TX_DESC_SMH_EN_8821C(txdesc) GET_TX_DESC_SMH_EN(txdesc)
+#define SET_TX_DESC_TAILPAGE_L_8821C(txdesc, value) \
+ SET_TX_DESC_TAILPAGE_L(txdesc, value)
+#define GET_TX_DESC_TAILPAGE_L_8821C(txdesc) GET_TX_DESC_TAILPAGE_L(txdesc)
+#define SET_TX_DESC_SDIO_DMASEQ_8821C(txdesc, value) \
+ SET_TX_DESC_SDIO_DMASEQ(txdesc, value)
+#define GET_TX_DESC_SDIO_DMASEQ_8821C(txdesc) GET_TX_DESC_SDIO_DMASEQ(txdesc)
+#define SET_TX_DESC_NEXTHEADPAGE_L_8821C(txdesc, value) \
+ SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value)
+#define GET_TX_DESC_NEXTHEADPAGE_L_8821C(txdesc) \
+ GET_TX_DESC_NEXTHEADPAGE_L(txdesc)
+#define SET_TX_DESC_EN_HWSEQ_8821C(txdesc, value) \
+ SET_TX_DESC_EN_HWSEQ(txdesc, value)
+#define GET_TX_DESC_EN_HWSEQ_8821C(txdesc) GET_TX_DESC_EN_HWSEQ(txdesc)
+#define SET_TX_DESC_EN_HWEXSEQ_8821C(txdesc, value) \
+ SET_TX_DESC_EN_HWEXSEQ(txdesc, value)
+#define GET_TX_DESC_EN_HWEXSEQ_8821C(txdesc) GET_TX_DESC_EN_HWEXSEQ(txdesc)
+#define SET_TX_DESC_DATA_RC_8821C(txdesc, value) \
+ SET_TX_DESC_DATA_RC(txdesc, value)
+#define GET_TX_DESC_DATA_RC_8821C(txdesc) GET_TX_DESC_DATA_RC(txdesc)
+#define SET_TX_DESC_BAR_RTY_TH_8821C(txdesc, value) \
+ SET_TX_DESC_BAR_RTY_TH(txdesc, value)
+#define GET_TX_DESC_BAR_RTY_TH_8821C(txdesc) GET_TX_DESC_BAR_RTY_TH(txdesc)
+#define SET_TX_DESC_RTS_RC_8821C(txdesc, value) \
+ SET_TX_DESC_RTS_RC(txdesc, value)
+#define GET_TX_DESC_RTS_RC_8821C(txdesc) GET_TX_DESC_RTS_RC(txdesc)
/*TXDESC_WORD9*/
-#define SET_TX_DESC_TAILPAGE_H_8821C(__pTxDesc, __Value) SET_TX_DESC_TAILPAGE_H(__pTxDesc, __Value)
-#define GET_TX_DESC_TAILPAGE_H_8821C(__pTxDesc) GET_TX_DESC_TAILPAGE_H(__pTxDesc)
-#define SET_TX_DESC_NEXTHEADPAGE_H_8821C(__pTxDesc, __Value) SET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc, __Value)
-#define GET_TX_DESC_NEXTHEADPAGE_H_8821C(__pTxDesc) GET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc)
-#define SET_TX_DESC_SW_SEQ_8821C(__pTxDesc, __Value) SET_TX_DESC_SW_SEQ(__pTxDesc, __Value)
-#define GET_TX_DESC_SW_SEQ_8821C(__pTxDesc) GET_TX_DESC_SW_SEQ(__pTxDesc)
-#define SET_TX_DESC_TXBF_PATH_8821C(__pTxDesc, __Value) SET_TX_DESC_TXBF_PATH(__pTxDesc, __Value)
-#define GET_TX_DESC_TXBF_PATH_8821C(__pTxDesc) GET_TX_DESC_TXBF_PATH(__pTxDesc)
-#define SET_TX_DESC_PADDING_LEN_8821C(__pTxDesc, __Value) SET_TX_DESC_PADDING_LEN(__pTxDesc, __Value)
-#define GET_TX_DESC_PADDING_LEN_8821C(__pTxDesc) GET_TX_DESC_PADDING_LEN(__pTxDesc)
-#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8821C(__pTxDesc, __Value) SET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc, __Value)
-#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8821C(__pTxDesc) GET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc)
+#define SET_TX_DESC_TAILPAGE_H_8821C(txdesc, value) \
+ SET_TX_DESC_TAILPAGE_H(txdesc, value)
+#define GET_TX_DESC_TAILPAGE_H_8821C(txdesc) GET_TX_DESC_TAILPAGE_H(txdesc)
+#define SET_TX_DESC_NEXTHEADPAGE_H_8821C(txdesc, value) \
+ SET_TX_DESC_NEXTHEADPAGE_H(txdesc, value)
+#define GET_TX_DESC_NEXTHEADPAGE_H_8821C(txdesc) \
+ GET_TX_DESC_NEXTHEADPAGE_H(txdesc)
+#define SET_TX_DESC_SW_SEQ_8821C(txdesc, value) \
+ SET_TX_DESC_SW_SEQ(txdesc, value)
+#define GET_TX_DESC_SW_SEQ_8821C(txdesc) GET_TX_DESC_SW_SEQ(txdesc)
+#define SET_TX_DESC_TXBF_PATH_8821C(txdesc, value) \
+ SET_TX_DESC_TXBF_PATH(txdesc, value)
+#define GET_TX_DESC_TXBF_PATH_8821C(txdesc) GET_TX_DESC_TXBF_PATH(txdesc)
+#define SET_TX_DESC_PADDING_LEN_8821C(txdesc, value) \
+ SET_TX_DESC_PADDING_LEN(txdesc, value)
+#define GET_TX_DESC_PADDING_LEN_8821C(txdesc) GET_TX_DESC_PADDING_LEN(txdesc)
+#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8821C(txdesc, value) \
+ SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value)
+#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8821C(txdesc) \
+ GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc)
/*WORD10*/
-#define SET_TX_DESC_MU_DATARATE_8821C(__pTxDesc, __Value) SET_TX_DESC_MU_DATARATE(__pTxDesc, __Value)
-#define GET_TX_DESC_MU_DATARATE_8821C(__pTxDesc) GET_TX_DESC_MU_DATARATE(__pTxDesc)
-#define SET_TX_DESC_MU_RC_8821C(__pTxDesc, __Value) SET_TX_DESC_MU_RC(__pTxDesc, __Value)
-#define GET_TX_DESC_MU_RC_8821C(__pTxDesc) GET_TX_DESC_MU_RC(__pTxDesc)
-#define SET_TX_DESC_SND_PKT_SEL_8821C(__pTxDesc, __Value) SET_TX_DESC_SND_PKT_SEL(__pTxDesc, __Value)
-#define GET_TX_DESC_SND_PKT_SEL_8821C(__pTxDesc) GET_TX_DESC_SND_PKT_SEL(__pTxDesc)
+#define SET_TX_DESC_MU_DATARATE_8821C(txdesc, value) \
+ SET_TX_DESC_MU_DATARATE(txdesc, value)
+#define GET_TX_DESC_MU_DATARATE_8821C(txdesc) GET_TX_DESC_MU_DATARATE(txdesc)
+#define SET_TX_DESC_MU_RC_8821C(txdesc, value) SET_TX_DESC_MU_RC(txdesc, value)
+#define GET_TX_DESC_MU_RC_8821C(txdesc) GET_TX_DESC_MU_RC(txdesc)
+#define SET_TX_DESC_SND_PKT_SEL_8821C(txdesc, value) \
+ SET_TX_DESC_SND_PKT_SEL(txdesc, value)
+#define GET_TX_DESC_SND_PKT_SEL_8821C(txdesc) GET_TX_DESC_SND_PKT_SEL(txdesc)
#endif
-#if (HALMAC_8188F_SUPPORT)
+#if (HALMAC_8814B_SUPPORT)
/*TXDESC_WORD0*/
-#define SET_TX_DESC_GF_8188F(__pTxDesc, __Value) SET_TX_DESC_GF(__pTxDesc, __Value)
-#define GET_TX_DESC_GF_8188F(__pTxDesc) GET_TX_DESC_GF(__pTxDesc)
-#define SET_TX_DESC_NO_ACM_8188F(__pTxDesc, __Value) SET_TX_DESC_NO_ACM(__pTxDesc, __Value)
-#define GET_TX_DESC_NO_ACM_8188F(__pTxDesc) GET_TX_DESC_NO_ACM(__pTxDesc)
-#define SET_TX_DESC_LS_8188F(__pTxDesc, __Value) SET_TX_DESC_LS(__pTxDesc, __Value)
-#define GET_TX_DESC_LS_8188F(__pTxDesc) GET_TX_DESC_LS(__pTxDesc)
-#define SET_TX_DESC_HTC_8188F(__pTxDesc, __Value) SET_TX_DESC_HTC(__pTxDesc, __Value)
-#define GET_TX_DESC_HTC_8188F(__pTxDesc) GET_TX_DESC_HTC(__pTxDesc)
-#define SET_TX_DESC_BMC_8188F(__pTxDesc, __Value) SET_TX_DESC_BMC(__pTxDesc, __Value)
-#define GET_TX_DESC_BMC_8188F(__pTxDesc) GET_TX_DESC_BMC(__pTxDesc)
-#define SET_TX_DESC_OFFSET_8188F(__pTxDesc, __Value) SET_TX_DESC_OFFSET(__pTxDesc, __Value)
-#define GET_TX_DESC_OFFSET_8188F(__pTxDesc) GET_TX_DESC_OFFSET(__pTxDesc)
-#define SET_TX_DESC_TXPKTSIZE_8188F(__pTxDesc, __Value) SET_TX_DESC_TXPKTSIZE(__pTxDesc, __Value)
-#define GET_TX_DESC_TXPKTSIZE_8188F(__pTxDesc) GET_TX_DESC_TXPKTSIZE(__pTxDesc)
-
-/*TXDESC_WORD1*/
-
-#define SET_TX_DESC_MOREDATA_8188F(__pTxDesc, __Value) SET_TX_DESC_MOREDATA(__pTxDesc, __Value)
-#define GET_TX_DESC_MOREDATA_8188F(__pTxDesc) GET_TX_DESC_MOREDATA(__pTxDesc)
-#define SET_TX_DESC_PKT_OFFSET_8188F(__pTxDesc, __Value) SET_TX_DESC_PKT_OFFSET(__pTxDesc, __Value)
-#define GET_TX_DESC_PKT_OFFSET_8188F(__pTxDesc) GET_TX_DESC_PKT_OFFSET(__pTxDesc)
-#define SET_TX_DESC_SEC_TYPE_8188F(__pTxDesc, __Value) SET_TX_DESC_SEC_TYPE(__pTxDesc, __Value)
-#define GET_TX_DESC_SEC_TYPE_8188F(__pTxDesc) GET_TX_DESC_SEC_TYPE(__pTxDesc)
-#define SET_TX_DESC_EN_DESC_ID_8188F(__pTxDesc, __Value) SET_TX_DESC_EN_DESC_ID(__pTxDesc, __Value)
-#define GET_TX_DESC_EN_DESC_ID_8188F(__pTxDesc) GET_TX_DESC_EN_DESC_ID(__pTxDesc)
-#define SET_TX_DESC_RATE_ID_8188F(__pTxDesc, __Value) SET_TX_DESC_RATE_ID(__pTxDesc, __Value)
-#define GET_TX_DESC_RATE_ID_8188F(__pTxDesc) GET_TX_DESC_RATE_ID(__pTxDesc)
-#define SET_TX_DESC_PIFS_8188F(__pTxDesc, __Value) SET_TX_DESC_PIFS(__pTxDesc, __Value)
-#define GET_TX_DESC_PIFS_8188F(__pTxDesc) GET_TX_DESC_PIFS(__pTxDesc)
-#define SET_TX_DESC_LSIG_TXOP_EN_8188F(__pTxDesc, __Value) SET_TX_DESC_LSIG_TXOP_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_LSIG_TXOP_EN_8188F(__pTxDesc) GET_TX_DESC_LSIG_TXOP_EN(__pTxDesc)
-#define SET_TX_DESC_RD_NAV_EXT_8188F(__pTxDesc, __Value) SET_TX_DESC_RD_NAV_EXT(__pTxDesc, __Value)
-#define GET_TX_DESC_RD_NAV_EXT_8188F(__pTxDesc) GET_TX_DESC_RD_NAV_EXT(__pTxDesc)
-#define SET_TX_DESC_QSEL_8188F(__pTxDesc, __Value) SET_TX_DESC_QSEL(__pTxDesc, __Value)
-#define GET_TX_DESC_QSEL_8188F(__pTxDesc) GET_TX_DESC_QSEL(__pTxDesc)
-#define SET_TX_DESC_MACID_8188F(__pTxDesc, __Value) SET_TX_DESC_MACID(__pTxDesc, __Value)
-#define GET_TX_DESC_MACID_8188F(__pTxDesc) GET_TX_DESC_MACID(__pTxDesc)
+#define SET_TX_DESC_IE_END_BODY_8814B(txdesc, value) \
+ SET_TX_DESC_IE_END_BODY(txdesc, value)
+#define GET_TX_DESC_IE_END_BODY_8814B(txdesc) GET_TX_DESC_IE_END_BODY(txdesc)
+#define SET_TX_DESC_AGG_EN_8814B(txdesc, value) \
+ SET_TX_DESC_AGG_EN_V1(txdesc, value)
+#define GET_TX_DESC_AGG_EN_8814B(txdesc) GET_TX_DESC_AGG_EN_V1(txdesc)
+#define SET_TX_DESC_BK_8814B(txdesc, value) SET_TX_DESC_BK_V1(txdesc, value)
+#define GET_TX_DESC_BK_8814B(txdesc) GET_TX_DESC_BK_V1(txdesc)
+#define SET_TX_DESC_PKT_OFFSET_8814B(txdesc, value) \
+ SET_TX_DESC_PKT_OFFSET_V1(txdesc, value)
+#define GET_TX_DESC_PKT_OFFSET_8814B(txdesc) GET_TX_DESC_PKT_OFFSET_V1(txdesc)
+#define SET_TX_DESC_OFFSET_8814B(txdesc, value) \
+ SET_TX_DESC_OFFSET(txdesc, value)
+#define GET_TX_DESC_OFFSET_8814B(txdesc) GET_TX_DESC_OFFSET(txdesc)
+#define SET_TX_DESC_TXPKTSIZE_8814B(txdesc, value) \
+ SET_TX_DESC_TXPKTSIZE(txdesc, value)
+#define GET_TX_DESC_TXPKTSIZE_8814B(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc)
+
+/*WORD1*/
+
+#define SET_TX_DESC_AMSDU_8814B(txdesc, value) SET_TX_DESC_AMSDU(txdesc, value)
+#define GET_TX_DESC_AMSDU_8814B(txdesc) GET_TX_DESC_AMSDU(txdesc)
+#define SET_TX_DESC_HW_AES_IV_8814B(txdesc, value) \
+ SET_TX_DESC_HW_AES_IV_V1(txdesc, value)
+#define GET_TX_DESC_HW_AES_IV_8814B(txdesc) GET_TX_DESC_HW_AES_IV_V1(txdesc)
+#define SET_TX_DESC_MHR_CP_8814B(txdesc, value) \
+ SET_TX_DESC_MHR_CP(txdesc, value)
+#define GET_TX_DESC_MHR_CP_8814B(txdesc) GET_TX_DESC_MHR_CP(txdesc)
+#define SET_TX_DESC_SMH_EN_8814B(txdesc, value) \
+ SET_TX_DESC_SMH_EN_V1(txdesc, value)
+#define GET_TX_DESC_SMH_EN_8814B(txdesc) GET_TX_DESC_SMH_EN_V1(txdesc)
+#define SET_TX_DESC_SMH_CAM_8814B(txdesc, value) \
+ SET_TX_DESC_SMH_CAM(txdesc, value)
+#define GET_TX_DESC_SMH_CAM_8814B(txdesc) GET_TX_DESC_SMH_CAM(txdesc)
+#define SET_TX_DESC_EXT_EDCA_8814B(txdesc, value) \
+ SET_TX_DESC_EXT_EDCA(txdesc, value)
+#define GET_TX_DESC_EXT_EDCA_8814B(txdesc) GET_TX_DESC_EXT_EDCA(txdesc)
+#define SET_TX_DESC_QSEL_8814B(txdesc, value) SET_TX_DESC_QSEL(txdesc, value)
+#define GET_TX_DESC_QSEL_8814B(txdesc) GET_TX_DESC_QSEL(txdesc)
+#define SET_TX_DESC_MACID_8814B(txdesc, value) \
+ SET_TX_DESC_MACID_V1(txdesc, value)
+#define GET_TX_DESC_MACID_8814B(txdesc) GET_TX_DESC_MACID_V1(txdesc)
/*TXDESC_WORD2*/
-#define SET_TX_DESC_FTM_EN_8188F(__pTxDesc, __Value) SET_TX_DESC_FTM_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_FTM_EN_8188F(__pTxDesc) GET_TX_DESC_FTM_EN(__pTxDesc)
-#define SET_TX_DESC_G_ID_8188F(__pTxDesc, __Value) SET_TX_DESC_G_ID(__pTxDesc, __Value)
-#define GET_TX_DESC_G_ID_8188F(__pTxDesc) GET_TX_DESC_G_ID(__pTxDesc)
-#define SET_TX_DESC_BT_NULL_8188F(__pTxDesc, __Value) SET_TX_DESC_BT_NULL(__pTxDesc, __Value)
-#define GET_TX_DESC_BT_NULL_8188F(__pTxDesc) GET_TX_DESC_BT_NULL(__pTxDesc)
-#define SET_TX_DESC_AMPDU_DENSITY_8188F(__pTxDesc, __Value) SET_TX_DESC_AMPDU_DENSITY(__pTxDesc, __Value)
-#define GET_TX_DESC_AMPDU_DENSITY_8188F(__pTxDesc) GET_TX_DESC_AMPDU_DENSITY(__pTxDesc)
-#define SET_TX_DESC_SPE_RPT_8188F(__pTxDesc, __Value) SET_TX_DESC_SPE_RPT(__pTxDesc, __Value)
-#define GET_TX_DESC_SPE_RPT_8188F(__pTxDesc) GET_TX_DESC_SPE_RPT(__pTxDesc)
-#define SET_TX_DESC_RAW_8188F(__pTxDesc, __Value) SET_TX_DESC_RAW(__pTxDesc, __Value)
-#define GET_TX_DESC_RAW_8188F(__pTxDesc) GET_TX_DESC_RAW(__pTxDesc)
-#define SET_TX_DESC_MOREFRAG_8188F(__pTxDesc, __Value) SET_TX_DESC_MOREFRAG(__pTxDesc, __Value)
-#define GET_TX_DESC_MOREFRAG_8188F(__pTxDesc) GET_TX_DESC_MOREFRAG(__pTxDesc)
-#define SET_TX_DESC_BK_8188F(__pTxDesc, __Value) SET_TX_DESC_BK(__pTxDesc, __Value)
-#define GET_TX_DESC_BK_8188F(__pTxDesc) GET_TX_DESC_BK(__pTxDesc)
-#define SET_TX_DESC_NULL_1_8188F(__pTxDesc, __Value) SET_TX_DESC_NULL_1(__pTxDesc, __Value)
-#define GET_TX_DESC_NULL_1_8188F(__pTxDesc) GET_TX_DESC_NULL_1(__pTxDesc)
-#define SET_TX_DESC_NULL_0_8188F(__pTxDesc, __Value) SET_TX_DESC_NULL_0(__pTxDesc, __Value)
-#define GET_TX_DESC_NULL_0_8188F(__pTxDesc) GET_TX_DESC_NULL_0(__pTxDesc)
-#define SET_TX_DESC_RDG_EN_8188F(__pTxDesc, __Value) SET_TX_DESC_RDG_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_RDG_EN_8188F(__pTxDesc) GET_TX_DESC_RDG_EN(__pTxDesc)
-#define SET_TX_DESC_AGG_EN_8188F(__pTxDesc, __Value) SET_TX_DESC_AGG_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_AGG_EN_8188F(__pTxDesc) GET_TX_DESC_AGG_EN(__pTxDesc)
-#define SET_TX_DESC_CCA_RTS_8188F(__pTxDesc, __Value) SET_TX_DESC_CCA_RTS(__pTxDesc, __Value)
-#define GET_TX_DESC_CCA_RTS_8188F(__pTxDesc) GET_TX_DESC_CCA_RTS(__pTxDesc)
-#define SET_TX_DESC_TRI_FRAME_8188F(__pTxDesc, __Value) SET_TX_DESC_TRI_FRAME(__pTxDesc, __Value)
-#define GET_TX_DESC_TRI_FRAME_8188F(__pTxDesc) GET_TX_DESC_TRI_FRAME(__pTxDesc)
-#define SET_TX_DESC_P_AID_8188F(__pTxDesc, __Value) SET_TX_DESC_P_AID(__pTxDesc, __Value)
-#define GET_TX_DESC_P_AID_8188F(__pTxDesc) GET_TX_DESC_P_AID(__pTxDesc)
+#define SET_TX_DESC_CHK_EN_8814B(txdesc, value) \
+ SET_TX_DESC_CHK_EN_V1(txdesc, value)
+#define GET_TX_DESC_CHK_EN_8814B(txdesc) GET_TX_DESC_CHK_EN_V1(txdesc)
+#define SET_TX_DESC_DMA_PRI_8814B(txdesc, value) \
+ SET_TX_DESC_DMA_PRI(txdesc, value)
+#define GET_TX_DESC_DMA_PRI_8814B(txdesc) GET_TX_DESC_DMA_PRI(txdesc)
+#define SET_TX_DESC_MAX_AMSDU_MODE_8814B(txdesc, value) \
+ SET_TX_DESC_MAX_AMSDU_MODE(txdesc, value)
+#define GET_TX_DESC_MAX_AMSDU_MODE_8814B(txdesc) \
+ GET_TX_DESC_MAX_AMSDU_MODE(txdesc)
+#define SET_TX_DESC_DMA_TXAGG_NUM_8814B(txdesc, value) \
+ SET_TX_DESC_DMA_TXAGG_NUM_V1(txdesc, value)
+#define GET_TX_DESC_DMA_TXAGG_NUM_8814B(txdesc) \
+ GET_TX_DESC_DMA_TXAGG_NUM_V1(txdesc)
+#define SET_TX_DESC_TXDESC_CHECKSUM_8814B(txdesc, value) \
+ SET_TX_DESC_TXDESC_CHECKSUM_V1(txdesc, value)
+#define GET_TX_DESC_TXDESC_CHECKSUM_8814B(txdesc) \
+ GET_TX_DESC_TXDESC_CHECKSUM_V1(txdesc)
/*TXDESC_WORD3*/
-#define SET_TX_DESC_AMPDU_MAX_TIME_8188F(__pTxDesc, __Value) SET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc, __Value)
-#define GET_TX_DESC_AMPDU_MAX_TIME_8188F(__pTxDesc) GET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc)
-#define SET_TX_DESC_NDPA_8188F(__pTxDesc, __Value) SET_TX_DESC_NDPA(__pTxDesc, __Value)
-#define GET_TX_DESC_NDPA_8188F(__pTxDesc) GET_TX_DESC_NDPA(__pTxDesc)
-#define SET_TX_DESC_MAX_AGG_NUM_8188F(__pTxDesc, __Value) SET_TX_DESC_MAX_AGG_NUM(__pTxDesc, __Value)
-#define GET_TX_DESC_MAX_AGG_NUM_8188F(__pTxDesc) GET_TX_DESC_MAX_AGG_NUM(__pTxDesc)
-#define SET_TX_DESC_USE_MAX_TIME_EN_8188F(__pTxDesc, __Value) SET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_USE_MAX_TIME_EN_8188F(__pTxDesc) GET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc)
-#define SET_TX_DESC_NAVUSEHDR_8188F(__pTxDesc, __Value) SET_TX_DESC_NAVUSEHDR(__pTxDesc, __Value)
-#define GET_TX_DESC_NAVUSEHDR_8188F(__pTxDesc) GET_TX_DESC_NAVUSEHDR(__pTxDesc)
-#define SET_TX_DESC_HW_RTS_EN_8188F(__pTxDesc, __Value) SET_TX_DESC_HW_RTS_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_HW_RTS_EN_8188F(__pTxDesc) GET_TX_DESC_HW_RTS_EN(__pTxDesc)
-#define SET_TX_DESC_RTSEN_8188F(__pTxDesc, __Value) SET_TX_DESC_RTSEN(__pTxDesc, __Value)
-#define GET_TX_DESC_RTSEN_8188F(__pTxDesc) GET_TX_DESC_RTSEN(__pTxDesc)
-#define SET_TX_DESC_CTS2SELF_8188F(__pTxDesc, __Value) SET_TX_DESC_CTS2SELF(__pTxDesc, __Value)
-#define GET_TX_DESC_CTS2SELF_8188F(__pTxDesc) GET_TX_DESC_CTS2SELF(__pTxDesc)
-#define SET_TX_DESC_DISDATAFB_8188F(__pTxDesc, __Value) SET_TX_DESC_DISDATAFB(__pTxDesc, __Value)
-#define GET_TX_DESC_DISDATAFB_8188F(__pTxDesc) GET_TX_DESC_DISDATAFB(__pTxDesc)
-#define SET_TX_DESC_DISRTSFB_8188F(__pTxDesc, __Value) SET_TX_DESC_DISRTSFB(__pTxDesc, __Value)
-#define GET_TX_DESC_DISRTSFB_8188F(__pTxDesc) GET_TX_DESC_DISRTSFB(__pTxDesc)
-#define SET_TX_DESC_USE_RATE_8188F(__pTxDesc, __Value) SET_TX_DESC_USE_RATE(__pTxDesc, __Value)
-#define GET_TX_DESC_USE_RATE_8188F(__pTxDesc) GET_TX_DESC_USE_RATE(__pTxDesc)
-#define SET_TX_DESC_HW_SSN_SEL_8188F(__pTxDesc, __Value) SET_TX_DESC_HW_SSN_SEL(__pTxDesc, __Value)
-#define GET_TX_DESC_HW_SSN_SEL_8188F(__pTxDesc) GET_TX_DESC_HW_SSN_SEL(__pTxDesc)
+#define SET_TX_DESC_OFFLOAD_SIZE_8814B(txdesc, value) \
+ SET_TX_DESC_OFFLOAD_SIZE(txdesc, value)
+#define GET_TX_DESC_OFFLOAD_SIZE_8814B(txdesc) GET_TX_DESC_OFFLOAD_SIZE(txdesc)
+#define SET_TX_DESC_CHANNEL_DMA_8814B(txdesc, value) \
+ SET_TX_DESC_CHANNEL_DMA(txdesc, value)
+#define GET_TX_DESC_CHANNEL_DMA_8814B(txdesc) GET_TX_DESC_CHANNEL_DMA(txdesc)
+#define SET_TX_DESC_IE_CNT_8814B(txdesc, value) \
+ SET_TX_DESC_IE_CNT(txdesc, value)
+#define GET_TX_DESC_IE_CNT_8814B(txdesc) GET_TX_DESC_IE_CNT(txdesc)
+#define SET_TX_DESC_IE_CNT_EN_8814B(txdesc, value) \
+ SET_TX_DESC_IE_CNT_EN(txdesc, value)
+#define GET_TX_DESC_IE_CNT_EN_8814B(txdesc) GET_TX_DESC_IE_CNT_EN(txdesc)
+#define SET_TX_DESC_WHEADER_LEN_8814B(txdesc, value) \
+ SET_TX_DESC_WHEADER_LEN_V1(txdesc, value)
+#define GET_TX_DESC_WHEADER_LEN_8814B(txdesc) GET_TX_DESC_WHEADER_LEN_V1(txdesc)
/*TXDESC_WORD4*/
-#define SET_TX_DESC_PCTS_MASK_IDX_8188F(__pTxDesc, __Value) SET_TX_DESC_PCTS_MASK_IDX(__pTxDesc, __Value)
-#define GET_TX_DESC_PCTS_MASK_IDX_8188F(__pTxDesc) GET_TX_DESC_PCTS_MASK_IDX(__pTxDesc)
-#define SET_TX_DESC_PCTS_EN_8188F(__pTxDesc, __Value) SET_TX_DESC_PCTS_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_PCTS_EN_8188F(__pTxDesc) GET_TX_DESC_PCTS_EN(__pTxDesc)
-#define SET_TX_DESC_RTSRATE_8188F(__pTxDesc, __Value) SET_TX_DESC_RTSRATE(__pTxDesc, __Value)
-#define GET_TX_DESC_RTSRATE_8188F(__pTxDesc) GET_TX_DESC_RTSRATE(__pTxDesc)
-#define SET_TX_DESC_RTS_DATA_RTY_LMT_8188F(__pTxDesc, __Value) SET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc, __Value)
-#define GET_TX_DESC_RTS_DATA_RTY_LMT_8188F(__pTxDesc) GET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc)
-#define SET_TX_DESC_RTY_LMT_EN_8188F(__pTxDesc, __Value) SET_TX_DESC_RTY_LMT_EN(__pTxDesc, __Value)
-#define GET_TX_DESC_RTY_LMT_EN_8188F(__pTxDesc) GET_TX_DESC_RTY_LMT_EN(__pTxDesc)
-#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8188F(__pTxDesc, __Value) SET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc, __Value)
-#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8188F(__pTxDesc) GET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc)
-#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8188F(__pTxDesc, __Value) SET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc, __Value)
-#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8188F(__pTxDesc) GET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc)
-#define SET_TX_DESC_TRY_RATE_8188F(__pTxDesc, __Value) SET_TX_DESC_TRY_RATE(__pTxDesc, __Value)
-#define GET_TX_DESC_TRY_RATE_8188F(__pTxDesc) GET_TX_DESC_TRY_RATE(__pTxDesc)
-#define SET_TX_DESC_DATARATE_8188F(__pTxDesc, __Value) SET_TX_DESC_DATARATE(__pTxDesc, __Value)
-#define GET_TX_DESC_DATARATE_8188F(__pTxDesc) GET_TX_DESC_DATARATE(__pTxDesc)
+/*TXDESC_WORD5*/
+
+/*TXDESC_WORD6*/
+
+/*TXDESC_WORD7*/
+
+/*TXDESC_WORD8*/
+
+/*TXDESC_WORD9*/
+
+/*WORD10*/
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/*TXDESC_WORD0*/
+
+#define SET_TX_DESC_DISQSELSEQ_8198F(txdesc, value) \
+ SET_TX_DESC_DISQSELSEQ(txdesc, value)
+#define GET_TX_DESC_DISQSELSEQ_8198F(txdesc) GET_TX_DESC_DISQSELSEQ(txdesc)
+#define SET_TX_DESC_GF_8198F(txdesc, value) SET_TX_DESC_GF(txdesc, value)
+#define GET_TX_DESC_GF_8198F(txdesc) GET_TX_DESC_GF(txdesc)
+#define SET_TX_DESC_NO_ACM_8198F(txdesc, value) \
+ SET_TX_DESC_NO_ACM(txdesc, value)
+#define GET_TX_DESC_NO_ACM_8198F(txdesc) GET_TX_DESC_NO_ACM(txdesc)
+#define SET_TX_DESC_BCNPKT_TSF_CTRL_8198F(txdesc, value) \
+ SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value)
+#define GET_TX_DESC_BCNPKT_TSF_CTRL_8198F(txdesc) \
+ GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc)
+#define SET_TX_DESC_AMSDU_PAD_EN_8198F(txdesc, value) \
+ SET_TX_DESC_AMSDU_PAD_EN(txdesc, value)
+#define GET_TX_DESC_AMSDU_PAD_EN_8198F(txdesc) GET_TX_DESC_AMSDU_PAD_EN(txdesc)
+#define SET_TX_DESC_LS_8198F(txdesc, value) SET_TX_DESC_LS(txdesc, value)
+#define GET_TX_DESC_LS_8198F(txdesc) GET_TX_DESC_LS(txdesc)
+#define SET_TX_DESC_HTC_8198F(txdesc, value) SET_TX_DESC_HTC(txdesc, value)
+#define GET_TX_DESC_HTC_8198F(txdesc) GET_TX_DESC_HTC(txdesc)
+#define SET_TX_DESC_BMC_8198F(txdesc, value) SET_TX_DESC_BMC(txdesc, value)
+#define GET_TX_DESC_BMC_8198F(txdesc) GET_TX_DESC_BMC(txdesc)
+#define SET_TX_DESC_OFFSET_8198F(txdesc, value) \
+ SET_TX_DESC_OFFSET(txdesc, value)
+#define GET_TX_DESC_OFFSET_8198F(txdesc) GET_TX_DESC_OFFSET(txdesc)
+#define SET_TX_DESC_TXPKTSIZE_8198F(txdesc, value) \
+ SET_TX_DESC_TXPKTSIZE(txdesc, value)
+#define GET_TX_DESC_TXPKTSIZE_8198F(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc)
+
+/*WORD1*/
+
+#define SET_TX_DESC_HW_AES_IV_8198F(txdesc, value) \
+ SET_TX_DESC_HW_AES_IV_V2(txdesc, value)
+#define GET_TX_DESC_HW_AES_IV_8198F(txdesc) GET_TX_DESC_HW_AES_IV_V2(txdesc)
+#define SET_TX_DESC_FTM_EN_8198F(txdesc, value) \
+ SET_TX_DESC_FTM_EN_V1(txdesc, value)
+#define GET_TX_DESC_FTM_EN_8198F(txdesc) GET_TX_DESC_FTM_EN_V1(txdesc)
+#define SET_TX_DESC_MOREDATA_8198F(txdesc, value) \
+ SET_TX_DESC_MOREDATA(txdesc, value)
+#define GET_TX_DESC_MOREDATA_8198F(txdesc) GET_TX_DESC_MOREDATA(txdesc)
+#define SET_TX_DESC_PKT_OFFSET_8198F(txdesc, value) \
+ SET_TX_DESC_PKT_OFFSET(txdesc, value)
+#define GET_TX_DESC_PKT_OFFSET_8198F(txdesc) GET_TX_DESC_PKT_OFFSET(txdesc)
+#define SET_TX_DESC_SEC_TYPE_8198F(txdesc, value) \
+ SET_TX_DESC_SEC_TYPE(txdesc, value)
+#define GET_TX_DESC_SEC_TYPE_8198F(txdesc) GET_TX_DESC_SEC_TYPE(txdesc)
+#define SET_TX_DESC_EN_DESC_ID_8198F(txdesc, value) \
+ SET_TX_DESC_EN_DESC_ID(txdesc, value)
+#define GET_TX_DESC_EN_DESC_ID_8198F(txdesc) GET_TX_DESC_EN_DESC_ID(txdesc)
+#define SET_TX_DESC_RATE_ID_8198F(txdesc, value) \
+ SET_TX_DESC_RATE_ID(txdesc, value)
+#define GET_TX_DESC_RATE_ID_8198F(txdesc) GET_TX_DESC_RATE_ID(txdesc)
+#define SET_TX_DESC_PIFS_8198F(txdesc, value) SET_TX_DESC_PIFS(txdesc, value)
+#define GET_TX_DESC_PIFS_8198F(txdesc) GET_TX_DESC_PIFS(txdesc)
+#define SET_TX_DESC_LSIG_TXOP_EN_8198F(txdesc, value) \
+ SET_TX_DESC_LSIG_TXOP_EN(txdesc, value)
+#define GET_TX_DESC_LSIG_TXOP_EN_8198F(txdesc) GET_TX_DESC_LSIG_TXOP_EN(txdesc)
+#define SET_TX_DESC_RD_NAV_EXT_8198F(txdesc, value) \
+ SET_TX_DESC_RD_NAV_EXT(txdesc, value)
+#define GET_TX_DESC_RD_NAV_EXT_8198F(txdesc) GET_TX_DESC_RD_NAV_EXT(txdesc)
+#define SET_TX_DESC_QSEL_8198F(txdesc, value) SET_TX_DESC_QSEL(txdesc, value)
+#define GET_TX_DESC_QSEL_8198F(txdesc) GET_TX_DESC_QSEL(txdesc)
+#define SET_TX_DESC_SPECIAL_CW_8198F(txdesc, value) \
+ SET_TX_DESC_SPECIAL_CW(txdesc, value)
+#define GET_TX_DESC_SPECIAL_CW_8198F(txdesc) GET_TX_DESC_SPECIAL_CW(txdesc)
+#define SET_TX_DESC_MACID_8198F(txdesc, value) SET_TX_DESC_MACID(txdesc, value)
+#define GET_TX_DESC_MACID_8198F(txdesc) GET_TX_DESC_MACID(txdesc)
+
+/*TXDESC_WORD2*/
+
+#define SET_TX_DESC_ANTCEL_D_8198F(txdesc, value) \
+ SET_TX_DESC_ANTCEL_D_V1(txdesc, value)
+#define GET_TX_DESC_ANTCEL_D_8198F(txdesc) GET_TX_DESC_ANTCEL_D_V1(txdesc)
+#define SET_TX_DESC_ANTSEL_C_8198F(txdesc, value) \
+ SET_TX_DESC_ANTSEL_C_V1(txdesc, value)
+#define GET_TX_DESC_ANTSEL_C_8198F(txdesc) GET_TX_DESC_ANTSEL_C_V1(txdesc)
+#define SET_TX_DESC_BT_NULL_8198F(txdesc, value) \
+ SET_TX_DESC_BT_NULL(txdesc, value)
+#define GET_TX_DESC_BT_NULL_8198F(txdesc) GET_TX_DESC_BT_NULL(txdesc)
+#define SET_TX_DESC_AMPDU_DENSITY_8198F(txdesc, value) \
+ SET_TX_DESC_AMPDU_DENSITY(txdesc, value)
+#define GET_TX_DESC_AMPDU_DENSITY_8198F(txdesc) \
+ GET_TX_DESC_AMPDU_DENSITY(txdesc)
+#define SET_TX_DESC_SPE_RPT_8198F(txdesc, value) \
+ SET_TX_DESC_SPE_RPT(txdesc, value)
+#define GET_TX_DESC_SPE_RPT_8198F(txdesc) GET_TX_DESC_SPE_RPT(txdesc)
+#define SET_TX_DESC_RAW_8198F(txdesc, value) SET_TX_DESC_RAW(txdesc, value)
+#define GET_TX_DESC_RAW_8198F(txdesc) GET_TX_DESC_RAW(txdesc)
+#define SET_TX_DESC_MOREFRAG_8198F(txdesc, value) \
+ SET_TX_DESC_MOREFRAG(txdesc, value)
+#define GET_TX_DESC_MOREFRAG_8198F(txdesc) GET_TX_DESC_MOREFRAG(txdesc)
+#define SET_TX_DESC_BK_8198F(txdesc, value) SET_TX_DESC_BK(txdesc, value)
+#define GET_TX_DESC_BK_8198F(txdesc) GET_TX_DESC_BK(txdesc)
+#define SET_TX_DESC_NULL_1_8198F(txdesc, value) \
+ SET_TX_DESC_NULL_1(txdesc, value)
+#define GET_TX_DESC_NULL_1_8198F(txdesc) GET_TX_DESC_NULL_1(txdesc)
+#define SET_TX_DESC_NULL_0_8198F(txdesc, value) \
+ SET_TX_DESC_NULL_0(txdesc, value)
+#define GET_TX_DESC_NULL_0_8198F(txdesc) GET_TX_DESC_NULL_0(txdesc)
+#define SET_TX_DESC_RDG_EN_8198F(txdesc, value) \
+ SET_TX_DESC_RDG_EN(txdesc, value)
+#define GET_TX_DESC_RDG_EN_8198F(txdesc) GET_TX_DESC_RDG_EN(txdesc)
+#define SET_TX_DESC_AGG_EN_8198F(txdesc, value) \
+ SET_TX_DESC_AGG_EN(txdesc, value)
+#define GET_TX_DESC_AGG_EN_8198F(txdesc) GET_TX_DESC_AGG_EN(txdesc)
+#define SET_TX_DESC_CCA_RTS_8198F(txdesc, value) \
+ SET_TX_DESC_CCA_RTS(txdesc, value)
+#define GET_TX_DESC_CCA_RTS_8198F(txdesc) GET_TX_DESC_CCA_RTS(txdesc)
+#define SET_TX_DESC_TRI_FRAME_8198F(txdesc, value) \
+ SET_TX_DESC_TRI_FRAME(txdesc, value)
+#define GET_TX_DESC_TRI_FRAME_8198F(txdesc) GET_TX_DESC_TRI_FRAME(txdesc)
+#define SET_TX_DESC_P_AID_8198F(txdesc, value) SET_TX_DESC_P_AID(txdesc, value)
+#define GET_TX_DESC_P_AID_8198F(txdesc) GET_TX_DESC_P_AID(txdesc)
+
+/*TXDESC_WORD3*/
+
+#define SET_TX_DESC_AMPDU_MAX_TIME_8198F(txdesc, value) \
+ SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value)
+#define GET_TX_DESC_AMPDU_MAX_TIME_8198F(txdesc) \
+ GET_TX_DESC_AMPDU_MAX_TIME(txdesc)
+#define SET_TX_DESC_NDPA_8198F(txdesc, value) SET_TX_DESC_NDPA(txdesc, value)
+#define GET_TX_DESC_NDPA_8198F(txdesc) GET_TX_DESC_NDPA(txdesc)
+#define SET_TX_DESC_MAX_AGG_NUM_8198F(txdesc, value) \
+ SET_TX_DESC_MAX_AGG_NUM(txdesc, value)
+#define GET_TX_DESC_MAX_AGG_NUM_8198F(txdesc) GET_TX_DESC_MAX_AGG_NUM(txdesc)
+#define SET_TX_DESC_USE_MAX_TIME_EN_8198F(txdesc, value) \
+ SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value)
+#define GET_TX_DESC_USE_MAX_TIME_EN_8198F(txdesc) \
+ GET_TX_DESC_USE_MAX_TIME_EN(txdesc)
+#define SET_TX_DESC_NAVUSEHDR_8198F(txdesc, value) \
+ SET_TX_DESC_NAVUSEHDR(txdesc, value)
+#define GET_TX_DESC_NAVUSEHDR_8198F(txdesc) GET_TX_DESC_NAVUSEHDR(txdesc)
+#define SET_TX_DESC_CHK_EN_8198F(txdesc, value) \
+ SET_TX_DESC_CHK_EN(txdesc, value)
+#define GET_TX_DESC_CHK_EN_8198F(txdesc) GET_TX_DESC_CHK_EN(txdesc)
+#define SET_TX_DESC_HW_RTS_EN_8198F(txdesc, value) \
+ SET_TX_DESC_HW_RTS_EN(txdesc, value)
+#define GET_TX_DESC_HW_RTS_EN_8198F(txdesc) GET_TX_DESC_HW_RTS_EN(txdesc)
+#define SET_TX_DESC_RTSEN_8198F(txdesc, value) SET_TX_DESC_RTSEN(txdesc, value)
+#define GET_TX_DESC_RTSEN_8198F(txdesc) GET_TX_DESC_RTSEN(txdesc)
+#define SET_TX_DESC_CTS2SELF_8198F(txdesc, value) \
+ SET_TX_DESC_CTS2SELF(txdesc, value)
+#define GET_TX_DESC_CTS2SELF_8198F(txdesc) GET_TX_DESC_CTS2SELF(txdesc)
+#define SET_TX_DESC_DISDATAFB_8198F(txdesc, value) \
+ SET_TX_DESC_DISDATAFB(txdesc, value)
+#define GET_TX_DESC_DISDATAFB_8198F(txdesc) GET_TX_DESC_DISDATAFB(txdesc)
+#define SET_TX_DESC_DISRTSFB_8198F(txdesc, value) \
+ SET_TX_DESC_DISRTSFB(txdesc, value)
+#define GET_TX_DESC_DISRTSFB_8198F(txdesc) GET_TX_DESC_DISRTSFB(txdesc)
+#define SET_TX_DESC_USE_RATE_8198F(txdesc, value) \
+ SET_TX_DESC_USE_RATE(txdesc, value)
+#define GET_TX_DESC_USE_RATE_8198F(txdesc) GET_TX_DESC_USE_RATE(txdesc)
+#define SET_TX_DESC_HW_SSN_SEL_8198F(txdesc, value) \
+ SET_TX_DESC_HW_SSN_SEL(txdesc, value)
+#define GET_TX_DESC_HW_SSN_SEL_8198F(txdesc) GET_TX_DESC_HW_SSN_SEL(txdesc)
+#define SET_TX_DESC_WHEADER_LEN_8198F(txdesc, value) \
+ SET_TX_DESC_WHEADER_LEN(txdesc, value)
+#define GET_TX_DESC_WHEADER_LEN_8198F(txdesc) GET_TX_DESC_WHEADER_LEN(txdesc)
+
+/*TXDESC_WORD4*/
+
+#define SET_TX_DESC_PCTS_MASK_IDX_8198F(txdesc, value) \
+ SET_TX_DESC_PCTS_MASK_IDX(txdesc, value)
+#define GET_TX_DESC_PCTS_MASK_IDX_8198F(txdesc) \
+ GET_TX_DESC_PCTS_MASK_IDX(txdesc)
+#define SET_TX_DESC_PCTS_EN_8198F(txdesc, value) \
+ SET_TX_DESC_PCTS_EN(txdesc, value)
+#define GET_TX_DESC_PCTS_EN_8198F(txdesc) GET_TX_DESC_PCTS_EN(txdesc)
+#define SET_TX_DESC_RTSRATE_8198F(txdesc, value) \
+ SET_TX_DESC_RTSRATE(txdesc, value)
+#define GET_TX_DESC_RTSRATE_8198F(txdesc) GET_TX_DESC_RTSRATE(txdesc)
+#define SET_TX_DESC_RTS_DATA_RTY_LMT_8198F(txdesc, value) \
+ SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value)
+#define GET_TX_DESC_RTS_DATA_RTY_LMT_8198F(txdesc) \
+ GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc)
+#define SET_TX_DESC_RTY_LMT_EN_8198F(txdesc, value) \
+ SET_TX_DESC_RTY_LMT_EN(txdesc, value)
+#define GET_TX_DESC_RTY_LMT_EN_8198F(txdesc) GET_TX_DESC_RTY_LMT_EN(txdesc)
+#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8198F(txdesc, value) \
+ SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value)
+#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8198F(txdesc) \
+ GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc)
+#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8198F(txdesc, value) \
+ SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value)
+#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8198F(txdesc) \
+ GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc)
+#define SET_TX_DESC_TRY_RATE_8198F(txdesc, value) \
+ SET_TX_DESC_TRY_RATE(txdesc, value)
+#define GET_TX_DESC_TRY_RATE_8198F(txdesc) GET_TX_DESC_TRY_RATE(txdesc)
+#define SET_TX_DESC_DATARATE_8198F(txdesc, value) \
+ SET_TX_DESC_DATARATE(txdesc, value)
+#define GET_TX_DESC_DATARATE_8198F(txdesc) GET_TX_DESC_DATARATE(txdesc)
/*TXDESC_WORD5*/
-#define SET_TX_DESC_TXPWR_OFSET_8188F(__pTxDesc, __Value) SET_TX_DESC_TXPWR_OFSET(__pTxDesc, __Value)
-#define GET_TX_DESC_TXPWR_OFSET_8188F(__pTxDesc) GET_TX_DESC_TXPWR_OFSET(__pTxDesc)
-#define SET_TX_DESC_TX_ANT_8188F(__pTxDesc, __Value) SET_TX_DESC_TX_ANT(__pTxDesc, __Value)
-#define GET_TX_DESC_TX_ANT_8188F(__pTxDesc) GET_TX_DESC_TX_ANT(__pTxDesc)
-#define SET_TX_DESC_PORT_ID_8188F(__pTxDesc, __Value) SET_TX_DESC_PORT_ID(__pTxDesc, __Value)
-#define GET_TX_DESC_PORT_ID_8188F(__pTxDesc) GET_TX_DESC_PORT_ID(__pTxDesc)
-#define SET_TX_DESC_RTS_SC_8188F(__pTxDesc, __Value) SET_TX_DESC_RTS_SC(__pTxDesc, __Value)
-#define GET_TX_DESC_RTS_SC_8188F(__pTxDesc) GET_TX_DESC_RTS_SC(__pTxDesc)
-#define SET_TX_DESC_RTS_SHORT_8188F(__pTxDesc, __Value) SET_TX_DESC_RTS_SHORT(__pTxDesc, __Value)
-#define GET_TX_DESC_RTS_SHORT_8188F(__pTxDesc) GET_TX_DESC_RTS_SHORT(__pTxDesc)
-#define SET_TX_DESC_RTS_STBC_8188F(__pTxDesc, __Value) SET_TX_DESC_RTS_STBC(__pTxDesc, __Value)
-#define GET_TX_DESC_RTS_STBC_8188F(__pTxDesc) GET_TX_DESC_RTS_STBC(__pTxDesc)
-#define SET_TX_DESC_DATA_STBC_8188F(__pTxDesc, __Value) SET_TX_DESC_DATA_STBC(__pTxDesc, __Value)
-#define GET_TX_DESC_DATA_STBC_8188F(__pTxDesc) GET_TX_DESC_DATA_STBC(__pTxDesc)
-#define SET_TX_DESC_DATA_BW_8188F(__pTxDesc, __Value) SET_TX_DESC_DATA_BW(__pTxDesc, __Value)
-#define GET_TX_DESC_DATA_BW_8188F(__pTxDesc) GET_TX_DESC_DATA_BW(__pTxDesc)
-#define SET_TX_DESC_DATA_SHORT_8188F(__pTxDesc, __Value) SET_TX_DESC_DATA_SHORT(__pTxDesc, __Value)
-#define GET_TX_DESC_DATA_SHORT_8188F(__pTxDesc) GET_TX_DESC_DATA_SHORT(__pTxDesc)
-#define SET_TX_DESC_DATA_SC_8188F(__pTxDesc, __Value) SET_TX_DESC_DATA_SC(__pTxDesc, __Value)
-#define GET_TX_DESC_DATA_SC_8188F(__pTxDesc) GET_TX_DESC_DATA_SC(__pTxDesc)
+#define SET_TX_DESC_POLLUTED_8198F(txdesc, value) \
+ SET_TX_DESC_POLLUTED(txdesc, value)
+#define GET_TX_DESC_POLLUTED_8198F(txdesc) GET_TX_DESC_POLLUTED(txdesc)
+#define SET_TX_DESC_TXPWR_OFSET_8198F(txdesc, value) \
+ SET_TX_DESC_TXPWR_OFSET(txdesc, value)
+#define GET_TX_DESC_TXPWR_OFSET_8198F(txdesc) GET_TX_DESC_TXPWR_OFSET(txdesc)
+#define SET_TX_DESC_DROP_ID_8198F(txdesc, value) \
+ SET_TX_DESC_DROP_ID(txdesc, value)
+#define GET_TX_DESC_DROP_ID_8198F(txdesc) GET_TX_DESC_DROP_ID(txdesc)
+#define SET_TX_DESC_PORT_ID_8198F(txdesc, value) \
+ SET_TX_DESC_PORT_ID(txdesc, value)
+#define GET_TX_DESC_PORT_ID_8198F(txdesc) GET_TX_DESC_PORT_ID(txdesc)
+#define SET_TX_DESC_MULTIPLE_PORT_8198F(txdesc, value) \
+ SET_TX_DESC_MULTIPLE_PORT(txdesc, value)
+#define GET_TX_DESC_MULTIPLE_PORT_8198F(txdesc) \
+ GET_TX_DESC_MULTIPLE_PORT(txdesc)
+#define SET_TX_DESC_SIGNALING_TAPKT_EN_8198F(txdesc, value) \
+ SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value)
+#define GET_TX_DESC_SIGNALING_TAPKT_EN_8198F(txdesc) \
+ GET_TX_DESC_SIGNALING_TAPKT_EN(txdesc)
+#define SET_TX_DESC_RTS_SC_8198F(txdesc, value) \
+ SET_TX_DESC_RTS_SC(txdesc, value)
+#define GET_TX_DESC_RTS_SC_8198F(txdesc) GET_TX_DESC_RTS_SC(txdesc)
+#define SET_TX_DESC_RTS_SHORT_8198F(txdesc, value) \
+ SET_TX_DESC_RTS_SHORT(txdesc, value)
+#define GET_TX_DESC_RTS_SHORT_8198F(txdesc) GET_TX_DESC_RTS_SHORT(txdesc)
+#define SET_TX_DESC_VCS_STBC_8198F(txdesc, value) \
+ SET_TX_DESC_VCS_STBC(txdesc, value)
+#define GET_TX_DESC_VCS_STBC_8198F(txdesc) GET_TX_DESC_VCS_STBC(txdesc)
+#define SET_TX_DESC_DATA_STBC_8198F(txdesc, value) \
+ SET_TX_DESC_DATA_STBC(txdesc, value)
+#define GET_TX_DESC_DATA_STBC_8198F(txdesc) GET_TX_DESC_DATA_STBC(txdesc)
+#define SET_TX_DESC_DATA_LDPC_8198F(txdesc, value) \
+ SET_TX_DESC_DATA_LDPC(txdesc, value)
+#define GET_TX_DESC_DATA_LDPC_8198F(txdesc) GET_TX_DESC_DATA_LDPC(txdesc)
+#define SET_TX_DESC_DATA_BW_8198F(txdesc, value) \
+ SET_TX_DESC_DATA_BW(txdesc, value)
+#define GET_TX_DESC_DATA_BW_8198F(txdesc) GET_TX_DESC_DATA_BW(txdesc)
+#define SET_TX_DESC_DATA_SHORT_8198F(txdesc, value) \
+ SET_TX_DESC_DATA_SHORT(txdesc, value)
+#define GET_TX_DESC_DATA_SHORT_8198F(txdesc) GET_TX_DESC_DATA_SHORT(txdesc)
+#define SET_TX_DESC_DATA_SC_8198F(txdesc, value) \
+ SET_TX_DESC_DATA_SC(txdesc, value)
+#define GET_TX_DESC_DATA_SC_8198F(txdesc) GET_TX_DESC_DATA_SC(txdesc)
/*TXDESC_WORD6*/
-#define SET_TX_DESC_ANTSEL_A_8188F(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_A(__pTxDesc, __Value)
-#define GET_TX_DESC_ANTSEL_A_8188F(__pTxDesc) GET_TX_DESC_ANTSEL_A(__pTxDesc)
-#define SET_TX_DESC_MBSSID_8188F(__pTxDesc, __Value) SET_TX_DESC_MBSSID(__pTxDesc, __Value)
-#define GET_TX_DESC_MBSSID_8188F(__pTxDesc) GET_TX_DESC_MBSSID(__pTxDesc)
-#define SET_TX_DESC_SW_DEFINE_8188F(__pTxDesc, __Value) SET_TX_DESC_SW_DEFINE(__pTxDesc, __Value)
-#define GET_TX_DESC_SW_DEFINE_8188F(__pTxDesc) GET_TX_DESC_SW_DEFINE(__pTxDesc)
+#define SET_TX_DESC_ANT_MAPD_8198F(txdesc, value) \
+ SET_TX_DESC_ANT_MAPD_V1(txdesc, value)
+#define GET_TX_DESC_ANT_MAPD_8198F(txdesc) GET_TX_DESC_ANT_MAPD_V1(txdesc)
+#define SET_TX_DESC_ANT_MAPC_8198F(txdesc, value) \
+ SET_TX_DESC_ANT_MAPC_V1(txdesc, value)
+#define GET_TX_DESC_ANT_MAPC_8198F(txdesc) GET_TX_DESC_ANT_MAPC_V1(txdesc)
+#define SET_TX_DESC_ANT_MAPB_8198F(txdesc, value) \
+ SET_TX_DESC_ANT_MAPB_V1(txdesc, value)
+#define GET_TX_DESC_ANT_MAPB_8198F(txdesc) GET_TX_DESC_ANT_MAPB_V1(txdesc)
+#define SET_TX_DESC_ANT_MAPA_8198F(txdesc, value) \
+ SET_TX_DESC_ANT_MAPA_V1(txdesc, value)
+#define GET_TX_DESC_ANT_MAPA_8198F(txdesc) GET_TX_DESC_ANT_MAPA_V1(txdesc)
+#define SET_TX_DESC_ANTSEL_B_8198F(txdesc, value) \
+ SET_TX_DESC_ANTSEL_B_V1(txdesc, value)
+#define GET_TX_DESC_ANTSEL_B_8198F(txdesc) GET_TX_DESC_ANTSEL_B_V1(txdesc)
+#define SET_TX_DESC_ANTSEL_A_8198F(txdesc, value) \
+ SET_TX_DESC_ANTSEL_A_V1(txdesc, value)
+#define GET_TX_DESC_ANTSEL_A_8198F(txdesc) GET_TX_DESC_ANTSEL_A_V1(txdesc)
+#define SET_TX_DESC_MBSSID_8198F(txdesc, value) \
+ SET_TX_DESC_MBSSID(txdesc, value)
+#define GET_TX_DESC_MBSSID_8198F(txdesc) GET_TX_DESC_MBSSID(txdesc)
+#define SET_TX_DESC_SWPS_SEQ_8198F(txdesc, value) \
+ SET_TX_DESC_SWPS_SEQ(txdesc, value)
+#define GET_TX_DESC_SWPS_SEQ_8198F(txdesc) GET_TX_DESC_SWPS_SEQ(txdesc)
/*TXDESC_WORD7*/
-#define SET_TX_DESC_DMA_TXAGG_NUM_8188F(__pTxDesc, __Value) SET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc, __Value)
-#define GET_TX_DESC_DMA_TXAGG_NUM_8188F(__pTxDesc) GET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc)
-#define SET_TX_DESC_TX_BUFF_SIZE_8188F(__pTxDesc, __Value) SET_TX_DESC_TX_BUFF_SIZE(__pTxDesc, __Value)
-#define GET_TX_DESC_TX_BUFF_SIZE_8188F(__pTxDesc) GET_TX_DESC_TX_BUFF_SIZE(__pTxDesc)
-#define SET_TX_DESC_TXDESC_CHECKSUM_8188F(__pTxDesc, __Value) SET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc, __Value)
-#define GET_TX_DESC_TXDESC_CHECKSUM_8188F(__pTxDesc) GET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc)
-#define SET_TX_DESC_TIMESTAMP_8188F(__pTxDesc, __Value) SET_TX_DESC_TIMESTAMP(__pTxDesc, __Value)
-#define GET_TX_DESC_TIMESTAMP_8188F(__pTxDesc) GET_TX_DESC_TIMESTAMP(__pTxDesc)
+#define SET_TX_DESC_DMA_TXAGG_NUM_8198F(txdesc, value) \
+ SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value)
+#define GET_TX_DESC_DMA_TXAGG_NUM_8198F(txdesc) \
+ GET_TX_DESC_DMA_TXAGG_NUM(txdesc)
+#define SET_TX_DESC_FINAL_DATA_RATE_8198F(txdesc, value) \
+ SET_TX_DESC_FINAL_DATA_RATE(txdesc, value)
+#define GET_TX_DESC_FINAL_DATA_RATE_8198F(txdesc) \
+ GET_TX_DESC_FINAL_DATA_RATE(txdesc)
+#define SET_TX_DESC_NTX_MAP_8198F(txdesc, value) \
+ SET_TX_DESC_NTX_MAP(txdesc, value)
+#define GET_TX_DESC_NTX_MAP_8198F(txdesc) GET_TX_DESC_NTX_MAP(txdesc)
+#define SET_TX_DESC_ANTSEL_EN_8198F(txdesc, value) \
+ SET_TX_DESC_ANTSEL_EN(txdesc, value)
+#define GET_TX_DESC_ANTSEL_EN_8198F(txdesc) GET_TX_DESC_ANTSEL_EN(txdesc)
+#define SET_TX_DESC_MBSSID_EX_8198F(txdesc, value) \
+ SET_TX_DESC_MBSSID_EX(txdesc, value)
+#define GET_TX_DESC_MBSSID_EX_8198F(txdesc) GET_TX_DESC_MBSSID_EX(txdesc)
+#define SET_TX_DESC_TX_BUFF_SIZE_8198F(txdesc, value) \
+ SET_TX_DESC_TX_BUFF_SIZE(txdesc, value)
+#define GET_TX_DESC_TX_BUFF_SIZE_8198F(txdesc) GET_TX_DESC_TX_BUFF_SIZE(txdesc)
+#define SET_TX_DESC_TXDESC_CHECKSUM_8198F(txdesc, value) \
+ SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value)
+#define GET_TX_DESC_TXDESC_CHECKSUM_8198F(txdesc) \
+ GET_TX_DESC_TXDESC_CHECKSUM(txdesc)
+#define SET_TX_DESC_TIMESTAMP_8198F(txdesc, value) \
+ SET_TX_DESC_TIMESTAMP(txdesc, value)
+#define GET_TX_DESC_TIMESTAMP_8198F(txdesc) GET_TX_DESC_TIMESTAMP(txdesc)
/*TXDESC_WORD8*/
-#define SET_TX_DESC_TAILPAGE_L_8188F(__pTxDesc, __Value) SET_TX_DESC_TAILPAGE_L(__pTxDesc, __Value)
-#define GET_TX_DESC_TAILPAGE_L_8188F(__pTxDesc) GET_TX_DESC_TAILPAGE_L(__pTxDesc)
-#define SET_TX_DESC_NEXTHEADPAGE_L_8188F(__pTxDesc, __Value) SET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc, __Value)
-#define GET_TX_DESC_NEXTHEADPAGE_L_8188F(__pTxDesc) GET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc)
-#define SET_TX_DESC_EN_HWSEQ_8188F(__pTxDesc, __Value) SET_TX_DESC_EN_HWSEQ(__pTxDesc, __Value)
-#define GET_TX_DESC_EN_HWSEQ_8188F(__pTxDesc) GET_TX_DESC_EN_HWSEQ(__pTxDesc)
-#define SET_TX_DESC_DATA_RC_8188F(__pTxDesc, __Value) SET_TX_DESC_DATA_RC(__pTxDesc, __Value)
-#define GET_TX_DESC_DATA_RC_8188F(__pTxDesc) GET_TX_DESC_DATA_RC(__pTxDesc)
-#define SET_TX_DESC_BAR_RTY_TH_8188F(__pTxDesc, __Value) SET_TX_DESC_BAR_RTY_TH(__pTxDesc, __Value)
-#define GET_TX_DESC_BAR_RTY_TH_8188F(__pTxDesc) GET_TX_DESC_BAR_RTY_TH(__pTxDesc)
-#define SET_TX_DESC_RTS_RC_8188F(__pTxDesc, __Value) SET_TX_DESC_RTS_RC(__pTxDesc, __Value)
-#define GET_TX_DESC_RTS_RC_8188F(__pTxDesc) GET_TX_DESC_RTS_RC(__pTxDesc)
+#define SET_TX_DESC_TXWIFI_CP_8198F(txdesc, value) \
+ SET_TX_DESC_TXWIFI_CP(txdesc, value)
+#define GET_TX_DESC_TXWIFI_CP_8198F(txdesc) GET_TX_DESC_TXWIFI_CP(txdesc)
+#define SET_TX_DESC_MAC_CP_8198F(txdesc, value) \
+ SET_TX_DESC_MAC_CP(txdesc, value)
+#define GET_TX_DESC_MAC_CP_8198F(txdesc) GET_TX_DESC_MAC_CP(txdesc)
+#define SET_TX_DESC_STW_PKTRE_DIS_8198F(txdesc, value) \
+ SET_TX_DESC_STW_PKTRE_DIS(txdesc, value)
+#define GET_TX_DESC_STW_PKTRE_DIS_8198F(txdesc) \
+ GET_TX_DESC_STW_PKTRE_DIS(txdesc)
+#define SET_TX_DESC_STW_RB_DIS_8198F(txdesc, value) \
+ SET_TX_DESC_STW_RB_DIS(txdesc, value)
+#define GET_TX_DESC_STW_RB_DIS_8198F(txdesc) GET_TX_DESC_STW_RB_DIS(txdesc)
+#define SET_TX_DESC_STW_RATE_DIS_8198F(txdesc, value) \
+ SET_TX_DESC_STW_RATE_DIS(txdesc, value)
+#define GET_TX_DESC_STW_RATE_DIS_8198F(txdesc) GET_TX_DESC_STW_RATE_DIS(txdesc)
+#define SET_TX_DESC_STW_ANT_DIS_8198F(txdesc, value) \
+ SET_TX_DESC_STW_ANT_DIS(txdesc, value)
+#define GET_TX_DESC_STW_ANT_DIS_8198F(txdesc) GET_TX_DESC_STW_ANT_DIS(txdesc)
+#define SET_TX_DESC_STW_EN_8198F(txdesc, value) \
+ SET_TX_DESC_STW_EN(txdesc, value)
+#define GET_TX_DESC_STW_EN_8198F(txdesc) GET_TX_DESC_STW_EN(txdesc)
+#define SET_TX_DESC_SMH_EN_8198F(txdesc, value) \
+ SET_TX_DESC_SMH_EN(txdesc, value)
+#define GET_TX_DESC_SMH_EN_8198F(txdesc) GET_TX_DESC_SMH_EN(txdesc)
+#define SET_TX_DESC_TAILPAGE_L_8198F(txdesc, value) \
+ SET_TX_DESC_TAILPAGE_L(txdesc, value)
+#define GET_TX_DESC_TAILPAGE_L_8198F(txdesc) GET_TX_DESC_TAILPAGE_L(txdesc)
+#define SET_TX_DESC_SDIO_DMASEQ_8198F(txdesc, value) \
+ SET_TX_DESC_SDIO_DMASEQ(txdesc, value)
+#define GET_TX_DESC_SDIO_DMASEQ_8198F(txdesc) GET_TX_DESC_SDIO_DMASEQ(txdesc)
+#define SET_TX_DESC_NEXTHEADPAGE_L_8198F(txdesc, value) \
+ SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value)
+#define GET_TX_DESC_NEXTHEADPAGE_L_8198F(txdesc) \
+ GET_TX_DESC_NEXTHEADPAGE_L(txdesc)
+#define SET_TX_DESC_EN_HWSEQ_8198F(txdesc, value) \
+ SET_TX_DESC_EN_HWSEQ(txdesc, value)
+#define GET_TX_DESC_EN_HWSEQ_8198F(txdesc) GET_TX_DESC_EN_HWSEQ(txdesc)
+#define SET_TX_DESC_EN_HWEXSEQ_8198F(txdesc, value) \
+ SET_TX_DESC_EN_HWEXSEQ(txdesc, value)
+#define GET_TX_DESC_EN_HWEXSEQ_8198F(txdesc) GET_TX_DESC_EN_HWEXSEQ(txdesc)
+#define SET_TX_DESC_DATA_RC_8198F(txdesc, value) \
+ SET_TX_DESC_DATA_RC(txdesc, value)
+#define GET_TX_DESC_DATA_RC_8198F(txdesc) GET_TX_DESC_DATA_RC(txdesc)
+#define SET_TX_DESC_BAR_RTY_TH_8198F(txdesc, value) \
+ SET_TX_DESC_BAR_RTY_TH(txdesc, value)
+#define GET_TX_DESC_BAR_RTY_TH_8198F(txdesc) GET_TX_DESC_BAR_RTY_TH(txdesc)
+#define SET_TX_DESC_RTS_RC_8198F(txdesc, value) \
+ SET_TX_DESC_RTS_RC(txdesc, value)
+#define GET_TX_DESC_RTS_RC_8198F(txdesc) GET_TX_DESC_RTS_RC(txdesc)
/*TXDESC_WORD9*/
-#define SET_TX_DESC_SW_SEQ_8188F(__pTxDesc, __Value) SET_TX_DESC_SW_SEQ(__pTxDesc, __Value)
-#define GET_TX_DESC_SW_SEQ_8188F(__pTxDesc) GET_TX_DESC_SW_SEQ(__pTxDesc)
-#define SET_TX_DESC_TXBF_PATH_8188F(__pTxDesc, __Value) SET_TX_DESC_TXBF_PATH(__pTxDesc, __Value)
-#define GET_TX_DESC_TXBF_PATH_8188F(__pTxDesc) GET_TX_DESC_TXBF_PATH(__pTxDesc)
-#define SET_TX_DESC_PADDING_LEN_8188F(__pTxDesc, __Value) SET_TX_DESC_PADDING_LEN(__pTxDesc, __Value)
-#define GET_TX_DESC_PADDING_LEN_8188F(__pTxDesc) GET_TX_DESC_PADDING_LEN(__pTxDesc)
-#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8188F(__pTxDesc, __Value) SET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc, __Value)
-#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8188F(__pTxDesc) GET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc)
+#define SET_TX_DESC_TAILPAGE_H_8198F(txdesc, value) \
+ SET_TX_DESC_TAILPAGE_H(txdesc, value)
+#define GET_TX_DESC_TAILPAGE_H_8198F(txdesc) GET_TX_DESC_TAILPAGE_H(txdesc)
+#define SET_TX_DESC_NEXTHEADPAGE_H_8198F(txdesc, value) \
+ SET_TX_DESC_NEXTHEADPAGE_H(txdesc, value)
+#define GET_TX_DESC_NEXTHEADPAGE_H_8198F(txdesc) \
+ GET_TX_DESC_NEXTHEADPAGE_H(txdesc)
+#define SET_TX_DESC_SW_SEQ_8198F(txdesc, value) \
+ SET_TX_DESC_SW_SEQ(txdesc, value)
+#define GET_TX_DESC_SW_SEQ_8198F(txdesc) GET_TX_DESC_SW_SEQ(txdesc)
+#define SET_TX_DESC_TXBF_PATH_8198F(txdesc, value) \
+ SET_TX_DESC_TXBF_PATH(txdesc, value)
+#define GET_TX_DESC_TXBF_PATH_8198F(txdesc) GET_TX_DESC_TXBF_PATH(txdesc)
+#define SET_TX_DESC_PADDING_LEN_8198F(txdesc, value) \
+ SET_TX_DESC_PADDING_LEN(txdesc, value)
+#define GET_TX_DESC_PADDING_LEN_8198F(txdesc) GET_TX_DESC_PADDING_LEN(txdesc)
+#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8198F(txdesc, value) \
+ SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value)
+#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8198F(txdesc) \
+ GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc)
/*WORD10*/
-
#endif
+#if (HALMAC_8822C_SUPPORT)
+
+/*TXDESC_WORD0*/
+
+#define SET_TX_DESC_DISQSELSEQ_8822C(txdesc, value) \
+ SET_TX_DESC_DISQSELSEQ(txdesc, value)
+#define GET_TX_DESC_DISQSELSEQ_8822C(txdesc) GET_TX_DESC_DISQSELSEQ(txdesc)
+#define SET_TX_DESC_GF_8822C(txdesc, value) SET_TX_DESC_GF(txdesc, value)
+#define GET_TX_DESC_GF_8822C(txdesc) GET_TX_DESC_GF(txdesc)
+#define SET_TX_DESC_NO_ACM_8822C(txdesc, value) \
+ SET_TX_DESC_NO_ACM(txdesc, value)
+#define GET_TX_DESC_NO_ACM_8822C(txdesc) GET_TX_DESC_NO_ACM(txdesc)
+#define SET_TX_DESC_BCNPKT_TSF_CTRL_8822C(txdesc, value) \
+ SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value)
+#define GET_TX_DESC_BCNPKT_TSF_CTRL_8822C(txdesc) \
+ GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc)
+#define SET_TX_DESC_AMSDU_PAD_EN_8822C(txdesc, value) \
+ SET_TX_DESC_AMSDU_PAD_EN(txdesc, value)
+#define GET_TX_DESC_AMSDU_PAD_EN_8822C(txdesc) GET_TX_DESC_AMSDU_PAD_EN(txdesc)
+#define SET_TX_DESC_LS_8822C(txdesc, value) SET_TX_DESC_LS(txdesc, value)
+#define GET_TX_DESC_LS_8822C(txdesc) GET_TX_DESC_LS(txdesc)
+#define SET_TX_DESC_HTC_8822C(txdesc, value) SET_TX_DESC_HTC(txdesc, value)
+#define GET_TX_DESC_HTC_8822C(txdesc) GET_TX_DESC_HTC(txdesc)
+#define SET_TX_DESC_BMC_8822C(txdesc, value) SET_TX_DESC_BMC(txdesc, value)
+#define GET_TX_DESC_BMC_8822C(txdesc) GET_TX_DESC_BMC(txdesc)
+#define SET_TX_DESC_OFFSET_8822C(txdesc, value) \
+ SET_TX_DESC_OFFSET(txdesc, value)
+#define GET_TX_DESC_OFFSET_8822C(txdesc) GET_TX_DESC_OFFSET(txdesc)
+#define SET_TX_DESC_TXPKTSIZE_8822C(txdesc, value) \
+ SET_TX_DESC_TXPKTSIZE(txdesc, value)
+#define GET_TX_DESC_TXPKTSIZE_8822C(txdesc) GET_TX_DESC_TXPKTSIZE(txdesc)
+
+/*WORD1*/
+
+#define SET_TX_DESC_MOREDATA_8822C(txdesc, value) \
+ SET_TX_DESC_MOREDATA(txdesc, value)
+#define GET_TX_DESC_MOREDATA_8822C(txdesc) GET_TX_DESC_MOREDATA(txdesc)
+#define SET_TX_DESC_PKT_OFFSET_8822C(txdesc, value) \
+ SET_TX_DESC_PKT_OFFSET(txdesc, value)
+#define GET_TX_DESC_PKT_OFFSET_8822C(txdesc) GET_TX_DESC_PKT_OFFSET(txdesc)
+#define SET_TX_DESC_SEC_TYPE_8822C(txdesc, value) \
+ SET_TX_DESC_SEC_TYPE(txdesc, value)
+#define GET_TX_DESC_SEC_TYPE_8822C(txdesc) GET_TX_DESC_SEC_TYPE(txdesc)
+#define SET_TX_DESC_EN_DESC_ID_8822C(txdesc, value) \
+ SET_TX_DESC_EN_DESC_ID(txdesc, value)
+#define GET_TX_DESC_EN_DESC_ID_8822C(txdesc) GET_TX_DESC_EN_DESC_ID(txdesc)
+#define SET_TX_DESC_RATE_ID_8822C(txdesc, value) \
+ SET_TX_DESC_RATE_ID(txdesc, value)
+#define GET_TX_DESC_RATE_ID_8822C(txdesc) GET_TX_DESC_RATE_ID(txdesc)
+#define SET_TX_DESC_PIFS_8822C(txdesc, value) SET_TX_DESC_PIFS(txdesc, value)
+#define GET_TX_DESC_PIFS_8822C(txdesc) GET_TX_DESC_PIFS(txdesc)
+#define SET_TX_DESC_LSIG_TXOP_EN_8822C(txdesc, value) \
+ SET_TX_DESC_LSIG_TXOP_EN(txdesc, value)
+#define GET_TX_DESC_LSIG_TXOP_EN_8822C(txdesc) GET_TX_DESC_LSIG_TXOP_EN(txdesc)
+#define SET_TX_DESC_RD_NAV_EXT_8822C(txdesc, value) \
+ SET_TX_DESC_RD_NAV_EXT(txdesc, value)
+#define GET_TX_DESC_RD_NAV_EXT_8822C(txdesc) GET_TX_DESC_RD_NAV_EXT(txdesc)
+#define SET_TX_DESC_QSEL_8822C(txdesc, value) SET_TX_DESC_QSEL(txdesc, value)
+#define GET_TX_DESC_QSEL_8822C(txdesc) GET_TX_DESC_QSEL(txdesc)
+#define SET_TX_DESC_MACID_8822C(txdesc, value) SET_TX_DESC_MACID(txdesc, value)
+#define GET_TX_DESC_MACID_8822C(txdesc) GET_TX_DESC_MACID(txdesc)
+
+/*TXDESC_WORD2*/
+
+#define SET_TX_DESC_HW_AES_IV_8822C(txdesc, value) \
+ SET_TX_DESC_HW_AES_IV(txdesc, value)
+#define GET_TX_DESC_HW_AES_IV_8822C(txdesc) GET_TX_DESC_HW_AES_IV(txdesc)
+#define SET_TX_DESC_FTM_EN_8822C(txdesc, value) \
+ SET_TX_DESC_FTM_EN(txdesc, value)
+#define GET_TX_DESC_FTM_EN_8822C(txdesc) GET_TX_DESC_FTM_EN(txdesc)
+#define SET_TX_DESC_G_ID_8822C(txdesc, value) SET_TX_DESC_G_ID(txdesc, value)
+#define GET_TX_DESC_G_ID_8822C(txdesc) GET_TX_DESC_G_ID(txdesc)
+#define SET_TX_DESC_BT_NULL_8822C(txdesc, value) \
+ SET_TX_DESC_BT_NULL(txdesc, value)
+#define GET_TX_DESC_BT_NULL_8822C(txdesc) GET_TX_DESC_BT_NULL(txdesc)
+#define SET_TX_DESC_AMPDU_DENSITY_8822C(txdesc, value) \
+ SET_TX_DESC_AMPDU_DENSITY(txdesc, value)
+#define GET_TX_DESC_AMPDU_DENSITY_8822C(txdesc) \
+ GET_TX_DESC_AMPDU_DENSITY(txdesc)
+#define SET_TX_DESC_SPE_RPT_8822C(txdesc, value) \
+ SET_TX_DESC_SPE_RPT(txdesc, value)
+#define GET_TX_DESC_SPE_RPT_8822C(txdesc) GET_TX_DESC_SPE_RPT(txdesc)
+#define SET_TX_DESC_RAW_8822C(txdesc, value) SET_TX_DESC_RAW(txdesc, value)
+#define GET_TX_DESC_RAW_8822C(txdesc) GET_TX_DESC_RAW(txdesc)
+#define SET_TX_DESC_MOREFRAG_8822C(txdesc, value) \
+ SET_TX_DESC_MOREFRAG(txdesc, value)
+#define GET_TX_DESC_MOREFRAG_8822C(txdesc) GET_TX_DESC_MOREFRAG(txdesc)
+#define SET_TX_DESC_BK_8822C(txdesc, value) SET_TX_DESC_BK(txdesc, value)
+#define GET_TX_DESC_BK_8822C(txdesc) GET_TX_DESC_BK(txdesc)
+#define SET_TX_DESC_NULL_1_8822C(txdesc, value) \
+ SET_TX_DESC_NULL_1(txdesc, value)
+#define GET_TX_DESC_NULL_1_8822C(txdesc) GET_TX_DESC_NULL_1(txdesc)
+#define SET_TX_DESC_NULL_0_8822C(txdesc, value) \
+ SET_TX_DESC_NULL_0(txdesc, value)
+#define GET_TX_DESC_NULL_0_8822C(txdesc) GET_TX_DESC_NULL_0(txdesc)
+#define SET_TX_DESC_RDG_EN_8822C(txdesc, value) \
+ SET_TX_DESC_RDG_EN(txdesc, value)
+#define GET_TX_DESC_RDG_EN_8822C(txdesc) GET_TX_DESC_RDG_EN(txdesc)
+#define SET_TX_DESC_AGG_EN_8822C(txdesc, value) \
+ SET_TX_DESC_AGG_EN(txdesc, value)
+#define GET_TX_DESC_AGG_EN_8822C(txdesc) GET_TX_DESC_AGG_EN(txdesc)
+#define SET_TX_DESC_CCA_RTS_8822C(txdesc, value) \
+ SET_TX_DESC_CCA_RTS(txdesc, value)
+#define GET_TX_DESC_CCA_RTS_8822C(txdesc) GET_TX_DESC_CCA_RTS(txdesc)
+#define SET_TX_DESC_TRI_FRAME_8822C(txdesc, value) \
+ SET_TX_DESC_TRI_FRAME(txdesc, value)
+#define GET_TX_DESC_TRI_FRAME_8822C(txdesc) GET_TX_DESC_TRI_FRAME(txdesc)
+#define SET_TX_DESC_P_AID_8822C(txdesc, value) SET_TX_DESC_P_AID(txdesc, value)
+#define GET_TX_DESC_P_AID_8822C(txdesc) GET_TX_DESC_P_AID(txdesc)
+
+/*TXDESC_WORD3*/
+
+#define SET_TX_DESC_AMPDU_MAX_TIME_8822C(txdesc, value) \
+ SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value)
+#define GET_TX_DESC_AMPDU_MAX_TIME_8822C(txdesc) \
+ GET_TX_DESC_AMPDU_MAX_TIME(txdesc)
+#define SET_TX_DESC_NDPA_8822C(txdesc, value) SET_TX_DESC_NDPA(txdesc, value)
+#define GET_TX_DESC_NDPA_8822C(txdesc) GET_TX_DESC_NDPA(txdesc)
+#define SET_TX_DESC_MAX_AGG_NUM_8822C(txdesc, value) \
+ SET_TX_DESC_MAX_AGG_NUM(txdesc, value)
+#define GET_TX_DESC_MAX_AGG_NUM_8822C(txdesc) GET_TX_DESC_MAX_AGG_NUM(txdesc)
+#define SET_TX_DESC_USE_MAX_TIME_EN_8822C(txdesc, value) \
+ SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value)
+#define GET_TX_DESC_USE_MAX_TIME_EN_8822C(txdesc) \
+ GET_TX_DESC_USE_MAX_TIME_EN(txdesc)
+#define SET_TX_DESC_NAVUSEHDR_8822C(txdesc, value) \
+ SET_TX_DESC_NAVUSEHDR(txdesc, value)
+#define GET_TX_DESC_NAVUSEHDR_8822C(txdesc) GET_TX_DESC_NAVUSEHDR(txdesc)
+#define SET_TX_DESC_CHK_EN_8822C(txdesc, value) \
+ SET_TX_DESC_CHK_EN(txdesc, value)
+#define GET_TX_DESC_CHK_EN_8822C(txdesc) GET_TX_DESC_CHK_EN(txdesc)
+#define SET_TX_DESC_HW_RTS_EN_8822C(txdesc, value) \
+ SET_TX_DESC_HW_RTS_EN(txdesc, value)
+#define GET_TX_DESC_HW_RTS_EN_8822C(txdesc) GET_TX_DESC_HW_RTS_EN(txdesc)
+#define SET_TX_DESC_RTSEN_8822C(txdesc, value) SET_TX_DESC_RTSEN(txdesc, value)
+#define GET_TX_DESC_RTSEN_8822C(txdesc) GET_TX_DESC_RTSEN(txdesc)
+#define SET_TX_DESC_CTS2SELF_8822C(txdesc, value) \
+ SET_TX_DESC_CTS2SELF(txdesc, value)
+#define GET_TX_DESC_CTS2SELF_8822C(txdesc) GET_TX_DESC_CTS2SELF(txdesc)
+#define SET_TX_DESC_DISDATAFB_8822C(txdesc, value) \
+ SET_TX_DESC_DISDATAFB(txdesc, value)
+#define GET_TX_DESC_DISDATAFB_8822C(txdesc) GET_TX_DESC_DISDATAFB(txdesc)
+#define SET_TX_DESC_DISRTSFB_8822C(txdesc, value) \
+ SET_TX_DESC_DISRTSFB(txdesc, value)
+#define GET_TX_DESC_DISRTSFB_8822C(txdesc) GET_TX_DESC_DISRTSFB(txdesc)
+#define SET_TX_DESC_USE_RATE_8822C(txdesc, value) \
+ SET_TX_DESC_USE_RATE(txdesc, value)
+#define GET_TX_DESC_USE_RATE_8822C(txdesc) GET_TX_DESC_USE_RATE(txdesc)
+#define SET_TX_DESC_HW_SSN_SEL_8822C(txdesc, value) \
+ SET_TX_DESC_HW_SSN_SEL(txdesc, value)
+#define GET_TX_DESC_HW_SSN_SEL_8822C(txdesc) GET_TX_DESC_HW_SSN_SEL(txdesc)
+#define SET_TX_DESC_WHEADER_LEN_8822C(txdesc, value) \
+ SET_TX_DESC_WHEADER_LEN(txdesc, value)
+#define GET_TX_DESC_WHEADER_LEN_8822C(txdesc) GET_TX_DESC_WHEADER_LEN(txdesc)
+
+/*TXDESC_WORD4*/
+
+#define SET_TX_DESC_PCTS_MASK_IDX_8822C(txdesc, value) \
+ SET_TX_DESC_PCTS_MASK_IDX(txdesc, value)
+#define GET_TX_DESC_PCTS_MASK_IDX_8822C(txdesc) \
+ GET_TX_DESC_PCTS_MASK_IDX(txdesc)
+#define SET_TX_DESC_PCTS_EN_8822C(txdesc, value) \
+ SET_TX_DESC_PCTS_EN(txdesc, value)
+#define GET_TX_DESC_PCTS_EN_8822C(txdesc) GET_TX_DESC_PCTS_EN(txdesc)
+#define SET_TX_DESC_RTSRATE_8822C(txdesc, value) \
+ SET_TX_DESC_RTSRATE(txdesc, value)
+#define GET_TX_DESC_RTSRATE_8822C(txdesc) GET_TX_DESC_RTSRATE(txdesc)
+#define SET_TX_DESC_RTS_DATA_RTY_LMT_8822C(txdesc, value) \
+ SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value)
+#define GET_TX_DESC_RTS_DATA_RTY_LMT_8822C(txdesc) \
+ GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc)
+#define SET_TX_DESC_RTY_LMT_EN_8822C(txdesc, value) \
+ SET_TX_DESC_RTY_LMT_EN(txdesc, value)
+#define GET_TX_DESC_RTY_LMT_EN_8822C(txdesc) GET_TX_DESC_RTY_LMT_EN(txdesc)
+#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8822C(txdesc, value) \
+ SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value)
+#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8822C(txdesc) \
+ GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc)
+#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8822C(txdesc, value) \
+ SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value)
+#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8822C(txdesc) \
+ GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc)
+#define SET_TX_DESC_TRY_RATE_8822C(txdesc, value) \
+ SET_TX_DESC_TRY_RATE(txdesc, value)
+#define GET_TX_DESC_TRY_RATE_8822C(txdesc) GET_TX_DESC_TRY_RATE(txdesc)
+#define SET_TX_DESC_DATARATE_8822C(txdesc, value) \
+ SET_TX_DESC_DATARATE(txdesc, value)
+#define GET_TX_DESC_DATARATE_8822C(txdesc) GET_TX_DESC_DATARATE(txdesc)
+
+/*TXDESC_WORD5*/
+
+#define SET_TX_DESC_POLLUTED_8822C(txdesc, value) \
+ SET_TX_DESC_POLLUTED(txdesc, value)
+#define GET_TX_DESC_POLLUTED_8822C(txdesc) GET_TX_DESC_POLLUTED(txdesc)
+#define SET_TX_DESC_ANTSEL_EN_8822C(txdesc, value) \
+ SET_TX_DESC_ANTSEL_EN_V1(txdesc, value)
+#define GET_TX_DESC_ANTSEL_EN_8822C(txdesc) GET_TX_DESC_ANTSEL_EN_V1(txdesc)
+#define SET_TX_DESC_TXPWR_OFSET_TYPE_8822C(txdesc, value) \
+ SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc, value)
+#define GET_TX_DESC_TXPWR_OFSET_TYPE_8822C(txdesc) \
+ GET_TX_DESC_TXPWR_OFSET_TYPE(txdesc)
+#define SET_TX_DESC_TX_ANT_8822C(txdesc, value) \
+ SET_TX_DESC_TX_ANT(txdesc, value)
+#define GET_TX_DESC_TX_ANT_8822C(txdesc) GET_TX_DESC_TX_ANT(txdesc)
+#define SET_TX_DESC_PORT_ID_8822C(txdesc, value) \
+ SET_TX_DESC_PORT_ID(txdesc, value)
+#define GET_TX_DESC_PORT_ID_8822C(txdesc) GET_TX_DESC_PORT_ID(txdesc)
+#define SET_TX_DESC_MULTIPLE_PORT_8822C(txdesc, value) \
+ SET_TX_DESC_MULTIPLE_PORT(txdesc, value)
+#define GET_TX_DESC_MULTIPLE_PORT_8822C(txdesc) \
+ GET_TX_DESC_MULTIPLE_PORT(txdesc)
+#define SET_TX_DESC_SIGNALING_TAPKT_EN_8822C(txdesc, value) \
+ SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value)
+#define GET_TX_DESC_SIGNALING_TAPKT_EN_8822C(txdesc) \
+ GET_TX_DESC_SIGNALING_TAPKT_EN(txdesc)
+#define SET_TX_DESC_SIGNALING_TA_PKT_SC_8822C(txdesc, value) \
+ SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc, value)
+#define GET_TX_DESC_SIGNALING_TA_PKT_SC_8822C(txdesc) \
+ GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc)
+#define SET_TX_DESC_RTS_SHORT_8822C(txdesc, value) \
+ SET_TX_DESC_RTS_SHORT(txdesc, value)
+#define GET_TX_DESC_RTS_SHORT_8822C(txdesc) GET_TX_DESC_RTS_SHORT(txdesc)
+#define SET_TX_DESC_VCS_STBC_8822C(txdesc, value) \
+ SET_TX_DESC_VCS_STBC(txdesc, value)
+#define GET_TX_DESC_VCS_STBC_8822C(txdesc) GET_TX_DESC_VCS_STBC(txdesc)
+#define SET_TX_DESC_DATA_STBC_8822C(txdesc, value) \
+ SET_TX_DESC_DATA_STBC(txdesc, value)
+#define GET_TX_DESC_DATA_STBC_8822C(txdesc) GET_TX_DESC_DATA_STBC(txdesc)
+#define SET_TX_DESC_DATA_LDPC_8822C(txdesc, value) \
+ SET_TX_DESC_DATA_LDPC(txdesc, value)
+#define GET_TX_DESC_DATA_LDPC_8822C(txdesc) GET_TX_DESC_DATA_LDPC(txdesc)
+#define SET_TX_DESC_DATA_BW_8822C(txdesc, value) \
+ SET_TX_DESC_DATA_BW(txdesc, value)
+#define GET_TX_DESC_DATA_BW_8822C(txdesc) GET_TX_DESC_DATA_BW(txdesc)
+#define SET_TX_DESC_DATA_SHORT_8822C(txdesc, value) \
+ SET_TX_DESC_DATA_SHORT(txdesc, value)
+#define GET_TX_DESC_DATA_SHORT_8822C(txdesc) GET_TX_DESC_DATA_SHORT(txdesc)
+#define SET_TX_DESC_DATA_SC_8822C(txdesc, value) \
+ SET_TX_DESC_DATA_SC(txdesc, value)
+#define GET_TX_DESC_DATA_SC_8822C(txdesc) GET_TX_DESC_DATA_SC(txdesc)
+
+/*TXDESC_WORD6*/
+
+#define SET_TX_DESC_ANTSEL_D_8822C(txdesc, value) \
+ SET_TX_DESC_ANTSEL_D(txdesc, value)
+#define GET_TX_DESC_ANTSEL_D_8822C(txdesc) GET_TX_DESC_ANTSEL_D(txdesc)
+#define SET_TX_DESC_ANT_MAPD_8822C(txdesc, value) \
+ SET_TX_DESC_ANT_MAPD(txdesc, value)
+#define GET_TX_DESC_ANT_MAPD_8822C(txdesc) GET_TX_DESC_ANT_MAPD(txdesc)
+#define SET_TX_DESC_ANT_MAPC_8822C(txdesc, value) \
+ SET_TX_DESC_ANT_MAPC(txdesc, value)
+#define GET_TX_DESC_ANT_MAPC_8822C(txdesc) GET_TX_DESC_ANT_MAPC(txdesc)
+#define SET_TX_DESC_ANT_MAPB_8822C(txdesc, value) \
+ SET_TX_DESC_ANT_MAPB(txdesc, value)
+#define GET_TX_DESC_ANT_MAPB_8822C(txdesc) GET_TX_DESC_ANT_MAPB(txdesc)
+#define SET_TX_DESC_ANT_MAPA_8822C(txdesc, value) \
+ SET_TX_DESC_ANT_MAPA(txdesc, value)
+#define GET_TX_DESC_ANT_MAPA_8822C(txdesc) GET_TX_DESC_ANT_MAPA(txdesc)
+#define SET_TX_DESC_ANTSEL_C_8822C(txdesc, value) \
+ SET_TX_DESC_ANTSEL_C(txdesc, value)
+#define GET_TX_DESC_ANTSEL_C_8822C(txdesc) GET_TX_DESC_ANTSEL_C(txdesc)
+#define SET_TX_DESC_ANTSEL_B_8822C(txdesc, value) \
+ SET_TX_DESC_ANTSEL_B(txdesc, value)
+#define GET_TX_DESC_ANTSEL_B_8822C(txdesc) GET_TX_DESC_ANTSEL_B(txdesc)
+#define SET_TX_DESC_ANTSEL_A_8822C(txdesc, value) \
+ SET_TX_DESC_ANTSEL_A(txdesc, value)
+#define GET_TX_DESC_ANTSEL_A_8822C(txdesc) GET_TX_DESC_ANTSEL_A(txdesc)
+#define SET_TX_DESC_MBSSID_8822C(txdesc, value) \
+ SET_TX_DESC_MBSSID(txdesc, value)
+#define GET_TX_DESC_MBSSID_8822C(txdesc) GET_TX_DESC_MBSSID(txdesc)
+#define SET_TX_DESC_SW_DEFINE_8822C(txdesc, value) \
+ SET_TX_DESC_SW_DEFINE(txdesc, value)
+#define GET_TX_DESC_SW_DEFINE_8822C(txdesc) GET_TX_DESC_SW_DEFINE(txdesc)
+
+/*TXDESC_WORD7*/
+
+#define SET_TX_DESC_DMA_TXAGG_NUM_8822C(txdesc, value) \
+ SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value)
+#define GET_TX_DESC_DMA_TXAGG_NUM_8822C(txdesc) \
+ GET_TX_DESC_DMA_TXAGG_NUM(txdesc)
+#define SET_TX_DESC_FINAL_DATA_RATE_8822C(txdesc, value) \
+ SET_TX_DESC_FINAL_DATA_RATE(txdesc, value)
+#define GET_TX_DESC_FINAL_DATA_RATE_8822C(txdesc) \
+ GET_TX_DESC_FINAL_DATA_RATE(txdesc)
+#define SET_TX_DESC_NTX_MAP_8822C(txdesc, value) \
+ SET_TX_DESC_NTX_MAP(txdesc, value)
+#define GET_TX_DESC_NTX_MAP_8822C(txdesc) GET_TX_DESC_NTX_MAP(txdesc)
+#define SET_TX_DESC_TX_BUFF_SIZE_8822C(txdesc, value) \
+ SET_TX_DESC_TX_BUFF_SIZE(txdesc, value)
+#define GET_TX_DESC_TX_BUFF_SIZE_8822C(txdesc) GET_TX_DESC_TX_BUFF_SIZE(txdesc)
+#define SET_TX_DESC_TXDESC_CHECKSUM_8822C(txdesc, value) \
+ SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value)
+#define GET_TX_DESC_TXDESC_CHECKSUM_8822C(txdesc) \
+ GET_TX_DESC_TXDESC_CHECKSUM(txdesc)
+#define SET_TX_DESC_TIMESTAMP_8822C(txdesc, value) \
+ SET_TX_DESC_TIMESTAMP(txdesc, value)
+#define GET_TX_DESC_TIMESTAMP_8822C(txdesc) GET_TX_DESC_TIMESTAMP(txdesc)
+
+/*TXDESC_WORD8*/
+
+#define SET_TX_DESC_TXWIFI_CP_8822C(txdesc, value) \
+ SET_TX_DESC_TXWIFI_CP(txdesc, value)
+#define GET_TX_DESC_TXWIFI_CP_8822C(txdesc) GET_TX_DESC_TXWIFI_CP(txdesc)
+#define SET_TX_DESC_MAC_CP_8822C(txdesc, value) \
+ SET_TX_DESC_MAC_CP(txdesc, value)
+#define GET_TX_DESC_MAC_CP_8822C(txdesc) GET_TX_DESC_MAC_CP(txdesc)
+#define SET_TX_DESC_STW_PKTRE_DIS_8822C(txdesc, value) \
+ SET_TX_DESC_STW_PKTRE_DIS(txdesc, value)
+#define GET_TX_DESC_STW_PKTRE_DIS_8822C(txdesc) \
+ GET_TX_DESC_STW_PKTRE_DIS(txdesc)
+#define SET_TX_DESC_STW_RB_DIS_8822C(txdesc, value) \
+ SET_TX_DESC_STW_RB_DIS(txdesc, value)
+#define GET_TX_DESC_STW_RB_DIS_8822C(txdesc) GET_TX_DESC_STW_RB_DIS(txdesc)
+#define SET_TX_DESC_STW_RATE_DIS_8822C(txdesc, value) \
+ SET_TX_DESC_STW_RATE_DIS(txdesc, value)
+#define GET_TX_DESC_STW_RATE_DIS_8822C(txdesc) GET_TX_DESC_STW_RATE_DIS(txdesc)
+#define SET_TX_DESC_STW_ANT_DIS_8822C(txdesc, value) \
+ SET_TX_DESC_STW_ANT_DIS(txdesc, value)
+#define GET_TX_DESC_STW_ANT_DIS_8822C(txdesc) GET_TX_DESC_STW_ANT_DIS(txdesc)
+#define SET_TX_DESC_STW_EN_8822C(txdesc, value) \
+ SET_TX_DESC_STW_EN(txdesc, value)
+#define GET_TX_DESC_STW_EN_8822C(txdesc) GET_TX_DESC_STW_EN(txdesc)
+#define SET_TX_DESC_SMH_EN_8822C(txdesc, value) \
+ SET_TX_DESC_SMH_EN(txdesc, value)
+#define GET_TX_DESC_SMH_EN_8822C(txdesc) GET_TX_DESC_SMH_EN(txdesc)
+#define SET_TX_DESC_TAILPAGE_L_8822C(txdesc, value) \
+ SET_TX_DESC_TAILPAGE_L(txdesc, value)
+#define GET_TX_DESC_TAILPAGE_L_8822C(txdesc) GET_TX_DESC_TAILPAGE_L(txdesc)
+#define SET_TX_DESC_SDIO_DMASEQ_8822C(txdesc, value) \
+ SET_TX_DESC_SDIO_DMASEQ(txdesc, value)
+#define GET_TX_DESC_SDIO_DMASEQ_8822C(txdesc) GET_TX_DESC_SDIO_DMASEQ(txdesc)
+#define SET_TX_DESC_NEXTHEADPAGE_L_8822C(txdesc, value) \
+ SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value)
+#define GET_TX_DESC_NEXTHEADPAGE_L_8822C(txdesc) \
+ GET_TX_DESC_NEXTHEADPAGE_L(txdesc)
+#define SET_TX_DESC_EN_HWSEQ_8822C(txdesc, value) \
+ SET_TX_DESC_EN_HWSEQ(txdesc, value)
+#define GET_TX_DESC_EN_HWSEQ_8822C(txdesc) GET_TX_DESC_EN_HWSEQ(txdesc)
+#define SET_TX_DESC_EN_HWEXSEQ_8822C(txdesc, value) \
+ SET_TX_DESC_EN_HWEXSEQ(txdesc, value)
+#define GET_TX_DESC_EN_HWEXSEQ_8822C(txdesc) GET_TX_DESC_EN_HWEXSEQ(txdesc)
+#define SET_TX_DESC_DATA_RC_8822C(txdesc, value) \
+ SET_TX_DESC_DATA_RC(txdesc, value)
+#define GET_TX_DESC_DATA_RC_8822C(txdesc) GET_TX_DESC_DATA_RC(txdesc)
+#define SET_TX_DESC_BAR_RTY_TH_8822C(txdesc, value) \
+ SET_TX_DESC_BAR_RTY_TH(txdesc, value)
+#define GET_TX_DESC_BAR_RTY_TH_8822C(txdesc) GET_TX_DESC_BAR_RTY_TH(txdesc)
+#define SET_TX_DESC_RTS_RC_8822C(txdesc, value) \
+ SET_TX_DESC_RTS_RC(txdesc, value)
+#define GET_TX_DESC_RTS_RC_8822C(txdesc) GET_TX_DESC_RTS_RC(txdesc)
+
+/*TXDESC_WORD9*/
+
+#define SET_TX_DESC_TAILPAGE_H_8822C(txdesc, value) \
+ SET_TX_DESC_TAILPAGE_H(txdesc, value)
+#define GET_TX_DESC_TAILPAGE_H_8822C(txdesc) GET_TX_DESC_TAILPAGE_H(txdesc)
+#define SET_TX_DESC_NEXTHEADPAGE_H_8822C(txdesc, value) \
+ SET_TX_DESC_NEXTHEADPAGE_H(txdesc, value)
+#define GET_TX_DESC_NEXTHEADPAGE_H_8822C(txdesc) \
+ GET_TX_DESC_NEXTHEADPAGE_H(txdesc)
+#define SET_TX_DESC_SW_SEQ_8822C(txdesc, value) \
+ SET_TX_DESC_SW_SEQ(txdesc, value)
+#define GET_TX_DESC_SW_SEQ_8822C(txdesc) GET_TX_DESC_SW_SEQ(txdesc)
+#define SET_TX_DESC_TXBF_PATH_8822C(txdesc, value) \
+ SET_TX_DESC_TXBF_PATH(txdesc, value)
+#define GET_TX_DESC_TXBF_PATH_8822C(txdesc) GET_TX_DESC_TXBF_PATH(txdesc)
+#define SET_TX_DESC_PADDING_LEN_8822C(txdesc, value) \
+ SET_TX_DESC_PADDING_LEN(txdesc, value)
+#define GET_TX_DESC_PADDING_LEN_8822C(txdesc) GET_TX_DESC_PADDING_LEN(txdesc)
+#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8822C(txdesc, value) \
+ SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value)
+#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8822C(txdesc) \
+ GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc)
+
+/*WORD10*/
+
+#define SET_TX_DESC_MU_DATARATE_8822C(txdesc, value) \
+ SET_TX_DESC_MU_DATARATE(txdesc, value)
+#define GET_TX_DESC_MU_DATARATE_8822C(txdesc) GET_TX_DESC_MU_DATARATE(txdesc)
+#define SET_TX_DESC_MU_RC_8822C(txdesc, value) SET_TX_DESC_MU_RC(txdesc, value)
+#define GET_TX_DESC_MU_RC_8822C(txdesc) GET_TX_DESC_MU_RC(txdesc)
+#define SET_TX_DESC_SND_PKT_SEL_8822C(txdesc, value) \
+ SET_TX_DESC_SND_PKT_SEL(txdesc, value)
+#define GET_TX_DESC_SND_PKT_SEL_8822C(txdesc) GET_TX_DESC_SND_PKT_SEL(txdesc)
+
+#endif
#endif
diff --git a/hal/halmac/halmac_tx_desc_ie_ap.h b/hal/halmac/halmac_tx_desc_ie_ap.h
new file mode 100644
index 0000000..a6d215f
--- /dev/null
+++ b/hal/halmac/halmac_tx_desc_ie_ap.h
@@ -0,0 +1,1005 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_TX_DESC_IE_AP_H_
+#define _HALMAC_TX_DESC_IE_AP_H_
+#if (HALMAC_8814B_SUPPORT)
+
+#define IE0_GET_TX_DESC_IE_END(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 31)
+#define IE0_SET_TX_DESC_IE_END(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31)
+#define IE0_SET_TX_DESC_IE_END_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31)
+#define IE0_GET_TX_DESC_IE_UP(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 30)
+#define IE0_SET_TX_DESC_IE_UP(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30)
+#define IE0_SET_TX_DESC_IE_UP_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30)
+#define IE0_GET_TX_DESC_IE_NUM(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0xf, 24)
+#define IE0_SET_TX_DESC_IE_NUM(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24)
+#define IE0_SET_TX_DESC_IE_NUM_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24)
+#define IE0_GET_TX_DESC_ARFR_TABLE_SEL(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 19)
+#define IE0_SET_TX_DESC_ARFR_TABLE_SEL(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 19)
+#define IE0_SET_TX_DESC_ARFR_TABLE_SEL_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 19)
+#define IE0_GET_TX_DESC_ARFR_HT_EN(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 18)
+#define IE0_SET_TX_DESC_ARFR_HT_EN(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 18)
+#define IE0_SET_TX_DESC_ARFR_HT_EN_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 18)
+#define IE0_GET_TX_DESC_ARFR_OFDM_EN(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 17)
+#define IE0_SET_TX_DESC_ARFR_OFDM_EN(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 17)
+#define IE0_SET_TX_DESC_ARFR_OFDM_EN_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 17)
+#define IE0_GET_TX_DESC_ARFR_CCK_EN(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 16)
+#define IE0_SET_TX_DESC_ARFR_CCK_EN(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 16)
+#define IE0_SET_TX_DESC_ARFR_CCK_EN_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 16)
+#define IE0_GET_TX_DESC_HW_RTS_EN(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 9)
+#define IE0_SET_TX_DESC_HW_RTS_EN(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 9)
+#define IE0_SET_TX_DESC_HW_RTS_EN_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 9)
+#define IE0_GET_TX_DESC_RTS_EN(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 8)
+#define IE0_SET_TX_DESC_RTS_EN(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 8)
+#define IE0_SET_TX_DESC_RTS_EN_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 8)
+#define IE0_GET_TX_DESC_CTS2SELF(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 7)
+#define IE0_SET_TX_DESC_CTS2SELF(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 7)
+#define IE0_SET_TX_DESC_CTS2SELF_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 7)
+#define IE0_GET_TX_DESC_RTY_LMT_EN(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 6)
+#define IE0_SET_TX_DESC_RTY_LMT_EN(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 6)
+#define IE0_SET_TX_DESC_RTY_LMT_EN_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 6)
+#define IE0_GET_TX_DESC_RTS_SHORT(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 5)
+#define IE0_SET_TX_DESC_RTS_SHORT(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 5)
+#define IE0_SET_TX_DESC_RTS_SHORT_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 5)
+#define IE0_GET_TX_DESC_DISDATAFB(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 4)
+#define IE0_SET_TX_DESC_DISDATAFB(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 4)
+#define IE0_SET_TX_DESC_DISDATAFB_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 4)
+#define IE0_GET_TX_DESC_DISRTSFB(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 3)
+#define IE0_SET_TX_DESC_DISRTSFB(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 3)
+#define IE0_SET_TX_DESC_DISRTSFB_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 3)
+#define IE0_GET_TX_DESC_DATA_SHORT(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 2)
+#define IE0_SET_TX_DESC_DATA_SHORT(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2)
+#define IE0_SET_TX_DESC_DATA_SHORT_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2)
+#define IE0_GET_TX_DESC_TRY_RATE(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 1)
+#define IE0_SET_TX_DESC_TRY_RATE(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1)
+#define IE0_SET_TX_DESC_TRY_RATE_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1)
+#define IE0_GET_TX_DESC_USERATE(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 0)
+#define IE0_SET_TX_DESC_USERATE(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0)
+#define IE0_SET_TX_DESC_USERATE_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0)
+#define IE0_GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \
+ 0xf, 27)
+#define IE0_SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 27)
+#define IE0_SET_TX_DESC_RTS_RTY_LOWEST_RATE_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 27)
+#define IE0_GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \
+ 0x1f, 22)
+#define IE0_SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1f, 22)
+#define IE0_SET_TX_DESC_DATA_RTY_LOWEST_RATE_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1f, 22)
+#define IE0_GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \
+ 0x3f, 16)
+#define IE0_SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3f, 16)
+#define IE0_SET_TX_DESC_RTS_DATA_RTY_LMT_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3f, 16)
+#define IE0_GET_TX_DESC_DATA_BW(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \
+ 0x3, 12)
+#define IE0_SET_TX_DESC_DATA_BW(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 12)
+#define IE0_SET_TX_DESC_DATA_BW_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 12)
+#define IE0_GET_TX_DESC_RTSRATE(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \
+ 0xf, 7)
+#define IE0_SET_TX_DESC_RTSRATE(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 7)
+#define IE0_SET_TX_DESC_RTSRATE_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 7)
+#define IE0_GET_TX_DESC_DATARATE(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \
+ 0x7f, 0)
+#define IE0_SET_TX_DESC_DATARATE(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x7f, 0)
+#define IE0_SET_TX_DESC_DATARATE_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x7f, 0)
+#define IE1_GET_TX_DESC_IE_END(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 31)
+#define IE1_SET_TX_DESC_IE_END(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31)
+#define IE1_SET_TX_DESC_IE_END_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31)
+#define IE1_GET_TX_DESC_IE_UP(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 30)
+#define IE1_SET_TX_DESC_IE_UP(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30)
+#define IE1_SET_TX_DESC_IE_UP_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30)
+#define IE1_GET_TX_DESC_IE_NUM(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0xf, 24)
+#define IE1_SET_TX_DESC_IE_NUM(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24)
+#define IE1_SET_TX_DESC_IE_NUM_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24)
+#define IE1_GET_TX_DESC_AMPDU_DENSITY(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x7, 21)
+#define IE1_SET_TX_DESC_AMPDU_DENSITY(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x7, 21)
+#define IE1_SET_TX_DESC_AMPDU_DENSITY_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x7, 21)
+#define IE1_GET_TX_DESC_MAX_AGG_NUM(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1f, 16)
+#define IE1_SET_TX_DESC_MAX_AGG_NUM(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1f, 16)
+#define IE1_SET_TX_DESC_MAX_AGG_NUM_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1f, 16)
+#define IE1_GET_TX_DESC_SECTYPE(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x3, 14)
+#define IE1_SET_TX_DESC_SECTYPE(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 14)
+#define IE1_SET_TX_DESC_SECTYPE_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 14)
+#define IE1_GET_TX_DESC_MOREFRAG(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 13)
+#define IE1_SET_TX_DESC_MOREFRAG(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 13)
+#define IE1_SET_TX_DESC_MOREFRAG_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 13)
+#define IE1_GET_TX_DESC_NOACM(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 12)
+#define IE1_SET_TX_DESC_NOACM(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 12)
+#define IE1_SET_TX_DESC_NOACM_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 12)
+#define IE1_GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 11)
+#define IE1_SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 11)
+#define IE1_SET_TX_DESC_BCNPKT_TSF_CTRL_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 11)
+#define IE1_GET_TX_DESC_NAVUSEHDR(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 10)
+#define IE1_SET_TX_DESC_NAVUSEHDR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 10)
+#define IE1_SET_TX_DESC_NAVUSEHDR_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 10)
+#define IE1_GET_TX_DESC_HTC(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 9)
+#define IE1_SET_TX_DESC_HTC(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 9)
+#define IE1_SET_TX_DESC_HTC_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 9)
+#define IE1_GET_TX_DESC_BMC(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 8)
+#define IE1_SET_TX_DESC_BMC(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 8)
+#define IE1_SET_TX_DESC_BMC_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 8)
+#define IE1_GET_TX_DESC_TX_PKT_AFTER_PIFS(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 7)
+#define IE1_SET_TX_DESC_TX_PKT_AFTER_PIFS(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 7)
+#define IE1_SET_TX_DESC_TX_PKT_AFTER_PIFS_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 7)
+#define IE1_GET_TX_DESC_USE_MAX_TIME_EN(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 6)
+#define IE1_SET_TX_DESC_USE_MAX_TIME_EN(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 6)
+#define IE1_SET_TX_DESC_USE_MAX_TIME_EN_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 6)
+#define IE1_GET_TX_DESC_HW_SSN_SEL(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x3, 4)
+#define IE1_SET_TX_DESC_HW_SSN_SEL(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 4)
+#define IE1_SET_TX_DESC_HW_SSN_SEL_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 4)
+#define IE1_GET_TX_DESC_DISQSELSEQ(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 3)
+#define IE1_SET_TX_DESC_DISQSELSEQ(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 3)
+#define IE1_SET_TX_DESC_DISQSELSEQ_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 3)
+#define IE1_GET_TX_DESC_EN_HWSEQ(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 2)
+#define IE1_SET_TX_DESC_EN_HWSEQ(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2)
+#define IE1_SET_TX_DESC_EN_HWSEQ_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2)
+#define IE1_GET_TX_DESC_EN_HWEXSEQ(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 1)
+#define IE1_SET_TX_DESC_EN_HWEXSEQ(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1)
+#define IE1_SET_TX_DESC_EN_HWEXSEQ_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1)
+#define IE1_GET_TX_DESC_EN_DESC_ID(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 0)
+#define IE1_SET_TX_DESC_EN_DESC_ID(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0)
+#define IE1_SET_TX_DESC_EN_DESC_ID_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0)
+#define IE1_GET_TX_DESC_AMPDU_MAX_TIME(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \
+ 0xff, 24)
+#define IE1_SET_TX_DESC_AMPDU_MAX_TIME(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xff, 24)
+#define IE1_SET_TX_DESC_AMPDU_MAX_TIME_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xff, 24)
+#define IE1_GET_TX_DESC_P_AID(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \
+ 0x1ff, 15)
+#define IE1_SET_TX_DESC_P_AID(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1ff, \
+ 15)
+#define IE1_SET_TX_DESC_P_AID_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1ff, \
+ 15)
+#define IE1_GET_TX_DESC_MOREDATA(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \
+ 0x1, 14)
+#define IE1_SET_TX_DESC_MOREDATA(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1, 14)
+#define IE1_SET_TX_DESC_MOREDATA_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1, 14)
+#define IE1_GET_TX_DESC_SW_SEQ(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \
+ 0xfff, 0)
+#define IE1_SET_TX_DESC_SW_SEQ(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xfff, 0)
+#define IE1_SET_TX_DESC_SW_SEQ_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xfff, 0)
+#define IE2_GET_TX_DESC_IE_END(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 31)
+#define IE2_SET_TX_DESC_IE_END(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31)
+#define IE2_SET_TX_DESC_IE_END_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31)
+#define IE2_GET_TX_DESC_IE_UP(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 30)
+#define IE2_SET_TX_DESC_IE_UP(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30)
+#define IE2_SET_TX_DESC_IE_UP_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30)
+#define IE2_GET_TX_DESC_IE_NUM(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0xf, 24)
+#define IE2_SET_TX_DESC_IE_NUM(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24)
+#define IE2_SET_TX_DESC_IE_NUM_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24)
+#define IE2_GET_TX_DESC_ADDR_CAM(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0xff, 16)
+#define IE2_SET_TX_DESC_ADDR_CAM(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xff, 16)
+#define IE2_SET_TX_DESC_ADDR_CAM_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xff, 16)
+#define IE2_GET_TX_DESC_MULTIPLE_PORT(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x7, 12)
+#define IE2_SET_TX_DESC_MULTIPLE_PORT(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x7, 12)
+#define IE2_SET_TX_DESC_MULTIPLE_PORT_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x7, 12)
+#define IE2_GET_TX_DESC_RAW(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 11)
+#define IE2_SET_TX_DESC_RAW(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 11)
+#define IE2_SET_TX_DESC_RAW_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 11)
+#define IE2_GET_TX_DESC_RDG_EN(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 10)
+#define IE2_SET_TX_DESC_RDG_EN(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 10)
+#define IE2_SET_TX_DESC_RDG_EN_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 10)
+#define IE2_GET_TX_DESC_SPECIAL_CW(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 7)
+#define IE2_SET_TX_DESC_SPECIAL_CW(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 7)
+#define IE2_SET_TX_DESC_SPECIAL_CW_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 7)
+#define IE2_GET_TX_DESC_POLLUTED(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 6)
+#define IE2_SET_TX_DESC_POLLUTED(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 6)
+#define IE2_SET_TX_DESC_POLLUTED_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 6)
+#define IE2_GET_TX_DESC_BT_NULL(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 5)
+#define IE2_SET_TX_DESC_BT_NULL(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 5)
+#define IE2_SET_TX_DESC_BT_NULL_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 5)
+#define IE2_GET_TX_DESC_NULL_1(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 4)
+#define IE2_SET_TX_DESC_NULL_1(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 4)
+#define IE2_SET_TX_DESC_NULL_1_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 4)
+#define IE2_GET_TX_DESC_NULL_0(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 3)
+#define IE2_SET_TX_DESC_NULL_0(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 3)
+#define IE2_SET_TX_DESC_NULL_0_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 3)
+#define IE2_GET_TX_DESC_TRI_FRAME(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 2)
+#define IE2_SET_TX_DESC_TRI_FRAME(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2)
+#define IE2_SET_TX_DESC_TRI_FRAME_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2)
+#define IE2_GET_TX_DESC_SPE_RPT(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 1)
+#define IE2_SET_TX_DESC_SPE_RPT(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1)
+#define IE2_SET_TX_DESC_SPE_RPT_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1)
+#define IE2_GET_TX_DESC_FTM_EN(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 0)
+#define IE2_SET_TX_DESC_FTM_EN(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0)
+#define IE2_SET_TX_DESC_FTM_EN_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0)
+#define IE2_GET_TX_DESC_MBSSID(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \
+ 0xf, 27)
+#define IE2_SET_TX_DESC_MBSSID(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 27)
+#define IE2_SET_TX_DESC_MBSSID_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 27)
+#define IE2_GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \
+ 0x7ff, 16)
+#define IE2_SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x7ff, \
+ 16)
+#define IE2_SET_TX_DESC_GROUP_BIT_IE_OFFSET_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x7ff, \
+ 16)
+#define IE2_GET_TX_DESC_RDG_NAV_EXT(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \
+ 0x1, 15)
+#define IE2_SET_TX_DESC_RDG_NAV_EXT(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1, 15)
+#define IE2_SET_TX_DESC_RDG_NAV_EXT_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1, 15)
+#define IE2_GET_TX_DESC_DROP_ID(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \
+ 0x3, 12)
+#define IE2_SET_TX_DESC_DROP_ID(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 12)
+#define IE2_SET_TX_DESC_DROP_ID_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 12)
+#define IE2_GET_TX_DESC_SW_DEFINE(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \
+ 0xfff, 0)
+#define IE2_SET_TX_DESC_SW_DEFINE(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xfff, 0)
+#define IE2_SET_TX_DESC_SW_DEFINE_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xfff, 0)
+#define IE3_GET_TX_DESC_IE_END(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 31)
+#define IE3_SET_TX_DESC_IE_END(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31)
+#define IE3_SET_TX_DESC_IE_END_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31)
+#define IE3_GET_TX_DESC_IE_UP(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 30)
+#define IE3_SET_TX_DESC_IE_UP(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30)
+#define IE3_SET_TX_DESC_IE_UP_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30)
+#define IE3_GET_TX_DESC_IE_NUM(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0xf, 24)
+#define IE3_SET_TX_DESC_IE_NUM(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24)
+#define IE3_SET_TX_DESC_IE_NUM_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24)
+#define IE3_GET_TX_DESC_DATA_SC(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0xf, 20)
+#define IE3_SET_TX_DESC_DATA_SC(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 20)
+#define IE3_SET_TX_DESC_DATA_SC_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 20)
+#define IE3_GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0xf, 16)
+#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 16)
+#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_SC_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 16)
+#define IE3_GET_TX_DESC_CTRL_CNT(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0xf, 8)
+#define IE3_SET_TX_DESC_CTRL_CNT(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 8)
+#define IE3_SET_TX_DESC_CTRL_CNT_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 8)
+#define IE3_GET_TX_DESC_CTRL_CNT_VALID(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 1)
+#define IE3_SET_TX_DESC_CTRL_CNT_VALID(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1)
+#define IE3_SET_TX_DESC_CTRL_CNT_VALID_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1)
+#define IE3_GET_TX_DESC_SIGNALING_TA_PKT_EN(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 0)
+#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_EN(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0)
+#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_EN_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0)
+#define IE3_GET_TX_DESC_G_ID(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \
+ 0x3f, 24)
+#define IE3_SET_TX_DESC_G_ID(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3f, 24)
+#define IE3_SET_TX_DESC_G_ID_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3f, 24)
+#define IE3_GET_TX_DESC_SND_TARGET(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \
+ 0xff, 16)
+#define IE3_SET_TX_DESC_SND_TARGET(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xff, 16)
+#define IE3_SET_TX_DESC_SND_TARGET_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xff, 16)
+#define IE3_GET_TX_DESC_CCA_RTS(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \
+ 0x3, 11)
+#define IE3_SET_TX_DESC_CCA_RTS(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 11)
+#define IE3_SET_TX_DESC_CCA_RTS_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 11)
+#define IE3_GET_TX_DESC_SND_PKT_SEL(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \
+ 0x3, 9)
+#define IE3_SET_TX_DESC_SND_PKT_SEL(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 9)
+#define IE3_SET_TX_DESC_SND_PKT_SEL_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 9)
+#define IE3_GET_TX_DESC_NDPA(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \
+ 0x3, 7)
+#define IE3_SET_TX_DESC_NDPA(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 7)
+#define IE3_SET_TX_DESC_NDPA_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 7)
+#define IE3_GET_TX_DESC_MU_DATARATE(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \
+ 0x7f, 0)
+#define IE3_SET_TX_DESC_MU_DATARATE(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x7f, 0)
+#define IE3_SET_TX_DESC_MU_DATARATE_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x7f, 0)
+#define IE4_GET_TX_DESC_IE_END(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 31)
+#define IE4_SET_TX_DESC_IE_END(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31)
+#define IE4_SET_TX_DESC_IE_END_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31)
+#define IE4_GET_TX_DESC_IE_UP(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 30)
+#define IE4_SET_TX_DESC_IE_UP(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30)
+#define IE4_SET_TX_DESC_IE_UP_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30)
+#define IE4_GET_TX_DESC_IE_NUM(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0xf, 24)
+#define IE4_SET_TX_DESC_IE_NUM(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24)
+#define IE4_SET_TX_DESC_IE_NUM_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24)
+#define IE4_GET_TX_DESC_VCS_STBC(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x3, 10)
+#define IE4_SET_TX_DESC_VCS_STBC(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 10)
+#define IE4_SET_TX_DESC_VCS_STBC_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 10)
+#define IE4_GET_TX_DESC_DATA_STBC(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x3, 8)
+#define IE4_SET_TX_DESC_DATA_STBC(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 8)
+#define IE4_SET_TX_DESC_DATA_STBC_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x3, 8)
+#define IE4_GET_TX_DESC_DATA_LDPC(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 2)
+#define IE4_SET_TX_DESC_DATA_LDPC(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2)
+#define IE4_SET_TX_DESC_DATA_LDPC_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 2)
+#define IE4_GET_TX_DESC_GF(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 1)
+#define IE4_SET_TX_DESC_GF(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1)
+#define IE4_SET_TX_DESC_GF_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 1)
+#define IE4_GET_TX_DESC_LSIG_TXOP_EN(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 0)
+#define IE4_SET_TX_DESC_LSIG_TXOP_EN(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0)
+#define IE4_SET_TX_DESC_LSIG_TXOP_EN_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 0)
+#define IE4_GET_TX_DESC_PATH_MAPA(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \
+ 0x3, 30)
+#define IE4_SET_TX_DESC_PATH_MAPA(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 30)
+#define IE4_SET_TX_DESC_PATH_MAPA_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 30)
+#define IE4_GET_TX_DESC_PATH_MAPB(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \
+ 0x3, 28)
+#define IE4_SET_TX_DESC_PATH_MAPB(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 28)
+#define IE4_SET_TX_DESC_PATH_MAPB_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 28)
+#define IE4_GET_TX_DESC_PATH_MAPC(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \
+ 0x3, 26)
+#define IE4_SET_TX_DESC_PATH_MAPC(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 26)
+#define IE4_SET_TX_DESC_PATH_MAPC_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 26)
+#define IE4_GET_TX_DESC_PATH_MAPD(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \
+ 0x3, 24)
+#define IE4_SET_TX_DESC_PATH_MAPD(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 24)
+#define IE4_SET_TX_DESC_PATH_MAPD_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 24)
+#define IE4_GET_TX_DESC_ANTSEL_A(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \
+ 0xf, 20)
+#define IE4_SET_TX_DESC_ANTSEL_A(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 20)
+#define IE4_SET_TX_DESC_ANTSEL_A_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 20)
+#define IE4_GET_TX_DESC_ANTSEL_B(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \
+ 0xf, 16)
+#define IE4_SET_TX_DESC_ANTSEL_B(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 16)
+#define IE4_SET_TX_DESC_ANTSEL_B_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 16)
+#define IE4_GET_TX_DESC_ANTSEL_C(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \
+ 0xf, 12)
+#define IE4_SET_TX_DESC_ANTSEL_C(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 12)
+#define IE4_SET_TX_DESC_ANTSEL_C_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 12)
+#define IE4_GET_TX_DESC_ANTSEL_D(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \
+ 0xf, 8)
+#define IE4_SET_TX_DESC_ANTSEL_D(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 8)
+#define IE4_SET_TX_DESC_ANTSEL_D_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 8)
+#define IE4_GET_TX_DESC_NTX_PATH_EN(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \
+ 0xf, 4)
+#define IE4_SET_TX_DESC_NTX_PATH_EN(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 4)
+#define IE4_SET_TX_DESC_NTX_PATH_EN_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0xf, 4)
+#define IE4_GET_TX_DESC_ANTLSEL_EN(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \
+ 0x1, 3)
+#define IE4_SET_TX_DESC_ANTLSEL_EN(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1, 3)
+#define IE4_SET_TX_DESC_ANTLSEL_EN_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1, 3)
+#define IE4_GET_TX_DESC_TXPWR_OFSET_TYPE(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \
+ 0x3, 0)
+#define IE4_SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 0)
+#define IE4_SET_TX_DESC_TXPWR_OFSET_TYPE_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3, 0)
+#define IE5_GET_TX_DESC_IE_END(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 31)
+#define IE5_SET_TX_DESC_IE_END(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31)
+#define IE5_SET_TX_DESC_IE_END_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 31)
+#define IE5_GET_TX_DESC_IE_UP(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1, 30)
+#define IE5_SET_TX_DESC_IE_UP(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30)
+#define IE5_SET_TX_DESC_IE_UP_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1, 30)
+#define IE5_GET_TX_DESC_IE_NUM(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0xf, 24)
+#define IE5_SET_TX_DESC_IE_NUM(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24)
+#define IE5_SET_TX_DESC_IE_NUM_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 24)
+#define IE5_GET_TX_DESC_LEN1_L(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x7f, 17)
+#define IE5_SET_TX_DESC_LEN1_L(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x7f, 17)
+#define IE5_SET_TX_DESC_LEN1_L_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x7f, 17)
+#define IE5_GET_TX_DESC_LEN0(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0x1fff, 4)
+#define IE5_SET_TX_DESC_LEN0(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1fff, \
+ 4)
+#define IE5_SET_TX_DESC_LEN0_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0x1fff, \
+ 4)
+#define IE5_GET_TX_DESC_PKT_NUM(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword0, \
+ 0xf, 0)
+#define IE5_SET_TX_DESC_PKT_NUM(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 0)
+#define IE5_SET_TX_DESC_PKT_NUM_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword0, value, 0xf, 0)
+#define IE5_GET_TX_DESC_LEN3(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \
+ 0x1fff, 19)
+#define IE5_SET_TX_DESC_LEN3(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1fff, \
+ 19)
+#define IE5_SET_TX_DESC_LEN3_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1fff, \
+ 19)
+#define IE5_GET_TX_DESC_LEN2(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \
+ 0x1fff, 6)
+#define IE5_SET_TX_DESC_LEN2(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1fff, \
+ 6)
+#define IE5_SET_TX_DESC_LEN2_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x1fff, \
+ 6)
+#define IE5_GET_TX_DESC_LEN1_H(txdesc_ie) \
+ HALMAC_GET_DESC_FIELD(((struct halmac_tx_desc *)txdesc_ie)->dword1, \
+ 0x3f, 0)
+#define IE5_SET_TX_DESC_LEN1_H(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3f, 0)
+#define IE5_SET_TX_DESC_LEN1_H_NO_CLR(txdesc_ie, value) \
+ HALMAC_SET_DESC_FIELD_NO_CLR( \
+ ((struct halmac_tx_desc *)txdesc_ie)->dword1, value, 0x3f, 0)
+
+#endif
+
+#endif
diff --git a/hal/halmac/halmac_tx_desc_ie_chip.h b/hal/halmac/halmac_tx_desc_ie_chip.h
new file mode 100644
index 0000000..8126a0c
--- /dev/null
+++ b/hal/halmac/halmac_tx_desc_ie_chip.h
@@ -0,0 +1,438 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_TX_DESC_IE_CHIP_H_
+#define _HALMAC_TX_DESC_IE_CHIP_H_
+#if (HALMAC_8814B_SUPPORT)
+
+#define IE0_GET_TX_DESC_IE_END_8814B(txdesc_ie) \
+ IE0_GET_TX_DESC_IE_END(txdesc_ie)
+#define IE0_SET_TX_DESC_IE_END_8814B(txdesc_ie, value) \
+ IE0_SET_TX_DESC_IE_END(txdesc_ie, value)
+#define IE0_GET_TX_DESC_IE_UP_8814B(txdesc_ie) IE0_GET_TX_DESC_IE_UP(txdesc_ie)
+#define IE0_SET_TX_DESC_IE_UP_8814B(txdesc_ie, value) \
+ IE0_SET_TX_DESC_IE_UP(txdesc_ie, value)
+#define IE0_GET_TX_DESC_IE_NUM_8814B(txdesc_ie) \
+ IE0_GET_TX_DESC_IE_NUM(txdesc_ie)
+#define IE0_SET_TX_DESC_IE_NUM_8814B(txdesc_ie, value) \
+ IE0_SET_TX_DESC_IE_NUM(txdesc_ie, value)
+#define IE0_GET_TX_DESC_ARFR_TABLE_SEL_8814B(txdesc_ie) \
+ IE0_GET_TX_DESC_ARFR_TABLE_SEL(txdesc_ie)
+#define IE0_SET_TX_DESC_ARFR_TABLE_SEL_8814B(txdesc_ie, value) \
+ IE0_SET_TX_DESC_ARFR_TABLE_SEL(txdesc_ie, value)
+#define IE0_GET_TX_DESC_ARFR_HT_EN_8814B(txdesc_ie) \
+ IE0_GET_TX_DESC_ARFR_HT_EN(txdesc_ie)
+#define IE0_SET_TX_DESC_ARFR_HT_EN_8814B(txdesc_ie, value) \
+ IE0_SET_TX_DESC_ARFR_HT_EN(txdesc_ie, value)
+#define IE0_GET_TX_DESC_ARFR_OFDM_EN_8814B(txdesc_ie) \
+ IE0_GET_TX_DESC_ARFR_OFDM_EN(txdesc_ie)
+#define IE0_SET_TX_DESC_ARFR_OFDM_EN_8814B(txdesc_ie, value) \
+ IE0_SET_TX_DESC_ARFR_OFDM_EN(txdesc_ie, value)
+#define IE0_GET_TX_DESC_ARFR_CCK_EN_8814B(txdesc_ie) \
+ IE0_GET_TX_DESC_ARFR_CCK_EN(txdesc_ie)
+#define IE0_SET_TX_DESC_ARFR_CCK_EN_8814B(txdesc_ie, value) \
+ IE0_SET_TX_DESC_ARFR_CCK_EN(txdesc_ie, value)
+#define IE0_GET_TX_DESC_HW_RTS_EN_8814B(txdesc_ie) \
+ IE0_GET_TX_DESC_HW_RTS_EN(txdesc_ie)
+#define IE0_SET_TX_DESC_HW_RTS_EN_8814B(txdesc_ie, value) \
+ IE0_SET_TX_DESC_HW_RTS_EN(txdesc_ie, value)
+#define IE0_GET_TX_DESC_RTS_EN_8814B(txdesc_ie) \
+ IE0_GET_TX_DESC_RTS_EN(txdesc_ie)
+#define IE0_SET_TX_DESC_RTS_EN_8814B(txdesc_ie, value) \
+ IE0_SET_TX_DESC_RTS_EN(txdesc_ie, value)
+#define IE0_GET_TX_DESC_CTS2SELF_8814B(txdesc_ie) \
+ IE0_GET_TX_DESC_CTS2SELF(txdesc_ie)
+#define IE0_SET_TX_DESC_CTS2SELF_8814B(txdesc_ie, value) \
+ IE0_SET_TX_DESC_CTS2SELF(txdesc_ie, value)
+#define IE0_GET_TX_DESC_RTY_LMT_EN_8814B(txdesc_ie) \
+ IE0_GET_TX_DESC_RTY_LMT_EN(txdesc_ie)
+#define IE0_SET_TX_DESC_RTY_LMT_EN_8814B(txdesc_ie, value) \
+ IE0_SET_TX_DESC_RTY_LMT_EN(txdesc_ie, value)
+#define IE0_GET_TX_DESC_RTS_SHORT_8814B(txdesc_ie) \
+ IE0_GET_TX_DESC_RTS_SHORT(txdesc_ie)
+#define IE0_SET_TX_DESC_RTS_SHORT_8814B(txdesc_ie, value) \
+ IE0_SET_TX_DESC_RTS_SHORT(txdesc_ie, value)
+#define IE0_GET_TX_DESC_DISDATAFB_8814B(txdesc_ie) \
+ IE0_GET_TX_DESC_DISDATAFB(txdesc_ie)
+#define IE0_SET_TX_DESC_DISDATAFB_8814B(txdesc_ie, value) \
+ IE0_SET_TX_DESC_DISDATAFB(txdesc_ie, value)
+#define IE0_GET_TX_DESC_DISRTSFB_8814B(txdesc_ie) \
+ IE0_GET_TX_DESC_DISRTSFB(txdesc_ie)
+#define IE0_SET_TX_DESC_DISRTSFB_8814B(txdesc_ie, value) \
+ IE0_SET_TX_DESC_DISRTSFB(txdesc_ie, value)
+#define IE0_GET_TX_DESC_DATA_SHORT_8814B(txdesc_ie) \
+ IE0_GET_TX_DESC_DATA_SHORT(txdesc_ie)
+#define IE0_SET_TX_DESC_DATA_SHORT_8814B(txdesc_ie, value) \
+ IE0_SET_TX_DESC_DATA_SHORT(txdesc_ie, value)
+#define IE0_GET_TX_DESC_TRY_RATE_8814B(txdesc_ie) \
+ IE0_GET_TX_DESC_TRY_RATE(txdesc_ie)
+#define IE0_SET_TX_DESC_TRY_RATE_8814B(txdesc_ie, value) \
+ IE0_SET_TX_DESC_TRY_RATE(txdesc_ie, value)
+#define IE0_GET_TX_DESC_USERATE_8814B(txdesc_ie) \
+ IE0_GET_TX_DESC_USERATE(txdesc_ie)
+#define IE0_SET_TX_DESC_USERATE_8814B(txdesc_ie, value) \
+ IE0_SET_TX_DESC_USERATE(txdesc_ie, value)
+#define IE0_GET_TX_DESC_RTS_RTY_LOWEST_RATE_8814B(txdesc_ie) \
+ IE0_GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc_ie)
+#define IE0_SET_TX_DESC_RTS_RTY_LOWEST_RATE_8814B(txdesc_ie, value) \
+ IE0_SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc_ie, value)
+#define IE0_GET_TX_DESC_DATA_RTY_LOWEST_RATE_8814B(txdesc_ie) \
+ IE0_GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc_ie)
+#define IE0_SET_TX_DESC_DATA_RTY_LOWEST_RATE_8814B(txdesc_ie, value) \
+ IE0_SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc_ie, value)
+#define IE0_GET_TX_DESC_RTS_DATA_RTY_LMT_8814B(txdesc_ie) \
+ IE0_GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc_ie)
+#define IE0_SET_TX_DESC_RTS_DATA_RTY_LMT_8814B(txdesc_ie, value) \
+ IE0_SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc_ie, value)
+#define IE0_GET_TX_DESC_DATA_BW_8814B(txdesc_ie) \
+ IE0_GET_TX_DESC_DATA_BW(txdesc_ie)
+#define IE0_SET_TX_DESC_DATA_BW_8814B(txdesc_ie, value) \
+ IE0_SET_TX_DESC_DATA_BW(txdesc_ie, value)
+#define IE0_GET_TX_DESC_RTSRATE_8814B(txdesc_ie) \
+ IE0_GET_TX_DESC_RTSRATE(txdesc_ie)
+#define IE0_SET_TX_DESC_RTSRATE_8814B(txdesc_ie, value) \
+ IE0_SET_TX_DESC_RTSRATE(txdesc_ie, value)
+#define IE0_GET_TX_DESC_DATARATE_8814B(txdesc_ie) \
+ IE0_GET_TX_DESC_DATARATE(txdesc_ie)
+#define IE0_SET_TX_DESC_DATARATE_8814B(txdesc_ie, value) \
+ IE0_SET_TX_DESC_DATARATE(txdesc_ie, value)
+#define IE1_GET_TX_DESC_IE_END_8814B(txdesc_ie) \
+ IE1_GET_TX_DESC_IE_END(txdesc_ie)
+#define IE1_SET_TX_DESC_IE_END_8814B(txdesc_ie, value) \
+ IE1_SET_TX_DESC_IE_END(txdesc_ie, value)
+#define IE1_GET_TX_DESC_IE_UP_8814B(txdesc_ie) IE1_GET_TX_DESC_IE_UP(txdesc_ie)
+#define IE1_SET_TX_DESC_IE_UP_8814B(txdesc_ie, value) \
+ IE1_SET_TX_DESC_IE_UP(txdesc_ie, value)
+#define IE1_GET_TX_DESC_IE_NUM_8814B(txdesc_ie) \
+ IE1_GET_TX_DESC_IE_NUM(txdesc_ie)
+#define IE1_SET_TX_DESC_IE_NUM_8814B(txdesc_ie, value) \
+ IE1_SET_TX_DESC_IE_NUM(txdesc_ie, value)
+#define IE1_GET_TX_DESC_AMPDU_DENSITY_8814B(txdesc_ie) \
+ IE1_GET_TX_DESC_AMPDU_DENSITY(txdesc_ie)
+#define IE1_SET_TX_DESC_AMPDU_DENSITY_8814B(txdesc_ie, value) \
+ IE1_SET_TX_DESC_AMPDU_DENSITY(txdesc_ie, value)
+#define IE1_GET_TX_DESC_MAX_AGG_NUM_8814B(txdesc_ie) \
+ IE1_GET_TX_DESC_MAX_AGG_NUM(txdesc_ie)
+#define IE1_SET_TX_DESC_MAX_AGG_NUM_8814B(txdesc_ie, value) \
+ IE1_SET_TX_DESC_MAX_AGG_NUM(txdesc_ie, value)
+#define IE1_GET_TX_DESC_SECTYPE_8814B(txdesc_ie) \
+ IE1_GET_TX_DESC_SECTYPE(txdesc_ie)
+#define IE1_SET_TX_DESC_SECTYPE_8814B(txdesc_ie, value) \
+ IE1_SET_TX_DESC_SECTYPE(txdesc_ie, value)
+#define IE1_GET_TX_DESC_MOREFRAG_8814B(txdesc_ie) \
+ IE1_GET_TX_DESC_MOREFRAG(txdesc_ie)
+#define IE1_SET_TX_DESC_MOREFRAG_8814B(txdesc_ie, value) \
+ IE1_SET_TX_DESC_MOREFRAG(txdesc_ie, value)
+#define IE1_GET_TX_DESC_NOACM_8814B(txdesc_ie) IE1_GET_TX_DESC_NOACM(txdesc_ie)
+#define IE1_SET_TX_DESC_NOACM_8814B(txdesc_ie, value) \
+ IE1_SET_TX_DESC_NOACM(txdesc_ie, value)
+#define IE1_GET_TX_DESC_BCNPKT_TSF_CTRL_8814B(txdesc_ie) \
+ IE1_GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc_ie)
+#define IE1_SET_TX_DESC_BCNPKT_TSF_CTRL_8814B(txdesc_ie, value) \
+ IE1_SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc_ie, value)
+#define IE1_GET_TX_DESC_NAVUSEHDR_8814B(txdesc_ie) \
+ IE1_GET_TX_DESC_NAVUSEHDR(txdesc_ie)
+#define IE1_SET_TX_DESC_NAVUSEHDR_8814B(txdesc_ie, value) \
+ IE1_SET_TX_DESC_NAVUSEHDR(txdesc_ie, value)
+#define IE1_GET_TX_DESC_HTC_8814B(txdesc_ie) IE1_GET_TX_DESC_HTC(txdesc_ie)
+#define IE1_SET_TX_DESC_HTC_8814B(txdesc_ie, value) \
+ IE1_SET_TX_DESC_HTC(txdesc_ie, value)
+#define IE1_GET_TX_DESC_BMC_8814B(txdesc_ie) IE1_GET_TX_DESC_BMC(txdesc_ie)
+#define IE1_SET_TX_DESC_BMC_8814B(txdesc_ie, value) \
+ IE1_SET_TX_DESC_BMC(txdesc_ie, value)
+#define IE1_GET_TX_DESC_TX_PKT_AFTER_PIFS_8814B(txdesc_ie) \
+ IE1_GET_TX_DESC_TX_PKT_AFTER_PIFS(txdesc_ie)
+#define IE1_SET_TX_DESC_TX_PKT_AFTER_PIFS_8814B(txdesc_ie, value) \
+ IE1_SET_TX_DESC_TX_PKT_AFTER_PIFS(txdesc_ie, value)
+#define IE1_GET_TX_DESC_USE_MAX_TIME_EN_8814B(txdesc_ie) \
+ IE1_GET_TX_DESC_USE_MAX_TIME_EN(txdesc_ie)
+#define IE1_SET_TX_DESC_USE_MAX_TIME_EN_8814B(txdesc_ie, value) \
+ IE1_SET_TX_DESC_USE_MAX_TIME_EN(txdesc_ie, value)
+#define IE1_GET_TX_DESC_HW_SSN_SEL_8814B(txdesc_ie) \
+ IE1_GET_TX_DESC_HW_SSN_SEL(txdesc_ie)
+#define IE1_SET_TX_DESC_HW_SSN_SEL_8814B(txdesc_ie, value) \
+ IE1_SET_TX_DESC_HW_SSN_SEL(txdesc_ie, value)
+#define IE1_GET_TX_DESC_DISQSELSEQ_8814B(txdesc_ie) \
+ IE1_GET_TX_DESC_DISQSELSEQ(txdesc_ie)
+#define IE1_SET_TX_DESC_DISQSELSEQ_8814B(txdesc_ie, value) \
+ IE1_SET_TX_DESC_DISQSELSEQ(txdesc_ie, value)
+#define IE1_GET_TX_DESC_EN_HWSEQ_8814B(txdesc_ie) \
+ IE1_GET_TX_DESC_EN_HWSEQ(txdesc_ie)
+#define IE1_SET_TX_DESC_EN_HWSEQ_8814B(txdesc_ie, value) \
+ IE1_SET_TX_DESC_EN_HWSEQ(txdesc_ie, value)
+#define IE1_GET_TX_DESC_EN_HWEXSEQ_8814B(txdesc_ie) \
+ IE1_GET_TX_DESC_EN_HWEXSEQ(txdesc_ie)
+#define IE1_SET_TX_DESC_EN_HWEXSEQ_8814B(txdesc_ie, value) \
+ IE1_SET_TX_DESC_EN_HWEXSEQ(txdesc_ie, value)
+#define IE1_GET_TX_DESC_EN_DESC_ID_8814B(txdesc_ie) \
+ IE1_GET_TX_DESC_EN_DESC_ID(txdesc_ie)
+#define IE1_SET_TX_DESC_EN_DESC_ID_8814B(txdesc_ie, value) \
+ IE1_SET_TX_DESC_EN_DESC_ID(txdesc_ie, value)
+#define IE1_GET_TX_DESC_AMPDU_MAX_TIME_8814B(txdesc_ie) \
+ IE1_GET_TX_DESC_AMPDU_MAX_TIME(txdesc_ie)
+#define IE1_SET_TX_DESC_AMPDU_MAX_TIME_8814B(txdesc_ie, value) \
+ IE1_SET_TX_DESC_AMPDU_MAX_TIME(txdesc_ie, value)
+#define IE1_GET_TX_DESC_P_AID_8814B(txdesc_ie) IE1_GET_TX_DESC_P_AID(txdesc_ie)
+#define IE1_SET_TX_DESC_P_AID_8814B(txdesc_ie, value) \
+ IE1_SET_TX_DESC_P_AID(txdesc_ie, value)
+#define IE1_GET_TX_DESC_MOREDATA_8814B(txdesc_ie) \
+ IE1_GET_TX_DESC_MOREDATA(txdesc_ie)
+#define IE1_SET_TX_DESC_MOREDATA_8814B(txdesc_ie, value) \
+ IE1_SET_TX_DESC_MOREDATA(txdesc_ie, value)
+#define IE1_GET_TX_DESC_SW_SEQ_8814B(txdesc_ie) \
+ IE1_GET_TX_DESC_SW_SEQ(txdesc_ie)
+#define IE1_SET_TX_DESC_SW_SEQ_8814B(txdesc_ie, value) \
+ IE1_SET_TX_DESC_SW_SEQ(txdesc_ie, value)
+#define IE2_GET_TX_DESC_IE_END_8814B(txdesc_ie) \
+ IE2_GET_TX_DESC_IE_END(txdesc_ie)
+#define IE2_SET_TX_DESC_IE_END_8814B(txdesc_ie, value) \
+ IE2_SET_TX_DESC_IE_END(txdesc_ie, value)
+#define IE2_GET_TX_DESC_IE_UP_8814B(txdesc_ie) IE2_GET_TX_DESC_IE_UP(txdesc_ie)
+#define IE2_SET_TX_DESC_IE_UP_8814B(txdesc_ie, value) \
+ IE2_SET_TX_DESC_IE_UP(txdesc_ie, value)
+#define IE2_GET_TX_DESC_IE_NUM_8814B(txdesc_ie) \
+ IE2_GET_TX_DESC_IE_NUM(txdesc_ie)
+#define IE2_SET_TX_DESC_IE_NUM_8814B(txdesc_ie, value) \
+ IE2_SET_TX_DESC_IE_NUM(txdesc_ie, value)
+#define IE2_GET_TX_DESC_ADDR_CAM_8814B(txdesc_ie) \
+ IE2_GET_TX_DESC_ADDR_CAM(txdesc_ie)
+#define IE2_SET_TX_DESC_ADDR_CAM_8814B(txdesc_ie, value) \
+ IE2_SET_TX_DESC_ADDR_CAM(txdesc_ie, value)
+#define IE2_GET_TX_DESC_MULTIPLE_PORT_8814B(txdesc_ie) \
+ IE2_GET_TX_DESC_MULTIPLE_PORT(txdesc_ie)
+#define IE2_SET_TX_DESC_MULTIPLE_PORT_8814B(txdesc_ie, value) \
+ IE2_SET_TX_DESC_MULTIPLE_PORT(txdesc_ie, value)
+#define IE2_GET_TX_DESC_RAW_8814B(txdesc_ie) IE2_GET_TX_DESC_RAW(txdesc_ie)
+#define IE2_SET_TX_DESC_RAW_8814B(txdesc_ie, value) \
+ IE2_SET_TX_DESC_RAW(txdesc_ie, value)
+#define IE2_GET_TX_DESC_RDG_EN_8814B(txdesc_ie) \
+ IE2_GET_TX_DESC_RDG_EN(txdesc_ie)
+#define IE2_SET_TX_DESC_RDG_EN_8814B(txdesc_ie, value) \
+ IE2_SET_TX_DESC_RDG_EN(txdesc_ie, value)
+#define IE2_GET_TX_DESC_SPECIAL_CW_8814B(txdesc_ie) \
+ IE2_GET_TX_DESC_SPECIAL_CW(txdesc_ie)
+#define IE2_SET_TX_DESC_SPECIAL_CW_8814B(txdesc_ie, value) \
+ IE2_SET_TX_DESC_SPECIAL_CW(txdesc_ie, value)
+#define IE2_GET_TX_DESC_POLLUTED_8814B(txdesc_ie) \
+ IE2_GET_TX_DESC_POLLUTED(txdesc_ie)
+#define IE2_SET_TX_DESC_POLLUTED_8814B(txdesc_ie, value) \
+ IE2_SET_TX_DESC_POLLUTED(txdesc_ie, value)
+#define IE2_GET_TX_DESC_BT_NULL_8814B(txdesc_ie) \
+ IE2_GET_TX_DESC_BT_NULL(txdesc_ie)
+#define IE2_SET_TX_DESC_BT_NULL_8814B(txdesc_ie, value) \
+ IE2_SET_TX_DESC_BT_NULL(txdesc_ie, value)
+#define IE2_GET_TX_DESC_NULL_1_8814B(txdesc_ie) \
+ IE2_GET_TX_DESC_NULL_1(txdesc_ie)
+#define IE2_SET_TX_DESC_NULL_1_8814B(txdesc_ie, value) \
+ IE2_SET_TX_DESC_NULL_1(txdesc_ie, value)
+#define IE2_GET_TX_DESC_NULL_0_8814B(txdesc_ie) \
+ IE2_GET_TX_DESC_NULL_0(txdesc_ie)
+#define IE2_SET_TX_DESC_NULL_0_8814B(txdesc_ie, value) \
+ IE2_SET_TX_DESC_NULL_0(txdesc_ie, value)
+#define IE2_GET_TX_DESC_TRI_FRAME_8814B(txdesc_ie) \
+ IE2_GET_TX_DESC_TRI_FRAME(txdesc_ie)
+#define IE2_SET_TX_DESC_TRI_FRAME_8814B(txdesc_ie, value) \
+ IE2_SET_TX_DESC_TRI_FRAME(txdesc_ie, value)
+#define IE2_GET_TX_DESC_SPE_RPT_8814B(txdesc_ie) \
+ IE2_GET_TX_DESC_SPE_RPT(txdesc_ie)
+#define IE2_SET_TX_DESC_SPE_RPT_8814B(txdesc_ie, value) \
+ IE2_SET_TX_DESC_SPE_RPT(txdesc_ie, value)
+#define IE2_GET_TX_DESC_FTM_EN_8814B(txdesc_ie) \
+ IE2_GET_TX_DESC_FTM_EN(txdesc_ie)
+#define IE2_SET_TX_DESC_FTM_EN_8814B(txdesc_ie, value) \
+ IE2_SET_TX_DESC_FTM_EN(txdesc_ie, value)
+#define IE2_GET_TX_DESC_MBSSID_8814B(txdesc_ie) \
+ IE2_GET_TX_DESC_MBSSID(txdesc_ie)
+#define IE2_SET_TX_DESC_MBSSID_8814B(txdesc_ie, value) \
+ IE2_SET_TX_DESC_MBSSID(txdesc_ie, value)
+#define IE2_GET_TX_DESC_GROUP_BIT_IE_OFFSET_8814B(txdesc_ie) \
+ IE2_GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc_ie)
+#define IE2_SET_TX_DESC_GROUP_BIT_IE_OFFSET_8814B(txdesc_ie, value) \
+ IE2_SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc_ie, value)
+#define IE2_GET_TX_DESC_RDG_NAV_EXT_8814B(txdesc_ie) \
+ IE2_GET_TX_DESC_RDG_NAV_EXT(txdesc_ie)
+#define IE2_SET_TX_DESC_RDG_NAV_EXT_8814B(txdesc_ie, value) \
+ IE2_SET_TX_DESC_RDG_NAV_EXT(txdesc_ie, value)
+#define IE2_GET_TX_DESC_DROP_ID_8814B(txdesc_ie) \
+ IE2_GET_TX_DESC_DROP_ID(txdesc_ie)
+#define IE2_SET_TX_DESC_DROP_ID_8814B(txdesc_ie, value) \
+ IE2_SET_TX_DESC_DROP_ID(txdesc_ie, value)
+#define IE2_GET_TX_DESC_SW_DEFINE_8814B(txdesc_ie) \
+ IE2_GET_TX_DESC_SW_DEFINE(txdesc_ie)
+#define IE2_SET_TX_DESC_SW_DEFINE_8814B(txdesc_ie, value) \
+ IE2_SET_TX_DESC_SW_DEFINE(txdesc_ie, value)
+#define IE3_GET_TX_DESC_IE_END_8814B(txdesc_ie) \
+ IE3_GET_TX_DESC_IE_END(txdesc_ie)
+#define IE3_SET_TX_DESC_IE_END_8814B(txdesc_ie, value) \
+ IE3_SET_TX_DESC_IE_END(txdesc_ie, value)
+#define IE3_GET_TX_DESC_IE_UP_8814B(txdesc_ie) IE3_GET_TX_DESC_IE_UP(txdesc_ie)
+#define IE3_SET_TX_DESC_IE_UP_8814B(txdesc_ie, value) \
+ IE3_SET_TX_DESC_IE_UP(txdesc_ie, value)
+#define IE3_GET_TX_DESC_IE_NUM_8814B(txdesc_ie) \
+ IE3_GET_TX_DESC_IE_NUM(txdesc_ie)
+#define IE3_SET_TX_DESC_IE_NUM_8814B(txdesc_ie, value) \
+ IE3_SET_TX_DESC_IE_NUM(txdesc_ie, value)
+#define IE3_GET_TX_DESC_DATA_SC_8814B(txdesc_ie) \
+ IE3_GET_TX_DESC_DATA_SC(txdesc_ie)
+#define IE3_SET_TX_DESC_DATA_SC_8814B(txdesc_ie, value) \
+ IE3_SET_TX_DESC_DATA_SC(txdesc_ie, value)
+#define IE3_GET_TX_DESC_SIGNALING_TA_PKT_SC_8814B(txdesc_ie) \
+ IE3_GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc_ie)
+#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_SC_8814B(txdesc_ie, value) \
+ IE3_SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc_ie, value)
+#define IE3_GET_TX_DESC_CTRL_CNT_8814B(txdesc_ie) \
+ IE3_GET_TX_DESC_CTRL_CNT(txdesc_ie)
+#define IE3_SET_TX_DESC_CTRL_CNT_8814B(txdesc_ie, value) \
+ IE3_SET_TX_DESC_CTRL_CNT(txdesc_ie, value)
+#define IE3_GET_TX_DESC_CTRL_CNT_VALID_8814B(txdesc_ie) \
+ IE3_GET_TX_DESC_CTRL_CNT_VALID(txdesc_ie)
+#define IE3_SET_TX_DESC_CTRL_CNT_VALID_8814B(txdesc_ie, value) \
+ IE3_SET_TX_DESC_CTRL_CNT_VALID(txdesc_ie, value)
+#define IE3_GET_TX_DESC_SIGNALING_TA_PKT_EN_8814B(txdesc_ie) \
+ IE3_GET_TX_DESC_SIGNALING_TA_PKT_EN(txdesc_ie)
+#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_EN_8814B(txdesc_ie, value) \
+ IE3_SET_TX_DESC_SIGNALING_TA_PKT_EN(txdesc_ie, value)
+#define IE3_GET_TX_DESC_G_ID_8814B(txdesc_ie) IE3_GET_TX_DESC_G_ID(txdesc_ie)
+#define IE3_SET_TX_DESC_G_ID_8814B(txdesc_ie, value) \
+ IE3_SET_TX_DESC_G_ID(txdesc_ie, value)
+#define IE3_GET_TX_DESC_SND_TARGET_8814B(txdesc_ie) \
+ IE3_GET_TX_DESC_SND_TARGET(txdesc_ie)
+#define IE3_SET_TX_DESC_SND_TARGET_8814B(txdesc_ie, value) \
+ IE3_SET_TX_DESC_SND_TARGET(txdesc_ie, value)
+#define IE3_GET_TX_DESC_CCA_RTS_8814B(txdesc_ie) \
+ IE3_GET_TX_DESC_CCA_RTS(txdesc_ie)
+#define IE3_SET_TX_DESC_CCA_RTS_8814B(txdesc_ie, value) \
+ IE3_SET_TX_DESC_CCA_RTS(txdesc_ie, value)
+#define IE3_GET_TX_DESC_SND_PKT_SEL_8814B(txdesc_ie) \
+ IE3_GET_TX_DESC_SND_PKT_SEL(txdesc_ie)
+#define IE3_SET_TX_DESC_SND_PKT_SEL_8814B(txdesc_ie, value) \
+ IE3_SET_TX_DESC_SND_PKT_SEL(txdesc_ie, value)
+#define IE3_GET_TX_DESC_NDPA_8814B(txdesc_ie) IE3_GET_TX_DESC_NDPA(txdesc_ie)
+#define IE3_SET_TX_DESC_NDPA_8814B(txdesc_ie, value) \
+ IE3_SET_TX_DESC_NDPA(txdesc_ie, value)
+#define IE3_GET_TX_DESC_MU_DATARATE_8814B(txdesc_ie) \
+ IE3_GET_TX_DESC_MU_DATARATE(txdesc_ie)
+#define IE3_SET_TX_DESC_MU_DATARATE_8814B(txdesc_ie, value) \
+ IE3_SET_TX_DESC_MU_DATARATE(txdesc_ie, value)
+#define IE4_GET_TX_DESC_IE_END_8814B(txdesc_ie) \
+ IE4_GET_TX_DESC_IE_END(txdesc_ie)
+#define IE4_SET_TX_DESC_IE_END_8814B(txdesc_ie, value) \
+ IE4_SET_TX_DESC_IE_END(txdesc_ie, value)
+#define IE4_GET_TX_DESC_IE_UP_8814B(txdesc_ie) IE4_GET_TX_DESC_IE_UP(txdesc_ie)
+#define IE4_SET_TX_DESC_IE_UP_8814B(txdesc_ie, value) \
+ IE4_SET_TX_DESC_IE_UP(txdesc_ie, value)
+#define IE4_GET_TX_DESC_IE_NUM_8814B(txdesc_ie) \
+ IE4_GET_TX_DESC_IE_NUM(txdesc_ie)
+#define IE4_SET_TX_DESC_IE_NUM_8814B(txdesc_ie, value) \
+ IE4_SET_TX_DESC_IE_NUM(txdesc_ie, value)
+#define IE4_GET_TX_DESC_VCS_STBC_8814B(txdesc_ie) \
+ IE4_GET_TX_DESC_VCS_STBC(txdesc_ie)
+#define IE4_SET_TX_DESC_VCS_STBC_8814B(txdesc_ie, value) \
+ IE4_SET_TX_DESC_VCS_STBC(txdesc_ie, value)
+#define IE4_GET_TX_DESC_DATA_STBC_8814B(txdesc_ie) \
+ IE4_GET_TX_DESC_DATA_STBC(txdesc_ie)
+#define IE4_SET_TX_DESC_DATA_STBC_8814B(txdesc_ie, value) \
+ IE4_SET_TX_DESC_DATA_STBC(txdesc_ie, value)
+#define IE4_GET_TX_DESC_DATA_LDPC_8814B(txdesc_ie) \
+ IE4_GET_TX_DESC_DATA_LDPC(txdesc_ie)
+#define IE4_SET_TX_DESC_DATA_LDPC_8814B(txdesc_ie, value) \
+ IE4_SET_TX_DESC_DATA_LDPC(txdesc_ie, value)
+#define IE4_GET_TX_DESC_GF_8814B(txdesc_ie) IE4_GET_TX_DESC_GF(txdesc_ie)
+#define IE4_SET_TX_DESC_GF_8814B(txdesc_ie, value) \
+ IE4_SET_TX_DESC_GF(txdesc_ie, value)
+#define IE4_GET_TX_DESC_LSIG_TXOP_EN_8814B(txdesc_ie) \
+ IE4_GET_TX_DESC_LSIG_TXOP_EN(txdesc_ie)
+#define IE4_SET_TX_DESC_LSIG_TXOP_EN_8814B(txdesc_ie, value) \
+ IE4_SET_TX_DESC_LSIG_TXOP_EN(txdesc_ie, value)
+#define IE4_GET_TX_DESC_PATH_MAPA_8814B(txdesc_ie) \
+ IE4_GET_TX_DESC_PATH_MAPA(txdesc_ie)
+#define IE4_SET_TX_DESC_PATH_MAPA_8814B(txdesc_ie, value) \
+ IE4_SET_TX_DESC_PATH_MAPA(txdesc_ie, value)
+#define IE4_GET_TX_DESC_PATH_MAPB_8814B(txdesc_ie) \
+ IE4_GET_TX_DESC_PATH_MAPB(txdesc_ie)
+#define IE4_SET_TX_DESC_PATH_MAPB_8814B(txdesc_ie, value) \
+ IE4_SET_TX_DESC_PATH_MAPB(txdesc_ie, value)
+#define IE4_GET_TX_DESC_PATH_MAPC_8814B(txdesc_ie) \
+ IE4_GET_TX_DESC_PATH_MAPC(txdesc_ie)
+#define IE4_SET_TX_DESC_PATH_MAPC_8814B(txdesc_ie, value) \
+ IE4_SET_TX_DESC_PATH_MAPC(txdesc_ie, value)
+#define IE4_GET_TX_DESC_PATH_MAPD_8814B(txdesc_ie) \
+ IE4_GET_TX_DESC_PATH_MAPD(txdesc_ie)
+#define IE4_SET_TX_DESC_PATH_MAPD_8814B(txdesc_ie, value) \
+ IE4_SET_TX_DESC_PATH_MAPD(txdesc_ie, value)
+#define IE4_GET_TX_DESC_ANTSEL_A_8814B(txdesc_ie) \
+ IE4_GET_TX_DESC_ANTSEL_A(txdesc_ie)
+#define IE4_SET_TX_DESC_ANTSEL_A_8814B(txdesc_ie, value) \
+ IE4_SET_TX_DESC_ANTSEL_A(txdesc_ie, value)
+#define IE4_GET_TX_DESC_ANTSEL_B_8814B(txdesc_ie) \
+ IE4_GET_TX_DESC_ANTSEL_B(txdesc_ie)
+#define IE4_SET_TX_DESC_ANTSEL_B_8814B(txdesc_ie, value) \
+ IE4_SET_TX_DESC_ANTSEL_B(txdesc_ie, value)
+#define IE4_GET_TX_DESC_ANTSEL_C_8814B(txdesc_ie) \
+ IE4_GET_TX_DESC_ANTSEL_C(txdesc_ie)
+#define IE4_SET_TX_DESC_ANTSEL_C_8814B(txdesc_ie, value) \
+ IE4_SET_TX_DESC_ANTSEL_C(txdesc_ie, value)
+#define IE4_GET_TX_DESC_ANTSEL_D_8814B(txdesc_ie) \
+ IE4_GET_TX_DESC_ANTSEL_D(txdesc_ie)
+#define IE4_SET_TX_DESC_ANTSEL_D_8814B(txdesc_ie, value) \
+ IE4_SET_TX_DESC_ANTSEL_D(txdesc_ie, value)
+#define IE4_GET_TX_DESC_NTX_PATH_EN_8814B(txdesc_ie) \
+ IE4_GET_TX_DESC_NTX_PATH_EN(txdesc_ie)
+#define IE4_SET_TX_DESC_NTX_PATH_EN_8814B(txdesc_ie, value) \
+ IE4_SET_TX_DESC_NTX_PATH_EN(txdesc_ie, value)
+#define IE4_GET_TX_DESC_ANTLSEL_EN_8814B(txdesc_ie) \
+ IE4_GET_TX_DESC_ANTLSEL_EN(txdesc_ie)
+#define IE4_SET_TX_DESC_ANTLSEL_EN_8814B(txdesc_ie, value) \
+ IE4_SET_TX_DESC_ANTLSEL_EN(txdesc_ie, value)
+#define IE4_GET_TX_DESC_TXPWR_OFSET_TYPE_8814B(txdesc_ie) \
+ IE4_GET_TX_DESC_TXPWR_OFSET_TYPE(txdesc_ie)
+#define IE4_SET_TX_DESC_TXPWR_OFSET_TYPE_8814B(txdesc_ie, value) \
+ IE4_SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc_ie, value)
+#define IE5_GET_TX_DESC_IE_END_8814B(txdesc_ie) \
+ IE5_GET_TX_DESC_IE_END(txdesc_ie)
+#define IE5_SET_TX_DESC_IE_END_8814B(txdesc_ie, value) \
+ IE5_SET_TX_DESC_IE_END(txdesc_ie, value)
+#define IE5_GET_TX_DESC_IE_UP_8814B(txdesc_ie) IE5_GET_TX_DESC_IE_UP(txdesc_ie)
+#define IE5_SET_TX_DESC_IE_UP_8814B(txdesc_ie, value) \
+ IE5_SET_TX_DESC_IE_UP(txdesc_ie, value)
+#define IE5_GET_TX_DESC_IE_NUM_8814B(txdesc_ie) \
+ IE5_GET_TX_DESC_IE_NUM(txdesc_ie)
+#define IE5_SET_TX_DESC_IE_NUM_8814B(txdesc_ie, value) \
+ IE5_SET_TX_DESC_IE_NUM(txdesc_ie, value)
+#define IE5_GET_TX_DESC_LEN1_L_8814B(txdesc_ie) \
+ IE5_GET_TX_DESC_LEN1_L(txdesc_ie)
+#define IE5_SET_TX_DESC_LEN1_L_8814B(txdesc_ie, value) \
+ IE5_SET_TX_DESC_LEN1_L(txdesc_ie, value)
+#define IE5_GET_TX_DESC_LEN0_8814B(txdesc_ie) IE5_GET_TX_DESC_LEN0(txdesc_ie)
+#define IE5_SET_TX_DESC_LEN0_8814B(txdesc_ie, value) \
+ IE5_SET_TX_DESC_LEN0(txdesc_ie, value)
+#define IE5_GET_TX_DESC_PKT_NUM_8814B(txdesc_ie) \
+ IE5_GET_TX_DESC_PKT_NUM(txdesc_ie)
+#define IE5_SET_TX_DESC_PKT_NUM_8814B(txdesc_ie, value) \
+ IE5_SET_TX_DESC_PKT_NUM(txdesc_ie, value)
+#define IE5_GET_TX_DESC_LEN3_8814B(txdesc_ie) IE5_GET_TX_DESC_LEN3(txdesc_ie)
+#define IE5_SET_TX_DESC_LEN3_8814B(txdesc_ie, value) \
+ IE5_SET_TX_DESC_LEN3(txdesc_ie, value)
+#define IE5_GET_TX_DESC_LEN2_8814B(txdesc_ie) IE5_GET_TX_DESC_LEN2(txdesc_ie)
+#define IE5_SET_TX_DESC_LEN2_8814B(txdesc_ie, value) \
+ IE5_SET_TX_DESC_LEN2(txdesc_ie, value)
+#define IE5_GET_TX_DESC_LEN1_H_8814B(txdesc_ie) \
+ IE5_GET_TX_DESC_LEN1_H(txdesc_ie)
+#define IE5_SET_TX_DESC_LEN1_H_8814B(txdesc_ie, value) \
+ IE5_SET_TX_DESC_LEN1_H(txdesc_ie, value)
+
+#endif
+
+#endif
diff --git a/hal/halmac/halmac_tx_desc_ie_nic.h b/hal/halmac/halmac_tx_desc_ie_nic.h
new file mode 100644
index 0000000..c88f8fa
--- /dev/null
+++ b/hal/halmac/halmac_tx_desc_ie_nic.h
@@ -0,0 +1,450 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
+#ifndef _HALMAC_TX_DESC_IE_NIC_H_
+#define _HALMAC_TX_DESC_IE_NIC_H_
+#if (HALMAC_8814B_SUPPORT)
+
+#define IE0_GET_TX_DESC_IE_END(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 31, 1)
+#define IE0_SET_TX_DESC_IE_END(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 31, 1, value)
+#define IE0_GET_TX_DESC_IE_UP(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 30, 1)
+#define IE0_SET_TX_DESC_IE_UP(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 30, 1, value)
+#define IE0_GET_TX_DESC_IE_NUM(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 24, 4)
+#define IE0_SET_TX_DESC_IE_NUM(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 24, 4, value)
+#define IE0_GET_TX_DESC_ARFR_TABLE_SEL(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 19, 1)
+#define IE0_SET_TX_DESC_ARFR_TABLE_SEL(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 19, 1, value)
+#define IE0_GET_TX_DESC_ARFR_HT_EN(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 18, 1)
+#define IE0_SET_TX_DESC_ARFR_HT_EN(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 18, 1, value)
+#define IE0_GET_TX_DESC_ARFR_OFDM_EN(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 17, 1)
+#define IE0_SET_TX_DESC_ARFR_OFDM_EN(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 17, 1, value)
+#define IE0_GET_TX_DESC_ARFR_CCK_EN(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 16, 1)
+#define IE0_SET_TX_DESC_ARFR_CCK_EN(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 16, 1, value)
+#define IE0_GET_TX_DESC_HW_RTS_EN(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 9, 1)
+#define IE0_SET_TX_DESC_HW_RTS_EN(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 9, 1, value)
+#define IE0_GET_TX_DESC_RTS_EN(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 8, 1)
+#define IE0_SET_TX_DESC_RTS_EN(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 8, 1, value)
+#define IE0_GET_TX_DESC_CTS2SELF(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 7, 1)
+#define IE0_SET_TX_DESC_CTS2SELF(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 7, 1, value)
+#define IE0_GET_TX_DESC_RTY_LMT_EN(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 6, 1)
+#define IE0_SET_TX_DESC_RTY_LMT_EN(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 6, 1, value)
+#define IE0_GET_TX_DESC_RTS_SHORT(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 5, 1)
+#define IE0_SET_TX_DESC_RTS_SHORT(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 5, 1, value)
+#define IE0_GET_TX_DESC_DISDATAFB(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 4, 1)
+#define IE0_SET_TX_DESC_DISDATAFB(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 4, 1, value)
+#define IE0_GET_TX_DESC_DISRTSFB(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 3, 1)
+#define IE0_SET_TX_DESC_DISRTSFB(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 3, 1, value)
+#define IE0_GET_TX_DESC_DATA_SHORT(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 2, 1)
+#define IE0_SET_TX_DESC_DATA_SHORT(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 2, 1, value)
+#define IE0_GET_TX_DESC_TRY_RATE(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 1, 1)
+#define IE0_SET_TX_DESC_TRY_RATE(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 1, 1, value)
+#define IE0_GET_TX_DESC_USERATE(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 0, 1)
+#define IE0_SET_TX_DESC_USERATE(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 0, 1, value)
+#define IE0_GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 27, 4)
+#define IE0_SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 27, 4, value)
+#define IE0_GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 22, 5)
+#define IE0_SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 22, 5, value)
+#define IE0_GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 16, 6)
+#define IE0_SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 16, 6, value)
+#define IE0_GET_TX_DESC_DATA_BW(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 12, 2)
+#define IE0_SET_TX_DESC_DATA_BW(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 12, 2, value)
+#define IE0_GET_TX_DESC_RTSRATE(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 7, 4)
+#define IE0_SET_TX_DESC_RTSRATE(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 7, 4, value)
+#define IE0_GET_TX_DESC_DATARATE(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 0, 7)
+#define IE0_SET_TX_DESC_DATARATE(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 0, 7, value)
+#define IE1_GET_TX_DESC_IE_END(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 31, 1)
+#define IE1_SET_TX_DESC_IE_END(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 31, 1, value)
+#define IE1_GET_TX_DESC_IE_UP(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 30, 1)
+#define IE1_SET_TX_DESC_IE_UP(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 30, 1, value)
+#define IE1_GET_TX_DESC_IE_NUM(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 24, 4)
+#define IE1_SET_TX_DESC_IE_NUM(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 24, 4, value)
+#define IE1_GET_TX_DESC_AMPDU_DENSITY(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 21, 3)
+#define IE1_SET_TX_DESC_AMPDU_DENSITY(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 21, 3, value)
+#define IE1_GET_TX_DESC_MAX_AGG_NUM(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 16, 5)
+#define IE1_SET_TX_DESC_MAX_AGG_NUM(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 16, 5, value)
+#define IE1_GET_TX_DESC_SECTYPE(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 14, 2)
+#define IE1_SET_TX_DESC_SECTYPE(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 14, 2, value)
+#define IE1_GET_TX_DESC_MOREFRAG(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 13, 1)
+#define IE1_SET_TX_DESC_MOREFRAG(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 13, 1, value)
+#define IE1_GET_TX_DESC_NOACM(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 12, 1)
+#define IE1_SET_TX_DESC_NOACM(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 12, 1, value)
+#define IE1_GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 11, 1)
+#define IE1_SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 11, 1, value)
+#define IE1_GET_TX_DESC_NAVUSEHDR(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 10, 1)
+#define IE1_SET_TX_DESC_NAVUSEHDR(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 10, 1, value)
+#define IE1_GET_TX_DESC_HTC(txdesc_ie) LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 9, 1)
+#define IE1_SET_TX_DESC_HTC(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 9, 1, value)
+#define IE1_GET_TX_DESC_BMC(txdesc_ie) LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 8, 1)
+#define IE1_SET_TX_DESC_BMC(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 8, 1, value)
+#define IE1_GET_TX_DESC_TX_PKT_AFTER_PIFS(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 7, 1)
+#define IE1_SET_TX_DESC_TX_PKT_AFTER_PIFS(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 7, 1, value)
+#define IE1_GET_TX_DESC_USE_MAX_TIME_EN(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 6, 1)
+#define IE1_SET_TX_DESC_USE_MAX_TIME_EN(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 6, 1, value)
+#define IE1_GET_TX_DESC_HW_SSN_SEL(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 4, 2)
+#define IE1_SET_TX_DESC_HW_SSN_SEL(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 4, 2, value)
+#define IE1_GET_TX_DESC_DISQSELSEQ(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 3, 1)
+#define IE1_SET_TX_DESC_DISQSELSEQ(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 3, 1, value)
+#define IE1_GET_TX_DESC_EN_HWSEQ(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 2, 1)
+#define IE1_SET_TX_DESC_EN_HWSEQ(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 2, 1, value)
+#define IE1_GET_TX_DESC_EN_HWEXSEQ(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 1, 1)
+#define IE1_SET_TX_DESC_EN_HWEXSEQ(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 1, 1, value)
+#define IE1_GET_TX_DESC_EN_DESC_ID(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 0, 1)
+#define IE1_SET_TX_DESC_EN_DESC_ID(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 0, 1, value)
+#define IE1_GET_TX_DESC_AMPDU_MAX_TIME(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 24, 8)
+#define IE1_SET_TX_DESC_AMPDU_MAX_TIME(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 24, 8, value)
+#define IE1_GET_TX_DESC_P_AID(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 15, 9)
+#define IE1_SET_TX_DESC_P_AID(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 15, 9, value)
+#define IE1_GET_TX_DESC_MOREDATA(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 14, 1)
+#define IE1_SET_TX_DESC_MOREDATA(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 14, 1, value)
+#define IE1_GET_TX_DESC_SW_SEQ(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 0, 12)
+#define IE1_SET_TX_DESC_SW_SEQ(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 0, 12, value)
+#define IE2_GET_TX_DESC_IE_END(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 31, 1)
+#define IE2_SET_TX_DESC_IE_END(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 31, 1, value)
+#define IE2_GET_TX_DESC_IE_UP(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 30, 1)
+#define IE2_SET_TX_DESC_IE_UP(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 30, 1, value)
+#define IE2_GET_TX_DESC_IE_NUM(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 24, 4)
+#define IE2_SET_TX_DESC_IE_NUM(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 24, 4, value)
+#define IE2_GET_TX_DESC_ADDR_CAM(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 16, 8)
+#define IE2_SET_TX_DESC_ADDR_CAM(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 16, 8, value)
+#define IE2_GET_TX_DESC_MULTIPLE_PORT(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 12, 3)
+#define IE2_SET_TX_DESC_MULTIPLE_PORT(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 12, 3, value)
+#define IE2_GET_TX_DESC_RAW(txdesc_ie) LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 11, 1)
+#define IE2_SET_TX_DESC_RAW(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 11, 1, value)
+#define IE2_GET_TX_DESC_RDG_EN(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 10, 1)
+#define IE2_SET_TX_DESC_RDG_EN(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 10, 1, value)
+#define IE2_GET_TX_DESC_SPECIAL_CW(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 7, 1)
+#define IE2_SET_TX_DESC_SPECIAL_CW(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 7, 1, value)
+#define IE2_GET_TX_DESC_POLLUTED(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 6, 1)
+#define IE2_SET_TX_DESC_POLLUTED(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 6, 1, value)
+#define IE2_GET_TX_DESC_BT_NULL(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 5, 1)
+#define IE2_SET_TX_DESC_BT_NULL(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 5, 1, value)
+#define IE2_GET_TX_DESC_NULL_1(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 4, 1)
+#define IE2_SET_TX_DESC_NULL_1(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 4, 1, value)
+#define IE2_GET_TX_DESC_NULL_0(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 3, 1)
+#define IE2_SET_TX_DESC_NULL_0(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 3, 1, value)
+#define IE2_GET_TX_DESC_TRI_FRAME(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 2, 1)
+#define IE2_SET_TX_DESC_TRI_FRAME(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 2, 1, value)
+#define IE2_GET_TX_DESC_SPE_RPT(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 1, 1)
+#define IE2_SET_TX_DESC_SPE_RPT(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 1, 1, value)
+#define IE2_GET_TX_DESC_FTM_EN(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 0, 1)
+#define IE2_SET_TX_DESC_FTM_EN(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 0, 1, value)
+#define IE2_GET_TX_DESC_MBSSID(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 27, 4)
+#define IE2_SET_TX_DESC_MBSSID(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 27, 4, value)
+#define IE2_GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 16, 11)
+#define IE2_SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 16, 11, value)
+#define IE2_GET_TX_DESC_RDG_NAV_EXT(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 15, 1)
+#define IE2_SET_TX_DESC_RDG_NAV_EXT(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 15, 1, value)
+#define IE2_GET_TX_DESC_DROP_ID(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 12, 2)
+#define IE2_SET_TX_DESC_DROP_ID(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 12, 2, value)
+#define IE2_GET_TX_DESC_SW_DEFINE(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 0, 12)
+#define IE2_SET_TX_DESC_SW_DEFINE(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 0, 12, value)
+#define IE3_GET_TX_DESC_IE_END(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 31, 1)
+#define IE3_SET_TX_DESC_IE_END(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 31, 1, value)
+#define IE3_GET_TX_DESC_IE_UP(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 30, 1)
+#define IE3_SET_TX_DESC_IE_UP(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 30, 1, value)
+#define IE3_GET_TX_DESC_IE_NUM(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 24, 4)
+#define IE3_SET_TX_DESC_IE_NUM(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 24, 4, value)
+#define IE3_GET_TX_DESC_DATA_SC(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 20, 4)
+#define IE3_SET_TX_DESC_DATA_SC(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 20, 4, value)
+#define IE3_GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 16, 4)
+#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 16, 4, value)
+#define IE3_GET_TX_DESC_CTRL_CNT(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 8, 4)
+#define IE3_SET_TX_DESC_CTRL_CNT(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 8, 4, value)
+#define IE3_GET_TX_DESC_CTRL_CNT_VALID(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 1, 1)
+#define IE3_SET_TX_DESC_CTRL_CNT_VALID(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 1, 1, value)
+#define IE3_GET_TX_DESC_SIGNALING_TA_PKT_EN(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 0, 1)
+#define IE3_SET_TX_DESC_SIGNALING_TA_PKT_EN(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 0, 1, value)
+#define IE3_GET_TX_DESC_G_ID(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 24, 6)
+#define IE3_SET_TX_DESC_G_ID(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 24, 6, value)
+#define IE3_GET_TX_DESC_SND_TARGET(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 16, 8)
+#define IE3_SET_TX_DESC_SND_TARGET(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 16, 8, value)
+#define IE3_GET_TX_DESC_CCA_RTS(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 11, 2)
+#define IE3_SET_TX_DESC_CCA_RTS(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 11, 2, value)
+#define IE3_GET_TX_DESC_SND_PKT_SEL(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 9, 2)
+#define IE3_SET_TX_DESC_SND_PKT_SEL(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 9, 2, value)
+#define IE3_GET_TX_DESC_NDPA(txdesc_ie) LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 7, 2)
+#define IE3_SET_TX_DESC_NDPA(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 7, 2, value)
+#define IE3_GET_TX_DESC_MU_DATARATE(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 0, 7)
+#define IE3_SET_TX_DESC_MU_DATARATE(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 0, 7, value)
+#define IE4_GET_TX_DESC_IE_END(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 31, 1)
+#define IE4_SET_TX_DESC_IE_END(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 31, 1, value)
+#define IE4_GET_TX_DESC_IE_UP(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 30, 1)
+#define IE4_SET_TX_DESC_IE_UP(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 30, 1, value)
+#define IE4_GET_TX_DESC_IE_NUM(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 24, 4)
+#define IE4_SET_TX_DESC_IE_NUM(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 24, 4, value)
+#define IE4_GET_TX_DESC_VCS_STBC(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 10, 2)
+#define IE4_SET_TX_DESC_VCS_STBC(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 10, 2, value)
+#define IE4_GET_TX_DESC_DATA_STBC(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 8, 2)
+#define IE4_SET_TX_DESC_DATA_STBC(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 8, 2, value)
+#define IE4_GET_TX_DESC_DATA_LDPC(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 2, 1)
+#define IE4_SET_TX_DESC_DATA_LDPC(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 2, 1, value)
+#define IE4_GET_TX_DESC_GF(txdesc_ie) LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 1, 1)
+#define IE4_SET_TX_DESC_GF(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 1, 1, value)
+#define IE4_GET_TX_DESC_LSIG_TXOP_EN(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 0, 1)
+#define IE4_SET_TX_DESC_LSIG_TXOP_EN(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 0, 1, value)
+#define IE4_GET_TX_DESC_PATH_MAPA(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 30, 2)
+#define IE4_SET_TX_DESC_PATH_MAPA(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 30, 2, value)
+#define IE4_GET_TX_DESC_PATH_MAPB(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 28, 2)
+#define IE4_SET_TX_DESC_PATH_MAPB(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 28, 2, value)
+#define IE4_GET_TX_DESC_PATH_MAPC(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 26, 2)
+#define IE4_SET_TX_DESC_PATH_MAPC(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 26, 2, value)
+#define IE4_GET_TX_DESC_PATH_MAPD(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 24, 2)
+#define IE4_SET_TX_DESC_PATH_MAPD(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 24, 2, value)
+#define IE4_GET_TX_DESC_ANTSEL_A(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 20, 4)
+#define IE4_SET_TX_DESC_ANTSEL_A(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 20, 4, value)
+#define IE4_GET_TX_DESC_ANTSEL_B(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 16, 4)
+#define IE4_SET_TX_DESC_ANTSEL_B(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 16, 4, value)
+#define IE4_GET_TX_DESC_ANTSEL_C(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 12, 4)
+#define IE4_SET_TX_DESC_ANTSEL_C(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 12, 4, value)
+#define IE4_GET_TX_DESC_ANTSEL_D(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 8, 4)
+#define IE4_SET_TX_DESC_ANTSEL_D(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 8, 4, value)
+#define IE4_GET_TX_DESC_NTX_PATH_EN(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 4, 4)
+#define IE4_SET_TX_DESC_NTX_PATH_EN(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 4, 4, value)
+#define IE4_GET_TX_DESC_ANTLSEL_EN(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 3, 1)
+#define IE4_SET_TX_DESC_ANTLSEL_EN(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 3, 1, value)
+#define IE4_GET_TX_DESC_TXPWR_OFSET_TYPE(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 0, 2)
+#define IE4_SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 0, 2, value)
+#define IE5_GET_TX_DESC_IE_END(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 31, 1)
+#define IE5_SET_TX_DESC_IE_END(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 31, 1, value)
+#define IE5_GET_TX_DESC_IE_UP(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 30, 1)
+#define IE5_SET_TX_DESC_IE_UP(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 30, 1, value)
+#define IE5_GET_TX_DESC_IE_NUM(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 24, 4)
+#define IE5_SET_TX_DESC_IE_NUM(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 24, 4, value)
+#define IE5_GET_TX_DESC_LEN1_L(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 17, 7)
+#define IE5_SET_TX_DESC_LEN1_L(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 17, 7, value)
+#define IE5_GET_TX_DESC_LEN0(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 4, 13)
+#define IE5_SET_TX_DESC_LEN0(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 4, 13, value)
+#define IE5_GET_TX_DESC_PKT_NUM(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x00, 0, 4)
+#define IE5_SET_TX_DESC_PKT_NUM(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x00, 0, 4, value)
+#define IE5_GET_TX_DESC_LEN3(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 19, 13)
+#define IE5_SET_TX_DESC_LEN3(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 19, 13, value)
+#define IE5_GET_TX_DESC_LEN2(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 6, 13)
+#define IE5_SET_TX_DESC_LEN2(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 6, 13, value)
+#define IE5_GET_TX_DESC_LEN1_H(txdesc_ie) \
+ LE_BITS_TO_4BYTE(txdesc_ie + 0x04, 0, 6)
+#define IE5_SET_TX_DESC_LEN1_H(txdesc_ie, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc_ie + 0x04, 0, 6, value)
+
+#endif
+
+#endif
diff --git a/hal/halmac/halmac_tx_desc_nic.h b/hal/halmac/halmac_tx_desc_nic.h
index 94eefbe..59a614f 100644
--- a/hal/halmac/halmac_tx_desc_nic.h
+++ b/hal/halmac/halmac_tx_desc_nic.h
@@ -1,451 +1,951 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
#ifndef _HALMAC_TX_DESC_NIC_H_
#define _HALMAC_TX_DESC_NIC_H_
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
/*TXDESC_WORD0*/
-#define SET_TX_DESC_DISQSELSEQ(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 31, 1, __Value)
-#define GET_TX_DESC_DISQSELSEQ(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 31, 1)
+#define SET_TX_DESC_DISQSELSEQ(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 31, 1, value)
+#define GET_TX_DESC_DISQSELSEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 31, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_IE_END_BODY(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 31, 1, value)
+#define GET_TX_DESC_IE_END_BODY(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 31, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_GF(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 30, 1, value)
+#define GET_TX_DESC_GF(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 30, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_AGG_EN_V1(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 30, 1, value)
+#define GET_TX_DESC_AGG_EN_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 30, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_NO_ACM(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 29, 1, value)
+#define GET_TX_DESC_NO_ACM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 29, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_BK_V1(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 29, 1, value)
+#define GET_TX_DESC_BK_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 29, 1)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_BCNPKT_TSF_CTRL(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 28, 1, value)
+#define GET_TX_DESC_BCNPKT_TSF_CTRL(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x00, 28, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_AMSDU_PAD_EN(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 27, 1, value)
+#define GET_TX_DESC_AMSDU_PAD_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 27, 1)
+#define SET_TX_DESC_LS(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 26, 1, value)
+#define GET_TX_DESC_LS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 26, 1)
+#define SET_TX_DESC_HTC(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 25, 1, value)
+#define GET_TX_DESC_HTC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 25, 1)
+#define SET_TX_DESC_BMC(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 24, 1, value)
+#define GET_TX_DESC_BMC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 24, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_PKT_OFFSET_V1(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 24, 5, value)
+#define GET_TX_DESC_PKT_OFFSET_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 24, 5)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_OFFSET(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 16, 8, value)
+#define GET_TX_DESC_OFFSET(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 16, 8)
+#define SET_TX_DESC_TXPKTSIZE(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x00, 0, 16, value)
+#define GET_TX_DESC_TXPKTSIZE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x00, 0, 16)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+/*WORD1*/
+
+#define SET_TX_DESC_HW_AES_IV_V2(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 31, 1, value)
+#define GET_TX_DESC_HW_AES_IV_V2(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 31, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_AMSDU(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 30, 1, value)
+#define GET_TX_DESC_AMSDU(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 30, 1)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8198F_SUPPORT)
-#define SET_TX_DESC_GF(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 30, 1, __Value)
-#define GET_TX_DESC_GF(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 30, 1)
-#define SET_TX_DESC_NO_ACM(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 29, 1, __Value)
-#define GET_TX_DESC_NO_ACM(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 29, 1)
+#define SET_TX_DESC_FTM_EN_V1(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 30, 1, value)
+#define GET_TX_DESC_FTM_EN_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 30, 1)
#endif
-#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
-#define SET_TX_DESC_BCNPKT_TSF_CTRL(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 28, 1, __Value)
-#define GET_TX_DESC_BCNPKT_TSF_CTRL(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 28, 1)
+#define SET_TX_DESC_MOREDATA(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 29, 1, value)
+#define GET_TX_DESC_MOREDATA(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 29, 1)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8814B_SUPPORT)
-#define SET_TX_DESC_AMSDU_PAD_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 27, 1, __Value)
-#define GET_TX_DESC_AMSDU_PAD_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 27, 1)
+#define SET_TX_DESC_HW_AES_IV_V1(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 29, 1, value)
+#define GET_TX_DESC_HW_AES_IV_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 29, 1)
+#define SET_TX_DESC_MHR_CP(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 25, 1, value)
+#define GET_TX_DESC_MHR_CP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 25, 1)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_PKT_OFFSET(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 24, 5, value)
+#define GET_TX_DESC_PKT_OFFSET(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 24, 5)
-#define SET_TX_DESC_LS(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 26, 1, __Value)
-#define GET_TX_DESC_LS(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 26, 1)
-#define SET_TX_DESC_HTC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 25, 1, __Value)
-#define GET_TX_DESC_HTC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 25, 1)
-#define SET_TX_DESC_BMC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 24, 1, __Value)
-#define GET_TX_DESC_BMC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 24, 1)
-#define SET_TX_DESC_OFFSET(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 16, 8, __Value)
-#define GET_TX_DESC_OFFSET(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 16, 8)
-#define SET_TX_DESC_TXPKTSIZE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 0, 16, __Value)
-#define GET_TX_DESC_TXPKTSIZE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 0, 16)
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_SMH_EN_V1(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 24, 1, value)
+#define GET_TX_DESC_SMH_EN_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 24, 1)
+
+#endif
-/*TXDESC_WORD1*/
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
-#define SET_TX_DESC_MOREDATA(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 29, 1, __Value)
-#define GET_TX_DESC_MOREDATA(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 29, 1)
-#define SET_TX_DESC_PKT_OFFSET(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 24, 5, __Value)
-#define GET_TX_DESC_PKT_OFFSET(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 24, 5)
-#define SET_TX_DESC_SEC_TYPE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 22, 2, __Value)
-#define GET_TX_DESC_SEC_TYPE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 22, 2)
-#define SET_TX_DESC_EN_DESC_ID(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 21, 1, __Value)
-#define GET_TX_DESC_EN_DESC_ID(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 21, 1)
-#define SET_TX_DESC_RATE_ID(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 16, 5, __Value)
-#define GET_TX_DESC_RATE_ID(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 16, 5)
-#define SET_TX_DESC_PIFS(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 15, 1, __Value)
-#define GET_TX_DESC_PIFS(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 15, 1)
-#define SET_TX_DESC_LSIG_TXOP_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 14, 1, __Value)
-#define GET_TX_DESC_LSIG_TXOP_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 14, 1)
-#define SET_TX_DESC_RD_NAV_EXT(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 13, 1, __Value)
-#define GET_TX_DESC_RD_NAV_EXT(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 13, 1)
-#define SET_TX_DESC_QSEL(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 8, 5, __Value)
-#define GET_TX_DESC_QSEL(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 8, 5)
-#define SET_TX_DESC_MACID(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 0, 7, __Value)
-#define GET_TX_DESC_MACID(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 0, 7)
+#define SET_TX_DESC_SEC_TYPE(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 22, 2, value)
+#define GET_TX_DESC_SEC_TYPE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 22, 2)
+#define SET_TX_DESC_EN_DESC_ID(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 21, 1, value)
+#define GET_TX_DESC_EN_DESC_ID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 21, 1)
+#define SET_TX_DESC_RATE_ID(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 16, 5, value)
+#define GET_TX_DESC_RATE_ID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 16, 5)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8814B_SUPPORT)
+#define SET_TX_DESC_SMH_CAM(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 16, 8, value)
+#define GET_TX_DESC_SMH_CAM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 16, 8)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_PIFS(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 15, 1, value)
+#define GET_TX_DESC_PIFS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 15, 1)
+#define SET_TX_DESC_LSIG_TXOP_EN(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 14, 1, value)
+#define GET_TX_DESC_LSIG_TXOP_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 14, 1)
+#define SET_TX_DESC_RD_NAV_EXT(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 13, 1, value)
+#define GET_TX_DESC_RD_NAV_EXT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 13, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_EXT_EDCA(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 13, 1, value)
+#define GET_TX_DESC_EXT_EDCA(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 13, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8814B_SUPPORT || HALMAC_8198F_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_QSEL(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 8, 5, value)
+#define GET_TX_DESC_QSEL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 8, 5)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_SPECIAL_CW(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 7, 1, value)
+#define GET_TX_DESC_SPECIAL_CW(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 7, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_MACID(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 0, 7, value)
+#define GET_TX_DESC_MACID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 0, 7)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_MACID_V1(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x04, 0, 7, value)
+#define GET_TX_DESC_MACID_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x04, 0, 7)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
/*TXDESC_WORD2*/
-#define SET_TX_DESC_HW_AES_IV(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 31, 1, __Value)
-#define GET_TX_DESC_HW_AES_IV(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 31, 1)
+#define SET_TX_DESC_HW_AES_IV(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 31, 1, value)
+#define GET_TX_DESC_HW_AES_IV(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 31, 1)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_CHK_EN_V1(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 31, 1, value)
+#define GET_TX_DESC_CHK_EN_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 31, 1)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_FTM_EN(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 30, 1, value)
+#define GET_TX_DESC_FTM_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 30, 1)
+
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_ANTCEL_D_V1(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 28, 4, value)
+#define GET_TX_DESC_ANTCEL_D_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 28, 4)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_DMA_PRI(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 27, 1, value)
+#define GET_TX_DESC_DMA_PRI(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 27, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_G_ID(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 24, 6, value)
+#define GET_TX_DESC_G_ID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 24, 6)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_MAX_AMSDU_MODE(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 24, 3, value)
+#define GET_TX_DESC_MAX_AMSDU_MODE(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x08, 24, 3)
#endif
-#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8198F_SUPPORT)
-#define SET_TX_DESC_FTM_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 30, 1, __Value)
-#define GET_TX_DESC_FTM_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 30, 1)
+#define SET_TX_DESC_ANTSEL_C_V1(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 24, 4, value)
+#define GET_TX_DESC_ANTSEL_C_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 24, 4)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
-#define SET_TX_DESC_G_ID(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 24, 6, __Value)
-#define GET_TX_DESC_G_ID(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 24, 6)
-#define SET_TX_DESC_BT_NULL(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 23, 1, __Value)
-#define GET_TX_DESC_BT_NULL(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 23, 1)
-#define SET_TX_DESC_AMPDU_DENSITY(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 20, 3, __Value)
-#define GET_TX_DESC_AMPDU_DENSITY(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 20, 3)
-#define SET_TX_DESC_SPE_RPT(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 19, 1, __Value)
-#define GET_TX_DESC_SPE_RPT(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 19, 1)
-#define SET_TX_DESC_RAW(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 18, 1, __Value)
-#define GET_TX_DESC_RAW(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 18, 1)
-#define SET_TX_DESC_MOREFRAG(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 17, 1, __Value)
-#define GET_TX_DESC_MOREFRAG(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 17, 1)
-#define SET_TX_DESC_BK(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 16, 1, __Value)
-#define GET_TX_DESC_BK(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 16, 1)
-#define SET_TX_DESC_NULL_1(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 15, 1, __Value)
-#define GET_TX_DESC_NULL_1(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 15, 1)
-#define SET_TX_DESC_NULL_0(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 14, 1, __Value)
-#define GET_TX_DESC_NULL_0(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 14, 1)
-#define SET_TX_DESC_RDG_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 13, 1, __Value)
-#define GET_TX_DESC_RDG_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 13, 1)
-#define SET_TX_DESC_AGG_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 12, 1, __Value)
-#define GET_TX_DESC_AGG_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 12, 1)
-#define SET_TX_DESC_CCA_RTS(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 10, 2, __Value)
-#define GET_TX_DESC_CCA_RTS(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 10, 2)
+#define SET_TX_DESC_BT_NULL(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 23, 1, value)
+#define GET_TX_DESC_BT_NULL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 23, 1)
+#define SET_TX_DESC_AMPDU_DENSITY(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 20, 3, value)
+#define GET_TX_DESC_AMPDU_DENSITY(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 20, 3)
+#define SET_TX_DESC_SPE_RPT(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 19, 1, value)
+#define GET_TX_DESC_SPE_RPT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 19, 1)
+#define SET_TX_DESC_RAW(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 18, 1, value)
+#define GET_TX_DESC_RAW(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 18, 1)
+#define SET_TX_DESC_MOREFRAG(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 17, 1, value)
+#define GET_TX_DESC_MOREFRAG(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 17, 1)
+#define SET_TX_DESC_BK(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 16, 1, value)
+#define GET_TX_DESC_BK(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 16, 1)
#endif
-#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8814B_SUPPORT)
-#define SET_TX_DESC_TRI_FRAME(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 9, 1, __Value)
-#define GET_TX_DESC_TRI_FRAME(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 9, 1)
+#define SET_TX_DESC_DMA_TXAGG_NUM_V1(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 16, 8, value)
+#define GET_TX_DESC_DMA_TXAGG_NUM_V1(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x08, 16, 8)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
-#define SET_TX_DESC_P_AID(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 0, 9, __Value)
-#define GET_TX_DESC_P_AID(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 0, 9)
+#define SET_TX_DESC_NULL_1(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 15, 1, value)
+#define GET_TX_DESC_NULL_1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 15, 1)
+#define SET_TX_DESC_NULL_0(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 14, 1, value)
+#define GET_TX_DESC_NULL_0(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 14, 1)
+#define SET_TX_DESC_RDG_EN(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 13, 1, value)
+#define GET_TX_DESC_RDG_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 13, 1)
+#define SET_TX_DESC_AGG_EN(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 12, 1, value)
+#define GET_TX_DESC_AGG_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 12, 1)
+#define SET_TX_DESC_CCA_RTS(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 10, 2, value)
+#define GET_TX_DESC_CCA_RTS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 10, 2)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_TRI_FRAME(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 9, 1, value)
+#define GET_TX_DESC_TRI_FRAME(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 9, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_P_AID(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 0, 9, value)
+#define GET_TX_DESC_P_AID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x08, 0, 9)
+
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_TXDESC_CHECKSUM_V1(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x08, 0, 16, value)
+#define GET_TX_DESC_TXDESC_CHECKSUM_V1(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x08, 0, 16)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
/*TXDESC_WORD3*/
-#define SET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 24, 8, __Value)
-#define GET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 24, 8)
-#define SET_TX_DESC_NDPA(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 22, 2, __Value)
-#define GET_TX_DESC_NDPA(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 22, 2)
-#define SET_TX_DESC_MAX_AGG_NUM(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 17, 5, __Value)
-#define GET_TX_DESC_MAX_AGG_NUM(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 17, 5)
-#define SET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 16, 1, __Value)
-#define GET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 16, 1)
-#define SET_TX_DESC_NAVUSEHDR(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 15, 1, __Value)
-#define GET_TX_DESC_NAVUSEHDR(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 15, 1)
+#define SET_TX_DESC_AMPDU_MAX_TIME(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 24, 8, value)
+#define GET_TX_DESC_AMPDU_MAX_TIME(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x0C, 24, 8)
+#define SET_TX_DESC_NDPA(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 22, 2, value)
+#define GET_TX_DESC_NDPA(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 22, 2)
+#define SET_TX_DESC_MAX_AGG_NUM(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 17, 5, value)
+#define GET_TX_DESC_MAX_AGG_NUM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 17, 5)
+#define SET_TX_DESC_USE_MAX_TIME_EN(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 16, 1, value)
+#define GET_TX_DESC_USE_MAX_TIME_EN(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x0C, 16, 1)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8814B_SUPPORT)
-#define SET_TX_DESC_CHK_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 14, 1, __Value)
-#define GET_TX_DESC_CHK_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 14, 1)
+#define SET_TX_DESC_OFFLOAD_SIZE(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 16, 15, value)
+#define GET_TX_DESC_OFFLOAD_SIZE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 16, 15)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
-#define SET_TX_DESC_HW_RTS_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 13, 1, __Value)
-#define GET_TX_DESC_HW_RTS_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 13, 1)
-#define SET_TX_DESC_RTSEN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 12, 1, __Value)
-#define GET_TX_DESC_RTSEN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 12, 1)
-#define SET_TX_DESC_CTS2SELF(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 11, 1, __Value)
-#define GET_TX_DESC_CTS2SELF(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 11, 1)
-#define SET_TX_DESC_DISDATAFB(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 10, 1, __Value)
-#define GET_TX_DESC_DISDATAFB(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 10, 1)
-#define SET_TX_DESC_DISRTSFB(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 9, 1, __Value)
-#define GET_TX_DESC_DISRTSFB(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 9, 1)
-#define SET_TX_DESC_USE_RATE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 8, 1, __Value)
-#define GET_TX_DESC_USE_RATE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 8, 1)
-#define SET_TX_DESC_HW_SSN_SEL(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 6, 2, __Value)
-#define GET_TX_DESC_HW_SSN_SEL(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 6, 2)
+#define SET_TX_DESC_NAVUSEHDR(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 15, 1, value)
+#define GET_TX_DESC_NAVUSEHDR(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 15, 1)
+#define SET_TX_DESC_CHK_EN(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 14, 1, value)
+#define GET_TX_DESC_CHK_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 14, 1)
+#define SET_TX_DESC_HW_RTS_EN(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 13, 1, value)
+#define GET_TX_DESC_HW_RTS_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 13, 1)
+#define SET_TX_DESC_RTSEN(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 12, 1, value)
+#define GET_TX_DESC_RTSEN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 12, 1)
+#define SET_TX_DESC_CTS2SELF(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 11, 1, value)
+#define GET_TX_DESC_CTS2SELF(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 11, 1)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8814B_SUPPORT)
-#define SET_TX_DESC_WHEADER_LEN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 0, 5, __Value)
-#define GET_TX_DESC_WHEADER_LEN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 0, 5)
+#define SET_TX_DESC_CHANNEL_DMA(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 11, 5, value)
+#define GET_TX_DESC_CHANNEL_DMA(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 11, 5)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+#define SET_TX_DESC_DISDATAFB(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 10, 1, value)
+#define GET_TX_DESC_DISDATAFB(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 10, 1)
+#define SET_TX_DESC_DISRTSFB(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 9, 1, value)
+#define GET_TX_DESC_DISRTSFB(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 9, 1)
+#define SET_TX_DESC_USE_RATE(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 8, 1, value)
+#define GET_TX_DESC_USE_RATE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 8, 1)
+#define SET_TX_DESC_HW_SSN_SEL(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 6, 2, value)
+#define GET_TX_DESC_HW_SSN_SEL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 6, 2)
-/*TXDESC_WORD4*/
+#endif
+
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_IE_CNT(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 6, 3, value)
+#define GET_TX_DESC_IE_CNT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 6, 3)
+#define SET_TX_DESC_IE_CNT_EN(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 5, 1, value)
+#define GET_TX_DESC_IE_CNT_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 5, 1)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
-#define SET_TX_DESC_PCTS_MASK_IDX(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x10, 30, 2, __Value)
-#define GET_TX_DESC_PCTS_MASK_IDX(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x10, 30, 2)
-#define SET_TX_DESC_PCTS_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x10, 29, 1, __Value)
-#define GET_TX_DESC_PCTS_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x10, 29, 1)
-#define SET_TX_DESC_RTSRATE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x10, 24, 5, __Value)
-#define GET_TX_DESC_RTSRATE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x10, 24, 5)
-#define SET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x10, 18, 6, __Value)
-#define GET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x10, 18, 6)
-#define SET_TX_DESC_RTY_LMT_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x10, 17, 1, __Value)
-#define GET_TX_DESC_RTY_LMT_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x10, 17, 1)
-#define SET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x10, 13, 4, __Value)
-#define GET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x10, 13, 4)
-#define SET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x10, 8, 5, __Value)
-#define GET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x10, 8, 5)
-#define SET_TX_DESC_TRY_RATE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x10, 7, 1, __Value)
-#define GET_TX_DESC_TRY_RATE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x10, 7, 1)
-#define SET_TX_DESC_DATARATE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x10, 0, 7, __Value)
-#define GET_TX_DESC_DATARATE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x10, 0, 7)
+#define SET_TX_DESC_WHEADER_LEN(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 0, 5, value)
+#define GET_TX_DESC_WHEADER_LEN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 0, 5)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8814B_SUPPORT)
+
+#define SET_TX_DESC_WHEADER_LEN_V1(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x0C, 0, 5, value)
+#define GET_TX_DESC_WHEADER_LEN_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x0C, 0, 5)
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/*TXDESC_WORD4*/
+
+#define SET_TX_DESC_PCTS_MASK_IDX(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 30, 2, value)
+#define GET_TX_DESC_PCTS_MASK_IDX(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x10, 30, 2)
+#define SET_TX_DESC_PCTS_EN(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 29, 1, value)
+#define GET_TX_DESC_PCTS_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x10, 29, 1)
+#define SET_TX_DESC_RTSRATE(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 24, 5, value)
+#define GET_TX_DESC_RTSRATE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x10, 24, 5)
+#define SET_TX_DESC_RTS_DATA_RTY_LMT(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 18, 6, value)
+#define GET_TX_DESC_RTS_DATA_RTY_LMT(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x10, 18, 6)
+#define SET_TX_DESC_RTY_LMT_EN(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 17, 1, value)
+#define GET_TX_DESC_RTY_LMT_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x10, 17, 1)
+#define SET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 13, 4, value)
+#define GET_TX_DESC_RTS_RTY_LOWEST_RATE(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x10, 13, 4)
+#define SET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 8, 5, value)
+#define GET_TX_DESC_DATA_RTY_LOWEST_RATE(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x10, 8, 5)
+#define SET_TX_DESC_TRY_RATE(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 7, 1, value)
+#define GET_TX_DESC_TRY_RATE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x10, 7, 1)
+#define SET_TX_DESC_DATARATE(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x10, 0, 7, value)
+#define GET_TX_DESC_DATARATE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x10, 0, 7)
/*TXDESC_WORD5*/
-#define SET_TX_DESC_POLLUTED(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 31, 1, __Value)
-#define GET_TX_DESC_POLLUTED(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 31, 1)
+#define SET_TX_DESC_POLLUTED(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 31, 1, value)
+#define GET_TX_DESC_POLLUTED(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 31, 1)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8822C_SUPPORT)
-#define SET_TX_DESC_TXPWR_OFSET(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 28, 3, __Value)
-#define GET_TX_DESC_TXPWR_OFSET(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 28, 3)
-#define SET_TX_DESC_TX_ANT(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 24, 4, __Value)
-#define GET_TX_DESC_TX_ANT(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 24, 4)
-#define SET_TX_DESC_PORT_ID(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 21, 3, __Value)
-#define GET_TX_DESC_PORT_ID(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 21, 3)
+#define SET_TX_DESC_ANTSEL_EN_V1(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 30, 1, value)
+#define GET_TX_DESC_ANTSEL_EN_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 30, 1)
#endif
-#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT)
-#define SET_TX_DESC_MULTIPLE_PORT(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 18, 3, __Value)
-#define GET_TX_DESC_MULTIPLE_PORT(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 18, 3)
+#define SET_TX_DESC_TXPWR_OFSET(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 28, 3, value)
+#define GET_TX_DESC_TXPWR_OFSET(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 28, 3)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8822C_SUPPORT)
-#define SET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 17, 1, __Value)
-#define GET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 17, 1)
+#define SET_TX_DESC_TXPWR_OFSET_TYPE(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 28, 2, value)
+#define GET_TX_DESC_TXPWR_OFSET_TYPE(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x14, 28, 2)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define SET_TX_DESC_RTS_SC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 13, 4, __Value)
-#define GET_TX_DESC_RTS_SC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 13, 4)
-#define SET_TX_DESC_RTS_SHORT(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 12, 1, __Value)
-#define GET_TX_DESC_RTS_SHORT(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 12, 1)
+#define SET_TX_DESC_TX_ANT(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 24, 4, value)
+#define GET_TX_DESC_TX_ANT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 24, 4)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8198F_SUPPORT)
-#define SET_TX_DESC_VCS_STBC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 10, 2, __Value)
-#define GET_TX_DESC_VCS_STBC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 10, 2)
+#define SET_TX_DESC_DROP_ID(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 24, 2, value)
+#define GET_TX_DESC_DROP_ID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 24, 2)
#endif
-#if (HALMAC_8188F_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
-#define SET_TX_DESC_RTS_STBC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 10, 2, __Value)
-#define GET_TX_DESC_RTS_STBC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 10, 2)
+#define SET_TX_DESC_PORT_ID(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 21, 3, value)
+#define GET_TX_DESC_PORT_ID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 21, 3)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || \
+ HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
-#define SET_TX_DESC_DATA_STBC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 8, 2, __Value)
-#define GET_TX_DESC_DATA_STBC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 8, 2)
+#define SET_TX_DESC_MULTIPLE_PORT(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 18, 3, value)
+#define GET_TX_DESC_MULTIPLE_PORT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 18, 3)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
-#define SET_TX_DESC_DATA_LDPC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 7, 1, __Value)
-#define GET_TX_DESC_DATA_LDPC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 7, 1)
+#define SET_TX_DESC_SIGNALING_TAPKT_EN(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 17, 1, value)
+#define GET_TX_DESC_SIGNALING_TAPKT_EN(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x14, 17, 1)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8198F_SUPPORT)
-#define SET_TX_DESC_DATA_BW(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 5, 2, __Value)
-#define GET_TX_DESC_DATA_BW(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 5, 2)
-#define SET_TX_DESC_DATA_SHORT(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 4, 1, __Value)
-#define GET_TX_DESC_DATA_SHORT(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 4, 1)
-#define SET_TX_DESC_DATA_SC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 0, 4, __Value)
-#define GET_TX_DESC_DATA_SC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 0, 4)
+#define SET_TX_DESC_RTS_SC(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 13, 4, value)
+#define GET_TX_DESC_RTS_SC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 13, 4)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 13, 4, value)
+#define GET_TX_DESC_SIGNALING_TA_PKT_SC(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x14, 13, 4)
+
+#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_RTS_SHORT(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 12, 1, value)
+#define GET_TX_DESC_RTS_SHORT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 12, 1)
+#define SET_TX_DESC_VCS_STBC(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 10, 2, value)
+#define GET_TX_DESC_VCS_STBC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 10, 2)
+#define SET_TX_DESC_DATA_STBC(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 8, 2, value)
+#define GET_TX_DESC_DATA_STBC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 8, 2)
+#define SET_TX_DESC_DATA_LDPC(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 7, 1, value)
+#define GET_TX_DESC_DATA_LDPC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 7, 1)
+#define SET_TX_DESC_DATA_BW(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 5, 2, value)
+#define GET_TX_DESC_DATA_BW(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 5, 2)
+#define SET_TX_DESC_DATA_SHORT(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 4, 1, value)
+#define GET_TX_DESC_DATA_SHORT(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 4, 1)
+#define SET_TX_DESC_DATA_SC(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x14, 0, 4, value)
+#define GET_TX_DESC_DATA_SC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x14, 0, 4)
+
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
/*TXDESC_WORD6*/
-#define SET_TX_DESC_ANTSEL_D(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 30, 2, __Value)
-#define GET_TX_DESC_ANTSEL_D(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 30, 2)
-#define SET_TX_DESC_ANT_MAPD(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 28, 2, __Value)
-#define GET_TX_DESC_ANT_MAPD(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 28, 2)
-#define SET_TX_DESC_ANT_MAPC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 26, 2, __Value)
-#define GET_TX_DESC_ANT_MAPC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 26, 2)
-#define SET_TX_DESC_ANT_MAPB(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 24, 2, __Value)
-#define GET_TX_DESC_ANT_MAPB(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 24, 2)
-#define SET_TX_DESC_ANT_MAPA(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 22, 2, __Value)
-#define GET_TX_DESC_ANT_MAPA(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 22, 2)
-#define SET_TX_DESC_ANTSEL_C(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 20, 2, __Value)
-#define GET_TX_DESC_ANTSEL_C(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 20, 2)
-#define SET_TX_DESC_ANTSEL_B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 18, 2, __Value)
-#define GET_TX_DESC_ANTSEL_B(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 18, 2)
+#define SET_TX_DESC_ANTSEL_D(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 30, 2, value)
+#define GET_TX_DESC_ANTSEL_D(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 30, 2)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8198F_SUPPORT)
-#define SET_TX_DESC_ANTSEL_A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 16, 2, __Value)
-#define GET_TX_DESC_ANTSEL_A(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 16, 2)
-#define SET_TX_DESC_MBSSID(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 12, 4, __Value)
-#define GET_TX_DESC_MBSSID(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 12, 4)
-#define SET_TX_DESC_SW_DEFINE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 0, 12, __Value)
-#define GET_TX_DESC_SW_DEFINE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 0, 12)
+#define SET_TX_DESC_ANT_MAPD_V1(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 30, 2, value)
+#define GET_TX_DESC_ANT_MAPD_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 30, 2)
-/*TXDESC_WORD7*/
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define SET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x1C, 24, 8, __Value)
-#define GET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x1C, 24, 8)
+#define SET_TX_DESC_ANT_MAPD(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 28, 2, value)
+#define GET_TX_DESC_ANT_MAPD(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 28, 2)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8198F_SUPPORT)
-#define SET_TX_DESC_FINAL_DATA_RATE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x1C, 24, 8, __Value)
-#define GET_TX_DESC_FINAL_DATA_RATE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x1C, 24, 8)
-#define SET_TX_DESC_NTX_MAP(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x1C, 20, 4, __Value)
-#define GET_TX_DESC_NTX_MAP(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x1C, 20, 4)
+#define SET_TX_DESC_ANT_MAPC_V1(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 28, 2, value)
+#define GET_TX_DESC_ANT_MAPC_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 28, 2)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define SET_TX_DESC_TX_BUFF_SIZE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x1C, 0, 16, __Value)
-#define GET_TX_DESC_TX_BUFF_SIZE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x1C, 0, 16)
-#define SET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x1C, 0, 16, __Value)
-#define GET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x1C, 0, 16)
-#define SET_TX_DESC_TIMESTAMP(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x1C, 0, 16, __Value)
-#define GET_TX_DESC_TIMESTAMP(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x1C, 0, 16)
+#define SET_TX_DESC_ANT_MAPC(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 26, 2, value)
+#define GET_TX_DESC_ANT_MAPC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 26, 2)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8198F_SUPPORT)
+#define SET_TX_DESC_ANT_MAPB_V1(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 26, 2, value)
+#define GET_TX_DESC_ANT_MAPB_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 26, 2)
-/*TXDESC_WORD8*/
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define SET_TX_DESC_TXWIFI_CP(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 31, 1, __Value)
-#define GET_TX_DESC_TXWIFI_CP(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 31, 1)
-#define SET_TX_DESC_MAC_CP(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 30, 1, __Value)
-#define GET_TX_DESC_MAC_CP(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 30, 1)
-#define SET_TX_DESC_STW_PKTRE_DIS(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 29, 1, __Value)
-#define GET_TX_DESC_STW_PKTRE_DIS(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 29, 1)
-#define SET_TX_DESC_STW_RB_DIS(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 28, 1, __Value)
-#define GET_TX_DESC_STW_RB_DIS(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 28, 1)
-#define SET_TX_DESC_STW_RATE_DIS(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 27, 1, __Value)
-#define GET_TX_DESC_STW_RATE_DIS(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 27, 1)
-#define SET_TX_DESC_STW_ANT_DIS(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 26, 1, __Value)
-#define GET_TX_DESC_STW_ANT_DIS(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 26, 1)
-#define SET_TX_DESC_STW_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 25, 1, __Value)
-#define GET_TX_DESC_STW_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 25, 1)
-#define SET_TX_DESC_SMH_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 24, 1, __Value)
-#define GET_TX_DESC_SMH_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 24, 1)
+#define SET_TX_DESC_ANT_MAPB(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 24, 2, value)
+#define GET_TX_DESC_ANT_MAPB(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 24, 2)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8198F_SUPPORT)
-#define SET_TX_DESC_TAILPAGE_L(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 24, 8, __Value)
-#define GET_TX_DESC_TAILPAGE_L(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 24, 8)
+#define SET_TX_DESC_ANT_MAPA_V1(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 24, 2, value)
+#define GET_TX_DESC_ANT_MAPA_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 24, 2)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define SET_TX_DESC_SDIO_DMASEQ(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 16, 8, __Value)
-#define GET_TX_DESC_SDIO_DMASEQ(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 16, 8)
+#define SET_TX_DESC_ANT_MAPA(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 22, 2, value)
+#define GET_TX_DESC_ANT_MAPA(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 22, 2)
+#define SET_TX_DESC_ANTSEL_C(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 20, 2, value)
+#define GET_TX_DESC_ANTSEL_C(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 20, 2)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8198F_SUPPORT)
-#define SET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 16, 8, __Value)
-#define GET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 16, 8)
-#define SET_TX_DESC_EN_HWSEQ(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 15, 1, __Value)
-#define GET_TX_DESC_EN_HWSEQ(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 15, 1)
+#define SET_TX_DESC_ANTSEL_B_V1(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 20, 4, value)
+#define GET_TX_DESC_ANTSEL_B_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 20, 4)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define SET_TX_DESC_EN_HWEXSEQ(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 14, 1, __Value)
-#define GET_TX_DESC_EN_HWEXSEQ(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 14, 1)
+#define SET_TX_DESC_ANTSEL_B(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 18, 2, value)
+#define GET_TX_DESC_ANTSEL_B(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 18, 2)
+#define SET_TX_DESC_ANTSEL_A(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 16, 2, value)
+#define GET_TX_DESC_ANTSEL_A(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 16, 2)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8198F_SUPPORT)
-#define SET_TX_DESC_DATA_RC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 8, 6, __Value)
-#define GET_TX_DESC_DATA_RC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 8, 6)
-#define SET_TX_DESC_BAR_RTY_TH(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 6, 2, __Value)
-#define GET_TX_DESC_BAR_RTY_TH(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 6, 2)
-#define SET_TX_DESC_RTS_RC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 0, 6, __Value)
-#define GET_TX_DESC_RTS_RC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 0, 6)
+#define SET_TX_DESC_ANTSEL_A_V1(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 16, 4, value)
+#define GET_TX_DESC_ANTSEL_A_V1(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 16, 4)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+#define SET_TX_DESC_MBSSID(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 12, 4, value)
+#define GET_TX_DESC_MBSSID(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 12, 4)
-/*TXDESC_WORD9*/
+#endif
+
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
-#define SET_TX_DESC_TAILPAGE_H(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x24, 28, 4, __Value)
-#define GET_TX_DESC_TAILPAGE_H(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x24, 28, 4)
-#define SET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x24, 24, 4, __Value)
-#define GET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x24, 24, 4)
+#define SET_TX_DESC_SW_DEFINE(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 0, 12, value)
+#define GET_TX_DESC_SW_DEFINE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 0, 12)
#endif
-#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8188F_SUPPORT)
+#if (HALMAC_8198F_SUPPORT)
-#define SET_TX_DESC_SW_SEQ(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x24, 12, 12, __Value)
-#define GET_TX_DESC_SW_SEQ(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x24, 12, 12)
-#define SET_TX_DESC_TXBF_PATH(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x24, 11, 1, __Value)
-#define GET_TX_DESC_TXBF_PATH(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x24, 11, 1)
-#define SET_TX_DESC_PADDING_LEN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x24, 0, 11, __Value)
-#define GET_TX_DESC_PADDING_LEN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x24, 0, 11)
-#define SET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x24, 0, 8, __Value)
-#define GET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x24, 0, 8)
+#define SET_TX_DESC_SWPS_SEQ(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x18, 0, 12, value)
+#define GET_TX_DESC_SWPS_SEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x18, 0, 12)
#endif
-#if (HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || HALMAC_8821C_SUPPORT)
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+/*TXDESC_WORD7*/
-/*WORD10*/
+#define SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 24, 8, value)
+#define GET_TX_DESC_DMA_TXAGG_NUM(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 24, 8)
+#define SET_TX_DESC_FINAL_DATA_RATE(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 24, 8, value)
+#define GET_TX_DESC_FINAL_DATA_RATE(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x1C, 24, 8)
+#define SET_TX_DESC_NTX_MAP(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 20, 4, value)
+#define GET_TX_DESC_NTX_MAP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 20, 4)
-#define SET_TX_DESC_MU_DATARATE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x28, 8, 8, __Value)
-#define GET_TX_DESC_MU_DATARATE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x28, 8, 8)
-#define SET_TX_DESC_MU_RC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x28, 4, 4, __Value)
-#define GET_TX_DESC_MU_RC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x28, 4, 4)
-#define SET_TX_DESC_SND_PKT_SEL(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x28, 0, 2, __Value)
-#define GET_TX_DESC_SND_PKT_SEL(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x28, 0, 2)
+#endif
+
+#if (HALMAC_8198F_SUPPORT)
+
+#define SET_TX_DESC_ANTSEL_EN(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 19, 1, value)
+#define GET_TX_DESC_ANTSEL_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 19, 1)
+#define SET_TX_DESC_MBSSID_EX(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 16, 3, value)
+#define GET_TX_DESC_MBSSID_EX(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 16, 3)
#endif
+#if (HALMAC_8814A_SUPPORT || HALMAC_8822B_SUPPORT || HALMAC_8197F_SUPPORT || \
+ HALMAC_8821C_SUPPORT || HALMAC_8198F_SUPPORT || HALMAC_8822C_SUPPORT)
+
+#define SET_TX_DESC_TX_BUFF_SIZE(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 0, 16, value)
+#define GET_TX_DESC_TX_BUFF_SIZE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 0, 16)
+#define SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 0, 16, value)
+#define GET_TX_DESC_TXDESC_CHECKSUM(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x1C, 0, 16)
+#define SET_TX_DESC_TIMESTAMP(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x1C, 0, 16, value)
+#define GET_TX_DESC_TIMESTAMP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x1C, 0, 16)
+
+/*TXDESC_WORD8*/
+
+#define SET_TX_DESC_TXWIFI_CP(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 31, 1, value)
+#define GET_TX_DESC_TXWIFI_CP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 31, 1)
+#define SET_TX_DESC_MAC_CP(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 30, 1, value)
+#define GET_TX_DESC_MAC_CP(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 30, 1)
+#define SET_TX_DESC_STW_PKTRE_DIS(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 29, 1, value)
+#define GET_TX_DESC_STW_PKTRE_DIS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 29, 1)
+#define SET_TX_DESC_STW_RB_DIS(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 28, 1, value)
+#define GET_TX_DESC_STW_RB_DIS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 28, 1)
+#define SET_TX_DESC_STW_RATE_DIS(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 27, 1, value)
+#define GET_TX_DESC_STW_RATE_DIS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 27, 1)
+#define SET_TX_DESC_STW_ANT_DIS(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 26, 1, value)
+#define GET_TX_DESC_STW_ANT_DIS(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 26, 1)
+#define SET_TX_DESC_STW_EN(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 25, 1, value)
+#define GET_TX_DESC_STW_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 25, 1)
+#define SET_TX_DESC_SMH_EN(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 24, 1, value)
+#define GET_TX_DESC_SMH_EN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 24, 1)
+#define SET_TX_DESC_TAILPAGE_L(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 24, 8, value)
+#define GET_TX_DESC_TAILPAGE_L(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 24, 8)
+#define SET_TX_DESC_SDIO_DMASEQ(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 16, 8, value)
+#define GET_TX_DESC_SDIO_DMASEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 16, 8)
+#define SET_TX_DESC_NEXTHEADPAGE_L(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 16, 8, value)
+#define GET_TX_DESC_NEXTHEADPAGE_L(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x20, 16, 8)
+#define SET_TX_DESC_EN_HWSEQ(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 15, 1, value)
+#define GET_TX_DESC_EN_HWSEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 15, 1)
+#define SET_TX_DESC_EN_HWEXSEQ(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 14, 1, value)
+#define GET_TX_DESC_EN_HWEXSEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 14, 1)
+#define SET_TX_DESC_DATA_RC(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 8, 6, value)
+#define GET_TX_DESC_DATA_RC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 8, 6)
+#define SET_TX_DESC_BAR_RTY_TH(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 6, 2, value)
+#define GET_TX_DESC_BAR_RTY_TH(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 6, 2)
+#define SET_TX_DESC_RTS_RC(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x20, 0, 6, value)
+#define GET_TX_DESC_RTS_RC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x20, 0, 6)
+
+/*TXDESC_WORD9*/
+
+#define SET_TX_DESC_TAILPAGE_H(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 28, 4, value)
+#define GET_TX_DESC_TAILPAGE_H(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 28, 4)
+#define SET_TX_DESC_NEXTHEADPAGE_H(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 24, 4, value)
+#define GET_TX_DESC_NEXTHEADPAGE_H(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x24, 24, 4)
+#define SET_TX_DESC_SW_SEQ(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 12, 12, value)
+#define GET_TX_DESC_SW_SEQ(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 12, 12)
+#define SET_TX_DESC_TXBF_PATH(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 11, 1, value)
+#define GET_TX_DESC_TXBF_PATH(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 11, 1)
+#define SET_TX_DESC_PADDING_LEN(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 0, 11, value)
+#define GET_TX_DESC_PADDING_LEN(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x24, 0, 11)
+#define SET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x24, 0, 8, value)
+#define GET_TX_DESC_GROUP_BIT_IE_OFFSET(txdesc) \
+ LE_BITS_TO_4BYTE(txdesc + 0x24, 0, 8)
+
+#endif
+
+#if (HALMAC_8822B_SUPPORT || HALMAC_8821C_SUPPORT || HALMAC_8822C_SUPPORT)
+
+/*WORD10*/
+
+#define SET_TX_DESC_MU_DATARATE(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 8, 8, value)
+#define GET_TX_DESC_MU_DATARATE(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 8, 8)
+#define SET_TX_DESC_MU_RC(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 4, 4, value)
+#define GET_TX_DESC_MU_RC(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 4, 4)
+#define SET_TX_DESC_SND_PKT_SEL(txdesc, value) \
+ SET_BITS_TO_LE_4BYTE(txdesc + 0x28, 0, 2, value)
+#define GET_TX_DESC_SND_PKT_SEL(txdesc) LE_BITS_TO_4BYTE(txdesc + 0x28, 0, 2)
+
+#endif
#endif
diff --git a/hal/halmac/halmac_type.h b/hal/halmac/halmac_type.h
index f99adba..8bfa449 100644
--- a/hal/halmac/halmac_type.h
+++ b/hal/halmac/halmac_type.h
@@ -1,90 +1,204 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
#ifndef _HALMAC_TYPE_H_
#define _HALMAC_TYPE_H_
#include "halmac_2_platform.h"
#include "halmac_hw_cfg.h"
#include "halmac_fw_info.h"
-
+#include "halmac_intf_phy_cmd.h"
+#include "halmac_state_machine.h"
#define IN
#define OUT
#define INOUT
-#define VOID void
-
-#define HALMAC_SCAN_CH_NUM_MAX 28
-#define HALMAC_BCN_IE_BMP_SIZE 24 /* ID0~ID191, 192/8=24 */
-#define HALMAC_PHY_PARAMETER_SIZE 12
-#define HALMAC_PHY_PARAMETER_MAX_NUM 128
-#define HALMAC_MAX_SSID_LEN 32
-#define HALMAC_SUPPORT_NLO_NUM 16
-#define HALMAC_SUPPORT_PROBE_REQ_NUM 8
-#define HALMC_DDMA_POLLING_COUNT 1000
-#define API_ARRAY_SIZE 32
+
+#define HALMAC_BCN_IE_BMP_SIZE 24 /* ID0~ID191, 192/8=24 */
+
+#ifndef HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE
+#define HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE 80
+#endif
+
+#ifndef HALMAC_MSG_LEVEL_TRACE
+#define HALMAC_MSG_LEVEL_TRACE 3
+#endif
+
+#ifndef HALMAC_MSG_LEVEL_WARNING
+#define HALMAC_MSG_LEVEL_WARNING 2
+#endif
+
+#ifndef HALMAC_MSG_LEVEL_ERR
+#define HALMAC_MSG_LEVEL_ERR 1
+#endif
+
+#ifndef HALMAC_MSG_LEVEL_NO_LOG
+#define HALMAC_MSG_LEVEL_NO_LOG 0
+#endif
+
+#ifndef HALMAC_MSG_LEVEL
+#define HALMAC_MSG_LEVEL HALMAC_MSG_LEVEL_TRACE
+#endif
/* platform api */
-#define PLATFORM_SDIO_CMD52_READ pHalmac_adapter->pHalmac_platform_api->SDIO_CMD52_READ
-#define PLATFORM_SDIO_CMD53_READ_8 pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_READ_8
-#define PLATFORM_SDIO_CMD53_READ_16 pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_READ_16
-#define PLATFORM_SDIO_CMD53_READ_32 pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_READ_32
-#define PLATFORM_SDIO_CMD52_WRITE pHalmac_adapter->pHalmac_platform_api->SDIO_CMD52_WRITE
-#define PLATFORM_SDIO_CMD53_WRITE_8 pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_WRITE_8
-#define PLATFORM_SDIO_CMD53_WRITE_16 pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_WRITE_16
-#define PLATFORM_SDIO_CMD53_WRITE_32 pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_WRITE_32
-
-#define PLATFORM_REG_READ_8 pHalmac_adapter->pHalmac_platform_api->REG_READ_8
-#define PLATFORM_REG_READ_16 pHalmac_adapter->pHalmac_platform_api->REG_READ_16
-#define PLATFORM_REG_READ_32 pHalmac_adapter->pHalmac_platform_api->REG_READ_32
-#define PLATFORM_REG_WRITE_8 pHalmac_adapter->pHalmac_platform_api->REG_WRITE_8
-#define PLATFORM_REG_WRITE_16 pHalmac_adapter->pHalmac_platform_api->REG_WRITE_16
-#define PLATFORM_REG_WRITE_32 pHalmac_adapter->pHalmac_platform_api->REG_WRITE_32
-
-#define PLATFORM_SEND_RSVD_PAGE pHalmac_adapter->pHalmac_platform_api->SEND_RSVD_PAGE
-#define PLATFORM_SEND_H2C_PKT pHalmac_adapter->pHalmac_platform_api->SEND_H2C_PKT
-
-#define PLATFORM_RTL_FREE pHalmac_adapter->pHalmac_platform_api->RTL_FREE
-#define PLATFORM_RTL_MALLOC pHalmac_adapter->pHalmac_platform_api->RTL_MALLOC
-#define PLATFORM_RTL_MEMCPY pHalmac_adapter->pHalmac_platform_api->RTL_MEMCPY
-#define PLATFORM_RTL_MEMSET pHalmac_adapter->pHalmac_platform_api->RTL_MEMSET
-#define PLATFORM_RTL_DELAY_US pHalmac_adapter->pHalmac_platform_api->RTL_DELAY_US
-
-#define PLATFORM_MUTEX_INIT pHalmac_adapter->pHalmac_platform_api->MUTEX_INIT
-#define PLATFORM_MUTEX_DEINIT pHalmac_adapter->pHalmac_platform_api->MUTEX_DEINIT
-#define PLATFORM_MUTEX_LOCK pHalmac_adapter->pHalmac_platform_api->MUTEX_LOCK
-#define PLATFORM_MUTEX_UNLOCK pHalmac_adapter->pHalmac_platform_api->MUTEX_UNLOCK
-
-#define PLATFORM_EVENT_INDICATION pHalmac_adapter->pHalmac_platform_api->EVENT_INDICATION
+#define PLTFM_SDIO_CMD52_R(offset) \
+ adapter->pltfm_api->SDIO_CMD52_READ(adapter->drv_adapter, offset)
+#define PLTFM_SDIO_CMD53_R8(offset) \
+ adapter->pltfm_api->SDIO_CMD53_READ_8(adapter->drv_adapter, offset)
+#define PLTFM_SDIO_CMD53_R16(offset) \
+ adapter->pltfm_api->SDIO_CMD53_READ_16(adapter->drv_adapter, offset)
+#define PLTFM_SDIO_CMD53_R32(offset) \
+ adapter->pltfm_api->SDIO_CMD53_READ_32(adapter->drv_adapter, offset)
+#define PLTFM_SDIO_CMD53_RN(offset, size, data) \
+ adapter->pltfm_api->SDIO_CMD53_READ_N(adapter->drv_adapter, offset, \
+ size, data)
+#define PLTFM_SDIO_CMD52_W(offset, val) \
+ adapter->pltfm_api->SDIO_CMD52_WRITE(adapter->drv_adapter, offset, val)
+#define PLTFM_SDIO_CMD53_W8(offset, val) \
+ adapter->pltfm_api->SDIO_CMD53_WRITE_8(adapter->drv_adapter, offset, \
+ val)
+#define PLTFM_SDIO_CMD53_W16(offset, val) \
+ adapter->pltfm_api->SDIO_CMD53_WRITE_16(adapter->drv_adapter, offset, \
+ val)
+#define PLTFM_SDIO_CMD53_W32(offset, val) \
+ adapter->pltfm_api->SDIO_CMD53_WRITE_32(adapter->drv_adapter, offset, \
+ val)
+#define PLTFM_SDIO_CMD52_CIA_R(offset) \
+ adapter->pltfm_api->SDIO_CMD52_CIA_READ(adapter->drv_adapter, offset)
+
+#define PLTFM_REG_R8(offset) \
+ adapter->pltfm_api->REG_READ_8(adapter->drv_adapter, offset)
+#define PLTFM_REG_R16(offset) \
+ adapter->pltfm_api->REG_READ_16(adapter->drv_adapter, offset)
+#define PLTFM_REG_R32(offset) \
+ adapter->pltfm_api->REG_READ_32(adapter->drv_adapter, offset)
+#define PLTFM_REG_W8(offset, val) \
+ adapter->pltfm_api->REG_WRITE_8(adapter->drv_adapter, offset, val)
+#define PLTFM_REG_W16(offset, val) \
+ adapter->pltfm_api->REG_WRITE_16(adapter->drv_adapter, offset, val)
+#define PLTFM_REG_W32(offset, val) \
+ adapter->pltfm_api->REG_WRITE_32(adapter->drv_adapter, offset, val)
+
+#define PLTFM_SEND_RSVD_PAGE(buf, size) \
+ adapter->pltfm_api->SEND_RSVD_PAGE(adapter->drv_adapter, buf, size)
+#define PLTFM_SEND_H2C_PKT(buf, size) \
+ adapter->pltfm_api->SEND_H2C_PKT(adapter->drv_adapter, buf, size)
+
+#define PLTFM_FREE(buf, size) \
+ adapter->pltfm_api->RTL_FREE(adapter->drv_adapter, buf, size)
+#define PLTFM_MALLOC(size) \
+ adapter->pltfm_api->RTL_MALLOC(adapter->drv_adapter, size)
+#define PLTFM_MEMCPY(dest, src, size) \
+ adapter->pltfm_api->RTL_MEMCPY(adapter->drv_adapter, dest, src, size)
+#define PLTFM_MEMSET(addr, value, size) \
+ adapter->pltfm_api->RTL_MEMSET(adapter->drv_adapter, addr, value, size)
+#define PLTFM_DELAY_US(us) \
+ adapter->pltfm_api->RTL_DELAY_US(adapter->drv_adapter, us)
+
+#define PLTFM_MUTEX_INIT(mutex) \
+ adapter->pltfm_api->MUTEX_INIT(adapter->drv_adapter, mutex)
+#define PLTFM_MUTEX_DEINIT(mutex) \
+ adapter->pltfm_api->MUTEX_DEINIT(adapter->drv_adapter, mutex)
+#define PLTFM_MUTEX_LOCK(mutex) \
+ adapter->pltfm_api->MUTEX_LOCK(adapter->drv_adapter, mutex)
+#define PLTFM_MUTEX_UNLOCK(mutex) \
+ adapter->pltfm_api->MUTEX_UNLOCK(adapter->drv_adapter, mutex)
+
+#define PLTFM_EVENT_SIG(feature_id, proc_status, buf, size) \
+ adapter->pltfm_api->EVENT_INDICATION(adapter->drv_adapter, feature_id, \
+ proc_status, buf, size)
+
+#if HALMAC_PLATFORM_WINDOWS
+#define PLTFM_MSG_PRINT adapter->pltfm_api->MSG_PRINT
+#endif
+#define PLTFM_MSG_ALWAYS(...) \
+ adapter->pltfm_api->MSG_PRINT(adapter->drv_adapter, HALMAC_MSG_INIT, \
+ HALMAC_DBG_ALWAYS, __VA_ARGS__)
#if HALMAC_DBG_MSG_ENABLE
-#define PLATFORM_MSG_PRINT pHalmac_adapter->pHalmac_platform_api->MSG_PRINT
+
+/* Enable debug msg depends on HALMAC_MSG_LEVEL */
+#if (HALMAC_MSG_LEVEL >= HALMAC_MSG_LEVEL_ERR)
+#define PLTFM_MSG_ERR(...) \
+ adapter->pltfm_api->MSG_PRINT(adapter->drv_adapter, HALMAC_MSG_INIT, \
+ HALMAC_DBG_ERR, __VA_ARGS__)
#else
-#define PLATFORM_MSG_PRINT(pDriver_adapter, msg_type, msg_level, fmt, ...)
+#define PLTFM_MSG_ERR(...) do {} while (0)
#endif
-#if HALMAC_PLATFORM_TESTPROGRAM
-#define PLATFORM_WRITE_DATA_SDIO_ADDR pHalmac_adapter->pHalmac_platform_api->WRITE_DATA_SDIO_ADDR
-#define PLATFORM_WRITE_DATA_USB_BULKOUT_ID pHalmac_adapter->pHalmac_platform_api->WRITE_DATA_USB_BULKOUT_ID
-#define PLATFORM_WRITE_DATA_PCIE_QUEUE pHalmac_adapter->pHalmac_platform_api->WRITE_DATA_PCIE_QUEUE
-#define PLATFORM_READ_DATA pHalmac_adapter->pHalmac_platform_api->READ_DATA
+#if (HALMAC_MSG_LEVEL >= HALMAC_MSG_LEVEL_WARNING)
+#define PLTFM_MSG_WARN(...) \
+ adapter->pltfm_api->MSG_PRINT(adapter->drv_adapter, HALMAC_MSG_INIT, \
+ HALMAC_DBG_WARN, __VA_ARGS__)
+#else
+#define PLTFM_MSG_WARN(...) do {} while (0)
+#endif
+
+#if (HALMAC_MSG_LEVEL >= HALMAC_MSG_LEVEL_TRACE)
+#define PLTFM_MSG_TRACE(...) \
+ adapter->pltfm_api->MSG_PRINT(adapter->drv_adapter, HALMAC_MSG_INIT, \
+ HALMAC_DBG_TRACE, __VA_ARGS__)
+#else
+#define PLTFM_MSG_TRACE(...) do {} while (0)
+#endif
+
+#else
+
+/* Disable debug msg */
+#define PLTFM_MSG_ERR(...) do {} while (0)
+#define PLTFM_MSG_WARN(...) do {} while (0)
+#define PLTFM_MSG_TRACE(...) do {} while (0)
+
#endif
-#define HALMAC_REG_READ_8 pHalmac_api->halmac_reg_read_8
-#define HALMAC_REG_READ_16 pHalmac_api->halmac_reg_read_16
-#define HALMAC_REG_READ_32 pHalmac_api->halmac_reg_read_32
-#define HALMAC_REG_WRITE_8 pHalmac_api->halmac_reg_write_8
-#define HALMAC_REG_WRITE_16 pHalmac_api->halmac_reg_write_16
-#define HALMAC_REG_WRITE_32 pHalmac_api->halmac_reg_write_32
+#define HALMAC_REG_R8(offset) api->halmac_reg_read_8(adapter, offset)
+#define HALMAC_REG_R16(offset) api->halmac_reg_read_16(adapter, offset)
+#define HALMAC_REG_R32(offset) api->halmac_reg_read_32(adapter, offset)
+#define HALMAC_REG_W8(offset, val) api->halmac_reg_write_8(adapter, offset, val)
+#define HALMAC_REG_W16(offset, val) \
+ api->halmac_reg_write_16(adapter, offset, val)
+#define HALMAC_REG_W32(offset, val) \
+ api->halmac_reg_write_32(adapter, offset, val)
+#define HALMAC_REG_SDIO_RN(offset, size, data) \
+ api->halmac_reg_sdio_cmd53_read_n(adapter, offset, size, data)
+
+#define HALMAC_REG_W8_CLR(offset, mask) \
+ HALMAC_REG_W8(offset, HALMAC_REG_R8(offset) & ~(mask))
+#define HALMAC_REG_W16_CLR(offset, mask) \
+ HALMAC_REG_W16(offset, HALMAC_REG_R16(offset) & ~(mask))
+#define HALMAC_REG_W32_CLR(offset, mask) \
+ HALMAC_REG_W32(offset, HALMAC_REG_R32(offset) & ~(mask))
+
+#define HALMAC_REG_W8_SET(offset, mask) \
+ HALMAC_REG_W8(offset, HALMAC_REG_R8(offset) | (mask))
+#define HALMAC_REG_W16_SET(offset, mask) \
+ HALMAC_REG_W16(offset, HALMAC_REG_R16(offset) | (mask))
+#define HALMAC_REG_W32_SET(offset, mask) \
+ HALMAC_REG_W32(offset, HALMAC_REG_R32(offset) | (mask))
/* Swap Little-endian <-> Big-endia*/
-#define SWAP32(x) ((u32)( \
- (((u32)(x) & (u32)0x000000ff) << 24) | \
- (((u32)(x) & (u32)0x0000ff00) << 8) | \
- (((u32)(x) & (u32)0x00ff0000) >> 8) | \
- (((u32)(x) & (u32)0xff000000) >> 24)))
+#define SWAP32(x) \
+ ((u32)((((u32)(x) & (u32)0x000000ff) << 24) | \
+ (((u32)(x) & (u32)0x0000ff00) << 8) | \
+ (((u32)(x) & (u32)0x00ff0000) >> 8) | \
+ (((u32)(x) & (u32)0xff000000) >> 24)))
-#define SWAP16(x) ((u16)( \
- (((u16)(x) & (u16)0x00ff) << 8) | \
- (((u16)(x) & (u16)0xff00) >> 8)))
+#define SWAP16(x) \
+ ((u16)((((u16)(x) & (u16)0x00ff) << 8) | \
+ (((u16)(x) & (u16)0xff00) >> 8)))
/*1->Little endian 0->Big endian*/
#if HALMAC_SYSTEM_ENDIAN
@@ -118,16 +232,16 @@
#if !((HALMAC_PLATFORM_WINDOWS == 1) && (HALMAC_PLATFORM_TESTPROGRAM == 0))
/* Byte Swapping routine */
-#ifndef EF1Byte
-#define EF1Byte (u8)
+#ifndef EF1BYTE
+#define EF1BYTE (u8)
#endif
-#ifndef EF2Byte
-#define EF2Byte rtk_le16_to_cpu
+#ifndef EF2BYTE
+#define EF2BYTE rtk_le16_to_cpu
#endif
-#ifndef EF4Byte
-#define EF4Byte rtk_le32_to_cpu
+#ifndef EF4BYTE
+#define EF4BYTE rtk_le32_to_cpu
#endif
/* Example:
@@ -137,8 +251,7 @@
* BIT_LEN_MASK_32(32) => 0xFFFFFFFF
*/
#ifndef BIT_LEN_MASK_32
-#define BIT_LEN_MASK_32(__BitLen) \
- (0xFFFFFFFF >> (32 - (__BitLen)))
+#define BIT_LEN_MASK_32(__bitlen) (0xFFFFFFFF >> (32 - (__bitlen)))
#endif
/* Example:
@@ -146,29 +259,24 @@
* BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
*/
#ifndef BIT_OFFSET_LEN_MASK_32
-#define BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) \
- (BIT_LEN_MASK_32(__BitLen) << (__BitOffset))
+#define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
+ (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
#endif
/* Return 4-byte value in host byte ordering from
* 4-byte pointer in litten-endian system
*/
#ifndef LE_P4BYTE_TO_HOST_4BYTE
-#define LE_P4BYTE_TO_HOST_4BYTE(__pStart) \
- (EF4Byte(*((u32 *)(__pStart))))
+#define LE_P4BYTE_TO_HOST_4BYTE(__start) (EF4BYTE(*((u32 *)(__start))))
#endif
-
/* Translate subfield (continuous bits in little-endian) of
* 4-byte value in litten byte to 4-byte value in host byte ordering
*/
#ifndef LE_BITS_TO_4BYTE
-#define LE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
- ( \
- (LE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset)) \
- & \
- BIT_LEN_MASK_32(__BitLen) \
- )
+#define LE_BITS_TO_4BYTE(__start, __bitoffset, __bitlen) \
+ ((LE_P4BYTE_TO_HOST_4BYTE(__start) >> (__bitoffset)) & \
+ BIT_LEN_MASK_32(__bitlen))
#endif
/* Mask subfield (continuous bits in little-endian) of 4-byte
@@ -176,50 +284,47 @@
* value in host byte ordering
*/
#ifndef LE_BITS_CLEARED_TO_4BYTE
-#define LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
- ( \
- LE_P4BYTE_TO_HOST_4BYTE(__pStart) \
- & \
- (~BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen)) \
- )
+#define LE_BITS_CLEARED_TO_4BYTE(__start, __bitoffset, __bitlen) \
+ (LE_P4BYTE_TO_HOST_4BYTE(__start) & \
+ (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)))
#endif
/* Set subfield of little-endian 4-byte value to specified value */
#ifndef SET_BITS_TO_LE_4BYTE
-#define SET_BITS_TO_LE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \
- do { \
- *((u32 *)(__pStart)) = \
- EF4Byte( \
- LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
- | \
- ((((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset)) \
- ); \
+#define SET_BITS_TO_LE_4BYTE(__start, __bitoffset, __bitlen, __value) \
+ do { \
+ *((u32 *)(__start)) = \
+ EF4BYTE( \
+ LE_BITS_CLEARED_TO_4BYTE(__start, __bitoffset, __bitlen) | \
+ ((((u32)__value) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset))\
+ ); \
} while (0)
#endif
#ifndef HALMAC_BIT_OFFSET_VAL_MASK_32
-#define HALMAC_BIT_OFFSET_VAL_MASK_32(__BitVal, __BitOffset) \
- (__BitVal << (__BitOffset))
+#define HALMAC_BIT_OFFSET_VAL_MASK_32(__bitval, __bitoffset) \
+ (__bitval << (__bitoffset))
#endif
#ifndef SET_MEM_OP
-#define SET_MEM_OP(Dw, Value32, Mask, Shift) \
- (((Dw) & ~((Mask) << (Shift))) | (((Value32) & (Mask)) << (Shift)))
+#define SET_MEM_OP(dw, value32, mask, shift) \
+ (((dw) & ~((mask) << (shift))) | (((value32) & (mask)) << (shift)))
#endif
#ifndef HALMAC_SET_DESC_FIELD_CLR
-#define HALMAC_SET_DESC_FIELD_CLR(Dw, Value32, Mask, Shift) \
- (Dw = (rtk_cpu_to_le32(SET_MEM_OP(rtk_cpu_to_le32(Dw), Value32, Mask, Shift))))
+#define HALMAC_SET_DESC_FIELD_CLR(dw, value32, mask, shift) \
+ (dw = (rtk_cpu_to_le32( \
+ SET_MEM_OP(rtk_cpu_to_le32(dw), value32, mask, shift))))
#endif
#ifndef HALMAC_SET_DESC_FIELD_NO_CLR
-#define HALMAC_SET_DESC_FIELD_NO_CLR(Dw, Value32, Mask, Shift) \
- (Dw |= (rtk_cpu_to_le32(((Value32) & (Mask)) << (Shift))))
+#define HALMAC_SET_DESC_FIELD_NO_CLR(dw, value32, mask, shift) \
+ (dw |= (rtk_cpu_to_le32(((value32) & (mask)) << (shift))))
#endif
#ifndef HALMAC_GET_DESC_FIELD
-#define HALMAC_GET_DESC_FIELD(Dw, Mask, Shift) \
- ((rtk_le32_to_cpu(Dw) >> (Shift)) & (Mask))
+#define HALMAC_GET_DESC_FIELD(dw, mask, shift) \
+ ((rtk_le32_to_cpu(dw) >> (shift)) & (mask))
#endif
#define HALMAC_SET_BD_FIELD_CLR HALMAC_SET_DESC_FIELD_CLR
@@ -256,10 +361,15 @@
#define BIT(x) (1 << (x))
#endif
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
+#endif
+
/* HALMAC API return status*/
-typedef enum _HALMAC_RET_STATUS {
+enum halmac_ret_status {
HALMAC_RET_SUCCESS = 0x00,
- HALMAC_RET_SUCCESS_ENQUEUE = 0x01,
+ HALMAC_RET_NOT_SUPPORT = 0x01,
+ HALMAC_RET_SUCCESS_ENQUEUE = 0x01, /*Don't use this return code!!*/
HALMAC_RET_PLATFORM_API_NULL = 0x02,
HALMAC_RET_EFUSE_SIZE_INCORRECT = 0x03,
HALMAC_RET_MALLOC_FAIL = 0x04,
@@ -267,7 +377,7 @@ typedef enum _HALMAC_RET_STATUS {
HALMAC_RET_ITF_INCORRECT = 0x06,
HALMAC_RET_DLFW_FAIL = 0x07,
HALMAC_RET_PORT_NOT_SUPPORT = 0x08,
- HALMAC_RET_TRXMODE_NOT_SUPPORT = 0x09,
+ HALMAC_RET_TXAGG_OVERFLOW = 0x09,
HALMAC_RET_INIT_LLT_FAIL = 0x0A,
HALMAC_RET_POWER_STATE_INVALID = 0x0B,
HALMAC_RET_H2C_ACK_NOT_RECEIVED = 0x0C,
@@ -333,7 +443,6 @@ typedef enum _HALMAC_RET_STATUS {
HALMAC_RET_EEPROM_PARSING_FAIL = 0x48,
HALMAC_RET_EFUSE_NOT_ENOUGH = 0x49,
HALMAC_RET_WRONG_ARGUMENT = 0x4A,
- HALMAC_RET_NOT_SUPPORT = 0x4B,
HALMAC_RET_C2H_NOT_HANDLED = 0x4C,
HALMAC_RET_PARA_SENDING = 0x4D,
HALMAC_RET_CFG_DLFW_SIZE_FAIL = 0x4E,
@@ -344,56 +453,44 @@ typedef enum _HALMAC_RET_STATUS {
HALMAC_RET_USB_MODE_UNCHANGE = 0x53,
HALMAC_RET_NO_DLFW = 0x54,
HALMAC_RET_USB2_3_SWITCH_UNSUPPORT = 0x55,
-} HALMAC_RET_STATUS;
-
-typedef enum _HALMAC_MAC_CLOCK_HW_DEF {
- HALMAC_MAC_CLOCK_HW_DEF_80M = 0,
- HALMAC_MAC_CLOCK_HW_DEF_40M = 1,
- HALMAC_MAC_CLOCK_HW_DEF_20M = 2,
-} HALMAC_MAC_CLOCK_HW_DEF;
-
-/* Rx aggregation parameters */
-typedef enum _HALMAC_NORMAL_RXAGG_TH_TO {
- HALMAC_NORMAL_RXAGG_THRESHOLD = 0xFF,
- HALMAC_NORMAL_RXAGG_TIMEOUT = 0x01,
-} HALMAC_NORMAL_RXAGG_TH_TO;
-
-typedef enum _HALMAC_LOOPBACK_RXAGG_TH_TO {
- HALMAC_LOOPBACK_RXAGG_THRESHOLD = 0xFF,
- HALMAC_LOOPBACK_RXAGG_TIMEOUT = 0x01,
-} HALMAC_LOOPBACK_RXAGG_TH_TO;
-
-/* Chip ID*/
-typedef enum _HALMAC_CHIP_ID {
+ HALMAC_RET_BIP_NO_SUPPORT = 0x56,
+ HALMAC_RET_ENTRY_INDEX_ERROR = 0x57,
+ HALMAC_RET_ENTRY_KEY_ID_ERROR = 0x58,
+ HALMAC_RET_DRV_DL_ERR = 0x59,
+ HALMAC_RET_OQT_NOT_ENOUGH = 0x5A,
+ HALMAC_RET_PWR_UNCHANGE = 0x5B,
+ HALMAC_RET_WRONG_INTF = 0x5C,
+ HALMAC_RET_POLLING_HIOE_REQ_FAIL = 0x5E,
+ HALMAC_RET_HIOE_CHKSUM_FAIL = 0x5F,
+ HALMAC_RET_HIOE_ERR = 0x60,
+ HALMAC_RET_FW_NO_SUPPORT = 0x60,
+ HALMAC_RET_TXFIFO_NO_EMPTY = 0x61,
+ HALMAC_RET_SDIO_CLOCK_ERR = 0x62,
+ HALMAC_RET_GET_PINMUX_ERR = 0x63,
+ HALMAC_RET_PINMUX_USED = 0x64,
+ HALMAC_RET_WRONG_GPIO = 0x65,
+ HALMAC_RET_LTECOEX_READY_FAIL = 0x66,
+ HALMAC_RET_IDMEM_CHKSUM_FAIL = 0x67,
+ HALMAC_RET_ILLEGAL_KEY_FAIL = 0x68,
+ HALMAC_RET_FW_READY_CHK_FAIL = 0x69,
+ HALMAC_RET_RSVD_PG_OVERFLOW_FAIL = 0x70,
+ HALMAC_RET_THRESHOLD_FAIL = 0x71,
+ HALMAC_RET_SDIO_MIX_MODE = 0x72,
+ HALMAC_RET_TXDESC_SET_FAIL = 0x73,
+ HALMAC_RET_WLHDR_FAIL = 0x74,
+ HALMAC_RET_WLAN_MODE_FAIL = 0x75,
+};
+
+enum halmac_chip_id {
HALMAC_CHIP_ID_8822B = 0,
HALMAC_CHIP_ID_8821C = 1,
- HALMAC_CHIP_ID_8824B = 2,
+ HALMAC_CHIP_ID_8814B = 2,
HALMAC_CHIP_ID_8197F = 3,
+ HALMAC_CHIP_ID_8822C = 4,
HALMAC_CHIP_ID_UNDEFINE = 0x7F,
-} HALMAC_CHIP_ID;
-
-typedef enum _HALMAC_CHIP_ID_HW_DEF {
- HALMAC_CHIP_ID_HW_DEF_8723A = 0x01,
- HALMAC_CHIP_ID_HW_DEF_8188E = 0x02,
- HALMAC_CHIP_ID_HW_DEF_8881A = 0x03,
- HALMAC_CHIP_ID_HW_DEF_8812A = 0x04,
- HALMAC_CHIP_ID_HW_DEF_8821A = 0x05,
- HALMAC_CHIP_ID_HW_DEF_8723B = 0x06,
- HALMAC_CHIP_ID_HW_DEF_8192E = 0x07,
- HALMAC_CHIP_ID_HW_DEF_8814A = 0x08,
- HALMAC_CHIP_ID_HW_DEF_8821C = 0x09,
- HALMAC_CHIP_ID_HW_DEF_8822B = 0x0A,
- HALMAC_CHIP_ID_HW_DEF_8703B = 0x0B,
- HALMAC_CHIP_ID_HW_DEF_8188F = 0x0C,
- HALMAC_CHIP_ID_HW_DEF_8192F = 0x0D,
- HALMAC_CHIP_ID_HW_DEF_8197F = 0x0E,
- HALMAC_CHIP_ID_HW_DEF_8723D = 0x0F,
- HALMAC_CHIP_ID_HW_DEF_UNDEFINE = 0x7F,
- HALMAC_CHIP_ID_HW_DEF_PS = 0xEA,
-} HALMAC_CHIP_ID_HW_DEF;
-
-/* Chip Version*/
-typedef enum _HALMAC_CHIP_VER {
+};
+
+enum halmac_chip_ver {
HALMAC_CHIP_VER_A_CUT = 0x00,
HALMAC_CHIP_VER_B_CUT = 0x01,
HALMAC_CHIP_VER_C_CUT = 0x02,
@@ -402,36 +499,45 @@ typedef enum _HALMAC_CHIP_VER {
HALMAC_CHIP_VER_F_CUT = 0x05,
HALMAC_CHIP_VER_TEST = 0xFF,
HALMAC_CHIP_VER_UNDEFINE = 0x7FFF,
-} HALMAC_CHIP_VER;
+};
-/* Network type select */
-typedef enum _HALMAC_NETWORK_TYPE_SELECT {
+enum halmac_network_type_select {
HALMAC_NETWORK_NO_LINK = 0,
HALMAC_NETWORK_ADHOC = 1,
HALMAC_NETWORK_INFRASTRUCTURE = 2,
HALMAC_NETWORK_AP = 3,
HALMAC_NETWORK_UNDEFINE = 0x7F,
-} HALMAC_NETWORK_TYPE_SELECT;
+};
-/* Transfer mode select */
-typedef enum _HALMAC_TRNSFER_MODE_SELECT {
+enum halmac_transfer_mode_select {
HALMAC_TRNSFER_NORMAL = 0x0,
HALMAC_TRNSFER_LOOPBACK_DIRECT = 0xB,
HALMAC_TRNSFER_LOOPBACK_DELAY = 0x3,
HALMAC_TRNSFER_UNDEFINE = 0x7F,
-} HALMAC_TRNSFER_MODE_SELECT;
+};
-/* Queue select */
-typedef enum _HALMAC_DMA_MAPPING {
+enum halmac_dma_mapping {
HALMAC_DMA_MAPPING_EXTRA = 0,
HALMAC_DMA_MAPPING_LOW = 1,
HALMAC_DMA_MAPPING_NORMAL = 2,
HALMAC_DMA_MAPPING_HIGH = 3,
HALMAC_DMA_MAPPING_UNDEFINE = 0x7F,
-} HALMAC_DMA_MAPPING;
-
-/* TXDESC queue select TID */
-typedef enum _HALMAC_TXDESC_QUEUE_TID {
+};
+
+enum halmac_io_size {
+ HALMAC_IO_BYTE = 0x0,
+ HALMAC_IO_WORD = 0x1,
+ HALMAC_IO_DWORD = 0x2,
+ HALMAC_IO_UNDEFINE = 0x7F,
+};
+
+#define HALMAC_MAP2_HQ HALMAC_DMA_MAPPING_HIGH
+#define HALMAC_MAP2_NQ HALMAC_DMA_MAPPING_NORMAL
+#define HALMAC_MAP2_LQ HALMAC_DMA_MAPPING_LOW
+#define HALMAC_MAP2_EXQ HALMAC_DMA_MAPPING_EXTRA
+#define HALMAC_MAP2_UNDEF HALMAC_DMA_MAPPING_UNDEFINE
+
+enum halmac_txdesc_queue_tid {
HALMAC_TXDESC_QSEL_TID0 = 0,
HALMAC_TXDESC_QSEL_TID1 = 1,
HALMAC_TXDESC_QSEL_TID2 = 2,
@@ -453,105 +559,163 @@ typedef enum _HALMAC_TXDESC_QUEUE_TID {
HALMAC_TXDESC_QSEL_HIGH = 0x11,
HALMAC_TXDESC_QSEL_MGT = 0x12,
HALMAC_TXDESC_QSEL_H2C_CMD = 0x13,
+ HALMAC_TXDESC_QSEL_FWCMD = 0x14,
HALMAC_TXDESC_QSEL_UNDEFINE = 0x7F,
-} HALMAC_TXDESC_QUEUE_TID;
-
-typedef enum _HALMAC_PTCL_QUEUE {
- HALMAC_PTCL_QUEUE_VO = 0x0,
- HALMAC_PTCL_QUEUE_VI = 0x1,
- HALMAC_PTCL_QUEUE_BE = 0x2,
- HALMAC_PTCL_QUEUE_BK = 0x3,
- HALMAC_PTCL_QUEUE_MG = 0x4,
- HALMAC_PTCL_QUEUE_HI = 0x5,
- HALMAC_PTCL_QUEUE_NUM = 0x6,
- HALMAC_PTCL_QUEUE_UNDEFINE = 0x7F,
-} HALMAC_PTCL_QUEUE;
-
-typedef enum {
- HALMAC_QUEUE_SELECT_VO = HALMAC_TXDESC_QSEL_TID6,
- HALMAC_QUEUE_SELECT_VI = HALMAC_TXDESC_QSEL_TID4,
- HALMAC_QUEUE_SELECT_BE = HALMAC_TXDESC_QSEL_TID0,
- HALMAC_QUEUE_SELECT_BK = HALMAC_TXDESC_QSEL_TID1,
- HALMAC_QUEUE_SELECT_VO_V2 = HALMAC_TXDESC_QSEL_TID7,
- HALMAC_QUEUE_SELECT_VI_V2 = HALMAC_TXDESC_QSEL_TID5,
- HALMAC_QUEUE_SELECT_BE_V2 = HALMAC_TXDESC_QSEL_TID3,
- HALMAC_QUEUE_SELECT_BK_V2 = HALMAC_TXDESC_QSEL_TID2,
- HALMAC_QUEUE_SELECT_BCN = HALMAC_TXDESC_QSEL_BEACON,
- HALMAC_QUEUE_SELECT_HIGH = HALMAC_TXDESC_QSEL_HIGH,
- HALMAC_QUEUE_SELECT_MGNT = HALMAC_TXDESC_QSEL_MGT,
- HALMAC_QUEUE_SELECT_CMD = HALMAC_TXDESC_QSEL_H2C_CMD,
- HALMAC_QUEUE_SELECT_UNDEFINE = 0x7F,
-} HALMAC_QUEUE_SELECT;
-
-
-/* USB burst size */
-typedef enum _HALMAC_USB_BURST_SIZE {
- HALMAC_USB_BURST_SIZE_3_0 = 0x0,
- HALMAC_USB_BURST_SIZE_2_0_HSPEED = 0x1,
- HALMAC_USB_BURST_SIZE_2_0_FSPEED = 0x2,
- HALMAC_USB_BURST_SIZE_2_0_OTHERS = 0x3,
- HALMAC_USB_BURST_SIZE_UNDEFINE = 0x7F,
-} HALMAC_USB_BURST_SIZE;
-
-/* HAL API function parameters*/
-typedef enum _HALMAC_INTERFACE {
+};
+
+enum halmac_pq_map_id {
+ HALMAC_PQ_MAP_VO = 0x0,
+ HALMAC_PQ_MAP_VI = 0x1,
+ HALMAC_PQ_MAP_BE = 0x2,
+ HALMAC_PQ_MAP_BK = 0x3,
+ HALMAC_PQ_MAP_MG = 0x4,
+ HALMAC_PQ_MAP_HI = 0x5,
+ HALMAC_PQ_MAP_NUM = 0x6,
+ HALMAC_PQ_MAP_UNDEF = 0x7F,
+};
+
+enum halmac_qsel {
+ HALMAC_QSEL_VO = HALMAC_TXDESC_QSEL_TID6,
+ HALMAC_QSEL_VI = HALMAC_TXDESC_QSEL_TID4,
+ HALMAC_QSEL_BE = HALMAC_TXDESC_QSEL_TID0,
+ HALMAC_QSEL_BK = HALMAC_TXDESC_QSEL_TID1,
+ HALMAC_QSEL_VO_V2 = HALMAC_TXDESC_QSEL_TID7,
+ HALMAC_QSEL_VI_V2 = HALMAC_TXDESC_QSEL_TID5,
+ HALMAC_QSEL_BE_V2 = HALMAC_TXDESC_QSEL_TID3,
+ HALMAC_QSEL_BK_V2 = HALMAC_TXDESC_QSEL_TID2,
+ HALMAC_QSEL_TID8 = HALMAC_TXDESC_QSEL_TID8,
+ HALMAC_QSEL_TID9 = HALMAC_TXDESC_QSEL_TID9,
+ HALMAC_QSEL_TIDA = HALMAC_TXDESC_QSEL_TIDA,
+ HALMAC_QSEL_TIDB = HALMAC_TXDESC_QSEL_TIDB,
+ HALMAC_QSEL_TIDC = HALMAC_TXDESC_QSEL_TIDC,
+ HALMAC_QSEL_TIDD = HALMAC_TXDESC_QSEL_TIDD,
+ HALMAC_QSEL_TIDE = HALMAC_TXDESC_QSEL_TIDE,
+ HALMAC_QSEL_TIDF = HALMAC_TXDESC_QSEL_TIDF,
+ HALMAC_QSEL_BCN = HALMAC_TXDESC_QSEL_BEACON,
+ HALMAC_QSEL_HIGH = HALMAC_TXDESC_QSEL_HIGH,
+ HALMAC_QSEL_MGNT = HALMAC_TXDESC_QSEL_MGT,
+ HALMAC_QSEL_CMD = HALMAC_TXDESC_QSEL_H2C_CMD,
+ HALMAC_QSEL_FWCMD = HALMAC_TXDESC_QSEL_FWCMD,
+ HALMAC_QSEL_UNDEFINE = 0x7F,
+};
+
+enum halmac_acq_id {
+ HALMAC_ACQ_ID_VO = 0,
+ HALMAC_ACQ_ID_VI = 1,
+ HALMAC_ACQ_ID_BE = 2,
+ HALMAC_ACQ_ID_BK = 3,
+ HALMAC_ACQ_ID_MAX = 0x7F,
+};
+
+enum halmac_txdesc_dma_ch {
+ HALMAC_TXDESC_DMA_CH0 = 0,
+ HALMAC_TXDESC_DMA_CH1 = 1,
+ HALMAC_TXDESC_DMA_CH2 = 2,
+ HALMAC_TXDESC_DMA_CH3 = 3,
+ HALMAC_TXDESC_DMA_CH4 = 4,
+ HALMAC_TXDESC_DMA_CH5 = 5,
+ HALMAC_TXDESC_DMA_CH6 = 6,
+ HALMAC_TXDESC_DMA_CH7 = 7,
+ HALMAC_TXDESC_DMA_CH8 = 8,
+ HALMAC_TXDESC_DMA_CH9 = 9,
+ HALMAC_TXDESC_DMA_CH10 = 10,
+ HALMAC_TXDESC_DMA_CH11 = 11,
+ HALMAC_TXDESC_DMA_CH12 = 12,
+ HALMAC_TXDESC_DMA_CH13 = 13,
+ HALMAC_TXDESC_DMA_CH14 = 14,
+ HALMAC_TXDESC_DMA_CH15 = 15,
+ HALMAC_TXDESC_DMA_CH16 = 16,
+ HALMAC_TXDESC_DMA_CH17 = 17,
+ HALMAC_TXDESC_DMA_CH18 = 18,
+ HALMAC_TXDESC_DMA_CH19 = 19,
+ HALMAC_TXDESC_DMA_CH20 = 20,
+ HALMAC_TXDESC_DMA_CHMAX,
+ HALMAC_TXDESC_DMA_CHUNDEFINE = 0x7F,
+};
+
+enum halmac_dma_ch {
+ HALMAC_DMA_CH_0 = HALMAC_TXDESC_DMA_CH0,
+ HALMAC_DMA_CH_1 = HALMAC_TXDESC_DMA_CH1,
+ HALMAC_DMA_CH_2 = HALMAC_TXDESC_DMA_CH2,
+ HALMAC_DMA_CH_3 = HALMAC_TXDESC_DMA_CH3,
+ HALMAC_DMA_CH_4 = HALMAC_TXDESC_DMA_CH4,
+ HALMAC_DMA_CH_5 = HALMAC_TXDESC_DMA_CH5,
+ HALMAC_DMA_CH_6 = HALMAC_TXDESC_DMA_CH6,
+ HALMAC_DMA_CH_7 = HALMAC_TXDESC_DMA_CH7,
+ HALMAC_DMA_CH_8 = HALMAC_TXDESC_DMA_CH8,
+ HALMAC_DMA_CH_9 = HALMAC_TXDESC_DMA_CH9,
+ HALMAC_DMA_CH_10 = HALMAC_TXDESC_DMA_CH10,
+ HALMAC_DMA_CH_11 = HALMAC_TXDESC_DMA_CH11,
+ HALMAC_DMA_CH_S0 = HALMAC_TXDESC_DMA_CH12,
+ HALMAC_DMA_CH_S1 = HALMAC_TXDESC_DMA_CH13,
+ HALMAC_DMA_CH_MGQ = HALMAC_TXDESC_DMA_CH14,
+ HALMAC_DMA_CH_HIGH = HALMAC_TXDESC_DMA_CH15,
+ HALMAC_DMA_CH_FWCMD = HALMAC_TXDESC_DMA_CH16,
+ HALMAC_DMA_CH_MGQ_BAND1 = HALMAC_TXDESC_DMA_CH17,
+ HALMAC_DMA_CH_HIGH_BAND1 = HALMAC_TXDESC_DMA_CH18,
+ HALMAC_DMA_CH_BCN = HALMAC_TXDESC_DMA_CH19,
+ HALMAC_DMA_CH_H2C = HALMAC_TXDESC_DMA_CH20,
+ HALMAC_DMA_CH_MAX = HALMAC_TXDESC_DMA_CHMAX,
+ HALMAC_DMA_CH_UNDEFINE = 0x7F,
+};
+
+enum halmac_interface {
HALMAC_INTERFACE_PCIE = 0x0,
HALMAC_INTERFACE_USB = 0x1,
HALMAC_INTERFACE_SDIO = 0x2,
+ HALMAC_INTERFACE_AXI = 0x3,
HALMAC_INTERFACE_UNDEFINE = 0x7F,
-} HALMAC_INTERFACE;
+};
-typedef enum _HALMAC_RX_AGG_MODE {
+enum halmac_rx_agg_mode {
HALMAC_RX_AGG_MODE_NONE = 0x0,
HALMAC_RX_AGG_MODE_DMA = 0x1,
HALMAC_RX_AGG_MODE_USB = 0x2,
HALMAC_RX_AGG_MODE_UNDEFINE = 0x7F,
-} HALMAC_RX_AGG_MODE;
-typedef struct _HALMAC_RXAGG_TH {
+};
+
+struct halmac_rxagg_th {
u8 drv_define;
u8 timeout;
u8 size;
-} HALMAC_RXAGG_TH, *PHALMAC_RXAGG_TH;
-
-typedef struct _HALMAC_RXAGG_CFG {
- HALMAC_RX_AGG_MODE mode;
- HALMAC_RXAGG_TH threshold;
-} HALMAC_RXAGG_CFG, *PHALMAC_RXAGG_CFG;
-
-
-typedef enum _HALMAC_MAC_POWER {
- HALMAC_MAC_POWER_OFF = 0x0,
- HALMAC_MAC_POWER_ON = 0x1,
- HALMAC_MAC_POWER_UNDEFINE = 0x7F,
-} HALMAC_MAC_POWER;
-
-typedef enum _HALMAC_PS_STATE {
- HALMAC_PS_STATE_ACT = 0x0,
- HALMAC_PS_STATE_LPS = 0x1,
- HALMAC_PS_STATE_IPS = 0x2,
- HALMAC_PS_STATE_UNDEFINE = 0x7F,
-} HALMAC_PS_STATE;
-
-typedef enum _HALMAC_TRX_MODE {
+ u8 size_limit_en;
+};
+
+struct halmac_rxagg_cfg {
+ enum halmac_rx_agg_mode mode;
+ struct halmac_rxagg_th threshold;
+};
+
+struct halmac_api_registry {
+ u8 rx_exp_en:1;
+ u8 la_mode_en:1;
+ u8 cfg_drv_rsvd_pg_en:1;
+ u8 sdio_cmd53_4byte_en:1;
+ u8 rsvd:4;
+};
+
+enum halmac_trx_mode {
HALMAC_TRX_MODE_NORMAL = 0x0,
HALMAC_TRX_MODE_TRXSHARE = 0x1,
HALMAC_TRX_MODE_WMM = 0x2,
HALMAC_TRX_MODE_P2P = 0x3,
HALMAC_TRX_MODE_LOOPBACK = 0x4,
HALMAC_TRX_MODE_DELAY_LOOPBACK = 0x5,
+ HALMAC_TRX_MODE_MAX = 0x6,
+ HALMAC_TRX_MODE_WMM_LINUX = 0x7E,
HALMAC_TRX_MODE_UNDEFINE = 0x7F,
-} HALMAC_TRX_MODE;
+};
-typedef enum _HALMAC_WIRELESS_MODE {
+enum halmac_wireless_mode {
HALMAC_WIRELESS_MODE_B = 0x0,
HALMAC_WIRELESS_MODE_G = 0x1,
HALMAC_WIRELESS_MODE_N = 0x2,
HALMAC_WIRELESS_MODE_AC = 0x3,
HALMAC_WIRELESS_MODE_UNDEFINE = 0x7F,
-} HALMAC_WIRELESS_MODE;
+};
-typedef enum _HALMAC_BW {
+enum halmac_bw {
HALMAC_BW_20 = 0x00,
HALMAC_BW_40 = 0x01,
HALMAC_BW_80 = 0x02,
@@ -560,87 +724,56 @@ typedef enum _HALMAC_BW {
HALMAC_BW_10 = 0x05,
HALMAC_BW_MAX = 0x06,
HALMAC_BW_UNDEFINE = 0x7F,
-} HALMAC_BW;
+};
-
-typedef enum _HALMAC_EFUSE_READ_CFG {
+enum halmac_efuse_read_cfg {
HALMAC_EFUSE_R_AUTO = 0x00,
HALMAC_EFUSE_R_DRV = 0x01,
HALMAC_EFUSE_R_FW = 0x02,
HALMAC_EFUSE_R_UNDEFINE = 0x7F,
-} HALMAC_EFUSE_READ_CFG;
-
-
-typedef struct _HALMAC_TX_DESC {
- u32 Dword0;
- u32 Dword1;
- u32 Dword2;
- u32 Dword3;
- u32 Dword4;
- u32 Dword5;
- u32 Dword6;
- u32 Dword7;
- u32 Dword8;
- u32 Dword9;
- u32 Dword10;
- u32 Dword11;
-} HALMAC_TX_DESC, *PHALMAC_TX_DESC;
-
-typedef struct _HALMAC_RX_DESC {
- u32 Dword0;
- u32 Dword1;
- u32 Dword2;
- u32 Dword3;
- u32 Dword4;
- u32 Dword5;
-} HALMAC_RX_DESC, *PHALMAC_RX_DESC;
-
-typedef struct _HALMAC_FWLPS_OPTION {
- u8 mode;
- u8 clk_request;
- u8 rlbm;
- u8 smart_ps;
- u8 awake_interval;
- u8 all_queue_uapsd;
- u8 pwr_state;
- u8 low_pwr_rx_beacon;
- u8 ant_auto_switch;
- u8 ps_allow_bt_high_Priority;
- u8 protect_bcn;
- u8 silence_period;
- u8 fast_bt_connect;
- u8 two_antenna_en;
- u8 adopt_user_Setting;
- u8 drv_bcn_early_shift;
- u8 enter_32K;
-} HALMAC_FWLPS_OPTION, *PHALMAC_FWLPS_OPTION;
-
-typedef struct _HALMAC_FWIPS_OPTION {
- u8 adopt_user_Setting;
-} HALMAC_FWIPS_OPTION, *PHALMAC_FWIPS_OPTION;
-
-typedef struct _HALMAC_WOWLAN_OPTION {
- u8 adopt_user_Setting;
-} HALMAC_WOWLAN_OPTION, *PHALMAC_WOWLAN_OPTION;
-
-typedef struct _HALMAC_BCN_IE_INFO {
- u8 func_en;
- u8 size_th;
- u8 timeout;
- u8 ie_bmp[HALMAC_BCN_IE_BMP_SIZE];
-} HALMAC_BCN_IE_INFO, *PHALMAC_BCN_IE_INFO;
-
-typedef enum _HALMAC_REG_TYPE {
- HALMAC_REG_TYPE_MAC = 0x0,
- HALMAC_REG_TYPE_BB = 0x1,
- HALMAC_REG_TYPE_RF = 0x2,
- HALMAC_REG_TYPE_UNDEFINE = 0x7F,
-} HALMAC_REG_TYPE;
-
-typedef enum _HALMAC_PARAMETER_CMD {
- /* HALMAC_PARAMETER_CMD_LLT = 0x1, */
- /* HALMAC_PARAMETER_CMD_R_EFUSE = 0x2, */
- /* HALMAC_PARAMETER_CMD_EFUSE_PATCH = 0x3, */
+};
+
+enum halmac_dlfw_mem {
+ HALMAC_DLFW_MEM_EMEM = 0x00,
+ HALMAC_DLFW_MEM_EMEM_RSVD_PG = 0x01,
+ HALMAC_DLFW_MEM_UNDEFINE = 0x7F,
+};
+
+struct halmac_tx_desc {
+ u32 dword0;
+ u32 dword1;
+ u32 dword2;
+ u32 dword3;
+ u32 dword4;
+ u32 dword5;
+ u32 dword6;
+ u32 dword7;
+ u32 dword8;
+ u32 dword9;
+ u32 dword10;
+ u32 dword11;
+};
+
+struct halmac_rx_desc {
+ u32 dword0;
+ u32 dword1;
+ u32 dword2;
+ u32 dword3;
+ u32 dword4;
+ u32 dword5;
+};
+
+struct halmac_bcn_ie_info {
+ u8 func_en;
+ u8 size_th;
+ u8 timeout;
+ u8 ie_bmp[HALMAC_BCN_IE_BMP_SIZE];
+};
+
+enum halmac_parameter_cmd {
+ /* HALMAC_PARAMETER_CMD_LLT = 0x1, */
+ /* HALMAC_PARAMETER_CMD_R_EFUSE = 0x2, */
+ /* HALMAC_PARAMETER_CMD_EFUSE_PATCH = 0x3, */
HALMAC_PARAMETER_CMD_MAC_W8 = 0x4,
HALMAC_PARAMETER_CMD_MAC_W16 = 0x5,
HALMAC_PARAMETER_CMD_MAC_W32 = 0x6,
@@ -651,160 +784,159 @@ typedef enum _HALMAC_PARAMETER_CMD {
HALMAC_PARAMETER_CMD_DELAY_US = 0X10,
HALMAC_PARAMETER_CMD_DELAY_MS = 0X11,
HALMAC_PARAMETER_CMD_END = 0XFF,
-} HALMAC_PARAMETER_CMD;
+};
-typedef union _HALMAC_PARAMETER_CONTENT {
+union halmac_parameter_content {
struct _MAC_REG_W {
- u32 value;
- u32 msk;
- u16 offset;
- u8 msk_en;
+ u32 value;
+ u32 msk;
+ u16 offset;
+ u8 msk_en;
} MAC_REG_W;
struct _BB_REG_W {
- u32 value;
- u32 msk;
- u16 offset;
- u8 msk_en;
+ u32 value;
+ u32 msk;
+ u16 offset;
+ u8 msk_en;
} BB_REG_W;
struct _RF_REG_W {
- u32 value;
- u32 msk;
- u8 offset;
- u8 msk_en;
- u8 rf_path;
+ u32 value;
+ u32 msk;
+ u8 offset;
+ u8 msk_en;
+ u8 rf_path;
} RF_REG_W;
struct _DELAY_TIME {
- u32 rsvd1;
- u32 rsvd2;
- u16 delay_time;
- u8 rsvd3;
+ u32 rsvd1;
+ u32 rsvd2;
+ u16 delay_time;
+ u8 rsvd3;
} DELAY_TIME;
-} HALMAC_PARAMETER_CONTENT, *PHALMAC_PARAMETER_CONTENT;
-
-typedef struct _HALMAC_PHY_PARAMETER_INFO {
- HALMAC_PARAMETER_CMD cmd_id;
- HALMAC_PARAMETER_CONTENT content;
-} HALMAC_PHY_PARAMETER_INFO, *PHALMAC_PHY_PARAMETER_INFO;
-
-typedef struct _HALMAC_H2C_INFO {
- u16 h2c_seq_num; /* H2C sequence number */
- u8 in_use; /* 0 : empty 1 : used */
- HALMAC_H2C_RETURN_CODE status;
-} HALMAC_H2C_INFO, *PHALMAC_H2C_INFO;
-
-typedef struct _HALMAC_PG_EFUSE_INFO {
- u8 *pEfuse_map;
- u32 efuse_map_size;
- u8 *pEfuse_mask;
+};
+
+struct halmac_phy_parameter_info {
+ enum halmac_parameter_cmd cmd_id;
+ union halmac_parameter_content content;
+};
+
+struct halmac_pg_efuse_info {
+ u8 *efuse_map;
+ u32 efuse_map_size;
+ u8 *efuse_mask;
u32 efuse_mask_size;
-} HALMAC_PG_EFUSE_INFO, *PHALMAC_PG_EFUSE_INFO;
-
-typedef struct _HALMAC_TXAGG_BUFF_INFO {
- u8 *pTx_agg_buf;
- u8 *pCurr_pkt_buf;
- u32 avai_buf_size;
- u32 total_pkt_size;
- u8 agg_num;
-} HALMAC_TXAGG_BUFF_INFO, *PHALMAC_TXAGG_BUFF_INFO;
-
-typedef struct _HALMAC_CONFIG_PARA_INFO {
- u32 para_buf_size; /* Parameter buffer size */
- u8 *pCfg_para_buf; /* Buffer for config parameter */
- u8 *pPara_buf_w; /* Write pointer of the parameter buffer */
- u32 para_num; /* Parameter numbers in parameter buffer */
- u32 avai_para_buf_size; /* Free size of parameter buffer */
- u32 offset_accumulation;
- u32 value_accumulation;
- HALMAC_DATA_TYPE data_type; /*DataType which is passed to FW*/
- u8 datapack_segment; /*DataPack Segment, from segment0...*/
- u8 full_fifo_mode; /* Used full tx fifo to save cfg parameter */
-} HALMAC_CONFIG_PARA_INFO, *PHALMAC_CONFIG_PARA_INFO;
-
-typedef struct _HALMAC_HW_CONFIG_INFO {
- u32 efuse_size; /* Record efuse size */
- u32 eeprom_size; /* Record eeprom size */
- u32 bt_efuse_size; /* Record BT efuse size */
- u32 tx_fifo_size; /* Record tx fifo size */
- u32 rx_fifo_size; /* Record rx fifo size */
- u8 txdesc_size; /* Record tx desc size */
- u8 rxdesc_size; /* Record rx desc size */
- u8 cam_entry_num; /* Record CAM entry number */
-} HALMAC_HW_CONFIG_INFO, *PHALMAC_HW_CONFIG_INFO;
-
-typedef struct _HALMAC_SDIO_FREE_SPACE {
- u16 high_queue_number; /* Free space of HIQ */
- u16 normal_queue_number; /* Free space of MIDQ */
- u16 low_queue_number; /* Free space of LOWQ */
- u16 public_queue_number; /* Free space of PUBQ */
- u16 extra_queue_number; /* Free space of EXBQ */
- u8 ac_oqt_number;
- u8 non_ac_oqt_number;
-} HALMAC_SDIO_FREE_SPACE, *PHALMAC_SDIO_FREE_SPACE;
-
-typedef enum _HAL_FIFO_SEL {
+};
+
+struct halmac_cfg_param_info {
+ u32 buf_size;
+ u8 *buf;
+ u8 *buf_wptr;
+ u32 num;
+ u32 avl_buf_size;
+ u32 offset_accum;
+ u32 value_accum;
+ enum halmac_data_type data_type;
+ u8 full_fifo_mode;
+};
+
+struct halmac_hw_cfg_info {
+ u32 efuse_size;
+ u32 eeprom_size;
+ u32 bt_efuse_size;
+ u32 tx_fifo_size;
+ u32 rx_fifo_size;
+ u32 rx_desc_fifo_size;
+ u32 page_size;
+ u16 tx_align_size;
+ u8 txdesc_size;
+ u8 rxdesc_size;
+ u8 cam_entry_num;
+ u8 chk_security_keyid;
+ u8 txdesc_ie_max_num;
+ u8 txdesc_body_size;
+ u8 ac_oqt_size;
+ u8 non_ac_oqt_size;
+ u8 acq_num;
+ u8 trx_mode;
+ u8 usb_txagg_num;
+};
+
+struct halmac_sdio_free_space {
+ u16 hiq_pg_num;
+ u16 miq_pg_num;
+ u16 lowq_pg_num;
+ u16 pubq_pg_num;
+ u16 exq_pg_num;
+ u8 ac_oqt_num;
+ u8 non_ac_oqt_num;
+ u8 ac_empty;
+ u8 *macid_map;
+ u32 macid_map_size;
+};
+
+enum hal_fifo_sel {
HAL_FIFO_SEL_TX,
HAL_FIFO_SEL_RX,
HAL_FIFO_SEL_RSVD_PAGE,
HAL_FIFO_SEL_REPORT,
HAL_FIFO_SEL_LLT,
-} HAL_FIFO_SEL;
-
-typedef enum _HALMAC_DRV_INFO {
- HALMAC_DRV_INFO_NONE, /* No information is appended in rx_pkt */
- HALMAC_DRV_INFO_PHY_STATUS, /* PHY status is appended after rx_desc */
- HALMAC_DRV_INFO_PHY_SNIFFER, /* PHY status and sniffer info are appended after rx_desc */
- HALMAC_DRV_INFO_PHY_PLCP, /* PHY status and plcp header are appended after rx_desc */
+ HAL_FIFO_SEL_RXBUF_FW,
+ HAL_FIFO_SEL_RXBUF_PHY,
+ HAL_FIFO_SEL_RXDESC,
+ HAL_BUF_SECURITY_CAM,
+ HAL_BUF_WOW_CAM,
+ HAL_BUF_RX_FILTER_CAM,
+ HAL_BUF_BA_CAM,
+ HAL_BUF_MBSSID_CAM
+};
+
+enum halmac_drv_info {
+ /* No information is appended in rx_pkt */
+ HALMAC_DRV_INFO_NONE,
+ /* PHY status is appended after rx_desc */
+ HALMAC_DRV_INFO_PHY_STATUS,
+ /* PHY status and sniffer info are appended after rx_desc */
+ HALMAC_DRV_INFO_PHY_SNIFFER,
+ /* PHY status and plcp header are appended after rx_desc */
+ HALMAC_DRV_INFO_PHY_PLCP,
HALMAC_DRV_INFO_UNDEFINE,
-} HALMAC_DRV_INFO;
-
-typedef struct _HALMAC_BT_COEX_CMD {
- u8 element_id;
- u8 op_code;
- u8 op_code_ver;
- u8 req_num;
- u8 data0;
- u8 data1;
- u8 data2;
- u8 data3;
- u8 data4;
-} HALMAC_BT_COEX_CMD, *PHALMAC_BT_COEX_CMD;
-
-typedef enum _HALMAC_PRI_CH_IDX {
+};
+
+enum halmac_pri_ch_idx {
HALMAC_CH_IDX_UNDEFINE = 0,
HALMAC_CH_IDX_1 = 1,
HALMAC_CH_IDX_2 = 2,
HALMAC_CH_IDX_3 = 3,
HALMAC_CH_IDX_4 = 4,
HALMAC_CH_IDX_MAX = 5,
-} HALMAC_PRI_CH_IDX;
+};
-typedef struct _HALMAC_CH_INFO {
- HALMAC_CS_ACTION_ID action_id;
- HALMAC_BW bw;
- HALMAC_PRI_CH_IDX pri_ch_idx;
+struct halmac_ch_info {
+ enum halmac_cs_action_id action_id;
+ enum halmac_bw bw;
+ enum halmac_pri_ch_idx pri_ch_idx;
u8 channel;
u8 timeout;
u8 extra_info;
-} HALMAC_CH_INFO, *PHALMAC_CH_INFO;
+};
-typedef struct _HALMAC_CH_EXTRA_INFO {
+struct halmac_ch_extra_info {
u8 extra_info;
- HALMAC_CS_EXTRA_ACTION_ID extra_action_id;
+ enum halmac_cs_extra_action_id extra_action_id;
u8 extra_info_size;
u8 *extra_info_data;
-} HALMAC_CH_EXTRA_INFO, *PHALMAC_CH_EXTRA_INFO;
+};
-typedef enum _HALMAC_CS_PERIODIC_OPTION {
+enum halmac_cs_periodic_option {
HALMAC_CS_PERIODIC_NONE,
HALMAC_CS_PERIODIC_NORMAL,
HALMAC_CS_PERIODIC_2_PHASE,
HALMAC_CS_PERIODIC_SEAMLESS,
-} HALMAC_CS_PERIODIC_OPTION;
+};
-typedef struct _HALMAC_CH_SWITCH_OPTION {
- HALMAC_BW dest_bw;
- HALMAC_CS_PERIODIC_OPTION periodic_option;
- HALMAC_PRI_CH_IDX dest_pri_ch_idx;
+struct halmac_ch_switch_option {
+ enum halmac_bw dest_bw;
+ enum halmac_cs_periodic_option periodic_option;
+ enum halmac_pri_ch_idx dest_pri_ch_idx;
/* u32 tsf_high; */
u32 tsf_low;
u8 switch_en;
@@ -812,17 +944,51 @@ typedef struct _HALMAC_CH_SWITCH_OPTION {
u8 absolute_time_en;
u8 dest_ch;
u8 normal_period;
+ u8 normal_period_sel;
u8 normal_cycle;
u8 phase_2_period;
-} HALMAC_CH_SWITCH_OPTION, *PHALMAC_CH_SWITCH_OPTION;
-
-typedef struct _HALMAC_FW_VERSION {
+ u8 phase_2_period_sel;
+};
+
+struct halmac_p2pps {
+ u8 offload_en:1;
+ u8 role:1;
+ u8 ctwindow_en:1;
+ u8 noa_en:1;
+ u8 noa_sel:1;
+ u8 all_sta_sleep:1;
+ u8 discovery:1;
+ u8 disable_close_rf:1;
+ u8 p2p_port_id;
+ u8 p2p_group;
+ u8 p2p_macid;
+ u8 ctwindow_length;
+ u8 rsvd3;
+ u8 rsvd4;
+ u8 rsvd5;
+ u32 noa_duration_para;
+ u32 noa_interval_para;
+ u32 noa_start_time_para;
+ u32 noa_count_para;
+};
+
+struct halmac_fw_build_time {
+ u16 year;
+ u8 month;
+ u8 date;
+ u8 hour;
+ u8 min;
+};
+
+struct halmac_fw_version {
u16 version;
u8 sub_version;
u8 sub_index;
-} HALMAC_FW_VERSION, *PHALMAC_FW_VERSION;
+ u16 h2c_version;
+ struct halmac_fw_build_time build_time;
+};
-typedef enum _HALMAC_RF_TYPE {
+enum halmac_rf_type {
HALMAC_RF_1T2R = 0,
HALMAC_RF_2T4R = 1,
HALMAC_RF_2T2R = 2,
@@ -833,43 +999,35 @@ typedef enum _HALMAC_RF_TYPE {
HALMAC_RF_3T4R = 7,
HALMAC_RF_4T4R = 8,
HALMAC_RF_MAX_TYPE = 0xF,
-} HALMAC_RF_TYPE;
+};
-typedef struct _HALMAC_GENERAL_INFO {
+struct halmac_general_info {
u8 rfe_type;
- HALMAC_RF_TYPE rf_type;
-} HALMAC_GENERAL_INFO, *PHALMAC_GENERAL_INFO;
+ enum halmac_rf_type rf_type;
+ u8 tx_ant_status;
+ u8 rx_ant_status;
+};
-typedef struct _HALMAC_PWR_TRACKING_PARA {
+struct halmac_pwr_tracking_para {
u8 enable;
u8 tx_pwr_index;
u8 pwr_tracking_offset_value;
u8 tssi_value;
-} HALMAC_PWR_TRACKING_PARA, *PHALMAC_PWR_TRACKING_PARA;
+};
-typedef struct _HALMAC_PWR_TRACKING_OPTION {
+struct halmac_pwr_tracking_option {
u8 type;
u8 bbswing_index;
- HALMAC_PWR_TRACKING_PARA pwr_tracking_para[4]; /* pathA, pathB, pathC, pathD */
-} HALMAC_PWR_TRACKING_OPTION, *PHALMAC_PWR_TRACKING_OPTION;
-
-typedef struct _HALMAC_NLO_CFG {
- u8 num_of_ssid;
- u8 num_of_hidden_ap;
- u8 rsvd[2];
- u32 pattern_check;
- u32 rsvd1;
- u32 rsvd2;
- u8 ssid_len[HALMAC_SUPPORT_NLO_NUM];
- u8 ChiperType[HALMAC_SUPPORT_NLO_NUM];
- u8 rsvd3[HALMAC_SUPPORT_NLO_NUM];
- u8 loc_probeReq[HALMAC_SUPPORT_PROBE_REQ_NUM];
- u8 rsvd4[56];
- u8 ssid[HALMAC_SUPPORT_NLO_NUM][HALMAC_MAX_SSID_LEN];
-} HALMAC_NLO_CFG, *PHALMAC_NLO_CFG;
-
-
-typedef enum _HALMAC_DATA_RATE {
+ /* pathA, pathB, pathC, pathD */
+ struct halmac_pwr_tracking_para pwr_tracking_para[4];
+};
+
+struct halmac_fast_edca_cfg {
+ enum halmac_acq_id acq_id;
+ u8 queue_to; /* unit : 32us*/
+};
+
+enum halmac_data_rate {
HALMAC_CCK1,
HALMAC_CCK2,
HALMAC_CCK5_5,
@@ -953,79 +1111,22 @@ typedef enum _HALMAC_DATA_RATE {
HALMAC_VHT_NSS4_MCS6,
HALMAC_VHT_NSS4_MCS7,
HALMAC_VHT_NSS4_MCS8,
- HALMAC_VHT_NSS4_MCS9
-} HALMAC_DATA_RATE;
-
-typedef enum _HALMAC_RF_PATH {
+ HALMAC_VHT_NSS4_MCS9,
+ /*FPGA only*/
+ HALMAC_VHT_NSS5_MCS0,
+ HALMAC_VHT_NSS6_MCS0,
+ HALMAC_VHT_NSS7_MCS0,
+ HALMAC_VHT_NSS8_MCS0
+};
+
+enum halmac_rf_path {
HALMAC_RF_PATH_A,
HALMAC_RF_PATH_B,
HALMAC_RF_PATH_C,
HALMAC_RF_PATH_D
-} HALMAC_RF_PATH;
-
-typedef enum _HALMAC_SND_PKT_SEL {
- HALMAC_UNI_NDPA,
- HALMAC_BMC_NDPA,
- HALMAC_NON_FINAL_BFRPRPOLL,
- HALMAC_FINAL_BFRPTPOLL,
-} HALMAC_SND_PKT_SEL;
-
-#if HALMAC_PLATFORM_TESTPROGRAM
+};
-typedef enum _HALMAC_PWR_SEQ_ID {
- HALMAC_PWR_SEQ_ENABLE,
- HALMAC_PWR_SEQ_DISABLE,
- HALMAC_PWR_SEQ_ENTER_LPS,
- HALMAC_PWR_SEQ_ENTER_DEEP_LPS,
- HALMAC_PWR_SEQ_LEAVE_LPS,
- HALMAC_PWR_SEQ_MAX
-} HALMAC_PWR_SEQ_ID;
-
-typedef enum _HAL_TX_ID {
- HAL_TX_ID_VO,
- HAL_TX_ID_VI,
- HAL_TX_ID_BE,
- HAL_TX_ID_BK,
- HAL_TX_ID_BCN,
- HAL_TX_ID_H2C,
- HAL_TX_ID_MAX
-} HAL_TX_ID;
-
-typedef enum _HAL_QSEL {
- HAL_QSEL_TID0,
- HAL_QSEL_TID1,
- HAL_QSEL_TID2,
- HAL_QSEL_TID3,
- HAL_QSEL_TID4,
- HAL_QSEL_TID5,
- HAL_QSEL_TID6,
- HAL_QSEL_TID7,
-
- HAL_QSEL_BEACON = 0x10,
- HAL_QSEL_HIGH = 0x11,
- HAL_QSEL_MGT = 0x12,
- HAL_QSEL_CMD = 0x13
-} HAL_QSEL;
-
-typedef enum _HAL_RTS_MODE {
- HAL_RTS_MODE_NONE,
- HAL_RTS_MODE_CTS2SELF,
- HAL_RTS_MODE_RTS,
-} HAL_RTS_MODE;
-
-typedef enum _HAL_DATA_BW {
- HAL_DATA_BW_20M,
- HAL_DATA_BW_40M,
- HAL_DATA_BW_80M,
- HAL_DATA_BW_160M,
-} HAL_DATA_BW;
-
-typedef enum _HAL_RTS_SHORT {
- HAL_RTS_SHORT_SHORT,
- HAL_RTS_SHORT_LONG,
-} HAL_RTS_SHORT;
-
-typedef enum _HAL_SECURITY_TYPE {
+enum hal_security_type {
HAL_SECURITY_TYPE_NONE = 0,
HAL_SECURITY_TYPE_WEP40 = 1,
HAL_SECURITY_TYPE_WEP104 = 2,
@@ -1038,142 +1139,32 @@ typedef enum _HAL_SECURITY_TYPE {
HAL_SECURITY_TYPE_GCMSMS4 = 9,
HAL_SECURITY_TYPE_BIP = 10,
HAL_SECURITY_TYPE_UNDEFINE = 0x7F,
-} HAL_SECURITY_TYPE;
-
-typedef enum _HAL_SECURITY_METHOD {
- HAL_SECURITY_METHOD_HW = 0,
- HAL_SECURITY_METHOD_SW = 1,
- HAL_SECURITY_METHOD_UNDEFINE = 0x7F,
-} HAL_SECURITY_METHOD;
-
-typedef struct _HAL_SECURITY_INFO {
- HAL_SECURITY_TYPE type;
- HAL_SECURITY_METHOD tx_method;
- HAL_SECURITY_METHOD rx_method;
-} HAL_SECURITY_INFO, *PHAL_SECURITY_INFO;
-
-typedef struct _HAL_TXDESC_INFO {
- u32 txdesc_length;
- u32 packet_size; /* payload + wlheader */
- HAL_TX_ID tx_id;
- HALMAC_DATA_RATE data_rate;
- HAL_RTS_MODE rts_mode;
- HAL_DATA_BW data_bw;
- HAL_RTS_SHORT rts_short;
- HAL_SECURITY_TYPE security_type;
- HAL_SECURITY_METHOD encryption_method;
- u16 seq_num;
- u8 retry_limit_en;
- u8 retry_limit_number;
- u8 rts_threshold;
- u8 qos;
- u8 ht;
- u8 ampdu;
- u8 early_mode;
- u8 bm_cast;
- u8 data_short;
- u8 mac_id;
-} HAL_TXDESC_INFO, *PHAL_TXDESC_INFO;
-
-typedef struct _HAL_RXDESC_INFO {
- u8 c2h;
- u8 *pWifi_pkt;
- u32 packet_size;
- u8 crc_err;
- u8 icv_err;
-} HAL_RXDESC_INFO, *PHAL_RXDESC_INFO;
-
-typedef struct _HAL_TXDESC_PARSER {
- u8 txdesc_len;
- u16 txpkt_size;
-} HAL_TXDESC_PARSER, *PHAL_TXDESC_PARSER;
-
-typedef struct _HAL_RXDESC_PARSER {
- u32 driver_info_size;
- u16 rxpkt_size;
- u8 rxdesc_len;
- u8 c2h;
- u8 crc_err;
- u8 icv_err;
-} HAL_RXDESC_PARSER, *PHAL_RXDESC_PARSER;
-
-typedef struct _HAL_RF_REG_INFO {
- HALMAC_RF_PATH rf_path;
- u32 offset;
- u32 bit_mask;
- u32 data;
-} HAL_RF_REG_INFO, *PHAL_RF_REG_INFO;
-
-typedef struct _HALMAC_SDIO_HIMR_INFO {
- u8 rx_request;
- u8 aval_msk;
-} HALMAC_SDIO_HIMR_INFO, *PHALMAC_SDIO_HIMR_INFO;
-
-typedef struct _HALMAC_BEACON_INFO {
-} HALMAC_BEACON_INFO, *PHALMAC_BEACON_INFO;
-
-typedef struct _HALMAC_MGNT_INFO {
- u8 mu_enable;
- u8 bip;
- u8 unicast;
- u32 packet_size;
-} HALMAC_MGNT_INFO, *PHALMAC_MGNT_INFO;
-
-typedef struct _HALMAC_CTRL_INFO {
- u8 snd_enable;
- HALMAC_SND_PKT_SEL snd_pkt_sel; /* 0:unicast ndpa 1:broadcast ndpa 3:non-final BF Rpt Poll 4:final BF Rpt Poll */
- u8 *pPacket_desc;
- u32 desc_size;
- u16 seq_num;
- u8 bw;
- u16 paid;
-} HALMAC_CTRL_INFO, *PHALMAC_CTRL_INFO;
-
-typedef struct _HALMAC_HIGH_QUEUE_INFO {
- u8 *pPacket_desc;
- u32 desc_size;
-} HALMAC_HIGH_QUEUE_INFO, *PHALMAC_HIGH_QUEUE_INFO;
-
-typedef struct _HALMAC_CHIP_TYPE {
- HALMAC_CHIP_ID chip_id;
- HALMAC_CHIP_VER chip_version;
-} HALMAC_CHIP_TYPE, *PHALMAC_CHIP_TYPE;
-
-typedef struct _HALMAC_CAM_ENTRY_FORMAT {
- u16 key_id : 2;
- u16 type : 3;
- u16 mic : 1;
- u16 grp : 1;
- u16 spp_mode : 1;
- u16 rpt_md : 1;
- u16 ext_sectype : 1;
- u16 mgnt : 1;
- u16 rsvd1 : 4;
- u16 valid : 1;
- u8 mac_address[6];
- u32 key[4];
- u32 rsvd[2];
-} HALMAC_CAM_ENTRY_FORMAT, *PHALMAC_CAM_ENTRY_FORMAT;
-
-typedef struct _HALMAC_CAM_ENTRY_INFO {
- HAL_SECURITY_TYPE security_type;
- u32 key[4];
- u32 key_ext[4];
- u8 mac_address[6];
- u8 unicast;
- u8 key_id;
- u8 valid;
-} HALMAC_CAM_ENTRY_INFO, *PHALMAC_CAM_ENTRY_INFO;
-
-#endif /* End of test program */
-
-typedef enum _HALMAC_DBG_MSG_INFO {
+};
+
+enum hal_intf_phy {
+ HAL_INTF_PHY_USB2 = 0,
+ HAL_INTF_PHY_USB3 = 1,
+ HAL_INTF_PHY_PCIE_GEN1 = 2,
+ HAL_INTF_PHY_PCIE_GEN2 = 3,
+ HAL_INTF_PHY_UNDEFINE = 0x7F,
+};
+
+struct halmac_cut_amsdu_cfg {
+ u8 cut_amsdu_en;
+ u8 chk_len_en;
+ u8 chk_len_def_val;
+ u8 chk_len_l_th;
+ u16 chk_len_h_th;
+};
+
+enum halmac_dbg_msg_info {
+ HALMAC_DBG_ALWAYS,
HALMAC_DBG_ERR,
HALMAC_DBG_WARN,
HALMAC_DBG_TRACE,
-} HALMAC_DBG_MSG_INFO;
+};
-typedef enum _HALMAC_DBG_MSG_TYPE {
+enum halmac_dbg_msg_type {
HALMAC_MSG_INIT,
HALMAC_MSG_EFUSE,
HALMAC_MSG_FW,
@@ -1181,18 +1172,12 @@ typedef enum _HALMAC_DBG_MSG_TYPE {
HALMAC_MSG_PWR,
HALMAC_MSG_SND,
HALMAC_MSG_COMMON,
-} HALMAC_DBG_MSG_TYPE;
-
-typedef enum _HALMAC_CMD_PROCESS_STATUS {
- HALMAC_CMD_PROCESS_IDLE = 0x01, /* Init status */
- HALMAC_CMD_PROCESS_SENDING = 0x02, /* Wait ack */
- HALMAC_CMD_PROCESS_RCVD = 0x03, /* Rcvd ack */
- HALMAC_CMD_PROCESS_DONE = 0x04, /* Event done */
- HALMAC_CMD_PROCESS_ERROR = 0x05, /* Return code error */
- HALMAC_CMD_PROCESS_UNDEFINE = 0x7F,
-} HALMAC_CMD_PROCESS_STATUS;
-
-typedef enum _HALMAC_FEATURE_ID {
+ HALMAC_MSG_DBI,
+ HALMAC_MSG_MDIO,
+ HALMAC_MSG_USB,
+};
+
+enum halmac_feature_id {
HALMAC_FEATURE_CFG_PARA, /* Support */
HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE, /* Support */
HALMAC_FEATURE_DUMP_LOGICAL_EFUSE, /* Support */
@@ -1203,298 +1188,189 @@ typedef enum _HALMAC_FEATURE_ID {
HALMAC_FEATURE_IQK, /* Support */
HALMAC_FEATURE_POWER_TRACKING, /* Support */
HALMAC_FEATURE_PSD, /* Support */
+ HALMAC_FEATURE_FW_SNDING, /* Support */
HALMAC_FEATURE_ALL, /* Support, only for reset */
-} HALMAC_FEATURE_ID;
+};
-typedef enum _HALMAC_DRV_RSVD_PG_NUM {
+enum halmac_drv_rsvd_pg_num {
+ HALMAC_RSVD_PG_NUM8, /* 1K */
HALMAC_RSVD_PG_NUM16, /* 2K */
HALMAC_RSVD_PG_NUM24, /* 3K */
HALMAC_RSVD_PG_NUM32, /* 4K */
-} HALMAC_DRV_RSVD_PG_NUM;
-
-
-/* Platform API setting */
-typedef struct _HALMAC_PLATFORM_API {
- /* R/W register */
- u8 (*SDIO_CMD52_READ)(VOID *pDriver_adapter, u32 offset);
- u8 (*SDIO_CMD53_READ_8)(VOID *pDriver_adapter, u32 offset);
- u16 (*SDIO_CMD53_READ_16)(VOID *pDriver_adapter, u32 offset);
- u32 (*SDIO_CMD53_READ_32)(VOID *pDriver_adapter, u32 offset);
- VOID (*SDIO_CMD52_WRITE)(VOID *pDriver_adapter, u32 offset, u8 value);
- VOID (*SDIO_CMD53_WRITE_8)(VOID *pDriver_adapter, u32 offset, u8 value);
- VOID (*SDIO_CMD53_WRITE_16)(VOID *pDriver_adapter, u32 offset, u16 value);
- VOID (*SDIO_CMD53_WRITE_32)(VOID *pDriver_adapter, u32 offset, u32 value);
- u8 (*REG_READ_8)(VOID *pDriver_adapter, u32 offset);
- u16 (*REG_READ_16)(VOID *pDriver_adapter, u32 offset);
- u32 (*REG_READ_32)(VOID *pDriver_adapter, u32 offset);
- VOID (*REG_WRITE_8)(VOID *pDriver_adapter, u32 offset, u8 value);
- VOID (*REG_WRITE_16)(VOID *pDriver_adapter, u32 offset, u16 value);
- VOID (*REG_WRITE_32)(VOID *pDriver_adapter, u32 offset, u32 value);
-
- /* send pBuf to reserved page, the tx_desc is not included in pBuf, driver need to fill tx_desc with qsel = bcn */
- u8 (*SEND_RSVD_PAGE)(VOID *pDriver_adapter, u8 *pBuf, u32 size);
- /* send pBuf to h2c queue, the tx_desc is not included in pBuf, driver need to fill tx_desc with qsel = h2c */
- u8 (*SEND_H2C_PKT)(VOID *pDriver_adapter, u8 *pBuf, u32 size);
-
- u8 (*RTL_FREE)(VOID *pDriver_adapter, VOID *pBuf, u32 size);
- VOID* (*RTL_MALLOC)(VOID *pDriver_adapter, u32 size);
- u8 (*RTL_MEMCPY)(VOID *pDriver_adapter, VOID *dest, VOID *src, u32 size);
- u8 (*RTL_MEMSET)(VOID *pDriver_adapter, VOID *pAddress, u8 value, u32 size);
- VOID (*RTL_DELAY_US)(VOID *pDriver_adapter, u32 us);
-
- u8 (*MUTEX_INIT)(VOID *pDriver_adapter, HALMAC_MUTEX *pMutex);
- u8 (*MUTEX_DEINIT)(VOID *pDriver_adapter, HALMAC_MUTEX *pMutex);
- u8 (*MUTEX_LOCK)(VOID *pDriver_adapter, HALMAC_MUTEX *pMutex);
- u8 (*MUTEX_UNLOCK)(VOID *pDriver_adapter, HALMAC_MUTEX *pMutex);
-
- u8 (*MSG_PRINT)(VOID *pDriver_adapter, u32 msg_type, u8 msg_level, s8 *fmt, ...);
-
- u8 (*EVENT_INDICATION)(VOID *pDriver_adapter, HALMAC_FEATURE_ID feature_id, HALMAC_CMD_PROCESS_STATUS process_status, u8 *buf, u32 size);
-
-#if HALMAC_PLATFORM_TESTPROGRAM
- VOID* (*PCI_ALLOC_COMM_BUFF)(VOID *pDriver_adapter, u32 size, u32 *physical_addr, u8 cache_en);
- VOID (*PCI_FREE_COMM_BUFF)(VOID *pDriver_adapter, u32 size, u32 physical_addr, VOID *virtual_addr, u8 cache_en);
- u8 (*WRITE_DATA_SDIO_ADDR)(VOID *pDriver_adapter, u8 *pBuf, u32 size, u32 addr);
- u8 (*WRITE_DATA_USB_BULKOUT_ID)(VOID *pDriver_adapter, u8 *pBuf, u32 size, u8 bulkout_id);
- u8 (*WRITE_DATA_PCIE_QUEUE)(VOID *pDriver_adapter, u8 *pBuf, u32 size, u8 queue);
- u8 (*READ_DATA)(VOID *pDriver_adapter, u8 *pBuf, u32 *read_length);
-#endif
-} HALMAC_PLATFORM_API, *PHALMAC_PLATFORM_API;
-
-/*1->Little endian 0->Big endian*/
-#if HALMAC_SYSTEM_ENDIAN
-
-/* User can not use members in Address_L_H, use Address[6] is mandatory */
-typedef union _HALMAC_WLAN_ADDR {
- u8 Address[6]; /* WLAN address (MACID, BSSID, Brodcast ID). Address[0] is lowest, Address[5] is highest*/
+ HALMAC_RSVD_PG_NUM64, /* 8K */
+ HALMAC_RSVD_PG_NUM128, /* 16K */
+};
+
+enum halmac_pcie_cfg {
+ HALMAC_PCIE_GEN1,
+ HALMAC_PCIE_GEN2,
+ HALMAC_PCIE_CFG_UNDEFINE,
+};
+
+enum halmac_portid {
+ HALMAC_PORTID0 = 0,
+ HALMAC_PORTID1 = 1,
+ HALMAC_PORTID2 = 2,
+ HALMAC_PORTID3 = 3,
+ HALMAC_PORTID4 = 4,
+ HALMAC_PORTID_NUM = 5,
+};
+
+struct halmac_bcn_ctrl {
+ u8 dis_rx_bssid_fit;
+ u8 en_txbcn_rpt;
+ u8 dis_tsf_udt;
+ u8 en_bcn;
+ u8 en_rxbcn_rpt;
+ u8 en_p2p_ctwin;
+ u8 en_p2p_bcn_area;
+};
+
+/* User only can use Address[6]*/
+/* Address[0] is lowest, Address[5] is highest */
+union halmac_wlan_addr {
+ u8 addr[6];
struct {
union {
- u32 Address_Low;
- u8 Address_Low_B[4];
+ u32 low;
+ u8 low_byte[4];
};
union {
- u16 Address_High;
- u8 Address_High_B[2];
+ u16 high;
+ u8 high_byte[2];
};
- } Address_L_H;
-} HALMAC_WLAN_ADDR, *PHALMAC_WLAN_ADDR;
-
-#else
+ } addr_l_h;
+};
-/* User can not use members in Address_L_H, use Address[6] is mandatory */
-typedef union _HALMAC_WLAN_ADDR {
- u8 Address[6]; /* WLAN address (MACID, BSSID, Brodcast ID). Address[0] is lowest, Address[5] is highest*/
- struct {
- union {
- u32 Address_Low;
- u8 Address_Low_B[4];
- };
- union {
- u16 Address_High;
- u8 Address_High_B[2];
- };
- } Address_L_H;
-} HALMAC_WLAN_ADDR, *PHALMAC_WLAN_ADDR;
+struct halmac_platform_api {
+ /* R/W register */
+ u8 (*SDIO_CMD52_READ)(void *drv_adapter, u32 offset);
+ u8 (*SDIO_CMD53_READ_8)(void *drv_adapter, u32 offset);
+ u16 (*SDIO_CMD53_READ_16)(void *drv_adapter, u32 offset);
+ u32 (*SDIO_CMD53_READ_32)(void *drv_adapter, u32 offset);
+ u8 (*SDIO_CMD53_READ_N)(void *drv_adapter, u32 offset, u32 size,
+ u8 *data);
+ void (*SDIO_CMD52_WRITE)(void *drv_adapter, u32 offset, u8 value);
+ void (*SDIO_CMD53_WRITE_8)(void *drv_adapter, u32 offset, u8 value);
+ void (*SDIO_CMD53_WRITE_16)(void *drv_adapter, u32 offset, u16 value);
+ void (*SDIO_CMD53_WRITE_32)(void *drv_adapter, u32 offset, u32 value);
+ u8 (*REG_READ_8)(void *drv_adapter, u32 offset);
+ u16 (*REG_READ_16)(void *drv_adapter, u32 offset);
+ u32 (*REG_READ_32)(void *drv_adapter, u32 offset);
+ void (*REG_WRITE_8)(void *drv_adapter, u32 offset, u8 value);
+ void (*REG_WRITE_16)(void *drv_adapter, u32 offset, u16 value);
+ void (*REG_WRITE_32)(void *drv_adapter, u32 offset, u32 value);
+ u8 (*SDIO_CMD52_CIA_READ)(void *drv_adapter, u32 offset);
+
+ /* send pBuf to reserved page, the tx_desc is not included in pBuf */
+ /* driver need to fill tx_desc with qsel = bcn */
+ u8 (*SEND_RSVD_PAGE)(void *drv_adapter, u8 *buf, u32 size);
+ /* send pBuf to h2c queue, the tx_desc is not included in pBuf */
+ /* driver need to fill tx_desc with qsel = h2c */
+ u8 (*SEND_H2C_PKT)(void *drv_adapter, u8 *buf, u32 size);
+ /* send pBuf to fw cmd queue, the tx_desc is not included in pBuf */
+ /*driver need to fill tx_desc with qsel = h2c */
+ u8 (*SEND_FWCMD)(void *drv_adapter, u8 *buf, u32 size);
+
+ u8 (*RTL_FREE)(void *drv_adapter, void *buf, u32 size);
+ void* (*RTL_MALLOC)(void *drv_adapter, u32 size);
+ u8 (*RTL_MEMCPY)(void *drv_adapter, void *dest, void *src, u32 size);
+ u8 (*RTL_MEMSET)(void *drv_adapter, void *addr, u8 value, u32 size);
+ void (*RTL_DELAY_US)(void *drv_adapter, u32 us);
+
+ u8 (*MUTEX_INIT)(void *drv_adapter, HALMAC_MUTEX *mutex);
+ u8 (*MUTEX_DEINIT)(void *drv_adapter, HALMAC_MUTEX *mutex);
+ u8 (*MUTEX_LOCK)(void *drv_adapter, HALMAC_MUTEX *mutex);
+ u8 (*MUTEX_UNLOCK)(void *drv_adapter, HALMAC_MUTEX *mutex);
+
+ u8 (*MSG_PRINT)(void *drv_adapter, u32 msg_type, u8 msg_level,
+ s8 *fmt, ...);
+ u8 (*BUFF_PRINT)(void *drv_adapter, u32 msg_type, u8 msg_level, s8 *buf,
+ u32 size);
+
+ u8 (*EVENT_INDICATION)(void *drv_adapter,
+ enum halmac_feature_id feature_id,
+ enum halmac_cmd_process_status process_status,
+ u8 *buf, u32 size);
+#if HALMAC_PLATFORM_TESTPROGRAM
+ struct halmisc_platform_api *halmisc_pltfm_api;
#endif
+};
-typedef enum _HALMAC_SND_ROLE {
+enum halmac_snd_role {
HAL_BFER = 0,
HAL_BFEE = 1,
-} HALMAC_SND_ROLE;
+};
-typedef enum _HALMAC_CSI_SEG_LEN {
+enum halmac_csi_seg_len {
HAL_CSI_SEG_4K = 0,
HAL_CSI_SEG_8K = 1,
HAL_CSI_SEG_11K = 2,
-} HALMAC_CSI_SEG_LEN;
+};
-
-typedef struct _HALMAC_CFG_MUMIMO_PARA {
- HALMAC_SND_ROLE role;
+struct halmac_cfg_mumimo_para {
+ enum halmac_snd_role role;
u8 sounding_sts[6];
u16 grouping_bitmap;
u8 mu_tx_en;
u32 given_gid_tab[2];
u32 given_user_pos[4];
-} HALMAC_CFG_MUMIMO_PARA, *PHALMAC_CFG_MUMIMO_PARA;
+};
-typedef struct _HALMAC_SU_BFER_INIT_PARA {
+struct halmac_su_bfer_init_para {
u8 userid;
u16 paid;
u16 csi_para;
- PHALMAC_WLAN_ADDR pbfer_address;
-} HALMAC_SU_BFER_INIT_PARA, *PHALMAC_SU_BFER_INIT_PARA;
+ union halmac_wlan_addr bfer_address;
+};
-typedef struct _HALMAC_MU_BFEE_INIT_PARA {
+struct halmac_mu_bfee_init_para {
u8 userid;
u16 paid;
- u32 user_position_l;
- u32 user_position_h;
-} HALMAC_MU_BFEE_INIT_PARA, *PHALMAC_MU_BFEE_INIT_PARA;
+ u32 user_position_l; /*for gid 0~15*/
+ u32 user_position_h; /*for gid 16~31*/
+ u32 user_position_l_1; /*for gid 32~47*/
+ u32 user_position_h_1; /*for gid 48~63*/
+};
-typedef struct _HALMAC_MU_BFER_INIT_PARA {
+struct halmac_mu_bfer_init_para {
u16 paid;
u16 csi_para;
u16 my_aid;
- HALMAC_CSI_SEG_LEN csi_length_sel;
- PHALMAC_WLAN_ADDR pbfer_address;
-} HALMAC_MU_BFER_INIT_PARA, *PHALMAC_MU_BFER_INIT_PARA;
+ enum halmac_csi_seg_len csi_length_sel;
+ union halmac_wlan_addr bfer_address;
+};
-typedef struct _HALMAC_SND_INFO {
- u16 paid;
- u8 userid;
- HALMAC_DATA_RATE ndpa_rate;
- u16 csi_para;
- u16 my_aid;
- HALMAC_DATA_RATE csi_rate;
- HALMAC_CSI_SEG_LEN csi_length_sel;
- HALMAC_SND_ROLE role;
- HALMAC_WLAN_ADDR bfer_address;
- HALMAC_BW bw;
- u8 txbf_en;
- PHALMAC_SU_BFER_INIT_PARA pSu_bfer_init;
- PHALMAC_MU_BFER_INIT_PARA pMu_bfer_init;
- PHALMAC_MU_BFEE_INIT_PARA pMu_bfee_init;
-} HALMAC_SND_INFO, *PHALMAC_SND_INFO;
-
-typedef struct _HALMAC_CS_INFO {
- u8 *ch_info_buf;
- u8 *ch_info_buf_w;
+struct halmac_ch_sw_info {
+ u8 *buf;
+ u8 *buf_wptr;
u8 extra_info_en;
- u32 buf_size; /* buffer size */
- u32 avai_buf_size; /* buffer size */
- u32 total_size;
- u32 accu_timeout;
- u32 ch_num;
-} HALMAC_CS_INFO, *PHALMAC_CS_INFO;
-
-typedef struct _HALMAC_RESTORE_INFO {
- u32 mac_register;
- u32 value;
- u8 length;
-} HALMAC_RESTORE_INFO, *PHALMAC_RESTORE_INFO;
-
-typedef struct _HALMAC_EVENT_TRIGGER {
- u32 physical_efuse_map : 1;
- u32 logical_efuse_map : 1;
- u32 rsvd1 : 28;
-} HALMAC_EVENT_TRIGGER, *PHALMAC_EVENT_TRIGGER;
-
-typedef struct _HALMAC_H2C_HEADER_INFO {
- u16 sub_cmd_id;
- u16 content_size;
+ u32 buf_size;
+ u32 avl_buf_size;
+ u32 total_size;
+ u32 ch_num;
+};
+
+struct halmac_event_trigger {
+ u32 phy_efuse_map : 1;
+ u32 log_efuse_map : 1;
+ u32 rsvd1 : 28;
+};
+
+struct halmac_h2c_header_info {
+ u16 sub_cmd_id;
+ u16 content_size;
u8 ack;
-} HALMAC_H2C_HEADER_INFO, *PHALMAC_H2C_HEADER_INFO;
-
-typedef enum _HALMAC_DLFW_STATE {
- HALMAC_DLFW_NONE = 0,
- HALMAC_DLFW_DONE = 1,
- HALMAC_GEN_INFO_SENT = 2,
- HALMAC_DLFW_UNDEFINED = 0x7F,
-} HALMAC_DLFW_STATE;
-
-typedef enum _HALMAC_EFUSE_CMD_CONSTRUCT_STATE {
- HALMAC_EFUSE_CMD_CONSTRUCT_IDLE = 0,
- HALMAC_EFUSE_CMD_CONSTRUCT_BUSY = 1,
- HALMAC_EFUSE_CMD_CONSTRUCT_H2C_SENT = 2,
- HALMAC_EFUSE_CMD_CONSTRUCT_STATE_NUM = 3,
- HALMAC_EFUSE_CMD_CONSTRUCT_UNDEFINED = 0x7F,
-} HALMAC_EFUSE_CMD_CONSTRUCT_STATE;
-
-typedef enum _HALMAC_CFG_PARA_CMD_CONSTRUCT_STATE {
- HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE = 0,
- HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING = 1,
- HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT = 2,
- HALMAC_CFG_PARA_CMD_CONSTRUCT_NUM = 3,
- HALMAC_CFG_PARA_CMD_CONSTRUCT_UNDEFINED = 0x7F,
-} HALMAC_CFG_PARA_CMD_CONSTRUCT_STATE;
-
-typedef enum _HALMAC_SCAN_CMD_CONSTRUCT_STATE {
- HALMAC_SCAN_CMD_CONSTRUCT_IDLE = 0,
- HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED = 1,
- HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING = 2,
- HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT = 3,
- HALMAC_SCAN_CMD_CONSTRUCT_STATE_NUM = 4,
- HALMAC_SCAN_CMD_CONSTRUCT_UNDEFINED = 0x7F,
-} HALMAC_SCAN_CMD_CONSTRUCT_STATE;
-
-typedef enum _HALMAC_API_STATE {
- HALMAC_API_STATE_INIT = 0,
- HALMAC_API_STATE_HALT = 1,
- HALMAC_API_STATE_UNDEFINED = 0x7F,
-} HALMAC_API_STATE;
-
-typedef struct _HALMAC_EFUSE_STATE_SET {
- HALMAC_EFUSE_CMD_CONSTRUCT_STATE efuse_cmd_construct_state;
- HALMAC_CMD_PROCESS_STATUS process_status;
- u8 fw_return_code;
- u16 seq_num;
-} HALMAC_EFUSE_STATE_SET, *PHALMAC_EFUSE_STATE_SET;
-
-typedef struct _HALMAC_CFG_PARA_STATE_SET {
- HALMAC_CFG_PARA_CMD_CONSTRUCT_STATE cfg_para_cmd_construct_state;
- HALMAC_CMD_PROCESS_STATUS process_status;
- u8 fw_return_code;
- u16 seq_num;
-} HALMAC_CFG_PARA_STATE_SET, *PHALMAC_CFG_PARA_STATE_SET;
-
-typedef struct _HALMAC_SCAN_STATE_SET {
- HALMAC_SCAN_CMD_CONSTRUCT_STATE scan_cmd_construct_state;
- HALMAC_CMD_PROCESS_STATUS process_status;
- u8 fw_return_code;
- u16 seq_num;
-} HALMAC_SCAN_STATE_SET, *PHALMAC_SCAN_STATE_SET;
-
-typedef struct _HALMAC_UPDATE_PACKET_STATE_SET {
- HALMAC_CMD_PROCESS_STATUS process_status;
- u8 fw_return_code;
- u16 seq_num;
-} HALMAC_UPDATE_PACKET_STATE_SET, *PHALMAC_UPDATE_PACKET_STATE_SET;
-
-typedef struct _HALMAC_IQK_STATE_SET {
- HALMAC_CMD_PROCESS_STATUS process_status;
- u8 fw_return_code;
- u16 seq_num;
-} HALMAC_IQK_STATE_SET, *PHALMAC_IQK_STATE_SET;
-
-typedef struct _HALMAC_POWER_TRACKING_STATE_SET {
- HALMAC_CMD_PROCESS_STATUS process_status;
- u8 fw_return_code;
- u16 seq_num;
-} HALMAC_POWER_TRACKING_STATE_SET, *PHALMAC_POWER_TRACKING_STATE_SET;
-
-typedef struct _HALMAC_PSD_STATE_SET {
- HALMAC_CMD_PROCESS_STATUS process_status;
- u16 data_size;
- u16 segment_size;
- u8 *pData;
- u8 fw_return_code;
- u16 seq_num;
-} HALMAC_PSD_STATE_SET, *PHALMAC_PSD_STATE_SET;
-
-typedef struct _HALMAC_STATE {
- HALMAC_EFUSE_STATE_SET efuse_state_set; /* State machine + cmd process status */
- HALMAC_CFG_PARA_STATE_SET cfg_para_state_set; /* State machine + cmd process status */
- HALMAC_SCAN_STATE_SET scan_state_set; /* State machine + cmd process status */
- HALMAC_UPDATE_PACKET_STATE_SET update_packet_set; /* cmd process status */
- HALMAC_IQK_STATE_SET iqk_set; /* cmd process status */
- HALMAC_POWER_TRACKING_STATE_SET power_tracking_set; /* cmd process status */
- HALMAC_PSD_STATE_SET psd_set; /* cmd process status */
- HALMAC_API_STATE api_state; /* Halmac api state */
- HALMAC_MAC_POWER mac_power; /* 0 : power off, 1 : power on*/
- HALMAC_PS_STATE ps_state; /* power saving state */
- HALMAC_DLFW_STATE dlfw_state; /* download FW state */
-} HALMAC_STATE, *PHALMAC_STATE;
-
-typedef struct _HALMAC_VER {
+};
+
+struct halmac_ver {
u8 major_ver;
u8 prototype_ver;
u8 minor_ver;
-} HALMAC_VER, *PHALMAC_VER;
+};
-
-typedef enum _HALMAC_API_ID {
+enum halmac_api_id {
/*stuff, need to be the 1st*/
HALMAC_API_STUFF = 0x0,
/*stuff, need to be the 1st*/
@@ -1524,8 +1400,6 @@ typedef enum _HALMAC_API_ID {
HALMAC_API_DEINIT_INTERFACE_CFG = 0x18,
HALMAC_API_GET_EFUSE_SIZE = 0x19,
HALMAC_API_DUMP_EFUSE_MAP = 0x1A,
- HALMAC_API_WRITE_EFUSE = 0x1B,
- HALMAC_API_READ_EFUSE = 0x1C,
HALMAC_API_GET_LOGICAL_EFUSE_SIZE = 0x1D,
HALMAC_API_DUMP_LOGICAL_EFUSE_MAP = 0x1E,
HALMAC_API_WRITE_LOGICAL_EFUSE = 0x1F,
@@ -1575,341 +1449,904 @@ typedef enum _HALMAC_API_ID {
HALMAC_API_SU_BFEE_ENTRY_DEL = 0x4B,
HALMAC_API_MU_BFER_ENTRY_DEL = 0x4C,
HALMAC_API_MU_BFEE_ENTRY_DEL = 0x4D,
-
HALMAC_API_ADD_CH_INFO = 0x4E,
HALMAC_API_ADD_EXTRA_CH_INFO = 0x4F,
HALMAC_API_CTRL_CH_SWITCH = 0x50,
HALMAC_API_CLEAR_CH_INFO = 0x51,
-
HALMAC_API_SEND_GENERAL_INFO = 0x52,
HALMAC_API_START_IQK = 0x53,
HALMAC_API_CTRL_PWR_TRACKING = 0x54,
HALMAC_API_PSD = 0x55,
HALMAC_API_CFG_TX_AGG_ALIGN = 0x56,
-
HALMAC_API_QUERY_STATE = 0x57,
HALMAC_API_RESET_FEATURE = 0x58,
HALMAC_API_CHECK_FW_STATUS = 0x59,
HALMAC_API_DUMP_FW_DMEM = 0x5A,
HALMAC_API_CFG_MAX_DL_SIZE = 0x5B,
-
HALMAC_API_INIT_OBJ = 0x5C,
HALMAC_API_DEINIT_OBJ = 0x5D,
HALMAC_API_CFG_LA_MODE = 0x5E,
HALMAC_API_GET_HW_VALUE = 0x5F,
HALMAC_API_SET_HW_VALUE = 0x60,
HALMAC_API_CFG_DRV_RSVD_PG_NUM = 0x61,
- HALMAC_API_SWITCH_EFUSE_BANK = 0x62,
HALMAC_API_WRITE_EFUSE_BT = 0x63,
HALMAC_API_DUMP_EFUSE_MAP_BT = 0x64,
+ HALMAC_API_DL_DRV_RSVD_PG = 0x65,
+ HALMAC_API_PCIE_SWITCH = 0x66,
+ HALMAC_API_PHY_CFG = 0x67,
+ HALMAC_API_CFG_RX_FIFO_EXPANDING_MODE = 0x68,
+ HALMAC_API_CFG_CSI_RATE = 0x69,
+ HALMAC_API_P2PPS = 0x6A,
+ HALMAC_API_CFG_TX_ADDR = 0x6B,
+ HALMAC_API_CFG_NET_TYPE = 0x6C,
+ HALMAC_API_CFG_TSF_RESET = 0x6D,
+ HALMAC_API_CFG_BCN_SPACE = 0x6E,
+ HALMAC_API_CFG_BCN_CTRL = 0x6F,
+ HALMAC_API_CFG_SIDEBAND_INT = 0x70,
+ HALMAC_API_REGISTER_API = 0x71,
+ HALMAC_API_FREE_DOWNLOAD_FIRMWARE = 0x72,
+ HALMAC_API_GET_FW_VERSION = 0x73,
+ HALMAC_API_GET_EFUSE_AVAL_SIZE = 0x74,
+ HALMAC_API_CHK_TXDESC = 0x75,
+ HALMAC_API_SDIO_CMD53_4BYTE = 0x76,
+ HALMAC_API_CFG_TRANS_ADDR = 0x77,
+ HALMAC_API_INTF_INTEGRA_TUNING = 0x78,
+ HALMAC_API_TXFIFO_IS_EMPTY = 0x79,
+ HALMAC_API_DOWNLOAD_FLASH = 0x7A,
+ HALMAC_API_READ_FLASH = 0x7B,
+ HALMAC_API_ERASE_FLASH = 0x7C,
+ HALMAC_API_CHECK_FLASH = 0x7D,
+ HALMAC_API_SDIO_HW_INFO = 0x80,
+ HALMAC_API_READ_EFUSE_BT = 0x81,
+ HALMAC_API_CFG_EFUSE_AUTO_CHECK = 0x82,
+ HALMAC_API_CFG_PINMUX_GET_FUNC = 0x83,
+ HALMAC_API_CFG_PINMUX_SET_FUNC = 0x84,
+ HALMAC_API_CFG_PINMUX_FREE_FUNC = 0x85,
+ HALMAC_API_CFG_PINMUX_WL_LED_MODE = 0x86,
+ HALMAC_API_CFG_PINMUX_WL_LED_SW_CTRL = 0x87,
+ HALMAC_API_CFG_PINMUX_SDIO_INT_POLARITY = 0x88,
+ HALMAC_API_CFG_PINMUX_GPIO_MODE = 0x89,
+ HALMAC_API_CFG_PINMUX_GPIO_OUTPUT = 0x90,
+ HALMAC_API_REG_READ_INDIRECT_32 = 0x91,
+ HALMAC_API_REG_SDIO_CMD53_READ_N = 0x92,
+ HALMAC_API_PINMUX_PIN_STATUS = 0x94,
+ HALMAC_API_OFLD_FUNC_CFG = 0x95,
+ HALMAC_API_MASK_LOGICAL_EFUSE = 0x96,
+ HALMAC_API_RX_CUT_AMSDU_CFG = 0x97,
+ HALMAC_API_FW_SNDING = 0x98,
+ HALMAC_API_ENTER_CPU_SLEEP_MODE = 0x99,
+ HALMAC_API_GET_CPU_MODE = 0x9A,
+ HALMAC_API_DRV_FWCTRL = 0x9B,
+ HALMAC_API_EN_REF_AUTOK = 0x9C,
HALMAC_API_MAX
-} HALMAC_API_ID;
-
+};
-typedef struct _HALMAC_API_RECORD {
- HALMAC_API_ID api_array[API_ARRAY_SIZE];
- u8 array_wptr;
-} HALMAC_API_RECORD, *PHALMAC_API_RECORD;
-
-typedef enum _HALMAC_LA_MODE {
+enum halmac_la_mode {
HALMAC_LA_MODE_DISABLE = 0,
HALMAC_LA_MODE_PARTIAL = 1,
HALMAC_LA_MODE_FULL = 2,
HALMAC_LA_MODE_UNDEFINE = 0x7F,
-} HALMAC_LA_MODE;
-
-typedef enum _HALMAC_USB_MODE {
+};
+
+enum halmac_rx_fifo_expanding_mode {
+ HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE = 0,
+ HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK = 1,
+ HALMAC_RX_FIFO_EXPANDING_MODE_2_BLOCK = 2,
+ HALMAC_RX_FIFO_EXPANDING_MODE_3_BLOCK = 3,
+ HALMAC_RX_FIFO_EXPANDING_MODE_4_BLOCK = 4,
+ HALMAC_RX_FIFO_EXPANDING_MODE_UNDEFINE = 0x7F,
+};
+
+enum halmac_sdio_cmd53_4byte_mode {
+ HALMAC_SDIO_CMD53_4BYTE_MODE_DISABLE = 0,
+ HALMAC_SDIO_CMD53_4BYTE_MODE_RW = 1,
+ HALMAC_SDIO_CMD53_4BYTE_MODE_R = 2,
+ HALMAC_SDIO_CMD53_4BYTE_MODE_W = 3,
+ HALMAC_SDIO_CMD53_4BYTE_MODE_UNDEFINE = 0x7F,
+};
+
+enum halmac_usb_mode {
HALMAC_USB_MODE_U2 = 1,
HALMAC_USB_MODE_U3 = 2,
-} HALMAC_USB_MODE;
-
-typedef enum _HALMAC_HW_ID {
- HALMAC_HW_RQPN_MAPPING = 0,
- HALMAC_HW_EFUSE_SIZE = 1,
- HALMAC_HW_EEPROM_SIZE = 2,
- HALMAC_HW_TXFIFO_SIZE = 3,
- HALMAC_HW_RSVD_PG_BNDY = 4,
- HALMAC_HW_CAM_ENTRY_NUM = 5,
- HALMAC_HW_HRPWM = 6,
- HALMAC_HW_HCPWM = 7,
- HALMAC_HW_HRPWM2 = 8,
- HALMAC_HW_HCPWM2 = 9,
- HALMAC_HW_WLAN_EFUSE_AVAILABLE_SIZE = 10,
- HALMAC_HW_TXFF_ALLOCATION = 11,
- HALMAC_HW_USB_MODE = 12,
- HALMAC_HW_SEQ_EN = 13,
- HALMAC_HW_BANDWIDTH = 14,
- HALMAC_HW_CHANNEL = 15,
- HALMAC_HW_PRI_CHANNEL_IDX = 16,
- HALMAC_HW_EN_BB_RF = 17,
- HALMAC_HW_BT_BANK_EFUSE_SIZE = 18,
- HALMAC_HW_BT_BANK1_EFUSE_SIZE = 19,
- HALMAC_HW_BT_BANK2_EFUSE_SIZE = 20,
+};
+
+enum halmac_sdio_tx_format {
+ HALMAC_SDIO_AGG_MODE = 1,
+ HALMAC_SDIO_DUMMY_BLOCK_MODE = 2,
+ HALMAC_SDIO_DUMMY_AUTO_MODE = 3,
+};
+
+enum halmac_hw_id {
+ /* Get HW value */
+ HALMAC_HW_RQPN_MAPPING = 0x00,
+ HALMAC_HW_EFUSE_SIZE = 0x01,
+ HALMAC_HW_EEPROM_SIZE = 0x02,
+ HALMAC_HW_BT_BANK_EFUSE_SIZE = 0x03,
+ HALMAC_HW_BT_BANK1_EFUSE_SIZE = 0x04,
+ HALMAC_HW_BT_BANK2_EFUSE_SIZE = 0x05,
+ HALMAC_HW_TXFIFO_SIZE = 0x06,
+ HALMAC_HW_RXFIFO_SIZE = 0x07,
+ HALMAC_HW_RSVD_PG_BNDY = 0x08,
+ HALMAC_HW_CAM_ENTRY_NUM = 0x09,
+ HALMAC_HW_IC_VERSION = 0x0A,
+ HALMAC_HW_PAGE_SIZE = 0x0B,
+ HALMAC_HW_TX_AGG_ALIGN_SIZE = 0x0C,
+ HALMAC_HW_RX_AGG_ALIGN_SIZE = 0x0D,
+ HALMAC_HW_DRV_INFO_SIZE = 0x0E,
+ HALMAC_HW_TXFF_ALLOCATION = 0x0F,
+ HALMAC_HW_RSVD_EFUSE_SIZE = 0x10,
+ HALMAC_HW_FW_HDR_SIZE = 0x11,
+ HALMAC_HW_TX_DESC_SIZE = 0x12,
+ HALMAC_HW_RX_DESC_SIZE = 0x13,
+ HALMAC_HW_FW_MAX_SIZE = 0x14,
+ HALMAC_HW_ORI_H2C_SIZE = 0x15,
+ HALMAC_HW_RSVD_DRV_PGNUM = 0x16,
+ HALMAC_HW_TX_PAGE_SIZE = 0x17,
+ HALMAC_HW_USB_TXAGG_DESC_NUM = 0x18,
+ HALMAC_HW_WLAN_EFUSE_AVAILABLE_SIZE = 0x19,
+ HALMAC_HW_HIOE_INST_START = 0x1A,
+ HALMAC_HW_HIOE_INST_END = 0x1B,
+ HALMAC_HW_AC_OQT_SIZE = 0x1C,
+ HALMAC_HW_NON_AC_OQT_SIZE = 0x1D,
+ HALMAC_HW_AC_QUEUE_NUM = 0x1E,
+ HALMAC_HW_RQPN_CH_MAPPING = 0x1F,
+ HALMAC_HW_PWR_STATE = 0x20,
+ /* Set HW value */
+ HALMAC_HW_USB_MODE = 0x60,
+ HALMAC_HW_SEQ_EN = 0x61,
+ HALMAC_HW_BANDWIDTH = 0x62,
+ HALMAC_HW_CHANNEL = 0x63,
+ HALMAC_HW_PRI_CHANNEL_IDX = 0x64,
+ HALMAC_HW_EN_BB_RF = 0x65,
+ HALMAC_HW_SDIO_TX_PAGE_THRESHOLD = 0x66,
+ HALMAC_HW_AMPDU_CONFIG = 0x67,
+ HALMAC_HW_RX_SHIFT = 0x68,
+ HALMAC_HW_TXDESC_CHECKSUM = 0x69,
+ HALMAC_HW_RX_CLK_GATE = 0x6A,
+ HALMAC_HW_RXGCK_FIFO = 0x6B,
+ HALMAC_HW_RX_IGNORE = 0x6C,
+ HALMAC_HW_SDIO_TX_FORMAT = 0x6D,
+ HALMAC_HW_FAST_EDCA = 0x6E,
+ HALMAC_HW_LDO25_EN = 0x6F,
+ HALMAC_HW_PCIE_REF_AUTOK = 0x70,
HALMAC_HW_ID_UNDEFINE = 0x7F,
-} HALMAC_HW_ID;
-typedef enum _HALMAC_EFUSE_BANK {
+};
+
+enum halmac_efuse_bank {
HALMAC_EFUSE_BANK_WIFI = 0,
HALMAC_EFUSE_BANK_BT = 1,
HALMAC_EFUSE_BANK_BT_1 = 2,
HALMAC_EFUSE_BANK_BT_2 = 3,
HALMAC_EFUSE_BANK_MAX,
HALMAC_EFUSE_BANK_UNDEFINE = 0X7F,
-} HALMAC_EFUSE_BANK;
-
-typedef struct _HALMAC_TXFF_ALLOCATION {
+};
+
+enum halmac_sdio_spec_ver {
+ HALMAC_SDIO_SPEC_VER_2_00 = 0,
+ HALMAC_SDIO_SPEC_VER_3_00 = 1,
+ HALMAC_SDIO_SPEC_VER_UNDEFINE = 0X7F,
+};
+
+enum halmac_gpio_func {
+ HALMAC_GPIO_FUNC_WL_LED = 0,
+ HALMAC_GPIO_FUNC_SDIO_INT = 1,
+ HALMAC_GPIO_FUNC_SW_IO_0 = 2,
+ HALMAC_GPIO_FUNC_SW_IO_1 = 3,
+ HALMAC_GPIO_FUNC_SW_IO_2 = 4,
+ HALMAC_GPIO_FUNC_SW_IO_3 = 5,
+ HALMAC_GPIO_FUNC_SW_IO_4 = 6,
+ HALMAC_GPIO_FUNC_SW_IO_5 = 7,
+ HALMAC_GPIO_FUNC_SW_IO_6 = 8,
+ HALMAC_GPIO_FUNC_SW_IO_7 = 9,
+ HALMAC_GPIO_FUNC_SW_IO_8 = 10,
+ HALMAC_GPIO_FUNC_SW_IO_9 = 11,
+ HALMAC_GPIO_FUNC_SW_IO_10 = 12,
+ HALMAC_GPIO_FUNC_SW_IO_11 = 13,
+ HALMAC_GPIO_FUNC_SW_IO_12 = 14,
+ HALMAC_GPIO_FUNC_SW_IO_13 = 15,
+ HALMAC_GPIO_FUNC_SW_IO_14 = 16,
+ HALMAC_GPIO_FUNC_SW_IO_15 = 17,
+ HALMAC_GPIO_FUNC_UNDEFINE = 0X7F,
+};
+
+enum halmac_wlled_mode {
+ HALMAC_WLLED_MODE_TRX = 0,
+ HALMAC_WLLED_MODE_TX = 1,
+ HALMAC_WLLED_MODE_RX = 2,
+ HALMAC_WLLED_MODE_SW_CTRL = 3,
+ HALMAC_WLLED_MODE_UNDEFINE = 0X7F,
+};
+
+enum halmac_psf_fcs_chk_thr {
+ HALMAC_PSF_FCS_CHK_THR_1 = 0,
+ HALMAC_PSF_FCS_CHK_THR_4 = 1,
+ HALMAC_PSF_FCS_CHK_THR_8 = 2,
+ HALMAC_PSF_FCS_CHK_THR_12 = 3,
+ HALMAC_PSF_FCS_CHK_THR_16 = 4,
+ HALMAC_PSF_FCS_CHK_THR_20 = 5,
+ HALMAC_PSF_FCS_CHK_THR_24 = 6,
+ HALMAC_PSF_FCS_CHK_THR_28 = 7,
+};
+
+struct halmac_txff_allocation {
u16 tx_fifo_pg_num;
u16 rsvd_pg_num;
u16 rsvd_drv_pg_num;
- u16 ac_q_pg_num;
+ u16 acq_pg_num;
u16 high_queue_pg_num;
u16 low_queue_pg_num;
u16 normal_queue_pg_num;
u16 extra_queue_pg_num;
u16 pub_queue_pg_num;
- u16 rsvd_pg_bndy;
- u16 rsvd_drv_pg_bndy;
- u16 rsvd_h2c_extra_info_pg_bndy;
- u16 rsvd_h2c_queue_pg_bndy;
- u16 rsvd_cpu_instr_pg_bndy;
- u16 rsvd_fw_txbuff_pg_bndy;
- HALMAC_LA_MODE la_mode;
-} HALMAC_TXFF_ALLOCATION, *PHALMAC_TXFF_ALLOCATION;
-
-typedef struct _HALMAC_RQPN_MAP {
- HALMAC_DMA_MAPPING dma_map_vo;
- HALMAC_DMA_MAPPING dma_map_vi;
- HALMAC_DMA_MAPPING dma_map_be;
- HALMAC_DMA_MAPPING dma_map_bk;
- HALMAC_DMA_MAPPING dma_map_mg;
- HALMAC_DMA_MAPPING dma_map_hi;
-} HALMAC_RQPN_MAP, *PHALMAC_RQPN_MAP;
-
-/* Hal mac adapter */
-typedef struct _HALMAC_ADAPTER {
- HALMAC_DMA_MAPPING halmac_ptcl_queue[HALMAC_PTCL_QUEUE_NUM]; /* Dma mapping of protocol queues */
- HALMAC_FWLPS_OPTION fwlps_option; /* low power state option */
- HALMAC_WLAN_ADDR pHal_mac_addr[2]; /* mac address information, suppot 2 ports */
- HALMAC_WLAN_ADDR pHal_bss_addr[2]; /* bss address information, suppot 2 ports */
- HALMAC_MUTEX h2c_seq_mutex; /* Protect h2c_packet_seq packet*/
- HALMAC_MUTEX EfuseMutex; /* Protect Efuse map memory of halmac_adapter */
- HALMAC_CONFIG_PARA_INFO config_para_info;
- HALMAC_CS_INFO ch_sw_info;
- HALMAC_EVENT_TRIGGER event_trigger;
- HALMAC_HW_CONFIG_INFO hw_config_info; /* HW related information */
- HALMAC_SDIO_FREE_SPACE sdio_free_space;
- HALMAC_SND_INFO snd_info;
- VOID *pHalAdapter_backup; /* Backup HalAdapter address */
- VOID *pDriver_adapter; /* Driver or FW adapter address. Do not write this memory*/
- u8 *pHalEfuse_map;
- VOID *pHalmac_api; /* Record function pointer of halmac api */
- PHALMAC_PLATFORM_API pHalmac_platform_api; /* Record function pointer of platform api */
- u32 efuse_end; /* Record efuse used memory */
- u32 h2c_buf_free_space;
- u32 h2c_buff_size;
- u32 max_download_size;
- HALMAC_CHIP_ID chip_id; /* Chip ID, 8822B, 8821C... */
- HALMAC_CHIP_VER chip_version; /* A cut, B cut... */
- HALMAC_FW_VERSION fw_version;
- HALMAC_STATE halmac_state;
- HALMAC_INTERFACE halmac_interface; /* Interface information, get from driver */
- HALMAC_TRX_MODE trx_mode; /* Noraml, WMM, P2P, LoopBack... */
- HALMAC_TXFF_ALLOCATION txff_allocation;
- u8 h2c_packet_seq; /* current h2c packet sequence number */
- u16 ack_h2c_packet_seq; /*the acked h2c packet sequence number */
- u8 hal_efuse_map_valid;
- u8 efuse_segment_size;
- u8 rpwm_record; /* record rpwm value */
- u8 low_clk; /*LPS 32K or IPS 32K*/
- u8 halmac_bulkout_num; /* USB bulkout num */
- HALMAC_API_RECORD api_record; /* API record */
- u8 gen_info_valid;
- HALMAC_GENERAL_INFO general_info;
-#if HALMAC_PLATFORM_TESTPROGRAM
- HALMAC_TXAGG_BUFF_INFO halmac_tx_buf_info[4];
- HALMAC_MUTEX agg_buff_mutex; /*used for tx_agg_buffer */
+ u16 rsvd_boundary;
+ u16 rsvd_drv_addr;
+ u16 rsvd_h2c_info_addr;
+ u16 rsvd_h2c_sta_info_addr;
+ u16 rsvd_h2cq_addr;
+ u16 rsvd_cpu_instr_addr;
+ u16 rsvd_fw_txbuf_addr;
+ u16 rsvd_csibuf_addr;
+ enum halmac_la_mode la_mode;
+ enum halmac_rx_fifo_expanding_mode rx_fifo_exp_mode;
+};
+
+struct halmac_rqpn_map {
+ enum halmac_dma_mapping dma_map_vo;
+ enum halmac_dma_mapping dma_map_vi;
+ enum halmac_dma_mapping dma_map_be;
+ enum halmac_dma_mapping dma_map_bk;
+ enum halmac_dma_mapping dma_map_mg;
+ enum halmac_dma_mapping dma_map_hi;
+};
+
+struct halmac_rqpn_ch_map {
+ enum halmac_dma_ch dma_map_vo;
+ enum halmac_dma_ch dma_map_vi;
+ enum halmac_dma_ch dma_map_be;
+ enum halmac_dma_ch dma_map_bk;
+ enum halmac_dma_ch dma_map_mg;
+ enum halmac_dma_ch dma_map_hi;
+};
+
+struct halmac_security_setting {
+ u8 tx_encryption;
+ u8 rx_decryption;
+ u8 bip_enable;
+ u8 compare_keyid;
+};
+
+struct halmac_cam_entry_info {
+ enum hal_security_type security_type;
+ u32 key[4];
+ u32 key_ext[4];
+ u8 mac_address[6];
+ u8 unicast;
+ u8 key_id;
+ u8 valid;
+};
+
+struct halmac_cam_entry_format {
+ u16 key_id : 2;
+ u16 type : 3;
+ u16 mic : 1;
+ u16 grp : 1;
+ u16 spp_mode : 1;
+ u16 rpt_md : 1;
+ u16 ext_sectype : 1;
+ u16 mgnt : 1;
+ u16 rsvd1 : 4;
+ u16 valid : 1;
+ u8 mac_address[6];
+ u32 key[4];
+ u32 rsvd[2];
+};
+
+struct halmac_tx_page_threshold_info {
+ u32 threshold;
+ enum halmac_dma_mapping dma_queue_sel;
+ u8 enable;
+};
+
+struct halmac_ampdu_config {
u8 max_agg_num;
- u8 send_bcn_reg_cr_backup;
+ u8 max_len_en;
+ u32 ht_max_len;
+ u32 vht_max_len;
+};
+
+struct halmac_rqpn {
+ enum halmac_trx_mode mode;
+ enum halmac_dma_mapping dma_map_vo;
+ enum halmac_dma_mapping dma_map_vi;
+ enum halmac_dma_mapping dma_map_be;
+ enum halmac_dma_mapping dma_map_bk;
+ enum halmac_dma_mapping dma_map_mg;
+ enum halmac_dma_mapping dma_map_hi;
+};
+
+struct halmac_ch_mapping {
+ enum halmac_trx_mode mode;
+ enum halmac_dma_ch dma_map_vo;
+ enum halmac_dma_ch dma_map_vi;
+ enum halmac_dma_ch dma_map_be;
+ enum halmac_dma_ch dma_map_bk;
+ enum halmac_dma_ch dma_map_mg;
+ enum halmac_dma_ch dma_map_hi;
+};
+
+struct halmac_pg_num {
+ enum halmac_trx_mode mode;
+ u16 hq_num;
+ u16 nq_num;
+ u16 lq_num;
+ u16 exq_num;
+ u16 gap_num;/*used for loopback mode*/
+};
+
+struct halmac_ch_pg_num {
+ enum halmac_trx_mode mode;
+ u16 ch_num[HALMAC_TXDESC_DMA_CH16 + 1];
+ u16 gap_num;
+};
+
+struct halmac_intf_phy_para {
+ u16 offset;
+ u16 value;
+ u16 ip_sel;
+ u16 cut;
+ u16 plaform;
+};
+
+struct halmac_iqk_para {
+ u8 clear;
+ u8 segment_iqk;
+};
+
+struct halmac_txdesc_ie_param {
+ u8 *start_offset;
+ u8 *end_offset;
+ u8 *ie_offset;
+ u8 *ie_exist;
+};
+
+struct halmac_sdio_hw_info {
+ enum halmac_sdio_spec_ver spec_ver;
+ u32 clock_speed;
+ u8 io_hi_speed_flag; /* Halmac internal use */
+ enum halmac_sdio_tx_format tx_addr_format;
+ u16 block_size;
+ u8 tx_seq;
+ u8 io_indir_flag; /* Halmac internal use */
+};
+
+struct halmac_edca_para {
+ u8 aifs;
+ u8 cw;
+ u16 txop_limit;
+};
+
+struct halmac_mac_rx_ignore_cfg {
+ u8 hdr_chk_en;
+ u8 fcs_chk_en;
+ enum halmac_psf_fcs_chk_thr fcs_chk_thr;
+};
+
+struct halmac_pinmux_info {
+ /* byte0 */
+ u8 wl_led:1;
+ u8 sdio_int:1;
+ u8 rsvd1:6;
+ /* byte1 */
+ u8 sw_io_0:1;
+ u8 sw_io_1:1;
+ u8 sw_io_2:1;
+ u8 sw_io_3:1;
+ u8 sw_io_4:1;
+ u8 sw_io_5:1;
+ u8 sw_io_6:1;
+ u8 sw_io_7:1;
+ /* byte2 */
+ u8 sw_io_8:1;
+ u8 sw_io_9:1;
+ u8 sw_io_10:1;
+ u8 sw_io_11:1;
+ u8 sw_io_12:1;
+ u8 sw_io_13:1;
+ u8 sw_io_14:1;
+ u8 sw_io_15:1;
+};
+
+struct halmac_ofld_func_info {
+ u32 halmac_malloc_max_sz;
+ u32 rsvd_pg_drv_buf_max_sz;
+};
+
+struct halmac_pltfm_cfg_info {
+ u32 malloc_size;
+ u32 rsvd_pg_size;
+};
+
+struct halmac_su_snding_info {
+ u8 su0_en;
+ u8 *su0_ndpa_pkt;
+ u32 su0_pkt_sz;
+};
+
+struct halmac_mu_snding_info {
+ u8 tmp;
+};
+
+struct halmac_h2c_info {
+ u32 buf_fs;
+ u32 buf_size;
+ u8 seq_num;
+};
+
+struct halmac_adapter {
+ enum halmac_dma_mapping pq_map[HALMAC_PQ_MAP_NUM];
+ enum halmac_dma_ch ch_map[HALMAC_PQ_MAP_NUM];
+ HALMAC_MUTEX h2c_seq_mutex;
+ HALMAC_MUTEX efuse_mutex;
+ HALMAC_MUTEX sdio_indir_mutex; /*Protect sdio indirect access */
+ struct halmac_cfg_param_info cfg_param_info;
+ struct halmac_ch_sw_info ch_sw_info;
+ struct halmac_event_trigger evnt;
+ struct halmac_hw_cfg_info hw_cfg_info;
+ struct halmac_sdio_free_space sdio_fs;
+ struct halmac_api_registry api_registry;
+ struct halmac_pinmux_info pinmux_info;
+ struct halmac_pltfm_cfg_info pltfm_info;
+ struct halmac_h2c_info h2c_info;
+ void *drv_adapter;
+ u8 *efuse_map;
+ void *halmac_api;
+ struct halmac_platform_api *pltfm_api;
+ u32 efuse_end;
+ u32 dlfw_pkt_size;
+ enum halmac_chip_id chip_id;
+ enum halmac_chip_ver chip_ver;
+ struct halmac_fw_version fw_ver;
+ struct halmac_state halmac_state;
+ enum halmac_interface intf;
+ enum halmac_trx_mode trx_mode;
+ struct halmac_txff_allocation txff_alloc;
+ u8 efuse_map_valid;
+ u8 efuse_seg_size;
+ u8 rpwm;
+ u8 bulkout_num;
+ u8 drv_info_size;
+ enum halmac_sdio_cmd53_4byte_mode sdio_cmd53_4byte;
+ struct halmac_sdio_hw_info sdio_hw_info;
+ u8 tx_desc_transfer;
+ u8 tx_desc_checksum;
+ u8 efuse_auto_check_en;
+ u8 pcie_refautok_en;
+ u8 pwr_off_flow_flag;
+
+#if HALMAC_PLATFORM_TESTPROGRAM
+ struct halmisc_adapter *halmisc_adapter;
#endif
-} HALMAC_ADAPTER, *PHALMAC_ADAPTER;
-
-
-/* Fuction pointer of Hal mac API */
-typedef struct _HALMAC_API {
- HALMAC_RET_STATUS (*halmac_mac_power_switch)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_MAC_POWER halmac_power);
- HALMAC_RET_STATUS (*halmac_download_firmware)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHamacl_fw, u32 halmac_fw_size);
- HALMAC_RET_STATUS (*halmac_get_fw_version)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_FW_VERSION pFw_version);
- HALMAC_RET_STATUS (*halmac_cfg_mac_addr)(PHALMAC_ADAPTER pHalmac_adapter, u8 halmac_port, PHALMAC_WLAN_ADDR pHal_address);
- HALMAC_RET_STATUS (*halmac_cfg_bssid)(PHALMAC_ADAPTER pHalmac_adapter, u8 halmac_port, PHALMAC_WLAN_ADDR pHal_address);
- HALMAC_RET_STATUS (*halmac_cfg_multicast_addr)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_WLAN_ADDR pHal_address);
- HALMAC_RET_STATUS (*halmac_pre_init_system_cfg)(PHALMAC_ADAPTER pHalmac_adapter);
- HALMAC_RET_STATUS (*halmac_init_system_cfg)(PHALMAC_ADAPTER pHalmac_adapter);
- HALMAC_RET_STATUS (*halmac_init_trx_cfg)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_TRX_MODE Mode);
- HALMAC_RET_STATUS (*halmac_init_h2c)(PHALMAC_ADAPTER pHalmac_adapter);
- HALMAC_RET_STATUS (*halmac_cfg_rx_aggregation)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_RXAGG_CFG phalmac_rxagg_cfg);
- HALMAC_RET_STATUS (*halmac_init_protocol_cfg)(PHALMAC_ADAPTER pHalmac_adapter);
- HALMAC_RET_STATUS (*halmac_init_edca_cfg)(PHALMAC_ADAPTER pHalmac_adapter);
- HALMAC_RET_STATUS (*halmac_cfg_operation_mode)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_WIRELESS_MODE wireless_mode);
- HALMAC_RET_STATUS (*halmac_cfg_ch_bw)(PHALMAC_ADAPTER pHalmac_adapter, u8 channel, HALMAC_PRI_CH_IDX pri_ch_idx, HALMAC_BW bw);
- HALMAC_RET_STATUS (*halmac_cfg_bw)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_BW bw);
- HALMAC_RET_STATUS (*halmac_init_wmac_cfg)(PHALMAC_ADAPTER pHalmac_adapter);
- HALMAC_RET_STATUS (*halmac_init_mac_cfg)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_TRX_MODE Mode);
- HALMAC_RET_STATUS (*halmac_init_sdio_cfg)(PHALMAC_ADAPTER pHalmac_adapter);
- HALMAC_RET_STATUS (*halmac_init_usb_cfg)(PHALMAC_ADAPTER pHalmac_adapter);
- HALMAC_RET_STATUS (*halmac_init_pcie_cfg)(PHALMAC_ADAPTER pHalmac_adapter);
- HALMAC_RET_STATUS (*halmac_init_interface_cfg)(PHALMAC_ADAPTER pHalmac_adapter);
- HALMAC_RET_STATUS (*halmac_deinit_sdio_cfg)(PHALMAC_ADAPTER pHalmac_adapter);
- HALMAC_RET_STATUS (*halmac_deinit_usb_cfg)(PHALMAC_ADAPTER pHalmac_adapter);
- HALMAC_RET_STATUS (*halmac_deinit_pcie_cfg)(PHALMAC_ADAPTER pHalmac_adapter);
- HALMAC_RET_STATUS (*halmac_deinit_interface_cfg)(PHALMAC_ADAPTER pHalmac_adapter);
- HALMAC_RET_STATUS (*halmac_get_efuse_size)(PHALMAC_ADAPTER pHalmac_adapter, u32 *halmac_size);
- HALMAC_RET_STATUS (*halmac_dump_efuse_map)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_EFUSE_READ_CFG cfg);
- HALMAC_RET_STATUS (*halmac_dump_efuse_map_bt)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_EFUSE_BANK halmac_efues_bank, u32 bt_efuse_map_size, u8 *pBT_efuse_map);
- HALMAC_RET_STATUS (*halmac_write_efuse)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 halmac_value);
- HALMAC_RET_STATUS (*halmac_read_efuse)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 *pValue);
- HALMAC_RET_STATUS (*halmac_switch_efuse_bank)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_EFUSE_BANK halmac_efues_bank);
- HALMAC_RET_STATUS (*halmac_write_efuse_bt)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 halmac_value, HALMAC_EFUSE_BANK halmac_efues_bank);
- HALMAC_RET_STATUS (*halmac_get_logical_efuse_size)(PHALMAC_ADAPTER pHalmac_adapter, u32 *halmac_size);
- HALMAC_RET_STATUS (*halmac_dump_logical_efuse_map)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_EFUSE_READ_CFG cfg);
- HALMAC_RET_STATUS (*halmac_write_logical_efuse)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 halmac_value);
- HALMAC_RET_STATUS (*halmac_read_logical_efuse)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 *pValue);
- HALMAC_RET_STATUS (*halmac_pg_efuse_by_map)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_PG_EFUSE_INFO pPg_efuse_info, HALMAC_EFUSE_READ_CFG cfg);
- HALMAC_RET_STATUS (*halmac_get_c2h_info)(PHALMAC_ADAPTER pHalmac_adapter, u8 *halmac_buf, u32 halmac_size);
- HALMAC_RET_STATUS (*halmac_cfg_fwlps_option)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_FWLPS_OPTION pLps_option);
- HALMAC_RET_STATUS (*halmac_cfg_fwips_option)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_FWIPS_OPTION pIps_option);
- HALMAC_RET_STATUS (*halmac_enter_wowlan)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_WOWLAN_OPTION pWowlan_option);
- HALMAC_RET_STATUS (*halmac_leave_wowlan)(PHALMAC_ADAPTER pHalmac_adapter);
- HALMAC_RET_STATUS (*halmac_enter_ps)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_PS_STATE ps_state);
- HALMAC_RET_STATUS (*halmac_leave_ps)(PHALMAC_ADAPTER pHalmac_adapter);
- HALMAC_RET_STATUS (*halmac_h2c_lb)(PHALMAC_ADAPTER pHalmac_adapter);
- HALMAC_RET_STATUS (*halmac_debug)(PHALMAC_ADAPTER pHalmac_adapter);
- HALMAC_RET_STATUS (*halmac_cfg_parameter)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_PHY_PARAMETER_INFO para_info, u8 full_fifo);
- HALMAC_RET_STATUS (*halmac_update_packet)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_PACKET_ID pkt_id, u8 *pkt, u32 pkt_size);
- HALMAC_RET_STATUS (*halmac_bcn_ie_filter)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_BCN_IE_INFO pBcn_ie_info);
- u8 (*halmac_reg_read_8)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset);
- HALMAC_RET_STATUS (*halmac_reg_write_8)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 halmac_data);
- u16 (*halmac_reg_read_16)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset);
- HALMAC_RET_STATUS (*halmac_reg_write_16)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u16 halmac_data);
- u32 (*halmac_reg_read_32)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset);
- HALMAC_RET_STATUS (*halmac_reg_write_32)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u32 halmac_data);
- HALMAC_RET_STATUS (*halmac_tx_allowed_sdio)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHalmac_buf, u32 halmac_size);
- HALMAC_RET_STATUS (*halmac_set_bulkout_num)(PHALMAC_ADAPTER pHalmac_adapter, u8 bulkout_num);
- HALMAC_RET_STATUS (*halmac_get_sdio_tx_addr)(PHALMAC_ADAPTER pHalmac_adapter, u8 *halmac_buf, u32 halmac_size, u32 *pcmd53_addr);
- HALMAC_RET_STATUS (*halmac_get_usb_bulkout_id)(PHALMAC_ADAPTER pHalmac_adapter, u8 *halmac_buf, u32 halmac_size, u8 *bulkout_id);
- HALMAC_RET_STATUS (*halmac_timer_2s)(PHALMAC_ADAPTER pHalmac_adapter);
- HALMAC_RET_STATUS (*halmac_fill_txdesc_checksum)(PHALMAC_ADAPTER pHalmac_adapter, u8 *cur_desc);
- HALMAC_RET_STATUS (*halmac_update_datapack)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_DATA_TYPE halmac_data_type, PHALMAC_PHY_PARAMETER_INFO para_info);
- HALMAC_RET_STATUS (*halmac_run_datapack)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_DATA_TYPE halmac_data_type);
- HALMAC_RET_STATUS (*halmac_cfg_drv_info)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_DRV_INFO halmac_drv_info);
- HALMAC_RET_STATUS (*halmac_send_bt_coex)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBt_buf, u32 bt_size, u8 ack);
- HALMAC_RET_STATUS (*halmac_verify_platform_api)(PHALMAC_ADAPTER pHalmac_adapte);
- u32 (*halmac_get_fifo_size)(PHALMAC_ADAPTER pHalmac_adapter, HAL_FIFO_SEL halmac_fifo_sel);
- HALMAC_RET_STATUS (*halmac_dump_fifo)(PHALMAC_ADAPTER pHalmac_adapter, HAL_FIFO_SEL halmac_fifo_sel, u8 *pFifo_map, u32 halmac_fifo_dump_size);
- HALMAC_RET_STATUS (*halmac_cfg_txbf)(PHALMAC_ADAPTER pHalmac_adapter, u8 userid, HALMAC_BW bw, u8 txbf_en);
- HALMAC_RET_STATUS (*halmac_cfg_mumimo)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_CFG_MUMIMO_PARA pCfgmu);
- HALMAC_RET_STATUS (*halmac_cfg_sounding)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_SND_ROLE role, HALMAC_DATA_RATE datarate);
- HALMAC_RET_STATUS (*halmac_del_sounding)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_SND_ROLE role);
- HALMAC_RET_STATUS (*halmac_su_bfer_entry_init)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_SU_BFER_INIT_PARA pSu_bfer_init);
- HALMAC_RET_STATUS (*halmac_su_bfee_entry_init)(PHALMAC_ADAPTER pHalmac_adapter, u8 userid, u16 paid);
- HALMAC_RET_STATUS (*halmac_mu_bfer_entry_init)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_MU_BFER_INIT_PARA pMu_bfer_init);
- HALMAC_RET_STATUS (*halmac_mu_bfee_entry_init)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_MU_BFEE_INIT_PARA pMu_bfee_init);
- HALMAC_RET_STATUS (*halmac_su_bfer_entry_del)(PHALMAC_ADAPTER pHalmac_adapter, u8 userid);
- HALMAC_RET_STATUS (*halmac_su_bfee_entry_del)(PHALMAC_ADAPTER pHalmac_adapter, u8 userid);
- HALMAC_RET_STATUS (*halmac_mu_bfer_entry_del)(PHALMAC_ADAPTER pHalmac_adapter);
- HALMAC_RET_STATUS (*halmac_mu_bfee_entry_del)(PHALMAC_ADAPTER pHalmac_adapter, u8 userid);
- HALMAC_RET_STATUS (*halmac_add_ch_info)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_CH_INFO pCh_info);
- HALMAC_RET_STATUS (*halmac_add_extra_ch_info)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_CH_EXTRA_INFO pCh_extra_info);
- HALMAC_RET_STATUS (*halmac_ctrl_ch_switch)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_CH_SWITCH_OPTION pCs_option);
- HALMAC_RET_STATUS (*halmac_clear_ch_info)(PHALMAC_ADAPTER pHalmac_adapter);
- HALMAC_RET_STATUS (*halmac_send_general_info)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_GENERAL_INFO pgGeneral_info);
- HALMAC_RET_STATUS (*halmac_start_iqk)(PHALMAC_ADAPTER pHalmac_adapter, u8 clear);
- HALMAC_RET_STATUS (*halmac_ctrl_pwr_tracking)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_PWR_TRACKING_OPTION pPwr_tracking_opt);
- HALMAC_RET_STATUS (*halmac_psd)(PHALMAC_ADAPTER pHalmac_adapter, u16 start_psd, u16 end_psd);
- HALMAC_RET_STATUS (*halmac_cfg_tx_agg_align)(PHALMAC_ADAPTER pHalmac_adapter, u8 enable, u16 align_size);
- HALMAC_RET_STATUS (*halmac_query_status)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_FEATURE_ID feature_id, HALMAC_CMD_PROCESS_STATUS *pProcess_status, u8 *data, u32 *size);
- HALMAC_RET_STATUS (*halmac_reset_feature)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_FEATURE_ID feature_id);
- HALMAC_RET_STATUS (*halmac_check_fw_status)(PHALMAC_ADAPTER pHalmac_adapter, u8 *fw_status);
- HALMAC_RET_STATUS (*halmac_dump_fw_dmem)(PHALMAC_ADAPTER pHalmac_adapter, u8 *dmem, u32 *size);
- HALMAC_RET_STATUS (*halmac_cfg_max_dl_size)(PHALMAC_ADAPTER pHalmac_adapter, u32 size);
- HALMAC_RET_STATUS (*halmac_cfg_la_mode)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_LA_MODE la_mode);
- HALMAC_RET_STATUS (*halmac_get_hw_value)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_HW_ID hw_id, VOID *pvalue);
- HALMAC_RET_STATUS (*halmac_set_hw_value)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_HW_ID hw_id, VOID *pvalue);
- HALMAC_RET_STATUS (*halmac_cfg_drv_rsvd_pg_num)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_DRV_RSVD_PG_NUM pg_num);
- HALMAC_RET_STATUS (*halmac_get_chip_version)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_VER *version);
- HALMAC_RET_STATUS (*halmac_chk_txdesc)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHalmac_buf, u32 halmac_size);
+};
+
+struct halmac_api {
+ enum halmac_ret_status
+ (*halmac_register_api)(struct halmac_adapter *adapter,
+ struct halmac_api_registry *registry);
+ enum halmac_ret_status
+ (*halmac_mac_power_switch)(struct halmac_adapter *adapter,
+ enum halmac_mac_power pwr);
+ enum halmac_ret_status
+ (*halmac_download_firmware)(struct halmac_adapter *adapter, u8 *fw_bin,
+ u32 size);
+ enum halmac_ret_status
+ (*halmac_free_download_firmware)(struct halmac_adapter *adapter,
+ enum halmac_dlfw_mem mem_sel,
+ u8 *fw_bin, u32 size);
+ enum halmac_ret_status
+ (*halmac_get_fw_version)(struct halmac_adapter *adapter,
+ struct halmac_fw_version *ver);
+ enum halmac_ret_status
+ (*halmac_cfg_mac_addr)(struct halmac_adapter *adapter,
+ u8 port, union halmac_wlan_addr *addr);
+ enum halmac_ret_status
+ (*halmac_cfg_bssid)(struct halmac_adapter *adapter, u8 port,
+ union halmac_wlan_addr *addr);
+ enum halmac_ret_status
+ (*halmac_cfg_multicast_addr)(struct halmac_adapter *adapter,
+ union halmac_wlan_addr *addr);
+ enum halmac_ret_status
+ (*halmac_pre_init_system_cfg)(struct halmac_adapter *adapter);
+ enum halmac_ret_status
+ (*halmac_init_system_cfg)(struct halmac_adapter *adapter);
+ enum halmac_ret_status
+ (*halmac_init_trx_cfg)(struct halmac_adapter *adapter,
+ enum halmac_trx_mode mode);
+ enum halmac_ret_status
+ (*halmac_init_h2c)(struct halmac_adapter *adapter);
+ enum halmac_ret_status
+ (*halmac_cfg_rx_aggregation)(struct halmac_adapter *adapter,
+ struct halmac_rxagg_cfg *cfg);
+ enum halmac_ret_status
+ (*halmac_init_protocol_cfg)(struct halmac_adapter *adapter);
+ enum halmac_ret_status
+ (*halmac_init_edca_cfg)(struct halmac_adapter *adapter);
+ enum halmac_ret_status
+ (*halmac_cfg_operation_mode)(struct halmac_adapter *adapter,
+ enum halmac_wireless_mode mode);
+ enum halmac_ret_status
+ (*halmac_cfg_ch_bw)(struct halmac_adapter *adapter, u8 ch,
+ enum halmac_pri_ch_idx idx, enum halmac_bw bw);
+ enum halmac_ret_status
+ (*halmac_cfg_bw)(struct halmac_adapter *adapter, enum halmac_bw bw);
+ enum halmac_ret_status
+ (*halmac_init_wmac_cfg)(struct halmac_adapter *adapter);
+ enum halmac_ret_status
+ (*halmac_init_mac_cfg)(struct halmac_adapter *adapter,
+ enum halmac_trx_mode mode);
+ enum halmac_ret_status
+ (*halmac_init_interface_cfg)(struct halmac_adapter *adapter);
+ enum halmac_ret_status
+ (*halmac_deinit_interface_cfg)(struct halmac_adapter *adapter);
+ enum halmac_ret_status
+ (*halmac_init_sdio_cfg)(struct halmac_adapter *adapter);
+ enum halmac_ret_status
+ (*halmac_init_usb_cfg)(struct halmac_adapter *adapter);
+ enum halmac_ret_status
+ (*halmac_init_pcie_cfg)(struct halmac_adapter *adapter);
+ enum halmac_ret_status
+ (*halmac_deinit_sdio_cfg)(struct halmac_adapter *adapter);
+ enum halmac_ret_status
+ (*halmac_deinit_usb_cfg)(struct halmac_adapter *adapter);
+ enum halmac_ret_status
+ (*halmac_deinit_pcie_cfg)(struct halmac_adapter *adapter);
+ enum halmac_ret_status
+ (*halmac_get_efuse_size)(struct halmac_adapter *adapter, u32 *size);
+ enum halmac_ret_status
+ (*halmac_get_efuse_available_size)(struct halmac_adapter *adapter,
+ u32 *size);
+ enum halmac_ret_status
+ (*halmac_dump_efuse_map)(struct halmac_adapter *adapter,
+ enum halmac_efuse_read_cfg cfg);
+ enum halmac_ret_status
+ (*halmac_dump_efuse_map_bt)(struct halmac_adapter *adapter,
+ enum halmac_efuse_bank bank, u32 size,
+ u8 *map);
+ enum halmac_ret_status
+ (*halmac_write_efuse_bt)(struct halmac_adapter *adapter, u32 offset,
+ u8 value, enum halmac_efuse_bank bank);
+ enum halmac_ret_status
+ (*halmac_read_efuse_bt)(struct halmac_adapter *adapter, u32 offset,
+ u8 *value, enum halmac_efuse_bank bank);
+ enum halmac_ret_status
+ (*halmac_cfg_efuse_auto_check)(struct halmac_adapter *adapter,
+ u8 enable);
+ enum halmac_ret_status
+ (*halmac_get_logical_efuse_size)(struct halmac_adapter *adapter,
+ u32 *size);
+ enum halmac_ret_status
+ (*halmac_dump_logical_efuse_map)(struct halmac_adapter *adapter,
+ enum halmac_efuse_read_cfg cfg);
+ enum halmac_ret_status
+ (*halmac_write_logical_efuse)(struct halmac_adapter *adapter,
+ u32 offset, u8 value);
+ enum halmac_ret_status
+ (*halmac_read_logical_efuse)(struct halmac_adapter *adapter, u32 offset,
+ u8 *value);
+ enum halmac_ret_status
+ (*halmac_pg_efuse_by_map)(struct halmac_adapter *adapter,
+ struct halmac_pg_efuse_info *info,
+ enum halmac_efuse_read_cfg cfg);
+ enum halmac_ret_status
+ (*halmac_mask_logical_efuse)(struct halmac_adapter *adapter,
+ struct halmac_pg_efuse_info *info);
+ enum halmac_ret_status
+ (*halmac_get_c2h_info)(struct halmac_adapter *adapter, u8 *buf,
+ u32 size);
+ enum halmac_ret_status
+ (*halmac_h2c_lb)(struct halmac_adapter *adapter);
+ enum halmac_ret_status
+ (*halmac_debug)(struct halmac_adapter *adapter);
+ enum halmac_ret_status
+ (*halmac_cfg_parameter)(struct halmac_adapter *adapter,
+ struct halmac_phy_parameter_info *info,
+ u8 full_fifo);
+ enum halmac_ret_status
+ (*halmac_update_packet)(struct halmac_adapter *adapter,
+ enum halmac_packet_id pkt_id, u8 *pkt,
+ u32 size);
+ enum halmac_ret_status
+ (*halmac_bcn_ie_filter)(struct halmac_adapter *adapter,
+ struct halmac_bcn_ie_info *info);
+ u8
+ (*halmac_reg_read_8)(struct halmac_adapter *adapter, u32 offset);
+ enum halmac_ret_status
+ (*halmac_reg_write_8)(struct halmac_adapter *adapter, u32 offset,
+ u8 value);
+ u16
+ (*halmac_reg_read_16)(struct halmac_adapter *adapter, u32 offset);
+ enum halmac_ret_status
+ (*halmac_reg_write_16)(struct halmac_adapter *adapter, u32 offset,
+ u16 value);
+ u32
+ (*halmac_reg_read_32)(struct halmac_adapter *adapter, u32 offset);
+ enum halmac_ret_status
+ (*halmac_reg_write_32)(struct halmac_adapter *adapter, u32 offset,
+ u32 value);
+ u32
+ (*halmac_reg_read_indirect_32)(struct halmac_adapter *adapter,
+ u32 offset);
+ enum halmac_ret_status
+ (*halmac_reg_sdio_cmd53_read_n)(struct halmac_adapter *adapter,
+ u32 offset, u32 size, u8 *value);
+ enum halmac_ret_status
+ (*halmac_tx_allowed_sdio)(struct halmac_adapter *adapter, u8 *buf,
+ u32 size);
+ enum halmac_ret_status
+ (*halmac_set_bulkout_num)(struct halmac_adapter *adapter, u8 num);
+ enum halmac_ret_status
+ (*halmac_get_sdio_tx_addr)(struct halmac_adapter *adapter, u8 *buf,
+ u32 size, u32 *cmd53_addr);
+ enum halmac_ret_status
+ (*halmac_get_usb_bulkout_id)(struct halmac_adapter *adapter, u8 *buf,
+ u32 size, u8 *id);
+ enum halmac_ret_status
+ (*halmac_fill_txdesc_checksum)(struct halmac_adapter *adapter,
+ u8 *txdesc);
+ enum halmac_ret_status
+ (*halmac_update_datapack)(struct halmac_adapter *adapter,
+ enum halmac_data_type data_type,
+ struct halmac_phy_parameter_info *info);
+ enum halmac_ret_status
+ (*halmac_run_datapack)(struct halmac_adapter *adapter,
+ enum halmac_data_type data_type);
+ enum halmac_ret_status
+ (*halmac_cfg_drv_info)(struct halmac_adapter *adapter,
+ enum halmac_drv_info drv_info);
+ enum halmac_ret_status
+ (*halmac_send_bt_coex)(struct halmac_adapter *adapter, u8 *buf,
+ u32 size, u8 ack);
+ enum halmac_ret_status
+ (*halmac_verify_platform_api)(struct halmac_adapter *adapter);
+ u32
+ (*halmac_get_fifo_size)(struct halmac_adapter *adapter,
+ enum hal_fifo_sel sel);
+ enum halmac_ret_status
+ (*halmac_dump_fifo)(struct halmac_adapter *adapter,
+ enum hal_fifo_sel sel, u32 start_addr, u32 size,
+ u8 *data);
+ enum halmac_ret_status
+ (*halmac_cfg_txbf)(struct halmac_adapter *adapter, u8 userid,
+ enum halmac_bw bw, u8 txbf_en);
+ enum halmac_ret_status
+ (*halmac_cfg_mumimo)(struct halmac_adapter *adapter,
+ struct halmac_cfg_mumimo_para *param);
+ enum halmac_ret_status
+ (*halmac_cfg_sounding)(struct halmac_adapter *adapter,
+ enum halmac_snd_role role,
+ enum halmac_data_rate rate);
+ enum halmac_ret_status
+ (*halmac_del_sounding)(struct halmac_adapter *adapter,
+ enum halmac_snd_role role);
+ enum halmac_ret_status
+ (*halmac_su_bfer_entry_init)(struct halmac_adapter *adapter,
+ struct halmac_su_bfer_init_para *param);
+ enum halmac_ret_status
+ (*halmac_su_bfee_entry_init)(struct halmac_adapter *adapter, u8 userid,
+ u16 paid);
+ enum halmac_ret_status
+ (*halmac_mu_bfer_entry_init)(struct halmac_adapter *adapter,
+ struct halmac_mu_bfer_init_para *param);
+ enum halmac_ret_status
+ (*halmac_mu_bfee_entry_init)(struct halmac_adapter *adapter,
+ struct halmac_mu_bfee_init_para *param);
+ enum halmac_ret_status
+ (*halmac_su_bfer_entry_del)(struct halmac_adapter *adapter, u8 userid);
+ enum halmac_ret_status
+ (*halmac_su_bfee_entry_del)(struct halmac_adapter *adapter, u8 userid);
+ enum halmac_ret_status
+ (*halmac_mu_bfer_entry_del)(struct halmac_adapter *adapter);
+ enum halmac_ret_status
+ (*halmac_mu_bfee_entry_del)(struct halmac_adapter *adapter, u8 userid);
+ enum halmac_ret_status
+ (*halmac_add_ch_info)(struct halmac_adapter *adapter,
+ struct halmac_ch_info *info);
+ enum halmac_ret_status
+ (*halmac_add_extra_ch_info)(struct halmac_adapter *adapter,
+ struct halmac_ch_extra_info *info);
+ enum halmac_ret_status
+ (*halmac_ctrl_ch_switch)(struct halmac_adapter *adapter,
+ struct halmac_ch_switch_option *opt);
+ enum halmac_ret_status
+ (*halmac_p2pps)(struct halmac_adapter *adapter,
+ struct halmac_p2pps *info);
+ enum halmac_ret_status
+ (*halmac_clear_ch_info)(struct halmac_adapter *adapter);
+ enum halmac_ret_status
+ (*halmac_send_general_info)(struct halmac_adapter *adapter,
+ struct halmac_general_info *info);
+ enum halmac_ret_status
+ (*halmac_start_iqk)(struct halmac_adapter *adapter,
+ struct halmac_iqk_para *param);
+ enum halmac_ret_status
+ (*halmac_ctrl_pwr_tracking)(struct halmac_adapter *adapter,
+ struct halmac_pwr_tracking_option *opt);
+ enum halmac_ret_status
+ (*halmac_psd)(struct halmac_adapter *adapter, u16 start_psd,
+ u16 end_psd);
+ enum halmac_ret_status
+ (*halmac_cfg_tx_agg_align)(struct halmac_adapter *adapter, u8 enable,
+ u16 align_size);
+ enum halmac_ret_status
+ (*halmac_query_status)(struct halmac_adapter *adapter,
+ enum halmac_feature_id feature_id,
+ enum halmac_cmd_process_status *proc_status,
+ u8 *data, u32 *size);
+ enum halmac_ret_status
+ (*halmac_reset_feature)(struct halmac_adapter *adapter,
+ enum halmac_feature_id feature_id);
+ enum halmac_ret_status
+ (*halmac_check_fw_status)(struct halmac_adapter *adapter,
+ u8 *fw_status);
+ enum halmac_ret_status
+ (*halmac_dump_fw_dmem)(struct halmac_adapter *adapter, u8 *dmem,
+ u32 *size);
+ enum halmac_ret_status
+ (*halmac_cfg_max_dl_size)(struct halmac_adapter *adapter, u32 size);
+ enum halmac_ret_status
+ (*halmac_cfg_la_mode)(struct halmac_adapter *adapter,
+ enum halmac_la_mode mode);
+ enum halmac_ret_status
+ (*halmac_cfg_rxff_expand_mode)(struct halmac_adapter *adapter,
+ enum halmac_rx_fifo_expanding_mode mode);
+ enum halmac_ret_status
+ (*halmac_config_security)(struct halmac_adapter *adapter,
+ struct halmac_security_setting *setting);
+ u8
+ (*halmac_get_used_cam_entry_num)(struct halmac_adapter *adapter,
+ enum hal_security_type sec_type);
+ enum halmac_ret_status
+ (*halmac_write_cam)(struct halmac_adapter *adapter, u32 idx,
+ struct halmac_cam_entry_info *info);
+ enum halmac_ret_status
+ (*halmac_read_cam_entry)(struct halmac_adapter *adapter, u32 idx,
+ struct halmac_cam_entry_format *content);
+ enum halmac_ret_status
+ (*halmac_clear_cam_entry)(struct halmac_adapter *adapter, u32 idx);
+ enum halmac_ret_status
+ (*halmac_get_hw_value)(struct halmac_adapter *adapter,
+ enum halmac_hw_id hw_id, void *value);
+ enum halmac_ret_status
+ (*halmac_set_hw_value)(struct halmac_adapter *adapter,
+ enum halmac_hw_id hw_id, void *value);
+ enum halmac_ret_status
+ (*halmac_cfg_drv_rsvd_pg_num)(struct halmac_adapter *adapter,
+ enum halmac_drv_rsvd_pg_num pg_num);
+ enum halmac_ret_status
+ (*halmac_get_chip_version)(struct halmac_adapter *adapter,
+ struct halmac_ver *ver);
+ enum halmac_ret_status
+ (*halmac_chk_txdesc)(struct halmac_adapter *adapter, u8 *buf, u32 size);
+ enum halmac_ret_status
+ (*halmac_dl_drv_rsvd_page)(struct halmac_adapter *adapter, u8 pg_offset,
+ u8 *buf, u32 size);
+ enum halmac_ret_status
+ (*halmac_pcie_switch)(struct halmac_adapter *adapter,
+ enum halmac_pcie_cfg cfg);
+ enum halmac_ret_status
+ (*halmac_phy_cfg)(struct halmac_adapter *adapter,
+ enum halmac_intf_phy_platform pltfm);
+ enum halmac_ret_status
+ (*halmac_cfg_csi_rate)(struct halmac_adapter *adapter, u8 rssi,
+ u8 cur_rate, u8 fixrate_en, u8 *new_rate);
+ enum halmac_ret_status
+ (*halmac_sdio_cmd53_4byte)(struct halmac_adapter *adapter,
+ enum halmac_sdio_cmd53_4byte_mode mode);
+ enum halmac_ret_status
+ (*halmac_sdio_hw_info)(struct halmac_adapter *adapter,
+ struct halmac_sdio_hw_info *info);
+ enum halmac_ret_status
+ (*halmac_cfg_transmitter_addr)(struct halmac_adapter *adapter, u8 port,
+ union halmac_wlan_addr *addr);
+ enum halmac_ret_status
+ (*halmac_cfg_net_type)(struct halmac_adapter *adapter, u8 port,
+ enum halmac_network_type_select net_type);
+ enum halmac_ret_status
+ (*halmac_cfg_tsf_rst)(struct halmac_adapter *adapter, u8 port);
+ enum halmac_ret_status
+ (*halmac_cfg_bcn_space)(struct halmac_adapter *adapter, u8 port,
+ u32 bcn_space);
+ enum halmac_ret_status
+ (*halmac_rw_bcn_ctrl)(struct halmac_adapter *adapter, u8 port,
+ u8 write_en, struct halmac_bcn_ctrl *ctrl);
+ enum halmac_ret_status
+ (*halmac_interface_integration_tuning)(struct halmac_adapter *adapter);
+ enum halmac_ret_status
+ (*halmac_txfifo_is_empty)(struct halmac_adapter *adapter, u32 chk_num);
+ enum halmac_ret_status
+ (*halmac_download_flash)(struct halmac_adapter *adapter, u8 *fw_bin,
+ u32 size, u32 rom_addr);
+ enum halmac_ret_status
+ (*halmac_read_flash)(struct halmac_adapter *adapter, u32 addr);
+ enum halmac_ret_status
+ (*halmac_erase_flash)(struct halmac_adapter *adapter, u8 erase_cmd,
+ u32 addr);
+ enum halmac_ret_status
+ (*halmac_check_flash)(struct halmac_adapter *adapter, u8 *fw_bin,
+ u32 size, u32 addr);
+ enum halmac_ret_status
+ (*halmac_cfg_edca_para)(struct halmac_adapter *adapter,
+ enum halmac_acq_id acq_id,
+ struct halmac_edca_para *param);
+ enum halmac_ret_status
+ (*halmac_pinmux_get_func)(struct halmac_adapter *adapter,
+ enum halmac_gpio_func gpio_func, u8 *enable);
+ enum halmac_ret_status
+ (*halmac_pinmux_set_func)(struct halmac_adapter *adapter,
+ enum halmac_gpio_func gpio_func);
+ enum halmac_ret_status
+ (*halmac_pinmux_free_func)(struct halmac_adapter *adapter,
+ enum halmac_gpio_func gpio_func);
+ enum halmac_ret_status
+ (*halmac_pinmux_wl_led_mode)(struct halmac_adapter *adapter,
+ enum halmac_wlled_mode mode);
+ void
+ (*halmac_pinmux_wl_led_sw_ctrl)(struct halmac_adapter *adapter, u8 on);
+ void
+ (*halmac_pinmux_sdio_int_polarity)(struct halmac_adapter *adapter,
+ u8 low_active);
+ enum halmac_ret_status
+ (*halmac_pinmux_gpio_mode)(struct halmac_adapter *adapter, u8 gpio_id,
+ u8 output);
+ enum halmac_ret_status
+ (*halmac_pinmux_gpio_output)(struct halmac_adapter *adapter, u8 gpio_id,
+ u8 high);
+ enum halmac_ret_status
+ (*halmac_pinmux_pin_status)(struct halmac_adapter *adapter, u8 pin_id,
+ u8 *high);
+ enum halmac_ret_status
+ (*halmac_ofld_func_cfg)(struct halmac_adapter *adapter,
+ struct halmac_ofld_func_info *info);
+ enum halmac_ret_status
+ (*halmac_rx_cut_amsdu_cfg)(struct halmac_adapter *adapter,
+ struct halmac_cut_amsdu_cfg *cfg);
+ enum halmac_ret_status
+ (*halmac_fw_snding)(struct halmac_adapter *adapter,
+ struct halmac_su_snding_info *su_info,
+ struct halmac_mu_snding_info *mu_info, u8 period);
+ enum halmac_ret_status
+ (*halmac_get_mac_addr)(struct halmac_adapter *adapter, u8 port,
+ union halmac_wlan_addr *addr);
+ enum halmac_ret_status
+ (*halmac_init_low_pwr)(struct halmac_adapter *adapter);
+ enum halmac_ret_status
+ (*halmac_enter_cpu_sleep_mode)(struct halmac_adapter *adapter);
+ enum halmac_ret_status
+ (*halmac_get_cpu_mode)(struct halmac_adapter *adapter,
+ enum halmac_wlcpu_mode *mode);
+ enum halmac_ret_status
+ (*halmac_drv_fwctrl)(struct halmac_adapter *adapter, u8 *payload,
+ u32 size, u8 ack);
+ enum halmac_ret_status
+ (*halmac_read_efuse)(struct halmac_adapter *adapter, u32 offset,
+ u8 *value);
+ enum halmac_ret_status
+ (*halmac_write_efuse)(struct halmac_adapter *adapter, u32 offset,
+ u8 value);
+ VOID
+ (*halmac_en_ref_autok_pcie)(struct halmac_adapter *adapter, u8 en);
#if HALMAC_PLATFORM_TESTPROGRAM
- HALMAC_RET_STATUS (*halmac_gen_txdesc)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pPcket_buffer, PHAL_TXDESC_INFO pTxdesc_info);
- HALMAC_RET_STATUS (*halmac_txdesc_parser)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pTxdesc, PHAL_TXDESC_PARSER pTxdesc_parser);
- HALMAC_RET_STATUS (*halmac_rxdesc_parser)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pRxdesc, PHAL_RXDESC_PARSER pRxdesc_parser);
- HALMAC_RET_STATUS (*halmac_get_txdesc_size)(PHALMAC_ADAPTER pHalmac_adapter, PHAL_TXDESC_INFO pTxdesc_info, u32 *size);
- HALMAC_RET_STATUS (*halmac_send_packet)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBuf, u32 size, PHAL_TXDESC_INFO pTxdesc_Info);
- HALMAC_RET_STATUS (*halmac_get_pcie_packet)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBuf, u32 *size);
- HALMAC_RET_STATUS (*halmac_gen_txagg_desc)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pPcket_buffer, u32 agg_num);
- HALMAC_RET_STATUS (*halmac_parse_packet)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBuf, PHAL_RXDESC_INFO pRxdesc_info, u8 **next_pkt);
- u32 (*halmac_bb_reg_read)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 len);
- HALMAC_RET_STATUS (*halmac_bb_reg_write)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u32 halmac_data, u8 len);
- u32 (*halmac_rf_reg_read)(PHALMAC_ADAPTER pHalmac_adapter, PHAL_RF_REG_INFO pRf_reg_info);
- HALMAC_RET_STATUS (*halmac_rf_reg_write)(PHALMAC_ADAPTER pHalmac_adapter, PHAL_RF_REG_INFO pRf_reg_info);
- HALMAC_RET_STATUS (*halmac_init_antenna_selection)(PHALMAC_ADAPTER pHalmac_adapter);
- HALMAC_RET_STATUS (*halmac_bb_preconfig)(PHALMAC_ADAPTER pHalmac_adapter);
- HALMAC_RET_STATUS (*halmac_init_crystal_capacity)(PHALMAC_ADAPTER pHalmac_adapter);
- HALMAC_RET_STATUS (*halmac_trx_antenna_setting)(PHALMAC_ADAPTER pHalmac_adapter);
- HALMAC_RET_STATUS (*halmac_himr_setting_sdio)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_SDIO_HIMR_INFO sdio_himr_sdio);
- HALMAC_RET_STATUS (*halmac_config_security)(PHALMAC_ADAPTER pHalmac_adapter, PHAL_SECURITY_INFO pSecurity_info);
- HALMAC_RET_STATUS (*halmac_write_cam)(PHALMAC_ADAPTER pHalmac_adapter, u32 entry_index, PHALMAC_CAM_ENTRY_INFO pCam_entry_info);
- HALMAC_RET_STATUS (*halmac_read_cam)(PHALMAC_ADAPTER pHalmac_adapter, u32 entry_index, PHALMAC_CAM_ENTRY_FORMAT pContent);
- HALMAC_RET_STATUS (*halmac_dump_cam_table)(PHALMAC_ADAPTER pHalmac_adapter, u32 entry_num, PHALMAC_CAM_ENTRY_FORMAT pCam_table);
- HALMAC_RET_STATUS (*halmac_load_cam_table)(PHALMAC_ADAPTER pHalmac_adapter, u8 entry_num, PHALMAC_CAM_ENTRY_FORMAT pCam_table);
- HALMAC_RET_STATUS (*halmac_send_beacon)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBuf, u32 size, PHALMAC_BEACON_INFO pbeacon_info);
- HALMAC_RET_STATUS (*halmac_get_management_txdesc)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBuf, u32 *pSize, PHALMAC_MGNT_INFO pmgnt_info);
- HALMAC_RET_STATUS (*halmac_send_control)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBuf, u32 size, PHALMAC_CTRL_INFO pctrl_info);
- HALMAC_RET_STATUS (*halmac_send_hiqueue)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBuf, u32 size, PHALMAC_HIGH_QUEUE_INFO pHigh_info);
- HALMAC_RET_STATUS (*halmac_run_pwrseq)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_PWR_SEQ_ID seq);
- HALMAC_RET_STATUS (*halmac_media_status_rpt)(PHALMAC_ADAPTER pHalmac_adapter, u8 op_mode, u8 mac_id_ind, u8 mac_id, u8 mac_id_end);
- HALMAC_RET_STATUS (*halmac_stop_beacon)(PHALMAC_ADAPTER pHalmac_adapter);
- HALMAC_RET_STATUS (*halmac_check_trx_status)(PHALMAC_ADAPTER pHalmac_adapter);
- HALMAC_RET_STATUS (*halmac_set_agg_num)(PHALMAC_ADAPTER pHalmac_adapter, u8 agg_num);
- HALMAC_RET_STATUS (*halmac_timer_10ms)(PHALMAC_ADAPTER pHalmac_adapter);
- HALMAC_RET_STATUS (*halmac_download_firmware_fpag)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHamacl_fw, u32 halmac_fw_size, u32 iram_address);
- HALMAC_RET_STATUS (*halmac_download_rom_fpga)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHamacl_fw, u32 halmac_fw_size, u32 rom_address);
- HALMAC_RET_STATUS (*halmac_download_flash)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHamacl_fw, u32 halmac_fw_size, u32 rom_address);
- HALMAC_RET_STATUS (*halmac_erase_flash)(PHALMAC_ADAPTER pHalmac_adapter);
- HALMAC_RET_STATUS (*halmac_check_flash)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHamacl_fw, u32 halmac_fw_size);
- HALMAC_RET_STATUS (*halmac_send_nlo)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_NLO_CFG pNlo_cfg);
- HALMAC_RET_STATUS (*halmac_get_chip_type)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_CHIP_TYPE pChip_type);
- u32 (*halmac_get_rx_agg_num)(PHALMAC_ADAPTER pHalmac_adapter, u32 pkt_size, u8 *pPkt_buff);
+ struct halmisc_api *halmisc_api;
#endif
-} HALMAC_API, *PHALMAC_API;
-
-#define HALMAC_GET_API(phalmac_adapter) ((PHALMAC_API)phalmac_adapter->pHalmac_api)
-
-static HALMAC_INLINE HALMAC_RET_STATUS
-halmac_adapter_validate(
- PHALMAC_ADAPTER pHalmac_adapter
-)
-{
- if ((NULL == pHalmac_adapter) || (pHalmac_adapter->pHalAdapter_backup != pHalmac_adapter))
- return HALMAC_RET_ADAPTER_INVALID;
-
- return HALMAC_RET_SUCCESS;
-}
+};
-static HALMAC_INLINE HALMAC_RET_STATUS
-halmac_api_validate(
- PHALMAC_ADAPTER pHalmac_adapter
-)
-{
- if (HALMAC_API_STATE_INIT != pHalmac_adapter->halmac_state.api_state)
- return HALMAC_RET_API_INVALID;
-
- return HALMAC_RET_SUCCESS;
-}
+#define HALMAC_GET_API(halmac_adapter) \
+ ((struct halmac_api *)halmac_adapter->halmac_api)
-static HALMAC_INLINE HALMAC_RET_STATUS
-halmac_fw_validate(
- PHALMAC_ADAPTER pHalmac_adapter
-)
+static HALMAC_INLINE enum halmac_ret_status
+halmac_fw_validate(struct halmac_adapter *adapter)
{
- if (HALMAC_DLFW_DONE != pHalmac_adapter->halmac_state.dlfw_state && HALMAC_GEN_INFO_SENT != pHalmac_adapter->halmac_state.dlfw_state)
+ if (adapter->halmac_state.dlfw_state != HALMAC_DLFW_DONE &&
+ adapter->halmac_state.dlfw_state != HALMAC_GEN_INFO_SENT)
return HALMAC_RET_NO_DLFW;
return HALMAC_RET_SUCCESS;
diff --git a/hal/halmac/halmac_usb_reg.h b/hal/halmac/halmac_usb_reg.h
index 1ff9bde..b856c55 100644
--- a/hal/halmac/halmac_usb_reg.h
+++ b/hal/halmac/halmac_usb_reg.h
@@ -1,8 +1,19 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2018 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ ******************************************************************************/
+
#ifndef __HALMAC_USB_REG_H__
#define __HALMAC_USB_REG_H__
-
-
-
-
#endif/* __HALMAC_USB_REG_H__ */
diff --git a/hal/led/hal_led.c b/hal/led/hal_led.c
new file mode 100644
index 0000000..95d3daa
--- /dev/null
+++ b/hal/led/hal_led.c
@@ -0,0 +1,254 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#include
+#include
+
+#ifdef CONFIG_RTW_LED
+void dump_led_config(void *sel, _adapter *adapter)
+{
+ struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
+ struct led_priv *ledpriv = adapter_to_led(adapter);
+ int i;
+
+ RTW_PRINT_SEL(sel, "strategy:%u\n", ledpriv->LedStrategy);
+#ifdef CONFIG_RTW_SW_LED
+ RTW_PRINT_SEL(sel, "bRegUseLed:%u\n", ledpriv->bRegUseLed);
+ RTW_PRINT_SEL(sel, "iface_en_mask:0x%02X\n", ledpriv->iface_en_mask);
+ for (i = 0; i < dvobj->iface_nums; i++)
+ RTW_PRINT_SEL(sel, "ctl_en_mask[%d]:0x%08X\n", i, ledpriv->ctl_en_mask[i]);
+#endif
+}
+
+void rtw_led_set_strategy(_adapter *adapter, u8 strategy)
+{
+ struct led_priv *ledpriv = adapter_to_led(adapter);
+ _adapter *pri_adapter = GET_PRIMARY_ADAPTER(adapter);
+
+#ifndef CONFIG_RTW_SW_LED
+ if (IS_SW_LED_STRATEGY(strategy)) {
+ RTW_WARN("CONFIG_RTW_SW_LED is not defined\n");
+ return;
+ }
+#endif
+
+#ifdef CONFIG_RTW_SW_LED
+ if (!ledpriv->bRegUseLed)
+ return;
+#endif
+
+ if (ledpriv->LedStrategy == strategy)
+ return;
+
+ if (IS_HW_LED_STRATEGY(strategy) || IS_HW_LED_STRATEGY(ledpriv->LedStrategy)) {
+ RTW_WARN("switching on/off HW_LED strategy is not supported\n");
+ return;
+ }
+
+ ledpriv->LedStrategy = strategy;
+
+#ifdef CONFIG_RTW_SW_LED
+ rtw_hal_sw_led_deinit(pri_adapter);
+#endif
+
+ rtw_led_control(pri_adapter, RTW_LED_OFF);
+}
+
+#ifdef CONFIG_RTW_SW_LED
+#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
+void rtw_sw_led_blink_uc_trx_only(LED_DATA *led)
+{
+ _adapter *adapter = led->padapter;
+ BOOLEAN bStopBlinking = _FALSE;
+
+ if (led->BlinkingLedState == RTW_LED_ON)
+ SwLedOn(adapter, led);
+ else
+ SwLedOff(adapter, led);
+
+ switch (led->CurrLedState) {
+ case RTW_LED_ON:
+ SwLedOn(adapter, led);
+ break;
+
+ case RTW_LED_OFF:
+ SwLedOff(adapter, led);
+ break;
+
+ case LED_BLINK_TXRX:
+ led->BlinkTimes--;
+ if (led->BlinkTimes == 0)
+ bStopBlinking = _TRUE;
+
+ if (adapter_to_pwrctl(adapter)->rf_pwrstate != rf_on
+ && adapter_to_pwrctl(adapter)->rfoff_reason > RF_CHANGE_BY_PS
+ ) {
+ SwLedOff(adapter, led);
+ led->bLedBlinkInProgress = _FALSE;
+ } else {
+ if (led->bLedOn)
+ led->BlinkingLedState = RTW_LED_OFF;
+ else
+ led->BlinkingLedState = RTW_LED_ON;
+
+ if (bStopBlinking) {
+ led->CurrLedState = RTW_LED_OFF;
+ led->bLedBlinkInProgress = _FALSE;
+ }
+ _set_timer(&(led->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
+ }
+ break;
+
+ default:
+ break;
+ }
+}
+
+void rtw_sw_led_ctl_mode_uc_trx_only(_adapter *adapter, LED_CTL_MODE ctl)
+{
+ struct led_priv *ledpriv = adapter_to_led(adapter);
+ LED_DATA *led = &(ledpriv->SwLed0);
+ LED_DATA *led1 = &(ledpriv->SwLed1);
+ LED_DATA *led2 = &(ledpriv->SwLed2);
+
+ switch (ctl) {
+ case LED_CTL_UC_TX:
+ case LED_CTL_UC_RX:
+ if (led->bLedBlinkInProgress == _FALSE) {
+ led->bLedBlinkInProgress = _TRUE;
+ led->CurrLedState = LED_BLINK_TXRX;
+ led->BlinkTimes = 2;
+ if (led->bLedOn)
+ led->BlinkingLedState = RTW_LED_OFF;
+ else
+ led->BlinkingLedState = RTW_LED_ON;
+ _set_timer(&(led->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA);
+ }
+ break;
+
+ case LED_CTL_POWER_OFF:
+ led->CurrLedState = RTW_LED_OFF;
+ led->BlinkingLedState = RTW_LED_OFF;
+
+ if (led->bLedBlinkInProgress) {
+ _cancel_timer_ex(&(led->BlinkTimer));
+ led->bLedBlinkInProgress = _FALSE;
+ }
+
+ SwLedOff(adapter, led);
+ SwLedOff(adapter, led1);
+ SwLedOff(adapter, led2);
+ break;
+
+ default:
+ break;
+ }
+}
+#endif /* CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY */
+
+void rtw_led_control(_adapter *adapter, LED_CTL_MODE ctl)
+{
+ struct led_priv *ledpriv = adapter_to_led(adapter);
+
+ if (ledpriv->LedControlHandler) {
+ #if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
+ if (ledpriv->LedStrategy != SW_LED_MODE_UC_TRX_ONLY) {
+ if (ctl == LED_CTL_UC_TX || ctl == LED_CTL_BMC_TX) {
+ if (ledpriv->ctl_en_mask[adapter->iface_id] & BIT(LED_CTL_TX))
+ ctl = LED_CTL_TX; /* transform specific TX ctl to general TX ctl */
+ } else if (ctl == LED_CTL_UC_RX || ctl == LED_CTL_BMC_RX) {
+ if (ledpriv->ctl_en_mask[adapter->iface_id] & BIT(LED_CTL_RX))
+ ctl = LED_CTL_RX; /* transform specific RX ctl to general RX ctl */
+ }
+ }
+ #endif
+
+ if ((ledpriv->iface_en_mask & BIT(adapter->iface_id))
+ && (ledpriv->ctl_en_mask[adapter->iface_id] & BIT(ctl)))
+ ledpriv->LedControlHandler(adapter, ctl);
+ }
+}
+
+void rtw_led_tx_control(_adapter *adapter, const u8 *da)
+{
+#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
+ if (IS_MCAST(da))
+ rtw_led_control(adapter, LED_CTL_BMC_TX);
+ else
+ rtw_led_control(adapter, LED_CTL_UC_TX);
+#else
+ rtw_led_control(adapter, LED_CTL_TX);
+#endif
+}
+
+void rtw_led_rx_control(_adapter *adapter, const u8 *da)
+{
+#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
+ if (IS_MCAST(da))
+ rtw_led_control(adapter, LED_CTL_BMC_RX);
+ else
+ rtw_led_control(adapter, LED_CTL_UC_RX);
+#else
+ rtw_led_control(adapter, LED_CTL_RX);
+#endif
+}
+
+void rtw_led_set_iface_en(_adapter *adapter, u8 en)
+{
+ struct led_priv *ledpriv = adapter_to_led(adapter);
+
+ if (en)
+ ledpriv->iface_en_mask |= BIT(adapter->iface_id);
+ else
+ ledpriv->iface_en_mask &= ~BIT(adapter->iface_id);
+}
+
+void rtw_led_set_iface_en_mask(_adapter *adapter, u8 mask)
+{
+ struct led_priv *ledpriv = adapter_to_led(adapter);
+
+ ledpriv->iface_en_mask = mask;
+}
+
+void rtw_led_set_ctl_en_mask(_adapter *adapter, u32 ctl_mask)
+{
+ struct led_priv *ledpriv = adapter_to_led(adapter);
+
+#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
+ if (ctl_mask & BIT(LED_CTL_TX))
+ ctl_mask |= BIT(LED_CTL_UC_TX) | BIT(LED_CTL_BMC_TX);
+ if (ctl_mask & BIT(LED_CTL_RX))
+ ctl_mask |= BIT(LED_CTL_UC_RX) | BIT(LED_CTL_BMC_RX);
+#endif
+
+ ledpriv->ctl_en_mask[adapter->iface_id] = ctl_mask;
+}
+
+void rtw_led_set_ctl_en_mask_primary(_adapter *adapter)
+{
+ rtw_led_set_ctl_en_mask(adapter, 0xFFFFFFFF);
+}
+
+void rtw_led_set_ctl_en_mask_virtual(_adapter *adapter)
+{
+ rtw_led_set_ctl_en_mask(adapter
+ , BIT(LED_CTL_POWER_ON) | BIT(LED_CTL_POWER_OFF)
+ | BIT(LED_CTL_TX) | BIT(LED_CTL_RX)
+ );
+}
+#endif /* CONFIG_RTW_SW_LED */
+
+#endif /* CONFIG_RTW_LED */
+
diff --git a/hal/led/hal_usb_led.c b/hal/led/hal_usb_led.c
index 72bacf6..19505b1 100644
--- a/hal/led/hal_usb_led.c
+++ b/hal/led/hal_usb_led.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -11,15 +11,11 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
+ *****************************************************************************/
#include
#include
+#ifdef CONFIG_RTW_SW_LED
/*
* Description:
@@ -38,10 +34,8 @@ SwLedBlink(
/* Change LED according to BlinkingLedState specified. */
if (pLed->BlinkingLedState == RTW_LED_ON) {
SwLedOn(padapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn on\n", pLed->BlinkTimes));
} else {
SwLedOff(padapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn off\n", pLed->BlinkTimes));
}
/* Determine if we shall change LED state again. */
@@ -125,7 +119,7 @@ SwLedBlink1(
{
_adapter *padapter = pLed->padapter;
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
- struct led_priv *ledpriv = &(padapter->ledpriv);
+ struct led_priv *ledpriv = adapter_to_led(padapter);
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
PLED_USB pLed1 = &(ledpriv->SwLed1);
u8 bStopBlinking = _FALSE;
@@ -140,10 +134,8 @@ SwLedBlink1(
/* Change LED according to BlinkingLedState specified. */
if (pLed->BlinkingLedState == RTW_LED_ON) {
SwLedOn(padapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn on\n", pLed->BlinkTimes));
} else {
SwLedOff(padapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn off\n", pLed->BlinkTimes));
}
@@ -154,14 +146,12 @@ SwLedBlink1(
pLed1->bSWLedCtrl = _TRUE;
} else if (!pLed1->bLedOn)
SwLedOn(padapter, pLed1);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (): turn on pLed1\n"));
} else {
if (!pLed1->bSWLedCtrl) {
SwLedOff(padapter, pLed1);
pLed1->bSWLedCtrl = _TRUE;
} else if (pLed1->bLedOn)
SwLedOff(padapter, pLed1);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (): turn off pLed1\n"));
}
}
@@ -198,7 +188,6 @@ SwLedBlink1(
else
pLed->BlinkingLedState = RTW_LED_ON;
_set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState));
} else if (check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE) {
pLed->bLedNoLinkBlinkInProgress = _TRUE;
@@ -208,7 +197,6 @@ SwLedBlink1(
else
pLed->BlinkingLedState = RTW_LED_ON;
_set_timer(&(pLed->BlinkTimer), uLedBlinkNoLinkInterval);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState));
}
pLed->bLedScanBlinkInProgress = _FALSE;
} else {
@@ -239,7 +227,6 @@ SwLedBlink1(
else
pLed->BlinkingLedState = RTW_LED_ON;
_set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState));
} else if (check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE) {
pLed->bLedNoLinkBlinkInProgress = _TRUE;
pLed->CurrLedState = LED_BLINK_SLOWLY;
@@ -248,7 +235,6 @@ SwLedBlink1(
else
pLed->BlinkingLedState = RTW_LED_ON;
_set_timer(&(pLed->BlinkTimer), uLedBlinkNoLinkInterval);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState));
}
pLed->BlinkTimes = 0;
pLed->bLedBlinkInProgress = _FALSE;
@@ -292,7 +278,6 @@ SwLedBlink1(
else
pLed->BlinkingLedState = RTW_LED_ON;
_set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState));
}
pLed->bLedWPSBlinkInProgress = _FALSE;
}
@@ -316,10 +301,8 @@ SwLedBlink2(
/* Change LED according to BlinkingLedState specified. */
if (pLed->BlinkingLedState == RTW_LED_ON) {
SwLedOn(padapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn on\n", pLed->BlinkTimes));
} else {
SwLedOff(padapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn off\n", pLed->BlinkTimes));
}
switch (pLed->CurrLedState) {
@@ -335,13 +318,11 @@ SwLedBlink2(
pLed->CurrLedState = RTW_LED_ON;
pLed->BlinkingLedState = RTW_LED_ON;
SwLedOn(padapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("stop scan blink CurrLedState %d\n", pLed->CurrLedState));
} else if (check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE) {
pLed->CurrLedState = RTW_LED_OFF;
pLed->BlinkingLedState = RTW_LED_OFF;
SwLedOff(padapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("stop scan blink CurrLedState %d\n", pLed->CurrLedState));
}
pLed->bLedScanBlinkInProgress = _FALSE;
} else {
@@ -368,13 +349,11 @@ SwLedBlink2(
pLed->CurrLedState = RTW_LED_ON;
pLed->BlinkingLedState = RTW_LED_ON;
SwLedOn(padapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("stop CurrLedState %d\n", pLed->CurrLedState));
} else if (check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE) {
pLed->CurrLedState = RTW_LED_OFF;
pLed->BlinkingLedState = RTW_LED_OFF;
SwLedOff(padapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("stop CurrLedState %d\n", pLed->CurrLedState));
}
pLed->bLedBlinkInProgress = _FALSE;
} else {
@@ -408,11 +387,9 @@ SwLedBlink3(
/* Change LED according to BlinkingLedState specified. */
if (pLed->BlinkingLedState == RTW_LED_ON) {
SwLedOn(padapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn on\n", pLed->BlinkTimes));
} else {
if (pLed->CurrLedState != LED_BLINK_WPS_STOP)
SwLedOff(padapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn off\n", pLed->BlinkTimes));
}
switch (pLed->CurrLedState) {
@@ -430,14 +407,12 @@ SwLedBlink3(
if (!pLed->bLedOn)
SwLedOn(padapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState));
} else if (check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE) {
pLed->CurrLedState = RTW_LED_OFF;
pLed->BlinkingLedState = RTW_LED_OFF;
if (pLed->bLedOn)
SwLedOff(padapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState));
}
pLed->bLedScanBlinkInProgress = _FALSE;
} else {
@@ -467,7 +442,6 @@ SwLedBlink3(
if (!pLed->bLedOn)
SwLedOn(padapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState));
} else if (check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE) {
pLed->CurrLedState = RTW_LED_OFF;
pLed->BlinkingLedState = RTW_LED_OFF;
@@ -476,7 +450,6 @@ SwLedBlink3(
SwLedOff(padapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState));
}
pLed->bLedBlinkInProgress = _FALSE;
} else {
@@ -515,7 +488,6 @@ SwLedBlink3(
pLed->CurrLedState = RTW_LED_ON;
pLed->BlinkingLedState = RTW_LED_ON;
SwLedOn(padapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState));
}
pLed->bLedWPSBlinkInProgress = _FALSE;
}
@@ -535,7 +507,7 @@ SwLedBlink4(
)
{
_adapter *padapter = pLed->padapter;
- struct led_priv *ledpriv = &(padapter->ledpriv);
+ struct led_priv *ledpriv = adapter_to_led(padapter);
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
PLED_USB pLed1 = &(ledpriv->SwLed1);
u8 bStopBlinking = _FALSE;
@@ -543,10 +515,8 @@ SwLedBlink4(
/* Change LED according to BlinkingLedState specified. */
if (pLed->BlinkingLedState == RTW_LED_ON) {
SwLedOn(padapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn on\n", pLed->BlinkTimes));
} else {
SwLedOff(padapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn off\n", pLed->BlinkTimes));
}
if (!pLed1->bLedWPSBlinkInProgress && pLed1->BlinkingLedState == LED_UNKNOWN) {
@@ -699,7 +669,6 @@ SwLedBlink4(
pLed->bLedBlinkInProgress = _FALSE;
} else {
if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS) {
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("RFOff Status\n"));
SwLedOff(padapter, pLed);
} else {
if (pLed->bLedOn)
@@ -716,7 +685,6 @@ SwLedBlink4(
break;
}
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("SwLedBlink4 CurrLedState %d\n", pLed->CurrLedState));
}
@@ -733,10 +701,8 @@ SwLedBlink5(
/* Change LED according to BlinkingLedState specified. */
if (pLed->BlinkingLedState == RTW_LED_ON) {
SwLedOn(padapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn on\n", pLed->BlinkTimes));
} else {
SwLedOff(padapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn off\n", pLed->BlinkTimes));
}
switch (pLed->CurrLedState) {
@@ -809,7 +775,6 @@ SwLedBlink5(
break;
}
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("SwLedBlink5 CurrLedState %d\n", pLed->CurrLedState));
}
@@ -826,13 +791,10 @@ SwLedBlink6(
/* Change LED according to BlinkingLedState specified. */
if (pLed->BlinkingLedState == RTW_LED_ON) {
SwLedOn(padapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn on\n", pLed->BlinkTimes));
} else {
SwLedOff(padapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn off\n", pLed->BlinkTimes));
}
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("<==== blink6\n"));
}
void
@@ -847,11 +809,9 @@ SwLedBlink7(
/* Change LED according to BlinkingLedState specified. */
if (pLed->BlinkingLedState == RTW_LED_ON) {
SwLedOn(Adapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn on\n", pLed->BlinkTimes));
} else {
if (pLed->CurrLedState != LED_BLINK_WPS_STOP)
SwLedOff(Adapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn off\n", pLed->BlinkTimes));
}
switch (pLed->CurrLedState) {
@@ -869,14 +829,12 @@ SwLedBlink7(
if (!pLed->bLedOn)
SwLedOn(Adapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState));
} else if (check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE) {
pLed->CurrLedState = RTW_LED_OFF;
pLed->BlinkingLedState = RTW_LED_OFF;
if (pLed->bLedOn)
SwLedOff(Adapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState));
}
pLed->bLedScanBlinkInProgress = _FALSE;
} else {
@@ -915,7 +873,6 @@ SwLedBlink7(
pLed->CurrLedState = RTW_LED_ON;
pLed->BlinkingLedState = RTW_LED_ON;
SwLedOn(Adapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState));
}
pLed->bLedWPSBlinkInProgress = _FALSE;
}
@@ -926,7 +883,6 @@ SwLedBlink7(
break;
}
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("<==== blink7\n"));
}
@@ -940,13 +896,10 @@ SwLedBlink8(
/* Change LED according to BlinkingLedState specified. */
if (pLed->BlinkingLedState == RTW_LED_ON) {
SwLedOn(Adapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes blink8(%d): turn on\n", pLed->BlinkTimes));
} else {
SwLedOff(Adapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes blink8(%d): turn off\n", pLed->BlinkTimes));
}
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("<==== blink8\n"));
}
@@ -963,10 +916,8 @@ SwLedBlink9(
/* Change LED according to BlinkingLedState specified. */
if (pLed->BlinkingLedState == RTW_LED_ON) {
SwLedOn(Adapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn on\n", pLed->BlinkTimes));
} else {
SwLedOff(Adapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn off\n", pLed->BlinkTimes));
}
/* RTW_INFO("%s, pLed->CurrLedState=%d, pLed->BlinkingLedState=%d\n", __FUNCTION__, pLed->CurrLedState, pLed->BlinkingLedState); */
@@ -1011,7 +962,6 @@ SwLedBlink9(
pLed->CurrLedState = LED_BLINK_SLOWLY;
_set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState));
} else if (check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE) {
pLed->bLedNoLinkBlinkInProgress = _TRUE;
pLed->CurrLedState = LED_BLINK_SLOWLY;
@@ -1020,7 +970,6 @@ SwLedBlink9(
else
pLed->BlinkingLedState = RTW_LED_ON;
_set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState));
}
pLed->BlinkTimes = 0;
pLed->bLedBlinkInProgress = _FALSE;
@@ -1140,7 +1089,6 @@ SwLedBlink9(
pLed->bLedBlinkInProgress = _FALSE;
} else {
if (adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(Adapter)->rfoff_reason > RF_CHANGE_BY_PS) {
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("RFOff Status\n"));
SwLedOff(Adapter, pLed);
} else {
if (IS_HARDWARE_TYPE_8812AU(Adapter))
@@ -1189,7 +1137,6 @@ SwLedBlink9(
break;
}
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("SwLedBlink9 CurrLedState %d\n", pLed->CurrLedState));
}
/* page added for Netgear A6200V2. 20120827 */
@@ -1205,10 +1152,8 @@ SwLedBlink10(
/* Change LED according to BlinkingLedState specified. */
if (pLed->BlinkingLedState == RTW_LED_ON) {
SwLedOn(Adapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn on\n", pLed->BlinkTimes));
} else {
SwLedOff(Adapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn off\n", pLed->BlinkTimes));
}
@@ -1253,7 +1198,6 @@ SwLedBlink10(
pLed->BlinkingLedState = RTW_LED_OFF;
_set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState));
}
pLed->BlinkTimes = 0;
pLed->bLedBlinkInProgress = _FALSE;
@@ -1345,7 +1289,6 @@ SwLedBlink10(
pLed->bLedBlinkInProgress = _FALSE;
} else {
if (adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(Adapter)->rfoff_reason > RF_CHANGE_BY_PS) {
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("RFOff Status\n"));
SwLedOff(Adapter, pLed);
} else {
if (IS_HARDWARE_TYPE_8812AU(Adapter))
@@ -1394,7 +1337,6 @@ SwLedBlink10(
break;
}
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("SwLedBlink10 CurrLedState %d\n", pLed->CurrLedState));
}
@@ -1410,10 +1352,8 @@ SwLedBlink11(
/* Change LED according to BlinkingLedState specified. */
if (pLed->BlinkingLedState == RTW_LED_ON) {
SwLedOn(Adapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn on\n", pLed->BlinkTimes));
} else {
SwLedOff(Adapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn off\n", pLed->BlinkTimes));
}
switch (pLed->CurrLedState) {
@@ -1469,7 +1409,6 @@ SwLedBlink11(
break;
}
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("SwLedBlink5 CurrLedState %d\n", pLed->CurrLedState));
}
void
@@ -1484,10 +1423,8 @@ SwLedBlink12(
/* Change LED according to BlinkingLedState specified. */
if (pLed->BlinkingLedState == RTW_LED_ON) {
SwLedOn(Adapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%ld): turn on\n", pLed->BlinkTimes));
} else {
SwLedOff(Adapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%ld): turn off\n", pLed->BlinkTimes));
}
switch (pLed->CurrLedState) {
@@ -1538,7 +1475,6 @@ SwLedBlink12(
break;
}
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("SwLedBlink8 CurrLedState %d\n", pLed->CurrLedState));
}
@@ -1556,14 +1492,10 @@ SwLedBlink13(
/* Change LED according to BlinkingLedState specified. */
if (pLed->BlinkingLedState == RTW_LED_ON) {
SwLedOn(Adapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn on\n", pLed->BlinkTimes));
} else {
if (pLed->CurrLedState != LED_BLINK_WPS_STOP)
SwLedOff(Adapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn off\n", pLed->BlinkTimes));
}
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("!!! SwLedBlink13 CurrLedState %d, bLedWPSBlinkInProgress %d, bLedBlinkInProgress %d\n", pLed->CurrLedState, pLed->bLedWPSBlinkInProgress,
- pLed->bLedBlinkInProgress));
switch (pLed->CurrLedState) {
case LED_BLINK_LINK_IN_PROCESS:
if (!pLed->bLedWPSBlinkInProgress)
@@ -1605,7 +1537,6 @@ SwLedBlink13(
break;
}
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("<==== blink13\n"));
}
@@ -1622,14 +1553,10 @@ SwLedBlink14(
/* Change LED according to BlinkingLedState specified. */
if (pLed->BlinkingLedState == RTW_LED_ON) {
SwLedOn(Adapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn on\n", pLed->BlinkTimes));
} else {
if (pLed->CurrLedState != LED_BLINK_WPS_STOP)
SwLedOff(Adapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn off\n", pLed->BlinkTimes));
}
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("!!! SwLedBlink14 CurrLedState %d, bLedWPSBlinkInProgress %d, bLedBlinkInProgress %d\n", pLed->CurrLedState, pLed->bLedWPSBlinkInProgress,
- pLed->bLedBlinkInProgress));
switch (pLed->CurrLedState) {
case LED_BLINK_TXRX:
pLed->BlinkTimes--;
@@ -1668,7 +1595,6 @@ SwLedBlink14(
break;
}
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("<==== blink14\n"));
}
VOID
@@ -1684,14 +1610,10 @@ SwLedBlink15(
if (pLed->BlinkingLedState == RTW_LED_ON) {
SwLedOn(Adapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn on\n", pLed->BlinkTimes));
} else {
if (pLed->CurrLedState != LED_BLINK_WPS_STOP)
SwLedOff(Adapter, pLed);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Blinktimes (%d): turn off\n", pLed->BlinkTimes));
}
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("!!! SwLedBlink15 CurrLedState %d, bLedWPSBlinkInProgress %d, bLedBlinkInProgress %d\n", pLed->CurrLedState, pLed->bLedWPSBlinkInProgress,
- pLed->bLedBlinkInProgress));
switch (pLed->CurrLedState) {
case LED_BLINK_WPS:
if (pLed->bLedOn) {
@@ -1704,7 +1626,6 @@ SwLedBlink15(
break;
case LED_BLINK_WPS_STOP: /* WPS success */
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("blink15, LED_BLINK_WPS_STOP BlinkingLedState %d\n", pLed->BlinkingLedState));
if (pLed->BlinkingLedState == RTW_LED_OFF) {
pLed->bLedWPSBlinkInProgress = _FALSE;
@@ -1719,7 +1640,6 @@ SwLedBlink15(
case LED_BLINK_NO_LINK: {
static BOOLEAN bLedOn = _TRUE;
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("blink15, LED_NO_LINK_BLINK bLedOn %d\n", bLedOn));
if (bLedOn) {
bLedOn = _FALSE;
pLed->BlinkingLedState = RTW_LED_OFF;
@@ -1734,7 +1654,6 @@ SwLedBlink15(
case LED_BLINK_LINK_IDEL: {
static BOOLEAN bLedOn = _TRUE;
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("blink15, LED_BLINK_LINK_IDEL bLedOn %d\n", bLedOn));
if (bLedOn) {
bLedOn = _FALSE;
pLed->BlinkingLedState = RTW_LED_OFF;
@@ -1750,7 +1669,6 @@ SwLedBlink15(
case LED_BLINK_SCAN: {
static u8 BlinkTime = 0;
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("blink15, LED_SCAN_BLINK bLedOn %d\n", BlinkTime));
if (BlinkTime % 2 == 0)
pLed->BlinkingLedState = RTW_LED_ON;
else
@@ -1805,7 +1723,6 @@ SwLedBlink15(
break;
}
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("<==== blink15\n"));
}
/*
@@ -1816,7 +1733,7 @@ SwLedBlink15(
void BlinkHandler(PLED_USB pLed)
{
_adapter *padapter = pLed->padapter;
- struct led_priv *ledpriv = &(padapter->ledpriv);
+ struct led_priv *ledpriv = adapter_to_led(padapter);
/* RTW_INFO("%s (%s:%d)\n",__FUNCTION__, current->comm, current->pid); */
@@ -1829,6 +1746,12 @@ void BlinkHandler(PLED_USB pLed)
}
switch (ledpriv->LedStrategy) {
+ #if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
+ case SW_LED_MODE_UC_TRX_ONLY:
+ rtw_sw_led_blink_uc_trx_only(pLed);
+ break;
+ #endif
+
case SW_LED_MODE0:
SwLedBlink(pLed);
break;
@@ -1894,7 +1817,6 @@ void BlinkHandler(PLED_USB pLed)
break;
default:
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("BlinkWorkItemCallback 0x%x\n", ledpriv->LedStrategy));
/* SwLedBlink(pLed); */
break;
}
@@ -1920,7 +1842,7 @@ void BlinkTimerCallback(void *data)
return;
}
-#ifdef CONFIG_LED_HANDLED_BY_CMD_THREAD
+#ifdef CONFIG_RTW_LED_HANDLED_BY_CMD_THREAD
rtw_led_blink_cmd(padapter, (PVOID)pLed);
#else
_set_workitem(&(pLed->BlinkWorkItem));
@@ -1944,7 +1866,7 @@ SwLedControlMode0(
LED_CTL_MODE LedAction
)
{
- struct led_priv *ledpriv = &(padapter->ledpriv);
+ struct led_priv *ledpriv = adapter_to_led(padapter);
PLED_USB pLed = &(ledpriv->SwLed1);
/* Decide led state */
@@ -2036,7 +1958,6 @@ SwLedControlMode0(
break;
}
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Led %d\n", pLed->CurrLedState));
}
@@ -2047,7 +1968,7 @@ SwLedControlMode1(
LED_CTL_MODE LedAction
)
{
- struct led_priv *ledpriv = &(padapter->ledpriv);
+ struct led_priv *ledpriv = adapter_to_led(padapter);
PLED_USB pLed = &(ledpriv->SwLed0);
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
@@ -2275,7 +2196,6 @@ SwLedControlMode1(
}
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Led %d\n", pLed->CurrLedState));
}
/* Arcadyan/Sitecom , added by chiyoko, 20090216 */
@@ -2285,7 +2205,7 @@ SwLedControlMode2(
LED_CTL_MODE LedAction
)
{
- struct led_priv *ledpriv = &(padapter->ledpriv);
+ struct led_priv *ledpriv = adapter_to_led(padapter);
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
PLED_USB pLed = &(ledpriv->SwLed0);
@@ -2372,7 +2292,6 @@ SwLedControlMode2(
pLed->CurrLedState = RTW_LED_ON;
pLed->BlinkingLedState = RTW_LED_ON;
_set_timer(&(pLed->BlinkTimer), 0);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState));
}
break;
@@ -2381,7 +2300,6 @@ SwLedControlMode2(
pLed->CurrLedState = RTW_LED_OFF;
pLed->BlinkingLedState = RTW_LED_OFF;
_set_timer(&(pLed->BlinkTimer), 0);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState));
break;
case LED_CTL_START_TO_LINK:
@@ -2417,7 +2335,6 @@ SwLedControlMode2(
}
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState));
}
/* COREGA, added by chiyoko, 20090316 */
@@ -2427,7 +2344,7 @@ SwLedControlMode3(
LED_CTL_MODE LedAction
)
{
- struct led_priv *ledpriv = &(padapter->ledpriv);
+ struct led_priv *ledpriv = adapter_to_led(padapter);
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
PLED_USB pLed = &(ledpriv->SwLed0);
@@ -2572,7 +2489,6 @@ SwLedControlMode3(
}
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("CurrLedState %d\n", pLed->CurrLedState));
}
@@ -2583,7 +2499,7 @@ SwLedControlMode4(
LED_CTL_MODE LedAction
)
{
- struct led_priv *ledpriv = &(padapter->ledpriv);
+ struct led_priv *ledpriv = adapter_to_led(padapter);
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
PLED_USB pLed = &(ledpriv->SwLed0);
PLED_USB pLed1 = &(ledpriv->SwLed1);
@@ -2877,7 +2793,6 @@ SwLedControlMode4(
}
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Led %d\n", pLed->CurrLedState));
}
@@ -2889,7 +2804,7 @@ SwLedControlMode5(
LED_CTL_MODE LedAction
)
{
- struct led_priv *ledpriv = &(padapter->ledpriv);
+ struct led_priv *ledpriv = adapter_to_led(padapter);
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
PLED_USB pLed = &(ledpriv->SwLed0);
@@ -2959,7 +2874,6 @@ SwLedControlMode5(
}
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Led %d\n", pLed->CurrLedState));
}
/* WNC-Corega, added by chiyoko, 20090902 */
@@ -2969,7 +2883,7 @@ SwLedControlMode6(
LED_CTL_MODE LedAction
)
{
- struct led_priv *ledpriv = &(padapter->ledpriv);
+ struct led_priv *ledpriv = adapter_to_led(padapter);
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
PLED_USB pLed0 = &(ledpriv->SwLed0);
@@ -2991,7 +2905,6 @@ SwLedControlMode6(
break;
}
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("ledcontrol 6 Led %d\n", pLed0->CurrLedState));
}
/* Netgear, added by sinda, 2011/11/11 */
@@ -3001,7 +2914,7 @@ SwLedControlMode7(
LED_CTL_MODE LedAction
)
{
- struct led_priv *ledpriv = &(Adapter->ledpriv);
+ struct led_priv *ledpriv = adapter_to_led(Adapter);
struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
PLED_USB pLed = &(ledpriv->SwLed0);
@@ -3132,7 +3045,6 @@ SwLedControlMode7(
}
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("LEd control mode 7 CurrLedState %d\n", pLed->CurrLedState));
}
void
@@ -3141,7 +3053,7 @@ SwLedControlMode8(
LED_CTL_MODE LedAction
)
{
- struct led_priv *ledpriv = &(Adapter->ledpriv);
+ struct led_priv *ledpriv = adapter_to_led(Adapter);
struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
PLED_USB pLed0 = &(ledpriv->SwLed0);
@@ -3168,7 +3080,6 @@ SwLedControlMode8(
break;
}
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Led control mode 8 %d\n", pLed0->CurrLedState));
}
@@ -3179,7 +3090,7 @@ SwLedControlMode9(
IN LED_CTL_MODE LedAction
)
{
- struct led_priv *ledpriv = &(Adapter->ledpriv);
+ struct led_priv *ledpriv = adapter_to_led(Adapter);
struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
PLED_USB pLed = &(ledpriv->SwLed0);
PLED_USB pLed1 = &(ledpriv->SwLed1);
@@ -3472,7 +3383,6 @@ SwLedControlMode9(
}
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Led control mode 9 Led %d\n", pLed->CurrLedState));
}
/* page added for Netgear A6200V2, 20120827 */
@@ -3483,7 +3393,7 @@ SwLedControlMode10(
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
- struct led_priv *ledpriv = &(Adapter->ledpriv);
+ struct led_priv *ledpriv = adapter_to_led(Adapter);
struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
PLED_USB pLed = &(ledpriv->SwLed0);
PLED_USB pLed1 = &(ledpriv->SwLed1);
@@ -3505,7 +3415,7 @@ SwLedControlMode10(
if (pLed->bLedWPSBlinkInProgress == _TRUE || pLed1->bLedWPSBlinkInProgress == _TRUE)
;
else {
- if (pHalData->CurrentBandType == BAND_ON_2_4G)
+ if (pHalData->current_band_type == BAND_ON_2_4G)
/* LED0 settings */
{
pLed->CurrLedState = RTW_LED_ON;
@@ -3519,7 +3429,7 @@ SwLedControlMode10(
pLed1->CurrLedState = RTW_LED_OFF;
pLed1->BlinkingLedState = RTW_LED_OFF;
_set_timer(&(pLed1->BlinkTimer), 0);
- } else if (pHalData->CurrentBandType == BAND_ON_5G)
+ } else if (pHalData->current_band_type == BAND_ON_5G)
/* LED1 settings */
{
pLed1->CurrLedState = RTW_LED_ON;
@@ -3615,7 +3525,7 @@ SwLedControlMode10(
break;
case LED_CTL_STOP_WPS: /* WPS connect success */
- if (pHalData->CurrentBandType == BAND_ON_2_4G)
+ if (pHalData->current_band_type == BAND_ON_2_4G)
/* LED0 settings */
{
pLed->bLedWPSBlinkInProgress = _FALSE;
@@ -3630,7 +3540,7 @@ SwLedControlMode10(
pLed1->CurrLedState = RTW_LED_OFF;
pLed1->BlinkingLedState = RTW_LED_OFF;
_set_timer(&(pLed1->BlinkTimer), 0);
- } else if (pHalData->CurrentBandType == BAND_ON_5G)
+ } else if (pHalData->current_band_type == BAND_ON_5G)
/* LED1 settings */
{
pLed1->bLedWPSBlinkInProgress = _FALSE;
@@ -3671,7 +3581,6 @@ SwLedControlMode10(
}
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Led control mode 10 Led %d\n", pLed->CurrLedState));
}
/* Edimax-ASUS, added by Page, 20121221 */
@@ -3681,7 +3590,7 @@ SwLedControlMode11(
LED_CTL_MODE LedAction
)
{
- struct led_priv *ledpriv = &(Adapter->ledpriv);
+ struct led_priv *ledpriv = adapter_to_led(Adapter);
struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
PLED_USB pLed = &(ledpriv->SwLed0);
@@ -3770,7 +3679,6 @@ SwLedControlMode11(
}
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Led mode 1 CurrLedState %d\n", pLed->CurrLedState));
}
/* page added for NEC */
@@ -3781,7 +3689,7 @@ SwLedControlMode12(
LED_CTL_MODE LedAction
)
{
- struct led_priv *ledpriv = &(Adapter->ledpriv);
+ struct led_priv *ledpriv = adapter_to_led(Adapter);
struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
PLED_USB pLed = &(ledpriv->SwLed0);
@@ -3852,7 +3760,6 @@ SwLedControlMode12(
}
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("SWLed12 %d\n", pLed->CurrLedState));
}
/* Maddest add for NETGEAR R6100 */
@@ -3863,11 +3770,10 @@ SwLedControlMode13(
IN LED_CTL_MODE LedAction
)
{
- struct led_priv *ledpriv = &(Adapter->ledpriv);
+ struct led_priv *ledpriv = adapter_to_led(Adapter);
struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
PLED_USB pLed = &(ledpriv->SwLed0);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Led control mode 13 CurrLedState %d, LedAction %d\n", pLed->CurrLedState, LedAction));
switch (LedAction) {
case LED_CTL_LINK:
if (pLed->bLedWPSBlinkInProgress)
@@ -4010,13 +3916,11 @@ SwLedControlMode14(
IN LED_CTL_MODE LedAction
)
{
- struct led_priv *ledpriv = &(Adapter->ledpriv);
+ struct led_priv *ledpriv = adapter_to_led(Adapter);
PLED_USB pLed = &(ledpriv->SwLed0);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Led control mode 14 CurrLedState %d, LedAction %d\n", pLed->CurrLedState, LedAction));
switch (LedAction) {
case LED_CTL_POWER_OFF:
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Led control mode 14 LED_CTL_POWER_OFF\n"));
pLed->CurrLedState = RTW_LED_OFF;
pLed->BlinkingLedState = RTW_LED_OFF;
if (pLed->bLedBlinkInProgress) {
@@ -4027,7 +3931,6 @@ SwLedControlMode14(
break;
case LED_CTL_POWER_ON:
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Led control mode 14 LED_CTL_POWER_ON\n"));
SwLedOn(Adapter, pLed);
break;
@@ -4072,15 +3975,13 @@ SwLedControlMode15(
IN LED_CTL_MODE LedAction
)
{
- struct led_priv *ledpriv = &(Adapter->ledpriv);
+ struct led_priv *ledpriv = adapter_to_led(Adapter);
struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
PLED_USB pLed = &(ledpriv->SwLed0);
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Led control mode 15 CurrLedState %d, LedAction %d\n", pLed->CurrLedState, LedAction));
switch (LedAction) {
case LED_CTL_START_WPS: /* wait until xinpin finish */
case LED_CTL_START_WPS_BOTTON:
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Led control mode 15 LED_CTL_START_WPS\n"));
if (pLed->bLedWPSBlinkInProgress == _FALSE) {
if (pLed->bLedBlinkInProgress == _TRUE) {
_cancel_timer_ex(&(pLed->BlinkTimer));
@@ -4103,7 +4004,6 @@ SwLedControlMode15(
break;
case LED_CTL_STOP_WPS:
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Led control mode 15 LED_CTL_STOP_WPS\n"));
if (pLed->bLedWPSBlinkInProgress)
_cancel_timer_ex(&(pLed->BlinkTimer));
@@ -4119,7 +4019,6 @@ SwLedControlMode15(
case LED_CTL_STOP_WPS_FAIL:
case LED_CTL_STOP_WPS_FAIL_OVERLAP: /* WPS session overlap */
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Led control mode 15 LED_CTL_STOP_WPS_FAIL\n"));
if (pLed->bLedWPSBlinkInProgress) {
_cancel_timer_ex(&(pLed->BlinkTimer));
pLed->bLedWPSBlinkInProgress = _FALSE;
@@ -4131,7 +4030,6 @@ SwLedControlMode15(
break;
case LED_CTL_NO_LINK:
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Led control mode 15 LED_CTL_NO_LINK\n"));
if (pLed->bLedWPSBlinkInProgress)
return;
@@ -4164,7 +4062,6 @@ SwLedControlMode15(
break;
case LED_CTL_LINK:
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("Led control mode 15 LED_CTL_LINK\n"));
if (pLed->bLedWPSBlinkInProgress)
return;
@@ -4227,7 +4124,7 @@ LedControlUSB(
LED_CTL_MODE LedAction
)
{
- struct led_priv *ledpriv = &(padapter->ledpriv);
+ struct led_priv *ledpriv = adapter_to_led(padapter);
#if (MP_DRIVER == 1)
if (padapter->registrypriv.mp_mode == 1)
@@ -4248,12 +4145,6 @@ LedControlUSB(
/* if(priv->bInHctTest) */
/* return; */
-#ifdef CONFIG_CONCURRENT_MODE
- /* Only do led action for PRIMARY_ADAPTER */
- if (padapter->adapter_type != PRIMARY_ADAPTER)
- return;
-#endif
-
if ((adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on &&
adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS) &&
(LedAction == LED_CTL_TX || LedAction == LED_CTL_RX ||
@@ -4264,6 +4155,12 @@ LedControlUSB(
return;
switch (ledpriv->LedStrategy) {
+ #if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
+ case SW_LED_MODE_UC_TRX_ONLY:
+ rtw_sw_led_ctl_mode_uc_trx_only(padapter, LedAction);
+ break;
+ #endif
+
case SW_LED_MODE0:
SwLedControlMode0(padapter, LedAction);
break;
@@ -4332,7 +4229,6 @@ LedControlUSB(
break;
}
- RT_TRACE(_module_rtl8712_led_c_, _drv_info_, ("LedStrategy:%d, LedAction %d\n", ledpriv->LedStrategy, LedAction));
}
/*
@@ -4373,7 +4269,7 @@ InitLed(
pLed->LedPin = LedPin;
ResetLedStatus(pLed);
- _init_timer(&(pLed->BlinkTimer), padapter->pnetdev, BlinkTimerCallback, pLed);
+ rtw_init_timer(&(pLed->BlinkTimer), padapter, BlinkTimerCallback, pLed);
_init_workitem(&(pLed->BlinkWorkItem), BlinkWorkItemCallback, pLed);
}
@@ -4391,3 +4287,4 @@ DeInitLed(
_cancel_timer_ex(&(pLed->BlinkTimer));
ResetLedStatus(pLed);
}
+#endif
diff --git a/hal/phydm/ap_makefile.mk b/hal/phydm/ap_makefile.mk
new file mode 100644
index 0000000..d578c8e
--- /dev/null
+++ b/hal/phydm/ap_makefile.mk
@@ -0,0 +1,118 @@
+
+_PHYDM_FILES :=\
+ phydm/phydm.o \
+ phydm/phydm_dig.o\
+ phydm/phydm_antdiv.o\
+ phydm/phydm_soml.o\
+ phydm/phydm_smt_ant.o\
+ phydm/phydm_pathdiv.o\
+ phydm/phydm_rainfo.o\
+ phydm/phydm_dynamictxpower.o\
+ phydm/phydm_adaptivity.o\
+ phydm/phydm_debug.o\
+ phydm/phydm_interface.o\
+ phydm/phydm_phystatus.o\
+ phydm/phydm_hwconfig.o\
+ phydm/phydm_dfs.o\
+ phydm/phydm_cfotracking.o\
+ phydm/phydm_adc_sampling.o\
+ phydm/phydm_ccx.o\
+ phydm/phydm_primary_cca.o\
+ phydm/phydm_cck_pd.o\
+ phydm/phydm_rssi_monitor.o\
+ phydm/phydm_auto_dbg.o\
+ phydm/phydm_math_lib.o\
+ phydm/phydm_noisemonitor.o\
+ phydm/phydm_api.o\
+ phydm/phydm_pow_train.o\
+ phydm/txbf/phydm_hal_txbf_api.o\
+ EdcaTurboCheck.o\
+ phydm/halrf/halrf.o\
+ phydm/halrf/halphyrf_ap.o\
+ phydm/halrf/halrf_powertracking_ap.o\
+ phydm/halrf/halrf_powertracking.o\
+ phydm/halrf/halrf_kfree.o
+
+ifeq ($(CONFIG_RTL_88E_SUPPORT),y)
+ ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
+ _PHYDM_FILES += \
+ phydm/rtl8188e/halhwimg8188e_bb.o\
+ phydm/rtl8188e/halhwimg8188e_mac.o\
+ phydm/rtl8188e/halhwimg8188e_rf.o\
+ phydm/rtl8188e/phydm_regconfig8188e.o\
+ phydm/rtl8188e/hal8188erateadaptive.o\
+ phydm/rtl8188e/phydm_rtl8188e.o\
+ phydm/halrf/rtl8188e/halrf_8188e_ap.o
+ endif
+endif
+
+ifeq ($(CONFIG_RTL_8812_SUPPORT),y)
+ ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
+ _PHYDM_FILES += ./phydm/halrf/rtl8812a/halrf_8812a_ap.o
+ endif
+endif
+
+ifeq ($(CONFIG_WLAN_HAL_8881A),y)
+ _PHYDM_FILES += phydm/halrf/rtl8821a/halrf_iqk_8821a_ap.o
+endif
+
+ifeq ($(CONFIG_WLAN_HAL_8192EE),y)
+ _PHYDM_FILES += \
+ phydm/halrf/rtl8192e/halrf_8192e_ap.o\
+ phydm/rtl8192e/phydm_rtl8192e.o
+endif
+
+ifeq ($(CONFIG_WLAN_HAL_8814AE),y)
+ rtl8192cd-objs += phydm/halrf/rtl8814a/halrf_8814a_ap.o
+ rtl8192cd-objs += phydm/halrf/rtl8814a/halrf_iqk_8814a.o
+ ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
+ rtl8192cd-objs += \
+ phydm/rtl8814a/halhwimg8814a_bb.o\
+ phydm/rtl8814a/halhwimg8814a_mac.o\
+ phydm/rtl8814a/halhwimg8814a_rf.o\
+ phydm/rtl8814a/phydm_regconfig8814a.o\
+ phydm/rtl8814a/phydm_rtl8814a.o
+ endif
+endif
+
+ifeq ($(CONFIG_WLAN_HAL_8822BE),y)
+ _PHYDM_FILES += phydm/halrf/rtl8822b/halrf_8822b.o
+ _PHYDM_FILES += phydm/halrf/rtl8822b/halrf_iqk_8822b.o
+ ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
+ _PHYDM_FILES += \
+ phydm/rtl8822b/halhwimg8822b_bb.o\
+ phydm/rtl8822b/halhwimg8822b_mac.o\
+ phydm/rtl8822b/halhwimg8822b_rf.o\
+ phydm/rtl8822b/phydm_regconfig8822b.o\
+ phydm/rtl8822b/phydm_hal_api8822b.o\
+ phydm/rtl8822b/phydm_rtl8822b.o
+ endif
+endif
+
+ifeq ($(CONFIG_WLAN_HAL_8821CE),y)
+ _PHYDM_FILES += phydm/halrf/rtl8821c/halrf_8821c.o
+ _PHYDM_FILES += phydm/halrf/rtl8821c/halrf_iqk_8821c.o
+ ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
+ _PHYDM_FILES += \
+ phydm/rtl8821c/halhwimg8821c_bb.o\
+ phydm/rtl8821c/halhwimg8821c_mac.o\
+ phydm/rtl8821c/halhwimg8821c_rf.o\
+ phydm/rtl8821c/phydm_regconfig8821c.o\
+ phydm/rtl8821c/phydm_hal_api8821c.o
+ endif
+endif
+
+ifeq ($(CONFIG_WLAN_HAL_8197F),y)
+ _PHYDM_FILES += phydm/halrf/rtl8197f/halrf_8197f.o
+ _PHYDM_FILES += phydm/halrf/rtl8197f/halrf_iqk_8197f.o
+ _PHYDM_FILES += efuse_97f/efuse.o
+ ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
+ _PHYDM_FILES += \
+ phydm/rtl8197f/halhwimg8197f_bb.o\
+ phydm/rtl8197f/halhwimg8197f_mac.o\
+ phydm/rtl8197f/halhwimg8197f_rf.o\
+ phydm/rtl8197f/phydm_hal_api8197f.o\
+ phydm/rtl8197f/phydm_regconfig8197f.o\
+ phydm/rtl8197f/phydm_rtl8197f.o
+ endif
+endif
diff --git a/hal/phydm/halhwimg.h b/hal/phydm/halhwimg.h
index 4c5c881..e8f5802 100644
--- a/hal/phydm/halhwimg.h
+++ b/hal/phydm/halhwimg.h
@@ -1,123 +1,137 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2016 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
#pragma once
#ifndef __INC_HW_IMG_H
#define __INC_HW_IMG_H
-//
-// 2011/03/15 MH Add for different IC HW image file selection. code size consideration.
-//
+/*
+ * 2011/03/15 MH Add for different IC HW image file selection. code size consideration.
+ * */
#if RT_PLATFORM == PLATFORM_LINUX
#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
- // For 92C
- #define RTL8192CE_HWIMG_SUPPORT 1
- #define RTL8192CE_TEST_HWIMG_SUPPORT 0
- #define RTL8192CU_HWIMG_SUPPORT 0
- #define RTL8192CU_TEST_HWIMG_SUPPORT 0
+ /* For 92C */
+ #define RTL8192CE_HWIMG_SUPPORT 1
+ #define RTL8192CE_TEST_HWIMG_SUPPORT 0
+ #define RTL8192CU_HWIMG_SUPPORT 0
+ #define RTL8192CU_TEST_HWIMG_SUPPORT 0
+
+ /* For 92D */
+ #define RTL8192DE_HWIMG_SUPPORT 1
+ #define RTL8192DE_TEST_HWIMG_SUPPORT 0
+ #define RTL8192DU_HWIMG_SUPPORT 0
+ #define RTL8192DU_TEST_HWIMG_SUPPORT 0
+
+ /* For 8723 */
+ #define RTL8723E_HWIMG_SUPPORT 1
+ #define RTL8723U_HWIMG_SUPPORT 0
+ #define RTL8723S_HWIMG_SUPPORT 0
+
+ /* For 88E */
+ #define RTL8188EE_HWIMG_SUPPORT 0
+ #define RTL8188EU_HWIMG_SUPPORT 0
+ #define RTL8188ES_HWIMG_SUPPORT 0
- // For 92D
- #define RTL8192DE_HWIMG_SUPPORT 1
- #define RTL8192DE_TEST_HWIMG_SUPPORT 0
- #define RTL8192DU_HWIMG_SUPPORT 0
- #define RTL8192DU_TEST_HWIMG_SUPPORT 0
-
- // For 8723
- #define RTL8723E_HWIMG_SUPPORT 1
- #define RTL8723U_HWIMG_SUPPORT 0
- #define RTL8723S_HWIMG_SUPPORT 0
-
- //For 88E
- #define RTL8188EE_HWIMG_SUPPORT 0
- #define RTL8188EU_HWIMG_SUPPORT 0
- #define RTL8188ES_HWIMG_SUPPORT 0
-
#elif (DEV_BUS_TYPE == RT_USB_INTERFACE)
- // For 92C
- #define RTL8192CE_HWIMG_SUPPORT 0
- #define RTL8192CE_TEST_HWIMG_SUPPORT 0
- #define RTL8192CU_HWIMG_SUPPORT 1
- #define RTL8192CU_TEST_HWIMG_SUPPORT 0
-
- //For 92D
- #define RTL8192DE_HWIMG_SUPPORT 0
- #define RTL8192DE_TEST_HWIMG_SUPPORT 0
- #define RTL8192DU_HWIMG_SUPPORT 1
- #define RTL8192DU_TEST_HWIMG_SUPPORT 0
-
- // For 8723
- #define RTL8723E_HWIMG_SUPPORT 0
- #define RTL8723U_HWIMG_SUPPORT 1
- #define RTL8723S_HWIMG_SUPPORT 0
-
- //For 88E
- #define RTL8188EE_HWIMG_SUPPORT 0
- #define RTL8188EU_HWIMG_SUPPORT 0
- #define RTL8188ES_HWIMG_SUPPORT 0
-
+ /* For 92C */
+ #define RTL8192CE_HWIMG_SUPPORT 0
+ #define RTL8192CE_TEST_HWIMG_SUPPORT 0
+ #define RTL8192CU_HWIMG_SUPPORT 1
+ #define RTL8192CU_TEST_HWIMG_SUPPORT 0
+
+ /* For 92D */
+ #define RTL8192DE_HWIMG_SUPPORT 0
+ #define RTL8192DE_TEST_HWIMG_SUPPORT 0
+ #define RTL8192DU_HWIMG_SUPPORT 1
+ #define RTL8192DU_TEST_HWIMG_SUPPORT 0
+
+ /* For 8723 */
+ #define RTL8723E_HWIMG_SUPPORT 0
+ #define RTL8723U_HWIMG_SUPPORT 1
+ #define RTL8723S_HWIMG_SUPPORT 0
+
+ /* For 88E */
+ #define RTL8188EE_HWIMG_SUPPORT 0
+ #define RTL8188EU_HWIMG_SUPPORT 0
+ #define RTL8188ES_HWIMG_SUPPORT 0
+
#elif (DEV_BUS_TYPE == RT_SDIO_INTERFACE)
- // For 92C
- #define RTL8192CE_HWIMG_SUPPORT 0
- #define RTL8192CE_TEST_HWIMG_SUPPORT 0
- #define RTL8192CU_HWIMG_SUPPORT 1
- #define RTL8192CU_TEST_HWIMG_SUPPORT 0
-
- //For 92D
- #define RTL8192DE_HWIMG_SUPPORT 0
- #define RTL8192DE_TEST_HWIMG_SUPPORT 0
- #define RTL8192DU_HWIMG_SUPPORT 1
- #define RTL8192DU_TEST_HWIMG_SUPPORT 0
-
- // For 8723
- #define RTL8723E_HWIMG_SUPPORT 0
- #define RTL8723U_HWIMG_SUPPORT 0
- #define RTL8723S_HWIMG_SUPPORT 1
-
- //For 88E
- #define RTL8188EE_HWIMG_SUPPORT 0
- #define RTL8188EU_HWIMG_SUPPORT 0
- #define RTL8188ES_HWIMG_SUPPORT 0
+ /* For 92C */
+ #define RTL8192CE_HWIMG_SUPPORT 0
+ #define RTL8192CE_TEST_HWIMG_SUPPORT 0
+ #define RTL8192CU_HWIMG_SUPPORT 1
+ #define RTL8192CU_TEST_HWIMG_SUPPORT 0
+
+ /* For 92D */
+ #define RTL8192DE_HWIMG_SUPPORT 0
+ #define RTL8192DE_TEST_HWIMG_SUPPORT 0
+ #define RTL8192DU_HWIMG_SUPPORT 1
+ #define RTL8192DU_TEST_HWIMG_SUPPORT 0
+
+ /* For 8723 */
+ #define RTL8723E_HWIMG_SUPPORT 0
+ #define RTL8723U_HWIMG_SUPPORT 0
+ #define RTL8723S_HWIMG_SUPPORT 1
+
+ /* For 88E */
+ #define RTL8188EE_HWIMG_SUPPORT 0
+ #define RTL8188EU_HWIMG_SUPPORT 0
+ #define RTL8188ES_HWIMG_SUPPORT 0
#endif
-#else // PLATFORM_WINDOWS & MacOSX
+#else /* PLATFORM_WINDOWS & MacOSX */
-//For 92C
-#define RTL8192CE_HWIMG_SUPPORT 1
-#define RTL8192CE_TEST_HWIMG_SUPPORT 1
-#define RTL8192CU_HWIMG_SUPPORT 1
-#define RTL8192CU_TEST_HWIMG_SUPPORT 1
+ /* For 92C */
+ #define RTL8192CE_HWIMG_SUPPORT 1
+ #define RTL8192CE_TEST_HWIMG_SUPPORT 1
+ #define RTL8192CU_HWIMG_SUPPORT 1
+ #define RTL8192CU_TEST_HWIMG_SUPPORT 1
-// For 92D
-#define RTL8192DE_HWIMG_SUPPORT 1
-#define RTL8192DE_TEST_HWIMG_SUPPORT 1
-#define RTL8192DU_HWIMG_SUPPORT 1
-#define RTL8192DU_TEST_HWIMG_SUPPORT 1
+ /* For 92D */
+ #define RTL8192DE_HWIMG_SUPPORT 1
+ #define RTL8192DE_TEST_HWIMG_SUPPORT 1
+ #define RTL8192DU_HWIMG_SUPPORT 1
+ #define RTL8192DU_TEST_HWIMG_SUPPORT 1
#if defined(UNDER_CE)
- // For 8723
- #define RTL8723E_HWIMG_SUPPORT 0
- #define RTL8723U_HWIMG_SUPPORT 0
- #define RTL8723S_HWIMG_SUPPORT 1
-
- // For 88E
- #define RTL8188EE_HWIMG_SUPPORT 0
- #define RTL8188EU_HWIMG_SUPPORT 0
- #define RTL8188ES_HWIMG_SUPPORT 0
-
- #else
-
- // For 8723
- #define RTL8723E_HWIMG_SUPPORT 1
- //#define RTL_8723E_TEST_HWIMG_SUPPORT 1
- #define RTL8723U_HWIMG_SUPPORT 1
- //#define RTL_8723U_TEST_HWIMG_SUPPORT 1
- #define RTL8723S_HWIMG_SUPPORT 1
- //#define RTL_8723S_TEST_HWIMG_SUPPORT 1
-
- //For 88E
- #define RTL8188EE_HWIMG_SUPPORT 1
- #define RTL8188EU_HWIMG_SUPPORT 1
- #define RTL8188ES_HWIMG_SUPPORT 1
+ /* For 8723 */
+ #define RTL8723E_HWIMG_SUPPORT 0
+ #define RTL8723U_HWIMG_SUPPORT 0
+ #define RTL8723S_HWIMG_SUPPORT 1
+
+ /* For 88E */
+ #define RTL8188EE_HWIMG_SUPPORT 0
+ #define RTL8188EU_HWIMG_SUPPORT 0
+ #define RTL8188ES_HWIMG_SUPPORT 0
+
+ #else
+
+ /* For 8723 */
+ #define RTL8723E_HWIMG_SUPPORT 1
+ /* #define RTL_8723E_TEST_HWIMG_SUPPORT 1 */
+ #define RTL8723U_HWIMG_SUPPORT 1
+ /* #define RTL_8723U_TEST_HWIMG_SUPPORT 1 */
+ #define RTL8723S_HWIMG_SUPPORT 1
+ /* #define RTL_8723S_TEST_HWIMG_SUPPORT 1 */
+
+ /* For 88E */
+ #define RTL8188EE_HWIMG_SUPPORT 1
+ #define RTL8188EU_HWIMG_SUPPORT 1
+ #define RTL8188ES_HWIMG_SUPPORT 1
#endif
#endif
-#endif //__INC_HW_IMG_H
+#endif /* __INC_HW_IMG_H */
diff --git a/hal/phydm/halphyrf_ap.c b/hal/phydm/halphyrf_ap.c
deleted file mode 100644
index 6cb87f8..0000000
--- a/hal/phydm/halphyrf_ap.c
+++ /dev/null
@@ -1,2790 +0,0 @@
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of version 2 of the GNU General Public License as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
-
- #include "mp_precomp.h"
- #include "phydm_precomp.h"
-
-#ifndef index_mapping_NUM_88E
- #define index_mapping_NUM_88E 15
-#endif
-
-//#if(DM_ODM_SUPPORT_TYPE & ODM_WIN)
-
-#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _deltaThermal) \
- do {\
- for(_offset = 0; _offset < _size; _offset++)\
- {\
- if(_deltaThermal < thermalThreshold[_direction][_offset])\
- {\
- if(_offset != 0)\
- _offset--;\
- break;\
- }\
- } \
- if(_offset >= _size)\
- _offset = _size-1;\
- } while(0)
-
-
-void ConfigureTxpowerTrack(
- IN PVOID pDM_VOID,
- OUT PTXPWRTRACK_CFG pConfig
- )
-{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
-#if RTL8812A_SUPPORT
-#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
- //if (IS_HARDWARE_TYPE_8812(pDM_Odm->Adapter))
- if(pDM_Odm->SupportICType==ODM_RTL8812)
- ConfigureTxpowerTrack_8812A(pConfig);
- //else
-#endif
-#endif
-
-#if RTL8814A_SUPPORT
- if(pDM_Odm->SupportICType== ODM_RTL8814A)
- ConfigureTxpowerTrack_8814A(pConfig);
-#endif
-
-
-#if RTL8188E_SUPPORT
- if(pDM_Odm->SupportICType==ODM_RTL8188E)
- ConfigureTxpowerTrack_8188E(pConfig);
-#endif
-
-#if RTL8197F_SUPPORT
- if (pDM_Odm->SupportICType == ODM_RTL8197F)
- ConfigureTxpowerTrack_8197F(pConfig);
-#endif
-
-#if RTL8822B_SUPPORT
- if (pDM_Odm->SupportICType == ODM_RTL8822B)
- ConfigureTxpowerTrack_8822B(pConfig);
-#endif
-
-
-}
-
-#if (RTL8192E_SUPPORT==1)
-VOID
-ODM_TXPowerTrackingCallback_ThermalMeter_92E(
-#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
- IN PVOID pDM_VOID
-#else
- IN PADAPTER Adapter
-#endif
- )
-{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- u1Byte ThermalValue = 0, delta, delta_IQK, delta_LCK, channel, is_decrease, rf_mimo_mode;
- u1Byte ThermalValue_AVG_count = 0;
- u1Byte OFDM_min_index = 10; //OFDM BB Swing should be less than +2.5dB, which is required by Arthur
- s1Byte OFDM_index[2], index ;
- u4Byte ThermalValue_AVG = 0, Reg0x18;
- u4Byte i = 0, j = 0, rf;
- s4Byte value32, CCK_index = 0, ele_A, ele_D, ele_C, X, Y;
- prtl8192cd_priv priv = pDM_Odm->priv;
-
- rf_mimo_mode = pDM_Odm->RFType;
- //ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("%s:%d rf_mimo_mode:%d\n", __FUNCTION__, __LINE__, rf_mimo_mode));
-
-#ifdef MP_TEST
- if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) {
- channel = priv->pshare->working_channel;
- if (priv->pshare->mp_txpwr_tracking == FALSE)
- return;
- } else
-#endif
- {
- channel = (priv->pmib->dot11RFEntry.dot11channel);
- }
-
- ThermalValue = (unsigned char)ODM_GetRFReg(pDM_Odm, RF_PATH_A, ODM_RF_T_METER_92E, 0xfc00); //0x42: RF Reg[15:10] 88E
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", ThermalValue, priv->pshare->ThermalValue, priv->pmib->dot11RFEntry.ther));
-
-
- switch (rf_mimo_mode) {
- case MIMO_1T1R:
- rf = 1;
- break;
- case MIMO_2T2R:
- rf = 2;
- break;
- default:
- rf = 2;
- break;
- }
-
- //Query OFDM path A default setting Bit[31:21]
- ele_D = PHY_QueryBBReg(priv, rOFDM0_XATxIQImbalance, bMaskOFDM_D);
- for (i = 0; i < OFDM_TABLE_SIZE_92E; i++) {
- if (ele_D == (OFDMSwingTable_92E[i] >> 22)) {
- OFDM_index[0] = (unsigned char)i;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("PathA 0xC80[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[0]));
- break;
- }
- }
-
- //Query OFDM path B default setting
- if (rf_mimo_mode == MIMO_2T2R) {
- ele_D = PHY_QueryBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskOFDM_D);
- for (i = 0; i < OFDM_TABLE_SIZE_92E; i++) {
- if (ele_D == (OFDMSwingTable_92E[i] >> 22)) {
- OFDM_index[1] = (unsigned char)i;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("PathB 0xC88[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[1]));
- break;
- }
- }
- }
-
- /* calculate average thermal meter */
- {
- priv->pshare->ThermalValue_AVG_88XX[priv->pshare->ThermalValue_AVG_index_88XX] = ThermalValue;
- priv->pshare->ThermalValue_AVG_index_88XX++;
- if (priv->pshare->ThermalValue_AVG_index_88XX == AVG_THERMAL_NUM_88XX)
- priv->pshare->ThermalValue_AVG_index_88XX = 0;
-
- for (i = 0; i < AVG_THERMAL_NUM_88XX; i++) {
- if (priv->pshare->ThermalValue_AVG_88XX[i]) {
- ThermalValue_AVG += priv->pshare->ThermalValue_AVG_88XX[i];
- ThermalValue_AVG_count++;
- }
- }
-
- if (ThermalValue_AVG_count) {
- ThermalValue = (unsigned char)(ThermalValue_AVG / ThermalValue_AVG_count);
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("AVG Thermal Meter = 0x%x \n", ThermalValue));
- }
- }
-
- /* Initialize */
- if (!priv->pshare->ThermalValue) {
- priv->pshare->ThermalValue = priv->pmib->dot11RFEntry.ther;
- priv->pshare->ThermalValue_IQK = ThermalValue;
- priv->pshare->ThermalValue_LCK = ThermalValue;
- }
-
- if (ThermalValue != priv->pshare->ThermalValue) {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\n******** START POWER TRACKING ********\n"));
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", ThermalValue, priv->pshare->ThermalValue, priv->pmib->dot11RFEntry.ther));
-
- delta = RTL_ABS(ThermalValue, priv->pmib->dot11RFEntry.ther);
- delta_IQK = RTL_ABS(ThermalValue, priv->pshare->ThermalValue_IQK);
- delta_LCK = RTL_ABS(ThermalValue, priv->pshare->ThermalValue_LCK);
- is_decrease = ((ThermalValue < priv->pmib->dot11RFEntry.ther) ? 1 : 0);
-
-#ifdef _TRACKING_TABLE_FILE
- if (priv->pshare->rf_ft_var.pwr_track_file) {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("Diff: (%s)%d ==> get index from table : %d)\n", (is_decrease?"-":"+"), delta, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0)));
-
- if (is_decrease) {
- for (i = 0; i < rf; i++) {
- OFDM_index[i] = priv->pshare->OFDM_index0[i] + get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0);
- OFDM_index[i] = ((OFDM_index[i] > (OFDM_TABLE_SIZE_92E- 1)) ? (OFDM_TABLE_SIZE_92E - 1) : OFDM_index[i]);
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0)));
- CCK_index = priv->pshare->CCK_index0 + get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1);
- CCK_index = ((CCK_index > (CCK_TABLE_SIZE_92E - 1)) ? (CCK_TABLE_SIZE_92E - 1) : CCK_index);
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> Decrese power ---> new CCK_INDEX:%d (%d + %d)\n", CCK_index, priv->pshare->CCK_index0, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1)));
- }
- } else {
- for (i = 0; i < rf; i++) {
- OFDM_index[i] = priv->pshare->OFDM_index0[i] - get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0);
- OFDM_index[i] = ((OFDM_index[i] < OFDM_min_index) ? OFDM_min_index : OFDM_index[i]);
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> Increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0)));
- CCK_index = priv->pshare->CCK_index0 - get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1);
- CCK_index = ((CCK_index < 0 )? 0 : CCK_index);
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> Increse power ---> new CCK_INDEX:%d (%d - %d)\n", CCK_index, priv->pshare->CCK_index0, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1)));
- }
- }
- }
-#endif //CFG_TRACKING_TABLE_FILE
-
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("OFDMSwingTable_92E[(unsigned int)OFDM_index[0]] = %x \n",OFDMSwingTable_92E[(unsigned int)OFDM_index[0]]));
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("OFDMSwingTable_92E[(unsigned int)OFDM_index[1]] = %x \n",OFDMSwingTable_92E[(unsigned int)OFDM_index[1]]));
-
- //Adujst OFDM Ant_A according to IQK result
- ele_D = (OFDMSwingTable_92E[(unsigned int)OFDM_index[0]] & 0xFFC00000) >> 22;
- X = priv->pshare->RegE94;
- Y = priv->pshare->RegE9C;
-
- if (X != 0) {
- if ((X & 0x00000200) != 0)
- X = X | 0xFFFFFC00;
- ele_A = ((X * ele_D) >> 8) & 0x000003FF;
-
- //new element C = element D x Y
- if ((Y & 0x00000200) != 0)
- Y = Y | 0xFFFFFC00;
- ele_C = ((Y * ele_D) >> 8) & 0x000003FF;
-
- //wirte new elements A, C, D to regC80 and regC94, element B is always 0
- value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A;
- PHY_SetBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord, value32);
-
- value32 = (ele_C&0x000003C0)>>6;
- PHY_SetBBReg(priv, rOFDM0_XCTxAFE, bMaskH4Bits, value32);
-
- value32 = ((X * ele_D)>>7)&0x01;
- PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(24), value32);
- } else {
- PHY_SetBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_92E[(unsigned int)OFDM_index[0]]);
- PHY_SetBBReg(priv, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00);
- PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(24), 0x00);
- }
-
- set_CCK_swing_index(priv, CCK_index);
-
- if (rf == 2) {
- ele_D = (OFDMSwingTable_92E[(unsigned int)OFDM_index[1]] & 0xFFC00000) >> 22;
- X = priv->pshare->RegEB4;
- Y = priv->pshare->RegEBC;
-
- if (X != 0) {
- if ((X & 0x00000200) != 0) //consider minus
- X = X | 0xFFFFFC00;
- ele_A = ((X * ele_D) >> 8) & 0x000003FF;
-
- //new element C = element D x Y
- if ((Y & 0x00000200) != 0)
- Y = Y | 0xFFFFFC00;
- ele_C = ((Y * ele_D) >> 8) & 0x00003FF;
-
- //wirte new elements A, C, D to regC88 and regC9C, element B is always 0
- value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A;
- PHY_SetBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord, value32);
-
- value32 = (ele_C & 0x000003C0) >> 6;
- PHY_SetBBReg(priv, rOFDM0_XDTxAFE, bMaskH4Bits, value32);
-
- value32 = ((X * ele_D) >> 7) & 0x01;
- PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(28), value32);
- } else {
- PHY_SetBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_92E[(unsigned int)OFDM_index[1]]);
- PHY_SetBBReg(priv, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00);
- PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(28), 0x00);
- }
-
- }
-
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("0xc80 = 0x%x \n", PHY_QueryBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord)));
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("0xc88 = 0x%x \n", PHY_QueryBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord)));
-
- if (delta_IQK > 3) {
- priv->pshare->ThermalValue_IQK = ThermalValue;
-#ifdef MP_TEST
- if (!(priv->pshare->rf_ft_var.mp_specific && (OPMODE & (WIFI_MP_CTX_BACKGROUND | WIFI_MP_CTX_PACKET))))
-#endif
- PHY_IQCalibrate_8192E(pDM_Odm,false);
- }
-
- if (delta_LCK > 8) {
- RTL_W8(0x522, 0xff);
- Reg0x18 = PHY_QueryRFReg(priv, RF_PATH_A, 0x18, bMask20Bits, 1);
- PHY_SetRFReg(priv, RF_PATH_A, 0xB4, BIT(14), 1);
- PHY_SetRFReg(priv, RF_PATH_A, 0x18, BIT(15), 1);
- delay_ms(1);
- PHY_SetRFReg(priv, RF_PATH_A, 0xB4, BIT(14), 0);
- PHY_SetRFReg(priv, RF_PATH_A, 0x18, bMask20Bits, Reg0x18);
- RTL_W8(0x522, 0x0);
- priv->pshare->ThermalValue_LCK = ThermalValue;
- }
- }
-
- //update thermal meter value
- priv->pshare->ThermalValue = ThermalValue;
- for (i = 0 ; i < rf ; i++)
- priv->pshare->OFDM_index[i] = OFDM_index[i];
- priv->pshare->CCK_index = CCK_index;
-
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\n******** END:%s() ********\n", __FUNCTION__));
-}
-#endif
-
-
-
-#if (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1)
-VOID
-ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries3(
-#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
- IN PVOID pDM_VOID
-#else
- IN PADAPTER Adapter
-#endif
- )
-{
-#if 1
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- u1Byte ThermalValue = 0, delta, delta_LCK, delta_IQK, channel, is_increase;
- u1Byte ThermalValue_AVG_count = 0, p = 0, i = 0;
- u4Byte ThermalValue_AVG = 0;
- prtl8192cd_priv priv = pDM_Odm->priv;
- TXPWRTRACK_CFG c;
- PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
-
- /*4 1. The following TWO tables decide the final index of OFDM/CCK swing table.*/
- pu1Byte deltaSwingTableIdx_TUP_A = NULL, deltaSwingTableIdx_TDOWN_A = NULL;
- pu1Byte deltaSwingTableIdx_TUP_B = NULL, deltaSwingTableIdx_TDOWN_B = NULL;
- pu1Byte deltaSwingTableIdx_TUP_CCK_A = NULL, deltaSwingTableIdx_TDOWN_CCK_A = NULL;
- pu1Byte deltaSwingTableIdx_TUP_CCK_B = NULL, deltaSwingTableIdx_TDOWN_CCK_B = NULL;
- /*for 8814 add by Yu Chen*/
- pu1Byte deltaSwingTableIdx_TUP_C = NULL, deltaSwingTableIdx_TDOWN_C = NULL;
- pu1Byte deltaSwingTableIdx_TUP_D = NULL, deltaSwingTableIdx_TDOWN_D = NULL;
- pu1Byte deltaSwingTableIdx_TUP_CCK_C = NULL, deltaSwingTableIdx_TDOWN_CCK_C = NULL;
- pu1Byte deltaSwingTableIdx_TUP_CCK_D = NULL, deltaSwingTableIdx_TDOWN_CCK_D = NULL;
-
-#ifdef MP_TEST
- if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) {
- channel = priv->pshare->working_channel;
- if (priv->pshare->mp_txpwr_tracking == FALSE)
- return;
- } else
-#endif
- {
- channel = (priv->pmib->dot11RFEntry.dot11channel);
- }
-
- ConfigureTxpowerTrack(pDM_Odm, &c);
-
- (*c.GetDeltaAllSwingTable)(pDM_Odm, (pu1Byte *)&deltaSwingTableIdx_TUP_A, (pu1Byte *)&deltaSwingTableIdx_TDOWN_A,
- (pu1Byte *)&deltaSwingTableIdx_TUP_B, (pu1Byte *)&deltaSwingTableIdx_TDOWN_B,
- (pu1Byte *)&deltaSwingTableIdx_TUP_CCK_A, (pu1Byte *)&deltaSwingTableIdx_TDOWN_CCK_A,
- (pu1Byte *)&deltaSwingTableIdx_TUP_CCK_B, (pu1Byte *)&deltaSwingTableIdx_TDOWN_CCK_B);
-
- ThermalValue = (u1Byte)ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, c.ThermalRegAddr, 0xfc00); /*0x42: RF Reg[15:10] 88E*/
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("Readback Thermal Meter = 0x%x(%d) EEPROMthermalmeter 0x%x(%d)\n"
- , ThermalValue, ThermalValue, priv->pmib->dot11RFEntry.ther, priv->pmib->dot11RFEntry.ther));
-
- /* Initialize */
- if (!pDM_Odm->RFCalibrateInfo.ThermalValue)
- pDM_Odm->RFCalibrateInfo.ThermalValue = priv->pmib->dot11RFEntry.ther;
-
- if (!pDM_Odm->RFCalibrateInfo.ThermalValue_LCK)
- pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = priv->pmib->dot11RFEntry.ther;
-
- if (!pDM_Odm->RFCalibrateInfo.ThermalValue_IQK)
- pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = priv->pmib->dot11RFEntry.ther;
-
- /* calculate average thermal meter */
- pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index] = ThermalValue;
- pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index++;
-
- if (pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index == c.AverageThermalNum) /*Average times = c.AverageThermalNum*/
- pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index = 0;
-
- for (i = 0; i < c.AverageThermalNum; i++) {
- if (pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i]) {
- ThermalValue_AVG += pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i];
- ThermalValue_AVG_count++;
- }
- }
-
- if (ThermalValue_AVG_count) {/*Calculate Average ThermalValue after average enough times*/
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("ThermalValue_AVG=0x%x(%d) ThermalValue_AVG_count = %d\n"
- , ThermalValue_AVG, ThermalValue_AVG, ThermalValue_AVG_count));
-
- ThermalValue = (u1Byte)(ThermalValue_AVG / ThermalValue_AVG_count);
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("AVG Thermal Meter = 0x%X(%d), EEPROMthermalmeter = 0x%X(%d)\n", ThermalValue, ThermalValue, priv->pmib->dot11RFEntry.ther, priv->pmib->dot11RFEntry.ther));
- }
-
- /*4 Calculate delta, delta_LCK, delta_IQK.*/
- delta = RTL_ABS(ThermalValue, priv->pmib->dot11RFEntry.ther);
- delta_LCK = RTL_ABS(ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue_LCK);
- delta_IQK = RTL_ABS(ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue_IQK);
- is_increase = ((ThermalValue < priv->pmib->dot11RFEntry.ther) ? 0 : 1);
-
- if (delta > 29) { /* power track table index(thermal diff.) upper bound*/
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta(%d) > 29, set delta to 29\n", delta));
- delta = 29;
- }
-
-
- /*4 if necessary, do LCK.*/
-
- if (delta_LCK > c.Threshold_IQK) {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= Threshold_IQK(%d)\n", delta_LCK, c.Threshold_IQK));
- pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue;
- if (c.PHY_LCCalibrate)
- (*c.PHY_LCCalibrate)(pDM_Odm);
- }
-
- if (delta_IQK > c.Threshold_IQK) {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_IQK(%d) >= Threshold_IQK(%d)\n", delta_IQK, c.Threshold_IQK));
- pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = ThermalValue;
- if (c.DoIQK)
- (*c.DoIQK)(pDM_Odm, TRUE, 0, 0);
- }
-
- if (!priv->pmib->dot11RFEntry.ther) /*Don't do power tracking since no calibrated thermal value*/
- return;
-
- /*4 Do Power Tracking*/
-
- if (ThermalValue != pDM_Odm->RFCalibrateInfo.ThermalValue) {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("\n\n******** START POWER TRACKING ********\n"));
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("Readback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n",
- ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue, priv->pmib->dot11RFEntry.ther));
-
-#ifdef _TRACKING_TABLE_FILE
- if (priv->pshare->rf_ft_var.pwr_track_file) {
- if (is_increase) { /*thermal is higher than base*/
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) {
- switch (p) {
- case ODM_RF_PATH_B:
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("deltaSwingTableIdx_TUP_B[%d] = %d deltaSwingTableIdx_TUP_CCK_B[%d] = %d\n", delta, deltaSwingTableIdx_TUP_B[delta], delta, deltaSwingTableIdx_TUP_CCK_B[delta]));
- pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_B[delta];
- pRFCalibrateInfo->Absolute_CCKSwingIdx[p] = deltaSwingTableIdx_TUP_CCK_B[delta];
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("******Temp is higher and pRF->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d pRF->Absolute_CCKSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p], pRFCalibrateInfo->Absolute_CCKSwingIdx[p]));
- break;
-
- case ODM_RF_PATH_C:
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("deltaSwingTableIdx_TUP_C[%d] = %d deltaSwingTableIdx_TUP_CCK_C[%d] = %d\n", delta, deltaSwingTableIdx_TUP_C[delta], delta, deltaSwingTableIdx_TUP_CCK_C[delta]));
- pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_C[delta];
- pRFCalibrateInfo->Absolute_CCKSwingIdx[p] = deltaSwingTableIdx_TUP_CCK_C[delta];
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("******Temp is higher and pRF->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d pRF->Absolute_CCKSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p], pRFCalibrateInfo->Absolute_CCKSwingIdx[p]));
- break;
-
- case ODM_RF_PATH_D:
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("deltaSwingTableIdx_TUP_D[%d] = %d deltaSwingTableIdx_TUP_CCK_D[%d] = %d\n", delta, deltaSwingTableIdx_TUP_D[delta], delta, deltaSwingTableIdx_TUP_CCK_D[delta]));
- pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_D[delta];
- pRFCalibrateInfo->Absolute_CCKSwingIdx[p] = deltaSwingTableIdx_TUP_CCK_D[delta];
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("******Temp is higher and pRF->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d pRF->Absolute_CCKSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p], pRFCalibrateInfo->Absolute_CCKSwingIdx[p]));
- break;
- default:
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("deltaSwingTableIdx_TUP_A[%d] = %d deltaSwingTableIdx_TUP_CCK_A[%d] = %d\n", delta, deltaSwingTableIdx_TUP_A[delta], delta, deltaSwingTableIdx_TUP_CCK_A[delta]));
- pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_A[delta];
- pRFCalibrateInfo->Absolute_CCKSwingIdx[p] = deltaSwingTableIdx_TUP_CCK_A[delta];
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("******Temp is higher and pRF->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d pRF->Absolute_CCKSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p], pRFCalibrateInfo->Absolute_CCKSwingIdx[p]));
- break;
- }
- }
- } else { /* thermal is lower than base*/
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) {
- switch (p) {
- case ODM_RF_PATH_B:
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("deltaSwingTableIdx_TDOWN_B[%d] = %d deltaSwingTableIdx_TDOWN_CCK_B[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_B[delta], delta, deltaSwingTableIdx_TDOWN_CCK_B[delta]));
- pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_B[delta];
- pRFCalibrateInfo->Absolute_CCKSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_CCK_B[delta];
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("******Temp is lower and pRF->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d pRF->Absolute_CCKSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p], pRFCalibrateInfo->Absolute_CCKSwingIdx[p]));
- break;
-
- case ODM_RF_PATH_C:
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("deltaSwingTableIdx_TDOWN_C[%d] = %d deltaSwingTableIdx_TDOWN_CCK_C[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_C[delta], delta, deltaSwingTableIdx_TDOWN_CCK_C[delta]));
- pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_C[delta];
- pRFCalibrateInfo->Absolute_CCKSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_CCK_C[delta];
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("******Temp is lower and pRF->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d pRF->Absolute_CCKSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p], pRFCalibrateInfo->Absolute_CCKSwingIdx[p]));
- break;
-
- case ODM_RF_PATH_D:
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("deltaSwingTableIdx_TDOWN_D[%d] = %d deltaSwingTableIdx_TDOWN_CCK_D[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_D[delta], delta, deltaSwingTableIdx_TDOWN_CCK_D[delta]));
- pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_D[delta];
- pRFCalibrateInfo->Absolute_CCKSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_CCK_D[delta];
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("******Temp is lower and pRF->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d pRF->Absolute_CCKSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p], pRFCalibrateInfo->Absolute_CCKSwingIdx[p]));
- break;
-
- default:
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("deltaSwingTableIdx_TDOWN_A[%d] = %d deltaSwingTableIdx_TDOWN_CCK_A[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_A[delta], delta, deltaSwingTableIdx_TDOWN_CCK_A[delta]));
- pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_A[delta];
- pRFCalibrateInfo->Absolute_CCKSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_CCK_A[delta];
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("******Temp is lower and pRF->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d pRF->Absolute_CCKSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p], pRFCalibrateInfo->Absolute_CCKSwingIdx[p]));
- break;
- }
- }
- }
-
- if (is_increase) {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, (">>> increse power --->\n"));
- if (GET_CHIP_VER(priv) == VERSION_8197F) {
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
- (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, p, 0);
- } else if (GET_CHIP_VER(priv) == VERSION_8822B) {
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
- (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0);
- }
- } else {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, (">>> decrese power --->\n"));
- if (GET_CHIP_VER(priv) == VERSION_8197F) {
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
- (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, p, 0);
- } else if (GET_CHIP_VER(priv) == VERSION_8822B) {
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
- (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0);
- }
- }
- }
-#endif
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\n******** END:%s() ********\n\n", __func__));
- /*update thermal meter value*/
- pDM_Odm->RFCalibrateInfo.ThermalValue = ThermalValue;
-
- }
-
-#endif
-}
-#endif
-
-/*#if (RTL8814A_SUPPORT == 1)*/
-#if (RTL8814A_SUPPORT == 1)
-
-VOID
-ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries2(
-#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
- IN PVOID pDM_VOID
-#else
- IN PADAPTER Adapter
-#endif
- )
-{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- u1Byte ThermalValue = 0, delta, delta_LCK, delta_IQK, channel, is_increase;
- u1Byte ThermalValue_AVG_count = 0, p = 0, i = 0;
- u4Byte ThermalValue_AVG = 0, Reg0x18;
- u4Byte BBSwingReg[4] = {rA_TxScale_Jaguar,rB_TxScale_Jaguar,rC_TxScale_Jaguar2,rD_TxScale_Jaguar2};
- s4Byte ele_D;
- u4Byte BBswingIdx;
- prtl8192cd_priv priv = pDM_Odm->priv;
- TXPWRTRACK_CFG c;
- BOOLEAN bTSSIenable = FALSE;
- PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
-
- //4 1. The following TWO tables decide the final index of OFDM/CCK swing table.
- pu1Byte deltaSwingTableIdx_TUP_A = NULL, deltaSwingTableIdx_TDOWN_A = NULL;
- pu1Byte deltaSwingTableIdx_TUP_B = NULL, deltaSwingTableIdx_TDOWN_B = NULL;
- //for 8814 add by Yu Chen
- pu1Byte deltaSwingTableIdx_TUP_C = NULL, deltaSwingTableIdx_TDOWN_C = NULL;
- pu1Byte deltaSwingTableIdx_TUP_D = NULL, deltaSwingTableIdx_TDOWN_D = NULL;
-
-#ifdef MP_TEST
- if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) {
- channel = priv->pshare->working_channel;
- if (priv->pshare->mp_txpwr_tracking == FALSE)
- return;
- } else
-#endif
- {
- channel = (priv->pmib->dot11RFEntry.dot11channel);
- }
-
- ConfigureTxpowerTrack(pDM_Odm, &c);
- pRFCalibrateInfo->DefaultOfdmIndex = priv->pshare->OFDM_index0[ODM_RF_PATH_A];
-
- (*c.GetDeltaSwingTable)(pDM_Odm, (pu1Byte*)&deltaSwingTableIdx_TUP_A, (pu1Byte*)&deltaSwingTableIdx_TDOWN_A,
- (pu1Byte*)&deltaSwingTableIdx_TUP_B, (pu1Byte*)&deltaSwingTableIdx_TDOWN_B);
-
- if(pDM_Odm->SupportICType & ODM_RTL8814A) // for 8814 path C & D
- (*c.GetDeltaSwingTable8814only)(pDM_Odm, (pu1Byte*)&deltaSwingTableIdx_TUP_C, (pu1Byte*)&deltaSwingTableIdx_TDOWN_C,
- (pu1Byte*)&deltaSwingTableIdx_TUP_D, (pu1Byte*)&deltaSwingTableIdx_TDOWN_D);
-
- ThermalValue = (u1Byte)ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, c.ThermalRegAddr, 0xfc00); //0x42: RF Reg[15:10] 88E
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("\nReadback Thermal Meter = 0x%x, pre thermal meter 0x%x, EEPROMthermalmeter 0x%x\n", ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue, priv->pmib->dot11RFEntry.ther));
-
- /* Initialize */
- if (!pDM_Odm->RFCalibrateInfo.ThermalValue) {
- pDM_Odm->RFCalibrateInfo.ThermalValue = priv->pmib->dot11RFEntry.ther;
- }
-
- if (!pDM_Odm->RFCalibrateInfo.ThermalValue_LCK) {
- pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = priv->pmib->dot11RFEntry.ther;
- }
-
- if (!pDM_Odm->RFCalibrateInfo.ThermalValue_IQK) {
- pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = priv->pmib->dot11RFEntry.ther;
- }
-
- bTSSIenable = (BOOLEAN)ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, rRF_TxGainOffset, BIT7); // check TSSI enable
-
- //4 Query OFDM BB swing default setting Bit[31:21]
- for(p = ODM_RF_PATH_A ; p < c.RfPathCount ; p++)
- {
- ele_D = ODM_GetBBReg(pDM_Odm, BBSwingReg[p], 0xffe00000);
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("0x%x:0x%x ([31:21] = 0x%x)\n", BBSwingReg[p], ODM_GetBBReg(pDM_Odm, BBSwingReg[p], bMaskDWord), ele_D));
-
- for (BBswingIdx = 0; BBswingIdx < TXSCALE_TABLE_SIZE; BBswingIdx++) {//4
- if (ele_D == TxScalingTable_Jaguar[BBswingIdx]) {
- pDM_Odm->RFCalibrateInfo.OFDM_index[p] = (u1Byte)BBswingIdx;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("OFDM_index[%d]=%d\n",p, pDM_Odm->RFCalibrateInfo.OFDM_index[p]));
- break;
- }
- }
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("KfreeOffset[%d]=%d\n",p, pRFCalibrateInfo->KfreeOffset[p]));
-
- }
-
- /* calculate average thermal meter */
- pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index] = ThermalValue;
- pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index++;
- if(pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index == c.AverageThermalNum) //Average times = c.AverageThermalNum
- pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index = 0;
-
- for(i = 0; i < c.AverageThermalNum; i++)
- {
- if(pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i])
- {
- ThermalValue_AVG += pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i];
- ThermalValue_AVG_count++;
- }
- }
-
- if(ThermalValue_AVG_count) //Calculate Average ThermalValue after average enough times
- {
- ThermalValue = (u1Byte)(ThermalValue_AVG / ThermalValue_AVG_count);
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("AVG Thermal Meter = 0x%X, EEPROMthermalmeter = 0x%X\n", ThermalValue, priv->pmib->dot11RFEntry.ther));
- }
-
- //4 Calculate delta, delta_LCK, delta_IQK.
- delta = RTL_ABS(ThermalValue, priv->pmib->dot11RFEntry.ther);
- delta_LCK = RTL_ABS(ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue_LCK);
- delta_IQK = RTL_ABS(ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue_IQK);
- is_increase = ((ThermalValue < priv->pmib->dot11RFEntry.ther) ? 0 : 1);
-
- //4 if necessary, do LCK.
- if (!(pDM_Odm->SupportICType & ODM_RTL8821)) {
- if (delta_LCK > c.Threshold_IQK) {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= Threshold_IQK(%d)\n", delta_LCK, c.Threshold_IQK));
- pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue;
-
- /*Use RTLCK, so close power tracking driver LCK*/
- #if (RTL8814A_SUPPORT != 1)
- if (!(pDM_Odm->SupportICType & ODM_RTL8814A)) {
- if (c.PHY_LCCalibrate)
- (*c.PHY_LCCalibrate)(pDM_Odm);
- }
- #endif
- }
- }
-
- if (delta_IQK > c.Threshold_IQK)
- {
- panic_printk("%s(%d)\n", __FUNCTION__, __LINE__);
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_IQK(%d) >= Threshold_IQK(%d)\n", delta_IQK, c.Threshold_IQK));
- pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = ThermalValue;
- if(c.DoIQK)
- (*c.DoIQK)(pDM_Odm, TRUE, 0, 0);
- }
-
- if(!priv->pmib->dot11RFEntry.ther) /*Don't do power tracking since no calibrated thermal value*/
- return;
-
- //4 Do Power Tracking
-
- if(bTSSIenable == TRUE)
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("**********Enter PURE TSSI MODE**********\n"));
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
- (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, TSSI_MODE, p, 0);
- }
- else if (ThermalValue != pDM_Odm->RFCalibrateInfo.ThermalValue)
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("\n******** START POWER TRACKING ********\n"));
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue, priv->pmib->dot11RFEntry.ther));
-
-#ifdef _TRACKING_TABLE_FILE
- if (priv->pshare->rf_ft_var.pwr_track_file)
- {
- if (is_increase) // thermal is higher than base
- {
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
- {
- switch(p)
- {
- case ODM_RF_PATH_B:
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("deltaSwingTableIdx_TUP_B[%d] = %d\n", delta, deltaSwingTableIdx_TUP_B[delta]));
- pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_B[delta]; // Record delta swing for mix mode power tracking
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("******Temp is higher and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
- break;
-
- case ODM_RF_PATH_C:
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("deltaSwingTableIdx_TUP_C[%d] = %d\n", delta, deltaSwingTableIdx_TUP_C[delta]));
- pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_C[delta]; // Record delta swing for mix mode power tracking
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("******Temp is higher and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
- break;
-
- case ODM_RF_PATH_D:
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("deltaSwingTableIdx_TUP_D[%d] = %d\n", delta, deltaSwingTableIdx_TUP_D[delta]));
- pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_D[delta]; // Record delta swing for mix mode power tracking
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("******Temp is higher and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
- break;
-
- default:
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("deltaSwingTableIdx_TUP_A[%d] = %d\n", delta, deltaSwingTableIdx_TUP_A[delta]));
- pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_A[delta]; // Record delta swing for mix mode power tracking
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("******Temp is higher and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
- break;
- }
- }
- }
- else // thermal is lower than base
- {
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
- {
- switch(p)
- {
- case ODM_RF_PATH_B:
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("deltaSwingTableIdx_TDOWN_B[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_B[delta]));
- pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_B[delta]; // Record delta swing for mix mode power tracking
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("******Temp is lower and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
- break;
-
- case ODM_RF_PATH_C:
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("deltaSwingTableIdx_TDOWN_C[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_C[delta]));
- pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_C[delta]; // Record delta swing for mix mode power tracking
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("******Temp is lower and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
- break;
-
- case ODM_RF_PATH_D:
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("deltaSwingTableIdx_TDOWN_D[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_D[delta]));
- pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_D[delta]; // Record delta swing for mix mode power tracking
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("******Temp is lower and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
- break;
-
- default:
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("deltaSwingTableIdx_TDOWN_A[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_A[delta]));
- pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_A[delta]; // Record delta swing for mix mode power tracking
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("******Temp is lower and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
- break;
- }
- }
- }
-
- if (is_increase)
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> increse power ---> \n"));
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
- (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0);
- }
- else
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> decrese power --->\n"));
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
- (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0);
- }
- }
-#endif
-
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\n******** END:%s() ********\n", __FUNCTION__));
- //update thermal meter value
- pDM_Odm->RFCalibrateInfo.ThermalValue = ThermalValue;
-
- }
-}
-#endif
-
-#if (RTL8812A_SUPPORT == 1 || RTL8881A_SUPPORT == 1)
-VOID
-ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries(
-#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
- IN PVOID pDM_VOID
-#else
- IN PADAPTER Adapter
-#endif
- )
-{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- unsigned char ThermalValue = 0, delta, delta_LCK, channel, is_decrease;
- unsigned char ThermalValue_AVG_count = 0;
- unsigned int ThermalValue_AVG = 0, Reg0x18;
- unsigned int BBSwingReg[4]={0xc1c,0xe1c,0x181c,0x1a1c};
- int ele_D, value32;
- char OFDM_index[2], index;
- unsigned int i = 0, j = 0, rf_path, max_rf_path =2 ,rf;
- prtl8192cd_priv priv = pDM_Odm->priv;
- unsigned char OFDM_min_index = 7; //OFDM BB Swing should be less than +2.5dB, which is required by Arthur and Mimic
-
-
-
-#ifdef MP_TEST
- if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) {
- channel = priv->pshare->working_channel;
- if (priv->pshare->mp_txpwr_tracking == FALSE)
- return;
- } else
-#endif
- {
- channel = (priv->pmib->dot11RFEntry.dot11channel);
- }
-
-#if RTL8881A_SUPPORT
- if (pDM_Odm->SupportICType == ODM_RTL8881A) {
- max_rf_path = 1;
- if ((get_bonding_type_8881A() == BOND_8881AM ||get_bonding_type_8881A() == BOND_8881AN)
- && priv->pshare->rf_ft_var.use_intpa8881A && (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G))
- OFDM_min_index = 6; // intPA - upper bond set to +3 dB (base: -2 dB)ot11RFEntry.phyBandSelect == PHY_BAND_2G))
- else
- OFDM_min_index = 10; //OFDM BB Swing should be less than +1dB, which is required by Arthur and Mimic
- }
-#endif
-
-
- ThermalValue = (unsigned char)PHY_QueryRFReg(priv, RF_PATH_A, 0x42, 0xfc00, 1); //0x42: RF Reg[15:10] 88E
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", ThermalValue, priv->pshare->ThermalValue, priv->pmib->dot11RFEntry.ther));
-
-
- //4 Query OFDM BB swing default setting Bit[31:21]
- for(rf_path = 0 ; rf_path < max_rf_path ; rf_path++){
- ele_D = PHY_QueryBBReg(priv, BBSwingReg[rf_path], 0xffe00000);
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("0x%x:0x%x ([31:21] = 0x%x)\n",BBSwingReg[rf_path], PHY_QueryBBReg(priv, BBSwingReg[rf_path], bMaskDWord),ele_D));
- for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {//4
- if (ele_D == OFDMSwingTable_8812[i]) {
- OFDM_index[rf_path] = (unsigned char)i;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("OFDM_index[%d]=%d\n",rf_path, OFDM_index[rf_path]));
- break;
- }
- }
- }
-#if 0
- //Query OFDM path A default setting Bit[31:21]
- ele_D = PHY_QueryBBReg(priv, 0xc1c, 0xffe00000);
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("0xc1c:0x%x ([31:21] = 0x%x)\n", PHY_QueryBBReg(priv, 0xc1c, bMaskDWord),ele_D));
- for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {//4
- if (ele_D == OFDMSwingTable_8812[i]) {
- OFDM_index[0] = (unsigned char)i;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("OFDM_index[0]=%d\n", OFDM_index[0]));
- break;
- }
- }
- //Query OFDM path B default setting
- if (rf == 2) {
- ele_D = PHY_QueryBBReg(priv, 0xe1c, 0xffe00000);
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("0xe1c:0x%x ([32:21] = 0x%x)\n", PHY_QueryBBReg(priv, 0xe1c, bMaskDWord),ele_D));
- for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {
- if (ele_D == OFDMSwingTable_8812[i]) {
- OFDM_index[1] = (unsigned char)i;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("OFDM_index[1]=%d\n", OFDM_index[1]));
- break;
- }
- }
- }
-#endif
- /* Initialize */
- if (!priv->pshare->ThermalValue) {
- priv->pshare->ThermalValue = priv->pmib->dot11RFEntry.ther;
- priv->pshare->ThermalValue_LCK = ThermalValue;
- }
-
- /* calculate average thermal meter */
- {
- priv->pshare->ThermalValue_AVG_8812[priv->pshare->ThermalValue_AVG_index_8812] = ThermalValue;
- priv->pshare->ThermalValue_AVG_index_8812++;
- if (priv->pshare->ThermalValue_AVG_index_8812 == AVG_THERMAL_NUM_8812)
- priv->pshare->ThermalValue_AVG_index_8812 = 0;
-
- for (i = 0; i < AVG_THERMAL_NUM_8812; i++) {
- if (priv->pshare->ThermalValue_AVG_8812[i]) {
- ThermalValue_AVG += priv->pshare->ThermalValue_AVG_8812[i];
- ThermalValue_AVG_count++;
- }
- }
-
- if (ThermalValue_AVG_count) {
- ThermalValue = (unsigned char)(ThermalValue_AVG / ThermalValue_AVG_count);
- //printk("AVG Thermal Meter = 0x%x \n", ThermalValue);
- }
- }
-
-
- //4 If necessary, do power tracking
-
- if(!priv->pmib->dot11RFEntry.ther) /*Don't do power tracking since no calibrated thermal value*/
- return;
-
- if (ThermalValue != priv->pshare->ThermalValue) {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\n******** START POWER TRACKING ********\n"));
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", ThermalValue, priv->pshare->ThermalValue, priv->pmib->dot11RFEntry.ther));
- delta = RTL_ABS(ThermalValue, priv->pmib->dot11RFEntry.ther);
- delta_LCK = RTL_ABS(ThermalValue, priv->pshare->ThermalValue_LCK);
- is_decrease = ((ThermalValue < priv->pmib->dot11RFEntry.ther) ? 1 : 0);
- //if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G)
- {
-#ifdef _TRACKING_TABLE_FILE
- if (priv->pshare->rf_ft_var.pwr_track_file) {
- for (rf_path = 0; rf_path < max_rf_path; rf_path++) {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("Diff: (%s)%d ==> get index from table : %d)\n", (is_decrease?"-":"+"), delta, get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0)));
- if (is_decrease) {
- OFDM_index[rf_path] = priv->pshare->OFDM_index0[rf_path] + get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0);
- OFDM_index[rf_path] = ((OFDM_index[rf_path] > (OFDM_TABLE_SIZE_8812 - 1)) ? (OFDM_TABLE_SIZE_8812 - 1) : OFDM_index[rf_path]);
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[rf_path], priv->pshare->OFDM_index0[rf_path], get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0)));
-#if 0// RTL8881A_SUPPORT
- if (pDM_Odm->SupportICType == ODM_RTL8881A){
- if(priv->pshare->rf_ft_var.pwrtrk_TxAGC_enable){
- if(priv->pshare->AddTxAGC){//TxAGC has been added
- AddTxPower88XX_AC(priv,0);
- priv->pshare->AddTxAGC = 0;
- priv->pshare->AddTxAGC_index = 0;
- }
- }
- }
-#endif
- } else {
-
- OFDM_index[rf_path] = priv->pshare->OFDM_index0[rf_path] - get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0);
-#if 0// RTL8881A_SUPPORT
- if(pDM_Odm->SupportICType == ODM_RTL8881A){
- if(priv->pshare->rf_ft_var.pwrtrk_TxAGC_enable){
- if(OFDM_index[i] < OFDM_min_index){
- priv->pshare->AddTxAGC_index = (OFDM_min_index - OFDM_index[i])/2; // Calculate Remnant TxAGC Value, 2 index for 1 TxAGC
- AddTxPower88XX_AC(priv,priv->pshare->AddTxAGC_index);
- priv->pshare->AddTxAGC = 1; //AddTxAGC Flag = 1
- OFDM_index[i] = OFDM_min_index;
- }
- else{
- if(priv->pshare->AddTxAGC){// TxAGC been added
- priv->pshare->AddTxAGC = 0;
- priv->pshare->AddTxAGC_index = 0;
- AddTxPower88XX_AC(priv,0); //minus the added TPI
- }
- }
- }
- }
-#else
- OFDM_index[rf_path] = ((OFDM_index[rf_path] < OFDM_min_index) ? OFDM_min_index : OFDM_index[rf_path]);
-#endif
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[rf_path], priv->pshare->OFDM_index0[rf_path], get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0)));
- }
- }
- }
-#endif
- //4 Set new BB swing index
- for (rf_path = 0; rf_path < max_rf_path; rf_path++) {
- PHY_SetBBReg(priv, BBSwingReg[rf_path], 0xffe00000, OFDMSwingTable_8812[(unsigned int)OFDM_index[rf_path]]);
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("Readback 0x%x[31:21] = 0x%x, OFDM_index:%d\n",BBSwingReg[rf_path], PHY_QueryBBReg(priv, BBSwingReg[rf_path], 0xffe00000), OFDM_index[rf_path]));
- }
-
- }
- if (delta_LCK > 8) {
- RTL_W8(0x522, 0xff);
- Reg0x18 = PHY_QueryRFReg(priv, RF_PATH_A, 0x18, bMask20Bits, 1);
- PHY_SetRFReg(priv, RF_PATH_A, 0xB4, BIT(14), 1);
- PHY_SetRFReg(priv, RF_PATH_A, 0x18, BIT(15), 1);
- delay_ms(200); // frequency deviation
- PHY_SetRFReg(priv, RF_PATH_A, 0xB4, BIT(14), 0);
- PHY_SetRFReg(priv, RF_PATH_A, 0x18, bMask20Bits, Reg0x18);
- #ifdef CONFIG_RTL_8812_SUPPORT
- if (GET_CHIP_VER(priv)== VERSION_8812E)
- UpdateBBRFVal8812(priv, priv->pmib->dot11RFEntry.dot11channel);
- #endif
- RTL_W8(0x522, 0x0);
- priv->pshare->ThermalValue_LCK = ThermalValue;
- }
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\n******** END:%s() ********\n", __FUNCTION__));
-
- //update thermal meter value
- priv->pshare->ThermalValue = ThermalValue;
- for (rf_path = 0; rf_path < max_rf_path; rf_path++)
- priv->pshare->OFDM_index[rf_path] = OFDM_index[rf_path];
- }
-}
-
-#endif
-
-
-VOID
-ODM_TXPowerTrackingCallback_ThermalMeter(
-#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
- IN PVOID pDM_VOID
-#else
- IN PADAPTER Adapter
-#endif
- )
-{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
-
-
-#if (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1)
- if (pDM_Odm->SupportICType == ODM_RTL8197F || pDM_Odm->SupportICType == ODM_RTL8822B) {
- ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries3(pDM_Odm);
- return;
- }
-#endif
-#if (RTL8814A_SUPPORT == 1) /*use this function to do power tracking after 8814 by YuChen*/
- if (pDM_Odm->SupportICType & ODM_RTL8814A) {
- ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries2(pDM_Odm);
- return;
- }
-#endif
-#if (RTL8881A_SUPPORT || RTL8812A_SUPPORT == 1)
- if (pDM_Odm->SupportICType & ODM_RTL8812 || pDM_Odm->SupportICType & ODM_RTL8881A) {
- ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries(pDM_Odm);
- return;
- }
-#endif
-
-#if (RTL8192E_SUPPORT == 1)
- if (pDM_Odm->SupportICType==ODM_RTL8192E) {
- ODM_TXPowerTrackingCallback_ThermalMeter_92E(pDM_Odm);
- return;
- }
-#endif
-
-#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
- //PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
-#endif
-
-
- u1Byte ThermalValue = 0, delta, delta_LCK, delta_IQK, offset;
- u1Byte ThermalValue_AVG_count = 0;
- u4Byte ThermalValue_AVG = 0;
-// s4Byte ele_A=0, ele_D, TempCCk, X, value32;
-// s4Byte Y, ele_C=0;
-// s1Byte OFDM_index[2], CCK_index=0, OFDM_index_old[2]={0,0}, CCK_index_old=0, index;
-// s1Byte deltaPowerIndex = 0;
- u4Byte i = 0;//, j = 0;
- BOOLEAN is2T = FALSE;
-// BOOLEAN bInteralPA = FALSE;
-
- u1Byte OFDM_max_index = 34, rf = (is2T) ? 2 : 1; //OFDM BB Swing should be less than +3.0dB, which is required by Arthur
- u1Byte Indexforchannel = 0;/*GetRightChnlPlaceforIQK(pHalData->CurrentChannel)*/
- enum _POWER_DEC_INC { POWER_DEC, POWER_INC };
- #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
- PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
- #endif
- #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
- PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
- #endif
-
- TXPWRTRACK_CFG c;
-
-
- //4 1. The following TWO tables decide the final index of OFDM/CCK swing table.
- s1Byte deltaSwingTableIdx[2][index_mapping_NUM_88E] = {
- // {{Power decreasing(lower temperature)}, {Power increasing(higher temperature)}}
- {0,0,2,3,4,4,5,6,7,7,8,9,10,10,11}, {0,0,1,2,3,4,4,4,4,5,7,8,9,9,10}
- };
- u1Byte thermalThreshold[2][index_mapping_NUM_88E]={
- // {{Power decreasing(lower temperature)}, {Power increasing(higher temperature)}}
- {0,2,4,6,8,10,12,14,16,18,20,22,24,26,27}, {0,2,4,6,8,10,12,14,16,18,20,22,25,25,25}
- };
-
-#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
- prtl8192cd_priv priv = pDM_Odm->priv;
-#endif
-
- //4 2. Initilization ( 7 steps in total )
-
- ConfigureTxpowerTrack(pDM_Odm, &c);
-
- pDM_Odm->RFCalibrateInfo.TXPowerTrackingCallbackCnt++; //cosa add for debug
- pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = TRUE;
-
-#if (MP_DRIVER == 1)
- pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = pHalData->TxPowerTrackControl; // We should keep updating the control variable according to HalData.
- // RFCalibrateInfo.RegA24 will be initialized when ODM HW configuring, but MP configures with para files.
- pDM_Odm->RFCalibrateInfo.RegA24 = 0x090e1317;
-#endif
-
-#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && defined(MP_TEST)
- if ((OPMODE & WIFI_MP_STATE) || pDM_Odm->priv->pshare->rf_ft_var.mp_specific) {
- if(pDM_Odm->priv->pshare->mp_txpwr_tracking == FALSE)
- return;
- }
-#endif
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("===>odm_TXPowerTrackingCallback_ThermalMeter_8188E, pDM_Odm->BbSwingIdxCckBase: %d, pDM_Odm->BbSwingIdxOfdmBase: %d \n", pRFCalibrateInfo->BbSwingIdxCckBase, pRFCalibrateInfo->BbSwingIdxOfdmBase));
-/*
- if (!pDM_Odm->RFCalibrateInfo.TM_Trigger) {
- ODM_SetRFReg(pDM_Odm, RF_PATH_A, c.ThermalRegAddr, BIT17 | BIT16, 0x3);
- pDM_Odm->RFCalibrateInfo.TM_Trigger = 1;
- return;
- }
-*/
- ThermalValue = (u1Byte)ODM_GetRFReg(pDM_Odm, RF_PATH_A, c.ThermalRegAddr, 0xfc00); //0x42: RF Reg[15:10] 88E
-#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
- if( ! ThermalValue || ! pDM_Odm->RFCalibrateInfo.TxPowerTrackControl)
-#else
- if( ! pDM_Odm->RFCalibrateInfo.TxPowerTrackControl)
-#endif
- return;
-
- //4 3. Initialize ThermalValues of RFCalibrateInfo
-
- if( ! pDM_Odm->RFCalibrateInfo.ThermalValue)
- {
- pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue;
- pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = ThermalValue;
- }
-
- if(pDM_Odm->RFCalibrateInfo.bReloadtxpowerindex)
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("reload ofdm index for band switch\n"));
- }
-
- //4 4. Calculate average thermal meter
-
- pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index] = ThermalValue;
- pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index++;
- if(pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index == c.AverageThermalNum)
- pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index = 0;
-
- for(i = 0; i < c.AverageThermalNum; i++)
- {
- if(pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i])
- {
- ThermalValue_AVG += pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i];
- ThermalValue_AVG_count++;
- }
- }
-
- if(ThermalValue_AVG_count)
- {
- // Give the new thermo value a weighting
- ThermalValue_AVG += (ThermalValue*4);
-
- ThermalValue = (u1Byte)(ThermalValue_AVG / (ThermalValue_AVG_count+4));
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("AVG Thermal Meter = 0x%x \n", ThermalValue));
- }
-
- //4 5. Calculate delta, delta_LCK, delta_IQK.
-
- delta = (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue)?(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue):(pDM_Odm->RFCalibrateInfo.ThermalValue - ThermalValue);
- delta_LCK = (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue_LCK)?(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue_LCK):(pDM_Odm->RFCalibrateInfo.ThermalValue_LCK - ThermalValue);
- delta_IQK = (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue_IQK)?(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK):(pDM_Odm->RFCalibrateInfo.ThermalValue_IQK - ThermalValue);
-
- //4 6. If necessary, do LCK.
- if (!(pDM_Odm->SupportICType & ODM_RTL8821)) {
- /*if((delta_LCK > pHalData->Delta_LCK) && (pHalData->Delta_LCK != 0))*/
- if (delta_LCK >= c.Threshold_IQK) {
- /*Delta temperature is equal to or larger than 20 centigrade.*/
- pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue;
- (*c.PHY_LCCalibrate)(pDM_Odm);
- }
- }
-
- //3 7. If necessary, move the index of swing table to adjust Tx power.
-
- if (delta > 0 && pDM_Odm->RFCalibrateInfo.TxPowerTrackControl)
- {
-#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
- delta = ThermalValue > pHalData->EEPROMThermalMeter?(ThermalValue - pHalData->EEPROMThermalMeter):(pHalData->EEPROMThermalMeter - ThermalValue);
-#else
- delta = (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther)?(ThermalValue - pDM_Odm->priv->pmib->dot11RFEntry.ther):(pDM_Odm->priv->pmib->dot11RFEntry.ther - ThermalValue);
-#endif
-
-
- //4 7.1 The Final Power Index = BaseIndex + PowerIndexOffset
-
-#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
- if(ThermalValue > pHalData->EEPROMThermalMeter) {
-#else
- if(ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) {
-#endif
- CALCULATE_SWINGTALBE_OFFSET(offset, POWER_INC, index_mapping_NUM_88E, delta);
- pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex;
- pDM_Odm->RFCalibrateInfo.DeltaPowerIndex = deltaSwingTableIdx[POWER_INC][offset];
-
- } else {
-
- CALCULATE_SWINGTALBE_OFFSET(offset, POWER_DEC, index_mapping_NUM_88E, delta);
- pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex;
- pDM_Odm->RFCalibrateInfo.DeltaPowerIndex = (-1)*deltaSwingTableIdx[POWER_DEC][offset];
- }
-
- if (pDM_Odm->RFCalibrateInfo.DeltaPowerIndex == pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast)
- pDM_Odm->RFCalibrateInfo.PowerIndexOffset = 0;
- else
- pDM_Odm->RFCalibrateInfo.PowerIndexOffset = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex - pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast;
-
- for(i = 0; i < rf; i++)
- pDM_Odm->RFCalibrateInfo.OFDM_index[i] = pRFCalibrateInfo->BbSwingIdxOfdmBase + pDM_Odm->RFCalibrateInfo.PowerIndexOffset;
- pDM_Odm->RFCalibrateInfo.CCK_index = pRFCalibrateInfo->BbSwingIdxCckBase + pDM_Odm->RFCalibrateInfo.PowerIndexOffset;
-
- pRFCalibrateInfo->BbSwingIdxCck = pDM_Odm->RFCalibrateInfo.CCK_index;
- pRFCalibrateInfo->BbSwingIdxOfdm[RF_PATH_A] = pDM_Odm->RFCalibrateInfo.OFDM_index[RF_PATH_A];
-
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("The 'CCK' final index(%d) = BaseIndex(%d) + PowerIndexOffset(%d)\n", pRFCalibrateInfo->BbSwingIdxCck, pRFCalibrateInfo->BbSwingIdxCckBase, pDM_Odm->RFCalibrateInfo.PowerIndexOffset));
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("The 'OFDM' final index(%d) = BaseIndex(%d) + PowerIndexOffset(%d)\n", pRFCalibrateInfo->BbSwingIdxOfdm[RF_PATH_A], pRFCalibrateInfo->BbSwingIdxOfdmBase, pDM_Odm->RFCalibrateInfo.PowerIndexOffset));
-
- //4 7.1 Handle boundary conditions of index.
-
-
- for(i = 0; i < rf; i++)
- {
- if(pDM_Odm->RFCalibrateInfo.OFDM_index[i] > OFDM_max_index)
- {
- pDM_Odm->RFCalibrateInfo.OFDM_index[i] = OFDM_max_index;
- }
- else if (pDM_Odm->RFCalibrateInfo.OFDM_index[i] < 0)
- {
- pDM_Odm->RFCalibrateInfo.OFDM_index[i] = 0;
- }
- }
-
- if(pDM_Odm->RFCalibrateInfo.CCK_index > c.SwingTableSize_CCK-1)
- pDM_Odm->RFCalibrateInfo.CCK_index = c.SwingTableSize_CCK-1;
- else if (pDM_Odm->RFCalibrateInfo.CCK_index < 0)
- pDM_Odm->RFCalibrateInfo.CCK_index = 0;
- }
- else
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("The thermal meter is unchanged or TxPowerTracking OFF: ThermalValue: %d , pDM_Odm->RFCalibrateInfo.ThermalValue: %d)\n", ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue));
- pDM_Odm->RFCalibrateInfo.PowerIndexOffset = 0;
- }
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("TxPowerTracking: [CCK] Swing Current Index: %d, Swing Base Index: %d\n", pDM_Odm->RFCalibrateInfo.CCK_index, pRFCalibrateInfo->BbSwingIdxCckBase));
-
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("TxPowerTracking: [OFDM] Swing Current Index: %d, Swing Base Index: %d\n", pDM_Odm->RFCalibrateInfo.OFDM_index[RF_PATH_A], pRFCalibrateInfo->BbSwingIdxOfdmBase));
-
- if (pDM_Odm->RFCalibrateInfo.PowerIndexOffset != 0 && pDM_Odm->RFCalibrateInfo.TxPowerTrackControl)
- {
- //4 7.2 Configure the Swing Table to adjust Tx Power.
-
- pDM_Odm->RFCalibrateInfo.bTxPowerChanged = TRUE; // Always TRUE after Tx Power is adjusted by power tracking.
- //
- // 2012/04/23 MH According to Luke's suggestion, we can not write BB digital
- // to increase TX power. Otherwise, EVM will be bad.
- //
- // 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E.
- if (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue)
- {
- //ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- // ("Temperature Increasing: delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
- // pDM_Odm->RFCalibrateInfo.PowerIndexOffset, delta, ThermalValue, pHalData->EEPROMThermalMeter, pDM_Odm->RFCalibrateInfo.ThermalValue));
- }
- else if (ThermalValue < pDM_Odm->RFCalibrateInfo.ThermalValue)// Low temperature
- {
- //ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- // ("Temperature Decreasing: delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
- // pDM_Odm->RFCalibrateInfo.PowerIndexOffset, delta, ThermalValue, pHalData->EEPROMThermalMeter, pDM_Odm->RFCalibrateInfo.ThermalValue));
- }
-#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
- if (ThermalValue > pHalData->EEPROMThermalMeter)
-#else
- if (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther)
-#endif
- {
-// ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("Temperature(%d) hugher than PG value(%d), increases the power by TxAGC\n", ThermalValue, pHalData->EEPROMThermalMeter));
- (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, TXAGC, 0, 0);
- }
- else
- {
- // ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("Temperature(%d) lower than PG value(%d), increases the power by TxAGC\n", ThermalValue, pHalData->EEPROMThermalMeter));
- (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, RF_PATH_A, Indexforchannel);
- if(is2T)
- (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, RF_PATH_B, Indexforchannel);
- }
-
- pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->BbSwingIdxCck;
- pRFCalibrateInfo->BbSwingIdxOfdmBase = pRFCalibrateInfo->BbSwingIdxOfdm[RF_PATH_A];
- pDM_Odm->RFCalibrateInfo.ThermalValue = ThermalValue;
-
- }
-
-#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
- // if((delta_IQK > pHalData->Delta_IQK) && (pHalData->Delta_IQK != 0))
- if ((delta_IQK >= 8)) // Delta temperature is equal to or larger than 20 centigrade.
- (*c.DoIQK)(pDM_Odm, delta_IQK, ThermalValue, 8);
-#endif
-
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("<===dm_TXPowerTrackingCallback_ThermalMeter_8188E\n"));
-
- pDM_Odm->RFCalibrateInfo.TXPowercount = 0;
-}
-
-#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-
-
-VOID
-phy_PathAStandBy(
- IN PADAPTER pAdapter
- )
-{
- RTPRINT(FINIT, INIT_IQK, ("Path-A standby mode!\n"));
-
- PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0x0);
- PHY_SetBBReg(pAdapter, 0x840, bMaskDWord, 0x00010000);
- PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0x808000);
-}
-
-//1 7. IQK
-//#define MAX_TOLERANCE 5
-//#define IQK_DELAY_TIME 1 //ms
-
-u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
-phy_PathA_IQK_8192C(
- IN PADAPTER pAdapter,
- IN BOOLEAN configPathB
- )
-{
-
- u4Byte regEAC, regE94, regE9C, regEA4;
- u1Byte result = 0x00;
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
-
- RTPRINT(FINIT, INIT_IQK, ("Path A IQK!\n"));
-
- //path-A IQK setting
- RTPRINT(FINIT, INIT_IQK, ("Path-A IQK setting!\n"));
- if(pAdapter->interfaceIndex == 0)
- {
- PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1f);
- PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f);
- }
- else
- {
- PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x10008c22);
- PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x10008c22);
- }
-
- PHY_SetBBReg(pAdapter, rTx_IQK_PI_A, bMaskDWord, 0x82140102);
-
- PHY_SetBBReg(pAdapter, rRx_IQK_PI_A, bMaskDWord, configPathB ? 0x28160202 :
- IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202:0x28160502);
-
- //path-B IQK setting
- if(configPathB)
- {
- PHY_SetBBReg(pAdapter, rTx_IQK_Tone_B, bMaskDWord, 0x10008c22);
- PHY_SetBBReg(pAdapter, rRx_IQK_Tone_B, bMaskDWord, 0x10008c22);
- PHY_SetBBReg(pAdapter, rTx_IQK_PI_B, bMaskDWord, 0x82140102);
- PHY_SetBBReg(pAdapter, rRx_IQK_PI_B, bMaskDWord, 0x28160202);
- }
-
- //LO calibration setting
- RTPRINT(FINIT, INIT_IQK, ("LO calibration setting!\n"));
- PHY_SetBBReg(pAdapter, rIQK_AGC_Rsp, bMaskDWord, 0x001028d1);
-
- //One shot, path A LOK & IQK
- RTPRINT(FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n"));
- PHY_SetBBReg(pAdapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
- PHY_SetBBReg(pAdapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
-
- // delay x ms
- RTPRINT(FINIT, INIT_IQK, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME));
- PlatformStallExecution(IQK_DELAY_TIME*1000);
-
- // Check failed
- regEAC = PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_A_2, bMaskDWord);
- RTPRINT(FINIT, INIT_IQK, ("0xeac = 0x%x\n", regEAC));
- regE94 = PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_A, bMaskDWord);
- RTPRINT(FINIT, INIT_IQK, ("0xe94 = 0x%x\n", regE94));
- regE9C= PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_A, bMaskDWord);
- RTPRINT(FINIT, INIT_IQK, ("0xe9c = 0x%x\n", regE9C));
- regEA4= PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_A_2, bMaskDWord);
- RTPRINT(FINIT, INIT_IQK, ("0xea4 = 0x%x\n", regEA4));
-
- if(!(regEAC & BIT28) &&
- (((regE94 & 0x03FF0000)>>16) != 0x142) &&
- (((regE9C & 0x03FF0000)>>16) != 0x42) )
- result |= 0x01;
- else //if Tx not OK, ignore Rx
- return result;
-
- if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK
- (((regEA4 & 0x03FF0000)>>16) != 0x132) &&
- (((regEAC & 0x03FF0000)>>16) != 0x36))
- result |= 0x02;
- else
- RTPRINT(FINIT, INIT_IQK, ("Path A Rx IQK fail!!\n"));
-
- return result;
-
-
-}
-
-u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
-phy_PathB_IQK_8192C(
- IN PADAPTER pAdapter
- )
-{
- u4Byte regEAC, regEB4, regEBC, regEC4, regECC;
- u1Byte result = 0x00;
- RTPRINT(FINIT, INIT_IQK, ("Path B IQK!\n"));
-
- //One shot, path B LOK & IQK
- RTPRINT(FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n"));
- PHY_SetBBReg(pAdapter, rIQK_AGC_Cont, bMaskDWord, 0x00000002);
- PHY_SetBBReg(pAdapter, rIQK_AGC_Cont, bMaskDWord, 0x00000000);
-
- // delay x ms
- RTPRINT(FINIT, INIT_IQK, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME));
- PlatformStallExecution(IQK_DELAY_TIME*1000);
-
- // Check failed
- regEAC = PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_A_2, bMaskDWord);
- RTPRINT(FINIT, INIT_IQK, ("0xeac = 0x%x\n", regEAC));
- regEB4 = PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_B, bMaskDWord);
- RTPRINT(FINIT, INIT_IQK, ("0xeb4 = 0x%x\n", regEB4));
- regEBC= PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_B, bMaskDWord);
- RTPRINT(FINIT, INIT_IQK, ("0xebc = 0x%x\n", regEBC));
- regEC4= PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_B_2, bMaskDWord);
- RTPRINT(FINIT, INIT_IQK, ("0xec4 = 0x%x\n", regEC4));
- regECC= PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_B_2, bMaskDWord);
- RTPRINT(FINIT, INIT_IQK, ("0xecc = 0x%x\n", regECC));
-
- if(!(regEAC & BIT31) &&
- (((regEB4 & 0x03FF0000)>>16) != 0x142) &&
- (((regEBC & 0x03FF0000)>>16) != 0x42))
- result |= 0x01;
- else
- return result;
-
- if(!(regEAC & BIT30) &&
- (((regEC4 & 0x03FF0000)>>16) != 0x132) &&
- (((regECC & 0x03FF0000)>>16) != 0x36))
- result |= 0x02;
- else
- RTPRINT(FINIT, INIT_IQK, ("Path B Rx IQK fail!!\n"));
-
-
- return result;
-
-}
-
-VOID
-phy_PathAFillIQKMatrix(
- IN PADAPTER pAdapter,
- IN BOOLEAN bIQKOK,
- IN s4Byte result[][8],
- IN u1Byte final_candidate,
- IN BOOLEAN bTxOnly
- )
-{
- u4Byte Oldval_0, X, TX0_A, reg;
- s4Byte Y, TX0_C;
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
-
- RTPRINT(FINIT, INIT_IQK, ("Path A IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed"));
-
- if(final_candidate == 0xFF)
- return;
-
- else if(bIQKOK)
- {
- Oldval_0 = (PHY_QueryBBReg(pAdapter, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF;
-
- X = result[final_candidate][0];
- if ((X & 0x00000200) != 0)
- X = X | 0xFFFFFC00;
- TX0_A = (X * Oldval_0) >> 8;
- RTPRINT(FINIT, INIT_IQK, ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0));
- PHY_SetBBReg(pAdapter, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A);
- PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(31), ((X * Oldval_0>>7) & 0x1));
-
- Y = result[final_candidate][1];
- if ((Y & 0x00000200) != 0)
- Y = Y | 0xFFFFFC00;
-
- //path B IQK result + 3
- if(pAdapter->interfaceIndex == 1 && pHalData->CurrentBandType == BAND_ON_5G)
- Y += 3;
-
- TX0_C = (Y * Oldval_0) >> 8;
- RTPRINT(FINIT, INIT_IQK, ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C));
- PHY_SetBBReg(pAdapter, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6));
- PHY_SetBBReg(pAdapter, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F));
- PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(29), ((Y * Oldval_0>>7) & 0x1));
-
- if(bTxOnly)
- {
- RTPRINT(FINIT, INIT_IQK, ("phy_PathAFillIQKMatrix only Tx OK\n"));
- return;
- }
-
- reg = result[final_candidate][2];
- PHY_SetBBReg(pAdapter, rOFDM0_XARxIQImbalance, 0x3FF, reg);
-
- reg = result[final_candidate][3] & 0x3F;
- PHY_SetBBReg(pAdapter, rOFDM0_XARxIQImbalance, 0xFC00, reg);
-
- reg = (result[final_candidate][3] >> 6) & 0xF;
- PHY_SetBBReg(pAdapter, rOFDM0_RxIQExtAnta, 0xF0000000, reg);
- }
-}
-
-VOID
-phy_PathBFillIQKMatrix(
- IN PADAPTER pAdapter,
- IN BOOLEAN bIQKOK,
- IN s4Byte result[][8],
- IN u1Byte final_candidate,
- IN BOOLEAN bTxOnly //do Tx only
- )
-{
- u4Byte Oldval_1, X, TX1_A, reg;
- s4Byte Y, TX1_C;
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
-
- RTPRINT(FINIT, INIT_IQK, ("Path B IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed"));
-
- if(final_candidate == 0xFF)
- return;
-
- else if(bIQKOK)
- {
- Oldval_1 = (PHY_QueryBBReg(pAdapter, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF;
-
- X = result[final_candidate][4];
- if ((X & 0x00000200) != 0)
- X = X | 0xFFFFFC00;
- TX1_A = (X * Oldval_1) >> 8;
- RTPRINT(FINIT, INIT_IQK, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A));
- PHY_SetBBReg(pAdapter, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A);
- PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(27), ((X * Oldval_1>>7) & 0x1));
-
- Y = result[final_candidate][5];
- if ((Y & 0x00000200) != 0)
- Y = Y | 0xFFFFFC00;
- if(pHalData->CurrentBandType == BAND_ON_5G)
- Y += 3; //temp modify for preformance
- TX1_C = (Y * Oldval_1) >> 8;
- RTPRINT(FINIT, INIT_IQK, ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C));
- PHY_SetBBReg(pAdapter, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6));
- PHY_SetBBReg(pAdapter, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F));
- PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(25), ((Y * Oldval_1>>7) & 0x1));
-
- if(bTxOnly)
- return;
-
- reg = result[final_candidate][6];
- PHY_SetBBReg(pAdapter, rOFDM0_XBRxIQImbalance, 0x3FF, reg);
-
- reg = result[final_candidate][7] & 0x3F;
- PHY_SetBBReg(pAdapter, rOFDM0_XBRxIQImbalance, 0xFC00, reg);
-
- reg = (result[final_candidate][7] >> 6) & 0xF;
- PHY_SetBBReg(pAdapter, rOFDM0_AGCRSSITable, 0x0000F000, reg);
- }
-}
-
-
-BOOLEAN
-phy_SimularityCompare_92C(
- IN PADAPTER pAdapter,
- IN s4Byte result[][8],
- IN u1Byte c1,
- IN u1Byte c2
- )
-{
- u4Byte i, j, diff, SimularityBitMap, bound = 0;
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
- u1Byte final_candidate[2] = {0xFF, 0xFF}; //for path A and path B
- BOOLEAN bResult = TRUE, is2T = IS_92C_SERIAL( pHalData->VersionID);
-
- if(is2T)
- bound = 8;
- else
- bound = 4;
-
- SimularityBitMap = 0;
-
- for( i = 0; i < bound; i++ )
- {
- diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] - result[c2][i]) : (result[c2][i] - result[c1][i]);
- if (diff > MAX_TOLERANCE)
- {
- if((i == 2 || i == 6) && !SimularityBitMap)
- {
- if(result[c1][i]+result[c1][i+1] == 0)
- final_candidate[(i/4)] = c2;
- else if (result[c2][i]+result[c2][i+1] == 0)
- final_candidate[(i/4)] = c1;
- else
- SimularityBitMap = SimularityBitMap|(1< do IQK again
-*/
-BOOLEAN
-phy_SimularityCompare(
- IN PADAPTER pAdapter,
- IN s4Byte result[][8],
- IN u1Byte c1,
- IN u1Byte c2
- )
-{
- return phy_SimularityCompare_92C(pAdapter, result, c1, c2);
-
-}
-
-VOID
-phy_IQCalibrate_8192C(
- IN PADAPTER pAdapter,
- IN s4Byte result[][8],
- IN u1Byte t,
- IN BOOLEAN is2T
- )
-{
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
- u4Byte i;
- u1Byte PathAOK, PathBOK;
- u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = {
- rFPGA0_XCD_SwitchControl, rBlue_Tooth,
- rRx_Wait_CCA, rTx_CCK_RFON,
- rTx_CCK_BBON, rTx_OFDM_RFON,
- rTx_OFDM_BBON, rTx_To_Rx,
- rTx_To_Tx, rRx_CCK,
- rRx_OFDM, rRx_Wait_RIFS,
- rRx_TO_Rx, rStandby,
- rSleep, rPMPD_ANAEN };
- u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = {
- REG_TXPAUSE, REG_BCN_CTRL,
- REG_BCN_CTRL_1, REG_GPIO_MUXCFG};
-
- //since 92C & 92D have the different define in IQK_BB_REG
- u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
- rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar,
- rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB,
- rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE,
- rFPGA0_XB_RFInterfaceOE, /*rFPGA0_RFMOD*/ rCCK0_AFESetting
- };
-
- u4Byte IQK_BB_REG_92D[IQK_BB_REG_NUM_92D] = { //for normal
- rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE,
- rFPGA0_XB_RFInterfaceOE, rOFDM0_TRMuxPar,
- rFPGA0_XCD_RFInterfaceSW, rOFDM0_TRxPathEnable,
- /*rFPGA0_RFMOD*/ rCCK0_AFESetting, rFPGA0_AnalogParameter4,
- rOFDM0_XAAGCCore1, rOFDM0_XBAGCCore1
- };
-#if MP_DRIVER
- const u4Byte retryCount = 9;
-#else
- const u4Byte retryCount = 2;
-#endif
- //Neil Chen--2011--05--19--
- //3 Path Div
- u1Byte rfPathSwitch=0x0;
-
- // Note: IQ calibration must be performed after loading
- // PHY_REG.txt , and radio_a, radio_b.txt
-
- u4Byte bbvalue;
-
- if(t==0)
- {
- //bbvalue = PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bMaskDWord);
- // RTPRINT(FINIT, INIT_IQK, ("phy_IQCalibrate_8192C()==>0x%08x\n",bbvalue));
-
- RTPRINT(FINIT, INIT_IQK, ("IQ Calibration for %s\n", (is2T ? "2T2R" : "1T1R")));
-
- // Save ADDA parameters, turn Path A ADDA on
- phy_SaveADDARegisters(pAdapter, ADDA_REG, pHalData->ADDA_backup, IQK_ADDA_REG_NUM);
- phy_SaveMACRegisters(pAdapter, IQK_MAC_REG, pHalData->IQK_MAC_backup);
- phy_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pHalData->IQK_BB_backup, IQK_BB_REG_NUM);
- }
-
- phy_PathADDAOn(pAdapter, ADDA_REG, TRUE, is2T);
-
- if(t==0)
- {
- pHalData->bRfPiEnable = (u1Byte)PHY_QueryBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, BIT(8));
- }
-
- if(!pHalData->bRfPiEnable){
- // Switch BB to PI mode to do IQ Calibration.
- phy_PIModeSwitch(pAdapter, TRUE);
- }
-
- //MAC settings
- phy_MACSettingCalibration(pAdapter, IQK_MAC_REG, pHalData->IQK_MAC_backup);
-
- //PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, BIT24, 0x00);
- PHY_SetBBReg(pAdapter, rCCK0_AFESetting, bMaskDWord, (0x0f000000 | (PHY_QueryBBReg(pAdapter, rCCK0_AFESetting, bMaskDWord))) );
- PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600);
- PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4);
- PHY_SetBBReg(pAdapter, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000);
- {
- PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01);
- PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01);
- PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00);
- PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00);
- }
-
- if(is2T)
- {
- PHY_SetBBReg(pAdapter, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00010000);
- PHY_SetBBReg(pAdapter, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00010000);
- }
-
- {
- //Page B init
- PHY_SetBBReg(pAdapter, rConfig_AntA, bMaskDWord, 0x00080000);
-
- if(is2T)
- {
- PHY_SetBBReg(pAdapter, rConfig_AntB, bMaskDWord, 0x00080000);
- }
- }
- // IQ calibration setting
- RTPRINT(FINIT, INIT_IQK, ("IQK setting!\n"));
- PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0x808000);
- PHY_SetBBReg(pAdapter, rTx_IQK, bMaskDWord, 0x01007c00);
- PHY_SetBBReg(pAdapter, rRx_IQK, bMaskDWord, 0x01004800);
-
- for(i = 0 ; i < retryCount ; i++){
- PathAOK = phy_PathA_IQK_8192C(pAdapter, is2T);
- if(PathAOK == 0x03){
- RTPRINT(FINIT, INIT_IQK, ("Path A IQK Success!!\n"));
- result[t][0] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;
- result[t][1] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
- result[t][2] = (PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
- result[t][3] = (PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
- break;
- }
- else if (i == (retryCount-1) && PathAOK == 0x01) //Tx IQK OK
- {
- RTPRINT(FINIT, INIT_IQK, ("Path A IQK Only Tx Success!!\n"));
-
- result[t][0] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;
- result[t][1] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
- }
- }
-
- if(0x00 == PathAOK){
- RTPRINT(FINIT, INIT_IQK, ("Path A IQK failed!!\n"));
- }
-
- if(is2T){
- phy_PathAStandBy(pAdapter);
-
- // Turn Path B ADDA on
- phy_PathADDAOn(pAdapter, ADDA_REG, FALSE, is2T);
-
- for(i = 0 ; i < retryCount ; i++){
- PathBOK = phy_PathB_IQK_8192C(pAdapter);
- if(PathBOK == 0x03){
- RTPRINT(FINIT, INIT_IQK, ("Path B IQK Success!!\n"));
- result[t][4] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16;
- result[t][5] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16;
- result[t][6] = (PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_B_2, bMaskDWord)&0x3FF0000)>>16;
- result[t][7] = (PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_B_2, bMaskDWord)&0x3FF0000)>>16;
- break;
- }
- else if (i == (retryCount - 1) && PathBOK == 0x01) //Tx IQK OK
- {
- RTPRINT(FINIT, INIT_IQK, ("Path B Only Tx IQK Success!!\n"));
- result[t][4] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16;
- result[t][5] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16;
- }
- }
-
- if(0x00 == PathBOK){
- RTPRINT(FINIT, INIT_IQK, ("Path B IQK failed!!\n"));
- }
- }
-
- //Back to BB mode, load original value
- RTPRINT(FINIT, INIT_IQK, ("IQK:Back to BB mode, load original value!\n"));
- PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0);
-
- if(t!=0)
- {
- if(!pHalData->bRfPiEnable){
- // Switch back BB to SI mode after finish IQ Calibration.
- phy_PIModeSwitch(pAdapter, FALSE);
- }
-
- // Reload ADDA power saving parameters
- phy_ReloadADDARegisters(pAdapter, ADDA_REG, pHalData->ADDA_backup, IQK_ADDA_REG_NUM);
-
- // Reload MAC parameters
- phy_ReloadMACRegisters(pAdapter, IQK_MAC_REG, pHalData->IQK_MAC_backup);
-
- // Reload BB parameters
- phy_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pHalData->IQK_BB_backup, IQK_BB_REG_NUM);
-
- /*Restore RX initial gain*/
- PHY_SetBBReg(pAdapter, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00032ed3);
- if (is2T)
- PHY_SetBBReg(pAdapter, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00032ed3);
- //load 0xe30 IQC default value
- PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);
- PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);
-
- }
- RTPRINT(FINIT, INIT_IQK, ("phy_IQCalibrate_8192C() <==\n"));
-
-}
-
-
-VOID
-phy_LCCalibrate92C(
- IN PADAPTER pAdapter,
- IN BOOLEAN is2T
- )
-{
- u1Byte tmpReg;
- u4Byte RF_Amode=0, RF_Bmode=0, LC_Cal;
-// HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
-
- //Check continuous TX and Packet TX
- tmpReg = PlatformEFIORead1Byte(pAdapter, 0xd03);
-
- if((tmpReg&0x70) != 0) //Deal with contisuous TX case
- PlatformEFIOWrite1Byte(pAdapter, 0xd03, tmpReg&0x8F); //disable all continuous TX
- else // Deal with Packet TX case
- PlatformEFIOWrite1Byte(pAdapter, REG_TXPAUSE, 0xFF); // block all queues
-
- if((tmpReg&0x70) != 0)
- {
- //1. Read original RF mode
- //Path-A
- RF_Amode = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits);
-
- //Path-B
- if(is2T)
- RF_Bmode = PHY_QueryRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits);
-
- //2. Set RF mode = standby mode
- //Path-A
- PHY_SetRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000);
-
- //Path-B
- if(is2T)
- PHY_SetRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000);
- }
-
- //3. Read RF reg18
- LC_Cal = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_CHNLBW, bMask12Bits);
-
- //4. Set LC calibration begin bit15
- PHY_SetRFReg(pAdapter, RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000);
-
- delay_ms(100);
-
-
- //Restore original situation
- if((tmpReg&0x70) != 0) //Deal with contisuous TX case
- {
- //Path-A
- PlatformEFIOWrite1Byte(pAdapter, 0xd03, tmpReg);
- PHY_SetRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits, RF_Amode);
-
- //Path-B
- if(is2T)
- PHY_SetRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode);
- }
- else // Deal with Packet TX case
- {
- PlatformEFIOWrite1Byte(pAdapter, REG_TXPAUSE, 0x00);
- }
-}
-
-
-VOID
-phy_LCCalibrate(
- IN PADAPTER pAdapter,
- IN BOOLEAN is2T
- )
-{
- phy_LCCalibrate92C(pAdapter, is2T);
-}
-
-
-
-//Analog Pre-distortion calibration
-#define APK_BB_REG_NUM 8
-#define APK_CURVE_REG_NUM 4
-#define PATH_NUM 2
-
-VOID
-phy_APCalibrate_8192C(
- IN PADAPTER pAdapter,
- IN s1Byte delta,
- IN BOOLEAN is2T
- )
-{
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
-
- u4Byte regD[PATH_NUM];
- u4Byte tmpReg, index, offset, i, apkbound;
- u1Byte path, pathbound = PATH_NUM;
- u4Byte BB_backup[APK_BB_REG_NUM];
- u4Byte BB_REG[APK_BB_REG_NUM] = {
- rFPGA1_TxBlock, rOFDM0_TRxPathEnable,
- rFPGA0_RFMOD, rOFDM0_TRMuxPar,
- rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW,
- rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE };
- u4Byte BB_AP_MODE[APK_BB_REG_NUM] = {
- 0x00000020, 0x00a05430, 0x02040000,
- 0x000800e4, 0x00204000 };
- u4Byte BB_normal_AP_MODE[APK_BB_REG_NUM] = {
- 0x00000020, 0x00a05430, 0x02040000,
- 0x000800e4, 0x22204000 };
-
- u4Byte AFE_backup[IQK_ADDA_REG_NUM];
- u4Byte AFE_REG[IQK_ADDA_REG_NUM] = {
- rFPGA0_XCD_SwitchControl, rBlue_Tooth,
- rRx_Wait_CCA, rTx_CCK_RFON,
- rTx_CCK_BBON, rTx_OFDM_RFON,
- rTx_OFDM_BBON, rTx_To_Rx,
- rTx_To_Tx, rRx_CCK,
- rRx_OFDM, rRx_Wait_RIFS,
- rRx_TO_Rx, rStandby,
- rSleep, rPMPD_ANAEN };
-
- u4Byte MAC_backup[IQK_MAC_REG_NUM];
- u4Byte MAC_REG[IQK_MAC_REG_NUM] = {
- REG_TXPAUSE, REG_BCN_CTRL,
- REG_BCN_CTRL_1, REG_GPIO_MUXCFG};
-
- u4Byte APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = {
- {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c},
- {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e}
- };
-
- u4Byte APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = {
- {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, //path settings equal to path b settings
- {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c}
- };
-
- u4Byte APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = {
- {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d},
- {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050}
- };
-
- u4Byte APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = {
- {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, //path settings equal to path b settings
- {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}
- };
-#if 0
- u4Byte APK_RF_value_A[PATH_NUM][APK_BB_REG_NUM] = {
- {0x1adb0, 0x1adb0, 0x1ada0, 0x1ad90, 0x1ad80},
- {0x00fb0, 0x00fb0, 0x00fa0, 0x00f90, 0x00f80}
- };
-#endif
- u4Byte AFE_on_off[PATH_NUM] = {
- 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on
-
- u4Byte APK_offset[PATH_NUM] = {
- rConfig_AntA, rConfig_AntB};
-
- u4Byte APK_normal_offset[PATH_NUM] = {
- rConfig_Pmpd_AntA, rConfig_Pmpd_AntB};
-
- u4Byte APK_value[PATH_NUM] = {
- 0x92fc0000, 0x12fc0000};
-
- u4Byte APK_normal_value[PATH_NUM] = {
- 0x92680000, 0x12680000};
-
- s1Byte APK_delta_mapping[APK_BB_REG_NUM][13] = {
- {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
- {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
- {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
- {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6},
- {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0}
- };
-
- u4Byte APK_normal_setting_value_1[13] = {
- 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28,
- 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3,
- 0x12680000, 0x00880000, 0x00880000
- };
-
- u4Byte APK_normal_setting_value_2[16] = {
- 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3,
- 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025,
- 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008,
- 0x00050006
- };
-
- u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a
-// u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM];
-
- s4Byte BB_offset, delta_V, delta_offset;
-
-#if MP_DRIVER == 1
- PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx);
-
- pMptCtx->APK_bound[0] = 45;
- pMptCtx->APK_bound[1] = 52;
-#endif
-
- RTPRINT(FINIT, INIT_IQK, ("==>phy_APCalibrate_8192C() delta %d\n", delta));
- RTPRINT(FINIT, INIT_IQK, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R")));
- if(!is2T)
- pathbound = 1;
-
- //2 FOR NORMAL CHIP SETTINGS
-
-// Temporarily do not allow normal driver to do the following settings because these offset
-// and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal
-// will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the
-// root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31.
-#if MP_DRIVER != 1
- return;
-#endif
- //settings adjust for normal chip
- for(index = 0; index < PATH_NUM; index ++)
- {
- APK_offset[index] = APK_normal_offset[index];
- APK_value[index] = APK_normal_value[index];
- AFE_on_off[index] = 0x6fdb25a4;
- }
-
- for(index = 0; index < APK_BB_REG_NUM; index ++)
- {
- for(path = 0; path < pathbound; path++)
- {
- APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index];
- APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index];
- }
- BB_AP_MODE[index] = BB_normal_AP_MODE[index];
- }
-
- apkbound = 6;
-
- //save BB default value
- for(index = 0; index < APK_BB_REG_NUM ; index++)
- {
- if(index == 0) //skip
- continue;
- BB_backup[index] = PHY_QueryBBReg(pAdapter, BB_REG[index], bMaskDWord);
- }
-
- //save MAC default value
- phy_SaveMACRegisters(pAdapter, MAC_REG, MAC_backup);
-
- //save AFE default value
- phy_SaveADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
-
- for(path = 0; path < pathbound; path++)
- {
-
-
- if(path == RF_PATH_A)
- {
- //path A APK
- //load APK setting
- //path-A
- offset = rPdp_AntA;
- for(index = 0; index < 11; index ++)
- {
- PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]);
- RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord)));
-
- offset += 0x04;
- }
-
- PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000);
-
- offset = rConfig_AntA;
- for(; index < 13; index ++)
- {
- PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]);
- RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord)));
-
- offset += 0x04;
- }
-
- //page-B1
- PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0x400000);
-
- //path A
- offset = rPdp_AntA;
- for(index = 0; index < 16; index++)
- {
- PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_2[index]);
- RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord)));
-
- offset += 0x04;
- }
- PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0);
- }
- else if(path == RF_PATH_B)
- {
- //path B APK
- //load APK setting
- //path-B
- offset = rPdp_AntB;
- for(index = 0; index < 10; index ++)
- {
- PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]);
- RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord)));
-
- offset += 0x04;
- }
- PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000);
-
- PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000);
-
- offset = rConfig_AntA;
- index = 11;
- for(; index < 13; index ++) //offset 0xb68, 0xb6c
- {
- PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]);
- RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord)));
-
- offset += 0x04;
- }
-
- //page-B1
- PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0x400000);
-
- //path B
- offset = 0xb60;
- for(index = 0; index < 16; index++)
- {
- PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_2[index]);
- RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord)));
-
- offset += 0x04;
- }
- PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0);
- }
-
- //save RF default value
- regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bRFRegOffsetMask);
-
- //Path A AFE all on, path B AFE All off or vise versa
- for(index = 0; index < IQK_ADDA_REG_NUM ; index++)
- PHY_SetBBReg(pAdapter, AFE_REG[index], bMaskDWord, AFE_on_off[path]);
- RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0xe70 %x\n", PHY_QueryBBReg(pAdapter, rRx_Wait_CCA, bMaskDWord)));
-
- //BB to AP mode
- if(path == 0)
- {
- for(index = 0; index < APK_BB_REG_NUM ; index++)
- {
-
- if(index == 0) //skip
- continue;
- else if (index < 5)
- PHY_SetBBReg(pAdapter, BB_REG[index], bMaskDWord, BB_AP_MODE[index]);
- else if (BB_REG[index] == 0x870)
- PHY_SetBBReg(pAdapter, BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26);
- else
- PHY_SetBBReg(pAdapter, BB_REG[index], BIT10, 0x0);
- }
-
- PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);
- PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);
- }
- else //path B
- {
- PHY_SetBBReg(pAdapter, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00);
- PHY_SetBBReg(pAdapter, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00);
-
- }
-
- RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x800 %x\n", PHY_QueryBBReg(pAdapter, 0x800, bMaskDWord)));
-
- //MAC settings
- phy_MACSettingCalibration(pAdapter, MAC_REG, MAC_backup);
-
- if(path == RF_PATH_A) //Path B to standby mode
- {
- PHY_SetRFReg(pAdapter, RF_PATH_B, RF_AC, bRFRegOffsetMask, 0x10000);
- }
- else //Path A to standby mode
- {
- PHY_SetRFReg(pAdapter, RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x10000);
- PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE1, bRFRegOffsetMask, 0x1000f);
- PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE2, bRFRegOffsetMask, 0x20103);
- }
-
- delta_offset = ((delta+14)/2);
- if(delta_offset < 0)
- delta_offset = 0;
- else if (delta_offset > 12)
- delta_offset = 12;
-
- //AP calibration
- for(index = 0; index < APK_BB_REG_NUM; index++)
- {
- if(index != 1) //only DO PA11+PAD01001, AP RF setting
- continue;
-
- tmpReg = APK_RF_init_value[path][index];
-#if 1
- if(!pHalData->bAPKThermalMeterIgnore)
- {
- BB_offset = (tmpReg & 0xF0000) >> 16;
-
- if(!(tmpReg & BIT15)) //sign bit 0
- {
- BB_offset = -BB_offset;
- }
-
- delta_V = APK_delta_mapping[index][delta_offset];
-
- BB_offset += delta_V;
-
- RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, delta_V, delta_offset));
-
- if(BB_offset < 0)
- {
- tmpReg = tmpReg & (~BIT15);
- BB_offset = -BB_offset;
- }
- else
- {
- tmpReg = tmpReg | BIT15;
- }
- tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16);
- }
-#endif
-
-#if DEV_BUS_TYPE==RT_PCI_INTERFACE
- if(IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID))
- PHY_SetRFReg(pAdapter, path, RF_IPA_A, bRFRegOffsetMask, 0x894ae);
- else
-#endif
- PHY_SetRFReg(pAdapter, path, RF_IPA_A, bRFRegOffsetMask, 0x8992e);
- RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, path, RF_IPA_A, bRFRegOffsetMask)));
- PHY_SetRFReg(pAdapter, path, RF_AC, bRFRegOffsetMask, APK_RF_value_0[path][index]);
- RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, path, RF_AC, bRFRegOffsetMask)));
- PHY_SetRFReg(pAdapter, path, RF_TXBIAS_A, bRFRegOffsetMask, tmpReg);
- RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bRFRegOffsetMask)));
-
- // PA11+PAD01111, one shot
- i = 0;
- do
- {
- PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0x800000);
- {
- PHY_SetBBReg(pAdapter, APK_offset[path], bMaskDWord, APK_value[0]);
- RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", APK_offset[path], PHY_QueryBBReg(pAdapter, APK_offset[path], bMaskDWord)));
- delay_ms(3);
- PHY_SetBBReg(pAdapter, APK_offset[path], bMaskDWord, APK_value[1]);
- RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", APK_offset[path], PHY_QueryBBReg(pAdapter, APK_offset[path], bMaskDWord)));
-
- delay_ms(20);
- }
- PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0);
-
- if(path == RF_PATH_A)
- tmpReg = PHY_QueryBBReg(pAdapter, rAPK, 0x03E00000);
- else
- tmpReg = PHY_QueryBBReg(pAdapter, rAPK, 0xF8000000);
- RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0xbd8[25:21] %x\n", tmpReg));
-
-
- i++;
- }
- while(tmpReg > apkbound && i < 4);
-
- APK_result[path][index] = tmpReg;
- }
- }
-
- //reload MAC default value
- phy_ReloadMACRegisters(pAdapter, MAC_REG, MAC_backup);
-
- //reload BB default value
- for(index = 0; index < APK_BB_REG_NUM ; index++)
- {
-
- if(index == 0) //skip
- continue;
- PHY_SetBBReg(pAdapter, BB_REG[index], bMaskDWord, BB_backup[index]);
- }
-
- //reload AFE default value
- phy_ReloadADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
-
- //reload RF path default value
- for(path = 0; path < pathbound; path++)
- {
- PHY_SetRFReg(pAdapter, path, RF_TXBIAS_A, bRFRegOffsetMask, regD[path]);
- if(path == RF_PATH_B)
- {
- PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE1, bRFRegOffsetMask, 0x1000f);
- PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE2, bRFRegOffsetMask, 0x20101);
- }
-
- //note no index == 0
- if (APK_result[path][1] > 6)
- APK_result[path][1] = 6;
- RTPRINT(FINIT, INIT_IQK, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1]));
- }
-
- RTPRINT(FINIT, INIT_IQK, ("\n"));
-
-
- for(path = 0; path < pathbound; path++)
- {
- PHY_SetRFReg(pAdapter, path, RF_BS_PA_APSET_G1_G4, bRFRegOffsetMask,
- ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1]));
- if(path == RF_PATH_A)
- PHY_SetRFReg(pAdapter, path, RF_BS_PA_APSET_G5_G8, bRFRegOffsetMask,
- ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05));
- else
- PHY_SetRFReg(pAdapter, path, RF_BS_PA_APSET_G5_G8, bRFRegOffsetMask,
- ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05));
-
- PHY_SetRFReg(pAdapter, path, RF_BS_PA_APSET_G9_G11, bRFRegOffsetMask, ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08));
- }
-
- pHalData->bAPKdone = TRUE;
-
- RTPRINT(FINIT, INIT_IQK, ("<==phy_APCalibrate_8192C()\n"));
-}
-
-
-VOID
-PHY_IQCalibrate_8192C(
- IN PADAPTER pAdapter,
- IN BOOLEAN bReCovery
- )
-{
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
- s4Byte result[4][8]; //last is final result
- u1Byte i, final_candidate, Indexforchannel;
- BOOLEAN bPathAOK, bPathBOK;
- s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0;
- BOOLEAN is12simular, is13simular, is23simular;
- BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE;
- u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
- rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance,
- rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable,
- rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance,
- rOFDM0_XCTxAFE, rOFDM0_XDTxAFE,
- rOFDM0_RxIQExtAnta};
-
- if (ODM_CheckPowerStatus(pAdapter) == FALSE)
- return;
-
-#if MP_DRIVER == 1
- bStartContTx = pAdapter->MptCtx.bStartContTx;
- bSingleTone = pAdapter->MptCtx.bSingleTone;
- bCarrierSuppression = pAdapter->MptCtx.bCarrierSuppression;
-#endif
-
- //ignore IQK when continuous Tx
- if(bStartContTx || bSingleTone || bCarrierSuppression)
- return;
-
-#ifdef DISABLE_BB_RF
- return;
-#endif
- if(pAdapter->bSlaveOfDMSP)
- return;
-
- if (bReCovery)
- {
- phy_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pHalData->IQK_BB_backup_recover, 9);
- return;
-
- }
-
- RTPRINT(FINIT, INIT_IQK, ("IQK:Start!!!\n"));
-
- for(i = 0; i < 8; i++)
- {
- result[0][i] = 0;
- result[1][i] = 0;
- result[2][i] = 0;
- result[3][i] = 0;
- }
- final_candidate = 0xff;
- bPathAOK = FALSE;
- bPathBOK = FALSE;
- is12simular = FALSE;
- is23simular = FALSE;
- is13simular = FALSE;
-
- AcquireCCKAndRWPageAControl(pAdapter);
- /*RT_TRACE(COMP_INIT,DBG_LOUD,("Acquire Mutex in IQCalibrate\n"));*/
- for (i=0; i<3; i++)
- {
- /*For 88C 1T1R*/
- phy_IQCalibrate_8192C(pAdapter, result, i, FALSE);
-
- if(i == 1)
- {
- is12simular = phy_SimularityCompare(pAdapter, result, 0, 1);
- if(is12simular)
- {
- final_candidate = 0;
- break;
- }
- }
-
- if(i == 2)
- {
- is13simular = phy_SimularityCompare(pAdapter, result, 0, 2);
- if(is13simular)
- {
- final_candidate = 0;
- break;
- }
-
- is23simular = phy_SimularityCompare(pAdapter, result, 1, 2);
- if(is23simular)
- final_candidate = 1;
- else
- {
- for(i = 0; i < 8; i++)
- RegTmp += result[3][i];
-
- if(RegTmp != 0)
- final_candidate = 3;
- else
- final_candidate = 0xFF;
- }
- }
- }
-// RT_TRACE(COMP_INIT,DBG_LOUD,("Release Mutex in IQCalibrate \n"));
- ReleaseCCKAndRWPageAControl(pAdapter);
-
- for (i=0; i<4; i++)
- {
- RegE94 = result[i][0];
- RegE9C = result[i][1];
- RegEA4 = result[i][2];
- RegEAC = result[i][3];
- RegEB4 = result[i][4];
- RegEBC = result[i][5];
- RegEC4 = result[i][6];
- RegECC = result[i][7];
- RTPRINT(FINIT, INIT_IQK, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC));
- }
-
- if(final_candidate != 0xff)
- {
- pHalData->RegE94 = RegE94 = result[final_candidate][0];
- pHalData->RegE9C = RegE9C = result[final_candidate][1];
- RegEA4 = result[final_candidate][2];
- RegEAC = result[final_candidate][3];
- pHalData->RegEB4 = RegEB4 = result[final_candidate][4];
- pHalData->RegEBC = RegEBC = result[final_candidate][5];
- RegEC4 = result[final_candidate][6];
- RegECC = result[final_candidate][7];
- RTPRINT(FINIT, INIT_IQK, ("IQK: final_candidate is %x\n",final_candidate));
- RTPRINT(FINIT, INIT_IQK, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC));
- bPathAOK = bPathBOK = TRUE;
- }
- else
- {
- RegE94 = RegEB4 = pHalData->RegE94 = pHalData->RegEB4 = 0x100; //X default value
- RegE9C = RegEBC = pHalData->RegE9C = pHalData->RegEBC = 0x0; //Y default value
- }
-
- if((RegE94 != 0)/*&&(RegEA4 != 0)*/)
- {
- if(pHalData->CurrentBandType == BAND_ON_5G)
- phy_PathAFillIQKMatrix_5G_Normal(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0));
- else
- phy_PathAFillIQKMatrix(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0));
-
- }
-
- if (IS_92C_SERIAL(pHalData->VersionID) || IS_92D_SINGLEPHY(pHalData->VersionID))
- {
- if((RegEB4 != 0)/*&&(RegEC4 != 0)*/)
- {
- if(pHalData->CurrentBandType == BAND_ON_5G)
- phy_PathBFillIQKMatrix_5G_Normal(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0));
- else
- phy_PathBFillIQKMatrix(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0));
- }
- }
-
- phy_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pHalData->IQK_BB_backup_recover, 9);
-
-}
-
-
-VOID
-PHY_LCCalibrate_8192C(
- IN PADAPTER pAdapter
- )
-{
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
- BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE;
- PMGNT_INFO pMgntInfo=&pAdapter->MgntInfo;
- PMGNT_INFO pMgntInfoBuddyAdapter;
- u4Byte timeout = 2000, timecount = 0;
- PADAPTER BuddyAdapter = pAdapter->BuddyAdapter;
-
-#if MP_DRIVER == 1
- bStartContTx = pAdapter->MptCtx.bStartContTx;
- bSingleTone = pAdapter->MptCtx.bSingleTone;
- bCarrierSuppression = pAdapter->MptCtx.bCarrierSuppression;
-#endif
-
-#ifdef DISABLE_BB_RF
- return;
-#endif
-
- //ignore LCK when continuous Tx
- if(bStartContTx || bSingleTone || bCarrierSuppression)
- return;
-
- if(BuddyAdapter != NULL &&
- ((pAdapter->interfaceIndex == 0 && pHalData->CurrentBandType == BAND_ON_2_4G) ||
- (pAdapter->interfaceIndex == 1 && pHalData->CurrentBandType == BAND_ON_5G)))
- {
- pMgntInfoBuddyAdapter=&BuddyAdapter->MgntInfo;
- while(pMgntInfoBuddyAdapter->bScanInProgress && timecount < timeout)
- {
- delay_ms(50);
- timecount += 50;
- }
- }
-
- while(pMgntInfo->bScanInProgress && timecount < timeout)
- {
- delay_ms(50);
- timecount += 50;
- }
-
- pHalData->bLCKInProgress = TRUE;
-
- RTPRINT(FINIT, INIT_IQK, ("LCK:Start!!!interface %d currentband %x delay %d ms\n", pAdapter->interfaceIndex, pHalData->CurrentBandType, timecount));
-
- //if(IS_92C_SERIAL(pHalData->VersionID) || IS_92D_SINGLEPHY(pHalData->VersionID))
- if(IS_2T2R(pHalData->VersionID))
- {
- phy_LCCalibrate(pAdapter, TRUE);
- }
- else{
- // For 88C 1T1R
- phy_LCCalibrate(pAdapter, FALSE);
- }
-
- pHalData->bLCKInProgress = FALSE;
-
- RTPRINT(FINIT, INIT_IQK, ("LCK:Finish!!!interface %d\n", pAdapter->interfaceIndex));
-
-
-}
-
-VOID
-PHY_APCalibrate_8192C(
- IN PADAPTER pAdapter,
- IN s1Byte delta
- )
-{
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
-
- //default disable APK, because Tx NG issue, suggest by Jenyu, 2011.11.25
- return;
-
-#ifdef DISABLE_BB_RF
- return;
-#endif
-
-#if FOR_BRAZIL_PRETEST != 1
- if(pHalData->bAPKdone)
-#endif
- return;
-
- if(IS_92C_SERIAL( pHalData->VersionID)){
- phy_APCalibrate_8192C(pAdapter, delta, TRUE);
- }
- else{
- // For 88C 1T1R
- phy_APCalibrate_8192C(pAdapter, delta, FALSE);
- }
-}
-
-
-#endif
-
-
-//3============================================================
-//3 IQ Calibration
-//3============================================================
-
-VOID
-ODM_ResetIQKResult(
- IN PVOID pDM_VOID
-)
-{
- return;
-}
-#if 1//!(DM_ODM_SUPPORT_TYPE & ODM_AP)
-u1Byte ODM_GetRightChnlPlaceforIQK(u1Byte chnl)
-{
- u1Byte channel_all[ODM_TARGET_CHNL_NUM_2G_5G] =
- {1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,100,102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,132,134,136,138,140,149,151,153,155,157,159,161,163,165};
- u1Byte place = chnl;
-
-
- if(chnl > 14)
- {
- for(place = 14; placeAdapter;
-
-#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
- if (*pDM_Odm->pIsFcsModeEnable)
- return;
-#endif
-
-
-
- if (pDM_Odm->bLinked) {
- if ((*pDM_Odm->pChannel != pDM_Odm->preChannel) && (!*pDM_Odm->pbScanInProcess)) {
- pDM_Odm->preChannel = *pDM_Odm->pChannel;
- pDM_Odm->LinkedInterval = 0;
- }
-
- if (pDM_Odm->LinkedInterval < 3)
- pDM_Odm->LinkedInterval++;
-
- if (pDM_Odm->LinkedInterval == 2) {
-
- #if (RTL8814A_SUPPORT == 1)
- if (pDM_Odm->SupportICType == ODM_RTL8814A)
- PHY_IQCalibrate_8814A(pDM_Odm, FALSE);
- #endif
-
- #if (RTL8822B_SUPPORT == 1)
- if (pDM_Odm->SupportICType == ODM_RTL8822B)
- PHY_IQCalibrate_8822B(pDM_Odm, FALSE);
- #endif
-
- #if (RTL8821C_SUPPORT == 1)
- if (pDM_Odm->SupportICType == ODM_RTL8821C)
- PHY_IQCalibrate_8821C(pDM_Odm, FALSE);
- #endif
-
- #if (RTL8821A_SUPPORT == 1)
- if (pDM_Odm->SupportICType == ODM_RTL8821)
- PHY_IQCalibrate_8821A(pDM_Odm, FALSE);
- #endif
-
- #if (RTL8812A_SUPPORT == 1)
- if (pDM_Odm->SupportICType == ODM_RTL8812)
- phy_IQCalibrate_8812A(pDM_Odm, FALSE);
- #endif
- }
- } else
- pDM_Odm->LinkedInterval = 0;
-
-}
-
-void phydm_rf_init(IN PVOID pDM_VOID)
-{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- odm_TXPowerTrackingInit(pDM_Odm);
-
-#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
- ODM_ClearTxPowerTrackingState(pDM_Odm);
-#endif
-
-#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-#if (RTL8814A_SUPPORT == 1)
- if (pDM_Odm->SupportICType & ODM_RTL8814A)
- PHY_IQCalibrate_8814A_Init(pDM_Odm);
-#endif
-#endif
-
-}
-
-void phydm_rf_watchdog(IN PVOID pDM_VOID)
-{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
-#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
- ODM_TXPowerTrackingCheck(pDM_Odm);
- if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
- odm_IQCalibrate(pDM_Odm);
-#endif
-}
diff --git a/hal/phydm/halphyrf_ap.h b/hal/phydm/halphyrf_ap.h
deleted file mode 100644
index 8281e55..0000000
--- a/hal/phydm/halphyrf_ap.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of version 2 of the GNU General Public License as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
-
- #ifndef __HAL_PHY_RF_H__
- #define __HAL_PHY_RF_H__
-
-#include "phydm_powertracking_ap.h"
-#if (RTL8814A_SUPPORT == 1)
-#include "rtl8814a/phydm_iqk_8814a.h"
-#endif
-
-#if (RTL8822B_SUPPORT == 1)
-#include "rtl8822b/phydm_iqk_8822b.h"
-#endif
-
-#if (RTL8821C_SUPPORT == 1)
-#include "rtl8822b/phydm_iqk_8821c.h"
-#endif
-
-typedef enum _PWRTRACK_CONTROL_METHOD {
- BBSWING,
- TXAGC,
- MIX_MODE,
- TSSI_MODE
-} PWRTRACK_METHOD;
-
-typedef VOID (*FuncSetPwr)(PVOID, PWRTRACK_METHOD, u1Byte, u1Byte);
-typedef VOID(*FuncIQK)(PVOID, u1Byte, u1Byte, u1Byte);
-typedef VOID (*FuncLCK)(PVOID);
- //refine by YuChen for 8814A
-typedef VOID (*FuncSwing)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*);
-typedef VOID (*FuncSwing8814only)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*);
-typedef VOID (*FuncAllSwing)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*);
-
-
-typedef struct _TXPWRTRACK_CFG {
- u1Byte SwingTableSize_CCK;
- u1Byte SwingTableSize_OFDM;
- u1Byte Threshold_IQK;
- u1Byte Threshold_DPK;
- u1Byte AverageThermalNum;
- u1Byte RfPathCount;
- u4Byte ThermalRegAddr;
- FuncSetPwr ODM_TxPwrTrackSetPwr;
- FuncIQK DoIQK;
- FuncLCK PHY_LCCalibrate;
- FuncSwing GetDeltaSwingTable;
- FuncSwing8814only GetDeltaSwingTable8814only;
- FuncAllSwing GetDeltaAllSwingTable;
-} TXPWRTRACK_CFG, *PTXPWRTRACK_CFG;
-
-VOID
-ConfigureTxpowerTrack(
- IN PVOID pDM_VOID,
- OUT PTXPWRTRACK_CFG pConfig
- );
-
-
-VOID
-ODM_TXPowerTrackingCallback_ThermalMeter(
-#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
- IN PVOID pDM_VOID
-#else
- IN PADAPTER Adapter
-#endif
- );
-
-#if (RTL8192E_SUPPORT==1)
-VOID
-ODM_TXPowerTrackingCallback_ThermalMeter_92E(
-#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
- IN PVOID pDM_VOID
-#else
- IN PADAPTER Adapter
-#endif
- );
-#endif
-
-#if (RTL8814A_SUPPORT == 1)
-VOID
-ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries2(
-#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
- IN PVOID pDM_VOID
-#else
- IN PADAPTER Adapter
-#endif
- );
-
-#elif ODM_IC_11AC_SERIES_SUPPORT
-VOID
-ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries(
-#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
- IN PVOID pDM_VOID
-#else
- IN PADAPTER Adapter
-#endif
- );
-
-#elif (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1)
-VOID
-ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries3(
-#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
- IN PVOID pDM_VOID
-#else
- IN PADAPTER Adapter
-#endif
- );
-
-#endif
-
-#define IS_CCK_RATE(_rate) (ODM_MGN_1M == _rate || _rate == ODM_MGN_2M || _rate == ODM_MGN_5_5M || _rate == ODM_MGN_11M )
-
-
-#if(DM_ODM_SUPPORT_TYPE & ODM_WIN)
-#define MAX_TOLERANCE 5
-#define IQK_DELAY_TIME 1 //ms
-
- //
-// BB/MAC/RF other monitor API
-//
-
-void PHY_SetMonitorMode8192C(IN PADAPTER pAdapter,
- IN BOOLEAN bEnableMonitorMode );
-
-//
-// IQ calibrate
-//
-void
-PHY_IQCalibrate_8192C( IN PADAPTER pAdapter,
- IN BOOLEAN bReCovery);
-
-//
-// LC calibrate
-//
-void
-PHY_LCCalibrate_8192C( IN PADAPTER pAdapter);
-
-//
-// AP calibrate
-//
-void
-PHY_APCalibrate_8192C( IN PADAPTER pAdapter,
- IN s1Byte delta);
-#endif
-
-#define ODM_TARGET_CHNL_NUM_2G_5G 59
-
-
-VOID
-ODM_ResetIQKResult(
- IN PVOID pDM_VOID
-);
-u1Byte
-ODM_GetRightChnlPlaceforIQK(
- IN u1Byte chnl
-);
-
-void phydm_rf_init(IN PVOID pDM_VOID);
-void phydm_rf_watchdog(IN PVOID pDM_VOID);
-
-#endif // #ifndef __HAL_PHY_RF_H__
-
diff --git a/hal/phydm/halphyrf_ce.c b/hal/phydm/halphyrf_ce.c
deleted file mode 100644
index 8b7322e..0000000
--- a/hal/phydm/halphyrf_ce.c
+++ /dev/null
@@ -1,801 +0,0 @@
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of version 2 of the GNU General Public License as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
-
-#include "mp_precomp.h"
-#include "phydm_precomp.h"
-
-#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _deltaThermal) \
- do {\
- for(_offset = 0; _offset < _size; _offset++)\
- {\
- if(_deltaThermal < thermalThreshold[_direction][_offset])\
- {\
- if(_offset != 0)\
- _offset--;\
- break;\
- }\
- } \
- if(_offset >= _size)\
- _offset = _size-1;\
- } while(0)
-
-void ConfigureTxpowerTrack(
- IN PVOID pDM_VOID,
- OUT PTXPWRTRACK_CFG pConfig
- )
-{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
-
-#if RTL8192E_SUPPORT
- if (pDM_Odm->SupportICType == ODM_RTL8192E)
- ConfigureTxpowerTrack_8192E(pConfig);
-#endif
-#if RTL8821A_SUPPORT
- if (pDM_Odm->SupportICType == ODM_RTL8821)
- ConfigureTxpowerTrack_8821A(pConfig);
-#endif
-#if RTL8812A_SUPPORT
- if (pDM_Odm->SupportICType == ODM_RTL8812)
- ConfigureTxpowerTrack_8812A(pConfig);
-#endif
-#if RTL8188E_SUPPORT
- if (pDM_Odm->SupportICType == ODM_RTL8188E)
- ConfigureTxpowerTrack_8188E(pConfig);
-#endif
-
-#if RTL8723B_SUPPORT
- if (pDM_Odm->SupportICType == ODM_RTL8723B)
- ConfigureTxpowerTrack_8723B(pConfig);
-#endif
-
-#if RTL8814A_SUPPORT
- if (pDM_Odm->SupportICType == ODM_RTL8814A)
- ConfigureTxpowerTrack_8814A(pConfig);
-#endif
-
-#if RTL8703B_SUPPORT
- if (pDM_Odm->SupportICType == ODM_RTL8703B)
- ConfigureTxpowerTrack_8703B(pConfig);
-#endif
-
-#if RTL8188F_SUPPORT
- if (pDM_Odm->SupportICType == ODM_RTL8188F)
- ConfigureTxpowerTrack_8188F(pConfig);
-#endif
-#if RTL8723D_SUPPORT
- if (pDM_Odm->SupportICType == ODM_RTL8723D)
- ConfigureTxpowerTrack_8723D(pConfig);
-#endif
-#if RTL8822B_SUPPORT
- if (pDM_Odm->SupportICType == ODM_RTL8822B)
- ConfigureTxpowerTrack_8822B(pConfig);
-#endif
-
-}
-
-//======================================================================
-// <20121113, Kordan> This function should be called when TxAGC changed.
-// Otherwise the previous compensation is gone, because we record the
-// delta of temperature between two TxPowerTracking watch dogs.
-//
-// NOTE: If Tx BB swing or Tx scaling is varified during run-time, still
-// need to call this function.
-//======================================================================
-VOID
-ODM_ClearTxPowerTrackingState(
- IN PVOID pDM_VOID
- )
-{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pDM_Odm->Adapter);
- u1Byte p = 0;
- PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
-
- pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->DefaultCckIndex;
- pRFCalibrateInfo->BbSwingIdxCck = pRFCalibrateInfo->DefaultCckIndex;
- pDM_Odm->RFCalibrateInfo.CCK_index = 0;
-
- for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p)
- {
- pRFCalibrateInfo->BbSwingIdxOfdmBase[p] = pRFCalibrateInfo->DefaultOfdmIndex;
- pRFCalibrateInfo->BbSwingIdxOfdm[p] = pRFCalibrateInfo->DefaultOfdmIndex;
- pRFCalibrateInfo->OFDM_index[p] = pRFCalibrateInfo->DefaultOfdmIndex;
-
- pRFCalibrateInfo->PowerIndexOffset[p] = 0;
- pRFCalibrateInfo->DeltaPowerIndex[p] = 0;
- pRFCalibrateInfo->DeltaPowerIndexLast[p] = 0;
-
- pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = 0; /* Initial Mix mode power tracking*/
- pRFCalibrateInfo->Remnant_OFDMSwingIdx[p] = 0;
- pRFCalibrateInfo->KfreeOffset[p] = 0;
- }
-
- pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE; /*Initial at Modify Tx Scaling Mode*/
- pRFCalibrateInfo->Modify_TxAGC_Flag_PathB = FALSE; /*Initial at Modify Tx Scaling Mode*/
- pRFCalibrateInfo->Modify_TxAGC_Flag_PathC = FALSE; /*Initial at Modify Tx Scaling Mode*/
- pRFCalibrateInfo->Modify_TxAGC_Flag_PathD = FALSE; /*Initial at Modify Tx Scaling Mode*/
- pRFCalibrateInfo->Remnant_CCKSwingIdx = 0;
- pRFCalibrateInfo->ThermalValue = pHalData->EEPROMThermalMeter;
-
- pRFCalibrateInfo->Modify_TxAGC_Value_CCK=0; //modify by Mingzhi.Guo
- pRFCalibrateInfo->Modify_TxAGC_Value_OFDM=0; //modify by Mingzhi.Guo
-
-}
-
-VOID
-ODM_TXPowerTrackingCallback_ThermalMeter(
-#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
- IN PDM_ODM_T pDM_Odm
-#else
- IN PADAPTER Adapter
-#endif
- )
-{
-
-#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
- #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
- PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
- #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
- PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
- #endif
-#endif
-
- PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
-
- u1Byte ThermalValue = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0;
- s1Byte diff_DPK[4] = {0};
- u1Byte ThermalValue_AVG_count = 0;
- u4Byte ThermalValue_AVG = 0, RegC80, RegCd0, RegCd4, Regab4;
-
- u1Byte OFDM_min_index = 0; // OFDM BB Swing should be less than +3.0dB, which is required by Arthur
- u1Byte Indexforchannel = 0; // GetRightChnlPlaceforIQK(pHalData->CurrentChannel)
- u1Byte PowerTrackingType = pHalData->RfPowerTrackingType;
- u1Byte XtalOffsetEanble = 0;
-
- TXPWRTRACK_CFG c;
-
- //4 1. The following TWO tables decide the final index of OFDM/CCK swing table.
- pu1Byte deltaSwingTableIdx_TUP_A = NULL;
- pu1Byte deltaSwingTableIdx_TDOWN_A = NULL;
- pu1Byte deltaSwingTableIdx_TUP_B = NULL;
- pu1Byte deltaSwingTableIdx_TDOWN_B = NULL;
- /*for 8814 add by Yu Chen*/
- pu1Byte deltaSwingTableIdx_TUP_C = NULL;
- pu1Byte deltaSwingTableIdx_TDOWN_C = NULL;
- pu1Byte deltaSwingTableIdx_TUP_D = NULL;
- pu1Byte deltaSwingTableIdx_TDOWN_D = NULL;
- /*for Xtal Offset by James.Tung*/
- ps1Byte deltaSwingTableXtal_UP = NULL;
- ps1Byte deltaSwingTableXtal_DOWN = NULL;
-
- //4 2. Initilization ( 7 steps in total )
-
- ConfigureTxpowerTrack(pDM_Odm, &c);
-
- (*c.GetDeltaSwingTable)(pDM_Odm, (pu1Byte *)&deltaSwingTableIdx_TUP_A, (pu1Byte *)&deltaSwingTableIdx_TDOWN_A,
- (pu1Byte *)&deltaSwingTableIdx_TUP_B, (pu1Byte *)&deltaSwingTableIdx_TDOWN_B);
-
- if (pDM_Odm->SupportICType & ODM_RTL8814A) /*for 8814 path C & D*/
- (*c.GetDeltaSwingTable8814only)(pDM_Odm, (pu1Byte *)&deltaSwingTableIdx_TUP_C, (pu1Byte *)&deltaSwingTableIdx_TDOWN_C,
- (pu1Byte *)&deltaSwingTableIdx_TUP_D, (pu1Byte *)&deltaSwingTableIdx_TDOWN_D);
-
- if (pDM_Odm->SupportICType & (ODM_RTL8703B | ODM_RTL8723D)) /*for Xtal Offset*/
- (*c.GetDeltaSwingXtalTable)(pDM_Odm, (ps1Byte *)&deltaSwingTableXtal_UP, (ps1Byte *)&deltaSwingTableXtal_DOWN);
-
- pRFCalibrateInfo->TXPowerTrackingCallbackCnt++; /*cosa add for debug*/
- pRFCalibrateInfo->bTXPowerTrackingInit = TRUE;
-
- /*pRFCalibrateInfo->TxPowerTrackControl = pHalData->TxPowerTrackControl;
- We should keep updating the control variable according to HalData.
- RFCalibrateInfo.RegA24 will be initialized when ODM HW configuring, but MP configures with para files. */
- #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
- #if (MP_DRIVER == 1)
- pRFCalibrateInfo->RegA24 = 0x090e1317;
- #endif
- #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
- if (pDM_Odm->mp_mode == TRUE)
- pRFCalibrateInfo->RegA24 = 0x090e1317;
- #endif
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("===>ODM_TXPowerTrackingCallback_ThermalMeter\n pRFCalibrateInfo->BbSwingIdxCckBase: %d, pRFCalibrateInfo->BbSwingIdxOfdmBase[A]: %d, pRFCalibrateInfo->DefaultOfdmIndex: %d\n",
- pRFCalibrateInfo->BbSwingIdxCckBase, pRFCalibrateInfo->BbSwingIdxOfdmBase[ODM_RF_PATH_A], pRFCalibrateInfo->DefaultOfdmIndex));
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("pRFCalibrateInfo->TxPowerTrackControl=%d, pHalData->EEPROMThermalMeter %d\n", pRFCalibrateInfo->TxPowerTrackControl, pHalData->EEPROMThermalMeter));
- ThermalValue = (u1Byte)ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, c.ThermalRegAddr, 0xfc00); //0x42: RF Reg[15:10] 88E
-
- /*add log by zhao he, check c80/c94/c14/ca0 value*/
- if (pDM_Odm->SupportICType == ODM_RTL8723D) {
- RegC80 = ODM_GetBBReg(pDM_Odm, 0xc80, bMaskDWord);
- RegCd0 = ODM_GetBBReg(pDM_Odm, 0xcd0, bMaskDWord);
- RegCd4 = ODM_GetBBReg(pDM_Odm, 0xcd4, bMaskDWord);
- Regab4 = ODM_GetBBReg(pDM_Odm, 0xab4, 0x000007FF);
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", RegC80, RegCd0, RegCd4, Regab4));
- }
-
- if (!pRFCalibrateInfo->TxPowerTrackControl)
- return;
-
-
- /*4 3. Initialize ThermalValues of RFCalibrateInfo*/
-
- if (pRFCalibrateInfo->bReloadtxpowerindex)
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("reload ofdm index for band switch\n"));
-
- /*4 4. Calculate average thermal meter*/
-
- pRFCalibrateInfo->ThermalValue_AVG[pRFCalibrateInfo->ThermalValue_AVG_index] = ThermalValue;
- pRFCalibrateInfo->ThermalValue_AVG_index++;
- if (pRFCalibrateInfo->ThermalValue_AVG_index == c.AverageThermalNum) /*Average times = c.AverageThermalNum*/
- pRFCalibrateInfo->ThermalValue_AVG_index = 0;
-
- for(i = 0; i < c.AverageThermalNum; i++)
- {
- if (pRFCalibrateInfo->ThermalValue_AVG[i]) {
- ThermalValue_AVG += pRFCalibrateInfo->ThermalValue_AVG[i];
- ThermalValue_AVG_count++;
- }
- }
-
- if(ThermalValue_AVG_count) //Calculate Average ThermalValue after average enough times
- {
- ThermalValue = (u1Byte)(ThermalValue_AVG / ThermalValue_AVG_count);
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("AVG Thermal Meter = 0x%X, EFUSE Thermal Base = 0x%X\n", ThermalValue, pHalData->EEPROMThermalMeter));
- }
-
- //4 5. Calculate delta, delta_LCK, delta_IQK.
-
- //"delta" here is used to determine whether thermal value changes or not.
- delta = (ThermalValue > pRFCalibrateInfo->ThermalValue)?(ThermalValue - pRFCalibrateInfo->ThermalValue):(pRFCalibrateInfo->ThermalValue - ThermalValue);
- delta_LCK = (ThermalValue > pRFCalibrateInfo->ThermalValue_LCK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_LCK):(pRFCalibrateInfo->ThermalValue_LCK - ThermalValue);
- delta_IQK = (ThermalValue > pRFCalibrateInfo->ThermalValue_IQK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_IQK):(pRFCalibrateInfo->ThermalValue_IQK - ThermalValue);
-
- if (pRFCalibrateInfo->ThermalValue_IQK == 0xff) { /*no PG, use thermal value for IQK*/
- pRFCalibrateInfo->ThermalValue_IQK = ThermalValue;
- delta_IQK = (ThermalValue > pRFCalibrateInfo->ThermalValue_IQK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_IQK):(pRFCalibrateInfo->ThermalValue_IQK - ThermalValue);
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, use ThermalValue for IQK\n"));
- }
-
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
- diff_DPK[p] = (s1Byte)ThermalValue - (s1Byte)pRFCalibrateInfo->DpkThermal[p];
-
- /*4 6. If necessary, do LCK.*/
-
- if (!(pDM_Odm->SupportICType & ODM_RTL8821)) { /*no PG , do LCK at initial status*/
- if (pRFCalibrateInfo->ThermalValue_LCK == 0xff) {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, do LCK\n"));
- pRFCalibrateInfo->ThermalValue_LCK = ThermalValue;
-
- /*Use RTLCK, so close power tracking driver LCK*/
- if (!(pDM_Odm->SupportICType & ODM_RTL8814A)) {
- if (c.PHY_LCCalibrate)
- (*c.PHY_LCCalibrate)(pDM_Odm);
- }
-
- delta_LCK = (ThermalValue > pRFCalibrateInfo->ThermalValue_LCK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_LCK):(pRFCalibrateInfo->ThermalValue_LCK - ThermalValue);
- }
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK));
-
- /* Delta temperature is equal to or larger than 20 centigrade.*/
- if (delta_LCK >= c.Threshold_IQK) {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= Threshold_IQK(%d)\n", delta_LCK, c.Threshold_IQK));
- pRFCalibrateInfo->ThermalValue_LCK = ThermalValue;
-
- /*Use RTLCK, so close power tracking driver LCK*/
- if (!(pDM_Odm->SupportICType & ODM_RTL8814A)) {
- if (c.PHY_LCCalibrate)
- (*c.PHY_LCCalibrate)(pDM_Odm);
- }
- }
- }
-
- /*3 7. If necessary, move the index of swing table to adjust Tx power.*/
-
- if (delta > 0 && pRFCalibrateInfo->TxPowerTrackControl)
- {
- //"delta" here is used to record the absolute value of differrence.
-#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
- delta = ThermalValue > pHalData->EEPROMThermalMeter?(ThermalValue - pHalData->EEPROMThermalMeter):(pHalData->EEPROMThermalMeter - ThermalValue);
-#else
- delta = (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther)?(ThermalValue - pDM_Odm->priv->pmib->dot11RFEntry.ther):(pDM_Odm->priv->pmib->dot11RFEntry.ther - ThermalValue);
-#endif
- if (delta >= TXPWR_TRACK_TABLE_SIZE)
- delta = TXPWR_TRACK_TABLE_SIZE - 1;
-
- /*4 7.1 The Final Power Index = BaseIndex + PowerIndexOffset*/
-
-#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
- if(ThermalValue > pHalData->EEPROMThermalMeter) {
-#else
- if(ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) {
-#endif
-
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) {
- pRFCalibrateInfo->DeltaPowerIndexLast[p] = pRFCalibrateInfo->DeltaPowerIndex[p]; /*recording poer index offset*/
- switch (p) {
- case ODM_RF_PATH_B:
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("deltaSwingTableIdx_TUP_B[%d] = %d\n", delta, deltaSwingTableIdx_TUP_B[delta]));
-
- pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_B[delta];
- pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_B[delta]; /*Record delta swing for mix mode power tracking*/
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
- break;
-
- case ODM_RF_PATH_C:
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("deltaSwingTableIdx_TUP_C[%d] = %d\n", delta, deltaSwingTableIdx_TUP_C[delta]));
-
- pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_C[delta];
- pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_C[delta]; /*Record delta swing for mix mode power tracking*/
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
- break;
-
- case ODM_RF_PATH_D:
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("deltaSwingTableIdx_TUP_D[%d] = %d\n", delta, deltaSwingTableIdx_TUP_D[delta]));
-
- pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_D[delta];
- pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_D[delta]; /*Record delta swing for mix mode power tracking*/
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
- break;
-
- default:
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("deltaSwingTableIdx_TUP_A[%d] = %d\n", delta, deltaSwingTableIdx_TUP_A[delta]));
-
- pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_A[delta];
- pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_A[delta]; /*Record delta swing for mix mode power tracking*/
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
- break;
- }
- }
-
- if (pDM_Odm->SupportICType & (ODM_RTL8703B | ODM_RTL8723D)) {
- /*Save XtalOffset from Xtal table*/
- pRFCalibrateInfo->XtalOffsetLast = pRFCalibrateInfo->XtalOffset; /*recording last Xtal offset*/
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("[Xtal] deltaSwingTableXtal_UP[%d] = %d\n", delta, deltaSwingTableXtal_UP[delta]));
- pRFCalibrateInfo->XtalOffset = deltaSwingTableXtal_UP[delta];
-
- if (pRFCalibrateInfo->XtalOffsetLast == pRFCalibrateInfo->XtalOffset)
- XtalOffsetEanble = 0;
- else
- XtalOffsetEanble = 1;
- }
-
- } else {
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) {
- pRFCalibrateInfo->DeltaPowerIndexLast[p] = pRFCalibrateInfo->DeltaPowerIndex[p]; /*recording poer index offset*/
-
- switch (p) {
- case ODM_RF_PATH_B:
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("deltaSwingTableIdx_TDOWN_B[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_B[delta]));
- pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_B[delta];
- pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_B[delta]; /*Record delta swing for mix mode power tracking*/
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
- break;
-
- case ODM_RF_PATH_C:
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("deltaSwingTableIdx_TDOWN_C[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_C[delta]));
- pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_C[delta];
- pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_C[delta]; /*Record delta swing for mix mode power tracking*/
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
- break;
-
- case ODM_RF_PATH_D:
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("deltaSwingTableIdx_TDOWN_D[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_D[delta]));
- pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_D[delta];
- pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_D[delta]; /*Record delta swing for mix mode power tracking*/
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
- break;
-
- default:
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("deltaSwingTableIdx_TDOWN_A[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_A[delta]));
- pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_A[delta];
- pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_A[delta]; /*Record delta swing for mix mode power tracking*/
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
- break;
- }
- }
-
- if (pDM_Odm->SupportICType & (ODM_RTL8703B | ODM_RTL8723D)) {
- /*Save XtalOffset from Xtal table*/
- pRFCalibrateInfo->XtalOffsetLast = pRFCalibrateInfo->XtalOffset; /*recording last Xtal offset*/
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("[Xtal] deltaSwingTableXtal_DOWN[%d] = %d\n", delta, deltaSwingTableXtal_DOWN[delta]));
- pRFCalibrateInfo->XtalOffset = deltaSwingTableXtal_DOWN[delta];
-
- if (pRFCalibrateInfo->XtalOffsetLast == pRFCalibrateInfo->XtalOffset)
- XtalOffsetEanble = 0;
- else
- XtalOffsetEanble = 1;
- }
-
- }
-
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("\n\n=========================== [Path-%d] Calculating PowerIndexOffset===========================\n", p));
-
- if (pRFCalibrateInfo->DeltaPowerIndex[p] == pRFCalibrateInfo->DeltaPowerIndexLast[p]) /*If Thermal value changes but lookup table value still the same*/
- pRFCalibrateInfo->PowerIndexOffset[p] = 0;
- else
- pRFCalibrateInfo->PowerIndexOffset[p] = pRFCalibrateInfo->DeltaPowerIndex[p] - pRFCalibrateInfo->DeltaPowerIndexLast[p]; /*Power Index Diff between 2 times Power Tracking*/
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("[Path-%d] PowerIndexOffset(%d) = DeltaPowerIndex(%d) - DeltaPowerIndexLast(%d)\n", p, pRFCalibrateInfo->PowerIndexOffset[p], pRFCalibrateInfo->DeltaPowerIndex[p], pRFCalibrateInfo->DeltaPowerIndexLast[p]));
-
- pRFCalibrateInfo->OFDM_index[p] = pRFCalibrateInfo->BbSwingIdxOfdmBase[p] + pRFCalibrateInfo->PowerIndexOffset[p];
- pRFCalibrateInfo->CCK_index = pRFCalibrateInfo->BbSwingIdxCckBase + pRFCalibrateInfo->PowerIndexOffset[p];
-
- pRFCalibrateInfo->BbSwingIdxCck = pRFCalibrateInfo->CCK_index;
- pRFCalibrateInfo->BbSwingIdxOfdm[p] = pRFCalibrateInfo->OFDM_index[p];
-
- /*************Print BB Swing Base and Index Offset*************/
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("The 'CCK' final index(%d) = BaseIndex(%d) + PowerIndexOffset(%d)\n", pRFCalibrateInfo->BbSwingIdxCck, pRFCalibrateInfo->BbSwingIdxCckBase, pRFCalibrateInfo->PowerIndexOffset[p]));
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("The 'OFDM' final index(%d) = BaseIndex[%d](%d) + PowerIndexOffset(%d)\n", pRFCalibrateInfo->BbSwingIdxOfdm[p], p, pRFCalibrateInfo->BbSwingIdxOfdmBase[p], pRFCalibrateInfo->PowerIndexOffset[p]));
-
- /*4 7.1 Handle boundary conditions of index.*/
-
- if (pRFCalibrateInfo->OFDM_index[p] > c.SwingTableSize_OFDM-1)
- pRFCalibrateInfo->OFDM_index[p] = c.SwingTableSize_OFDM-1;
- else if (pRFCalibrateInfo->OFDM_index[p] <= OFDM_min_index)
- pRFCalibrateInfo->OFDM_index[p] = OFDM_min_index;
- }
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("\n\n========================================================================================================\n"));
-
- if (pRFCalibrateInfo->CCK_index > c.SwingTableSize_CCK-1)
- pRFCalibrateInfo->CCK_index = c.SwingTableSize_CCK-1;
- else if (pRFCalibrateInfo->CCK_index <= 0)
- pRFCalibrateInfo->CCK_index = 0;
- } else {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("The thermal meter is unchanged or TxPowerTracking OFF(%d): ThermalValue: %d , pRFCalibrateInfo->ThermalValue: %d\n",
- pRFCalibrateInfo->TxPowerTrackControl, ThermalValue, pRFCalibrateInfo->ThermalValue));
-
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
- pRFCalibrateInfo->PowerIndexOffset[p] = 0;
- }
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("TxPowerTracking: [CCK] Swing Current Index: %d, Swing Base Index: %d\n",
- pRFCalibrateInfo->CCK_index, pRFCalibrateInfo->BbSwingIdxCckBase)); /*Print Swing base & current*/
-
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("TxPowerTracking: [OFDM] Swing Current Index: %d, Swing Base Index[%d]: %d\n",
- pRFCalibrateInfo->OFDM_index[p], p, pRFCalibrateInfo->BbSwingIdxOfdmBase[p]));
- }
-
- if ((pDM_Odm->SupportICType & ODM_RTL8814A)) {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("PowerTrackingType=%d\n", PowerTrackingType));
-
- if (PowerTrackingType == 0) {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n"));
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
- (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0);
- } else if (PowerTrackingType == 1) {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(2G) TSSI(5G) MODE**********\n"));
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
- (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_2G_TSSI_5G_MODE, p, 0);
- } else if (PowerTrackingType == 2) {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(5G) TSSI(2G)MODE**********\n"));
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
- (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_5G_TSSI_2G_MODE, p, 0);
- } else if (PowerTrackingType == 3) {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking TSSI MODE**********\n"));
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
- (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, TSSI_MODE, p, 0);
- }
- pRFCalibrateInfo->ThermalValue = ThermalValue; /*Record last Power Tracking Thermal Value*/
-
- } else if ((pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_A] != 0 ||
- pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_B] != 0 ||
- pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_C] != 0 ||
- pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_D] != 0) &&
- pRFCalibrateInfo->TxPowerTrackControl && (pHalData->EEPROMThermalMeter != 0xff)) {
- //4 7.2 Configure the Swing Table to adjust Tx Power.
-
- pRFCalibrateInfo->bTxPowerChanged = TRUE; /*Always TRUE after Tx Power is adjusted by power tracking.*/
- //
- // 2012/04/23 MH According to Luke's suggestion, we can not write BB digital
- // to increase TX power. Otherwise, EVM will be bad.
- //
- // 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E.
- if (ThermalValue > pRFCalibrateInfo->ThermalValue) {
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("Temperature Increasing(%d): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
- p, pRFCalibrateInfo->PowerIndexOffset[p], delta, ThermalValue, pHalData->EEPROMThermalMeter, pRFCalibrateInfo->ThermalValue));
- }
- } else if (ThermalValue < pRFCalibrateInfo->ThermalValue) { /*Low temperature*/
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("Temperature Decreasing(%d): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
- p, pRFCalibrateInfo->PowerIndexOffset[p], delta, ThermalValue, pHalData->EEPROMThermalMeter, pRFCalibrateInfo->ThermalValue));
- }
- }
-
-#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
- if (ThermalValue > pHalData->EEPROMThermalMeter)
-#else
- if (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther)
-#endif
- {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("Temperature(%d) higher than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter));
-
- if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8821 ||
- pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8723B || pDM_Odm->SupportICType == ODM_RTL8814A ||
- pDM_Odm->SupportICType == ODM_RTL8703B || pDM_Odm->SupportICType == ODM_RTL8188F || pDM_Odm->SupportICType == ODM_RTL8822B || pDM_Odm->SupportICType == ODM_RTL8723D) {
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n"));
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
- (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0);
- } else {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n"));
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
- (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, p, Indexforchannel);
- }
- }
- else
- {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("Temperature(%d) lower than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter));
-
- if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8821 ||
- pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8723B || pDM_Odm->SupportICType == ODM_RTL8814A ||
- pDM_Odm->SupportICType == ODM_RTL8703B || pDM_Odm->SupportICType == ODM_RTL8188F || pDM_Odm->SupportICType == ODM_RTL8822B || pDM_Odm->SupportICType == ODM_RTL8723D) {
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n"));
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
- (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, Indexforchannel);
- } else {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n"));
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
- (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, p, Indexforchannel);
- }
-
- }
-
- pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->BbSwingIdxCck; /*Record last time Power Tracking result as base.*/
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
- pRFCalibrateInfo->BbSwingIdxOfdmBase[p] = pRFCalibrateInfo->BbSwingIdxOfdm[p];
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("pRFCalibrateInfo->ThermalValue = %d ThermalValue= %d\n", pRFCalibrateInfo->ThermalValue, ThermalValue));
-
- pRFCalibrateInfo->ThermalValue = ThermalValue; /*Record last Power Tracking Thermal Value*/
-
- }
-
-
- if (pDM_Odm->SupportICType == ODM_RTL8703B || pDM_Odm->SupportICType == ODM_RTL8723D) {
-
- if (XtalOffsetEanble != 0 && pRFCalibrateInfo->TxPowerTrackControl && (pHalData->EEPROMThermalMeter != 0xff)) {
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter Xtal Tracking**********\n"));
-
-#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
- if (ThermalValue > pHalData->EEPROMThermalMeter) {
-#else
- if (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) {
-#endif
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("Temperature(%d) higher than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter));
- (*c.ODM_TxXtalTrackSetXtal)(pDM_Odm);
- } else {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("Temperature(%d) lower than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter));
- (*c.ODM_TxXtalTrackSetXtal)(pDM_Odm);
- }
- }
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********End Xtal Tracking**********\n"));
- }
-
-#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
-
- if (!IS_HARDWARE_TYPE_8723B(Adapter)) {
- /*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
- if (delta_IQK >= c.Threshold_IQK) {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_IQK(%d) >= Threshold_IQK(%d)\n", delta_IQK, c.Threshold_IQK));
- if (!pRFCalibrateInfo->bIQKInProgress)
- (*c.DoIQK)(pDM_Odm, delta_IQK, ThermalValue, 8);
- }
- }
- if (pRFCalibrateInfo->DpkThermal[ODM_RF_PATH_A] != 0) {
- if (diff_DPK[ODM_RF_PATH_A] >= c.Threshold_DPK) {
- ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1);
- ODM_SetBBReg(pDM_Odm, 0xcc4, BIT14|BIT13|BIT12|BIT11|BIT10, (diff_DPK[ODM_RF_PATH_A] / c.Threshold_DPK));
- ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0);
- } else if ((diff_DPK[ODM_RF_PATH_A] <= -1 * c.Threshold_DPK)) {
- s4Byte value = 0x20 + (diff_DPK[ODM_RF_PATH_A] / c.Threshold_DPK);
-
- ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1);
- ODM_SetBBReg(pDM_Odm, 0xcc4, BIT14|BIT13|BIT12|BIT11|BIT10, value);
- ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0);
- } else {
- ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1);
- ODM_SetBBReg(pDM_Odm, 0xcc4, BIT14|BIT13|BIT12|BIT11|BIT10, 0);
- ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0);
- }
- }
- if (pRFCalibrateInfo->DpkThermal[ODM_RF_PATH_B] != 0) {
- if (diff_DPK[ODM_RF_PATH_B] >= c.Threshold_DPK) {
- ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1);
- ODM_SetBBReg(pDM_Odm, 0xec4, BIT14|BIT13|BIT12|BIT11|BIT10, (diff_DPK[ODM_RF_PATH_B] / c.Threshold_DPK));
- ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0);
- } else if ((diff_DPK[ODM_RF_PATH_B] <= -1 * c.Threshold_DPK)) {
- s4Byte value = 0x20 + (diff_DPK[ODM_RF_PATH_B] / c.Threshold_DPK);
-
- ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1);
- ODM_SetBBReg(pDM_Odm, 0xec4, BIT14|BIT13|BIT12|BIT11|BIT10, value);
- ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0);
- } else {
- ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1);
- ODM_SetBBReg(pDM_Odm, 0xec4, BIT14|BIT13|BIT12|BIT11|BIT10, 0);
- ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0);
- }
- }
-
-#endif
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("<===ODM_TXPowerTrackingCallback_ThermalMeter\n"));
-
- pRFCalibrateInfo->TXPowercount = 0;
-}
-
-
-
-//3============================================================
-//3 IQ Calibration
-//3============================================================
-
-VOID
-ODM_ResetIQKResult(
- IN PVOID pDM_VOID
-)
-{
- return;
-}
-#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
-u1Byte ODM_GetRightChnlPlaceforIQK(u1Byte chnl)
-{
- u1Byte channel_all[ODM_TARGET_CHNL_NUM_2G_5G] =
- {1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,100,102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,132,134,136,138,140,149,151,153,155,157,159,161,163,165};
- u1Byte place = chnl;
-
-
- if(chnl > 14)
- {
- for(place = 14; placeAdapter;
-
-#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
- if (*pDM_Odm->pIsFcsModeEnable)
- return;
-#endif
-
-#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
- if (IS_HARDWARE_TYPE_8812AU(Adapter))
- return;
-#endif
-
- if (pDM_Odm->bLinked) {
- if ((*pDM_Odm->pChannel != pDM_Odm->preChannel) && (!*pDM_Odm->pbScanInProcess)) {
- pDM_Odm->preChannel = *pDM_Odm->pChannel;
- pDM_Odm->LinkedInterval = 0;
- }
-
- if (pDM_Odm->LinkedInterval < 3)
- pDM_Odm->LinkedInterval++;
-
- if (pDM_Odm->LinkedInterval == 2) {
- if (IS_HARDWARE_TYPE_8814A(Adapter)) {
- #if (RTL8814A_SUPPORT == 1)
- PHY_IQCalibrate_8814A(pDM_Odm, FALSE);
- #endif
- }
-
- #if (RTL8822B_SUPPORT == 1)
- else if (IS_HARDWARE_TYPE_8822B(Adapter))
- PHY_IQCalibrate_8822B(pDM_Odm, FALSE);
- #endif
-
- #if (RTL8821C_SUPPORT == 1)
- else if (IS_HARDWARE_TYPE_8821C(Adapter))
- PHY_IQCalibrate_8821C(pDM_Odm, FALSE);
- #endif
-
- #if (RTL8821A_SUPPORT == 1)
- else if (IS_HARDWARE_TYPE_8821(Adapter))
- PHY_IQCalibrate_8821A(pDM_Odm, FALSE);
- #endif
- }
- } else
- pDM_Odm->LinkedInterval = 0;
-}
-
-void phydm_rf_init(IN PVOID pDM_VOID)
-{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- odm_TXPowerTrackingInit(pDM_Odm);
-
-#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
- ODM_ClearTxPowerTrackingState(pDM_Odm);
-#endif
-
-#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-#if (RTL8814A_SUPPORT == 1)
- if (pDM_Odm->SupportICType & ODM_RTL8814A)
- PHY_IQCalibrate_8814A_Init(pDM_Odm);
-#endif
-#endif
-
-}
-
-void phydm_rf_watchdog(IN PVOID pDM_VOID)
-{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
-#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
- ODM_TXPowerTrackingCheck(pDM_Odm);
- if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
- odm_IQCalibrate(pDM_Odm);
-#endif
-}
diff --git a/hal/phydm/halphyrf_ce.h b/hal/phydm/halphyrf_ce.h
deleted file mode 100644
index a0ed5dc..0000000
--- a/hal/phydm/halphyrf_ce.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of version 2 of the GNU General Public License as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
-
- #ifndef __HAL_PHY_RF_H__
- #define __HAL_PHY_RF_H__
-
-#include "phydm_kfree.h"
-#if (RTL8814A_SUPPORT == 1)
-#include "rtl8814a/phydm_iqk_8814a.h"
-#endif
-
-#if (RTL8822B_SUPPORT == 1)
-#include "rtl8822b/phydm_iqk_8822b.h"
-#endif
-
-#if (RTL8821C_SUPPORT == 1)
-#include "rtl8821c/phydm_iqk_8821c.h"
-#endif
-
-#include "phydm_powertracking_ce.h"
-
-
-typedef enum _SPUR_CAL_METHOD {
- PLL_RESET,
- AFE_PHASE_SEL
-} SPUR_CAL_METHOD;
-
-typedef enum _PWRTRACK_CONTROL_METHOD {
- BBSWING,
- TXAGC,
- MIX_MODE,
- TSSI_MODE,
- MIX_2G_TSSI_5G_MODE,
- MIX_5G_TSSI_2G_MODE
-} PWRTRACK_METHOD;
-
-typedef VOID (*FuncSetPwr)(PVOID, PWRTRACK_METHOD, u1Byte, u1Byte);
-typedef VOID(*FuncIQK)(PVOID, u1Byte, u1Byte, u1Byte);
-typedef VOID (*FuncLCK)(PVOID);
-typedef VOID (*FuncSwing)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*);
-typedef VOID (*FuncSwing8814only)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*);
-typedef VOID(*FuncSwingXtal)(PVOID, ps1Byte*, ps1Byte*);
-typedef VOID(*FuncSetXtal)(PVOID);
-
-typedef struct _TXPWRTRACK_CFG {
- u1Byte SwingTableSize_CCK;
- u1Byte SwingTableSize_OFDM;
- u1Byte Threshold_IQK;
- u1Byte Threshold_DPK;
- u1Byte AverageThermalNum;
- u1Byte RfPathCount;
- u4Byte ThermalRegAddr;
- FuncSetPwr ODM_TxPwrTrackSetPwr;
- FuncIQK DoIQK;
- FuncLCK PHY_LCCalibrate;
- FuncSwing GetDeltaSwingTable;
- FuncSwing8814only GetDeltaSwingTable8814only;
- FuncSwingXtal GetDeltaSwingXtalTable;
- FuncSetXtal ODM_TxXtalTrackSetXtal;
-} TXPWRTRACK_CFG, *PTXPWRTRACK_CFG;
-
-VOID
-ConfigureTxpowerTrack(
- IN PVOID pDM_VOID,
- OUT PTXPWRTRACK_CFG pConfig
- );
-
-
-VOID
-ODM_ClearTxPowerTrackingState(
- IN PVOID pDM_VOID
- );
-
-VOID
-ODM_TXPowerTrackingCallback_ThermalMeter(
-#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
- IN PVOID pDM_VOID
-#else
- IN PADAPTER Adapter
-#endif
- );
-
-
-
-#define ODM_TARGET_CHNL_NUM_2G_5G 59
-
-
-VOID
-ODM_ResetIQKResult(
- IN PVOID pDM_VOID
-);
-u1Byte
-ODM_GetRightChnlPlaceforIQK(
- IN u1Byte chnl
-);
-
-void phydm_rf_init( IN PVOID pDM_VOID);
-void phydm_rf_watchdog( IN PVOID pDM_VOID);
-
-#endif // #ifndef __HAL_PHY_RF_H__
-
diff --git a/hal/phydm/halphyrf_win.c b/hal/phydm/halphyrf_win.c
deleted file mode 100644
index a93860f..0000000
--- a/hal/phydm/halphyrf_win.c
+++ /dev/null
@@ -1,780 +0,0 @@
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of version 2 of the GNU General Public License as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
-
-#include "mp_precomp.h"
-#include "phydm_precomp.h"
-
-#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _deltaThermal) \
- do {\
- for(_offset = 0; _offset < _size; _offset++)\
- {\
- if(_deltaThermal < thermalThreshold[_direction][_offset])\
- {\
- if(_offset != 0)\
- _offset--;\
- break;\
- }\
- } \
- if(_offset >= _size)\
- _offset = _size-1;\
- } while(0)
-
-void ConfigureTxpowerTrack(
- IN PDM_ODM_T pDM_Odm,
- OUT PTXPWRTRACK_CFG pConfig
- )
-{
-#if RTL8192E_SUPPORT
- if (pDM_Odm->SupportICType == ODM_RTL8192E)
- ConfigureTxpowerTrack_8192E(pConfig);
-#endif
-#if RTL8821A_SUPPORT
- if (pDM_Odm->SupportICType == ODM_RTL8821)
- ConfigureTxpowerTrack_8821A(pConfig);
-#endif
-#if RTL8812A_SUPPORT
- if (pDM_Odm->SupportICType == ODM_RTL8812)
- ConfigureTxpowerTrack_8812A(pConfig);
-#endif
-#if RTL8188E_SUPPORT
- if (pDM_Odm->SupportICType == ODM_RTL8188E)
- ConfigureTxpowerTrack_8188E(pConfig);
-#endif
-
-#if RTL8188F_SUPPORT
- if (pDM_Odm->SupportICType == ODM_RTL8188F)
- ConfigureTxpowerTrack_8188F(pConfig);
-#endif
-
-#if RTL8723B_SUPPORT
- if (pDM_Odm->SupportICType == ODM_RTL8723B)
- ConfigureTxpowerTrack_8723B(pConfig);
-#endif
-
-#if RTL8814A_SUPPORT
- if (pDM_Odm->SupportICType == ODM_RTL8814A)
- ConfigureTxpowerTrack_8814A(pConfig);
-#endif
-
-#if RTL8703B_SUPPORT
- if (pDM_Odm->SupportICType == ODM_RTL8703B)
- ConfigureTxpowerTrack_8703B(pConfig);
-#endif
-
-#if RTL8822B_SUPPORT
- if (pDM_Odm->SupportICType == ODM_RTL8822B)
- ConfigureTxpowerTrack_8822B(pConfig);
-#endif
-
-#if RTL8723D_SUPPORT
- if (pDM_Odm->SupportICType == ODM_RTL8723D)
- ConfigureTxpowerTrack_8723D(pConfig);
-#endif
-}
-
-//======================================================================
-// <20121113, Kordan> This function should be called when TxAGC changed.
-// Otherwise the previous compensation is gone, because we record the
-// delta of temperature between two TxPowerTracking watch dogs.
-//
-// NOTE: If Tx BB swing or Tx scaling is varified during run-time, still
-// need to call this function.
-//======================================================================
-VOID
-ODM_ClearTxPowerTrackingState(
- IN PDM_ODM_T pDM_Odm
- )
-{
- PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pDM_Odm->Adapter);
- u1Byte p = 0;
- PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
-
- pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->DefaultCckIndex;
- pRFCalibrateInfo->BbSwingIdxCck = pRFCalibrateInfo->DefaultCckIndex;
- pRFCalibrateInfo->CCK_index = 0;
-
- for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p)
- {
- pRFCalibrateInfo->BbSwingIdxOfdmBase[p] = pRFCalibrateInfo->DefaultOfdmIndex;
- pRFCalibrateInfo->BbSwingIdxOfdm[p] = pRFCalibrateInfo->DefaultOfdmIndex;
- pRFCalibrateInfo->OFDM_index[p] = pRFCalibrateInfo->DefaultOfdmIndex;
-
- pRFCalibrateInfo->PowerIndexOffset[p] = 0;
- pRFCalibrateInfo->DeltaPowerIndex[p] = 0;
- pRFCalibrateInfo->DeltaPowerIndexLast[p] = 0;
-
- pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = 0; /* Initial Mix mode power tracking*/
- pRFCalibrateInfo->Remnant_OFDMSwingIdx[p] = 0;
- pRFCalibrateInfo->KfreeOffset[p] = 0;
- }
-
- pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE; /*Initial at Modify Tx Scaling Mode*/
- pRFCalibrateInfo->Modify_TxAGC_Flag_PathB = FALSE; /*Initial at Modify Tx Scaling Mode*/
- pRFCalibrateInfo->Modify_TxAGC_Flag_PathC = FALSE; /*Initial at Modify Tx Scaling Mode*/
- pRFCalibrateInfo->Modify_TxAGC_Flag_PathD = FALSE; /*Initial at Modify Tx Scaling Mode*/
- pRFCalibrateInfo->Remnant_CCKSwingIdx = 0;
- pRFCalibrateInfo->ThermalValue = pHalData->EEPROMThermalMeter;
-
- pRFCalibrateInfo->Modify_TxAGC_Value_CCK=0; //modify by Mingzhi.Guo
- pRFCalibrateInfo->Modify_TxAGC_Value_OFDM=0; //modify by Mingzhi.Guo
-
-}
-
-VOID
-ODM_TXPowerTrackingCallback_ThermalMeter(
-#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
- IN PDM_ODM_T pDM_Odm
-#else
- IN PADAPTER Adapter
-#endif
- )
-{
-#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
-#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
- PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
-#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
- PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
-#endif
-#endif
-
- PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
-
- u1Byte ThermalValue = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0;
- s1Byte diff_DPK[4] = {0};
- u1Byte ThermalValue_AVG_count = 0;
- u4Byte ThermalValue_AVG = 0, RegC80, RegCd0, RegCd4, Regab4;
-
- u1Byte OFDM_min_index = 0; // OFDM BB Swing should be less than +3.0dB, which is required by Arthur
- u1Byte Indexforchannel = 0; // GetRightChnlPlaceforIQK(pHalData->CurrentChannel)
- u1Byte PowerTrackingType = pHalData->RfPowerTrackingType;
- u1Byte XtalOffsetEanble = 0;
-
- TXPWRTRACK_CFG c;
-
- //4 1. The following TWO tables decide the final index of OFDM/CCK swing table.
- pu1Byte deltaSwingTableIdx_TUP_A = NULL;
- pu1Byte deltaSwingTableIdx_TDOWN_A = NULL;
- pu1Byte deltaSwingTableIdx_TUP_B = NULL;
- pu1Byte deltaSwingTableIdx_TDOWN_B = NULL;
- /*for 8814 add by Yu Chen*/
- pu1Byte deltaSwingTableIdx_TUP_C = NULL;
- pu1Byte deltaSwingTableIdx_TDOWN_C = NULL;
- pu1Byte deltaSwingTableIdx_TUP_D = NULL;
- pu1Byte deltaSwingTableIdx_TDOWN_D = NULL;
- /*for Xtal Offset by James.Tung*/
- ps1Byte deltaSwingTableXtal_UP = NULL;
- ps1Byte deltaSwingTableXtal_DOWN = NULL;
-
- //4 2. Initilization ( 7 steps in total )
-
- ConfigureTxpowerTrack(pDM_Odm, &c);
-
- (*c.GetDeltaSwingTable)(pDM_Odm, (pu1Byte *)&deltaSwingTableIdx_TUP_A, (pu1Byte *)&deltaSwingTableIdx_TDOWN_A,
- (pu1Byte *)&deltaSwingTableIdx_TUP_B, (pu1Byte *)&deltaSwingTableIdx_TDOWN_B);
-
- if (pDM_Odm->SupportICType & ODM_RTL8814A) /*for 8814 path C & D*/
- (*c.GetDeltaSwingTable8814only)(pDM_Odm, (pu1Byte *)&deltaSwingTableIdx_TUP_C, (pu1Byte *)&deltaSwingTableIdx_TDOWN_C,
- (pu1Byte *)&deltaSwingTableIdx_TUP_D, (pu1Byte *)&deltaSwingTableIdx_TDOWN_D);
-
- if (pDM_Odm->SupportICType & (ODM_RTL8703B | ODM_RTL8723D)) /*for Xtal Offset*/
- (*c.GetDeltaSwingXtalTable)(pDM_Odm, (ps1Byte *)&deltaSwingTableXtal_UP, (ps1Byte *)&deltaSwingTableXtal_DOWN);
-
-
- pRFCalibrateInfo->TXPowerTrackingCallbackCnt++; /*cosa add for debug*/
- pRFCalibrateInfo->bTXPowerTrackingInit = TRUE;
-
- /*pRFCalibrateInfo->TxPowerTrackControl = pHalData->TxPowerTrackControl;
- We should keep updating the control variable according to HalData.
- RFCalibrateInfo.RegA24 will be initialized when ODM HW configuring, but MP configures with para files. */
- #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
- #if (MP_DRIVER == 1)
- pRFCalibrateInfo->RegA24 = 0x090e1317;
- #endif
- #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
- if (pDM_Odm->mp_mode == TRUE)
- pRFCalibrateInfo->RegA24 = 0x090e1317;
- #endif
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("===>ODM_TXPowerTrackingCallback_ThermalMeter\n pRFCalibrateInfo->BbSwingIdxCckBase: %d, pRFCalibrateInfo->BbSwingIdxOfdmBase[A]: %d, pRFCalibrateInfo->DefaultOfdmIndex: %d\n",
- pRFCalibrateInfo->BbSwingIdxCckBase, pRFCalibrateInfo->BbSwingIdxOfdmBase[ODM_RF_PATH_A], pRFCalibrateInfo->DefaultOfdmIndex));
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("pRFCalibrateInfo->TxPowerTrackControl=%d, pHalData->EEPROMThermalMeter %d\n", pRFCalibrateInfo->TxPowerTrackControl, pHalData->EEPROMThermalMeter));
- ThermalValue = (u1Byte)ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, c.ThermalRegAddr, 0xfc00); //0x42: RF Reg[15:10] 88E
-
- /*add log by zhao he, check c80/c94/c14/ca0 value*/
- if (pDM_Odm->SupportICType == ODM_RTL8723D) {
- RegC80 = ODM_GetBBReg(pDM_Odm, 0xc80, bMaskDWord);
- RegCd0 = ODM_GetBBReg(pDM_Odm, 0xcd0, bMaskDWord);
- RegCd4 = ODM_GetBBReg(pDM_Odm, 0xcd4, bMaskDWord);
- Regab4 = ODM_GetBBReg(pDM_Odm, 0xab4, 0x000007FF);
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", RegC80, RegCd0, RegCd4, Regab4));
- }
-
- if (!pRFCalibrateInfo->TxPowerTrackControl)
- return;
-
-
- /*4 3. Initialize ThermalValues of RFCalibrateInfo*/
-
- if (pRFCalibrateInfo->bReloadtxpowerindex)
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("reload ofdm index for band switch\n"));
-
- /*4 4. Calculate average thermal meter*/
-
- pRFCalibrateInfo->ThermalValue_AVG[pRFCalibrateInfo->ThermalValue_AVG_index] = ThermalValue;
- pRFCalibrateInfo->ThermalValue_AVG_index++;
- if (pRFCalibrateInfo->ThermalValue_AVG_index == c.AverageThermalNum) /*Average times = c.AverageThermalNum*/
- pRFCalibrateInfo->ThermalValue_AVG_index = 0;
-
- for(i = 0; i < c.AverageThermalNum; i++)
- {
- if (pRFCalibrateInfo->ThermalValue_AVG[i]) {
- ThermalValue_AVG += pRFCalibrateInfo->ThermalValue_AVG[i];
- ThermalValue_AVG_count++;
- }
- }
-
- if(ThermalValue_AVG_count) //Calculate Average ThermalValue after average enough times
- {
- ThermalValue = (u1Byte)(ThermalValue_AVG / ThermalValue_AVG_count);
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("AVG Thermal Meter = 0x%X, EFUSE Thermal Base = 0x%X\n", ThermalValue, pHalData->EEPROMThermalMeter));
- }
-
- //4 5. Calculate delta, delta_LCK, delta_IQK.
-
- //"delta" here is used to determine whether thermal value changes or not.
- delta = (ThermalValue > pRFCalibrateInfo->ThermalValue)?(ThermalValue - pRFCalibrateInfo->ThermalValue):(pRFCalibrateInfo->ThermalValue - ThermalValue);
- delta_LCK = (ThermalValue > pRFCalibrateInfo->ThermalValue_LCK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_LCK):(pRFCalibrateInfo->ThermalValue_LCK - ThermalValue);
- delta_IQK = (ThermalValue > pRFCalibrateInfo->ThermalValue_IQK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_IQK):(pRFCalibrateInfo->ThermalValue_IQK - ThermalValue);
-
- if (pRFCalibrateInfo->ThermalValue_IQK == 0xff) { /*no PG, use thermal value for IQK*/
- pRFCalibrateInfo->ThermalValue_IQK = ThermalValue;
- delta_IQK = (ThermalValue > pRFCalibrateInfo->ThermalValue_IQK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_IQK):(pRFCalibrateInfo->ThermalValue_IQK - ThermalValue);
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, use ThermalValue for IQK\n"));
- }
-
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
- diff_DPK[p] = (s1Byte)ThermalValue - (s1Byte)pRFCalibrateInfo->DpkThermal[p];
-
- /*4 6. If necessary, do LCK.*/
-
- if (!(pDM_Odm->SupportICType & ODM_RTL8821)) { /*no PG , do LCK at initial status*/
- if (pRFCalibrateInfo->ThermalValue_LCK == 0xff) {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, do LCK\n"));
- pRFCalibrateInfo->ThermalValue_LCK = ThermalValue;
-
- /*Use RTLCK, so close power tracking driver LCK*/
- if (!(pDM_Odm->SupportICType & ODM_RTL8814A)) {
- if (c.PHY_LCCalibrate)
- (*c.PHY_LCCalibrate)(pDM_Odm);
- }
-
- delta_LCK = (ThermalValue > pRFCalibrateInfo->ThermalValue_LCK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_LCK):(pRFCalibrateInfo->ThermalValue_LCK - ThermalValue);
- }
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK));
-
- /* Delta temperature is equal to or larger than 20 centigrade.*/
- if (delta_LCK >= c.Threshold_IQK) {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= Threshold_IQK(%d)\n", delta_LCK, c.Threshold_IQK));
- pRFCalibrateInfo->ThermalValue_LCK = ThermalValue;
-
- /*Use RTLCK, so close power tracking driver LCK*/
- if (!(pDM_Odm->SupportICType & ODM_RTL8814A)) {
- if (c.PHY_LCCalibrate)
- (*c.PHY_LCCalibrate)(pDM_Odm);
- }
- }
- }
-
- /*3 7. If necessary, move the index of swing table to adjust Tx power.*/
-
- if (delta > 0 && pRFCalibrateInfo->TxPowerTrackControl)
- {
- //"delta" here is used to record the absolute value of differrence.
-#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
- delta = ThermalValue > pHalData->EEPROMThermalMeter?(ThermalValue - pHalData->EEPROMThermalMeter):(pHalData->EEPROMThermalMeter - ThermalValue);
-#else
- delta = (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther)?(ThermalValue - pDM_Odm->priv->pmib->dot11RFEntry.ther):(pDM_Odm->priv->pmib->dot11RFEntry.ther - ThermalValue);
-#endif
- if (delta >= TXPWR_TRACK_TABLE_SIZE)
- delta = TXPWR_TRACK_TABLE_SIZE - 1;
-
- /*4 7.1 The Final Power Index = BaseIndex + PowerIndexOffset*/
-
-#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
- if(ThermalValue > pHalData->EEPROMThermalMeter) {
-#else
- if(ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) {
-#endif
-
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) {
- pRFCalibrateInfo->DeltaPowerIndexLast[p] = pRFCalibrateInfo->DeltaPowerIndex[p]; /*recording poer index offset*/
- switch (p) {
- case ODM_RF_PATH_B:
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("deltaSwingTableIdx_TUP_B[%d] = %d\n", delta, deltaSwingTableIdx_TUP_B[delta]));
-
- pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_B[delta];
- pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_B[delta]; /*Record delta swing for mix mode power tracking*/
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
- break;
-
- case ODM_RF_PATH_C:
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("deltaSwingTableIdx_TUP_C[%d] = %d\n", delta, deltaSwingTableIdx_TUP_C[delta]));
-
- pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_C[delta];
- pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_C[delta]; /*Record delta swing for mix mode power tracking*/
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
- break;
-
- case ODM_RF_PATH_D:
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("deltaSwingTableIdx_TUP_D[%d] = %d\n", delta, deltaSwingTableIdx_TUP_D[delta]));
-
- pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_D[delta];
- pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_D[delta]; /*Record delta swing for mix mode power tracking*/
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
- break;
-
- default:
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("deltaSwingTableIdx_TUP_A[%d] = %d\n", delta, deltaSwingTableIdx_TUP_A[delta]));
-
- pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_A[delta];
- pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_A[delta]; /*Record delta swing for mix mode power tracking*/
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
- break;
- }
- }
-
- if (pDM_Odm->SupportICType & (ODM_RTL8703B | ODM_RTL8723D)) {
- /*Save XtalOffset from Xtal table*/
- pRFCalibrateInfo->XtalOffsetLast = pRFCalibrateInfo->XtalOffset; /*recording last Xtal offset*/
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("[Xtal] deltaSwingTableXtal_UP[%d] = %d\n", delta, deltaSwingTableXtal_UP[delta]));
- pRFCalibrateInfo->XtalOffset = deltaSwingTableXtal_UP[delta];
-
- if (pRFCalibrateInfo->XtalOffsetLast == pRFCalibrateInfo->XtalOffset)
- XtalOffsetEanble = 0;
- else
- XtalOffsetEanble = 1;
- }
-
- } else {
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) {
- pRFCalibrateInfo->DeltaPowerIndexLast[p] = pRFCalibrateInfo->DeltaPowerIndex[p]; /*recording poer index offset*/
-
- switch (p) {
- case ODM_RF_PATH_B:
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("deltaSwingTableIdx_TDOWN_B[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_B[delta]));
- pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_B[delta];
- pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_B[delta]; /*Record delta swing for mix mode power tracking*/
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
- break;
-
- case ODM_RF_PATH_C:
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("deltaSwingTableIdx_TDOWN_C[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_C[delta]));
- pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_C[delta];
- pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_C[delta]; /*Record delta swing for mix mode power tracking*/
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
- break;
-
- case ODM_RF_PATH_D:
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("deltaSwingTableIdx_TDOWN_D[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_D[delta]));
- pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_D[delta];
- pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_D[delta]; /*Record delta swing for mix mode power tracking*/
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
- break;
-
- default:
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("deltaSwingTableIdx_TDOWN_A[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_A[delta]));
- pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_A[delta];
- pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_A[delta]; /*Record delta swing for mix mode power tracking*/
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p]));
- break;
- }
- }
-
- if (pDM_Odm->SupportICType & (ODM_RTL8703B | ODM_RTL8723D)) {
- /*Save XtalOffset from Xtal table*/
- pRFCalibrateInfo->XtalOffsetLast = pRFCalibrateInfo->XtalOffset; /*recording last Xtal offset*/
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("[Xtal] deltaSwingTableXtal_DOWN[%d] = %d\n", delta, deltaSwingTableXtal_DOWN[delta]));
- pRFCalibrateInfo->XtalOffset = deltaSwingTableXtal_DOWN[delta];
-
- if (pRFCalibrateInfo->XtalOffsetLast == pRFCalibrateInfo->XtalOffset)
- XtalOffsetEanble = 0;
- else
- XtalOffsetEanble = 1;
- }
-
- }
-
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("\n\n=========================== [Path-%d] Calculating PowerIndexOffset===========================\n", p));
-
- if (pRFCalibrateInfo->DeltaPowerIndex[p] == pRFCalibrateInfo->DeltaPowerIndexLast[p]) /*If Thermal value changes but lookup table value still the same*/
- pRFCalibrateInfo->PowerIndexOffset[p] = 0;
- else
- pRFCalibrateInfo->PowerIndexOffset[p] = pRFCalibrateInfo->DeltaPowerIndex[p] - pRFCalibrateInfo->DeltaPowerIndexLast[p]; /*Power Index Diff between 2 times Power Tracking*/
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("[Path-%d] PowerIndexOffset(%d) = DeltaPowerIndex(%d) - DeltaPowerIndexLast(%d)\n", p, pRFCalibrateInfo->PowerIndexOffset[p], pRFCalibrateInfo->DeltaPowerIndex[p], pRFCalibrateInfo->DeltaPowerIndexLast[p]));
-
- pRFCalibrateInfo->OFDM_index[p] = pRFCalibrateInfo->BbSwingIdxOfdmBase[p] + pRFCalibrateInfo->PowerIndexOffset[p];
- pRFCalibrateInfo->CCK_index = pRFCalibrateInfo->BbSwingIdxCckBase + pRFCalibrateInfo->PowerIndexOffset[p];
-
- pRFCalibrateInfo->BbSwingIdxCck = pRFCalibrateInfo->CCK_index;
- pRFCalibrateInfo->BbSwingIdxOfdm[p] = pRFCalibrateInfo->OFDM_index[p];
-
- /*************Print BB Swing Base and Index Offset*************/
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("The 'CCK' final index(%d) = BaseIndex(%d) + PowerIndexOffset(%d)\n", pRFCalibrateInfo->BbSwingIdxCck, pRFCalibrateInfo->BbSwingIdxCckBase, pRFCalibrateInfo->PowerIndexOffset[p]));
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("The 'OFDM' final index(%d) = BaseIndex[%d](%d) + PowerIndexOffset(%d)\n", pRFCalibrateInfo->BbSwingIdxOfdm[p], p, pRFCalibrateInfo->BbSwingIdxOfdmBase[p], pRFCalibrateInfo->PowerIndexOffset[p]));
-
- /*4 7.1 Handle boundary conditions of index.*/
-
- if (pRFCalibrateInfo->OFDM_index[p] > c.SwingTableSize_OFDM-1)
- pRFCalibrateInfo->OFDM_index[p] = c.SwingTableSize_OFDM-1;
- else if (pRFCalibrateInfo->OFDM_index[p] <= OFDM_min_index)
- pRFCalibrateInfo->OFDM_index[p] = OFDM_min_index;
- }
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("\n\n========================================================================================================\n"));
-
- if (pRFCalibrateInfo->CCK_index > c.SwingTableSize_CCK-1)
- pRFCalibrateInfo->CCK_index = c.SwingTableSize_CCK-1;
- else if (pRFCalibrateInfo->CCK_index <= 0)
- pRFCalibrateInfo->CCK_index = 0;
- } else {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("The thermal meter is unchanged or TxPowerTracking OFF(%d): ThermalValue: %d , pRFCalibrateInfo->ThermalValue: %d\n",
- pRFCalibrateInfo->TxPowerTrackControl, ThermalValue, pRFCalibrateInfo->ThermalValue));
-
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
- pRFCalibrateInfo->PowerIndexOffset[p] = 0;
- }
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("TxPowerTracking: [CCK] Swing Current Index: %d, Swing Base Index: %d\n",
- pRFCalibrateInfo->CCK_index, pRFCalibrateInfo->BbSwingIdxCckBase)); /*Print Swing base & current*/
-
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("TxPowerTracking: [OFDM] Swing Current Index: %d, Swing Base Index[%d]: %d\n",
- pRFCalibrateInfo->OFDM_index[p], p, pRFCalibrateInfo->BbSwingIdxOfdmBase[p]));
- }
-
- if ((pDM_Odm->SupportICType & ODM_RTL8814A)) {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("PowerTrackingType=%d\n", PowerTrackingType));
-
- if (PowerTrackingType == 0) {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n"));
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
- (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0);
- } else if (PowerTrackingType == 1) {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(2G) TSSI(5G) MODE**********\n"));
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
- (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_2G_TSSI_5G_MODE, p, 0);
- } else if (PowerTrackingType == 2) {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(5G) TSSI(2G)MODE**********\n"));
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
- (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_5G_TSSI_2G_MODE, p, 0);
- } else if (PowerTrackingType == 3) {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking TSSI MODE**********\n"));
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
- (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, TSSI_MODE, p, 0);
- }
- pRFCalibrateInfo->ThermalValue = ThermalValue; /*Record last Power Tracking Thermal Value*/
-
- } else if ((pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_A] != 0 ||
- pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_B] != 0 ||
- pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_C] != 0 ||
- pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_D] != 0) &&
- pRFCalibrateInfo->TxPowerTrackControl && (pHalData->EEPROMThermalMeter != 0xff)) {
- //4 7.2 Configure the Swing Table to adjust Tx Power.
-
- pRFCalibrateInfo->bTxPowerChanged = TRUE; /*Always TRUE after Tx Power is adjusted by power tracking.*/
- //
- // 2012/04/23 MH According to Luke's suggestion, we can not write BB digital
- // to increase TX power. Otherwise, EVM will be bad.
- //
- // 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E.
- if (ThermalValue > pRFCalibrateInfo->ThermalValue) {
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("Temperature Increasing(%d): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
- p, pRFCalibrateInfo->PowerIndexOffset[p], delta, ThermalValue, pHalData->EEPROMThermalMeter, pRFCalibrateInfo->ThermalValue));
- }
- } else if (ThermalValue < pRFCalibrateInfo->ThermalValue) { /*Low temperature*/
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("Temperature Decreasing(%d): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
- p, pRFCalibrateInfo->PowerIndexOffset[p], delta, ThermalValue, pHalData->EEPROMThermalMeter, pRFCalibrateInfo->ThermalValue));
- }
- }
-
-#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
- if (ThermalValue > pHalData->EEPROMThermalMeter)
-#else
- if (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther)
-#endif
- {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("Temperature(%d) higher than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter));
-
- if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8821 ||
- pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8723B || pDM_Odm->SupportICType == ODM_RTL8814A ||
- pDM_Odm->SupportICType == ODM_RTL8703B || pDM_Odm->SupportICType == ODM_RTL8188F || pDM_Odm->SupportICType == ODM_RTL8822B ||
- pDM_Odm->SupportICType == ODM_RTL8723D) {
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n"));
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
- (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0);
- } else {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n"));
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
- (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, p, Indexforchannel);
- }
- }
- else
- {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("Temperature(%d) lower than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter));
-
- if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8821 ||
- pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8723B || pDM_Odm->SupportICType == ODM_RTL8814A ||
- pDM_Odm->SupportICType == ODM_RTL8703B || pDM_Odm->SupportICType == ODM_RTL8188F || pDM_Odm->SupportICType == ODM_RTL8822B ||
- pDM_Odm->SupportICType == ODM_RTL8723D) {
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n"));
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
- (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, Indexforchannel);
- } else {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n"));
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
- (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, p, Indexforchannel);
- }
-
- }
-
- pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->BbSwingIdxCck; /*Record last time Power Tracking result as base.*/
- for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
- pRFCalibrateInfo->BbSwingIdxOfdmBase[p] = pRFCalibrateInfo->BbSwingIdxOfdm[p];
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("pRFCalibrateInfo->ThermalValue = %d ThermalValue= %d\n", pRFCalibrateInfo->ThermalValue, ThermalValue));
-
- pRFCalibrateInfo->ThermalValue = ThermalValue; /*Record last Power Tracking Thermal Value*/
-
- }
-
-
- if (pDM_Odm->SupportICType == ODM_RTL8703B || pDM_Odm->SupportICType == ODM_RTL8723D) {
-
- if (XtalOffsetEanble != 0 && pRFCalibrateInfo->TxPowerTrackControl && (pHalData->EEPROMThermalMeter != 0xff)) {
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter Xtal Tracking**********\n"));
-
-#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
- if (ThermalValue > pHalData->EEPROMThermalMeter) {
-#else
- if (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) {
-#endif
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("Temperature(%d) higher than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter));
- (*c.ODM_TxXtalTrackSetXtal)(pDM_Odm);
- } else {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
- ("Temperature(%d) lower than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter));
- (*c.ODM_TxXtalTrackSetXtal)(pDM_Odm);
- }
- }
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********End Xtal Tracking**********\n"));
- }
-
-#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
-
- if (!IS_HARDWARE_TYPE_8723B(Adapter)) {
- /*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
- if (delta_IQK >= c.Threshold_IQK) {
- pRFCalibrateInfo->ThermalValue_IQK = ThermalValue;
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_IQK(%d) >= Threshold_IQK(%d)\n", delta_IQK, c.Threshold_IQK));
- if (!pRFCalibrateInfo->bIQKInProgress)
- (*c.DoIQK)(pDM_Odm, delta_IQK, ThermalValue, 8);
- }
- }
- if (pRFCalibrateInfo->DpkThermal[ODM_RF_PATH_A] != 0) {
- if (diff_DPK[ODM_RF_PATH_A] >= c.Threshold_DPK) {
- ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1);
- ODM_SetBBReg(pDM_Odm, 0xcc4, BIT14|BIT13|BIT12|BIT11|BIT10, (diff_DPK[ODM_RF_PATH_A] / c.Threshold_DPK));
- ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0);
- } else if ((diff_DPK[ODM_RF_PATH_A] <= -1 * c.Threshold_DPK)) {
- s4Byte value = 0x20 + (diff_DPK[ODM_RF_PATH_A] / c.Threshold_DPK);
-
- ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1);
- ODM_SetBBReg(pDM_Odm, 0xcc4, BIT14|BIT13|BIT12|BIT11|BIT10, value);
- ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0);
- } else {
- ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1);
- ODM_SetBBReg(pDM_Odm, 0xcc4, BIT14|BIT13|BIT12|BIT11|BIT10, 0);
- ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0);
- }
- }
- if (pRFCalibrateInfo->DpkThermal[ODM_RF_PATH_B] != 0) {
- if (diff_DPK[ODM_RF_PATH_B] >= c.Threshold_DPK) {
- ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1);
- ODM_SetBBReg(pDM_Odm, 0xec4, BIT14|BIT13|BIT12|BIT11|BIT10, (diff_DPK[ODM_RF_PATH_B] / c.Threshold_DPK));
- ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0);
- } else if ((diff_DPK[ODM_RF_PATH_B] <= -1 * c.Threshold_DPK)) {
- s4Byte value = 0x20 + (diff_DPK[ODM_RF_PATH_B] / c.Threshold_DPK);
-
- ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1);
- ODM_SetBBReg(pDM_Odm, 0xec4, BIT14|BIT13|BIT12|BIT11|BIT10, value);
- ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0);
- } else {
- ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1);
- ODM_SetBBReg(pDM_Odm, 0xec4, BIT14|BIT13|BIT12|BIT11|BIT10, 0);
- ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0);
- }
- }
-
-#endif
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("<===ODM_TXPowerTrackingCallback_ThermalMeter\n"));
-
- pRFCalibrateInfo->TXPowercount = 0;
-}
-
-
-
-//3============================================================
-//3 IQ Calibration
-//3============================================================
-
-VOID
-ODM_ResetIQKResult(
- IN PDM_ODM_T pDM_Odm
-)
-{
- return;
-}
-#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
-u1Byte ODM_GetRightChnlPlaceforIQK(u1Byte chnl)
-{
- u1Byte channel_all[ODM_TARGET_CHNL_NUM_2G_5G] =
- {1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,100,102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,132,134,136,138,140,149,151,153,155,157,159,161,163,165};
- u1Byte place = chnl;
-
-
- if(chnl > 14)
- {
- for(place = 14; placeAdapter;
-
-#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
- if (*pDM_Odm->pIsFcsModeEnable)
- return;
-#endif
-
- if (pDM_Odm->bLinked) {
-
- if ((*pDM_Odm->pChannel != pDM_Odm->preChannel) && (!*pDM_Odm->pbScanInProcess)) {
- pDM_Odm->preChannel = *pDM_Odm->pChannel;
- pDM_Odm->LinkedInterval = 0;
- }
-
- if (pDM_Odm->LinkedInterval < 3)
- pDM_Odm->LinkedInterval++;
-
- if (pDM_Odm->LinkedInterval == 2) {
- PHY_IQCalibrate(Adapter, FALSE);
- }
- } else
- pDM_Odm->LinkedInterval = 0;
-
-}
-
-void phydm_rf_init(IN PDM_ODM_T pDM_Odm)
-{
-
- odm_TXPowerTrackingInit(pDM_Odm);
-
-#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
- ODM_ClearTxPowerTrackingState(pDM_Odm);
-#endif
-
-#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-#if (RTL8814A_SUPPORT == 1)
- if (pDM_Odm->SupportICType & ODM_RTL8814A)
- PHY_IQCalibrate_8814A_Init(pDM_Odm);
-#endif
-#endif
-
-}
-
-void phydm_rf_watchdog(IN PDM_ODM_T pDM_Odm)
-{
-
-#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
- ODM_TXPowerTrackingCheck(pDM_Odm);
- if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
- odm_IQCalibrate(pDM_Odm);
-#endif
-}
diff --git a/hal/phydm/halphyrf_win.h b/hal/phydm/halphyrf_win.h
deleted file mode 100644
index 783643b..0000000
--- a/hal/phydm/halphyrf_win.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/******************************************************************************
- *
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of version 2 of the GNU General Public License as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
- *
- *
- ******************************************************************************/
-
- #ifndef __HAL_PHY_RF_H__
- #define __HAL_PHY_RF_H__
-
-#include "phydm_kfree.h"
-#if (RTL8814A_SUPPORT == 1)
-#include "rtl8814a/phydm_iqk_8814a.h"
-#endif
-
-#if (RTL8822B_SUPPORT == 1)
-#include "rtl8822b/phydm_iqk_8822b.h"
-#include "../mac/Halmac_type.h"
-#endif
-#include "phydm_powertracking_win.h"
-
-#if (RTL8821C_SUPPORT == 1)
-#include "rtl8821c/phydm_iqk_8821c.h"
-#endif
-
-typedef enum _SPUR_CAL_METHOD {
- PLL_RESET,
- AFE_PHASE_SEL
-} SPUR_CAL_METHOD;
-
-typedef enum _PWRTRACK_CONTROL_METHOD {
- BBSWING,
- TXAGC,
- MIX_MODE,
- TSSI_MODE,
- MIX_2G_TSSI_5G_MODE,
- MIX_5G_TSSI_2G_MODE
-} PWRTRACK_METHOD;
-
-typedef VOID(*FuncSetPwr)(PVOID, PWRTRACK_METHOD, u1Byte, u1Byte);
-typedef VOID(*FuncIQK)(PVOID, u1Byte, u1Byte, u1Byte);
-typedef VOID(*FuncLCK)(PVOID);
-typedef VOID(*FuncSwing)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*);
-typedef VOID(*FuncSwing8814only)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*);
-typedef VOID (*FuncSwingXtal)(PVOID, ps1Byte*, ps1Byte*);
-typedef VOID (*FuncSetXtal)(PVOID);
-typedef VOID(*FuncAllSwing)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*);
-
-typedef struct _TXPWRTRACK_CFG {
- u1Byte SwingTableSize_CCK;
- u1Byte SwingTableSize_OFDM;
- u1Byte Threshold_IQK;
- u1Byte Threshold_DPK;
- u1Byte AverageThermalNum;
- u1Byte RfPathCount;
- u4Byte ThermalRegAddr;
- FuncSetPwr ODM_TxPwrTrackSetPwr;
- FuncIQK DoIQK;
- FuncLCK PHY_LCCalibrate;
- FuncSwing GetDeltaSwingTable;
- FuncSwing8814only GetDeltaSwingTable8814only;
- FuncSwingXtal GetDeltaSwingXtalTable;
- FuncSetXtal ODM_TxXtalTrackSetXtal;
- FuncAllSwing GetDeltaAllSwingTable;
-} TXPWRTRACK_CFG, *PTXPWRTRACK_CFG;
-
-VOID
-ConfigureTxpowerTrack(
- IN PDM_ODM_T pDM_Odm,
- OUT PTXPWRTRACK_CFG pConfig
- );
-
-
-VOID
-ODM_ClearTxPowerTrackingState(
- IN PDM_ODM_T pDM_Odm
- );
-
-VOID
-ODM_TXPowerTrackingCallback_ThermalMeter(
-#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
- IN PDM_ODM_T pDM_Odm
-#else
- IN PADAPTER Adapter
-#endif
- );
-
-
-
-#define ODM_TARGET_CHNL_NUM_2G_5G 59
-
-
-VOID
-ODM_ResetIQKResult(
- IN PDM_ODM_T pDM_Odm
-);
-u1Byte
-ODM_GetRightChnlPlaceforIQK(
- IN u1Byte chnl
-);
-
-VOID odm_IQCalibrate(IN PDM_ODM_T pDM_Odm);
-VOID phydm_rf_init( IN PDM_ODM_T pDM_Odm);
-VOID phydm_rf_watchdog( IN PDM_ODM_T pDM_Odm);
-
-#endif // #ifndef __HAL_PHY_RF_H__
-
diff --git a/hal/phydm/halrf/halphyrf_ap.c b/hal/phydm/halrf/halphyrf_ap.c
new file mode 100644
index 0000000..e6b07a1
--- /dev/null
+++ b/hal/phydm/halrf/halphyrf_ap.c
@@ -0,0 +1,1305 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+#ifndef index_mapping_NUM_88E
+ #define index_mapping_NUM_88E 15
+#endif
+
+/* #if(DM_ODM_SUPPORT_TYPE & ODM_WIN) */
+
+#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _delta_thermal) \
+ do {\
+ for (_offset = 0; _offset < _size; _offset++) { \
+ \
+ if (_delta_thermal < thermal_threshold[_direction][_offset]) { \
+ \
+ if (_offset != 0)\
+ _offset--;\
+ break;\
+ } \
+ } \
+ if (_offset >= _size)\
+ _offset = _size-1;\
+ } while (0)
+
+
+void configure_txpower_track(
+ void *dm_void,
+ struct txpwrtrack_cfg *config
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+#if RTL8812A_SUPPORT
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+ /* if (IS_HARDWARE_TYPE_8812(dm->adapter)) */
+ if (dm->support_ic_type == ODM_RTL8812)
+ configure_txpower_track_8812a(config);
+ /* else */
+#endif
+#endif
+
+#if RTL8814A_SUPPORT
+ if (dm->support_ic_type == ODM_RTL8814A)
+ configure_txpower_track_8814a(config);
+#endif
+
+
+#if RTL8188E_SUPPORT
+ if (dm->support_ic_type == ODM_RTL8188E)
+ configure_txpower_track_8188e(config);
+#endif
+
+#if RTL8197F_SUPPORT
+ if (dm->support_ic_type == ODM_RTL8197F)
+ configure_txpower_track_8197f(config);
+#endif
+
+#if RTL8822B_SUPPORT
+ if (dm->support_ic_type == ODM_RTL8822B)
+ configure_txpower_track_8822b(config);
+#endif
+
+
+}
+
+#if (RTL8192E_SUPPORT == 1)
+void
+odm_txpowertracking_callback_thermal_meter_92e(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+ u8 thermal_value = 0, delta, delta_IQK, delta_LCK, channel, is_decrease, rf_mimo_mode;
+ u8 thermal_value_avg_count = 0;
+ u8 OFDM_min_index = 10; /* OFDM BB Swing should be less than +2.5dB, which is required by Arthur */
+ s8 OFDM_index[2], index ;
+ u32 thermal_value_avg = 0, reg0x18;
+ u32 i = 0, j = 0, rf;
+ s32 value32, CCK_index = 0, ele_A, ele_D, ele_C, X, Y;
+ struct rtl8192cd_priv *priv = dm->priv;
+
+ rf_mimo_mode = dm->rf_type;
+ /* PHYDM_DBG(dm,ODM_COMP_TX_PWR_TRACK,"%s:%d rf_mimo_mode:%d\n", __FUNCTION__, __LINE__, rf_mimo_mode); */
+
+#ifdef MP_TEST
+ if ((OPMODE & WIFI_MP_STATE) || *(dm->mp_mode)) {
+ channel = priv->pshare->working_channel;
+ if (priv->pshare->mp_txpwr_tracking == false)
+ return;
+ } else
+#endif
+ {
+ channel = (priv->pmib->dot11RFEntry.dot11channel);
+ }
+
+ thermal_value = (unsigned char)odm_get_rf_reg(dm, RF_PATH_A, ODM_RF_T_METER_92E, 0xfc00); /* 0x42: RF Reg[15:10] 88E */
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther);
+
+
+ switch (rf_mimo_mode) {
+ case RF_1T1R:
+ rf = 1;
+ break;
+ case RF_2T2R:
+ rf = 2;
+ break;
+ default:
+ rf = 2;
+ break;
+ }
+
+ /* Query OFDM path A default setting Bit[31:21] */
+ ele_D = phy_query_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKOFDM_D);
+ for (i = 0; i < OFDM_TABLE_SIZE_92E; i++) {
+ if (ele_D == (ofdm_swing_table_92e[i] >> 22)) {
+ OFDM_index[0] = (unsigned char)i;
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "PathA 0xC80[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[0]);
+ break;
+ }
+ }
+
+ /* Query OFDM path B default setting */
+ if (rf_mimo_mode == RF_2T2R) {
+ ele_D = phy_query_bb_reg(priv, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKOFDM_D);
+ for (i = 0; i < OFDM_TABLE_SIZE_92E; i++) {
+ if (ele_D == (ofdm_swing_table_92e[i] >> 22)) {
+ OFDM_index[1] = (unsigned char)i;
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "PathB 0xC88[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[1]);
+ break;
+ }
+ }
+ }
+
+ /* calculate average thermal meter */
+ {
+ priv->pshare->thermal_value_avg_88xx[priv->pshare->thermal_value_avg_index_88xx] = thermal_value;
+ priv->pshare->thermal_value_avg_index_88xx++;
+ if (priv->pshare->thermal_value_avg_index_88xx == AVG_THERMAL_NUM_88XX)
+ priv->pshare->thermal_value_avg_index_88xx = 0;
+
+ for (i = 0; i < AVG_THERMAL_NUM_88XX; i++) {
+ if (priv->pshare->thermal_value_avg_88xx[i]) {
+ thermal_value_avg += priv->pshare->thermal_value_avg_88xx[i];
+ thermal_value_avg_count++;
+ }
+ }
+
+ if (thermal_value_avg_count) {
+ thermal_value = (unsigned char)(thermal_value_avg / thermal_value_avg_count);
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "AVG Thermal Meter = 0x%x\n", thermal_value);
+ }
+ }
+
+ /* Initialize */
+ if (!priv->pshare->thermal_value) {
+ priv->pshare->thermal_value = priv->pmib->dot11RFEntry.ther;
+ priv->pshare->thermal_value_iqk = thermal_value;
+ priv->pshare->thermal_value_lck = thermal_value;
+ }
+
+ if (thermal_value != priv->pshare->thermal_value) {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\n******** START POWER TRACKING ********\n");
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther);
+
+ delta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther);
+ delta_IQK = RTL_ABS(thermal_value, priv->pshare->thermal_value_iqk);
+ delta_LCK = RTL_ABS(thermal_value, priv->pshare->thermal_value_lck);
+ is_decrease = ((thermal_value < priv->pmib->dot11RFEntry.ther) ? 1 : 0);
+
+#ifdef _TRACKING_TABLE_FILE
+ if (priv->pshare->rf_ft_var.pwr_track_file) {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "diff: (%s)%d ==> get index from table : %d)\n", (is_decrease ? "-" : "+"), delta, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0));
+
+ if (is_decrease) {
+ for (i = 0; i < rf; i++) {
+ OFDM_index[i] = priv->pshare->OFDM_index0[i] + get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0);
+ OFDM_index[i] = ((OFDM_index[i] > (OFDM_TABLE_SIZE_92E- 1)) ? (OFDM_TABLE_SIZE_92E - 1) : OFDM_index[i]);
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0));
+ CCK_index = priv->pshare->CCK_index0 + get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1);
+ CCK_index = ((CCK_index > (CCK_TABLE_SIZE_92E - 1)) ? (CCK_TABLE_SIZE_92E - 1) : CCK_index);
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> Decrese power ---> new CCK_INDEX:%d (%d + %d)\n", CCK_index, priv->pshare->CCK_index0, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1));
+ }
+ } else {
+ for (i = 0; i < rf; i++) {
+ OFDM_index[i] = priv->pshare->OFDM_index0[i] - get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0);
+ OFDM_index[i] = ((OFDM_index[i] < OFDM_min_index) ? OFDM_min_index : OFDM_index[i]);
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> Increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0));
+ CCK_index = priv->pshare->CCK_index0 - get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1);
+ CCK_index = ((CCK_index < 0) ? 0 : CCK_index);
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> Increse power ---> new CCK_INDEX:%d (%d - %d)\n", CCK_index, priv->pshare->CCK_index0, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1));
+ }
+ }
+ }
+#endif /* CFG_TRACKING_TABLE_FILE */
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "ofdm_swing_table_92e[(unsigned int)OFDM_index[0]] = %x\n", ofdm_swing_table_92e[(unsigned int)OFDM_index[0]]);
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "ofdm_swing_table_92e[(unsigned int)OFDM_index[1]] = %x\n", ofdm_swing_table_92e[(unsigned int)OFDM_index[1]]);
+
+ /* Adujst OFDM Ant_A according to IQK result */
+ ele_D = (ofdm_swing_table_92e[(unsigned int)OFDM_index[0]] & 0xFFC00000) >> 22;
+ X = priv->pshare->rege94;
+ Y = priv->pshare->rege9c;
+
+ if (X != 0) {
+ if ((X & 0x00000200) != 0)
+ X = X | 0xFFFFFC00;
+ ele_A = ((X * ele_D) >> 8) & 0x000003FF;
+
+ /* new element C = element D x Y */
+ if ((Y & 0x00000200) != 0)
+ Y = Y | 0xFFFFFC00;
+ ele_C = ((Y * ele_D) >> 8) & 0x000003FF;
+
+ /* wirte new elements A, C, D to regC80 and regC94, element B is always 0 */
+ value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A;
+ phy_set_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD, value32);
+
+ value32 = (ele_C & 0x000003C0) >> 6;
+ phy_set_bb_reg(priv, REG_OFDM_0_XC_TX_AFE, MASKH4BITS, value32);
+
+ value32 = ((X * ele_D) >> 7) & 0x01;
+ phy_set_bb_reg(priv, REG_OFDM_0_ECCA_THRESHOLD, BIT(24), value32);
+ } else {
+ phy_set_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD, ofdm_swing_table_92e[(unsigned int)OFDM_index[0]]);
+ phy_set_bb_reg(priv, REG_OFDM_0_XC_TX_AFE, MASKH4BITS, 0x00);
+ phy_set_bb_reg(priv, REG_OFDM_0_ECCA_THRESHOLD, BIT(24), 0x00);
+ }
+
+ set_CCK_swing_index(priv, CCK_index);
+
+ if (rf == 2) {
+ ele_D = (ofdm_swing_table_92e[(unsigned int)OFDM_index[1]] & 0xFFC00000) >> 22;
+ X = priv->pshare->regeb4;
+ Y = priv->pshare->regebc;
+
+ if (X != 0) {
+ if ((X & 0x00000200) != 0) /* consider minus */
+ X = X | 0xFFFFFC00;
+ ele_A = ((X * ele_D) >> 8) & 0x000003FF;
+
+ /* new element C = element D x Y */
+ if ((Y & 0x00000200) != 0)
+ Y = Y | 0xFFFFFC00;
+ ele_C = ((Y * ele_D) >> 8) & 0x00003FF;
+
+ /* wirte new elements A, C, D to regC88 and regC9C, element B is always 0 */
+ value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A;
+ phy_set_bb_reg(priv, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD, value32);
+
+ value32 = (ele_C & 0x000003C0) >> 6;
+ phy_set_bb_reg(priv, REG_OFDM_0_XD_TX_AFE, MASKH4BITS, value32);
+
+ value32 = ((X * ele_D) >> 7) & 0x01;
+ phy_set_bb_reg(priv, REG_OFDM_0_ECCA_THRESHOLD, BIT(28), value32);
+ } else {
+ phy_set_bb_reg(priv, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD, ofdm_swing_table_92e[(unsigned int)OFDM_index[1]]);
+ phy_set_bb_reg(priv, REG_OFDM_0_XD_TX_AFE, MASKH4BITS, 0x00);
+ phy_set_bb_reg(priv, REG_OFDM_0_ECCA_THRESHOLD, BIT(28), 0x00);
+ }
+
+ }
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "0xc80 = 0x%x\n", phy_query_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKDWORD));
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "0xc88 = 0x%x\n", phy_query_bb_reg(priv, REG_OFDM_0_XB_TX_IQ_IMBALANCE, MASKDWORD));
+
+ if ((delta_IQK > 3) && (!iqk_info->rfk_forbidden)) {
+ priv->pshare->thermal_value_iqk = thermal_value;
+#ifdef MP_TEST
+#endif if (!(*(dm->mp_mode) && (OPMODE & (WIFI_MP_CTX_BACKGROUND | WIFI_MP_CTX_PACKET))))
+
+ halrf_iqk_trigger(dm, false);
+ }
+
+ if ((delta_LCK > 8) && (!iqk_info->rfk_forbidden)) {
+ RTL_W8(0x522, 0xff);
+ reg0x18 = phy_query_rf_reg(priv, RF_PATH_A, 0x18, MASK20BITS, 1);
+ phy_set_rf_reg(priv, RF_PATH_A, 0xB4, BIT(14), 1);
+ phy_set_rf_reg(priv, RF_PATH_A, 0x18, BIT(15), 1);
+ delay_ms(1);
+ phy_set_rf_reg(priv, RF_PATH_A, 0xB4, BIT(14), 0);
+ phy_set_rf_reg(priv, RF_PATH_A, 0x18, MASK20BITS, reg0x18);
+ RTL_W8(0x522, 0x0);
+ priv->pshare->thermal_value_lck = thermal_value;
+ }
+ }
+
+ /* update thermal meter value */
+ priv->pshare->thermal_value = thermal_value;
+ for (i = 0 ; i < rf ; i++)
+ priv->pshare->OFDM_index[i] = OFDM_index[i];
+ priv->pshare->CCK_index = CCK_index;
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\n******** END:%s() ********\n", __FUNCTION__);
+}
+#endif
+
+
+
+#if (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
+void
+odm_txpowertracking_callback_thermal_meter_jaguar_series3(
+ void *dm_void
+)
+{
+#if 1
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ u8 thermal_value = 0, delta, delta_LCK, delta_IQK, channel, is_increase;
+ u8 thermal_value_avg_count = 0, p = 0, i = 0;
+ u32 thermal_value_avg = 0;
+ struct rtl8192cd_priv *priv = dm->priv;
+ struct txpwrtrack_cfg c;
+ struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+ /*4 1. The following TWO tables decide the final index of OFDM/CCK swing table.*/
+ u8 *delta_swing_table_idx_tup_a = NULL, *delta_swing_table_idx_tdown_a = NULL;
+ u8 *delta_swing_table_idx_tup_b = NULL, *delta_swing_table_idx_tdown_b = NULL;
+ u8 *delta_swing_table_idx_tup_cck_a = NULL, *delta_swing_table_idx_tdown_cck_a = NULL;
+ u8 *delta_swing_table_idx_tup_cck_b = NULL, *delta_swing_table_idx_tdown_cck_b = NULL;
+ /*for 8814 add by Yu Chen*/
+ u8 *delta_swing_table_idx_tup_c = NULL, *delta_swing_table_idx_tdown_c = NULL;
+ u8 *delta_swing_table_idx_tup_d = NULL, *delta_swing_table_idx_tdown_d = NULL;
+ u8 *delta_swing_table_idx_tup_cck_c = NULL, *delta_swing_table_idx_tdown_cck_c = NULL;
+ u8 *delta_swing_table_idx_tup_cck_d = NULL, *delta_swing_table_idx_tdown_cck_d = NULL;
+
+#ifdef MP_TEST
+ if ((OPMODE & WIFI_MP_STATE) || *(dm->mp_mode)) {
+ channel = priv->pshare->working_channel;
+ if (priv->pshare->mp_txpwr_tracking == false)
+ return;
+ } else
+#endif
+ {
+ channel = (priv->pmib->dot11RFEntry.dot11channel);
+ }
+
+ configure_txpower_track(dm, &c);
+
+ (*c.get_delta_all_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,
+ (u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b,
+ (u8 **)&delta_swing_table_idx_tup_cck_a, (u8 **)&delta_swing_table_idx_tdown_cck_a,
+ (u8 **)&delta_swing_table_idx_tup_cck_b, (u8 **)&delta_swing_table_idx_tdown_cck_b);
+
+ thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00); /*0x42: RF Reg[15:10] 88E*/
+#ifdef THER_TRIM
+ if (GET_CHIP_VER(priv) == VERSION_8197F) {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"orig thermal_value=%d, ther_trim_val=%d\n", thermal_value, priv->pshare->rf_ft_var.ther_trim_val);
+
+ thermal_value += priv->pshare->rf_ft_var.ther_trim_val;
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"after thermal trim, thermal_value=%d\n", thermal_value);
+ }
+#endif
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"Readback Thermal Meter = 0x%x(%d) EEPROMthermalmeter 0x%x(%d)\n"
+ , thermal_value, thermal_value, priv->pmib->dot11RFEntry.ther, priv->pmib->dot11RFEntry.ther);
+
+ /* Initialize */
+ if (!dm->rf_calibrate_info.thermal_value)
+ dm->rf_calibrate_info.thermal_value = priv->pmib->dot11RFEntry.ther;
+
+ if (!dm->rf_calibrate_info.thermal_value_lck)
+ dm->rf_calibrate_info.thermal_value_lck = priv->pmib->dot11RFEntry.ther;
+
+ if (!dm->rf_calibrate_info.thermal_value_iqk)
+ dm->rf_calibrate_info.thermal_value_iqk = priv->pmib->dot11RFEntry.ther;
+
+ /* calculate average thermal meter */
+ dm->rf_calibrate_info.thermal_value_avg[dm->rf_calibrate_info.thermal_value_avg_index] = thermal_value;
+ dm->rf_calibrate_info.thermal_value_avg_index++;
+
+ if (dm->rf_calibrate_info.thermal_value_avg_index == c.average_thermal_num) /*Average times = c.average_thermal_num*/
+ dm->rf_calibrate_info.thermal_value_avg_index = 0;
+
+ for (i = 0; i < c.average_thermal_num; i++) {
+ if (dm->rf_calibrate_info.thermal_value_avg[i]) {
+ thermal_value_avg += dm->rf_calibrate_info.thermal_value_avg[i];
+ thermal_value_avg_count++;
+ }
+ }
+
+ if (thermal_value_avg_count) {/*Calculate Average thermal_value after average enough times*/
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"thermal_value_avg=0x%x(%d) thermal_value_avg_count = %d\n"
+ , thermal_value_avg, thermal_value_avg, thermal_value_avg_count);
+
+ thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"AVG Thermal Meter = 0x%X(%d), EEPROMthermalmeter = 0x%X(%d)\n", thermal_value, thermal_value, priv->pmib->dot11RFEntry.ther, priv->pmib->dot11RFEntry.ther);
+ }
+
+ /*4 Calculate delta, delta_LCK, delta_IQK.*/
+ delta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther);
+ delta_LCK = RTL_ABS(thermal_value, dm->rf_calibrate_info.thermal_value_lck);
+ delta_IQK = RTL_ABS(thermal_value, dm->rf_calibrate_info.thermal_value_iqk);
+ is_increase = ((thermal_value < priv->pmib->dot11RFEntry.ther) ? 0 : 1);
+
+ if (delta > 29) { /* power track table index(thermal diff.) upper bound*/
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "delta(%d) > 29, set delta to 29\n", delta);
+ delta = 29;
+ }
+
+
+ /*4 if necessary, do LCK.*/
+ if ((delta_LCK > c.threshold_iqk) && (!iqk_info->rfk_forbidden)) {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
+ dm->rf_calibrate_info.thermal_value_lck = thermal_value;
+#if (RTL8822B_SUPPORT != 1)
+ if (!(dm->support_ic_type & ODM_RTL8822B)) {
+ if (c.phy_lc_calibrate)
+ (*c.phy_lc_calibrate)(dm);
+ }
+#endif
+ }
+
+ if ((delta_IQK > c.threshold_iqk) && (!iqk_info->rfk_forbidden)) {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
+ dm->rf_calibrate_info.thermal_value_iqk = thermal_value;
+ if (c.do_iqk)
+ (*c.do_iqk)(dm, true, 0, 0);
+ }
+
+ if (!priv->pmib->dot11RFEntry.ther) /*Don't do power tracking since no calibrated thermal value*/
+ return;
+
+ /*4 Do Power Tracking*/
+
+ if (thermal_value != dm->rf_calibrate_info.thermal_value) {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"\n\n******** START POWER TRACKING ********\n");
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"Readback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n",
+ thermal_value, dm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther);
+
+#ifdef _TRACKING_TABLE_FILE
+ if (priv->pshare->rf_ft_var.pwr_track_file) {
+ if (is_increase) { /*thermal is higher than base*/
+ for (p = RF_PATH_A; p < c.rf_path_count; p++) {
+ switch (p) {
+ case RF_PATH_B:
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tup_b[%d] = %d delta_swing_table_idx_tup_cck_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta], delta, delta_swing_table_idx_tup_cck_b[delta]);
+ cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_b[delta];
+ cali_info->absolute_cck_swing_idx[p] = delta_swing_table_idx_tup_cck_b[delta];
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_B] = %d pRF->absolute_cck_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
+ break;
+
+ case RF_PATH_C:
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tup_c[%d] = %d delta_swing_table_idx_tup_cck_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta], delta, delta_swing_table_idx_tup_cck_c[delta]);
+ cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_c[delta];
+ cali_info->absolute_cck_swing_idx[p] = delta_swing_table_idx_tup_cck_c[delta];
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_C] = %d pRF->absolute_cck_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
+ break;
+
+ case RF_PATH_D:
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tup_d[%d] = %d delta_swing_table_idx_tup_cck_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta], delta, delta_swing_table_idx_tup_cck_d[delta]);
+ cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_d[delta];
+ cali_info->absolute_cck_swing_idx[p] = delta_swing_table_idx_tup_cck_d[delta];
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_D] = %d pRF->absolute_cck_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
+ break;
+ default:
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tup_a[%d] = %d delta_swing_table_idx_tup_cck_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta], delta, delta_swing_table_idx_tup_cck_a[delta]);
+ cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_a[delta];
+ cali_info->absolute_cck_swing_idx[p] = delta_swing_table_idx_tup_cck_a[delta];
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is higher and pRF->absolute_ofdm_swing_idx[RF_PATH_A] = %d pRF->absolute_cck_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
+ break;
+ }
+ }
+ } else { /* thermal is lower than base*/
+ for (p = RF_PATH_A; p < c.rf_path_count; p++) {
+ switch (p) {
+ case RF_PATH_B:
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tdown_b[%d] = %d delta_swing_table_idx_tdown_cck_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta], delta, delta_swing_table_idx_tdown_cck_b[delta]);
+ cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta];
+ cali_info->absolute_cck_swing_idx[p] = -1 * delta_swing_table_idx_tdown_cck_b[delta];
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_B] = %d pRF->absolute_cck_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
+ break;
+
+ case RF_PATH_C:
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tdown_c[%d] = %d delta_swing_table_idx_tdown_cck_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta], delta, delta_swing_table_idx_tdown_cck_c[delta]);
+ cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_c[delta];
+ cali_info->absolute_cck_swing_idx[p] = -1 * delta_swing_table_idx_tdown_cck_c[delta];
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_C] = %d pRF->absolute_cck_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
+ break;
+
+ case RF_PATH_D:
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tdown_d[%d] = %d delta_swing_table_idx_tdown_cck_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta], delta, delta_swing_table_idx_tdown_cck_d[delta]);
+ cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_d[delta];
+ cali_info->absolute_cck_swing_idx[p] = -1 * delta_swing_table_idx_tdown_cck_d[delta];
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_D] = %d pRF->absolute_cck_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
+ break;
+
+ default:
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tdown_a[%d] = %d delta_swing_table_idx_tdown_cck_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta], delta, delta_swing_table_idx_tdown_cck_a[delta]);
+ cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta];
+ cali_info->absolute_cck_swing_idx[p] = -1 * delta_swing_table_idx_tdown_cck_a[delta];
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is lower and pRF->absolute_ofdm_swing_idx[RF_PATH_A] = %d pRF->absolute_cck_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p], cali_info->absolute_cck_swing_idx[p]);
+ break;
+ }
+ }
+ }
+
+ if (is_increase) {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> increse power --->\n");
+ if (GET_CHIP_VER(priv) == VERSION_8197F) {
+ for (p = RF_PATH_A; p < c.rf_path_count; p++)
+ (*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, 0);
+ } else if (GET_CHIP_VER(priv) == VERSION_8822B) {
+ for (p = RF_PATH_A; p < c.rf_path_count; p++)
+ (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
+ } else if (GET_CHIP_VER(priv) == VERSION_8821C) {
+ for (p = RF_PATH_A; p < c.rf_path_count; p++)
+ (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
+ }
+ } else {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> decrese power --->\n");
+ if (GET_CHIP_VER(priv) == VERSION_8197F) {
+ for (p = RF_PATH_A; p < c.rf_path_count; p++)
+ (*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, 0);
+ } else if (GET_CHIP_VER(priv) == VERSION_8822B) {
+ for (p = RF_PATH_A; p < c.rf_path_count; p++)
+ (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
+ } else if (GET_CHIP_VER(priv) == VERSION_8821C) {
+ for (p = RF_PATH_A; p < c.rf_path_count; p++)
+ (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
+ }
+ }
+ }
+#endif
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\n******** END:%s() ********\n\n", __func__);
+ /*update thermal meter value*/
+ dm->rf_calibrate_info.thermal_value = thermal_value;
+
+ }
+
+#endif
+}
+#endif
+
+/*#if (RTL8814A_SUPPORT == 1)*/
+#if (RTL8814A_SUPPORT == 1)
+
+void
+odm_txpowertracking_callback_thermal_meter_jaguar_series2(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ u8 thermal_value = 0, delta, delta_LCK, delta_IQK, channel, is_increase;
+ u8 thermal_value_avg_count = 0, p = 0, i = 0;
+ u32 thermal_value_avg = 0, reg0x18;
+ u32 bb_swing_reg[4] = {REG_A_TX_SCALE_JAGUAR, REG_B_TX_SCALE_JAGUAR, REG_C_TX_SCALE_JAGUAR2, REG_D_TX_SCALE_JAGUAR2};
+ s32 ele_D;
+ u32 bb_swing_idx;
+ struct rtl8192cd_priv *priv = dm->priv;
+ struct txpwrtrack_cfg c;
+ boolean is_tssi_enable = false;
+ struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+
+ /* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */
+ u8 *delta_swing_table_idx_tup_a = NULL, *delta_swing_table_idx_tdown_a = NULL;
+ u8 *delta_swing_table_idx_tup_b = NULL, *delta_swing_table_idx_tdown_b = NULL;
+ /* for 8814 add by Yu Chen */
+ u8 *delta_swing_table_idx_tup_c = NULL, *delta_swing_table_idx_tdown_c = NULL;
+ u8 *delta_swing_table_idx_tup_d = NULL, *delta_swing_table_idx_tdown_d = NULL;
+
+#ifdef MP_TEST
+ if ((OPMODE & WIFI_MP_STATE) || *(dm->mp_mode)) {
+ channel = priv->pshare->working_channel;
+ if (priv->pshare->mp_txpwr_tracking == false)
+ return;
+ } else
+#endif
+ {
+ channel = (priv->pmib->dot11RFEntry.dot11channel);
+ }
+
+ configure_txpower_track(dm, &c);
+ cali_info->default_ofdm_index = priv->pshare->OFDM_index0[RF_PATH_A];
+
+ (*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,
+ (u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b);
+
+ if (dm->support_ic_type & ODM_RTL8814A) /* for 8814 path C & D */
+ (*c.get_delta_swing_table8814only)(dm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c,
+ (u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d);
+
+ thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00); /* 0x42: RF Reg[15:10] 88E */
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"\nReadback Thermal Meter = 0x%x, pre thermal meter 0x%x, EEPROMthermalmeter 0x%x\n", thermal_value, dm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther);
+
+ /* Initialize */
+ if (!dm->rf_calibrate_info.thermal_value)
+ dm->rf_calibrate_info.thermal_value = priv->pmib->dot11RFEntry.ther;
+
+ if (!dm->rf_calibrate_info.thermal_value_lck)
+ dm->rf_calibrate_info.thermal_value_lck = priv->pmib->dot11RFEntry.ther;
+
+ if (!dm->rf_calibrate_info.thermal_value_iqk)
+ dm->rf_calibrate_info.thermal_value_iqk = priv->pmib->dot11RFEntry.ther;
+
+ is_tssi_enable = (boolean)odm_get_rf_reg(dm, RF_PATH_A, REG_RF_TX_GAIN_OFFSET, BIT(7)); /* check TSSI enable */
+
+ /* 4 Query OFDM BB swing default setting Bit[31:21] */
+ for (p = RF_PATH_A ; p < c.rf_path_count ; p++) {
+ ele_D = odm_get_bb_reg(dm, bb_swing_reg[p], 0xffe00000);
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"0x%x:0x%x ([31:21] = 0x%x)\n", bb_swing_reg[p], odm_get_bb_reg(dm, bb_swing_reg[p], MASKDWORD), ele_D);
+
+ for (bb_swing_idx = 0; bb_swing_idx < TXSCALE_TABLE_SIZE; bb_swing_idx++) {/* 4 */
+ if (ele_D == tx_scaling_table_jaguar[bb_swing_idx]) {
+ dm->rf_calibrate_info.OFDM_index[p] = (u8)bb_swing_idx;
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"OFDM_index[%d]=%d\n", p, dm->rf_calibrate_info.OFDM_index[p]);
+ break;
+ }
+ }
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "kfree_offset[%d]=%d\n", p, cali_info->kfree_offset[p]);
+
+ }
+
+ /* calculate average thermal meter */
+ dm->rf_calibrate_info.thermal_value_avg[dm->rf_calibrate_info.thermal_value_avg_index] = thermal_value;
+ dm->rf_calibrate_info.thermal_value_avg_index++;
+ if (dm->rf_calibrate_info.thermal_value_avg_index == c.average_thermal_num) /* Average times = c.average_thermal_num */
+ dm->rf_calibrate_info.thermal_value_avg_index = 0;
+
+ for (i = 0; i < c.average_thermal_num; i++) {
+ if (dm->rf_calibrate_info.thermal_value_avg[i]) {
+ thermal_value_avg += dm->rf_calibrate_info.thermal_value_avg[i];
+ thermal_value_avg_count++;
+ }
+ }
+
+ if (thermal_value_avg_count) { /* Calculate Average thermal_value after average enough times */
+ thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"AVG Thermal Meter = 0x%X, EEPROMthermalmeter = 0x%X\n", thermal_value, priv->pmib->dot11RFEntry.ther);
+ }
+
+ /* 4 Calculate delta, delta_LCK, delta_IQK. */
+ delta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther);
+ delta_LCK = RTL_ABS(thermal_value, dm->rf_calibrate_info.thermal_value_lck);
+ delta_IQK = RTL_ABS(thermal_value, dm->rf_calibrate_info.thermal_value_iqk);
+ is_increase = ((thermal_value < priv->pmib->dot11RFEntry.ther) ? 0 : 1);
+
+ /* 4 if necessary, do LCK. */
+ if (!(dm->support_ic_type & ODM_RTL8821)) {
+ if ((delta_LCK > c.threshold_iqk) && (!iqk_info->rfk_forbidden)) {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
+ dm->rf_calibrate_info.thermal_value_lck = thermal_value;
+
+ /*Use RTLCK, so close power tracking driver LCK*/
+#if (RTL8814A_SUPPORT != 1)
+ if (!(dm->support_ic_type & ODM_RTL8814A)) {
+ if (c.phy_lc_calibrate)
+ (*c.phy_lc_calibrate)(dm);
+ }
+#endif
+ }
+ }
+
+ if ((delta_IQK > c.threshold_iqk) && (!iqk_info->rfk_forbidden)) {
+ panic_printk("%s(%d)\n", __FUNCTION__, __LINE__);
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
+ dm->rf_calibrate_info.thermal_value_iqk = thermal_value;
+ if (c.do_iqk)
+ (*c.do_iqk)(dm, true, 0, 0);
+ }
+
+ if (!priv->pmib->dot11RFEntry.ther) /*Don't do power tracking since no calibrated thermal value*/
+ return;
+
+ /* 4 Do Power Tracking */
+
+ if (is_tssi_enable == true) {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter PURE TSSI MODE**********\n");
+ for (p = RF_PATH_A; p < c.rf_path_count; p++)
+ (*c.odm_tx_pwr_track_set_pwr)(dm, TSSI_MODE, p, 0);
+ } else if (thermal_value != dm->rf_calibrate_info.thermal_value) {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"\n******** START POWER TRACKING ********\n");
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, dm->rf_calibrate_info.thermal_value, priv->pmib->dot11RFEntry.ther);
+
+#ifdef _TRACKING_TABLE_FILE
+ if (priv->pshare->rf_ft_var.pwr_track_file) {
+ if (is_increase) { /* thermal is higher than base */
+ for (p = RF_PATH_A; p < c.rf_path_count; p++) {
+ switch (p) {
+ case RF_PATH_B:
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta]);
+ cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_b[delta]; /* Record delta swing for mix mode power tracking */
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+ break;
+
+ case RF_PATH_C:
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tup_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta]);
+ cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_c[delta]; /* Record delta swing for mix mode power tracking */
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+ break;
+
+ case RF_PATH_D:
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tup_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta]);
+ cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_d[delta]; /* Record delta swing for mix mode power tracking */
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+ break;
+
+ default:
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta]);
+ cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_a[delta]; /* Record delta swing for mix mode power tracking */
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is higher and dm->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+ break;
+ }
+ }
+ } else { /* thermal is lower than base */
+ for (p = RF_PATH_A; p < c.rf_path_count; p++) {
+ switch (p) {
+ case RF_PATH_B:
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta]);
+ cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta]; /* Record delta swing for mix mode power tracking */
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+ break;
+
+ case RF_PATH_C:
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tdown_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta]);
+ cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_c[delta]; /* Record delta swing for mix mode power tracking */
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+ break;
+
+ case RF_PATH_D:
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tdown_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta]);
+ cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_d[delta]; /* Record delta swing for mix mode power tracking */
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+ break;
+
+ default:
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta]);
+ cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta]; /* Record delta swing for mix mode power tracking */
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"******Temp is lower and dm->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+ break;
+ }
+ }
+ }
+
+ if (is_increase) {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> increse power --->\n");
+ for (p = RF_PATH_A; p < c.rf_path_count; p++)
+ (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
+ } else {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> decrese power --->\n");
+ for (p = RF_PATH_A; p < c.rf_path_count; p++)
+ (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
+ }
+ }
+#endif
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\n******** END:%s() ********\n", __FUNCTION__);
+ /* update thermal meter value */
+ dm->rf_calibrate_info.thermal_value = thermal_value;
+
+ }
+}
+#endif
+
+#if (RTL8812A_SUPPORT == 1 || RTL8881A_SUPPORT == 1)
+void
+odm_txpowertracking_callback_thermal_meter_jaguar_series(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ unsigned char thermal_value = 0, delta, delta_LCK, channel, is_decrease;
+ unsigned char thermal_value_avg_count = 0;
+ unsigned int thermal_value_avg = 0, reg0x18;
+ unsigned int bb_swing_reg[4] = {0xc1c, 0xe1c, 0x181c, 0x1a1c};
+ int ele_D, value32;
+ char OFDM_index[2], index;
+ unsigned int i = 0, j = 0, rf_path, max_rf_path = 2, rf;
+ struct rtl8192cd_priv *priv = dm->priv;
+ unsigned char OFDM_min_index = 7; /* OFDM BB Swing should be less than +2.5dB, which is required by Arthur and Mimic */
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+
+
+#ifdef MP_TEST
+ if ((OPMODE & WIFI_MP_STATE) || *(dm->mp_mode)) {
+ channel = priv->pshare->working_channel;
+ if (priv->pshare->mp_txpwr_tracking == false)
+ return;
+ } else
+#endif
+ {
+ channel = (priv->pmib->dot11RFEntry.dot11channel);
+ }
+
+#if RTL8881A_SUPPORT
+ if (dm->support_ic_type == ODM_RTL8881A) {
+ max_rf_path = 1;
+ if ((get_bonding_type_8881A() == BOND_8881AM || get_bonding_type_8881A() == BOND_8881AN)
+ && priv->pshare->rf_ft_var.use_intpa8881A && (*dm->band_type == ODM_BAND_2_4G))
+ OFDM_min_index = 6; /* intPA - upper bond set to +3 dB (base: -2 dB)ot11RFEntry.phy_band_select == PHY_BAND_2G)) */
+ else
+ OFDM_min_index = 10; /* OFDM BB Swing should be less than +1dB, which is required by Arthur and Mimic */
+ }
+#endif
+
+
+ thermal_value = (unsigned char)phy_query_rf_reg(priv, RF_PATH_A, 0x42, 0xfc00, 1); /* 0x42: RF Reg[15:10] 88E */
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther);
+
+
+ /* 4 Query OFDM BB swing default setting Bit[31:21] */
+ for (rf_path = 0 ; rf_path < max_rf_path ; rf_path++) {
+ ele_D = phy_query_bb_reg(priv, bb_swing_reg[rf_path], 0xffe00000);
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "0x%x:0x%x ([31:21] = 0x%x)\n", bb_swing_reg[rf_path], phy_query_bb_reg(priv, bb_swing_reg[rf_path], MASKDWORD), ele_D);
+ for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {/* 4 */
+ if (ele_D == ofdm_swing_table_8812[i]) {
+ OFDM_index[rf_path] = (unsigned char)i;
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "OFDM_index[%d]=%d\n", rf_path, OFDM_index[rf_path]);
+ break;
+ }
+ }
+ }
+#if 0
+ /* Query OFDM path A default setting Bit[31:21] */
+ ele_D = phy_query_bb_reg(priv, 0xc1c, 0xffe00000);
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "0xc1c:0x%x ([31:21] = 0x%x)\n", phy_query_bb_reg(priv, 0xc1c, MASKDWORD), ele_D);
+ for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {/* 4 */
+ if (ele_D == ofdm_swing_table_8812[i]) {
+ OFDM_index[0] = (unsigned char)i;
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "OFDM_index[0]=%d\n", OFDM_index[0]);
+ break;
+ }
+ }
+ /* Query OFDM path B default setting */
+ if (rf == 2) {
+ ele_D = phy_query_bb_reg(priv, 0xe1c, 0xffe00000);
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "0xe1c:0x%x ([32:21] = 0x%x)\n", phy_query_bb_reg(priv, 0xe1c, MASKDWORD), ele_D);
+ for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {
+ if (ele_D == ofdm_swing_table_8812[i]) {
+ OFDM_index[1] = (unsigned char)i;
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "OFDM_index[1]=%d\n", OFDM_index[1]);
+ break;
+ }
+ }
+ }
+#endif
+ /* Initialize */
+ if (!priv->pshare->thermal_value) {
+ priv->pshare->thermal_value = priv->pmib->dot11RFEntry.ther;
+ priv->pshare->thermal_value_lck = thermal_value;
+ }
+
+ /* calculate average thermal meter */
+ {
+ priv->pshare->thermal_value_avg_8812[priv->pshare->thermal_value_avg_index_8812] = thermal_value;
+ priv->pshare->thermal_value_avg_index_8812++;
+ if (priv->pshare->thermal_value_avg_index_8812 == AVG_THERMAL_NUM_8812)
+ priv->pshare->thermal_value_avg_index_8812 = 0;
+
+ for (i = 0; i < AVG_THERMAL_NUM_8812; i++) {
+ if (priv->pshare->thermal_value_avg_8812[i]) {
+ thermal_value_avg += priv->pshare->thermal_value_avg_8812[i];
+ thermal_value_avg_count++;
+ }
+ }
+
+ if (thermal_value_avg_count) {
+ thermal_value = (unsigned char)(thermal_value_avg / thermal_value_avg_count);
+ /* printk("AVG Thermal Meter = 0x%x\n", thermal_value); */
+ }
+ }
+
+
+ /* 4 If necessary, do power tracking */
+
+ if (!priv->pmib->dot11RFEntry.ther) /*Don't do power tracking since no calibrated thermal value*/
+ return;
+
+ if (thermal_value != priv->pshare->thermal_value) {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\n******** START POWER TRACKING ********\n");
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", thermal_value, priv->pshare->thermal_value, priv->pmib->dot11RFEntry.ther);
+ delta = RTL_ABS(thermal_value, priv->pmib->dot11RFEntry.ther);
+ delta_LCK = RTL_ABS(thermal_value, priv->pshare->thermal_value_lck);
+ is_decrease = ((thermal_value < priv->pmib->dot11RFEntry.ther) ? 1 : 0);
+ /* if (*dm->band_type == ODM_BAND_5G) */
+ {
+#ifdef _TRACKING_TABLE_FILE
+ if (priv->pshare->rf_ft_var.pwr_track_file) {
+ for (rf_path = 0; rf_path < max_rf_path; rf_path++) {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "diff: (%s)%d ==> get index from table : %d)\n", (is_decrease ? "-" : "+"), delta, get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0));
+ if (is_decrease) {
+ OFDM_index[rf_path] = priv->pshare->OFDM_index0[rf_path] + get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0);
+ OFDM_index[rf_path] = ((OFDM_index[rf_path] > (OFDM_TABLE_SIZE_8812 - 1)) ? (OFDM_TABLE_SIZE_8812 - 1) : OFDM_index[rf_path]);
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[rf_path], priv->pshare->OFDM_index0[rf_path], get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0));
+#if 0/* RTL8881A_SUPPORT */
+ if (dm->support_ic_type == ODM_RTL8881A) {
+ if (priv->pshare->rf_ft_var.pwrtrk_tx_agc_enable) {
+ if (priv->pshare->add_tx_agc) { /* tx_agc has been added */
+ add_tx_power88xx_ac(priv, 0);
+ priv->pshare->add_tx_agc = 0;
+ priv->pshare->add_tx_agc_index = 0;
+ }
+ }
+ }
+#endif
+ } else {
+
+ OFDM_index[rf_path] = priv->pshare->OFDM_index0[rf_path] - get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0);
+#if 0/* RTL8881A_SUPPORT */
+ if (dm->support_ic_type == ODM_RTL8881A) {
+ if (priv->pshare->rf_ft_var.pwrtrk_tx_agc_enable) {
+ if (OFDM_index[i] < OFDM_min_index) {
+ priv->pshare->add_tx_agc_index = (OFDM_min_index - OFDM_index[i]) / 2; /* Calculate Remnant tx_agc value, 2 index for 1 tx_agc */
+ add_tx_power88xx_ac(priv, priv->pshare->add_tx_agc_index);
+ priv->pshare->add_tx_agc = 1; /* add_tx_agc Flag = 1 */
+ OFDM_index[i] = OFDM_min_index;
+ } else {
+ if (priv->pshare->add_tx_agc) { /* tx_agc been added */
+ priv->pshare->add_tx_agc = 0;
+ priv->pshare->add_tx_agc_index = 0;
+ add_tx_power88xx_ac(priv, 0); /* minus the added TPI */
+ }
+ }
+ }
+ }
+#else
+ OFDM_index[rf_path] = ((OFDM_index[rf_path] < OFDM_min_index) ? OFDM_min_index : OFDM_index[rf_path]);
+#endif
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, ">>> increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[rf_path], priv->pshare->OFDM_index0[rf_path], get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0));
+ }
+ }
+ }
+#endif
+ /* 4 Set new BB swing index */
+ for (rf_path = 0; rf_path < max_rf_path; rf_path++) {
+ phy_set_bb_reg(priv, bb_swing_reg[rf_path], 0xffe00000, ofdm_swing_table_8812[(unsigned int)OFDM_index[rf_path]]);
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "Readback 0x%x[31:21] = 0x%x, OFDM_index:%d\n", bb_swing_reg[rf_path], phy_query_bb_reg(priv, bb_swing_reg[rf_path], 0xffe00000), OFDM_index[rf_path]);
+ }
+
+ }
+ if ((delta_LCK > 8) && (!iqk_info->rfk_forbidden)) {
+ RTL_W8(0x522, 0xff);
+ reg0x18 = phy_query_rf_reg(priv, RF_PATH_A, 0x18, MASK20BITS, 1);
+ phy_set_rf_reg(priv, RF_PATH_A, 0xB4, BIT(14), 1);
+ phy_set_rf_reg(priv, RF_PATH_A, 0x18, BIT(15), 1);
+ delay_ms(200); /* frequency deviation */
+ phy_set_rf_reg(priv, RF_PATH_A, 0xB4, BIT(14), 0);
+ phy_set_rf_reg(priv, RF_PATH_A, 0x18, MASK20BITS, reg0x18);
+#ifdef CONFIG_RTL_8812_SUPPORT
+ if (GET_CHIP_VER(priv) == VERSION_8812E)
+ update_bbrf_val8812(priv, priv->pmib->dot11RFEntry.dot11channel);
+#endif
+ RTL_W8(0x522, 0x0);
+ priv->pshare->thermal_value_lck = thermal_value;
+ }
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "\n******** END:%s() ********\n", __FUNCTION__);
+
+ /* update thermal meter value */
+ priv->pshare->thermal_value = thermal_value;
+ for (rf_path = 0; rf_path < max_rf_path; rf_path++)
+ priv->pshare->OFDM_index[rf_path] = OFDM_index[rf_path];
+ }
+}
+
+#endif
+
+
+void
+odm_txpowertracking_callback_thermal_meter(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+
+#if (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
+ if (dm->support_ic_type == ODM_RTL8197F || dm->support_ic_type == ODM_RTL8822B
+ || dm->support_ic_type == ODM_RTL8821C) {
+ odm_txpowertracking_callback_thermal_meter_jaguar_series3(dm);
+ return;
+ }
+#endif
+#if (RTL8814A_SUPPORT == 1) /*use this function to do power tracking after 8814 by YuChen*/
+ if (dm->support_ic_type & ODM_RTL8814A) {
+ odm_txpowertracking_callback_thermal_meter_jaguar_series2(dm);
+ return;
+ }
+#endif
+#if (RTL8881A_SUPPORT || RTL8812A_SUPPORT == 1)
+ if (dm->support_ic_type & ODM_RTL8812 || dm->support_ic_type & ODM_RTL8881A) {
+ odm_txpowertracking_callback_thermal_meter_jaguar_series(dm);
+ return;
+ }
+#endif
+
+#if (RTL8192E_SUPPORT == 1)
+ if (dm->support_ic_type == ODM_RTL8192E) {
+ odm_txpowertracking_callback_thermal_meter_92e(dm);
+ return;
+ }
+#endif
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+ /* PMGNT_INFO mgnt_info = &adapter->mgnt_info; */
+#endif
+
+
+ u8 thermal_value = 0, delta, delta_LCK, delta_IQK, offset;
+ u8 thermal_value_avg_count = 0;
+ u32 thermal_value_avg = 0;
+ /* s32 ele_A=0, ele_D, TempCCk, X, value32;
+ * s32 Y, ele_C=0;
+ * s8 OFDM_index[2], CCK_index=0, OFDM_index_old[2]={0,0}, CCK_index_old=0, index;
+ * s8 deltaPowerIndex = 0; */
+ u32 i = 0;/* , j = 0; */
+ boolean is2T = false;
+ /* bool bInteralPA = false; */
+
+ u8 OFDM_max_index = 34, rf = (is2T) ? 2 : 1; /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */
+ u8 indexforchannel = 0;/*get_right_chnl_place_for_iqk(hal_data->current_channel)*/
+ enum _POWER_DEC_INC { POWER_DEC, POWER_INC };
+
+ struct txpwrtrack_cfg c;
+
+
+ /* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */
+ s8 delta_swing_table_idx[2][index_mapping_NUM_88E] = {
+ /* {{Power decreasing(lower temperature)}, {Power increasing(higher temperature)}} */
+ {0, 0, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 10, 10, 11}, {0, 0, 1, 2, 3, 4, 4, 4, 4, 5, 7, 8, 9, 9, 10}
+ };
+ u8 thermal_threshold[2][index_mapping_NUM_88E] = {
+ /* {{Power decreasing(lower temperature)}, {Power increasing(higher temperature)}} */
+ {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 27}, {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 25, 25, 25}
+ };
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ struct rtl8192cd_priv *priv = dm->priv;
+#endif
+
+ /* 4 2. Initilization ( 7 steps in total ) */
+
+ configure_txpower_track(dm, &c);
+
+ dm->rf_calibrate_info.txpowertracking_callback_cnt++; /* cosa add for debug */
+ dm->rf_calibrate_info.is_txpowertracking_init = true;
+
+#if (MP_DRIVER == 1)
+ dm->rf_calibrate_info.txpowertrack_control = hal_data->txpowertrack_control; /* We should keep updating the control variable according to HalData.
+ * rf_calibrate_info.rega24 will be initialized when ODM HW configuring, but MP configures with para files. */
+ dm->rf_calibrate_info.rega24 = 0x090e1317;
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && defined(MP_TEST)
+ if ((OPMODE & WIFI_MP_STATE) || *(dm->mp_mode)) {
+ if (dm->priv->pshare->mp_txpwr_tracking == false)
+ return;
+ }
+#endif
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "===>odm_txpowertracking_callback_thermal_meter_8188e, dm->bb_swing_idx_cck_base: %d, dm->bb_swing_idx_ofdm_base: %d\n", cali_info->bb_swing_idx_cck_base, cali_info->bb_swing_idx_ofdm_base);
+ /*
+ if (!dm->rf_calibrate_info.tm_trigger) {
+ odm_set_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, BIT(17) | BIT(16), 0x3);
+ dm->rf_calibrate_info.tm_trigger = 1;
+ return;
+ }
+ */
+ thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00); /* 0x42: RF Reg[15:10] 88E */
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ if (!thermal_value || !dm->rf_calibrate_info.txpowertrack_control)
+#else
+ if (!dm->rf_calibrate_info.txpowertrack_control)
+#endif
+ return;
+
+ /* 4 3. Initialize ThermalValues of rf_calibrate_info */
+
+ if (!dm->rf_calibrate_info.thermal_value) {
+ dm->rf_calibrate_info.thermal_value_lck = thermal_value;
+ dm->rf_calibrate_info.thermal_value_iqk = thermal_value;
+ }
+
+ if (dm->rf_calibrate_info.is_reloadtxpowerindex)
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "reload ofdm index for band switch\n");
+
+ /* 4 4. Calculate average thermal meter */
+
+ dm->rf_calibrate_info.thermal_value_avg[dm->rf_calibrate_info.thermal_value_avg_index] = thermal_value;
+ dm->rf_calibrate_info.thermal_value_avg_index++;
+ if (dm->rf_calibrate_info.thermal_value_avg_index == c.average_thermal_num)
+ dm->rf_calibrate_info.thermal_value_avg_index = 0;
+
+ for (i = 0; i < c.average_thermal_num; i++) {
+ if (dm->rf_calibrate_info.thermal_value_avg[i]) {
+ thermal_value_avg += dm->rf_calibrate_info.thermal_value_avg[i];
+ thermal_value_avg_count++;
+ }
+ }
+
+ if (thermal_value_avg_count) {
+ /* Give the new thermo value a weighting */
+ thermal_value_avg += (thermal_value * 4);
+
+ thermal_value = (u8)(thermal_value_avg / (thermal_value_avg_count + 4));
+ cali_info->thermal_value_delta = thermal_value - priv->pmib->dot11RFEntry.ther;
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "AVG Thermal Meter = 0x%x\n", thermal_value);
+ }
+
+ /* 4 5. Calculate delta, delta_LCK, delta_IQK. */
+
+ delta = (thermal_value > dm->rf_calibrate_info.thermal_value) ? (thermal_value - dm->rf_calibrate_info.thermal_value) : (dm->rf_calibrate_info.thermal_value - thermal_value);
+ delta_LCK = (thermal_value > dm->rf_calibrate_info.thermal_value_lck) ? (thermal_value - dm->rf_calibrate_info.thermal_value_lck) : (dm->rf_calibrate_info.thermal_value_lck - thermal_value);
+ delta_IQK = (thermal_value > dm->rf_calibrate_info.thermal_value_iqk) ? (thermal_value - dm->rf_calibrate_info.thermal_value_iqk) : (dm->rf_calibrate_info.thermal_value_iqk - thermal_value);
+
+ /* 4 6. If necessary, do LCK. */
+ if (!(dm->support_ic_type & ODM_RTL8821)) {
+ /*if((delta_LCK > hal_data->delta_lck) && (hal_data->delta_lck != 0))*/
+ if ((delta_LCK >= c.threshold_iqk) && (!iqk_info->rfk_forbidden)) {
+ /*Delta temperature is equal to or larger than 20 centigrade.*/
+ dm->rf_calibrate_info.thermal_value_lck = thermal_value;
+ (*c.phy_lc_calibrate)(dm);
+ }
+ }
+
+ /* 3 7. If necessary, move the index of swing table to adjust Tx power. */
+
+ if (delta > 0 && dm->rf_calibrate_info.txpowertrack_control) {
+
+ delta = (thermal_value > dm->priv->pmib->dot11RFEntry.ther) ? (thermal_value - dm->priv->pmib->dot11RFEntry.ther) : (dm->priv->pmib->dot11RFEntry.ther - thermal_value);
+
+ /* 4 7.1 The Final Power index = BaseIndex + power_index_offset */
+
+ if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) {
+ CALCULATE_SWINGTALBE_OFFSET(offset, POWER_INC, index_mapping_NUM_88E, delta);
+ dm->rf_calibrate_info.delta_power_index_last = dm->rf_calibrate_info.delta_power_index;
+ dm->rf_calibrate_info.delta_power_index = delta_swing_table_idx[POWER_INC][offset];
+
+ } else {
+
+ CALCULATE_SWINGTALBE_OFFSET(offset, POWER_DEC, index_mapping_NUM_88E, delta);
+ dm->rf_calibrate_info.delta_power_index_last = dm->rf_calibrate_info.delta_power_index;
+ dm->rf_calibrate_info.delta_power_index = (-1) * delta_swing_table_idx[POWER_DEC][offset];
+ }
+
+ if (dm->rf_calibrate_info.delta_power_index == dm->rf_calibrate_info.delta_power_index_last)
+ dm->rf_calibrate_info.power_index_offset = 0;
+ else
+ dm->rf_calibrate_info.power_index_offset = dm->rf_calibrate_info.delta_power_index - dm->rf_calibrate_info.delta_power_index_last;
+
+ for (i = 0; i < rf; i++)
+ dm->rf_calibrate_info.OFDM_index[i] = cali_info->bb_swing_idx_ofdm_base + dm->rf_calibrate_info.power_index_offset;
+ dm->rf_calibrate_info.CCK_index = cali_info->bb_swing_idx_cck_base + dm->rf_calibrate_info.power_index_offset;
+
+ cali_info->bb_swing_idx_cck = dm->rf_calibrate_info.CCK_index;
+ cali_info->bb_swing_idx_ofdm[RF_PATH_A] = dm->rf_calibrate_info.OFDM_index[RF_PATH_A];
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_cck, cali_info->bb_swing_idx_cck_base, dm->rf_calibrate_info.power_index_offset);
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "The 'OFDM' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_ofdm[RF_PATH_A], cali_info->bb_swing_idx_ofdm_base, dm->rf_calibrate_info.power_index_offset);
+
+ /* 4 7.1 Handle boundary conditions of index. */
+
+
+ for (i = 0; i < rf; i++) {
+ if (dm->rf_calibrate_info.OFDM_index[i] > OFDM_max_index)
+ dm->rf_calibrate_info.OFDM_index[i] = OFDM_max_index;
+ else if (dm->rf_calibrate_info.OFDM_index[i] < 0)
+ dm->rf_calibrate_info.OFDM_index[i] = 0;
+ }
+
+ if (dm->rf_calibrate_info.CCK_index > c.swing_table_size_cck - 1)
+ dm->rf_calibrate_info.CCK_index = c.swing_table_size_cck - 1;
+ else if (dm->rf_calibrate_info.CCK_index < 0)
+ dm->rf_calibrate_info.CCK_index = 0;
+ } else {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"The thermal meter is unchanged or TxPowerTracking OFF: thermal_value: %d, dm->rf_calibrate_info.thermal_value: %d)\n", thermal_value, dm->rf_calibrate_info.thermal_value);
+ dm->rf_calibrate_info.power_index_offset = 0;
+ }
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n", dm->rf_calibrate_info.CCK_index, cali_info->bb_swing_idx_cck_base);
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index: %d\n", dm->rf_calibrate_info.OFDM_index[RF_PATH_A], cali_info->bb_swing_idx_ofdm_base);
+
+ if (dm->rf_calibrate_info.power_index_offset != 0 && dm->rf_calibrate_info.txpowertrack_control) {
+ /* 4 7.2 Configure the Swing Table to adjust Tx Power. */
+
+ dm->rf_calibrate_info.is_tx_power_changed = true; /* Always true after Tx Power is adjusted by power tracking. */
+ /* */
+ /* 2012/04/23 MH According to Luke's suggestion, we can not write BB digital */
+ /* to increase TX power. Otherwise, EVM will be bad. */
+ /* */
+ /* 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. */
+ if (thermal_value > dm->rf_calibrate_info.thermal_value) {
+ /* PHYDM_DBG(dm,ODM_COMP_TX_PWR_TRACK, */
+ /* "Temperature Increasing: delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", */
+ /* dm->rf_calibrate_info.power_index_offset, delta, thermal_value, hal_data->eeprom_thermal_meter, dm->rf_calibrate_info.thermal_value); */
+ } else if (thermal_value < dm->rf_calibrate_info.thermal_value) { /* Low temperature */
+ /* PHYDM_DBG(dm,ODM_COMP_TX_PWR_TRACK, */
+ /* "Temperature Decreasing: delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", */
+ /* dm->rf_calibrate_info.power_index_offset, delta, thermal_value, hal_data->eeprom_thermal_meter, dm->rf_calibrate_info.thermal_value); */
+ }
+ if (thermal_value > dm->priv->pmib->dot11RFEntry.ther)
+ {
+ /* PHYDM_DBG(dm,ODM_COMP_TX_PWR_TRACK,"Temperature(%d) hugher than PG value(%d), increases the power by tx_agc\n", thermal_value, hal_data->eeprom_thermal_meter); */
+ (*c.odm_tx_pwr_track_set_pwr)(dm, TXAGC, 0, 0);
+ } else {
+ /* PHYDM_DBG(dm,ODM_COMP_TX_PWR_TRACK,"Temperature(%d) lower than PG value(%d), increases the power by tx_agc\n", thermal_value, hal_data->eeprom_thermal_meter); */
+ (*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, RF_PATH_A, indexforchannel);
+ if (is2T)
+ (*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, RF_PATH_B, indexforchannel);
+ }
+
+ cali_info->bb_swing_idx_cck_base = cali_info->bb_swing_idx_cck;
+ cali_info->bb_swing_idx_ofdm_base = cali_info->bb_swing_idx_ofdm[RF_PATH_A];
+ dm->rf_calibrate_info.thermal_value = thermal_value;
+
+ }
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "<===dm_TXPowerTrackingCallback_ThermalMeter_8188E\n");
+
+ dm->rf_calibrate_info.tx_powercount = 0;
+}
+
+/* 3============================================================
+ * 3 IQ Calibration
+ * 3============================================================ */
+
+void
+odm_reset_iqk_result(
+ void *dm_void
+)
+{
+ return;
+}
+#if 1/* !(DM_ODM_SUPPORT_TYPE & ODM_AP) */
+u8 odm_get_right_chnl_place_for_iqk(u8 chnl)
+{
+ u8 channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = {
+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, 161, 163, 165
+ };
+ u8 place = chnl;
+
+
+ if (chnl > 14) {
+ for (place = 14; place < sizeof(channel_all); place++) {
+ if (channel_all[place] == chnl)
+ return place - 13;
+ }
+ }
+ return 0;
+
+}
+#endif
+
+void
+odm_iq_calibrate(
+ struct dm_struct *dm
+)
+{
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+
+ if ((dm->is_linked) && (!iqk_info->rfk_forbidden)) {
+ if ((*dm->channel != dm->pre_channel) && (!*dm->is_scan_in_process)) {
+ dm->pre_channel = *dm->channel;
+ dm->linked_interval = 0;
+ }
+
+ if (dm->linked_interval < 3)
+ dm->linked_interval++;
+
+ if (dm->linked_interval == 2)
+ halrf_iqk_trigger(dm, false);
+ } else
+ dm->linked_interval = 0;
+
+}
+
+void phydm_rf_init(void *dm_void)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ odm_txpowertracking_init(dm);
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+#if (RTL8814A_SUPPORT == 1)
+ if (dm->support_ic_type & ODM_RTL8814A)
+ phy_iq_calibrate_8814a_init(dm);
+#endif
+#endif
+
+}
+
+void phydm_rf_watchdog(void *dm_void)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+ odm_txpowertracking_check(dm);
+ if (dm->support_ic_type & ODM_IC_11AC_SERIES)
+ odm_iq_calibrate(dm);
+#endif
+}
diff --git a/hal/phydm/halrf/halphyrf_ap.h b/hal/phydm/halrf/halphyrf_ap.h
new file mode 100644
index 0000000..6c6d629
--- /dev/null
+++ b/hal/phydm/halrf/halphyrf_ap.h
@@ -0,0 +1,122 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#ifndef __HAL_PHY_RF_H__
+#define __HAL_PHY_RF_H__
+
+#include "halrf/halrf_powertracking_ap.h"
+#include "halrf/halrf_kfree.h"
+
+#if (RTL8814A_SUPPORT == 1)
+ #include "halrf/rtl8814a/halrf_iqk_8814a.h"
+#endif
+
+#if (RTL8822B_SUPPORT == 1)
+ #include "halrf/rtl8822b/halrf_iqk_8822b.h"
+#endif
+
+#if (RTL8821C_SUPPORT == 1)
+ #include "halrf/rtl8821c/halrf_iqk_8821c.h"
+#endif
+
+enum pwrtrack_method {
+ BBSWING,
+ TXAGC,
+ MIX_MODE,
+ TSSI_MODE
+};
+
+typedef void (*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
+typedef void(*func_iqk)(void *, u8, u8, u8);
+typedef void (*func_lck)(void *);
+/* refine by YuChen for 8814A */
+typedef void (*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
+typedef void (*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
+typedef void (*func_all_swing)(void *, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **);
+
+
+struct txpwrtrack_cfg {
+ u8 swing_table_size_cck;
+ u8 swing_table_size_ofdm;
+ u8 threshold_iqk;
+ u8 threshold_dpk;
+ u8 average_thermal_num;
+ u8 rf_path_count;
+ u32 thermal_reg_addr;
+ func_set_pwr odm_tx_pwr_track_set_pwr;
+ func_iqk do_iqk;
+ func_lck phy_lc_calibrate;
+ func_swing get_delta_swing_table;
+ func_swing8814only get_delta_swing_table8814only;
+ func_all_swing get_delta_all_swing_table;
+};
+
+void
+configure_txpower_track(
+ void *dm_void,
+ struct txpwrtrack_cfg *config
+);
+
+
+void
+odm_txpowertracking_callback_thermal_meter(
+ void *dm_void
+);
+
+#if (RTL8192E_SUPPORT == 1)
+void
+odm_txpowertracking_callback_thermal_meter_92e(
+ void *dm_void
+);
+#endif
+
+#if (RTL8814A_SUPPORT == 1)
+void
+odm_txpowertracking_callback_thermal_meter_jaguar_series2(
+ void *dm_void
+);
+
+#elif ODM_IC_11AC_SERIES_SUPPORT
+void
+odm_txpowertracking_callback_thermal_meter_jaguar_series(
+ void *dm_void
+);
+
+#elif (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1)
+void
+odm_txpowertracking_callback_thermal_meter_jaguar_series3(
+ void *dm_void
+);
+
+#endif
+
+#define IS_CCK_RATE(_rate) (ODM_MGN_1M == _rate || _rate == ODM_MGN_2M || _rate == ODM_MGN_5_5M || _rate == ODM_MGN_11M)
+
+#define ODM_TARGET_CHNL_NUM_2G_5G 59
+
+
+void
+odm_reset_iqk_result(
+ void *dm_void
+);
+u8
+odm_get_right_chnl_place_for_iqk(
+ u8 chnl
+);
+
+void phydm_rf_init(void *dm_void);
+void phydm_rf_watchdog(void *dm_void);
+
+#endif /* #ifndef __HAL_PHY_RF_H__ */
diff --git a/hal/phydm/halrf/halphyrf_ce.c b/hal/phydm/halrf/halphyrf_ce.c
new file mode 100644
index 0000000..847a685
--- /dev/null
+++ b/hal/phydm/halrf/halphyrf_ce.c
@@ -0,0 +1,907 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger
+ *
+ *****************************************************************************/
+
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _delta_thermal) \
+ do {\
+ for (_offset = 0; _offset < _size; _offset++) { \
+ if (_delta_thermal < thermal_threshold[_direction][_offset]) { \
+ if (_offset != 0)\
+ _offset--;\
+ break;\
+ } \
+ } \
+ if (_offset >= _size)\
+ _offset = _size-1;\
+ } while (0)
+
+void configure_txpower_track(
+ void *dm_void,
+ struct txpwrtrack_cfg *config
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+#if RTL8192E_SUPPORT
+ if (dm->support_ic_type == ODM_RTL8192E)
+ configure_txpower_track_8192e(config);
+#endif
+#if RTL8821A_SUPPORT
+ if (dm->support_ic_type == ODM_RTL8821)
+ configure_txpower_track_8821a(config);
+#endif
+#if RTL8812A_SUPPORT
+ if (dm->support_ic_type == ODM_RTL8812)
+ configure_txpower_track_8812a(config);
+#endif
+#if RTL8188E_SUPPORT
+ if (dm->support_ic_type == ODM_RTL8188E)
+ configure_txpower_track_8188e(config);
+#endif
+
+#if RTL8723B_SUPPORT
+ if (dm->support_ic_type == ODM_RTL8723B)
+ configure_txpower_track_8723b(config);
+#endif
+
+#if RTL8814A_SUPPORT
+ if (dm->support_ic_type == ODM_RTL8814A)
+ configure_txpower_track_8814a(config);
+#endif
+
+#if RTL8703B_SUPPORT
+ if (dm->support_ic_type == ODM_RTL8703B)
+ configure_txpower_track_8703b(config);
+#endif
+
+#if RTL8188F_SUPPORT
+ if (dm->support_ic_type == ODM_RTL8188F)
+ configure_txpower_track_8188f(config);
+#endif
+#if RTL8723D_SUPPORT
+ if (dm->support_ic_type == ODM_RTL8723D)
+ configure_txpower_track_8723d(config);
+#endif
+/* JJ ADD 20161014 */
+#if RTL8710B_SUPPORT
+ if (dm->support_ic_type == ODM_RTL8710B)
+ configure_txpower_track_8710b(config);
+#endif
+
+#if RTL8822B_SUPPORT
+ if (dm->support_ic_type == ODM_RTL8822B)
+ configure_txpower_track_8822b(config);
+#endif
+#if RTL8821C_SUPPORT
+ if (dm->support_ic_type == ODM_RTL8821C)
+ configure_txpower_track_8821c(config);
+#endif
+
+}
+
+/* **********************************************************************
+ * <20121113, Kordan> This function should be called when tx_agc changed.
+ * Otherwise the previous compensation is gone, because we record the
+ * delta of temperature between two TxPowerTracking watch dogs.
+ *
+ * NOTE: If Tx BB swing or Tx scaling is varified during run-time, still
+ * need to call this function.
+ * ********************************************************************** */
+void
+odm_clear_txpowertracking_state(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
+ struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
+ struct rtl_efuse *rtlefu = rtl_efuse(rtlpriv);
+#else
+ PHAL_DATA_TYPE hal_data = GET_HAL_DATA(dm->adapter);
+#endif
+ u8 p = 0;
+ struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
+
+ cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;
+ cali_info->bb_swing_idx_cck = cali_info->default_cck_index;
+ dm->rf_calibrate_info.CCK_index = 0;
+
+ for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) {
+ cali_info->bb_swing_idx_ofdm_base[p] = cali_info->default_ofdm_index;
+ cali_info->bb_swing_idx_ofdm[p] = cali_info->default_ofdm_index;
+ cali_info->OFDM_index[p] = cali_info->default_ofdm_index;
+
+ cali_info->power_index_offset[p] = 0;
+ cali_info->delta_power_index[p] = 0;
+ cali_info->delta_power_index_last[p] = 0;
+
+ cali_info->absolute_ofdm_swing_idx[p] = 0; /* Initial Mix mode power tracking*/
+ cali_info->remnant_ofdm_swing_idx[p] = 0;
+ cali_info->kfree_offset[p] = 0;
+ }
+
+ cali_info->modify_tx_agc_flag_path_a = false; /*Initial at Modify Tx Scaling mode*/
+ cali_info->modify_tx_agc_flag_path_b = false; /*Initial at Modify Tx Scaling mode*/
+ cali_info->modify_tx_agc_flag_path_c = false; /*Initial at Modify Tx Scaling mode*/
+ cali_info->modify_tx_agc_flag_path_d = false; /*Initial at Modify Tx Scaling mode*/
+ cali_info->remnant_cck_swing_idx = 0;
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
+ cali_info->thermal_value = rtlefu->eeprom_thermalmeter;
+#else
+ cali_info->thermal_value = hal_data->eeprom_thermal_meter;
+#endif
+
+ cali_info->modify_tx_agc_value_cck = 0; /* modify by Mingzhi.Guo */
+ cali_info->modify_tx_agc_value_ofdm = 0; /* modify by Mingzhi.Guo */
+
+}
+
+void
+odm_txpowertracking_callback_thermal_meter(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ struct dm_struct *dm
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ void *dm_void
+#else
+ void *adapter
+#endif
+)
+{
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
+ struct rtl_efuse *rtlefu = rtl_efuse(rtlpriv);
+ void *adapter = dm->adapter;
+#elif !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+ struct dm_struct *dm = &hal_data->DM_OutSrc;
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ void *adapter = dm->adapter;
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+#endif
+#endif
+
+ struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+
+ u8 thermal_value = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0;
+ s8 diff_DPK[4] = {0};
+ u8 thermal_value_avg_count = 0;
+ u32 thermal_value_avg = 0, regc80, regcd0, regcd4, regab4;
+
+ u8 OFDM_min_index = 0; /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */
+ u8 indexforchannel = 0; /* get_right_chnl_place_for_iqk(hal_data->current_channel) */
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
+ u8 power_tracking_type = 0; /* no specify type */
+#else
+ u8 power_tracking_type = hal_data->rf_power_tracking_type;
+#endif
+ u8 xtal_offset_eanble = 0;
+ s8 thermal_value_temp = 0;
+
+ struct txpwrtrack_cfg c = {0};
+
+ /* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */
+ u8 *delta_swing_table_idx_tup_a = NULL;
+ u8 *delta_swing_table_idx_tdown_a = NULL;
+ u8 *delta_swing_table_idx_tup_b = NULL;
+ u8 *delta_swing_table_idx_tdown_b = NULL;
+ /*for 8814 add by Yu Chen*/
+ u8 *delta_swing_table_idx_tup_c = NULL;
+ u8 *delta_swing_table_idx_tdown_c = NULL;
+ u8 *delta_swing_table_idx_tup_d = NULL;
+ u8 *delta_swing_table_idx_tdown_d = NULL;
+ /*for Xtal Offset by James.Tung*/
+ s8 *delta_swing_table_xtal_up = NULL;
+ s8 *delta_swing_table_xtal_down = NULL;
+
+ /* 4 2. Initilization ( 7 steps in total ) */
+
+ configure_txpower_track(dm, &c);
+
+ (*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,
+ (u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b);
+
+ if (dm->support_ic_type & ODM_RTL8814A) /*for 8814 path C & D*/
+ (*c.get_delta_swing_table8814only)(dm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c,
+ (u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d);
+ /* JJ ADD 20161014 */
+ if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) /*for Xtal Offset*/
+ (*c.get_delta_swing_xtal_table)(dm, (s8 **)&delta_swing_table_xtal_up, (s8 **)&delta_swing_table_xtal_down);
+
+ cali_info->txpowertracking_callback_cnt++; /*cosa add for debug*/
+ cali_info->is_txpowertracking_init = true;
+
+ /*cali_info->txpowertrack_control = hal_data->txpowertrack_control;
+ We should keep updating the control variable according to HalData.
+ rf_calibrate_info.rega24 will be initialized when ODM HW configuring, but MP configures with para files. */
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+#if (MP_DRIVER == 1)
+ cali_info->rega24 = 0x090e1317;
+#endif
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+ if (*(dm->mp_mode) == true)
+ cali_info->rega24 = 0x090e1317;
+#endif
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "===>odm_txpowertracking_callback_thermal_meter\n cali_info->bb_swing_idx_cck_base: %d, cali_info->bb_swing_idx_ofdm_base[A]: %d, cali_info->default_ofdm_index: %d\n",
+ cali_info->bb_swing_idx_cck_base, cali_info->bb_swing_idx_ofdm_base[RF_PATH_A], cali_info->default_ofdm_index);
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "cali_info->txpowertrack_control=%d, rtlefu->eeprom_thermalmeter %d\n", cali_info->txpowertrack_control, rtlefu->eeprom_thermalmeter);
+#else
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "cali_info->txpowertrack_control=%d, hal_data->eeprom_thermal_meter %d\n", cali_info->txpowertrack_control, hal_data->eeprom_thermal_meter);
+#endif
+
+ thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00); /* 0x42: RF Reg[15:10] 88E */
+
+ thermal_value_temp = thermal_value + phydm_get_thermal_offset(dm);
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "thermal_value_temp(%d) = thermal_value(%d) + power_trim_thermal(%d)\n", thermal_value_temp, thermal_value, phydm_get_thermal_offset(dm));
+
+ if (thermal_value_temp > 63)
+ thermal_value = 63;
+ else if (thermal_value_temp < 0)
+ thermal_value = 0;
+ else
+ thermal_value = thermal_value_temp;
+
+ /*add log by zhao he, check c80/c94/c14/ca0 value*/
+ if (dm->support_ic_type == ODM_RTL8723D) {
+ regc80 = odm_get_bb_reg(dm, 0xc80, MASKDWORD);
+ regcd0 = odm_get_bb_reg(dm, 0xcd0, MASKDWORD);
+ regcd4 = odm_get_bb_reg(dm, 0xcd4, MASKDWORD);
+ regab4 = odm_get_bb_reg(dm, 0xab4, 0x000007FF);
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4);
+ }
+ /* JJ ADD 20161014 */
+ if (dm->support_ic_type == ODM_RTL8710B) {
+ regc80 = odm_get_bb_reg(dm, 0xc80, MASKDWORD);
+ regcd0 = odm_get_bb_reg(dm, 0xcd0, MASKDWORD);
+ regcd4 = odm_get_bb_reg(dm, 0xcd4, MASKDWORD);
+ regab4 = odm_get_bb_reg(dm, 0xab4, 0x000007FF);
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4);
+ }
+
+ if (!cali_info->txpowertrack_control)
+ return;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
+ if (rtlefu->eeprom_thermalmeter == 0xff) {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "no pg, hal_data->eeprom_thermal_meter = 0x%x\n", rtlefu->eeprom_thermalmeter);
+ return;
+ }
+#else
+ if (hal_data->eeprom_thermal_meter == 0xff) {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "no pg, hal_data->eeprom_thermal_meter = 0x%x\n", hal_data->eeprom_thermal_meter);
+ return;
+ }
+#endif
+
+ /*4 3. Initialize ThermalValues of rf_calibrate_info*/
+
+ if (cali_info->is_reloadtxpowerindex)
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "reload ofdm index for band switch\n");
+
+ /*4 4. Calculate average thermal meter*/
+
+ cali_info->thermal_value_avg[cali_info->thermal_value_avg_index] = thermal_value;
+ cali_info->thermal_value_avg_index++;
+ if (cali_info->thermal_value_avg_index == c.average_thermal_num) /*Average times = c.average_thermal_num*/
+ cali_info->thermal_value_avg_index = 0;
+
+ for (i = 0; i < c.average_thermal_num; i++) {
+ if (cali_info->thermal_value_avg[i]) {
+ thermal_value_avg += cali_info->thermal_value_avg[i];
+ thermal_value_avg_count++;
+ }
+ }
+
+ if (thermal_value_avg_count) { /* Calculate Average thermal_value after average enough times */
+ thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
+ cali_info->thermal_value_delta = thermal_value - rtlefu->eeprom_thermalmeter;
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n", thermal_value, rtlefu->eeprom_thermalmeter);
+#else
+ cali_info->thermal_value_delta = thermal_value - hal_data->eeprom_thermal_meter;
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n", thermal_value, hal_data->eeprom_thermal_meter);
+#endif
+ }
+
+ /* 4 5. Calculate delta, delta_LCK, delta_IQK. */
+
+ /* "delta" here is used to determine whether thermal value changes or not. */
+ delta = (thermal_value > cali_info->thermal_value) ? (thermal_value - cali_info->thermal_value) : (cali_info->thermal_value - thermal_value);
+ delta_LCK = (thermal_value > cali_info->thermal_value_lck) ? (thermal_value - cali_info->thermal_value_lck) : (cali_info->thermal_value_lck - thermal_value);
+ delta_IQK = (thermal_value > cali_info->thermal_value_iqk) ? (thermal_value - cali_info->thermal_value_iqk) : (cali_info->thermal_value_iqk - thermal_value);
+
+ if (cali_info->thermal_value_iqk == 0xff) { /*no PG, use thermal value for IQK*/
+ cali_info->thermal_value_iqk = thermal_value;
+ delta_IQK = (thermal_value > cali_info->thermal_value_iqk) ? (thermal_value - cali_info->thermal_value_iqk) : (cali_info->thermal_value_iqk - thermal_value);
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "no PG, use thermal_value for IQK\n");
+ }
+
+ for (p = RF_PATH_A; p < c.rf_path_count; p++)
+ diff_DPK[p] = (s8)thermal_value - (s8)cali_info->dpk_thermal[p];
+
+ /*4 6. If necessary, do LCK.*/
+
+ if (!(dm->support_ic_type & ODM_RTL8821)) { /*no PG, do LCK at initial status*/
+ if (cali_info->thermal_value_lck == 0xff) {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "no PG, do LCK\n");
+ cali_info->thermal_value_lck = thermal_value;
+
+ /*Use RTLCK, so close power tracking driver LCK*/
+ if (!(dm->support_ic_type & ODM_RTL8814A) && !(dm->support_ic_type & ODM_RTL8822B) && c.phy_lc_calibrate)
+ (*c.phy_lc_calibrate)(dm);
+
+ delta_LCK = (thermal_value > cali_info->thermal_value_lck) ? (thermal_value - cali_info->thermal_value_lck) : (cali_info->thermal_value_lck - thermal_value);
+ }
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK);
+
+ /* Wait sacn to do LCK by RF Jenyu*/
+ if ((*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) {
+ /* Delta temperature is equal to or larger than 20 centigrade.*/
+ if (delta_LCK >= c.threshold_iqk) {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
+ cali_info->thermal_value_lck = thermal_value;
+
+ /*Use RTLCK, so close power tracking driver LCK*/
+ if (!(dm->support_ic_type & ODM_RTL8814A) && !(dm->support_ic_type & ODM_RTL8822B) && c.phy_lc_calibrate)
+ (*c.phy_lc_calibrate)(dm);
+ }
+ }
+ }
+
+ /*3 7. If necessary, move the index of swing table to adjust Tx power.*/
+
+ if (delta > 0 && cali_info->txpowertrack_control) {
+ /* "delta" here is used to record the absolute value of differrence. */
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
+ delta = thermal_value > rtlefu->eeprom_thermalmeter ? (thermal_value - rtlefu->eeprom_thermalmeter) : (rtlefu->eeprom_thermalmeter - thermal_value);
+#else
+ delta = thermal_value > hal_data->eeprom_thermal_meter ? (thermal_value - hal_data->eeprom_thermal_meter) : (hal_data->eeprom_thermal_meter - thermal_value);
+#endif
+#else
+ delta = (thermal_value > dm->priv->pmib->dot11RFEntry.ther) ? (thermal_value - dm->priv->pmib->dot11RFEntry.ther) : (dm->priv->pmib->dot11RFEntry.ther - thermal_value);
+#endif
+ if (delta >= TXPWR_TRACK_TABLE_SIZE)
+ delta = TXPWR_TRACK_TABLE_SIZE - 1;
+
+ /*4 7.1 The Final Power index = BaseIndex + power_index_offset*/
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
+ if (thermal_value > rtlefu->eeprom_thermalmeter) {
+#else
+ if (thermal_value > hal_data->eeprom_thermal_meter) {
+#endif
+#else
+ if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) {
+#endif
+
+ for (p = RF_PATH_A; p < c.rf_path_count; p++) {
+ cali_info->delta_power_index_last[p] = cali_info->delta_power_index[p]; /*recording poer index offset*/
+ switch (p) {
+ case RF_PATH_B:
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta]);
+
+ cali_info->delta_power_index[p] = delta_swing_table_idx_tup_b[delta];
+ cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_b[delta]; /*Record delta swing for mix mode power tracking*/
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+ break;
+
+ case RF_PATH_C:
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "delta_swing_table_idx_tup_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta]);
+
+ cali_info->delta_power_index[p] = delta_swing_table_idx_tup_c[delta];
+ cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_c[delta]; /*Record delta swing for mix mode power tracking*/
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+ break;
+
+ case RF_PATH_D:
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "delta_swing_table_idx_tup_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta]);
+
+ cali_info->delta_power_index[p] = delta_swing_table_idx_tup_d[delta];
+ cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_d[delta]; /*Record delta swing for mix mode power tracking*/
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+ break;
+
+ default:
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta]);
+
+ cali_info->delta_power_index[p] = delta_swing_table_idx_tup_a[delta];
+ cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_a[delta]; /*Record delta swing for mix mode power tracking*/
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+ break;
+ }
+ }
+ /* JJ ADD 20161014 */
+ if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {
+ /*Save xtal_offset from Xtal table*/
+ cali_info->xtal_offset_last = cali_info->xtal_offset; /*recording last Xtal offset*/
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "[Xtal] delta_swing_table_xtal_up[%d] = %d\n", delta, delta_swing_table_xtal_up[delta]);
+ cali_info->xtal_offset = delta_swing_table_xtal_up[delta];
+ xtal_offset_eanble = (cali_info->xtal_offset_last != cali_info->xtal_offset);
+ }
+
+ } else {
+ for (p = RF_PATH_A; p < c.rf_path_count; p++) {
+ cali_info->delta_power_index_last[p] = cali_info->delta_power_index[p]; /*recording poer index offset*/
+
+ switch (p) {
+ case RF_PATH_B:
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta]);
+ cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_b[delta];
+ cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta]; /*Record delta swing for mix mode power tracking*/
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+ break;
+
+ case RF_PATH_C:
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "delta_swing_table_idx_tdown_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta]);
+ cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_c[delta];
+ cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_c[delta]; /*Record delta swing for mix mode power tracking*/
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+ break;
+
+ case RF_PATH_D:
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "delta_swing_table_idx_tdown_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta]);
+ cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_d[delta];
+ cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_d[delta]; /*Record delta swing for mix mode power tracking*/
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+ break;
+
+ default:
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta]);
+ cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_a[delta];
+ cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta]; /*Record delta swing for mix mode power tracking*/
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+ break;
+ }
+ }
+ /* JJ ADD 20161014 */
+ if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {
+ /*Save xtal_offset from Xtal table*/
+ cali_info->xtal_offset_last = cali_info->xtal_offset; /*recording last Xtal offset*/
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "[Xtal] delta_swing_table_xtal_down[%d] = %d\n", delta, delta_swing_table_xtal_down[delta]);
+ cali_info->xtal_offset = delta_swing_table_xtal_down[delta];
+ xtal_offset_eanble = (cali_info->xtal_offset_last != cali_info->xtal_offset);
+ }
+
+ }
+
+ for (p = RF_PATH_A; p < c.rf_path_count; p++) {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "\n\n=========================== [path-%d] Calculating power_index_offset===========================\n", p);
+
+ if (cali_info->delta_power_index[p] == cali_info->delta_power_index_last[p]) /*If Thermal value changes but lookup table value still the same*/
+ cali_info->power_index_offset[p] = 0;
+ else
+ cali_info->power_index_offset[p] = cali_info->delta_power_index[p] - cali_info->delta_power_index_last[p]; /*Power index diff between 2 times Power Tracking*/
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "[path-%d] power_index_offset(%d) = delta_power_index(%d) - delta_power_index_last(%d)\n", p, cali_info->power_index_offset[p], cali_info->delta_power_index[p], cali_info->delta_power_index_last[p]);
+
+ cali_info->OFDM_index[p] = cali_info->bb_swing_idx_ofdm_base[p] + cali_info->power_index_offset[p];
+ cali_info->CCK_index = cali_info->bb_swing_idx_cck_base + cali_info->power_index_offset[p];
+
+ cali_info->bb_swing_idx_cck = cali_info->CCK_index;
+ cali_info->bb_swing_idx_ofdm[p] = cali_info->OFDM_index[p];
+
+ /*************Print BB Swing base and index Offset*************/
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_cck, cali_info->bb_swing_idx_cck_base, cali_info->power_index_offset[p]);
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "The 'OFDM' final index(%d) = BaseIndex[%d](%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_ofdm[p], p, cali_info->bb_swing_idx_ofdm_base[p], cali_info->power_index_offset[p]);
+
+ /*4 7.1 Handle boundary conditions of index.*/
+
+ if (cali_info->OFDM_index[p] > c.swing_table_size_ofdm - 1)
+ cali_info->OFDM_index[p] = c.swing_table_size_ofdm - 1;
+ else if (cali_info->OFDM_index[p] <= OFDM_min_index)
+ cali_info->OFDM_index[p] = OFDM_min_index;
+ }
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "\n\n========================================================================================================\n");
+
+ if (cali_info->CCK_index > c.swing_table_size_cck - 1)
+ cali_info->CCK_index = c.swing_table_size_cck - 1;
+ else if (cali_info->CCK_index <= 0)
+ cali_info->CCK_index = 0;
+ } else {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "The thermal meter is unchanged or TxPowerTracking OFF(%d): thermal_value: %d, cali_info->thermal_value: %d\n",
+ cali_info->txpowertrack_control, thermal_value, cali_info->thermal_value);
+
+ for (p = RF_PATH_A; p < c.rf_path_count; p++)
+ cali_info->power_index_offset[p] = 0;
+ }
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n",
+ cali_info->CCK_index, cali_info->bb_swing_idx_cck_base); /*Print Swing base & current*/
+
+ for (p = RF_PATH_A; p < c.rf_path_count; p++) {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index[%d]: %d\n",
+ cali_info->OFDM_index[p], p, cali_info->bb_swing_idx_ofdm_base[p]);
+ }
+
+ if ((dm->support_ic_type & ODM_RTL8814A)) {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "power_tracking_type=%d\n", power_tracking_type);
+
+ if (power_tracking_type == 0) {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
+ for (p = RF_PATH_A; p < c.rf_path_count; p++)
+ (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
+ } else if (power_tracking_type == 1) {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX(2G) TSSI(5G) MODE**********\n");
+ for (p = RF_PATH_A; p < c.rf_path_count; p++)
+ (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_2G_TSSI_5G_MODE, p, 0);
+ } else if (power_tracking_type == 2) {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX(5G) TSSI(2G)MODE**********\n");
+ for (p = RF_PATH_A; p < c.rf_path_count; p++)
+ (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_5G_TSSI_2G_MODE, p, 0);
+ } else if (power_tracking_type == 3) {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking TSSI MODE**********\n");
+ for (p = RF_PATH_A; p < c.rf_path_count; p++)
+ (*c.odm_tx_pwr_track_set_pwr)(dm, TSSI_MODE, p, 0);
+ }
+ cali_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/
+
+ } else if ((cali_info->power_index_offset[RF_PATH_A] != 0 ||
+ cali_info->power_index_offset[RF_PATH_B] != 0 ||
+ cali_info->power_index_offset[RF_PATH_C] != 0 ||
+ cali_info->power_index_offset[RF_PATH_D] != 0) &&
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
+ cali_info->txpowertrack_control && (rtlefu->eeprom_thermalmeter != 0xff)) {
+#else
+ cali_info->txpowertrack_control && (hal_data->eeprom_thermal_meter != 0xff)) {
+#endif
+ /* 4 7.2 Configure the Swing Table to adjust Tx Power. */
+
+ cali_info->is_tx_power_changed = true; /*Always true after Tx Power is adjusted by power tracking.*/
+ /* */
+ /* 2012/04/23 MH According to Luke's suggestion, we can not write BB digital */
+ /* to increase TX power. Otherwise, EVM will be bad. */
+ /* */
+ /* 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. */
+ if (thermal_value > cali_info->thermal_value) {
+ for (p = RF_PATH_A; p < c.rf_path_count; p++) {
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "Temperature Increasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
+ p, cali_info->power_index_offset[p], delta, thermal_value, rtlefu->eeprom_thermalmeter, cali_info->thermal_value);
+#else
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "Temperature Increasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
+ p, cali_info->power_index_offset[p], delta, thermal_value, hal_data->eeprom_thermal_meter, cali_info->thermal_value);
+#endif
+ }
+ } else if (thermal_value < cali_info->thermal_value) { /*Low temperature*/
+ for (p = RF_PATH_A; p < c.rf_path_count; p++) {
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "Temperature Decreasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
+ p, cali_info->power_index_offset[p], delta, thermal_value, rtlefu->eeprom_thermalmeter, cali_info->thermal_value);
+#else
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "Temperature Decreasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
+ p, cali_info->power_index_offset[p], delta, thermal_value, hal_data->eeprom_thermal_meter, cali_info->thermal_value);
+#endif
+ }
+ }
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
+ if (thermal_value > rtlefu->eeprom_thermalmeter)
+#else
+ if (thermal_value > hal_data->eeprom_thermal_meter)
+#endif
+#else
+ if (thermal_value > dm->priv->pmib->dot11RFEntry.ther)
+#endif
+ {
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "Temperature(%d) higher than PG value(%d)\n", thermal_value, rtlefu->eeprom_thermalmeter);
+#else
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "Temperature(%d) higher than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter);
+#endif
+
+ if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8821 ||
+ dm->support_ic_type == ODM_RTL8812 || dm->support_ic_type == ODM_RTL8723B || dm->support_ic_type == ODM_RTL8814A ||
+ dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8822B ||
+ dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
+ for (p = RF_PATH_A; p < c.rf_path_count; p++)
+ (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
+ } else {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
+ for (p = RF_PATH_A; p < c.rf_path_count; p++)
+ (*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel);
+ }
+ } else {
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "Temperature(%d) lower than PG value(%d)\n", thermal_value, rtlefu->eeprom_thermalmeter);
+#else
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "Temperature(%d) lower than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter);
+#endif
+
+ if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8821 ||
+ dm->support_ic_type == ODM_RTL8812 || dm->support_ic_type == ODM_RTL8723B || dm->support_ic_type == ODM_RTL8814A ||
+ dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8822B ||
+ dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
+ for (p = RF_PATH_A; p < c.rf_path_count; p++)
+ (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, indexforchannel);
+ } else {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
+ for (p = RF_PATH_A; p < c.rf_path_count; p++)
+ (*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel);
+ }
+
+ }
+
+ cali_info->bb_swing_idx_cck_base = cali_info->bb_swing_idx_cck; /*Record last time Power Tracking result as base.*/
+ for (p = RF_PATH_A; p < c.rf_path_count; p++)
+ cali_info->bb_swing_idx_ofdm_base[p] = cali_info->bb_swing_idx_ofdm[p];
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "cali_info->thermal_value = %d thermal_value= %d\n", cali_info->thermal_value, thermal_value);
+
+ cali_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/
+
+ }
+
+
+ if (dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
+ if (xtal_offset_eanble != 0 && cali_info->txpowertrack_control && (rtlefu->eeprom_thermalmeter != 0xff)) {
+#else
+ if (xtal_offset_eanble != 0 && cali_info->txpowertrack_control && (hal_data->eeprom_thermal_meter != 0xff)) {
+#endif
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter Xtal Tracking**********\n");
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
+ if (thermal_value > rtlefu->eeprom_thermalmeter) {
+#else
+ if (thermal_value > hal_data->eeprom_thermal_meter) {
+#endif
+#else
+ if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) {
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "Temperature(%d) higher than PG value(%d)\n", thermal_value, rtlefu->eeprom_thermalmeter);
+#else
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "Temperature(%d) higher than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter);
+#endif
+ (*c.odm_txxtaltrack_set_xtal)(dm);
+ } else {
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "Temperature(%d) lower than PG value(%d)\n", thermal_value, rtlefu->eeprom_thermalmeter);
+#else
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "Temperature(%d) lower than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter);
+#endif
+ (*c.odm_txxtaltrack_set_xtal)(dm);
+ }
+ }
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********End Xtal Tracking**********\n");
+ }
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+
+ /* Wait sacn to do IQK by RF Jenyu*/
+ if ((*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) {
+ if (!IS_HARDWARE_TYPE_8723B(adapter)) {
+ /*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
+ if (delta_IQK >= c.threshold_iqk) {
+ cali_info->thermal_value_iqk = thermal_value;
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
+ if (!cali_info->is_iqk_in_progress)
+ (*c.do_iqk)(dm, delta_IQK, thermal_value, 8);
+ }
+ }
+ }
+ if (cali_info->dpk_thermal[RF_PATH_A] != 0) {
+ if (diff_DPK[RF_PATH_A] >= c.threshold_dpk) {
+ odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
+ odm_set_bb_reg(dm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_A] / c.threshold_dpk));
+ odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
+ } else if ((diff_DPK[RF_PATH_A] <= -1 * c.threshold_dpk)) {
+ s32 value = 0x20 + (diff_DPK[RF_PATH_A] / c.threshold_dpk);
+
+ odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
+ odm_set_bb_reg(dm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);
+ odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
+ } else {
+ odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
+ odm_set_bb_reg(dm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);
+ odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
+ }
+ }
+ if (cali_info->dpk_thermal[RF_PATH_B] != 0) {
+ if (diff_DPK[RF_PATH_B] >= c.threshold_dpk) {
+ odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
+ odm_set_bb_reg(dm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_B] / c.threshold_dpk));
+ odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
+ } else if ((diff_DPK[RF_PATH_B] <= -1 * c.threshold_dpk)) {
+ s32 value = 0x20 + (diff_DPK[RF_PATH_B] / c.threshold_dpk);
+
+ odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
+ odm_set_bb_reg(dm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);
+ odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
+ } else {
+ odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
+ odm_set_bb_reg(dm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);
+ odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
+ }
+ }
+
+#endif
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "<===odm_txpowertracking_callback_thermal_meter\n");
+
+ cali_info->tx_powercount = 0;
+}
+
+
+
+/* 3============================================================
+ * 3 IQ Calibration
+ * 3============================================================ */
+
+void
+odm_reset_iqk_result(
+ void *dm_void
+)
+{
+ return;
+}
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+u8 odm_get_right_chnl_place_for_iqk(u8 chnl)
+{
+ u8 channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = {
+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, 161, 163, 165
+ };
+ u8 place = chnl;
+
+
+ if (chnl > 14) {
+ for (place = 14; place < sizeof(channel_all); place++) {
+ if (channel_all[place] == chnl)
+ return place - 13;
+ }
+ }
+ return 0;
+
+}
+#endif
+
+void
+odm_iq_calibrate(
+ struct dm_struct *dm
+)
+{
+ void *adapter = dm->adapter;
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+ if (*dm->is_fcs_mode_enable)
+ return;
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
+ if (IS_HARDWARE_TYPE_8812AU(adapter))
+ return;
+#endif
+
+ if ((dm->is_linked) && (!iqk_info->rfk_forbidden)) {
+ if ((*dm->channel != dm->pre_channel) && (!*dm->is_scan_in_process)) {
+ dm->pre_channel = *dm->channel;
+ dm->linked_interval = 0;
+ }
+
+ if (dm->linked_interval < 3)
+ dm->linked_interval++;
+
+ if (dm->linked_interval == 2)
+ halrf_iqk_trigger(dm, false);
+ } else
+ dm->linked_interval = 0;
+}
+
+void phydm_rf_init(void *dm_void)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ odm_txpowertracking_init(dm);
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+ odm_clear_txpowertracking_state(dm);
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+#if (RTL8814A_SUPPORT == 1)
+ if (dm->support_ic_type & ODM_RTL8814A)
+ phy_iq_calibrate_8814a_init(dm);
+#endif
+#endif
+
+}
+
+void phydm_rf_watchdog(void *dm_void)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+ odm_txpowertracking_check(dm);
+ /*if (dm->support_ic_type & ODM_IC_11AC_SERIES)*/
+ /*odm_iq_calibrate(dm);*/
+#endif
+}
diff --git a/hal/phydm/halrf/halphyrf_ce.h b/hal/phydm/halrf/halphyrf_ce.h
new file mode 100644
index 0000000..a4a8938
--- /dev/null
+++ b/hal/phydm/halrf/halphyrf_ce.h
@@ -0,0 +1,124 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger
+ *
+ *****************************************************************************/
+
+#ifndef __HAL_PHY_RF_H__
+#define __HAL_PHY_RF_H__
+
+#include "halrf/halrf_kfree.h"
+#if (RTL8814A_SUPPORT == 1)
+ #include "halrf/rtl8814a/halrf_iqk_8814a.h"
+#endif
+
+#if (RTL8822B_SUPPORT == 1)
+ #include "halrf/rtl8822b/halrf_iqk_8822b.h"
+#endif
+
+#if (RTL8821C_SUPPORT == 1)
+ #include "halrf/rtl8821c/halrf_iqk_8821c.h"
+#endif
+
+#include "halrf/halrf_powertracking_ce.h"
+
+
+enum spur_cal_method {
+ PLL_RESET,
+ AFE_PHASE_SEL
+};
+
+enum pwrtrack_method {
+ BBSWING,
+ TXAGC,
+ MIX_MODE,
+ TSSI_MODE,
+ MIX_2G_TSSI_5G_MODE,
+ MIX_5G_TSSI_2G_MODE
+};
+
+typedef void (*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
+typedef void(*func_iqk)(void *, u8, u8, u8);
+typedef void (*func_lck)(void *);
+typedef void (*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
+typedef void (*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
+typedef void(*func_swing_xtal)(void *, s8 **, s8 **);
+typedef void(*func_set_xtal)(void *);
+
+struct txpwrtrack_cfg {
+ u8 swing_table_size_cck;
+ u8 swing_table_size_ofdm;
+ u8 threshold_iqk;
+ u8 threshold_dpk;
+ u8 average_thermal_num;
+ u8 rf_path_count;
+ u32 thermal_reg_addr;
+ func_set_pwr odm_tx_pwr_track_set_pwr;
+ func_iqk do_iqk;
+ func_lck phy_lc_calibrate;
+ func_swing get_delta_swing_table;
+ func_swing8814only get_delta_swing_table8814only;
+ func_swing_xtal get_delta_swing_xtal_table;
+ func_set_xtal odm_txxtaltrack_set_xtal;
+};
+
+void
+configure_txpower_track(
+ void *dm_void,
+ struct txpwrtrack_cfg *config
+);
+
+
+void
+odm_clear_txpowertracking_state(
+ void *dm_void
+);
+
+void
+odm_txpowertracking_callback_thermal_meter(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ void *dm_void
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+ void *dm
+#else
+ void *adapter
+#endif
+);
+
+
+
+#define ODM_TARGET_CHNL_NUM_2G_5G 59
+
+
+void
+odm_reset_iqk_result(
+ void *dm_void
+);
+u8
+odm_get_right_chnl_place_for_iqk(
+ u8 chnl
+);
+
+void phydm_rf_init(void *dm_void);
+void phydm_rf_watchdog(void *dm_void);
+
+#endif /* #ifndef __HAL_PHY_RF_H__ */
diff --git a/hal/phydm/halrf/halphyrf_win.c b/hal/phydm/halrf/halphyrf_win.c
new file mode 100644
index 0000000..bb4c000
--- /dev/null
+++ b/hal/phydm/halrf/halphyrf_win.c
@@ -0,0 +1,817 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _delta_thermal) \
+ do {\
+ for (_offset = 0; _offset < _size; _offset++) { \
+ \
+ if (_delta_thermal < thermal_threshold[_direction][_offset]) { \
+ \
+ if (_offset != 0)\
+ _offset--;\
+ break;\
+ } \
+ } \
+ if (_offset >= _size)\
+ _offset = _size-1;\
+ } while (0)
+
+void configure_txpower_track(
+ struct dm_struct *dm,
+ struct txpwrtrack_cfg *config
+)
+{
+#if RTL8192E_SUPPORT
+ if (dm->support_ic_type == ODM_RTL8192E)
+ configure_txpower_track_8192e(config);
+#endif
+#if RTL8821A_SUPPORT
+ if (dm->support_ic_type == ODM_RTL8821)
+ configure_txpower_track_8821a(config);
+#endif
+#if RTL8812A_SUPPORT
+ if (dm->support_ic_type == ODM_RTL8812)
+ configure_txpower_track_8812a(config);
+#endif
+#if RTL8188E_SUPPORT
+ if (dm->support_ic_type == ODM_RTL8188E)
+ configure_txpower_track_8188e(config);
+#endif
+
+#if RTL8188F_SUPPORT
+ if (dm->support_ic_type == ODM_RTL8188F)
+ configure_txpower_track_8188f(config);
+#endif
+
+#if RTL8723B_SUPPORT
+ if (dm->support_ic_type == ODM_RTL8723B)
+ configure_txpower_track_8723b(config);
+#endif
+
+#if RTL8814A_SUPPORT
+ if (dm->support_ic_type == ODM_RTL8814A)
+ configure_txpower_track_8814a(config);
+#endif
+
+#if RTL8703B_SUPPORT
+ if (dm->support_ic_type == ODM_RTL8703B)
+ configure_txpower_track_8703b(config);
+#endif
+
+#if RTL8822B_SUPPORT
+ if (dm->support_ic_type == ODM_RTL8822B)
+ configure_txpower_track_8822b(config);
+#endif
+
+#if RTL8723D_SUPPORT
+ if (dm->support_ic_type == ODM_RTL8723D)
+ configure_txpower_track_8723d(config);
+#endif
+
+/* JJ ADD 20161014 */
+#if RTL8710B_SUPPORT
+ if (dm->support_ic_type == ODM_RTL8710B)
+ configure_txpower_track_8710b(config);
+#endif
+
+#if RTL8821C_SUPPORT
+ if (dm->support_ic_type == ODM_RTL8821C)
+ configure_txpower_track_8821c(config);
+#endif
+
+}
+
+/* **********************************************************************
+ * <20121113, Kordan> This function should be called when tx_agc changed.
+ * Otherwise the previous compensation is gone, because we record the
+ * delta of temperature between two TxPowerTracking watch dogs.
+ *
+ * NOTE: If Tx BB swing or Tx scaling is varified during run-time, still
+ * need to call this function.
+ * ********************************************************************** */
+void
+odm_clear_txpowertracking_state(
+ struct dm_struct *dm
+)
+{
+ PHAL_DATA_TYPE hal_data = GET_HAL_DATA((PADAPTER)(dm->adapter));
+ u8 p = 0;
+ struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
+
+ cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;
+ cali_info->bb_swing_idx_cck = cali_info->default_cck_index;
+ cali_info->CCK_index = 0;
+
+ for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) {
+ cali_info->bb_swing_idx_ofdm_base[p] = cali_info->default_ofdm_index;
+ cali_info->bb_swing_idx_ofdm[p] = cali_info->default_ofdm_index;
+ cali_info->OFDM_index[p] = cali_info->default_ofdm_index;
+
+ cali_info->power_index_offset[p] = 0;
+ cali_info->delta_power_index[p] = 0;
+ cali_info->delta_power_index_last[p] = 0;
+
+ cali_info->absolute_ofdm_swing_idx[p] = 0; /* Initial Mix mode power tracking*/
+ cali_info->remnant_ofdm_swing_idx[p] = 0;
+ cali_info->kfree_offset[p] = 0;
+ }
+
+ cali_info->modify_tx_agc_flag_path_a = false; /*Initial at Modify Tx Scaling mode*/
+ cali_info->modify_tx_agc_flag_path_b = false; /*Initial at Modify Tx Scaling mode*/
+ cali_info->modify_tx_agc_flag_path_c = false; /*Initial at Modify Tx Scaling mode*/
+ cali_info->modify_tx_agc_flag_path_d = false; /*Initial at Modify Tx Scaling mode*/
+ cali_info->remnant_cck_swing_idx = 0;
+ cali_info->thermal_value = hal_data->eeprom_thermal_meter;
+
+ cali_info->modify_tx_agc_value_cck = 0; /* modify by Mingzhi.Guo */
+ cali_info->modify_tx_agc_value_ofdm = 0; /* modify by Mingzhi.Guo */
+
+}
+
+void
+odm_txpowertracking_callback_thermal_meter(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ struct dm_struct *dm
+#else
+ void *adapter
+#endif
+)
+{
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+ struct dm_struct *dm = &hal_data->DM_OutSrc;
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ struct dm_struct *dm = &hal_data->odmpriv;
+#endif
+#endif
+
+ struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+ u8 thermal_value = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0;
+ s8 diff_DPK[4] = {0};
+ u8 thermal_value_avg_count = 0;
+ u32 thermal_value_avg = 0, regc80, regcd0, regcd4, regab4;
+
+ u8 OFDM_min_index = 0; /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */
+ u8 indexforchannel = 0; /* get_right_chnl_place_for_iqk(hal_data->current_channel) */
+ u8 power_tracking_type = hal_data->RfPowerTrackingType;
+ u8 xtal_offset_eanble = 0;
+ s8 thermal_value_temp = 0;
+
+ struct txpwrtrack_cfg c;
+
+ /* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */
+ u8 *delta_swing_table_idx_tup_a = NULL;
+ u8 *delta_swing_table_idx_tdown_a = NULL;
+ u8 *delta_swing_table_idx_tup_b = NULL;
+ u8 *delta_swing_table_idx_tdown_b = NULL;
+ /*for 8814 add by Yu Chen*/
+ u8 *delta_swing_table_idx_tup_c = NULL;
+ u8 *delta_swing_table_idx_tdown_c = NULL;
+ u8 *delta_swing_table_idx_tup_d = NULL;
+ u8 *delta_swing_table_idx_tdown_d = NULL;
+ /*for Xtal Offset by James.Tung*/
+ s8 *delta_swing_table_xtal_up = NULL;
+ s8 *delta_swing_table_xtal_down = NULL;
+
+ /* 4 2. Initilization ( 7 steps in total ) */
+
+ configure_txpower_track(dm, &c);
+
+ (*c.get_delta_swing_table)(dm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a,
+ (u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b);
+
+ if (dm->support_ic_type & ODM_RTL8814A) /*for 8814 path C & D*/
+ (*c.get_delta_swing_table8814only)(dm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c,
+ (u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d);
+ /* JJ ADD 20161014 */
+ if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) /*for Xtal Offset*/
+ (*c.get_delta_swing_xtal_table)(dm, (s8 **)&delta_swing_table_xtal_up, (s8 **)&delta_swing_table_xtal_down);
+
+
+ cali_info->txpowertracking_callback_cnt++; /*cosa add for debug*/
+ cali_info->is_txpowertracking_init = true;
+
+ /*cali_info->txpowertrack_control = hal_data->txpowertrack_control;
+ We should keep updating the control variable according to HalData.
+ rf_calibrate_info.rega24 will be initialized when ODM HW configuring, but MP configures with para files. */
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+#if (MP_DRIVER == 1)
+ cali_info->rega24 = 0x090e1317;
+#endif
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+ if (*(dm->mp_mode) == true)
+ cali_info->rega24 = 0x090e1317;
+#endif
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "===>odm_txpowertracking_callback_thermal_meter\n cali_info->bb_swing_idx_cck_base: %d, cali_info->bb_swing_idx_ofdm_base[A]: %d, cali_info->default_ofdm_index: %d\n",
+ cali_info->bb_swing_idx_cck_base, cali_info->bb_swing_idx_ofdm_base[RF_PATH_A], cali_info->default_ofdm_index);
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "cali_info->txpowertrack_control=%d, hal_data->eeprom_thermal_meter %d\n", cali_info->txpowertrack_control, hal_data->eeprom_thermal_meter);
+ thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, c.thermal_reg_addr, 0xfc00); /* 0x42: RF Reg[15:10] 88E */
+
+ thermal_value_temp = thermal_value + phydm_get_thermal_offset(dm);
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "thermal_value_temp(%d) = thermal_value(%d) + power_time_thermal(%d)\n", thermal_value_temp, thermal_value, phydm_get_thermal_offset(dm));
+
+ if (thermal_value_temp > 63)
+ thermal_value = 63;
+ else if (thermal_value_temp < 0)
+ thermal_value = 0;
+ else
+ thermal_value = thermal_value_temp;
+
+ /*add log by zhao he, check c80/c94/c14/ca0 value*/
+ if (dm->support_ic_type == ODM_RTL8723D) {
+ regc80 = odm_get_bb_reg(dm, 0xc80, MASKDWORD);
+ regcd0 = odm_get_bb_reg(dm, 0xcd0, MASKDWORD);
+ regcd4 = odm_get_bb_reg(dm, 0xcd4, MASKDWORD);
+ regab4 = odm_get_bb_reg(dm, 0xab4, 0x000007FF);
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4);
+ }
+
+ /* JJ ADD 20161014 */
+ if (dm->support_ic_type == ODM_RTL8710B) {
+ regc80 = odm_get_bb_reg(dm, 0xc80, MASKDWORD);
+ regcd0 = odm_get_bb_reg(dm, 0xcd0, MASKDWORD);
+ regcd4 = odm_get_bb_reg(dm, 0xcd4, MASKDWORD);
+ regab4 = odm_get_bb_reg(dm, 0xab4, 0x000007FF);
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4);
+ }
+
+ if (!cali_info->txpowertrack_control)
+ return;
+
+ if (hal_data->eeprom_thermal_meter == 0xff) {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "no pg, hal_data->eeprom_thermal_meter = 0x%x\n", hal_data->eeprom_thermal_meter);
+ return;
+ }
+
+ /*4 3. Initialize ThermalValues of rf_calibrate_info*/
+
+ if (cali_info->is_reloadtxpowerindex)
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "reload ofdm index for band switch\n");
+
+ /*4 4. Calculate average thermal meter*/
+
+ cali_info->thermal_value_avg[cali_info->thermal_value_avg_index] = thermal_value;
+ cali_info->thermal_value_avg_index++;
+ if (cali_info->thermal_value_avg_index == c.average_thermal_num) /*Average times = c.average_thermal_num*/
+ cali_info->thermal_value_avg_index = 0;
+
+ for (i = 0; i < c.average_thermal_num; i++) {
+ if (cali_info->thermal_value_avg[i]) {
+ thermal_value_avg += cali_info->thermal_value_avg[i];
+ thermal_value_avg_count++;
+ }
+ }
+
+ if (thermal_value_avg_count) { /* Calculate Average thermal_value after average enough times */
+ thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);
+ cali_info->thermal_value_delta = thermal_value - hal_data->eeprom_thermal_meter;
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n", thermal_value, hal_data->eeprom_thermal_meter);
+ }
+
+ /* 4 5. Calculate delta, delta_LCK, delta_IQK. */
+
+ /* "delta" here is used to determine whether thermal value changes or not. */
+ delta = (thermal_value > cali_info->thermal_value) ? (thermal_value - cali_info->thermal_value) : (cali_info->thermal_value - thermal_value);
+ delta_LCK = (thermal_value > cali_info->thermal_value_lck) ? (thermal_value - cali_info->thermal_value_lck) : (cali_info->thermal_value_lck - thermal_value);
+ delta_IQK = (thermal_value > cali_info->thermal_value_iqk) ? (thermal_value - cali_info->thermal_value_iqk) : (cali_info->thermal_value_iqk - thermal_value);
+
+ if (cali_info->thermal_value_iqk == 0xff) { /*no PG, use thermal value for IQK*/
+ cali_info->thermal_value_iqk = thermal_value;
+ delta_IQK = (thermal_value > cali_info->thermal_value_iqk) ? (thermal_value - cali_info->thermal_value_iqk) : (cali_info->thermal_value_iqk - thermal_value);
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "no PG, use thermal_value for IQK\n");
+ }
+
+ for (p = RF_PATH_A; p < c.rf_path_count; p++)
+ diff_DPK[p] = (s8)thermal_value - (s8)cali_info->dpk_thermal[p];
+
+ /*4 6. If necessary, do LCK.*/
+
+ if (!(dm->support_ic_type & ODM_RTL8821)) { /*no PG, do LCK at initial status*/
+ if (cali_info->thermal_value_lck == 0xff) {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "no PG, do LCK\n");
+ cali_info->thermal_value_lck = thermal_value;
+
+ /*Use RTLCK, so close power tracking driver LCK*/
+ if ((!(dm->support_ic_type & ODM_RTL8814A)) && (!(dm->support_ic_type & ODM_RTL8822B))) {
+ if (c.phy_lc_calibrate)
+ (*c.phy_lc_calibrate)(dm);
+ }
+
+ delta_LCK = (thermal_value > cali_info->thermal_value_lck) ? (thermal_value - cali_info->thermal_value_lck) : (cali_info->thermal_value_lck - thermal_value);
+ }
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK);
+
+ /* Wait sacn to do LCK by RF Jenyu*/
+ if( (*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) {
+ /* Delta temperature is equal to or larger than 20 centigrade.*/
+ if (delta_LCK >= c.threshold_iqk) {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk);
+ cali_info->thermal_value_lck = thermal_value;
+
+ /*Use RTLCK, so close power tracking driver LCK*/
+ if ((!(dm->support_ic_type & ODM_RTL8814A)) && (!(dm->support_ic_type & ODM_RTL8822B))) {
+ if (c.phy_lc_calibrate)
+ (*c.phy_lc_calibrate)(dm);
+ }
+ }
+ }
+ }
+
+ /*3 7. If necessary, move the index of swing table to adjust Tx power.*/
+
+ if (delta > 0 && cali_info->txpowertrack_control) {
+ /* "delta" here is used to record the absolute value of differrence. */
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+ delta = thermal_value > hal_data->eeprom_thermal_meter ? (thermal_value - hal_data->eeprom_thermal_meter) : (hal_data->eeprom_thermal_meter - thermal_value);
+#else
+ delta = (thermal_value > dm->priv->pmib->dot11RFEntry.ther) ? (thermal_value - dm->priv->pmib->dot11RFEntry.ther) : (dm->priv->pmib->dot11RFEntry.ther - thermal_value);
+#endif
+ if (delta >= TXPWR_TRACK_TABLE_SIZE)
+ delta = TXPWR_TRACK_TABLE_SIZE - 1;
+
+ /*4 7.1 The Final Power index = BaseIndex + power_index_offset*/
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+ if (thermal_value > hal_data->eeprom_thermal_meter) {
+#else
+ if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) {
+#endif
+
+ for (p = RF_PATH_A; p < c.rf_path_count; p++) {
+ cali_info->delta_power_index_last[p] = cali_info->delta_power_index[p]; /*recording poer index offset*/
+ switch (p) {
+ case RF_PATH_B:
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta]);
+
+ cali_info->delta_power_index[p] = delta_swing_table_idx_tup_b[delta];
+ cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_b[delta]; /*Record delta swing for mix mode power tracking*/
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+ break;
+
+ case RF_PATH_C:
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "delta_swing_table_idx_tup_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta]);
+
+ cali_info->delta_power_index[p] = delta_swing_table_idx_tup_c[delta];
+ cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_c[delta]; /*Record delta swing for mix mode power tracking*/
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+ break;
+
+ case RF_PATH_D:
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "delta_swing_table_idx_tup_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta]);
+
+ cali_info->delta_power_index[p] = delta_swing_table_idx_tup_d[delta];
+ cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_d[delta]; /*Record delta swing for mix mode power tracking*/
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+ break;
+
+ default:
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta]);
+
+ cali_info->delta_power_index[p] = delta_swing_table_idx_tup_a[delta];
+ cali_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_a[delta]; /*Record delta swing for mix mode power tracking*/
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "******Temp is higher and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+ break;
+ }
+ }
+ /* JJ ADD 20161014 */
+ if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {
+ /*Save xtal_offset from Xtal table*/
+ cali_info->xtal_offset_last = cali_info->xtal_offset; /*recording last Xtal offset*/
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "[Xtal] delta_swing_table_xtal_up[%d] = %d\n", delta, delta_swing_table_xtal_up[delta]);
+ cali_info->xtal_offset = delta_swing_table_xtal_up[delta];
+
+ if (cali_info->xtal_offset_last == cali_info->xtal_offset)
+ xtal_offset_eanble = 0;
+ else
+ xtal_offset_eanble = 1;
+ }
+
+ } else {
+ for (p = RF_PATH_A; p < c.rf_path_count; p++) {
+ cali_info->delta_power_index_last[p] = cali_info->delta_power_index[p]; /*recording poer index offset*/
+
+ switch (p) {
+ case RF_PATH_B:
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta]);
+ cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_b[delta];
+ cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta]; /*Record delta swing for mix mode power tracking*/
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_B] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+ break;
+
+ case RF_PATH_C:
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "delta_swing_table_idx_tdown_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta]);
+ cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_c[delta];
+ cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_c[delta]; /*Record delta swing for mix mode power tracking*/
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_C] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+ break;
+
+ case RF_PATH_D:
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "delta_swing_table_idx_tdown_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta]);
+ cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_d[delta];
+ cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_d[delta]; /*Record delta swing for mix mode power tracking*/
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_D] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+ break;
+
+ default:
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta]);
+ cali_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_a[delta];
+ cali_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta]; /*Record delta swing for mix mode power tracking*/
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "******Temp is lower and cali_info->absolute_ofdm_swing_idx[RF_PATH_A] = %d\n", cali_info->absolute_ofdm_swing_idx[p]);
+ break;
+ }
+ }
+ /* JJ ADD 20161014 */
+ if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {
+ /*Save xtal_offset from Xtal table*/
+ cali_info->xtal_offset_last = cali_info->xtal_offset; /*recording last Xtal offset*/
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "[Xtal] delta_swing_table_xtal_down[%d] = %d\n", delta, delta_swing_table_xtal_down[delta]);
+ cali_info->xtal_offset = delta_swing_table_xtal_down[delta];
+
+ if (cali_info->xtal_offset_last == cali_info->xtal_offset)
+ xtal_offset_eanble = 0;
+ else
+ xtal_offset_eanble = 1;
+ }
+
+ }
+
+ for (p = RF_PATH_A; p < c.rf_path_count; p++) {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "\n\n=========================== [path-%d] Calculating power_index_offset===========================\n", p);
+
+ if (cali_info->delta_power_index[p] == cali_info->delta_power_index_last[p]) /*If Thermal value changes but lookup table value still the same*/
+ cali_info->power_index_offset[p] = 0;
+ else
+ cali_info->power_index_offset[p] = cali_info->delta_power_index[p] - cali_info->delta_power_index_last[p]; /*Power index diff between 2 times Power Tracking*/
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "[path-%d] power_index_offset(%d) = delta_power_index(%d) - delta_power_index_last(%d)\n", p, cali_info->power_index_offset[p], cali_info->delta_power_index[p], cali_info->delta_power_index_last[p]);
+
+ cali_info->OFDM_index[p] = cali_info->bb_swing_idx_ofdm_base[p] + cali_info->power_index_offset[p];
+ cali_info->CCK_index = cali_info->bb_swing_idx_cck_base + cali_info->power_index_offset[p];
+
+ cali_info->bb_swing_idx_cck = cali_info->CCK_index;
+ cali_info->bb_swing_idx_ofdm[p] = cali_info->OFDM_index[p];
+
+ /*************Print BB Swing base and index Offset*************/
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_cck, cali_info->bb_swing_idx_cck_base, cali_info->power_index_offset[p]);
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "The 'OFDM' final index(%d) = BaseIndex[%d](%d) + power_index_offset(%d)\n", cali_info->bb_swing_idx_ofdm[p], p, cali_info->bb_swing_idx_ofdm_base[p], cali_info->power_index_offset[p]);
+
+ /*4 7.1 Handle boundary conditions of index.*/
+
+ if (cali_info->OFDM_index[p] > c.swing_table_size_ofdm - 1)
+ cali_info->OFDM_index[p] = c.swing_table_size_ofdm - 1;
+ else if (cali_info->OFDM_index[p] <= OFDM_min_index)
+ cali_info->OFDM_index[p] = OFDM_min_index;
+ }
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "\n\n========================================================================================================\n");
+
+ if (cali_info->CCK_index > c.swing_table_size_cck - 1)
+ cali_info->CCK_index = c.swing_table_size_cck - 1;
+ else if (cali_info->CCK_index <= 0)
+ cali_info->CCK_index = 0;
+ } else {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "The thermal meter is unchanged or TxPowerTracking OFF(%d): thermal_value: %d, cali_info->thermal_value: %d\n",
+ cali_info->txpowertrack_control, thermal_value, cali_info->thermal_value);
+
+ for (p = RF_PATH_A; p < c.rf_path_count; p++)
+ cali_info->power_index_offset[p] = 0;
+ }
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n",
+ cali_info->CCK_index, cali_info->bb_swing_idx_cck_base); /*Print Swing base & current*/
+
+ for (p = RF_PATH_A; p < c.rf_path_count; p++) {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index[%d]: %d\n",
+ cali_info->OFDM_index[p], p, cali_info->bb_swing_idx_ofdm_base[p]);
+ }
+
+ if ((dm->support_ic_type & ODM_RTL8814A)) {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "power_tracking_type=%d\n", power_tracking_type);
+
+ if (power_tracking_type == 0) {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
+ for (p = RF_PATH_A; p < c.rf_path_count; p++)
+ (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
+ } else if (power_tracking_type == 1) {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX(2G) TSSI(5G) MODE**********\n");
+ for (p = RF_PATH_A; p < c.rf_path_count; p++)
+ (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_2G_TSSI_5G_MODE, p, 0);
+ } else if (power_tracking_type == 2) {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX(5G) TSSI(2G)MODE**********\n");
+ for (p = RF_PATH_A; p < c.rf_path_count; p++)
+ (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_5G_TSSI_2G_MODE, p, 0);
+ } else if (power_tracking_type == 3) {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking TSSI MODE**********\n");
+ for (p = RF_PATH_A; p < c.rf_path_count; p++)
+ (*c.odm_tx_pwr_track_set_pwr)(dm, TSSI_MODE, p, 0);
+ }
+ cali_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/
+
+ } else if ((cali_info->power_index_offset[RF_PATH_A] != 0 ||
+ cali_info->power_index_offset[RF_PATH_B] != 0 ||
+ cali_info->power_index_offset[RF_PATH_C] != 0 ||
+ cali_info->power_index_offset[RF_PATH_D] != 0) &&
+ cali_info->txpowertrack_control && (hal_data->eeprom_thermal_meter != 0xff)) {
+ /* 4 7.2 Configure the Swing Table to adjust Tx Power. */
+
+ cali_info->is_tx_power_changed = true; /*Always true after Tx Power is adjusted by power tracking.*/
+ /* */
+ /* 2012/04/23 MH According to Luke's suggestion, we can not write BB digital */
+ /* to increase TX power. Otherwise, EVM will be bad. */
+ /* */
+ /* 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. */
+ if (thermal_value > cali_info->thermal_value) {
+ for (p = RF_PATH_A; p < c.rf_path_count; p++) {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "Temperature Increasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
+ p, cali_info->power_index_offset[p], delta, thermal_value, hal_data->eeprom_thermal_meter, cali_info->thermal_value);
+ }
+ } else if (thermal_value < cali_info->thermal_value) { /*Low temperature*/
+ for (p = RF_PATH_A; p < c.rf_path_count; p++) {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "Temperature Decreasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
+ p, cali_info->power_index_offset[p], delta, thermal_value, hal_data->eeprom_thermal_meter, cali_info->thermal_value);
+ }
+ }
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ if (thermal_value > hal_data->eeprom_thermal_meter)
+#else
+ if (thermal_value > dm->priv->pmib->dot11RFEntry.ther)
+#endif
+ {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "Temperature(%d) higher than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter);
+
+ if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8821 ||
+ dm->support_ic_type == ODM_RTL8812 || dm->support_ic_type == ODM_RTL8723B || dm->support_ic_type == ODM_RTL8814A ||
+ dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8822B ||
+ dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
+ for (p = RF_PATH_A; p < c.rf_path_count; p++)
+ (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, 0);
+ } else {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
+ for (p = RF_PATH_A; p < c.rf_path_count; p++)
+ (*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel);
+ }
+ } else {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "Temperature(%d) lower than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter);
+
+ if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8821 ||
+ dm->support_ic_type == ODM_RTL8812 || dm->support_ic_type == ODM_RTL8723B || dm->support_ic_type == ODM_RTL8814A ||
+ dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8822B ||
+ dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8821C || dm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking MIX_MODE**********\n");
+ for (p = RF_PATH_A; p < c.rf_path_count; p++)
+ (*c.odm_tx_pwr_track_set_pwr)(dm, MIX_MODE, p, indexforchannel);
+ } else {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter POWER Tracking BBSWING_MODE**********\n");
+ for (p = RF_PATH_A; p < c.rf_path_count; p++)
+ (*c.odm_tx_pwr_track_set_pwr)(dm, BBSWING, p, indexforchannel);
+ }
+
+ }
+
+ cali_info->bb_swing_idx_cck_base = cali_info->bb_swing_idx_cck; /*Record last time Power Tracking result as base.*/
+ for (p = RF_PATH_A; p < c.rf_path_count; p++)
+ cali_info->bb_swing_idx_ofdm_base[p] = cali_info->bb_swing_idx_ofdm[p];
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "cali_info->thermal_value = %d thermal_value= %d\n", cali_info->thermal_value, thermal_value);
+
+ cali_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/
+
+ }
+
+
+ if (dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */
+
+ if (xtal_offset_eanble != 0 && cali_info->txpowertrack_control && (hal_data->eeprom_thermal_meter != 0xff)) {
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********Enter Xtal Tracking**********\n");
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ if (thermal_value > hal_data->eeprom_thermal_meter) {
+#else
+ if (thermal_value > dm->priv->pmib->dot11RFEntry.ther) {
+#endif
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "Temperature(%d) higher than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter);
+ (*c.odm_txxtaltrack_set_xtal)(dm);
+ } else {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "Temperature(%d) lower than PG value(%d)\n", thermal_value, hal_data->eeprom_thermal_meter);
+ (*c.odm_txxtaltrack_set_xtal)(dm);
+ }
+ }
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "**********End Xtal Tracking**********\n");
+ }
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+
+ /* Wait sacn to do IQK by RF Jenyu*/
+ if ((*dm->is_scan_in_process == false) && (!iqk_info->rfk_forbidden)) {
+ if (!IS_HARDWARE_TYPE_8723B(adapter)) {
+ /*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
+ if (delta_IQK >= c.threshold_iqk) {
+ cali_info->thermal_value_iqk = thermal_value;
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk);
+ if (!cali_info->is_iqk_in_progress)
+ (*c.do_iqk)(dm, delta_IQK, thermal_value, 8);
+ }
+ }
+ }
+ if (cali_info->dpk_thermal[RF_PATH_A] != 0) {
+ if (diff_DPK[RF_PATH_A] >= c.threshold_dpk) {
+ odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
+ odm_set_bb_reg(dm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_A] / c.threshold_dpk));
+ odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
+ } else if ((diff_DPK[RF_PATH_A] <= -1 * c.threshold_dpk)) {
+ s32 value = 0x20 + (diff_DPK[RF_PATH_A] / c.threshold_dpk);
+
+ odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
+ odm_set_bb_reg(dm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);
+ odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
+ } else {
+ odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
+ odm_set_bb_reg(dm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);
+ odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
+ }
+ }
+ if (cali_info->dpk_thermal[RF_PATH_B] != 0) {
+ if (diff_DPK[RF_PATH_B] >= c.threshold_dpk) {
+ odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
+ odm_set_bb_reg(dm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[RF_PATH_B] / c.threshold_dpk));
+ odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
+ } else if ((diff_DPK[RF_PATH_B] <= -1 * c.threshold_dpk)) {
+ s32 value = 0x20 + (diff_DPK[RF_PATH_B] / c.threshold_dpk);
+
+ odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
+ odm_set_bb_reg(dm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value);
+ odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
+ } else {
+ odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1);
+ odm_set_bb_reg(dm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0);
+ odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0);
+ }
+ }
+
+#endif
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "<===odm_txpowertracking_callback_thermal_meter\n");
+
+ cali_info->tx_powercount = 0;
+}
+
+
+
+/* 3============================================================
+ * 3 IQ Calibration
+ * 3============================================================ */
+
+void
+odm_reset_iqk_result(
+ struct dm_struct *dm
+)
+{
+ return;
+}
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+u8 odm_get_right_chnl_place_for_iqk(u8 chnl)
+{
+ u8 channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = {
+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, 161, 163, 165
+ };
+ u8 place = chnl;
+
+
+ if (chnl > 14) {
+ for (place = 14; place < sizeof(channel_all); place++) {
+ if (channel_all[place] == chnl)
+ return place - 13;
+ }
+ }
+ return 0;
+
+}
+#endif
+
+void
+odm_iq_calibrate(
+ struct dm_struct *dm
+)
+{
+ void *adapter = dm->adapter;
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+
+ RT_TRACE(COMP_SCAN, ODM_DBG_LOUD, ("=>%s\n" , __FUNCTION__));
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+ if (*dm->is_fcs_mode_enable)
+ return;
+#endif
+
+ if ((dm->is_linked) && (!iqk_info->rfk_forbidden)) {
+ RT_TRACE(COMP_SCAN, ODM_DBG_LOUD, ("interval=%d ch=%d prech=%d scan=%s\n", dm->linked_interval,
+ *dm->channel, dm->pre_channel, *dm->is_scan_in_process == TRUE ? "TRUE":"FALSE"));
+
+ if (*dm->channel != dm->pre_channel) {
+ dm->pre_channel = *dm->channel;
+ dm->linked_interval = 0;
+ }
+
+ if ((dm->linked_interval < 3) && (!*dm->is_scan_in_process))
+ dm->linked_interval++;
+
+ if (dm->linked_interval == 2)
+ PHY_IQCalibrate((PADAPTER)adapter, false);
+ } else
+ dm->linked_interval = 0;
+
+ RT_TRACE(COMP_SCAN, ODM_DBG_LOUD, ("<=%s interval=%d ch=%d prech=%d scan=%s\n", __FUNCTION__, dm->linked_interval,
+ *dm->channel, dm->pre_channel, *dm->is_scan_in_process == TRUE?"TRUE":"FALSE"));
+}
+
+void phydm_rf_init(struct dm_struct *dm)
+{
+
+ odm_txpowertracking_init(dm);
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+ odm_clear_txpowertracking_state(dm);
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+#if (RTL8814A_SUPPORT == 1)
+ if (dm->support_ic_type & ODM_RTL8814A)
+ phy_iq_calibrate_8814a_init(dm);
+#endif
+#endif
+
+}
+
+void phydm_rf_watchdog(struct dm_struct *dm)
+{
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+ odm_txpowertracking_check(dm);
+ if (dm->support_ic_type & ODM_IC_11AC_SERIES)
+ odm_iq_calibrate(dm);
+#endif
+}
diff --git a/hal/phydm/halrf/halphyrf_win.h b/hal/phydm/halrf/halphyrf_win.h
new file mode 100644
index 0000000..0d36a75
--- /dev/null
+++ b/hal/phydm/halrf/halphyrf_win.h
@@ -0,0 +1,135 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#ifndef __HAL_PHY_RF_H__
+#define __HAL_PHY_RF_H__
+
+#if (RTL8814A_SUPPORT == 1)
+ #if RT_PLATFORM == PLATFORM_MACOSX
+ #include "rtl8814a/halrf_iqk_8814a.h"
+ #else
+ #include "halrf/rtl8814a/halrf_iqk_8814a.h"
+ #endif
+#endif
+
+#if (RTL8822B_SUPPORT == 1)
+ #if RT_PLATFORM == PLATFORM_MACOSX
+ #include "rtl8822b/halrf_iqk_8822b.h"
+ #include "../../MAC/Halmac_type.h"
+ #else
+ #include "halrf/rtl8822b/halrf_iqk_8822b.h"
+ #include "../mac/Halmac_type.h"
+ #endif
+#endif
+
+#if RT_PLATFORM == PLATFORM_MACOSX
+ #include "halrf_powertracking_win.h"
+ #include "halrf_kfree.h"
+ #include "halrf_txgapcal.h"
+#else
+ #include "halrf/halrf_powertracking_win.h"
+ #include "halrf/halrf_kfree.h"
+ #include "halrf/halrf_txgapcal.h"
+#endif
+
+#if (RTL8821C_SUPPORT == 1)
+ #if RT_PLATFORM == PLATFORM_MACOSX
+ #include "rtl8821c/halrf_iqk_8821c.h"
+ #else
+ #include "halrf/rtl8821c/halrf_iqk_8821c.h"
+ #endif
+#endif
+
+enum spur_cal_method {
+ PLL_RESET,
+ AFE_PHASE_SEL
+};
+
+enum pwrtrack_method {
+ BBSWING,
+ TXAGC,
+ MIX_MODE,
+ TSSI_MODE,
+ MIX_2G_TSSI_5G_MODE,
+ MIX_5G_TSSI_2G_MODE
+};
+
+typedef void(*func_set_pwr)(void *, enum pwrtrack_method, u8, u8);
+typedef void(*func_iqk)(void *, u8, u8, u8);
+typedef void(*func_lck)(void *);
+typedef void(*func_swing)(void *, u8 **, u8 **, u8 **, u8 **);
+typedef void(*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **);
+typedef void (*func_swing_xtal)(void *, s8 **, s8 **);
+typedef void (*func_set_xtal)(void *);
+typedef void(*func_all_swing)(void *, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **);
+
+struct txpwrtrack_cfg {
+ u8 swing_table_size_cck;
+ u8 swing_table_size_ofdm;
+ u8 threshold_iqk;
+ u8 threshold_dpk;
+ u8 average_thermal_num;
+ u8 rf_path_count;
+ u32 thermal_reg_addr;
+ func_set_pwr odm_tx_pwr_track_set_pwr;
+ func_iqk do_iqk;
+ func_lck phy_lc_calibrate;
+ func_swing get_delta_swing_table;
+ func_swing8814only get_delta_swing_table8814only;
+ func_swing_xtal get_delta_swing_xtal_table;
+ func_set_xtal odm_txxtaltrack_set_xtal;
+ func_all_swing get_delta_all_swing_table;
+};
+
+void
+configure_txpower_track(
+ struct dm_struct *dm,
+ struct txpwrtrack_cfg *config
+);
+
+
+void
+odm_clear_txpowertracking_state(
+ struct dm_struct *dm
+);
+
+void
+odm_txpowertracking_callback_thermal_meter(
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ struct dm_struct *dm
+#else
+ void *adapter
+#endif
+);
+
+
+
+#define ODM_TARGET_CHNL_NUM_2G_5G 59
+
+
+void
+odm_reset_iqk_result(
+ struct dm_struct *dm
+);
+u8
+odm_get_right_chnl_place_for_iqk(
+ u8 chnl
+);
+
+void odm_iq_calibrate(struct dm_struct *dm);
+void phydm_rf_init(struct dm_struct *dm);
+void phydm_rf_watchdog(struct dm_struct *dm);
+
+#endif /* #ifndef __HAL_PHY_RF_H__ */
diff --git a/hal/phydm/halrf/halrf.c b/hal/phydm/halrf/halrf.c
new file mode 100644
index 0000000..9760014
--- /dev/null
+++ b/hal/phydm/halrf/halrf.c
@@ -0,0 +1,1575 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger
+ *
+ *****************************************************************************/
+
+/* ************************************************************
+ * include files
+ * ************************************************************ */
+
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+void halrf_basic_profile(
+ void *dm_void,
+ u32 *_used,
+ char *output,
+ u32 *_out_len
+)
+{
+#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ u32 used = *_used;
+ u32 out_len = *_out_len;
+
+ /* HAL RF version List */
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "%-35s\n", "% HAL RF version %");
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ " %-35s: %s\n", "Power Tracking",
+ HALRF_POWRTRACKING_VER);
+
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ " %-35s: %s %s\n", "IQK",
+ (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD)? "FW" : HALRF_IQK_VER,
+ (halrf_match_iqk_version(dm_void))? "(match)" : "(mismatch)");
+
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ " %-35s: %s\n", "LCK", HALRF_LCK_VER);
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ " %-35s: %s\n", "DPK", HALRF_DPK_VER);
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ " %-35s: %s\n", "KFREE", HALRF_KFREE_VER);
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ " %-35s: %s\n", "TX 2G Current Calibration",
+ HALRF_PABIASK_VER);
+
+ *_used = used;
+ *_out_len = out_len;
+#endif
+}
+
+#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
+void
+_iqk_page_switch(
+ void *dm_void)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ if (dm->support_ic_type == ODM_RTL8821C)
+ odm_write_4byte(dm, 0x1b00, 0xf8000008);
+ else
+ odm_write_4byte(dm, 0x1b00, 0xf800000a);
+}
+
+u32 halrf_psd_log2base(u32 val)
+{
+ u8 j;
+ u32 tmp, tmp2, val_integerd_b = 0, tindex, shiftcount = 0;
+ u32 result, val_fractiond_b = 0, table_fraction[21] = {0, 432, 332, 274, 232, 200,
+ 174, 151, 132, 115, 100, 86, 74, 62, 51, 42,
+ 32, 23, 15, 7, 0
+ };
+
+ if (val == 0)
+ return 0;
+
+ tmp = val;
+
+ while (1) {
+ if (tmp == 1)
+ break;
+
+ tmp = (tmp >> 1);
+ shiftcount++;
+ }
+
+
+ val_integerd_b = shiftcount + 1;
+
+ tmp2 = 1;
+ for (j = 1; j <= val_integerd_b; j++)
+ tmp2 = tmp2 * 2;
+
+ tmp = (val * 100) / tmp2;
+ tindex = tmp / 5;
+
+ if (tindex > 20)
+ tindex = 20;
+
+ val_fractiond_b = table_fraction[tindex];
+
+ result = val_integerd_b * 100 - val_fractiond_b;
+
+ return result;
+
+
+}
+
+void phydm_get_iqk_cfir(
+ void *dm_void,
+ u8 idx,
+ u8 path,
+ boolean debug
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+
+ u8 i, ch;
+ u32 tmp;
+
+ if (debug)
+ ch = 2;
+ else
+ ch = 0;
+ odm_set_bb_reg(dm, 0x1b00, MASKDWORD, 0xf8000008 | path << 1);
+ if (idx == 0)
+ odm_set_bb_reg(dm, 0x1b0c, BIT(13) | BIT(12), 0x3);
+ else
+ odm_set_bb_reg(dm, 0x1b0c, BIT(13) | BIT(12), 0x1);
+ odm_set_bb_reg(dm, 0x1bd4, BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16), 0x10);
+ for (i = 0; i < 8; i++) {
+ odm_set_bb_reg(dm, 0x1bd8, MASKDWORD, 0xe0000001 + (i * 4));
+ tmp = odm_get_bb_reg(dm, 0x1bfc, MASKDWORD);
+ iqk_info->iqk_cfir_real[ch][path][idx][i] = (tmp & 0x0fff0000) >> 16;
+ iqk_info->iqk_cfir_imag[ch][path][idx][i] = tmp & 0xfff;
+ }
+ odm_set_bb_reg(dm, 0x1bd8, MASKDWORD, 0x0);
+ odm_set_bb_reg(dm, 0x1b0c, BIT(13) | BIT(12), 0x0);
+}
+
+void
+halrf_iqk_xym_enable(
+ struct dm_struct *dm,
+ u8 xym_enable
+ )
+{
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+
+ if (xym_enable == 0)
+ iqk_info->xym_read = false;
+ else
+ iqk_info->xym_read = true;
+
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]%-20s %s\n", "xym_read = ", (iqk_info->xym_read ? "true": "false"));
+}
+
+void
+halrf_iqk_xym_read(
+ void *dm_void,
+ u8 path,
+ u8 xym_type /*0: rx_sym; 1: tx_xym; 2:gs1_xym; 3:gs2_sym; 4: rxk1_xym*/
+ )
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+ u8 i, start, num;
+ u32 tmp1, tmp2;
+
+ if (!iqk_info->xym_read)
+ return;
+
+ if (*dm->band_width == 0) {
+ start = 3;
+ num = 4;
+ }else if (*dm->band_width == 1) {
+ start = 2;
+ num = 6;
+ }else {
+ start = 0;
+ num = 10;
+ }
+
+ odm_write_4byte(dm, 0x1b00, 0xf8000008);
+ tmp1 = odm_read_4byte(dm, 0x1b1c);
+ odm_write_4byte(dm, 0x1b1c, 0xa2193c32);
+
+ odm_write_4byte(dm, 0x1b00, 0xf800000a);
+ tmp2 = odm_read_4byte(dm, 0x1b1c);
+ odm_write_4byte(dm, 0x1b1c, 0xa2193c32);
+
+ for (path = 0; path < 2; path ++) {
+ odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
+ switch(xym_type){
+ case 0:
+ for (i = 0; i < num ;i++) {
+ odm_write_4byte(dm, 0x1b14, 0xe6+start+i);
+ odm_write_4byte(dm, 0x1b14, 0x0);
+ iqk_info->rx_xym[path][i] = odm_read_4byte(dm, 0x1b38);
+ }
+ break;
+ case 1:
+ for (i = 0; i < num ;i++) {
+ odm_write_4byte(dm, 0x1b14, 0xe6+start+i);
+ odm_write_4byte(dm, 0x1b14, 0x0);
+ iqk_info->tx_xym[path][i] = odm_read_4byte(dm, 0x1b38);
+ }
+ break;
+ case 2:
+ for (i = 0; i < 6 ;i++) {
+ odm_write_4byte(dm, 0x1b14, 0xe0+i);
+ odm_write_4byte(dm, 0x1b14, 0x0);
+ iqk_info->gs1_xym[path][i] = odm_read_4byte(dm, 0x1b38);
+ }
+ break;
+ case 3:
+ for (i = 0; i < 6 ;i++) {
+ odm_write_4byte(dm, 0x1b14, 0xe0+i);
+ odm_write_4byte(dm, 0x1b14, 0x0);
+ iqk_info->gs2_xym[path][i] = odm_read_4byte(dm, 0x1b38);
+ }
+ break;
+ case 4:
+ for (i = 0; i < 6 ;i++) {
+ odm_write_4byte(dm, 0x1b14, 0xe0+i);
+ odm_write_4byte(dm, 0x1b14, 0x0);
+ iqk_info->rxk1_xym[path][i] = odm_read_4byte(dm, 0x1b38);
+ }
+ break;
+
+ }
+ odm_write_4byte(dm, 0x1b38, 0x20000000);
+ odm_write_4byte(dm, 0x1b00, 0xf8000008);
+ odm_write_4byte(dm, 0x1b1c, tmp1);
+ odm_write_4byte(dm, 0x1b00, 0xf800000a);
+ odm_write_4byte(dm, 0x1b1c, tmp2);
+ _iqk_page_switch(dm);
+ }
+}
+
+void halrf_iqk_xym_show(
+ struct dm_struct *dm,
+ u8 xym_type /*0: rx_sym; 1: tx_xym; 2:gs1_xym; 3:gs2_sym; 4: rxk1_xym*/
+ )
+{
+ u8 num, path, path_num, i;
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+
+ if (dm->rf_type ==RF_1T1R)
+ path_num = 0x1;
+ else if (dm->rf_type ==RF_2T2R)
+ path_num = 0x2;
+ else
+ path_num = 0x4;
+
+ if (*dm->band_width == CHANNEL_WIDTH_20)
+ num = 4;
+ else if (*dm->band_width == CHANNEL_WIDTH_40)
+ num = 6;
+ else
+ num = 10;
+
+ for (path = 0; path < path_num; path ++) {
+ switch (xym_type){
+ case 0:
+ for (i = 0 ; i < num; i ++)
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]%-20s %-2d: 0x%x\n",
+ (path == 0) ? "PATH A RX-XYM ": "PATH B RX-XYM", i, iqk_info->rx_xym[path][i]);
+ break;
+ case 1:
+ for (i = 0 ; i < num; i ++)
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]%-20s %-2d: 0x%x\n",
+ (path == 0) ? "PATH A TX-XYM ": "PATH B TX-XYM", i, iqk_info->tx_xym[path][i]);
+ break;
+ case 2:
+ for (i = 0 ; i < 6; i ++)
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]%-20s %-2d: 0x%x\n",
+ (path == 0) ? "PATH A GS1-XYM ": "PATH B GS1-XYM", i, iqk_info->gs1_xym[path][i]);
+ break;
+ case 3:
+ for (i = 0 ; i < 6; i ++)
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]%-20s %-2d: 0x%x\n",
+ (path == 0) ? "PATH A GS2-XYM ": "PATH B GS2-XYM", i, iqk_info->gs2_xym[path][i]);
+ break;
+ case 4:
+ for (i = 0 ; i < 6; i ++)
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]%-20s %-2d: 0x%x\n",
+ (path == 0) ? "PATH A RXK1-XYM ": "PATH B RXK1-XYM", i, iqk_info->rxk1_xym[path][i]);
+ break;
+ }
+ }
+}
+
+
+void
+halrf_iqk_xym_dump(
+ void *dm_void
+ )
+{
+ u32 tmp1, tmp2;
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+ odm_write_4byte(dm, 0x1b00, 0xf8000008);
+ tmp1 = odm_read_4byte(dm, 0x1b1c);
+ odm_write_4byte(dm, 0x1b00, 0xf800000a);
+ tmp2 = odm_read_4byte(dm, 0x1b1c);
+ /*halrf_iqk_xym_read(dm, xym_type);*/
+ odm_write_4byte(dm, 0x1b00, 0xf8000008);
+ odm_write_4byte(dm, 0x1b1c, tmp1);
+ odm_write_4byte(dm, 0x1b00, 0xf800000a);
+ odm_write_4byte(dm, 0x1b1c, tmp2);
+ _iqk_page_switch(dm);
+}
+
+void halrf_iqk_info_dump(
+ void *dm_void,
+ u32 *_used,
+ char *output,
+ u32 *_out_len)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ u32 used = *_used;
+ u32 out_len = *_out_len;
+ u8 path, num, i;
+
+ u8 rf_path, j, reload_iqk = 0;
+ u32 tmp;
+ boolean iqk_result[2][NUM][2]; /*two channel, PATH, TX/RX, 0:pass 1 :fail*/
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+
+ /* IQK INFO */
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "%-20s\n", "% IQK Info %");
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "%-20s\n",
+ (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? "FW-IQK" : "Driver-IQK");
+
+ reload_iqk = (u8)odm_get_bb_reg(dm, 0x1bf0, BIT(16));
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "%-20s: %s\n",
+ "reload", (reload_iqk) ? "True" : "False");
+
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "%-20s: %s\n",
+ "rfk_forbidden", (iqk_info->rfk_forbidden) ? "True" : "False");
+#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "%-20s: %s\n",
+ "segment_iqk", (iqk_info->segment_iqk) ? "True" : "False");
+#endif
+
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "%-20s:%d %d\n",
+ "iqk count / fail count", dm->n_iqk_cnt, dm->n_iqk_fail_cnt);
+
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "%-20s: %d\n",
+ "channel", *dm->channel);
+
+ if (*dm->band_width == CHANNEL_WIDTH_20)
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "%-20s: %s\n",
+ "bandwidth", "BW_20");
+ else if (*dm->band_width == CHANNEL_WIDTH_40)
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "%-20s: %s\n",
+ "bandwidth", "BW_40");
+ else if (*dm->band_width == CHANNEL_WIDTH_80)
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "%-20s: %s\n",
+ "bandwidth", "BW_80");
+ else if (*dm->band_width == CHANNEL_WIDTH_160)
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "%-20s: %s\n",
+ "bandwidth", "BW_160");
+ else
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "%-20s: %s\n",
+ "bandwidth", "BW_UNKNOW");
+
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "%-20s: %llu %s\n",
+ "progressing_time", dm->rf_calibrate_info.iqk_total_progressing_time, "(ms)");
+
+ tmp = odm_read_4byte(dm, 0x1bf0);
+ for(rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++)
+ for(j = 0; j < 2; j++)
+ iqk_result[0][rf_path][j] = (boolean)(tmp & BIT(rf_path + (j * 4)) >> (rf_path + (j * 4)));
+
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "%-20s: 0x%08x\n","Reg0x1bf0", tmp);
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "%-20s: %s\n",
+ "PATH_A-Tx result", (iqk_result[0][RF_PATH_A][0]) ? "Fail" : "Pass");
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "%-20s: %s\n",
+ "PATH_A-Rx result", (iqk_result[0][RF_PATH_A][1]) ? "Fail" : "Pass");
+#if (RTL8822B_SUPPORT == 1)
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "%-20s: %s\n",
+ "PATH_B-Tx result", (iqk_result[0][RF_PATH_B][0]) ? "Fail" : "Pass");
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "%-20s: %s\n",
+ "PATH_B-Rx result", (iqk_result[0][RF_PATH_B][1]) ? "Fail" : "Pass");
+#endif
+ *_used = used;
+ *_out_len = out_len;
+
+}
+
+void halrf_get_fw_version(void *dm_void)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct _hal_rf_ *rf = &dm->rf_table;
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+ {
+ void *adapter = dm->adapter;
+
+ rf->fw_ver = (((PADAPTER)adapter)->MgntInfo.FirmwareVersion << 16) | ((PADAPTER)adapter)->MgntInfo.FirmwareSubVersion;
+ }
+#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ {
+ struct rtl8192cd_priv *priv = dm->priv;
+
+ rf->fw_ver = (priv->pshare->fw_version << 16) | priv->pshare->fw_sub_version;
+ }
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
+ {
+ struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
+ struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
+
+ rf->fw_ver = (rtlhal->fw_version << 16) | rtlhal->fw_subversion;
+ }
+#else
+ {
+ void *adapter = dm->adapter;
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+
+ rf->fw_ver = (hal_data->firmware_version << 16) | hal_data->firmware_sub_version;
+ }
+#endif
+}
+
+
+
+void halrf_iqk_dbg(void *dm_void)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ u8 rf_path, j, reload_iqk = 0;
+ u8 path, num, i;
+ u32 tmp;
+ boolean iqk_result[2][NUM][2]; /*two channel, PATH, TX/RX, 0:pass 1 :fail*/
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+ struct _hal_rf_ *rf = &dm->rf_table;
+
+ /* IQK INFO */
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s\n", "====== IQK Info ======");
+
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s\n",
+ (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? "FW-IQK" : "Driver-IQK");
+
+ if (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) {
+ halrf_get_fw_version(dm);
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: 0x%x\n",
+ "FW_VER", rf->fw_ver);
+ } else
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: %s\n",
+ "IQK_VER", HALRF_IQK_VER);
+
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"%-20s: %s\n",
+ "reload", (iqk_info->is_reload) ? "True" : "False");
+
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: %d %d\n",
+ "iqk count / fail count", dm->n_iqk_cnt, dm->n_iqk_fail_cnt);
+
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: %d\n",
+ "channel", *dm->channel);
+
+ if (*dm->band_width == CHANNEL_WIDTH_20)
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: %s\n",
+ "bandwidth", "BW_20");
+ else if (*dm->band_width == CHANNEL_WIDTH_40)
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: %s\n",
+ "bandwidth", "BW_40");
+ else if (*dm->band_width == CHANNEL_WIDTH_80)
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: %s\n",
+ "bandwidth", "BW_80");
+ else if (*dm->band_width == CHANNEL_WIDTH_160)
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: %s\n",
+ "bandwidth", "BW_160");
+ else
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: %s\n",
+ "bandwidth", "BW_UNKNOW");
+/*
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: %llu %s\n",
+ "progressing_time", dm->rf_calibrate_info.iqk_total_progressing_time, "(ms)");
+*/
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: %s\n",
+ "rfk_forbidden", (iqk_info->rfk_forbidden) ? "True" : "False");
+#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: %s\n",
+ "segment_iqk", (iqk_info->segment_iqk) ? "True" : "False");
+#endif
+
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: %llu %s\n",
+ "progressing_time", dm->rf_calibrate_info.iqk_progressing_time, "(ms)");
+
+
+
+
+ tmp = odm_read_4byte(dm, 0x1bf0);
+ for(rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++)
+ for(j = 0; j < 2; j++)
+ iqk_result[0][rf_path][j] = (boolean)(tmp & BIT(rf_path + (j * 4)) >> (rf_path + (j * 4)));
+
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: 0x%08x\n", "Reg0x1bf0", tmp);
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: 0x%08x\n", "Reg0x1be8", odm_read_4byte(dm, 0x1be8));
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: %s\n",
+ "PATH_A-Tx result", (iqk_result[0][RF_PATH_A][0]) ? "Fail" : "Pass");
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: %s\n",
+ "PATH_A-Rx result", (iqk_result[0][RF_PATH_A][1]) ? "Fail" : "Pass");
+#if (RTL8822B_SUPPORT == 1)
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: %s\n",
+ "PATH_B-Tx result", (iqk_result[0][RF_PATH_B][0]) ? "Fail" : "Pass");
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: %s\n",
+ "PATH_B-Rx result", (iqk_result[0][RF_PATH_B][1]) ? "Fail" : "Pass");
+#endif
+
+
+}
+void halrf_lck_dbg(struct dm_struct *dm)
+{
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s\n", "====== LCK Info ======");
+ /*PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s\n",
+ (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? "LCK" : "RTK"));*/
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "%-20s: %llu %s\n",
+ "progressing_time", dm->rf_calibrate_info.lck_progressing_time, "(ms)");
+}
+
+void
+halrf_iqk_dbg_cfir_backup(struct dm_struct *dm)
+{
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+ u8 path, idx, i;
+
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]%-20s\n", "backup TX/RX CFIR");
+
+ for (path = 0; path < 2; path ++) {
+ for (idx = 0; idx < 2; idx++) {
+ phydm_get_iqk_cfir(dm, idx, path, true);
+ }
+ }
+
+ for (path = 0; path < 2; path ++) {
+ for (idx = 0; idx < 2; idx++) {
+ for(i = 0; i < 8; i++) {
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]%-7s %-3s CFIR_real: %-2d: 0x%x\n",
+ (path == 0) ? "PATH A": "PATH B", (idx == 0) ? "TX": "RX", i, iqk_info->iqk_cfir_real[2][path][idx][i]);
+ }
+ for(i = 0; i < 8; i++) {
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]%-7s %-3s CFIR_img:%-2d: 0x%x\n",
+ (path == 0) ? "PATH A": "PATH B", (idx == 0) ? "TX": "RX", i, iqk_info->iqk_cfir_imag[2][path][idx][i]);
+ }
+ }
+ }
+}
+
+
+void
+halrf_iqk_dbg_cfir_backup_update(
+ struct dm_struct *dm
+)
+{
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+ u8 i, path, idx;
+
+ if(iqk_info->iqk_cfir_real[2][0][0][0] == 0) {
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]%-20s\n", "CFIR is invalid");
+ return;
+ }
+ for (path = 0; path < 2; path++) {
+ for (idx = 0; idx < 2; idx++) {
+ odm_set_bb_reg(dm, 0x1b00, MASKDWORD, 0xf8000008 | path << 1);
+ odm_set_bb_reg(dm, 0x1b2c, MASKDWORD, 0x7);
+ odm_set_bb_reg(dm, 0x1b38, MASKDWORD, 0x20000000);
+ odm_set_bb_reg(dm, 0x1b3c, MASKDWORD, 0x20000000);
+ odm_set_bb_reg(dm, 0x1bcc, MASKDWORD, 0x00000000);
+ if (idx == 0)
+ odm_set_bb_reg(dm, 0x1b0c, BIT(13) | BIT(12), 0x3);
+ else
+ odm_set_bb_reg(dm, 0x1b0c, BIT(13) | BIT(12), 0x1);
+ odm_set_bb_reg(dm, 0x1bd4, BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16), 0x10);
+ for (i = 0; i < 8; i++) {
+ odm_write_4byte(dm, 0x1bd8, ((0xc0000000 >> idx) + 0x3) + (i * 4) + (iqk_info->iqk_cfir_real[2][path][idx][i] << 9));
+ odm_write_4byte(dm, 0x1bd8, ((0xc0000000 >> idx) + 0x1) + (i * 4) + (iqk_info->iqk_cfir_imag[2][path][idx][i] << 9));
+ /*odm_write_4byte(dm, 0x1bd8, iqk_info->iqk_cfir_real[2][path][idx][i]);*/
+ /*odm_write_4byte(dm, 0x1bd8, iqk_info->iqk_cfir_imag[2][path][idx][i]);*/
+ }
+ }
+ odm_set_bb_reg(dm, 0x1bd8, MASKDWORD, 0x0);
+ odm_set_bb_reg(dm, 0x1b0c, BIT(13) | BIT(12), 0x0);
+ }
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]%-20s\n", "update new CFIR");
+}
+
+
+void
+halrf_iqk_dbg_cfir_reload(
+ struct dm_struct *dm
+)
+{
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+ u8 i, path, idx;
+
+ if(iqk_info->iqk_cfir_real[0][0][0][0] == 0) {
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]%-20s\n", "CFIR is invalid");
+ return;
+ }
+ for (path = 0; path < 2; path++) {
+ for (idx = 0; idx < 2; idx++) {
+ odm_set_bb_reg(dm, 0x1b00, MASKDWORD, 0xf8000008 | path << 1);
+ odm_set_bb_reg(dm, 0x1b2c, MASKDWORD, 0x7);
+ odm_set_bb_reg(dm, 0x1b38, MASKDWORD, 0x20000000);
+ odm_set_bb_reg(dm, 0x1b3c, MASKDWORD, 0x20000000);
+ odm_set_bb_reg(dm, 0x1bcc, MASKDWORD, 0x00000000);
+ if (idx == 0)
+ odm_set_bb_reg(dm, 0x1b0c, BIT(13) | BIT(12), 0x3);
+ else
+ odm_set_bb_reg(dm, 0x1b0c, BIT(13) | BIT(12), 0x1);
+ odm_set_bb_reg(dm, 0x1bd4, BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16), 0x10);
+ for (i = 0; i < 8; i++) {
+ /*odm_write_4byte(dm, 0x1bd8, iqk_info->iqk_cfir_real[0][path][idx][i]);*/
+ /*odm_write_4byte(dm, 0x1bd8, iqk_info->iqk_cfir_imag[0][path][idx][i]);*/
+ odm_write_4byte(dm, 0x1bd8, ((0xc0000000 >> idx) + 0x3) + (i * 4) + (iqk_info->iqk_cfir_real[0][path][idx][i] << 9));
+ odm_write_4byte(dm, 0x1bd8, ((0xc0000000 >> idx) + 0x1) + (i * 4) + (iqk_info->iqk_cfir_imag[0][path][idx][i] << 9));
+ }
+ }
+ odm_set_bb_reg(dm, 0x1bd8, MASKDWORD, 0x0);
+ odm_set_bb_reg(dm, 0x1b0c, BIT(13) | BIT(12), 0x0);
+ }
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]%-20s\n", "write CFIR with default value");
+}
+
+void
+halrf_iqk_dbg_cfir_write(
+ struct dm_struct *dm,
+ u8 type,
+ u32 path,
+ u32 idx,
+ u32 i,
+ u32 data
+)
+{
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+ if (type == 0)
+ iqk_info->iqk_cfir_real[2][path][idx][i] = data;
+ else
+ iqk_info->iqk_cfir_imag[2][path][idx][i] = data;
+}
+
+void
+halrf_iqk_dbg_cfir_backup_show(struct dm_struct *dm)
+{
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+ u8 path, idx, i;
+
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]%-20s\n", "backup TX/RX CFIR");
+
+ for (path = 0; path < 2; path ++) {
+ for (idx = 0; idx < 2; idx++) {
+ for(i = 0; i < 8; i++) {
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]%-10s %-3s CFIR_real: %-2d: 0x%x\n",
+ (path == 0) ? "PATH A": "PATH B", (idx == 0) ? "TX": "RX", i, iqk_info->iqk_cfir_real[2][path][idx][i]);
+ }
+ for(i = 0; i < 8; i++) {
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]%-10s %-3s CFIR_img:%-2d: 0x%x\n",
+ (path == 0) ? "PATH A": "PATH B", (idx == 0) ? "TX": "RX", i, iqk_info->iqk_cfir_imag[2][path][idx][i]);
+ }
+ }
+ }
+}
+
+void
+halrf_do_imr_test(
+ void *dm_void,
+ u8 flag_imr_test
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+ if (flag_imr_test != 0x0)
+ switch (dm->support_ic_type) {
+#if (RTL8822B_SUPPORT == 1)
+ case ODM_RTL8822B:
+ do_imr_test_8822b(dm);
+ break;
+#endif
+#if (RTL8821C_SUPPORT == 1)
+ case ODM_RTL8821C:
+ do_imr_test_8821c(dm);
+ break;
+#endif
+ default:
+ break;
+ }
+}
+
+void halrf_iqk_debug(
+ void *dm_void,
+ u32 *const dm_value,
+ u32 *_used,
+ char *output,
+ u32 *_out_len
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+
+ /*dm_value[0]=0x0: backup from SRAM & show*/
+ /*dm_value[0]=0x1: write backup CFIR to SRAM*/
+ /*dm_value[0]=0x2: reload default CFIR to SRAM*/
+ /*dm_value[0]=0x3: show backup*/
+ /*dm_value[0]=0x10: write backup CFIR real part*/
+ /*--> dm_value[1]:path, dm_value[2]:tx/rx, dm_value[3]:index, dm_value[4]:data*/
+ /*dm_value[0]=0x11: write backup CFIR imag*/
+ /*--> dm_value[1]:path, dm_value[2]:tx/rx, dm_value[3]:index, dm_value[4]:data*/
+ /*dm_value[0]=0x20 :xym_read enable*/
+ /*--> dm_value[1]:0:disable, 1:enable*/
+ /*if dm_value[0]=0x20 = enable, */
+ /*0x1:show rx_sym; 0x2: tx_xym; 0x3:gs1_xym; 0x4:gs2_sym; 0x5:rxk1_xym*/
+
+ if (dm_value[0] == 0x0)
+ halrf_iqk_dbg_cfir_backup(dm);
+ else if (dm_value[0] == 0x1)
+ halrf_iqk_dbg_cfir_backup_update(dm);
+ else if (dm_value[0] == 0x2)
+ halrf_iqk_dbg_cfir_reload(dm);
+ else if (dm_value[0] == 0x3)
+ halrf_iqk_dbg_cfir_backup_show(dm);
+ else if (dm_value[0] == 0x10)
+ halrf_iqk_dbg_cfir_write(dm, 0, dm_value[1], dm_value[2], dm_value[3], dm_value[4]);
+ else if (dm_value[0] == 0x11)
+ halrf_iqk_dbg_cfir_write(dm, 1, dm_value[1], dm_value[2], dm_value[3], dm_value[4]);
+ else if (dm_value[0] == 0x20)
+ halrf_iqk_xym_enable(dm, (u8)dm_value[1]);
+ else if (dm_value[0] == 0x21)
+ halrf_iqk_xym_show(dm,(u8)dm_value[1]);
+ else if (dm_value[0] == 0x30)
+ halrf_do_imr_test(dm, (u8)dm_value[1]);
+}
+
+void
+halrf_iqk_hwtx_check(
+ void *dm_void,
+ boolean is_check
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+ u32 tmp_b04;
+
+ if (is_check)
+ iqk_info->is_hwtx = (boolean)odm_get_bb_reg(dm, 0xb00, BIT(8));
+ else {
+ if (iqk_info->is_hwtx) {
+ tmp_b04 = odm_read_4byte(dm, 0xb04);
+ odm_set_bb_reg(dm, 0xb04, BIT(3) | BIT (2), 0x0);
+ odm_write_4byte(dm, 0xb04, tmp_b04);
+ }
+ }
+}
+
+void
+halrf_segment_iqk_trigger(
+ void *dm_void,
+ boolean clear,
+ boolean segment_iqk
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+ struct _hal_rf_ *rf = &dm->rf_table;
+ u64 start_time;
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
+ if (odm_check_power_status(dm) == false)
+ return;
+#endif
+
+ if ((dm->mp_mode != NULL) && (rf->is_con_tx != NULL) && (rf->is_single_tone != NULL) && (rf->is_carrier_suppresion != NULL))
+ if (*dm->mp_mode && ((*rf->is_con_tx || *rf->is_single_tone || *rf->is_carrier_suppresion)))
+ return;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ if (!(rf->rf_supportability & HAL_RF_IQK))
+ return;
+#endif
+
+#if DISABLE_BB_RF
+ return;
+#endif
+ if (iqk_info->rfk_forbidden)
+ return;
+
+ if (!dm->rf_calibrate_info.is_iqk_in_progress) {
+ odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
+ dm->rf_calibrate_info.is_iqk_in_progress = true;
+ odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
+ start_time = odm_get_current_time(dm);
+ dm->IQK_info.segment_iqk = segment_iqk;
+
+ switch (dm->support_ic_type) {
+#if (RTL8822B_SUPPORT == 1)
+ case ODM_RTL8822B:
+ phy_iq_calibrate_8822b(dm, clear, segment_iqk);
+ break;
+#endif
+#if (RTL8821C_SUPPORT == 1)
+ case ODM_RTL8821C:
+ phy_iq_calibrate_8821c(dm, clear, segment_iqk);
+ break;
+#endif
+#if (RTL8814B_SUPPORT == 1)
+ case ODM_RTL8814B:
+ break;
+#endif
+ default:
+ break;
+ }
+ dm->rf_calibrate_info.iqk_progressing_time = odm_get_progressing_time(dm, start_time);
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]IQK progressing_time = %lld ms\n", dm->rf_calibrate_info.iqk_progressing_time);
+
+ odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
+ dm->rf_calibrate_info.is_iqk_in_progress = false;
+ odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
+ } else
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "== Return the IQK CMD, because RFKs in Progress ==\n");
+}
+
+
+
+#endif
+
+
+
+u8 halrf_match_iqk_version(void *dm_void)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct _hal_rf_ *rf = &dm->rf_table;
+
+ u32 iqk_version = 0;
+ char temp[10] = {0};
+
+ odm_move_memory(dm, temp, (PVOID)(HALRF_IQK_VER), sizeof(temp));
+ PHYDM_SSCANF(temp + 2, DCMD_HEX, &iqk_version);
+
+ if (dm->support_ic_type == ODM_RTL8822B) {
+ if ((iqk_version >= 0x24) && (odm_get_hw_img_version(dm) >= 72))
+ return 1;
+ else if ((iqk_version <= 0x23) && (odm_get_hw_img_version(dm) <= 71))
+ return 1;
+ else
+ return 0;
+ }
+
+ if (dm->support_ic_type == ODM_RTL8821C) {
+ if ((iqk_version >= 0x18) && (odm_get_hw_img_version(dm) >= 37))
+ return 1;
+ else
+ return 0;
+ }
+
+ return 1;
+}
+
+
+
+void
+halrf_rf_lna_setting(
+ void *dm_void,
+ enum phydm_lna_set type
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct _hal_rf_ *rf = &dm->rf_table;
+
+ switch (dm->support_ic_type) {
+#if (RTL8188E_SUPPORT == 1)
+ case ODM_RTL8188E:
+ halrf_rf_lna_setting_8188e(dm, type);
+ break;
+#endif
+#if (RTL8192E_SUPPORT == 1)
+ case ODM_RTL8192E:
+ halrf_rf_lna_setting_8192e(dm, type);
+ break;
+#endif
+#if (RTL8723B_SUPPORT == 1)
+ case ODM_RTL8723B:
+ halrf_rf_lna_setting_8723b(dm, type);
+ break;
+#endif
+#if (RTL8812A_SUPPORT == 1)
+ case ODM_RTL8812:
+ halrf_rf_lna_setting_8812a(dm, type);
+ break;
+#endif
+#if ((RTL8821A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1))
+ case ODM_RTL8881A:
+ case ODM_RTL8821:
+ halrf_rf_lna_setting_8821a(dm, type);
+ break;
+#endif
+#if (RTL8822B_SUPPORT == 1)
+ case ODM_RTL8822B:
+ halrf_rf_lna_setting_8822b(dm, type);
+ break;
+#endif
+#if (RTL8821C_SUPPORT == 1)
+ case ODM_RTL8821C:
+ halrf_rf_lna_setting_8821c(dm, type);
+ break;
+#endif
+ default:
+ break;
+ }
+
+ }
+
+
+void
+halrf_support_ability_debug(
+ void *dm_void,
+ char input[][16],
+ u32 *_used,
+ char *output,
+ u32 *_out_len
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct _hal_rf_ *rf = &dm->rf_table;
+ u32 dm_value[10] = {0};
+ u32 used = *_used;
+ u32 out_len = *_out_len;
+ u8 i;
+
+ for (i = 0; i < 5; i++) {
+ if (input[i + 1]) {
+ PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &dm_value[i]);
+ }
+ }
+
+ PDM_SNPF(out_len, used, output + used, out_len - used, "\n%s\n",
+ "================================");
+ if (dm_value[0] == 100) {
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "[RF Supportability]\n");
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "%s\n", "================================");
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "00. (( %s ))Power Tracking\n",
+ ((rf->rf_supportability & HAL_RF_TX_PWR_TRACK) ? ("V") : (".")));
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "01. (( %s ))IQK\n",
+ ((rf->rf_supportability & HAL_RF_IQK) ? ("V") : (".")));
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "02. (( %s ))LCK\n",
+ ((rf->rf_supportability & HAL_RF_LCK) ? ("V") : (".")));
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "03. (( %s ))DPK\n",
+ ((rf->rf_supportability & HAL_RF_DPK) ? ("V") : (".")));
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "04. (( %s ))HAL_RF_TXGAPK\n",
+ ((rf->rf_supportability & HAL_RF_TXGAPK) ? ("V") : (".")));
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "%s\n", "================================");
+ }
+ else {
+ if (dm_value[1] == 1) { /* enable */
+ rf->rf_supportability |= BIT(dm_value[0]) ;
+ } else if (dm_value[1] == 2) /* disable */
+ rf->rf_supportability &= ~(BIT(dm_value[0])) ;
+ else {
+ PDM_SNPF(out_len, used, output + used,
+ out_len - used, "%s\n",
+ "[Warning!!!] 1:enable, 2:disable");
+ }
+ }
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "Curr-RF_supportability = 0x%x\n",
+ rf->rf_supportability);
+ PDM_SNPF(out_len, used, output + used, out_len - used, "%s\n",
+ "================================");
+
+ *_used = used;
+ *_out_len = out_len;
+}
+
+void
+halrf_cmn_info_init(
+ void *dm_void,
+enum halrf_cmninfo_init cmn_info,
+ u32 value
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct _hal_rf_ *rf = &dm->rf_table;
+
+ switch (cmn_info) {
+ case HALRF_CMNINFO_EEPROM_THERMAL_VALUE:
+ rf->eeprom_thermal = (u8)value;
+ break;
+ case HALRF_CMNINFO_FW_VER:
+ rf->fw_ver = (u32)value;
+ break;
+ default:
+ break;
+ }
+}
+
+
+void
+halrf_cmn_info_hook(
+ void *dm_void,
+enum halrf_cmninfo_hook cmn_info,
+ void *value
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct _hal_rf_ *rf = &dm->rf_table;
+
+ switch (cmn_info) {
+ case HALRF_CMNINFO_CON_TX:
+ rf->is_con_tx = (boolean *)value;
+ break;
+ case HALRF_CMNINFO_SINGLE_TONE:
+ rf->is_single_tone = (boolean *)value;
+ break;
+ case HALRF_CMNINFO_CARRIER_SUPPRESSION:
+ rf->is_carrier_suppresion = (boolean *)value;
+ break;
+ case HALRF_CMNINFO_MP_RATE_INDEX:
+ rf->mp_rate_index = (u8 *)value;
+ break;
+ default:
+ /*do nothing*/
+ break;
+ }
+}
+
+void
+halrf_cmn_info_set(
+ void *dm_void,
+ u32 cmn_info,
+ u64 value
+)
+{
+ /* */
+ /* This init variable may be changed in run time. */
+ /* */
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct _hal_rf_ *rf = &dm->rf_table;
+
+ switch (cmn_info) {
+ case HALRF_CMNINFO_ABILITY:
+ rf->rf_supportability = (u32)value;
+ break;
+
+ case HALRF_CMNINFO_DPK_EN:
+ rf->dpk_en = (u8)value;
+ break;
+ case HALRF_CMNINFO_RFK_FORBIDDEN :
+ dm->IQK_info.rfk_forbidden = (boolean)value;
+ break;
+ #if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
+ case HALRF_CMNINFO_IQK_SEGMENT:
+ dm->IQK_info.segment_iqk = (boolean)value;
+ break;
+ #endif
+ case HALRF_CMNINFO_RATE_INDEX:
+ rf->p_rate_index = (u32)value;
+ break;
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+ case HALRF_CMNINFO_MP_PSD_POINT:
+ rf->halrf_psd_data.point = (u32)value;
+ break;
+ case HALRF_CMNINFO_MP_PSD_START_POINT:
+ rf->halrf_psd_data.start_point = (u32)value;
+ break;
+ case HALRF_CMNINFO_MP_PSD_STOP_POINT:
+ rf->halrf_psd_data.stop_point = (u32)value;
+ break;
+ case HALRF_CMNINFO_MP_PSD_AVERAGE:
+ rf->halrf_psd_data.average = (u32)value;
+ break;
+#endif
+ default:
+ /* do nothing */
+ break;
+ }
+}
+
+u64
+halrf_cmn_info_get(
+ void *dm_void,
+ u32 cmn_info
+)
+{
+ /* */
+ /* This init variable may be changed in run time. */
+ /* */
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct _hal_rf_ *rf = &dm->rf_table;
+ u64 return_value = 0;
+
+ switch (cmn_info) {
+ case HALRF_CMNINFO_ABILITY:
+ return_value = (u32)rf->rf_supportability;
+ break;
+ case HALRF_CMNINFO_RFK_FORBIDDEN :
+ return_value = dm->IQK_info.rfk_forbidden;
+ break;
+ #if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
+ case HALRF_CMNINFO_IQK_SEGMENT:
+ return_value = dm->IQK_info.segment_iqk;
+ break;
+ #endif
+ default:
+ /* do nothing */
+ break;
+ }
+
+ return return_value;
+}
+
+void
+halrf_supportability_init_mp(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct _hal_rf_ *rf = &dm->rf_table;
+
+ switch (dm->support_ic_type) {
+ case ODM_RTL8814B:
+ #if (RTL8814B_SUPPORT == 1)
+ rf->rf_supportability =
+ HAL_RF_TX_PWR_TRACK |
+ HAL_RF_IQK |
+ HAL_RF_LCK |
+ /*HAL_RF_DPK |*/
+ 0;
+ #endif
+ break;
+ #if (RTL8822B_SUPPORT == 1)
+ case ODM_RTL8822B:
+ rf->rf_supportability =
+ HAL_RF_TX_PWR_TRACK |
+ HAL_RF_IQK |
+ HAL_RF_LCK |
+ /*HAL_RF_DPK |*/
+ 0;
+ break;
+ #endif
+
+ #if (RTL8821C_SUPPORT == 1)
+ case ODM_RTL8821C:
+ rf->rf_supportability =
+ HAL_RF_TX_PWR_TRACK |
+ HAL_RF_IQK |
+ HAL_RF_LCK |
+ /*HAL_RF_DPK |*/
+ /*HAL_RF_TXGAPK |*/
+ 0;
+ break;
+ #endif
+
+ default:
+ rf->rf_supportability =
+ HAL_RF_TX_PWR_TRACK |
+ HAL_RF_IQK |
+ HAL_RF_LCK |
+ /*HAL_RF_DPK |*/
+ /*HAL_RF_TXGAPK |*/
+ 0;
+ break;
+
+ }
+
+ PHYDM_DBG(dm, ODM_COMP_INIT, "IC = ((0x%x)), RF_Supportability Init MP = ((0x%x))\n", dm->support_ic_type, rf->rf_supportability);
+}
+
+void
+halrf_supportability_init(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct _hal_rf_ *rf = &dm->rf_table;
+
+ switch (dm->support_ic_type) {
+ case ODM_RTL8814B:
+ #if (RTL8814B_SUPPORT == 1)
+ rf->rf_supportability =
+ HAL_RF_TX_PWR_TRACK |
+ HAL_RF_IQK |
+ HAL_RF_LCK |
+ /*HAL_RF_DPK |*/
+ 0;
+ #endif
+ break;
+ #if (RTL8822B_SUPPORT == 1)
+ case ODM_RTL8822B:
+ rf->rf_supportability =
+ HAL_RF_TX_PWR_TRACK |
+ HAL_RF_IQK |
+ HAL_RF_LCK |
+ /*HAL_RF_DPK |*/
+ 0;
+ break;
+ #endif
+
+ #if (RTL8821C_SUPPORT == 1)
+ case ODM_RTL8821C:
+ rf->rf_supportability =
+ HAL_RF_TX_PWR_TRACK |
+ HAL_RF_IQK |
+ HAL_RF_LCK |
+ /*HAL_RF_DPK |*/
+ /*HAL_RF_TXGAPK |*/
+ 0;
+ break;
+ #endif
+
+ default:
+ rf->rf_supportability =
+ HAL_RF_TX_PWR_TRACK |
+ HAL_RF_IQK |
+ HAL_RF_LCK |
+ /*HAL_RF_DPK |*/
+ 0;
+ break;
+
+ }
+
+ PHYDM_DBG(dm, ODM_COMP_INIT, "IC = ((0x%x)), RF_Supportability Init = ((0x%x))\n", dm->support_ic_type, rf->rf_supportability);
+}
+
+void
+halrf_watchdog(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ phydm_rf_watchdog(dm);
+}
+#if 0
+void
+halrf_iqk_init(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct _hal_rf_ *rf = &(dm->rf_table);
+
+ switch (dm->support_ic_type) {
+ #if (RTL8814B_SUPPORT == 1)
+ case ODM_RTL8814B:
+ break;
+ #endif
+ #if (RTL8822B_SUPPORT == 1)
+ case ODM_RTL8822B:
+ _iq_calibrate_8822b_init(dm);
+ break;
+ #endif
+ #if (RTL8821C_SUPPORT == 1)
+ case ODM_RTL8821C:
+ break;
+ #endif
+
+ default:
+ break;
+ }
+}
+#endif
+
+
+void
+halrf_iqk_trigger(
+ void *dm_void,
+ boolean is_recovery
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+ struct _hal_rf_ *rf = &dm->rf_table;
+ u64 start_time;
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
+ if (odm_check_power_status(dm) == false)
+ return;
+#endif
+
+ if ((dm->mp_mode != NULL) && (rf->is_con_tx != NULL) && (rf->is_single_tone != NULL) && (rf->is_carrier_suppresion != NULL))
+ if (*dm->mp_mode && ((*rf->is_con_tx || *rf->is_single_tone || *rf->is_carrier_suppresion)))
+ return;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ if (!(rf->rf_supportability & HAL_RF_IQK))
+ return;
+#endif
+
+#if DISABLE_BB_RF
+ return;
+#endif
+
+ if (iqk_info->rfk_forbidden)
+ return;
+
+ if (!dm->rf_calibrate_info.is_iqk_in_progress) {
+ odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
+ dm->rf_calibrate_info.is_iqk_in_progress = true;
+ odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
+ start_time = odm_get_current_time(dm);
+ switch (dm->support_ic_type) {
+#if (RTL8188E_SUPPORT == 1)
+ case ODM_RTL8188E:
+ phy_iq_calibrate_8188e(dm, is_recovery);
+ break;
+#endif
+#if (RTL8188F_SUPPORT == 1)
+ case ODM_RTL8188F:
+ phy_iq_calibrate_8188f(dm, is_recovery);
+ break;
+#endif
+#if (RTL8192E_SUPPORT == 1)
+ case ODM_RTL8192E:
+ phy_iq_calibrate_8192e(dm, is_recovery);
+ break;
+#endif
+#if (RTL8197F_SUPPORT == 1)
+ case ODM_RTL8197F:
+ phy_iq_calibrate_8197f(dm, is_recovery);
+ break;
+#endif
+#if (RTL8703B_SUPPORT == 1)
+ case ODM_RTL8703B:
+ phy_iq_calibrate_8703b(dm, is_recovery);
+ break;
+#endif
+#if (RTL8710B_SUPPORT == 1)
+ case ODM_RTL8710B:
+ phy_iq_calibrate_8710b(dm, is_recovery);
+ break;
+#endif
+#if (RTL8723B_SUPPORT == 1)
+ case ODM_RTL8723B:
+ phy_iq_calibrate_8723b(dm, is_recovery);
+ break;
+#endif
+#if (RTL8723D_SUPPORT == 1)
+ case ODM_RTL8723D:
+ phy_iq_calibrate_8723d(dm, is_recovery);
+ break;
+#endif
+#if (RTL8812A_SUPPORT == 1)
+ case ODM_RTL8812:
+ phy_iq_calibrate_8812a(dm, is_recovery);
+ break;
+#endif
+#if (RTL8821A_SUPPORT == 1)
+ case ODM_RTL8821:
+ phy_iq_calibrate_8821a(dm, is_recovery);
+ break;
+#endif
+#if (RTL8814A_SUPPORT == 1)
+ case ODM_RTL8814A:
+ phy_iq_calibrate_8814a(dm, is_recovery);
+ break;
+#endif
+#if (RTL8822B_SUPPORT == 1)
+ case ODM_RTL8822B:
+ phy_iq_calibrate_8822b(dm, false, false);
+ break;
+#endif
+#if (RTL8821C_SUPPORT == 1)
+ case ODM_RTL8821C:
+ phy_iq_calibrate_8821c(dm, false, false);
+ break;
+#endif
+#if (RTL8814B_SUPPORT == 1)
+ case ODM_RTL8814B:
+ break;
+#endif
+ default:
+ break;
+ }
+ dm->rf_calibrate_info.iqk_progressing_time = odm_get_progressing_time(dm, start_time);
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]IQK progressing_time = %lld ms\n", dm->rf_calibrate_info.iqk_progressing_time);
+
+ odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
+ dm->rf_calibrate_info.is_iqk_in_progress = false;
+ odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
+ } else
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "== Return the IQK CMD, because RFKs in Progress ==\n");
+}
+
+
+
+void
+halrf_lck_trigger(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+ struct _hal_rf_ *rf = &dm->rf_table;
+ u64 start_time;
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
+ if (odm_check_power_status(dm) == false)
+ return;
+#endif
+
+ if ((dm->mp_mode != NULL) && (rf->is_con_tx != NULL) && (rf->is_single_tone != NULL) && (rf->is_carrier_suppresion != NULL))
+ if (*dm->mp_mode && ((*rf->is_con_tx || *rf->is_single_tone || *rf->is_carrier_suppresion)))
+ return;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ if (!(rf->rf_supportability & HAL_RF_LCK))
+ return;
+#endif
+
+#if DISABLE_BB_RF
+ return;
+#endif
+ if (iqk_info->rfk_forbidden)
+ return;
+ while (*dm->is_scan_in_process) {
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[LCK]scan is in process, bypass LCK\n");
+ return;
+ }
+
+ if (!dm->rf_calibrate_info.is_lck_in_progress) {
+ odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
+ dm->rf_calibrate_info.is_lck_in_progress = true;
+ odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
+ start_time = odm_get_current_time(dm);
+ switch (dm->support_ic_type) {
+#if (RTL8188E_SUPPORT == 1)
+ case ODM_RTL8188E:
+ phy_lc_calibrate_8188e(dm);
+ break;
+#endif
+#if (RTL8188F_SUPPORT == 1)
+ case ODM_RTL8188F:
+ phy_lc_calibrate_8188f(dm);
+ break;
+#endif
+#if (RTL8192E_SUPPORT == 1)
+ case ODM_RTL8192E:
+ phy_lc_calibrate_8192e(dm);
+ break;
+#endif
+#if (RTL8197F_SUPPORT == 1)
+ case ODM_RTL8197F:
+ phy_lc_calibrate_8197f(dm);
+ break;
+#endif
+#if (RTL8703B_SUPPORT == 1)
+ case ODM_RTL8703B:
+ phy_lc_calibrate_8703b(dm);
+ break;
+#endif
+#if (RTL8710B_SUPPORT == 1)
+ case ODM_RTL8710B:
+ phy_lc_calibrate_8710b(dm);
+ break;
+#endif
+#if (RTL8723B_SUPPORT == 1)
+ case ODM_RTL8723B:
+ phy_lc_calibrate_8723b(dm);
+ break;
+#endif
+#if (RTL8723D_SUPPORT == 1)
+ case ODM_RTL8723D:
+ phy_lc_calibrate_8723d(dm);
+ break;
+#endif
+#if (RTL8812A_SUPPORT == 1)
+ case ODM_RTL8812:
+ phy_lc_calibrate_8812a(dm);
+ break;
+#endif
+#if (RTL8821A_SUPPORT == 1)
+ case ODM_RTL8821:
+ phy_lc_calibrate_8821a(dm);
+ break;
+#endif
+#if (RTL8814A_SUPPORT == 1)
+ case ODM_RTL8814A:
+ phy_lc_calibrate_8814a(dm);
+ break;
+#endif
+#if (RTL8822B_SUPPORT == 1)
+ case ODM_RTL8822B:
+ phy_lc_calibrate_8822b(dm);
+ break;
+#endif
+#if (RTL8821C_SUPPORT == 1)
+ case ODM_RTL8821C:
+ phy_lc_calibrate_8821c(dm);
+ break;
+#endif
+#if (RTL8814B_SUPPORT == 1)
+ case ODM_RTL8814B:
+ break;
+#endif
+ default:
+ break;
+ }
+ dm->rf_calibrate_info.lck_progressing_time = odm_get_progressing_time(dm, start_time);
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]LCK progressing_time = %lld ms\n", dm->rf_calibrate_info.lck_progressing_time);
+#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
+ halrf_lck_dbg(dm);
+#endif
+ odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
+ dm->rf_calibrate_info.is_lck_in_progress = false;
+ odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
+ }else
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "== Return the LCK CMD, because RFK is in Progress ==\n");
+}
+
+void
+halrf_init(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+ PHYDM_DBG(dm, ODM_COMP_INIT, "HALRF_Init\n");
+
+ if (*dm->mp_mode == true)
+ halrf_supportability_init_mp(dm);
+ else
+ halrf_supportability_init(dm);
+
+ /*Init all RF funciton*/
+ /*iqk_init();*/
+ /*dpk_init();*/
+}
+
+
+
+
diff --git a/hal/phydm/halrf/halrf.h b/hal/phydm/halrf/halrf.h
new file mode 100644
index 0000000..7240397
--- /dev/null
+++ b/hal/phydm/halrf/halrf.h
@@ -0,0 +1,455 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger
+ *
+ *****************************************************************************/
+
+
+#ifndef _HALRF_H__
+#define _HALRF_H__
+
+/*============================================================*/
+/*include files*/
+/*============================================================*/
+#include "halrf/halrf_psd.h"
+
+
+/*============================================================*/
+/*Definition */
+/*============================================================*/
+/*IQK version*/
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
+#define IQK_VERSION_8188E "0x14"
+#define IQK_VERSION_8192E "0x01"
+#define IQK_VERSION_8723B "0x1e"
+#define IQK_VERSION_8812A "0x01"
+#define IQK_VERSION_8821A "0x01"
+#elif (DM_ODM_SUPPORT_TYPE & (ODM_CE))
+#define IQK_VERSION_8188E "0x01"
+#define IQK_VERSION_8192E "0x01"
+#define IQK_VERSION_8723B "0x1e"
+#define IQK_VERSION_8812A "0x01"
+#define IQK_VERSION_8821A "0x01"
+#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+#define IQK_VERSION_8188E "0x01"
+#define IQK_VERSION_8192E "0x01"
+#define IQK_VERSION_8723B "0x1e"
+#define IQK_VERSION_8812A "0x01"
+#define IQK_VERSION_8821A "0x01"
+#endif
+#define IQK_VERSION_8814A "0x0f"
+#define IQK_VERSION_8188F "0x01"
+#define IQK_VERSION_8197F "0x01"
+#define IQK_VERSION_8703B "0x05"
+#define IQK_VERSION_8710B "0x01"
+#define IQK_VERSION_8723D "0x02"
+#define IQK_VERSION_8822B "0x2f"
+#define IQK_VERSION_8821C "0x23"
+
+/*LCK version*/
+#define LCK_VERSION_8188E "0x01"
+#define LCK_VERSION_8192E "0x01"
+#define LCK_VERSION_8723B "0x01"
+#define LCK_VERSION_8812A "0x01"
+#define LCK_VERSION_8821A "0x01"
+#define LCK_VERSION_8814A "0x01"
+#define LCK_VERSION_8188F "0x01"
+#define LCK_VERSION_8197F "0x01"
+#define LCK_VERSION_8703B "0x01"
+#define LCK_VERSION_8710B "0x01"
+#define LCK_VERSION_8723D "0x01"
+#define LCK_VERSION_8822B "0x01"
+#define LCK_VERSION_8821C "0x01"
+
+/*power tracking version*/
+#define POWERTRACKING_VERSION_8188E "0x01"
+#define POWERTRACKING_VERSION_8192E "0x01"
+#define POWERTRACKING_VERSION_8723B "0x01"
+#define POWERTRACKING_VERSION_8812A "0x01"
+#define POWERTRACKING_VERSION_8821A "0x01"
+#define POWERTRACKING_VERSION_8814A "0x01"
+#define POWERTRACKING_VERSION_8188F "0x01"
+#define POWERTRACKING_VERSION_8197F "0x01"
+#define POWERTRACKING_VERSION_8703B "0x01"
+#define POWERTRACKING_VERSION_8710B "0x01"
+#define POWERTRACKING_VERSION_8723D "0x01"
+#define POWERTRACKING_VERSION_8822B "0x01"
+#define POWERTRACKING_VERSION_8821C "0x01"
+
+/*DPK tracking version*/
+#define DPK_VERSION_8188E "NONE"
+#define DPK_VERSION_8192E "NONE"
+#define DPK_VERSION_8723B "NONE"
+#define DPK_VERSION_8812A "NONE"
+#define DPK_VERSION_8821A "NONE"
+#define DPK_VERSION_8814A "NONE"
+#define DPK_VERSION_8188F "NONE"
+#define DPK_VERSION_8197F "NONE"
+#define DPK_VERSION_8703B "NONE"
+#define DPK_VERSION_8710B "NONE"
+#define DPK_VERSION_8723D "NONE"
+#define DPK_VERSION_8822B "NONE"
+#define DPK_VERSION_8821C "NONE"
+
+/*Kfree tracking version*/
+#define KFREE_VERSION_8188E (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE"
+#define KFREE_VERSION_8192E (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE"
+#define KFREE_VERSION_8723B (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE"
+#define KFREE_VERSION_8812A (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE"
+#define KFREE_VERSION_8821A (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE"
+#define KFREE_VERSION_8814A (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE"
+#define KFREE_VERSION_8188F (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE"
+#define KFREE_VERSION_8197F (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE"
+#define KFREE_VERSION_8703B (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE"
+#define KFREE_VERSION_8710B (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE"
+#define KFREE_VERSION_8723D (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE"
+#define KFREE_VERSION_8822B (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE"
+#define KFREE_VERSION_8821C (dm->power_trim_data.flag & KFREE_FLAG_ON)? "0x01" : "NONE"
+
+/*PA Bias Calibration version*/
+#define PABIASK_VERSION_8188E (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE"
+#define PABIASK_VERSION_8192E (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE"
+#define PABIASK_VERSION_8723B (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE"
+#define PABIASK_VERSION_8812A (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE"
+#define PABIASK_VERSION_8821A (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE"
+#define PABIASK_VERSION_8814A (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE"
+#define PABIASK_VERSION_8188F (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE"
+#define PABIASK_VERSION_8197F (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE"
+#define PABIASK_VERSION_8703B (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE"
+#define PABIASK_VERSION_8710B (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE"
+#define PABIASK_VERSION_8723D (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE"
+#define PABIASK_VERSION_8822B (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE"
+#define PABIASK_VERSION_8821C (dm->power_trim_data.pa_bias_flag & PA_BIAS_FLAG_ON)? "0x01" : "NONE"
+
+
+
+#define HALRF_IQK_VER (dm->support_ic_type == ODM_RTL8188E)? IQK_VERSION_8188E :\
+ (dm->support_ic_type == ODM_RTL8192E)? IQK_VERSION_8192E :\
+ (dm->support_ic_type == ODM_RTL8723B)? IQK_VERSION_8723B :\
+ (dm->support_ic_type == ODM_RTL8812)? IQK_VERSION_8812A :\
+ (dm->support_ic_type == ODM_RTL8821)? IQK_VERSION_8821A :\
+ (dm->support_ic_type == ODM_RTL8814A)? IQK_VERSION_8814A :\
+ (dm->support_ic_type == ODM_RTL8188F)? IQK_VERSION_8188F :\
+ (dm->support_ic_type == ODM_RTL8197F)? IQK_VERSION_8197F :\
+ (dm->support_ic_type == ODM_RTL8703B)? IQK_VERSION_8703B :\
+ (dm->support_ic_type == ODM_RTL8710B)? IQK_VERSION_8710B :\
+ (dm->support_ic_type == ODM_RTL8723D)? IQK_VERSION_8723D :\
+ (dm->support_ic_type == ODM_RTL8822B)? IQK_VERSION_8822B :\
+ (dm->support_ic_type == ODM_RTL8821C)? IQK_VERSION_8821C :"unknown"
+
+
+#define HALRF_LCK_VER (dm->support_ic_type == ODM_RTL8188E)? LCK_VERSION_8188E :\
+ (dm->support_ic_type == ODM_RTL8192E)? LCK_VERSION_8192E :\
+ (dm->support_ic_type == ODM_RTL8723B)? LCK_VERSION_8723B :\
+ (dm->support_ic_type == ODM_RTL8812)? LCK_VERSION_8812A :\
+ (dm->support_ic_type == ODM_RTL8821)? LCK_VERSION_8821A :\
+ (dm->support_ic_type == ODM_RTL8814A)? LCK_VERSION_8814A :\
+ (dm->support_ic_type == ODM_RTL8188F)? LCK_VERSION_8188F :\
+ (dm->support_ic_type == ODM_RTL8197F)? LCK_VERSION_8197F :\
+ (dm->support_ic_type == ODM_RTL8703B)? LCK_VERSION_8703B :\
+ (dm->support_ic_type == ODM_RTL8710B)? LCK_VERSION_8710B :\
+ (dm->support_ic_type == ODM_RTL8723D)? LCK_VERSION_8723D :\
+ (dm->support_ic_type == ODM_RTL8822B)? LCK_VERSION_8822B :\
+ (dm->support_ic_type == ODM_RTL8821C)? LCK_VERSION_8821C :"unknown"
+
+
+#define HALRF_POWRTRACKING_VER (dm->support_ic_type == ODM_RTL8188E)? POWERTRACKING_VERSION_8188E :\
+ (dm->support_ic_type == ODM_RTL8192E)? POWERTRACKING_VERSION_8192E :\
+ (dm->support_ic_type == ODM_RTL8723B)? POWERTRACKING_VERSION_8723B :\
+ (dm->support_ic_type == ODM_RTL8812)? POWERTRACKING_VERSION_8812A :\
+ (dm->support_ic_type == ODM_RTL8821)? POWERTRACKING_VERSION_8821A :\
+ (dm->support_ic_type == ODM_RTL8814A)? POWERTRACKING_VERSION_8814A :\
+ (dm->support_ic_type == ODM_RTL8188F)? POWERTRACKING_VERSION_8188F :\
+ (dm->support_ic_type == ODM_RTL8197F)? POWERTRACKING_VERSION_8197F :\
+ (dm->support_ic_type == ODM_RTL8703B)? POWERTRACKING_VERSION_8703B :\
+ (dm->support_ic_type == ODM_RTL8710B)? POWERTRACKING_VERSION_8710B :\
+ (dm->support_ic_type == ODM_RTL8723D)? POWERTRACKING_VERSION_8723D :\
+ (dm->support_ic_type == ODM_RTL8822B)? POWERTRACKING_VERSION_8822B :\
+ (dm->support_ic_type == ODM_RTL8821C)? POWERTRACKING_VERSION_8821C :"unknown"
+
+#define HALRF_DPK_VER (dm->support_ic_type == ODM_RTL8188E)? DPK_VERSION_8188E :\
+ (dm->support_ic_type == ODM_RTL8192E)? DPK_VERSION_8192E :\
+ (dm->support_ic_type == ODM_RTL8723B)? DPK_VERSION_8723B :\
+ (dm->support_ic_type == ODM_RTL8812)? DPK_VERSION_8812A :\
+ (dm->support_ic_type == ODM_RTL8821)? DPK_VERSION_8821A :\
+ (dm->support_ic_type == ODM_RTL8814A)? DPK_VERSION_8814A :\
+ (dm->support_ic_type == ODM_RTL8188F)? DPK_VERSION_8188F :\
+ (dm->support_ic_type == ODM_RTL8197F)? DPK_VERSION_8197F :\
+ (dm->support_ic_type == ODM_RTL8703B)? DPK_VERSION_8703B :\
+ (dm->support_ic_type == ODM_RTL8710B)? DPK_VERSION_8710B :\
+ (dm->support_ic_type == ODM_RTL8723D)? DPK_VERSION_8723D :\
+ (dm->support_ic_type == ODM_RTL8822B)? DPK_VERSION_8822B :\
+ (dm->support_ic_type == ODM_RTL8821C)? DPK_VERSION_8821C :"unknown"
+
+#define HALRF_KFREE_VER (dm->support_ic_type == ODM_RTL8188E)? KFREE_VERSION_8188E :\
+ (dm->support_ic_type == ODM_RTL8192E)? KFREE_VERSION_8192E :\
+ (dm->support_ic_type == ODM_RTL8723B)? KFREE_VERSION_8723B :\
+ (dm->support_ic_type == ODM_RTL8812)? KFREE_VERSION_8812A :\
+ (dm->support_ic_type == ODM_RTL8821)? KFREE_VERSION_8821A :\
+ (dm->support_ic_type == ODM_RTL8814A)? KFREE_VERSION_8814A :\
+ (dm->support_ic_type == ODM_RTL8188F)? KFREE_VERSION_8188F :\
+ (dm->support_ic_type == ODM_RTL8197F)? KFREE_VERSION_8197F :\
+ (dm->support_ic_type == ODM_RTL8703B)? KFREE_VERSION_8703B :\
+ (dm->support_ic_type == ODM_RTL8710B)? KFREE_VERSION_8710B :\
+ (dm->support_ic_type == ODM_RTL8723D)? KFREE_VERSION_8723D :\
+ (dm->support_ic_type == ODM_RTL8822B)? KFREE_VERSION_8822B :\
+ (dm->support_ic_type == ODM_RTL8821C)? KFREE_VERSION_8821C :"unknown"
+
+#define HALRF_PABIASK_VER (dm->support_ic_type == ODM_RTL8188E)? PABIASK_VERSION_8188E :\
+ (dm->support_ic_type == ODM_RTL8192E)? PABIASK_VERSION_8192E :\
+ (dm->support_ic_type == ODM_RTL8723B)? PABIASK_VERSION_8723B :\
+ (dm->support_ic_type == ODM_RTL8812)? PABIASK_VERSION_8812A :\
+ (dm->support_ic_type == ODM_RTL8821)? PABIASK_VERSION_8821A :\
+ (dm->support_ic_type == ODM_RTL8814A)? PABIASK_VERSION_8814A :\
+ (dm->support_ic_type == ODM_RTL8188F)? PABIASK_VERSION_8188F :\
+ (dm->support_ic_type == ODM_RTL8197F)? PABIASK_VERSION_8197F :\
+ (dm->support_ic_type == ODM_RTL8703B)? PABIASK_VERSION_8703B :\
+ (dm->support_ic_type == ODM_RTL8710B)? PABIASK_VERSION_8710B :\
+ (dm->support_ic_type == ODM_RTL8723D)? PABIASK_VERSION_8723D :\
+ (dm->support_ic_type == ODM_RTL8822B)? PABIASK_VERSION_8822B :\
+ (dm->support_ic_type == ODM_RTL8821C)? PABIASK_VERSION_8821C :"unknown"
+
+
+
+#define IQK_THRESHOLD 8
+#define DPK_THRESHOLD 4
+
+/*===========================================================*/
+/*AGC RX High Power mode*/
+/*===========================================================*/
+#define lna_low_gain_1 0x64
+#define lna_low_gain_2 0x5A
+#define lna_low_gain_3 0x58
+
+/*============================================================*/
+/* enumeration */
+/*============================================================*/
+enum halrf_ability {
+ HAL_RF_TX_PWR_TRACK = BIT(0),
+ HAL_RF_IQK = BIT(1),
+ HAL_RF_LCK = BIT(2),
+ HAL_RF_DPK = BIT(3),
+ HAL_RF_TXGAPK = BIT(4)
+};
+
+enum halrf_cmninfo_init {
+ HALRF_CMNINFO_ABILITY = 0,
+ HALRF_CMNINFO_DPK_EN = 1,
+ HALRF_CMNINFO_EEPROM_THERMAL_VALUE,
+ HALRF_CMNINFO_FW_VER,
+ HALRF_CMNINFO_RFK_FORBIDDEN,
+ HALRF_CMNINFO_IQK_SEGMENT,
+ HALRF_CMNINFO_RATE_INDEX,
+ HALRF_CMNINFO_MP_PSD_POINT,
+ HALRF_CMNINFO_MP_PSD_START_POINT,
+ HALRF_CMNINFO_MP_PSD_STOP_POINT,
+ HALRF_CMNINFO_MP_PSD_AVERAGE
+};
+
+enum halrf_cmninfo_hook {
+ HALRF_CMNINFO_CON_TX,
+ HALRF_CMNINFO_SINGLE_TONE,
+ HALRF_CMNINFO_CARRIER_SUPPRESSION,
+ HALRF_CMNINFO_MP_RATE_INDEX
+};
+
+enum phydm_lna_set {
+ phydm_lna_disable = 0,
+ phydm_lna_enable = 1,
+};
+
+
+/*============================================================*/
+/* structure */
+/*============================================================*/
+
+struct _hal_rf_ {
+ /*hook*/
+ u8 *test1;
+
+ /*update*/
+ u32 rf_supportability;
+
+ u8 eeprom_thermal;
+ u8 dpk_en; /*Enable Function DPK OFF/ON = 0/1*/
+ boolean dpk_done;
+ u32 fw_ver;
+
+ boolean *is_con_tx;
+ boolean *is_single_tone;
+ boolean *is_carrier_suppresion;
+
+ u8 *mp_rate_index;
+ u32 p_rate_index;
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+ struct _halrf_psd_data halrf_psd_data;
+#endif
+};
+
+/*============================================================*/
+/* function prototype */
+/*============================================================*/
+
+void halrf_basic_profile(
+ void *dm_void,
+ u32 *_used,
+ char *output,
+ u32 *_out_len
+);
+#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
+void halrf_iqk_info_dump(
+ void *dm_void,
+ u32 *_used,
+ char *output,
+ u32 *_out_len
+);
+
+void
+halrf_iqk_hwtx_check(
+ void *dm_void,
+ boolean is_check
+);
+#endif
+
+u8
+halrf_match_iqk_version(
+ void *dm_void
+);
+
+void
+halrf_support_ability_debug(
+ void *dm_void,
+ char input[][16],
+ u32 *_used,
+ char *output,
+ u32 *_out_len
+);
+
+void
+halrf_cmn_info_init(
+ void *dm_void,
+ enum halrf_cmninfo_init cmn_info,
+ u32 value
+);
+
+void
+halrf_cmn_info_hook(
+ void *dm_void,
+ u32 cmn_info,
+ void *value
+);
+
+void
+halrf_cmn_info_set(
+ void *dm_void,
+ u32 cmn_info,
+ u64 value
+);
+
+u64
+halrf_cmn_info_get(
+ void *dm_void,
+ u32 cmn_info
+);
+
+void
+halrf_watchdog(
+ void *dm_void
+);
+
+void
+halrf_supportability_init(
+ void *dm_void
+);
+
+void
+halrf_init(
+ void *dm_void
+);
+
+void
+halrf_iqk_trigger(
+ void *dm_void,
+ boolean is_recovery
+);
+
+void
+halrf_segment_iqk_trigger(
+ void *dm_void,
+ boolean clear,
+ boolean segment_iqk
+);
+
+void
+halrf_lck_trigger(
+ void *dm_void
+);
+
+void
+halrf_iqk_debug(
+ void *dm_void,
+ u32 *const dm_value,
+ u32 *_used,
+ char *output,
+ u32 *_out_len
+);
+
+void
+phydm_get_iqk_cfir(
+ void *dm_void,
+ u8 idx,
+ u8 path,
+ boolean debug
+);
+
+void
+halrf_iqk_xym_read(
+ void *dm_void,
+ u8 path,
+ u8 xym_type
+ );
+
+void
+halrf_rf_lna_setting(
+ void *dm_void,
+ enum phydm_lna_set type
+);
+
+
+void
+halrf_do_imr_test(
+ void *dm_void,
+ u8 data
+);
+
+u32
+halrf_psd_log2base(
+ u32 val
+);
+
+
+#if (RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
+void halrf_iqk_dbg(void *dm_void);
+#endif
+#endif
+
+
diff --git a/hal/phydm/halrf/halrf_features.h b/hal/phydm/halrf/halrf_features.h
new file mode 100644
index 0000000..c6ef3e6
--- /dev/null
+++ b/hal/phydm/halrf/halrf_features.h
@@ -0,0 +1,43 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger
+ *
+ *****************************************************************************/
+
+#ifndef __HALRF_FEATURES_H__
+#define __HALRF_FEATURES
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+
+ #define CONFIG_HALRF_POWERTRACKING 1
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
+
+ #define CONFIG_HALRF_POWERTRACKING 1
+
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+
+ #define CONFIG_HALRF_POWERTRACKING 1
+
+#endif
+
+#endif
diff --git a/hal/phydm/halrf/halrf_iqk.h b/hal/phydm/halrf/halrf_iqk.h
new file mode 100644
index 0000000..846feb1
--- /dev/null
+++ b/hal/phydm/halrf/halrf_iqk.h
@@ -0,0 +1,85 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger
+ *
+ *****************************************************************************/
+
+#ifndef __PHYDMIQK_H__
+#define __PHYDMIQK_H__
+
+/*--------------------------Define Parameters-------------------------------*/
+#define LOK_delay 1
+#define WBIQK_delay 10
+#define TX_IQK 0
+#define RX_IQK 1
+#define TXIQK 0
+#define RXIQK1 1
+#define RXIQK2 2
+#define kcount_limit_80m 2
+#define kcount_limit_others 4
+#define rxiqk_gs_limit 10
+
+#define NUM 4
+/*---------------------------End Define Parameters-------------------------------*/
+
+struct dm_iqk_info {
+ boolean lok_fail[NUM];
+ boolean iqk_fail[2][NUM];
+ u32 iqc_matrix[2][NUM];
+ u8 iqk_times;
+ u32 rf_reg18;
+ u32 lna_idx;
+ u8 rxiqk_step;
+ u8 tmp1bcc;
+ u8 kcount;
+ u8 rfk_ing; /*bit0:IQKing, bit1:LCKing, bit2:DPKing*/
+ boolean rfk_forbidden;
+#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
+ u32 iqk_channel[2];
+ boolean iqk_fail_report[2][4][2]; /*channel/path/TRX(TX:0, RX:1) */
+ u32 iqk_cfir_real[3][4][2][8]; /*channel / path / TRX(TX:0, RX:1) / CFIR_real*/ /*channel index = 2 is just for debug*/
+ u32 iqk_cfir_imag[3][4][2][8]; /*channel / path / TRX(TX:0, RX:1) / CFIR_imag*/ /*channel index = 2 is just for debug*/
+ u8 retry_count[2][4][3]; /* channel / path / (TXK:0, RXK1:1, RXK2:2) */
+ u8 gs_retry_count[2][4][2]; /* channel / path / (GSRXK1:0, GSRXK2:1) */
+ u8 rxiqk_fail_code[2][4]; /* channel / path 0:SRXK1 fail, 1:RXK1 fail 2:RXK2 fail */
+ u32 lok_idac[2][4]; /*channel / path*/
+ u16 rxiqk_agc[2][4]; /*channel / path*/
+ u32 bypass_iqk[2][4]; /*channel / 0xc94/0xe94*/
+ u32 txgap_result[8]; /*txagpK result */
+ u32 tmp_gntwl;
+ boolean is_btg;
+ boolean isbnd;
+ boolean is_reload;
+ boolean segment_iqk;
+ boolean is_hwtx;
+
+ boolean xym_read;
+ boolean trximr_enable;
+ u32 rx_xym[2][10];
+ u32 tx_xym[2][10];
+ u32 gs1_xym[2][6];
+ u32 gs2_xym[2][6];
+ u32 rxk1_xym[2][6];
+#endif
+};
+
+#endif
diff --git a/hal/phydm/halrf/halrf_kfree.c b/hal/phydm/halrf/halrf_kfree.c
new file mode 100644
index 0000000..acc705f
--- /dev/null
+++ b/hal/phydm/halrf/halrf_kfree.c
@@ -0,0 +1,883 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger
+ *
+ *****************************************************************************/
+
+/*============================================================*/
+/*include files*/
+/*============================================================*/
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+
+/* Add for KFree Feature Requested by RF David.*/
+/*This is a phydm API*/
+
+void
+phydm_set_kfree_to_rf_8814a(
+ void *dm_void,
+ u8 e_rf_path,
+ u8 data
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
+ boolean is_odd;
+
+ if ((data % 2) != 0) { /*odd->positive*/
+ data = data - 1;
+ odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(19), 1);
+ is_odd = true;
+ } else { /*even->negative*/
+ odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(19), 0);
+ is_odd = false;
+ }
+ PHYDM_DBG(dm, ODM_COMP_MP, "phy_ConfigKFree8814A(): RF_0x55[19]= %d\n", is_odd);
+ switch (data) {
+ case 0:
+ odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0);
+ odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 0);
+ cali_info->kfree_offset[e_rf_path] = 0;
+ break;
+ case 2:
+ odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1);
+ odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 0);
+ cali_info->kfree_offset[e_rf_path] = 0;
+ break;
+ case 4:
+ odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0);
+ odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 1);
+ cali_info->kfree_offset[e_rf_path] = 1;
+ break;
+ case 6:
+ odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1);
+ odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 1);
+ cali_info->kfree_offset[e_rf_path] = 1;
+ break;
+ case 8:
+ odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0);
+ odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 2);
+ cali_info->kfree_offset[e_rf_path] = 2;
+ break;
+ case 10:
+ odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1);
+ odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 2);
+ cali_info->kfree_offset[e_rf_path] = 2;
+ break;
+ case 12:
+ odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0);
+ odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 3);
+ cali_info->kfree_offset[e_rf_path] = 3;
+ break;
+ case 14:
+ odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1);
+ odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 3);
+ cali_info->kfree_offset[e_rf_path] = 3;
+ break;
+ case 16:
+ odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0);
+ odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 4);
+ cali_info->kfree_offset[e_rf_path] = 4;
+ break;
+ case 18:
+ odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1);
+ odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 4);
+ cali_info->kfree_offset[e_rf_path] = 4;
+ break;
+ case 20:
+ odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0);
+ odm_set_rf_reg(dm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 5);
+ cali_info->kfree_offset[e_rf_path] = 5;
+ break;
+
+ default:
+ break;
+ }
+
+ if (is_odd == false) {
+ /*that means Kfree offset is negative, we need to record it.*/
+ cali_info->kfree_offset[e_rf_path] = (-1) * cali_info->kfree_offset[e_rf_path];
+ PHYDM_DBG(dm, ODM_COMP_MP, "phy_ConfigKFree8814A(): kfree_offset = %d\n", cali_info->kfree_offset[e_rf_path]);
+ } else
+ PHYDM_DBG(dm, ODM_COMP_MP, "phy_ConfigKFree8814A(): kfree_offset = %d\n", cali_info->kfree_offset[e_rf_path]);
+
+}
+
+
+
+//
+//
+//
+void
+phydm_get_thermal_trim_offset_8821c(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
+
+ u8 pg_therm = 0xff;
+
+ odm_efuse_one_byte_read(dm, PPG_THERMAL_OFFSET_8821C, &pg_therm, false);
+
+ if (pg_therm != 0xff) {
+ pg_therm = pg_therm & 0x1f;
+ if ((pg_therm & BIT(0)) == 0)
+ power_trim_info->thermal = (-1 * (pg_therm >> 1));
+ else
+ power_trim_info->thermal = (pg_therm >> 1);
+
+ power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
+ }
+
+ PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8821c thermal trim flag:0x%02x\n", power_trim_info->flag);
+
+ if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
+ PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8821c thermal:%d\n", power_trim_info->thermal);
+}
+
+
+
+void
+phydm_get_power_trim_offset_8821c(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
+
+ u8 pg_power = 0xff, i;
+
+ odm_efuse_one_byte_read(dm, PPG_BB_GAIN_2G_TXAB_OFFSET_8821C, &pg_power, false);
+
+ if (pg_power != 0xff) {
+ power_trim_info->bb_gain[0][0] = pg_power;
+ odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GL1_TXA_OFFSET_8821C, &pg_power, false);
+ power_trim_info->bb_gain[1][0] = pg_power;
+ odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GL2_TXA_OFFSET_8821C, &pg_power, false);
+ power_trim_info->bb_gain[2][0] = pg_power;
+ odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GM1_TXA_OFFSET_8821C, &pg_power, false);
+ power_trim_info->bb_gain[3][0] = pg_power;
+ odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GM2_TXA_OFFSET_8821C, &pg_power, false);
+ power_trim_info->bb_gain[4][0] = pg_power;
+ odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GH1_TXA_OFFSET_8821C, &pg_power, false);
+ power_trim_info->bb_gain[5][0] = pg_power;
+ power_trim_info->flag = power_trim_info->flag | KFREE_FLAG_ON | KFREE_FLAG_ON_2G | KFREE_FLAG_ON_5G;
+ }
+
+ PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8821c power trim flag:0x%02x\n", power_trim_info->flag);
+
+ if (power_trim_info->flag & KFREE_FLAG_ON) {
+ for (i = 0; i < KFREE_BAND_NUM; i++)
+ PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8821c power_trim_data->bb_gain[%d][0]=0x%X\n", i, power_trim_info->bb_gain[i][0]);
+ }
+}
+
+
+
+void
+phydm_set_kfree_to_rf_8821c(
+ void *dm_void,
+ u8 e_rf_path,
+ boolean wlg_btg,
+ u8 data
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
+ u8 wlg, btg;
+
+ odm_set_rf_reg(dm, e_rf_path, 0xde, BIT(0), 1);
+ odm_set_rf_reg(dm, e_rf_path, 0xde, BIT(5), 1);
+ odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(6), 1);
+ odm_set_rf_reg(dm, e_rf_path, 0x65, BIT(6), 1);
+
+ if (wlg_btg == true) {
+ wlg = data & 0xf;
+ btg = (data & 0xf0) >> 4;
+
+ odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(19), (wlg & BIT(0)));
+ odm_set_rf_reg(dm, e_rf_path, 0x55, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), (wlg >> 1));
+
+ odm_set_rf_reg(dm, e_rf_path, 0x65, BIT(19), (btg & BIT(0)));
+ odm_set_rf_reg(dm, e_rf_path, 0x65, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), (btg >> 1));
+ } else {
+ odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(19), (data & BIT(0)));
+ odm_set_rf_reg(dm, e_rf_path, 0x55, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), ((data & 0x1f) >> 1));
+ }
+
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[kfree] 8821c 0x55[19:14]=0x%X 0x65[19:14]=0x%X\n",
+ odm_get_rf_reg(dm, e_rf_path, 0x55, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14))),
+ odm_get_rf_reg(dm, e_rf_path, 0x65, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)))
+ );
+}
+
+
+
+void
+phydm_clear_kfree_to_rf_8821c(
+ void *dm_void,
+ u8 e_rf_path,
+ u8 data
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
+
+ odm_set_rf_reg(dm, e_rf_path, 0xde, BIT(0), 1);
+ odm_set_rf_reg(dm, e_rf_path, 0xde, BIT(5), 1);
+ odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(6), 1);
+ odm_set_rf_reg(dm, e_rf_path, 0x65, BIT(6), 1);
+
+ odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(19), (data & BIT(0)));
+ odm_set_rf_reg(dm, e_rf_path, 0x55, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), (data >> 1));
+
+ odm_set_rf_reg(dm, e_rf_path, 0x65, BIT(19), (data & BIT(0)));
+ odm_set_rf_reg(dm, e_rf_path, 0x65, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), (data >> 1));
+
+ odm_set_rf_reg(dm, e_rf_path, 0xde, BIT(0), 0);
+ odm_set_rf_reg(dm, e_rf_path, 0xde, BIT(5), 0);
+ odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(6), 0);
+ odm_set_rf_reg(dm, e_rf_path, 0x65, BIT(6), 0);
+
+
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[kfree] 8821c 0x55[19:14]=0x%X 0x65[19:14]=0x%X\n",
+ odm_get_rf_reg(dm, e_rf_path, 0x55, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14))),
+ odm_get_rf_reg(dm, e_rf_path, 0x65, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)))
+ );
+}
+
+
+
+void
+phydm_get_thermal_trim_offset_8822b(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
+
+ u8 pg_therm = 0xff;
+
+#if 0
+ u32 thermal_trim_enable = 0xff;
+
+ odm_efuse_logical_map_read(dm, 1, 0xc8, &thermal_trim_enable);
+
+ PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8822b 0xc8:0x%2x\n", thermal_trim_enable);
+
+ thermal_trim_enable = (thermal_trim_enable & BIT(5)) >> 5;
+
+ PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8822b thermal trim Enable:%d\n", thermal_trim_enable);
+
+ if ((cali_info->reg_rf_kfree_enable == 0 && thermal_trim_enable == 1) ||
+ cali_info->reg_rf_kfree_enable == 1) {
+#endif
+
+ odm_efuse_one_byte_read(dm, PPG_THERMAL_OFFSET, &pg_therm, false);
+
+ if (pg_therm != 0xff) {
+ pg_therm = pg_therm & 0x1f;
+ if ((pg_therm & BIT(0)) == 0)
+ power_trim_info->thermal = (-1 * (pg_therm >> 1));
+ else
+ power_trim_info->thermal = (pg_therm >> 1);
+
+ power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
+ }
+
+ PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8822b thermal trim flag:0x%02x\n", power_trim_info->flag);
+
+ if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
+ PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8822b thermal:%d\n", power_trim_info->thermal);
+#if 0
+ } else
+ return;
+#endif
+
+}
+
+
+
+void
+phydm_get_power_trim_offset_8822b(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
+ struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
+
+ u8 pg_power = 0xff, i, j;
+
+#if 0
+ u32 power_trim_enable = 0xff;
+
+ odm_efuse_logical_map_read(dm, 1, 0xc8, &power_trim_enable);
+
+ PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8822b 0xc8:0x%2x\n", power_trim_enable);
+
+ power_trim_enable = (power_trim_enable & BIT(4)) >> 4;
+
+ PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8822b power trim Enable:%d\n", power_trim_enable);
+
+ if ((cali_info->reg_rf_kfree_enable == 0 && power_trim_enable == 1) ||
+ cali_info->reg_rf_kfree_enable == 1) {
+#endif
+
+ odm_efuse_one_byte_read(dm, PPG_BB_GAIN_2G_TXAB_OFFSET, &pg_power, false);
+
+ if (pg_power != 0xff) {
+ /*Path A*/
+ odm_efuse_one_byte_read(dm, PPG_BB_GAIN_2G_TXAB_OFFSET, &pg_power, false);
+ power_trim_info->bb_gain[0][0] = (pg_power & 0xf);
+
+ /*Path B*/
+ odm_efuse_one_byte_read(dm, PPG_BB_GAIN_2G_TXAB_OFFSET, &pg_power, false);
+ power_trim_info->bb_gain[0][1] = ((pg_power & 0xf0) >> 4);
+
+ power_trim_info->flag |= KFREE_FLAG_ON_2G;
+ power_trim_info->flag |= KFREE_FLAG_ON;
+ }
+
+ odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GL1_TXA_OFFSET, &pg_power, false);
+
+ if (pg_power != 0xff) {
+ /*Path A*/
+ odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GL1_TXA_OFFSET, &pg_power, false);
+ power_trim_info->bb_gain[1][0] = pg_power;
+ odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GL2_TXA_OFFSET, &pg_power, false);
+ power_trim_info->bb_gain[2][0] = pg_power;
+ odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GM1_TXA_OFFSET, &pg_power, false);
+ power_trim_info->bb_gain[3][0] = pg_power;
+ odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GM2_TXA_OFFSET, &pg_power, false);
+ power_trim_info->bb_gain[4][0] = pg_power;
+ odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GH1_TXA_OFFSET, &pg_power, false);
+ power_trim_info->bb_gain[5][0] = pg_power;
+
+ /*Path B*/
+ odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GL1_TXB_OFFSET, &pg_power, false);
+ power_trim_info->bb_gain[1][1] = pg_power;
+ odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GL2_TXB_OFFSET, &pg_power, false);
+ power_trim_info->bb_gain[2][1] = pg_power;
+ odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GM1_TXB_OFFSET, &pg_power, false);
+ power_trim_info->bb_gain[3][1] = pg_power;
+ odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GM2_TXB_OFFSET, &pg_power, false);
+ power_trim_info->bb_gain[4][1] = pg_power;
+ odm_efuse_one_byte_read(dm, PPG_BB_GAIN_5GH1_TXB_OFFSET, &pg_power, false);
+ power_trim_info->bb_gain[5][1] = pg_power;
+
+ power_trim_info->flag |= KFREE_FLAG_ON_5G;
+ power_trim_info->flag |= KFREE_FLAG_ON;
+ }
+
+ PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8822b power trim flag:0x%02x\n", power_trim_info->flag);
+
+ if (!(power_trim_info->flag & KFREE_FLAG_ON))
+ return;
+
+ for (i = 0; i < KFREE_BAND_NUM; i++) {
+ for (j = 0; j < 2; j++)
+ PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8822b power_trim_data->bb_gain[%d][%d]=0x%X\n", i, j, power_trim_info->bb_gain[i][j]);
+ }
+#if 0
+ } else
+ return;
+#endif
+}
+
+
+
+void
+phydm_set_pa_bias_to_rf_8822b(
+ void *dm_void,
+ u8 e_rf_path,
+ s8 tx_pa_bias
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
+ u32 rf_reg_51 = 0, rf_reg_52 = 0, rf_reg_3f = 0;
+
+ rf_reg_51 = odm_get_rf_reg(dm, e_rf_path, 0x51, RFREGOFFSETMASK);
+ rf_reg_52 = odm_get_rf_reg(dm, e_rf_path, 0x52, RFREGOFFSETMASK);
+
+ PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8822b 2g rf(0x51)=0x%X rf(0x52)=0x%X path=%d\n",
+ rf_reg_51, rf_reg_52, e_rf_path);
+
+ /*rf3f => rf52[19:17] = rf3f[2:0] rf52[16:15] = rf3f[4:3] rf52[3:0] = rf3f[8:5]*/
+ /*rf3f => rf51[6:3] = rf3f[12:9] rf52[13] = rf3f[13]*/
+ rf_reg_3f = ((rf_reg_52 & 0xe0000) >> 17) |
+ (((rf_reg_52 & 0x18000) >> 15) << 3) |
+ ((rf_reg_52 & 0xf) << 5) |
+ (((rf_reg_51 & 0x78) >> 3) << 9) |
+ (((rf_reg_52 & 0x2000) >> 13) << 13);
+
+ PHYDM_DBG(dm, ODM_COMP_MP,"[kfree] 8822b 2g original tx_pa_bias=%d rf_reg_3f=0x%X path=%d\n",
+ tx_pa_bias, rf_reg_3f, e_rf_path);
+
+ tx_pa_bias = (s8)((rf_reg_3f & (BIT(12) | BIT(11) | BIT(10) | BIT(9))) >> 9) + tx_pa_bias;
+
+ if (tx_pa_bias < 0)
+ tx_pa_bias = 0;
+ else if (tx_pa_bias > 7)
+ tx_pa_bias = 7;
+
+ rf_reg_3f = ((rf_reg_3f & 0xfe1ff) | (tx_pa_bias << 9));
+
+ PHYDM_DBG(dm, ODM_COMP_MP,"[kfree] 8822b 2g offset efuse 0x3d5 0x3d6 tx_pa_bias=%d rf_reg_3f=0x%X path=%d\n",
+ tx_pa_bias, rf_reg_3f, e_rf_path);
+
+ odm_set_rf_reg(dm, e_rf_path, 0xef, BIT(10), 0x1);
+ odm_set_rf_reg(dm, e_rf_path, 0x33, RFREGOFFSETMASK, 0x0);
+ odm_set_rf_reg(dm, e_rf_path, 0x3f, RFREGOFFSETMASK, rf_reg_3f);
+ odm_set_rf_reg(dm, e_rf_path, 0x33, BIT(0), 0x1);
+ odm_set_rf_reg(dm, e_rf_path, 0x3f, RFREGOFFSETMASK, rf_reg_3f);
+ odm_set_rf_reg(dm, e_rf_path, 0x33, BIT(1), 0x1);
+ odm_set_rf_reg(dm, e_rf_path, 0x3f, RFREGOFFSETMASK, rf_reg_3f);
+ odm_set_rf_reg(dm, e_rf_path, 0x33, (BIT(1) | BIT(0)), 0x3);
+ odm_set_rf_reg(dm, e_rf_path, 0x3f, RFREGOFFSETMASK, rf_reg_3f);
+ odm_set_rf_reg(dm, e_rf_path, 0xef, BIT(10), 0x0);
+
+ PHYDM_DBG(dm, ODM_COMP_MP,"[kfree] 8822b 2g tx pa bias rf_0x3f(0x%X) path=%d\n",
+ odm_get_rf_reg(dm, e_rf_path, 0x3f, (BIT(12) | BIT(11) | BIT(10) | BIT(9))), e_rf_path);
+}
+
+
+
+void
+phydm_get_pa_bias_offset_8822b(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
+
+ u8 pg_pa_bias = 0xff, e_rf_path = 0;
+ s8 tx_pa_bias[2] = {0};
+
+ odm_efuse_one_byte_read(dm, PPG_PA_BIAS_2G_TXA_OFFSET, &pg_pa_bias, false);
+
+ if (pg_pa_bias != 0xff) {
+ /*paht a*/
+ odm_efuse_one_byte_read(dm, PPG_PA_BIAS_2G_TXA_OFFSET, &pg_pa_bias, false);
+ pg_pa_bias = pg_pa_bias & 0xf;
+
+ if ((pg_pa_bias & BIT(0)) == 0)
+ tx_pa_bias[0] = (-1 * (pg_pa_bias >> 1));
+ else
+ tx_pa_bias[0] = (pg_pa_bias >> 1);
+
+ /*paht b*/
+ odm_efuse_one_byte_read(dm, PPG_PA_BIAS_2G_TXB_OFFSET, &pg_pa_bias, false);
+ pg_pa_bias = pg_pa_bias & 0xf;
+
+ if ((pg_pa_bias & BIT(0)) == 0)
+ tx_pa_bias[1] = (-1 * (pg_pa_bias >> 1));
+ else
+ tx_pa_bias[1] = (pg_pa_bias >> 1);
+
+ PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8822b 2g tx_patha_pa_bias:%d tx_pathb_pa_bias:%d\n", tx_pa_bias[0], tx_pa_bias[1]);
+
+ for (e_rf_path = RF_PATH_A; e_rf_path < 2; e_rf_path++)
+ phydm_set_pa_bias_to_rf_8822b(dm, e_rf_path, tx_pa_bias[e_rf_path]);
+
+ power_trim_info->pa_bias_flag |= PA_BIAS_FLAG_ON;
+ }
+ else
+ PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] 8822b 2g tx pa bias no pg\n");
+}
+
+
+
+void
+phydm_set_kfree_to_rf_8822b(
+ void *dm_void,
+ u8 e_rf_path,
+ u8 data
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
+
+ odm_set_rf_reg(dm, e_rf_path, 0xde, BIT(0), 1);
+ odm_set_rf_reg(dm, e_rf_path, 0xde, BIT(4), 1);
+ odm_set_rf_reg(dm, e_rf_path, 0x65, MASKLWORD, 0x9000);
+ odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(5), 1);
+
+ odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(19), (data & BIT(0)));
+ odm_set_rf_reg(dm, e_rf_path, 0x55, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), ((data & 0x1f) >> 1));
+
+ PHYDM_DBG(dm, ODM_COMP_MP,"[kfree] 8822b 0x55[19:14]=0x%X path=%d\n",
+ odm_get_rf_reg(dm, e_rf_path, 0x55, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14))),
+ e_rf_path
+ );
+}
+
+
+
+void
+phydm_clear_kfree_to_rf_8822b(
+ void *dm_void,
+ u8 e_rf_path,
+ u8 data
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
+
+ odm_set_rf_reg(dm, e_rf_path, 0xde, BIT(0), 1);
+ odm_set_rf_reg(dm, e_rf_path, 0xde, BIT(4), 1);
+ odm_set_rf_reg(dm, e_rf_path, 0x65, MASKLWORD, 0x9000);
+ odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(5), 1);
+
+ odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(19), (data & BIT(0)));
+ odm_set_rf_reg(dm, e_rf_path, 0x55, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), ((data & 0x1f) >> 1));
+
+ odm_set_rf_reg(dm, e_rf_path, 0xde, BIT(0), 0);
+ odm_set_rf_reg(dm, e_rf_path, 0xde, BIT(4), 1);
+ odm_set_rf_reg(dm, e_rf_path, 0x65, MASKLWORD, 0x9000);
+ odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(5), 0);
+ odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(7), 0);
+
+ PHYDM_DBG(dm, ODM_COMP_MP,"[kfree] 8822b clear power trim 0x55[19:14]=0x%X path=%d\n",
+ odm_get_rf_reg(dm, e_rf_path, 0x55, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14))),
+ e_rf_path
+ );
+}
+
+void
+phydm_get_thermal_trim_offset_8710b(
+void *dm_void)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct odm_power_trim_data *power_trim_info = &(dm->power_trim_data);
+
+ u8 pg_therm = 0xff;
+
+ odm_efuse_one_byte_read(dm, 0x0EF, &pg_therm, false);
+
+ if (pg_therm != 0xff) {
+ pg_therm = pg_therm & 0x1f;
+ if ((pg_therm & BIT(0)) == 0)
+ power_trim_info->thermal = (-1 * (pg_therm >> 1));
+ else
+ power_trim_info->thermal = (pg_therm >> 1);
+
+ power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON;
+ }
+
+ ODM_RT_TRACE(dm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8710b thermal trim flag:0x%02x\n", power_trim_info->flag));
+
+ if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
+ ODM_RT_TRACE(dm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8710b thermal:%d\n", power_trim_info->thermal));
+
+}
+
+void
+phydm_get_power_trim_offset_8710b(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct odm_power_trim_data *power_trim_info = &(dm->power_trim_data);
+ struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
+
+ u8 pg_power = 0xff;
+
+ odm_efuse_one_byte_read(dm, 0xEE, &pg_power, false);
+
+ if (pg_power != 0xff) {
+ /*Path A*/
+ odm_efuse_one_byte_read(dm, 0xEE, &pg_power, false);
+ power_trim_info->bb_gain[0][0] = (pg_power & 0xf);
+
+ power_trim_info->flag |= KFREE_FLAG_ON_2G;
+ power_trim_info->flag |= KFREE_FLAG_ON;
+ }
+
+
+ ODM_RT_TRACE(dm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8710b power trim flag:0x%02x\n", power_trim_info->flag));
+
+ if (power_trim_info->flag & KFREE_FLAG_ON)
+
+ ODM_RT_TRACE(dm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] 8710b power_trim_data->bb_gain[0][0]=0x%X\n", power_trim_info->bb_gain[0][0]));
+
+}
+void
+phydm_set_kfree_to_rf_8710b(
+ void *dm_void,
+ u8 e_rf_path,
+ u8 data
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
+
+ odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(19), (data & BIT(0)));
+ odm_set_rf_reg(dm, e_rf_path, 0x55, (BIT(18) | BIT(17) | BIT(16) | BIT(15)), ((data & 0xf) >> 1));
+
+ ODM_RT_TRACE(dm, ODM_COMP_MP, ODM_DBG_LOUD,
+ ("[kfree] 8710b 0x55[19:14]=0x%X path=%d\n",
+ odm_get_rf_reg(dm, e_rf_path, 0x55, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14))),
+ e_rf_path
+ ));
+}
+
+void
+phydm_clear_kfree_to_rf_8710b(
+ void *dm_void,
+ u8 e_rf_path,
+ u8 data
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
+
+ odm_set_rf_reg(dm, e_rf_path, 0x55, BIT(19), (data & BIT(0)));
+ odm_set_rf_reg(dm, e_rf_path, 0x55, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), ((data & 0x1f) >> 1));
+
+ ODM_RT_TRACE(dm, ODM_COMP_MP, ODM_DBG_LOUD,
+ ("[kfree] 8710b clear power trim 0x55[19:14]=0x%X path=%d\n",
+ odm_get_rf_reg(dm, e_rf_path, 0x55, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14))),
+ e_rf_path
+ ));
+}
+
+
+void
+phydm_set_kfree_to_rf(
+ void *dm_void,
+ u8 e_rf_path,
+ u8 data
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+ if (dm->support_ic_type & ODM_RTL8814A)
+ phydm_set_kfree_to_rf_8814a(dm, e_rf_path, data);
+
+ if ((dm->support_ic_type & ODM_RTL8821C) && (*dm->band_type == ODM_BAND_2_4G))
+ phydm_set_kfree_to_rf_8821c(dm, e_rf_path, true, data);
+ else if (dm->support_ic_type & ODM_RTL8821C)
+ phydm_set_kfree_to_rf_8821c(dm, e_rf_path, false, data);
+
+ if (dm->support_ic_type & ODM_RTL8822B)
+ phydm_set_kfree_to_rf_8822b(dm, e_rf_path, data);
+ if (dm->support_ic_type & ODM_RTL8710B)
+ phydm_set_kfree_to_rf_8710b(dm, e_rf_path, data);
+}
+
+
+
+void
+phydm_clear_kfree_to_rf(
+ void *dm_void,
+ u8 e_rf_path,
+ u8 data
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+ if (dm->support_ic_type & ODM_RTL8822B)
+ phydm_clear_kfree_to_rf_8822b(dm, e_rf_path, 1);
+
+ if (dm->support_ic_type & ODM_RTL8821C)
+ phydm_clear_kfree_to_rf_8821c(dm, e_rf_path, 1);
+
+ if (dm->support_ic_type & ODM_RTL8710B)
+ phydm_set_kfree_to_rf_8710b(dm, e_rf_path, data);
+}
+
+
+
+
+void
+phydm_get_thermal_trim_offset(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+ void *adapter = dm->adapter;
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+ PEFUSE_HAL pEfuseHal = &hal_data->EfuseHal;
+ u1Byte eFuseContent[DCMD_EFUSE_MAX_SECTION_NUM * EFUSE_MAX_WORD_UNIT * 2];
+
+ if (HAL_MAC_Dump_EFUSE(&GET_HAL_MAC_INFO((PADAPTER)adapter), EFUSE_WIFI, eFuseContent, pEfuseHal->PhysicalLen_WiFi, HAL_MAC_EFUSE_PHYSICAL, HAL_MAC_EFUSE_PARSE_DRV) != RT_STATUS_SUCCESS)
+ PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] dump efuse fail !!!\n");
+#endif
+
+ if (dm->support_ic_type & ODM_RTL8821C)
+ phydm_get_thermal_trim_offset_8821c(dm_void);
+ else if (dm->support_ic_type & ODM_RTL8822B)
+ phydm_get_thermal_trim_offset_8822b(dm_void);
+ else if (dm->support_ic_type & ODM_RTL8710B)
+ phydm_get_thermal_trim_offset_8710b(dm_void);
+}
+
+
+
+void
+phydm_get_power_trim_offset(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+#if 0 //(DM_ODM_SUPPORT_TYPE & ODM_WIN) // 2017 MH DM Should use the same code.s
+ void *adapter = dm->adapter;
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+ PEFUSE_HAL pEfuseHal = &hal_data->EfuseHal;
+ u1Byte eFuseContent[DCMD_EFUSE_MAX_SECTION_NUM * EFUSE_MAX_WORD_UNIT * 2];
+
+ if (HAL_MAC_Dump_EFUSE(&GET_HAL_MAC_INFO(adapter), EFUSE_WIFI, eFuseContent, pEfuseHal->PhysicalLen_WiFi, HAL_MAC_EFUSE_PHYSICAL, HAL_MAC_EFUSE_PARSE_DRV) != RT_STATUS_SUCCESS)
+ PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] dump efuse fail !!!\n");
+#endif
+
+ if (dm->support_ic_type & ODM_RTL8821C)
+ phydm_get_power_trim_offset_8821c(dm_void);
+ else if (dm->support_ic_type & ODM_RTL8822B)
+ phydm_get_power_trim_offset_8822b(dm_void);
+ else if (dm->support_ic_type & ODM_RTL8710B)
+ phydm_get_power_trim_offset_8710b(dm_void);
+
+}
+
+
+
+void
+phydm_get_pa_bias_offset(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+ void *adapter = dm->adapter;
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+ PEFUSE_HAL pEfuseHal = &hal_data->EfuseHal;
+ u1Byte eFuseContent[DCMD_EFUSE_MAX_SECTION_NUM * EFUSE_MAX_WORD_UNIT * 2];
+
+ if (HAL_MAC_Dump_EFUSE(&GET_HAL_MAC_INFO((PADAPTER)adapter), EFUSE_WIFI, eFuseContent, pEfuseHal->PhysicalLen_WiFi, HAL_MAC_EFUSE_PHYSICAL, HAL_MAC_EFUSE_PARSE_DRV) != RT_STATUS_SUCCESS)
+ PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] dump efuse fail !!!\n");
+#endif
+
+ if (dm->support_ic_type & ODM_RTL8822B)
+ phydm_get_pa_bias_offset_8822b(dm_void);
+}
+
+
+
+s8
+phydm_get_thermal_offset(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
+
+ if (power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON)
+ return power_trim_info->thermal;
+ else
+ return 0;
+}
+
+
+
+void
+phydm_config_kfree(
+ void *dm_void,
+ u8 channel_to_sw
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
+ struct odm_power_trim_data *power_trim_info = &dm->power_trim_data;
+
+ u8 rfpath = 0, max_rf_path = 0;
+ u8 channel_idx = 0, i, j;
+
+ if (dm->support_ic_type & ODM_RTL8814A)
+ max_rf_path = 4; /*0~3*/
+ else if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E | ODM_RTL8822B))
+ max_rf_path = 2; /*0~1*/
+ else if (dm->support_ic_type & (ODM_RTL8821C| ODM_RTL8710B))
+ max_rf_path = 1;
+
+ PHYDM_DBG(dm, ODM_COMP_MP, "===>[kfree] phy_ConfigKFree()\n");
+
+ if (cali_info->reg_rf_kfree_enable == 2) {
+ PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] phy_ConfigKFree(): reg_rf_kfree_enable == 2, Disable\n");
+ return;
+ } else if (cali_info->reg_rf_kfree_enable == 1 || cali_info->reg_rf_kfree_enable == 0) {
+ PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] phy_ConfigKFree(): reg_rf_kfree_enable == true\n");
+ /*Make sure the targetval is defined*/
+ if (!(power_trim_info->flag & KFREE_FLAG_ON)) {
+ PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] phy_ConfigKFree(): targetval not defined, Don't execute KFree Process.\n");
+ return;
+ }
+ /*if kfree_table[0] == 0xff, means no Kfree*/
+ if (dm->support_ic_type &ODM_RTL8710B)
+ ODM_RT_TRACE(dm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] power_trim_data->bb_gain[0][0]=0x%X\n", power_trim_info->bb_gain[0][0]));
+ else if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E | ODM_RTL8822B |ODM_RTL8821C | ODM_RTL8814A)){
+ for (i = 0; i < KFREE_BAND_NUM; i++) {
+ for (j = 0; j < max_rf_path; j++)
+ PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] power_trim_data->bb_gain[%d][%d]=0x%X\n", i, j, power_trim_info->bb_gain[i][j]);
+ }
+ }
+ if (*dm->band_type == ODM_BAND_2_4G && power_trim_info->flag & KFREE_FLAG_ON_2G) {
+ if (channel_to_sw >= 1 && channel_to_sw <= 14)
+ channel_idx = PHYDM_2G;
+
+ for (rfpath = RF_PATH_A; rfpath < max_rf_path; rfpath++) {
+ PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] phydm_kfree(): channel_to_sw=%d PATH_%d bb_gain:0x%X\n", channel_to_sw, rfpath, power_trim_info->bb_gain[channel_idx][rfpath]);
+ phydm_set_kfree_to_rf(dm, rfpath, power_trim_info->bb_gain[channel_idx][rfpath]);
+ }
+
+ } else if (*dm->band_type == ODM_BAND_5G && power_trim_info->flag & KFREE_FLAG_ON_5G) {
+ if (channel_to_sw >= 36 && channel_to_sw <= 48)
+ channel_idx = PHYDM_5GLB1;
+ if (channel_to_sw >= 52 && channel_to_sw <= 64)
+ channel_idx = PHYDM_5GLB2;
+ if (channel_to_sw >= 100 && channel_to_sw <= 120)
+ channel_idx = PHYDM_5GMB1;
+ if (channel_to_sw >= 122 && channel_to_sw <= 144)
+ channel_idx = PHYDM_5GMB2;
+ if (channel_to_sw >= 149 && channel_to_sw <= 177)
+ channel_idx = PHYDM_5GHB;
+
+ for (rfpath = RF_PATH_A; rfpath < max_rf_path; rfpath++) {
+ PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] phydm_kfree(): channel_to_sw=%d PATH_%d bb_gain:0x%X\n", channel_to_sw, rfpath, power_trim_info->bb_gain[channel_idx][rfpath]);
+ phydm_set_kfree_to_rf(dm, rfpath, power_trim_info->bb_gain[channel_idx][rfpath]);
+ }
+ } else {
+ PHYDM_DBG(dm, ODM_COMP_MP, "[kfree] Set default Register\n");
+ for (rfpath = RF_PATH_A; rfpath < max_rf_path; rfpath++)
+ phydm_clear_kfree_to_rf(dm, rfpath, power_trim_info->bb_gain[channel_idx][rfpath]);
+ }
+ }
+
+ PHYDM_DBG(dm, ODM_COMP_MP, "<===[kfree] phy_ConfigKFree()\n");
+}
diff --git a/hal/phydm/halrf/halrf_kfree.h b/hal/phydm/halrf/halrf_kfree.h
new file mode 100644
index 0000000..a5159d1
--- /dev/null
+++ b/hal/phydm/halrf/halrf_kfree.h
@@ -0,0 +1,142 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger
+ *
+ *****************************************************************************/
+
+
+#ifndef __PHYDMKFREE_H__
+#define __PHYDKFREE_H__
+
+#define KFREE_VERSION "1.0"
+
+#define KFREE_BAND_NUM 6
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_AP))
+
+#define BB_GAIN_NUM 6
+
+#endif
+
+#define KFREE_FLAG_ON BIT(0)
+#define KFREE_FLAG_THERMAL_K_ON BIT(1)
+
+#define KFREE_FLAG_ON_2G BIT(2)
+#define KFREE_FLAG_ON_5G BIT(3)
+
+#define PA_BIAS_FLAG_ON BIT(4)
+
+#define PPG_THERMAL_OFFSET_8821C 0x1EF
+#define PPG_BB_GAIN_2G_TXAB_OFFSET_8821C 0x1EE
+#define PPG_BB_GAIN_5GL1_TXA_OFFSET_8821C 0x1EC
+#define PPG_BB_GAIN_5GL2_TXA_OFFSET_8821C 0x1E8
+#define PPG_BB_GAIN_5GM1_TXA_OFFSET_8821C 0x1E4
+#define PPG_BB_GAIN_5GM2_TXA_OFFSET_8821C 0x1E0
+#define PPG_BB_GAIN_5GH1_TXA_OFFSET_8821C 0x1DC
+
+
+
+#define PPG_THERMAL_OFFSET 0x3EF
+#define PPG_BB_GAIN_2G_TXAB_OFFSET 0x3EE
+#define PPG_BB_GAIN_2G_TXCD_OFFSET 0x3ED
+#define PPG_BB_GAIN_5GL1_TXA_OFFSET 0x3EC
+#define PPG_BB_GAIN_5GL1_TXB_OFFSET 0x3EB
+#define PPG_BB_GAIN_5GL1_TXC_OFFSET 0x3EA
+#define PPG_BB_GAIN_5GL1_TXD_OFFSET 0x3E9
+#define PPG_BB_GAIN_5GL2_TXA_OFFSET 0x3E8
+#define PPG_BB_GAIN_5GL2_TXB_OFFSET 0x3E7
+#define PPG_BB_GAIN_5GL2_TXC_OFFSET 0x3E6
+#define PPG_BB_GAIN_5GL2_TXD_OFFSET 0x3E5
+#define PPG_BB_GAIN_5GM1_TXA_OFFSET 0x3E4
+#define PPG_BB_GAIN_5GM1_TXB_OFFSET 0x3E3
+#define PPG_BB_GAIN_5GM1_TXC_OFFSET 0x3E2
+#define PPG_BB_GAIN_5GM1_TXD_OFFSET 0x3E1
+#define PPG_BB_GAIN_5GM2_TXA_OFFSET 0x3E0
+#define PPG_BB_GAIN_5GM2_TXB_OFFSET 0x3DF
+#define PPG_BB_GAIN_5GM2_TXC_OFFSET 0x3DE
+#define PPG_BB_GAIN_5GM2_TXD_OFFSET 0x3DD
+#define PPG_BB_GAIN_5GH1_TXA_OFFSET 0x3DC
+#define PPG_BB_GAIN_5GH1_TXB_OFFSET 0x3DB
+#define PPG_BB_GAIN_5GH1_TXC_OFFSET 0x3DA
+#define PPG_BB_GAIN_5GH1_TXD_OFFSET 0x3D9
+
+#define PPG_PA_BIAS_2G_TXA_OFFSET 0x3D5
+#define PPG_PA_BIAS_2G_TXB_OFFSET 0x3D6
+
+
+
+struct odm_power_trim_data {
+ u8 flag;
+ u8 pa_bias_flag;
+ s8 bb_gain[KFREE_BAND_NUM][MAX_RF_PATH];
+ s8 thermal;
+};
+
+
+
+enum phydm_kfree_channeltosw {
+ PHYDM_2G = 0,
+ PHYDM_5GLB1 = 1,
+ PHYDM_5GLB2 = 2,
+ PHYDM_5GMB1 = 3,
+ PHYDM_5GMB2 = 4,
+ PHYDM_5GHB = 5,
+};
+
+
+
+void
+phydm_get_thermal_trim_offset(
+ void *dm_void
+);
+
+void
+phydm_get_power_trim_offset(
+ void *dm_void
+);
+
+void
+phydm_get_pa_bias_offset(
+ void *dm_void
+);
+
+s8
+phydm_get_thermal_offset(
+ void *dm_void
+);
+
+void
+phydm_clear_kfree_to_rf(
+ void *dm_void,
+ u8 e_rf_path,
+ u8 data
+);
+
+
+void
+phydm_config_kfree(
+ void *dm_void,
+ u8 channel_to_sw
+);
+
+
+#endif
diff --git a/hal/phydm/halrf/halrf_powertracking.c b/hal/phydm/halrf/halrf_powertracking.c
new file mode 100644
index 0000000..db751bd
--- /dev/null
+++ b/hal/phydm/halrf/halrf_powertracking.c
@@ -0,0 +1,159 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger
+ *
+ *****************************************************************************/
+
+/* ************************************************************
+ * include files
+ * ************************************************************ */
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+
+boolean
+odm_check_power_status(
+ void *dm_void
+)
+{
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ PADAPTER adapter = (PADAPTER)dm->adapter;
+
+ RT_RF_POWER_STATE rt_state;
+ MGNT_INFO *mgnt_info = &adapter->MgntInfo;
+
+ /* 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. */
+ if (mgnt_info->init_adpt_in_progress == true) {
+ PHYDM_DBG(dm, ODM_COMP_INIT, "check_pow_status Return true, due to initadapter\n");
+ return true;
+ }
+
+ /* */
+ /* 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. */
+ /* */
+ adapter->HalFunc.GetHwRegHandler(adapter, HW_VAR_RF_STATE, (u8 *)(&rt_state));
+ if (adapter->bDriverStopped || adapter->bDriverIsGoingToPnpSetPowerSleep || rt_state == eRfOff) {
+ PHYDM_DBG(dm, ODM_COMP_INIT, "check_pow_status Return false, due to %d/%d/%d\n",
+ adapter->bDriverStopped, adapter->bDriverIsGoingToPnpSetPowerSleep, rt_state);
+ return false;
+ }
+#endif
+ return true;
+
+}
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+void
+halrf_update_pwr_track(
+ void *dm_void,
+ u8 rate
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+ u8 path_idx = 0;
+#endif
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "Pwr Track Get rate=0x%x\n", rate);
+
+ dm->tx_rate = rate;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+#if DEV_BUS_TYPE == RT_PCI_INTERFACE
+#if USE_WORKITEM
+ odm_schedule_work_item(&dm->ra_rpt_workitem);
+#else
+ if (dm->support_ic_type == ODM_RTL8821) {
+#if (RTL8821A_SUPPORT == 1)
+ odm_tx_pwr_track_set_pwr8821a(dm, MIX_MODE, RF_PATH_A, 0);
+#endif
+ } else if (dm->support_ic_type == ODM_RTL8812) {
+ for (path_idx = RF_PATH_A; path_idx < MAX_PATH_NUM_8812A; path_idx++) {
+#if (RTL8812A_SUPPORT == 1)
+ odm_tx_pwr_track_set_pwr8812a(dm, MIX_MODE, path_idx, 0);
+#endif
+ }
+ } else if (dm->support_ic_type == ODM_RTL8723B) {
+#if (RTL8723B_SUPPORT == 1)
+ odm_tx_pwr_track_set_pwr_8723b(dm, MIX_MODE, RF_PATH_A, 0);
+#endif
+ } else if (dm->support_ic_type == ODM_RTL8192E) {
+ for (path_idx = RF_PATH_A; path_idx < MAX_PATH_NUM_8192E; path_idx++) {
+#if (RTL8192E_SUPPORT == 1)
+ odm_tx_pwr_track_set_pwr92_e(dm, MIX_MODE, path_idx, 0);
+#endif
+ }
+ } else if (dm->support_ic_type == ODM_RTL8188E) {
+#if (RTL8188E_SUPPORT == 1)
+ odm_tx_pwr_track_set_pwr88_e(dm, MIX_MODE, RF_PATH_A, 0);
+#endif
+ }
+#endif
+#else
+ odm_schedule_work_item(&dm->ra_rpt_workitem);
+#endif
+#endif
+
+}
+
+#endif
+
+
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+void
+halrf_update_init_rate_work_item_callback(
+ void *context
+)
+{
+ void *adapter = (void *)context;
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+ struct dm_struct *dm = &hal_data->DM_OutSrc;
+ u8 p = 0;
+
+ if (dm->support_ic_type == ODM_RTL8821) {
+ odm_tx_pwr_track_set_pwr8821a(dm, MIX_MODE, RF_PATH_A, 0);
+ /**/
+ } else if (dm->support_ic_type == ODM_RTL8812) {
+ for (p = RF_PATH_A; p < MAX_PATH_NUM_8812A; p++) { /*DOn't know how to include &c*/
+
+ odm_tx_pwr_track_set_pwr8812a(dm, MIX_MODE, p, 0);
+ /**/
+ }
+ } else if (dm->support_ic_type == ODM_RTL8723B) {
+ odm_tx_pwr_track_set_pwr_8723b(dm, MIX_MODE, RF_PATH_A, 0);
+ /**/
+ } else if (dm->support_ic_type == ODM_RTL8192E) {
+ for (p = RF_PATH_A; p < MAX_PATH_NUM_8192E; p++) { /*DOn't know how to include &c*/
+ odm_tx_pwr_track_set_pwr92_e(dm, MIX_MODE, p, 0);
+ /**/
+ }
+ } else if (dm->support_ic_type == ODM_RTL8188E) {
+ odm_tx_pwr_track_set_pwr88_e(dm, MIX_MODE, RF_PATH_A, 0);
+ /**/
+ }
+}
+#endif
+
+
+
diff --git a/hal/phydm/halrf/halrf_powertracking.h b/hal/phydm/halrf/halrf_powertracking.h
new file mode 100644
index 0000000..15e056b
--- /dev/null
+++ b/hal/phydm/halrf/halrf_powertracking.h
@@ -0,0 +1,50 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger
+ *
+ *****************************************************************************/
+
+#ifndef __HALRF_POWER_TRACKING_H__
+#define __HALRF_POWER_TRACKING_H__
+
+
+boolean
+odm_check_power_status(
+ void *dm_void
+);
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+void
+halrf_update_pwr_track(
+ void *dm_void,
+ u8 rate
+);
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+void
+halrf_update_init_rate_work_item_callback(
+ void *context
+);
+#endif
+
+#endif
diff --git a/hal/phydm/halrf/halrf_powertracking_ap.c b/hal/phydm/halrf/halrf_powertracking_ap.c
new file mode 100644
index 0000000..4e4e6a7
--- /dev/null
+++ b/hal/phydm/halrf/halrf_powertracking_ap.c
@@ -0,0 +1,1158 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+/* ************************************************************
+ * include files
+ * ************************************************************ */
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+#if !defined(_OUTSRC_COEXIST)
+/* ************************************************************
+ * Global var
+ * ************************************************************ */
+
+
+u32 ofdm_swing_table_new[OFDM_TABLE_SIZE_92D] = {
+ 0x0b40002d, /* 0, -15.0dB */
+ 0x0c000030, /* 1, -14.5dB */
+ 0x0cc00033, /* 2, -14.0dB */
+ 0x0d800036, /* 3, -13.5dB */
+ 0x0e400039, /* 4, -13.0dB */
+ 0x0f00003c, /* 5, -12.5dB */
+ 0x10000040, /* 6, -12.0dB */
+ 0x11000044, /* 7, -11.5dB */
+ 0x12000048, /* 8, -11.0dB */
+ 0x1300004c, /* 9, -10.5dB */
+ 0x14400051, /* 10, -10.0dB */
+ 0x15800056, /* 11, -9.5dB */
+ 0x16c0005b, /* 12, -9.0dB */
+ 0x18000060, /* 13, -8.5dB */
+ 0x19800066, /* 14, -8.0dB */
+ 0x1b00006c, /* 15, -7.5dB */
+ 0x1c800072, /* 16, -7.0dB */
+ 0x1e400079, /* 17, -6.5dB */
+ 0x20000080, /* 18, -6.0dB */
+ 0x22000088, /* 19, -5.5dB */
+ 0x24000090, /* 20, -5.0dB */
+ 0x26000098, /* 21, -4.5dB */
+ 0x288000a2, /* 22, -4.0dB */
+ 0x2ac000ab, /* 23, -3.5dB */
+ 0x2d4000b5, /* 24, -3.0dB */
+ 0x300000c0, /* 25, -2.5dB */
+ 0x32c000cb, /* 26, -2.0dB */
+ 0x35c000d7, /* 27, -1.5dB */
+ 0x390000e4, /* 28, -1.0dB */
+ 0x3c8000f2, /* 29, -0.5dB */
+ 0x40000100, /* 30, +0dB */
+ 0x43c0010f, /* 31, +0.5dB */
+ 0x47c0011f, /* 32, +1.0dB */
+ 0x4c000130, /* 33, +1.5dB */
+ 0x50800142, /* 34, +2.0dB */
+ 0x55400155, /* 35, +2.5dB */
+ 0x5a400169, /* 36, +3.0dB */
+ 0x5fc0017f, /* 37, +3.5dB */
+ 0x65400195, /* 38, +4.0dB */
+ 0x6b8001ae, /* 39, +4.5dB */
+ 0x71c001c7, /* 40, +5.0dB */
+ 0x788001e2, /* 41, +5.5dB */
+ 0x7f8001fe /* 42, +6.0dB */
+};
+
+u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = {
+ {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, /* 0, -16.0dB */
+ {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 1, -15.5dB */
+ {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 2, -15.0dB */
+ {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 3, -14.5dB */
+ {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 4, -14.0dB */
+ {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 5, -13.5dB */
+ {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 6, -13.0dB */
+ {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 7, -12.5dB */
+ {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 8, -12.0dB */
+ {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 9, -11.5dB */
+ {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 10, -11.0dB */
+ {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 11, -10.5dB */
+ {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 12, -10.0dB */
+ {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 13, -9.5dB */
+ {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 14, -9.0dB */
+ {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 15, -8.5dB */
+ {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
+ {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 17, -7.5dB */
+ {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 18, -7.0dB */
+ {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 19, -6.5dB */
+ {0x1c, 0x1a, 0x18, 0x12, 0x0e, 0x08, 0x04, 0x02}, /* 20, -6.0dB */
+ {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 21, -5.5dB */
+ {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 22, -5.0dB */
+ {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 23, -4.5dB */
+ {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 24, -4.0dB */
+ {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 25, -3.5dB */
+ {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 26, -3.0dB */
+ {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 27, -2.5dB */
+ {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 28, -2.0dB */
+ {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 29, -1.5dB */
+ {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 30, -1.0dB */
+ {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 31, -0.5dB */
+ {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} /* 32, +0dB */
+};
+
+
+u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = {
+ {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, /* 0, -16.0dB */
+ {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 1, -15.5dB */
+ {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 2, -15.0dB */
+ {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 3, -14.5dB */
+ {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 4, -14.0dB */
+ {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 5, -13.5dB */
+ {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 6, -13.0dB */
+ {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 7, -12.5dB */
+ {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 8, -12.0dB */
+ {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 9, -11.5dB */
+ {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 10, -11.0dB */
+ {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 11, -10.5dB */
+ {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 12, -10.0dB */
+ {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 13, -9.5dB */
+ {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 14, -9.0dB */
+ {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 15, -8.5dB */
+ {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
+ {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 17, -7.5dB */
+ {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 18, -7.0dB */
+ {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 19, -6.5dB */
+ {0x1c, 0x1a, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 20, -6.0dB */
+ {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 21, -5.5dB */
+ {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 22, -5.0dB */
+ {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 23, -4.5dB */
+ {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 24, -4.0dB */
+ {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 25, -3.5dB */
+ {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 26, -3.0dB */
+ {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 27, -2.5dB */
+ {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 28, -2.0dB */
+ {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 29, -1.5dB */
+ {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 30, -1.0dB */
+ {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 31, -0.5dB */
+ {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} /* 32, +0dB */
+};
+
+u32 ofdm_swing_table[OFDM_TABLE_SIZE_92D] = {
+ 0x0b40002d, /* 0, -15.0dB */
+ 0x0c000030, /* 1, -14.5dB */
+ 0x0cc00033, /* 2, -14.0dB */
+ 0x0d800036, /* 3, -13.5dB */
+ 0x0e400039, /* 4, -13.0dB */
+ 0x0f00003c, /* 5, -12.5dB */
+ 0x10000040, /* 6, -12.0dB */
+ 0x11000044, /* 7, -11.5dB */
+ 0x12000048, /* 8, -11.0dB */
+ 0x1300004c, /* 9, -10.5dB */
+ 0x14400051, /* 10, -10.0dB */
+ 0x15800056, /* 11, -9.5dB */
+ 0x16c0005b, /* 12, -9.0dB */
+ 0x18000060, /* 13, -8.5dB */
+ 0x19800066, /* 14, -8.0dB */
+ 0x1b00006c, /* 15, -7.5dB */
+ 0x1c800072, /* 16, -7.0dB */
+ 0x1e400079, /* 17, -6.5dB */
+ 0x20000080, /* 18, -6.0dB */
+ 0x22000088, /* 19, -5.5dB */
+ 0x24000090, /* 20, -5.0dB */
+ 0x26000098, /* 21, -4.5dB */
+ 0x288000a2, /* 22, -4.0dB */
+ 0x2ac000ab, /* 23, -3.5dB */
+ 0x2d4000b5, /* 24, -3.0dB */
+ 0x300000c0, /* 25, -2.5dB */
+ 0x32c000cb, /* 26, -2.0dB */
+ 0x35c000d7, /* 27, -1.5dB */
+ 0x390000e4, /* 28, -1.0dB */
+ 0x3c8000f2, /* 29, -0.5dB */
+ 0x40000100, /* 30, +0dB */
+ 0x43c0010f, /* 31, +0.5dB */
+ 0x47c0011f, /* 32, +1.0dB */
+ 0x4c000130, /* 33, +1.5dB */
+ 0x50800142, /* 34, +2.0dB */
+ 0x55400155, /* 35, +2.5dB */
+ 0x5a400169, /* 36, +3.0dB */
+ 0x5fc0017f, /* 37, +3.5dB */
+ 0x65400195, /* 38, +4.0dB */
+ 0x6b8001ae, /* 39, +4.5dB */
+ 0x71c001c7, /* 40, +5.0dB */
+ 0x788001e2, /* 41, +5.5dB */
+ 0x7f8001fe /* 42, +6.0dB */
+};
+
+
+u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = {
+ {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, /* 0, -16.0dB */
+ {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 1, -15.5dB */
+ {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 2, -15.0dB */
+ {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 3, -14.5dB */
+ {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 4, -14.0dB */
+ {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 5, -13.5dB */
+ {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 6, -13.0dB */
+ {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 7, -12.5dB */
+ {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 8, -12.0dB */
+ {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 9, -11.5dB */
+ {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 10, -11.0dB */
+ {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 11, -10.5dB */
+ {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 12, -10.0dB */
+ {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 13, -9.5dB */
+ {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 14, -9.0dB */
+ {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 15, -8.5dB */
+ {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
+ {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 17, -7.5dB */
+ {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 18, -7.0dB */
+ {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 19, -6.5dB */
+ {0x1c, 0x1a, 0x18, 0x12, 0x0e, 0x08, 0x04, 0x02}, /* 20, -6.0dB */
+ {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 21, -5.5dB */
+ {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 22, -5.0dB */
+ {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 23, -4.5dB */
+ {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 24, -4.0dB */
+ {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 25, -3.5dB */
+ {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 26, -3.0dB */
+ {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 27, -2.5dB */
+ {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 28, -2.0dB */
+ {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 29, -1.5dB */
+ {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 30, -1.0dB */
+ {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 31, -0.5dB */
+ {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} /* 32, +0dB */
+};
+
+
+u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8] = {
+ {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, /* 0, -16.0dB */
+ {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 1, -15.5dB */
+ {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 2, -15.0dB */
+ {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 3, -14.5dB */
+ {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 4, -14.0dB */
+ {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 5, -13.5dB */
+ {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 6, -13.0dB */
+ {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 7, -12.5dB */
+ {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 8, -12.0dB */
+ {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 9, -11.5dB */
+ {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 10, -11.0dB */
+ {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 11, -10.5dB */
+ {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 12, -10.0dB */
+ {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 13, -9.5dB */
+ {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 14, -9.0dB */
+ {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 15, -8.5dB */
+ {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
+ {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 17, -7.5dB */
+ {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 18, -7.0dB */
+ {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 19, -6.5dB */
+ {0x1c, 0x1a, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 20, -6.0dB */
+ {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 21, -5.5dB */
+ {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 22, -5.0dB */
+ {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 23, -4.5dB */
+ {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 24, -4.0dB */
+ {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 25, -3.5dB */
+ {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 26, -3.0dB */
+ {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 27, -2.5dB */
+ {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 28, -2.0dB */
+ {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 29, -1.5dB */
+ {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 30, -1.0dB */
+ {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 31, -0.5dB */
+ {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} /* 32, +0dB */
+};
+
+u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
+ {0x16, 0x15, 0x13, 0x10, 0xD, 0x9, 0x6, 0x3, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 0 -16dB */
+ {0x18, 0x17, 0x15, 0x12, 0xE, 0xA, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 1 -15.5dB */
+ {0x1B, 0x1A, 0x18, 0x14, 0x10, 0xB, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 2 -15dB */
+ {0x1F, 0x1E, 0x1B, 0x17, 0x12, 0xD, 0x8, 0x5, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 3 -14.5dB */
+ {0x22, 0x21, 0x1E, 0x19, 0x14, 0xE, 0x9, 0x5, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 4 -14dB */
+ {0x26, 0x25, 0x22, 0x1C, 0x16, 0x10, 0xA, 0x6, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 5 -13.5dB */
+ {0x2B, 0x2A, 0x26, 0x20, 0x19, 0x12, 0xC, 0x7, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 6 -13dB */
+ {0x30, 0x2F, 0x2A, 0x24, 0x1C, 0x14, 0xD, 0x8, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 7 -12.5dB */
+ {0x36, 0x34, 0x2F, 0x28, 0x1F, 0x17, 0xF, 0x9, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 8 -12dB */
+ {0x3D, 0x3B, 0x35, 0x2D, 0x23, 0x19, 0x11, 0xA, 0x5, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 9 -11.5dB */
+ {0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0xB, 0x5, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 10 -11dB */
+ {0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0xC, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 11 -10.5dB */
+ {0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0xE, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 12 -10dB */
+ {0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0xF, 0x7, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 13 -9.5dB */
+ {0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x8, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 14 -9dB */
+ {0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x9, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 15 -8.5dB */
+ {0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0xA, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 16 -8dB */
+ {0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0xB, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 17 -7.5dB */
+ {0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0xD, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 18 -7dB */
+ {0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0xE, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 19 -6.5dB */
+ {0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x5, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} /* 20 -6dB */
+};
+
+
+u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = {
+ {0x16, 0x15, 0x13, 0x10, 0xD, 0x9, 0x6, 0x3, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 0 -16dB */
+ {0x18, 0x17, 0x15, 0x12, 0xE, 0xA, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 1 -15.5dB */
+ {0x1B, 0x1A, 0x18, 0x14, 0x10, 0xB, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 2 -15dB */
+ {0x1F, 0x1E, 0x1B, 0x17, 0x12, 0xD, 0x8, 0x5, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 3 -14.5dB */
+ {0x22, 0x21, 0x1E, 0x19, 0x14, 0xE, 0x9, 0x5, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 4 -14dB */
+ {0x26, 0x25, 0x22, 0x1C, 0x16, 0x10, 0xA, 0x6, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 5 -13.5dB */
+ {0x2B, 0x2A, 0x26, 0x20, 0x19, 0x12, 0xC, 0x7, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 6 -13dB */
+ {0x30, 0x2F, 0x2A, 0x24, 0x1C, 0x14, 0xD, 0x8, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 7 -12.5dB */
+ {0x36, 0x34, 0x2F, 0x28, 0x1F, 0x17, 0xF, 0x9, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 8 -12dB */
+ {0x3D, 0x3B, 0x35, 0x2D, 0x23, 0x19, 0x11, 0xA, 0x5, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 9 -11.5dB */
+ {0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0xB, 0x5, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 10 -11dB */
+ {0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0xC, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 11 -10.5dB */
+ {0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0xE, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 12 -10dB */
+ {0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0xF, 0x7, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 13 -9.5dB */
+ {0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x8, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 14 -9dB */
+ {0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x9, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 15 -8.5dB */
+ {0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0xA, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 16 -8dB */
+ {0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0xB, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 17 -7.5dB */
+ {0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0xD, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 18 -7dB */
+ {0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0xE, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 19 -6.5dB */
+ {0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x5, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} /* 20 -6dB */
+};
+
+
+u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
+ {0x44, 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
+ {0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
+ {0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
+ {0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
+ {0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
+ {0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
+ {0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
+ {0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
+ {0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
+ {0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
+ {0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
+ {0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
+ {0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
+ {0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
+ {0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
+ {0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
+ {0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
+ {0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
+ {0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
+ {0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
+ {0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
+};
+
+
+
+#if 0
+u32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E] = {
+ /* Index0 6 dB */ 0x7fc001ff,
+ /* Index1 5.7dB */ 0x7b4001ed,
+ /* Index2 5.4dB */ 0x774001dd,
+ /* Index3 5.1dB */ 0x734001cd,
+ /* Index4 4.8dB */ 0x6f4001bd,
+ /* Index5 4.5dB */ 0x6b8001ae,
+ /* Index6 4.2dB */ 0x67c0019f,
+ /* Index7 3.9dB */ 0x64400191,
+ /* Index8 3.6dB */ 0x60c00183,
+ /* Index9 3.3dB */ 0x5d800176,
+ /* Index10 3 dB */ 0x5a80016a,
+ /* Index11 2.7dB */ 0x5740015d,
+ /* Index12 2.4dB */ 0x54400151,
+ /* Index13 2.1dB */ 0x51800146,
+ /* Index14 1.8dB */ 0x4ec0013b,
+ /* Index15 1.5dB */ 0x4c000130,
+ /* Index16 1.2dB */ 0x49800126,
+ /* Index17 0.9dB */ 0x4700011c,
+ /* Index18 0.6dB */ 0x44800112,
+ /* Index19 0.3dB */ 0x42000108,
+ /* Index20 0 dB */ 0x40000100, /* 20 This is OFDM base index */
+ /* Index21 -0.3dB */ 0x3dc000f7,
+ /* Index22 -0.6dB */ 0x3bc000ef,
+ /* Index23 -0.9dB */ 0x39c000e7,
+ /* Index24 -1.2dB */ 0x37c000df,
+ /* Index25 -1.5dB */ 0x35c000d7,
+ /* Index26 -1.8dB */ 0x340000d0,
+ /* Index27 -2.1dB */ 0x324000c9,
+ /* Index28 -2.4dB */ 0x308000c2,
+ /* Index29 -2.7dB */ 0x2f0000bc,
+ /* Index30 -3 dB */ 0x2d4000b5,
+ /* Index31 -3.3dB */ 0x2bc000af,
+ /* Index32 -3.6dB */ 0x2a4000a9,
+ /* Index33 -3.9dB */ 0x28c000a3,
+ /* Index34 -4.2dB */ 0x2780009e,
+ /* Index35 -4.5dB */ 0x26000098,
+ /* Index36 -4.8dB */ 0x24c00093,
+ /* Index37 -5.1dB */ 0x2380008e,
+ /* Index38 -5.4dB */ 0x22400089,
+ /* Index39 -5.7dB */ 0x21400085,
+ /* Index40 -6 dB */ 0x20000080,
+ /* Index41 -6.3dB */ 0x1f00007c,
+ /* Index42 -6.6dB */ 0x1e000078,
+ /* Index43 -6.9dB */ 0x1d000074,
+ /* Index44 -7.2dB */ 0x1c000070,
+ /* Index45 -7.5dB */ 0x1b00006c,
+ /* Index46 -7.8dB */ 0x1a000068,
+ /* Index47 -8.1dB */ 0x19400065,
+ /* Index48 -8.4dB */ 0x18400061,
+ /* Index49 -8.7dB */ 0x1780005e,
+ /* Index50 -9 dB */ 0x16c0005b,
+ /* Index51 -9.3dB */ 0x16000058,
+ /* Index52 -9.6dB */ 0x15400055,
+ /* Index53 -9.9dB */ 0x14800052
+};
+u8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8] = {
+ /* Index0 0 dB */ {0x36, 0x34, 0x2E, 0x26, 0x1C, 0x12, 0x08, 0x04},
+ /* Index1 -0.3dB */ {0x34, 0x32, 0x2C, 0x25, 0x1B, 0x11, 0x08, 0x04},
+ /* Index2 -0.6dB */ {0x32, 0x30, 0x2B, 0x23, 0x1A, 0x11, 0x07, 0x04},
+ /* Index3 -0.9dB */ {0x31, 0x2F, 0x29, 0x22, 0x19, 0x10, 0x07, 0x04},
+ /* Index4 -1.2dB */ {0x2F, 0x2D, 0x28, 0x21, 0x18, 0x10, 0x07, 0x03},
+ /* Index5 -1.5dB */ {0x2D, 0x2C, 0x27, 0x20, 0x18, 0x0F, 0x07, 0x03},
+ /* Index6 -1.8dB */ {0x2C, 0x2A, 0x25, 0x1F, 0x17, 0x0F, 0x06, 0x03},
+ /* Index7 -2.1dB */ {0x2A, 0x29, 0x24, 0x1E, 0x16, 0x0E, 0x06, 0x03},
+ /* Index8 -2.4dB */ {0x29, 0x27, 0x23, 0x1D, 0x15, 0x0E, 0x06, 0x03},
+ /* Index9 -2.7dB */ {0x27, 0x26, 0x22, 0x1C, 0x14, 0x0D, 0x06, 0x03},
+ /* Index10 -3 dB */ {0x26, 0x25, 0x20, 0x1B, 0x14, 0x0D, 0x06, 0x03},
+ /* Index11 -3.3dB */ {0x25, 0x23, 0x1F, 0x1A, 0x13, 0x0C, 0x05, 0x03},
+ /* Index12 -3.6dB */ {0x24, 0x22, 0x1E, 0x19, 0x12, 0x0C, 0x05, 0x03},
+ /* Index13 -3.9dB */ {0x22, 0x21, 0x1D, 0x18, 0x12, 0x0B, 0x05, 0x03},
+ /* Index14 -4.2dB */ {0x21, 0x20, 0x1C, 0x17, 0x11, 0x0B, 0x05, 0x02},
+ /* Index15 -4.5dB */ {0x20, 0x1F, 0x1B, 0x17, 0x11, 0x0B, 0x05, 0x02},
+ /* Index16 -4.8dB */ {0x1F, 0x1E, 0x1A, 0x16, 0x10, 0x0A, 0x05, 0x02},
+ /* Index17 -5.1dB */ {0x1E, 0x1D, 0x1A, 0x15, 0x10, 0x0A, 0x04, 0x02},
+ /* Index18 -5.4dB */ {0x1D, 0x1C, 0x19, 0x14, 0x0F, 0x0A, 0x04, 0x02},
+ /* Index19 -5.7dB */ {0x1C, 0x1B, 0x18, 0x14, 0x0E, 0x09, 0x04, 0x02},
+ /* Index20 -6.0dB */ {0x1B, 0x1A, 0x17, 0x13, 0x0E, 0x09, 0x04, 0x02}, /* 20 This is CCK base index */
+ /* Index21 -6.3dB */ {0x1A, 0x19, 0x16, 0x12, 0x0E, 0x09, 0x04, 0x02},
+ /* Index22 -6.6dB */ {0x19, 0x18, 0x15, 0x12, 0x0D, 0x08, 0x04, 0x02},
+ /* Index23 -6.9dB */ {0x18, 0x17, 0x15, 0x11, 0x0D, 0x08, 0x04, 0x02},
+ /* Index24 -7.2dB */ {0x18, 0x17, 0x14, 0x11, 0x0C, 0x08, 0x03, 0x02},
+ /* Index25 -7.5dB */ {0x17, 0x16, 0x13, 0x10, 0x0C, 0x08, 0x03, 0x02},
+ /* Index26 -7.8dB */ {0x16, 0x15, 0x13, 0x0F, 0x0B, 0x07, 0x03, 0x02},
+ /* Index27 -8.1dB */ {0x15, 0x14, 0x12, 0x0F, 0x0B, 0x07, 0x03, 0x02},
+ /* Index28 -8.4dB */ {0x14, 0x14, 0x11, 0x0E, 0x0B, 0x07, 0x03, 0x02},
+ /* Index29 -8.7dB */ {0x14, 0x13, 0x11, 0x0E, 0x0A, 0x07, 0x03, 0x01},
+ /* Index30 -9.0dB */ {0x13, 0x12, 0x10, 0x0D, 0x0A, 0x06, 0x03, 0x01}, /* 30 This is hp CCK base index */
+ /* Index31 -9.3dB */ {0x12, 0x12, 0x0F, 0x0D, 0x0A, 0x06, 0x03, 0x01},
+ /* Index32 -9.6dB */ {0x12, 0x11, 0x0F, 0x0D, 0x09, 0x06, 0x03, 0x01},
+ /* Index33 -9.9dB */ {0x11, 0x11, 0x0F, 0x0C, 0x09, 0x06, 0x03, 0x01},
+ /* Index34 -10.2dB */ {0x11, 0x11, 0x0E, 0x0C, 0x09, 0x06, 0x02, 0x01},
+ /* Index35 -10.5dB */ {0x10, 0x0F, 0x0E, 0x0B, 0x08, 0x05, 0x02, 0x01},
+ /* Index36 -10.8dB */ {0x10, 0x0F, 0x0D, 0x0B, 0x08, 0x05, 0x02, 0x01},
+ /* Index37 -11.1dB */ {0x0F, 0x0E, 0x0D, 0x0A, 0x08, 0x05, 0x02, 0x01},
+ /* Index38 -11.4dB */ {0x0E, 0x0E, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01},
+ /* Index39 -11.7dB */ {0x0E, 0x0D, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01},
+ /* Index40 -12 dB */ {0x0E, 0x0D, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01},
+ /* Index41 -12.3dB */ {0x0D, 0x0D, 0x0B, 0x09, 0x07, 0x04, 0x02, 0x01},
+ /* Index42 -12.6dB */ {0x0D, 0x0C, 0x0B, 0x09, 0x07, 0x04, 0x02, 0x01},
+ /* Index43 -12.9dB */ {0x0C, 0x0C, 0x0A, 0x09, 0x06, 0x04, 0x02, 0x01},
+ /* Index44 -13.2dB */ {0x0C, 0x0B, 0x0A, 0x08, 0x06, 0x04, 0x02, 0x01},
+ /* Index45 -13.5dB */ {0x0B, 0x0B, 0x0A, 0x08, 0x06, 0x04, 0x02, 0x01},
+ /* Index46 -13.8dB */ {0x0B, 0x0B, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},
+ /* Index47 -14.1dB */ {0x0B, 0x0A, 0x09, 0x07, 0x06, 0x04, 0x02, 0x01},
+ /* Index48 -14.4dB */ {0x0A, 0x0A, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},
+ /* Index49 -14.7dB */ {0x0A, 0x0A, 0x08, 0x07, 0x05, 0x03, 0x01, 0x01},
+ /* Index50 -15 dB */ {0x0A, 0x09, 0x08, 0x07, 0x05, 0x03, 0x01, 0x01},
+ /* Index51 -15.3dB */ {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
+ /* Index52 -15.6dB */ {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
+ /* Index53 -15.9dB */ {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}
+};
+u8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8] = {
+ /* Index0 0 dB */ {0x36, 0x34, 0x2E, 0x26, 0x00, 0x00, 0x00, 0x00},
+ /* Index1 -0.3dB */ {0x34, 0x32, 0x2C, 0x25, 0x00, 0x00, 0x00, 0x00},
+ /* Index2 -0.6dB */ {0x32, 0x30, 0x2B, 0x23, 0x00, 0x00, 0x00, 0x00},
+ /* Index3 -0.9dB */ {0x31, 0x2F, 0x29, 0x22, 0x00, 0x00, 0x00, 0x00},
+ /* Index4 -1.2dB */ {0x2F, 0x2D, 0x28, 0x21, 0x00, 0x00, 0x00, 0x00},
+ /* Index5 -1.5dB */ {0x2D, 0x2C, 0x27, 0x20, 0x00, 0x00, 0x00, 0x00},
+ /* Index6 -1.8dB */ {0x2C, 0x2A, 0x25, 0x1F, 0x00, 0x00, 0x00, 0x00},
+ /* Index7 -2.1dB */ {0x2A, 0x29, 0x24, 0x1E, 0x00, 0x00, 0x00, 0x00},
+ /* Index8 -2.4dB */ {0x29, 0x27, 0x23, 0x1D, 0x00, 0x00, 0x00, 0x00},
+ /* Index9 -2.7dB */ {0x27, 0x26, 0x22, 0x1C, 0x00, 0x00, 0x00, 0x00},
+ /* Index10 -3 dB */ {0x26, 0x25, 0x20, 0x1B, 0x00, 0x00, 0x00, 0x00},
+ /* Index11 -3.3dB */ {0x25, 0x23, 0x1F, 0x1A, 0x00, 0x00, 0x00, 0x00},
+ /* Index12 -3.6dB */ {0x24, 0x22, 0x1E, 0x19, 0x00, 0x00, 0x00, 0x00},
+ /* Index13 -3.9dB */ {0x22, 0x21, 0x1D, 0x18, 0x00, 0x00, 0x00, 0x00},
+ /* Index14 -4.2dB */ {0x21, 0x20, 0x1C, 0x17, 0x00, 0x00, 0x00, 0x00},
+ /* Index15 -4.5dB */ {0x20, 0x1F, 0x1B, 0x17, 0x00, 0x00, 0x00, 0x00},
+ /* Index16 -4.8dB */ {0x1F, 0x1E, 0x1A, 0x16, 0x00, 0x00, 0x00, 0x00},
+ /* Index17 -5.1dB */ {0x1E, 0x1D, 0x1A, 0x15, 0x00, 0x00, 0x00, 0x00},
+ /* Index18 -5.4dB */ {0x1D, 0x1C, 0x19, 0x14, 0x00, 0x00, 0x00, 0x00},
+ /* Index19 -5.7dB */ {0x1C, 0x1B, 0x18, 0x14, 0x00, 0x00, 0x00, 0x00},
+ /* Index20 -6 dB */ {0x1B, 0x1A, 0x17, 0x13, 0x00, 0x00, 0x00, 0x00},
+ /* Index21 -6.3dB */ {0x1A, 0x19, 0x16, 0x12, 0x00, 0x00, 0x00, 0x00},
+ /* Index22 -6.6dB */ {0x19, 0x18, 0x15, 0x12, 0x00, 0x00, 0x00, 0x00},
+ /* Index23 -6.9dB */ {0x18, 0x17, 0x15, 0x11, 0x00, 0x00, 0x00, 0x00},
+ /* Index24 -7.2dB */ {0x18, 0x17, 0x14, 0x11, 0x00, 0x00, 0x00, 0x00},
+ /* Index25 -7.5dB */ {0x17, 0x16, 0x13, 0x10, 0x00, 0x00, 0x00, 0x00},
+ /* Index26 -7.8dB */ {0x16, 0x15, 0x13, 0x0F, 0x00, 0x00, 0x00, 0x00},
+ /* Index27 -8.1dB */ {0x15, 0x14, 0x12, 0x0F, 0x00, 0x00, 0x00, 0x00},
+ /* Index28 -8.4dB */ {0x14, 0x14, 0x11, 0x0E, 0x00, 0x00, 0x00, 0x00},
+ /* Index29 -8.7dB */ {0x14, 0x13, 0x11, 0x0E, 0x00, 0x00, 0x00, 0x00},
+ /* Index30 -9 dB */ {0x13, 0x12, 0x10, 0x0D, 0x00, 0x00, 0x00, 0x00},
+ /* Index31 -9.3dB */ {0x12, 0x12, 0x0F, 0x0D, 0x00, 0x00, 0x00, 0x00},
+ /* Index32 -9.6dB */ {0x12, 0x11, 0x0F, 0x0D, 0x00, 0x00, 0x00, 0x00},
+ /* Index33 -9.9dB */ {0x11, 0x11, 0x0F, 0x0C, 0x00, 0x00, 0x00, 0x00},
+ /* Index34 -10.2dB */ {0x11, 0x11, 0x0E, 0x0C, 0x00, 0x00, 0x00, 0x00},
+ /* Index35 -10.5dB */ {0x10, 0x0F, 0x0E, 0x0B, 0x00, 0x00, 0x00, 0x00},
+ /* Index36 -10.8dB */ {0x10, 0x0F, 0x0D, 0x0B, 0x00, 0x00, 0x00, 0x00},
+ /* Index37 -11.1dB */ {0x0F, 0x0E, 0x0D, 0x0A, 0x00, 0x00, 0x00, 0x00},
+ /* Index38 -11.4dB */ {0x0E, 0x0E, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00},
+ /* Index39 -11.7dB */ {0x0E, 0x0D, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00},
+ /* Index40 -12 dB */ {0x0E, 0x0D, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00},
+ /* Index41 -12.3dB */ {0x0D, 0x0D, 0x0B, 0x09, 0x00, 0x00, 0x00, 0x00},
+ /* Index42 -12.6dB */ {0x0D, 0x0C, 0x0B, 0x09, 0x00, 0x00, 0x00, 0x00},
+ /* Index43 -12.9dB */ {0x0C, 0x0C, 0x0A, 0x09, 0x00, 0x00, 0x00, 0x00},
+ /* Index44 -13.2dB */ {0x0C, 0x0B, 0x0A, 0x08, 0x00, 0x00, 0x00, 0x00},
+ /* Index45 -13.5dB */ {0x0B, 0x0B, 0x0A, 0x08, 0x00, 0x00, 0x00, 0x00},
+ /* Index46 -13.8dB */ {0x0B, 0x0B, 0x09, 0x08, 0x00, 0x00, 0x00, 0x00},
+ /* Index47 -14.1dB */ {0x0B, 0x0A, 0x09, 0x07, 0x00, 0x00, 0x00, 0x00},
+ /* Index48 -14.4dB */ {0x0A, 0x0A, 0x09, 0x07, 0x00, 0x00, 0x00, 0x00},
+ /* Index49 -14.7dB */ {0x0A, 0x0A, 0x08, 0x07, 0x00, 0x00, 0x00, 0x00},
+ /* Index50 -15 dB */ {0x0A, 0x09, 0x08, 0x07, 0x00, 0x00, 0x00, 0x00},
+ /* Index51 -15.3dB */ {0x09, 0x09, 0x08, 0x06, 0x00, 0x00, 0x00, 0x00},
+ /* Index52 -15.6dB */ {0x09, 0x09, 0x08, 0x06, 0x00, 0x00, 0x00, 0x00},
+ /* Index53 -15.9dB */ {0x09, 0x08, 0x07, 0x06, 0x00, 0x00, 0x00, 0x00}
+};
+#endif
+#endif
+
+
+u8 delta_swing_table_idx_2ga_p_default[DELTA_SWINGIDX_SIZE] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3
+ , 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9
+ };
+u8 delta_swing_table_idx_2ga_n_default[DELTA_SWINGIDX_SIZE] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4
+ , 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11
+ };
+
+
+#ifdef CONFIG_WLAN_HAL_8192EE
+u32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E] = {
+ /* Index0 6 dB */ 0x7fc001ff,
+ /* Index1 5.7dB */ 0x7b4001ed,
+ /* Index2 5.4dB */ 0x774001dd,
+ /* Index3 5.1dB */ 0x734001cd,
+ /* Index4 4.8dB */ 0x6f4001bd,
+ /* Index5 4.5dB */ 0x6b8001ae,
+ /* Index6 4.2dB */ 0x67c0019f,
+ /* Index7 3.9dB */ 0x64400191,
+ /* Index8 3.6dB */ 0x60c00183,
+ /* Index9 3.3dB */ 0x5d800176,
+ /* Index10 3 dB */ 0x5a80016a,
+ /* Index11 2.7dB */ 0x5740015d,
+ /* Index12 2.4dB */ 0x54400151,
+ /* Index13 2.1dB */ 0x51800146,
+ /* Index14 1.8dB */ 0x4ec0013b,
+ /* Index15 1.5dB */ 0x4c000130,
+ /* Index16 1.2dB */ 0x49800126,
+ /* Index17 0.9dB */ 0x4700011c,
+ /* Index18 0.6dB */ 0x44800112,
+ /* Index19 0.3dB */ 0x42000108,
+ /* Index20 0 dB */ 0x40000100, /* 20 This is OFDM base index */
+ /* Index21 -0.3dB */ 0x3dc000f7,
+ /* Index22 -0.6dB */ 0x3bc000ef,
+ /* Index23 -0.9dB */ 0x39c000e7,
+ /* Index24 -1.2dB */ 0x37c000df,
+ /* Index25 -1.5dB */ 0x35c000d7,
+ /* Index26 -1.8dB */ 0x340000d0,
+ /* Index27 -2.1dB */ 0x324000c9,
+ /* Index28 -2.4dB */ 0x308000c2,
+ /* Index29 -2.7dB */ 0x2f0000bc,
+ /* Index30 -3 dB */ 0x2d4000b5,
+ /* Index31 -3.3dB */ 0x2bc000af,
+ /* Index32 -3.6dB */ 0x2a4000a9,
+ /* Index33 -3.9dB */ 0x28c000a3,
+ /* Index34 -4.2dB */ 0x2780009e,
+ /* Index35 -4.5dB */ 0x26000098,
+ /* Index36 -4.8dB */ 0x24c00093,
+ /* Index37 -5.1dB */ 0x2380008e,
+ /* Index38 -5.4dB */ 0x22400089,
+ /* Index39 -5.7dB */ 0x21400085,
+ /* Index40 -6 dB */ 0x20000080,
+ /* Index41 -6.3dB */ 0x1f00007c,
+ /* Index42 -6.6dB */ 0x1e000078,
+ /* Index43 -6.9dB */ 0x1d000074,
+ /* Index44 -7.2dB */ 0x1c000070,
+ /* Index45 -7.5dB */ 0x1b00006c,
+ /* Index46 -7.8dB */ 0x1a000068,
+ /* Index47 -8.1dB */ 0x19400065,
+ /* Index48 -8.4dB */ 0x18400061,
+ /* Index49 -8.7dB */ 0x1780005e,
+ /* Index50 -9 dB */ 0x16c0005b,
+ /* Index51 -9.3dB */ 0x16000058,
+ /* Index52 -9.6dB */ 0x15400055,
+ /* Index53 -9.9dB */ 0x14800052
+};
+u8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8] = {
+ /* Index0 0 dB */ {0x36, 0x34, 0x2E, 0x26, 0x1C, 0x12, 0x08, 0x04},
+ /* Index1 -0.3dB */ {0x34, 0x32, 0x2C, 0x25, 0x1B, 0x11, 0x08, 0x04},
+ /* Index2 -0.6dB */ {0x32, 0x30, 0x2B, 0x23, 0x1A, 0x11, 0x07, 0x04},
+ /* Index3 -0.9dB */ {0x31, 0x2F, 0x29, 0x22, 0x19, 0x10, 0x07, 0x04},
+ /* Index4 -1.2dB */ {0x2F, 0x2D, 0x28, 0x21, 0x18, 0x10, 0x07, 0x03},
+ /* Index5 -1.5dB */ {0x2D, 0x2C, 0x27, 0x20, 0x18, 0x0F, 0x07, 0x03},
+ /* Index6 -1.8dB */ {0x2C, 0x2A, 0x25, 0x1F, 0x17, 0x0F, 0x06, 0x03},
+ /* Index7 -2.1dB */ {0x2A, 0x29, 0x24, 0x1E, 0x16, 0x0E, 0x06, 0x03},
+ /* Index8 -2.4dB */ {0x29, 0x27, 0x23, 0x1D, 0x15, 0x0E, 0x06, 0x03},
+ /* Index9 -2.7dB */ {0x27, 0x26, 0x22, 0x1C, 0x14, 0x0D, 0x06, 0x03},
+ /* Index10 -3 dB */ {0x26, 0x25, 0x20, 0x1B, 0x14, 0x0D, 0x06, 0x03},
+ /* Index11 -3.3dB */ {0x25, 0x23, 0x1F, 0x1A, 0x13, 0x0C, 0x05, 0x03},
+ /* Index12 -3.6dB */ {0x24, 0x22, 0x1E, 0x19, 0x12, 0x0C, 0x05, 0x03},
+ /* Index13 -3.9dB */ {0x22, 0x21, 0x1D, 0x18, 0x12, 0x0B, 0x05, 0x03},
+ /* Index14 -4.2dB */ {0x21, 0x20, 0x1C, 0x17, 0x11, 0x0B, 0x05, 0x02},
+ /* Index15 -4.5dB */ {0x20, 0x1F, 0x1B, 0x17, 0x11, 0x0B, 0x05, 0x02},
+ /* Index16 -4.8dB */ {0x1F, 0x1E, 0x1A, 0x16, 0x10, 0x0A, 0x05, 0x02},
+ /* Index17 -5.1dB */ {0x1E, 0x1D, 0x1A, 0x15, 0x10, 0x0A, 0x04, 0x02},
+ /* Index18 -5.4dB */ {0x1D, 0x1C, 0x19, 0x14, 0x0F, 0x0A, 0x04, 0x02},
+ /* Index19 -5.7dB */ {0x1C, 0x1B, 0x18, 0x14, 0x0E, 0x09, 0x04, 0x02},
+ /* Index20 -6.0dB */ {0x1B, 0x1A, 0x17, 0x13, 0x0E, 0x09, 0x04, 0x02}, /* 20 This is CCK base index */
+ /* Index21 -6.3dB */ {0x1A, 0x19, 0x16, 0x12, 0x0E, 0x09, 0x04, 0x02},
+ /* Index22 -6.6dB */ {0x19, 0x18, 0x15, 0x12, 0x0D, 0x08, 0x04, 0x02},
+ /* Index23 -6.9dB */ {0x18, 0x17, 0x15, 0x11, 0x0D, 0x08, 0x04, 0x02},
+ /* Index24 -7.2dB */ {0x18, 0x17, 0x14, 0x11, 0x0C, 0x08, 0x03, 0x02},
+ /* Index25 -7.5dB */ {0x17, 0x16, 0x13, 0x10, 0x0C, 0x08, 0x03, 0x02},
+ /* Index26 -7.8dB */ {0x16, 0x15, 0x13, 0x0F, 0x0B, 0x07, 0x03, 0x02},
+ /* Index27 -8.1dB */ {0x15, 0x14, 0x12, 0x0F, 0x0B, 0x07, 0x03, 0x02},
+ /* Index28 -8.4dB */ {0x14, 0x14, 0x11, 0x0E, 0x0B, 0x07, 0x03, 0x02},
+ /* Index29 -8.7dB */ {0x14, 0x13, 0x11, 0x0E, 0x0A, 0x07, 0x03, 0x01},
+ /* Index30 -9.0dB */ {0x13, 0x12, 0x10, 0x0D, 0x0A, 0x06, 0x03, 0x01}, /* 30 This is hp CCK base index */
+ /* Index31 -9.3dB */ {0x12, 0x12, 0x0F, 0x0D, 0x0A, 0x06, 0x03, 0x01},
+ /* Index32 -9.6dB */ {0x12, 0x11, 0x0F, 0x0D, 0x09, 0x06, 0x03, 0x01},
+ /* Index33 -9.9dB */ {0x11, 0x11, 0x0F, 0x0C, 0x09, 0x06, 0x03, 0x01},
+ /* Index34 -10.2dB */ {0x11, 0x11, 0x0E, 0x0C, 0x09, 0x06, 0x02, 0x01},
+ /* Index35 -10.5dB */ {0x10, 0x0F, 0x0E, 0x0B, 0x08, 0x05, 0x02, 0x01},
+ /* Index36 -10.8dB */ {0x10, 0x0F, 0x0D, 0x0B, 0x08, 0x05, 0x02, 0x01},
+ /* Index37 -11.1dB */ {0x0F, 0x0E, 0x0D, 0x0A, 0x08, 0x05, 0x02, 0x01},
+ /* Index38 -11.4dB */ {0x0E, 0x0E, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01},
+ /* Index39 -11.7dB */ {0x0E, 0x0D, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01},
+ /* Index40 -12 dB */ {0x0E, 0x0D, 0x0C, 0x0A, 0x07, 0x05, 0x02, 0x01},
+ /* Index41 -12.3dB */ {0x0D, 0x0D, 0x0B, 0x09, 0x07, 0x04, 0x02, 0x01},
+ /* Index42 -12.6dB */ {0x0D, 0x0C, 0x0B, 0x09, 0x07, 0x04, 0x02, 0x01},
+ /* Index43 -12.9dB */ {0x0C, 0x0C, 0x0A, 0x09, 0x06, 0x04, 0x02, 0x01},
+ /* Index44 -13.2dB */ {0x0C, 0x0B, 0x0A, 0x08, 0x06, 0x04, 0x02, 0x01},
+ /* Index45 -13.5dB */ {0x0B, 0x0B, 0x0A, 0x08, 0x06, 0x04, 0x02, 0x01},
+ /* Index46 -13.8dB */ {0x0B, 0x0B, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},
+ /* Index47 -14.1dB */ {0x0B, 0x0A, 0x09, 0x07, 0x06, 0x04, 0x02, 0x01},
+ /* Index48 -14.4dB */ {0x0A, 0x0A, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},
+ /* Index49 -14.7dB */ {0x0A, 0x0A, 0x08, 0x07, 0x05, 0x03, 0x01, 0x01},
+ /* Index50 -15 dB */ {0x0A, 0x09, 0x08, 0x07, 0x05, 0x03, 0x01, 0x01},
+ /* Index51 -15.3dB */ {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
+ /* Index52 -15.6dB */ {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
+ /* Index53 -15.9dB */ {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}
+};
+u8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8] = {
+ /* Index0 0 dB */ {0x36, 0x34, 0x2E, 0x26, 0x00, 0x00, 0x00, 0x00},
+ /* Index1 -0.3dB */ {0x34, 0x32, 0x2C, 0x25, 0x00, 0x00, 0x00, 0x00},
+ /* Index2 -0.6dB */ {0x32, 0x30, 0x2B, 0x23, 0x00, 0x00, 0x00, 0x00},
+ /* Index3 -0.9dB */ {0x31, 0x2F, 0x29, 0x22, 0x00, 0x00, 0x00, 0x00},
+ /* Index4 -1.2dB */ {0x2F, 0x2D, 0x28, 0x21, 0x00, 0x00, 0x00, 0x00},
+ /* Index5 -1.5dB */ {0x2D, 0x2C, 0x27, 0x20, 0x00, 0x00, 0x00, 0x00},
+ /* Index6 -1.8dB */ {0x2C, 0x2A, 0x25, 0x1F, 0x00, 0x00, 0x00, 0x00},
+ /* Index7 -2.1dB */ {0x2A, 0x29, 0x24, 0x1E, 0x00, 0x00, 0x00, 0x00},
+ /* Index8 -2.4dB */ {0x29, 0x27, 0x23, 0x1D, 0x00, 0x00, 0x00, 0x00},
+ /* Index9 -2.7dB */ {0x27, 0x26, 0x22, 0x1C, 0x00, 0x00, 0x00, 0x00},
+ /* Index10 -3 dB */ {0x26, 0x25, 0x20, 0x1B, 0x00, 0x00, 0x00, 0x00},
+ /* Index11 -3.3dB */ {0x25, 0x23, 0x1F, 0x1A, 0x00, 0x00, 0x00, 0x00},
+ /* Index12 -3.6dB */ {0x24, 0x22, 0x1E, 0x19, 0x00, 0x00, 0x00, 0x00},
+ /* Index13 -3.9dB */ {0x22, 0x21, 0x1D, 0x18, 0x00, 0x00, 0x00, 0x00},
+ /* Index14 -4.2dB */ {0x21, 0x20, 0x1C, 0x17, 0x00, 0x00, 0x00, 0x00},
+ /* Index15 -4.5dB */ {0x20, 0x1F, 0x1B, 0x17, 0x00, 0x00, 0x00, 0x00},
+ /* Index16 -4.8dB */ {0x1F, 0x1E, 0x1A, 0x16, 0x00, 0x00, 0x00, 0x00},
+ /* Index17 -5.1dB */ {0x1E, 0x1D, 0x1A, 0x15, 0x00, 0x00, 0x00, 0x00},
+ /* Index18 -5.4dB */ {0x1D, 0x1C, 0x19, 0x14, 0x00, 0x00, 0x00, 0x00},
+ /* Index19 -5.7dB */ {0x1C, 0x1B, 0x18, 0x14, 0x00, 0x00, 0x00, 0x00},
+ /* Index20 -6 dB */ {0x1B, 0x1A, 0x17, 0x13, 0x00, 0x00, 0x00, 0x00},
+ /* Index21 -6.3dB */ {0x1A, 0x19, 0x16, 0x12, 0x00, 0x00, 0x00, 0x00},
+ /* Index22 -6.6dB */ {0x19, 0x18, 0x15, 0x12, 0x00, 0x00, 0x00, 0x00},
+ /* Index23 -6.9dB */ {0x18, 0x17, 0x15, 0x11, 0x00, 0x00, 0x00, 0x00},
+ /* Index24 -7.2dB */ {0x18, 0x17, 0x14, 0x11, 0x00, 0x00, 0x00, 0x00},
+ /* Index25 -7.5dB */ {0x17, 0x16, 0x13, 0x10, 0x00, 0x00, 0x00, 0x00},
+ /* Index26 -7.8dB */ {0x16, 0x15, 0x13, 0x0F, 0x00, 0x00, 0x00, 0x00},
+ /* Index27 -8.1dB */ {0x15, 0x14, 0x12, 0x0F, 0x00, 0x00, 0x00, 0x00},
+ /* Index28 -8.4dB */ {0x14, 0x14, 0x11, 0x0E, 0x00, 0x00, 0x00, 0x00},
+ /* Index29 -8.7dB */ {0x14, 0x13, 0x11, 0x0E, 0x00, 0x00, 0x00, 0x00},
+ /* Index30 -9 dB */ {0x13, 0x12, 0x10, 0x0D, 0x00, 0x00, 0x00, 0x00},
+ /* Index31 -9.3dB */ {0x12, 0x12, 0x0F, 0x0D, 0x00, 0x00, 0x00, 0x00},
+ /* Index32 -9.6dB */ {0x12, 0x11, 0x0F, 0x0D, 0x00, 0x00, 0x00, 0x00},
+ /* Index33 -9.9dB */ {0x11, 0x11, 0x0F, 0x0C, 0x00, 0x00, 0x00, 0x00},
+ /* Index34 -10.2dB */ {0x11, 0x11, 0x0E, 0x0C, 0x00, 0x00, 0x00, 0x00},
+ /* Index35 -10.5dB */ {0x10, 0x0F, 0x0E, 0x0B, 0x00, 0x00, 0x00, 0x00},
+ /* Index36 -10.8dB */ {0x10, 0x0F, 0x0D, 0x0B, 0x00, 0x00, 0x00, 0x00},
+ /* Index37 -11.1dB */ {0x0F, 0x0E, 0x0D, 0x0A, 0x00, 0x00, 0x00, 0x00},
+ /* Index38 -11.4dB */ {0x0E, 0x0E, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00},
+ /* Index39 -11.7dB */ {0x0E, 0x0D, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00},
+ /* Index40 -12 dB */ {0x0E, 0x0D, 0x0C, 0x0A, 0x00, 0x00, 0x00, 0x00},
+ /* Index41 -12.3dB */ {0x0D, 0x0D, 0x0B, 0x09, 0x00, 0x00, 0x00, 0x00},
+ /* Index42 -12.6dB */ {0x0D, 0x0C, 0x0B, 0x09, 0x00, 0x00, 0x00, 0x00},
+ /* Index43 -12.9dB */ {0x0C, 0x0C, 0x0A, 0x09, 0x00, 0x00, 0x00, 0x00},
+ /* Index44 -13.2dB */ {0x0C, 0x0B, 0x0A, 0x08, 0x00, 0x00, 0x00, 0x00},
+ /* Index45 -13.5dB */ {0x0B, 0x0B, 0x0A, 0x08, 0x00, 0x00, 0x00, 0x00},
+ /* Index46 -13.8dB */ {0x0B, 0x0B, 0x09, 0x08, 0x00, 0x00, 0x00, 0x00},
+ /* Index47 -14.1dB */ {0x0B, 0x0A, 0x09, 0x07, 0x00, 0x00, 0x00, 0x00},
+ /* Index48 -14.4dB */ {0x0A, 0x0A, 0x09, 0x07, 0x00, 0x00, 0x00, 0x00},
+ /* Index49 -14.7dB */ {0x0A, 0x0A, 0x08, 0x07, 0x00, 0x00, 0x00, 0x00},
+ /* Index50 -15 dB */ {0x0A, 0x09, 0x08, 0x07, 0x00, 0x00, 0x00, 0x00},
+ /* Index51 -15.3dB */ {0x09, 0x09, 0x08, 0x06, 0x00, 0x00, 0x00, 0x00},
+ /* Index52 -15.6dB */ {0x09, 0x09, 0x08, 0x06, 0x00, 0x00, 0x00, 0x00},
+ /* Index53 -15.9dB */ {0x09, 0x08, 0x07, 0x06, 0x00, 0x00, 0x00, 0x00}
+};
+#endif
+
+#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
+u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = {
+ 0x081, /* 0, -12.0dB */
+ 0x088, /* 1, -11.5dB */
+ 0x090, /* 2, -11.0dB */
+ 0x099, /* 3, -10.5dB */
+ 0x0A2, /* 4, -10.0dB */
+ 0x0AC, /* 5, -9.5dB */
+ 0x0B6, /* 6, -9.0dB */
+ 0x0C0, /* 7, -8.5dB */
+ 0x0CC, /* 8, -8.0dB */
+ 0x0D8, /* 9, -7.5dB */
+ 0x0E5, /* 10, -7.0dB */
+ 0x0F2, /* 11, -6.5dB */
+ 0x101, /* 12, -6.0dB */
+ 0x110, /* 13, -5.5dB */
+ 0x120, /* 14, -5.0dB */
+ 0x131, /* 15, -4.5dB */
+ 0x143, /* 16, -4.0dB */
+ 0x156, /* 17, -3.5dB */
+ 0x16A, /* 18, -3.0dB */
+ 0x180, /* 19, -2.5dB */
+ 0x197, /* 20, -2.0dB */
+ 0x1AF, /* 21, -1.5dB */
+ 0x1C8, /* 22, -1.0dB */
+ 0x1E3, /* 23, -0.5dB */
+ 0x200, /* 24, +0 dB */
+ 0x21E, /* 25, +0.5dB */
+ 0x23E, /* 26, +1.0dB */
+ 0x261, /* 27, +1.5dB */
+ 0x285, /* 28, +2.0dB */
+ 0x2AB, /* 29, +2.5dB */
+ 0x2D3, /* 30, +3.0dB */
+ 0x2FE, /* 31, +3.5dB */
+ 0x32B, /* 32, +4.0dB */
+ 0x35C, /* 33, +4.5dB */
+ 0x38E, /* 34, +5.0dB */
+ 0x3C4, /* 35, +5.5dB */
+ 0x3FE /* 36, +6.0dB */
+};
+#elif(ODM_IC_11AC_SERIES_SUPPORT)
+u32 ofdm_swing_table_8812[OFDM_TABLE_SIZE_8812] = {
+ 0x3FE, /* 0, (6dB) */
+ 0x3C4, /* 1, (5.5dB) */
+ 0x38E, /* 2, (5dB) */
+ 0x35C, /* 3, (4.5dB) */
+ 0x32B, /* 4, (4dB) */
+ 0x2FE, /* 5, (3.5dB) */
+ 0x2D3, /* 6, (3dB) */
+ 0x2AB, /* 7, (2.5dB) */
+ 0x285, /* 8, (2dB) */
+ 0x261, /* 9, (1.5dB */
+ 0x23E, /* 10, (1dB) */
+ 0x21E, /* 11, (0.5dB) */
+ 0x200, /* 12, (0dB) 8814 int PA 2G default */
+ 0x1E3, /* 13, (-0.5dB) */
+ 0x1C8, /* 14, (-1dB) */
+ 0x1AF, /* 15, (-1.5dB) */
+ 0x197, /* 16, (-2dB) */
+ 0x180, /* 17, (-2.5dB) */
+ 0x16A, /* 18, (-3dB) 8812 / 8814 int PA 5G / 8814 ext PA 2G5G default */
+ 0x156, /* 19, (-3.5dB) */
+ 0x143, /* 20, (-4dB) 8812 HP default */
+ 0x131, /* 21, (-4.5dB) */
+ 0x120, /* 22, (-5dB) */
+ 0x110, /* 23, (-5.5dB) */
+ 0x101, /* 24, (-6dB) */
+ 0x0F2, /* 25, (-6.5dB) */
+ 0x0E5, /* 26, (-7dB) */
+ 0x0D8, /* 27, (-7.5dB) */
+ 0x0CC, /* 28, (-8dB) */
+ 0x0C0, /* 29, (-8.5dB) */
+ 0x0B6, /* 30, (-9dB) */
+ 0x0AC, /* 31, (-9.5dB) */
+ 0x0A2, /* 32, (-10dB) */
+ 0x099, /* 33, (-10.5dB) */
+ 0x090, /* 34, (-11dB) */
+ 0x088, /* 35, (-11.5dB) */
+ 0x081, /* 36, (-12dB) */
+ 0x079, /* 37, (-12.5dB) */
+ 0x072, /* 38, (-13dB) */
+ 0x06c, /* 39, (-13.5dB) */
+ 0x066, /* 40, (-14dB) */
+ 0x060, /* 41, (-14.5dB) */
+ 0x05B /* 42, (-15dB) */
+};
+#endif
+
+u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = {
+ 0x0CD,
+ 0x0D9,
+ 0x0E6,
+ 0x0F3,
+ 0x102,
+ 0x111,
+ 0x121,
+ 0x132,
+ 0x144,
+ 0x158,
+ 0x16C,
+ 0x182,
+ 0x198,
+ 0x1B1,
+ 0x1CA,
+ 0x1E5,
+ 0x202,
+ 0x221,
+ 0x241,
+ 0x263,
+ 0x287,
+ 0x2AE,
+ 0x2D6,
+ 0x301,
+ 0x32F,
+ 0x35F,
+ 0x392,
+ 0x3C9,
+ 0x402,
+ 0x43F,
+ 0x47F,
+ 0x4C3,
+ 0x50C,
+ 0x558,
+ 0x5A9,
+ 0x5FF,
+ 0x65A,
+ 0x6BA,
+ 0x720,
+ 0x78C,
+ 0x7FF,
+};
+/* JJ ADD 20161014 */
+u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = {
+ 0x0CD,
+ 0x0D9,
+ 0x0E6,
+ 0x0F3,
+ 0x102,
+ 0x111,
+ 0x121,
+ 0x132,
+ 0x144,
+ 0x158,
+ 0x16C,
+ 0x182,
+ 0x198,
+ 0x1B1,
+ 0x1CA,
+ 0x1E5,
+ 0x202,
+ 0x221,
+ 0x241,
+ 0x263,
+ 0x287,
+ 0x2AE,
+ 0x2D6,
+ 0x301,
+ 0x32F,
+ 0x35F,
+ 0x392,
+ 0x3C9,
+ 0x402,
+ 0x43F,
+ 0x47F,
+ 0x4C3,
+ 0x50C,
+ 0x558,
+ 0x5A9,
+ 0x5FF,
+ 0x65A,
+ 0x6BA,
+ 0x720,
+ 0x78C,
+ 0x7FF,
+};
+
+
+/* #endif */
+/* 3============================================================
+ * 3 Tx Power Tracking
+ * 3============================================================ */
+
+void
+odm_txpowertracking_init(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+ if (!(dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_IC_11N_SERIES)))
+ return;
+#endif
+
+ odm_txpowertracking_thermal_meter_init(dm);
+}
+
+
+u8
+get_swing_index(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ u8 i = 0, bb_swing_mask = 0;
+ u32 bb_swing = 0;
+ u32 swing_table_size = 0;
+ u32 *swing_table = 0;
+ struct rtl8192cd_priv *priv = dm->priv;
+
+#if (RTL8197F_SUPPORT == 1)
+ if (GET_CHIP_VER(priv) == VERSION_8197F) {
+ bb_swing = phy_query_bb_reg(priv, REG_OFDM_0_XA_TX_IQ_IMBALANCE, MASKOFDM_D);
+ swing_table = ofdm_swing_table_new;
+ swing_table_size = OFDM_TABLE_SIZE_92D;
+ bb_swing_mask = 22;
+ }
+#endif
+
+#if (RTL8822B_SUPPORT == 1)
+ if (GET_CHIP_VER(priv) == VERSION_8822B) {
+ bb_swing = phy_query_bb_reg(priv, REG_A_TX_SCALE_JAGUAR, 0xFFE00000);
+ swing_table = tx_scaling_table_jaguar;
+ swing_table_size = TXSCALE_TABLE_SIZE;
+ bb_swing_mask = 0;
+ }
+#endif
+
+ for (i = 0; i < swing_table_size - 1; i++) {
+ u32 table_value = swing_table[i] >> bb_swing_mask;
+
+ if (bb_swing == table_value)
+ break;
+ }
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "bb_swing=0x%x bbswing_index=%d\n", bb_swing, i);
+
+
+ return i;
+}
+
+
+void
+odm_txpowertracking_thermal_meter_init(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
+ struct rtl8192cd_priv *priv = dm->priv;
+ u8 p;
+ u8 default_swing_index;
+#if (RTL8197F_SUPPORT == 1 || RTL8822B_SUPPORT == 1)
+ if ((GET_CHIP_VER(priv) == VERSION_8197F) || (GET_CHIP_VER(priv) == VERSION_8822B))
+ default_swing_index = get_swing_index(dm);
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+ void *adapter = dm->adapter;
+ PMGNT_INFO mgnt_info = &adapter->MgntInfo;
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+
+ mgnt_info->is_txpowertracking = true;
+ hal_data->tx_powercount = 0;
+ hal_data->is_txpowertracking_init = false;
+
+ if (*(dm->mp_mode) == false)
+ hal_data->txpowertrack_control = true;
+ PHYDM_DBG(dm, COMP_POWER_TRACKING, "mgnt_info->is_txpowertracking = %d\n", mgnt_info->is_txpowertracking);
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+#ifdef CONFIG_RTL8188E
+ {
+ dm->rf_calibrate_info.is_txpowertracking = true;
+ dm->rf_calibrate_info.tx_powercount = 0;
+ dm->rf_calibrate_info.is_txpowertracking_init = false;
+
+ if (*(dm->mp_mode) == false)
+ dm->rf_calibrate_info.txpowertrack_control = true;
+
+ MSG_8192C("dm txpowertrack_control = %d\n", dm->rf_calibrate_info.txpowertrack_control);
+ }
+#else
+ {
+ void *adapter = dm->adapter;
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+ struct dm_priv *pdmpriv = &hal_data->dmpriv;
+
+ pdmpriv->is_txpowertracking = true;
+ pdmpriv->tx_powercount = 0;
+ pdmpriv->is_txpowertracking_init = false;
+
+ if (*(dm->mp_mode) == false) /* for mp driver, turn off txpwrtracking as default */
+ pdmpriv->txpowertrack_control = true;
+
+ MSG_8192C("pdmpriv->txpowertrack_control = %d\n", pdmpriv->txpowertrack_control);
+
+ }
+#endif/* endif (CONFIG_RTL8188E==1) */
+#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+
+#ifdef RTL8188E_SUPPORT
+ {
+ dm->rf_calibrate_info.is_txpowertracking = true;
+ dm->rf_calibrate_info.tx_powercount = 0;
+ dm->rf_calibrate_info.is_txpowertracking_init = false;
+ dm->rf_calibrate_info.txpowertrack_control = true;
+ dm->rf_calibrate_info.tm_trigger = 0;
+ }
+#endif
+#endif
+
+ dm->rf_calibrate_info.txpowertrack_control = true;
+ dm->rf_calibrate_info.delta_power_index = 0;
+ dm->rf_calibrate_info.delta_power_index_last = 0;
+ dm->rf_calibrate_info.power_index_offset = 0;
+ dm->rf_calibrate_info.thermal_value = 0;
+ cali_info->default_ofdm_index = 28;
+
+#if (RTL8197F_SUPPORT == 1)
+ if (GET_CHIP_VER(priv) == VERSION_8197F) {
+ cali_info->default_ofdm_index = (default_swing_index >= (OFDM_TABLE_SIZE_92D - 1)) ? 30 : default_swing_index;
+ cali_info->default_cck_index = 28;
+ }
+#endif
+
+#if (RTL8822B_SUPPORT == 1)
+ if (GET_CHIP_VER(priv) == VERSION_8822B) {
+ cali_info->default_ofdm_index = (default_swing_index >= (TXSCALE_TABLE_SIZE - 1)) ? 24 : default_swing_index;
+ cali_info->default_cck_index = 20;
+ }
+#endif
+
+
+#if RTL8188E_SUPPORT
+ cali_info->default_cck_index = 20; /* -6 dB */
+#elif RTL8192E_SUPPORT
+ cali_info->default_cck_index = 8; /* -12 dB */
+#endif
+ cali_info->bb_swing_idx_ofdm_base = cali_info->default_ofdm_index;
+ cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;
+ dm->rf_calibrate_info.CCK_index = cali_info->default_cck_index;
+
+ for (p = 0; p < MAX_RF_PATH; p++) {
+ dm->rf_calibrate_info.OFDM_index[p] = cali_info->default_ofdm_index;
+ cali_info->bb_swing_idx_ofdm[p] = cali_info->default_ofdm_index;
+ cali_info->kfree_offset[p] = 0; /* for 8814 kfree*/
+ }
+ cali_info->bb_swing_idx_cck = cali_info->default_cck_index;
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "cali_info->default_ofdm_index=%d cali_info->default_cck_index=%d\n", cali_info->default_ofdm_index, cali_info->default_cck_index);
+
+ cali_info->tm_trigger = 0;
+}
+
+
+void
+odm_txpowertracking_check(
+ void *dm_void
+)
+{
+ /* */
+ /* For AP/ADSL use struct rtl8192cd_priv* */
+ /* For CE/NIC use struct void* */
+ /* */
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct _hal_rf_ *rf = &(dm->rf_table);
+
+
+ if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK))
+ return;
+
+ /* */
+ /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
+ /* at the same time. In the stage2/3, we need to prive universal interface and merge all */
+ /* HW dynamic mechanism. */
+ /* */
+ switch (dm->support_platform) {
+ case ODM_WIN:
+ odm_txpowertracking_check_mp(dm);
+ break;
+
+ case ODM_CE:
+ odm_txpowertracking_check_ce(dm);
+ break;
+
+ case ODM_AP:
+ odm_txpowertracking_check_ap(dm);
+ break;
+ }
+
+}
+
+void
+odm_txpowertracking_check_ce(
+ void *dm_void
+)
+{
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ void *adapter = dm->adapter;
+ struct _hal_rf_ *rf = &(dm->rf_table);
+
+#if (RTL8188E_SUPPORT == 1)
+
+ /* if(!mgnt_info->is_txpowertracking || (!pdmpriv->txpowertrack_control && pdmpriv->is_ap_kdone)) */
+
+ if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK))
+ return;
+
+ if (!dm->rf_calibrate_info.tm_trigger) { /* at least delay 1 sec */
+ /* hal_data->TxPowerCheckCnt++; */ /* cosa add for debug */
+ odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60);
+ /* DBG_8192C("Trigger 92C Thermal Meter!!\n"); */
+
+ dm->rf_calibrate_info.tm_trigger = 1;
+ return;
+
+ } else {
+ /* DBG_8192C("Schedule TxPowerTracking direct call!!\n"); */
+ odm_txpowertracking_callback_thermal_meter_8188e(adapter);
+ dm->rf_calibrate_info.tm_trigger = 0;
+ }
+#endif
+
+#endif
+}
+
+void
+odm_txpowertracking_check_mp(
+ void *dm_void
+)
+{
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ void *adapter = dm->adapter;
+
+ if (odm_check_power_status(adapter) == false)
+ return;
+
+ if (!adapter->is_slave_of_dmsp || adapter->dual_mac_smart_concurrent == false)
+ odm_txpowertracking_thermal_meter_check(adapter);
+#endif
+
+}
+
+
+void
+odm_txpowertracking_check_ap(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+ struct rtl8192cd_priv *priv = dm->priv;
+
+#if ((RTL8188E_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8197F_SUPPORT == 1))
+ if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8881A | ODM_RTL8814A | ODM_RTL8197F | ODM_RTL8822B | ODM_RTL8821C))
+ odm_txpowertracking_callback_thermal_meter(dm);
+ else
+#endif
+ {
+ }
+#endif
+
+}
diff --git a/hal/phydm/halrf/halrf_powertracking_ap.h b/hal/phydm/halrf/halrf_powertracking_ap.h
new file mode 100644
index 0000000..703b876
--- /dev/null
+++ b/hal/phydm/halrf/halrf_powertracking_ap.h
@@ -0,0 +1,345 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#ifndef __PHYDMPOWERTRACKING_H__
+#define __PHYDMPOWERTRACKING_H__
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+ #ifdef RTK_AC_SUPPORT
+ #define ODM_IC_11AC_SERIES_SUPPORT 1
+ #else
+ #define ODM_IC_11AC_SERIES_SUPPORT 0
+ #endif
+#else
+ #define ODM_IC_11AC_SERIES_SUPPORT 1
+#endif
+
+#define DPK_DELTA_MAPPING_NUM 13
+#define index_mapping_HP_NUM 15
+#define DELTA_SWINGIDX_SIZE 30
+#define DELTA_SWINTSSI_SIZE 61
+#define BAND_NUM 3
+#define MAX_RF_PATH 4
+#define TXSCALE_TABLE_SIZE 37
+#define CCK_TABLE_SIZE_8723D 41
+/* JJ ADD 20161014 */
+#define CCK_TABLE_SIZE_8710B 41
+
+#define IQK_MAC_REG_NUM 4
+#define IQK_ADDA_REG_NUM 16
+#define IQK_BB_REG_NUM_MAX 10
+
+#define IQK_BB_REG_NUM 9
+
+#define AVG_THERMAL_NUM 8
+#define iqk_matrix_reg_num 8
+/* #define IQK_MATRIX_SETTINGS_NUM 1+24+21 */
+#define IQK_MATRIX_SETTINGS_NUM (14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */
+
+#if !defined(_OUTSRC_COEXIST)
+ #define OFDM_TABLE_SIZE_92D 43
+ #define OFDM_TABLE_SIZE 37
+ #define CCK_TABLE_SIZE 33
+ #define CCK_TABLE_SIZE_88F 21
+
+
+
+ /* #define OFDM_TABLE_SIZE_92E 54 */
+ /* #define CCK_TABLE_SIZE_92E 54 */
+ extern u32 ofdm_swing_table[OFDM_TABLE_SIZE_92D];
+ extern u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8];
+ extern u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8];
+
+
+ extern u32 ofdm_swing_table_new[OFDM_TABLE_SIZE_92D];
+ extern u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8];
+ extern u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8];
+ extern u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];
+ extern u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];
+ extern u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];
+
+#endif
+
+#define ODM_OFDM_TABLE_SIZE 37
+#define ODM_CCK_TABLE_SIZE 33
+/* <20140613, YuChen> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. */
+extern u8 delta_swing_table_idx_2ga_p_default[DELTA_SWINGIDX_SIZE];
+extern u8 delta_swing_table_idx_2ga_n_default[DELTA_SWINGIDX_SIZE];
+
+static u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9};
+static u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11};
+
+/* extern u32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E];
+ * extern u8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8];
+ * extern u8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8]; */
+
+#ifdef CONFIG_WLAN_HAL_8192EE
+ #define OFDM_TABLE_SIZE_92E 54
+ #define CCK_TABLE_SIZE_92E 54
+ extern u32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E];
+ extern u8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8];
+ extern u8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8];
+#endif
+
+#define OFDM_TABLE_SIZE_8812 43
+#define AVG_THERMAL_NUM_8812 4
+
+#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
+ extern u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];
+ #elif(ODM_IC_11AC_SERIES_SUPPORT)
+ extern unsigned int ofdm_swing_table_8812[OFDM_TABLE_SIZE_8812];
+#endif
+
+extern u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];
+/* JJ ADD 20161014 */
+extern u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B];
+
+#define dm_check_txpowertracking odm_txpowertracking_check
+
+struct iqk_matrix_regs_setting {
+ boolean is_iqk_done;
+ s32 value[1][iqk_matrix_reg_num];
+};
+
+struct dm_rf_calibration_struct {
+ /* for tx power tracking */
+
+ u32 rega24; /* for TempCCK */
+ s32 rege94;
+ s32 rege9c;
+ s32 regeb4;
+ s32 regebc;
+
+ /* u8 is_txpowertracking; */
+ u8 tx_powercount;
+ boolean is_txpowertracking_init;
+ boolean is_txpowertracking;
+ u8 txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */
+ u8 tm_trigger;
+ u8 internal_pa_5g[2]; /* pathA / pathB */
+
+ u8 thermal_meter[2]; /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
+ u8 thermal_value;
+ u8 thermal_value_lck;
+ u8 thermal_value_iqk;
+ s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */
+ u8 thermal_value_dpk;
+ u8 thermal_value_avg[AVG_THERMAL_NUM];
+ u8 thermal_value_avg_index;
+ u8 thermal_value_rx_gain;
+ u8 thermal_value_crystal;
+ u8 thermal_value_dpk_store;
+ u8 thermal_value_dpk_track;
+ boolean txpowertracking_in_progress;
+ boolean is_dpk_enable;
+
+ boolean is_reloadtxpowerindex;
+ u8 is_rf_pi_enable;
+ u32 txpowertracking_callback_cnt; /* cosa add for debug */
+
+ u8 is_cck_in_ch14;
+ u8 CCK_index;
+ u8 OFDM_index[MAX_RF_PATH];
+ s8 power_index_offset;
+ s8 delta_power_index;
+ s8 delta_power_index_last;
+ boolean is_tx_power_changed;
+
+ struct iqk_matrix_regs_setting iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];
+ u8 delta_lck;
+ u8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];
+ u8 delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];
+ u8 delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];
+ u8 delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];
+ u8 delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];
+ u8 delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];
+ u8 delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];
+ u8 delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];
+ u8 delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];
+ u8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
+ u8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
+ u8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
+ u8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];
+
+ u8 bb_swing_idx_ofdm[MAX_RF_PATH];
+ u8 bb_swing_idx_ofdm_current;
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+ u8 bb_swing_idx_ofdm_base[MAX_RF_PATH];
+#else
+ u8 bb_swing_idx_ofdm_base;
+#endif
+ boolean bb_swing_flag_ofdm;
+ u8 bb_swing_idx_cck;
+ u8 bb_swing_idx_cck_current;
+ u8 bb_swing_idx_cck_base;
+ u8 default_ofdm_index;
+ u8 default_cck_index;
+ boolean bb_swing_flag_cck;
+
+ s8 absolute_ofdm_swing_idx[MAX_RF_PATH];
+ s8 remnant_ofdm_swing_idx[MAX_RF_PATH];
+ s8 absolute_cck_swing_idx[MAX_RF_PATH];
+ s8 remnant_cck_swing_idx;
+ s8 modify_tx_agc_value; /*Remnat compensate value at tx_agc */
+ boolean modify_tx_agc_flag_path_a;
+ boolean modify_tx_agc_flag_path_b;
+ boolean modify_tx_agc_flag_path_c;
+ boolean modify_tx_agc_flag_path_d;
+ boolean modify_tx_agc_flag_path_a_cck;
+
+ s8 kfree_offset[MAX_RF_PATH];
+
+ /* -------------------------------------------------------------------- */
+
+ /* for IQK */
+ u32 regc04;
+ u32 reg874;
+ u32 regc08;
+ u32 regb68;
+ u32 regb6c;
+ u32 reg870;
+ u32 reg860;
+ u32 reg864;
+
+ boolean is_iqk_initialized;
+ boolean is_lck_in_progress;
+ boolean is_antenna_detected;
+ boolean is_need_iqk;
+ boolean is_iqk_in_progress;
+ boolean is_iqk_pa_off;
+ u8 delta_iqk;
+ u32 ADDA_backup[IQK_ADDA_REG_NUM];
+ u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
+ u32 IQK_BB_backup_recover[9];
+ u32 IQK_BB_backup[IQK_BB_REG_NUM];
+ u32 tx_iqc_8723b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
+ u32 rx_iqc_8723b[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
+ u32 tx_iqc_8703b[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
+ u32 rx_iqc_8703b[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
+
+ u64 iqk_start_time;
+ u64 iqk_total_progressing_time;
+ u64 iqk_progressing_time;
+ u64 lck_progressing_time;
+ u32 lok_result;
+ u8 iqk_step;
+ u8 kcount;
+ u8 retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */
+ boolean is_mp_mode;
+
+ /* for APK */
+ u32 ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */
+ u8 is_ap_kdone;
+ u8 is_apk_thermal_meter_ignore;
+ u8 is_dp_done;
+ u8 is_dp_path_aok;
+ u8 is_dp_path_bok;
+
+ /*Add by Yuchen for Kfree Phydm*/
+ u8 reg_rf_kfree_enable; /*for registry*/
+ u8 rf_kfree_enable; /*for efuse enable check*/
+ u32 tx_lok[2];
+};
+
+void
+odm_txpowertracking_check_ap(
+ void *dm_void
+);
+
+void
+odm_txpowertracking_check(
+ void *dm_void
+);
+
+
+void
+odm_txpowertracking_thermal_meter_init(
+ void *dm_void
+);
+
+void
+odm_txpowertracking_init(
+ void *dm_void
+);
+
+void
+odm_txpowertracking_check_mp(
+ void *dm_void
+);
+
+
+void
+odm_txpowertracking_check_ce(
+ void *dm_void
+);
+
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
+
+void
+odm_txpowertracking_callback_thermal_meter92c(
+ void *adapter
+);
+
+void
+odm_txpowertracking_callback_rx_gain_thermal_meter92d(
+ void *adapter
+);
+
+void
+odm_txpowertracking_callback_thermal_meter92d(
+ void *adapter
+);
+
+void
+odm_txpowertracking_direct_call92c(
+ void *adapter
+);
+
+void
+odm_txpowertracking_thermal_meter_check(
+ void *adapter
+);
+
+#endif
+
+
+
+#endif
diff --git a/hal/phydm/halrf/halrf_powertracking_ce.c b/hal/phydm/halrf/halrf_powertracking_ce.c
new file mode 100644
index 0000000..6b8402e
--- /dev/null
+++ b/hal/phydm/halrf/halrf_powertracking_ce.c
@@ -0,0 +1,761 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger
+ *
+ *****************************************************************************/
+
+/*============================================================ */
+/* include files */
+/*============================================================ */
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+/* ************************************************************
+ * Global var
+ * ************************************************************ */
+
+u32 ofdm_swing_table[OFDM_TABLE_SIZE] = {
+ 0x7f8001fe, /* 0, +6.0dB */
+ 0x788001e2, /* 1, +5.5dB */
+ 0x71c001c7, /* 2, +5.0dB*/
+ 0x6b8001ae, /* 3, +4.5dB*/
+ 0x65400195, /* 4, +4.0dB*/
+ 0x5fc0017f, /* 5, +3.5dB*/
+ 0x5a400169, /* 6, +3.0dB*/
+ 0x55400155, /* 7, +2.5dB*/
+ 0x50800142, /* 8, +2.0dB*/
+ 0x4c000130, /* 9, +1.5dB*/
+ 0x47c0011f, /* 10, +1.0dB*/
+ 0x43c0010f, /* 11, +0.5dB*/
+ 0x40000100, /* 12, +0dB*/
+ 0x3c8000f2, /* 13, -0.5dB*/
+ 0x390000e4, /* 14, -1.0dB*/
+ 0x35c000d7, /* 15, -1.5dB*/
+ 0x32c000cb, /* 16, -2.0dB*/
+ 0x300000c0, /* 17, -2.5dB*/
+ 0x2d4000b5, /* 18, -3.0dB*/
+ 0x2ac000ab, /* 19, -3.5dB*/
+ 0x288000a2, /* 20, -4.0dB*/
+ 0x26000098, /* 21, -4.5dB*/
+ 0x24000090, /* 22, -5.0dB*/
+ 0x22000088, /* 23, -5.5dB*/
+ 0x20000080, /* 24, -6.0dB*/
+ 0x1e400079, /* 25, -6.5dB*/
+ 0x1c800072, /* 26, -7.0dB*/
+ 0x1b00006c, /* 27. -7.5dB*/
+ 0x19800066, /* 28, -8.0dB*/
+ 0x18000060, /* 29, -8.5dB*/
+ 0x16c0005b, /* 30, -9.0dB*/
+ 0x15800056, /* 31, -9.5dB*/
+ 0x14400051, /* 32, -10.0dB*/
+ 0x1300004c, /* 33, -10.5dB*/
+ 0x12000048, /* 34, -11.0dB*/
+ 0x11000044, /* 35, -11.5dB*/
+ 0x10000040, /* 36, -12.0dB*/
+};
+
+u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = {
+ {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */
+ {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */
+ {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB*/
+ {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB*/
+ {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */
+ {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB*/
+ {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB*/
+ {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB*/
+ {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */
+ {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB*/
+ {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */
+ {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB*/
+ {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB <== default */
+ {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB*/
+ {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */
+ {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB*/
+ {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
+ {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB*/
+ {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */
+ {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB*/
+ {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB*/
+ {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB*/
+ {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB*/
+ {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB*/
+ {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB*/
+ {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB*/
+ {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB*/
+ {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB*/
+ {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB*/
+ {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB*/
+ {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB*/
+ {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB*/
+ {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB*/
+};
+
+
+u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8] = {
+ {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */
+ {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */
+ {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */
+ {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB*/
+ {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */
+ {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB*/
+ {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */
+ {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */
+ {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */
+ {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB*/
+ {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */
+ {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB*/
+ {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB <== default*/
+ {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */
+ {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */
+ {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB*/
+ {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
+ {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB*/
+ {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */
+ {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB*/
+ {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB*/
+ {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB*/
+ {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB*/
+ {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB*/
+ {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB*/
+ {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB*/
+ {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB*/
+ {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB*/
+ {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB*/
+ {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB*/
+ {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB*/
+ {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB*/
+ {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB*/
+};
+
+
+u32 ofdm_swing_table_new[OFDM_TABLE_SIZE] = {
+ 0x0b40002d, /* 0, -15.0dB */
+ 0x0c000030, /* 1, -14.5dB*/
+ 0x0cc00033, /* 2, -14.0dB*/
+ 0x0d800036, /* 3, -13.5dB*/
+ 0x0e400039, /* 4, -13.0dB */
+ 0x0f00003c, /* 5, -12.5dB*/
+ 0x10000040, /* 6, -12.0dB*/
+ 0x11000044, /* 7, -11.5dB*/
+ 0x12000048, /* 8, -11.0dB*/
+ 0x1300004c, /* 9, -10.5dB*/
+ 0x14400051, /* 10, -10.0dB*/
+ 0x15800056, /* 11, -9.5dB*/
+ 0x16c0005b, /* 12, -9.0dB*/
+ 0x18000060, /* 13, -8.5dB*/
+ 0x19800066, /* 14, -8.0dB*/
+ 0x1b00006c, /* 15, -7.5dB*/
+ 0x1c800072, /* 16, -7.0dB*/
+ 0x1e400079, /* 17, -6.5dB*/
+ 0x20000080, /* 18, -6.0dB*/
+ 0x22000088, /* 19, -5.5dB*/
+ 0x24000090, /* 20, -5.0dB*/
+ 0x26000098, /* 21, -4.5dB*/
+ 0x288000a2, /* 22, -4.0dB*/
+ 0x2ac000ab, /* 23, -3.5dB*/
+ 0x2d4000b5, /* 24, -3.0dB*/
+ 0x300000c0, /* 25, -2.5dB*/
+ 0x32c000cb, /* 26, -2.0dB*/
+ 0x35c000d7, /* 27, -1.5dB*/
+ 0x390000e4, /* 28, -1.0dB*/
+ 0x3c8000f2, /* 29, -0.5dB*/
+ 0x40000100, /* 30, +0dB*/
+ 0x43c0010f, /* 31, +0.5dB*/
+ 0x47c0011f, /* 32, +1.0dB*/
+ 0x4c000130, /* 33, +1.5dB*/
+ 0x50800142, /* 34, +2.0dB*/
+ 0x55400155, /* 35, +2.5dB*/
+ 0x5a400169, /* 36, +3.0dB*/
+ 0x5fc0017f, /* 37, +3.5dB*/
+ 0x65400195, /* 38, +4.0dB*/
+ 0x6b8001ae, /* 39, +4.5dB*/
+ 0x71c001c7, /* 40, +5.0dB*/
+ 0x788001e2, /* 41, +5.5dB*/
+ 0x7f8001fe /* 42, +6.0dB*/
+};
+
+
+u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
+ {0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
+ {0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
+ {0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
+ {0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
+ {0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
+ {0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
+ {0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
+ {0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
+ {0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
+ {0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
+ {0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
+ {0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
+ {0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
+ {0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
+ {0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
+ {0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
+ {0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
+ {0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
+ {0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
+ {0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
+ {0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
+};
+
+
+u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = {
+ {0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
+ {0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
+ {0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
+ {0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
+ {0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
+ {0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
+ {0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
+ {0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
+ {0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
+ {0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
+ {0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
+ {0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
+ {0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
+ {0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
+ {0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
+ {0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
+ {0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
+ {0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
+ {0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
+ {0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
+ {0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
+};
+
+
+u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
+ {0x44, 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
+ {0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
+ {0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
+ {0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
+ {0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
+ {0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
+ {0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
+ {0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
+ {0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
+ {0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
+ {0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
+ {0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
+ {0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
+ {0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
+ {0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
+ {0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
+ {0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
+ {0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
+ {0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
+ {0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
+ {0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
+};
+
+
+u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = {
+ {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, /* 0, -16.0dB*/
+ {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 1, -15.5dB*/
+ {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 2, -15.0dB*/
+ {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 3, -14.5dB*/
+ {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 4, -14.0dB*/
+ {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 5, -13.5dB*/
+ {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 6, -13.0dB*/
+ {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 7, -12.5dB*/
+ {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 8, -12.0dB*/
+ {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 9, -11.5dB*/
+ {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 10, -11.0dB*/
+ {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 11, -10.5dB*/
+ {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 12, -10.0dB*/
+ {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 13, -9.5dB*/
+ {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 14, -9.0dB */
+ {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 15, -8.5dB*/
+ {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
+ {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 17, -7.5dB*/
+ {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 18, -7.0dB */
+ {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 19, -6.5dB*/
+ {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /*20, -6.0dB */
+ {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 21, -5.5dB*/
+ {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 22, -5.0dB */
+ {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 23, -4.5dB*/
+ {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 24, -4.0dB */
+ {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 25, -3.5dB*/
+ {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 26, -3.0dB*/
+ {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 27, -2.5dB*/
+ {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 28, -2.0dB */
+ {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 29, -1.5dB*/
+ {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 30, -1.0dB*/
+ {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 31, -0.5dB*/
+ {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} /* 32, +0dB*/
+};
+
+
+u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = {
+ {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, /* 0, -16.0dB*/
+ {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 1, -15.5dB*/
+ {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 2, -15.0dB*/
+ {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 3, -14.5dB*/
+ {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 4, -14.0dB*/
+ {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /*5, -13.5dB*/
+ {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 6, -13.0dB*/
+ {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 7, -12.5dB*/
+ {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 8, -12.0dB*/
+ {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 9, -11.5dB*/
+ {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 10, -11.0dB*/
+ {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /*11, -10.5dB*/
+ {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 12, -10.0dB*/
+ {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 13, -9.5dB*/
+ {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /*14, -9.0dB */
+ {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 15, -8.5dB*/
+ {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
+ {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 17, -7.5dB*/
+ {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 18, -7.0dB */
+ {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 19, -6.5dB */
+ {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 20, -6.0dB */
+ {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 21, -5.5dB*/
+ {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 22, -5.0dB */
+ {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /*23, -4.5dB*/
+ {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 24, -4.0dB */
+ {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 25, -3.5dB */
+ {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 26, -3.0dB */
+ {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /*27, -2.5dB*/
+ {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 28, -2.0dB */
+ {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /*29, -1.5dB*/
+ {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 30, -1.0dB */
+ {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 31, -0.5dB */
+ {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} /* 32, +0dB */
+};
+u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = {
+ 0x0CD, /*0 , -20dB*/
+ 0x0D9,
+ 0x0E6,
+ 0x0F3,
+ 0x102,
+ 0x111,
+ 0x121,
+ 0x132,
+ 0x144,
+ 0x158,
+ 0x16C,
+ 0x182,
+ 0x198,
+ 0x1B1,
+ 0x1CA,
+ 0x1E5,
+ 0x202,
+ 0x221,
+ 0x241,
+ 0x263,
+ 0x287,
+ 0x2AE,
+ 0x2D6,
+ 0x301,
+ 0x32F,
+ 0x35F,
+ 0x392,
+ 0x3C9,
+ 0x402,
+ 0x43F,
+ 0x47F,
+ 0x4C3,
+ 0x50C,
+ 0x558,
+ 0x5A9,
+ 0x5FF,
+ 0x65A,
+ 0x6BA,
+ 0x720,
+ 0x78C,
+ 0x7FF,
+};
+/* JJ ADD 20161014 */
+u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = {
+ 0x0CD, /*0 , -20dB*/
+ 0x0D9,
+ 0x0E6,
+ 0x0F3,
+ 0x102,
+ 0x111,
+ 0x121,
+ 0x132,
+ 0x144,
+ 0x158,
+ 0x16C,
+ 0x182,
+ 0x198,
+ 0x1B1,
+ 0x1CA,
+ 0x1E5,
+ 0x202,
+ 0x221,
+ 0x241,
+ 0x263,
+ 0x287,
+ 0x2AE,
+ 0x2D6,
+ 0x301,
+ 0x32F,
+ 0x35F,
+ 0x392,
+ 0x3C9,
+ 0x402,
+ 0x43F,
+ 0x47F,
+ 0x4C3,
+ 0x50C,
+ 0x558,
+ 0x5A9,
+ 0x5FF,
+ 0x65A,
+ 0x6BA,
+ 0x720,
+ 0x78C,
+ 0x7FF,
+};
+
+
+u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = {
+ 0x081, /* 0, -12.0dB*/
+ 0x088, /* 1, -11.5dB*/
+ 0x090, /* 2, -11.0dB*/
+ 0x099, /* 3, -10.5dB*/
+ 0x0A2, /* 4, -10.0dB*/
+ 0x0AC, /* 5, -9.5dB*/
+ 0x0B6, /* 6, -9.0dB*/
+ 0x0C0, /*7, -8.5dB*/
+ 0x0CC, /* 8, -8.0dB*/
+ 0x0D8, /* 9, -7.5dB*/
+ 0x0E5, /* 10, -7.0dB*/
+ 0x0F2, /* 11, -6.5dB*/
+ 0x101, /* 12, -6.0dB*/
+ 0x110, /* 13, -5.5dB*/
+ 0x120, /* 14, -5.0dB*/
+ 0x131, /* 15, -4.5dB*/
+ 0x143, /* 16, -4.0dB*/
+ 0x156, /* 17, -3.5dB*/
+ 0x16A, /* 18, -3.0dB*/
+ 0x180, /* 19, -2.5dB*/
+ 0x197, /* 20, -2.0dB*/
+ 0x1AF, /* 21, -1.5dB*/
+ 0x1C8, /* 22, -1.0dB*/
+ 0x1E3, /* 23, -0.5dB*/
+ 0x200, /* 24, +0 dB*/
+ 0x21E, /* 25, +0.5dB*/
+ 0x23E, /* 26, +1.0dB*/
+ 0x261, /* 27, +1.5dB*/
+ 0x285,/* 28, +2.0dB*/
+ 0x2AB, /* 29, +2.5dB*/
+ 0x2D3, /*30, +3.0dB*/
+ 0x2FE, /* 31, +3.5dB*/
+ 0x32B, /* 32, +4.0dB*/
+ 0x35C, /* 33, +4.5dB*/
+ 0x38E, /* 34, +5.0dB*/
+ 0x3C4, /* 35, +5.5dB*/
+ 0x3FE /* 36, +6.0dB */
+};
+
+void
+odm_txpowertracking_init(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+ if (!(dm->support_ic_type & (ODM_RTL8814A | ODM_IC_11N_SERIES | ODM_RTL8822B)))
+ return;
+#endif
+
+ odm_txpowertracking_thermal_meter_init(dm);
+}
+
+u8
+get_swing_index(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
+ void *adapter = dm->adapter;
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+#endif
+ u8 i = 0;
+ u32 bb_swing;
+ u32 swing_table_size;
+ u32 *swing_table;
+
+ if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B
+ || dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8710B
+ ) {
+ bb_swing = odm_get_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 0xFFC00000);
+
+ swing_table = ofdm_swing_table_new;
+ swing_table_size = OFDM_TABLE_SIZE;
+ } else {
+#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
+ if (dm->support_ic_type == ODM_RTL8812 || dm->support_ic_type == ODM_RTL8821) {
+ bb_swing = phy_get_tx_bb_swing_8812a(adapter, hal_data->current_band_type, RF_PATH_A);
+ swing_table = tx_scaling_table_jaguar;
+ swing_table_size = TXSCALE_TABLE_SIZE;
+ } else
+#endif
+ {
+ bb_swing = 0;
+ swing_table = ofdm_swing_table;
+ swing_table_size = OFDM_TABLE_SIZE;
+ }
+ }
+
+ for (i = 0; i < swing_table_size; ++i) {
+ u32 table_value = swing_table[i];
+
+ if (table_value >= 0x100000)
+ table_value >>= 22;
+ if (bb_swing == table_value)
+ break;
+ }
+ return i;
+}
+
+u8
+get_cck_swing_index(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+ u8 i = 0;
+ u32 bb_cck_swing;
+
+ if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B ||
+ dm->support_ic_type == ODM_RTL8192E) {
+ bb_cck_swing = odm_read_1byte(dm, 0xa22);
+
+ for (i = 0; i < CCK_TABLE_SIZE; i++) {
+ if (bb_cck_swing == cck_swing_table_ch1_ch13_new[i][0])
+ break;
+ }
+ } else if (dm->support_ic_type == ODM_RTL8703B) {
+ bb_cck_swing = odm_read_1byte(dm, 0xa22);
+
+ for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
+ if (bb_cck_swing == cck_swing_table_ch1_ch14_88f[i][0])
+ break;
+ }
+ }
+
+ return i;
+}
+
+
+void
+odm_txpowertracking_thermal_meter_init(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ u8 default_swing_index = get_swing_index(dm);
+ u8 default_cck_swing_index = get_cck_swing_index(dm);
+ u8 p = 0;
+ struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+ void *adapter = dm->adapter;
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+
+ if (*dm->mp_mode == false)
+ hal_data->txpowertrack_control = true;
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+#ifdef DM_ODM_CE_MAC80211
+ struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
+ struct rtl_efuse *rtlefu = rtl_efuse(rtlpriv);
+#else
+ void *adapter = dm->adapter;
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
+#endif
+
+ cali_info->is_txpowertracking = true;
+ cali_info->tx_powercount = 0;
+ cali_info->is_txpowertracking_init = false;
+
+ if (*dm->mp_mode == false)
+ cali_info->txpowertrack_control = true;
+ else
+ cali_info->txpowertrack_control = false;
+
+ if (*dm->mp_mode == false)
+ cali_info->txpowertrack_control = true;
+
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "dm txpowertrack_control = %d\n", cali_info->txpowertrack_control);
+
+#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+#ifdef RTL8188E_SUPPORT
+ {
+ cali_info->is_txpowertracking = true;
+ cali_info->tx_powercount = 0;
+ cali_info->is_txpowertracking_init = false;
+ cali_info->txpowertrack_control = true;
+ }
+#endif
+#endif
+
+ /* dm->rf_calibrate_info.txpowertrack_control = true; */
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
+ cali_info->thermal_value = rtlefu->eeprom_thermalmeter;
+ cali_info->thermal_value_iqk = rtlefu->eeprom_thermalmeter;
+ cali_info->thermal_value_lck = rtlefu->eeprom_thermalmeter;
+#else
+ cali_info->thermal_value = hal_data->eeprom_thermal_meter;
+ cali_info->thermal_value_iqk = hal_data->eeprom_thermal_meter;
+ cali_info->thermal_value_lck = hal_data->eeprom_thermal_meter;
+#endif
+
+ if (cali_info->default_bb_swing_index_flag != true) {
+ /*The index of "0 dB" in SwingTable.*/
+ if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B ||
+ dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8703B) {
+ cali_info->default_ofdm_index = (default_swing_index >= OFDM_TABLE_SIZE) ? 30 : default_swing_index;
+ cali_info->default_cck_index = (default_cck_swing_index >= CCK_TABLE_SIZE) ? 20 : default_cck_swing_index;
+ } else if (dm->support_ic_type == ODM_RTL8188F) { /*add by Mingzhi.Guo 2015-03-23*/
+ cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/
+ cali_info->default_cck_index = 20; /*CCK:-6dB*/
+ } else if (dm->support_ic_type == ODM_RTL8723D) { /*add by zhaohe 2015-10-27*/
+ cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/
+ cali_info->default_cck_index = 28; /*CCK: -6dB*/
+ } else if (dm->support_ic_type == ODM_RTL8710B) { /* JJ ADD 20161014 */
+ cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/
+ cali_info->default_cck_index = 28; /*CCK: -6dB*/
+ } else {
+ cali_info->default_ofdm_index = (default_swing_index >= TXSCALE_TABLE_SIZE) ? 24 : default_swing_index;
+ cali_info->default_cck_index = 24;
+ }
+ cali_info->default_bb_swing_index_flag = true;
+ }
+
+ cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;
+ cali_info->CCK_index = cali_info->default_cck_index;
+
+ for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) {
+ cali_info->bb_swing_idx_ofdm_base[p] = cali_info->default_ofdm_index;
+ cali_info->OFDM_index[p] = cali_info->default_ofdm_index;
+ cali_info->delta_power_index[p] = 0;
+ cali_info->delta_power_index_last[p] = 0;
+ cali_info->power_index_offset[p] = 0;
+ }
+ cali_info->modify_tx_agc_value_ofdm = 0;
+ cali_info->modify_tx_agc_value_cck = 0;
+ cali_info->tm_trigger = 0;
+}
+
+
+void
+odm_txpowertracking_check(
+ void *dm_void
+)
+{
+ /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate
+ at the same time. In the stage2/3, we need to prive universal interface and merge all
+ HW dynamic mechanism. */
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ switch (dm->support_platform) {
+ case ODM_WIN:
+ odm_txpowertracking_check_mp(dm);
+ break;
+
+ case ODM_CE:
+ odm_txpowertracking_check_ce(dm);
+ break;
+
+ case ODM_AP:
+ odm_txpowertracking_check_ap(dm);
+ break;
+
+ default:
+ break;
+ }
+
+}
+
+void
+odm_txpowertracking_check_ce(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct _hal_rf_ *rf = &dm->rf_table;
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ void *adapter = dm->adapter;
+
+
+ if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK))
+ return;
+
+ if (!dm->rf_calibrate_info.tm_trigger) {
+ if (IS_HARDWARE_TYPE_8188E(adapter) || IS_HARDWARE_TYPE_8188F(adapter) || IS_HARDWARE_TYPE_8192E(adapter)
+ || IS_HARDWARE_TYPE_8723B(adapter) || IS_HARDWARE_TYPE_JAGUAR(adapter) || IS_HARDWARE_TYPE_8814A(adapter)
+ || IS_HARDWARE_TYPE_8703B(adapter) || IS_HARDWARE_TYPE_8723D(adapter) || IS_HARDWARE_TYPE_8822B(adapter)
+ || IS_HARDWARE_TYPE_8821C(adapter) || (dm->support_ic_type == ODM_RTL8710B)
+ )/* JJ ADD 20161014 */
+ odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER_NEW, (BIT(17) | BIT(16)), 0x03);
+ else
+ odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER_OLD, RFREGOFFSETMASK, 0x60);
+
+
+
+ dm->rf_calibrate_info.tm_trigger = 1;
+ return;
+ } else {
+ odm_txpowertracking_callback_thermal_meter(dm);
+ dm->rf_calibrate_info.tm_trigger = 0;
+ }
+
+#endif
+}
+
+void
+odm_txpowertracking_check_mp(
+ void *dm_void
+)
+{
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ void *adapter = dm->adapter;
+
+ if (odm_check_power_status(adapter) == false) {
+ RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("check_pow_status, return false\n"));
+ return;
+ }
+
+ odm_txpowertracking_thermal_meter_check(adapter);
+#endif
+
+}
+
+
+void
+odm_txpowertracking_check_ap(
+ void *dm_void
+)
+{
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct rtl8192cd_priv *priv = dm->priv;
+
+ return;
+
+#endif
+}
diff --git a/hal/phydm/halrf/halrf_powertracking_ce.h b/hal/phydm/halrf/halrf_powertracking_ce.h
new file mode 100644
index 0000000..1fef265
--- /dev/null
+++ b/hal/phydm/halrf/halrf_powertracking_ce.h
@@ -0,0 +1,348 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger
+ *
+ *****************************************************************************/
+
+#ifndef __PHYDMPOWERTRACKING_H__
+#define __PHYDMPOWERTRACKING_H__
+
+#define DPK_DELTA_MAPPING_NUM 13
+#define index_mapping_HP_NUM 15
+#define OFDM_TABLE_SIZE 43
+#define CCK_TABLE_SIZE 33
+#define CCK_TABLE_SIZE_88F 21
+#define TXSCALE_TABLE_SIZE 37
+#define CCK_TABLE_SIZE_8723D 41
+/* JJ ADD 20161014 */
+#define CCK_TABLE_SIZE_8710B 41
+
+#define TXPWR_TRACK_TABLE_SIZE 30
+#define DELTA_SWINGIDX_SIZE 30
+#define DELTA_SWINTSSI_SIZE 61
+#define BAND_NUM 4
+
+#define AVG_THERMAL_NUM 8
+#define IQK_MAC_REG_NUM 4
+#define IQK_ADDA_REG_NUM 16
+#define IQK_BB_REG_NUM_MAX 10
+
+#define IQK_BB_REG_NUM 9
+
+
+
+#define iqk_matrix_reg_num 8
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
+#else
+#define IQK_MATRIX_SETTINGS_NUM (14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */
+#endif
+
+extern u32 ofdm_swing_table[OFDM_TABLE_SIZE];
+extern u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8];
+extern u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8];
+
+extern u32 ofdm_swing_table_new[OFDM_TABLE_SIZE];
+extern u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8];
+extern u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8];
+extern u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];
+extern u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];
+extern u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];
+extern u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];
+/* JJ ADD 20161014 */
+extern u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B];
+
+extern u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];
+
+/* <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. */
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
+#else
+static u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9};
+static u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11};
+#endif
+
+#define dm_check_txpowertracking odm_txpowertracking_check
+
+struct iqk_matrix_regs_setting {
+ boolean is_iqk_done;
+ s32 value[3][iqk_matrix_reg_num];
+ boolean is_bw_iqk_result_saved[3];
+};
+
+struct dm_rf_calibration_struct {
+ /* for tx power tracking */
+
+ u32 rega24; /* for TempCCK */
+ s32 rege94;
+ s32 rege9c;
+ s32 regeb4;
+ s32 regebc;
+
+ u8 tx_powercount;
+ boolean is_txpowertracking_init;
+ boolean is_txpowertracking;
+ u8 txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */
+ u8 tm_trigger;
+ u8 internal_pa_5g[2]; /* pathA / pathB */
+
+ u8 thermal_meter[2]; /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
+ u8 thermal_value;
+ u8 thermal_value_lck;
+ u8 thermal_value_iqk;
+ s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */
+ u8 thermal_value_dpk;
+ u8 thermal_value_avg[AVG_THERMAL_NUM];
+ u8 thermal_value_avg_index;
+ u8 thermal_value_rx_gain;
+ u8 thermal_value_crystal;
+ u8 thermal_value_dpk_store;
+ u8 thermal_value_dpk_track;
+ boolean txpowertracking_in_progress;
+
+ boolean is_reloadtxpowerindex;
+ u8 is_rf_pi_enable;
+ u32 txpowertracking_callback_cnt; /* cosa add for debug */
+
+
+ /* ------------------------- Tx power Tracking ------------------------- */
+ u8 is_cck_in_ch14;
+ u8 CCK_index;
+ u8 OFDM_index[MAX_RF_PATH];
+ s8 power_index_offset[MAX_RF_PATH];
+ s8 delta_power_index[MAX_RF_PATH];
+ s8 delta_power_index_last[MAX_RF_PATH];
+ boolean is_tx_power_changed;
+ s8 xtal_offset;
+ s8 xtal_offset_last;
+
+ struct iqk_matrix_regs_setting iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];
+ u8 delta_lck;
+ s8 bb_swing_diff_2g, bb_swing_diff_5g; /* Unit: dB */
+ u8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];
+ u8 delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];
+ u8 delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];
+ u8 delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];
+ u8 delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];
+ u8 delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];
+ u8 delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];
+ u8 delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];
+ u8 delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];
+ u8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
+ u8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
+ u8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
+ s8 delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];
+ s8 delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];
+
+ u8 bb_swing_idx_ofdm[MAX_RF_PATH];
+ u8 bb_swing_idx_ofdm_current;
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+ u8 bb_swing_idx_ofdm_base[MAX_RF_PATH];
+#else
+ u8 bb_swing_idx_ofdm_base;
+#endif
+ boolean default_bb_swing_index_flag;
+ boolean bb_swing_flag_ofdm;
+ u8 bb_swing_idx_cck;
+ u8 bb_swing_idx_cck_current;
+ u8 bb_swing_idx_cck_base;
+ u8 default_ofdm_index;
+ u8 default_cck_index;
+ boolean bb_swing_flag_cck;
+
+ s8 absolute_ofdm_swing_idx[MAX_RF_PATH];
+ s8 remnant_ofdm_swing_idx[MAX_RF_PATH];
+ s8 absolute_cck_swing_idx[MAX_RF_PATH];
+ s8 remnant_cck_swing_idx;
+ s8 modify_tx_agc_value; /*Remnat compensate value at tx_agc */
+ boolean modify_tx_agc_flag_path_a;
+ boolean modify_tx_agc_flag_path_b;
+ boolean modify_tx_agc_flag_path_c;
+ boolean modify_tx_agc_flag_path_d;
+ boolean modify_tx_agc_flag_path_a_cck;
+
+ s8 kfree_offset[MAX_RF_PATH];
+
+ /* -------------------------------------------------------------------- */
+
+ /* for IQK */
+ u32 regc04;
+ u32 reg874;
+ u32 regc08;
+ u32 regb68;
+ u32 regb6c;
+ u32 reg870;
+ u32 reg860;
+ u32 reg864;
+
+ boolean is_iqk_initialized;
+ boolean is_lck_in_progress;
+ boolean is_antenna_detected;
+ boolean is_need_iqk;
+ boolean is_iqk_in_progress;
+ boolean is_iqk_pa_off;
+ u8 delta_iqk;
+ u32 ADDA_backup[IQK_ADDA_REG_NUM];
+ u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
+ u32 IQK_BB_backup_recover[9];
+ u32 IQK_BB_backup[IQK_BB_REG_NUM];
+ u32 tx_iqc_8723b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
+ u32 rx_iqc_8723b[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
+ u32 tx_iqc_8703b[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
+ u32 rx_iqc_8703b[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
+ u32 tx_iqc_8723d[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
+ u32 rx_iqc_8723d[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
+ /* JJ ADD 20161014 */
+ u32 tx_iqc_8710b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
+ u32 rx_iqc_8710b[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
+
+ u8 iqk_step;
+ u8 kcount;
+ u8 retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */
+ boolean is_mp_mode;
+
+
+
+ /* IQK time measurement */
+ u64 iqk_start_time;
+ u64 iqk_progressing_time;
+ u64 iqk_total_progressing_time;
+ u64 lck_progressing_time;
+
+ u32 lok_result;
+
+ /* for APK */
+ u32 ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */
+ u8 is_ap_kdone;
+ u8 is_apk_thermal_meter_ignore;
+
+ /* DPK */
+ boolean is_dpk_fail;
+ u8 is_dp_done;
+ u8 is_dp_path_aok;
+ u8 is_dp_path_bok;
+
+ u32 tx_lok[2];
+ u32 dpk_tx_agc;
+ s32 dpk_gain;
+ u32 dpk_thermal[4];
+ s8 modify_tx_agc_value_ofdm;
+ s8 modify_tx_agc_value_cck;
+
+ /*Add by Yuchen for Kfree Phydm*/
+ u8 reg_rf_kfree_enable; /*for registry*/
+ u8 rf_kfree_enable; /*for efuse enable check*/
+
+};
+
+
+void
+odm_txpowertracking_check(
+ void *dm_void
+);
+
+
+void
+odm_txpowertracking_init(
+ void *dm_void
+);
+
+void
+odm_txpowertracking_check_ap(
+ void *dm_void
+);
+
+void
+odm_txpowertracking_thermal_meter_init(
+ void *dm_void
+);
+
+void
+odm_txpowertracking_init(
+ void *dm_void
+);
+
+void
+odm_txpowertracking_check_mp(
+ void *dm_void
+);
+
+
+void
+odm_txpowertracking_check_ce(
+ void *dm_void
+);
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
+
+void
+odm_txpowertracking_callback_thermal_meter92c(
+ void *adapter
+);
+
+void
+odm_txpowertracking_callback_rx_gain_thermal_meter92d(
+ void *adapter
+);
+
+void
+odm_txpowertracking_callback_thermal_meter92d(
+ void *adapter
+);
+
+void
+odm_txpowertracking_direct_call92c(
+ void *adapter
+);
+
+void
+odm_txpowertracking_thermal_meter_check(
+ void *adapter
+);
+
+#endif
+
+#endif
diff --git a/hal/phydm/halrf/halrf_powertracking_win.c b/hal/phydm/halrf/halrf_powertracking_win.c
new file mode 100644
index 0000000..5705259
--- /dev/null
+++ b/hal/phydm/halrf/halrf_powertracking_win.c
@@ -0,0 +1,806 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+/*============================================================ */
+/* include files */
+/*============================================================ */
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+/* ************************************************************
+ * Global var
+ * ************************************************************ */
+
+u32 ofdm_swing_table[OFDM_TABLE_SIZE] = {
+ 0x7f8001fe, /* 0, +6.0dB */
+ 0x788001e2, /* 1, +5.5dB */
+ 0x71c001c7, /* 2, +5.0dB */
+ 0x6b8001ae, /* 3, +4.5dB */
+ 0x65400195, /* 4, +4.0dB */
+ 0x5fc0017f, /* 5, +3.5dB */
+ 0x5a400169, /* 6, +3.0dB */
+ 0x55400155, /* 7, +2.5dB */
+ 0x50800142, /* 8, +2.0dB */
+ 0x4c000130, /* 9, +1.5dB */
+ 0x47c0011f, /* 10, +1.0dB */
+ 0x43c0010f, /* 11, +0.5dB */
+ 0x40000100, /* 12, +0dB */
+ 0x3c8000f2, /* 13, -0.5dB */
+ 0x390000e4, /* 14, -1.0dB */
+ 0x35c000d7, /* 15, -1.5dB */
+ 0x32c000cb, /* 16, -2.0dB */
+ 0x300000c0, /* 17, -2.5dB */
+ 0x2d4000b5, /* 18, -3.0dB */
+ 0x2ac000ab, /* 19, -3.5dB */
+ 0x288000a2, /* 20, -4.0dB */
+ 0x26000098, /* 21, -4.5dB */
+ 0x24000090, /* 22, -5.0dB */
+ 0x22000088, /* 23, -5.5dB */
+ 0x20000080, /* 24, -6.0dB */
+ 0x1e400079, /* 25, -6.5dB */
+ 0x1c800072, /* 26, -7.0dB */
+ 0x1b00006c, /* 27. -7.5dB */
+ 0x19800066, /* 28, -8.0dB */
+ 0x18000060, /* 29, -8.5dB */
+ 0x16c0005b, /* 30, -9.0dB */
+ 0x15800056, /* 31, -9.5dB */
+ 0x14400051, /* 32, -10.0dB */
+ 0x1300004c, /* 33, -10.5dB */
+ 0x12000048, /* 34, -11.0dB */
+ 0x11000044, /* 35, -11.5dB */
+ 0x10000040, /* 36, -12.0dB */
+};
+
+u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = {
+ {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */
+ {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */
+ {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */
+ {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */
+ {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */
+ {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */
+ {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */
+ {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */
+ {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */
+ {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */
+ {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */
+ {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */
+ {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB <== default */
+ {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */
+ {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */
+ {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */
+ {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
+ {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */
+ {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */
+ {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */
+ {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */
+ {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */
+ {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */
+ {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */
+ {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */
+ {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */
+ {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */
+ {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */
+ {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */
+ {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */
+ {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */
+ {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */
+ {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */
+};
+
+
+u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8] = {
+ {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */
+ {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */
+ {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */
+ {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */
+ {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */
+ {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */
+ {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */
+ {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */
+ {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */
+ {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */
+ {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */
+ {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */
+ {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB <== default */
+ {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */
+ {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */
+ {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */
+ {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
+ {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */
+ {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */
+ {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */
+ {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB */
+ {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB */
+ {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB */
+ {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB */
+ {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB */
+ {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB */
+ {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB */
+ {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB */
+ {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB */
+ {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB */
+ {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB */
+ {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB */
+ {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB */
+};
+
+
+u32 ofdm_swing_table_new[OFDM_TABLE_SIZE] = {
+ 0x0b40002d, /* 0, -15.0dB */
+ 0x0c000030, /* 1, -14.5dB */
+ 0x0cc00033, /* 2, -14.0dB */
+ 0x0d800036, /* 3, -13.5dB */
+ 0x0e400039, /* 4, -13.0dB */
+ 0x0f00003c, /* 5, -12.5dB */
+ 0x10000040, /* 6, -12.0dB */
+ 0x11000044, /* 7, -11.5dB */
+ 0x12000048, /* 8, -11.0dB */
+ 0x1300004c, /* 9, -10.5dB */
+ 0x14400051, /* 10, -10.0dB */
+ 0x15800056, /* 11, -9.5dB */
+ 0x16c0005b, /* 12, -9.0dB */
+ 0x18000060, /* 13, -8.5dB */
+ 0x19800066, /* 14, -8.0dB */
+ 0x1b00006c, /* 15, -7.5dB */
+ 0x1c800072, /* 16, -7.0dB */
+ 0x1e400079, /* 17, -6.5dB */
+ 0x20000080, /* 18, -6.0dB */
+ 0x22000088, /* 19, -5.5dB */
+ 0x24000090, /* 20, -5.0dB */
+ 0x26000098, /* 21, -4.5dB */
+ 0x288000a2, /* 22, -4.0dB */
+ 0x2ac000ab, /* 23, -3.5dB */
+ 0x2d4000b5, /* 24, -3.0dB */
+ 0x300000c0, /* 25, -2.5dB */
+ 0x32c000cb, /* 26, -2.0dB */
+ 0x35c000d7, /* 27, -1.5dB */
+ 0x390000e4, /* 28, -1.0dB */
+ 0x3c8000f2, /* 29, -0.5dB */
+ 0x40000100, /* 30, +0dB */
+ 0x43c0010f, /* 31, +0.5dB */
+ 0x47c0011f, /* 32, +1.0dB */
+ 0x4c000130, /* 33, +1.5dB */
+ 0x50800142, /* 34, +2.0dB */
+ 0x55400155, /* 35, +2.5dB */
+ 0x5a400169, /* 36, +3.0dB */
+ 0x5fc0017f, /* 37, +3.5dB */
+ 0x65400195, /* 38, +4.0dB */
+ 0x6b8001ae, /* 39, +4.5dB */
+ 0x71c001c7, /* 40, +5.0dB */
+ 0x788001e2, /* 41, +5.5dB */
+ 0x7f8001fe /* 42, +6.0dB */
+};
+
+
+u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
+ {0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
+ {0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
+ {0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
+ {0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
+ {0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
+ {0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
+ {0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
+ {0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
+ {0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
+ {0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
+ {0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
+ {0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
+ {0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
+ {0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
+ {0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
+ {0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
+ {0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
+ {0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
+ {0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
+ {0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
+ {0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
+};
+
+
+u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = {
+ {0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
+ {0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
+ {0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
+ {0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
+ {0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
+ {0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
+ {0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
+ {0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
+ {0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
+ {0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
+ {0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
+ {0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
+ {0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
+ {0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
+ {0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
+ {0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
+ {0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
+ {0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
+ {0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
+ {0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
+ {0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
+};
+
+
+u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
+ {0x44, 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
+ {0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
+ {0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
+ {0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
+ {0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
+ {0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
+ {0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
+ {0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
+ {0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
+ {0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
+ {0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
+ {0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
+ {0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
+ {0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
+ {0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
+ {0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
+ {0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
+ {0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
+ {0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
+ {0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
+ {0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
+};
+
+
+u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = {
+ {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, /* 0, -16.0dB */
+ {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 1, -15.5dB */
+ {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 2, -15.0dB */
+ {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 3, -14.5dB */
+ {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 4, -14.0dB */
+ {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 5, -13.5dB */
+ {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 6, -13.0dB */
+ {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 7, -12.5dB */
+ {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 8, -12.0dB */
+ {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 9, -11.5dB */
+ {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 10, -11.0dB */
+ {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 11, -10.5dB */
+ {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 12, -10.0dB */
+ {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 13, -9.5dB */
+ {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 14, -9.0dB */
+ {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 15, -8.5dB */
+ {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
+ {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 17, -7.5dB */
+ {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 18, -7.0dB */
+ {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 19, -6.5dB */
+ {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 20, -6.0dB */
+ {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 21, -5.5dB */
+ {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 22, -5.0dB */
+ {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 23, -4.5dB */
+ {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 24, -4.0dB */
+ {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 25, -3.5dB */
+ {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 26, -3.0dB */
+ {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 27, -2.5dB */
+ {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 28, -2.0dB */
+ {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 29, -1.5dB */
+ {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 30, -1.0dB */
+ {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 31, -0.5dB */
+ {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} /* 32, +0dB */
+};
+
+
+u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = {
+ {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, /* 0, -16.0dB */
+ {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 1, -15.5dB */
+ {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 2, -15.0dB */
+ {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 3, -14.5dB */
+ {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 4, -14.0dB */
+ {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 5, -13.5dB */
+ {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 6, -13.0dB */
+ {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 7, -12.5dB */
+ {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 8, -12.0dB */
+ {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 9, -11.5dB */
+ {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 10, -11.0dB */
+ {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 11, -10.5dB */
+ {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 12, -10.0dB */
+ {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 13, -9.5dB */
+ {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 14, -9.0dB */
+ {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 15, -8.5dB */
+ {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
+ {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 17, -7.5dB */
+ {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 18, -7.0dB */
+ {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 19, -6.5dB */
+ {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 20, -6.0dB */
+ {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 21, -5.5dB */
+ {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 22, -5.0dB */
+ {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 23, -4.5dB */
+ {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 24, -4.0dB */
+ {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 25, -3.5dB */
+ {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 26, -3.0dB */
+ {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 27, -2.5dB */
+ {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 28, -2.0dB */
+ {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 29, -1.5dB */
+ {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 30, -1.0dB */
+ {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 31, -0.5dB */
+ {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} /* 32, +0dB */
+};
+u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = {
+ 0x0CD,
+ 0x0D9,
+ 0x0E6,
+ 0x0F3,
+ 0x102,
+ 0x111,
+ 0x121,
+ 0x132,
+ 0x144,
+ 0x158,
+ 0x16C,
+ 0x182,
+ 0x198,
+ 0x1B1,
+ 0x1CA,
+ 0x1E5,
+ 0x202,
+ 0x221,
+ 0x241,
+ 0x263,
+ 0x287,
+ 0x2AE,
+ 0x2D6,
+ 0x301,
+ 0x32F,
+ 0x35F,
+ 0x392,
+ 0x3C9,
+ 0x402,
+ 0x43F,
+ 0x47F,
+ 0x4C3,
+ 0x50C,
+ 0x558,
+ 0x5A9,
+ 0x5FF,
+ 0x65A,
+ 0x6BA,
+ 0x720,
+ 0x78C,
+ 0x7FF,
+};
+/* JJ ADD 20161014 */
+u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = {
+ 0x0CD, /*0 , -20dB*/
+ 0x0D9,
+ 0x0E6,
+ 0x0F3,
+ 0x102,
+ 0x111,
+ 0x121,
+ 0x132,
+ 0x144,
+ 0x158,
+ 0x16C,
+ 0x182,
+ 0x198,
+ 0x1B1,
+ 0x1CA,
+ 0x1E5,
+ 0x202,
+ 0x221,
+ 0x241,
+ 0x263, /*19*/
+ 0x287, /*20*/
+ 0x2AE, /*21*/
+ 0x2D6, /*22*/
+ 0x301, /*23*/
+ 0x32F, /*24*/
+ 0x35F, /*25*/
+ 0x392, /*26*/
+ 0x3C9, /*27*/
+ 0x402, /*28*/
+ 0x43F, /*29*/
+ 0x47F, /*30*/
+ 0x4C3, /*31*/
+ 0x50C, /*32*/
+ 0x558, /*33*/
+ 0x5A9, /*34*/
+ 0x5FF, /*35*/
+ 0x65A, /*36*/
+ 0x6BA,
+ 0x720,
+ 0x78C,
+ 0x7FF,
+};
+
+
+u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = {
+ 0x081, /* 0, -12.0dB */
+ 0x088, /* 1, -11.5dB */
+ 0x090, /* 2, -11.0dB */
+ 0x099, /* 3, -10.5dB */
+ 0x0A2, /* 4, -10.0dB */
+ 0x0AC, /* 5, -9.5dB */
+ 0x0B6, /* 6, -9.0dB */
+ 0x0C0, /* 7, -8.5dB */
+ 0x0CC, /* 8, -8.0dB */
+ 0x0D8, /* 9, -7.5dB */
+ 0x0E5, /* 10, -7.0dB */
+ 0x0F2, /* 11, -6.5dB */
+ 0x101, /* 12, -6.0dB */
+ 0x110, /* 13, -5.5dB */
+ 0x120, /* 14, -5.0dB */
+ 0x131, /* 15, -4.5dB */
+ 0x143, /* 16, -4.0dB */
+ 0x156, /* 17, -3.5dB */
+ 0x16A, /* 18, -3.0dB */
+ 0x180, /* 19, -2.5dB */
+ 0x197, /* 20, -2.0dB */
+ 0x1AF, /* 21, -1.5dB */
+ 0x1C8, /* 22, -1.0dB */
+ 0x1E3, /* 23, -0.5dB */
+ 0x200, /* 24, +0 dB */
+ 0x21E, /* 25, +0.5dB */
+ 0x23E, /* 26, +1.0dB */
+ 0x261, /* 27, +1.5dB */
+ 0x285, /* 28, +2.0dB */
+ 0x2AB, /* 29, +2.5dB */
+ 0x2D3, /* 30, +3.0dB */
+ 0x2FE, /* 31, +3.5dB */
+ 0x32B, /* 32, +4.0dB */
+ 0x35C, /* 33, +4.5dB */
+ 0x38E, /* 34, +5.0dB */
+ 0x3C4, /* 35, +5.5dB */
+ 0x3FE /* 36, +6.0dB */
+};
+
+void
+odm_txpowertracking_init(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+ if (!(dm->support_ic_type & (ODM_RTL8814A | ODM_IC_11N_SERIES | ODM_RTL8822B)))
+ return;
+#endif
+
+ odm_txpowertracking_thermal_meter_init(dm);
+}
+
+u8
+get_swing_index(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ void *adapter = dm->adapter;
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+ u8 i = 0;
+ u32 bb_swing;
+ u32 swing_table_size;
+ u32 *swing_table;
+
+ if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B ||
+ dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8703B || dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8710B) {
+ bb_swing = odm_get_bb_reg(dm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 0xFFC00000);
+
+ swing_table = ofdm_swing_table_new;
+ swing_table_size = OFDM_TABLE_SIZE;
+ } else {
+ bb_swing = PHY_GetTxBBSwing_8812A((PADAPTER)adapter, hal_data->CurrentBandType, RF_PATH_A);
+ swing_table = tx_scaling_table_jaguar;
+ swing_table_size = TXSCALE_TABLE_SIZE;
+ }
+
+ for (i = 0; i < swing_table_size; ++i) {
+ u32 table_value = swing_table[i];
+
+ if (table_value >= 0x100000)
+ table_value >>= 22;
+ if (bb_swing == table_value)
+ break;
+ }
+ return i;
+}
+
+u8
+get_cck_swing_index(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+ u8 i = 0;
+ u32 bb_cck_swing;
+
+ if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B ||
+ dm->support_ic_type == ODM_RTL8192E) {
+ bb_cck_swing = odm_read_1byte(dm, 0xa22);
+
+ for (i = 0; i < CCK_TABLE_SIZE; i++) {
+ if (bb_cck_swing == cck_swing_table_ch1_ch13_new[i][0])
+ break;
+ }
+ } else if (dm->support_ic_type == ODM_RTL8703B) {
+ bb_cck_swing = odm_read_1byte(dm, 0xa22);
+
+ for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
+ if (bb_cck_swing == cck_swing_table_ch1_ch14_88f[i][0])
+ break;
+ }
+ }
+
+ return i;
+}
+
+
+void
+odm_txpowertracking_thermal_meter_init(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ u8 default_swing_index = get_swing_index(dm);
+ u8 default_cck_swing_index = get_cck_swing_index(dm);
+ struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+ void *adapter = dm->adapter;
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+ u8 p = 0;
+
+ if (*(dm->mp_mode) == false)
+ cali_info->txpowertrack_control = true;
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+#ifdef CONFIG_RTL8188E
+ {
+ cali_info->is_txpowertracking = true;
+ cali_info->tx_powercount = 0;
+ cali_info->is_txpowertracking_init = false;
+
+ if (*(dm->mp_mode) == false)
+ cali_info->txpowertrack_control = true;
+
+ MSG_8192C("dm txpowertrack_control = %d\n", cali_info->txpowertrack_control);
+ }
+#else
+ {
+ void *adapter = dm->adapter;
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+ struct dm_priv *pdmpriv = &hal_data->dmpriv;
+
+ pdmpriv->is_txpowertracking = true;
+ pdmpriv->tx_powercount = 0;
+ pdmpriv->is_txpowertracking_init = false;
+
+ if (*(dm->mp_mode) == false)
+ pdmpriv->txpowertrack_control = true;
+
+ MSG_8192C("pdmpriv->txpowertrack_control = %d\n", pdmpriv->txpowertrack_control);
+
+ }
+#endif
+#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+#ifdef RTL8188E_SUPPORT
+ {
+ cali_info->is_txpowertracking = true;
+ cali_info->tx_powercount = 0;
+ cali_info->is_txpowertracking_init = false;
+ cali_info->txpowertrack_control = true;
+ }
+#endif
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+#if (MP_DRIVER == 1)
+ cali_info->txpowertrack_control = false;
+#else
+ cali_info->txpowertrack_control = true;
+#endif
+#else
+ cali_info->txpowertrack_control = true;
+#endif
+
+ cali_info->thermal_value = hal_data->eeprom_thermal_meter;
+ cali_info->thermal_value_iqk = hal_data->eeprom_thermal_meter;
+ cali_info->thermal_value_lck = hal_data->eeprom_thermal_meter;
+
+ if (cali_info->default_bb_swing_index_flag != true) {
+ /*The index of "0 dB" in SwingTable.*/
+ if (dm->support_ic_type == ODM_RTL8188E || dm->support_ic_type == ODM_RTL8723B ||
+ dm->support_ic_type == ODM_RTL8192E || dm->support_ic_type == ODM_RTL8703B) {
+ cali_info->default_ofdm_index = (default_swing_index >= OFDM_TABLE_SIZE) ? 30 : default_swing_index;
+ cali_info->default_cck_index = (default_cck_swing_index >= CCK_TABLE_SIZE) ? 20 : default_cck_swing_index;
+ } else if (dm->support_ic_type == ODM_RTL8188F) { /*add by Mingzhi.Guo 2015-03-23*/
+ cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/
+ cali_info->default_cck_index = 20; /*CCK:-6dB*/
+ } else if (dm->support_ic_type == ODM_RTL8723D) { /*add by zhaohe 2015-10-27*/
+ cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/
+ cali_info->default_cck_index = 28; /*CCK: -6dB*/
+ /* JJ ADD 20161014 */
+ } else if (dm->support_ic_type == ODM_RTL8710B) {
+ cali_info->default_ofdm_index = 28; /*OFDM: -1dB*/
+ cali_info->default_cck_index = 28; /*CCK: -6dB*/
+ } else {
+ cali_info->default_ofdm_index = (default_swing_index >= TXSCALE_TABLE_SIZE) ? 24 : default_swing_index;
+ cali_info->default_cck_index = 24;
+ }
+ cali_info->default_bb_swing_index_flag = true;
+ }
+
+ cali_info->bb_swing_idx_cck_base = cali_info->default_cck_index;
+ cali_info->CCK_index = cali_info->default_cck_index;
+
+ for (p = RF_PATH_A; p < MAX_RF_PATH; ++p) {
+ cali_info->bb_swing_idx_ofdm_base[p] = cali_info->default_ofdm_index;
+ cali_info->OFDM_index[p] = cali_info->default_ofdm_index;
+ cali_info->delta_power_index[p] = 0;
+ cali_info->delta_power_index_last[p] = 0;
+ cali_info->power_index_offset[p] = 0;
+ cali_info->kfree_offset[p] = 0;
+ }
+ cali_info->modify_tx_agc_value_ofdm = 0;
+ cali_info->modify_tx_agc_value_cck = 0;
+ cali_info->tm_trigger = 0;
+}
+
+
+void
+odm_txpowertracking_check(
+ void *dm_void
+)
+{
+
+#if 0
+ /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
+ /* at the same time. In the stage2/3, we need to prive universal interface and merge all */
+ /* HW dynamic mechanism. */
+#endif
+
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ switch (dm->support_platform) {
+ case ODM_WIN:
+ odm_txpowertracking_check_mp(dm);
+ break;
+
+ case ODM_CE:
+ odm_txpowertracking_check_ce(dm);
+ break;
+
+ case ODM_AP:
+ odm_txpowertracking_check_ap(dm);
+ break;
+
+ default:
+ break;
+ }
+
+}
+
+void
+odm_txpowertracking_check_ce(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct _hal_rf_ *rf = &(dm->rf_table);
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ void *adapter = dm->adapter;
+#if ((RTL8188F_SUPPORT == 1))
+ rtl8192c_odm_check_txpowertracking(adapter);
+#endif
+
+#if (RTL8188E_SUPPORT == 1)
+
+ if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK))
+ return;
+
+ if (!cali_info->tm_trigger) {
+ odm_set_rf_reg(dm, RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60);
+ /*DBG_8192C("Trigger 92C Thermal Meter!!\n");*/
+
+ cali_info->tm_trigger = 1;
+ return;
+
+ } else {
+ /*DBG_8192C("Schedule TxPowerTracking direct call!!\n");*/
+ odm_txpowertracking_callback_thermal_meter_8188e(adapter);
+ cali_info->tm_trigger = 0;
+ }
+#endif
+#endif
+}
+
+void
+odm_txpowertracking_check_mp(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+ void *adapter = dm->adapter;
+
+ if (*dm->is_fcs_mode_enable)
+ return;
+
+ if (odm_check_power_status(dm) == false) {
+ RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("check_pow_status return false\n"));
+ return;
+ }
+
+ if (IS_HARDWARE_TYPE_8821B(adapter)) /* TODO: Don't Do PowerTracking*/
+ return;
+
+ odm_txpowertracking_thermal_meter_check(adapter);
+
+
+#endif
+
+}
+
+
+void
+odm_txpowertracking_check_ap(
+ void *dm_void
+)
+{
+ return;
+
+}
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+
+void
+odm_txpowertracking_direct_call(
+ void *adapter
+)
+{
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+ struct dm_struct *dm = &hal_data->DM_OutSrc;
+
+ odm_txpowertracking_callback_thermal_meter(adapter);
+}
+
+void
+odm_txpowertracking_thermal_meter_check(
+ void *adapter
+)
+{
+ static u8 tm_trigger = 0;
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(((PADAPTER)adapter));
+ struct dm_struct *dm = &(pHalData->DM_OutSrc);
+ struct _hal_rf_ *rf = &(dm->rf_table);
+
+ if (!(rf->rf_supportability & HAL_RF_TX_PWR_TRACK)) {
+ RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
+ ("===>odm_txpowertracking_thermal_meter_check(),mgnt_info->is_txpowertracking is false, return!!\n"));
+ return;
+ }
+
+ if (!tm_trigger) {
+ if (IS_HARDWARE_TYPE_8188E(adapter) || IS_HARDWARE_TYPE_JAGUAR(adapter) || IS_HARDWARE_TYPE_8192E(adapter) ||
+ IS_HARDWARE_TYPE_8723B(adapter) || IS_HARDWARE_TYPE_8814A(adapter) || IS_HARDWARE_TYPE_8188F(adapter) || IS_HARDWARE_TYPE_8703B(adapter)
+ || IS_HARDWARE_TYPE_8822B(adapter) || IS_HARDWARE_TYPE_8723D(adapter) || IS_HARDWARE_TYPE_8821C(adapter) || IS_HARDWARE_TYPE_8710B(adapter))/* JJ ADD 20161014 */
+ PHY_SetRFReg((PADAPTER)adapter, RF_PATH_A, RF_T_METER_88E, BIT(17) | BIT(16), 0x03);
+ else
+ PHY_SetRFReg((PADAPTER)adapter, RF_PATH_A, RF_T_METER, RFREGOFFSETMASK, 0x60);
+
+ RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("Trigger Thermal Meter!!\n"));
+
+ tm_trigger = 1;
+ return;
+ } else {
+ RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("Schedule TxPowerTracking direct call!!\n"));
+ odm_txpowertracking_direct_call(adapter);
+ tm_trigger = 0;
+ }
+}
+
+#endif
diff --git a/hal/phydm/halrf/halrf_powertracking_win.h b/hal/phydm/halrf/halrf_powertracking_win.h
new file mode 100644
index 0000000..19b27c0
--- /dev/null
+++ b/hal/phydm/halrf/halrf_powertracking_win.h
@@ -0,0 +1,299 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#ifndef __PHYDMPOWERTRACKING_H__
+#define __PHYDMPOWERTRACKING_H__
+
+#define DPK_DELTA_MAPPING_NUM 13
+#define index_mapping_HP_NUM 15
+#define TXSCALE_TABLE_SIZE 37
+#define OFDM_TABLE_SIZE 43
+#define CCK_TABLE_SIZE 33
+#define CCK_TABLE_SIZE_8723D 41
+#define TXPWR_TRACK_TABLE_SIZE 30
+#define DELTA_SWINGIDX_SIZE 30
+#define DELTA_SWINTSSI_SIZE 61
+#define BAND_NUM 3
+#define MAX_RF_PATH 4
+#define CCK_TABLE_SIZE_88F 21
+/* JJ ADD 20161014 */
+#define CCK_TABLE_SIZE_8710B 41
+
+
+#define dm_check_txpowertracking odm_txpowertracking_check
+
+#define IQK_MATRIX_SETTINGS_NUM (14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */
+#define AVG_THERMAL_NUM 8
+#define iqk_matrix_reg_num 8
+#define IQK_MAC_REG_NUM 4
+#define IQK_ADDA_REG_NUM 16
+
+#define IQK_BB_REG_NUM 9
+
+
+extern u32 ofdm_swing_table[OFDM_TABLE_SIZE];
+extern u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8];
+extern u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8];
+
+extern u32 ofdm_swing_table_new[OFDM_TABLE_SIZE];
+extern u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8];
+extern u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8];
+extern u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16];
+extern u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16];
+extern u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16];
+extern u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D];
+/* JJ ADD 20161014 */
+extern u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B];
+
+extern u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE];
+
+/* <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. */
+static u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9};
+static u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11};
+
+void
+odm_txpowertracking_check(
+ void *dm_void
+);
+
+void
+odm_txpowertracking_check_ap(
+ void *dm_void
+);
+
+void
+odm_txpowertracking_thermal_meter_init(
+ void *dm_void
+);
+
+void
+odm_txpowertracking_init(
+ void *dm_void
+);
+
+void
+odm_txpowertracking_check_mp(
+ void *dm_void
+);
+
+
+void
+odm_txpowertracking_check_ce(
+ void *dm_void
+);
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
+
+
+void
+odm_txpowertracking_thermal_meter_check(
+ void *adapter
+);
+
+#endif
+
+struct iqk_matrix_regs_setting {
+ boolean is_iqk_done;
+ s32 value[3][iqk_matrix_reg_num];
+ boolean is_bw_iqk_result_saved[3];
+};
+
+struct dm_rf_calibration_struct {
+ /* for tx power tracking */
+
+ u32 rega24; /* for TempCCK */
+ s32 rege94;
+ s32 rege9c;
+ s32 regeb4;
+ s32 regebc;
+ /* u8 is_txpowertracking; */
+ u8 tx_powercount;
+ boolean is_txpowertracking_init;
+ boolean is_txpowertracking;
+ u8 txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */
+ u8 tm_trigger;
+ u8 internal_pa_5g[2]; /* pathA / pathB */
+
+ u8 thermal_meter[2]; /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */
+ u8 thermal_value;
+ u8 thermal_value_lck;
+ u8 thermal_value_iqk;
+ u8 thermal_value_dpk;
+ s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */
+ u8 thermal_value_avg[AVG_THERMAL_NUM];
+ u8 thermal_value_avg_index;
+ u8 thermal_value_rx_gain;
+
+
+ boolean is_reloadtxpowerindex;
+ u8 is_rf_pi_enable;
+ u32 txpowertracking_callback_cnt; /* cosa add for debug */
+
+
+ /* ------------------------- Tx power Tracking ------------------------- */
+ u8 is_cck_in_ch14;
+ u8 CCK_index;
+ u8 OFDM_index[MAX_RF_PATH];
+ s8 power_index_offset[MAX_RF_PATH];
+ s8 delta_power_index[MAX_RF_PATH];
+ s8 delta_power_index_last[MAX_RF_PATH];
+ boolean is_tx_power_changed;
+ s8 xtal_offset;
+ s8 xtal_offset_last;
+
+ struct iqk_matrix_regs_setting iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM];
+ u8 delta_lck;
+ s8 bb_swing_diff_2g, bb_swing_diff_5g; /* Unit: dB */
+ u8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE];
+ u8 delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE];
+ u8 delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE];
+ u8 delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE];
+ u8 delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE];
+ u8 delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE];
+ u8 delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE];
+ u8 delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE];
+ u8 delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE];
+ u8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE];
+ u8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE];
+ u8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE];
+ s8 delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE];
+ s8 delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE];
+ u8 delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE];
+
+ u8 bb_swing_idx_ofdm[MAX_RF_PATH];
+ u8 bb_swing_idx_ofdm_current;
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+ u8 bb_swing_idx_ofdm_base[MAX_RF_PATH];
+#else
+ u8 bb_swing_idx_ofdm_base;
+#endif
+ boolean default_bb_swing_index_flag;
+ boolean bb_swing_flag_ofdm;
+ u8 bb_swing_idx_cck;
+ u8 bb_swing_idx_cck_current;
+ u8 bb_swing_idx_cck_base;
+ u8 default_ofdm_index;
+ u8 default_cck_index;
+ boolean bb_swing_flag_cck;
+
+ s8 absolute_ofdm_swing_idx[MAX_RF_PATH];
+ s8 remnant_ofdm_swing_idx[MAX_RF_PATH];
+ s8 absolute_cck_swing_idx[MAX_RF_PATH];
+ s8 remnant_cck_swing_idx;
+ s8 modify_tx_agc_value; /*Remnat compensate value at tx_agc */
+ boolean modify_tx_agc_flag_path_a;
+ boolean modify_tx_agc_flag_path_b;
+ boolean modify_tx_agc_flag_path_c;
+ boolean modify_tx_agc_flag_path_d;
+ boolean modify_tx_agc_flag_path_a_cck;
+
+ s8 kfree_offset[MAX_RF_PATH];
+
+ /* -------------------------------------------------------------------- */
+
+ /* for IQK */
+ u32 regc04;
+ u32 reg874;
+ u32 regc08;
+ u32 regb68;
+ u32 regb6c;
+ u32 reg870;
+ u32 reg860;
+ u32 reg864;
+
+ boolean is_iqk_initialized;
+ boolean is_lck_in_progress;
+ boolean is_antenna_detected;
+ boolean is_need_iqk;
+ boolean is_iqk_in_progress;
+ boolean is_iqk_pa_off;
+ u8 delta_iqk;
+ u32 ADDA_backup[IQK_ADDA_REG_NUM];
+ u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
+ u32 IQK_BB_backup_recover[9];
+ u32 IQK_BB_backup[IQK_BB_REG_NUM];
+ u32 tx_iqc_8723b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
+ u32 rx_iqc_8723b[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
+ u32 tx_iqc_8703b[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
+ u32 rx_iqc_8703b[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
+ u32 tx_iqc_8723d[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
+ u32 rx_iqc_8723d[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
+ /* JJ ADD 20161014 */
+ u32 tx_iqc_8710b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/
+ u32 rx_iqc_8710b[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/
+
+ u64 iqk_start_time;
+ u64 iqk_total_progressing_time;
+ u64 iqk_progressing_time;
+ u64 lck_progressing_time;
+ u32 lok_result;
+ u8 iqk_step;
+ u8 kcount;
+ u8 retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */
+ boolean is_mp_mode;
+
+ /* for APK */
+ u32 ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */
+ u8 is_ap_kdone;
+ u8 is_apk_thermal_meter_ignore;
+
+ /* DPK */
+ boolean is_dpk_fail;
+ u8 is_dp_done;
+ u8 is_dp_path_aok;
+ u8 is_dp_path_bok;
+
+ u32 tx_lok[2];
+ u32 dpk_tx_agc;
+ s32 dpk_gain;
+ u32 dpk_thermal[4];
+
+ s8 modify_tx_agc_value_ofdm;
+ s8 modify_tx_agc_value_cck;
+
+ /*Add by Yuchen for Kfree Phydm*/
+ u8 reg_rf_kfree_enable; /*for registry*/
+ u8 rf_kfree_enable; /*for efuse enable check*/
+};
+
+
+
+
+#endif
diff --git a/hal/phydm/halrf/halrf_psd.c b/hal/phydm/halrf/halrf_psd.c
new file mode 100644
index 0000000..3193ebe
--- /dev/null
+++ b/hal/phydm/halrf/halrf_psd.c
@@ -0,0 +1,321 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+//============================================================
+// include files
+//============================================================
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+
+#if 0
+u32 _sqrt(u64 n)
+{
+ u64 ans = 0, q = 0;
+ s64 i;
+
+ /*for (i = sizeof(n) * 8 - 2; i > -1; i = i - 2) {*/
+ for (i = 8 * 8 - 2; i > -1; i = i - 2) {
+ q = (q << 2) | ((n & (3 << i)) >> i);
+ if (q >= ((ans << 2) | 1))
+ {
+ q = q - ((ans << 2) | 1);
+ ans = (ans << 1) | 1;
+ }
+ else
+ ans = ans << 1;
+ }
+ DbgPrint("ans=0x%x\n", ans);
+
+ return (u32)ans;
+}
+#endif
+
+
+
+u64 _sqrt(u64 x)
+{
+ u64 i = 0;
+ u64 j = x / 2 + 1;
+
+ while (i <= j) {
+ u64 mid = (i + j) / 2;
+
+ u64 sq = mid * mid;
+
+ if (sq == x)
+ return mid;
+ else if (sq < x)
+ i = mid + 1;
+ else
+ j = mid - 1;
+ }
+
+ return j;
+}
+
+
+
+u32
+halrf_get_psd_data(
+ struct dm_struct *dm,
+ u32 point
+ )
+{
+ struct _hal_rf_ *rf = &(dm->rf_table);
+ struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
+ u32 psd_val = 0, psd_reg, psd_report, psd_point, psd_start, i, delay_time;
+
+#if (DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)
+ if (psd->average == 0)
+ delay_time = 100;
+ else
+ delay_time = 0;
+#else
+ if (psd->average == 0)
+ delay_time = 1000;
+ else
+ delay_time = 100;
+#endif
+
+ if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) {
+ psd_reg = 0x910;
+ psd_report = 0xf44;
+ } else {
+ psd_reg = 0x808;
+ psd_report = 0x8b4;
+ }
+
+ if (dm->support_ic_type & ODM_RTL8710B) {
+ psd_point = 0xeffffc00;
+ psd_start = 0x10000000;
+ } else {
+ psd_point = 0xffbffc00;
+ psd_start = 0x00400000;
+ }
+
+ psd_val = odm_get_bb_reg(dm, psd_reg, MASKDWORD);
+
+ psd_val &= psd_point;
+ psd_val |= point;
+
+ odm_set_bb_reg(dm, psd_reg, MASKDWORD, psd_val);
+
+ psd_val |= psd_start;
+
+ odm_set_bb_reg(dm, psd_reg, MASKDWORD, psd_val);
+
+ for (i = 0; i < delay_time; i++)
+ ODM_delay_us(1);
+
+ psd_val = odm_get_bb_reg(dm, psd_report, MASKDWORD);
+
+ if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8710B)) {
+ psd_val &= MASKL3BYTES;
+ psd_val = psd_val / 32;
+ } else
+ psd_val &= MASKLWORD;
+
+ return psd_val;
+}
+
+
+
+void
+halrf_psd(
+ struct dm_struct *dm,
+ u32 point,
+ u32 start_point,
+ u32 stop_point,
+ u32 average
+ )
+{
+ struct _hal_rf_ *rf = &(dm->rf_table);
+ struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
+
+ u32 i = 0, j = 0, k = 0;
+ u32 psd_reg, avg_org, point_temp, average_tmp;
+ u64 data_tatal = 0, data_temp[64] = {0};
+
+ psd->buf_size = 256;
+
+ if (average == 0)
+ average_tmp = 1;
+ else
+ average_tmp = average;
+
+ if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
+ psd_reg = 0x910;
+ else
+ psd_reg = 0x808;
+
+#if 0
+ dbg_print("[PSD]point=%d, start_point=%d, stop_point=%d, average=%d, average_tmp=%d, buf_size=%d\n",
+ point, start_point, stop_point, average, average_tmp, psd->buf_size);
+#endif
+
+ for (i = 0; i < psd->buf_size; i++)
+ psd->psd_data[i] = 0;
+
+ if (dm->support_ic_type & ODM_RTL8710B)
+ avg_org = odm_get_bb_reg(dm, psd_reg, 0x30000);
+ else
+ avg_org = odm_get_bb_reg(dm, psd_reg, 0x3000);
+
+ if (average != 0)
+ {
+ if (dm->support_ic_type & ODM_RTL8710B)
+ odm_set_bb_reg(dm, psd_reg, 0x30000, 0x1);
+ else
+ odm_set_bb_reg(dm, psd_reg, 0x3000, 0x1);
+ }
+
+#if 0
+ if (avg_temp == 0)
+ avg = 1;
+ else if (avg_temp == 1)
+ avg = 8;
+ else if (avg_temp == 2)
+ avg = 16;
+ else if (avg_temp == 3)
+ avg = 32;
+#endif
+
+ i = start_point;
+ while (i < stop_point) {
+ data_tatal = 0;
+
+ if (i >= point)
+ point_temp = i - point;
+ else
+ point_temp = i;
+
+ for (k = 0; k < average_tmp; k++) {
+ data_temp[k] = halrf_get_psd_data(dm, point_temp);
+ data_tatal = data_tatal + (data_temp[k] * data_temp[k]);
+
+#if 0
+ if ((k % 20) == 0)
+ dbg_print("\n ");
+
+ dbg_print("0x%x ", data_temp[k]);
+#endif
+ }
+ /*dbg_print("\n");*/
+
+ data_tatal = ((data_tatal * 100) / average_tmp);
+ psd->psd_data[j] = (u32)_sqrt(data_tatal);
+
+ i++;
+ j++;
+ }
+
+#if 0
+ for (i = 0; i < psd->buf_size; i++) {
+ if ((i % 20) == 0)
+ dbg_print("\n ");
+
+ dbg_print("0x%x ", psd->psd_data[i]);
+ }
+ dbg_print("\n\n");
+#endif
+
+ if (dm->support_ic_type & ODM_RTL8710B)
+ odm_set_bb_reg(dm, psd_reg, 0x30000, avg_org);
+ else
+ odm_set_bb_reg(dm, psd_reg, 0x3000, avg_org);
+}
+
+
+
+enum rt_status
+halrf_psd_init(
+ struct dm_struct *dm
+ )
+{
+ enum rt_status ret_status = RT_STATUS_SUCCESS;
+ struct _hal_rf_ *rf = &(dm->rf_table);
+ struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
+
+ if (psd->psd_progress)
+ ret_status = RT_STATUS_PENDING;
+ else {
+ psd->psd_progress = 1;
+ halrf_psd(dm, psd->point, psd->start_point, psd->stop_point, psd->average);
+ psd->psd_progress = 0;
+ }
+
+ return ret_status;
+}
+
+
+
+enum rt_status
+halrf_psd_query(
+ struct dm_struct *dm,
+ u32 *outbuf,
+ u32 buf_size
+ )
+{
+ enum rt_status ret_status = RT_STATUS_SUCCESS;
+ struct _hal_rf_ *rf = &(dm->rf_table);
+ struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
+
+ if (psd->psd_progress)
+ ret_status = RT_STATUS_PENDING;
+ else
+ PlatformMoveMemory(outbuf, psd->psd_data, 0x400);
+
+ return ret_status;
+}
+
+
+
+enum rt_status
+halrf_psd_init_query(
+ struct dm_struct *dm,
+ u32 *outbuf,
+ u32 point,
+ u32 start_point,
+ u32 stop_point,
+ u32 average,
+ u32 buf_size
+ )
+{
+ enum rt_status ret_status = RT_STATUS_SUCCESS;
+ struct _hal_rf_ *rf = &(dm->rf_table);
+ struct _halrf_psd_data *psd = &(rf->halrf_psd_data);
+
+ psd->point = point;
+ psd->start_point = start_point;
+ psd->stop_point = stop_point;
+ psd->average = average;
+
+ if (psd->psd_progress)
+ ret_status = RT_STATUS_PENDING;
+ else {
+ psd->psd_progress = 1;
+ halrf_psd(dm, psd->point, psd->start_point, psd->stop_point, psd->average);
+ PlatformMoveMemory(outbuf, psd->psd_data, 0x400);
+ psd->psd_progress = 0;
+ }
+
+ return ret_status;
+}
+
+#endif /*#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)*/
+
diff --git a/hal/phydm/halrf/halrf_psd.h b/hal/phydm/halrf/halrf_psd.h
new file mode 100644
index 0000000..8e4b7f4
--- /dev/null
+++ b/hal/phydm/halrf/halrf_psd.h
@@ -0,0 +1,60 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ *****************************************************************************/
+
+#ifndef __HALRF_PSD_H__
+#define __HALRF_PSD_H__
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+
+struct _halrf_psd_data {
+ u32 point;
+ u32 start_point;
+ u32 stop_point;
+ u32 average;
+ u32 buf_size;
+ u32 psd_data[256];
+ u32 psd_progress;
+};
+
+
+
+enum rt_status
+halrf_psd_init (
+ struct dm_struct *dm
+ );
+
+
+
+enum rt_status
+halrf_psd_query (
+ struct dm_struct *dm,
+ u32 *outbuf,
+ u32 buf_size
+);
+
+enum rt_status
+halrf_psd_init_query(
+ struct dm_struct *dm,
+ u32 *outbuf,
+ u32 point,
+ u32 start_point,
+ u32 stop_point,
+ u32 average,
+ u32 buf_size
+);
+
+#endif /*#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)*/
+#endif /*#ifndef __HALRF_PSD_H__*/
+
diff --git a/hal/phydm/halrf/halrf_txgapcal.c b/hal/phydm/halrf/halrf_txgapcal.c
new file mode 100644
index 0000000..713f811
--- /dev/null
+++ b/hal/phydm/halrf/halrf_txgapcal.c
@@ -0,0 +1,303 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger
+ *
+ *****************************************************************************/
+#include "mp_precomp.h"
+#include "phydm_precomp.h"
+
+
+
+void odm_bub_sort(pu4Byte data, u4Byte n)
+{
+ int i, j, temp, sp;
+
+ for (i = n - 1;i >= 0;i--) {
+ sp = 1;
+ for (j = 0;j < i;j++) {
+ if (data[j] < data[j + 1]) {
+ temp = data[j];
+ data[j] = data[j + 1];
+ data[j + 1] = temp;
+ sp = 0;
+ }
+ }
+ if (sp == 1)
+ break;
+ }
+}
+
+
+#if (RTL8197F_SUPPORT == 1)
+
+u4Byte
+odm_tx_gain_gap_psd_8197f(
+ void *dm_void,
+ u1Byte rf_path,
+ u4Byte rf56
+)
+{
+ PDM_ODM_T dm = (PDM_ODM_T)dm_void;
+
+ u1Byte i, j;
+ u4Byte psd_vaule[5], psd_avg_time = 5, psd_vaule_temp;
+
+ u4Byte iqk_ctl_addr[2][6] = {{0xe30, 0xe34, 0xe50, 0xe54, 0xe38, 0xe3c},
+ {0xe50, 0xe54, 0xe30, 0xe34, 0xe58, 0xe5c}};
+
+ u4Byte psd_finish_bit[2] = {0x04000000, 0x20000000};
+ u4Byte psd_fail_bit[2] = {0x08000000, 0x40000000};
+
+ u4Byte psd_cntl_value[2][2] = {{0x38008c1c, 0x10008c1c},
+ {0x38008c2c, 0x10008c2c}};
+
+ u4Byte psd_report_addr[2] = {0xea0, 0xec0};
+
+ odm_set_rf_reg(dm, rf_path, 0xdf, bRFRegOffsetMask, 0x00e02);
+
+ ODM_delay_us(100);
+
+ odm_set_bb_reg(dm, 0xe28, 0xffffffff, 0x0);
+
+ odm_set_rf_reg(dm, rf_path, 0x56, 0xfff, rf56);
+ while(rf56 != (odm_get_rf_reg(dm, rf_path, 0x56, 0xfff)))
+ odm_set_rf_reg(dm, rf_path, 0x56, 0xfff, rf56);
+
+ odm_set_bb_reg(dm, 0xd94, 0xffffffff, 0x44FFBB44);
+ odm_set_bb_reg(dm, 0xe70, 0xffffffff, 0x00400040);
+ odm_set_bb_reg(dm, 0xc04, 0xffffffff, 0x6f005403);
+ odm_set_bb_reg(dm, 0xc08, 0xffffffff, 0x000804e4);
+ odm_set_bb_reg(dm, 0x874, 0xffffffff, 0x04203400);
+ odm_set_bb_reg(dm, 0xe28, 0xffffffff, 0x80800000);
+
+ odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][0], 0xffffffff, psd_cntl_value[rf_path][0]);
+ odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][1], 0xffffffff, psd_cntl_value[rf_path][1]);
+ odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][2], 0xffffffff, psd_cntl_value[rf_path][0]);
+ odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][3], 0xffffffff, psd_cntl_value[rf_path][0]);
+ odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][4], 0xffffffff, 0x8215001F);
+ odm_set_bb_reg(dm, iqk_ctl_addr[rf_path][5], 0xffffffff, 0x2805001F);
+
+ odm_set_bb_reg(dm, 0xe40, 0xffffffff, 0x81007C00);
+ odm_set_bb_reg(dm, 0xe44, 0xffffffff, 0x81004800);
+ odm_set_bb_reg(dm, 0xe4c, 0xffffffff, 0x0046a8d0);
+
+
+ for (i = 0; i < psd_avg_time; i++) {
+
+ for(j = 0; j < 1000 ; j++) {
+ odm_set_bb_reg(dm, 0xe48, 0xffffffff, 0xfa005800);
+ odm_set_bb_reg(dm, 0xe48, 0xffffffff, 0xf8005800);
+
+ while(!odm_get_bb_reg(dm, 0xeac, psd_finish_bit[rf_path])); /*wait finish bit*/
+
+ if (!odm_get_bb_reg(dm, 0xeac, psd_fail_bit[rf_path])) { /*check fail bit*/
+
+ psd_vaule[i] = odm_get_bb_reg(dm, psd_report_addr[rf_path], 0xffffffff);
+
+ if (psd_vaule[i] > 0xffff)
+ break;
+ }
+ }
+
+
+
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[TGGC] rf0=0x%x rf56=0x%x rf56_reg=0x%x time=%d psd_vaule=0x%x\n",
+ odm_get_rf_reg(dm, rf_path, 0x0, 0xff),
+ rf56, odm_get_rf_reg(dm, rf_path, 0x56, 0xfff), j, psd_vaule[i]);
+ }
+
+ odm_bub_sort(psd_vaule, psd_avg_time);
+
+ psd_vaule_temp = psd_vaule[(UINT)(psd_avg_time / 2)];
+
+ odm_set_bb_reg(dm, 0xd94, 0xffffffff, 0x44BBBB44);
+ odm_set_bb_reg(dm, 0xe70, 0xffffffff, 0x80408040);
+ odm_set_bb_reg(dm, 0xc04, 0xffffffff, 0x6f005433);
+ odm_set_bb_reg(dm, 0xc08, 0xffffffff, 0x000004e4);
+ odm_set_bb_reg(dm, 0x874, 0xffffffff, 0x04003400);
+ odm_set_bb_reg(dm, 0xe28, 0xffffffff, 0x00000000);
+
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[TGGC] rf0=0x%x rf56=0x%x rf56_reg=0x%x psd_vaule_temp=0x%x\n",
+ odm_get_rf_reg(dm, rf_path, 0x0, 0xff),
+ rf56, odm_get_rf_reg(dm, rf_path, 0x56, 0xfff), psd_vaule_temp);
+
+ odm_set_rf_reg(dm, rf_path, 0xdf, bRFRegOffsetMask, 0x00602);
+
+ return psd_vaule_temp;
+
+}
+
+
+
+void
+odm_tx_gain_gap_calibration_8197f(
+ void *dm_void
+)
+{
+ PDM_ODM_T dm = (PDM_ODM_T)dm_void;
+
+ u1Byte rf_path, rf0_idx, rf0_idx_current, rf0_idx_next, i, delta_gain_retry = 3;
+
+ s1Byte delta_gain_gap_pre, delta_gain_gap[2][11];
+ u4Byte rf56_current, rf56_next, psd_value_current, psd_value_next;
+ u4Byte psd_gap, rf56_current_temp[2][11];
+ s4Byte rf33[2][11];
+
+ memset(rf33, 0x0, sizeof(rf33));
+
+ for (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++) {
+
+ if (rf_path == RF_PATH_A)
+ odm_set_bb_reg(dm, 0x88c, (BIT(21) | BIT(20)), 0x3); /*disable 3-wire*/
+ else if (rf_path == RF_PATH_B)
+ odm_set_bb_reg(dm, 0x88c, (BIT(23) | BIT(22)), 0x3); /*disable 3-wire*/
+
+ ODM_delay_us(100);
+
+ for (rf0_idx = 1; rf0_idx <= 10; rf0_idx++) {
+
+ rf0_idx_current = 3 * (rf0_idx - 1) + 1;
+ odm_set_rf_reg(dm, rf_path, 0x0, 0xff, rf0_idx_current);
+ ODM_delay_us(100);
+ rf56_current_temp[rf_path][rf0_idx] = odm_get_rf_reg(dm, rf_path, 0x56, 0xfff);
+ rf56_current = rf56_current_temp[rf_path][rf0_idx];
+
+ rf0_idx_next = 3 * rf0_idx + 1;
+ odm_set_rf_reg(dm, rf_path, 0x0, 0xff, rf0_idx_next);
+ ODM_delay_us(100);
+ rf56_next= odm_get_rf_reg(dm, rf_path, 0x56, 0xfff);
+
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[TGGC] rf56_current[%d][%d]=0x%x rf56_next[%d][%d]=0x%x\n",
+ rf_path, rf0_idx, rf56_current, rf_path, rf0_idx, rf56_next);
+
+ if ((rf56_current >> 5) == (rf56_next >> 5)) {
+ delta_gain_gap[rf_path][rf0_idx] = 0;
+
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[TGGC] rf56_current[11:5] == rf56_next[%d][%d][11:5]=0x%x delta_gain_gap[%d][%d]=%d\n",
+ rf_path, rf0_idx, (rf56_next >> 5), rf_path, rf0_idx, delta_gain_gap[rf_path][rf0_idx]);
+
+ continue;
+ }
+
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[TGGC] rf56_current[%d][%d][11:5]=0x%x != rf56_next[%d][%d][11:5]=0x%x\n",
+ rf_path, rf0_idx, (rf56_current >> 5), rf_path, rf0_idx, (rf56_next >> 5));
+
+ for (i = 0; i < delta_gain_retry; i++) {
+ psd_value_current = odm_tx_gain_gap_psd_8197f(dm, rf_path, rf56_current);
+
+ psd_value_next = odm_tx_gain_gap_psd_8197f(dm, rf_path, rf56_next - 2);
+
+ psd_gap = psd_value_next / (psd_value_current / 1000);
+
+#if 0
+ if (psd_gap > 1413)
+ delta_gain_gap[rf_path][rf0_idx] = 1;
+ else if (psd_gap > 1122)
+ delta_gain_gap[rf_path][rf0_idx] = 0;
+ else
+ delta_gain_gap[rf_path][rf0_idx] = -1;
+#endif
+
+ if (psd_gap > 1445)
+ delta_gain_gap[rf_path][rf0_idx] = 1;
+ else if (psd_gap > 1096)
+ delta_gain_gap[rf_path][rf0_idx] = 0;
+ else
+ delta_gain_gap[rf_path][rf0_idx] = -1;
+
+ if (i == 0)
+ delta_gain_gap_pre = delta_gain_gap[rf_path][rf0_idx];
+
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[TGGC] psd_value_current=0x%x psd_value_next=0x%x psd_value_next/psd_value_current=%d delta_gain_gap[%d][%d]=%d\n",
+ psd_value_current, psd_value_next, psd_gap, rf_path, rf0_idx, delta_gain_gap[rf_path][rf0_idx]);
+
+ if ((i == 0) && (delta_gain_gap[rf_path][rf0_idx] == 0))
+ break;
+
+ if (delta_gain_gap_pre != delta_gain_gap[rf_path][rf0_idx]) {
+ delta_gain_gap[rf_path][rf0_idx] = 0;
+
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[TGGC] delta_gain_gap_pre(%d) != delta_gain_gap[%d][%d](%d) time=%d\n",
+ delta_gain_gap_pre, rf_path, rf0_idx, delta_gain_gap[rf_path][rf0_idx], i);
+
+ break;
+ } else {
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[TGGC] delta_gain_gap_pre(%d) == delta_gain_gap[%d][%d](%d) time=%d\n",
+ delta_gain_gap_pre, rf_path, rf0_idx, delta_gain_gap[rf_path][rf0_idx], i);
+ }
+ }
+ }
+
+ if (rf_path == RF_PATH_A)
+ odm_set_bb_reg(dm, 0x88c, (BIT(21) | BIT(20)), 0x0); /*enable 3-wire*/
+ else if (rf_path == RF_PATH_B)
+ odm_set_bb_reg(dm, 0x88c, (BIT(23) | BIT(22)), 0x0); /*enable 3-wire*/
+
+ ODM_delay_us(100);
+
+ }
+
+ /*odm_set_bb_reg(dm, 0x88c, (BIT(23) | BIT(22) | BIT(21) | BIT(20)), 0x0);*/ /*enable 3-wire*/
+
+ for (rf_path = RF_PATH_A; rf_path <= RF_PATH_B; rf_path++) {
+
+ odm_set_rf_reg(dm, rf_path, 0xef, bRFRegOffsetMask, 0x00100);
+
+ for (rf0_idx = 1; rf0_idx <= 10; rf0_idx++) {
+
+ rf33[rf_path][rf0_idx] = rf33[rf_path][rf0_idx] + (rf56_current_temp[rf_path][rf0_idx] & 0x1f);
+
+ for (i = rf0_idx; i <= 10; i++)
+ rf33[rf_path][rf0_idx] = rf33[rf_path][rf0_idx] + delta_gain_gap[rf_path][i];
+
+ if (rf33[rf_path][rf0_idx] >= 0x1d)
+ rf33[rf_path][rf0_idx] = 0x1d;
+ else if (rf33[rf_path][rf0_idx] <= 0x2)
+ rf33[rf_path][rf0_idx] = 0x2;
+
+ rf33[rf_path][rf0_idx] = rf33[rf_path][rf0_idx] + ((rf0_idx - 1) * 0x4000) + (rf56_current_temp[rf_path][rf0_idx] & 0xfffe0);
+
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[TGGC] rf56[%d][%d]=0x%05x rf33[%d][%d]=0x%05x\n", rf_path, rf0_idx, rf56_current_temp[rf_path][rf0_idx], rf_path, rf0_idx, rf33[rf_path][rf0_idx]);
+
+ odm_set_rf_reg(dm, rf_path, 0x33, bRFRegOffsetMask, rf33[rf_path][rf0_idx]);
+ }
+
+ odm_set_rf_reg(dm, rf_path, 0xef, bRFRegOffsetMask, 0x00000);
+ }
+
+}
+#endif
+
+
+void
+odm_tx_gain_gap_calibration(
+ void *dm_void
+)
+{
+ PDM_ODM_T dm = (PDM_ODM_T)dm_void;
+
+ #if (RTL8197F_SUPPORT == 1)
+ if (dm->SupportICType & ODM_RTL8197F)
+ odm_tx_gain_gap_calibration_8197f(dm_void);
+ #endif
+
+}
diff --git a/hal/phydm/halrf/halrf_txgapcal.h b/hal/phydm/halrf/halrf_txgapcal.h
new file mode 100644
index 0000000..c404114
--- /dev/null
+++ b/hal/phydm/halrf/halrf_txgapcal.h
@@ -0,0 +1,29 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger
+ *
+ *****************************************************************************/
+void
+odm_tx_gain_gap_calibration(
+ void *dm_void
+);
+
diff --git a/hal/phydm/halrf/rtl8822b/halrf_8822b.c b/hal/phydm/halrf/rtl8822b/halrf_8822b.c
new file mode 100644
index 0000000..eb28312
--- /dev/null
+++ b/hal/phydm/halrf/rtl8822b/halrf_8822b.c
@@ -0,0 +1,553 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger
+ *
+ *****************************************************************************/
+
+#include "mp_precomp.h"
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+ #if RT_PLATFORM==PLATFORM_MACOSX
+ #include "phydm_precomp.h"
+ #else
+ #include "../phydm_precomp.h"
+ #endif
+#else
+#include "../../phydm_precomp.h"
+#endif
+
+#if (RTL8822B_SUPPORT == 1)
+void
+halrf_rf_lna_setting_8822b(
+ struct dm_struct *dm_void,
+ enum phydm_lna_set type
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ u8 path = 0x0;
+
+ for (path = 0x0; path < 2; path++)
+ if (type == phydm_lna_disable) {
+ /*S0*/
+ odm_set_rf_reg(dm, (enum rf_path)path, 0xef, BIT(19), 0x1);
+ odm_set_rf_reg(dm, (enum rf_path)path, 0x33, RFREGOFFSETMASK, 0x00003);
+ odm_set_rf_reg(dm, (enum rf_path)path, 0x3e, RFREGOFFSETMASK, 0x00064);
+ odm_set_rf_reg(dm, (enum rf_path)path, 0x3f, RFREGOFFSETMASK, 0x0afce);
+ odm_set_rf_reg(dm, (enum rf_path)path, 0xef, BIT(19), 0x0);
+ } else if (type == phydm_lna_enable) {
+ /*S0*/
+ odm_set_rf_reg(dm, (enum rf_path)path, 0xef, BIT(19), 0x1);
+ odm_set_rf_reg(dm, (enum rf_path)path, 0x33, RFREGOFFSETMASK, 0x00003);
+ odm_set_rf_reg(dm, (enum rf_path)path, 0x3e, RFREGOFFSETMASK, 0x00064);
+ odm_set_rf_reg(dm, (enum rf_path)path, 0x3f, RFREGOFFSETMASK, 0x1afce);
+ odm_set_rf_reg(dm, (enum rf_path)path, 0xef, BIT(19), 0x0);
+ }
+}
+
+boolean
+get_mix_mode_tx_agc_bb_swing_offset_8822b(
+ void *dm_void,
+ enum pwrtrack_method method,
+ u8 rf_path,
+ u8 tx_power_index_offest
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
+
+ u8 bb_swing_upper_bound = cali_info->default_ofdm_index + 10;
+ u8 bb_swing_lower_bound = 0;
+
+ s8 tx_agc_index = 0;
+ u8 tx_bb_swing_index = cali_info->default_ofdm_index;
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"Path_%d cali_info->absolute_ofdm_swing_idx[rf_path]=%d, tx_power_index_offest=%d\n",
+ rf_path, cali_info->absolute_ofdm_swing_idx[rf_path], tx_power_index_offest);
+
+ if (tx_power_index_offest > 0XF)
+ tx_power_index_offest = 0XF;
+
+ if (cali_info->absolute_ofdm_swing_idx[rf_path] >= 0 && cali_info->absolute_ofdm_swing_idx[rf_path] <= tx_power_index_offest) {
+ tx_agc_index = cali_info->absolute_ofdm_swing_idx[rf_path];
+ tx_bb_swing_index = cali_info->default_ofdm_index;
+ } else if (cali_info->absolute_ofdm_swing_idx[rf_path] > tx_power_index_offest) {
+ tx_agc_index = tx_power_index_offest;
+ cali_info->remnant_ofdm_swing_idx[rf_path] = cali_info->absolute_ofdm_swing_idx[rf_path] - tx_power_index_offest;
+ tx_bb_swing_index = cali_info->default_ofdm_index + cali_info->remnant_ofdm_swing_idx[rf_path];
+
+ if (tx_bb_swing_index > bb_swing_upper_bound)
+ tx_bb_swing_index = bb_swing_upper_bound;
+ } else {
+ tx_agc_index = 0;
+
+ if (cali_info->default_ofdm_index > (cali_info->absolute_ofdm_swing_idx[rf_path] * (-1)))
+ tx_bb_swing_index = cali_info->default_ofdm_index + cali_info->absolute_ofdm_swing_idx[rf_path];
+ else
+ tx_bb_swing_index = bb_swing_lower_bound;
+
+ if (tx_bb_swing_index < bb_swing_lower_bound)
+ tx_bb_swing_index = bb_swing_lower_bound;
+ }
+
+ cali_info->absolute_ofdm_swing_idx[rf_path] = tx_agc_index;
+ cali_info->bb_swing_idx_ofdm[rf_path] = tx_bb_swing_index;
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"MixMode Offset Path_%d cali_info->absolute_ofdm_swing_idx[rf_path]=%d cali_info->bb_swing_idx_ofdm[rf_path]=%d tx_power_index_offest=%d\n",
+ rf_path, cali_info->absolute_ofdm_swing_idx[rf_path], cali_info->bb_swing_idx_ofdm[rf_path], tx_power_index_offest);
+
+ return true;
+}
+
+
+void
+odm_tx_pwr_track_set_pwr8822b(
+ void *dm_void,
+ enum pwrtrack_method method,
+ u8 rf_path,
+ u8 channel_mapped_index
+)
+{
+#if 0
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ void *adapter = dm->adapter;
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+ struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
+ u8 channel = *dm->channel;
+ u8 band_width = hal_data->current_channel_bw;
+ u8 tx_power_index = 0;
+ u8 tx_rate = 0xFF;
+ enum rt_status status = RT_STATUS_SUCCESS;
+
+ PHALMAC_PWR_TRACKING_OPTION p_pwr_tracking_opt = &(cali_info->HALMAC_PWR_TRACKING_INFO);
+
+ if (*(dm->mp_mode) == true) {
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+#if (MP_DRIVER == 1)
+ PMPT_CONTEXT p_mpt_ctx = &(adapter->mpt_ctx);
+
+ tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
+#endif
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+ PMPT_CONTEXT p_mpt_ctx = &(adapter->mppriv.mpt_ctx);
+
+ tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
+#endif
+#endif
+ } else {
+ u16 rate = *(dm->forced_data_rate);
+
+ if (!rate) { /*auto rate*/
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+ tx_rate = ((PADAPTER)adapter)->HalFunc.GetHwRateFromMRateHandler(dm->tx_rate);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+ if (dm->number_linked_client != 0)
+ tx_rate = hw_rate_to_m_rate(dm->tx_rate);
+#endif
+ } else /*force rate*/
+ tx_rate = (u8) rate;
+ }
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "Call:%s tx_rate=0x%X\n", __func__, tx_rate);
+
+ tx_power_index = phy_get_tx_power_index(adapter, (enum rf_path) rf_path, tx_rate, band_width, channel);
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "type=%d tx_power_index=%d cali_info->absolute_ofdm_swing_idx=%d cali_info->default_ofdm_index=%d rf_path=%d\n", method, tx_power_index, cali_info->absolute_ofdm_swing_idx[rf_path], cali_info->default_ofdm_index, rf_path);
+
+ p_pwr_tracking_opt->type = method;
+ p_pwr_tracking_opt->bbswing_index = cali_info->default_ofdm_index;
+ p_pwr_tracking_opt->pwr_tracking_para[rf_path].enable = 1;
+ p_pwr_tracking_opt->pwr_tracking_para[rf_path].tx_pwr_index = tx_power_index;
+ p_pwr_tracking_opt->pwr_tracking_para[rf_path].pwr_tracking_offset_value = cali_info->absolute_ofdm_swing_idx[rf_path];
+ p_pwr_tracking_opt->pwr_tracking_para[rf_path].tssi_value = 0;
+
+
+ if (rf_path == (MAX_PATH_NUM_8822B - 1)) {
+ status = hal_mac_send_power_tracking_info(&GET_HAL_MAC_INFO(adapter), p_pwr_tracking_opt);
+
+ if (status == RT_STATUS_SUCCESS) {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "path A 0xC94=0x%X 0xC1C=0x%X\n",
+ odm_get_bb_reg(dm, 0xC94, BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)),
+ odm_get_bb_reg(dm, 0xC1C, 0xFFE00000)
+ );
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "path B 0xE94=0x%X 0xE1C=0x%X\n",
+ odm_get_bb_reg(dm, 0xE94, BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)),
+ odm_get_bb_reg(dm, 0xE1C, 0xFFE00000)
+ );
+ } else {
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,
+ "Power Tracking to FW Fail ret code = %d\n", status);
+ }
+ }
+
+#endif
+
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct dm_rf_calibration_struct *cali_info = &dm->rf_calibrate_info;
+ struct _hal_rf_ *rf = &dm->rf_table;
+ u8 tx_power_index_offest = 0;
+ u8 tx_power_index = 0;
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+ struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
+ struct rtl_phy *rtlphy = &rtlpriv->phy;
+ u8 channel = rtlphy->current_channel;
+ u8 band_width = rtlphy->current_chan_bw;
+#else
+ struct _ADAPTER *adapter = (PADAPTER)dm->adapter;
+ u8 channel = *dm->channel;
+ u8 band_width = *dm->band_width;
+#endif
+ u8 tx_rate = 0xFF;
+
+ if (*dm->mp_mode == true) {
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+#if (MP_DRIVER == 1)
+ PMPT_CONTEXT p_mpt_ctx = &adapter->MptCtx;
+
+ tx_rate = MptToMgntRate(p_mpt_ctx->MptRateIndex);
+#endif
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+#ifdef CONFIG_MP_INCLUDED
+ PMPT_CONTEXT p_mpt_ctx = &adapter->mppriv.mpt_ctx;
+
+ tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
+#endif
+#endif
+#endif
+ } else {
+ u16 rate = *dm->forced_data_rate;
+
+ if (!rate) { /*auto rate*/
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+ tx_rate = ((PADAPTER)adapter)->HalFunc.GetHwRateFromMRateHandler(dm->tx_rate);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+ tx_rate = dm->tx_rate;
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+ if (dm->number_linked_client != 0)
+ tx_rate = hw_rate_to_m_rate(dm->tx_rate);
+ else
+ tx_rate = rf->p_rate_index;
+#endif
+ } else /*force rate*/
+ tx_rate = (u8) rate;
+ }
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK, "Call:%s tx_rate=0x%X\n", __func__, tx_rate);
+
+#endif
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"pRF->default_ofdm_index=%d pRF->default_cck_index=%d\n", cali_info->default_ofdm_index, cali_info->default_cck_index);
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"pRF->absolute_ofdm_swing_idx=%d pRF->remnant_ofdm_swing_idx=%d pRF->absolute_cck_swing_idx=%d pRF->remnant_cck_swing_idx=%d rf_path=%d\n",
+ cali_info->absolute_ofdm_swing_idx[rf_path], cali_info->remnant_ofdm_swing_idx[rf_path], cali_info->absolute_cck_swing_idx[rf_path], cali_info->remnant_cck_swing_idx, rf_path);
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+ tx_power_index = odm_get_tx_power_index(dm, (enum rf_path) rf_path, tx_rate, (enum channel_width)band_width, channel);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+ tx_power_index = odm_get_tx_power_index(dm, (enum rf_path) rf_path, tx_rate, band_width, channel);
+#else
+ tx_power_index = config_phydm_read_txagc_8822b(dm, rf_path, 0x04); /*0x04(TX_AGC_OFDM_6M)*/
+#endif
+
+ if (tx_power_index >= 63)
+ tx_power_index = 63;
+
+ tx_power_index_offest = 63 - tx_power_index;
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"tx_power_index=%d tx_power_index_offest=%d rf_path=%d\n", tx_power_index, tx_power_index_offest, rf_path);
+
+ if (method == BBSWING) { /*use for mp driver clean power tracking status*/
+ switch (rf_path) {
+ case RF_PATH_A:
+ odm_set_bb_reg(dm, 0xC94, (BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)), cali_info->absolute_ofdm_swing_idx[rf_path]);
+ odm_set_bb_reg(dm, REG_A_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]);
+ break;
+ case RF_PATH_B:
+ odm_set_bb_reg(dm, 0xE94, (BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)), cali_info->absolute_ofdm_swing_idx[rf_path]);
+ odm_set_bb_reg(dm, REG_B_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]);
+ break;
+
+ default:
+ break;
+ }
+ } else if (method == MIX_MODE) {
+ switch (rf_path) {
+ case RF_PATH_A:
+ get_mix_mode_tx_agc_bb_swing_offset_8822b(dm, method, rf_path, tx_power_index_offest);
+ odm_set_bb_reg(dm, 0xC94, (BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)), cali_info->absolute_ofdm_swing_idx[rf_path]);
+ odm_set_bb_reg(dm, REG_A_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]);
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"TXAGC(0xC94)=0x%x BBSwing(0xc1c)=0x%x BBSwingIndex=%d rf_path=%d\n",
+ odm_get_bb_reg(dm, 0xC94, (BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25))),
+ odm_get_bb_reg(dm, 0xc1c, 0xFFE00000),
+ cali_info->bb_swing_idx_ofdm[rf_path], rf_path);
+ break;
+
+ case RF_PATH_B:
+ get_mix_mode_tx_agc_bb_swing_offset_8822b(dm, method, rf_path, tx_power_index_offest);
+ odm_set_bb_reg(dm, 0xE94, (BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)), cali_info->absolute_ofdm_swing_idx[rf_path]);
+ odm_set_bb_reg(dm, REG_B_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[cali_info->bb_swing_idx_ofdm[rf_path]]);
+
+ PHYDM_DBG(dm, ODM_COMP_TX_PWR_TRACK,"TXAGC(0xE94)=0x%x BBSwing(0xe1c)=0x%x BBSwingIndex=%d rf_path=%d\n",
+ odm_get_bb_reg(dm, 0xE94, (BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25))),
+ odm_get_bb_reg(dm, 0xe1c, 0xFFE00000),
+ cali_info->bb_swing_idx_ofdm[rf_path], rf_path);
+ break;
+
+ default:
+ break;
+ }
+ }
+}
+
+
+void
+get_delta_swing_table_8822b(
+ void *dm_void,
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ u8 **temperature_up_a,
+ u8 **temperature_down_a,
+ u8 **temperature_up_b,
+ u8 **temperature_down_b,
+ u8 **temperature_up_cck_a,
+ u8 **temperature_down_cck_a,
+ u8 **temperature_up_cck_b,
+ u8 **temperature_down_cck_b
+#else
+ u8 **temperature_up_a,
+ u8 **temperature_down_a,
+ u8 **temperature_up_b,
+ u8 **temperature_down_b
+#endif
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ u8 channel = *(dm->channel);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
+ struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
+ struct rtl_phy *rtlphy = &(rtlpriv->phy);
+ u8 channel = rtlphy->current_channel;
+#else
+ void *adapter = dm->adapter;
+ u8 channel = *dm->channel;
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ *temperature_up_cck_a = cali_info->delta_swing_table_idx_2g_cck_a_p;
+ *temperature_down_cck_a = cali_info->delta_swing_table_idx_2g_cck_a_n;
+ *temperature_up_cck_b = cali_info->delta_swing_table_idx_2g_cck_b_p;
+ *temperature_down_cck_b = cali_info->delta_swing_table_idx_2g_cck_b_n;
+#endif
+
+ *temperature_up_a = cali_info->delta_swing_table_idx_2ga_p;
+ *temperature_down_a = cali_info->delta_swing_table_idx_2ga_n;
+ *temperature_up_b = cali_info->delta_swing_table_idx_2gb_p;
+ *temperature_down_b = cali_info->delta_swing_table_idx_2gb_n;
+
+ if (36 <= channel && channel <= 64) {
+ *temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[0];
+ *temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[0];
+ *temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[0];
+ *temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[0];
+ } else if (100 <= channel && channel <= 144) {
+ *temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[1];
+ *temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[1];
+ *temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[1];
+ *temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[1];
+ } else if (149 <= channel && channel <= 177) {
+ *temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[2];
+ *temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[2];
+ *temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[2];
+ *temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[2];
+ }
+}
+
+
+void
+_phy_lc_calibrate_8822b(
+ struct dm_struct *dm
+)
+{
+ u32 lc_cal = 0, cnt = 0,tmp0xc00, tmp0xe00;
+
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[LCK]LCK start!!!!!!!\n");
+ tmp0xc00 = odm_read_4byte(dm, 0xc00);
+ tmp0xe00 = odm_read_4byte(dm, 0xe00);
+ odm_write_4byte(dm, 0xc00, 0x4);
+ odm_write_4byte(dm, 0xe00, 0x4);
+ odm_set_rf_reg(dm, RF_PATH_A, 0x0, RFREGOFFSETMASK, 0x10000);
+ odm_set_rf_reg(dm, RF_PATH_B, 0x0, RFREGOFFSETMASK, 0x10000);
+ /*backup RF0x18*/
+ lc_cal = odm_get_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK);
+ /*disable RTK*/
+ odm_set_rf_reg(dm, RF_PATH_A, 0xc4, RFREGOFFSETMASK, 0x01402);
+ /*Start LCK*/
+ odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal | 0x08000);
+ ODM_delay_ms(100);
+ for (cnt = 0; cnt < 100; cnt++) {
+ if (odm_get_rf_reg(dm, RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1)
+ break;
+ ODM_delay_ms(10);
+ }
+ /*Recover channel number*/
+ odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal);
+ /*enable RTK*/
+ odm_set_rf_reg(dm, RF_PATH_A, 0xc4, RFREGOFFSETMASK, 0x81402);
+ /**restore*/
+ odm_write_4byte(dm, 0xc00, tmp0xc00);
+ odm_write_4byte(dm, 0xe00, tmp0xe00);
+ odm_set_rf_reg(dm, RF_PATH_A, 0x0, RFREGOFFSETMASK, 0x3ffff);
+ odm_set_rf_reg(dm, RF_PATH_B, 0x0, RFREGOFFSETMASK, 0x3ffff);
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[LCK]LCK end!!!!!!!\n");
+}
+
+/*LCK VERSION:0x1*/
+void
+phy_lc_calibrate_8822b(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+ _phy_lc_calibrate_8822b(dm);
+}
+
+
+
+void configure_txpower_track_8822b(
+ struct txpwrtrack_cfg *config
+)
+{
+ config->swing_table_size_cck = TXSCALE_TABLE_SIZE;
+ config->swing_table_size_ofdm = TXSCALE_TABLE_SIZE;
+ config->threshold_iqk = IQK_THRESHOLD;
+ config->threshold_dpk = DPK_THRESHOLD;
+ config->average_thermal_num = AVG_THERMAL_NUM_8822B;
+ config->rf_path_count = MAX_PATH_NUM_8822B;
+ config->thermal_reg_addr = RF_T_METER_8822B;
+
+ config->odm_tx_pwr_track_set_pwr = odm_tx_pwr_track_set_pwr8822b;
+ config->do_iqk = do_iqk_8822b;
+ config->phy_lc_calibrate = halrf_lck_trigger;
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ config->get_delta_all_swing_table = get_delta_swing_table_8822b;
+#else
+ config->get_delta_swing_table = get_delta_swing_table_8822b;
+#endif
+}
+
+
+void phy_set_rf_path_switch_8822b(
+#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
+ struct dm_struct *dm,
+#else
+ void *adapter,
+#endif
+ boolean is_main
+)
+{
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+ struct dm_struct *dm = &hal_data->DM_OutSrc;
+#endif
+#endif
+
+ /*BY SY Request */
+ odm_set_bb_reg(dm, 0x4C, (BIT(24) | BIT(23)), 0x2);
+
+ odm_set_bb_reg(dm, 0x974, 0xff, 0xff);
+
+ /*odm_set_bb_reg(dm, 0x1991, 0x3, 0x0);*/
+ odm_set_bb_reg(dm, 0x1990, (BIT(9) | BIT(8)), 0x0);
+
+ /*odm_set_bb_reg(dm, 0xCBE, 0x8, 0x0);*/
+ odm_set_bb_reg(dm, 0xCBC, BIT(19), 0x0);
+
+ odm_set_bb_reg(dm, 0xCB4, 0xff, 0x77);
+
+ odm_set_bb_reg(dm, 0x70, MASKBYTE3, 0x0e);
+ odm_set_bb_reg(dm, 0x1704, MASKDWORD, 0x0000ff00);
+ odm_set_bb_reg(dm, 0x1700, MASKDWORD, 0xc00f0038);
+
+ if (is_main) {
+ /*odm_set_bb_reg(dm, 0xCBD, 0x3, 0x2); WiFi */
+ odm_set_bb_reg(dm, 0xCBC, (BIT(9) | BIT(8)), 0x2); /*WiFi */
+ } else {
+ /*odm_set_bb_reg(dm, 0xCBD, 0x3, 0x1); BT*/
+ odm_set_bb_reg(dm, 0xCBC, (BIT(9) | BIT(8)), 0x1); /*BT*/
+ }
+}
+
+boolean
+_phy_query_rf_path_switch_8822b(
+#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
+ struct dm_struct *dm
+#else
+ void *adapter
+#endif
+)
+{
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+ struct dm_struct *dm = &hal_data->DM_OutSrc;
+#endif
+#endif
+
+ if (odm_get_bb_reg(dm, 0xCBC, (BIT(9) | BIT(8))) == 0x2) /*WiFi */
+ return true;
+ else
+ return false;
+}
+
+
+boolean phy_query_rf_path_switch_8822b(
+#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
+ struct dm_struct *dm
+#else
+ void *adapter
+#endif
+)
+{
+#if DISABLE_BB_RF
+ return true;
+#endif
+
+#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
+ return _phy_query_rf_path_switch_8822b(dm);
+#else
+ return _phy_query_rf_path_switch_8822b(adapter);
+#endif
+}
+
+
+#endif /* (RTL8822B_SUPPORT == 0)*/
diff --git a/hal/phydm/halrf/rtl8822b/halrf_8822b.h b/hal/phydm/halrf/rtl8822b/halrf_8822b.h
new file mode 100644
index 0000000..ea1c115
--- /dev/null
+++ b/hal/phydm/halrf/rtl8822b/halrf_8822b.h
@@ -0,0 +1,85 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger
+ *
+ *****************************************************************************/
+
+#ifndef __HAL_PHY_RF_8822B_H__
+#define __HAL_PHY_RF_8822B_H__
+
+#define AVG_THERMAL_NUM_8822B 4
+#define RF_T_METER_8822B 0x42
+
+void configure_txpower_track_8822b(
+ struct txpwrtrack_cfg *config
+);
+
+void
+odm_tx_pwr_track_set_pwr8822b(
+ void *dm_void,
+ enum pwrtrack_method method,
+ u8 rf_path,
+ u8 channel_mapped_index
+);
+
+void
+get_delta_swing_table_8822b(
+ void *dm_void,
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ u8 **temperature_up_a,
+ u8 **temperature_down_a,
+ u8 **temperature_up_b,
+ u8 **temperature_down_b,
+ u8 **temperature_up_cck_a,
+ u8 **temperature_down_cck_a,
+ u8 **temperature_up_cck_b,
+ u8 **temperature_down_cck_b
+#else
+ u8 **temperature_up_a,
+ u8 **temperature_down_a,
+ u8 **temperature_up_b,
+ u8 **temperature_down_b
+#endif
+);
+
+void
+phy_lc_calibrate_8822b(
+ void *dm_void
+);
+
+void
+halrf_rf_lna_setting_8822b(
+ struct dm_struct *dm,
+ enum phydm_lna_set type
+);
+
+
+void phy_set_rf_path_switch_8822b(
+#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
+ struct dm_struct *dm,
+#else
+ void *adapter,
+#endif
+ boolean is_main
+);
+
+#endif /* #ifndef __HAL_PHY_RF_8822B_H__ */
diff --git a/hal/phydm/halrf/rtl8822b/halrf_iqk_8822b.c b/hal/phydm/halrf/rtl8822b/halrf_iqk_8822b.c
new file mode 100644
index 0000000..8017135
--- /dev/null
+++ b/hal/phydm/halrf/rtl8822b/halrf_iqk_8822b.c
@@ -0,0 +1,1811 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger
+ *
+ *****************************************************************************/
+
+#include "mp_precomp.h"
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+ #if RT_PLATFORM==PLATFORM_MACOSX
+ #include "phydm_precomp.h"
+ #else
+ #include "../phydm_precomp.h"
+ #endif
+#else
+#include "../../phydm_precomp.h"
+#endif
+
+#if (RTL8822B_SUPPORT == 1)
+
+
+/*---------------------------Define Local Constant---------------------------*/
+
+
+void phydm_get_read_counter(struct dm_struct *dm)
+{
+ u32 counter = 0x0;
+
+ while (1) {
+ if ((odm_get_rf_reg(dm, RF_PATH_A, 0x8, RFREGOFFSETMASK) == 0xabcde) || (counter > 300))
+ break;
+ counter++;
+ ODM_delay_ms(1);
+ };
+ odm_set_rf_reg(dm, RF_PATH_A, 0x8, RFREGOFFSETMASK, 0x0);
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]counter = %d\n", counter);
+}
+
+/*---------------------------Define Local Constant---------------------------*/
+
+
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+void do_iqk_8822b(
+ void *dm_void,
+ u8 delta_thermal_index,
+ u8 thermal_value,
+ u8 threshold
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+
+ dm->rf_calibrate_info.thermal_value_iqk = thermal_value;
+ halrf_segment_iqk_trigger(dm, true, iqk_info->segment_iqk);
+}
+#else
+/*Originally config->do_iqk is hooked phy_iq_calibrate_8822b, but do_iqk_8822b and phy_iq_calibrate_8822b have different arguments*/
+void do_iqk_8822b(
+ void *dm_void,
+ u8 delta_thermal_index,
+ u8 thermal_value,
+ u8 threshold
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+ boolean is_recovery = (boolean) delta_thermal_index;
+
+ halrf_segment_iqk_trigger(dm, true, iqk_info->segment_iqk);
+}
+#endif
+
+
+
+void
+_iqk_rf_set_check(
+ struct dm_struct *dm,
+ u8 path,
+ u16 add,
+ u32 data
+ )
+{
+ u32 i;
+
+ odm_set_rf_reg(dm, (enum rf_path)path, add, RFREGOFFSETMASK, data);
+
+ for (i = 0; i < 100; i++) {
+ if (odm_get_rf_reg(dm, (enum rf_path)path, add, RFREGOFFSETMASK) == data)
+ break;
+ else {
+ ODM_delay_us(10);
+ odm_set_rf_reg(dm, (enum rf_path)path, add, RFREGOFFSETMASK, data);
+ }
+ }
+}
+
+
+void
+_iqk_rf0xb0_workaround(
+ struct dm_struct *dm
+ )
+{
+ /*add 0xb8 control for the bad phase noise after switching channel*/
+ odm_set_rf_reg(dm, (enum rf_path)0x0, 0xb8, RFREGOFFSETMASK, 0x00a00);
+ odm_set_rf_reg(dm, (enum rf_path)0x0, 0xb8, RFREGOFFSETMASK, 0x80a00);
+}
+
+void
+_iqk_fill_iqk_report_8822b(
+ void *dm_void,
+ u8 channel
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+ u32 tmp1 = 0x0, tmp2 = 0x0, tmp3 = 0x0;
+ u8 i;
+
+ for (i = 0; i < SS_8822B; i++) {
+ tmp1 = tmp1 + ((iqk_info->iqk_fail_report[channel][i][TX_IQK] & 0x1) << i);
+ tmp2 = tmp2 + ((iqk_info->iqk_fail_report[channel][i][RX_IQK] & 0x1) << (i + 4));
+ tmp3 = tmp3 + ((iqk_info->rxiqk_fail_code[channel][i] & 0x3) << (i * 2 + 8));
+ }
+ odm_write_4byte(dm, 0x1b00, 0xf8000008);
+ odm_set_bb_reg(dm, 0x1bf0, 0x0000ffff, tmp1 | tmp2 | tmp3);
+
+ for (i = 0; i < 2; i++)
+ odm_write_4byte(dm, 0x1be8 + (i * 4), (iqk_info->rxiqk_agc[channel][(i * 2) + 1] << 16) | iqk_info->rxiqk_agc[channel][i * 2]);
+}
+
+void
+_iqk_fail_count_8822b(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+ u8 i;
+
+ dm->n_iqk_cnt++;
+ if (odm_get_rf_reg(dm, RF_PATH_A, 0x1bf0, BIT(16)) == 1)
+ iqk_info->is_reload = true;
+ else
+ iqk_info->is_reload = false;
+
+ if (!iqk_info->is_reload) {
+ for (i = 0; i < 8; i++) {
+ if (odm_get_bb_reg(dm, 0x1bf0, BIT(i)) == 1)
+ dm->n_iqk_fail_cnt++;
+ }
+ }
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]All/Fail = %d %d\n", dm->n_iqk_cnt, dm->n_iqk_fail_cnt);
+}
+
+void
+_iqk_iqk_fail_report_8822b(
+ struct dm_struct *dm
+)
+{
+ u32 tmp1bf0 = 0x0;
+ u8 i;
+
+ tmp1bf0 = odm_read_4byte(dm, 0x1bf0);
+
+ for (i = 0; i < 4; i++) {
+ if (tmp1bf0 & (0x1 << i))
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK] please check S%d TXIQK\n", i);
+#else
+ panic_printk("[IQK] please check S%d TXIQK\n", i);
+#endif
+ if (tmp1bf0 & (0x1 << (i + 12)))
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK] please check S%d RXIQK\n", i);
+#else
+ panic_printk("[IQK] please check S%d RXIQK\n", i);
+#endif
+
+ }
+}
+
+
+void
+_iqk_backup_mac_bb_8822b(
+ struct dm_struct *dm,
+ u32 *MAC_backup,
+ u32 *BB_backup,
+ u32 *backup_mac_reg,
+ u32 *backup_bb_reg
+)
+{
+ u32 i;
+ for (i = 0; i < MAC_REG_NUM_8822B; i++)
+ MAC_backup[i] = odm_read_4byte(dm, backup_mac_reg[i]);
+
+ for (i = 0; i < BB_REG_NUM_8822B; i++)
+ BB_backup[i] = odm_read_4byte(dm, backup_bb_reg[i]);
+
+ /* PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]BackupMacBB Success!!!!\n"); */
+}
+
+
+void
+_iqk_backup_rf_8822b(
+ struct dm_struct *dm,
+ u32 RF_backup[][2],
+ u32 *backup_rf_reg
+)
+{
+ u32 i;
+
+ for (i = 0; i < RF_REG_NUM_8822B; i++) {
+ RF_backup[i][RF_PATH_A] = odm_get_rf_reg(dm, RF_PATH_A, backup_rf_reg[i], RFREGOFFSETMASK);
+ RF_backup[i][RF_PATH_B] = odm_get_rf_reg(dm, RF_PATH_B, backup_rf_reg[i], RFREGOFFSETMASK);
+ }
+ /* PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]BackupRF Success!!!!\n"); */
+}
+
+
+void
+_iqk_agc_bnd_int_8822b(
+ struct dm_struct *dm
+)
+{
+ /*initialize RX AGC bnd, it must do after bbreset*/
+ odm_write_4byte(dm, 0x1b00, 0xf8000008);
+ odm_write_4byte(dm, 0x1b00, 0xf80a7008);
+ odm_write_4byte(dm, 0x1b00, 0xf8015008);
+ odm_write_4byte(dm, 0x1b00, 0xf8000008);
+ /*PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]init. rx agc bnd\n");*/
+}
+
+
+void
+_iqk_bb_reset_8822b(
+ struct dm_struct *dm
+)
+{
+ boolean cca_ing = false;
+ u32 count = 0;
+
+ odm_set_rf_reg(dm, RF_PATH_A, 0x0, RFREGOFFSETMASK, 0x10000);
+ odm_set_rf_reg(dm, RF_PATH_B, 0x0, RFREGOFFSETMASK, 0x10000);
+ /*reset BB report*/
+ odm_set_bb_reg(dm, 0x8f8, 0x0ff00000, 0x0);
+
+ while (1) {
+ odm_write_4byte(dm, 0x8fc, 0x0);
+ odm_set_bb_reg(dm, 0x198c, 0x7, 0x7);
+ cca_ing = (boolean) odm_get_bb_reg(dm, 0xfa0, BIT(3));
+
+ if (count > 30)
+ cca_ing = false;
+
+ if (cca_ing) {
+ ODM_delay_ms(1);
+ count++;
+ } else {
+ odm_write_1byte(dm, 0x808, 0x0); /*RX ant off*/
+ odm_set_bb_reg(dm, 0xa04, BIT(27) | BIT(26) | BIT(25) | BIT(24), 0x0); /*CCK RX path off*/
+
+ /*BBreset*/
+ odm_set_bb_reg(dm, 0x0, BIT(16), 0x0);
+ odm_set_bb_reg(dm, 0x0, BIT(16), 0x1);
+
+ if (odm_get_bb_reg(dm, 0x660, BIT(16)))
+ odm_write_4byte(dm, 0x6b4, 0x89000006);
+ /*PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]BBreset!!!!\n");*/
+ break;
+ }
+ }
+}
+
+void
+_iqk_afe_setting_8822b(
+ struct dm_struct *dm,
+ boolean do_iqk
+)
+{
+ if (do_iqk) {
+ odm_write_4byte(dm, 0xc60, 0x50000000);
+ odm_write_4byte(dm, 0xc60, 0x70070040);
+ odm_write_4byte(dm, 0xe60, 0x50000000);
+ odm_write_4byte(dm, 0xe60, 0x70070040);
+ odm_write_4byte(dm, 0xc58, 0xd8000402);
+ odm_write_4byte(dm, 0xc5c, 0xd1000120);
+ odm_write_4byte(dm, 0xc6c, 0x00000a15);
+ odm_write_4byte(dm, 0xe58, 0xd8000402);
+ odm_write_4byte(dm, 0xe5c, 0xd1000120);
+ odm_write_4byte(dm, 0xe6c, 0x00000a15);
+ _iqk_bb_reset_8822b(dm);
+ /* PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]AFE setting for IQK mode!!!!\n"); */
+ } else {
+ odm_write_4byte(dm, 0xc60, 0x50000000);
+ odm_write_4byte(dm, 0xc60, 0x70038040);
+ odm_write_4byte(dm, 0xe60, 0x50000000);
+ odm_write_4byte(dm, 0xe60, 0x70038040);
+ odm_write_4byte(dm, 0xc58, 0xd8020402);
+ odm_write_4byte(dm, 0xc5c, 0xde000120);
+ odm_write_4byte(dm, 0xc6c, 0x0000122a);
+ odm_write_4byte(dm, 0xe58, 0xd8020402);
+ odm_write_4byte(dm, 0xe5c, 0xde000120);
+ odm_write_4byte(dm, 0xe6c, 0x0000122a);
+ /* PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]AFE setting for Normal mode!!!!\n"); */
+ }
+ /*0x9a4[31]=0: Select da clock*/
+ odm_set_bb_reg(dm, 0x9a4, BIT(31), 0x0);
+}
+
+void
+_iqk_restore_mac_bb_8822b(
+ struct dm_struct *dm,
+ u32 *MAC_backup,
+ u32 *BB_backup,
+ u32 *backup_mac_reg,
+ u32 *backup_bb_reg
+)
+{
+ u32 i;
+
+ for (i = 0; i < MAC_REG_NUM_8822B; i++)
+ odm_write_4byte(dm, backup_mac_reg[i], MAC_backup[i]);
+ for (i = 0; i < BB_REG_NUM_8822B; i++)
+ odm_write_4byte(dm, backup_bb_reg[i], BB_backup[i]);
+ /* PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]RestoreMacBB Success!!!!\n"); */
+}
+
+void
+_iqk_restore_rf_8822b(
+ struct dm_struct *dm,
+ u32 *backup_rf_reg,
+ u32 RF_backup[][2]
+)
+{
+ u32 i;
+
+ odm_set_rf_reg(dm, RF_PATH_A, 0xef, RFREGOFFSETMASK, 0x0);
+ odm_set_rf_reg(dm, RF_PATH_B, 0xef, RFREGOFFSETMASK, 0x0);
+ /*0xdf[4]=0*/
+ _iqk_rf_set_check(dm, RF_PATH_A, 0xdf, RF_backup[0][RF_PATH_A] & (~BIT(4)));
+ _iqk_rf_set_check(dm, RF_PATH_B, 0xdf, RF_backup[0][RF_PATH_B] & (~BIT(4)));
+
+ /*odm_set_rf_reg(dm, RF_PATH_A, 0xdf, RFREGOFFSETMASK, RF_backup[0][RF_PATH_A] & (~BIT(4)));*/
+ /*odm_set_rf_reg(dm, RF_PATH_B, 0xdf, RFREGOFFSETMASK, RF_backup[0][RF_PATH_B] & (~BIT(4)));*/
+
+ for (i = 1; i < RF_REG_NUM_8822B; i++) {
+ odm_set_rf_reg(dm, RF_PATH_A, backup_rf_reg[i], RFREGOFFSETMASK, RF_backup[i][RF_PATH_A]);
+ odm_set_rf_reg(dm, RF_PATH_B, backup_rf_reg[i], RFREGOFFSETMASK, RF_backup[i][RF_PATH_B]);
+ }
+ /* PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]RestoreRF Success!!!!\n"); */
+
+}
+
+
+void
+_iqk_backup_iqk_8822b(
+ struct dm_struct *dm,
+ u8 step,
+ u8 path
+)
+{
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+ u8 i, j, k;
+
+ switch (step) {
+ case 0:
+ iqk_info->iqk_channel[1] = iqk_info->iqk_channel[0];
+ for (i = 0; i < 2; i++) {
+ iqk_info->lok_idac[1][i] = iqk_info->lok_idac[0][i];
+ iqk_info->rxiqk_agc[1][i] = iqk_info->rxiqk_agc[0][i];
+ iqk_info->bypass_iqk[1][i] = iqk_info->bypass_iqk[0][i];
+ iqk_info->rxiqk_fail_code[1][i] = iqk_info->rxiqk_fail_code[0][i];
+ for (j = 0; j < 2; j++) {
+ iqk_info->iqk_fail_report[1][i][j] = iqk_info->iqk_fail_report[0][i][j];
+ for (k = 0; k < 8; k++) {
+ iqk_info->iqk_cfir_real[1][i][j][k] = iqk_info->iqk_cfir_real[0][i][j][k];
+ iqk_info->iqk_cfir_imag[1][i][j][k] = iqk_info->iqk_cfir_imag[0][i][j][k];
+ }
+ }
+ }
+
+ for (i = 0; i < 4; i++) {
+ iqk_info->rxiqk_fail_code[0][i] = 0x0;
+ iqk_info->rxiqk_agc[0][i] = 0x0;
+ for (j = 0; j < 2; j++) {
+ iqk_info->iqk_fail_report[0][i][j] = true;
+ iqk_info->gs_retry_count[0][i][j] = 0x0;
+ }
+ for (j = 0; j < 3; j++)
+ iqk_info->retry_count[0][i][j] = 0x0;
+ }
+ /*backup channel*/
+ iqk_info->iqk_channel[0] = iqk_info->rf_reg18;
+ break;
+ case 1: /*LOK backup*/
+ iqk_info->lok_idac[0][path] = odm_get_rf_reg(dm, (enum rf_path)path, 0x58, RFREGOFFSETMASK);
+ break;
+ case 2: /*TXIQK backup*/
+ case 3: /*RXIQK backup*/
+ phydm_get_iqk_cfir(dm, (step-2), path, false);
+ break;
+ }
+}
+
+void
+_iqk_reload_iqk_setting_8822b(
+ struct dm_struct *dm,
+ u8 channel,
+ u8 reload_idx /*1: reload TX, 2: reload LO, TX, RX*/
+)
+{
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+ u8 i, path, idx;
+ u16 iqk_apply[2] = {0xc94, 0xe94};
+ u32 tmp;
+
+ for (path = 0; path < 2; path++) {
+ if (reload_idx == 2) {
+ /*odm_set_rf_reg(dm, (enum rf_path)path, 0xdf, BIT(4), 0x1);*/
+ tmp = odm_get_rf_reg(dm, (enum rf_path)path, 0xdf, RFREGOFFSETMASK) | BIT(4);
+ _iqk_rf_set_check(dm, (enum rf_path)path, 0xdf, tmp);
+ odm_set_rf_reg(dm, (enum rf_path)path, 0x58, RFREGOFFSETMASK, iqk_info->lok_idac[channel][path]);
+ }
+
+ for (idx = 0; idx < reload_idx; idx++) {
+ odm_set_bb_reg(dm, 0x1b00, MASKDWORD, 0xf8000008 | path << 1);
+ odm_set_bb_reg(dm, 0x1b2c, MASKDWORD, 0x7);
+ odm_set_bb_reg(dm, 0x1b38, MASKDWORD, 0x20000000);
+ odm_set_bb_reg(dm, 0x1b3c, MASKDWORD, 0x20000000);
+ odm_set_bb_reg(dm, 0x1bcc, MASKDWORD, 0x00000000);
+ if (idx == 0)
+ odm_set_bb_reg(dm, 0x1b0c, BIT(13) | BIT(12), 0x3);
+ else
+ odm_set_bb_reg(dm, 0x1b0c, BIT(13) | BIT(12), 0x1);
+ odm_set_bb_reg(dm, 0x1bd4, BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16), 0x10);
+ for (i = 0; i < 8; i++) {
+ odm_write_4byte(dm, 0x1bd8, ((0xc0000000 >> idx) + 0x3) + (i * 4) + (iqk_info->iqk_cfir_real[channel][path][idx][i] << 9));
+ odm_write_4byte(dm, 0x1bd8, ((0xc0000000 >> idx) + 0x1) + (i * 4) + (iqk_info->iqk_cfir_imag[channel][path][idx][i] << 9));
+ }
+ if (idx == 0)
+ odm_set_bb_reg(dm, iqk_apply[path], BIT(0), !(iqk_info->iqk_fail_report[channel][path][idx]));
+ else
+ odm_set_bb_reg(dm, iqk_apply[path], BIT(10), !(iqk_info->iqk_fail_report[channel][path][idx]));
+ }
+ odm_set_bb_reg(dm, 0x1bd8, MASKDWORD, 0x0);
+ odm_set_bb_reg(dm, 0x1b0c, BIT(13) | BIT(12), 0x0);
+ }
+}
+
+boolean
+_iqk_reload_iqk_8822b(
+ struct dm_struct *dm,
+ boolean reset
+)
+{
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+ u8 i;
+ iqk_info->is_reload = false;
+
+ if (reset) {
+ for (i = 0; i < 2; i++)
+ iqk_info->iqk_channel[i] = 0x0;
+ } else {
+ iqk_info->rf_reg18 = odm_get_rf_reg(dm, RF_PATH_A, 0x18, RFREGOFFSETMASK);
+
+ for (i = 0; i < 2; i++) {
+ if (iqk_info->rf_reg18 == iqk_info->iqk_channel[i]) {
+ _iqk_reload_iqk_setting_8822b(dm, i, 2);
+ _iqk_fill_iqk_report_8822b(dm, i);
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]reload IQK result before!!!!\n");
+ iqk_info->is_reload = true;
+ }
+ }
+ }
+ /*report*/
+ odm_set_bb_reg(dm, 0x1bf0, BIT(16), (u8) iqk_info->is_reload);
+ return iqk_info->is_reload;
+}
+
+
+void
+_iqk_rfe_setting_8822b(
+ struct dm_struct *dm,
+ boolean ext_pa_on
+)
+{
+ if (ext_pa_on) {
+ /*RFE setting*/
+ odm_write_4byte(dm, 0xcb0, 0x77777777);
+ odm_write_4byte(dm, 0xcb4, 0x00007777);
+ odm_write_4byte(dm, 0xcbc, 0x0000083B);
+ odm_write_4byte(dm, 0xeb0, 0x77777777);
+ odm_write_4byte(dm, 0xeb4, 0x00007777);
+ odm_write_4byte(dm, 0xebc, 0x0000083B);
+ /*odm_write_4byte(dm, 0x1990, 0x00000c30);*/
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]external PA on!!!!\n");
+ } else {
+ /*RFE setting*/
+ odm_write_4byte(dm, 0xcb0, 0x77777777);
+ odm_write_4byte(dm, 0xcb4, 0x00007777);
+ odm_write_4byte(dm, 0xcbc, 0x00000100);
+ odm_write_4byte(dm, 0xeb0, 0x77777777);
+ odm_write_4byte(dm, 0xeb4, 0x00007777);
+ odm_write_4byte(dm, 0xebc, 0x00000100);
+ /*odm_write_4byte(dm, 0x1990, 0x00000c30);*/
+ /* PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]external PA off!!!!\n");*/
+ }
+}
+
+
+void
+_iqk_rf_setting_8822b(
+ struct dm_struct *dm
+)
+{
+ u8 path;
+ u32 tmp;
+
+ odm_write_4byte(dm, 0x1b00, 0xf8000008);
+ odm_write_4byte(dm, 0x1bb8, 0x00000000);
+
+ for (path = 0; path < 2; path++) {
+ /*0xdf:B11 = 1,B4 = 0, B1 = 1*/
+ tmp = odm_get_rf_reg(dm, (enum rf_path)path, 0xdf, RFREGOFFSETMASK);
+ tmp = (tmp & (~BIT(4))) | BIT(1) | BIT(11);
+ _iqk_rf_set_check(dm, (enum rf_path)path, 0xdf, tmp);
+ /*odm_set_rf_reg(dm, (enum rf_path)path, 0xdf, RFREGOFFSETMASK, tmp);*/
+
+ /*release 0x56 TXBB*/
+ odm_set_rf_reg(dm, (enum rf_path)path, 0x65, RFREGOFFSETMASK, 0x09000);
+
+ if (*dm->band_type == ODM_BAND_5G) {
+ odm_set_rf_reg(dm, (enum rf_path)path, 0xef, BIT(19), 0x1);
+ odm_set_rf_reg(dm, (enum rf_path)path, 0x33, RFREGOFFSETMASK, 0x00026);
+ odm_set_rf_reg(dm, (enum rf_path)path, 0x3e, RFREGOFFSETMASK, 0x00037);
+ odm_set_rf_reg(dm, (enum rf_path)path, 0x3f, RFREGOFFSETMASK, 0xdefce);
+ odm_set_rf_reg(dm, (enum rf_path)path, 0xef, BIT(19), 0x0);
+ } else {
+ odm_set_rf_reg(dm, (enum rf_path)path, 0xef, BIT(19), 0x1);
+ odm_set_rf_reg(dm, (enum rf_path)path, 0x33, RFREGOFFSETMASK, 0x00026);
+ odm_set_rf_reg(dm, (enum rf_path)path, 0x3e, RFREGOFFSETMASK, 0x00037);
+ odm_set_rf_reg(dm, (enum rf_path)path, 0x3f, RFREGOFFSETMASK, 0x5efce);
+ odm_set_rf_reg(dm, (enum rf_path)path, 0xef, BIT(19), 0x0);
+ }
+ }
+}
+
+
+
+void
+_iqk_configure_macbb_8822b(
+ struct dm_struct *dm
+)
+{
+ /*MACBB register setting*/
+ odm_write_1byte(dm, 0x522, 0x7f);
+ odm_set_bb_reg(dm, 0x550, BIT(11) | BIT(3), 0x0);
+ odm_set_bb_reg(dm, 0x90c, BIT(15), 0x1); /*0x90c[15]=1: dac_buf reset selection*/
+ /*0xc94[0]=1, 0xe94[0]=1: Let tx from IQK*/
+ odm_set_bb_reg(dm, 0xc94, BIT(0), 0x1);
+ odm_set_bb_reg(dm, 0xe94, BIT(0), 0x1);
+ odm_set_bb_reg(dm, 0xc94, (BIT(11) | BIT(10)), 0x1);
+ odm_set_bb_reg(dm, 0xe94, (BIT(11) | BIT(10)), 0x1);
+ /* 3-wire off*/
+ odm_write_4byte(dm, 0xc00, 0x00000004);
+ odm_write_4byte(dm, 0xe00, 0x00000004);
+ /*disable PMAC*/
+ odm_set_bb_reg(dm, 0xb00, BIT(8), 0x0);
+ /*disable CCK block*/
+ odm_set_bb_reg(dm, 0x808, BIT(28), 0x0);
+ /*disable OFDM CCA*/
+ odm_set_bb_reg(dm, 0x838, BIT(3) | BIT(2) | BIT(1), 0x7);
+ /* PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]Set MACBB setting for IQK!!!!\n");*/
+
+}
+
+void
+_iqk_lok_setting_8822b(
+ struct dm_struct *dm,
+
+ u8 path
+)
+{
+ odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
+ odm_write_4byte(dm, 0x1bcc, 0x9);
+ odm_write_1byte(dm, 0x1b23, 0x00);
+
+ switch (*dm->band_type) {
+ case ODM_BAND_2_4G:
+ odm_write_1byte(dm, 0x1b2b, 0x00);
+ odm_set_rf_reg(dm, (enum rf_path)path, 0x56, RFREGOFFSETMASK, 0x50df2);
+ odm_set_rf_reg(dm, (enum rf_path)path, 0x8f, RFREGOFFSETMASK, 0xadc00);
+ /* WE_LUT_TX_LOK*/
+ odm_set_rf_reg(dm, (enum rf_path)path, 0xef, BIT(4), 0x1);
+ odm_set_rf_reg(dm, (enum rf_path)path, 0x33, BIT(1) | BIT(0), 0x0);
+ break;
+ case ODM_BAND_5G:
+ odm_write_1byte(dm, 0x1b2b, 0x80);
+ odm_set_rf_reg(dm, (enum rf_path)path, 0x56, RFREGOFFSETMASK, 0x5086c);
+ odm_set_rf_reg(dm, (enum rf_path)path, 0x8f, RFREGOFFSETMASK, 0xa9c00);
+ /* WE_LUT_TX_LOK*/
+ odm_set_rf_reg(dm, (enum rf_path)path, 0xef, BIT(4), 0x1);
+ odm_set_rf_reg(dm, (enum rf_path)path, 0x33, BIT(1) | BIT(0), 0x1);
+ break;
+ }
+ /* PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]Set LOK setting!!!!\n");*/
+}
+
+
+void
+_iqk_txk_setting_8822b(
+ struct dm_struct *dm,
+ u8 path
+)
+{
+ odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
+ odm_write_4byte(dm, 0x1bcc, 0x9);
+ odm_write_4byte(dm, 0x1b20, 0x01440008);
+
+ if (path == 0x0)
+ odm_write_4byte(dm, 0x1b00, 0xf800000a);
+ else
+ odm_write_4byte(dm, 0x1b00, 0xf8000008);
+ odm_write_4byte(dm, 0x1bcc, 0x3f);
+
+ switch (*dm->band_type) {
+ case ODM_BAND_2_4G:
+ odm_set_rf_reg(dm, (enum rf_path)path, 0x56, RFREGOFFSETMASK, 0x50df2);
+ odm_set_rf_reg(dm, (enum rf_path)path, 0x8f, RFREGOFFSETMASK, 0xadc00);
+ odm_write_1byte(dm, 0x1b2b, 0x00);
+ break;
+ case ODM_BAND_5G:
+ odm_set_rf_reg(dm, (enum rf_path)path, 0x56, RFREGOFFSETMASK, 0x500ef);
+ odm_set_rf_reg(dm, (enum rf_path)path, 0x8f, RFREGOFFSETMASK, 0xa9c00);
+ odm_write_1byte(dm, 0x1b2b, 0x80);
+ break;
+ }
+ /* PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]Set TXK setting!!!!\n");*/
+
+}
+
+
+void
+_iqk_rxk1_setting_8822b(
+ struct dm_struct *dm,
+ u8 path
+)
+{
+ odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
+
+ switch (*dm->band_type) {
+ case ODM_BAND_2_4G:
+ odm_write_1byte(dm, 0x1bcc, 0x9);
+ odm_write_1byte(dm, 0x1b2b, 0x00);
+ odm_write_4byte(dm, 0x1b20, 0x01450008);
+ odm_write_4byte(dm, 0x1b24, 0x01460c88);
+ odm_set_rf_reg(dm, (enum rf_path)path, 0x56, RFREGOFFSETMASK, 0x510e0);
+ odm_set_rf_reg(dm, (enum rf_path)path, 0x8f, RFREGOFFSETMASK, 0xacc00);
+ break;
+ case ODM_BAND_5G:
+ odm_write_1byte(dm, 0x1bcc, 0x09);
+ odm_write_1byte(dm, 0x1b2b, 0x80);
+ odm_write_4byte(dm, 0x1b20, 0x00850008);
+ odm_write_4byte(dm, 0x1b24, 0x00460048);
+ odm_set_rf_reg(dm, (enum rf_path)path, 0x56, RFREGOFFSETMASK, 0x510e0);
+ odm_set_rf_reg(dm, (enum rf_path)path, 0x8f, RFREGOFFSETMASK, 0xadc00);
+ break;
+ }
+ /*PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]Set RXK setting!!!!\n");*/
+
+}
+
+
+void
+_iqk_rxk2_setting_8822b(
+ struct dm_struct *dm,
+ u8 path,
+ boolean is_gs
+)
+{
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+
+ odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
+
+ switch (*dm->band_type) {
+ case ODM_BAND_2_4G:
+ if (is_gs)
+ iqk_info->tmp1bcc = 0x12;
+ odm_write_1byte(dm, 0x1bcc, iqk_info->tmp1bcc);
+ odm_write_1byte(dm, 0x1b2b, 0x00);
+ odm_write_4byte(dm, 0x1b20, 0x01450008);
+ odm_write_4byte(dm, 0x1b24, 0x01460848);
+ odm_set_rf_reg(dm, (enum rf_path)path, 0x56, RFREGOFFSETMASK, 0x510e0);
+ odm_set_rf_reg(dm, (enum rf_path)path, 0x8f, RFREGOFFSETMASK, 0xa9c00);
+ break;
+ case ODM_BAND_5G:
+ if (is_gs) {
+ if (path == RF_PATH_A)
+ iqk_info->tmp1bcc = 0x12;
+ else
+ iqk_info->tmp1bcc = 0x09;
+ }
+ odm_write_1byte(dm, 0x1bcc, iqk_info->tmp1bcc);
+ odm_write_1byte(dm, 0x1b2b, 0x80);
+ odm_write_4byte(dm, 0x1b20, 0x00850008);
+ odm_write_4byte(dm, 0x1b24, 0x00460848);
+ odm_set_rf_reg(dm, (enum rf_path)path, 0x56, RFREGOFFSETMASK, 0x51060);
+ odm_set_rf_reg(dm, (enum rf_path)path, 0x8f, RFREGOFFSETMASK, 0xa9c00);
+ break;
+ }
+ /* PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]Set RXK setting!!!!\n");*/
+
+}
+
+
+void
+halrf_iqk_set_rf0x8(
+ struct dm_struct *dm,
+ u8 path
+)
+{
+ u16 c = 0x0;
+
+ while (c < 30000) {
+ odm_set_rf_reg(dm, (enum rf_path)path, 0xef, RFREGOFFSETMASK, 0x0);
+ odm_set_rf_reg(dm, (enum rf_path)path, 0x8, RFREGOFFSETMASK, 0x0);
+ if (odm_get_rf_reg(dm, (enum rf_path)path, 0x8, RFREGOFFSETMASK) == 0x0)
+ break;
+ c++;
+ }
+}
+
+void
+halrf_iqk_check_if_reload(
+ struct dm_struct *dm
+)
+{
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+
+ iqk_info->is_reload = (boolean)odm_get_bb_reg(dm, 0x1bf0, BIT(16));
+}
+
+
+boolean
+_iqk_check_cal_8822b(
+ struct dm_struct *dm,
+ u8 path,
+ u8 cmd
+)
+{
+ boolean notready = true, fail = true;
+ u32 delay_count = 0x0;
+
+ while (notready) {
+ if (odm_get_rf_reg(dm, (enum rf_path)path, 0x8, RFREGOFFSETMASK) == 0x12345) {
+ if (cmd == 0x0)/*LOK*/
+ fail = false;
+ else
+ fail = (boolean) odm_get_bb_reg(dm, 0x1b08, BIT(26));
+ notready = false;
+ } else {
+ ODM_delay_ms(1);
+ delay_count++;
+ }
+
+ if (delay_count >= 50) {
+ fail = true;
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]IQK timeout!!!\n");
+ break;
+ }
+ }
+ halrf_iqk_set_rf0x8(dm, path);
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]delay count = 0x%x!!!\n", delay_count);
+ return fail;
+}
+
+
+boolean
+_iqk_rx_iqk_gain_search_fail_8822b(
+ struct dm_struct *dm,
+ u8 path,
+ u8 step
+)
+{
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+ boolean fail = true;
+ u32 IQK_CMD = 0x0, rf_reg0, tmp, bb_idx;
+ u8 IQMUX[4] = {0x9, 0x12, 0x1b, 0x24};
+ u8 idx;
+
+
+ if (step == RXIQK1) {
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]============ S%d RXIQK GainSearch ============\n", path);
+ IQK_CMD = 0xf8000208 | (1 << (path + 4));
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]S%d GS%d_Trigger = 0x%x\n", path, step, IQK_CMD);
+ odm_write_4byte(dm, 0x1b00, IQK_CMD);
+ odm_write_4byte(dm, 0x1b00, IQK_CMD + 0x1);
+ ODM_delay_ms(GS_delay_8822B);
+ fail = _iqk_check_cal_8822b(dm, path, 0x1);
+ } else if (step == RXIQK2) {
+ for (idx = 0; idx < 4; idx++) {
+ if (iqk_info->tmp1bcc == IQMUX[idx])
+ break;
+ }
+ odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
+ odm_write_4byte(dm, 0x1bcc, iqk_info->tmp1bcc);
+
+ IQK_CMD = 0xf8000308 | (1 << (path + 4));
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]S%d GS%d_Trigger = 0x%x\n", path, step, IQK_CMD);
+ odm_write_4byte(dm, 0x1b00, IQK_CMD);
+ odm_write_4byte(dm, 0x1b00, IQK_CMD + 0x1);
+ ODM_delay_ms(GS_delay_8822B);
+ fail = _iqk_check_cal_8822b(dm, path, 0x1);
+
+ rf_reg0 = odm_get_rf_reg(dm, (enum rf_path)path, 0x0, RFREGOFFSETMASK);
+ odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]S%d ==> RF0x0 = 0x%x, tmp1bcc = 0x%x, idx = %d, 0x1b3c = 0x%x\n", path, rf_reg0, iqk_info->tmp1bcc, idx, odm_read_4byte(dm, 0x1b3c));
+ tmp = (rf_reg0 & 0x1fe0) >> 5;
+ iqk_info->lna_idx = tmp >> 5;
+ bb_idx = tmp & 0x1f;
+
+ if (bb_idx == 0x1) {
+ if (iqk_info->lna_idx != 0x0)
+ iqk_info->lna_idx--;
+ else if (idx != 3)
+ idx++;
+ else
+ iqk_info->isbnd = true;
+ fail = true;
+ } else if (bb_idx == 0xa) {
+ if (idx != 0)
+ idx--;
+ else if (iqk_info->lna_idx != 0x7)
+ iqk_info->lna_idx++;
+ else
+ iqk_info->isbnd = true;
+ fail = true;
+ } else
+ fail = false;
+
+ if (iqk_info->isbnd == true)
+ fail = false;
+
+ iqk_info->tmp1bcc = IQMUX[idx];
+
+ if (fail) {
+ odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
+ odm_write_4byte(dm, 0x1b24, (odm_read_4byte(dm, 0x1b24) & 0xffffe3ff) | (iqk_info->lna_idx << 10));
+ }
+ }
+ return fail;
+}
+
+boolean
+_lok_one_shot_8822b(
+ void *dm_void,
+ u8 path
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+ u8 delay_count = 0;
+ boolean LOK_notready = false;
+ u32 LOK_temp = 0;
+ u32 IQK_CMD = 0x0;
+
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]==========S%d LOK ==========\n", path);
+ IQK_CMD = 0xf8000008 | (1 << (4 + path));
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]LOK_Trigger = 0x%x\n", IQK_CMD);
+ odm_write_4byte(dm, 0x1b00, IQK_CMD);
+ odm_write_4byte(dm, 0x1b00, IQK_CMD + 1);
+ /*LOK: CMD ID = 0 {0xf8000018, 0xf8000028}*/
+ /*LOK: CMD ID = 0 {0xf8000019, 0xf8000029}*/
+ ODM_delay_ms(LOK_delay_8822B);
+ LOK_notready = _iqk_check_cal_8822b(dm, path, 0x0);
+ if (!LOK_notready)
+ _iqk_backup_iqk_8822b(dm, 0x1, path);
+ if (ODM_COMP_CALIBRATION) {
+ if (!LOK_notready) {
+ LOK_temp = odm_get_rf_reg(dm, (enum rf_path)path, 0x58, RFREGOFFSETMASK);
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]0x58 = 0x%x\n", LOK_temp);
+ } else
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]==>S%d LOK Fail!!!\n", path);
+ }
+ iqk_info->lok_fail[path] = LOK_notready;
+ return LOK_notready;
+}
+
+
+
+
+boolean
+_iqk_one_shot_8822b(
+ void *dm_void,
+ u8 path,
+ u8 idx
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+ u8 delay_count = 0;
+ boolean notready = true, fail = true;
+ u32 IQK_CMD = 0x0;
+ u16 iqk_apply[2] = {0xc94, 0xe94};
+
+ if (idx == TXIQK)
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]============ S%d WBTXIQK ============\n", path);
+ else if (idx == RXIQK1)
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]============ S%d WBRXIQK STEP1============\n", path);
+ else
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]============ S%d WBRXIQK STEP2============\n", path);
+
+ if (idx == TXIQK) {
+ IQK_CMD = 0xf8000008 | ((*dm->band_width + 4) << 8) | (1 << (path + 4));
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]TXK_Trigger = 0x%x\n", IQK_CMD);
+ /*{0xf8000418, 0xf800042a} ==> 20 WBTXK (CMD = 4)*/
+ /*{0xf8000518, 0xf800052a} ==> 40 WBTXK (CMD = 5)*/
+ /*{0xf8000618, 0xf800062a} ==> 80 WBTXK (CMD = 6)*/
+ } else if (idx == RXIQK1) {
+ if (*dm->band_width == 2)
+ IQK_CMD = 0xf8000808 | (1 << (path + 4));
+ else
+ IQK_CMD = 0xf8000708 | (1 << (path + 4));
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]RXK1_Trigger = 0x%x\n", IQK_CMD);
+ /*{0xf8000718, 0xf800072a} ==> 20 WBTXK (CMD = 7)*/
+ /*{0xf8000718, 0xf800072a} ==> 40 WBTXK (CMD = 7)*/
+ /*{0xf8000818, 0xf800082a} ==> 80 WBTXK (CMD = 8)*/
+ } else if (idx == RXIQK2) {
+ IQK_CMD = 0xf8000008 | ((*dm->band_width + 9) << 8) | (1 << (path + 4));
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]RXK2_Trigger = 0x%x\n", IQK_CMD);
+ /*{0xf8000918, 0xf800092a} ==> 20 WBRXK (CMD = 9)*/
+ /*{0xf8000a18, 0xf8000a2a} ==> 40 WBRXK (CMD = 10)*/
+ /*{0xf8000b18, 0xf8000b2a} ==> 80 WBRXK (CMD = 11)*/
+ odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
+ odm_write_4byte(dm, 0x1b24, (odm_read_4byte(dm, 0x1b24) & 0xffffe3ff) | ((iqk_info->lna_idx & 0x7) << 10));
+ }
+ odm_write_4byte(dm, 0x1b00, IQK_CMD);
+ odm_write_4byte(dm, 0x1b00, IQK_CMD + 0x1);
+ ODM_delay_ms(WBIQK_delay_8822B);
+ fail = _iqk_check_cal_8822b(dm, path, 0x1);
+
+ if (dm->debug_components & ODM_COMP_CALIBRATION) {
+ odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]S%d ==> 0x1b00 = 0x%x, 0x1b08 = 0x%x\n", path, odm_read_4byte(dm, 0x1b00), odm_read_4byte(dm, 0x1b08));
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]S%d ==> delay_count = 0x%x\n", path, delay_count);
+ if (idx != TXIQK)
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]S%d ==> RF0x0 = 0x%x, RF0x56 = 0x%x\n", path, odm_get_rf_reg(dm, (enum rf_path)path, 0x0, RFREGOFFSETMASK),
+ odm_get_rf_reg(dm, (enum rf_path)path, 0x56, RFREGOFFSETMASK));
+ }
+
+ odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
+
+ if (idx == TXIQK) {
+ if (fail)
+ odm_set_bb_reg(dm, iqk_apply[path], BIT(0), 0x0);
+ else
+ _iqk_backup_iqk_8822b(dm, 0x2, path);
+ }
+
+ if (idx == RXIQK2) {
+ iqk_info->rxiqk_agc[0][path] =
+ (u16)(((odm_get_rf_reg(dm, (enum rf_path)path, 0x0, RFREGOFFSETMASK) >> 5) & 0xff) |
+ (iqk_info->tmp1bcc << 8));
+
+ odm_write_4byte(dm, 0x1b38, 0x20000000);
+
+ if (fail)
+ odm_set_bb_reg(dm, iqk_apply[path], (BIT(11) | BIT(10)), 0x0);
+ else
+ _iqk_backup_iqk_8822b(dm, 0x3, path);
+ }
+
+ if (idx == TXIQK)
+ iqk_info->iqk_fail_report[0][path][TXIQK] = fail;
+ else
+ iqk_info->iqk_fail_report[0][path][RXIQK] = fail;
+
+ return fail;
+}
+
+
+boolean
+_iqk_rx_iqk_by_path_8822b(
+ void *dm_void,
+ u8 path
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+ boolean KFAIL = true, gonext;
+
+#if 1
+ switch (iqk_info->rxiqk_step) {
+ case 1: /*gain search_RXK1*/
+ _iqk_rxk1_setting_8822b(dm, path);
+ gonext = false;
+ while (1) {
+ KFAIL = _iqk_rx_iqk_gain_search_fail_8822b(dm, path, RXIQK1);
+ if (KFAIL && (iqk_info->gs_retry_count[0][path][0] < 2))
+ iqk_info->gs_retry_count[0][path][0]++;
+ else if (KFAIL) {
+ iqk_info->rxiqk_fail_code[0][path] = 0;
+ iqk_info->rxiqk_step = 5;
+ gonext = true;
+ } else {
+ iqk_info->rxiqk_step++;
+ gonext = true;
+ }
+ if (gonext)
+ break;
+ }
+ halrf_iqk_xym_read(dm, path, 0x2);
+ break;
+ case 2: /*gain search_RXK2*/
+ _iqk_rxk2_setting_8822b(dm, path, true);
+ iqk_info->isbnd = false;
+ while (1) {
+ KFAIL = _iqk_rx_iqk_gain_search_fail_8822b(dm, path, RXIQK2);
+ if (KFAIL && (iqk_info->gs_retry_count[0][path][1] < rxiqk_gs_limit))
+ iqk_info->gs_retry_count[0][path][1]++;
+ else {
+ iqk_info->rxiqk_step++;
+ break;
+ }
+ }
+ halrf_iqk_xym_read(dm, path, 0x3);
+ break;
+ case 3: /*RXK1*/
+ _iqk_rxk1_setting_8822b(dm, path);
+ gonext = false;
+ while (1) {
+ KFAIL = _iqk_one_shot_8822b(dm, path, RXIQK1);
+ if (KFAIL && (iqk_info->retry_count[0][path][RXIQK1] < 2))
+ iqk_info->retry_count[0][path][RXIQK1]++;
+ else if (KFAIL) {
+ iqk_info->rxiqk_fail_code[0][path] = 1;
+ iqk_info->rxiqk_step = 5;
+ gonext = true;
+ } else {
+ iqk_info->rxiqk_step++;
+ gonext = true;
+ }
+ if (gonext)
+ break;
+ }
+ halrf_iqk_xym_read(dm, path, 0x4);
+ break;
+ case 4: /*RXK2*/
+ _iqk_rxk2_setting_8822b(dm, path, false);
+ gonext = false;
+ while (1) {
+ KFAIL = _iqk_one_shot_8822b(dm, path, RXIQK2);
+ if (KFAIL && (iqk_info->retry_count[0][path][RXIQK2] < 2))
+ iqk_info->retry_count[0][path][RXIQK2]++;
+ else if (KFAIL) {
+ iqk_info->rxiqk_fail_code[0][path] = 2;
+ iqk_info->rxiqk_step = 5;
+ gonext = true;
+ } else {
+ iqk_info->rxiqk_step++;
+ gonext = true;
+ }
+ if (gonext)
+ break;
+ }
+ halrf_iqk_xym_read(dm, path, 0x0);
+ break;
+ }
+ return KFAIL;
+#endif
+}
+
+
+void
+_iqk_iqk_by_path_8822b(
+ void *dm_void,
+ boolean segment_iqk
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+ boolean KFAIL = true;
+ u8 i, kcount_limit;
+
+ /* PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]iqk_step = 0x%x\n", dm->rf_calibrate_info.iqk_step); */
+
+ if (*dm->band_width == 2)
+ kcount_limit = kcount_limit_80m;
+ else
+ kcount_limit = kcount_limit_others;
+
+ while (1) {
+#if 1
+ switch (dm->rf_calibrate_info.iqk_step) {
+ case 1: /*S0 LOK*/
+#if 1
+ _iqk_lok_setting_8822b(dm, RF_PATH_A);
+ _lok_one_shot_8822b(dm, RF_PATH_A);
+#endif
+ dm->rf_calibrate_info.iqk_step++;
+ break;
+ case 2: /*S1 LOK*/
+#if 1
+ _iqk_lok_setting_8822b(dm, RF_PATH_B);
+ _lok_one_shot_8822b(dm, RF_PATH_B);
+#endif
+ dm->rf_calibrate_info.iqk_step++;
+ break;
+ case 3: /*S0 TXIQK*/
+#if 1
+ _iqk_txk_setting_8822b(dm, RF_PATH_A);
+ KFAIL = _iqk_one_shot_8822b(dm, RF_PATH_A, TXIQK);
+ iqk_info->kcount++;
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]S0TXK KFail = 0x%x\n", KFAIL);
+
+ if (KFAIL && (iqk_info->retry_count[0][RF_PATH_A][TXIQK] < 3))
+ iqk_info->retry_count[0][RF_PATH_A][TXIQK]++;
+ else
+#endif
+ dm->rf_calibrate_info.iqk_step++;
+ halrf_iqk_xym_read(dm, RF_PATH_A, 0x1);
+ break;
+ case 4: /*S1 TXIQK*/
+#if 1
+ _iqk_txk_setting_8822b(dm, RF_PATH_B);
+ KFAIL = _iqk_one_shot_8822b(dm, RF_PATH_B, TXIQK);
+ iqk_info->kcount++;
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]S1TXK KFail = 0x%x\n", KFAIL);
+ if (KFAIL && iqk_info->retry_count[0][RF_PATH_B][TXIQK] < 3)
+ iqk_info->retry_count[0][RF_PATH_B][TXIQK]++;
+ else
+#endif
+ dm->rf_calibrate_info.iqk_step++;
+ halrf_iqk_xym_read(dm, RF_PATH_B, 0x1);
+ break;
+ case 5: /*S0 RXIQK*/
+ while (1) {
+ KFAIL = _iqk_rx_iqk_by_path_8822b(dm, RF_PATH_A);
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]S0RXK KFail = 0x%x\n", KFAIL);
+ if (iqk_info->rxiqk_step == 5) {
+ dm->rf_calibrate_info.iqk_step++;
+ iqk_info->rxiqk_step = 1;
+ if (KFAIL)
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]S0RXK fail code: %d!!!\n", iqk_info->rxiqk_fail_code[0][RF_PATH_A]);
+ break;
+ }
+ }
+ iqk_info->kcount++;
+ break;
+ case 6: /*S1 RXIQK*/
+ while (1) {
+ KFAIL = _iqk_rx_iqk_by_path_8822b(dm, RF_PATH_B);
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]S1RXK KFail = 0x%x\n", KFAIL);
+ if (iqk_info->rxiqk_step == 5) {
+ dm->rf_calibrate_info.iqk_step++;
+ iqk_info->rxiqk_step = 1;
+ if (KFAIL)
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]S1RXK fail code: %d!!!\n", iqk_info->rxiqk_fail_code[0][RF_PATH_B]);
+ break;
+ }
+ }
+ iqk_info->kcount++;
+ break;
+ }
+
+ if (dm->rf_calibrate_info.iqk_step == 7) {
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]==========LOK summary ==========\n");
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]PathA_LOK_notready = %d, PathB_LOK1_notready = %d\n",
+ iqk_info->lok_fail[RF_PATH_A], iqk_info->lok_fail[RF_PATH_B]);
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]==========IQK summary ==========\n");
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]PathA_TXIQK_fail = %d, PathB_TXIQK_fail = %d\n",
+ iqk_info->iqk_fail_report[0][RF_PATH_A][TXIQK], iqk_info->iqk_fail_report[0][RF_PATH_B][TXIQK]);
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]PathA_RXIQK_fail = %d, PathB_RXIQK_fail = %d\n",
+ iqk_info->iqk_fail_report[0][RF_PATH_A][RXIQK], iqk_info->iqk_fail_report[0][RF_PATH_B][RXIQK]);
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]PathA_TXIQK_retry = %d, PathB_TXIQK_retry = %d\n",
+ iqk_info->retry_count[0][RF_PATH_A][TXIQK], iqk_info->retry_count[0][RF_PATH_B][TXIQK]);
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]PathA_RXK1_retry = %d, PathA_RXK2_retry = %d, PathB_RXK1_retry = %d, PathB_RXK2_retry = %d\n",
+ iqk_info->retry_count[0][RF_PATH_A][RXIQK1], iqk_info->retry_count[0][RF_PATH_A][RXIQK2],
+ iqk_info->retry_count[0][RF_PATH_B][RXIQK1], iqk_info->retry_count[0][RF_PATH_B][RXIQK2]);
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]PathA_GS1_retry = %d, PathA_GS2_retry = %d, PathB_GS1_retry = %d, PathB_GS2_retry = %d\n",
+ iqk_info->gs_retry_count[0][RF_PATH_A][0], iqk_info->gs_retry_count[0][RF_PATH_A][1],
+ iqk_info->gs_retry_count[0][RF_PATH_B][0], iqk_info->gs_retry_count[0][RF_PATH_B][1]);
+ for (i = 0; i < 2; i++) {
+ odm_write_4byte(dm, 0x1b00, 0xf8000008 | i << 1);
+ odm_write_4byte(dm, 0x1b2c, 0x7);
+ odm_write_4byte(dm, 0x1bcc, 0x0);
+ odm_write_4byte(dm, 0x1b38, 0x20000000);
+ }
+ break;
+ }
+
+ if (segment_iqk && (iqk_info->kcount == kcount_limit))
+ break;
+#endif
+}
+}
+
+void
+_iqk_start_iqk_8822b(
+ struct dm_struct *dm,
+ boolean segment_iqk
+)
+{
+ u32 tmp;
+
+ /*GNT_WL = 1*/
+ tmp = odm_get_rf_reg(dm, RF_PATH_A, 0x1, RFREGOFFSETMASK);
+ tmp = tmp | BIT(5) | BIT(0);
+ odm_set_rf_reg(dm, RF_PATH_A, 0x1, RFREGOFFSETMASK, tmp);
+
+ tmp = odm_get_rf_reg(dm, RF_PATH_B, 0x1, RFREGOFFSETMASK);
+ tmp = tmp | BIT(5) | BIT(0);
+ odm_set_rf_reg(dm, RF_PATH_B, 0x1, RFREGOFFSETMASK, tmp);
+
+ _iqk_iqk_by_path_8822b(dm, segment_iqk);
+
+
+}
+
+void
+_iq_calibrate_8822b_init(
+ struct dm_struct *dm
+)
+{
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+ u8 i, j, k, m;
+ static boolean firstrun = true;
+
+ if (firstrun) {
+ firstrun = false;
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]=====>PHY_IQCalibrate_8822B_Init\n");
+
+ for (i = 0; i < SS_8822B; i++) {
+ for (j = 0; j < 2; j++) {
+ iqk_info->lok_fail[i] = true;
+ iqk_info->iqk_fail[j][i] = true;
+ iqk_info->iqc_matrix[j][i] = 0x20000000;
+ }
+ }
+
+ for (i = 0; i < 2; i++) {
+ iqk_info->iqk_channel[i] = 0x0;
+
+ for (j = 0; j < SS_8822B; j++) {
+ iqk_info->lok_idac[i][j] = 0x0;
+ iqk_info->rxiqk_agc[i][j] = 0x0;
+ iqk_info->bypass_iqk[i][j] = 0x0;
+
+ for (k = 0; k < 2; k++) {
+ iqk_info->iqk_fail_report[i][j][k] = true;
+ for (m = 0; m < 8; m++) {
+ iqk_info->iqk_cfir_real[i][j][k][m] = 0x0;
+ iqk_info->iqk_cfir_imag[i][j][k][m] = 0x0;
+ }
+ }
+
+ for (k = 0; k < 3; k++)
+ iqk_info->retry_count[i][j][k] = 0x0;
+
+ }
+ }
+ }
+ /*parameters init.*/
+ /*cu_distance (IQK result variation)=111*/
+ odm_write_4byte(dm, 0x1b10, 0x88011c00);
+}
+
+
+
+boolean
+_iqk_rximr_rxk1_test_8822b(
+ struct dm_struct *dm,
+ u8 path,
+ u32 tone_index
+)
+{
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+ boolean fail = true;
+ u32 IQK_CMD ;
+
+ odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
+ odm_write_4byte(dm, 0x1b20, (odm_read_4byte(dm, 0x1b20) & 0x000fffff) | ((tone_index & 0xfff)<<20));
+ odm_write_4byte(dm, 0x1b24, (odm_read_4byte(dm, 0x1b24) & 0x000fffff) | ((tone_index & 0xfff)<<20));
+
+ IQK_CMD = 0xf8000208 | (1 << (path + 4));
+ odm_write_4byte(dm, 0x1b00, IQK_CMD);
+ odm_write_4byte(dm, 0x1b00, IQK_CMD + 0x1);
+
+ ODM_delay_ms(GS_delay_8822B);
+ fail = _iqk_check_cal_8822b(dm, path, 0x1);
+ return fail;
+}
+
+u32
+_iqk_tximr_selfcheck_8822b(
+ void *dm_void,
+ u8 tone_index,
+ u8 path
+)
+{
+ u32 tx_ini_power_H[2], tx_ini_power_L[2];
+ u32 tmp1, tmp2, tmp3, tmp4, tmp5;
+ u32 IQK_CMD;
+ u32 tximr = 0x0;
+ u8 i;
+
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+/*backup*/
+ odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
+ odm_write_4byte(dm, 0x1bc8, 0x80000000);
+ odm_write_4byte(dm, 0x8f8, 0x41400080);
+ tmp1 = odm_read_4byte(dm, 0x1b0c);
+ tmp2 = odm_read_4byte(dm, 0x1b14);
+ tmp3 = odm_read_4byte(dm, 0x1b1c);
+ tmp4 = odm_read_4byte(dm, 0x1b20);
+ tmp5 = odm_read_4byte(dm, 0x1b24);
+/*setup*/
+ odm_write_4byte(dm, 0x1b0c, 0x00003000);
+ odm_write_4byte(dm, 0x1b1c, 0xA2193C32);
+ odm_write_1byte(dm, 0x1b15, 0x00);
+ odm_write_4byte(dm, 0x1b20, (u32)(tone_index << 20 | 0x00040008));
+ odm_write_4byte(dm, 0x1b24, (u32)(tone_index << 20 | 0x00060008));
+ odm_write_4byte(dm, 0x1b2c, 0x07);
+ odm_write_4byte(dm, 0x1b38, 0x20000000);
+ odm_write_4byte(dm, 0x1b3c, 0x20000000);
+/* ======derive pwr1========*/
+ for (i = 0; i < 2; i++) {
+ odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
+ if (i == 0)
+ odm_write_4byte(dm, 0x1bcc, 0x0f);
+ else
+ odm_write_4byte(dm, 0x1bcc, 0x09);
+/* One Shot*/
+ IQK_CMD = 0x00000800;
+ odm_write_4byte(dm, 0x1b34, IQK_CMD+1);
+ odm_write_4byte(dm, 0x1b34, IQK_CMD);
+ ODM_delay_ms(1);
+ odm_write_4byte(dm, 0x1bd4, 0x00040001);
+ tx_ini_power_H[i] = odm_read_4byte(dm, 0x1bfc);
+ odm_write_4byte(dm, 0x1bd4, 0x000C0001);
+ tx_ini_power_L[i] = odm_read_4byte(dm, 0x1bfc);
+ }
+/*restore*/
+ odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
+ odm_write_4byte(dm, 0x1b0c, tmp1);
+ odm_write_4byte(dm, 0x1b14, tmp2);
+ odm_write_4byte(dm, 0x1b1c, tmp3);
+ odm_write_4byte(dm, 0x1b20, tmp4);
+ odm_write_4byte(dm, 0x1b24, tmp5);
+
+ if (tx_ini_power_H[1] == tx_ini_power_H[0])
+ tximr = (3*(halrf_psd_log2base(tx_ini_power_L[0] << 2) - halrf_psd_log2base(tx_ini_power_L[1])))/100;
+ else
+ tximr = 0;
+ return tximr;
+}
+
+void
+_iqk_start_tximr_test_8822b(
+ struct dm_struct *dm,
+ u8 imr_limit
+ )
+{
+ boolean KFAIL;
+ u8 path, i, tone_index;
+ u32 imr_result;
+
+ for (path = 0; path < 2; path++) {
+ _iqk_txk_setting_8822b(dm, path);
+ KFAIL = _iqk_one_shot_8822b(dm, path, TXIQK);
+ for (i = 0x0; i < imr_limit; i++) {
+ tone_index = (u8)(0x08|i<<4);
+ imr_result = _iqk_tximr_selfcheck_8822b(dm, tone_index, path);
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]path=%x, toneindex = %x, TXIMR = %d\n", path, tone_index, imr_result);
+ }
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "\n");
+ }
+}
+
+u32
+_iqk_rximr_selfcheck_8822b(
+ void *dm_void,
+ u32 tone_index,
+ u8 path,
+ u32 tmp1b38
+)
+{
+ u32 rx_ini_power_H[2], rx_ini_power_L[2];/*[0]: psd tone; [1]: image tone*/
+ u32 tmp1, tmp2, tmp3, tmp4, tmp5;
+ u32 IQK_CMD, tmp1bcc;
+ u8 i, num_k1, rximr_step, count = 0x0;
+ u32 rximr = 0x0;
+ boolean KFAIL = true;
+
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+
+ /*backup*/
+ odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
+ tmp1 = odm_read_4byte(dm, 0x1b0c);
+ tmp2 = odm_read_4byte(dm, 0x1b14);
+ tmp3 = odm_read_4byte(dm, 0x1b1c);
+ tmp4 = odm_read_4byte(dm, 0x1b20);
+ tmp5 = odm_read_4byte(dm, 0x1b24);
+
+ odm_write_4byte(dm, 0x1b0c, 0x00001000);
+ odm_write_1byte(dm, 0x1b15, 0x00);
+ odm_write_4byte(dm, 0x1b1c, 0x82193d31);
+ odm_write_4byte(dm, 0x1b20, (u32)(tone_index << 20 | 0x00040008));
+ odm_write_4byte(dm, 0x1b24, (u32)(tone_index << 20 | 0x00060048));
+ odm_write_4byte(dm, 0x1b2c, 0x07);
+ odm_write_4byte(dm, 0x1b38, tmp1b38);
+ odm_write_4byte(dm, 0x1b3c, 0x20000000);
+
+ for (i = 0; i < 2; i++) {
+ if (i == 0)
+ odm_write_4byte(dm, 0x1b1c, 0x82193d31);
+ else
+ odm_write_4byte(dm, 0x1b1c, 0xa2193d31);
+ IQK_CMD = 0x00000800;
+ odm_write_4byte(dm, 0x1b34, IQK_CMD + 1);
+ odm_write_4byte(dm, 0x1b34, IQK_CMD);
+ ODM_delay_ms(2);
+ odm_write_1byte(dm, 0x1bd6, 0xb);
+ while (count < 100) {
+ count++;
+ if(odm_get_bb_reg(dm, 0x1bfc, BIT(1)) == 1)
+ break;
+ else
+ ODM_delay_ms(1);
+ }
+ if (1) {
+ odm_write_1byte(dm, 0x1bd6, 0x5);
+ rx_ini_power_H[i] = odm_read_4byte(dm, 0x1bfc);
+ odm_write_1byte(dm, 0x1bd6, 0xe);
+ rx_ini_power_L[i] = odm_read_4byte(dm, 0x1bfc);
+ } else {
+ rx_ini_power_H[i] = 0x0;
+ rx_ini_power_L[i] = 0x0;
+ }
+
+ }
+ /*restore*/
+ odm_write_4byte(dm, 0x1b0c, tmp1);
+ odm_write_4byte(dm, 0x1b14, tmp2);
+ odm_write_4byte(dm, 0x1b1c, tmp3);
+ odm_write_4byte(dm, 0x1b20, tmp4);
+ odm_write_4byte(dm, 0x1b24, tmp5);
+ for (i = 0 ; i < 2; i++)
+ rx_ini_power_H[i] = (rx_ini_power_H[i] & 0xf8000000)>>27;
+
+ if (rx_ini_power_H[0] != rx_ini_power_H[1]) {
+ switch (rx_ini_power_H[0]) {
+ case 1:
+ rx_ini_power_L[0] = (u32)((rx_ini_power_L[0]>>1) | 0x80000000);
+ rx_ini_power_L[1] = (u32)rx_ini_power_L[1]>>1;
+ break;
+ case 2:
+ rx_ini_power_L[0] = (u32)((rx_ini_power_L[0]>>2) | 0x80000000);
+ rx_ini_power_L[1] = (u32)rx_ini_power_L[1]>>2;
+ break;
+ case 3:
+ rx_ini_power_L[0] = (u32)((rx_ini_power_L[0]>>2) | 0xc0000000);
+ rx_ini_power_L[1] = (u32)rx_ini_power_L[1]>>2;
+ break;
+ case 4:
+ rx_ini_power_L[0] = (u32)((rx_ini_power_L[0]>>3) | 0x80000000);
+ rx_ini_power_L[1] = (u32)rx_ini_power_L[1]>>3;
+ break;
+ case 5:
+ rx_ini_power_L[0] = (u32)((rx_ini_power_L[0]>>3) | 0xa0000000);
+ rx_ini_power_L[1] = (u32)rx_ini_power_L[1]>>3;
+ break;
+ case 6:
+ rx_ini_power_L[0] = (u32)((rx_ini_power_L[0]>>3) | 0xc0000000);
+ rx_ini_power_L[1] = (u32)rx_ini_power_L[1]>>3;
+ break;
+ case 7:
+ rx_ini_power_L[0] = (u32)((rx_ini_power_L[0]>>3) | 0xe0000000);
+ rx_ini_power_L[1] = (u32)rx_ini_power_L[1]>>3;
+ break;
+ default:
+ break;
+ }
+ }
+ rximr = (u32)(3*((halrf_psd_log2base(rx_ini_power_L[0]/100) - halrf_psd_log2base(rx_ini_power_L[1]/100)))/100);
+ return rximr;
+}
+
+
+void
+_iqk_rximr_test_8822b(
+ struct dm_struct *dm,
+ u8 path,
+ u8 imr_limit
+ )
+{
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+ boolean kfail;
+ u8 i, step, count, side;
+ u32 imr_result = 0, tone_index;
+ u32 temp = 0, temp1b38[2][15];
+ char *freq[15]= {"1.25MHz", "3.75MHz", "6.25MHz", "8.75MHz", "11.25MHz",
+ "13.75MHz", "16.25MHz", "18.75MHz", "21.25MHz", "23.75MHz",
+ "26.25MHz", "28.75MHz", "31.25MHz", "33.75MHz", "36.25MHz"};
+
+ for (step = 1; step < 5; step++) {
+ count = 0;
+ switch (step) {
+ case 1: /*gain search_RXK1*/
+ _iqk_rxk1_setting_8822b(dm, path);
+ while (count < 3) {
+ kfail = _iqk_rx_iqk_gain_search_fail_8822b(dm, path, RXIQK1);
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]path = %x, kfail = %x\n", path, kfail);
+ if (kfail) {
+ count++;
+ if (count == 3)
+ step = 5;
+ } else {
+ break;
+ }
+ }
+ break;
+ case 2: /*gain search_RXK2*/
+ _iqk_rxk2_setting_8822b(dm, path, true);
+ iqk_info->isbnd = false;
+ while (count < 8) {
+ kfail = _iqk_rx_iqk_gain_search_fail_8822b(dm, path, RXIQK2);
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]path = %x, kfail = %x\n", path, kfail);
+ if (kfail) {
+ count++;
+ if (count == 8)
+ step = 5;
+ } else {
+ break;
+ }
+ }
+ break;
+ case 3: /*get RXK1 IQC*/
+ odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
+ temp = odm_read_4byte(dm, 0x1b1c);
+ for (side =0; side < 2; side++) {
+ for (i = 0; i < imr_limit; i++) {
+ if (side ==0)
+ tone_index = 0xff8 -(i<<4);
+ else
+ tone_index = 0x08 | (i<<4);
+ while (count < 3) {
+ _iqk_rxk1_setting_8822b(dm, path);
+ kfail = _iqk_rximr_rxk1_test_8822b(dm, path, tone_index);
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]path = %x, kfail = %x\n", path, kfail);
+ if (kfail) {
+ count++;
+ if (count == 3) {
+ step = 5;
+ temp1b38[side][i] = 0x20000000;
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]path = %x, toneindex = %x rxk1 fail\n", path, tone_index);
+ }
+ } else {
+ odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
+ odm_write_4byte(dm, 0x1b1c, 0xa2193c32);
+ odm_write_4byte(dm, 0x1b14, 0xe5);
+ odm_write_4byte(dm, 0x1b14, 0x0);
+ temp1b38[side][i] = odm_read_4byte(dm, 0x1b38);
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]path = 0x%x, tone_idx = 0x%x, tmp1b38 = 0x%x\n", path, tone_index, temp1b38[side][i]);
+ break;
+ }
+ }
+ }
+ }
+ break;
+ case 4: /*get RX IMR*/
+ for (side =0; side < 2; side++) {
+ for (i = 0x0; i < imr_limit; i++) {
+ if (side ==0)
+ tone_index = 0xff8 -(i<<4);
+ else
+ tone_index = 0x08 | (i<<4);
+ _iqk_rxk2_setting_8822b(dm, path, false);
+ imr_result = _iqk_rximr_selfcheck_8822b(dm, tone_index, path, temp1b38[side][i]);
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]tone_idx = 0x%5x, freq = %s%10s, RXIMR = %5d dB\n", tone_index, (side ==0)?"-":" ", freq[i], imr_result);
+ }
+ odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
+ odm_write_4byte(dm, 0x1b1c, temp);
+ odm_write_4byte(dm, 0x1b38, 0x20000000);
+ }
+ break;
+ }
+ }
+}
+
+
+void
+_iqk_start_rximr_test_8822b(
+ struct dm_struct *dm,
+ u8 imr_limit
+ )
+{
+ u8 path;
+
+ for (path = 0; path < 2; path++)
+ _iqk_rximr_test_8822b(dm, path, imr_limit);
+}
+
+void
+_iqk_start_imr_test_8822b(
+ void *dm_void
+ )
+{
+ u8 imr_limit;
+
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+
+ if (*dm->band_width == 2)
+ imr_limit = 0xf;
+ else if (*dm->band_width == 1)
+ imr_limit = 0x8;
+ else
+ imr_limit = 0x4;
+// _iqk_start_tximr_test_8822b(dm, imr_limit);
+ _iqk_start_rximr_test_8822b(dm, imr_limit);
+}
+
+
+void
+_phy_iq_calibrate_8822b(
+ struct dm_struct *dm,
+ boolean reset,
+ boolean segment_iqk
+)
+{
+ u32 MAC_backup[MAC_REG_NUM_8822B], BB_backup[BB_REG_NUM_8822B], RF_backup[RF_REG_NUM_8822B][SS_8822B];
+ u32 backup_mac_reg[MAC_REG_NUM_8822B] = {0x520, 0x550};
+ u32 backup_bb_reg[BB_REG_NUM_8822B] = {0x808, 0x90c, 0xc00, 0xcb0, 0xcb4, 0xcbc, 0xe00, 0xeb0, 0xeb4, 0xebc, 0x1990, 0x9a4, 0xa04, 0xb00, 0x838};
+ u32 backup_rf_reg[RF_REG_NUM_8822B] = {0xdf, 0x8f, 0x65, 0x0, 0x1};
+ boolean is_mp = false;
+
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+
+ if (*dm->mp_mode)
+ is_mp = true;
+
+ if (!is_mp)
+ if (_iqk_reload_iqk_8822b(dm, reset))
+ return;
+
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]==========IQK strat!!!!!==========\n");
+
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]band_type = %s, band_width = %d, ExtPA2G = %d, ext_pa_5g = %d\n", (*dm->band_type == ODM_BAND_5G) ? "5G" : "2G", *dm->band_width, dm->ext_pa, dm->ext_pa_5g);
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK]Interface = %d, cut_version = %x\n", dm->support_interface, dm->cut_version);
+
+ iqk_info->iqk_times++;
+ iqk_info->kcount = 0;
+ dm->rf_calibrate_info.iqk_step = 1;
+ iqk_info->rxiqk_step = 1;
+
+ _iqk_backup_iqk_8822b(dm, 0x0, 0x0);
+ _iqk_backup_mac_bb_8822b(dm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg);
+ _iqk_backup_rf_8822b(dm, RF_backup, backup_rf_reg);
+#if 0
+ _iqk_configure_macbb_8822b(dm);
+ _iqk_afe_setting_8822b(dm, true);
+ _iqk_rfe_setting_8822b(dm, false);
+ _iqk_agc_bnd_int_8822b(dm);
+ _iqk_rf_setting_8822b(dm);
+#endif
+
+ while (1) {
+ _iqk_configure_macbb_8822b(dm);
+ _iqk_afe_setting_8822b(dm, true);
+ _iqk_rfe_setting_8822b(dm, false);
+ _iqk_agc_bnd_int_8822b(dm);
+ _iqk_rf_setting_8822b(dm);
+ _iqk_start_iqk_8822b(dm, segment_iqk);
+ _iqk_afe_setting_8822b(dm, false);
+ _iqk_restore_mac_bb_8822b(dm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg);
+ _iqk_restore_rf_8822b(dm, backup_rf_reg, RF_backup);
+ if (dm->rf_calibrate_info.iqk_step == 7)
+ break;
+ iqk_info->kcount = 0;
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]delay 50ms!!!\n");
+ ODM_delay_ms(50);
+ };
+ if (segment_iqk)
+ _iqk_reload_iqk_setting_8822b(dm, 0x0, 0x1);
+#if 0
+ _iqk_afe_setting_8822b(dm, false);
+ _iqk_restore_mac_bb_8822b(dm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg);
+ _iqk_restore_rf_8822b(dm, backup_rf_reg, RF_backup);
+#endif
+ _iqk_fill_iqk_report_8822b(dm, 0);
+ _iqk_rf0xb0_workaround(dm);
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]==========IQK end!!!!!==========\n");
+}
+
+
+void
+_phy_iq_calibrate_by_fw_8822b(
+ void *dm_void,
+ u8 clear,
+ u8 segment_iqk
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+ enum hal_status status = HAL_STATUS_FAILURE;
+
+ if (*dm->mp_mode)
+ clear = 0x1;
+// else if (dm->is_linked)
+// segment_iqk = 0x1;
+
+ iqk_info->iqk_times++;
+ status = odm_iq_calibrate_by_fw(dm, clear, segment_iqk);
+
+ if (status == HAL_STATUS_SUCCESS)
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]FWIQK OK!!!\n");
+ else
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "[IQK]FWIQK fail!!!\n");
+}
+
+/*IQK_version:0x2f, NCTL:0x8*/
+/*1.disable CCK block and OFDM CCA block while IQKing*/
+void
+phy_iq_calibrate_8822b(
+ void *dm_void,
+ boolean clear,
+ boolean segment_iqk
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct _hal_rf_ *rf = &dm->rf_table;
+
+ if (*dm->mp_mode)
+ halrf_iqk_hwtx_check(dm, true);
+ /*FW IQK*/
+ if (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) {
+ _phy_iq_calibrate_by_fw_8822b(dm, clear, (u8)(segment_iqk));
+ phydm_get_read_counter(dm);
+ halrf_iqk_check_if_reload(dm);
+ } else {
+ _iq_calibrate_8822b_init(dm);
+ _phy_iq_calibrate_8822b(dm, clear, segment_iqk);
+ }
+ _iqk_fail_count_8822b(dm);
+ if (*dm->mp_mode)
+ halrf_iqk_hwtx_check(dm, false);
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ _iqk_iqk_fail_report_8822b(dm);
+#endif
+ halrf_iqk_dbg(dm);
+}
+
+void
+_phy_imr_measure(
+ struct dm_struct *dm
+)
+{
+ struct dm_iqk_info *iqk_info = &dm->IQK_info;
+ u32 MAC_backup[MAC_REG_NUM_8822B], BB_backup[BB_REG_NUM_8822B], RF_backup[RF_REG_NUM_8822B][SS_8822B];
+ u32 backup_mac_reg[MAC_REG_NUM_8822B] = {0x520, 0x550};
+ u32 backup_bb_reg[BB_REG_NUM_8822B] = {0x808, 0x90c, 0xc00, 0xcb0, 0xcb4, 0xcbc, 0xe00, 0xeb0, 0xeb4, 0xebc, 0x1990, 0x9a4, 0xa04, 0xb00};
+ u32 backup_rf_reg[RF_REG_NUM_8822B] = {0xdf, 0x8f, 0x65, 0x0, 0x1};
+
+ _iqk_backup_iqk_8822b(dm, 0x0, 0x0);
+ _iqk_backup_mac_bb_8822b(dm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg);
+ _iqk_backup_rf_8822b(dm, RF_backup, backup_rf_reg);
+ _iqk_configure_macbb_8822b(dm);
+ _iqk_afe_setting_8822b(dm, true);
+ _iqk_rfe_setting_8822b(dm, false);
+ _iqk_agc_bnd_int_8822b(dm);
+ _iqk_rf_setting_8822b(dm);
+
+ _iqk_start_imr_test_8822b(dm);
+
+ _iqk_afe_setting_8822b(dm, false);
+ _iqk_restore_mac_bb_8822b(dm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg);
+ _iqk_restore_rf_8822b(dm, backup_rf_reg, RF_backup);
+}
+
+void
+do_imr_test_8822b(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK] ************IMR Test *****************\n");
+ _phy_imr_measure(dm);
+ PHYDM_DBG(dm, ODM_COMP_CALIBRATION,"[IQK] **********End IMR Test *******************\n");
+}
+#endif
diff --git a/hal/phydm/halrf/rtl8822b/halrf_iqk_8822b.h b/hal/phydm/halrf/rtl8822b/halrf_iqk_8822b.h
new file mode 100644
index 0000000..3ec83e3
--- /dev/null
+++ b/hal/phydm/halrf/rtl8822b/halrf_iqk_8822b.h
@@ -0,0 +1,78 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger
+ *
+ *****************************************************************************/
+
+#ifndef __PHYDM_IQK_8822B_H__
+#define __PHYDM_IQK_8822B_H__
+
+#if (RTL8822B_SUPPORT == 1)
+/*--------------------------Define Parameters-------------------------------*/
+#define MAC_REG_NUM_8822B 2
+#define BB_REG_NUM_8822B 15
+#define RF_REG_NUM_8822B 5
+#define LOK_delay_8822B 2
+#define GS_delay_8822B 2
+#define WBIQK_delay_8822B 2
+
+#define TXIQK 0
+#define RXIQK 1
+#define SS_8822B 2
+/*---------------------------End Define Parameters-------------------------------*/
+#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
+void
+do_iqk_8822b(
+ void *dm_void,
+ u8 delta_thermal_index,
+ u8 thermal_value,
+ u8 threshold
+);
+#else
+void
+do_iqk_8822b(
+ void *dm_void,
+ u8 delta_thermal_index,
+ u8 thermal_value,
+ u8 threshold
+);
+#endif
+
+void
+phy_iq_calibrate_8822b(
+ void *dm_void,
+ boolean clear,
+ boolean segment_iqk
+);
+
+void
+do_imr_test_8822b(
+ void *dm_void
+);
+
+#else /* (RTL8822B_SUPPORT == 0)*/
+
+#define phy_iq_calibrate_8822b(_pdm_void, clear, segment_iqk)
+
+#endif /* RTL8822B_SUPPORT */
+
+#endif /* #ifndef __PHYDM_IQK_8822B_H__*/
diff --git a/hal/phydm/mp_precomp.h b/hal/phydm/mp_precomp.h
index 2e950cb..897adc1 100644
--- a/hal/phydm/mp_precomp.h
+++ b/hal/phydm/mp_precomp.h
@@ -1,20 +1,24 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
- *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
*
+ * Larry Finger
*
- ******************************************************************************/
-
+ *****************************************************************************/
diff --git a/hal/phydm/phydm.c b/hal/phydm/phydm.c
index 5f98239..77c044a 100644
--- a/hal/phydm/phydm.c
+++ b/hal/phydm/phydm.c
@@ -1,2998 +1,3092 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
- *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
*
+ * Larry Finger
*
- ******************************************************************************/
+ *****************************************************************************/
-//============================================================
-// include files
-//============================================================
+/* ************************************************************
+ * include files
+ * ************************************************************ */
#include "mp_precomp.h"
#include "phydm_precomp.h"
-const u2Byte dB_Invert_Table[12][8] = {
- { 1, 1, 1, 2, 2, 2, 2, 3},
- { 3, 3, 4, 4, 4, 5, 6, 6},
- { 7, 8, 9, 10, 11, 13, 14, 16},
- { 18, 20, 22, 25, 28, 32, 35, 40},
- { 45, 50, 56, 63, 71, 79, 89, 100},
- { 112, 126, 141, 158, 178, 200, 224, 251},
- { 282, 316, 355, 398, 447, 501, 562, 631},
- { 708, 794, 891, 1000, 1122, 1259, 1413, 1585},
- { 1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981},
- { 4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000},
- { 11220, 12589, 14125, 15849, 17783, 19953, 22387, 25119},
- { 28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535}
-};
-
-
-//============================================================
-// Local Function predefine.
-//============================================================
-
-/* START------------COMMON INFO RELATED--------------- */
-
-VOID
-odm_GlobalAdapterCheck(
- IN VOID
- );
-
-//move to odm_PowerTacking.h by YuChen
-
-
-
-VOID
-odm_UpdatePowerTrainingState(
- IN PDM_ODM_T pDM_Odm
-);
-
-//============================================================
-//3 Export Interface
-//============================================================
-
-/*Y = 10*log(X)*/
-s4Byte
-ODM_PWdB_Conversion(
- IN s4Byte X,
- IN u4Byte TotalBit,
- IN u4Byte DecimalBit
- )
-{
- s4Byte Y, integer = 0, decimal = 0;
- u4Byte i;
-
- if(X == 0)
- X = 1; // log2(x), x can't be 0
-
- for(i = (TotalBit-1); i > 0; i--)
- {
- if(X & BIT(i))
- {
- integer = i;
- if(i > 0)
- decimal = (X & BIT(i-1))?2:0; //decimal is 0.5dB*3=1.5dB~=2dB
- break;
- }
- }
-
- Y = 3*(integer-DecimalBit)+decimal; //10*log(x)=3*log2(x),
- return Y;
-}
-
-s4Byte
-ODM_SignConversion(
- IN s4Byte value,
- IN u4Byte TotalBit
- )
-{
- if(value&BIT(TotalBit-1))
- value -= BIT(TotalBit);
- return value;
-}
+const u16 phy_rate_table[] = { /*20M*/
+ 1, 2, 5, 11,
+ 6, 9, 12, 18, 24, 36, 48, 54,
+ 6, 13, 19, 26, 39, 52, 58, 65, /*MCS0~7*/
+ 13, 26, 39, 52, 78, 104, 117, 130 /*MCS8~15*/
+};
void
-phydm_seq_sorting(
- IN PVOID pDM_VOID,
- IN OUT u4Byte *p_value,
- IN OUT u4Byte *rank_idx,
- IN OUT u4Byte *p_idx_out,
- IN u1Byte seq_length
-)
-{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- u1Byte i = 0 , j = 0;
- u4Byte tmp_a, tmp_b;
- u4Byte tmp_idx_a, tmp_idx_b;
-
- for (i = 0; i < seq_length; i++) {
- rank_idx[i] = i;
- /**/
- }
-
- for (i = 0; i < (seq_length - 1); i++) {
-
- for (j = 0; j < (seq_length - 1 - i); j++) {
-
- tmp_a = p_value[j];
- tmp_b = p_value[j+1];
-
- tmp_idx_a = rank_idx[j];
- tmp_idx_b = rank_idx[j+1];
-
- if (tmp_a < tmp_b) {
- p_value[j] = tmp_b;
- p_value[j+1] = tmp_a;
-
- rank_idx[j] = tmp_idx_b;
- rank_idx[j+1] = tmp_idx_a;
- }
- }
- }
-
- for (i = 0; i < seq_length; i++) {
- p_idx_out[rank_idx[i]] = i+1;
- /**/
- }
-
-
-
-}
-
-VOID
-ODM_InitMpDriverStatus(
- IN PDM_ODM_T pDM_Odm
+phydm_traffic_load_decision(
+ void *dm_void
)
{
-#if(DM_ODM_SUPPORT_TYPE & ODM_WIN)
-
- // Decide when compile time
- #if(MP_DRIVER == 1)
- pDM_Odm->mp_mode = TRUE;
- #else
- pDM_Odm->mp_mode = FALSE;
- #endif
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ u8 bit_shift_num = 0;
-#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
+ /*---TP & Trafic-load calculation---*/
- PADAPTER Adapter = pDM_Odm->Adapter;
+ if (dm->last_tx_ok_cnt > *dm->num_tx_bytes_unicast)
+ dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast;
- // Update information every period
- pDM_Odm->mp_mode = (BOOLEAN)Adapter->registrypriv.mp_mode;
+ if (dm->last_rx_ok_cnt > *dm->num_rx_bytes_unicast)
+ dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast;
-#else
-
- prtl8192cd_priv priv = pDM_Odm->priv;
-
- pDM_Odm->mp_mode = (BOOLEAN)priv->pshare->rf_ft_var.mp_specific;
-
-#endif
-}
-
-VOID
-ODM_UpdateMpDriverStatus(
- IN PDM_ODM_T pDM_Odm
-)
-{
-#if(DM_ODM_SUPPORT_TYPE & ODM_WIN)
-
- // Do nothing.
+ dm->cur_tx_ok_cnt = *dm->num_tx_bytes_unicast - dm->last_tx_ok_cnt;
+ dm->cur_rx_ok_cnt = *dm->num_rx_bytes_unicast - dm->last_rx_ok_cnt;
+ dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast;
+ dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast;
-#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
- PADAPTER Adapter = pDM_Odm->Adapter;
+ bit_shift_num = 17 + (PHYDM_WATCH_DOG_PERIOD - 1); /*AP: <<3(8bit), >>20(10^6,M), >>0(1sec)*/
+ /*WIN&CE: <<3(8bit), >>20(10^6,M), >>1(2sec)*/
- // Update information erery period
- pDM_Odm->mp_mode = (BOOLEAN)Adapter->registrypriv.mp_mode;
+ dm->tx_tp = ((dm->tx_tp) >> 1) + (u32)(((dm->cur_tx_ok_cnt) >> bit_shift_num) >> 1);
+ dm->rx_tp = ((dm->rx_tp) >> 1) + (u32)(((dm->cur_rx_ok_cnt) >> bit_shift_num) >> 1);
-#else
+ dm->total_tp = dm->tx_tp + dm->rx_tp;
- // Do nothing.
+ /*[Calculate TX/RX state]*/
+ if (dm->tx_tp > (dm->rx_tp << 1))
+ dm->txrx_state_all = TX_STATE;
+ else if (dm->rx_tp > (dm->tx_tp << 1))
+ dm->txrx_state_all = RX_STATE;
+ else
+ dm->txrx_state_all = BI_DIRECTION_STATE;
-#endif
-}
+ /*[Calculate consecutive idlel time]*/
+ if (dm->total_tp == 0)
+ dm->consecutive_idlel_time += PHYDM_WATCH_DOG_PERIOD;
+ else
+ dm->consecutive_idlel_time = 0;
-VOID
-PHYDM_InitTRXAntennaSetting(
- IN PDM_ODM_T pDM_Odm
-)
-{
-/*#if (RTL8814A_SUPPORT == 1)*/
-
- if (pDM_Odm->SupportICType & (ODM_RTL8814A)) {
- u1Byte RxAnt = 0, TxAnt = 0;
-
- RxAnt = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG(BB_RX_PATH, pDM_Odm), ODM_BIT(BB_RX_PATH, pDM_Odm));
- TxAnt = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG(BB_TX_PATH, pDM_Odm), ODM_BIT(BB_TX_PATH, pDM_Odm));
- pDM_Odm->TXAntStatus = (TxAnt & 0xf);
- pDM_Odm->RXAntStatus = (RxAnt & 0xf);
- } else if (pDM_Odm->SupportICType & (ODM_RTL8723D | ODM_RTL8821C)) {
- pDM_Odm->TXAntStatus = 0x1;
- pDM_Odm->RXAntStatus = 0x1;
-
- }
-/*#endif*/
-}
+ /*[Traffic load decision]*/
+ dm->pre_traffic_load = dm->traffic_load;
-void
-phydm_traffic_load_decision(
- IN PVOID pDM_VOID
- )
-{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
-
- /*---trafic load decision---*/
- pDM_Odm->curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast) - pDM_Odm->lastTxOkCnt;
- pDM_Odm->curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast) - pDM_Odm->lastRxOkCnt;
- pDM_Odm->lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast);
- pDM_Odm->lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast);
-
- #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
- pDM_Odm->tx_tp = ((pDM_Odm->tx_tp)>>1) + (u4Byte)(((pDM_Odm->curTxOkCnt)>>17)>>1); /* <<3(8bit), >>20(10^6,M)*/
- pDM_Odm->rx_tp = ((pDM_Odm->rx_tp)>>1) + (u4Byte)(((pDM_Odm->curRxOkCnt)>>17)>>1); /* <<3(8bit), >>20(10^6,M)*/
- #else
- pDM_Odm->tx_tp = ((pDM_Odm->tx_tp)>>1) + (u4Byte)(((pDM_Odm->curTxOkCnt)>>18)>>1); /* <<3(8bit), >>20(10^6,M), >>1(2sec)*/
- pDM_Odm->rx_tp = ((pDM_Odm->rx_tp)>>1) + (u4Byte)(((pDM_Odm->curRxOkCnt)>>18)>>1); /* <<3(8bit), >>20(10^6,M), >>1(2sec)*/
- #endif
- pDM_Odm->total_tp = pDM_Odm->tx_tp + pDM_Odm->rx_tp;
-
+ if (dm->cur_tx_ok_cnt > 1875000 || dm->cur_rx_ok_cnt > 1875000) { /* ( 1.875M * 8bit ) / 2sec= 7.5M bits /sec )*/
- pDM_Odm->pre_TrafficLoad = pDM_Odm->TrafficLoad;
-
- if (pDM_Odm->curTxOkCnt > 1875000 || pDM_Odm->curRxOkCnt > 1875000) { /* ( 1.875M * 8bit ) / 2sec= 7.5M bits /sec )*/
-
- pDM_Odm->TrafficLoad = TRAFFIC_HIGH;
+ dm->traffic_load = TRAFFIC_HIGH;
/**/
- } else if (pDM_Odm->curTxOkCnt > 500000 || pDM_Odm->curRxOkCnt > 500000) { /*( 0.5M * 8bit ) / 2sec = 2M bits /sec )*/
-
- pDM_Odm->TrafficLoad = TRAFFIC_MID;
+ } else if (dm->cur_tx_ok_cnt > 500000 || dm->cur_rx_ok_cnt > 500000) { /*( 0.5M * 8bit ) / 2sec = 2M bits /sec )*/
+
+ dm->traffic_load = TRAFFIC_MID;
/**/
- } else if (pDM_Odm->curTxOkCnt > 100000 || pDM_Odm->curRxOkCnt > 100000) { /*( 0.1M * 8bit ) / 2sec = 0.4M bits /sec )*/
-
- pDM_Odm->TrafficLoad = TRAFFIC_LOW;
+ } else if (dm->cur_tx_ok_cnt > 100000 || dm->cur_rx_ok_cnt > 100000) { /*( 0.1M * 8bit ) / 2sec = 0.4M bits /sec )*/
+
+ dm->traffic_load = TRAFFIC_LOW;
/**/
} else {
-
- pDM_Odm->TrafficLoad = TRAFFIC_ULTRA_LOW;
+ dm->traffic_load = TRAFFIC_ULTRA_LOW;
/**/
}
-}
-VOID
-phydm_config_ofdm_tx_path(
- IN PDM_ODM_T pDM_Odm,
- IN u4Byte path
-)
-{
- u1Byte ofdm_rx_path;
+ /*
+ PHYDM_DBG(dm, DBG_COMMON_FLOW, "cur_tx_ok_cnt = %d, cur_rx_ok_cnt = %d, last_tx_ok_cnt = %d, last_rx_ok_cnt = %d\n",
+ dm->cur_tx_ok_cnt, dm->cur_rx_ok_cnt, dm->last_tx_ok_cnt, dm->last_rx_ok_cnt);
- #if (RTL8192E_SUPPORT == 1)
- if (pDM_Odm->SupportICType & (ODM_RTL8192E)) {
-
- if (path == PHYDM_A) {
- ODM_SetBBReg(pDM_Odm, 0x90c , bMaskDWord, 0x81321311);
- /**/
- } else if (path == PHYDM_B) {
- ODM_SetBBReg(pDM_Odm, 0x90c , bMaskDWord, 0x82321322);
- /**/
- } else if (path == PHYDM_AB) {
- ODM_SetBBReg(pDM_Odm, 0x90c , bMaskDWord, 0x83321333);
- /**/
- }
-
+ PHYDM_DBG(dm, DBG_COMMON_FLOW, "tx_tp = %d, rx_tp = %d\n",
+ dm->tx_tp, dm->rx_tp);
+ */
- }
- #endif
}
-VOID
-phydm_config_ofdm_rx_path(
- IN PDM_ODM_T pDM_Odm,
- IN u4Byte path
+void
+phydm_init_cck_setting(
+ struct dm_struct *dm
)
{
- u1Byte ofdm_rx_path = 0;
+#if (RTL8192E_SUPPORT == 1)
+ u32 value_824, value_82c;
+#endif
- #if (RTL8192E_SUPPORT == 1)
- if (pDM_Odm->SupportICType & (ODM_RTL8192E)) {
-
- if (path == PHYDM_A) {
- ofdm_rx_path = 1;
- /**/
- } else if (path == PHYDM_B) {
- ofdm_rx_path = 2;
- /**/
- } else if (path == PHYDM_AB) {
- ofdm_rx_path = 3;
- /**/
- }
-
- ODM_SetBBReg(pDM_Odm, 0xC04 , 0xff, (((ofdm_rx_path)<<4)|ofdm_rx_path));
- ODM_SetBBReg(pDM_Odm, 0xD04 , 0xf, ofdm_rx_path);
- }
- #endif
-}
+ dm->is_cck_high_power = (boolean) odm_get_bb_reg(dm, ODM_REG(CCK_RPT_FORMAT, dm), ODM_BIT(CCK_RPT_FORMAT, dm));
-VOID
-phydm_config_cck_rx_antenna_init(
- IN PDM_ODM_T pDM_Odm
-)
-{
- #if (RTL8192E_SUPPORT == 1)
- if (pDM_Odm->SupportICType & (ODM_RTL8192E)) {
-
- /*CCK 2R CCA parameters*/
- ODM_SetBBReg(pDM_Odm, 0xa2c , BIT18, 1); /*enable 2R Rx path*/
- ODM_SetBBReg(pDM_Odm, 0xa2c , BIT22, 1); /*enable 2R MRC*/
- ODM_SetBBReg(pDM_Odm, 0xa84 , BIT28, 1); /*1. pdx1[5:0] > 2*PD_lim 2. RXIQ_3 = 0 ( signed )*/
- ODM_SetBBReg(pDM_Odm, 0xa70 , BIT7, 0); /*Concurrent CCA at LSB & USB*/
- ODM_SetBBReg(pDM_Odm, 0xa74 , BIT8, 0); /*RX path diversity enable*/
- ODM_SetBBReg(pDM_Odm, 0xa08 , BIT28, 1); /* r_cck_2nd_sel_eco*/
- ODM_SetBBReg(pDM_Odm, 0xa14 , BIT7, 0); /* r_en_mrc_antsel*/
- }
- #endif
-}
+ phydm_config_cck_rx_antenna_init(dm);
+ phydm_config_cck_rx_path(dm, BB_PATH_A);
-VOID
-phydm_config_cck_rx_path(
- IN PDM_ODM_T pDM_Odm,
- IN u1Byte path,
- IN u1Byte path_div_en
-)
-{
- u1Byte path_div_select = 0;
- u1Byte cck_1_path = 0, cck_2_path = 0;
+#if (RTL8192E_SUPPORT == 1)
+ if (dm->support_ic_type & (ODM_RTL8192E)) {
+ /* 0x824[9] = 0x82C[9] = 0xA80[7] those registers setting should be equal or CCK RSSI report may be incorrect */
+ value_824 = odm_get_bb_reg(dm, 0x824, BIT(9));
+ value_82c = odm_get_bb_reg(dm, 0x82c, BIT(9));
- #if (RTL8192E_SUPPORT == 1)
- if (pDM_Odm->SupportICType & (ODM_RTL8192E)) {
-
- if (path == PHYDM_A) {
- path_div_select = 0;
- cck_1_path = 0;
- cck_2_path = 0;
- } else if (path == PHYDM_B) {
- path_div_select = 0;
- cck_1_path = 1;
- cck_2_path = 1;
- } else if (path == PHYDM_AB) {
-
- if (path_div_en == CCA_PATHDIV_ENABLE)
- path_div_select = 1;
-
- cck_1_path = 0;
- cck_2_path = 1;
-
- }
-
- ODM_SetBBReg(pDM_Odm, 0xa04 , (BIT27|BIT26), cck_1_path);
- ODM_SetBBReg(pDM_Odm, 0xa04 , (BIT25|BIT24), cck_2_path);
- ODM_SetBBReg(pDM_Odm, 0xa74 , BIT8, path_div_select);
-
- }
- #endif
-}
+ if (value_824 != value_82c)
+ odm_set_bb_reg(dm, 0x82c, BIT(9), value_824);
+ odm_set_bb_reg(dm, 0xa80, BIT(7), value_824);
+ dm->cck_agc_report_type = (boolean)value_824;
-VOID
-phydm_config_trx_path(
- IN PVOID pDM_VOID,
- IN u4Byte *const dm_value,
- IN u4Byte *_used,
- OUT char *output,
- IN u4Byte *_out_len
- )
-{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- u4Byte pre_support_ability;
- u4Byte used = *_used;
- u4Byte out_len = *_out_len;
+ PHYDM_DBG(dm, ODM_COMP_INIT, "cck_agc_report_type = (( %d )), ext_lna_gain = (( %d ))\n", dm->cck_agc_report_type, dm->ext_lna_gain);
+ }
+#endif
- /* CCK */
- if (dm_value[0] == 0) {
-
- if (dm_value[1] == 1) { /*TX*/
- if (dm_value[2] == 1)
- ODM_SetBBReg(pDM_Odm, 0xa04, 0xf0000000, 0x8);
- else if (dm_value[2] == 2)
- ODM_SetBBReg(pDM_Odm, 0xa04, 0xf0000000, 0x4);
- else if (dm_value[2] == 3)
- ODM_SetBBReg(pDM_Odm, 0xa04, 0xf0000000, 0xc);
- } else if (dm_value[1] == 2) { /*RX*/
-
- phydm_config_cck_rx_antenna_init(pDM_Odm);
-
- if (dm_value[2] == 1) {
- phydm_config_cck_rx_path(pDM_Odm, PHYDM_A, CCA_PATHDIV_DISABLE);
- } else if (dm_value[2] == 2) {
- phydm_config_cck_rx_path(pDM_Odm, PHYDM_B, CCA_PATHDIV_DISABLE);
- } else if (dm_value[2] == 3) {
- if (dm_value[3] == 1) /*enable path diversity*/
- phydm_config_cck_rx_path(pDM_Odm, PHYDM_AB, CCA_PATHDIV_ENABLE);
- else
- phydm_config_cck_rx_path(pDM_Odm, PHYDM_B, CCA_PATHDIV_DISABLE);
- }
- }
- }
- /* OFDM */
- else if (dm_value[0] == 1) {
+#if ((RTL8703B_SUPPORT == 1) || (RTL8723D_SUPPORT == 1) || (RTL8710B_SUPPORT == 1))
+ if (dm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) {
+ dm->cck_agc_report_type = odm_get_bb_reg(dm, 0x950, BIT(11)) ? 1 : 0; /*1: 4bit LNA, 0: 3bit LNA */
- if (dm_value[1] == 1) { /*TX*/
- phydm_config_ofdm_tx_path(pDM_Odm, dm_value[2]);
- /**/
- } else if (dm_value[1] == 2) { /*RX*/
- phydm_config_ofdm_rx_path(pDM_Odm, dm_value[2]);
+ if (dm->cck_agc_report_type != 1) {
+ pr_debug("[Warning] 8703B/8723D/8710B CCK should be 4bit LNA, ie. 0x950[11] = 1\n");
/**/
}
}
+#endif
- PHYDM_SNPRINTF((output+used, out_len-used, "PHYDM Set Path [%s] [%s] = [%s%s%s%s]\n",
- (dm_value[0] == 1) ? "CCK" : "OFDM",
- (dm_value[1] == 1) ? "TX" : "RX",
- (dm_value[2] & 0x1)?"A":"",
- (dm_value[2] & 0x2)?"B":"",
- (dm_value[2] & 0x4)?"C":"",
- (dm_value[2] & 0x8)?"D":""
- ));
-
-}
-
-VOID
-phydm_Init_cck_setting(
- IN PDM_ODM_T pDM_Odm
-)
-{
- u4Byte value_824,value_82c;
-
- pDM_Odm->bCckHighPower = (BOOLEAN) ODM_GetBBReg(pDM_Odm, ODM_REG(CCK_RPT_FORMAT,pDM_Odm), ODM_BIT(CCK_RPT_FORMAT,pDM_Odm));
+#if (RTL8821C_SUPPORT == 1)
+ if (dm->support_ic_type & ODM_RTL8821C) {
+ dm->cck_new_agc = odm_get_bb_reg(dm, 0xa9c, BIT(17)) ? true : false; /*1: new agc 0: old agc*/
+ if (dm->cck_new_agc == 0 && dm->default_rf_set_8821c == SWITCH_TO_BTG)
+ dm->cck_agc_report_type = 1;
+ }
+#endif
- #if (RTL8192E_SUPPORT == 1)
- if(pDM_Odm->SupportICType & (ODM_RTL8192E))
+#if ((RTL8723D_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8710B_SUPPORT == 1))
+ if (dm->support_ic_type & (ODM_RTL8723D | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8710B))
+ dm->cck_new_agc = odm_get_bb_reg(dm, 0xa9c, BIT(17)) ? true : false; /*1: new agc 0: old agc*/
+ else
+#endif
{
- #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
- phydm_config_cck_rx_antenna_init(pDM_Odm);
- phydm_config_cck_rx_path(pDM_Odm, PHYDM_A, CCA_PATHDIV_DISABLE);
- #endif
-
- /* 0x824[9] = 0x82C[9] = 0xA80[7] those registers setting should be equal or CCK RSSI report may be incorrect */
- value_824 = ODM_GetBBReg(pDM_Odm, 0x824, BIT9);
- value_82c = ODM_GetBBReg(pDM_Odm, 0x82c, BIT9);
-
- if(value_824 != value_82c)
- {
- ODM_SetBBReg(pDM_Odm, 0x82c , BIT9, value_824);
- }
- ODM_SetBBReg(pDM_Odm, 0xa80 , BIT7, value_824);
- pDM_Odm->cck_agc_report_type = (BOOLEAN)value_824;
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("cck_agc_report_type = (( %d )), ExtLNAGain = (( %d ))\n", pDM_Odm->cck_agc_report_type, pDM_Odm->ExtLNAGain));
+ dm->cck_new_agc = false;
+ /**/
}
- #endif
-
-#if ((RTL8703B_SUPPORT == 1) || (RTL8723D_SUPPORT == 1))
- if (pDM_Odm->SupportICType & (ODM_RTL8703B|ODM_RTL8723D)) {
- pDM_Odm->cck_agc_report_type = ODM_GetBBReg(pDM_Odm, 0x950, BIT11) ? 1 : 0; /*1: 4bit LNA , 0: 3bit LNA */
-
- if (pDM_Odm->cck_agc_report_type != 1) {
- DbgPrint("[Warning] 8703B/8723D CCK should be 4bit LNA, ie. 0x950[11] = 1\n");
- /**/
- }
- }
-#endif
-
-#if ((RTL8723D_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1))
+ phydm_get_cck_rssi_table_from_reg(dm);
- if (pDM_Odm->SupportICType & (ODM_RTL8723D|ODM_RTL8822B|ODM_RTL8197F)) {
- pDM_Odm->cck_new_agc = ODM_GetBBReg(pDM_Odm, 0xa9c, BIT17)?TRUE:FALSE; /*1: new agc 0: old agc*/
- } else
-#endif
- pDM_Odm->cck_new_agc = FALSE;
-
}
-VOID
-PHYDM_InitSoftMLSetting(
- IN PDM_ODM_T pDM_Odm
+void
+phydm_init_hw_info_by_rfe(
+ struct dm_struct *dm
)
{
#if (RTL8822B_SUPPORT == 1)
- if (pDM_Odm->mp_mode == FALSE) {
- if (pDM_Odm->SupportICType & ODM_RTL8822B)
- ODM_SetBBReg(pDM_Odm, 0x19a8, bMaskDWord, 0xc10a0000);
- }
+ if (dm->support_ic_type & ODM_RTL8822B)
+ phydm_init_hw_info_by_rfe_type_8822b(dm);
+#endif
+#if (RTL8821C_SUPPORT == 1)
+ if (dm->support_ic_type & ODM_RTL8821C)
+ phydm_init_hw_info_by_rfe_type_8821c(dm);
+#endif
+#if (RTL8197F_SUPPORT == 1)
+ if (dm->support_ic_type & ODM_RTL8197F)
+ phydm_init_hw_info_by_rfe_type_8197f(dm);
#endif
}
-VOID
-PHYDM_InitHwInfoByRfe(
- IN PDM_ODM_T pDM_Odm
+void
+phydm_common_info_self_init(
+ struct dm_struct *dm
)
{
-#if (RTL8822B_SUPPORT == 1)
- if (pDM_Odm->SupportICType & ODM_RTL8822B)
- phydm_init_hw_info_by_rfe_type_8822b(pDM_Odm);
+ phydm_init_cck_setting(dm);
+ dm->rf_path_rx_enable = (u8) odm_get_bb_reg(dm, ODM_REG(BB_RX_PATH, dm), ODM_BIT(BB_RX_PATH, dm));
+#if (DM_ODM_SUPPORT_TYPE != ODM_CE)
+ dm->is_net_closed = &dm->BOOLEAN_temp;
+
+ phydm_init_debug_setting(dm);
#endif
+ phydm_init_trx_antenna_setting(dm);
+ phydm_init_soft_ml_setting(dm);
+
+ dm->phydm_sys_up_time = 0;
+
+ if (dm->support_ic_type & ODM_IC_1SS)
+ dm->num_rf_path = 1;
+ else if (dm->support_ic_type & ODM_IC_2SS)
+ dm->num_rf_path = 2;
+ else if (dm->support_ic_type & ODM_IC_3SS)
+ dm->num_rf_path = 3;
+ else if (dm->support_ic_type & ODM_IC_4SS)
+ dm->num_rf_path = 4;
+ else
+ dm->num_rf_path = 1;
+
+ dm->tx_rate = 0xFF;
+ dm->rssi_min_by_path = 0xFF;
+
+ dm->number_linked_client = 0;
+ dm->pre_number_linked_client = 0;
+ dm->number_active_client = 0;
+ dm->pre_number_active_client = 0;
+
+ dm->last_tx_ok_cnt = 0;
+ dm->last_rx_ok_cnt = 0;
+ dm->tx_tp = 0;
+ dm->rx_tp = 0;
+ dm->total_tp = 0;
+ dm->traffic_load = TRAFFIC_LOW;
+
+ dm->nbi_set_result = 0;
+ dm->is_init_hw_info_by_rfe = false;
+ dm->pre_dbg_priority = BB_DBGPORT_RELEASE;
+ dm->tp_active_th = 5;
+ dm->disable_phydm_watchdog = 0;
+
+ dm->u8_dummy = 0xf;
+ dm->u16_dummy = 0xffff;
+ dm->u32_dummy = 0xffffffff;
+
+ /*odm_memory_set(dm, &(dm->pause_lv_table.lv_dig), 0, sizeof(struct phydm_pause_lv));*/
+ dm->pause_lv_table.lv_cckpd = PHYDM_PAUSE_RELEASE;
+ dm->pause_lv_table.lv_dig = PHYDM_PAUSE_RELEASE;
+
}
-VOID
-odm_CommonInfoSelfInit(
- IN PDM_ODM_T pDM_Odm
- )
+void
+phydm_cmn_sta_info_update(
+ void *dm_void,
+ u8 macid
+)
{
- phydm_Init_cck_setting(pDM_Odm);
- pDM_Odm->RFPathRxEnable = (u1Byte) ODM_GetBBReg(pDM_Odm, ODM_REG(BB_RX_PATH,pDM_Odm), ODM_BIT(BB_RX_PATH,pDM_Odm));
-#if (DM_ODM_SUPPORT_TYPE != ODM_CE)
- pDM_Odm->pbNet_closed = &pDM_Odm->BOOLEAN_temp;
-#endif
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct cmn_sta_info *sta = dm->phydm_sta_info[macid];
+ struct ra_sta_info *ra = NULL;
- PHYDM_InitDebugSetting(pDM_Odm);
- ODM_InitMpDriverStatus(pDM_Odm);
- PHYDM_InitTRXAntennaSetting(pDM_Odm);
- PHYDM_InitSoftMLSetting(pDM_Odm);
+ if (is_sta_active(sta)) {
+ ra = &sta->ra_info;
+ } else {
+ PHYDM_DBG(dm, DBG_RA_MASK, "[Warning] %s invalid sta_info\n", __func__);
+ return;
+ }
- pDM_Odm->TxRate = 0xFF;
+ PHYDM_DBG(dm, DBG_RA_MASK, "%s ======>\n", __func__);
+ PHYDM_DBG(dm, DBG_RA_MASK, "MACID=%d\n", sta->mac_id);
- pDM_Odm->number_linked_client = 0;
- pDM_Odm->pre_number_linked_client = 0;
- pDM_Odm->number_active_client = 0;
- pDM_Odm->pre_number_active_client = 0;
+ /*[Calculate TX/RX state]*/
+ if (sta->tx_moving_average_tp > (sta->rx_moving_average_tp << 1))
+ ra->txrx_state= TX_STATE;
+ else if (sta->rx_moving_average_tp > (sta->tx_moving_average_tp << 1))
+ ra->txrx_state = RX_STATE;
+ else
+ ra->txrx_state = BI_DIRECTION_STATE;
- pDM_Odm->lastTxOkCnt = 0;
- pDM_Odm->lastRxOkCnt = 0;
- pDM_Odm->tx_tp = 0;
- pDM_Odm->rx_tp = 0;
- pDM_Odm->total_tp = 0;
- pDM_Odm->TrafficLoad = TRAFFIC_LOW;
+ ra->is_noisy = dm->noisy_decision;
- pDM_Odm->nbi_set_result = 0;
-
}
-VOID
-odm_CommonInfoSelfUpdate(
- IN PDM_ODM_T pDM_Odm
- )
+void
+phydm_common_info_self_update(
+ struct dm_struct *dm
+)
{
- u1Byte EntryCnt = 0, num_active_client = 0;
- u4Byte i, OneEntry_MACID = 0, ma_rx_tp = 0;
- PSTA_INFO_T pEntry;
+ u8 sta_cnt = 0, num_active_client = 0;
+ u32 i, one_entry_macid = 0;
+ u32 ma_rx_tp = 0;
+ struct cmn_sta_info *sta;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
- PADAPTER Adapter = pDM_Odm->Adapter;
- PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
+ PADAPTER adapter = (PADAPTER)dm->adapter;
- pEntry = pDM_Odm->pODM_StaInfo[0];
- if (pMgntInfo->mAssoc) {
- pEntry->bUsed = TRUE;
+ PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;
+
+ sta = dm->phydm_sta_info[0];
+ if (mgnt_info->mAssoc) {
+ sta->dm_ctrl |= STA_DM_CTRL_ACTIVE;
for (i = 0; i < 6; i++)
- pEntry->MacAddr[i] = pMgntInfo->Bssid[i];
- } else if (GetFirstClientPort(Adapter)) {
- PADAPTER pClientAdapter = GetFirstClientPort(Adapter);
+ sta->mac_addr[i] = mgnt_info->Bssid[i];
+ } else if (GetFirstClientPort(adapter)) {
+ //void *client_adapter = GetFirstClientPort(adapter);
+ struct _ADAPTER *client_adapter = GetFirstClientPort(adapter);
- pEntry->bUsed = TRUE;
+ sta->dm_ctrl |= STA_DM_CTRL_ACTIVE;
for (i = 0; i < 6; i++)
- pEntry->MacAddr[i] = pClientAdapter->MgntInfo.Bssid[i];
+ sta->mac_addr[i] = client_adapter->MgntInfo.Bssid[i];
} else {
- pEntry->bUsed = FALSE;
+ sta->dm_ctrl = sta->dm_ctrl & (~STA_DM_CTRL_ACTIVE);
for (i = 0; i < 6; i++)
- pEntry->MacAddr[i] = 0;
+ sta->mac_addr[i] = 0;
}
- //STA mode is linked to AP
- if(IS_STA_VALID(pDM_Odm->pODM_StaInfo[0]) && !ACTING_AS_AP(Adapter))
- pDM_Odm->bsta_state = TRUE;
+ /* STA mode is linked to AP */
+ if (is_sta_active(sta) && !ACTING_AS_AP(adapter))
+ dm->bsta_state = true;
else
- pDM_Odm->bsta_state = FALSE;
+ dm->bsta_state = false;
#endif
-/* THis variable cannot be used because it is wrong*/
-#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
- if (*(pDM_Odm->pBandWidth) == ODM_BW40M)
- {
- if (*(pDM_Odm->pSecChOffset) == 1)
- pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) + 2;
- else if (*(pDM_Odm->pSecChOffset) == 2)
- pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) - 2;
- } else if (*(pDM_Odm->pBandWidth) == ODM_BW80M) {
- if (*(pDM_Odm->pSecChOffset) == 1)
- pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) + 6;
- else if (*(pDM_Odm->pSecChOffset) == 2)
- pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) - 6;
- } else
- pDM_Odm->ControlChannel = *(pDM_Odm->pChannel);
-#else
- if (*(pDM_Odm->pBandWidth) == ODM_BW40M) {
- if (*(pDM_Odm->pSecChOffset) == 1)
- pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) - 2;
- else if (*(pDM_Odm->pSecChOffset) == 2)
- pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) + 2;
- } else
- pDM_Odm->ControlChannel = *(pDM_Odm->pChannel);
-#endif
+ for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
+ sta = dm->phydm_sta_info[i];
+ if (is_sta_active(sta)) {
+ sta_cnt++;
+
+ if (sta_cnt == 1)
+ one_entry_macid = i;
- for (i=0; ipODM_StaInfo[i];
- if(IS_STA_VALID(pEntry))
- {
- EntryCnt++;
- if(EntryCnt==1)
- {
- OneEntry_MACID=i;
- }
+ phydm_cmn_sta_info_update(dm, (u8)i);
+ #if (BEAMFORMING_SUPPORT == 1)
+ //phydm_get_txbf_device_num(dm, (u8)i);
+ #endif
- #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
- ma_rx_tp = (pEntry->rx_byte_cnt_LowMAW)<<3; /* low moving average RX TP ( bit /sec)*/
+ ma_rx_tp = sta->rx_moving_average_tp + sta->tx_moving_average_tp;
+ PHYDM_DBG(dm, DBG_COMMON_FLOW, "TP[%d]: ((%d )) bit/sec\n", i, ma_rx_tp);
- ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("ClientTP[%d]: ((%d )) bit/sec\n", i, ma_rx_tp));
-
- if (ma_rx_tp > ACTIVE_TP_THRESHOLD)
- num_active_client++;
- #endif
- }
- }
-
- if(EntryCnt == 1)
- {
- pDM_Odm->bOneEntryOnly = TRUE;
- pDM_Odm->OneEntry_MACID=OneEntry_MACID;
+ if (ma_rx_tp > ACTIVE_TP_THRESHOLD)
+ num_active_client++;
+ }
}
- else
- pDM_Odm->bOneEntryOnly = FALSE;
- pDM_Odm->pre_number_linked_client = pDM_Odm->number_linked_client;
- pDM_Odm->pre_number_active_client = pDM_Odm->number_active_client;
-
- pDM_Odm->number_linked_client = EntryCnt;
- pDM_Odm->number_active_client = num_active_client;
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+ dm->is_linked = (sta_cnt != 0) ? true : false;
+#endif
+
+ if (sta_cnt == 1) {
+ dm->is_one_entry_only = true;
+ dm->one_entry_macid = one_entry_macid;
+ dm->one_entry_tp = ma_rx_tp;
- /* Update MP driver status*/
- ODM_UpdateMpDriverStatus(pDM_Odm);
+ dm->tp_active_occur = 0;
+
+ PHYDM_DBG(dm, DBG_COMMON_FLOW, "one_entry_tp=((%d)), pre_one_entry_tp=((%d))\n",
+ dm->one_entry_tp, dm->pre_one_entry_tp);
+
+ if ((dm->one_entry_tp > dm->pre_one_entry_tp) && (dm->pre_one_entry_tp <= 2)) {
+ if ((dm->one_entry_tp - dm->pre_one_entry_tp) > dm->tp_active_th)
+ dm->tp_active_occur = 1;
+ }
+ dm->pre_one_entry_tp = dm->one_entry_tp;
+ } else
+ dm->is_one_entry_only = false;
+
+ dm->pre_number_linked_client = dm->number_linked_client;
+ dm->pre_number_active_client = dm->number_active_client;
+
+ dm->number_linked_client = sta_cnt;
+ dm->number_active_client = num_active_client;
/*Traffic load information update*/
- phydm_traffic_load_decision(pDM_Odm);
+ phydm_traffic_load_decision(dm);
+
+ dm->phydm_sys_up_time += PHYDM_WATCH_DOG_PERIOD;
+
+ dm->is_dfs_band = phydm_is_dfs_band(dm);
+ dm->phy_dbg_info.show_phy_sts_cnt = 0;
+
}
-VOID
-odm_CommonInfoSelfReset(
- IN PDM_ODM_T pDM_Odm
- )
+void
+phydm_common_info_self_reset(
+ struct dm_struct *dm
+)
{
-#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
- pDM_Odm->PhyDbgInfo.NumQryBeaconPkt = 0;
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+ dm->phy_dbg_info.num_qry_beacon_pkt = 0;
#endif
}
-PVOID
-PhyDM_Get_Structure(
- IN PDM_ODM_T pDM_Odm,
- IN u1Byte Structure_Type
+void *
+phydm_get_structure(
+ struct dm_struct *dm,
+ u8 structure_type
)
{
- PVOID pStruct = NULL;
+ void *structure = NULL;
#if RTL8195A_SUPPORT
- switch (Structure_Type){
- case PHYDM_FALSEALMCNT:
- pStruct = &FalseAlmCnt;
+ switch (structure_type) {
+ case PHYDM_FALSEALMCNT:
+ structure = &false_alm_cnt;
break;
-
- case PHYDM_CFOTRACK:
- pStruct = &DM_CfoTrack;
+
+ case PHYDM_CFOTRACK:
+ structure = &dm_cfo_track;
break;
- case PHYDM_ADAPTIVITY:
- pStruct = &(pDM_Odm->Adaptivity);
+ case PHYDM_ADAPTIVITY:
+ structure = &dm->adaptivity;
break;
-
- default:
+
+ default:
break;
}
#else
- switch (Structure_Type){
- case PHYDM_FALSEALMCNT:
- pStruct = &(pDM_Odm->FalseAlmCnt);
+ switch (structure_type) {
+ case PHYDM_FALSEALMCNT:
+ structure = &dm->false_alm_cnt;
break;
-
- case PHYDM_CFOTRACK:
- pStruct = &(pDM_Odm->DM_CfoTrack);
+
+ case PHYDM_CFOTRACK:
+ structure = &dm->dm_cfo_track;
break;
- case PHYDM_ADAPTIVITY:
- pStruct = &(pDM_Odm->Adaptivity);
+ case PHYDM_ADAPTIVITY:
+ structure = &dm->adaptivity;
break;
-
- default:
+
+ case PHYDM_DFS:
+ structure = &dm->dfs;
+ break;
+
+ default:
break;
}
#endif
- return pStruct;
+ return structure;
}
-VOID
-odm_HWSetting(
- IN PDM_ODM_T pDM_Odm
- )
+void
+phydm_hw_setting(
+ struct dm_struct *dm
+)
{
#if (RTL8821A_SUPPORT == 1)
- if(pDM_Odm->SupportICType & ODM_RTL8821)
- odm_HWSetting_8821A(pDM_Odm);
+ if (dm->support_ic_type & ODM_RTL8821)
+ odm_hw_setting_8821a(dm);
#endif
#if (RTL8814A_SUPPORT == 1)
- if (pDM_Odm->SupportICType & ODM_RTL8814A)
- phydm_hwsetting_8814a(pDM_Odm);
+ if (dm->support_ic_type & ODM_RTL8814A)
+ phydm_hwsetting_8814a(dm);
#endif
-}
-
-//
-// 2011/09/21 MH Add to describe different team necessary resource allocate??
-//
-VOID
-ODM_DMInit(
- IN PDM_ODM_T pDM_Odm
- )
-{
-#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
- PADAPTER Adapter = pDM_Odm->Adapter;
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
-#endif
-
- odm_CommonInfoSelfInit(pDM_Odm);
- odm_DIGInit(pDM_Odm);
- Phydm_NHMCounterStatisticsInit(pDM_Odm);
- Phydm_AdaptivityInit(pDM_Odm);
- phydm_ra_info_init(pDM_Odm);
- odm_RateAdaptiveMaskInit(pDM_Odm);
- ODM_CfoTrackingInit(pDM_Odm);
- ODM_EdcaTurboInit(pDM_Odm);
- odm_RSSIMonitorInit(pDM_Odm);
- phydm_rf_init(pDM_Odm);
- odm_TXPowerTrackingInit(pDM_Odm);
- odm_AntennaDiversityInit(pDM_Odm);
- odm_AutoChannelSelectInit(pDM_Odm);
- odm_PathDiversityInit(pDM_Odm);
- odm_DynamicTxPowerInit(pDM_Odm);
- phydm_initRaInfo(pDM_Odm);
-
-#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
-#ifdef BEAMFORMING_VERSION_1
- if (pHalData->BeamformingVersion == BEAMFORMING_VERSION_1)
+#if (RTL8822B_SUPPORT == 1)
+ if (dm->support_ic_type & ODM_RTL8822B)
+ phydm_hwsetting_8822b(dm);
#endif
- {
- phydm_Beamforming_Init(pDM_Odm);
- }
-#endif
- if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
- {
- odm_DynamicBBPowerSavingInit(pDM_Odm);
+#if (RTL8812A_SUPPORT == 1)
+ if (dm->support_ic_type & ODM_RTL8812)
+ phydm_hwsetting_8812a(dm);
+#endif
-#if (RTL8188E_SUPPORT == 1)
- if(pDM_Odm->SupportICType==ODM_RTL8188E)
- {
- ODM_PrimaryCCA_Init(pDM_Odm);
- ODM_RAInfo_Init_all(pDM_Odm);
- }
+#if (RTL8197F_SUPPORT == 1)
+ if (dm->support_ic_type & ODM_RTL8197F)
+ phydm_hwsetting_8197f(dm);
#endif
+}
-#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
-
- #if (RTL8723B_SUPPORT == 1)
- if(pDM_Odm->SupportICType == ODM_RTL8723B)
- odm_SwAntDetectInit(pDM_Odm);
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
+u64
+phydm_supportability_init_win(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ u64 support_ability = 0;
+
+ switch (dm->support_ic_type) {
+ /*---------------N Series--------------------*/
+ #if (RTL8188E_SUPPORT == 1)
+ case ODM_RTL8188E:
+ support_ability |=
+ ODM_BB_DIG |
+ ODM_BB_RA_MASK |
+ /*ODM_BB_DYNAMIC_TXPWR |*/
+ ODM_BB_FA_CNT |
+ ODM_BB_RSSI_MONITOR |
+ ODM_BB_CCK_PD |
+ /*ODM_BB_PWR_TRAIN |*/
+ ODM_BB_RATE_ADAPTIVE |
+ ODM_BB_CFO_TRACKING |
+ ODM_BB_ENV_MONITOR |
+ ODM_BB_PRIMARY_CCA;
+ break;
#endif
#if (RTL8192E_SUPPORT == 1)
- if(pDM_Odm->SupportICType==ODM_RTL8192E)
- odm_PrimaryCCA_Check_Init(pDM_Odm);
+ case ODM_RTL8192E:
+ support_ability |=
+ ODM_BB_DIG |
+ ODM_BB_RA_MASK |
+ /*ODM_BB_DYNAMIC_TXPWR |*/
+ ODM_BB_FA_CNT |
+ ODM_BB_RSSI_MONITOR |
+ ODM_BB_CCK_PD |
+ /*ODM_BB_PWR_TRAIN |*/
+ ODM_BB_RATE_ADAPTIVE |
+ ODM_BB_CFO_TRACKING |
+ ODM_BB_ENV_MONITOR |
+ ODM_BB_PRIMARY_CCA;
+ break;
#endif
-#endif
-
- }
+ #if (RTL8723B_SUPPORT == 1)
+ case ODM_RTL8723B:
+ support_ability |=
+ ODM_BB_DIG |
+ ODM_BB_RA_MASK |
+ /*ODM_BB_DYNAMIC_TXPWR |*/
+ ODM_BB_FA_CNT |
+ ODM_BB_RSSI_MONITOR |
+ ODM_BB_CCK_PD |
+ /*ODM_BB_PWR_TRAIN |*/
+ ODM_BB_RATE_ADAPTIVE |
+ ODM_BB_CFO_TRACKING |
+ ODM_BB_ENV_MONITOR |
+ ODM_BB_PRIMARY_CCA;
+ break;
+ #endif
+
+ #if (RTL8703B_SUPPORT == 1)
+ case ODM_RTL8703B:
+ support_ability |=
+ ODM_BB_DIG |
+ ODM_BB_RA_MASK |
+ /*ODM_BB_DYNAMIC_TXPWR |*/
+ ODM_BB_FA_CNT |
+ ODM_BB_RSSI_MONITOR |
+ ODM_BB_CCK_PD |
+ /*ODM_BB_PWR_TRAIN |*/
+ ODM_BB_RATE_ADAPTIVE |
+ ODM_BB_CFO_TRACKING |
+ ODM_BB_ENV_MONITOR;
+ break;
+ #endif
+
+ #if (RTL8723D_SUPPORT == 1)
+ case ODM_RTL8723D:
+ support_ability |=
+ ODM_BB_DIG |
+ ODM_BB_RA_MASK |
+ /*ODM_BB_DYNAMIC_TXPWR |*/
+ ODM_BB_FA_CNT |
+ ODM_BB_RSSI_MONITOR |
+ ODM_BB_CCK_PD |
+ /* ODM_BB_PWR_TRAIN | */
+ ODM_BB_RATE_ADAPTIVE |
+ ODM_BB_CFO_TRACKING |
+ ODM_BB_ENV_MONITOR;
+ break;
+ #endif
+
+ #if (RTL8710B_SUPPORT == 1)
+ case ODM_RTL8710B:
+ support_ability |=
+ ODM_BB_DIG |
+ ODM_BB_RA_MASK |
+ /*ODM_BB_DYNAMIC_TXPWR |*/
+ ODM_BB_FA_CNT |
+ ODM_BB_RSSI_MONITOR |
+ ODM_BB_CCK_PD |
+ /*ODM_BB_PWR_TRAIN |*/
+ ODM_BB_RATE_ADAPTIVE |
+ ODM_BB_CFO_TRACKING |
+ ODM_BB_ENV_MONITOR;
+ break;
+ #endif
+ #if (RTL8188F_SUPPORT == 1)
+ case ODM_RTL8188F:
+ support_ability |=
+ ODM_BB_DIG |
+ ODM_BB_RA_MASK |
+ /*ODM_BB_DYNAMIC_TXPWR |*/
+ ODM_BB_FA_CNT |
+ ODM_BB_RSSI_MONITOR |
+ ODM_BB_CCK_PD |
+ /*ODM_BB_PWR_TRAIN |*/
+ ODM_BB_RATE_ADAPTIVE |
+ ODM_BB_CFO_TRACKING |
+ ODM_BB_ENV_MONITOR;
+ break;
+ #endif
+
+ /*---------------AC Series-------------------*/
+
+ #if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
+ case ODM_RTL8812:
+ case ODM_RTL8821:
+ support_ability |=
+ ODM_BB_DIG |
+ ODM_BB_RA_MASK |
+ ODM_BB_DYNAMIC_TXPWR |
+ ODM_BB_FA_CNT |
+ ODM_BB_RSSI_MONITOR |
+ ODM_BB_CCK_PD |
+ /*ODM_BB_PWR_TRAIN |*/
+ ODM_BB_RATE_ADAPTIVE |
+ ODM_BB_CFO_TRACKING |
+ ODM_BB_ENV_MONITOR;
+ break;
+ #endif
+
+ #if (RTL8814A_SUPPORT == 1)
+ case ODM_RTL8814A:
+ support_ability |=
+ ODM_BB_DIG |
+ ODM_BB_RA_MASK |
+ ODM_BB_DYNAMIC_TXPWR |
+ ODM_BB_FA_CNT |
+ ODM_BB_RSSI_MONITOR |
+ ODM_BB_CCK_PD |
+ /*ODM_BB_PWR_TRAIN |*/
+ ODM_BB_RATE_ADAPTIVE |
+ ODM_BB_CFO_TRACKING |
+ ODM_BB_ENV_MONITOR;
+ break;
+ #endif
+
+ #if (RTL8814B_SUPPORT == 1)
+ case ODM_RTL8814B:
+ support_ability |=
+ ODM_BB_DIG |
+ ODM_BB_RA_MASK |
+ /*ODM_BB_DYNAMIC_TXPWR |*/
+ ODM_BB_FA_CNT |
+ ODM_BB_RSSI_MONITOR |
+ ODM_BB_CCK_PD |
+ /*ODM_BB_PWR_TRAIN |*/
+ ODM_BB_RATE_ADAPTIVE |
+ ODM_BB_CFO_TRACKING |
+ ODM_BB_ENV_MONITOR;
+ break;
+ #endif
+
+ #if (RTL8822B_SUPPORT == 1)
+ case ODM_RTL8822B:
+ support_ability |=
+ ODM_BB_DIG |
+ ODM_BB_RA_MASK |
+ /*ODM_BB_DYNAMIC_TXPWR |*/
+ ODM_BB_FA_CNT |
+ ODM_BB_RSSI_MONITOR |
+ ODM_BB_CCK_PD |
+ /*ODM_BB_PWR_TRAIN |*/
+ ODM_BB_RATE_ADAPTIVE |
+ ODM_BB_CFO_TRACKING |
+ ODM_BB_ENV_MONITOR |
+ ODM_BB_ADAPTIVE_SOML;
+ break;
+ #endif
+
+ #if (RTL8821C_SUPPORT == 1)
+ case ODM_RTL8821C:
+ support_ability |=
+ ODM_BB_DIG |
+ ODM_BB_RA_MASK |
+ /*ODM_BB_DYNAMIC_TXPWR |*/
+ ODM_BB_FA_CNT |
+ ODM_BB_RSSI_MONITOR |
+ ODM_BB_CCK_PD |
+ /*ODM_BB_PWR_TRAIN |*/
+ ODM_BB_RATE_ADAPTIVE |
+ ODM_BB_CFO_TRACKING |
+ ODM_BB_ENV_MONITOR;
+ break;
+ #endif
+
+ default:
+ support_ability |=
+ ODM_BB_DIG |
+ ODM_BB_RA_MASK |
+ /*ODM_BB_DYNAMIC_TXPWR |*/
+ ODM_BB_FA_CNT |
+ ODM_BB_RSSI_MONITOR |
+ ODM_BB_CCK_PD |
+ /*ODM_BB_PWR_TRAIN |*/
+ ODM_BB_RATE_ADAPTIVE |
+ ODM_BB_CFO_TRACKING |
+ ODM_BB_ENV_MONITOR;
+
+ pr_debug("[Warning] Supportability Init Warning !!!\n");
+ break;
+
+ }
+
+ return support_ability;
}
+#endif
-VOID
-ODM_DMReset(
- IN PDM_ODM_T pDM_Odm
- )
+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
+u64
+phydm_supportability_init_ce(
+ void *dm_void
+)
{
- pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ u64 support_ability = 0;
+
+ switch (dm->support_ic_type) {
+ /*---------------N Series--------------------*/
+ #if (RTL8188E_SUPPORT == 1)
+ case ODM_RTL8188E:
+ support_ability |=
+ ODM_BB_DIG |
+ ODM_BB_RA_MASK |
+ /*ODM_BB_DYNAMIC_TXPWR |*/
+ ODM_BB_FA_CNT |
+ ODM_BB_RSSI_MONITOR |
+ ODM_BB_CCK_PD |
+ /*ODM_BB_PWR_TRAIN |*/
+ ODM_BB_RATE_ADAPTIVE |
+ ODM_BB_CFO_TRACKING |
+ ODM_BB_ENV_MONITOR |
+ ODM_BB_PRIMARY_CCA;
+ break;
+ #endif
+
+ #if (RTL8192E_SUPPORT == 1)
+ case ODM_RTL8192E:
+ support_ability |=
+ ODM_BB_DIG |
+ ODM_BB_RA_MASK |
+ /*ODM_BB_DYNAMIC_TXPWR |*/
+ ODM_BB_FA_CNT |
+ ODM_BB_RSSI_MONITOR |
+ ODM_BB_CCK_PD |
+ /*ODM_BB_PWR_TRAIN |*/
+ ODM_BB_RATE_ADAPTIVE |
+ ODM_BB_CFO_TRACKING |
+ ODM_BB_ENV_MONITOR |
+ ODM_BB_PRIMARY_CCA;
+ break;
+ #endif
+
+ #if (RTL8723B_SUPPORT == 1)
+ case ODM_RTL8723B:
+ support_ability |=
+ ODM_BB_DIG |
+ ODM_BB_RA_MASK |
+ /*ODM_BB_DYNAMIC_TXPWR |*/
+ ODM_BB_FA_CNT |
+ ODM_BB_RSSI_MONITOR |
+ ODM_BB_CCK_PD |
+ /*ODM_BB_PWR_TRAIN |*/
+ ODM_BB_RATE_ADAPTIVE |
+ ODM_BB_CFO_TRACKING |
+ ODM_BB_ENV_MONITOR |
+ ODM_BB_PRIMARY_CCA;
+ break;
+ #endif
+
+ #if (RTL8703B_SUPPORT == 1)
+ case ODM_RTL8703B:
+ support_ability |=
+ ODM_BB_DIG |
+ ODM_BB_RA_MASK |
+ /*ODM_BB_DYNAMIC_TXPWR |*/
+ ODM_BB_FA_CNT |
+ ODM_BB_RSSI_MONITOR |
+ ODM_BB_CCK_PD |
+ /*ODM_BB_PWR_TRAIN |*/
+ ODM_BB_RATE_ADAPTIVE |
+ ODM_BB_CFO_TRACKING |
+ ODM_BB_ENV_MONITOR;
+ break;
+ #endif
+
+ #if (RTL8723D_SUPPORT == 1)
+ case ODM_RTL8723D:
+ support_ability |=
+ ODM_BB_DIG |
+ ODM_BB_RA_MASK |
+ /*ODM_BB_DYNAMIC_TXPWR |*/
+ ODM_BB_FA_CNT |
+ ODM_BB_RSSI_MONITOR |
+ ODM_BB_CCK_PD |
+ /* ODM_BB_PWR_TRAIN | */
+ ODM_BB_RATE_ADAPTIVE |
+ ODM_BB_CFO_TRACKING |
+ ODM_BB_ENV_MONITOR;
+ break;
+ #endif
+
+ #if (RTL8710B_SUPPORT == 1)
+ case ODM_RTL8710B:
+ support_ability |=
+ ODM_BB_DIG |
+ ODM_BB_RA_MASK |
+ /*ODM_BB_DYNAMIC_TXPWR |*/
+ ODM_BB_FA_CNT |
+ ODM_BB_RSSI_MONITOR |
+ ODM_BB_CCK_PD |
+ /*ODM_BB_PWR_TRAIN |*/
+ ODM_BB_RATE_ADAPTIVE |
+ ODM_BB_CFO_TRACKING |
+ ODM_BB_ENV_MONITOR;
+ break;
+ #endif
+
+ #if (RTL8188F_SUPPORT == 1)
+ case ODM_RTL8188F:
+ support_ability |=
+ ODM_BB_DIG |
+ ODM_BB_RA_MASK |
+ /*ODM_BB_DYNAMIC_TXPWR |*/
+ ODM_BB_FA_CNT |
+ ODM_BB_RSSI_MONITOR |
+ ODM_BB_CCK_PD |
+ /*ODM_BB_PWR_TRAIN |*/
+ ODM_BB_RATE_ADAPTIVE |
+ ODM_BB_CFO_TRACKING |
+ ODM_BB_ENV_MONITOR;
+ break;
+ #endif
+
+ /*---------------AC Series-------------------*/
+
+ #if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1))
+ case ODM_RTL8812:
+ case ODM_RTL8821:
+ support_ability |=
+ ODM_BB_DIG |
+ ODM_BB_RA_MASK |
+ /*ODM_BB_DYNAMIC_TXPWR |*/
+ ODM_BB_FA_CNT |
+ ODM_BB_RSSI_MONITOR |
+ ODM_BB_CCK_PD |
+ /*ODM_BB_PWR_TRAIN |*/
+ ODM_BB_RATE_ADAPTIVE |
+ ODM_BB_CFO_TRACKING |
+ ODM_BB_ENV_MONITOR;
+ break;
+ #endif
- ODM_AntDivReset(pDM_Odm);
- phydm_setEDCCAThresholdAPI(pDM_Odm, pDM_DigTable->CurIGValue);
+ #if (RTL8814A_SUPPORT == 1)
+ case ODM_RTL8814A:
+ support_ability |=
+ ODM_BB_DIG |
+ ODM_BB_RA_MASK |
+ /*ODM_BB_DYNAMIC_TXPWR |*/
+ ODM_BB_FA_CNT |
+ ODM_BB_RSSI_MONITOR |
+ ODM_BB_CCK_PD |
+ /*ODM_BB_PWR_TRAIN |*/
+ ODM_BB_RATE_ADAPTIVE |
+ ODM_BB_CFO_TRACKING |
+ ODM_BB_ENV_MONITOR;
+ break;
+ #endif
+
+ #if (RTL8814B_SUPPORT == 1)
+ case ODM_RTL8814B:
+ support_ability |=
+ ODM_BB_DIG |
+ ODM_BB_RA_MASK |
+ /*ODM_BB_DYNAMIC_TXPWR |*/
+ ODM_BB_FA_CNT |
+ ODM_BB_RSSI_MONITOR |
+ ODM_BB_CCK_PD |
+ /*ODM_BB_PWR_TRAIN |*/
+ ODM_BB_RATE_ADAPTIVE |
+ ODM_BB_CFO_TRACKING |
+ ODM_BB_ENV_MONITOR;
+ break;
+ #endif
+
+ #if (RTL8822B_SUPPORT == 1)
+ case ODM_RTL8822B:
+ support_ability |=
+ ODM_BB_DIG |
+ ODM_BB_RA_MASK |
+ /*ODM_BB_DYNAMIC_TXPWR |*/
+ ODM_BB_FA_CNT |
+ ODM_BB_RSSI_MONITOR |
+ ODM_BB_CCK_PD |
+ /*ODM_BB_PWR_TRAIN |*/
+ ODM_BB_RATE_ADAPTIVE |
+ ODM_BB_CFO_TRACKING |
+ ODM_BB_ENV_MONITOR;
+ break;
+ #endif
+
+ #if (RTL8821C_SUPPORT == 1)
+ case ODM_RTL8821C:
+ support_ability |=
+ ODM_BB_DIG |
+ ODM_BB_RA_MASK |
+ /*ODM_BB_DYNAMIC_TXPWR |*/
+ ODM_BB_FA_CNT |
+ ODM_BB_RSSI_MONITOR |
+ ODM_BB_CCK_PD |
+ /*ODM_BB_PWR_TRAIN |*/
+ ODM_BB_RATE_ADAPTIVE |
+ ODM_BB_CFO_TRACKING |
+ ODM_BB_ENV_MONITOR;
+ break;
+ #endif
+
+ default:
+ support_ability |=
+ ODM_BB_DIG |
+ ODM_BB_RA_MASK |
+ /*ODM_BB_DYNAMIC_TXPWR |*/
+ ODM_BB_FA_CNT |
+ ODM_BB_RSSI_MONITOR |
+ ODM_BB_CCK_PD |
+ /*ODM_BB_PWR_TRAIN |*/
+ ODM_BB_RATE_ADAPTIVE |
+ ODM_BB_CFO_TRACKING |
+ ODM_BB_ENV_MONITOR;
+
+ pr_debug("[Warning] Supportability Init Warning !!!\n");
+ break;
+
+ }
+
+ return support_ability;
}
+#endif
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+u64
+phydm_supportability_init_ap(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ u64 support_ability = 0;
+
+ switch (dm->support_ic_type) {
+ /*---------------N Series--------------------*/
+ #if (RTL8188E_SUPPORT == 1)
+ case ODM_RTL8188E:
+ support_ability |=
+ ODM_BB_DIG |
+ ODM_BB_RA_MASK |
+ ODM_BB_FA_CNT |
+ ODM_BB_RSSI_MONITOR |
+ ODM_BB_CCK_PD |
+ /*ODM_BB_PWR_TRAIN |*/
+ ODM_BB_RATE_ADAPTIVE |
+ ODM_BB_CFO_TRACKING |
+ ODM_BB_ENV_MONITOR |
+ ODM_BB_PRIMARY_CCA;
+ break;
+ #endif
-VOID
+ #if (RTL8192E_SUPPORT == 1)
+ case ODM_RTL8192E:
+ support_ability |=
+ ODM_BB_DIG |
+ ODM_BB_RA_MASK |
+ ODM_BB_FA_CNT |
+ ODM_BB_RSSI_MONITOR |
+ ODM_BB_CCK_PD |
+ /*ODM_BB_PWR_TRAIN |*/
+ ODM_BB_RATE_ADAPTIVE |
+ ODM_BB_CFO_TRACKING |
+ ODM_BB_ENV_MONITOR |
+ ODM_BB_PRIMARY_CCA;
+ break;
+ #endif
+
+ #if (RTL8723B_SUPPORT == 1)
+ case ODM_RTL8723B:
+ support_ability |=
+ ODM_BB_DIG |
+ ODM_BB_RA_MASK |
+ ODM_BB_FA_CNT |
+ ODM_BB_RSSI_MONITOR |
+ ODM_BB_CCK_PD |
+ /*ODM_BB_PWR_TRAIN |*/
+ ODM_BB_RATE_ADAPTIVE |
+ ODM_BB_CFO_TRACKING |
+ ODM_BB_ENV_MONITOR;
+ break;
+ #endif
+
+ #if ((RTL8198F_SUPPORT == 1) || (RTL8197F_SUPPORT == 1))
+ case ODM_RTL8198F:
+ case ODM_RTL8197F:
+ support_ability |=
+ ODM_BB_DIG |
+ ODM_BB_RA_MASK |
+ ODM_BB_FA_CNT |
+ ODM_BB_RSSI_MONITOR |
+ ODM_BB_CCK_PD |
+ /*ODM_BB_PWR_TRAIN |*/
+ ODM_BB_RATE_ADAPTIVE |
+ ODM_BB_CFO_TRACKING |
+ ODM_BB_ADAPTIVE_SOML |
+ ODM_BB_ENV_MONITOR |
+ ODM_BB_LNA_SAT_CHK |
+ ODM_BB_PRIMARY_CCA;
+ break;
+ #endif
+
+ /*---------------AC Series-------------------*/
+
+ #if (RTL8881A_SUPPORT == 1)
+ case ODM_RTL8881A:
+ support_ability |=
+ ODM_BB_DIG |
+ ODM_BB_RA_MASK |
+ ODM_BB_FA_CNT |
+ ODM_BB_RSSI_MONITOR |
+ ODM_BB_CCK_PD |
+ /*ODM_BB_PWR_TRAIN |*/
+ ODM_BB_RATE_ADAPTIVE |
+ ODM_BB_CFO_TRACKING |
+ ODM_BB_ENV_MONITOR;
+ break;
+ #endif
+
+ #if (RTL8814A_SUPPORT == 1)
+ case ODM_RTL8814A:
+ support_ability |=
+ ODM_BB_DIG |
+ ODM_BB_RA_MASK |
+ ODM_BB_FA_CNT |
+ ODM_BB_RSSI_MONITOR |
+ ODM_BB_CCK_PD |
+ /*ODM_BB_PWR_TRAIN |*/
+ ODM_BB_RATE_ADAPTIVE |
+ ODM_BB_CFO_TRACKING |
+ ODM_BB_ENV_MONITOR;
+ break;
+ #endif
+
+ #if (RTL8814B_SUPPORT == 1)
+ case ODM_RTL8814B:
+ support_ability |=
+ ODM_BB_DIG |
+ ODM_BB_RA_MASK |
+ ODM_BB_FA_CNT |
+ ODM_BB_RSSI_MONITOR |
+ ODM_BB_CCK_PD |
+ /*ODM_BB_PWR_TRAIN |*/
+ ODM_BB_RATE_ADAPTIVE |
+ ODM_BB_CFO_TRACKING |
+ ODM_BB_ENV_MONITOR;
+ break;
+ #endif
+
+ #if (RTL8822B_SUPPORT == 1)
+ case ODM_RTL8822B:
+ support_ability |=
+ ODM_BB_DIG |
+ ODM_BB_RA_MASK |
+ ODM_BB_FA_CNT |
+ ODM_BB_RSSI_MONITOR |
+ ODM_BB_CCK_PD |
+ /*ODM_BB_PWR_TRAIN |*/
+ /*ODM_BB_ADAPTIVE_SOML |*/
+ ODM_BB_RATE_ADAPTIVE |
+ ODM_BB_CFO_TRACKING |
+ ODM_BB_ENV_MONITOR ;
+ break;
+ #endif
+
+ #if (RTL8821C_SUPPORT == 1)
+ case ODM_RTL8821C:
+ support_ability |=
+ ODM_BB_DIG |
+ ODM_BB_RA_MASK |
+ ODM_BB_FA_CNT |
+ ODM_BB_RSSI_MONITOR |
+ ODM_BB_CCK_PD |
+ /*ODM_BB_PWR_TRAIN |*/
+ ODM_BB_RATE_ADAPTIVE |
+ ODM_BB_CFO_TRACKING |
+ ODM_BB_ENV_MONITOR;
+
+ break;
+ #endif
+
+ default:
+ support_ability |=
+ ODM_BB_DIG |
+ ODM_BB_RA_MASK |
+ ODM_BB_FA_CNT |
+ ODM_BB_RSSI_MONITOR |
+ ODM_BB_CCK_PD |
+ /*ODM_BB_PWR_TRAIN |*/
+ ODM_BB_RATE_ADAPTIVE |
+ ODM_BB_CFO_TRACKING |
+ ODM_BB_ENV_MONITOR;
+
+ pr_debug("[Warning] Supportability Init Warning !!!\n");
+ break;
+
+ }
+
+ #if 0
+ /*[Config Antenna Diveristy]*/
+ if (*(dm->enable_antdiv))
+ support_ability |= ODM_BB_ANT_DIV;
+
+ /*[Config Adaptivity]*/
+ if (*(dm->enable_adaptivity))
+ support_ability |= ODM_BB_ADAPTIVITY;
+ #endif
+
+ return support_ability;
+}
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_IOT))
+u64
+phydm_supportability_init_iot(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ u64 support_ability = 0;
+
+ switch (dm->support_ic_type) {
+ #if (RTL8710B_SUPPORT == 1)
+ case ODM_RTL8710B:
+ support_ability |=
+ ODM_BB_DIG |
+ ODM_BB_RA_MASK |
+ /*ODM_BB_DYNAMIC_TXPWR |*/
+ ODM_BB_FA_CNT |
+ ODM_BB_RSSI_MONITOR |
+ ODM_BB_CCK_PD |
+ /*ODM_BB_PWR_TRAIN |*/
+ ODM_BB_RATE_ADAPTIVE |
+ ODM_BB_CFO_TRACKING |
+ ODM_BB_ENV_MONITOR;
+ break;
+ #endif
+
+ #if (RTL8195A_SUPPORT == 1)
+ case ODM_RTL8195A:
+ support_ability |=
+ ODM_BB_DIG |
+ ODM_BB_RA_MASK |
+ /*ODM_BB_DYNAMIC_TXPWR |*/
+ ODM_BB_FA_CNT |
+ ODM_BB_RSSI_MONITOR |
+ ODM_BB_CCK_PD |
+ /*ODM_BB_PWR_TRAIN |*/
+ ODM_BB_RATE_ADAPTIVE |
+ ODM_BB_CFO_TRACKING |
+ ODM_BB_ENV_MONITOR;
+ break;
+ #endif
+
+ default:
+ support_ability |=
+ ODM_BB_DIG |
+ ODM_BB_RA_MASK |
+ /*ODM_BB_DYNAMIC_TXPWR |*/
+ ODM_BB_FA_CNT |
+ ODM_BB_RSSI_MONITOR |
+ ODM_BB_CCK_PD |
+ /*ODM_BB_PWR_TRAIN |*/
+ ODM_BB_RATE_ADAPTIVE |
+ ODM_BB_CFO_TRACKING |
+ ODM_BB_ENV_MONITOR;
+
+ pr_debug("[Warning] Supportability Init Warning !!!\n");
+ break;
+
+ }
+
+ return support_ability;
+}
+#endif
+
+void
+phydm_fwoffload_ability_init(
+ struct dm_struct *dm,
+ enum phydm_offload_ability offload_ability
+)
+{
+ switch (offload_ability) {
+ case PHYDM_PHY_PARAM_OFFLOAD:
+ if (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
+ dm->fw_offload_ability |= PHYDM_PHY_PARAM_OFFLOAD;
+ break;
+
+ case PHYDM_RF_IQK_OFFLOAD:
+ dm->fw_offload_ability |= PHYDM_RF_IQK_OFFLOAD;
+ break;
+
+ default:
+ PHYDM_DBG(dm, ODM_COMP_INIT, "fwofflad, wrong init type!!\n");
+ break;
+
+ }
+
+ PHYDM_DBG(dm, ODM_COMP_INIT,
+ "fw_offload_ability = %x\n", dm->fw_offload_ability);
+
+}
+void
+phydm_fwoffload_ability_clear(
+ struct dm_struct *dm,
+ enum phydm_offload_ability offload_ability
+)
+{
+ switch (offload_ability) {
+ case PHYDM_PHY_PARAM_OFFLOAD:
+ if (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C))
+ dm->fw_offload_ability &= (~PHYDM_PHY_PARAM_OFFLOAD);
+ break;
+
+ case PHYDM_RF_IQK_OFFLOAD:
+ dm->fw_offload_ability &= (~PHYDM_RF_IQK_OFFLOAD);
+ break;
+
+ default:
+ PHYDM_DBG(dm, ODM_COMP_INIT, "fwofflad, wrong init type!!\n");
+ break;
+
+ }
+
+ PHYDM_DBG(dm, ODM_COMP_INIT,
+ "fw_offload_ability = %x\n", dm->fw_offload_ability);
+
+}
+
+void
+phydm_supportability_init(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ u64 support_ability;
+
+ if (*dm->mp_mode == true) {
+ support_ability = 0;
+
+ /**/
+ } else {
+ #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
+ support_ability = phydm_supportability_init_win(dm);
+ #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+ support_ability = phydm_supportability_init_ap(dm);
+ #elif(DM_ODM_SUPPORT_TYPE & (ODM_CE))
+ support_ability = phydm_supportability_init_ce(dm);
+ #elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT))
+ support_ability = phydm_supportability_init_iot(dm);
+ #endif
+
+ /*[Config Antenna Diveristy]*/
+ if (IS_FUNC_EN(dm->enable_antdiv))
+ support_ability |= ODM_BB_ANT_DIV;
+
+ /*[Config Adaptive SOML]*/
+ if (IS_FUNC_EN(dm->en_adap_soml))
+ support_ability |= ODM_BB_ADAPTIVE_SOML;
+
+ /*[Config Adaptivity]*/
+ if (IS_FUNC_EN(dm->enable_adaptivity))
+ support_ability |= ODM_BB_ADAPTIVITY;
+ }
+ odm_cmn_info_init(dm, ODM_CMNINFO_ABILITY, support_ability);
+ PHYDM_DBG(dm, ODM_COMP_INIT, "IC = ((0x%x)), Supportability Init = ((0x%llx))\n", dm->support_ic_type, dm->support_ability);
+}
+
+void
+phydm_rfe_init(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+ PHYDM_DBG(dm, ODM_COMP_INIT, "RFE_Init\n");
+#if (RTL8822B_SUPPORT == 1)
+ if (dm->support_ic_type == ODM_RTL8822B) {
+ phydm_rfe_8822b_init(dm);
+ /**/
+ }
+#endif
+}
+
+void
+phydm_dm_early_init(
+ struct dm_struct *dm
+)
+{
+ #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+ halrf_init(dm);
+ #endif
+}
+
+void
+odm_dm_init(
+ struct dm_struct *dm
+)
+{
+ halrf_init(dm);
+ phydm_supportability_init(dm);
+ phydm_rfe_init(dm);
+ phydm_common_info_self_init(dm);
+ phydm_rx_phy_status_init(dm);
+ phydm_auto_dbg_engine_init(dm);
+ phydm_dig_init(dm);
+ phydm_cck_pd_init(dm);
+ phydm_env_monitor_init(dm);
+ phydm_adaptivity_init(dm);
+ phydm_ra_info_init(dm);
+ phydm_rssi_monitor_init(dm);
+ phydm_cfo_tracking_init(dm);
+ phydm_rf_init(dm);
+ phydm_dc_cancellation(dm);
+#ifdef PHYDM_TXA_CALIBRATION
+ phydm_txcurrentcalibration(dm);
+ phydm_get_pa_bias_offset(dm);
+#endif
+ odm_antenna_diversity_init(dm);
+ phydm_adaptive_soml_init(dm);
+#ifdef CONFIG_DYNAMIC_RX_PATH
+ phydm_dynamic_rx_path_init(dm);
+#endif
+ phydm_path_diversity_init(dm);
+ phydm_pow_train_init(dm);
+ phydm_dynamic_tx_power_init(dm);
+#if (PHYDM_LA_MODE_SUPPORT == 1)
+ adc_smp_init(dm);
+#endif
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+ phydm_beamforming_init(dm);
+#endif
+#if (RTL8188E_SUPPORT == 1)
+ odm_ra_info_init_all(dm);
+#endif
+
+ phydm_primary_cca_init(dm);
+
+ #ifdef CONFIG_PSD_TOOL
+ phydm_psd_init(dm);
+ #endif
+
+ #ifdef CONFIG_SMART_ANTENNA
+ phydm_smt_ant_init(dm);
+ #endif
+
+}
+
+void
+odm_dm_reset(
+ struct dm_struct *dm
+)
+{
+ struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
+
+ odm_ant_div_reset(dm);
+ phydm_set_edcca_threshold_api(dm, dig_t->cur_ig_value);
+}
+
+void
phydm_support_ability_debug(
- IN PVOID pDM_VOID,
- IN u4Byte *const dm_value,
- IN u4Byte *_used,
- OUT char *output,
- IN u4Byte *_out_len
- )
+ void *dm_void,
+ u32 *const dm_value,
+ u32 *_used,
+ char *output,
+ u32 *_out_len
+)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- u4Byte pre_support_ability;
- u4Byte used = *_used;
- u4Byte out_len = *_out_len;
-
- pre_support_ability = pDM_Odm->SupportAbility ;
- PHYDM_SNPRINTF((output+used, out_len-used,"\n%s\n", "================================"));
- if(dm_value[0] == 100)
- {
- PHYDM_SNPRINTF((output+used, out_len-used, "[Supportability] PhyDM Selection\n"));
- PHYDM_SNPRINTF((output+used, out_len-used,"%s\n", "================================"));
- PHYDM_SNPRINTF((output+used, out_len-used, "00. (( %s ))DIG\n", ((pDM_Odm->SupportAbility & ODM_BB_DIG)?("V"):("."))));
- PHYDM_SNPRINTF((output+used, out_len-used, "01. (( %s ))RA_MASK\n", ((pDM_Odm->SupportAbility & ODM_BB_RA_MASK)?("V"):("."))));
- PHYDM_SNPRINTF((output+used, out_len-used, "02. (( %s ))DYNAMIC_TXPWR\n", ((pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR)?("V"):("."))));
- PHYDM_SNPRINTF((output+used, out_len-used, "03. (( %s ))FA_CNT\n", ((pDM_Odm->SupportAbility & ODM_BB_FA_CNT)?("V"):("."))));
- PHYDM_SNPRINTF((output+used, out_len-used, "04. (( %s ))RSSI_MONITOR\n", ((pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR)?("V"):("."))));
- PHYDM_SNPRINTF((output+used, out_len-used, "05. (( %s ))CCK_PD\n", ((pDM_Odm->SupportAbility & ODM_BB_CCK_PD)?("V"):("."))));
- PHYDM_SNPRINTF((output+used, out_len-used, "06. (( %s ))ANT_DIV\n", ((pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)?("V"):("."))));
- PHYDM_SNPRINTF((output+used, out_len-used, "08. (( %s ))PWR_TRAIN\n", ((pDM_Odm->SupportAbility & ODM_BB_PWR_TRAIN)?("V"):("."))));
- PHYDM_SNPRINTF((output+used, out_len-used, "09. (( %s ))RATE_ADAPTIVE\n", ((pDM_Odm->SupportAbility & ODM_BB_RATE_ADAPTIVE)?("V"):("."))));
- PHYDM_SNPRINTF((output+used, out_len-used, "10. (( %s ))PATH_DIV\n", ((pDM_Odm->SupportAbility & ODM_BB_PATH_DIV)?("V"):("."))));
- PHYDM_SNPRINTF((output+used, out_len-used, "13. (( %s ))ADAPTIVITY\n", ((pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY)?("V"):("."))));
- PHYDM_SNPRINTF((output+used, out_len-used, "14. (( %s ))CFO_TRACKING\n", ((pDM_Odm->SupportAbility & ODM_BB_CFO_TRACKING)?("V"):("."))));
- PHYDM_SNPRINTF((output+used, out_len-used, "15. (( %s ))NHM_CNT\n", ((pDM_Odm->SupportAbility & ODM_BB_NHM_CNT)?("V"):("."))));
- PHYDM_SNPRINTF((output+used, out_len-used, "16. (( %s ))PRIMARY_CCA\n", ((pDM_Odm->SupportAbility & ODM_BB_PRIMARY_CCA)?("V"):("."))));
- PHYDM_SNPRINTF((output+used, out_len-used, "17. (( %s ))TXBF\n", ((pDM_Odm->SupportAbility & ODM_BB_TXBF)?("V"):("."))));
- PHYDM_SNPRINTF((output+used, out_len-used, "18. (( %s ))DYNAMIC_ARFR\n", ((pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_ARFR)?("V"):("."))));
- PHYDM_SNPRINTF((output+used, out_len-used, "20. (( %s ))EDCA_TURBO\n", ((pDM_Odm->SupportAbility & ODM_MAC_EDCA_TURBO)?("V"):("."))));
- PHYDM_SNPRINTF((output+used, out_len-used, "21. (( %s ))EARLY_MODE\n", ((pDM_Odm->SupportAbility & ODM_MAC_EARLY_MODE)?("V"):("."))));
- PHYDM_SNPRINTF((output+used, out_len-used, "24. (( %s ))TX_PWR_TRACK\n", ((pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK)?("V"):("."))));
- PHYDM_SNPRINTF((output+used, out_len-used, "25. (( %s ))RX_GAIN_TRACK\n", ((pDM_Odm->SupportAbility & ODM_RF_RX_GAIN_TRACK)?("V"):("."))));
- PHYDM_SNPRINTF((output+used, out_len-used, "26. (( %s ))RF_CALIBRATION\n", ((pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)?("V"):("."))));
- PHYDM_SNPRINTF((output+used, out_len-used,"%s\n", "================================"));
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ u64 pre_support_ability, one = 1;
+ u32 used = *_used;
+ u32 out_len = *_out_len;
+
+ pre_support_ability = dm->support_ability;
+
+ PDM_SNPF(out_len, used, output + used, out_len - used, "\n%s\n",
+ "================================");
+ if (dm_value[0] == 100) {
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "[Supportability] PhyDM Selection\n");
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "%s\n", "================================");
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "00. (( %s ))DIG\n",
+ ((dm->support_ability & ODM_BB_DIG) ? ("V") : (".")));
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "01. (( %s ))RA_MASK\n",
+ ((dm->support_ability & ODM_BB_RA_MASK) ? ("V") : (".")));
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "02. (( %s ))DYN_TXPWR\n",
+ ((dm->support_ability & ODM_BB_DYNAMIC_TXPWR) ? ("V") : (".")));
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "03. (( %s ))FA_CNT\n",
+ ((dm->support_ability & ODM_BB_FA_CNT) ? ("V") : (".")));
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "04. (( %s ))RSSI_MNTR\n",
+ ((dm->support_ability & ODM_BB_RSSI_MONITOR) ? ("V") : (".")));
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "05. (( %s ))CCK_PD\n",
+ ((dm->support_ability & ODM_BB_CCK_PD) ? ("V") : (".")));
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "06. (( %s ))ANT_DIV\n",
+ ((dm->support_ability & ODM_BB_ANT_DIV) ? ("V") : (".")));
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "07. (( %s ))SMT_ANT\n",
+ ((dm->support_ability & ODM_BB_SMT_ANT) ? ("V") : (".")));
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "08. (( %s ))PWR_TRAIN\n",
+ ((dm->support_ability & ODM_BB_PWR_TRAIN) ? ("V") : (".")));
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "09. (( %s ))RA\n",
+ ((dm->support_ability & ODM_BB_RATE_ADAPTIVE) ? ("V") : (".")));
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "10. (( %s ))PATH_DIV\n",
+ ((dm->support_ability & ODM_BB_PATH_DIV) ? ("V") : (".")));
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "11. (( %s ))DFS\n",
+ ((dm->support_ability & ODM_BB_DFS) ? ("V") : (".")));
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "12. (( %s ))DYN_ARFR\n",
+ ((dm->support_ability & ODM_BB_DYNAMIC_ARFR) ? ("V") : (".")));
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "13. (( %s ))ADAPTIVITY\n",
+ ((dm->support_ability & ODM_BB_ADAPTIVITY) ? ("V") : (".")));
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "14. (( %s ))CFO_TRACK\n",
+ ((dm->support_ability & ODM_BB_CFO_TRACKING) ? ("V") : (".")));
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "15. (( %s ))ENV_MONITOR\n",
+ ((dm->support_ability & ODM_BB_ENV_MONITOR) ? ("V") : (".")));
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "16. (( %s ))PRI_CCA\n",
+ ((dm->support_ability & ODM_BB_PRIMARY_CCA) ? ("V") : (".")));
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "17. (( %s ))ADPTV_SOML\n",
+ ((dm->support_ability & ODM_BB_ADAPTIVE_SOML) ? ("V") : (".")));
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "18. (( %s ))NA_SAT_CHK\n",
+ ((dm->support_ability & ODM_BB_LNA_SAT_CHK) ? ("V") : (".")));
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "19. (( %s ))DYN_RX_PATH\n",
+ ((dm->support_ability & ODM_BB_DYNAMIC_RX_PATH) ? ("V") : (".")));
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "%s\n", "================================");
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "[Supportability] PhyDM offload ability\n");
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "%s\n", "================================");
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "00. (( %s ))PHY PARAM OFFLOAD\n",
+ ((dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) ? ("V") : (".")));
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "01. (( %s ))RF IQK OFFLOAD\n",
+ ((dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? ("V") : (".")));
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "%s\n", "================================");
+
}
/*
else if(dm_value[0] == 101)
{
- pDM_Odm->SupportAbility = 0 ;
- DbgPrint("Disable all SupportAbility components \n");
- PHYDM_SNPRINTF((output+used, out_len-used,"%s\n", "Disable all SupportAbility components"));
+ dm->support_ability = 0 ;
+ dbg_print("Disable all support_ability components\n");
+ PDM_SNPF((output+used, out_len-used,"%s\n", "Disable all support_ability components"));
}
*/
- else
+ else {
+ if (dm_value[1] == 1) { /* enable */
+ dm->support_ability |= (one << dm_value[0]);
+ if (BIT(dm_value[0]) & ODM_BB_PATH_DIV)
+ phydm_path_diversity_init(dm);
+ } else if (dm_value[1] == 2) /* disable */
+ dm->support_ability &= ~(one << dm_value[0]);
+ else
+ PDM_SNPF(out_len, used, output + used,
+ out_len - used, "%s\n",
+ "[Warning!!!] 1:enable, 2:disable");
+ }
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "pre-support_ability = 0x%llx\n",
+ pre_support_ability);
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "Curr-support_ability = 0x%llx\n",
+ dm->support_ability);
+ PDM_SNPF(out_len, used, output + used, out_len - used, "%s\n",
+ "================================");
+
+ *_used = used;
+ *_out_len = out_len;
+}
+
+void
+phydm_watchdog_lps_32k(
+ struct dm_struct *dm
+)
+{
+ PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
+
+ phydm_common_info_self_update(dm);
+ phydm_rssi_monitor_check(dm);
+ phydm_dig_lps_32k(dm);
+ phydm_common_info_self_reset(dm);
+}
+
+void
+phydm_watchdog_lps(
+ struct dm_struct *dm
+)
+{
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+ PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
+
+ phydm_common_info_self_update(dm);
+ phydm_rssi_monitor_check(dm);
+ phydm_basic_dbg_message(dm);
+ phydm_receiver_blocking(dm);
+ odm_false_alarm_counter_statistics(dm);
+ phydm_dig_by_rssi_lps(dm);
+ phydm_cck_pd_th(dm);
+ phydm_adaptivity(dm);
+ #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
+ odm_antenna_diversity(dm); /*enable AntDiv in PS mode, request from SD4 Jeff*/
+ #endif
+ phydm_common_info_self_reset(dm);
+#endif
+}
+
+void
+phydm_watchdog_mp(
+ struct dm_struct *dm
+)
+{
+#ifdef CONFIG_DYNAMIC_RX_PATH
+ phydm_dynamic_rx_path_caller(dm);
+#endif
+}
+
+void
+phydm_pause_dm_watchdog(
+ void *dm_void,
+ enum phydm_pause_type pause_type
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+ if (pause_type == PHYDM_PAUSE) {
+ dm->disable_phydm_watchdog = 1;
+ PHYDM_DBG(dm, ODM_COMP_API, "PHYDM Stop\n");
+ } else {
+ dm->disable_phydm_watchdog = 0;
+ PHYDM_DBG(dm, ODM_COMP_API, "PHYDM Start\n");
+ }
+}
+
+u8
+phydm_pause_func(
+ void *dm_void,
+ enum phydm_func_idx pause_func,
+ enum phydm_pause_type pause_type,
+ enum phydm_pause_level pause_lv,
+ u8 val_lehgth,
+ u32 *val_buf
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ s8 *pause_lv_pre = &dm->s8_dummy;
+ u32 *bkp_val = &dm->u32_dummy;
+ u32 ori_val[5] = {0};
+ u64 pause_func_bitmap = (u64)BIT(pause_func);
+ u8 i;
+
+
+
+ PHYDM_DBG(dm, ODM_COMP_API, "[%s][%s] LV=%d, Len=%d\n", __func__,
+ ((pause_type == PHYDM_PAUSE) ? "Pause" : "Resume"), pause_lv, val_lehgth);
+
+ if (pause_lv >= PHYDM_PAUSE_MAX_NUM) {
+ PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] Wrong LV=%d\n", pause_lv);
+ return PAUSE_FAIL;
+ }
+
+ if (pause_func == F00_DIG) {
+ PHYDM_DBG(dm, ODM_COMP_API, "[DIG]\n");
+
+ if (val_lehgth != 1) {
+ PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] val_length != 1\n");
+ return PAUSE_FAIL;
+ }
+
+ ori_val[0] = (u32)(dm->dm_dig_table.cur_ig_value); /*0xc50*/
+ pause_lv_pre = &dm->pause_lv_table.lv_dig;
+ bkp_val = (u32*)(&dm->dm_dig_table.rvrt_val);
+ dm->phydm_func_handler.pause_phydm_handler = phydm_set_dig_val; /*function pointer hook*/
+
+ } else
+
+#ifdef PHYDM_SUPPORT_CCKPD
+ if (pause_func == F05_CCK_PD) {
+
+ PHYDM_DBG(dm, ODM_COMP_API, "[CCK_PD]\n");
+
+ if (val_lehgth != 2) {
+ PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] val_length != 2\n");
+ return PAUSE_FAIL;
+ }
+
+ ori_val[0] = dm->dm_cckpd_table.cur_cck_cca_thres; /*0xa0a*/
+ ori_val[1] = dm->dm_cckpd_table.cck_cca_th_aaa; /*0xaaa*/
+ pause_lv_pre = &dm->pause_lv_table.lv_cckpd;
+ bkp_val = &dm->dm_cckpd_table.rvrt_val[0];
+ dm->phydm_func_handler.pause_phydm_handler = phydm_set_cckpd_val; /*function pointer hook*/
+
+ } else
+#endif
+
+#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
+ if (pause_func == F06_ANT_DIV) {
+ PHYDM_DBG(dm, ODM_COMP_API, "[AntDiv]\n");
+
+ if (val_lehgth != 1) {
+ PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] val_length != 1\n");
+ return PAUSE_FAIL;
+ }
+
+ ori_val[0] = (u32)(dm->dm_fat_table.rx_idle_ant); /*default antenna*/
+ pause_lv_pre = &dm->pause_lv_table.lv_antdiv;
+ bkp_val = (u32*)(&dm->dm_fat_table.rvrt_val);
+ dm->phydm_func_handler.pause_phydm_handler = phydm_set_antdiv_val; /*function pointer hook*/
+
+ } else
+#endif
+
+ if (pause_func == F13_ADPTVTY) {
+ PHYDM_DBG(dm, ODM_COMP_API, "[Adaptivity]\n");
+
+ if (val_lehgth != 2) {
+ PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] val_length != 2\n");
+ return PAUSE_FAIL;
+ }
+
+ ori_val[0] = (u32)(dm->adaptivity.th_l2h); /*th_l2h*/
+ ori_val[1] = (u32)(dm->adaptivity.th_h2l); /*th_h2l*/
+ pause_lv_pre = &dm->pause_lv_table.lv_adapt;
+ bkp_val = (u32 *)(&dm->adaptivity.rvrt_val);
+ dm->phydm_func_handler.pause_phydm_handler = phydm_set_edcca_val; /*function pointer hook*/
+
+ } else
+
{
+ PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] error func idx\n");
+ return PAUSE_FAIL;
+ }
- if(dm_value[1] == 1) //enable
- {
- pDM_Odm->SupportAbility |= BIT(dm_value[0]) ;
- if(BIT(dm_value[0]) & ODM_BB_PATH_DIV)
- {
- odm_PathDiversityInit(pDM_Odm);
- }
+ PHYDM_DBG(dm, ODM_COMP_API, "Pause_LV{new , pre} = {%d ,%d}\n", pause_lv, *pause_lv_pre);
+
+ if ((pause_type == PHYDM_PAUSE) || (pause_type == PHYDM_PAUSE_NO_SET)) {
+ if (pause_lv <= *pause_lv_pre) {
+ PHYDM_DBG(dm, ODM_COMP_API, "[PAUSE FAIL] Pre_LV >= Curr_LV\n");
+ return PAUSE_FAIL;
}
- else if(dm_value[1] == 2) //disable
- {
- pDM_Odm->SupportAbility &= ~(BIT(dm_value[0])) ;
+
+ if (!(dm->pause_ability & pause_func_bitmap)) {
+ for (i = 0; i < val_lehgth; i ++)
+ bkp_val[i] = ori_val[i];
}
- else
- {
- //DbgPrint("\n[Warning!!!] 1:enable, 2:disable \n\n");
- PHYDM_SNPRINTF((output+used, out_len-used,"%s\n", "[Warning!!!] 1:enable, 2:disable"));
+
+ dm->pause_ability |= pause_func_bitmap;
+ PHYDM_DBG(dm, ODM_COMP_API, "pause_ability=0x%llx\n", dm->pause_ability);
+
+ if (pause_type == PHYDM_PAUSE) {
+ for (i = 0; i < val_lehgth; i ++) {
+ PHYDM_DBG(dm, ODM_COMP_API, "[PAUSE SUCCESS] val_idx[%d]{New, Ori}={0x%x, 0x%x}\n",i, val_buf[i], bkp_val[i]);
+ /**/
+ }
+ dm->phydm_func_handler.pause_phydm_handler(dm, val_buf, val_lehgth);
+ } else {
+ for (i = 0; i < val_lehgth; i ++) {
+ PHYDM_DBG(dm, ODM_COMP_API, "[PAUSE NO Set: SUCCESS] val_idx[%d]{Ori}={0x%x}\n",i, bkp_val[i]);
+ /**/
+ }
}
+
+ *pause_lv_pre = pause_lv;
+ return PAUSE_SUCCESS;
+
+ } else if (pause_type == PHYDM_RESUME) {
+ dm->pause_ability &= ~pause_func_bitmap;
+ PHYDM_DBG(dm, ODM_COMP_API, "pause_ability=0x%llx\n", dm->pause_ability);
+
+ *pause_lv_pre = PHYDM_PAUSE_RELEASE;
+
+ for (i = 0; i < val_lehgth; i ++) {
+ PHYDM_DBG(dm, ODM_COMP_API, "[RESUME] val_idx[%d]={0x%x}\n", i, bkp_val[i]);
+ }
+
+ dm->phydm_func_handler.pause_phydm_handler(dm, bkp_val, val_lehgth);
+
+ return PAUSE_SUCCESS;
+ } else {
+ PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] error pause_type\n");
+ return PAUSE_FAIL;
}
- PHYDM_SNPRINTF((output+used, out_len-used,"pre-SupportAbility = 0x%x\n", pre_support_ability ));
- PHYDM_SNPRINTF((output+used, out_len-used,"Curr-SupportAbility = 0x%x\n", pDM_Odm->SupportAbility ));
- PHYDM_SNPRINTF((output+used, out_len-used,"%s\n", "================================"));
+
}
-#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-//
-//tmp modify for LC Only
-//
-VOID
-ODM_DMWatchdog_LPS(
- IN PDM_ODM_T pDM_Odm
- )
-{
- odm_CommonInfoSelfUpdate(pDM_Odm);
- odm_FalseAlarmCounterStatistics(pDM_Odm);
- odm_RSSIMonitorCheck(pDM_Odm);
- odm_DIGbyRSSI_LPS(pDM_Odm);
- odm_CCKPacketDetectionThresh(pDM_Odm);
- odm_CommonInfoSelfReset(pDM_Odm);
-
- if(*(pDM_Odm->pbPowerSaving)==TRUE)
- return;
-}
-#endif
-//
-// 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM.
-// You can not add any dummy function here, be care, you can only use DM structure
-// to perform any new ODM_DM.
-//
-VOID
-ODM_DMWatchdog(
- IN PDM_ODM_T pDM_Odm
- )
+void
+phydm_pause_func_console(
+ void *dm_void,
+ char input[][16],
+ u32 *_used,
+ char *output,
+ u32 *_out_len,
+ u32 input_num
+)
{
- odm_CommonInfoSelfUpdate(pDM_Odm);
- phydm_BasicDbgMessage(pDM_Odm);
- odm_HWSetting(pDM_Odm);
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ char help[] = "-h";
+ u32 var1[10] = {0};
+ u32 used = *_used;
+ u32 out_len = *_out_len;
+ u32 i;
+ u8 val_length = 0;
+ u32 val_buf[5] = {0};
+ u8 set_result = 0;
+ enum phydm_func_idx func = (enum phydm_func_idx)0;
+ enum phydm_pause_type pause_type = (enum phydm_pause_type)0;
+ enum phydm_pause_level pause_lv = (enum phydm_pause_level)0;
+
+ if ((strcmp(input[1], help) == 0)) {
+ PDM_SNPF(out_len, used, output + used, out_len - used, "{Func} {1:pause, 2:Resume} {lv} Val[5:0]\n");
+
+ } else {
+ for (i = 0; i < 10; i++) {
+ if (input[i + 1]) {
+ PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
+ }
+ }
-#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
- {
- prtl8192cd_priv priv = pDM_Odm->priv;
- if( (priv->auto_channel != 0) && (priv->auto_channel != 2) )//if ACS running, do not do FA/CCA counter read
- return;
- }
-#endif
- odm_FalseAlarmCounterStatistics(pDM_Odm);
- phydm_NoisyDetection(pDM_Odm);
+ func = (enum phydm_func_idx)var1[0];
+ pause_type = (enum phydm_pause_type)var1[1];
+ pause_lv = (enum phydm_pause_level)var1[2];
- odm_RSSIMonitorCheck(pDM_Odm);
- if(*(pDM_Odm->pbPowerSaving) == TRUE)
- {
- odm_DIGbyRSSI_LPS(pDM_Odm);
- {
- pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
- Phydm_Adaptivity(pDM_Odm, pDM_DigTable->CurIGValue);
+ for (i = 0; i < 5; i++) {
+ val_buf[i] = var1[3 + i];
}
- #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
- odm_AntennaDiversity(pDM_Odm); /*enable AntDiv in PS mode, request from SD4 Jeff*/
- #endif
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("DMWatchdog in power saving mode\n"));
- return;
+
+ if (func == F00_DIG) {
+ PDM_SNPF(out_len, used, output + used, out_len - used, "[DIG]\n");
+ val_length = 1;
+
+ } else if (func == F05_CCK_PD) {
+ PDM_SNPF(out_len, used, output + used, out_len - used, "[CCK_PD]\n");
+ val_length = 2;
+ } else if (func == F06_ANT_DIV) {
+ PDM_SNPF(out_len, used, output + used, out_len - used, "[Ant_Div]\n");
+ val_length = 1;
+ } else if (func == F13_ADPTVTY) {
+ PDM_SNPF(out_len, used, output + used, out_len - used, "[Adaptivity]\n");
+ val_length = 2;
+ } else {
+ PDM_SNPF(out_len, used, output + used, out_len - used, "[Set Function Error]\n");
+ val_length = 0;
+ }
+
+ if (val_length != 0) {
+
+ PDM_SNPF(out_len, used, output + used, out_len - used, "{%s, lv=%d} val = %d, %d}\n",
+ ((pause_type == PHYDM_PAUSE) ? "Pause" : "Resume"),
+ pause_lv, var1[3], var1[4]);
+
+ set_result= phydm_pause_func(dm, func, pause_type, pause_lv, val_length, val_buf);
+ }
+
+ PDM_SNPF(out_len, used, output + used, out_len - used, "set_result = %d\n",
+ set_result);
}
+
+
+ *_used = used;
+ *_out_len = out_len;
+}
+
+u8
+phydm_stop_dm_watchdog_check(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+ if (dm->disable_phydm_watchdog == 1) {
+ PHYDM_DBG(dm, DBG_COMMON_FLOW, "Disable phydm\n");
+ return true;
+ } else
+ return false;
+
+}
+
+/*
+ * 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM.
+ * You can not add any dummy function here, be care, you can only use DM structure
+ * to perform any new ODM_DM.
+ * */
+void
+phydm_watchdog(
+ struct dm_struct *dm
+)
+{
+ PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__);
+
+ phydm_common_info_self_update(dm);
+ phydm_rssi_monitor_check(dm);
+ phydm_basic_dbg_message(dm);
+ phydm_auto_dbg_engine(dm);
+ phydm_receiver_blocking(dm);
+
+ if (phydm_stop_dm_watchdog_check(dm) == true)
+ return;
+
+ phydm_hw_setting(dm);
- Phydm_CheckAdaptivity(pDM_Odm);
- odm_UpdatePowerTrainingState(pDM_Odm);
- odm_DIG(pDM_Odm);
+ #ifdef PHYDM_TDMA_DIG_SUPPORT
+ if (dm->original_dig_restore == 0)
+ phydm_tdma_dig_timer_check(dm);
+ else
+ #endif
{
- pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
- Phydm_Adaptivity(pDM_Odm, pDM_DigTable->CurIGValue);
+ odm_false_alarm_counter_statistics(dm);
+ phydm_noisy_detection(dm);
+ phydm_dig(dm);
+ phydm_cck_pd_th(dm);
}
- odm_CCKPacketDetectionThresh(pDM_Odm);
-
- phydm_ra_info_watchdog(pDM_Odm);
- odm_EdcaTurboCheck(pDM_Odm);
- odm_PathDiversity(pDM_Odm);
- ODM_CfoTracking(pDM_Odm);
- odm_DynamicTxPower(pDM_Odm);
- odm_AntennaDiversity(pDM_Odm);
+
+#ifdef PHYDM_POWER_TRAINING_SUPPORT
+ phydm_update_power_training_state(dm);
+#endif
+ phydm_adaptivity(dm);
+ phydm_ra_info_watchdog(dm);
+ odm_path_diversity(dm);
+ phydm_cfo_tracking(dm);
+ /* odm_dynamic_tx_power(dm); */
+ phydm_dynamic_tx_power(dm);
+ odm_antenna_diversity(dm);
+ phydm_adaptive_soml(dm);
+#ifdef CONFIG_DYNAMIC_RX_PATH
+ phydm_dynamic_rx_path(dm);
+#endif
+
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
- phydm_Beamforming_Watchdog(pDM_Odm);
+ phydm_beamforming_watchdog(dm);
+#endif
+
+ halrf_watchdog(dm);
+ phydm_primary_cca(dm);
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ odm_dtc(dm);
+#endif
+
+ phydm_env_mntr_watchdog(dm);
+
+#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
+ phydm_lna_sat_chk_watchdog(dm);
#endif
- phydm_rf_watchdog(pDM_Odm);
+ phydm_common_info_self_reset(dm);
+
+}
+
+
+/*
+ * Init /.. Fixed HW value. Only init time.
+ * */
+void
+odm_cmn_info_init(
+ struct dm_struct *dm,
+ enum odm_cmninfo cmn_info,
+ u64 value
+)
+{
+ /* */
+ /* This section is used for init value */
+ /* */
+ switch (cmn_info) {
+ /* */
+ /* Fixed ODM value. */
+ /* */
+ case ODM_CMNINFO_ABILITY:
+ dm->support_ability = (u64)value;
+ break;
+
+ case ODM_CMNINFO_RF_TYPE:
+ dm->rf_type = (u8)value;
+ break;
+
+ case ODM_CMNINFO_PLATFORM:
+ dm->support_platform = (u8)value;
+ break;
+
+ case ODM_CMNINFO_INTERFACE:
+ dm->support_interface = (u8)value;
+ break;
+
+ case ODM_CMNINFO_MP_TEST_CHIP:
+ dm->is_mp_chip = (u8)value;
+ break;
+
+ case ODM_CMNINFO_IC_TYPE:
+ dm->support_ic_type = (u32)value;
+ break;
+
+ case ODM_CMNINFO_CUT_VER:
+ dm->cut_version = (u8)value;
+ break;
+
+ case ODM_CMNINFO_FAB_VER:
+ dm->fab_version = (u8)value;
+ break;
+
+ case ODM_CMNINFO_RFE_TYPE:
+ #if (RTL8821C_SUPPORT == 1)
+ if (dm->support_ic_type & ODM_RTL8821C)
+ dm->rfe_type_expand = (u8)value; /**/
+ else
+ #endif
+ dm->rfe_type = (u8)value;
+ phydm_init_hw_info_by_rfe(dm);
+ break;
+
+ case ODM_CMNINFO_RF_ANTENNA_TYPE:
+ dm->ant_div_type = (u8)value;
+ break;
+
+ case ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH:
+ dm->with_extenal_ant_switch = (u8)value;
+ break;
+
+ case ODM_CMNINFO_BE_FIX_TX_ANT:
+ dm->dm_fat_table.b_fix_tx_ant = (u8)value;
+ break;
+
+ case ODM_CMNINFO_BOARD_TYPE:
+ if (!dm->is_init_hw_info_by_rfe)
+ dm->board_type = (u8)value;
+ break;
+
+ case ODM_CMNINFO_PACKAGE_TYPE:
+ if (!dm->is_init_hw_info_by_rfe)
+ dm->package_type = (u8)value;
+ break;
+
+ case ODM_CMNINFO_EXT_LNA:
+ if (!dm->is_init_hw_info_by_rfe)
+ dm->ext_lna = (u8)value;
+ break;
+
+ case ODM_CMNINFO_5G_EXT_LNA:
+ if (!dm->is_init_hw_info_by_rfe)
+ dm->ext_lna_5g = (u8)value;
+ break;
+
+ case ODM_CMNINFO_EXT_PA:
+ if (!dm->is_init_hw_info_by_rfe)
+ dm->ext_pa = (u8)value;
+ break;
+
+ case ODM_CMNINFO_5G_EXT_PA:
+ if (!dm->is_init_hw_info_by_rfe)
+ dm->ext_pa_5g = (u8)value;
+ break;
+
+ case ODM_CMNINFO_GPA:
+ if (!dm->is_init_hw_info_by_rfe)
+ dm->type_gpa = (u16)value;
+ break;
+
+ case ODM_CMNINFO_APA:
+ if (!dm->is_init_hw_info_by_rfe)
+ dm->type_apa = (u16)value;
+ break;
+
+ case ODM_CMNINFO_GLNA:
+ if (!dm->is_init_hw_info_by_rfe)
+ dm->type_glna = (u16)value;
+ break;
+
+ case ODM_CMNINFO_ALNA:
+ if (!dm->is_init_hw_info_by_rfe)
+ dm->type_alna = (u16)value;
+ break;
+
+ case ODM_CMNINFO_EXT_TRSW:
+ if (!dm->is_init_hw_info_by_rfe)
+ dm->ext_trsw = (u8)value;
+ break;
+ case ODM_CMNINFO_EXT_LNA_GAIN:
+ dm->ext_lna_gain = (u8)value;
+ break;
+ case ODM_CMNINFO_PATCH_ID:
+ dm->iot_table.win_patch_id = (u8)value;
+ break;
+ case ODM_CMNINFO_BINHCT_TEST:
+ dm->is_in_hct_test = (boolean)value;
+ break;
+ case ODM_CMNINFO_BWIFI_TEST:
+ dm->wifi_test = (u8)value;
+ break;
+ case ODM_CMNINFO_SMART_CONCURRENT:
+ dm->is_dual_mac_smart_concurrent = (boolean)value;
+ break;
+ case ODM_CMNINFO_DOMAIN_CODE_2G:
+ dm->odm_regulation_2_4g = (u8)value;
+ break;
+ case ODM_CMNINFO_DOMAIN_CODE_5G:
+ dm->odm_regulation_5g = (u8)value;
+ break;
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+ case ODM_CMNINFO_CONFIG_BB_RF:
+ dm->config_bbrf = (boolean)value;
+ break;
+#endif
+ case ODM_CMNINFO_IQKPAOFF:
+ dm->rf_calibrate_info.is_iqk_pa_off = (boolean)value;
+ break;
+ case ODM_CMNINFO_REGRFKFREEENABLE:
+ dm->rf_calibrate_info.reg_rf_kfree_enable = (u8)value;
+ break;
+ case ODM_CMNINFO_RFKFREEENABLE:
+ dm->rf_calibrate_info.rf_kfree_enable = (u8)value;
+ break;
+ case ODM_CMNINFO_NORMAL_RX_PATH_CHANGE:
+ dm->normal_rx_path = (u8)value;
+ break;
+ case ODM_CMNINFO_EFUSE0X3D8:
+ dm->efuse0x3d8 = (u8)value;
+ break;
+ case ODM_CMNINFO_EFUSE0X3D7:
+ dm->efuse0x3d7 = (u8)value;
+ break;
+ case ODM_CMNINFO_ADVANCE_OTA:
+ dm->p_advance_ota = (u8)value;
+ break;
+
+#ifdef CONFIG_PHYDM_DFS_MASTER
+ case ODM_CMNINFO_DFS_REGION_DOMAIN:
+ dm->dfs_region_domain = (u8)value;
+ break;
+#endif
+ case ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING:
+ dm->soft_ap_special_setting = (u32)value;
+ break;
+
+ case ODM_CMNINFO_DPK_EN:
+ /*dm->dpk_en = (u1Byte)value;*/
+ halrf_cmn_info_set(dm, HALRF_CMNINFO_DPK_EN, (u64)value);
+ break;
+
+ case ODM_CMNINFO_HP_HWID:
+ dm->hp_hw_id = (boolean)value;
+ break;
+ /* To remove the compiler warning, must add an empty default statement to handle the other values. */
+ default:
+ /* do nothing */
+ break;
+
+ }
+
+}
+
+
+void
+odm_cmn_info_hook(
+ struct dm_struct *dm,
+ enum odm_cmninfo cmn_info,
+ void *value
+)
+{
+ /* */
+ /* Hook call by reference pointer. */
+ /* */
+ switch (cmn_info) {
+ /* */
+ /* Dynamic call by reference pointer. */
+ /* */
+ case ODM_CMNINFO_TX_UNI:
+ dm->num_tx_bytes_unicast = (u64 *)value;
+ break;
+
+ case ODM_CMNINFO_RX_UNI:
+ dm->num_rx_bytes_unicast = (u64 *)value;
+ break;
+
+ case ODM_CMNINFO_BAND:
+ dm->band_type = (u8 *)value;
+ break;
+
+ case ODM_CMNINFO_SEC_CHNL_OFFSET:
+ dm->sec_ch_offset = (u8 *)value;
+ break;
+
+ case ODM_CMNINFO_SEC_MODE:
+ dm->security = (u8 *)value;
+ break;
+
+ case ODM_CMNINFO_BW:
+ dm->band_width = (u8 *)value;
+ break;
+
+ case ODM_CMNINFO_CHNL:
+ dm->channel = (u8 *)value;
+ break;
+
+ case ODM_CMNINFO_SCAN:
+ dm->is_scan_in_process = (boolean *)value;
+ break;
+
+ case ODM_CMNINFO_POWER_SAVING:
+ dm->is_power_saving = (boolean *)value;
+ break;
+
+ case ODM_CMNINFO_ONE_PATH_CCA:
+ dm->one_path_cca = (u8 *)value;
+ break;
+
+ case ODM_CMNINFO_DRV_STOP:
+ dm->is_driver_stopped = (boolean *)value;
+ break;
+
+ case ODM_CMNINFO_PNP_IN:
+ dm->is_driver_is_going_to_pnp_set_power_sleep = (boolean *)value;
+ break;
+
+ case ODM_CMNINFO_INIT_ON:
+ dm->pinit_adpt_in_progress = (boolean *)value;
+ break;
+
+ case ODM_CMNINFO_ANT_TEST:
+ dm->antenna_test = (u8 *)value;
+ break;
+
+ case ODM_CMNINFO_NET_CLOSED:
+ dm->is_net_closed = (boolean *)value;
+ break;
- if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
- {
-
-#if (RTL8188E_SUPPORT == 1)
- if (pDM_Odm->SupportICType == ODM_RTL8188E)
- ODM_DynamicPrimaryCCA(pDM_Odm);
-#endif
+ case ODM_CMNINFO_FORCED_RATE:
+ dm->forced_data_rate = (u16 *)value;
+ break;
+ case ODM_CMNINFO_ANT_DIV:
+ dm->enable_antdiv = (u8 *)value;
+ break;
-#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
+ case ODM_CMNINFO_ADAPTIVE_SOML:
+ dm->en_adap_soml = (u8 *)value;
+ break;
- #if (RTL8192E_SUPPORT == 1)
- if(pDM_Odm->SupportICType==ODM_RTL8192E)
- odm_DynamicPrimaryCCA_Check(pDM_Odm);
- #endif
-#endif
- }
+ case ODM_CMNINFO_ADAPTIVITY:
+ dm->enable_adaptivity = (u8 *)value;
+ break;
-#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
- odm_dtc(pDM_Odm);
-#endif
+ case ODM_CMNINFO_P2P_LINK:
+ dm->dm_dig_table.is_p2p_in_process = (u8 *)value;
+ break;
- odm_CommonInfoSelfReset(pDM_Odm);
-
-}
+ case ODM_CMNINFO_IS1ANTENNA:
+ dm->is_1_antenna = (boolean *)value;
+ break;
+ case ODM_CMNINFO_RFDEFAULTPATH:
+ dm->rf_default_path = (u8 *)value;
+ break;
-//
-// Init /.. Fixed HW value. Only init time.
-//
-VOID
-ODM_CmnInfoInit(
- IN PDM_ODM_T pDM_Odm,
- IN ODM_CMNINFO_E CmnInfo,
- IN u4Byte Value
- )
-{
- //
- // This section is used for init value
- //
- switch (CmnInfo)
- {
- //
- // Fixed ODM value.
- //
- case ODM_CMNINFO_ABILITY:
- pDM_Odm->SupportAbility = (u4Byte)Value;
- break;
-
- case ODM_CMNINFO_RF_TYPE:
- pDM_Odm->RFType = (u1Byte)Value;
- break;
-
- case ODM_CMNINFO_PLATFORM:
- pDM_Odm->SupportPlatform = (u1Byte)Value;
- break;
-
- case ODM_CMNINFO_INTERFACE:
- pDM_Odm->SupportInterface = (u1Byte)Value;
- break;
-
- case ODM_CMNINFO_MP_TEST_CHIP:
- pDM_Odm->bIsMPChip= (u1Byte)Value;
- break;
-
- case ODM_CMNINFO_IC_TYPE:
- pDM_Odm->SupportICType = Value;
- break;
-
- case ODM_CMNINFO_CUT_VER:
- pDM_Odm->CutVersion = (u1Byte)Value;
- break;
-
- case ODM_CMNINFO_FAB_VER:
- pDM_Odm->FabVersion = (u1Byte)Value;
- break;
-
- case ODM_CMNINFO_RFE_TYPE:
- pDM_Odm->RFEType = (u1Byte)Value;
- PHYDM_InitHwInfoByRfe(pDM_Odm);
- break;
-
- case ODM_CMNINFO_RF_ANTENNA_TYPE:
- pDM_Odm->AntDivType= (u1Byte)Value;
- break;
-
- case ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH:
- pDM_Odm->with_extenal_ant_switch = (u1Byte)Value;
- break;
-
- case ODM_CMNINFO_BE_FIX_TX_ANT:
- pDM_Odm->DM_FatTable.b_fix_tx_ant = (u1Byte)Value;
- break;
-
- case ODM_CMNINFO_BOARD_TYPE:
- if (!pDM_Odm->bInitHwInfoByRfe)
- pDM_Odm->BoardType = (u1Byte)Value;
- break;
-
- case ODM_CMNINFO_PACKAGE_TYPE:
- if (!pDM_Odm->bInitHwInfoByRfe)
- pDM_Odm->PackageType = (u1Byte)Value;
- break;
-
- case ODM_CMNINFO_EXT_LNA:
- if (!pDM_Odm->bInitHwInfoByRfe)
- pDM_Odm->ExtLNA = (u1Byte)Value;
- break;
-
- case ODM_CMNINFO_5G_EXT_LNA:
- if (!pDM_Odm->bInitHwInfoByRfe)
- pDM_Odm->ExtLNA5G = (u1Byte)Value;
- break;
-
- case ODM_CMNINFO_EXT_PA:
- if (!pDM_Odm->bInitHwInfoByRfe)
- pDM_Odm->ExtPA = (u1Byte)Value;
- break;
-
- case ODM_CMNINFO_5G_EXT_PA:
- if (!pDM_Odm->bInitHwInfoByRfe)
- pDM_Odm->ExtPA5G = (u1Byte)Value;
- break;
-
- case ODM_CMNINFO_GPA:
- if (!pDM_Odm->bInitHwInfoByRfe)
- pDM_Odm->TypeGPA = (u2Byte)Value;
- break;
-
- case ODM_CMNINFO_APA:
- if (!pDM_Odm->bInitHwInfoByRfe)
- pDM_Odm->TypeAPA = (u2Byte)Value;
- break;
-
- case ODM_CMNINFO_GLNA:
- if (!pDM_Odm->bInitHwInfoByRfe)
- pDM_Odm->TypeGLNA = (u2Byte)Value;
- break;
-
- case ODM_CMNINFO_ALNA:
- if (!pDM_Odm->bInitHwInfoByRfe)
- pDM_Odm->TypeALNA = (u2Byte)Value;
- break;
-
- case ODM_CMNINFO_EXT_TRSW:
- pDM_Odm->ExtTRSW = (u1Byte)Value;
- break;
- case ODM_CMNINFO_EXT_LNA_GAIN:
- pDM_Odm->ExtLNAGain = (u1Byte)Value;
- break;
- case ODM_CMNINFO_PATCH_ID:
- pDM_Odm->PatchID = (u1Byte)Value;
- break;
- case ODM_CMNINFO_BINHCT_TEST:
- pDM_Odm->bInHctTest = (BOOLEAN)Value;
- break;
- case ODM_CMNINFO_BWIFI_TEST:
- pDM_Odm->WIFITest = (u1Byte)Value;
- break;
- case ODM_CMNINFO_SMART_CONCURRENT:
- pDM_Odm->bDualMacSmartConcurrent = (BOOLEAN )Value;
- break;
- case ODM_CMNINFO_DOMAIN_CODE_2G:
- pDM_Odm->odm_Regulation2_4G = (u1Byte)Value;
- break;
- case ODM_CMNINFO_DOMAIN_CODE_5G:
- pDM_Odm->odm_Regulation5G = (u1Byte)Value;
- break;
- case ODM_CMNINFO_CONFIG_BB_RF:
- pDM_Odm->ConfigBBRF = (BOOLEAN)Value;
- break;
- case ODM_CMNINFO_IQKFWOFFLOAD:
- pDM_Odm->IQKFWOffload = (u1Byte)Value;
- break;
- case ODM_CMNINFO_IQKPAOFF:
- pDM_Odm->RFCalibrateInfo.bIQKPAoff = (BOOLEAN )Value;
- break;
- case ODM_CMNINFO_REGRFKFREEENABLE:
- pDM_Odm->RFCalibrateInfo.RegRfKFreeEnable = (u1Byte)Value;
- break;
- case ODM_CMNINFO_RFKFREEENABLE:
- pDM_Odm->RFCalibrateInfo.RfKFreeEnable = (u1Byte)Value;
- break;
+ case ODM_CMNINFO_FCS_MODE:
+ dm->is_fcs_mode_enable = (boolean *)value;
+ break;
+ /*add by YuChen for beamforming PhyDM*/
+ case ODM_CMNINFO_HUBUSBMODE:
+ dm->hub_usb_mode = (u8 *)value;
+ break;
+ case ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS:
+ dm->is_fw_dw_rsvd_page_in_progress = (boolean *)value;
+ break;
+ case ODM_CMNINFO_TX_TP:
+ dm->current_tx_tp = (u32 *)value;
+ break;
+ case ODM_CMNINFO_RX_TP:
+ dm->current_rx_tp = (u32 *)value;
+ break;
+ case ODM_CMNINFO_SOUNDING_SEQ:
+ dm->sounding_seq = (u8 *)value;
+ break;
#ifdef CONFIG_PHYDM_DFS_MASTER
- case ODM_CMNINFO_DFS_REGION_DOMAIN:
- pDM_Odm->DFS_RegionDomain = (u1Byte)Value;
- break;
-#endif
- //To remove the compiler warning, must add an empty default statement to handle the other values.
- default:
- //do nothing
- break;
-
+ case ODM_CMNINFO_DFS_MASTER_ENABLE:
+ dm->dfs_master_enabled = (u8 *)value;
+ break;
+#endif
+ case ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC:
+ dm->dm_fat_table.p_force_tx_ant_by_desc = (u8 *)value;
+ break;
+ case ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA:
+ dm->dm_fat_table.p_default_s0_s1 = (u8 *)value;
+ break;
+ case ODM_CMNINFO_SOFT_AP_MODE:
+ dm->soft_ap_mode = (u32 *)value;
+ break;
+ case ODM_CMNINFO_MP_MODE:
+ dm->mp_mode = (u8 *)value;
+ break;
+ case ODM_CMNINFO_INTERRUPT_MASK:
+ dm->interrupt_mask = (u32 *)value;
+ break;
+ case ODM_CMNINFO_BB_OPERATION_MODE:
+ dm->bb_op_mode = (u8 *)value;
+ break;
+ case ODM_CMNINFO_BF_ANTDIV_DECISION:
+ dm->dm_fat_table.is_no_csi_feedback = (boolean *)value;
+ break;
+
+ default:
+ /*do nothing*/
+ break;
+
}
}
+/*
+ * Update band/CHannel/.. The values are dynamic but non-per-packet.
+ * */
+void
+odm_cmn_info_update(
+ struct dm_struct *dm,
+ u32 cmn_info,
+ u64 value
+)
+{
+ /* */
+ /* This init variable may be changed in run time. */
+ /* */
+ switch (cmn_info) {
+ case ODM_CMNINFO_LINK_IN_PROGRESS:
+ dm->is_link_in_process = (boolean)value;
+ break;
+ case ODM_CMNINFO_ABILITY:
+ dm->support_ability = (u64)value;
+ break;
-VOID
-ODM_CmnInfoHook(
- IN PDM_ODM_T pDM_Odm,
- IN ODM_CMNINFO_E CmnInfo,
- IN PVOID pValue
- )
-{
- //
- // Hook call by reference pointer.
- //
- switch (CmnInfo)
- {
- //
- // Dynamic call by reference pointer.
- //
- case ODM_CMNINFO_MAC_PHY_MODE:
- pDM_Odm->pMacPhyMode = (u1Byte *)pValue;
- break;
-
- case ODM_CMNINFO_TX_UNI:
- pDM_Odm->pNumTxBytesUnicast = (u8Byte *)pValue;
- break;
+ case ODM_CMNINFO_RF_TYPE:
+ dm->rf_type = (u8)value;
+ break;
+
+ case ODM_CMNINFO_WIFI_DIRECT:
+ dm->is_wifi_direct = (boolean)value;
+ break;
- case ODM_CMNINFO_RX_UNI:
- pDM_Odm->pNumRxBytesUnicast = (u8Byte *)pValue;
- break;
+ case ODM_CMNINFO_WIFI_DISPLAY:
+ dm->is_wifi_display = (boolean)value;
+ break;
- case ODM_CMNINFO_WM_MODE:
- pDM_Odm->pWirelessMode = (u1Byte *)pValue;
- break;
+ case ODM_CMNINFO_LINK:
+ dm->is_linked = (boolean)value;
+ break;
- case ODM_CMNINFO_BAND:
- pDM_Odm->pBandType = (u1Byte *)pValue;
- break;
+ case ODM_CMNINFO_CMW500LINK:
+ dm->iot_table.is_linked_cmw500 = (boolean)value;
+ break;
- case ODM_CMNINFO_SEC_CHNL_OFFSET:
- pDM_Odm->pSecChOffset = (u1Byte *)pValue;
- break;
+ case ODM_CMNINFO_STATION_STATE:
+ dm->bsta_state = (boolean)value;
+ break;
- case ODM_CMNINFO_SEC_MODE:
- pDM_Odm->pSecurity = (u1Byte *)pValue;
- break;
+ case ODM_CMNINFO_RSSI_MIN:
+ dm->rssi_min = (u8)value;
+ break;
- case ODM_CMNINFO_BW:
- pDM_Odm->pBandWidth = (u1Byte *)pValue;
- break;
+ case ODM_CMNINFO_RSSI_MIN_BY_PATH:
+ dm->rssi_min_by_path = (u8)value;
+ break;
- case ODM_CMNINFO_CHNL:
- pDM_Odm->pChannel = (u1Byte *)pValue;
- break;
-
- case ODM_CMNINFO_DMSP_GET_VALUE:
- pDM_Odm->pbGetValueFromOtherMac = (BOOLEAN *)pValue;
- break;
+ case ODM_CMNINFO_DBG_COMP:
+ dm->debug_components = (u64)value;
+ break;
- case ODM_CMNINFO_BUDDY_ADAPTOR:
- pDM_Odm->pBuddyAdapter = (PADAPTER *)pValue;
- break;
+ case ODM_CMNINFO_DBG_LEVEL:
+ dm->debug_level = (u32)value;
+ break;
- case ODM_CMNINFO_DMSP_IS_MASTER:
- pDM_Odm->pbMasterOfDMSP = (BOOLEAN *)pValue;
- break;
+#ifdef ODM_CONFIG_BT_COEXIST
+ /* The following is for BT HS mode and BT coexist mechanism. */
+ case ODM_CMNINFO_BT_ENABLED:
+ dm->bt_info_table.is_bt_enabled = (boolean)value;
+ break;
- case ODM_CMNINFO_SCAN:
- pDM_Odm->pbScanInProcess = (BOOLEAN *)pValue;
- break;
+ case ODM_CMNINFO_BT_HS_CONNECT_PROCESS:
+ dm->bt_info_table.is_bt_connect_process = (boolean)value;
+ break;
- case ODM_CMNINFO_POWER_SAVING:
- pDM_Odm->pbPowerSaving = (BOOLEAN *)pValue;
- break;
+ case ODM_CMNINFO_BT_HS_RSSI:
+ dm->bt_info_table.bt_hs_rssi = (u8)value;
+ break;
- case ODM_CMNINFO_ONE_PATH_CCA:
- pDM_Odm->pOnePathCCA = (u1Byte *)pValue;
- break;
+ case ODM_CMNINFO_BT_OPERATION:
+ dm->bt_info_table.is_bt_hs_operation = (boolean)value;
+ break;
- case ODM_CMNINFO_DRV_STOP:
- pDM_Odm->pbDriverStopped = (BOOLEAN *)pValue;
- break;
+ case ODM_CMNINFO_BT_LIMITED_DIG:
+ dm->bt_info_table.is_bt_limited_dig = (boolean)value;
+ break;
+#endif
- case ODM_CMNINFO_PNP_IN:
- pDM_Odm->pbDriverIsGoingToPnpSetPowerSleep = (BOOLEAN *)pValue;
- break;
+ case ODM_CMNINFO_AP_TOTAL_NUM:
+ dm->ap_total_num = (u8)value;
+ break;
- case ODM_CMNINFO_INIT_ON:
- pDM_Odm->pinit_adpt_in_progress = (BOOLEAN *)pValue;
- break;
+#ifdef CONFIG_PHYDM_DFS_MASTER
+ case ODM_CMNINFO_DFS_REGION_DOMAIN:
+ dm->dfs_region_domain = (u8)value;
+ break;
+#endif
- case ODM_CMNINFO_ANT_TEST:
- pDM_Odm->pAntennaTest = (u1Byte *)pValue;
- break;
+ case ODM_CMNINFO_BT_CONTINUOUS_TURN:
+ dm->is_bt_continuous_turn = (boolean)value;
+ break;
- case ODM_CMNINFO_NET_CLOSED:
- pDM_Odm->pbNet_closed = (BOOLEAN *)pValue;
- break;
+#if 0
+ case ODM_CMNINFO_OP_MODE:
+ dm->op_mode = (u8)value;
+ break;
- case ODM_CMNINFO_FORCED_RATE:
- pDM_Odm->pForcedDataRate = (pu2Byte)pValue;
- break;
+ case ODM_CMNINFO_BAND:
+ dm->band_type = (u8)value;
+ break;
- case ODM_CMNINFO_FORCED_IGI_LB:
- pDM_Odm->pu1ForcedIgiLb = (u1Byte *)pValue;
- break;
+ case ODM_CMNINFO_SEC_CHNL_OFFSET:
+ dm->sec_ch_offset = (u8)value;
+ break;
- case ODM_CMNINFO_P2P_LINK:
- pDM_Odm->DM_DigTable.bP2PInProcess = (u1Byte *)pValue;
- break;
+ case ODM_CMNINFO_SEC_MODE:
+ dm->security = (u8)value;
+ break;
- case ODM_CMNINFO_IS1ANTENNA:
- pDM_Odm->pIs1Antenna = (BOOLEAN *)pValue;
- break;
-
- case ODM_CMNINFO_RFDEFAULTPATH:
- pDM_Odm->pRFDefaultPath= (u1Byte *)pValue;
- break;
-
- case ODM_CMNINFO_FCS_MODE:
- pDM_Odm->pIsFcsModeEnable = (BOOLEAN *)pValue;
- break;
- /*add by YuChen for beamforming PhyDM*/
- case ODM_CMNINFO_HUBUSBMODE:
- pDM_Odm->HubUsbMode = (u1Byte *)pValue;
- break;
- case ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS:
- pDM_Odm->pbFwDwRsvdPageInProgress = (BOOLEAN *)pValue;
- break;
- case ODM_CMNINFO_TX_TP:
- pDM_Odm->pCurrentTxTP = (u4Byte *)pValue;
- break;
- case ODM_CMNINFO_RX_TP:
- pDM_Odm->pCurrentRxTP = (u4Byte *)pValue;
- break;
- case ODM_CMNINFO_SOUNDING_SEQ:
- pDM_Odm->pSoundingSeq = (u1Byte *)pValue;
- break;
-#ifdef CONFIG_PHYDM_DFS_MASTER
- case ODM_CMNINFO_DFS_MASTER_ENABLE:
- pDM_Odm->dfs_master_enabled = (u1Byte *)pValue;
- break;
-#endif
- case ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC:
- pDM_Odm->DM_FatTable.pForceTxAntByDesc = (u1Byte *)pValue;
- break;
- //case ODM_CMNINFO_RTSTA_AID:
- // pDM_Odm->pAidMap = (u1Byte *)pValue;
- // break;
-
- //case ODM_CMNINFO_BT_COEXIST:
- // pDM_Odm->BTCoexist = (BOOLEAN *)pValue;
-
- //case ODM_CMNINFO_STA_STATUS:
- //pDM_Odm->pODM_StaInfo[] = (PSTA_INFO_T)pValue;
- //break;
-
- //case ODM_CMNINFO_PHY_STATUS:
- // pDM_Odm->pPhyInfo = (ODM_PHY_INFO *)pValue;
- // break;
-
- //case ODM_CMNINFO_MAC_STATUS:
- // pDM_Odm->pMacInfo = (ODM_MAC_INFO *)pValue;
- // break;
- //To remove the compiler warning, must add an empty default statement to handle the other values.
- default:
- //do nothing
- break;
+ case ODM_CMNINFO_BW:
+ dm->band_width = (u8)value;
+ break;
+ case ODM_CMNINFO_CHNL:
+ dm->channel = (u8)value;
+ break;
+#endif
+ default:
+ /* do nothing */
+ break;
}
-}
+}
-VOID
-ODM_CmnInfoPtrArrayHook(
- IN PDM_ODM_T pDM_Odm,
- IN ODM_CMNINFO_E CmnInfo,
- IN u2Byte Index,
- IN PVOID pValue
- )
+u32
+phydm_cmn_info_query(
+ struct dm_struct *dm,
+ enum phydm_info_query info_type
+)
{
- //
- // Hook call by reference pointer.
- //
- switch (CmnInfo)
- {
- //
- // Dynamic call by reference pointer.
- //
- case ODM_CMNINFO_STA_STATUS:
- pDM_Odm->pODM_StaInfo[Index] = (PSTA_INFO_T)pValue;
-
- if (IS_STA_VALID(pDM_Odm->pODM_StaInfo[Index]))
- #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
- pDM_Odm->platform2phydm_macid_table[((PSTA_INFO_T)pValue)->AssociatedMacId] = Index; /*AssociatedMacId are unique bttween different Adapter*/
- #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
- pDM_Odm->platform2phydm_macid_table[((PSTA_INFO_T)pValue)->aid] = Index;
- #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
- pDM_Odm->platform2phydm_macid_table[((PSTA_INFO_T)pValue)->mac_id] = Index;
- #endif
-
- break;
- //To remove the compiler warning, must add an empty default statement to handle the other values.
- default:
- //do nothing
- break;
- }
-
-}
+ struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
+ struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
+ struct ccx_info *ccx_info = &dm->dm_ccx_info;
+ switch (info_type) {
+ /*=== [FA Relative] ===========================================*/
+ case PHYDM_INFO_FA_OFDM:
+ return fa_t->cnt_ofdm_fail;
-//
-// Update Band/CHannel/.. The values are dynamic but non-per-packet.
-//
-VOID
-ODM_CmnInfoUpdate(
- IN PDM_ODM_T pDM_Odm,
- IN u4Byte CmnInfo,
- IN u8Byte Value
- )
-{
- //
- // This init variable may be changed in run time.
- //
- switch (CmnInfo)
- {
- case ODM_CMNINFO_LINK_IN_PROGRESS:
- pDM_Odm->bLinkInProcess = (BOOLEAN)Value;
- break;
-
- case ODM_CMNINFO_ABILITY:
- pDM_Odm->SupportAbility = (u4Byte)Value;
- break;
+ case PHYDM_INFO_FA_CCK:
+ return fa_t->cnt_cck_fail;
- case ODM_CMNINFO_RF_TYPE:
- pDM_Odm->RFType = (u1Byte)Value;
- break;
+ case PHYDM_INFO_FA_TOTAL:
+ return fa_t->cnt_all;
- case ODM_CMNINFO_WIFI_DIRECT:
- pDM_Odm->bWIFI_Direct = (BOOLEAN)Value;
- break;
+ case PHYDM_INFO_CCA_OFDM:
+ return fa_t->cnt_ofdm_cca;
- case ODM_CMNINFO_WIFI_DISPLAY:
- pDM_Odm->bWIFI_Display = (BOOLEAN)Value;
- break;
+ case PHYDM_INFO_CCA_CCK:
+ return fa_t->cnt_cck_cca;
- case ODM_CMNINFO_LINK:
- pDM_Odm->bLinked = (BOOLEAN)Value;
- break;
+ case PHYDM_INFO_CCA_ALL:
+ return fa_t->cnt_cca_all;
- case ODM_CMNINFO_STATION_STATE:
- pDM_Odm->bsta_state = (BOOLEAN)Value;
- break;
-
- case ODM_CMNINFO_RSSI_MIN:
- pDM_Odm->RSSI_Min= (u1Byte)Value;
- break;
-
- case ODM_CMNINFO_DBG_COMP:
- pDM_Odm->DebugComponents = (u4Byte)Value;
- break;
-
- case ODM_CMNINFO_DBG_LEVEL:
- pDM_Odm->DebugLevel = (u4Byte)Value;
- break;
- case ODM_CMNINFO_RA_THRESHOLD_HIGH:
- pDM_Odm->RateAdaptive.HighRSSIThresh = (u1Byte)Value;
- break;
-
- case ODM_CMNINFO_RA_THRESHOLD_LOW:
- pDM_Odm->RateAdaptive.LowRSSIThresh = (u1Byte)Value;
- break;
-#if defined(BT_SUPPORT) && (BT_SUPPORT == 1)
- // The following is for BT HS mode and BT coexist mechanism.
- case ODM_CMNINFO_BT_ENABLED:
- pDM_Odm->bBtEnabled = (BOOLEAN)Value;
- break;
-
- case ODM_CMNINFO_BT_HS_CONNECT_PROCESS:
- pDM_Odm->bBtConnectProcess = (BOOLEAN)Value;
- break;
-
- case ODM_CMNINFO_BT_HS_RSSI:
- pDM_Odm->btHsRssi = (u1Byte)Value;
- break;
-
- case ODM_CMNINFO_BT_OPERATION:
- pDM_Odm->bBtHsOperation = (BOOLEAN)Value;
- break;
+ case PHYDM_INFO_CRC32_OK_VHT:
+ return fa_t->cnt_vht_crc32_ok;
- case ODM_CMNINFO_BT_LIMITED_DIG:
- pDM_Odm->bBtLimitedDig = (BOOLEAN)Value;
- break;
+ case PHYDM_INFO_CRC32_OK_HT:
+ return fa_t->cnt_ht_crc32_ok;
- case ODM_CMNINFO_BT_DIG:
- pDM_Odm->btHsDigVal = (u1Byte)Value;
- break;
-
- case ODM_CMNINFO_BT_BUSY:
- pDM_Odm->bBtBusy = (BOOLEAN)Value;
- break;
+ case PHYDM_INFO_CRC32_OK_LEGACY:
+ return fa_t->cnt_ofdm_crc32_ok;
- case ODM_CMNINFO_BT_DISABLE_EDCA:
- pDM_Odm->bBtDisableEdcaTurbo = (BOOLEAN)Value;
- break;
-#endif
+ case PHYDM_INFO_CRC32_OK_CCK:
+ return fa_t->cnt_cck_crc32_ok;
-#if(DM_ODM_SUPPORT_TYPE & ODM_AP) // for repeater mode add by YuChen 2014.06.23
-#ifdef UNIVERSAL_REPEATER
- case ODM_CMNINFO_VXD_LINK:
- pDM_Odm->VXD_bLinked= (BOOLEAN)Value;
- break;
-#endif
-#endif
+ case PHYDM_INFO_CRC32_ERROR_VHT:
+ return fa_t->cnt_vht_crc32_error;
- case ODM_CMNINFO_AP_TOTAL_NUM:
- pDM_Odm->APTotalNum = (u1Byte)Value;
- break;
+ case PHYDM_INFO_CRC32_ERROR_HT:
+ return fa_t->cnt_ht_crc32_error;
- case ODM_CMNINFO_POWER_TRAINING:
- pDM_Odm->bDisablePowerTraining = (BOOLEAN)Value;
- break;
+ case PHYDM_INFO_CRC32_ERROR_LEGACY:
+ return fa_t->cnt_ofdm_crc32_error;
-#ifdef CONFIG_PHYDM_DFS_MASTER
- case ODM_CMNINFO_DFS_REGION_DOMAIN:
- pDM_Odm->DFS_RegionDomain = (u1Byte)Value;
- break;
-#endif
+ case PHYDM_INFO_CRC32_ERROR_CCK:
+ return fa_t->cnt_cck_crc32_error;
-/*
- case ODM_CMNINFO_OP_MODE:
- pDM_Odm->OPMode = (u1Byte)Value;
- break;
-
- case ODM_CMNINFO_WM_MODE:
- pDM_Odm->WirelessMode = (u1Byte)Value;
- break;
-
- case ODM_CMNINFO_BAND:
- pDM_Odm->BandType = (u1Byte)Value;
- break;
-
- case ODM_CMNINFO_SEC_CHNL_OFFSET:
- pDM_Odm->SecChOffset = (u1Byte)Value;
- break;
-
- case ODM_CMNINFO_SEC_MODE:
- pDM_Odm->Security = (u1Byte)Value;
- break;
-
- case ODM_CMNINFO_BW:
- pDM_Odm->BandWidth = (u1Byte)Value;
- break;
-
- case ODM_CMNINFO_CHNL:
- pDM_Odm->Channel = (u1Byte)Value;
- break;
-*/
- default:
- //do nothing
- break;
- }
+ case PHYDM_INFO_EDCCA_FLAG:
+ return fa_t->edcca_flag;
+ case PHYDM_INFO_OFDM_ENABLE:
+ return fa_t->ofdm_block_enable;
+
+ case PHYDM_INFO_CCK_ENABLE:
+ return fa_t->cck_block_enable;
+
+ case PHYDM_INFO_DBG_PORT_0:
+ return fa_t->dbg_port0;
+
+ case PHYDM_INFO_CRC32_OK_HT_AGG:
+ return fa_t->cnt_ht_crc32_ok_agg;
+
+ case PHYDM_INFO_CRC32_ERROR_HT_AGG:
+ return fa_t->cnt_ht_crc32_error_agg;
+
+ /*=== [DIG] ================================================*/
+ case PHYDM_INFO_CURR_IGI:
+ return dig_t->cur_ig_value;
+
+ /*=== [RSSI] ===============================================*/
+ case PHYDM_INFO_RSSI_MIN:
+ return (u32)dm->rssi_min;
+
+ case PHYDM_INFO_RSSI_MAX:
+ return (u32)dm->rssi_max;
+
+ case PHYDM_INFO_CLM_RATIO :
+ return (u32)ccx_info->clm_ratio;
+ case PHYDM_INFO_NHM_RATIO :
+ return (u32)ccx_info->nhm_ratio;
+ default:
+ return 0xffffffff;
+
+ }
}
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-VOID
-ODM_InitAllWorkItems(IN PDM_ODM_T pDM_Odm )
+void
+odm_init_all_work_items(struct dm_struct *dm)
{
-
- PADAPTER pAdapter = pDM_Odm->Adapter;
+ void *adapter = dm->adapter;
#if USE_WORKITEM
- #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
- ODM_InitializeWorkItem( pDM_Odm,
- &pDM_Odm->DM_SWAT_Table.phydm_SwAntennaSwitchWorkitem,
- (RT_WORKITEM_CALL_BACK)ODM_SW_AntDiv_WorkitemCallback,
- (PVOID)pAdapter,
- "AntennaSwitchWorkitem");
- #endif
- #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
- ODM_InitializeWorkItem(pDM_Odm,
- &pDM_Odm->dm_sat_table.hl_smart_antenna_workitem,
- (RT_WORKITEM_CALL_BACK)phydm_beam_switch_workitem_callback,
- (PVOID)pAdapter,
- "hl_smart_ant_workitem");
-
- ODM_InitializeWorkItem(pDM_Odm,
- &pDM_Odm->dm_sat_table.hl_smart_antenna_decision_workitem,
- (RT_WORKITEM_CALL_BACK)phydm_beam_decision_workitem_callback,
- (PVOID)pAdapter,
- "hl_smart_ant_decision_workitem");
- #endif
-
- ODM_InitializeWorkItem(
- pDM_Odm,
- &(pDM_Odm->PathDivSwitchWorkitem),
- (RT_WORKITEM_CALL_BACK)odm_PathDivChkAntSwitchWorkitemCallback,
- (PVOID)pAdapter,
+
+#ifdef CONFIG_DYNAMIC_RX_PATH
+ odm_initialize_work_item(dm,
+ &dm->dm_drp_table.phydm_dynamic_rx_path_workitem,
+ (RT_WORKITEM_CALL_BACK)phydm_dynamic_rx_path_workitem_callback,
+ (void *)adapter,
+ "DynamicRxPathWorkitem");
+
+#endif
+
+#ifdef CONFIG_ADAPTIVE_SOML
+ odm_initialize_work_item(dm,
+ &dm->dm_soml_table.phydm_adaptive_soml_workitem,
+ (RT_WORKITEM_CALL_BACK)phydm_adaptive_soml_workitem_callback,
+ (void *)adapter,
+ "AdaptiveSOMLWorkitem");
+#endif
+
+#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
+ odm_initialize_work_item(dm,
+ &dm->dm_swat_table.phydm_sw_antenna_switch_workitem,
+ (RT_WORKITEM_CALL_BACK)odm_sw_antdiv_workitem_callback,
+ (void *)adapter,
+ "AntennaSwitchWorkitem");
+#endif
+#if (defined(CONFIG_HL_SMART_ANTENNA))
+ odm_initialize_work_item(dm,
+ &dm->dm_sat_table.hl_smart_antenna_workitem,
+ (RT_WORKITEM_CALL_BACK)phydm_beam_switch_workitem_callback,
+ (void *)adapter,
+ "hl_smart_ant_workitem");
+
+ odm_initialize_work_item(dm,
+ &dm->dm_sat_table.hl_smart_antenna_decision_workitem,
+ (RT_WORKITEM_CALL_BACK)phydm_beam_decision_workitem_callback,
+ (void *)adapter,
+ "hl_smart_ant_decision_workitem");
+#endif
+
+ odm_initialize_work_item(
+ dm,
+ &dm->path_div_switch_workitem,
+ (RT_WORKITEM_CALL_BACK)odm_path_div_chk_ant_switch_workitem_callback,
+ (void *)adapter,
"SWAS_WorkItem");
- ODM_InitializeWorkItem(
- pDM_Odm,
- &(pDM_Odm->CCKPathDiversityWorkitem),
- (RT_WORKITEM_CALL_BACK)odm_CCKTXPathDiversityWorkItemCallback,
- (PVOID)pAdapter,
+ odm_initialize_work_item(
+ dm,
+ &dm->cck_path_diversity_workitem,
+ (RT_WORKITEM_CALL_BACK)odm_cck_tx_path_diversity_work_item_callback,
+ (void *)adapter,
"CCKTXPathDiversityWorkItem");
- ODM_InitializeWorkItem(
- pDM_Odm,
- &(pDM_Odm->MPT_DIGWorkitem),
- (RT_WORKITEM_CALL_BACK)odm_MPT_DIGWorkItemCallback,
- (PVOID)pAdapter,
- "MPT_DIGWorkitem");
-
- ODM_InitializeWorkItem(
- pDM_Odm,
- &(pDM_Odm->RaRptWorkitem),
- (RT_WORKITEM_CALL_BACK)ODM_UpdateInitRateWorkItemCallback,
- (PVOID)pAdapter,
- "RaRptWorkitem");
-
-#if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) )
- ODM_InitializeWorkItem(
- pDM_Odm,
- &(pDM_Odm->FastAntTrainingWorkitem),
- (RT_WORKITEM_CALL_BACK)odm_FastAntTrainingWorkItemCallback,
- (PVOID)pAdapter,
- "FastAntTrainingWorkitem");
+ odm_initialize_work_item(
+ dm,
+ &dm->ra_rpt_workitem,
+ (RT_WORKITEM_CALL_BACK)halrf_update_init_rate_work_item_callback,
+ (void *)adapter,
+ "ra_rpt_workitem");
+
+#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
+ odm_initialize_work_item(
+ dm,
+ &dm->fast_ant_training_workitem,
+ (RT_WORKITEM_CALL_BACK)odm_fast_ant_training_work_item_callback,
+ (void *)adapter,
+ "fast_ant_training_workitem");
#endif
#endif /*#if USE_WORKITEM*/
#if (BEAMFORMING_SUPPORT == 1)
- ODM_InitializeWorkItem(
- pDM_Odm,
- &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_EnterWorkItem),
- (RT_WORKITEM_CALL_BACK)halComTxbf_EnterWorkItemCallback,
- (PVOID)pAdapter,
- "Txbf_EnterWorkItem");
-
- ODM_InitializeWorkItem(
- pDM_Odm,
- &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_LeaveWorkItem),
- (RT_WORKITEM_CALL_BACK)halComTxbf_LeaveWorkItemCallback,
- (PVOID)pAdapter,
- "Txbf_LeaveWorkItem");
-
- ODM_InitializeWorkItem(
- pDM_Odm,
- &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_FwNdpaWorkItem),
- (RT_WORKITEM_CALL_BACK)halComTxbf_FwNdpaWorkItemCallback,
- (PVOID)pAdapter,
- "Txbf_FwNdpaWorkItem");
-
- ODM_InitializeWorkItem(
- pDM_Odm,
- &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_ClkWorkItem),
- (RT_WORKITEM_CALL_BACK)halComTxbf_ClkWorkItemCallback,
- (PVOID)pAdapter,
- "Txbf_ClkWorkItem");
-
- ODM_InitializeWorkItem(
- pDM_Odm,
- &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_RateWorkItem),
- (RT_WORKITEM_CALL_BACK)halComTxbf_RateWorkItemCallback,
- (PVOID)pAdapter,
- "Txbf_RateWorkItem");
-
- ODM_InitializeWorkItem(
- pDM_Odm,
- &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_StatusWorkItem),
- (RT_WORKITEM_CALL_BACK)halComTxbf_StatusWorkItemCallback,
- (PVOID)pAdapter,
- "Txbf_StatusWorkItem");
-
- ODM_InitializeWorkItem(
- pDM_Odm,
- &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_ResetTxPathWorkItem),
- (RT_WORKITEM_CALL_BACK)halComTxbf_ResetTxPathWorkItemCallback,
- (PVOID)pAdapter,
- "Txbf_ResetTxPathWorkItem");
-
- ODM_InitializeWorkItem(
- pDM_Odm,
- &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_GetTxRateWorkItem),
- (RT_WORKITEM_CALL_BACK)halComTxbf_GetTxRateWorkItemCallback,
- (PVOID)pAdapter,
- "Txbf_GetTxRateWorkItem");
-#endif
-
- ODM_InitializeWorkItem(
- pDM_Odm,
- &(pDM_Odm->Adaptivity.phydm_pauseEDCCAWorkItem),
- (RT_WORKITEM_CALL_BACK)phydm_pauseEDCCA_WorkItemCallback,
- (PVOID)pAdapter,
- "phydm_pauseEDCCAWorkItem");
-
- ODM_InitializeWorkItem(
- pDM_Odm,
- &(pDM_Odm->Adaptivity.phydm_resumeEDCCAWorkItem),
- (RT_WORKITEM_CALL_BACK)phydm_resumeEDCCA_WorkItemCallback,
- (PVOID)pAdapter,
- "phydm_resumeEDCCAWorkItem");
+ odm_initialize_work_item(
+ dm,
+ &dm->beamforming_info.txbf_info.txbf_enter_work_item,
+ (RT_WORKITEM_CALL_BACK)hal_com_txbf_enter_work_item_callback,
+ (void *)adapter,
+ "txbf_enter_work_item");
+
+ odm_initialize_work_item(
+ dm,
+ &dm->beamforming_info.txbf_info.txbf_leave_work_item,
+ (RT_WORKITEM_CALL_BACK)hal_com_txbf_leave_work_item_callback,
+ (void *)adapter,
+ "txbf_leave_work_item");
+
+ odm_initialize_work_item(
+ dm,
+ &dm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item,
+ (RT_WORKITEM_CALL_BACK)hal_com_txbf_fw_ndpa_work_item_callback,
+ (void *)adapter,
+ "txbf_fw_ndpa_work_item");
+
+ odm_initialize_work_item(
+ dm,
+ &dm->beamforming_info.txbf_info.txbf_clk_work_item,
+ (RT_WORKITEM_CALL_BACK)hal_com_txbf_clk_work_item_callback,
+ (void *)adapter,
+ "txbf_clk_work_item");
+
+ odm_initialize_work_item(
+ dm,
+ &dm->beamforming_info.txbf_info.txbf_rate_work_item,
+ (RT_WORKITEM_CALL_BACK)hal_com_txbf_rate_work_item_callback,
+ (void *)adapter,
+ "txbf_rate_work_item");
+
+ odm_initialize_work_item(
+ dm,
+ &dm->beamforming_info.txbf_info.txbf_status_work_item,
+ (RT_WORKITEM_CALL_BACK)hal_com_txbf_status_work_item_callback,
+ (void *)adapter,
+ "txbf_status_work_item");
+
+ odm_initialize_work_item(
+ dm,
+ &dm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item,
+ (RT_WORKITEM_CALL_BACK)hal_com_txbf_reset_tx_path_work_item_callback,
+ (void *)adapter,
+ "txbf_reset_tx_path_work_item");
+
+ odm_initialize_work_item(
+ dm,
+ &dm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item,
+ (RT_WORKITEM_CALL_BACK)hal_com_txbf_get_tx_rate_work_item_callback,
+ (void *)adapter,
+ "txbf_get_tx_rate_work_item");
+#endif
+
+ odm_initialize_work_item(
+ dm,
+ &dm->adaptivity.phydm_pause_edcca_work_item,
+ (RT_WORKITEM_CALL_BACK)phydm_pause_edcca_work_item_callback,
+ (void *)adapter,
+ "phydm_pause_edcca_work_item");
+
+ odm_initialize_work_item(
+ dm,
+ &dm->adaptivity.phydm_resume_edcca_work_item,
+ (RT_WORKITEM_CALL_BACK)phydm_resume_edcca_work_item_callback,
+ (void *)adapter,
+ "phydm_resume_edcca_work_item");
+
+#if (PHYDM_LA_MODE_SUPPORT == 1)
+ odm_initialize_work_item(
+ dm,
+ &dm->adcsmp.adc_smp_work_item,
+ (RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback,
+ (void *)adapter,
+ "adc_smp_work_item");
+
+ odm_initialize_work_item(
+ dm,
+ &dm->adcsmp.adc_smp_work_item_1,
+ (RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback,
+ (void *)adapter,
+ "adc_smp_work_item_1");
+#endif
}
-VOID
-ODM_FreeAllWorkItems(IN PDM_ODM_T pDM_Odm )
+void
+odm_free_all_work_items(struct dm_struct *dm)
{
#if USE_WORKITEM
#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
- ODM_FreeWorkItem(&(pDM_Odm->DM_SWAT_Table.phydm_SwAntennaSwitchWorkitem));
+ odm_free_work_item(&dm->dm_swat_table.phydm_sw_antenna_switch_workitem);
+#endif
+
+#ifdef CONFIG_DYNAMIC_RX_PATH
+ odm_free_work_item(&dm->dm_drp_table.phydm_dynamic_rx_path_workitem);
+#endif
+
+#ifdef CONFIG_ADAPTIVE_SOML
+ odm_free_work_item(&dm->dm_soml_table.phydm_adaptive_soml_workitem);
#endif
-#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
- ODM_FreeWorkItem(&(pDM_Odm->dm_sat_table.hl_smart_antenna_workitem));
- ODM_FreeWorkItem(&(pDM_Odm->dm_sat_table.hl_smart_antenna_decision_workitem));
+
+#if (defined(CONFIG_HL_SMART_ANTENNA))
+ odm_free_work_item(&dm->dm_sat_table.hl_smart_antenna_workitem);
+ odm_free_work_item(&dm->dm_sat_table.hl_smart_antenna_decision_workitem);
#endif
- ODM_FreeWorkItem(&(pDM_Odm->PathDivSwitchWorkitem));
- ODM_FreeWorkItem(&(pDM_Odm->CCKPathDiversityWorkitem));
+ odm_free_work_item(&dm->path_div_switch_workitem);
+ odm_free_work_item(&dm->cck_path_diversity_workitem);
#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
- ODM_FreeWorkItem(&(pDM_Odm->FastAntTrainingWorkitem));
+ odm_free_work_item(&dm->fast_ant_training_workitem);
#endif
- ODM_FreeWorkItem(&(pDM_Odm->MPT_DIGWorkitem));
- ODM_FreeWorkItem(&(pDM_Odm->RaRptWorkitem));
- /*ODM_FreeWorkItem((&pDM_Odm->sbdcnt_workitem));*/
+ odm_free_work_item(&dm->ra_rpt_workitem);
+ /*odm_free_work_item((&dm->sbdcnt_workitem));*/
#endif
#if (BEAMFORMING_SUPPORT == 1)
- ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_EnterWorkItem));
- ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_LeaveWorkItem));
- ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_FwNdpaWorkItem));
- ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_ClkWorkItem));
- ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_RateWorkItem));
- ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_StatusWorkItem));
- ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_ResetTxPathWorkItem));
- ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_GetTxRateWorkItem));
+ odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_enter_work_item));
+ odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_leave_work_item));
+ odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item));
+ odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_clk_work_item));
+ odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_rate_work_item));
+ odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_status_work_item));
+ odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item));
+ odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item));
#endif
- ODM_FreeWorkItem((&pDM_Odm->Adaptivity.phydm_pauseEDCCAWorkItem));
- ODM_FreeWorkItem((&pDM_Odm->Adaptivity.phydm_resumeEDCCAWorkItem));
-
-}
-#endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
-
-/*
-VOID
-odm_FindMinimumRSSI(
- IN PDM_ODM_T pDM_Odm
- )
-{
- u4Byte i;
- u1Byte RSSI_Min = 0xFF;
-
- for(i=0; ipODM_StaInfo[i] != NULL)
- if(IS_STA_VALID(pDM_Odm->pODM_StaInfo[i]) )
- {
- if(pDM_Odm->pODM_StaInfo[i]->RSSI_Ave < RSSI_Min)
- {
- RSSI_Min = pDM_Odm->pODM_StaInfo[i]->RSSI_Ave;
- }
- }
- }
-
- pDM_Odm->RSSI_Min = RSSI_Min;
-
-}
+ odm_free_work_item((&dm->adaptivity.phydm_pause_edcca_work_item));
+ odm_free_work_item((&dm->adaptivity.phydm_resume_edcca_work_item));
-VOID
-odm_IsLinked(
- IN PDM_ODM_T pDM_Odm
- )
-{
- u4Byte i;
- BOOLEAN Linked = FALSE;
-
- for(i=0; ipODM_StaInfo[i]) )
- {
- Linked = TRUE;
- break;
- }
-
- }
+#if (PHYDM_LA_MODE_SUPPORT == 1)
+ odm_free_work_item((&dm->adcsmp.adc_smp_work_item));
+ odm_free_work_item((&dm->adcsmp.adc_smp_work_item_1));
+#endif
- pDM_Odm->bLinked = Linked;
}
-*/
+#endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
-VOID
-ODM_InitAllTimers(
- IN PDM_ODM_T pDM_Odm
- )
+void
+odm_init_all_timers(
+ struct dm_struct *dm
+)
{
#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
- ODM_AntDivTimers(pDM_Odm,INIT_ANTDIV_TIMMER);
+ odm_ant_div_timers(dm, INIT_ANTDIV_TIMMER);
#endif
-#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-#ifdef MP_TEST
- if (pDM_Odm->priv->pshare->rf_ft_var.mp_specific)
- ODM_InitializeTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer,
- (RT_TIMER_CALL_BACK)odm_MPT_DIGCallback, NULL, "MPT_DIGTimer");
+ phydm_adaptive_soml_timers(dm, INIT_SOML_TIMMER);
+
+#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
+ phydm_lna_sat_chk_timers(dm, INIT_LNA_SAT_CHK_TIMMER);
#endif
-#elif(DM_ODM_SUPPORT_TYPE == ODM_WIN)
- ODM_InitializeTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer,
- (RT_TIMER_CALL_BACK)odm_MPT_DIGCallback, NULL, "MPT_DIGTimer");
+
+#ifdef CONFIG_DYNAMIC_RX_PATH
+ phydm_dynamic_rx_path_timers(dm, INIT_DRP_TIMMER);
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
- ODM_InitializeTimer(pDM_Odm, &pDM_Odm->PathDivSwitchTimer,
- (RT_TIMER_CALL_BACK)odm_PathDivChkAntSwitchCallback, NULL, "PathDivTimer");
- ODM_InitializeTimer(pDM_Odm, &pDM_Odm->CCKPathDiversityTimer,
- (RT_TIMER_CALL_BACK)odm_CCKTXPathDiversityCallback, NULL, "CCKPathDiversityTimer");
- ODM_InitializeTimer(pDM_Odm, &pDM_Odm->sbdcnt_timer,
- (RT_TIMER_CALL_BACK)phydm_sbd_callback, NULL, "SbdTimer");
+ odm_initialize_timer(dm, &dm->path_div_switch_timer,
+ (void *)odm_path_div_chk_ant_switch_callback, NULL, "PathDivTimer");
+ odm_initialize_timer(dm, &dm->cck_path_diversity_timer,
+ (void *)odm_cck_tx_path_diversity_callback, NULL, "cck_path_diversity_timer");
+ odm_initialize_timer(dm, &dm->sbdcnt_timer,
+ (void *)phydm_sbd_callback, NULL, "SbdTimer");
#if (BEAMFORMING_SUPPORT == 1)
- ODM_InitializeTimer(pDM_Odm, &pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_FwNdpaTimer,
- (RT_TIMER_CALL_BACK)halComTxbf_FwNdpaTimerCallback, NULL, "Txbf_FwNdpaTimer");
+ odm_initialize_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer,
+ (void *)hal_com_txbf_fw_ndpa_timer_callback, NULL, "txbf_fw_ndpa_timer");
#endif
#endif
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
#if (BEAMFORMING_SUPPORT == 1)
- ODM_InitializeTimer(pDM_Odm, &pDM_Odm->BeamformingInfo.BeamformingTimer,
- (RT_TIMER_CALL_BACK)Beamforming_SWTimerCallback, NULL, "BeamformingTimer");
+ odm_initialize_timer(dm, &dm->beamforming_info.beamforming_timer,
+ (void *)beamforming_sw_timer_callback, NULL, "beamforming_timer");
#endif
#endif
}
-VOID
-ODM_CancelAllTimers(
- IN PDM_ODM_T pDM_Odm
- )
+void
+odm_cancel_all_timers(
+ struct dm_struct *dm
+)
{
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
- //
- // 2012/01/12 MH Temp BSOD fix. We need to find NIC allocate mem fail reason in
- // win7 platform.
- //
- HAL_ADAPTER_STS_CHK(pDM_Odm)
-#endif
+ /* 2012/01/12 MH Temp BSOD fix. We need to find NIC allocate mem fail reason in win7*/
+ if (dm->adapter == NULL)
+ return;
+#endif
#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
- ODM_AntDivTimers(pDM_Odm,CANCEL_ANTDIV_TIMMER);
+ odm_ant_div_timers(dm, CANCEL_ANTDIV_TIMMER);
#endif
-#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-#ifdef MP_TEST
- if (pDM_Odm->priv->pshare->rf_ft_var.mp_specific)
- ODM_CancelTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer);
+ phydm_adaptive_soml_timers(dm, CANCEL_SOML_TIMMER);
+
+#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
+ phydm_lna_sat_chk_timers(dm, CANCEL_LNA_SAT_CHK_TIMMER);
#endif
-#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
- ODM_CancelTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer);
+
+
+#ifdef CONFIG_DYNAMIC_RX_PATH
+ phydm_dynamic_rx_path_timers(dm, CANCEL_DRP_TIMMER);
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
- ODM_CancelTimer(pDM_Odm, &pDM_Odm->PathDivSwitchTimer);
- ODM_CancelTimer(pDM_Odm, &pDM_Odm->CCKPathDiversityTimer);
- ODM_CancelTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer);
- ODM_CancelTimer(pDM_Odm, &pDM_Odm->sbdcnt_timer);
+ odm_cancel_timer(dm, &dm->path_div_switch_timer);
+ odm_cancel_timer(dm, &dm->cck_path_diversity_timer);
+ odm_cancel_timer(dm, &dm->sbdcnt_timer);
#if (BEAMFORMING_SUPPORT == 1)
- ODM_CancelTimer(pDM_Odm, &pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_FwNdpaTimer);
+ odm_cancel_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer);
#endif
#endif
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
#if (BEAMFORMING_SUPPORT == 1)
- ODM_CancelTimer(pDM_Odm, &pDM_Odm->BeamformingInfo.BeamformingTimer);
+ odm_cancel_timer(dm, &dm->beamforming_info.beamforming_timer);
#endif
#endif
}
-VOID
-ODM_ReleaseAllTimers(
- IN PDM_ODM_T pDM_Odm
- )
+void
+odm_release_all_timers(
+ struct dm_struct *dm
+)
{
#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
- ODM_AntDivTimers(pDM_Odm,RELEASE_ANTDIV_TIMMER);
+ odm_ant_div_timers(dm, RELEASE_ANTDIV_TIMMER);
#endif
+ phydm_adaptive_soml_timers(dm, RELEASE_SOML_TIMMER);
-#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
- #ifdef MP_TEST
- if (pDM_Odm->priv->pshare->rf_ft_var.mp_specific)
- ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer);
- #endif
-#elif(DM_ODM_SUPPORT_TYPE == ODM_WIN)
-ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer);
+#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
+ phydm_lna_sat_chk_timers(dm, RELEASE_LNA_SAT_CHK_TIMMER);
#endif
-#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
- ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->PathDivSwitchTimer);
- ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->CCKPathDiversityTimer);
- ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer);
- ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->sbdcnt_timer);
-#if (BEAMFORMING_SUPPORT == 1)
- ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_FwNdpaTimer);
-#endif
+#ifdef CONFIG_DYNAMIC_RX_PATH
+ phydm_dynamic_rx_path_timers(dm, RELEASE_DRP_TIMMER);
#endif
-#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+ odm_release_timer(dm, &dm->path_div_switch_timer);
+ odm_release_timer(dm, &dm->cck_path_diversity_timer);
+ odm_release_timer(dm, &dm->sbdcnt_timer);
#if (BEAMFORMING_SUPPORT == 1)
- ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->BeamformingInfo.BeamformingTimer);
-#endif
-#endif
-}
-
-
-//3============================================================
-//3 Tx Power Tracking
-//3============================================================
-
-
-
-
-#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-VOID
-ODM_InitAllThreads(
- IN PDM_ODM_T pDM_Odm
- )
-{
- #ifdef TPT_THREAD
- kTPT_task_init(pDM_Odm->priv);
- #endif
-}
-
-VOID
-ODM_StopAllThreads(
- IN PDM_ODM_T pDM_Odm
- )
-{
- #ifdef TPT_THREAD
- kTPT_task_stop(pDM_Odm->priv);
- #endif
-}
-#endif
-
-
-#if( DM_ODM_SUPPORT_TYPE == ODM_WIN)
-//
-// 2011/07/26 MH Add an API for testing IQK fail case.
-//
-BOOLEAN
-ODM_CheckPowerStatus(
- IN PADAPTER Adapter)
-{
-
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
- PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
- RT_RF_POWER_STATE rtState;
- PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
-
- // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence.
- if (pMgntInfo->init_adpt_in_progress == TRUE)
- {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter\n"));
- return TRUE;
- }
-
- //
- // 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK.
- //
- Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState));
- if(Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff)
- {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n",
- Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState));
- return FALSE;
- }
- return TRUE;
-}
-#elif( DM_ODM_SUPPORT_TYPE == ODM_AP)
-BOOLEAN
-ODM_CheckPowerStatus(
- IN PADAPTER Adapter)
-{
- /*
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
- PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
- RT_RF_POWER_STATE rtState;
- PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
-
- // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence.
- if (pMgntInfo->init_adpt_in_progress == TRUE)
- {
- ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter"));
- return TRUE;
- }
-
- //
- // 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK.
- //
- Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState));
- if(Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff)
- {
- ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n",
- Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState));
- return FALSE;
- }
- */
- return TRUE;
-}
-#endif
-
-// need to ODM CE Platform
-//move to here for ANT detection mechanism using
-
-#if ((DM_ODM_SUPPORT_TYPE == ODM_WIN)||(DM_ODM_SUPPORT_TYPE == ODM_CE))
-u4Byte
-GetPSDData(
- IN PDM_ODM_T pDM_Odm,
- unsigned int point,
- u1Byte initial_gain_psd)
-{
- //unsigned int val, rfval;
- //int psd_report;
- u4Byte psd_report;
-
- //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
- //Debug Message
- //val = PHY_QueryBBReg(Adapter,0x908, bMaskDWord);
- //DbgPrint("Reg908 = 0x%x\n",val);
- //val = PHY_QueryBBReg(Adapter,0xDF4, bMaskDWord);
- //rfval = PHY_QueryRFReg(Adapter, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask);
- //DbgPrint("RegDF4 = 0x%x, RFReg00 = 0x%x\n",val, rfval);
- //DbgPrint("PHYTXON = %x, OFDMCCA_PP = %x, CCKCCA_PP = %x, RFReg00 = %x\n",
- //(val&BIT25)>>25, (val&BIT14)>>14, (val&BIT15)>>15, rfval);
-
- //Set DCO frequency index, offset=(40MHz/SamplePts)*point
- ODM_SetBBReg(pDM_Odm, 0x808, 0x3FF, point);
-
- //Start PSD calculation, Reg808[22]=0->1
- ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 1);
- //Need to wait for HW PSD report
- ODM_StallExecution(1000);
- ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 0);
- //Read PSD report, Reg8B4[15:0]
- psd_report = ODM_GetBBReg(pDM_Odm,0x8B4, bMaskDWord) & 0x0000FFFF;
-
-#if 1//(DEV_BUS_TYPE == RT_PCI_INTERFACE) && ( (RT_PLATFORM == PLATFORM_LINUX) || (RT_PLATFORM == PLATFORM_MACOSX))
- psd_report = (u4Byte) (odm_ConvertTo_dB(psd_report))+(u4Byte)(initial_gain_psd-0x1c);
-#else
- psd_report = (int) (20*log10((double)psd_report))+(int)(initial_gain_psd-0x1c);
+ odm_release_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer);
#endif
-
- return psd_report;
-
-}
#endif
-u4Byte
-odm_ConvertTo_dB(
- u4Byte Value)
-{
- u1Byte i;
- u1Byte j;
- u4Byte dB;
-
- Value = Value & 0xFFFF;
-
- for (i = 0; i < 12; i++)
- {
- if (Value <= dB_Invert_Table[i][7])
- {
- break;
- }
- }
-
- if (i >= 12)
- {
- return (96); // maximum 96 dB
- }
-
- for (j = 0; j < 8; j++)
- {
- if (Value <= dB_Invert_Table[i][j])
- {
- break;
- }
- }
-
- dB = (i << 3) + j + 1;
-
- return (dB);
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+#if (BEAMFORMING_SUPPORT == 1)
+ odm_release_timer(dm, &dm->beamforming_info.beamforming_timer);
+#endif
+#endif
}
-u4Byte
-odm_ConvertTo_linear(
- u4Byte Value)
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+void
+odm_init_all_threads(
+ struct dm_struct *dm
+)
{
- u1Byte i;
- u1Byte j;
- u4Byte linear;
-
- /* 1dB~96dB */
-
- Value = Value & 0xFF;
-
- i = (u1Byte)((Value - 1) >> 3);
- j = (u1Byte)(Value - 1) - (i << 3);
-
- linear = dB_Invert_Table[i][j];
-
- return (linear);
+#ifdef TPT_THREAD
+ k_tpt_task_init(dm->priv);
+#endif
}
-//
-// ODM multi-port consideration, added by Roger, 2013.10.01.
-//
-VOID
-ODM_AsocEntry_Init(
- IN PDM_ODM_T pDM_Odm
- )
+void
+odm_stop_all_threads(
+ struct dm_struct *dm
+)
{
-#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
- PADAPTER pLoopAdapter = GetDefaultAdapter(pDM_Odm->Adapter);
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pLoopAdapter);
- PDM_ODM_T pDM_OutSrc = &pHalData->DM_OutSrc;
- u1Byte TotalAssocEntryNum = 0;
- u1Byte index = 0;
- u1Byte adaptercount = 0;
-
- ODM_CmnInfoPtrArrayHook(pDM_OutSrc, ODM_CMNINFO_STA_STATUS, 0, &pLoopAdapter->MgntInfo.DefaultPort[0]);
- pLoopAdapter->MgntInfo.DefaultPort[0].MultiPortStationIdx = TotalAssocEntryNum;
-
- adaptercount += 1;
- RT_TRACE(COMP_INIT, DBG_LOUD, ("adaptercount=%d\n", adaptercount));
- pLoopAdapter = GetNextExtAdapter(pLoopAdapter);
- TotalAssocEntryNum +=1;
-
- while(pLoopAdapter)
- {
- for (index = 0; index MgntInfo.AsocEntry[index]);
- pLoopAdapter->MgntInfo.AsocEntry[index].MultiPortStationIdx = TotalAssocEntryNum+index;
- }
-
- TotalAssocEntryNum+= index;
- if(IS_HARDWARE_TYPE_8188E((pDM_Odm->Adapter)))
- pLoopAdapter->RASupport = TRUE;
- adaptercount += 1;
- RT_TRACE(COMP_INIT, DBG_LOUD, ("adaptercount=%d\n", adaptercount));
- pLoopAdapter = GetNextExtAdapter(pLoopAdapter);
- }
-
- RT_TRACE(COMP_INIT, DBG_LOUD, ("TotalAssocEntryNum = %d\n", TotalAssocEntryNum));
- if (TotalAssocEntryNum < (ODM_ASSOCIATE_ENTRY_NUM-1)) {
-
- RT_TRACE(COMP_INIT, DBG_LOUD, ("In hook null\n"));
- for (index = TotalAssocEntryNum; index < ODM_ASSOCIATE_ENTRY_NUM; index++)
- ODM_CmnInfoPtrArrayHook(pDM_OutSrc, ODM_CMNINFO_STA_STATUS, index, NULL);
- }
+#ifdef TPT_THREAD
+ k_tpt_task_stop(dm->priv);
#endif
}
+#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
/* Justin: According to the current RRSI to adjust Response Frame TX power, 2012/11/05 */
-void odm_dtc(PDM_ODM_T pDM_Odm)
+void odm_dtc(struct dm_struct *dm)
{
#ifdef CONFIG_DM_RESP_TXAGC
- #define DTC_BASE 35 /* RSSI higher than this value, start to decade TX power */
- #define DTC_DWN_BASE (DTC_BASE-5) /* RSSI lower than this value, start to increase TX power */
+#define DTC_BASE 35 /* RSSI higher than this value, start to decade TX power */
+#define DTC_DWN_BASE (DTC_BASE-5) /* RSSI lower than this value, start to increase TX power */
/* RSSI vs TX power step mapping: decade TX power */
- static const u8 dtc_table_down[]={
+ static const u8 dtc_table_down[] = {
DTC_BASE,
- (DTC_BASE+5),
- (DTC_BASE+10),
- (DTC_BASE+15),
- (DTC_BASE+20),
- (DTC_BASE+25)
+ (DTC_BASE + 5),
+ (DTC_BASE + 10),
+ (DTC_BASE + 15),
+ (DTC_BASE + 20),
+ (DTC_BASE + 25)
};
/* RSSI vs TX power step mapping: increase TX power */
- static const u8 dtc_table_up[]={
+ static const u8 dtc_table_up[] = {
DTC_DWN_BASE,
- (DTC_DWN_BASE-5),
- (DTC_DWN_BASE-10),
- (DTC_DWN_BASE-15),
- (DTC_DWN_BASE-15),
- (DTC_DWN_BASE-20),
- (DTC_DWN_BASE-20),
- (DTC_DWN_BASE-25),
- (DTC_DWN_BASE-25),
- (DTC_DWN_BASE-30),
- (DTC_DWN_BASE-35)
+ (DTC_DWN_BASE - 5),
+ (DTC_DWN_BASE - 10),
+ (DTC_DWN_BASE - 15),
+ (DTC_DWN_BASE - 15),
+ (DTC_DWN_BASE - 20),
+ (DTC_DWN_BASE - 20),
+ (DTC_DWN_BASE - 25),
+ (DTC_DWN_BASE - 25),
+ (DTC_DWN_BASE - 30),
+ (DTC_DWN_BASE - 35)
};
u8 i;
- u8 dtc_steps=0;
+ u8 dtc_steps = 0;
u8 sign;
- u8 resp_txagc=0;
+ u8 resp_txagc = 0;
- #if 0
+#if 0
/* As DIG is disabled, DTC is also disable */
- if(!(pDM_Odm->SupportAbility & ODM_XXXXXX))
+ if (!(dm->support_ability & ODM_XXXXXX))
return;
- #endif
+#endif
- if (DTC_BASE < pDM_Odm->RSSI_Min) {
+ if (dm->rssi_min > DTC_BASE) {
/* need to decade the CTS TX power */
sign = 1;
- for (i=0;i= pDM_Odm->RSSI_Min) || (dtc_steps >= 6))
+ for (i = 0; i < ARRAY_SIZE(dtc_table_down); i++) {
+ if ((dtc_table_down[i] >= dm->rssi_min) || (dtc_steps >= 6))
break;
else
dtc_steps++;
}
}
#if 0
- else if (DTC_DWN_BASE > pDM_Odm->RSSI_Min)
- {
+ else if (dm->rssi_min > DTC_DWN_BASE) {
/* needs to increase the CTS TX power */
sign = 0;
dtc_steps = 1;
- for (i=0;iRSSI_Min) || (dtc_steps>=10))
+ for (i = 0; i < ARRAY_SIZE(dtc_table_up); i++) {
+ if ((dtc_table_up[i] <= dm->rssi_min) || (dtc_steps >= 10))
break;
else
dtc_steps++;
}
}
#endif
- else
- {
+ else {
sign = 0;
dtc_steps = 0;
}
resp_txagc = dtc_steps | (sign << 4);
resp_txagc = resp_txagc | (resp_txagc << 5);
- ODM_Write1Byte(pDM_Odm, 0x06d9, resp_txagc);
+ odm_write_1byte(dm, 0x06d9, resp_txagc);
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_PWR_TRAIN, ODM_DBG_LOUD, ("%s RSSI_Min:%u, set RESP_TXAGC to %s %u\n",
- __func__, pDM_Odm->RSSI_Min, sign ? "minus" : "plus", dtc_steps));
+ PHYDM_DBG(dm, ODM_COMP_PWR_TRAIN, "%s rssi_min:%u, set RESP_TXAGC to %s %u\n",
+ __func__, dm->rssi_min, sign ? "minus" : "plus", dtc_steps);
#endif /* CONFIG_RESP_TXAGC_ADJUST */
}
#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */
-VOID
-odm_UpdatePowerTrainingState(
- IN PDM_ODM_T pDM_Odm
- )
-{
-#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
- PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm , PHYDM_FALSEALMCNT);
- pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
- u4Byte score = 0;
-
- if(!(pDM_Odm->SupportAbility & ODM_BB_PWR_TRAIN))
- return;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState()============>\n"));
- pDM_Odm->bChangeState = FALSE;
+/*<20170126, BB-Kevin>8188F D-CUT DC cancellation and 8821C*/
+void
+phydm_dc_cancellation(
+ struct dm_struct *dm
- // Debug command
- if(pDM_Odm->ForcePowerTrainingState)
- {
- if(pDM_Odm->ForcePowerTrainingState == 1 && !pDM_Odm->bDisablePowerTraining)
- {
- pDM_Odm->bChangeState = TRUE;
- pDM_Odm->bDisablePowerTraining = TRUE;
- }
- else if(pDM_Odm->ForcePowerTrainingState == 2 && pDM_Odm->bDisablePowerTraining)
- {
- pDM_Odm->bChangeState = TRUE;
- pDM_Odm->bDisablePowerTraining = FALSE;
- }
+)
+{
+#ifdef PHYDM_DC_CANCELLATION
+ u32 offset_i_hex[PHYDM_MAX_RF_PATH] = {0};
+ u32 offset_q_hex[PHYDM_MAX_RF_PATH] = {0};
+ u32 reg_value32[PHYDM_MAX_RF_PATH] = {0};
+ u8 path = RF_PATH_A;
- pDM_Odm->PT_score = 0;
- pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM = 0;
- pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK = 0;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): ForcePowerTrainingState = %d\n",
- pDM_Odm->ForcePowerTrainingState));
- return;
- }
-
- if(!pDM_Odm->bLinked)
- return;
-
- // First connect
- if((pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == FALSE))
- {
- pDM_Odm->PT_score = 0;
- pDM_Odm->bChangeState = TRUE;
- pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM = 0;
- pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK = 0;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): First Connect\n"));
+ if (!(dm->support_ic_type & ODM_DC_CANCELLATION_SUPPORT))
return;
- }
-
- // Compute score
- if(pDM_Odm->NHM_cnt_0 >= 215)
- score = 2;
- else if(pDM_Odm->NHM_cnt_0 >= 190)
- score = 1; // unknow state
- else
- {
- u4Byte RX_Pkt_Cnt;
-
- RX_Pkt_Cnt = (u4Byte)(pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM) + (u4Byte)(pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK);
-
- if((FalseAlmCnt->Cnt_CCA_all > 31 && RX_Pkt_Cnt > 31) && (FalseAlmCnt->Cnt_CCA_all >= RX_Pkt_Cnt))
- {
- if((RX_Pkt_Cnt + (RX_Pkt_Cnt >> 1)) <= FalseAlmCnt->Cnt_CCA_all)
- score = 0;
- else if((RX_Pkt_Cnt + (RX_Pkt_Cnt >> 2)) <= FalseAlmCnt->Cnt_CCA_all)
- score = 1;
- else
- score = 2;
- }
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): RX_Pkt_Cnt = %d, Cnt_CCA_all = %d\n",
- RX_Pkt_Cnt, FalseAlmCnt->Cnt_CCA_all));
- }
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): NumQryPhyStatusOFDM = %d, NumQryPhyStatusCCK = %d\n",
- (u4Byte)(pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM), (u4Byte)(pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK)));
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): NHM_cnt_0 = %d, score = %d\n",
- pDM_Odm->NHM_cnt_0, score));
-
- // smoothing
- pDM_Odm->PT_score = (score << 4) + (pDM_Odm->PT_score>>1) + (pDM_Odm->PT_score>>2);
- score = (pDM_Odm->PT_score + 32) >> 6;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): PT_score = %d, score after smoothing = %d\n",
- pDM_Odm->PT_score, score));
-
- // Mode decision
- if(score == 2)
- {
- if(pDM_Odm->bDisablePowerTraining)
- {
- pDM_Odm->bChangeState = TRUE;
- pDM_Odm->bDisablePowerTraining = FALSE;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): Change state\n"));
- }
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): Enable Power Training\n"));
- }
- else if(score == 0)
- {
- if(!pDM_Odm->bDisablePowerTraining)
- {
- pDM_Odm->bChangeState = TRUE;
- pDM_Odm->bDisablePowerTraining = TRUE;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): Change state\n"));
- }
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): Disable Power Training\n"));
- }
-
- pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM = 0;
- pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK = 0;
-#endif
-}
-
-
-/*===========================================================*/
-/* The following is for compile only*/
-/*===========================================================*/
-/*#define TARGET_CHNL_NUM_2G_5G 59*/
-#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+ if ((dm->support_ic_type & ODM_RTL8188F) && (dm->cut_version < ODM_CUT_D))
+ return;
-u1Byte GetRightChnlPlaceforIQK(u1Byte chnl)
-{
- u1Byte channel_all[TARGET_CHNL_NUM_2G_5G] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100,
- 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, 161, 163, 165};
- u1Byte place = chnl;
+ /*DC_Estimation (only for 2x2 ic now) */
-
- if (chnl > 14) {
- for (place = 14; place < sizeof(channel_all); place++) {
- if (channel_all[place] == chnl)
- return place-13;
+ for (path = RF_PATH_A; path < PHYDM_MAX_RF_PATH; path++) {
+ if (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8710B)) {
+ if (!phydm_set_bb_dbg_port(dm,
+ BB_DBGPORT_PRIORITY_2, 0x235)) {/*set debug port to 0x235*/
+ PHYDM_DBG(dm, ODM_COMP_API,
+ "[DC Cancellation] Set Debug port Fail");
+ return;
+ }
+ } else if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B)) {
+ if (!phydm_set_bb_dbg_port(dm, BB_DBGPORT_PRIORITY_2, 0x200)) {
+ /*set debug port to 0x200*/
+ PHYDM_DBG(dm, ODM_COMP_API,
+ "[DC Cancellation] Set Debug port Fail");
+ return;
+ }
+ phydm_bb_dbg_port_header_sel(dm, 0x0);
+ if (dm->rf_type > RF_1T1R) {
+ if (!phydm_set_bb_dbg_port(dm, BB_DBGPORT_PRIORITY_2, 0x202)) {
+ /*set debug port to 0x200*/
+ PHYDM_DBG(dm, ODM_COMP_API,
+ "[DC Cancellation] Set Debug port Fail");
+ return;
+ }
+ phydm_bb_dbg_port_header_sel(dm, 0x0);
+ }
}
- }
-
- return 0;
-}
-
-#endif
-/*===========================================================*/
-
-VOID
-phydm_NoisyDetection(
- IN PDM_ODM_T pDM_Odm
- )
-{
- u4Byte Total_FA_Cnt, Total_CCA_Cnt;
- u4Byte Score = 0, i, Score_Smooth;
-
- Total_CCA_Cnt = pDM_Odm->FalseAlmCnt.Cnt_CCA_all;
- Total_FA_Cnt = pDM_Odm->FalseAlmCnt.Cnt_all;
-
-/*
- if( Total_FA_Cnt*16>=Total_CCA_Cnt*14 ) // 87.5
-
- else if( Total_FA_Cnt*16>=Total_CCA_Cnt*12 ) // 75
-
- else if( Total_FA_Cnt*16>=Total_CCA_Cnt*10 ) // 56.25
-
- else if( Total_FA_Cnt*16>=Total_CCA_Cnt*8 ) // 50
-
- else if( Total_FA_Cnt*16>=Total_CCA_Cnt*7 ) // 43.75
-
- else if( Total_FA_Cnt*16>=Total_CCA_Cnt*6 ) // 37.5
-
- else if( Total_FA_Cnt*16>=Total_CCA_Cnt*5 ) // 31.25%
-
- else if( Total_FA_Cnt*16>=Total_CCA_Cnt*4 ) // 25%
-
- else if( Total_FA_Cnt*16>=Total_CCA_Cnt*3 ) // 18.75%
-
- else if( Total_FA_Cnt*16>=Total_CCA_Cnt*2 ) // 12.5%
-
- else if( Total_FA_Cnt*16>=Total_CCA_Cnt*1 ) // 6.25%
-*/
- for(i=0;i<=16;i++)
- {
- if( Total_FA_Cnt*16>=Total_CCA_Cnt*(16-i) )
- {
- Score = 16-i;
- break;
- }
- }
-
- // NoisyDecision_Smooth = NoisyDecision_Smooth>>1 + (Score<<3)>>1;
- pDM_Odm->NoisyDecision_Smooth = (pDM_Odm->NoisyDecision_Smooth>>1) + (Score<<2);
-
- // Round the NoisyDecision_Smooth: +"3" comes from (2^3)/2-1
- Score_Smooth = (Total_CCA_Cnt>=300)?((pDM_Odm->NoisyDecision_Smooth+3)>>3):0;
-
- pDM_Odm->NoisyDecision = (Score_Smooth>=3)?1:0;
-/*
- switch(Score_Smooth)
- {
- case 0:
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,
- ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=0%%\n"));
- break;
- case 1:
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,
- ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=6.25%%\n"));
- break;
- case 2:
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,
- ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=12.5%%\n"));
- break;
- case 3:
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,
- ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=18.75%%\n"));
- break;
- case 4:
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,
- ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=25%%\n"));
- break;
- case 5:
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,
- ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=31.25%%\n"));
- break;
- case 6:
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,
- ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=37.5%%\n"));
- break;
- case 7:
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,
- ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=43.75%%\n"));
- break;
- case 8:
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,
- ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=50%%\n"));
- break;
- case 9:
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,
- ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=56.25%%\n"));
- break;
- case 10:
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,
- ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=62.5%%\n"));
- break;
- case 11:
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,
- ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=68.75%%\n"));
- break;
- case 12:
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,
- ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=75%%\n"));
- break;
- case 13:
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,
- ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=81.25%%\n"));
- break;
- case 14:
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,
- ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=87.5%%\n"));
- break;
- case 15:
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,
- ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=93.75%%\n"));
- break;
- case 16:
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,
- ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=100%%\n"));
- break;
- default:
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,
- ("[NoisyDetection] Unknown Value!! Need Check!!\n"));
- }
-*/
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_NOISY_DETECT, ODM_DBG_LOUD,
- ("[NoisyDetection] Total_CCA_Cnt=%d, Total_FA_Cnt=%d, NoisyDecision_Smooth=%d, Score=%d, Score_Smooth=%d, pDM_Odm->NoisyDecision=%d\n",
- Total_CCA_Cnt, Total_FA_Cnt, pDM_Odm->NoisyDecision_Smooth, Score, Score_Smooth, pDM_Odm->NoisyDecision));
-
-}
-
-VOID
-phydm_csi_mask_enable(
- IN PVOID pDM_VOID,
- IN u4Byte enable
-)
-{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- u4Byte reg_value = 0;
-
- reg_value = (enable == CSI_MASK_ENABLE) ? 1 : 0;
-
- if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
-
- ODM_SetBBReg(pDM_Odm, 0xD2C, BIT28, reg_value);
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable CSI Mask: Reg 0xD2C[28] = ((0x%x))\n", reg_value));
-
- } else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
-
- ODM_SetBBReg(pDM_Odm, 0x874, BIT0, reg_value);
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable CSI Mask: Reg 0x874[0] = ((0x%x))\n", reg_value));
- }
-
-}
-
-VOID
-phydm_clean_all_csi_mask(
- IN PVOID pDM_VOID
-)
-{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
-
- if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
-
- ODM_SetBBReg(pDM_Odm, 0xD40, bMaskDWord, 0);
- ODM_SetBBReg(pDM_Odm, 0xD44, bMaskDWord, 0);
- ODM_SetBBReg(pDM_Odm, 0xD48, bMaskDWord, 0);
- ODM_SetBBReg(pDM_Odm, 0xD4c, bMaskDWord, 0);
-
- } else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
-
- ODM_SetBBReg(pDM_Odm, 0x880, bMaskDWord, 0);
- ODM_SetBBReg(pDM_Odm, 0x884, bMaskDWord, 0);
- ODM_SetBBReg(pDM_Odm, 0x888, bMaskDWord, 0);
- ODM_SetBBReg(pDM_Odm, 0x88c, bMaskDWord, 0);
- ODM_SetBBReg(pDM_Odm, 0x890, bMaskDWord, 0);
- ODM_SetBBReg(pDM_Odm, 0x894, bMaskDWord, 0);
- ODM_SetBBReg(pDM_Odm, 0x898, bMaskDWord, 0);
- ODM_SetBBReg(pDM_Odm, 0x89c, bMaskDWord, 0);
- }
-}
-
-VOID
-phydm_set_csi_mask_reg(
- IN PVOID pDM_VOID,
- IN u4Byte tone_idx_tmp,
- IN u1Byte tone_direction
-)
-{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- u1Byte byte_offset, bit_offset;
- u4Byte target_reg;
- u1Byte reg_tmp_value;
- u4Byte tone_num = 64;
- u4Byte tone_num_shift = 0;
- u4Byte csi_mask_reg_p = 0, csi_mask_reg_n = 0;
-
- /* calculate real tone idx*/
- if ((tone_idx_tmp % 10) >= 5)
- tone_idx_tmp += 10;
-
- tone_idx_tmp = (tone_idx_tmp/10);
-
- if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
-
- tone_num = 64;
- csi_mask_reg_p = 0xD40;
- csi_mask_reg_n = 0xD48;
-
- } else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
-
- tone_num = 128;
- csi_mask_reg_p = 0x880;
- csi_mask_reg_n = 0x890;
- }
-
- if (tone_direction == FREQ_POSITIVE) {
-
- if (tone_idx_tmp >= (tone_num - 1))
- tone_idx_tmp = (tone_num - 1);
-
- byte_offset = (u1Byte)(tone_idx_tmp >> 3);
- bit_offset = (u1Byte)(tone_idx_tmp & 0x7);
- target_reg = csi_mask_reg_p + byte_offset;
-
- } else {
- tone_num_shift = tone_num;
-
- if (tone_idx_tmp >= tone_num)
- tone_idx_tmp = tone_num;
-
- tone_idx_tmp = tone_num - tone_idx_tmp;
-
- byte_offset = (u1Byte)(tone_idx_tmp >> 3);
- bit_offset = (u1Byte)(tone_idx_tmp & 0x7);
- target_reg = csi_mask_reg_n + byte_offset;
- }
- reg_tmp_value = ODM_Read1Byte(pDM_Odm, target_reg);
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("Pre Mask tone idx[%d]: Reg0x%x = ((0x%x))\n", (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value));
- reg_tmp_value |= BIT(bit_offset);
- ODM_Write1Byte(pDM_Odm, target_reg, reg_tmp_value);
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("New Mask tone idx[%d]: Reg0x%x = ((0x%x))\n", (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value));
-}
-
-VOID
-phydm_set_nbi_reg(
- IN PVOID pDM_VOID,
- IN u4Byte tone_idx_tmp,
- IN u4Byte bw
-)
-{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- u4Byte nbi_table_128[NBI_TABLE_SIZE_128] = {25, 55, 85, 115, 135, 155, 185, 205, 225, 245, /*1~10*/ /*tone_idx X 10*/
- 265, 285, 305, 335, 355, 375, 395, 415, 435, 455, /*11~20*/
- 485, 505, 525, 555, 585, 615, 635}; /*21~27*/
+ odm_write_dig(dm, 0x7E);
- u4Byte nbi_table_256[NBI_TABLE_SIZE_256] = { 25, 55, 85, 115, 135, 155, 175, 195, 225, 245, /*1~10*/
- 265, 285, 305, 325, 345, 365, 385, 405, 425, 445, /*11~20*/
- 465, 485, 505, 525, 545, 565, 585, 605, 625, 645, /*21~30*/
- 665, 695, 715, 735, 755, 775, 795, 815, 835, 855, /*31~40*/
- 875, 895, 915, 935, 955, 975, 995, 1015, 1035, 1055, /*41~50*/
- 1085, 1105, 1125, 1145, 1175, 1195, 1225, 1255, 1275}; /*51~59*/
-
- u4Byte reg_idx = 0;
- u4Byte i;
- u1Byte nbi_table_idx = FFT_128_TYPE;
-
- if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
-
- nbi_table_idx = FFT_128_TYPE;
- } else if (pDM_Odm->SupportICType & ODM_IC_11AC_1_SERIES) {
-
- nbi_table_idx = FFT_256_TYPE;
- } else if (pDM_Odm->SupportICType & ODM_IC_11AC_2_SERIES) {
-
- if (bw == 80)
- nbi_table_idx = FFT_256_TYPE;
- else /*20M, 40M*/
- nbi_table_idx = FFT_128_TYPE;
- }
-
- if (nbi_table_idx == FFT_128_TYPE) {
-
- for (i = 0; i < NBI_TABLE_SIZE_128; i++) {
- if (tone_idx_tmp < nbi_table_128[i]) {
- reg_idx = i+1;
- break;
- }
+ if (dm->support_ic_type & ODM_IC_11N_SERIES)
+ odm_set_bb_reg(dm, 0x88c, BIT(21)|BIT(20), 0x3);
+ else {
+ odm_set_bb_reg(dm, 0xc00, BIT(1)|BIT(0), 0x0);
+ if (dm->rf_type > RF_1T1R)
+ odm_set_bb_reg(dm, 0xe00, BIT(1)|BIT(0), 0x0);
}
-
- } else if (nbi_table_idx == FFT_256_TYPE) {
-
- for (i = 0; i < NBI_TABLE_SIZE_256; i++) {
- if (tone_idx_tmp < nbi_table_256[i]) {
- reg_idx = i+1;
- break;
- }
- }
- }
-
- if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
- ODM_SetBBReg(pDM_Odm, 0xc40, 0x1f000000, reg_idx);
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("Set tone idx: Reg0xC40[28:24] = ((0x%x))\n", reg_idx));
- /**/
- } else {
- ODM_SetBBReg(pDM_Odm, 0x87c, 0xfc000, reg_idx);
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("Set tone idx: Reg0x87C[19:14] = ((0x%x))\n", reg_idx));
- /**/
- }
-}
-
-
-VOID
-phydm_nbi_enable(
- IN PVOID pDM_VOID,
- IN u4Byte enable
-)
-{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- u4Byte reg_value = 0;
-
- reg_value = (enable == NBI_ENABLE) ? 1 : 0;
+ odm_set_bb_reg(dm, 0xa78, MASKBYTE1, 0x0); /*disable CCK DCNF*/
+
+ PHYDM_DBG(dm, ODM_COMP_API, "DC cancellation Begin!!!");
- if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
+ phydm_stop_ck320(dm, true); /*stop ck320*/
- ODM_SetBBReg(pDM_Odm, 0xc40, BIT9, reg_value);
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable NBI Reg0xC40[9] = ((0x%x))\n", reg_value));
-
- } else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
+ /* the same debug port both for path-a and path-b*/
+ reg_value32[path] = phydm_get_bb_dbg_port_value(dm);
- ODM_SetBBReg(pDM_Odm, 0x87c, BIT13, reg_value);
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable NBI Reg0x87C[13] = ((0x%x))\n", reg_value));
- }
-}
+ phydm_stop_ck320(dm, false); /*start ck320*/
-u1Byte
-phydm_calculate_fc(
- IN PVOID pDM_VOID,
- IN u4Byte channel,
- IN u4Byte bw,
- IN u4Byte Second_ch,
- IN OUT u4Byte *fc_in
-)
-{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- u4Byte fc = *fc_in;
- u4Byte start_ch_per_40m[NUM_START_CH_40M] = {36, 44, 52, 60, 100, 108, 116, 124, 132, 140, 149, 157, 165, 173};
- u4Byte start_ch_per_80m[NUM_START_CH_80M] = {36, 52, 100, 116, 132, 149, 165};
- pu4Byte p_start_ch = &(start_ch_per_40m[0]);
- u4Byte num_start_channel = NUM_START_CH_40M;
- u4Byte channel_offset = 0;
- u4Byte i;
-
- /*2.4G*/
- if (channel <= 14 && channel > 0) {
-
- if (bw == 80) {
- return SET_ERROR;
+ if (dm->support_ic_type & ODM_IC_11N_SERIES) {
+ odm_set_bb_reg(dm, 0x88c, BIT(21)|BIT(20), 0x0);
+ } else {
+ odm_set_bb_reg(dm, 0xc00, BIT(1)|BIT(0), 0x3);
+ odm_set_bb_reg(dm, 0xe00, BIT(1)|BIT(0), 0x3);
}
+ odm_write_dig(dm, 0x20);
+ phydm_release_bb_dbg_port(dm);
- fc = 2412 + (channel - 1)*5;
-
- if (bw == 40 && (Second_ch == PHYDM_ABOVE)) {
-
- if (channel >= 10) {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("CH = ((%d)), Scnd_CH = ((%d)) Error Setting\n", channel, Second_ch));
- return SET_ERROR;
- }
- fc += 10;
- } else if (bw == 40 && (Second_ch == PHYDM_BELOW)) {
-
- if (channel <= 2) {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("CH = ((%d)), Scnd_CH = ((%d)) Error Setting\n", channel, Second_ch));
- return SET_ERROR;
- }
- fc -= 10;
- }
+ PHYDM_DBG(dm, ODM_COMP_API, "DC cancellation OK!!!");
}
- /*5G*/
- else if (channel >= 36 && channel <= 177) {
-
- if (bw != 20) {
-
- if (bw == 40) {
- num_start_channel = NUM_START_CH_40M;
- p_start_ch = &(start_ch_per_40m[0]);
- channel_offset = CH_OFFSET_40M;
- } else if (bw == 80) {
- num_start_channel = NUM_START_CH_80M;
- p_start_ch = &(start_ch_per_80m[0]);
- channel_offset = CH_OFFSET_80M;
- }
-
- for (i = 0; i < num_start_channel; i++) {
-
- if (channel < p_start_ch[i+1]) {
- channel = p_start_ch[i] + channel_offset;
- break;
- }
- }
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("Mod_CH = ((%d))\n", channel));
- }
- fc = 5180 + (channel-36)*5;
-
- } else {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("CH = ((%d)) Error Setting\n", channel));
- return SET_ERROR;
- }
-
- *fc_in = fc;
-
- return SET_SUCCESS;
-}
-
-
-u1Byte
-phydm_calculate_intf_distance(
- IN PVOID pDM_VOID,
- IN u4Byte bw,
- IN u4Byte fc,
- IN u4Byte f_interference,
- IN OUT u4Byte *p_tone_idx_tmp_in
-)
-{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- u4Byte bw_up, bw_low;
- u4Byte int_distance;
- u4Byte tone_idx_tmp;
- u1Byte set_result = SET_NO_NEED;
+ /*DC_Cancellation*/
+ odm_set_bb_reg(dm, 0xa9c, BIT(20), 0x1); /*DC compensation to CCK data path*/
+ if (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8710B)) {
+ offset_i_hex[0] = (reg_value32[0] & 0xffc0000) >> 18;
+ offset_q_hex[0] = (reg_value32[0] & 0x3ff00) >> 8;
+
+ /*Before filling into registers, offset should be multiplexed (-1)*/
+ offset_i_hex[0] = (offset_i_hex[0] >= 0x200) ? (0x400 - offset_i_hex[1]) : (0x1ff - offset_i_hex[1]);
+ offset_q_hex[0] = (offset_q_hex[0] >= 0x200) ? (0x400 - offset_q_hex[1]) : (0x1ff - offset_q_hex[1]);
+
+ odm_set_bb_reg(dm, 0x950, 0x1ff, offset_i_hex[1]);
+ odm_set_bb_reg(dm, 0x950, 0x1ff0000, offset_q_hex[1]);
+ } else if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B)) {
- bw_up = fc + bw/2;
- bw_low = fc - bw/2;
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("[f_l, fc, fh] = [ %d, %d, %d ], f_int = ((%d))\n", bw_low, fc, bw_up, f_interference));
-
- if ((f_interference >= bw_low) && (f_interference <= bw_up)) {
-
- int_distance = (fc >= f_interference) ? (fc - f_interference) : (f_interference - fc);
- tone_idx_tmp = (int_distance<<5); /* =10*(int_distance /0.3125) */
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("int_distance = ((%d MHz)) Mhz, tone_idx_tmp = ((%d.%d))\n", int_distance, (tone_idx_tmp/10), (tone_idx_tmp%10)));
- *p_tone_idx_tmp_in = tone_idx_tmp;
- set_result = SET_SUCCESS;
- }
+ /* Path-a */
+ offset_i_hex[0] = (reg_value32[0] & 0xffc00) >> 10;
+ offset_q_hex[0] = reg_value32[0] & 0x3ff;
- return set_result;
-
-}
+ /*Before filling into registers, offset should be multiplexed (-1)*/
+ offset_i_hex[0] = 0x400 - offset_i_hex[0];
+ offset_q_hex[0] = 0x400 - offset_q_hex[0];
+ odm_set_bb_reg(dm, 0xc10, 0x3c000000, ((0x3c0 & offset_i_hex[0]) >> 6));
+ odm_set_bb_reg(dm, 0xc10, 0xfc00, (0x3f & offset_i_hex[0]));
+ odm_set_bb_reg(dm, 0xc14, 0x3c000000, ((0x3c0 & offset_q_hex[0]) >> 6));
+ odm_set_bb_reg(dm, 0xc14, 0xfc00, (0x3f & offset_q_hex[0]));
-u1Byte
-phydm_csi_mask_setting(
- IN PVOID pDM_VOID,
- IN u4Byte enable,
- IN u4Byte channel,
- IN u4Byte bw,
- IN u4Byte f_interference,
- IN u4Byte Second_ch
-)
-{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- u4Byte fc;
- u4Byte int_distance;
- u1Byte tone_direction;
- u4Byte tone_idx_tmp;
- u1Byte set_result = SET_SUCCESS;
-
- if (enable == CSI_MASK_DISABLE) {
- set_result = SET_SUCCESS;
- phydm_clean_all_csi_mask(pDM_Odm);
-
- } else {
+ /* Path-b */
+ if (dm->rf_type > RF_1T1R) {
+
+ offset_i_hex[1] = (reg_value32[1] & 0xffc00) >> 10;
+ offset_q_hex[1] = reg_value32[1] & 0x3ff;
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("[Set CSI MASK_] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
- channel, bw, f_interference, (((bw == 20) || (channel > 14)) ? "Don't care" : (Second_ch == PHYDM_ABOVE) ? "H" : "L")));
+ /*Before filling into registers, offset should be multiplexed (-1)*/
+ offset_i_hex[1] = 0x400 - offset_i_hex[1];
+ offset_q_hex[1] = 0x400 - offset_q_hex[1];
- /*calculate fc*/
- if (phydm_calculate_fc(pDM_Odm, channel, bw, Second_ch, &fc) == SET_ERROR)
- set_result = SET_ERROR;
-
- else {
- /*calculate interference distance*/
- if (phydm_calculate_intf_distance(pDM_Odm, bw, fc, f_interference, &tone_idx_tmp) == SET_SUCCESS) {
-
- tone_direction = (f_interference >= fc) ? FREQ_POSITIVE : FREQ_NEGATIVE;
- phydm_set_csi_mask_reg(pDM_Odm, tone_idx_tmp, tone_direction);
- set_result = SET_SUCCESS;
- } else
- set_result = SET_NO_NEED;
+ odm_set_bb_reg(dm, 0xe10, 0x3c000000, ((0x3c0 & offset_i_hex[1]) >> 6));
+ odm_set_bb_reg(dm, 0xe10, 0xfc00, (0x3f & offset_i_hex[1]));
+ odm_set_bb_reg(dm, 0xe14, 0x3c000000, ((0x3c0 & offset_q_hex[1]) >> 6));
+ odm_set_bb_reg(dm, 0xe14, 0xfc00, (0x3f & offset_q_hex[1]));
}
}
-
- if (set_result == SET_SUCCESS)
- phydm_csi_mask_enable(pDM_Odm, enable);
- else
- phydm_csi_mask_enable(pDM_Odm, CSI_MASK_DISABLE);
-
- return set_result;
+#endif
}
-u1Byte
-phydm_nbi_setting(
- IN PVOID pDM_VOID,
- IN u4Byte enable,
- IN u4Byte channel,
- IN u4Byte bw,
- IN u4Byte f_interference,
- IN u4Byte Second_ch
+void
+phydm_receiver_blocking(
+ void *dm_void
)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- u4Byte fc;
- u4Byte int_distance;
- u4Byte tone_idx_tmp;
- u1Byte set_result = SET_SUCCESS;
- u4Byte bw_max = 40;
-
- if (enable == NBI_DISABLE)
- set_result = SET_SUCCESS;
-
- else {
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_API, ODM_DBG_LOUD, ("[Set NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
- channel, bw, f_interference, (((Second_ch == PHYDM_DONT_CARE) || (bw == 20) || (channel > 14)) ? "Don't care" : (Second_ch == PHYDM_ABOVE) ? "H" : "L")));
-
- /*calculate fc*/
- if (phydm_calculate_fc(pDM_Odm, channel, bw, Second_ch, &fc) == SET_ERROR)
- set_result = SET_ERROR;
-
- else {
- /*calculate interference distance*/
- if (phydm_calculate_intf_distance(pDM_Odm, bw, fc, f_interference, &tone_idx_tmp) == SET_SUCCESS) {
-
- phydm_set_nbi_reg(pDM_Odm, tone_idx_tmp, bw);
- set_result = SET_SUCCESS;
- } else
- set_result = SET_NO_NEED;
- }
- }
-
- if (set_result == SET_SUCCESS)
- phydm_nbi_enable(pDM_Odm, enable);
- else
- phydm_nbi_enable(pDM_Odm, NBI_DISABLE);
+#ifdef CONFIG_RECEIVER_BLOCKING
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ u32 channel = *dm->channel;
+ u8 bw = *dm->band_width;
+ u32 bb_regf0 = odm_get_bb_reg(dm, 0xf0, MASKDWORD);
- return set_result;
-}
+ if (!(dm->support_ic_type & ODM_RECEIVER_BLOCKING_SUPPORT))
+ return;
-VOID
-phydm_api_debug(
- IN PVOID pDM_VOID,
- IN u4Byte function_map,
- IN u4Byte *const dm_value,
- IN u4Byte *_used,
- OUT char *output,
- IN u4Byte *_out_len
- )
-{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- u4Byte used = *_used;
- u4Byte out_len = *_out_len;
- u4Byte channel = dm_value[1];
- u4Byte bw = dm_value[2];
- u4Byte f_interference = dm_value[3];
- u4Byte Second_ch = dm_value[4];
- u1Byte set_result = 0;
-
- /*PHYDM_API_NBI*/
- /*-------------------------------------------------------------------------------------------------------------------------------*/
- if (function_map == PHYDM_API_NBI) {
-
- if (dm_value[0] == 100) {
-
- PHYDM_SNPRINTF((output+used, out_len-used, "[HELP-NBI] EN(on=1, off=2) CH BW(20/40/80) f_intf(Mhz) Scnd_CH(L=1, H=2)\n"));
+ if ((dm->support_ic_type & ODM_RTL8188E && ((bb_regf0 & 0xf000) >> 12) < 8) ||
+ dm->support_ic_type & ODM_RTL8192E) { /*8188E_T version*/
+ if (dm->consecutive_idlel_time > 10 && *dm->mp_mode == false && dm->adaptivity_enable == true) {
+ if ((bw == CHANNEL_WIDTH_20) && (channel == 1)) {
+ phydm_nbi_setting(dm, FUNC_ENABLE, channel, 20, 2410, PHYDM_DONT_CARE);
+ dm->is_receiver_blocking_en = true;
+ } else if ((bw == CHANNEL_WIDTH_20) && (channel == 13)) {
+ phydm_nbi_setting(dm, FUNC_ENABLE, channel, 20, 2473, PHYDM_DONT_CARE);
+ dm->is_receiver_blocking_en = true;
+ } else if (dm->is_receiver_blocking_en && channel != 1 && channel != 13) {
+ phydm_nbi_enable(dm, FUNC_DISABLE);
+ odm_set_bb_reg(dm, 0xc40, 0x1f000000, 0x1f);
+ dm->is_receiver_blocking_en = false;
+ }
return;
-
- } else if (dm_value[0] == NBI_ENABLE) {
-
- PHYDM_SNPRINTF((output+used, out_len-used, "[Enable NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
- channel, bw, f_interference, ((Second_ch == PHYDM_DONT_CARE) || (bw == 20) || (channel > 14)) ? "Don't care" : ((Second_ch == PHYDM_ABOVE) ? "H" : "L")));
- set_result = phydm_nbi_setting(pDM_Odm, NBI_ENABLE, channel, bw, f_interference, Second_ch);
-
- } else if (dm_value[0] == NBI_DISABLE) {
-
- PHYDM_SNPRINTF((output+used, out_len-used, "[Disable NBI]\n"));
- set_result = phydm_nbi_setting(pDM_Odm, NBI_DISABLE, channel, bw, f_interference, Second_ch);
-
- } else {
-
- set_result = SET_ERROR;
}
- PHYDM_SNPRINTF((output+used, out_len-used, "[NBI set result: %s]\n", (set_result == SET_SUCCESS) ? "Success" : ((set_result == SET_NO_NEED) ? "No need" : "Error")));
-
- }
-
- /*PHYDM_CSI_MASK*/
- /*-------------------------------------------------------------------------------------------------------------------------------*/
- else if (function_map == PHYDM_API_CSI_MASK) {
-
- if (dm_value[0] == 100) {
-
- PHYDM_SNPRINTF((output+used, out_len-used, "[HELP-CSI MASK] EN(on=1, off=2) CH BW(20/40/80) f_intf(Mhz) Scnd_CH(L=1, H=2)\n"));
+ } else if ((dm->support_ic_type & ODM_RTL8188E && ((bb_regf0 & 0xf000) >> 12) >= 8)) { /*8188E_S version*/
+ if (dm->consecutive_idlel_time > 10 && *dm->mp_mode == false && dm->adaptivity_enable == true) {
+ if ((bw == CHANNEL_WIDTH_20) && (channel == 13)) {
+ phydm_nbi_setting(dm, FUNC_ENABLE, channel, 20, 2473, PHYDM_DONT_CARE);
+ dm->is_receiver_blocking_en = true;
+ } else if (dm->is_receiver_blocking_en && channel != 13) {
+ phydm_nbi_enable(dm, FUNC_DISABLE);
+ odm_set_bb_reg(dm, 0xc40, 0x1f000000, 0x1f);
+ dm->is_receiver_blocking_en = false;
+ }
return;
-
- } else if (dm_value[0] == CSI_MASK_ENABLE) {
-
- PHYDM_SNPRINTF((output+used, out_len-used, "[Enable CSI MASK] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
- channel, bw, f_interference, (channel > 14)?"Don't care":(((Second_ch == PHYDM_DONT_CARE) || (bw == 20) || (channel > 14)) ? "H" : "L")));
- set_result = phydm_csi_mask_setting(pDM_Odm, CSI_MASK_ENABLE, channel, bw, f_interference, Second_ch);
-
- } else if (dm_value[0] == CSI_MASK_DISABLE) {
-
- PHYDM_SNPRINTF((output+used, out_len-used, "[Disable CSI MASK]\n"));
- set_result = phydm_csi_mask_setting(pDM_Odm, CSI_MASK_DISABLE, channel, bw, f_interference, Second_ch);
-
- } else {
-
- set_result = SET_ERROR;
}
- PHYDM_SNPRINTF((output+used, out_len-used, "[CSI MASK set result: %s]\n", (set_result == SET_SUCCESS) ? "Success" : ((set_result == SET_NO_NEED) ? "No need" : "Error")));
}
-}
+ if (dm->is_receiver_blocking_en) {
+ phydm_nbi_enable(dm, FUNC_DISABLE);
+ odm_set_bb_reg(dm, 0xc40, 0x1f000000, 0x1f);
+ dm->is_receiver_blocking_en = false;
+ }
+#endif
+}
diff --git a/hal/phydm/phydm.h b/hal/phydm/phydm.h
index 442c3b7..602b663 100644
--- a/hal/phydm/phydm.h
+++ b/hal/phydm/phydm.h
@@ -1,72 +1,85 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
- *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
*
+ * Larry Finger
*
- ******************************************************************************/
+ *****************************************************************************/
#ifndef __HALDMOUTSRC_H__
#define __HALDMOUTSRC_H__
-//============================================================
-// include files
-//============================================================
+/*============================================================*/
+/*include files*/
+/*============================================================*/
+/*PHYDM header*/
#include "phydm_pre_define.h"
#include "phydm_dig.h"
-#include "phydm_edcaturbocheck.h"
#include "phydm_pathdiv.h"
#include "phydm_antdiv.h"
+#include "phydm_soml.h"
+#include "phydm_smt_ant.h"
#include "phydm_antdect.h"
-#include "phydm_dynamicbbpowersaving.h"
#include "phydm_rainfo.h"
#include "phydm_dynamictxpower.h"
#include "phydm_cfotracking.h"
-#include "phydm_acs.h"
#include "phydm_adaptivity.h"
-#include "phydm_iqk.h"
#include "phydm_dfs.h"
#include "phydm_ccx.h"
#include "txbf/phydm_hal_txbf_api.h"
-
-#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
-#include "phydm_beamforming.h"
-#endif
-
-#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-#include "halphyrf_ap.h"
#include "phydm_adc_sampling.h"
-#endif
-
-#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
+#include "phydm_dynamic_rx_path.h"
+#include "phydm_psd.h"
+#include "phydm_primary_cca.h"
+#include "phydm_cck_pd.h"
+#include "phydm_rssi_monitor.h"
+#include "phydm_auto_dbg.h"
+#include "phydm_math_lib.h"
#include "phydm_noisemonitor.h"
-#include "halphyrf_ce.h"
+#include "phydm_api.h"
+#include "phydm_pow_train.h"
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
+ #include "phydm_beamforming.h"
#endif
-#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
-#include "halphyrf_win.h"
-#include "phydm_noisemonitor.h"
+/* reg naming transfer */
+#include "phydm_regtable.h"
+
+/*HALRF header*/
+#include "halrf/halrf_iqk.h"
+#include "halrf/halrf.h"
+#include "halrf/halrf_powertracking.h"
+#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
+ #include "halrf/halphyrf_ap.h"
+#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE))
+ #include "halrf/halphyrf_ce.h"
+#elif (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
+ #include "halrf/halphyrf_win.h"
#endif
-//============================================================
-// Definition
-//============================================================
-//
-// 2011/09/22 MH Define all team supprt ability.
-//
+extern const u16 phy_rate_table[28];
+
+/*============================================================*/
+/*Definition */
+/*============================================================*/
/* Traffic load decision */
#define TRAFFIC_ULTRA_LOW 1
@@ -76,303 +89,155 @@
#define NONE 0
-/*NBI API------------------------------------*/
-#define NBI_ENABLE 1
-#define NBI_DISABLE 2
-
-#define NBI_TABLE_SIZE_128 27
-#define NBI_TABLE_SIZE_256 59
-
-#define NUM_START_CH_80M 7
-#define NUM_START_CH_40M 14
-
-#define CH_OFFSET_40M 2
-#define CH_OFFSET_80M 6
-
-/*CSI MASK API------------------------------------*/
-#define CSI_MASK_ENABLE 1
-#define CSI_MASK_DISABLE 2
-
-/*------------------------------------------------*/
-
-#define FFT_128_TYPE 1
-#define FFT_256_TYPE 2
+#define MAX_2(_x_, _y_) (((_x_)>(_y_))? (_x_) : (_y_))
+#define MIN_2(_x_, _y_) (((_x_)<(_y_))? (_x_) : (_y_))
+#define DIFF_2(_x_,_y_) ((_x_ >= _y_) ? (_x_ - _y_) : (_y_ - _x_))
-#define SET_SUCCESS 1
-#define SET_ERROR 2
-#define SET_NO_NEED 3
+#define BYTE_2_DWORD(B3, B2, B1, B0) ((B3 << 24) | (B2 << 16) | (B1 << 8) | B0)
+#define BIT_2_BYTE(B3, B2, B1, B0) ((B3 << 3) | (B2 << 2) | (B1 << 1) | B0)
-#define FREQ_POSITIVE 1
-#define FREQ_NEGATIVE 2
+/*For cmn sta info*/
+#define is_sta_active(sta) ((sta) && (sta->dm_ctrl & STA_DM_CTRL_ACTIVE))
-
-
-//============================================================
-// structure and define
-//============================================================
-
-//
-// 2011/09/20 MH Add for AP/ADSLpseudo DM structuer requirement.
-// We need to remove to other position???
-//
-#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
-typedef struct rtl8192cd_priv {
- u1Byte temp;
-
-}rtl8192cd_priv, *prtl8192cd_priv;
-#endif
-
-
-#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
-typedef struct _ADAPTER{
- u1Byte temp;
- #ifdef AP_BUILD_WORKAROUND
- HAL_DATA_TYPE* temp2;
- prtl8192cd_priv priv;
- #endif
-}ADAPTER, *PADAPTER;
-#endif
+#define IS_FUNC_EN(name) ((name) && (*name))
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-
-typedef struct _WLAN_STA{
- u1Byte temp;
-} WLAN_STA, *PRT_WLAN_STA;
-
-#endif
-
-typedef struct _Dynamic_Primary_CCA{
- u1Byte PriCCA_flag;
- u1Byte intf_flag;
- u1Byte intf_type;
- u1Byte DupRTS_flag;
- u1Byte Monitor_flag;
- u1Byte CH_offset;
- u1Byte MF_state;
-}Pri_CCA_T, *pPri_CCA_T;
-
-
-#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
- #ifdef ADSL_AP_BUILD_WORKAROUND
- #define MAX_TOLERANCE 5
- #define IQK_DELAY_TIME 1 /*ms*/
- #endif
-#endif /*#if(DM_ODM_SUPPORT_TYPE & (ODM_AP))*/
-
-#define DM_Type_ByFW 0
-#define DM_Type_ByDriver 1
-
-//
-// Declare for common info
-//
-
-#define IQK_THRESHOLD 8
-#define DPK_THRESHOLD 4
-
-
-#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-__PACK typedef struct _ODM_Phy_Status_Info_
-{
- u1Byte RxPWDBAll;
- u1Byte SignalQuality; /* in 0-100 index. */
- u1Byte RxMIMOSignalStrength[4]; /* in 0~100 index */
- s1Byte RxMIMOSignalQuality[4]; /* EVM */
- s1Byte RxSNR[4]; /* per-path's SNR */
-#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
- u1Byte RxCount:2; /* RX path counter---*/
- u1Byte BandWidth:2;
- u1Byte rxsc:4; /* sub-channel---*/
-#else
- u1Byte BandWidth;
-#endif
-#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
- u1Byte channel; /* channel number---*/
- BOOLEAN bMuPacket; /* is MU packet or not---*/
- BOOLEAN bBeamformed; /* BF packet---*/
-#endif
-} __WLAN_ATTRIB_PACK__ ODM_PHY_INFO_T, *PODM_PHY_INFO_T;
-
-typedef struct _ODM_Phy_Status_Info_Append_
-{
- u1Byte MAC_CRC32;
-
-}ODM_PHY_INFO_Append_T,*PODM_PHY_INFO_Append_T;
-
-#else
-
-typedef struct _ODM_Phy_Status_Info_
-{
- //
- // Be care, if you want to add any element please insert between
- // RxPWDBAll & SignalStrength.
- //
-#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
- u4Byte RxPWDBAll;
-#else
- u1Byte RxPWDBAll;
-#endif
- u1Byte SignalQuality; /* in 0-100 index. */
- s1Byte RxMIMOSignalQuality[4]; /* per-path's EVM */
- u1Byte RxMIMOEVMdbm[4]; /* per-path's EVM dbm */
- u1Byte RxMIMOSignalStrength[4]; /* in 0~100 index */
- s2Byte Cfo_short[4]; /* per-path's Cfo_short */
- s2Byte Cfo_tail[4]; /* per-path's Cfo_tail */
- s1Byte RxPower; /* in dBm Translate from PWdB */
- s1Byte RecvSignalPower; /* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */
- u1Byte BTRxRSSIPercentage;
- u1Byte SignalStrength; /* in 0-100 index. */
- s1Byte RxPwr[4]; /* per-path's pwdb */
- s1Byte RxSNR[4]; /* per-path's SNR */
-#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
- u1Byte RxCount:2; /* RX path counter---*/
- u1Byte BandWidth:2;
- u1Byte rxsc:4; /* sub-channel---*/
+ #define PHYDM_WATCH_DOG_PERIOD 1 /*second*/
#else
- u1Byte BandWidth;
-#endif
-#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
- u1Byte btCoexPwrAdjust;
-#endif
-#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
- u1Byte channel; /* channel number---*/
- BOOLEAN bMuPacket; /* is MU packet or not---*/
- BOOLEAN bBeamformed; /* BF packet---*/
-#endif
-}ODM_PHY_INFO_T,*PODM_PHY_INFO_T;
+ #define PHYDM_WATCH_DOG_PERIOD 2 /*second*/
#endif
-typedef struct _ODM_Per_Pkt_Info_
-{
- //u1Byte Rate;
- u1Byte DataRate;
- u1Byte StationID;
- BOOLEAN bPacketMatchBSSID;
- BOOLEAN bPacketToSelf;
- BOOLEAN bPacketBeacon;
- BOOLEAN bToSelf;
-}ODM_PACKET_INFO_T,*PODM_PACKET_INFO_T;
+/*============================================================*/
+/*structure and define*/
+/*============================================================*/
+#define dm_type_by_fw 0
+#define dm_type_by_driver 1
-typedef struct _ODM_Phy_Dbg_Info_
-{
- //ODM Write,debug info
- s1Byte RxSNRdB[4];
- u4Byte NumQryPhyStatus;
- u4Byte NumQryPhyStatusCCK;
- u4Byte NumQryPhyStatusOFDM;
-#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
- u4Byte NumQryMuPkt;
- u4Byte NumQryBfPkt;
- u4Byte NumQryMuVhtPkt[40];
- u4Byte NumQryVhtPkt[40];
-#endif
- u1Byte NumQryBeaconPkt;
- //Others
- s4Byte RxEVM[4];
+struct phydm_phystatus_statistic {
-}ODM_PHY_DBG_INFO_T;
-
+ /*[CCK]*/
+ u32 rssi_cck_sum;
+ u32 rssi_cck_cnt;
+ /*[OFDM]*/
+ u32 rssi_ofdm_sum;
+ u32 rssi_ofdm_cnt;
+ u32 evm_ofdm_sum;
+ u32 snr_ofdm_sum;
+ /*[1SS]*/
+ u32 rssi_1ss_cnt;
+ u32 rssi_1ss_sum;
+ u32 evm_1ss_sum;
+ u32 snr_1ss_sum;
+ /*[2SS]*/
+ #if (defined(PHYDM_COMPILE_ABOVE_2SS))
+ u32 rssi_2ss_cnt;
+ u32 rssi_2ss_sum[2];
+ u32 evm_2ss_sum[2];
+ u32 snr_2ss_sum[2];
+ #endif
+ /*[3SS]*/
+ #if (defined(PHYDM_COMPILE_ABOVE_3SS))
+ u32 rssi_3ss_cnt;
+ u32 rssi_3ss_sum[3];
+ u32 evm_3ss_sum[3];
+ u32 snr_3ss_sum[3];
+ #endif
+ /*[4SS]*/
+ #if (defined(PHYDM_COMPILE_ABOVE_4SS))
+ u32 rssi_4ss_cnt;
+ u32 rssi_4ss_sum[4];
+ u32 evm_4ss_sum[4];
+ u32 snr_4ss_sum[4];
+ #endif
+};
-typedef struct _ODM_Mac_Status_Info_
-{
- u1Byte test;
+struct phydm_phystatus_avg {
-}ODM_MAC_INFO;
-
-//
-// 2011/20/20 MH For MP driver RT_WLAN_STA = STA_INFO_T
-// Please declare below ODM relative info in your STA info structure.
-//
-#if 1
-typedef struct _ODM_STA_INFO{
- // Driver Write
- BOOLEAN bUsed; // record the sta status link or not?
- //u1Byte WirelessMode; //
- u1Byte IOTPeer; // Enum value. HT_IOT_PEER_E
-
- // ODM Write
- //1 PHY_STATUS_INFO
- u1Byte RSSI_Path[4]; //
- u1Byte RSSI_Ave;
- u1Byte RXEVM[4];
- u1Byte RXSNR[4];
-
- // ODM Write
- //1 TX_INFO (may changed by IC)
- //TX_INFO_T pTxInfo; // Define in IC folder. Move lower layer.
-#if 0
- u1Byte ANTSEL_A; //in Jagar: 4bit; others: 2bit
- u1Byte ANTSEL_B; //in Jagar: 4bit; others: 2bit
- u1Byte ANTSEL_C; //only in Jagar: 4bit
- u1Byte ANTSEL_D; //only in Jagar: 4bit
- u1Byte TX_ANTL; //not in Jagar: 2bit
- u1Byte TX_ANT_HT; //not in Jagar: 2bit
- u1Byte TX_ANT_CCK; //not in Jagar: 2bit
- u1Byte TXAGC_A; //not in Jagar: 4bit
- u1Byte TXAGC_B; //not in Jagar: 4bit
- u1Byte TXPWR_OFFSET; //only in Jagar: 3bit
- u1Byte TX_ANT; //only in Jagar: 4bit for TX_ANTL/TX_ANTHT/TX_ANT_CCK
-#endif
-
- //
- // Please use compile flag to disabe the strcutrue for other IC except 88E.
- // Move To lower layer.
- //
- // ODM Write Wilson will handle this part(said by Luke.Lee)
- //TX_RPT_T pTxRpt; // Define in IC folder. Move lower layer.
-#if 0
- //1 For 88E RA (don't redefine the naming)
- u1Byte rate_id;
- u1Byte rate_SGI;
- u1Byte rssi_sta_ra;
- u1Byte SGI_enable;
- u1Byte Decision_rate;
- u1Byte Pre_rate;
- u1Byte Active;
-
- // Driver write Wilson handle.
- //1 TX_RPT (don't redefine the naming)
- u2Byte RTY[4]; // ???
- u2Byte TOTAL; // ???
- u2Byte DROP; // ???
- //
- // Please use compile flag to disabe the strcutrue for other IC except 88E.
- //
-#endif
+ /*[CCK]*/
+ u8 rssi_cck_avg;
+ /*[OFDM]*/
+ u8 rssi_ofdm_avg;
+ u8 evm_ofdm_avg;
+ u8 snr_ofdm_avg;
+ /*[1SS]*/
+ u8 rssi_1ss_avg;
+ u8 evm_1ss_avg;
+ u8 snr_1ss_avg;
+ /*[2SS]*/
+ #if (defined(PHYDM_COMPILE_ABOVE_2SS))
+ u8 rssi_2ss_avg[2];
+ u8 evm_2ss_avg[2];
+ u8 snr_2ss_avg[2];
+ #endif
+ /*[3SS]*/
+ #if (defined(PHYDM_COMPILE_ABOVE_3SS))
+ u8 rssi_3ss_avg[3];
+ u8 evm_3ss_avg[3];
+ u8 snr_3ss_avg[3];
+ #endif
+ /*[4SS]*/
+ #if (defined(PHYDM_COMPILE_ABOVE_4SS))
+ u8 rssi_4ss_avg[4];
+ u8 evm_4ss_avg[4];
+ u8 snr_4ss_avg[4];
+ #endif
+};
-}ODM_STA_INFO_T, *PODM_STA_INFO_T;
+struct odm_phy_dbg_info {
+ /*ODM Write,debug info*/
+
+ u32 num_qry_phy_status_cck;
+ u32 num_qry_phy_status_ofdm;
+#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
+ u32 num_qry_mu_pkt;
+ u32 num_qry_bf_pkt;
+ u32 num_qry_mu_vht_pkt[VHT_RATE_NUM];
+ boolean is_ldpc_pkt;
+ boolean is_stbc_pkt;
+ u8 num_of_ppdu[4];
+ u8 gid_num[4];
#endif
+ u8 num_qry_beacon_pkt;
+ u8 show_phy_sts_all_pkt; /*Show phy status witch not match BSSID*/
+ u16 show_phy_sts_max_cnt; /*show number of phy-status row data per PHYDM watchdog*/
+ u16 show_phy_sts_cnt;
+ /* Others */
+ /*s32 rx_evm[4];*/
+ /*s8 rx_snr_db[4];*/
+
+ u16 num_qry_legacy_pkt[LEGACY_RATE_NUM];
+ u16 num_qry_ht_pkt[HT_RATE_NUM];
+ u16 num_qry_pkt_sc_20m[LOW_BW_RATE_NUM]; /*for 20M SC*/
+ boolean ht_pkt_not_zero;
+ boolean low_bw_20_occur;
+ #if ODM_IC_11AC_SERIES_SUPPORT
+ u16 num_qry_vht_pkt[VHT_RATE_NUM];
+ u16 num_qry_pkt_sc_40m[LOW_BW_RATE_NUM]; /*for 40M SC*/
+ boolean vht_pkt_not_zero;
+ boolean low_bw_40_occur;
+ #endif
+ struct phydm_phystatus_statistic phystatus_statistic_info;
+ struct phydm_phystatus_avg phystatus_statistic_avg;
+};
-//
-// 2011/10/20 MH Define Common info enum for all team.
-//
-typedef enum _ODM_Common_Info_Definition
-{
-//-------------REMOVED CASE-----------//
- //ODM_CMNINFO_CCK_HP,
- //ODM_CMNINFO_RFPATH_ENABLE, // Define as ODM write???
- //ODM_CMNINFO_BT_COEXIST, // ODM_BT_COEXIST_E
- //ODM_CMNINFO_OP_MODE, // ODM_OPERATION_MODE_E
-//-------------REMOVED CASE-----------//
-
- //
- // Fixed value:
- //
-
- //-----------HOOK BEFORE REG INIT-----------//
+enum odm_cmninfo {
+ /*Fixed value*/
+ /*-----------HOOK BEFORE REG INIT-----------*/
ODM_CMNINFO_PLATFORM = 0,
- ODM_CMNINFO_ABILITY, // ODM_ABILITY_E
- ODM_CMNINFO_INTERFACE, // ODM_INTERFACE_E
+ ODM_CMNINFO_ABILITY,
+ ODM_CMNINFO_INTERFACE,
ODM_CMNINFO_MP_TEST_CHIP,
- ODM_CMNINFO_IC_TYPE, // ODM_IC_TYPE_E
- ODM_CMNINFO_CUT_VER, // ODM_CUT_VERSION_E
- ODM_CMNINFO_FAB_VER, // ODM_FAB_E
- ODM_CMNINFO_RF_TYPE, // ODM_RF_PATH_E or ODM_RF_TYPE_E?
- ODM_CMNINFO_RFE_TYPE,
- ODM_CMNINFO_BOARD_TYPE, // ODM_BOARD_TYPE_E
+ ODM_CMNINFO_IC_TYPE,
+ ODM_CMNINFO_CUT_VER,
+ ODM_CMNINFO_FAB_VER,
+ ODM_CMNINFO_RF_TYPE,
+ ODM_CMNINFO_RFE_TYPE,
+ ODM_CMNINFO_DPK_EN,
+ ODM_CMNINFO_BOARD_TYPE,
ODM_CMNINFO_PACKAGE_TYPE,
- ODM_CMNINFO_EXT_LNA, // TRUE
- ODM_CMNINFO_5G_EXT_LNA,
+ ODM_CMNINFO_EXT_LNA,
+ ODM_CMNINFO_5G_EXT_LNA,
ODM_CMNINFO_EXT_PA,
ODM_CMNINFO_5G_EXT_PA,
ODM_CMNINFO_GPA,
@@ -381,14 +246,13 @@ typedef enum _ODM_Common_Info_Definition
ODM_CMNINFO_ALNA,
ODM_CMNINFO_EXT_TRSW,
ODM_CMNINFO_EXT_LNA_GAIN,
- ODM_CMNINFO_PATCH_ID, //CUSTOMER ID
+ ODM_CMNINFO_PATCH_ID,
ODM_CMNINFO_BINHCT_TEST,
ODM_CMNINFO_BWIFI_TEST,
ODM_CMNINFO_SMART_CONCURRENT,
ODM_CMNINFO_CONFIG_BB_RF,
ODM_CMNINFO_DOMAIN_CODE_2G,
ODM_CMNINFO_DOMAIN_CODE_5G,
- ODM_CMNINFO_IQKFWOFFLOAD,
ODM_CMNINFO_IQKPAOFF,
ODM_CMNINFO_HUBUSBMODE,
ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS,
@@ -397,696 +261,792 @@ typedef enum _ODM_Common_Info_Definition
ODM_CMNINFO_SOUNDING_SEQ,
ODM_CMNINFO_REGRFKFREEENABLE,
ODM_CMNINFO_RFKFREEENABLE,
- //-----------HOOK BEFORE REG INIT-----------//
+ ODM_CMNINFO_NORMAL_RX_PATH_CHANGE,
+ ODM_CMNINFO_EFUSE0X3D8,
+ ODM_CMNINFO_EFUSE0X3D7,
+ ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING,
+ ODM_CMNINFO_ADVANCE_OTA,
+ ODM_CMNINFO_HP_HWID,
+ /*-----------HOOK BEFORE REG INIT-----------*/
+ /*Dynamic value:*/
- //
- // Dynamic value:
- //
-//--------- POINTER REFERENCE-----------//
- ODM_CMNINFO_MAC_PHY_MODE, // ODM_MAC_PHY_MODE_E
+ /*--------- POINTER REFERENCE-----------*/
ODM_CMNINFO_TX_UNI,
ODM_CMNINFO_RX_UNI,
- ODM_CMNINFO_WM_MODE, // ODM_WIRELESS_MODE_E
- ODM_CMNINFO_BAND, // ODM_BAND_TYPE_E
- ODM_CMNINFO_SEC_CHNL_OFFSET, // ODM_SEC_CHNL_OFFSET_E
- ODM_CMNINFO_SEC_MODE, // ODM_SECURITY_E
- ODM_CMNINFO_BW, // ODM_BW_E
+ ODM_CMNINFO_BAND,
+ ODM_CMNINFO_SEC_CHNL_OFFSET,
+ ODM_CMNINFO_SEC_MODE,
+ ODM_CMNINFO_BW,
ODM_CMNINFO_CHNL,
ODM_CMNINFO_FORCED_RATE,
-
- ODM_CMNINFO_DMSP_GET_VALUE,
- ODM_CMNINFO_BUDDY_ADAPTOR,
- ODM_CMNINFO_DMSP_IS_MASTER,
+ ODM_CMNINFO_ANT_DIV,
+ ODM_CMNINFO_ADAPTIVE_SOML,
+ ODM_CMNINFO_ADAPTIVITY,
ODM_CMNINFO_SCAN,
ODM_CMNINFO_POWER_SAVING,
- ODM_CMNINFO_ONE_PATH_CCA, // ODM_CCA_PATH_E
+ ODM_CMNINFO_ONE_PATH_CCA,
ODM_CMNINFO_DRV_STOP,
ODM_CMNINFO_PNP_IN,
ODM_CMNINFO_INIT_ON,
ODM_CMNINFO_ANT_TEST,
ODM_CMNINFO_NET_CLOSED,
- //ODM_CMNINFO_RTSTA_AID, // For win driver only?
- ODM_CMNINFO_FORCED_IGI_LB,
ODM_CMNINFO_P2P_LINK,
ODM_CMNINFO_FCS_MODE,
ODM_CMNINFO_IS1ANTENNA,
ODM_CMNINFO_RFDEFAULTPATH,
ODM_CMNINFO_DFS_MASTER_ENABLE,
ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC,
-//--------- POINTER REFERENCE-----------//
-
-//------------CALL BY VALUE-------------//
+ ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA,
+ ODM_CMNINFO_SOFT_AP_MODE,
+ ODM_CMNINFO_MP_MODE,
+ ODM_CMNINFO_INTERRUPT_MASK,
+ ODM_CMNINFO_BB_OPERATION_MODE,
+ ODM_CMNINFO_BF_ANTDIV_DECISION,
+ /*--------- POINTER REFERENCE-----------*/
+
+ /*------------CALL BY VALUE-------------*/
ODM_CMNINFO_WIFI_DIRECT,
ODM_CMNINFO_WIFI_DISPLAY,
- ODM_CMNINFO_LINK_IN_PROGRESS,
+ ODM_CMNINFO_LINK_IN_PROGRESS,
ODM_CMNINFO_LINK,
+ ODM_CMNINFO_CMW500LINK,
ODM_CMNINFO_STATION_STATE,
ODM_CMNINFO_RSSI_MIN,
- ODM_CMNINFO_DBG_COMP, /* u4SByte*/
- ODM_CMNINFO_DBG_LEVEL, /* u4Byte*/
- ODM_CMNINFO_RA_THRESHOLD_HIGH, /* u1Byte*/
- ODM_CMNINFO_RA_THRESHOLD_LOW, /* u1Byte*/
- ODM_CMNINFO_RF_ANTENNA_TYPE, /* u1Byte*/
+ ODM_CMNINFO_RSSI_MIN_BY_PATH,
+ ODM_CMNINFO_DBG_COMP,
+ ODM_CMNINFO_DBG_LEVEL,
+ ODM_CMNINFO_RA_THRESHOLD_HIGH, /*to be removed*/
+ ODM_CMNINFO_RA_THRESHOLD_LOW, /*to be removed*/
+ ODM_CMNINFO_RF_ANTENNA_TYPE,
ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH,
ODM_CMNINFO_BE_FIX_TX_ANT,
ODM_CMNINFO_BT_ENABLED,
ODM_CMNINFO_BT_HS_CONNECT_PROCESS,
ODM_CMNINFO_BT_HS_RSSI,
ODM_CMNINFO_BT_OPERATION,
- ODM_CMNINFO_BT_LIMITED_DIG, //Need to Limited Dig or not
- ODM_CMNINFO_BT_DIG,
- ODM_CMNINFO_BT_BUSY, //Check Bt is using or not//neil
- ODM_CMNINFO_BT_DISABLE_EDCA,
-#if(DM_ODM_SUPPORT_TYPE & ODM_AP) // for repeater mode add by YuChen 2014.06.23
-#ifdef UNIVERSAL_REPEATER
- ODM_CMNINFO_VXD_LINK,
-#endif
-#endif
+ ODM_CMNINFO_BT_LIMITED_DIG,
ODM_CMNINFO_AP_TOTAL_NUM,
ODM_CMNINFO_POWER_TRAINING,
ODM_CMNINFO_DFS_REGION_DOMAIN,
-//------------CALL BY VALUE-------------//
+ ODM_CMNINFO_BT_CONTINUOUS_TURN,
+ /*------------CALL BY VALUE-------------*/
- //
- // Dynamic ptr array hook itms.
- //
+ /*Dynamic ptr array hook itms.*/
ODM_CMNINFO_STA_STATUS,
- ODM_CMNINFO_PHY_STATUS,
- ODM_CMNINFO_MAC_STATUS,
-
ODM_CMNINFO_MAX,
+};
-}ODM_CMNINFO_E;
+enum phydm_rfe_bb_source_sel {
+ PAPE_2G = 0,
+ PAPE_5G = 1,
+ LNA0N_2G = 2,
+ LNAON_5G = 3,
+ TRSW = 4,
+ TRSW_B = 5,
+ GNT_BT = 6,
+ ZERO = 7,
+ ANTSEL_0 = 8,
+ ANTSEL_1 = 9,
+ ANTSEL_2 = 0xa,
+ ANTSEL_3 = 0xb,
+ ANTSEL_4 = 0xc,
+ ANTSEL_5 = 0xd,
+ ANTSEL_6 = 0xe,
+ ANTSEL_7 = 0xf
+};
-typedef enum _PHYDM_API_Definition {
+enum phydm_info_query {
+ PHYDM_INFO_FA_OFDM,
+ PHYDM_INFO_FA_CCK,
+ PHYDM_INFO_FA_TOTAL,
+ PHYDM_INFO_CCA_OFDM,
+ PHYDM_INFO_CCA_CCK,
+ PHYDM_INFO_CCA_ALL,
+ PHYDM_INFO_CRC32_OK_VHT,
+ PHYDM_INFO_CRC32_OK_HT,
+ PHYDM_INFO_CRC32_OK_LEGACY,
+ PHYDM_INFO_CRC32_OK_CCK,
+ PHYDM_INFO_CRC32_ERROR_VHT,
+ PHYDM_INFO_CRC32_ERROR_HT,
+ PHYDM_INFO_CRC32_ERROR_LEGACY,
+ PHYDM_INFO_CRC32_ERROR_CCK,
+ PHYDM_INFO_EDCCA_FLAG,
+ PHYDM_INFO_OFDM_ENABLE,
+ PHYDM_INFO_CCK_ENABLE,
+ PHYDM_INFO_CRC32_OK_HT_AGG,
+ PHYDM_INFO_CRC32_ERROR_HT_AGG,
+ PHYDM_INFO_DBG_PORT_0,
+ PHYDM_INFO_CURR_IGI,
+ PHYDM_INFO_RSSI_MIN,
+ PHYDM_INFO_RSSI_MAX,
+ PHYDM_INFO_CLM_RATIO,
+ PHYDM_INFO_NHM_RATIO,
+};
+enum phydm_api {
PHYDM_API_NBI = 1,
PHYDM_API_CSI_MASK,
-
-} PHYDM_API_E;
+};
+enum phydm_func_idx { /*F_XXX = PHYDM XXX function*/
+
+ F00_DIG = 0,
+ F01_RA_MASK = 1,
+ F02_DYN_TXPWR = 2,
+ F03_FA_CNT = 3,
+ F04_RSSI_MNTR = 4,
+ F05_CCK_PD = 5,
+ F06_ANT_DIV = 6,
+ F07_SMT_ANT = 7,
+ F08_PWR_TRAIN = 8,
+ F09_RA = 9,
+ F10_PATH_DIV = 10,
+ F11_DFS = 11,
+ F12_DYN_ARFR = 12,
+ F13_ADPTVTY = 13,
+ F14_CFO_TRK = 14,
+ F15_ENV_MNTR = 15,
+ F16_PRI_CCA = 16,
+ F17_ADPTV_SOML = 17,
+ F18_LNA_SAT_CHK = 18,
+ F19_DYN_RX_PATH = 19
+};
-//
-// 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY
-//
-typedef enum _ODM_Support_Ability_Definition
-{
- //
- // BB ODM section BIT 0-19
- //
- ODM_BB_DIG = BIT0,
- ODM_BB_RA_MASK = BIT1,
- ODM_BB_DYNAMIC_TXPWR = BIT2,
- ODM_BB_FA_CNT = BIT3,
- ODM_BB_RSSI_MONITOR = BIT4,
- ODM_BB_CCK_PD = BIT5,
- ODM_BB_ANT_DIV = BIT6,
- ODM_BB_PWR_TRAIN = BIT8,
- ODM_BB_RATE_ADAPTIVE = BIT9,
- ODM_BB_PATH_DIV = BIT10,
- ODM_BB_ADAPTIVITY = BIT13,
- ODM_BB_CFO_TRACKING = BIT14,
- ODM_BB_NHM_CNT = BIT15,
- ODM_BB_PRIMARY_CCA = BIT16,
- ODM_BB_TXBF = BIT17,
- ODM_BB_DYNAMIC_ARFR = BIT18,
-
- //
- // MAC DM section BIT 20-23
- //
- ODM_MAC_EDCA_TURBO = BIT20,
- ODM_MAC_EARLY_MODE = BIT21,
-
- //
- // RF ODM section BIT 24-31
- //
- ODM_RF_TX_PWR_TRACK = BIT24,
- ODM_RF_RX_GAIN_TRACK = BIT25,
- ODM_RF_CALIBRATION = BIT26,
-
-}ODM_ABILITY_E;
+/*=[PHYDM supportability]==========================================*/
+enum odm_ability {
+ ODM_BB_DIG = BIT(F00_DIG),
+ ODM_BB_RA_MASK = BIT(F01_RA_MASK),
+ ODM_BB_DYNAMIC_TXPWR = BIT(F02_DYN_TXPWR),
+ ODM_BB_FA_CNT = BIT(F03_FA_CNT),
+ ODM_BB_RSSI_MONITOR = BIT(F04_RSSI_MNTR),
+ ODM_BB_CCK_PD = BIT(F05_CCK_PD),
+ ODM_BB_ANT_DIV = BIT(F06_ANT_DIV),
+ ODM_BB_SMT_ANT = BIT(F07_SMT_ANT),
+ ODM_BB_PWR_TRAIN = BIT(F08_PWR_TRAIN),
+ ODM_BB_RATE_ADAPTIVE = BIT(F09_RA),
+ ODM_BB_PATH_DIV = BIT(F10_PATH_DIV),
+ ODM_BB_DFS = BIT(F11_DFS),
+ ODM_BB_DYNAMIC_ARFR = BIT(F12_DYN_ARFR),
+ ODM_BB_ADAPTIVITY = BIT(F13_ADPTVTY),
+ ODM_BB_CFO_TRACKING = BIT(F14_CFO_TRK),
+ ODM_BB_ENV_MONITOR = BIT(F15_ENV_MNTR),
+ ODM_BB_PRIMARY_CCA = BIT(F16_PRI_CCA),
+ ODM_BB_ADAPTIVE_SOML = BIT(F17_ADPTV_SOML),
+ ODM_BB_LNA_SAT_CHK = BIT(F18_LNA_SAT_CHK),
+ ODM_BB_DYNAMIC_RX_PATH = BIT(F19_DYN_RX_PATH)
+};
+
+/*=[PHYDM Debug Component]=====================================*/
+enum phydm_dbg_comp {
+ /*BB Driver Functions*/
+ DBG_DIG = BIT(F00_DIG),
+ DBG_RA_MASK = BIT(F01_RA_MASK),
+ DBG_DYN_TXPWR = BIT(F02_DYN_TXPWR),
+ DBG_FA_CNT = BIT(F03_FA_CNT),
+ DBG_RSSI_MNTR = BIT(F04_RSSI_MNTR),
+ DBG_CCKPD = BIT(F05_CCK_PD),
+ DBG_ANT_DIV = BIT(F06_ANT_DIV),
+ DBG_SMT_ANT = BIT(F07_SMT_ANT),
+ DBG_PWR_TRAIN = BIT(F08_PWR_TRAIN),
+ DBG_RA = BIT(F09_RA),
+ DBG_PATH_DIV = BIT(F10_PATH_DIV),
+ DBG_DFS = BIT(F11_DFS),
+ DBG_DYN_ARFR = BIT(F12_DYN_ARFR),
+ DBG_ADPTVTY = BIT(F13_ADPTVTY),
+ DBG_CFO_TRK = BIT(F14_CFO_TRK),
+ DBG_ENV_MNTR = BIT(F15_ENV_MNTR),
+ DBG_PRI_CCA = BIT(F16_PRI_CCA),
+ DBG_ADPTV_SOML = BIT(F17_ADPTV_SOML),
+ DBG_LNA_SAT_CHK = BIT(F18_LNA_SAT_CHK),
+ DBG_DYN_RX_PATH = BIT(F19_DYN_RX_PATH),
+ /*Neet to re-arrange*/
+ DBG_PHY_STATUS = BIT(20),
+ DBG_TMP = BIT(21),
+ DBG_FW_TRACE = BIT(22),
+ DBG_TXBF = BIT(23),
+ DBG_COMMON_FLOW = BIT(24),
+ ODM_COMP_TX_PWR_TRACK = BIT(25),
+ ODM_COMP_CALIBRATION = BIT(26),
+ ODM_COMP_MP = BIT(27),
+ ODM_PHY_CONFIG = BIT(28),
+ ODM_COMP_INIT = BIT(29),
+ ODM_COMP_COMMON = BIT(30),
+ ODM_COMP_API = BIT(31)
+};
+/*=========================================================*/
-// ODM_CMNINFO_ONE_PATH_CCA
-typedef enum tag_CCA_Path
-{
+/*ODM_CMNINFO_ONE_PATH_CCA*/
+enum odm_cca_path {
ODM_CCA_2R = 0,
ODM_CCA_1R_A = 1,
ODM_CCA_1R_B = 2,
-}ODM_CCA_PATH_E;
+};
-typedef enum CCA_PATHDIV_EN {
- CCA_PATHDIV_DISABLE = 0,
- CCA_PATHDIV_ENABLE = 1,
+enum phy_reg_pg_type {
+ PHY_REG_PG_RELATIVE_VALUE = 0,
+ PHY_REG_PG_EXACT_VALUE = 1
+};
-} CCA_PATHDIV_EN_E;
+enum phydm_offload_ability {
+ PHYDM_PHY_PARAM_OFFLOAD = BIT(0),
+ PHYDM_RF_IQK_OFFLOAD = BIT(1),
+};
+struct phydm_pause_lv {
+ s8 lv_dig;
+ s8 lv_cckpd;
+ s8 lv_antdiv;
+ s8 lv_adapt;
+};
-typedef enum _BASEBAND_CONFIG_PHY_REG_PG_VALUE_TYPE{
- PHY_REG_PG_RELATIVE_VALUE = 0,
- PHY_REG_PG_EXACT_VALUE = 1
-} PHY_REG_PG_TYPE;
+struct phydm_func_poiner {
+ void (*pause_phydm_handler)(void *dm_void, u32 *val_buf, u8 val_len);
+};
-//
-// 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration.
-//
-#if(DM_ODM_SUPPORT_TYPE & ODM_WIN)
-#if (RT_PLATFORM != PLATFORM_LINUX)
-typedef
+struct pkt_process_info {
+ u8 phystatus_smp_mode_en; /*send phystatus every sampling time*/
+ u8 pre_ppdu_cnt;
+ u8 lna_idx;
+ u8 vga_idx;
+};
+
+#ifdef ODM_CONFIG_BT_COEXIST
+struct phydm_bt_info {
+ boolean is_bt_enabled; /*BT is enabled*/
+ boolean is_bt_connect_process; /*BT HS is under connection progress.*/
+ u8 bt_hs_rssi; /*BT HS mode wifi rssi value.*/
+ boolean is_bt_hs_operation; /*BT HS mode is under progress*/
+ boolean is_bt_limited_dig; /*BT is busy.*/
+};
#endif
-
-struct DM_Out_Source_Dynamic_Mechanism_Structure
-#else// for AP,ADSL,CE Team
-typedef struct DM_Out_Source_Dynamic_Mechanism_Structure
+
+struct phydm_iot_center {
+ boolean is_linked_cmw500;
+ u8 win_patch_id; /*Customer ID*/
+ u32 phydm_patch_id;
+
+};
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+ #if (RT_PLATFORM != PLATFORM_LINUX)
+ typedef
+ #endif
+
+ struct dm_struct
+#else/*for AP, CE Team*/
+ struct dm_struct
#endif
{
- // Add for different team use temporarily
- //
- PADAPTER Adapter; // For CE/NIC team
- prtl8192cd_priv priv; // For AP/ADSL team
- // WHen you use Adapter or priv pointer, you must make sure the pointer is ready.
- BOOLEAN odm_ready;
-
-#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
- rtl8192cd_priv fake_priv;
-#endif
-#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
- // ADSL_AP_BUILD_WORKAROUND
- ADAPTER fake_adapter;
-#endif
-
- PHY_REG_PG_TYPE PhyRegPgValueType;
- u1Byte PhyRegPgVersion;
-
- u4Byte DebugComponents;
- u4Byte DebugLevel;
-
- u4Byte NumQryPhyStatusAll; //CCK + OFDM
- u4Byte LastNumQryPhyStatusAll;
- u4Byte RxPWDBAve;
- BOOLEAN MPDIG_2G; //off MPDIG
- u1Byte Times_2G;
- BOOLEAN bInitHwInfoByRfe;
-
-//------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------//
- BOOLEAN bCckHighPower;
- u1Byte RFPathRxEnable; // ODM_CMNINFO_RFPATH_ENABLE
- u1Byte ControlChannel;
-//------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------//
-
-//--------REMOVED COMMON INFO----------//
- //u1Byte PseudoMacPhyMode;
- //BOOLEAN *BTCoexist;
- //BOOLEAN PseudoBtCoexist;
- //u1Byte OPMode;
- //BOOLEAN bAPMode;
- //BOOLEAN bClientMode;
- //BOOLEAN bAdHocMode;
- //BOOLEAN bSlaveOfDMSP;
-//--------REMOVED COMMON INFO----------//
-
-
-//1 COMMON INFORMATION
-
- //
- // Init Value
- //
-//-----------HOOK BEFORE REG INIT-----------//
- // ODM Platform info AP/ADSL/CE/MP = 1/2/3/4
- u1Byte SupportPlatform;
- // ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ¡K¡K = 1/2/3/¡K
- u4Byte SupportAbility;
- // ODM PCIE/USB/SDIO = 1/2/3
- u1Byte SupportInterface;
- // ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/...
- u4Byte SupportICType;
- // Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/...
- u1Byte CutVersion;
- // Fab Version TSMC/UMC = 0/1
- u1Byte FabVersion;
- // RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/...
- u1Byte RFType;
- u1Byte RFEType;
- // Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/...
- u1Byte BoardType;
- u1Byte PackageType;
- u2Byte TypeGLNA;
- u2Byte TypeGPA;
- u2Byte TypeALNA;
- u2Byte TypeAPA;
- // with external LNA NO/Yes = 0/1
- u1Byte ExtLNA; // 2G
- u1Byte ExtLNA5G; //5G
- // with external PA NO/Yes = 0/1
- u1Byte ExtPA; // 2G
- u1Byte ExtPA5G; //5G
- // with external TRSW NO/Yes = 0/1
- u1Byte ExtTRSW;
- u1Byte ExtLNAGain; // 2G
- u1Byte PatchID; //Customer ID
- BOOLEAN bInHctTest;
- u1Byte WIFITest;
-
- BOOLEAN bDualMacSmartConcurrent;
- u4Byte BK_SupportAbility;
- u1Byte AntDivType;
- u1Byte with_extenal_ant_switch;
- BOOLEAN ConfigBBRF;
- u1Byte odm_Regulation2_4G;
- u1Byte odm_Regulation5G;
- u1Byte IQKFWOffload;
- BOOLEAN cck_new_agc;
-//-----------HOOK BEFORE REG INIT-----------//
-
- //
- // Dynamic Value
- //
-//--------- POINTER REFERENCE-----------//
-
- u1Byte u1Byte_temp;
- BOOLEAN BOOLEAN_temp;
- PADAPTER PADAPTER_temp;
+ /*Add for different team use temporarily*/
+ void *adapter; /*For CE/NIC team*/
+ struct rtl8192cd_priv *priv; /*For AP team*/
+ /*WHen you use adapter or priv pointer, you must make sure the pointer is ready.*/
+ boolean odm_ready;
+ enum phy_reg_pg_type phy_reg_pg_value_type;
+ u8 phy_reg_pg_version;
+ u64 support_ability; /*PHYDM function Supportability*/
+ u64 pause_ability; /*PHYDM function pause Supportability*/
+ u64 debug_components;
+ u8 cmn_dbg_msg_period;
+ u8 cmn_dbg_msg_cnt;
+ u32 fw_debug_components;
+ u32 debug_level;
+ u32 num_qry_phy_status_all; /*CCK + OFDM*/
+ u32 last_num_qry_phy_status_all;
+ u32 rx_pwdb_ave;
+ boolean is_init_hw_info_by_rfe;
+
+ /*------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/
+ boolean is_cck_high_power;
+ u8 rf_path_rx_enable;
+ /*------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/
+
+ /* COMMON INFORMATION */
+
+ /*Init value*/
+ /*-----------HOOK BEFORE REG INIT-----------*/
+
+ u8 support_platform;/*PHYDM Platform info WIN/AP/CE = 1/2/3 */
+ u8 normal_rx_path;
+ boolean brxagcswitch; /* for rx AGC table switch in Microsoft case */
+ u8 support_interface;/*PHYDM PCIE/USB/SDIO = 1/2/3*/
+ u32 support_ic_type; /*PHYDM supported IC*/
+ u8 cut_version; /*cut version TestChip/A-cut/B-cut... = 0/1/2/3/...*/
+ u8 fab_version; /*Fab version TSMC/UMC = 0/1*/
+ u8 rf_type; /*RF type 4T4R/3T3R/2T2R/1T2R/1T1R/...*/
+ u8 rfe_type;
+ u8 board_type;
+ u8 package_type;
+ u16 type_glna;
+ u16 type_gpa;
+ u16 type_alna;
+ u16 type_apa;
+ u8 ext_lna; /*with 2G external LNA NO/Yes = 0/1*/
+ u8 ext_lna_5g; /*with 5G external LNA NO/Yes = 0/1*/
+ u8 ext_pa; /*with 2G external PNA NO/Yes = 0/1*/
+ u8 ext_pa_5g; /*with 5G external PNA NO/Yes = 0/1*/
+ u8 efuse0x3d7; /*with Efuse number*/
+ u8 efuse0x3d8;
+ u8 ext_trsw; /*with external TRSW NO/Yes = 0/1*/
+ u8 ext_lna_gain; /*gain of external lna*/
+ boolean is_in_hct_test;
+ u8 wifi_test;
+ boolean is_dual_mac_smart_concurrent;
+ u32 bk_support_ability; /*SD4 only*/
+ u8 with_extenal_ant_switch;
+ /*cck agc relative*/
+ boolean cck_new_agc;
+ s8 cck_lna_gain_table[8];
+ /*-------------------------------------*/
+ u32 phydm_sys_up_time;
+ u8 num_rf_path; /*ex: 8821C=1, 8192E=2, 8814B=4*/
+ u32 soft_ap_special_setting;
+ s8 s8_dummy;
+ u8 u8_dummy;
+ u16 u16_dummy;
+ u32 u32_dummy;
+ u8 rfe_hwsetting_band;
+ u8 p_advance_ota;
+ boolean hp_hw_id;
+ boolean BOOLEAN_temp;
+ boolean is_dfs_band;
+ u8 is_receiver_blocking_en;
+ u16 fw_offload_ability;
+/*-----------HOOK BEFORE REG INIT-----------*/
+/*===========================================================*/
+/*====[ CALL BY Reference ]=========================================*/
+/*===========================================================*/
+
+ u64 *num_tx_bytes_unicast; /*TX Unicast byte count*/
+ u64 *num_rx_bytes_unicast; /*RX Unicast byte count*/
+ u8 *band_type; /*Frequence band 2.4G/5G = 0/1*/
+ u8 *sec_ch_offset; /*Secondary channel offset don't_care/below/above = 0/1/2*/
+ u8 *security; /*security mode Open/WEP/AES/TKIP = 0/1/2/3*/
+ u8 *band_width; /*BW info 20M/40M/80M = 0/1/2*/
+ u8 *channel; /*central channel number*/
+ boolean *is_scan_in_process; /*Common info for status*/
+ boolean *is_power_saving;
+ u8 *one_path_cca; /*CCA path 2-path/path-A/path-B = 0/1/2; using enum odm_cca_path.*/
+ u8 *antenna_test;
+ boolean *is_net_closed;
+ boolean *is_fcs_mode_enable;
+ /*--------- For 8723B IQK-------------------------------------*/
+ boolean *is_1_antenna;
+ u8 *rf_default_path; /* 0:S1, 1:S0 */
+ /*-----------------------------------------------------------*/
+
+ u16 *forced_data_rate;
+ u8 *enable_antdiv;
+ u8 *en_adap_soml;
+ u8 *enable_adaptivity;
+ u8 *hub_usb_mode; /*1: USB 2.0, 2: USB 3.0*/
+ boolean *is_fw_dw_rsvd_page_in_progress;
+ u32 *current_tx_tp;
+ u32 *current_rx_tp;
+ u8 *sounding_seq;
+ u32 *soft_ap_mode;
+ u8 *mp_mode;
+ u32 *interrupt_mask;
+ u8 *bb_op_mode;
+/*===========================================================*/
+/*====[ CALL BY VALUE ]===========================================*/
+/*===========================================================*/
+
+ u8 disable_phydm_watchdog;
+ boolean is_link_in_process;
+ boolean is_wifi_direct;
+ boolean is_wifi_display;
+ boolean is_linked;
+ boolean bsta_state;
+ u8 rssi_min;
+ u8 pre_rssi_min;
+ u8 rssi_max;
+ u8 rssi_min_by_path;
+ boolean is_mp_chip;
+ boolean is_one_entry_only;
+ u32 one_entry_macid;
+ u32 one_entry_tp;
+ u32 pre_one_entry_tp;
+ u8 pre_number_linked_client;
+ u8 number_linked_client;
+ u8 pre_number_active_client;
+ u8 number_active_client;
+ boolean is_disable_phy_api;
+ u8 rssi_a;
+ u8 rssi_b;
+ u8 rssi_c;
+ u8 rssi_d;
+ u64 rssi_trsw;
+ u64 rssi_trsw_h;
+ u64 rssi_trsw_l;
+ u64 rssi_trsw_iso;
+ u8 tx_ant_status;
+ u8 rx_ant_status;
+ u8 cck_lna_idx;
+ u8 cck_vga_idx;
+ u8 curr_station_id;
+ u8 ofdm_agc_idx[4];
+ u8 rx_rate;
+ u8 rate_ss;
+ u8 tx_rate;
+ u8 linked_interval;
+ u8 pre_channel;
+ u32 txagc_offset_value_a;
+ boolean is_txagc_offset_positive_a;
+ u32 txagc_offset_value_b;
+ boolean is_txagc_offset_positive_b;
+ /*[traffic]*/
+ u8 traffic_load;
+ u8 pre_traffic_load;
+ u32 tx_tp; /*Mbps*/
+ u32 rx_tp; /*Mbps*/
+ u32 total_tp;/*Mbps*/
+ u8 txrx_state_all; /*0: tx, 1:rx, 2:bi-direction*/
+ u64 cur_tx_ok_cnt;
+ u64 cur_rx_ok_cnt;
+ u64 last_tx_ok_cnt;
+ u64 last_rx_ok_cnt;
+ u16 consecutive_idlel_time; /*unit: second*/
+ /*---------------------------*/
+ boolean is_bb_swing_offset_positive_a;
+ boolean is_bb_swing_offset_positive_b;
+
+ /*[DIG]*/
+ boolean MPDIG_2G; /*off MPDIG*/
+ u8 times_2g; /*for MP DIG*/
+
+ /*[TDMA-DIG]*/
+ u8 tdma_dig_timer_ms;
+ u8 tdma_dig_state_number;
+ u8 tdma_dig_low_upper_bond;
+ u8 fix_expire_to_zero;
+ boolean original_dig_restore;
+ /*---------------------------*/
+
+ /*[AntDiv]*/
+ u8 ant_div_type;
+ u8 antdiv_rssi;
+ u8 fat_comb_a;
+ u8 fat_comb_b;
+ u8 antdiv_intvl;
+ u8 ant_type;
+ u8 pre_ant_type;
+ u8 antdiv_period;
+ u8 evm_antdiv_period;
+ u8 antdiv_select;
+ u8 antdiv_train_num;/*training time for each antenna in EVM method*/
+ u8 stop_antdiv_rssi_th;
+ u16 stop_antdiv_tp_diff_th;
+ u16 stop_antdiv_tp_th;
+ u8 antdiv_tp_period;
+ u16 tp_active_th;
+ u8 tp_active_occur;
+ u8 path_select;
+ u8 antdiv_evm_en;
+ u8 bdc_holdstate;
+ /*---------------------------*/
- // MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2
- u1Byte *pMacPhyMode;
- //TX Unicast byte count
- u8Byte *pNumTxBytesUnicast;
- //RX Unicast byte count
- u8Byte *pNumRxBytesUnicast;
- // Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3
- u1Byte *pWirelessMode; //ODM_WIRELESS_MODE_E
- // Frequence band 2.4G/5G = 0/1
- u1Byte *pBandType;
- // Secondary channel offset don't_care/below/above = 0/1/2
- u1Byte *pSecChOffset;
- // Security mode Open/WEP/AES/TKIP = 0/1/2/3
- u1Byte *pSecurity;
- // BW info 20M/40M/80M = 0/1/2
- u1Byte *pBandWidth;
- // Central channel location Ch1/Ch2/....
- u1Byte *pChannel; //central channel number
- BOOLEAN DPK_Done;
- // Common info for 92D DMSP
+ u8 ndpa_period;
+ boolean h2c_rarpt_connect;
+ boolean cck_agc_report_type;
+ u8 print_agc;
+ u8 la_mode;
+ /*---8821C Antenna and RF Set BTG/WLG/WLA Select---------------*/
+ u8 current_rf_set_8821c;
+ u8 default_rf_set_8821c;
+ u8 current_ant_num_8821c;
+ u8 default_ant_num_8821c;
+ u8 rfe_type_expand;
+ /*-----------------------------------------------------------*/
+ /*---For Adaptivtiy---------------------------------------------*/
+ s8 TH_L2H_default;
+ s8 th_edcca_hl_diff_default;
+ s8 th_l2h_ini;
+ s8 th_edcca_hl_diff;
+ s8 th_l2h_ini_mode2;
+ s8 th_edcca_hl_diff_mode2;
+ boolean carrier_sense_enable;
+ boolean adaptivity_flag; /*Limit IGI upper bound for Adaptivity*/
+ u8 dc_backoff;
+ boolean adaptivity_enable;
+ u8 ap_total_num;
+ boolean edcca_enable;
+ u8 odm_regulation_2_4g;
+ u8 odm_regulation_5g;
+ /*-----------------------------------------------------------*/
- BOOLEAN *pbGetValueFromOtherMac;
- PADAPTER *pBuddyAdapter;
- BOOLEAN *pbMasterOfDMSP; //MAC0: master, MAC1: slave
- // Common info for Status
- BOOLEAN *pbScanInProcess;
- BOOLEAN *pbPowerSaving;
- // CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E.
- u1Byte *pOnePathCCA;
- //pMgntInfo->AntennaTest
- u1Byte *pAntennaTest;
- BOOLEAN *pbNet_closed;
- //u1Byte *pAidMap;
- u1Byte *pu1ForcedIgiLb;
- BOOLEAN *pIsFcsModeEnable;
-/*--------- For 8723B IQK-----------*/
- BOOLEAN *pIs1Antenna;
- u1Byte *pRFDefaultPath;
- // 0:S1, 1:S0
+ u8 pre_dbg_priority;
+ u8 nbi_set_result;
+ u8 c2h_cmd_start;
+ u8 fw_debug_trace[60];
+ u8 pre_c2h_seq;
+ boolean fw_buff_is_enpty;
+ u32 data_frame_num;
+
+ /*--- for noise detection ---------------------------------------*/
+ boolean is_noisy_state;
+ boolean noisy_decision; /*b_noisy*/
+ boolean pre_b_noisy;
+ u32 noisy_decision_smooth;
+ u8 lna_sat_chk_cnt;
+ u8 lna_sat_chk_duty_cycle;
+ u32 lna_sat_chk_period_ms;
+ boolean is_disable_lna_sat_chk;
+ boolean is_disable_gain_table_switch;
+ /*-----------------------------------------------------------*/
-//--------- POINTER REFERENCE-----------//
- pu2Byte pForcedDataRate;
- pu1Byte HubUsbMode;
- BOOLEAN *pbFwDwRsvdPageInProgress;
- u4Byte *pCurrentTxTP;
- u4Byte *pCurrentRxTP;
- u1Byte *pSoundingSeq;
-//------------CALL BY VALUE-------------//
- BOOLEAN bLinkInProcess;
- BOOLEAN bWIFI_Direct;
- BOOLEAN bWIFI_Display;
- BOOLEAN bLinked;
- BOOLEAN bsta_state;
-#if(DM_ODM_SUPPORT_TYPE & ODM_AP) // for repeater mode add by YuChen 2014.06.23
-#ifdef UNIVERSAL_REPEATER
- BOOLEAN VXD_bLinked;
+ boolean is_disable_dym_ecs;
+ boolean is_disable_dym_ant_weighting;
+ struct sta_info *odm_sta_info[ODM_ASSOCIATE_ENTRY_NUM];/*odm_sta_info, 2012/01/12 MH For MP, we need to reduce one array pointer for default port.??*/
+ struct cmn_sta_info *phydm_sta_info[ODM_ASSOCIATE_ENTRY_NUM];
+ u8 phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM];
+
+#if (RATE_ADAPTIVE_SUPPORT == 1)
+ u16 currmin_rpt_time;
+ struct _odm_ra_info_ ra_info[ODM_ASSOCIATE_ENTRY_NUM];
+ /*Use mac_id as array index. STA mac_id=0, VWiFi Client mac_id={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119*/
#endif
-#endif // for repeater mode add by YuChen 2014.06.23
- u1Byte RSSI_Min;
- u1Byte InterfaceIndex; /*Add for 92D dual MAC: 0--Mac0 1--Mac1*/
- BOOLEAN bIsMPChip;
- BOOLEAN bOneEntryOnly;
- BOOLEAN mp_mode;
- u4Byte OneEntry_MACID;
- u1Byte pre_number_linked_client;
- u1Byte number_linked_client;
- u1Byte pre_number_active_client;
- u1Byte number_active_client;
- // Common info for BTDM
- BOOLEAN bBtEnabled; // BT is enabled
- BOOLEAN bBtConnectProcess; // BT HS is under connection progress.
- u1Byte btHsRssi; // BT HS mode wifi rssi value.
- BOOLEAN bBtHsOperation; // BT HS mode is under progress
- u1Byte btHsDigVal; // use BT rssi to decide the DIG value
- BOOLEAN bBtDisableEdcaTurbo; // Under some condition, don't enable the EDCA Turbo
- BOOLEAN bBtBusy; // BT is busy.
- BOOLEAN bBtLimitedDig; // BT is busy.
- BOOLEAN bDisablePhyApi;
-//------------CALL BY VALUE-------------//
- u1Byte RSSI_A;
- u1Byte RSSI_B;
- u1Byte RSSI_C;
- u1Byte RSSI_D;
- u8Byte RSSI_TRSW;
- u8Byte RSSI_TRSW_H;
- u8Byte RSSI_TRSW_L;
- u8Byte RSSI_TRSW_iso;
- u1Byte TXAntStatus;
- u1Byte RXAntStatus;
- u1Byte cck_lna_idx;
- u1Byte cck_vga_idx;
- u1Byte curr_station_id;
- u1Byte ofdm_agc_idx[4];
-
- u1Byte RxRate;
- BOOLEAN bNoisyState;
- u1Byte TxRate;
- u1Byte LinkedInterval;
- u1Byte preChannel;
- u4Byte TxagcOffsetValueA;
- BOOLEAN IsTxagcOffsetPositiveA;
- u4Byte TxagcOffsetValueB;
- BOOLEAN IsTxagcOffsetPositiveB;
- u4Byte tx_tp;
- u4Byte rx_tp;
- u4Byte total_tp;
- u8Byte curTxOkCnt;
- u8Byte curRxOkCnt;
- u8Byte lastTxOkCnt;
- u8Byte lastRxOkCnt;
- u4Byte BbSwingOffsetA;
- BOOLEAN IsBbSwingOffsetPositiveA;
- u4Byte BbSwingOffsetB;
- BOOLEAN IsBbSwingOffsetPositiveB;
- u1Byte IGI_LowerBound;
- u1Byte IGI_UpperBound;
- u1Byte antdiv_rssi;
- u1Byte fat_comb_a;
- u1Byte fat_comb_b;
- u1Byte antdiv_intvl;
- u1Byte AntType;
- u1Byte pre_AntType;
- u1Byte antdiv_period;
- u1Byte evm_antdiv_period;
- u1Byte antdiv_select;
- u1Byte path_select;
- u1Byte antdiv_evm_en;
- u1Byte bdc_holdstate;
- u1Byte NdpaPeriod;
- BOOLEAN H2C_RARpt_connect;
- BOOLEAN cck_agc_report_type;
+ boolean ra_support88e; /*2012/02/14 MH Add to share 88E ra with other SW team.We need to colelct all support abilit to a proper area.*/
+ boolean *is_driver_stopped;
+ boolean *is_driver_is_going_to_pnp_set_power_sleep;
+ boolean *pinit_adpt_in_progress;
+ boolean is_user_assign_level;
+ u8 RSSI_BT; /*come from BT*/
+
+ /*---PSD Relative ---------------------------------------------*/
+ boolean is_psd_in_process;
+ boolean is_psd_active;
+ /*-----------------------------------------------------------*/
- u1Byte dm_dig_max_TH;
- u1Byte dm_dig_min_TH;
- u1Byte print_agc;
- u1Byte TrafficLoad;
- u1Byte pre_TrafficLoad;
-
-
- //For Adaptivtiy
- u2Byte NHM_cnt_0;
- u2Byte NHM_cnt_1;
- s1Byte TH_L2H_default;
- s1Byte TH_EDCCA_HL_diff_default;
- s1Byte TH_L2H_ini;
- s1Byte TH_EDCCA_HL_diff;
- s1Byte TH_L2H_ini_mode2;
- s1Byte TH_EDCCA_HL_diff_mode2;
- BOOLEAN Carrier_Sense_enable;
- u1Byte Adaptivity_IGI_upper;
- BOOLEAN adaptivity_flag;
- u1Byte DCbackoff;
- BOOLEAN Adaptivity_enable;
- u1Byte APTotalNum;
- BOOLEAN EDCCA_enable;
- ADAPTIVITY_STATISTICS Adaptivity;
- //For Adaptivtiy
- u1Byte LastUSBHub;
- u1Byte TxBfDataRate;
-
- u1Byte nbi_set_result;
-
- u1Byte c2h_cmd_start;
- u1Byte fw_debug_trace[60];
- u1Byte pre_c2h_seq;
- BOOLEAN fw_buff_is_enpty;
- u4Byte data_frame_num;
-
- /*for noise detection*/
- BOOLEAN NoisyDecision; /*b_noisy*/
- BOOLEAN pre_b_noisy;
- u4Byte NoisyDecision_Smooth;
-
-#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
- ODM_NOISE_MONITOR noise_level;//[ODM_MAX_CHANNEL_NUM];
+ boolean bsomlenabled; /* for dynamic SoML control */
+ boolean bhtstfdisabled; /* for dynamic HTSTF gain control */
+ boolean disrxhpsoml; /* for dynamic RxHP control with SoML on/off */
+ u32 n_iqk_cnt;
+ u32 n_iqk_ok_cnt;
+ u32 n_iqk_fail_cnt;
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ boolean config_bbrf;
#endif
- //
- //2 Define STA info.
- // _ODM_STA_INFO
- // 2012/01/12 MH For MP, we need to reduce one array pointer for default port.??
- PSTA_INFO_T pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM];
- u2Byte platform2phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM]; /* platform_macid_table[platform_macid] = phydm_macid */
-#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
- s4Byte AccumulatePWDB[ODM_ASSOCIATE_ENTRY_NUM];
+ boolean is_disable_power_training;
+ boolean is_bt_continuous_turn;
+ u8 dynamic_tx_high_power_lvl;
+ u8 last_dtp_lvl;
+ u8 min_power_index;
+ u32 tx_agc_ofdm_18_6;
+ u8 rx_pkt_type;
+
+#ifdef CONFIG_PHYDM_DFS_MASTER
+ u8 dfs_region_domain;
+ u8 *dfs_master_enabled;
+ /*---phydm_radar_detect_with_dbg_parm start --------------------*/
+ u8 radar_detect_dbg_parm_en;
+ u32 radar_detect_reg_918;
+ u32 radar_detect_reg_91c;
+ u32 radar_detect_reg_920;
+ u32 radar_detect_reg_924;
+ /*-----------------------------------------------------------*/
#endif
-#if (RATE_ADAPTIVE_SUPPORT == 1)
- u2Byte CurrminRptTime;
- ODM_RA_INFO_T RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; //Use MacID as array index. STA MacID=0, VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119
+/*=== PHYDM Timer ========================================== (start)*/
+
+ struct phydm_timer_list mpt_dig_timer; /*MPT DIG timer*/
+ struct phydm_timer_list path_div_switch_timer;
+ struct phydm_timer_list cck_path_diversity_timer; /*2011.09.27 add for path Diversity*/
+ struct phydm_timer_list fast_ant_training_timer;
+#ifdef ODM_EVM_ENHANCE_ANTDIV
+ struct phydm_timer_list evm_fast_ant_training_timer;
+#endif
+ struct phydm_timer_list sbdcnt_timer;
+
+
+/*=== PHYDM Workitem ======================================= (start)*/
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+#if USE_WORKITEM
+ RT_WORK_ITEM path_div_switch_workitem;
+ RT_WORK_ITEM cck_path_diversity_workitem;
+ RT_WORK_ITEM fast_ant_training_workitem;
+ RT_WORK_ITEM ra_rpt_workitem;
+ RT_WORK_ITEM sbdcnt_workitem;
+#endif
#endif
- //
- // 2012/02/14 MH Add to share 88E ra with other SW team.
- // We need to colelct all support abilit to a proper area.
- //
- BOOLEAN RaSupport88E;
- // Define ...........
- // Latest packet phy info (ODM write)
- ODM_PHY_DBG_INFO_T PhyDbgInfo;
- //PHY_INFO_88E PhyInfo;
+/*=== PHYDM Structure ======================================== (start)*/
+ struct phydm_func_poiner phydm_func_handler;
+ struct phydm_iot_center iot_table;
- // Latest packet phy info (ODM write)
- ODM_MAC_INFO *pMacInfo;
- //MAC_INFO_88E MacInfo;
+#ifdef ODM_CONFIG_BT_COEXIST
+ struct phydm_bt_info bt_info_table;
+#endif
+
+ struct pkt_process_info pkt_proc_struct;
+ struct phydm_adaptivity_struct adaptivity;
+ struct _DFS_STATISTICS dfs;
- // Different Team independt structure??
+ struct odm_noise_monitor noise_level;
- //
- //TX_RTP_CMN TX_retrpo;
- //TX_RTP_88E TX_retrpo;
- //TX_RTP_8195 TX_retrpo;
+ struct odm_phy_dbg_info phy_dbg_info;
+
+#ifdef CONFIG_ADAPTIVE_SOML
+ struct adaptive_soml dm_soml_table;
+#endif
- //
- //ODM Structure
- //
#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
- BDC_T DM_BdcTable;
+ struct _BF_DIV_COEX_ dm_bdc_table;
#endif
-
- #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
- SAT_T dm_sat_table;
+
+ #if (defined(CONFIG_HL_SMART_ANTENNA))
+ struct smt_ant_honbo dm_sat_table;
#endif
+#endif
+
+#if (defined(CONFIG_SMART_ANTENNA))
+ struct smt_ant smtant_table;
+#endif
+
+ struct phydm_fat_struct dm_fat_table;
+ struct phydm_dig_struct dm_dig_table;
+ struct phydm_lna_sat_info_struct dm_lna_sat_info;
+
+#ifdef PHYDM_SUPPORT_CCKPD
+ struct phydm_cckpd_struct dm_cckpd_table;
+#endif
+#ifdef PHYDM_PRIMARY_CCA
+ struct phydm_pricca_struct dm_pri_cca;
#endif
- FAT_T DM_FatTable;
- DIG_T DM_DigTable;
-
- PS_T DM_PSTable;
- Pri_CCA_T DM_PriCCA;
- RA_T DM_RA_Table;
- FALSE_ALARM_STATISTICS FalseAlmCnt;
- FALSE_ALARM_STATISTICS FlaseAlmCntBuddyAdapter;
- SWAT_T DM_SWAT_Table;
- CFO_TRACKING DM_CfoTrack;
- ACS DM_ACS;
- CCX_INFO DM_CCX_INFO;
-#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
- RT_ADCSMP adcsmp;
+
+ struct ra_table dm_ra_table;
+ struct phydm_fa_struct false_alm_cnt;
+#ifdef PHYDM_TDMA_DIG_SUPPORT
+ struct phydm_fa_acc_struct false_alm_cnt_acc;
+#endif
+ struct sw_antenna_switch dm_swat_table;
+ struct phydm_cfo_track_struct dm_cfo_track;
+ struct ccx_info dm_ccx_info;
+ struct _hal_rf_ rf_table; /*for HALRF function*/
+ struct dm_rf_calibration_struct rf_calibrate_info;
+ struct odm_power_trim_data power_trim_data;
+#if (RTL8822B_SUPPORT == 1)
+ struct drp_rtl8822b_struct phydm_rtl8822b;
#endif
-#if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
- IQK_INFO IQK_info;
+#ifdef CONFIG_PSD_TOOL
+ struct psd_info dm_psd_table;
#endif
-#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
- //Path Div Struct
- PATHDIV_PARA pathIQK;
+#if (PHYDM_LA_MODE_SUPPORT == 1)
+ struct rt_adcsmp adcsmp;
#endif
-#if(defined(CONFIG_PATH_DIVERSITY))
- PATHDIV_T DM_PathDiv;
-#endif
-
- EDCA_T DM_EDCA_Table;
- u4Byte WMMEDCA_BE;
-
- // Copy from SD4 structure
- //
- // ==================================================
- //
-
- //common
- //u1Byte DM_Type;
- //u1Byte PSD_Report_RXHP[80]; // Add By Gary
- //u1Byte PSD_func_flag; // Add By Gary
- //for DIG
- //u1Byte bDMInitialGainEnable;
- //u1Byte binitialized; // for dm_initial_gain_Multi_STA use.
-
- BOOLEAN *pbDriverStopped;
- BOOLEAN *pbDriverIsGoingToPnpSetPowerSleep;
- BOOLEAN *pinit_adpt_in_progress;
-
- //PSD
- BOOLEAN bUserAssignLevel;
- u1Byte RSSI_BT; /*come from BT*/
- BOOLEAN bPSDinProcess;
- BOOLEAN bPSDactive;
- BOOLEAN bDMInitialGainEnable;
-
- //MPT DIG
- RT_TIMER MPT_DIGTimer;
-
- //for rate adaptive, in fact, 88c/92c fw will handle this
- u1Byte bUseRAMask;
- ODM_RATE_ADAPTIVE RateAdaptive;
- #if (defined(CONFIG_ANT_DETECTION))
- ANT_DETECTED_INFO AntDetectedInfo; /* Antenna detected information for RSSI tool*/
- #endif
- ODM_RF_CAL_T RFCalibrateInfo;
- u4Byte nIQK_Cnt;
- u4Byte nIQK_OK_Cnt;
- u4Byte nIQK_Fail_Cnt;
-
-#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
- //
- // Power Training
- //
- u1Byte ForcePowerTrainingState;
- BOOLEAN bChangeState;
- u4Byte PT_score;
- u8Byte OFDM_RX_Cnt;
- u8Byte CCK_RX_Cnt;
+#ifdef CONFIG_DYNAMIC_RX_PATH
+ struct _DYNAMIC_RX_PATH_ dm_drp_table;
#endif
- BOOLEAN bDisablePowerTraining;
- u1Byte DynamicTxHighPowerLvl;
- u1Byte LastDTPLvl;
- u4Byte tx_agc_ofdm_18_6;
- u1Byte rx_pkt_type;
-
- //
- // ODM system resource.
- //
-
- // ODM relative time.
- RT_TIMER PathDivSwitchTimer;
- //2011.09.27 add for Path Diversity
- RT_TIMER CCKPathDiversityTimer;
- RT_TIMER FastAntTrainingTimer;
- #ifdef ODM_EVM_ENHANCE_ANTDIV
- RT_TIMER EVM_FastAntTrainingTimer;
- #endif
- RT_TIMER sbdcnt_timer;
- // ODM relative workitem.
-#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-#if USE_WORKITEM
- RT_WORK_ITEM PathDivSwitchWorkitem;
- RT_WORK_ITEM CCKPathDiversityWorkitem;
- RT_WORK_ITEM FastAntTrainingWorkitem;
- RT_WORK_ITEM MPT_DIGWorkitem;
- RT_WORK_ITEM RaRptWorkitem;
- RT_WORK_ITEM sbdcnt_workitem;
+ struct dm_iqk_info IQK_info;
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+ struct _path_div_parameter_define_ path_iqk;
+#endif
+
+#if (defined(CONFIG_PATH_DIVERSITY))
+ struct _ODM_PATH_DIVERSITY_ dm_path_div;
#endif
+
+#if (defined(CONFIG_ANT_DETECTION))
+ struct _ANT_DETECTED_INFO ant_detected_info; /* Antenna detected information for RSSI tool*/
#endif
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
#if (BEAMFORMING_SUPPORT == 1)
- RT_BEAMFORMING_INFO BeamformingInfo;
-#endif
+ struct _RT_BEAMFORMING_INFO beamforming_info;
+#endif
+#endif
+#ifdef PHYDM_AUTO_DEGBUG
+ struct phydm_auto_dbg_struc auto_dbg_table;
#endif
-#ifdef CONFIG_PHYDM_DFS_MASTER
- u1Byte DFS_RegionDomain;
- pu1Byte dfs_master_enabled;
-
- /*====== phydm_radar_detect_with_dbg_parm start ======*/
- u1Byte radar_detect_dbg_parm_en;
- u4Byte radar_detect_reg_918;
- u4Byte radar_detect_reg_91c;
- u4Byte radar_detect_reg_920;
- u4Byte radar_detect_reg_924;
- /*====== phydm_radar_detect_with_dbg_parm end ======*/
+ struct phydm_pause_lv pause_lv_table;
+ struct phydm_api_stuc api_table;
+#ifdef PHYDM_POWER_TRAINING_SUPPORT
+ struct phydm_pow_train_stuc pow_train_table;
#endif
+/*==========================================================*/
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-#if(DM_ODM_SUPPORT_TYPE & ODM_WIN)
-
#if (RT_PLATFORM != PLATFORM_LINUX)
-} DM_ODM_T, *PDM_ODM_T; // DM_Dynamic_Mechanism_Structure
+}dm_struct; /*DM_Dynamic_Mechanism_Structure*/
#else
};
-#endif
+#endif
-#else// for AP,ADSL,CE Team
-} DM_ODM_T, *PDM_ODM_T; // DM_Dynamic_Mechanism_Structure
+#else /*for AP,CE Team*/
+};
#endif
+enum phydm_adv_ota {
+ PHYDM_PATHB_1RCCA = BIT(0),
+ PHYDM_HP_OTA_SETTING_A = BIT(1),
+ PHYDM_HP_OTA_SETTING_B = BIT(2),
+ PHYDM_ASUS_OTA_SETTING = BIT(3),
+ PHYDM_ASUS_OTA_SETTING_CCK_PATH = BIT(4),
+ PHYDM_HP_OTA_SETTING_CCK_PATH = BIT(5),
+ PHYDM_LENOVO_OTA_SETTING_NBI_CSI = BIT(6),
-typedef enum _PHYDM_STRUCTURE_TYPE{
+};
+
+enum phydm_bb_op_mode {
+ PHYDM_PERFORMANCE_MODE = 0, /*Service one device*/
+ PHYDM_BALANCE_MODE = 1, /*Service more than one device*/
+};
+
+enum phydm_structure_type {
PHYDM_FALSEALMCNT,
PHYDM_CFOTRACK,
PHYDM_ADAPTIVITY,
+ PHYDM_DFS,
PHYDM_ROMINFO,
-
-}PHYDM_STRUCTURE_TYPE;
+};
-
- typedef enum _ODM_RF_CONTENT{
- odm_radioa_txt = 0x1000,
- odm_radiob_txt = 0x1001,
- odm_radioc_txt = 0x1002,
- odm_radiod_txt = 0x1003
-} ODM_RF_CONTENT;
-
-typedef enum _ODM_BB_Config_Type{
- CONFIG_BB_PHY_REG,
- CONFIG_BB_AGC_TAB,
+enum odm_bb_config_type {
+ CONFIG_BB_PHY_REG,
+ CONFIG_BB_AGC_TAB,
CONFIG_BB_AGC_TAB_2G,
- CONFIG_BB_AGC_TAB_5G,
+ CONFIG_BB_AGC_TAB_5G,
CONFIG_BB_PHY_REG_PG,
CONFIG_BB_PHY_REG_MP,
CONFIG_BB_AGC_TAB_DIFF,
-} ODM_BB_Config_Type, *PODM_BB_Config_Type;
+};
-typedef enum _ODM_RF_Config_Type{
+enum odm_rf_config_type {
CONFIG_RF_RADIO,
- CONFIG_RF_TXPWR_LMT,
-} ODM_RF_Config_Type, *PODM_RF_Config_Type;
-
-typedef enum _ODM_FW_Config_Type{
- CONFIG_FW_NIC,
- CONFIG_FW_NIC_2,
- CONFIG_FW_AP,
- CONFIG_FW_AP_2,
- CONFIG_FW_MP,
- CONFIG_FW_WoWLAN,
- CONFIG_FW_WoWLAN_2,
- CONFIG_FW_AP_WoWLAN,
- CONFIG_FW_BT,
-} ODM_FW_Config_Type;
-
-// Status code
+ CONFIG_RF_TXPWR_LMT,
+};
+
+enum odm_fw_config_type {
+ CONFIG_FW_NIC,
+ CONFIG_FW_NIC_2,
+ CONFIG_FW_AP,
+ CONFIG_FW_AP_2,
+ CONFIG_FW_MP,
+ CONFIG_FW_WOWLAN,
+ CONFIG_FW_WOWLAN_2,
+ CONFIG_FW_AP_WOWLAN,
+ CONFIG_FW_BT,
+};
+
+/*status code*/
#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
-typedef enum _RT_STATUS{
+enum rt_status {
RT_STATUS_SUCCESS,
RT_STATUS_FAILURE,
RT_STATUS_PENDING,
@@ -1095,303 +1055,183 @@ typedef enum _RT_STATUS{
RT_STATUS_INVALID_PARAMETER,
RT_STATUS_NOT_SUPPORT,
RT_STATUS_OS_API_FAILED,
-}RT_STATUS,*PRT_STATUS;
-#endif // end of RT_STATUS definition
-
-#ifdef REMOVE_PACK
-#pragma pack()
-#endif
-
-//3===========================================================
-//3 AGC RX High Power Mode
-//3===========================================================
-#define LNA_Low_Gain_1 0x64
-#define LNA_Low_Gain_2 0x5A
-#define LNA_Low_Gain_3 0x58
-
-#define FA_RXHP_TH1 5000
-#define FA_RXHP_TH2 1500
-#define FA_RXHP_TH3 800
-#define FA_RXHP_TH4 600
-#define FA_RXHP_TH5 500
-
-typedef enum tag_1R_CCA_Type_Definition
-{
- CCA_1R =0,
- CCA_2R = 1,
- CCA_MAX = 2,
-}DM_1R_CCA_E;
-
-typedef enum tag_RF_Type_Definition
-{
- RF_Save =0,
- RF_Normal = 1,
- RF_MAX = 2,
-}DM_RF_E;
-
-//
-// check Sta pointer valid or not
-//
-#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
-#define IS_STA_VALID(pSta) (pSta && pSta->expire_to)
-#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-#define IS_STA_VALID(pSta) (pSta && pSta->bUsed)
-#else
-#define IS_STA_VALID(pSta) (pSta)
-#endif
-
-#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_AP))
-
-BOOLEAN
-ODM_CheckPowerStatus(
- IN PADAPTER Adapter
- );
-
-#endif
-
-
-
-u4Byte odm_ConvertTo_dB(u4Byte Value);
-
-u4Byte odm_ConvertTo_linear(u4Byte Value);
-
-#if((DM_ODM_SUPPORT_TYPE==ODM_WIN)||(DM_ODM_SUPPORT_TYPE==ODM_CE))
-
-u4Byte
-GetPSDData(
- PDM_ODM_T pDM_Odm,
- unsigned int point,
- u1Byte initial_gain_psd);
+};
+#endif /*end of enum rt_status definition*/
-#endif
+void
+phydm_watchdog_lps(
+ struct dm_struct *dm
+);
-#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-VOID
-ODM_DMWatchdog_LPS(
- IN PDM_ODM_T pDM_Odm
+void
+phydm_watchdog_lps_32k(
+ struct dm_struct *dm
);
-#endif
+void
+phydm_txcurrentcalibration(
+ struct dm_struct *dm
+);
-s4Byte
-ODM_PWdB_Conversion(
- IN s4Byte X,
- IN u4Byte TotalBit,
- IN u4Byte DecimalBit
- );
+void
+phydm_dm_early_init(
+ struct dm_struct *dm
+);
-s4Byte
-ODM_SignConversion(
- IN s4Byte value,
- IN u4Byte TotalBit
- );
+void
+odm_dm_init(
+ struct dm_struct *dm
+);
void
-phydm_seq_sorting(
- IN PVOID pDM_VOID,
- IN OUT u4Byte *p_value,
- IN OUT u4Byte *rank_idx,
- IN OUT u4Byte *p_idx_out,
- IN u1Byte seq_length
+odm_dm_reset(
+ struct dm_struct *dm
);
-VOID
-ODM_DMInit(
- IN PDM_ODM_T pDM_Odm
+void
+phydm_fwoffload_ability_init(
+ struct dm_struct *dm,
+ enum phydm_offload_ability offload_ability
);
-VOID
-ODM_DMReset(
- IN PDM_ODM_T pDM_Odm
- );
+void
+phydm_fwoffload_ability_clear(
+ struct dm_struct *dm,
+ enum phydm_offload_ability offload_ability
+);
-VOID
+void
phydm_support_ability_debug(
- IN PVOID pDM_VOID,
- IN u4Byte *const dm_value,
- IN u4Byte *_used,
- OUT char *output,
- IN u4Byte *_out_len
- );
-
-VOID
-phydm_config_trx_path(
- IN PVOID pDM_VOID,
- IN u4Byte *const dm_value,
- IN u4Byte *_used,
- OUT char *output,
- IN u4Byte *_out_len
- );
-
-VOID
-ODM_DMWatchdog(
- IN PDM_ODM_T pDM_Odm // For common use in the future
- );
-
-VOID
-ODM_CmnInfoInit(
- IN PDM_ODM_T pDM_Odm,
- IN ODM_CMNINFO_E CmnInfo,
- IN u4Byte Value
- );
-
-VOID
-ODM_CmnInfoHook(
- IN PDM_ODM_T pDM_Odm,
- IN ODM_CMNINFO_E CmnInfo,
- IN PVOID pValue
- );
-
-VOID
-ODM_CmnInfoPtrArrayHook(
- IN PDM_ODM_T pDM_Odm,
- IN ODM_CMNINFO_E CmnInfo,
- IN u2Byte Index,
- IN PVOID pValue
- );
-
-VOID
-ODM_CmnInfoUpdate(
- IN PDM_ODM_T pDM_Odm,
- IN u4Byte CmnInfo,
- IN u8Byte Value
- );
-
-#if(DM_ODM_SUPPORT_TYPE==ODM_AP)
-VOID
-ODM_InitAllThreads(
- IN PDM_ODM_T pDM_Odm
- );
-
-VOID
-ODM_StopAllThreads(
- IN PDM_ODM_T pDM_Odm
- );
-#endif
-
-VOID
-ODM_InitAllTimers(
- IN PDM_ODM_T pDM_Odm
- );
-
-VOID
-ODM_CancelAllTimers(
- IN PDM_ODM_T pDM_Odm
- );
-
-VOID
-ODM_ReleaseAllTimers(
- IN PDM_ODM_T pDM_Odm
- );
-
-
+ void *dm_void,
+ u32 *const dm_value,
+ u32 *_used,
+ char *output,
+ u32 *_out_len
+);
+void
+phydm_pause_dm_watchdog(
+ void *dm_void,
+ enum phydm_pause_type pause_type
+);
-#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-VOID ODM_InitAllWorkItems(IN PDM_ODM_T pDM_Odm );
-VOID ODM_FreeAllWorkItems(IN PDM_ODM_T pDM_Odm );
+void
+phydm_watchdog(
+ struct dm_struct *dm
+);
+void
+phydm_watchdog_mp(
+ struct dm_struct *dm
+);
+u8
+phydm_pause_func(
+ void *dm_void,
+ enum phydm_func_idx pause_func,
+ enum phydm_pause_type pause_type,
+ enum phydm_pause_level pause_lv,
+ u8 val_lehgth,
+ u32 *val_buf
+
+);
-u8Byte
-PlatformDivision64(
- IN u8Byte x,
- IN u8Byte y
+void
+phydm_pause_func_console(
+ void *dm_void,
+ char input[][16],
+ u32 *_used,
+ char *output,
+ u32 *_out_len,
+ u32 input_num
);
-//====================================================
-//3 PathDiV End
-//====================================================
+void
+odm_cmn_info_init(
+ struct dm_struct *dm,
+ enum odm_cmninfo cmn_info,
+ u64 value
+);
+void
+odm_cmn_info_hook(
+ struct dm_struct *dm,
+ enum odm_cmninfo cmn_info,
+ void *value
+);
-#define DM_ChangeDynamicInitGainThresh ODM_ChangeDynamicInitGainThresh
+void
+odm_cmn_info_update(
+ struct dm_struct *dm,
+ u32 cmn_info,
+ u64 value
+);
-typedef enum tag_DIG_Connect_Definition
-{
- DIG_STA_DISCONNECT = 0,
- DIG_STA_CONNECT = 1,
- DIG_STA_BEFORE_CONNECT = 2,
- DIG_MultiSTA_DISCONNECT = 3,
- DIG_MultiSTA_CONNECT = 4,
- DIG_CONNECT_MAX
-}DM_DIG_CONNECT_E;
-
-
-//
-// 2012/01/12 MH Check afapter status. Temp fix BSOD.
-//
-#define HAL_ADAPTER_STS_CHK(pDM_Odm)\
- if (pDM_Odm->Adapter == NULL)\
- {\
- return;\
- }\
-
-#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-
-VOID
-ODM_AsocEntry_Init(
- IN PDM_ODM_T pDM_Odm
- );
-
-
-PVOID
-PhyDM_Get_Structure(
- IN PDM_ODM_T pDM_Odm,
- IN u1Byte Structure_Type
+u32
+phydm_cmn_info_query(
+ struct dm_struct *dm,
+ enum phydm_info_query info_type
);
-#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) ||(DM_ODM_SUPPORT_TYPE == ODM_CE)
-/*===========================================================*/
-/* The following is for compile only*/
-/*===========================================================*/
+void
+odm_init_all_timers(
+ struct dm_struct *dm
+);
-#define IS_HARDWARE_TYPE_8723A(_Adapter) FALSE
-#define IS_HARDWARE_TYPE_8723AE(_Adapter) FALSE
-#define IS_HARDWARE_TYPE_8192C(_Adapter) FALSE
-#define IS_HARDWARE_TYPE_8192D(_Adapter) FALSE
-#define RF_T_METER_92D 0x42
+void
+odm_cancel_all_timers(
+ struct dm_struct *dm
+);
+void
+odm_release_all_timers(
+ struct dm_struct *dm
+);
-#define GET_RX_STATUS_DESC_RX_MCS(__pRxStatusDesc) LE_BITS_TO_1BYTE( __pRxStatusDesc+12, 0, 6)
+void *
+phydm_get_structure(
+ struct dm_struct *dm,
+ u8 structure_type
+);
-#define rConfig_ram64x16 0xb2c
+void
+phydm_dc_cancellation(
+ struct dm_struct *dm
+);
-#define TARGET_CHNL_NUM_2G_5G 59
+void
+phydm_receiver_blocking(
+ void *dm_void
+);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-u1Byte GetRightChnlPlaceforIQK(u1Byte chnl);
-#endif
-
-//===========================================================
-#endif
+void
+odm_init_all_work_items(
+ struct dm_struct *dm
+);
+void
+odm_free_all_work_items(
+ struct dm_struct *dm
+);
+#endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
-void odm_dtc(PDM_ODM_T pDM_Odm);
-#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */
-
-
-VOID phydm_NoisyDetection(IN PDM_ODM_T pDM_Odm );
-
-
+void
+odm_dtc(
+ struct dm_struct *dm
+);
#endif
-VOID
-phydm_api_debug(
- IN PVOID pDM_VOID,
- IN u4Byte function_map,
- IN u4Byte *const dm_value,
- IN u4Byte *_used,
- OUT char *output,
- IN u4Byte *_out_len
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+void
+odm_init_all_threads(
+ struct dm_struct *dm
);
-u1Byte
-phydm_nbi_setting(
- IN PVOID pDM_VOID,
- IN u4Byte enable,
- IN u4Byte channel,
- IN u4Byte bw,
- IN u4Byte f_interference,
- IN u4Byte Second_ch
+void
+odm_stop_all_threads(
+ struct dm_struct *dm
);
+#endif
+#endif
diff --git a/hal/phydm/phydm.mk b/hal/phydm/phydm.mk
new file mode 100644
index 0000000..1b9ade7
--- /dev/null
+++ b/hal/phydm/phydm.mk
@@ -0,0 +1,166 @@
+EXTRA_CFLAGS += -I$(src)/hal/phydm
+
+_PHYDM_FILES := hal/phydm/phydm_debug.o \
+ hal/phydm/phydm_antdiv.o\
+ hal/phydm/phydm_soml.o\
+ hal/phydm/phydm_smt_ant.o\
+ hal/phydm/phydm_antdect.o\
+ hal/phydm/phydm_interface.o\
+ hal/phydm/phydm_phystatus.o\
+ hal/phydm/phydm_hwconfig.o\
+ hal/phydm/phydm.o\
+ hal/phydm/phydm_dig.o\
+ hal/phydm/phydm_pathdiv.o\
+ hal/phydm/phydm_rainfo.o\
+ hal/phydm/phydm_dynamictxpower.o\
+ hal/phydm/phydm_adaptivity.o\
+ hal/phydm/phydm_cfotracking.o\
+ hal/phydm/phydm_noisemonitor.o\
+ hal/phydm/phydm_beamforming.o\
+ hal/phydm/phydm_dfs.o\
+ hal/phydm/txbf/halcomtxbf.o\
+ hal/phydm/txbf/haltxbfinterface.o\
+ hal/phydm/txbf/phydm_hal_txbf_api.o\
+ hal/phydm/phydm_adc_sampling.o\
+ hal/phydm/phydm_ccx.o\
+ hal/phydm/phydm_psd.o\
+ hal/phydm/phydm_primary_cca.o\
+ hal/phydm/phydm_cck_pd.o\
+ hal/phydm/phydm_rssi_monitor.o\
+ hal/phydm/phydm_auto_dbg.o\
+ hal/phydm/phydm_math_lib.o\
+ hal/phydm/phydm_api.o\
+ hal/phydm/phydm_pow_train.o\
+ hal/phydm/halrf/halrf.o\
+ hal/phydm/halrf/halphyrf_ce.o\
+ hal/phydm/halrf/halrf_powertracking_ce.o\
+ hal/phydm/halrf/halrf_powertracking.o\
+ hal/phydm/halrf/halrf_kfree.o
+
+ifeq ($(CONFIG_RTL8188E), y)
+RTL871X = rtl8188e
+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8188e_mac.o\
+ hal/phydm/$(RTL871X)/halhwimg8188e_bb.o\
+ hal/phydm/$(RTL871X)/halhwimg8188e_rf.o\
+ hal/phydm/halrf/$(RTL871X)/halrf_8188e_ce.o\
+ hal/phydm/$(RTL871X)/phydm_regconfig8188e.o\
+ hal/phydm/$(RTL871X)/hal8188erateadaptive.o\
+ hal/phydm/$(RTL871X)/phydm_rtl8188e.o
+endif
+
+ifeq ($(CONFIG_RTL8192E), y)
+RTL871X = rtl8192e
+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8192e_mac.o\
+ hal/phydm/$(RTL871X)/halhwimg8192e_bb.o\
+ hal/phydm/$(RTL871X)/halhwimg8192e_rf.o\
+ hal/phydm/halrf/$(RTL871X)/halrf_8192e_ce.o\
+ hal/phydm/$(RTL871X)/phydm_regconfig8192e.o\
+ hal/phydm/$(RTL871X)/phydm_rtl8192e.o
+endif
+
+
+ifeq ($(CONFIG_RTL8812A), y)
+RTL871X = rtl8812a
+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8812a_mac.o\
+ hal/phydm/$(RTL871X)/halhwimg8812a_bb.o\
+ hal/phydm/$(RTL871X)/halhwimg8812a_rf.o\
+ hal/phydm/halrf/$(RTL871X)/halrf_8812a_ce.o\
+ hal/phydm/$(RTL871X)/phydm_regconfig8812a.o\
+ hal/phydm/$(RTL871X)/phydm_rtl8812a.o\
+ hal/phydm/txbf/haltxbfjaguar.o
+endif
+
+ifeq ($(CONFIG_RTL8821A), y)
+RTL871X = rtl8821a
+_PHYDM_FILES += hal/phydm/rtl8821a/halhwimg8821a_mac.o\
+ hal/phydm/rtl8821a/halhwimg8821a_bb.o\
+ hal/phydm/rtl8821a/halhwimg8821a_rf.o\
+ hal/phydm/halrf/rtl8812a/halrf_8812a_ce.o\
+ hal/phydm/halrf/rtl8821a/halrf_8821a_ce.o\
+ hal/phydm/rtl8821a/phydm_regconfig8821a.o\
+ hal/phydm/rtl8821a/phydm_rtl8821a.o\
+ hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ce.o\
+ hal/phydm/txbf/haltxbfjaguar.o
+endif
+
+
+ifeq ($(CONFIG_RTL8723B), y)
+RTL871X = rtl8723b
+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723b_bb.o\
+ hal/phydm/$(RTL871X)/halhwimg8723b_mac.o\
+ hal/phydm/$(RTL871X)/halhwimg8723b_rf.o\
+ hal/phydm/$(RTL871X)/halhwimg8723b_mp.o\
+ hal/phydm/$(RTL871X)/phydm_regconfig8723b.o\
+ hal/phydm/halrf/$(RTL871X)/halrf_8723b_ce.o\
+ hal/phydm/$(RTL871X)/phydm_rtl8723b.o
+endif
+
+
+ifeq ($(CONFIG_RTL8814A), y)
+RTL871X = rtl8814a
+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8814a_bb.o\
+ hal/phydm/$(RTL871X)/halhwimg8814a_mac.o\
+ hal/phydm/$(RTL871X)/halhwimg8814a_rf.o\
+ hal/phydm/halrf/$(RTL871X)/halrf_iqk_8814a.o\
+ hal/phydm/$(RTL871X)/phydm_regconfig8814a.o\
+ hal/phydm/halrf/$(RTL871X)/halrf_8814a_ce.o\
+ hal/phydm/$(RTL871X)/phydm_rtl8814a.o\
+ hal/phydm/txbf/haltxbf8814a.o
+endif
+
+
+ifeq ($(CONFIG_RTL8723C), y)
+RTL871X = rtl8703b
+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8703b_bb.o\
+ hal/phydm/$(RTL871X)/halhwimg8703b_mac.o\
+ hal/phydm/$(RTL871X)/halhwimg8703b_rf.o\
+ hal/phydm/$(RTL871X)/phydm_regconfig8703b.o\
+ hal/phydm/halrf/$(RTL871X)/halrf_8703b.o
+endif
+
+ifeq ($(CONFIG_RTL8723D), y)
+RTL871X = rtl8723d
+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723d_bb.o\
+ hal/phydm/$(RTL871X)/halhwimg8723d_mac.o\
+ hal/phydm/$(RTL871X)/halhwimg8723d_rf.o\
+ hal/phydm/$(RTL871X)/phydm_regconfig8723d.o\
+ hal/phydm/$(RTL871X)/phydm_rtl8723d.o\
+ hal/phydm/halrf/$(RTL871X)/halrf_8723d.o
+endif
+
+
+ifeq ($(CONFIG_RTL8188F), y)
+RTL871X = rtl8188f
+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8188f_bb.o\
+ hal/phydm/$(RTL871X)/halhwimg8188f_mac.o\
+ hal/phydm/$(RTL871X)/halhwimg8188f_rf.o\
+ hal/phydm/$(RTL871X)/phydm_regconfig8188f.o\
+ hal/phydm/halrf/$(RTL871X)/halrf_8188f.o \
+ hal/phydm/$(RTL871X)/phydm_rtl8188f.o
+endif
+
+ifeq ($(CONFIG_RTL8822B), y)
+RTL871X = rtl8822b
+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8822b_bb.o \
+ hal/phydm/$(RTL871X)/halhwimg8822b_mac.o \
+ hal/phydm/$(RTL871X)/halhwimg8822b_rf.o \
+ hal/phydm/halrf/$(RTL871X)/halrf_8822b.o \
+ hal/phydm/$(RTL871X)/phydm_hal_api8822b.o \
+ hal/phydm/halrf/$(RTL871X)/halrf_iqk_8822b.o \
+ hal/phydm/$(RTL871X)/phydm_regconfig8822b.o \
+ hal/phydm/$(RTL871X)/phydm_rtl8822b.o
+
+_PHYDM_FILES += hal/phydm/txbf/haltxbf8822b.o
+endif
+
+
+ifeq ($(CONFIG_RTL8821C), y)
+RTL871X = rtl8821c
+_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8821c_bb.o \
+ hal/phydm/$(RTL871X)/halhwimg8821c_mac.o \
+ hal/phydm/$(RTL871X)/halhwimg8821c_rf.o \
+ hal/phydm/$(RTL871X)/phydm_hal_api8821c.o \
+ hal/phydm/$(RTL871X)/phydm_regconfig8821c.o\
+ hal/phydm/halrf/$(RTL871X)/halrf_8821c.o\
+ hal/phydm/halrf/$(RTL871X)/halrf_iqk_8821c.o
+endif
\ No newline at end of file
diff --git a/hal/phydm/phydm_acs.c b/hal/phydm/phydm_acs.c
index 021702c..de49bb3 100644
--- a/hal/phydm/phydm_acs.c
+++ b/hal/phydm/phydm_acs.c
@@ -1,498 +1,461 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
- *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
*
+ * Larry Finger
*
- ******************************************************************************/
+ *****************************************************************************/
-//============================================================
-// include files
-//============================================================
+/* ************************************************************
+ * include files
+ * ************************************************************ */
#include "mp_precomp.h"
#include "phydm_precomp.h"
-u1Byte
-ODM_GetAutoChannelSelectResult(
- IN PVOID pDM_VOID,
- IN u1Byte Band
+u8
+odm_get_auto_channel_select_result(
+ void *dm_void,
+ u8 band
)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- PACS pACS = &pDM_Odm->DM_ACS;
-
-#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
- if(Band == ODM_BAND_2_4G)
- {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("[ACS] ODM_GetAutoChannelSelectResult(): CleanChannel_2G(%d)\n", pACS->CleanChannel_2G));
- return (u1Byte)pACS->CleanChannel_2G;
- }
- else
- {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("[ACS] ODM_GetAutoChannelSelectResult(): CleanChannel_5G(%d)\n", pACS->CleanChannel_5G));
- return (u1Byte)pACS->CleanChannel_5G;
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct acs_info *acs = &dm->dm_acs;
+
+ PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__);
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+ if (band == ODM_BAND_2_4G) {
+ PHYDM_DBG(dm, ODM_COMP_API, "clean_CH_2g=%d\n", acs->clean_channel_2g);
+ return (u8)acs->clean_channel_2g;
+ } else {
+ PHYDM_DBG(dm, ODM_COMP_API, "clean_CH_5g=%d\n", acs->clean_channel_5g);
+ return (u8)acs->clean_channel_5g;
}
#else
- return (u1Byte)pACS->CleanChannel_2G;
+ return (u8)acs->clean_channel_2g;
#endif
}
-VOID
-odm_AutoChannelSelectSetting(
- IN PVOID pDM_VOID,
- IN BOOLEAN IsEnable
-)
-{
-#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- u2Byte period = 0x2710;// 40ms in default
- u2Byte NHMType = 0x7;
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelectSetting()=========> \n"));
-
- if(IsEnable)
- {//20 ms
- period = 0x1388;
- NHMType = 0x1;
- }
-
- if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
- {
- //PHY parameters initialize for ac series
- ODM_Write2Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11AC+2, period); //0x990[31:16]=0x2710 Time duration for NHM unit: 4us, 0x2710=40ms
- //ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT8|BIT9|BIT10, NHMType); //0x994[9:8]=3 enable CCX
- }
- else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
- {
- //PHY parameters initialize for n series
- ODM_Write2Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11N+2, period); //0x894[31:16]=0x2710 Time duration for NHM unit: 4us, 0x2710=40ms
- //ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, NHMType); //0x890[9:8]=3 enable CCX
- }
-#endif
-}
-
-VOID
-odm_AutoChannelSelectInit(
- IN PVOID pDM_VOID
+void
+odm_auto_channel_select_init(
+ void *dm_void
)
{
-#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- PACS pACS = &pDM_Odm->DM_ACS;
- u1Byte i;
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct acs_info *acs = &dm->dm_acs;
+ u8 i;
- if(!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT))
+ if (!(dm->support_ability & ODM_BB_ENV_MONITOR))
return;
- if(pACS->bForceACSResult)
+ if (acs->is_force_acs_result)
return;
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelectInit()=========> \n"));
+ PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__);
- pACS->CleanChannel_2G = 1;
- pACS->CleanChannel_5G = 36;
+ acs->clean_channel_2g = 1;
+ acs->clean_channel_5g = 36;
- for (i = 0; i < ODM_MAX_CHANNEL_2G; ++i)
- {
- pACS->Channel_Info_2G[0][i] = 0;
- pACS->Channel_Info_2G[1][i] = 0;
+ for (i = 0; i < ODM_MAX_CHANNEL_2G; ++i) {
+ acs->channel_info_2g[0][i] = 0;
+ acs->channel_info_2g[1][i] = 0;
}
- if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
- {
- for (i = 0; i < ODM_MAX_CHANNEL_5G; ++i)
- {
- pACS->Channel_Info_5G[0][i] = 0;
- pACS->Channel_Info_5G[1][i] = 0;
+ if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+ for (i = 0; i < ODM_MAX_CHANNEL_5G; ++i) {
+ acs->channel_info_5g[0][i] = 0;
+ acs->channel_info_5g[1][i] = 0;
}
}
#endif
}
-VOID
-odm_AutoChannelSelectReset(
- IN PVOID pDM_VOID
+void
+odm_auto_channel_select_reset(
+ void *dm_void
)
{
-#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- PACS pACS = &pDM_Odm->DM_ACS;
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct acs_info *acs = &dm->dm_acs;
+ struct ccx_info *ccx_info = &dm->dm_ccx_info;
- if(!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT))
+ if (!(dm->support_ability & ODM_BB_ENV_MONITOR))
return;
- if(pACS->bForceACSResult)
+ if (acs->is_force_acs_result)
return;
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelectReset()=========> \n"));
+ PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__);
- odm_AutoChannelSelectSetting(pDM_Odm,TRUE);// for 20ms measurement
- Phydm_NHMCounterStatisticsReset(pDM_Odm);
+ ccx_info->nhm_period = 0x1388; /*20ms*/
+ phydm_nhm_setting(dm, SET_NHM_SETTING);
+ phydm_nhm_trigger(dm);
#endif
}
-VOID
-odm_AutoChannelSelect(
- IN PVOID pDM_VOID,
- IN u1Byte Channel
+void
+odm_auto_channel_select(
+ void *dm_void,
+ u8 channel
)
{
-#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- PACS pACS = &pDM_Odm->DM_ACS;
- u1Byte ChannelIDX = 0, SearchIDX = 0;
- u2Byte MaxScore=0;
-
- if(!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT))
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): Return: SupportAbility ODM_BB_NHM_CNT is disabled\n"));
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct acs_info *acs = &dm->dm_acs;
+ struct ccx_info *ccx_info = &dm->dm_ccx_info;
+ u8 channel_idx = 0, search_idx = 0;
+ u8 noisy_nhm_th = 0x52;
+ u8 i, noisy_nhm_th_index, low_pwr_cnt = 0;
+ u16 max_score = 0;
+
+ PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__);
+
+ if (!(dm->support_ability & ODM_BB_ENV_MONITOR)) {
+ PHYDM_DBG(dm, DBG_DIG, "Return: Not support\n");
return;
}
- if(pACS->bForceACSResult)
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): Force 2G clean channel = %d, 5G clean channel = %d\n",
- pACS->CleanChannel_2G, pACS->CleanChannel_5G));
+ if (acs->is_force_acs_result) {
+ PHYDM_DBG(dm, DBG_DIG, "Force clean CH{2G,5G}={%d,%d}\n",
+ acs->clean_channel_2g, acs->clean_channel_5g);
return;
}
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): Channel = %d=========> \n", Channel));
+ PHYDM_DBG(dm, ODM_COMP_API, "CH=%d\n", channel);
- Phydm_GetNHMCounterStatistics(pDM_Odm);
- odm_AutoChannelSelectSetting(pDM_Odm,FALSE);
+ phydm_get_nhm_result(dm);
+ noisy_nhm_th_index = (noisy_nhm_th - ccx_info->nhm_th[0]) << 2;
- if(Channel >=1 && Channel <=14)
- {
- ChannelIDX = Channel - 1;
- pACS->Channel_Info_2G[1][ChannelIDX]++;
-
- if(pACS->Channel_Info_2G[1][ChannelIDX] >= 2)
- pACS->Channel_Info_2G[0][ChannelIDX] = (pACS->Channel_Info_2G[0][ChannelIDX] >> 1) +
- (pACS->Channel_Info_2G[0][ChannelIDX] >> 2) + (pDM_Odm->NHM_cnt_0>>2);
+ for (i = 0; i <= 11; i++) {
+ if (i <= noisy_nhm_th_index)
+ low_pwr_cnt += ccx_info->nhm_result[i];
+ }
+
+ ccx_info->nhm_period = 0x2710;
+ phydm_nhm_setting(dm, SET_NHM_SETTING);
+
+ if (channel >= 1 && channel <= 14) {
+ channel_idx = channel - 1;
+ acs->channel_info_2g[1][channel_idx]++;
+
+ if (acs->channel_info_2g[1][channel_idx] >= 2)
+ acs->channel_info_2g[0][channel_idx] = (acs->channel_info_2g[0][channel_idx] >> 1) +
+ (acs->channel_info_2g[0][channel_idx] >> 2) + (low_pwr_cnt >> 2);
else
- pACS->Channel_Info_2G[0][ChannelIDX] = pDM_Odm->NHM_cnt_0;
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): NHM_cnt_0 = %d \n", pDM_Odm->NHM_cnt_0));
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): Channel_Info[0][%d] = %d, Channel_Info[1][%d] = %d\n", ChannelIDX, pACS->Channel_Info_2G[0][ChannelIDX], ChannelIDX, pACS->Channel_Info_2G[1][ChannelIDX]));
+ acs->channel_info_2g[0][channel_idx] = low_pwr_cnt;
- for(SearchIDX = 0; SearchIDX < ODM_MAX_CHANNEL_2G; SearchIDX++)
- {
- if(pACS->Channel_Info_2G[1][SearchIDX] != 0)
- {
- if(pACS->Channel_Info_2G[0][SearchIDX] >= MaxScore)
- {
- MaxScore = pACS->Channel_Info_2G[0][SearchIDX];
- pACS->CleanChannel_2G = SearchIDX+1;
- }
+ PHYDM_DBG(dm, ODM_COMP_API, "low_pwr_cnt = %d\n", low_pwr_cnt);
+ PHYDM_DBG(dm, ODM_COMP_API, "CH_Info[0][%d]=%d, CH_Info[1][%d]=%d\n", channel_idx, acs->channel_info_2g[0][channel_idx], channel_idx, acs->channel_info_2g[1][channel_idx]);
+
+ for (search_idx = 0; search_idx < ODM_MAX_CHANNEL_2G; search_idx++) {
+ if (acs->channel_info_2g[1][search_idx] != 0 && acs->channel_info_2g[0][search_idx] >= max_score) {
+ max_score = acs->channel_info_2g[0][search_idx];
+ acs->clean_channel_2g = search_idx + 1;
}
}
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("(1)odm_AutoChannelSelect(): 2G: CleanChannel_2G = %d, MaxScore = %d \n",
- pACS->CleanChannel_2G, MaxScore));
+ PHYDM_DBG(dm, ODM_COMP_API, "clean_CH_2g=%d, max_score=%d\n",
+ acs->clean_channel_2g, max_score);
+ } else if (channel >= 36) {
+ /* Need to do */
+ acs->clean_channel_5g = channel;
}
- else if(Channel >= 36)
- {
- // Need to do
- pACS->CleanChannel_5G = Channel;
- }
#endif
}
-#if ( DM_ODM_SUPPORT_TYPE & ODM_AP )
+boolean
+phydm_acs_check(
+ void *dm_void
+)
+{
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct rtl8192cd_priv *priv = dm->priv;
+
+ if ((priv->auto_channel != 0) && (priv->auto_channel != 2)) /* if struct acs_info running, do not do FA/CCA counter read */
+ return true;
+ else
+ return false;
+#else
+ return false;
+#endif
+}
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
-VOID
-phydm_AutoChannelSelectSettingAP(
- IN PVOID pDM_VOID,
- IN u4Byte setting, // 0: STORE_DEFAULT_NHM_SETTING; 1: RESTORE_DEFAULT_NHM_SETTING, 2: ACS_NHM_SETTING
- IN u4Byte acs_step
+void
+phydm_auto_channel_select_setting_ap(
+ void *dm_void,
+ u32 setting, /* 0: STORE_DEFAULT_NHM_SETTING; 1: RESTORE_DEFAULT_NHM_SETTING, 2: ACS_NHM_SETTING */
+ u32 acs_step
)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- prtl8192cd_priv priv = pDM_Odm->priv;
- PACS pACS = &pDM_Odm->DM_ACS;
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelectSettingAP()=========> \n"));
-
- //3 Store Default Setting
- if(setting == STORE_DEFAULT_NHM_SETTING)
- {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("STORE_DEFAULT_NHM_SETTING\n"));
-
- if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) // store Reg0x990, Reg0x994, Reg0x998, Reg0x99C, Reg0x9a0
- {
- pACS->Reg0x990 = ODM_Read4Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11AC); // Reg0x990
- pACS->Reg0x994 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC); // Reg0x994
- pACS->Reg0x998 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC); // Reg0x998
- pACS->Reg0x99C = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC); // Reg0x99c
- pACS->Reg0x9A0 = ODM_Read1Byte(pDM_Odm, ODM_REG_NHM_TH8_11AC); // Reg0x9a0, u1Byte
- }
- else if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
- {
- pACS->Reg0x890 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N); // Reg0x890
- pACS->Reg0x894 = ODM_Read4Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11N); // Reg0x894
- pACS->Reg0x898 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N); // Reg0x898
- pACS->Reg0x89C = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N); // Reg0x89c
- pACS->Reg0xE28 = ODM_Read1Byte(pDM_Odm, ODM_REG_NHM_TH8_11N); // Reg0xe28, u1Byte
- }
- }
-
- //3 Restore Default Setting
- else if(setting == RESTORE_DEFAULT_NHM_SETTING)
- {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("RESTORE_DEFAULT_NHM_SETTING\n"));
-
- if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) // store Reg0x990, Reg0x994, Reg0x998, Reg0x99C, Reg0x9a0
- {
- ODM_Write4Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11AC, pACS->Reg0x990);
- ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, pACS->Reg0x994);
- ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, pACS->Reg0x998);
- ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, pACS->Reg0x99C);
- ODM_Write1Byte(pDM_Odm, ODM_REG_NHM_TH8_11AC, pACS->Reg0x9A0);
- }
- else if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
- {
- ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, pACS->Reg0x890);
- ODM_Write4Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11AC, pACS->Reg0x894);
- ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, pACS->Reg0x898);
- ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, pACS->Reg0x89C);
- ODM_Write1Byte(pDM_Odm, ODM_REG_NHM_TH8_11N, pACS->Reg0xE28);
- }
- }
-
- //3 ACS Setting
- else if(setting == ACS_NHM_SETTING)
- {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("ACS_NHM_SETTING\n"));
- u2Byte period;
- period = 0x61a8;
- pACS->ACS_Step = acs_step;
-
- if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
- {
- //4 Set NHM period, 0x990[31:16]=0x61a8, Time duration for NHM unit: 4us, 0x61a8=100ms
- ODM_Write2Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11AC+2, period);
- //4 Set NHM ignore_cca=1, ignore_txon=1, ccx_en=0
- ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC,BIT8|BIT9|BIT10, 3);
-
- if(pACS->ACS_Step == 0)
- {
- //4 Set IGI
- ODM_SetBBReg(pDM_Odm,0xc50,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x3E);
- if (get_rf_mimo_mode(priv) != MIMO_1T1R)
- ODM_SetBBReg(pDM_Odm,0xe50,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x3E);
-
- //4 Set ACS NHM threshold
- ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0x82786e64);
- ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffff8c);
- ODM_Write1Byte(pDM_Odm, ODM_REG_NHM_TH8_11AC, 0xff);
- ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC+2, 0xffff);
-
- }
- else if(pACS->ACS_Step == 1)
- {
- //4 Set IGI
- ODM_SetBBReg(pDM_Odm,0xc50,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x2A);
- if (get_rf_mimo_mode(priv) != MIMO_1T1R)
- ODM_SetBBReg(pDM_Odm,0xe50,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x2A);
-
- //4 Set ACS NHM threshold
- ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0x5a50463c);
- ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffff64);
-
- }
-
- }
- else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
- {
- //4 Set NHM period, 0x894[31:16]=0x61a8, Time duration for NHM unit: 4us, 0x61a8=100ms
- ODM_Write2Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11AC+2, period);
- //4 Set NHM ignore_cca=1, ignore_txon=1, ccx_en=0
- ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N,BIT8|BIT9|BIT10, 3);
-
- if(pACS->ACS_Step == 0)
- {
- //4 Set IGI
- ODM_SetBBReg(pDM_Odm,0xc50,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x3E);
- if (get_rf_mimo_mode(priv) != MIMO_1T1R)
- ODM_SetBBReg(pDM_Odm,0xc58,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x3E);
-
- //4 Set ACS NHM threshold
- ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0x82786e64);
- ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffff8c);
- ODM_Write1Byte(pDM_Odm, ODM_REG_NHM_TH8_11N, 0xff);
- ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N+2, 0xffff);
-
- }
- else if(pACS->ACS_Step == 1)
- {
- //4 Set IGI
- ODM_SetBBReg(pDM_Odm,0xc50,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x2A);
- if (get_rf_mimo_mode(priv) != MIMO_1T1R)
- ODM_SetBBReg(pDM_Odm,0xc58,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x2A);
-
- //4 Set ACS NHM threshold
- ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0x5a50463c);
- ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffff64);
-
- }
- }
- }
-
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct rtl8192cd_priv *priv = dm->priv;
+ struct acs_info *acs = &dm->dm_acs;
+
+ PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__);
+
+ /* 3 Store Default setting */
+ if (setting == STORE_DEFAULT_NHM_SETTING) {
+ PHYDM_DBG(dm, ODM_COMP_API, "STORE_DEFAULT_NHM_SETTING\n");
+
+ if (dm->support_ic_type & ODM_IC_11AC_SERIES) { /* store reg0x990, reg0x994, reg0x998, reg0x99c, Reg0x9a0 */
+ acs->reg0x990 = odm_read_4byte(dm, ODM_REG_CCX_PERIOD_11AC); /* reg0x990 */
+ acs->reg0x994 = odm_read_4byte(dm, ODM_REG_NHM_TH9_TH10_11AC); /* reg0x994 */
+ acs->reg0x998 = odm_read_4byte(dm, ODM_REG_NHM_TH3_TO_TH0_11AC); /* reg0x998 */
+ acs->reg0x99c = odm_read_4byte(dm, ODM_REG_NHM_TH7_TO_TH4_11AC); /* Reg0x99c */
+ acs->reg0x9a0 = odm_read_1byte(dm, ODM_REG_NHM_TH8_11AC); /* Reg0x9a0, u8 */
+ } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
+ acs->reg0x890 = odm_read_4byte(dm, ODM_REG_NHM_TH9_TH10_11N); /* reg0x890 */
+ acs->reg0x894 = odm_read_4byte(dm, ODM_REG_CCX_PERIOD_11N); /* reg0x894 */
+ acs->reg0x898 = odm_read_4byte(dm, ODM_REG_NHM_TH3_TO_TH0_11N); /* reg0x898 */
+ acs->reg0x89c = odm_read_4byte(dm, ODM_REG_NHM_TH7_TO_TH4_11N); /* Reg0x89c */
+ acs->reg0xe28 = odm_read_1byte(dm, ODM_REG_NHM_TH8_11N); /* Reg0xe28, u8 */
+ }
+ }
+
+ /* 3 Restore Default setting */
+ else if (setting == RESTORE_DEFAULT_NHM_SETTING) {
+ PHYDM_DBG(dm, ODM_COMP_API, "RESTORE_DEFAULT_NHM_SETTING\n");
+
+ if (dm->support_ic_type & ODM_IC_11AC_SERIES) { /* store reg0x990, reg0x994, reg0x998, reg0x99c, Reg0x9a0 */
+ odm_write_4byte(dm, ODM_REG_CCX_PERIOD_11AC, acs->reg0x990);
+ odm_write_4byte(dm, ODM_REG_NHM_TH9_TH10_11AC, acs->reg0x994);
+ odm_write_4byte(dm, ODM_REG_NHM_TH3_TO_TH0_11AC, acs->reg0x998);
+ odm_write_4byte(dm, ODM_REG_NHM_TH7_TO_TH4_11AC, acs->reg0x99c);
+ odm_write_1byte(dm, ODM_REG_NHM_TH8_11AC, acs->reg0x9a0);
+ } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
+ odm_write_4byte(dm, ODM_REG_NHM_TH9_TH10_11N, acs->reg0x890);
+ odm_write_4byte(dm, ODM_REG_CCX_PERIOD_11AC, acs->reg0x894);
+ odm_write_4byte(dm, ODM_REG_NHM_TH3_TO_TH0_11N, acs->reg0x898);
+ odm_write_4byte(dm, ODM_REG_NHM_TH7_TO_TH4_11N, acs->reg0x89c);
+ odm_write_1byte(dm, ODM_REG_NHM_TH8_11N, acs->reg0xe28);
+ }
+ }
+
+ /* 3 struct acs_info setting */
+ else if (setting == ACS_NHM_SETTING) {
+ PHYDM_DBG(dm, ODM_COMP_API, "ACS_NHM_SETTING\n");
+ u16 period;
+ period = 0x61a8;
+ acs->acs_step = acs_step;
+
+ if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+ /* 4 Set NHM period, 0x990[31:16]=0x61a8, Time duration for NHM unit: 4us, 0x61a8=100ms */
+ odm_write_2byte(dm, ODM_REG_CCX_PERIOD_11AC + 2, period);
+ /* 4 Set NHM ignore_cca=1, ignore_txon=1, ccx_en=0 */
+ odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(8) | BIT(9) | BIT(10), 3);
+
+ if (acs->acs_step == 0) {
+ /* 4 Set IGI */
+ odm_set_bb_reg(dm, 0xc50, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x3E);
+ if (get_rf_mimo_mode(priv) != RF_1T1R)
+ odm_set_bb_reg(dm, 0xe50, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x3E);
+
+ /* 4 Set struct acs_info NHM threshold */
+ odm_write_4byte(dm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0x82786e64);
+ odm_write_4byte(dm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffff8c);
+ odm_write_1byte(dm, ODM_REG_NHM_TH8_11AC, 0xff);
+ odm_write_2byte(dm, ODM_REG_NHM_TH9_TH10_11AC + 2, 0xffff);
+
+ } else if (acs->acs_step == 1) {
+ /* 4 Set IGI */
+ odm_set_bb_reg(dm, 0xc50, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x2A);
+ if (get_rf_mimo_mode(priv) != RF_1T1R)
+ odm_set_bb_reg(dm, 0xe50, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x2A);
+
+ /* 4 Set struct acs_info NHM threshold */
+ odm_write_4byte(dm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0x5a50463c);
+ odm_write_4byte(dm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffff64);
+
+ }
+
+ } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
+ /* 4 Set NHM period, 0x894[31:16]=0x61a8, Time duration for NHM unit: 4us, 0x61a8=100ms */
+ odm_write_2byte(dm, ODM_REG_CCX_PERIOD_11AC + 2, period);
+ /* 4 Set NHM ignore_cca=1, ignore_txon=1, ccx_en=0 */
+ odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(8) | BIT(9) | BIT(10), 3);
+
+ if (acs->acs_step == 0) {
+ /* 4 Set IGI */
+ odm_set_bb_reg(dm, 0xc50, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x3E);
+ if (get_rf_mimo_mode(priv) != RF_1T1R)
+ odm_set_bb_reg(dm, 0xc58, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x3E);
+
+ /* 4 Set struct acs_info NHM threshold */
+ odm_write_4byte(dm, ODM_REG_NHM_TH3_TO_TH0_11N, 0x82786e64);
+ odm_write_4byte(dm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffff8c);
+ odm_write_1byte(dm, ODM_REG_NHM_TH8_11N, 0xff);
+ odm_write_2byte(dm, ODM_REG_NHM_TH9_TH10_11N + 2, 0xffff);
+
+ } else if (acs->acs_step == 1) {
+ /* 4 Set IGI */
+ odm_set_bb_reg(dm, 0xc50, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x2A);
+ if (get_rf_mimo_mode(priv) != RF_1T1R)
+ odm_set_bb_reg(dm, 0xc58, BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6), 0x2A);
+
+ /* 4 Set struct acs_info NHM threshold */
+ odm_write_4byte(dm, ODM_REG_NHM_TH3_TO_TH0_11N, 0x5a50463c);
+ odm_write_4byte(dm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffff64);
+
+ }
+ }
+ }
+
}
-VOID
-phydm_GetNHMStatisticsAP(
- IN PVOID pDM_VOID,
- IN u4Byte idx, // @ 2G, Real channel number = idx+1
- IN u4Byte acs_step
+void
+phydm_get_nhm_statistics_ap(
+ void *dm_void,
+ u32 idx, /* @ 2G, Real channel number = idx+1 */
+ u32 acs_step
)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- prtl8192cd_priv priv = pDM_Odm->priv;
- PACS pACS = &pDM_Odm->DM_ACS;
- u4Byte value32 = 0;
- u1Byte i;
-
- pACS->ACS_Step = acs_step;
-
- if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
- {
- //4 Check if NHM result is ready
- for (i=0; i<20; i++) {
-
- ODM_delay_ms(1);
- if ( ODM_GetBBReg(pDM_Odm,rFPGA0_PSDReport,BIT17) )
- break;
- }
-
- //4 Get NHM Statistics
- if ( pACS->ACS_Step==1 ) {
-
- value32 = ODM_Read4Byte(pDM_Odm,ODM_REG_NHM_CNT7_TO_CNT4_11N);
-
- pACS->NHM_Cnt[idx][9] = (value32 & bMaskByte1) >> 8;
- pACS->NHM_Cnt[idx][8] = (value32 & bMaskByte0);
-
- value32 = ODM_Read4Byte(pDM_Odm,ODM_REG_NHM_CNT_11N); // ODM_REG_NHM_CNT3_TO_CNT0_11N
-
- pACS->NHM_Cnt[idx][7] = (value32 & bMaskByte3) >> 24;
- pACS->NHM_Cnt[idx][6] = (value32 & bMaskByte2) >> 16;
- pACS->NHM_Cnt[idx][5] = (value32 & bMaskByte1) >> 8;
-
- } else if (pACS->ACS_Step==2) {
-
- value32 = ODM_Read4Byte(pDM_Odm,ODM_REG_NHM_CNT_11N); // ODM_REG_NHM_CNT3_TO_CNT0_11N
-
- pACS->NHM_Cnt[idx][4] = ODM_Read1Byte(pDM_Odm, ODM_REG_NHM_CNT7_TO_CNT4_11N);
- pACS->NHM_Cnt[idx][3] = (value32 & bMaskByte3) >> 24;
- pACS->NHM_Cnt[idx][2] = (value32 & bMaskByte2) >> 16;
- pACS->NHM_Cnt[idx][1] = (value32 & bMaskByte1) >> 8;
- pACS->NHM_Cnt[idx][0] = (value32 & bMaskByte0);
- }
- }
- else if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
- {
- //4 Check if NHM result is ready
- for (i=0; i<20; i++) {
-
- ODM_delay_ms(1);
- if (ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_DUR_READY_11AC, BIT16))
- break;
- }
-
- if ( pACS->ACS_Step==1 ) {
-
- value32 = ODM_Read4Byte(pDM_Odm,ODM_REG_NHM_CNT7_TO_CNT4_11AC);
-
- pACS->NHM_Cnt[idx][9] = (value32 & bMaskByte1) >> 8;
- pACS->NHM_Cnt[idx][8] = (value32 & bMaskByte0);
-
- value32 = ODM_Read4Byte(pDM_Odm,ODM_REG_NHM_CNT_11AC); // ODM_REG_NHM_CNT3_TO_CNT0_11AC
-
- pACS->NHM_Cnt[idx][7] = (value32 & bMaskByte3) >> 24;
- pACS->NHM_Cnt[idx][6] = (value32 & bMaskByte2) >> 16;
- pACS->NHM_Cnt[idx][5] = (value32 & bMaskByte1) >> 8;
-
- } else if (pACS->ACS_Step==2) {
-
- value32 = ODM_Read4Byte(pDM_Odm,ODM_REG_NHM_CNT_11AC); // ODM_REG_NHM_CNT3_TO_CNT0_11AC
-
- pACS->NHM_Cnt[idx][4] = ODM_Read1Byte(pDM_Odm, ODM_REG_NHM_CNT7_TO_CNT4_11AC);
- pACS->NHM_Cnt[idx][3] = (value32 & bMaskByte3) >> 24;
- pACS->NHM_Cnt[idx][2] = (value32 & bMaskByte2) >> 16;
- pACS->NHM_Cnt[idx][1] = (value32 & bMaskByte1) >> 8;
- pACS->NHM_Cnt[idx][0] = (value32 & bMaskByte0);
- }
- }
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct rtl8192cd_priv *priv = dm->priv;
+ struct acs_info *acs = &dm->dm_acs;
+ u32 value32 = 0;
+ u8 i;
+
+ acs->acs_step = acs_step;
+
+ if (dm->support_ic_type & ODM_IC_11N_SERIES) {
+ /* 4 Check if NHM result is ready */
+ for (i = 0; i < 20; i++) {
+ ODM_delay_ms(1);
+ if (odm_get_bb_reg(dm, REG_FPGA0_PSD_REPORT, BIT(17)))
+ break;
+ }
+
+ /* 4 Get NHM Statistics */
+ if (acs->acs_step == 1) {
+ value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT7_TO_CNT4_11N);
+
+ acs->nhm_cnt[idx][9] = (value32 & MASKBYTE1) >> 8;
+ acs->nhm_cnt[idx][8] = (value32 & MASKBYTE0);
+
+ value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT_11N); /* ODM_REG_NHM_CNT3_TO_CNT0_11N */
+
+ acs->nhm_cnt[idx][7] = (value32 & MASKBYTE3) >> 24;
+ acs->nhm_cnt[idx][6] = (value32 & MASKBYTE2) >> 16;
+ acs->nhm_cnt[idx][5] = (value32 & MASKBYTE1) >> 8;
+
+ } else if (acs->acs_step == 2) {
+ value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT_11N); /* ODM_REG_NHM_CNT3_TO_CNT0_11N */
+
+ acs->nhm_cnt[idx][4] = odm_read_1byte(dm, ODM_REG_NHM_CNT7_TO_CNT4_11N);
+ acs->nhm_cnt[idx][3] = (value32 & MASKBYTE3) >> 24;
+ acs->nhm_cnt[idx][2] = (value32 & MASKBYTE2) >> 16;
+ acs->nhm_cnt[idx][1] = (value32 & MASKBYTE1) >> 8;
+ acs->nhm_cnt[idx][0] = (value32 & MASKBYTE0);
+ }
+ } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+ /* 4 Check if NHM result is ready */
+ for (i = 0; i < 20; i++) {
+ ODM_delay_ms(1);
+ if (odm_get_bb_reg(dm, ODM_REG_NHM_DUR_READY_11AC, BIT(16)))
+ break;
+ }
+
+ if (acs->acs_step == 1) {
+ value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT7_TO_CNT4_11AC);
+
+ acs->nhm_cnt[idx][9] = (value32 & MASKBYTE1) >> 8;
+ acs->nhm_cnt[idx][8] = (value32 & MASKBYTE0);
+
+ value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT_11AC); /* ODM_REG_NHM_CNT3_TO_CNT0_11AC */
+
+ acs->nhm_cnt[idx][7] = (value32 & MASKBYTE3) >> 24;
+ acs->nhm_cnt[idx][6] = (value32 & MASKBYTE2) >> 16;
+ acs->nhm_cnt[idx][5] = (value32 & MASKBYTE1) >> 8;
+
+ } else if (acs->acs_step == 2) {
+ value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT_11AC); /* ODM_REG_NHM_CNT3_TO_CNT0_11AC */
+
+ acs->nhm_cnt[idx][4] = odm_read_1byte(dm, ODM_REG_NHM_CNT7_TO_CNT4_11AC);
+ acs->nhm_cnt[idx][3] = (value32 & MASKBYTE3) >> 24;
+ acs->nhm_cnt[idx][2] = (value32 & MASKBYTE2) >> 16;
+ acs->nhm_cnt[idx][1] = (value32 & MASKBYTE1) >> 8;
+ acs->nhm_cnt[idx][0] = (value32 & MASKBYTE0);
+ }
+ }
}
-//#define ACS_DEBUG_INFO //acs debug default off
-/*
-int phydm_AutoChannelSelectAP(
- IN PVOID pDM_VOID,
- IN u4Byte ACS_Type, // 0: RXCount_Type, 1:NHM_Type
- IN u4Byte available_chnl_num // amount of all channels
- )
+/* #define ACS_DEBUG_INFO */ /* acs debug default off */
+#if 0
+int phydm_AutoChannelSelectAP(
+ void *dm_void,
+ u32 ACS_Type, /* 0: RXCount_Type, 1:NHM_Type */
+ u32 available_chnl_num /* amount of all channels */
+)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- PACS pACS = &pDM_Odm->DM_ACS;
- prtl8192cd_priv priv = pDM_Odm->priv;
-
- static u4Byte score2G[MAX_2G_CHANNEL_NUM], score5G[MAX_5G_CHANNEL_NUM];
- u4Byte score[MAX_BSS_NUM], use_nhm = 0;
- u4Byte minScore=0xffffffff;
- u4Byte tmpScore, tmpIdx=0;
- u4Byte traffic_check = 0;
- u4Byte fa_count_weighting = 1;
- int i, j, idx=0, idx_2G_end=-1, idx_5G_begin=-1, minChan=0;
- struct bss_desc *pBss=NULL;
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct acs_info *acs = &dm->dm_acs;
+ struct rtl8192cd_priv *priv = dm->priv;
+
+ static u32 score2G[MAX_2G_CHANNEL_NUM], score5G[MAX_5G_CHANNEL_NUM];
+ u32 score[MAX_BSS_NUM], use_nhm = 0;
+ u32 minScore = 0xffffffff;
+ u32 tmpScore, tmpIdx = 0;
+ u32 traffic_check = 0;
+ u32 fa_count_weighting = 1;
+ int i, j, idx = 0, idx_2G_end = -1, idx_5G_begin = -1, minChan = 0;
+ struct bss_desc *pBss = NULL;
#ifdef _DEBUG_RTL8192CD_
char tmpbuf[400];
- int len=0;
+ int len = 0;
#endif
memset(score2G, '\0', sizeof(score2G));
memset(score5G, '\0', sizeof(score5G));
- for (i=0; iavailable_chnl_num; i++) {
+ for (i = 0; i < priv->available_chnl_num; i++) {
if (priv->available_chnl[i] <= 14)
idx_2G_end = i;
else
break;
}
- for (i=0; iavailable_chnl_num; i++) {
+ for (i = 0; i < priv->available_chnl_num; i++) {
if (priv->available_chnl[i] > 14) {
idx_5G_begin = i;
break;
}
}
-// DELETE
+ /* DELETE */
#ifndef CONFIG_RTL_NEW_AUTOCH
- for (i=0; isite_survey->count; i++) {
+ for (i = 0; i < priv->site_survey->count; i++) {
pBss = &priv->site_survey->bss[i];
- for (idx=0; idxavailable_chnl_num; idx++) {
+ for (idx = 0; idx < priv->available_chnl_num; idx++) {
if (pBss->channel == priv->available_chnl[idx]) {
if (pBss->channel <= 14)
- setChannelScore(idx, score2G, 0, MAX_2G_CHANNEL_NUM-1);
+ setChannelScore(idx, score2G, 0, MAX_2G_CHANNEL_NUM - 1);
else
score5G[idx - idx_5G_begin] += 5;
break;
@@ -502,42 +465,41 @@ int phydm_AutoChannelSelectAP(
#endif
if (idx_2G_end >= 0)
- for (i=0; i<=idx_2G_end; i++)
+ for (i = 0; i <= idx_2G_end; i++)
score[i] = score2G[i];
if (idx_5G_begin >= 0)
- for (i=idx_5G_begin; iavailable_chnl_num; i++)
+ for (i = idx_5G_begin; i < priv->available_chnl_num; i++)
score[i] = score5G[i - idx_5G_begin];
-
+
#ifdef CONFIG_RTL_NEW_AUTOCH
{
- u4Byte y, ch_begin=0, ch_end= priv->available_chnl_num;
+ u32 y, ch_begin = 0, ch_end = priv->available_chnl_num;
+
+ u32 do_ap_check = 1, ap_ratio = 0;
- u4Byte do_ap_check = 1, ap_ratio = 0;
-
- if (idx_2G_end >= 0)
- ch_end = idx_2G_end+1;
- if (idx_5G_begin >= 0)
+ if (idx_2G_end >= 0)
+ ch_end = idx_2G_end + 1;
+ if (idx_5G_begin >= 0)
ch_begin = idx_5G_begin;
-#ifdef ACS_DEBUG_INFO//for debug
+#ifdef ACS_DEBUG_INFO/* for debug */
printk("\n");
- for (y=ch_begin; yavailable_chnl[y],
- priv->chnl_ss_mac_rx_count[y],
- priv->chnl_ss_mac_rx_count_40M[y],
- priv->chnl_ss_fa_count[y],
- score[y]);
+ priv->available_chnl[y],
+ priv->chnl_ss_mac_rx_count[y],
+ priv->chnl_ss_mac_rx_count_40M[y],
+ priv->chnl_ss_fa_count[y],
+ score[y]);
printk("\n");
#endif
#if defined(CONFIG_RTL_88E_SUPPORT) || defined(CONFIG_WLAN_HAL_8192EE)
- if( pDM_Odm->SupportICType&(ODM_RTL8188E|ODM_RTL8192E)&& priv->pmib->dot11RFEntry.acs_type )
- {
- u4Byte tmp_score[MAX_BSS_NUM];
+ if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8192E) && priv->pmib->dot11RFEntry.acs_type) {
+ u32 tmp_score[MAX_BSS_NUM];
memcpy(tmp_score, score, sizeof(score));
if (find_clean_channel(priv, ch_begin, ch_end, tmp_score)) {
- //memcpy(score, tmp_score, sizeof(score));
+ /* memcpy(score, tmp_score, sizeof(score)); */
#ifdef _DEBUG_RTL8192CD_
printk("!! Found clean channel, select minimum FA channel\n");
#endif
@@ -548,152 +510,151 @@ int phydm_AutoChannelSelectAP(
#endif
use_nhm = 1;
USE_CLN_CH:
- for (y=ch_begin; ynhm_cnt[y][i];
- for (j=0; jnhm_cnt[y][i];
+ for (j = 0; j < i; j++)
val32 *= 3;
score[y] += val32;
}
-#ifdef _DEBUG_RTL8192CD_
- printk("nhm_cnt_%d: H<-[ %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d]->L, score: %d\n",
- y+1, priv->nhm_cnt[y][9], priv->nhm_cnt[y][8], priv->nhm_cnt[y][7],
- priv->nhm_cnt[y][6], priv->nhm_cnt[y][5], priv->nhm_cnt[y][4],
- priv->nhm_cnt[y][3], priv->nhm_cnt[y][2], priv->nhm_cnt[y][1],
- priv->nhm_cnt[y][0], score[y]);
+#ifdef _DEBUG_RTL8192CD_
+ printk("nhm_cnt_%d: H<-[ %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d]->L, score: %d\n",
+ y + 1, priv->nhm_cnt[y][9], priv->nhm_cnt[y][8], priv->nhm_cnt[y][7],
+ priv->nhm_cnt[y][6], priv->nhm_cnt[y][5], priv->nhm_cnt[y][4],
+ priv->nhm_cnt[y][3], priv->nhm_cnt[y][2], priv->nhm_cnt[y][1],
+ priv->nhm_cnt[y][0], score[y]);
#endif
}
if (!use_nhm)
memcpy(score, tmp_score, sizeof(score));
-
+
goto choose_ch;
}
#endif
- // For each channel, weighting behind channels with MAC RX counter
- //For each channel, weighting the channel with FA counter
+ /* For each channel, weighting behind channels with MAC RX counter */
+ /* For each channel, weighting the channel with FA counter */
- for (y=ch_begin; ychnl_ss_mac_rx_count[y];
if (priv->chnl_ss_mac_rx_count[y] > 30)
do_ap_check = 0;
- if( priv->chnl_ss_mac_rx_count[y] > MAC_RX_COUNT_THRESHOLD )
+ if (priv->chnl_ss_mac_rx_count[y] > MAC_RX_COUNT_THRESHOLD)
traffic_check = 1;
-
+
#ifdef RTK_5G_SUPPORT
- if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G)
+ if (*dm->band_type == ODM_BAND_2_4G)
#endif
{
- if ((int)(y-4) >= (int)ch_begin)
- score[y-4] += 2 * priv->chnl_ss_mac_rx_count[y];
- if ((int)(y-3) >= (int)ch_begin)
- score[y-3] += 8 * priv->chnl_ss_mac_rx_count[y];
- if ((int)(y-2) >= (int)ch_begin)
- score[y-2] += 8 * priv->chnl_ss_mac_rx_count[y];
- if ((int)(y-1) >= (int)ch_begin)
- score[y-1] += 10 * priv->chnl_ss_mac_rx_count[y];
- if ((int)(y+1) < (int)ch_end)
- score[y+1] += 10 * priv->chnl_ss_mac_rx_count[y];
- if ((int)(y+2) < (int)ch_end)
- score[y+2] += 8 * priv->chnl_ss_mac_rx_count[y];
- if ((int)(y+3) < (int)ch_end)
- score[y+3] += 8 * priv->chnl_ss_mac_rx_count[y];
- if ((int)(y+4) < (int)ch_end)
- score[y+4] += 2 * priv->chnl_ss_mac_rx_count[y];
+ if ((int)(y - 4) >= (int)ch_begin)
+ score[y - 4] += 2 * priv->chnl_ss_mac_rx_count[y];
+ if ((int)(y - 3) >= (int)ch_begin)
+ score[y - 3] += 8 * priv->chnl_ss_mac_rx_count[y];
+ if ((int)(y - 2) >= (int)ch_begin)
+ score[y - 2] += 8 * priv->chnl_ss_mac_rx_count[y];
+ if ((int)(y - 1) >= (int)ch_begin)
+ score[y - 1] += 10 * priv->chnl_ss_mac_rx_count[y];
+ if ((int)(y + 1) < (int)ch_end)
+ score[y + 1] += 10 * priv->chnl_ss_mac_rx_count[y];
+ if ((int)(y + 2) < (int)ch_end)
+ score[y + 2] += 8 * priv->chnl_ss_mac_rx_count[y];
+ if ((int)(y + 3) < (int)ch_end)
+ score[y + 3] += 8 * priv->chnl_ss_mac_rx_count[y];
+ if ((int)(y + 4) < (int)ch_end)
+ score[y + 4] += 2 * priv->chnl_ss_mac_rx_count[y];
}
- //this is for CH_LOAD caculation
- if( priv->chnl_ss_cca_count[y] > priv->chnl_ss_fa_count[y])
- priv->chnl_ss_cca_count[y]-= priv->chnl_ss_fa_count[y];
+ /* this is for CH_LOAD caculation */
+ if (priv->chnl_ss_cca_count[y] > priv->chnl_ss_fa_count[y])
+ priv->chnl_ss_cca_count[y] -= priv->chnl_ss_fa_count[y];
else
priv->chnl_ss_cca_count[y] = 0;
}
-#ifdef ACS_DEBUG_INFO//for debug
+#ifdef ACS_DEBUG_INFO/* for debug */
printk("\n");
- for (y=ch_begin; yavailable_chnl[y], score[y]);
+ for (y = ch_begin; y < ch_end; y++)
+ printk("2. after 20M check: chnl[%d] score[%d]\n", priv->available_chnl[y], score[y]);
printk("\n");
-#endif
+#endif
- for (y=ch_begin; ychnl_ss_mac_rx_count_40M[y]) {
score[y] += 5 * priv->chnl_ss_mac_rx_count_40M[y];
if (priv->chnl_ss_mac_rx_count_40M[y] > 30)
do_ap_check = 0;
- if( priv->chnl_ss_mac_rx_count_40M[y] > MAC_RX_COUNT_THRESHOLD )
+ if (priv->chnl_ss_mac_rx_count_40M[y] > MAC_RX_COUNT_THRESHOLD)
traffic_check = 1;
-
+
#ifdef RTK_5G_SUPPORT
- if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G)
+ if (*dm->band_type == ODM_BAND_2_4G)
#endif
{
- if ((int)(y-6) >= (int)ch_begin)
- score[y-6] += 1 * priv->chnl_ss_mac_rx_count_40M[y];
- if ((int)(y-5) >= (int)ch_begin)
- score[y-5] += 4 * priv->chnl_ss_mac_rx_count_40M[y];
- if ((int)(y-4) >= (int)ch_begin)
- score[y-4] += 4 * priv->chnl_ss_mac_rx_count_40M[y];
- if ((int)(y-3) >= (int)ch_begin)
- score[y-3] += 5 * priv->chnl_ss_mac_rx_count_40M[y];
- if ((int)(y-2) >= (int)ch_begin)
- score[y-2] += (5 * priv->chnl_ss_mac_rx_count_40M[y])/2;
- if ((int)(y-1) >= (int)ch_begin)
- score[y-1] += 5 * priv->chnl_ss_mac_rx_count_40M[y];
- if ((int)(y+1) < (int)ch_end)
- score[y+1] += 5 * priv->chnl_ss_mac_rx_count_40M[y];
- if ((int)(y+2) < (int)ch_end)
- score[y+2] += (5 * priv->chnl_ss_mac_rx_count_40M[y])/2;
- if ((int)(y+3) < (int)ch_end)
- score[y+3] += 5 * priv->chnl_ss_mac_rx_count_40M[y];
- if ((int)(y+4) < (int)ch_end)
- score[y+4] += 4 * priv->chnl_ss_mac_rx_count_40M[y];
- if ((int)(y+5) < (int)ch_end)
- score[y+5] += 4 * priv->chnl_ss_mac_rx_count_40M[y];
- if ((int)(y+6) < (int)ch_end)
- score[y+6] += 1 * priv->chnl_ss_mac_rx_count_40M[y];
+ if ((int)(y - 6) >= (int)ch_begin)
+ score[y - 6] += 1 * priv->chnl_ss_mac_rx_count_40M[y];
+ if ((int)(y - 5) >= (int)ch_begin)
+ score[y - 5] += 4 * priv->chnl_ss_mac_rx_count_40M[y];
+ if ((int)(y - 4) >= (int)ch_begin)
+ score[y - 4] += 4 * priv->chnl_ss_mac_rx_count_40M[y];
+ if ((int)(y - 3) >= (int)ch_begin)
+ score[y - 3] += 5 * priv->chnl_ss_mac_rx_count_40M[y];
+ if ((int)(y - 2) >= (int)ch_begin)
+ score[y - 2] += (5 * priv->chnl_ss_mac_rx_count_40M[y]) / 2;
+ if ((int)(y - 1) >= (int)ch_begin)
+ score[y - 1] += 5 * priv->chnl_ss_mac_rx_count_40M[y];
+ if ((int)(y + 1) < (int)ch_end)
+ score[y + 1] += 5 * priv->chnl_ss_mac_rx_count_40M[y];
+ if ((int)(y + 2) < (int)ch_end)
+ score[y + 2] += (5 * priv->chnl_ss_mac_rx_count_40M[y]) / 2;
+ if ((int)(y + 3) < (int)ch_end)
+ score[y + 3] += 5 * priv->chnl_ss_mac_rx_count_40M[y];
+ if ((int)(y + 4) < (int)ch_end)
+ score[y + 4] += 4 * priv->chnl_ss_mac_rx_count_40M[y];
+ if ((int)(y + 5) < (int)ch_end)
+ score[y + 5] += 4 * priv->chnl_ss_mac_rx_count_40M[y];
+ if ((int)(y + 6) < (int)ch_end)
+ score[y + 6] += 1 * priv->chnl_ss_mac_rx_count_40M[y];
}
}
}
-#ifdef ACS_DEBUG_INFO//for debug
+#ifdef ACS_DEBUG_INFO/* for debug */
printk("\n");
- for (y=ch_begin; yavailable_chnl[y], score[y]);
+ for (y = ch_begin; y < ch_end; y++)
+ printk("3. after 40M check: chnl[%d] score[%d]\n", priv->available_chnl[y], score[y]);
printk("\n");
printk("4. do_ap_check=%d traffic_check=%d\n", do_ap_check, traffic_check);
printk("\n");
#endif
- if( traffic_check == 0)
+ if (traffic_check == 0)
fa_count_weighting = 5;
else
fa_count_weighting = 1;
- for (y=ch_begin; ychnl_ss_fa_count[y];
- }
-#ifdef ACS_DEBUG_INFO//for debug
+#ifdef ACS_DEBUG_INFO/* for debug */
printk("\n");
- for (y=ch_begin; yavailable_chnl[y], score[y]);
+ for (y = ch_begin; y < ch_end; y++)
+ printk("5. after fa check: chnl[%d] score[%d]\n", priv->available_chnl[y], score[y]);
printk("\n");
-#endif
+#endif
if (do_ap_check) {
- for (i=0; isite_survey->count; i++) {
+ for (i = 0; i < priv->site_survey->count; i++) {
pBss = &priv->site_survey->bss[i];
- for (y=ch_begin; ychannel == priv->available_chnl[y]) {
if (pBss->channel <= 14) {
-#ifdef ACS_DEBUG_INFO//for debug
- printk("\n");
- printk("chnl[%d] has ap rssi=%d bw[0x%02x]\n",
- pBss->channel, pBss->rssi, pBss->t_stamp[1]);
- printk("\n");
+#ifdef ACS_DEBUG_INFO/* for debug */
+ printk("\n");
+ printk("chnl[%d] has ap rssi=%d bw[0x%02x]\n",
+ pBss->channel, pBss->rssi, pBss->t_stamp[1]);
+ printk("\n");
#endif
if (pBss->rssi > 60)
ap_ratio = 4;
@@ -701,86 +662,81 @@ int phydm_AutoChannelSelectAP(
ap_ratio = 2;
else
ap_ratio = 1;
-
+
if ((pBss->t_stamp[1] & 0x6) == 0) {
score[y] += 50 * ap_ratio;
- if ((int)(y-4) >= (int)ch_begin)
- score[y-4] += 10 * ap_ratio;
- if ((int)(y-3) >= (int)ch_begin)
- score[y-3] += 20 * ap_ratio;
- if ((int)(y-2) >= (int)ch_begin)
- score[y-2] += 30 * ap_ratio;
- if ((int)(y-1) >= (int)ch_begin)
- score[y-1] += 40 * ap_ratio;
- if ((int)(y+1) < (int)ch_end)
- score[y+1] += 40 * ap_ratio;
- if ((int)(y+2) < (int)ch_end)
- score[y+2] += 30 * ap_ratio;
- if ((int)(y+3) < (int)ch_end)
- score[y+3] += 20 * ap_ratio;
- if ((int)(y+4) < (int)ch_end)
- score[y+4] += 10 * ap_ratio;
- }
- else if ((pBss->t_stamp[1] & 0x4) == 0) {
+ if ((int)(y - 4) >= (int)ch_begin)
+ score[y - 4] += 10 * ap_ratio;
+ if ((int)(y - 3) >= (int)ch_begin)
+ score[y - 3] += 20 * ap_ratio;
+ if ((int)(y - 2) >= (int)ch_begin)
+ score[y - 2] += 30 * ap_ratio;
+ if ((int)(y - 1) >= (int)ch_begin)
+ score[y - 1] += 40 * ap_ratio;
+ if ((int)(y + 1) < (int)ch_end)
+ score[y + 1] += 40 * ap_ratio;
+ if ((int)(y + 2) < (int)ch_end)
+ score[y + 2] += 30 * ap_ratio;
+ if ((int)(y + 3) < (int)ch_end)
+ score[y + 3] += 20 * ap_ratio;
+ if ((int)(y + 4) < (int)ch_end)
+ score[y + 4] += 10 * ap_ratio;
+ } else if ((pBss->t_stamp[1] & 0x4) == 0) {
score[y] += 50 * ap_ratio;
- if ((int)(y-3) >= (int)ch_begin)
- score[y-3] += 20 * ap_ratio;
- if ((int)(y-2) >= (int)ch_begin)
- score[y-2] += 30 * ap_ratio;
- if ((int)(y-1) >= (int)ch_begin)
- score[y-1] += 40 * ap_ratio;
- if ((int)(y+1) < (int)ch_end)
- score[y+1] += 50 * ap_ratio;
- if ((int)(y+2) < (int)ch_end)
- score[y+2] += 50 * ap_ratio;
- if ((int)(y+3) < (int)ch_end)
- score[y+3] += 50 * ap_ratio;
- if ((int)(y+4) < (int)ch_end)
- score[y+4] += 50 * ap_ratio;
- if ((int)(y+5) < (int)ch_end)
- score[y+5] += 40 * ap_ratio;
- if ((int)(y+6) < (int)ch_end)
- score[y+6] += 30 * ap_ratio;
- if ((int)(y+7) < (int)ch_end)
- score[y+7] += 20 * ap_ratio;
- }
- else {
+ if ((int)(y - 3) >= (int)ch_begin)
+ score[y - 3] += 20 * ap_ratio;
+ if ((int)(y - 2) >= (int)ch_begin)
+ score[y - 2] += 30 * ap_ratio;
+ if ((int)(y - 1) >= (int)ch_begin)
+ score[y - 1] += 40 * ap_ratio;
+ if ((int)(y + 1) < (int)ch_end)
+ score[y + 1] += 50 * ap_ratio;
+ if ((int)(y + 2) < (int)ch_end)
+ score[y + 2] += 50 * ap_ratio;
+ if ((int)(y + 3) < (int)ch_end)
+ score[y + 3] += 50 * ap_ratio;
+ if ((int)(y + 4) < (int)ch_end)
+ score[y + 4] += 50 * ap_ratio;
+ if ((int)(y + 5) < (int)ch_end)
+ score[y + 5] += 40 * ap_ratio;
+ if ((int)(y + 6) < (int)ch_end)
+ score[y + 6] += 30 * ap_ratio;
+ if ((int)(y + 7) < (int)ch_end)
+ score[y + 7] += 20 * ap_ratio;
+ } else {
score[y] += 50 * ap_ratio;
- if ((int)(y-7) >= (int)ch_begin)
- score[y-7] += 20 * ap_ratio;
- if ((int)(y-6) >= (int)ch_begin)
- score[y-6] += 30 * ap_ratio;
- if ((int)(y-5) >= (int)ch_begin)
- score[y-5] += 40 * ap_ratio;
- if ((int)(y-4) >= (int)ch_begin)
- score[y-4] += 50 * ap_ratio;
- if ((int)(y-3) >= (int)ch_begin)
- score[y-3] += 50 * ap_ratio;
- if ((int)(y-2) >= (int)ch_begin)
- score[y-2] += 50 * ap_ratio;
- if ((int)(y-1) >= (int)ch_begin)
- score[y-1] += 50 * ap_ratio;
- if ((int)(y+1) < (int)ch_end)
- score[y+1] += 40 * ap_ratio;
- if ((int)(y+2) < (int)ch_end)
- score[y+2] += 30 * ap_ratio;
- if ((int)(y+3) < (int)ch_end)
- score[y+3] += 20 * ap_ratio;
- }
- }
- else {
- if ((pBss->t_stamp[1] & 0x6) == 0) {
- score[y] += 500;
+ if ((int)(y - 7) >= (int)ch_begin)
+ score[y - 7] += 20 * ap_ratio;
+ if ((int)(y - 6) >= (int)ch_begin)
+ score[y - 6] += 30 * ap_ratio;
+ if ((int)(y - 5) >= (int)ch_begin)
+ score[y - 5] += 40 * ap_ratio;
+ if ((int)(y - 4) >= (int)ch_begin)
+ score[y - 4] += 50 * ap_ratio;
+ if ((int)(y - 3) >= (int)ch_begin)
+ score[y - 3] += 50 * ap_ratio;
+ if ((int)(y - 2) >= (int)ch_begin)
+ score[y - 2] += 50 * ap_ratio;
+ if ((int)(y - 1) >= (int)ch_begin)
+ score[y - 1] += 50 * ap_ratio;
+ if ((int)(y + 1) < (int)ch_end)
+ score[y + 1] += 40 * ap_ratio;
+ if ((int)(y + 2) < (int)ch_end)
+ score[y + 2] += 30 * ap_ratio;
+ if ((int)(y + 3) < (int)ch_end)
+ score[y + 3] += 20 * ap_ratio;
}
+ } else {
+ if ((pBss->t_stamp[1] & 0x6) == 0)
+ score[y] += 500;
else if ((pBss->t_stamp[1] & 0x4) == 0) {
score[y] += 500;
- if ((int)(y+1) < (int)ch_end)
- score[y+1] += 500;
- }
- else {
+ if ((int)(y + 1) < (int)ch_end)
+ score[y + 1] += 500;
+ } else {
score[y] += 500;
- if ((int)(y-1) >= (int)ch_begin)
- score[y-1] += 500;
+ if ((int)(y - 1) >= (int)ch_begin)
+ score[y - 1] += 500;
}
}
break;
@@ -789,78 +745,75 @@ int phydm_AutoChannelSelectAP(
}
}
-#ifdef ACS_DEBUG_INFO//for debug
+#ifdef ACS_DEBUG_INFO/* for debug */
printk("\n");
- for (y=ch_begin; yavailable_chnl[y],score[y]);
+ for (y = ch_begin; y < ch_end; y++)
+ printk("6. after ap check: chnl[%d]:%d\n", priv->available_chnl[y], score[y]);
printk("\n");
-#endif
+#endif
-#ifdef SS_CH_LOAD_PROC
+#ifdef SS_CH_LOAD_PROC
- // caculate noise level -- suggested by wilson
- for (y=ch_begin; ychnl_ss_fa_count[y]>1000) {
+ /* caculate noise level -- suggested by wilson */
+ for (y = ch_begin; y < ch_end; y++) {
+ int fa_lv = 0, cca_lv = 0;
+ if (priv->chnl_ss_fa_count[y] > 1000)
fa_lv = 100;
- } else if (priv->chnl_ss_fa_count[y]>500) {
- fa_lv = 34 * (priv->chnl_ss_fa_count[y]-500) / 500 + 66;
- } else if (priv->chnl_ss_fa_count[y]>200) {
+ else if (priv->chnl_ss_fa_count[y] > 500)
+ fa_lv = 34 * (priv->chnl_ss_fa_count[y] - 500) / 500 + 66;
+ else if (priv->chnl_ss_fa_count[y] > 200)
fa_lv = 33 * (priv->chnl_ss_fa_count[y] - 200) / 300 + 33;
- } else if (priv->chnl_ss_fa_count[y]>100) {
+ else if (priv->chnl_ss_fa_count[y] > 100)
fa_lv = 18 * (priv->chnl_ss_fa_count[y] - 100) / 100 + 15;
- } else {
+ else
fa_lv = 15 * priv->chnl_ss_fa_count[y] / 100;
- }
- if (priv->chnl_ss_cca_count[y]>400) {
+ if (priv->chnl_ss_cca_count[y] > 400)
cca_lv = 100;
- } else if (priv->chnl_ss_cca_count[y]>200) {
+ else if (priv->chnl_ss_cca_count[y] > 200)
cca_lv = 34 * (priv->chnl_ss_cca_count[y] - 200) / 200 + 66;
- } else if (priv->chnl_ss_cca_count[y]>80) {
+ else if (priv->chnl_ss_cca_count[y] > 80)
cca_lv = 33 * (priv->chnl_ss_cca_count[y] - 80) / 120 + 33;
- } else if (priv->chnl_ss_cca_count[y]>40) {
+ else if (priv->chnl_ss_cca_count[y] > 40)
cca_lv = 18 * (priv->chnl_ss_cca_count[y] - 40) / 40 + 15;
- } else {
+ else
cca_lv = 15 * priv->chnl_ss_cca_count[y] / 40;
- }
- priv->chnl_ss_load[y] = (((fa_lv > cca_lv)? fa_lv : cca_lv)*75+((score[y]>100)?100:score[y])*25)/100;
-
- DEBUG_INFO("ch:%d f=%d (%d), c=%d (%d), fl=%d, cl=%d, sc=%d, cu=%d\n",
- priv->available_chnl[y],
- priv->chnl_ss_fa_count[y], fa_thd,
- priv->chnl_ss_cca_count[y], cca_thd,
- fa_lv,
- cca_lv,
- score[y],
- priv->chnl_ss_load[y]);
-
- }
-#endif
+ priv->chnl_ss_load[y] = (((fa_lv > cca_lv) ? fa_lv : cca_lv) * 75 + ((score[y] > 100) ? 100 : score[y]) * 25) / 100;
+
+ DEBUG_INFO("ch:%d f=%d (%d), c=%d (%d), fl=%d, cl=%d, sc=%d, cu=%d\n",
+ priv->available_chnl[y],
+ priv->chnl_ss_fa_count[y], fa_thd,
+ priv->chnl_ss_cca_count[y], cca_thd,
+ fa_lv,
+ cca_lv,
+ score[y],
+ priv->chnl_ss_load[y]);
+
+ }
+#endif
}
#endif
choose_ch:
#ifdef DFS
- // heavy weighted DFS channel
- if (idx_5G_begin >= 0){
- for (i=idx_5G_begin; iavailable_chnl_num; i++) {
- if (!priv->pmib->dot11DFSEntry.disable_DFS && is_DFS_channel(priv->available_chnl[i])
- && (score[i]!= 0xffffffff)){
- score[i] += 1600;
+ /* heavy weighted DFS channel */
+ if (idx_5G_begin >= 0) {
+ for (i = idx_5G_begin; i < priv->available_chnl_num; i++) {
+ if (!priv->pmib->dot11DFSEntry.disable_DFS && is_DFS_channel(priv->available_chnl[i])
+ && (score[i] != 0xffffffff))
+ score[i] += 1600;
}
}
- }
#endif
-//prevent Auto Channel selecting wrong channel in 40M mode-----------------
+ /* prevent Auto channel selecting wrong channel in 40M mode----------------- */
if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11N)
- && priv->pshare->is_40m_bw) {
+ && priv->pshare->is_40m_bw) {
#if 0
if (GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset == 1) {
- //Upper Primary Channel, cannot select the two lowest channels
+ /* Upper Primary channel, cannot select the two lowest channels */
if (priv->pmib->dot11BssType.net_work_type & WIRELESS_11G) {
score[0] = 0xffffffff;
score[1] = 0xffffffff;
@@ -873,13 +826,12 @@ int phydm_AutoChannelSelectAP(
score[11] = 0xffffffff;
}
-// if (priv->pmib->dot11BssType.net_work_type & WIRELESS_11A) {
-// score[idx_5G_begin] = 0xffffffff;
-// score[idx_5G_begin + 1] = 0xffffffff;
-// }
- }
- else if (GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset == 2) {
- //Lower Primary Channel, cannot select the two highest channels
+ /* if (priv->pmib->dot11BssType.net_work_type & WIRELESS_11A) { */
+ /* score[idx_5G_begin] = 0xffffffff; */
+ /* score[idx_5G_begin + 1] = 0xffffffff; */
+ /* } */
+ } else if (GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset == 2) {
+ /* Lower Primary channel, cannot select the two highest channels */
if (priv->pmib->dot11BssType.net_work_type & WIRELESS_11G) {
score[0] = 0xffffffff;
score[1] = 0xffffffff;
@@ -892,33 +844,33 @@ int phydm_AutoChannelSelectAP(
score[9] = 0xffffffff;
}
-// if (priv->pmib->dot11BssType.net_work_type & WIRELESS_11A) {
-// score[priv->available_chnl_num - 2] = 0xffffffff;
-// score[priv->available_chnl_num - 1] = 0xffffffff;
-// }
+ /* if (priv->pmib->dot11BssType.net_work_type & WIRELESS_11A) { */
+ /* score[priv->available_chnl_num - 2] = 0xffffffff; */
+ /* score[priv->available_chnl_num - 1] = 0xffffffff; */
+ /* } */
}
#endif
- for (i=0; i<=idx_2G_end; ++i)
+ for (i = 0; i <= idx_2G_end; ++i)
if (priv->available_chnl[i] == 14)
- score[i] = 0xffffffff; // mask chan14
+ score[i] = 0xffffffff; /* mask chan14 */
#ifdef RTK_5G_SUPPORT
if (idx_5G_begin >= 0) {
- for (i=idx_5G_begin; iavailable_chnl_num; i++) {
+ for (i = idx_5G_begin; i < priv->available_chnl_num; i++) {
int ch = priv->available_chnl[i];
- if(priv->available_chnl[i] > 144)
+ if (priv->available_chnl[i] > 144)
--ch;
- if((ch%4) || ch==140 || ch == 164 ) //mask ch 140, ch 165, ch 184...
+ if ((ch % 4) || ch == 140 || ch == 164) /* mask ch 140, ch 165, ch 184... */
score[i] = 0xffffffff;
}
}
#endif
-
+
}
if (priv->pmib->dot11RFEntry.disable_ch1213) {
- for (i=0; i<=idx_2G_end; ++i) {
+ for (i = 0; i <= idx_2G_end; ++i) {
int ch = priv->available_chnl[i];
if ((ch == 12) || (ch == 13))
score[i] = 0xffffffff;
@@ -926,33 +878,31 @@ int phydm_AutoChannelSelectAP(
}
if (((priv->pmib->dot11StationConfigEntry.dot11RegDomain == DOMAIN_GLOBAL) ||
- (priv->pmib->dot11StationConfigEntry.dot11RegDomain == DOMAIN_WORLD_WIDE)) &&
- (idx_2G_end >= 11) && (idx_2G_end < 14)) {
- score[13] = 0xffffffff; // mask chan14
- score[12] = 0xffffffff; // mask chan13
- score[11] = 0xffffffff; // mask chan12
+ (priv->pmib->dot11StationConfigEntry.dot11RegDomain == DOMAIN_WORLD_WIDE)) &&
+ (idx_2G_end >= 11) && (idx_2G_end < 14)) {
+ score[13] = 0xffffffff; /* mask chan14 */
+ score[12] = 0xffffffff; /* mask chan13 */
+ score[11] = 0xffffffff; /* mask chan12 */
}
-
-//------------------------------------------------------------------
+
+ /* ------------------------------------------------------------------ */
#ifdef _DEBUG_RTL8192CD_
- for (i=0; iavailable_chnl_num; i++) {
- len += sprintf(tmpbuf+len, "ch%d:%u ", priv->available_chnl[i], score[i]);
- }
+ for (i = 0; i < priv->available_chnl_num; i++)
+ len += sprintf(tmpbuf + len, "ch%d:%u ", priv->available_chnl[i], score[i]);
strcat(tmpbuf, "\n");
panic_printk("%s", tmpbuf);
#endif
- if ( (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G)
- && (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_80))
- {
- for (i=0; iavailable_chnl_num; i++) {
+ if ((*dm->band_type == ODM_BAND_5G)
+ && (priv->pmib->dot11nConfigEntry.dot11nUse40M == CHANNEL_WIDTH_80)) {
+ for (i = 0; i < priv->available_chnl_num; i++) {
if (is80MChannel(priv->available_chnl, priv->available_chnl_num, priv->available_chnl[i])) {
tmpScore = 0;
- for (j=0; j<4; j++) {
- if ((tmpScore != 0xffffffff) && (score[i+j] != 0xffffffff))
- tmpScore += score[i+j];
+ for (j = 0; j < 4; j++) {
+ if ((tmpScore != 0xffffffff) && (score[i + j] != 0xffffffff))
+ tmpScore += score[i + j];
else
tmpScore = 0xffffffff;
}
@@ -961,10 +911,10 @@ int phydm_AutoChannelSelectAP(
minScore = tmpScore;
tmpScore = 0xffffffff;
- for (j=0; j<4; j++) {
- if (score[i+j] < tmpScore) {
- tmpScore = score[i+j];
- tmpIdx = i+j;
+ for (j = 0; j < 4; j++) {
+ if (score[i + j] < tmpScore) {
+ tmpScore = score[i + j];
+ tmpIdx = i + j;
}
}
@@ -974,37 +924,35 @@ int phydm_AutoChannelSelectAP(
}
}
if (minScore == 0xffffffff) {
- // there is no 80M channels
- priv->pshare->is_40m_bw = HT_CHANNEL_WIDTH_20;
- for (i=0; iavailable_chnl_num; i++) {
+ /* there is no 80M channels */
+ priv->pshare->is_40m_bw = CHANNEL_WIDTH_20;
+ for (i = 0; i < priv->available_chnl_num; i++) {
if (score[i] < minScore) {
minScore = score[i];
idx = i;
}
}
}
- }
- else if( (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G)
- && (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_20_40))
- {
- for (i=0; iavailable_chnl_num; i++) {
- if(is40MChannel(priv->available_chnl,priv->available_chnl_num,priv->available_chnl[i])) {
+ } else if ((*dm->band_type == ODM_BAND_5G)
+ && (priv->pmib->dot11nConfigEntry.dot11nUse40M == CHANNEL_WIDTH_40)) {
+ for (i = 0; i < priv->available_chnl_num; i++) {
+ if (is40MChannel(priv->available_chnl, priv->available_chnl_num, priv->available_chnl[i])) {
tmpScore = 0;
- for(j=0;j<2;j++) {
- if ((tmpScore != 0xffffffff) && (score[i+j] != 0xffffffff))
- tmpScore += score[i+j];
+ for (j = 0; j < 2; j++) {
+ if ((tmpScore != 0xffffffff) && (score[i + j] != 0xffffffff))
+ tmpScore += score[i + j];
else
tmpScore = 0xffffffff;
}
tmpScore = tmpScore / 2;
- if(minScore > tmpScore) {
+ if (minScore > tmpScore) {
minScore = tmpScore;
tmpScore = 0xffffffff;
- for (j=0; j<2; j++) {
- if (score[i+j] < tmpScore) {
- tmpScore = score[i+j];
- tmpIdx = i+j;
+ for (j = 0; j < 2; j++) {
+ if (score[i + j] < tmpScore) {
+ tmpScore = score[i + j];
+ tmpIdx = i + j;
}
}
@@ -1014,40 +962,35 @@ int phydm_AutoChannelSelectAP(
}
}
if (minScore == 0xffffffff) {
- // there is no 40M channels
- priv->pshare->is_40m_bw = HT_CHANNEL_WIDTH_20;
- for (i=0; iavailable_chnl_num; i++) {
+ /* there is no 40M channels */
+ priv->pshare->is_40m_bw = CHANNEL_WIDTH_20;
+ for (i = 0; i < priv->available_chnl_num; i++) {
if (score[i] < minScore) {
minScore = score[i];
idx = i;
}
}
}
- }
- else if( (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G)
- && (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_20_40)
- && (priv->available_chnl_num >= 8) )
- {
- u4Byte groupScore[14];
-
- memset(groupScore, 0xff , sizeof(groupScore));
- for (i=0; iavailable_chnl_num-4; i++) {
- if (score[i] != 0xffffffff && score[i+4] != 0xffffffff) {
- groupScore[i] = score[i] + score[i+4];
- DEBUG_INFO("groupScore, ch %d,%d: %d\n", i+1, i+5, groupScore[i]);
+ } else if ((*dm->band_type == ODM_BAND_2_4G)
+ && (priv->pmib->dot11nConfigEntry.dot11nUse40M == CHANNEL_WIDTH_40)
+ && (priv->available_chnl_num >= 8)) {
+ u32 groupScore[14];
+
+ memset(groupScore, 0xff, sizeof(groupScore));
+ for (i = 0; i < priv->available_chnl_num - 4; i++) {
+ if (score[i] != 0xffffffff && score[i + 4] != 0xffffffff) {
+ groupScore[i] = score[i] + score[i + 4];
+ DEBUG_INFO("groupScore, ch %d,%d: %d\n", i + 1, i + 5, groupScore[i]);
if (groupScore[i] < minScore) {
#ifdef AUTOCH_SS_SPEEDUP
- if(priv->pmib->miscEntry.autoch_1611_enable)
- {
- if(priv->available_chnl[i]==1 || priv->available_chnl[i]==6 || priv->available_chnl[i]==11)
- {
+ if (priv->pmib->miscEntry.autoch_1611_enable) {
+ if (priv->available_chnl[i] == 1 || priv->available_chnl[i] == 6 || priv->available_chnl[i] == 11) {
minScore = groupScore[i];
idx = i;
}
- }
- else
+ } else
#endif
- {
+ {
minScore = groupScore[i];
idx = i;
}
@@ -1055,31 +998,26 @@ int phydm_AutoChannelSelectAP(
}
}
- if (score[idx] < score[idx+4]) {
+ if (score[idx] < score[idx + 4]) {
GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_ABOVE;
- priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_ABOVE;
+ priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_ABOVE;
} else {
idx = idx + 4;
GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_BELOW;
- priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_BELOW;
+ priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_BELOW;
}
- }
- else
- {
- for (i=0; iavailable_chnl_num; i++) {
+ } else {
+ for (i = 0; i < priv->available_chnl_num; i++) {
if (score[i] < minScore) {
#ifdef AUTOCH_SS_SPEEDUP
- if(priv->pmib->miscEntry.autoch_1611_enable)
- {
- if(priv->available_chnl[i]==1 || priv->available_chnl[i]==6 || priv->available_chnl[i]==11)
- {
+ if (priv->pmib->miscEntry.autoch_1611_enable) {
+ if (priv->available_chnl[i] == 1 || priv->available_chnl[i] == 6 || priv->available_chnl[i] == 11) {
minScore = score[i];
idx = i;
}
- }
- else
+ } else
#endif
- {
+ {
minScore = score[i];
idx = i;
}
@@ -1088,34 +1026,34 @@ int phydm_AutoChannelSelectAP(
}
if (IS_A_CUT_8881A(priv) &&
- (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_80)) {
+ (priv->pmib->dot11nConfigEntry.dot11nUse40M == CHANNEL_WIDTH_80)) {
if ((priv->available_chnl[idx] == 36) ||
- (priv->available_chnl[idx] == 52) ||
- (priv->available_chnl[idx] == 100) ||
- (priv->available_chnl[idx] == 116) ||
- (priv->available_chnl[idx] == 132) ||
- (priv->available_chnl[idx] == 149) ||
- (priv->available_chnl[idx] == 165))
+ (priv->available_chnl[idx] == 52) ||
+ (priv->available_chnl[idx] == 100) ||
+ (priv->available_chnl[idx] == 116) ||
+ (priv->available_chnl[idx] == 132) ||
+ (priv->available_chnl[idx] == 149) ||
+ (priv->available_chnl[idx] == 165))
idx++;
else if ((priv->available_chnl[idx] == 48) ||
- (priv->available_chnl[idx] == 64) ||
- (priv->available_chnl[idx] == 112) ||
- (priv->available_chnl[idx] == 128) ||
- (priv->available_chnl[idx] == 144) ||
- (priv->available_chnl[idx] == 161) ||
- (priv->available_chnl[idx] == 177))
+ (priv->available_chnl[idx] == 64) ||
+ (priv->available_chnl[idx] == 112) ||
+ (priv->available_chnl[idx] == 128) ||
+ (priv->available_chnl[idx] == 144) ||
+ (priv->available_chnl[idx] == 161) ||
+ (priv->available_chnl[idx] == 177))
idx--;
}
minChan = priv->available_chnl[idx];
- // skip channel 14 if don't support ofdm
+ /* skip channel 14 if don't support ofdm */
if ((priv->pmib->dot11RFEntry.disable_ch14_ofdm) &&
- (minChan == 14)) {
+ (minChan == 14)) {
score[idx] = 0xffffffff;
-
+
minScore = 0xffffffff;
- for (i=0; iavailable_chnl_num; i++) {
+ for (i = 0; i < priv->available_chnl_num; i++) {
if (score[i] < minScore) {
minScore = score[i];
idx = i;
@@ -1125,26 +1063,19 @@ int phydm_AutoChannelSelectAP(
}
#if 0
- //Check if selected channel available for 80M/40M BW or NOT ?
- if(priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G)
- {
- if(priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_80)
- {
- if(!is80MChannel(priv->available_chnl,priv->available_chnl_num,minChan))
- {
- //printk("BW=80M, selected channel = %d is unavaliable! reduce to 40M\n", minChan);
- //priv->pmib->dot11nConfigEntry.dot11nUse40M = HT_CHANNEL_WIDTH_20_40;
- priv->pshare->is_40m_bw = HT_CHANNEL_WIDTH_20_40;
+ /* Check if selected channel available for 80M/40M BW or NOT ? */
+ if (*dm->band_type == ODM_BAND_5G) {
+ if (priv->pmib->dot11nConfigEntry.dot11nUse40M == CHANNEL_WIDTH_80) {
+ if (!is80MChannel(priv->available_chnl, priv->available_chnl_num, minChan)) {
+ /* priv->pmib->dot11n_config_entry.dot11nUse40M = CHANNEL_WIDTH_40; */
+ priv->pshare->is_40m_bw = CHANNEL_WIDTH_40;
}
}
-
- if(priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_20_40)
- {
- if(!is40MChannel(priv->available_chnl,priv->available_chnl_num,minChan))
- {
- //printk("BW=40M, selected channel = %d is unavaliable! reduce to 20M\n", minChan);
- //priv->pmib->dot11nConfigEntry.dot11nUse40M = HT_CHANNEL_WIDTH_20;
- priv->pshare->is_40m_bw = HT_CHANNEL_WIDTH_20;
+
+ if (priv->pmib->dot11nConfigEntry.dot11nUse40M == CHANNEL_WIDTH_40) {
+ if (!is40MChannel(priv->available_chnl, priv->available_chnl_num, minChan)) {
+ /* priv->pmib->dot11n_config_entry.dot11nUse40M = CHANNEL_WIDTH_20; */
+ priv->pshare->is_40m_bw = CHANNEL_WIDTH_20;
}
}
}
@@ -1154,13 +1085,12 @@ int phydm_AutoChannelSelectAP(
RTL_W32(RXERR_RPT, RXERR_RPT_RST);
#endif
-// auto adjust contro-sideband
+ /* auto adjust contro-sideband */
if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11N)
- && (priv->pshare->is_40m_bw ==1 || priv->pshare->is_40m_bw ==2)) {
-
+ && (priv->pshare->is_40m_bw == 1 || priv->pshare->is_40m_bw == 2)) {
#ifdef RTK_5G_SUPPORT
- if (priv->pmib->dot11RFEntry.phyBandSelect & PHY_BAND_5G) {
- if( (minChan>144) ? ((minChan-1)%8) : (minChan%8)) {
+ if (*dm->band_type == ODM_BAND_5G) {
+ if ((minChan > 144) ? ((minChan - 1) % 8) : (minChan % 8)) {
GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_ABOVE;
priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_ABOVE;
} else {
@@ -1169,7 +1099,7 @@ int phydm_AutoChannelSelectAP(
}
} else
-#endif
+#endif
{
#if 0
#ifdef CONFIG_RTL_NEW_AUTOCH
@@ -1180,8 +1110,8 @@ int phydm_AutoChannelSelectAP(
else
ch_max = priv->available_chnl[idx_2G_end];
- if ((minChan >= 5) && (minChan <= (ch_max-5))) {
- if (score[minChan+4] > score[minChan-4]) { // what if some channels were cancelled?
+ if ((minChan >= 5) && (minChan <= (ch_max - 5))) {
+ if (score[minChan + 4] > score[minChan - 4]) { /* what if some channels were cancelled? */
GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_BELOW;
priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_BELOW;
} else {
@@ -1194,8 +1124,7 @@ int phydm_AutoChannelSelectAP(
if (minChan < 5) {
GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_ABOVE;
priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_ABOVE;
- }
- else if (minChan > 7) {
+ } else if (minChan > 7) {
GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_BELOW;
priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_BELOW;
}
@@ -1203,7 +1132,7 @@ int phydm_AutoChannelSelectAP(
#endif
}
}
-//-----------------------
+ /* ----------------------- */
#if defined(__ECOS) && defined(CONFIG_SDIO_HCI)
panic_printk("Auto channel choose ch:%d\n", minChan);
@@ -1212,15 +1141,12 @@ int phydm_AutoChannelSelectAP(
panic_printk("Auto channel choose ch:%d\n", minChan);
#endif
#endif
-#ifdef ACS_DEBUG_INFO//for debug
+#ifdef ACS_DEBUG_INFO/* for debug */
printk("7. minChan:%d 2nd_offset:%d\n", minChan, priv->pshare->offset_2nd_chan);
#endif
return minChan;
}
-*/
-
#endif
-
-
+#endif
diff --git a/hal/phydm/phydm_acs.h b/hal/phydm/phydm_acs.h
index a12e120..61bdecc 100644
--- a/hal/phydm/phydm_acs.h
+++ b/hal/phydm/phydm_acs.h
@@ -1,23 +1,28 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
- *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
*
+ * Larry Finger
*
- ******************************************************************************/
-
+ *****************************************************************************/
+
#ifndef __PHYDMACS_H__
#define __PHYDMACS_H__
@@ -27,80 +32,84 @@
#define ODM_MAX_CHANNEL_2G 14
#define ODM_MAX_CHANNEL_5G 24
-// For phydm_AutoChannelSelectSettingAP()
+/* For phydm_auto_channel_select_setting_ap() */
#define STORE_DEFAULT_NHM_SETTING 0
#define RESTORE_DEFAULT_NHM_SETTING 1
#define ACS_NHM_SETTING 2
-typedef struct _ACS_
-{
- BOOLEAN bForceACSResult;
- u1Byte CleanChannel_2G;
- u1Byte CleanChannel_5G;
- u2Byte Channel_Info_2G[2][ODM_MAX_CHANNEL_2G]; //Channel_Info[1]: Channel Score, Channel_Info[2]:Channel_Scan_Times
- u2Byte Channel_Info_5G[2][ODM_MAX_CHANNEL_5G];
-
-#if ( DM_ODM_SUPPORT_TYPE & ODM_AP )
- u1Byte ACS_Step;
- // NHM Count 0-11
- u1Byte NHM_Cnt[14][11];
-
- // AC-Series, for storing previous setting
- u4Byte Reg0x990;
- u4Byte Reg0x994;
- u4Byte Reg0x998;
- u4Byte Reg0x99C;
- u1Byte Reg0x9A0; // u1Byte
-
- // N-Series, for storing previous setting
- u4Byte Reg0x890;
- u4Byte Reg0x894;
- u4Byte Reg0x898;
- u4Byte Reg0x89C;
- u1Byte Reg0xE28; // u1Byte
+struct acs_info {
+ boolean is_force_acs_result;
+ u8 clean_channel_2g;
+ u8 clean_channel_5g;
+ u16 channel_info_2g[2][ODM_MAX_CHANNEL_2G]; /* Channel_Info[1]: channel score, Channel_Info[2]:Channel_Scan_Times */
+ u16 channel_info_5g[2][ODM_MAX_CHANNEL_5G];
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ u8 acs_step;
+ /* NHM count 0-11 */
+ u8 nhm_cnt[14][11];
+
+ /* AC-Series, for storing previous setting */
+ u32 reg0x990;
+ u32 reg0x994;
+ u32 reg0x998;
+ u32 reg0x99c;
+ u8 reg0x9a0; /* u8 */
+
+ /* N-Series, for storing previous setting */
+ u32 reg0x890;
+ u32 reg0x894;
+ u32 reg0x898;
+ u32 reg0x89c;
+ u8 reg0xe28; /* u8 */
#endif
-}ACS, *PACS;
+};
-VOID
-odm_AutoChannelSelectInit(
- IN PVOID pDM_VOID
+void
+odm_auto_channel_select_init(
+ void *dm_void
+);
+
+void
+odm_auto_channel_select_reset(
+ void *dm_void
);
-VOID
-odm_AutoChannelSelectReset(
- IN PVOID pDM_VOID
+void
+odm_auto_channel_select(
+ void *dm_void,
+ u8 channel
);
-VOID
-odm_AutoChannelSelect(
- IN PVOID pDM_VOID,
- IN u1Byte Channel
+u8
+odm_get_auto_channel_select_result(
+ void *dm_void,
+ u8 band
);
-u1Byte
-ODM_GetAutoChannelSelectResult(
- IN PVOID pDM_VOID,
- IN u1Byte Band
+boolean
+phydm_acs_check(
+ void *dm_void
);
-#if ( DM_ODM_SUPPORT_TYPE & ODM_AP )
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
-VOID
-phydm_AutoChannelSelectSettingAP(
- IN PVOID pDM_VOID,
- IN u4Byte Setting, // 0: STORE_DEFAULT_NHM_SETTING; 1: RESTORE_DEFAULT_NHM_SETTING, 2: ACS_NHM_SETTING
- IN u4Byte acs_step
+void
+phydm_auto_channel_select_setting_ap(
+ void *dm_void,
+ u32 setting, /* 0: STORE_DEFAULT_NHM_SETTING; 1: RESTORE_DEFAULT_NHM_SETTING, 2: ACS_NHM_SETTING */
+ u32 acs_step
);
-VOID
-phydm_GetNHMStatisticsAP(
- IN PVOID pDM_VOID,
- IN u4Byte idx, // @ 2G, Real channel number = idx+1
- IN u4Byte acs_step
+void
+phydm_get_nhm_statistics_ap(
+ void *dm_void,
+ u32 idx, /* @ 2G, Real channel number = idx+1 */
+ u32 acs_step
);
-#endif //#if ( DM_ODM_SUPPORT_TYPE & ODM_AP )
+#endif /* #if ( DM_ODM_SUPPORT_TYPE & ODM_AP ) */
-#endif //#ifndef __PHYDMACS_H__
\ No newline at end of file
+#endif /* #ifndef __PHYDMACS_H__ */
diff --git a/hal/phydm/phydm_adaptivity.c b/hal/phydm/phydm_adaptivity.c
index 956147a..fafe2d5 100644
--- a/hal/phydm/phydm_adaptivity.c
+++ b/hal/phydm/phydm_adaptivity.c
@@ -1,6 +1,6 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
@@ -8,991 +8,769 @@
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
*
+ * Contact Information:
+ * wlanfae
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
*
- ******************************************************************************/
+ * Larry Finger
+ *
+ *****************************************************************************/
-//============================================================
-// include files
-//============================================================
+/* ************************************************************
+ * include files
+ * ************************************************************ */
#include "mp_precomp.h"
#include "phydm_precomp.h"
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-#if WPP_SOFTWARE_TRACE
-#include "PhyDM_Adaptivity.tmh"
-#endif
+ #if WPP_SOFTWARE_TRACE
+ #include "PhyDM_Adaptivity.tmh"
+ #endif
#endif
-
-VOID
-Phydm_CheckAdaptivity(
- IN PVOID pDM_VOID
+void
+phydm_dig_up_bound_lmt_en(
+ void *dm_void
)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);
-
- if (pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY) {
-#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
- if (pDM_Odm->APTotalNum > Adaptivity->APNumTH) {
- pDM_Odm->Adaptivity_enable = FALSE;
- pDM_Odm->adaptivity_flag = FALSE;
- ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("AP total num > %d!!, disable adaptivity\n", Adaptivity->APNumTH));
- } else
-#endif
- {
- if (Adaptivity->DynamicLinkAdaptivity || Adaptivity->AcsForAdaptivity) {
- if (pDM_Odm->bLinked && Adaptivity->bCheck == FALSE) {
- Phydm_NHMCounterStatistics(pDM_Odm);
- Phydm_CheckEnvironment(pDM_Odm);
- } else if (!pDM_Odm->bLinked)
- Adaptivity->bCheck = FALSE;
- } else {
- pDM_Odm->Adaptivity_enable = TRUE;
-
- if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))
- pDM_Odm->adaptivity_flag = FALSE;
- else
- pDM_Odm->adaptivity_flag = TRUE;
- }
- }
- } else {
- pDM_Odm->Adaptivity_enable = FALSE;
- pDM_Odm->adaptivity_flag = FALSE;
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct phydm_adaptivity_struct *adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(dm, PHYDM_ADAPTIVITY);
+
+ if (!(dm->support_ability & ODM_BB_ADAPTIVITY) ||
+ (!dm->adaptivity_flag) ||
+ (!dm->is_linked) ||
+ (!dm->adaptivity_enable)
+ ) {
+ adaptivity->igi_up_bound_lmt_cnt = 0;
+ adaptivity->igi_lmt_en = false;
+ return;
}
-
+ if (dm->total_tp > 1) {
+ adaptivity->igi_lmt_en = true;
+ adaptivity->igi_up_bound_lmt_cnt = adaptivity->igi_up_bound_lmt_val;
+ PHYDM_DBG(dm, DBG_ADPTVTY, "TP >1, Start limit IGI upper bound\n");
+ } else {
+ if (adaptivity->igi_up_bound_lmt_cnt == 0)
+ adaptivity->igi_lmt_en = false;
+ else
+ adaptivity->igi_up_bound_lmt_cnt--;
+ }
+ PHYDM_DBG(dm, DBG_ADPTVTY, "IGI_lmt_cnt = %d\n", adaptivity->igi_up_bound_lmt_cnt);
}
-#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-BOOLEAN
-Phydm_CheckChannelPlan(
- IN PVOID pDM_VOID
+void
+phydm_check_adaptivity(
+ void *dm_void
)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- PADAPTER pAdapter = pDM_Odm->Adapter;
- PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo);
-
- if (pMgntInfo->RegEnableAdaptivity == 2) {
- if (pDM_Odm->Carrier_Sense_enable == FALSE) { /*check domain Code for Adaptivity or CarrierSense*/
- if ((*pDM_Odm->pBandType == ODM_BAND_5G) &&
- !(pDM_Odm->odm_Regulation5G == REGULATION_ETSI || pDM_Odm->odm_Regulation5G == REGULATION_WW)) {
- ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity skip 5G domain code : %d\n", pDM_Odm->odm_Regulation5G));
- pDM_Odm->Adaptivity_enable = FALSE;
- pDM_Odm->adaptivity_flag = FALSE;
- return TRUE;
- } else if ((*pDM_Odm->pBandType == ODM_BAND_2_4G) &&
- !(pDM_Odm->odm_Regulation2_4G == REGULATION_ETSI || pDM_Odm->odm_Regulation2_4G == REGULATION_WW)) {
- ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity skip 2.4G domain code : %d\n", pDM_Odm->odm_Regulation2_4G));
- pDM_Odm->Adaptivity_enable = FALSE;
- pDM_Odm->adaptivity_flag = FALSE;
- return TRUE;
-
- } else if ((*pDM_Odm->pBandType != ODM_BAND_2_4G) && (*pDM_Odm->pBandType != ODM_BAND_5G)) {
- ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity neither 2G nor 5G band, return\n"));
- pDM_Odm->Adaptivity_enable = FALSE;
- pDM_Odm->adaptivity_flag = FALSE;
- return TRUE;
- }
- } else {
- if ((*pDM_Odm->pBandType == ODM_BAND_5G) &&
- !(pDM_Odm->odm_Regulation5G == REGULATION_MKK || pDM_Odm->odm_Regulation5G == REGULATION_WW)) {
- ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 5G domain code : %d\n", pDM_Odm->odm_Regulation5G));
- pDM_Odm->Adaptivity_enable = FALSE;
- pDM_Odm->adaptivity_flag = FALSE;
- return TRUE;
- }
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct phydm_adaptivity_struct *adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(dm, PHYDM_ADAPTIVITY);
- else if ((*pDM_Odm->pBandType == ODM_BAND_2_4G) &&
- !(pDM_Odm->odm_Regulation2_4G == REGULATION_MKK || pDM_Odm->odm_Regulation2_4G == REGULATION_WW)) {
- ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 2.4G domain code : %d\n", pDM_Odm->odm_Regulation2_4G));
- pDM_Odm->Adaptivity_enable = FALSE;
- pDM_Odm->adaptivity_flag = FALSE;
- return TRUE;
-
- } else if ((*pDM_Odm->pBandType != ODM_BAND_2_4G) && (*pDM_Odm->pBandType != ODM_BAND_5G)) {
- ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense neither 2G nor 5G band, return\n"));
- pDM_Odm->Adaptivity_enable = FALSE;
- pDM_Odm->adaptivity_flag = FALSE;
- return TRUE;
- }
- }
+ if (!(dm->support_ability & ODM_BB_ADAPTIVITY)) {
+ dm->adaptivity_enable = false;
+ return;
}
-
- return FALSE;
-
-}
-#endif
-
-VOID
-Phydm_NHMCounterStatisticsInit(
- IN PVOID pDM_VOID
-)
-{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
-
- if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
- /*PHY parameters initialize for n series*/
- ODM_Write2Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11N+ 2, 0xC350); /*0x894[31:16]=0x0xC350 Time duration for NHM unit: us, 0xc350=200ms*/
- ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N + 2, 0xffff); /*0x890[31:16]=0xffff th_9, th_10*/
- ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0xffffff50); /*0x898=0xffffff52 th_3, th_2, th_1, th_0*/
- ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffffff); /*0x89c=0xffffffff th_7, th_6, th_5, th_4*/
- ODM_SetBBReg(pDM_Odm, ODM_REG_FPGA0_IQK_11N, bMaskByte0, 0xff); /*0xe28[7:0]=0xff th_8*/
- ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10 | BIT9 | BIT8, 0x1); /*0x890[10:8]=1 ignoreCCA ignore PHYTXON enable CCX*/
- ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT7, 0x1); /*0xc0c[7]=1 max power among all RX ants*/
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+ if (dm->ap_total_num > adaptivity->ap_num_th) {
+ dm->adaptivity_enable = false;
+ PHYDM_DBG(dm, DBG_ADPTVTY, "AP total num > %d!!, disable adaptivity\n", adaptivity->ap_num_th);
+ return;
}
-#if (RTL8195A_SUPPORT == 0)
- else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
- /*PHY parameters initialize for ac series*/
- ODM_Write2Byte(pDM_Odm, ODM_REG_CCX_PERIOD_11AC+ 2, 0xC350); /*0x990[31:16]=0xC350 Time duration for NHM unit: us, 0xc350=200ms*/
- ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC + 2, 0xffff); /*0x994[31:16]=0xffff th_9, th_10*/
- ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0xffffff50); /*0x998=0xffffff52 th_3, th_2, th_1, th_0*/
- ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffffff); /*0x99c=0xffffffff th_7, th_6, th_5, th_4*/
- ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11AC, bMaskByte0, 0xff); /*0x9a0[7:0]=0xff th_8*/
- ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT8 | BIT9 | BIT10, 0x1); /*0x994[10:8]=1 ignoreCCA ignore PHYTXON enable CCX*/
- ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_9E8_11AC, BIT0, 0x1); /*0x9e8[7]=1 max power among all RX ants*/
+#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
+ if (adaptivity->dynamic_link_adaptivity) {
+ if (dm->is_linked && adaptivity->is_check == false) {
+ phydm_check_environment(dm);
+ } else if (!dm->is_linked)
+ adaptivity->is_check = false;
+ return;
}
#endif
+
+ dm->adaptivity_enable = true;
}
-VOID
-Phydm_NHMCounterStatistics(
- IN PVOID pDM_VOID
-)
-{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
-
- if (!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT))
- return;
-
- /*Get NHM report*/
- Phydm_GetNHMCounterStatistics(pDM_Odm);
-
- /*Reset NHM counter*/
- Phydm_NHMCounterStatisticsReset(pDM_Odm);
-}
-
-VOID
-Phydm_GetNHMCounterStatistics(
- IN PVOID pDM_VOID
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+boolean
+phydm_check_channel_plan(
+ void *dm_void
)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- u4Byte value32 = 0;
-#if (RTL8195A_SUPPORT == 0)
- if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
- value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_CNT_11AC, bMaskDWord);
- else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
-#endif
- value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_CNT_11N, bMaskDWord);
-
- pDM_Odm->NHM_cnt_0 = (u1Byte)(value32 & bMaskByte0);
- pDM_Odm->NHM_cnt_1 = (u1Byte)((value32 & bMaskByte1) >> 8);
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ void *adapter = dm->adapter;
+ PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;
+
+ if (mgnt_info->RegEnableAdaptivity == 2) {
+ if (dm->carrier_sense_enable == false) { /*check domain Code for adaptivity or CarrierSense*/
+ if ((*dm->band_type == ODM_BAND_5G) &&
+ !(dm->odm_regulation_5g == REGULATION_ETSI || dm->odm_regulation_5g == REGULATION_WW)) {
+ PHYDM_DBG(dm, DBG_ADPTVTY, "adaptivity skip 5G domain code : %d\n", dm->odm_regulation_5g);
+ dm->adaptivity_enable = false;
+ return true;
+ } else if ((*dm->band_type == ODM_BAND_2_4G) &&
+ !(dm->odm_regulation_2_4g == REGULATION_ETSI || dm->odm_regulation_2_4g == REGULATION_WW)) {
+ PHYDM_DBG(dm, DBG_ADPTVTY, "adaptivity skip 2.4G domain code : %d\n", dm->odm_regulation_2_4g);
+ dm->adaptivity_enable = false;
+ return true;
+
+ } else if ((*dm->band_type != ODM_BAND_2_4G) && (*dm->band_type != ODM_BAND_5G)) {
+ PHYDM_DBG(dm, DBG_ADPTVTY, "adaptivity neither 2G nor 5G band, return\n");
+ dm->adaptivity_enable = false;
+ return true;
+ }
+ } else {
+ if ((*dm->band_type == ODM_BAND_5G) &&
+ !(dm->odm_regulation_5g == REGULATION_MKK || dm->odm_regulation_5g == REGULATION_WW)) {
+ PHYDM_DBG(dm, DBG_ADPTVTY, "CarrierSense skip 5G domain code : %d\n", dm->odm_regulation_5g);
+ dm->adaptivity_enable = false;
+ return true;
+ }
-}
+ else if ((*dm->band_type == ODM_BAND_2_4G) &&
+ !(dm->odm_regulation_2_4g == REGULATION_MKK || dm->odm_regulation_2_4g == REGULATION_WW)) {
+ PHYDM_DBG(dm, DBG_ADPTVTY, "CarrierSense skip 2.4G domain code : %d\n", dm->odm_regulation_2_4g);
+ dm->adaptivity_enable = false;
+ return true;
-VOID
-Phydm_NHMCounterStatisticsReset(
- IN PVOID pDM_VOID
-)
-{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
-
- if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
- ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 0);
- ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 1);
- }
-#if (RTL8195A_SUPPORT == 0)
- else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
- ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 0);
- ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 1);
+ } else if ((*dm->band_type != ODM_BAND_2_4G) && (*dm->band_type != ODM_BAND_5G)) {
+ PHYDM_DBG(dm, DBG_ADPTVTY, "CarrierSense neither 2G nor 5G band, return\n");
+ dm->adaptivity_enable = false;
+ return true;
+ }
+ }
}
-#endif
+ return false;
}
+#endif
-VOID
-Phydm_SetEDCCAThreshold(
- IN PVOID pDM_VOID,
- IN s1Byte H2L,
- IN s1Byte L2H
+void
+phydm_set_edcca_threshold(
+ void *dm_void,
+ s8 H2L,
+ s8 L2H
)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
- if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
- ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskByte2|bMaskByte0, (u4Byte)((u1Byte)L2H|(u1Byte)H2L<<16));
+ if (dm->support_ic_type & ODM_IC_11N_SERIES)
+ odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, MASKBYTE2 | MASKBYTE0, (u32)((u8)L2H | (u8)H2L << 16));
#if (RTL8195A_SUPPORT == 0)
- else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
- ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, bMaskLWord, (u2Byte)((u1Byte)L2H|(u1Byte)H2L<<8));
+ else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
+ odm_set_bb_reg(dm, REG_FPGA0_XB_LSSI_READ_BACK, MASKLWORD, (u16)((u8)L2H | (u8)H2L << 8));
#endif
}
-VOID
-Phydm_SetLNA(
- IN PVOID pDM_VOID,
- IN PhyDM_set_LNA type
+void
+phydm_set_lna(
+ void *dm_void,
+ enum phydm_set_lna type
)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
-
- if (pDM_Odm->SupportICType & (ODM_RTL8188E | ODM_RTL8192E)) {
- if (type == PhyDM_disable_LNA) {
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0000f);
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0x37f82); /*disable LNA*/
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
- if (pDM_Odm->RFType > ODM_1T1R) {
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1);
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000);
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x0000f);
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0x37f82);
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0);
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+ if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8192E)) {
+ if (type == phydm_disable_lna) {
+ odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x1);
+ odm_set_rf_reg(dm, RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
+ odm_set_rf_reg(dm, RF_PATH_A, 0x31, 0xfffff, 0x0000f);
+ odm_set_rf_reg(dm, RF_PATH_A, 0x32, 0xfffff, 0x37f82); /*disable LNA*/
+ odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x0);
+ if (dm->rf_type > RF_1T1R) {
+ odm_set_rf_reg(dm, RF_PATH_B, 0xef, 0x80000, 0x1);
+ odm_set_rf_reg(dm, RF_PATH_B, 0x30, 0xfffff, 0x18000);
+ odm_set_rf_reg(dm, RF_PATH_B, 0x31, 0xfffff, 0x0000f);
+ odm_set_rf_reg(dm, RF_PATH_B, 0x32, 0xfffff, 0x37f82);
+ odm_set_rf_reg(dm, RF_PATH_B, 0xef, 0x80000, 0x0);
}
- } else if (type == PhyDM_enable_LNA) {
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0000f);
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0x77f82); /*back to normal*/
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
- if (pDM_Odm->RFType > ODM_1T1R) {
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1);
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000);
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x0000f);
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0x77f82);
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0);
+ } else if (type == phydm_enable_lna) {
+ odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x1);
+ odm_set_rf_reg(dm, RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
+ odm_set_rf_reg(dm, RF_PATH_A, 0x31, 0xfffff, 0x0000f);
+ odm_set_rf_reg(dm, RF_PATH_A, 0x32, 0xfffff, 0x77f82); /*back to normal*/
+ odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x0);
+ if (dm->rf_type > RF_1T1R) {
+ odm_set_rf_reg(dm, RF_PATH_B, 0xef, 0x80000, 0x1);
+ odm_set_rf_reg(dm, RF_PATH_B, 0x30, 0xfffff, 0x18000);
+ odm_set_rf_reg(dm, RF_PATH_B, 0x31, 0xfffff, 0x0000f);
+ odm_set_rf_reg(dm, RF_PATH_B, 0x32, 0xfffff, 0x77f82);
+ odm_set_rf_reg(dm, RF_PATH_B, 0xef, 0x80000, 0x0);
}
}
- } else if (pDM_Odm->SupportICType & ODM_RTL8723B) {
- if (type == PhyDM_disable_LNA) {
+ } else if (dm->support_ic_type & ODM_RTL8723B) {
+ if (type == phydm_disable_lna) {
/*S0*/
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0001f);
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xe6137); /*disable LNA*/
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
+ odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x1);
+ odm_set_rf_reg(dm, RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
+ odm_set_rf_reg(dm, RF_PATH_A, 0x31, 0xfffff, 0x0001f);
+ odm_set_rf_reg(dm, RF_PATH_A, 0x32, 0xfffff, 0xe6137); /*disable LNA*/
+ odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x0);
/*S1*/
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x1);
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, 0xfffff, 0x3008d); /*select Rx mode and disable LNA*/
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x0);
- } else if (type == PhyDM_enable_LNA) {
+ odm_set_rf_reg(dm, RF_PATH_A, 0xed, 0x00020, 0x1);
+ odm_set_rf_reg(dm, RF_PATH_A, 0x43, 0xfffff, 0x3008d); /*select Rx mode and disable LNA*/
+ odm_set_rf_reg(dm, RF_PATH_A, 0xed, 0x00020, 0x0);
+ } else if (type == phydm_enable_lna) {
/*S0*/
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0001f);
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xe6177); /*disable LNA*/
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
+ odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x1);
+ odm_set_rf_reg(dm, RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
+ odm_set_rf_reg(dm, RF_PATH_A, 0x31, 0xfffff, 0x0001f);
+ odm_set_rf_reg(dm, RF_PATH_A, 0x32, 0xfffff, 0xe6177); /*disable LNA*/
+ odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x0);
/*S1*/
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x1);
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, 0xfffff, 0x300bd); /*select Rx mode and disable LNA*/
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x0);
+ odm_set_rf_reg(dm, RF_PATH_A, 0xed, 0x00020, 0x1);
+ odm_set_rf_reg(dm, RF_PATH_A, 0x43, 0xfffff, 0x300bd); /*select Rx mode and disable LNA*/
+ odm_set_rf_reg(dm, RF_PATH_A, 0xed, 0x00020, 0x0);
}
-
- } else if (pDM_Odm->SupportICType & ODM_RTL8812) {
- if (type == PhyDM_disable_LNA) {
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x3f7ff);
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xc22bf); /*disable LNA*/
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
- if (pDM_Odm->RFType > ODM_1T1R) {
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1);
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x3f7ff);
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0xc22bf); /*disable LNA*/
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0);
- }
- } else if (type == PhyDM_enable_LNA) {
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x3f7ff);
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xc26bf); /*disable LNA*/
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
- if (pDM_Odm->RFType > ODM_1T1R) {
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1);
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x3f7ff);
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0xc26bf); /*disable LNA*/
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0);
- }
+
+ } else if (dm->support_ic_type & ODM_RTL8812) {
+ if (type == phydm_disable_lna) {
+ odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x1);
+ odm_set_rf_reg(dm, RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
+ odm_set_rf_reg(dm, RF_PATH_A, 0x31, 0xfffff, 0x3f7ff);
+ odm_set_rf_reg(dm, RF_PATH_A, 0x32, 0xfffff, 0xc22bf); /*disable LNA*/
+ odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x0);
+ if (dm->rf_type > RF_1T1R) {
+ odm_set_rf_reg(dm, RF_PATH_B, 0xef, 0x80000, 0x1);
+ odm_set_rf_reg(dm, RF_PATH_B, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
+ odm_set_rf_reg(dm, RF_PATH_B, 0x31, 0xfffff, 0x3f7ff);
+ odm_set_rf_reg(dm, RF_PATH_B, 0x32, 0xfffff, 0xc22bf); /*disable LNA*/
+ odm_set_rf_reg(dm, RF_PATH_B, 0xef, 0x80000, 0x0);
+ }
+ } else if (type == phydm_enable_lna) {
+ odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x1);
+ odm_set_rf_reg(dm, RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
+ odm_set_rf_reg(dm, RF_PATH_A, 0x31, 0xfffff, 0x3f7ff);
+ odm_set_rf_reg(dm, RF_PATH_A, 0x32, 0xfffff, 0xc26bf); /*disable LNA*/
+ odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x0);
+ if (dm->rf_type > RF_1T1R) {
+ odm_set_rf_reg(dm, RF_PATH_B, 0xef, 0x80000, 0x1);
+ odm_set_rf_reg(dm, RF_PATH_B, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
+ odm_set_rf_reg(dm, RF_PATH_B, 0x31, 0xfffff, 0x3f7ff);
+ odm_set_rf_reg(dm, RF_PATH_B, 0x32, 0xfffff, 0xc26bf); /*disable LNA*/
+ odm_set_rf_reg(dm, RF_PATH_B, 0xef, 0x80000, 0x0);
+ }
}
- } else if (pDM_Odm->SupportICType & (ODM_RTL8821 | ODM_RTL8881A)) {
- if (type == PhyDM_disable_LNA) {
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0002f);
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xfb09b); /*disable LNA*/
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
- } else if (type == PhyDM_enable_LNA) {
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0002f);
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xfb0bb); /*disable LNA*/
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
+ } else if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A)) {
+ if (type == phydm_disable_lna) {
+ odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x1);
+ odm_set_rf_reg(dm, RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
+ odm_set_rf_reg(dm, RF_PATH_A, 0x31, 0xfffff, 0x0002f);
+ odm_set_rf_reg(dm, RF_PATH_A, 0x32, 0xfffff, 0xfb09b); /*disable LNA*/
+ odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x0);
+ } else if (type == phydm_enable_lna) {
+ odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x1);
+ odm_set_rf_reg(dm, RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
+ odm_set_rf_reg(dm, RF_PATH_A, 0x31, 0xfffff, 0x0002f);
+ odm_set_rf_reg(dm, RF_PATH_A, 0x32, 0xfffff, 0xfb0bb); /*disable LNA*/
+ odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x0);
}
}
}
-VOID
-Phydm_SetTRxMux(
- IN PVOID pDM_VOID,
- IN PhyDM_Trx_MUX_Type txMode,
- IN PhyDM_Trx_MUX_Type rxMode
+void
+phydm_set_trx_mux(
+ void *dm_void,
+ enum phydm_trx_mux_type tx_mode,
+ enum phydm_trx_mux_type rx_mode
)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
-
- if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
- ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT3 | BIT2 | BIT1, txMode); /*set TXmod to standby mode to remove outside noise affect*/
- ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT22 | BIT21 | BIT20, rxMode); /*set RXmod to standby mode to remove outside noise affect*/
- if (pDM_Odm->RFType > ODM_1T1R) {
- ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT3 | BIT2 | BIT1, txMode); /*set TXmod to standby mode to remove outside noise affect*/
- ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT22 | BIT21 | BIT20, rxMode); /*set RXmod to standby mode to remove outside noise affect*/
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+ if (dm->support_ic_type & ODM_IC_11N_SERIES) {
+ odm_set_bb_reg(dm, ODM_REG_CCK_RPT_FORMAT_11N, BIT(3) | BIT(2) | BIT(1), tx_mode); /*set TXmod to standby mode to remove outside noise affect*/
+ odm_set_bb_reg(dm, ODM_REG_CCK_RPT_FORMAT_11N, BIT(22) | BIT(21) | BIT(20), rx_mode); /*set RXmod to standby mode to remove outside noise affect*/
+ if (dm->rf_type > RF_1T1R) {
+ odm_set_bb_reg(dm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT(3) | BIT(2) | BIT(1), tx_mode); /*set TXmod to standby mode to remove outside noise affect*/
+ odm_set_bb_reg(dm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT(22) | BIT(21) | BIT(20), rx_mode); /*set RXmod to standby mode to remove outside noise affect*/
}
}
#if (RTL8195A_SUPPORT == 0)
- else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
- ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC, BIT11 | BIT10 | BIT9 | BIT8, txMode); /*set TXmod to standby mode to remove outside noise affect*/
- ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC, BIT7 | BIT6 | BIT5 | BIT4, rxMode); /*set RXmod to standby mode to remove outside noise affect*/
- if (pDM_Odm->RFType > ODM_1T1R) {
- ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC_B, BIT11 | BIT10 | BIT9 | BIT8, txMode); /*set TXmod to standby mode to remove outside noise affect*/
- ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC_B, BIT7 | BIT6 | BIT5 | BIT4, rxMode); /*set RXmod to standby mode to remove outside noise affect*/
+ else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+ odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, BIT(11) | BIT(10) | BIT(9) | BIT(8), tx_mode); /*set TXmod to standby mode to remove outside noise affect*/
+ odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, BIT(7) | BIT(6) | BIT(5) | BIT(4), rx_mode); /*set RXmod to standby mode to remove outside noise affect*/
+ if (dm->rf_type > RF_1T1R) {
+ odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC_B, BIT(11) | BIT(10) | BIT(9) | BIT(8), tx_mode); /*set TXmod to standby mode to remove outside noise affect*/
+ odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC_B, BIT(7) | BIT(6) | BIT(5) | BIT(4), rx_mode); /*set RXmod to standby mode to remove outside noise affect*/
}
}
#endif
}
-VOID
-Phydm_MACEDCCAState(
- IN PVOID pDM_VOID,
- IN PhyDM_MACEDCCA_Type State
+void
+phydm_mac_edcca_state(
+ void *dm_void,
+ enum phydm_mac_edcca_type state
)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- if (State == PhyDM_IGNORE_EDCCA) {
- ODM_SetMACReg(pDM_Odm, REG_TX_PTCL_CTRL, BIT15, 1); /*ignore EDCCA reg520[15]=1*/
-/* ODM_SetMACReg(pDM_Odm, REG_RD_CTRL, BIT11, 0); *//*reg524[11]=0*/
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ if (state == phydm_ignore_edcca) {
+ odm_set_mac_reg(dm, REG_TX_PTCL_CTRL, BIT(15), 1); /*ignore EDCCA reg520[15]=1*/
+ /* odm_set_mac_reg(dm, REG_RD_CTRL, BIT(11), 0); */ /*reg524[11]=0*/
} else { /*don't set MAC ignore EDCCA signal*/
- ODM_SetMACReg(pDM_Odm, REG_TX_PTCL_CTRL, BIT15, 0); /*don't ignore EDCCA reg520[15]=0*/
-/* ODM_SetMACReg(pDM_Odm, REG_RD_CTRL, BIT11, 1); *//*reg524[11]=1 */
+ odm_set_mac_reg(dm, REG_TX_PTCL_CTRL, BIT(15), 0); /*don't ignore EDCCA reg520[15]=0*/
+ /* odm_set_mac_reg(dm, REG_RD_CTRL, BIT(11), 1); */ /*reg524[11]=1 */
}
- ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("EDCCA enable State = %d\n", State));
+ PHYDM_DBG(dm, DBG_ADPTVTY, "EDCCA enable state = %d\n", state);
}
-BOOLEAN
-Phydm_CalNHMcnt(
- IN PVOID pDM_VOID
+void
+phydm_search_pwdb_lower_bound(
+ void *dm_void
)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- u2Byte Base = 0;
-
- Base = pDM_Odm->NHM_cnt_0 + pDM_Odm->NHM_cnt_1;
-
- if (Base != 0) {
- pDM_Odm->NHM_cnt_0 = ((pDM_Odm->NHM_cnt_0) << 8) / Base;
- pDM_Odm->NHM_cnt_1 = ((pDM_Odm->NHM_cnt_1) << 8) / Base;
- }
- if ((pDM_Odm->NHM_cnt_0 - pDM_Odm->NHM_cnt_1) >= 100)
- return TRUE; /*clean environment*/
- else
- return FALSE; /*noisy environment*/
-
-}
-
-
-VOID
-Phydm_CheckEnvironment(
- IN PVOID pDM_VOID
-)
-{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);
- BOOLEAN isCleanEnvironment = FALSE;
-#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
- prtl8192cd_priv priv = pDM_Odm->priv;
-#endif
-
- if (Adaptivity->bFirstLink == TRUE) {
- if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))
- pDM_Odm->adaptivity_flag = FALSE;
- else
- pDM_Odm->adaptivity_flag = TRUE;
-
- Adaptivity->bFirstLink = FALSE;
- return;
- } else {
- if (Adaptivity->NHMWait < 3) { /*Start enter NHM after 4 NHMWait*/
- Adaptivity->NHMWait++;
- Phydm_NHMCounterStatistics(pDM_Odm);
- return;
- } else {
- Phydm_NHMCounterStatistics(pDM_Odm);
- isCleanEnvironment = Phydm_CalNHMcnt(pDM_Odm);
- if (isCleanEnvironment == TRUE) {
- pDM_Odm->TH_L2H_ini = Adaptivity->TH_L2H_ini_backup; /*adaptivity mode*/
- pDM_Odm->TH_EDCCA_HL_diff = Adaptivity->TH_EDCCA_HL_diff_backup;
-
- pDM_Odm->Adaptivity_enable = TRUE;
-
- if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))
- pDM_Odm->adaptivity_flag = FALSE;
- else
- pDM_Odm->adaptivity_flag = TRUE;
-#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
- priv->pshare->rf_ft_var.isCleanEnvironment = TRUE;
-#endif
- } else {
- if (!Adaptivity->AcsForAdaptivity) {
- pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_mode2; /*mode2*/
- pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_mode2;
-
- pDM_Odm->adaptivity_flag = FALSE;
- pDM_Odm->Adaptivity_enable = FALSE;
- }
-#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
- priv->pshare->rf_ft_var.isCleanEnvironment = FALSE;
-#endif
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct phydm_adaptivity_struct *adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(dm, PHYDM_ADAPTIVITY);
+ u32 value32 = 0, reg_value32 = 0;
+ u8 cnt, try_count = 0;
+ u8 tx_edcca1 = 0;
+ boolean is_adjust = true;
+ s8 th_l2h_dmc, th_h2l_dmc, igi_target = 0x32;
+ s8 diff;
+ u8 IGI = adaptivity->igi_base + 30 + (u8)dm->th_l2h_ini - (u8)dm->th_edcca_hl_diff;
+
+ if (dm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A))
+ phydm_set_lna(dm, phydm_disable_lna);
+
+ diff = igi_target - (s8)IGI;
+ th_l2h_dmc = dm->th_l2h_ini + diff;
+ if (th_l2h_dmc > 10)
+ th_l2h_dmc = 10;
+
+ th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
+ phydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc);
+ ODM_delay_ms(30);
+
+ while (is_adjust) {
+ /*check CCA status*/
+ if (phydm_set_bb_dbg_port(dm, BB_DBGPORT_PRIORITY_1, 0x0)) {/*set debug port to 0x0*/
+ reg_value32 = phydm_get_bb_dbg_port_value(dm);
+
+ while (reg_value32 & BIT(3) && try_count < 3) {
+ ODM_delay_ms(3);
+ try_count = try_count + 1;
+ reg_value32 = phydm_get_bb_dbg_port_value(dm);
}
- Adaptivity->NHMWait = 0;
- Adaptivity->bFirstLink = TRUE;
- Adaptivity->bCheck = TRUE;
+ phydm_release_bb_dbg_port(dm);
+ try_count = 0;
}
- }
-
-
-}
-
-VOID
-Phydm_SearchPwdBLowerBound(
- IN PVOID pDM_VOID
-)
-{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);
- u4Byte value32 = 0;
- u1Byte cnt;
- u1Byte txEdcca1 = 0, txEdcca0 = 0;
- BOOLEAN bAdjust = TRUE;
- s1Byte TH_L2H_dmc, TH_H2L_dmc, IGI_target = 0x32;
- s1Byte Diff;
- u1Byte IGI = Adaptivity->IGI_Base + 30 + (u1Byte)pDM_Odm->TH_L2H_ini - (u1Byte)pDM_Odm->TH_EDCCA_HL_diff;
-
- if (pDM_Odm->SupportICType & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A))
- Phydm_SetLNA(pDM_Odm, PhyDM_disable_LNA);
- else {
- Phydm_SetTRxMux(pDM_Odm, PhyDM_STANDBY_MODE, PhyDM_STANDBY_MODE);
- odm_PauseDIG(pDM_Odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_0, 0x7e);
- }
-
- Diff = IGI_target - (s1Byte)IGI;
- TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff;
- if (TH_L2H_dmc > 10)
- TH_L2H_dmc = 10;
- TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
-
- Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);
- ODM_delay_ms(5);
-
- while (bAdjust) {
+ /*count EDCCA signal = 1 times*/
for (cnt = 0; cnt < 20; cnt++) {
- if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
- value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11N, bMaskDWord);
-#if (RTL8195A_SUPPORT == 0)
- else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
- value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC, bMaskDWord);
-#endif
- if (value32 & BIT30 && (pDM_Odm->SupportICType & (ODM_RTL8723B | ODM_RTL8188E)))
- txEdcca1 = txEdcca1 + 1;
- else if (value32 & BIT29)
- txEdcca1 = txEdcca1 + 1;
- else
- txEdcca0 = txEdcca0 + 1;
+ if (phydm_set_bb_dbg_port(dm, BB_DBGPORT_PRIORITY_1, adaptivity->adaptivity_dbg_port)) {
+ value32 = phydm_get_bb_dbg_port_value(dm);
+ phydm_release_bb_dbg_port(dm);
+ }
+
+ if (value32 & BIT(30) && (dm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E)))
+ tx_edcca1 = tx_edcca1 + 1;
+ else if (value32 & BIT(29))
+ tx_edcca1 = tx_edcca1 + 1;
}
- if (txEdcca1 > 1) {
+ if (tx_edcca1 > 1) {
IGI = IGI - 1;
- TH_L2H_dmc = TH_L2H_dmc + 1;
- if (TH_L2H_dmc > 10)
- TH_L2H_dmc = 10;
- TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
-
- Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);
- if (TH_L2H_dmc == 10) {
- bAdjust = FALSE;
- Adaptivity->H2L_lb = TH_H2L_dmc;
- Adaptivity->L2H_lb = TH_L2H_dmc;
- pDM_Odm->Adaptivity_IGI_upper = IGI;
- }
+ th_l2h_dmc = th_l2h_dmc + 1;
+ if (th_l2h_dmc > 10)
+ th_l2h_dmc = 10;
- txEdcca1 = 0;
- txEdcca0 = 0;
+ th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
+ phydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc);
+ tx_edcca1 = 0;
+ if (th_l2h_dmc == 10)
+ is_adjust = false;
+
+ } else
+ is_adjust = false;
- } else {
- bAdjust = FALSE;
- Adaptivity->H2L_lb = TH_H2L_dmc;
- Adaptivity->L2H_lb = TH_L2H_dmc;
- pDM_Odm->Adaptivity_IGI_upper = IGI;
- txEdcca1 = 0;
- txEdcca0 = 0;
- }
}
- pDM_Odm->Adaptivity_IGI_upper = pDM_Odm->Adaptivity_IGI_upper - pDM_Odm->DCbackoff;
- Adaptivity->H2L_lb = Adaptivity->H2L_lb + pDM_Odm->DCbackoff;
- Adaptivity->L2H_lb = Adaptivity->L2H_lb + pDM_Odm->DCbackoff;
+ adaptivity->adapt_igi_up = IGI - dm->dc_backoff;
+ adaptivity->h2l_lb = th_h2l_dmc + dm->dc_backoff;
+ adaptivity->l2h_lb = th_l2h_dmc + dm->dc_backoff;
- if (pDM_Odm->SupportICType & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A))
- Phydm_SetLNA(pDM_Odm, PhyDM_enable_LNA);
- else {
- Phydm_SetTRxMux(pDM_Odm, PhyDM_TX_MODE, PhyDM_RX_MODE);
- odm_PauseDIG(pDM_Odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_0, NONE);
- }
-
- Phydm_SetEDCCAThreshold(pDM_Odm, 0x7f, 0x7f); /*resume to no link state*/
+ if (dm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A))
+ phydm_set_lna(dm, phydm_enable_lna);
+
+ phydm_set_edcca_threshold(dm, 0x7f, 0x7f); /*resume to no link state*/
}
-BOOLEAN
-phydm_reSearchCondition(
- IN PVOID pDM_VOID
+boolean
+phydm_re_search_condition(
+ void *dm_void
)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- /*PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);*/
- u1Byte Adaptivity_IGI_upper;
- /*s1Byte TH_L2H_dmc, IGI_target = 0x32;*/
- /*s1Byte Diff;*/
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct phydm_adaptivity_struct *adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(dm, PHYDM_ADAPTIVITY);
+ u8 adaptivity_igi_upper = adaptivity->adapt_igi_up + dm->dc_backoff;
+ /*s8 TH_L2H_dmc, IGI_target = 0x32;*/
+ /*s8 diff;*/
- Adaptivity_IGI_upper = pDM_Odm->Adaptivity_IGI_upper + pDM_Odm->DCbackoff;
-
/*TH_L2H_dmc = 10;*/
- /*Diff = TH_L2H_dmc - pDM_Odm->TH_L2H_ini;*/
- /*lowest_IGI_upper = IGI_target - Diff;*/
+ /*diff = TH_L2H_dmc - dm->TH_L2H_ini;*/
+ /*lowest_IGI_upper = IGI_target - diff;*/
+ /*if ((adaptivity_igi_upper - lowest_IGI_upper) <= 5)*/
- /*if ((Adaptivity_IGI_upper - lowest_IGI_upper) <= 5)*/
- if (Adaptivity_IGI_upper <= 0x26)
- return TRUE;
+ if (adaptivity_igi_upper <= 0x26)
+ return true;
else
- return FALSE;
-
+ return false;
}
-VOID
-phydm_adaptivityInfoInit(
- IN PVOID pDM_VOID,
- IN PHYDM_ADAPINFO_E CmnInfo,
- IN u4Byte Value
- )
+void
+phydm_adaptivity_info_init(
+ void *dm_void,
+ enum phydm_adapinfo cmn_info,
+ u32 value
+)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct phydm_adaptivity_struct *adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(dm, PHYDM_ADAPTIVITY);
- switch (CmnInfo) {
+ switch (cmn_info) {
case PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE:
- pDM_Odm->Carrier_Sense_enable = (BOOLEAN)Value;
- break;
+ dm->carrier_sense_enable = (boolean)value;
+ break;
case PHYDM_ADAPINFO_DCBACKOFF:
- pDM_Odm->DCbackoff = (u1Byte)Value;
- break;
+ dm->dc_backoff = (u8)value;
+ break;
case PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY:
- Adaptivity->DynamicLinkAdaptivity = (BOOLEAN)Value;
- break;
+ adaptivity->dynamic_link_adaptivity = (boolean)value;
+ break;
case PHYDM_ADAPINFO_TH_L2H_INI:
- pDM_Odm->TH_L2H_ini = (s1Byte)Value;
- break;
+ dm->th_l2h_ini = (s8)value;
+ break;
case PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF:
- pDM_Odm->TH_EDCCA_HL_diff = (s1Byte)Value;
- break;
+ dm->th_edcca_hl_diff = (s8)value;
+ break;
case PHYDM_ADAPINFO_AP_NUM_TH:
- Adaptivity->APNumTH = (u1Byte)Value;
- break;
+ adaptivity->ap_num_th = (u8)value;
+ break;
default:
- break;
-
+ break;
+
}
}
-
-
-VOID
-Phydm_AdaptivityInit(
- IN PVOID pDM_VOID
+void
+phydm_adaptivity_init(
+ void *dm_void
)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);
- s1Byte IGItarget = 0x32;
- /*pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;*/
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct phydm_adaptivity_struct *adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(dm, PHYDM_ADAPTIVITY);
+ s8 igi_target = 0x32;
+ /*struct phydm_dig_struct* dig_t = &dm->dm_dig_table;*/
-#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN))
- if (pDM_Odm->Carrier_Sense_enable == FALSE) {
- if (pDM_Odm->TH_L2H_ini == 0)
- pDM_Odm->TH_L2H_ini = 0xf5;
+ if (dm->carrier_sense_enable == false) {
+ if (dm->th_l2h_ini == 0)
+ phydm_set_l2h_th_ini(dm);
} else
- pDM_Odm->TH_L2H_ini = 0xa;
+ dm->th_l2h_ini = 0xa;
- if (pDM_Odm->TH_EDCCA_HL_diff == 0)
- pDM_Odm->TH_EDCCA_HL_diff = 7;
-#if(DM_ODM_SUPPORT_TYPE & (ODM_CE))
- if (pDM_Odm->WIFITest == TRUE || pDM_Odm->mp_mode == TRUE)
+ if (dm->th_edcca_hl_diff == 0)
+ dm->th_edcca_hl_diff = 7;
+#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
+ if (dm->wifi_test == true || *dm->mp_mode == true)
#else
- if ((pDM_Odm->WIFITest & RT_WIFI_LOGO) == TRUE)
+ if ((dm->wifi_test & RT_WIFI_LOGO) == true)
#endif
- pDM_Odm->EDCCA_enable = FALSE; /*even no adaptivity, we still enable EDCCA, AP side use mib control*/
+ dm->edcca_enable = false; /*even no adaptivity, we still enable EDCCA, AP side use mib control*/
else
- pDM_Odm->EDCCA_enable = TRUE;
+ dm->edcca_enable = true;
#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
- prtl8192cd_priv priv = pDM_Odm->priv;
+ struct rtl8192cd_priv *priv = dm->priv;
- if (pDM_Odm->Carrier_Sense_enable) {
- pDM_Odm->TH_L2H_ini = 0xa;
- pDM_Odm->TH_EDCCA_HL_diff = 7;
+ if (dm->carrier_sense_enable) {
+ dm->th_l2h_ini = 0xa;
+ dm->th_edcca_hl_diff = 7;
} else {
- pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_default; /*set by mib*/
- pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_default;
+ dm->th_l2h_ini = dm->TH_L2H_default; /*set by mib*/
+ dm->th_edcca_hl_diff = dm->th_edcca_hl_diff_default;
}
- if (priv->pshare->rf_ft_var.adaptivity_enable == 3)
- Adaptivity->AcsForAdaptivity = TRUE;
- else
- Adaptivity->AcsForAdaptivity = FALSE;
-
if (priv->pshare->rf_ft_var.adaptivity_enable == 2)
- Adaptivity->DynamicLinkAdaptivity = TRUE;
+ adaptivity->dynamic_link_adaptivity = true;
else
- Adaptivity->DynamicLinkAdaptivity = FALSE;
-
- priv->pshare->rf_ft_var.isCleanEnvironment = FALSE;
-
-#endif
-
- pDM_Odm->Adaptivity_IGI_upper = 0;
- pDM_Odm->Adaptivity_enable = FALSE; /*use this flag to decide enable or disable*/
-
- pDM_Odm->TH_L2H_ini_mode2 = 20;
- pDM_Odm->TH_EDCCA_HL_diff_mode2 = 8;
- Adaptivity->TH_L2H_ini_backup = pDM_Odm->TH_L2H_ini;
- Adaptivity->TH_EDCCA_HL_diff_backup = pDM_Odm->TH_EDCCA_HL_diff;
-
- Adaptivity->IGI_Base = 0x32;
- Adaptivity->IGI_target = 0x1c;
- Adaptivity->H2L_lb = 0;
- Adaptivity->L2H_lb = 0;
- Adaptivity->NHMWait = 0;
- Adaptivity->bCheck = FALSE;
- Adaptivity->bFirstLink = TRUE;
- Adaptivity->AdajustIGILevel = 0;
- Adaptivity->bStopEDCCA = FALSE;
- Adaptivity->backupH2L = 0;
- Adaptivity->backupL2H = 0;
-
- Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);
-
- /*Search pwdB lower bound*/
- if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
- ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11N, bMaskDWord, 0x208);
-#if (RTL8195A_SUPPORT == 0)
- else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
- ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC, bMaskDWord, 0x209);
-#endif
-
- if (pDM_Odm->SupportICType & ODM_IC_11N_GAIN_IDX_EDCCA) {
- /*ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_DOWN_OPT_11N, BIT12 | BIT11 | BIT10, 0x7);*/ /*interfernce need > 2^x us, and then EDCCA will be 1*/
- if (pDM_Odm->SupportICType & ODM_RTL8197F) {
- ODM_SetBBReg(pDM_Odm, ODM_REG_PAGE_B1_97F, BIT30, 0x1); /*set to page B1*/
- ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_DCNF_97F, BIT27 | BIT26, 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
- ODM_SetBBReg(pDM_Odm, ODM_REG_PAGE_B1_97F, BIT30, 0x0);
+ adaptivity->dynamic_link_adaptivity = false;
+
+#endif
+
+ adaptivity->adapt_igi_up = 0;
+ dm->adaptivity_enable = false; /*use this flag to decide enable or disable*/
+
+ dm->th_l2h_ini_mode2 = 20;
+ dm->th_edcca_hl_diff_mode2 = 8;
+ adaptivity->debug_mode = false;
+ adaptivity->th_l2h_ini_backup = dm->th_l2h_ini;
+ adaptivity->th_edcca_hl_diff_backup = dm->th_edcca_hl_diff;
+
+ adaptivity->igi_base = 0x32;
+ adaptivity->igi_target = 0x1c;
+ adaptivity->h2l_lb = 0;
+ adaptivity->l2h_lb = 0;
+ adaptivity->is_check = false;
+ adaptivity->adajust_igi_level = 0;
+ adaptivity->is_stop_edcca = false;
+ adaptivity->backup_h2l = 0;
+ adaptivity->backup_l2h = 0;
+ adaptivity->adaptivity_dbg_port = (dm->support_ic_type & ODM_IC_11N_SERIES) ? 0x208 : 0x209;
+
+ phydm_mac_edcca_state(dm, phydm_dont_ignore_edcca);
+
+ if (dm->support_ic_type & ODM_IC_11N_GAIN_IDX_EDCCA) {
+ /*odm_set_bb_reg(dm, ODM_REG_EDCCA_DOWN_OPT_11N, BIT(12) | BIT(11) | BIT(10), 0x7);*/ /*interfernce need > 2^x us, and then EDCCA will be 1*/
+ if (dm->support_ic_type & ODM_RTL8197F) {
+ odm_set_bb_reg(dm, ODM_REG_PAGE_B1_97F, BIT(30), 0x1); /*set to page B1*/
+ odm_set_bb_reg(dm, ODM_REG_EDCCA_DCNF_97F, BIT(27) | BIT(26), 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
+ odm_set_bb_reg(dm, ODM_REG_PAGE_B1_97F, BIT(30), 0x0);
} else
- ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_DCNF_11N, BIT21 | BIT20, 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
+ odm_set_bb_reg(dm, ODM_REG_EDCCA_DCNF_11N, BIT(21) | BIT(20), 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
}
#if (RTL8195A_SUPPORT == 0)
- if (pDM_Odm->SupportICType & ODM_IC_11AC_GAIN_IDX_EDCCA) { /*8814a no need to find pwdB lower bound, maybe*/
- /*ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_DOWN_OPT, BIT30 | BIT29 | BIT28, 0x7);*/ /*interfernce need > 2^x us, and then EDCCA will be 1*/
- ODM_SetBBReg(pDM_Odm, ODM_REG_ACBB_EDCCA_ENHANCE, BIT29 | BIT28, 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
+ if (dm->support_ic_type & ODM_IC_11AC_GAIN_IDX_EDCCA) { /*8814a no need to find pwdB lower bound, maybe*/
+ /*odm_set_bb_reg(dm, ODM_REG_EDCCA_DOWN_OPT, BIT(30) | BIT(29) | BIT(28), 0x7);*/ /*interfernce need > 2^x us, and then EDCCA will be 1*/
+ odm_set_bb_reg(dm, ODM_REG_ACBB_EDCCA_ENHANCE, BIT(29) | BIT(28), 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
}
- if (!(pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))) {
- Phydm_SearchPwdBLowerBound(pDM_Odm);
- if (phydm_reSearchCondition(pDM_Odm))
- Phydm_SearchPwdBLowerBound(pDM_Odm);
- }
+ if (!(dm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))) {
+ phydm_search_pwdb_lower_bound(dm);
+ if (phydm_re_search_condition(dm))
+ phydm_search_pwdb_lower_bound(dm);
+ } else
+ phydm_set_edcca_threshold(dm, 0x7f, 0x7f); /*resume to no link state*/
#endif
+ /*forgetting factor setting*/
+ phydm_set_forgetting_factor(dm);
-/*we need to consider PwdB upper bound for 8814 later IC*/
- Adaptivity->AdajustIGILevel = (u1Byte)((pDM_Odm->TH_L2H_ini + IGItarget) - PwdBUpperBound + DFIRloss); /*IGI = L2H - PwdB - DFIRloss*/
+ /*pwdb mode setting with 0: mean, 1:max*/
+ phydm_set_pwdb_mode(dm);
- ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("TH_L2H_ini = 0x%x, TH_EDCCA_HL_diff = 0x%x, Adaptivity->AdajustIGILevel = 0x%x\n", pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff, Adaptivity->AdajustIGILevel));
+ /*we need to consider PwdB upper bound for 8814 later IC*/
+ adaptivity->adajust_igi_level = (u8)((dm->th_l2h_ini + igi_target) - pwdb_upper_bound + dfir_loss); /*IGI = L2H - PwdB - dfir_loss*/
/*Check this later on Windows*/
- /*phydm_setEDCCAThresholdAPI(pDM_Odm, pDM_DigTable->CurIGValue);*/
+ /*phydm_set_edcca_threshold_api(dm, dig_t->cur_ig_value);*/
+
+ dm->adaptivity_flag = (dm->support_ic_type & ODM_IC_GAIN_IDX_EDCCA) ? false : true;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+ adaptivity->igi_up_bound_lmt_val = 180;
+#else
+ adaptivity->igi_up_bound_lmt_val = 90;
+#endif
+ adaptivity->igi_up_bound_lmt_cnt = 0;
+ adaptivity->igi_lmt_en = false;
}
-VOID
-Phydm_Adaptivity(
- IN PVOID pDM_VOID,
- IN u1Byte IGI
+void
+phydm_adaptivity(
+ void *dm_void
)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- s1Byte TH_L2H_dmc, TH_H2L_dmc;
- s1Byte Diff = 0, IGI_target;
- PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
+ u8 igi = dig_t->cur_ig_value;
+ s8 th_l2h_dmc, th_h2l_dmc;
+ s8 diff = 0, igi_target = 0x32;
+ struct phydm_adaptivity_struct *adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(dm, PHYDM_ADAPTIVITY);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
- PADAPTER pAdapter = pDM_Odm->Adapter;
- BOOLEAN bFwCurrentInPSMode = FALSE;
+ PADAPTER adapter = (PADAPTER)dm->adapter;
+ u32 is_fw_current_in_ps_mode = false;
+ u8 disable_ap_adapt_setting;
- pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_FW_PSMODE_STATUS, (pu1Byte)(&bFwCurrentInPSMode));
+ adapter->HalFunc.GetHwRegHandler(adapter, HW_VAR_FW_PSMODE_STATUS, (u8 *)(&is_fw_current_in_ps_mode));
/*Disable EDCCA mode while under LPS mode, added by Roger, 2012.09.14.*/
- if (bFwCurrentInPSMode)
+ if (is_fw_current_in_ps_mode)
return;
#endif
- if ((pDM_Odm->EDCCA_enable == FALSE) || (Adaptivity->bStopEDCCA == TRUE)) {
- ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Disable EDCCA!!!\n"));
+ if (!dm->edcca_enable || adaptivity->is_stop_edcca) {
+ PHYDM_DBG(dm, DBG_ADPTVTY, "Disable EDCCA!!!\n");
return;
}
- if (!(pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY)) {
- ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("adaptivity disable, enable EDCCA mode!!!\n"));
- pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_mode2;
- pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_mode2;
+ phydm_check_adaptivity(dm); /*Check adaptivity enable*/
+ phydm_dig_up_bound_lmt_en(dm);
+
+ if ((!(dm->support_ability & ODM_BB_ADAPTIVITY)) && adaptivity->debug_mode == false) {
+ PHYDM_DBG(dm, DBG_ADPTVTY, "adaptivity disable, enable EDCCA mode!!!\n");
+ dm->th_l2h_ini = dm->th_l2h_ini_mode2;
+ dm->th_edcca_hl_diff = dm->th_edcca_hl_diff_mode2;
}
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
- else{
- if (Phydm_CheckChannelPlan(pDM_Odm) || (pDM_Odm->APTotalNum > Adaptivity->APNumTH)) {
- pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_mode2;
- pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_mode2;
+ else if (adaptivity->debug_mode == false) {
+ disable_ap_adapt_setting = false;
+ if (dm->soft_ap_mode != NULL) {
+ if (*dm->soft_ap_mode != 0 && (dm->soft_ap_special_setting & BIT(0)))
+ disable_ap_adapt_setting = true;
+ PHYDM_DBG(dm, DBG_ADPTVTY, "soft_ap_setting = %x, soft_ap = %d, dis_ap_adapt = %d\n",
+ dm->soft_ap_special_setting, *dm->soft_ap_mode, disable_ap_adapt_setting);
+ }
+ if (phydm_check_channel_plan(dm) || (dm->ap_total_num > adaptivity->ap_num_th) || disable_ap_adapt_setting) {
+ dm->th_l2h_ini = dm->th_l2h_ini_mode2;
+ dm->th_edcca_hl_diff = dm->th_edcca_hl_diff_mode2;
} else {
- pDM_Odm->TH_L2H_ini = Adaptivity->TH_L2H_ini_backup;
- pDM_Odm->TH_EDCCA_HL_diff = Adaptivity->TH_EDCCA_HL_diff_backup;
+ dm->th_l2h_ini = adaptivity->th_l2h_ini_backup;
+ dm->th_edcca_hl_diff = adaptivity->th_edcca_hl_diff_backup;
}
}
#endif
-
- ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("odm_Adaptivity() =====>\n"));
- ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("IGI_Base=0x%x, TH_L2H_ini = %d, TH_EDCCA_HL_diff = %d\n",
- Adaptivity->IGI_Base, pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff));
+ else if (adaptivity->debug_mode == true) {
+ dm->th_l2h_ini = adaptivity->th_l2h_ini_debug;
+ dm->th_edcca_hl_diff = 7;
+ adaptivity->adajust_igi_level = (u8)((dm->th_l2h_ini + igi_target) - pwdb_upper_bound + dfir_loss); /*IGI = L2H - PwdB - dfir_loss*/
+ }
+ PHYDM_DBG(dm, DBG_ADPTVTY, "odm_Adaptivity() =====>\n");
+ PHYDM_DBG(dm, DBG_ADPTVTY, "igi_base=0x%x, th_l2h_ini = %d, th_edcca_hl_diff = %d\n",
+ adaptivity->igi_base, dm->th_l2h_ini, dm->th_edcca_hl_diff);
#if (RTL8195A_SUPPORT == 0)
- if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
+ if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
/*fix AC series when enable EDCCA hang issue*/
- ODM_SetBBReg(pDM_Odm, 0x800, BIT10, 1); /*ADC_mask disable*/
- ODM_SetBBReg(pDM_Odm, 0x800, BIT10, 0); /*ADC_mask enable*/
+ odm_set_bb_reg(dm, 0x800, BIT(10), 1); /*ADC_mask disable*/
+ odm_set_bb_reg(dm, 0x800, BIT(10), 0); /*ADC_mask enable*/
}
#endif
- if (*pDM_Odm->pBandWidth == ODM_BW20M) /*CHANNEL_WIDTH_20*/
- IGI_target = Adaptivity->IGI_Base;
- else if (*pDM_Odm->pBandWidth == ODM_BW40M)
- IGI_target = Adaptivity->IGI_Base + 2;
-#if (RTL8195A_SUPPORT == 0)
- else if (*pDM_Odm->pBandWidth == ODM_BW80M)
- IGI_target = Adaptivity->IGI_Base + 2;
-#endif
- else
- IGI_target = Adaptivity->IGI_Base;
- Adaptivity->IGI_target = (u1Byte) IGI_target;
- ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("BandWidth=%s, IGI_target=0x%x, DynamicLinkAdaptivity = %d, AcsForAdaptivity = %d\n",
- (*pDM_Odm->pBandWidth == ODM_BW80M) ? "80M" : ((*pDM_Odm->pBandWidth == ODM_BW40M) ? "40M" : "20M"), IGI_target, Adaptivity->DynamicLinkAdaptivity, Adaptivity->AcsForAdaptivity));
- ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("RSSI_min = %d, Adaptivity->AdajustIGILevel= 0x%x, adaptivity_flag = %d, Adaptivity_enable = %d\n",
- pDM_Odm->RSSI_Min, Adaptivity->AdajustIGILevel, pDM_Odm->adaptivity_flag, pDM_Odm->Adaptivity_enable));
+ igi_target = adaptivity->igi_base;
+ adaptivity->igi_target = (u8) igi_target;
+
+ PHYDM_DBG(dm, DBG_ADPTVTY, "band_width=%s, igi_target=0x%x, dynamic_link_adaptivity = %d\n",
+ (*dm->band_width == CHANNEL_WIDTH_80) ? "80M" : ((*dm->band_width == CHANNEL_WIDTH_40) ? "40M" : "20M"), igi_target, adaptivity->dynamic_link_adaptivity);
+ PHYDM_DBG(dm, DBG_ADPTVTY, "adajust_igi_level= 0x%x, adaptivity_flag = %d, adaptivity_enable = %d\n",
+ adaptivity->adajust_igi_level, dm->adaptivity_flag, dm->adaptivity_enable);
- if ((Adaptivity->DynamicLinkAdaptivity == TRUE) && (!pDM_Odm->bLinked) && (pDM_Odm->Adaptivity_enable == FALSE)) {
- Phydm_SetEDCCAThreshold(pDM_Odm, 0x7f, 0x7f);
- ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("In DynamicLink mode(noisy) and No link, Turn off EDCCA!!\n"));
+ if (adaptivity->dynamic_link_adaptivity && (!dm->is_linked) && !dm->adaptivity_enable) {
+ phydm_set_edcca_threshold(dm, 0x7f, 0x7f);
+ PHYDM_DBG(dm, DBG_ADPTVTY, "In DynamicLink mode(noisy) and No link, Turn off EDCCA!!\n");
return;
}
- if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) {
- if ((Adaptivity->AdajustIGILevel > IGI) && (pDM_Odm->Adaptivity_enable == TRUE))
- Diff = Adaptivity->AdajustIGILevel - IGI;
-
- TH_L2H_dmc = pDM_Odm->TH_L2H_ini - Diff + IGI_target;
- TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
+ if (dm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) {
+ if ((adaptivity->adajust_igi_level > igi) && dm->adaptivity_enable)
+ diff = adaptivity->adajust_igi_level - igi;
+ else if (dm->adaptivity_enable == false)
+ diff = 0x3e - igi;
+
+ th_l2h_dmc = dm->th_l2h_ini - diff + igi_target;
+ th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
}
#if (RTL8195A_SUPPORT == 0)
else {
- Diff = IGI_target - (s1Byte)IGI;
- TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff;
- if (TH_L2H_dmc > 10 && (pDM_Odm->Adaptivity_enable == TRUE))
- TH_L2H_dmc = 10;
+ diff = igi_target - (s8)igi;
+ th_l2h_dmc = dm->th_l2h_ini + diff;
+ if (th_l2h_dmc > 10 && dm->adaptivity_enable)
+ th_l2h_dmc = 10;
- TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
+ th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
/*replace lower bound to prevent EDCCA always equal 1*/
- if (TH_H2L_dmc < Adaptivity->H2L_lb)
- TH_H2L_dmc = Adaptivity->H2L_lb;
- if (TH_L2H_dmc < Adaptivity->L2H_lb)
- TH_L2H_dmc = Adaptivity->L2H_lb;
+ if (th_h2l_dmc < adaptivity->h2l_lb)
+ th_h2l_dmc = adaptivity->h2l_lb;
+ if (th_l2h_dmc < adaptivity->l2h_lb)
+ th_l2h_dmc = adaptivity->l2h_lb;
}
#endif
- ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("IGI=0x%x, TH_L2H_dmc = %d, TH_H2L_dmc = %d\n", IGI, TH_L2H_dmc, TH_H2L_dmc));
- ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity_IGI_upper=0x%x, H2L_lb = 0x%x, L2H_lb = 0x%x\n", pDM_Odm->Adaptivity_IGI_upper, Adaptivity->H2L_lb, Adaptivity->L2H_lb));
+ adaptivity->th_l2h = th_l2h_dmc;
+ adaptivity->th_h2l = th_h2l_dmc;
+ PHYDM_DBG(dm, DBG_ADPTVTY, "IGI=0x%x, th_l2h_dmc = %d, th_h2l_dmc = %d\n", igi, th_l2h_dmc, th_h2l_dmc);
+ PHYDM_DBG(dm, DBG_ADPTVTY, "adapt_igi_up=0x%x, h2l_lb = 0x%x, l2h_lb = 0x%x\n", adaptivity->adapt_igi_up, adaptivity->h2l_lb, adaptivity->l2h_lb);
+ PHYDM_DBG(dm, DBG_ADPTVTY, "debug_mode = %d\n", adaptivity->debug_mode);
+ phydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc);
+
+ if (dm->adaptivity_enable == true)
+ odm_set_mac_reg(dm, REG_RD_CTRL, BIT(11), 1);
- Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);
-
- if (pDM_Odm->Adaptivity_enable == TRUE)
- ODM_SetMACReg(pDM_Odm, REG_RD_CTRL, BIT11, 1);
-
return;
}
-
-#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-
-VOID
-Phydm_AdaptivityBSOD(
- IN PVOID pDM_VOID
+/*This API is for solving USB can't Tx problem due to USB3.0 interference in 2.4G*/
+void
+phydm_pause_edcca(
+ void *dm_void,
+ boolean is_pasue_edcca
)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- PADAPTER pAdapter = pDM_Odm->Adapter;
- PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo);
- u1Byte count = 0;
- u4Byte u4Value;
-
- /*
- 1. turn off RF (TRX Mux in standby mode)
- 2. H2C mac id drop
- 3. ignore EDCCA
- 4. wait for clear FIFO
- 5. don't ignore EDCCA
- 6. turn on RF (TRX Mux in TRx mdoe)
- 7. H2C mac id resume
- */
-
- RT_TRACE(COMP_MLME, DBG_WARNING, ("MAC id drop packet!!!!!\n"));
-
- pAdapter->dropPktByMacIdCnt++;
- pMgntInfo->bDropPktInProgress = TRUE;
-
- pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_MAX_Q_PAGE_NUM, (pu1Byte)(&u4Value));
- RT_TRACE(COMP_INIT, DBG_LOUD, ("Queue Reserved Page Number = 0x%08x\n", u4Value));
- pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_AVBL_Q_PAGE_NUM, (pu1Byte)(&u4Value));
- RT_TRACE(COMP_INIT, DBG_LOUD, ("Available Queue Page Number = 0x%08x\n", u4Value));
-
- /*Standby mode*/
- Phydm_SetTRxMux(pDM_Odm, PhyDM_STANDBY_MODE, PhyDM_STANDBY_MODE);
- ODM_Write_DIG(pDM_Odm, 0x20);
-
- /*H2C mac id drop*/
- MacIdIndicateDisconnect(pAdapter);
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct phydm_adaptivity_struct *adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(dm, PHYDM_ADAPTIVITY);
+ struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
+ u8 IGI = dig_t->cur_ig_value;
+ s8 diff = 0;
- /*Ignore EDCCA*/
- Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA);
+ if (is_pasue_edcca) {
+ adaptivity->is_stop_edcca = true;
- delay_ms(50);
- count = 5;
+ if (dm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) {
+ if (adaptivity->adajust_igi_level > IGI)
+ diff = adaptivity->adajust_igi_level - IGI;
- /*Resume EDCCA*/
- Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);
-
- /*Turn on TRx mode*/
- Phydm_SetTRxMux(pDM_Odm, PhyDM_TX_MODE, PhyDM_RX_MODE);
- ODM_Write_DIG(pDM_Odm, 0x20);
-
- /*Resume H2C macid*/
- MacIdRecoverMediaStatus(pAdapter);
-
- pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_AVBL_Q_PAGE_NUM, (pu1Byte)(&u4Value));
- RT_TRACE(COMP_INIT, DBG_LOUD, ("Available Queue Page Number = 0x%08x\n", u4Value));
-
- pMgntInfo->bDropPktInProgress = FALSE;
- RT_TRACE(COMP_MLME, DBG_WARNING, ("End of MAC id drop packet, spent %dms\n", count * 10));
-
-}
+ adaptivity->backup_l2h = dm->th_l2h_ini - diff + adaptivity->igi_target;
+ adaptivity->backup_h2l = adaptivity->backup_l2h - dm->th_edcca_hl_diff;
+ }
+#if (RTL8195A_SUPPORT == 0)
+ else {
+ diff = adaptivity->igi_target - (s8)IGI;
+ adaptivity->backup_l2h = dm->th_l2h_ini + diff;
+ if (adaptivity->backup_l2h > 10)
+ adaptivity->backup_l2h = 10;
-#endif
+ adaptivity->backup_h2l = adaptivity->backup_l2h - dm->th_edcca_hl_diff;
-/*This API is for solving USB can't Tx problem due to USB3.0 interference in 2.4G*/
-VOID
-phydm_pauseEDCCA(
- IN PVOID pDM_VOID,
- IN BOOLEAN bPasueEDCCA
-)
-{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);
- pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
- u1Byte IGI = pDM_DigTable->CurIGValue;
- s1Byte Diff = 0;
-
- if (bPasueEDCCA) {
- Adaptivity->bStopEDCCA = TRUE;
-
- if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) {
- if (Adaptivity->AdajustIGILevel > IGI)
- Diff = Adaptivity->AdajustIGILevel - IGI;
-
- Adaptivity->backupL2H = pDM_Odm->TH_L2H_ini - Diff + Adaptivity->IGI_target;
- Adaptivity->backupH2L = Adaptivity->backupL2H - pDM_Odm->TH_EDCCA_HL_diff;
- }
-#if (RTL8195A_SUPPORT == 0)
- else {
- Diff = Adaptivity->IGI_target - (s1Byte)IGI;
- Adaptivity->backupL2H = pDM_Odm->TH_L2H_ini + Diff;
- if (Adaptivity->backupL2H > 10)
- Adaptivity->backupL2H = 10;
-
- Adaptivity->backupH2L = Adaptivity->backupL2H - pDM_Odm->TH_EDCCA_HL_diff;
-
- /*replace lower bound to prevent EDCCA always equal 1*/
- if (Adaptivity->backupH2L < Adaptivity->H2L_lb)
- Adaptivity->backupH2L = Adaptivity->H2L_lb;
- if (Adaptivity->backupL2H < Adaptivity->L2H_lb)
- Adaptivity->backupL2H = Adaptivity->L2H_lb;
- }
+ /*replace lower bound to prevent EDCCA always equal 1*/
+ if (adaptivity->backup_h2l < adaptivity->h2l_lb)
+ adaptivity->backup_h2l = adaptivity->h2l_lb;
+ if (adaptivity->backup_l2h < adaptivity->l2h_lb)
+ adaptivity->backup_l2h = adaptivity->l2h_lb;
+ }
#endif
- ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("pauseEDCCA : L2Hbak = 0x%x, H2Lbak = 0x%x, IGI = 0x%x\n", Adaptivity->backupL2H, Adaptivity->backupH2L, IGI));
+ PHYDM_DBG(dm, DBG_ADPTVTY, "pauseEDCCA : L2Hbak = 0x%x, H2Lbak = 0x%x, IGI = 0x%x\n", adaptivity->backup_l2h, adaptivity->backup_h2l, IGI);
/*Disable EDCCA*/
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
- if (PlatformIsWorkItemScheduled(&(Adaptivity->phydm_pauseEDCCAWorkItem)) == FALSE)
- PlatformScheduleWorkItem(&(Adaptivity->phydm_pauseEDCCAWorkItem));
+ if (odm_is_work_item_scheduled(&adaptivity->phydm_pause_edcca_work_item) == false)
+ odm_schedule_work_item(&adaptivity->phydm_pause_edcca_work_item);
#else
- phydm_pauseEDCCA_WorkItemCallback(pDM_Odm);
+ phydm_pause_edcca_work_item_callback(dm);
#endif
-
- } else {
- Adaptivity->bStopEDCCA = FALSE;
- ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("resumeEDCCA : L2Hbak = 0x%x, H2Lbak = 0x%x, IGI = 0x%x\n", Adaptivity->backupL2H, Adaptivity->backupH2L, IGI));
+ } else {
+ adaptivity->is_stop_edcca = false;
+ PHYDM_DBG(dm, DBG_ADPTVTY, "resumeEDCCA : L2Hbak = 0x%x, H2Lbak = 0x%x, IGI = 0x%x\n", adaptivity->backup_l2h, adaptivity->backup_h2l, IGI);
/*Resume EDCCA*/
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
- if (PlatformIsWorkItemScheduled(&(Adaptivity->phydm_resumeEDCCAWorkItem)) == FALSE)
- PlatformScheduleWorkItem(&(Adaptivity->phydm_resumeEDCCAWorkItem));
+ if (odm_is_work_item_scheduled(&adaptivity->phydm_resume_edcca_work_item) == false)
+ odm_schedule_work_item(&adaptivity->phydm_resume_edcca_work_item);
#else
- phydm_resumeEDCCA_WorkItemCallback(pDM_Odm);
+ phydm_resume_edcca_work_item_callback(dm);
#endif
}
@@ -1000,98 +778,228 @@ phydm_pauseEDCCA(
}
-VOID
-phydm_pauseEDCCA_WorkItemCallback(
+void
+phydm_pause_edcca_work_item_callback(
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
- IN PADAPTER Adapter
+ void *adapter
#else
- IN PVOID pDM_VOID
+ void *dm_void
#endif
)
{
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
- PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
- PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
+ PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+ struct dm_struct *dm = &hal_data->DM_OutSrc;
#else
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
#endif
- if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
- ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskByte2|bMaskByte0, (u4Byte)(0x7f|0x7f<<16));
+ if (dm->support_ic_type & ODM_IC_11N_SERIES)
+ odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, MASKBYTE2 | MASKBYTE0, (u32)(0x7f | 0x7f << 16));
#if (RTL8195A_SUPPORT == 0)
- else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
- ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, bMaskLWord, (u2Byte)(0x7f|0x7f<<8));
+ else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
+ odm_set_bb_reg(dm, REG_FPGA0_XB_LSSI_READ_BACK, MASKLWORD, (u16)(0x7f | 0x7f << 8));
#endif
}
-VOID
-phydm_resumeEDCCA_WorkItemCallback(
+void
+phydm_resume_edcca_work_item_callback(
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
- IN PADAPTER Adapter
+ void *adapter
#else
- IN PVOID pDM_VOID
+ void *dm_void
#endif
)
{
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
- PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
- PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
+ PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+ struct dm_struct *dm = &hal_data->DM_OutSrc;
#else
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
#endif
- PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);
-
- if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
- ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskByte2|bMaskByte0, (u4Byte)((u1Byte)Adaptivity->backupL2H|(u1Byte)Adaptivity->backupH2L<<16));
+ struct phydm_adaptivity_struct *adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(dm, PHYDM_ADAPTIVITY);
+
+ if (dm->support_ic_type & ODM_IC_11N_SERIES)
+ odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD, MASKBYTE2 | MASKBYTE0, (u32)((u8)adaptivity->backup_l2h | (u8)adaptivity->backup_h2l << 16));
#if (RTL8195A_SUPPORT == 0)
- else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
- ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, bMaskLWord, (u2Byte)((u1Byte)Adaptivity->backupL2H|(u1Byte)Adaptivity->backupH2L<<8));
+ else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
+ odm_set_bb_reg(dm, REG_FPGA0_XB_LSSI_READ_BACK, MASKLWORD, (u16)((u8)adaptivity->backup_l2h | (u8)adaptivity->backup_h2l << 8));
#endif
}
-VOID
-phydm_setEDCCAThresholdAPI(
- IN PVOID pDM_VOID,
- IN u1Byte IGI
+void
+phydm_set_edcca_threshold_api(
+ void *dm_void,
+ u8 IGI
)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);
- s1Byte TH_L2H_dmc, TH_H2L_dmc;
- s1Byte Diff = 0, IGI_target = 0x32;
-
- if (pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY) {
- if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) {
- if (Adaptivity->AdajustIGILevel > IGI)
- Diff = Adaptivity->AdajustIGILevel - IGI;
-
- TH_L2H_dmc = pDM_Odm->TH_L2H_ini - Diff + IGI_target;
- TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct phydm_adaptivity_struct *adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(dm, PHYDM_ADAPTIVITY);
+ s8 th_l2h_dmc, th_h2l_dmc;
+ s8 diff = 0, igi_target = 0x32;
+
+ if (dm->support_ability & ODM_BB_ADAPTIVITY) {
+ if (dm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) {
+ if (adaptivity->adajust_igi_level > IGI)
+ diff = adaptivity->adajust_igi_level - IGI;
+
+ th_l2h_dmc = dm->th_l2h_ini - diff + igi_target;
+ th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
}
#if (RTL8195A_SUPPORT == 0)
else {
- Diff = IGI_target - (s1Byte)IGI;
- TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff;
- if (TH_L2H_dmc > 10)
- TH_L2H_dmc = 10;
+ diff = igi_target - (s8)IGI;
+ th_l2h_dmc = dm->th_l2h_ini + diff;
+ if (th_l2h_dmc > 10)
+ th_l2h_dmc = 10;
- TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
+ th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
/*replace lower bound to prevent EDCCA always equal 1*/
- if (TH_H2L_dmc < Adaptivity->H2L_lb)
- TH_H2L_dmc = Adaptivity->H2L_lb;
- if (TH_L2H_dmc < Adaptivity->L2H_lb)
- TH_L2H_dmc = Adaptivity->L2H_lb;
+ if (th_h2l_dmc < adaptivity->h2l_lb)
+ th_h2l_dmc = adaptivity->h2l_lb;
+ if (th_l2h_dmc < adaptivity->l2h_lb)
+ th_l2h_dmc = adaptivity->l2h_lb;
}
#endif
- ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("API :IGI=0x%x, TH_L2H_dmc = %d, TH_H2L_dmc = %d\n", IGI, TH_L2H_dmc, TH_H2L_dmc));
- ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("API :Adaptivity_IGI_upper=0x%x, H2L_lb = 0x%x, L2H_lb = 0x%x\n", pDM_Odm->Adaptivity_IGI_upper, Adaptivity->H2L_lb, Adaptivity->L2H_lb));
+ PHYDM_DBG(dm, DBG_ADPTVTY, "API :IGI=0x%x, th_l2h_dmc = %d, th_h2l_dmc = %d\n", IGI, th_l2h_dmc, th_h2l_dmc);
+ PHYDM_DBG(dm, DBG_ADPTVTY, "API :adapt_igi_up=0x%x, h2l_lb = 0x%x, l2h_lb = 0x%x\n", adaptivity->adapt_igi_up, adaptivity->h2l_lb, adaptivity->l2h_lb);
- Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);
+ phydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc);
+ }
+}
+
+void
+phydm_adaptivity_debug(
+ void *dm_void,
+ u32 *const dm_value,
+ u32 *_used,
+ char *output,
+ u32 *_out_len
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct phydm_adaptivity_struct *adaptivity = (struct phydm_adaptivity_struct *)phydm_get_structure(dm, PHYDM_ADAPTIVITY);
+ u32 used = *_used;
+ u32 out_len = *_out_len;
+ u32 reg_value32;
+ s8 h2l_diff = 0;
+
+ if (dm_value[0] == PHYDM_ADAPT_DEBUG) {
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "Adaptivity Debug Mode ===>\n");
+ adaptivity->debug_mode = true;
+ adaptivity->th_l2h_ini_debug = (s8)dm_value[1];
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "th_l2h_ini_debug = %d\n",
+ adaptivity->th_l2h_ini_debug);
+ } else if (dm_value[0] == PHYDM_ADAPT_RESUME) {
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "===> Adaptivity Resume\n");
+ adaptivity->debug_mode = false;
+ } else if (dm_value[0] == PHYDM_EDCCA_TH_PAUSE) {
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "EDCCA Threshold Pause\n");
+ dm->edcca_enable = false;
+ } else if (dm_value[0] == PHYDM_EDCCA_RESUME) {
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "EDCCA Resume\n");
+ dm->edcca_enable = true;
+ } else if (dm_value[0] == PHYDM_ADAPT_MSG) {
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "debug_mode = %s, th_l2h_ini = %d\n",
+ (adaptivity->debug_mode ? "TRUE" : "FALSE"),
+ dm->th_l2h_ini);
+ if (dm->support_ic_type & ODM_IC_11N_SERIES) {
+ reg_value32 = odm_get_bb_reg(dm, 0xc4c, MASKDWORD);
+ h2l_diff = (s8)(0x000000ff & reg_value32) - (s8)((0x00ff0000 & reg_value32)>>16);
+ }
+#if (RTL8195A_SUPPORT == 0)
+ else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+ reg_value32 = odm_get_bb_reg(dm, 0x8a4, MASKDWORD);
+ h2l_diff = (s8)(0x000000ff & reg_value32) - (s8)((0x0000ff00 & reg_value32)>>8);
+ }
+#endif
+ if (h2l_diff == 7)
+ PDM_SNPF(out_len, used, output + used,
+ out_len - used,
+ "adaptivity is enabled\n");
+ else
+ PDM_SNPF(out_len, used, output + used,
+ out_len - used,
+ "adaptivity is disabled\n");
}
+ *_used = used;
+ *_out_len = out_len;
+}
+
+void
+phydm_set_l2h_th_ini(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+ if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+ if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814A))
+ dm->th_l2h_ini = 0xf2;
+ else
+ dm->th_l2h_ini = 0xef;
+ } else
+ dm->th_l2h_ini = 0xf5;
+}
+
+void
+phydm_set_forgetting_factor(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+ if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814A))
+ odm_set_bb_reg(dm, 0x8a0, BIT(1) | BIT(0), 0);
+}
+void
+phydm_set_pwdb_mode(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+ if (dm->support_ability & ODM_BB_ADAPTIVITY) {
+ if (dm->support_ic_type & ODM_RTL8822B)
+ odm_set_bb_reg(dm, 0x8dc, BIT(5), 0x1);
+ else if (dm->support_ic_type & ODM_RTL8197F)
+ odm_set_bb_reg(dm, 0xce8, BIT(13), 0x1);
+ } else {
+ if (dm->support_ic_type & ODM_RTL8822B)
+ odm_set_bb_reg(dm, 0x8dc, BIT(5), 0x0);
+ else if (dm->support_ic_type & ODM_RTL8197F)
+ odm_set_bb_reg(dm, 0xce8, BIT(13), 0x0);
+ }
}
+void
+phydm_set_edcca_val(
+ void *dm_void,
+ u32 *val_buf,
+ u8 val_len
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+ if (val_len != 2) {
+ PHYDM_DBG(dm, ODM_COMP_API, "[Error][adaptivity]Need val_len = 2\n");
+ return;
+ }
+ if (dm->pause_ability & BIT(F13_ADPTVTY))
+ dm->adaptivity.is_stop_edcca = true;
+ else
+ dm->adaptivity.is_stop_edcca = false;
+
+ phydm_set_edcca_threshold(dm, (s8)val_buf[1], (s8)val_buf[0]);
+}
diff --git a/hal/phydm/phydm_adaptivity.h b/hal/phydm/phydm_adaptivity.h
index e2ca0d6..f1edb5c 100644
--- a/hal/phydm/phydm_adaptivity.h
+++ b/hal/phydm/phydm_adaptivity.h
@@ -1,222 +1,217 @@
-
/******************************************************************************
*
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
- *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
*
+ * Contact Information:
+ * wlanfae
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
*
- ******************************************************************************/
-
+ * Larry Finger
+ *
+ *****************************************************************************/
+
+
#ifndef __PHYDMADAPTIVITY_H__
#define __PHYDMADAPTIVITY_H__
-#define ADAPTIVITY_VERSION "9.3.3" /*20151230 changed by Kevin, modify 0x524[11] when adaptivity is enabled*/
+#define ADAPTIVITY_VERSION "9.5.7" /*20170627 changed by Kevin, move adapt_igi_up from phydm.h to phydm_adaptivity.h*/
-#define PwdBUpperBound 7
-#define DFIRloss 5
+#define pwdb_upper_bound 7
+#define dfir_loss 7
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
-typedef enum _tag_PhyDM_REGULATION_Type {
- REGULATION_FCC = 0,
- REGULATION_MKK = 1,
- REGULATION_ETSI = 2,
- REGULATION_WW = 3,
-
- MAX_REGULATION_NUM = 4
-} PhyDM_REGULATION_TYPE;
+enum phydm_regulation_type {
+ REGULATION_FCC = 0,
+ REGULATION_MKK = 1,
+ REGULATION_ETSI = 2,
+ REGULATION_WW = 3,
+ MAX_REGULATION_NUM = 4
+};
#endif
-typedef enum _PHYDM_ADAPTIVITY_Info_Definition {
+enum phydm_adapinfo {
PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE = 0,
PHYDM_ADAPINFO_DCBACKOFF,
PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY,
PHYDM_ADAPINFO_TH_L2H_INI,
PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF,
PHYDM_ADAPINFO_AP_NUM_TH
-
-} PHYDM_ADAPINFO_E;
-
-
-
-typedef enum tag_PhyDM_set_LNA {
- PhyDM_disable_LNA = 0,
- PhyDM_enable_LNA = 1,
-} PhyDM_set_LNA;
-
-
-typedef enum tag_PhyDM_TRx_MUX_Type
-{
- PhyDM_SHUTDOWN = 0,
- PhyDM_STANDBY_MODE = 1,
- PhyDM_TX_MODE = 2,
- PhyDM_RX_MODE = 3
-}PhyDM_Trx_MUX_Type;
-
-typedef enum tag_PhyDM_MACEDCCA_Type
-{
- PhyDM_IGNORE_EDCCA = 0,
- PhyDM_DONT_IGNORE_EDCCA = 1
-}PhyDM_MACEDCCA_Type;
-
-typedef struct _ADAPTIVITY_STATISTICS {
- s1Byte TH_L2H_ini_backup;
- s1Byte TH_EDCCA_HL_diff_backup;
- s1Byte IGI_Base;
- u1Byte IGI_target;
- u1Byte NHMWait;
- s1Byte H2L_lb;
- s1Byte L2H_lb;
- BOOLEAN bFirstLink;
- BOOLEAN bCheck;
- BOOLEAN DynamicLinkAdaptivity;
- u1Byte APNumTH;
- u1Byte AdajustIGILevel;
- BOOLEAN AcsForAdaptivity;
- s1Byte backupL2H;
- s1Byte backupH2L;
- BOOLEAN bStopEDCCA;
-#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
- RT_WORK_ITEM phydm_pauseEDCCAWorkItem;
- RT_WORK_ITEM phydm_resumeEDCCAWorkItem;
+};
+
+enum phydm_set_lna {
+ phydm_disable_lna = 0,
+ phydm_enable_lna = 1,
+};
+
+enum phydm_trx_mux_type {
+ phydm_shutdown = 0,
+ phydm_standby_mode = 1,
+ phydm_tx_mode = 2,
+ phydm_rx_mode = 3
+};
+
+enum phydm_mac_edcca_type {
+ phydm_ignore_edcca = 0,
+ phydm_dont_ignore_edcca = 1
+};
+
+enum phydm_adaptivity_mode {
+ PHYDM_ADAPT_MSG = 0,
+ PHYDM_ADAPT_DEBUG = 1,
+ PHYDM_ADAPT_RESUME = 2,
+ PHYDM_EDCCA_TH_PAUSE = 3,
+ PHYDM_EDCCA_RESUME = 4
+};
+
+struct phydm_adaptivity_struct {
+ s8 th_l2h_ini_backup;
+ s8 th_edcca_hl_diff_backup;
+ s8 igi_base;
+ u8 igi_target;
+ s8 h2l_lb;
+ s8 l2h_lb;
+ boolean is_check;
+ boolean dynamic_link_adaptivity;
+ u8 ap_num_th;
+ u8 adajust_igi_level;
+ s8 backup_l2h;
+ s8 backup_h2l;
+ boolean is_stop_edcca;
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+ RT_WORK_ITEM phydm_pause_edcca_work_item;
+ RT_WORK_ITEM phydm_resume_edcca_work_item;
#endif
-} ADAPTIVITY_STATISTICS, *PADAPTIVITY_STATISTICS;
-
-VOID
-phydm_pauseEDCCA(
- IN PVOID pDM_VOID,
- IN BOOLEAN bPasueEDCCA
+ u32 adaptivity_dbg_port; /*N:0x208, AC:0x209*/
+ u8 debug_mode;
+ s8 th_l2h_ini_debug;
+ u16 igi_up_bound_lmt_cnt; /*When igi_up_bound_lmt_cnt !=0, limit IGI upper bound to "adapt_igi_up"*/
+ u16 igi_up_bound_lmt_val; /*max value of igi_up_bound_lmt_cnt*/
+ boolean igi_lmt_en;
+ u8 adapt_igi_up;
+ s8 rvrt_val[2];
+ s8 th_l2h;
+ s8 th_h2l;
+};
+
+void
+phydm_pause_edcca(
+ void *dm_void,
+ boolean is_pasue_edcca
);
-VOID
-Phydm_CheckAdaptivity(
- IN PVOID pDM_VOID
- );
-
-VOID
-Phydm_CheckEnvironment(
- IN PVOID pDM_VOID
- );
-
-VOID
-Phydm_NHMCounterStatisticsInit(
- IN PVOID pDM_VOID
- );
-
-VOID
-Phydm_NHMCounterStatistics(
- IN PVOID pDM_VOID
- );
-
-VOID
-Phydm_NHMCounterStatisticsReset(
- IN PVOID pDM_VOID
+void
+phydm_check_environment(
+ void *dm_void
);
-VOID
-Phydm_GetNHMCounterStatistics(
- IN PVOID pDM_VOID
+void
+phydm_mac_edcca_state(
+ void *dm_void,
+ enum phydm_mac_edcca_type state
);
-VOID
-Phydm_MACEDCCAState(
- IN PVOID pDM_VOID,
- IN PhyDM_MACEDCCA_Type State
+void
+phydm_set_edcca_threshold(
+ void *dm_void,
+ s8 H2L,
+ s8 L2H
);
-VOID
-Phydm_SetEDCCAThreshold(
- IN PVOID pDM_VOID,
- IN s1Byte H2L,
- IN s1Byte L2H
+void
+phydm_set_trx_mux(
+ void *dm_void,
+ enum phydm_trx_mux_type tx_mode,
+ enum phydm_trx_mux_type rx_mode
);
-VOID
-Phydm_SetTRxMux(
- IN PVOID pDM_VOID,
- IN PhyDM_Trx_MUX_Type txMode,
- IN PhyDM_Trx_MUX_Type rxMode
-);
-
-BOOLEAN
-Phydm_CalNHMcnt(
- IN PVOID pDM_VOID
+void
+phydm_search_pwdb_lower_bound(
+ void *dm_void
);
-VOID
-Phydm_SearchPwdBLowerBound(
- IN PVOID pDM_VOID
+void
+phydm_adaptivity_info_init(
+ void *dm_void,
+ enum phydm_adapinfo cmn_info,
+ u32 value
);
-VOID
-phydm_adaptivityInfoInit(
- IN PVOID pDM_VOID,
- IN PHYDM_ADAPINFO_E CmnInfo,
- IN u4Byte Value
- );
+void
+phydm_adaptivity_init(
+ void *dm_void
+);
-VOID
-Phydm_AdaptivityInit(
- IN PVOID pDM_VOID
- );
+void
+phydm_adaptivity(
+ void *dm_void
+);
-VOID
-Phydm_Adaptivity(
- IN PVOID pDM_VOID,
- IN u1Byte IGI
- );
+void
+phydm_set_edcca_threshold_api(
+ void *dm_void,
+ u8 IGI
+);
-VOID
-phydm_setEDCCAThresholdAPI(
- IN PVOID pDM_VOID,
- IN u1Byte IGI
+void
+phydm_pause_edcca_work_item_callback(
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+ void *adapter
+#else
+ void *dm_void
+#endif
);
+void
+phydm_resume_edcca_work_item_callback(
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
-VOID
-Phydm_DisableEDCCA(
- IN PVOID pDM_VOID
+ void *adapter
+#else
+ void *dm_void
+#endif
);
-VOID
-Phydm_DynamicEDCCA(
- IN PVOID pDM_VOID
+void
+phydm_adaptivity_debug(
+ void *dm_void,
+ u32 *const dm_value,
+ u32 *_used,
+ char *output,
+ u32 *_out_len
);
-VOID
-Phydm_AdaptivityBSOD(
- IN PVOID pDM_VOID
+void
+phydm_set_l2h_th_ini(
+ void *dm_void
);
-#endif
+void
+phydm_set_forgetting_factor(
+ void *dm_void
+);
-VOID
-phydm_pauseEDCCA_WorkItemCallback(
-#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
- IN PADAPTER Adapter
-#else
- IN PVOID pDM_VOID
-#endif
- );
+void
+phydm_set_pwdb_mode(
+ void *dm_void
+);
-VOID
-phydm_resumeEDCCA_WorkItemCallback(
-#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
- IN PADAPTER Adapter
-#else
- IN PVOID pDM_VOID
-#endif
- );
+void
+phydm_set_edcca_val(
+ void *dm_void,
+ u32 *val_buf,
+ u8 val_len
+);
#endif
diff --git a/hal/phydm/phydm_adc_sampling.c b/hal/phydm/phydm_adc_sampling.c
index 388c942..55bb013 100644
--- a/hal/phydm/phydm_adc_sampling.c
+++ b/hal/phydm/phydm_adc_sampling.c
@@ -1,426 +1,790 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger
+ *
+ *****************************************************************************/
+
#include "mp_precomp.h"
#include "phydm_precomp.h"
-#include "rtl8197f/Hal8197FPhyReg.h"
-#if ((RTL8197F_SUPPORT == 1)||(RTL8822B_SUPPORT == 1))
-#include "WlanHAL/HalMac88XX/halmac_reg2.h"
-#else
-#include "WlanHAL/HalHeader/HalComReg.h"
+
+#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ #if ((RTL8197F_SUPPORT == 1) || (RTL8822B_SUPPORT == 1))
+ #include "rtl8197f/Hal8197FPhyReg.h"
+ #include "WlanHAL/HalMac88XX/halmac_reg2.h"
+ #else
+ #include "WlanHAL/HalHeader/HalComReg.h"
+ #endif
#endif
#if (PHYDM_LA_MODE_SUPPORT == 1)
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-BOOLEAN
-ADCSmp_BufferAllocate(
- IN PADAPTER Adapter,
- IN PRT_ADCSMP AdcSmp
- )
-{
- PRT_ADCSMP_STRING ADCSmpBuf = &(AdcSmp->ADCSmpBuf);
- if (ADCSmpBuf->Length == 0) {
- if (PlatformAllocateMemoryWithZero(Adapter, (void **)&(ADCSmpBuf->Octet), 0x10000) == RT_STATUS_SUCCESS)
- ADCSmpBuf->Length = 0x10000;
- else
- return FALSE;
- }
+#if WPP_SOFTWARE_TRACE
+ #include "phydm_adc_sampling.tmh"
+#endif
- return TRUE;
-}
#endif
-VOID
-ADCSmp_GetTxPktBuf(
- IN PVOID pDM_VOID,
- IN PRT_ADCSMP_STRING ADCSmpBuf
- )
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+boolean
+phydm_la_buffer_allocate(
+ void *dm_void
+)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- u4Byte i = 0, value32, DataL = 0, DataH = 0;
- u4Byte Addr, Finish_Addr;
- u4Byte End_Addr = (ADCSmpBuf->start_pos + ADCSmpBuf->buffer_size)-1; /*End_Addr = 0x3ffff;*/
- BOOLEAN bRoundUp;
- static u4Byte page = 0xFF;
-
-
- PlatformZeroMemory(ADCSmpBuf->Octet, ADCSmpBuf->Length);
-
- ODM_Write1Byte(pDM_Odm, REG_PKT_BUFF_ACCESS_CTRL, 0x69);
- /*PlatformEFIOWrite1Byte(Adapter, REG_PKT_BUFF_ACCESS_CTRL_8814A, 0x69);*/
- /*0x106[7:0]=0x69: access TXPKT Buffer*/
- /* 0xA5: access RXPKT Buffer*/
- /* 0x7F: access TXREPORT buffer*/
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct rt_adcsmp *adc_smp = &dm->adcsmp;
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+ void *adapter = dm->adapter;
+#endif
+ struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
+ boolean ret = true;
- DbgPrint("%s\n", __func__);
+ pr_debug("[LA mode BufferAllocate]\n");
- value32 = ODM_Read4Byte(pDM_Odm, REG_IQ_DUMP);
- bRoundUp = (BOOLEAN)((value32 & BIT31) >> 31);
- Finish_Addr = (value32 & 0x7FFF0000) >> 16; /*Reg7C0[30:16]: finish addr (unit: 8byte)*/
+ if (adc_smp_buf->length == 0) {
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+ if (PlatformAllocateMemoryWithZero(adapter, (void **)&adc_smp_buf->octet, adc_smp_buf->buffer_size) != RT_STATUS_SUCCESS)
+ ret = false;
+#else
+ odm_allocate_memory(dm, (void **)&adc_smp_buf->octet, adc_smp_buf->buffer_size);
- if (bRoundUp)
- Addr = (Finish_Addr+1)<<3;
- else
- Addr = ADCSmpBuf->start_pos;
+ if (!adc_smp_buf->octet)
+ ret = false;
+#endif
- DbgPrint("bRoundUp = %d, Finish_Addr=0x%x, value32=0x%x\n", bRoundUp, Finish_Addr, value32);
- DbgPrint("End_Addr = %x, ADCSmpBuf->start_pos = 0x%x, ADCSmpBuf->buffer_size = 0x%x\n", End_Addr, ADCSmpBuf->start_pos, ADCSmpBuf->buffer_size);
+ if (ret)
+ adc_smp_buf->length = adc_smp_buf->buffer_size;
+ }
-#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
- watchdog_stop(pDM_Odm->priv);
+ return ret;
+}
#endif
- if (pDM_Odm->SupportICType & ODM_RTL8197F) {
- for (Addr = 0x0, i = 0; Addr < End_Addr; Addr += 8, i += 2) { /*64K byte*/
- if ((Addr&0xfff) == 0)
- ODM_Write2Byte(pDM_Odm, REG_PKTBUF_DBG_CTRL, 0x780+(Addr >> 12));
- DataL = ODM_Read4Byte(pDM_Odm, 0x8000+(Addr&0xfff));
- DataH = ODM_Read4Byte(pDM_Odm, 0x8000+(Addr&0xfff)+4);
+void
+phydm_la_get_tx_pkt_buf(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct rt_adcsmp *adc_smp = &dm->adcsmp;
+ struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
+ u32 i = 0, value32, data_l = 0, data_h = 0;
+ u32 addr, finish_addr;
+ u32 end_addr = (adc_smp_buf->start_pos + adc_smp_buf->buffer_size) - 1; /*end_addr = 0x3ffff;*/
+ boolean is_round_up;
+ static u32 page = 0xFF;
+ u32 smp_cnt = 0, smp_number = 0, addr_8byte = 0;
+ u8 backup_dma = 0;
+
+ odm_memory_set(dm, adc_smp_buf->octet, 0, adc_smp_buf->length);
+ odm_write_1byte(dm, 0x0106, 0x69);
+
+ pr_debug("GetTxPktBuf\n");
+
+ value32 = odm_read_4byte(dm, 0x7c0);
+ is_round_up = (boolean)((value32 & BIT(31)) >> 31);
+ finish_addr = (value32 & 0x7FFF0000) >> 16; /*Reg7C0[30:16]: finish addr (unit: 8byte)*/
+
+ #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ #if (RTL8197F_SUPPORT)
+ if (dm->support_ic_type & ODM_RTL8197F) {
+ odm_set_bb_reg(dm, 0x7c0, BIT(0), 0x0);
+
+ /*Stop DMA*/
+ backup_dma = odm_get_mac_reg(dm, 0x300, MASKLWORD);
+ odm_set_mac_reg(dm, 0x300, 0x7fff, 0x7fff);
+
+ /*move LA mode content from IMEM to TxPktBuffer
+ Source : OCPBASE_IMEM 0x00000000
+ Destination : OCPBASE_TXBUF 0x18780000
+ Length : 64K*/
+ GET_HAL_INTERFACE(dm->priv)->init_ddma_handler(dm->priv, OCPBASE_IMEM, OCPBASE_TXBUF, 0x10000);
+ }
+ #endif
+ #endif
+
+ if (is_round_up) {
+ addr = (finish_addr + 1) << 3;
+ pr_debug("is_round_up = ((%d)), finish_addr=((0x%x)), 0x7c0=((0x%x))\n", is_round_up, finish_addr, value32);
+ smp_number = ((adc_smp_buf->buffer_size) >> 3); /*Byte to 8Byte (64bit)*/
+ } else {
+ addr = adc_smp_buf->start_pos;
+ addr_8byte = addr >> 3;
+
+ if (addr_8byte > finish_addr)
+ smp_number = addr_8byte - finish_addr;
+ else
+ smp_number = finish_addr - addr_8byte;
+
+ pr_debug("is_round_up = ((%d)), finish_addr=((0x%x * 8Byte)), Start_Addr = ((0x%x * 8Byte)), smp_number = ((%d))\n", is_round_up, finish_addr, addr_8byte, smp_number);
- DbgPrint("%08x%08x\n", DataH, DataL);
+ }
+ /*
+ dbg_print("is_round_up = %d, finish_addr=0x%x, value32=0x%x\n", is_round_up, finish_addr, value32);
+ dbg_print("end_addr = %x, adc_smp_buf->start_pos = 0x%x, adc_smp_buf->buffer_size = 0x%x\n", end_addr, adc_smp_buf->start_pos, adc_smp_buf->buffer_size);
+ */
+
+ if (dm->support_ic_type & ODM_RTL8197F) {
+ for (addr = 0x0, i = 0; addr < end_addr; addr += 8, i += 2) { /*64K byte*/
+ if ((addr & 0xfff) == 0)
+ odm_set_bb_reg(dm, 0x0140, MASKLWORD, 0x780 + (addr >> 12));
+ data_l = odm_get_bb_reg(dm, 0x8000 + (addr & 0xfff), MASKDWORD);
+ data_h = odm_get_bb_reg(dm, 0x8000 + (addr & 0xfff) + 4, MASKDWORD);
+
+ pr_debug("%08x%08x\n", data_h, data_l);
}
} else {
- while (Addr != (Finish_Addr<<3)) {
- if (page != (Addr >> 12)) {
- /*Reg140=0x780+(Addr>>12), Addr=0x30~0x3F, total 16 pages*/
- page = (Addr >> 12);
- ODM_Write2Byte(pDM_Odm, REG_PKTBUF_DBG_CTRL, 0x780+page);
+
+ i = 0;
+ while (addr != (finish_addr << 3)) {
+ if (page != (addr >> 12)) {
+ /*Reg140=0x780+(addr>>12), addr=0x30~0x3F, total 16 pages*/
+ page = (addr >> 12);
}
- /*pDataL = 0x8000+(Addr&0xfff);*/
- DataL = ODM_Read4Byte(pDM_Odm, 0x8000+(Addr&0xfff));
- DataH = ODM_Read4Byte(pDM_Odm, 0x8000+(Addr&0xfff)+4);
-
- /*ADCSmpBuf->Octet[i] = DataH;*/
- /*ADCSmpBuf->Octet[i+1] = DataL;*/
- /*DbgPrint("%08x%08x\n", ADCSmpBuf->Octet[i], ADCSmpBuf->Octet[i+1]);*/
- DbgPrint("%08x%08x\n", DataH, DataL);
+ odm_set_bb_reg(dm, 0x0140, MASKLWORD, 0x780 + page);
+
+ /*pDataL = 0x8000+(addr&0xfff);*/
+ data_l = odm_get_bb_reg(dm, 0x8000 + (addr & 0xfff), MASKDWORD);
+ data_h = odm_get_bb_reg(dm, 0x8000 + (addr & 0xfff) + 4, MASKDWORD);
+
+ #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+ adc_smp_buf->octet[i] = data_h;
+ adc_smp_buf->octet[i + 1] = data_l;
+ #endif
+
+ #if DBG /*WIN driver check build*/
+ pr_debug("%08x%08x\n", data_h, data_l);
+ #else /*WIN driver free build*/
+ #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+ RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("%08x%08x\n", adc_smp_buf->octet[i], adc_smp_buf->octet[i + 1]));
+ #endif
+ #endif
+
i = i + 2;
-
- if ((Addr+8) >= End_Addr)
- Addr = ADCSmpBuf->start_pos;
+
+ if ((addr + 8) >= end_addr)
+ addr = adc_smp_buf->start_pos;
else
- Addr = Addr + 8;
+ addr = addr + 8;
+
+ smp_cnt++;
+ if (smp_cnt >= (smp_number - 1))
+ break;
}
+ pr_debug("smp_cnt = ((%d))\n", smp_cnt);
+
+ #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+ RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("smp_cnt = ((%d))\n", smp_cnt));
+ #endif
}
-
-#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
- watchdog_resume(pDM_Odm->priv);
-#endif
-}
+ #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ #if (RTL8197F_SUPPORT)
+ if (dm->support_ic_type & ODM_RTL8197F)
+ odm_set_mac_reg(dm, 0x300, 0x7fff, backup_dma); /*Resume DMA*/
+ #endif
+ #endif
+}
-VOID
-ADCSmp_Start(
- IN PVOID pDM_VOID,
- IN PRT_ADCSMP AdcSmp
- )
+void
+phydm_la_mode_set_mac_iq_dump(
+ void *dm_void
+)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- u1Byte tmpU1b;
- PRT_ADCSMP_STRING Buffer = &(AdcSmp->ADCSmpBuf);
- RT_ADCSMP_TRIG_SIG_SEL TrigSigSel = AdcSmp->ADCSmpTrigSigSel;
- u1Byte backup_DMA;
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct rt_adcsmp *adc_smp = &dm->adcsmp;
+ u32 reg_value;
- DbgPrint("%s\n", __func__);
+ odm_write_1byte(dm, 0x7c0, 0); /*clear all 0x7c0*/
+ odm_set_mac_reg(dm, 0x7c0, BIT(0), 1); /*Enable LA mode HW block*/
- if (pDM_Odm->SupportICType & ODM_RTL8197F)
- ODM_SetBBReg(pDM_Odm, r_dma_trigger_8197F, 0xf00, AdcSmp->ADCSmpDmaDataSigSel); /*0x9A0[11:8]*/
- else
- ODM_SetBBReg(pDM_Odm , ODM_ADC_TRIGGER_Jaguar2, 0xf00, AdcSmp->ADCSmpDmaDataSigSel); /*0x95C[11:8]*/
+ if (adc_smp->la_trig_mode == PHYDM_MAC_TRIG) {
+ adc_smp->is_bb_trigger = 0;
+ odm_set_mac_reg(dm, 0x7c0, BIT(2), 1); /*polling bit for MAC mode*/
+ odm_set_mac_reg(dm, 0x7c0, BIT(4) | BIT(3), adc_smp->la_trigger_edge); /*trigger mode for MAC*/
- ODM_Write1Byte(pDM_Odm, REG_IQ_DUMP+1, AdcSmp->ADCSmpTriggerTime);
+ pr_debug("[MAC_trig] ref_mask = ((0x%x)), ref_value = ((0x%x)), dbg_port = ((0x%x))\n", adc_smp->la_mac_mask_or_hdr_sel, adc_smp->la_trig_sig_sel, adc_smp->la_dbg_port);
+ /*[Set MAC Debug Port]*/
+ odm_set_mac_reg(dm, 0xF4, BIT(16), 1);
+ odm_set_mac_reg(dm, 0x38, 0xff0000, adc_smp->la_dbg_port);
+ odm_set_mac_reg(dm, 0x7c4, MASKDWORD, adc_smp->la_mac_mask_or_hdr_sel);
+ odm_set_mac_reg(dm, 0x7c8, MASKDWORD, adc_smp->la_trig_sig_sel);
+ } else {
+ adc_smp->is_bb_trigger = 1;
+ odm_set_mac_reg(dm, 0x7c0, BIT(1), 1); /*polling bit for BB ADC mode*/
- if (pDM_Odm->SupportICType & ODM_RTL8197F)
- ODM_SetBBReg(pDM_Odm, r_reset_cfo_rpt_ctrl_8197F, BIT26, 0x1);
- else { /*for 8814A and 8822B?*/
- ODM_Write1Byte(pDM_Odm, 0x198c, 0x7);
- ODM_Write1Byte(pDM_Odm, 0x8b4, 0x80);
- }
-
- if (AdcSmp->ADCSmpTrigSel == ADCSMP_MAC_TRIG) { /* trigger by MAC*/
- if (TrigSigSel == ADCSMP_TRIG_REG) { /* manual trigger 0x7C0[5] = 0 -> 1*/
- ODM_Write1Byte(pDM_Odm, REG_IQ_DUMP, 0xCB); /*0x7C0[7:0]=8'b1100_1011*/
- ODM_Write1Byte(pDM_Odm, REG_IQ_DUMP, 0xEB); /*0x7C0[7:0]=8'b1110_1011*/
- } else if (TrigSigSel == ADCSMP_TRIG_CCA)
- ODM_Write1Byte(pDM_Odm, REG_IQ_DUMP, 0x8B); /*0x7C0[7:0]=8'b1000_1011*/
- else if (TrigSigSel == ADCSMP_TRIG_CRCFAIL)
- ODM_Write1Byte(pDM_Odm, REG_IQ_DUMP, 0x4B); /*0x7C0[7:0]=8'b0100_1011*/
- else if (TrigSigSel == ADCSMP_TRIG_CRCOK)
- ODM_Write1Byte(pDM_Odm, REG_IQ_DUMP, 0x0B); /*0x7C0[7:0]=8'b0000_1011*/
- } else { /*trigger by BB*/
- if (pDM_Odm->SupportICType & ODM_RTL8197F)
- ODM_SetBBReg(pDM_Odm, r_dma_trigger_8197F, 0x1f, TrigSigSel); /*0x9A0[4:0]*/
- else
- ODM_SetBBReg(pDM_Odm , ODM_ADC_TRIGGER_Jaguar2, 0x1f, TrigSigSel); /*0x95C[4:0], 0x1F: trigger by CCA*/
- ODM_Write1Byte(pDM_Odm, REG_IQ_DUMP, 0x03); /*0x7C0[7:0]=8'b0000_0011*/
+ if (adc_smp->la_trig_mode == PHYDM_ADC_MAC_TRIG) {
+ odm_set_mac_reg(dm, 0x7c0, BIT(3), 1); /*polling bit for MAC trigger event*/
+ odm_set_mac_reg(dm, 0x7c0, BIT(7) | BIT(6), adc_smp->la_trig_sig_sel);
+
+ if (adc_smp->la_trig_sig_sel == ADCSMP_TRIG_REG)
+ odm_set_mac_reg(dm, 0x7c0, BIT(5), 1); /* manual trigger 0x7C0[5] = 0->1*/
+ }
}
-
-#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
- watchdog_stop(pDM_Odm->priv);
+
+ reg_value = odm_get_bb_reg(dm, 0x7c0, 0xff);
+ pr_debug("4. [Set MAC IQ dump] 0x7c0[7:0] = ((0x%x))\n", reg_value);
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+ RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("4. [Set MAC IQ dump] 0x7c0[7:0] = ((0x%x))\n", reg_value));
#endif
- /*Polling*/
- do {
- tmpU1b = ODM_Read1Byte(pDM_Odm, REG_IQ_DUMP);
+}
+
+void
+phydm_adc_smp_start(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct rt_adcsmp *adc_smp = &dm->adcsmp;
+ u8 tmp_u1b;
+ u8 while_cnt = 0;
+ u8 polling_ok = false, target_polling_bit;
+
+ phydm_la_mode_bb_setting(dm);
+ phydm_la_mode_set_trigger_time(dm, adc_smp->la_trigger_time);
+
+ if (dm->support_ic_type & ODM_RTL8197F)
+ odm_set_bb_reg(dm, 0xd00, BIT(26), 0x1);
+ else { /*for 8814A and 8822B?*/
+ odm_write_1byte(dm, 0x8b4, 0x80);
+ /* odm_set_bb_reg(dm, 0x8b4, BIT(7), 1); */
+ }
+
+ phydm_la_mode_set_mac_iq_dump(dm);
+
+ #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ watchdog_stop(dm->priv);
+ #endif
- if (AdcSmp->ADCSmpState != ADCSMP_STATE_SET) {
- DbgPrint("ADCSmpState != ADCSMP_STATE_SET\n");
+ target_polling_bit = (adc_smp->is_bb_trigger) ? BIT(1) : BIT(2);
+ do { /*Polling time always use 100ms, when it exceed 2s, break while loop*/
+ tmp_u1b = odm_read_1byte(dm, 0x7c0);
+
+ if (adc_smp->adc_smp_state != ADCSMP_STATE_SET) {
+ pr_debug("[state Error] adc_smp_state != ADCSMP_STATE_SET\n");
break;
-
- } else if (tmpU1b & BIT1) {
- ODM_delay_us(AdcSmp->ADCSmpPollingTime);
+
+ } else if (tmp_u1b & target_polling_bit) {
+ ODM_delay_ms(100);
+ while_cnt = while_cnt + 1;
continue;
} else {
- DbgPrint("%s Query OK\n", __func__);
- if (pDM_Odm->SupportICType & ODM_RTL8197F)
- ODM_SetBBReg(pDM_Odm, REG_IQ_DUMP, BIT0, 0x0);
+ pr_debug("[LA Query OK] polling_bit=((0x%x))\n", target_polling_bit);
+ polling_ok = true;
break;
}
- } while (1);
-
-#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
- watchdog_resume(pDM_Odm->priv);
-#if (RTL8197F_SUPPORT == 1)
- if (pDM_Odm->SupportICType & ODM_RTL8197F) {
- /*Stop DMA*/
- backup_DMA = ODM_GetMACReg(pDM_Odm, 0x300, bMaskLWord);
- ODM_SetMACReg(pDM_Odm, 0x300, 0x7fff, backup_DMA|0x7fff);
-
- /*move LA mode content from IMEM to TxPktBuffer
- Src : OCPBASE_IMEM 0x00000000
- Dest : OCPBASE_TXBUF 0x18780000
- Len : 64K*/
- GET_HAL_INTERFACE(pDM_Odm->priv)->InitDDMAHandler(pDM_Odm->priv, OCPBASE_IMEM, OCPBASE_TXBUF, 0x10000);
+ } while (while_cnt < 20);
+
+ if (adc_smp->adc_smp_state == ADCSMP_STATE_SET) {
+ if (polling_ok)
+ phydm_la_get_tx_pkt_buf(dm);
+ else
+ pr_debug("[Polling timeout]\n");
}
-#endif
-#endif
- if (AdcSmp->ADCSmpState == ADCSMP_STATE_SET)
- ADCSmp_GetTxPktBuf(pDM_Odm, Buffer);
+ #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
+ watchdog_resume(dm->priv);
+ #endif
-#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
- if (pDM_Odm->SupportICType & ODM_RTL8197F)
- ODM_SetMACReg(pDM_Odm, 0x300, 0x7fff, backup_DMA); /*Resume DMA*/
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+ if (adc_smp->adc_smp_state == ADCSMP_STATE_SET)
+ adc_smp->adc_smp_state = ADCSMP_STATE_QUERY;
#endif
+ pr_debug("[LA mode] LA_pattern_count = ((%d))\n", adc_smp->la_count);
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
- if (AdcSmp->ADCSmpState == ADCSMP_STATE_SET)
- AdcSmp->ADCSmpState = ADCSMP_STATE_QUERY;
+ RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("[LA mode] la_count = ((%d))\n", adc_smp->la_count));
#endif
- DbgPrint("%s Status %d\n", __func__, AdcSmp->ADCSmpState);
+
+ adc_smp_stop(dm);
+
+ if (adc_smp->la_count == 0) {
+ pr_debug("LA Dump finished ---------->\n\n\n");
+ phydm_release_bb_dbg_port(dm);
+
+ if ((dm->support_ic_type & ODM_RTL8821C) && (dm->cut_version >= ODM_CUT_B))
+ odm_set_bb_reg(dm, 0x95c, BIT(23), 0);
+
+ } else {
+ adc_smp->la_count--;
+ pr_debug("LA Dump more ---------->\n\n\n");
+ adc_smp_set(dm, adc_smp->la_trig_mode, adc_smp->la_trig_sig_sel, adc_smp->la_dma_type, adc_smp->la_trigger_time, 0);
+ }
+
}
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-VOID
-ADCSmpWorkItemCallback(
- IN PVOID pContext
- )
+void
+adc_smp_work_item_callback(
+ void *context
+)
{
- PADAPTER Adapter = (PADAPTER)pContext;
- PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
- PRT_ADCSMP AdcSmp = &(pHalData->ADCSmp);
+ void *adapter = (void *)context;
+ PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+ struct dm_struct *dm = &hal_data->DM_OutSrc;
+ struct rt_adcsmp *adc_smp = &dm->adcsmp;
- ADCSmp_Start(Adapter, AdcSmp);
+ pr_debug("[WorkItem Call back] LA_State=((%d))\n", adc_smp->adc_smp_state);
+ phydm_adc_smp_start(dm);
}
#endif
-VOID
-ADCSmp_Set(
- IN PVOID pDM_VOID,
- IN RT_ADCSMP_TRIG_SEL TrigSel,
- IN RT_ADCSMP_TRIG_SIG_SEL TrigSigSel,
- IN u1Byte DmaDataSigSel,
- IN u1Byte TriggerTime,
- IN u2Byte PollingTime
- )
+void
+adc_smp_set(
+ void *dm_void,
+ u8 trig_mode,
+ u32 trig_sig_sel,
+ u8 dma_data_sig_sel,
+ u32 trigger_time,
+ u16 polling_time
+)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- BOOLEAN retValue = TRUE;
-
- PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp);
-/*
- DbgPrint("%s\n ADCSmpState %d ADCSmpTrigSig %d ADCSmpTrigSigSel %d\n",
- __FUNCTION__, AdcSmp->ADCSmpState, TrigSel, TrigSigSel);
-
- DbgPrint("ADCSmpDmaDataSigSel %d, ADCSmpTriggerTime %d ADCSmpPollingTime %d\n",
- DmaDataSigSel, TriggerTime, PollingTime);
-*/
- AdcSmp->ADCSmpTrigSel = TrigSel;
- AdcSmp->ADCSmpTrigSigSel = TrigSigSel;
- AdcSmp->ADCSmpDmaDataSigSel = DmaDataSigSel;
- AdcSmp->ADCSmpTriggerTime = TriggerTime;
- AdcSmp->ADCSmpPollingTime = PollingTime;
-
-#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
- if (AdcSmp->ADCSmpState != ADCSMP_STATE_IDLE)
- retValue = FALSE;
- else if (AdcSmp->ADCSmpBuf.Length == 0)
- retValue = ADCSmp_BufferAllocate(pDM_Odm, AdcSmp);
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ boolean is_set_success = true;
+ struct rt_adcsmp *adc_smp = &dm->adcsmp;
+
+ adc_smp->la_trig_mode = trig_mode;
+ adc_smp->la_trig_sig_sel = trig_sig_sel;
+ adc_smp->la_dma_type = dma_data_sig_sel;
+ adc_smp->la_trigger_time = trigger_time;
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+ if (adc_smp->adc_smp_state != ADCSMP_STATE_IDLE)
+ is_set_success = false;
+ else if (adc_smp->adc_smp_buf.length == 0)
+ is_set_success = phydm_la_buffer_allocate(dm);
#endif
- if (retValue) {
- AdcSmp->ADCSmpState = ADCSMP_STATE_SET;
+ if (is_set_success) {
+ adc_smp->adc_smp_state = ADCSMP_STATE_SET;
+
+ pr_debug("[LA Set Success] LA_State=((%d))\n", adc_smp->adc_smp_state);
+
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
- PlatformScheduleWorkItem(&(pHalData->ADCSmpWorkItem));
-#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
- ADCSmp_Start(pDM_Odm, AdcSmp);
+
+ pr_debug("ADCSmp_work_item_index = ((%d))\n", adc_smp->la_work_item_index);
+ if (adc_smp->la_work_item_index != 0) {
+ odm_schedule_work_item(&adc_smp->adc_smp_work_item_1);
+ adc_smp->la_work_item_index = 0;
+ } else {
+ odm_schedule_work_item(&adc_smp->adc_smp_work_item);
+ adc_smp->la_work_item_index = 1;
+ }
+#else
+ phydm_adc_smp_start(dm);
#endif
- }
+ } else
+ pr_debug("[LA Set Fail] LA_State=((%d))\n", adc_smp->adc_smp_state);
+
- DbgPrint("ADCSmpState %d Return Status %d\n", AdcSmp->ADCSmpState, retValue);
}
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-RT_STATUS
-ADCSmp_Query(
- IN PADAPTER Adapter,
- IN ULONG InformationBufferLength,
- OUT PVOID InformationBuffer,
- OUT PULONG BytesWritten
- )
+enum rt_status
+adc_smp_query(
+ void *dm_void,
+ ULONG information_buffer_length,
+ void *information_buffer,
+ PULONG bytes_written
+)
{
- RT_STATUS retStatus = RT_STATUS_SUCCESS;
- PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
- PRT_ADCSMP AdcSmp = &(pHalData->ADCSmp);
- PRT_ADCSMP_STRING ADCSmpBuf = &(AdcSmp->ADCSmpBuf);
-
- DbgPrint("%s ADCSmpState %d", __func__, AdcSmp->ADCSmpState);
-
- if (InformationBufferLength != ADCSmpBuf->buffer_size) {
- *BytesWritten = 0;
- retStatus = RT_STATUS_RESOURCE;
- } else if (ADCSmpBuf->Length != ADCSmpBuf->buffer_size) {
- *BytesWritten = 0;
- retStatus = RT_STATUS_RESOURCE;
- } else if (AdcSmp->ADCSmpState != ADCSMP_STATE_QUERY) {
- *BytesWritten = 0;
- retStatus = RT_STATUS_PENDING;
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct rt_adcsmp *adc_smp = &dm->adcsmp;
+ enum rt_status ret_status = RT_STATUS_SUCCESS;
+ struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
+
+ pr_debug("[%s] LA_State=((%d))", __func__, adc_smp->adc_smp_state);
+
+ if (information_buffer_length != adc_smp_buf->buffer_size) {
+ *bytes_written = 0;
+ ret_status = RT_STATUS_RESOURCE;
+ } else if (adc_smp_buf->length != adc_smp_buf->buffer_size) {
+ *bytes_written = 0;
+ ret_status = RT_STATUS_RESOURCE;
+ } else if (adc_smp->adc_smp_state != ADCSMP_STATE_QUERY) {
+ *bytes_written = 0;
+ ret_status = RT_STATUS_PENDING;
} else {
- PlatformMoveMemory(InformationBuffer, ADCSmpBuf->Octet, ADCSmpBuf->buffer_size);
- *BytesWritten = ADCSmpBuf->buffer_size;
+ odm_move_memory(dm, information_buffer, adc_smp_buf->octet, adc_smp_buf->buffer_size);
+ *bytes_written = adc_smp_buf->buffer_size;
- AdcSmp->ADCSmpState = ADCSMP_STATE_IDLE;
+ adc_smp->adc_smp_state = ADCSMP_STATE_IDLE;
}
- DbgPrint("Return Status %d\n", retStatus);
+ pr_debug("Return status %d\n", ret_status);
- return retStatus;
+ return ret_status;
}
-#endif
-
-VOID
-ADCSmp_Stop(
- IN PVOID pDM_VOID
- )
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+
+void
+adc_smp_query(
+ void *dm_void,
+ void *output,
+ u32 out_len,
+ u32 *pused
+)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp);
-
- AdcSmp->ADCSmpState = ADCSMP_STATE_IDLE;
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct rt_adcsmp *adc_smp = &dm->adcsmp;
+ struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
+ u32 used = *pused;
+ u32 i;
+ /* struct timespec t; */
+ /* rtw_get_current_timespec(&t); */
+
+ pr_debug("%s adc_smp_state %d", __func__, adc_smp->adc_smp_state);
+
+ for (i = 0; i < (adc_smp_buf->length >> 2) - 2; i += 2) {
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "%08x%08x\n", adc_smp_buf->octet[i],
+ adc_smp_buf->octet[i + 1]);
+ }
- DbgPrint("%s status %d\n", __func__, AdcSmp->ADCSmpState);
+ PDM_SNPF(out_len, used, output + used, out_len - used, "\n");
+ /* PDM_SNPF((output+used, out_len-used, "\n[%lu.%06lu]\n", t.tv_sec, t.tv_nsec)); */
+ *pused = used;
}
+s32
+adc_smp_get_sample_counts(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct rt_adcsmp *adc_smp = &dm->adcsmp;
+ struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
+
+ return (adc_smp_buf->length >> 2) - 2;
+}
+s32
+adc_smp_query_single_data(
+ void *dm_void,
+ void *output,
+ u32 out_len,
+ u32 index
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct rt_adcsmp *adc_smp = &dm->adcsmp;
+ struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
+ u32 used = 0;
+
+ /* dbg_print("%s adc_smp_state %d\n", __func__, adc_smp->adc_smp_state); */
+ if (adc_smp->adc_smp_state != ADCSMP_STATE_QUERY) {
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "Error: la data is not ready yet ...\n");
+ return -1;
+ }
+ if (index < ((adc_smp_buf->length >> 2) - 2)) {
+ PDM_SNPF(out_len, used, output + used, out_len - used,
+ "%08x%08x\n",
+ adc_smp_buf->octet[index],
+ adc_smp_buf->octet[index + 1]);
+ }
+ return 0;
+}
-#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
-u1Byte ADC_buffer[0x20000];
#endif
-VOID
-ADCSmp_Init(
- IN PVOID pDM_VOID
- )
+void
+adc_smp_stop(
+ void *dm_void
+)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- PRT_ADCSMP AdcSmp = &(pDM_Odm->adcsmp);
- PRT_ADCSMP_STRING ADCSmpBuf = &(AdcSmp->ADCSmpBuf);
-
- AdcSmp->ADCSmpState = ADCSMP_STATE_IDLE;
-
- if (pDM_Odm->SupportICType & ODM_RTL8814A) {
- ADCSmpBuf->start_pos = 0x30000;
- ADCSmpBuf->buffer_size = 0x10000;
- } else if (pDM_Odm->SupportICType & ODM_RTL8822B) {
- ADCSmpBuf->start_pos = 0x20000;
- ADCSmpBuf->buffer_size = 0x20000;
- } else if (pDM_Odm->SupportICType & ODM_RTL8197F) {
- ADCSmpBuf->start_pos = 0x00000;
- ADCSmpBuf->buffer_size = 0x10000;
- }
-
-#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
- PlatformInitializeWorkItem(
- Adapter,
- &(pHalData->ADCSmpWorkItem),
- (RT_WORKITEM_CALL_BACK)ADCSmpWorkItemCallback,
- (PVOID)Adapter,
- "ADCSmpWorkItem");
-#endif
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct rt_adcsmp *adc_smp = &dm->adcsmp;
+
+ adc_smp->adc_smp_state = ADCSMP_STATE_IDLE;
+ pr_debug("[LA_Stop] LA_state = ((%d))\n", adc_smp->adc_smp_state);
}
-#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-VOID
-ADCSmp_DeInit(
- PADAPTER Adapter
- )
+void
+adc_smp_init(
+ void *dm_void
+)
{
- PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
- PRT_ADCSMP AdcSmp = &(pHalData->ADCSmp);
- PRT_ADCSMP_STRING ADCSmpBuf = &(AdcSmp->ADCSmpBuf);
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct rt_adcsmp *adc_smp = &dm->adcsmp;
+ struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
+
+ adc_smp->adc_smp_state = ADCSMP_STATE_IDLE;
+
+ if (dm->support_ic_type & ODM_RTL8814A) {
+ adc_smp_buf->start_pos = 0x30000;
+ adc_smp_buf->buffer_size = 0x10000;
+ } else if (dm->support_ic_type & ODM_RTL8822B) {
+ adc_smp_buf->start_pos = 0x20000;
+ adc_smp_buf->buffer_size = 0x20000;
+ } else if (dm->support_ic_type & ODM_RTL8197F) {
+ adc_smp_buf->start_pos = 0x00000;
+ adc_smp_buf->buffer_size = 0x10000;
+ } else if (dm->support_ic_type & ODM_RTL8821C) {
+ adc_smp_buf->start_pos = 0x8000;
+ adc_smp_buf->buffer_size = 0x8000;
+ }
- ADCSmp_Stop(Adapter);
+}
+
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+void
+adc_smp_de_init(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct rt_adcsmp *adc_smp = &dm->adcsmp;
+ struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
- PlatformFreeWorkItem(&(pHalData->ADCSmpWorkItem));
+ adc_smp_stop(dm);
- if (ADCSmpBuf->Length != 0x0) {
- PlatformFreeMemory(ADCSmpBuf->Octet, ADCSmpBuf->Length);
- ADCSmpBuf->Length = 0x0;
+ if (adc_smp_buf->length != 0x0) {
+ odm_free_memory(dm, adc_smp_buf->octet, adc_smp_buf->length);
+ adc_smp_buf->length = 0x0;
}
-}
+}
+
+#endif
-VOID
-Dump_MAC(
- PADAPTER Adapter
- )
+void
+phydm_la_mode_bb_setting(
+ void *dm_void
+)
{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct rt_adcsmp *adc_smp = &dm->adcsmp;
- u4Byte Addr = 0;
-
- for (Addr = 0; Addr < 0x1A3D; Addr++)
- DbgPrint("%04x %04x\n", Addr, PlatformEFIORead4Byte(Adapter, Addr));
-}
+ u8 trig_mode = adc_smp->la_trig_mode;
+ u32 trig_sig_sel = adc_smp->la_trig_sig_sel;
+ u32 dbg_port = adc_smp->la_dbg_port;
+ u8 is_trigger_edge = adc_smp->la_trigger_edge;
+ u8 sampling_rate = adc_smp->la_smp_rate;
+ u8 la_dma_type = adc_smp->la_dma_type;
+ u32 dbg_port_header_sel = 0;
+ pr_debug("1. [BB Setting] trig_mode = ((%d)), dbg_port = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Sel = ((0x%x)), Dma_type = ((%d))\n",
+ trig_mode, dbg_port, is_trigger_edge, sampling_rate, trig_sig_sel, la_dma_type);
-VOID
-Dump_BB(
- PADAPTER Adapter
- )
-{
- u4Byte Addr = 0;
-
- for (Addr = 0; Addr < 0x1AFD; Addr++)
- DbgPrint("%04x %04x\n", Addr, PHY_QueryBBReg(Adapter, Addr, bMaskDWord));
-}
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+ RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("1. [LA mode bb_setting]trig_mode = ((%d)), dbg_port = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Sel = ((0x%x)), Dma_type = ((%d))\n",
+ trig_mode, dbg_port, is_trigger_edge, sampling_rate, trig_sig_sel, la_dma_type));
+#endif
+ if (trig_mode == PHYDM_MAC_TRIG)
+ trig_sig_sel = 0; /*ignore this setting*/
-VOID
-Dump_RF(
- PADAPTER Adapter
- )
-{
- u1Byte Addr = 0, Path = 0;
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+ /*set BB debug port*/
+ if (phydm_set_bb_dbg_port(dm, BB_DBGPORT_PRIORITY_3, dbg_port)) {
+ pr_debug("Set dbg_port((0x%x)) success\n", dbg_port);
+ }
- for (Path = ODM_RF_PATH_A; Path < pHalData->NumTotalRFPath; Path++) {
- for (Addr = 0; Addr < 0xF6; Addr++)
- DbgPrint("%04x %04x\n", Addr, PHY_QueryRFReg(Adapter, Path, Addr, bRFRegOffsetMask));
+ if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
+ if (trig_mode == PHYDM_ADC_RF0_TRIG)
+ dbg_port_header_sel = 9; /*DBGOUT_RFC_a[31:0]*/
+ else if (trig_mode == PHYDM_ADC_RF1_TRIG)
+ dbg_port_header_sel = 8; /*DBGOUT_RFC_b[31:0]*/
+ else if ((trig_mode == PHYDM_ADC_BB_TRIG) || (trig_mode == PHYDM_ADC_MAC_TRIG)) {
+
+ if (adc_smp->la_mac_mask_or_hdr_sel <= 0xf) {
+ dbg_port_header_sel = adc_smp->la_mac_mask_or_hdr_sel;
+ } else {
+ dbg_port_header_sel = 0;
+ }
+ }
+
+ phydm_bb_dbg_port_header_sel(dm, dbg_port_header_sel);
+
+ odm_set_bb_reg(dm, 0x95c, 0xf00, la_dma_type); /*0x95C[11:8]*/
+ odm_set_bb_reg(dm, 0x95C, 0x1f, trig_sig_sel); /*0x95C[4:0], BB debug port bit*/
+ odm_set_bb_reg(dm, 0x95C, BIT(31), is_trigger_edge); /*0: posedge, 1: negedge*/
+ odm_set_bb_reg(dm, 0x95c, 0xe0, sampling_rate);
+ /* (0:) '80MHz'
+ (1:) '40MHz'
+ (2:) '20MHz'
+ (3:) '10MHz'
+ (4:) '5MHz'
+ (5:) '2.5MHz'
+ (6:) '1.25MHz'
+ (7:) '160MHz (for BW160 ic)'
+ */
+ if ((dm->support_ic_type & ODM_RTL8821C) && (dm->cut_version >= ODM_CUT_B)) {
+ odm_set_bb_reg(dm, 0x95c, BIT(23), 1);
+ }
+ } else {
+ odm_set_bb_reg(dm, 0x9a0, 0xf00, la_dma_type); /*0x9A0[11:8]*/
+ odm_set_bb_reg(dm, 0x9a0, 0x1f, trig_sig_sel); /*0x9A0[4:0], BB debug port bit*/
+ odm_set_bb_reg(dm, 0x9A0, BIT(31), is_trigger_edge); /*0: posedge, 1: negedge*/
+ odm_set_bb_reg(dm, 0x9A0, 0xe0, sampling_rate);
+ /* (0:) '80MHz'
+ (1:) '40MHz'
+ (2:) '20MHz'
+ (3:) '10MHz'
+ (4:) '5MHz'
+ (5:) '2.5MHz'
+ (6:) '1.25MHz'
+ (7:) '160MHz (for BW160 ic)'
+ */
}
}
+
+void
+phydm_la_mode_set_trigger_time(
+ void *dm_void,
+ u32 trigger_time_mu_sec
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ u8 trigger_time_unit_num;
+ u32 time_unit = 0;
+
+ if (trigger_time_mu_sec < 128) {
+ time_unit = 0; /*unit: 1mu sec*/
+ } else if (trigger_time_mu_sec < 256) {
+ time_unit = 1; /*unit: 2mu sec*/
+ } else if (trigger_time_mu_sec < 512) {
+ time_unit = 2; /*unit: 4mu sec*/
+ } else if (trigger_time_mu_sec < 1024) {
+ time_unit = 3; /*unit: 8mu sec*/
+ } else if (trigger_time_mu_sec < 2048) {
+ time_unit = 4; /*unit: 16mu sec*/
+ } else if (trigger_time_mu_sec < 4096) {
+ time_unit = 5; /*unit: 32mu sec*/
+ } else if (trigger_time_mu_sec < 8192) {
+ time_unit = 6; /*unit: 64mu sec*/
+ }
+
+ trigger_time_unit_num = (u8)(trigger_time_mu_sec >> time_unit);
+
+ pr_debug("2. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n", trigger_time_unit_num, time_unit);
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+ RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("3. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n", trigger_time_unit_num, time_unit));
#endif
+ odm_set_mac_reg(dm, 0x7cc, BIT(20) | BIT(19) | BIT(18), time_unit);
+ odm_set_mac_reg(dm, 0x7c0, 0x7f00, (trigger_time_unit_num & 0x7f));
+
+}
+
+
+void
+phydm_lamode_trigger_setting(
+ void *dm_void,
+ char input[][16],
+ u32 *_used,
+ char *output,
+ u32 *_out_len,
+ u32 input_num
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct rt_adcsmp *adc_smp = &dm->adcsmp;
+ u8 trig_mode, dma_data_sig_sel;
+ u32 trig_sig_sel;
+ boolean is_enable_la_mode;
+ u32 trigger_time_mu_sec;
+ char help[] = "-h";
+ u32 var1[10] = {0};
+ u32 used = *_used;
+ u32 out_len = *_out_len;
+
+ if (dm->support_ic_type & PHYDM_IC_SUPPORT_LA_MODE) {
+ PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
+ is_enable_la_mode = (boolean)var1[0];
+ /*dbg_print("echo cmd input_num = %d\n", input_num);*/
+
+ if ((strcmp(input[1], help) == 0)) {
+ PDM_SNPF(out_len, used, output + used,
+ out_len - used,
+ "{En} {0:BB,1:BB_MAC,2:RF0,3:RF1,4:MAC} \n {BB:dbg_port[bit],BB_MAC:0-ok/1-fail/2-cca,MAC:ref} {DMA type} {TrigTime} \n {DbgPort_head/ref_mask} {dbg_port} {0:P_Edge, 1:N_Edge} {SpRate:0-80M,1-40M,2-20M} {Capture num}\n");
+ /**/
+ } else if ((is_enable_la_mode == 1)) {
+ PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]);
+
+ trig_mode = (u8)var1[1];
+
+ if (trig_mode == PHYDM_MAC_TRIG)
+ PHYDM_SSCANF(input[3], DCMD_HEX, &var1[2]);
+ else
+ PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
+ trig_sig_sel = var1[2];
+
+ PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]);
+ PHYDM_SSCANF(input[5], DCMD_DECIMAL, &var1[4]);
+ PHYDM_SSCANF(input[6], DCMD_HEX, &var1[5]);
+ PHYDM_SSCANF(input[7], DCMD_HEX, &var1[6]);
+ PHYDM_SSCANF(input[8], DCMD_DECIMAL, &var1[7]);
+ PHYDM_SSCANF(input[9], DCMD_DECIMAL, &var1[8]);
+ PHYDM_SSCANF(input[10], DCMD_DECIMAL, &var1[9]);
+
+ dma_data_sig_sel = (u8)var1[3];
+ trigger_time_mu_sec = var1[4]; /*unit: us*/
+
+ adc_smp->la_mac_mask_or_hdr_sel = var1[5];
+ adc_smp->la_dbg_port = var1[6];
+ adc_smp->la_trigger_edge = (u8) var1[7];
+ adc_smp->la_smp_rate = (u8)(var1[8] & 0x7);
+ adc_smp->la_count = var1[9];
+
+
+ pr_debug("echo lamode %d %d %d %d %d %d %x %d %d %d\n", var1[0], var1[1], var1[2], var1[3], var1[4], var1[5], var1[6], var1[7], var1[8], var1[9]);
+#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
+ RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ("echo lamode %d %d %d %d %d %d %x %d %d %d\n", var1[0], var1[1], var1[2], var1[3], var1[4], var1[5], var1[6], var1[7], var1[8], var1[9]));
#endif
+ PDM_SNPF(out_len, used, output + used,
+ out_len - used,
+ "a.En= ((1)), b.mode = ((%d)), c.Trig_Sel = ((0x%x)), d.Dma_type = ((%d))\n",
+ trig_mode, trig_sig_sel,
+ dma_data_sig_sel);
+ PDM_SNPF(out_len, used, output + used,
+ out_len - used,
+ "e.Trig_Time = ((%dus)), f.Dbg_head/mac_ref_mask = ((0x%x)), g.dbg_port = ((0x%x))\n",
+ trigger_time_mu_sec,
+ adc_smp->la_mac_mask_or_hdr_sel,
+ adc_smp->la_dbg_port);
+ PDM_SNPF(out_len, used, output + used,
+ out_len - used,
+ "h.Trig_edge = ((%d)), i.smp rate = ((%d MHz)), j.Cap_num = ((%d))\n",
+ adc_smp->la_trigger_edge,
+ (80 >> adc_smp->la_smp_rate),
+ adc_smp->la_count);
+
+ adc_smp_set(dm, trig_mode, trig_sig_sel, dma_data_sig_sel, trigger_time_mu_sec, 0);
+
+ } else {
+ adc_smp_stop(dm);
+ PDM_SNPF(out_len, used, output + used,
+ out_len - used, "Disable LA mode\n");
+ }
+ }
+ *_used = used;
+ *_out_len = out_len;
+}
+
+#endif /*endif PHYDM_LA_MODE_SUPPORT == 1*/
diff --git a/hal/phydm/phydm_adc_sampling.h b/hal/phydm/phydm_adc_sampling.h
index 330a3ce..9e9fc59 100644
--- a/hal/phydm/phydm_adc_sampling.h
+++ b/hal/phydm/phydm_adc_sampling.h
@@ -1,101 +1,172 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger
+ *
+ *****************************************************************************/
+
#ifndef __INC_ADCSMP_H
#define __INC_ADCSMP_H
-typedef struct _RT_ADCSMP_STRING {
- pu4Byte Octet;
- u4Byte Length;
- u4Byte buffer_size;
- u4Byte start_pos;
-} RT_ADCSMP_STRING, *PRT_ADCSMP_STRING;
-
-
-typedef enum _RT_ADCSMP_TRIG_SEL {
- ADCSMP_BB_TRIG,
- ADCSMP_MAC_TRIG,
-} RT_ADCSMP_TRIG_SEL, *PRT_ADCSMP_TRIG_SEL;
-
-
-typedef enum _RT_ADCSMP_TRIG_SIG_SEL {
- ADCSMP_TRIG_CRCOK,
- ADCSMP_TRIG_CRCFAIL,
- ADCSMP_TRIG_CCA,
- ADCSMP_TRIG_REG,
-} RT_ADCSMP_TRIG_SIG_SEL, *PRT_ADCSMP_TRIG_SIG_SEL;
-
-
-typedef enum _RT_ADCSMP_STATE {
- ADCSMP_STATE_IDLE,
- ADCSMP_STATE_SET,
- ADCSMP_STATE_QUERY,
-} RT_ADCSMP_STATE, *PRT_ADCSMP_STATE;
-
-
-typedef struct _RT_ADCSMP {
- RT_ADCSMP_STRING ADCSmpBuf;
- RT_ADCSMP_STATE ADCSmpState;
- RT_ADCSMP_TRIG_SEL ADCSmpTrigSel;
- RT_ADCSMP_TRIG_SIG_SEL ADCSmpTrigSigSel;
- u1Byte ADCSmpDmaDataSigSel;
- u1Byte ADCSmpTriggerTime;
- u2Byte ADCSmpPollingTime;
-} RT_ADCSMP, *PRT_ADCSMP;
+#define DYNAMIC_LA_MODE "2.0" /*2017.02.06 Dino */
+
+#if (PHYDM_LA_MODE_SUPPORT == 1)
+
+struct rt_adcsmp_string {
+ u32 *octet;
+ u32 length;
+ u32 buffer_size;
+ u32 start_pos;
+};
+
+
+enum rt_adcsmp_trig_sel {
+ PHYDM_ADC_BB_TRIG = 0,
+ PHYDM_ADC_MAC_TRIG = 1,
+ PHYDM_ADC_RF0_TRIG = 2,
+ PHYDM_ADC_RF1_TRIG = 3,
+ PHYDM_MAC_TRIG = 4
+};
+
+
+enum rt_adcsmp_trig_sig_sel {
+ ADCSMP_TRIG_CRCOK = 0,
+ ADCSMP_TRIG_CRCFAIL = 1,
+ ADCSMP_TRIG_CCA = 2,
+ ADCSMP_TRIG_REG = 3
+};
+
+
+enum rt_adcsmp_state {
+ ADCSMP_STATE_IDLE = 0,
+ ADCSMP_STATE_SET = 1,
+ ADCSMP_STATE_QUERY = 2
+};
+
+
+struct rt_adcsmp {
+ struct rt_adcsmp_string adc_smp_buf;
+ enum rt_adcsmp_state adc_smp_state;
+ u8 la_trig_mode;
+ u32 la_trig_sig_sel;
+ u8 la_dma_type;
+ u32 la_trigger_time;
+ u32 la_mac_mask_or_hdr_sel; /*1.BB mode: for debug port header sel; 2.MAC mode: for reference mask*/
+ u32 la_dbg_port;
+ u8 la_trigger_edge;
+ u8 la_smp_rate;
+ u32 la_count;
+ u8 is_bb_trigger;
+ u8 la_work_item_index;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+ RT_WORK_ITEM adc_smp_work_item;
+ RT_WORK_ITEM adc_smp_work_item_1;
+#endif
+};
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-VOID
-ADCSmpWorkItemCallback(
- IN PVOID pContext
+void
+adc_smp_work_item_callback(
+ void *context
);
#endif
-VOID
-ADCSmp_Set(
- IN PVOID pDM_VOID,
- IN RT_ADCSMP_TRIG_SEL TrigSel,
- IN RT_ADCSMP_TRIG_SIG_SEL TrigSigSel,
- IN u1Byte DmaDataSigSel,
- IN u1Byte TriggerTime,
- IN u2Byte PollingTime
+void
+adc_smp_set(
+ void *dm_void,
+ u8 trig_mode,
+ u32 trig_sig_sel,
+ u8 dma_data_sig_sel,
+ u32 trigger_time,
+ u16 polling_time
);
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-RT_STATUS
-ADCSmp_Query(
- IN PADAPTER Adapter,
- IN ULONG InformationBufferLength,
- OUT PVOID InformationBuffer,
- OUT PULONG BytesWritten
+enum rt_status
+adc_smp_query(
+ void *dm_void,
+ ULONG information_buffer_length,
+ void *information_buffer,
+ PULONG bytes_written
);
+#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
+void
+adc_smp_query(
+ void *dm_void,
+ void *output,
+ u32 out_len,
+ u32 *pused
+);
+
+s32
+adc_smp_get_sample_counts(
+ void *dm_void
+);
+
+s32
+adc_smp_query_single_data(
+ void *dm_void,
+ void *output,
+ u32 out_len,
+ u32 index
+);
+
#endif
-VOID
-ADCSmp_Stop(
- IN PVOID pDM_VOID
+void
+adc_smp_stop(
+ void *dm_void
);
-VOID
-ADCSmp_Init(
- IN PVOID pDM_VOID
+void
+adc_smp_init(
+ void *dm_void
);
-#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
-VOID
-ADCSmp_DeInit(
- PADAPTER Adapter
+#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
+void
+adc_smp_de_init(
+ void *dm_void
);
+#endif
-VOID
-Dump_MAC(
- PADAPTER Adapter
+void
+phydm_la_mode_bb_setting(
+ void *dm_void
);
-VOID
-Dump_BB(
- PADAPTER Adapter
+void
+phydm_la_mode_set_trigger_time(
+ void *dm_void,
+ u32 trigger_time_mu_sec
);
-VOID
-Dump_RF(
- PADAPTER Adapter
+void
+phydm_lamode_trigger_setting(
+ void *dm_void,
+ char input[][16],
+ u32 *_used,
+ char *output,
+ u32 *_out_len,
+ u32 input_num
);
#endif
#endif
-
diff --git a/hal/phydm/phydm_antdect.c b/hal/phydm/phydm_antdect.c
index afa478c..1d96aa9 100644
--- a/hal/phydm/phydm_antdect.c
+++ b/hal/phydm/phydm_antdect.c
@@ -1,706 +1,617 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
- *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
*
+ * Larry Finger
*
- ******************************************************************************/
+ *****************************************************************************/
-//============================================================
-// include files
-//============================================================
+/* ************************************************************
+ * include files
+ * ************************************************************ */
#include "mp_precomp.h"
#include "phydm_precomp.h"
-//#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE))
-#if(defined(CONFIG_ANT_DETECTION))
-
-//IS_ANT_DETECT_SUPPORT_SINGLE_TONE(Adapter)
-//IS_ANT_DETECT_SUPPORT_RSSI(Adapter)
-//IS_ANT_DETECT_SUPPORT_PSD(Adapter)
-
-//1 [1. Single Tone Method] ===================================================
-
-//
-// Description:
-// Set Single/Dual Antenna default setting for products that do not do detection in advance.
-//
-// Added by Joseph, 2012.03.22
-//
-VOID
-ODM_SingleDualAntennaDefaultSetting(
- IN PVOID pDM_VOID
- )
-{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
- PADAPTER pAdapter = pDM_Odm->Adapter;
+/* #if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE)) */
+#if (defined(CONFIG_ANT_DETECTION))
- u1Byte btAntNum=BT_GetPgAntNum(pAdapter);
- // Set default antenna A and B status
- if(btAntNum == 2)
- {
- pDM_SWAT_Table->ANTA_ON=TRUE;
- pDM_SWAT_Table->ANTB_ON=TRUE;
-
- }
- else if(btAntNum == 1)
- {// Set antenna A as default
- pDM_SWAT_Table->ANTA_ON=TRUE;
- pDM_SWAT_Table->ANTB_ON=FALSE;
-
- }
- else
- {
- RT_ASSERT(FALSE, ("Incorrect antenna number!!\n"));
- }
+/* IS_ANT_DETECT_SUPPORT_SINGLE_TONE(adapter)
+ * IS_ANT_DETECT_SUPPORT_RSSI(adapter)
+ * IS_ANT_DETECT_SUPPORT_PSD(adapter) */
+
+/* 1 [1. Single Tone method] =================================================== */
+
+/*
+ * Description:
+ * Set Single/Dual Antenna default setting for products that do not do detection in advance.
+ *
+ * Added by Joseph, 2012.03.22
+ * */
+void
+odm_single_dual_antenna_default_setting(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
+ void *adapter = dm->adapter;
+
+ u8 bt_ant_num = BT_GetPgAntNum(adapter);
+ /* Set default antenna A and B status */
+ if (bt_ant_num == 2) {
+ dm_swat_table->ANTA_ON = true;
+ dm_swat_table->ANTB_ON = true;
+
+ } else if (bt_ant_num == 1) {
+ /* Set antenna A as default */
+ dm_swat_table->ANTA_ON = true;
+ dm_swat_table->ANTB_ON = false;
+
+ } else
+ RT_ASSERT(false, ("Incorrect antenna number!!\n"));
}
-//2 8723A ANT DETECT
-//
-// Description:
-// Implement IQK single tone for RF DPK loopback and BB PSD scanning.
-// This function is cooperated with BB team Neil.
-//
-// Added by Roger, 2011.12.15
-//
-BOOLEAN
-ODM_SingleDualAntennaDetection(
- IN PVOID pDM_VOID,
- IN u1Byte mode
- )
+/* 2 8723A ANT DETECT
+ *
+ * Description:
+ * Implement IQK single tone for RF DPK loopback and BB PSD scanning.
+ * This function is cooperated with BB team Neil.
+ *
+ * Added by Roger, 2011.12.15
+ * */
+boolean
+odm_single_dual_antenna_detection(
+ void *dm_void,
+ u8 mode
+)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- PADAPTER pAdapter = pDM_Odm->Adapter;
- pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
- u4Byte CurrentChannel,RfLoopReg;
- u1Byte n;
- u4Byte Reg88c, Regc08, Reg874, Regc50, Reg948, Regb2c, Reg92c, Reg930, Reg064, AFE_rRx_Wait_CCA;
- u1Byte initial_gain = 0x5a;
- u4Byte PSD_report_tmp;
- u4Byte AntA_report = 0x0, AntB_report = 0x0, AntO_report = 0x0;
- BOOLEAN bResult = TRUE;
- u4Byte AFE_Backup[16];
- u4Byte AFE_REG_8723A[16] = {
- rRx_Wait_CCA, rTx_CCK_RFON,
- rTx_CCK_BBON, rTx_OFDM_RFON,
- rTx_OFDM_BBON, rTx_To_Rx,
- rTx_To_Tx, rRx_CCK,
- rRx_OFDM, rRx_Wait_RIFS,
- rRx_TO_Rx, rStandby,
- rSleep, rPMPD_ANAEN,
- rFPGA0_XCD_SwitchControl, rBlue_Tooth};
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection()============>\n"));
-
-
- if (!(pDM_Odm->SupportICType & ODM_RTL8723B))
- return bResult;
-
- // Retrieve antenna detection registry info, added by Roger, 2012.11.27.
- if(!IS_ANT_DETECT_SUPPORT_SINGLE_TONE(pAdapter))
- return bResult;
-
- //1 Backup Current RF/BB Settings
-
- CurrentChannel = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask);
- RfLoopReg = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask);
- if (pDM_Odm->SupportICType & ODM_RTL8723B) {
- Reg92c = ODM_GetBBReg(pDM_Odm, rDPDT_control, bMaskDWord);
- Reg930 = ODM_GetBBReg(pDM_Odm, rfe_ctrl_anta_src, bMaskDWord);
- Reg948 = ODM_GetBBReg(pDM_Odm, rS0S1_PathSwitch, bMaskDWord);
- Regb2c = ODM_GetBBReg(pDM_Odm, rAGC_table_select, bMaskDWord);
- Reg064 = ODM_GetMACReg(pDM_Odm, rSYM_WLBT_PAPE_SEL, BIT29);
- ODM_SetBBReg(pDM_Odm, rDPDT_control, 0x3, 0x1);
- ODM_SetBBReg(pDM_Odm, rfe_ctrl_anta_src, 0xff, 0x77);
- ODM_SetMACReg(pDM_Odm, rSYM_WLBT_PAPE_SEL, BIT29, 0x1); //dbg 7
- ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, 0x3c0, 0x0);//dbg 8
- ODM_SetBBReg(pDM_Odm, rAGC_table_select, BIT31, 0x0);
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ void *adapter = dm->adapter;
+ struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
+ u32 current_channel, rf_loop_reg;
+ u8 n;
+ u32 reg88c, regc08, reg874, regc50, reg948, regb2c, reg92c, reg930, reg064, afe_rrx_wait_cca;
+ u8 initial_gain = 0x5a;
+ u32 PSD_report_tmp;
+ u32 ant_a_report = 0x0, ant_b_report = 0x0, ant_0_report = 0x0;
+ boolean is_result = true;
+
+ PHYDM_DBG(dm, DBG_ANT_DIV, "odm_single_dual_antenna_detection()============>\n");
+
+
+ if (!(dm->support_ic_type & ODM_RTL8723B))
+ return is_result;
+
+ /* Retrieve antenna detection registry info, added by Roger, 2012.11.27. */
+ if (!IS_ANT_DETECT_SUPPORT_SINGLE_TONE(((PADAPTER)adapter)))
+ return is_result;
+
+ /* 1 Backup Current RF/BB Settings */
+
+ current_channel = odm_get_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK);
+ rf_loop_reg = odm_get_rf_reg(dm, RF_PATH_A, 0x00, RFREGOFFSETMASK);
+ if (dm->support_ic_type & ODM_RTL8723B) {
+ reg92c = odm_get_bb_reg(dm, REG_DPDT_CONTROL, MASKDWORD);
+ reg930 = odm_get_bb_reg(dm, rfe_ctrl_anta_src, MASKDWORD);
+ reg948 = odm_get_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD);
+ regb2c = odm_get_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD);
+ reg064 = odm_get_mac_reg(dm, REG_SYM_WLBT_PAPE_SEL, BIT(29));
+ odm_set_bb_reg(dm, REG_DPDT_CONTROL, 0x3, 0x1);
+ odm_set_bb_reg(dm, rfe_ctrl_anta_src, 0xff, 0x77);
+ odm_set_mac_reg(dm, REG_SYM_WLBT_PAPE_SEL, BIT(29), 0x1); /* dbg 7 */
+ odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0x3c0, 0x0);/* dbg 8 */
+ odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, BIT(31), 0x0);
}
- ODM_StallExecution(10);
-
- //Store A Path Register 88c, c08, 874, c50
- Reg88c = ODM_GetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord);
- Regc08 = ODM_GetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord);
- Reg874 = ODM_GetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord);
- Regc50 = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord);
-
- // Store AFE Registers
- if (pDM_Odm->SupportICType & ODM_RTL8723B)
- AFE_rRx_Wait_CCA = ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA,bMaskDWord);
-
- //Set PSD 128 pts
- ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT14|BIT15, 0x0); //128 pts
-
- // To SET CH1 to do
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask, 0x7401); //Channel 1
-
- // AFE all on step
- if (pDM_Odm->SupportICType & ODM_RTL8723B)
- ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, 0x01c00016);
-
- // 3 wire Disable
- ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, 0xCCF000C0);
-
- //BB IQK Setting
- ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800E4);
- ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22208000);
-
- //IQK setting tone@ 4.34Mhz
- ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008C1C);
- ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);
-
- //Page B init
- ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00080000);
- ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000);
- ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);
- ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f);
- if (pDM_Odm->SupportICType & ODM_RTL8723B) {
- ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82150016);
- ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28150016);
+ ODM_delay_us(10);
+
+ /* Store A path Register 88c, c08, 874, c50 */
+ reg88c = odm_get_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD);
+ regc08 = odm_get_bb_reg(dm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD);
+ reg874 = odm_get_bb_reg(dm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD);
+ regc50 = odm_get_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD);
+
+ /* Store AFE Registers */
+ if (dm->support_ic_type & ODM_RTL8723B)
+ afe_rrx_wait_cca = odm_get_bb_reg(dm, REG_RX_WAIT_CCA, MASKDWORD);
+
+ /* Set PSD 128 pts */
+ odm_set_bb_reg(dm, REG_FPGA0_PSD_FUNCTION, BIT(14) | BIT15, 0x0); /* 128 pts */
+
+ /* To SET CH1 to do */
+ odm_set_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK, 0x7401); /* channel 1 */
+
+ /* AFE all on step */
+ if (dm->support_ic_type & ODM_RTL8723B)
+ odm_set_bb_reg(dm, REG_RX_WAIT_CCA, MASKDWORD, 0x01c00016);
+
+ /* 3 wire Disable */
+ odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD, 0xCCF000C0);
+
+ /* BB IQK setting */
+ odm_set_bb_reg(dm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD, 0x000800E4);
+ odm_set_bb_reg(dm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD, 0x22208000);
+
+ /* IQK setting tone@ 4.34Mhz */
+ odm_set_bb_reg(dm, REG_TX_IQK_TONE_A, MASKDWORD, 0x10008C1C);
+ odm_set_bb_reg(dm, REG_TX_IQK, MASKDWORD, 0x01007c00);
+
+ /* Page B init */
+ odm_set_bb_reg(dm, REG_CONFIG_ANT_A, MASKDWORD, 0x00080000);
+ odm_set_bb_reg(dm, REG_CONFIG_ANT_A, MASKDWORD, 0x0f600000);
+ odm_set_bb_reg(dm, REG_RX_IQK, MASKDWORD, 0x01004800);
+ odm_set_bb_reg(dm, REG_RX_IQK_TONE_A, MASKDWORD, 0x10008c1f);
+ if (dm->support_ic_type & ODM_RTL8723B) {
+ odm_set_bb_reg(dm, REG_TX_IQK_PI_A, MASKDWORD, 0x82150016);
+ odm_set_bb_reg(dm, REG_RX_IQK_PI_A, MASKDWORD, 0x28150016);
}
- ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x001028d0);
- ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, 0x7f, initial_gain);
-
- //IQK Single tone start
- ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000);
- ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
- ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
-
- ODM_StallExecution(10000);
-
- // PSD report of antenna A
- PSD_report_tmp=0x0;
- for (n=0;n<2;n++)
- {
- PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain);
- if(PSD_report_tmp >AntA_report)
- AntA_report=PSD_report_tmp;
+ odm_set_bb_reg(dm, REG_IQK_AGC_RSP, MASKDWORD, 0x001028d0);
+ odm_set_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, 0x7f, initial_gain);
+
+ /* IQK Single tone start */
+ odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x808000);
+ odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf9000000);
+ odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf8000000);
+
+ ODM_delay_us(10000);
+
+ /* PSD report of antenna A */
+ PSD_report_tmp = 0x0;
+ for (n = 0; n < 2; n++) {
+ PSD_report_tmp = phydm_get_psd_data(dm, 14, initial_gain);
+ if (PSD_report_tmp > ant_a_report)
+ ant_a_report = PSD_report_tmp;
}
- // change to Antenna B
- if (pDM_Odm->SupportICType & ODM_RTL8723B) {
- //ODM_SetBBReg(pDM_Odm, rDPDT_control, 0x3, 0x2);
- ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, 0xfff, 0x280);
- ODM_SetBBReg(pDM_Odm, rAGC_table_select, BIT31, 0x1);
+ /* change to Antenna B */
+ if (dm->support_ic_type & ODM_RTL8723B) {
+ /* odm_set_bb_reg(dm, REG_DPDT_CONTROL, 0x3, 0x2); */
+ odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0xfff, 0x280);
+ odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, BIT(31), 0x1);
}
- ODM_StallExecution(10);
+ ODM_delay_us(10);
- // PSD report of antenna B
- PSD_report_tmp=0x0;
- for (n=0;n<2;n++)
- {
- PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain);
- if(PSD_report_tmp > AntB_report)
- AntB_report=PSD_report_tmp;
+ /* PSD report of antenna B */
+ PSD_report_tmp = 0x0;
+ for (n = 0; n < 2; n++) {
+ PSD_report_tmp = phydm_get_psd_data(dm, 14, initial_gain);
+ if (PSD_report_tmp > ant_b_report)
+ ant_b_report = PSD_report_tmp;
}
- //Close IQK Single Tone function
- ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000);
+ /* Close IQK Single Tone function */
+ odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
- //1 Return to antanna A
- if (pDM_Odm->SupportICType & ODM_RTL8723B) {
- // external DPDT
- ODM_SetBBReg(pDM_Odm, rDPDT_control, bMaskDWord, Reg92c);
+ /* 1 Return to antanna A */
+ if (dm->support_ic_type & ODM_RTL8723B) {
+ /* external DPDT */
+ odm_set_bb_reg(dm, REG_DPDT_CONTROL, MASKDWORD, reg92c);
- //internal S0/S1
- ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, bMaskDWord, Reg948);
- ODM_SetBBReg(pDM_Odm, rAGC_table_select, bMaskDWord, Regb2c);
- ODM_SetBBReg(pDM_Odm, rfe_ctrl_anta_src, bMaskDWord, Reg930);
- ODM_SetMACReg(pDM_Odm, rSYM_WLBT_PAPE_SEL, BIT29, Reg064);
+ /* internal S0/S1 */
+ odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD, reg948);
+ odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD, regb2c);
+ odm_set_bb_reg(dm, rfe_ctrl_anta_src, MASKDWORD, reg930);
+ odm_set_mac_reg(dm, REG_SYM_WLBT_PAPE_SEL, BIT(29), reg064);
}
-
- ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, Reg88c);
- ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, Regc08);
- ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, Reg874);
- ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, 0x7F, 0x40);
- ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord, Regc50);
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask,CurrentChannel);
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask,RfLoopReg);
-
- //Reload AFE Registers
- if (pDM_Odm->SupportICType & ODM_RTL8723B)
- ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, AFE_rRx_Wait_CCA);
-
- if (pDM_Odm->SupportICType & ODM_RTL8723B) {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_A[%d]= %d\n", 2416, AntA_report));
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_B[%d]= %d\n", 2416, AntB_report));
-
- //2 Test Ant B based on Ant A is ON
- if((AntA_report >= 100) && (AntB_report >= 100) && (AntA_report <= 135) && (AntB_report <= 135))
- {
- u1Byte TH1=2, TH2=6;
-
- if((AntA_report - AntB_report < TH1) || (AntB_report - AntA_report < TH1))
- {
- pDM_SWAT_Table->ANTA_ON=TRUE;
- pDM_SWAT_Table->ANTB_ON=TRUE;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SingleDualAntennaDetection(): Dual Antenna\n"));
- }
- else if(((AntA_report - AntB_report >= TH1) && (AntA_report - AntB_report <= TH2)) ||
- ((AntB_report - AntA_report >= TH1) && (AntB_report - AntA_report <= TH2)))
- {
- pDM_SWAT_Table->ANTA_ON=FALSE;
- pDM_SWAT_Table->ANTB_ON=FALSE;
- bResult = FALSE;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
- }
- else
- {
- pDM_SWAT_Table->ANTA_ON = TRUE;
- pDM_SWAT_Table->ANTB_ON=FALSE;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SingleDualAntennaDetection(): Single Antenna\n"));
+
+ odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD, reg88c);
+ odm_set_bb_reg(dm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD, regc08);
+ odm_set_bb_reg(dm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD, reg874);
+ odm_set_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, 0x7F, 0x40);
+ odm_set_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD, regc50);
+ odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, current_channel);
+ odm_set_rf_reg(dm, RF_PATH_A, 0x00, RFREGOFFSETMASK, rf_loop_reg);
+
+ /* Reload AFE Registers */
+ if (dm->support_ic_type & ODM_RTL8723B)
+ odm_set_bb_reg(dm, REG_RX_WAIT_CCA, MASKDWORD, afe_rrx_wait_cca);
+
+ if (dm->support_ic_type & ODM_RTL8723B) {
+ PHYDM_DBG(dm, DBG_ANT_DIV, "psd_report_A[%d]= %d\n", 2416, ant_a_report);
+ PHYDM_DBG(dm, DBG_ANT_DIV, "psd_report_B[%d]= %d\n", 2416, ant_b_report);
+
+ /* 2 Test ant B based on ant A is ON */
+ if ((ant_a_report >= 100) && (ant_b_report >= 100) && (ant_a_report <= 135) && (ant_b_report <= 135)) {
+ u8 TH1 = 2, TH2 = 6;
+
+ if ((ant_a_report - ant_b_report < TH1) || (ant_b_report - ant_a_report < TH1)) {
+ dm_swat_table->ANTA_ON = true;
+ dm_swat_table->ANTB_ON = true;
+ PHYDM_DBG(dm, DBG_ANT_DIV, "odm_single_dual_antenna_detection(): Dual Antenna\n");
+ } else if (((ant_a_report - ant_b_report >= TH1) && (ant_a_report - ant_b_report <= TH2)) ||
+ ((ant_b_report - ant_a_report >= TH1) && (ant_b_report - ant_a_report <= TH2))) {
+ dm_swat_table->ANTA_ON = false;
+ dm_swat_table->ANTB_ON = false;
+ is_result = false;
+ PHYDM_DBG(dm, DBG_ANT_DIV, "odm_single_dual_antenna_detection(): Need to check again\n");
+ } else {
+ dm_swat_table->ANTA_ON = true;
+ dm_swat_table->ANTB_ON = false;
+ PHYDM_DBG(dm, DBG_ANT_DIV, "odm_single_dual_antenna_detection(): Single Antenna\n");
}
- pDM_Odm->AntDetectedInfo.bAntDetected= TRUE;
- pDM_Odm->AntDetectedInfo.dBForAntA = AntA_report;
- pDM_Odm->AntDetectedInfo.dBForAntB = AntB_report;
- pDM_Odm->AntDetectedInfo.dBForAntO = AntO_report;
-
- }
- else
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("return FALSE!!\n"));
- bResult = FALSE;
+ dm->ant_detected_info.is_ant_detected = true;
+ dm->ant_detected_info.db_for_ant_a = ant_a_report;
+ dm->ant_detected_info.db_for_ant_b = ant_b_report;
+ dm->ant_detected_info.db_for_ant_o = ant_0_report;
+
+ } else {
+ PHYDM_DBG(dm, DBG_ANT_DIV, "return false!!\n");
+ is_result = false;
}
}
- return bResult;
+ return is_result;
}
-//1 [2. Scan AP RSSI Method] ==================================================
+/* 1 [2. Scan AP RSSI method] ================================================== */
-BOOLEAN
-ODM_SwAntDivCheckBeforeLink(
- IN PVOID pDM_VOID
- )
+boolean
+odm_sw_ant_div_check_before_link(
+ void *dm_void
+)
{
-
#if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM)
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- PADAPTER Adapter = pDM_Odm->Adapter;
- HAL_DATA_TYPE* pHalData = GET_HAL_DATA(Adapter);
- PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
- pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
- pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
- s1Byte Score = 0;
- PRT_WLAN_BSS pTmpBssDesc, pTestBssDesc;
- u1Byte power_target_L = 9, power_target_H = 16;
- u1Byte tmp_power_diff = 0,power_diff = 0,avg_power_diff = 0,max_power_diff = 0,min_power_diff = 0xff;
- u2Byte index, counter = 0;
- static u1Byte ScanChannel;
- u4Byte tmp_SWAS_NoLink_BK_Reg948;
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ANTA_ON = (( %d )) , ANTB_ON = (( %d ))\n", pDM_Odm->DM_SWAT_Table.ANTA_ON, pDM_Odm->DM_SWAT_Table.ANTB_ON));
-
- //if(HP id)
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ void *adapter = dm->adapter;
+ HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
+ //PMGNT_INFO mgnt_info = &adapter->MgntInfo;
+ PMGNT_INFO mgnt_info = &(((PADAPTER)(adapter))->MgntInfo);
+ struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
+ struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+ s8 score = 0;
+ PRT_WLAN_BSS p_tmp_bss_desc, p_test_bss_desc;
+ u8 power_target_L = 9, power_target_H = 16;
+ u8 tmp_power_diff = 0, power_diff = 0, avg_power_diff = 0, max_power_diff = 0, min_power_diff = 0xff;
+ u16 index, counter = 0;
+ static u8 scan_channel;
+ u32 tmp_swas_no_link_bk_reg948;
+
+ PHYDM_DBG(dm, DBG_ANT_DIV, "ANTA_ON = (( %d )) , ANTB_ON = (( %d ))\n", dm->dm_swat_table.ANTA_ON, dm->dm_swat_table.ANTB_ON);
+
+ /* if(HP id) */
{
- if(pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult==TRUE && pDM_Odm->SupportICType == ODM_RTL8723B)
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("8723B RSSI-based Antenna Detection is done\n"));
- return FALSE;
+ if (dm->dm_swat_table.rssi_ant_dect_result == true && dm->support_ic_type == ODM_RTL8723B) {
+ PHYDM_DBG(dm, DBG_ANT_DIV, "8723B RSSI-based Antenna Detection is done\n");
+ return false;
}
-
- if(pDM_Odm->SupportICType == ODM_RTL8723B)
- {
- if(pDM_SWAT_Table->SWAS_NoLink_BK_Reg948 == 0xff)
- pDM_SWAT_Table->SWAS_NoLink_BK_Reg948 = ODM_Read4Byte(pDM_Odm, rS0S1_PathSwitch );
+
+ if (dm->support_ic_type == ODM_RTL8723B) {
+ if (dm_swat_table->swas_no_link_bk_reg948 == 0xff)
+ dm_swat_table->swas_no_link_bk_reg948 = odm_read_4byte(dm, REG_S0_S1_PATH_SWITCH);
}
}
- if (pDM_Odm->Adapter == NULL) //For BSOD when plug/unplug fast. //By YJ,120413
- { // The ODM structure is not initialized.
- return FALSE;
+ if (dm->adapter == NULL) { /* For BSOD when plug/unplug fast. //By YJ,120413 */
+ /* The ODM structure is not initialized. */
+ return false;
}
- // Retrieve antenna detection registry info, added by Roger, 2012.11.27.
- if(!IS_ANT_DETECT_SUPPORT_RSSI(Adapter))
- {
- return FALSE;
- }
+ /* Retrieve antenna detection registry info, added by Roger, 2012.11.27. */
+ if (!IS_ANT_DETECT_SUPPORT_RSSI(((PADAPTER)adapter)))
+ return false;
else
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Antenna Detection: RSSI Method\n"));
- }
+ PHYDM_DBG(dm, DBG_ANT_DIV, "Antenna Detection: RSSI method\n");
- // Since driver is going to set BB register, it shall check if there is another thread controlling BB/RF.
- PlatformAcquireSpinLock(Adapter, RT_RF_STATE_SPINLOCK);
- if(pHalData->eRFPowerState!=eRfOn || pMgntInfo->RFChangeInProgress || pMgntInfo->bMediaConnect)
- {
- PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK);
-
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
- ("ODM_SwAntDivCheckBeforeLink(): RFChangeInProgress(%x), eRFPowerState(%x)\n",
- pMgntInfo->RFChangeInProgress, pHalData->eRFPowerState));
-
- pDM_SWAT_Table->SWAS_NoLink_State = 0;
-
- return FALSE;
- }
- else
- {
- PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK);
- }
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("pDM_SWAT_Table->SWAS_NoLink_State = %d\n", pDM_SWAT_Table->SWAS_NoLink_State));
- //1 Run AntDiv mechanism "Before Link" part.
- if(pDM_SWAT_Table->SWAS_NoLink_State == 0)
- {
- //1 Prepare to do Scan again to check current antenna state.
-
- // Set check state to next step.
- pDM_SWAT_Table->SWAS_NoLink_State = 1;
-
- // Copy Current Scan list.
- pMgntInfo->tmpNumBssDesc = pMgntInfo->NumBssDesc;
- PlatformMoveMemory((PVOID)Adapter->MgntInfo.tmpbssDesc, (PVOID)pMgntInfo->bssDesc, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC);
-
- // Go back to scan function again.
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink: Scan one more time\n"));
- pMgntInfo->ScanStep=0;
- pMgntInfo->bScanAntDetect = TRUE;
- ScanChannel = odm_SwAntDivSelectScanChnl(Adapter);
-
-
- if(pDM_Odm->SupportICType & (ODM_RTL8188E|ODM_RTL8821))
- {
- if(pDM_FatTable->RxIdleAnt == MAIN_ANT)
- ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT);
+ /* Since driver is going to set BB register, it shall check if there is another thread controlling BB/RF. */
+ odm_acquire_spin_lock(dm, RT_RF_STATE_SPINLOCK);
+ if (hal_data->eRFPowerState != eRfOn || mgnt_info->RFChangeInProgress || mgnt_info->bMediaConnect) {
+ odm_release_spin_lock(dm, RT_RF_STATE_SPINLOCK);
+
+ PHYDM_DBG(dm, DBG_ANT_DIV,
+ "odm_sw_ant_div_check_before_link(): rf_change_in_progress(%x), e_rf_power_state(%x)\n",
+ mgnt_info->RFChangeInProgress, hal_data->eRFPowerState);
+
+ dm_swat_table->swas_no_link_state = 0;
+
+ return false;
+ } else
+ odm_release_spin_lock(dm, RT_RF_STATE_SPINLOCK);
+ PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->swas_no_link_state = %d\n", dm_swat_table->swas_no_link_state);
+ /* 1 Run AntDiv mechanism "Before Link" part. */
+ if (dm_swat_table->swas_no_link_state == 0) {
+ /* 1 Prepare to do Scan again to check current antenna state. */
+
+ /* Set check state to next step. */
+ dm_swat_table->swas_no_link_state = 1;
+
+ /* Copy Current Scan list. */
+ mgnt_info->tmpNumBssDesc = mgnt_info->NumBssDesc;
+ PlatformMoveMemory((void *)mgnt_info->tmpbssDesc, (void *)mgnt_info->bssDesc, sizeof(RT_WLAN_BSS) * MAX_BSS_DESC);
+
+ /* Go back to scan function again. */
+ PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link: Scan one more time\n");
+ mgnt_info->ScanStep = 0;
+ mgnt_info->bScanAntDetect = true;
+ scan_channel = odm_sw_ant_div_select_scan_chnl(adapter);
+
+
+ if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8821)) {
+ if (fat_tab->rx_idle_ant == MAIN_ANT)
+ odm_update_rx_idle_ant(dm, AUX_ANT);
else
- ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);
- if(ScanChannel == 0)
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
- ("ODM_SwAntDivCheckBeforeLink(): No AP List Avaiable, Using Ant(%s)\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"AUX_ANT":"MAIN_ANT"));
-
- if(IS_5G_WIRELESS_MODE(pMgntInfo->dot11CurrentWirelessMode))
- {
- pDM_SWAT_Table->Ant5G = pDM_FatTable->RxIdleAnt;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant5G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
- }
- else
- {
- pDM_SWAT_Table->Ant2G = pDM_FatTable->RxIdleAnt;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant2G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
+ odm_update_rx_idle_ant(dm, MAIN_ANT);
+ if (scan_channel == 0) {
+ PHYDM_DBG(dm, DBG_ANT_DIV,
+ "odm_sw_ant_div_check_before_link(): No AP List Avaiable, Using ant(%s)\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "AUX_ANT" : "MAIN_ANT");
+
+ if (IS_5G_WIRELESS_MODE(mgnt_info->dot11CurrentWirelessMode)) {
+ dm_swat_table->ant_5g = fat_tab->rx_idle_ant;
+ PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->ant_5g=%s\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
+ } else {
+ dm_swat_table->ant_2g = fat_tab->rx_idle_ant;
+ PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->ant_2g=%s\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
}
- return FALSE;
+ return false;
}
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
- ("ODM_SwAntDivCheckBeforeLink: Change to %s for testing.\n", ((pDM_FatTable->RxIdleAnt == MAIN_ANT)?"MAIN_ANT":"AUX_ANT")));
- } else if (pDM_Odm->SupportICType & (ODM_RTL8723B)) {
+ PHYDM_DBG(dm, DBG_ANT_DIV,
+ "odm_sw_ant_div_check_before_link: Change to %s for testing.\n", ((fat_tab->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"));
+ } else if (dm->support_ic_type & (ODM_RTL8723B)) {
/*Switch Antenna to another one.*/
-
- tmp_SWAS_NoLink_BK_Reg948 = ODM_Read4Byte(pDM_Odm, rS0S1_PathSwitch);
-
- if ((pDM_SWAT_Table->CurAntenna == MAIN_ANT) && (tmp_SWAS_NoLink_BK_Reg948 == 0x200)) {
- ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, 0xfff, 0x280);
- ODM_SetBBReg(pDM_Odm, rAGC_table_select, BIT31, 0x1);
- pDM_SWAT_Table->CurAntenna = AUX_ANT;
+
+ tmp_swas_no_link_bk_reg948 = odm_read_4byte(dm, REG_S0_S1_PATH_SWITCH);
+
+ if ((dm_swat_table->cur_antenna == MAIN_ANT) && (tmp_swas_no_link_bk_reg948 == 0x200)) {
+ odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0xfff, 0x280);
+ odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, BIT(31), 0x1);
+ dm_swat_table->cur_antenna = AUX_ANT;
} else {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Reg[948]= (( %x )) was in wrong state\n", tmp_SWAS_NoLink_BK_Reg948));
- return FALSE;
+ PHYDM_DBG(dm, DBG_ANT_DIV, "Reg[948]= (( %x )) was in wrong state\n", tmp_swas_no_link_bk_reg948);
+ return false;
}
- ODM_StallExecution(10);
+ ODM_delay_us(10);
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink: Change to (( %s-ant)) for testing.\n", (pDM_SWAT_Table->CurAntenna == MAIN_ANT)?"MAIN":"AUX"));
+ PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link: Change to (( %s-ant)) for testing.\n", (dm_swat_table->cur_antenna == MAIN_ANT) ? "MAIN" : "AUX");
}
-
- odm_SwAntDivConstructScanChnl(Adapter, ScanChannel);
- PlatformSetTimer(Adapter, &pMgntInfo->ScanTimer, 5);
- return TRUE;
- }
- else //pDM_SWAT_Table->SWAS_NoLink_State == 1
- {
- //1 ScanComple() is called after antenna swiched.
- //1 Check scan result and determine which antenna is going
- //1 to be used.
-
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,(" tmpNumBssDesc= (( %d )) \n",pMgntInfo->tmpNumBssDesc));// debug for Dino
-
- for(index = 0; index < pMgntInfo->tmpNumBssDesc; index++)
- {
- pTmpBssDesc = &(pMgntInfo->tmpbssDesc[index]); // Antenna 1
- pTestBssDesc = &(pMgntInfo->bssDesc[index]); // Antenna 2
-
- if(PlatformCompareMemory(pTestBssDesc->bdBssIdBuf, pTmpBssDesc->bdBssIdBuf, 6)!=0)
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): ERROR!! This shall not happen.\n"));
+ odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel);
+ PlatformSetTimer(adapter, &mgnt_info->ScanTimer, 5);
+
+ return true;
+ } else { /* dm_swat_table->swas_no_link_state == 1 */
+ /* 1 ScanComple() is called after antenna swiched. */
+ /* 1 Check scan result and determine which antenna is going */
+ /* 1 to be used. */
+
+ PHYDM_DBG(dm, DBG_ANT_DIV, " tmp_num_bss_desc= (( %d ))\n", mgnt_info->tmpNumBssDesc); /* debug for Dino */
+
+ for (index = 0; index < mgnt_info->tmpNumBssDesc; index++) {
+ p_tmp_bss_desc = &mgnt_info->tmpbssDesc[index]; /* Antenna 1 */
+ p_test_bss_desc = &mgnt_info->bssDesc[index]; /* Antenna 2 */
+
+ if (PlatformCompareMemory(p_test_bss_desc->bdBssIdBuf, p_tmp_bss_desc->bdBssIdBuf, 6) != 0) {
+ PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link(): ERROR!! This shall not happen.\n");
continue;
}
- if(pDM_Odm->SupportICType != ODM_RTL8723B)
- {
- if(pTmpBssDesc->ChannelNumber == ScanChannel)
- {
- if(pTmpBssDesc->RecvSignalPower > pTestBssDesc->RecvSignalPower)
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink: Compare scan entry: Score++\n"));
- RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", pTmpBssDesc->bdSsIdBuf, pTmpBssDesc->bdSsIdLen);
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n\n", pTmpBssDesc->ChannelNumber, pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
-
- Score++;
- PlatformMoveMemory(pTestBssDesc, pTmpBssDesc, sizeof(RT_WLAN_BSS));
- }
- else if(pTmpBssDesc->RecvSignalPower < pTestBssDesc->RecvSignalPower)
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink: Compare scan entry: Score--\n"));
- RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", pTmpBssDesc->bdSsIdBuf, pTmpBssDesc->bdSsIdLen);
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n\n", pTmpBssDesc->ChannelNumber, pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
- Score--;
- }
- else
- {
- if(pTestBssDesc->bdTstamp - pTmpBssDesc->bdTstamp < 5000)
- {
- RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", pTmpBssDesc->bdSsIdBuf, pTmpBssDesc->bdSsIdLen);
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n", pTmpBssDesc->ChannelNumber, pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("The 2nd Antenna didn't get this AP\n\n"));
+ if (dm->support_ic_type != ODM_RTL8723B) {
+ if (p_tmp_bss_desc->ChannelNumber == scan_channel) {
+ if (p_tmp_bss_desc->RecvSignalPower > p_test_bss_desc->RecvSignalPower) {
+ PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link: Compare scan entry: score++\n");
+ RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen);
+ PHYDM_DBG(dm, DBG_ANT_DIV, "at ch %d, Original: %d, Test: %d\n\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
+
+ score++;
+ PlatformMoveMemory(p_test_bss_desc, p_tmp_bss_desc, sizeof(RT_WLAN_BSS));
+ } else if (p_tmp_bss_desc->RecvSignalPower < p_test_bss_desc->RecvSignalPower) {
+ PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link: Compare scan entry: score--\n");
+ RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen);
+ PHYDM_DBG(dm, DBG_ANT_DIV, "at ch %d, Original: %d, Test: %d\n\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
+ score--;
+ } else {
+ if (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp < 5000) {
+ RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen);
+ PHYDM_DBG(dm, DBG_ANT_DIV, "at ch %d, Original: %d, Test: %d\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
+ PHYDM_DBG(dm, DBG_ANT_DIV, "The 2nd Antenna didn't get this AP\n\n");
}
}
}
- }
- else // 8723B
- {
- if(pTmpBssDesc->ChannelNumber == ScanChannel)
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ChannelNumber == ScanChannel -> (( %d )) \n", pTmpBssDesc->ChannelNumber ));
-
- if(pTmpBssDesc->RecvSignalPower > pTestBssDesc->RecvSignalPower) // Pow(Ant1) > Pow(Ant2)
- {
+ } else { /* 8723B */
+ if (p_tmp_bss_desc->ChannelNumber == scan_channel) {
+ PHYDM_DBG(dm, DBG_ANT_DIV, "channel_number == scan_channel->(( %d ))\n", p_tmp_bss_desc->ChannelNumber);
+
+ if (p_tmp_bss_desc->RecvSignalPower > p_test_bss_desc->RecvSignalPower) { /* Pow(Ant1) > Pow(Ant2) */
counter++;
- tmp_power_diff=(u1Byte)(pTmpBssDesc->RecvSignalPower - pTestBssDesc->RecvSignalPower);
- power_diff = power_diff + tmp_power_diff;
-
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
- ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), pTmpBssDesc->bdSsIdBuf);
- ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), pTmpBssDesc->bdBssIdBuf);
-
- //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("tmp_power_diff: (( %d)),max_power_diff: (( %d)),min_power_diff: (( %d)) \n", tmp_power_diff,max_power_diff,min_power_diff));
- if(tmp_power_diff > max_power_diff)
- max_power_diff=tmp_power_diff;
- if(tmp_power_diff < min_power_diff)
- min_power_diff=tmp_power_diff;
- //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("max_power_diff: (( %d)),min_power_diff: (( %d)) \n",max_power_diff,min_power_diff));
-
- PlatformMoveMemory(pTestBssDesc, pTmpBssDesc, sizeof(RT_WLAN_BSS));
- }
- else if(pTestBssDesc->RecvSignalPower > pTmpBssDesc->RecvSignalPower) // Pow(Ant1) < Pow(Ant2)
- {
+ tmp_power_diff = (u8)(p_tmp_bss_desc->RecvSignalPower - p_test_bss_desc->RecvSignalPower);
+ power_diff = power_diff + tmp_power_diff;
+
+ PHYDM_DBG(dm, DBG_ANT_DIV, "Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
+ PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "SSID:", p_tmp_bss_desc->bdSsIdBuf);
+ PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "BSSID:", p_tmp_bss_desc->bdSsIdBuf);
+
+ /* PHYDM_DBG(dm,DBG_ANT_DIV, "tmp_power_diff: (( %d)),max_power_diff: (( %d)),min_power_diff: (( %d))\n", tmp_power_diff,max_power_diff,min_power_diff); */
+ if (tmp_power_diff > max_power_diff)
+ max_power_diff = tmp_power_diff;
+ if (tmp_power_diff < min_power_diff)
+ min_power_diff = tmp_power_diff;
+ /* PHYDM_DBG(dm,DBG_ANT_DIV, "max_power_diff: (( %d)),min_power_diff: (( %d))\n",max_power_diff,min_power_diff); */
+
+ PlatformMoveMemory(p_test_bss_desc, p_tmp_bss_desc, sizeof(RT_WLAN_BSS));
+ } else if (p_test_bss_desc->RecvSignalPower > p_tmp_bss_desc->RecvSignalPower) { /* Pow(Ant1) < Pow(Ant2) */
counter++;
- tmp_power_diff=(u1Byte)(pTestBssDesc->RecvSignalPower - pTmpBssDesc->RecvSignalPower);
- power_diff = power_diff + tmp_power_diff;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
- ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), pTmpBssDesc->bdSsIdBuf);
- ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), pTmpBssDesc->bdBssIdBuf);
- if(tmp_power_diff > max_power_diff)
- max_power_diff=tmp_power_diff;
- if(tmp_power_diff < min_power_diff)
- min_power_diff=tmp_power_diff;
- }
- else // Pow(Ant1) = Pow(Ant2)
- {
- if(pTestBssDesc->bdTstamp > pTmpBssDesc->bdTstamp) // Stamp(Ant1) < Stamp(Ant2)
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("time_diff: %lld\n", (pTestBssDesc->bdTstamp-pTmpBssDesc->bdTstamp)/1000));
- if(pTestBssDesc->bdTstamp - pTmpBssDesc->bdTstamp > 5000)
- {
- counter++;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
- ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), pTmpBssDesc->bdSsIdBuf);
- ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), pTmpBssDesc->bdBssIdBuf);
+ tmp_power_diff = (u8)(p_test_bss_desc->RecvSignalPower - p_tmp_bss_desc->RecvSignalPower);
+ power_diff = power_diff + tmp_power_diff;
+ PHYDM_DBG(dm, DBG_ANT_DIV, "Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
+ PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "SSID:", p_tmp_bss_desc->bdSsIdBuf);
+ PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "BSSID:", p_tmp_bss_desc->bdSsIdBuf);
+ if (tmp_power_diff > max_power_diff)
+ max_power_diff = tmp_power_diff;
+ if (tmp_power_diff < min_power_diff)
+ min_power_diff = tmp_power_diff;
+ } else { /* Pow(Ant1) = Pow(Ant2) */
+ if (p_test_bss_desc->bdTstamp > p_tmp_bss_desc->bdTstamp) { /* Stamp(Ant1) < Stamp(Ant2) */
+ PHYDM_DBG(dm, DBG_ANT_DIV, "time_diff: %lld\n", (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp) / 1000);
+ if (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp > 5000) {
+ counter++;
+ PHYDM_DBG(dm, DBG_ANT_DIV, "Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
+ PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "SSID:", p_tmp_bss_desc->bdSsIdBuf);
+ PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "BSSID:", p_tmp_bss_desc->bdSsIdBuf);
min_power_diff = 0;
- }
+ }
+ } else
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[Error !!!]: Time_diff: %lld\n", (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp) / 1000);
}
- else
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Error !!!]: Time_diff: %lld\n", (pTestBssDesc->bdTstamp-pTmpBssDesc->bdTstamp)/1000));
- }
}
}
}
- }
- if(pDM_Odm->SupportICType & (ODM_RTL8188E|ODM_RTL8821))
- {
- if(pMgntInfo->NumBssDesc!=0 && Score<0)
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
- ("ODM_SwAntDivCheckBeforeLink(): Using Ant(%s)\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
- }
- else
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
- ("ODM_SwAntDivCheckBeforeLink(): Remain Ant(%s)\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"AUX_ANT":"MAIN_ANT"));
+ if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8821)) {
+ if (mgnt_info->NumBssDesc != 0 && score < 0) {
+ PHYDM_DBG(dm, DBG_ANT_DIV,
+ "odm_sw_ant_div_check_before_link(): Using ant(%s)\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
+ } else {
+ PHYDM_DBG(dm, DBG_ANT_DIV,
+ "odm_sw_ant_div_check_before_link(): Remain ant(%s)\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "AUX_ANT" : "MAIN_ANT");
- if(pDM_FatTable->RxIdleAnt == MAIN_ANT)
- ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT);
+ if (fat_tab->rx_idle_ant == MAIN_ANT)
+ odm_update_rx_idle_ant(dm, AUX_ANT);
else
- ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);
- }
-
- if(IS_5G_WIRELESS_MODE(pMgntInfo->dot11CurrentWirelessMode))
- {
- pDM_SWAT_Table->Ant5G = pDM_FatTable->RxIdleAnt;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant5G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
- }
- else
- {
- pDM_SWAT_Table->Ant2G = pDM_FatTable->RxIdleAnt;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant2G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
+ odm_update_rx_idle_ant(dm, MAIN_ANT);
}
- }
- else if(pDM_Odm->SupportICType == ODM_RTL8723B)
- {
- if(counter == 0)
- {
- if(pDM_Odm->DM_SWAT_Table.Pre_Aux_FailDetec == FALSE)
- {
- pDM_Odm->DM_SWAT_Table.Pre_Aux_FailDetec = TRUE;
- pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=FALSE;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Counter=(( 0 )) , [[ Cannot find any AP with Aux-ant ]] -> Scan Target-channel again \n"));
-
- //3 [ Scan again ]
- odm_SwAntDivConstructScanChnl(Adapter, ScanChannel);
- PlatformSetTimer(Adapter, &pMgntInfo->ScanTimer, 5);
- return TRUE;
- }
- else// Pre_Aux_FailDetec == TRUE
- {
- //2 [ Single Antenna ]
- pDM_Odm->DM_SWAT_Table.Pre_Aux_FailDetec = FALSE;
- pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=TRUE;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Counter=(( 0 )) , [[ Still cannot find any AP ]] \n"));
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): Single antenna\n"));
- }
- pDM_Odm->DM_SWAT_Table.Aux_FailDetec_Counter++;
+
+ if (IS_5G_WIRELESS_MODE(mgnt_info->dot11CurrentWirelessMode)) {
+ dm_swat_table->ant_5g = fat_tab->rx_idle_ant;
+ PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->ant_5g=%s\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
+ } else {
+ dm_swat_table->ant_2g = fat_tab->rx_idle_ant;
+ PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->ant_2g=%s\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
}
- else
- {
- pDM_Odm->DM_SWAT_Table.Pre_Aux_FailDetec = FALSE;
-
- if(counter==3)
- {
- avg_power_diff = ((power_diff-max_power_diff - min_power_diff)>>1)+ ((max_power_diff + min_power_diff)>>2);
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("counter: (( %d )) , power_diff: (( %d )) \n", counter, power_diff));
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ counter==3 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d )) \n", avg_power_diff,max_power_diff, min_power_diff));
- }
- else if(counter>=4)
- {
- avg_power_diff=(power_diff-max_power_diff - min_power_diff) / (counter - 2);
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("counter: (( %d )) , power_diff: (( %d )) \n", counter, power_diff));
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ counter>=4 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d )) \n", avg_power_diff,max_power_diff, min_power_diff));
-
+ } else if (dm->support_ic_type == ODM_RTL8723B) {
+ if (counter == 0) {
+ if (dm->dm_swat_table.pre_aux_fail_detec == false) {
+ dm->dm_swat_table.pre_aux_fail_detec = true;
+ dm->dm_swat_table.rssi_ant_dect_result = false;
+ PHYDM_DBG(dm, DBG_ANT_DIV, "counter=(( 0 )) , [[ Cannot find any AP with Aux-ant ]] -> Scan Target-channel again\n");
+
+ /* 3 [ Scan again ] */
+ odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel);
+ PlatformSetTimer(adapter, &mgnt_info->ScanTimer, 5);
+ return true;
+ } else { /* pre_aux_fail_detec == true */
+ /* 2 [ Single Antenna ] */
+ dm->dm_swat_table.pre_aux_fail_detec = false;
+ dm->dm_swat_table.rssi_ant_dect_result = true;
+ PHYDM_DBG(dm, DBG_ANT_DIV, "counter=(( 0 )) , [[ Still cannot find any AP ]]\n");
+ PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link(): Single antenna\n");
}
- else//counter==1,2
- {
- avg_power_diff=power_diff/counter;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("avg_power_diff: (( %d )) , counter: (( %d )) , power_diff: (( %d )) \n", avg_power_diff,counter, power_diff));
+ dm->dm_swat_table.aux_fail_detec_counter++;
+ } else {
+ dm->dm_swat_table.pre_aux_fail_detec = false;
+
+ if (counter == 3) {
+ avg_power_diff = ((power_diff - max_power_diff - min_power_diff) >> 1) + ((max_power_diff + min_power_diff) >> 2);
+ PHYDM_DBG(dm, DBG_ANT_DIV, "counter: (( %d )) , power_diff: (( %d ))\n", counter, power_diff);
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[ counter==3 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d ))\n", avg_power_diff, max_power_diff, min_power_diff);
+ } else if (counter >= 4) {
+ avg_power_diff = (power_diff - max_power_diff - min_power_diff) / (counter - 2);
+ PHYDM_DBG(dm, DBG_ANT_DIV, "counter: (( %d )) , power_diff: (( %d ))\n", counter, power_diff);
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[ counter>=4 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d ))\n", avg_power_diff, max_power_diff, min_power_diff);
+
+ } else { /* counter==1,2 */
+ avg_power_diff = power_diff / counter;
+ PHYDM_DBG(dm, DBG_ANT_DIV, "avg_power_diff: (( %d )) , counter: (( %d )) , power_diff: (( %d ))\n", avg_power_diff, counter, power_diff);
}
- //2 [ Retry ]
- if( (avg_power_diff >=power_target_L) && (avg_power_diff <=power_target_H) )
- {
- pDM_Odm->DM_SWAT_Table.Retry_Counter++;
-
- if(pDM_Odm->DM_SWAT_Table.Retry_Counter<=3)
- {
- pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=FALSE;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[[ Low confidence result ]] avg_power_diff= (( %d )) -> Scan Target-channel again ]] \n", avg_power_diff));
-
- //3 [ Scan again ]
- odm_SwAntDivConstructScanChnl(Adapter, ScanChannel);
- PlatformSetTimer(Adapter, &pMgntInfo->ScanTimer, 5);
- return TRUE;
- }
- else
- {
- pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=TRUE;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[[ Still Low confidence result ]] (( Retry_Counter > 3 )) \n"));
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): Single antenna\n"));
+ /* 2 [ Retry ] */
+ if ((avg_power_diff >= power_target_L) && (avg_power_diff <= power_target_H)) {
+ dm->dm_swat_table.retry_counter++;
+
+ if (dm->dm_swat_table.retry_counter <= 3) {
+ dm->dm_swat_table.rssi_ant_dect_result = false;
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[[ Low confidence result ]] avg_power_diff= (( %d )) -> Scan Target-channel again ]]\n", avg_power_diff);
+
+ /* 3 [ Scan again ] */
+ odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel);
+ PlatformSetTimer(adapter, &mgnt_info->ScanTimer, 5);
+ return true;
+ } else {
+ dm->dm_swat_table.rssi_ant_dect_result = true;
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[[ Still Low confidence result ]] (( retry_counter > 3 ))\n");
+ PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link(): Single antenna\n");
}
-
+
}
- //2 [ Dual Antenna ]
- else if( (pMgntInfo->NumBssDesc != 0) && (avg_power_diff < power_target_L) )
- {
- pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=TRUE;
- if(pDM_Odm->DM_SWAT_Table.ANTB_ON == FALSE)
- {
- pDM_Odm->DM_SWAT_Table.ANTA_ON = TRUE;
- pDM_Odm->DM_SWAT_Table.ANTB_ON = TRUE;
+ /* 2 [ Dual Antenna ] */
+ else if ((mgnt_info->NumBssDesc != 0) && (avg_power_diff < power_target_L)) {
+ dm->dm_swat_table.rssi_ant_dect_result = true;
+ if (dm->dm_swat_table.ANTB_ON == false) {
+ dm->dm_swat_table.ANTA_ON = true;
+ dm->dm_swat_table.ANTB_ON = true;
}
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SwAntDivCheckBeforeLink(): Dual antenna\n"));
- pDM_Odm->DM_SWAT_Table.Dual_Ant_Counter++;
-
- // set bt coexDM from 1ant coexDM to 2ant coexDM
- BT_SetBtCoexAntNum(Adapter, BT_COEX_ANT_TYPE_DETECTED, 2);
-
- //3 [ Init antenna diversity ]
- pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV;
- ODM_AntDivInit(pDM_Odm);
+ PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link(): Dual antenna\n");
+ dm->dm_swat_table.dual_ant_counter++;
+
+ /* set bt coexDM from 1ant coexDM to 2ant coexDM */
+ BT_SetBtCoexAntNum(adapter, BT_COEX_ANT_TYPE_DETECTED, 2);
+
+ /* 3 [ Init antenna diversity ] */
+ dm->support_ability |= ODM_BB_ANT_DIV;
+ odm_ant_div_init(dm);
}
- //2 [ Single Antenna ]
- else if(avg_power_diff > power_target_H)
- {
- pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=TRUE;
- if(pDM_Odm->DM_SWAT_Table.ANTB_ON == TRUE)
- {
- pDM_Odm->DM_SWAT_Table.ANTA_ON = TRUE;
- pDM_Odm->DM_SWAT_Table.ANTB_ON = FALSE;
- //BT_SetBtCoexAntNum(Adapter, BT_COEX_ANT_TYPE_DETECTED, 1);
+ /* 2 [ Single Antenna ] */
+ else if (avg_power_diff > power_target_H) {
+ dm->dm_swat_table.rssi_ant_dect_result = true;
+ if (dm->dm_swat_table.ANTB_ON == true) {
+ dm->dm_swat_table.ANTA_ON = true;
+ dm->dm_swat_table.ANTB_ON = false;
+ /* bt_set_bt_coex_ant_num(adapter, BT_COEX_ANT_TYPE_DETECTED, 1); */
}
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): Single antenna\n"));
- pDM_Odm->DM_SWAT_Table.Single_Ant_Counter++;
+ PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link(): Single antenna\n");
+ dm->dm_swat_table.single_ant_counter++;
}
}
- //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("bResult=(( %d ))\n",pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult));
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Dual_Ant_Counter = (( %d )), Single_Ant_Counter = (( %d )) , Retry_Counter = (( %d )) , Aux_FailDetec_Counter = (( %d ))\n\n\n",
- pDM_Odm->DM_SWAT_Table.Dual_Ant_Counter,pDM_Odm->DM_SWAT_Table.Single_Ant_Counter,pDM_Odm->DM_SWAT_Table.Retry_Counter,pDM_Odm->DM_SWAT_Table.Aux_FailDetec_Counter));
+ /* PHYDM_DBG(dm,DBG_ANT_DIV, "is_result=(( %d ))\n",dm->dm_swat_table.rssi_ant_dect_result); */
+ PHYDM_DBG(dm, DBG_ANT_DIV, "dual_ant_counter = (( %d )), single_ant_counter = (( %d )) , retry_counter = (( %d )) , aux_fail_detec_counter = (( %d ))\n\n\n",
+ dm->dm_swat_table.dual_ant_counter, dm->dm_swat_table.single_ant_counter, dm->dm_swat_table.retry_counter, dm->dm_swat_table.aux_fail_detec_counter);
+
+ /* 2 recover the antenna setting */
+
+ if (dm->dm_swat_table.ANTB_ON == false)
+ odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0xfff, (dm_swat_table->swas_no_link_bk_reg948));
- //2 recover the antenna setting
+ PHYDM_DBG(dm, DBG_ANT_DIV, "is_result=(( %d )), Recover Reg[948]= (( %x ))\n\n", dm->dm_swat_table.rssi_ant_dect_result, dm_swat_table->swas_no_link_bk_reg948);
- if(pDM_Odm->DM_SWAT_Table.ANTB_ON == FALSE)
- ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, 0xfff, (pDM_SWAT_Table->SWAS_NoLink_BK_Reg948));
-
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("bResult=(( %d )), Recover Reg[948]= (( %x )) \n\n",pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult, pDM_SWAT_Table->SWAS_NoLink_BK_Reg948 ));
-
}
-
- // Check state reset to default and wait for next time.
- pDM_SWAT_Table->SWAS_NoLink_State = 0;
- pMgntInfo->bScanAntDetect = FALSE;
- return FALSE;
+ /* Check state reset to default and wait for next time. */
+ dm_swat_table->swas_no_link_state = 0;
+ mgnt_info->bScanAntDetect = false;
+
+ return false;
}
#else
- return FALSE;
+ return false;
#endif
-return FALSE;
+ return false;
}
@@ -708,257 +619,225 @@ return FALSE;
-//1 [3. PSD Method] ==========================================================
-
-
+/* 1 [3. PSD method] ========================================================== */
+void
+odm_single_dual_antenna_detection_psd(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ u32 channel_ori;
+ u8 initial_gain = 0x36;
+ u8 tone_idx;
+ u8 tone_lenth_1 = 7, tone_lenth_2 = 4;
+ u16 tone_idx_1[7] = {88, 104, 120, 8, 24, 40, 56};
+ u16 tone_idx_2[4] = {8, 24, 40, 56};
+ u32 psd_report_main[11] = {0}, psd_report_aux[11] = {0};
+ /* u8 tone_lenth_1=4, tone_lenth_2=2; */
+ /* u16 tone_idx_1[4]={88, 120, 24, 56}; */
+ /* u16 tone_idx_2[2]={ 24, 56}; */
+ /* u32 psd_report_main[6]={0}, psd_report_aux[6]={0}; */
+
+ u32 PSD_report_temp, max_psd_report_main = 0, max_psd_report_aux = 0;
+ u32 PSD_power_threshold;
+ u32 main_psd_result = 0, aux_psd_result = 0;
+ u32 regc50, reg948, regb2c, regc14, reg908;
+ u32 i = 0, test_num = 8;
+
+
+ if (dm->support_ic_type != ODM_RTL8723B)
+ return;
+ PHYDM_DBG(dm, DBG_ANT_DIV, "odm_single_dual_antenna_detection_psd()============>\n");
-u4Byte
-odm_GetPSDData(
- IN PVOID pDM_VOID,
- IN u2Byte point,
- IN u1Byte initial_gain)
-{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- u4Byte psd_report;
-
- ODM_SetBBReg(pDM_Odm, 0x808, 0x3FF, point);
- ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 1); //Start PSD calculation, Reg808[22]=0->1
- ODM_StallExecution(150);//Wait for HW PSD report
- ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 0);//Stop PSD calculation, Reg808[22]=1->0
- psd_report = ODM_GetBBReg(pDM_Odm,0x8B4, bMaskDWord) & 0x0000FFFF;//Read PSD report, Reg8B4[15:0]
-
- psd_report = (u4Byte) (odm_ConvertTo_dB(psd_report));//+(u4Byte)(initial_gain);
- return psd_report;
-}
+ /* 2 [ Backup Current RF/BB Settings ] */
+ channel_ori = odm_get_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK);
+ reg948 = odm_get_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD);
+ regb2c = odm_get_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD);
+ regc50 = odm_get_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD);
+ regc14 = odm_get_bb_reg(dm, 0xc14, MASKDWORD);
+ reg908 = odm_get_bb_reg(dm, 0x908, MASKDWORD);
+ /* 2 [ setting for doing PSD function (CH4)] */
+ odm_set_bb_reg(dm, REG_FPGA0_RFMOD, BIT(24), 0); /* disable whole CCK block */
+ odm_write_1byte(dm, REG_TXPAUSE, 0xFF); /* Turn off TX -> Pause TX Queue */
+ odm_set_bb_reg(dm, 0xC14, MASKDWORD, 0x0); /* [ Set IQK Matrix = 0 ] equivalent to [ Turn off CCA] */
-VOID
-ODM_SingleDualAntennaDetection_PSD(
- IN PVOID pDM_VOID
-)
-{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- u4Byte Channel_ori;
- u1Byte initial_gain = 0x36;
- u1Byte tone_idx;
- u1Byte Tone_lenth_1=7, Tone_lenth_2=4;
- u2Byte Tone_idx_1[7]={88, 104, 120, 8, 24, 40, 56};
- u2Byte Tone_idx_2[4]={8, 24, 40, 56};
- u4Byte PSD_report_Main[11]={0}, PSD_report_Aux[11]={0};
- //u1Byte Tone_lenth_1=4, Tone_lenth_2=2;
- //u2Byte Tone_idx_1[4]={88, 120, 24, 56};
- //u2Byte Tone_idx_2[2]={ 24, 56};
- //u4Byte PSD_report_Main[6]={0}, PSD_report_Aux[6]={0};
-
- u4Byte PSD_report_temp,MAX_PSD_report_Main=0,MAX_PSD_report_Aux=0;
- u4Byte PSD_power_threshold;
- u4Byte Main_psd_result=0, Aux_psd_result=0;
- u4Byte Regc50, Reg948, Regb2c,Regc14,Reg908;
- u4Byte i=0,test_num=8;
-
-
- if(pDM_Odm->SupportICType != ODM_RTL8723B)
- return;
-
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection_PSD()============> \n"));
-
- //2 [ Backup Current RF/BB Settings ]
-
- Channel_ori = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask);
- Reg948 = ODM_GetBBReg(pDM_Odm, rS0S1_PathSwitch, bMaskDWord);
- Regb2c = ODM_GetBBReg(pDM_Odm, rAGC_table_select, bMaskDWord);
- Regc50 = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord);
- Regc14 = ODM_GetBBReg(pDM_Odm, 0xc14, bMaskDWord);
- Reg908 = ODM_GetBBReg(pDM_Odm, 0x908, bMaskDWord);
-
- //2 [ Setting for doing PSD function (CH4)]
- ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0); //disable whole CCK block
- ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); // Turn off TX -> Pause TX Queue
- ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, 0x0); // [ Set IQK Matrix = 0 ] equivalent to [ Turn off CCA]
-
- // PHYTXON while loop
- ODM_SetBBReg(pDM_Odm, 0x908, bMaskDWord, 0x803);
- while (ODM_GetBBReg(pDM_Odm, 0xdf4, BIT6))
- {
+ /* PHYTXON while loop */
+ odm_set_bb_reg(dm, 0x908, MASKDWORD, 0x803);
+ while (odm_get_bb_reg(dm, 0xdf4, BIT(6))) {
i++;
- if (i > 1000000)
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Wait in %s() more than %d times!\n", __FUNCTION__, i));
+ if (i > 1000000) {
+ PHYDM_DBG(dm, DBG_ANT_DIV, "Wait in %s() more than %d times!\n", __FUNCTION__, i);
break;
}
}
-
- ODM_SetBBReg(pDM_Odm, 0xc50, 0x7f, initial_gain);
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); // Set RF to CH4 & 40M
- ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, 0xf00000, 0xf); // 3 wire Disable 88c[23:20]=0xf
- ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT14|BIT15, 0x0); //128 pt //Set PSD 128 ptss
- ODM_StallExecution(3000);
-
-
- //2 [ Doing PSD Function in (CH4)]
-
- //Antenna A
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Main-ant (CH4)\n"));
- ODM_SetBBReg(pDM_Odm, 0x948, 0xfff, 0x200);
- ODM_StallExecution(10);
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dbg\n"));
- for (i=0;iPSD_report_Main[tone_idx] )
- PSD_report_Main[tone_idx]+=PSD_report_temp;
+
+ odm_set_bb_reg(dm, 0xc50, 0x7f, initial_gain);
+ odm_set_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); /* Set RF to CH4 & 40M */
+ odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0xf); /* 3 wire Disable 88c[23:20]=0xf */
+ odm_set_bb_reg(dm, REG_FPGA0_PSD_FUNCTION, BIT(14) | BIT15, 0x0); /* 128 pt */ /* Set PSD 128 ptss */
+ ODM_delay_us(3000);
+
+
+ /* 2 [ Doing PSD Function in (CH4)] */
+
+ /* Antenna A */
+ PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Main-ant (CH4)\n");
+ odm_set_bb_reg(dm, 0x948, 0xfff, 0x200);
+ ODM_delay_us(10);
+ PHYDM_DBG(dm, DBG_ANT_DIV, "dbg\n");
+ for (i = 0; i < test_num; i++) {
+ for (tone_idx = 0; tone_idx < tone_lenth_1; tone_idx++) {
+ PSD_report_temp = phydm_get_psd_data(dm, tone_idx_1[tone_idx], initial_gain);
+ /* if( PSD_report_temp>psd_report_main[tone_idx] ) */
+ psd_report_main[tone_idx] += PSD_report_temp;
}
}
- //Antenna B
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Aux-ant (CH4)\n"));
- ODM_SetBBReg(pDM_Odm, 0x948, 0xfff, 0x280);
- ODM_StallExecution(10);
- for (i=0;iPSD_report_Aux[tone_idx] )
- PSD_report_Aux[tone_idx]+=PSD_report_temp;
+ /* Antenna B */
+ PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Aux-ant (CH4)\n");
+ odm_set_bb_reg(dm, 0x948, 0xfff, 0x280);
+ ODM_delay_us(10);
+ for (i = 0; i < test_num; i++) {
+ for (tone_idx = 0; tone_idx < tone_lenth_1; tone_idx++) {
+ PSD_report_temp = phydm_get_psd_data(dm, tone_idx_1[tone_idx], initial_gain);
+ /* if( PSD_report_temp>psd_report_aux[tone_idx] ) */
+ psd_report_aux[tone_idx] += PSD_report_temp;
}
}
- //2 [ Doing PSD Function in (CH8)]
-
- ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, 0xf00000, 0x0); // 3 wire enable 88c[23:20]=0x0
- ODM_StallExecution(3000);
-
- ODM_SetBBReg(pDM_Odm, 0xc50, 0x7f, initial_gain);
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); // Set RF to CH8 & 40M
-
- ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, 0xf00000, 0xf); // 3 wire Disable 88c[23:20]=0xf
- ODM_StallExecution(3000);
-
- //Antenna A
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Main-ant (CH8)\n"));
- ODM_SetBBReg(pDM_Odm, 0x948, 0xfff, 0x200);
- ODM_StallExecution(10);
-
- for (i=0;iPSD_report_Main[tone_idx] )
- PSD_report_Main[Tone_lenth_1+tone_idx]+=PSD_report_temp;
+ /* 2 [ Doing PSD Function in (CH8)] */
+
+ odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0x0); /* 3 wire enable 88c[23:20]=0x0 */
+ ODM_delay_us(3000);
+
+ odm_set_bb_reg(dm, 0xc50, 0x7f, initial_gain);
+ odm_set_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); /* Set RF to CH8 & 40M */
+
+ odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0xf); /* 3 wire Disable 88c[23:20]=0xf */
+ ODM_delay_us(3000);
+
+ /* Antenna A */
+ PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Main-ant (CH8)\n");
+ odm_set_bb_reg(dm, 0x948, 0xfff, 0x200);
+ ODM_delay_us(10);
+
+ for (i = 0; i < test_num; i++) {
+ for (tone_idx = 0; tone_idx < tone_lenth_2; tone_idx++) {
+ PSD_report_temp = phydm_get_psd_data(dm, tone_idx_2[tone_idx], initial_gain);
+ /* if( PSD_report_temp>psd_report_main[tone_idx] ) */
+ psd_report_main[tone_lenth_1 + tone_idx] += PSD_report_temp;
}
}
- //Antenna B
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Aux-ant (CH8)\n"));
- ODM_SetBBReg(pDM_Odm, 0x948, 0xfff, 0x280);
- ODM_StallExecution(10);
+ /* Antenna B */
+ PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Aux-ant (CH8)\n");
+ odm_set_bb_reg(dm, 0x948, 0xfff, 0x280);
+ ODM_delay_us(10);
- for (i=0;iPSD_report_Aux[tone_idx] )
- PSD_report_Aux[Tone_lenth_1+tone_idx]+=PSD_report_temp;
+ for (i = 0; i < test_num; i++) {
+ for (tone_idx = 0; tone_idx < tone_lenth_2; tone_idx++) {
+ PSD_report_temp = phydm_get_psd_data(dm, tone_idx_2[tone_idx], initial_gain);
+ /* if( PSD_report_temp>psd_report_aux[tone_idx] ) */
+ psd_report_aux[tone_lenth_1 + tone_idx] += PSD_report_temp;
}
}
- //2 [ Calculate Result ]
+ /* 2 [ Calculate Result ] */
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\nMain PSD Result: (ALL) \n"));
- for (tone_idx=0;tone_idx<(Tone_lenth_1+Tone_lenth_2);tone_idx++)
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Tone-%d]: %d, \n",(tone_idx+1), PSD_report_Main[tone_idx] ));
- Main_psd_result+= PSD_report_Main[tone_idx];
- if(PSD_report_Main[tone_idx]>MAX_PSD_report_Main)
- MAX_PSD_report_Main=PSD_report_Main[tone_idx];
+ PHYDM_DBG(dm, DBG_ANT_DIV, "\nMain PSD Result: (ALL)\n");
+ for (tone_idx = 0; tone_idx < (tone_lenth_1 + tone_lenth_2); tone_idx++) {
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[Tone-%d]: %d,\n", (tone_idx + 1), psd_report_main[tone_idx]);
+ main_psd_result += psd_report_main[tone_idx];
+ if (psd_report_main[tone_idx] > max_psd_report_main)
+ max_psd_report_main = psd_report_main[tone_idx];
}
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("--------------------------- \nTotal_Main= (( %d ))\n", Main_psd_result));
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MAX_Main = (( %d ))\n", MAX_PSD_report_Main));
-
+ PHYDM_DBG(dm, DBG_ANT_DIV, "--------------------------- \nTotal_Main= (( %d ))\n", main_psd_result);
+ PHYDM_DBG(dm, DBG_ANT_DIV, "MAX_Main = (( %d ))\n", max_psd_report_main);
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\nAux PSD Result: (ALL) \n"));
- for (tone_idx=0;tone_idx<(Tone_lenth_1+Tone_lenth_2);tone_idx++)
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Tone-%d]: %d, \n",(tone_idx+1), PSD_report_Aux[tone_idx] ));
- Aux_psd_result+= PSD_report_Aux[tone_idx];
- if(PSD_report_Aux[tone_idx]>MAX_PSD_report_Aux)
- MAX_PSD_report_Aux=PSD_report_Aux[tone_idx];
+
+ PHYDM_DBG(dm, DBG_ANT_DIV, "\nAux PSD Result: (ALL)\n");
+ for (tone_idx = 0; tone_idx < (tone_lenth_1 + tone_lenth_2); tone_idx++) {
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[Tone-%d]: %d,\n", (tone_idx + 1), psd_report_aux[tone_idx]);
+ aux_psd_result += psd_report_aux[tone_idx];
+ if (psd_report_aux[tone_idx] > max_psd_report_aux)
+ max_psd_report_aux = psd_report_aux[tone_idx];
}
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("--------------------------- \nTotal_Aux= (( %d ))\n", Aux_psd_result));
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MAX_Aux = (( %d ))\n\n", MAX_PSD_report_Aux));
-
- //Main_psd_result=Main_psd_result-MAX_PSD_report_Main;
- //Aux_psd_result=Aux_psd_result-MAX_PSD_report_Aux;
- PSD_power_threshold=(Main_psd_result*7)>>3;
-
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Main_result , Aux_result ] = [ %d , %d ], PSD_power_threshold=(( %d ))\n", Main_psd_result, Aux_psd_result,PSD_power_threshold));
-
- //3 [ Dual Antenna ]
- if(Aux_psd_result >= PSD_power_threshold )
- {
- if(pDM_Odm->DM_SWAT_Table.ANTB_ON == FALSE)
- {
- pDM_Odm->DM_SWAT_Table.ANTA_ON = TRUE;
- pDM_Odm->DM_SWAT_Table.ANTB_ON = TRUE;
- }
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SwAntDivCheckBeforeLink(): Dual antenna\n"));
-
- // set bt coexDM from 1ant coexDM to 2ant coexDM
- //BT_SetBtCoexAntNum(pAdapter, BT_COEX_ANT_TYPE_DETECTED, 2);
-
- // Init antenna diversity
- pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV;
- ODM_AntDivInit(pDM_Odm);
+ PHYDM_DBG(dm, DBG_ANT_DIV, "--------------------------- \nTotal_Aux= (( %d ))\n", aux_psd_result);
+ PHYDM_DBG(dm, DBG_ANT_DIV, "MAX_Aux = (( %d ))\n\n", max_psd_report_aux);
+
+ /* main_psd_result=main_psd_result-max_psd_report_main; */
+ /* aux_psd_result=aux_psd_result-max_psd_report_aux; */
+ PSD_power_threshold = (main_psd_result * 7) >> 3;
+
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[ Main_result, Aux_result ] = [ %d , %d ], PSD_power_threshold=(( %d ))\n", main_psd_result, aux_psd_result, PSD_power_threshold);
+
+ /* 3 [ Dual Antenna ] */
+ if (aux_psd_result >= PSD_power_threshold) {
+ if (dm->dm_swat_table.ANTB_ON == false) {
+ dm->dm_swat_table.ANTA_ON = true;
+ dm->dm_swat_table.ANTB_ON = true;
}
- //3 [ Single Antenna ]
- else
- {
- if(pDM_Odm->DM_SWAT_Table.ANTB_ON == TRUE)
- {
- pDM_Odm->DM_SWAT_Table.ANTA_ON = TRUE;
- pDM_Odm->DM_SWAT_Table.ANTB_ON = FALSE;
+ PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link(): Dual antenna\n");
+
+ /* set bt coexDM from 1ant coexDM to 2ant coexDM */
+ /* bt_set_bt_coex_ant_num(adapter, BT_COEX_ANT_TYPE_DETECTED, 2); */
+
+ /* Init antenna diversity */
+ dm->support_ability |= ODM_BB_ANT_DIV;
+ odm_ant_div_init(dm);
+ }
+ /* 3 [ Single Antenna ] */
+ else {
+ if (dm->dm_swat_table.ANTB_ON == true) {
+ dm->dm_swat_table.ANTA_ON = true;
+ dm->dm_swat_table.ANTB_ON = false;
}
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): Single antenna\n"));
+ PHYDM_DBG(dm, DBG_ANT_DIV, "odm_sw_ant_div_check_before_link(): Single antenna\n");
}
- //2 [ Recover all parameters ]
-
- ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask,Channel_ori);
- ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, 0xf00000, 0x0); // 3 wire enable 88c[23:20]=0x0
- ODM_SetBBReg(pDM_Odm, 0xc50, 0x7f, Regc50);
-
- ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, bMaskDWord, Reg948);
- ODM_SetBBReg(pDM_Odm, rAGC_table_select, bMaskDWord, Regb2c);
-
- ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 1); //enable whole CCK block
- ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x0); //Turn on TX // Resume TX Queue
- ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, Regc14); // [ Set IQK Matrix = 0 ] equivalent to [ Turn on CCA]
- ODM_SetBBReg(pDM_Odm, 0x908, bMaskDWord, Reg908);
-
+ /* 2 [ Recover all parameters ] */
+
+ odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, channel_ori);
+ odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0x0); /* 3 wire enable 88c[23:20]=0x0 */
+ odm_set_bb_reg(dm, 0xc50, 0x7f, regc50);
+
+ odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD, reg948);
+ odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD, regb2c);
+
+ odm_set_bb_reg(dm, REG_FPGA0_RFMOD, BIT(24), 1); /* enable whole CCK block */
+ odm_write_1byte(dm, REG_TXPAUSE, 0x0); /* Turn on TX */ /* Resume TX Queue */
+ odm_set_bb_reg(dm, 0xC14, MASKDWORD, regc14); /* [ Set IQK Matrix = 0 ] equivalent to [ Turn on CCA] */
+ odm_set_bb_reg(dm, 0x908, MASKDWORD, reg908);
+
return;
}
#endif
void
-odm_SwAntDetectInit(
- IN PVOID pDM_VOID
- )
+odm_sw_ant_detect_init(
+ void *dm_void
+)
{
-#if(defined(CONFIG_ANT_DETECTION))
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
-
- //pDM_SWAT_Table->PreAntenna = MAIN_ANT;
- //pDM_SWAT_Table->CurAntenna = MAIN_ANT;
- pDM_SWAT_Table->SWAS_NoLink_State = 0;
- pDM_SWAT_Table->Pre_Aux_FailDetec = FALSE;
- pDM_SWAT_Table->SWAS_NoLink_BK_Reg948 = 0xff;
+#if (defined(CONFIG_ANT_DETECTION))
+#if (RTL8723B_SUPPORT == 1)
+
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
+
+ if (dm->support_ic_type != ODM_RTL8723B)
+ return;
+
+ /* dm_swat_table->pre_antenna = MAIN_ANT; */
+ /* dm_swat_table->cur_antenna = MAIN_ANT; */
+ dm_swat_table->swas_no_link_state = 0;
+ dm_swat_table->pre_aux_fail_detec = false;
+ dm_swat_table->swas_no_link_bk_reg948 = 0xff;
+
+ #ifdef CONFIG_PSD_TOOL
+ phydm_psd_init(dm);
+ #endif
+#endif
#endif
}
-
diff --git a/hal/phydm/phydm_antdect.h b/hal/phydm/phydm_antdect.h
index 8cf60e8..bf85c9b 100644
--- a/hal/phydm/phydm_antdect.h
+++ b/hal/phydm/phydm_antdect.h
@@ -1,98 +1,100 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
- *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
*
+ * Larry Finger
*
- ******************************************************************************/
-
+ *****************************************************************************/
+
#ifndef __PHYDMANTDECT_H__
#define __PHYDMANTDECT_H__
#define ANTDECT_VERSION "2.1" /*2015.07.29 by YuChen*/
-#if(defined(CONFIG_ANT_DETECTION))
-//#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE))
-//ANT Test
-#define ANTTESTALL 0x00 /*Ant A or B will be Testing*/
-#define ANTTESTA 0x01 /*Ant A will be Testing*/
-#define ANTTESTB 0x02 /*Ant B will be testing*/
+#if (defined(CONFIG_ANT_DETECTION))
+/* #if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE)) */
+/* ANT Test */
+#define ANTTESTALL 0x00 /*ant A or B will be Testing*/
+#define ANTTESTA 0x01 /*ant A will be Testing*/
+#define ANTTESTB 0x02 /*ant B will be testing*/
-#define MAX_ANTENNA_DETECTION_CNT 10
+#define MAX_ANTENNA_DETECTION_CNT 10
-typedef struct _ANT_DETECTED_INFO{
- BOOLEAN bAntDetected;
- u4Byte dBForAntA;
- u4Byte dBForAntB;
- u4Byte dBForAntO;
-}ANT_DETECTED_INFO, *PANT_DETECTED_INFO;
+struct _ANT_DETECTED_INFO {
+ boolean is_ant_detected;
+ u32 db_for_ant_a;
+ u32 db_for_ant_b;
+ u32 db_for_ant_o;
+};
-typedef enum tag_SW_Antenna_Switch_Definition
-{
- Antenna_A = 1,
- Antenna_B = 2,
- Antenna_MAX = 3,
-}DM_SWAS_E;
+enum dm_swas {
+ antenna_a = 1,
+ antenna_b = 2,
+ antenna_max = 3,
+};
-//1 [1. Single Tone Method] ===================================================
+/* 1 [1. Single Tone method] =================================================== */
-VOID
-ODM_SingleDualAntennaDefaultSetting(
- IN PVOID pDM_VOID
- );
+void
+odm_single_dual_antenna_default_setting(
+ void *dm_void
+);
-BOOLEAN
-ODM_SingleDualAntennaDetection(
- IN PVOID pDM_VOID,
- IN u1Byte mode
- );
+boolean
+odm_single_dual_antenna_detection(
+ void *dm_void,
+ u8 mode
+);
-//1 [2. Scan AP RSSI Method] ==================================================
+/* 1 [2. Scan AP RSSI method] ================================================== */
-#define SwAntDivCheckBeforeLink ODM_SwAntDivCheckBeforeLink
+#define sw_ant_div_check_before_link odm_sw_ant_div_check_before_link
-BOOLEAN
-ODM_SwAntDivCheckBeforeLink(
- IN PVOID pDM_VOID
- );
+boolean
+odm_sw_ant_div_check_before_link(
+ void *dm_void
+);
-//1 [3. PSD Method] ==========================================================
+/* 1 [3. PSD method] ========================================================== */
-VOID
-ODM_SingleDualAntennaDetection_PSD(
- IN PVOID pDM_VOID
+void
+odm_single_dual_antenna_detection_psd(
+ void *dm_void
);
#endif
-VOID
-odm_SwAntDetectInit(
- IN PVOID pDM_VOID
- );
+void
+odm_sw_ant_detect_init(
+ void *dm_void
+);
#endif
-
-
diff --git a/hal/phydm/phydm_antdiv.c b/hal/phydm/phydm_antdiv.c
index e155f5c..ffa3ec4 100644
--- a/hal/phydm/phydm_antdiv.c
+++ b/hal/phydm/phydm_antdiv.c
@@ -1,5367 +1,4702 @@
/******************************************************************************
*
- * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
- *
+ * Copyright(c) 2007 - 2017 Realtek Corporation.
+ *
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
*
+ * Larry Finger
*
- ******************************************************************************/
+ *****************************************************************************/
-//============================================================
-// include files
-//============================================================
+/* ************************************************************
+ * include files
+ * ************************************************************ */
#include "mp_precomp.h"
#include "phydm_precomp.h"
-//======================================================
-// when antenna test utility is on or some testing need to disable antenna diversity
-// call this function to disable all ODM related mechanisms which will switch antenna.
-//======================================================
-VOID
-ODM_StopAntennaSwitchDm(
- IN PVOID pDM_VOID
- )
+/* ******************************************************
+ * when antenna test utility is on or some testing need to disable antenna diversity
+ * call this function to disable all ODM related mechanisms which will switch antenna.
+ * ****************************************************** */
+void
+odm_stop_antenna_switch_dm(
+ void *dm_void
+)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- // disable ODM antenna diversity
- pDM_Odm->SupportAbility &= ~ODM_BB_ANT_DIV;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("STOP Antenna Diversity \n"));
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ /* disable ODM antenna diversity */
+ dm->support_ability &= ~ODM_BB_ANT_DIV;
+ odm_ant_div_on_off(dm, ANTDIV_OFF);
+ odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
+ PHYDM_DBG(dm, DBG_ANT_DIV, "STOP Antenna Diversity\n");
}
-VOID
+void
phydm_enable_antenna_diversity(
- IN PVOID pDM_VOID
- )
+ void *dm_void
+)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
- pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("AntDiv is enabled & Re-Init AntDiv\n"));
- odm_AntennaDiversityInit(pDM_Odm);
+ dm->support_ability |= ODM_BB_ANT_DIV;
+ dm->antdiv_select = 0;
+ PHYDM_DBG(dm, DBG_ANT_DIV, "AntDiv is enabled & Re-Init AntDiv\n");
+ odm_antenna_diversity_init(dm);
}
-VOID
-ODM_SetAntConfig(
- IN PVOID pDM_VOID,
- IN u1Byte antSetting // 0=A, 1=B, 2=C, ....
- )
+void
+odm_set_ant_config(
+ void *dm_void,
+ u8 ant_setting /* 0=A, 1=B, 2=C, .... */
+)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- if (pDM_Odm->SupportICType == ODM_RTL8723B) {
- if (antSetting == 0) /* ant A*/
- ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000000);
- else if (antSetting == 1)
- ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280);
- } else if (pDM_Odm->SupportICType == ODM_RTL8723D) {
- if (antSetting == 0) /* ant A*/
- ODM_SetBBReg(pDM_Odm, 0x948, bMaskLWord, 0x0000);
- else if (antSetting == 1)
- ODM_SetBBReg(pDM_Odm, 0x948, bMaskLWord, 0x0280);
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ if (dm->support_ic_type == ODM_RTL8723B) {
+ if (ant_setting == 0) /* ant A*/
+ odm_set_bb_reg(dm, 0x948, MASKDWORD, 0x00000000);
+ else if (ant_setting == 1)
+ odm_set_bb_reg(dm, 0x948, MASKDWORD, 0x00000280);
+ } else if (dm->support_ic_type == ODM_RTL8723D) {
+ if (ant_setting == 0) /* ant A*/
+ odm_set_bb_reg(dm, 0x948, MASKLWORD, 0x0000);
+ else if (ant_setting == 1)
+ odm_set_bb_reg(dm, 0x948, MASKLWORD, 0x0280);
}
}
-//======================================================
+/* ****************************************************** */
-VOID
-ODM_SwAntDivRestAfterLink(
- IN PVOID pDM_VOID
- )
+void
+odm_sw_ant_div_rest_after_link(
+ void *dm_void
+)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
- pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
- u4Byte i;
-
- if (pDM_Odm->AntDivType == S0S1_SW_ANTDIV) {
-
- pDM_SWAT_Table->try_flag = SWAW_STEP_INIT;
- pDM_SWAT_Table->RSSI_Trying = 0;
- pDM_SWAT_Table->Double_chk_flag= 0;
-
- pDM_FatTable->RxIdleAnt=MAIN_ANT;
-
- for (i=0; iMainAnt_Sum[i] = 0;
- pDM_FatTable->AuxAnt_Sum[i] = 0;
- pDM_FatTable->MainAnt_Cnt[i] = 0;
- pDM_FatTable->AuxAnt_Cnt[i] = 0;
- }
-
+#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
+ struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+ u32 i;
+
+ if (dm->ant_div_type == S0S1_SW_ANTDIV) {
+ dm_swat_table->try_flag = SWAW_STEP_INIT;
+ dm_swat_table->rssi_trying = 0;
+ dm_swat_table->double_chk_flag = 0;
+ fat_tab->rx_idle_ant = MAIN_ANT;
+
+ for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
+ phydm_antdiv_reset_statistic(dm, i);
}
+
+#endif
}
-
-#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
-VOID
-odm_AntDiv_on_off(
- IN PVOID pDM_VOID ,
- IN u1Byte swch
- )
+void
+odm_ant_div_on_off(
+ void *dm_void,
+ u8 swch
+)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
-
- if(pDM_FatTable->AntDiv_OnOff != swch)
- {
- if (pDM_Odm->AntDivType == S0S1_SW_ANTDIV)
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+
+ if (fat_tab->ant_div_on_off != swch) {
+ if (dm->ant_div_type == S0S1_SW_ANTDIV)
return;
- if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT)
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("(( Turn %s )) N-Series HW-AntDiv block\n",(swch==ANTDIV_ON)?"ON" : "OFF"));
- ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, swch);
- ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, swch);
-
- }
- else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT)
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("(( Turn %s )) AC-Series HW-AntDiv block\n",(swch==ANTDIV_ON)?"ON" : "OFF"));
- if (pDM_Odm->SupportICType == ODM_RTL8812) {
- ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, swch); //OFDM AntDiv function block enable
- ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, swch); //CCK AntDiv function block enable
+ if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT) {
+ PHYDM_DBG(dm, DBG_ANT_DIV, "(( Turn %s )) N-Series HW-AntDiv block\n", (swch == ANTDIV_ON) ? "ON" : "OFF");
+ odm_set_bb_reg(dm, 0xc50, BIT(7), swch);
+ odm_set_bb_reg(dm, 0xa00, BIT(15), swch);
+
+#if (RTL8723D_SUPPORT == 1)
+ /*Mingzhi 2017-05-08*/
+ if (dm->support_ic_type == ODM_RTL8723D) {
+ if (swch == ANTDIV_ON) {
+ odm_set_bb_reg(dm, 0xce0, BIT(1), 1);
+ odm_set_bb_reg(dm, 0x948, BIT(6), 1); /*1:HW ctrl 0:SW ctrl*/
+ }
+ else{
+ odm_set_bb_reg(dm, 0xce0, BIT(1), 0);
+ odm_set_bb_reg(dm, 0x948, BIT(6), 0); /*1:HW ctrl 0:SW ctrl*/
+ }
+ }
+#endif
+
+ } else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) {
+ PHYDM_DBG(dm, DBG_ANT_DIV, "(( Turn %s )) AC-Series HW-AntDiv block\n", (swch == ANTDIV_ON) ? "ON" : "OFF");
+ if (dm->support_ic_type & ODM_RTL8812) {
+ odm_set_bb_reg(dm, 0xc50, BIT(7), swch); /* OFDM AntDiv function block enable */
+ odm_set_bb_reg(dm, 0xa00, BIT(15), swch); /* CCK AntDiv function block enable */
} else {
- ODM_SetBBReg(pDM_Odm, 0x8D4 , BIT24, swch); //OFDM AntDiv function block enable
-
- if( (pDM_Odm->CutVersion >= ODM_CUT_C) && (pDM_Odm->SupportICType == ODM_RTL8821) && ( pDM_Odm->AntDivType != S0S1_SW_ANTDIV))
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("(( Turn %s )) CCK HW-AntDiv block\n",(swch==ANTDIV_ON)?"ON" : "OFF"));
- ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, swch);
- ODM_SetBBReg(pDM_Odm, 0xA00 , BIT15, swch); //CCK AntDiv function block enable
+ odm_set_bb_reg(dm, 0x8D4, BIT(24), swch); /* OFDM AntDiv function block enable */
+
+ if ((dm->cut_version >= ODM_CUT_C) && (dm->support_ic_type == ODM_RTL8821) && (dm->ant_div_type != S0S1_SW_ANTDIV)) {
+ PHYDM_DBG(dm, DBG_ANT_DIV, "(( Turn %s )) CCK HW-AntDiv block\n", (swch == ANTDIV_ON) ? "ON" : "OFF");
+ odm_set_bb_reg(dm, 0x800, BIT(25), swch);
+ odm_set_bb_reg(dm, 0xA00, BIT(15), swch); /* CCK AntDiv function block enable */
+ } else if (dm->support_ic_type == ODM_RTL8821C) {
+ PHYDM_DBG(dm, DBG_ANT_DIV, "(( Turn %s )) CCK HW-AntDiv block\n", (swch == ANTDIV_ON) ? "ON" : "OFF");
+ odm_set_bb_reg(dm, 0x800, BIT(25), swch);
+ odm_set_bb_reg(dm, 0xA00, BIT(15), swch); /* CCK AntDiv function block enable */
}
- }
+ }
}
}
- pDM_FatTable->AntDiv_OnOff =swch;
-
+ fat_tab->ant_div_on_off = swch;
+
}
-VOID
-phydm_FastTraining_enable(
- IN PVOID pDM_VOID,
- IN u1Byte swch
- )
+void
+odm_tx_by_tx_desc_or_reg(
+ void *dm_void,
+ u8 swch
+)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- u1Byte enable;
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+ u8 enable;
- if (swch == FAT_ON)
- enable=1;
+ if (fat_tab->b_fix_tx_ant == NO_FIX_TX_ANT)
+ enable = (swch == TX_BY_DESC) ? 1 : 0;
else
- enable=0;
+ enable = 0;/*Force TX by Reg*/
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Fast Ant Training_en = ((%d))\n", enable));
+ if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) {
+ if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT)
+ odm_set_bb_reg(dm, 0x80c, BIT(21), enable);
+ else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT)
+ odm_set_bb_reg(dm, 0x900, BIT(18), enable);
- if (pDM_Odm->SupportICType == ODM_RTL8188E) {
- ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, enable); /*enable fast training*/
- /**/
- } else if (pDM_Odm->SupportICType == ODM_RTL8192E) {
- ODM_SetBBReg(pDM_Odm, 0xB34 , BIT28, enable); /*enable fast training (path-A)*/
- /*ODM_SetBBReg(pDM_Odm, 0xB34 , BIT29, enable);*/ /*enable fast training (path-B)*/
- } else if (pDM_Odm->SupportICType == ODM_RTL8821) {
- ODM_SetBBReg(pDM_Odm, 0x900 , BIT19, enable); /*enable fast training */
- /**/
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[AntDiv] TX_Ant_BY (( %s ))\n", (enable == TX_BY_DESC) ? "DESC" : "REG");
}
}
-phydm_keep_RxAckAnt_By_TxAnt_time(
- IN PVOID pDM_VOID,
- IN u4Byte time
- )
+#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
+void
+phydm_antdiv_reset_statistic(
+ void *dm_void,
+ u32 macid
+)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+
+ fat_tab->main_ant_sum[macid] = 0;
+ fat_tab->aux_ant_sum[macid] = 0;
+ fat_tab->main_ant_cnt[macid] = 0;
+ fat_tab->aux_ant_cnt[macid] = 0;
+ fat_tab->main_ant_sum_cck[macid] = 0;
+ fat_tab->aux_ant_sum_cck[macid] = 0;
+ fat_tab->main_ant_cnt_cck[macid] = 0;
+ fat_tab->aux_ant_cnt_cck[macid] = 0;
+}
- /* Timming issue: keep Rx ant after tx for ACK ( time x 3.2 mu sec)*/
- if (pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT) {
-
- ODM_SetBBReg(pDM_Odm, 0xE20, BIT23|BIT22|BIT21|BIT20, time);
- /**/
- } else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT) {
+void
+phydm_fast_training_enable(
+ void *dm_void,
+ u8 swch
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ u8 enable;
+
+ if (swch == FAT_ON)
+ enable = 1;
+ else
+ enable = 0;
+
+ PHYDM_DBG(dm, DBG_ANT_DIV, "Fast ant Training_en = ((%d))\n", enable);
- ODM_SetBBReg(pDM_Odm, 0x818, BIT23|BIT22|BIT21|BIT20, time);
+ if (dm->support_ic_type == ODM_RTL8188E) {
+ odm_set_bb_reg(dm, 0xe08, BIT(16), enable); /*enable fast training*/
+ /**/
+ } else if (dm->support_ic_type == ODM_RTL8192E) {
+ odm_set_bb_reg(dm, 0xB34, BIT(28), enable); /*enable fast training (path-A)*/
+ /*odm_set_bb_reg(dm, 0xB34, BIT(29), enable);*/ /*enable fast training (path-B)*/
+ } else if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8822B)) {
+ odm_set_bb_reg(dm, 0x900, BIT(19), enable); /*enable fast training */
/**/
}
}
-VOID
-odm_Tx_By_TxDesc_or_Reg(
- IN PVOID pDM_VOID,
- IN u1Byte swch
- )
+void
+phydm_keep_rx_ack_ant_by_tx_ant_time(
+ void *dm_void,
+ u32 time
+)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
- u1Byte enable;
-
- if (pDM_FatTable->b_fix_tx_ant == NO_FIX_TX_ANT)
- enable = (swch == TX_BY_DESC) ? 1 : 0;
- else
- enable = 0;/*Force TX by Reg*/
-
- if(pDM_Odm->AntDivType != CGCS_RX_HW_ANTDIV)
- {
- if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT)
- {
- ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, enable);
- }
- else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT)
- {
- ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, enable);
- }
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[AntDiv] TX_Ant_BY (( %s ))\n", (enable == TX_BY_DESC) ? "DESC":"REG"));
+ /* Timming issue: keep Rx ant after tx for ACK ( time x 3.2 mu sec)*/
+ if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT) {
+ odm_set_bb_reg(dm, 0xE20, BIT(23) | BIT(22) | BIT(21) | BIT(20), time);
+ /**/
+ } else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) {
+ odm_set_bb_reg(dm, 0x818, BIT(23) | BIT(22) | BIT(21) | BIT(20), time);
+ /**/
}
}
-VOID
-ODM_UpdateRxIdleAnt(
- IN PVOID pDM_VOID,
- IN u1Byte Ant
- )
+void
+odm_update_rx_idle_ant(
+ void *dm_void,
+ u8 ant
+)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
- u4Byte DefaultAnt, OptionalAnt, value32, Default_tx_Ant;
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+ u32 default_ant, optional_ant, value32, default_tx_ant;
- if(pDM_FatTable->RxIdleAnt != Ant)
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] RxIdleAnt =%s\n",(Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
+ if (fat_tab->rx_idle_ant != ant) {
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[ Update Rx-Idle-ant ] rx_idle_ant =%s\n", (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
- if(!(pDM_Odm->SupportICType & ODM_RTL8723B))
- pDM_FatTable->RxIdleAnt = Ant;
+ if (!(dm->support_ic_type & ODM_RTL8723B))
+ fat_tab->rx_idle_ant = ant;
- if(Ant == MAIN_ANT)
- {
- DefaultAnt = ANT1_2G;
- OptionalAnt = ANT2_2G;
- }
- else
- {
- DefaultAnt = ANT2_2G;
- OptionalAnt = ANT1_2G;
+ if (ant == MAIN_ANT) {
+ default_ant = ANT1_2G;
+ optional_ant = ANT2_2G;
+ } else {
+ default_ant = ANT2_2G;
+ optional_ant = ANT1_2G;
}
-
- if (pDM_FatTable->b_fix_tx_ant != NO_FIX_TX_ANT)
- Default_tx_Ant = (pDM_FatTable->b_fix_tx_ant == FIX_TX_AT_MAIN) ? 0 : 1;
+
+ if (fat_tab->b_fix_tx_ant != NO_FIX_TX_ANT)
+ default_tx_ant = (fat_tab->b_fix_tx_ant == FIX_TX_AT_MAIN) ? 0 : 1;
else
- Default_tx_Ant = DefaultAnt;
-
- if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT)
- {
- if(pDM_Odm->SupportICType==ODM_RTL8192E)
- {
- ODM_SetBBReg(pDM_Odm, 0xB38 , BIT5|BIT4|BIT3, DefaultAnt); //Default RX
- ODM_SetBBReg(pDM_Odm, 0xB38 , BIT8|BIT7|BIT6, OptionalAnt);//Optional RX
- ODM_SetBBReg(pDM_Odm, 0x860, BIT14|BIT13|BIT12, DefaultAnt);//Default TX
+ default_tx_ant = default_ant;
+
+ if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT) {
+ if (dm->support_ic_type == ODM_RTL8192E) {
+ odm_set_bb_reg(dm, 0xB38, BIT(5) | BIT(4) | BIT(3), default_ant); /* Default RX */
+ odm_set_bb_reg(dm, 0xB38, BIT(8) | BIT(7) | BIT(6), optional_ant); /* Optional RX */
+ odm_set_bb_reg(dm, 0x860, BIT(14) | BIT(13) | BIT(12), default_ant); /* Default TX */
}
- #if (RTL8723B_SUPPORT == 1)
- else if (pDM_Odm->SupportICType == ODM_RTL8723B) {
-
- value32 = ODM_GetBBReg(pDM_Odm, 0x948, 0xFFF);
-
- if(value32 !=0x280)
- ODM_UpdateRxIdleAnt_8723B(pDM_Odm, Ant, DefaultAnt, OptionalAnt);
+#if (RTL8723B_SUPPORT == 1)
+ else if (dm->support_ic_type == ODM_RTL8723B) {
+ value32 = odm_get_bb_reg(dm, 0x948, 0xFFF);
+
+ if (value32 != 0x280)
+ odm_update_rx_idle_ant_8723b(dm, ant, default_ant, optional_ant);
else
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: Fail to set RX antenna due to 0x948 = 0x280\n"));
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to 0x948 = 0x280\n");
}
- #endif
- else { /*8188E & 8188F*/
+#endif
- if (pDM_Odm->SupportICType == ODM_RTL8723D) {
- #if (RTL8723D_SUPPORT == 1)
- phydm_set_tx_ant_pwr_8723d(pDM_Odm, Ant);
- #endif
+#if (RTL8723D_SUPPORT == 1) /*Mingzhi 2017-05-08*/
+ else if (dm->support_ic_type == ODM_RTL8723D) {
+ phydm_set_tx_ant_pwr_8723d(dm, ant);
+ odm_update_rx_idle_ant_8723d(dm, ant, default_ant, optional_ant);
+
+ }
+#endif
+
+ else { /*8188E & 8188F*/
+/*
+ if (dm->support_ic_type == ODM_RTL8723D) {
+#if (RTL8723D_SUPPORT == 1)
+ phydm_set_tx_ant_pwr_8723d(dm, ant);
+#endif
}
- #if (RTL8188F_SUPPORT == 1)
- else if (pDM_Odm->SupportICType == ODM_RTL8188F) {
- phydm_update_rx_idle_antenna_8188F(pDM_Odm, DefaultAnt);
+*/
+#if (RTL8188F_SUPPORT == 1)
+ if (dm->support_ic_type == ODM_RTL8188F) {
+ phydm_update_rx_idle_antenna_8188F(dm, default_ant);
/**/
}
- #endif
-
- ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, DefaultAnt); /*Default RX*/
- ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, OptionalAnt); /*Optional RX*/
- ODM_SetBBReg(pDM_Odm, 0x860, BIT14|BIT13|BIT12, Default_tx_Ant); /*Default TX*/
+#endif
+
+ odm_set_bb_reg(dm, 0x864, BIT(5) | BIT(4) | BIT(3), default_ant); /*Default RX*/
+ odm_set_bb_reg(dm, 0x864, BIT(8) | BIT(7) | BIT(6), optional_ant); /*Optional RX*/
+ odm_set_bb_reg(dm, 0x860, BIT(14) | BIT(13) | BIT(12), default_tx_ant); /*Default TX*/
}
- }
- else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT)
- {
- u2Byte value16 = ODM_Read2Byte(pDM_Odm, ODM_REG_TRMUX_11AC+2);
- //
- // 2014/01/14 MH/Luke.Lee Add direct write for register 0xc0a to prevnt
- // incorrect 0xc08 bit0-15 .We still not know why it is changed.
- //
- value16 &= ~(BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3);
- value16 |= ((u2Byte)DefaultAnt <<3);
- value16 |= ((u2Byte)OptionalAnt <<6);
- value16 |= ((u2Byte)DefaultAnt <<9);
- ODM_Write2Byte(pDM_Odm, ODM_REG_TRMUX_11AC+2, value16);
- /*
- ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC , BIT21|BIT20|BIT19, DefaultAnt); //Default RX
- ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC , BIT24|BIT23|BIT22, OptionalAnt);//Optional RX
- ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC , BIT27|BIT26|BIT25, DefaultAnt); //Default TX
- */
+ } else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) {
+ u16 value16 = odm_read_2byte(dm, ODM_REG_TRMUX_11AC + 2);
+ /* */
+ /* 2014/01/14 MH/Luke.Lee Add direct write for register 0xc0a to prevnt */
+ /* incorrect 0xc08 bit0-15 .We still not know why it is changed. */
+ /* */
+ value16 &= ~(BIT(11) | BIT(10) | BIT(9) | BIT(8) | BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT(3));
+ value16 |= ((u16)default_ant << 3);
+ value16 |= ((u16)optional_ant << 6);
+ value16 |= ((u16)default_ant << 9);
+ odm_write_2byte(dm, ODM_REG_TRMUX_11AC + 2, value16);
+#if 0
+ odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, BIT(21) | BIT20 | BIT19, default_ant); /* Default RX */
+ odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, BIT(24) | BIT23 | BIT22, optional_ant); /* Optional RX */
+ odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, BIT(27) | BIT26 | BIT25, default_ant); /* Default TX */
+#endif
}
- if (pDM_Odm->SupportICType == ODM_RTL8188E)
- {
- ODM_SetMACReg(pDM_Odm, 0x6D8 , BIT7|BIT6, Default_tx_Ant); /*PathA Resp Tx*/
+ if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814A)) {
+ odm_set_mac_reg(dm, 0x6D8, 0x7, default_tx_ant); /*PathA Resp Tx*/
/**/
- }
- else
- {
- ODM_SetMACReg(pDM_Odm, 0x6D8 , BIT10|BIT9|BIT8, Default_tx_Ant); /*PathA Resp Tx*/
+ } else if (dm->support_ic_type == ODM_RTL8188E) {
+ odm_set_mac_reg(dm, 0x6D8, BIT(7) | BIT(6), default_tx_ant); /*PathA Resp Tx*/
/**/
- }
+ } else {
+ odm_set_mac_reg(dm, 0x6D8, BIT(10) | BIT(9) | BIT(8), default_tx_ant); /*PathA Resp Tx*/
+ /**/
+ }
- }
- else// pDM_FatTable->RxIdleAnt == Ant
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Stay in Ori-Ant ] RxIdleAnt =%s\n",(Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
- pDM_FatTable->RxIdleAnt = Ant;
+ } else { /* fat_tab->rx_idle_ant == ant */
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[ Stay in Ori-ant ] rx_idle_ant =%s\n", (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
+ fat_tab->rx_idle_ant = ant;
}
}
-VOID
-odm_UpdateTxAnt(
- IN PVOID pDM_VOID,
- IN u1Byte Ant,
- IN u4Byte MacId
- )
+void
+phydm_set_antdiv_val(
+ void *dm_void,
+ u32 *val_buf,
+ u8 val_len
+)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
- u1Byte TxAnt;
-
- if (pDM_FatTable->b_fix_tx_ant != NO_FIX_TX_ANT)
- Ant = (pDM_FatTable->b_fix_tx_ant == FIX_TX_AT_MAIN) ? MAIN_ANT : AUX_ANT;
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
- if (pDM_Odm->AntDivType==CG_TRX_SMART_ANTDIV)
- {
- TxAnt=Ant;
- }
- else
- {
- if(Ant == MAIN_ANT)
- TxAnt = ANT1_2G;
- else
- TxAnt = ANT2_2G;
+ if (val_len != 1) {
+ PHYDM_DBG(dm, ODM_COMP_API, "[Error][antdiv]Need val_len=1\n");
+ return;
}
- pDM_FatTable->antsel_a[MacId] = TxAnt&BIT0;
- pDM_FatTable->antsel_b[MacId] = (TxAnt&BIT1)>>1;
- pDM_FatTable->antsel_c[MacId] = (TxAnt&BIT2)>>2;
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Set TX-DESC value]: MacID:(( %d )), TxAnt = (( %s ))\n", MacId, (Ant == MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
- //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=(( 3'b%d%d%d ))\n",pDM_FatTable->antsel_c[MacId] , pDM_FatTable->antsel_b[MacId] , pDM_FatTable->antsel_a[MacId] ));
-
+ odm_update_rx_idle_ant(dm, (u8)(*val_buf));
+}
+
+void
+odm_update_tx_ant(
+ void *dm_void,
+ u8 ant,
+ u32 mac_id
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+ u8 tx_ant;
+
+ if (fat_tab->b_fix_tx_ant != NO_FIX_TX_ANT)
+ ant = (fat_tab->b_fix_tx_ant == FIX_TX_AT_MAIN) ? MAIN_ANT : AUX_ANT;
+
+ if (dm->ant_div_type == CG_TRX_SMART_ANTDIV)
+ tx_ant = ant;
+ else {
+ if (ant == MAIN_ANT)
+ tx_ant = ANT1_2G;
+ else
+ tx_ant = ANT2_2G;
+ }
+
+ fat_tab->antsel_a[mac_id] = tx_ant & BIT(0);
+ fat_tab->antsel_b[mac_id] = (tx_ant & BIT(1)) >> 1;
+ fat_tab->antsel_c[mac_id] = (tx_ant & BIT(2)) >> 2;
+
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[Set TX-DESC value]: mac_id:(( %d )), tx_ant = (( %s ))\n", mac_id, (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
+ /* PHYDM_DBG(dm,DBG_ANT_DIV,"antsel_tr_mux=(( 3'b%d%d%d ))\n",fat_tab->antsel_c[mac_id] , fat_tab->antsel_b[mac_id] , fat_tab->antsel_a[mac_id] ); */
+
}
#ifdef BEAMFORMING_SUPPORT
-#if(DM_ODM_SUPPORT_TYPE == ODM_AP)
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
-VOID
-odm_BDC_Init(
- IN PVOID pDM_VOID
- )
+void
+odm_bdc_init(
+ void *dm_void
+)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- pBDC_T pDM_BdcTable=&pDM_Odm->DM_BdcTable;
-
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n[ BDC Initialization......] \n"));
- pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE;
- pDM_BdcTable->BDC_Mode=BDC_MODE_NULL;
- pDM_BdcTable->BDC_Try_flag=0;
- pDM_BdcTable->BDCcoexType_wBfer=0;
- pDM_Odm->bdc_holdstate=0xff;
-
- if(pDM_Odm->SupportICType == ODM_RTL8192E)
- {
- ODM_SetBBReg(pDM_Odm, 0xd7c , 0x0FFFFFFF, 0x1081008);
- ODM_SetBBReg(pDM_Odm, 0xd80 , 0x0FFFFFFF, 0);
- }
- else if(pDM_Odm->SupportICType == ODM_RTL8812)
- {
- ODM_SetBBReg(pDM_Odm, 0x9b0 , 0x0FFFFFFF, 0x1081008); //0x9b0[30:0] = 01081008
- ODM_SetBBReg(pDM_Odm, 0x9b4 , 0x0FFFFFFF, 0); //0x9b4[31:0] = 00000000
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
+
+ PHYDM_DBG(dm, DBG_ANT_DIV, "\n[ BDC Initialization......]\n");
+ dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
+ dm_bdc_table->bdc_mode = BDC_MODE_NULL;
+ dm_bdc_table->bdc_try_flag = 0;
+ dm_bdc_table->bd_ccoex_type_wbfer = 0;
+ dm->bdc_holdstate = 0xff;
+
+ if (dm->support_ic_type == ODM_RTL8192E) {
+ odm_set_bb_reg(dm, 0xd7c, 0x0FFFFFFF, 0x1081008);
+ odm_set_bb_reg(dm, 0xd80, 0x0FFFFFFF, 0);
+ } else if (dm->support_ic_type == ODM_RTL8812) {
+ odm_set_bb_reg(dm, 0x9b0, 0x0FFFFFFF, 0x1081008); /* 0x9b0[30:0] = 01081008 */
+ odm_set_bb_reg(dm, 0x9b4, 0x0FFFFFFF, 0); /* 0x9b4[31:0] = 00000000 */
}
-
+
}
-VOID
+void
odm_CSI_on_off(
- IN PVOID pDM_VOID,
- IN u1Byte CSI_en
- )
+ void *dm_void,
+ u8 CSI_en
+)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- if(CSI_en==CSI_ON)
- {
- if(pDM_Odm->SupportICType == ODM_RTL8192E)
- {
- ODM_SetMACReg(pDM_Odm, 0xd84 , BIT11, 1); //0xd84[11]=1
- }
- else if(pDM_Odm->SupportICType == ODM_RTL8812)
- {
- ODM_SetMACReg(pDM_Odm, 0x9b0 , BIT31, 1); //0x9b0[31]=1
- }
-
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ if (CSI_en == CSI_ON) {
+ if (dm->support_ic_type == ODM_RTL8192E)
+ odm_set_mac_reg(dm, 0xd84, BIT(11), 1); /* 0xd84[11]=1 */
+ else if (dm->support_ic_type == ODM_RTL8812)
+ odm_set_mac_reg(dm, 0x9b0, BIT(31), 1); /* 0x9b0[31]=1 */
+
+ } else if (CSI_en == CSI_OFF) {
+ if (dm->support_ic_type == ODM_RTL8192E)
+ odm_set_mac_reg(dm, 0xd84, BIT(11), 0); /* 0xd84[11]=0 */
+ else if (dm->support_ic_type == ODM_RTL8812)
+ odm_set_mac_reg(dm, 0x9b0, BIT(31), 0); /* 0x9b0[31]=0 */
}
- else if(CSI_en==CSI_OFF)
- {
- if(pDM_Odm->SupportICType == ODM_RTL8192E)
- {
- ODM_SetMACReg(pDM_Odm, 0xd84 , BIT11, 0); //0xd84[11]=0
- }
- else if(pDM_Odm->SupportICType == ODM_RTL8812)
- {
- ODM_SetMACReg(pDM_Odm, 0x9b0 , BIT31, 0); //0x9b0[31]=0
- }
- }
}
-VOID
-odm_BDCcoexType_withBferClient(
- IN PVOID pDM_VOID,
- IN u1Byte swch
- )
+void
+odm_bd_ccoex_type_with_bfer_client(
+ void *dm_void,
+ u8 swch
+)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- pBDC_T pDM_BdcTable = &pDM_Odm->DM_BdcTable;
- u1Byte BDCcoexType_wBfer;
-
- if(swch==DIVON_CSIOFF)
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[BDCcoexType: 1] {DIV,CSI} ={1,0} \n"));
- BDCcoexType_wBfer=1;
-
- if(BDCcoexType_wBfer != pDM_BdcTable->BDCcoexType_wBfer)
- {
- odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON);
- odm_CSI_on_off(pDM_Odm,CSI_OFF);
- pDM_BdcTable->BDCcoexType_wBfer=1;
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
+ u8 bd_ccoex_type_wbfer;
+
+ if (swch == DIVON_CSIOFF) {
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[BDCcoexType: 1] {DIV,CSI} ={1,0}\n");
+ bd_ccoex_type_wbfer = 1;
+
+ if (bd_ccoex_type_wbfer != dm_bdc_table->bd_ccoex_type_wbfer) {
+ odm_ant_div_on_off(dm, ANTDIV_ON);
+ odm_CSI_on_off(dm, CSI_OFF);
+ dm_bdc_table->bd_ccoex_type_wbfer = 1;
}
- }
- else if(swch==DIVOFF_CSION)
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[BDCcoexType: 2] {DIV,CSI} ={0,1}\n"));
- BDCcoexType_wBfer=2;
-
- if(BDCcoexType_wBfer != pDM_BdcTable->BDCcoexType_wBfer)
- {
- odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);
- odm_CSI_on_off(pDM_Odm,CSI_ON);
- pDM_BdcTable->BDCcoexType_wBfer=2;
+ } else if (swch == DIVOFF_CSION) {
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[BDCcoexType: 2] {DIV,CSI} ={0,1}\n");
+ bd_ccoex_type_wbfer = 2;
+
+ if (bd_ccoex_type_wbfer != dm_bdc_table->bd_ccoex_type_wbfer) {
+ odm_ant_div_on_off(dm, ANTDIV_OFF);
+ odm_CSI_on_off(dm, CSI_ON);
+ dm_bdc_table->bd_ccoex_type_wbfer = 2;
}
}
}
-VOID
-odm_BF_AntDiv_ModeArbitration(
- IN PVOID pDM_VOID
- )
+void
+odm_bf_ant_div_mode_arbitration(
+ void *dm_void
+)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- pBDC_T pDM_BdcTable = &pDM_Odm->DM_BdcTable;
- u1Byte current_BDC_Mode;
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
+ u8 current_bdc_mode;
- #if(DM_ODM_SUPPORT_TYPE == ODM_AP)
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n"));
-
- //2 Mode 1
- if((pDM_BdcTable->num_Txbfee_Client !=0) && (pDM_BdcTable->num_Txbfer_Client == 0))
- {
- current_BDC_Mode=BDC_MODE_1;
-
- if(current_BDC_Mode != pDM_BdcTable->BDC_Mode)
- {
- pDM_BdcTable->BDC_Mode=BDC_MODE_1;
- odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF);
- pDM_BdcTable->BDC_RxIdleUpdate_counter=1;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to (( Mode1 ))\n"));
- }
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
+ PHYDM_DBG(dm, DBG_ANT_DIV, "\n");
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Antdiv + BF coextance Mode] : (( Mode1 ))\n"));
- }
- //2 Mode 2
- else if((pDM_BdcTable->num_Txbfee_Client ==0) && (pDM_BdcTable->num_Txbfer_Client != 0))
- {
- current_BDC_Mode=BDC_MODE_2;
-
- if(current_BDC_Mode != pDM_BdcTable->BDC_Mode)
- {
- pDM_BdcTable->BDC_Mode=BDC_MODE_2;
- pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE;
- pDM_BdcTable->BDC_Try_flag=0;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to (( Mode2 ))\n"));
-
- }
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Antdiv + BF coextance Mode] : (( Mode2 ))\n"));
+ /* 2 mode 1 */
+ if ((dm_bdc_table->num_txbfee_client != 0) && (dm_bdc_table->num_txbfer_client == 0)) {
+ current_bdc_mode = BDC_MODE_1;
+
+ if (current_bdc_mode != dm_bdc_table->bdc_mode) {
+ dm_bdc_table->bdc_mode = BDC_MODE_1;
+ odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
+ dm_bdc_table->bdc_rx_idle_update_counter = 1;
+ PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode1 ))\n");
}
- //2 Mode 3
- else if((pDM_BdcTable->num_Txbfee_Client !=0) && (pDM_BdcTable->num_Txbfer_Client != 0))
- {
- current_BDC_Mode=BDC_MODE_3;
-
- if(current_BDC_Mode != pDM_BdcTable->BDC_Mode)
- {
- pDM_BdcTable->BDC_Mode=BDC_MODE_3;
- pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE;
- pDM_BdcTable->BDC_Try_flag=0;
- pDM_BdcTable->BDC_RxIdleUpdate_counter=1;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to (( Mode3 ))\n"));
- }
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Antdiv + BF coextance Mode] : (( Mode3 ))\n"));
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[Antdiv + BF coextance mode] : (( Mode1 ))\n");
+ }
+ /* 2 mode 2 */
+ else if ((dm_bdc_table->num_txbfee_client == 0) && (dm_bdc_table->num_txbfer_client != 0)) {
+ current_bdc_mode = BDC_MODE_2;
+
+ if (current_bdc_mode != dm_bdc_table->bdc_mode) {
+ dm_bdc_table->bdc_mode = BDC_MODE_2;
+ dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
+ dm_bdc_table->bdc_try_flag = 0;
+ PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode2 ))\n");
+
+ }
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[Antdiv + BF coextance mode] : (( Mode2 ))\n");
+ }
+ /* 2 mode 3 */
+ else if ((dm_bdc_table->num_txbfee_client != 0) && (dm_bdc_table->num_txbfer_client != 0)) {
+ current_bdc_mode = BDC_MODE_3;
+
+ if (current_bdc_mode != dm_bdc_table->bdc_mode) {
+ dm_bdc_table->bdc_mode = BDC_MODE_3;
+ dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
+ dm_bdc_table->bdc_try_flag = 0;
+ dm_bdc_table->bdc_rx_idle_update_counter = 1;
+ PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode3 ))\n");
}
- //2 Mode 4
- else if((pDM_BdcTable->num_Txbfee_Client ==0) && (pDM_BdcTable->num_Txbfer_Client == 0))
- {
- current_BDC_Mode=BDC_MODE_4;
-
- if(current_BDC_Mode != pDM_BdcTable->BDC_Mode)
- {
- pDM_BdcTable->BDC_Mode=BDC_MODE_4;
- odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF);
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to (( Mode4 ))\n"));
- }
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Antdiv + BF coextance Mode] : (( Mode4 ))\n"));
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[Antdiv + BF coextance mode] : (( Mode3 ))\n");
+ }
+ /* 2 mode 4 */
+ else if ((dm_bdc_table->num_txbfee_client == 0) && (dm_bdc_table->num_txbfer_client == 0)) {
+ current_bdc_mode = BDC_MODE_4;
+
+ if (current_bdc_mode != dm_bdc_table->bdc_mode) {
+ dm_bdc_table->bdc_mode = BDC_MODE_4;
+ odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
+ PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode4 ))\n");
}
- #endif
+
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[Antdiv + BF coextance mode] : (( Mode4 ))\n");
+ }
+#endif
}
-VOID
-odm_DivTrainState_setting(
- IN PVOID pDM_VOID
- )
+void
+odm_div_train_state_setting(
+ void *dm_void
+)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- pBDC_T pDM_BdcTable=&pDM_Odm->DM_BdcTable;
-
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n*****[S T A R T ]***** [2-0. DIV_TRAIN_STATE] \n"));
- pDM_BdcTable->BDC_Try_counter =2;
- pDM_BdcTable->BDC_Try_flag=1;
- pDM_BdcTable->BDC_state=BDC_BFer_TRAIN_STATE;
- odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF);
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
+
+ PHYDM_DBG(dm, DBG_ANT_DIV, "\n*****[S T A R T ]***** [2-0. DIV_TRAIN_STATE]\n");
+ dm_bdc_table->bdc_try_counter = 2;
+ dm_bdc_table->bdc_try_flag = 1;
+ dm_bdc_table->BDC_state = bdc_bfer_train_state;
+ odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
}
-VOID
-odm_BDCcoex_BFeeRxDiv_Arbitration(
- IN PVOID pDM_VOID
+void
+odm_bd_ccoex_bfee_rx_div_arbitration(
+ void *dm_void
)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- pBDC_T pDM_BdcTable = &pDM_Odm->DM_BdcTable;
- BOOLEAN StopBF_flag;
- u1Byte BDC_active_Mode;
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
+ boolean stop_bf_flag;
+ u8 bdc_active_mode;
- #if(DM_ODM_SUPPORT_TYPE == ODM_AP)
+#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***{ num_BFee, num_BFer , num_Client} = (( %d , %d , %d)) \n",pDM_BdcTable->num_Txbfee_Client,pDM_BdcTable->num_Txbfer_Client,pDM_BdcTable->num_Client));
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***{ num_BF_tars, num_DIV_tars } = (( %d , %d )) \n",pDM_BdcTable->num_BfTar , pDM_BdcTable->num_DivTar ));
+ PHYDM_DBG(dm, DBG_ANT_DIV, "***{ num_BFee, num_BFer, num_client} = (( %d , %d , %d))\n", dm_bdc_table->num_txbfee_client, dm_bdc_table->num_txbfer_client, dm_bdc_table->num_client);
+ PHYDM_DBG(dm, DBG_ANT_DIV, "***{ num_BF_tars, num_DIV_tars } = (( %d , %d ))\n", dm_bdc_table->num_bf_tar, dm_bdc_table->num_div_tar);
- //2 [ MIB control ]
- if (pDM_Odm->bdc_holdstate==2)
- {
- odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION);
- pDM_BdcTable->BDC_state=BDC_BF_HOLD_STATE;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Force in [ BF STATE] \n"));
- return;
- }
- else if (pDM_Odm->bdc_holdstate==1)
- {
- pDM_BdcTable->BDC_state=BDC_DIV_HOLD_STATE;
- odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF);
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Force in [ DIV STATE] \n"));
- return;
- }
+ /* 2 [ MIB control ] */
+ if (dm->bdc_holdstate == 2) {
+ odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
+ dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE;
+ PHYDM_DBG(dm, DBG_ANT_DIV, "Force in [ BF STATE]\n");
+ return;
+ } else if (dm->bdc_holdstate == 1) {
+ dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;
+ odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
+ PHYDM_DBG(dm, DBG_ANT_DIV, "Force in [ DIV STATE]\n");
+ return;
+ }
- //------------------------------------------------------------
+ /* ------------------------------------------------------------ */
-
- //2 Mode 2 & 3
- if(pDM_BdcTable->BDC_Mode==BDC_MODE_2 ||pDM_BdcTable->BDC_Mode==BDC_MODE_3)
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n{ Try_flag , Try_counter } = { %d , %d } \n",pDM_BdcTable->BDC_Try_flag,pDM_BdcTable->BDC_Try_counter));
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BDCcoexType = (( %d )) \n\n", pDM_BdcTable->BDCcoexType_wBfer));
-
- // All Client have Bfer-Cap-------------------------------
- if(pDM_BdcTable->num_Txbfer_Client == pDM_BdcTable->num_Client) //BFer STA Only?: yes
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BFer STA only? (( Yes ))\n"));
- pDM_BdcTable->BDC_Try_flag=0;
- pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE;
- odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION);
- return;
- }
- else
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BFer STA only? (( No ))\n"));
- }
- //
- if(pDM_BdcTable->bAll_BFSta_Idle==FALSE && pDM_BdcTable->bAll_DivSta_Idle==TRUE)
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("All DIV-STA are idle, but BF-STA not\n"));
- pDM_BdcTable->BDC_Try_flag=0;
- pDM_BdcTable->BDC_state=BDC_BFer_TRAIN_STATE;
- odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION);
- return;
+ /* 2 mode 2 & 3 */
+ if (dm_bdc_table->bdc_mode == BDC_MODE_2 || dm_bdc_table->bdc_mode == BDC_MODE_3) {
+ PHYDM_DBG(dm, DBG_ANT_DIV, "\n{ Try_flag, Try_counter } = { %d , %d }\n", dm_bdc_table->bdc_try_flag, dm_bdc_table->bdc_try_counter);
+ PHYDM_DBG(dm, DBG_ANT_DIV, "BDCcoexType = (( %d ))\n\n", dm_bdc_table->bd_ccoex_type_wbfer);
+
+ /* All Client have Bfer-Cap------------------------------- */
+ if (dm_bdc_table->num_txbfer_client == dm_bdc_table->num_client) { /* BFer STA Only?: yes */
+ PHYDM_DBG(dm, DBG_ANT_DIV, "BFer STA only? (( Yes ))\n");
+ dm_bdc_table->bdc_try_flag = 0;
+ dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
+ odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
+ return;
+ } else
+ PHYDM_DBG(dm, DBG_ANT_DIV, "BFer STA only? (( No ))\n");
+ /* */
+ if (dm_bdc_table->is_all_bf_sta_idle == false && dm_bdc_table->is_all_div_sta_idle == true) {
+ PHYDM_DBG(dm, DBG_ANT_DIV, "All DIV-STA are idle, but BF-STA not\n");
+ dm_bdc_table->bdc_try_flag = 0;
+ dm_bdc_table->BDC_state = bdc_bfer_train_state;
+ odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
+ return;
+ } else if (dm_bdc_table->is_all_bf_sta_idle == true && dm_bdc_table->is_all_div_sta_idle == false) {
+ PHYDM_DBG(dm, DBG_ANT_DIV, "All BF-STA are idle, but DIV-STA not\n");
+ dm_bdc_table->bdc_try_flag = 0;
+ dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
+ odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
+ return;
+ }
+
+ /* Select active mode-------------------------------------- */
+ if (dm_bdc_table->num_bf_tar == 0) { /* Selsect_1, Selsect_2 */
+ if (dm_bdc_table->num_div_tar == 0) { /* Selsect_3 */
+ PHYDM_DBG(dm, DBG_ANT_DIV, "Select active mode (( 1 ))\n");
+ dm_bdc_table->bdc_active_mode = 1;
+ } else {
+ PHYDM_DBG(dm, DBG_ANT_DIV, "Select active mode (( 2 ))\n");
+ dm_bdc_table->bdc_active_mode = 2;
}
- else if(pDM_BdcTable->bAll_BFSta_Idle==TRUE && pDM_BdcTable->bAll_DivSta_Idle==FALSE)
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("All BF-STA are idle, but DIV-STA not\n"));
- pDM_BdcTable->BDC_Try_flag=0;
- pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE;
- odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF);
+ dm_bdc_table->bdc_try_flag = 0;
+ dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
+ odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
+ return;
+ } else { /* num_bf_tar > 0 */
+ if (dm_bdc_table->num_div_tar == 0) { /* Selsect_3 */
+ PHYDM_DBG(dm, DBG_ANT_DIV, "Select active mode (( 3 ))\n");
+ dm_bdc_table->bdc_active_mode = 3;
+ dm_bdc_table->bdc_try_flag = 0;
+ dm_bdc_table->BDC_state = bdc_bfer_train_state;
+ odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
return;
- }
+ } else { /* Selsect_4 */
+ bdc_active_mode = 4;
+ PHYDM_DBG(dm, DBG_ANT_DIV, "Select active mode (( 4 ))\n");
- //Select active mode--------------------------------------
- if(pDM_BdcTable->num_BfTar ==0) // Selsect_1, Selsect_2
- {
- if(pDM_BdcTable->num_DivTar ==0) // Selsect_3
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Select active mode (( 1 )) \n"));
- pDM_BdcTable->BDC_active_Mode=1;
- }
- else
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Select active mode (( 2 ))\n"));
- pDM_BdcTable->BDC_active_Mode=2;
- }
- pDM_BdcTable->BDC_Try_flag=0;
- pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE;
- odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF);
- return;
- }
- else // num_BfTar > 0
- {
- if(pDM_BdcTable->num_DivTar ==0) // Selsect_3
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Select active mode (( 3 ))\n"));
- pDM_BdcTable->BDC_active_Mode=3;
- pDM_BdcTable->BDC_Try_flag=0;
- pDM_BdcTable->BDC_state=BDC_BFer_TRAIN_STATE;
- odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION);
+ if (bdc_active_mode != dm_bdc_table->bdc_active_mode) {
+ dm_bdc_table->bdc_active_mode = 4;
+ PHYDM_DBG(dm, DBG_ANT_DIV, "Change to active mode (( 4 )) & return!!!\n");
return;
}
- else // Selsect_4
- {
- BDC_active_Mode=4;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Select active mode (( 4 ))\n"));
-
- if(BDC_active_Mode!=pDM_BdcTable->BDC_active_Mode)
- {
- pDM_BdcTable->BDC_active_Mode=4;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to active mode (( 4 )) & return!!! \n"));
- return;
- }
- }
}
+ }
#if 1
- if (pDM_Odm->bdc_holdstate==0xff)
- {
- pDM_BdcTable->BDC_state=BDC_DIV_HOLD_STATE;
- odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF);
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Force in [ DIV STATE] \n"));
+ if (dm->bdc_holdstate == 0xff) {
+ dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;
+ odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
+ PHYDM_DBG(dm, DBG_ANT_DIV, "Force in [ DIV STATE]\n");
return;
}
#endif
- // Does Client number changed ? -------------------------------
- if(pDM_BdcTable->num_Client !=pDM_BdcTable->pre_num_Client)
- {
- pDM_BdcTable->BDC_Try_flag=0;
- pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ The number of client has been changed !!!] return to (( BDC_DIV_TRAIN_STATE )) \n"));
+ /* Does Client number changed ? ------------------------------- */
+ if (dm_bdc_table->num_client != dm_bdc_table->pre_num_client) {
+ dm_bdc_table->bdc_try_flag = 0;
+ dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[ The number of client has been changed !!!] return to (( BDC_DIV_TRAIN_STATE ))\n");
+ }
+ dm_bdc_table->pre_num_client = dm_bdc_table->num_client;
+
+ if (dm_bdc_table->bdc_try_flag == 0) {
+ /* 2 DIV_TRAIN_STATE (mode 2-0) */
+ if (dm_bdc_table->BDC_state == BDC_DIV_TRAIN_STATE)
+ odm_div_train_state_setting(dm);
+ /* 2 BFer_TRAIN_STATE (mode 2-1) */
+ else if (dm_bdc_table->BDC_state == bdc_bfer_train_state) {
+ PHYDM_DBG(dm, DBG_ANT_DIV, "*****[2-1. BFer_TRAIN_STATE ]*****\n");
+
+ /* if(dm_bdc_table->num_bf_tar==0) */
+ /* { */
+ /* PHYDM_DBG(dm,DBG_ANT_DIV, "BF_tars exist? : (( No )), [ bdc_bfer_train_state ] >> [BDC_DIV_TRAIN_STATE]\n"); */
+ /* odm_div_train_state_setting( dm); */
+ /* } */
+ /* else */ /* num_bf_tar != 0 */
+ /* { */
+ dm_bdc_table->bdc_try_counter = 2;
+ dm_bdc_table->bdc_try_flag = 1;
+ dm_bdc_table->BDC_state = BDC_DECISION_STATE;
+ odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
+ PHYDM_DBG(dm, DBG_ANT_DIV, "BF_tars exist? : (( Yes )), [ bdc_bfer_train_state ] >> [BDC_DECISION_STATE]\n");
+ /* } */
+ }
+ /* 2 DECISION_STATE (mode 2-2) */
+ else if (dm_bdc_table->BDC_state == BDC_DECISION_STATE) {
+ PHYDM_DBG(dm, DBG_ANT_DIV, "*****[2-2. DECISION_STATE]*****\n");
+ /* if(dm_bdc_table->num_bf_tar==0) */
+ /* { */
+ /* ODM_AntDiv_Printk(("BF_tars exist? : (( No )), [ DECISION_STATE ] >> [BDC_DIV_TRAIN_STATE]\n")); */
+ /* odm_div_train_state_setting( dm); */
+ /* } */
+ /* else */ /* num_bf_tar != 0 */
+ /* { */
+ if (dm_bdc_table->BF_pass == false || dm_bdc_table->DIV_pass == false)
+ stop_bf_flag = true;
+ else
+ stop_bf_flag = false;
+
+ PHYDM_DBG(dm, DBG_ANT_DIV, "BF_tars exist? : (( Yes )), {BF_pass, DIV_pass, stop_bf_flag } = { %d, %d, %d }\n", dm_bdc_table->BF_pass, dm_bdc_table->DIV_pass, stop_bf_flag);
+
+ if (stop_bf_flag == true) { /* DIV_en */
+ dm_bdc_table->bdc_hold_counter = 10; /* 20 */
+ odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
+ dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[ stop_bf_flag= ((true)), BDC_DECISION_STATE ] >> [BDC_DIV_HOLD_STATE]\n");
+ } else { /* BF_en */
+ dm_bdc_table->bdc_hold_counter = 10; /* 20 */
+ odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
+ dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE;
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[stop_bf_flag= ((false)), BDC_DECISION_STATE ] >> [BDC_BF_HOLD_STATE]\n");
+ }
+ /* } */
}
- pDM_BdcTable->pre_num_Client=pDM_BdcTable->num_Client;
+ /* 2 BF-HOLD_STATE (mode 2-3) */
+ else if (dm_bdc_table->BDC_state == BDC_BF_HOLD_STATE) {
+ PHYDM_DBG(dm, DBG_ANT_DIV, "*****[2-3. BF_HOLD_STATE ]*****\n");
- if( pDM_BdcTable->BDC_Try_flag==0)
- {
- //2 DIV_TRAIN_STATE (Mode 2-0)
- if(pDM_BdcTable->BDC_state==BDC_DIV_TRAIN_STATE)
- {
- odm_DivTrainState_setting( pDM_Odm);
+ PHYDM_DBG(dm, DBG_ANT_DIV, "bdc_hold_counter = (( %d ))\n", dm_bdc_table->bdc_hold_counter);
+
+ if (dm_bdc_table->bdc_hold_counter == 1) {
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n");
+ odm_div_train_state_setting(dm);
+ } else {
+ dm_bdc_table->bdc_hold_counter--;
+
+ /* if(dm_bdc_table->num_bf_tar==0) */
+ /* { */
+ /* PHYDM_DBG(dm,DBG_ANT_DIV, "BF_tars exist? : (( No )), [ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n"); */
+ /* odm_div_train_state_setting( dm); */
+ /* } */
+ /* else */ /* num_bf_tar != 0 */
+ /* { */
+ /* PHYDM_DBG(dm,DBG_ANT_DIV, "BF_tars exist? : (( Yes ))\n"); */
+ dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE;
+ odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_BF_HOLD_STATE ] >> [BDC_BF_HOLD_STATE]\n");
+ /* } */
}
- //2 BFer_TRAIN_STATE (Mode 2-1)
- else if(pDM_BdcTable->BDC_state==BDC_BFer_TRAIN_STATE)
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*****[2-1. BFer_TRAIN_STATE ]***** \n"));
-
- //if(pDM_BdcTable->num_BfTar==0)
- //{
- // ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( No )), [ BDC_BFer_TRAIN_STATE ] >> [BDC_DIV_TRAIN_STATE] \n"));
- // odm_DivTrainState_setting( pDM_Odm);
- //}
- //else //num_BfTar != 0
- //{
- pDM_BdcTable->BDC_Try_counter=2;
- pDM_BdcTable->BDC_Try_flag=1;
- pDM_BdcTable->BDC_state=BDC_DECISION_STATE;
- odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION);
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( Yes )), [ BDC_BFer_TRAIN_STATE ] >> [BDC_DECISION_STATE] \n"));
- //}
- }
- //2 DECISION_STATE (Mode 2-2)
- else if(pDM_BdcTable->BDC_state==BDC_DECISION_STATE)
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*****[2-2. DECISION_STATE]***** \n"));
- //if(pDM_BdcTable->num_BfTar==0)
- //{
- // ODM_AntDiv_Printk(("BF_tars exist? : (( No )), [ DECISION_STATE ] >> [BDC_DIV_TRAIN_STATE] \n"));
- // odm_DivTrainState_setting( pDM_Odm);
- //}
- //else //num_BfTar != 0
- //{
- if(pDM_BdcTable->BF_pass==FALSE || pDM_BdcTable->DIV_pass == FALSE)
- StopBF_flag=TRUE;
- else
- StopBF_flag=FALSE;
-
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( Yes )), {BF_pass, DIV_pass, StopBF_flag } = { %d, %d, %d } \n" ,pDM_BdcTable->BF_pass,pDM_BdcTable->DIV_pass,StopBF_flag));
-
- if(StopBF_flag==TRUE) //DIV_en
- {
- pDM_BdcTable->BDC_Hold_counter=10; //20
- odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF);
- pDM_BdcTable->BDC_state=BDC_DIV_HOLD_STATE;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ StopBF_flag= ((TRUE)), BDC_DECISION_STATE ] >> [BDC_DIV_HOLD_STATE] \n"));
- }
- else //BF_en
- {
- pDM_BdcTable->BDC_Hold_counter=10; //20
- odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION);
- pDM_BdcTable->BDC_state=BDC_BF_HOLD_STATE;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[StopBF_flag= ((FALSE)), BDC_DECISION_STATE ] >> [BDC_BF_HOLD_STATE] \n"));
- }
- //}
- }
- //2 BF-HOLD_STATE (Mode 2-3)
- else if(pDM_BdcTable->BDC_state==BDC_BF_HOLD_STATE)
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*****[2-3. BF_HOLD_STATE ]*****\n"));
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BDC_Hold_counter = (( %d )) \n",pDM_BdcTable->BDC_Hold_counter ));
+ }
+ /* 2 DIV-HOLD_STATE (mode 2-4) */
+ else if (dm_bdc_table->BDC_state == BDC_DIV_HOLD_STATE) {
+ PHYDM_DBG(dm, DBG_ANT_DIV, "*****[2-4. DIV_HOLD_STATE ]*****\n");
- if(pDM_BdcTable->BDC_Hold_counter==1)
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE] \n"));
- odm_DivTrainState_setting( pDM_Odm);
- }
- else
- {
- pDM_BdcTable->BDC_Hold_counter--;
-
- //if(pDM_BdcTable->num_BfTar==0)
- //{
- // ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( No )), [ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE] \n"));
- // odm_DivTrainState_setting( pDM_Odm);
- //}
- //else //num_BfTar != 0
- //{
- //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( Yes ))\n"));
- pDM_BdcTable->BDC_state=BDC_BF_HOLD_STATE;
- odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION);
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ BDC_BF_HOLD_STATE ] >> [BDC_BF_HOLD_STATE] \n"));
- //}
- }
-
- }
- //2 DIV-HOLD_STATE (Mode 2-4)
- else if(pDM_BdcTable->BDC_state==BDC_DIV_HOLD_STATE)
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*****[2-4. DIV_HOLD_STATE ]*****\n"));
-
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BDC_Hold_counter = (( %d )) \n",pDM_BdcTable->BDC_Hold_counter ));
-
- if(pDM_BdcTable->BDC_Hold_counter==1)
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE] \n"));
- odm_DivTrainState_setting( pDM_Odm);
- }
- else
- {
- pDM_BdcTable->BDC_Hold_counter--;
- pDM_BdcTable->BDC_state=BDC_DIV_HOLD_STATE;
- odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF);
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_HOLD_STATE] \n"));
- }
-
+ PHYDM_DBG(dm, DBG_ANT_DIV, "bdc_hold_counter = (( %d ))\n", dm_bdc_table->bdc_hold_counter);
+
+ if (dm_bdc_table->bdc_hold_counter == 1) {
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n");
+ odm_div_train_state_setting(dm);
+ } else {
+ dm_bdc_table->bdc_hold_counter--;
+ dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;
+ odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_HOLD_STATE]\n");
}
-
+
}
- else if( pDM_BdcTable->BDC_Try_flag==1)
- {
- //2 Set Training Counter
- if(pDM_BdcTable->BDC_Try_counter >1)
- {
- pDM_BdcTable->BDC_Try_counter--;
- if(pDM_BdcTable->BDC_Try_counter ==1)
- pDM_BdcTable->BDC_Try_flag=0;
-
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training !!\n"));
- //return ;
- }
-
+
+ } else if (dm_bdc_table->bdc_try_flag == 1) {
+ /* 2 Set Training counter */
+ if (dm_bdc_table->bdc_try_counter > 1) {
+ dm_bdc_table->bdc_try_counter--;
+ if (dm_bdc_table->bdc_try_counter == 1)
+ dm_bdc_table->bdc_try_flag = 0;
+
+ PHYDM_DBG(dm, DBG_ANT_DIV, "Training !!\n");
+ /* return ; */
}
-
+
}
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n[end]\n"));
+ }
+
+ PHYDM_DBG(dm, DBG_ANT_DIV, "\n[end]\n");
+
+#endif /* #if(DM_ODM_SUPPORT_TYPE == ODM_AP) */
- #endif //#if(DM_ODM_SUPPORT_TYPE == ODM_AP)
-
}
#endif
-#endif //#ifdef BEAMFORMING_SUPPORT
+#endif /* #ifdef BEAMFORMING_SUPPORT */
#if (RTL8188E_SUPPORT == 1)
-VOID
-odm_RX_HWAntDiv_Init_88E(
- IN PVOID pDM_VOID
+void
+odm_rx_hw_ant_div_init_88e(
+ void *dm_void
)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- u4Byte value32;
- pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
-
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ u32 value32;
+ struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
- if(pDM_Odm->mp_mode == TRUE)
- {
- ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv
- ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); // 1:CG, 0:CS
- return;
+#if 0
+ if (*(dm->mp_mode) == true) {
+ odm_set_bb_reg(dm, ODM_REG_IGI_A_11N, BIT(7), 0); /* disable HW AntDiv */
+ odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* 1:CG, 0:CS */
+ return;
}
-
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init => AntDivType=[CGCS_RX_HW_ANTDIV]\n"));
-
- //MAC Setting
- value32 = ODM_GetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
- ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output
- //Pin Settings
- ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW
- ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW
- ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 1); //Regb2c[22]=1'b0 //disable CS/CG switch
- ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only
- //OFDM Settings
- ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N , bMaskDWord, 0x000000a0);
- //CCK Settings
- ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); //Fix CCK PHY status report issue
- ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); //CCK complete HW AntDiv within 64 samples
-
- ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , 0xFFFF, 0x0001); //antenna mapping table
+#endif
- pDM_FatTable->enable_ctrl_frame_antdiv = 1;
+ PHYDM_DBG(dm, DBG_ANT_DIV, "***8188E AntDiv_Init => ant_div_type=[CGCS_RX_HW_ANTDIV]\n");
+
+ /* MAC setting */
+ value32 = odm_get_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD);
+ odm_set_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
+ /* Pin Settings */
+ odm_set_bb_reg(dm, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);/* reg870[8]=1'b0, reg870[9]=1'b0 */ /* antsel antselb by HW */
+ odm_set_bb_reg(dm, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); /* reg864[10]=1'b0 */ /* antsel2 by HW */
+ odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(22), 1); /* regb2c[22]=1'b0 */ /* disable CS/CG switch */
+ odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* regb2c[31]=1'b1 */ /* output at CG only */
+ /* OFDM Settings */
+ odm_set_bb_reg(dm, ODM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0);
+ /* CCK Settings */
+ odm_set_bb_reg(dm, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); /* Fix CCK PHY status report issue */
+ odm_set_bb_reg(dm, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */
+
+ odm_set_bb_reg(dm, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0001); /* antenna mapping table */
+
+ fat_tab->enable_ctrl_frame_antdiv = 1;
}
-VOID
-odm_TRX_HWAntDiv_Init_88E(
- IN PVOID pDM_VOID
+void
+odm_trx_hw_ant_div_init_88e(
+ void *dm_void
)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- u4Byte value32;
- pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
-
- if(pDM_Odm->mp_mode == TRUE)
- {
- ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv
- ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, 0); //Default RX (0/1)
- return;
- }
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ u32 value32;
+ struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init => AntDivType=[CG_TRX_HW_ANTDIV (SPDT)]\n"));
-
- //MAC Setting
- value32 = ODM_GetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
- ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output
- //Pin Settings
- ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW
- ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW
- ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 0); //Regb2c[22]=1'b0 //disable CS/CG switch
- ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only
- //OFDM Settings
- ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N , bMaskDWord, 0x000000a0);
- //CCK Settings
- ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); //Fix CCK PHY status report issue
- ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); //CCK complete HW AntDiv within 64 samples
-
- //antenna mapping table
- if(!pDM_Odm->bIsMPChip) //testchip
- {
- ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT10|BIT9|BIT8, 1); //Reg858[10:8]=3'b001
- ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT13|BIT12|BIT11, 2); //Reg858[13:11]=3'b010
+#if 0
+ if (*(dm->mp_mode) == true) {
+ odm_set_bb_reg(dm, ODM_REG_IGI_A_11N, BIT(7), 0); /* disable HW AntDiv */
+ odm_set_bb_reg(dm, ODM_REG_RX_ANT_CTRL_11N, BIT(5) | BIT4 | BIT3, 0); /* Default RX (0/1) */
+ return;
}
- else //MPchip
- ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , bMaskDWord, 0x0201); /*Reg914=3'b010, Reg915=3'b001*/
+#endif
- pDM_FatTable->enable_ctrl_frame_antdiv = 1;
+ PHYDM_DBG(dm, DBG_ANT_DIV, "***8188E AntDiv_Init => ant_div_type=[CG_TRX_HW_ANTDIV (SPDT)]\n");
+
+ /* MAC setting */
+ value32 = odm_get_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD);
+ odm_set_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
+ /* Pin Settings */
+ odm_set_bb_reg(dm, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);/* reg870[8]=1'b0, reg870[9]=1'b0 */ /* antsel antselb by HW */
+ odm_set_bb_reg(dm, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); /* reg864[10]=1'b0 */ /* antsel2 by HW */
+ odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(22), 0); /* regb2c[22]=1'b0 */ /* disable CS/CG switch */
+ odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* regb2c[31]=1'b1 */ /* output at CG only */
+ /* OFDM Settings */
+ odm_set_bb_reg(dm, ODM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0);
+ /* CCK Settings */
+ odm_set_bb_reg(dm, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); /* Fix CCK PHY status report issue */
+ odm_set_bb_reg(dm, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */
+
+ /* antenna mapping table */
+ if (!dm->is_mp_chip) { /* testchip */
+ odm_set_bb_reg(dm, ODM_REG_RX_DEFAULT_A_11N, BIT(10) | BIT(9) | BIT(8), 1); /* Reg858[10:8]=3'b001 */
+ odm_set_bb_reg(dm, ODM_REG_RX_DEFAULT_A_11N, BIT(13) | BIT(12) | BIT(11), 2); /* Reg858[13:11]=3'b010 */
+ } else /* MPchip */
+ odm_set_bb_reg(dm, ODM_REG_ANT_MAPPING1_11N, MASKDWORD, 0x0201); /*Reg914=3'b010, Reg915=3'b001*/
+
+ fat_tab->enable_ctrl_frame_antdiv = 1;
}
-#if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) )
-VOID
-odm_Smart_HWAntDiv_Init_88E(
- IN PVOID pDM_VOID
+#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
+void
+odm_smart_hw_ant_div_init_88e(
+ void *dm_void
)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- u4Byte value32, i;
- pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ u32 value32, i;
+ struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init => AntDivType=[CG_TRX_SMART_ANTDIV]\n"));
-
- if(pDM_Odm->mp_mode == TRUE)
- {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("pDM_Odm->AntDivType: %d\n", pDM_Odm->AntDivType));
+ PHYDM_DBG(dm, DBG_ANT_DIV, "***8188E AntDiv_Init => ant_div_type=[CG_TRX_SMART_ANTDIV]\n");
+
+#if 0
+ if (*(dm->mp_mode) == true) {
+ PHYDM_DBG(dm, ODM_COMP_INIT, "dm->ant_div_type: %d\n", dm->ant_div_type);
return;
}
+#endif
- pDM_FatTable->TrainIdx = 0;
- pDM_FatTable->FAT_State = FAT_PREPARE_STATE;
-
- pDM_Odm->fat_comb_a=5;
- pDM_Odm->antdiv_intvl = 0x64; // 100ms
+ fat_tab->train_idx = 0;
+ fat_tab->fat_state = FAT_PREPARE_STATE;
- for(i=0; i<6; i++)
- {
- pDM_FatTable->Bssid[i] = 0;
- }
- for(i=0; i< (pDM_Odm->fat_comb_a) ; i++)
- {
- pDM_FatTable->antSumRSSI[i] = 0;
- pDM_FatTable->antRSSIcnt[i] = 0;
- pDM_FatTable->antAveRSSI[i] = 0;
- }
+ dm->fat_comb_a = 5;
+ dm->antdiv_intvl = 0x64; /* 100ms */
- //MAC Setting
- value32 = ODM_GetMACReg(pDM_Odm, 0x4c, bMaskDWord);
- ODM_SetMACReg(pDM_Odm, 0x4c, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output
- value32 = ODM_GetMACReg(pDM_Odm, 0x7B4, bMaskDWord);
- ODM_SetMACReg(pDM_Odm, 0x7b4, bMaskDWord, value32|(BIT16|BIT17)); //Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match
- //value32 = PlatformEFIORead4Byte(Adapter, 0x7B4);
- //PlatformEFIOWrite4Byte(Adapter, 0x7b4, value32|BIT18); //append MACID in reponse packet
-
- //Match MAC ADDR
- ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, 0);
- ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, 0);
-
- ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW
- ODM_SetBBReg(pDM_Odm, 0x864 , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW
- ODM_SetBBReg(pDM_Odm, 0xb2c , BIT22, 0); //Regb2c[22]=1'b0 //disable CS/CG switch
- ODM_SetBBReg(pDM_Odm, 0xb2c , BIT31, 0); //Regb2c[31]=1'b1 //output at CS only
- ODM_SetBBReg(pDM_Odm, 0xca4 , bMaskDWord, 0x000000a0);
-
- //antenna mapping table
- if(pDM_Odm->fat_comb_a == 2)
- {
- if(!pDM_Odm->bIsMPChip) //testchip
- {
- ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 1); //Reg858[10:8]=3'b001
- ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 2); //Reg858[13:11]=3'b010
- }
- else //MPchip
- {
- ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 1);
- ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 2);
- }
+ for (i = 0; i < 6; i++)
+ fat_tab->bssid[i] = 0;
+ for (i = 0; i < (dm->fat_comb_a) ; i++) {
+ fat_tab->ant_sum_rssi[i] = 0;
+ fat_tab->ant_rssi_cnt[i] = 0;
+ fat_tab->ant_ave_rssi[i] = 0;
}
- else
- {
- if(!pDM_Odm->bIsMPChip) //testchip
- {
- ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 0); //Reg858[10:8]=3'b000
- ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 1); //Reg858[13:11]=3'b001
- ODM_SetBBReg(pDM_Odm, 0x878 , BIT16, 0);
- ODM_SetBBReg(pDM_Odm, 0x858 , BIT15|BIT14, 2); //(Reg878[0],Reg858[14:15])=3'b010
- ODM_SetBBReg(pDM_Odm, 0x878 , BIT19|BIT18|BIT17, 3);//Reg878[3:1]=3b'011
- ODM_SetBBReg(pDM_Odm, 0x878 , BIT22|BIT21|BIT20, 4);//Reg878[6:4]=3b'100
- ODM_SetBBReg(pDM_Odm, 0x878 , BIT25|BIT24|BIT23, 5);//Reg878[9:7]=3b'101
- ODM_SetBBReg(pDM_Odm, 0x878 , BIT28|BIT27|BIT26, 6);//Reg878[12:10]=3b'110
- ODM_SetBBReg(pDM_Odm, 0x878 , BIT31|BIT30|BIT29, 7);//Reg878[15:13]=3b'111
+
+ /* MAC setting */
+ value32 = odm_get_mac_reg(dm, 0x4c, MASKDWORD);
+ odm_set_mac_reg(dm, 0x4c, MASKDWORD, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
+ value32 = odm_get_mac_reg(dm, 0x7B4, MASKDWORD);
+ odm_set_mac_reg(dm, 0x7b4, MASKDWORD, value32 | (BIT(16) | BIT(17))); /* Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match */
+ /* value32 = platform_efio_read_4byte(adapter, 0x7B4); */
+ /* platform_efio_write_4byte(adapter, 0x7b4, value32|BIT(18)); */ /* append MACID in reponse packet */
+
+ /* Match MAC ADDR */
+ odm_set_mac_reg(dm, 0x7b4, 0xFFFF, 0);
+ odm_set_mac_reg(dm, 0x7b0, MASKDWORD, 0);
+
+ odm_set_bb_reg(dm, 0x870, BIT(9) | BIT(8), 0);/* reg870[8]=1'b0, reg870[9]=1'b0 */ /* antsel antselb by HW */
+ odm_set_bb_reg(dm, 0x864, BIT(10), 0); /* reg864[10]=1'b0 */ /* antsel2 by HW */
+ odm_set_bb_reg(dm, 0xb2c, BIT(22), 0); /* regb2c[22]=1'b0 */ /* disable CS/CG switch */
+ odm_set_bb_reg(dm, 0xb2c, BIT(31), 0); /* regb2c[31]=1'b1 */ /* output at CS only */
+ odm_set_bb_reg(dm, 0xca4, MASKDWORD, 0x000000a0);
+
+ /* antenna mapping table */
+ if (dm->fat_comb_a == 2) {
+ if (!dm->is_mp_chip) { /* testchip */
+ odm_set_bb_reg(dm, 0x858, BIT(10) | BIT(9) | BIT(8), 1); /* Reg858[10:8]=3'b001 */
+ odm_set_bb_reg(dm, 0x858, BIT(13) | BIT(12) | BIT(11), 2); /* Reg858[13:11]=3'b010 */
+ } else { /* MPchip */
+ odm_set_bb_reg(dm, 0x914, MASKBYTE0, 1);
+ odm_set_bb_reg(dm, 0x914, MASKBYTE1, 2);
}
- else //MPchip
- {
- ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 4); // 0: 3b'000
- ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 2); // 1: 3b'001
- ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte2, 0); // 2: 3b'010
- ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte3, 1); // 3: 3b'011
- ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte0, 3); // 4: 3b'100
- ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte1, 5); // 5: 3b'101
- ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte2, 6); // 6: 3b'110
- ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte3, 255); // 7: 3b'111
+ } else {
+ if (!dm->is_mp_chip) { /* testchip */
+ odm_set_bb_reg(dm, 0x858, BIT(10) | BIT(9) | BIT(8), 0); /* Reg858[10:8]=3'b000 */
+ odm_set_bb_reg(dm, 0x858, BIT(13) | BIT(12) | BIT(11), 1); /* Reg858[13:11]=3'b001 */
+ odm_set_bb_reg(dm, 0x878, BIT(16), 0);
+ odm_set_bb_reg(dm, 0x858, BIT(15) | BIT(14), 2); /* (Reg878[0],Reg858[14:15])=3'b010 */
+ odm_set_bb_reg(dm, 0x878, BIT(19) | BIT(18) | BIT(17), 3); /* Reg878[3:1]=3b'011 */
+ odm_set_bb_reg(dm, 0x878, BIT(22) | BIT(21) | BIT(20), 4); /* Reg878[6:4]=3b'100 */
+ odm_set_bb_reg(dm, 0x878, BIT(25) | BIT(24) | BIT(23), 5); /* Reg878[9:7]=3b'101 */
+ odm_set_bb_reg(dm, 0x878, BIT(28) | BIT(27) | BIT(26), 6); /* Reg878[12:10]=3b'110 */
+ odm_set_bb_reg(dm, 0x878, BIT(31) | BIT(30) | BIT(29), 7); /* Reg878[15:13]=3b'111 */
+ } else { /* MPchip */
+ odm_set_bb_reg(dm, 0x914, MASKBYTE0, 4); /* 0: 3b'000 */
+ odm_set_bb_reg(dm, 0x914, MASKBYTE1, 2); /* 1: 3b'001 */
+ odm_set_bb_reg(dm, 0x914, MASKBYTE2, 0); /* 2: 3b'010 */
+ odm_set_bb_reg(dm, 0x914, MASKBYTE3, 1); /* 3: 3b'011 */
+ odm_set_bb_reg(dm, 0x918, MASKBYTE0, 3); /* 4: 3b'100 */
+ odm_set_bb_reg(dm, 0x918, MASKBYTE1, 5); /* 5: 3b'101 */
+ odm_set_bb_reg(dm, 0x918, MASKBYTE2, 6); /* 6: 3b'110 */
+ odm_set_bb_reg(dm, 0x918, MASKBYTE3, 255); /* 7: 3b'111 */
}
}
- //Default Ant Setting when no fast training
- ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, 0); //Default RX
- ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, 1); //Optional RX
- ODM_SetBBReg(pDM_Odm, 0x860 , BIT14|BIT13|BIT12, 0);//Default TX
-
- //Enter Traing state
- ODM_SetBBReg(pDM_Odm, 0x864 , BIT2|BIT1|BIT0, (pDM_Odm->fat_comb_a-1)); //Reg864[2:0]=3'd6 //ant combination=reg864[2:0]+1
-
- //SW Control
- //PHY_SetBBReg(Adapter, 0x864 , BIT10, 1);
- //PHY_SetBBReg(Adapter, 0x870 , BIT9, 1);
- //PHY_SetBBReg(Adapter, 0x870 , BIT8, 1);
- //PHY_SetBBReg(Adapter, 0x864 , BIT11, 1);
- //PHY_SetBBReg(Adapter, 0x860 , BIT9, 0);
- //PHY_SetBBReg(Adapter, 0x860 , BIT8, 0);
+ /* Default ant setting when no fast training */
+ odm_set_bb_reg(dm, 0x864, BIT(5) | BIT(4) | BIT(3), 0); /* Default RX */
+ odm_set_bb_reg(dm, 0x864, BIT(8) | BIT(7) | BIT(6), 1); /* Optional RX */
+ odm_set_bb_reg(dm, 0x860, BIT(14) | BIT(13) | BIT(12), 0); /* Default TX */
+
+ /* Enter Traing state */
+ odm_set_bb_reg(dm, 0x864, BIT(2) | BIT(1) | BIT(0), (dm->fat_comb_a - 1)); /* reg864[2:0]=3'd6 */ /* ant combination=reg864[2:0]+1 */
+
+ /* SW Control */
+ /* phy_set_bb_reg(adapter, 0x864, BIT10, 1); */
+ /* phy_set_bb_reg(adapter, 0x870, BIT9, 1); */
+ /* phy_set_bb_reg(adapter, 0x870, BIT8, 1); */
+ /* phy_set_bb_reg(adapter, 0x864, BIT11, 1); */
+ /* phy_set_bb_reg(adapter, 0x860, BIT9, 0); */
+ /* phy_set_bb_reg(adapter, 0x860, BIT8, 0); */
}
#endif
-#endif //#if (RTL8188E_SUPPORT == 1)
+#endif /* #if (RTL8188E_SUPPORT == 1) */
#if (RTL8192E_SUPPORT == 1)
-VOID
-odm_RX_HWAntDiv_Init_92E(
- IN PVOID pDM_VOID
+void
+odm_rx_hw_ant_div_init_92e(
+ void *dm_void
)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
-
- if(pDM_Odm->mp_mode == TRUE)
- {
- odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);
- ODM_SetBBReg(pDM_Odm, 0xc50 , BIT8, 0); //r_rxdiv_enable_anta Regc50[8]=1'b0 0: control by c50[9]
- ODM_SetBBReg(pDM_Odm, 0xc50 , BIT9, 1); // 1:CG, 0:CS
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+
+#if 0
+ if (*(dm->mp_mode) == true) {
+ odm_ant_div_on_off(dm, ANTDIV_OFF);
+ odm_set_bb_reg(dm, 0xc50, BIT(8), 0); /* r_rxdiv_enable_anta regc50[8]=1'b0 0: control by c50[9] */
+ odm_set_bb_reg(dm, 0xc50, BIT(9), 1); /* 1:CG, 0:CS */
return;
}
-
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8192E AntDiv_Init => AntDivType=[CGCS_RX_HW_ANTDIV]\n"));
-
- //Pin Settings
- ODM_SetBBReg(pDM_Odm, 0x870 , BIT8, 0);//Reg870[8]=1'b0, // "antsel" is controled by HWs
- ODM_SetBBReg(pDM_Odm, 0xc50 , BIT8, 1); //Regc50[8]=1'b1 //" CS/CG switching" is controled by HWs
-
- //Mapping table
- ODM_SetBBReg(pDM_Odm, 0x914 , 0xFFFF, 0x0100); //antenna mapping table
-
- //OFDM Settings
- ODM_SetBBReg(pDM_Odm, 0xca4 , 0x7FF, 0xA0); //thershold
- ODM_SetBBReg(pDM_Odm, 0xca4 , 0x7FF000, 0x0); //bias
-
- //CCK Settings
- ODM_SetBBReg(pDM_Odm, 0xa04 , 0xF000000, 0); //Select which path to receive for CCK_1 & CCK_2
- ODM_SetBBReg(pDM_Odm, 0xb34 , BIT30, 0); //(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0
- ODM_SetBBReg(pDM_Odm, 0xa74 , BIT7, 1); //Fix CCK PHY status report issue
- ODM_SetBBReg(pDM_Odm, 0xa0c , BIT4, 1); //CCK complete HW AntDiv within 64 samples
-
- #ifdef ODM_EVM_ENHANCE_ANTDIV
- //EVM enhance AntDiv method init----------------------------------------------------------------------
- pDM_FatTable->EVM_method_enable=0;
- pDM_FatTable->FAT_State = NORMAL_STATE_MIAN;
- pDM_Odm->antdiv_intvl = 0x64;
- ODM_SetBBReg(pDM_Odm, 0x910 , 0x3f, 0xf );
- pDM_Odm->antdiv_evm_en=1;
- //pDM_Odm->antdiv_period=1;
- pDM_Odm->evm_antdiv_period = 3;
-
- #endif
-
+#endif
+
+ PHYDM_DBG(dm, DBG_ANT_DIV, "***8192E AntDiv_Init => ant_div_type=[CGCS_RX_HW_ANTDIV]\n");
+
+ /* Pin Settings */
+ odm_set_bb_reg(dm, 0x870, BIT(8), 0);/* reg870[8]=1'b0, */ /* "antsel" is controled by HWs */
+ odm_set_bb_reg(dm, 0xc50, BIT(8), 1); /* regc50[8]=1'b1 */ /* " CS/CG switching" is controled by HWs */
+
+ /* Mapping table */
+ odm_set_bb_reg(dm, 0x914, 0xFFFF, 0x0100); /* antenna mapping table */
+
+ /* OFDM Settings */
+ odm_set_bb_reg(dm, 0xca4, 0x7FF, 0xA0); /* thershold */
+ odm_set_bb_reg(dm, 0xca4, 0x7FF000, 0x0); /* bias */
+
+ /* CCK Settings */
+ odm_set_bb_reg(dm, 0xa04, 0xF000000, 0); /* Select which path to receive for CCK_1 & CCK_2 */
+ odm_set_bb_reg(dm, 0xb34, BIT(30), 0); /* (92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */
+ odm_set_bb_reg(dm, 0xa74, BIT(7), 1); /* Fix CCK PHY status report issue */
+ odm_set_bb_reg(dm, 0xa0c, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */
+
+#ifdef ODM_EVM_ENHANCE_ANTDIV
+ phydm_evm_sw_antdiv_init(dm);
+#endif
+
}
-VOID
-odm_TRX_HWAntDiv_Init_92E(
- IN PVOID pDM_VOID
+void
+odm_trx_hw_ant_div_init_92e(
+ void *dm_void
)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
-
- if(pDM_Odm->mp_mode == TRUE)
- {
- odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);
- ODM_SetBBReg(pDM_Odm, 0xc50 , BIT8, 0); //r_rxdiv_enable_anta Regc50[8]=1'b0 0: control by c50[9]
- ODM_SetBBReg(pDM_Odm, 0xc50 , BIT9, 1); // 1:CG, 0:CS
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+#if 0
+ if (*(dm->mp_mode) == true) {
+ odm_ant_div_on_off(dm, ANTDIV_OFF);
+ odm_set_bb_reg(dm, 0xc50, BIT(8), 0); /* r_rxdiv_enable_anta regc50[8]=1'b0 0: control by c50[9] */
+ odm_set_bb_reg(dm, 0xc50, BIT(9), 1); /* 1:CG, 0:CS */
return;
}
+#endif
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8192E AntDiv_Init => AntDivType=[ Only for DIR605, CG_TRX_HW_ANTDIV]\n"));
-
- //3 --RFE pin setting---------
- //[MAC]
- ODM_SetMACReg(pDM_Odm, 0x38, BIT11, 1); //DBG PAD Driving control (GPIO 8)
- ODM_SetMACReg(pDM_Odm, 0x4c, BIT23, 0); //path-A , RFE_CTRL_3
- ODM_SetMACReg(pDM_Odm, 0x4c, BIT29, 1); //path-A , RFE_CTRL_8
- //[BB]
- ODM_SetBBReg(pDM_Odm, 0x944 , BIT3, 1); //RFE_buffer
- ODM_SetBBReg(pDM_Odm, 0x944 , BIT8, 1);
- ODM_SetBBReg(pDM_Odm, 0x940 , BIT7|BIT6, 0x0); // r_rfe_path_sel_ (RFE_CTRL_3)
- ODM_SetBBReg(pDM_Odm, 0x940 , BIT17|BIT16, 0x0); // r_rfe_path_sel_ (RFE_CTRL_8)
- ODM_SetBBReg(pDM_Odm, 0x944 , BIT31, 0); //RFE_buffer
- ODM_SetBBReg(pDM_Odm, 0x92C , BIT3, 0); //rfe_inv (RFE_CTRL_3)
- ODM_SetBBReg(pDM_Odm, 0x92C , BIT8, 1); //rfe_inv (RFE_CTRL_8)
- ODM_SetBBReg(pDM_Odm, 0x930 , 0xF000, 0x8); //path-A , RFE_CTRL_3
- ODM_SetBBReg(pDM_Odm, 0x934 , 0xF, 0x8); //path-A , RFE_CTRL_8
- //3 -------------------------
-
- //Pin Settings
- ODM_SetBBReg(pDM_Odm, 0xC50 , BIT8, 0); //path-A //disable CS/CG switch
+ PHYDM_DBG(dm, DBG_ANT_DIV, "***8192E AntDiv_Init => ant_div_type=[ Only for DIR605, CG_TRX_HW_ANTDIV]\n");
+
+ /* 3 --RFE pin setting--------- */
+ /* [MAC] */
+ odm_set_mac_reg(dm, 0x38, BIT(11), 1); /* DBG PAD Driving control (GPIO 8) */
+ odm_set_mac_reg(dm, 0x4c, BIT(23), 0); /* path-A, RFE_CTRL_3 */
+ odm_set_mac_reg(dm, 0x4c, BIT(29), 1); /* path-A, RFE_CTRL_8 */
+ /* [BB] */
+ odm_set_bb_reg(dm, 0x944, BIT(3), 1); /* RFE_buffer */
+ odm_set_bb_reg(dm, 0x944, BIT(8), 1);
+ odm_set_bb_reg(dm, 0x940, BIT(7) | BIT(6), 0x0); /* r_rfe_path_sel_ (RFE_CTRL_3) */
+ odm_set_bb_reg(dm, 0x940, BIT(17) | BIT(16), 0x0); /* r_rfe_path_sel_ (RFE_CTRL_8) */
+ odm_set_bb_reg(dm, 0x944, BIT(31), 0); /* RFE_buffer */
+ odm_set_bb_reg(dm, 0x92C, BIT(3), 0); /* rfe_inv (RFE_CTRL_3) */
+ odm_set_bb_reg(dm, 0x92C, BIT(8), 1); /* rfe_inv (RFE_CTRL_8) */
+ odm_set_bb_reg(dm, 0x930, 0xF000, 0x8); /* path-A, RFE_CTRL_3 */
+ odm_set_bb_reg(dm, 0x934, 0xF, 0x8); /* path-A, RFE_CTRL_8 */
+ /* 3 ------------------------- */
+
+ /* Pin Settings */
+ odm_set_bb_reg(dm, 0xC50, BIT(8), 0); /* path-A */ /* disable CS/CG switch */
-/* Let it follows PHY_REG for bit9 setting
- if(pDM_Odm->priv->pshare->rf_ft_var.use_ext_pa || pDM_Odm->priv->pshare->rf_ft_var.use_ext_lna)
- ODM_SetBBReg(pDM_Odm, 0xC50 , BIT9, 1);//path-A //output at CS
+#if 0
+ /* Let it follows PHY_REG for bit9 setting */
+ if (dm->priv->pshare->rf_ft_var.use_ext_pa || dm->priv->pshare->rf_ft_var.use_ext_lna)
+ odm_set_bb_reg(dm, 0xC50, BIT(9), 1); /* path-A output at CS */
else
- ODM_SetBBReg(pDM_Odm, 0xC50 , BIT9, 0); //path-A //output at CG ->normal power
-*/
+ odm_set_bb_reg(dm, 0xC50, BIT(9), 0); /* path-A output at CG ->normal power */
+#endif
+
+ odm_set_bb_reg(dm, 0x870, BIT(9) | BIT(8), 0); /* path-A*/ /* antsel antselb by HW */
+ odm_set_bb_reg(dm, 0xB38, BIT(10), 0); /* path-A */ /* antsel2 by HW */
+
+ /* Mapping table */
+ odm_set_bb_reg(dm, 0x914, 0xFFFF, 0x0100); /* antenna mapping table */
- ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0); //path-A //antsel antselb by HW
- ODM_SetBBReg(pDM_Odm, 0xB38 , BIT10, 0); //path-A //antsel2 by HW
-
- //Mapping table
- ODM_SetBBReg(pDM_Odm, 0x914 , 0xFFFF, 0x0100); //antenna mapping table
-
- //OFDM Settings
- ODM_SetBBReg(pDM_Odm, 0xca4 , 0x7FF, 0xA0); //thershold
- ODM_SetBBReg(pDM_Odm, 0xca4 , 0x7FF000, 0x0); //bias
-
- //CCK Settings
- ODM_SetBBReg(pDM_Odm, 0xa04 , 0xF000000, 0); //Select which path to receive for CCK_1 & CCK_2
- ODM_SetBBReg(pDM_Odm, 0xb34 , BIT30, 0); //(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0
- ODM_SetBBReg(pDM_Odm, 0xa74 , BIT7, 1); //Fix CCK PHY status report issue
- ODM_SetBBReg(pDM_Odm, 0xa0c , BIT4, 1); //CCK complete HW AntDiv within 64 samples
-
- #ifdef ODM_EVM_ENHANCE_ANTDIV
- //EVM enhance AntDiv method init----------------------------------------------------------------------
- pDM_FatTable->EVM_method_enable=0;
- pDM_FatTable->FAT_State = NORMAL_STATE_MIAN;
- pDM_Odm->antdiv_intvl = 0x64;
- ODM_SetBBReg(pDM_Odm, 0x910 , 0x3f, 0xf );
- pDM_Odm->antdiv_evm_en=1;
- //pDM_Odm->antdiv_period=1;
- pDM_Odm->evm_antdiv_period = 3;
- #endif
+ /* OFDM Settings */
+ odm_set_bb_reg(dm, 0xca4, 0x7FF, 0xA0); /* thershold */
+ odm_set_bb_reg(dm, 0xca4, 0x7FF000, 0x0); /* bias */
+
+ /* CCK Settings */
+ odm_set_bb_reg(dm, 0xa04, 0xF000000, 0); /* Select which path to receive for CCK_1 & CCK_2 */
+ odm_set_bb_reg(dm, 0xb34, BIT(30), 0); /* (92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */
+ odm_set_bb_reg(dm, 0xa74, BIT(7), 1); /* Fix CCK PHY status report issue */
+ odm_set_bb_reg(dm, 0xa0c, BIT(4), 1); /* CCK complete HW AntDiv within 64 samples */
+
+#ifdef ODM_EVM_ENHANCE_ANTDIV
+ phydm_evm_sw_antdiv_init(dm);
+#endif
}
-#if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) )
-VOID
-odm_Smart_HWAntDiv_Init_92E(
- IN PVOID pDM_VOID
+#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
+void
+odm_smart_hw_ant_div_init_92e(
+ void *dm_void
)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8192E AntDiv_Init => AntDivType=[CG_TRX_SMART_ANTDIV]\n"));
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+ PHYDM_DBG(dm, DBG_ANT_DIV, "***8192E AntDiv_Init => ant_div_type=[CG_TRX_SMART_ANTDIV]\n");
}
#endif
-#endif //#if (RTL8192E_SUPPORT == 1)
+#endif /* #if (RTL8192E_SUPPORT == 1) */
#if (RTL8723D_SUPPORT == 1)
-VOID
-odm_TRX_HWAntDiv_Init_8723D(
- IN PVOID pDM_VOID
+void
+odm_trx_hw_ant_div_init_8723d(
+ void *dm_void
)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8723D] AntDiv_Init => AntDivType=[S0S1_HW_TRX_AntDiv]\n"));
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[8723D] AntDiv_Init => ant_div_type=[S0S1_HW_TRX_AntDiv]\n");
/*BT Coexistence*/
/*keep antsel_map when GNT_BT = 1*/
- ODM_SetBBReg(pDM_Odm, 0x864, BIT12, 1);
- /* //Disable hw antsw & fast_train.antsw when GNT_BT=1*/
- ODM_SetBBReg(pDM_Odm, 0x874 , BIT23, 0);
- /*//Disable hw antsw & fast_train.antsw when BT TX/RX*/
- ODM_SetBBReg(pDM_Odm, 0xE64 , 0xFFFF0000, 0x000c);
+ odm_set_bb_reg(dm, 0x864, BIT(12), 1);
+ /* Disable hw antsw & fast_train.antsw when GNT_BT=1 */
+ odm_set_bb_reg(dm, 0x874, BIT(23), 0);
+ /* Disable hw antsw & fast_train.antsw when BT TX/RX */
+ odm_set_bb_reg(dm, 0xE64, 0xFFFF0000, 0x000c);
- ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0);
+ odm_set_bb_reg(dm, 0x870, BIT(9) | BIT(8), 0);
/*PTA setting: WL_BB_SEL_BTG_TRXG_anta, (1: HW CTRL 0: SW CTRL)*/
- /*ODM_SetBBReg(pDM_Odm, 0x948 , BIT6, 0);*/
- /*ODM_SetBBReg(pDM_Odm, 0x948 , BIT8, 0);*/
+ /*odm_set_bb_reg(dm, 0x948, BIT6, 0);*/
+ /*odm_set_bb_reg(dm, 0x948, BIT8, 0);*/
/*GNT_WL tx*/
- ODM_SetBBReg(pDM_Odm, 0x950 , BIT29, 0);
-
-
+ odm_set_bb_reg(dm, 0x950, BIT(29), 0);
+
+
/*Mapping Table*/
- ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 0);
- ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 3);
- ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, 0);
- ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, 1);
-
- /* //Set WLBB_SEL_RF_ON 1 if RXFIR_PWDB > 0xCcc[3:0]*/
- ODM_SetBBReg(pDM_Odm, 0xCcc, BIT12, 0);
- /* //Low-to-High threshold for WLBB_SEL_RF_ON when OFDM enable*/
- ODM_SetBBReg(pDM_Odm, 0xCcc , 0x0F, 0x01);
- /*//High-to-Low threshold for WLBB_SEL_RF_ON when OFDM enable*/
- ODM_SetBBReg(pDM_Odm, 0xCcc , 0xF0, 0x0);
- /* //b Low-to-High threshold for WLBB_SEL_RF_ON when OFDM disable ( only CCK )*/
- ODM_SetBBReg(pDM_Odm, 0xAbc , 0xFF, 0x06);
- /* //High-to-Low threshold for WLBB_SEL_RF_ON when OFDM disable ( only CCK )*/
- ODM_SetBBReg(pDM_Odm, 0xAbc , 0xFF00, 0x00);
-
-
+ odm_set_bb_reg(dm, 0x914, MASKBYTE0, 0);
+ odm_set_bb_reg(dm, 0x914, MASKBYTE1, 3);
+ /* odm_set_bb_reg(dm, 0x864, BIT5|BIT4|BIT3, 0); */
+ /* odm_set_bb_reg(dm, 0x864, BIT8|BIT7|BIT6, 1); */
+
+ /* Set WLBB_SEL_RF_ON 1 if RXFIR_PWDB > 0xCcc[3:0] */
+ odm_set_bb_reg(dm, 0xCcc, BIT(12), 0);
+ /* Low-to-High threshold for WLBB_SEL_RF_ON when OFDM enable */
+ odm_set_bb_reg(dm, 0xCcc, 0x0F, 0x01);
+ /* High-to-Low threshold for WLBB_SEL_RF_ON when OFDM enable */
+ odm_set_bb_reg(dm, 0xCcc, 0xF0, 0x0);
+ /* b Low-to-High threshold for WLBB_SEL_RF_ON when OFDM disable ( only CCK ) */
+ odm_set_bb_reg(dm, 0xAbc, 0xFF, 0x06);
+ /* High-to-Low threshold for WLBB_SEL_RF_ON when OFDM disable ( only CCK ) */
+ odm_set_bb_reg(dm, 0xAbc, 0xFF00, 0x00);
+
+
/*OFDM HW AntDiv Parameters*/
- ODM_SetBBReg(pDM_Odm, 0xCA4 , 0x7FF, 0xa0);
- ODM_SetBBReg(pDM_Odm, 0xCA4 , 0x7FF000, 0x00);
- ODM_SetBBReg(pDM_Odm, 0xC5C , BIT20|BIT19|BIT18, 0x04);
-
+ odm_set_bb_reg(dm, 0xCA4, 0x7FF, 0xa0);
+ odm_set_bb_reg(dm, 0xCA4, 0x7FF000, 0x00);
+ odm_set_bb_reg(dm, 0xC5C, BIT(20) | BIT(19) | BIT(18), 0x04);
+
/*CCK HW AntDiv Parameters*/
- ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1);
- ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1);
- ODM_SetBBReg(pDM_Odm, 0xAA8 , BIT8, 0);
-
- ODM_SetBBReg(pDM_Odm, 0xA0C , 0x0F, 0xf);
- ODM_SetBBReg(pDM_Odm, 0xA14 , 0x1F, 0x8);
- ODM_SetBBReg(pDM_Odm, 0xA10 , BIT13, 0x1);
- ODM_SetBBReg(pDM_Odm, 0xA74 , BIT8, 0x0);
- ODM_SetBBReg(pDM_Odm, 0xB34 , BIT30, 0x1);
-
+ odm_set_bb_reg(dm, 0xA74, BIT(7), 1);
+ odm_set_bb_reg(dm, 0xA0C, BIT(4), 1);
+ odm_set_bb_reg(dm, 0xAA8, BIT(8), 0);
+
+ odm_set_bb_reg(dm, 0xA0C, 0x0F, 0xf);
+ odm_set_bb_reg(dm, 0xA14, 0x1F, 0x8);
+ odm_set_bb_reg(dm, 0xA10, BIT(13), 0x1);
+ odm_set_bb_reg(dm, 0xA74, BIT(8), 0x0);
+ odm_set_bb_reg(dm, 0xB34, BIT(30), 0x1);
+
/*disable antenna training */
- ODM_SetBBReg(pDM_Odm, 0xE08 , BIT16, 0);
- ODM_SetBBReg(pDM_Odm, 0xc50 , BIT8, 0);
+ odm_set_bb_reg(dm, 0xE08, BIT(16), 0);
+ odm_set_bb_reg(dm, 0xc50, BIT(8), 0);
+
+}
+/*Mingzhi 2017-05-08*/
+
+void
+odm_update_rx_idle_ant_8723d(
+ void *dm_void,
+ u8 ant,
+ u32 default_ant,
+ u32 optional_ant
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+ void *adapter = dm->adapter;
+ u8 count = 0;
+
+
+/* odm_set_bb_reg(dm, 0x948, BIT(6), 0x1); */
+ odm_set_bb_reg(dm, 0x948, BIT(7), default_ant);
+ odm_set_bb_reg(dm, 0x864, BIT(5) | BIT(4) | BIT(3), default_ant); /*Default RX*/
+ odm_set_bb_reg(dm, 0x864, BIT(8) | BIT(7) | BIT(6), optional_ant); /*Optional RX*/
+ odm_set_bb_reg(dm, 0x860, BIT(14) | BIT(13) | BIT(12), default_ant); /*Default TX*/
+ fat_tab->rx_idle_ant = ant;
}
-VOID
+void
phydm_set_tx_ant_pwr_8723d(
- IN PVOID pDM_VOID,
- IN u1Byte Ant
+ void *dm_void,
+ u8 ant
)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
- PADAPTER pAdapter = pDM_Odm->Adapter;
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+ PADAPTER adapter = (PADAPTER)dm->adapter;
+
+ fat_tab->rx_idle_ant = ant;
+
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+ adapter->HalFunc.SetTxPowerLevelHandler(adapter, *dm->channel);
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ rtw_hal_set_tx_power_level(adapter, *dm->channel);
+#endif
- pDM_FatTable->RxIdleAnt = Ant;
-
- #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
- pAdapter->HalFunc.SetTxPowerLevelHandler(pAdapter, pHalData->CurrentChannel);
- #elif(DM_ODM_SUPPORT_TYPE == ODM_CE)
- rtw_hal_set_tx_power_level(pAdapter, pHalData->CurrentChannel);
- #endif
-
}
#endif
#if (RTL8723B_SUPPORT == 1)
-VOID
-odm_TRX_HWAntDiv_Init_8723B(
- IN PVOID pDM_VOID
+void
+odm_trx_hw_ant_div_init_8723b(
+ void *dm_void
)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8723B AntDiv_Init => AntDivType=[CG_TRX_HW_ANTDIV(DPDT)]\n"));
-
- //Mapping Table
- ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 0);
- ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 1);
-
- //OFDM HW AntDiv Parameters
- ODM_SetBBReg(pDM_Odm, 0xCA4 , 0x7FF, 0xa0); //thershold
- ODM_SetBBReg(pDM_Odm, 0xCA4 , 0x7FF000, 0x00); //bias
-
- //CCK HW AntDiv Parameters
- ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M
- ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples
-
- //BT Coexistence
- ODM_SetBBReg(pDM_Odm, 0x864, BIT12, 0); //keep antsel_map when GNT_BT = 1
- ODM_SetBBReg(pDM_Odm, 0x874 , BIT23, 0); //Disable hw antsw & fast_train.antsw when GNT_BT=1
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
- //Output Pin Settings
- ODM_SetBBReg(pDM_Odm, 0x870 , BIT8, 0); //
-
- ODM_SetBBReg(pDM_Odm, 0x948 , BIT6, 0); //WL_BB_SEL_BTG_TRXG_anta, (1: HW CTRL 0: SW CTRL)
- ODM_SetBBReg(pDM_Odm, 0x948 , BIT7, 0);
-
- ODM_SetMACReg(pDM_Odm, 0x40 , BIT3, 1);
- ODM_SetMACReg(pDM_Odm, 0x38 , BIT11, 1);
- ODM_SetMACReg(pDM_Odm, 0x4C , BIT24|BIT23, 2); //select DPDT_P and DPDT_N as output pin
-
- ODM_SetBBReg(pDM_Odm, 0x944 , BIT0|BIT1, 3); //in/out
- ODM_SetBBReg(pDM_Odm, 0x944 , BIT31, 0); //
+ PHYDM_DBG(dm, DBG_ANT_DIV, "***8723B AntDiv_Init => ant_div_type=[CG_TRX_HW_ANTDIV(DPDT)]\n");
+
+ /* Mapping Table */
+ odm_set_bb_reg(dm, 0x914, MASKBYTE0, 0);
+ odm_set_bb_reg(dm, 0x914, MASKBYTE1, 1);
+
+ /* OFDM HW AntDiv Parameters */
+ odm_set_bb_reg(dm, 0xCA4, 0x7FF, 0xa0); /* thershold */
+ odm_set_bb_reg(dm, 0xCA4, 0x7FF000, 0x00); /* bias */
- ODM_SetBBReg(pDM_Odm, 0x92C , BIT1, 0); //DPDT_P non-inverse
- ODM_SetBBReg(pDM_Odm, 0x92C , BIT0, 1); //DPDT_N inverse
+ /* CCK HW AntDiv Parameters */
+ odm_set_bb_reg(dm, 0xA74, BIT(7), 1); /* patch for clk from 88M to 80M */
+ odm_set_bb_reg(dm, 0xA0C, BIT(4), 1); /* do 64 samples */
- ODM_SetBBReg(pDM_Odm, 0x930 , 0xF0, 8); // DPDT_P = ANTSEL[0]
- ODM_SetBBReg(pDM_Odm, 0x930 , 0xF, 8); // DPDT_N = ANTSEL[0]
+ /* BT Coexistence */
+ odm_set_bb_reg(dm, 0x864, BIT(12), 0); /* keep antsel_map when GNT_BT = 1 */
+ odm_set_bb_reg(dm, 0x874, BIT(23), 0); /* Disable hw antsw & fast_train.antsw when GNT_BT=1 */
- //2 [--For HW Bug Setting]
- if(pDM_Odm->AntType == ODM_AUTO_ANT)
- ODM_SetBBReg(pDM_Odm, 0xA00 , BIT15, 0); //CCK AntDiv function block enable
+ /* Output Pin Settings */
+ odm_set_bb_reg(dm, 0x870, BIT(8), 0);
+
+ odm_set_bb_reg(dm, 0x948, BIT(6), 0); /* WL_BB_SEL_BTG_TRXG_anta, (1: HW CTRL 0: SW CTRL) */
+ odm_set_bb_reg(dm, 0x948, BIT(7), 0);
+
+ odm_set_mac_reg(dm, 0x40, BIT(3), 1);
+ odm_set_mac_reg(dm, 0x38, BIT(11), 1);
+ odm_set_mac_reg(dm, 0x4C, BIT(24) | BIT(23), 2); /* select DPDT_P and DPDT_N as output pin */
+
+ odm_set_bb_reg(dm, 0x944, BIT(0) | BIT(1), 3); /* in/out */
+ odm_set_bb_reg(dm, 0x944, BIT(31), 0);
+
+ odm_set_bb_reg(dm, 0x92C, BIT(1), 0); /* DPDT_P non-inverse */
+ odm_set_bb_reg(dm, 0x92C, BIT(0), 1); /* DPDT_N inverse */
+
+ odm_set_bb_reg(dm, 0x930, 0xF0, 8); /* DPDT_P = ANTSEL[0] */
+ odm_set_bb_reg(dm, 0x930, 0xF, 8); /* DPDT_N = ANTSEL[0] */
+
+ /* 2 [--For HW Bug setting] */
+ if (dm->ant_type == ODM_AUTO_ANT)
+ odm_set_bb_reg(dm, 0xA00, BIT(15), 0); /* CCK AntDiv function block enable */
}
-
-VOID
-odm_S0S1_SWAntDiv_Init_8723B(
- IN PVOID pDM_VOID
+
+void
+odm_s0s1_sw_ant_div_init_8723b(
+ void *dm_void
)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
- pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
+ struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8723B AntDiv_Init => AntDivType=[ S0S1_SW_AntDiv] \n"));
+ PHYDM_DBG(dm, DBG_ANT_DIV, "***8723B AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n");
- //Mapping Table
- ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 0);
- ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 1);
-
- //Output Pin Settings
- //ODM_SetBBReg(pDM_Odm, 0x948 , BIT6, 0x1);
- ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0);
+ /* Mapping Table */
+ odm_set_bb_reg(dm, 0x914, MASKBYTE0, 0);
+ odm_set_bb_reg(dm, 0x914, MASKBYTE1, 1);
- pDM_FatTable->bBecomeLinked =FALSE;
- pDM_SWAT_Table->try_flag = SWAW_STEP_INIT;
- pDM_SWAT_Table->Double_chk_flag = 0;
-
- //2 [--For HW Bug Setting]
- ODM_SetBBReg(pDM_Odm, 0x80C , BIT21, 0); //TX Ant by Reg
+ /* Output Pin Settings */
+ /* odm_set_bb_reg(dm, 0x948, BIT6, 0x1); */
+ odm_set_bb_reg(dm, 0x870, BIT(9) | BIT(8), 0);
+
+ fat_tab->is_become_linked = false;
+ dm_swat_table->try_flag = SWAW_STEP_INIT;
+ dm_swat_table->double_chk_flag = 0;
+
+ /* 2 [--For HW Bug setting] */
+ odm_set_bb_reg(dm, 0x80C, BIT(21), 0); /* TX ant by Reg */
}
-VOID
-ODM_UpdateRxIdleAnt_8723B(
- IN PVOID pDM_VOID,
- IN u1Byte Ant,
- IN u4Byte DefaultAnt,
- IN u4Byte OptionalAnt
+void
+odm_update_rx_idle_ant_8723b(
+ void *dm_void,
+ u8 ant,
+ u32 default_ant,
+ u32 optional_ant
)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
- PADAPTER pAdapter = pDM_Odm->Adapter;
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
- u1Byte count=0;
- u1Byte u1Temp;
- u1Byte H2C_Parameter;
-
- if ((!pDM_Odm->bLinked) && (pDM_Odm->AntType == ODM_AUTO_ANT))
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: Fail to set RX antenna due to no link\n"));
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+ PADAPTER adapter = (PADAPTER)dm->adapter;
+ u8 count = 0;
+ /*u8 u1_temp;*/
+ /*u8 h2c_parameter;*/
+
+ if ((!dm->is_linked) && (dm->ant_type == ODM_AUTO_ANT)) {
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to no link\n");
return;
}
#if 0
- // Send H2C command to FW
- // Enable wifi calibration
- H2C_Parameter = TRUE;
- ODM_FillH2CCmd(pDM_Odm, ODM_H2C_WIFI_CALIBRATION, 1, &H2C_Parameter);
-
- // Check if H2C command sucess or not (0x1e6)
- u1Temp = ODM_Read1Byte(pDM_Odm, 0x1e6);
- while((u1Temp != 0x1) && (count < 100))
- {
- ODM_delay_us(10);
- u1Temp = ODM_Read1Byte(pDM_Odm, 0x1e6);
+ /* Send H2C command to FW */
+ /* Enable wifi calibration */
+ h2c_parameter = true;
+ odm_fill_h2c_cmd(dm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter);
+
+ /* Check if H2C command sucess or not (0x1e6) */
+ u1_temp = odm_read_1byte(dm, 0x1e6);
+ while ((u1_temp != 0x1) && (count < 100)) {
+ ODM_delay_us(10);
+ u1_temp = odm_read_1byte(dm, 0x1e6);
count++;
}
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: H2C command status = %d, count = %d\n", u1Temp, count));
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[ Update Rx-Idle-ant ] 8723B: H2C command status = %d, count = %d\n", u1_temp, count);
- if(u1Temp == 0x1)
- {
- // Check if BT is doing IQK (0x1e7)
+ if (u1_temp == 0x1) {
+ /* Check if BT is doing IQK (0x1e7) */
count = 0;
- u1Temp = ODM_Read1Byte(pDM_Odm, 0x1e7);
- while((!(u1Temp & BIT0)) && (count < 100))
- {
- ODM_delay_us(50);
- u1Temp = ODM_Read1Byte(pDM_Odm, 0x1e7);
+ u1_temp = odm_read_1byte(dm, 0x1e7);
+ while ((!(u1_temp & BIT(0))) && (count < 100)) {
+ ODM_delay_us(50);
+ u1_temp = odm_read_1byte(dm, 0x1e7);
count++;
}
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: BT IQK status = %d, count = %d\n", u1Temp, count));
-
- if(u1Temp & BIT0)
- {
- ODM_SetBBReg(pDM_Odm, 0x948 , BIT6, 0x1);
- ODM_SetBBReg(pDM_Odm, 0x948 , BIT9, DefaultAnt);
- ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, DefaultAnt); //Default RX
- ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, OptionalAnt); //Optional RX
- ODM_SetBBReg(pDM_Odm, 0x860, BIT14|BIT13|BIT12, DefaultAnt); //Default TX
- pDM_FatTable->RxIdleAnt = Ant;
-
- // Set TX AGC by S0/S1
- // Need to consider Linux driver
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[ Update Rx-Idle-ant ] 8723B: BT IQK status = %d, count = %d\n", u1_temp, count);
+
+ if (u1_temp & BIT(0)) {
+ odm_set_bb_reg(dm, 0x948, BIT(6), 0x1);
+ odm_set_bb_reg(dm, 0x948, BIT(9), default_ant);
+ odm_set_bb_reg(dm, 0x864, BIT(5) | BIT4 | BIT3, default_ant); /* Default RX */
+ odm_set_bb_reg(dm, 0x864, BIT(8) | BIT7 | BIT6, optional_ant); /* Optional RX */
+ odm_set_bb_reg(dm, 0x860, BIT(14) | BIT13 | BIT12, default_ant); /* Default TX */
+ fat_tab->rx_idle_ant = ant;
+
+ /* Set TX AGC by S0/S1 */
+ /* Need to consider Linux driver */
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
- pAdapter->HalFunc.SetTxPowerLevelHandler(pAdapter, pHalData->CurrentChannel);
-#elif(DM_ODM_SUPPORT_TYPE == ODM_CE)
- rtw_hal_set_tx_power_level(pAdapter, pHalData->CurrentChannel);
+ adapter->hal_func.set_tx_power_level_handler(adapter, *dm->channel);
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ rtw_hal_set_tx_power_level(adapter, *dm->channel);
#endif
- // Set IQC by S0/S1
- ODM_SetIQCbyRFpath(pDM_Odm,DefaultAnt);
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: Sucess to set RX antenna\n"));
- }
- else
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: Fail to set RX antenna due to BT IQK\n"));
- }
- else
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: Fail to set RX antenna due to H2C command fail\n"));
-
- // Send H2C command to FW
- // Disable wifi calibration
- H2C_Parameter = FALSE;
- ODM_FillH2CCmd(pDM_Odm, ODM_H2C_WIFI_CALIBRATION, 1, &H2C_Parameter);
+ /* Set IQC by S0/S1 */
+ odm_set_iqc_by_rfpath(dm, default_ant);
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[ Update Rx-Idle-ant ] 8723B: Success to set RX antenna\n");
+ } else
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to BT IQK\n");
+ } else
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to H2C command fail\n");
+
+ /* Send H2C command to FW */
+ /* Disable wifi calibration */
+ h2c_parameter = false;
+ odm_fill_h2c_cmd(dm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter);
#else
- ODM_SetBBReg(pDM_Odm, 0x948 , BIT6, 0x1);
- ODM_SetBBReg(pDM_Odm, 0x948 , BIT9, DefaultAnt);
- ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, DefaultAnt); /*Default RX*/
- ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, OptionalAnt); /*Optional RX*/
- ODM_SetBBReg(pDM_Odm, 0x860, BIT14|BIT13|BIT12, DefaultAnt); /*Default TX*/
- pDM_FatTable->RxIdleAnt = Ant;
+ odm_set_bb_reg(dm, 0x948, BIT(6), 0x1);
+ odm_set_bb_reg(dm, 0x948, BIT(9), default_ant);
+ odm_set_bb_reg(dm, 0x864, BIT(5) | BIT(4) | BIT(3), default_ant); /*Default RX*/
+ odm_set_bb_reg(dm, 0x864, BIT(8) | BIT(7) | BIT(6), optional_ant); /*Optional RX*/
+ odm_set_bb_reg(dm, 0x860, BIT(14) | BIT(13) | BIT(12), default_ant); /*Default TX*/
+ fat_tab->rx_idle_ant = ant;
/* Set TX AGC by S0/S1 */
/* Need to consider Linux driver */
- #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
- pAdapter->HalFunc.SetTxPowerLevelHandler(pAdapter, pHalData->CurrentChannel);
- #elif(DM_ODM_SUPPORT_TYPE == ODM_CE)
- rtw_hal_set_tx_power_level(pAdapter, pHalData->CurrentChannel);
- #endif
+#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
+ adapter->HalFunc.SetTxPowerLevelHandler(adapter, *dm->channel);
+#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
+ rtw_hal_set_tx_power_level(adapter, *dm->channel);
+#endif
/* Set IQC by S0/S1 */
- ODM_SetIQCbyRFpath(pDM_Odm, DefaultAnt);
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: Success to set RX antenna\n"));
+ odm_set_iqc_by_rfpath(dm, default_ant);
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[ Update Rx-Idle-ant ] 8723B: Success to set RX antenna\n");
#endif
}
-BOOLEAN
-phydm_IsBtEnable_8723b(
- IN PVOID pDM_VOID
+boolean
+phydm_is_bt_enable_8723b(
+ void *dm_void
)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- u4Byte bt_state;
- /*u4Byte reg75;*/
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ u32 bt_state;
+ /*u32 reg75;*/
- /*reg75 = ODM_GetBBReg(pDM_Odm, 0x74 , BIT8);*/
- /*ODM_SetBBReg(pDM_Odm, 0x74 , BIT8, 0x0);*/
- ODM_SetBBReg(pDM_Odm, 0xa0 , BIT24|BIT25|BIT26, 0x5);
- bt_state = ODM_GetBBReg(pDM_Odm, 0xa0 , (BIT3|BIT2|BIT1|BIT0));
- /*ODM_SetBBReg(pDM_Odm, 0x74 , BIT8, reg75);*/
+ /*reg75 = odm_get_bb_reg(dm, 0x74, BIT8);*/
+ /*odm_set_bb_reg(dm, 0x74, BIT8, 0x0);*/
+ odm_set_bb_reg(dm, 0xa0, BIT(24) | BIT(25) | BIT(26), 0x5);
+ bt_state = odm_get_bb_reg(dm, 0xa0, (BIT(3) | BIT(2) | BIT(1) | BIT(0)));
+ /*odm_set_bb_reg(dm, 0x74, BIT8, reg75);*/
if ((bt_state == 4) || (bt_state == 7) || (bt_state == 9) || (bt_state == 13))
- return TRUE;
+ return true;
else
- return FALSE;
+ return false;
}
-#endif //#if (RTL8723B_SUPPORT == 1)
+#endif /* #if (RTL8723B_SUPPORT == 1) */
#if (RTL8821A_SUPPORT == 1)
-#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
-VOID
-phydm_hl_smart_ant_type1_init_8821a(
- IN PVOID pDM_VOID
- )
+
+void
+odm_trx_hw_ant_div_init_8821a(
+ void *dm_void
+)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table);
- pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
- u4Byte value32;
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821A SmartAnt_Init => AntDivType=[Hong-Lin Smart Ant Type1]\n"));
-
- /*----------------------------------------
- GPIO 2-3 for Beam control
- reg0x66[2]=0
- reg0x44[27:26] = 0
- reg0x44[23:16] //enable_output for P_GPIO[7:0]
- reg0x44[15:8] //output_value for P_GPIO[7:0]
- reg0x40[1:0] = 0 //GPIO function
- ------------------------------------------*/
-
- /*GPIO Setting*/
- ODM_SetMACReg(pDM_Odm, 0x64 , BIT18, 0);
- ODM_SetMACReg(pDM_Odm, 0x44 , BIT27|BIT26, 0);
- ODM_SetMACReg(pDM_Odm, 0x44 , BIT19|BIT18, 0x3); /*enable_output for P_GPIO[3:2]*/
- /*ODM_SetMACReg(pDM_Odm, 0x44 , BIT11|BIT10, 0);*/ /*output value*/
- ODM_SetMACReg(pDM_Odm, 0x40 , BIT1|BIT0, 0); /*GPIO function*/
-
- /*Hong_lin smart antenna HW Setting*/
- pdm_sat_table->data_codeword_bit_num = 24;/*max=32*/
- pdm_sat_table->beam_patten_num_each_ant = 4;
-
- #if DEV_BUS_TYPE == RT_SDIO_INTERFACE
- pdm_sat_table->latch_time = 100; /*mu sec*/
- #elif DEV_BUS_TYPE == RT_USB_INTERFACE
- pdm_sat_table->latch_time = 100; /*mu sec*/
- #endif
- pdm_sat_table->pkt_skip_statistic_en = 0;
-
- pdm_sat_table->ant_num = 1;/*max=8*/
- pdm_sat_table->ant_num_total = NUM_ANTENNA_8821A;
- pdm_sat_table->first_train_ant = MAIN_ANT;
-
- pdm_sat_table->rfu_codeword_table[0] = 0x0;
- pdm_sat_table->rfu_codeword_table[1] = 0x4;
- pdm_sat_table->rfu_codeword_table[2] = 0x8;
- pdm_sat_table->rfu_codeword_table[3] = 0xc;
-
- pdm_sat_table->rfu_codeword_table_5g[0] = 0x1;
- pdm_sat_table->rfu_codeword_table_5g[1] = 0x2;
- pdm_sat_table->rfu_codeword_table_5g[2] = 0x4;
- pdm_sat_table->rfu_codeword_table_5g[3] = 0x8;
-
- pdm_sat_table->fix_beam_pattern_en = 0;
- pdm_sat_table->decision_holding_period = 0;
-
- /*beam training setting*/
- pdm_sat_table->pkt_counter = 0;
- pdm_sat_table->per_beam_training_pkt_num = 10;
-
- /*set default beam*/
- pdm_sat_table->fast_training_beam_num = 0;
- pdm_sat_table->pre_fast_training_beam_num = pdm_sat_table->fast_training_beam_num;
- phydm_set_all_ant_same_beam_num(pDM_Odm);
-
- pDM_FatTable->FAT_State = FAT_BEFORE_LINK_STATE;
-
- ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskDWord, 0x01000100);
- ODM_SetBBReg(pDM_Odm, 0xCA8 , bMaskDWord, 0x01000100);
-
- /*[BB] FAT Setting*/
- ODM_SetBBReg(pDM_Odm, 0xc08 , BIT18|BIT17|BIT16, pdm_sat_table->ant_num);
- ODM_SetBBReg(pDM_Odm, 0xc08 , BIT31, 0); /*increase ant num every FAT period 0:+1, 1+2*/
- ODM_SetBBReg(pDM_Odm, 0x8c4 , BIT2|BIT1, 1); /*change cca antenna timming threshold if no CCA occurred: 0:200ms / 1:100ms / 2:no use / 3: 300*/
- ODM_SetBBReg(pDM_Odm, 0x8c4 , BIT0, 1); /*FAT_watchdog_en*/
-
- value32 = ODM_GetMACReg(pDM_Odm, 0x7B4, bMaskDWord);
- ODM_SetMACReg(pDM_Odm, 0x7b4, bMaskDWord, value32|(BIT16|BIT17)); /*Reg7B4[16]=1 enable antenna training */
- /*Reg7B4[17]=1 enable match MAC Addr*/
- ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, 0);/*Match MAC ADDR*/
- ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, 0);
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
-}
-#endif
+ PHYDM_DBG(dm, DBG_ANT_DIV, "***8821A AntDiv_Init => ant_div_type=[ CG_TRX_HW_ANTDIV (DPDT)]\n");
-VOID
-odm_TRX_HWAntDiv_Init_8821A(
- IN PVOID pDM_VOID
- )
-{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821A AntDiv_Init => AntDivType=[ CG_TRX_HW_ANTDIV (DPDT)] \n"));
+ /* Output Pin Settings */
+ odm_set_mac_reg(dm, 0x4C, BIT(25), 0);
- //Output Pin Settings
- ODM_SetMACReg(pDM_Odm, 0x4C , BIT25, 0);
+ odm_set_mac_reg(dm, 0x64, BIT(29), 1); /* PAPE by WLAN control */
+ odm_set_mac_reg(dm, 0x64, BIT(28), 1); /* LNAON by WLAN control */
- ODM_SetMACReg(pDM_Odm, 0x64 , BIT29, 1); //PAPE by WLAN control
- ODM_SetMACReg(pDM_Odm, 0x64 , BIT28, 1); //LNAON by WLAN control
+ odm_set_bb_reg(dm, 0xCB8, BIT(16), 0);
- ODM_SetBBReg(pDM_Odm, 0xCB0 , bMaskDWord, 0x77775745);
- ODM_SetBBReg(pDM_Odm, 0xCB8 , BIT16, 0);
-
- ODM_SetMACReg(pDM_Odm, 0x4C , BIT23, 0); //select DPDT_P and DPDT_N as output pin
- ODM_SetMACReg(pDM_Odm, 0x4C , BIT24, 1); //by WLAN control
- ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF, 8); // DPDT_P = ANTSEL[0]
- ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF0, 8); // DPDT_N = ANTSEL[0]
- ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT29, 0); //DPDT_P non-inverse
- ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT28, 1); //DPDT_N inverse
-
- //Mapping Table
- ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte0, 0);
- ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte1, 1);
-
- //OFDM HW AntDiv Parameters
- ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF, 0xA0); //thershold
- ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF000, 0x10); //bias
-
- //CCK HW AntDiv Parameters
- ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M
- ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples
+ odm_set_mac_reg(dm, 0x4C, BIT(23), 0); /* select DPDT_P and DPDT_N as output pin */
+ odm_set_mac_reg(dm, 0x4C, BIT(24), 1); /* by WLAN control */
+ odm_set_bb_reg(dm, 0xCB4, 0xF, 8); /* DPDT_P = ANTSEL[0] */
+ odm_set_bb_reg(dm, 0xCB4, 0xF0, 8); /* DPDT_N = ANTSEL[0] */
+ odm_set_bb_reg(dm, 0xCB4, BIT(29), 0); /* DPDT_P non-inverse */
+ odm_set_bb_reg(dm, 0xCB4, BIT(28), 1); /* DPDT_N inverse */
- ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //ANTSEL_CCK sent to the smart_antenna circuit
- ODM_SetBBReg(pDM_Odm, 0xA00 , BIT15, 0); //CCK AntDiv function block enable
+ /* Mapping Table */
+ odm_set_bb_reg(dm, 0xCA4, MASKBYTE0, 0);
+ odm_set_bb_reg(dm, 0xCA4, MASKBYTE1, 1);
- //BT Coexistence
- ODM_SetBBReg(pDM_Odm, 0xCAC , BIT9, 1); //keep antsel_map when GNT_BT = 1
- ODM_SetBBReg(pDM_Odm, 0x804 , BIT4, 1); //Disable hw antsw & fast_train.antsw when GNT_BT=1
+ /* OFDM HW AntDiv Parameters */
+ odm_set_bb_reg(dm, 0x8D4, 0x7FF, 0xA0); /* thershold */
+ odm_set_bb_reg(dm, 0x8D4, 0x7FF000, 0x10); /* bias */
- ODM_SetBBReg(pDM_Odm, 0x8CC , BIT20|BIT19|BIT18, 3); //settling time of antdiv by RF LNA = 100ns
+ /* CCK HW AntDiv Parameters */
+ odm_set_bb_reg(dm, 0xA74, BIT(7), 1); /* patch for clk from 88M to 80M */
+ odm_set_bb_reg(dm, 0xA0C, BIT(4), 1); /* do 64 samples */
+
+ odm_set_bb_reg(dm, 0x800, BIT(25), 0); /* ANTSEL_CCK sent to the smart_antenna circuit */
+ odm_set_bb_reg(dm, 0xA00, BIT(15), 0); /* CCK AntDiv function block enable */
+
+ /* BT Coexistence */
+ odm_set_bb_reg(dm, 0xCAC, BIT(9), 1); /* keep antsel_map when GNT_BT = 1 */
+ odm_set_bb_reg(dm, 0x804, BIT(4), 1); /* Disable hw antsw & fast_train.antsw when GNT_BT=1 */
+
+ odm_set_bb_reg(dm, 0x8CC, BIT(20) | BIT(19) | BIT(18), 3); /* settling time of antdiv by RF LNA = 100ns */
+
+ /* response TX ant by RX ant */
+ odm_set_mac_reg(dm, 0x668, BIT(3), 1);
- //response TX ant by RX ant
- ODM_SetMACReg(pDM_Odm, 0x668 , BIT3, 1);
-
}
-VOID
-odm_S0S1_SWAntDiv_Init_8821A(
- IN PVOID pDM_VOID
- )
+void
+odm_s0s1_sw_ant_div_init_8821a(
+ void *dm_void
+)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821A AntDiv_Init => AntDivType=[ S0S1_SW_AntDiv]\n"));
+ PHYDM_DBG(dm, DBG_ANT_DIV, "***8821A AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n");
- //Output Pin Settings
- ODM_SetMACReg(pDM_Odm, 0x4C , BIT25, 0);
+ /* Output Pin Settings */
+ odm_set_mac_reg(dm, 0x4C, BIT(25), 0);
- ODM_SetMACReg(pDM_Odm, 0x64 , BIT29, 1); //PAPE by WLAN control
- ODM_SetMACReg(pDM_Odm, 0x64 , BIT28, 1); //LNAON by WLAN control
+ odm_set_mac_reg(dm, 0x64, BIT(29), 1); /* PAPE by WLAN control */
+ odm_set_mac_reg(dm, 0x64, BIT(28), 1); /* LNAON by WLAN control */
- ODM_SetBBReg(pDM_Odm, 0xCB0 , bMaskDWord, 0x77775745);
- ODM_SetBBReg(pDM_Odm, 0xCB8 , BIT16, 0);
-
- ODM_SetMACReg(pDM_Odm, 0x4C , BIT23, 0); //select DPDT_P and DPDT_N as output pin
- ODM_SetMACReg(pDM_Odm, 0x4C , BIT24, 1); //by WLAN control
- ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF, 8); // DPDT_P = ANTSEL[0]
- ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF0, 8); // DPDT_N = ANTSEL[0]
- ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT29, 0); //DPDT_P non-inverse
- ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT28, 1); //DPDT_N inverse
-
- //Mapping Table
- ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte0, 0);
- ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte1, 1);
-
- //OFDM HW AntDiv Parameters
- ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF, 0xA0); //thershold
- ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF000, 0x10); //bias
-
- //CCK HW AntDiv Parameters
- ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M
- ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples
+ odm_set_bb_reg(dm, 0xCB8, BIT(16), 0);
- ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //ANTSEL_CCK sent to the smart_antenna circuit
- ODM_SetBBReg(pDM_Odm, 0xA00 , BIT15, 0); //CCK AntDiv function block enable
+ odm_set_mac_reg(dm, 0x4C, BIT(23), 0); /* select DPDT_P and DPDT_N as output pin */
+ odm_set_mac_reg(dm, 0x4C, BIT(24), 1); /* by WLAN control */
+ odm_set_bb_reg(dm, 0xCB4, 0xF, 8); /* DPDT_P = ANTSEL[0] */
+ odm_set_bb_reg(dm, 0xCB4, 0xF0, 8); /* DPDT_N = ANTSEL[0] */
+ odm_set_bb_reg(dm, 0xCB4, BIT(29), 0); /* DPDT_P non-inverse */
+ odm_set_bb_reg(dm, 0xCB4, BIT(28), 1); /* DPDT_N inverse */
- //BT Coexistence
- ODM_SetBBReg(pDM_Odm, 0xCAC , BIT9, 1); //keep antsel_map when GNT_BT = 1
- ODM_SetBBReg(pDM_Odm, 0x804 , BIT4, 1); //Disable hw antsw & fast_train.antsw when GNT_BT=1
+ /* Mapping Table */
+ odm_set_bb_reg(dm, 0xCA4, MASKBYTE0, 0);
+ odm_set_bb_reg(dm, 0xCA4, MASKBYTE1, 1);
- ODM_SetBBReg(pDM_Odm, 0x8CC , BIT20|BIT19|BIT18, 3); //settling time of antdiv by RF LNA = 100ns
+ /* OFDM HW AntDiv Parameters */
+ odm_set_bb_reg(dm, 0x8D4, 0x7FF, 0xA0); /* thershold */
+ odm_set_bb_reg(dm, 0x8D4, 0x7FF000, 0x10); /* bias */
- //response TX ant by RX ant
- ODM_SetMACReg(pDM_Odm, 0x668 , BIT3, 1);
+ /* CCK HW AntDiv Parameters */
+ odm_set_bb_reg(dm, 0xA74, BIT(7), 1); /* patch for clk from 88M to 80M */
+ odm_set_bb_reg(dm, 0xA0C, BIT(4), 1); /* do 64 samples */
+ odm_set_bb_reg(dm, 0x800, BIT(25), 0); /* ANTSEL_CCK sent to the smart_antenna circuit */
+ odm_set_bb_reg(dm, 0xA00, BIT(15), 0); /* CCK AntDiv function block enable */
- ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 0);
-
- pDM_SWAT_Table->try_flag = SWAW_STEP_INIT;
- pDM_SWAT_Table->Double_chk_flag = 0;
- pDM_SWAT_Table->CurAntenna = MAIN_ANT;
- pDM_SWAT_Table->PreAntenna = MAIN_ANT;
- pDM_SWAT_Table->SWAS_NoLink_State = 0;
+ /* BT Coexistence */
+ odm_set_bb_reg(dm, 0xCAC, BIT(9), 1); /* keep antsel_map when GNT_BT = 1 */
+ odm_set_bb_reg(dm, 0x804, BIT(4), 1); /* Disable hw antsw & fast_train.antsw when GNT_BT=1 */
+
+ odm_set_bb_reg(dm, 0x8CC, BIT(20) | BIT(19) | BIT(18), 3); /* settling time of antdiv by RF LNA = 100ns */
+
+ /* response TX ant by RX ant */
+ odm_set_mac_reg(dm, 0x668, BIT(3), 1);
+
+
+ odm_set_bb_reg(dm, 0x900, BIT(18), 0);
+
+ dm_swat_table->try_flag = SWAW_STEP_INIT;
+ dm_swat_table->double_chk_flag = 0;
+ dm_swat_table->cur_antenna = MAIN_ANT;
+ dm_swat_table->pre_antenna = MAIN_ANT;
+ dm_swat_table->swas_no_link_state = 0;
}
-#endif //#if (RTL8821A_SUPPORT == 1)
+#endif /* #if (RTL8821A_SUPPORT == 1) */
#if (RTL8821C_SUPPORT == 1)
-VOID
-odm_TRX_HWAntDiv_Init_8821C(
- IN PVOID pDM_VOID
- )
+void
+odm_trx_hw_ant_div_init_8821c(
+ void *dm_void
+)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821C AntDiv_Init => AntDivType=[ CG_TRX_HW_ANTDIV (DPDT)] \n"));
- //Output Pin Settings
- ODM_SetMACReg(pDM_Odm, 0x4C , BIT25, 0);
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
- ODM_SetMACReg(pDM_Odm, 0x64 , BIT29, 1); //PAPE by WLAN control
- ODM_SetMACReg(pDM_Odm, 0x64 , BIT28, 1); //LNAON by WLAN control
+ PHYDM_DBG(dm, DBG_ANT_DIV, "***8821C AntDiv_Init => ant_div_type=[ CG_TRX_HW_ANTDIV (DPDT)]\n");
+ /* Output Pin Settings */
+ odm_set_mac_reg(dm, 0x4C, BIT(25), 0);
- ODM_SetBBReg(pDM_Odm, 0xCB0 , bMaskDWord, 0x77775745);
- ODM_SetBBReg(pDM_Odm, 0xCB8 , BIT16, 0);
-
- ODM_SetMACReg(pDM_Odm, 0x4C , BIT23, 0); //select DPDT_P and DPDT_N as output pin
- ODM_SetMACReg(pDM_Odm, 0x4C , BIT24, 1); //by WLAN control
- ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF, 8); // DPDT_P = ANTSEL[0]
- ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF0, 8); // DPDT_N = ANTSEL[0]
- ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT29, 0); //DPDT_P non-inverse
- ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT28, 1); //DPDT_N inverse
-
- //Mapping Table
- ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte0, 0);
- ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte1, 1);
-
- //OFDM HW AntDiv Parameters
- ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF, 0xA0); //thershold
- ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF000, 0x10); //bias
-
- //CCK HW AntDiv Parameters
- ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M
- ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples
+ odm_set_mac_reg(dm, 0x64, BIT(29), 1); /* PAPE by WLAN control */
+ odm_set_mac_reg(dm, 0x64, BIT(28), 1); /* LNAON by WLAN control */
- ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //ANTSEL_CCK sent to the smart_antenna circuit
- ODM_SetBBReg(pDM_Odm, 0xA00 , BIT15, 0); //CCK AntDiv function block enable
+ odm_set_bb_reg(dm, 0xCB8, BIT(16), 0);
- //BT Coexistence
- ODM_SetBBReg(pDM_Odm, 0xCAC , BIT9, 1); //keep antsel_map when GNT_BT = 1
- ODM_SetBBReg(pDM_Odm, 0x804 , BIT4, 1); //Disable hw antsw & fast_train.antsw when GNT_BT=1
+ odm_set_mac_reg(dm, 0x4C, BIT(23), 0); /* select DPDT_P and DPDT_N as output pin */
+ odm_set_mac_reg(dm, 0x4C, BIT(24), 1); /* by WLAN control */
+ odm_set_bb_reg(dm, 0xCB4, 0xF, 8); /* DPDT_P = ANTSEL[0] */
+ odm_set_bb_reg(dm, 0xCB4, 0xF0, 8); /* DPDT_N = ANTSEL[0] */
+ odm_set_bb_reg(dm, 0xCB4, BIT(29), 0); /* DPDT_P non-inverse */
+ odm_set_bb_reg(dm, 0xCB4, BIT(28), 1); /* DPDT_N inverse */
- //Timming issue
- ODM_SetBBReg(pDM_Odm, 0x818 , BIT23|BIT22|BIT21|BIT20, 8); /*keep antidx after tx for ACK ( unit x 3.2 mu sec)*/
- ODM_SetBBReg(pDM_Odm, 0x8CC , BIT20|BIT19|BIT18, 3); //settling time of antdiv by RF LNA = 100ns
+ /* Mapping Table */
+ odm_set_bb_reg(dm, 0xCA4, MASKBYTE0, 0);
+ odm_set_bb_reg(dm, 0xCA4, MASKBYTE1, 1);
- //response TX ant by RX ant
- ODM_SetMACReg(pDM_Odm, 0x668 , BIT3, 1);
-
-}
-#endif //#if (RTL8821C_SUPPORT == 1)
+ /* OFDM HW AntDiv Parameters */
+ odm_set_bb_reg(dm, 0x8D4, 0x7FF, 0xA0); /* thershold */
+ odm_set_bb_reg(dm, 0x8D4, 0x7FF000, 0x10); /* bias */
+ /* CCK HW AntDiv Parameters */
+ odm_set_bb_reg(dm, 0xA74, BIT(7), 1); /* patch for clk from 88M to 80M */
+ odm_set_bb_reg(dm, 0xA0C, BIT(4), 1); /* do 64 samples */
-#if (RTL8881A_SUPPORT == 1)
-VOID
-odm_TRX_HWAntDiv_Init_8881A(
- IN PVOID pDM_VOID
- )
-{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8881A AntDiv_Init => AntDivType=[ CG_TRX_HW_ANTDIV (SPDT)] \n"));
-
- //Output Pin Settings
- // [SPDT related]
- ODM_SetMACReg(pDM_Odm, 0x4C , BIT25, 0);
- ODM_SetMACReg(pDM_Odm, 0x4C , BIT26, 0);
- ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT31, 0); //delay buffer
- ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT22, 0);
- ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT24, 1);
- ODM_SetBBReg(pDM_Odm, 0xCB0 , 0xF00, 8); // DPDT_P = ANTSEL[0]
- ODM_SetBBReg(pDM_Odm, 0xCB0 , 0xF0000, 8); // DPDT_N = ANTSEL[0]
-
- //Mapping Table
- ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte0, 0);
- ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte1, 1);
-
- //OFDM HW AntDiv Parameters
- ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF, 0xA0); //thershold
- ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF000, 0x0); //bias
- ODM_SetBBReg(pDM_Odm, 0x8CC , BIT20|BIT19|BIT18, 3); //settling time of antdiv by RF LNA = 100ns
-
- //CCK HW AntDiv Parameters
- ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M
- ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples
+ odm_set_bb_reg(dm, 0x800, BIT(25), 0); /* ANTSEL_CCK sent to the smart_antenna circuit */
+ odm_set_bb_reg(dm, 0xA00, BIT(15), 0); /* CCK AntDiv function block enable */
- //2 [--For HW Bug Setting]
+ /* BT Coexistence */
+ odm_set_bb_reg(dm, 0xCAC, BIT(9), 1); /* keep antsel_map when GNT_BT = 1 */
+ odm_set_bb_reg(dm, 0x804, BIT(4), 1); /* Disable hw antsw & fast_train.antsw when GNT_BT=1 */
- ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 0); //TX Ant by Reg // A-cut bug
-}
+ /* Timming issue */
+ odm_set_bb_reg(dm, 0x818, BIT(23) | BIT(22) | BIT(21) | BIT(20), 0); /*keep antidx after tx for ACK ( unit x 3.2 mu sec)*/
+ odm_set_bb_reg(dm, 0x8CC, BIT(20) | BIT(19) | BIT(18), 3); /* settling time of antdiv by RF LNA = 100ns */
-#endif //#if (RTL8881A_SUPPORT == 1)
+ /* response TX ant by RX ant */
+ odm_set_mac_reg(dm, 0x668, BIT(3), 1);
+}
-#if (RTL8812A_SUPPORT == 1)
-VOID
-odm_TRX_HWAntDiv_Init_8812A(
- IN PVOID pDM_VOID
- )
+void
+phydm_s0s1_sw_ant_div_init_8821c(
+ void *dm_void
+)
{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8812A AntDiv_Init => AntDivType=[ CG_TRX_HW_ANTDIV (SPDT)] \n"));
-
- //3 //3 --RFE pin setting---------
- //[BB]
- ODM_SetBBReg(pDM_Odm, 0x900 , BIT10|BIT9|BIT8, 0x0); //disable SW switch
- ODM_SetBBReg(pDM_Odm, 0x900 , BIT17|BIT16, 0x0);
- ODM_SetBBReg(pDM_Odm, 0x974 , BIT7|BIT6, 0x3); // in/out
- ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT31, 0); //delay buffer
- ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT26, 0);
- ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT27, 1);
- ODM_SetBBReg(pDM_Odm, 0xCB0 , 0xF000000, 8); // DPDT_P = ANTSEL[0]
- ODM_SetBBReg(pDM_Odm, 0xCB0 , 0xF0000000, 8); // DPDT_N = ANTSEL[0]
- //3 -------------------------
-
- //Mapping Table
- ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte0, 0);
- ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte1, 1);
-
- //OFDM HW AntDiv Parameters
- ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF, 0xA0); //thershold
- ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF000, 0x0); //bias
- ODM_SetBBReg(pDM_Odm, 0x8CC , BIT20|BIT19|BIT18, 3); //settling time of antdiv by RF LNA = 100ns
-
- //CCK HW AntDiv Parameters
- ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M
- ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
- //2 [--For HW Bug Setting]
+ PHYDM_DBG(dm, DBG_ANT_DIV, "***8821C AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n");
- ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 0); //TX Ant by Reg // A-cut bug
-
-}
+ /* Output Pin Settings */
+ odm_set_mac_reg(dm, 0x4C, BIT(25), 0);
-#endif //#if (RTL8812A_SUPPORT == 1)
+ odm_set_mac_reg(dm, 0x64, BIT(29), 1); /* PAPE by WLAN control */
+ odm_set_mac_reg(dm, 0x64, BIT(28), 1); /* LNAON by WLAN control */
-#if (RTL8188F_SUPPORT == 1)
-VOID
-odm_S0S1_SWAntDiv_Init_8188F(
- IN PVOID pDM_VOID
-)
-{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
- pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
+ odm_set_bb_reg(dm, 0xCB8, BIT(16), 0);
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188F AntDiv_Init => AntDivType=[ S0S1_SW_AntDiv]\n"));
+ odm_set_mac_reg(dm, 0x4C, BIT(23), 0); /* select DPDT_P and DPDT_N as output pin */
+ odm_set_mac_reg(dm, 0x4C, BIT(24), 1); /* by WLAN control */
+ odm_set_bb_reg(dm, 0xCB4, 0xF, 8); /* DPDT_P = ANTSEL[0] */
+ odm_set_bb_reg(dm, 0xCB4, 0xF0, 8); /* DPDT_N = ANTSEL[0] */
+ odm_set_bb_reg(dm, 0xCB4, BIT(29), 0); /* DPDT_P non-inverse */
+ odm_set_bb_reg(dm, 0xCB4, BIT(28), 1); /* DPDT_N inverse */
+ /* Mapping Table */
+ odm_set_bb_reg(dm, 0xCA4, MASKBYTE0, 0);
+ odm_set_bb_reg(dm, 0xCA4, MASKBYTE1, 1);
- /*GPIO Setting*/
- /*ODM_SetMACReg(pDM_Odm, 0x64 , BIT18, 0); */
- /*ODM_SetMACReg(pDM_Odm, 0x44 , BIT28|BIT27, 0);*/
- ODM_SetMACReg(pDM_Odm, 0x44 , BIT20|BIT19, 0x3); /*enable_output for P_GPIO[4:3]*/
- /*ODM_SetMACReg(pDM_Odm, 0x44 , BIT12|BIT11, 0);*/ /*output value*/
- /*ODM_SetMACReg(pDM_Odm, 0x40 , BIT1|BIT0, 0);*/ /*GPIO function*/
+ /* OFDM HW AntDiv Parameters */
+ odm_set_bb_reg(dm, 0x8D4, 0x7FF, 0xA0); /* thershold */
+ odm_set_bb_reg(dm, 0x8D4, 0x7FF000, 0x00); /* bias */
- pDM_FatTable->bBecomeLinked = FALSE;
- pDM_SWAT_Table->try_flag = SWAW_STEP_INIT;
- pDM_SWAT_Table->Double_chk_flag = 0;
-}
+ /* CCK HW AntDiv Parameters */
+ odm_set_bb_reg(dm, 0xA74, BIT(7), 1); /* patch for clk from 88M to 80M */
+ odm_set_bb_reg(dm, 0xA0C, BIT(4), 1); /* do 64 samples */
-VOID
-phydm_update_rx_idle_antenna_8188F(
- IN PVOID pDM_VOID,
- IN u4Byte default_ant
-)
-{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- u1Byte codeword;
+ odm_set_bb_reg(dm, 0x800, BIT(25), 0); /* ANTSEL_CCK sent to the smart_antenna circuit */
+ odm_set_bb_reg(dm, 0xA00, BIT(15), 0); /* CCK AntDiv function block enable */
- if (default_ant == ANT1_2G)
- codeword = 1; /*2'b01*/
- else
- codeword = 2;/*2'b10*/
-
- ODM_SetMACReg(pDM_Odm, 0x44 , (BIT12|BIT11), codeword); /*GPIO[4:3] output value*/
-}
+ /* BT Coexistence */
+ odm_set_bb_reg(dm, 0xCAC, BIT(9), 1); /* keep antsel_map when GNT_BT = 1 */
+ odm_set_bb_reg(dm, 0x804, BIT(4), 1); /* Disable hw antsw & fast_train.antsw when GNT_BT=1 */
-#endif
+ odm_set_bb_reg(dm, 0x8CC, BIT(20) | BIT(19) | BIT(18), 3); /* settling time of antdiv by RF LNA = 100ns */
+ /* response TX ant by RX ant */
+ odm_set_mac_reg(dm, 0x668, BIT(3), 1);
-#ifdef ODM_EVM_ENHANCE_ANTDIV
+ odm_set_bb_reg(dm, 0x900, BIT(18), 0);
+
+ dm_swat_table->try_flag = SWAW_STEP_INIT;
+ dm_swat_table->double_chk_flag = 0;
+ dm_swat_table->cur_antenna = MAIN_ANT;
+ dm_swat_table->pre_antenna = MAIN_ANT;
+ dm_swat_table->swas_no_link_state = 0;
-VOID
-odm_EVM_FastAnt_Reset(
- IN PVOID pDM_VOID
- )
-{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
-
- pDM_FatTable->EVM_method_enable=0;
- odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON);
- pDM_FatTable->FAT_State = NORMAL_STATE_MIAN;
- pDM_Odm->antdiv_period=0;
- ODM_SetMACReg(pDM_Odm, 0x608, BIT8, 0);
}
+#endif /* #if (RTL8821C_SUPPORT == 1) */
-VOID
-odm_EVM_Enhance_AntDiv(
- IN PVOID pDM_VOID
- )
-{
- PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
- u4Byte Main_RSSI, Aux_RSSI ;
- u4Byte Main_CRC_utility=0,Aux_CRC_utility=0,utility_ratio=1;
- u4Byte Main_EVM, Aux_EVM,Diff_RSSI=0,diff_EVM=0;
- u1Byte score_EVM=0,score_CRC=0;
- u1Byte rssi_larger_ant = 0;
- pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
- u4Byte value32, i;
- BOOLEAN Main_above1=FALSE,Aux_above1=FALSE;
- BOOLEAN Force_antenna=FALSE;
- PSTA_INFO_T pEntry;
- pDM_FatTable->TargetAnt_enhance=0xFF;
-
+#if (RTL8881A_SUPPORT == 1)
+void
+odm_trx_hw_ant_div_init_8881a(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+ PHYDM_DBG(dm, DBG_ANT_DIV, "***8881A AntDiv_Init => ant_div_type=[ CG_TRX_HW_ANTDIV (SPDT)]\n");
+
+ /* Output Pin Settings */
+ /* [SPDT related] */
+ odm_set_mac_reg(dm, 0x4C, BIT(25), 0);
+ odm_set_mac_reg(dm, 0x4C, BIT(26), 0);
+ odm_set_bb_reg(dm, 0xCB4, BIT(31), 0); /* delay buffer */
+ odm_set_bb_reg(dm, 0xCB4, BIT(22), 0);
+ odm_set_bb_reg(dm, 0xCB4, BIT(24), 1);
+ odm_set_bb_reg(dm, 0xCB0, 0xF00, 8); /* DPDT_P = ANTSEL[0] */
+ odm_set_bb_reg(dm, 0xCB0, 0xF0000, 8); /* DPDT_N = ANTSEL[0] */
+
+ /* Mapping Table */
+ odm_set_bb_reg(dm, 0xCA4, MASKBYTE0, 0);
+ odm_set_bb_reg(dm, 0xCA4, MASKBYTE1, 1);
+
+ /* OFDM HW AntDiv Parameters */
+ odm_set_bb_reg(dm, 0x8D4, 0x7FF, 0xA0); /* thershold */
+ odm_set_bb_reg(dm, 0x8D4, 0x7FF000, 0x0); /* bias */
+ odm_set_bb_reg(dm, 0x8CC, BIT(20) | BIT(19) | BIT(18), 3); /* settling time of antdiv by RF LNA = 100ns */
+
+ /* CCK HW AntDiv Parameters */
+ odm_set_bb_reg(dm, 0xA74, BIT(7), 1); /* patch for clk from 88M to 80M */
+ odm_set_bb_reg(dm, 0xA0C, BIT(4), 1); /* do 64 samples */
+
+ /* 2 [--For HW Bug setting] */
+
+ odm_set_bb_reg(dm, 0x900, BIT(18), 0); /* TX ant by Reg */ /* A-cut bug */
+}
+
+#endif /* #if (RTL8881A_SUPPORT == 1) */
+
+
+#if (RTL8812A_SUPPORT == 1)
+void
+odm_trx_hw_ant_div_init_8812a(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+
+ PHYDM_DBG(dm, DBG_ANT_DIV, "***8812A AntDiv_Init => ant_div_type=[ CG_TRX_HW_ANTDIV (SPDT)]\n");
+
+ /* 3 */ /* 3 --RFE pin setting--------- */
+ /* [BB] */
+ odm_set_bb_reg(dm, 0x900, BIT(10) | BIT(9) | BIT(8), 0x0); /* disable SW switch */
+ odm_set_bb_reg(dm, 0x900, BIT(17) | BIT(16), 0x0);
+ odm_set_bb_reg(dm, 0x974, BIT(7) | BIT(6), 0x3); /* in/out */
+ odm_set_bb_reg(dm, 0xCB4, BIT(31), 0); /* delay buffer */
+ odm_set_bb_reg(dm, 0xCB4, BIT(26), 0);
+ odm_set_bb_reg(dm, 0xCB4, BIT(27), 1);
+ odm_set_bb_reg(dm, 0xCB0, 0xF000000, 8); /* DPDT_P = ANTSEL[0] */
+ odm_set_bb_reg(dm, 0xCB0, 0xF0000000, 8); /* DPDT_N = ANTSEL[0] */
+ /* 3 ------------------------- */
+
+ /* Mapping Table */
+ odm_set_bb_reg(dm, 0xCA4, MASKBYTE0, 0);
+ odm_set_bb_reg(dm, 0xCA4, MASKBYTE1, 1);
+
+ /* OFDM HW AntDiv Parameters */
+ odm_set_bb_reg(dm, 0x8D4, 0x7FF, 0xA0); /* thershold */
+ odm_set_bb_reg(dm, 0x8D4, 0x7FF000, 0x0); /* bias */
+ odm_set_bb_reg(dm, 0x8CC, BIT(20) | BIT(19) | BIT(18), 3); /* settling time of antdiv by RF LNA = 100ns */
+
+ /* CCK HW AntDiv Parameters */
+ odm_set_bb_reg(dm, 0xA74, BIT(7), 1); /* patch for clk from 88M to 80M */
+ odm_set_bb_reg(dm, 0xA0C, BIT(4), 1); /* do 64 samples */
+
+ /* 2 [--For HW Bug setting] */
+
+ odm_set_bb_reg(dm, 0x900, BIT(18), 0); /* TX ant by Reg */ /* A-cut bug */
+
+}
+
+#endif /* #if (RTL8812A_SUPPORT == 1) */
+
+#if (RTL8188F_SUPPORT == 1)
+void
+odm_s0s1_sw_ant_div_init_8188f(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
+ struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+
+ PHYDM_DBG(dm, DBG_ANT_DIV, "***8188F AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n");
+
+
+ /*GPIO setting*/
+ /*odm_set_mac_reg(dm, 0x64, BIT(18), 0); */
+ /*odm_set_mac_reg(dm, 0x44, BIT(28)|BIT(27), 0);*/
+ /*odm_set_mac_reg(dm, 0x44, BIT(20) | BIT(19), 0x3);*/ /*enable_output for P_GPIO[4:3]*/
+ /*odm_set_mac_reg(dm, 0x44, BIT(12)|BIT(11), 0);*/ /*output value*/
+ /*odm_set_mac_reg(dm, 0x40, BIT(1)|BIT(0), 0);*/ /*GPIO function*/
+
+ if (dm->support_ic_type == ODM_RTL8188F) {
+ if (dm->support_interface == ODM_ITRF_USB)
+ odm_set_mac_reg(dm, 0x44, BIT(20) | BIT(19), 0x3); /*enable_output for P_GPIO[4:3]*/
+ else if (dm->support_interface == ODM_ITRF_SDIO)
+ odm_set_mac_reg(dm, 0x44, BIT(18), 0x1); /*enable_output for P_GPIO[2]*/
+ }
- if((pDM_Odm->SupportICType & ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC))
- {
- if(pDM_Odm->bOneEntryOnly)
- {
- //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[One Client only] \n"));
- i = pDM_Odm->OneEntry_MACID;
+ fat_tab->is_become_linked = false;
+ dm_swat_table->try_flag = SWAW_STEP_INIT;
+ dm_swat_table->double_chk_flag = 0;
+}
- Main_RSSI = (pDM_FatTable->MainAnt_Cnt[i]!=0)?(pDM_FatTable->MainAnt_Sum[i]/pDM_FatTable->MainAnt_Cnt[i]):0;
- Aux_RSSI = (pDM_FatTable->AuxAnt_Cnt[i]!=0)?(pDM_FatTable->AuxAnt_Sum[i]/pDM_FatTable->AuxAnt_Cnt[i]):0;
+void
+phydm_update_rx_idle_antenna_8188F(
+ void *dm_void,
+ u32 default_ant
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ u8 codeword;
- if((Main_RSSI==0 && Aux_RSSI !=0 && Aux_RSSI>=FORCE_RSSI_DIFF) || (Main_RSSI!=0 && Aux_RSSI==0 && Main_RSSI>=FORCE_RSSI_DIFF))
- {
- Diff_RSSI=FORCE_RSSI_DIFF;
- }
- else if(Main_RSSI!=0 && Aux_RSSI !=0)
- {
- Diff_RSSI = (Main_RSSI>=Aux_RSSI)?(Main_RSSI-Aux_RSSI):(Aux_RSSI-Main_RSSI);
+ if (dm->support_ic_type == ODM_RTL8188F) {
+ if (dm->support_interface == ODM_ITRF_USB) {
+ if (default_ant == ANT1_2G)
+ codeword = 1; /*2'b01*/
+ else
+ codeword = 2;/*2'b10*/
+ odm_set_mac_reg(dm, 0x44, (BIT(12) | BIT(11)), codeword); /*GPIO[4:3] output value*/
+ } else if (dm->support_interface == ODM_ITRF_SDIO) {
+ if (default_ant == ANT1_2G) {
+ codeword = 0; /*1'b0*/
+ odm_set_bb_reg(dm, 0x870, BIT(9)|BIT(8), 0x3);
+ odm_set_bb_reg(dm, 0x860, BIT(9)|BIT(8), 0x1);
+ } else {
+ codeword = 1;/*1'b1*/
+ odm_set_bb_reg(dm, 0x870, BIT(9)|BIT(8), 0x3);
+ odm_set_bb_reg(dm, 0x860, BIT(9)|BIT(8), 0x2);
}
-
- if (Main_RSSI >= Aux_RSSI)
+ odm_set_mac_reg(dm, 0x44, BIT(10), codeword); /*GPIO[2] output value*/
+ }
+ }
+}
+#endif
+
+
+
+#ifdef ODM_EVM_ENHANCE_ANTDIV
+void
+phydm_evm_sw_antdiv_init(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+
+ /*EVM enhance AntDiv method init----------------------------------------------------------------------*/
+ fat_tab->evm_method_enable = 0;
+ fat_tab->fat_state = NORMAL_STATE_MIAN;
+ fat_tab->fat_state_cnt = 0;
+ fat_tab->pre_antdiv_rssi = 0;
+
+ dm->antdiv_intvl = 30;
+ dm->antdiv_train_num = 2;
+ odm_set_bb_reg(dm, 0x910, 0x3f, 0xf);
+ dm->antdiv_evm_en = 1;
+ /*dm->antdiv_period=1;*/
+ dm->evm_antdiv_period = 3;
+ dm->stop_antdiv_rssi_th = 3;
+ dm->stop_antdiv_tp_th = 80;
+ dm->antdiv_tp_period = 3;
+ dm->stop_antdiv_tp_diff_th = 5;
+}
+
+void
+odm_evm_fast_ant_reset(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+
+ fat_tab->evm_method_enable = 0;
+ odm_ant_div_on_off(dm, ANTDIV_ON);
+ fat_tab->fat_state = NORMAL_STATE_MIAN;
+ fat_tab->fat_state_cnt = 0;
+ dm->antdiv_period = 0;
+ odm_set_mac_reg(dm, 0x608, BIT(8), 0);
+}
+
+
+void
+odm_evm_enhance_ant_div(
+ void *dm_void
+)
+{
+ struct dm_struct *dm = (struct dm_struct *)dm_void;
+ u32 main_rssi, aux_rssi ;
+ u32 main_crc_utility = 0, aux_crc_utility = 0, utility_ratio = 1;
+ u32 main_evm, aux_evm, diff_rssi = 0, diff_EVM = 0;
+ u32 main_2ss_evm[2], aux_2ss_evm[2];
+ u32 main_1ss_evm, aux_1ss_evm;
+ u32 main_2ss_evm_sum, aux_2ss_evm_sum;
+ u8 score_EVM = 0, score_CRC = 0;
+ u8 rssi_larger_ant = 0;
+ struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
+ u32 value32, i;
+ boolean main_above1 = false, aux_above1 = false;
+ boolean force_antenna = false;
+ struct cmn_sta_info *sta;
+ u32 antdiv_tp_main_avg, antdiv_tp_aux_avg;
+ u8 curr_rssi, rssi_diff;
+ u32 tp_diff;
+ u8 tp_diff_return = 0, tp_return = 0, rssi_return = 0;
+ u8 target_ant_evm_1ss, target_ant_evm_2ss;
+ u8 decision_evm_ss;
+ u8 next_ant;
+
+ fat_tab->target_ant_enhance = 0xFF;
+
+ if ((dm->support_ic_type & ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC)) {
+ if (dm->is_one_entry_only) {
+ /* PHYDM_DBG(dm,DBG_ANT_DIV, "[One Client only]\n"); */
+ i = dm->one_entry_macid;
+ sta = dm->phydm_sta_info[i];
+
+ main_rssi = (fat_tab->main_ant_cnt[i] != 0) ? (fat_tab->main_ant_sum[i] / fat_tab->main_ant_cnt[i]) : 0;
+ aux_rssi = (fat_tab->aux_ant_cnt[i] != 0) ? (fat_tab->aux_ant_sum[i] / fat_tab->aux_ant_cnt[i]) : 0;
+
+ if ((main_rssi == 0 && aux_rssi != 0 && aux_rssi >= FORCE_RSSI_DIFF) || (main_rssi != 0 && aux_rssi == 0 && main_rssi >= FORCE_RSSI_DIFF))
+ diff_rssi = FORCE_RSSI_DIFF;
+ else if (main_rssi != 0 && aux_rssi != 0)
+ diff_rssi = (main_rssi >= aux_rssi) ? (main_rssi - aux_rssi) : (aux_rssi - main_rssi);
+
+ if (main_rssi >= aux_rssi)
rssi_larger_ant = MAIN_ANT;
else
rssi_larger_ant = AUX_ANT;
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" Main_Cnt = (( %d )) , Main_RSSI= (( %d ))\n", pDM_FatTable->MainAnt_Cnt[i], Main_RSSI));
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" Aux_Cnt = (( %d )) , Aux_RSSI = (( %d ))\n", pDM_FatTable->AuxAnt_Cnt[i], Aux_RSSI));
-
- if( ((Main_RSSI>=Evm_RSSI_TH_High||Aux_RSSI>=Evm_RSSI_TH_High )|| (pDM_FatTable->EVM_method_enable==1) )
- //&& (Diff_RSSI <= FORCE_RSSI_DIFF + 1)
- )
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[> TH_H || EVM_method_enable==1] && "));
-
- if(((Main_RSSI>=Evm_RSSI_TH_Low)||(Aux_RSSI>=Evm_RSSI_TH_Low) ))
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[> TH_L ] \n"));
-
- //2 [ Normal state Main]
- if(pDM_FatTable->FAT_State == NORMAL_STATE_MIAN)
- {
-
- pDM_FatTable->EVM_method_enable=1;
- odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);
- pDM_Odm->antdiv_period = pDM_Odm->evm_antdiv_period;
-
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ start training: MIAN] \n"));
- pDM_FatTable->MainAntEVM_Sum[i] = 0;
- pDM_FatTable->AuxAntEVM_Sum[i] = 0;
- pDM_FatTable->MainAntEVM_Cnt[i] = 0;
- pDM_FatTable->AuxAntEVM_Cnt[i] = 0;
-
- pDM_FatTable->FAT_State = NORMAL_STATE_AUX;
- ODM_SetMACReg(pDM_Odm, 0x608, BIT8, 1); //Accept CRC32 Error packets.
- ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);
-
- pDM_FatTable->CRC32_Ok_Cnt=0;
- pDM_FatTable->CRC32_Fail_Cnt=0;
- ODM_SetTimer(pDM_Odm,&pDM_Odm->EVM_FastAntTrainingTimer, pDM_Odm->antdiv_intvl ); //m
- }
- //2 [ Normal state Aux ]
- else if(pDM_FatTable->FAT_State == NORMAL_STATE_AUX)
- {
- pDM_FatTable->MainCRC32_Ok_Cnt=pDM_FatTable->CRC32_Ok_Cnt;
- pDM_FatTable->MainCRC32_Fail_Cnt=pDM_FatTable->CRC32_Fail_Cnt;
-
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ start training: AUX] \n"));
- pDM_FatTable->FAT_State = TRAINING_STATE;
- ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT);
-
- pDM_FatTable->CRC32_Ok_Cnt=0;
- pDM_FatTable->CRC32_Fail_Cnt=0;
- ODM_SetTimer(pDM_Odm,&pDM_Odm->EVM_FastAntTrainingTimer, pDM_Odm->antdiv_intvl ); //ms
- }
- else if(pDM_FatTable->FAT_State == TRAINING_STATE)
- {
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Training state ] \n"));
- pDM_FatTable->FAT_State = NORMAL_STATE_MIAN;
-
- //3 [CRC32 statistic]
- pDM_FatTable->AuxCRC32_Ok_Cnt=pDM_FatTable->CRC32_Ok_Cnt;
- pDM_FatTable->AuxCRC32_Fail_Cnt=pDM_FatTable->CRC32_Fail_Cnt;
-
- if ((pDM_FatTable->MainCRC32_Ok_Cnt > ((pDM_FatTable->AuxCRC32_Ok_Cnt)<<1)) || ((Diff_RSSI >= 20) && (rssi_larger_ant == MAIN_ANT))) {
- pDM_FatTable->TargetAnt_CRC32=MAIN_ANT;
- Force_antenna=TRUE;
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("CRC32 Force Main\n"));
- } else if ((pDM_FatTable->AuxCRC32_Ok_Cnt > ((pDM_FatTable->MainCRC32_Ok_Cnt)<<1)) || ((Diff_RSSI >= 20) && (rssi_larger_ant == AUX_ANT))) {
- pDM_FatTable->TargetAnt_CRC32=AUX_ANT;
- Force_antenna=TRUE;
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("CRC32 Force Aux\n"));
+ PHYDM_DBG(dm, DBG_ANT_DIV, "Main_Cnt=(( %d )), main_rssi=(( %d ))\n", fat_tab->main_ant_cnt[i], main_rssi);
+ PHYDM_DBG(dm, DBG_ANT_DIV, "Aux_Cnt=(( %d )), aux_rssi=(( %d ))\n", fat_tab->aux_ant_cnt[i], aux_rssi);
+
+ if (((main_rssi >= evm_rssi_th_high || aux_rssi >= evm_rssi_th_high) || (fat_tab->evm_method_enable == 1))
+ /* && (diff_rssi <= FORCE_RSSI_DIFF + 1) */
+ ) {
+ PHYDM_DBG(dm, DBG_ANT_DIV, "> TH_H || evm_method_enable==1\n");
+
+ if (((main_rssi >= evm_rssi_th_low) || (aux_rssi >= evm_rssi_th_low))) {
+ PHYDM_DBG(dm, DBG_ANT_DIV, "> TH_L, fat_state_cnt =((%d))\n", fat_tab->fat_state_cnt);
+
+ /*Traning state: 0(alt) 1(ori) 2(alt) 3(ori)============================================================*/
+ if (fat_tab->fat_state_cnt < ((dm->antdiv_train_num)<<1)) {
+ if (fat_tab->fat_state_cnt == 0) {
+ /*Reset EVM 1SS Method */
+ fat_tab->main_ant_evm_sum[i] = 0;
+ fat_tab->aux_ant_evm_sum[i] = 0;
+ fat_tab->main_ant_evm_cnt[i] = 0;
+ fat_tab->aux_ant_evm_cnt[i] = 0;
+ /*Reset EVM 2SS Method */
+ fat_tab->main_ant_evm_2ss_sum[i][0] = 0;
+ fat_tab->main_ant_evm_2ss_sum[i][1] = 0;
+ fat_tab->aux_ant_evm_2ss_sum[i][0] = 0;
+ fat_tab->aux_ant_evm_2ss_sum[i][1] = 0;
+ fat_tab->main_ant_evm_2ss_cnt[i] = 0;
+ fat_tab->aux_ant_evm_2ss_cnt[i] = 0;
+ #if 0
+ /*Reset TP Method */
+ fat_tab->antdiv_tp_main = 0;
+ fat_tab->antdiv_tp_aux = 0;
+ fat_tab->antdiv_tp_main_cnt = 0;
+ fat_tab->antdiv_tp_aux_cnt = 0;
+ #endif
+ /*Reset CRC Method */
+ fat_tab->main_crc32_ok_cnt = 0;
+ fat_tab->main_crc32_fail_cnt = 0;
+ fat_tab->aux_crc32_ok_cnt = 0;
+ fat_tab->aux_crc32_fail_cnt = 0;
+
+ #ifdef SKIP_EVM_ANTDIV_TRAINING_PATCH
+ if ((*dm->band_width == CHANNEL_WIDTH_20) && (sta->mimo_type == RF_2T2R)) {
+ /*1. Skip training: RSSI*/
+ /*PHYDM_DBG(pDM_Odm,DBG_ANT_DIV, "TargetAnt_enhance=((%d)), RxIdleAnt=((%d))\n", pDM_FatTable->TargetAnt_enhance, pDM_FatTable->RxIdleAnt);*/
+ curr_rssi = (u8)((fat_tab->rx_idle_ant == MAIN_ANT) ? main_rssi : aux_rssi);
+ rssi_diff = (curr_rssi > fat_tab->pre_antdiv_rssi) ? (curr_rssi - fat_tab->pre_antdiv_rssi) : (fat_tab->pre_antdiv_rssi - curr_rssi);
+
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[1] rssi_return, curr_rssi=((%d)), pre_rssi=((%d))\n", curr_rssi, fat_tab->pre_antdiv_rssi);
+
+ fat_tab->pre_antdiv_rssi = curr_rssi;
+ if ((rssi_diff < (dm->stop_antdiv_rssi_th)) && (curr_rssi != 0))
+ rssi_return = 1;
+
+ /*2. Skip training: TP Diff*/
+ tp_diff = (dm->rx_tp > fat_tab->pre_antdiv_tp) ? (dm->rx_tp - fat_tab->pre_antdiv_tp) : (fat_tab->pre_antdiv_tp - dm->rx_tp);
+
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[2] tp_diff_return, curr_tp=((%d)), pre_tp=((%d))\n", dm->rx_tp, fat_tab->pre_antdiv_tp);
+ fat_tab->pre_antdiv_tp = dm->rx_tp;
+ if ((tp_diff < (u32)(dm->stop_antdiv_tp_diff_th) && (dm->rx_tp != 0)))
+ tp_diff_return = 1;
+
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[3] tp_return, curr_rx_tp=((%d))\n", dm->rx_tp);
+ /*3. Skip training: TP*/
+ if (dm->rx_tp >= (u32)(dm->stop_antdiv_tp_th))
+ tp_return = 1;
+
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[4] Return {rssi, tp_diff, tp} = {%d, %d, %d}\n", rssi_return, tp_diff_return, tp_return);
+ /*4. Joint Return Decision*/
+ if (tp_return) {
+ if (tp_diff_return || rssi_diff) {
+ PHYDM_DBG(dm, DBG_ANT_DIV, "***Return EVM SW AntDiv\n");
+ return;
+ }
+ }
+ }
+ #endif
+
+ fat_tab->evm_method_enable = 1;
+ odm_ant_div_on_off(dm, ANTDIV_OFF);
+ dm->antdiv_period = dm->evm_antdiv_period;
+ odm_set_mac_reg(dm, 0x608, BIT(8), 1); /*RCR accepts CRC32-Error packets*/
+
}
- else
+
+
+ fat_tab->fat_state_cnt++;
+ next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;
+ odm_update_rx_idle_ant(dm, next_ant);
+ odm_set_timer(dm, &dm->evm_fast_ant_training_timer, dm->antdiv_intvl); //ms
+
+ }
+ /*Decision state: 4==============================================================*/
+ else {
+ fat_tab->fat_state_cnt = 0;
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[Decisoin state ]\n");
+
+ /* 3 [CRC32 statistic] */
+ #if 0
+ if ((fat_tab->main_crc32_ok_cnt > ((fat_tab->aux_crc32_ok_cnt) << 1)) || ((diff_rssi >= 40) && (rssi_larger_ant == MAIN_ANT))) {
+ fat_tab->target_ant_crc32 = MAIN_ANT;
+ force_antenna = true;
+ PHYDM_DBG(dm, DBG_ANT_DIV, "CRC32 Force Main\n");
+ } else if ((fat_tab->aux_crc32_ok_cnt > ((fat_tab->main_crc32_ok_cnt) << 1)) || ((diff_rssi >= 40) && (rssi_larger_ant == AUX_ANT))) {
+ fat_tab->target_ant_crc32 = AUX_ANT;
+ force_antenna = true;
+ PHYDM_DBG(dm, DBG_ANT_DIV, "CRC32 Force Aux\n");
+ } else
+ #endif
{
- if(pDM_FatTable->MainCRC32_Fail_Cnt<=5)
- pDM_FatTable->MainCRC32_Fail_Cnt=5;
-
- if(pDM_FatTable->AuxCRC32_Fail_Cnt<=5)
- pDM_FatTable->AuxCRC32_Fail_Cnt=5;
-
- if(pDM_FatTable->MainCRC32_Ok_Cnt >pDM_FatTable->MainCRC32_Fail_Cnt )
- Main_above1=TRUE;
-
- if(pDM_FatTable->AuxCRC32_Ok_Cnt >pDM_FatTable->AuxCRC32_Fail_Cnt )
- Aux_above1=TRUE;
-
- if(Main_above1==TRUE && Aux_above1==FALSE)
- {
- Force_antenna=TRUE;
- pDM_FatTable->TargetAnt_CRC32=MAIN_ANT;
- }
- else if(Main_above1==FALSE && Aux_above1==TRUE)
- {
- Force_antenna=TRUE;
- pDM_FatTable->TargetAnt_CRC32=AUX_ANT;
- }
- else if(Main_above1==TRUE && Aux_above1==TRUE)
- {
- Main_CRC_utility=((pDM_FatTable->MainCRC32_Ok_Cnt)<<7)/pDM_FatTable->MainCRC32_Fail_Cnt;
- Aux_CRC_utility=((pDM_FatTable->AuxCRC32_Ok_Cnt)<<7)/pDM_FatTable->AuxCRC32_Fail_Cnt;
- pDM_FatTable->TargetAnt_CRC32 = (Main_CRC_utility==Aux_CRC_utility)?(pDM_FatTable->pre_TargetAnt_enhance):((Main_CRC_utility>=Aux_CRC_utility)?MAIN_ANT:AUX_ANT);
-
- if(Main_CRC_utility!=0 && Aux_CRC_utility!=0)
- {
- if(Main_CRC_utility>=Aux_CRC_utility)
- utility_ratio=(Main_CRC_utility<<1)/Aux_CRC_utility;
+ if (fat_tab->main_crc32_fail_cnt <= 5)
+ fat_tab->main_crc32_fail_cnt = 5;
+
+ if (fat_tab->aux_crc32_fail_cnt <= 5)
+ fat_tab->aux_crc32_fail_cnt = 5;
+
+ if (fat_tab->main_crc32_ok_cnt > fat_tab->main_crc32_fail_cnt)
+ main_above1 = true;
+
+ if (fat_tab->aux_crc32_ok_cnt > fat_tab->aux_crc32_fail_cnt)
+ aux_above1 = true;
+
+ if (main_above1 == true && aux_above1 == false) {
+ force_antenna = true;
+ fat_tab->target_ant_crc32 = MAIN_ANT;
+ } else if (main_above1 == false && aux_above1 == true) {
+ force_antenna = true;
+ fat_tab->target_ant_crc32 = AUX_ANT;
+ } else if (main_above1 == true && aux_above1 == true) {
+ main_crc_utility = ((fat_tab->main_crc32_ok_cnt) << 7) / fat_tab->main_crc32_fail_cnt;
+ aux_crc_utility = ((fat_tab->aux_crc32_ok_cnt) << 7) / fat_tab->aux_crc32_fail_cnt;
+ fat_tab->target_ant_crc32 = (main_crc_utility == aux_crc_utility) ? (fat_tab->pre_target_ant_enhance) : ((main_crc_utility >= aux_crc_utility) ? MAIN_ANT : AUX_ANT);
+
+ if (main_crc_utility != 0 && aux_crc_utility != 0) {
+ if (main_crc_utility >= aux_crc_utility)
+ utility_ratio = (main_crc_utility << 1) / aux_crc_utility;
else
- utility_ratio=(Aux_CRC_utility<<1)/Main_CRC_utility;
+ utility_ratio = (aux_crc_utility << 1) / main_crc_utility;
}
- }
- else if(Main_above1==FALSE && Aux_above1==FALSE)
- {
- if(pDM_FatTable->MainCRC32_Ok_Cnt==0)
- pDM_FatTable->MainCRC32_Ok_Cnt=1;
- if(pDM_FatTable->AuxCRC32_Ok_Cnt==0)
- pDM_FatTable->AuxCRC32_Ok_Cnt=1;
-
- Main_CRC_utility=((pDM_FatTable->MainCRC32_Fail_Cnt)<<7)/pDM_FatTable->MainCRC32_Ok_Cnt;
- Aux_CRC_utility=((pDM_FatTable->AuxCRC32_Fail_Cnt)<<7)/pDM_FatTable->AuxCRC32_Ok_Cnt;
- pDM_FatTable->TargetAnt_CRC32 = (Main_CRC_utility==Aux_CRC_utility)?(pDM_FatTable->pre_TargetAnt_enhance):((Main_CRC_utility<=Aux_CRC_utility)?MAIN_ANT:AUX_ANT);
-
- if(Main_CRC_utility!=0 && Aux_CRC_utility!=0)
- {
- if(Main_CRC_utility>=Aux_CRC_utility)
- utility_ratio=(Main_CRC_utility<<1)/(Aux_CRC_utility);
+ } else if (main_above1 == false && aux_above1 == false) {
+ if (fat_tab->main_crc32_ok_cnt == 0)
+ fat_tab->main_crc32_ok_cnt = 1;
+ if (fat_tab->aux_crc32_ok_cnt == 0)
+ fat_tab->aux_crc32_ok_cnt = 1;
+
+ main_crc_utility = ((fat_tab->main_crc32_fail_cnt) << 7) / fat_tab->main_crc32_ok_cnt;
+ aux_crc_utility = ((fat_tab->aux_crc32_fail_cnt) << 7) / fat_tab->aux_crc32_ok_cnt;
+ fat_tab->target_ant_crc32 = (main_crc_utility == aux_crc_utility) ? (fat_tab->pre_target_ant_enhance) : ((main_crc_utility <= aux_crc_utility) ? MAIN_ANT : AUX_ANT);
+
+ if (main_crc_utility != 0 && aux_crc_utility != 0) {
+ if (main_crc_utility >= aux_crc_utility)
+ utility_ratio = (main_crc_utility << 1) / (aux_crc_utility);
else
- utility_ratio=(Aux_CRC_utility<<1)/(Main_CRC_utility);
+ utility_ratio = (aux_crc_utility << 1) / (main_crc_utility);
}
}
}
- ODM_SetMACReg(pDM_Odm, 0x608, BIT8, 0);//NOT Accept CRC32 Error packets.
-
- //3 [EVM statistic]
- Main_EVM = (pDM_FatTable->MainAntEVM_Cnt[i]!=0)?(pDM_FatTable->MainAntEVM_Sum[i]/pDM_FatTable->MainAntEVM_Cnt[i]):0;
- Aux_EVM = (pDM_FatTable->AuxAntEVM_Cnt[i]!=0)?(pDM_FatTable->AuxAntEVM_Sum[i]/pDM_FatTable->AuxAntEVM_Cnt[i]):0;
- pDM_FatTable->TargetAnt_EVM = (Main_EVM==Aux_EVM)?(pDM_FatTable->pre_TargetAnt_enhance):((Main_EVM>=Aux_EVM)?MAIN_ANT:AUX_ANT);
+ odm_set_mac_reg(dm, 0x608, BIT(8), 0);/* NOT Accept CRC32 Error packets. */
+ PHYDM_DBG(dm, DBG_ANT_DIV, "MAIN_CRC: Ok=((%d)), Fail = ((%d)), Utility = ((%d))\n", fat_tab->main_crc32_ok_cnt, fat_tab->main_crc32_fail_cnt, main_crc_utility);
+ PHYDM_DBG(dm, DBG_ANT_DIV, "AUX__CRC: Ok=((%d)), Fail = ((%d)), Utility = ((%d))\n", fat_tab->aux_crc32_ok_cnt, fat_tab->aux_crc32_fail_cnt, aux_crc_utility);
+ PHYDM_DBG(dm, DBG_ANT_DIV, "***1.TargetAnt_CRC32 = ((%s))\n", (fat_tab->target_ant_crc32 == MAIN_ANT)?"MAIN_ANT":"AUX_ANT");
+
+ /* 3 [EVM statistic] */
+ /*1SS EVM*/
+ main_1ss_evm = (fat_tab->main_ant_evm_cnt[i] != 0) ? (fat_tab->main_ant_evm_sum[i] / fat_tab->main_ant_evm_cnt[i]) : 0;
+ aux_1ss_evm = (fat_tab->aux_ant_evm_cnt[i] != 0) ? (fat_tab->aux_ant_evm_sum[i] / fat_tab->aux_ant_evm_cnt[i]) : 0;
+ target_ant_evm_1ss = (main_1ss_evm == aux_1ss_evm) ? (fat_tab->pre_target_ant_enhance) : ((main_1ss_evm >= aux_1ss_evm) ? MAIN_ANT : AUX_ANT);
+
+ PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Main1ss_EVM= (( %d ))\n", fat_tab->main_ant_evm_cnt[i], main_1ss_evm);
+ PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Aux_1ss_EVM = (( %d ))\n", fat_tab->main_ant_evm_cnt[i], aux_1ss_evm);
+
+ /*2SS EVM*/
+ main_2ss_evm[0] = (fat_tab->main_ant_evm_2ss_cnt[i] != 0) ? (fat_tab->main_ant_evm_2ss_sum[i][0] / fat_tab->main_ant_evm_2ss_cnt[i]) : 0;
+ main_2ss_evm[1] = (fat_tab->main_ant_evm_2ss_cnt[i] != 0) ? (fat_tab->main_ant_evm_2ss_sum[i][1] / fat_tab->main_ant_evm_2ss_cnt[i]) : 0;
+ main_2ss_evm_sum = main_2ss_evm[0] + main_2ss_evm[1];
+
+ aux_2ss_evm[0] = (fat_tab->aux_ant_evm_2ss_cnt[i] != 0) ? (fat_tab->aux_ant_evm_2ss_sum[i][0] / fat_tab->aux_ant_evm_2ss_cnt[i]) : 0;
+ aux_2ss_evm[1] = (fat_tab->aux_ant_evm_2ss_cnt[i] != 0) ? (fat_tab->aux_ant_evm_2ss_sum[i][1] / fat_tab->aux_ant_evm_2ss_cnt[i]) : 0;
+ aux_2ss_evm_sum = aux_2ss_evm[0] + aux_2ss_evm[1];
+
+ target_ant_evm_2ss = (main_2ss_evm_sum == aux_2ss_evm_sum) ? (fat_tab->pre_target_ant_enhance) : ((main_2ss_evm_sum >= aux_2ss_evm_sum) ? MAIN_ANT : AUX_ANT);
+
+ PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Main2ss_EVM{A,B,Sum} = {%d, %d, %d}\n",
+ fat_tab->main_ant_evm_2ss_cnt[i], main_2ss_evm[0], main_2ss_evm[1], main_2ss_evm_sum);
+ PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Aux_2ss_EVM{A,B,Sum} = {%d, %d, %d}\n",
+ fat_tab->aux_ant_evm_2ss_cnt[i], aux_2ss_evm[0], aux_2ss_evm[1], aux_2ss_evm_sum);
+
+ if ((main_2ss_evm_sum + aux_2ss_evm_sum) != 0) {
+ decision_evm_ss = 2;
+ main_evm = main_2ss_evm_sum;
+ aux_evm = aux_2ss_evm_sum;
+ fat_tab->target_ant_evm = target_ant_evm_2ss;
+ } else {
+ decision_evm_ss = 1;
+ main_evm = main_1ss_evm;
+ aux_evm = aux_1ss_evm;
+ fat_tab->target_ant_evm = target_ant_evm_1ss;
+ }
- if((Main_EVM==0 || Aux_EVM==0))
- diff_EVM=0;
- else if(Main_EVM>=Aux_EVM)
- diff_EVM=Main_EVM-Aux_EVM;
+ if ((main_evm == 0 || aux_evm == 0))
+ diff_EVM = 100;
+ else if (main_evm >= aux_evm)
+ diff_EVM = main_evm - aux_evm;
else
- diff_EVM=Aux_EVM-Main_EVM;
-
- //2 [ Decision state ]
- if (pDM_FatTable->TargetAnt_EVM == pDM_FatTable->TargetAnt_CRC32) {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Decision Type 1, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM));
-
- if ((utility_ratio < 2 && Force_antenna == FALSE) && diff_EVM <= 30)
- pDM_FatTable->TargetAnt_enhance = pDM_FatTable->pre_TargetAnt_enhance;
+ diff_EVM = aux_evm - main_evm;
+
+ PHYDM_DBG(dm, DBG_ANT_DIV, "***2.TargetAnt_EVM((%d-ss)) = ((%s))\n", decision_evm_ss, (fat_tab->target_ant_evm == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
+
+
+ //3 [TP statistic]
+ antdiv_tp_main_avg = (fat_tab->antdiv_tp_main_cnt != 0) ? (fat_tab->antdiv_tp_main / fat_tab->antdiv_tp_main_cnt) : 0;
+ antdiv_tp_aux_avg = (fat_tab->antdiv_tp_aux_cnt != 0) ? (fat_tab->antdiv_tp_aux / fat_tab->antdiv_tp_aux_cnt) : 0;
+ fat_tab->target_ant_tp = (antdiv_tp_main_avg == antdiv_tp_aux_avg) ? (fat_tab->pre_target_ant_enhance) : ((antdiv_tp_main_avg >= antdiv_tp_aux_avg) ? MAIN_ANT : AUX_ANT);
+
+ PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Main_TP = ((%d))\n", fat_tab->antdiv_tp_main_cnt, antdiv_tp_main_avg);
+ PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Aux_TP = ((%d))\n", fat_tab->antdiv_tp_aux_cnt, antdiv_tp_aux_avg);
+ PHYDM_DBG(dm, DBG_ANT_DIV, "***3.TargetAnt_TP = ((%s))\n", (fat_tab->target_ant_tp == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
+
+ /*Reset TP Method */
+ fat_tab->antdiv_tp_main = 0;
+ fat_tab->antdiv_tp_aux = 0;
+ fat_tab->antdiv_tp_main_cnt = 0;
+ fat_tab->antdiv_tp_aux_cnt = 0;
+
+ /* 2 [ Decision state ] */
+ if (fat_tab->target_ant_evm == fat_tab->target_ant_crc32) {
+ PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 1, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM);
+
+ if ((utility_ratio < 2 && force_antenna == false) && diff_EVM <= 30)
+ fat_tab->target_ant_enhance = fat_tab->pre_target_ant_enhance;
else
- pDM_FatTable->TargetAnt_enhance = pDM_FatTable->TargetAnt_EVM;
- } else if ((diff_EVM <= 50 && (utility_ratio > 4 && Force_antenna == FALSE)) || (Force_antenna == TRUE)) {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Decision Type 2, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM));
- pDM_FatTable->TargetAnt_enhance = pDM_FatTable->TargetAnt_CRC32;
- } else if (diff_EVM >= 100) {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Decision Type 3, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM));
- pDM_FatTable->TargetAnt_enhance = pDM_FatTable->TargetAnt_EVM;
- } else if (utility_ratio >= 6 && Force_antenna == FALSE) {
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Decision Type 4, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM));
- pDM_FatTable->TargetAnt_enhance = pDM_FatTable->TargetAnt_CRC32;
+ fat_tab->target_ant_enhance = fat_tab->target_ant_evm;
+ }
+ #if 0
+ else if ((diff_EVM <= 50 && (utility_ratio > 4 && force_antenna == false)) || (force_antenna == true)) {
+ PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 2, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM);
+ fat_tab->target_ant_enhance = fat_tab->target_ant_crc32;
+ }
+ #endif
+ else if (diff_EVM >= 20) {
+ PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 3, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM);
+ fat_tab->target_ant_enhance = fat_tab->target_ant_evm;
+ } else if (utility_ratio >= 6 && force_antenna == false) {
+ PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 4, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM);
+ fat_tab->target_ant_enhance = fat_tab->target_ant_crc32;
} else {
-
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Decision Type 5, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM));
-
- if (Force_antenna == TRUE)
- score_CRC = 3;
- else if (utility_ratio >= 3) /*>0.5*/
+ PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 5, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM);
+
+ if (force_antenna == true)
score_CRC = 2;
- else if (utility_ratio >= 2) /*>1*/
+ else if (utility_ratio >= 5) /*>2.5*/
+ score_CRC = 2;
+ else if (utility_ratio >= 4) /*>2*/
score_CRC = 1;
else
score_CRC = 0;
-
- if (diff_EVM >= 100)
+
+ if (diff_EVM >= 15)
+ score_EVM = 3;
+ else if (diff_EVM >= 10)
score_EVM = 2;
- else if (diff_EVM >= 50)
+ else if (diff_EVM >= 5)
score_EVM = 1;
else
score_EVM = 0;
if (score_CRC > score_EVM)
- pDM_FatTable->TargetAnt_enhance = pDM_FatTable->TargetAnt_CRC32;
+ fat_tab->target_ant_enhance = fat_tab->target_ant_crc32;
else if (score_CRC < score_EVM)
- pDM_FatTable->TargetAnt_enhance = pDM_FatTable->TargetAnt_EVM;
+ fat_tab->target_ant_enhance = fat_tab->target_ant_evm;
else
- pDM_FatTable->TargetAnt_enhance = pDM_FatTable->pre_TargetAnt_enhance;
- }
- pDM_FatTable->pre_TargetAnt_enhance=pDM_FatTable->TargetAnt_enhance;
-
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : MainEVM_Cnt = (( %d )) , Main_EVM= (( %d )) \n",i, pDM_FatTable->MainAntEVM_Cnt[i], Main_EVM));
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : AuxEVM_Cnt = (( %d )) , Aux_EVM = (( %d )) \n" ,i, pDM_FatTable->AuxAntEVM_Cnt[i] , Aux_EVM));
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** TargetAnt_EVM = (( %s ))\n", ( pDM_FatTable->TargetAnt_EVM ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("M_CRC_Ok = (( %d )) , M_CRC_Fail = (( %d )), Main_CRC_utility = (( %d )) \n" , pDM_FatTable->MainCRC32_Ok_Cnt, pDM_FatTable->MainCRC32_Fail_Cnt,Main_CRC_utility));
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("A_CRC_Ok = (( %d )) , A_CRC_Fail = (( %d )), Aux_CRC_utility = (( %d )) \n" , pDM_FatTable->AuxCRC32_Ok_Cnt, pDM_FatTable->AuxCRC32_Fail_Cnt,Aux_CRC_utility));
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** TargetAnt_CRC32 = (( %s ))\n", ( pDM_FatTable->TargetAnt_CRC32 ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("****** TargetAnt_enhance = (( %s ))******\n", ( pDM_FatTable->TargetAnt_enhance ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
-
-
+ fat_tab->target_ant_enhance = fat_tab->pre_target_ant_enhance;
+ }
+ fat_tab->pre_target_ant_enhance = fat_tab->target_ant_enhance;
+
+ PHYDM_DBG(dm, DBG_ANT_DIV, "*** 4.TargetAnt_enhance = (( %s ))******\n", (fat_tab->target_ant_enhance == MAIN_ANT)?"MAIN_ANT":"AUX_ANT");
+
+
}
+ } else { /* RSSI< = evm_rssi_th_low */
+ PHYDM_DBG(dm, DBG_ANT_DIV, "[